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BpfBuilder

Struct BpfBuilder 

Source
pub struct BpfBuilder {
    clang: ClangInfo,
    cflags: Vec<String>,
    out_dir: PathBuf,
    sources: BTreeSet<String>,
    intf_input_output: Option<(String, String)>,
    skel_input_name: Option<(String, String)>,
}
Expand description

§Build helpers for sched_ext schedulers with Rust userspace component

This is to be used from build.rs of a cargo project which implements a sched_ext scheduler with C BPF component and Rust userspace component. BpfBuilder provides everything necessary to build the BPF component and generate Rust bindings. BpfBuilder provides the following.

  1. vmlinux.h and other common BPF header files

All sched_ext BPF implementations require vmlinux.h and many make use of common constructs such as user_exit_info. BpfBuilder makes these headers available when compiling BPF source code and generating bindings for it. The included headers can be browsed at https://github.com/sched-ext/scx/tree/main/scheds/include.

These headers can be superseded using environment variables which will be discussed later.

  1. Header bindings using bindgen

If enabled with .enable_intf(), the input .h file is processed by bindgen to generate Rust bindings. This is useful in establishing shared constants and data types between the BPF and user components.

Note that the types generated with bindgen are different from the types used by the BPF skeleton even when they are the same types in BPF. This is a source of ugliness and we are hoping to address it by improving libbpf-cargo in the future.

  1. BPF compilation and generation of the skeleton and its bindings

If enabled with .enable_skel(), the input .bpf.c file is compiled and its skeleton and bindings are generated using libbpf-cargo.

§An Example

This section shows how BpfBuilder can be used in an example project. For a concrete example, take a look at scx_rusty.

A minimal source tree using all features would look like the following:

scx_hello_world
|-- Cargo.toml
|-- build.rs
\-- src
    |-- main.rs
    |-- bpf_intf.rs
    |-- bpf_skel.rs
    \-- bpf
        |-- intf.h
        \-- main.c

The following three files would contain the actual implementation:

  • src/main.rs: Rust userspace component which loads the BPF blob and interacts it using the generated bindings.

  • src/bpf/intf.h: C header file defining constants and structs that will be used by both the BPF and userspace components.

  • src/bpf/main.c: C source code implementing the BPF component - including struct sched_ext_ops.

And then there are boilerplates to generate the bindings and make them available as modules to main.rs.

  • Cargo.toml: Includes scx_cargo in the [build-dependencies] section.

  • build.rs: Uses scx_cargo::BpfBuilder to build and generate bindings for the BPF component. For this project, it can look like the following.

fn main() {
    scx_cargo::BpfBuilder::new()
        .unwrap()
        .enable_intf("src/bpf/intf.h", "bpf_intf.rs")
        .enable_skel("src/bpf/main.bpf.c", "bpf")
        .build()
        .unwrap();
}
  • bpf_intf.rs: Import the bindings generated by bindgen into a module. Above, we told .enable_intf() to generate the bindings into bpf_intf.rs, so the file would look like the following. The allow directives are useful if the header is including vmlinux.h.
#![allow(non_upper_case_globals)]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![allow(dead_code)]

include!(concat!(env!("OUT_DIR"), "/bpf_intf.rs"));
  • bpf_skel.rs: Import the BPF skeleton bindings generated by libbpf-cargo into a module. Above, we told .enable_skel() to use the skeleton name bpf, so the file would look like the following.
include!(concat!(env!("OUT_DIR"), "/bpf_skel.rs"));

§Compiler Flags and Environment Variables

BPF being its own CPU architecture and independent runtime environment, build environment and steps are already rather complex. The need to interface between two different languages - C and Rust - adds further complexities. BpfBuilder automates most of the process. The determined build environment is recorded in the build.rs output and can be obtained with a command like the following:

$ grep '^scx_utils:clang=' target/release/build/scx_rusty-*/output

While the automatic settings should work most of the time, there can be times when overriding them is necessary. The following environment variables can be used to customize the build environment.

  • BPF_CLANG: The clang command to use. (Default: clang)

  • BPF_CFLAGS: Compiler flags to use when building BPF source code. If specified, the flags from this variable are the only flags passed to the compiler. BpfBuilder won’t generate any flags including -I flags for the common header files and other CFLAGS related variables are ignored.

  • BPF_BASE_CFLAGS: Override the non-include part of cflags.

  • BPF_EXTRA_CFLAGS_PRE_INCL: Add cflags before the automatic include search path options. Header files in the search paths added by this variable will supersede the automatic ones.

  • BPF_EXTRA_CFLAGS_POST_INCL: Add cflags after the automatic include search path options. Header paths added by this variable will be searched only if the target header file can’t be found in the automatic header paths.

  • RUSTFLAGS: This is a generic cargo flag and can be useful for specifying extra linker flags.

A common case for using the above flags is using the latest libbpf from the kernel tree. Let’s say the kernel tree is at $KERNEL and libbpf. The following builds libbpf shipped with the kernel:

$ cd $KERNEL
$ make -C tools/bpf/bpftool

To link the scheduler against the resulting libbpf:

$ env BPF_EXTRA_CFLAGS_POST_INCL=$KERNEL/tools/bpf/bpftool/libbpf/include \
  RUSTFLAGS="-C link-args=-lelf -C link-args=-lz -C link-args=-lzstd \
  -L$KERNEL/tools/bpf/bpftool/libbpf" cargo build --release

Fields§

§clang: ClangInfo§cflags: Vec<String>§out_dir: PathBuf§sources: BTreeSet<String>§intf_input_output: Option<(String, String)>§skel_input_name: Option<(String, String)>

Implementations§

Source§

impl BpfBuilder

Source

const BPF_H_TAR: &'static [u8] = b"./\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000040755\x000001751\x000001751\x0000000000000\x0015172171634\x000007410\x005\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00bpf_arena_spin_lock.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000033454\x0015172171634\x000013410\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00// SPDX-License-Identifier: GPL-2.0\n/* Copyright (c) 2025 Meta Platforms, Inc. and affiliates. */\n#ifndef BPF_ARENA_SPIN_LOCK_H\n#define BPF_ARENA_SPIN_LOCK_H\n\n#ifdef __BPF__\n\n#include <vmlinux.h>\n#include <bpf/bpf_helpers.h>\n\n#include \"bpf_arena_common.bpf.h\"\n#include \"bpf_atomic.h\"\n\n#define arch_mcs_spin_lock_contended_label(l, label) smp_cond_load_acquire_label(l, VAL, label)\n#define arch_mcs_spin_unlock_contended(l) smp_store_release((l), 1)\n\n#define EBUSY 16\n#define EOPNOTSUPP 95\n#define ETIMEDOUT 110\n\nextern unsigned long CONFIG_NR_CPUS __kconfig;\n\n#endif\n\n/*\n * Typically, we\'d just rely on the definition in vmlinux.h for qspinlock, but\n * PowerPC overrides the definition to define lock->val as u32 instead of\n * atomic_t, leading to compilation errors. Import a local definition below so\n * that we don\'t depend on the vmlinux.h version.\n */\n\nstruct __qspinlock {\n\tunion {\n\t\tatomic_t val;\n#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n\t\tstruct {\n\t\t\tu8 locked;\n\t\t\tu8 pending;\n\t\t};\n\t\tstruct {\n\t\t\tu16 locked_pending;\n\t\t\tu16 tail;\n\t\t};\n#else\n\t\tstruct {\n\t\t\tu16 tail;\n\t\t\tu16 locked_pending;\n\t\t};\n\t\tstruct {\n\t\t\tu8 reserved[2];\n\t\t\tu8 pending;\n\t\t\tu8 locked;\n\t\t};\n#endif\n\t};\n};\n\n#define arena_spinlock_t struct __qspinlock\n/* FIXME: Using typedef causes CO-RE relocation error */\n/* typedef struct qspinlock arena_spinlock_t; */\n\nstruct arena_mcs_spinlock {\n\tstruct arena_mcs_spinlock __arena *next;\n\tint locked;\n\tint count;\n};\n\nstruct arena_qnode {\n\tstruct arena_mcs_spinlock mcs;\n};\n\n#define _Q_MAX_NODES\t\t4\n#define _Q_PENDING_LOOPS\t1\n\n/*\n * Bitfields in the atomic value:\n *\n * 0- 7: locked byte\n * 8: pending\n * 9-15: not used\n * 16-17: tail index\n * 18-31: tail cpu (+1)\n */\n#define _Q_MAX_CPUS\t\t16384\n\n#define\t_Q_SET_MASK(type)\t(((1U << _Q_ ## type ## _BITS) - 1)\\\n\t\t\t\t << _Q_ ## type ## _OFFSET)\n#define _Q_LOCKED_OFFSET\t0\n#define _Q_LOCKED_BITS\t\t8\n#define _Q_LOCKED_MASK\t\t_Q_SET_MASK(LOCKED)\n\n#define _Q_PENDING_OFFSET\t(_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)\n#define _Q_PENDING_BITS\t\t8\n#define _Q_PENDING_MASK\t\t_Q_SET_MASK(PENDING)\n\n#define _Q_TAIL_IDX_OFFSET\t(_Q_PENDING_OFFSET + _Q_PENDING_BITS)\n#define _Q_TAIL_IDX_BITS\t2\n#define _Q_TAIL_IDX_MASK\t_Q_SET_MASK(TAIL_IDX)\n\n#define _Q_TAIL_CPU_OFFSET\t(_Q_TAIL_IDX_OFFSET + _Q_TAIL_IDX_BITS)\n#define _Q_TAIL_CPU_BITS\t(32 - _Q_TAIL_CPU_OFFSET)\n#define _Q_TAIL_CPU_MASK\t_Q_SET_MASK(TAIL_CPU)\n\n#define _Q_TAIL_OFFSET\t\t_Q_TAIL_IDX_OFFSET\n#define _Q_TAIL_MASK\t\t(_Q_TAIL_IDX_MASK | _Q_TAIL_CPU_MASK)\n\n#define _Q_LOCKED_VAL\t\t(1U << _Q_LOCKED_OFFSET)\n#define _Q_PENDING_VAL\t\t(1U << _Q_PENDING_OFFSET)\n\n#ifndef likely\n#define likely(x) __builtin_expect(!!(x), 1)\n#endif\n#ifndef unlikely\n#define unlikely(x) __builtin_expect(!!(x), 0)\n#endif\n\nstatic struct arena_qnode __arena qnodes[_Q_MAX_CPUS][_Q_MAX_NODES];\n\n#ifdef __BPF__\n\nstatic inline u32 encode_tail(int cpu, int idx)\n{\n\tu32 tail;\n\n\ttail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;\n\ttail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */\n\n\treturn tail;\n}\n\nstatic inline struct arena_mcs_spinlock __arena *decode_tail(u32 tail)\n{\n\tu32 cpu = (tail >> _Q_TAIL_CPU_OFFSET) - 1;\n\tu32 idx = (tail & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;\n\n\treturn &qnodes[cpu][idx].mcs;\n}\n\nstatic inline\nstruct arena_mcs_spinlock __arena *grab_mcs_node(struct arena_mcs_spinlock __arena *base, int idx)\n{\n\treturn &((struct arena_qnode __arena *)base + idx)->mcs;\n}\n\n#define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK)\n\n/**\n * xchg_tail - Put in the new queue tail code word & retrieve previous one\n * @lock : Pointer to queued spinlock structure\n * @tail : The new queue tail code word\n * Return: The previous queue tail code word\n *\n * xchg(lock, tail)\n *\n * p,*,* -> n,*,* ; prev = xchg(lock, node)\n */\nstatic __always_inline u32 xchg_tail(arena_spinlock_t __arena *lock, u32 tail)\n{\n\tu32 old, new;\n\n\told = atomic_read(&lock->val);\n\tdo {\n\t\tnew = (old & _Q_LOCKED_PENDING_MASK) | tail;\n\t\t/*\n\t\t * We can use relaxed semantics since the caller ensures that\n\t\t * the MCS node is properly initialized before updating the\n\t\t * tail.\n\t\t */\n\t\t/* These loops are not expected to stall, but we still need to\n\t\t * prove to the verifier they will terminate eventually.\n\t\t */\n\t\tcond_break_label(out);\n\t} while (!atomic_try_cmpxchg_relaxed(&lock->val, &old, new));\n\n\treturn old;\nout:\n\tbpf_printk(\"RUNTIME ERROR: %s unexpected cond_break exit!!!\", __func__);\n\treturn old;\n}\n\n/**\n * clear_pending - clear the pending bit.\n * @lock: Pointer to queued spinlock structure\n *\n * *,1,* -> *,0,*\n */\nstatic __always_inline void clear_pending(arena_spinlock_t __arena *lock)\n{\n\t(void)WRITE_ONCE(lock->pending, 0);\n}\n\n/**\n * clear_pending_set_locked - take ownership and clear the pending bit.\n * @lock: Pointer to queued spinlock structure\n *\n * *,1,0 -> *,0,1\n *\n * Lock stealing is not allowed if this function is used.\n */\nstatic __always_inline void clear_pending_set_locked(arena_spinlock_t __arena *lock)\n{\n\t(void)WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL);\n}\n\n/**\n * set_locked - Set the lock bit and own the lock\n * @lock: Pointer to queued spinlock structure\n *\n * *,*,0 -> *,0,1\n */\nstatic __always_inline void set_locked(arena_spinlock_t __arena *lock)\n{\n\t(void)WRITE_ONCE(lock->locked, _Q_LOCKED_VAL);\n}\n\nstatic __always_inline\nu32 arena_fetch_set_pending_acquire(arena_spinlock_t __arena *lock)\n{\n\tu32 old, new;\n\n\told = atomic_read(&lock->val);\n\tdo {\n\t\tnew = old | _Q_PENDING_VAL;\n\t\t/*\n\t\t * These loops are not expected to stall, but we still need to\n\t\t * prove to the verifier they will terminate eventually.\n\t\t */\n\t\tcond_break_label(out);\n\t} while (!atomic_try_cmpxchg_acquire(&lock->val, &old, new));\n\n\treturn old;\nout:\n\tbpf_printk(\"RUNTIME ERROR: %s unexpected cond_break exit!!!\", __func__);\n\treturn old;\n}\n\n/**\n * arena_spin_trylock - try to acquire the queued spinlock\n * @lock : Pointer to queued spinlock structure\n * Return: 1 if lock acquired, 0 if failed\n */\nstatic __always_inline int arena_spin_trylock(arena_spinlock_t __arena *lock)\n{\n\tint val = atomic_read(&lock->val);\n\n\tif (unlikely(val))\n\t\treturn 0;\n\n\treturn likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL));\n}\n\n__noinline __weak\nint arena_spin_lock_slowpath(arena_spinlock_t __arena __arg_arena *lock, u32 val)\n{\n\tstruct arena_mcs_spinlock __arena *prev, *next, *node0, *node;\n\tint ret = -ETIMEDOUT;\n\tu32 old, tail;\n\tint idx;\n\n\t/*\n\t * Wait for in-progress pending->locked hand-overs with a bounded\n\t * number of spins so that we guarantee forward progress.\n\t *\n\t * 0,1,0 -> 0,0,1\n\t */\n\tif (val == _Q_PENDING_VAL) {\n\t\tint cnt = _Q_PENDING_LOOPS;\n\t\tval = atomic_cond_read_relaxed_label(&lock->val,\n\t\t\t\t\t\t (VAL != _Q_PENDING_VAL) || !cnt--,\n\t\t\t\t\t\t release_err);\n\t}\n\n\t/*\n\t * If we observe any contention; queue.\n\t */\n\tif (val & ~_Q_LOCKED_MASK)\n\t\tgoto queue;\n\n\t/*\n\t * trylock || pending\n\t *\n\t * 0,0,* -> 0,1,* -> 0,0,1 pending, trylock\n\t */\n\tval = arena_fetch_set_pending_acquire(lock);\n\n\t/*\n\t * If we observe contention, there is a concurrent locker.\n\t *\n\t * Undo and queue; our setting of PENDING might have made the\n\t * n,0,0 -> 0,0,0 transition fail and it will now be waiting\n\t * on @next to become !NULL.\n\t */\n\tif (unlikely(val & ~_Q_LOCKED_MASK)) {\n\n\t\t/* Undo PENDING if we set it. */\n\t\tif (!(val & _Q_PENDING_MASK))\n\t\t\tclear_pending(lock);\n\n\t\tgoto queue;\n\t}\n\n\t/*\n\t * We\'re pending, wait for the owner to go away.\n\t *\n\t * 0,1,1 -> *,1,0\n\t *\n\t * this wait loop must be a load-acquire such that we match the\n\t * store-release that clears the locked bit and create lock\n\t * sequentiality; this is because not all\n\t * clear_pending_set_locked() implementations imply full\n\t * barriers.\n\t */\n\tif (val & _Q_LOCKED_MASK)\n\t\t(void)smp_cond_load_acquire_label(&lock->locked, !VAL, release_err);\n\n\t/*\n\t * take ownership and clear the pending bit.\n\t *\n\t * 0,1,0 -> 0,0,1\n\t */\n\tclear_pending_set_locked(lock);\n\treturn 0;\n\n\t/*\n\t * End of pending bit optimistic spinning and beginning of MCS\n\t * queuing.\n\t */\nqueue:\n\tnode0 = &(qnodes[bpf_get_smp_processor_id()])[0].mcs;\n\tidx = node0->count++;\n\ttail = encode_tail(bpf_get_smp_processor_id(), idx);\n\n\t/*\n\t * 4 nodes are allocated based on the assumption that there will not be\n\t * nested NMIs taking spinlocks. That may not be true in some\n\t * architectures even though the chance of needing more than 4 nodes\n\t * will still be extremely unlikely. When that happens, we simply return\n\t * an error. Original qspinlock has a trylock fallback in this case.\n\t */\n\tif (unlikely(idx >= _Q_MAX_NODES)) {\n\t\tret = -EBUSY;\n\t\tgoto release_node_err;\n\t}\n\n\tnode = grab_mcs_node(node0, idx);\n\n\t/*\n\t * Ensure that we increment the head node->count before initialising\n\t * the actual node. If the compiler is kind enough to reorder these\n\t * stores, then an IRQ could overwrite our assignments.\n\t */\n\tbarrier();\n\n\tnode->locked = 0;\n\tnode->next = NULL;\n\n\t/*\n\t * We touched a (possibly) cold cacheline in the per-cpu queue node;\n\t * attempt the trylock once more in the hope someone let go while we\n\t * weren\'t watching.\n\t */\n\tif (arena_spin_trylock(lock))\n\t\tgoto release;\n\n\t/*\n\t * Ensure that the initialisation of @node is complete before we\n\t * publish the updated tail via xchg_tail() and potentially link\n\t * @node into the waitqueue via WRITE_ONCE(prev->next, node) below.\n\t */\n\tsmp_wmb();\n\n\t/*\n\t * Publish the updated tail.\n\t * We have already touched the queueing cacheline; don\'t bother with\n\t * pending stuff.\n\t *\n\t * p,*,* -> n,*,*\n\t */\n\told = xchg_tail(lock, tail);\n\tnext = NULL;\n\n\t/*\n\t * if there was a previous node; link it and wait until reaching the\n\t * head of the waitqueue.\n\t */\n\tif (old & _Q_TAIL_MASK) {\n\t\tprev = decode_tail(old);\n\n\t\t/* Link @node into the waitqueue. */\n\t\t(void)WRITE_ONCE(prev->next, node);\n\n\t\t(void)arch_mcs_spin_lock_contended_label(&node->locked, release_node_err);\n\n\t\t/*\n\t\t * While waiting for the MCS lock, the next pointer may have\n\t\t * been set by another lock waiter. We cannot prefetch here\n\t\t * due to lack of equivalent instruction in BPF ISA.\n\t\t */\n\t\tnext = READ_ONCE(node->next);\n\t}\n\n\t/*\n\t * we\'re at the head of the waitqueue, wait for the owner & pending to\n\t * go away.\n\t *\n\t * *,x,y -> *,0,0\n\t *\n\t * this wait loop must use a load-acquire such that we match the\n\t * store-release that clears the locked bit and create lock\n\t * sequentiality; this is because the set_locked() function below\n\t * does not imply a full barrier.\n\t */\n\tval = atomic_cond_read_acquire_label(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK),\n\t\t\t\t\t release_node_err);\n\n\t/*\n\t * claim the lock:\n\t *\n\t * n,0,0 -> 0,0,1 : lock, uncontended\n\t * *,*,0 -> *,*,1 : lock, contended\n\t *\n\t * If the queue head is the only one in the queue (lock value == tail)\n\t * and nobody is pending, clear the tail code and grab the lock.\n\t * Otherwise, we only need to grab the lock.\n\t */\n\n\t/*\n\t * In the PV case we might already have _Q_LOCKED_VAL set, because\n\t * of lock stealing; therefore we must also allow:\n\t *\n\t * n,0,1 -> 0,0,1\n\t *\n\t * Note: at this point: (val & _Q_PENDING_MASK) == 0, because of the\n\t * above wait condition, therefore any concurrent setting of\n\t * PENDING will make the uncontended transition fail.\n\t */\n\tif ((val & _Q_TAIL_MASK) == tail) {\n\t\tif (atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL))\n\t\t\tgoto release; /* No contention */\n\t}\n\n\t/*\n\t * Either somebody is queued behind us or _Q_PENDING_VAL got set\n\t * which will then detect the remaining tail and queue behind us\n\t * ensuring we\'ll see a @next.\n\t */\n\tset_locked(lock);\n\n\t/*\n\t * contended path; wait for next if not observed yet, release.\n\t */\n\tif (!next)\n\t\tnext = smp_cond_load_relaxed_label(&node->next, (VAL), release_node_err);\n\n\tarch_mcs_spin_unlock_contended(&next->locked);\n\nrelease:;\n\t/*\n\t * release the node\n\t *\n\t * Doing a normal dec vs this_cpu_dec is fine. An upper context always\n\t * decrements count it incremented before returning, thus we\'re fine.\n\t * For contexts interrupting us, they either observe our dec or not.\n\t * Just ensure the compiler doesn\'t reorder this statement, as a\n\t * this_cpu_dec implicitly implied that.\n\t */\n\tbarrier();\n\tnode0->count--;\n\treturn 0;\nrelease_node_err:\n\tbarrier();\n\tnode0->count--;\n\tgoto release_err;\nrelease_err:\n\treturn ret;\n}\n\n/**\n * arena_spin_lock - acquire a queued spinlock\n * @lock: Pointer to queued spinlock structure\n *\n * On error, returned value will be negative.\n * On success, zero is returned.\n *\n * The return value _must_ be tested against zero for success,\n * instead of checking it against negative, for passing the\n * BPF verifier.\n *\n * The user should do:\n *\tif (arena_spin_lock(...) != 0) // failure\n *\t\tor\n *\tif (arena_spin_lock(...) == 0) // success\n *\t\tor\n *\tif (arena_spin_lock(...)) // failure\n *\t\tor\n *\tif (!arena_spin_lock(...)) // success\n * instead of:\n *\tif (arena_spin_lock(...) < 0) // failure\n *\n * The return value can still be inspected later.\n */\nstatic __always_inline int arena_spin_lock(arena_spinlock_t __arena *lock)\n{\n\tint val = 0;\n\n\tif (CONFIG_NR_CPUS > _Q_MAX_CPUS)\n\t\treturn -EOPNOTSUPP;\n\n\tbpf_preempt_disable();\n\tif (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL)))\n\t\treturn 0;\n\n\tval = arena_spin_lock_slowpath(lock, val);\n\t/* FIXME: bpf_assert_range(-MAX_ERRNO, 0) once we have it working for all cases. */\n\tif (val)\n\t\tbpf_preempt_enable();\n\treturn val;\n}\n\n/**\n * arena_spin_unlock - release a queued spinlock\n * @lock : Pointer to queued spinlock structure\n */\nstatic __always_inline void arena_spin_unlock(arena_spinlock_t __arena *lock)\n{\n\t/*\n\t * unlock() needs release semantics:\n\t */\n\tsmp_store_release(&lock->locked, 0);\n\tbpf_preempt_enable();\n}\n\n#define arena_spin_lock_irqsave(lock, flags) \\\n\t({ \\\n\t\tint __ret; \\\n\t\tbpf_local_irq_save(&(flags)); \\\n\t\t__ret = arena_spin_lock((lock)); \\\n\t\tif (__ret) \\\n\t\t\tbpf_local_irq_restore(&(flags)); \\\n\t\t(__ret); \\\n\t})\n\n#define arena_spin_unlock_irqrestore(lock, flags) \\\n\t({ \\\n\t\tarena_spin_unlock((lock)); \\\n\t\tbpf_local_irq_restore(&(flags)); \\\n\t})\n\n#endif /* __BPF__ */\n\n#endif /* BPF_ARENA_SPIN_LOCK_H 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Define struct user_exit_info which is shared between BPF and userspace parts\n * to communicate exit status and other information.\n *\n * Copyright (c) 2022 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2022 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2022 David Vernet <dvernet@meta.com>\n */\n#ifndef __USER_EXIT_INFO_COMMON_H\n#define __USER_EXIT_INFO_COMMON_H\n\n#ifdef LSP\n#include \"../vmlinux.h\"\n#endif\n\nenum uei_sizes {\n\tUEI_REASON_LEN\t\t= 128,\n\tUEI_MSG_LEN\t\t= 1024,\n\tUEI_DUMP_DFL_LEN\t= 32768,\n};\n\nstruct user_exit_info {\n\tint\t\tkind;\n\ts64\t\texit_code;\n\tchar\t\treason[UEI_REASON_LEN];\n\tchar\t\tmsg[UEI_MSG_LEN];\n};\n\n#endif /* __USER_EXIT_INFO_COMMON_H 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Convenience macros for getting/setting struct scx_enums instances.\n *\n * Copyright (c) 2024 Meta Platforms, Inc. and affiliates.\n */\n#ifndef __SCX_ENUMS_BPF_H\n#define __SCX_ENUMS_BPF_H\n\n#include \"enums.autogen.bpf.h\"\n\n#endif /* __SCX_ENUMS_BPF_H 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */\n#ifndef __TASK_LOCAL_DATA_BPF_H\n#define __TASK_LOCAL_DATA_BPF_H\n\n/*\n * Task local data is a library that facilitates sharing per-task data\n * between user space and bpf programs.\n *\n *\n * USAGE\n *\n * A TLD, an entry of data in task local data, first needs to be created by the\n * user space. This is done by calling user space API, TLD_DEFINE_KEY() or\n * tld_create_key(), with the name of the TLD and the size.\n *\n * TLD_DEFINE_KEY(prio, \"priority\", sizeof(int));\n *\n * or\n *\n * void func_call(...) {\n * tld_key_t prio, in_cs;\n *\n * prio = tld_create_key(\"priority\", sizeof(int));\n * in_cs = tld_create_key(\"in_critical_section\", sizeof(bool));\n * ...\n *\n * A key associated with the TLD, which has an opaque type tld_key_t, will be\n * initialized or returned. It can be used to get a pointer to the TLD in the\n * user space by calling tld_get_data().\n *\n * In a bpf program, tld_object_init() first needs to be called to initialized a\n * tld_object on the stack. Then, TLDs can be accessed by calling tld_get_data().\n * The API will try to fetch the key by the name and use it to locate the data.\n * A pointer to the TLD will be returned. It also caches the key in a task local\n * storage map, tld_key_map, whose value type, struct tld_keys, must be defined\n * by the developer.\n *\n * struct tld_keys {\n * tld_key_t prio;\n * tld_key_t in_cs;\n * };\n *\n * SEC(\"struct_ops\")\n * void prog(struct task_struct task, ...)\n * {\n * struct tld_object tld_obj;\n * int err, *p;\n *\n * err = tld_object_init(task, &tld_obj);\n * if (err)\n * return;\n *\n * p = tld_get_data(&tld_obj, prio, \"priority\", sizeof(int));\n * if (p)\n * // do something depending on *p\n */\n#include <errno.h>\n#include <bpf/bpf_helpers.h>\n\n#define TLD_ROUND_MASK(x, y) ((__typeof__(x))((y) - 1))\n#define TLD_ROUND_UP(x, y) ((((x) - 1) | TLD_ROUND_MASK(x, y)) + 1)\n\n#define TLD_MAX_DATA_CNT (__PAGE_SIZE / sizeof(struct tld_metadata) - 1)\n\n#ifndef TLD_NAME_LEN\n#define TLD_NAME_LEN 62\n#endif\n\n#ifndef TLD_KEY_MAP_CREATE_RETRY\n#define TLD_KEY_MAP_CREATE_RETRY 10\n#endif\n\ntypedef struct {\n\t__s16 off;\n} tld_key_t;\n\nstruct tld_metadata {\n\tchar name[TLD_NAME_LEN];\n\t__u16 size;\n};\n\nstruct tld_meta_u {\n\t__u16 cnt;\n\t__u16 size;\n\tstruct tld_metadata metadata[TLD_MAX_DATA_CNT];\n};\n\nstruct tld_data_u {\n\t__u64 start; /* offset of tld_data_u->data in a page */\n\tchar data[__PAGE_SIZE - sizeof(__u64)];\n};\n\nstruct tld_map_value {\n\tstruct tld_data_u __uptr *data;\n\tstruct tld_meta_u __uptr *meta;\n};\n\ntypedef struct tld_uptr_dummy {\n\tstruct tld_data_u data[0];\n\tstruct tld_meta_u meta[0];\n} *tld_uptr_dummy_t;\n\nstruct tld_object {\n\tstruct tld_map_value *data_map;\n\tstruct tld_keys *key_map;\n\t/*\n\t * Force the compiler to generate the actual definition of tld_meta_u\n\t * and tld_data_u in BTF. Without it, tld_meta_u and u_tld_data will\n\t * be BTF_KIND_FWD.\n\t */\n\ttld_uptr_dummy_t dummy[0];\n};\n\n/*\n * Map value of tld_key_map for caching keys. Must be defined by the developer.\n * Members should be tld_key_t and passed to the 3rd argument of tld_fetch_key().\n */\nstruct tld_keys;\n\nstruct {\n\t__uint(type, BPF_MAP_TYPE_TASK_STORAGE);\n\t__uint(map_flags, BPF_F_NO_PREALLOC);\n\t__type(key, int);\n\t__type(value, struct tld_map_value);\n} tld_data_map SEC(\".maps\");\n\nstruct {\n\t__uint(type, BPF_MAP_TYPE_TASK_STORAGE);\n\t__uint(map_flags, BPF_F_NO_PREALLOC);\n\t__type(key, int);\n\t__type(value, struct tld_keys);\n} tld_key_map SEC(\".maps\");\n\n/**\n * tld_object_init() - Initialize a tld_object.\n *\n * @task: The task_struct of the target task\n * @tld_obj: A pointer to a tld_object to be initialized\n *\n * Return 0 on success; -ENODATA if the user space did not initialize task local data\n * for the current task through tld_get_data(); -ENOMEM if the creation of tld_key_map\n * fails\n */\n__attribute__((unused))\nstatic int tld_object_init(struct task_struct *task, struct tld_object *tld_obj)\n{\n\tint i;\n\n\ttld_obj->data_map = bpf_task_storage_get(&tld_data_map, task, 0, 0);\n\tif (!tld_obj->data_map)\n\t\treturn -ENODATA;\n\n\tbpf_for(i, 0, TLD_KEY_MAP_CREATE_RETRY) {\n\t\ttld_obj->key_map = bpf_task_storage_get(&tld_key_map, task, 0,\n\t\t\t\t\t\t\tBPF_LOCAL_STORAGE_GET_F_CREATE);\n\t\tif (likely(tld_obj->key_map))\n\t\t\tbreak;\n\t}\n\tif (!tld_obj->key_map)\n\t\treturn -ENOMEM;\n\n\treturn 0;\n}\n\n/*\n * Return the offset of TLD if @name is found. Otherwise, return the current TLD count\n * using the nonpositive range so that the next tld_get_data() can skip fetching key if\n * no new TLD is added or start comparing name from the first newly added TLD.\n */\n__attribute__((unused))\nstatic int __tld_fetch_key(struct tld_object *tld_obj, const char *name, int i_start)\n{\n\tstruct tld_metadata *metadata;\n\tint i, cnt, start, off = 0;\n\n\tif (!tld_obj->data_map || !tld_obj->data_map->data || !tld_obj->data_map->meta)\n\t\treturn 0;\n\n\tstart = tld_obj->data_map->data->start;\n\tcnt = tld_obj->data_map->meta->cnt;\n\tmetadata = tld_obj->data_map->meta->metadata;\n\n\tbpf_for(i, 0, cnt) {\n\t\tif (i >= TLD_MAX_DATA_CNT)\n\t\t\tbreak;\n\n\t\tif (i >= i_start && !bpf_strncmp(metadata[i].name, TLD_NAME_LEN, name))\n\t\t\treturn start + off;\n\n\t\toff += TLD_ROUND_UP(metadata[i].size, 8);\n\t}\n\n\treturn -cnt;\n}\n\n/**\n * tld_get_data() - Retrieve a pointer to the TLD associated with the name.\n *\n * @tld_obj: A pointer to a valid tld_object initialized by tld_object_init()\n * @key: The cached key of the TLD in tld_key_map\n * @name: The name of the key associated with a TLD\n * @size: The size of the TLD. Must be a known constant value\n *\n * Return a pointer to the TLD associated with @name; NULL if not found or @size is too\n * big. @key is used to cache the key if the TLD is found to speed up subsequent calls.\n * It should be defined as an member of tld_keys of tld_key_t type by the developer.\n */\n#define tld_get_data(tld_obj, key, name, size)\t\t\t\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\t\t\\\n\t\tvoid *data = NULL, *_data = (tld_obj)->data_map->data;\t\t\t\\\n\t\tlong off = (tld_obj)->key_map->key.off;\t\t\t\t\t\\\n\t\tint cnt;\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif (likely(_data)) {\t\t\t\t\t\t\t\\\n\t\t\tif (likely(off > 0)) {\t\t\t\t\t\t\\\n\t\t\t\tbarrier_var(off);\t\t\t\t\t\\\n\t\t\t\tif (likely(off < __PAGE_SIZE - size))\t\t\t\\\n\t\t\t\t\tdata = _data + off;\t\t\t\t\\\n\t\t\t} else {\t\t\t\t\t\t\t\\\n\t\t\t\tcnt = -(off);\t\t\t\t\t\t\\\n\t\t\t\tif (likely((tld_obj)->data_map->meta) &&\t\t\\\n\t\t\t\t cnt < (tld_obj)->data_map->meta->cnt) {\t\t\\\n\t\t\t\t\toff = __tld_fetch_key(tld_obj, name, cnt);\t\\\n\t\t\t\t\t(tld_obj)->key_map->key.off = off;\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\tif (likely(off < __PAGE_SIZE - size)) {\t\t\\\n\t\t\t\t\t\tbarrier_var(off);\t\t\t\\\n\t\t\t\t\t\tif (off > 0)\t\t\t\t\\\n\t\t\t\t\t\t\tdata = _data + off;\t\t\\\n\t\t\t\t\t}\t\t\t\t\t\t\\\n\t\t\t\t}\t\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\\\n\t\tdata;\t\t\t\t\t\t\t\t\t\\\n\t})\n\n#endif\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/compat.bpf.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000035666\x0015172171634\x000012267\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (c) 2024 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2024 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2024 David Vernet <dvernet@meta.com>\n */\n#ifndef __SCX_COMPAT_BPF_H\n#define __SCX_COMPAT_BPF_H\n\n#define __COMPAT_ENUM_OR_ZERO(__type, __ent)\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\t__type __ret = 0;\t\t\t\t\t\t\t\\\n\tif (bpf_core_enum_value_exists(__type, __ent))\t\t\t\t\\\n\t\t__ret = __ent;\t\t\t\t\t\t\t\\\n\t__ret;\t\t\t\t\t\t\t\t\t\\\n})\n\n/* v6.12: 819513666966 (\"sched_ext: Add cgroup support\") */\nstruct cgroup *scx_bpf_task_cgroup___new(struct task_struct *p) __ksym __weak;\n\n#define scx_bpf_task_cgroup(p)\t\t\t\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_task_cgroup___new) ?\t\t\t\t\\\n\t scx_bpf_task_cgroup___new((p)) : NULL)\n\n/*\n * v6.13: The verb `dispatch` was too overloaded and confusing. kfuncs are\n * renamed to unload the verb.\n *\n * scx_bpf_dispatch_from_dsq() and friends were added during v6.12 by\n * 4c30f5ce4f7a (\"sched_ext: Implement scx_bpf_dispatch[_vtime]_from_dsq()\").\n *\n * v7.1: scx_bpf_dsq_move_to_local___v2() to add @enq_flags.\n */\nbool scx_bpf_dsq_move_to_local___v2(u64 dsq_id, u64 enq_flags) __ksym __weak;\nbool scx_bpf_dsq_move_to_local___v1(u64 dsq_id) __ksym __weak;\nvoid scx_bpf_dsq_move_set_slice___new(struct bpf_iter_scx_dsq *it__iter, u64 slice) __ksym __weak;\nvoid scx_bpf_dsq_move_set_vtime___new(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __ksym __weak;\nbool scx_bpf_dsq_move___new(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __ksym __weak;\nbool scx_bpf_dsq_move_vtime___new(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __ksym __weak;\n\nbool scx_bpf_consume___old(u64 dsq_id) __ksym __weak;\nvoid scx_bpf_dispatch_from_dsq_set_slice___old(struct bpf_iter_scx_dsq *it__iter, u64 slice) __ksym __weak;\nvoid scx_bpf_dispatch_from_dsq_set_vtime___old(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __ksym __weak;\nbool scx_bpf_dispatch_from_dsq___old(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __ksym __weak;\nbool scx_bpf_dispatch_vtime_from_dsq___old(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __ksym __weak;\n\n#define scx_bpf_dsq_move_to_local(dsq_id, enq_flags)\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_dsq_move_to_local___v2) ?\t\t\t\\\n\t scx_bpf_dsq_move_to_local___v2((dsq_id), (enq_flags)) :\t\t\\\n\t (bpf_ksym_exists(scx_bpf_dsq_move_to_local___v1) ?\t\t\t\\\n\t scx_bpf_dsq_move_to_local___v1((dsq_id)) :\t\t\t\t\\\n\t scx_bpf_consume___old((dsq_id))))\n\n#define scx_bpf_dsq_move_set_slice(it__iter, slice)\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_dsq_move_set_slice___new) ?\t\t\t\\\n\t scx_bpf_dsq_move_set_slice___new((it__iter), (slice)) :\t\t\\\n\t (bpf_ksym_exists(scx_bpf_dispatch_from_dsq_set_slice___old) ?\t\t\\\n\t scx_bpf_dispatch_from_dsq_set_slice___old((it__iter), (slice)) :\t\\\n\t (void)0))\n\n#define scx_bpf_dsq_move_set_vtime(it__iter, vtime)\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_dsq_move_set_vtime___new) ?\t\t\t\\\n\t scx_bpf_dsq_move_set_vtime___new((it__iter), (vtime)) :\t\t\\\n\t (bpf_ksym_exists(scx_bpf_dispatch_from_dsq_set_vtime___old) ?\t\t\\\n\t scx_bpf_dispatch_from_dsq_set_vtime___old((it__iter), (vtime)) :\t\\\n\t (void)0))\n\n#define scx_bpf_dsq_move(it__iter, p, dsq_id, enq_flags)\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_dsq_move___new) ?\t\t\t\t\\\n\t scx_bpf_dsq_move___new((it__iter), (p), (dsq_id), (enq_flags)) :\t\\\n\t (bpf_ksym_exists(scx_bpf_dispatch_from_dsq___old) ?\t\t\t\\\n\t scx_bpf_dispatch_from_dsq___old((it__iter), (p), (dsq_id), (enq_flags)) : \\\n\t false))\n\n#define scx_bpf_dsq_move_vtime(it__iter, p, dsq_id, enq_flags)\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_dsq_move_vtime___new) ?\t\t\t\\\n\t scx_bpf_dsq_move_vtime___new((it__iter), (p), (dsq_id), (enq_flags)) : \\\n\t (bpf_ksym_exists(scx_bpf_dispatch_vtime_from_dsq___old) ?\t\t\\\n\t scx_bpf_dispatch_vtime_from_dsq___old((it__iter), (p), (dsq_id), (enq_flags)) : \\\n\t false))\n\n/*\n * v6.15: 950ad93df2fc (\"bpf: add kfunc for populating cpumask bits\")\n *\n * Compat macro will be dropped on v6.19 release.\n */\nint bpf_cpumask_populate(struct cpumask *dst, void *src, size_t src__sz) __ksym __weak;\n\n#define __COMPAT_bpf_cpumask_populate(cpumask, src, size__sz)\t\t\\\n\t(bpf_ksym_exists(bpf_cpumask_populate) ?\t\t\t\\\n\t (bpf_cpumask_populate(cpumask, src, size__sz)) : -EOPNOTSUPP)\n\n/*\n * v6.19: Introduce lockless peek API for user DSQs.\n *\n * Preserve the following macro until v6.21.\n */\nstatic inline struct task_struct *__COMPAT_scx_bpf_dsq_peek(u64 dsq_id)\n{\n\tstruct task_struct *p = NULL;\n\tstruct bpf_iter_scx_dsq it;\n\n\tif (bpf_ksym_exists(scx_bpf_dsq_peek))\n\t\treturn scx_bpf_dsq_peek(dsq_id);\n\tif (!bpf_iter_scx_dsq_new(&it, dsq_id, 0))\n\t\tp = bpf_iter_scx_dsq_next(&it);\n\tbpf_iter_scx_dsq_destroy(&it);\n\treturn p;\n}\n\n/**\n * __COMPAT_is_enq_cpu_selected - Test if SCX_ENQ_CPU_SELECTED is on\n * in a compatible way. We will preserve this __COMPAT helper until v6.16.\n *\n * @enq_flags: enqueue flags from ops.enqueue()\n *\n * Return: True if SCX_ENQ_CPU_SELECTED is turned on in @enq_flags\n */\nstatic inline bool __COMPAT_is_enq_cpu_selected(u64 enq_flags)\n{\n#ifdef HAVE_SCX_ENQ_CPU_SELECTED\n\t/*\n\t * This is the case that a BPF code compiled against vmlinux.h\n\t * where the enum SCX_ENQ_CPU_SELECTED exists.\n\t */\n\n\t/*\n\t * We should temporarily suspend the macro expansion of\n\t * \'SCX_ENQ_CPU_SELECTED\'. This avoids \'SCX_ENQ_CPU_SELECTED\' being\n\t * rewritten to \'__SCX_ENQ_CPU_SELECTED\' when \'SCX_ENQ_CPU_SELECTED\'\n\t * is defined in \'scripts/gen_enums.py\'.\n\t */\n#pragma push_macro(\"SCX_ENQ_CPU_SELECTED\")\n#undef SCX_ENQ_CPU_SELECTED\n\tu64 flag;\n\n\t/*\n\t * When the kernel did not have SCX_ENQ_CPU_SELECTED,\n\t * select_task_rq_scx() has never been skipped. Thus, this case\n\t * should be considered that the CPU has already been selected.\n\t */\n\tif (!bpf_core_enum_value_exists(enum scx_enq_flags,\n\t\t\t\t\tSCX_ENQ_CPU_SELECTED))\n\t\treturn true;\n\n\tflag = bpf_core_enum_value(enum scx_enq_flags, SCX_ENQ_CPU_SELECTED);\n\treturn enq_flags & flag;\n\n\t/*\n\t * Once done, resume the macro expansion of \'SCX_ENQ_CPU_SELECTED\'.\n\t */\n#pragma pop_macro(\"SCX_ENQ_CPU_SELECTED\")\n#else\n\t/*\n\t * This is the case that a BPF code compiled against vmlinux.h\n\t * where the enum SCX_ENQ_CPU_SELECTED does NOT exist.\n\t */\n\treturn true;\n#endif /* HAVE_SCX_ENQ_CPU_SELECTED */\n}\n\n\n#define scx_bpf_now()\t\t\t\t\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_now) ?\t\t\t\t\t\t\\\n\t scx_bpf_now() :\t\t\t\t\t\t\t\\\n\t bpf_ktime_get_ns())\n\n/*\n * v6.15: Introduce event counters.\n *\n * Preserve the following macro until v6.17.\n */\n#define __COMPAT_scx_bpf_events(events, size)\t\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_events) ?\t\t\t\t\t\\\n\t scx_bpf_events(events, size) : ({}))\n\n/*\n * v6.15: Introduce NUMA-aware kfuncs to operate with per-node idle\n * cpumasks.\n *\n * Preserve the following __COMPAT_scx_*_node macros until v6.17.\n */\n#define __COMPAT_scx_bpf_nr_node_ids()\t\t\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_nr_node_ids) ?\t\t\t\t\t\\\n\t scx_bpf_nr_node_ids() : 1U)\n\n#define __COMPAT_scx_bpf_cpu_node(cpu)\t\t\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_cpu_node) ?\t\t\t\t\t\\\n\t scx_bpf_cpu_node(cpu) : 0)\n\n#define __COMPAT_scx_bpf_get_idle_cpumask_node(node)\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_get_idle_cpumask_node) ?\t\t\t\\\n\t scx_bpf_get_idle_cpumask_node(node) :\t\t\t\t\t\\\n\t scx_bpf_get_idle_cpumask())\t\t\t\t\t\t\\\n\n#define __COMPAT_scx_bpf_get_idle_smtmask_node(node)\t\t\t\t\\\n\t(bpf_ksym_exists(scx_bpf_get_idle_smtmask_node) ?\t\t\t\\\n\t scx_bpf_get_idle_smtmask_node(node) :\t\t\t\t\t\\\n\t scx_bpf_get_idle_smtmask())\n\n#define __COMPAT_scx_bpf_pick_idle_cpu_node(cpus_allowed, node, flags)\t\t\\\n\t(bpf_ksym_exists(scx_bpf_pick_idle_cpu_node) ?\t\t\t\t\\\n\t scx_bpf_pick_idle_cpu_node(cpus_allowed, node, flags) :\t\t\\\n\t scx_bpf_pick_idle_cpu(cpus_allowed, flags))\n\n#define __COMPAT_scx_bpf_pick_any_cpu_node(cpus_allowed, node, flags)\t\t\\\n\t(bpf_ksym_exists(scx_bpf_pick_any_cpu_node) ?\t\t\t\t\\\n\t scx_bpf_pick_any_cpu_node(cpus_allowed, node, flags) :\t\t\t\\\n\t scx_bpf_pick_any_cpu(cpus_allowed, flags))\n\n/*\n * v6.18: Add a helper to retrieve the current task running on a CPU.\n *\n * Keep this helper available until v6.20 for compatibility.\n */\nstatic inline struct task_struct *__COMPAT_scx_bpf_cpu_curr(int cpu)\n{\n\tstruct rq *rq;\n\n\tif (bpf_ksym_exists(scx_bpf_cpu_curr))\n\t\treturn scx_bpf_cpu_curr(cpu);\n\n\trq = scx_bpf_cpu_rq(cpu);\n\n\treturn rq ? rq->curr : NULL;\n}\n\n/*\n * v6.19: To work around BPF maximum parameter limit, the following kfuncs are\n * replaced with variants that pack scalar arguments in a struct. Wrappers are\n * provided to maintain source compatibility.\n *\n * v6.13: scx_bpf_dsq_insert_vtime() renaming is also handled here. See the\n * block on dispatch renaming above for more details.\n *\n * The kernel will carry the compat variants until v6.23 to maintain binary\n * compatibility. After v6.23 release, remove the compat handling and move the\n * wrappers to common.bpf.h.\n */\ns32 scx_bpf_select_cpu_and___compat(struct task_struct *p, s32 prev_cpu, u64 wake_flags,\n\t\t\t\t const struct cpumask *cpus_allowed, u64 flags) __ksym __weak;\nvoid scx_bpf_dispatch_vtime___compat(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __ksym __weak;\nvoid scx_bpf_dsq_insert_vtime___compat(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __ksym __weak;\n\n/**\n * scx_bpf_select_cpu_and - Pick an idle CPU usable by task @p\n * @p: task_struct to select a CPU for\n * @prev_cpu: CPU @p was on previously\n * @wake_flags: %SCX_WAKE_* flags\n * @cpus_allowed: cpumask of allowed CPUs\n * @flags: %SCX_PICK_IDLE* flags\n *\n * Inline wrapper that packs scalar arguments into a struct and calls\n * __scx_bpf_select_cpu_and(). See __scx_bpf_select_cpu_and() for details.\n */\nstatic inline s32\nscx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags,\n\t\t const struct cpumask *cpus_allowed, u64 flags)\n{\n\tif (bpf_core_type_exists(struct scx_bpf_select_cpu_and_args)) {\n\t\tstruct scx_bpf_select_cpu_and_args args = {\n\t\t\t.prev_cpu = prev_cpu,\n\t\t\t.wake_flags = wake_flags,\n\t\t\t.flags = flags,\n\t\t};\n\n\t\treturn __scx_bpf_select_cpu_and(p, cpus_allowed, &args);\n\t} else {\n\t\treturn scx_bpf_select_cpu_and___compat(p, prev_cpu, wake_flags,\n\t\t\t\t\t\t cpus_allowed, flags);\n\t}\n}\n\n/*\n * scx_bpf_select_cpu_and() is now an inline wrapper. Use this instead of\n * bpf_ksym_exists(scx_bpf_select_cpu_and) to test availability.\n */\n#define __COMPAT_HAS_scx_bpf_select_cpu_and\t\t\t\t\\\n\t(bpf_core_type_exists(struct scx_bpf_select_cpu_and_args) ||\t\\\n\t bpf_ksym_exists(scx_bpf_select_cpu_and___compat))\n\n/**\n * scx_bpf_dsq_insert_vtime - Insert a task into the vtime priority queue of a DSQ\n * @p: task_struct to insert\n * @dsq_id: DSQ to insert into\n * @slice: duration @p can run for in nsecs, 0 to keep the current value\n * @vtime: @p\'s ordering inside the vtime-sorted queue of the target DSQ\n * @enq_flags: SCX_ENQ_*\n *\n * Inline wrapper that packs scalar arguments into a struct and calls\n * __scx_bpf_dsq_insert_vtime(). See __scx_bpf_dsq_insert_vtime() for details.\n */\nstatic inline bool\nscx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime,\n\t\t\t u64 enq_flags)\n{\n\tif (bpf_core_type_exists(struct scx_bpf_dsq_insert_vtime_args)) {\n\t\tstruct scx_bpf_dsq_insert_vtime_args args = {\n\t\t\t.dsq_id = dsq_id,\n\t\t\t.slice = slice,\n\t\t\t.vtime = vtime,\n\t\t\t.enq_flags = enq_flags,\n\t\t};\n\n\t\treturn __scx_bpf_dsq_insert_vtime(p, &args);\n\t} else if (bpf_ksym_exists(scx_bpf_dsq_insert_vtime___compat)) {\n\t\tscx_bpf_dsq_insert_vtime___compat(p, dsq_id, slice, vtime,\n\t\t\t\t\t\t enq_flags);\n\t\treturn true;\n\t} else {\n\t\tscx_bpf_dispatch_vtime___compat(p, dsq_id, slice, vtime,\n\t\t\t\t\t\tenq_flags);\n\t\treturn true;\n\t}\n}\n\n/*\n * v6.19: scx_bpf_dsq_insert() now returns bool instead of void. Move\n * scx_bpf_dsq_insert() decl to common.bpf.h and drop compat helper after v6.22.\n * The extra ___compat suffix is to work around libbpf not ignoring __SUFFIX on\n * kernel side. The entire suffix can be dropped later.\n *\n * v6.13: scx_bpf_dsq_insert() renaming is also handled here. See the block on\n * dispatch renaming above for more details.\n */\nbool scx_bpf_dsq_insert___v2___compat(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __ksym __weak;\nvoid scx_bpf_dsq_insert___v1(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __ksym __weak;\nvoid scx_bpf_dispatch___compat(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __ksym __weak;\n\nstatic inline bool\nscx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags)\n{\n\tif (bpf_ksym_exists(scx_bpf_dsq_insert___v2___compat)) {\n\t\treturn scx_bpf_dsq_insert___v2___compat(p, dsq_id, slice, enq_flags);\n\t} else if (bpf_ksym_exists(scx_bpf_dsq_insert___v1)) {\n\t\tscx_bpf_dsq_insert___v1(p, dsq_id, slice, enq_flags);\n\t\treturn true;\n\t} else {\n\t\tscx_bpf_dispatch___compat(p, dsq_id, slice, enq_flags);\n\t\treturn true;\n\t}\n}\n\n/*\n * v6.19: scx_bpf_task_set_slice() and scx_bpf_task_set_dsq_vtime() added to for\n * sub-sched authority checks. Drop the wrappers and move the decls to\n * common.bpf.h after v6.22.\n */\nbool scx_bpf_task_set_slice___new(struct task_struct *p, u64 slice) __ksym __weak;\nbool scx_bpf_task_set_dsq_vtime___new(struct task_struct *p, u64 vtime) __ksym __weak;\n\nstatic inline void scx_bpf_task_set_slice(struct task_struct *p, u64 slice)\n{\n\tif (bpf_ksym_exists(scx_bpf_task_set_slice___new))\n\t\tscx_bpf_task_set_slice___new(p, slice);\n\telse\n\t\tp->scx.slice = slice;\n}\n\nstatic inline void scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime)\n{\n\tif (bpf_ksym_exists(scx_bpf_task_set_dsq_vtime___new))\n\t\tscx_bpf_task_set_dsq_vtime___new(p, vtime);\n\telse\n\t\tp->scx.dsq_vtime = vtime;\n}\n\n/*\n * v6.19: The new void variant can be called from anywhere while the older v1\n * variant can only be called from ops.cpu_release(). The double ___ prefixes on\n * the v2 variant need to be removed once libbpf is updated to ignore ___ prefix\n * on kernel side. Drop the wrapper and move the decl to common.bpf.h after\n * v6.22.\n */\nu32 scx_bpf_reenqueue_local___v1(void) __ksym __weak;\nvoid scx_bpf_reenqueue_local___v2___compat(void) __ksym __weak;\n\nstatic inline bool __COMPAT_scx_bpf_reenqueue_local_from_anywhere(void)\n{\n\treturn bpf_ksym_exists(scx_bpf_reenqueue_local___v2___compat);\n}\n\nstatic inline void scx_bpf_reenqueue_local(void)\n{\n\tif (__COMPAT_scx_bpf_reenqueue_local_from_anywhere())\n\t\tscx_bpf_reenqueue_local___v2___compat();\n\telse\n\t\tscx_bpf_reenqueue_local___v1();\n}\n\n/*\n * v6.20: New scx_bpf_dsq_reenq() that allows re-enqueues on more DSQs. This\n * will eventually deprecate scx_bpf_reenqueue_local().\n */\nvoid scx_bpf_dsq_reenq___compat(u64 dsq_id, u64 reenq_flags, const struct bpf_prog_aux *aux__prog) __ksym __weak;\n\nstatic inline bool __COMPAT_has_generic_reenq(void)\n{\n\treturn bpf_ksym_exists(scx_bpf_dsq_reenq___compat);\n}\n\nstatic inline void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags)\n{\n\tif (bpf_ksym_exists(scx_bpf_dsq_reenq___compat))\n\t\tscx_bpf_dsq_reenq___compat(dsq_id, reenq_flags, NULL);\n\telse if (dsq_id == SCX_DSQ_LOCAL && reenq_flags == 0)\n\t\tscx_bpf_reenqueue_local();\n\telse\n\t\tscx_bpf_error(\"kernel too old to reenqueue foreign local or user DSQs\");\n}\n\n/*\n * Define sched_ext_ops. This may be expanded to define multiple variants for\n * backward compatibility. See compat.h::SCX_OPS_LOAD/ATTACH().\n */\n#define SCX_OPS_DEFINE(__name, ...)\t\t\t\t\t\t\\\n\tSEC(\".struct_ops.link\")\t\t\t\t\t\t\t\\\n\tstruct sched_ext_ops __name = {\t\t\t\t\t\t\\\n\t\t__VA_ARGS__,\t\t\t\t\t\t\t\\\n\t};\n\n#endif\t/* __SCX_COMPAT_BPF_H */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/namespace_impl.bpf.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000003512\x0015172171634\x000013742\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (c) 2024 Meta Platforms, Inc. and affiliates.\n */\n#include \"namespace.bpf.h\"\n\n#include <bpf/bpf_core_read.h>\n#include <bpf/bpf_helpers.h>\n\n\n__hidden struct pid* get_task_pid_ptr(const struct task_struct* task,\n\t\t\t\t enum pid_type type)\n{\n\t// Returns the pid pointer of the given task. See get_task_pid_ptr for\n\t// the kernel implementation.\n\treturn (type == PIDTYPE_PID) ? BPF_CORE_READ(task, thread_pid) :\n\t\tBPF_CORE_READ(task, signal, pids[type]);\n}\n\n__hidden struct pid_namespace* get_task_pid_ns(const struct task_struct* task,\n\t\t\t\t\t enum pid_type type)\n{\n\tstruct pid_namespace* ns;\n\tstruct pid* p;\n\tint level;\n\n\t// See kernel function task_active_pid_ns in pid.c which calls into\n\t// ns_of_pid. Returns the pid namespace of the given task.\n\tif (!task)\n\t\ttask = (struct task_struct*)bpf_get_current_task();\n\n\tif (!task)\n\t\treturn NULL;\n\n\tp = get_task_pid_ptr(task, type);\n\tif (!p)\n\t\treturn NULL;\n\n\tlevel = BPF_CORE_READ(p, level);\n\tns = BPF_CORE_READ(p, numbers[level].ns);\n\treturn ns;\n}\n\n__hidden pid_t get_pid_nr_ns(struct pid* pid, struct pid_namespace* ns)\n{\n\tint level, ns_level;\n\tpid_t nr = 0;\n\n\t/* This function implements the kernel equivalent pid_nr_ns in linux/pid.h */\n\tif (!pid || !ns)\n\t\treturn nr;\n\n\tlevel = BPF_CORE_READ(pid, level);\n\tns_level = BPF_CORE_READ(ns, level);\n\tif (ns_level <= level) {\n\t\tstruct upid upid;\n\n\t\tupid = BPF_CORE_READ(pid, numbers[ns_level]);\n\t\tif (upid.ns == ns)\n\t\t\tnr = upid.nr;\n\t}\n\treturn nr;\n}\n\n__hidden pid_t get_task_ns_pid(const struct task_struct* task)\n{\n\tstruct pid_namespace* ns;\n\tstruct pid* p;\n\n\tif (!task)\n\t\ttask = (struct task_struct*)bpf_get_current_task();\n\n\tns = get_task_pid_ns(task, PIDTYPE_TGID);\n\tp = get_task_pid_ptr(task, PIDTYPE_PID);\n\treturn get_pid_nr_ns(p, ns);\n}\n\n__hidden pid_t get_ns_pid(void)\n{\n\treturn get_task_ns_pid(NULL);\n}\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/enums.autogen.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000005423\x0015172171634\x000013012\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/*\n * WARNING: This file is autogenerated from scripts/gen_enums.py. If you would\n * like to access an enum that is currently missing, add it to the script\n * and run it from the root directory to update this file.\n */\n\n#define SCX_ENUM_INIT(skel) do { \\\n\tSCX_ENUM_SET(skel, scx_public_consts, SCX_OPS_NAME_LEN); \\\n\tSCX_ENUM_SET(skel, scx_public_consts, SCX_SLICE_DFL); \\\n\tSCX_ENUM_SET(skel, scx_public_consts, SCX_SLICE_INF); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_ONLINE); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_CAN_STOP_TICK); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_BAL_PENDING); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_BAL_KEEP); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_BYPASSING); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_CLK_VALID); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_IN_WAKEUP); \\\n\tSCX_ENUM_SET(skel, scx_rq_flags, SCX_RQ_IN_BALANCE); \\\n\tSCX_ENUM_SET(skel, scx_dsq_id_flags, SCX_DSQ_FLAG_BUILTIN); \\\n\tSCX_ENUM_SET(skel, scx_dsq_id_flags, SCX_DSQ_FLAG_LOCAL_ON); \\\n\tSCX_ENUM_SET(skel, scx_dsq_id_flags, SCX_DSQ_INVALID); \\\n\tSCX_ENUM_SET(skel, scx_dsq_id_flags, SCX_DSQ_GLOBAL); \\\n\tSCX_ENUM_SET(skel, scx_dsq_id_flags, SCX_DSQ_LOCAL); \\\n\tSCX_ENUM_SET(skel, scx_dsq_id_flags, SCX_DSQ_LOCAL_ON); \\\n\tSCX_ENUM_SET(skel, scx_dsq_id_flags, SCX_DSQ_LOCAL_CPU_MASK); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_QUEUED); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_RESET_RUNNABLE_AT); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_DEQD_FOR_SLEEP); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_SUB_INIT); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_IMMED); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_STATE_SHIFT); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_STATE_BITS); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_STATE_MASK); \\\n\tSCX_ENUM_SET(skel, scx_ent_flags, SCX_TASK_CURSOR); \\\n\tSCX_ENUM_SET(skel, scx_task_state, SCX_TASK_NONE); \\\n\tSCX_ENUM_SET(skel, scx_task_state, SCX_TASK_INIT); \\\n\tSCX_ENUM_SET(skel, scx_task_state, SCX_TASK_READY); \\\n\tSCX_ENUM_SET(skel, scx_task_state, SCX_TASK_ENABLED); \\\n\tSCX_ENUM_SET(skel, scx_task_state, SCX_TASK_NR_STATES); \\\n\tSCX_ENUM_SET(skel, scx_ent_dsq_flags, SCX_TASK_DSQ_ON_PRIQ); \\\n\tSCX_ENUM_SET(skel, scx_kick_flags, SCX_KICK_IDLE); \\\n\tSCX_ENUM_SET(skel, scx_kick_flags, SCX_KICK_PREEMPT); \\\n\tSCX_ENUM_SET(skel, scx_kick_flags, SCX_KICK_WAIT); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_WAKEUP); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_HEAD); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_PREEMPT); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_IMMED); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_REENQ); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_LAST); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_CLEAR_OPSS); \\\n\tSCX_ENUM_SET(skel, scx_enq_flags, SCX_ENQ_DSQ_PRIQ); \\\n\tSCX_ENUM_SET(skel, scx_deq_flags, SCX_DEQ_SCHED_CHANGE); \\\n} while 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BSD-2-Clause) */\n/* Copyright (c) 2024 Meta Platforms, Inc. and affiliates. */\n#pragma once\n\n#ifndef arena_container_of\n#define arena_container_of(ptr, type, member)\t\t\t\\\n\t({\t\t\t\t\t\t\t\\\n\t\tvoid __arena *__mptr = (void __arena *)(ptr);\t\\\n\t\t((type *)(__mptr - offsetof(type, member)));\t\\\n\t})\n#endif\n\n/* Provide the definition of PAGE_SIZE. */\n#include <sys/user.h>\n\n#define __arena\n#define __arg_arena\n#define cast_kern(ptr) /* nop for user space */\n#define cast_user(ptr) /* nop for user space */\nchar __attribute__((weak)) arena[1];\n\n#ifndef offsetof\n#define offsetof(type, member) ((unsigned long)&((type *)0)->member)\n#endif\n\nstatic inline void __arena* bpf_arena_alloc_pages(void *map, void *addr, __u32 page_cnt,\n\t\t\t\t\t\t int node_id, __u64 flags)\n{\n\treturn NULL;\n}\nstatic inline void bpf_arena_free_pages(void *map, void __arena *ptr, __u32 page_cnt)\n{\n}\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/arena_userspace_interrop.bpf.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000001131\x0015172171634\x000016042\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar 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Copyright (c) 2025 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2025 Jake Hillion <jake@hillion.co.uk>\n */\n#ifndef __SCX_ARENA_USERSPACE_INTERROP_H\n#define __SCX_ARENA_USERSPACE_INTERROP_H\n\n#ifndef __arena\n#define __arena\n#endif\n\n#ifndef __KERNEL__\ntypedef unsigned char u8;\ntypedef unsigned int u32;\ntypedef unsigned long long u64;\n#endif\n\nstruct scx_userspace_arena_alloc_pages_args\n{\n\tu32\t\tsz;\n\tvoid __arena\t*ret;\n};\n\nstruct scx_userspace_arena_free_pages_args\n{\n\tvoid __arena\t*addr;\n\tu32\t\tsz;\n};\n\n#endif /* __SCX_ARENA_USERSPACE_INTERROP_H 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (c) 2024 Meta Platforms, Inc. and affiliates.\n */\n#ifndef __SCHED_EXT_NAMESPACE_BPF_H\n#define __SCHED_EXT_NAMESPACE_BPF_H\n\n#ifdef LSP\n#define __bpf__\n#include \"../vmlinux.h\"\n#else\n#include \"vmlinux.h\"\n#endif\n\nstruct pid_namespace* get_task_pid_ns(const struct task_struct* task, enum pid_type);\nstruct pid* get_task_pid_ptr(const struct task_struct* task, enum pid_type type);\npid_t get_task_ns_pid(const struct task_struct* task);\n\npid_t get_pid_nr_ns(struct pid* pid, struct pid_namespace* ns);\npid_t get_ns_pid(void);\n\n#endif /* __SCHED_EXT_NAMESPACE_BPF_H */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/percpu.bpf.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000006363\x0015172171634\x000012272\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (c) 2025 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2025 Daniel Hodges <hodgesd@meta.com>\n */\n#ifndef BPF_PERCPU_H\n#define BPF_PERCPU_H\n\n#ifdef LSP\n#define __bpf__\n#include \"../vmlinux.h\"\n#else\n#include \"vmlinux.h\"\n#endif\n\n#include <bpf/bpf_core_read.h>\n#include <bpf/bpf_helpers.h>\n\n\nextern int sd_llc_size __ksym __weak;\nextern int sd_llc_id __ksym __weak;\nextern int sched_core_priority __ksym __weak;\nextern struct sugov_cpu sugov_cpu __ksym __weak;\nextern struct psi_group_cpu psi_group_cpu __ksym __weak;\nextern struct kernel_stat kernel_stat __ksym __weak;\nextern struct kernel_cpustat kernel_cpustat __ksym __weak;\nextern struct cpufreq_policy* cpufreq_cpu_data __ksym __weak;\nextern struct sched_domain* sd_llc __ksym __weak;\nextern struct vm_event_state vm_event_states __ksym __weak;\n\n\n#define DEFINE_PER_CPU_PTR_FUNC(func_name, type, var_name)\t\\\ntype *func_name(s32 cpu)\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\ttype *ptr;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tif (!&var_name)\t\t\t\t\t\t\\\n\t\treturn NULL;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tptr = bpf_per_cpu_ptr(&var_name, cpu);\t\t\t\\\n\tif (!ptr)\t\t\t\t\t\t\\\n\t\treturn NULL;\t\t\t\t\t\\\n\treturn ptr;\t\t\t\t\t\t\\\n}\n\n\n#define DEFINE_PER_CPU_PTR_PTR_FUNC(func_name, type, per_cpu_var_name)\t\t\\\nstatic __always_inline type func_name(s32 cpu)\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\\\n\ttype *ptr_to_per_cpu_var = bpf_per_cpu_ptr(&per_cpu_var_name, cpu);\t\\\n\t\t\t\t\t\t\t\t\t\t\\\n\tif (!ptr_to_per_cpu_var) \\\n\t\treturn NULL;\t\t\t\t\t\t\t\\\n\treturn *ptr_to_per_cpu_var;\t\t\t\t\t\t\\\n}\n\n\n#define DEFINE_PER_CPU_VAL_FUNC(func_name, type, var_name)\t\\\ntype func_name(s32 cpu) {\t\t\t\t\t\\\n\ttype *ptr;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tif (!&var_name)\t\t\t\t\t\t\\\n\t\treturn -ENOENT;\t\t\t\t\t\\\n\tptr = bpf_per_cpu_ptr(&var_name, cpu);\t\t\t\\\n\tif (!ptr)\t\t\t\t\t\t\\\n\t\treturn -EINVAL;\t\t\t\t\t\\\n\treturn *ptr;\t\t\t\t\t\t\\\n}\n\n#define DEFINE_THIS_CPU_VAL_FUNC(orig_func_name)\t\t\t\\\nstatic inline typeof(orig_func_name(0)) this_##orig_func_name(void) {\t\\\n\treturn orig_func_name(bpf_get_smp_processor_id());\t\t\\\n}\n\n#define DEFINE_THIS_CPU_PTR_FUNC(orig_func_name)\t\t\t\\\nstatic inline typeof(orig_func_name(0)) this_##orig_func_name(void) {\t\\\n\treturn orig_func_name(bpf_get_smp_processor_id());\t\t\\\n}\n\nDEFINE_PER_CPU_VAL_FUNC(cpu_llc_size, int, sd_llc_size)\nDEFINE_PER_CPU_VAL_FUNC(cpu_llc_id, int, sd_llc_id)\nDEFINE_PER_CPU_VAL_FUNC(cpu_priority, int, sched_core_priority)\n\nDEFINE_PER_CPU_PTR_PTR_FUNC(cpu_cpufreq_policy, struct cpufreq_policy*, cpufreq_cpu_data)\nDEFINE_PER_CPU_PTR_PTR_FUNC(cpu_llc_dom, struct sched_domain*, sd_llc)\n\nDEFINE_PER_CPU_PTR_FUNC(cpu_kernel_cpustat, struct kernel_cpustat, kernel_cpustat)\nDEFINE_PER_CPU_PTR_FUNC(cpu_kernel_stat, struct kernel_stat, kernel_stat)\nDEFINE_PER_CPU_PTR_FUNC(cpu_psi_group, struct psi_group_cpu, psi_group_cpu)\nDEFINE_PER_CPU_PTR_FUNC(cpu_sugov, struct sugov_cpu, sugov_cpu)\nDEFINE_PER_CPU_PTR_FUNC(cpu_vm_event_state, struct vm_event_state, vm_event_states)\n\nDEFINE_THIS_CPU_VAL_FUNC(cpu_llc_id)\nDEFINE_THIS_CPU_VAL_FUNC(cpu_llc_size)\nDEFINE_THIS_CPU_VAL_FUNC(cpu_priority)\n\nDEFINE_THIS_CPU_PTR_FUNC(cpu_cpufreq_policy)\nDEFINE_THIS_CPU_PTR_FUNC(cpu_kernel_cpustat)\nDEFINE_THIS_CPU_PTR_FUNC(cpu_kernel_stat)\nDEFINE_THIS_CPU_PTR_FUNC(cpu_psi_group)\nDEFINE_THIS_CPU_PTR_FUNC(cpu_llc_dom)\nDEFINE_THIS_CPU_PTR_FUNC(cpu_sugov)\nDEFINE_THIS_CPU_PTR_FUNC(cpu_vm_event_state)\n\n#endif /* BPF_PERCPU_H */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/common.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000004452\x0015172171634\x000011513\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (c) 2023 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2023 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2023 David Vernet <dvernet@meta.com>\n */\n#ifndef __SCHED_EXT_COMMON_H\n#define __SCHED_EXT_COMMON_H\n\n#ifdef __KERNEL__\n#error \"Should not be included by BPF programs\"\n#endif\n\n#include <stdarg.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdint.h>\n#include <errno.h>\n#include \"enum_defs.autogen.h\"\n\ntypedef uint8_t u8;\ntypedef uint16_t u16;\ntypedef uint32_t u32;\ntypedef uint64_t u64;\ntypedef int8_t s8;\ntypedef int16_t s16;\ntypedef int32_t s32;\ntypedef int64_t s64;\n\n#define SCX_BUG(__fmt, ...)\t\t\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\t\\\n\t\tfprintf(stderr, \"[SCX_BUG] %s:%d\", __FILE__, __LINE__);\t\t\\\n\t\tif (errno)\t\t\t\t\t\t\t\\\n\t\t\tfprintf(stderr, \" (%s)\\n\", strerror(errno));\t\t\\\n\t\telse\t\t\t\t\t\t\t\t\\\n\t\t\tfprintf(stderr, \"\\n\");\t\t\t\t\t\\\n\t\tfprintf(stderr, __fmt __VA_OPT__(,) __VA_ARGS__);\t\t\\\n\t\tfprintf(stderr, \"\\n\");\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\\\n\t\texit(EXIT_FAILURE);\t\t\t\t\t\t\\\n\t} while (0)\n\n#define SCX_BUG_ON(__cond, __fmt, ...)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tif (__cond)\t\t\t\t\t\t\\\n\t\t\tSCX_BUG((__fmt) __VA_OPT__(,) __VA_ARGS__);\t\\\n\t} while (0)\n\n/**\n * RESIZE_ARRAY - Convenience macro for resizing a BPF array\n * @__skel: the skeleton containing the array\n * @elfsec: the data section of the BPF program in which the array exists\n * @arr: the name of the array\n * @n: the desired array element count\n *\n * For BPF arrays declared with RESIZABLE_ARRAY(), this macro performs two\n * operations. It resizes the map which corresponds to the custom data\n * section that contains the target array. As a side effect, the BTF info for\n * the array is adjusted so that the array length is sized to cover the new\n * data section size. The second operation is reassigning the skeleton pointer\n * for that custom data section so that it points to the newly memory mapped\n * region.\n */\n#define RESIZE_ARRAY(__skel, elfsec, arr, n)\t\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\t\t\\\n\t\tsize_t __sz;\t\t\t\t\t\t\t\t\\\n\t\tbpf_map__set_value_size((__skel)->maps.elfsec##_##arr,\t\t\t\\\n\t\t\t\tsizeof((__skel)->elfsec##_##arr->arr[0]) * (n));\t\\\n\t\t(__skel)->elfsec##_##arr =\t\t\t\t\t\t\\\n\t\t\tbpf_map__initial_value((__skel)->maps.elfsec##_##arr, &__sz);\t\\\n\t} while (0)\n\n#include \"user_exit_info.h\"\n#include \"compat.h\"\n#include \"enums.h\"\n\n#include \"bpf_arena_common.h\"\n\n#endif\t/* __SCHED_EXT_COMMON_H */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/compat.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000021004\x0015172171634\x000011476\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (c) 2024 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2024 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2024 David Vernet <dvernet@meta.com>\n */\n#ifndef __SCX_COMPAT_H\n#define __SCX_COMPAT_H\n\n#include <bpf/btf.h>\n#include <bpf/libbpf.h>\n#include <fcntl.h>\n#include <stdlib.h>\n#include <unistd.h>\n\nstruct btf *__COMPAT_vmlinux_btf __attribute__((weak));\n\nstatic inline void __COMPAT_load_vmlinux_btf(void)\n{\n\tif (!__COMPAT_vmlinux_btf) {\n\t\t__COMPAT_vmlinux_btf = btf__load_vmlinux_btf();\n\t\tSCX_BUG_ON(!__COMPAT_vmlinux_btf, \"btf__load_vmlinux_btf()\");\n\t}\n}\n\nstatic inline bool __COMPAT_read_enum(const char *type, const char *name, u64 *v)\n{\n\tconst struct btf_type *t;\n\tconst char *n;\n\ts32 tid;\n\tint i;\n\n\t__COMPAT_load_vmlinux_btf();\n\n\ttid = btf__find_by_name(__COMPAT_vmlinux_btf, type);\n\tif (tid < 0)\n\t\treturn false;\n\n\tt = btf__type_by_id(__COMPAT_vmlinux_btf, tid);\n\tSCX_BUG_ON(!t, \"btf__type_by_id(%d)\", tid);\n\n\tif (btf_is_enum(t)) {\n\t\tstruct btf_enum *e = btf_enum(t);\n\n\t\tfor (i = 0; i < BTF_INFO_VLEN(t->info); i++) {\n\t\t\tn = btf__name_by_offset(__COMPAT_vmlinux_btf, e[i].name_off);\n\t\t\tSCX_BUG_ON(!n, \"btf__name_by_offset()\");\n\t\t\tif (!strcmp(n, name)) {\n\t\t\t\t*v = e[i].val;\n\t\t\t\treturn true;\n\t\t\t}\n\t\t}\n\t} else if (btf_is_enum64(t)) {\n\t\tstruct btf_enum64 *e = btf_enum64(t);\n\n\t\tfor (i = 0; i < BTF_INFO_VLEN(t->info); i++) {\n\t\t\tn = btf__name_by_offset(__COMPAT_vmlinux_btf, e[i].name_off);\n\t\t\tSCX_BUG_ON(!n, \"btf__name_by_offset()\");\n\t\t\tif (!strcmp(n, name)) {\n\t\t\t\t*v = btf_enum64_value(&e[i]);\n\t\t\t\treturn true;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn false;\n}\n\n#define __COMPAT_ENUM_OR_ZERO(__type, __ent)\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tu64 __val = 0;\t\t\t\t\t\t\t\t\\\n\t__COMPAT_read_enum(__type, __ent, &__val);\t\t\t\t\\\n\t__val;\t\t\t\t\t\t\t\t\t\\\n})\n\nstatic inline bool __COMPAT_has_ksym(const char *ksym)\n{\n\t__COMPAT_load_vmlinux_btf();\n\treturn btf__find_by_name(__COMPAT_vmlinux_btf, ksym) >= 0;\n}\n\nstatic inline bool __COMPAT_struct_has_field(const char *type, const char *field)\n{\n\tconst struct btf_type *t;\n\tconst struct btf_member *m;\n\tconst char *n;\n\ts32 tid;\n\tint i;\n\n\t__COMPAT_load_vmlinux_btf();\n\ttid = btf__find_by_name_kind(__COMPAT_vmlinux_btf, type, BTF_KIND_STRUCT);\n\tif (tid < 0)\n\t\treturn false;\n\n\tt = btf__type_by_id(__COMPAT_vmlinux_btf, tid);\n\tSCX_BUG_ON(!t, \"btf__type_by_id(%d)\", tid);\n\n\tm = btf_members(t);\n\n\tfor (i = 0; i < BTF_INFO_VLEN(t->info); i++) {\n\t\tn = btf__name_by_offset(__COMPAT_vmlinux_btf, m[i].name_off);\n\t\tSCX_BUG_ON(!n, \"btf__name_by_offset()\");\n\t\t\tif (!strcmp(n, field))\n\t\t\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n#define SCX_OPS_FLAG(name) __COMPAT_ENUM_OR_ZERO(\"scx_ops_flags\", #name)\n\n#define SCX_OPS_KEEP_BUILTIN_IDLE SCX_OPS_FLAG(SCX_OPS_KEEP_BUILTIN_IDLE)\n#define SCX_OPS_ENQ_LAST SCX_OPS_FLAG(SCX_OPS_ENQ_LAST)\n#define SCX_OPS_ENQ_EXITING SCX_OPS_FLAG(SCX_OPS_ENQ_EXITING)\n#define SCX_OPS_SWITCH_PARTIAL SCX_OPS_FLAG(SCX_OPS_SWITCH_PARTIAL)\n#define SCX_OPS_ENQ_MIGRATION_DISABLED SCX_OPS_FLAG(SCX_OPS_ENQ_MIGRATION_DISABLED)\n#define SCX_OPS_ALLOW_QUEUED_WAKEUP SCX_OPS_FLAG(SCX_OPS_ALLOW_QUEUED_WAKEUP)\n#define SCX_OPS_BUILTIN_IDLE_PER_NODE SCX_OPS_FLAG(SCX_OPS_BUILTIN_IDLE_PER_NODE)\n#define SCX_OPS_ALWAYS_ENQ_IMMED SCX_OPS_FLAG(SCX_OPS_ALWAYS_ENQ_IMMED)\n\n#define SCX_PICK_IDLE_FLAG(name) __COMPAT_ENUM_OR_ZERO(\"scx_pick_idle_cpu_flags\", #name)\n\n#define SCX_PICK_IDLE_CORE SCX_PICK_IDLE_FLAG(SCX_PICK_IDLE_CORE)\n#define SCX_PICK_IDLE_IN_NODE SCX_PICK_IDLE_FLAG(SCX_PICK_IDLE_IN_NODE)\n\nstatic inline long scx_hotplug_seq(void)\n{\n\tint fd;\n\tchar buf[32];\n\tchar *endptr;\n\tssize_t len;\n\tlong val;\n\n\tfd = open(\"/sys/kernel/sched_ext/hotplug_seq\", O_RDONLY);\n\tif (fd < 0)\n\t\treturn -ENOENT;\n\n\tlen = read(fd, buf, sizeof(buf) - 1);\n\tSCX_BUG_ON(len <= 0, \"read failed (%ld)\", len);\n\tbuf[len] = 0;\n\tclose(fd);\n\n\terrno = 0;\n\tval = strtoul(buf, &endptr, 10);\n\tSCX_BUG_ON(errno == ERANGE || endptr == buf ||\n\t\t (*endptr != \'\\n\' && *endptr != \'\\0\'), \"invalid num hotplug events: %ld\", val);\n\n\treturn val;\n}\n\n/*\n * struct sched_ext_ops can change over time. If compat.bpf.h::SCX_OPS_DEFINE()\n * is used to define ops and compat.h::SCX_OPS_LOAD/ATTACH() are used to load\n * and attach it, backward compatibility is automatically maintained where\n * reasonable.\n *\n * ec7e3b0463e1 (\"implement-ops\") in https://github.com/sched-ext/sched_ext is\n * the current minimum required kernel version.\n *\n * COMPAT:\n * - v6.17: ops.cgroup_set_bandwidth()\n * - v6.19: ops.cgroup_set_idle()\n * - v7.1: ops.sub_attach(), ops.sub_detach(), ops.sub_cgroup_id\n */\n#define SCX_OPS_OPEN(__ops_name, __scx_name) ({\t\t\t\t\t\\\n\tstruct __scx_name *__skel;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\\\n\tSCX_BUG_ON(!__COMPAT_struct_has_field(\"sched_ext_ops\", \"dump\"),\t\t\\\n\t\t \"sched_ext_ops.dump() missing, kernel too old?\");\t\t\\\n\t\t\t\t\t\t\t\t\t\t\\\n\t__skel = __scx_name##__open();\t\t\t\t\t\t\\\n\tSCX_BUG_ON(!__skel, \"Could not open \" #__scx_name);\t\t\t\\\n\t__skel->struct_ops.__ops_name->hotplug_seq = scx_hotplug_seq();\t\t\\\n\tSCX_ENUM_INIT(__skel);\t\t\t\t\t\t\t\\\n\tif (__skel->struct_ops.__ops_name->cgroup_set_bandwidth &&\t\t\\\n\t !__COMPAT_struct_has_field(\"sched_ext_ops\", \"cgroup_set_bandwidth\")) { \\\n\t\tfprintf(stderr, \"WARNING: kernel doesn\'t support ops.cgroup_set_bandwidth()\\n\"); \\\n\t\t__skel->struct_ops.__ops_name->cgroup_set_bandwidth = NULL;\t\\\n\t}\t\t\t\t\t\t\t\t\t\\\n\tif (__skel->struct_ops.__ops_name->cgroup_set_idle &&\t\t\t\\\n\t !__COMPAT_struct_has_field(\"sched_ext_ops\", \"cgroup_set_idle\")) { \\\n\t\tfprintf(stderr, \"WARNING: kernel doesn\'t support ops.cgroup_set_idle()\\n\"); \\\n\t\t__skel->struct_ops.__ops_name->cgroup_set_idle = NULL;\t\\\n\t}\t\t\t\t\t\t\t\t\t\\\n\tif (__skel->struct_ops.__ops_name->sub_attach &&\t\t\t\\\n\t !__COMPAT_struct_has_field(\"sched_ext_ops\", \"sub_attach\")) {\t\\\n\t\tfprintf(stderr, \"WARNING: kernel doesn\'t support ops.sub_attach()\\n\"); \\\n\t\t__skel->struct_ops.__ops_name->sub_attach = NULL;\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\\\n\tif (__skel->struct_ops.__ops_name->sub_detach &&\t\t\t\\\n\t !__COMPAT_struct_has_field(\"sched_ext_ops\", \"sub_detach\")) {\t\\\n\t\tfprintf(stderr, \"WARNING: kernel doesn\'t support ops.sub_detach()\\n\"); \\\n\t\t__skel->struct_ops.__ops_name->sub_detach = NULL;\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\\\n\tif (__skel->struct_ops.__ops_name->sub_cgroup_id > 1 &&\t\t\\\n\t !__COMPAT_struct_has_field(\"sched_ext_ops\", \"sub_cgroup_id\")) { \\\n\t\tfprintf(stderr, \"WARNING: kernel doesn\'t support ops.sub_cgroup_id\\n\"); \\\n\t\t__skel->struct_ops.__ops_name->sub_cgroup_id = 1;\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\\\n\t__skel; \t\t\t\t\t\t\t\t\\\n})\n\n/*\n * Associate non-struct_ops BPF programs with the scheduler\'s struct_ops map so\n * that scx_prog_sched() can determine which scheduler a BPF program belongs\n * to. Requires libbpf >= 1.7.\n */\n#if LIBBPF_MAJOR_VERSION > 1 ||\t\t\t\t\t\t\t\\\n\t(LIBBPF_MAJOR_VERSION == 1 && LIBBPF_MINOR_VERSION >= 7)\nstatic inline void __scx_ops_assoc_prog(struct bpf_program *prog,\n\t\t\t\t\tstruct bpf_map *map,\n\t\t\t\t\tconst char *ops_name)\n{\n\ts32 err = bpf_program__assoc_struct_ops(prog, map, NULL);\n\tif (err)\n\t\tfprintf(stderr,\n\t\t\t\"ERROR: Failed to associate %s with %s: %d\\n\",\n\t\t\tbpf_program__name(prog), ops_name, err);\n}\n#else\nstatic inline void __scx_ops_assoc_prog(struct bpf_program *prog,\n\t\t\t\t\tstruct bpf_map *map,\n\t\t\t\t\tconst char *ops_name)\n{\n}\n#endif\n\n#define SCX_OPS_LOAD(__skel, __ops_name, __scx_name, __uei_name) ({\t\t\\\n\tstruct bpf_program *__prog;\t\t\t\t\t\t\\\n\tUEI_SET_SIZE(__skel, __ops_name, __uei_name);\t\t\t\t\\\n\tSCX_BUG_ON(__scx_name##__load((__skel)), \"Failed to load skel\");\t\\\n\tbpf_object__for_each_program(__prog, (__skel)->obj) {\t\t\t\\\n\t\tif (bpf_program__type(__prog) == BPF_PROG_TYPE_STRUCT_OPS)\t\\\n\t\t\tcontinue;\t\t\t\t\t\t\\\n\t\t__scx_ops_assoc_prog(__prog, (__skel)->maps.__ops_name,\t\t\\\n\t\t\t\t #__ops_name);\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\\\n})\n\n/*\n * New versions of bpftool now emit additional link placeholders for BPF maps,\n * and set up BPF skeleton in such a way that libbpf will auto-attach BPF maps\n * automatically, assuming libbpf is recent enough (v1.5+). Old libbpf will do\n * nothing with those links and won\'t attempt to auto-attach maps.\n *\n * To maintain compatibility with older libbpf while avoiding trying to attach\n * twice, disable the autoattach feature on newer libbpf.\n */\n#if LIBBPF_MAJOR_VERSION > 1 ||\t\t\t\t\t\t\t\\\n\t(LIBBPF_MAJOR_VERSION == 1 && LIBBPF_MINOR_VERSION >= 5)\n#define __SCX_OPS_DISABLE_AUTOATTACH(__skel, __ops_name)\t\t\t\\\n\tbpf_map__set_autoattach((__skel)->maps.__ops_name, false)\n#else\n#define __SCX_OPS_DISABLE_AUTOATTACH(__skel, __ops_name) do {} while (0)\n#endif\n\n#define SCX_OPS_ATTACH(__skel, __ops_name, __scx_name) ({\t\t\t\\\n\tstruct bpf_link *__link;\t\t\t\t\t\t\\\n\t__SCX_OPS_DISABLE_AUTOATTACH(__skel, __ops_name);\t\t\t\\\n\tSCX_BUG_ON(__scx_name##__attach((__skel)), \"Failed to attach skel\");\t\\\n\t__link = bpf_map__attach_struct_ops((__skel)->maps.__ops_name);\t\t\\\n\tSCX_BUG_ON(!__link, \"Failed to attach struct_ops\");\t\t\t\\\n\t__link;\t\t\t\t\t\t\t\t\t\\\n})\n\n#endif\t/* __SCX_COMPAT_H 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/*\n * WARNING: This file is autogenerated from gen_enum_defs.py [1].\n *\n * [1] https://github.com/sched-ext/scx/blob/main/scripts/gen_enum_defs.py\n */\n\n#ifndef __ENUM_DEFS_AUTOGEN_H__\n#define __ENUM_DEFS_AUTOGEN_H__\n\n#define HAVE_SCX_DSP_DFL_MAX_BATCH\n#define HAVE_SCX_DSP_MAX_LOOPS\n#define HAVE_SCX_WATCHDOG_MAX_TIMEOUT\n#define HAVE_SCX_EXIT_BT_LEN\n#define HAVE_SCX_EXIT_MSG_LEN\n#define HAVE_SCX_EXIT_DUMP_DFL_LEN\n#define HAVE_SCX_CPUPERF_ONE\n#define HAVE_SCX_TASK_ITER_BATCH\n#define HAVE_SCX_BYPASS_HOST_NTH\n#define HAVE_SCX_BYPASS_LB_DFL_INTV_US\n#define HAVE_SCX_BYPASS_LB_DONOR_PCT\n#define HAVE_SCX_BYPASS_LB_MIN_DELTA_DIV\n#define HAVE_SCX_BYPASS_LB_BATCH\n#define HAVE_SCX_REENQ_LOCAL_MAX_REPEAT\n#define HAVE_SCX_SUB_MAX_DEPTH\n#define HAVE_SCX_CPU_PREEMPT_RT\n#define HAVE_SCX_CPU_PREEMPT_DL\n#define HAVE_SCX_CPU_PREEMPT_STOP\n#define HAVE_SCX_CPU_PREEMPT_UNKNOWN\n#define HAVE_SCX_DEQ_SLEEP\n#define HAVE_SCX_DEQ_CORE_SCHED_EXEC\n#define HAVE_SCX_DEQ_SCHED_CHANGE\n#define HAVE_SCX_DSQ_FLAG_BUILTIN\n#define HAVE_SCX_DSQ_FLAG_LOCAL_ON\n#define HAVE_SCX_DSQ_INVALID\n#define HAVE_SCX_DSQ_GLOBAL\n#define HAVE_SCX_DSQ_LOCAL\n#define HAVE_SCX_DSQ_BYPASS\n#define HAVE_SCX_DSQ_LOCAL_ON\n#define HAVE_SCX_DSQ_LOCAL_CPU_MASK\n#define HAVE_SCX_DSQ_ITER_REV\n#define HAVE___SCX_DSQ_ITER_HAS_SLICE\n#define HAVE___SCX_DSQ_ITER_HAS_VTIME\n#define HAVE___SCX_DSQ_ITER_USER_FLAGS\n#define HAVE___SCX_DSQ_ITER_ALL_FLAGS\n#define HAVE_SCX_DSQ_LNODE_ITER_CURSOR\n#define HAVE___SCX_DSQ_LNODE_PRIV_SHIFT\n#define HAVE_SCX_ENABLING\n#define HAVE_SCX_ENABLED\n#define HAVE_SCX_DISABLING\n#define HAVE_SCX_DISABLED\n#define HAVE_SCX_ENQ_WAKEUP\n#define HAVE_SCX_ENQ_HEAD\n#define HAVE_SCX_ENQ_CPU_SELECTED\n#define HAVE_SCX_ENQ_PREEMPT\n#define HAVE_SCX_ENQ_IMMED\n#define HAVE_SCX_ENQ_REENQ\n#define HAVE_SCX_ENQ_LAST\n#define HAVE___SCX_ENQ_INTERNAL_MASK\n#define HAVE_SCX_ENQ_CLEAR_OPSS\n#define HAVE_SCX_ENQ_DSQ_PRIQ\n#define HAVE_SCX_ENQ_NESTED\n#define HAVE_SCX_TASK_DSQ_ON_PRIQ\n#define HAVE_SCX_TASK_QUEUED\n#define HAVE_SCX_TASK_IN_CUSTODY\n#define HAVE_SCX_TASK_RESET_RUNNABLE_AT\n#define HAVE_SCX_TASK_DEQD_FOR_SLEEP\n#define HAVE_SCX_TASK_SUB_INIT\n#define HAVE_SCX_TASK_IMMED\n#define HAVE_SCX_TASK_STATE_SHIFT\n#define HAVE_SCX_TASK_STATE_BITS\n#define HAVE_SCX_TASK_STATE_MASK\n#define HAVE_SCX_TASK_NONE\n#define HAVE_SCX_TASK_INIT\n#define HAVE_SCX_TASK_READY\n#define HAVE_SCX_TASK_ENABLED\n#define HAVE_SCX_TASK_REENQ_REASON_SHIFT\n#define HAVE_SCX_TASK_REENQ_REASON_BITS\n#define HAVE_SCX_TASK_REENQ_REASON_MASK\n#define HAVE_SCX_TASK_REENQ_NONE\n#define HAVE_SCX_TASK_REENQ_KFUNC\n#define HAVE_SCX_TASK_REENQ_IMMED\n#define HAVE_SCX_TASK_REENQ_PREEMPTED\n#define HAVE_SCX_TASK_CURSOR\n#define HAVE_SCX_ECODE_RSN_HOTPLUG\n#define HAVE_SCX_ECODE_RSN_CGROUP_OFFLINE\n#define HAVE_SCX_ECODE_ACT_RESTART\n#define HAVE_SCX_EFLAG_INITIALIZED\n#define HAVE_SCX_EXIT_NONE\n#define HAVE_SCX_EXIT_DONE\n#define HAVE_SCX_EXIT_UNREG\n#define HAVE_SCX_EXIT_UNREG_BPF\n#define HAVE_SCX_EXIT_UNREG_KERN\n#define HAVE_SCX_EXIT_SYSRQ\n#define HAVE_SCX_EXIT_PARENT\n#define HAVE_SCX_EXIT_ERROR\n#define HAVE_SCX_EXIT_ERROR_BPF\n#define HAVE_SCX_EXIT_ERROR_STALL\n#define HAVE_SCX_KF_UNLOCKED\n#define HAVE_SCX_KF_CPU_RELEASE\n#define HAVE_SCX_KF_DISPATCH\n#define HAVE_SCX_KF_ENQUEUE\n#define HAVE_SCX_KF_SELECT_CPU\n#define HAVE_SCX_KF_REST\n#define HAVE___SCX_KF_RQ_LOCKED\n#define HAVE___SCX_KF_TERMINAL\n#define HAVE_SCX_KICK_IDLE\n#define HAVE_SCX_KICK_PREEMPT\n#define HAVE_SCX_KICK_WAIT\n#define HAVE_SCX_OPI_BEGIN\n#define HAVE_SCX_OPI_NORMAL_BEGIN\n#define HAVE_SCX_OPI_NORMAL_END\n#define HAVE_SCX_OPI_CPU_HOTPLUG_BEGIN\n#define HAVE_SCX_OPI_CPU_HOTPLUG_END\n#define HAVE_SCX_OPI_END\n#define HAVE_SCX_OPS_KEEP_BUILTIN_IDLE\n#define HAVE_SCX_OPS_ENQ_LAST\n#define HAVE_SCX_OPS_ENQ_EXITING\n#define HAVE_SCX_OPS_SWITCH_PARTIAL\n#define HAVE_SCX_OPS_ENQ_MIGRATION_DISABLED\n#define HAVE_SCX_OPS_ALLOW_QUEUED_WAKEUP\n#define HAVE_SCX_OPS_BUILTIN_IDLE_PER_NODE\n#define HAVE_SCX_OPS_ALWAYS_ENQ_IMMED\n#define HAVE_SCX_OPS_ALL_FLAGS\n#define HAVE___SCX_OPS_INTERNAL_MASK\n#define HAVE_SCX_OPS_HAS_CPU_PREEMPT\n#define HAVE_SCX_OPSS_NONE\n#define HAVE_SCX_OPSS_QUEUEING\n#define HAVE_SCX_OPSS_QUEUED\n#define HAVE_SCX_OPSS_DISPATCHING\n#define HAVE_SCX_OPSS_QSEQ_SHIFT\n#define HAVE_SCX_PICK_IDLE_CORE\n#define HAVE_SCX_PICK_IDLE_IN_NODE\n#define HAVE_SCX_OPS_NAME_LEN\n#define HAVE_SCX_SLICE_DFL\n#define HAVE_SCX_SLICE_BYPASS\n#define HAVE_SCX_SLICE_INF\n#define HAVE_SCX_REENQ_ANY\n#define HAVE___SCX_REENQ_FILTER_MASK\n#define HAVE___SCX_REENQ_USER_MASK\n#define HAVE_SCX_REENQ_TSR_RQ_OPEN\n#define HAVE_SCX_REENQ_TSR_NOT_FIRST\n#define HAVE___SCX_REENQ_TSR_MASK\n#define HAVE_SCX_RQ_ONLINE\n#define HAVE_SCX_RQ_CAN_STOP_TICK\n#define HAVE_SCX_RQ_BAL_KEEP\n#define HAVE_SCX_RQ_CLK_VALID\n#define HAVE_SCX_RQ_BAL_CB_PENDING\n#define HAVE_SCX_RQ_IN_WAKEUP\n#define HAVE_SCX_RQ_IN_BALANCE\n#define HAVE_SCX_SCHED_PCPU_BYPASSING\n#define HAVE_SCX_TG_ONLINE\n#define HAVE_SCX_TG_INITED\n#define HAVE_SCX_WAKE_FORK\n#define HAVE_SCX_WAKE_TTWU\n#define HAVE_SCX_WAKE_SYNC\n\n#endif /* __ENUM_DEFS_AUTOGEN_H__ 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (c) 2022 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2022 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2022 David Vernet <dvernet@meta.com>\n */\n#ifndef __SCX_COMMON_BPF_H\n#define __SCX_COMMON_BPF_H\n\n/*\n * The generated kfunc prototypes in vmlinux.h are missing address space\n * attributes which cause build failures. For now, suppress the generated\n * prototypes. See https://github.com/sched-ext/scx/issues/1111.\n */\n#define BPF_NO_KFUNC_PROTOTYPES\n\n#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wmissing-declarations\"\n\n#ifdef LSP\n#define __bpf__\n#include \"../vmlinux.h\"\n#else\n#include \"vmlinux.h\"\n#endif\n\n#pragma clang diagnostic pop\n\n#include <bpf/bpf_helpers.h>\n#include <bpf/bpf_tracing.h>\n#include <asm-generic/errno.h>\n#include \"user_exit_info.bpf.h\"\n#include \"enum_defs.autogen.h\"\n\n#define PF_IDLE\t\t\t\t0x00000002\t/* I am an IDLE thread */\n#define PF_IO_WORKER\t\t\t0x00000010\t/* Task is an IO worker */\n#define PF_WQ_WORKER\t\t\t0x00000020\t/* I\'m a workqueue worker */\n#define PF_KCOMPACTD\t\t\t0x00010000 /* I am kcompactd */\n#define PF_KSWAPD\t\t\t0x00020000 /* I am kswapd */\n#define PF_KTHREAD\t\t\t0x00200000\t/* I am a kernel thread */\n#define PF_EXITING\t\t\t0x00000004\n#define CLOCK_MONOTONIC\t\t\t1\n\n#ifndef NR_CPUS\n#define NR_CPUS 1024\n#endif\n\n#ifndef NUMA_NO_NODE\n#define\tNUMA_NO_NODE\t(-1)\n#endif\n\nextern int LINUX_KERNEL_VERSION __kconfig;\nextern const char CONFIG_CC_VERSION_TEXT[64] __kconfig __weak;\nextern const char CONFIG_LOCALVERSION[64] __kconfig __weak;\nextern bool CONFIG_PREEMPT_RCU __kconfig __weak;\n\n/*\n * Earlier versions of clang/pahole lost upper 32bits in 64bit enums which can\n * lead to really confusing misbehaviors. Let\'s trigger a build failure.\n */\nstatic inline void ___vmlinux_h_sanity_check___(void)\n{\n\t_Static_assert(SCX_DSQ_FLAG_BUILTIN,\n\t\t \"bpftool generated vmlinux.h is missing high bits for 64bit enums, upgrade clang and pahole\");\n}\n\ns32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __ksym;\ns32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __ksym;\ns32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed,\n\t\t\t struct scx_bpf_select_cpu_and_args *args) __ksym __weak;\nbool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __ksym __weak;\nu32 scx_bpf_dispatch_nr_slots(void) __ksym;\nvoid scx_bpf_dispatch_cancel(void) __ksym;\nvoid scx_bpf_kick_cpu(s32 cpu, u64 flags) __ksym;\ns32 scx_bpf_dsq_nr_queued(u64 dsq_id) __ksym;\nvoid scx_bpf_destroy_dsq(u64 dsq_id) __ksym;\nstruct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __ksym __weak;\nint bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __ksym __weak;\nstruct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __ksym __weak;\nvoid bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __ksym __weak;\nvoid scx_bpf_exit_bstr(s64 exit_code, char *fmt, unsigned long long *data, u32 data__sz) __ksym __weak;\nvoid scx_bpf_error_bstr(char *fmt, unsigned long long *data, u32 data_len) __ksym;\nvoid scx_bpf_dump_bstr(char *fmt, unsigned long long *data, u32 data_len) __ksym __weak;\nu32 scx_bpf_cpuperf_cap(s32 cpu) __ksym __weak;\nu32 scx_bpf_cpuperf_cur(s32 cpu) __ksym __weak;\nvoid scx_bpf_cpuperf_set(s32 cpu, u32 perf) __ksym __weak;\nu32 scx_bpf_nr_node_ids(void) __ksym __weak;\nu32 scx_bpf_nr_cpu_ids(void) __ksym __weak;\nint scx_bpf_cpu_node(s32 cpu) __ksym __weak;\nconst struct cpumask *scx_bpf_get_possible_cpumask(void) __ksym __weak;\nconst struct cpumask *scx_bpf_get_online_cpumask(void) __ksym __weak;\nvoid scx_bpf_put_cpumask(const struct cpumask *cpumask) __ksym __weak;\nconst struct cpumask *scx_bpf_get_idle_cpumask_node(int node) __ksym __weak;\nconst struct cpumask *scx_bpf_get_idle_cpumask(void) __ksym;\nconst struct cpumask *scx_bpf_get_idle_smtmask_node(int node) __ksym __weak;\nconst struct cpumask *scx_bpf_get_idle_smtmask(void) __ksym;\nvoid scx_bpf_put_idle_cpumask(const struct cpumask *cpumask) __ksym;\nbool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __ksym;\ns32 scx_bpf_pick_idle_cpu_node(const cpumask_t *cpus_allowed, int node, u64 flags) __ksym __weak;\ns32 scx_bpf_pick_idle_cpu(const cpumask_t *cpus_allowed, u64 flags) __ksym;\ns32 scx_bpf_pick_any_cpu_node(const cpumask_t *cpus_allowed, int node, u64 flags) __ksym __weak;\ns32 scx_bpf_pick_any_cpu(const cpumask_t *cpus_allowed, u64 flags) __ksym;\nbool scx_bpf_task_running(const struct task_struct *p) __ksym;\ns32 scx_bpf_task_cpu(const struct task_struct *p) __ksym;\nstruct rq *scx_bpf_cpu_rq(s32 cpu) __ksym;\nstruct rq *scx_bpf_locked_rq(void) __ksym;\nstruct task_struct *scx_bpf_cpu_curr(s32 cpu) __ksym __weak;\nu64 scx_bpf_now(void) __ksym __weak;\nvoid scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __ksym __weak;\nbool scx_bpf_sub_dispatch(u64 cgroup_id) __ksym __weak;\n\n/*\n * Use the following as @it__iter when calling scx_bpf_dsq_move[_vtime]() from\n * within bpf_for_each() loops.\n */\n#define BPF_FOR_EACH_ITER\t(&___it)\n\n#define scx_read_event(e, name)\t\t\t\t\t\t\t\\\n\t(bpf_core_field_exists((e)->name) ? (e)->name : 0)\n\nstatic inline __attribute__((format(printf, 1, 2)))\nvoid ___scx_bpf_bstr_format_checker(const char *fmt, ...) {}\n\n#define SCX_STRINGIFY(x) #x\n#define SCX_TOSTRING(x) SCX_STRINGIFY(x)\n\n/*\n * Helper macro for initializing the fmt and variadic argument inputs to both\n * bstr exit kfuncs. Callers to this function should use ___fmt and ___param to\n * refer to the initialized list of inputs to the bstr kfunc.\n */\n#define scx_bpf_bstr_preamble(fmt, args...)\t\t\t\t\t\\\n\tstatic char ___fmt[] = fmt;\t\t\t\t\t\t\\\n\t/*\t\t\t\t\t\t\t\t\t\\\n\t * Note that __param[] must have at least one\t\t\t\t\\\n\t * element to keep the verifier happy.\t\t\t\t\t\\\n\t */\t\t\t\t\t\t\t\t\t\\\n\tunsigned long long ___param[___bpf_narg(args) ?: 1] = {};\t\t\\\n\t\t\t\t\t\t\t\t\t\t\\\n\t_Pragma(\"GCC diagnostic push\")\t\t\t\t\t\t\\\n\t_Pragma(\"GCC diagnostic ignored \\\"-Wint-conversion\\\"\")\t\t\t\\\n\t___bpf_fill(___param, args);\t\t\t\t\t\t\\\n\t_Pragma(\"GCC diagnostic pop\")\n\n/*\n * scx_bpf_exit() wraps the scx_bpf_exit_bstr() kfunc with variadic arguments\n * instead of an array of u64. Using this macro will cause the scheduler to\n * exit cleanly with the specified exit code being passed to user space.\n */\n#define scx_bpf_exit(code, fmt, args...)\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tscx_bpf_bstr_preamble(fmt, args)\t\t\t\t\t\\\n\tscx_bpf_exit_bstr(code, ___fmt, ___param, sizeof(___param));\t\t\\\n\t___scx_bpf_bstr_format_checker(fmt, ##args);\t\t\t\t\\\n})\n\n/*\n * scx_bpf_error() wraps the scx_bpf_error_bstr() kfunc with variadic arguments\n * instead of an array of u64. Invoking this macro will cause the scheduler to\n * exit in an erroneous state, with diagnostic information being passed to the\n * user. It appends the file and line number to aid debugging.\n */\n#define scx_bpf_error(fmt, args...)\t\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tscx_bpf_bstr_preamble(\t\t\t\t\t\t\t\\\n\t\t__FILE__ \":\" SCX_TOSTRING(__LINE__) \": \" fmt, ##args)\t\t\\\n\tscx_bpf_error_bstr(___fmt, ___param, sizeof(___param));\t\t\t\\\n\t___scx_bpf_bstr_format_checker(\t\t\t\t\t\t\\\n\t\t__FILE__ \":\" SCX_TOSTRING(__LINE__) \": \" fmt, ##args);\t\t\\\n})\n\n/*\n * scx_bpf_dump() wraps the scx_bpf_dump_bstr() kfunc with variadic arguments\n * instead of an array of u64. To be used from ops.dump() and friends.\n */\n#define scx_bpf_dump(fmt, args...)\t\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tscx_bpf_bstr_preamble(fmt, args)\t\t\t\t\t\\\n\tscx_bpf_dump_bstr(___fmt, ___param, sizeof(___param));\t\t\t\\\n\t___scx_bpf_bstr_format_checker(fmt, ##args);\t\t\t\t\\\n})\n\n/*\n * scx_bpf_dump_header() is a wrapper around scx_bpf_dump that adds a header\n * of system information for debugging.\n */\n#define scx_bpf_dump_header()\t\t\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tscx_bpf_dump(\"kernel: %d.%d.%d %s\\ncc: %s\\n\",\t\t\t\t\\\n\t\t LINUX_KERNEL_VERSION >> 16,\t\t\t\t\\\n\t\t LINUX_KERNEL_VERSION >> 8 & 0xFF,\t\t\t\t\\\n\t\t LINUX_KERNEL_VERSION & 0xFF,\t\t\t\t\\\n\t\t CONFIG_LOCALVERSION,\t\t\t\t\t\\\n\t\t CONFIG_CC_VERSION_TEXT);\t\t\t\t\t\\\n})\n\n#define BPF_STRUCT_OPS(name, args...)\t\t\t\t\t\t\\\nSEC(\"struct_ops/\"#name)\t\t\t\t\t\t\t\t\\\nBPF_PROG(name, ##args)\n\n#define BPF_STRUCT_OPS_SLEEPABLE(name, args...)\t\t\t\t\t\\\nSEC(\"struct_ops.s/\"#name)\t\t\t\t\t\t\t\\\nBPF_PROG(name, ##args)\n\n/**\n * RESIZABLE_ARRAY - Generates annotations for an array that may be resized\n * @elfsec: the data section of the BPF program in which to place the array\n * @arr: the name of the array\n *\n * libbpf has an API for setting map value sizes. Since data sections (i.e.\n * bss, data, rodata) themselves are maps, a data section can be resized. If\n * a data section has an array as its last element, the BTF info for that\n * array will be adjusted so that length of the array is extended to meet the\n * new length of the data section. This macro annotates an array to have an\n * element count of one with the assumption that this array can be resized\n * within the userspace program. It also annotates the section specifier so\n * this array exists in a custom sub data section which can be resized\n * independently.\n *\n * See RESIZE_ARRAY() for the userspace convenience macro for resizing an\n * array declared with RESIZABLE_ARRAY().\n */\n#define RESIZABLE_ARRAY(elfsec, arr) arr[1] SEC(\".\"#elfsec\".\"#arr)\n\n/**\n * MEMBER_VPTR - Obtain the verified pointer to a struct or array member\n * @base: struct or array to index\n * @member: dereferenced member (e.g. .field, [idx0][idx1], .field[idx0] ...)\n *\n * The verifier often gets confused by the instruction sequence the compiler\n * generates for indexing struct fields or arrays. This macro forces the\n * compiler to generate a code sequence which first calculates the byte offset,\n * checks it against the struct or array size and add that byte offset to\n * generate the pointer to the member to help the verifier.\n *\n * Ideally, we want to abort if the calculated offset is out-of-bounds. However,\n * BPF currently doesn\'t support abort, so evaluate to %NULL instead. The caller\n * must check for %NULL and take appropriate action to appease the verifier. To\n * avoid confusing the verifier, it\'s best to check for %NULL and dereference\n * immediately.\n *\n *\tvptr = MEMBER_VPTR(my_array, [i][j]);\n *\tif (!vptr)\n *\t\treturn error;\n *\t*vptr = new_value;\n *\n * sizeof(@base) should encompass the memory area to be accessed and thus can\'t\n * be a pointer to the area. Use `MEMBER_VPTR(*ptr, .member)` instead of\n * `MEMBER_VPTR(ptr, ->member)`.\n */\n#ifndef MEMBER_VPTR\n#define MEMBER_VPTR(base, member) (typeof((base) member) *)\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tu64 __base = (u64)&(base);\t\t\t\t\t\t\\\n\tu64 __addr = (u64)&((base) member) - __base;\t\t\t\t\\\n\t_Static_assert(sizeof(base) >= sizeof((base) member),\t\t\t\\\n\t\t \"@base is smaller than @member, is @base a pointer?\");\t\\\n\tasm volatile (\t\t\t\t\t\t\t\t\\\n\t\t\"if %0 <= %[max] goto +2\\n\"\t\t\t\t\t\\\n\t\t\"%0 = 0\\n\"\t\t\t\t\t\t\t\\\n\t\t\"goto +1\\n\"\t\t\t\t\t\t\t\\\n\t\t\"%0 += %1\\n\"\t\t\t\t\t\t\t\\\n\t\t: \"+r\"(__addr)\t\t\t\t\t\t\t\\\n\t\t: \"r\"(__base),\t\t\t\t\t\t\t\\\n\t\t [max]\"i\"(sizeof(base) - sizeof((base) member)));\t\t\\\n\t__addr;\t\t\t\t\t\t\t\t\t\\\n})\n#endif /* MEMBER_VPTR */\n\n/**\n * ARRAY_ELEM_PTR - Obtain the verified pointer to an array element\n * @arr: array to index into\n * @i: array index\n * @n: number of elements in array\n *\n * Similar to MEMBER_VPTR() but is intended for use with arrays where the\n * element count needs to be explicit.\n * It can be used in cases where a global array is defined with an initial\n * size but is intended to be be resized before loading the BPF program.\n * Without this version of the macro, MEMBER_VPTR() will use the compile time\n * size of the array to compute the max, which will result in rejection by\n * the verifier.\n */\n#ifndef ARRAY_ELEM_PTR\n#define ARRAY_ELEM_PTR(arr, i, n) (typeof(arr[i]) *)\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tu64 __base = (u64)arr;\t\t\t\t\t\t\t\\\n\tu64 __addr = (u64)&(arr[i]) - __base;\t\t\t\t\t\\\n\tasm volatile (\t\t\t\t\t\t\t\t\\\n\t\t\"if %0 <= %[max] goto +2\\n\"\t\t\t\t\t\\\n\t\t\"%0 = 0\\n\"\t\t\t\t\t\t\t\\\n\t\t\"goto +1\\n\"\t\t\t\t\t\t\t\\\n\t\t\"%0 += %1\\n\"\t\t\t\t\t\t\t\\\n\t\t: \"+r\"(__addr)\t\t\t\t\t\t\t\\\n\t\t: \"r\"(__base),\t\t\t\t\t\t\t\\\n\t\t [max]\"r\"(sizeof(arr[0]) * ((n) - 1)));\t\t\t\\\n\t__addr;\t\t\t\t\t\t\t\t\t\\\n})\n#endif /* ARRAY_ELEM_PTR */\n\n/**\n * __sink - Hide @expr\'s value from the compiler and BPF verifier\n * @expr: The expression whose value should be opacified\n *\n * No-op at runtime. The empty inline assembly with a read-write constraint\n * (\"+g\") has two effects at compile/verify time:\n *\n * 1. Compiler: treats @expr as both read and written, preventing dead-code\n * elimination and keeping @expr (and any side effects that produced it)\n * alive.\n *\n * 2. BPF verifier: forgets the precise value/range of @expr (\"makes it\n * imprecise\"). The verifier normally tracks exact ranges for every register\n * and stack slot. While useful, precision means each distinct value creates a\n * separate verifier state. Inside loops this leads to state explosion - each\n * iteration carries different precise values so states never merge and the\n * verifier explores every iteration individually.\n *\n * Example - preventing loop state explosion::\n *\n * u32 nr_intersects = 0, nr_covered = 0;\n * __sink(nr_intersects);\n * __sink(nr_covered);\n * bpf_for(i, 0, nr_nodes) {\n * if (intersects(cpumask, node_mask[i]))\n * nr_intersects++;\n * if (covers(cpumask, node_mask[i]))\n * nr_covered++;\n * }\n *\n * Without __sink(), the verifier tracks every possible (nr_intersects,\n * nr_covered) pair across iterations, causing \"BPF program is too large\". With\n * __sink(), the values become unknown scalars so all iterations collapse into\n * one reusable state.\n *\n * Example - keeping a reference alive::\n *\n * struct task_struct *t = bpf_task_acquire(task);\n * __sink(t);\n *\n * Follows the convention from BPF selftests (bpf_misc.h).\n */\n#define __sink(expr) asm volatile (\"\" : \"+g\"(expr))\n\n/*\n * BPF declarations and helpers\n */\n\n/* list and rbtree */\n#define __contains(name, node) __attribute__((btf_decl_tag(\"contains:\" #name \":\" #node)))\n#define private(name) SEC(\".data.\" #name) __hidden __attribute__((aligned(8)))\n\nvoid *bpf_obj_new_impl(__u64 local_type_id, void *meta) __ksym;\nvoid bpf_obj_drop_impl(void *kptr, void *meta) __ksym;\n\n#define bpf_obj_new(type) ((type *)bpf_obj_new_impl(bpf_core_type_id_local(type), NULL))\n#define bpf_obj_drop(kptr) bpf_obj_drop_impl(kptr, NULL)\n\nint bpf_list_push_front_impl(struct bpf_list_head *head,\n\t\t\t\t struct bpf_list_node *node,\n\t\t\t\t void *meta, __u64 off) __ksym;\n#define bpf_list_push_front(head, node) bpf_list_push_front_impl(head, node, NULL, 0)\n\nint bpf_list_push_back_impl(struct bpf_list_head *head,\n\t\t\t\t struct bpf_list_node *node,\n\t\t\t\t void *meta, __u64 off) __ksym;\n#define bpf_list_push_back(head, node) bpf_list_push_back_impl(head, node, NULL, 0)\n\nstruct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __ksym;\nstruct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __ksym;\nstruct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root,\n\t\t\t\t struct bpf_rb_node *node) __ksym;\nint bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node,\n\t\t\tbool (less)(struct bpf_rb_node *a, const struct bpf_rb_node *b),\n\t\t\tvoid *meta, __u64 off) __ksym;\n#define bpf_rbtree_add(head, node, less) bpf_rbtree_add_impl(head, node, less, NULL, 0)\n\nstruct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __ksym;\n\nvoid *bpf_refcount_acquire_impl(void *kptr, void *meta) __ksym;\n#define bpf_refcount_acquire(kptr) bpf_refcount_acquire_impl(kptr, NULL)\n\n/* task */\nstruct task_struct *bpf_task_from_pid(s32 pid) __ksym;\nstruct task_struct *bpf_task_acquire(struct task_struct *p) __ksym;\nvoid bpf_task_release(struct task_struct *p) __ksym;\n\n/* cgroup */\nstruct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __ksym;\nstruct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __ksym;\nvoid bpf_cgroup_release(struct cgroup *cgrp) __ksym;\nstruct cgroup *bpf_cgroup_from_id(u64 cgid) __ksym;\n\n/* css iteration */\nstruct bpf_iter_css;\nstruct cgroup_subsys_state;\nextern int bpf_iter_css_new(struct bpf_iter_css *it,\n\t\t\t struct cgroup_subsys_state *start,\n\t\t\t unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *\nbpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\n\n/* cpumask */\nstruct bpf_cpumask *bpf_cpumask_create(void) __ksym;\nstruct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __ksym;\nvoid bpf_cpumask_release(struct bpf_cpumask *cpumask) __ksym;\nu32 bpf_cpumask_first(const struct cpumask *cpumask) __ksym;\nu32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __ksym;\nvoid bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __ksym;\nvoid bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __ksym;\nbool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __ksym;\nbool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __ksym;\nbool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __ksym;\nvoid bpf_cpumask_setall(struct bpf_cpumask *cpumask) __ksym;\nvoid bpf_cpumask_clear(struct bpf_cpumask *cpumask) __ksym;\nbool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1,\n\t\t const struct cpumask *src2) __ksym;\nvoid bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1,\n\t\t const struct cpumask *src2) __ksym;\nvoid bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1,\n\t\t const struct cpumask *src2) __ksym;\nbool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __ksym;\nbool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __ksym;\nbool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __ksym;\nbool bpf_cpumask_empty(const struct cpumask *cpumask) __ksym;\nbool bpf_cpumask_full(const struct cpumask *cpumask) __ksym;\nvoid bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __ksym;\nu32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __ksym;\nu32 bpf_cpumask_any_and_distribute(const struct cpumask *src1,\n\t\t\t\t const struct cpumask *src2) __ksym;\nu32 bpf_cpumask_weight(const struct cpumask *cpumask) __ksym;\n\nint bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __ksym;\nint *bpf_iter_bits_next(struct bpf_iter_bits *it) __ksym;\nvoid bpf_iter_bits_destroy(struct bpf_iter_bits *it) __ksym;\n\n#define def_iter_struct(name)\t\t\t\t\t\t\t\\\nstruct bpf_iter_##name {\t\t\t\t\t\t\t\\\n struct bpf_iter_bits it;\t\t\t\t\t\t\t\\\n const struct cpumask *bitmap;\t\t\t\t\t\t\\\n};\n\n#define def_iter_new(name)\t\t\t\t\t\t\t\\\nstatic inline int bpf_iter_##name##_new(\t\t\t\t\t\\\n\tstruct bpf_iter_##name *it, const u64 *unsafe_ptr__ign, u32 nr_words)\t\\\n{\t\t\t\t\t\t\t\t\t\t\\\n\tit->bitmap = scx_bpf_get_##name##_cpumask();\t\t\t\t\\\n\treturn bpf_iter_bits_new(&it->it, (const u64 *)it->bitmap,\t\t\\\n\t\t\t\t sizeof(struct cpumask) / 8);\t\t\t\\\n}\n\n#define def_iter_next(name)\t\t\t\t\t\t\t\\\nstatic inline int *bpf_iter_##name##_next(struct bpf_iter_##name *it) {\t\t\\\n\treturn bpf_iter_bits_next(&it->it);\t\t\t\t\t\\\n}\n\n#define def_iter_destroy(name)\t\t\t\t\t\t\t\\\nstatic inline void bpf_iter_##name##_destroy(struct bpf_iter_##name *it) {\t\\\n\tscx_bpf_put_cpumask(it->bitmap);\t\t\t\t\t\\\n\tbpf_iter_bits_destroy(&it->it);\t\t\t\t\t\t\\\n}\n#define def_for_each_cpu(cpu, name) for_each_##name##_cpu(cpu)\n\n/// Provides iterator for possible and online cpus.\n///\n/// # Example\n///\n/// ```\n/// static inline void example_use() {\n/// int *cpu;\n///\n/// for_each_possible_cpu(cpu){\n/// bpf_printk(\"CPU %d is possible\", *cpu);\n/// }\n///\n/// for_each_online_cpu(cpu){\n/// bpf_printk(\"CPU %d is online\", *cpu);\n/// }\n/// }\n/// ```\ndef_iter_struct(possible);\ndef_iter_new(possible);\ndef_iter_next(possible);\ndef_iter_destroy(possible);\n#define for_each_possible_cpu(cpu) bpf_for_each(possible, cpu, NULL, 0)\n\ndef_iter_struct(online);\ndef_iter_new(online);\ndef_iter_next(online);\ndef_iter_destroy(online);\n#define for_each_online_cpu(cpu) bpf_for_each(online, cpu, NULL, 0)\n\n/*\n * Access a cpumask in read-only mode (typically to check bits).\n */\nstatic __always_inline const struct cpumask *cast_mask(struct bpf_cpumask *mask)\n{\n\treturn (const struct cpumask *)mask;\n}\n\n/*\n * True if the BPF prolog (__bpf_prog_enter) calls migrate_disable() for the\n * current task. Probed at runtime by scx_lib_init(). Defaults to true because\n * the prolog called migrate_disable() unconditionally on kernels before v6.18,\n * so schedulers that omit scx_lib_init() safely fall back to the original\n * p == current disambiguation.\n */\nstatic bool __scx_prolog_disables_migration = true;\n\n/*\n * scx_lib_init - initialize the scx BPF library\n *\n * Must be called at the top of ops.init(). Probes runtime behavior needed by\n * library functions such as is_migration_disabled().\n *\n * Returns 0 on success.\n */\nstatic inline int scx_lib_init(void)\n{\n\t/*\n\t * Probe whether the BPF prolog calls migrate_disable() by checking\n\t * migration_disabled of the current task. Since we are executing BPF\n\t * code right now, the prolog has already run: if it called\n\t * migrate_disable(), migration_disabled is non-zero.\n\t */\n\tif (bpf_core_field_exists(((struct task_struct *)0)->migration_disabled)) {\n\t\tconst struct task_struct *p = bpf_get_current_task_btf();\n\t\t__scx_prolog_disables_migration = p->migration_disabled > 0;\n\t}\n\treturn 0;\n}\n\n/*\n * Return true if task @p cannot migrate to a different CPU, false\n * otherwise.\n */\nstatic inline bool is_migration_disabled(const struct task_struct *p)\n{\n\t/*\n\t * Testing p->migration_disabled in BPF is tricky because the BPF prolog\n\t * (__bpf_prog_enter) may call migrate_disable() for the current task,\n\t * making migration_disabled == 1 even for tasks that are not truly\n\t * migration-disabled.\n\t *\n\t * Since commit 8e4f0b1ebcf2 (\"bpf: use rcu_read_lock_dont_migrate() for\n\t * trampoline.c\"), the BPF prolog calls migrate_disable() only when\n\t * CONFIG_PREEMPT_RCU is enabled. Two fast paths cover the common cases:\n\t *\n\t * 1) CONFIG_PREEMPT_RCU: prolog always calls migrate_disable(), so\n\t * migration_disabled == 1 for the current task is ambiguous.\n\t * Disambiguate by checking p == current.\n\t *\n\t * 2) v6.18+ without CONFIG_PREEMPT_RCU: prolog never calls\n\t * migrate_disable(), so migration_disabled == 1 is unambiguously\n\t * a real migrate_disable() call.\n\t *\n\t * A slow path handles pre-v6.18 kernels without CONFIG_PREEMPT_RCU,\n\t * where the prolog historically called migrate_disable() unconditionally\n\t * but a cherry-picked downstream kernel may not. The runtime-probed flag\n\t * __scx_prolog_disables_migration (set by scx_lib_init()) distinguishes\n\t * the two cases without relying on the kernel version alone.\n\t */\n\tif (bpf_core_field_exists(p->migration_disabled)) {\n\t\tif (p->migration_disabled == 1) {\n\t\t\t/* Fast path: prolog always disables migration */\n\t\t\tif (CONFIG_PREEMPT_RCU)\n\t\t\t\treturn bpf_get_current_task_btf() != p;\n\t\t\t/* Fast path: prolog never disables migration */\n\t\t\tif (LINUX_KERNEL_VERSION >= KERNEL_VERSION(6, 18, 0))\n\t\t\t\treturn true;\n\t\t\t/* Slow path: pre-v6.18, !PREEMPT_RCU - use runtime flag */\n\t\t\treturn __scx_prolog_disables_migration ?\n\t\t\t bpf_get_current_task_btf() != p : true;\n\t\t}\n\t\treturn p->migration_disabled;\n\t}\n\treturn false;\n}\n\n/* rcu */\nvoid bpf_rcu_read_lock(void) __ksym;\nvoid bpf_rcu_read_unlock(void) __ksym;\n\n/*\n * Time helpers, most of which are from jiffies.h.\n */\n\n/**\n * time_delta - Calculate the delta between new and old time stamp\n * @after: first comparable as u64\n * @before: second comparable as u64\n *\n * Return: the time difference, which is >= 0\n */\nstatic inline s64 time_delta(u64 after, u64 before)\n{\n\treturn (s64)(after - before) > 0 ? (s64)(after - before) : 0;\n}\n\n/**\n * time_after - returns true if the time a is after time b.\n * @a: first comparable as u64\n * @b: second comparable as u64\n *\n * Do this with \"<0\" and \">=0\" to only test the sign of the result. A\n * good compiler would generate better code (and a really good compiler\n * wouldn\'t care). Gcc is currently neither.\n *\n * Return: %true is time a is after time b, otherwise %false.\n */\nstatic inline bool time_after(u64 a, u64 b)\n{\n\treturn (s64)(b - a) < 0;\n}\n\n/**\n * time_before - returns true if the time a is before time b.\n * @a: first comparable as u64\n * @b: second comparable as u64\n *\n * Return: %true is time a is before time b, otherwise %false.\n */\nstatic inline bool time_before(u64 a, u64 b)\n{\n\treturn time_after(b, a);\n}\n\n/**\n * time_after_eq - returns true if the time a is after or the same as time b.\n * @a: first comparable as u64\n * @b: second comparable as u64\n *\n * Return: %true is time a is after or the same as time b, otherwise %false.\n */\nstatic inline bool time_after_eq(u64 a, u64 b)\n{\n\treturn (s64)(a - b) >= 0;\n}\n\n/**\n * time_before_eq - returns true if the time a is before or the same as time b.\n * @a: first comparable as u64\n * @b: second comparable as u64\n *\n * Return: %true is time a is before or the same as time b, otherwise %false.\n */\nstatic inline bool time_before_eq(u64 a, u64 b)\n{\n\treturn time_after_eq(b, a);\n}\n\n/**\n * time_in_range - Calculate whether a is in the range of [b, c].\n * @a: time to test\n * @b: beginning of the range\n * @c: end of the range\n *\n * Return: %true is time a is in the range [b, c], otherwise %false.\n */\nstatic inline bool time_in_range(u64 a, u64 b, u64 c)\n{\n\treturn time_after_eq(a, b) && time_before_eq(a, c);\n}\n\n/**\n * time_in_range_open - Calculate whether a is in the range of [b, c).\n * @a: time to test\n * @b: beginning of the range\n * @c: end of the range\n *\n * Return: %true is time a is in the range [b, c), otherwise %false.\n */\nstatic inline bool time_in_range_open(u64 a, u64 b, u64 c)\n{\n\treturn time_after_eq(a, b) && time_before(a, c);\n}\n\n\n/*\n * Other helpers\n */\n\n/* useful compiler attributes */\n#ifndef likely\n#define likely(x) __builtin_expect(!!(x), 1)\n#endif\n#ifndef unlikely\n#define unlikely(x) __builtin_expect(!!(x), 0)\n#endif\n#ifndef __maybe_unused\n#define __maybe_unused __attribute__((__unused__))\n#endif\n\n/*\n * READ/WRITE_ONCE() are from kernel (include/asm-generic/rwonce.h). They\n * prevent compiler from caching, redoing or reordering reads or writes.\n */\ntypedef __u8 __attribute__((__may_alias__)) __u8_alias_t;\ntypedef __u16 __attribute__((__may_alias__)) __u16_alias_t;\ntypedef __u32 __attribute__((__may_alias__)) __u32_alias_t;\ntypedef __u64 __attribute__((__may_alias__)) __u64_alias_t;\n\nstatic __always_inline void __read_once_size(const volatile void *p, void *res, int size)\n{\n\tswitch (size) {\n\tcase 1: *(__u8_alias_t *) res = *(volatile __u8_alias_t *) p; break;\n\tcase 2: *(__u16_alias_t *) res = *(volatile __u16_alias_t *) p; break;\n\tcase 4: *(__u32_alias_t *) res = *(volatile __u32_alias_t *) p; break;\n\tcase 8: *(__u64_alias_t *) res = *(volatile __u64_alias_t *) p; break;\n\tdefault:\n\t\tbarrier();\n\t\t__builtin_memcpy((void *)res, (const void *)p, size);\n\t\tbarrier();\n\t}\n}\n\nstatic __always_inline void __write_once_size(volatile void *p, void *res, int size)\n{\n\tswitch (size) {\n\tcase 1: *(volatile __u8_alias_t *) p = *(__u8_alias_t *) res; break;\n\tcase 2: *(volatile __u16_alias_t *) p = *(__u16_alias_t *) res; break;\n\tcase 4: *(volatile __u32_alias_t *) p = *(__u32_alias_t *) res; break;\n\tcase 8: *(volatile __u64_alias_t *) p = *(__u64_alias_t *) res; break;\n\tdefault:\n\t\tbarrier();\n\t\t__builtin_memcpy((void *)p, (const void *)res, size);\n\t\tbarrier();\n\t}\n}\n\n/*\n * __unqual_typeof(x) - Declare an unqualified scalar type, leaving\n *\t\t\tnon-scalar types unchanged,\n *\n * Prefer C11 _Generic for better compile-times and simpler code. Note: \'char\'\n * is not type-compatible with \'signed char\', and we define a separate case.\n *\n * This is copied verbatim from kernel\'s include/linux/compiler_types.h, but\n * with default expression (for pointers) changed from (x) to (typeof(x)0).\n *\n * This is because LLVM has a bug where for lvalue (x), it does not get rid of\n * an extra address_space qualifier, but does in case of rvalue (typeof(x)0).\n * Hence, for pointers, we need to create an rvalue expression to get the\n * desired type. See https://github.com/llvm/llvm-project/issues/53400.\n */\n#define __scalar_type_to_expr_cases(type) \\\n\tunsigned type : (unsigned type)0, signed type : (signed type)0\n\n#define __unqual_typeof(x) \\\n\ttypeof(_Generic((x), \\\n\t\tchar: (char)0, \\\n\t\t__scalar_type_to_expr_cases(char), \\\n\t\t__scalar_type_to_expr_cases(short), \\\n\t\t__scalar_type_to_expr_cases(int), \\\n\t\t__scalar_type_to_expr_cases(long), \\\n\t\t__scalar_type_to_expr_cases(long long), \\\n\t\tdefault: (typeof(x))0))\n\n#define READ_ONCE(x)\t\t\t\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tunion { __unqual_typeof(x) __val; char __c[1]; } __u =\t\t\t\\\n\t\t{ .__c = { 0 } };\t\t\t\t\t\t\\\n\t__read_once_size((__unqual_typeof(x) *)&(x), __u.__c, sizeof(x));\t\\\n\t__u.__val;\t\t\t\t\t\t\t\t\\\n})\n\n#define WRITE_ONCE(x, val)\t\t\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\\\n\tunion { __unqual_typeof(x) __val; char __c[1]; } __u =\t\t\t\\\n\t\t{ .__val = (val) }; \t\t\t\t\t\t\\\n\t__write_once_size((__unqual_typeof(x) *)&(x), __u.__c, sizeof(x));\t\\\n\t__u.__val;\t\t\t\t\t\t\t\t\\\n})\n\n/*\n * __calc_avg - Calculate exponential weighted moving average (EWMA) with\n * @old and @new values. @decay represents how large the @old value remains.\n * With a larger @decay value, the moving average changes slowly, exhibiting\n * fewer fluctuations.\n */\n#define __calc_avg(old, new, decay) ({\t\t\t\t\t\t\\\n\ttypeof(decay) thr = 1 << (decay);\t\t\t\t\t\\\n\ttypeof(old) ret;\t\t\t\t\t\t\t\\\n\tif (((old) < thr) || ((new) < thr)) {\t\t\t\t\t\\\n\t\tif (((old) == 1) && ((new) == 0))\t\t\t\t\\\n\t\t\tret = 0;\t\t\t\t\t\t\\\n\t\telse\t\t\t\t\t\t\t\t\\\n\t\t\tret = ((old) - ((old) >> 1)) + ((new) >> 1);\t\t\\\n\t} else {\t\t\t\t\t\t\t\t\\\n\t\tret = ((old) - ((old) >> (decay))) + ((new) >> (decay));\t\\\n\t}\t\t\t\t\t\t\t\t\t\\\n\tret;\t\t\t\t\t\t\t\t\t\\\n})\n\n/*\n * log2_u32 - Compute the base 2 logarithm of a 32-bit exponential value.\n * @v: The value for which we\'re computing the base 2 logarithm.\n */\nstatic inline u32 log2_u32(u32 v)\n{\n u32 r;\n u32 shift;\n\n r = (v > 0xFFFF) << 4; v >>= r;\n shift = (v > 0xFF) << 3; v >>= shift; r |= shift;\n shift = (v > 0xF) << 2; v >>= shift; r |= shift;\n shift = (v > 0x3) << 1; v >>= shift; r |= shift;\n r |= (v >> 1);\n return r;\n}\n\n/*\n * log2_u64 - Compute the base 2 logarithm of a 64-bit exponential value.\n * @v: The value for which we\'re computing the base 2 logarithm.\n */\nstatic inline u32 log2_u64(u64 v)\n{\n u32 hi = v >> 32;\n if (hi)\n return log2_u32(hi) + 32 + 1;\n else\n return log2_u32(v) + 1;\n}\n\n/*\n * sqrt_u64 - Calculate the square root of value @x using Newton\'s method.\n */\nstatic inline u64 __sqrt_u64(u64 x)\n{\n\tif (x == 0 || x == 1)\n\t\treturn x;\n\n\tu64 r = ((1ULL << 32) > x) ? x : (1ULL << 32);\n\n\tfor (int i = 0; i < 8; ++i) {\n\t\tu64 q = x / r;\n\t\tif (r <= q)\n\t\t\tbreak;\n\t\tr = (r + q) >> 1;\n\t}\n\treturn r;\n}\n\n/*\n * ctzll -- Counts trailing zeros in an unsigned long long. If the input value\n * is zero, the return value is undefined.\n */\nstatic inline int ctzll(u64 v)\n{\n#if (!defined(__BPF__) && defined(__SCX_TARGET_ARCH_x86)) || \\\n\t(defined(__BPF__) && defined(__clang_major__) && __clang_major__ >= 19)\n\t/*\n\t * Use the ctz builtin when: (1) building for native x86, or\n\t * (2) building for BPF with clang >= 19 (BPF backend supports\n\t * the intrinsic from clang 19 onward; earlier versions hit\n\t * \"unimplemented opcode\" in the backend).\n\t */\n\treturn __builtin_ctzll(v);\n#else\n\t/*\n\t * If neither the target architecture nor the toolchains support ctzll,\n\t * use software-based emulation. Let\'s use the De Bruijn sequence-based\n\t * approach to find LSB fastly. See the details of De Bruijn sequence:\n\t *\n\t * https://en.wikipedia.org/wiki/De_Bruijn_sequence\n\t * https://www.chessprogramming.org/BitScan#De_Bruijn_Multiplication\n\t */\n\tconst int lookup_table[64] = {\n\t\t 0, 1, 48, 2, 57, 49, 28, 3, 61, 58, 50, 42, 38, 29, 17, 4,\n\t\t62, 55, 59, 36, 53, 51, 43, 22, 45, 39, 33, 30, 24, 18, 12, 5,\n\t\t63, 47, 56, 27, 60, 41, 37, 16, 54, 35, 52, 21, 44, 32, 23, 11,\n\t\t46, 26, 40, 15, 34, 20, 31, 10, 25, 14, 19, 9, 13, 8, 7, 6,\n\t};\n\tconst u64 DEBRUIJN_CONSTANT = 0x03f79d71b4cb0a89ULL;\n\tunsigned int index;\n\tu64 lowest_bit;\n\tconst int *lt;\n\n\tif (v == 0)\n\t\treturn -1;\n\n\t/*\n\t * Isolate the least significant bit (LSB).\n\t * For example, if v = 0b...10100, then v & -v = 0b...00100\n\t */\n\tlowest_bit = v & -v;\n\n\t/*\n\t * Each isolated bit produces a unique 6-bit value, guaranteed by the\n\t * De Bruijn property. Calculate a unique index into the lookup table\n\t * using the magic constant and a right shift.\n\t *\n\t * Multiplying by the 64-bit constant \"spreads out\" that 1-bit into a\n\t * unique pattern in the top 6 bits. This uniqueness property is\n\t * exactly what a De Bruijn sequence guarantees: Every possible 6-bit\n\t * pattern (in top bits) occurs exactly once for each LSB position. So,\n\t * the constant 0x03f79d71b4cb0a89ULL is carefully chosen to be a\n\t * De Bruijn sequence, ensuring no collisions in the table index.\n\t */\n\tindex = (lowest_bit * DEBRUIJN_CONSTANT) >> 58;\n\n\t/*\n\t * Lookup in a precomputed table. No collision is guaranteed by the\n\t * De Bruijn property.\n\t */\n\tlt = MEMBER_VPTR(lookup_table, [index]);\n\treturn (lt)? *lt : -1;\n#endif\n}\n\n/*\n * Return a value proportionally scaled to the task\'s weight.\n */\nstatic inline u64 scale_by_task_weight(const struct task_struct *p, u64 value)\n{\n\treturn (value * p->scx.weight) / 100;\n}\n\n/*\n * Return a value inversely proportional to the task\'s weight.\n */\nstatic inline u64 scale_by_task_weight_inverse(const struct task_struct *p, u64 value)\n{\n\treturn value * 100 / p->scx.weight;\n}\n\n\n/*\n * Get a random u64 from the kernel\'s pseudo-random generator.\n */\nstatic inline u64 get_prandom_u64()\n{\n\treturn ((u64)bpf_get_prandom_u32() << 32) | bpf_get_prandom_u32();\n}\n\n/*\n * Define the shadow structure to avoid a compilation error when\n * vmlinux.h does not enable necessary kernel configs. The ___local\n * suffix is a CO-RE convention that tells the loader to match this\n * against the base struct rq in the kernel. The attribute\n * preserve_access_index tells the compiler to generate a CO-RE\n * relocation for these fields.\n */\nstruct rq___local {\n\t/*\n\t * A monotonically increasing clock per CPU. It is rq->clock minus\n\t * cumulative IRQ time and hypervisor steal time. Unlike rq->clock,\n\t * it does not advance during IRQ processing or hypervisor preemption.\n\t * It does advance during idle (the idle task counts as a running task\n\t * for this purpose).\n\t */\n\tu64\t\tclock_task;\n\t/*\n\t * Invariant version of clock_task scaled by CPU capacity and\n\t * frequency. For example, clock_pelt advances 2x slower on a CPU\n\t * with half the capacity.\n\t *\n\t * At idle exit, rq->clock_pelt jumps forward to resync with\n\t * clock_task. The kernel\'s rq_clock_pelt() corrects for this jump\n\t * by subtracting lost_idle_time, yielding a clock that appears\n\t * continuous across idle transitions. scx_clock_pelt() mirrors\n\t * rq_clock_pelt() by performing the same subtraction.\n\t */\n\tu64\t\tclock_pelt;\n\t/*\n\t * Accumulates the magnitude of each clock_pelt jump at idle exit.\n\t * Subtracting this from clock_pelt gives rq_clock_pelt(): a\n\t * continuous, capacity-invariant clock suitable for both task\n\t * execution time stamping and cross-idle measurements.\n\t */\n\tunsigned long\tlost_idle_time;\n\t/*\n\t * Shadow of paravirt_steal_clock() (the hypervisor\'s cumulative\n\t * stolen time counter). Stays frozen while the hypervisor preempts\n\t * the vCPU; catches up the next time update_rq_clock_task() is\n\t * called. The delta is the stolen time not yet subtracted from\n\t * clock_task.\n\t *\n\t * Unlike irqtime->total (a plain kernel-side field), the live stolen\n\t * time counter lives in hypervisor-specific shared memory and has no\n\t * kernel-side equivalent readable from BPF in a hypervisor-agnostic\n\t * way. This field is therefore the only portable BPF-accessible\n\t * approximation of cumulative steal time.\n\t *\n\t * Available only when CONFIG_PARAVIRT_TIME_ACCOUNTING is on.\n\t */\n\tu64\t\tprev_steal_time_rq;\n} __attribute__((preserve_access_index));\n\nextern struct rq runqueues __ksym;\n\n/*\n * Define the shadow structure to avoid a compilation error when\n * vmlinux.h does not enable necessary kernel configs.\n */\nstruct irqtime___local {\n\t/*\n\t * Cumulative IRQ time counter for this CPU, in nanoseconds. Advances\n\t * immediately at the exit of every hardirq and non-ksoftirqd softirq\n\t * via irqtime_account_irq(). ksoftirqd time is counted as normal\n\t * task time and is NOT included. NMI time is also NOT included.\n\t *\n\t * The companion field irqtime->sync (struct u64_stats_sync) protects\n\t * against 64-bit tearing on 32-bit architectures. On 64-bit kernels,\n\t * u64_stats_sync is an empty struct and all seqcount operations are\n\t * no-ops, so a plain BPF_CORE_READ of this field is safe.\n\t *\n\t * Available only when CONFIG_IRQ_TIME_ACCOUNTING is on.\n\t */\n\tu64\t\ttotal;\n} __attribute__((preserve_access_index));\n\n/*\n * cpu_irqtime is a per-CPU variable defined only when\n * CONFIG_IRQ_TIME_ACCOUNTING is on. Declare it as __weak so the BPF\n * loader sets its address to 0 (rather than failing) when the symbol\n * is absent from the running kernel.\n */\nextern struct irqtime___local cpu_irqtime __ksym __weak;\n\nstatic inline struct rq___local *get_current_rq(u32 cpu)\n{\n\t/*\n\t * This is a workaround to get an rq pointer since we decided to\n\t * deprecate scx_bpf_cpu_rq().\n\t *\n\t * WARNING: The caller must hold the rq lock for @cpu. This is\n\t * guaranteed when called from scheduling callbacks (ops.running,\n\t * ops.stopping, ops.enqueue, ops.dequeue, ops.dispatch, etc.).\n\t * There is no runtime check available in BPF for kernel spinlock\n\t * state \xe2\x80\x94 correctness is enforced by calling context only.\n\t */\n\treturn (void *)bpf_per_cpu_ptr(&runqueues, cpu);\n}\n\nstatic inline u64 scx_clock_task(u32 cpu)\n{\n\tstruct rq___local *rq = get_current_rq(cpu);\n\n\t/*\n\t * Equivalent to the kernel\'s rq_clock_task(): wall-clock time minus\n\t * cumulative IRQ time (CONFIG_IRQ_TIME_ACCOUNTING) and hypervisor\n\t * steal time (CONFIG_PARAVIRT_TIME_ACCOUNTING). Without those configs,\n\t * it equals rq->clock.\n\t *\n\t * Conceptually this clock advances during idle (the idle task counts\n\t * as a running task), but rq->clock_task is only updated on scheduling\n\t * events. With NO_HZ_IDLE (the default), the periodic tick is stopped\n\t * on idle CPUs, so rq->clock_task is not refreshed while a CPU is\n\t * idle. Reading this clock for a remote idle CPU from a BPF timer\n\t * callback returns the value from when the CPU last went idle, making\n\t * the delta over an idle interval effectively zero.\n\t */\n\treturn rq ? rq->clock_task : 0;\n}\n\nstatic inline u64 scx_clock_pelt(u32 cpu)\n{\n\tstruct rq___local *rq = get_current_rq(cpu);\n\n\t/*\n\t * Equivalent to the kernel\'s rq_clock_pelt(): subtracts\n\t * lost_idle_time from clock_pelt to absorb the jump that occurs\n\t * when clock_pelt resyncs with clock_task at idle exit. The intent\n\t * is a continuous, capacity- and frequency-invariant clock that is\n\t * frozen during idle, IRQ, and hypervisor steal.\n\t *\n\t * However, like scx_clock_task(), this clock has a stale-read issue\n\t * for remote idle CPUs with NO_HZ_IDLE (the default). clock_pelt\n\t * itself advances at wall-clock rate (hardware-clock based), but\n\t * lost_idle_time is only updated via update_rq_clock_pelt(), which\n\t * requires update_rq_clock() to be called. With NO_HZ_IDLE, the\n\t * periodic tick is stopped on idle CPUs, so lost_idle_time is not\n\t * refreshed during idle. Reading this clock for a remote idle CPU\n\t * from a BPF timer callback therefore returns a value that drifts\n\t * at wall-clock rate -- the same stale behaviour as scx_clock_task().\n\t *\n\t * Without NO_HZ_IDLE, periodic ticks keep lost_idle_time nearly in\n\t * sync (stale by at most one tick period, ~1 ms), so the result is\n\t * accurate.\n\t */\n\treturn rq ? (rq->clock_pelt - rq->lost_idle_time) : 0;\n}\n\nstatic inline u64 scx_clock_virt(u32 cpu)\n{\n\tstruct rq___local *rq;\n\n\t/*\n\t * Check field existence before calling get_current_rq() so we avoid\n\t * the per_cpu lookup entirely on kernels built without\n\t * CONFIG_PARAVIRT_TIME_ACCOUNTING.\n\t */\n\tif (!bpf_core_field_exists(((struct rq___local *)0)->prev_steal_time_rq))\n\t\treturn 0;\n\n\t/* Lagging shadow of the kernel\'s paravirt_steal_clock(). */\n\trq = get_current_rq(cpu);\n\treturn rq ? BPF_CORE_READ(rq, prev_steal_time_rq) : 0;\n}\n\nstatic inline u64 scx_clock_irq(u32 cpu)\n{\n\tstruct irqtime___local *irqt;\n\n\t/*\n\t * bpf_core_type_exists() resolves at load time: if struct irqtime is\n\t * absent from kernel BTF (CONFIG_IRQ_TIME_ACCOUNTING off), the loader\n\t * patches this into an unconditional return 0, making the\n\t * bpf_per_cpu_ptr() call below dead code that the verifier never sees.\n\t */\n\tif (!bpf_core_type_exists(struct irqtime___local))\n\t\treturn 0;\n\n\t/* Equivalent to the kernel\'s irq_time_read(). */\n\tirqt = bpf_per_cpu_ptr(&cpu_irqtime, cpu);\n\treturn irqt ? BPF_CORE_READ(irqt, total) : 0;\n}\n\n#include \"compat.bpf.h\"\n#include \"enums.bpf.h\"\n\n#endif\t/* __SCX_COMMON_BPF_H */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00scx/enums.autogen.bpf.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000010373\x0015172171634\x000013560\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/*\n * WARNING: This file is autogenerated from scripts/gen_enums.py. If you would\n * like to access an enum that is currently missing, add it to the script\n * and run it from the root directory to update this file.\n */\n\nconst volatile u64 __SCX_OPS_NAME_LEN __weak;\n#define SCX_OPS_NAME_LEN __SCX_OPS_NAME_LEN\n\nconst volatile u64 __SCX_SLICE_DFL __weak;\n#define SCX_SLICE_DFL __SCX_SLICE_DFL\n\nconst volatile u64 __SCX_SLICE_INF __weak;\n#define SCX_SLICE_INF __SCX_SLICE_INF\n\nconst volatile u64 __SCX_RQ_ONLINE __weak;\n#define SCX_RQ_ONLINE __SCX_RQ_ONLINE\n\nconst volatile u64 __SCX_RQ_CAN_STOP_TICK __weak;\n#define SCX_RQ_CAN_STOP_TICK __SCX_RQ_CAN_STOP_TICK\n\nconst volatile u64 __SCX_RQ_BAL_PENDING __weak;\n#define SCX_RQ_BAL_PENDING __SCX_RQ_BAL_PENDING\n\nconst volatile u64 __SCX_RQ_BAL_KEEP __weak;\n#define SCX_RQ_BAL_KEEP __SCX_RQ_BAL_KEEP\n\nconst volatile u64 __SCX_RQ_BYPASSING __weak;\n#define SCX_RQ_BYPASSING __SCX_RQ_BYPASSING\n\nconst volatile u64 __SCX_RQ_CLK_VALID __weak;\n#define SCX_RQ_CLK_VALID __SCX_RQ_CLK_VALID\n\nconst volatile u64 __SCX_RQ_IN_WAKEUP __weak;\n#define SCX_RQ_IN_WAKEUP __SCX_RQ_IN_WAKEUP\n\nconst volatile u64 __SCX_RQ_IN_BALANCE __weak;\n#define SCX_RQ_IN_BALANCE __SCX_RQ_IN_BALANCE\n\nconst volatile u64 __SCX_DSQ_FLAG_BUILTIN __weak;\n#define SCX_DSQ_FLAG_BUILTIN __SCX_DSQ_FLAG_BUILTIN\n\nconst volatile u64 __SCX_DSQ_FLAG_LOCAL_ON __weak;\n#define SCX_DSQ_FLAG_LOCAL_ON __SCX_DSQ_FLAG_LOCAL_ON\n\nconst volatile u64 __SCX_DSQ_INVALID __weak;\n#define SCX_DSQ_INVALID __SCX_DSQ_INVALID\n\nconst volatile u64 __SCX_DSQ_GLOBAL __weak;\n#define SCX_DSQ_GLOBAL __SCX_DSQ_GLOBAL\n\nconst volatile u64 __SCX_DSQ_LOCAL __weak;\n#define SCX_DSQ_LOCAL __SCX_DSQ_LOCAL\n\nconst volatile u64 __SCX_DSQ_LOCAL_ON __weak;\n#define SCX_DSQ_LOCAL_ON __SCX_DSQ_LOCAL_ON\n\nconst volatile u64 __SCX_DSQ_LOCAL_CPU_MASK __weak;\n#define SCX_DSQ_LOCAL_CPU_MASK __SCX_DSQ_LOCAL_CPU_MASK\n\nconst volatile u64 __SCX_TASK_QUEUED __weak;\n#define SCX_TASK_QUEUED __SCX_TASK_QUEUED\n\nconst volatile u64 __SCX_TASK_RESET_RUNNABLE_AT __weak;\n#define SCX_TASK_RESET_RUNNABLE_AT __SCX_TASK_RESET_RUNNABLE_AT\n\nconst volatile u64 __SCX_TASK_DEQD_FOR_SLEEP __weak;\n#define SCX_TASK_DEQD_FOR_SLEEP __SCX_TASK_DEQD_FOR_SLEEP\n\nconst volatile u64 __SCX_TASK_SUB_INIT __weak;\n#define SCX_TASK_SUB_INIT __SCX_TASK_SUB_INIT\n\nconst volatile u64 __SCX_TASK_IMMED __weak;\n#define SCX_TASK_IMMED __SCX_TASK_IMMED\n\nconst volatile u64 __SCX_TASK_STATE_SHIFT __weak;\n#define SCX_TASK_STATE_SHIFT __SCX_TASK_STATE_SHIFT\n\nconst volatile u64 __SCX_TASK_STATE_BITS __weak;\n#define SCX_TASK_STATE_BITS __SCX_TASK_STATE_BITS\n\nconst volatile u64 __SCX_TASK_STATE_MASK __weak;\n#define SCX_TASK_STATE_MASK __SCX_TASK_STATE_MASK\n\nconst volatile u64 __SCX_TASK_CURSOR __weak;\n#define SCX_TASK_CURSOR __SCX_TASK_CURSOR\n\nconst volatile u64 __SCX_TASK_NONE __weak;\n#define SCX_TASK_NONE __SCX_TASK_NONE\n\nconst volatile u64 __SCX_TASK_INIT __weak;\n#define SCX_TASK_INIT __SCX_TASK_INIT\n\nconst volatile u64 __SCX_TASK_READY __weak;\n#define SCX_TASK_READY __SCX_TASK_READY\n\nconst volatile u64 __SCX_TASK_ENABLED __weak;\n#define SCX_TASK_ENABLED __SCX_TASK_ENABLED\n\nconst volatile u64 __SCX_TASK_NR_STATES __weak;\n#define SCX_TASK_NR_STATES __SCX_TASK_NR_STATES\n\nconst volatile u64 __SCX_TASK_DSQ_ON_PRIQ __weak;\n#define SCX_TASK_DSQ_ON_PRIQ __SCX_TASK_DSQ_ON_PRIQ\n\nconst volatile u64 __SCX_KICK_IDLE __weak;\n#define SCX_KICK_IDLE __SCX_KICK_IDLE\n\nconst volatile u64 __SCX_KICK_PREEMPT __weak;\n#define SCX_KICK_PREEMPT __SCX_KICK_PREEMPT\n\nconst volatile u64 __SCX_KICK_WAIT __weak;\n#define SCX_KICK_WAIT __SCX_KICK_WAIT\n\nconst volatile u64 __SCX_ENQ_WAKEUP __weak;\n#define SCX_ENQ_WAKEUP __SCX_ENQ_WAKEUP\n\nconst volatile u64 __SCX_ENQ_HEAD __weak;\n#define SCX_ENQ_HEAD __SCX_ENQ_HEAD\n\nconst volatile u64 __SCX_ENQ_PREEMPT __weak;\n#define SCX_ENQ_PREEMPT __SCX_ENQ_PREEMPT\n\nconst volatile u64 __SCX_ENQ_IMMED __weak;\n#define SCX_ENQ_IMMED __SCX_ENQ_IMMED\n\nconst volatile u64 __SCX_ENQ_REENQ __weak;\n#define SCX_ENQ_REENQ __SCX_ENQ_REENQ\n\nconst volatile u64 __SCX_ENQ_LAST __weak;\n#define SCX_ENQ_LAST __SCX_ENQ_LAST\n\nconst volatile u64 __SCX_ENQ_CLEAR_OPSS __weak;\n#define SCX_ENQ_CLEAR_OPSS __SCX_ENQ_CLEAR_OPSS\n\nconst volatile u64 __SCX_ENQ_DSQ_PRIQ __weak;\n#define SCX_ENQ_DSQ_PRIQ __SCX_ENQ_DSQ_PRIQ\n\nconst volatile u64 __SCX_DEQ_SCHED_CHANGE __weak;\n#define SCX_DEQ_SCHED_CHANGE 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Define struct user_exit_info which is shared between BPF and userspace parts\n * to communicate exit status and other information.\n *\n * Copyright (c) 2022 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2022 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2022 David Vernet <dvernet@meta.com>\n */\n\n#ifndef __USER_EXIT_INFO_BPF_H\n#define __USER_EXIT_INFO_BPF_H\n\n#ifndef LSP\n#include \"vmlinux.h\"\n#endif\n#include <bpf/bpf_core_read.h>\n\n#include \"user_exit_info_common.h\"\n\n#define UEI_DEFINE(__name)\t\t\t\t\t\t\t\\\n\tchar RESIZABLE_ARRAY(data, __name##_dump);\t\t\t\t\\\n\tconst volatile u32 __name##_dump_len;\t\t\t\t\t\\\n\tstruct user_exit_info __name SEC(\".data\")\n\n#define UEI_RECORD(__uei_name, __ei) ({\t\t\t\t\t\t\\\n\tbpf_probe_read_kernel_str(__uei_name.reason,\t\t\t\t\\\n\t\t\t\t sizeof(__uei_name.reason), (__ei)->reason);\t\\\n\tbpf_probe_read_kernel_str(__uei_name.msg,\t\t\t\t\\\n\t\t\t\t sizeof(__uei_name.msg), (__ei)->msg);\t\t\\\n\tbpf_probe_read_kernel_str(__uei_name##_dump,\t\t\t\t\\\n\t\t\t\t __uei_name##_dump_len, (__ei)->dump);\t\t\\\n\tif (bpf_core_field_exists((__ei)->exit_code))\t\t\t\t\\\n\t\t__uei_name.exit_code = (__ei)->exit_code;\t\t\t\\\n\t/* use __sync to force memory barrier */\t\t\t\t\\\n\t__sync_val_compare_and_swap(&__uei_name.kind, __uei_name.kind,\t\t\\\n\t\t\t\t (__ei)->kind);\t\t\t\t\\\n})\n\n#endif /* __USER_EXIT_INFO_BPF_H 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Define struct user_exit_info which is shared between BPF and userspace parts\n * to communicate exit status and other information.\n *\n * Copyright (c) 2022 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2022 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2022 David Vernet <dvernet@meta.com>\n */\n#ifndef __USER_EXIT_INFO_H\n#define __USER_EXIT_INFO_H\n\n#include <stdio.h>\n#include <stdbool.h>\n\n#include \"user_exit_info_common.h\"\n\n/* no need to call the following explicitly if SCX_OPS_LOAD() is used */\n#define UEI_SET_SIZE(__skel, __ops_name, __uei_name) ({\t\t\t\t\t\\\n\tu32 __len = (__skel)->struct_ops.__ops_name->exit_dump_len ?: UEI_DUMP_DFL_LEN;\t\\\n\t(__skel)->rodata->__uei_name##_dump_len = __len;\t\t\t\t\\\n\tRESIZE_ARRAY((__skel), data, __uei_name##_dump, __len);\t\t\t\t\\\n})\n\n#define UEI_EXITED(__skel, __uei_name) ({\t\t\t\t\t\\\n\t/* use __sync to force memory barrier */\t\t\t\t\\\n\t__sync_val_compare_and_swap(&(__skel)->data->__uei_name.kind, -1, -1);\t\\\n})\n\n#define UEI_REPORT(__skel, __uei_name) ({\t\t\t\t\t\\\n\tstruct user_exit_info *__uei = &(__skel)->data->__uei_name;\t\t\\\n\tchar *__uei_dump = (__skel)->data_##__uei_name##_dump->__uei_name##_dump; \\\n\tif (__uei_dump[0] != \'\\0\') {\t\t\t\t\t\t\\\n\t\tfputs(\"\\nDEBUG DUMP\\n\", stderr);\t\t\t\t\\\n\t\tfputs(\"================================================================================\\n\\n\", stderr); \\\n\t\tfputs(__uei_dump, stderr);\t\t\t\t\t\\\n\t\tfputs(\"\\n================================================================================\\n\\n\", stderr); \\\n\t}\t\t\t\t\t\t\t\t\t\\\n\tfprintf(stderr, \"EXIT: %s\", __uei->reason);\t\t\t\t\\\n\tif (__uei->msg[0] != \'\\0\')\t\t\t\t\t\t\\\n\t\tfprintf(stderr, \" (%s)\", __uei->msg);\t\t\t\t\\\n\tfputs(\"\\n\", stderr);\t\t\t\t\t\t\t\\\n\t__uei->exit_code;\t\t\t\t\t\t\t\\\n})\n\n/*\n * We can\'t import vmlinux.h while compiling user C code. Let\'s duplicate\n * scx_exit_code definition.\n */\nenum scx_exit_code {\n\t/* Reasons */\n\tSCX_ECODE_RSN_HOTPLUG\t\t= 1LLU << 32,\n\n\t/* Actions */\n\tSCX_ECODE_ACT_RESTART\t\t= 1LLU << 48,\n};\n\nenum uei_ecode_mask {\n\tUEI_ECODE_USER_MASK\t\t= ((1LLU << 32) - 1),\n\tUEI_ECODE_SYS_RSN_MASK\t\t= ((1LLU << 16) - 1) << 32,\n\tUEI_ECODE_SYS_ACT_MASK\t\t= ((1LLU << 16) - 1) << 48,\n};\n\n/*\n * These macro interpret the ecode returned from UEI_REPORT().\n */\n#define UEI_ECODE_USER(__ecode)\t\t((__ecode) & UEI_ECODE_USER_MASK)\n#define UEI_ECODE_SYS_RSN(__ecode)\t((__ecode) & UEI_ECODE_SYS_RSN_MASK)\n#define UEI_ECODE_SYS_ACT(__ecode)\t((__ecode) & UEI_ECODE_SYS_ACT_MASK)\n\n#define UEI_ECODE_RESTART(__ecode)\t(UEI_ECODE_SYS_ACT((__ecode)) == SCX_ECODE_ACT_RESTART)\n\n#endif\t/* __USER_EXIT_INFO_H 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Define struct scx_enums that stores the load-time values of enums\n * used by the BPF program.\n *\n * Copyright (c) 2024 Meta Platforms, Inc. and affiliates.\n */\n\n#ifndef __SCX_ENUMS_H\n#define __SCX_ENUMS_H\n\nstatic inline void __ENUM_set(u64 *val, char *type, char *name)\n{\n\tbool res;\n\n\tres = __COMPAT_read_enum(type, name, val);\n\tif (!res)\n\t\t*val = 0;\n}\n\n#define SCX_ENUM_SET(skel, type, name) do {\t\t\t\\\n\t__ENUM_set(&skel->rodata->__##name, #type, #name);\t\\\n\t} while (0)\n\n\n#include \"enums.autogen.h\"\n\n#endif /* __SCX_ENUMS_H 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n/* Copyright (c) 2024 Meta Platforms, Inc. and affiliates. */\n#pragma once\n\n#ifndef PAGE_SIZE\n#define PAGE_SIZE __PAGE_SIZE\n/*\n * for older kernels try sizeof(struct genradix_node)\n * or flexible:\n * static inline long __bpf_page_size(void) {\n * return bpf_core_enum_value(enum page_size_enum___l, __PAGE_SIZE___l) ?: sizeof(struct genradix_node);\n * }\n * but generated code is not great.\n */\n#endif\n\n#if defined(__BPF_FEATURE_ADDR_SPACE_CAST) && !defined(BPF_ARENA_FORCE_ASM)\n#ifndef __arena\n#define __arena __attribute__((address_space(1)))\n#endif\n#define __arena_global __attribute__((address_space(1)))\n#define cast_kern(ptr) /* nop for bpf prog. emitted by LLVM */\n#define cast_user(ptr) /* nop for bpf prog. emitted by LLVM */\n#else\n\n/* emit instruction:\n * rX = rX .off = BPF_ADDR_SPACE_CAST .imm32 = (dst_as << 16) | src_as\n *\n * This is a workaround for LLVM compiler versions without\n * __BPF_FEATURE_ADDR_SPACE_CAST that do not automatically cast between arena\n * pointers and native kernel/userspace ones. In this case we explicitly do so\n * with cast_kern() and cast_user(). E.g., in the Linux kernel tree,\n * tools/testing/selftests/bpf includes tests that use these macros to implement\n * linked lists and hashtables backed by arena memory. In sched_ext, we use\n * cast_kern() and cast_user() for compatibility with older LLVM toolchains.\n */\n#ifndef bpf_addr_space_cast\n#define bpf_addr_space_cast(var, dst_as, src_as)\\\n\tasm volatile(\".byte 0xBF;\t\t\\\n\t\t .ifc %[reg], r0;\t\t\\\n\t\t .byte 0x00;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r1;\t\t\\\n\t\t .byte 0x11;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r2;\t\t\\\n\t\t .byte 0x22;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r3;\t\t\\\n\t\t .byte 0x33;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r4;\t\t\\\n\t\t .byte 0x44;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r5;\t\t\\\n\t\t .byte 0x55;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r6;\t\t\\\n\t\t .byte 0x66;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r7;\t\t\\\n\t\t .byte 0x77;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r8;\t\t\\\n\t\t .byte 0x88;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r9;\t\t\\\n\t\t .byte 0x99;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .short %[off];\t\t\\\n\t\t .long %[as]\"\t\t\\\n\t\t : [reg]\"+r\"(var)\t\t\\\n\t\t : [off]\"i\"(BPF_ADDR_SPACE_CAST) \\\n\t\t , [as]\"i\"((dst_as << 16) | src_as));\n#endif\n\n#define __arena\n#define __arena_global SEC(\".addr_space.1\")\n#define cast_kern(ptr) bpf_addr_space_cast(ptr, 0, 1)\n#define cast_user(ptr) bpf_addr_space_cast(ptr, 1, 0)\n#endif\n\nvoid __arena* bpf_arena_alloc_pages(void *map, void __arena *addr, __u32 page_cnt,\n\t\t\t\t int node_id, __u64 flags) __ksym __weak;\nvoid bpf_arena_free_pages(void *map, void __arena *ptr, __u32 page_cnt) __ksym __weak;\nint bpf_arena_reserve_pages(void *map, void __arena *ptr, __u32 page_cnt) __ksym __weak;\n\n/*\n * Note that cond_break can only be portably used in the body of a breakable\n * construct, whereas can_loop can be used anywhere.\n */\n#ifdef SCX_BPF_UNITTEST\n#define can_loop true\n#define __cond_break(expr) expr\n#else\n#ifdef __BPF_FEATURE_MAY_GOTO\n#define can_loop\t\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tbool ret = true;\t\t\t\t\\\n\tasm volatile goto(\"may_goto %l[l_break]\"\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: ret = false;\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\tret;\t\t\t\t\t\t\\\n\t})\n\n#define __cond_break(expr)\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tasm volatile goto(\"may_goto %l[l_break]\"\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: expr;\t\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\t})\n#else\n#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n#define can_loop\t\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tbool ret = true;\t\t\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long ((%l[l_break] - 1b - 8) / 8) & 0xffff;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: ret = false;\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\tret;\t\t\t\t\t\t\\\n\t})\n\n#define __cond_break(expr)\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long ((%l[l_break] - 1b - 8) / 8) & 0xffff;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: expr;\t\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\t})\n#else\n#define can_loop\t\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tbool ret = true;\t\t\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long (((%l[l_break] - 1b - 8) / 8) & 0xffff) << 16;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: ret = false;\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\tret;\t\t\t\t\t\t\\\n\t})\n\n#define __cond_break(expr)\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long (((%l[l_break] - 1b - 8) / 8) & 0xffff) << 16;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: expr;\t\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\t})\n#endif /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */\n#endif /* __BPF_FEATURE_MAY_GOTO */\n#endif /* SCX_BPF_UNITTEST */\n\n#define cond_break __cond_break(break)\n#define cond_break_label(label) __cond_break(goto label)\n\n\nvoid bpf_preempt_disable(void) __weak __ksym;\nvoid bpf_preempt_enable(void) __weak __ksym;\nssize_t bpf_arena_mapping_nr_pages(void *p__map) __weak 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including /usr/include/gnu/stubs.h when\n * compiling BPF files although its content doesn\'t play any role. The file in\n * turn includes stubs-64.h or stubs-32.h depending on whether __x86_64__ is\n * defined. When compiling a BPF source, __x86_64__ isn\'t set and thus\n * stubs-32.h is selected. However, the file is not there if the system doesn\'t\n * have 32bit glibc devel package installed leading to a build failure.\n *\n * The problem is worked around by making this file available in the include\n * search paths before the system one when building BPF.\n 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Copyright (c) 2025 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2025 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2025 Emil Tsalapatis <etsal@meta.com>\n */\n#pragma once\n\n#ifdef __BPF__\n\n#include <bpf_arena_common.bpf.h>\n#include <bpf_arena_spin_lock.h>\n#include \"sdt_task_defs.h\"\n#endif\n\nstruct scx_stk_seg;\ntypedef struct scx_stk_seg __arena scx_stk_seg_t;\n\n#define SCX_STK_SEG_MAX (SDT_TASK_ENTS_PER_CHUNK - 2)\n\nstruct scx_stk_seg {\n\tvoid __arena\t*elems[SCX_STK_SEG_MAX];\n\tscx_stk_seg_t\t*prev;\n\tscx_stk_seg_t\t*next;\n};\n\n/*\n * Extensible stack struct.\n */\nstruct scx_stk {\n\tarena_spinlock_t __arena *lock;\n\n\tscx_stk_seg_t *first;\t/* First stack segment. */\n\tscx_stk_seg_t *last;\n\n\tscx_stk_seg_t *current;\t/* Current stack segment. */\n\t__u64 cind;\n\n\t__u64 capacity;\t\t/* Free slots in the stack. */\n\t__u64 available;\t/* Available items in the stack. */\n\t__u64 data_size;\n\t__u64 nr_pages_per_alloc;\n\n\tscx_stk_seg_t *reserve;\n};\n\n#ifdef __BPF__\n\nvoid __arena *scx_task_data(struct task_struct *p);\nint scx_task_init(__u64 data_size);\nvoid __arena *scx_task_alloc(struct task_struct *p);\nvoid scx_task_free(struct task_struct *p);\nvoid scx_arena_subprog_init(void);\n\nint scx_alloc_init(struct scx_allocator *alloc, __u64 data_size);\nu64 scx_alloc_internal(struct scx_allocator *alloc);\nint scx_alloc_free_idx(struct scx_allocator *alloc, __u64 idx);\n\n#define scx_alloc(alloc) ((struct sdt_data __arena *)scx_alloc_internal((alloc)))\n\nu64 scx_static_alloc_internal(size_t bytes, size_t alignment);\n#define scx_static_alloc(bytes, alignment) ((void __arena *)scx_static_alloc_internal((bytes), (alignment)))\nint scx_static_init(size_t max_alloc_pages);\n\nu64 scx_stk_alloc(struct scx_stk *stack);\nint scx_stk_init(struct scx_stk *stackp, __u64 data_size, __u64 nr_pages_per_alloc);\nint scx_stk_free_internal(struct scx_stk *stack, __u64 elem);\n\n#define scx_stk_free(stack, elem) scx_stk_free_internal(stack, (__u64)elem)\n\n/* Buddy allocator-related structs. */\n\nstruct scx_buddy_chunk;\ntypedef struct scx_buddy_chunk __arena scx_buddy_chunk_t;\n\nstruct scx_buddy_header;\ntypedef struct scx_buddy_header __arena scx_buddy_header_t;\n\nenum scx_buddy_consts {\n\tSCX_BUDDY_MIN_ALLOC_SHIFT\t= 4,\n\tSCX_BUDDY_MIN_ALLOC_BYTES\t= 1 << SCX_BUDDY_MIN_ALLOC_SHIFT,\n\tSCX_BUDDY_CHUNK_MAX_ORDER\t= 16,\n\tSCX_BUDDY_CHUNK_PAGES\t\t= (SCX_BUDDY_MIN_ALLOC_BYTES << SCX_BUDDY_CHUNK_MAX_ORDER) / PAGE_SIZE,\n\tSCX_BUDDY_CHUNK_ITEMS\t\t= SCX_BUDDY_CHUNK_PAGES * PAGE_SIZE / SCX_BUDDY_MIN_ALLOC_BYTES,\n\tSCX_BUDDY_CHUNK_OFFSET_MASK\t= (SCX_BUDDY_CHUNK_PAGES * PAGE_SIZE) - 1,\n};\n\nstruct scx_buddy_header {\n\tu32 prev_index;\t/* \"Pointer\" to the previous available allocation of the same size. */\n\tu32 next_index; /* Same for the next allocation. */\n};\n\n/*\n * We bring memory into the allocator 1MiB at a time.\n */\nstruct scx_buddy_chunk {\n\t/* The order of the current allocation for a item. 4 bits per order. */\n\tu8\t\t\torders[SCX_BUDDY_CHUNK_ITEMS / 2];\n\tu64\t\t\torder_indices[SCX_BUDDY_CHUNK_MAX_ORDER];\n\tscx_buddy_chunk_t\t*prev;\n\tscx_buddy_chunk_t\t*next;\n};\n\nstruct scx_buddy {\n\tscx_buddy_chunk_t *first_chunk;\t\t/* Pointer to the chunk linked list. */\n\tsize_t min_alloc_bytes;\t\t\t/* Minimum allocation in bytes */\n\tstruct scx_stk stack;\t\t\t/* Underlying stack page allocator. */\n\tstruct bpf_spin_lock lock;\n\n\t/* XXXETSAL: Track used pages, used to drain the underlying page stack. */\n};\n\nint scx_buddy_init(struct scx_buddy *buddy, size_t size);\nvoid scx_buddy_free_internal(struct scx_buddy *buddy, u64 free);\n#define scx_buddy_free(buddy, ptr) do { scx_buddy_free_internal((buddy), (u64)(ptr)); } while (0)\nu64 scx_buddy_alloc_internal(struct scx_buddy *buddy, size_t size);\n#define scx_buddy_alloc(alloc, size) ((void __arena *)scx_buddy_alloc_internal((alloc), (size)))\n\nstatic inline\nint scx_ffs(__u64 word)\n{\n\tunsigned int num = 0;\n\n\tif ((word & 0xffffffff) == 0) {\n\t\tnum += 32;\n\t\tword >>= 32;\n\t}\n\n\tif ((word & 0xffff) == 0) {\n\t\tnum += 16;\n\t\tword >>= 16;\n\t}\n\n\tif ((word & 0xff) == 0) {\n\t\tnum += 8;\n\t\tword >>= 8;\n\t}\n\n\tif ((word & 0xf) == 0) {\n\t\tnum += 4;\n\t\tword >>= 4;\n\t}\n\n\tif ((word & 0x3) == 0) {\n\t\tnum += 2;\n\t\tword >>= 2;\n\t}\n\n\tif ((word & 0x1) == 0) {\n\t\tnum += 1;\n\t\tword >>= 1;\n\t}\n\n\treturn num;\n}\n\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/percpu.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000006346\x0015172171634\x000011476\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#include <scx/common.bpf.h>\n#include <lib/cpumask.h>\n\nstruct scx_percpu_storage {\n\tstruct bpf_cpumask __kptr *bpfmask;\n\tscx_bitmap_t scx_bitmap;\n\tcpumask_t cpumask;\n\tstruct scx_bitmap scx_bitmap_stack;\n};\n\n/*\n * XXX Need protection against grabbing the same per-cpu temporary storage\n * twice, or this can lead to very nasty bugs.\n */\nstruct {\n\t__uint(type, BPF_MAP_TYPE_PERCPU_ARRAY);\n\t__type(key, u32);\n\t__type(value, struct scx_percpu_storage);\n\t__uint(max_entries, 1);\n} scx_percpu_storage_map __weak SEC(\".maps\");\n\nstatic s32 create_save_scx_bitmap(scx_bitmap_t *maskp)\n{\n\tscx_bitmap_t mask;\n\n\tmask = scx_bitmap_alloc();\n\tif (!mask)\n\t\treturn -ENOMEM;\n\n\tscx_bitmap_clear(mask);\n\n\t*maskp = mask;\n\n\treturn 0;\n}\n\nstatic s32 create_save_bpfmask(struct bpf_cpumask __kptr **kptr)\n{\n\tstruct bpf_cpumask *bpfmask;\n\n\tbpfmask = bpf_cpumask_create();\n\tif (!bpfmask) {\n\t\tbpf_printk(\"Failed to create bpfmask\");\n\t\treturn -ENOMEM;\n\t}\n\n\tbpfmask = bpf_kptr_xchg(kptr, bpfmask);\n\tif (bpfmask) {\n\t\tbpf_printk(\"kptr already had cpumask\");\n\t\tbpf_cpumask_release(bpfmask);\n\t}\n\n\treturn 0;\n}\n\n__weak int scx_storage_init_single(u32 cpu)\n{\n\tstruct scx_percpu_storage *storage;\n\tvoid *map = &scx_percpu_storage_map;\n\tconst u32 zero = 0;\n\tint ret;\n\n\tstorage = bpf_map_lookup_percpu_elem(map, &zero, cpu);\n\tif (!storage) {\n\t\t/* Should be impossible. */\n\t\tbpf_printk(\"Did not find map entry for cpu %d\", cpu);\n\t\treturn -EINVAL;\n\t}\n\n\tret = create_save_bpfmask(&storage->bpfmask);\n\tif (ret)\n\t\treturn ret;\n\n\treturn create_save_scx_bitmap(&storage->scx_bitmap);\n}\n\n__weak int scx_percpu_storage_init(void)\n{\n\tint ret, i;\n\n\tbpf_for(i, 0, nr_cpu_ids) {\n\t\tret = scx_storage_init_single(i);\n\t\tif (ret != 0)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic __maybe_unused\nstruct bpf_cpumask *scx_percpu_bpfmask(void)\n{\n\tstruct scx_percpu_storage *storage;\n\tvoid *map = &scx_percpu_storage_map;\n\tconst u32 zero = 0;\n\n\tstorage = bpf_map_lookup_elem(map, &zero);\n\tif (!storage) {\n\t\t/* Should be impossible. */\n\t\tbpf_printk(\"Did not find map entry\");\n\t\treturn NULL;\n\t}\n\n\tif (!storage->bpfmask)\n\t\tbpf_printk(\"Did not properly initialize singleton bpfmask\");\n\n\treturn storage->bpfmask;\n}\n\nstatic __maybe_unused\nscx_bitmap_t scx_percpu_scx_bitmap(void)\n{\n\tstruct scx_percpu_storage *storage;\n\tvoid *map = &scx_percpu_storage_map;\n\tconst u32 zero = 0;\n\n\tstorage = bpf_map_lookup_elem(map, &zero);\n\tif (!storage) {\n\t\t/* Should be impossible. */\n\t\tbpf_printk(\"Did not find map entry (bitmap)\");\n\t\treturn NULL;\n\t}\n\n\tif (!storage->scx_bitmap)\n\t\tbpf_printk(\"Did not properly initialize singleton scx_bitmap\");\n\n\treturn storage->scx_bitmap;\n}\n\nstatic __maybe_unused\ncpumask_t *scx_percpu_cpumask(void)\n{\n\tstruct scx_percpu_storage *storage;\n\tvoid *map = &scx_percpu_storage_map;\n\tconst u32 zero = 0;\n\n\tstorage = bpf_map_lookup_elem(map, &zero);\n\tif (!storage) {\n\t\t/* Should be impossible. */\n\t\tbpf_printk(\"Did not find map entry\");\n\t\treturn NULL;\n\t}\n\n\treturn &storage->cpumask;\n}\n\nstatic __maybe_unused\nstruct scx_bitmap *scx_percpu_scx_bitmap_stack(void)\n{\n\tstruct scx_percpu_storage *storage;\n\tvoid *map = &scx_percpu_storage_map;\n\tconst u32 zero = 0;\n\n\tstorage = bpf_map_lookup_elem(map, &zero);\n\tif (!storage) {\n\t\t/* Should be impossible. */\n\t\tbpf_printk(\"Did not find map entry\");\n\t\treturn NULL;\n\t}\n\n\treturn &storage->scx_bitmap_stack;\n}\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/rbtree.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000004466\x0015172171634\x000011464\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#ifdef __BPF__\n#include <scx/common.bpf.h>\n#include <bpf_arena_common.bpf.h>\n#include <bpf_arena_spin_lock.h>\n#endif /* __BPF__ */\n\n#include <lib/sdt_task.h>\n\n#define RB_MAXLVL_PRINT (16)\n\nstruct rbnode;\n\ntypedef struct rbnode __arena rbnode_t;\n\nstruct rbnode {\n\tunion sdt_id tid;\n\trbnode_t *parent;\n\tunion {\n\t\tstruct {\n\t\t\trbnode_t *left;\n\t\t\trbnode_t *right;\n\t\t};\n\n\t\trbnode_t *child[2];\n\t};\n\tuint64_t key;\n\t/* Used as a linked list or to store KV pairs. */\n\tunion {\n\t\trbnode_t *next;\n\t\tuint64_t value;\n\t};\n\tbool is_red;\n};\n\n/* \n * Does the rbtree allocate is own nodes, or do they get\n * allocated by the caller?\n */\nenum rbtree_alloc {\n\tRB_ALLOC,\n\tRB_NOALLOC,\n};\n\n/*\n * Specify the behavior of rbtree insertions when the key is\n * already present in the tree.\n *\n * RB_DEFAULT: Default behavior, reject the new insert.\n *\n * RB_UPDATE: Update the existing value in the rbtree.\n * This updates the node itself, not just the value in\n * the existing node.\n *\n * RB_DUPLICATE: Allow nodes with identical keys in the rbtree.\n * Finding/popping/removing a key acts on any of the nodes\n * with the appropriate key - there is no ordering by time\n * of insertion.\n */\nenum rbtree_insert_mode {\n\tRB_DEFAULT,\n\tRB_UPDATE,\n\tRB_DUPLICATE,\n};\n\nstruct rbtree {\n\tunion sdt_id tid;\n\trbnode_t *root;\n\trbnode_t *freelist;\n\tenum rbtree_alloc alloc;\n\tenum rbtree_insert_mode insert;\n};\n\ntypedef struct rbtree __arena rbtree_t;\n\nint scx_rb_init(void);\n\n#ifdef __BPF__\nu64 rb_create_internal(enum rbtree_alloc alloc, enum rbtree_insert_mode insert);\n#define rb_create(alloc, insert) ((rbtree_t *)rb_create_internal((alloc), (insert)))\n\nint rb_destroy(rbtree_t __arg_arena *rbtree);\nint rb_insert(rbtree_t *rbtree, u64 key, u64 value);\nint rb_remove(rbtree_t *rbtree, u64 key);\nint rb_find(rbtree_t *rbtree, u64 key, u64 *value);\nint rb_print(rbtree_t *rbtree);\nint rb_least(rbtree_t *rbtree, u64 *key, u64 *value);\nint rb_pop(rbtree_t *rbtree, u64 *key, u64 *value);\n\nint rb_insert_node(rbtree_t *rbtree, rbnode_t *node);\nint rb_remove_node(rbtree_t *rbtree, rbnode_t *node);\nu64 rb_node_alloc_internal(rbtree_t *rbtree, u64 key, u64 value);\n#define rb_node_alloc(rbtree, key, value) ((rbnode_t *)rb_node_alloc_internal((rbtree), (key), (value)))\nint rb_node_free(rbtree_t *rbtree, rbnode_t *rbnode);\n\nint rb_integrity_check(rbtree_t *rbtree);\n\n#endif /* __BPF__ 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#ifndef __SCX_RAVG_BPF_H__\n#define __SCX_RAVG_BPF_H__\n\n/*\n * Running average helpers to be used in BPF progs. Assumes vmlinux.h has\n * already been included.\n */\nenum ravg_consts {\n\tRAVG_VAL_BITS\t\t= 44,\t\t/* input values are 44bit */\n\tRAVG_FRAC_BITS\t\t= 20,\t\t/* 1048576 is 1.0 */\n};\n\n#ifdef __BPF__\n\n#ifndef __arena\n#define __arena __attribute__((address_space(1)))\n#endif /* __arena */\n\n/*\n * Running avg mechanism. Accumulates values between 0 and RAVG_MAX_VAL in\n * arbitrary time intervals. The accumulated values are halved every half_life\n * with each period starting when the current time % half_life is 0. Zeroing is\n * enough for initialization.\n *\n * See ravg_accumulate() and ravg_read() for more details.\n */\nstruct ravg_data {\n\t/* current value */\n\tu64\t\t\tval;\n\n\t/*\n\t * The timestamp of @val. The latest completed seq #:\n\t *\n\t * (val_at / half_life) - 1\n\t */\n\tu64\t\t\tval_at;\n\n\t/* running avg as of the latest completed seq */\n\tu64\t\t\told;\n\n\t/*\n\t * Accumulated value of the current period. Input value is 48bits and we\n\t * normalize half-life to 16bit, so it should fit in a u64.\n\t */\n\tu64\t\t\tcur;\n};\n\n#define RAVG_FN_ATTRS __attribute__((unused, always_inline))\n\nint ravg_scale(struct ravg_data *rd, u32 mult, u32 rshift);\nu64 ravg_read(struct ravg_data *rd, u64 now, u64 half_life);\nint ravg_accumulate(struct ravg_data *rd, u64 new_val, u64 now, u32 half_life);\n\nstatic RAVG_FN_ATTRS void ravg_add(u64 *sum, u64 addend)\n{\n\tu64 new = *sum + addend;\n\n\tif (new >= *sum)\n\t\t*sum = new;\n\telse\n\t\t*sum = -1;\n}\n\nstatic RAVG_FN_ATTRS inline u64 ravg_decay(u64 v, u32 shift)\n{\n\tif (shift >= 64)\n\t\treturn 0;\n\telse\n\t\treturn v >> shift;\n}\n\nstatic RAVG_FN_ATTRS u32 ravg_normalize_dur(u32 dur, u32 half_life)\n{\n\tif (dur < half_life)\n\t\treturn (((u64)dur << RAVG_FRAC_BITS) + half_life - 1) /\n\t\t\thalf_life;\n\telse\n\t\treturn 1 << RAVG_FRAC_BITS;\n}\n\n/**\n * ravg_transfer - Transfer in or out a component running avg\n * @base: ravg_data to transfer @xfer into or out of\n * @base_new_val: new value for @base\n * @xfer: ravg_data to transfer\n * @xfer_new_val: new value for @xfer\n * @is_xfer_in: transfer direction\n *\n * An ravg may be a sum of component ravgs. For example, a scheduling domain\'s\n * load is the sum of the load values of all member tasks. If a task is migrated\n * to a different domain, its contribution should be subtracted from the source\n * ravg and added to the destination one.\n *\n * This function can be used for such component transfers. Both @base and @xfer\n * must have been accumulated at the same timestamp. @xfer\'s contribution is\n * subtracted if @is_fer_in is %false and added if %true.\n */\nstatic RAVG_FN_ATTRS void ravg_transfer(struct ravg_data *base, u64 base_new_val,\n\t\t\t\t\tstruct ravg_data *xfer, u64 xfer_new_val,\n\t\t\t\t\tu32 half_life, bool is_xfer_in)\n{\n\t/* synchronize @base and @xfer */\n\tif ((s64)(base->val_at - xfer->val_at) < 0)\n\t\travg_accumulate(base, base_new_val, xfer->val_at, half_life);\n\telse if ((s64)(base->val_at - xfer->val_at) > 0)\n\t\travg_accumulate(xfer, xfer_new_val, base->val_at, half_life);\n\n\t/* transfer */\n\tif (is_xfer_in) {\n\t\tbase->old += xfer->old;\n\t\tbase->cur += xfer->cur;\n\t} else {\n\t\tif (base->old > xfer->old)\n\t\t\tbase->old -= xfer->old;\n\t\telse\n\t\t\tbase->old = 0;\n\n\t\tif (base->cur > xfer->cur)\n\t\t\tbase->cur -= xfer->cur;\n\t\telse\n\t\t\tbase->cur = 0;\n\t}\n}\n\nstatic RAVG_FN_ATTRS int ravg_to_arena(struct ravg_data __arena *to, struct ravg_data *from)\n{\n\t*to = *from;\n\n\treturn 0;\n}\n\n\nstatic RAVG_FN_ATTRS int ravg_from_arena(struct ravg_data *to, struct ravg_data __arena *from)\n{\n\t*to = *from;\n\n\treturn 0;\n}\n\n#endif /* __BPF__ */\n\n#endif /* __SCX_RAVG_BPF_H__ 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#include <scx/common.bpf.h>\n#include <bpf_arena_common.bpf.h>\n#include <bpf_arena_spin_lock.h>\n\n#define BT_MAXLVL_PRINT (10)\n#define BT_LEAFSZ 10\n\n#define BT_F_LEAF (0x1)\n\nstruct bt_node;\ntypedef struct bt_node __arena bt_node;\n\nstruct bt_node {\n\tu64 keys[BT_LEAFSZ];\n\tu64 values[BT_LEAFSZ];\n\tu64 flags;\n\tu64 numkeys;\n\tbt_node *parent;\n};\n\nstruct btree {\n\tbt_node *root;\n\tbt_node *freelist;\n\t/* XXXETSAL Locking */\n};\n\ntypedef struct btree __arena btree_t;\n\nu64 bt_create_internal(void);\n#define bt_create() ((btree_t *)(bt_create_internal()))\n\nint bt_destroy(btree_t *btree);\nint bt_insert(btree_t *btree, u64 key, u64 value, bool update);\nint bt_remove(btree_t *btree, u64 key);\nint bt_find(btree_t *btree, u64 key, u64 *value);\nint bt_print(btree_t *btree);\n\n/* XXXETSAL Iterators */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/pmu.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000000547\x0015172171634\x000010776\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\nint scx_pmu_install(u64 event);\nint scx_pmu_uninstall(u64 event);\n\nint scx_pmu_task_init(struct task_struct *p);\nint scx_pmu_task_fini(struct task_struct *p);\n\nint scx_pmu_event_start(struct task_struct *p, bool update);\nint scx_pmu_event_stop(struct task_struct *p);\n\nint scx_pmu_read(struct task_struct *p, u64 event, u64 *value, bool clear);\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/dhq.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000012421\x0015172171634\x000010743\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#ifdef __BPF__\n#include <scx/common.bpf.h>\n#include <bpf_arena_common.bpf.h>\n#include <bpf_arena_spin_lock.h>\n#endif /* __BPF__ */\n\n#include <lib/minheap.h>\n\n#define SCX_DHQ_INF_CAPACITY ((u64)-1)\n\n/* Dequeue modes */\n#define SCX_DHQ_MODE_ALTERNATING\t0\n#define SCX_DHQ_MODE_PRIORITY\t\t1\n#define SCX_DHQ_MODE_BALANCED\t\t2\n\n/* Strand identifiers */\n#define SCX_DHQ_STRAND_A\t\t0\n#define SCX_DHQ_STRAND_B\t\t1\n#define SCX_DHQ_STRAND_AUTO\t\t2 /* Auto-select based on balancing */\n\n/**\n * scx_dhq - Double Helix Queue\n *\n * A queue structure inspired by DNA\'s double helix with two intertwined\n * strands. Tasks can be enqueued to either strand and dequeued according\n * to different strategies (alternating, priority-based, or balanced).\n *\n * For cross-LLC task migration, strands typically represent the two LLCs\n * sharing the queue. The max_imbalance constraint applies only to enqueue\n * (based on size) to prevent one LLC from flooding the DHQ. On dequeue,\n * asymmetric consumption is allowed so idle LLCs can freely steal work\n * from busy LLCs without being blocked by imbalance constraints.\n *\n * @strand_a: Min heap for strand A\n * @strand_b: Min heap for strand B\n * @lock: Arena spinlock for thread-safety\n * @capacity: Total capacity across both strands\n * @size_a: Number of tasks in strand A\n * @size_b: Number of tasks in strand B\n * @seq_a: Sequence number for strand A (FIFO mode)\n * @seq_b: Sequence number for strand B (FIFO mode)\n * @dequeue_count_a: Number of dequeues from strand A (tracking only)\n * @dequeue_count_b: Number of dequeues from strand B (tracking only)\n * @max_imbalance: Maximum size difference on enqueue (0 = no limit)\n * @fifo: FIFO mode flag (1 = FIFO, 0 = priority/vtime)\n * @last_strand: Last strand dequeued from (for alternating mode)\n * @mode: Dequeue mode (ALTERNATING, PRIORITY, or BALANCED)\n */\nstruct scx_dhq {\n\tscx_minheap_t *strand_a;\n\tscx_minheap_t *strand_b;\n\tarena_spinlock_t lock;\n\tu64 capacity;\n\tu64 size_a;\n\tu64 size_b;\n\tu64 seq_a;\n\tu64 seq_b;\n\tu64 dequeue_count_a;\n\tu64 dequeue_count_b;\n\tu64 max_imbalance;\n\tu8 fifo;\n\tu8 last_strand;\n\tu8 mode;\n};\n\ntypedef struct scx_dhq __arena scx_dhq_t;\n\n#ifdef __BPF__\n/**\n * scx_dhq_create_internal - Create a double helix queue\n * @fifo: true for FIFO mode, false for vtime/priority mode\n * @capacity: Total capacity (SCX_DHQ_INF_CAPACITY for unlimited)\n * @mode: Dequeue mode (ALTERNATING, PRIORITY, or BALANCED)\n * @max_imbalance: Maximum size difference allowed on enqueue (0 for unlimited)\n * NOTE: Only applies to enqueue, not dequeue. This prevents\n * one strand from flooding the queue while allowing asymmetric\n * consumption on dequeue for efficient cross-LLC work stealing.\n *\n * Returns: Pointer to scx_dhq_t or NULL on failure\n */\nu64 scx_dhq_create_internal(bool fifo, size_t capacity, u64 mode, u64 max_imbalance);\n\n#define scx_dhq_create(fifo, mode) \\\n\tscx_dhq_create_internal((fifo), SCX_DHQ_INF_CAPACITY, (mode), 0)\n\n#define scx_dhq_create_size(fifo, capacity, mode) \\\n\tscx_dhq_create_internal((fifo), (capacity), (mode), 0)\n\n#define scx_dhq_create_balanced(fifo, capacity, mode, max_imbalance) \\\n\tscx_dhq_create_internal((fifo), (capacity), (mode), (max_imbalance))\n\n/**\n * scx_dhq_insert - Insert task into DHQ in FIFO mode\n * @dhq_ptr: Pointer to double helix queue\n * @taskc_ptr: Pointer to task context\n * @strand: Target strand (STRAND_A, STRAND_B, or STRAND_AUTO)\n *\n * Returns: 0 on success, negative error code on failure\n */\nint scx_dhq_insert(scx_dhq_t *dhq_ptr, u64 taskc_ptr, u64 strand);\n\n/**\n * scx_dhq_insert_vtime - Insert task into DHQ with vtime/priority\n * @dhq: Pointer to double helix queue\n * @taskc_ptr: Pointer to task context\n * @vtime: Virtual time / priority value\n * @strand: Target strand (STRAND_A, STRAND_B, or STRAND_AUTO)\n *\n * Returns: 0 on success, negative error code on failure\n */\nint scx_dhq_insert_vtime(scx_dhq_t *dhq, u64 taskc_ptr, u64 vtime, u64 strand);\n\n/**\n * scx_dhq_nr_queued - Get total number of queued tasks\n * @dhq: Pointer to double helix queue\n *\n * Returns: Total number of tasks in both strands\n */\nint scx_dhq_nr_queued(scx_dhq_t *dhq);\n\n/**\n * scx_dhq_nr_queued_strand - Get number of queued tasks in specific strand\n * @dhq: Pointer to double helix queue\n * @strand: Target strand (STRAND_A or STRAND_B)\n *\n * Returns: Number of tasks in specified strand\n */\nint scx_dhq_nr_queued_strand(scx_dhq_t *dhq, u64 strand);\n\n/**\n * scx_dhq_pop - Dequeue task according to queue mode\n * @dhq: Pointer to double helix queue\n *\n * Returns: Task context pointer or NULL if empty\n */\nu64 scx_dhq_pop(scx_dhq_t *dhq);\n\n/**\n * scx_dhq_pop_strand - Dequeue task from specific strand\n * @dhq: Pointer to double helix queue\n * @strand: Target strand (STRAND_A or STRAND_B)\n *\n * Returns: Task context pointer or NULL if strand is empty\n */\nu64 scx_dhq_pop_strand(scx_dhq_t *dhq, u64 strand);\n\n/**\n * scx_dhq_peek - Peek at next task without removing it\n * @dhq: Pointer to double helix queue\n *\n * Returns: Task context pointer or NULL if empty\n */\nu64 scx_dhq_peek(scx_dhq_t *dhq);\n\n/**\n * scx_dhq_peek_strand - Peek at next task in specific strand\n * @dhq: Pointer to double helix queue\n * @strand: Target strand (STRAND_A or STRAND_B)\n *\n * Returns: Task context pointer or NULL if strand is empty\n */\nu64 scx_dhq_peek_strand(scx_dhq_t *dhq, u64 strand);\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/cpumask.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000004762\x0015172171634\x000011643\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n#include <scx/common.bpf.h>\n\n#include <lib/sdt_task.h>\n\n#define SCXMASK_NLONG (512 / 8)\n\nstruct scx_bitmap {\n\tunion sdt_id tid;\n\tu64 bits[SCXMASK_NLONG];\n};\n\ntypedef struct scx_bitmap __arena * __arg_arena scx_bitmap_t;\n\nconst extern volatile u32 nr_cpu_ids;\n\n/* Mask size in 64-bit words. */\nextern size_t mask_size;\n\nint scx_bitmap_init(__u64 total_mask_size);\nu64 scx_bitmap_alloc_internal(void);\n#define scx_bitmap_alloc() ( (scx_bitmap_t) scx_bitmap_alloc_internal() )\nint scx_bitmap_free(scx_bitmap_t __arg_arena mask);\n\nint scx_bitmap_copy_to_stack(struct scx_bitmap *dst, scx_bitmap_t __arg_arena src);\nint scx_bitmap_to_bpf(struct bpf_cpumask __kptr *bpfmask __arg_trusted, scx_bitmap_t __arg_arena scx_bitmap);\n\nint scx_bitmap_set_cpu(u32 cpu, scx_bitmap_t __arg_arena mask);\nint scx_bitmap_clear_cpu(u32 cpu, scx_bitmap_t __arg_arena mask);\nbool scx_bitmap_test_cpu(u32 cpu, scx_bitmap_t __arg_arena mask);\nbool scx_bitmap_test_and_clear_cpu(u32 cpu, scx_bitmap_t __arg_arena mask);\n\nint scx_bitmap_clear(scx_bitmap_t __arg_arena mask);\nint scx_bitmap_and(scx_bitmap_t __arg_arena dst, scx_bitmap_t __arg_arena src1, scx_bitmap_t __arg_arena src2);\nint scx_bitmap_or(scx_bitmap_t __arg_arena dst, scx_bitmap_t __arg_arena src1, scx_bitmap_t __arg_arena src2);\nbool scx_bitmap_empty(scx_bitmap_t __arg_arena mask);\nint scx_bitmap_copy(scx_bitmap_t __arg_arena dst, scx_bitmap_t __arg_arena src);\n\nint scx_bitmap_from_bpf(scx_bitmap_t __arg_arena scx_bitmap, const cpumask_t *bpfmask __arg_trusted);\nint scx_bitmap_and_cpumask(scx_bitmap_t dst __arg_arena, scx_bitmap_t scx __arg_arena,\n\t\t\t const struct cpumask *bpf __arg_trusted);\n\nbool scx_bitmap_intersects(scx_bitmap_t __arg_arena arg1, scx_bitmap_t __arg_arena arg2);\nbool scx_bitmap_intersects_cpumask(scx_bitmap_t __arg_arena scx, const struct cpumask *bpf __arg_trusted);\nbool scx_bitmap_subset(scx_bitmap_t __arg_arena big, scx_bitmap_t __arg_arena small);\nbool scx_bitmap_subset_cpumask(scx_bitmap_t __arg_arena big, const struct cpumask *small __arg_trusted);\nint scx_bitmap_print(scx_bitmap_t __arg_arena mask);\n\ns32 scx_bitmap_pick_idle_cpu(scx_bitmap_t mask __arg_arena, int flags);\ns32 scx_bitmap_any_distribute(scx_bitmap_t mask __arg_arena);\ns32 scx_bitmap_any_and_distribute(scx_bitmap_t scx __arg_arena, const struct cpumask *bpf);\ns32 scx_bitmap_pick_any_cpu(scx_bitmap_t mask __arg_arena);\ns32 scx_bitmap_pick_any_cpu_from(scx_bitmap_t __arg_arena mask, u64 __arg_arena *start);\ns32 scx_bitmap_vacate_cpu(scx_bitmap_t __arg_arena mask, s32 cpu);\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000040755\x000001751\x000001751\x0000000000000\x0015172171634\x000011034\x005\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n/* Buddy allocator-related structs. */\n\nstruct buddy_chunk;\ntypedef struct buddy_chunk __arena buddy_chunk_t;\n\nstruct buddy_header;\ntypedef struct buddy_header __arena buddy_header_t;\n\nenum buddy_consts {\n\tBUDDY_MIN_ALLOC_SHIFT\t= 4,\n\tBUDDY_MIN_ALLOC_BYTES\t= 1 << BUDDY_MIN_ALLOC_SHIFT,\n\tBUDDY_CHUNK_NUM_ORDERS\t= 1 << 4,\t/* 4 bits per order */\n\tBUDDY_CHUNK_BYTES\t= BUDDY_MIN_ALLOC_BYTES << BUDDY_CHUNK_NUM_ORDERS,\n\tBUDDY_HEADER_OFF\t= 8, /* header byte offset, see buddy.bpf.c for details */\n\tBUDDY_CHUNK_PAGES\t= BUDDY_CHUNK_BYTES / PAGE_SIZE,\n\tBUDDY_CHUNK_ITEMS\t= 1 << BUDDY_CHUNK_NUM_ORDERS,\n\tBUDDY_CHUNK_OFFSET_MASK\t= BUDDY_CHUNK_BYTES - 1,\n\tBUDDY_VADDR_OFFSET\t= BUDDY_CHUNK_BYTES,\t/* Start aligning at chunk */\n\tBUDDY_VADDR_SIZE\t= BUDDY_CHUNK_BYTES << 10 /* 1024 chunks maximum */\n};\n\nstruct buddy_header {\n\tu32 prev_index;\t/* \"Pointer\" to the previous available allocation of the same size. */\n\tu32 next_index; /* Same for the next allocation. */\n};\n\n/*\n * We bring memory into the allocator 1MiB at a time.\n */\nstruct buddy_chunk {\n\t/* The order of the current allocation for a item. 4 bits per order. */\n\tu8\t\torders[BUDDY_CHUNK_ITEMS / 2];\n\t/* \n\t * Bit to denote whether chunk is allocated. Size of the allocated/free\n\t * chunk found from the orders array.\n\t */\n\tu8\t\tallocated[BUDDY_CHUNK_ITEMS / 8];\n\t/* Freelists for O(1) allocation. */\n\tu64\t\tfreelists[BUDDY_CHUNK_NUM_ORDERS];\n\tbuddy_chunk_t\t*prev;\n\tbuddy_chunk_t\t*next;\n};\n\nstruct buddy {\n\tbuddy_chunk_t *first_chunk;\t\t/* Pointer to the chunk linked list. */\n\tarena_spinlock_t __arena *lock;\t\t/* Allocator lock */\n\tu64 vaddr;\t\t\t\t/* Allocation into reserved vaddr */\n};\n\n#ifdef __BPF__\n\nint buddy_init(struct buddy *buddy, arena_spinlock_t __arena *lock);\nint buddy_destroy(struct buddy *buddy);\nint buddy_free_internal(struct buddy *buddy, u64 free);\n#define buddy_free(buddy, ptr) do { buddy_free_internal((buddy), (u64)(ptr)); } while (0)\nu64 buddy_alloc_internal(struct buddy *buddy, size_t size);\n#define buddy_alloc(alloc, size) ((void __arena *)buddy_alloc_internal((alloc), (size)))\n\n\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc/bpf_arena_common.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000004360\x0015172171634\x000014551\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n/* Copyright (c) 2024 Meta Platforms, Inc. and affiliates. */\n#pragma once\n\n#ifndef WRITE_ONCE\n#define WRITE_ONCE(x, val) ((*(volatile typeof(x) *) &(x)) = (val))\n#endif\n\n#ifndef NUMA_NO_NODE\n#define\tNUMA_NO_NODE\t(-1)\n#endif\n\n#ifndef arena_container_of\n#define arena_container_of(ptr, type, member)\t\t\t\\\n\t({\t\t\t\t\t\t\t\\\n\t\tvoid __arena *__mptr = (void __arena *)(ptr);\t\\\n\t\t((type *)(__mptr - offsetof(type, member)));\t\\\n\t})\n#endif\n\n#ifdef __BPF__ /* when compiled as bpf program */\n\n#ifndef PAGE_SIZE\n#define PAGE_SIZE __PAGE_SIZE\n/*\n * for older kernels try sizeof(struct genradix_node)\n * or flexible:\n * static inline long __bpf_page_size(void) {\n * return bpf_core_enum_value(enum page_size_enum___l, __PAGE_SIZE___l) ?: sizeof(struct genradix_node);\n * }\n * but generated code is not great.\n */\n#endif\n\n#if defined(__BPF_FEATURE_ADDR_SPACE_CAST) && !defined(BPF_ARENA_FORCE_ASM)\n#define __arena __attribute__((address_space(1)))\n#define __arena_global __attribute__((address_space(1)))\n#define cast_kern(ptr) /* nop for bpf prog. emitted by LLVM */\n#define cast_user(ptr) /* nop for bpf prog. emitted by LLVM */\n#else\n#define __arena\n#define __arena_global SEC(\".addr_space.1\")\n#define cast_kern(ptr) bpf_addr_space_cast(ptr, 0, 1)\n#define cast_user(ptr) bpf_addr_space_cast(ptr, 1, 0)\n#endif\n\nvoid __arena* bpf_arena_alloc_pages(void *map, void __arena *addr, __u32 page_cnt,\n\t\t\t\t int node_id, __u64 flags) __ksym __weak;\nint bpf_arena_reserve_pages(void *map, void __arena *addr, __u32 page_cnt) __ksym __weak;\nvoid bpf_arena_free_pages(void *map, void __arena *ptr, __u32 page_cnt) __ksym __weak;\n\n#define arena_base(map) ((void __arena *)((struct bpf_arena *)(map))->user_vm_start)\n\n#else /* when compiled as user space code */\n\n#define __arena\n#define __arg_arena\n#define cast_kern(ptr) /* nop for user space */\n#define cast_user(ptr) /* nop for user space */\n__weak char arena[1];\n\n#ifndef offsetof\n#define offsetof(type, member) ((unsigned long)&((type *)0)->member)\n#endif\n\nstatic inline void __arena* bpf_arena_alloc_pages(void *map, void *addr, __u32 page_cnt,\n\t\t\t\t\t\t int node_id, __u64 flags)\n{\n\treturn NULL;\n}\nstatic inline void bpf_arena_free_pages(void *map, void __arena *ptr, __u32 page_cnt)\n{\n}\n\n#endif\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc/stack.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000002144\x0015172171634\x000012367\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\nstruct stk_seg;\ntypedef struct stk_seg __arena stk_seg_t;\n\n/*\n * We devote a single page to stk_seg, and size\n * the void * array so it fits exactly in it.\n * Account for prev/next pointers (2 * sizeof(void *)).\n */\n#define STK_SEG_MAX ((PAGE_SIZE - 2 * sizeof(void *)) / sizeof(void *))\n\nstruct stk_seg {\n\tvoid __arena\t*elems[STK_SEG_MAX];\n\tstk_seg_t\t*prev;\n\tstk_seg_t\t*next;\n};\n\n/*\n * Extensible stack struct.\n */\nstruct stk {\n\tarena_spinlock_t __arena *lock;\n\n\tstk_seg_t *first;\t/* First stack segment. */\n\tstk_seg_t *last;\n\n\tstk_seg_t *current;\t/* Current stack segment. */\n\t__u64 cind;\n\n\t__u64 capacity;\t\t/* Free slots in the stack. */\n\t__u64 available;\t/* Available items in the stack. */\n\t__u64 data_size;\n\t__u64 nr_pages_per_alloc;\n\n\tstk_seg_t *reserve;\n};\n\n\n#ifdef __BPF__\n\nu64 stk_alloc(struct stk *stack);\nint stk_init(struct stk *stackp, arena_spinlock_t __arena *lock,\n\t\t__u64 data_size, __u64 nr_pages_per_alloc);\nvoid stk_destroy(struct stk *stack);\nint stk_free_internal(struct stk *stack, __u64 elem);\n\n#define stk_free(stack, elem) stk_free_internal(stack, (__u64)elem)\n\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc/userapi.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000000415\x0015172171634\x000012731\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#define __arena\n#define PAGE_SIZE (1ULL << 12)\n\ntypedef uint8_t u8;\ntypedef uint16_t u16;\ntypedef uint32_t u32;\ntypedef uint64_t u64;\ntypedef int8_t s8;\ntypedef int16_t s16;\ntypedef int32_t s32;\ntypedef int64_t s64;\n\n#include \"common.h\"\n#include \"asan.h\"\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc/bump.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000000657\x0015172171634\x000012234\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#ifdef __BPF__\n\nu64 bump_alloc_internal(size_t bytes, size_t alignment);\n#define bump_alloc(bytes, alignment) ((void __arena *)bump_alloc_internal((bytes), (alignment)))\nint bump_init(size_t max_alloc_pages);\nint bump_destroy(void);\nint bump_memlimit(u64 lim_memusage);\n\n#endif /* __BPF__ */\n\nstruct bump {\n\tsize_t max_contig_bytes;\n\tvoid __arena *memory;\n\tsize_t off;\n\tsize_t lim_memusage;\n\tsize_t cur_memusage;\n};\n\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc/common.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000004467\x0015172171634\x000012564\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#ifdef __BPF__\n\n#define BPF_NO_KFUNC_PROTOTYPES\n\n#include <bpf_experimental.h>\n#include <bpf_arena_common.h>\n#include <bpf_arena_spin_lock.h>\n#include \"bpf_helpers_local.h\"\n\n#include <asm-generic/errno.h>\n\n#ifndef __BPF_FEATURE_ADDR_SPACE_CAST\n#error \"Arena allocators only require bpf_addr_space_cast feature\"\n#endif\n\n#define arena_stdout(fmt, ...) bpf_stream_printk(1, (fmt), ##__VA_ARGS__)\n#define arena_stderr(fmt, ...) bpf_stream_printk(2, (fmt), ##__VA_ARGS__)\n\n#define DIAG() (arena_stderr(\"%s:%d\\n\", __func__, __LINE__))\n\nstatic inline void\narena_bug_trigger(const char *func, const int line)\n{\n\tvolatile u8 __arena *nullptr = (u8 __arena *)0ULL;\n\n\t*nullptr = 0;\n}\n\nint arena_fls(__u64 word);\n\nextern volatile u64 asan_violated;\n\n#ifndef div_round_up\n#define div_round_up(a, b) (((a) + (b) - 1) / (b))\n#endif\n\n#ifndef round_up\n#define round_up(a, b) ((((a) + (b) - 1) / (b)) * b)\n#endif\n\n#ifndef __maybe_unused\n#define __maybe_unused __attribute__((__unused__))\n#endif\n\n#define private(name) SEC(\".data.\" #name) __hidden __attribute__((aligned(8)))\n\n/* How many pages do we reserve at the beginning of the arena segment? */\n#define RESERVE_ALLOC (8)\n\nstruct {\n\t__uint(type, BPF_MAP_TYPE_ARENA);\n\t__uint(map_flags, BPF_F_MMAPABLE);\n#if defined(__TARGET_ARCH_arm64) || defined(__aarch64__)\n\t__uint(max_entries, 1 << 16); /* number of pages */\n __ulong(map_extra, (1ull << 32)); /* start of mmap() region */\n#else\n\t__uint(max_entries, 1 << 20); /* number of pages */\n __ulong(map_extra, (1ull << 44)); /* start of mmap() region */\n#endif\n} arena __weak SEC(\".maps\");\n\n#endif /* __BPF__ */\n\nstruct arena_get_base_args {\n\tvoid __arena *arena_base;\n};\n\n#ifdef __BPF__\n\nSEC(\"syscall\") __weak\nint arena_get_base(struct arena_get_base_args *args)\n{\n\targs->arena_base = arena_base(&arena);\n\n\treturn 0;\n}\n\nSEC(\"syscall\") __weak\nint arena_alloc_reserve(void)\n{\n\treturn bpf_arena_reserve_pages(&arena, NULL, RESERVE_ALLOC);\n}\n\n__weak\nint arena_fls(__u64 word)\n{\n\tunsigned int num = 0;\n\n\tif (word & 0xffffffff00000000ULL) {\n\t\tnum += 32;\n\t\tword >>= 32;\n\t}\n\n\tif (word & 0xffff0000) {\n\t\tnum += 16;\n\t\tword >>= 16;\n\t}\n\n\tif (word & 0xff00) {\n\t\tnum += 8;\n\t\tword >>= 8;\n\t}\n\n\tif (word & 0xf0) {\n\t\tnum += 4;\n\t\tword >>= 4;\n\t}\n\n\tif (word & 0xc) {\n\t\tnum += 2;\n\t\tword >>= 2;\n\t}\n\n\tif (word & 0x2) {\n\t\tnum += 1;\n\t}\n\n\treturn num;\n}\n\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc/asan.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000007064\x0015172171634\x000012212\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\nstruct asan_init_args {\n\tu64 arena_all_pages;\n\tu64 arena_globals_pages;\n};\n\nint asan_init(struct asan_init_args *args);\n\n#ifdef __BPF__\n\n#define ASAN_SHADOW_SHIFT 3\n#define ASAN_SHADOW_SCALE (1ULL << ASAN_SHADOW_SHIFT)\n#define ASAN_GRANULE_MASK ((1ULL << ASAN_SHADOW_SHIFT) - 1)\n#define ASAN_GRANULE(addr) ((s8)((u32)(u64)((addr)) & ASAN_GRANULE_MASK))\n\n/* XXX Find the page size from the running kernel. */\n#define PAGE_SHIFT (12)\n\n#define __noasan __attribute__((no_sanitize(\"address\"))) \n\n\n#ifdef BPF_ARENA_ASAN\n\nextern u64 __asan_shadow_memory_dynamic_address;\n\n/* Defined as char * to get 1-byte granularity for pointer arithmetic. */\ntypedef s8 __arena s8a;\n\nstatic inline \ns8a *mem_to_shadow(void __arena __arg_arena *addr)\n{\n\treturn (s8a *)(((u32)(u64)addr >> ASAN_SHADOW_SHIFT) + __asan_shadow_memory_dynamic_address);\n}\n\nstatic inline __noasan\ns8 asan_shadow_value(void __arena __arg_arena *addr) \n{\n\treturn *(s8a *)mem_to_shadow(addr);\n}\n\nint asan_poison(void __arena *addr, s8 val, size_t size);\nint asan_unpoison(void __arena *addr, size_t size);\nbool asan_shadow_set(void __arena *addr);\ns8 asan_shadow_value(void __arena *addr);\n\n/*\n * Dummy calls to ensure the ASAN runtime\'s BTF information is present\n * in every object file when compiling the runtime and local BPF code\n * separately. The runtime calls are injected into the LLVM IR file \n */\n#define DECLARE_ASAN_LOAD_STORE_SIZE(size)\t\t\t\t\\\n\tvoid __asan_store##size(void *addr);\t\t\t\t\\\n\tvoid __asan_store##size##_noabort(void *addr);\t\\\n\tvoid __asan_load##size(void *addr);\t\t\t\t\\\n\tvoid __asan_load##size##_noabort(void *addr);\t\\\n\tvoid __asan_report_store##size(void *addr);\t\t\t\\\n\tvoid __asan_report_store##size##_noabort(void *addr);\t\t\\\n\tvoid __asan_report_load##size(void *addr);\t\t\t\\\n\tvoid __asan_report_load##size##_noabort(void *addr);\t\t\n\nDECLARE_ASAN_LOAD_STORE_SIZE(1);\nDECLARE_ASAN_LOAD_STORE_SIZE(2);\nDECLARE_ASAN_LOAD_STORE_SIZE(4);\nDECLARE_ASAN_LOAD_STORE_SIZE(8);\n\n#define DECLARE_ASAN_LOAD_STORE(size)\t\t\t\t\\\n\tvoid __asan_store##size(void *addr);\t\t\t\\\n\tvoid __asan_store##size##_noabort(void *addr);\t\t\\\n\tvoid __asan_load##size(void *addr);\t\t\t\\\n\tvoid __asan_load##size##_noabort(void *addr);\t\t\\\n\tvoid __asan_report_store##size(void *addr);\t\t\\\n\tvoid __asan_report_store##size##_noabort(void *addr);\t\\\n\tvoid __asan_report_load##size(void *addr);\t\t\\\n\tvoid __asan_report_load##size##_noabort(void *addr);\t\t\n\n#define ASAN_DUMMY_CALLS_SIZE(size, arg)\t\t\\\ndo {\t\t\t\t\t\t\t\\\n\t__asan_store##size((arg));\t\t\t\\\n\t__asan_store##size##_noabort((arg));\t\t\\\n\t__asan_load##size((arg));\t\t\t\\\n\t__asan_load##size##_noabort((arg));\t\t\\\n\t__asan_report_store##size((arg));\t\t\\\n\t__asan_report_store##size##_noabort((arg));\t\\\n\t__asan_report_load##size((arg));\t\t\\\n\t__asan_report_load##size##_noabort((arg));\t\\\n} while (0)\t\n\n#define ASAN_DUMMY_CALLS_ALL(arg)\t\\\ndo { \t\t\t\t\t\\\n\tASAN_DUMMY_CALLS_SIZE(1, (arg));\t\\\n\tASAN_DUMMY_CALLS_SIZE(2, (arg));\t\\\n\tASAN_DUMMY_CALLS_SIZE(4, (arg));\t\\\n\tASAN_DUMMY_CALLS_SIZE(8, (arg));\t\\\n} while (0)\n\n__weak __attribute__((no_sanitize_address))\nint asan_dummy_call() {\n\t/* Use the shadow map base to prevent it from being optimized out. */\n\tif (__asan_shadow_memory_dynamic_address) \n\t\tASAN_DUMMY_CALLS_ALL(NULL);\n\n\treturn 0;\n}\n\n#else /* BPF_ARENA_ASAN */\n\nstatic inline int asan_poison(void __arena *addr, s8 val, size_t size) { return 0; }\nstatic inline int asan_unpoison(void __arena *addr, size_t size) { return 0; }\nstatic inline bool asan_shadow_set(void __arena *addr) { return 0; }\nstatic inline s8 asan_shadow_value(void __arena *addr) { return 0; }\nstatic inline int asan_dummy_call() { return 0; }\n\n#endif /* BPF_ARENA_ASAN */\n\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/alloc/bpf_helpers_local.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000001631\x0015172171634\x000014725\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */\n#ifndef __BPF_HELPERS_LOCAL__\n#define __BPF_HELPERS_LOCAL__\n\n/*\n * This header provides additional BPF helpers not in the standard bpf_helpers.h.\n * It assumes the standard <bpf/bpf_helpers.h> has already been included.\n */\n\nextern int bpf_stream_vprintk_impl(int stream_id, const char *fmt__str, const void *args,\n\t\t\t\t __u32 len__sz, void *aux__prog) __weak __ksym;\n\n#define bpf_stream_printk(stream_id, fmt, args...)\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\t\t\\\n\tstatic const char ___fmt[] = fmt;\t\t\t\t\t\t\\\n\tunsigned long long ___param[___bpf_narg(args)];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t_Pragma(\"GCC diagnostic push\")\t\t\t\t\t\t\t\\\n\t_Pragma(\"GCC diagnostic ignored \\\"-Wint-conversion\\\"\")\t\t\t\t\\\n\t___bpf_fill(___param, args);\t\t\t\t\t\t\t\\\n\t_Pragma(\"GCC diagnostic pop\")\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\tbpf_stream_vprintk_impl(stream_id, ___fmt, ___param, sizeof(___param), NULL);\t\\\n})\n\n#endif /* __BPF_HELPERS_LOCAL__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/arena_map.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000000671\x0015172171634\x000012116\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\nstruct {\n\t__uint(type, BPF_MAP_TYPE_ARENA);\n\t__uint(map_flags, BPF_F_MMAPABLE);\n#if defined(__TARGET_ARCH_arm64) || defined(__aarch64__)\n\t__uint(max_entries, 1 << 16); /* number of pages */\n __ulong(map_extra, (1ull << 32)); /* start of mmap() region */\n#else\n\t__uint(max_entries, 1 << 20); /* number of pages */\n __ulong(map_extra, (1ull << 44)); /* start of mmap() region */\n#endif\n} arena __weak SEC(\".maps\");\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/cleanup.bpf.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000010652\x0015172171634\x000012370\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* Copyright (c) Meta Platforms, Inc. and affiliates. */\n/*\n * This software may be used and distributed according to the terms of the\n * GNU General Public License version 2.\n *\n * RAII guard framework \xe2\x80\x94 subset of the kernel\'s cleanup.h for BPF.\n *\n * Naming and structure follow the kernel\'s include/linux/cleanup.h.\n */\n\n#pragma once\n\n/* DEFINE_FREE \xe2\x80\x94 scoped cleanup for owned resources (refcounts, allocations) */\n#define DEFINE_FREE(_name, _type, _free) \\\n\tstatic inline void __free_##_name(void *p) \\\n\t{ \\\n\t\t_type _T = *(_type *)p; \\\n\t\t_free; \\\n\t}\n\n#define __free(_name) __attribute__((__cleanup__(__free_##_name)))\n\n/*\n * Wrapper that enforces __must_check semantics so callers cannot\n * accidentally discard the returned pointer and leak the resource.\n */\nstatic inline __attribute__((__warn_unused_result__)) const volatile void *\n__must_check_fn(const volatile void *val)\n{\n\treturn val;\n}\n\n/* Like a non-atomic xchg(var, NULL), returns the old value. */\n#define __get_and_null(p) \\\n\t({ \\\n\t\ttypeof(p) *__ptr = &(p); \\\n\t\ttypeof(p) __val = *__ptr; \\\n\t\t*__ptr\t\t = NULL; \\\n\t\t__val; \\\n\t})\n\n/*\n * Transfer ownership out, preventing cleanup.\n *\n * Sets the variable to NULL (so the cleanup is a no-op, assuming\n * the DEFINE_FREE expression includes a NULL check) and returns the\n * original value.\n */\n#define no_free_ptr(p) \\\n\t((typeof(p))__must_check_fn((const volatile void *)__get_and_null(p)))\n\n#define return_ptr(p) return no_free_ptr(p)\n\n/*\n * DEFINE_GUARD \xe2\x80\x94 scoped cleanup for lock-like resources.\n * Built on DEFINE_CLASS, matching the kernel\'s naming convention.\n *\n * _type is the lock pointer type, _lock/_unlock use _T as the pointer.\n */\n#define DEFINE_CLASS(_name, _type, _exit, _init, _init_args...) \\\n\ttypedef _type\t class_##_name##_t; \\\n\tstatic inline void class_##_name##_destructor(_type *p) \\\n\t{ \\\n\t\t_type _T = *p; \\\n\t\t_exit; \\\n\t} \\\n\tstatic inline _type class_##_name##_constructor(_init_args) \\\n\t{ \\\n\t\t_type t = _init; \\\n\t\treturn t; \\\n\t}\n\n#define CLASS(_name, var) \\\n\tclass_##_name##_t var \\\n\t\t__attribute__((__cleanup__(class_##_name##_destructor))) = \\\n\t\t\tclass_##_name##_constructor\n\n#define DEFINE_GUARD(_name, _type, _lock, _unlock) \\\n\tDEFINE_CLASS( \\\n\t\t_name, _type, if (_T) { _unlock; }, ({ \\\n\t\t\t_lock; \\\n\t\t\t_T; \\\n\t\t}), \\\n\t\t_type _T)\n\n#define guard(_name) CLASS(_name, ___bpf_apply(__guard_, __COUNTER__))\n\n#define __scoped_guard(_name, _label, args...) \\\n\tfor (CLASS(_name, scope)(args); true; ({ goto _label; })) \\\n\t\tif (0) { \\\n_label: \\\n\t\t\tbreak; \\\n\t\t} else\n\n#define scoped_guard(_name, args...) \\\n\t__scoped_guard(_name, ___bpf_apply(__label_, __COUNTER__), args)\n\n/*\n * Resource type definitions\n */\n\n/* Cgroup reference */\nDEFINE_FREE(cgroup, struct cgroup *, if (_T) bpf_cgroup_release(_T))\n\n/* BPF cpumask */\nDEFINE_FREE(bpf_cpumask, struct bpf_cpumask *, if (_T) bpf_cpumask_release(_T))\n\n/* Idle cpumask from scx_bpf_get_idle_smtmask */\nDEFINE_FREE(idle_cpumask, const struct cpumask *,\n\t if (_T) scx_bpf_put_idle_cpumask(_T))\n\n/*\n * RCU read lock \xe2\x80\x94 vmlinux.h already exports class_rcu_t from the\n * kernel\'s own guard. Reuse that type and just define the\n * constructor/destructor.\n */\nstatic inline void class_rcu_destructor(class_rcu_t *_T)\n{\n\tif (_T->lock)\n\t\tbpf_rcu_read_unlock();\n}\n\nstatic inline class_rcu_t class_rcu_constructor(void)\n{\n\tclass_rcu_t _t = { .lock = (void *)1 };\n\tbpf_rcu_read_lock();\n\treturn _t;\n}\n\n/* BPF spin lock */\nDEFINE_GUARD(spin_lock, struct bpf_spin_lock *, bpf_spin_lock(_T),\n\t bpf_spin_unlock(_T))\n\n/* Task reference from bpf_task_from_pid / bpf_task_acquire */\nDEFINE_FREE(task, struct task_struct *, if (_T) bpf_task_release(_T))\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/pagefrag_alloc.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000002753\x0015172171634\x000013124\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n/* Copyright (c) 2024-2025 Meta Platforms, Inc. and affiliates. */\n#pragma once\n#include <scx/bpf_arena_common.bpf.h>\n#include <lib/arena_map.h>\n\n#ifndef __round_mask\n#define __round_mask(x, y) ((__typeof__(x))((y)-1))\n#endif\n#ifndef round_up\n#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)\n#endif\n\nstatic void __arena * __arena page_frag_cur_page[NR_CPUS];\nstatic int __arena page_frag_cur_offset[NR_CPUS];\n\n/* Simple page_frag allocator */\nstatic inline void __arena* pagefrag_alloc(unsigned int size)\n{\n\t__u64 __arena *obj_cnt;\n\t__u32 cpu = bpf_get_smp_processor_id();\n\tvoid __arena *page = page_frag_cur_page[cpu];\n\tint __arena *cur_offset = &page_frag_cur_offset[cpu];\n\tint offset;\n\n\tsize = round_up(size, 8);\n\tif (size >= PAGE_SIZE - 8)\n\t\treturn NULL;\n\tif (!page) {\nrefill:\n\t\tpage = bpf_arena_alloc_pages(&arena, NULL, 1, NUMA_NO_NODE, 0);\n\t\tif (!page)\n\t\t\treturn NULL;\n\t\tcast_kern(page);\n\t\tpage_frag_cur_page[cpu] = page;\n\t\t*cur_offset = PAGE_SIZE - 8;\n\t\tobj_cnt = page + PAGE_SIZE - 8;\n\t\t*obj_cnt = 0;\n\t} else {\n\t\tcast_kern(page);\n\t\tobj_cnt = page + PAGE_SIZE - 8;\n\t}\n\n\toffset = *cur_offset - size;\n\tif (offset < 0)\n\t\tgoto refill;\n\n\t(*obj_cnt)++;\n\t*cur_offset = offset;\n\treturn page + offset;\n}\n\nstatic inline void pagefrag_free(void __arena *addr)\n{\n\t__u64 __arena *obj_cnt;\n\n\taddr = (void __arena *)(((long)addr) & ~(PAGE_SIZE - 1));\n\tobj_cnt = addr + PAGE_SIZE - 8;\n\tif (--(*obj_cnt) == 0)\n\t\tbpf_arena_free_pages(&arena, addr, 1);\n}\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/cgroup.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000017301\x0015172171634\x000011470\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/*\n * SPDX-License-Identifier: GPL-2.0\n * Copyright (c) 2025 Meta Platforms, Inc. and affiliates.\n * Author: Changwoo Min <changwoo@igalia.com>\n */\n#pragma once\n\n#include <errno.h>\n\n/**\n * Configs for cpu.max\n */\nstruct scx_cgroup_bw_config {\n\t/* verbose level */\n\tint\t\tverbose;\n};\n\n/**\n * scx_cgroup_bw_lib_init - Initialize the library with a configuration.\n * @config: tunnables, see the struct definition.\n *\n * It should be called for the library initialization before calling any\n * other API.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_lib_init(struct scx_cgroup_bw_config *config);\n\n/**\n * scx_cgroup_bw_init - Initialize a cgroup for CPU bandwidth control.\n * @cgrp: cgroup being initialized.\n * @args: init arguments, see the struct definition.\n *\n * Either the BPF scheduler is being loaded or @cgrp created, initialize\n * @cgrp for CPU bandwidth control. When being loaded, cgroups are initialized\n * in a pre-order from the root. This operation may block.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_init(struct cgroup *cgrp __arg_trusted, struct scx_cgroup_init_args *args __arg_trusted);\n\n/**\n * scx_cgroup_bw_exit - Exit a cgroup.\n * @cgrp: cgroup being exited\n *\n * Either the BPF scheduler is being unloaded or @cgrp destroyed, exit\n * @cgrp for sched_ext. This operation my block.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_exit(struct cgroup *cgrp __arg_trusted);\n\n/**\n * scx_cgroup_bw_set - A cgroup\'s bandwidth is being changed.\n * @cgrp: cgroup whose bandwidth is being updated\n * @period_us: bandwidth control period\n * @quota_us: bandwidth control quota\n * @burst_us: bandwidth control burst\n *\n * Update @cgrp\'s bandwidth control parameters. This is from the cpu.max\n * cgroup interface.\n *\n * @quota_us / @period_us determines the CPU bandwidth @cgrp is entitled\n * to. For example, if @period_us is 1_000_000 and @quota_us is\n * 2_500_000. @cgrp is entitled to 2.5 CPUs. @burst_us can be\n * interpreted in the same fashion and specifies how much @cgrp can\n * burst temporarily. The specific control mechanism and thus the\n * interpretation of @period_us and burstiness is upto to the BPF\n * scheduler.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_set(struct cgroup *cgrp __arg_trusted, u64 period_us, u64 quota_us, u64 burst_us);\n\n/**\n * scx_cgroup_bw_throttled - Check if the cgroup is throttled or not.\n * @cgrp: cgroup where a task belongs to.\n * @p: a task to be tested.\n *\n * Return 0 when the cgroup is not throttled,\n * -EAGAIN when the cgroup is throttled, and\n * -errno for some other failures.\n */\nint scx_cgroup_bw_throttled(struct cgroup *cgrp __arg_trusted, struct task_struct *p __arg_trusted);\n\n/**\n * scx_cgroup_bw_consume - Consume the time actually used after the task execution.\n * @cgrp: cgroup where a task belongs to.\n * @consumed_ns: amount of time actually used.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_consume(struct cgroup *cgrp __arg_trusted, u64 consumed_ns);\n\n/**\n * scx_cgroup_bw_put_aside - Put aside a task to execute it when the cgroup is\n * unthrottled later.\n * @p: a task to be put aside since the cgroup is throttled.\n * @taskc: a task-embedded pointer to scx_task_common.\n * @vtime: vtime of a task @p.\n * @cgrp: cgroup where a task belongs to.\n *\n * When a cgroup is throttled (i.e., scx_cgroup_bw_reserve() returns -EAGAIN),\n * a task that is in the ops.enqueue() path should be put aside to the BTQ of\n * its associated LLC context. When the cgroup becomes unthrottled again,\n * the registered enqueue_cb() will be called to re-enqueue the task for\n * execution.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_put_aside(struct task_struct *p __arg_trusted, u64 taskc, u64 vtime, struct cgroup *cgrp __arg_trusted);\n\n/**\n * scx_cgroup_bw_reenqueue - Reenqueue backlogged tasks.\n *\n * When a cgroup is throttled, a task should be put aside at the ops.enqueue()\n * path. Once the cgroup becomes unthrottled again, such backlogged tasks\n * should be requeued for execution. To this end, a BPF scheduler should call\n * this at the beginning of its ops.dispatch() method, so that backlogged tasks\n * can be reenqueued if necessary.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_reenqueue(void);\n\n/**\n * scx_cgroup_bw_cancel - Cancel throttling for a task.\n *\n * @taskc: Pointer to the scx_task_common task context. Passed as a u64\n * to avoid exposing the scx_task_common type to the scheduler.\n *\n * Tasks may be dequeued from the BPF side by the scx core during system\n * calls like sched_setaffinity(2). In that case, we must cancel any\n * throttling-related ATQ insert operations for the task:\n * - We must avoid double inserts caused by the dequeued task being\n * reenqueed and throttled again while still in an ATQ.\n * - We want to remove tasks not in scx anymore from throttling. While\n * inserting non-scx tasks into a DSQ is a no-op, we would like our\n * accounting to be as accurate as possible.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_cancel(u64 taskc);\n\n/**\n * REGISTER_SCX_CGROUP_BW_ENQUEUE_CB - Register an enqueue callback.\n * @eqcb: A function name with a prototype of\n * \'int fn(struct task_struct * __arg_trusted, u64)\'.\n *\n * @eqcb enqueues task @p following the BPF scheduler\'s regular enqueue\n * path. @eqcb will be called when a throttled cgroup becomes available\n * again or when the cgroup is exiting for some reason.\n * @eqcb MUST enqueue the task; otherwise, the task will be lost and\n * never be scheduled.\n */\n#define REGISTER_SCX_CGROUP_BW_ENQUEUE_CB(eqcb)\t\t\t\t\t\\\n\t__hidden int scx_cgroup_bw_enqueue_cb(u64 ctx)\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\\\n\t\textern int eqcb(struct task_struct * __arg_trusted, u64);\t\\\n\t\ttask_ctx *taskc = (task_ctx *)ctx;\t\t\t\t\\\n\t\tstruct task_struct *p = bpf_task_from_pid(taskc->pid);\t\t\\\n\t\tif (p) {\t\t\t\t\t\t\t\\\n\t\t\teqcb(p, (u64)taskc);\t\t\t\t\t\\\n\t\t\tbpf_task_release(p);\t\t\t\t\t\\\n\t\t} else {\t\t\t\t\t\t\t\\\n\t\t\tscx_bpf_error(\"BUG: bpf_task_from_pid() failed for \"\t\\\n\t\t\t\t \"pid %d -- exiting task was \"\t\t\\\n\t\t\t\t \"unexpectedly throttled\", taskc->pid);\t\\\n\t\t}\t\t\t\t\t\t\t\t\\\n\t\treturn 0;\t\t\t\t\t\t\t\\\n\t}\n\n/**\n * scx_cgroup_bw_is_cgroup_throttled - Test if a cgroup is throttled or not.\n *\n * @cgrp_id: cgroup id\n *\n * Return true if the cgroup is throttled. Otherwise, return false.\n */\nint scx_cgroup_bw_is_cgroup_throttled(u64 cgrp_id);\n\n/**\n * scx_cgroup_bw_is_task_throttled - Test if a task is throttled or not.\n *\n * @taskc: Pointer to the scx_task_common task context. Passed as a u64\n * to avoid exposing the scx_task_common type to the scheduler.\n *\n * Return true if the task is throttled. Otherwise, return false.\n */\nint scx_cgroup_bw_is_task_throttled(u64 taskc);\n\n/**\n * scx_cgroup_bw_move - Move a task from a cgroup to another (@from -> @to).\n *\n * @p: task being moved\n * @taskc: Pointer to the scx_task_common task context. Passed as a u64\n * to avoid exposing the scx_task_common type to the scheduler.\n * @from: cgroup @p is being moved from\n * @to: cgroup @p is being moved to\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_move(struct task_struct *p __arg_trusted, u64 taskc,\n\t\t struct cgroup *from __arg_trusted,\n\t\t struct cgroup *to __arg_trusted);\n\n/**\n * scx_cgroup_bw_dump - Dump the cgroup status\n *\n * @cgrp_id: cgroup id\n * @descendent: If true, dump the cgroup and its descendent in preorder.\n * Otherwise, dump only itself.\n * @accurate: If true, update runtime total before dumping the status to\n * get more accurate information. Otherwise, dump the currently collected\n * snapshot of runtime values.\n * @indent: If true, indent the output. Otherwise, do not indent the output.\n *\n * Return 0 for success, -errno for failure.\n */\nint scx_cgroup_bw_dump(u64 cgrp_id, bool descendent, bool accurate, bool indent);\n\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/sdt_task_defs.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000005162\x0015172171634\x000013010\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/*\n * SPDX-License-Identifier: GPL-2.0\n * Copyright (c) 2025 Meta Platforms, Inc. and affiliates.\n * Copyright (c) 2025 Tejun Heo <tj@kernel.org>\n * Copyright (c) 2025 Emil Tsalapatis <etsal@meta.com>\n */\n#pragma once\n\n#ifndef div_round_up\n#define div_round_up(a, b) (((a) + (b) - 1) / (b))\n#endif\n\n#ifndef round_up\n#define round_up(a, b) (div_round_up((a), (b)) * (b))\n#endif\n\ntypedef struct sdt_desc __arena sdt_desc_t;\n\nenum sdt_consts {\n\tSDT_TASK_ENTS_PER_PAGE_SHIFT\t= 9,\n\tSDT_TASK_LEVELS\t\t\t= 3,\n\tSDT_TASK_ENTS_PER_CHUNK\t\t= 1 << SDT_TASK_ENTS_PER_PAGE_SHIFT,\n\tSDT_TASK_CHUNK_BITMAP_U64S\t= div_round_up(SDT_TASK_ENTS_PER_CHUNK, 64),\n\tSDT_TASK_ALLOC_STACK_MIN\t= 2 * SDT_TASK_LEVELS,\n\tSDT_TASK_ALLOC_STACK_MAX\t= SDT_TASK_ALLOC_STACK_MIN * 5,\n\tSDT_TASK_MIN_ELEM_PER_ALLOC \t= 8,\n\tSDT_TASK_ALLOC_ATTEMPTS\t\t= 32,\n};\n\nunion sdt_id {\n\t__s64\t\t\t\tval;\n\tstruct {\n\t\t__s32\t\t\tidx;\t/* index in the radix tree */\n\t\t__s32\t\t\tgenn;\t/* ++\'d on recycle so that it forms unique\'ish 64bit ID */\n\t};\n};\n\nstruct sdt_chunk;\n\n/*\n * Each index page is described by the following descriptor which carries the\n * bitmap. This way the actual index can host power-of-two numbers of entries\n * which makes indexing cheaper.\n */\nstruct sdt_desc {\n\t__u64\t\t\t\tallocated[SDT_TASK_CHUNK_BITMAP_U64S];\n\t__u64\t\t\t\tnr_free;\n\tstruct sdt_chunk __arena\t*chunk;\n};\n\n/*\n * Leaf node containing per-task data.\n */\nstruct sdt_data {\n\tunion sdt_id\t\t\ttid;\n\t__u64\t\t\t\tpayload[];\n};\n\n/*\n * Intermediate node pointing to another intermediate node or leaf node.\n */\nstruct sdt_chunk {\n\tunion {\n\t\tsdt_desc_t * descs[SDT_TASK_ENTS_PER_CHUNK];\n\t\tstruct sdt_data __arena *data[SDT_TASK_ENTS_PER_CHUNK];\n\t};\n};\n\n/*\n * Stack structure to avoid chunk allocations/frees while under lock. The\n * allocator preallocates enough arena pages before any operation to satisfy\n * the maximum amount of chunk allocations:(2 * SDT_TASK_LEVELS + 1), two\n * allocations per tree level, and one for the data itself. Preallocating\n * ensures that the stack can satisfy these allocations, so we do not need\n * to drop the lock to allocate pages from the arena in the middle of the\n * top-level alloc. This in turn prevents races and simplifies the code.\n */\nstruct scx_alloc_stack {\n\t__u64 idx;\n\tvoid __arena\t*stack[SDT_TASK_ALLOC_STACK_MAX];\n};\n\nstruct sdt_pool {\n\tvoid __arena\t*slab;\n\t__u64\t\telem_size;\n\t__u64\t\tmax_elems;\n\t__u64\t\tidx;\n};\n\nstruct scx_alloc_stats {\n\t__u64\t\tchunk_allocs;\n\t__u64\t\tdata_allocs;\n\t__u64\t\talloc_ops;\n\t__u64\t\tfree_ops;\n\t__u64\t\tactive_allocs;\n\t__u64\t\tarena_pages_used;\n};\n\nstruct scx_allocator {\n\tstruct sdt_pool\tpool;\n\tsdt_desc_t\t*root;\n};\n\nstruct scx_static {\n\tsize_t max_alloc_bytes;\n\tvoid __arena *memory;\n\tsize_t off;\n};\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/lvqueue.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000001117\x0015172171634\x000011655\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\nstruct lv_arr;\n\n#define LV_ARR_BASESZ 128\n#define LV_ARR_ORDERS 10\n\nstruct lv_arr {\n\tu64 __arena *data;\n\tu64 order;\n};\n\ntypedef volatile struct lv_arr __arena lv_arr_t;\n\nstruct lv_queue {\n\tlv_arr_t *cur;\n\tvolatile u64 top;\n\tvolatile u64 bottom;\n\tstruct lv_arr arr[LV_ARR_ORDERS];\n};\n\ntypedef struct lv_queue __arena lv_queue_t;\n\nint lvq_push(lv_queue_t *lvq, u64 val);\nint lvq_pop(lv_queue_t *lvq, u64 *val);\nint lvq_steal(lv_queue_t *lvq, u64 *val);\n\nu64 lvq_create_internal(void);\n#define lvq_create() ((lv_queue_t *)lvq_create_internal())\n\nint lvq_destroy(lv_queue_t *lvq);\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/topology.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000005475\x0015172171634\x000012056\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#include <lib/cpumask.h>\n\nstruct topology;\ntypedef struct topology __arena * topo_ptr;\n\nenum topo_level {\n\tTOPO_TOP\t= 0,\n\tTOPO_NODE\t= 1,\n\tTOPO_LLC\t= 2,\n\tTOPO_CORE\t= 3,\n\tTOPO_CPU\t= 4,\n\tTOPO_MAX_LEVEL\t= 5,\n};\n\nstruct topology {\n\ttopo_ptr parent;\n\tsize_t nr_children;\n\tscx_bitmap_t mask;\n\tenum topo_level level;\n\tu64 id;\n\n\t/* Generic pointer, can be used for anything. */\n\tvoid __arena *data;\n\n\t/*\n\t * Variable-length children array. Allocated as part of the struct via\n\t * scx_static_alloc(sizeof(struct topology) + max_children * sizeof(topo_ptr)).\n\t * The per-level capacity is stored in topo_max_children[].\n\t */\n\ttopo_ptr children[];\n};\n\nextern volatile topo_ptr topo_all;\n\n/*\n * Per-level maximum number of children. Must be set via arena_topology_init()\n * before any topo_init() calls. Each node at level L is allocated with\n * topo_max_children[L] child pointer slots.\n */\nextern u32 topo_max_children[TOPO_MAX_LEVEL];\n\nint topo_init(scx_bitmap_t __arg_arena mask, u64 data_size, u64 id);\nint topo_contains(topo_ptr topo, u32 cpu);\nint topo_cpu_to_llc_id(u32 cpu);\n\nu64 topo_mask_level_internal(topo_ptr topo, enum topo_level level);\n#define topo_mask_level(topo, level) ((scx_bitmap_t) topo_mask_level_internal((topo), (level)))\n\nint topo_print(void);\nint topo_print_by_level(void);\n\nstruct topo_iter {\n\t/* The current topology node. */\n\ttopo_ptr topo;\n\t/*\n\t * The index for every node in the path of the tree for , -1 denotes levels > the current one.\n\t * E.g., [0, 1, 2, 1, 2] means:\n\t * - index on level 0 (we only have one top-level node]\n\t * - index 1 on level 1 (the top-level node\'s second child)\n\t * - index 2 on level 2 (the NUMA node topology node\'s third child)\n\t * and so on.\n\t */\n\tint indices[TOPO_MAX_LEVEL];\n};\n\n/* Below is the machinery required for traversing the topology. It\'s better not to use it directly. */\n__weak u64 topo_iter_level_internal(struct topo_iter *iter, enum topo_level lvl);\nstatic inline int topo_iter_start(struct topo_iter *iter)\n{\n\tint ind;\n\n\tif (!topo_all)\n\t\treturn -EINVAL;\n\n\titer->topo = topo_all;\n\tbpf_for(ind, 0, TOPO_MAX_LEVEL)\n\t\titer->indices[ind] = -1;\n\n\treturn 0;\n}\n\n#define TOPO_FOR_EACH_LEVEL(_iter, _topo, _lvl)\t\t\\\n\ttopo_iter_start((_iter));\t\t\t\\\n\twhile (((_topo) = ((topo_ptr)topo_iter_level_internal((_iter), _lvl))) && can_loop)\n\n/* User-friendly macros that are good for usage within schedulers. */\n#define TOPO_FOR_EACH_NODE(_iter, _topo) TOPO_FOR_EACH_LEVEL((_iter), (_topo), TOPO_NODE)\n#define TOPO_FOR_EACH_LLC(_iter, _topo) TOPO_FOR_EACH_LEVEL((_iter), (_topo), TOPO_LLC)\n#define TOPO_FOR_EACH_CORE(_iter, _topo) TOPO_FOR_EACH_LEVEL((_iter), (_topo), TOPO_CORE)\n#define TOPO_FOR_EACH_CPU(_iter, _topo) TOPO_FOR_EACH_LEVEL((_iter), (_topo), TOPO_CPU)\n\nextern u64 topo_nodes[TOPO_MAX_LEVEL][NR_CPUS];\nextern int nr_topo_nodes[TOPO_MAX_LEVEL];\n\n#define TOPO_NR(type) nr_topo_nodes[TOPO_##type - 1]\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/minheap.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000001303\x0015172171634\x000011605\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\nstruct scx_minheap_elem {\n\tu64 elem;\n\tu64 weight;\n};\n\nstruct scx_minheap {\n\tu64\t\t\t\tsize;\n\tu64\t\t\t\tcapacity;\n\tstruct scx_minheap_elem\t\t__arena *helems;\n};\n\ntypedef struct scx_minheap __arena scx_minheap_t;\n\n#ifdef __BPF__\n\nu64 scx_minheap_alloc_internal(size_t capacity);\n#define scx_minheap_alloc(capacity) (scx_minheap_t *)scx_minheap_alloc_internal(capacity)\n\nint scx_minheap_balance_top_down(void __arena *heap_ptr __arg_arena);\nint scx_minheap_insert(void __arena *heap_ptr __arg_arena, u64 elem, u64 weight);\nint scx_minheap_dump(scx_minheap_t *heap __arg_arena);\nint scx_minheap_pop(void __arena *heap_ptr __arg_arena, struct scx_minheap_elem *helem __arg_trusted);\n\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/arena.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000001612\x0015172171634\x000011255\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#include <lib/topology.h>\n\n#define NR_CPU_IDS_UNINIT (~(u32)0)\n\n/* For userspace programs, __arena is a no-op. */\n#if !defined(__arena) && !defined(__BPF__)\n#define __arena\n#endif\n\nstruct arena_init_args {\n\tu64 static_pages;\n\tu64 task_ctx_size;\n};\n\nint arena_init(struct arena_init_args *args);\n\nstruct arena_alloc_mask_args {\n\tu64 bitmap;\n};\n\nint arena_alloc_mask(struct arena_alloc_mask_args *args);\n\nstruct arena_topology_node_init_args {\n\tu64 bitmap;\n\tu64 data_size;\n\tu64 id;\n};\n\nint arena_topology_node_init(struct arena_topology_node_init_args *args);\n\n/*\n * Must be called once before any arena_topology_node_init() calls to set the\n * per-level maximum number of children. The array is indexed by topo_level.\n */\nstruct arena_topology_init_args {\n\tu32 max_children[TOPO_MAX_LEVEL];\n};\n\nint arena_topology_init(struct arena_topology_init_args *args);\n\nint arena_topology_print(void);\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00lib/atq.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000003606\x0015172171634\x000010761\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma once\n\n#ifdef __BPF__\n#include <scx/common.bpf.h>\n#include <bpf_arena_common.bpf.h>\n\n#else /* __BPF__ */\n#define atomic_t u64\n#endif /* __BPF__ */\n\n#include <bpf_arena_spin_lock.h>\n#include <lib/rbtree.h>\n\nenum scx_atq_consts {\n\tSCX_ATQ_INF_CAPACITY = ((u64)-1),\n\tSCX_ATQ_FIFO = ((u64)-1)\n};\n\nenum scx_task_throttle {\n\tSCX_TSK_CANRUN = 0,\n\tSCX_TSK_THROTTLED\n};\n\nstruct scx_atq {\n\tunion sdt_id tid;\n\trbtree_t *tree;\n\tarena_spinlock_t lock;\n\tu64 capacity;\n\tu64 size;\n\tu64 seq;\n\tu64 fifo;\n};\n\n\ntypedef struct scx_atq __arena scx_atq_t;\n\nint scx_atq_init(void);\n\nstruct scx_task_common {\n\tstruct rbnode node;\t/* rbnode for being inserted into ATQs */\n\tscx_atq_t *atq;\n\tenum scx_task_throttle state;\n};\n\ntypedef struct scx_task_common __arena scx_task_common;\n\n#ifdef __BPF__\nu64 scx_atq_create_internal(bool fifo, size_t capacity);\n#define scx_atq_create(fifo) scx_atq_create_internal((fifo), SCX_ATQ_INF_CAPACITY)\n#define scx_atq_create_size(fifo, capacity) scx_atq_create_internal((fifo), (capacity))\nint scx_atq_destroy(scx_atq_t __arg_arena *atq);\nint scx_atq_insert(scx_atq_t *atq, scx_task_common *taskc);\nint scx_atq_insert_vtime(scx_atq_t __arg_arena *atq, scx_task_common *taskc, u64 vtime);\nint scx_atq_remove(scx_atq_t *atq, scx_task_common *taskc);\nint scx_atq_insert_unlocked(scx_atq_t *atq, scx_task_common __arg_arena *taskc);\nint scx_atq_insert_vtime_unlocked(scx_atq_t __arg_arena *atq, scx_task_common __arg_arena *taskc, u64 vtime);\nint scx_atq_remove_unlocked(scx_atq_t *atq, scx_task_common __arg_arena *taskc);\nint scx_atq_nr_queued(scx_atq_t *atq);\nu64 scx_atq_pop(scx_atq_t *atq);\nu64 scx_atq_peek(scx_atq_t *atq);\nint scx_atq_cancel(scx_task_common *taskc);\n\nstatic __always_inline\nint scx_atq_lock(scx_atq_t __arg_arena *atq)\n{\n\treturn arena_spin_lock(&atq->lock);\n}\n\nstatic __always_inline\nvoid scx_atq_unlock(scx_atq_t __arg_arena *atq)\n{\n\tarena_spin_unlock(&atq->lock);\n}\n#endif /* __BPF__ */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00bpf_atomic.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000011760\x0015172171634\x000011531\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00// SPDX-License-Identifier: GPL-2.0\n/* Copyright (c) 2025 Meta Platforms, Inc. and affiliates. */\n#ifndef BPF_ATOMIC_H\n#define BPF_ATOMIC_H\n\n#include <vmlinux.h>\n#include <bpf/bpf_helpers.h>\n#include \"bpf_experimental.h\"\n\nextern bool CONFIG_X86_64 __kconfig __weak;\n\n/*\n * __unqual_typeof(x) - Declare an unqualified scalar type, leaving\n *\t\t\tnon-scalar types unchanged,\n *\n * Prefer C11 _Generic for better compile-times and simpler code. Note: \'char\'\n * is not type-compatible with \'signed char\', and we define a separate case.\n *\n * This is copied verbatim from kernel\'s include/linux/compiler_types.h, but\n * with default expression (for pointers) changed from (x) to (typeof(x)0).\n *\n * This is because LLVM has a bug where for lvalue (x), it does not get rid of\n * an extra address_space qualifier, but does in case of rvalue (typeof(x)0).\n * Hence, for pointers, we need to create an rvalue expression to get the\n * desired type. See https://github.com/llvm/llvm-project/issues/53400.\n */\n#define __scalar_type_to_expr_cases(type) \\\n\tunsigned type : (unsigned type)0, signed type : (signed type)0\n\n#define __unqual_typeof(x) \\\n\ttypeof(_Generic((x), \\\n\t\tchar: (char)0, \\\n\t\t__scalar_type_to_expr_cases(char), \\\n\t\t__scalar_type_to_expr_cases(short), \\\n\t\t__scalar_type_to_expr_cases(int), \\\n\t\t__scalar_type_to_expr_cases(long), \\\n\t\t__scalar_type_to_expr_cases(long long), \\\n\t\tdefault: (typeof(x))0))\n\n/* No-op for BPF */\n#define cpu_relax() ({})\n\n#ifndef READ_ONCE\n#define READ_ONCE(x) (*(volatile typeof(x) *)&(x))\n#endif\n\n#ifndef WRITE_ONCE\n#define WRITE_ONCE(x, val) ((*(volatile typeof(x) *)&(x)) = (val))\n#endif\n\n#define cmpxchg(p, old, new) __sync_val_compare_and_swap((p), old, new)\n\n#define try_cmpxchg(p, pold, new) \\\n\t({ \\\n\t\t__unqual_typeof(*(pold)) __o = *(pold); \\\n\t\t__unqual_typeof(*(p)) __r = cmpxchg(p, __o, new); \\\n\t\tif (__r != __o) \\\n\t\t\t*(pold) = __r; \\\n\t\t__r == __o; \\\n\t})\n\n#define try_cmpxchg_relaxed(p, pold, new) try_cmpxchg(p, pold, new)\n\n#define try_cmpxchg_acquire(p, pold, new) try_cmpxchg(p, pold, new)\n\n#define smp_mb() \\\n\t({ \\\n\t\tvolatile unsigned long __val; \\\n\t\t__sync_fetch_and_add(&__val, 0); \\\n\t})\n\n#define smp_rmb() \\\n\t({ \\\n\t\tif (!CONFIG_X86_64) \\\n\t\t\tsmp_mb(); \\\n\t\telse \\\n\t\t\tbarrier(); \\\n\t})\n\n#define smp_wmb() \\\n\t({ \\\n\t\tif (!CONFIG_X86_64) \\\n\t\t\tsmp_mb(); \\\n\t\telse \\\n\t\t\tbarrier(); \\\n\t})\n\n/* Control dependency provides LOAD->STORE, provide LOAD->LOAD */\n#define smp_acquire__after_ctrl_dep() ({ smp_rmb(); })\n\n#define smp_load_acquire(p) \\\n\t({ \\\n\t\t__unqual_typeof(*(p)) __v = READ_ONCE(*(p)); \\\n\t\tif (!CONFIG_X86_64) \\\n\t\t\tsmp_mb(); \\\n\t\tbarrier(); \\\n\t\t__v; \\\n\t})\n\n#define smp_store_release(p, val) \\\n\t({ \\\n\t\tif (!CONFIG_X86_64) \\\n\t\t\tsmp_mb(); \\\n\t\tbarrier(); \\\n\t\t(void)WRITE_ONCE(*(p), val); \\\n\t})\n\n#define smp_cond_load_relaxed_label(p, cond_expr, label) \\\n\t({ \\\n\t\ttypeof(p) __ptr = (p); \\\n\t\t__unqual_typeof(*(p)) VAL; \\\n\t\tfor (;;) { \\\n\t\t\tVAL = (__unqual_typeof(*(p)))READ_ONCE(*__ptr); \\\n\t\t\tif (cond_expr) \\\n\t\t\t\tbreak; \\\n\t\t\tcond_break_label(label); \\\n\t\t\tcpu_relax(); \\\n\t\t} \\\n\t\t(typeof(*(p)))VAL; \\\n\t})\n\n#define smp_cond_load_acquire_label(p, cond_expr, label) \\\n\t({ \\\n\t\t__unqual_typeof(*p) __val = \\\n\t\t\tsmp_cond_load_relaxed_label(p, cond_expr, label); \\\n\t\tsmp_acquire__after_ctrl_dep(); \\\n\t\t(typeof(*(p)))__val; \\\n\t})\n\n#define atomic_read(p) READ_ONCE((p)->counter)\n\n#define atomic_cond_read_relaxed_label(p, cond_expr, label) \\\n\tsmp_cond_load_relaxed_label(&(p)->counter, cond_expr, label)\n\n#define atomic_cond_read_acquire_label(p, cond_expr, label) \\\n\tsmp_cond_load_acquire_label(&(p)->counter, cond_expr, label)\n\n#define atomic_try_cmpxchg_relaxed(p, pold, new) \\\n\ttry_cmpxchg_relaxed(&(p)->counter, pold, new)\n\n#define atomic_try_cmpxchg_acquire(p, pold, new) \\\n\ttry_cmpxchg_acquire(&(p)->counter, pold, new)\n\n#endif /* BPF_ATOMIC_H */\n\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00bpf_experimental.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100644\x000001751\x000001751\x0000000056213\x0015172171634\x000012754\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#ifndef __BPF_EXPERIMENTAL__\n#define __BPF_EXPERIMENTAL__\n\n#include <vmlinux.h>\n#include <bpf/bpf_tracing.h>\n#include <bpf/bpf_helpers.h>\n#include <bpf/bpf_core_read.h>\n\n#define __contains(name, node) __attribute__((btf_decl_tag(\"contains:\" #name \":\" #node)))\n\n/* Description\n *\tAllocates an object of the type represented by \'local_type_id\' in\n *\tprogram BTF. User may use the bpf_core_type_id_local macro to pass the\n *\ttype ID of a struct in program BTF.\n *\n *\tThe \'local_type_id\' parameter must be a known constant.\n *\tThe \'meta\' parameter is rewritten by the verifier, no need for BPF\n *\tprogram to set it.\n * Returns\n *\tA pointer to an object of the type corresponding to the passed in\n *\t\'local_type_id\', or NULL on failure.\n */\nextern void *bpf_obj_new_impl(__u64 local_type_id, void *meta) __ksym;\n\n/* Convenience macro to wrap over bpf_obj_new_impl */\n#define bpf_obj_new(type) ((type *)bpf_obj_new_impl(bpf_core_type_id_local(type), NULL))\n\n/* Description\n *\tFree an allocated object. All fields of the object that require\n *\tdestruction will be destructed before the storage is freed.\n *\n *\tThe \'meta\' parameter is rewritten by the verifier, no need for BPF\n *\tprogram to set it.\n * Returns\n *\tVoid.\n */\nextern void bpf_obj_drop_impl(void *kptr, void *meta) __ksym;\n\n/* Convenience macro to wrap over bpf_obj_drop_impl */\n#define bpf_obj_drop(kptr) bpf_obj_drop_impl(kptr, NULL)\n\n/* Description\n *\tIncrement the refcount on a refcounted local kptr, turning the\n *\tnon-owning reference input into an owning reference in the process.\n *\n *\tThe \'meta\' parameter is rewritten by the verifier, no need for BPF\n *\tprogram to set it.\n * Returns\n *\tAn owning reference to the object pointed to by \'kptr\'\n */\nextern void *bpf_refcount_acquire_impl(void *kptr, void *meta) __ksym;\n\n/* Convenience macro to wrap over bpf_refcount_acquire_impl */\n#define bpf_refcount_acquire(kptr) bpf_refcount_acquire_impl(kptr, NULL)\n\n/* Description\n *\tAdd a new entry to the beginning of the BPF linked list.\n *\n *\tThe \'meta\' and \'off\' parameters are rewritten by the verifier, no need\n *\tfor BPF programs to set them\n * Returns\n *\t0 if the node was successfully added\n *\t-EINVAL if the node wasn\'t added because it\'s already in a list\n */\nextern int bpf_list_push_front_impl(struct bpf_list_head *head,\n\t\t\t\t struct bpf_list_node *node,\n\t\t\t\t void *meta, __u64 off) __ksym;\n\n/* Convenience macro to wrap over bpf_list_push_front_impl */\n#define bpf_list_push_front(head, node) bpf_list_push_front_impl(head, node, NULL, 0)\n\n/* Description\n *\tAdd a new entry to the end of the BPF linked list.\n *\n *\tThe \'meta\' and \'off\' parameters are rewritten by the verifier, no need\n *\tfor BPF programs to set them\n * Returns\n *\t0 if the node was successfully added\n *\t-EINVAL if the node wasn\'t added because it\'s already in a list\n */\nextern int bpf_list_push_back_impl(struct bpf_list_head *head,\n\t\t\t\t struct bpf_list_node *node,\n\t\t\t\t void *meta, __u64 off) __ksym;\n\n/* Convenience macro to wrap over bpf_list_push_back_impl */\n#define bpf_list_push_back(head, node) bpf_list_push_back_impl(head, node, NULL, 0)\n\n/* Description\n *\tRemove the entry at the beginning of the BPF linked list.\n * Returns\n *\tPointer to bpf_list_node of deleted entry, or NULL if list is empty.\n */\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __ksym;\n\n/* Description\n *\tRemove the entry at the end of the BPF linked list.\n * Returns\n *\tPointer to bpf_list_node of deleted entry, or NULL if list is empty.\n */\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __ksym;\n\n/* Description\n *\tRemove \'node\' from rbtree with root \'root\'\n * Returns\n * \tPointer to the removed node, or NULL if \'root\' didn\'t contain \'node\'\n */\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root,\n\t\t\t\t\t struct bpf_rb_node *node) __ksym;\n\n/* Description\n *\tAdd \'node\' to rbtree with root \'root\' using comparator \'less\'\n *\n *\tThe \'meta\' and \'off\' parameters are rewritten by the verifier, no need\n *\tfor BPF programs to set them\n * Returns\n *\t0 if the node was successfully added\n *\t-EINVAL if the node wasn\'t added because it\'s already in a tree\n */\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node,\n\t\t\t bool (less)(struct bpf_rb_node *a, const struct bpf_rb_node *b),\n\t\t\t void *meta, __u64 off) __ksym;\n\n/* Convenience macro to wrap over bpf_rbtree_add_impl */\n#define bpf_rbtree_add(head, node, less) bpf_rbtree_add_impl(head, node, less, NULL, 0)\n\n/* Description\n *\tReturn the first (leftmost) node in input tree\n * Returns\n *\tPointer to the node, which is _not_ removed from the tree. If the tree\n *\tcontains no nodes, returns NULL.\n */\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __ksym;\n\n/* Description\n *\tAllocates a percpu object of the type represented by \'local_type_id\' in\n *\tprogram BTF. User may use the bpf_core_type_id_local macro to pass the\n *\ttype ID of a struct in program BTF.\n *\n *\tThe \'local_type_id\' parameter must be a known constant.\n *\tThe \'meta\' parameter is rewritten by the verifier, no need for BPF\n *\tprogram to set it.\n * Returns\n *\tA pointer to a percpu object of the type corresponding to the passed in\n *\t\'local_type_id\', or NULL on failure.\n */\nextern void *bpf_percpu_obj_new_impl(__u64 local_type_id, void *meta) __ksym;\n\n/* Convenience macro to wrap over bpf_percpu_obj_new_impl */\n#define bpf_percpu_obj_new(type) ((type __percpu_kptr *)bpf_percpu_obj_new_impl(bpf_core_type_id_local(type), NULL))\n\n/* Description\n *\tFree an allocated percpu object. All fields of the object that require\n *\tdestruction will be destructed before the storage is freed.\n *\n *\tThe \'meta\' parameter is rewritten by the verifier, no need for BPF\n *\tprogram to set it.\n * Returns\n *\tVoid.\n */\nextern void bpf_percpu_obj_drop_impl(void *kptr, void *meta) __ksym;\n\nstruct bpf_iter_task_vma;\n\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it,\n\t\t\t\t struct task_struct *task,\n\t\t\t\t __u64 addr) __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __ksym;\n\n/* Convenience macro to wrap over bpf_obj_drop_impl */\n#define bpf_percpu_obj_drop(kptr) bpf_percpu_obj_drop_impl(kptr, NULL)\n\n/* Description\n *\tThrow a BPF exception from the program, immediately terminating its\n *\texecution and unwinding the stack. The supplied \'cookie\' parameter\n *\twill be the return value of the program when an exception is thrown,\n *\tand the default exception callback is used. Otherwise, if an exception\n *\tcallback is set using the \'__exception_cb(callback)\' declaration tag\n *\ton the main program, the \'cookie\' parameter will be the callback\'s only\n *\tinput argument.\n *\n *\tThus, in case of default exception callback, \'cookie\' is subjected to\n *\tconstraints on the program\'s return value (as with R0 on exit).\n *\tOtherwise, the return value of the marked exception callback will be\n *\tsubjected to the same checks.\n *\n *\tNote that throwing an exception with lingering resources (locks,\n *\treferences, etc.) will lead to a verification error.\n *\n *\tNote that callbacks *cannot* call this helper.\n * Returns\n *\tNever.\n * Throws\n *\tAn exception with the specified \'cookie\' value.\n */\nextern void bpf_throw(u64 cookie) __ksym;\n\n/* Description\n *\tAcquire a reference on the exe_file member field belonging to the\n *\tmm_struct that is nested within the supplied task_struct. The supplied\n *\ttask_struct must be trusted/referenced.\n * Returns\n *\tA referenced file pointer pointing to the exe_file member field of the\n *\tmm_struct nested in the supplied task_struct, or NULL.\n */\nextern struct file *bpf_get_task_exe_file(struct task_struct *task) __ksym;\n\n/* Description\n *\tRelease a reference on the supplied file. The supplied file must be\n *\tacquired.\n */\nextern void bpf_put_file(struct file *file) __ksym;\n\n/* Description\n *\tResolve a pathname for the supplied path and store it in the supplied\n *\tbuffer. The supplied path must be trusted/referenced.\n * Returns\n *\tA positive integer corresponding to the length of the resolved pathname,\n *\tincluding the NULL termination character, stored in the supplied\n *\tbuffer. On error, a negative integer is returned.\n */\nextern int bpf_path_d_path(const struct path *path, char *buf, size_t buf__sz) __ksym;\n\n/* This macro must be used to mark the exception callback corresponding to the\n * main program. For example:\n *\n * int exception_cb(u64 cookie) {\n *\treturn cookie;\n * }\n *\n * SEC(\"tc\")\n * __exception_cb(exception_cb)\n * int main_prog(struct __sk_buff *ctx) {\n *\t...\n *\treturn TC_ACT_OK;\n * }\n *\n * Here, exception callback for the main program will be \'exception_cb\'. Note\n * that this attribute can only be used once, and multiple exception callbacks\n * specified for the main program will lead to verification error.\n */\n#define __exception_cb(name) __attribute__((btf_decl_tag(\"exception_callback:\" #name)))\n\n#define __bpf_assert_signed(x) _Generic((x), \\\n unsigned long: 0, \\\n unsigned long long: 0, \\\n signed long: 1, \\\n signed long long: 1 \\\n)\n\n#define __bpf_assert_check(LHS, op, RHS)\t\t\t\t\t\t\t\t \\\n\t_Static_assert(sizeof(&(LHS)), \"1st argument must be an lvalue expression\");\t\t\t \\\n\t_Static_assert(sizeof(LHS) == 8, \"Only 8-byte integers are supported\\n\");\t\t\t \\\n\t_Static_assert(__builtin_constant_p(__bpf_assert_signed(LHS)), \"internal static assert\");\t \\\n\t_Static_assert(__builtin_constant_p((RHS)), \"2nd argument must be a constant expression\")\n\n#define __bpf_assert(LHS, op, cons, RHS, VAL)\t\t\t\t\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t(void)bpf_throw;\t\t\t\t\t\t\t\t\\\n\t\tasm volatile (\"if %[lhs] \" op \" %[rhs] goto +2; r1 = %[value]; call bpf_throw\"\t\\\n\t\t\t : : [lhs] \"r\"(LHS), [rhs] cons(RHS), [value] \"ri\"(VAL) : );\t\\\n\t})\n\n#define __bpf_assert_op_sign(LHS, op, cons, RHS, VAL, supp_sign)\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\t\t\\\n\t\t__bpf_assert_check(LHS, op, RHS);\t\t\t\t\t\\\n\t\tif (__bpf_assert_signed(LHS) && !(supp_sign))\t\t\t\t\\\n\t\t\t__bpf_assert(LHS, \"s\" #op, cons, RHS, VAL);\t\t\t\\\n\t\telse\t\t\t\t\t\t\t\t\t\\\n\t\t\t__bpf_assert(LHS, #op, cons, RHS, VAL);\t\t\t\t\\\n\t })\n\n#define __bpf_assert_op(LHS, op, RHS, VAL, supp_sign)\t\t\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\t\t\\\n\t\tif (sizeof(typeof(RHS)) == 8) {\t\t\t\t\t\t\\\n\t\t\tconst typeof(RHS) rhs_var = (RHS);\t\t\t\t\\\n\t\t\t__bpf_assert_op_sign(LHS, op, \"r\", rhs_var, VAL, supp_sign);\t\\\n\t\t} else {\t\t\t\t\t\t\t\t\\\n\t\t\t__bpf_assert_op_sign(LHS, op, \"i\", RHS, VAL, supp_sign);\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\\\n\t })\n\n#define __cmp_cannot_be_signed(x) \\\n\t__builtin_strcmp(#x, \"==\") == 0 || __builtin_strcmp(#x, \"!=\") == 0 || \\\n\t__builtin_strcmp(#x, \"&\") == 0\n\n#define __is_signed_type(type) (((type)(-1)) < (type)1)\n\n#define __bpf_cmp(LHS, OP, PRED, RHS, DEFAULT)\t\t\t\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t__label__ l_true;\t\t\t\t\t\t\t\t\\\n\t\tbool ret = DEFAULT;\t\t\t\t\t\t\t\t\\\n\t\tasm volatile goto(\"if %[lhs] \" OP \" %[rhs] goto %l[l_true]\"\t\t\\\n\t\t\t\t :: [lhs] \"r\"((short)LHS), [rhs] PRED (RHS) :: l_true);\t\\\n\t\tret = !DEFAULT;\t\t\t\t\t\t\t\t\t\\\nl_true:\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tret;\t\t\t\t\t\t\t\t\t\t\\\n })\n\n/* C type conversions coupled with comparison operator are tricky.\n * Make sure BPF program is compiled with -Wsign-compare then\n * __lhs OP __rhs below will catch the mistake.\n * Be aware that we check only __lhs to figure out the sign of compare.\n */\n#define _bpf_cmp(LHS, OP, RHS, UNLIKELY)\t\t\t\t\t\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\t\t\t\\\n\t\ttypeof(LHS) __lhs = (LHS);\t\t\t\t\t\t\t\\\n\t\ttypeof(RHS) __rhs = (RHS);\t\t\t\t\t\t\t\\\n\t\tbool ret;\t\t\t\t\t\t\t\t\t\\\n\t\t_Static_assert(sizeof(&(LHS)), \"1st argument must be an lvalue expression\");\t\\\n\t\t(void)(__lhs OP __rhs);\t\t\t\t\t\t\t\t\\\n\t\tif (__cmp_cannot_be_signed(OP) || !__is_signed_type(typeof(__lhs))) {\t\t\\\n\t\t\tif (sizeof(__rhs) == 8)\t\t\t\t\t\t\t\\\n\t\t\t\t/* \"i\" will truncate 64-bit constant into s32,\t\t\t\\\n\t\t\t\t * so we have to use extra register via \"r\".\t\t\t\\\n\t\t\t\t */\t\t\t\t\t\t\t\t\\\n\t\t\t\tret = __bpf_cmp(__lhs, #OP, \"r\", __rhs, UNLIKELY);\t\t\\\n\t\t\telse\t\t\t\t\t\t\t\t\t\\\n\t\t\t\tret = __bpf_cmp(__lhs, #OP, \"ri\", __rhs, UNLIKELY);\t\t\\\n\t\t} else {\t\t\t\t\t\t\t\t\t\\\n\t\t\tif (sizeof(__rhs) == 8)\t\t\t\t\t\t\t\\\n\t\t\t\tret = __bpf_cmp(__lhs, \"s\"#OP, \"r\", __rhs, UNLIKELY);\t\t\\\n\t\t\telse\t\t\t\t\t\t\t\t\t\\\n\t\t\t\tret = __bpf_cmp(__lhs, \"s\"#OP, \"ri\", __rhs, UNLIKELY);\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\\\n\t\tret;\t\t\t\t\t\t\t\t\t\t\\\n })\n\n#ifndef bpf_cmp_unlikely\n#define bpf_cmp_unlikely(LHS, OP, RHS) _bpf_cmp(LHS, OP, RHS, true)\n#endif\n\n#ifndef bpf_cmp_likely\n#define bpf_cmp_likely(LHS, OP, RHS)\t\t\t\t\t\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tbool ret = 0;\t\t\t\t\t\t\t\t\t\\\n\t\tif (__builtin_strcmp(#OP, \"==\") == 0)\t\t\t\t\t\t\\\n\t\t\tret = _bpf_cmp(LHS, !=, RHS, false);\t\t\t\t\t\\\n\t\telse if (__builtin_strcmp(#OP, \"!=\") == 0)\t\t\t\t\t\\\n\t\t\tret = _bpf_cmp(LHS, ==, RHS, false);\t\t\t\t\t\\\n\t\telse if (__builtin_strcmp(#OP, \"<=\") == 0)\t\t\t\t\t\\\n\t\t\tret = _bpf_cmp(LHS, >, RHS, false);\t\t\t\t\t\\\n\t\telse if (__builtin_strcmp(#OP, \"<\") == 0)\t\t\t\t\t\\\n\t\t\tret = _bpf_cmp(LHS, >=, RHS, false);\t\t\t\t\t\\\n\t\telse if (__builtin_strcmp(#OP, \">\") == 0)\t\t\t\t\t\\\n\t\t\tret = _bpf_cmp(LHS, <=, RHS, false);\t\t\t\t\t\\\n\t\telse if (__builtin_strcmp(#OP, \">=\") == 0)\t\t\t\t\t\\\n\t\t\tret = _bpf_cmp(LHS, <, RHS, false);\t\t\t\t\t\\\n\t\telse\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tasm volatile(\"r0 \" #OP \" invalid compare\");\t\t\t\t\\\n\t\tret;\t\t\t\t\t\t\t\t\t\t\\\n })\n#endif\n\n/*\n * Note that cond_break can only be portably used in the body of a breakable\n * construct, whereas can_loop can be used anywhere.\n */\n#ifdef __BPF_FEATURE_MAY_GOTO\n#define can_loop\t\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tbool ret = true;\t\t\t\t\\\n\tasm volatile goto(\"may_goto %l[l_break]\"\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: ret = false;\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\tret;\t\t\t\t\t\t\\\n\t})\n\n#define __cond_break(expr)\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tasm volatile goto(\"may_goto %l[l_break]\"\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: expr;\t\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\t})\n#else\n#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n#define can_loop\t\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tbool ret = true;\t\t\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long ((%l[l_break] - 1b - 8) / 8) & 0xffff;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: ret = false;\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\tret;\t\t\t\t\t\t\\\n\t})\n\n#define __cond_break(expr)\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long ((%l[l_break] - 1b - 8) / 8) & 0xffff;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: expr;\t\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\t})\n#else\n#define can_loop\t\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tbool ret = true;\t\t\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long (((%l[l_break] - 1b - 8) / 8) & 0xffff) << 16;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: ret = false;\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\tret;\t\t\t\t\t\t\\\n\t})\n\n#define __cond_break(expr)\t\t\t\t\\\n\t({ __label__ l_break, l_continue;\t\t\\\n\tasm volatile goto(\"1:.byte 0xe5;\t\t\\\n\t\t .byte 0;\t\t\t\t\\\n\t\t .long (((%l[l_break] - 1b - 8) / 8) & 0xffff) << 16;\t\\\n\t\t .short 0\"\t\t\t\t\\\n\t\t :::: l_break);\t\t\t\\\n\tgoto l_continue;\t\t\t\t\\\n\tl_break: expr;\t\t\t\t\t\\\n\tl_continue:;\t\t\t\t\t\\\n\t})\n#endif\n#endif\n\n#define cond_break __cond_break(break)\n#define cond_break_label(label) __cond_break(goto label)\n\n#ifndef bpf_nop_mov\n#define bpf_nop_mov(var) \\\n\tasm volatile(\"%[reg]=%[reg]\"::[reg]\"r\"((short)var))\n#endif\n\n/* emit instruction:\n * rX = rX .off = BPF_ADDR_SPACE_CAST .imm32 = (dst_as << 16) | src_as\n */\n#ifndef bpf_addr_space_cast\n#define bpf_addr_space_cast(var, dst_as, src_as)\\\n\tasm volatile(\".byte 0xBF;\t\t\\\n\t\t .ifc %[reg], r0;\t\t\\\n\t\t .byte 0x00;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r1;\t\t\\\n\t\t .byte 0x11;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r2;\t\t\\\n\t\t .byte 0x22;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r3;\t\t\\\n\t\t .byte 0x33;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r4;\t\t\\\n\t\t .byte 0x44;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r5;\t\t\\\n\t\t .byte 0x55;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r6;\t\t\\\n\t\t .byte 0x66;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r7;\t\t\\\n\t\t .byte 0x77;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r8;\t\t\\\n\t\t .byte 0x88;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .ifc %[reg], r9;\t\t\\\n\t\t .byte 0x99;\t\t\\\n\t\t .endif;\t\t\t\\\n\t\t .short %[off];\t\t\\\n\t\t .long %[as]\"\t\t\\\n\t\t : [reg]\"+r\"(var)\t\t\\\n\t\t : [off]\"i\"(BPF_ADDR_SPACE_CAST) \\\n\t\t , [as]\"i\"((dst_as << 16) | src_as));\n#endif\n\nvoid bpf_preempt_disable(void) __weak __ksym;\nvoid bpf_preempt_enable(void) __weak __ksym;\n\ntypedef struct {\n} __bpf_preempt_t;\n\nstatic inline __bpf_preempt_t __bpf_preempt_constructor(void)\n{\n\t__bpf_preempt_t ret = {};\n\n\tbpf_preempt_disable();\n\treturn ret;\n}\nstatic inline void __bpf_preempt_destructor(__bpf_preempt_t *t)\n{\n\tbpf_preempt_enable();\n}\n#define bpf_guard_preempt() \\\n\t__bpf_preempt_t ___bpf_apply(preempt, __COUNTER__)\t\t\t\\\n\t__attribute__((__unused__, __cleanup__(__bpf_preempt_destructor))) =\t\\\n\t__bpf_preempt_constructor()\n\n/* Description\n *\tAssert that a conditional expression is true.\n * Returns\n *\tVoid.\n * Throws\n *\tAn exception with the value zero when the assertion fails.\n */\n#define bpf_assert(cond) if (!(cond)) bpf_throw(0);\n\n/* Description\n *\tAssert that a conditional expression is true.\n * Returns\n *\tVoid.\n * Throws\n *\tAn exception with the specified value when the assertion fails.\n */\n#define bpf_assert_with(cond, value) if (!(cond)) bpf_throw(value);\n\n/* Description\n *\tAssert that LHS is in the range [BEG, END] (inclusive of both). This\n *\tstatement updates the known bounds of LHS during verification. Note\n *\tthat both BEG and END must be constant values, and must fit within the\n *\tdata type of LHS.\n * Returns\n *\tVoid.\n * Throws\n *\tAn exception with the value zero when the assertion fails.\n */\n#define bpf_assert_range(LHS, BEG, END)\t\t\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\\\n\t\t_Static_assert(BEG <= END, \"BEG must be <= END\");\t\\\n\t\tbarrier_var(LHS);\t\t\t\t\t\\\n\t\t__bpf_assert_op(LHS, >=, BEG, 0, false);\t\t\\\n\t\t__bpf_assert_op(LHS, <=, END, 0, false);\t\t\\\n\t})\n\n/* Description\n *\tAssert that LHS is in the range [BEG, END] (inclusive of both). This\n *\tstatement updates the known bounds of LHS during verification. Note\n *\tthat both BEG and END must be constant values, and must fit within the\n *\tdata type of LHS.\n * Returns\n *\tVoid.\n * Throws\n *\tAn exception with the specified value when the assertion fails.\n */\n#define bpf_assert_range_with(LHS, BEG, END, value)\t\t\t\\\n\t({\t\t\t\t\t\t\t\t\\\n\t\t_Static_assert(BEG <= END, \"BEG must be <= END\");\t\\\n\t\tbarrier_var(LHS);\t\t\t\t\t\\\n\t\t__bpf_assert_op(LHS, >=, BEG, value, false);\t\t\\\n\t\t__bpf_assert_op(LHS, <=, END, value, false);\t\t\\\n\t})\n\nstruct bpf_iter_css_task;\nstruct cgroup_subsys_state;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it,\n\t\tstruct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\n\nstruct bpf_iter_task;\nextern int bpf_iter_task_new(struct bpf_iter_task *it,\n\t\tstruct task_struct *task, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\n\nstruct bpf_iter_css;\nextern int bpf_iter_css_new(struct bpf_iter_css *it,\n\t\t\t\tstruct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\n\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\n\nstruct bpf_iter_kmem_cache;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\n\nstruct bpf_iter_dmabuf;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\n\nextern int bpf_cgroup_read_xattr(struct cgroup *cgroup, const char *name__str,\n\t\t\t\t struct bpf_dynptr *value_p) __weak __ksym;\n\n#define PREEMPT_BITS\t8\n#define SOFTIRQ_BITS\t8\n#define HARDIRQ_BITS\t4\n#define NMI_BITS\t4\n\n#define PREEMPT_SHIFT\t0\n#define SOFTIRQ_SHIFT\t(PREEMPT_SHIFT + PREEMPT_BITS)\n#define HARDIRQ_SHIFT\t(SOFTIRQ_SHIFT + SOFTIRQ_BITS)\n#define NMI_SHIFT\t(HARDIRQ_SHIFT + HARDIRQ_BITS)\n\n#define __IRQ_MASK(x)\t((1UL << (x))-1)\n\n#define SOFTIRQ_MASK\t(__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT)\n#define HARDIRQ_MASK\t(__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT)\n#define NMI_MASK\t(__IRQ_MASK(NMI_BITS) << NMI_SHIFT)\n\n#define SOFTIRQ_OFFSET\t(1UL << SOFTIRQ_SHIFT)\n\nextern bool CONFIG_PREEMPT_RT __kconfig __weak;\n#ifdef bpf_target_x86\nextern const int __preempt_count __ksym __weak;\n\nstruct pcpu_hot___local {\n\tint preempt_count;\n} __attribute__((preserve_access_index));\n\nextern struct pcpu_hot___local pcpu_hot __ksym __weak;\n#endif\n\nstruct task_struct___preempt_rt {\n\tint softirq_disable_cnt;\n} __attribute__((preserve_access_index));\n\nstatic inline int get_preempt_count(void)\n{\n#if defined(bpf_target_x86)\n\t/* By default, read the per-CPU __preempt_count. */\n\tif (bpf_ksym_exists(&__preempt_count))\n\t\treturn *(int *) bpf_this_cpu_ptr(&__preempt_count);\n\n\t/*\n\t * If __preempt_count does not exist, try to read preempt_count under\n\t * struct pcpu_hot. Between v6.1 and v6.14 -- more specifically,\n\t * [64701838bf057, 46e8fff6d45fe), preempt_count had been managed\n\t * under struct pcpu_hot.\n\t */\n\tif (bpf_core_field_exists(pcpu_hot.preempt_count))\n\t\treturn ((struct pcpu_hot___local *)\n\t\t\tbpf_this_cpu_ptr(&pcpu_hot))->preempt_count;\n#elif defined(bpf_target_arm64)\n\treturn bpf_get_current_task_btf()->thread_info.preempt.count;\n#endif\n\treturn 0;\n}\n\n/* Description\n *\tReport whether it is in interrupt context. Only works on the following archs:\n *\t* x86\n *\t* arm64\n */\nstatic inline int bpf_in_interrupt(void)\n{\n\tstruct task_struct___preempt_rt *tsk;\n\tint pcnt;\n\n\tpcnt = get_preempt_count();\n\tif (!CONFIG_PREEMPT_RT)\n\t\treturn pcnt & (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_MASK);\n\n\ttsk = (void *) bpf_get_current_task_btf();\n\treturn (pcnt & (NMI_MASK | HARDIRQ_MASK)) |\n\t (tsk->softirq_disable_cnt & SOFTIRQ_MASK);\n}\n\n/* Description\n *\tReport whether it is in NMI context. Only works on the following archs:\n *\t* x86\n *\t* arm64\n */\nstatic inline int bpf_in_nmi(void)\n{\n\treturn get_preempt_count() & NMI_MASK;\n}\n\n/* Description\n *\tReport whether it is in hard IRQ context. Only works on the following archs:\n *\t* x86\n *\t* arm64\n */\nstatic inline int bpf_in_hardirq(void)\n{\n\treturn get_preempt_count() & HARDIRQ_MASK;\n}\n\n/* Description\n *\tReport whether it is in softirq context. Only works on the following archs:\n *\t* x86\n *\t* arm64\n */\nstatic inline int bpf_in_serving_softirq(void)\n{\n\tstruct task_struct___preempt_rt *tsk;\n\tint pcnt;\n\n\tpcnt = get_preempt_count();\n\tif (!CONFIG_PREEMPT_RT)\n\t\treturn (pcnt & SOFTIRQ_MASK) & SOFTIRQ_OFFSET;\n\n\ttsk = (void *) bpf_get_current_task_btf();\n\treturn (tsk->softirq_disable_cnt & SOFTIRQ_MASK) & SOFTIRQ_OFFSET;\n}\n\n/* Description\n *\tReport whether it is in task context. Only works on the following archs:\n *\t* x86\n *\t* arm64\n */\nstatic inline int bpf_in_task(void)\n{\n\tstruct task_struct___preempt_rt *tsk;\n\tint pcnt;\n\n\tpcnt = get_preempt_count();\n\tif (!CONFIG_PREEMPT_RT)\n\t\treturn !(pcnt & (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET));\n\n\ttsk = (void *) bpf_get_current_task_btf();\n\treturn !((pcnt & (NMI_MASK | HARDIRQ_MASK)) |\n\t\t ((tsk->softirq_disable_cnt & SOFTIRQ_MASK) & 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diagnostic ignored \"-Wmissing-declarations\"\n#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DMPS = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_CPD = 1048576,\n\tPORT_CMD_MPSP = 524288,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_CMD_CAP = 8126464,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_SUSPEND_PHYS = 33554432,\n\tAHCI_HFLAG_NO_SXS = 67108864,\n\tAHCI_HFLAG_43BIT_ONLY = 134217728,\n\tAHCI_HFLAG_INTEL_PCS_QUIRK = 268435456,\n\tAHCI_HFLAG_ATAPI_DMA_QUIRK = 536870912,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 15,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tASSUME_PERFECT = 255,\n\tASSUME_VALID_DTB = 1,\n\tASSUME_VALID_INPUT = 2,\n\tASSUME_LATEST = 4,\n\tASSUME_NO_ROLLBACK = 8,\n\tASSUME_LIBFDT_ORDER = 16,\n\tASSUME_LIBFDT_FLAWLESS = 32,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = -2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = -2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_CDL = 24,\n\tATA_LOG_CDL_SIZE = 512,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SENSE_NCQ = 15,\n\tATA_LOG_SENSE_NCQ_SIZE = 1024,\n\tATA_LOG_CONCURRENT_POSITIONING_RANGES = 71,\n\tATA_LOG_SUPPORTED_CAPABILITIES = 3,\n\tATA_LOG_CURRENT_SETTINGS = 4,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSETFEATURES_CDL = 13,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tSETFEATURE_SENSE_DATA_SUCC_NCQ = 196,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum {\n\tATA_QUIRK_DIAGNOSTIC = 1,\n\tATA_QUIRK_NODMA = 2,\n\tATA_QUIRK_NONCQ = 4,\n\tATA_QUIRK_BROKEN_HPA = 8,\n\tATA_QUIRK_DISABLE = 16,\n\tATA_QUIRK_HPA_SIZE = 32,\n\tATA_QUIRK_IVB = 64,\n\tATA_QUIRK_STUCK_ERR = 128,\n\tATA_QUIRK_BRIDGE_OK = 256,\n\tATA_QUIRK_ATAPI_MOD16_DMA = 512,\n\tATA_QUIRK_FIRMWARE_WARN = 1024,\n\tATA_QUIRK_1_5_GBPS = 2048,\n\tATA_QUIRK_NOSETXFER = 4096,\n\tATA_QUIRK_BROKEN_FPDMA_AA = 8192,\n\tATA_QUIRK_DUMP_ID = 16384,\n\tATA_QUIRK_MAX_SEC_LBA48 = 32768,\n\tATA_QUIRK_ATAPI_DMADIR = 65536,\n\tATA_QUIRK_NO_NCQ_TRIM = 131072,\n\tATA_QUIRK_NOLPM = 262144,\n\tATA_QUIRK_WD_BROKEN_LPM = 524288,\n\tATA_QUIRK_ZERO_AFTER_TRIM = 1048576,\n\tATA_QUIRK_NO_DMA_LOG = 2097152,\n\tATA_QUIRK_NOTRIM = 4194304,\n\tATA_QUIRK_MAX_SEC = 8388608,\n\tATA_QUIRK_MAX_TRIM_128M = 16777216,\n\tATA_QUIRK_NO_NCQ_ON_ATI = 33554432,\n\tATA_QUIRK_NO_LPM_ON_ATI = 67108864,\n\tATA_QUIRK_NO_ID_DEV_LOG = 134217728,\n\tATA_QUIRK_NO_LOG_DIR = 268435456,\n\tATA_QUIRK_NO_FUA = 536870912,\n};\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = -2147483648,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tBATTERY_INT_STATUS = 0,\n\tBATTERY_INT_ENABLE = 4,\n\tBATTERY_AC_ONLINE = 8,\n\tBATTERY_STATUS = 12,\n\tBATTERY_HEALTH = 16,\n\tBATTERY_PRESENT = 20,\n\tBATTERY_CAPACITY = 24,\n\tBATTERY_VOLTAGE = 28,\n\tBATTERY_TEMP = 32,\n\tBATTERY_CHARGE_COUNTER = 36,\n\tBATTERY_VOLTAGE_MAX = 40,\n\tBATTERY_CURRENT_MAX = 44,\n\tBATTERY_CURRENT_NOW = 48,\n\tBATTERY_CURRENT_AVG = 52,\n\tBATTERY_CHARGE_FULL_UAH = 56,\n\tBATTERY_CYCLE_COUNT = 64,\n\tBATTERY_STATUS_CHANGED = 1,\n\tAC_STATUS_CHANGED = 2,\n\tBATTERY_INT_MASK = 3,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 38,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBRIDGE_QUERIER_UNSPEC = 0,\n\tBRIDGE_QUERIER_IP_ADDRESS = 1,\n\tBRIDGE_QUERIER_IP_PORT = 2,\n\tBRIDGE_QUERIER_IP_OTHER_TIMER = 3,\n\tBRIDGE_QUERIER_PAD = 4,\n\tBRIDGE_QUERIER_IPV6_ADDRESS = 5,\n\tBRIDGE_QUERIER_IPV6_PORT = 6,\n\tBRIDGE_QUERIER_IPV6_OTHER_TIMER = 7,\n\t__BRIDGE_QUERIER_MAX = 8,\n};\n\nenum {\n\tBRIDGE_XSTATS_UNSPEC = 0,\n\tBRIDGE_XSTATS_VLAN = 1,\n\tBRIDGE_XSTATS_MCAST = 2,\n\tBRIDGE_XSTATS_PAD = 3,\n\tBRIDGE_XSTATS_STP = 4,\n\t__BRIDGE_XSTATS_MAX = 5,\n};\n\nenum {\n\tBR_FDB_LOCAL = 0,\n\tBR_FDB_STATIC = 1,\n\tBR_FDB_STICKY = 2,\n\tBR_FDB_ADDED_BY_USER = 3,\n\tBR_FDB_ADDED_BY_EXT_LEARN = 4,\n\tBR_FDB_OFFLOADED = 5,\n\tBR_FDB_NOTIFY = 6,\n\tBR_FDB_NOTIFY_INACTIVE = 7,\n\tBR_FDB_LOCKED = 8,\n\tBR_FDB_DYNAMIC_LEARNED = 9,\n};\n\nenum {\n\tBR_GROUPFWD_STP = 1,\n\tBR_GROUPFWD_MACPAUSE = 2,\n\tBR_GROUPFWD_LACP = 4,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBR_VLFLAG_PER_PORT_STATS = 1,\n\tBR_VLFLAG_ADDED_BY_SWITCHDEV = 2,\n\tBR_VLFLAG_MCAST_ENABLED = 4,\n\tBR_VLFLAG_GLOBAL_MCAST_ENABLED = 8,\n\tBR_VLFLAG_NEIGH_SUPPRESS_ENABLED = 16,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tCACHE_VALID = 0,\n\tCACHE_NEGATIVE = 1,\n\tCACHE_PENDING = 2,\n\tCACHE_CLEANED = 3,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 250,\n\tCRNG_RESEED_INTERVAL = 15000,\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\t__CRYPTOA_MAX = 3,\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tDAD_PROCESS = 0,\n\tDAD_BEGIN = 1,\n\tDAD_ABORT = 2,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEVCONF_FORWARDING = 0,\n\tDEVCONF_HOPLIMIT = 1,\n\tDEVCONF_MTU6 = 2,\n\tDEVCONF_ACCEPT_RA = 3,\n\tDEVCONF_ACCEPT_REDIRECTS = 4,\n\tDEVCONF_AUTOCONF = 5,\n\tDEVCONF_DAD_TRANSMITS = 6,\n\tDEVCONF_RTR_SOLICITS = 7,\n\tDEVCONF_RTR_SOLICIT_INTERVAL = 8,\n\tDEVCONF_RTR_SOLICIT_DELAY = 9,\n\tDEVCONF_USE_TEMPADDR = 10,\n\tDEVCONF_TEMP_VALID_LFT = 11,\n\tDEVCONF_TEMP_PREFERED_LFT = 12,\n\tDEVCONF_REGEN_MAX_RETRY = 13,\n\tDEVCONF_MAX_DESYNC_FACTOR = 14,\n\tDEVCONF_MAX_ADDRESSES = 15,\n\tDEVCONF_FORCE_MLD_VERSION = 16,\n\tDEVCONF_ACCEPT_RA_DEFRTR = 17,\n\tDEVCONF_ACCEPT_RA_PINFO = 18,\n\tDEVCONF_ACCEPT_RA_RTR_PREF = 19,\n\tDEVCONF_RTR_PROBE_INTERVAL = 20,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN = 21,\n\tDEVCONF_PROXY_NDP = 22,\n\tDEVCONF_OPTIMISTIC_DAD = 23,\n\tDEVCONF_ACCEPT_SOURCE_ROUTE = 24,\n\tDEVCONF_MC_FORWARDING = 25,\n\tDEVCONF_DISABLE_IPV6 = 26,\n\tDEVCONF_ACCEPT_DAD = 27,\n\tDEVCONF_FORCE_TLLAO = 28,\n\tDEVCONF_NDISC_NOTIFY = 29,\n\tDEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL = 30,\n\tDEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL = 31,\n\tDEVCONF_SUPPRESS_FRAG_NDISC = 32,\n\tDEVCONF_ACCEPT_RA_FROM_LOCAL = 33,\n\tDEVCONF_USE_OPTIMISTIC = 34,\n\tDEVCONF_ACCEPT_RA_MTU = 35,\n\tDEVCONF_STABLE_SECRET = 36,\n\tDEVCONF_USE_OIF_ADDRS_ONLY = 37,\n\tDEVCONF_ACCEPT_RA_MIN_HOP_LIMIT = 38,\n\tDEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 39,\n\tDEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 40,\n\tDEVCONF_DROP_UNSOLICITED_NA = 41,\n\tDEVCONF_KEEP_ADDR_ON_DOWN = 42,\n\tDEVCONF_RTR_SOLICIT_MAX_INTERVAL = 43,\n\tDEVCONF_SEG6_ENABLED = 44,\n\tDEVCONF_SEG6_REQUIRE_HMAC = 45,\n\tDEVCONF_ENHANCED_DAD = 46,\n\tDEVCONF_ADDR_GEN_MODE = 47,\n\tDEVCONF_DISABLE_POLICY = 48,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN = 49,\n\tDEVCONF_NDISC_TCLASS = 50,\n\tDEVCONF_RPL_SEG_ENABLED = 51,\n\tDEVCONF_RA_DEFRTR_METRIC = 52,\n\tDEVCONF_IOAM6_ENABLED = 53,\n\tDEVCONF_IOAM6_ID = 54,\n\tDEVCONF_IOAM6_ID_WIDE = 55,\n\tDEVCONF_NDISC_EVICT_NOCARRIER = 56,\n\tDEVCONF_ACCEPT_UNTRACKED_NA = 57,\n\tDEVCONF_ACCEPT_RA_MIN_LFT = 58,\n\tDEVCONF_FORCE_FORWARDING = 59,\n\tDEVCONF_MAX = 60,\n};\n\nenum {\n\tDEVLINK_ATTR_STATS_RX_PACKETS = 0,\n\tDEVLINK_ATTR_STATS_RX_BYTES = 1,\n\tDEVLINK_ATTR_STATS_RX_DROPPED = 2,\n\t__DEVLINK_ATTR_STATS_MAX = 3,\n\tDEVLINK_ATTR_STATS_MAX = 2,\n};\n\nenum {\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_IN_PORT = 0,\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_FA_COOKIE = 1,\n};\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDSA_NOTIFIER_AGEING_TIME = 0,\n\tDSA_NOTIFIER_BRIDGE_JOIN = 1,\n\tDSA_NOTIFIER_BRIDGE_LEAVE = 2,\n\tDSA_NOTIFIER_FDB_ADD = 3,\n\tDSA_NOTIFIER_FDB_DEL = 4,\n\tDSA_NOTIFIER_HOST_FDB_ADD = 5,\n\tDSA_NOTIFIER_HOST_FDB_DEL = 6,\n\tDSA_NOTIFIER_LAG_FDB_ADD = 7,\n\tDSA_NOTIFIER_LAG_FDB_DEL = 8,\n\tDSA_NOTIFIER_LAG_CHANGE = 9,\n\tDSA_NOTIFIER_LAG_JOIN = 10,\n\tDSA_NOTIFIER_LAG_LEAVE = 11,\n\tDSA_NOTIFIER_MDB_ADD = 12,\n\tDSA_NOTIFIER_MDB_DEL = 13,\n\tDSA_NOTIFIER_HOST_MDB_ADD = 14,\n\tDSA_NOTIFIER_HOST_MDB_DEL = 15,\n\tDSA_NOTIFIER_VLAN_ADD = 16,\n\tDSA_NOTIFIER_VLAN_DEL = 17,\n\tDSA_NOTIFIER_HOST_VLAN_ADD = 18,\n\tDSA_NOTIFIER_HOST_VLAN_DEL = 19,\n\tDSA_NOTIFIER_MTU = 20,\n\tDSA_NOTIFIER_TAG_PROTO = 21,\n\tDSA_NOTIFIER_TAG_PROTO_CONNECT = 22,\n\tDSA_NOTIFIER_TAG_PROTO_DISCONNECT = 23,\n\tDSA_NOTIFIER_TAG_8021Q_VLAN_ADD = 24,\n\tDSA_NOTIFIER_TAG_8021Q_VLAN_DEL = 25,\n\tDSA_NOTIFIER_CONDUIT_STATE_CHANGE = 26,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tES0_ACTION_TYPE_NORMAL = 0,\n\tES0_ACTION_TYPE_MAX = 1,\n};\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_CODE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_CODE_OK = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE_OPEN = 2,\n\tETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT = 3,\n\tETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT = 4,\n\tETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH = 5,\n\tETHTOOL_A_CABLE_RESULT_CODE_NOISE = 6,\n\tETHTOOL_A_CABLE_RESULT_CODE_RESOLUTION_NOT_POSSIBLE = 7,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENT_CMD_COMPLETE = 0,\n\tEVENT_XFER_COMPLETE = 1,\n\tEVENT_DATA_COMPLETE = 2,\n\tEVENT_DATA_ERROR = 3,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEXT4_FC_REASON_XATTR = 0,\n\tEXT4_FC_REASON_CROSS_RENAME = 1,\n\tEXT4_FC_REASON_JOURNAL_FLAG_CHANGE = 2,\n\tEXT4_FC_REASON_NOMEM = 3,\n\tEXT4_FC_REASON_SWAP_BOOT = 4,\n\tEXT4_FC_REASON_RESIZE = 5,\n\tEXT4_FC_REASON_RENAME_DIR = 6,\n\tEXT4_FC_REASON_FALLOC_RANGE = 7,\n\tEXT4_FC_REASON_INODE_JOURNAL_DATA = 8,\n\tEXT4_FC_REASON_ENCRYPTED_FILENAME = 9,\n\tEXT4_FC_REASON_MIGRATE = 10,\n\tEXT4_FC_REASON_VERITY = 11,\n\tEXT4_FC_REASON_MOVE_EXT = 12,\n\tEXT4_FC_REASON_MAX = 13,\n};\n\nenum {\n\tEXT4_FC_STATUS_OK = 0,\n\tEXT4_FC_STATUS_INELIGIBLE = 1,\n\tEXT4_FC_STATUS_SKIPPED = 2,\n\tEXT4_FC_STATUS_FAILED = 3,\n};\n\nenum {\n\tEXT4_FLAGS_RESIZING = 0,\n\tEXT4_FLAGS_SHUTDOWN = 1,\n\tEXT4_FLAGS_BDEV_IS_DAX = 2,\n\tEXT4_FLAGS_EMERGENCY_RO = 3,\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nenum {\n\tEXT4_MF_MNTDIR_SAMPLED = 0,\n\tEXT4_MF_FC_INELIGIBLE = 1,\n\tEXT4_MF_JOURNAL_DESTROY = 2,\n};\n\nenum {\n\tEXT4_STATE_NEW = 0,\n\tEXT4_STATE_XATTR = 1,\n\tEXT4_STATE_NO_EXPAND = 2,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 3,\n\tEXT4_STATE_EXT_MIGRATE = 4,\n\tEXT4_STATE_NEWENTRY = 5,\n\tEXT4_STATE_MAY_INLINE_DATA = 6,\n\tEXT4_STATE_EXT_PRECACHED = 7,\n\tEXT4_STATE_LUSTRE_EA_INODE = 8,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 9,\n\tEXT4_STATE_FC_COMMITTING = 10,\n\tEXT4_STATE_FC_FLUSHING_DATA = 11,\n\tEXT4_STATE_ORPHAN_FILE = 12,\n};\n\nenum {\n\tFAN_EVENT_INIT = 0,\n\tFAN_EVENT_REPORTED = 1,\n\tFAN_EVENT_ANSWERED = 2,\n\tFAN_EVENT_CANCELED = 3,\n};\n\nenum {\n\tFATTR4_CLONE_BLKSIZE = 77,\n\tFATTR4_SPACE_FREED = 78,\n\tFATTR4_CHANGE_ATTR_TYPE = 79,\n\tFATTR4_SEC_LABEL = 80,\n};\n\nenum {\n\tFATTR4_DIR_NOTIF_DELAY = 56,\n\tFATTR4_DIRENT_NOTIF_DELAY = 57,\n\tFATTR4_DACL = 58,\n\tFATTR4_SACL = 59,\n\tFATTR4_CHANGE_POLICY = 60,\n\tFATTR4_FS_STATUS = 61,\n\tFATTR4_FS_LAYOUT_TYPES = 62,\n\tFATTR4_LAYOUT_HINT = 63,\n\tFATTR4_LAYOUT_TYPES = 64,\n\tFATTR4_LAYOUT_BLKSIZE = 65,\n\tFATTR4_LAYOUT_ALIGNMENT = 66,\n\tFATTR4_FS_LOCATIONS_INFO = 67,\n\tFATTR4_MDSTHRESHOLD = 68,\n\tFATTR4_RETENTION_GET = 69,\n\tFATTR4_RETENTION_SET = 70,\n\tFATTR4_RETENTEVT_GET = 71,\n\tFATTR4_RETENTEVT_SET = 72,\n\tFATTR4_RETENTION_HOLD = 73,\n\tFATTR4_MODE_SET_MASKED = 74,\n\tFATTR4_SUPPATTR_EXCLCREAT = 75,\n\tFATTR4_FS_CHARSET_CAP = 76,\n};\n\nenum {\n\tFATTR4_MODE_UMASK = 81,\n};\n\nenum {\n\tFATTR4_OPEN_ARGUMENTS = 86,\n};\n\nenum {\n\tFATTR4_SUPPORTED_ATTRS = 0,\n\tFATTR4_TYPE = 1,\n\tFATTR4_FH_EXPIRE_TYPE = 2,\n\tFATTR4_CHANGE = 3,\n\tFATTR4_SIZE = 4,\n\tFATTR4_LINK_SUPPORT = 5,\n\tFATTR4_SYMLINK_SUPPORT = 6,\n\tFATTR4_NAMED_ATTR = 7,\n\tFATTR4_FSID = 8,\n\tFATTR4_UNIQUE_HANDLES = 9,\n\tFATTR4_LEASE_TIME = 10,\n\tFATTR4_RDATTR_ERROR = 11,\n\tFATTR4_ACL = 12,\n\tFATTR4_ACLSUPPORT = 13,\n\tFATTR4_ARCHIVE = 14,\n\tFATTR4_CANSETTIME = 15,\n\tFATTR4_CASE_INSENSITIVE = 16,\n\tFATTR4_CASE_PRESERVING = 17,\n\tFATTR4_CHOWN_RESTRICTED = 18,\n\tFATTR4_FILEHANDLE = 19,\n\tFATTR4_FILEID = 20,\n\tFATTR4_FILES_AVAIL = 21,\n\tFATTR4_FILES_FREE = 22,\n\tFATTR4_FILES_TOTAL = 23,\n\tFATTR4_FS_LOCATIONS = 24,\n\tFATTR4_HIDDEN = 25,\n\tFATTR4_HOMOGENEOUS = 26,\n\tFATTR4_MAXFILESIZE = 27,\n\tFATTR4_MAXLINK = 28,\n\tFATTR4_MAXNAME = 29,\n\tFATTR4_MAXREAD = 30,\n\tFATTR4_MAXWRITE = 31,\n\tFATTR4_MIMETYPE = 32,\n\tFATTR4_MODE = 33,\n\tFATTR4_NO_TRUNC = 34,\n\tFATTR4_NUMLINKS = 35,\n\tFATTR4_OWNER = 36,\n\tFATTR4_OWNER_GROUP = 37,\n\tFATTR4_QUOTA_AVAIL_HARD = 38,\n\tFATTR4_QUOTA_AVAIL_SOFT = 39,\n\tFATTR4_QUOTA_USED = 40,\n\tFATTR4_RAWDEV = 41,\n\tFATTR4_SPACE_AVAIL = 42,\n\tFATTR4_SPACE_FREE = 43,\n\tFATTR4_SPACE_TOTAL = 44,\n\tFATTR4_SPACE_USED = 45,\n\tFATTR4_SYSTEM = 46,\n\tFATTR4_TIME_ACCESS = 47,\n\tFATTR4_TIME_ACCESS_SET = 48,\n\tFATTR4_TIME_BACKUP = 49,\n\tFATTR4_TIME_CREATE = 50,\n\tFATTR4_TIME_DELTA = 51,\n\tFATTR4_TIME_METADATA = 52,\n\tFATTR4_TIME_MODIFY = 53,\n\tFATTR4_TIME_MODIFY_SET = 54,\n\tFATTR4_MOUNTED_ON_FILEID = 55,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_ACCESS = 84,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_MODIFY = 85,\n};\n\nenum {\n\tFATTR4_XATTR_SUPPORT = 82,\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nenum {\n\tFB_GET_WIDTH = 0,\n\tFB_GET_HEIGHT = 4,\n\tFB_INT_STATUS = 8,\n\tFB_INT_ENABLE = 12,\n\tFB_SET_BASE = 16,\n\tFB_SET_ROTATION = 20,\n\tFB_SET_BLANK = 24,\n\tFB_GET_PHYS_WIDTH = 28,\n\tFB_GET_PHYS_HEIGHT = 32,\n\tFB_INT_VSYNC = 1,\n\tFB_INT_BASE_UPDATE_DONE = 2,\n};\n\nenum {\n\tFDB_NOTIFY_BIT = 1,\n\tFDB_NOTIFY_INACTIVE_BIT = 2,\n};\n\nenum {\n\tFIB6_NO_SERNUM_CHANGE = 0,\n};\n\nenum {\n\tFILEID_HIGH_OFF = 0,\n\tFILEID_LOW_OFF = 1,\n\tFILE_I_TYPE_OFF = 2,\n\tEMBED_FH_OFF = 3,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFP_FRE = 0,\n\tFP_FR0 = 1,\n\tFP_FR1 = 2,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFUNC_CAN0_a = 0,\n\tFUNC_CAN0_b = 1,\n\tFUNC_CAN1 = 2,\n\tFUNC_CLKMON = 3,\n\tFUNC_NONE = 4,\n\tFUNC_FAN = 5,\n\tFUNC_FC = 6,\n\tFUNC_FC0_a = 7,\n\tFUNC_FC0_b = 8,\n\tFUNC_FC0_c = 9,\n\tFUNC_FC1_a = 10,\n\tFUNC_FC1_b = 11,\n\tFUNC_FC1_c = 12,\n\tFUNC_FC2_a = 13,\n\tFUNC_FC2_b = 14,\n\tFUNC_FC3_a = 15,\n\tFUNC_FC3_b = 16,\n\tFUNC_FC3_c = 17,\n\tFUNC_FC4_a = 18,\n\tFUNC_FC4_b = 19,\n\tFUNC_FC4_c = 20,\n\tFUNC_FC_SHRD = 21,\n\tFUNC_FC_SHRD0 = 22,\n\tFUNC_FC_SHRD1 = 23,\n\tFUNC_FC_SHRD2 = 24,\n\tFUNC_FC_SHRD3 = 25,\n\tFUNC_FC_SHRD4 = 26,\n\tFUNC_FC_SHRD5 = 27,\n\tFUNC_FC_SHRD6 = 28,\n\tFUNC_FC_SHRD7 = 29,\n\tFUNC_FC_SHRD8 = 30,\n\tFUNC_FC_SHRD9 = 31,\n\tFUNC_FC_SHRD10 = 32,\n\tFUNC_FC_SHRD11 = 33,\n\tFUNC_FC_SHRD12 = 34,\n\tFUNC_FC_SHRD13 = 35,\n\tFUNC_FC_SHRD14 = 36,\n\tFUNC_FC_SHRD15 = 37,\n\tFUNC_FC_SHRD16 = 38,\n\tFUNC_FC_SHRD17 = 39,\n\tFUNC_FC_SHRD18 = 40,\n\tFUNC_FC_SHRD19 = 41,\n\tFUNC_FC_SHRD20 = 42,\n\tFUNC_FUSA = 43,\n\tFUNC_GPIO = 44,\n\tFUNC_I2C = 45,\n\tFUNC_I2C_Sa = 46,\n\tFUNC_IB_TRG_a = 47,\n\tFUNC_IB_TRG_b = 48,\n\tFUNC_IB_TRG_c = 49,\n\tFUNC_IRQ0 = 50,\n\tFUNC_IRQ_IN_a = 51,\n\tFUNC_IRQ_IN_b = 52,\n\tFUNC_IRQ_IN_c = 53,\n\tFUNC_IRQ0_IN = 54,\n\tFUNC_IRQ_OUT_a = 55,\n\tFUNC_IRQ_OUT_b = 56,\n\tFUNC_IRQ_OUT_c = 57,\n\tFUNC_IRQ0_OUT = 58,\n\tFUNC_IRQ1 = 59,\n\tFUNC_IRQ1_IN = 60,\n\tFUNC_IRQ1_OUT = 61,\n\tFUNC_IRQ2 = 62,\n\tFUNC_IRQ3 = 63,\n\tFUNC_IRQ4 = 64,\n\tFUNC_EXT_IRQ = 65,\n\tFUNC_MACLED = 66,\n\tFUNC_MIIM = 67,\n\tFUNC_MIIM_a = 68,\n\tFUNC_MIIM_b = 69,\n\tFUNC_MIIM_c = 70,\n\tFUNC_MIIM_Sa = 71,\n\tFUNC_MIIM_Sb = 72,\n\tFUNC_MIIM_IRQ = 73,\n\tFUNC_OB_TRG = 74,\n\tFUNC_OB_TRG_a = 75,\n\tFUNC_OB_TRG_b = 76,\n\tFUNC_PHY_LED = 77,\n\tFUNC_PHY_DBG = 78,\n\tFUNC_PCI_WAKE = 79,\n\tFUNC_MD = 80,\n\tFUNC_PCIE_PERST = 81,\n\tFUNC_PTP0 = 82,\n\tFUNC_PTP1 = 83,\n\tFUNC_PTP2 = 84,\n\tFUNC_PTP3 = 85,\n\tFUNC_PTPSYNC_0 = 86,\n\tFUNC_PTPSYNC_1 = 87,\n\tFUNC_PTPSYNC_2 = 88,\n\tFUNC_PTPSYNC_3 = 89,\n\tFUNC_PTPSYNC_4 = 90,\n\tFUNC_PTPSYNC_5 = 91,\n\tFUNC_PTPSYNC_6 = 92,\n\tFUNC_PTPSYNC_7 = 93,\n\tFUNC_PWM = 94,\n\tFUNC_PWM_a = 95,\n\tFUNC_PWM_b = 96,\n\tFUNC_QSPI1 = 97,\n\tFUNC_QSPI2 = 98,\n\tFUNC_R = 99,\n\tFUNC_RECO_a = 100,\n\tFUNC_RECO_b = 101,\n\tFUNC_RECO_CLK = 102,\n\tFUNC_SD = 103,\n\tFUNC_SFP = 104,\n\tFUNC_SFP_SD = 105,\n\tFUNC_SG0 = 106,\n\tFUNC_SG1 = 107,\n\tFUNC_SG2 = 108,\n\tFUNC_SPI = 109,\n\tFUNC_SGPIO_a = 110,\n\tFUNC_SGPIO_b = 111,\n\tFUNC_SI = 112,\n\tFUNC_SI2 = 113,\n\tFUNC_SI_Sa = 114,\n\tFUNC_SYNCE = 115,\n\tFUNC_TACHO = 116,\n\tFUNC_TACHO_a = 117,\n\tFUNC_TACHO_b = 118,\n\tFUNC_TWI = 119,\n\tFUNC_TWI2 = 120,\n\tFUNC_TWI3 = 121,\n\tFUNC_TWI_SCL_M = 122,\n\tFUNC_TWI_SLC_GATE = 123,\n\tFUNC_TWI_SLC_GATE_AD = 124,\n\tFUNC_UART = 125,\n\tFUNC_UART2 = 126,\n\tFUNC_UART3 = 127,\n\tFUNC_USB_H_a = 128,\n\tFUNC_USB_H_b = 129,\n\tFUNC_USB_H_c = 130,\n\tFUNC_USB_S_a = 131,\n\tFUNC_USB_S_b = 132,\n\tFUNC_USB_S_c = 133,\n\tFUNC_USB_POWER = 134,\n\tFUNC_USB2PHY_RST = 135,\n\tFUNC_USB_OVER_DETECT = 136,\n\tFUNC_USB_ULPI = 137,\n\tFUNC_PLL_STAT = 138,\n\tFUNC_EMMC = 139,\n\tFUNC_EMMC_SD = 140,\n\tFUNC_REF_CLK = 141,\n\tFUNC_RCVRD_CLK = 142,\n\tFUNC_RGMII = 143,\n\tFUNC_MAX = 144,\n};\n\nenum {\n\tFUSE_I_ADVISE_RDPLUS = 0,\n\tFUSE_I_INIT_RDPLUS = 1,\n\tFUSE_I_SIZE_UNSTABLE = 2,\n\tFUSE_I_BAD = 3,\n\tFUSE_I_BTIME = 4,\n\tFUSE_I_CACHE_IO_MODE = 5,\n\tFUSE_I_EXCLUSIVE = 6,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGPIO_SYSFS_LINE_CHIP_ATTR_DIRECTION = 0,\n\tGPIO_SYSFS_LINE_CHIP_ATTR_VALUE = 1,\n\tGPIO_SYSFS_LINE_CHIP_ATTR_SENTINEL = 2,\n\tGPIO_SYSFS_LINE_CHIP_ATTR_SIZE = 3,\n};\n\nenum {\n\tGPIO_SYSFS_LINE_CLASS_ATTR_DIRECTION = 0,\n\tGPIO_SYSFS_LINE_CLASS_ATTR_VALUE = 1,\n\tGPIO_SYSFS_LINE_CLASS_ATTR_EDGE = 2,\n\tGPIO_SYSFS_LINE_CLASS_ATTR_ACTIVE_LOW = 3,\n\tGPIO_SYSFS_LINE_CLASS_ATTR_SENTINEL = 4,\n\tGPIO_SYSFS_LINE_CLASS_ATTR_SIZE = 5,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tGSSX_NULL = 0,\n\tGSSX_INDICATE_MECHS = 1,\n\tGSSX_GET_CALL_CONTEXT = 2,\n\tGSSX_IMPORT_AND_CANON_NAME = 3,\n\tGSSX_EXPORT_CRED = 4,\n\tGSSX_IMPORT_CRED = 5,\n\tGSSX_ACQUIRE_CRED = 6,\n\tGSSX_STORE_CRED = 7,\n\tGSSX_INIT_SEC_CONTEXT = 8,\n\tGSSX_ACCEPT_SEC_CONTEXT = 9,\n\tGSSX_RELEASE_HANDLE = 10,\n\tGSSX_GET_MIC = 11,\n\tGSSX_VERIFY = 12,\n\tGSSX_WRAP = 13,\n\tGSSX_UNWRAP = 14,\n\tGSSX_WRAP_SIZE_LIMIT = 15,\n};\n\nenum {\n\tHANDSHAKE_A_ACCEPT_SOCKFD = 1,\n\tHANDSHAKE_A_ACCEPT_HANDLER_CLASS = 2,\n\tHANDSHAKE_A_ACCEPT_MESSAGE_TYPE = 3,\n\tHANDSHAKE_A_ACCEPT_TIMEOUT = 4,\n\tHANDSHAKE_A_ACCEPT_AUTH_MODE = 5,\n\tHANDSHAKE_A_ACCEPT_PEER_IDENTITY = 6,\n\tHANDSHAKE_A_ACCEPT_CERTIFICATE = 7,\n\tHANDSHAKE_A_ACCEPT_PEERNAME = 8,\n\tHANDSHAKE_A_ACCEPT_KEYRING = 9,\n\t__HANDSHAKE_A_ACCEPT_MAX = 10,\n\tHANDSHAKE_A_ACCEPT_MAX = 9,\n};\n\nenum {\n\tHANDSHAKE_A_DONE_STATUS = 1,\n\tHANDSHAKE_A_DONE_SOCKFD = 2,\n\tHANDSHAKE_A_DONE_REMOTE_AUTH = 3,\n\t__HANDSHAKE_A_DONE_MAX = 4,\n\tHANDSHAKE_A_DONE_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_A_X509_CERT = 1,\n\tHANDSHAKE_A_X509_PRIVKEY = 2,\n\t__HANDSHAKE_A_X509_MAX = 3,\n\tHANDSHAKE_A_X509_MAX = 2,\n};\n\nenum {\n\tHANDSHAKE_CMD_READY = 1,\n\tHANDSHAKE_CMD_ACCEPT = 2,\n\tHANDSHAKE_CMD_DONE = 3,\n\t__HANDSHAKE_CMD_MAX = 4,\n\tHANDSHAKE_CMD_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_NLGRP_NONE = 0,\n\tHANDSHAKE_NLGRP_TLSHD = 1,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tICQ_EXITED = 4,\n\tICQ_DESTROYED = 8,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIEEE754_CLASS_NORM = 0,\n\tIEEE754_CLASS_ZERO = 1,\n\tIEEE754_CLASS_DNORM = 2,\n\tIEEE754_CLASS_INF = 3,\n\tIEEE754_CLASS_SNAN = 4,\n\tIEEE754_CLASS_QNAN = 5,\n};\n\nenum {\n\tIFAL_ADDRESS = 1,\n\tIFAL_LABEL = 2,\n\t__IFAL_MAX = 3,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRIDGE_VLAN_TUNNEL_UNSPEC = 0,\n\tIFLA_BRIDGE_VLAN_TUNNEL_ID = 1,\n\tIFLA_BRIDGE_VLAN_TUNNEL_VID = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_FLAGS = 3,\n\t__IFLA_BRIDGE_VLAN_TUNNEL_MAX = 4,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_BR_UNSPEC = 0,\n\tIFLA_BR_FORWARD_DELAY = 1,\n\tIFLA_BR_HELLO_TIME = 2,\n\tIFLA_BR_MAX_AGE = 3,\n\tIFLA_BR_AGEING_TIME = 4,\n\tIFLA_BR_STP_STATE = 5,\n\tIFLA_BR_PRIORITY = 6,\n\tIFLA_BR_VLAN_FILTERING = 7,\n\tIFLA_BR_VLAN_PROTOCOL = 8,\n\tIFLA_BR_GROUP_FWD_MASK = 9,\n\tIFLA_BR_ROOT_ID = 10,\n\tIFLA_BR_BRIDGE_ID = 11,\n\tIFLA_BR_ROOT_PORT = 12,\n\tIFLA_BR_ROOT_PATH_COST = 13,\n\tIFLA_BR_TOPOLOGY_CHANGE = 14,\n\tIFLA_BR_TOPOLOGY_CHANGE_DETECTED = 15,\n\tIFLA_BR_HELLO_TIMER = 16,\n\tIFLA_BR_TCN_TIMER = 17,\n\tIFLA_BR_TOPOLOGY_CHANGE_TIMER = 18,\n\tIFLA_BR_GC_TIMER = 19,\n\tIFLA_BR_GROUP_ADDR = 20,\n\tIFLA_BR_FDB_FLUSH = 21,\n\tIFLA_BR_MCAST_ROUTER = 22,\n\tIFLA_BR_MCAST_SNOOPING = 23,\n\tIFLA_BR_MCAST_QUERY_USE_IFADDR = 24,\n\tIFLA_BR_MCAST_QUERIER = 25,\n\tIFLA_BR_MCAST_HASH_ELASTICITY = 26,\n\tIFLA_BR_MCAST_HASH_MAX = 27,\n\tIFLA_BR_MCAST_LAST_MEMBER_CNT = 28,\n\tIFLA_BR_MCAST_STARTUP_QUERY_CNT = 29,\n\tIFLA_BR_MCAST_LAST_MEMBER_INTVL = 30,\n\tIFLA_BR_MCAST_MEMBERSHIP_INTVL = 31,\n\tIFLA_BR_MCAST_QUERIER_INTVL = 32,\n\tIFLA_BR_MCAST_QUERY_INTVL = 33,\n\tIFLA_BR_MCAST_QUERY_RESPONSE_INTVL = 34,\n\tIFLA_BR_MCAST_STARTUP_QUERY_INTVL = 35,\n\tIFLA_BR_NF_CALL_IPTABLES = 36,\n\tIFLA_BR_NF_CALL_IP6TABLES = 37,\n\tIFLA_BR_NF_CALL_ARPTABLES = 38,\n\tIFLA_BR_VLAN_DEFAULT_PVID = 39,\n\tIFLA_BR_PAD = 40,\n\tIFLA_BR_VLAN_STATS_ENABLED = 41,\n\tIFLA_BR_MCAST_STATS_ENABLED = 42,\n\tIFLA_BR_MCAST_IGMP_VERSION = 43,\n\tIFLA_BR_MCAST_MLD_VERSION = 44,\n\tIFLA_BR_VLAN_STATS_PER_PORT = 45,\n\tIFLA_BR_MULTI_BOOLOPT = 46,\n\tIFLA_BR_MCAST_QUERIER_STATE = 47,\n\tIFLA_BR_FDB_N_LEARNED = 48,\n\tIFLA_BR_FDB_MAX_LEARNED = 49,\n\t__IFLA_BR_MAX = 50,\n};\n\nenum {\n\tIFLA_DSA_UNSPEC = 0,\n\tIFLA_DSA_CONDUIT = 1,\n\tIFLA_DSA_MASTER = 1,\n\t__IFLA_DSA_MAX = 2,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET6_UNSPEC = 0,\n\tIFLA_INET6_FLAGS = 1,\n\tIFLA_INET6_CONF = 2,\n\tIFLA_INET6_STATS = 3,\n\tIFLA_INET6_MCAST = 4,\n\tIFLA_INET6_CACHEINFO = 5,\n\tIFLA_INET6_ICMP6STATS = 6,\n\tIFLA_INET6_TOKEN = 7,\n\tIFLA_INET6_ADDR_GEN_MODE = 8,\n\tIFLA_INET6_RA_MTU = 9,\n\t__IFLA_INET6_MAX = 10,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tINET6_IFADDR_STATE_PREDAD = 0,\n\tINET6_IFADDR_STATE_DAD = 1,\n\tINET6_IFADDR_STATE_POSTDAD = 2,\n\tINET6_IFADDR_STATE_ERRDAD = 3,\n\tINET6_IFADDR_STATE_DEAD = 4,\n};\n\nenum {\n\tINET_DIAG_BC_NOP = 0,\n\tINET_DIAG_BC_JMP = 1,\n\tINET_DIAG_BC_S_GE = 2,\n\tINET_DIAG_BC_S_LE = 3,\n\tINET_DIAG_BC_D_GE = 4,\n\tINET_DIAG_BC_D_LE = 5,\n\tINET_DIAG_BC_AUTO = 6,\n\tINET_DIAG_BC_S_COND = 7,\n\tINET_DIAG_BC_D_COND = 8,\n\tINET_DIAG_BC_DEV_COND = 9,\n\tINET_DIAG_BC_MARK_COND = 10,\n\tINET_DIAG_BC_S_EQ = 11,\n\tINET_DIAG_BC_D_EQ = 12,\n\tINET_DIAG_BC_CGROUP_COND = 13,\n};\n\nenum {\n\tINET_DIAG_NONE = 0,\n\tINET_DIAG_MEMINFO = 1,\n\tINET_DIAG_INFO = 2,\n\tINET_DIAG_VEGASINFO = 3,\n\tINET_DIAG_CONG = 4,\n\tINET_DIAG_TOS = 5,\n\tINET_DIAG_TCLASS = 6,\n\tINET_DIAG_SKMEMINFO = 7,\n\tINET_DIAG_SHUTDOWN = 8,\n\tINET_DIAG_DCTCPINFO = 9,\n\tINET_DIAG_PROTOCOL = 10,\n\tINET_DIAG_SKV6ONLY = 11,\n\tINET_DIAG_LOCALS = 12,\n\tINET_DIAG_PEERS = 13,\n\tINET_DIAG_PAD = 14,\n\tINET_DIAG_MARK = 15,\n\tINET_DIAG_BBRINFO = 16,\n\tINET_DIAG_CLASS_ID = 17,\n\tINET_DIAG_MD5SIG = 18,\n\tINET_DIAG_ULP_INFO = 19,\n\tINET_DIAG_SK_BPF_STORAGES = 20,\n\tINET_DIAG_CGROUP_ID = 21,\n\tINET_DIAG_SOCKOPT = 22,\n\t__INET_DIAG_MAX = 23,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINET_ULP_INFO_UNSPEC = 0,\n\tINET_ULP_INFO_NAME = 1,\n\tINET_ULP_INFO_TLS = 2,\n\tINET_ULP_INFO_MPTCP = 3,\n\t__INET_ULP_INFO_MAX = 4,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINTEL_DSM_FNS = 0,\n\tINTEL_DSM_V18_SWITCH = 3,\n\tINTEL_DSM_V33_SWITCH = 4,\n\tINTEL_DSM_DRV_STRENGTH = 9,\n\tINTEL_DSM_D3_RETUNE = 10,\n};\n\nenum {\n\tIOAM6_ATTR_UNSPEC = 0,\n\tIOAM6_ATTR_NS_ID = 1,\n\tIOAM6_ATTR_NS_DATA = 2,\n\tIOAM6_ATTR_NS_DATA_WIDE = 3,\n\tIOAM6_ATTR_SC_ID = 4,\n\tIOAM6_ATTR_SC_DATA = 5,\n\tIOAM6_ATTR_SC_NONE = 6,\n\tIOAM6_ATTR_PAD = 7,\n\t__IOAM6_ATTR_MAX = 8,\n};\n\nenum {\n\tIOAM6_CMD_UNSPEC = 0,\n\tIOAM6_CMD_ADD_NAMESPACE = 1,\n\tIOAM6_CMD_DEL_NAMESPACE = 2,\n\tIOAM6_CMD_DUMP_NAMESPACES = 3,\n\tIOAM6_CMD_ADD_SCHEMA = 4,\n\tIOAM6_CMD_DEL_SCHEMA = 5,\n\tIOAM6_CMD_DUMP_SCHEMAS = 6,\n\tIOAM6_CMD_NS_SET_SCHEMA = 7,\n\t__IOAM6_CMD_MAX = 8,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIPV6_SADDR_RULE_INIT = 0,\n\tIPV6_SADDR_RULE_LOCAL = 1,\n\tIPV6_SADDR_RULE_SCOPE = 2,\n\tIPV6_SADDR_RULE_PREFERRED = 3,\n\tIPV6_SADDR_RULE_OIF = 4,\n\tIPV6_SADDR_RULE_LABEL = 5,\n\tIPV6_SADDR_RULE_PRIVACY = 6,\n\tIPV6_SADDR_RULE_ORCHID = 7,\n\tIPV6_SADDR_RULE_PREFIX = 8,\n\tIPV6_SADDR_RULE_MAX = 9,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tIS1_ACTION_TYPE_NORMAL = 0,\n\tIS1_ACTION_TYPE_MAX = 1,\n};\n\nenum {\n\tIS2_ACTION_TYPE_NORMAL = 0,\n\tIS2_ACTION_TYPE_SMAC_SIP = 1,\n\tIS2_ACTION_TYPE_MAX = 2,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = -1,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_FUA = 512,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_NCQ_SEND_RECV = 2048,\n\tATA_DFLAG_NCQ_PRIO = 4096,\n\tATA_DFLAG_CDL = 8192,\n\tATA_DFLAG_CFG_MASK = 16383,\n\tATA_DFLAG_PIO = 16384,\n\tATA_DFLAG_NCQ_OFF = 32768,\n\tATA_DFLAG_SLEEPING = 65536,\n\tATA_DFLAG_DUBIOUS_XFER = 131072,\n\tATA_DFLAG_NO_UNLOAD = 262144,\n\tATA_DFLAG_UNLOCK_HPA = 524288,\n\tATA_DFLAG_INIT_MASK = 1048575,\n\tATA_DFLAG_NCQ_PRIO_ENABLED = 1048576,\n\tATA_DFLAG_CDL_ENABLED = 2097152,\n\tATA_DFLAG_RESUMING = 4194304,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_FEATURES_MASK = 201341696,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DEBOUNCE_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_RESUMING = 65536,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_RTF_FILLED = 4,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_HAS_CDL = 256,\n\tATA_QCFLAG_EH = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_QCFLAG_EH_SUCCESS_CMD = 524288,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_HOST_NO_PART = 16,\n\tATA_HOST_NO_SSC = 32,\n\tATA_HOST_NO_DEVSLP = 64,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 10000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_GET_SUCCESS_SENSE = 64,\n\tATA_EH_SET_ACTIVE = 128,\n\tATA_EH_PERDEV_MASK = 225,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_PRINT_QUIRKS = 2097152,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum {\n\tLINK_CAPA_10HD = 0,\n\tLINK_CAPA_10FD = 1,\n\tLINK_CAPA_100HD = 2,\n\tLINK_CAPA_100FD = 3,\n\tLINK_CAPA_1000HD = 4,\n\tLINK_CAPA_1000FD = 5,\n\tLINK_CAPA_2500FD = 6,\n\tLINK_CAPA_5000FD = 7,\n\tLINK_CAPA_10000FD = 8,\n\tLINK_CAPA_20000FD = 9,\n\tLINK_CAPA_25000FD = 10,\n\tLINK_CAPA_40000FD = 11,\n\tLINK_CAPA_50000FD = 12,\n\tLINK_CAPA_56000FD = 13,\n\tLINK_CAPA_80000FD = 14,\n\tLINK_CAPA_100000FD = 15,\n\tLINK_CAPA_200000FD = 16,\n\tLINK_CAPA_400000FD = 17,\n\tLINK_CAPA_800000FD = 18,\n\tLINK_CAPA_1600000FD = 19,\n\t__LINK_CAPA_MAX = 20,\n};\n\nenum {\n\tLINK_XSTATS_TYPE_UNSPEC = 0,\n\tLINK_XSTATS_TYPE_BRIDGE = 1,\n\tLINK_XSTATS_TYPE_BOND = 2,\n\t__LINK_XSTATS_TYPE_MAX = 3,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLK_STATE_IN_USE = 0,\n\tNFS_DELEGATED_STATE = 1,\n\tNFS_OPEN_STATE = 2,\n\tNFS_O_RDONLY_STATE = 3,\n\tNFS_O_WRONLY_STATE = 4,\n\tNFS_O_RDWR_STATE = 5,\n\tNFS_STATE_RECLAIM_REBOOT = 6,\n\tNFS_STATE_RECLAIM_NOGRACE = 7,\n\tNFS_STATE_POSIX_LOCKS = 8,\n\tNFS_STATE_RECOVERY_FAILED = 9,\n\tNFS_STATE_MAY_NOTIFY_LOCK = 10,\n\tNFS_STATE_CHANGE_WAIT = 11,\n\tNFS_CLNT_DST_SSC_COPY_STATE = 12,\n\tNFS_CLNT_SRC_SSC_COPY_STATE = 13,\n\tNFS_SRV_SSC_COPY_STATE = 14,\n};\n\nenum {\n\tLOCKD_A_SERVER_GRACETIME = 1,\n\tLOCKD_A_SERVER_TCP_PORT = 2,\n\tLOCKD_A_SERVER_UDP_PORT = 3,\n\t__LOCKD_A_SERVER_MAX = 4,\n\tLOCKD_A_SERVER_MAX = 3,\n};\n\nenum {\n\tLOCKD_CMD_SERVER_SET = 1,\n\tLOCKD_CMD_SERVER_GET = 2,\n\t__LOCKD_CMD_MAX = 3,\n\tLOCKD_CMD_MAX = 2,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n\tLo_deleting = 3,\n};\n\nenum {\n\tMAGNITUDE_STRONG = 2,\n\tMAGNITUDE_WEAK = 3,\n\tMAGNITUDE_NUM = 4,\n};\n\nenum {\n\tMAX_BUFFERS_PER_COMMAND = 336,\n\tMAX_SIGNALLED_PIPES = 64,\n\tINITIAL_PIPES_CAPACITY = 64,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMBE_REFERENCED_B = 0,\n\tMBE_REUSABLE_B = 1,\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_MDB_EATTR_UNSPEC = 0,\n\tMDBA_MDB_EATTR_TIMER = 1,\n\tMDBA_MDB_EATTR_SRC_LIST = 2,\n\tMDBA_MDB_EATTR_GROUP_MODE = 3,\n\tMDBA_MDB_EATTR_SOURCE = 4,\n\tMDBA_MDB_EATTR_RTPROT = 5,\n\tMDBA_MDB_EATTR_DST = 6,\n\tMDBA_MDB_EATTR_DST_PORT = 7,\n\tMDBA_MDB_EATTR_VNI = 8,\n\tMDBA_MDB_EATTR_IFINDEX = 9,\n\tMDBA_MDB_EATTR_SRC_VNI = 10,\n\t__MDBA_MDB_EATTR_MAX = 11,\n};\n\nenum {\n\tMDBA_MDB_ENTRY_UNSPEC = 0,\n\tMDBA_MDB_ENTRY_INFO = 1,\n\t__MDBA_MDB_ENTRY_MAX = 2,\n};\n\nenum {\n\tMDBA_MDB_SRCATTR_UNSPEC = 0,\n\tMDBA_MDB_SRCATTR_ADDRESS = 1,\n\tMDBA_MDB_SRCATTR_TIMER = 2,\n\t__MDBA_MDB_SRCATTR_MAX = 3,\n};\n\nenum {\n\tMDBA_MDB_SRCLIST_UNSPEC = 0,\n\tMDBA_MDB_SRCLIST_ENTRY = 1,\n\t__MDBA_MDB_SRCLIST_MAX = 2,\n};\n\nenum {\n\tMDBA_MDB_UNSPEC = 0,\n\tMDBA_MDB_ENTRY = 1,\n\t__MDBA_MDB_MAX = 2,\n};\n\nenum {\n\tMDBA_ROUTER_PATTR_UNSPEC = 0,\n\tMDBA_ROUTER_PATTR_TIMER = 1,\n\tMDBA_ROUTER_PATTR_TYPE = 2,\n\tMDBA_ROUTER_PATTR_INET_TIMER = 3,\n\tMDBA_ROUTER_PATTR_INET6_TIMER = 4,\n\tMDBA_ROUTER_PATTR_VID = 5,\n\t__MDBA_ROUTER_PATTR_MAX = 6,\n};\n\nenum {\n\tMDBA_ROUTER_UNSPEC = 0,\n\tMDBA_ROUTER_PORT = 1,\n\t__MDBA_ROUTER_MAX = 2,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_UNSPEC = 0,\n\tMDBA_MDB = 1,\n\tMDBA_ROUTER = 2,\n\t__MDBA_MAX = 3,\n};\n\nenum {\n\tMDBE_ATTR_UNSPEC = 0,\n\tMDBE_ATTR_SOURCE = 1,\n\tMDBE_ATTR_SRC_LIST = 2,\n\tMDBE_ATTR_GROUP_MODE = 3,\n\tMDBE_ATTR_RTPROT = 4,\n\tMDBE_ATTR_DST = 5,\n\tMDBE_ATTR_DST_PORT = 6,\n\tMDBE_ATTR_VNI = 7,\n\tMDBE_ATTR_IFINDEX = 8,\n\tMDBE_ATTR_SRC_VNI = 9,\n\tMDBE_ATTR_STATE_MASK = 10,\n\t__MDBE_ATTR_MAX = 11,\n};\n\nenum {\n\tMDBE_SRCATTR_UNSPEC = 0,\n\tMDBE_SRCATTR_ADDRESS = 1,\n\t__MDBE_SRCATTR_MAX = 2,\n};\n\nenum {\n\tMDBE_SRC_LIST_UNSPEC = 0,\n\tMDBE_SRC_LIST_ENTRY = 1,\n\t__MDBE_SRC_LIST_MAX = 2,\n};\n\nenum {\n\tMDB_RTR_TYPE_DISABLED = 0,\n\tMDB_RTR_TYPE_TEMP_QUERY = 1,\n\tMDB_RTR_TYPE_PERM = 2,\n\tMDB_RTR_TYPE_TEMP = 3,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMICRON_ON_DIE_UNSUPPORTED = 0,\n\tMICRON_ON_DIE_SUPPORTED = 1,\n\tMICRON_ON_DIE_MANDATORY = 2,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMLO_PAUSE_NONE = 0,\n\tMLO_PAUSE_RX = 1,\n\tMLO_PAUSE_TX = 2,\n\tMLO_PAUSE_TXRX_MASK = 3,\n\tMLO_PAUSE_AN = 4,\n\tMLO_AN_PHY = 0,\n\tMLO_AN_FIXED = 1,\n\tMLO_AN_INBAND = 2,\n\tPHYLINK_PCS_NEG_NONE = 0,\n\tPHYLINK_PCS_NEG_ENABLED = 16,\n\tPHYLINK_PCS_NEG_OUTBAND = 32,\n\tPHYLINK_PCS_NEG_INBAND = 64,\n\tPHYLINK_PCS_NEG_INBAND_DISABLED = 64,\n\tPHYLINK_PCS_NEG_INBAND_ENABLED = 80,\n\tMAC_SYM_PAUSE = 1,\n\tMAC_ASYM_PAUSE = 2,\n\tMAC_10HD = 4,\n\tMAC_10FD = 8,\n\tMAC_10 = 12,\n\tMAC_100HD = 16,\n\tMAC_100FD = 32,\n\tMAC_100 = 48,\n\tMAC_1000HD = 64,\n\tMAC_1000FD = 128,\n\tMAC_1000 = 192,\n\tMAC_2500FD = 256,\n\tMAC_5000FD = 512,\n\tMAC_10000FD = 1024,\n\tMAC_20000FD = 2048,\n\tMAC_25000FD = 4096,\n\tMAC_40000FD = 8192,\n\tMAC_50000FD = 16384,\n\tMAC_56000FD = 32768,\n\tMAC_80000FD = 65536,\n\tMAC_100000FD = 131072,\n\tMAC_200000FD = 262144,\n\tMAC_400000FD = 524288,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMOUNTPROC3_NULL = 0,\n\tMOUNTPROC3_MNT = 1,\n\tMOUNTPROC3_DUMP = 2,\n\tMOUNTPROC3_UMNT = 3,\n\tMOUNTPROC3_UMNTALL = 4,\n\tMOUNTPROC3_EXPORT = 5,\n};\n\nenum {\n\tMOUNTPROC_NULL = 0,\n\tMOUNTPROC_MNT = 1,\n\tMOUNTPROC_DUMP = 2,\n\tMOUNTPROC_UMNT = 3,\n\tMOUNTPROC_UMNTALL = 4,\n\tMOUNTPROC_EXPORT = 5,\n};\n\nenum {\n\tMOVE_CANCEL_RACE = 1,\n\tMOVE_SOURCE_RD_ERR = 2,\n\tMOVE_TARGET_RD_ERR = 3,\n\tMOVE_TARGET_WR_ERR = 4,\n\tMOVE_TARGET_BITFLIPS = 5,\n\tMOVE_RETRY = 6,\n};\n\nenum {\n\tMOXA_SUPP_RS232 = 1,\n\tMOXA_SUPP_RS422 = 2,\n\tMOXA_SUPP_RS485 = 4,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tMTD_OPS_PLACE_OOB = 0,\n\tMTD_OPS_AUTO_OOB = 1,\n\tMTD_OPS_RAW = 2,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNDUSEROPT_UNSPEC = 0,\n\tNDUSEROPT_SRCADDR = 1,\n\t__NDUSEROPT_MAX = 2,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFEA_UNSPEC = 0,\n\tNFEA_ACTIVITY_NOTIFY = 1,\n\tNFEA_DONT_REFRESH = 2,\n\t__NFEA_MAX = 3,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNFSPROC4_CLNT_NULL = 0,\n\tNFSPROC4_CLNT_READ = 1,\n\tNFSPROC4_CLNT_WRITE = 2,\n\tNFSPROC4_CLNT_COMMIT = 3,\n\tNFSPROC4_CLNT_OPEN = 4,\n\tNFSPROC4_CLNT_OPEN_CONFIRM = 5,\n\tNFSPROC4_CLNT_OPEN_NOATTR = 6,\n\tNFSPROC4_CLNT_OPEN_DOWNGRADE = 7,\n\tNFSPROC4_CLNT_CLOSE = 8,\n\tNFSPROC4_CLNT_SETATTR = 9,\n\tNFSPROC4_CLNT_FSINFO = 10,\n\tNFSPROC4_CLNT_RENEW = 11,\n\tNFSPROC4_CLNT_SETCLIENTID = 12,\n\tNFSPROC4_CLNT_SETCLIENTID_CONFIRM = 13,\n\tNFSPROC4_CLNT_LOCK = 14,\n\tNFSPROC4_CLNT_LOCKT = 15,\n\tNFSPROC4_CLNT_LOCKU = 16,\n\tNFSPROC4_CLNT_ACCESS = 17,\n\tNFSPROC4_CLNT_GETATTR = 18,\n\tNFSPROC4_CLNT_LOOKUP = 19,\n\tNFSPROC4_CLNT_LOOKUP_ROOT = 20,\n\tNFSPROC4_CLNT_REMOVE = 21,\n\tNFSPROC4_CLNT_RENAME = 22,\n\tNFSPROC4_CLNT_LINK = 23,\n\tNFSPROC4_CLNT_SYMLINK = 24,\n\tNFSPROC4_CLNT_CREATE = 25,\n\tNFSPROC4_CLNT_PATHCONF = 26,\n\tNFSPROC4_CLNT_STATFS = 27,\n\tNFSPROC4_CLNT_READLINK = 28,\n\tNFSPROC4_CLNT_READDIR = 29,\n\tNFSPROC4_CLNT_SERVER_CAPS = 30,\n\tNFSPROC4_CLNT_DELEGRETURN = 31,\n\tNFSPROC4_CLNT_GETACL = 32,\n\tNFSPROC4_CLNT_SETACL = 33,\n\tNFSPROC4_CLNT_FS_LOCATIONS = 34,\n\tNFSPROC4_CLNT_RELEASE_LOCKOWNER = 35,\n\tNFSPROC4_CLNT_SECINFO = 36,\n\tNFSPROC4_CLNT_FSID_PRESENT = 37,\n\tNFSPROC4_CLNT_EXCHANGE_ID = 38,\n\tNFSPROC4_CLNT_CREATE_SESSION = 39,\n\tNFSPROC4_CLNT_DESTROY_SESSION = 40,\n\tNFSPROC4_CLNT_SEQUENCE = 41,\n\tNFSPROC4_CLNT_GET_LEASE_TIME = 42,\n\tNFSPROC4_CLNT_RECLAIM_COMPLETE = 43,\n\tNFSPROC4_CLNT_LAYOUTGET = 44,\n\tNFSPROC4_CLNT_GETDEVICEINFO = 45,\n\tNFSPROC4_CLNT_LAYOUTCOMMIT = 46,\n\tNFSPROC4_CLNT_LAYOUTRETURN = 47,\n\tNFSPROC4_CLNT_SECINFO_NO_NAME = 48,\n\tNFSPROC4_CLNT_TEST_STATEID = 49,\n\tNFSPROC4_CLNT_FREE_STATEID = 50,\n\tNFSPROC4_CLNT_GETDEVICELIST = 51,\n\tNFSPROC4_CLNT_BIND_CONN_TO_SESSION = 52,\n\tNFSPROC4_CLNT_DESTROY_CLIENTID = 53,\n\tNFSPROC4_CLNT_SEEK = 54,\n\tNFSPROC4_CLNT_ALLOCATE = 55,\n\tNFSPROC4_CLNT_DEALLOCATE = 56,\n\tNFSPROC4_CLNT_ZERO_RANGE = 57,\n\tNFSPROC4_CLNT_LAYOUTSTATS = 58,\n\tNFSPROC4_CLNT_CLONE = 59,\n\tNFSPROC4_CLNT_COPY = 60,\n\tNFSPROC4_CLNT_OFFLOAD_CANCEL = 61,\n\tNFSPROC4_CLNT_LOOKUPP = 62,\n\tNFSPROC4_CLNT_LAYOUTERROR = 63,\n\tNFSPROC4_CLNT_COPY_NOTIFY = 64,\n\tNFSPROC4_CLNT_GETXATTR = 65,\n\tNFSPROC4_CLNT_SETXATTR = 66,\n\tNFSPROC4_CLNT_LISTXATTRS = 67,\n\tNFSPROC4_CLNT_REMOVEXATTR = 68,\n\tNFSPROC4_CLNT_READ_PLUS = 69,\n\tNFSPROC4_CLNT_OFFLOAD_STATUS = 70,\n};\n\nenum {\n\tNFS_DELEGATION_NEED_RECLAIM = 0,\n\tNFS_DELEGATION_RETURN_IF_CLOSED = 1,\n\tNFS_DELEGATION_REFERENCED = 2,\n\tNFS_DELEGATION_RETURNING = 3,\n\tNFS_DELEGATION_REVOKED = 4,\n\tNFS_DELEGATION_TEST_EXPIRED = 5,\n\tNFS_DELEGATION_DELEGTIME = 6,\n};\n\nenum {\n\tNFS_DEVICEID_INVALID = 0,\n\tNFS_DEVICEID_UNAVAILABLE = 1,\n\tNFS_DEVICEID_NOCACHE = 2,\n};\n\nenum {\n\tNFS_IOHDR_ERROR = 0,\n\tNFS_IOHDR_EOF = 1,\n\tNFS_IOHDR_REDO = 2,\n\tNFS_IOHDR_STAT = 3,\n\tNFS_IOHDR_RESEND_PNFS = 4,\n\tNFS_IOHDR_RESEND_MDS = 5,\n\tNFS_IOHDR_UNSTABLE_WRITES = 6,\n\tNFS_IOHDR_ODIRECT = 7,\n};\n\nenum {\n\tNFS_LAYOUT_RO_FAILED = 0,\n\tNFS_LAYOUT_RW_FAILED = 1,\n\tNFS_LAYOUT_BULK_RECALL = 2,\n\tNFS_LAYOUT_RETURN = 3,\n\tNFS_LAYOUT_RETURN_LOCK = 4,\n\tNFS_LAYOUT_RETURN_REQUESTED = 5,\n\tNFS_LAYOUT_INVALID_STID = 6,\n\tNFS_LAYOUT_FIRST_LAYOUTGET = 7,\n\tNFS_LAYOUT_INODE_FREEING = 8,\n\tNFS_LAYOUT_HASHED = 9,\n\tNFS_LAYOUT_DRAIN = 10,\n};\n\nenum {\n\tNFS_LSEG_VALID = 0,\n\tNFS_LSEG_ROC = 1,\n\tNFS_LSEG_LAYOUTCOMMIT = 2,\n\tNFS_LSEG_LAYOUTRETURN = 3,\n\tNFS_LSEG_UNAVAILABLE = 4,\n};\n\nenum {\n\tNFS_OWNER_RECLAIM_REBOOT = 0,\n\tNFS_OWNER_RECLAIM_NOGRACE = 1,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNLM_LCK_GRANTED = 0,\n\tNLM_LCK_DENIED = 1,\n\tNLM_LCK_DENIED_NOLOCKS = 2,\n\tNLM_LCK_BLOCKED = 3,\n\tNLM_LCK_DENIED_GRACE_PERIOD = 4,\n\tNLM_DEADLCK = 5,\n\tNLM_ROFS = 6,\n\tNLM_STALE_FH = 7,\n\tNLM_FBIG = 8,\n\tNLM_FAILED = 9,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNSMPROC_NULL = 0,\n\tNSMPROC_STAT = 1,\n\tNSMPROC_MON = 2,\n\tNSMPROC_UNMON = 3,\n\tNSMPROC_UNMON_ALL = 4,\n\tNSMPROC_SIMU_CRASH = 5,\n\tNSMPROC_NOTIFY = 6,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 16,\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n\tNVMEM_LAYOUT_ADD = 5,\n\tNVMEM_LAYOUT_REMOVE = 6,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tOPT_SOURCE = 0,\n\tOPT_SUBTYPE = 1,\n\tOPT_FD = 2,\n\tOPT_ROOTMODE = 3,\n\tOPT_USER_ID = 4,\n\tOPT_GROUP_ID = 5,\n\tOPT_DEFAULT_PERMISSIONS = 6,\n\tOPT_ALLOW_OTHER = 7,\n\tOPT_MAX_READ = 8,\n\tOPT_BLKSIZE = 9,\n\tOPT_ERR = 10,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOVL_REDIRECT_OFF = 0,\n\tOVL_REDIRECT_FOLLOW = 1,\n\tOVL_REDIRECT_NOFOLLOW = 2,\n\tOVL_REDIRECT_ON = 3,\n};\n\nenum {\n\tOVL_UUID_OFF = 0,\n\tOVL_UUID_NULL = 1,\n\tOVL_UUID_AUTO = 2,\n\tOVL_UUID_ON = 3,\n};\n\nenum {\n\tOVL_VERITY_OFF = 0,\n\tOVL_VERITY_ON = 1,\n\tOVL_VERITY_REQUIRE = 2,\n};\n\nenum {\n\tOVL_XINO_OFF = 0,\n\tOVL_XINO_AUTO = 1,\n\tOVL_XINO_ON = 2,\n};\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid = 2,\n\tOpt_nogrpid = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb = 6,\n\tOpt_nouid32 = 7,\n\tOpt_debug = 8,\n\tOpt_removed = 9,\n\tOpt_user_xattr = 10,\n\tOpt_acl = 11,\n\tOpt_auto_da_alloc = 12,\n\tOpt_noauto_da_alloc = 13,\n\tOpt_noload = 14,\n\tOpt_commit = 15,\n\tOpt_min_batch_time = 16,\n\tOpt_max_batch_time = 17,\n\tOpt_journal_dev = 18,\n\tOpt_journal_path = 19,\n\tOpt_journal_checksum = 20,\n\tOpt_journal_async_commit = 21,\n\tOpt_abort = 22,\n\tOpt_data_journal = 23,\n\tOpt_data_ordered = 24,\n\tOpt_data_writeback = 25,\n\tOpt_data_err_abort = 26,\n\tOpt_data_err_ignore = 27,\n\tOpt_test_dummy_encryption = 28,\n\tOpt_inlinecrypt = 29,\n\tOpt_usrjquota = 30,\n\tOpt_grpjquota = 31,\n\tOpt_quota = 32,\n\tOpt_noquota = 33,\n\tOpt_barrier = 34,\n\tOpt_nobarrier = 35,\n\tOpt_err = 36,\n\tOpt_usrquota = 37,\n\tOpt_grpquota = 38,\n\tOpt_prjquota = 39,\n\tOpt_dax = 40,\n\tOpt_dax_always = 41,\n\tOpt_dax_inode = 42,\n\tOpt_dax_never = 43,\n\tOpt_stripe = 44,\n\tOpt_delalloc = 45,\n\tOpt_nodelalloc = 46,\n\tOpt_warn_on_error = 47,\n\tOpt_nowarn_on_error = 48,\n\tOpt_mblk_io_submit = 49,\n\tOpt_debug_want_extra_isize = 50,\n\tOpt_nomblk_io_submit = 51,\n\tOpt_block_validity = 52,\n\tOpt_noblock_validity = 53,\n\tOpt_inode_readahead_blks = 54,\n\tOpt_journal_ioprio = 55,\n\tOpt_dioread_nolock = 56,\n\tOpt_dioread_lock = 57,\n\tOpt_discard = 58,\n\tOpt_nodiscard = 59,\n\tOpt_init_itable = 60,\n\tOpt_noinit_itable = 61,\n\tOpt_max_dir_size_kb = 62,\n\tOpt_nojournal_checksum = 63,\n\tOpt_nombcache = 64,\n\tOpt_no_prefetch_block_bitmaps = 65,\n\tOpt_mb_optimize_scan = 66,\n\tOpt_errors = 67,\n\tOpt_data = 68,\n\tOpt_data_err = 69,\n\tOpt_jqfmt = 70,\n\tOpt_dax_type = 71,\n};\n\nenum {\n\tOpt_check = 0,\n\tOpt_uid = 1,\n\tOpt_gid = 2,\n\tOpt_umask = 3,\n\tOpt_dmask = 4,\n\tOpt_fmask = 5,\n\tOpt_allow_utime = 6,\n\tOpt_codepage = 7,\n\tOpt_usefree = 8,\n\tOpt_nocase = 9,\n\tOpt_quiet = 10,\n\tOpt_showexec = 11,\n\tOpt_debug___2 = 12,\n\tOpt_immutable = 13,\n\tOpt_dots = 14,\n\tOpt_dotsOK = 15,\n\tOpt_charset = 16,\n\tOpt_shortname = 17,\n\tOpt_utf8 = 18,\n\tOpt_utf8_bool = 19,\n\tOpt_uni_xl = 20,\n\tOpt_uni_xl_bool = 21,\n\tOpt_nonumtail = 22,\n\tOpt_nonumtail_bool = 23,\n\tOpt_obsolete = 24,\n\tOpt_flush = 25,\n\tOpt_tz = 26,\n\tOpt_rodir = 27,\n\tOpt_errors___2 = 28,\n\tOpt_discard___2 = 29,\n\tOpt_nfs = 30,\n\tOpt_nfs_enum = 31,\n\tOpt_time_offset = 32,\n\tOpt_dos1xfloppy = 33,\n};\n\nenum {\n\tOpt_fatal_neterrors_default = 0,\n\tOpt_fatal_neterrors_enetunreach = 1,\n\tOpt_fatal_neterrors_none = 2,\n};\n\nenum {\n\tOpt_find_uid = 0,\n\tOpt_find_gid = 1,\n\tOpt_find_user = 2,\n\tOpt_find_group = 3,\n\tOpt_find_err = 4,\n};\n\nenum {\n\tOpt_local_lock_all = 0,\n\tOpt_local_lock_flock = 1,\n\tOpt_local_lock_none = 2,\n\tOpt_local_lock_posix = 3,\n};\n\nenum {\n\tOpt_lookupcache_all = 0,\n\tOpt_lookupcache_none = 1,\n\tOpt_lookupcache_positive = 2,\n};\n\nenum {\n\tOpt_sec_krb5 = 0,\n\tOpt_sec_krb5i = 1,\n\tOpt_sec_krb5p = 2,\n\tOpt_sec_lkey = 3,\n\tOpt_sec_lkeyi = 4,\n\tOpt_sec_lkeyp = 5,\n\tOpt_sec_none = 6,\n\tOpt_sec_spkm = 7,\n\tOpt_sec_spkmi = 8,\n\tOpt_sec_spkmp = 9,\n\tOpt_sec_sys = 10,\n\tnr__Opt_sec = 11,\n};\n\nenum {\n\tOpt_uid___2 = 0,\n\tOpt_gid___2 = 1,\n\tOpt_mode = 2,\n\tOpt_source = 3,\n};\n\nenum {\n\tOpt_uid___3 = 0,\n\tOpt_gid___3 = 1,\n\tOpt_mode___2 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___2 = 6,\n};\n\nenum {\n\tOpt_vers_2 = 0,\n\tOpt_vers_3 = 1,\n\tOpt_vers_4 = 2,\n\tOpt_vers_4_0 = 3,\n\tOpt_vers_4_1 = 4,\n\tOpt_vers_4_2 = 5,\n};\n\nenum {\n\tOpt_write_lazy = 0,\n\tOpt_write_eager = 1,\n\tOpt_write_wait = 2,\n};\n\nenum {\n\tOpt_xprt_rdma = 0,\n\tOpt_xprt_rdma6 = 1,\n\tOpt_xprt_tcp = 2,\n\tOpt_xprt_tcp6 = 3,\n\tOpt_xprt_udp = 4,\n\tOpt_xprt_udp6 = 5,\n\tnr__Opt_xprt = 6,\n};\n\nenum {\n\tOpt_xprtsec_none = 0,\n\tOpt_xprtsec_tls = 1,\n\tOpt_xprtsec_mtls = 2,\n\tnr__Opt_xprtsec = 3,\n};\n\nenum {\n\tPAGE_REPORTING_IDLE = 0,\n\tPAGE_REPORTING_REQUESTED = 1,\n\tPAGE_REPORTING_ACTIVE = 2,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPARSE_INVALID = 1,\n\tPARSE_NOT_LONGNAME = 2,\n\tPARSE_EOF = 3,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_BRIDGE_RESOURCES = 7,\n\tPCI_BRIDGE_RESOURCE_END = 10,\n\tPCI_NUM_RESOURCES = 11,\n\tDEVICE_COUNT_RESOURCE = 11,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPG_BUSY = 0,\n\tPG_MAPPED = 1,\n\tPG_FOLIO = 2,\n\tPG_CLEAN = 3,\n\tPG_COMMIT_TO_DS = 4,\n\tPG_INODE_REF = 5,\n\tPG_HEADLOCK = 6,\n\tPG_TEARDOWN = 7,\n\tPG_UNLOCKPAGE = 8,\n\tPG_UPTODATE = 9,\n\tPG_WB_END = 10,\n\tPG_REMOVE = 11,\n\tPG_CONTENDED1 = 12,\n\tPG_CONTENDED2 = 13,\n};\n\nenum {\n\tPHYLINK_DISABLE_STOPPED = 0,\n\tPHYLINK_DISABLE_LINK = 1,\n\tPHYLINK_DISABLE_MAC_WOL = 2,\n\tPHYLINK_DISABLE_REPLAY = 3,\n\tPCS_STATE_DOWN = 0,\n\tPCS_STATE_STARTING = 1,\n\tPCS_STATE_STARTED = 2,\n};\n\nenum {\n\tPIM_TYPE_HELLO = 0,\n\tPIM_TYPE_REGISTER = 1,\n\tPIM_TYPE_REGISTER_STOP = 2,\n\tPIM_TYPE_JOIN_PRUNE = 3,\n\tPIM_TYPE_BOOTSTRAP = 4,\n\tPIM_TYPE_ASSERT = 5,\n\tPIM_TYPE_GRAFT = 6,\n\tPIM_TYPE_GRAFT_ACK = 7,\n\tPIM_TYPE_CANDIDATE_RP_ADV = 8,\n};\n\nenum {\n\tPINCONF_BIAS = 0,\n\tPINCONF_SCHMITT = 1,\n\tPINCONF_DRIVE_STRENGTH = 2,\n};\n\nenum {\n\tPIPE_DRIVER_VERSION = 2,\n\tPIPE_CURRENT_DEVICE_VERSION = 2,\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = -1,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPOWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_LOW = 2,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_FULL = 5,\n};\n\nenum {\n\tPOWER_SUPPLY_HEALTH_UNKNOWN = 0,\n\tPOWER_SUPPLY_HEALTH_GOOD = 1,\n\tPOWER_SUPPLY_HEALTH_OVERHEAT = 2,\n\tPOWER_SUPPLY_HEALTH_DEAD = 3,\n\tPOWER_SUPPLY_HEALTH_OVERVOLTAGE = 4,\n\tPOWER_SUPPLY_HEALTH_UNDERVOLTAGE = 5,\n\tPOWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 6,\n\tPOWER_SUPPLY_HEALTH_COLD = 7,\n\tPOWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 8,\n\tPOWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 9,\n\tPOWER_SUPPLY_HEALTH_OVERCURRENT = 10,\n\tPOWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 11,\n\tPOWER_SUPPLY_HEALTH_WARM = 12,\n\tPOWER_SUPPLY_HEALTH_COOL = 13,\n\tPOWER_SUPPLY_HEALTH_HOT = 14,\n\tPOWER_SUPPLY_HEALTH_NO_BATTERY = 15,\n\tPOWER_SUPPLY_HEALTH_BLOWN_FUSE = 16,\n\tPOWER_SUPPLY_HEALTH_CELL_IMBALANCE = 17,\n};\n\nenum {\n\tPOWER_SUPPLY_SCOPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_SCOPE_SYSTEM = 1,\n\tPOWER_SUPPLY_SCOPE_DEVICE = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_STATUS_UNKNOWN = 0,\n\tPOWER_SUPPLY_STATUS_CHARGING = 1,\n\tPOWER_SUPPLY_STATUS_DISCHARGING = 2,\n\tPOWER_SUPPLY_STATUS_NOT_CHARGING = 3,\n\tPOWER_SUPPLY_STATUS_FULL = 4,\n};\n\nenum {\n\tPOWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,\n\tPOWER_SUPPLY_TECHNOLOGY_NiMH = 1,\n\tPOWER_SUPPLY_TECHNOLOGY_LION = 2,\n\tPOWER_SUPPLY_TECHNOLOGY_LIPO = 3,\n\tPOWER_SUPPLY_TECHNOLOGY_LiFe = 4,\n\tPOWER_SUPPLY_TECHNOLOGY_NiCd = 5,\n\tPOWER_SUPPLY_TECHNOLOGY_LiMn = 6,\n};\n\nenum {\n\tPREFIX_UNSPEC = 0,\n\tPREFIX_ADDRESS = 1,\n\tPREFIX_CACHEINFO = 2,\n\t__PREFIX_MAX = 3,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tPTP_PIN_ACTION_IDLE = 0,\n\tPTP_PIN_ACTION_LOAD = 1,\n\tPTP_PIN_ACTION_SAVE = 2,\n\tPTP_PIN_ACTION_CLOCK = 3,\n\tPTP_PIN_ACTION_DELTA = 4,\n\tPTP_PIN_ACTION_NOSYNC = 5,\n\tPTP_PIN_ACTION_SYNC = 6,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tREGULATOR_ERROR_CLEARED = 0,\n\tREGULATOR_FAILED_RETRY = 1,\n\tREGULATOR_ERROR_ON = 2,\n};\n\nenum {\n\tREG_READ = 0,\n\tREG_SET_PAGE = 0,\n\tREG_LEN = 4,\n\tREG_DATA = 8,\n\tPAGE_NAME = 0,\n\tPAGE_EVBITS = 65536,\n\tPAGE_ABSDATA = 131075,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 1250,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRPCAUTH_lockd = 0,\n\tRPCAUTH_mount = 1,\n\tRPCAUTH_nfs = 2,\n\tRPCAUTH_portmap = 3,\n\tRPCAUTH_statd = 4,\n\tRPCAUTH_nfsd4_cb = 5,\n\tRPCAUTH_cache = 6,\n\tRPCAUTH_nfsd = 7,\n\tRPCAUTH_RootEOF = 8,\n};\n\nenum {\n\tRPCBPROC_NULL = 0,\n\tRPCBPROC_SET = 1,\n\tRPCBPROC_UNSET = 2,\n\tRPCBPROC_GETPORT = 3,\n\tRPCBPROC_GETADDR = 3,\n\tRPCBPROC_DUMP = 4,\n\tRPCBPROC_CALLIT = 5,\n\tRPCBPROC_BCAST = 5,\n\tRPCBPROC_GETTIME = 6,\n\tRPCBPROC_UADDR2TADDR = 7,\n\tRPCBPROC_TADDR2UADDR = 8,\n\tRPCBPROC_GETVERSADDR = 9,\n\tRPCBPROC_INDIRECT = 10,\n\tRPCBPROC_GETADDRLIST = 11,\n\tRPCBPROC_GETSTAT = 12,\n};\n\nenum {\n\tRPCSVC_MAXPAYLOAD = 4194304,\n\tRPCSVC_MAXPAYLOAD_TCP = 4194304,\n\tRPCSVC_MAXPAYLOAD_UDP = 32768,\n};\n\nenum {\n\tRPC_PIPEFS_MOUNT = 0,\n\tRPC_PIPEFS_UMOUNT = 1,\n};\n\nenum {\n\tRPC_TASK_RUNNING = 0,\n\tRPC_TASK_QUEUED = 1,\n\tRPC_TASK_ACTIVE = 2,\n\tRPC_TASK_NEED_XMIT = 3,\n\tRPC_TASK_NEED_RECV = 4,\n\tRPC_TASK_MSG_PIN_WAIT = 5,\n};\n\nenum {\n\tRQ_SECURE = 0,\n\tRQ_LOCAL = 1,\n\tRQ_USEDEFERRAL = 2,\n\tRQ_DROPME = 3,\n\tRQ_VICTIM = 4,\n\tRQ_DATA = 5,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tRworksched = 1,\n\tRpending = 2,\n\tWworksched = 4,\n\tWpending = 8,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSEAD3_REG_LCD_CTRL = 0,\n\tSEAD3_REG_LCD_DATA = 8,\n\tSEAD3_REG_CPLD_STATUS = 16,\n\tSEAD3_REG_CPLD_DATA = 24,\n};\n\nenum {\n\tSEG6_ATTR_UNSPEC = 0,\n\tSEG6_ATTR_DST = 1,\n\tSEG6_ATTR_DSTLEN = 2,\n\tSEG6_ATTR_HMACKEYID = 3,\n\tSEG6_ATTR_SECRET = 4,\n\tSEG6_ATTR_SECRETLEN = 5,\n\tSEG6_ATTR_ALGID = 6,\n\tSEG6_ATTR_HMACINFO = 7,\n\t__SEG6_ATTR_MAX = 8,\n};\n\nenum {\n\tSEG6_CMD_UNSPEC = 0,\n\tSEG6_CMD_SETHMAC = 1,\n\tSEG6_CMD_DUMPHMAC = 2,\n\tSEG6_CMD_SET_TUNSRC = 3,\n\tSEG6_CMD_GET_TUNSRC = 4,\n\t__SEG6_CMD_MAX = 5,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSKCIPHER_WALK_SLOW = 1,\n\tSKCIPHER_WALK_COPY = 2,\n\tSKCIPHER_WALK_DIFF = 4,\n\tSKCIPHER_WALK_SLEEP = 8,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSP_TASK_PENDING = 0,\n\tSP_NEED_VICTIM = 1,\n\tSP_VICTIM_REMAINS = 2,\n\tSP_TASK_STARTING = 3,\n};\n\nenum {\n\tSTRICT = 0,\n\tEMULATED = 1,\n\tLEGACY = 2,\n\tSTD2008 = 3,\n\tRELAXED = 4,\n};\n\nenum {\n\tSUNRPC_MAX_UDP_SENDPAGES = 11,\n};\n\nenum {\n\tSUNRPC_PIPEFS_NFS_PRIO = 0,\n\tSUNRPC_PIPEFS_RPC_PRIO = 1,\n};\n\nenum {\n\tSVC_HANDSHAKE_TO = 1250,\n};\n\nenum {\n\tSVC_POOL_AUTO = -1,\n\tSVC_POOL_GLOBAL = 0,\n\tSVC_POOL_PERCPU = 1,\n\tSVC_POOL_PERNODE = 2,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWMII_SPEED_10 = 0,\n\tSWMII_SPEED_100 = 1,\n\tSWMII_SPEED_1000 = 2,\n\tSWMII_DUPLEX_HALF = 0,\n\tSWMII_DUPLEX_FULL = 1,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = -1,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 1,\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 14,\n\tTCP_DATA_OFFSET = 240,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTC_TAPRIO_CMD_SET_GATES = 0,\n\tTC_TAPRIO_CMD_SET_AND_HOLD = 1,\n\tTC_TAPRIO_CMD_SET_AND_RELEASE = 2,\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nenum {\n\tTLS_ALERT_DESC_CLOSE_NOTIFY = 0,\n\tTLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10,\n\tTLS_ALERT_DESC_BAD_RECORD_MAC = 20,\n\tTLS_ALERT_DESC_RECORD_OVERFLOW = 22,\n\tTLS_ALERT_DESC_HANDSHAKE_FAILURE = 40,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE = 42,\n\tTLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43,\n\tTLS_ALERT_DESC_CERTIFICATE_REVOKED = 44,\n\tTLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45,\n\tTLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46,\n\tTLS_ALERT_DESC_ILLEGAL_PARAMETER = 47,\n\tTLS_ALERT_DESC_UNKNOWN_CA = 48,\n\tTLS_ALERT_DESC_ACCESS_DENIED = 49,\n\tTLS_ALERT_DESC_DECODE_ERROR = 50,\n\tTLS_ALERT_DESC_DECRYPT_ERROR = 51,\n\tTLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52,\n\tTLS_ALERT_DESC_PROTOCOL_VERSION = 70,\n\tTLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71,\n\tTLS_ALERT_DESC_INTERNAL_ERROR = 80,\n\tTLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86,\n\tTLS_ALERT_DESC_USER_CANCELED = 90,\n\tTLS_ALERT_DESC_MISSING_EXTENSION = 109,\n\tTLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110,\n\tTLS_ALERT_DESC_UNRECOGNIZED_NAME = 112,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113,\n\tTLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115,\n\tTLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116,\n\tTLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120,\n};\n\nenum {\n\tTLS_ALERT_LEVEL_WARNING = 1,\n\tTLS_ALERT_LEVEL_FATAL = 2,\n};\n\nenum {\n\tTLS_NO_KEYRING = 0,\n\tTLS_NO_PEERID = 0,\n\tTLS_NO_CERT = 0,\n\tTLS_NO_PRIVKEY = 0,\n};\n\nenum {\n\tTLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20,\n\tTLS_RECORD_TYPE_ALERT = 21,\n\tTLS_RECORD_TYPE_HANDSHAKE = 22,\n\tTLS_RECORD_TYPE_DATA = 23,\n\tTLS_RECORD_TYPE_HEARTBEAT = 24,\n\tTLS_RECORD_TYPE_TLS12_CID = 25,\n\tTLS_RECORD_TYPE_ACK = 26,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tTRANS_MODE_PIO = 0,\n\tTRANS_MODE_IDMAC = 1,\n\tTRANS_MODE_EDMAC = 2,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUBI_COMPAT_DELETE = 1,\n\tUBI_COMPAT_RO = 2,\n\tUBI_COMPAT_PRESERVE = 4,\n\tUBI_COMPAT_REJECT = 5,\n};\n\nenum {\n\tUBI_DYNAMIC_VOLUME = 3,\n\tUBI_STATIC_VOLUME = 4,\n};\n\nenum {\n\tUBI_IO_FF = 1,\n\tUBI_IO_FF_BITFLIPS = 2,\n\tUBI_IO_BAD_HDR = 3,\n\tUBI_IO_BAD_HDR_EBADMSG = 4,\n\tUBI_IO_BITFLIPS = 5,\n};\n\nenum {\n\tUBI_READONLY = 1,\n\tUBI_READWRITE = 2,\n\tUBI_EXCLUSIVE = 3,\n\tUBI_METAONLY = 4,\n};\n\nenum {\n\tUBI_VID_DYNAMIC = 1,\n\tUBI_VID_STATIC = 2,\n};\n\nenum {\n\tUBI_VOLUME_ADDED = 0,\n\tUBI_VOLUME_REMOVED = 1,\n\tUBI_VOLUME_RESIZED = 2,\n\tUBI_VOLUME_RENAMED = 3,\n\tUBI_VOLUME_SHUTDOWN = 4,\n\tUBI_VOLUME_UPDATED = 5,\n};\n\nenum {\n\tUBI_VOL_PROP_DIRECT_WRITE = 1,\n};\n\nenum {\n\tUBI_VOL_SKIP_CRC_CHECK_FLG = 1,\n};\n\nenum {\n\tUBI_VTBL_AUTORESIZE_FLG = 1,\n\tUBI_VTBL_SKIP_CRC_CHECK_FLG = 2,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUNALIGNED_ACTION_QUIET = 0,\n\tUNALIGNED_ACTION_SIGNAL = 1,\n\tUNALIGNED_ACTION_SHOW = 2,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tVCAP_CORE_UPDATE_CTRL = 0,\n\tVCAP_CORE_MV_CFG = 1,\n\tVCAP_CACHE_ENTRY_DAT = 2,\n\tVCAP_CACHE_MASK_DAT = 3,\n\tVCAP_CACHE_ACTION_DAT = 4,\n\tVCAP_CACHE_CNT_DAT = 5,\n\tVCAP_CACHE_TG_DAT = 6,\n\tVCAP_CONST_VCAP_VER = 7,\n\tVCAP_CONST_ENTRY_WIDTH = 8,\n\tVCAP_CONST_ENTRY_CNT = 9,\n\tVCAP_CONST_ENTRY_SWCNT = 10,\n\tVCAP_CONST_ENTRY_TG_WIDTH = 11,\n\tVCAP_CONST_ACTION_DEF_CNT = 12,\n\tVCAP_CONST_ACTION_WIDTH = 13,\n\tVCAP_CONST_CNT_WIDTH = 14,\n\tVCAP_CONST_CORE_CNT = 15,\n\tVCAP_CONST_IF_CNT = 16,\n};\n\nenum {\n\tVCAP_ES0 = 0,\n\tVCAP_IS1 = 1,\n\tVCAP_IS2 = 2,\n\t__VCAP_COUNT = 3,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tVP_MSIX_CONFIG_VECTOR = 0,\n\tVP_MSIX_VQ_VECTOR = 1,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tXPT_BUSY = 0,\n\tXPT_CONN = 1,\n\tXPT_CLOSE = 2,\n\tXPT_DATA = 3,\n\tXPT_TEMP = 4,\n\tXPT_DEAD = 5,\n\tXPT_CHNGBUF = 6,\n\tXPT_DEFERRED = 7,\n\tXPT_OLD = 8,\n\tXPT_LISTENER = 9,\n\tXPT_CACHE_AUTH = 10,\n\tXPT_LOCAL = 11,\n\tXPT_KILL_TEMP = 12,\n\tXPT_CONG_CTRL = 13,\n\tXPT_HANDSHAKE = 14,\n\tXPT_TLS_SESSION = 15,\n\tXPT_PEER_AUTH = 16,\n\tXPT_PEER_VALID = 17,\n\tXPT_RPCB_UNREG = 18,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tMAX_ZONELISTS = 1,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 0,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 10,\n\t__SCHED_FEAT_HRTICK = 11,\n\t__SCHED_FEAT_HRTICK_DL = 12,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 13,\n\t__SCHED_FEAT_TTWU_QUEUE = 14,\n\t__SCHED_FEAT_SIS_UTIL = 15,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 16,\n\t__SCHED_FEAT_RT_PUSH_IPI = 17,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 18,\n\t__SCHED_FEAT_LB_MIN = 19,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 20,\n\t__SCHED_FEAT_WA_IDLE = 21,\n\t__SCHED_FEAT_WA_WEIGHT = 22,\n\t__SCHED_FEAT_WA_BIAS = 23,\n\t__SCHED_FEAT_UTIL_EST = 24,\n\t__SCHED_FEAT_LATENCY_WARN = 25,\n\t__SCHED_FEAT_NI_RANDOM = 26,\n\t__SCHED_FEAT_NR = 27,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NO_OBJ_EXT_BIT = 24,\n\t___GFP_LAST_BIT = 25,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 4,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 5,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 7,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 8,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 9,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 10,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 11,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 12,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 13,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 14,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 15,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 16,\n\t__ctx_convertBPF_PROG_TYPE_NETFILTER = 17,\n\t__ctx_convert_unused = 18,\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_sra_exceeded_retry_limit = 5,\n\tattr_inode_readahead = 6,\n\tattr_trigger_test_error = 7,\n\tattr_first_error_time = 8,\n\tattr_last_error_time = 9,\n\tattr_clusters_in_group = 10,\n\tattr_mb_order = 11,\n\tattr_feature = 12,\n\tattr_pointer_pi = 13,\n\tattr_pointer_ui = 14,\n\tattr_pointer_ul = 15,\n\tattr_pointer_u64 = 16,\n\tattr_pointer_u8 = 17,\n\tattr_pointer_string = 18,\n\tattr_pointer_atomic = 19,\n\tattr_journal_task = 20,\n\tattr_err_report_sec = 21,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\tlbl_incready = 1,\n\tlbl_poll_cont = 2,\n\tlbl_secondary_hang = 3,\n\tlbl_disable_coherence = 4,\n\tlbl_flush_fsb = 5,\n\tlbl_invicache = 6,\n\tlbl_flushdcache = 7,\n\tlbl_hang = 8,\n\tlbl_set_cont = 9,\n\tlbl_secondary_cont = 10,\n\tlbl_decready = 11,\n};\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n\tEXT4_IGET_BAD = 4,\n\tEXT4_IGET_EA_INODE = 8,\n} ext4_iget_flags;\n\ntypedef enum {\n\tFL_READY = 0,\n\tFL_STATUS = 1,\n\tFL_CFI_QUERY = 2,\n\tFL_JEDEC_QUERY = 3,\n\tFL_ERASING = 4,\n\tFL_ERASE_SUSPENDING = 5,\n\tFL_ERASE_SUSPENDED = 6,\n\tFL_WRITING = 7,\n\tFL_WRITING_TO_BUFFER = 8,\n\tFL_OTP_WRITE = 9,\n\tFL_WRITE_SUSPENDING = 10,\n\tFL_WRITE_SUSPENDED = 11,\n\tFL_PM_SUSPENDED = 12,\n\tFL_SYNCING = 13,\n\tFL_UNLOADING = 14,\n\tFL_LOCKING = 15,\n\tFL_UNLOCKING = 16,\n\tFL_POINT = 17,\n\tFL_XIP_WHILE_ERASING = 18,\n\tFL_XIP_WHILE_WRITING = 19,\n\tFL_SHUTDOWN = 20,\n\tFL_READING = 21,\n\tFL_CACHEDPRG = 22,\n\tFL_RESETTING = 23,\n\tFL_OTPING = 24,\n\tFL_PREPARING_ERASE = 25,\n\tFL_VERIFYING_ERASE = 26,\n\tFL_UNKNOWN = 27,\n} flstate_t;\n\ntypedef enum {\n\tFS_DECRYPT = 0,\n\tFS_ENCRYPT = 1,\n} fscrypt_direction_t;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum MIPS16e_i64_func {\n\tMIPS16e_ldsp_func = 0,\n\tMIPS16e_sdsp_func = 1,\n\tMIPS16e_sdrasp_func = 2,\n\tMIPS16e_dadjsp_func = 3,\n\tMIPS16e_ldpc_func = 4,\n};\n\nenum MIPS16e_ops {\n\tMIPS16e_jal_op = 3,\n\tMIPS16e_ld_op = 7,\n\tMIPS16e_i8_op = 12,\n\tMIPS16e_sd_op = 15,\n\tMIPS16e_lb_op = 16,\n\tMIPS16e_lh_op = 17,\n\tMIPS16e_lwsp_op = 18,\n\tMIPS16e_lw_op = 19,\n\tMIPS16e_lbu_op = 20,\n\tMIPS16e_lhu_op = 21,\n\tMIPS16e_lwpc_op = 22,\n\tMIPS16e_lwu_op = 23,\n\tMIPS16e_sb_op = 24,\n\tMIPS16e_sh_op = 25,\n\tMIPS16e_swsp_op = 26,\n\tMIPS16e_sw_op = 27,\n\tMIPS16e_rr_op = 29,\n\tMIPS16e_extend_op = 30,\n\tMIPS16e_i64_op = 31,\n};\n\nenum MIPS16e_rr_func {\n\tMIPS16e_jr_func = 0,\n};\n\nenum MIPS6e_i8_func {\n\tMIPS16e_swrasp_func = 2,\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecPublicKey = 2,\n\tOID_id_prime192v1 = 3,\n\tOID_id_prime256v1 = 4,\n\tOID_id_ecdsa_with_sha1 = 5,\n\tOID_id_ecdsa_with_sha224 = 6,\n\tOID_id_ecdsa_with_sha256 = 7,\n\tOID_id_ecdsa_with_sha384 = 8,\n\tOID_id_ecdsa_with_sha512 = 9,\n\tOID_rsaEncryption = 10,\n\tOID_sha1WithRSAEncryption = 11,\n\tOID_sha256WithRSAEncryption = 12,\n\tOID_sha384WithRSAEncryption = 13,\n\tOID_sha512WithRSAEncryption = 14,\n\tOID_sha224WithRSAEncryption = 15,\n\tOID_data = 16,\n\tOID_signed_data = 17,\n\tOID_email_address = 18,\n\tOID_contentType = 19,\n\tOID_messageDigest = 20,\n\tOID_signingTime = 21,\n\tOID_smimeCapabilites = 22,\n\tOID_smimeAuthenticatedAttrs = 23,\n\tOID_mskrb5 = 24,\n\tOID_krb5 = 25,\n\tOID_krb5u2u = 26,\n\tOID_msIndirectData = 27,\n\tOID_msStatementType = 28,\n\tOID_msSpOpusInfo = 29,\n\tOID_msPeImageDataObjId = 30,\n\tOID_msIndividualSPKeyPurpose = 31,\n\tOID_msOutlookExpress = 32,\n\tOID_ntlmssp = 33,\n\tOID_negoex = 34,\n\tOID_spnego = 35,\n\tOID_IAKerb = 36,\n\tOID_PKU2U = 37,\n\tOID_Scram = 38,\n\tOID_certAuthInfoAccess = 39,\n\tOID_sha1 = 40,\n\tOID_id_ansip384r1 = 41,\n\tOID_id_ansip521r1 = 42,\n\tOID_sha256 = 43,\n\tOID_sha384 = 44,\n\tOID_sha512 = 45,\n\tOID_sha224 = 46,\n\tOID_commonName = 47,\n\tOID_surname = 48,\n\tOID_countryName = 49,\n\tOID_locality = 50,\n\tOID_stateOrProvinceName = 51,\n\tOID_organizationName = 52,\n\tOID_organizationUnitName = 53,\n\tOID_title = 54,\n\tOID_description = 55,\n\tOID_name = 56,\n\tOID_givenName = 57,\n\tOID_initials = 58,\n\tOID_generationalQualifier = 59,\n\tOID_subjectKeyIdentifier = 60,\n\tOID_keyUsage = 61,\n\tOID_subjectAltName = 62,\n\tOID_issuerAltName = 63,\n\tOID_basicConstraints = 64,\n\tOID_crlDistributionPoints = 65,\n\tOID_certPolicies = 66,\n\tOID_authorityKeyIdentifier = 67,\n\tOID_extKeyUsage = 68,\n\tOID_NetlogonMechanism = 69,\n\tOID_appleLocalKdcSupported = 70,\n\tOID_gostCPSignA = 71,\n\tOID_gostCPSignB = 72,\n\tOID_gostCPSignC = 73,\n\tOID_gost2012PKey256 = 74,\n\tOID_gost2012PKey512 = 75,\n\tOID_gost2012Digest256 = 76,\n\tOID_gost2012Digest512 = 77,\n\tOID_gost2012Signature256 = 78,\n\tOID_gost2012Signature512 = 79,\n\tOID_gostTC26Sign256A = 80,\n\tOID_gostTC26Sign256B = 81,\n\tOID_gostTC26Sign256C = 82,\n\tOID_gostTC26Sign256D = 83,\n\tOID_gostTC26Sign512A = 84,\n\tOID_gostTC26Sign512B = 85,\n\tOID_gostTC26Sign512C = 86,\n\tOID_sm2 = 87,\n\tOID_sm3 = 88,\n\tOID_SM2_with_SM3 = 89,\n\tOID_sm3WithRSAEncryption = 90,\n\tOID_TPMLoadableKey = 91,\n\tOID_TPMImportableKey = 92,\n\tOID_TPMSealedData = 93,\n\tOID_sha3_256 = 94,\n\tOID_sha3_384 = 95,\n\tOID_sha3_512 = 96,\n\tOID_id_ecdsa_with_sha3_256 = 97,\n\tOID_id_ecdsa_with_sha3_384 = 98,\n\tOID_id_ecdsa_with_sha3_512 = 99,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102,\n\tOID_id_ml_dsa_44 = 103,\n\tOID_id_ml_dsa_65 = 104,\n\tOID_id_ml_dsa_87 = 105,\n\tOID__NR = 106,\n};\n\nenum PipeCmdCode {\n\tPIPE_CMD_OPEN = 1,\n\tPIPE_CMD_CLOSE = 2,\n\tPIPE_CMD_POLL = 3,\n\tPIPE_CMD_WRITE = 4,\n\tPIPE_CMD_WAKE_ON_WRITE = 5,\n\tPIPE_CMD_READ = 6,\n\tPIPE_CMD_WAKE_ON_READ = 7,\n\tPIPE_CMD_WAKE_ON_DONE_IO = 8,\n};\n\nenum PipeErrors {\n\tPIPE_ERROR_INVAL = -1,\n\tPIPE_ERROR_AGAIN = -2,\n\tPIPE_ERROR_NOMEM = -3,\n\tPIPE_ERROR_IO = -4,\n};\n\nenum PipeFlagsBits {\n\tBIT_CLOSED_ON_HOST = 0,\n\tBIT_WAKE_ON_WRITE = 1,\n\tBIT_WAKE_ON_READ = 2,\n};\n\nenum PipePollFlags {\n\tPIPE_POLL_IN = 1,\n\tPIPE_POLL_OUT = 2,\n\tPIPE_POLL_HUP = 4,\n};\n\nenum PipeRegs {\n\tPIPE_REG_CMD = 0,\n\tPIPE_REG_SIGNAL_BUFFER_HIGH = 4,\n\tPIPE_REG_SIGNAL_BUFFER = 8,\n\tPIPE_REG_SIGNAL_BUFFER_COUNT = 12,\n\tPIPE_REG_OPEN_BUFFER_HIGH = 20,\n\tPIPE_REG_OPEN_BUFFER = 24,\n\tPIPE_REG_VERSION = 36,\n\tPIPE_REG_GET_SIGNALLED = 48,\n};\n\nenum PipeWakeFlags {\n\tPIPE_WAKE_CLOSED = 1,\n\tPIPE_WAKE_READ = 2,\n\tPIPE_WAKE_WRITE = 4,\n\tPIPE_WAKE_UNLOCK_DMA = 8,\n\tPIPE_WAKE_UNLOCK_DMA_SHARED = 16,\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum UART_TX_FLAGS {\n\tUART_TX_NOSTOP = 1,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_ACCOUNT = 13,\n\t_SLAB_NO_USER_FLAGS = 14,\n\t_SLAB_RECLAIM_ACCOUNT = 15,\n\t_SLAB_OBJECT_POISON = 16,\n\t_SLAB_CMPXCHG_DOUBLE = 17,\n\t_SLAB_NO_OBJ_EXT = 18,\n\t_SLAB_FLAGS_LAST_BIT = 19,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum addr_type_t {\n\tUNICAST_ADDR = 0,\n\tMULTICAST_ADDR = 1,\n\tANYCAST_ADDR = 2,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum amd_chipset_gen {\n\tAMD_CHIPSET_BEFORE_ML = 0,\n\tAMD_CHIPSET_CZ = 1,\n\tAMD_CHIPSET_NL = 2,\n\tAMD_CHIPSET_UNKNOWN = 3,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nenum ata_quirks {\n\t__ATA_QUIRK_DIAGNOSTIC = 0,\n\t__ATA_QUIRK_NODMA = 1,\n\t__ATA_QUIRK_NONCQ = 2,\n\t__ATA_QUIRK_BROKEN_HPA = 3,\n\t__ATA_QUIRK_DISABLE = 4,\n\t__ATA_QUIRK_HPA_SIZE = 5,\n\t__ATA_QUIRK_IVB = 6,\n\t__ATA_QUIRK_STUCK_ERR = 7,\n\t__ATA_QUIRK_BRIDGE_OK = 8,\n\t__ATA_QUIRK_ATAPI_MOD16_DMA = 9,\n\t__ATA_QUIRK_FIRMWARE_WARN = 10,\n\t__ATA_QUIRK_1_5_GBPS = 11,\n\t__ATA_QUIRK_NOSETXFER = 12,\n\t__ATA_QUIRK_BROKEN_FPDMA_AA = 13,\n\t__ATA_QUIRK_DUMP_ID = 14,\n\t__ATA_QUIRK_MAX_SEC_LBA48 = 15,\n\t__ATA_QUIRK_ATAPI_DMADIR = 16,\n\t__ATA_QUIRK_NO_NCQ_TRIM = 17,\n\t__ATA_QUIRK_NOLPM = 18,\n\t__ATA_QUIRK_WD_BROKEN_LPM = 19,\n\t__ATA_QUIRK_ZERO_AFTER_TRIM = 20,\n\t__ATA_QUIRK_NO_DMA_LOG = 21,\n\t__ATA_QUIRK_NOTRIM = 22,\n\t__ATA_QUIRK_MAX_SEC = 23,\n\t__ATA_QUIRK_MAX_TRIM_128M = 24,\n\t__ATA_QUIRK_NO_NCQ_ON_ATI = 25,\n\t__ATA_QUIRK_NO_LPM_ON_ATI = 26,\n\t__ATA_QUIRK_NO_ID_DEV_LOG = 27,\n\t__ATA_QUIRK_NO_LOG_DIR = 28,\n\t__ATA_QUIRK_NO_FUA = 29,\n\t__ATA_QUIRK_MAX = 30,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum bcop_op {\n\tbcf_op = 0,\n\tbct_op = 1,\n\tbcfl_op = 2,\n\tbctl_op = 3,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bfqq_expiration {\n\tBFQQE_TOO_IDLE = 0,\n\tBFQQE_BUDGET_TIMEOUT = 1,\n\tBFQQE_BUDGET_EXHAUSTED = 2,\n\tBFQQE_NO_MORE_REQUESTS = 3,\n\tBFQQE_PREEMPTED = 4,\n};\n\nenum bfqq_state_flags {\n\tBFQQF_just_created = 0,\n\tBFQQF_busy = 1,\n\tBFQQF_wait_request = 2,\n\tBFQQF_non_blocking_wait_rq = 3,\n\tBFQQF_fifo_expire = 4,\n\tBFQQF_has_short_ttime = 5,\n\tBFQQF_sync = 6,\n\tBFQQF_IO_bound = 7,\n\tBFQQF_in_large_burst = 8,\n\tBFQQF_softrt_update = 9,\n\tBFQQF_coop = 10,\n\tBFQQF_split_coop = 11,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blkg_iostat_type {\n\tBLKG_IOSTAT_READ = 0,\n\tBLKG_IOSTAT_WRITE = 1,\n\tBLKG_IOSTAT_DISCARD = 2,\n\tBLKG_IOSTAT_NR = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_43bit_dma = 1,\n\tboard_ahci_ign_iferr = 2,\n\tboard_ahci_no_debounce_delay = 3,\n\tboard_ahci_no_msi = 4,\n\tboard_ahci_pcs_quirk = 5,\n\tboard_ahci_pcs_quirk_no_devslp = 6,\n\tboard_ahci_pcs_quirk_no_sntf = 7,\n\tboard_ahci_yes_fbs = 8,\n\tboard_ahci_yes_fbs_atapi_dma = 9,\n\tboard_ahci_al = 10,\n\tboard_ahci_avn = 11,\n\tboard_ahci_mcp65 = 12,\n\tboard_ahci_mcp77 = 13,\n\tboard_ahci_mcp89 = 14,\n\tboard_ahci_mv = 15,\n\tboard_ahci_sb600 = 16,\n\tboard_ahci_sb700 = 17,\n\tboard_ahci_vt8251 = 18,\n\tboard_ahci_mcp_linux = 12,\n\tboard_ahci_mcp67 = 12,\n\tboard_ahci_mcp73 = 12,\n\tboard_ahci_mcp79 = 13,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum br_boolopt_id {\n\tBR_BOOLOPT_NO_LL_LEARN = 0,\n\tBR_BOOLOPT_MCAST_VLAN_SNOOPING = 1,\n\tBR_BOOLOPT_MST_ENABLE = 2,\n\tBR_BOOLOPT_MDB_OFFLOAD_FAIL_NOTIFICATION = 3,\n\tBR_BOOLOPT_FDB_LOCAL_VLAN_0 = 4,\n\tBR_BOOLOPT_MAX = 5,\n};\n\nenum br_pkt_type {\n\tBR_PKT_UNICAST = 0,\n\tBR_PKT_MULTICAST = 1,\n\tBR_PKT_BROADCAST = 2,\n};\n\nenum bshfl_func {\n\twsbh_op = 2,\n\tseb_op = 16,\n\tseh_op = 24,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_COUNT = 0,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tio_cgrp_id = 3,\n\tmemory_cgrp_id = 4,\n\tdevices_cgrp_id = 5,\n\tfreezer_cgrp_id = 6,\n\tpids_cgrp_id = 7,\n\tCGROUP_SUBSYS_COUNT = 8,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum cleanup_prefix_rt_t {\n\tCLEANUP_PREFIX_RT_NOP = 0,\n\tCLEANUP_PREFIX_RT_DEL = 1,\n\tCLEANUP_PREFIX_RT_EXPIRE = 2,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum cop0_coi_func {\n\ttlbr_op = 1,\n\ttlbwi_op = 2,\n\ttlbwr_op = 6,\n\ttlbp_op = 8,\n\trfe_op = 16,\n\teret_op = 24,\n\twait_op = 32,\n\thypcall_op = 40,\n};\n\nenum cop1_fmt {\n\ts_fmt = 0,\n\td_fmt = 1,\n\te_fmt = 2,\n\tq_fmt = 3,\n\tw_fmt = 4,\n\tl_fmt = 5,\n};\n\nenum cop1_sdw_func {\n\tfadd_op = 0,\n\tfsub_op = 1,\n\tfmul_op = 2,\n\tfdiv_op = 3,\n\tfsqrt_op = 4,\n\tfabs_op = 5,\n\tfmov_op = 6,\n\tfneg_op = 7,\n\tfroundl_op = 8,\n\tftruncl_op = 9,\n\tfceill_op = 10,\n\tffloorl_op = 11,\n\tfround_op = 12,\n\tftrunc_op = 13,\n\tfceil_op = 14,\n\tffloor_op = 15,\n\tfsel_op = 16,\n\tfmovc_op = 17,\n\tfmovz_op = 18,\n\tfmovn_op = 19,\n\tfseleqz_op = 20,\n\tfrecip_op = 21,\n\tfrsqrt_op = 22,\n\tfselnez_op = 23,\n\tfmaddf_op = 24,\n\tfmsubf_op = 25,\n\tfrint_op = 26,\n\tfclass_op = 27,\n\tfmin_op = 28,\n\tfmina_op = 29,\n\tfmax_op = 30,\n\tfmaxa_op = 31,\n\tfcvts_op = 32,\n\tfcvtd_op = 33,\n\tfcvte_op = 34,\n\tfcvtw_op = 36,\n\tfcvtl_op = 37,\n\tfcmp_op = 48,\n};\n\nenum cop1x_func {\n\tlwxc1_op = 0,\n\tldxc1_op = 1,\n\tswxc1_op = 8,\n\tsdxc1_op = 9,\n\tpfetch_op = 15,\n\tmadd_s_op = 32,\n\tmadd_d_op = 33,\n\tmadd_e_op = 34,\n\tmsub_s_op = 40,\n\tmsub_d_op = 41,\n\tmsub_e_op = 42,\n\tnmadd_s_op = 48,\n\tnmadd_d_op = 49,\n\tnmadd_e_op = 50,\n\tnmsub_s_op = 56,\n\tnmsub_d_op = 57,\n\tnmsub_e_op = 58,\n};\n\nenum cop_op {\n\tmfc_op = 0,\n\tdmfc_op = 1,\n\tcfc_op = 2,\n\tmfhc0_op = 2,\n\tmfhc_op = 3,\n\tmtc_op = 4,\n\tdmtc_op = 5,\n\tctc_op = 6,\n\tmthc0_op = 6,\n\tmthc_op = 7,\n\tbc_op = 8,\n\tbc1eqz_op = 9,\n\tmfmc0_op = 11,\n\tbc1nez_op = 13,\n\twrpgpr_op = 14,\n\tcop_op = 16,\n\tcopm_op = 24,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cps_pm_state {\n\tCPS_PM_NC_WAIT = 0,\n\tCPS_PM_CLOCK_GATED = 1,\n\tCPS_PM_POWER_GATED = 2,\n\tCPS_PM_STATE_COUNT = 3,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_death {\n\tCPU_DEATH_HALT = 0,\n\tCPU_DEATH_POWER = 1,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_pm_event {\n\tCPU_PM_ENTER = 0,\n\tCPU_PM_ENTER_FAILED = 1,\n\tCPU_PM_EXIT = 2,\n\tCPU_CLUSTER_PM_ENTER = 3,\n\tCPU_CLUSTER_PM_ENTER_FAILED = 4,\n\tCPU_CLUSTER_PM_EXIT = 5,\n};\n\nenum cpu_type_enum {\n\tCPU_UNKNOWN = 0,\n\tCPU_R2000 = 1,\n\tCPU_R3000 = 2,\n\tCPU_R3000A = 3,\n\tCPU_R3041 = 4,\n\tCPU_R3051 = 5,\n\tCPU_R3052 = 6,\n\tCPU_R3081 = 7,\n\tCPU_R3081E = 8,\n\tCPU_R4000PC = 9,\n\tCPU_R4000SC = 10,\n\tCPU_R4000MC = 11,\n\tCPU_R4200 = 12,\n\tCPU_R4300 = 13,\n\tCPU_R4310 = 14,\n\tCPU_R4400PC = 15,\n\tCPU_R4400SC = 16,\n\tCPU_R4400MC = 17,\n\tCPU_R4600 = 18,\n\tCPU_R4640 = 19,\n\tCPU_R4650 = 20,\n\tCPU_R4700 = 21,\n\tCPU_R5000 = 22,\n\tCPU_R5500 = 23,\n\tCPU_NEVADA = 24,\n\tCPU_R10000 = 25,\n\tCPU_R12000 = 26,\n\tCPU_R14000 = 27,\n\tCPU_R16000 = 28,\n\tCPU_RM7000 = 29,\n\tCPU_SR71000 = 30,\n\tCPU_TX49XX = 31,\n\tCPU_4KC = 32,\n\tCPU_4KEC = 33,\n\tCPU_4KSC = 34,\n\tCPU_24K = 35,\n\tCPU_34K = 36,\n\tCPU_1004K = 37,\n\tCPU_74K = 38,\n\tCPU_ALCHEMY = 39,\n\tCPU_PR4450 = 40,\n\tCPU_BMIPS32 = 41,\n\tCPU_BMIPS3300 = 42,\n\tCPU_BMIPS4350 = 43,\n\tCPU_BMIPS4380 = 44,\n\tCPU_BMIPS5000 = 45,\n\tCPU_XBURST = 46,\n\tCPU_LOONGSON32 = 47,\n\tCPU_M14KC = 48,\n\tCPU_M14KEC = 49,\n\tCPU_INTERAPTIV = 50,\n\tCPU_P5600 = 51,\n\tCPU_PROAPTIV = 52,\n\tCPU_1074K = 53,\n\tCPU_M5150 = 54,\n\tCPU_I6400 = 55,\n\tCPU_P6600 = 56,\n\tCPU_M6250 = 57,\n\tCPU_5KC = 58,\n\tCPU_5KE = 59,\n\tCPU_20KC = 60,\n\tCPU_25KF = 61,\n\tCPU_SB1 = 62,\n\tCPU_SB1A = 63,\n\tCPU_LOONGSON2EF = 64,\n\tCPU_LOONGSON64 = 65,\n\tCPU_CAVIUM_OCTEON = 66,\n\tCPU_CAVIUM_OCTEON_PLUS = 67,\n\tCPU_CAVIUM_OCTEON2 = 68,\n\tCPU_CAVIUM_OCTEON3 = 69,\n\tCPU_I6500 = 70,\n\tCPU_QEMU_GENERIC = 71,\n\tCPU_LAST = 72,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tNR_STATS = 10,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum createmode4 {\n\tNFS4_CREATE_UNCHECKED = 0,\n\tNFS4_CREATE_GUARDED = 1,\n\tNFS4_CREATE_EXCLUSIVE = 2,\n\tNFS4_CREATE_EXCLUSIVE4_1 = 3,\n};\n\nenum criteria {\n\tCR_POWER2_ALIGNED = 0,\n\tCR_GOAL_LEN_FAST = 1,\n\tCR_BEST_AVAIL_LEN = 2,\n\tCR_GOAL_LEN_SLOW = 3,\n\tCR_ANY_FREE = 4,\n\tEXT4_MB_NUM_CRS = 5,\n};\n\nenum csr_target {\n\tMACRO_CTRL = 7,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum cti_port_type {\n\tCTI_PORT_TYPE_NONE = 0,\n\tCTI_PORT_TYPE_RS232 = 1,\n\tCTI_PORT_TYPE_RS422_485 = 2,\n\tCTI_PORT_TYPE_RS232_422_485_HW = 3,\n\tCTI_PORT_TYPE_RS232_422_485_SW = 4,\n\tCTI_PORT_TYPE_RS232_422_485_4B = 5,\n\tCTI_PORT_TYPE_RS232_422_485_2B = 6,\n\tCTI_PORT_TYPE_MAX = 7,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum cu2_ops {\n\tCU2_EXCEPTION = 0,\n\tCU2_LWC2_OP = 1,\n\tCU2_LDC2_OP = 2,\n\tCU2_SWC2_OP = 3,\n\tCU2_SDC2_OP = 4,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum data_content4 {\n\tNFS4_CONTENT_DATA = 0,\n\tNFS4_CONTENT_HOLE = 1,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dbshfl_func {\n\tdsbh_op = 2,\n\tdshd_op = 5,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum ddivu_op {\n\tddivu_ddivu_op = 0,\n\tddivu_ddivu6_op = 2,\n\tddivu_dmodu_op = 3,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum devcg_behavior {\n\tDEVCG_DEFAULT_NONE = 0,\n\tDEVCG_DEFAULT_ALLOW = 1,\n\tDEVCG_DEFAULT_DENY = 2,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_attr {\n\tDEVLINK_ATTR_UNSPEC = 0,\n\tDEVLINK_ATTR_BUS_NAME = 1,\n\tDEVLINK_ATTR_DEV_NAME = 2,\n\tDEVLINK_ATTR_PORT_INDEX = 3,\n\tDEVLINK_ATTR_PORT_TYPE = 4,\n\tDEVLINK_ATTR_PORT_DESIRED_TYPE = 5,\n\tDEVLINK_ATTR_PORT_NETDEV_IFINDEX = 6,\n\tDEVLINK_ATTR_PORT_NETDEV_NAME = 7,\n\tDEVLINK_ATTR_PORT_IBDEV_NAME = 8,\n\tDEVLINK_ATTR_PORT_SPLIT_COUNT = 9,\n\tDEVLINK_ATTR_PORT_SPLIT_GROUP = 10,\n\tDEVLINK_ATTR_SB_INDEX = 11,\n\tDEVLINK_ATTR_SB_SIZE = 12,\n\tDEVLINK_ATTR_SB_INGRESS_POOL_COUNT = 13,\n\tDEVLINK_ATTR_SB_EGRESS_POOL_COUNT = 14,\n\tDEVLINK_ATTR_SB_INGRESS_TC_COUNT = 15,\n\tDEVLINK_ATTR_SB_EGRESS_TC_COUNT = 16,\n\tDEVLINK_ATTR_SB_POOL_INDEX = 17,\n\tDEVLINK_ATTR_SB_POOL_TYPE = 18,\n\tDEVLINK_ATTR_SB_POOL_SIZE = 19,\n\tDEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE = 20,\n\tDEVLINK_ATTR_SB_THRESHOLD = 21,\n\tDEVLINK_ATTR_SB_TC_INDEX = 22,\n\tDEVLINK_ATTR_SB_OCC_CUR = 23,\n\tDEVLINK_ATTR_SB_OCC_MAX = 24,\n\tDEVLINK_ATTR_ESWITCH_MODE = 25,\n\tDEVLINK_ATTR_ESWITCH_INLINE_MODE = 26,\n\tDEVLINK_ATTR_DPIPE_TABLES = 27,\n\tDEVLINK_ATTR_DPIPE_TABLE = 28,\n\tDEVLINK_ATTR_DPIPE_TABLE_NAME = 29,\n\tDEVLINK_ATTR_DPIPE_TABLE_SIZE = 30,\n\tDEVLINK_ATTR_DPIPE_TABLE_MATCHES = 31,\n\tDEVLINK_ATTR_DPIPE_TABLE_ACTIONS = 32,\n\tDEVLINK_ATTR_DPIPE_TABLE_COUNTERS_ENABLED = 33,\n\tDEVLINK_ATTR_DPIPE_ENTRIES = 34,\n\tDEVLINK_ATTR_DPIPE_ENTRY = 35,\n\tDEVLINK_ATTR_DPIPE_ENTRY_INDEX = 36,\n\tDEVLINK_ATTR_DPIPE_ENTRY_MATCH_VALUES = 37,\n\tDEVLINK_ATTR_DPIPE_ENTRY_ACTION_VALUES = 38,\n\tDEVLINK_ATTR_DPIPE_ENTRY_COUNTER = 39,\n\tDEVLINK_ATTR_DPIPE_MATCH = 40,\n\tDEVLINK_ATTR_DPIPE_MATCH_VALUE = 41,\n\tDEVLINK_ATTR_DPIPE_MATCH_TYPE = 42,\n\tDEVLINK_ATTR_DPIPE_ACTION = 43,\n\tDEVLINK_ATTR_DPIPE_ACTION_VALUE = 44,\n\tDEVLINK_ATTR_DPIPE_ACTION_TYPE = 45,\n\tDEVLINK_ATTR_DPIPE_VALUE = 46,\n\tDEVLINK_ATTR_DPIPE_VALUE_MASK = 47,\n\tDEVLINK_ATTR_DPIPE_VALUE_MAPPING = 48,\n\tDEVLINK_ATTR_DPIPE_HEADERS = 49,\n\tDEVLINK_ATTR_DPIPE_HEADER = 50,\n\tDEVLINK_ATTR_DPIPE_HEADER_NAME = 51,\n\tDEVLINK_ATTR_DPIPE_HEADER_ID = 52,\n\tDEVLINK_ATTR_DPIPE_HEADER_FIELDS = 53,\n\tDEVLINK_ATTR_DPIPE_HEADER_GLOBAL = 54,\n\tDEVLINK_ATTR_DPIPE_HEADER_INDEX = 55,\n\tDEVLINK_ATTR_DPIPE_FIELD = 56,\n\tDEVLINK_ATTR_DPIPE_FIELD_NAME = 57,\n\tDEVLINK_ATTR_DPIPE_FIELD_ID = 58,\n\tDEVLINK_ATTR_DPIPE_FIELD_BITWIDTH = 59,\n\tDEVLINK_ATTR_DPIPE_FIELD_MAPPING_TYPE = 60,\n\tDEVLINK_ATTR_PAD = 61,\n\tDEVLINK_ATTR_ESWITCH_ENCAP_MODE = 62,\n\tDEVLINK_ATTR_RESOURCE_LIST = 63,\n\tDEVLINK_ATTR_RESOURCE = 64,\n\tDEVLINK_ATTR_RESOURCE_NAME = 65,\n\tDEVLINK_ATTR_RESOURCE_ID = 66,\n\tDEVLINK_ATTR_RESOURCE_SIZE = 67,\n\tDEVLINK_ATTR_RESOURCE_SIZE_NEW = 68,\n\tDEVLINK_ATTR_RESOURCE_SIZE_VALID = 69,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MIN = 70,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MAX = 71,\n\tDEVLINK_ATTR_RESOURCE_SIZE_GRAN = 72,\n\tDEVLINK_ATTR_RESOURCE_UNIT = 73,\n\tDEVLINK_ATTR_RESOURCE_OCC = 74,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID = 75,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS = 76,\n\tDEVLINK_ATTR_PORT_FLAVOUR = 77,\n\tDEVLINK_ATTR_PORT_NUMBER = 78,\n\tDEVLINK_ATTR_PORT_SPLIT_SUBPORT_NUMBER = 79,\n\tDEVLINK_ATTR_PARAM = 80,\n\tDEVLINK_ATTR_PARAM_NAME = 81,\n\tDEVLINK_ATTR_PARAM_GENERIC = 82,\n\tDEVLINK_ATTR_PARAM_TYPE = 83,\n\tDEVLINK_ATTR_PARAM_VALUES_LIST = 84,\n\tDEVLINK_ATTR_PARAM_VALUE = 85,\n\tDEVLINK_ATTR_PARAM_VALUE_DATA = 86,\n\tDEVLINK_ATTR_PARAM_VALUE_CMODE = 87,\n\tDEVLINK_ATTR_REGION_NAME = 88,\n\tDEVLINK_ATTR_REGION_SIZE = 89,\n\tDEVLINK_ATTR_REGION_SNAPSHOTS = 90,\n\tDEVLINK_ATTR_REGION_SNAPSHOT = 91,\n\tDEVLINK_ATTR_REGION_SNAPSHOT_ID = 92,\n\tDEVLINK_ATTR_REGION_CHUNKS = 93,\n\tDEVLINK_ATTR_REGION_CHUNK = 94,\n\tDEVLINK_ATTR_REGION_CHUNK_DATA = 95,\n\tDEVLINK_ATTR_REGION_CHUNK_ADDR = 96,\n\tDEVLINK_ATTR_REGION_CHUNK_LEN = 97,\n\tDEVLINK_ATTR_INFO_DRIVER_NAME = 98,\n\tDEVLINK_ATTR_INFO_SERIAL_NUMBER = 99,\n\tDEVLINK_ATTR_INFO_VERSION_FIXED = 100,\n\tDEVLINK_ATTR_INFO_VERSION_RUNNING = 101,\n\tDEVLINK_ATTR_INFO_VERSION_STORED = 102,\n\tDEVLINK_ATTR_INFO_VERSION_NAME = 103,\n\tDEVLINK_ATTR_INFO_VERSION_VALUE = 104,\n\tDEVLINK_ATTR_SB_POOL_CELL_SIZE = 105,\n\tDEVLINK_ATTR_FMSG = 106,\n\tDEVLINK_ATTR_FMSG_OBJ_NEST_START = 107,\n\tDEVLINK_ATTR_FMSG_PAIR_NEST_START = 108,\n\tDEVLINK_ATTR_FMSG_ARR_NEST_START = 109,\n\tDEVLINK_ATTR_FMSG_NEST_END = 110,\n\tDEVLINK_ATTR_FMSG_OBJ_NAME = 111,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_TYPE = 112,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_DATA = 113,\n\tDEVLINK_ATTR_HEALTH_REPORTER = 114,\n\tDEVLINK_ATTR_HEALTH_REPORTER_NAME = 115,\n\tDEVLINK_ATTR_HEALTH_REPORTER_STATE = 116,\n\tDEVLINK_ATTR_HEALTH_REPORTER_ERR_COUNT = 117,\n\tDEVLINK_ATTR_HEALTH_REPORTER_RECOVER_COUNT = 118,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS = 119,\n\tDEVLINK_ATTR_HEALTH_REPORTER_GRACEFUL_PERIOD = 120,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_RECOVER = 121,\n\tDEVLINK_ATTR_FLASH_UPDATE_FILE_NAME = 122,\n\tDEVLINK_ATTR_FLASH_UPDATE_COMPONENT = 123,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_MSG = 124,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_DONE = 125,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TOTAL = 126,\n\tDEVLINK_ATTR_PORT_PCI_PF_NUMBER = 127,\n\tDEVLINK_ATTR_PORT_PCI_VF_NUMBER = 128,\n\tDEVLINK_ATTR_STATS = 129,\n\tDEVLINK_ATTR_TRAP_NAME = 130,\n\tDEVLINK_ATTR_TRAP_ACTION = 131,\n\tDEVLINK_ATTR_TRAP_TYPE = 132,\n\tDEVLINK_ATTR_TRAP_GENERIC = 133,\n\tDEVLINK_ATTR_TRAP_METADATA = 134,\n\tDEVLINK_ATTR_TRAP_GROUP_NAME = 135,\n\tDEVLINK_ATTR_RELOAD_FAILED = 136,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS_NS = 137,\n\tDEVLINK_ATTR_NETNS_FD = 138,\n\tDEVLINK_ATTR_NETNS_PID = 139,\n\tDEVLINK_ATTR_NETNS_ID = 140,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_DUMP = 141,\n\tDEVLINK_ATTR_TRAP_POLICER_ID = 142,\n\tDEVLINK_ATTR_TRAP_POLICER_RATE = 143,\n\tDEVLINK_ATTR_TRAP_POLICER_BURST = 144,\n\tDEVLINK_ATTR_PORT_FUNCTION = 145,\n\tDEVLINK_ATTR_INFO_BOARD_SERIAL_NUMBER = 146,\n\tDEVLINK_ATTR_PORT_LANES = 147,\n\tDEVLINK_ATTR_PORT_SPLITTABLE = 148,\n\tDEVLINK_ATTR_PORT_EXTERNAL = 149,\n\tDEVLINK_ATTR_PORT_CONTROLLER_NUMBER = 150,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TIMEOUT = 151,\n\tDEVLINK_ATTR_FLASH_UPDATE_OVERWRITE_MASK = 152,\n\tDEVLINK_ATTR_RELOAD_ACTION = 153,\n\tDEVLINK_ATTR_RELOAD_ACTIONS_PERFORMED = 154,\n\tDEVLINK_ATTR_RELOAD_LIMITS = 155,\n\tDEVLINK_ATTR_DEV_STATS = 156,\n\tDEVLINK_ATTR_RELOAD_STATS = 157,\n\tDEVLINK_ATTR_RELOAD_STATS_ENTRY = 158,\n\tDEVLINK_ATTR_RELOAD_STATS_LIMIT = 159,\n\tDEVLINK_ATTR_RELOAD_STATS_VALUE = 160,\n\tDEVLINK_ATTR_REMOTE_RELOAD_STATS = 161,\n\tDEVLINK_ATTR_RELOAD_ACTION_INFO = 162,\n\tDEVLINK_ATTR_RELOAD_ACTION_STATS = 163,\n\tDEVLINK_ATTR_PORT_PCI_SF_NUMBER = 164,\n\tDEVLINK_ATTR_RATE_TYPE = 165,\n\tDEVLINK_ATTR_RATE_TX_SHARE = 166,\n\tDEVLINK_ATTR_RATE_TX_MAX = 167,\n\tDEVLINK_ATTR_RATE_NODE_NAME = 168,\n\tDEVLINK_ATTR_RATE_PARENT_NODE_NAME = 169,\n\tDEVLINK_ATTR_REGION_MAX_SNAPSHOTS = 170,\n\tDEVLINK_ATTR_LINECARD_INDEX = 171,\n\tDEVLINK_ATTR_LINECARD_STATE = 172,\n\tDEVLINK_ATTR_LINECARD_TYPE = 173,\n\tDEVLINK_ATTR_LINECARD_SUPPORTED_TYPES = 174,\n\tDEVLINK_ATTR_NESTED_DEVLINK = 175,\n\tDEVLINK_ATTR_SELFTESTS = 176,\n\tDEVLINK_ATTR_RATE_TX_PRIORITY = 177,\n\tDEVLINK_ATTR_RATE_TX_WEIGHT = 178,\n\tDEVLINK_ATTR_REGION_DIRECT = 179,\n\tDEVLINK_ATTR_RATE_TC_BWS = 180,\n\tDEVLINK_ATTR_HEALTH_REPORTER_BURST_PERIOD = 181,\n\tDEVLINK_ATTR_PARAM_VALUE_DEFAULT = 182,\n\tDEVLINK_ATTR_PARAM_RESET_DEFAULT = 183,\n\t__DEVLINK_ATTR_MAX = 184,\n\tDEVLINK_ATTR_MAX = 183,\n};\n\nenum devlink_attr_selftest_id {\n\tDEVLINK_ATTR_SELFTEST_ID_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_ID_FLASH = 1,\n\t__DEVLINK_ATTR_SELFTEST_ID_MAX = 2,\n\tDEVLINK_ATTR_SELFTEST_ID_MAX = 1,\n};\n\nenum devlink_attr_selftest_result {\n\tDEVLINK_ATTR_SELFTEST_RESULT_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_RESULT = 1,\n\tDEVLINK_ATTR_SELFTEST_RESULT_ID = 2,\n\tDEVLINK_ATTR_SELFTEST_RESULT_STATUS = 3,\n\t__DEVLINK_ATTR_SELFTEST_RESULT_MAX = 4,\n\tDEVLINK_ATTR_SELFTEST_RESULT_MAX = 3,\n};\n\nenum devlink_command {\n\tDEVLINK_CMD_UNSPEC = 0,\n\tDEVLINK_CMD_GET = 1,\n\tDEVLINK_CMD_SET = 2,\n\tDEVLINK_CMD_NEW = 3,\n\tDEVLINK_CMD_DEL = 4,\n\tDEVLINK_CMD_PORT_GET = 5,\n\tDEVLINK_CMD_PORT_SET = 6,\n\tDEVLINK_CMD_PORT_NEW = 7,\n\tDEVLINK_CMD_PORT_DEL = 8,\n\tDEVLINK_CMD_PORT_SPLIT = 9,\n\tDEVLINK_CMD_PORT_UNSPLIT = 10,\n\tDEVLINK_CMD_SB_GET = 11,\n\tDEVLINK_CMD_SB_SET = 12,\n\tDEVLINK_CMD_SB_NEW = 13,\n\tDEVLINK_CMD_SB_DEL = 14,\n\tDEVLINK_CMD_SB_POOL_GET = 15,\n\tDEVLINK_CMD_SB_POOL_SET = 16,\n\tDEVLINK_CMD_SB_POOL_NEW = 17,\n\tDEVLINK_CMD_SB_POOL_DEL = 18,\n\tDEVLINK_CMD_SB_PORT_POOL_GET = 19,\n\tDEVLINK_CMD_SB_PORT_POOL_SET = 20,\n\tDEVLINK_CMD_SB_PORT_POOL_NEW = 21,\n\tDEVLINK_CMD_SB_PORT_POOL_DEL = 22,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_GET = 23,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_SET = 24,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_NEW = 25,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_DEL = 26,\n\tDEVLINK_CMD_SB_OCC_SNAPSHOT = 27,\n\tDEVLINK_CMD_SB_OCC_MAX_CLEAR = 28,\n\tDEVLINK_CMD_ESWITCH_GET = 29,\n\tDEVLINK_CMD_ESWITCH_SET = 30,\n\tDEVLINK_CMD_DPIPE_TABLE_GET = 31,\n\tDEVLINK_CMD_DPIPE_ENTRIES_GET = 32,\n\tDEVLINK_CMD_DPIPE_HEADERS_GET = 33,\n\tDEVLINK_CMD_DPIPE_TABLE_COUNTERS_SET = 34,\n\tDEVLINK_CMD_RESOURCE_SET = 35,\n\tDEVLINK_CMD_RESOURCE_DUMP = 36,\n\tDEVLINK_CMD_RELOAD = 37,\n\tDEVLINK_CMD_PARAM_GET = 38,\n\tDEVLINK_CMD_PARAM_SET = 39,\n\tDEVLINK_CMD_PARAM_NEW = 40,\n\tDEVLINK_CMD_PARAM_DEL = 41,\n\tDEVLINK_CMD_REGION_GET = 42,\n\tDEVLINK_CMD_REGION_SET = 43,\n\tDEVLINK_CMD_REGION_NEW = 44,\n\tDEVLINK_CMD_REGION_DEL = 45,\n\tDEVLINK_CMD_REGION_READ = 46,\n\tDEVLINK_CMD_PORT_PARAM_GET = 47,\n\tDEVLINK_CMD_PORT_PARAM_SET = 48,\n\tDEVLINK_CMD_PORT_PARAM_NEW = 49,\n\tDEVLINK_CMD_PORT_PARAM_DEL = 50,\n\tDEVLINK_CMD_INFO_GET = 51,\n\tDEVLINK_CMD_HEALTH_REPORTER_GET = 52,\n\tDEVLINK_CMD_HEALTH_REPORTER_SET = 53,\n\tDEVLINK_CMD_HEALTH_REPORTER_RECOVER = 54,\n\tDEVLINK_CMD_HEALTH_REPORTER_DIAGNOSE = 55,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_GET = 56,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_CLEAR = 57,\n\tDEVLINK_CMD_FLASH_UPDATE = 58,\n\tDEVLINK_CMD_FLASH_UPDATE_END = 59,\n\tDEVLINK_CMD_FLASH_UPDATE_STATUS = 60,\n\tDEVLINK_CMD_TRAP_GET = 61,\n\tDEVLINK_CMD_TRAP_SET = 62,\n\tDEVLINK_CMD_TRAP_NEW = 63,\n\tDEVLINK_CMD_TRAP_DEL = 64,\n\tDEVLINK_CMD_TRAP_GROUP_GET = 65,\n\tDEVLINK_CMD_TRAP_GROUP_SET = 66,\n\tDEVLINK_CMD_TRAP_GROUP_NEW = 67,\n\tDEVLINK_CMD_TRAP_GROUP_DEL = 68,\n\tDEVLINK_CMD_TRAP_POLICER_GET = 69,\n\tDEVLINK_CMD_TRAP_POLICER_SET = 70,\n\tDEVLINK_CMD_TRAP_POLICER_NEW = 71,\n\tDEVLINK_CMD_TRAP_POLICER_DEL = 72,\n\tDEVLINK_CMD_HEALTH_REPORTER_TEST = 73,\n\tDEVLINK_CMD_RATE_GET = 74,\n\tDEVLINK_CMD_RATE_SET = 75,\n\tDEVLINK_CMD_RATE_NEW = 76,\n\tDEVLINK_CMD_RATE_DEL = 77,\n\tDEVLINK_CMD_LINECARD_GET = 78,\n\tDEVLINK_CMD_LINECARD_SET = 79,\n\tDEVLINK_CMD_LINECARD_NEW = 80,\n\tDEVLINK_CMD_LINECARD_DEL = 81,\n\tDEVLINK_CMD_SELFTESTS_GET = 82,\n\tDEVLINK_CMD_SELFTESTS_RUN = 83,\n\tDEVLINK_CMD_NOTIFY_FILTER_SET = 84,\n\t__DEVLINK_CMD_MAX = 85,\n\tDEVLINK_CMD_MAX = 84,\n};\n\nenum devlink_dpipe_action_type {\n\tDEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY = 0,\n};\n\nenum devlink_dpipe_field_ethernet_id {\n\tDEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC = 0,\n};\n\nenum devlink_dpipe_field_ipv4_id {\n\tDEVLINK_DPIPE_FIELD_IPV4_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_ipv6_id {\n\tDEVLINK_DPIPE_FIELD_IPV6_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_mapping_type {\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0,\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1,\n};\n\nenum devlink_dpipe_header_id {\n\tDEVLINK_DPIPE_HEADER_ETHERNET = 0,\n\tDEVLINK_DPIPE_HEADER_IPV4 = 1,\n\tDEVLINK_DPIPE_HEADER_IPV6 = 2,\n};\n\nenum devlink_dpipe_match_type {\n\tDEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT = 0,\n};\n\nenum devlink_eswitch_encap_mode {\n\tDEVLINK_ESWITCH_ENCAP_MODE_NONE = 0,\n\tDEVLINK_ESWITCH_ENCAP_MODE_BASIC = 1,\n};\n\nenum devlink_health_reporter_state {\n\tDEVLINK_HEALTH_REPORTER_STATE_HEALTHY = 0,\n\tDEVLINK_HEALTH_REPORTER_STATE_ERROR = 1,\n};\n\nenum devlink_info_version_type {\n\tDEVLINK_INFO_VERSION_TYPE_NONE = 0,\n\tDEVLINK_INFO_VERSION_TYPE_COMPONENT = 1,\n};\n\nenum devlink_linecard_state {\n\tDEVLINK_LINECARD_STATE_UNSPEC = 0,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONED = 1,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONING = 2,\n\tDEVLINK_LINECARD_STATE_PROVISIONING = 3,\n\tDEVLINK_LINECARD_STATE_PROVISIONING_FAILED = 4,\n\tDEVLINK_LINECARD_STATE_PROVISIONED = 5,\n\tDEVLINK_LINECARD_STATE_ACTIVE = 6,\n\t__DEVLINK_LINECARD_STATE_MAX = 7,\n\tDEVLINK_LINECARD_STATE_MAX = 6,\n};\n\nenum devlink_multicast_groups {\n\tDEVLINK_MCGRP_CONFIG = 0,\n};\n\nenum devlink_param_cmode {\n\tDEVLINK_PARAM_CMODE_RUNTIME = 0,\n\tDEVLINK_PARAM_CMODE_DRIVERINIT = 1,\n\tDEVLINK_PARAM_CMODE_PERMANENT = 2,\n\t__DEVLINK_PARAM_CMODE_MAX = 3,\n\tDEVLINK_PARAM_CMODE_MAX = 2,\n};\n\nenum devlink_param_generic_id {\n\tDEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET = 0,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MACS = 1,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_SRIOV = 2,\n\tDEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT = 3,\n\tDEVLINK_PARAM_GENERIC_ID_IGNORE_ARI = 4,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX = 5,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN = 6,\n\tDEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY = 7,\n\tDEVLINK_PARAM_GENERIC_ID_RESET_DEV_ON_DRV_PROBE = 8,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE = 9,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_REMOTE_DEV_RESET = 10,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ETH = 11,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA = 12,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_VNET = 13,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_IWARP = 14,\n\tDEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE = 15,\n\tDEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE = 16,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_PHC = 17,\n\tDEVLINK_PARAM_GENERIC_ID_CLOCK_ID = 18,\n\tDEVLINK_PARAM_GENERIC_ID_TOTAL_VFS = 19,\n\tDEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS = 20,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF = 21,\n\t__DEVLINK_PARAM_GENERIC_ID_MAX = 22,\n\tDEVLINK_PARAM_GENERIC_ID_MAX = 21,\n};\n\nenum devlink_param_type {\n\tDEVLINK_PARAM_TYPE_U8 = 1,\n\tDEVLINK_PARAM_TYPE_U16 = 2,\n\tDEVLINK_PARAM_TYPE_U32 = 3,\n\tDEVLINK_PARAM_TYPE_U64 = 4,\n\tDEVLINK_PARAM_TYPE_STRING = 5,\n\tDEVLINK_PARAM_TYPE_BOOL = 6,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_attr_cap {\n\tDEVLINK_PORT_FN_ATTR_CAP_ROCE_BIT = 0,\n\tDEVLINK_PORT_FN_ATTR_CAP_MIGRATABLE_BIT = 1,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_CRYPTO_BIT = 2,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_PACKET_BIT = 3,\n\t__DEVLINK_PORT_FN_ATTR_CAPS_MAX = 4,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_function_attr {\n\tDEVLINK_PORT_FUNCTION_ATTR_UNSPEC = 0,\n\tDEVLINK_PORT_FUNCTION_ATTR_HW_ADDR = 1,\n\tDEVLINK_PORT_FN_ATTR_STATE = 2,\n\tDEVLINK_PORT_FN_ATTR_OPSTATE = 3,\n\tDEVLINK_PORT_FN_ATTR_CAPS = 4,\n\tDEVLINK_PORT_FN_ATTR_DEVLINK = 5,\n\tDEVLINK_PORT_FN_ATTR_MAX_IO_EQS = 6,\n\t__DEVLINK_PORT_FUNCTION_ATTR_MAX = 7,\n\tDEVLINK_PORT_FUNCTION_ATTR_MAX = 6,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_tc_attr {\n\tDEVLINK_RATE_TC_ATTR_UNSPEC = 0,\n\tDEVLINK_RATE_TC_ATTR_INDEX = 1,\n\tDEVLINK_RATE_TC_ATTR_BW = 2,\n\t__DEVLINK_RATE_TC_ATTR_MAX = 3,\n\tDEVLINK_RATE_TC_ATTR_MAX = 2,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devlink_reload_action {\n\tDEVLINK_RELOAD_ACTION_UNSPEC = 0,\n\tDEVLINK_RELOAD_ACTION_DRIVER_REINIT = 1,\n\tDEVLINK_RELOAD_ACTION_FW_ACTIVATE = 2,\n\t__DEVLINK_RELOAD_ACTION_MAX = 3,\n\tDEVLINK_RELOAD_ACTION_MAX = 2,\n};\n\nenum devlink_reload_limit {\n\tDEVLINK_RELOAD_LIMIT_UNSPEC = 0,\n\tDEVLINK_RELOAD_LIMIT_NO_RESET = 1,\n\t__DEVLINK_RELOAD_LIMIT_MAX = 2,\n\tDEVLINK_RELOAD_LIMIT_MAX = 1,\n};\n\nenum devlink_resource_unit {\n\tDEVLINK_RESOURCE_UNIT_ENTRY = 0,\n};\n\nenum devlink_sb_pool_type {\n\tDEVLINK_SB_POOL_TYPE_INGRESS = 0,\n\tDEVLINK_SB_POOL_TYPE_EGRESS = 1,\n};\n\nenum devlink_sb_threshold_type {\n\tDEVLINK_SB_THRESHOLD_TYPE_STATIC = 0,\n\tDEVLINK_SB_THRESHOLD_TYPE_DYNAMIC = 1,\n};\n\nenum devlink_selftest_status {\n\tDEVLINK_SELFTEST_STATUS_SKIP = 0,\n\tDEVLINK_SELFTEST_STATUS_PASS = 1,\n\tDEVLINK_SELFTEST_STATUS_FAIL = 2,\n};\n\nenum devlink_trap_action {\n\tDEVLINK_TRAP_ACTION_DROP = 0,\n\tDEVLINK_TRAP_ACTION_TRAP = 1,\n\tDEVLINK_TRAP_ACTION_MIRROR = 2,\n};\n\nenum devlink_trap_generic_id {\n\tDEVLINK_TRAP_GENERIC_ID_SMAC_MC = 0,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_TAG_MISMATCH = 1,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_VLAN_FILTER = 2,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_STP_FILTER = 3,\n\tDEVLINK_TRAP_GENERIC_ID_EMPTY_TX_LIST = 4,\n\tDEVLINK_TRAP_GENERIC_ID_PORT_LOOPBACK_FILTER = 5,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_ROUTE = 6,\n\tDEVLINK_TRAP_GENERIC_ID_TTL_ERROR = 7,\n\tDEVLINK_TRAP_GENERIC_ID_TAIL_DROP = 8,\n\tDEVLINK_TRAP_GENERIC_ID_NON_IP_PACKET = 9,\n\tDEVLINK_TRAP_GENERIC_ID_UC_DIP_MC_DMAC = 10,\n\tDEVLINK_TRAP_GENERIC_ID_DIP_LB = 11,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_MC = 12,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_LB = 13,\n\tDEVLINK_TRAP_GENERIC_ID_CORRUPTED_IP_HDR = 14,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_SIP_BC = 15,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_RESERVED_SCOPE = 16,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_INTERFACE_LOCAL_SCOPE = 17,\n\tDEVLINK_TRAP_GENERIC_ID_MTU_ERROR = 18,\n\tDEVLINK_TRAP_GENERIC_ID_UNRESOLVED_NEIGH = 19,\n\tDEVLINK_TRAP_GENERIC_ID_RPF = 20,\n\tDEVLINK_TRAP_GENERIC_ID_REJECT_ROUTE = 21,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_LPM_UNICAST_MISS = 22,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_LPM_UNICAST_MISS = 23,\n\tDEVLINK_TRAP_GENERIC_ID_NON_ROUTABLE = 24,\n\tDEVLINK_TRAP_GENERIC_ID_DECAP_ERROR = 25,\n\tDEVLINK_TRAP_GENERIC_ID_OVERLAY_SMAC_MC = 26,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_FLOW_ACTION_DROP = 27,\n\tDEVLINK_TRAP_GENERIC_ID_EGRESS_FLOW_ACTION_DROP = 28,\n\tDEVLINK_TRAP_GENERIC_ID_STP = 29,\n\tDEVLINK_TRAP_GENERIC_ID_LACP = 30,\n\tDEVLINK_TRAP_GENERIC_ID_LLDP = 31,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_QUERY = 32,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V1_REPORT = 33,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_REPORT = 34,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V3_REPORT = 35,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_LEAVE = 36,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_QUERY = 37,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_REPORT = 38,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V2_REPORT = 39,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_DONE = 40,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_DHCP = 41,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DHCP = 42,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_REQUEST = 43,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_RESPONSE = 44,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_OVERLAY = 45,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_SOLICIT = 46,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_ADVERT = 47,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BFD = 48,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BFD = 49,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_OSPF = 50,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_OSPF = 51,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BGP = 52,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BGP = 53,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_VRRP = 54,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_VRRP = 55,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_PIM = 56,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_PIM = 57,\n\tDEVLINK_TRAP_GENERIC_ID_UC_LB = 58,\n\tDEVLINK_TRAP_GENERIC_ID_LOCAL_ROUTE = 59,\n\tDEVLINK_TRAP_GENERIC_ID_EXTERNAL_ROUTE = 60,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_UC_DIP_LINK_LOCAL_SCOPE = 61,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_NODES = 62,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_ROUTERS = 63,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_SOLICIT = 64,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ADVERT = 65,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_REDIRECT = 66,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_ROUTER_ALERT = 67,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ALERT = 68,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_EVENT = 69,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_GENERAL = 70,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_SAMPLE = 71,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_TRAP = 72,\n\tDEVLINK_TRAP_GENERIC_ID_EARLY_DROP = 73,\n\tDEVLINK_TRAP_GENERIC_ID_VXLAN_PARSING = 74,\n\tDEVLINK_TRAP_GENERIC_ID_LLC_SNAP_PARSING = 75,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_PARSING = 76,\n\tDEVLINK_TRAP_GENERIC_ID_PPPOE_PPP_PARSING = 77,\n\tDEVLINK_TRAP_GENERIC_ID_MPLS_PARSING = 78,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_PARSING = 79,\n\tDEVLINK_TRAP_GENERIC_ID_IP_1_PARSING = 80,\n\tDEVLINK_TRAP_GENERIC_ID_IP_N_PARSING = 81,\n\tDEVLINK_TRAP_GENERIC_ID_GRE_PARSING = 82,\n\tDEVLINK_TRAP_GENERIC_ID_UDP_PARSING = 83,\n\tDEVLINK_TRAP_GENERIC_ID_TCP_PARSING = 84,\n\tDEVLINK_TRAP_GENERIC_ID_IPSEC_PARSING = 85,\n\tDEVLINK_TRAP_GENERIC_ID_SCTP_PARSING = 86,\n\tDEVLINK_TRAP_GENERIC_ID_DCCP_PARSING = 87,\n\tDEVLINK_TRAP_GENERIC_ID_GTP_PARSING = 88,\n\tDEVLINK_TRAP_GENERIC_ID_ESP_PARSING = 89,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_NEXTHOP = 90,\n\tDEVLINK_TRAP_GENERIC_ID_DMAC_FILTER = 91,\n\tDEVLINK_TRAP_GENERIC_ID_EAPOL = 92,\n\tDEVLINK_TRAP_GENERIC_ID_LOCKED_PORT = 93,\n\t__DEVLINK_TRAP_GENERIC_ID_MAX = 94,\n\tDEVLINK_TRAP_GENERIC_ID_MAX = 93,\n};\n\nenum devlink_trap_group_generic_id {\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L2_DROPS = 0,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_DROPS = 1,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_EXCEPTIONS = 2,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BUFFER_DROPS = 3,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_TUNNEL_DROPS = 4,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_DROPS = 5,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_STP = 6,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LACP = 7,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LLDP = 8,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MC_SNOOPING = 9,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_DHCP = 10,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_NEIGH_DISCOVERY = 11,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BFD = 12,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_OSPF = 13,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BGP = 14,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_VRRP = 15,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PIM = 16,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_UC_LB = 17,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LOCAL_DELIVERY = 18,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EXTERNAL_DELIVERY = 19,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_IPV6 = 20,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_EVENT = 21,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_GENERAL = 22,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_SAMPLE = 23,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_TRAP = 24,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PARSER_ERROR_DROPS = 25,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EAPOL = 26,\n\t__DEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 27,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 26,\n};\n\nenum devlink_trap_type {\n\tDEVLINK_TRAP_TYPE_DROP = 0,\n\tDEVLINK_TRAP_TYPE_EXCEPTION = 1,\n\tDEVLINK_TRAP_TYPE_CONTROL = 2,\n};\n\nenum devlink_var_attr_type {\n\tDEVLINK_VAR_ATTR_TYPE_U8 = 1,\n\tDEVLINK_VAR_ATTR_TYPE_U16 = 2,\n\tDEVLINK_VAR_ATTR_TYPE_U32 = 3,\n\tDEVLINK_VAR_ATTR_TYPE_U64 = 4,\n\tDEVLINK_VAR_ATTR_TYPE_STRING = 5,\n\tDEVLINK_VAR_ATTR_TYPE_FLAG = 6,\n\tDEVLINK_VAR_ATTR_TYPE_NUL_STRING = 10,\n\tDEVLINK_VAR_ATTR_TYPE_BINARY = 11,\n\t__DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE = 128,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum die_val {\n\tDIE_OOPS = 1,\n\tDIE_FP = 2,\n\tDIE_TRAP = 3,\n\tDIE_RI = 4,\n\tDIE_PAGE_FAULT = 5,\n\tDIE_BREAK = 6,\n\tDIE_SSTEPBP = 7,\n\tDIE_MSAFP = 8,\n\tDIE_UPROBE = 9,\n\tDIE_UPROBE_XOL = 10,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum divu_op {\n\tdivu_divu_op = 0,\n\tdivu_divu6_op = 2,\n\tdivu_modu_op = 3,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n\tDMA_PREP_REPEAT = 256,\n\tDMA_PREP_LOAD_EOT = 512,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nenum dma_irq_dir {\n\tDMA_DIR_RX = 1,\n\tDMA_DIR_TX = 2,\n\tDMA_DIR_RXTX = 3,\n};\n\nenum dma_irq_status {\n\ttx_hard_error = 1,\n\ttx_hard_error_bump_tc = 2,\n\thandle_rx = 4,\n\thandle_tx = 8,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n\tDMA_SLAVE_BUSWIDTH_128_BYTES = 128,\n};\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n\tDMA_OUT_OF_ORDER = 4,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_COMPLETION_NO_ORDER = 13,\n\tDMA_REPEAT = 14,\n\tDMA_LOAD_EOT = 15,\n\tDMA_TX_TYPE_END = 16,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n\tDMAENGINE_ALIGN_128_BYTES = 7,\n\tDMAENGINE_ALIGN_256_BYTES = 8,\n};\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dmultu_op {\n\tdmultu_dmultu_op = 0,\n\tdmultu_dmulu_op = 2,\n\tdmultu_dmuhu_op = 3,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum dsa_db_type {\n\tDSA_DB_PORT = 0,\n\tDSA_DB_LAG = 1,\n\tDSA_DB_BRIDGE = 2,\n};\n\nenum dsa_port_mall_action_type {\n\tDSA_PORT_MALL_MIRROR = 0,\n\tDSA_PORT_MALL_POLICER = 1,\n};\n\nenum dsa_standalone_event {\n\tDSA_UC_ADD = 0,\n\tDSA_UC_DEL = 1,\n\tDSA_MC_ADD = 2,\n\tDSA_MC_DEL = 3,\n};\n\nenum dsa_tag_protocol {\n\tDSA_TAG_PROTO_NONE = 0,\n\tDSA_TAG_PROTO_BRCM = 1,\n\tDSA_TAG_PROTO_BRCM_LEGACY = 22,\n\tDSA_TAG_PROTO_BRCM_LEGACY_FCS = 29,\n\tDSA_TAG_PROTO_BRCM_PREPEND = 2,\n\tDSA_TAG_PROTO_DSA = 3,\n\tDSA_TAG_PROTO_EDSA = 4,\n\tDSA_TAG_PROTO_GSWIP = 5,\n\tDSA_TAG_PROTO_KSZ9477 = 6,\n\tDSA_TAG_PROTO_KSZ9893 = 7,\n\tDSA_TAG_PROTO_LAN9303 = 8,\n\tDSA_TAG_PROTO_MTK = 9,\n\tDSA_TAG_PROTO_QCA = 10,\n\tDSA_TAG_PROTO_TRAILER = 11,\n\tDSA_TAG_PROTO_8021Q = 12,\n\tDSA_TAG_PROTO_SJA1105 = 13,\n\tDSA_TAG_PROTO_KSZ8795 = 14,\n\tDSA_TAG_PROTO_OCELOT = 15,\n\tDSA_TAG_PROTO_AR9331 = 16,\n\tDSA_TAG_PROTO_RTL4_A = 17,\n\tDSA_TAG_PROTO_HELLCREEK = 18,\n\tDSA_TAG_PROTO_XRS700X = 19,\n\tDSA_TAG_PROTO_OCELOT_8021Q = 20,\n\tDSA_TAG_PROTO_SEVILLE = 21,\n\tDSA_TAG_PROTO_SJA1110 = 23,\n\tDSA_TAG_PROTO_RTL8_4 = 24,\n\tDSA_TAG_PROTO_RTL8_4T = 25,\n\tDSA_TAG_PROTO_RZN1_A5PSW = 26,\n\tDSA_TAG_PROTO_LAN937X = 27,\n\tDSA_TAG_PROTO_VSC73XX_8021Q = 28,\n\tDSA_TAG_PROTO_YT921X = 30,\n\tDSA_TAG_PROTO_MXL_GSW1XX = 31,\n\tDSA_TAG_PROTO_MXL862 = 32,\n};\n\nenum dw_mci_cookie {\n\tCOOKIE_UNMAPPED = 0,\n\tCOOKIE_PRE_MAPPED = 1,\n\tCOOKIE_MAPPED = 2,\n};\n\nenum dw_mci_state {\n\tSTATE_IDLE = 0,\n\tSTATE_SENDING_CMD = 1,\n\tSTATE_SENDING_DATA = 2,\n\tSTATE_DATA_BUSY = 3,\n\tSTATE_SENDING_STOP = 4,\n\tSTATE_DATA_ERROR = 5,\n\tSTATE_SENDING_CMD11 = 6,\n\tSTATE_WAITING_CMD11_DONE = 7,\n};\n\nenum dw_xpcs_clock {\n\tDW_XPCS_CORE_CLK = 0,\n\tDW_XPCS_PAD_CLK = 1,\n\tDW_XPCS_NUM_CLKS = 2,\n};\n\nenum dw_xpcs_pcs_id {\n\tDW_XPCS_ID_NATIVE = 0,\n\tNXP_SJA1105_XPCS_ID = 16,\n\tNXP_SJA1110_XPCS_ID = 32,\n\tDW_XPCS_ID = 2039926480,\n\tDW_XPCS_ID_MASK = 4294967295,\n};\n\nenum dw_xpcs_pma_id {\n\tDW_XPCS_PMA_ID_NATIVE = 0,\n\tDW_XPCS_PMA_GEN1_3G_ID = 1,\n\tDW_XPCS_PMA_GEN2_3G_ID = 2,\n\tDW_XPCS_PMA_GEN2_6G_ID = 3,\n\tDW_XPCS_PMA_GEN4_3G_ID = 4,\n\tDW_XPCS_PMA_GEN4_6G_ID = 5,\n\tDW_XPCS_PMA_GEN5_10G_ID = 6,\n\tDW_XPCS_PMA_GEN5_12G_ID = 7,\n\tWX_TXGBE_XPCS_PMA_10G_ID = 4236271616,\n\tMP_FBNIC_XPCS_PMA_100G_ID = 1183858688,\n};\n\nenum dwc2_control_phase {\n\tDWC2_CONTROL_SETUP = 0,\n\tDWC2_CONTROL_DATA = 1,\n\tDWC2_CONTROL_STATUS = 2,\n};\n\nenum dwc2_halt_status {\n\tDWC2_HC_XFER_NO_HALT_STATUS = 0,\n\tDWC2_HC_XFER_COMPLETE = 1,\n\tDWC2_HC_XFER_URB_COMPLETE = 2,\n\tDWC2_HC_XFER_ACK = 3,\n\tDWC2_HC_XFER_NAK = 4,\n\tDWC2_HC_XFER_NYET = 5,\n\tDWC2_HC_XFER_STALL = 6,\n\tDWC2_HC_XFER_XACT_ERR = 7,\n\tDWC2_HC_XFER_FRAME_OVERRUN = 8,\n\tDWC2_HC_XFER_BABBLE_ERR = 9,\n\tDWC2_HC_XFER_DATA_TOGGLE_ERR = 10,\n\tDWC2_HC_XFER_AHB_ERR = 11,\n\tDWC2_HC_XFER_PERIODIC_INCOMPLETE = 12,\n\tDWC2_HC_XFER_URB_DEQUEUE = 13,\n};\n\nenum dwc2_hsotg_dmamode {\n\tS3C_HSOTG_DMA_NONE = 0,\n\tS3C_HSOTG_DMA_ONLY = 1,\n\tS3C_HSOTG_DMA_DRV = 2,\n};\n\nenum dwc2_lx_state {\n\tDWC2_L0 = 0,\n\tDWC2_L1 = 1,\n\tDWC2_L2 = 2,\n\tDWC2_L3 = 3,\n};\n\nenum dwc2_transaction_type {\n\tDWC2_TRANSACTION_NONE = 0,\n\tDWC2_TRANSACTION_PERIODIC = 1,\n\tDWC2_TRANSACTION_NON_PERIODIC = 2,\n\tDWC2_TRANSACTION_ALL = 3,\n};\n\nenum dwmac4_irq_status {\n\ttime_stamp_irq = 4096,\n\tmmc_rx_csum_offload_irq = 2048,\n\tmmc_tx_irq = 1024,\n\tmmc_rx_irq = 512,\n\tmmc_irq = 256,\n\tlpi_irq = 32,\n\tpmt_irq = 16,\n};\n\nenum dwmac_core_type {\n\tDWMAC_CORE_MAC100 = 0,\n\tDWMAC_CORE_GMAC = 1,\n\tDWMAC_CORE_GMAC4 = 2,\n\tDWMAC_CORE_XGMAC = 3,\n};\n\nenum ehci_hrtimer_event {\n\tEHCI_HRTIMER_POLL_ASS = 0,\n\tEHCI_HRTIMER_POLL_PSS = 1,\n\tEHCI_HRTIMER_POLL_DEAD = 2,\n\tEHCI_HRTIMER_UNLINK_INTR = 3,\n\tEHCI_HRTIMER_FREE_ITDS = 4,\n\tEHCI_HRTIMER_ACTIVE_UNLINK = 5,\n\tEHCI_HRTIMER_START_UNLINK_INTR = 6,\n\tEHCI_HRTIMER_ASYNC_UNLINKS = 7,\n\tEHCI_HRTIMER_IAA_WATCHDOG = 8,\n\tEHCI_HRTIMER_DISABLE_PERIODIC = 9,\n\tEHCI_HRTIMER_DISABLE_ASYNC = 10,\n\tEHCI_HRTIMER_IO_WATCHDOG = 11,\n\tEHCI_HRTIMER_NUM_EVENTS = 12,\n};\n\nenum ehci_rh_state {\n\tEHCI_RH_HALTED = 0,\n\tEHCI_RH_SUSPENDED = 1,\n\tEHCI_RH_RUNNING = 2,\n\tEHCI_RH_STOPPING = 3,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum ext4_journal_trigger_type {\n\tEXT4_JTR_ORPHAN_FILE = 0,\n\tEXT4_JTR_NONE = 1,\n};\n\nenum ext4_li_mode {\n\tEXT4_LI_MODE_PREFETCH_BBITMAP = 0,\n\tEXT4_LI_MODE_ITABLE = 1,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum fanotify_event_type {\n\tFANOTIFY_EVENT_TYPE_FID = 0,\n\tFANOTIFY_EVENT_TYPE_FID_NAME = 1,\n\tFANOTIFY_EVENT_TYPE_PATH = 2,\n\tFANOTIFY_EVENT_TYPE_PATH_PERM = 3,\n\tFANOTIFY_EVENT_TYPE_OVERFLOW = 4,\n\tFANOTIFY_EVENT_TYPE_FS_ERROR = 5,\n\tFANOTIFY_EVENT_TYPE_MNT = 6,\n\t__FANOTIFY_EVENT_TYPE_NUM = 7,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fib6_walk_state {\n\tFWS_L = 0,\n\tFWS_R = 1,\n\tFWS_C = 2,\n\tFWS_U = 3,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum fields {\n\tRS = 1,\n\tRT = 2,\n\tRD = 4,\n\tRE = 8,\n\tSIMM = 16,\n\tUIMM = 32,\n\tBIMM = 64,\n\tJIMM = 128,\n\tFUNC = 256,\n\tSET = 512,\n\tSCIMM = 1024,\n\tSIMM9 = 2048,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum fixed_addresses {\n\tFIX_CMAP_BEGIN = 0,\n\tFIX_CMAP_END = 16,\n\tFIX_KMAP_BEGIN = 17,\n\tFIX_KMAP_END = 272,\n\t__end_of_fixed_addresses = 273,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_cls_command {\n\tFLOW_CLS_REPLACE = 0,\n\tFLOW_CLS_DESTROY = 1,\n\tFLOW_CLS_STATS = 2,\n\tFLOW_CLS_TMPLT_CREATE = 3,\n\tFLOW_CLS_TMPLT_DESTROY = 4,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum flowlabel_reflect {\n\tFLOWLABEL_REFLECT_ESTABLISHED = 1,\n\tFLOWLABEL_REFLECT_TCP_RESET = 2,\n\tFLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum fpu_mode {\n\tFPU_32BIT = 0,\n\tFPU_64BIT = 1,\n\tFPU_AS_IS = 2,\n\tFPU_HYBRID = 3,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fscache_cache_state {\n\tFSCACHE_CACHE_IS_NOT_PRESENT = 0,\n\tFSCACHE_CACHE_IS_PREPARING = 1,\n\tFSCACHE_CACHE_IS_ACTIVE = 2,\n\tFSCACHE_CACHE_GOT_IOERROR = 3,\n\tFSCACHE_CACHE_IS_WITHDRAWN = 4,\n};\n\nenum fscache_cookie_state {\n\tFSCACHE_COOKIE_STATE_QUIESCENT = 0,\n\tFSCACHE_COOKIE_STATE_LOOKING_UP = 1,\n\tFSCACHE_COOKIE_STATE_CREATING = 2,\n\tFSCACHE_COOKIE_STATE_ACTIVE = 3,\n\tFSCACHE_COOKIE_STATE_INVALIDATING = 4,\n\tFSCACHE_COOKIE_STATE_FAILED = 5,\n\tFSCACHE_COOKIE_STATE_LRU_DISCARDING = 6,\n\tFSCACHE_COOKIE_STATE_WITHDRAWING = 7,\n\tFSCACHE_COOKIE_STATE_RELINQUISHING = 8,\n\tFSCACHE_COOKIE_STATE_DROPPED = 9,\n} __attribute__((mode(byte)));\n\nenum fscache_want_state {\n\tFSCACHE_WANT_PARAMS = 0,\n\tFSCACHE_WANT_WRITE = 1,\n\tFSCACHE_WANT_READ = 2,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftlb_flags {\n\tFTLB_EN = 1,\n\tFTLB_SET_PROB = 2,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum fuse_dax_mode {\n\tFUSE_DAX_INODE_DEFAULT = 0,\n\tFUSE_DAX_ALWAYS = 1,\n\tFUSE_DAX_NEVER = 2,\n\tFUSE_DAX_INODE_USER = 3,\n};\n\nenum fuse_ext_type {\n\tFUSE_MAX_NR_SECCTX = 31,\n\tFUSE_EXT_GROUPS = 32,\n};\n\nenum fuse_notify_code {\n\tFUSE_NOTIFY_POLL = 1,\n\tFUSE_NOTIFY_INVAL_INODE = 2,\n\tFUSE_NOTIFY_INVAL_ENTRY = 3,\n\tFUSE_NOTIFY_STORE = 4,\n\tFUSE_NOTIFY_RETRIEVE = 5,\n\tFUSE_NOTIFY_DELETE = 6,\n\tFUSE_NOTIFY_RESEND = 7,\n\tFUSE_NOTIFY_INC_EPOCH = 8,\n\tFUSE_NOTIFY_PRUNE = 9,\n};\n\nenum fuse_opcode {\n\tFUSE_LOOKUP = 1,\n\tFUSE_FORGET = 2,\n\tFUSE_GETATTR = 3,\n\tFUSE_SETATTR = 4,\n\tFUSE_READLINK = 5,\n\tFUSE_SYMLINK = 6,\n\tFUSE_MKNOD = 8,\n\tFUSE_MKDIR = 9,\n\tFUSE_UNLINK = 10,\n\tFUSE_RMDIR = 11,\n\tFUSE_RENAME = 12,\n\tFUSE_LINK = 13,\n\tFUSE_OPEN = 14,\n\tFUSE_READ = 15,\n\tFUSE_WRITE = 16,\n\tFUSE_STATFS = 17,\n\tFUSE_RELEASE = 18,\n\tFUSE_FSYNC = 20,\n\tFUSE_SETXATTR = 21,\n\tFUSE_GETXATTR = 22,\n\tFUSE_LISTXATTR = 23,\n\tFUSE_REMOVEXATTR = 24,\n\tFUSE_FLUSH = 25,\n\tFUSE_INIT = 26,\n\tFUSE_OPENDIR = 27,\n\tFUSE_READDIR = 28,\n\tFUSE_RELEASEDIR = 29,\n\tFUSE_FSYNCDIR = 30,\n\tFUSE_GETLK = 31,\n\tFUSE_SETLK = 32,\n\tFUSE_SETLKW = 33,\n\tFUSE_ACCESS = 34,\n\tFUSE_CREATE = 35,\n\tFUSE_INTERRUPT = 36,\n\tFUSE_BMAP = 37,\n\tFUSE_DESTROY = 38,\n\tFUSE_IOCTL = 39,\n\tFUSE_POLL = 40,\n\tFUSE_NOTIFY_REPLY = 41,\n\tFUSE_BATCH_FORGET = 42,\n\tFUSE_FALLOCATE = 43,\n\tFUSE_READDIRPLUS = 44,\n\tFUSE_RENAME2 = 45,\n\tFUSE_LSEEK = 46,\n\tFUSE_COPY_FILE_RANGE = 47,\n\tFUSE_SETUPMAPPING = 48,\n\tFUSE_REMOVEMAPPING = 49,\n\tFUSE_SYNCFS = 50,\n\tFUSE_TMPFILE = 51,\n\tFUSE_STATX = 52,\n\tFUSE_COPY_FILE_RANGE_64 = 53,\n\tCUSE_INIT = 4096,\n\tCUSE_INIT_BSWAP_RESERVED = 1048576,\n\tFUSE_INIT_BSWAP_RESERVED = 436207616,\n};\n\nenum fuse_parse_result {\n\tFOUND_ERR = -1,\n\tFOUND_NONE = 0,\n\tFOUND_SOME = 1,\n\tFOUND_ALL = 2,\n};\n\nenum fuse_req_flag {\n\tFR_ISREPLY = 0,\n\tFR_FORCE = 1,\n\tFR_BACKGROUND = 2,\n\tFR_WAITING = 3,\n\tFR_ABORTED = 4,\n\tFR_INTERRUPTED = 5,\n\tFR_LOCKED = 6,\n\tFR_PENDING = 7,\n\tFR_SENT = 8,\n\tFR_FINISHED = 9,\n\tFR_PRIVATE = 10,\n\tFR_ASYNC = 11,\n\tFR_URING = 12,\n};\n\nenum fuse_ring_req_state {\n\tFRRS_INVALID = 0,\n\tFRRS_COMMIT = 1,\n\tFRRS_AVAILABLE = 2,\n\tFRRS_FUSE_REQ = 3,\n\tFRRS_USERSPACE = 4,\n\tFRRS_TEARDOWN = 5,\n\tFRRS_RELEASED = 6,\n};\n\nenum fuse_uring_cmd {\n\tFUSE_IO_URING_CMD_INVALID = 0,\n\tFUSE_IO_URING_CMD_REGISTER = 1,\n\tFUSE_IO_URING_CMD_COMMIT_AND_FETCH = 2,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n\tFW_OPT_PARTIAL = 128,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nenum fwh_lock_state {\n\tFWH_UNLOCKED = 0,\n\tFWH_DENY_WRITE = 1,\n\tFWH_IMMUTABLE = 2,\n\tFWH_DENY_READ = 4,\n};\n\nenum gddrnf4_status {\n\tGDD4_OK = 0,\n\tGDD4_UNAVAIL = 1,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum gpio_lookup_flags {\n\tGPIO_ACTIVE_HIGH = 0,\n\tGPIO_ACTIVE_LOW = 1,\n\tGPIO_OPEN_DRAIN = 2,\n\tGPIO_OPEN_SOURCE = 4,\n\tGPIO_PERSISTENT = 0,\n\tGPIO_TRANSITORY = 8,\n\tGPIO_PULL_UP = 16,\n\tGPIO_PULL_DOWN = 32,\n\tGPIO_PULL_DISABLE = 64,\n\tGPIO_LOOKUP_FLAGS_DEFAULT = 0,\n};\n\nenum gpio_v2_line_attr_id {\n\tGPIO_V2_LINE_ATTR_ID_FLAGS = 1,\n\tGPIO_V2_LINE_ATTR_ID_OUTPUT_VALUES = 2,\n\tGPIO_V2_LINE_ATTR_ID_DEBOUNCE = 3,\n};\n\nenum gpio_v2_line_changed_type {\n\tGPIO_V2_LINE_CHANGED_REQUESTED = 1,\n\tGPIO_V2_LINE_CHANGED_RELEASED = 2,\n\tGPIO_V2_LINE_CHANGED_CONFIG = 3,\n};\n\nenum gpio_v2_line_event_id {\n\tGPIO_V2_LINE_EVENT_RISING_EDGE = 1,\n\tGPIO_V2_LINE_EVENT_FALLING_EDGE = 2,\n};\n\nenum gpio_v2_line_flag {\n\tGPIO_V2_LINE_FLAG_USED = 1,\n\tGPIO_V2_LINE_FLAG_ACTIVE_LOW = 2,\n\tGPIO_V2_LINE_FLAG_INPUT = 4,\n\tGPIO_V2_LINE_FLAG_OUTPUT = 8,\n\tGPIO_V2_LINE_FLAG_EDGE_RISING = 16,\n\tGPIO_V2_LINE_FLAG_EDGE_FALLING = 32,\n\tGPIO_V2_LINE_FLAG_OPEN_DRAIN = 64,\n\tGPIO_V2_LINE_FLAG_OPEN_SOURCE = 128,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_UP = 256,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_DOWN = 512,\n\tGPIO_V2_LINE_FLAG_BIAS_DISABLED = 1024,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME = 2048,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE = 4096,\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum handshake_auth {\n\tHANDSHAKE_AUTH_UNSPEC = 0,\n\tHANDSHAKE_AUTH_UNAUTH = 1,\n\tHANDSHAKE_AUTH_PSK = 2,\n\tHANDSHAKE_AUTH_X509 = 3,\n};\n\nenum handshake_handler_class {\n\tHANDSHAKE_HANDLER_CLASS_NONE = 0,\n\tHANDSHAKE_HANDLER_CLASS_TLSHD = 1,\n\tHANDSHAKE_HANDLER_CLASS_MAX = 2,\n};\n\nenum handshake_msg_type {\n\tHANDSHAKE_MSG_TYPE_UNSPEC = 0,\n\tHANDSHAKE_MSG_TYPE_CLIENTHELLO = 1,\n\tHANDSHAKE_MSG_TYPE_SERVERHELLO = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum hid_class_request {\n\tHID_REQ_GET_REPORT = 1,\n\tHID_REQ_GET_IDLE = 2,\n\tHID_REQ_GET_PROTOCOL = 3,\n\tHID_REQ_SET_REPORT = 9,\n\tHID_REQ_SET_IDLE = 10,\n\tHID_REQ_SET_PROTOCOL = 11,\n};\n\nenum hid_report_type {\n\tHID_INPUT_REPORT = 0,\n\tHID_OUTPUT_REPORT = 1,\n\tHID_FEATURE_REPORT = 2,\n\tHID_REPORT_TYPES = 3,\n};\n\nenum hid_type {\n\tHID_TYPE_OTHER = 0,\n\tHID_TYPE_USBMOUSE = 1,\n\tHID_TYPE_USBNONE = 2,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hn_flags_bits {\n\tHANDSHAKE_F_NET_DRAINING = 0,\n};\n\nenum hp_flags_bits {\n\tHANDSHAKE_F_PROTO_NOTIFY = 0,\n};\n\nenum hr_flags_bits {\n\tHANDSHAKE_F_REQ_COMPLETED = 0,\n\tHANDSHAKE_F_REQ_SESSION = 1,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nenum hsr_port_type {\n\tHSR_PT_NONE = 0,\n\tHSR_PT_SLAVE_A = 1,\n\tHSR_PT_SLAVE_B = 2,\n\tHSR_PT_INTERLINK = 3,\n\tHSR_PT_MASTER = 4,\n\tHSR_PT_PORTS = 5,\n};\n\nenum hub_activation_type {\n\tHUB_INIT = 0,\n\tHUB_INIT2 = 1,\n\tHUB_INIT3 = 2,\n\tHUB_POST_RESET = 3,\n\tHUB_RESUME = 4,\n\tHUB_RESET_RESUME = 5,\n};\n\nenum hub_led_mode {\n\tINDICATOR_AUTO = 0,\n\tINDICATOR_CYCLE = 1,\n\tINDICATOR_GREEN_BLINK = 2,\n\tINDICATOR_GREEN_BLINK_OFF = 3,\n\tINDICATOR_AMBER_BLINK = 4,\n\tINDICATOR_AMBER_BLINK_OFF = 5,\n\tINDICATOR_ALT_BLINK = 6,\n\tINDICATOR_ALT_BLINK_OFF = 7,\n} __attribute__((mode(byte)));\n\nenum hub_quiescing_type {\n\tHUB_DISCONNECT = 0,\n\tHUB_PRE_RESET = 1,\n\tHUB_SUSPEND = 2,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nenum i2c_scl_freq {\n\tREG_VALUES_100KHZ = 0,\n\tREG_VALUES_400KHZ = 1,\n\tREG_VALUES_1MHZ = 2,\n};\n\nenum ib_atomic_cap {\n\tIB_ATOMIC_NONE = 0,\n\tIB_ATOMIC_HCA = 1,\n\tIB_ATOMIC_GLOB = 2,\n};\n\nenum ib_cq_notify_flags {\n\tIB_CQ_SOLICITED = 1,\n\tIB_CQ_NEXT_COMP = 2,\n\tIB_CQ_SOLICITED_MASK = 3,\n\tIB_CQ_REPORT_MISSED_EVENTS = 4,\n};\n\nenum ib_event_type {\n\tIB_EVENT_CQ_ERR = 0,\n\tIB_EVENT_QP_FATAL = 1,\n\tIB_EVENT_QP_REQ_ERR = 2,\n\tIB_EVENT_QP_ACCESS_ERR = 3,\n\tIB_EVENT_COMM_EST = 4,\n\tIB_EVENT_SQ_DRAINED = 5,\n\tIB_EVENT_PATH_MIG = 6,\n\tIB_EVENT_PATH_MIG_ERR = 7,\n\tIB_EVENT_DEVICE_FATAL = 8,\n\tIB_EVENT_PORT_ACTIVE = 9,\n\tIB_EVENT_PORT_ERR = 10,\n\tIB_EVENT_LID_CHANGE = 11,\n\tIB_EVENT_PKEY_CHANGE = 12,\n\tIB_EVENT_SM_CHANGE = 13,\n\tIB_EVENT_SRQ_ERR = 14,\n\tIB_EVENT_SRQ_LIMIT_REACHED = 15,\n\tIB_EVENT_QP_LAST_WQE_REACHED = 16,\n\tIB_EVENT_CLIENT_REREGISTER = 17,\n\tIB_EVENT_GID_CHANGE = 18,\n\tIB_EVENT_WQ_FATAL = 19,\n\tIB_EVENT_DEVICE_SPEED_CHANGE = 20,\n};\n\nenum ib_flow_action_type {\n\tIB_FLOW_ACTION_UNSPECIFIED = 0,\n\tIB_FLOW_ACTION_ESP = 1,\n};\n\nenum ib_flow_attr_type {\n\tIB_FLOW_ATTR_NORMAL = 0,\n\tIB_FLOW_ATTR_ALL_DEFAULT = 1,\n\tIB_FLOW_ATTR_MC_DEFAULT = 2,\n\tIB_FLOW_ATTR_SNIFFER = 3,\n};\n\nenum ib_flow_spec_type {\n\tIB_FLOW_SPEC_ETH = 32,\n\tIB_FLOW_SPEC_IB = 34,\n\tIB_FLOW_SPEC_IPV4 = 48,\n\tIB_FLOW_SPEC_IPV6 = 49,\n\tIB_FLOW_SPEC_ESP = 52,\n\tIB_FLOW_SPEC_TCP = 64,\n\tIB_FLOW_SPEC_UDP = 65,\n\tIB_FLOW_SPEC_VXLAN_TUNNEL = 80,\n\tIB_FLOW_SPEC_GRE = 81,\n\tIB_FLOW_SPEC_MPLS = 96,\n\tIB_FLOW_SPEC_INNER = 256,\n\tIB_FLOW_SPEC_ACTION_TAG = 4096,\n\tIB_FLOW_SPEC_ACTION_DROP = 4097,\n\tIB_FLOW_SPEC_ACTION_HANDLE = 4098,\n\tIB_FLOW_SPEC_ACTION_COUNT = 4099,\n};\n\nenum ib_gid_type {\n\tIB_GID_TYPE_IB = 0,\n\tIB_GID_TYPE_ROCE = 1,\n\tIB_GID_TYPE_ROCE_UDP_ENCAP = 2,\n\tIB_GID_TYPE_SIZE = 3,\n};\n\nenum ib_mig_state {\n\tIB_MIG_MIGRATED = 0,\n\tIB_MIG_REARM = 1,\n\tIB_MIG_ARMED = 2,\n};\n\nenum ib_mr_type {\n\tIB_MR_TYPE_MEM_REG = 0,\n\tIB_MR_TYPE_SG_GAPS = 1,\n\tIB_MR_TYPE_DM = 2,\n\tIB_MR_TYPE_USER = 3,\n\tIB_MR_TYPE_DMA = 4,\n\tIB_MR_TYPE_INTEGRITY = 5,\n};\n\nenum ib_mtu {\n\tIB_MTU_256 = 1,\n\tIB_MTU_512 = 2,\n\tIB_MTU_1024 = 3,\n\tIB_MTU_2048 = 4,\n\tIB_MTU_4096 = 5,\n};\n\nenum ib_mw_type {\n\tIB_MW_TYPE_1 = 1,\n\tIB_MW_TYPE_2 = 2,\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nenum ib_port_state {\n\tIB_PORT_NOP = 0,\n\tIB_PORT_DOWN = 1,\n\tIB_PORT_INIT = 2,\n\tIB_PORT_ARMED = 3,\n\tIB_PORT_ACTIVE = 4,\n\tIB_PORT_ACTIVE_DEFER = 5,\n};\n\nenum ib_qp_state {\n\tIB_QPS_RESET = 0,\n\tIB_QPS_INIT = 1,\n\tIB_QPS_RTR = 2,\n\tIB_QPS_RTS = 3,\n\tIB_QPS_SQD = 4,\n\tIB_QPS_SQE = 5,\n\tIB_QPS_ERR = 6,\n};\n\nenum ib_qp_type {\n\tIB_QPT_SMI = 0,\n\tIB_QPT_GSI = 1,\n\tIB_QPT_RC = 2,\n\tIB_QPT_UC = 3,\n\tIB_QPT_UD = 4,\n\tIB_QPT_RAW_IPV6 = 5,\n\tIB_QPT_RAW_ETHERTYPE = 6,\n\tIB_QPT_RAW_PACKET = 8,\n\tIB_QPT_XRC_INI = 9,\n\tIB_QPT_XRC_TGT = 10,\n\tIB_QPT_MAX = 11,\n\tIB_QPT_DRIVER = 255,\n\tIB_QPT_RESERVED1 = 4096,\n\tIB_QPT_RESERVED2 = 4097,\n\tIB_QPT_RESERVED3 = 4098,\n\tIB_QPT_RESERVED4 = 4099,\n\tIB_QPT_RESERVED5 = 4100,\n\tIB_QPT_RESERVED6 = 4101,\n\tIB_QPT_RESERVED7 = 4102,\n\tIB_QPT_RESERVED8 = 4103,\n\tIB_QPT_RESERVED9 = 4104,\n\tIB_QPT_RESERVED10 = 4105,\n};\n\nenum ib_sig_err_type {\n\tIB_SIG_BAD_GUARD = 0,\n\tIB_SIG_BAD_REFTAG = 1,\n\tIB_SIG_BAD_APPTAG = 2,\n};\n\nenum ib_sig_type {\n\tIB_SIGNAL_ALL_WR = 0,\n\tIB_SIGNAL_REQ_WR = 1,\n};\n\nenum ib_signature_type {\n\tIB_SIG_TYPE_NONE = 0,\n\tIB_SIG_TYPE_T10_DIF = 1,\n};\n\nenum ib_srq_attr_mask {\n\tIB_SRQ_MAX_WR = 1,\n\tIB_SRQ_LIMIT = 2,\n};\n\nenum ib_srq_type {\n\tIB_SRQT_BASIC = 0,\n\tIB_SRQT_XRC = 1,\n\tIB_SRQT_TM = 2,\n};\n\nenum ib_t10_dif_bg_type {\n\tIB_T10DIF_CRC = 0,\n\tIB_T10DIF_CSUM = 1,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_FLUSH_GLOBAL = 256,\n\tIB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_advise_mr_advice {\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2,\n};\n\nenum ib_uverbs_device_cap_flags {\n\tIB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL,\n\tIB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL,\n\tIB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL,\n\tIB_UVERBS_DEVICE_RAW_MULTI = 8ULL,\n\tIB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL,\n\tIB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL,\n\tIB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL,\n\tIB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL,\n\tIB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL,\n\tIB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL,\n\tIB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL,\n\tIB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL,\n\tIB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL,\n\tIB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL,\n\tIB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL,\n\tIB_UVERBS_DEVICE_XRC = 1048576ULL,\n\tIB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL,\n\tIB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL,\n\tIB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL,\n\tIB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL,\n\tIB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL,\n\tIB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL,\n\tIB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL,\n\tIB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL,\n\tIB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL,\n};\n\nenum ib_uverbs_gid_type {\n\tIB_UVERBS_GID_TYPE_IB = 0,\n\tIB_UVERBS_GID_TYPE_ROCE_V1 = 1,\n\tIB_UVERBS_GID_TYPE_ROCE_V2 = 2,\n};\n\nenum ib_uverbs_odp_general_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT = 1,\n\tIB_UVERBS_ODP_SUPPORT_IMPLICIT = 2,\n};\n\nenum ib_uverbs_odp_transport_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT_SEND = 1,\n\tIB_UVERBS_ODP_SUPPORT_RECV = 2,\n\tIB_UVERBS_ODP_SUPPORT_WRITE = 4,\n\tIB_UVERBS_ODP_SUPPORT_READ = 8,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC = 16,\n\tIB_UVERBS_ODP_SUPPORT_SRQ_RECV = 32,\n\tIB_UVERBS_ODP_SUPPORT_FLUSH = 64,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 128,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_raw_packet_caps {\n\tIB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2,\n\tIB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4,\n\tIB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wc_opcode {\n\tIB_UVERBS_WC_SEND = 0,\n\tIB_UVERBS_WC_RDMA_WRITE = 1,\n\tIB_UVERBS_WC_RDMA_READ = 2,\n\tIB_UVERBS_WC_COMP_SWAP = 3,\n\tIB_UVERBS_WC_FETCH_ADD = 4,\n\tIB_UVERBS_WC_BIND_MW = 5,\n\tIB_UVERBS_WC_LOCAL_INV = 6,\n\tIB_UVERBS_WC_TSO = 7,\n\tIB_UVERBS_WC_FLUSH = 8,\n\tIB_UVERBS_WC_ATOMIC_WRITE = 9,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_UVERBS_WR_FLUSH = 14,\n\tIB_UVERBS_WR_ATOMIC_WRITE = 15,\n};\n\nenum ib_wc_opcode {\n\tIB_WC_SEND = 0,\n\tIB_WC_RDMA_WRITE = 1,\n\tIB_WC_RDMA_READ = 2,\n\tIB_WC_COMP_SWAP = 3,\n\tIB_WC_FETCH_ADD = 4,\n\tIB_WC_BIND_MW = 5,\n\tIB_WC_LOCAL_INV = 6,\n\tIB_WC_LSO = 7,\n\tIB_WC_ATOMIC_WRITE = 9,\n\tIB_WC_REG_MR = 10,\n\tIB_WC_MASKED_COMP_SWAP = 11,\n\tIB_WC_MASKED_FETCH_ADD = 12,\n\tIB_WC_FLUSH = 8,\n\tIB_WC_RECV = 128,\n\tIB_WC_RECV_RDMA_WITH_IMM = 129,\n};\n\nenum ib_wc_status {\n\tIB_WC_SUCCESS = 0,\n\tIB_WC_LOC_LEN_ERR = 1,\n\tIB_WC_LOC_QP_OP_ERR = 2,\n\tIB_WC_LOC_EEC_OP_ERR = 3,\n\tIB_WC_LOC_PROT_ERR = 4,\n\tIB_WC_WR_FLUSH_ERR = 5,\n\tIB_WC_MW_BIND_ERR = 6,\n\tIB_WC_BAD_RESP_ERR = 7,\n\tIB_WC_LOC_ACCESS_ERR = 8,\n\tIB_WC_REM_INV_REQ_ERR = 9,\n\tIB_WC_REM_ACCESS_ERR = 10,\n\tIB_WC_REM_OP_ERR = 11,\n\tIB_WC_RETRY_EXC_ERR = 12,\n\tIB_WC_RNR_RETRY_EXC_ERR = 13,\n\tIB_WC_LOC_RDD_VIOL_ERR = 14,\n\tIB_WC_REM_INV_RD_REQ_ERR = 15,\n\tIB_WC_REM_ABORT_ERR = 16,\n\tIB_WC_INV_EECN_ERR = 17,\n\tIB_WC_INV_EEC_STATE_ERR = 18,\n\tIB_WC_FATAL_ERR = 19,\n\tIB_WC_RESP_TIMEOUT_ERR = 20,\n\tIB_WC_GENERAL_ERR = 21,\n};\n\nenum ib_wq_state {\n\tIB_WQS_RESET = 0,\n\tIB_WQS_RDY = 1,\n\tIB_WQS_ERR = 2,\n};\n\nenum ib_wq_type {\n\tIB_WQT_RQ = 0,\n};\n\nenum ib_wr_opcode {\n\tIB_WR_RDMA_WRITE = 0,\n\tIB_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_WR_SEND = 2,\n\tIB_WR_SEND_WITH_IMM = 3,\n\tIB_WR_RDMA_READ = 4,\n\tIB_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_WR_BIND_MW = 8,\n\tIB_WR_LSO = 10,\n\tIB_WR_SEND_WITH_INV = 9,\n\tIB_WR_RDMA_READ_WITH_INV = 11,\n\tIB_WR_LOCAL_INV = 7,\n\tIB_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_WR_FLUSH = 14,\n\tIB_WR_ATOMIC_WRITE = 15,\n\tIB_WR_REG_MR = 32,\n\tIB_WR_REG_MR_INTEGRITY = 33,\n\tIB_WR_RESERVED1 = 240,\n\tIB_WR_RESERVED2 = 241,\n\tIB_WR_RESERVED3 = 242,\n\tIB_WR_RESERVED4 = 243,\n\tIB_WR_RESERVED5 = 244,\n\tIB_WR_RESERVED6 = 245,\n\tIB_WR_RESERVED7 = 246,\n\tIB_WR_RESERVED8 = 247,\n\tIB_WR_RESERVED9 = 248,\n\tIB_WR_RESERVED10 = 249,\n};\n\nenum img_i2c_mode {\n\tMODE_INACTIVE = 0,\n\tMODE_RAW = 1,\n\tMODE_ATOMIC = 2,\n\tMODE_AUTOMATIC = 3,\n\tMODE_SEQUENCE = 4,\n\tMODE_FATAL = 5,\n\tMODE_WAITSTOP = 6,\n\tMODE_SUSPEND = 7,\n};\n\nenum in6_addr_gen_mode {\n\tIN6_ADDR_GEN_MODE_EUI64 = 0,\n\tIN6_ADDR_GEN_MODE_NONE = 1,\n\tIN6_ADDR_GEN_MODE_STABLE_PRIVACY = 2,\n\tIN6_ADDR_GEN_MODE_RANDOM = 3,\n};\n\nenum inband_type {\n\tINBAND_NONE = 0,\n\tINBAND_CISCO_SGMII = 1,\n\tINBAND_BASEX = 2,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum ingenic_machine_type {\n\tMACH_INGENIC_UNKNOWN = 0,\n\tMACH_INGENIC_JZ4720 = 1,\n\tMACH_INGENIC_JZ4725 = 2,\n\tMACH_INGENIC_JZ4725B = 3,\n\tMACH_INGENIC_JZ4730 = 4,\n\tMACH_INGENIC_JZ4740 = 5,\n\tMACH_INGENIC_JZ4750 = 6,\n\tMACH_INGENIC_JZ4755 = 7,\n\tMACH_INGENIC_JZ4760 = 8,\n\tMACH_INGENIC_JZ4760B = 9,\n\tMACH_INGENIC_JZ4770 = 10,\n\tMACH_INGENIC_JZ4775 = 11,\n\tMACH_INGENIC_JZ4780 = 12,\n\tMACH_INGENIC_X1000 = 13,\n\tMACH_INGENIC_X1000E = 14,\n\tMACH_INGENIC_X1830 = 15,\n\tMACH_INGENIC_X2000 = 16,\n\tMACH_INGENIC_X2000E = 17,\n\tMACH_INGENIC_X2000H = 18,\n\tMACH_INGENIC_X2100 = 19,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioam6_event_attr {\n\tIOAM6_EVENT_ATTR_UNSPEC = 0,\n\tIOAM6_EVENT_ATTR_TRACE_NAMESPACE = 1,\n\tIOAM6_EVENT_ATTR_TRACE_NODELEN = 2,\n\tIOAM6_EVENT_ATTR_TRACE_TYPE = 3,\n\tIOAM6_EVENT_ATTR_TRACE_DATA = 4,\n\t__IOAM6_EVENT_ATTR_MAX = 5,\n};\n\nenum ioam6_event_type {\n\tIOAM6_EVENT_UNSPEC = 0,\n\tIOAM6_EVENT_TRACE = 1,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum ip6_defrag_users {\n\tIP6_DEFRAG_LOCAL_DELIVER = 0,\n\tIP6_DEFRAG_CONNTRACK_IN = 1,\n\t__IP6_DEFRAG_CONNTRACK_IN = 65536,\n\tIP6_DEFRAG_CONNTRACK_OUT = 65537,\n\t__IP6_DEFRAG_CONNTRACK_OUT = 131072,\n\tIP6_DEFRAG_CONNTRACK_BRIDGE_IN = 131073,\n\t__IP6_DEFRAG_CONNTRACK_BRIDGE_IN = 196608,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_conntrack_info;\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum jbd2_shrink_type {\n\tJBD2_SHRINK_DESTROY = 0,\n\tJBD2_SHRINK_BUSY_STOP = 1,\n\tJBD2_SHRINK_BUSY_SKIP = 2,\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 17,\n\tBH_JWrite = 18,\n\tBH_Freed = 19,\n\tBH_Revoked = 20,\n\tBH_RevokeValid = 21,\n\tBH_JBDDirty = 22,\n\tBH_JournalHead = 23,\n\tBH_Shadow = 24,\n\tBH_Verified = 25,\n\tBH_JBDPrivateStart = 26,\n};\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_DMA = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_CGROUP = 2,\n\tNR_KMALLOC_TYPES = 3,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum label_id {\n\tlabel_clear_nopref = 1,\n\tlabel_clear_pref = 2,\n\tlabel_copy_nopref = 3,\n\tlabel_copy_pref_both = 4,\n\tlabel_copy_pref_store = 5,\n};\n\nenum label_id___2 {\n\tlabel_second_part = 1,\n\tlabel_leave = 2,\n\tlabel_vmalloc = 3,\n\tlabel_vmalloc_done = 4,\n\tlabel_tlbw_hazard_0 = 5,\n\tlabel_split = 13,\n\tlabel_tlbl_goaround1 = 14,\n\tlabel_tlbl_goaround2 = 15,\n\tlabel_nopage_tlbl = 16,\n\tlabel_nopage_tlbs = 17,\n\tlabel_nopage_tlbm = 18,\n\tlabel_smp_pgtable_change = 19,\n\tlabel_r3000_write_probe_fail = 20,\n\tlabel_large_segbits_fault = 21,\n};\n\nenum label_id___3 {\n\tlabel_not_nmi = 1,\n};\n\nenum layoutdriver_policy_flags {\n\tPNFS_LAYOUTRET_ON_SETATTR = 1,\n\tPNFS_LAYOUTRET_ON_ERROR = 2,\n\tPNFS_READ_WHOLE_PAGE = 4,\n\tPNFS_LAYOUTGET_ON_OPEN = 8,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum led_default_state {\n\tLEDS_DEFSTATE_OFF = 0,\n\tLEDS_DEFSTATE_ON = 1,\n\tLEDS_DEFSTATE_KEEP = 2,\n};\n\nenum led_trigger_netdev_modes {\n\tTRIGGER_NETDEV_LINK = 0,\n\tTRIGGER_NETDEV_LINK_10 = 1,\n\tTRIGGER_NETDEV_LINK_100 = 2,\n\tTRIGGER_NETDEV_LINK_1000 = 3,\n\tTRIGGER_NETDEV_LINK_2500 = 4,\n\tTRIGGER_NETDEV_LINK_5000 = 5,\n\tTRIGGER_NETDEV_LINK_10000 = 6,\n\tTRIGGER_NETDEV_HALF_DUPLEX = 7,\n\tTRIGGER_NETDEV_FULL_DUPLEX = 8,\n\tTRIGGER_NETDEV_TX = 9,\n\tTRIGGER_NETDEV_RX = 10,\n\tTRIGGER_NETDEV_TX_ERR = 11,\n\tTRIGGER_NETDEV_RX_ERR = 12,\n\t__TRIGGER_NETDEV_MAX = 13,\n};\n\nenum limit_by4 {\n\tNFS4_LIMIT_SIZE = 1,\n\tNFS4_LIMIT_BLOCKS = 2,\n};\n\nenum linedisp_map_type {\n\tLINEDISP_MAP_SEG7 = 0,\n\tLINEDISP_MAP_SEG14 = 1,\n};\n\nenum link_inband_signalling {\n\tLINK_INBAND_DISABLE = 1,\n\tLINK_INBAND_ENABLE = 2,\n\tLINK_INBAND_BYPASS = 4,\n};\n\nenum lock_type4 {\n\tNFS4_UNLOCK_LT = 0,\n\tNFS4_READ_LT = 1,\n\tNFS4_WRITE_LT = 2,\n\tNFS4_READW_LT = 3,\n\tNFS4_WRITEW_LT = 4,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lx_func {\n\tlwx_op = 0,\n\tlhx_op = 4,\n\tlbux_op = 6,\n\tldx_op = 8,\n\tlwux_op = 16,\n\tlhux_op = 20,\n\tlbx_op = 22,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum macaccess_entry_type {\n\tENTRYTYPE_NORMAL = 0,\n\tENTRYTYPE_LOCKED = 1,\n\tENTRYTYPE_MACv4 = 2,\n\tENTRYTYPE_MACv6 = 3,\n};\n\nenum maddf_flags {\n\tMADDF_NEGATE_PRODUCT = 1,\n\tMADDF_NEGATE_ADDITION = 2,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum major_op {\n\tspec_op = 0,\n\tbcond_op = 1,\n\tj_op = 2,\n\tjal_op = 3,\n\tbeq_op = 4,\n\tbne_op = 5,\n\tblez_op = 6,\n\tbgtz_op = 7,\n\taddi_op = 8,\n\tpop10_op = 8,\n\taddiu_op = 9,\n\tslti_op = 10,\n\tsltiu_op = 11,\n\tandi_op = 12,\n\tori_op = 13,\n\txori_op = 14,\n\tlui_op = 15,\n\tcop0_op = 16,\n\tcop1_op = 17,\n\tcop2_op = 18,\n\tcop1x_op = 19,\n\tbeql_op = 20,\n\tbnel_op = 21,\n\tblezl_op = 22,\n\tbgtzl_op = 23,\n\tdaddi_op = 24,\n\tpop30_op = 24,\n\tdaddiu_op = 25,\n\tldl_op = 26,\n\tldr_op = 27,\n\tspec2_op = 28,\n\tjalx_op = 29,\n\tmdmx_op = 30,\n\tmsa_op = 30,\n\tspec3_op = 31,\n\tlb_op = 32,\n\tlh_op = 33,\n\tlwl_op = 34,\n\tlw_op = 35,\n\tlbu_op = 36,\n\tlhu_op = 37,\n\tlwr_op = 38,\n\tlwu_op = 39,\n\tsb_op = 40,\n\tsh_op = 41,\n\tswl_op = 42,\n\tsw_op = 43,\n\tsdl_op = 44,\n\tsdr_op = 45,\n\tswr_op = 46,\n\tcache_op = 47,\n\tll_op = 48,\n\tlwc1_op = 49,\n\tlwc2_op = 50,\n\tbc6_op = 50,\n\tpref_op = 51,\n\tlld_op = 52,\n\tldc1_op = 53,\n\tldc2_op = 54,\n\tpop66_op = 54,\n\tld_op = 55,\n\tsc_op = 56,\n\tswc1_op = 57,\n\tswc2_op = 58,\n\tbalc6_op = 58,\n\tmajor_3b_op = 59,\n\tscd_op = 60,\n\tsdc1_op = 61,\n\tsdc2_op = 62,\n\tpop76_op = 62,\n\tsd_op = 63,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum mctrl_gpio_idx {\n\tUART_GPIO_CTS = 0,\n\tUART_GPIO_DSR = 1,\n\tUART_GPIO_DCD = 2,\n\tUART_GPIO_RNG = 3,\n\tUART_GPIO_RI = 3,\n\tUART_GPIO_RTS = 4,\n\tUART_GPIO_DTR = 5,\n\tUART_GPIO_MAX = 6,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 46,\n\tMEMCG_SOCK = 47,\n\tMEMCG_PERCPU_B = 48,\n\tMEMCG_VMALLOC = 49,\n\tMEMCG_KMEM = 50,\n\tMEMCG_ZSWAP_B = 51,\n\tMEMCG_ZSWAPPED = 52,\n\tMEMCG_NR_STAT = 53,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mext_move_type {\n\tMEXT_SKIP_EXTENT = 0,\n\tMEXT_MOVE_EXTENT = 1,\n\tMEXT_COPY_DATA = 2,\n};\n\nenum mfill_atomic_mode {\n\tMFILL_ATOMIC_COPY = 0,\n\tMFILL_ATOMIC_ZEROPAGE = 1,\n\tMFILL_ATOMIC_CONTINUE = 2,\n\tMFILL_ATOMIC_POISON = 3,\n\tNR_MFILL_ATOMIC_MODES = 4,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\t__MIGRATE_TYPE_END = 3,\n\tMIGRATE_TYPES = 4,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum mips_gic_local_interrupt {\n\tGIC_LOCAL_INT_WD = 0,\n\tGIC_LOCAL_INT_COMPARE = 1,\n\tGIC_LOCAL_INT_TIMER = 2,\n\tGIC_LOCAL_INT_PERFCTR = 3,\n\tGIC_LOCAL_INT_SWINT0 = 4,\n\tGIC_LOCAL_INT_SWINT1 = 5,\n\tGIC_LOCAL_INT_FDC = 6,\n\tGIC_NUM_LOCAL_INTRS = 7,\n};\n\nenum mips_regset {\n\tREGSET_GPR = 0,\n\tREGSET_DSP = 1,\n\tREGSET_FPR = 2,\n\tREGSET_FP_MODE = 3,\n};\n\nenum mm_16c_minor_op {\n\tmm_lwm16_op = 4,\n\tmm_swm16_op = 5,\n\tmm_jr16_op = 12,\n\tmm_jrc_op = 13,\n\tmm_jalr16_op = 14,\n\tmm_jalrs16_op = 15,\n\tmm_jraddiusp_op = 24,\n};\n\nenum mm_32a_minor_op {\n\tmm_sll32_op = 0,\n\tmm_ins_op = 12,\n\tmm_sllv32_op = 16,\n\tmm_ext_op = 44,\n\tmm_pool32axf_op = 60,\n\tmm_srl32_op = 64,\n\tmm_srlv32_op = 80,\n\tmm_sra_op = 128,\n\tmm_srav_op = 144,\n\tmm_rotr_op = 192,\n\tmm_lwxs_op = 280,\n\tmm_addu32_op = 336,\n\tmm_subu32_op = 464,\n\tmm_wsbh_op = 492,\n\tmm_mul_op = 528,\n\tmm_and_op = 592,\n\tmm_or32_op = 656,\n\tmm_xor32_op = 784,\n\tmm_slt_op = 848,\n\tmm_sltu_op = 912,\n};\n\nenum mm_32axf_minor_op {\n\tmm_mfc0_op = 3,\n\tmm_mtc0_op = 11,\n\tmm_tlbp_op = 13,\n\tmm_mfhi32_op = 53,\n\tmm_jalr_op = 60,\n\tmm_tlbr_op = 77,\n\tmm_mflo32_op = 117,\n\tmm_jalrhb_op = 124,\n\tmm_tlbwi_op = 141,\n\tmm_mthi32_op = 181,\n\tmm_tlbwr_op = 205,\n\tmm_mtlo32_op = 245,\n\tmm_di_op = 285,\n\tmm_jalrs_op = 316,\n\tmm_jalrshb_op = 380,\n\tmm_sync_op = 429,\n\tmm_syscall_op = 557,\n\tmm_wait_op = 589,\n\tmm_eret_op = 973,\n\tmm_divu_op = 1500,\n};\n\nenum mm_32b_func {\n\tmm_lwc2_func = 0,\n\tmm_lwp_func = 1,\n\tmm_ldc2_func = 2,\n\tmm_ldp_func = 4,\n\tmm_lwm32_func = 5,\n\tmm_cache_func = 6,\n\tmm_ldm_func = 7,\n\tmm_swc2_func = 8,\n\tmm_swp_func = 9,\n\tmm_sdc2_func = 10,\n\tmm_sdp_func = 12,\n\tmm_swm32_func = 13,\n\tmm_sdm_func = 15,\n};\n\nenum mm_32c_func {\n\tmm_pref_func = 2,\n\tmm_ll_func = 3,\n\tmm_swr_func = 9,\n\tmm_sc_func = 11,\n\tmm_lwu_func = 14,\n};\n\nenum mm_32f_10_minor_op {\n\tmm_lwxc1_op = 1,\n\tmm_swxc1_op = 2,\n\tmm_ldxc1_op = 3,\n\tmm_sdxc1_op = 4,\n\tmm_luxc1_op = 5,\n\tmm_suxc1_op = 6,\n};\n\nenum mm_32f_40_minor_op {\n\tmm_fmovf_op = 0,\n\tmm_fmovt_op = 1,\n};\n\nenum mm_32f_60_minor_op {\n\tmm_fadd_op = 0,\n\tmm_fsub_op = 1,\n\tmm_fmul_op = 2,\n\tmm_fdiv_op = 3,\n};\n\nenum mm_32f_70_minor_op {\n\tmm_fmovn_op = 0,\n\tmm_fmovz_op = 1,\n};\n\nenum mm_32f_73_minor_op {\n\tmm_fmov0_op = 1,\n\tmm_fcvtl_op = 4,\n\tmm_movf0_op = 5,\n\tmm_frsqrt_op = 8,\n\tmm_ffloorl_op = 12,\n\tmm_fabs0_op = 13,\n\tmm_fcvtw_op = 36,\n\tmm_movt0_op = 37,\n\tmm_fsqrt_op = 40,\n\tmm_ffloorw_op = 44,\n\tmm_fneg0_op = 45,\n\tmm_cfc1_op = 64,\n\tmm_frecip_op = 72,\n\tmm_fceill_op = 76,\n\tmm_fcvtd0_op = 77,\n\tmm_ctc1_op = 96,\n\tmm_fceilw_op = 108,\n\tmm_fcvts0_op = 109,\n\tmm_mfc1_op = 128,\n\tmm_fmov1_op = 129,\n\tmm_movf1_op = 133,\n\tmm_ftruncl_op = 140,\n\tmm_fabs1_op = 141,\n\tmm_mtc1_op = 160,\n\tmm_movt1_op = 165,\n\tmm_ftruncw_op = 172,\n\tmm_fneg1_op = 173,\n\tmm_mfhc1_op = 192,\n\tmm_froundl_op = 204,\n\tmm_fcvtd1_op = 205,\n\tmm_mthc1_op = 224,\n\tmm_froundw_op = 236,\n\tmm_fcvts1_op = 237,\n};\n\nenum mm_32f_func {\n\tmm_lwxc1_func = 72,\n\tmm_swxc1_func = 136,\n\tmm_ldxc1_func = 200,\n\tmm_sdxc1_func = 264,\n};\n\nenum mm_32f_minor_op {\n\tmm_32f_00_op = 0,\n\tmm_32f_01_op = 1,\n\tmm_32f_02_op = 2,\n\tmm_32f_10_op = 8,\n\tmm_32f_11_op = 9,\n\tmm_32f_12_op = 10,\n\tmm_32f_20_op = 16,\n\tmm_32f_30_op = 24,\n\tmm_32f_40_op = 32,\n\tmm_32f_41_op = 33,\n\tmm_32f_42_op = 34,\n\tmm_32f_50_op = 40,\n\tmm_32f_51_op = 41,\n\tmm_32f_52_op = 42,\n\tmm_32f_60_op = 48,\n\tmm_32f_70_op = 56,\n\tmm_32f_73_op = 59,\n\tmm_32f_74_op = 60,\n};\n\nenum mm_32i_minor_op {\n\tmm_bltz_op = 0,\n\tmm_bltzal_op = 1,\n\tmm_bgez_op = 2,\n\tmm_bgezal_op = 3,\n\tmm_blez_op = 4,\n\tmm_bnezc_op = 5,\n\tmm_bgtz_op = 6,\n\tmm_beqzc_op = 7,\n\tmm_tlti_op = 8,\n\tmm_tgei_op = 9,\n\tmm_tltiu_op = 10,\n\tmm_tgeiu_op = 11,\n\tmm_tnei_op = 12,\n\tmm_lui_op = 13,\n\tmm_teqi_op = 14,\n\tmm_reserved13_op = 15,\n\tmm_synci_op = 16,\n\tmm_bltzals_op = 17,\n\tmm_reserved14_op = 18,\n\tmm_bgezals_op = 19,\n\tmm_bc2f_op = 20,\n\tmm_bc2t_op = 21,\n\tmm_reserved15_op = 22,\n\tmm_reserved16_op = 23,\n\tmm_reserved17_op = 24,\n\tmm_reserved18_op = 25,\n\tmm_bposge64_op = 26,\n\tmm_bposge32_op = 27,\n\tmm_bc1f_op = 28,\n\tmm_bc1t_op = 29,\n\tmm_reserved19_op = 30,\n\tmm_reserved20_op = 31,\n\tmm_bc1any2f_op = 32,\n\tmm_bc1any2t_op = 33,\n\tmm_bc1any4f_op = 34,\n\tmm_bc1any4t_op = 35,\n};\n\nenum mm_major_op {\n\tmm_pool32a_op = 0,\n\tmm_pool16a_op = 1,\n\tmm_lbu16_op = 2,\n\tmm_move16_op = 3,\n\tmm_addi32_op = 4,\n\tmm_lbu32_op = 5,\n\tmm_sb32_op = 6,\n\tmm_lb32_op = 7,\n\tmm_pool32b_op = 8,\n\tmm_pool16b_op = 9,\n\tmm_lhu16_op = 10,\n\tmm_andi16_op = 11,\n\tmm_addiu32_op = 12,\n\tmm_lhu32_op = 13,\n\tmm_sh32_op = 14,\n\tmm_lh32_op = 15,\n\tmm_pool32i_op = 16,\n\tmm_pool16c_op = 17,\n\tmm_lwsp16_op = 18,\n\tmm_pool16d_op = 19,\n\tmm_ori32_op = 20,\n\tmm_pool32f_op = 21,\n\tmm_pool32s_op = 22,\n\tmm_reserved2_op = 23,\n\tmm_pool32c_op = 24,\n\tmm_lwgp16_op = 25,\n\tmm_lw16_op = 26,\n\tmm_pool16e_op = 27,\n\tmm_xori32_op = 28,\n\tmm_jals32_op = 29,\n\tmm_addiupc_op = 30,\n\tmm_reserved3_op = 31,\n\tmm_reserved4_op = 32,\n\tmm_pool16f_op = 33,\n\tmm_sb16_op = 34,\n\tmm_beqz16_op = 35,\n\tmm_slti32_op = 36,\n\tmm_beq32_op = 37,\n\tmm_swc132_op = 38,\n\tmm_lwc132_op = 39,\n\tmm_reserved5_op = 40,\n\tmm_reserved6_op = 41,\n\tmm_sh16_op = 42,\n\tmm_bnez16_op = 43,\n\tmm_sltiu32_op = 44,\n\tmm_bne32_op = 45,\n\tmm_sdc132_op = 46,\n\tmm_ldc132_op = 47,\n\tmm_reserved7_op = 48,\n\tmm_reserved8_op = 49,\n\tmm_swsp16_op = 50,\n\tmm_b16_op = 51,\n\tmm_andi32_op = 52,\n\tmm_j32_op = 53,\n\tmm_sd32_op = 54,\n\tmm_ld32_op = 55,\n\tmm_reserved11_op = 56,\n\tmm_reserved12_op = 57,\n\tmm_sw16_op = 58,\n\tmm_li16_op = 59,\n\tmm_jalx32_op = 60,\n\tmm_jal32_op = 61,\n\tmm_sw32_op = 62,\n\tmm_lw32_op = 63,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mmap_allocation_direction {\n\tUP = 0,\n\tDOWN = 1,\n};\n\nenum mmc_busy_cmd {\n\tMMC_BUSY_CMD6 = 0,\n\tMMC_BUSY_ERASE = 1,\n\tMMC_BUSY_HPI = 2,\n\tMMC_BUSY_EXTR_SINGLE = 3,\n\tMMC_BUSY_IO = 4,\n};\n\nenum mmc_drv_op {\n\tMMC_DRV_OP_IOCTL = 0,\n\tMMC_DRV_OP_IOCTL_RPMB = 1,\n\tMMC_DRV_OP_BOOT_WP = 2,\n\tMMC_DRV_OP_GET_CARD_STATUS = 3,\n\tMMC_DRV_OP_GET_EXT_CSD = 4,\n};\n\nenum mmc_err_stat {\n\tMMC_ERR_CMD_TIMEOUT = 0,\n\tMMC_ERR_CMD_CRC = 1,\n\tMMC_ERR_DAT_TIMEOUT = 2,\n\tMMC_ERR_DAT_CRC = 3,\n\tMMC_ERR_AUTO_CMD = 4,\n\tMMC_ERR_ADMA = 5,\n\tMMC_ERR_TUNING = 6,\n\tMMC_ERR_CMDQ_RED = 7,\n\tMMC_ERR_CMDQ_GCE = 8,\n\tMMC_ERR_CMDQ_ICCE = 9,\n\tMMC_ERR_REQ_TIMEOUT = 10,\n\tMMC_ERR_CMDQ_REQ_TIMEOUT = 11,\n\tMMC_ERR_ICE_CFG = 12,\n\tMMC_ERR_CTRL_TIMEOUT = 13,\n\tMMC_ERR_UNEXPECTED_IRQ = 14,\n\tMMC_ERR_MAX = 15,\n};\n\nenum mmc_issue_type {\n\tMMC_ISSUE_SYNC = 0,\n\tMMC_ISSUE_DCMD = 1,\n\tMMC_ISSUE_ASYNC = 2,\n\tMMC_ISSUE_MAX = 3,\n};\n\nenum mmc_issued {\n\tMMC_REQ_STARTED = 0,\n\tMMC_REQ_BUSY = 1,\n\tMMC_REQ_FAILED_TO_START = 2,\n\tMMC_REQ_FINISHED = 3,\n};\n\nenum mmc_poweroff_type {\n\tMMC_POWEROFF_SUSPEND = 0,\n\tMMC_POWEROFF_SHUTDOWN = 1,\n\tMMC_POWEROFF_UNDERVOLTAGE = 2,\n\tMMC_POWEROFF_UNBIND = 3,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mountstat {\n\tMNT_OK = 0,\n\tMNT_EPERM = 1,\n\tMNT_ENOENT = 2,\n\tMNT_EACCES = 13,\n\tMNT_EINVAL = 22,\n};\n\nenum mountstat3 {\n\tMNT3_OK = 0,\n\tMNT3ERR_PERM = 1,\n\tMNT3ERR_NOENT = 2,\n\tMNT3ERR_IO = 5,\n\tMNT3ERR_ACCES = 13,\n\tMNT3ERR_NOTDIR = 20,\n\tMNT3ERR_INVAL = 22,\n\tMNT3ERR_NAMETOOLONG = 63,\n\tMNT3ERR_NOTSUPP = 10004,\n\tMNT3ERR_SERVERFAULT = 10006,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum msa_elm {\n\tmsa_ctc_op = 62,\n\tmsa_cfc_op = 126,\n};\n\nenum msa_func {\n\tmsa_elm_op = 25,\n};\n\nenum mscc_qos_rate_mode {\n\tMSCC_QOS_RATE_MODE_DISABLED = 0,\n\tMSCC_QOS_RATE_MODE_LINE = 1,\n\tMSCC_QOS_RATE_MODE_DATA = 2,\n\tMSCC_QOS_RATE_MODE_FRAME = 3,\n\t__MSCC_QOS_RATE_MODE_END = 4,\n\tNUM_MSCC_QOS_RATE_MODE = 4,\n\tMSCC_QOS_RATE_MODE_MAX = 3,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum mtd_file_modes {\n\tMTD_FILE_MODE_NORMAL = 0,\n\tMTD_FILE_MODE_OTP_FACTORY = 1,\n\tMTD_FILE_MODE_OTP_USER = 2,\n\tMTD_FILE_MODE_RAW = 3,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum multu_op {\n\tmultu_multu_op = 0,\n\tmultu_mulu_op = 2,\n\tmultu_muhu_op = 3,\n};\n\nenum nand_bbt_block_status {\n\tNAND_BBT_BLOCK_STATUS_UNKNOWN = 0,\n\tNAND_BBT_BLOCK_GOOD = 1,\n\tNAND_BBT_BLOCK_WORN = 2,\n\tNAND_BBT_BLOCK_RESERVED = 3,\n\tNAND_BBT_BLOCK_FACTORY_BAD = 4,\n\tNAND_BBT_BLOCK_NUM_STATUS = 5,\n};\n\nenum nand_ecc_algo {\n\tNAND_ECC_ALGO_UNKNOWN = 0,\n\tNAND_ECC_ALGO_HAMMING = 1,\n\tNAND_ECC_ALGO_BCH = 2,\n\tNAND_ECC_ALGO_RS = 3,\n};\n\nenum nand_ecc_engine_integration {\n\tNAND_ECC_ENGINE_INTEGRATION_INVALID = 0,\n\tNAND_ECC_ENGINE_INTEGRATION_PIPELINED = 1,\n\tNAND_ECC_ENGINE_INTEGRATION_EXTERNAL = 2,\n};\n\nenum nand_ecc_engine_type {\n\tNAND_ECC_ENGINE_TYPE_INVALID = 0,\n\tNAND_ECC_ENGINE_TYPE_NONE = 1,\n\tNAND_ECC_ENGINE_TYPE_SOFT = 2,\n\tNAND_ECC_ENGINE_TYPE_ON_HOST = 3,\n\tNAND_ECC_ENGINE_TYPE_ON_DIE = 4,\n};\n\nenum nand_ecc_legacy_mode {\n\tNAND_ECC_INVALID = 0,\n\tNAND_ECC_NONE = 1,\n\tNAND_ECC_SOFT = 2,\n\tNAND_ECC_SOFT_BCH = 3,\n\tNAND_ECC_HW = 4,\n\tNAND_ECC_HW_SYNDROME = 5,\n\tNAND_ECC_ON_DIE = 6,\n};\n\nenum nand_ecc_placement {\n\tNAND_ECC_PLACEMENT_UNKNOWN = 0,\n\tNAND_ECC_PLACEMENT_OOB = 1,\n\tNAND_ECC_PLACEMENT_INTERLEAVED = 2,\n};\n\nenum nand_interface_type {\n\tNAND_SDR_IFACE = 0,\n\tNAND_NVDDR_IFACE = 1,\n};\n\nenum nand_op_instr_type {\n\tNAND_OP_CMD_INSTR = 0,\n\tNAND_OP_ADDR_INSTR = 1,\n\tNAND_OP_DATA_IN_INSTR = 2,\n\tNAND_OP_DATA_OUT_INSTR = 3,\n\tNAND_OP_WAITRDY_INSTR = 4,\n};\n\nenum nand_page_io_req_type {\n\tNAND_PAGE_READ = 0,\n\tNAND_PAGE_WRITE = 1,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum net_bridge_opts {\n\tBROPT_VLAN_ENABLED = 0,\n\tBROPT_VLAN_STATS_ENABLED = 1,\n\tBROPT_NF_CALL_IPTABLES = 2,\n\tBROPT_NF_CALL_IP6TABLES = 3,\n\tBROPT_NF_CALL_ARPTABLES = 4,\n\tBROPT_GROUP_ADDR_SET = 5,\n\tBROPT_MULTICAST_ENABLED = 6,\n\tBROPT_MULTICAST_QUERY_USE_IFADDR = 7,\n\tBROPT_MULTICAST_STATS_ENABLED = 8,\n\tBROPT_HAS_IPV6_ADDR = 9,\n\tBROPT_NEIGH_SUPPRESS_ENABLED = 10,\n\tBROPT_MTU_SET_BY_USER = 11,\n\tBROPT_VLAN_STATS_PER_PORT = 12,\n\tBROPT_NO_LL_LEARN = 13,\n\tBROPT_VLAN_BRIDGE_BINDING = 14,\n\tBROPT_MCAST_VLAN_SNOOPING_ENABLED = 15,\n\tBROPT_MST_ENABLED = 16,\n\tBROPT_MDB_OFFLOAD_FAIL_NOTIFICATION = 17,\n\tBROPT_FDB_LOCAL_VLAN_0 = 18,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_lag_hash {\n\tNETDEV_LAG_HASH_NONE = 0,\n\tNETDEV_LAG_HASH_L2 = 1,\n\tNETDEV_LAG_HASH_L34 = 2,\n\tNETDEV_LAG_HASH_L23 = 3,\n\tNETDEV_LAG_HASH_E23 = 4,\n\tNETDEV_LAG_HASH_E34 = 5,\n\tNETDEV_LAG_HASH_VLAN_SRCMAC = 6,\n\tNETDEV_LAG_HASH_UNKNOWN = 7,\n};\n\nenum netdev_lag_tx_type {\n\tNETDEV_LAG_TX_TYPE_UNKNOWN = 0,\n\tNETDEV_LAG_TX_TYPE_RANDOM = 1,\n\tNETDEV_LAG_TX_TYPE_BROADCAST = 2,\n\tNETDEV_LAG_TX_TYPE_ROUNDROBIN = 3,\n\tNETDEV_LAG_TX_TYPE_ACTIVEBACKUP = 4,\n\tNETDEV_LAG_TX_TYPE_HASH = 5,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netfs_failure {\n\tnetfs_fail_check_write_begin = 0,\n\tnetfs_fail_copy_to_cache = 1,\n\tnetfs_fail_dio_read_short = 2,\n\tnetfs_fail_dio_read_zero = 3,\n\tnetfs_fail_read = 4,\n\tnetfs_fail_short_read = 5,\n\tnetfs_fail_prepare_write = 6,\n\tnetfs_fail_write = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_folio_trace {\n\tnetfs_folio_is_uptodate = 0,\n\tnetfs_just_prefetch = 1,\n\tnetfs_whole_folio_modify = 2,\n\tnetfs_modify_and_clear = 3,\n\tnetfs_streaming_write = 4,\n\tnetfs_streaming_write_cont = 5,\n\tnetfs_flush_content = 6,\n\tnetfs_streaming_filled_page = 7,\n\tnetfs_streaming_cont_filled_page = 8,\n\tnetfs_folio_trace_abandon = 9,\n\tnetfs_folio_trace_alloc_buffer = 10,\n\tnetfs_folio_trace_cancel_copy = 11,\n\tnetfs_folio_trace_cancel_store = 12,\n\tnetfs_folio_trace_clear = 13,\n\tnetfs_folio_trace_clear_cc = 14,\n\tnetfs_folio_trace_clear_g = 15,\n\tnetfs_folio_trace_clear_s = 16,\n\tnetfs_folio_trace_copy_to_cache = 17,\n\tnetfs_folio_trace_end_copy = 18,\n\tnetfs_folio_trace_filled_gaps = 19,\n\tnetfs_folio_trace_kill = 20,\n\tnetfs_folio_trace_kill_cc = 21,\n\tnetfs_folio_trace_kill_g = 22,\n\tnetfs_folio_trace_kill_s = 23,\n\tnetfs_folio_trace_mkwrite = 24,\n\tnetfs_folio_trace_mkwrite_plus = 25,\n\tnetfs_folio_trace_not_under_wback = 26,\n\tnetfs_folio_trace_not_locked = 27,\n\tnetfs_folio_trace_put = 28,\n\tnetfs_folio_trace_read = 29,\n\tnetfs_folio_trace_read_done = 30,\n\tnetfs_folio_trace_read_gaps = 31,\n\tnetfs_folio_trace_read_unlock = 32,\n\tnetfs_folio_trace_redirtied = 33,\n\tnetfs_folio_trace_store = 34,\n\tnetfs_folio_trace_store_copy = 35,\n\tnetfs_folio_trace_store_plus = 36,\n\tnetfs_folio_trace_wthru = 37,\n\tnetfs_folio_trace_wthru_plus = 38,\n} __attribute__((mode(byte)));\n\nenum netfs_folioq_trace {\n\tnetfs_trace_folioq_alloc_buffer = 0,\n\tnetfs_trace_folioq_clear = 1,\n\tnetfs_trace_folioq_delete = 2,\n\tnetfs_trace_folioq_make_space = 3,\n\tnetfs_trace_folioq_rollbuf_init = 4,\n\tnetfs_trace_folioq_read_progress = 5,\n} __attribute__((mode(byte)));\n\nenum netfs_io_origin {\n\tNETFS_READAHEAD = 0,\n\tNETFS_READPAGE = 1,\n\tNETFS_READ_GAPS = 2,\n\tNETFS_READ_SINGLE = 3,\n\tNETFS_READ_FOR_WRITE = 4,\n\tNETFS_UNBUFFERED_READ = 5,\n\tNETFS_DIO_READ = 6,\n\tNETFS_WRITEBACK = 7,\n\tNETFS_WRITEBACK_SINGLE = 8,\n\tNETFS_WRITETHROUGH = 9,\n\tNETFS_UNBUFFERED_WRITE = 10,\n\tNETFS_DIO_WRITE = 11,\n\tNETFS_PGPRIV2_COPY_TO_CACHE = 12,\n\tnr__netfs_io_origin = 13,\n} __attribute__((mode(byte)));\n\nenum netfs_io_source {\n\tNETFS_SOURCE_UNKNOWN = 0,\n\tNETFS_FILL_WITH_ZEROES = 1,\n\tNETFS_DOWNLOAD_FROM_SERVER = 2,\n\tNETFS_READ_FROM_CACHE = 3,\n\tNETFS_INVALID_READ = 4,\n\tNETFS_UPLOAD_TO_SERVER = 5,\n\tNETFS_WRITE_TO_CACHE = 6,\n} __attribute__((mode(byte)));\n\nenum netfs_read_from_hole {\n\tNETFS_READ_HOLE_IGNORE = 0,\n\tNETFS_READ_HOLE_FAIL = 1,\n};\n\nenum netfs_read_trace {\n\tnetfs_read_trace_dio_read = 0,\n\tnetfs_read_trace_expanded = 1,\n\tnetfs_read_trace_readahead = 2,\n\tnetfs_read_trace_readpage = 3,\n\tnetfs_read_trace_read_gaps = 4,\n\tnetfs_read_trace_read_single = 5,\n\tnetfs_read_trace_prefetch_for_write = 6,\n\tnetfs_read_trace_write_begin = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_ref_trace {\n\tnetfs_rreq_trace_get_for_outstanding = 0,\n\tnetfs_rreq_trace_get_subreq = 1,\n\tnetfs_rreq_trace_put_complete = 2,\n\tnetfs_rreq_trace_put_discard = 3,\n\tnetfs_rreq_trace_put_failed = 4,\n\tnetfs_rreq_trace_put_no_submit = 5,\n\tnetfs_rreq_trace_put_return = 6,\n\tnetfs_rreq_trace_put_subreq = 7,\n\tnetfs_rreq_trace_put_work_ip = 8,\n\tnetfs_rreq_trace_see_work = 9,\n\tnetfs_rreq_trace_see_work_complete = 10,\n\tnetfs_rreq_trace_new = 11,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_trace {\n\tnetfs_rreq_trace_assess = 0,\n\tnetfs_rreq_trace_collect = 1,\n\tnetfs_rreq_trace_complete = 2,\n\tnetfs_rreq_trace_copy = 3,\n\tnetfs_rreq_trace_dirty = 4,\n\tnetfs_rreq_trace_done = 5,\n\tnetfs_rreq_trace_end_copy_to_cache = 6,\n\tnetfs_rreq_trace_free = 7,\n\tnetfs_rreq_trace_intr = 8,\n\tnetfs_rreq_trace_ki_complete = 9,\n\tnetfs_rreq_trace_recollect = 10,\n\tnetfs_rreq_trace_redirty = 11,\n\tnetfs_rreq_trace_resubmit = 12,\n\tnetfs_rreq_trace_set_abandon = 13,\n\tnetfs_rreq_trace_set_pause = 14,\n\tnetfs_rreq_trace_unlock = 15,\n\tnetfs_rreq_trace_unlock_pgpriv2 = 16,\n\tnetfs_rreq_trace_unmark = 17,\n\tnetfs_rreq_trace_unpause = 18,\n\tnetfs_rreq_trace_wait_ip = 19,\n\tnetfs_rreq_trace_wait_pause = 20,\n\tnetfs_rreq_trace_wait_quiesce = 21,\n\tnetfs_rreq_trace_waited_ip = 22,\n\tnetfs_rreq_trace_waited_pause = 23,\n\tnetfs_rreq_trace_waited_quiesce = 24,\n\tnetfs_rreq_trace_wake_ip = 25,\n\tnetfs_rreq_trace_wake_queue = 26,\n\tnetfs_rreq_trace_write_done = 27,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_ref_trace {\n\tnetfs_sreq_trace_get_copy_to_cache = 0,\n\tnetfs_sreq_trace_get_resubmit = 1,\n\tnetfs_sreq_trace_get_submit = 2,\n\tnetfs_sreq_trace_get_short_read = 3,\n\tnetfs_sreq_trace_new = 4,\n\tnetfs_sreq_trace_put_abandon = 5,\n\tnetfs_sreq_trace_put_cancel = 6,\n\tnetfs_sreq_trace_put_clear = 7,\n\tnetfs_sreq_trace_put_consumed = 8,\n\tnetfs_sreq_trace_put_done = 9,\n\tnetfs_sreq_trace_put_failed = 10,\n\tnetfs_sreq_trace_put_merged = 11,\n\tnetfs_sreq_trace_put_no_copy = 12,\n\tnetfs_sreq_trace_put_oom = 13,\n\tnetfs_sreq_trace_put_wip = 14,\n\tnetfs_sreq_trace_put_work = 15,\n\tnetfs_sreq_trace_put_terminated = 16,\n\tnetfs_sreq_trace_see_failed = 17,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_trace {\n\tnetfs_sreq_trace_abandoned = 0,\n\tnetfs_sreq_trace_add_donations = 1,\n\tnetfs_sreq_trace_added = 2,\n\tnetfs_sreq_trace_cache_nowrite = 3,\n\tnetfs_sreq_trace_cache_prepare = 4,\n\tnetfs_sreq_trace_cache_write = 5,\n\tnetfs_sreq_trace_cancel = 6,\n\tnetfs_sreq_trace_clear = 7,\n\tnetfs_sreq_trace_consumed = 8,\n\tnetfs_sreq_trace_discard = 9,\n\tnetfs_sreq_trace_donate_to_prev = 10,\n\tnetfs_sreq_trace_donate_to_next = 11,\n\tnetfs_sreq_trace_download_instead = 12,\n\tnetfs_sreq_trace_fail = 13,\n\tnetfs_sreq_trace_free = 14,\n\tnetfs_sreq_trace_hit_eof = 15,\n\tnetfs_sreq_trace_io_bad = 16,\n\tnetfs_sreq_trace_io_malformed = 17,\n\tnetfs_sreq_trace_io_unknown = 18,\n\tnetfs_sreq_trace_io_progress = 19,\n\tnetfs_sreq_trace_io_req_submitted = 20,\n\tnetfs_sreq_trace_io_retry_needed = 21,\n\tnetfs_sreq_trace_limited = 22,\n\tnetfs_sreq_trace_need_clear = 23,\n\tnetfs_sreq_trace_partial_read = 24,\n\tnetfs_sreq_trace_need_retry = 25,\n\tnetfs_sreq_trace_prepare = 26,\n\tnetfs_sreq_trace_prep_failed = 27,\n\tnetfs_sreq_trace_progress = 28,\n\tnetfs_sreq_trace_reprep_failed = 29,\n\tnetfs_sreq_trace_retry = 30,\n\tnetfs_sreq_trace_short = 31,\n\tnetfs_sreq_trace_split = 32,\n\tnetfs_sreq_trace_submit = 33,\n\tnetfs_sreq_trace_superfluous = 34,\n\tnetfs_sreq_trace_terminated = 35,\n\tnetfs_sreq_trace_wait_for = 36,\n\tnetfs_sreq_trace_write = 37,\n\tnetfs_sreq_trace_write_skip = 38,\n\tnetfs_sreq_trace_write_term = 39,\n} __attribute__((mode(byte)));\n\nenum netfs_write_trace {\n\tnetfs_write_trace_copy_to_cache = 0,\n\tnetfs_write_trace_dio_write = 1,\n\tnetfs_write_trace_unbuffered_write = 2,\n\tnetfs_write_trace_writeback = 3,\n\tnetfs_write_trace_writeback_single = 4,\n\tnetfs_write_trace_writethrough = 5,\n} __attribute__((mode(byte)));\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netloc_type4 {\n\tNL4_NAME = 1,\n\tNL4_URL = 2,\n\tNL4_NETADDR = 3,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_dev_hooks {\n\tNF_NETDEV_INGRESS = 0,\n\tNF_NETDEV_EGRESS = 1,\n\tNF_NETDEV_NUMHOOKS = 2,\n};\n\nenum nf_hook_ops_type {\n\tNF_HOOK_OP_UNDEFINED = 0,\n\tNF_HOOK_OP_NF_TABLES = 1,\n\tNF_HOOK_OP_BPF = 2,\n\tNF_HOOK_OP_NFT_FT = 3,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nf_ip_hook_priorities {\n\tNF_IP_PRI_FIRST = -2147483648,\n\tNF_IP_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP_PRI_RAW = -300,\n\tNF_IP_PRI_SELINUX_FIRST = -225,\n\tNF_IP_PRI_CONNTRACK = -200,\n\tNF_IP_PRI_MANGLE = -150,\n\tNF_IP_PRI_NAT_DST = -100,\n\tNF_IP_PRI_FILTER = 0,\n\tNF_IP_PRI_SECURITY = 50,\n\tNF_IP_PRI_NAT_SRC = 100,\n\tNF_IP_PRI_SELINUX_LAST = 225,\n\tNF_IP_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP_PRI_CONNTRACK_CONFIRM = 2147483647,\n\tNF_IP_PRI_LAST = 2147483647,\n};\n\nenum nf_log_type {\n\tNF_LOG_TYPE_LOG = 0,\n\tNF_LOG_TYPE_ULOG = 1,\n\tNF_LOG_TYPE_MAX = 2,\n};\n\nenum nfs3_createmode {\n\tNFS3_CREATE_UNCHECKED = 0,\n\tNFS3_CREATE_GUARDED = 1,\n\tNFS3_CREATE_EXCLUSIVE = 2,\n};\n\nenum nfs3_ftype {\n\tNF3NON = 0,\n\tNF3REG = 1,\n\tNF3DIR = 2,\n\tNF3BLK = 3,\n\tNF3CHR = 4,\n\tNF3LNK = 5,\n\tNF3SOCK = 6,\n\tNF3FIFO = 7,\n\tNF3BAD = 8,\n};\n\nenum nfs3_stable_how {\n\tNFS_UNSTABLE = 0,\n\tNFS_DATA_SYNC = 1,\n\tNFS_FILE_SYNC = 2,\n\tNFS_INVALID_STABLE_HOW = -1,\n};\n\nenum nfs4_acl_type {\n\tNFS4ACL_NONE = 0,\n\tNFS4ACL_ACL = 1,\n\tNFS4ACL_DACL = 2,\n\tNFS4ACL_SACL = 3,\n};\n\nenum nfs4_callback_procnum {\n\tCB_NULL = 0,\n\tCB_COMPOUND = 1,\n};\n\nenum nfs4_change_attr_type {\n\tNFS4_CHANGE_TYPE_IS_MONOTONIC_INCR = 0,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER = 1,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER_NOPNFS = 2,\n\tNFS4_CHANGE_TYPE_IS_TIME_METADATA = 3,\n\tNFS4_CHANGE_TYPE_IS_UNDEFINED = 4,\n};\n\nenum nfs4_client_state {\n\tNFS4CLNT_MANAGER_RUNNING = 0,\n\tNFS4CLNT_CHECK_LEASE = 1,\n\tNFS4CLNT_LEASE_EXPIRED = 2,\n\tNFS4CLNT_RECLAIM_REBOOT = 3,\n\tNFS4CLNT_RECLAIM_NOGRACE = 4,\n\tNFS4CLNT_DELEGRETURN = 5,\n\tNFS4CLNT_SESSION_RESET = 6,\n\tNFS4CLNT_LEASE_CONFIRM = 7,\n\tNFS4CLNT_SERVER_SCOPE_MISMATCH = 8,\n\tNFS4CLNT_PURGE_STATE = 9,\n\tNFS4CLNT_BIND_CONN_TO_SESSION = 10,\n\tNFS4CLNT_MOVED = 11,\n\tNFS4CLNT_LEASE_MOVED = 12,\n\tNFS4CLNT_DELEGATION_EXPIRED = 13,\n\tNFS4CLNT_RUN_MANAGER = 14,\n\tNFS4CLNT_MANAGER_AVAILABLE = 15,\n\tNFS4CLNT_RECALL_RUNNING = 16,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_READ = 17,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_RW = 18,\n\tNFS4CLNT_DELEGRETURN_DELAYED = 19,\n};\n\nenum nfs4_ff_op_type {\n\tNFS4_FF_OP_LAYOUTSTATS = 0,\n\tNFS4_FF_OP_LAYOUTRETURN = 1,\n};\n\nenum nfs4_open_delegation_type4 {\n\tNFS4_OPEN_DELEGATE_NONE = 0,\n\tNFS4_OPEN_DELEGATE_READ = 1,\n\tNFS4_OPEN_DELEGATE_WRITE = 2,\n\tNFS4_OPEN_DELEGATE_NONE_EXT = 3,\n\tNFS4_OPEN_DELEGATE_READ_ATTRS_DELEG = 4,\n\tNFS4_OPEN_DELEGATE_WRITE_ATTRS_DELEG = 5,\n};\n\nenum nfs4_session_state {\n\tNFS4_SESSION_INITING = 0,\n\tNFS4_SESSION_ESTABLISHED = 1,\n};\n\nenum nfs4_setxattr_options {\n\tSETXATTR4_EITHER = 0,\n\tSETXATTR4_CREATE = 1,\n\tSETXATTR4_REPLACE = 2,\n};\n\nenum nfs4_slot_tbl_state {\n\tNFS4_SLOT_TBL_DRAINING = 0,\n};\n\nenum nfs_cb_opnum4 {\n\tOP_CB_GETATTR = 3,\n\tOP_CB_RECALL = 4,\n\tOP_CB_LAYOUTRECALL = 5,\n\tOP_CB_NOTIFY = 6,\n\tOP_CB_PUSH_DELEG = 7,\n\tOP_CB_RECALL_ANY = 8,\n\tOP_CB_RECALLABLE_OBJ_AVAIL = 9,\n\tOP_CB_RECALL_SLOT = 10,\n\tOP_CB_SEQUENCE = 11,\n\tOP_CB_WANTS_CANCELLED = 12,\n\tOP_CB_NOTIFY_LOCK = 13,\n\tOP_CB_NOTIFY_DEVICEID = 14,\n\tOP_CB_OFFLOAD = 15,\n\tOP_CB_ILLEGAL = 10044,\n};\n\nenum nfs_ftype4 {\n\tNF4BAD = 0,\n\tNF4REG = 1,\n\tNF4DIR = 2,\n\tNF4BLK = 3,\n\tNF4CHR = 4,\n\tNF4LNK = 5,\n\tNF4SOCK = 6,\n\tNF4FIFO = 7,\n\tNF4ATTRDIR = 8,\n\tNF4NAMEDATTR = 9,\n};\n\nenum nfs_lock_status {\n\tNFS_LOCK_NOT_SET = 0,\n\tNFS_LOCK_LOCK = 1,\n\tNFS_LOCK_NOLOCK = 2,\n};\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nfs_param {\n\tOpt_ac = 0,\n\tOpt_acdirmax = 1,\n\tOpt_acdirmin = 2,\n\tOpt_acl___2 = 3,\n\tOpt_acregmax = 4,\n\tOpt_acregmin = 5,\n\tOpt_actimeo = 6,\n\tOpt_addr = 7,\n\tOpt_bg = 8,\n\tOpt_bsize = 9,\n\tOpt_clientaddr = 10,\n\tOpt_cto = 11,\n\tOpt_alignwrite = 12,\n\tOpt_fatal_neterrors = 13,\n\tOpt_fg = 14,\n\tOpt_fscache = 15,\n\tOpt_fscache_flag = 16,\n\tOpt_hard = 17,\n\tOpt_intr = 18,\n\tOpt_local_lock = 19,\n\tOpt_lock = 20,\n\tOpt_lookupcache = 21,\n\tOpt_migration = 22,\n\tOpt_minorversion = 23,\n\tOpt_mountaddr = 24,\n\tOpt_mounthost = 25,\n\tOpt_mountport = 26,\n\tOpt_mountproto = 27,\n\tOpt_mountvers = 28,\n\tOpt_namelen = 29,\n\tOpt_nconnect = 30,\n\tOpt_max_connect = 31,\n\tOpt_port = 32,\n\tOpt_posix = 33,\n\tOpt_proto = 34,\n\tOpt_rdirplus = 35,\n\tOpt_rdirplus_none = 36,\n\tOpt_rdirplus_force = 37,\n\tOpt_rdma = 38,\n\tOpt_resvport = 39,\n\tOpt_retrans = 40,\n\tOpt_retry = 41,\n\tOpt_rsize = 42,\n\tOpt_sec = 43,\n\tOpt_sharecache = 44,\n\tOpt_sloppy = 45,\n\tOpt_soft = 46,\n\tOpt_softerr = 47,\n\tOpt_softreval = 48,\n\tOpt_source___2 = 49,\n\tOpt_tcp = 50,\n\tOpt_timeo = 51,\n\tOpt_trunkdiscovery = 52,\n\tOpt_udp = 53,\n\tOpt_v = 54,\n\tOpt_vers = 55,\n\tOpt_wsize = 56,\n\tOpt_write = 57,\n\tOpt_xprtsec = 58,\n\tOpt_cert_serial = 59,\n\tOpt_privkey_serial = 60,\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nenum nfs_stat_bytecounters {\n\tNFSIOS_NORMALREADBYTES = 0,\n\tNFSIOS_NORMALWRITTENBYTES = 1,\n\tNFSIOS_DIRECTREADBYTES = 2,\n\tNFSIOS_DIRECTWRITTENBYTES = 3,\n\tNFSIOS_SERVERREADBYTES = 4,\n\tNFSIOS_SERVERWRITTENBYTES = 5,\n\tNFSIOS_READPAGES = 6,\n\tNFSIOS_WRITEPAGES = 7,\n\t__NFSIOS_BYTESMAX = 8,\n};\n\nenum nfs_stat_eventcounters {\n\tNFSIOS_INODEREVALIDATE = 0,\n\tNFSIOS_DENTRYREVALIDATE = 1,\n\tNFSIOS_DATAINVALIDATE = 2,\n\tNFSIOS_ATTRINVALIDATE = 3,\n\tNFSIOS_VFSOPEN = 4,\n\tNFSIOS_VFSLOOKUP = 5,\n\tNFSIOS_VFSACCESS = 6,\n\tNFSIOS_VFSUPDATEPAGE = 7,\n\tNFSIOS_VFSREADPAGE = 8,\n\tNFSIOS_VFSREADPAGES = 9,\n\tNFSIOS_VFSWRITEPAGE = 10,\n\tNFSIOS_VFSWRITEPAGES = 11,\n\tNFSIOS_VFSGETDENTS = 12,\n\tNFSIOS_VFSSETATTR = 13,\n\tNFSIOS_VFSFLUSH = 14,\n\tNFSIOS_VFSFSYNC = 15,\n\tNFSIOS_VFSLOCK = 16,\n\tNFSIOS_VFSRELEASE = 17,\n\tNFSIOS_CONGESTIONWAIT = 18,\n\tNFSIOS_SETATTRTRUNC = 19,\n\tNFSIOS_EXTENDWRITE = 20,\n\tNFSIOS_SILLYRENAME = 21,\n\tNFSIOS_SHORTREAD = 22,\n\tNFSIOS_SHORTWRITE = 23,\n\tNFSIOS_DELAY = 24,\n\tNFSIOS_PNFS_READ = 25,\n\tNFSIOS_PNFS_WRITE = 26,\n\t__NFSIOS_COUNTSMAX = 27,\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n\tNFS4ERR_NOXATTR = 10095,\n\tNFS4ERR_XATTR2BIG = 10096,\n\tNFS4ERR_FIRST_FREE = 10097,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_SWAPCACHE = 39,\n\tPGDEMOTE_KSWAPD = 40,\n\tPGDEMOTE_DIRECT = 41,\n\tPGDEMOTE_KHUGEPAGED = 42,\n\tPGDEMOTE_PROACTIVE = 43,\n\tNR_BALLOON_PAGES = 44,\n\tNR_KERNEL_FILE_PAGES = 45,\n\tNR_VM_NODE_STAT_ITEMS = 46,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 3,\n\tN_MEMORY = 4,\n\tN_CPU = 5,\n\tN_GENERIC_INITIATOR = 6,\n\tNR_NODE_STATES = 7,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n\tNVMEM_TYPE_FRAM = 4,\n};\n\nenum oatc14_hdd_status {\n\tOATC14_HDD_STATUS_CABLE_OK = 0,\n\tOATC14_HDD_STATUS_OPEN = 1,\n\tOATC14_HDD_STATUS_SHORT = 2,\n\tOATC14_HDD_STATUS_NOT_DETECTABLE = 3,\n};\n\nenum objext_flags {\n\tOBJEXTS_ALLOC_FAIL = 1,\n\t__OBJEXTS_FLAG_UNUSED = 4,\n\t__NR_OBJEXTS_FLAGS = 8,\n};\n\nenum ocelot_action_type {\n\tOCELOT_MACT_LEARN = 0,\n\tOCELOT_MACT_FORGET = 1,\n};\n\nenum ocelot_es0_pcp_sel {\n\tOCELOT_CLASSIFIED_PCP = 0,\n\tOCELOT_ES0_PCP = 1,\n};\n\nenum ocelot_es0_tag {\n\tOCELOT_NO_ES0_TAG = 0,\n\tOCELOT_ES0_TAG = 1,\n\tOCELOT_FORCE_PORT_TAG = 2,\n\tOCELOT_FORCE_UNTAG = 3,\n};\n\nenum ocelot_es0_vid_sel {\n\tOCELOT_ES0_VID_PLUS_CLASSIFIED_VID = 0,\n\tOCELOT_ES0_VID = 1,\n};\n\nenum ocelot_mask_mode {\n\tOCELOT_MASK_MODE_NONE = 0,\n\tOCELOT_MASK_MODE_PERMIT_DENY = 1,\n\tOCELOT_MASK_MODE_POLICY = 2,\n\tOCELOT_MASK_MODE_REDIRECT = 3,\n};\n\nenum ocelot_port_tag_config {\n\tOCELOT_PORT_TAG_DISABLED = 0,\n\tOCELOT_PORT_TAG_NATIVE = 1,\n\tOCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,\n\tOCELOT_PORT_TAG_TRUNK = 3,\n};\n\nenum ocelot_proto {\n\tOCELOT_PROTO_PTP_L2 = 1,\n\tOCELOT_PROTO_PTP_L4 = 2,\n};\n\nenum ocelot_ptp_pins {\n\tPTP_PIN_0 = 0,\n\tPTP_PIN_1 = 1,\n\tPTP_PIN_2 = 2,\n\tPTP_PIN_3 = 3,\n\tTOD_ACC_PIN = 4,\n};\n\nenum ocelot_reg {\n\tANA_ADVLEARN = 16777216,\n\tANA_VLANMASK = 16777217,\n\tANA_PORT_B_DOMAIN = 16777218,\n\tANA_ANAGEFIL = 16777219,\n\tANA_ANEVENTS = 16777220,\n\tANA_STORMLIMIT_BURST = 16777221,\n\tANA_STORMLIMIT_CFG = 16777222,\n\tANA_ISOLATED_PORTS = 16777223,\n\tANA_COMMUNITY_PORTS = 16777224,\n\tANA_AUTOAGE = 16777225,\n\tANA_MACTOPTIONS = 16777226,\n\tANA_LEARNDISC = 16777227,\n\tANA_AGENCTRL = 16777228,\n\tANA_MIRRORPORTS = 16777229,\n\tANA_EMIRRORPORTS = 16777230,\n\tANA_FLOODING = 16777231,\n\tANA_FLOODING_IPMC = 16777232,\n\tANA_SFLOW_CFG = 16777233,\n\tANA_PORT_MODE = 16777234,\n\tANA_CUT_THRU_CFG = 16777235,\n\tANA_PGID_PGID = 16777236,\n\tANA_TABLES_ANMOVED = 16777237,\n\tANA_TABLES_MACHDATA = 16777238,\n\tANA_TABLES_MACLDATA = 16777239,\n\tANA_TABLES_STREAMDATA = 16777240,\n\tANA_TABLES_MACACCESS = 16777241,\n\tANA_TABLES_MACTINDX = 16777242,\n\tANA_TABLES_VLANACCESS = 16777243,\n\tANA_TABLES_VLANTIDX = 16777244,\n\tANA_TABLES_ISDXACCESS = 16777245,\n\tANA_TABLES_ISDXTIDX = 16777246,\n\tANA_TABLES_ENTRYLIM = 16777247,\n\tANA_TABLES_PTP_ID_HIGH = 16777248,\n\tANA_TABLES_PTP_ID_LOW = 16777249,\n\tANA_TABLES_STREAMACCESS = 16777250,\n\tANA_TABLES_STREAMTIDX = 16777251,\n\tANA_TABLES_SEQ_HISTORY = 16777252,\n\tANA_TABLES_SEQ_MASK = 16777253,\n\tANA_TABLES_SFID_MASK = 16777254,\n\tANA_TABLES_SFIDACCESS = 16777255,\n\tANA_TABLES_SFIDTIDX = 16777256,\n\tANA_MSTI_STATE = 16777257,\n\tANA_OAM_UPM_LM_CNT = 16777258,\n\tANA_SG_ACCESS_CTRL = 16777259,\n\tANA_SG_CONFIG_REG_1 = 16777260,\n\tANA_SG_CONFIG_REG_2 = 16777261,\n\tANA_SG_CONFIG_REG_3 = 16777262,\n\tANA_SG_CONFIG_REG_4 = 16777263,\n\tANA_SG_CONFIG_REG_5 = 16777264,\n\tANA_SG_GCL_GS_CONFIG = 16777265,\n\tANA_SG_GCL_TI_CONFIG = 16777266,\n\tANA_SG_STATUS_REG_1 = 16777267,\n\tANA_SG_STATUS_REG_2 = 16777268,\n\tANA_SG_STATUS_REG_3 = 16777269,\n\tANA_PORT_VLAN_CFG = 16777270,\n\tANA_PORT_DROP_CFG = 16777271,\n\tANA_PORT_QOS_CFG = 16777272,\n\tANA_PORT_VCAP_CFG = 16777273,\n\tANA_PORT_VCAP_S1_KEY_CFG = 16777274,\n\tANA_PORT_VCAP_S2_CFG = 16777275,\n\tANA_PORT_PCP_DEI_MAP = 16777276,\n\tANA_PORT_CPU_FWD_CFG = 16777277,\n\tANA_PORT_CPU_FWD_BPDU_CFG = 16777278,\n\tANA_PORT_CPU_FWD_GARP_CFG = 16777279,\n\tANA_PORT_CPU_FWD_CCM_CFG = 16777280,\n\tANA_PORT_PORT_CFG = 16777281,\n\tANA_PORT_POL_CFG = 16777282,\n\tANA_PORT_PTP_CFG = 16777283,\n\tANA_PORT_PTP_DLY1_CFG = 16777284,\n\tANA_PORT_PTP_DLY2_CFG = 16777285,\n\tANA_PORT_SFID_CFG = 16777286,\n\tANA_PFC_PFC_CFG = 16777287,\n\tANA_PFC_PFC_TIMER = 16777288,\n\tANA_IPT_OAM_MEP_CFG = 16777289,\n\tANA_IPT_IPT = 16777290,\n\tANA_PPT_PPT = 16777291,\n\tANA_FID_MAP_FID_MAP = 16777292,\n\tANA_AGGR_CFG = 16777293,\n\tANA_CPUQ_CFG = 16777294,\n\tANA_CPUQ_CFG2 = 16777295,\n\tANA_CPUQ_8021_CFG = 16777296,\n\tANA_DSCP_CFG = 16777297,\n\tANA_DSCP_REWR_CFG = 16777298,\n\tANA_VCAP_RNG_TYPE_CFG = 16777299,\n\tANA_VCAP_RNG_VAL_CFG = 16777300,\n\tANA_VRAP_CFG = 16777301,\n\tANA_VRAP_HDR_DATA = 16777302,\n\tANA_VRAP_HDR_MASK = 16777303,\n\tANA_DISCARD_CFG = 16777304,\n\tANA_FID_CFG = 16777305,\n\tANA_POL_PIR_CFG = 16777306,\n\tANA_POL_CIR_CFG = 16777307,\n\tANA_POL_MODE_CFG = 16777308,\n\tANA_POL_PIR_STATE = 16777309,\n\tANA_POL_CIR_STATE = 16777310,\n\tANA_POL_STATE = 16777311,\n\tANA_POL_FLOWC = 16777312,\n\tANA_POL_HYST = 16777313,\n\tANA_POL_MISC_CFG = 16777314,\n\tQS_XTR_GRP_CFG = 33554432,\n\tQS_XTR_RD = 33554433,\n\tQS_XTR_FRM_PRUNING = 33554434,\n\tQS_XTR_FLUSH = 33554435,\n\tQS_XTR_DATA_PRESENT = 33554436,\n\tQS_XTR_CFG = 33554437,\n\tQS_INJ_GRP_CFG = 33554438,\n\tQS_INJ_WR = 33554439,\n\tQS_INJ_CTRL = 33554440,\n\tQS_INJ_STATUS = 33554441,\n\tQS_INJ_ERR = 33554442,\n\tQS_INH_DBG = 33554443,\n\tQSYS_PORT_MODE = 50331648,\n\tQSYS_SWITCH_PORT_MODE = 50331649,\n\tQSYS_STAT_CNT_CFG = 50331650,\n\tQSYS_EEE_CFG = 50331651,\n\tQSYS_EEE_THRES = 50331652,\n\tQSYS_IGR_NO_SHARING = 50331653,\n\tQSYS_EGR_NO_SHARING = 50331654,\n\tQSYS_SW_STATUS = 50331655,\n\tQSYS_EXT_CPU_CFG = 50331656,\n\tQSYS_PAD_CFG = 50331657,\n\tQSYS_CPU_GROUP_MAP = 50331658,\n\tQSYS_QMAP = 50331659,\n\tQSYS_ISDX_SGRP = 50331660,\n\tQSYS_TIMED_FRAME_ENTRY = 50331661,\n\tQSYS_TFRM_MISC = 50331662,\n\tQSYS_TFRM_PORT_DLY = 50331663,\n\tQSYS_TFRM_TIMER_CFG_1 = 50331664,\n\tQSYS_TFRM_TIMER_CFG_2 = 50331665,\n\tQSYS_TFRM_TIMER_CFG_3 = 50331666,\n\tQSYS_TFRM_TIMER_CFG_4 = 50331667,\n\tQSYS_TFRM_TIMER_CFG_5 = 50331668,\n\tQSYS_TFRM_TIMER_CFG_6 = 50331669,\n\tQSYS_TFRM_TIMER_CFG_7 = 50331670,\n\tQSYS_TFRM_TIMER_CFG_8 = 50331671,\n\tQSYS_RED_PROFILE = 50331672,\n\tQSYS_RES_QOS_MODE = 50331673,\n\tQSYS_RES_CFG = 50331674,\n\tQSYS_RES_STAT = 50331675,\n\tQSYS_EGR_DROP_MODE = 50331676,\n\tQSYS_EQ_CTRL = 50331677,\n\tQSYS_EVENTS_CORE = 50331678,\n\tQSYS_QMAXSDU_CFG_0 = 50331679,\n\tQSYS_QMAXSDU_CFG_1 = 50331680,\n\tQSYS_QMAXSDU_CFG_2 = 50331681,\n\tQSYS_QMAXSDU_CFG_3 = 50331682,\n\tQSYS_QMAXSDU_CFG_4 = 50331683,\n\tQSYS_QMAXSDU_CFG_5 = 50331684,\n\tQSYS_QMAXSDU_CFG_6 = 50331685,\n\tQSYS_QMAXSDU_CFG_7 = 50331686,\n\tQSYS_PREEMPTION_CFG = 50331687,\n\tQSYS_CIR_CFG = 50331688,\n\tQSYS_EIR_CFG = 50331689,\n\tQSYS_SE_CFG = 50331690,\n\tQSYS_SE_DWRR_CFG = 50331691,\n\tQSYS_SE_CONNECT = 50331692,\n\tQSYS_SE_DLB_SENSE = 50331693,\n\tQSYS_CIR_STATE = 50331694,\n\tQSYS_EIR_STATE = 50331695,\n\tQSYS_SE_STATE = 50331696,\n\tQSYS_HSCH_MISC_CFG = 50331697,\n\tQSYS_TAG_CONFIG = 50331698,\n\tQSYS_TAS_PARAM_CFG_CTRL = 50331699,\n\tQSYS_PORT_MAX_SDU = 50331700,\n\tQSYS_PARAM_CFG_REG_1 = 50331701,\n\tQSYS_PARAM_CFG_REG_2 = 50331702,\n\tQSYS_PARAM_CFG_REG_3 = 50331703,\n\tQSYS_PARAM_CFG_REG_4 = 50331704,\n\tQSYS_PARAM_CFG_REG_5 = 50331705,\n\tQSYS_GCL_CFG_REG_1 = 50331706,\n\tQSYS_GCL_CFG_REG_2 = 50331707,\n\tQSYS_PARAM_STATUS_REG_1 = 50331708,\n\tQSYS_PARAM_STATUS_REG_2 = 50331709,\n\tQSYS_PARAM_STATUS_REG_3 = 50331710,\n\tQSYS_PARAM_STATUS_REG_4 = 50331711,\n\tQSYS_PARAM_STATUS_REG_5 = 50331712,\n\tQSYS_PARAM_STATUS_REG_6 = 50331713,\n\tQSYS_PARAM_STATUS_REG_7 = 50331714,\n\tQSYS_PARAM_STATUS_REG_8 = 50331715,\n\tQSYS_PARAM_STATUS_REG_9 = 50331716,\n\tQSYS_GCL_STATUS_REG_1 = 50331717,\n\tQSYS_GCL_STATUS_REG_2 = 50331718,\n\tREW_PORT_VLAN_CFG = 67108864,\n\tREW_TAG_CFG = 67108865,\n\tREW_PORT_CFG = 67108866,\n\tREW_DSCP_CFG = 67108867,\n\tREW_PCP_DEI_QOS_MAP_CFG = 67108868,\n\tREW_PTP_CFG = 67108869,\n\tREW_PTP_DLY1_CFG = 67108870,\n\tREW_RED_TAG_CFG = 67108871,\n\tREW_DSCP_REMAP_DP1_CFG = 67108872,\n\tREW_DSCP_REMAP_CFG = 67108873,\n\tREW_STAT_CFG = 67108874,\n\tREW_REW_STICKY = 67108875,\n\tREW_PPT = 67108876,\n\tSYS_COUNT_RX_OCTETS = 83886080,\n\tSYS_COUNT_RX_UNICAST = 83886081,\n\tSYS_COUNT_RX_MULTICAST = 83886082,\n\tSYS_COUNT_RX_BROADCAST = 83886083,\n\tSYS_COUNT_RX_SHORTS = 83886084,\n\tSYS_COUNT_RX_FRAGMENTS = 83886085,\n\tSYS_COUNT_RX_JABBERS = 83886086,\n\tSYS_COUNT_RX_CRC_ALIGN_ERRS = 83886087,\n\tSYS_COUNT_RX_SYM_ERRS = 83886088,\n\tSYS_COUNT_RX_64 = 83886089,\n\tSYS_COUNT_RX_65_127 = 83886090,\n\tSYS_COUNT_RX_128_255 = 83886091,\n\tSYS_COUNT_RX_256_511 = 83886092,\n\tSYS_COUNT_RX_512_1023 = 83886093,\n\tSYS_COUNT_RX_1024_1526 = 83886094,\n\tSYS_COUNT_RX_1527_MAX = 83886095,\n\tSYS_COUNT_RX_PAUSE = 83886096,\n\tSYS_COUNT_RX_CONTROL = 83886097,\n\tSYS_COUNT_RX_LONGS = 83886098,\n\tSYS_COUNT_RX_CLASSIFIED_DROPS = 83886099,\n\tSYS_COUNT_RX_RED_PRIO_0 = 83886100,\n\tSYS_COUNT_RX_RED_PRIO_1 = 83886101,\n\tSYS_COUNT_RX_RED_PRIO_2 = 83886102,\n\tSYS_COUNT_RX_RED_PRIO_3 = 83886103,\n\tSYS_COUNT_RX_RED_PRIO_4 = 83886104,\n\tSYS_COUNT_RX_RED_PRIO_5 = 83886105,\n\tSYS_COUNT_RX_RED_PRIO_6 = 83886106,\n\tSYS_COUNT_RX_RED_PRIO_7 = 83886107,\n\tSYS_COUNT_RX_YELLOW_PRIO_0 = 83886108,\n\tSYS_COUNT_RX_YELLOW_PRIO_1 = 83886109,\n\tSYS_COUNT_RX_YELLOW_PRIO_2 = 83886110,\n\tSYS_COUNT_RX_YELLOW_PRIO_3 = 83886111,\n\tSYS_COUNT_RX_YELLOW_PRIO_4 = 83886112,\n\tSYS_COUNT_RX_YELLOW_PRIO_5 = 83886113,\n\tSYS_COUNT_RX_YELLOW_PRIO_6 = 83886114,\n\tSYS_COUNT_RX_YELLOW_PRIO_7 = 83886115,\n\tSYS_COUNT_RX_GREEN_PRIO_0 = 83886116,\n\tSYS_COUNT_RX_GREEN_PRIO_1 = 83886117,\n\tSYS_COUNT_RX_GREEN_PRIO_2 = 83886118,\n\tSYS_COUNT_RX_GREEN_PRIO_3 = 83886119,\n\tSYS_COUNT_RX_GREEN_PRIO_4 = 83886120,\n\tSYS_COUNT_RX_GREEN_PRIO_5 = 83886121,\n\tSYS_COUNT_RX_GREEN_PRIO_6 = 83886122,\n\tSYS_COUNT_RX_GREEN_PRIO_7 = 83886123,\n\tSYS_COUNT_RX_ASSEMBLY_ERRS = 83886124,\n\tSYS_COUNT_RX_SMD_ERRS = 83886125,\n\tSYS_COUNT_RX_ASSEMBLY_OK = 83886126,\n\tSYS_COUNT_RX_MERGE_FRAGMENTS = 83886127,\n\tSYS_COUNT_RX_PMAC_OCTETS = 83886128,\n\tSYS_COUNT_RX_PMAC_UNICAST = 83886129,\n\tSYS_COUNT_RX_PMAC_MULTICAST = 83886130,\n\tSYS_COUNT_RX_PMAC_BROADCAST = 83886131,\n\tSYS_COUNT_RX_PMAC_SHORTS = 83886132,\n\tSYS_COUNT_RX_PMAC_FRAGMENTS = 83886133,\n\tSYS_COUNT_RX_PMAC_JABBERS = 83886134,\n\tSYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS = 83886135,\n\tSYS_COUNT_RX_PMAC_SYM_ERRS = 83886136,\n\tSYS_COUNT_RX_PMAC_64 = 83886137,\n\tSYS_COUNT_RX_PMAC_65_127 = 83886138,\n\tSYS_COUNT_RX_PMAC_128_255 = 83886139,\n\tSYS_COUNT_RX_PMAC_256_511 = 83886140,\n\tSYS_COUNT_RX_PMAC_512_1023 = 83886141,\n\tSYS_COUNT_RX_PMAC_1024_1526 = 83886142,\n\tSYS_COUNT_RX_PMAC_1527_MAX = 83886143,\n\tSYS_COUNT_RX_PMAC_PAUSE = 83886144,\n\tSYS_COUNT_RX_PMAC_CONTROL = 83886145,\n\tSYS_COUNT_RX_PMAC_LONGS = 83886146,\n\tSYS_COUNT_TX_OCTETS = 83886147,\n\tSYS_COUNT_TX_UNICAST = 83886148,\n\tSYS_COUNT_TX_MULTICAST = 83886149,\n\tSYS_COUNT_TX_BROADCAST = 83886150,\n\tSYS_COUNT_TX_COLLISION = 83886151,\n\tSYS_COUNT_TX_DROPS = 83886152,\n\tSYS_COUNT_TX_PAUSE = 83886153,\n\tSYS_COUNT_TX_64 = 83886154,\n\tSYS_COUNT_TX_65_127 = 83886155,\n\tSYS_COUNT_TX_128_255 = 83886156,\n\tSYS_COUNT_TX_256_511 = 83886157,\n\tSYS_COUNT_TX_512_1023 = 83886158,\n\tSYS_COUNT_TX_1024_1526 = 83886159,\n\tSYS_COUNT_TX_1527_MAX = 83886160,\n\tSYS_COUNT_TX_YELLOW_PRIO_0 = 83886161,\n\tSYS_COUNT_TX_YELLOW_PRIO_1 = 83886162,\n\tSYS_COUNT_TX_YELLOW_PRIO_2 = 83886163,\n\tSYS_COUNT_TX_YELLOW_PRIO_3 = 83886164,\n\tSYS_COUNT_TX_YELLOW_PRIO_4 = 83886165,\n\tSYS_COUNT_TX_YELLOW_PRIO_5 = 83886166,\n\tSYS_COUNT_TX_YELLOW_PRIO_6 = 83886167,\n\tSYS_COUNT_TX_YELLOW_PRIO_7 = 83886168,\n\tSYS_COUNT_TX_GREEN_PRIO_0 = 83886169,\n\tSYS_COUNT_TX_GREEN_PRIO_1 = 83886170,\n\tSYS_COUNT_TX_GREEN_PRIO_2 = 83886171,\n\tSYS_COUNT_TX_GREEN_PRIO_3 = 83886172,\n\tSYS_COUNT_TX_GREEN_PRIO_4 = 83886173,\n\tSYS_COUNT_TX_GREEN_PRIO_5 = 83886174,\n\tSYS_COUNT_TX_GREEN_PRIO_6 = 83886175,\n\tSYS_COUNT_TX_GREEN_PRIO_7 = 83886176,\n\tSYS_COUNT_TX_AGED = 83886177,\n\tSYS_COUNT_TX_MM_HOLD = 83886178,\n\tSYS_COUNT_TX_MERGE_FRAGMENTS = 83886179,\n\tSYS_COUNT_TX_PMAC_OCTETS = 83886180,\n\tSYS_COUNT_TX_PMAC_UNICAST = 83886181,\n\tSYS_COUNT_TX_PMAC_MULTICAST = 83886182,\n\tSYS_COUNT_TX_PMAC_BROADCAST = 83886183,\n\tSYS_COUNT_TX_PMAC_PAUSE = 83886184,\n\tSYS_COUNT_TX_PMAC_64 = 83886185,\n\tSYS_COUNT_TX_PMAC_65_127 = 83886186,\n\tSYS_COUNT_TX_PMAC_128_255 = 83886187,\n\tSYS_COUNT_TX_PMAC_256_511 = 83886188,\n\tSYS_COUNT_TX_PMAC_512_1023 = 83886189,\n\tSYS_COUNT_TX_PMAC_1024_1526 = 83886190,\n\tSYS_COUNT_TX_PMAC_1527_MAX = 83886191,\n\tSYS_COUNT_DROP_LOCAL = 83886192,\n\tSYS_COUNT_DROP_TAIL = 83886193,\n\tSYS_COUNT_DROP_YELLOW_PRIO_0 = 83886194,\n\tSYS_COUNT_DROP_YELLOW_PRIO_1 = 83886195,\n\tSYS_COUNT_DROP_YELLOW_PRIO_2 = 83886196,\n\tSYS_COUNT_DROP_YELLOW_PRIO_3 = 83886197,\n\tSYS_COUNT_DROP_YELLOW_PRIO_4 = 83886198,\n\tSYS_COUNT_DROP_YELLOW_PRIO_5 = 83886199,\n\tSYS_COUNT_DROP_YELLOW_PRIO_6 = 83886200,\n\tSYS_COUNT_DROP_YELLOW_PRIO_7 = 83886201,\n\tSYS_COUNT_DROP_GREEN_PRIO_0 = 83886202,\n\tSYS_COUNT_DROP_GREEN_PRIO_1 = 83886203,\n\tSYS_COUNT_DROP_GREEN_PRIO_2 = 83886204,\n\tSYS_COUNT_DROP_GREEN_PRIO_3 = 83886205,\n\tSYS_COUNT_DROP_GREEN_PRIO_4 = 83886206,\n\tSYS_COUNT_DROP_GREEN_PRIO_5 = 83886207,\n\tSYS_COUNT_DROP_GREEN_PRIO_6 = 83886208,\n\tSYS_COUNT_DROP_GREEN_PRIO_7 = 83886209,\n\tSYS_COUNT_SF_MATCHING_FRAMES = 83886210,\n\tSYS_COUNT_SF_NOT_PASSING_FRAMES = 83886211,\n\tSYS_COUNT_SF_NOT_PASSING_SDU = 83886212,\n\tSYS_COUNT_SF_RED_FRAMES = 83886213,\n\tSYS_RESET_CFG = 83886214,\n\tSYS_SR_ETYPE_CFG = 83886215,\n\tSYS_VLAN_ETYPE_CFG = 83886216,\n\tSYS_PORT_MODE = 83886217,\n\tSYS_FRONT_PORT_MODE = 83886218,\n\tSYS_FRM_AGING = 83886219,\n\tSYS_STAT_CFG = 83886220,\n\tSYS_SW_STATUS = 83886221,\n\tSYS_MISC_CFG = 83886222,\n\tSYS_REW_MAC_HIGH_CFG = 83886223,\n\tSYS_REW_MAC_LOW_CFG = 83886224,\n\tSYS_TIMESTAMP_OFFSET = 83886225,\n\tSYS_CMID = 83886226,\n\tSYS_PAUSE_CFG = 83886227,\n\tSYS_PAUSE_TOT_CFG = 83886228,\n\tSYS_ATOP = 83886229,\n\tSYS_ATOP_TOT_CFG = 83886230,\n\tSYS_MAC_FC_CFG = 83886231,\n\tSYS_MMGT = 83886232,\n\tSYS_MMGT_FAST = 83886233,\n\tSYS_EVENTS_DIF = 83886234,\n\tSYS_EVENTS_CORE = 83886235,\n\tSYS_PTP_STATUS = 83886236,\n\tSYS_PTP_TXSTAMP = 83886237,\n\tSYS_PTP_NXT = 83886238,\n\tSYS_PTP_CFG = 83886239,\n\tSYS_RAM_INIT = 83886240,\n\tSYS_CM_ADDR = 83886241,\n\tSYS_CM_DATA_WR = 83886242,\n\tSYS_CM_DATA_RD = 83886243,\n\tSYS_CM_OP = 83886244,\n\tSYS_CM_DATA = 83886245,\n\tPTP_PIN_CFG = 167772160,\n\tPTP_PIN_TOD_SEC_MSB = 167772161,\n\tPTP_PIN_TOD_SEC_LSB = 167772162,\n\tPTP_PIN_TOD_NSEC = 167772163,\n\tPTP_PIN_WF_HIGH_PERIOD = 167772164,\n\tPTP_PIN_WF_LOW_PERIOD = 167772165,\n\tPTP_CFG_MISC = 167772166,\n\tPTP_CLK_CFG_ADJ_CFG = 167772167,\n\tPTP_CLK_CFG_ADJ_FREQ = 167772168,\n\tGCB_SOFT_RST = 201326592,\n\tGCB_MIIM_MII_STATUS = 201326593,\n\tGCB_MIIM_MII_CMD = 201326594,\n\tGCB_MIIM_MII_DATA = 201326595,\n\tDEV_CLOCK_CFG = 218103808,\n\tDEV_PORT_MISC = 218103809,\n\tDEV_EVENTS = 218103810,\n\tDEV_EEE_CFG = 218103811,\n\tDEV_RX_PATH_DELAY = 218103812,\n\tDEV_TX_PATH_DELAY = 218103813,\n\tDEV_PTP_PREDICT_CFG = 218103814,\n\tDEV_MAC_ENA_CFG = 218103815,\n\tDEV_MAC_MODE_CFG = 218103816,\n\tDEV_MAC_MAXLEN_CFG = 218103817,\n\tDEV_MAC_TAGS_CFG = 218103818,\n\tDEV_MAC_ADV_CHK_CFG = 218103819,\n\tDEV_MAC_IFG_CFG = 218103820,\n\tDEV_MAC_HDX_CFG = 218103821,\n\tDEV_MAC_DBG_CFG = 218103822,\n\tDEV_MAC_FC_MAC_LOW_CFG = 218103823,\n\tDEV_MAC_FC_MAC_HIGH_CFG = 218103824,\n\tDEV_MAC_STICKY = 218103825,\n\tDEV_MM_ENABLE_CONFIG = 218103826,\n\tDEV_MM_VERIF_CONFIG = 218103827,\n\tDEV_MM_STATUS = 218103828,\n\tPCS1G_CFG = 218103829,\n\tPCS1G_MODE_CFG = 218103830,\n\tPCS1G_SD_CFG = 218103831,\n\tPCS1G_ANEG_CFG = 218103832,\n\tPCS1G_ANEG_NP_CFG = 218103833,\n\tPCS1G_LB_CFG = 218103834,\n\tPCS1G_DBG_CFG = 218103835,\n\tPCS1G_CDET_CFG = 218103836,\n\tPCS1G_ANEG_STATUS = 218103837,\n\tPCS1G_ANEG_NP_STATUS = 218103838,\n\tPCS1G_LINK_STATUS = 218103839,\n\tPCS1G_LINK_DOWN_CNT = 218103840,\n\tPCS1G_STICKY = 218103841,\n\tPCS1G_DEBUG_STATUS = 218103842,\n\tPCS1G_LPI_CFG = 218103843,\n\tPCS1G_LPI_WAKE_ERROR_CNT = 218103844,\n\tPCS1G_LPI_STATUS = 218103845,\n\tPCS1G_TSTPAT_MODE_CFG = 218103846,\n\tPCS1G_TSTPAT_STATUS = 218103847,\n\tDEV_PCS_FX100_CFG = 218103848,\n\tDEV_PCS_FX100_STATUS = 218103849,\n};\n\nenum ocelot_regfield {\n\tANA_ADVLEARN_VLAN_CHK = 0,\n\tANA_ADVLEARN_LEARN_MIRROR = 1,\n\tANA_ANEVENTS_FLOOD_DISCARD = 2,\n\tANA_ANEVENTS_MSTI_DROP = 3,\n\tANA_ANEVENTS_ACLKILL = 4,\n\tANA_ANEVENTS_ACLUSED = 5,\n\tANA_ANEVENTS_AUTOAGE = 6,\n\tANA_ANEVENTS_VS2TTL1 = 7,\n\tANA_ANEVENTS_STORM_DROP = 8,\n\tANA_ANEVENTS_LEARN_DROP = 9,\n\tANA_ANEVENTS_AGED_ENTRY = 10,\n\tANA_ANEVENTS_CPU_LEARN_FAILED = 11,\n\tANA_ANEVENTS_AUTO_LEARN_FAILED = 12,\n\tANA_ANEVENTS_LEARN_REMOVE = 13,\n\tANA_ANEVENTS_AUTO_LEARNED = 14,\n\tANA_ANEVENTS_AUTO_MOVED = 15,\n\tANA_ANEVENTS_DROPPED = 16,\n\tANA_ANEVENTS_CLASSIFIED_DROP = 17,\n\tANA_ANEVENTS_CLASSIFIED_COPY = 18,\n\tANA_ANEVENTS_VLAN_DISCARD = 19,\n\tANA_ANEVENTS_FWD_DISCARD = 20,\n\tANA_ANEVENTS_MULTICAST_FLOOD = 21,\n\tANA_ANEVENTS_UNICAST_FLOOD = 22,\n\tANA_ANEVENTS_DEST_KNOWN = 23,\n\tANA_ANEVENTS_BUCKET3_MATCH = 24,\n\tANA_ANEVENTS_BUCKET2_MATCH = 25,\n\tANA_ANEVENTS_BUCKET1_MATCH = 26,\n\tANA_ANEVENTS_BUCKET0_MATCH = 27,\n\tANA_ANEVENTS_CPU_OPERATION = 28,\n\tANA_ANEVENTS_DMAC_LOOKUP = 29,\n\tANA_ANEVENTS_SMAC_LOOKUP = 30,\n\tANA_ANEVENTS_SEQ_GEN_ERR_0 = 31,\n\tANA_ANEVENTS_SEQ_GEN_ERR_1 = 32,\n\tANA_TABLES_MACACCESS_B_DOM = 33,\n\tANA_TABLES_MACTINDX_BUCKET = 34,\n\tANA_TABLES_MACTINDX_M_INDEX = 35,\n\tQSYS_SWITCH_PORT_MODE_PORT_ENA = 36,\n\tQSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG = 37,\n\tQSYS_SWITCH_PORT_MODE_YEL_RSRVD = 38,\n\tQSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE = 39,\n\tQSYS_SWITCH_PORT_MODE_TX_PFC_ENA = 40,\n\tQSYS_SWITCH_PORT_MODE_TX_PFC_MODE = 41,\n\tQSYS_TIMED_FRAME_ENTRY_TFRM_VLD = 42,\n\tQSYS_TIMED_FRAME_ENTRY_TFRM_FP = 43,\n\tQSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO = 44,\n\tQSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL = 45,\n\tQSYS_TIMED_FRAME_ENTRY_TFRM_TM_T = 46,\n\tSYS_PORT_MODE_DATA_WO_TS = 47,\n\tSYS_PORT_MODE_INCL_INJ_HDR = 48,\n\tSYS_PORT_MODE_INCL_XTR_HDR = 49,\n\tSYS_PORT_MODE_INCL_HDR_ERR = 50,\n\tSYS_RESET_CFG_CORE_ENA = 51,\n\tSYS_RESET_CFG_MEM_ENA = 52,\n\tSYS_RESET_CFG_MEM_INIT = 53,\n\tGCB_SOFT_RST_SWC_RST = 54,\n\tGCB_MIIM_MII_STATUS_PENDING = 55,\n\tGCB_MIIM_MII_STATUS_BUSY = 56,\n\tSYS_PAUSE_CFG_PAUSE_START = 57,\n\tSYS_PAUSE_CFG_PAUSE_STOP = 58,\n\tSYS_PAUSE_CFG_PAUSE_ENA = 59,\n\tREGFIELD_MAX = 60,\n};\n\nenum ocelot_sb {\n\tOCELOT_SB_BUF = 0,\n\tOCELOT_SB_REF = 1,\n\tOCELOT_SB_NUM = 2,\n};\n\nenum ocelot_sb_pool {\n\tOCELOT_SB_POOL_ING = 0,\n\tOCELOT_SB_POOL_EGR = 1,\n\tOCELOT_SB_POOL_NUM = 2,\n};\n\nenum ocelot_stat {\n\tOCELOT_STAT_RX_OCTETS = 0,\n\tOCELOT_STAT_RX_UNICAST = 1,\n\tOCELOT_STAT_RX_MULTICAST = 2,\n\tOCELOT_STAT_RX_BROADCAST = 3,\n\tOCELOT_STAT_RX_SHORTS = 4,\n\tOCELOT_STAT_RX_FRAGMENTS = 5,\n\tOCELOT_STAT_RX_JABBERS = 6,\n\tOCELOT_STAT_RX_CRC_ALIGN_ERRS = 7,\n\tOCELOT_STAT_RX_SYM_ERRS = 8,\n\tOCELOT_STAT_RX_64 = 9,\n\tOCELOT_STAT_RX_65_127 = 10,\n\tOCELOT_STAT_RX_128_255 = 11,\n\tOCELOT_STAT_RX_256_511 = 12,\n\tOCELOT_STAT_RX_512_1023 = 13,\n\tOCELOT_STAT_RX_1024_1526 = 14,\n\tOCELOT_STAT_RX_1527_MAX = 15,\n\tOCELOT_STAT_RX_PAUSE = 16,\n\tOCELOT_STAT_RX_CONTROL = 17,\n\tOCELOT_STAT_RX_LONGS = 18,\n\tOCELOT_STAT_RX_CLASSIFIED_DROPS = 19,\n\tOCELOT_STAT_RX_RED_PRIO_0 = 20,\n\tOCELOT_STAT_RX_RED_PRIO_1 = 21,\n\tOCELOT_STAT_RX_RED_PRIO_2 = 22,\n\tOCELOT_STAT_RX_RED_PRIO_3 = 23,\n\tOCELOT_STAT_RX_RED_PRIO_4 = 24,\n\tOCELOT_STAT_RX_RED_PRIO_5 = 25,\n\tOCELOT_STAT_RX_RED_PRIO_6 = 26,\n\tOCELOT_STAT_RX_RED_PRIO_7 = 27,\n\tOCELOT_STAT_RX_YELLOW_PRIO_0 = 28,\n\tOCELOT_STAT_RX_YELLOW_PRIO_1 = 29,\n\tOCELOT_STAT_RX_YELLOW_PRIO_2 = 30,\n\tOCELOT_STAT_RX_YELLOW_PRIO_3 = 31,\n\tOCELOT_STAT_RX_YELLOW_PRIO_4 = 32,\n\tOCELOT_STAT_RX_YELLOW_PRIO_5 = 33,\n\tOCELOT_STAT_RX_YELLOW_PRIO_6 = 34,\n\tOCELOT_STAT_RX_YELLOW_PRIO_7 = 35,\n\tOCELOT_STAT_RX_GREEN_PRIO_0 = 36,\n\tOCELOT_STAT_RX_GREEN_PRIO_1 = 37,\n\tOCELOT_STAT_RX_GREEN_PRIO_2 = 38,\n\tOCELOT_STAT_RX_GREEN_PRIO_3 = 39,\n\tOCELOT_STAT_RX_GREEN_PRIO_4 = 40,\n\tOCELOT_STAT_RX_GREEN_PRIO_5 = 41,\n\tOCELOT_STAT_RX_GREEN_PRIO_6 = 42,\n\tOCELOT_STAT_RX_GREEN_PRIO_7 = 43,\n\tOCELOT_STAT_RX_ASSEMBLY_ERRS = 44,\n\tOCELOT_STAT_RX_SMD_ERRS = 45,\n\tOCELOT_STAT_RX_ASSEMBLY_OK = 46,\n\tOCELOT_STAT_RX_MERGE_FRAGMENTS = 47,\n\tOCELOT_STAT_RX_PMAC_OCTETS = 48,\n\tOCELOT_STAT_RX_PMAC_UNICAST = 49,\n\tOCELOT_STAT_RX_PMAC_MULTICAST = 50,\n\tOCELOT_STAT_RX_PMAC_BROADCAST = 51,\n\tOCELOT_STAT_RX_PMAC_SHORTS = 52,\n\tOCELOT_STAT_RX_PMAC_FRAGMENTS = 53,\n\tOCELOT_STAT_RX_PMAC_JABBERS = 54,\n\tOCELOT_STAT_RX_PMAC_CRC_ALIGN_ERRS = 55,\n\tOCELOT_STAT_RX_PMAC_SYM_ERRS = 56,\n\tOCELOT_STAT_RX_PMAC_64 = 57,\n\tOCELOT_STAT_RX_PMAC_65_127 = 58,\n\tOCELOT_STAT_RX_PMAC_128_255 = 59,\n\tOCELOT_STAT_RX_PMAC_256_511 = 60,\n\tOCELOT_STAT_RX_PMAC_512_1023 = 61,\n\tOCELOT_STAT_RX_PMAC_1024_1526 = 62,\n\tOCELOT_STAT_RX_PMAC_1527_MAX = 63,\n\tOCELOT_STAT_RX_PMAC_PAUSE = 64,\n\tOCELOT_STAT_RX_PMAC_CONTROL = 65,\n\tOCELOT_STAT_RX_PMAC_LONGS = 66,\n\tOCELOT_STAT_TX_OCTETS = 67,\n\tOCELOT_STAT_TX_UNICAST = 68,\n\tOCELOT_STAT_TX_MULTICAST = 69,\n\tOCELOT_STAT_TX_BROADCAST = 70,\n\tOCELOT_STAT_TX_COLLISION = 71,\n\tOCELOT_STAT_TX_DROPS = 72,\n\tOCELOT_STAT_TX_PAUSE = 73,\n\tOCELOT_STAT_TX_64 = 74,\n\tOCELOT_STAT_TX_65_127 = 75,\n\tOCELOT_STAT_TX_128_255 = 76,\n\tOCELOT_STAT_TX_256_511 = 77,\n\tOCELOT_STAT_TX_512_1023 = 78,\n\tOCELOT_STAT_TX_1024_1526 = 79,\n\tOCELOT_STAT_TX_1527_MAX = 80,\n\tOCELOT_STAT_TX_YELLOW_PRIO_0 = 81,\n\tOCELOT_STAT_TX_YELLOW_PRIO_1 = 82,\n\tOCELOT_STAT_TX_YELLOW_PRIO_2 = 83,\n\tOCELOT_STAT_TX_YELLOW_PRIO_3 = 84,\n\tOCELOT_STAT_TX_YELLOW_PRIO_4 = 85,\n\tOCELOT_STAT_TX_YELLOW_PRIO_5 = 86,\n\tOCELOT_STAT_TX_YELLOW_PRIO_6 = 87,\n\tOCELOT_STAT_TX_YELLOW_PRIO_7 = 88,\n\tOCELOT_STAT_TX_GREEN_PRIO_0 = 89,\n\tOCELOT_STAT_TX_GREEN_PRIO_1 = 90,\n\tOCELOT_STAT_TX_GREEN_PRIO_2 = 91,\n\tOCELOT_STAT_TX_GREEN_PRIO_3 = 92,\n\tOCELOT_STAT_TX_GREEN_PRIO_4 = 93,\n\tOCELOT_STAT_TX_GREEN_PRIO_5 = 94,\n\tOCELOT_STAT_TX_GREEN_PRIO_6 = 95,\n\tOCELOT_STAT_TX_GREEN_PRIO_7 = 96,\n\tOCELOT_STAT_TX_AGED = 97,\n\tOCELOT_STAT_TX_MM_HOLD = 98,\n\tOCELOT_STAT_TX_MERGE_FRAGMENTS = 99,\n\tOCELOT_STAT_TX_PMAC_OCTETS = 100,\n\tOCELOT_STAT_TX_PMAC_UNICAST = 101,\n\tOCELOT_STAT_TX_PMAC_MULTICAST = 102,\n\tOCELOT_STAT_TX_PMAC_BROADCAST = 103,\n\tOCELOT_STAT_TX_PMAC_PAUSE = 104,\n\tOCELOT_STAT_TX_PMAC_64 = 105,\n\tOCELOT_STAT_TX_PMAC_65_127 = 106,\n\tOCELOT_STAT_TX_PMAC_128_255 = 107,\n\tOCELOT_STAT_TX_PMAC_256_511 = 108,\n\tOCELOT_STAT_TX_PMAC_512_1023 = 109,\n\tOCELOT_STAT_TX_PMAC_1024_1526 = 110,\n\tOCELOT_STAT_TX_PMAC_1527_MAX = 111,\n\tOCELOT_STAT_DROP_LOCAL = 112,\n\tOCELOT_STAT_DROP_TAIL = 113,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_0 = 114,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_1 = 115,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_2 = 116,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_3 = 117,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_4 = 118,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_5 = 119,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_6 = 120,\n\tOCELOT_STAT_DROP_YELLOW_PRIO_7 = 121,\n\tOCELOT_STAT_DROP_GREEN_PRIO_0 = 122,\n\tOCELOT_STAT_DROP_GREEN_PRIO_1 = 123,\n\tOCELOT_STAT_DROP_GREEN_PRIO_2 = 124,\n\tOCELOT_STAT_DROP_GREEN_PRIO_3 = 125,\n\tOCELOT_STAT_DROP_GREEN_PRIO_4 = 126,\n\tOCELOT_STAT_DROP_GREEN_PRIO_5 = 127,\n\tOCELOT_STAT_DROP_GREEN_PRIO_6 = 128,\n\tOCELOT_STAT_DROP_GREEN_PRIO_7 = 129,\n\tOCELOT_NUM_STATS = 130,\n};\n\nenum ocelot_tag_prefix {\n\tOCELOT_TAG_PREFIX_DISABLED = 0,\n\tOCELOT_TAG_PREFIX_NONE = 1,\n\tOCELOT_TAG_PREFIX_SHORT = 2,\n\tOCELOT_TAG_PREFIX_LONG = 3,\n};\n\nenum ocelot_tag_tpid_sel {\n\tOCELOT_TAG_TPID_SEL_8021Q = 0,\n\tOCELOT_TAG_TPID_SEL_8021AD = 1,\n};\n\nenum ocelot_target {\n\tANA = 1,\n\tQS = 2,\n\tQSYS = 3,\n\tREW = 4,\n\tSYS = 5,\n\tS0 = 6,\n\tS1 = 7,\n\tS2 = 8,\n\tHSIO = 9,\n\tPTP = 10,\n\tFDMA = 11,\n\tGCB = 12,\n\tDEV_GMII = 13,\n\tTARGET_MAX = 14,\n};\n\nenum ocelot_vcap_bit {\n\tOCELOT_VCAP_BIT_ANY = 0,\n\tOCELOT_VCAP_BIT_0 = 1,\n\tOCELOT_VCAP_BIT_1 = 2,\n};\n\nenum ocelot_vcap_filter_type {\n\tOCELOT_VCAP_FILTER_DUMMY = 0,\n\tOCELOT_VCAP_FILTER_PAG = 1,\n\tOCELOT_VCAP_FILTER_OFFLOAD = 2,\n\tOCELOT_PSFP_FILTER_OFFLOAD = 3,\n};\n\nenum ocelot_vcap_key_type {\n\tOCELOT_VCAP_KEY_ANY = 0,\n\tOCELOT_VCAP_KEY_ETYPE = 1,\n\tOCELOT_VCAP_KEY_LLC = 2,\n\tOCELOT_VCAP_KEY_SNAP = 3,\n\tOCELOT_VCAP_KEY_ARP = 4,\n\tOCELOT_VCAP_KEY_IPV4 = 5,\n\tOCELOT_VCAP_KEY_IPV6 = 6,\n};\n\nenum of_gpio_flags {\n\tOF_GPIO_ACTIVE_LOW = 1,\n\tOF_GPIO_SINGLE_ENDED = 2,\n\tOF_GPIO_OPEN_DRAIN = 4,\n\tOF_GPIO_TRANSITORY = 8,\n\tOF_GPIO_PULL_UP = 16,\n\tOF_GPIO_PULL_DOWN = 32,\n\tOF_GPIO_PULL_DISABLE = 64,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum ohci_rh_state {\n\tOHCI_RH_HALTED = 0,\n\tOHCI_RH_SUSPENDED = 1,\n\tOHCI_RH_RUNNING = 2,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum opcode {\n\tinsn_addiu = 0,\n\tinsn_addu = 1,\n\tinsn_and = 2,\n\tinsn_andi = 3,\n\tinsn_bbit0 = 4,\n\tinsn_bbit1 = 5,\n\tinsn_beq = 6,\n\tinsn_beql = 7,\n\tinsn_bgez = 8,\n\tinsn_bgezl = 9,\n\tinsn_bgtz = 10,\n\tinsn_blez = 11,\n\tinsn_bltz = 12,\n\tinsn_bltzl = 13,\n\tinsn_bne = 14,\n\tinsn_break = 15,\n\tinsn_cache = 16,\n\tinsn_cfc1 = 17,\n\tinsn_cfcmsa = 18,\n\tinsn_ctc1 = 19,\n\tinsn_ctcmsa = 20,\n\tinsn_daddiu = 21,\n\tinsn_daddu = 22,\n\tinsn_ddivu = 23,\n\tinsn_ddivu_r6 = 24,\n\tinsn_di = 25,\n\tinsn_dins = 26,\n\tinsn_dinsm = 27,\n\tinsn_dinsu = 28,\n\tinsn_divu = 29,\n\tinsn_divu_r6 = 30,\n\tinsn_dmfc0 = 31,\n\tinsn_dmodu = 32,\n\tinsn_dmtc0 = 33,\n\tinsn_dmultu = 34,\n\tinsn_dmulu = 35,\n\tinsn_drotr = 36,\n\tinsn_drotr32 = 37,\n\tinsn_dsbh = 38,\n\tinsn_dshd = 39,\n\tinsn_dsll = 40,\n\tinsn_dsll32 = 41,\n\tinsn_dsllv = 42,\n\tinsn_dsra = 43,\n\tinsn_dsra32 = 44,\n\tinsn_dsrav = 45,\n\tinsn_dsrl = 46,\n\tinsn_dsrl32 = 47,\n\tinsn_dsrlv = 48,\n\tinsn_dsubu = 49,\n\tinsn_eret = 50,\n\tinsn_ext = 51,\n\tinsn_ins = 52,\n\tinsn_j = 53,\n\tinsn_jal = 54,\n\tinsn_jalr = 55,\n\tinsn_jr = 56,\n\tinsn_lb = 57,\n\tinsn_lbu = 58,\n\tinsn_ld = 59,\n\tinsn_lddir = 60,\n\tinsn_ldpte = 61,\n\tinsn_ldx = 62,\n\tinsn_lh = 63,\n\tinsn_lhu = 64,\n\tinsn_ll = 65,\n\tinsn_lld = 66,\n\tinsn_lui = 67,\n\tinsn_lw = 68,\n\tinsn_lwu = 69,\n\tinsn_lwx = 70,\n\tinsn_mfc0 = 71,\n\tinsn_mfhc0 = 72,\n\tinsn_mfhi = 73,\n\tinsn_mflo = 74,\n\tinsn_modu = 75,\n\tinsn_movn = 76,\n\tinsn_movz = 77,\n\tinsn_mtc0 = 78,\n\tinsn_mthc0 = 79,\n\tinsn_mthi = 80,\n\tinsn_mtlo = 81,\n\tinsn_mul = 82,\n\tinsn_multu = 83,\n\tinsn_mulu = 84,\n\tinsn_muhu = 85,\n\tinsn_nor = 86,\n\tinsn_or = 87,\n\tinsn_ori = 88,\n\tinsn_pref = 89,\n\tinsn_rfe = 90,\n\tinsn_rotr = 91,\n\tinsn_sb = 92,\n\tinsn_sc = 93,\n\tinsn_scd = 94,\n\tinsn_seleqz = 95,\n\tinsn_selnez = 96,\n\tinsn_sd = 97,\n\tinsn_sh = 98,\n\tinsn_sll = 99,\n\tinsn_sllv = 100,\n\tinsn_slt = 101,\n\tinsn_slti = 102,\n\tinsn_sltiu = 103,\n\tinsn_sltu = 104,\n\tinsn_sra = 105,\n\tinsn_srav = 106,\n\tinsn_srl = 107,\n\tinsn_srlv = 108,\n\tinsn_subu = 109,\n\tinsn_sw = 110,\n\tinsn_sync = 111,\n\tinsn_syscall = 112,\n\tinsn_tlbp = 113,\n\tinsn_tlbr = 114,\n\tinsn_tlbwi = 115,\n\tinsn_tlbwr = 116,\n\tinsn_wait = 117,\n\tinsn_wsbh = 118,\n\tinsn_xor = 119,\n\tinsn_xori = 120,\n\tinsn_yield = 121,\n\tinsn_invalid = 122,\n};\n\nenum open_claim_type4 {\n\tNFS4_OPEN_CLAIM_NULL = 0,\n\tNFS4_OPEN_CLAIM_PREVIOUS = 1,\n\tNFS4_OPEN_CLAIM_DELEGATE_CUR = 2,\n\tNFS4_OPEN_CLAIM_DELEGATE_PREV = 3,\n\tNFS4_OPEN_CLAIM_FH = 4,\n\tNFS4_OPEN_CLAIM_DELEG_CUR_FH = 5,\n\tNFS4_OPEN_CLAIM_DELEG_PREV_FH = 6,\n};\n\nenum opentype4 {\n\tNFS4_OPEN_NOCREATE = 0,\n\tNFS4_OPEN_CREATE = 1,\n};\n\nenum ovl_copyop {\n\tOVL_COPY = 0,\n\tOVL_CLONE = 1,\n\tOVL_DEDUPE = 2,\n};\n\nenum ovl_entry_flag {\n\tOVL_E_UPPER_ALIAS = 0,\n\tOVL_E_OPAQUE = 1,\n\tOVL_E_CONNECTED = 2,\n\tOVL_E_XWHITEOUTS = 3,\n};\n\nenum ovl_inode_flag {\n\tOVL_IMPURE = 0,\n\tOVL_WHITEOUTS = 1,\n\tOVL_INDEX = 2,\n\tOVL_UPPERDATA = 3,\n\tOVL_CONST_INO = 4,\n\tOVL_HAS_DIGEST = 5,\n\tOVL_VERIFIED_DIGEST = 6,\n};\n\nenum ovl_opt {\n\tOpt_lowerdir = 0,\n\tOpt_lowerdir_add = 1,\n\tOpt_datadir_add = 2,\n\tOpt_upperdir = 3,\n\tOpt_workdir = 4,\n\tOpt_default_permissions = 5,\n\tOpt_redirect_dir = 6,\n\tOpt_index = 7,\n\tOpt_uuid = 8,\n\tOpt_nfs_export = 9,\n\tOpt_userxattr = 10,\n\tOpt_xino = 11,\n\tOpt_metacopy = 12,\n\tOpt_verity = 13,\n\tOpt_volatile = 14,\n\tOpt_override_creds = 15,\n};\n\nenum ovl_path_type {\n\t__OVL_PATH_UPPER = 1,\n\t__OVL_PATH_MERGE = 2,\n\t__OVL_PATH_ORIGIN = 4,\n};\n\nenum ovl_xattr {\n\tOVL_XATTR_OPAQUE = 0,\n\tOVL_XATTR_REDIRECT = 1,\n\tOVL_XATTR_ORIGIN = 2,\n\tOVL_XATTR_IMPURE = 3,\n\tOVL_XATTR_NLINK = 4,\n\tOVL_XATTR_UPPER = 5,\n\tOVL_XATTR_UUID = 6,\n\tOVL_XATTR_METACOPY = 7,\n\tOVL_XATTR_PROTATTR = 8,\n\tOVL_XATTR_XWHITEOUT = 9,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum p9_fid_reftype {\n\tP9_FID_REF_CREATE = 0,\n\tP9_FID_REF_GET = 1,\n\tP9_FID_REF_PUT = 2,\n\tP9_FID_REF_DESTROY = 3,\n} __attribute__((mode(byte)));\n\nenum p9_msg_t {\n\tP9_TLERROR = 6,\n\tP9_RLERROR = 7,\n\tP9_TSTATFS = 8,\n\tP9_RSTATFS = 9,\n\tP9_TLOPEN = 12,\n\tP9_RLOPEN = 13,\n\tP9_TLCREATE = 14,\n\tP9_RLCREATE = 15,\n\tP9_TSYMLINK = 16,\n\tP9_RSYMLINK = 17,\n\tP9_TMKNOD = 18,\n\tP9_RMKNOD = 19,\n\tP9_TRENAME = 20,\n\tP9_RRENAME = 21,\n\tP9_TREADLINK = 22,\n\tP9_RREADLINK = 23,\n\tP9_TGETATTR = 24,\n\tP9_RGETATTR = 25,\n\tP9_TSETATTR = 26,\n\tP9_RSETATTR = 27,\n\tP9_TXATTRWALK = 30,\n\tP9_RXATTRWALK = 31,\n\tP9_TXATTRCREATE = 32,\n\tP9_RXATTRCREATE = 33,\n\tP9_TREADDIR = 40,\n\tP9_RREADDIR = 41,\n\tP9_TFSYNC = 50,\n\tP9_RFSYNC = 51,\n\tP9_TLOCK = 52,\n\tP9_RLOCK = 53,\n\tP9_TGETLOCK = 54,\n\tP9_RGETLOCK = 55,\n\tP9_TLINK = 70,\n\tP9_RLINK = 71,\n\tP9_TMKDIR = 72,\n\tP9_RMKDIR = 73,\n\tP9_TRENAMEAT = 74,\n\tP9_RRENAMEAT = 75,\n\tP9_TUNLINKAT = 76,\n\tP9_RUNLINKAT = 77,\n\tP9_TVERSION = 100,\n\tP9_RVERSION = 101,\n\tP9_TAUTH = 102,\n\tP9_RAUTH = 103,\n\tP9_TATTACH = 104,\n\tP9_RATTACH = 105,\n\tP9_TERROR = 106,\n\tP9_RERROR = 107,\n\tP9_TFLUSH = 108,\n\tP9_RFLUSH = 109,\n\tP9_TWALK = 110,\n\tP9_RWALK = 111,\n\tP9_TOPEN = 112,\n\tP9_ROPEN = 113,\n\tP9_TCREATE = 114,\n\tP9_RCREATE = 115,\n\tP9_TREAD = 116,\n\tP9_RREAD = 117,\n\tP9_TWRITE = 118,\n\tP9_RWRITE = 119,\n\tP9_TCLUNK = 120,\n\tP9_RCLUNK = 121,\n\tP9_TREMOVE = 122,\n\tP9_RREMOVE = 123,\n\tP9_TSTAT = 124,\n\tP9_RSTAT = 125,\n\tP9_TWSTAT = 126,\n\tP9_RWSTAT = 127,\n};\n\nenum p9_open_mode_t {\n\tP9_OREAD = 0,\n\tP9_OWRITE = 1,\n\tP9_ORDWR = 2,\n\tP9_OEXEC = 3,\n\tP9_OTRUNC = 16,\n\tP9_OREXEC = 32,\n\tP9_ORCLOSE = 64,\n\tP9_OAPPEND = 128,\n\tP9_OEXCL = 4096,\n\tP9L_MODE_MASK = 8191,\n\tP9L_DIRECT = 8192,\n\tP9L_NOWRITECACHE = 16384,\n\tP9L_LOOSE = 32768,\n};\n\nenum p9_proto_versions {\n\tp9_proto_legacy = 0,\n\tp9_proto_2000u = 1,\n\tp9_proto_2000L = 2,\n};\n\nenum p9_req_status_t {\n\tREQ_STATUS_ALLOC = 0,\n\tREQ_STATUS_UNSENT = 1,\n\tREQ_STATUS_SENT = 2,\n\tREQ_STATUS_RCVD = 3,\n\tREQ_STATUS_FLSHD = 4,\n\tREQ_STATUS_ERROR = 5,\n};\n\nenum p9_trans_status {\n\tConnected = 0,\n\tBeginDisconnect = 1,\n\tDisconnected = 2,\n\tHung = 3,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum packets_types {\n\tPACKET_AVCPQ = 1,\n\tPACKET_PTPQ = 2,\n\tPACKET_DCBCPQ = 3,\n\tPACKET_UPQ = 4,\n\tPACKET_MCBCQ = 5,\n};\n\nenum packing_op {\n\tPACK = 0,\n\tUNPACK = 1,\n};\n\nenum page_memcg_data_flags {\n\tMEMCG_DATA_OBJEXTS = 1,\n\tMEMCG_DATA_KMEM = 2,\n\t__NR_MEMCG_DATA_FLAGS = 4,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 4096,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\t__NR_PAGEBLOCK_BITS = 4,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\t__NR_PAGEFLAGS = 21,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nenum pce_status {\n\tPCE_STATUS_NONE = 0,\n\tPCE_STATUS_ACQUIRED = 1,\n\tPCE_STATUS_PREPARED = 2,\n\tPCE_STATUS_ENABLED = 3,\n\tPCE_STATUS_ERROR = 4,\n};\n\nenum pch_dma_width {\n\tPCH_DMA_WIDTH_1_BYTE = 0,\n\tPCH_DMA_WIDTH_2_BYTES = 1,\n\tPCH_DMA_WIDTH_4_BYTES = 2,\n};\n\nenum pch_status {\n\tPCH_SUCCESS = 0,\n\tPCH_INVALIDPARAM = 1,\n\tPCH_NOTIMESTAMP = 2,\n\tPCH_INTERRUPTMODEINUSE = 3,\n\tPCH_FAILED = 4,\n\tPCH_UNSUPPORTED = 5,\n};\n\nenum pch_type_t {\n\tINTEL_EG20T_PCH = 0,\n\tOKISEMI_ML7223m_IOH = 1,\n\tOKISEMI_ML7223n_IOH = 2,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_15625000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_oxsemi = 71,\n\tpbn_oxsemi_1_15625000 = 72,\n\tpbn_oxsemi_2_15625000 = 73,\n\tpbn_oxsemi_4_15625000 = 74,\n\tpbn_oxsemi_8_15625000 = 75,\n\tpbn_intel_i960 = 76,\n\tpbn_sgi_ioc3 = 77,\n\tpbn_computone_4 = 78,\n\tpbn_computone_6 = 79,\n\tpbn_computone_8 = 80,\n\tpbn_sbsxrsio = 81,\n\tpbn_pasemi_1682M = 82,\n\tpbn_ni8430_2 = 83,\n\tpbn_ni8430_4 = 84,\n\tpbn_ni8430_8 = 85,\n\tpbn_ni8430_16 = 86,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 87,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 90,\n\tpbn_ce4100_1_115200 = 91,\n\tpbn_omegapci = 92,\n\tpbn_NETMOS9900_2s_115200 = 93,\n\tpbn_brcm_trumanage = 94,\n\tpbn_fintek_4 = 95,\n\tpbn_fintek_8 = 96,\n\tpbn_fintek_12 = 97,\n\tpbn_fintek_F81504A = 98,\n\tpbn_fintek_F81508A = 99,\n\tpbn_fintek_F81512A = 100,\n\tpbn_wch382_2 = 101,\n\tpbn_wch384_4 = 102,\n\tpbn_wch384_8 = 103,\n\tpbn_sunix_pci_1s = 104,\n\tpbn_sunix_pci_2s = 105,\n\tpbn_sunix_pci_4s = 106,\n\tpbn_sunix_pci_8s = 107,\n\tpbn_sunix_pci_16s = 108,\n\tpbn_titan_1_4000000 = 109,\n\tpbn_titan_2_4000000 = 110,\n\tpbn_titan_4_4000000 = 111,\n\tpbn_titan_8_4000000 = 112,\n\tpbn_moxa_2 = 113,\n\tpbn_moxa_4 = 114,\n\tpbn_moxa_8 = 115,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_interrupt_pin {\n\tPCI_INTERRUPT_UNKNOWN = 0,\n\tPCI_INTERRUPT_INTA = 1,\n\tPCI_INTERRUPT_INTB = 2,\n\tPCI_INTERRUPT_INTC = 3,\n\tPCI_INTERRUPT_INTD = 4,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_bits {\n\t_PAGE_PRESENT_SHIFT = 0,\n\t_PAGE_WRITE_SHIFT = 1,\n\t_PAGE_ACCESSED_SHIFT = 2,\n\t_PAGE_MODIFIED_SHIFT = 3,\n\t_PAGE_NO_EXEC_SHIFT = 4,\n\t_PAGE_NO_READ_SHIFT = 5,\n\t_PAGE_GLOBAL_SHIFT = 6,\n\t_PAGE_VALID_SHIFT = 7,\n\t_PAGE_DIRTY_SHIFT = 8,\n\t_CACHE_SHIFT = 9,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum phy_led_modes {\n\tPHY_LED_ACTIVE_HIGH = 0,\n\tPHY_LED_ACTIVE_LOW = 1,\n\tPHY_LED_INACTIVE_HIGH_IMPEDANCE = 2,\n\t__PHY_LED_MODES_NUM = 3,\n};\n\nenum phy_media {\n\tPHY_MEDIA_DEFAULT = 0,\n\tPHY_MEDIA_SR = 1,\n\tPHY_MEDIA_DAC = 2,\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n\tPHY_MODE_HDMI = 20,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_port_parent {\n\tPHY_PORT_PHY = 0,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_state_work {\n\tPHY_STATE_WORK_NONE = 0,\n\tPHY_STATE_WORK_ANEG = 1,\n\tPHY_STATE_WORK_SUSPEND = 2,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_ufs_state {\n\tPHY_UFS_HIBERN8_ENTER = 0,\n\tPHY_UFS_HIBERN8_EXIT = 1,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum phylink_op_type {\n\tPHYLINK_NETDEV = 0,\n\tPHYLINK_DEV = 1,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidcg_event {\n\tPIDCG_MAX = 0,\n\tPIDCG_FORKFAIL = 1,\n\tNR_PIDCG_EVENTS = 2,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum pin_config_param {\n\tPIN_CONFIG_BIAS_BUS_HOLD = 0,\n\tPIN_CONFIG_BIAS_DISABLE = 1,\n\tPIN_CONFIG_BIAS_HIGH_IMPEDANCE = 2,\n\tPIN_CONFIG_BIAS_PULL_DOWN = 3,\n\tPIN_CONFIG_BIAS_PULL_PIN_DEFAULT = 4,\n\tPIN_CONFIG_BIAS_PULL_UP = 5,\n\tPIN_CONFIG_DRIVE_OPEN_DRAIN = 6,\n\tPIN_CONFIG_DRIVE_OPEN_SOURCE = 7,\n\tPIN_CONFIG_DRIVE_PUSH_PULL = 8,\n\tPIN_CONFIG_DRIVE_STRENGTH = 9,\n\tPIN_CONFIG_DRIVE_STRENGTH_UA = 10,\n\tPIN_CONFIG_INPUT_DEBOUNCE = 11,\n\tPIN_CONFIG_INPUT_ENABLE = 12,\n\tPIN_CONFIG_INPUT_SCHMITT = 13,\n\tPIN_CONFIG_INPUT_SCHMITT_ENABLE = 14,\n\tPIN_CONFIG_INPUT_SCHMITT_UV = 15,\n\tPIN_CONFIG_MODE_LOW_POWER = 16,\n\tPIN_CONFIG_MODE_PWM = 17,\n\tPIN_CONFIG_LEVEL = 18,\n\tPIN_CONFIG_OUTPUT_ENABLE = 19,\n\tPIN_CONFIG_OUTPUT_IMPEDANCE_OHMS = 20,\n\tPIN_CONFIG_PERSIST_STATE = 21,\n\tPIN_CONFIG_POWER_SOURCE = 22,\n\tPIN_CONFIG_SKEW_DELAY = 23,\n\tPIN_CONFIG_SKEW_DELAY_INPUT_PS = 24,\n\tPIN_CONFIG_SKEW_DELAY_OUTPUT_PS = 25,\n\tPIN_CONFIG_SLEEP_HARDWARE_STATE = 26,\n\tPIN_CONFIG_SLEW_RATE = 27,\n\tPIN_CONFIG_END = 127,\n\tPIN_CONFIG_MAX = 255,\n};\n\nenum pinctrl_map_type {\n\tPIN_MAP_TYPE_INVALID = 0,\n\tPIN_MAP_TYPE_DUMMY_STATE = 1,\n\tPIN_MAP_TYPE_MUX_GROUP = 2,\n\tPIN_MAP_TYPE_CONFIGS_PIN = 3,\n\tPIN_MAP_TYPE_CONFIGS_GROUP = 4,\n};\n\nenum pistachio_mux_option {\n\tPISTACHIO_FUNCTION_NONE = -1,\n\tPISTACHIO_FUNCTION_SPIM0 = 0,\n\tPISTACHIO_FUNCTION_SPIM1 = 1,\n\tPISTACHIO_FUNCTION_SPIS = 2,\n\tPISTACHIO_FUNCTION_SDHOST = 3,\n\tPISTACHIO_FUNCTION_I2C0 = 4,\n\tPISTACHIO_FUNCTION_I2C1 = 5,\n\tPISTACHIO_FUNCTION_I2C2 = 6,\n\tPISTACHIO_FUNCTION_I2C3 = 7,\n\tPISTACHIO_FUNCTION_AUDIO_CLK_IN = 8,\n\tPISTACHIO_FUNCTION_I2S_OUT = 9,\n\tPISTACHIO_FUNCTION_I2S_DAC_CLK = 10,\n\tPISTACHIO_FUNCTION_AUDIO_SYNC = 11,\n\tPISTACHIO_FUNCTION_AUDIO_TRIGGER = 12,\n\tPISTACHIO_FUNCTION_I2S_IN = 13,\n\tPISTACHIO_FUNCTION_UART0 = 14,\n\tPISTACHIO_FUNCTION_UART1 = 15,\n\tPISTACHIO_FUNCTION_SPDIF_OUT = 16,\n\tPISTACHIO_FUNCTION_SPDIF_IN = 17,\n\tPISTACHIO_FUNCTION_ETH = 18,\n\tPISTACHIO_FUNCTION_IR = 19,\n\tPISTACHIO_FUNCTION_PWMPDM = 20,\n\tPISTACHIO_FUNCTION_MIPS_TRACE_CLK = 21,\n\tPISTACHIO_FUNCTION_MIPS_TRACE_DINT = 22,\n\tPISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT = 23,\n\tPISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN = 24,\n\tPISTACHIO_FUNCTION_MIPS_TRACE_DM = 25,\n\tPISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N = 26,\n\tPISTACHIO_FUNCTION_MIPS_TRACE_DATA = 27,\n\tPISTACHIO_FUNCTION_SRAM_DEBUG = 28,\n\tPISTACHIO_FUNCTION_ROM_DEBUG = 29,\n\tPISTACHIO_FUNCTION_RPU_DEBUG = 30,\n\tPISTACHIO_FUNCTION_MIPS_DEBUG = 31,\n\tPISTACHIO_FUNCTION_ETH_DEBUG = 32,\n\tPISTACHIO_FUNCTION_USB_DEBUG = 33,\n\tPISTACHIO_FUNCTION_SDHOST_DEBUG = 34,\n\tPISTACHIO_FUNCTION_SOCIF_DEBUG = 35,\n\tPISTACHIO_FUNCTION_MDC_DEBUG = 36,\n\tPISTACHIO_FUNCTION_DDR_DEBUG = 37,\n\tPISTACHIO_FUNCTION_DREQ0 = 38,\n\tPISTACHIO_FUNCTION_DREQ1 = 39,\n\tPISTACHIO_FUNCTION_DREQ2 = 40,\n\tPISTACHIO_FUNCTION_DREQ3 = 41,\n\tPISTACHIO_FUNCTION_DREQ4 = 42,\n\tPISTACHIO_FUNCTION_DREQ5 = 43,\n\tPISTACHIO_FUNCTION_MIPS_PLL_LOCK = 44,\n\tPISTACHIO_FUNCTION_AUDIO_PLL_LOCK = 45,\n\tPISTACHIO_FUNCTION_RPU_V_PLL_LOCK = 46,\n\tPISTACHIO_FUNCTION_RPU_L_PLL_LOCK = 47,\n\tPISTACHIO_FUNCTION_SYS_PLL_LOCK = 48,\n\tPISTACHIO_FUNCTION_WIFI_PLL_LOCK = 49,\n\tPISTACHIO_FUNCTION_BT_PLL_LOCK = 50,\n\tPISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND = 51,\n\tPISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND = 52,\n\tPISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND = 53,\n\tPISTACHIO_FUNCTION_DEBUG_AGC_DONE_0 = 54,\n\tPISTACHIO_FUNCTION_DEBUG_AGC_DONE_1 = 55,\n\tPISTACHIO_FUNCTION_DEBUG_ED_CCA_IND = 56,\n\tPISTACHIO_FUNCTION_DEBUG_S2L_DONE = 57,\n};\n\nenum pistachio_pll_type {\n\tPLL_GF40LP_LAINT = 0,\n\tPLL_GF40LP_FRAC = 1,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum pll_mode {\n\tPLL_MODE_FRAC = 0,\n\tPLL_MODE_INT = 1,\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = -1,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum pnfs_iomode {\n\tIOMODE_READ = 1,\n\tIOMODE_RW = 2,\n\tIOMODE_ANY = 3,\n};\n\nenum pnfs_layout_destroy_mode {\n\tPNFS_LAYOUT_INVALIDATE = 0,\n\tPNFS_LAYOUT_BULK_RETURN = 1,\n\tPNFS_LAYOUT_FILE_BULK_RETURN = 2,\n};\n\nenum pnfs_layoutreturn_type {\n\tRETURN_FILE = 1,\n\tRETURN_FSID = 2,\n\tRETURN_ALL = 3,\n};\n\nenum pnfs_layouttype {\n\tLAYOUT_NFSV4_1_FILES = 1,\n\tLAYOUT_OSD2_OBJECTS = 2,\n\tLAYOUT_BLOCK_VOLUME = 3,\n\tLAYOUT_FLEX_FILES = 4,\n\tLAYOUT_SCSI = 5,\n\tLAYOUT_TYPE_MAX = 6,\n};\n\nenum pnfs_notify_deviceid_type4 {\n\tNOTIFY_DEVICEID4_CHANGE = 2,\n\tNOTIFY_DEVICEID4_DELETE = 4,\n};\n\nenum pnfs_try_status {\n\tPNFS_ATTEMPTED = 0,\n\tPNFS_NOT_ATTEMPTED = 1,\n\tPNFS_TRY_AGAIN = 2,\n};\n\nenum pnfs_update_layout_reason {\n\tPNFS_UPDATE_LAYOUT_UNKNOWN = 0,\n\tPNFS_UPDATE_LAYOUT_NO_PNFS = 1,\n\tPNFS_UPDATE_LAYOUT_RD_ZEROLEN = 2,\n\tPNFS_UPDATE_LAYOUT_MDSTHRESH = 3,\n\tPNFS_UPDATE_LAYOUT_NOMEM = 4,\n\tPNFS_UPDATE_LAYOUT_BULK_RECALL = 5,\n\tPNFS_UPDATE_LAYOUT_IO_TEST_FAIL = 6,\n\tPNFS_UPDATE_LAYOUT_FOUND_CACHED = 7,\n\tPNFS_UPDATE_LAYOUT_RETURN = 8,\n\tPNFS_UPDATE_LAYOUT_RETRY = 9,\n\tPNFS_UPDATE_LAYOUT_BLOCKED = 10,\n\tPNFS_UPDATE_LAYOUT_INVALID_OPEN = 11,\n\tPNFS_UPDATE_LAYOUT_SEND_LAYOUTGET = 12,\n\tPNFS_UPDATE_LAYOUT_EXIT = 13,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port_pkey_state {\n\tIB_PORT_PKEY_NOT_VALID = 0,\n\tIB_PORT_PKEY_VALID = 1,\n\tIB_PORT_PKEY_LISTED = 2,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum power_event {\n\tpointer_reset = 2147483648,\n\tglobal_unicast = 512,\n\twake_up_rx_frame = 64,\n\tmagic_frame = 32,\n\twake_up_frame_en = 4,\n\tmagic_pkt_en = 2,\n\tpower_down = 1,\n};\n\nenum power_supply_charge_behaviour {\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO = 0,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE = 1,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE_AWAKE = 2,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE = 3,\n};\n\nenum power_supply_charge_type {\n\tPOWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_CHARGE_TYPE_NONE = 1,\n\tPOWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2,\n\tPOWER_SUPPLY_CHARGE_TYPE_FAST = 3,\n\tPOWER_SUPPLY_CHARGE_TYPE_STANDARD = 4,\n\tPOWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5,\n\tPOWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6,\n\tPOWER_SUPPLY_CHARGE_TYPE_LONGLIFE = 7,\n\tPOWER_SUPPLY_CHARGE_TYPE_BYPASS = 8,\n};\n\nenum power_supply_notifier_events {\n\tPSY_EVENT_PROP_CHANGED = 0,\n};\n\nenum power_supply_property {\n\tPOWER_SUPPLY_PROP_STATUS = 0,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPE = 1,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPES = 2,\n\tPOWER_SUPPLY_PROP_HEALTH = 3,\n\tPOWER_SUPPLY_PROP_PRESENT = 4,\n\tPOWER_SUPPLY_PROP_ONLINE = 5,\n\tPOWER_SUPPLY_PROP_AUTHENTIC = 6,\n\tPOWER_SUPPLY_PROP_TECHNOLOGY = 7,\n\tPOWER_SUPPLY_PROP_CYCLE_COUNT = 8,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX = 9,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN = 10,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN = 11,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN = 12,\n\tPOWER_SUPPLY_PROP_VOLTAGE_NOW = 13,\n\tPOWER_SUPPLY_PROP_VOLTAGE_AVG = 14,\n\tPOWER_SUPPLY_PROP_VOLTAGE_OCV = 15,\n\tPOWER_SUPPLY_PROP_VOLTAGE_BOOT = 16,\n\tPOWER_SUPPLY_PROP_CURRENT_MAX = 17,\n\tPOWER_SUPPLY_PROP_CURRENT_NOW = 18,\n\tPOWER_SUPPLY_PROP_CURRENT_AVG = 19,\n\tPOWER_SUPPLY_PROP_CURRENT_BOOT = 20,\n\tPOWER_SUPPLY_PROP_POWER_NOW = 21,\n\tPOWER_SUPPLY_PROP_POWER_AVG = 22,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL_DESIGN = 23,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN = 24,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL = 25,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY = 26,\n\tPOWER_SUPPLY_PROP_CHARGE_NOW = 27,\n\tPOWER_SUPPLY_PROP_CHARGE_AVG = 28,\n\tPOWER_SUPPLY_PROP_CHARGE_COUNTER = 29,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT = 30,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX = 31,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE = 32,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX = 33,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT = 34,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX = 35,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD = 36,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD = 37,\n\tPOWER_SUPPLY_PROP_CHARGE_BEHAVIOUR = 38,\n\tPOWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT = 39,\n\tPOWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT = 40,\n\tPOWER_SUPPLY_PROP_INPUT_POWER_LIMIT = 41,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL_DESIGN = 42,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN = 43,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL = 44,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY = 45,\n\tPOWER_SUPPLY_PROP_ENERGY_NOW = 46,\n\tPOWER_SUPPLY_PROP_ENERGY_AVG = 47,\n\tPOWER_SUPPLY_PROP_CAPACITY = 48,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MIN = 49,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MAX = 50,\n\tPOWER_SUPPLY_PROP_CAPACITY_ERROR_MARGIN = 51,\n\tPOWER_SUPPLY_PROP_CAPACITY_LEVEL = 52,\n\tPOWER_SUPPLY_PROP_TEMP = 53,\n\tPOWER_SUPPLY_PROP_TEMP_MAX = 54,\n\tPOWER_SUPPLY_PROP_TEMP_MIN = 55,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MIN = 56,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MAX = 57,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT = 58,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN = 59,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX = 60,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW = 61,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG = 62,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_NOW = 63,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_AVG = 64,\n\tPOWER_SUPPLY_PROP_TYPE = 65,\n\tPOWER_SUPPLY_PROP_USB_TYPE = 66,\n\tPOWER_SUPPLY_PROP_SCOPE = 67,\n\tPOWER_SUPPLY_PROP_PRECHARGE_CURRENT = 68,\n\tPOWER_SUPPLY_PROP_CHARGE_TERM_CURRENT = 69,\n\tPOWER_SUPPLY_PROP_CALIBRATE = 70,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_YEAR = 71,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_MONTH = 72,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_DAY = 73,\n\tPOWER_SUPPLY_PROP_INTERNAL_RESISTANCE = 74,\n\tPOWER_SUPPLY_PROP_STATE_OF_HEALTH = 75,\n\tPOWER_SUPPLY_PROP_MODEL_NAME = 76,\n\tPOWER_SUPPLY_PROP_MANUFACTURER = 77,\n\tPOWER_SUPPLY_PROP_SERIAL_NUMBER = 78,\n};\n\nenum power_supply_type {\n\tPOWER_SUPPLY_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_TYPE_BATTERY = 1,\n\tPOWER_SUPPLY_TYPE_UPS = 2,\n\tPOWER_SUPPLY_TYPE_MAINS = 3,\n\tPOWER_SUPPLY_TYPE_USB = 4,\n\tPOWER_SUPPLY_TYPE_USB_DCP = 5,\n\tPOWER_SUPPLY_TYPE_USB_CDP = 6,\n\tPOWER_SUPPLY_TYPE_USB_ACA = 7,\n\tPOWER_SUPPLY_TYPE_USB_TYPE_C = 8,\n\tPOWER_SUPPLY_TYPE_USB_PD = 9,\n\tPOWER_SUPPLY_TYPE_USB_PD_DRP = 10,\n\tPOWER_SUPPLY_TYPE_APPLE_BRICK_ID = 11,\n\tPOWER_SUPPLY_TYPE_WIRELESS = 12,\n};\n\nenum power_supply_usb_type {\n\tPOWER_SUPPLY_USB_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_USB_TYPE_SDP = 1,\n\tPOWER_SUPPLY_USB_TYPE_DCP = 2,\n\tPOWER_SUPPLY_USB_TYPE_CDP = 3,\n\tPOWER_SUPPLY_USB_TYPE_ACA = 4,\n\tPOWER_SUPPLY_USB_TYPE_C = 5,\n\tPOWER_SUPPLY_USB_TYPE_PD = 6,\n\tPOWER_SUPPLY_USB_TYPE_PD_DRP = 7,\n\tPOWER_SUPPLY_USB_TYPE_PD_PPS = 8,\n\tPOWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID = 9,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___4 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum ps2_disposition {\n\tPS2_PROCESS = 0,\n\tPS2_IGNORE = 1,\n\tPS2_ERROR = 2,\n};\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum pt_watch_style {\n\tpt_watch_style_mips32 = 0,\n\tpt_watch_style_mips64 = 1,\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_EXTOFF = 2,\n\tPTP_CLOCK_PPS = 3,\n\tPTP_CLOCK_PPSUSR = 4,\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nenum ptw_func {\n\tlwdir_op = 0,\n\tlwpte_op = 1,\n\tlddir_op = 2,\n\tldpte_op = 3,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum ramfs_param {\n\tOpt_mode___3 = 0,\n};\n\nenum rdma_ah_attr_type {\n\tRDMA_AH_ATTR_TYPE_UNDEFINED = 0,\n\tRDMA_AH_ATTR_TYPE_IB = 1,\n\tRDMA_AH_ATTR_TYPE_ROCE = 2,\n\tRDMA_AH_ATTR_TYPE_OPA = 3,\n};\n\nenum rdma_driver_id {\n\tRDMA_DRIVER_UNKNOWN = 0,\n\tRDMA_DRIVER_MLX5 = 1,\n\tRDMA_DRIVER_MLX4 = 2,\n\tRDMA_DRIVER_CXGB3 = 3,\n\tRDMA_DRIVER_CXGB4 = 4,\n\tRDMA_DRIVER_MTHCA = 5,\n\tRDMA_DRIVER_BNXT_RE = 6,\n\tRDMA_DRIVER_OCRDMA = 7,\n\tRDMA_DRIVER_NES = 8,\n\tRDMA_DRIVER_I40IW = 9,\n\tRDMA_DRIVER_IRDMA = 9,\n\tRDMA_DRIVER_VMW_PVRDMA = 10,\n\tRDMA_DRIVER_QEDR = 11,\n\tRDMA_DRIVER_HNS = 12,\n\tRDMA_DRIVER_USNIC = 13,\n\tRDMA_DRIVER_RXE = 14,\n\tRDMA_DRIVER_HFI1 = 15,\n\tRDMA_DRIVER_QIB = 16,\n\tRDMA_DRIVER_EFA = 17,\n\tRDMA_DRIVER_SIW = 18,\n\tRDMA_DRIVER_ERDMA = 19,\n\tRDMA_DRIVER_MANA = 20,\n\tRDMA_DRIVER_IONIC = 21,\n};\n\nenum rdma_link_layer {\n\tIB_LINK_LAYER_UNSPECIFIED = 0,\n\tIB_LINK_LAYER_INFINIBAND = 1,\n\tIB_LINK_LAYER_ETHERNET = 2,\n};\n\nenum rdma_netdev_t {\n\tRDMA_NETDEV_OPA_VNIC = 0,\n\tRDMA_NETDEV_IPOIB = 1,\n};\n\nenum rdma_nl_counter_mask {\n\tRDMA_COUNTER_MASK_QP_TYPE = 1,\n\tRDMA_COUNTER_MASK_PID = 2,\n};\n\nenum rdma_nl_counter_mode {\n\tRDMA_COUNTER_MODE_NONE = 0,\n\tRDMA_COUNTER_MODE_AUTO = 1,\n\tRDMA_COUNTER_MODE_MANUAL = 2,\n\tRDMA_COUNTER_MODE_MAX = 3,\n};\n\nenum rdma_nl_dev_type {\n\tRDMA_DEVICE_TYPE_SMI = 1,\n};\n\nenum rdma_nl_name_assign_type {\n\tRDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0,\n\tRDMA_NAME_ASSIGN_TYPE_USER = 1,\n};\n\nenum rdma_restrack_type {\n\tRDMA_RESTRACK_PD = 0,\n\tRDMA_RESTRACK_CQ = 1,\n\tRDMA_RESTRACK_QP = 2,\n\tRDMA_RESTRACK_CM_ID = 3,\n\tRDMA_RESTRACK_MR = 4,\n\tRDMA_RESTRACK_CTX = 5,\n\tRDMA_RESTRACK_COUNTER = 6,\n\tRDMA_RESTRACK_SRQ = 7,\n\tRDMA_RESTRACK_DMAH = 8,\n\tRDMA_RESTRACK_MAX = 9,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_FLAT = 2,\n\tREGCACHE_MAPLE = 3,\n\tREGCACHE_FLAT_S = 4,\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nenum regulator_active_discharge {\n\tREGULATOR_ACTIVE_DISCHARGE_DEFAULT = 0,\n\tREGULATOR_ACTIVE_DISCHARGE_DISABLE = 1,\n\tREGULATOR_ACTIVE_DISCHARGE_ENABLE = 2,\n};\n\nenum regulator_detection_severity {\n\tREGULATOR_SEVERITY_PROT = 0,\n\tREGULATOR_SEVERITY_ERR = 1,\n\tREGULATOR_SEVERITY_WARN = 2,\n};\n\nenum regulator_get_type {\n\tNORMAL_GET = 0,\n\tEXCLUSIVE_GET = 1,\n\tOPTIONAL_GET = 2,\n\tMAX_GET_TYPE = 3,\n};\n\nenum regulator_status {\n\tREGULATOR_STATUS_OFF = 0,\n\tREGULATOR_STATUS_ON = 1,\n\tREGULATOR_STATUS_ERROR = 2,\n\tREGULATOR_STATUS_FAST = 3,\n\tREGULATOR_STATUS_NORMAL = 4,\n\tREGULATOR_STATUS_IDLE = 5,\n\tREGULATOR_STATUS_STANDBY = 6,\n\tREGULATOR_STATUS_BYPASS = 7,\n\tREGULATOR_STATUS_UNDEFINED = 8,\n};\n\nenum regulator_type {\n\tREGULATOR_VOLTAGE = 0,\n\tREGULATOR_CURRENT = 1,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum request_irq_err {\n\tREQ_IRQ_ERR_ALL = 0,\n\tREQ_IRQ_ERR_TX = 1,\n\tREQ_IRQ_ERR_RX = 2,\n\tREQ_IRQ_ERR_SFTY = 3,\n\tREQ_IRQ_ERR_SFTY_UE = 4,\n\tREQ_IRQ_ERR_SFTY_CE = 5,\n\tREQ_IRQ_ERR_WOL = 6,\n\tREQ_IRQ_ERR_MAC = 7,\n\tREQ_IRQ_ERR_NO = 8,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reset_control_flags {\n\tRESET_CONTROL_EXCLUSIVE = 4,\n\tRESET_CONTROL_EXCLUSIVE_DEASSERTED = 12,\n\tRESET_CONTROL_EXCLUSIVE_RELEASED = 0,\n\tRESET_CONTROL_SHARED = 1,\n\tRESET_CONTROL_SHARED_DEASSERTED = 9,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE = 6,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_DEASSERTED = 14,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_RELEASED = 2,\n\tRESET_CONTROL_OPTIONAL_SHARED = 3,\n\tRESET_CONTROL_OPTIONAL_SHARED_DEASSERTED = 11,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum rgmii_clock_delay {\n\tRGMII_CLK_DELAY_0_2_NS = 0,\n\tRGMII_CLK_DELAY_0_8_NS = 1,\n\tRGMII_CLK_DELAY_1_1_NS = 2,\n\tRGMII_CLK_DELAY_1_7_NS = 3,\n\tRGMII_CLK_DELAY_2_0_NS = 4,\n\tRGMII_CLK_DELAY_2_3_NS = 5,\n\tRGMII_CLK_DELAY_2_6_NS = 6,\n\tRGMII_CLK_DELAY_3_4_NS = 7,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rpc_accept_stat {\n\tRPC_SUCCESS = 0,\n\tRPC_PROG_UNAVAIL = 1,\n\tRPC_PROG_MISMATCH = 2,\n\tRPC_PROC_UNAVAIL = 3,\n\tRPC_GARBAGE_ARGS = 4,\n\tRPC_SYSTEM_ERR = 5,\n\tRPC_DROP_REPLY = 60000,\n};\n\nenum rpc_auth_flavors {\n\tRPC_AUTH_NULL = 0,\n\tRPC_AUTH_UNIX = 1,\n\tRPC_AUTH_SHORT = 2,\n\tRPC_AUTH_DES = 3,\n\tRPC_AUTH_KRB = 4,\n\tRPC_AUTH_GSS = 6,\n\tRPC_AUTH_TLS = 7,\n\tRPC_AUTH_MAXFLAVOR = 8,\n\tRPC_AUTH_GSS_KRB5 = 390003,\n\tRPC_AUTH_GSS_KRB5I = 390004,\n\tRPC_AUTH_GSS_KRB5P = 390005,\n\tRPC_AUTH_GSS_LKEY = 390006,\n\tRPC_AUTH_GSS_LKEYI = 390007,\n\tRPC_AUTH_GSS_LKEYP = 390008,\n\tRPC_AUTH_GSS_SPKM = 390009,\n\tRPC_AUTH_GSS_SPKMI = 390010,\n\tRPC_AUTH_GSS_SPKMP = 390011,\n};\n\nenum rpc_auth_stat {\n\tRPC_AUTH_OK = 0,\n\tRPC_AUTH_BADCRED = 1,\n\tRPC_AUTH_REJECTEDCRED = 2,\n\tRPC_AUTH_BADVERF = 3,\n\tRPC_AUTH_REJECTEDVERF = 4,\n\tRPC_AUTH_TOOWEAK = 5,\n\tRPC_AUTH_INVALIDRESP = 6,\n\tRPC_AUTH_FAILED = 7,\n\tRPCSEC_GSS_CREDPROBLEM = 13,\n\tRPCSEC_GSS_CTXPROBLEM = 14,\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum rpc_gss_proc {\n\tRPC_GSS_PROC_DATA = 0,\n\tRPC_GSS_PROC_INIT = 1,\n\tRPC_GSS_PROC_CONTINUE_INIT = 2,\n\tRPC_GSS_PROC_DESTROY = 3,\n};\n\nenum rpc_gss_svc {\n\tRPC_GSS_SVC_NONE = 1,\n\tRPC_GSS_SVC_INTEGRITY = 2,\n\tRPC_GSS_SVC_PRIVACY = 3,\n};\n\nenum rpc_msg_type {\n\tRPC_CALL = 0,\n\tRPC_REPLY = 1,\n};\n\nenum rpc_reject_stat {\n\tRPC_MISMATCH = 0,\n\tRPC_AUTH_ERROR = 1,\n};\n\nenum rpc_reply_stat {\n\tRPC_MSG_ACCEPTED = 0,\n\tRPC_MSG_DENIED = 1,\n};\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rpmb_type {\n\tRPMB_TYPE_EMMC = 0,\n\tRPMB_TYPE_UFS = 1,\n\tRPMB_TYPE_NVME = 2,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rt6_nud_state {\n\tRT6_NUD_FAIL_HARD = -3,\n\tRT6_NUD_FAIL_PROBE = -2,\n\tRT6_NUD_FAIL_DO_RR = -1,\n\tRT6_NUD_SUCCEED = 1,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_op {\n\tbltz_op = 0,\n\tbgez_op = 1,\n\tbltzl_op = 2,\n\tbgezl_op = 3,\n\tspimi_op = 4,\n\tunused_rt_op_0x05 = 5,\n\tunused_rt_op_0x06 = 6,\n\tunused_rt_op_0x07 = 7,\n\ttgei_op = 8,\n\ttgeiu_op = 9,\n\ttlti_op = 10,\n\ttltiu_op = 11,\n\tteqi_op = 12,\n\tunused_0x0d_rt_op = 13,\n\ttnei_op = 14,\n\tunused_0x0f_rt_op = 15,\n\tbltzal_op = 16,\n\tbgezal_op = 17,\n\tbltzall_op = 18,\n\tbgezall_op = 19,\n\trt_op_0x14 = 20,\n\trt_op_0x15 = 21,\n\trt_op_0x16 = 22,\n\trt_op_0x17 = 23,\n\trt_op_0x18 = 24,\n\trt_op_0x19 = 25,\n\trt_op_0x1a = 26,\n\trt_op_0x1b = 27,\n\tbposge32_op = 28,\n\trt_op_0x1d = 29,\n\trt_op_0x1e = 30,\n\tsynci_op = 31,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtc_control {\n\tDMA_CONTROL_RTC_64 = 0,\n\tDMA_CONTROL_RTC_32 = 8,\n\tDMA_CONTROL_RTC_96 = 16,\n\tDMA_CONTROL_RTC_128 = 24,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rx_frame_status {\n\tgood_frame = 0,\n\tdiscard_frame = 1,\n\tcsum_none = 2,\n\tllc_snap = 4,\n\tdma_own = 8,\n\trx_not_ls = 16,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 2500,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 7500,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_HAS_CGROUP_WEIGHT = 65536ULL,\n\tSCX_OPS_ALL_FLAGS = 65663ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1,\n\t__SCX_REENQ_FILTER_MASK = 65535,\n\t__SCX_REENQ_USER_MASK = 1,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum sd_uhs2_operation {\n\tUHS2_PHY_INIT = 0,\n\tUHS2_SET_CONFIG = 1,\n\tUHS2_ENABLE_INT = 2,\n\tUHS2_DISABLE_INT = 3,\n\tUHS2_ENABLE_CLK = 4,\n\tUHS2_DISABLE_CLK = 5,\n\tUHS2_CHECK_DORMANT = 6,\n\tUHS2_SET_IOS = 7,\n};\n\nenum sdhci_cookie {\n\tCOOKIE_UNMAPPED___2 = 0,\n\tCOOKIE_PRE_MAPPED___2 = 1,\n\tCOOKIE_MAPPED___2 = 2,\n};\n\nenum sdhci_reset_reason {\n\tSDHCI_RESET_FOR_INIT = 0,\n\tSDHCI_RESET_FOR_REQUEST_ERROR = 1,\n\tSDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY = 2,\n\tSDHCI_RESET_FOR_TUNING_ABORT = 3,\n\tSDHCI_RESET_FOR_CARD_REMOVED = 4,\n\tSDHCI_RESET_FOR_CQE_RECOVERY = 5,\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum shmem_param {\n\tOpt_gid___5 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___4 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes = 5,\n\tOpt_size = 6,\n\tOpt_uid___4 = 7,\n\tOpt_inode32 = 8,\n\tOpt_inode64 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota___2 = 11,\n\tOpt_usrquota___2 = 12,\n\tOpt_grpquota___2 = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN___2 = 0,\n\tPARTIAL = 1,\n\tUP___2 = 2,\n\tFULL = 3,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum snoop_when {\n\tSUBMIT = 0,\n\tCOMPLETE = 1,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_DGRAM = 1,\n\tSOCK_STREAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum spec2_op {\n\tmadd_op = 0,\n\tmaddu_op = 1,\n\tmul_op = 2,\n\tspec2_3_unused_op = 3,\n\tmsub_op = 4,\n\tmsubu_op = 5,\n\tclz_op = 32,\n\tclo_op = 33,\n\tdclz_op = 36,\n\tdclo_op = 37,\n\tsdbpp_op = 63,\n};\n\nenum spec3_op {\n\text_op = 0,\n\tdextm_op = 1,\n\tdextu_op = 2,\n\tdext_op = 3,\n\tins_op = 4,\n\tdinsm_op = 5,\n\tdinsu_op = 6,\n\tdins_op = 7,\n\tyield_op = 9,\n\tlx_op = 10,\n\tlwle_op = 25,\n\tlwre_op = 26,\n\tcachee_op = 27,\n\tsbe_op = 28,\n\tshe_op = 29,\n\tsce_op = 30,\n\tswe_op = 31,\n\tbshfl_op = 32,\n\tswle_op = 33,\n\tswre_op = 34,\n\tprefe_op = 35,\n\tdbshfl_op = 36,\n\tcache6_op = 37,\n\tsc6_op = 38,\n\tscd6_op = 39,\n\tlbue_op = 40,\n\tlhue_op = 41,\n\tlbe_op = 44,\n\tlhe_op = 45,\n\tlle_op = 46,\n\tlwe_op = 47,\n\tpref6_op = 53,\n\tll6_op = 54,\n\tlld6_op = 55,\n\trdhwr_op = 59,\n};\n\nenum spec_op {\n\tsll_op = 0,\n\tmovc_op = 1,\n\tsrl_op = 2,\n\tsra_op = 3,\n\tsllv_op = 4,\n\tpmon_op = 5,\n\tsrlv_op = 6,\n\tsrav_op = 7,\n\tjr_op = 8,\n\tjalr_op = 9,\n\tmovz_op = 10,\n\tmovn_op = 11,\n\tsyscall_op = 12,\n\tbreak_op = 13,\n\tspim_op = 14,\n\tsync_op = 15,\n\tmfhi_op = 16,\n\tmthi_op = 17,\n\tmflo_op = 18,\n\tmtlo_op = 19,\n\tdsllv_op = 20,\n\tspec2_unused_op = 21,\n\tdsrlv_op = 22,\n\tdsrav_op = 23,\n\tmult_op = 24,\n\tmultu_op = 25,\n\tdiv_op = 26,\n\tdivu_op = 27,\n\tdmult_op = 28,\n\tdmultu_op = 29,\n\tddiv_op = 30,\n\tddivu_op = 31,\n\tadd_op = 32,\n\taddu_op = 33,\n\tsub_op = 34,\n\tsubu_op = 35,\n\tand_op = 36,\n\tor_op = 37,\n\txor_op = 38,\n\tnor_op = 39,\n\tspec3_unused_op = 40,\n\tspec4_unused_op = 41,\n\tslt_op = 42,\n\tsltu_op = 43,\n\tdadd_op = 44,\n\tdaddu_op = 45,\n\tdsub_op = 46,\n\tdsubu_op = 47,\n\ttge_op = 48,\n\ttgeu_op = 49,\n\ttlt_op = 50,\n\ttltu_op = 51,\n\tteq_op = 52,\n\tseleqz_op = 53,\n\ttne_op = 54,\n\tselnez_op = 55,\n\tdsll_op = 56,\n\tspec5_unused_op = 57,\n\tdsrl_op = 58,\n\tdsra_op = 59,\n\tdsll32_op = 60,\n\tspec6_unused_op = 61,\n\tdsrl32_op = 62,\n\tdsra32_op = 63,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum spi_mem_data_dir {\n\tSPI_MEM_NO_DATA = 0,\n\tSPI_MEM_DATA_IN = 1,\n\tSPI_MEM_DATA_OUT = 2,\n};\n\nenum spi_nor_cmd_ext {\n\tSPI_NOR_EXT_NONE = 0,\n\tSPI_NOR_EXT_REPEAT = 1,\n\tSPI_NOR_EXT_INVERT = 2,\n\tSPI_NOR_EXT_HEX = 3,\n};\n\nenum spi_nor_option_flags {\n\tSNOR_F_HAS_SR_TB = 1,\n\tSNOR_F_NO_OP_CHIP_ERASE = 2,\n\tSNOR_F_BROKEN_RESET = 4,\n\tSNOR_F_4B_OPCODES = 8,\n\tSNOR_F_HAS_4BAIT = 16,\n\tSNOR_F_HAS_LOCK = 32,\n\tSNOR_F_HAS_16BIT_SR = 64,\n\tSNOR_F_NO_READ_CR = 128,\n\tSNOR_F_HAS_SR_TB_BIT6 = 256,\n\tSNOR_F_HAS_4BIT_BP = 512,\n\tSNOR_F_HAS_SR_BP3_BIT6 = 1024,\n\tSNOR_F_IO_MODE_EN_VOLATILE = 2048,\n\tSNOR_F_SOFT_RESET = 4096,\n\tSNOR_F_SWP_IS_VOLATILE = 8192,\n\tSNOR_F_RWW = 16384,\n\tSNOR_F_ECC = 32768,\n\tSNOR_F_NO_WP = 65536,\n\tSNOR_F_SWAP16 = 131072,\n};\n\nenum spi_nor_pp_command_index {\n\tSNOR_CMD_PP = 0,\n\tSNOR_CMD_PP_1_1_4 = 1,\n\tSNOR_CMD_PP_1_4_4 = 2,\n\tSNOR_CMD_PP_4_4_4 = 3,\n\tSNOR_CMD_PP_1_1_8 = 4,\n\tSNOR_CMD_PP_1_8_8 = 5,\n\tSNOR_CMD_PP_8_8_8 = 6,\n\tSNOR_CMD_PP_8_8_8_DTR = 7,\n\tSNOR_CMD_PP_MAX = 8,\n};\n\nenum spi_nor_protocol {\n\tSNOR_PROTO_1_1_1 = 65793,\n\tSNOR_PROTO_1_1_2 = 65794,\n\tSNOR_PROTO_1_1_4 = 65796,\n\tSNOR_PROTO_1_1_8 = 65800,\n\tSNOR_PROTO_1_2_2 = 66050,\n\tSNOR_PROTO_1_4_4 = 66564,\n\tSNOR_PROTO_1_8_8 = 67592,\n\tSNOR_PROTO_2_2_2 = 131586,\n\tSNOR_PROTO_4_4_4 = 263172,\n\tSNOR_PROTO_8_8_8 = 526344,\n\tSNOR_PROTO_1_1_1_DTR = 16843009,\n\tSNOR_PROTO_1_2_2_DTR = 16843266,\n\tSNOR_PROTO_1_4_4_DTR = 16843780,\n\tSNOR_PROTO_1_8_8_DTR = 16844808,\n\tSNOR_PROTO_8_8_8_DTR = 17303560,\n};\n\nenum spi_nor_read_command_index {\n\tSNOR_CMD_READ = 0,\n\tSNOR_CMD_READ_FAST = 1,\n\tSNOR_CMD_READ_1_1_1_DTR = 2,\n\tSNOR_CMD_READ_1_1_2 = 3,\n\tSNOR_CMD_READ_1_2_2 = 4,\n\tSNOR_CMD_READ_2_2_2 = 5,\n\tSNOR_CMD_READ_1_2_2_DTR = 6,\n\tSNOR_CMD_READ_1_1_4 = 7,\n\tSNOR_CMD_READ_1_4_4 = 8,\n\tSNOR_CMD_READ_4_4_4 = 9,\n\tSNOR_CMD_READ_1_4_4_DTR = 10,\n\tSNOR_CMD_READ_1_1_8 = 11,\n\tSNOR_CMD_READ_1_8_8 = 12,\n\tSNOR_CMD_READ_8_8_8 = 13,\n\tSNOR_CMD_READ_1_8_8_DTR = 14,\n\tSNOR_CMD_READ_8_8_8_DTR = 15,\n\tSNOR_CMD_READ_MAX = 16,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum state_protect_how4 {\n\tSP4_NONE = 0,\n\tSP4_MACH_CRED = 1,\n\tSP4_SSV = 2,\n};\n\nenum stmmac_dl_param_id {\n\tSTMMAC_DEVLINK_PARAM_ID_BASE = 21,\n\tSTMMAC_DEVLINK_PARAM_ID_TS_COARSE = 22,\n};\n\nenum stmmac_lpi_mode {\n\tSTMMAC_LPI_DISABLE = 0,\n\tSTMMAC_LPI_FORCED = 1,\n\tSTMMAC_LPI_TIMER = 2,\n};\n\nenum stmmac_rfs_type {\n\tSTMMAC_RFS_T_VLAN = 0,\n\tSTMMAC_RFS_T_LLDP = 1,\n\tSTMMAC_RFS_T_1588 = 2,\n\tSTMMAC_RFS_T_MAX = 3,\n};\n\nenum stmmac_state {\n\tSTMMAC_DOWN = 0,\n\tSTMMAC_RESET_REQUESTED = 1,\n\tSTMMAC_RESETING = 2,\n\tSTMMAC_SERVICE_SCHED = 3,\n};\n\nenum stmmac_txbuf_type {\n\tSTMMAC_TXBUF_T_SKB = 0,\n\tSTMMAC_TXBUF_T_XDP_TX = 1,\n\tSTMMAC_TXBUF_T_XDP_NDO = 2,\n\tSTMMAC_TXBUF_T_XSK_TX = 3,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum stripetype4 {\n\tSTRIPE_SPARSE = 1,\n\tSTRIPE_DENSE = 2,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum suspend_stat_step {\n\tSUSPEND_WORKING = 0,\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nenum svc_auth_status {\n\tSVC_GARBAGE = 1,\n\tSVC_VALID = 2,\n\tSVC_NEGATIVE = 3,\n\tSVC_OK = 4,\n\tSVC_DROP = 5,\n\tSVC_CLOSE = 6,\n\tSVC_DENIED = 7,\n\tSVC_PENDING = 8,\n\tSVC_COMPLETE = 9,\n};\n\nenum sw_activity {\n\tOFF = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum switchdev_attr_id {\n\tSWITCHDEV_ATTR_ID_UNDEFINED = 0,\n\tSWITCHDEV_ATTR_ID_PORT_STP_STATE = 1,\n\tSWITCHDEV_ATTR_ID_PORT_MST_STATE = 2,\n\tSWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS = 3,\n\tSWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS = 4,\n\tSWITCHDEV_ATTR_ID_PORT_MROUTER = 5,\n\tSWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME = 6,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING = 7,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_PROTOCOL = 8,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED = 9,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MROUTER = 10,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MST = 11,\n\tSWITCHDEV_ATTR_ID_MRP_PORT_ROLE = 12,\n\tSWITCHDEV_ATTR_ID_VLAN_MSTI = 13,\n};\n\nenum switchdev_notifier_type {\n\tSWITCHDEV_FDB_ADD_TO_BRIDGE = 1,\n\tSWITCHDEV_FDB_DEL_TO_BRIDGE = 2,\n\tSWITCHDEV_FDB_ADD_TO_DEVICE = 3,\n\tSWITCHDEV_FDB_DEL_TO_DEVICE = 4,\n\tSWITCHDEV_FDB_OFFLOADED = 5,\n\tSWITCHDEV_FDB_FLUSH_TO_BRIDGE = 6,\n\tSWITCHDEV_PORT_OBJ_ADD = 7,\n\tSWITCHDEV_PORT_OBJ_DEL = 8,\n\tSWITCHDEV_PORT_ATTR_SET = 9,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_BRIDGE = 10,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_BRIDGE = 11,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_DEVICE = 12,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_DEVICE = 13,\n\tSWITCHDEV_VXLAN_FDB_OFFLOADED = 14,\n\tSWITCHDEV_BRPORT_OFFLOADED = 15,\n\tSWITCHDEV_BRPORT_UNOFFLOADED = 16,\n\tSWITCHDEV_BRPORT_REPLAY = 17,\n};\n\nenum switchdev_obj_id {\n\tSWITCHDEV_OBJ_ID_UNDEFINED = 0,\n\tSWITCHDEV_OBJ_ID_PORT_VLAN = 1,\n\tSWITCHDEV_OBJ_ID_PORT_MDB = 2,\n\tSWITCHDEV_OBJ_ID_HOST_MDB = 3,\n\tSWITCHDEV_OBJ_ID_MRP = 4,\n\tSWITCHDEV_OBJ_ID_RING_TEST_MRP = 5,\n\tSWITCHDEV_OBJ_ID_RING_ROLE_MRP = 6,\n\tSWITCHDEV_OBJ_ID_RING_STATE_MRP = 7,\n\tSWITCHDEV_OBJ_ID_IN_TEST_MRP = 8,\n\tSWITCHDEV_OBJ_ID_IN_ROLE_MRP = 9,\n\tSWITCHDEV_OBJ_ID_IN_STATE_MRP = 10,\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_clsu32_command {\n\tTC_CLSU32_NEW_KNODE = 0,\n\tTC_CLSU32_REPLACE_KNODE = 1,\n\tTC_CLSU32_DELETE_KNODE = 2,\n\tTC_CLSU32_NEW_HNODE = 3,\n\tTC_CLSU32_REPLACE_HNODE = 4,\n\tTC_CLSU32_DELETE_HNODE = 5,\n};\n\nenum tc_matchall_command {\n\tTC_CLSMATCHALL_REPLACE = 0,\n\tTC_CLSMATCHALL_DESTROY = 1,\n\tTC_CLSMATCHALL_STATS = 2,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tc_taprio_qopt_cmd {\n\tTAPRIO_CMD_REPLACE = 0,\n\tTAPRIO_CMD_DESTROY = 1,\n\tTAPRIO_CMD_STATS = 2,\n\tTAPRIO_CMD_QUEUE_STATS = 3,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPERS_MAX = 1,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum tlb_write_entry {\n\ttlb_random = 0,\n\ttlb_indexed = 1,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tph_mem_type {\n\tTPH_MEM_TYPE_VM = 0,\n\tTPH_MEM_TYPE_PM = 1,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum ttc_control {\n\tDMA_CONTROL_TTC_64 = 0,\n\tDMA_CONTROL_TTC_128 = 16384,\n\tDMA_CONTROL_TTC_192 = 32768,\n\tDMA_CONTROL_TTC_256 = 49152,\n\tDMA_CONTROL_TTC_40 = 65536,\n\tDMA_CONTROL_TTC_32 = 81920,\n\tDMA_CONTROL_TTC_24 = 98304,\n\tDMA_CONTROL_TTC_16 = 114688,\n};\n\nenum ttc_control___2 {\n\tDMA_CONTROL_TTC_DEFAULT = 0,\n\tDMA_CONTROL_TTC_64___2 = 16384,\n\tDMA_CONTROL_TTC_128___2 = 32768,\n\tDMA_CONTROL_TTC_256___2 = 49152,\n\tDMA_CONTROL_TTC_18 = 4194304,\n\tDMA_CONTROL_TTC_24___2 = 4210688,\n\tDMA_CONTROL_TTC_32___2 = 4227072,\n\tDMA_CONTROL_TTC_40___2 = 4243456,\n\tDMA_CONTROL_SE = 8,\n\tDMA_CONTROL_OSF = 4,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tunnel_encap_types {\n\tTUNNEL_ENCAP_NONE = 0,\n\tTUNNEL_ENCAP_FOU = 1,\n\tTUNNEL_ENCAP_GUE = 2,\n\tTUNNEL_ENCAP_MPLS = 3,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum tx_frame_status {\n\ttx_done = 0,\n\ttx_not_ls = 1,\n\ttx_err = 2,\n\ttx_dma_own = 4,\n\ttx_err_bump_tc = 8,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum uart_iotype {\n\tUPIO_UNKNOWN = -1,\n\tUPIO_PORT = 0,\n\tUPIO_HUB6 = 1,\n\tUPIO_MEM = 2,\n\tUPIO_MEM32 = 3,\n\tUPIO_AU = 4,\n\tUPIO_TSI = 5,\n\tUPIO_MEM32BE = 6,\n\tUPIO_MEM16 = 7,\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_FANOTIFY_GROUPS = 10,\n\tUCOUNT_FANOTIFY_MARKS = 11,\n\tUCOUNT_COUNTS = 12,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum usb3_link_state {\n\tUSB3_LPM_U0 = 0,\n\tUSB3_LPM_U1 = 1,\n\tUSB3_LPM_U2 = 2,\n\tUSB3_LPM_U3 = 3,\n};\n\nenum usb_charger_state {\n\tUSB_CHARGER_DEFAULT = 0,\n\tUSB_CHARGER_PRESENT = 1,\n\tUSB_CHARGER_ABSENT = 2,\n};\n\nenum usb_charger_type {\n\tUNKNOWN_TYPE = 0,\n\tSDP_TYPE = 1,\n\tDCP_TYPE = 2,\n\tCDP_TYPE = 3,\n\tACA_TYPE = 4,\n};\n\nenum usb_dev_authorize_policy {\n\tUSB_DEVICE_AUTHORIZE_NONE = 0,\n\tUSB_DEVICE_AUTHORIZE_ALL = 1,\n\tUSB_DEVICE_AUTHORIZE_INTERNAL = 2,\n};\n\nenum usb_device_speed {\n\tUSB_SPEED_UNKNOWN = 0,\n\tUSB_SPEED_LOW = 1,\n\tUSB_SPEED_FULL = 2,\n\tUSB_SPEED_HIGH = 3,\n\tUSB_SPEED_WIRELESS = 4,\n\tUSB_SPEED_SUPER = 5,\n\tUSB_SPEED_SUPER_PLUS = 6,\n};\n\nenum usb_device_state {\n\tUSB_STATE_NOTATTACHED = 0,\n\tUSB_STATE_ATTACHED = 1,\n\tUSB_STATE_POWERED = 2,\n\tUSB_STATE_RECONNECTING = 3,\n\tUSB_STATE_UNAUTHENTICATED = 4,\n\tUSB_STATE_DEFAULT = 5,\n\tUSB_STATE_ADDRESS = 6,\n\tUSB_STATE_CONFIGURED = 7,\n\tUSB_STATE_SUSPENDED = 8,\n};\n\nenum usb_dr_mode {\n\tUSB_DR_MODE_UNKNOWN = 0,\n\tUSB_DR_MODE_HOST = 1,\n\tUSB_DR_MODE_PERIPHERAL = 2,\n\tUSB_DR_MODE_OTG = 3,\n};\n\nenum usb_interface_condition {\n\tUSB_INTERFACE_UNBOUND = 0,\n\tUSB_INTERFACE_BINDING = 1,\n\tUSB_INTERFACE_BOUND = 2,\n\tUSB_INTERFACE_UNBINDING = 3,\n};\n\nenum usb_led_event {\n\tUSB_LED_EVENT_HOST = 0,\n\tUSB_LED_EVENT_GADGET = 1,\n};\n\nenum usb_link_tunnel_mode {\n\tUSB_LINK_UNKNOWN = 0,\n\tUSB_LINK_NATIVE = 1,\n\tUSB_LINK_TUNNELED = 2,\n};\n\nenum usb_otg_state {\n\tOTG_STATE_UNDEFINED = 0,\n\tOTG_STATE_B_IDLE = 1,\n\tOTG_STATE_B_SRP_INIT = 2,\n\tOTG_STATE_B_PERIPHERAL = 3,\n\tOTG_STATE_B_WAIT_ACON = 4,\n\tOTG_STATE_B_HOST = 5,\n\tOTG_STATE_A_IDLE = 6,\n\tOTG_STATE_A_WAIT_VRISE = 7,\n\tOTG_STATE_A_WAIT_BCON = 8,\n\tOTG_STATE_A_HOST = 9,\n\tOTG_STATE_A_SUSPEND = 10,\n\tOTG_STATE_A_PERIPHERAL = 11,\n\tOTG_STATE_A_WAIT_VFALL = 12,\n\tOTG_STATE_A_VBUS_ERR = 13,\n};\n\nenum usb_phy_events {\n\tUSB_EVENT_NONE = 0,\n\tUSB_EVENT_VBUS = 1,\n\tUSB_EVENT_ID = 2,\n\tUSB_EVENT_CHARGER = 3,\n\tUSB_EVENT_ENUMERATED = 4,\n};\n\nenum usb_phy_interface {\n\tUSBPHY_INTERFACE_MODE_UNKNOWN = 0,\n\tUSBPHY_INTERFACE_MODE_UTMI = 1,\n\tUSBPHY_INTERFACE_MODE_UTMIW = 2,\n\tUSBPHY_INTERFACE_MODE_ULPI = 3,\n\tUSBPHY_INTERFACE_MODE_SERIAL = 4,\n\tUSBPHY_INTERFACE_MODE_HSIC = 5,\n};\n\nenum usb_phy_type {\n\tUSB_PHY_TYPE_UNDEFINED = 0,\n\tUSB_PHY_TYPE_USB2 = 1,\n\tUSB_PHY_TYPE_USB3 = 2,\n};\n\nenum usb_port_connect_type {\n\tUSB_PORT_CONNECT_TYPE_UNKNOWN = 0,\n\tUSB_PORT_CONNECT_TYPE_HOT_PLUG = 1,\n\tUSB_PORT_CONNECT_TYPE_HARD_WIRED = 2,\n\tUSB_PORT_NOT_USED = 3,\n};\n\nenum usb_role {\n\tUSB_ROLE_NONE = 0,\n\tUSB_ROLE_HOST = 1,\n\tUSB_ROLE_DEVICE = 2,\n};\n\nenum usb_ssp_rate {\n\tUSB_SSP_GEN_UNKNOWN = 0,\n\tUSB_SSP_GEN_2x1 = 1,\n\tUSB_SSP_GEN_1x2 = 2,\n\tUSB_SSP_GEN_2x2 = 3,\n};\n\nenum usb_wireless_status {\n\tUSB_WIRELESS_STATUS_NA = 0,\n\tUSB_WIRELESS_STATUS_DISCONNECTED = 1,\n\tUSB_WIRELESS_STATUS_CONNECTED = 2,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vcap_cmd {\n\tVCAP_CMD_WRITE = 0,\n\tVCAP_CMD_READ = 1,\n\tVCAP_CMD_MOVE_UP = 2,\n\tVCAP_CMD_MOVE_DOWN = 3,\n\tVCAP_CMD_INITIALIZE = 4,\n};\n\nenum vcap_es0_action_field {\n\tVCAP_ES0_ACT_PUSH_OUTER_TAG = 0,\n\tVCAP_ES0_ACT_PUSH_INNER_TAG = 1,\n\tVCAP_ES0_ACT_TAG_A_TPID_SEL = 2,\n\tVCAP_ES0_ACT_TAG_A_VID_SEL = 3,\n\tVCAP_ES0_ACT_TAG_A_PCP_SEL = 4,\n\tVCAP_ES0_ACT_TAG_A_DEI_SEL = 5,\n\tVCAP_ES0_ACT_TAG_B_TPID_SEL = 6,\n\tVCAP_ES0_ACT_TAG_B_VID_SEL = 7,\n\tVCAP_ES0_ACT_TAG_B_PCP_SEL = 8,\n\tVCAP_ES0_ACT_TAG_B_DEI_SEL = 9,\n\tVCAP_ES0_ACT_VID_A_VAL = 10,\n\tVCAP_ES0_ACT_PCP_A_VAL = 11,\n\tVCAP_ES0_ACT_DEI_A_VAL = 12,\n\tVCAP_ES0_ACT_VID_B_VAL = 13,\n\tVCAP_ES0_ACT_PCP_B_VAL = 14,\n\tVCAP_ES0_ACT_DEI_B_VAL = 15,\n\tVCAP_ES0_ACT_RSV = 16,\n\tVCAP_ES0_ACT_HIT_STICKY = 17,\n};\n\nenum vcap_es0_key_field {\n\tVCAP_ES0_EGR_PORT = 0,\n\tVCAP_ES0_IGR_PORT = 1,\n\tVCAP_ES0_RSV = 2,\n\tVCAP_ES0_L2_MC = 3,\n\tVCAP_ES0_L2_BC = 4,\n\tVCAP_ES0_VID = 5,\n\tVCAP_ES0_DP = 6,\n\tVCAP_ES0_PCP = 7,\n};\n\nenum vcap_is1_action_field {\n\tVCAP_IS1_ACT_DSCP_ENA = 0,\n\tVCAP_IS1_ACT_DSCP_VAL = 1,\n\tVCAP_IS1_ACT_QOS_ENA = 2,\n\tVCAP_IS1_ACT_QOS_VAL = 3,\n\tVCAP_IS1_ACT_DP_ENA = 4,\n\tVCAP_IS1_ACT_DP_VAL = 5,\n\tVCAP_IS1_ACT_PAG_OVERRIDE_MASK = 6,\n\tVCAP_IS1_ACT_PAG_VAL = 7,\n\tVCAP_IS1_ACT_RSV = 8,\n\tVCAP_IS1_ACT_VID_REPLACE_ENA = 9,\n\tVCAP_IS1_ACT_VID_ADD_VAL = 10,\n\tVCAP_IS1_ACT_FID_SEL = 11,\n\tVCAP_IS1_ACT_FID_VAL = 12,\n\tVCAP_IS1_ACT_PCP_DEI_ENA = 13,\n\tVCAP_IS1_ACT_PCP_VAL = 14,\n\tVCAP_IS1_ACT_DEI_VAL = 15,\n\tVCAP_IS1_ACT_VLAN_POP_CNT_ENA = 16,\n\tVCAP_IS1_ACT_VLAN_POP_CNT = 17,\n\tVCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA = 18,\n\tVCAP_IS1_ACT_HIT_STICKY = 19,\n};\n\nenum vcap_is1_half_key_field {\n\tVCAP_IS1_HK_TYPE = 0,\n\tVCAP_IS1_HK_LOOKUP = 1,\n\tVCAP_IS1_HK_IGR_PORT_MASK = 2,\n\tVCAP_IS1_HK_RSV = 3,\n\tVCAP_IS1_HK_OAM_Y1731 = 4,\n\tVCAP_IS1_HK_L2_MC = 5,\n\tVCAP_IS1_HK_L2_BC = 6,\n\tVCAP_IS1_HK_IP_MC = 7,\n\tVCAP_IS1_HK_VLAN_TAGGED = 8,\n\tVCAP_IS1_HK_VLAN_DBL_TAGGED = 9,\n\tVCAP_IS1_HK_TPID = 10,\n\tVCAP_IS1_HK_VID = 11,\n\tVCAP_IS1_HK_DEI = 12,\n\tVCAP_IS1_HK_PCP = 13,\n\tVCAP_IS1_HK_L2_SMAC = 14,\n\tVCAP_IS1_HK_ETYPE_LEN = 15,\n\tVCAP_IS1_HK_ETYPE = 16,\n\tVCAP_IS1_HK_IP_SNAP = 17,\n\tVCAP_IS1_HK_IP4 = 18,\n\tVCAP_IS1_HK_L3_FRAGMENT = 19,\n\tVCAP_IS1_HK_L3_FRAG_OFS_GT0 = 20,\n\tVCAP_IS1_HK_L3_OPTIONS = 21,\n\tVCAP_IS1_HK_L3_DSCP = 22,\n\tVCAP_IS1_HK_L3_IP4_SIP = 23,\n\tVCAP_IS1_HK_TCP_UDP = 24,\n\tVCAP_IS1_HK_TCP = 25,\n\tVCAP_IS1_HK_L4_SPORT = 26,\n\tVCAP_IS1_HK_L4_RNG = 27,\n\tVCAP_IS1_HK_IP4_INNER_TPID = 28,\n\tVCAP_IS1_HK_IP4_INNER_VID = 29,\n\tVCAP_IS1_HK_IP4_INNER_DEI = 30,\n\tVCAP_IS1_HK_IP4_INNER_PCP = 31,\n\tVCAP_IS1_HK_IP4_IP4 = 32,\n\tVCAP_IS1_HK_IP4_L3_FRAGMENT = 33,\n\tVCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0 = 34,\n\tVCAP_IS1_HK_IP4_L3_OPTIONS = 35,\n\tVCAP_IS1_HK_IP4_L3_DSCP = 36,\n\tVCAP_IS1_HK_IP4_L3_IP4_DIP = 37,\n\tVCAP_IS1_HK_IP4_L3_IP4_SIP = 38,\n\tVCAP_IS1_HK_IP4_L3_PROTO = 39,\n\tVCAP_IS1_HK_IP4_TCP_UDP = 40,\n\tVCAP_IS1_HK_IP4_TCP = 41,\n\tVCAP_IS1_HK_IP4_L4_RNG = 42,\n\tVCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE = 43,\n};\n\nenum vcap_is2_action_field {\n\tVCAP_IS2_ACT_HIT_ME_ONCE = 0,\n\tVCAP_IS2_ACT_CPU_COPY_ENA = 1,\n\tVCAP_IS2_ACT_CPU_QU_NUM = 2,\n\tVCAP_IS2_ACT_MASK_MODE = 3,\n\tVCAP_IS2_ACT_MIRROR_ENA = 4,\n\tVCAP_IS2_ACT_LRN_DIS = 5,\n\tVCAP_IS2_ACT_POLICE_ENA = 6,\n\tVCAP_IS2_ACT_POLICE_IDX = 7,\n\tVCAP_IS2_ACT_POLICE_VCAP_ONLY = 8,\n\tVCAP_IS2_ACT_PORT_MASK = 9,\n\tVCAP_IS2_ACT_REW_OP = 10,\n\tVCAP_IS2_ACT_SMAC_REPLACE_ENA = 11,\n\tVCAP_IS2_ACT_RSV = 12,\n\tVCAP_IS2_ACT_ACL_ID = 13,\n\tVCAP_IS2_ACT_HIT_CNT = 14,\n};\n\nenum vcap_is2_half_key_field {\n\tVCAP_IS2_TYPE = 0,\n\tVCAP_IS2_HK_FIRST = 1,\n\tVCAP_IS2_HK_PAG = 2,\n\tVCAP_IS2_HK_RSV1 = 3,\n\tVCAP_IS2_HK_IGR_PORT_MASK = 4,\n\tVCAP_IS2_HK_RSV2 = 5,\n\tVCAP_IS2_HK_HOST_MATCH = 6,\n\tVCAP_IS2_HK_L2_MC = 7,\n\tVCAP_IS2_HK_L2_BC = 8,\n\tVCAP_IS2_HK_VLAN_TAGGED = 9,\n\tVCAP_IS2_HK_VID = 10,\n\tVCAP_IS2_HK_DEI = 11,\n\tVCAP_IS2_HK_PCP = 12,\n\tVCAP_IS2_HK_L2_DMAC = 13,\n\tVCAP_IS2_HK_L2_SMAC = 14,\n\tVCAP_IS2_HK_MAC_ETYPE_ETYPE = 15,\n\tVCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0 = 16,\n\tVCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1 = 17,\n\tVCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2 = 18,\n\tVCAP_IS2_HK_MAC_LLC_DMAC = 19,\n\tVCAP_IS2_HK_MAC_LLC_SMAC = 20,\n\tVCAP_IS2_HK_MAC_LLC_L2_LLC = 21,\n\tVCAP_IS2_HK_MAC_SNAP_SMAC = 22,\n\tVCAP_IS2_HK_MAC_SNAP_DMAC = 23,\n\tVCAP_IS2_HK_MAC_SNAP_L2_SNAP = 24,\n\tVCAP_IS2_HK_MAC_ARP_SMAC = 25,\n\tVCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK = 26,\n\tVCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK = 27,\n\tVCAP_IS2_HK_MAC_ARP_LEN_OK = 28,\n\tVCAP_IS2_HK_MAC_ARP_TARGET_MATCH = 29,\n\tVCAP_IS2_HK_MAC_ARP_SENDER_MATCH = 30,\n\tVCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN = 31,\n\tVCAP_IS2_HK_MAC_ARP_OPCODE = 32,\n\tVCAP_IS2_HK_MAC_ARP_L3_IP4_DIP = 33,\n\tVCAP_IS2_HK_MAC_ARP_L3_IP4_SIP = 34,\n\tVCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP = 35,\n\tVCAP_IS2_HK_IP4 = 36,\n\tVCAP_IS2_HK_L3_FRAGMENT = 37,\n\tVCAP_IS2_HK_L3_FRAG_OFS_GT0 = 38,\n\tVCAP_IS2_HK_L3_OPTIONS = 39,\n\tVCAP_IS2_HK_IP4_L3_TTL_GT0 = 40,\n\tVCAP_IS2_HK_L3_TOS = 41,\n\tVCAP_IS2_HK_L3_IP4_DIP = 42,\n\tVCAP_IS2_HK_L3_IP4_SIP = 43,\n\tVCAP_IS2_HK_DIP_EQ_SIP = 44,\n\tVCAP_IS2_HK_TCP = 45,\n\tVCAP_IS2_HK_L4_SPORT = 46,\n\tVCAP_IS2_HK_L4_DPORT = 47,\n\tVCAP_IS2_HK_L4_RNG = 48,\n\tVCAP_IS2_HK_L4_SPORT_EQ_DPORT = 49,\n\tVCAP_IS2_HK_L4_SEQUENCE_EQ0 = 50,\n\tVCAP_IS2_HK_L4_URG = 51,\n\tVCAP_IS2_HK_L4_ACK = 52,\n\tVCAP_IS2_HK_L4_PSH = 53,\n\tVCAP_IS2_HK_L4_RST = 54,\n\tVCAP_IS2_HK_L4_SYN = 55,\n\tVCAP_IS2_HK_L4_FIN = 56,\n\tVCAP_IS2_HK_L4_1588_DOM = 57,\n\tVCAP_IS2_HK_L4_1588_VER = 58,\n\tVCAP_IS2_HK_IP4_L3_PROTO = 59,\n\tVCAP_IS2_HK_L3_PAYLOAD = 60,\n\tVCAP_IS2_HK_IP6_L3_TTL_GT0 = 61,\n\tVCAP_IS2_HK_IP6_L3_PROTO = 62,\n\tVCAP_IS2_HK_L3_IP6_SIP = 63,\n\tVCAP_IS2_HK_OAM_MEL_FLAGS = 64,\n\tVCAP_IS2_HK_OAM_VER = 65,\n\tVCAP_IS2_HK_OAM_OPCODE = 66,\n\tVCAP_IS2_HK_OAM_FLAGS = 67,\n\tVCAP_IS2_HK_OAM_MEPID = 68,\n\tVCAP_IS2_HK_OAM_CCM_CNTS_EQ0 = 69,\n\tVCAP_IS2_HK_OAM_IS_Y1731 = 70,\n};\n\nenum vcap_sel {\n\tVCAP_SEL_ENTRY = 1,\n\tVCAP_SEL_ACTION = 2,\n\tVCAP_SEL_COUNTER = 4,\n\tVCAP_SEL_ALL = 7,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_R4K = 1,\n\tVDSO_CLOCKMODE_GIC = 2,\n\tVDSO_CLOCKMODE_MAX = 3,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum virtio_balloon_config_read {\n\tVIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0,\n};\n\nenum virtio_balloon_vq {\n\tVIRTIO_BALLOON_VQ_INFLATE = 0,\n\tVIRTIO_BALLOON_VQ_DEFLATE = 1,\n\tVIRTIO_BALLOON_VQ_STATS = 2,\n\tVIRTIO_BALLOON_VQ_FREE_PAGE = 3,\n\tVIRTIO_BALLOON_VQ_REPORTING = 4,\n\tVIRTIO_BALLOON_VQ_MAX = 5,\n};\n\nenum virtnet_xmit_type {\n\tVIRTNET_XMIT_TYPE_SKB = 0,\n\tVIRTNET_XMIT_TYPE_SKB_ORPHAN = 1,\n\tVIRTNET_XMIT_TYPE_XDP = 2,\n\tVIRTNET_XMIT_TYPE_XSK = 3,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_NORMAL = 4,\n\tPGALLOC_HIGH = 5,\n\tPGALLOC_MOVABLE = 6,\n\tALLOCSTALL_NORMAL = 7,\n\tALLOCSTALL_HIGH = 8,\n\tALLOCSTALL_MOVABLE = 9,\n\tPGSCAN_SKIP_NORMAL = 10,\n\tPGSCAN_SKIP_HIGH = 11,\n\tPGSCAN_SKIP_MOVABLE = 12,\n\tPGFREE = 13,\n\tPGACTIVATE = 14,\n\tPGDEACTIVATE = 15,\n\tPGLAZYFREE = 16,\n\tPGFAULT = 17,\n\tPGMAJFAULT = 18,\n\tPGLAZYFREED = 19,\n\tPGREFILL = 20,\n\tPGREUSE = 21,\n\tPGSTEAL_KSWAPD = 22,\n\tPGSTEAL_DIRECT = 23,\n\tPGSTEAL_KHUGEPAGED = 24,\n\tPGSTEAL_PROACTIVE = 25,\n\tPGSCAN_KSWAPD = 26,\n\tPGSCAN_DIRECT = 27,\n\tPGSCAN_KHUGEPAGED = 28,\n\tPGSCAN_PROACTIVE = 29,\n\tPGSCAN_DIRECT_THROTTLE = 30,\n\tPGSCAN_ANON = 31,\n\tPGSCAN_FILE = 32,\n\tPGSTEAL_ANON = 33,\n\tPGSTEAL_FILE = 34,\n\tPGINODESTEAL = 35,\n\tSLABS_SCANNED = 36,\n\tKSWAPD_INODESTEAL = 37,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 38,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 39,\n\tPAGEOUTRUN = 40,\n\tPGROTATED = 41,\n\tDROP_PAGECACHE = 42,\n\tDROP_SLAB = 43,\n\tOOM_KILL = 44,\n\tPGMIGRATE_SUCCESS = 45,\n\tPGMIGRATE_FAIL = 46,\n\tTHP_MIGRATION_SUCCESS = 47,\n\tTHP_MIGRATION_FAIL = 48,\n\tTHP_MIGRATION_SPLIT = 49,\n\tCOMPACTMIGRATE_SCANNED = 50,\n\tCOMPACTFREE_SCANNED = 51,\n\tCOMPACTISOLATED = 52,\n\tCOMPACTSTALL = 53,\n\tCOMPACTFAIL = 54,\n\tCOMPACTSUCCESS = 55,\n\tKCOMPACTD_WAKE = 56,\n\tKCOMPACTD_MIGRATE_SCANNED = 57,\n\tKCOMPACTD_FREE_SCANNED = 58,\n\tUNEVICTABLE_PGCULLED = 59,\n\tUNEVICTABLE_PGSCANNED = 60,\n\tUNEVICTABLE_PGRESCUED = 61,\n\tUNEVICTABLE_PGMLOCKED = 62,\n\tUNEVICTABLE_PGMUNLOCKED = 63,\n\tUNEVICTABLE_PGCLEARED = 64,\n\tUNEVICTABLE_PGSTRANDED = 65,\n\tBALLOON_INFLATE = 66,\n\tBALLOON_DEFLATE = 67,\n\tBALLOON_MIGRATE = 68,\n\tSWAP_RA = 69,\n\tSWAP_RA_HIT = 70,\n\tSWPIN_ZERO = 71,\n\tSWPOUT_ZERO = 72,\n\tNR_VM_EVENT_ITEMS = 73,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vmalloc64_mode {\n\tnot_refill = 0,\n\trefill_scratch = 1,\n\trefill_noscratch = 2,\n};\n\nenum vmpressure_levels {\n\tVMPRESSURE_LOW = 0,\n\tVMPRESSURE_MEDIUM = 1,\n\tVMPRESSURE_CRITICAL = 2,\n\tVMPRESSURE_NUM_LEVELS = 3,\n};\n\nenum vmpressure_modes {\n\tVMPRESSURE_NO_PASSTHROUGH = 0,\n\tVMPRESSURE_HIERARCHY = 1,\n\tVMPRESSURE_LOCAL = 2,\n\tVMPRESSURE_NUM_MODES = 3,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum vp_vq_vector_policy {\n\tVP_VQ_VECTOR_POLICY_EACH = 0,\n\tVP_VQ_VECTOR_POLICY_SHARED_SLOW = 1,\n\tVP_VQ_VECTOR_POLICY_SHARED = 2,\n};\n\nenum vq_layout {\n\tVQ_LAYOUT_SPLIT = 0,\n\tVQ_LAYOUT_PACKED = 1,\n\tVQ_LAYOUT_SPLIT_IN_ORDER = 2,\n\tVQ_LAYOUT_PACKED_IN_ORDER = 3,\n};\n\nenum vsc85xx_global_phy {\n\tVSC88XX_BASE_ADDR = 0,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum wd_read_status {\n\tWD_READ_SUCCESS = 0,\n\tWD_READ_UNSTABLE = 1,\n\tWD_READ_SKIP = 2,\n};\n\nenum why_no_delegation4 {\n\tWND4_NOT_WANTED = 0,\n\tWND4_CONTENTION = 1,\n\tWND4_RESOURCE = 2,\n\tWND4_NOT_SUPP_FTYPE = 3,\n\tWND4_WRITE_DELEG_NOT_SUPP_FTYPE = 4,\n\tWND4_NOT_SUPP_UPGRADE = 5,\n\tWND4_NOT_SUPP_DOWNGRADE = 6,\n\tWND4_CANCELLED = 7,\n\tWND4_IS_DIR = 8,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 11,\n\tWORK_OFFQ_POOL_BITS = 11,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 75000,\n\tMAYDAY_INITIAL_TIMEOUT = 2,\n\tMAYDAY_INTERVAL = 25,\n\tCREATE_COOLDOWN = 250,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 16,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xhci_cancelled_td_status {\n\tTD_DIRTY = 0,\n\tTD_HALTED = 1,\n\tTD_CLEARING_CACHE = 2,\n\tTD_CLEARING_CACHE_DEFERRED = 3,\n\tTD_CLEARED = 4,\n};\n\nenum xhci_ep_reset_type {\n\tEP_HARD_RESET = 0,\n\tEP_SOFT_RESET = 1,\n};\n\nenum xhci_overhead_type {\n\tLS_OVERHEAD_TYPE = 0,\n\tFS_OVERHEAD_TYPE = 1,\n\tHS_OVERHEAD_TYPE = 2,\n};\n\nenum xhci_ring_type {\n\tTYPE_CTRL = 0,\n\tTYPE_ISOC = 1,\n\tTYPE_BULK = 2,\n\tTYPE_INTR = 3,\n\tTYPE_STREAM = 4,\n\tTYPE_COMMAND = 5,\n\tTYPE_EVENT = 6,\n};\n\nenum xhci_setup_dev {\n\tSETUP_CONTEXT_ONLY = 0,\n\tSETUP_CONTEXT_ADDRESS = 1,\n};\n\nenum xhci_sideband_notify_type {\n\tXHCI_SIDEBAND_XFER_RING_FREE = 0,\n};\n\nenum xhci_sideband_type {\n\tXHCI_SIDEBAND_AUDIO = 0,\n\tXHCI_SIDEBAND_VENDOR = 1,\n};\n\nenum xiic_endian {\n\tLITTLE = 0,\n\tBIG = 1,\n};\n\nenum xilinx_i2c_state {\n\tSTATE_DONE = 0,\n\tSTATE_ERROR = 1,\n\tSTATE_START = 2,\n};\n\nenum xprt_transports {\n\tXPRT_TRANSPORT_UDP = 17,\n\tXPRT_TRANSPORT_TCP = 6,\n\tXPRT_TRANSPORT_BC_TCP = -2147483642,\n\tXPRT_TRANSPORT_RDMA = 256,\n\tXPRT_TRANSPORT_BC_RDMA = -2147483392,\n\tXPRT_TRANSPORT_LOCAL = 257,\n\tXPRT_TRANSPORT_TCP_TLS = 258,\n};\n\nenum xprt_xid_rb_cmp {\n\tXID_RB_EQUAL = 0,\n\tXID_RB_LEFT = 1,\n\tXID_RB_RIGHT = 2,\n};\n\nenum xprtsec_policies {\n\tRPC_XPRTSEC_NONE = 0,\n\tRPC_XPRTSEC_TLS_ANON = 1,\n\tRPC_XPRTSEC_TLS_X509 = 2,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_FREE_CMA_PAGES = 9,\n\tNR_VM_ZONE_STAT_ITEMS = 10,\n};\n\nenum zone_type {\n\tZONE_NORMAL = 0,\n\tZONE_HIGHMEM = 1,\n\tZONE_MOVABLE = 2,\n\t__MAX_NR_ZONES = 3,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\ntypedef _Bool bool;\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef int __s32;\n\ntypedef __s32 Elf32_Sword;\n\ntypedef __s32 s32;\n\ntypedef s32 __compat_uid_t;\n\ntypedef __compat_uid_t __compat_uid32_t;\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_ipc_pid_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_ptrdiff_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_ssize_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef s32 dma_cookie_t;\n\ntypedef int ext4_grpblk_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef int suspend_state_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef int vma_flag_t;\n\ntypedef int word_type;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef long int __kernel_daddr_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 s64;\n\ntypedef s64 int64_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef long long int qsize_t;\n\ntypedef __s64 time64_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef __u64 __virtio64;\n\ntypedef u64 acpi_io_address;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 clientid4;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef __be64 fdt64_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef long long unsigned int llu;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 sci_t;\n\ntypedef u64 sector_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef u64 upf_t;\n\ntypedef uint64_t vli_type;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef __kernel_ulong_t __kernel_ino_t;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int dspreg_t;\n\ntypedef long unsigned int elf_greg_t;\n\ntypedef elf_greg_t elf_gregset_t[45];\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int old_sigset_t;\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int u_long;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short int mm_id_mapcount_t;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef __u16 __hc16;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef __kernel_gid16_t gid16_t;\n\ntypedef short unsigned int mm_id_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef short unsigned int pipe_index_t;\n\ntypedef __u16 port_id;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef u16 u_int16_t;\n\ntypedef short unsigned int u_short;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef u16 wchar_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef u8 dscp_t;\n\ntypedef unsigned char *sk_buff_data_t;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef __u8 virtio_net_ctrl_ack;\n\ntypedef unsigned int __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef unsigned int __u32;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef __u32 u32;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef unsigned int OM_uint32;\n\ntypedef __u32 __be32;\n\ntypedef __u32 __hc32;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_gid_t;\n\ntypedef unsigned int __kernel_mode_t;\n\ntypedef unsigned int __kernel_old_dev_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __virtio32;\n\ntypedef __u32 __wsum;\n\ntypedef u32 acpi_object_type;\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef unsigned int cycles_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef u32 dma_addr_t;\n\ntypedef u32 errseq_t;\n\ntypedef unsigned int ext4_group_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef __be32 fdt32_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef u32 jump_label_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef unsigned int mips_instruction;\n\ntypedef unsigned int mmc_pm_flag_t;\n\ntypedef __kernel_mode_t mode_t;\n\ntypedef u32 nlink_t;\n\ntypedef u32 pci_bus_addr_t;\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef u32 phys_addr_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u32 rpc_authflavor_t;\n\ntypedef __be32 rpc_fraghdr;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int speed_t;\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int tid_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef u32 u_int32_t;\n\ntypedef unsigned int uffd_flags_t;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef unsigned int upstat_t;\n\ntypedef u32 usb_port_location_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\nstruct DWstruct {\n\tint low;\n\tint high;\n};\n\ntypedef union {\n\tstruct DWstruct s;\n\tlong long int ll;\n} DWunion;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n\tlong: 32;\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\nstruct buffer_head;\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n\tlong: 32;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tlong unsigned int fds_bits[32];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef union {\n} aes_encrypt_arg;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\ntypedef atomic_t atomic_long_t;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\nstruct uart_port;\n\ntypedef struct {\n\tstruct uart_port *lock;\n\tlong unsigned int flags;\n} class_uart_port_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_write_lock_irqsave_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n} ext4_acl_entry;\n\ntypedef struct {\n\t__le32 a_version;\n} ext4_acl_header;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tunsigned int __softirq_pending;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n} irq_cpustat_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\t__le64 b;\n\t__le64 a;\n} le128;\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef union {\n\tlong unsigned int x[1];\n} map_word;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\nstruct qspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tstruct {\n\t\t\tu8 locked;\n\t\t\tu8 pending;\n\t\t};\n\t\tstruct {\n\t\t\tu16 locked_pending;\n\t\t\tu16 tail;\n\t\t};\n\t};\n};\n\ntypedef struct qspinlock arch_spinlock_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tunion {\n\t\tu64 asid[16];\n\t\tatomic64_t mmid;\n\t};\n\tvoid *vdso;\n\tspinlock_t bd_emupage_lock;\n\tlong unsigned int *bd_emupage_allocmap;\n\twait_queue_head_t bd_emupage_queue;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[2];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tchar data[8];\n} nfs4_verifier;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\ntypedef struct {\n\tlong unsigned int pgd;\n} pgd_t;\n\ntypedef struct {\n\tpgd_t pgd;\n} p4d_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\ntypedef struct {\n\tlong unsigned int pgprot;\n} pgprot_t;\n\ntypedef struct {\n\tp4d_t p4d;\n} pud_t;\n\ntypedef struct {\n\tpud_t pud;\n} pmd_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tlong unsigned int pte;\n} pte_t;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[4];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\tu64 v;\n} u64_stats_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {\n\tseqcount_t seq;\n};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lock_class_key {};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong int privdata[0];\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct lockdep_map {};\n\nstruct srcu_ctr;\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tlong: 32;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n\tlong: 32;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool work_in_progress;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tbool smart_suspend: 1;\n\tbool must_resume: 1;\n\tbool may_skip_resume: 1;\n\tbool out_band_wakeup: 1;\n\tbool strict_midlayer: 1;\n\tstruct hrtimer suspend_timer;\n\tu64 timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tbool idle_notification: 1;\n\tbool request_pending: 1;\n\tbool deferred_resume: 1;\n\tbool needs_force_resume: 1;\n\tbool runtime_auto: 1;\n\tbool ignore_children: 1;\n\tbool no_callbacks: 1;\n\tbool irq_safe: 1;\n\tbool use_autosuspend: 1;\n\tbool timer_autosuspends: 1;\n\tbool memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tenum rpm_status last_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tlong: 32;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct dev_archdata {};\n\nstruct dev_iommu;\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct dev_pin_info;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct dma_coherent_mem;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct dev_pin_info *pins;\n\tstruct dev_msi_info msi;\n\tu64 *dma_mask;\n\tlong: 32;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct dma_coherent_mem *dma_mem;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_coherent: 1;\n\tbool dma_skip_sync: 1;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tlong: 32;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n\tlong: 32;\n};\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct __bridge_info {\n\t__u64 designated_root;\n\t__u64 bridge_id;\n\t__u32 root_path_cost;\n\t__u32 max_age;\n\t__u32 hello_time;\n\t__u32 forward_delay;\n\t__u32 bridge_max_age;\n\t__u32 bridge_hello_time;\n\t__u32 bridge_forward_delay;\n\t__u8 topology_change;\n\t__u8 topology_change_detected;\n\t__u8 root_port;\n\t__u8 stp_enabled;\n\t__u32 ageing_time;\n\t__u32 gc_interval;\n\t__u32 hello_timer_value;\n\t__u32 tcn_timer_value;\n\t__u32 topology_change_timer_value;\n\t__u32 gc_timer_value;\n};\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct __fat_dirent {\n\tlong int d_ino;\n\t__kernel_off_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[256];\n};\n\nstruct __fdb_entry {\n\t__u8 mac_addr[6];\n\t__u8 port_no;\n\t__u8 is_local;\n\t__u32 ageing_timer_value;\n\t__u8 port_hi;\n\t__u8 pad0;\n\t__u16 unused;\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct sha512_block_state {\n\tu64 h[8];\n};\n\nstruct __sha512_ctx {\n\tstruct sha512_block_state state;\n\tu64 bytecount_lo;\n\tu64 bytecount_hi;\n\tu8 buf[128];\n};\n\nstruct __hmac_sha512_ctx {\n\tstruct __sha512_ctx sha_ctx;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __hmac_sha512_key {\n\tstruct sha512_block_state istate;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong: 32;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong: 32;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong: 32;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct __large_struct {\n\tlong unsigned int buf[100];\n};\n\nstruct __port_info {\n\t__u64 designated_root;\n\t__u64 designated_bridge;\n\t__u16 port_id;\n\t__u16 designated_port;\n\t__u32 path_cost;\n\t__u32 designated_cost;\n\t__u8 state;\n\t__u8 top_change_ack;\n\t__u8 config_pending;\n\t__u8 unused0;\n\t__u32 message_age_timer_value;\n\t__u32 forward_delay_timer_value;\n\t__u32 hold_timer_value;\n\tlong: 32;\n};\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct dentry;\n\nstruct __track_dentry_update_args {\n\tstruct dentry *dentry;\n\tint op;\n};\n\nstruct __track_range_args {\n\text4_lblk_t start;\n\text4_lblk_t end;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n};\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct _ieee754_csr {\n\tunsigned int rm: 2;\n\tunsigned int sx: 5;\n\tunsigned int mx: 5;\n\tunsigned int cx: 6;\n\tunsigned int nan2008: 1;\n\tunsigned int abs2008: 1;\n\tunsigned int pad0: 3;\n\tunsigned int c: 1;\n\tunsigned int nod: 1;\n\tunsigned int fcc: 7;\n};\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct a4tech_sc {\n\tlong unsigned int quirks;\n\tunsigned int hw_wheel;\n\t__s32 delayed_value;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct net_device;\n\nstruct ac6_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct comp_alg_common {\n\tstruct crypto_alg base;\n};\n\nstruct acomp_req;\n\nstruct crypto_acomp;\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\ntypedef void (*crypto_completion_t)(void *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n};\n\nstruct acomp_req_chain {\n\tcrypto_completion_t compl;\n\tvoid *data;\n\tstruct scatterlist ssg;\n\tstruct scatterlist dsg;\n\tunion {\n\t\tconst u8 *src;\n\t\tstruct folio *sfolio;\n\t};\n\tunion {\n\t\tu8 *dst;\n\t\tstruct folio *dfolio;\n\t};\n\tu32 flags;\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tunion {\n\t\tstruct scatterlist *dst;\n\t\tu8 *dvirt;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct acomp_req_chain chain;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nunion crypto_no_such_thing;\n\nstruct scatter_walk {\n\tunion {\n\t\tvoid * const addr;\n\t\tunion crypto_no_such_thing *__addr;\n\t};\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct acomp_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tint flags;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\ntypedef void *acpi_handle;\n\nunion acpi_object {\n\tacpi_object_type type;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tlong: 32;\n\t\tu64 value;\n\t} integer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tchar *pointer;\n\t} string;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tu8 *pointer;\n\t} buffer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 count;\n\t\tunion acpi_object *elements;\n\t} package;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tacpi_object_type actual_type;\n\t\tacpi_handle handle;\n\t} reference;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 proc_id;\n\t\tacpi_io_address pblk_address;\n\t\tu32 pblk_length;\n\t\tlong: 32;\n\t} processor;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 system_level;\n\t\tu32 resource_order;\n\t} power_resource;\n};\n\nstruct action_cache {};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct regulator;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tlong: 32;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n\tstruct regulator *bus_regulator;\n\tstruct dentry *debugfs;\n\tlong unsigned int addrs_in_instantiation[4];\n\tlong: 32;\n};\n\nstruct adapter_info;\n\nstruct i2c_algo_pch_data {\n\tstruct i2c_adapter pch_adapter;\n\tstruct adapter_info *p_adapter_info;\n\tvoid *pch_base_address;\n\tint pch_buff_mode_en;\n\tu32 pch_event_flag;\n\tbool pch_i2c_xfer_in_progress;\n\tlong: 32;\n};\n\nstruct adapter_info {\n\tstruct i2c_algo_pch_data pch_data[2];\n\tbool pch_i2c_suspended;\n\tint ch_num;\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct inode;\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct file;\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct audit_ntp_data {};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n\tlong: 32;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n\tlong: 32;\n};\n\nstruct crypto_aead;\n\nstruct aead_request;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nunion aes_enckey_arch {\n\tu32 rndkeys[60];\n};\n\nstruct aes_enckey {\n\tu32 len;\n\tu32 nrounds;\n\tu32 padding[2];\n\tunion aes_enckey_arch k;\n};\n\nunion aes_invkey_arch {\n\tu32 inv_rndkeys[60];\n};\n\nstruct aes_key {\n\tstruct aes_enckey;\n\tunion aes_invkey_arch inv_k;\n};\n\nstruct cpumask;\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\nstruct aggregate_control {\n\tlong int *aggregate;\n\tlong int *local;\n\tlong int *pending;\n\tlong int *ppending;\n\tlong int *cstat;\n\tlong int *cstat_prev;\n\tint size;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request;\n\nstruct crypto_ahash;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*export_core)(struct ahash_request *, void *);\n\tint (*import_core)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_ahash *);\n\tvoid (*exit_tfm)(struct crypto_ahash *);\n\tint (*clone_tfm)(struct crypto_ahash *, struct crypto_ahash *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct hash_alg_common halg;\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[256];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tu8 *result;\n\tstruct scatterlist sg_head[2];\n\tcrypto_completion_t saved_complete;\n\tvoid *saved_data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\nstruct ata_link;\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct clk_bulk_data;\n\nstruct reset_control;\n\nstruct phy;\n\nstruct ata_port;\n\nstruct ata_host;\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 mask_port_map;\n\tu32 mask_port_ext;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 saved_port_cap[32];\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tunsigned int n_clks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int f_rsts;\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[15];\n\tchar *irq_desc;\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tlong: 32;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n\tlong: 32;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct eventfd_ctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct akcipher_request;\n\nstruct crypto_akcipher;\n\nstruct akcipher_alg {\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct alias_prop {\n\tstruct list_head link;\n\tconst char *alias;\n\tstruct device_node *np;\n\tint id;\n\tchar stem[0];\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n\tlong: 32;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n\tlong: 32;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct psmouse;\n\nstruct input_dev;\n\nstruct alps_nibble_commands;\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct amba_cs_uci_id {\n\tunsigned int devarch;\n\tunsigned int devarch_mask;\n\tunsigned int devtype;\n\tvoid *data;\n};\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct clk;\n\nstruct amba_device {\n\tstruct device dev;\n\tstruct resource res;\n\tstruct clk *pclk;\n\tstruct device_dma_parameters dma_parms;\n\tunsigned int periphid;\n\tstruct mutex periphid_lock;\n\tunsigned int cid;\n\tstruct amba_cs_uci_id uci;\n\tunsigned int irq[9];\n\tconst char *driver_override;\n};\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct dev_pm_ops;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct device_attribute;\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct vm_area_struct;\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct api_context {\n\tstruct completion done;\n\tint status;\n};\n\nstruct apple_backlight_config_report {\n\tu8 report_id;\n\tu8 version;\n\tu16 backlight_off;\n\tu16 backlight_on_min;\n\tu16 backlight_on_max;\n};\n\nstruct apple_backlight_set_report {\n\tu8 report_id;\n\tu8 version;\n\tu16 backlight;\n\tu16 rate;\n};\n\nstruct apple_key_translation {\n\tu16 from;\n\tu16 to;\n\tlong unsigned int flags;\n};\n\nstruct led_pattern;\n\nstruct led_classdev {\n\tconst char *name;\n\tunsigned int brightness;\n\tunsigned int max_brightness;\n\tunsigned int color;\n\tint flags;\n\tlong unsigned int work_flags;\n\tvoid (*brightness_set)(struct led_classdev *, enum led_brightness);\n\tint (*brightness_set_blocking)(struct led_classdev *, enum led_brightness);\n\tenum led_brightness (*brightness_get)(struct led_classdev *);\n\tint (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *);\n\tint (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int);\n\tint (*pattern_clear)(struct led_classdev *);\n\tstruct device *dev;\n\tconst struct attribute_group **groups;\n\tstruct list_head node;\n\tconst char *default_trigger;\n\tlong unsigned int blink_delay_on;\n\tlong unsigned int blink_delay_off;\n\tstruct timer_list blink_timer;\n\tint blink_brightness;\n\tint new_blink_brightness;\n\tvoid (*flash_resume)(struct led_classdev *);\n\tstruct workqueue_struct *wq;\n\tstruct work_struct set_brightness_work;\n\tint delayed_set_value;\n\tlong unsigned int delayed_delay_on;\n\tlong unsigned int delayed_delay_off;\n\tstruct mutex led_access;\n};\n\nstruct hid_report;\n\nstruct apple_magic_backlight {\n\tstruct led_classdev cdev;\n\tstruct hid_report *brightness;\n\tstruct hid_report *power;\n};\n\nstruct apple_non_apple_keyboard {\n\tchar *name;\n};\n\nstruct hid_device;\n\nstruct apple_sc_backlight;\n\nstruct apple_sc {\n\tstruct hid_device *hdev;\n\tlong unsigned int quirks;\n\tunsigned int fn_on;\n\tunsigned int fn_found;\n\tlong unsigned int pressed_numlock[24];\n\tstruct timer_list battery_timer;\n\tstruct apple_sc_backlight *backlight;\n};\n\nstruct apple_sc_backlight {\n\tstruct led_classdev cdev;\n\tstruct hid_device *hdev;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct arasan_host {\n\tu32 chg_clk;\n};\n\nstruct arch_elf_state {\n\tint nan_2008;\n\tint fp_abi;\n\tint interp_fp_abi;\n\tint overall_fp_mode;\n};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct arch_msi_msg_addr_hi {\n\tu32 address_hi;\n};\n\ntypedef struct arch_msi_msg_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct arch_msi_msg_addr_lo {\n\tu32 address_lo;\n};\n\ntypedef struct arch_msi_msg_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct arch_msi_msg_data {\n\tu32 data;\n};\n\ntypedef struct arch_msi_msg_data arch_msi_msg_data_t;\n\nstruct arch_vdso_time_data {};\n\nstruct arg_dev_net_ip {\n\tstruct net *net;\n\tstruct in6_addr *addr;\n};\n\nstruct arg_netdev_event {\n\tconst struct net_device *dev;\n\tunion {\n\t\tunsigned char nh_flags;\n\t\tlong unsigned int event;\n\t};\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct usb_dev_state;\n\nstruct pid;\n\nstruct urb;\n\nstruct usb_memory;\n\nstruct async {\n\tstruct list_head asynclist;\n\tstruct usb_dev_state *ps;\n\tstruct pid *pid;\n\tconst struct cred *cred;\n\tunsigned int signr;\n\tunsigned int ifnum;\n\tvoid *userbuffer;\n\tvoid *userurb;\n\tsigval_t userurb_sigval;\n\tstruct urb *urb;\n\tstruct usb_memory *usbm;\n\tunsigned int mem_usage;\n\tint status;\n\tu8 bulk_addr;\n\tu8 bulk_status;\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n\tlong: 32;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nstruct ata_cdl {\n\tu8 desc_log_buf[512];\n\tu8 ncq_sense_log_buf[1024];\n};\n\nstruct ata_cpr {\n\tu8 num;\n\tu8 num_storage_elements;\n\tlong: 32;\n\tu64 start_lba;\n\tu64 num_lbas;\n};\n\nstruct ata_cpr_log {\n\tu8 nr_cpr;\n\tlong: 32;\n\tstruct ata_cpr cpr[0];\n};\n\nstruct ata_dev_quirk_value {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 val;\n};\n\nstruct ata_dev_quirks_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 quirks;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tlong: 32;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tu64 quirks;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tlong: 32;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 gp_log_dir[512];\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tstruct ata_cpr_log *cpr_log;\n\tstruct ata_cdl *cdl;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tu8 sector_buf[512];\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst unsigned int *timeouts;\n};\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[16];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tlong: 32;\n\tu64 value;\n\tu8 cbl;\n\tu8 spd_limit;\n\tunsigned int xfer_mask;\n\tu64 quirk_on;\n\tu64 quirk_off;\n\tunsigned int pflags_on;\n\tu16 lflags_on;\n\tu16 lflags_off;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tunion {\n\t\tu8 error;\n\t\tu8 feature;\n\t};\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tunion {\n\t\tu8 status;\n\t\tu8 command;\n\t};\n\tu32 auxiliary;\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct scsi_cmnd;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tu64 qc_active;\n\tint nr_active_links;\n\tstruct work_struct deferred_qc_work;\n\tstruct ata_queued_cmd *deferred_qc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tlong: 32;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct delayed_work scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tunsigned int fastdrain_cnt;\n\tlong: 32;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nstruct ata_reset_operations {\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tvoid (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tvoid (*qc_ncq_fill_rtf)(struct ata_port *, u64);\n\tint (*cable_detect)(struct ata_port *);\n\tunsigned int (*mode_filter)(struct ata_device *, unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, __le16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tstruct ata_reset_operations reset;\n\tstruct ata_reset_operations pmp_reset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ps2dev;\n\ntypedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int);\n\ntypedef void (*ps2_receive_handler_t)(struct ps2dev *, u8);\n\nstruct serio;\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n\tps2_pre_receive_handler_t pre_receive_handler;\n\tps2_receive_handler_t receive_handler;\n};\n\nstruct vivaldi_data {\n\tu32 function_row_physmap[24];\n\tunsigned int num_function_row_keys;\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[16];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tstruct vivaldi_data vdata;\n};\n\nstruct notifier_block;\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct bin_attribute;\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct auth_cred {\n\tconst struct cred *cred;\n\tconst char *principal;\n};\n\nstruct auth_ops;\n\nstruct auth_domain {\n\tstruct kref ref;\n\tstruct hlist_node hash;\n\tchar *name;\n\tstruct auth_ops *flavour;\n\tstruct callback_head callback_head;\n};\n\nstruct svc_rqst;\n\nstruct auth_ops {\n\tchar *name;\n\tstruct module *owner;\n\tint flavour;\n\tenum svc_auth_status (*accept)(struct svc_rqst *);\n\tint (*release)(struct svc_rqst *);\n\tvoid (*domain_release)(struct auth_domain *);\n\tenum svc_auth_status (*set_client)(struct svc_rqst *);\n\trpc_authflavor_t (*pseudoflavor)(struct svc_rqst *);\n};\n\nstruct auto_mode_param {\n\tint qp_type;\n};\n\nstruct task_group;\n\nstruct autogroup {\n\tstruct kref kref;\n\tstruct task_group *tg;\n\tstruct rw_semaphore lock;\n\tlong unsigned int id;\n\tint nice;\n};\n\nstruct b_format {\n\tunsigned int func: 6;\n\tunsigned int code: 20;\n\tunsigned int opcode: 6;\n};\n\nstruct backing_aio {\n\tstruct kiocb iocb;\n\trefcount_t ref;\n\tstruct kiocb *orig_iocb;\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n\tstruct work_struct work;\n\tlong int res;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\tlong: 32;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n\tlong: 32;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct backing_dev_info;\n\nstruct cgroup_subsys_state;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tlong: 32;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tlong: 32;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n\tstruct percpu_ref refcnt;\n\tlong: 32;\n\tstruct fprop_local_percpu memcg_completions;\n\tstruct cgroup_subsys_state *memcg_css;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct list_head memcg_node;\n\tstruct list_head blkcg_node;\n\tstruct list_head b_attached;\n\tstruct list_head offline_node;\n\tstruct work_struct switch_work;\n\tstruct llist_head switch_wbs_ctxs;\n\tunion {\n\t\tstruct work_struct release_work;\n\t\tstruct callback_head rcu;\n\t};\n\tlong: 32;\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\tstruct xarray cgwb_tree;\n\tstruct mutex cgwb_release_mutex;\n\tstruct rw_semaphore wb_switch_rwsem;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tlong: 32;\n\tloff_t prev_pos;\n};\n\nstruct file_operations;\n\nstruct fown_struct;\n\nstruct hlist_head;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tlong: 32;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n\tlong: 32;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backing_file_ctx {\n\tconst struct cred *cred;\n\tvoid (*accessed)(struct file *);\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n\tlong: 32;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct page;\n\nstruct balloon_dev_info {\n\tlong unsigned int isolated_pages;\n\tstruct list_head pages;\n\tint (*migratepage)(struct balloon_dev_info *, struct page *, struct page *, enum migrate_mode);\n\tbool adjust_managed_page_count;\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct local_lock {};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct bcache_ops {\n\tvoid (*bc_enable)(void);\n\tvoid (*bc_disable)(void);\n\tvoid (*bc_wback_inv)(long unsigned int, long unsigned int);\n\tvoid (*bc_inv)(long unsigned int, long unsigned int);\n\tvoid (*bc_prefetch_enable)(void);\n\tvoid (*bc_prefetch_disable)(void);\n\tbool (*bc_prefetch_is_enabled)(void);\n};\n\nstruct gf_poly;\n\nstruct bch_control {\n\tunsigned int m;\n\tunsigned int n;\n\tunsigned int t;\n\tunsigned int ecc_bits;\n\tunsigned int ecc_bytes;\n\tuint16_t *a_pow_tab;\n\tuint16_t *a_log_tab;\n\tuint32_t *mod8_tab;\n\tuint32_t *ecc_buf;\n\tuint32_t *ecc_buf2;\n\tunsigned int *xi_tab;\n\tunsigned int *syn;\n\tint *cache;\n\tstruct gf_poly *elp;\n\tstruct gf_poly *poly_2t[4];\n\tbool swap_bits;\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tlong: 32;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct super_block;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct fsnotify_mark_connector;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tseqcount_t i_size_seqcount;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct bdi_writeback *i_wb;\n\tint i_wb_frn_winner;\n\tu16 i_wb_frn_avg_time;\n\tu16 i_wb_frn_history;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n\tlong: 32;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct bfq_sched_data;\n\nstruct bfq_queue;\n\nstruct bfq_entity {\n\tstruct rb_node rb_node;\n\tbool on_st_or_in_serv;\n\tu64 start;\n\tu64 finish;\n\tstruct rb_root *tree;\n\tlong: 32;\n\tu64 min_start;\n\tint service;\n\tint budget;\n\tint allocated;\n\tint dev_weight;\n\tint weight;\n\tint new_weight;\n\tint orig_weight;\n\tstruct bfq_entity *parent;\n\tstruct bfq_sched_data *my_sched_data;\n\tstruct bfq_sched_data *sched_data;\n\tint prio_changed;\n\tbool in_groups_with_pending_reqs;\n\tstruct bfq_queue *last_bfqq_created;\n\tlong: 32;\n};\n\nstruct bfq_ttime {\n\tu64 last_end_request;\n\tu64 ttime_total;\n\tlong unsigned int ttime_samples;\n\tlong: 32;\n\tu64 ttime_mean;\n};\n\nstruct bfq_data;\n\nstruct request;\n\nstruct bfq_weight_counter;\n\nstruct bfq_io_cq;\n\nstruct bfq_queue {\n\tint ref;\n\tint stable_ref;\n\tstruct bfq_data *bfqd;\n\tshort unsigned int ioprio;\n\tshort unsigned int ioprio_class;\n\tshort unsigned int new_ioprio;\n\tshort unsigned int new_ioprio_class;\n\tlong: 32;\n\tu64 last_serv_time_ns;\n\tunsigned int inject_limit;\n\tlong unsigned int decrease_time_jif;\n\tstruct bfq_queue *new_bfqq;\n\tstruct rb_node pos_node;\n\tstruct rb_root *pos_root;\n\tstruct rb_root sort_list;\n\tstruct request *next_rq;\n\tint queued[2];\n\tint meta_pending;\n\tstruct list_head fifo;\n\tstruct bfq_entity entity;\n\tstruct bfq_weight_counter *weight_counter;\n\tint max_budget;\n\tlong unsigned int budget_timeout;\n\tint dispatched;\n\tlong unsigned int flags;\n\tstruct list_head bfqq_list;\n\tlong: 32;\n\tstruct bfq_ttime ttime;\n\tu64 io_start_time;\n\tu64 tot_idle_time;\n\tu32 seek_history;\n\tstruct hlist_node burst_list_node;\n\tlong: 32;\n\tsector_t last_request_pos;\n\tunsigned int requests_within_timer;\n\tpid_t pid;\n\tstruct bfq_io_cq *bic;\n\tlong unsigned int wr_cur_max_time;\n\tlong unsigned int soft_rt_next_start;\n\tlong unsigned int last_wr_start_finish;\n\tunsigned int wr_coeff;\n\tlong unsigned int last_idle_bklogged;\n\tlong unsigned int service_from_backlogged;\n\tlong unsigned int service_from_wr;\n\tlong unsigned int wr_start_at_switch_to_srt;\n\tlong unsigned int split_time;\n\tlong unsigned int first_IO_time;\n\tlong unsigned int creation_time;\n\tstruct bfq_queue *waker_bfqq;\n\tstruct bfq_queue *tentative_waker_bfqq;\n\tunsigned int num_waker_detections;\n\tlong: 32;\n\tu64 waker_detection_started;\n\tstruct hlist_node woken_list_node;\n\tstruct hlist_head woken_list;\n\tunsigned int actuator_idx;\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tlong: 32;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct bfq_group;\n\nstruct bfq_data {\n\tstruct request_queue *queue;\n\tstruct list_head dispatch;\n\tstruct bfq_group *root_group;\n\tstruct rb_root_cached queue_weights_tree;\n\tunsigned int num_groups_with_pending_reqs;\n\tunsigned int busy_queues[3];\n\tint wr_busy_queues;\n\tint queued;\n\tint tot_rq_in_driver;\n\tint rq_in_driver[8];\n\tbool nonrot_with_queueing;\n\tint max_rq_in_driver;\n\tint hw_tag_samples;\n\tint hw_tag;\n\tint budgets_assigned;\n\tstruct hrtimer idle_slice_timer;\n\tstruct bfq_queue *in_service_queue;\n\tlong: 32;\n\tsector_t last_position;\n\tsector_t in_serv_last_pos;\n\tu64 last_completion;\n\tstruct bfq_queue *last_completed_rq_bfqq;\n\tstruct bfq_queue *last_bfqq_created;\n\tu64 last_empty_occupied_ns;\n\tbool wait_dispatch;\n\tstruct request *waited_rq;\n\tbool rqs_injected;\n\tlong: 32;\n\tu64 first_dispatch;\n\tu64 last_dispatch;\n\tktime_t last_budget_start;\n\tktime_t last_idling_start;\n\tlong unsigned int last_idling_start_jiffies;\n\tint peak_rate_samples;\n\tu32 sequential_samples;\n\tlong: 32;\n\tu64 tot_sectors_dispatched;\n\tu32 last_rq_max_size;\n\tlong: 32;\n\tu64 delta_from_first;\n\tu32 peak_rate;\n\tint bfq_max_budget;\n\tstruct list_head active_list[8];\n\tstruct list_head idle_list;\n\tu64 bfq_fifo_expire[2];\n\tunsigned int bfq_back_penalty;\n\tunsigned int bfq_back_max;\n\tu32 bfq_slice_idle;\n\tint bfq_user_max_budget;\n\tunsigned int bfq_timeout;\n\tbool strict_guarantees;\n\tlong unsigned int last_ins_in_burst;\n\tlong unsigned int bfq_burst_interval;\n\tint burst_size;\n\tstruct bfq_entity *burst_parent_entity;\n\tlong unsigned int bfq_large_burst_thresh;\n\tbool large_burst;\n\tstruct hlist_head burst_list;\n\tbool low_latency;\n\tunsigned int bfq_wr_coeff;\n\tunsigned int bfq_wr_rt_max_time;\n\tunsigned int bfq_wr_min_idle_time;\n\tlong unsigned int bfq_wr_min_inter_arr_async;\n\tunsigned int bfq_wr_max_softrt_rate;\n\tlong: 32;\n\tu64 rate_dur_prod;\n\tstruct bfq_queue oom_bfqq;\n\tspinlock_t lock;\n\tstruct bfq_io_cq *bio_bic;\n\tstruct bfq_queue *bio_bfqq;\n\tunsigned int async_depths[4];\n\tunsigned int num_actuators;\n\tsector_t sector[8];\n\tsector_t nr_sectors[8];\n\tstruct blk_independent_access_range ia_ranges[8];\n\tunsigned int actuator_load_threshold;\n\tlong: 32;\n};\n\nstruct blkcg_gq;\n\nstruct blkg_policy_data {\n\tstruct blkcg_gq *blkg;\n\tint plid;\n\tbool online;\n};\n\nstruct bfq_service_tree {\n\tstruct rb_root active;\n\tstruct rb_root idle;\n\tstruct bfq_entity *first_idle;\n\tstruct bfq_entity *last_idle;\n\tu64 vtime;\n\tlong unsigned int wsum;\n\tlong: 32;\n};\n\nstruct bfq_sched_data {\n\tstruct bfq_entity *in_service_entity;\n\tstruct bfq_entity *next_in_service;\n\tstruct bfq_service_tree service_tree[3];\n\tlong unsigned int bfq_class_idle_last_service;\n\tlong: 32;\n};\n\nstruct blkg_rwstat {\n\tstruct percpu_counter cpu_cnt[5];\n\tatomic64_t aux_cnt[5];\n};\n\nstruct bfqg_stats {\n\tstruct blkg_rwstat bytes;\n\tstruct blkg_rwstat ios;\n};\n\nstruct bfq_group {\n\tstruct blkg_policy_data pd;\n\trefcount_t ref;\n\tstruct bfq_entity entity;\n\tstruct bfq_sched_data sched_data;\n\tstruct bfq_data *bfqd;\n\tstruct bfq_queue *async_bfqq[128];\n\tstruct bfq_queue *async_idle_bfqq[8];\n\tstruct bfq_entity *my_entity;\n\tint active_entities;\n\tint num_queues_with_pending_reqs;\n\tstruct rb_root rq_pos_tree;\n\tlong: 32;\n\tstruct bfqg_stats stats;\n};\n\nstruct blkcg;\n\nstruct blkcg_policy_data {\n\tstruct blkcg *blkcg;\n\tint plid;\n};\n\nstruct bfq_group_data {\n\tstruct blkcg_policy_data pd;\n\tunsigned int weight;\n};\n\nstruct io_context;\n\nstruct kmem_cache;\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct bfq_iocq_bfqq_data {\n\tbool saved_has_short_ttime;\n\tbool saved_IO_bound;\n\tbool saved_in_large_burst;\n\tbool was_in_burst_list;\n\tunsigned int saved_weight;\n\tu64 saved_io_start_time;\n\tu64 saved_tot_idle_time;\n\tlong unsigned int saved_wr_coeff;\n\tlong unsigned int saved_last_wr_start_finish;\n\tlong unsigned int saved_service_from_wr;\n\tlong unsigned int saved_wr_start_at_switch_to_srt;\n\tstruct bfq_ttime saved_ttime;\n\tunsigned int saved_wr_cur_max_time;\n\tunsigned int saved_inject_limit;\n\tlong unsigned int saved_decrease_time_jif;\n\tlong: 32;\n\tu64 saved_last_serv_time_ns;\n\tstruct bfq_queue *stable_merge_bfqq;\n\tbool stably_merged;\n};\n\nstruct bfq_io_cq {\n\tstruct io_cq icq;\n\tstruct bfq_queue *bfqq[16];\n\tint ioprio;\n\tuint64_t blkcg_serial_nr;\n\tstruct bfq_iocq_bfqq_data bfqq_data[8];\n\tunsigned int requests;\n\tlong: 32;\n};\n\nstruct bfq_weight_counter {\n\tunsigned int weight;\n\tunsigned int num_active;\n\tstruct rb_node weights_node;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n};\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tstruct blkcg_gq *bi_blkg;\n\tu64 issue_time_ns;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n\tlong: 32;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tlong: 32;\n\tu64 bc_dun[4];\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec;\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tlong: 32;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct fsverity_info;\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct fsverity_info *vi;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bl_dev_msg {\n\tint32_t status;\n\tuint32_t major;\n\tuint32_t minor;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tlong: 32;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_file;\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tlong: 32;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct cgroup;\n\nstruct cgroup_subsys;\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tlong: 32;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n\tlong: 32;\n};\n\nstruct blkcg {\n\tstruct cgroup_subsys_state css;\n\tspinlock_t lock;\n\trefcount_t online_pin;\n\tatomic_t congestion_count;\n\tstruct xarray blkg_tree;\n\tstruct blkcg_gq *blkg_hint;\n\tstruct hlist_head blkg_list;\n\tstruct blkcg_policy_data *cpd[6];\n\tstruct list_head all_blkcgs_node;\n\tstruct llist_head *lhead;\n\tstruct list_head cgwb_list;\n\tlong: 32;\n};\n\nstruct blkg_iostat {\n\tu64 bytes[3];\n\tu64 ios[3];\n};\n\nstruct blkg_iostat_set {\n\tstruct u64_stats_sync sync;\n\tstruct blkcg_gq *blkg;\n\tstruct llist_node lnode;\n\tint lqueued;\n\tstruct blkg_iostat cur;\n\tstruct blkg_iostat last;\n};\n\nstruct blkcg_gq {\n\tstruct request_queue *q;\n\tstruct list_head q_node;\n\tstruct hlist_node blkcg_node;\n\tstruct blkcg *blkcg;\n\tstruct blkcg_gq *parent;\n\tstruct percpu_ref refcnt;\n\tbool online;\n\tstruct blkg_iostat_set *iostat_cpu;\n\tlong: 32;\n\tstruct blkg_iostat_set iostat;\n\tstruct blkg_policy_data *pd[6];\n\tunion {\n\t\tstruct work_struct async_bio_work;\n\t\tstruct work_struct free_work;\n\t};\n\tatomic_t use_delay;\n\tlong: 32;\n\tatomic64_t delay_nsec;\n\tatomic64_t delay_start;\n\tu64 last_delay;\n\tint last_use;\n\tstruct callback_head callback_head;\n\tlong: 32;\n};\n\ntypedef struct blkcg_policy_data *blkcg_pol_alloc_cpd_fn(gfp_t);\n\ntypedef void blkcg_pol_free_cpd_fn(struct blkcg_policy_data *);\n\ntypedef struct blkg_policy_data *blkcg_pol_alloc_pd_fn(struct gendisk *, struct blkcg *, gfp_t);\n\ntypedef void blkcg_pol_init_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_online_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_offline_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_free_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_reset_pd_stats_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_stat_pd_fn(struct blkg_policy_data *, struct seq_file *);\n\nstruct cftype;\n\nstruct blkcg_policy {\n\tint plid;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tblkcg_pol_alloc_cpd_fn *cpd_alloc_fn;\n\tblkcg_pol_free_cpd_fn *cpd_free_fn;\n\tblkcg_pol_alloc_pd_fn *pd_alloc_fn;\n\tblkcg_pol_init_pd_fn *pd_init_fn;\n\tblkcg_pol_online_pd_fn *pd_online_fn;\n\tblkcg_pol_offline_pd_fn *pd_offline_fn;\n\tblkcg_pol_free_pd_fn *pd_free_fn;\n\tblkcg_pol_reset_pd_stats_fn *pd_reset_stats_fn;\n\tblkcg_pol_stat_pd_fn *pd_stat_fn;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bio bio;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct blkg_conf_ctx {\n\tchar *input;\n\tchar *body;\n\tstruct block_device *bdev;\n\tstruct blkcg_gq *blkg;\n};\n\nstruct blkg_rwstat_sample {\n\tu64 cnt[5];\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n\tlong: 32;\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[64];\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct software_node;\n\nstruct spi_board_info {\n\tchar modalias[32];\n\tconst void *platform_data;\n\tconst struct software_node *swnode;\n\tvoid *controller_data;\n\tint irq;\n\tu32 max_speed_hz;\n\tu16 bus_num;\n\tu16 chip_select;\n\tu32 mode;\n};\n\nstruct boardinfo {\n\tstruct list_head list;\n\tstruct spi_board_info board_info;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct obj_cgroup;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tstruct obj_cgroup *objcg;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tlong: 32;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tlong: 32;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tlong: 32;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n\tlong: 32;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct bpf_prog;\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n\tlong: 32;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tlong: 32;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n\tlong: 32;\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\tlong: 32;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t\tlong: 32;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\tlong: 32;\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\tlong: 32;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t\tlong: 32;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t\tlong: 32;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t\tlong: 32;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 32;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n\tlong: 32;\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\tlong: 32;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\traw_spinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n\tlong: 32;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n\tlong: 32;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct sock;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tlong: 32;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_rxq_info;\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t\tu64 frame_sz_flags_init;\n\t};\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tlong: 32;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tlong: 32;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n\tlong: 32;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_prog;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_kern;\n\tlong: 32;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n\tlong: 32;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n\tlong: 32;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tlong: 32;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t\tlong: 32;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tlong: 32;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n\tlong: 32;\n};\n\nstruct bpf_cgroup_storage;\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tlong: 32;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n\tlong: 32;\n};\n\nstruct perf_event;\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n\tlong: 32;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tlong: 32;\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n\tlong: 32;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n\tlong: 32;\n};\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tlong: 32;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 32;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tlong: 32;\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n\tlong: 32;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct fib6_info;\n\nstruct bpf_iter__ipv6_route {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct fib6_info *rt;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tlong: 32;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct sock_common;\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n\tlong: 32;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 32;\n\tint bucket;\n\tlong: 32;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n\tlong: 32;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n\tlong: 32;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n\tlong: 32;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n\tlong: 32;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tlong: 32;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 32;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tlong: 32;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct mm_struct;\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n\tlong: 32;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n\tlong: 32;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct key;\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tlong: 32;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t\tlong: 32;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tlong: 32;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\tlong: 32;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\tlong: 32;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t\tlong: 32;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t\tlong: 32;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tlong: 32;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\tlong: 32;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\tlong: 32;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n\tlong: 32;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tlong: 32;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n\tlong: 32;\n};\n\ntypedef struct qspinlock rqspinlock_t;\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tlong: 32;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tlong: 32;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tlong: 32;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n\tlong: 32;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tlong: 32;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tlong: 32;\n\tatomic64_t revision;\n\tu32 count;\n\tlong: 32;\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n\tlong: 32;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\ntypedef unsigned int nf_hookfn(void *, struct sk_buff *, const struct nf_hook_state *);\n\nstruct nf_hook_ops {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tnf_hookfn *hook;\n\tstruct net_device *dev;\n\tvoid *priv;\n\tu8 pf;\n\tenum nf_hook_ops_type hook_ops_type: 8;\n\tunsigned int hooknum;\n\tint priority;\n};\n\nstruct nf_defrag_hook;\n\nstruct bpf_nf_link {\n\tstruct bpf_link link;\n\tstruct nf_hook_ops hook_ops;\n\tnetns_tracker ns_tracker;\n\tstruct net *net;\n\tu32 dead;\n\tconst struct nf_defrag_hook *defrag_hook;\n\tlong: 32;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tlong: 32;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_arena;\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tlong: 32;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n\tlong: 32;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n\tlong: 32;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct tracepoint;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tlong: 32;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tlong: 32;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tlong: 32;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\trqspinlock_t spinlock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_t busy;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int consumer_pos;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n\tlong: 32;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n\tlong: 32;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tlong: 32;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bpf_dummy_ops data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n\tlong: 32;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_ext_ops data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tlong: 32;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tlong: 32;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tlong: 32;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n\tlong: 32;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tlong: 32;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n\tlong: 32;\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[38];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n\tlong: 32;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tlong: 32;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tlong: 32;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tlong: 32;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n\tlong: 32;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct br_boolopt_multi {\n\t__u32 optval;\n\t__u32 optmask;\n};\n\nstruct bridge_id {\n\tunsigned char prio[2];\n\tunsigned char addr[6];\n};\n\ntypedef struct bridge_id bridge_id;\n\nstruct br_config_bpdu {\n\tunsigned int topology_change: 1;\n\tunsigned int topology_change_ack: 1;\n\tbridge_id root;\n\tint root_path_cost;\n\tbridge_id bridge_id;\n\tport_id port_id;\n\tint message_age;\n\tint max_age;\n\tint hello_time;\n\tint forward_delay;\n};\n\nstruct net_bridge_port;\n\nstruct br_frame_type {\n\t__be16 type;\n\tint (*frame_handler)(struct net_bridge_port *, struct sk_buff *);\n\tstruct hlist_node list;\n};\n\nstruct br_input_skb_cb {\n\tstruct net_device *brdev;\n\tu16 frag_max_size;\n\tu8 igmp;\n\tu8 mrouters_only: 1;\n\tu8 proxyarp_replied: 1;\n\tu8 src_port_isolated: 1;\n\tu8 promisc: 1;\n\tu8 tx_fwd_offload: 1;\n\tint src_hwdom;\n\tlong unsigned int fwd_hwdoms;\n\tu32 backup_nhid;\n};\n\nstruct br_ip {\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t} src;\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t\tunsigned char mac_addr[6];\n\t} dst;\n\t__be16 proto;\n\t__u16 vid;\n};\n\nstruct br_ip_list {\n\tstruct list_head list;\n\tstruct br_ip addr;\n};\n\nstruct br_mcast_stats {\n\t__u64 igmp_v1queries[2];\n\t__u64 igmp_v2queries[2];\n\t__u64 igmp_v3queries[2];\n\t__u64 igmp_leaves[2];\n\t__u64 igmp_v1reports[2];\n\t__u64 igmp_v2reports[2];\n\t__u64 igmp_v3reports[2];\n\t__u64 igmp_parse_errors;\n\t__u64 mld_v1queries[2];\n\t__u64 mld_v2queries[2];\n\t__u64 mld_leaves[2];\n\t__u64 mld_v1reports[2];\n\t__u64 mld_v2reports[2];\n\t__u64 mld_parse_errors;\n\t__u64 mcast_bytes[2];\n\t__u64 mcast_packets[2];\n};\n\nstruct net_bridge;\n\nstruct br_mdb_entry;\n\nstruct br_mdb_src_entry;\n\nstruct br_mdb_config {\n\tstruct net_bridge *br;\n\tstruct net_bridge_port *p;\n\tstruct br_mdb_entry *entry;\n\tstruct br_ip group;\n\tbool src_entry;\n\tu8 filter_mode;\n\tu16 nlflags;\n\tstruct br_mdb_src_entry *src_entries;\n\tint num_src_entries;\n\tu8 rt_protocol;\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_mdb_flush_desc {\n\tu32 port_ifindex;\n\tu16 vid;\n\tu8 rt_protocol;\n\tu8 state;\n\tu8 state_mask;\n};\n\nstruct br_mdb_src_entry {\n\tstruct br_ip addr;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct br_switchdev_mdb_complete_info {\n\tstruct net_bridge_port *port;\n\tstruct br_ip ip;\n};\n\nstruct metadata_dst;\n\nstruct br_tunnel_info {\n\t__be64 tunnel_id;\n\tstruct metadata_dst *tunnel_dst;\n\tlong: 32;\n};\n\nstruct brd_device {\n\tint brd_number;\n\tstruct gendisk *brd_disk;\n\tstruct list_head brd_list;\n\tstruct xarray brd_pages;\n\tlong: 32;\n\tu64 brd_nr_pages;\n};\n\nstruct bridge_mcast_other_query {\n\tstruct timer_list timer;\n\tstruct timer_list delay_timer;\n};\n\nstruct bridge_mcast_own_query {\n\tstruct timer_list timer;\n\tu32 startup_sent;\n};\n\nstruct bridge_mcast_querier {\n\tstruct br_ip addr;\n\tint port_ifidx;\n\tseqcount_spinlock_t seq;\n};\n\nstruct bridge_mcast_stats {\n\tstruct br_mcast_stats mstats;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct bridge_stp_xstats {\n\t__u64 transition_blk;\n\t__u64 transition_fwd;\n\t__u64 rx_bpdu;\n\t__u64 tx_bpdu;\n\t__u64 rx_tcn;\n\t__u64 tx_tcn;\n};\n\nstruct bridge_vlan_info {\n\t__u16 flags;\n\t__u16 vid;\n};\n\nstruct bridge_vlan_xstats {\n\t__u64 rx_bytes;\n\t__u64 rx_packets;\n\t__u64 tx_bytes;\n\t__u64 tx_packets;\n\t__u16 vid;\n\t__u16 flags;\n\t__u32 pad2;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct brport_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct net_bridge_port *, char *);\n\tint (*store)(struct net_bridge_port *, long unsigned int);\n\tint (*store_raw)(struct net_bridge_port *, char *);\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tlong: 32;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n\tlong: 32;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[60];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\ntypedef void *va_list;\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, va_list);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct hlist_nulls_node;\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tlong: 32;\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct c0r_format {\n\tunsigned int sel: 3;\n\tunsigned int z: 8;\n\tunsigned int rd: 5;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct c_format {\n\tunsigned int simmediate: 16;\n\tunsigned int cache: 2;\n\tunsigned int c_op: 3;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct cache_head;\n\nstruct cache_deferred_req {\n\tstruct hlist_node hash;\n\tstruct list_head recent;\n\tstruct cache_head *item;\n\tvoid *owner;\n\tvoid (*revisit)(struct cache_deferred_req *, int);\n};\n\nstruct cache_desc {\n\tunsigned int waysize;\n\tshort unsigned int sets;\n\tunsigned char ways;\n\tunsigned char linesz;\n\tunsigned char waybit;\n\tunsigned char flags;\n};\n\nstruct proc_dir_entry;\n\nstruct cache_detail {\n\tstruct module *owner;\n\tint hash_size;\n\tstruct hlist_head *hash_table;\n\tspinlock_t hash_lock;\n\tchar *name;\n\tvoid (*cache_put)(struct kref *);\n\tint (*cache_upcall)(struct cache_detail *, struct cache_head *);\n\tvoid (*cache_request)(struct cache_detail *, struct cache_head *, char **, int *);\n\tint (*cache_parse)(struct cache_detail *, char *, int);\n\tint (*cache_show)(struct seq_file *, struct cache_detail *, struct cache_head *);\n\tvoid (*warn_no_listener)(struct cache_detail *, int);\n\tstruct cache_head * (*alloc)(void);\n\tvoid (*flush)(void);\n\tint (*match)(struct cache_head *, struct cache_head *);\n\tvoid (*init)(struct cache_head *, struct cache_head *);\n\tvoid (*update)(struct cache_head *, struct cache_head *);\n\ttime64_t flush_time;\n\tstruct list_head others;\n\ttime64_t nextcheck;\n\tint entries;\n\tstruct list_head queue;\n\tatomic_t writers;\n\ttime64_t last_close;\n\ttime64_t last_warn;\n\tunion {\n\t\tstruct proc_dir_entry *procfs;\n\t\tstruct dentry *pipefs;\n\t};\n\tstruct net *net;\n};\n\nstruct cache_head {\n\tstruct hlist_node cache_list;\n\ttime64_t expiry_time;\n\ttime64_t last_refresh;\n\tstruct kref ref;\n\tlong unsigned int flags;\n};\n\nstruct cache_queue {\n\tstruct list_head list;\n\tint reader;\n};\n\nstruct cache_reader {\n\tstruct cache_queue q;\n\tint offset;\n};\n\nstruct cache_req {\n\tstruct cache_deferred_req * (*defer)(struct cache_req *);\n\tlong unsigned int thread_wait;\n};\n\nstruct cache_request {\n\tstruct cache_queue q;\n\tstruct cache_head *item;\n\tchar *buf;\n\tint len;\n\tint readers;\n};\n\nstruct cache_type_info {\n\tconst char *size_prop;\n\tconst char *line_size_props[2];\n\tconst char *nr_sets_prop;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct cb_process_state;\n\nstruct xdr_stream;\n\nstruct callback_op {\n\t__be32 (*process_op)(void *, void *, struct cb_process_state *);\n\t__be32 (*decode_args)(struct svc_rqst *, struct xdr_stream *, void *);\n\t__be32 (*encode_res)(struct svc_rqst *, struct xdr_stream *, const void *);\n\tlong int res_maxsize;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct cb_compound_hdr_arg {\n\tunsigned int taglen;\n\tconst char *tag;\n\tunsigned int minorversion;\n\tunsigned int cb_ident;\n\tunsigned int nops;\n};\n\nstruct cb_compound_hdr_res {\n\t__be32 *status;\n\tunsigned int taglen;\n\tconst char *tag;\n\t__be32 *nops;\n};\n\nstruct cb_devicenotifyitem;\n\nstruct cb_devicenotifyargs {\n\tuint32_t ndevs;\n\tstruct cb_devicenotifyitem *devs;\n};\n\nstruct nfs4_deviceid {\n\tchar data[16];\n};\n\nstruct cb_devicenotifyitem {\n\tuint32_t cbd_notify_type;\n\tuint32_t cbd_layout_type;\n\tstruct nfs4_deviceid cbd_dev_id;\n\tuint32_t cbd_immediate;\n};\n\nstruct nfs_fh {\n\tshort unsigned int size;\n\tunsigned char data[128];\n};\n\nstruct cb_getattrargs {\n\tstruct nfs_fh fh;\n\tuint32_t bitmap[3];\n};\n\nstruct cb_getattrres {\n\t__be32 status;\n\tuint32_t bitmap[3];\n\tuint64_t size;\n\tuint64_t change_attr;\n\tstruct timespec64 atime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 mtime;\n};\n\nstruct pnfs_layout_range {\n\tu32 iomode;\n\tlong: 32;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct nfs4_stateid_struct {\n\tunion {\n\t\tchar data[16];\n\t\tstruct {\n\t\t\t__be32 seqid;\n\t\t\tchar other[12];\n\t\t};\n\t};\n\tenum {\n\t\tNFS4_INVALID_STATEID_TYPE = 0,\n\t\tNFS4_SPECIAL_STATEID_TYPE = 1,\n\t\tNFS4_OPEN_STATEID_TYPE = 2,\n\t\tNFS4_LOCK_STATEID_TYPE = 3,\n\t\tNFS4_DELEGATION_STATEID_TYPE = 4,\n\t\tNFS4_LAYOUT_STATEID_TYPE = 5,\n\t\tNFS4_PNFS_DS_STATEID_TYPE = 6,\n\t\tNFS4_REVOKED_STATEID_TYPE = 7,\n\t\tNFS4_FREED_STATEID_TYPE = 8,\n\t} type;\n};\n\ntypedef struct nfs4_stateid_struct nfs4_stateid;\n\nstruct nfs_fsid {\n\tuint64_t major;\n\tuint64_t minor;\n};\n\nstruct cb_layoutrecallargs {\n\tuint32_t cbl_recall_type;\n\tuint32_t cbl_layout_type;\n\tuint32_t cbl_layoutchanged;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct nfs_fh cbl_fh;\n\t\t\tlong: 32;\n\t\t\tstruct pnfs_layout_range cbl_range;\n\t\t\tnfs4_stateid cbl_stateid;\n\t\t\tlong: 32;\n\t\t};\n\t\tstruct nfs_fsid cbl_fsid;\n\t};\n};\n\nstruct nfs_lowner {\n\t__u64 clientid;\n\t__u64 id;\n\tdev_t s_dev;\n\tlong: 32;\n};\n\nstruct cb_notify_lock_args {\n\tstruct nfs_fh cbnl_fh;\n\tlong: 32;\n\tstruct nfs_lowner cbnl_owner;\n\tbool cbnl_valid;\n\tlong: 32;\n};\n\nstruct nfs_write_verifier {\n\tchar data[8];\n};\n\nstruct nfs_writeverf {\n\tstruct nfs_write_verifier verifier;\n\tenum nfs3_stable_how committed;\n};\n\nstruct cb_offloadargs {\n\tstruct nfs_fh coa_fh;\n\tnfs4_stateid coa_stateid;\n\tuint32_t error;\n\tlong: 32;\n\tuint64_t wr_count;\n\tstruct nfs_writeverf wr_writeverf;\n\tlong: 32;\n};\n\nstruct nfs_client;\n\nstruct nfs4_slot;\n\nstruct cb_process_state {\n\tstruct nfs_client *clp;\n\tstruct nfs4_slot *slot;\n\tstruct net *net;\n\tu32 minorversion;\n\t__be32 drc_status;\n\tunsigned int referring_calls;\n};\n\nstruct cb_recallanyargs {\n\tuint32_t craa_objs_to_keep;\n\tuint32_t craa_type_mask;\n};\n\nstruct cb_recallargs {\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tuint32_t truncate;\n};\n\nstruct cb_recallslotargs {\n\tuint32_t crsa_target_highest_slotid;\n};\n\nstruct nfs4_sessionid {\n\tunsigned char data[16];\n};\n\nstruct referring_call_list;\n\nstruct cb_sequenceargs {\n\tstruct sockaddr *csa_addr;\n\tstruct nfs4_sessionid csa_sessionid;\n\tuint32_t csa_sequenceid;\n\tuint32_t csa_slotid;\n\tuint32_t csa_highestslotid;\n\tuint32_t csa_cachethis;\n\tuint32_t csa_nrclists;\n\tstruct referring_call_list *csa_rclists;\n};\n\nstruct cb_sequenceres {\n\t__be32 csr_status;\n\tstruct nfs4_sessionid csr_sessionid;\n\tuint32_t csr_sequenceid;\n\tuint32_t csr_slotid;\n\tuint32_t csr_highestslotid;\n\tuint32_t csr_target_highestslotid;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct clock_event_device;\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct cee_pfc {\n\t__u8 willing;\n\t__u8 error;\n\t__u8 pfc_en;\n\t__u8 tcs_supported;\n};\n\nstruct cee_pg {\n\t__u8 willing;\n\t__u8 error;\n\t__u8 pg_en;\n\t__u8 tcs_supported;\n\t__u8 pg_bw[8];\n\t__u8 prio_pg[8];\n};\n\nstruct cfi_private;\n\nstruct cfi_early_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct cfi_private *);\n};\n\nstruct cfi_extquery {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n};\n\nstruct mtd_info;\n\nstruct cfi_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct mtd_info *);\n};\n\nstruct cfi_ident {\n\tuint8_t qry[3];\n\tuint16_t P_ID;\n\tuint16_t P_ADR;\n\tuint16_t A_ID;\n\tuint16_t A_ADR;\n\tuint8_t VccMin;\n\tuint8_t VccMax;\n\tuint8_t VppMin;\n\tuint8_t VppMax;\n\tuint8_t WordWriteTimeoutTyp;\n\tuint8_t BufWriteTimeoutTyp;\n\tuint8_t BlockEraseTimeoutTyp;\n\tuint8_t ChipEraseTimeoutTyp;\n\tuint8_t WordWriteTimeoutMax;\n\tuint8_t BufWriteTimeoutMax;\n\tuint8_t BlockEraseTimeoutMax;\n\tuint8_t ChipEraseTimeoutMax;\n\tuint8_t DevSize;\n\tuint16_t InterfaceDesc;\n\tuint16_t MaxBufWriteSize;\n\tuint8_t NumEraseRegions;\n\tuint32_t EraseRegionInfo[0];\n} __attribute__((packed));\n\nstruct cfi_intelext_blockinfo {\n\tuint16_t NumIdentBlocks;\n\tuint16_t BlockSize;\n\tuint16_t MinBlockEraseCycles;\n\tuint8_t BitsPerCell;\n\tuint8_t BlockCap;\n};\n\nstruct cfi_intelext_otpinfo {\n\tuint32_t ProtRegAddr;\n\tuint16_t FactGroups;\n\tuint8_t FactProtRegSize;\n\tuint16_t UserGroups;\n\tuint8_t UserProtRegSize;\n} __attribute__((packed));\n\nstruct cfi_intelext_programming_regioninfo {\n\tuint8_t ProgRegShift;\n\tuint8_t Reserved1;\n\tuint8_t ControlValid;\n\tuint8_t Reserved2;\n\tuint8_t ControlInvalid;\n\tuint8_t Reserved3;\n};\n\nstruct cfi_intelext_regioninfo {\n\tuint16_t NumIdentPartitions;\n\tuint8_t NumOpAllowed;\n\tuint8_t NumOpAllowedSimProgMode;\n\tuint8_t NumOpAllowedSimEraMode;\n\tuint8_t NumBlockTypes;\n\tstruct cfi_intelext_blockinfo BlockTypes[1];\n};\n\nstruct cfi_pri_atmel {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n\tuint8_t Features;\n\tuint8_t BottomBoot;\n\tuint8_t BurstMode;\n\tuint8_t PageMode;\n};\n\nstruct cfi_pri_intelext {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n\tuint32_t FeatureSupport;\n\tuint8_t SuspendCmdSupport;\n\tuint16_t BlkStatusRegMask;\n\tuint8_t VccOptimal;\n\tuint8_t VppOptimal;\n\tuint8_t NumProtectionFields;\n\tuint16_t ProtRegAddr;\n\tuint8_t FactProtRegSize;\n\tuint8_t UserProtRegSize;\n\tuint8_t extra[0];\n} __attribute__((packed));\n\nstruct flchip {\n\tlong unsigned int start;\n\tint ref_point_counter;\n\tflstate_t state;\n\tflstate_t oldstate;\n\tunsigned int write_suspended: 1;\n\tunsigned int erase_suspended: 1;\n\tlong unsigned int in_progress_block_addr;\n\tlong unsigned int in_progress_block_mask;\n\tstruct mutex mutex;\n\twait_queue_head_t wq;\n\tint word_write_time;\n\tint buffer_write_time;\n\tint erase_time;\n\tint word_write_time_max;\n\tint buffer_write_time_max;\n\tint erase_time_max;\n\tvoid *priv;\n};\n\nstruct map_info;\n\nstruct cfi_private {\n\tuint16_t cmdset;\n\tvoid *cmdset_priv;\n\tint interleave;\n\tint device_type;\n\tint cfi_mode;\n\tint addr_unlock1;\n\tint addr_unlock2;\n\tstruct mtd_info * (*cmdset_setup)(struct map_info *);\n\tstruct cfi_ident *cfiq;\n\tint mfr;\n\tint id;\n\tint numchips;\n\tmap_word sector_erase_cmd;\n\tlong unsigned int chipshift;\n\tconst char *im_name;\n\tlong unsigned int quirks;\n\tstruct flchip chips[0];\n};\n\nstruct cfs_bandwidth {\n\traw_spinlock_t lock;\n\tlong: 32;\n\tktime_t period;\n\tu64 quota;\n\tu64 runtime;\n\tu64 burst;\n\tu64 runtime_snap;\n\ts64 hierarchical_quota;\n\tu8 idle;\n\tu8 period_active;\n\tu8 slack_started;\n\tlong: 32;\n\tstruct hrtimer period_timer;\n\tstruct hrtimer slack_timer;\n\tstruct list_head throttled_cfs_rq;\n\tint nr_periods;\n\tint nr_throttled;\n\tint nr_burst;\n\tlong: 32;\n\tu64 throttled_time;\n\tu64 burst_time;\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sched_entity;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_avg avg;\n\tu64 last_update_time_copy;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tint runtime_enabled;\n\ts64 runtime_remaining;\n\tu64 throttled_pelt_idle;\n\tu64 throttled_pelt_idle_copy;\n\tu64 throttled_clock;\n\tu64 throttled_clock_pelt;\n\tu64 throttled_clock_pelt_time;\n\tu64 throttled_clock_self;\n\tu64 throttled_clock_self_time;\n\tbool throttled: 1;\n\tbool pelt_clock_throttled: 1;\n\tint throttle_count;\n\tstruct list_head throttled_list;\n\tstruct list_head throttled_csd_list;\n\tstruct list_head throttled_limbo_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cfs_schedulable_data {\n\tstruct task_group *tg;\n\tlong: 32;\n\tu64 period;\n\tu64 quota;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 ntime;\n};\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n\tlong: 32;\n};\n\nstruct cgroup_bpf {};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[0];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[8];\n\tint nr_dying_subsys[8];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[8];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n\tlong: 32;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tlong: 32;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct chip_probe {\n\tchar *name;\n\tint (*probe_chip)(struct map_info *, __u32, long unsigned int *, struct cfi_private *);\n};\n\nstruct chip_props {\n\tu8 flags;\n\tu8 reg_off_sticky;\n\tu8 reg_off_ena;\n\tu8 reg_off_ena_clr;\n\tu8 reg_off_ena_set;\n\tu8 reg_off_ident;\n\tu8 reg_off_trigger;\n\tu8 reg_off_ena_irq0;\n\tu8 n_irq;\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct mmc_card;\n\nstruct sdio_func;\n\ntypedef int tpl_parse_t(struct mmc_card *, struct sdio_func *, const unsigned char *, unsigned int);\n\nstruct cis_tpl {\n\tunsigned char code;\n\tunsigned char min_size;\n\ttpl_parse_t *parse;\n};\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_info {\n\tint class;\n\tchar *class_name;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct clk_core;\n\nstruct clk {\n\tstruct clk_core *core;\n\tstruct device *dev;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tunsigned int exclusive_count;\n\tstruct hlist_node clks_node;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct clk_bulk_devres {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct clk_init_data;\n\nstruct clk_hw {\n\tstruct clk_core *core;\n\tstruct clk *clk;\n\tconst struct clk_init_data *init;\n};\n\nstruct clk_rate_request;\n\nstruct clk_duty;\n\nstruct clk_ops {\n\tint (*prepare)(struct clk_hw *);\n\tvoid (*unprepare)(struct clk_hw *);\n\tint (*is_prepared)(struct clk_hw *);\n\tvoid (*unprepare_unused)(struct clk_hw *);\n\tint (*enable)(struct clk_hw *);\n\tvoid (*disable)(struct clk_hw *);\n\tint (*is_enabled)(struct clk_hw *);\n\tvoid (*disable_unused)(struct clk_hw *);\n\tint (*save_context)(struct clk_hw *);\n\tvoid (*restore_context)(struct clk_hw *);\n\tlong unsigned int (*recalc_rate)(struct clk_hw *, long unsigned int);\n\tlong int (*round_rate)(struct clk_hw *, long unsigned int, long unsigned int *);\n\tint (*determine_rate)(struct clk_hw *, struct clk_rate_request *);\n\tint (*set_parent)(struct clk_hw *, u8);\n\tu8 (*get_parent)(struct clk_hw *);\n\tint (*set_rate)(struct clk_hw *, long unsigned int, long unsigned int);\n\tint (*set_rate_and_parent)(struct clk_hw *, long unsigned int, long unsigned int, u8);\n\tlong unsigned int (*recalc_accuracy)(struct clk_hw *, long unsigned int);\n\tint (*get_phase)(struct clk_hw *);\n\tint (*set_phase)(struct clk_hw *, int);\n\tint (*get_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*set_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*init)(struct clk_hw *);\n\tvoid (*terminate)(struct clk_hw *);\n\tvoid (*debug_init)(struct clk_hw *, struct dentry *);\n};\n\nstruct clk_composite {\n\tstruct clk_hw hw;\n\tstruct clk_ops ops;\n\tstruct clk_hw *mux_hw;\n\tstruct clk_hw *rate_hw;\n\tstruct clk_hw *gate_hw;\n\tconst struct clk_ops *mux_ops;\n\tconst struct clk_ops *rate_ops;\n\tconst struct clk_ops *gate_ops;\n};\n\nstruct clk_duty {\n\tunsigned int num;\n\tunsigned int den;\n};\n\nstruct clk_parent_map;\n\nstruct clk_core {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tstruct clk_hw *hw;\n\tstruct module *owner;\n\tstruct device *dev;\n\tstruct hlist_node rpm_node;\n\tstruct device_node *of_node;\n\tstruct clk_core *parent;\n\tstruct clk_parent_map *parents;\n\tu8 num_parents;\n\tu8 new_parent_index;\n\tlong unsigned int rate;\n\tlong unsigned int req_rate;\n\tlong unsigned int new_rate;\n\tstruct clk_core *new_parent;\n\tstruct clk_core *new_child;\n\tlong unsigned int flags;\n\tbool orphan;\n\tbool rpm_enabled;\n\tunsigned int enable_count;\n\tunsigned int prepare_count;\n\tunsigned int protect_count;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int accuracy;\n\tint phase;\n\tstruct clk_duty duty;\n\tstruct hlist_head children;\n\tstruct hlist_node child_node;\n\tstruct hlist_node hashtable_node;\n\tstruct hlist_head clks;\n\tunsigned int notifier_count;\n\tstruct dentry *dentry;\n\tstruct hlist_node debug_node;\n\tstruct kref ref;\n};\n\nstruct clk_div_table {\n\tunsigned int val;\n\tunsigned int div;\n};\n\nstruct clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu16 flags;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct clk_fixed_factor {\n\tstruct clk_hw hw;\n\tunsigned int mult;\n\tunsigned int div;\n\tlong unsigned int acc;\n\tunsigned int flags;\n};\n\nstruct clk_fixed_rate {\n\tstruct clk_hw hw;\n\tlong unsigned int fixed_rate;\n\tlong unsigned int fixed_accuracy;\n\tlong unsigned int flags;\n};\n\nstruct clk_fractional_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 mshift;\n\tu8 mwidth;\n\tu8 nshift;\n\tu8 nwidth;\n\tu8 flags;\n\tvoid (*approximation)(struct clk_hw *, long unsigned int, long unsigned int *, long unsigned int *, long unsigned int *);\n\tspinlock_t *lock;\n};\n\nstruct clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct gpio_desc;\n\nstruct clk_gpio {\n\tstruct clk_hw hw;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct clk_gated_fixed {\n\tstruct clk_gpio clk_gpio;\n\tstruct regulator *supply;\n\tlong unsigned int rate;\n};\n\nstruct clk_hw_onecell_data {\n\tunsigned int num;\n\tstruct clk_hw *hws[0];\n};\n\nstruct clk_parent_data;\n\nstruct clk_init_data {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tconst char * const *parent_names;\n\tconst struct clk_parent_data *parent_data;\n\tconst struct clk_hw **parent_hws;\n\tu8 num_parents;\n\tlong unsigned int flags;\n};\n\nstruct clk_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct clk *clk;\n\tstruct clk_hw *clk_hw;\n};\n\nstruct clk_lookup_alloc {\n\tstruct clk_lookup cl;\n\tchar dev_id[24];\n\tchar con_id[16];\n};\n\nstruct clk_multiplier {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tconst u32 *table;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct srcu_node;\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[2];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct clk_notifier {\n\tstruct clk *clk;\n\tstruct srcu_notifier_head notifier_head;\n\tstruct list_head node;\n};\n\nstruct clk_notifier_data {\n\tstruct clk *clk;\n\tlong unsigned int old_rate;\n\tlong unsigned int new_rate;\n};\n\nstruct clk_notifier_devres {\n\tstruct clk *clk;\n\tstruct notifier_block *nb;\n};\n\nstruct clk_onecell_data {\n\tstruct clk **clks;\n\tunsigned int clk_num;\n};\n\nstruct clk_parent_data {\n\tconst struct clk_hw *hw;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_parent_map {\n\tconst struct clk_hw *hw;\n\tstruct clk_core *core;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_rate_request {\n\tstruct clk_core *core;\n\tlong unsigned int rate;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int best_parent_rate;\n\tstruct clk_hw *best_parent_hw;\n};\n\nstruct clock_read_data {\n\tu64 epoch_ns;\n\tu64 epoch_cyc;\n\tu64 sched_clock_mask;\n\tu64 (*read_sched_clock)(void);\n\tu32 mult;\n\tu32 shift;\n\tlong: 32;\n};\n\nstruct clock_data {\n\tseqcount_latch_t seq;\n\tlong: 32;\n\tstruct clock_read_data read_data[2];\n\tktime_t wrap_kt;\n\tlong unsigned int rate;\n\tu64 (*actual_read_sched_clock)(void);\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tlong: 32;\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct clock_provider {\n\tvoid (*clk_init_cb)(struct device_node *);\n\tstruct device_node *np;\n\tstruct list_head node;\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tlong: 32;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct list_head wd_list;\n\tlong: 32;\n\tu64 cs_last;\n\tu64 wd_last;\n\tstruct module *owner;\n\tlong: 32;\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct core_boot_config;\n\nstruct cluster_boot_config {\n\tlong unsigned int *core_power;\n\tstruct cpumask cpumask;\n\tstruct core_boot_config *core_config;\n};\n\nstruct mtd_partition;\n\nstruct cmdline_mtd_partition {\n\tstruct cmdline_mtd_partition *next;\n\tchar *mtd_id;\n\tint num_parts;\n\tstruct mtd_partition *parts;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct co_format {\n\tunsigned int func: 6;\n\tunsigned int code: 19;\n\tunsigned int co: 1;\n\tunsigned int opcode: 6;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n\tlong: 32;\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[11];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_nfs_string {\n\tcompat_uint_t len;\n\tcompat_uptr_t data;\n};\n\nstruct compat_nfs4_mount_data_v1 {\n\tcompat_int_t version;\n\tcompat_int_t flags;\n\tcompat_int_t rsize;\n\tcompat_int_t wsize;\n\tcompat_int_t timeo;\n\tcompat_int_t retrans;\n\tcompat_int_t acregmin;\n\tcompat_int_t acregmax;\n\tcompat_int_t acdirmin;\n\tcompat_int_t acdirmax;\n\tstruct compat_nfs_string client_addr;\n\tstruct compat_nfs_string mnt_path;\n\tstruct compat_nfs_string hostname;\n\tcompat_uint_t host_addrlen;\n\tcompat_uptr_t host_addr;\n\tcompat_int_t proto;\n\tcompat_int_t auth_flavourlen;\n\tcompat_uptr_t auth_flavours;\n};\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\nstruct compound_hdr {\n\tint32_t status;\n\tuint32_t nops;\n\t__be32 *nops_p;\n\tuint32_t taglen;\n\tchar *tag;\n\tuint32_t replen;\n\tu32 minorversion;\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct connect_timeout_data {\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct console;\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tlong: 32;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tlong: 32;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct;\n\nstruct console___2 {\n\tstruct list_head list;\n\tstruct hvc_struct *hvc;\n\tstruct winsize ws;\n\tu32 vtermno;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n\tlong: 32;\n};\n\nstruct context_tracking {\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct virtio_net_ctrl_hdr {\n\t__u8 class;\n\t__u8 cmd;\n};\n\nstruct control_buf {\n\tstruct virtio_net_ctrl_hdr hdr;\n\tvirtio_net_ctrl_ack status;\n};\n\nstruct vpe_boot_config;\n\nstruct core_boot_config {\n\tatomic_t vpe_mask;\n\tstruct vpe_boot_config *vpe_config;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tlong: 32;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct regulator_dev;\n\nstruct regulator_coupler;\n\nstruct coupling_desc {\n\tstruct regulator_dev **coupled_rdevs;\n\tstruct regulator_coupler *coupler;\n\tint n_resolved;\n\tint n_coupled;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct cpu_ipi_domain_state {\n\tlong unsigned int allocated[1];\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct kernel_cpustat;\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tu64 *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tlong: 32;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tlong: 32;\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tlong: 32;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct guest_info {\n\tlong unsigned int ases;\n\tlong unsigned int ases_dyn;\n\tlong long unsigned int options;\n\tlong long unsigned int options_dyn;\n\tint tlbsize;\n\tu8 conf;\n\tu8 kscratch_mask;\n};\n\nstruct cpuinfo_mips {\n\tu64 asid_cache;\n\tlong unsigned int ases;\n\tlong: 32;\n\tlong long unsigned int options;\n\tunsigned int udelay_val;\n\tunsigned int processor_id;\n\tunsigned int fpu_id;\n\tunsigned int fpu_csr31;\n\tunsigned int fpu_msk31;\n\tunsigned int msa_id;\n\tunsigned int cputype;\n\tint isa_level;\n\tint tlbsize;\n\tint tlbsizevtlb;\n\tint tlbsizeftlbsets;\n\tint tlbsizeftlbways;\n\tstruct cache_desc icache;\n\tstruct cache_desc dcache;\n\tstruct cache_desc vcache;\n\tstruct cache_desc scache;\n\tstruct cache_desc tcache;\n\tint srsets;\n\tint package;\n\tunsigned int globalnumber;\n\tvoid *data;\n\tunsigned int watch_reg_count;\n\tunsigned int watch_reg_use_cnt;\n\tu16 watch_reg_masks[4];\n\tunsigned int kscratch_mask;\n\tunsigned int writecombine;\n\tunsigned int htw_seq;\n\tstruct guest_info guest;\n\tunsigned int gtoffset_mask;\n\tunsigned int guestid_mask;\n\tunsigned int guestid_cache;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tlong: 32;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct cqhci_host_ops;\n\nstruct mmc_host;\n\nstruct cqhci_slot;\n\nstruct cqhci_host {\n\tconst struct cqhci_host_ops *ops;\n\tvoid *mmio;\n\tstruct mmc_host *mmc;\n\tspinlock_t lock;\n\tunsigned int rca;\n\tbool dma64;\n\tint num_slots;\n\tint qcnt;\n\tu32 dcmd_slot;\n\tu32 caps;\n\tu32 quirks;\n\tbool enabled;\n\tbool halted;\n\tbool init_done;\n\tbool activated;\n\tbool waiting_for_idle;\n\tbool recovery_halt;\n\tsize_t desc_size;\n\tsize_t data_size;\n\tu8 *desc_base;\n\tu8 slot_sz;\n\tu8 task_desc_len;\n\tu8 link_desc_len;\n\tu8 *trans_desc_base;\n\tu8 trans_desc_len;\n\tdma_addr_t desc_dma_base;\n\tdma_addr_t trans_desc_dma_base;\n\tstruct completion halt_comp;\n\twait_queue_head_t wait_queue;\n\tstruct cqhci_slot *slot;\n};\n\nstruct mmc_request;\n\nstruct cqhci_host_ops {\n\tvoid (*dumpregs)(struct mmc_host *);\n\tvoid (*write_l)(struct cqhci_host *, u32, int);\n\tu32 (*read_l)(struct cqhci_host *, int);\n\tvoid (*enable)(struct mmc_host *);\n\tvoid (*disable)(struct mmc_host *, bool);\n\tvoid (*update_dcmd_desc)(struct mmc_host *, struct mmc_request *, u64 *);\n\tvoid (*pre_enable)(struct mmc_host *);\n\tvoid (*post_disable)(struct mmc_host *);\n\tvoid (*set_tran_desc)(struct cqhci_host *, u8 **, dma_addr_t, int, bool, bool);\n};\n\nstruct cqhci_slot {\n\tstruct mmc_request *mrq;\n\tunsigned int flags;\n};\n\nstruct cramfs_info {\n\t__u32 crc;\n\t__u32 edition;\n\t__u32 blocks;\n\t__u32 files;\n};\n\nstruct cramfs_inode {\n\t__u32 mode: 16;\n\t__u32 uid: 16;\n\t__u32 size: 24;\n\t__u32 gid: 8;\n\t__u32 namelen: 6;\n\t__u32 offset: 26;\n};\n\nstruct cramfs_super {\n\t__u32 magic;\n\t__u32 size;\n\t__u32 flags;\n\t__u32 future;\n\t__u8 signature[16];\n\tstruct cramfs_info fsid;\n\t__u8 name[16];\n\tstruct cramfs_inode root;\n};\n\ntypedef const struct cred *class_copy_up_creds_t;\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef class_override_creds_t class_override_creds_ovl_t;\n\ntypedef const struct cred *class_ovl_override_creator_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n\tlong: 32;\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_acomp_stream {\n\tspinlock_t lock;\n\tvoid *ctx;\n};\n\nstruct crypto_acomp_streams {\n\tvoid * (*alloc_ctx)(void);\n\tvoid (*free_ctx)(void *);\n\tstruct crypto_acomp_stream *streams;\n\tstruct work_struct stream_work;\n\tcpumask_t stream_want;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_aes_ctx {\n\tu32 key_enc[60];\n\tu32 key_dec[60];\n\tu32 key_length;\n};\n\nstruct crypto_ahash {\n\tbool using_shash;\n\tunsigned int statesize;\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_akcipher {\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_akcipher_sync_data {\n\tstruct crypto_akcipher *tfm;\n\tconst void *src;\n\tvoid *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct akcipher_request *req;\n\tstruct crypto_wait cwait;\n\tstruct scatterlist sg;\n\tu8 *buf;\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher;\n\nstruct crypto_cts_ctx {\n\tstruct crypto_skcipher *child;\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_cts_reqctx {\n\tstruct scatterlist sg[2];\n\tunsigned int offset;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct skcipher_request subreq;\n};\n\nstruct crypto_hash_walk {\n\tconst char *data;\n\tunsigned int offset;\n\tunsigned int flags;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n};\n\nstruct crypto_kpp {\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_kpp_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n\tbool test_started;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct crypto_lskcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_lskcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sig {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sig_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sync_aead {\n\tstruct crypto_aead base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct hlist_head dead;\n\tstruct module *module;\n\tstruct work_struct free_work;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tvoid (*destroy)(struct crypto_alg *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n\tunsigned int algsize;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_alg data;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[8];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[8];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ctl_table;\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct fuse_conn;\n\nstruct fuse_mount {\n\tstruct fuse_conn *fc;\n\tstruct super_block *sb;\n\tstruct list_head fc_entry;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_forget_one {\n\tuint64_t nodeid;\n\tuint64_t nlookup;\n};\n\nstruct fuse_forget_link {\n\tstruct fuse_forget_one forget_one;\n\tstruct fuse_forget_link *next;\n\tlong: 32;\n};\n\nstruct fasync_struct;\n\nstruct fuse_iqueue_ops;\n\nstruct fuse_iqueue {\n\tunsigned int connected;\n\tspinlock_t lock;\n\twait_queue_head_t waitq;\n\tlong: 32;\n\tu64 reqctr;\n\tstruct list_head pending;\n\tstruct list_head interrupts;\n\tstruct fuse_forget_link forget_list_head;\n\tstruct fuse_forget_link *forget_list_tail;\n\tint forget_batch;\n\tstruct fasync_struct *fasync;\n\tconst struct fuse_iqueue_ops *ops;\n\tvoid *priv;\n\tlong: 32;\n};\n\nstruct fuse_sync_bucket;\n\nstruct fuse_ring;\n\nstruct fuse_conn {\n\tspinlock_t lock;\n\trefcount_t count;\n\tatomic_t dev_count;\n\tatomic_t epoch;\n\tstruct work_struct epoch_work;\n\tstruct callback_head rcu;\n\tkuid_t user_id;\n\tkgid_t group_id;\n\tstruct pid_namespace *pid_ns;\n\tstruct user_namespace *user_ns;\n\tunsigned int max_read;\n\tunsigned int max_write;\n\tunsigned int max_pages;\n\tunsigned int max_pages_limit;\n\tstruct fuse_iqueue iq;\n\tatomic64_t khctr;\n\tstruct rb_root polled_files;\n\tunsigned int max_background;\n\tunsigned int congestion_threshold;\n\tunsigned int num_background;\n\tunsigned int active_background;\n\tstruct list_head bg_queue;\n\tspinlock_t bg_lock;\n\tint initialized;\n\tint blocked;\n\twait_queue_head_t blocked_waitq;\n\tunsigned int connected;\n\tbool aborted;\n\tunsigned int conn_error: 1;\n\tunsigned int conn_init: 1;\n\tunsigned int async_read: 1;\n\tunsigned int abort_err: 1;\n\tunsigned int atomic_o_trunc: 1;\n\tunsigned int export_support: 1;\n\tunsigned int writeback_cache: 1;\n\tunsigned int parallel_dirops: 1;\n\tunsigned int handle_killpriv: 1;\n\tunsigned int cache_symlinks: 1;\n\tunsigned int legacy_opts_show: 1;\n\tunsigned int handle_killpriv_v2: 1;\n\tunsigned int no_open: 1;\n\tunsigned int no_opendir: 1;\n\tunsigned int no_fsync: 1;\n\tunsigned int no_fsyncdir: 1;\n\tunsigned int no_flush: 1;\n\tunsigned int no_setxattr: 1;\n\tunsigned int setxattr_ext: 1;\n\tunsigned int no_getxattr: 1;\n\tunsigned int no_listxattr: 1;\n\tunsigned int no_removexattr: 1;\n\tunsigned int no_lock: 1;\n\tunsigned int no_access: 1;\n\tunsigned int no_create: 1;\n\tunsigned int no_interrupt: 1;\n\tunsigned int no_bmap: 1;\n\tunsigned int no_poll: 1;\n\tunsigned int big_writes: 1;\n\tunsigned int dont_mask: 1;\n\tunsigned int no_flock: 1;\n\tunsigned int no_fallocate: 1;\n\tunsigned int no_rename2: 1;\n\tunsigned int auto_inval_data: 1;\n\tunsigned int explicit_inval_data: 1;\n\tunsigned int do_readdirplus: 1;\n\tunsigned int readdirplus_auto: 1;\n\tunsigned int async_dio: 1;\n\tunsigned int no_lseek: 1;\n\tunsigned int posix_acl: 1;\n\tunsigned int default_permissions: 1;\n\tunsigned int allow_other: 1;\n\tunsigned int no_copy_file_range: 1;\n\tunsigned int no_copy_file_range_64: 1;\n\tunsigned int destroy: 1;\n\tunsigned int delete_stale: 1;\n\tunsigned int no_control: 1;\n\tunsigned int no_force_umount: 1;\n\tunsigned int auto_submounts: 1;\n\tunsigned int sync_fs: 1;\n\tunsigned int init_security: 1;\n\tunsigned int create_supp_group: 1;\n\tunsigned int inode_dax: 1;\n\tunsigned int no_tmpfile: 1;\n\tunsigned int direct_io_allow_mmap: 1;\n\tunsigned int no_statx: 1;\n\tunsigned int passthrough: 1;\n\tunsigned int use_pages_for_kvec_io: 1;\n\tunsigned int no_link: 1;\n\tunsigned int sync_init: 1;\n\tunsigned int io_uring;\n\tint max_stack_depth;\n\tatomic_t num_waiting;\n\tunsigned int minor;\n\tstruct list_head entry;\n\tdev_t dev;\n\tu32 scramble_key[4];\n\tatomic64_t attr_version;\n\tatomic64_t evict_ctr;\n\tu32 name_max;\n\tvoid (*release)(struct fuse_conn *);\n\tstruct rw_semaphore killsb;\n\tstruct list_head devices;\n\tstruct list_head mounts;\n\tstruct fuse_sync_bucket *curr_bucket;\n\tstruct idr backing_files_map;\n\tstruct fuse_ring *ring;\n\tstruct {\n\t\tstruct delayed_work work;\n\t\tunsigned int req_timeout;\n\t} timeout;\n};\n\nstruct cuse_conn {\n\tstruct list_head list;\n\tstruct fuse_mount fm;\n\tstruct fuse_conn fc;\n\tstruct cdev *cdev;\n\tstruct device *dev;\n\tbool unrestricted_ioctl;\n\tlong: 32;\n};\n\nstruct cuse_devinfo {\n\tconst char *name;\n};\n\nstruct fuse_in_arg {\n\tunsigned int size;\n\tconst void *value;\n};\n\nstruct fuse_arg {\n\tunsigned int size;\n\tvoid *value;\n};\n\nstruct fuse_args {\n\tuint64_t nodeid;\n\tuint32_t opcode;\n\tuint8_t in_numargs;\n\tuint8_t out_numargs;\n\tuint8_t ext_idx;\n\tbool force: 1;\n\tbool noreply: 1;\n\tbool nocreds: 1;\n\tbool in_pages: 1;\n\tbool out_pages: 1;\n\tbool user_pages: 1;\n\tbool out_argvar: 1;\n\tbool page_zeroing: 1;\n\tbool page_replace: 1;\n\tbool may_block: 1;\n\tbool is_ext: 1;\n\tbool is_pinned: 1;\n\tbool invalidate_vmap: 1;\n\tstruct fuse_in_arg in_args[4];\n\tstruct fuse_arg out_args[2];\n\tvoid (*end)(struct fuse_mount *, struct fuse_args *, int);\n\tvoid *vmap_base;\n\tlong: 32;\n};\n\nstruct fuse_folio_desc;\n\nstruct fuse_args_pages {\n\tstruct fuse_args args;\n\tstruct folio **folios;\n\tstruct fuse_folio_desc *descs;\n\tunsigned int num_folios;\n\tlong: 32;\n};\n\nstruct cuse_init_in {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t unused;\n\tuint32_t flags;\n};\n\nstruct cuse_init_out {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t unused;\n\tuint32_t flags;\n\tuint32_t max_read;\n\tuint32_t max_write;\n\tuint32_t dev_major;\n\tuint32_t dev_minor;\n\tuint32_t spare[10];\n};\n\nstruct fuse_folio_desc {\n\tunsigned int length;\n\tunsigned int offset;\n};\n\nstruct cuse_init_args {\n\tstruct fuse_args_pages ap;\n\tstruct cuse_init_in in;\n\tstruct cuse_init_out out;\n\tstruct folio *folio;\n\tstruct fuse_folio_desc desc;\n\tlong: 32;\n};\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tlong: 32;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct llc_sap;\n\nstruct packet_type;\n\nstruct datalink_proto {\n\tunsigned char type[8];\n\tstruct llc_sap *sap;\n\tshort unsigned int header_length;\n\tint (*rcvfunc)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tint (*request)(struct datalink_proto *, struct sk_buff *, const unsigned char *);\n\tstruct list_head node;\n};\n\nstruct dax_device;\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct dcb_app {\n\t__u8 selector;\n\t__u8 priority;\n\t__u16 protocol;\n};\n\nstruct dcb_peer_app_info {\n\t__u8 willing;\n\t__u8 error;\n};\n\nstruct dcbnl_buffer {\n\t__u8 prio2buffer[8];\n\t__u32 buffer_size[8];\n\t__u32 total_size;\n};\n\nstruct ieee_ets;\n\nstruct ieee_maxrate;\n\nstruct ieee_qcn;\n\nstruct ieee_qcn_stats;\n\nstruct ieee_pfc;\n\nstruct dcbnl_rtnl_ops {\n\tint (*ieee_getets)(struct net_device *, struct ieee_ets *);\n\tint (*ieee_setets)(struct net_device *, struct ieee_ets *);\n\tint (*ieee_getmaxrate)(struct net_device *, struct ieee_maxrate *);\n\tint (*ieee_setmaxrate)(struct net_device *, struct ieee_maxrate *);\n\tint (*ieee_getqcn)(struct net_device *, struct ieee_qcn *);\n\tint (*ieee_setqcn)(struct net_device *, struct ieee_qcn *);\n\tint (*ieee_getqcnstats)(struct net_device *, struct ieee_qcn_stats *);\n\tint (*ieee_getpfc)(struct net_device *, struct ieee_pfc *);\n\tint (*ieee_setpfc)(struct net_device *, struct ieee_pfc *);\n\tint (*ieee_getapp)(struct net_device *, struct dcb_app *);\n\tint (*ieee_setapp)(struct net_device *, struct dcb_app *);\n\tint (*ieee_delapp)(struct net_device *, struct dcb_app *);\n\tint (*ieee_peer_getets)(struct net_device *, struct ieee_ets *);\n\tint (*ieee_peer_getpfc)(struct net_device *, struct ieee_pfc *);\n\tu8 (*getstate)(struct net_device *);\n\tu8 (*setstate)(struct net_device *, u8);\n\tvoid (*getpermhwaddr)(struct net_device *, u8 *);\n\tvoid (*setpgtccfgtx)(struct net_device *, int, u8, u8, u8, u8);\n\tvoid (*setpgbwgcfgtx)(struct net_device *, int, u8);\n\tvoid (*setpgtccfgrx)(struct net_device *, int, u8, u8, u8, u8);\n\tvoid (*setpgbwgcfgrx)(struct net_device *, int, u8);\n\tvoid (*getpgtccfgtx)(struct net_device *, int, u8 *, u8 *, u8 *, u8 *);\n\tvoid (*getpgbwgcfgtx)(struct net_device *, int, u8 *);\n\tvoid (*getpgtccfgrx)(struct net_device *, int, u8 *, u8 *, u8 *, u8 *);\n\tvoid (*getpgbwgcfgrx)(struct net_device *, int, u8 *);\n\tvoid (*setpfccfg)(struct net_device *, int, u8);\n\tvoid (*getpfccfg)(struct net_device *, int, u8 *);\n\tu8 (*setall)(struct net_device *);\n\tu8 (*getcap)(struct net_device *, int, u8 *);\n\tint (*getnumtcs)(struct net_device *, int, u8 *);\n\tint (*setnumtcs)(struct net_device *, int, u8);\n\tu8 (*getpfcstate)(struct net_device *);\n\tvoid (*setpfcstate)(struct net_device *, u8);\n\tvoid (*getbcncfg)(struct net_device *, int, u32 *);\n\tvoid (*setbcncfg)(struct net_device *, int, u32);\n\tvoid (*getbcnrp)(struct net_device *, int, u8 *);\n\tvoid (*setbcnrp)(struct net_device *, int, u8);\n\tint (*setapp)(struct net_device *, u8, u16, u8);\n\tint (*getapp)(struct net_device *, u8, u16);\n\tu8 (*getfeatcfg)(struct net_device *, int, u8 *);\n\tu8 (*setfeatcfg)(struct net_device *, int, u8);\n\tu8 (*getdcbx)(struct net_device *);\n\tu8 (*setdcbx)(struct net_device *, u8);\n\tint (*peer_getappinfo)(struct net_device *, struct dcb_peer_app_info *, u16 *);\n\tint (*peer_getapptable)(struct net_device *, struct dcb_app *);\n\tint (*cee_peer_getpg)(struct net_device *, struct cee_pg *);\n\tint (*cee_peer_getpfc)(struct net_device *, struct cee_pfc *);\n\tint (*dcbnl_getbuffer)(struct net_device *, struct dcbnl_buffer *);\n\tint (*dcbnl_setbuffer)(struct net_device *, struct dcbnl_buffer *);\n\tint (*dcbnl_setapptrust)(struct net_device *, u8 *, int);\n\tint (*dcbnl_getapptrust)(struct net_device *, u8 *, int *);\n\tint (*dcbnl_setrewr)(struct net_device *, struct dcb_app *);\n\tint (*dcbnl_delrewr)(struct net_device *, struct dcb_app *);\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct ohci_hcd;\n\nstruct debug_buffer {\n\tssize_t (*fill_func)(struct debug_buffer *);\n\tstruct ohci_hcd *ohci;\n\tstruct mutex mutex;\n\tsize_t count;\n\tchar *page;\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct decryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tstruct scatterlist frags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct filename;\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n\tlong: 32;\n};\n\nunion shortname_store {\n\tunsigned char string[36];\n\tlong unsigned int words[9];\n};\n\nstruct lockref {\n\tunion {\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tlong: 32;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n\tlong: 32;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_bucket {\n\tstruct rb_root tree;\n\tspinlock_t lock;\n};\n\nstruct dentry_info_args {\n\tint parent_ino;\n\tint dname_len;\n\tint ino;\n\tint inode_len;\n\tchar *dname;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct dev_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head exceptions;\n\tenum devcg_behavior behavior;\n\tlong: 32;\n};\n\nstruct dev_exception_item {\n\tu32 major;\n\tu32 minor;\n\tshort int type;\n\tshort int access;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct dev_pin_info {\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *default_state;\n\tstruct pinctrl_state *init_state;\n\tstruct pinctrl_state *sleep_state;\n\tstruct pinctrl_state *idle_state;\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct dev_pm_domain_attach_data {\n\tconst char * const *pd_names;\n\tconst u32 num_pd_names;\n\tconst u32 pd_flags;\n};\n\nstruct device_link;\n\nstruct dev_pm_domain_list {\n\tstruct device **pd_devs;\n\tstruct device_link **pd_links;\n\tu32 *opp_tokens;\n\tu32 num_pds;\n};\n\nstruct opp_table;\n\nstruct dev_pm_opp;\n\ntypedef int (*config_clks_t)(struct device *, struct opp_table *, struct dev_pm_opp *, void *, bool);\n\ntypedef int (*config_regulators_t)(struct device *, struct dev_pm_opp *, struct dev_pm_opp *, struct regulator **, unsigned int);\n\nstruct dev_pm_opp_config {\n\tconst char * const *clk_names;\n\tconfig_clks_t config_clks;\n\tconst char *prop_name;\n\tconfig_regulators_t config_regulators;\n\tconst unsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char * const *regulator_names;\n\tstruct device *required_dev;\n\tunsigned int required_dev_index;\n};\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_pm_runtime_active_auto_t;\n\ntypedef class_pm_runtime_active_auto_t class_pm_runtime_active_auto_try_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\ntypedef struct device *class_pm_runtime_noresume_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct of_device_id;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n\tlong: 32;\n};\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tstruct kobject kobj;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n\tlong: 32;\n};\n\nstruct devlink_dev_stats {\n\tu32 reload_stats[6];\n\tu32 remote_reload_stats[6];\n};\n\nstruct devlink_dpipe_headers;\n\nstruct devlink_ops;\n\nstruct devlink_rel;\n\nstruct devlink {\n\tu32 index;\n\tstruct xarray ports;\n\tstruct list_head rate_list;\n\tstruct list_head sb_list;\n\tstruct list_head dpipe_table_list;\n\tstruct list_head resource_list;\n\tstruct xarray params;\n\tstruct list_head region_list;\n\tstruct list_head reporter_list;\n\tstruct devlink_dpipe_headers *dpipe_headers;\n\tstruct list_head trap_list;\n\tstruct list_head trap_group_list;\n\tstruct list_head trap_policer_list;\n\tstruct list_head linecard_list;\n\tconst struct devlink_ops *ops;\n\tstruct xarray snapshot_ids;\n\tstruct devlink_dev_stats stats;\n\tstruct device *dev;\n\tpossible_net_t _net;\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tu8 reload_failed: 1;\n\trefcount_t refcount;\n\tstruct rcu_work rwork;\n\tstruct devlink_rel *rel;\n\tstruct xarray nested_rels;\n\tlong: 32;\n\tchar priv[0];\n};\n\nstruct devlink_dpipe_header;\n\nstruct devlink_dpipe_action {\n\tenum devlink_dpipe_action_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct genl_info;\n\nstruct devlink_dpipe_dump_ctx {\n\tstruct genl_info *info;\n\tenum devlink_command cmd;\n\tstruct sk_buff *skb;\n\tstruct nlattr *nest;\n\tvoid *hdr;\n};\n\nstruct devlink_dpipe_value;\n\nstruct devlink_dpipe_entry {\n\tu64 index;\n\tstruct devlink_dpipe_value *match_values;\n\tunsigned int match_values_count;\n\tstruct devlink_dpipe_value *action_values;\n\tunsigned int action_values_count;\n\tu64 counter;\n\tbool counter_valid;\n\tlong: 32;\n};\n\nstruct devlink_dpipe_field {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int bitwidth;\n\tenum devlink_dpipe_field_mapping_type mapping_type;\n};\n\nstruct devlink_dpipe_header {\n\tconst char *name;\n\tunsigned int id;\n\tstruct devlink_dpipe_field *fields;\n\tunsigned int fields_count;\n\tbool global;\n};\n\nstruct devlink_dpipe_headers {\n\tstruct devlink_dpipe_header **headers;\n\tunsigned int headers_count;\n};\n\nstruct devlink_dpipe_match {\n\tenum devlink_dpipe_match_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct devlink_dpipe_table_ops;\n\nstruct devlink_dpipe_table {\n\tvoid *priv;\n\tstruct list_head list;\n\tconst char *name;\n\tbool counters_enabled;\n\tbool counter_control_extern;\n\tbool resource_valid;\n\tlong: 32;\n\tu64 resource_id;\n\tu64 resource_units;\n\tconst struct devlink_dpipe_table_ops *table_ops;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct devlink_dpipe_table_ops {\n\tint (*actions_dump)(void *, struct sk_buff *);\n\tint (*matches_dump)(void *, struct sk_buff *);\n\tint (*entries_dump)(void *, bool, struct devlink_dpipe_dump_ctx *);\n\tint (*counters_set_update)(void *, bool);\n\tu64 (*size_get)(void *);\n};\n\nstruct devlink_dpipe_value {\n\tunion {\n\t\tstruct devlink_dpipe_action *action;\n\t\tstruct devlink_dpipe_match *match;\n\t};\n\tunsigned int mapping_value;\n\tbool mapping_valid;\n\tunsigned int value_size;\n\tvoid *value;\n\tvoid *mask;\n};\n\nstruct devlink_flash_component_lookup_ctx {\n\tconst char *lookup_name;\n\tbool lookup_name_found;\n};\n\nstruct devlink_flash_notify {\n\tconst char *status_msg;\n\tconst char *component;\n\tlong unsigned int done;\n\tlong unsigned int total;\n\tlong unsigned int timeout;\n};\n\nstruct firmware;\n\nstruct devlink_flash_update_params {\n\tconst struct firmware *fw;\n\tconst char *component;\n\tu32 overwrite_mask;\n};\n\nstruct devlink_fmsg {\n\tstruct list_head item_list;\n\tint err;\n\tbool putting_binary;\n};\n\nstruct devlink_fmsg_item {\n\tstruct list_head list;\n\tint attrtype;\n\tu8 nla_type;\n\tu16 len;\n\tint value[0];\n};\n\nstruct devlink_health_reporter_ops;\n\nstruct devlink_port;\n\nstruct devlink_health_reporter {\n\tstruct list_head list;\n\tvoid *priv;\n\tconst struct devlink_health_reporter_ops *ops;\n\tstruct devlink *devlink;\n\tstruct devlink_port *devlink_port;\n\tstruct devlink_fmsg *dump_fmsg;\n\tlong: 32;\n\tu64 graceful_period;\n\tu64 burst_period;\n\tbool auto_recover;\n\tbool auto_dump;\n\tu8 health_state;\n\tlong: 32;\n\tu64 dump_ts;\n\tu64 dump_real_ts;\n\tu64 error_count;\n\tu64 recovery_count;\n\tu64 last_recovery_ts;\n};\n\nstruct devlink_health_reporter_ops {\n\tchar *name;\n\tint (*recover)(struct devlink_health_reporter *, void *, struct netlink_ext_ack *);\n\tint (*dump)(struct devlink_health_reporter *, struct devlink_fmsg *, void *, struct netlink_ext_ack *);\n\tint (*diagnose)(struct devlink_health_reporter *, struct devlink_fmsg *, struct netlink_ext_ack *);\n\tint (*test)(struct devlink_health_reporter *, struct netlink_ext_ack *);\n\tlong: 32;\n\tu64 default_graceful_period;\n\tu64 default_burst_period;\n};\n\nstruct devlink_info_req {\n\tstruct sk_buff *msg;\n\tvoid (*version_cb)(const char *, enum devlink_info_version_type, void *);\n\tvoid *version_cb_priv;\n};\n\nstruct devlink_linecard_ops;\n\nstruct devlink_linecard_type;\n\nstruct devlink_linecard {\n\tstruct list_head list;\n\tstruct devlink *devlink;\n\tunsigned int index;\n\tconst struct devlink_linecard_ops *ops;\n\tvoid *priv;\n\tenum devlink_linecard_state state;\n\tstruct mutex state_lock;\n\tconst char *type;\n\tstruct devlink_linecard_type *types;\n\tunsigned int types_count;\n\tu32 rel_index;\n};\n\nstruct devlink_linecard_ops {\n\tint (*provision)(struct devlink_linecard *, void *, const char *, const void *, struct netlink_ext_ack *);\n\tint (*unprovision)(struct devlink_linecard *, void *, struct netlink_ext_ack *);\n\tbool (*same_provision)(struct devlink_linecard *, void *, const char *, const void *);\n\tunsigned int (*types_count)(struct devlink_linecard *, void *);\n\tvoid (*types_get)(struct devlink_linecard *, void *, unsigned int, const char **, const void **);\n};\n\nstruct devlink_linecard_type {\n\tconst char *type;\n\tconst void *priv;\n};\n\nstruct devlink_nl_dump_state {\n\tlong unsigned int instance;\n\tint idx;\n\tunion {\n\t\tstruct {\n\t\t\tu64 start_offset;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dump_ts;\n\t\t};\n\t};\n};\n\nstruct devlink_obj_desc;\n\nstruct devlink_nl_sock_priv {\n\tstruct devlink_obj_desc *flt;\n\tspinlock_t flt_lock;\n};\n\nstruct devlink_obj_desc {\n\tstruct callback_head rcu;\n\tconst char *bus_name;\n\tconst char *dev_name;\n\tunsigned int port_index;\n\tbool port_index_valid;\n\tlong int data[0];\n};\n\nstruct devlink_sb_pool_info;\n\nstruct devlink_trap;\n\nstruct devlink_trap_group;\n\nstruct devlink_trap_policer;\n\nstruct devlink_port_new_attrs;\n\nstruct devlink_rate;\n\nstruct devlink_ops {\n\tu32 supported_flash_update_params;\n\tlong unsigned int reload_actions;\n\tlong unsigned int reload_limits;\n\tint (*reload_down)(struct devlink *, bool, enum devlink_reload_action, enum devlink_reload_limit, struct netlink_ext_ack *);\n\tint (*reload_up)(struct devlink *, enum devlink_reload_action, enum devlink_reload_limit, u32 *, struct netlink_ext_ack *);\n\tint (*sb_pool_get)(struct devlink *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*sb_pool_set)(struct devlink *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*sb_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *);\n\tint (*sb_port_pool_set)(struct devlink_port *, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_tc_pool_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*sb_tc_pool_bind_set)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_occ_snapshot)(struct devlink *, unsigned int);\n\tint (*sb_occ_max_clear)(struct devlink *, unsigned int);\n\tint (*sb_occ_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *, u32 *);\n\tint (*sb_occ_tc_port_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*eswitch_mode_get)(struct devlink *, u16 *);\n\tint (*eswitch_mode_set)(struct devlink *, u16, struct netlink_ext_ack *);\n\tint (*eswitch_inline_mode_get)(struct devlink *, u8 *);\n\tint (*eswitch_inline_mode_set)(struct devlink *, u8, struct netlink_ext_ack *);\n\tint (*eswitch_encap_mode_get)(struct devlink *, enum devlink_eswitch_encap_mode *);\n\tint (*eswitch_encap_mode_set)(struct devlink *, enum devlink_eswitch_encap_mode, struct netlink_ext_ack *);\n\tint (*info_get)(struct devlink *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*flash_update)(struct devlink *, struct devlink_flash_update_params *, struct netlink_ext_ack *);\n\tint (*trap_init)(struct devlink *, const struct devlink_trap *, void *);\n\tvoid (*trap_fini)(struct devlink *, const struct devlink_trap *, void *);\n\tint (*trap_action_set)(struct devlink *, const struct devlink_trap *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_group_init)(struct devlink *, const struct devlink_trap_group *);\n\tint (*trap_group_set)(struct devlink *, const struct devlink_trap_group *, const struct devlink_trap_policer *, struct netlink_ext_ack *);\n\tint (*trap_group_action_set)(struct devlink *, const struct devlink_trap_group *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_drop_counter_get)(struct devlink *, const struct devlink_trap *, u64 *);\n\tint (*trap_policer_init)(struct devlink *, const struct devlink_trap_policer *);\n\tvoid (*trap_policer_fini)(struct devlink *, const struct devlink_trap_policer *);\n\tint (*trap_policer_set)(struct devlink *, const struct devlink_trap_policer *, u64, u64, struct netlink_ext_ack *);\n\tint (*trap_policer_counter_get)(struct devlink *, const struct devlink_trap_policer *, u64 *);\n\tint (*port_new)(struct devlink *, const struct devlink_port_new_attrs *, struct netlink_ext_ack *, struct devlink_port **);\n\tint (*rate_leaf_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_new)(struct devlink_rate *, void **, struct netlink_ext_ack *);\n\tint (*rate_node_del)(struct devlink_rate *, void *, struct netlink_ext_ack *);\n\tint (*rate_leaf_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tint (*rate_node_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tbool (*selftest_check)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n\tenum devlink_selftest_status (*selftest_run)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n};\n\nstruct devlink_param_gset_ctx;\n\nunion devlink_param_value;\n\nstruct devlink_param {\n\tu32 id;\n\tconst char *name;\n\tbool generic;\n\tenum devlink_param_type type;\n\tlong unsigned int supported_cmodes;\n\tint (*get)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*set)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*validate)(struct devlink *, u32, union devlink_param_value, struct netlink_ext_ack *);\n\tint (*get_default)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*reset_default)(struct devlink *, u32, enum devlink_param_cmode, struct netlink_ext_ack *);\n};\n\nunion devlink_param_value {\n\tu8 vu8;\n\tu16 vu16;\n\tu32 vu32;\n\tu64 vu64;\n\tchar vstr[32];\n\tbool vbool;\n};\n\nstruct devlink_param_gset_ctx {\n\tunion devlink_param_value val;\n\tenum devlink_param_cmode cmode;\n\tlong: 32;\n};\n\nstruct devlink_param_item {\n\tstruct list_head list;\n\tconst struct devlink_param *param;\n\tlong: 32;\n\tunion devlink_param_value driverinit_value;\n\tbool driverinit_value_valid;\n\tlong: 32;\n\tunion devlink_param_value driverinit_value_new;\n\tbool driverinit_value_new_valid;\n\tlong: 32;\n\tunion devlink_param_value driverinit_default;\n};\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_port_ops;\n\nstruct ib_device;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct devlink_port_new_attrs {\n\tenum devlink_port_flavour flavour;\n\tunsigned int port_index;\n\tu32 controller;\n\tu32 sfnum;\n\tu16 pfnum;\n\tu8 port_index_valid: 1;\n\tu8 controller_valid: 1;\n\tu8 sfnum_valid: 1;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_port_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tlong: 32;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n\tlong: 32;\n};\n\nstruct devlink_region_ops;\n\nstruct devlink_region {\n\tstruct devlink *devlink;\n\tstruct devlink_port *port;\n\tstruct list_head list;\n\tunion {\n\t\tconst struct devlink_region_ops *ops;\n\t\tconst struct devlink_port_region_ops *port_ops;\n\t};\n\tstruct mutex snapshot_lock;\n\tstruct list_head snapshot_list;\n\tu32 max_snapshots;\n\tu32 cur_snapshots;\n\tlong: 32;\n\tu64 size;\n};\n\nstruct devlink_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\ntypedef void devlink_rel_notify_cb_t(struct devlink *, u32);\n\ntypedef void devlink_rel_cleanup_cb_t(struct devlink *, u32, u32);\n\nstruct devlink_rel {\n\tu32 index;\n\trefcount_t refcount;\n\tu32 devlink_index;\n\tstruct {\n\t\tu32 devlink_index;\n\t\tu32 obj_index;\n\t\tdevlink_rel_notify_cb_t *notify_cb;\n\t\tdevlink_rel_cleanup_cb_t *cleanup_cb;\n\t\tstruct delayed_work notify_work;\n\t} nested_in;\n};\n\nstruct devlink_reload_combination {\n\tenum devlink_reload_action action;\n\tenum devlink_reload_limit limit;\n};\n\nstruct devlink_resource_size_params {\n\tu64 size_min;\n\tu64 size_max;\n\tu64 size_granularity;\n\tenum devlink_resource_unit unit;\n\tlong: 32;\n};\n\ntypedef u64 devlink_resource_occ_get_t(void *);\n\nstruct devlink_resource {\n\tconst char *name;\n\tlong: 32;\n\tu64 id;\n\tu64 size;\n\tu64 size_new;\n\tbool size_valid;\n\tstruct devlink_resource *parent;\n\tstruct devlink_resource_size_params size_params;\n\tstruct list_head list;\n\tstruct list_head resource_list;\n\tdevlink_resource_occ_get_t *occ_get;\n\tvoid *occ_get_priv;\n};\n\nstruct devlink_sb {\n\tstruct list_head list;\n\tunsigned int index;\n\tu32 size;\n\tu16 ingress_pools_count;\n\tu16 egress_pools_count;\n\tu16 ingress_tc_count;\n\tu16 egress_tc_count;\n};\n\nstruct devlink_sb_pool_info {\n\tenum devlink_sb_pool_type pool_type;\n\tu32 size;\n\tenum devlink_sb_threshold_type threshold_type;\n\tu32 cell_size;\n};\n\nstruct devlink_snapshot {\n\tstruct list_head list;\n\tstruct devlink_region *region;\n\tu8 *data;\n\tu32 id;\n};\n\nstruct devlink_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct devlink_trap {\n\tenum devlink_trap_type type;\n\tenum devlink_trap_action init_action;\n\tbool generic;\n\tu16 id;\n\tconst char *name;\n\tu16 init_group_id;\n\tu32 metadata_cap;\n};\n\nstruct devlink_trap_group {\n\tconst char *name;\n\tu16 id;\n\tbool generic;\n\tu32 init_policer_id;\n};\n\nstruct devlink_trap_policer_item;\n\nstruct devlink_trap_group_item {\n\tconst struct devlink_trap_group *group;\n\tstruct devlink_trap_policer_item *policer_item;\n\tstruct list_head list;\n\tstruct devlink_stats *stats;\n};\n\nstruct devlink_trap_item {\n\tconst struct devlink_trap *trap;\n\tstruct devlink_trap_group_item *group_item;\n\tstruct list_head list;\n\tenum devlink_trap_action action;\n\tstruct devlink_stats *stats;\n\tvoid *priv;\n};\n\nstruct flow_action_cookie;\n\nstruct devlink_trap_metadata {\n\tconst char *trap_name;\n\tconst char *trap_group_name;\n\tstruct net_device *input_dev;\n\tnetdevice_tracker dev_tracker;\n\tconst struct flow_action_cookie *fa_cookie;\n\tenum devlink_trap_type trap_type;\n};\n\nstruct devlink_trap_policer {\n\tu32 id;\n\tlong: 32;\n\tu64 init_rate;\n\tu64 init_burst;\n\tu64 max_rate;\n\tu64 min_rate;\n\tu64 max_burst;\n\tu64 min_burst;\n};\n\nstruct devlink_trap_policer_item {\n\tconst struct devlink_trap_policer *policer;\n\tlong: 32;\n\tu64 rate;\n\tu64 burst;\n\tstruct list_head list;\n};\n\nstruct devm_clk_state {\n\tstruct clk *clk;\n\tvoid (*exit)(struct clk *);\n};\n\nstruct of_regulator_match;\n\nstruct devm_of_regulator_matches {\n\tstruct of_regulator_match *matches;\n\tunsigned int num_matches;\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct pt_regs;\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n\tlong: 32;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\nstruct dio {\n\tint flags;\n\tblk_opf_t opf;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tbool is_pinned;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tlong: 32;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tlong: 32;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n\tlong: 32;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tlong: 32;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tlong: 32;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n\tlong: 32;\n\tu64 cookie;\n\tbool initialized;\n\tlong: 32;\n};\n\nstruct wb_domain;\n\nstruct dirty_throttle_control {\n\tstruct wb_domain *dom;\n\tstruct dirty_throttle_control *gdtc;\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n\tlong: 32;\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tlong: 32;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tlong: 32;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tlong: 32;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nstruct dmaengine_result;\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dma_chan;\n\nstruct dmaengine_unmap_data;\n\nstruct dma_descriptor_metadata_ops;\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_resv;\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct sg_table;\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_device;\n\nstruct dma_chan_dev;\n\nstruct dma_chan_percpu;\n\nstruct dma_router;\n\nstruct dma_chan {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan *chan;\n\tlong: 32;\n\tstruct device device;\n\tint dev_id;\n\tbool chan_dma_dev;\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_chan_tbl_ent {\n\tstruct dma_chan *chan;\n};\n\nstruct dma_coherent_mem {\n\tvoid *virt_base;\n\tdma_addr_t device_base;\n\tlong unsigned int pfn_base;\n\tint size;\n\tlong unsigned int *bitmap;\n\tspinlock_t spinlock;\n\tbool use_dev_dma_pfn_offset;\n};\n\nstruct dma_desc {\n\t__le32 des0;\n\t__le32 des1;\n\t__le32 des2;\n\t__le32 des3;\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan *, void *);\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct dma_vec;\n\nstruct dma_interleaved_template;\n\nstruct dma_slave_caps;\n\nstruct dma_slave_config;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan *);\n\tint (*device_router_config)(struct dma_chan *);\n\tvoid (*device_free_chan_resources)(struct dma_chan *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_peripheral_dma_vec)(struct dma_chan *, const struct dma_vec *, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan *, struct dma_interleaved_template *, long unsigned int);\n\tvoid (*device_caps)(struct dma_chan *, struct dma_slave_caps *);\n\tint (*device_config)(struct dma_chan *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan *);\n\tint (*device_resume)(struct dma_chan *);\n\tint (*device_terminate_all)(struct dma_chan *);\n\tvoid (*device_synchronize)(struct dma_chan *);\n\tenum dma_status (*device_tx_status)(struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_edesc {\n\t__le32 des4;\n\t__le32 des5;\n\t__le32 des6;\n\t__le32 des7;\n\tstruct dma_desc basic;\n};\n\nstruct dma_extended_desc {\n\tstruct dma_desc basic;\n\t__le32 des4;\n\t__le32 des5;\n\t__le32 des6;\n\t__le32 des7;\n};\n\nstruct dma_features {\n\tunsigned int mbps_10_100;\n\tunsigned int mbps_1000;\n\tunsigned int half_duplex;\n\tunsigned int hash_filter;\n\tunsigned int multi_addr;\n\tunsigned int pcs;\n\tunsigned int sma_mdio;\n\tunsigned int pmt_remote_wake_up;\n\tunsigned int pmt_magic_frame;\n\tunsigned int rmon;\n\tunsigned int time_stamp;\n\tunsigned int atime_stamp;\n\tunsigned int eee;\n\tunsigned int av;\n\tunsigned int hash_tb_sz;\n\tunsigned int tsoen;\n\tunsigned int tx_coe;\n\tunsigned int rx_coe;\n\tunsigned int rx_coe_type1;\n\tunsigned int rx_coe_type2;\n\tunsigned int rxfifo_over_2048;\n\tunsigned int number_rx_channel;\n\tunsigned int number_tx_channel;\n\tunsigned int number_rx_queues;\n\tunsigned int number_tx_queues;\n\tunsigned int pps_out_num;\n\tunsigned int numtc;\n\tunsigned int dcben;\n\tunsigned int advthword;\n\tunsigned int ptoen;\n\tunsigned int osten;\n\tunsigned int pfcen;\n\tunsigned int enh_desc;\n\tunsigned int tx_fifo_size;\n\tunsigned int rx_fifo_size;\n\tunsigned int asp;\n\tunsigned int frpsel;\n\tunsigned int frpbs;\n\tunsigned int frpes;\n\tunsigned int addr64;\n\tunsigned int host_dma_width;\n\tunsigned int rssen;\n\tunsigned int vlhash;\n\tunsigned int sphen;\n\tunsigned int vlins;\n\tunsigned int dvlan;\n\tunsigned int l3l4fnum;\n\tunsigned int arpoffsel;\n\tunsigned int pou_ost_en;\n\tunsigned int ttsfd;\n\tunsigned int cbtisel;\n\tunsigned int frppipe_num;\n\tunsigned int nrvf_num;\n\tunsigned int estwid;\n\tunsigned int estdep;\n\tunsigned int estsel;\n\tunsigned int fpesel;\n\tunsigned int tbssel;\n\tunsigned int tbs_ch_num;\n\tunsigned int sgfsel;\n\tunsigned int aux_snapshot_n;\n\tunsigned int tssrc;\n\tunsigned int edma;\n\tunsigned int ediffc;\n\tunsigned int vxn;\n\tunsigned int dbgmem;\n\tunsigned int pcsel;\n\tu8 actphyif;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n\tlong: 32;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tlong: 32;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_vec {\n\tdma_addr_t addr;\n\tsize_t len;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmaengine_desc_callback {\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\nstruct dmaengine_unmap_data {\n\tu8 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dmaengine_unmap_pool {\n\tstruct kmem_cache *cache;\n\tconst char *name;\n\tmempool_t *pool;\n\tsize_t size;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tlong: 32;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tlong: 32;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct pci_driver;\n\nstruct pci_dev;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct dsa_switch;\n\nstruct dsa_8021q_context {\n\tstruct dsa_switch *ds;\n\tstruct list_head vlans;\n\t__be16 proto;\n};\n\nstruct dsa_bridge {\n\tstruct net_device *dev;\n\tunsigned int num;\n\tbool tx_fwd_offload;\n\trefcount_t refcount;\n};\n\nstruct dsa_chip_data {\n\tstruct device *host_dev;\n\tint sw_addr;\n\tstruct device *netdev[12];\n\tint eeprom_len;\n\tstruct device_node *of_node;\n\tchar *port_names[12];\n\tstruct device_node *port_dn[12];\n\ts8 rtable[4];\n};\n\nstruct dsa_lag {\n\tstruct net_device *dev;\n\tunsigned int id;\n\tstruct mutex fdb_lock;\n\tstruct list_head fdbs;\n\trefcount_t refcount;\n};\n\nstruct dsa_port;\n\nstruct dsa_db {\n\tenum dsa_db_type type;\n\tunion {\n\t\tconst struct dsa_port *dp;\n\t\tstruct dsa_lag lag;\n\t\tstruct dsa_bridge bridge;\n\t};\n};\n\nstruct dsa_device_ops {\n\tstruct sk_buff * (*xmit)(struct sk_buff *, struct net_device *);\n\tstruct sk_buff * (*rcv)(struct sk_buff *, struct net_device *);\n\tvoid (*flow_dissect)(const struct sk_buff *, __be16 *, int *);\n\tint (*connect)(struct dsa_switch *);\n\tvoid (*disconnect)(struct dsa_switch *);\n\tunsigned int needed_headroom;\n\tunsigned int needed_tailroom;\n\tconst char *name;\n\tenum dsa_tag_protocol proto;\n\tbool promisc_on_conduit;\n};\n\nstruct dsa_devlink_priv {\n\tstruct dsa_switch *ds;\n};\n\nstruct dsa_host_vlan_rx_filtering_ctx {\n\tstruct net_device *dev;\n\tconst unsigned char *addr;\n\tenum dsa_standalone_event event;\n};\n\nstruct dsa_hw_port {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tint old_mtu;\n};\n\nstruct dsa_link {\n\tstruct dsa_port *dp;\n\tstruct dsa_port *link_dp;\n\tstruct list_head list;\n};\n\nstruct dsa_mac_addr {\n\tunsigned char addr[6];\n\tu16 vid;\n\trefcount_t refcount;\n\tstruct list_head list;\n\tstruct dsa_db db;\n};\n\nstruct dsa_mall_mirror_tc_entry {\n\tu8 to_local_port;\n\tbool ingress;\n};\n\nstruct flow_action_police {\n\tu32 burst;\n\tlong: 32;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n\tlong: 32;\n};\n\nstruct dsa_mall_tc_entry {\n\tstruct list_head list;\n\tlong unsigned int cookie;\n\tenum dsa_port_mall_action_type type;\n\tunion {\n\t\tstruct dsa_mall_mirror_tc_entry mirror;\n\t\tstruct flow_action_police policer;\n\t};\n};\n\nstruct dsa_notifier_ageing_time_info {\n\tunsigned int ageing_time;\n};\n\nstruct dsa_notifier_bridge_info {\n\tconst struct dsa_port *dp;\n\tstruct dsa_bridge bridge;\n\tbool tx_fwd_offload;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct dsa_notifier_conduit_state_info {\n\tconst struct net_device *conduit;\n\tbool operational;\n};\n\nstruct dsa_notifier_fdb_info {\n\tconst struct dsa_port *dp;\n\tconst unsigned char *addr;\n\tu16 vid;\n\tstruct dsa_db db;\n};\n\nstruct dsa_notifier_lag_fdb_info {\n\tstruct dsa_lag *lag;\n\tconst unsigned char *addr;\n\tu16 vid;\n\tstruct dsa_db db;\n};\n\nstruct netdev_lag_upper_info;\n\nstruct dsa_notifier_lag_info {\n\tconst struct dsa_port *dp;\n\tstruct dsa_lag lag;\n\tstruct netdev_lag_upper_info *info;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct switchdev_obj_port_mdb;\n\nstruct dsa_notifier_mdb_info {\n\tconst struct dsa_port *dp;\n\tconst struct switchdev_obj_port_mdb *mdb;\n\tstruct dsa_db db;\n};\n\nstruct dsa_notifier_mtu_info {\n\tconst struct dsa_port *dp;\n\tint mtu;\n};\n\nstruct dsa_notifier_tag_8021q_vlan_info {\n\tconst struct dsa_port *dp;\n\tu16 vid;\n};\n\nstruct dsa_notifier_tag_proto_info {\n\tconst struct dsa_device_ops *tag_ops;\n};\n\nstruct switchdev_obj_port_vlan;\n\nstruct dsa_notifier_vlan_info {\n\tconst struct dsa_port *dp;\n\tconst struct switchdev_obj_port_vlan *vlan;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct dsa_platform_data {\n\tstruct device *netdev;\n\tstruct net_device *of_netdev;\n\tint nr_chips;\n\tstruct dsa_chip_data *chip;\n};\n\nstruct phylink_link_state;\n\nstruct phylink_config {\n\tstruct device *dev;\n\tenum phylink_op_type type;\n\tbool poll_fixed_state;\n\tbool mac_managed_pm;\n\tbool mac_requires_rxc;\n\tbool default_an_inband;\n\tbool eee_rx_clk_stop_enable;\n\tvoid (*get_fixed_state)(struct phylink_config *, struct phylink_link_state *);\n\tlong unsigned int supported_interfaces[2];\n\tlong unsigned int lpi_interfaces[2];\n\tlong unsigned int mac_capabilities;\n\tlong unsigned int lpi_capabilities;\n\tu32 lpi_timer_default;\n\tbool eee_enabled_default;\n\tbool wol_phy_legacy;\n\tbool wol_phy_speed_ctrl;\n\tu32 wol_mac_support;\n};\n\nstruct dsa_switch_tree;\n\nstruct phylink;\n\nstruct ethtool_ops;\n\nstruct dsa_port {\n\tunion {\n\t\tstruct net_device *conduit;\n\t\tstruct net_device *user;\n\t};\n\tconst struct dsa_device_ops *tag_ops;\n\tstruct dsa_switch_tree *dst;\n\tstruct sk_buff * (*rcv)(struct sk_buff *, struct net_device *);\n\tstruct dsa_switch *ds;\n\tunsigned int index;\n\tenum {\n\t\tDSA_PORT_TYPE_UNUSED = 0,\n\t\tDSA_PORT_TYPE_CPU = 1,\n\t\tDSA_PORT_TYPE_DSA = 2,\n\t\tDSA_PORT_TYPE_USER = 3,\n\t} type;\n\tconst char *name;\n\tstruct dsa_port *cpu_dp;\n\tu8 mac[6];\n\tu8 stp_state;\n\tu8 vlan_filtering: 1;\n\tu8 learning: 1;\n\tu8 lag_tx_enabled: 1;\n\tu8 conduit_admin_up: 1;\n\tu8 conduit_oper_up: 1;\n\tu8 cpu_port_in_lag: 1;\n\tu8 setup: 1;\n\tstruct device_node *dn;\n\tunsigned int ageing_time;\n\tstruct dsa_bridge *bridge;\n\tstruct devlink_port devlink_port;\n\tstruct phylink *pl;\n\tstruct phylink_config pl_config;\n\tnetdevice_tracker conduit_tracker;\n\tstruct dsa_lag *lag;\n\tstruct net_device *hsr_dev;\n\tstruct list_head list;\n\tconst struct ethtool_ops *orig_ethtool_ops;\n\tstruct mutex addr_lists_lock;\n\tstruct list_head fdbs;\n\tstruct list_head mdbs;\n\tstruct mutex vlans_lock;\n\tunion {\n\t\tstruct list_head vlans;\n\t\tstruct list_head user_vlans;\n\t};\n};\n\nstruct dsa_standalone_event_work {\n\tstruct work_struct work;\n\tstruct net_device *dev;\n\tenum dsa_standalone_event event;\n\tunsigned char addr[6];\n\tu16 vid;\n};\n\nstruct kernel_hwtstamp_config;\n\nstruct dsa_stubs {\n\tint (*conduit_hwtstamp_validate)(struct net_device *, const struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct dsa_switch_ops;\n\nstruct phylink_mac_ops;\n\nstruct mii_bus;\n\nstruct dsa_switch {\n\tstruct device *dev;\n\tstruct dsa_switch_tree *dst;\n\tunsigned int index;\n\tu32 setup: 1;\n\tu32 vlan_filtering_is_global: 1;\n\tu32 needs_standalone_vlan_filtering: 1;\n\tu32 configure_vlan_while_not_filtering: 1;\n\tu32 untag_bridge_pvid: 1;\n\tu32 untag_vlan_aware_bridge_pvid: 1;\n\tu32 assisted_learning_on_cpu_port: 1;\n\tu32 vlan_filtering: 1;\n\tu32 mtu_enforcement_ingress: 1;\n\tu32 fdb_isolation: 1;\n\tu32 dscp_prio_mapping_is_global: 1;\n\tstruct notifier_block nb;\n\tvoid *priv;\n\tvoid *tagger_data;\n\tstruct dsa_chip_data *cd;\n\tconst struct dsa_switch_ops *ops;\n\tconst struct phylink_mac_ops *phylink_mac_ops;\n\tu32 phys_mii_mask;\n\tstruct mii_bus *user_mii_bus;\n\tunsigned int ageing_time_min;\n\tunsigned int ageing_time_max;\n\tstruct dsa_8021q_context *tag_8021q_ctx;\n\tstruct devlink *devlink;\n\tunsigned int num_tx_queues;\n\tunsigned int num_lag_ids;\n\tunsigned int max_num_bridges;\n\tunsigned int num_ports;\n};\n\ntypedef int dsa_fdb_dump_cb_t(const unsigned char *, u16, bool, void *);\n\nstruct ethtool_eth_phy_stats;\n\nstruct ethtool_eth_mac_stats;\n\nstruct ethtool_eth_ctrl_stats;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ts_stats;\n\nstruct rtnl_link_stats64;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_test;\n\nstruct ethtool_wolinfo;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_mm_state;\n\nstruct ethtool_mm_cfg;\n\nstruct ethtool_mm_stats;\n\nstruct phy_device;\n\nstruct ethtool_keee;\n\nstruct ethtool_eeprom;\n\nstruct ethtool_regs;\n\nstruct netdev_notifier_changeupper_info;\n\nstruct switchdev_mst_state;\n\nstruct switchdev_brport_flags;\n\nstruct switchdev_vlan_msti;\n\nstruct ethtool_rxnfc;\n\nstruct flow_cls_offload;\n\nstruct switchdev_obj_mrp;\n\nstruct switchdev_obj_ring_role_mrp;\n\nstruct dsa_switch_ops {\n\tenum dsa_tag_protocol (*get_tag_protocol)(struct dsa_switch *, int, enum dsa_tag_protocol);\n\tint (*change_tag_protocol)(struct dsa_switch *, enum dsa_tag_protocol);\n\tint (*connect_tag_protocol)(struct dsa_switch *, enum dsa_tag_protocol);\n\tint (*port_change_conduit)(struct dsa_switch *, int, struct net_device *, struct netlink_ext_ack *);\n\tint (*setup)(struct dsa_switch *);\n\tvoid (*teardown)(struct dsa_switch *);\n\tint (*port_setup)(struct dsa_switch *, int);\n\tvoid (*port_teardown)(struct dsa_switch *, int);\n\tu32 (*get_phy_flags)(struct dsa_switch *, int);\n\tint (*phy_read)(struct dsa_switch *, int, int);\n\tint (*phy_write)(struct dsa_switch *, int, int, u16);\n\tvoid (*phylink_get_caps)(struct dsa_switch *, int, struct phylink_config *);\n\tvoid (*phylink_fixed_state)(struct dsa_switch *, int, struct phylink_link_state *);\n\tvoid (*get_strings)(struct dsa_switch *, int, u32, uint8_t *);\n\tvoid (*get_ethtool_stats)(struct dsa_switch *, int, uint64_t *);\n\tint (*get_sset_count)(struct dsa_switch *, int, int);\n\tvoid (*get_ethtool_phy_stats)(struct dsa_switch *, int, uint64_t *);\n\tvoid (*get_eth_phy_stats)(struct dsa_switch *, int, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct dsa_switch *, int, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct dsa_switch *, int, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct dsa_switch *, int, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tvoid (*get_ts_stats)(struct dsa_switch *, int, struct ethtool_ts_stats *);\n\tvoid (*get_stats64)(struct dsa_switch *, int, struct rtnl_link_stats64 *);\n\tvoid (*get_pause_stats)(struct dsa_switch *, int, struct ethtool_pause_stats *);\n\tvoid (*self_test)(struct dsa_switch *, int, struct ethtool_test *, u64 *);\n\tvoid (*get_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *);\n\tint (*get_ts_info)(struct dsa_switch *, int, struct kernel_ethtool_ts_info *);\n\tint (*get_mm)(struct dsa_switch *, int, struct ethtool_mm_state *);\n\tint (*set_mm)(struct dsa_switch *, int, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct dsa_switch *, int, struct ethtool_mm_stats *);\n\tint (*port_get_default_prio)(struct dsa_switch *, int);\n\tint (*port_set_default_prio)(struct dsa_switch *, int, u8);\n\tint (*port_get_dscp_prio)(struct dsa_switch *, int, u8);\n\tint (*port_add_dscp_prio)(struct dsa_switch *, int, u8, u8);\n\tint (*port_del_dscp_prio)(struct dsa_switch *, int, u8, u8);\n\tint (*port_set_apptrust)(struct dsa_switch *, int, const u8 *, int);\n\tint (*port_get_apptrust)(struct dsa_switch *, int, u8 *, int *);\n\tint (*suspend)(struct dsa_switch *);\n\tint (*resume)(struct dsa_switch *);\n\tint (*port_enable)(struct dsa_switch *, int, struct phy_device *);\n\tvoid (*port_disable)(struct dsa_switch *, int);\n\tint (*port_set_mac_address)(struct dsa_switch *, int, const unsigned char *);\n\tstruct dsa_port * (*preferred_default_local_cpu_port)(struct dsa_switch *);\n\tbool (*support_eee)(struct dsa_switch *, int);\n\tint (*set_mac_eee)(struct dsa_switch *, int, struct ethtool_keee *);\n\tint (*get_eeprom_len)(struct dsa_switch *);\n\tint (*get_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *);\n\tint (*get_regs_len)(struct dsa_switch *, int);\n\tvoid (*get_regs)(struct dsa_switch *, int, struct ethtool_regs *, void *);\n\tint (*port_prechangeupper)(struct dsa_switch *, int, struct netdev_notifier_changeupper_info *);\n\tint (*set_ageing_time)(struct dsa_switch *, unsigned int);\n\tint (*port_bridge_join)(struct dsa_switch *, int, struct dsa_bridge, bool *, struct netlink_ext_ack *);\n\tvoid (*port_bridge_leave)(struct dsa_switch *, int, struct dsa_bridge);\n\tvoid (*port_stp_state_set)(struct dsa_switch *, int, u8);\n\tint (*port_mst_state_set)(struct dsa_switch *, int, const struct switchdev_mst_state *);\n\tvoid (*port_fast_age)(struct dsa_switch *, int);\n\tint (*port_vlan_fast_age)(struct dsa_switch *, int, u16);\n\tint (*port_pre_bridge_flags)(struct dsa_switch *, int, struct switchdev_brport_flags, struct netlink_ext_ack *);\n\tint (*port_bridge_flags)(struct dsa_switch *, int, struct switchdev_brport_flags, struct netlink_ext_ack *);\n\tvoid (*port_set_host_flood)(struct dsa_switch *, int, bool, bool);\n\tint (*port_vlan_filtering)(struct dsa_switch *, int, bool, struct netlink_ext_ack *);\n\tint (*port_vlan_add)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *, struct netlink_ext_ack *);\n\tint (*port_vlan_del)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *);\n\tint (*vlan_msti_set)(struct dsa_switch *, struct dsa_bridge, const struct switchdev_vlan_msti *);\n\tint (*port_fdb_add)(struct dsa_switch *, int, const unsigned char *, u16, struct dsa_db);\n\tint (*port_fdb_del)(struct dsa_switch *, int, const unsigned char *, u16, struct dsa_db);\n\tint (*port_fdb_dump)(struct dsa_switch *, int, dsa_fdb_dump_cb_t *, void *);\n\tint (*lag_fdb_add)(struct dsa_switch *, struct dsa_lag, const unsigned char *, u16, struct dsa_db);\n\tint (*lag_fdb_del)(struct dsa_switch *, struct dsa_lag, const unsigned char *, u16, struct dsa_db);\n\tint (*port_mdb_add)(struct dsa_switch *, int, const struct switchdev_obj_port_mdb *, struct dsa_db);\n\tint (*port_mdb_del)(struct dsa_switch *, int, const struct switchdev_obj_port_mdb *, struct dsa_db);\n\tint (*get_rxnfc)(struct dsa_switch *, int, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct dsa_switch *, int, struct ethtool_rxnfc *);\n\tint (*cls_flower_add)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*cls_flower_del)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*cls_flower_stats)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*port_mirror_add)(struct dsa_switch *, int, struct dsa_mall_mirror_tc_entry *, bool, struct netlink_ext_ack *);\n\tvoid (*port_mirror_del)(struct dsa_switch *, int, struct dsa_mall_mirror_tc_entry *);\n\tint (*port_policer_add)(struct dsa_switch *, int, const struct flow_action_police *);\n\tvoid (*port_policer_del)(struct dsa_switch *, int);\n\tint (*port_setup_tc)(struct dsa_switch *, int, enum tc_setup_type, void *);\n\tint (*crosschip_bridge_join)(struct dsa_switch *, int, int, int, struct dsa_bridge, struct netlink_ext_ack *);\n\tvoid (*crosschip_bridge_leave)(struct dsa_switch *, int, int, int, struct dsa_bridge);\n\tint (*crosschip_lag_change)(struct dsa_switch *, int, int);\n\tint (*crosschip_lag_join)(struct dsa_switch *, int, int, struct dsa_lag, struct netdev_lag_upper_info *, struct netlink_ext_ack *);\n\tint (*crosschip_lag_leave)(struct dsa_switch *, int, int, struct dsa_lag);\n\tint (*port_hwtstamp_get)(struct dsa_switch *, int, struct kernel_hwtstamp_config *);\n\tint (*port_hwtstamp_set)(struct dsa_switch *, int, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*port_txtstamp)(struct dsa_switch *, int, struct sk_buff *);\n\tbool (*port_rxtstamp)(struct dsa_switch *, int, struct sk_buff *, unsigned int);\n\tint (*devlink_param_get)(struct dsa_switch *, u32, struct devlink_param_gset_ctx *);\n\tint (*devlink_param_set)(struct dsa_switch *, u32, struct devlink_param_gset_ctx *);\n\tint (*devlink_info_get)(struct dsa_switch *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*devlink_sb_pool_get)(struct dsa_switch *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*devlink_sb_pool_set)(struct dsa_switch *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*devlink_sb_port_pool_get)(struct dsa_switch *, int, unsigned int, u16, u32 *);\n\tint (*devlink_sb_port_pool_set)(struct dsa_switch *, int, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*devlink_sb_tc_pool_bind_get)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*devlink_sb_tc_pool_bind_set)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*devlink_sb_occ_snapshot)(struct dsa_switch *, unsigned int);\n\tint (*devlink_sb_occ_max_clear)(struct dsa_switch *, unsigned int);\n\tint (*devlink_sb_occ_port_pool_get)(struct dsa_switch *, int, unsigned int, u16, u32 *, u32 *);\n\tint (*devlink_sb_occ_tc_port_bind_get)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*port_change_mtu)(struct dsa_switch *, int, int);\n\tint (*port_max_mtu)(struct dsa_switch *, int);\n\tint (*port_lag_change)(struct dsa_switch *, int);\n\tint (*port_lag_join)(struct dsa_switch *, int, struct dsa_lag, struct netdev_lag_upper_info *, struct netlink_ext_ack *);\n\tint (*port_lag_leave)(struct dsa_switch *, int, struct dsa_lag);\n\tint (*port_hsr_join)(struct dsa_switch *, int, struct net_device *, struct netlink_ext_ack *);\n\tint (*port_hsr_leave)(struct dsa_switch *, int, struct net_device *);\n\tint (*port_mrp_add)(struct dsa_switch *, int, const struct switchdev_obj_mrp *);\n\tint (*port_mrp_del)(struct dsa_switch *, int, const struct switchdev_obj_mrp *);\n\tint (*port_mrp_add_ring_role)(struct dsa_switch *, int, const struct switchdev_obj_ring_role_mrp *);\n\tint (*port_mrp_del_ring_role)(struct dsa_switch *, int, const struct switchdev_obj_ring_role_mrp *);\n\tint (*tag_8021q_vlan_add)(struct dsa_switch *, int, u16, u16);\n\tint (*tag_8021q_vlan_del)(struct dsa_switch *, int, u16);\n\tvoid (*conduit_state_change)(struct dsa_switch *, const struct net_device *, bool);\n};\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct dsa_switch_tree {\n\tstruct list_head list;\n\tstruct list_head ports;\n\tstruct raw_notifier_head nh;\n\tunsigned int index;\n\tstruct kref refcount;\n\tstruct dsa_lag **lags;\n\tconst struct dsa_device_ops *tag_ops;\n\tenum dsa_tag_protocol default_proto;\n\tbool setup;\n\tstruct dsa_platform_data *pd;\n\tstruct list_head rtable;\n\tunsigned int lags_len;\n\tunsigned int last_switch;\n};\n\nstruct dsa_switchdev_event_work {\n\tstruct net_device *dev;\n\tstruct net_device *orig_dev;\n\tstruct work_struct work;\n\tlong unsigned int event;\n\tunsigned char addr[6];\n\tu16 vid;\n\tbool host_addr;\n};\n\nstruct dsa_tag_8021q_vlan {\n\tstruct list_head list;\n\tint port;\n\tu16 vid;\n\trefcount_t refcount;\n};\n\nstruct dsa_tag_driver {\n\tconst struct dsa_device_ops *ops;\n\tstruct list_head list;\n\tstruct module *owner;\n};\n\nstruct netlink_callback;\n\nstruct dsa_user_dump_ctx {\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tint idx;\n};\n\nstruct gro_cell;\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct dsa_user_priv {\n\tstruct sk_buff * (*xmit)(struct sk_buff *, struct net_device *);\n\tstruct gro_cells gcells;\n\tstruct dsa_port *dp;\n\tstruct list_head mall_tc_list;\n};\n\nstruct dsa_vlan {\n\tu16 vid;\n\trefcount_t refcount;\n\tstruct list_head list;\n};\n\nstruct dsp_format {\n\tunsigned int func: 6;\n\tunsigned int op: 5;\n\tunsigned int rd: 5;\n\tunsigned int index: 5;\n\tunsigned int base: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct dst_entry;\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tlocal_lock_t bh_lock;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct dst_ops;\n\nstruct lwtunnel_state;\n\nstruct uncached_list;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tvoid *__pad1;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tstruct lwtunnel_state *lwtstate;\n\trcuref_t __rcuref;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct uart_8250_port;\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_tx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan *rxchan;\n\tstruct dma_chan *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct dw8250_port_data {\n\tint line;\n\tstruct uart_8250_dma dma;\n\tu32 cpr_value;\n\tu8 dlf_size;\n\tbool hw_rs485_support;\n};\n\nstruct dw8250_platform_data;\n\nstruct dw8250_data {\n\tstruct dw8250_port_data data;\n\tconst struct dw8250_platform_data *pdata;\n\tu32 msr_mask_on;\n\tu32 msr_mask_off;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_notifier;\n\tstruct work_struct clk_work;\n\tstruct reset_control *rst;\n\tunsigned int skip_autocfg: 1;\n\tunsigned int uart_16550_compatible: 1;\n};\n\nstruct dw8250_platform_data {\n\tu8 usr_reg;\n\tu32 cpr_value;\n\tunsigned int quirks;\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_gpio;\n};\n\nstruct regmap;\n\nstruct i2c_client;\n\nstruct i2c_msg;\n\nstruct dw_i2c_dev {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct regmap *sysmap;\n\tvoid *base;\n\tvoid *ext;\n\tstruct completion cmd_complete;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct reset_control *rst;\n\tstruct i2c_client *slave;\n\tu32 (*get_clk_rate_khz)(struct dw_i2c_dev *);\n\tint cmd_err;\n\tstruct i2c_msg *msgs;\n\tint msgs_num;\n\tint msg_write_idx;\n\tu32 tx_buf_len;\n\tu8 *tx_buf;\n\tint msg_read_idx;\n\tu32 rx_buf_len;\n\tu8 *rx_buf;\n\tint msg_err;\n\tunsigned int status;\n\tunsigned int abort_source;\n\tunsigned int sw_mask;\n\tint irq;\n\tu32 flags;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tu32 functionality;\n\tu32 master_cfg;\n\tu32 slave_cfg;\n\tunsigned int tx_fifo_depth;\n\tunsigned int rx_fifo_depth;\n\tint rx_outstanding;\n\tstruct i2c_timings timings;\n\tu32 sda_hold_time;\n\tu16 ss_hcnt;\n\tu16 ss_lcnt;\n\tu16 fs_hcnt;\n\tu16 fs_lcnt;\n\tu16 fp_hcnt;\n\tu16 fp_lcnt;\n\tu16 hs_hcnt;\n\tu16 hs_lcnt;\n\tint (*acquire_lock)(void);\n\tvoid (*release_lock)(void);\n\tint semaphore_idx;\n\tbool shared_with_punit;\n\tint (*set_sda_hold_time)(struct dw_i2c_dev *);\n\tint mode;\n\tstruct i2c_bus_recovery_info rinfo;\n\tu32 bus_capacitance_pF;\n\tbool clk_freq_optimized;\n\tbool emptyfifo_hold_master;\n};\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct mmc_data;\n\nstruct uhs2_command;\n\nstruct mmc_command {\n\tu32 opcode;\n\tu32 arg;\n\tu32 resp[4];\n\tunsigned int flags;\n\tunsigned int retries;\n\tint error;\n\tunsigned int busy_timeout;\n\tstruct mmc_data *data;\n\tstruct mmc_request *mrq;\n\tstruct uhs2_command *uhs2_cmd;\n\tbool has_ext_addr;\n\tu8 ext_addr;\n};\n\nstruct dw_mci_dma_ops;\n\nstruct dw_mci_dma_slave;\n\nstruct dw_mci_board;\n\nstruct dw_mci_drv_data;\n\nstruct dw_mci_slot;\n\nstruct dw_mci {\n\tspinlock_t lock;\n\tspinlock_t irq_lock;\n\tvoid *regs;\n\tvoid *fifo_reg;\n\tu32 data_addr_override;\n\tbool wm_aligned;\n\tstruct scatterlist *sg;\n\tstruct sg_mapping_iter sg_miter;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command stop_abort;\n\tunsigned int prev_blksz;\n\tunsigned char timing;\n\tint use_dma;\n\tint using_dma;\n\tint dma_64bit_address;\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tconst struct dw_mci_dma_ops *dma_ops;\n\tunsigned int ring_size;\n\tstruct dw_mci_dma_slave *dms;\n\tresource_size_t phy_regs;\n\tu32 cmd_status;\n\tu32 data_status;\n\tu32 stop_cmdr;\n\tu32 dir_status;\n\tstruct work_struct bh_work;\n\tlong unsigned int pending_events;\n\tlong unsigned int completed_events;\n\tenum dw_mci_state state;\n\tstruct list_head queue;\n\tu32 bus_hz;\n\tu32 current_speed;\n\tu32 minimum_speed;\n\tu32 fifoth_val;\n\tu16 verid;\n\tstruct device *dev;\n\tstruct dw_mci_board *pdata;\n\tconst struct dw_mci_drv_data *drv_data;\n\tvoid *priv;\n\tstruct clk *biu_clk;\n\tstruct clk *ciu_clk;\n\tstruct dw_mci_slot *slot;\n\tint fifo_depth;\n\tint data_shift;\n\tu8 part_buf_start;\n\tu8 part_buf_count;\n\tunion {\n\t\tu16 part_buf16;\n\t\tu32 part_buf32;\n\t\tu64 part_buf;\n\t};\n\tvoid (*push_data)(struct dw_mci *, void *, int);\n\tvoid (*pull_data)(struct dw_mci *, void *, int);\n\tu32 quirks;\n\tbool vqmmc_enabled;\n\tlong unsigned int irq_flags;\n\tint irq;\n\tint sdio_id0;\n\tstruct timer_list cmd11_timer;\n\tstruct timer_list cto_timer;\n\tstruct timer_list dto_timer;\n};\n\nstruct dma_pdata;\n\nstruct dw_mci_board {\n\tunsigned int bus_hz;\n\tu32 caps;\n\tu32 caps2;\n\tu32 pm_caps;\n\tunsigned int fifo_depth;\n\tu32 detect_delay_ms;\n\tstruct reset_control *rstc;\n\tstruct dw_mci_dma_ops *dma_ops;\n\tstruct dma_pdata *data;\n};\n\nstruct dw_mci_dma_ops {\n\tint (*init)(struct dw_mci *);\n\tint (*start)(struct dw_mci *, unsigned int);\n\tvoid (*complete)(void *);\n\tvoid (*stop)(struct dw_mci *);\n\tvoid (*cleanup)(struct dw_mci *);\n\tvoid (*exit)(struct dw_mci *);\n};\n\nstruct dw_mci_dma_slave {\n\tstruct dma_chan *ch;\n\tenum dma_transfer_direction direction;\n};\n\nstruct mmc_ios;\n\nstruct dw_mci_drv_data {\n\tlong unsigned int *caps;\n\tu32 num_caps;\n\tu32 common_caps;\n\tint (*init)(struct dw_mci *);\n\tvoid (*set_ios)(struct dw_mci *, struct mmc_ios *);\n\tint (*parse_dt)(struct dw_mci *);\n\tint (*execute_tuning)(struct dw_mci_slot *, u32);\n\tint (*prepare_hs400_tuning)(struct dw_mci *, struct mmc_ios *);\n\tint (*switch_voltage)(struct mmc_host *, struct mmc_ios *);\n\tvoid (*set_data_timeout)(struct dw_mci *, unsigned int);\n\tu32 (*get_drto_clks)(struct dw_mci *);\n\tvoid (*hw_reset)(struct dw_mci *);\n};\n\nstruct dw_mci_slot {\n\tstruct mmc_host *mmc;\n\tstruct dw_mci *host;\n\tu32 ctype;\n\tstruct mmc_request *mrq;\n\tstruct list_head queue_node;\n\tunsigned int clock;\n\tunsigned int __clk_old;\n\tlong unsigned int flags;\n\tint id;\n\tint sdio_id;\n};\n\nstruct spi_mem;\n\nstruct spi_mem_op;\n\nstruct spi_mem_dirmap_desc;\n\nstruct spi_controller_mem_ops {\n\tint (*adjust_op_size)(struct spi_mem *, struct spi_mem_op *);\n\tbool (*supports_op)(struct spi_mem *, const struct spi_mem_op *);\n\tint (*exec_op)(struct spi_mem *, const struct spi_mem_op *);\n\tconst char * (*get_name)(struct spi_mem *);\n\tint (*dirmap_create)(struct spi_mem_dirmap_desc *);\n\tvoid (*dirmap_destroy)(struct spi_mem_dirmap_desc *);\n\tssize_t (*dirmap_read)(struct spi_mem_dirmap_desc *, u64, size_t, void *);\n\tssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *, u64, size_t, const void *);\n\tint (*poll_status)(struct spi_mem *, const struct spi_mem_op *, u16, u16, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct spi_controller;\n\nstruct spi_device;\n\nstruct dw_spi_dma_ops;\n\nstruct dw_spi {\n\tstruct spi_controller *ctlr;\n\tu32 ip;\n\tu32 ver;\n\tu32 caps;\n\tvoid *regs;\n\tlong unsigned int paddr;\n\tint irq;\n\tu32 fifo_len;\n\tunsigned int dfs_offset;\n\tu32 max_mem_freq;\n\tu32 max_freq;\n\tu32 reg_io_width;\n\tu32 num_cs;\n\tu16 bus_num;\n\tvoid (*set_cs)(struct spi_device *, bool);\n\tvoid *tx;\n\tunsigned int tx_len;\n\tvoid *rx;\n\tunsigned int rx_len;\n\tu8 buf[266];\n\tint dma_mapped;\n\tu8 n_bytes;\n\tirqreturn_t (*transfer_handler)(struct dw_spi *);\n\tu32 current_freq;\n\tu32 cur_rx_sample_dly;\n\tu32 def_rx_sample_dly_ns;\n\tstruct spi_controller_mem_ops mem_ops;\n\tstruct dma_chan *txchan;\n\tu32 txburst;\n\tstruct dma_chan *rxchan;\n\tu32 rxburst;\n\tu32 dma_sg_burst;\n\tu32 dma_addr_widths;\n\tlong unsigned int dma_chan_busy;\n\tdma_addr_t dma_addr;\n\tconst struct dw_spi_dma_ops *dma_ops;\n\tstruct completion dma_completion;\n\tstruct dentry *debugfs;\n\tstruct debugfs_regset32 regset;\n};\n\nstruct dw_spi_cfg {\n\tu8 tmode;\n\tu8 dfs;\n\tu32 ndf;\n\tu32 freq;\n};\n\nstruct dw_spi_chip_data {\n\tu32 cr0;\n\tu32 rx_sample_dly;\n};\n\nstruct spi_transfer;\n\nstruct dw_spi_dma_ops {\n\tint (*dma_init)(struct device *, struct dw_spi *);\n\tvoid (*dma_exit)(struct dw_spi *);\n\tint (*dma_setup)(struct dw_spi *, struct spi_transfer *);\n\tbool (*can_dma)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tint (*dma_transfer)(struct dw_spi *, struct spi_transfer *);\n\tvoid (*dma_stop)(struct dw_spi *);\n};\n\nstruct dw_spi_mmio {\n\tstruct dw_spi dws;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tvoid *priv;\n\tstruct reset_control *rstc;\n};\n\nstruct dw_spi_mscc {\n\tstruct regmap *syscon;\n\tvoid *spi_mst;\n};\n\nstruct dw_xpcs_info {\n\tu32 pcs;\n\tu32 pma;\n};\n\nstruct phylink_pcs_ops;\n\nstruct phylink_pcs {\n\tlong unsigned int supported_interfaces[2];\n\tconst struct phylink_pcs_ops *ops;\n\tstruct phylink *phylink;\n\tbool poll;\n\tbool rxc_always_on;\n};\n\nstruct dw_xpcs_desc;\n\nstruct mdio_device;\n\nstruct dw_xpcs {\n\tstruct dw_xpcs_info info;\n\tconst struct dw_xpcs_desc *desc;\n\tstruct mdio_device *mdiodev;\n\tstruct clk_bulk_data clks[2];\n\tstruct phylink_pcs pcs;\n\tphy_interface_t interface;\n\tbool need_reset;\n\tu8 eee_mult_fact;\n};\n\nstruct dw_xpcs_compat {\n\tphy_interface_t interface;\n\tconst int *supported;\n\tint an_mode;\n\tint (*pma_config)(struct dw_xpcs *);\n};\n\nstruct dw_xpcs_desc {\n\tu32 id;\n\tu32 mask;\n\tconst struct dw_xpcs_compat *compat;\n};\n\nstruct platform_device;\n\nstruct dw_xpcs_plat {\n\tstruct platform_device *pdev;\n\tstruct mii_bus *bus;\n\tbool reg_indir;\n\tint reg_width;\n\tvoid *reg_base;\n\tstruct clk *cclk;\n};\n\nstruct usb_otg_caps {\n\tu16 otg_rev;\n\tbool hnp_support;\n\tbool srp_support;\n\tbool adp_support;\n};\n\nstruct dwc2_core_params {\n\tstruct usb_otg_caps otg_caps;\n\tu8 phy_type;\n\tu8 speed;\n\tu8 phy_utmi_width;\n\tbool eusb2_disc;\n\tbool phy_ulpi_ddr;\n\tbool phy_ulpi_ext_vbus;\n\tbool enable_dynamic_fifo;\n\tbool en_multiple_tx_fifo;\n\tbool i2c_enable;\n\tbool acg_enable;\n\tbool ulpi_fs_ls;\n\tbool ts_dline;\n\tbool reload_ctl;\n\tbool uframe_sched;\n\tbool external_id_pin_ctl;\n\tint power_down;\n\tbool no_clock_gating;\n\tbool lpm;\n\tbool lpm_clock_gating;\n\tbool besl;\n\tbool hird_threshold_en;\n\tbool service_interval;\n\tu8 hird_threshold;\n\tbool activate_stm_fs_transceiver;\n\tbool activate_stm_id_vb_detection;\n\tbool activate_ingenic_overcurrent_detection;\n\tbool ipg_isoc_en;\n\tu16 max_packet_count;\n\tu32 max_transfer_size;\n\tu32 ahbcfg;\n\tu32 ref_clk_per;\n\tu16 sof_cnt_wkup_alert;\n\tbool host_dma;\n\tbool dma_desc_enable;\n\tbool dma_desc_fs_enable;\n\tbool host_support_fs_ls_low_power;\n\tbool host_ls_low_power_phy_clk;\n\tbool oc_disable;\n\tu8 host_channels;\n\tu16 host_rx_fifo_size;\n\tu16 host_nperio_tx_fifo_size;\n\tu16 host_perio_tx_fifo_size;\n\tbool g_dma;\n\tbool g_dma_desc;\n\tu32 g_rx_fifo_size;\n\tu32 g_np_tx_fifo_size;\n\tu32 g_tx_fifo_size[16];\n\tbool change_speed_quirk;\n};\n\nstruct dwc2_dma_desc {\n\tu32 status;\n\tu32 buf;\n};\n\nstruct dwc2_dregs_backup {\n\tu32 dcfg;\n\tu32 dctl;\n\tu32 daintmsk;\n\tu32 diepmsk;\n\tu32 doepmsk;\n\tu32 diepctl[16];\n\tu32 dieptsiz[16];\n\tu32 diepdma[16];\n\tu32 doepctl[16];\n\tu32 doeptsiz[16];\n\tu32 doepdma[16];\n\tu32 dtxfsiz[16];\n\tbool valid;\n};\n\nstruct dwc2_gregs_backup {\n\tu32 gintsts;\n\tu32 gotgctl;\n\tu32 gintmsk;\n\tu32 gahbcfg;\n\tu32 gusbcfg;\n\tu32 grxfsiz;\n\tu32 gnptxfsiz;\n\tu32 gi2cctl;\n\tu32 glpmcfg;\n\tu32 pcgcctl;\n\tu32 pcgcctl1;\n\tu32 gdfifocfg;\n\tu32 gpwrdn;\n\tbool valid;\n};\n\nunion dwc2_hcd_internal_flags {\n\tu32 d32;\n\tstruct {\n\t\tunsigned int port_connect_status_change: 1;\n\t\tunsigned int port_connect_status: 1;\n\t\tunsigned int port_reset_change: 1;\n\t\tunsigned int port_enable_change: 1;\n\t\tunsigned int port_suspend_change: 1;\n\t\tunsigned int port_over_current_change: 1;\n\t\tunsigned int port_l1_change: 1;\n\t\tunsigned int reserved: 25;\n\t} b;\n};\n\nstruct dwc2_hcd_iso_packet_desc {\n\tu32 offset;\n\tu32 length;\n\tu32 actual_length;\n\tu32 status;\n};\n\nstruct dwc2_hcd_pipe_info {\n\tu8 dev_addr;\n\tu8 ep_num;\n\tu8 pipe_type;\n\tu8 pipe_dir;\n\tu16 maxp;\n\tu16 maxp_mult;\n};\n\nstruct dwc2_qtd;\n\nstruct dwc2_hcd_urb {\n\tvoid *priv;\n\tstruct dwc2_qtd *qtd;\n\tvoid *buf;\n\tdma_addr_t dma;\n\tvoid *setup_packet;\n\tdma_addr_t setup_dma;\n\tu32 length;\n\tu32 actual_length;\n\tu32 status;\n\tu32 error_count;\n\tu32 packet_count;\n\tu32 flags;\n\tu16 interval;\n\tstruct dwc2_hcd_pipe_info pipe_info;\n\tstruct dwc2_hcd_iso_packet_desc iso_descs[0];\n};\n\nstruct dwc2_qh;\n\nstruct dwc2_host_chan {\n\tu8 hc_num;\n\tunsigned int dev_addr: 7;\n\tunsigned int ep_num: 4;\n\tunsigned int ep_is_in: 1;\n\tunsigned int speed: 4;\n\tunsigned int ep_type: 2;\n\tlong: 6;\n\tunsigned int max_packet: 11;\n\tunsigned int data_pid_start: 2;\n\tunsigned int multi_count: 2;\n\tu8 *xfer_buf;\n\tdma_addr_t xfer_dma;\n\tdma_addr_t align_buf;\n\tu32 xfer_len;\n\tu32 xfer_count;\n\tu16 start_pkt_count;\n\tu8 xfer_started;\n\tu8 do_ping;\n\tu8 error_state;\n\tu8 halt_on_queue;\n\tu8 halt_pending;\n\tu8 do_split;\n\tu8 complete_split;\n\tu8 hub_addr;\n\tu8 hub_port;\n\tu8 xact_pos;\n\tu8 requests;\n\tu8 schinfo;\n\tu16 ntd;\n\tenum dwc2_halt_status halt_status;\n\tu32 hcint;\n\tstruct dwc2_qh *qh;\n\tstruct list_head hc_list_entry;\n\tdma_addr_t desc_list_addr;\n\tu32 desc_list_sz;\n\tstruct list_head split_order_list_entry;\n};\n\nstruct dwc2_hregs_backup {\n\tu32 hcfg;\n\tu32 hflbaddr;\n\tu32 haintmsk;\n\tu32 hcchar[16];\n\tu32 hcsplt[16];\n\tu32 hcintmsk[16];\n\tu32 hctsiz[16];\n\tu32 hcidma[16];\n\tu32 hcidmab[16];\n\tu32 hprt0;\n\tu32 hfir;\n\tu32 hptxfsiz;\n\tbool valid;\n};\n\nstruct dwc2_hs_transfer_time {\n\tu32 start_schedule_us;\n\tu16 duration_us;\n};\n\nstruct dwc2_hw_params {\n\tunsigned int op_mode: 3;\n\tunsigned int arch: 2;\n\tunsigned int dma_desc_enable: 1;\n\tunsigned int enable_dynamic_fifo: 1;\n\tunsigned int en_multiple_tx_fifo: 1;\n\tunsigned int rx_fifo_size: 16;\n\tlong: 8;\n\tunsigned int host_nperio_tx_fifo_size: 16;\n\tunsigned int dev_nperio_tx_fifo_size: 16;\n\tunsigned int host_perio_tx_fifo_size: 16;\n\tunsigned int nperio_tx_q_depth: 3;\n\tunsigned int host_perio_tx_q_depth: 3;\n\tunsigned int dev_token_q_depth: 5;\n\tlong: 5;\n\tunsigned int max_transfer_size: 26;\n\tlong: 6;\n\tunsigned int max_packet_count: 11;\n\tunsigned int host_channels: 5;\n\tunsigned int hs_phy_type: 2;\n\tunsigned int fs_phy_type: 2;\n\tunsigned int i2c_enable: 1;\n\tunsigned int acg_enable: 1;\n\tunsigned int num_dev_ep: 4;\n\tunsigned int num_dev_in_eps: 4;\n\tlong: 2;\n\tunsigned int num_dev_perio_in_ep: 4;\n\tunsigned int total_fifo_size: 16;\n\tunsigned int power_optimized: 1;\n\tunsigned int hibernation: 1;\n\tunsigned int utmi_phy_data_width: 2;\n\tunsigned int lpm_mode: 1;\n\tunsigned int ipg_isoc_en: 1;\n\tunsigned int service_interval_mode: 1;\n\tu32 snpsid;\n\tu32 dev_ep_dirs;\n\tu32 g_tx_fifo_size[16];\n};\n\nstruct regulator_bulk_data {\n\tconst char *supply;\n\tstruct regulator *consumer;\n\tint init_load_uA;\n\tint ret;\n};\n\nstruct usb_role_switch;\n\nstruct usb_phy;\n\nstruct dwc2_hsotg_plat;\n\nstruct dwc2_hsotg {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct dwc2_hw_params hw_params;\n\tstruct dwc2_core_params params;\n\tenum usb_otg_state op_state;\n\tenum usb_dr_mode dr_mode;\n\tstruct usb_role_switch *role_sw;\n\tenum usb_dr_mode role_sw_default_mode;\n\tunsigned int hcd_enabled: 1;\n\tunsigned int gadget_enabled: 1;\n\tunsigned int ll_hw_enabled: 1;\n\tunsigned int hibernated: 1;\n\tunsigned int in_ppd: 1;\n\tbool bus_suspended;\n\tunsigned int reset_phy_on_wake: 1;\n\tunsigned int need_phy_for_wake: 1;\n\tunsigned int phy_off_for_suspend: 1;\n\tu16 frame_number;\n\tstruct phy *phy;\n\tstruct usb_phy *uphy;\n\tstruct dwc2_hsotg_plat *plat;\n\tstruct regulator_bulk_data supplies[2];\n\tstruct regulator *vbus_supply;\n\tstruct regulator *usb33d;\n\tspinlock_t lock;\n\tvoid *priv;\n\tint irq;\n\tstruct clk *clk;\n\tstruct clk *utmi_clk;\n\tstruct reset_control *reset;\n\tstruct reset_control *reset_ecc;\n\tunsigned int queuing_high_bandwidth: 1;\n\tunsigned int srp_success: 1;\n\tstruct workqueue_struct *wq_otg;\n\tstruct work_struct wf_otg;\n\tstruct timer_list wkp_timer;\n\tenum dwc2_lx_state lx_state;\n\tstruct dwc2_gregs_backup gr_backup;\n\tstruct dwc2_dregs_backup dr_backup;\n\tstruct dwc2_hregs_backup hr_backup;\n\tstruct dentry *debug_root;\n\tstruct debugfs_regset32 *regset;\n\tbool needs_byte_swap;\n\tunion dwc2_hcd_internal_flags flags;\n\tstruct list_head non_periodic_sched_inactive;\n\tstruct list_head non_periodic_sched_waiting;\n\tstruct list_head non_periodic_sched_active;\n\tstruct list_head *non_periodic_qh_ptr;\n\tstruct list_head periodic_sched_inactive;\n\tstruct list_head periodic_sched_ready;\n\tstruct list_head periodic_sched_assigned;\n\tstruct list_head periodic_sched_queued;\n\tstruct list_head split_order;\n\tu16 periodic_usecs;\n\tlong unsigned int hs_periodic_bitmap[25];\n\tu16 periodic_qh_count;\n\tbool new_connection;\n\tu16 last_frame_num;\n\tstruct list_head free_hc_list;\n\tint periodic_channels;\n\tint non_periodic_channels;\n\tint available_host_channels;\n\tstruct dwc2_host_chan *hc_ptr_array[16];\n\tu8 *status_buf;\n\tdma_addr_t status_buf_dma;\n\tstruct delayed_work start_work;\n\tstruct delayed_work reset_work;\n\tstruct work_struct phy_reset_work;\n\tu8 otg_port;\n\tu32 *frame_list;\n\tdma_addr_t frame_list_dma;\n\tu32 frame_list_sz;\n\tstruct kmem_cache *desc_gen_cache;\n\tstruct kmem_cache *desc_hsisoc_cache;\n\tstruct kmem_cache *unaligned_cache;\n};\n\nstruct dwc2_hsotg_plat {\n\tenum dwc2_hsotg_dmamode dma;\n\tunsigned int is_osc: 1;\n\tint phy_type;\n\tint (*phy_init)(struct platform_device *, int);\n\tint (*phy_exit)(struct platform_device *, int);\n};\n\nstruct dwc2_tt;\n\nstruct dwc2_qh {\n\tstruct dwc2_hsotg *hsotg;\n\tu8 ep_type;\n\tu8 ep_is_in;\n\tu16 maxp;\n\tu16 maxp_mult;\n\tu8 dev_speed;\n\tu8 data_toggle;\n\tu8 ping_state;\n\tu8 do_split;\n\tu8 td_first;\n\tu8 td_last;\n\tu16 host_us;\n\tu16 device_us;\n\tu16 host_interval;\n\tu16 device_interval;\n\tu16 next_active_frame;\n\tu16 start_active_frame;\n\ts16 num_hs_transfers;\n\tstruct dwc2_hs_transfer_time hs_transfers[8];\n\tu32 ls_start_schedule_slice;\n\tu16 ntd;\n\tu8 *dw_align_buf;\n\tdma_addr_t dw_align_buf_dma;\n\tstruct list_head qtd_list;\n\tstruct dwc2_host_chan *channel;\n\tstruct list_head qh_list_entry;\n\tstruct dwc2_dma_desc *desc_list;\n\tdma_addr_t desc_list_dma;\n\tu32 desc_list_sz;\n\tu32 *n_bytes;\n\tstruct timer_list unreserve_timer;\n\tstruct hrtimer wait_timer;\n\tstruct dwc2_tt *dwc_tt;\n\tint ttport;\n\tunsigned int tt_buffer_dirty: 1;\n\tunsigned int unreserve_pending: 1;\n\tunsigned int schedule_low_speed: 1;\n\tunsigned int want_wait: 1;\n\tunsigned int wait_timer_cancel: 1;\n\tlong: 32;\n};\n\nstruct dwc2_qtd {\n\tenum dwc2_control_phase control_phase;\n\tu8 in_process;\n\tu8 data_toggle;\n\tu8 complete_split;\n\tu8 isoc_split_pos;\n\tu16 isoc_frame_index;\n\tu16 isoc_split_offset;\n\tu16 isoc_td_last;\n\tu16 isoc_td_first;\n\tu32 ssplit_out_xfer_count;\n\tu8 error_count;\n\tu8 n_desc;\n\tu16 isoc_frame_index_last;\n\tu16 num_naks;\n\tstruct dwc2_hcd_urb *urb;\n\tstruct dwc2_qh *qh;\n\tstruct list_head qtd_list_entry;\n};\n\nstruct usb_tt;\n\nstruct dwc2_tt {\n\tint refcount;\n\tstruct usb_tt *usb_tt;\n\tlong unsigned int periodic_bitmaps[0];\n};\n\nstruct dwmac4_addrs {\n\tu32 dma_chan;\n\tu32 dma_chan_offset;\n\tu32 mtl_chan;\n\tu32 mtl_chan_offset;\n\tu32 mtl_ets_ctrl;\n\tu32 mtl_ets_ctrl_offset;\n\tu32 mtl_txq_weight;\n\tu32 mtl_txq_weight_offset;\n\tu32 mtl_send_slp_cred;\n\tu32 mtl_send_slp_cred_offset;\n\tu32 mtl_high_cred;\n\tu32 mtl_high_cred_offset;\n\tu32 mtl_low_cred;\n\tu32 mtl_low_cred_offset;\n};\n\nstruct dwmac5_error_desc;\n\nstruct dwmac5_error {\n\tconst struct dwmac5_error_desc *desc;\n};\n\nstruct dwmac5_error_desc {\n\tbool valid;\n\tconst char *desc;\n\tconst char *detailed_desc;\n};\n\nstruct dwxgmac3_error_desc;\n\nstruct dwxgmac3_error {\n\tconst struct dwxgmac3_error_desc *desc;\n};\n\nstruct dwxgmac3_error_desc {\n\tbool valid;\n\tconst char *desc;\n\tconst char *detailed_desc;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct usb_device;\n\nstruct each_dev_arg {\n\tvoid *data;\n\tint (*fn)(struct usb_device *, void *);\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\tunion {\n\t\t__u32 padding[5];\n\t\tstruct {\n\t\t\t__u8 addr_recv;\n\t\t\t__u8 addr_dest;\n\t\t\t__u8 padding0[2];\n\t\t\t__u32 padding1[4];\n\t\t};\n\t};\n};\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct ktermios;\n\nstruct uart_state;\n\nstruct uart_ops;\n\nstruct serial_port_device;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int ctrl_id;\n\tunsigned int port_id;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char quirks;\n\tenum uart_iotype iotype;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tlong: 32;\n\tupf_t flags;\n\tupstat_t status;\n\tbool hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int frame_time;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tstruct serial_port_device *port_dev;\n\tlong unsigned int sysrq;\n\tu8 sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tunsigned char console_reinit;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct serial_rs485 rs485_supported;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct gpio_desc *rs485_rx_during_tx_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tlong: 32;\n\tstruct uart_port port;\n\tchar options[32];\n\tunsigned int baud;\n\tlong: 32;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nstruct td;\n\nstruct ed {\n\t__hc32 hwINFO;\n\t__hc32 hwTailP;\n\t__hc32 hwHeadP;\n\t__hc32 hwNextED;\n\tdma_addr_t dma;\n\tstruct td *dummy;\n\tstruct ed *ed_next;\n\tstruct ed *ed_prev;\n\tstruct list_head td_list;\n\tstruct list_head in_use_list;\n\tu8 state;\n\tu8 type;\n\tu8 branch;\n\tu16 interval;\n\tu16 load;\n\tu16 last_iso;\n\tu16 tick;\n\tunsigned int takeback_wdh_cnt;\n\tstruct td *pending_td;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[4];\n\tlong unsigned int advertised[4];\n\tlong unsigned int lp_advertised[4];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct eeprom_93cx6 {\n\tvoid *data;\n\tvoid (*register_read)(struct eeprom_93cx6 *);\n\tvoid (*register_write)(struct eeprom_93cx6 *);\n\tint width;\n\tunsigned int quirks;\n\tchar drive_data;\n\tchar reg_data_in;\n\tchar reg_data_out;\n\tchar reg_data_clock;\n\tchar reg_chip_select;\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct usb_hcd;\n\nstruct ehci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\nstruct ehci_qh;\n\nstruct ehci_itd;\n\nstruct ehci_sitd;\n\nstruct ehci_fstn;\n\nunion ehci_shadow {\n\tstruct ehci_qh *qh;\n\tstruct ehci_itd *itd;\n\tstruct ehci_sitd *sitd;\n\tstruct ehci_fstn *fstn;\n\t__le32 *hw_next;\n\tvoid *ptr;\n};\n\nstruct ehci_fstn {\n\t__le32 hw_next;\n\t__le32 hw_prev;\n\tdma_addr_t fstn_dma;\n\tunion ehci_shadow fstn_next;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_regs;\n\nstruct ehci_hcd {\n\tenum ehci_hrtimer_event next_hrtimer_event;\n\tunsigned int enabled_hrtimer_events;\n\tktime_t hr_timeouts[12];\n\tstruct hrtimer hrtimer;\n\tint PSS_poll_count;\n\tint ASS_poll_count;\n\tint died_poll_count;\n\tstruct ehci_caps *caps;\n\tstruct ehci_regs *regs;\n\tstruct ehci_dbg_port *debug;\n\t__u32 hcs_params;\n\tspinlock_t lock;\n\tenum ehci_rh_state rh_state;\n\tbool scanning: 1;\n\tbool need_rescan: 1;\n\tbool intr_unlinking: 1;\n\tbool iaa_in_progress: 1;\n\tbool async_unlinking: 1;\n\tbool shutdown: 1;\n\tstruct ehci_qh *qh_scan_next;\n\tstruct ehci_qh *async;\n\tstruct ehci_qh *dummy;\n\tstruct list_head async_unlink;\n\tstruct list_head async_idle;\n\tunsigned int async_unlink_cycle;\n\tunsigned int async_count;\n\t__le32 old_current;\n\t__le32 old_token;\n\tunsigned int periodic_size;\n\t__le32 *periodic;\n\tdma_addr_t periodic_dma;\n\tstruct list_head intr_qh_list;\n\tunsigned int i_thresh;\n\tunion ehci_shadow *pshadow;\n\tstruct list_head intr_unlink_wait;\n\tstruct list_head intr_unlink;\n\tunsigned int intr_unlink_wait_cycle;\n\tunsigned int intr_unlink_cycle;\n\tunsigned int now_frame;\n\tunsigned int last_iso_frame;\n\tunsigned int intr_count;\n\tunsigned int isoc_count;\n\tunsigned int periodic_count;\n\tunsigned int uframe_periodic_max;\n\tstruct list_head cached_itd_list;\n\tstruct ehci_itd *last_itd_to_free;\n\tstruct list_head cached_sitd_list;\n\tstruct ehci_sitd *last_sitd_to_free;\n\tlong unsigned int reset_done[15];\n\tlong unsigned int bus_suspended;\n\tlong unsigned int companion_ports;\n\tlong unsigned int owned_ports;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int suspended_ports;\n\tlong unsigned int resuming_ports;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *qtd_pool;\n\tstruct dma_pool *itd_pool;\n\tstruct dma_pool *sitd_pool;\n\tunsigned int random_frame;\n\tlong unsigned int next_statechange;\n\tlong: 32;\n\tktime_t last_periodic_enable;\n\tu32 command;\n\tunsigned int no_selective_suspend: 1;\n\tunsigned int has_fsl_port_bug: 1;\n\tunsigned int has_fsl_hs_errata: 1;\n\tunsigned int has_fsl_susp_errata: 1;\n\tunsigned int has_ci_pec_bug: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_capbase: 1;\n\tunsigned int has_amcc_usb23: 1;\n\tunsigned int need_io_watchdog: 1;\n\tunsigned int amd_pll_fix: 1;\n\tunsigned int use_dummy_qh: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int frame_index_bug: 1;\n\tunsigned int need_oc_pp_cycle: 1;\n\tunsigned int imx28_write_fix: 1;\n\tunsigned int spurious_oc: 1;\n\tunsigned int is_aspeed: 1;\n\tunsigned int zx_wakeup_clear_needed: 1;\n\t__le32 *ohci_hcctrl_reg;\n\tunsigned int has_hostpc: 1;\n\tunsigned int has_tdi_phy_lpm: 1;\n\tunsigned int has_ppcd: 1;\n\tu8 sbrn;\n\tu8 bandwidth[64];\n\tu8 tt_budget[64];\n\tstruct list_head tt_list;\n\tlong unsigned int priv[0];\n};\n\nstruct ehci_iso_packet {\n\tu64 bufp;\n\t__le32 transaction;\n\tu8 cross;\n\tu32 buf1;\n\tlong: 32;\n};\n\nstruct ehci_iso_sched {\n\tstruct list_head td_list;\n\tunsigned int span;\n\tunsigned int first_packet;\n\tstruct ehci_iso_packet packet[0];\n};\n\nstruct usb_host_endpoint;\n\nstruct ehci_per_sched {\n\tstruct usb_device *udev;\n\tstruct usb_host_endpoint *ep;\n\tstruct list_head ps_list;\n\tu16 tt_usecs;\n\tu16 cs_mask;\n\tu16 period;\n\tu16 phase;\n\tu8 bw_phase;\n\tu8 phase_uf;\n\tu8 usecs;\n\tu8 c_usecs;\n\tu8 bw_uperiod;\n\tu8 bw_period;\n};\n\nstruct ehci_qh_hw;\n\nstruct ehci_iso_stream {\n\tstruct ehci_qh_hw *hw;\n\tu8 bEndpointAddress;\n\tu8 highspeed;\n\tstruct list_head td_list;\n\tstruct list_head free_list;\n\tstruct ehci_per_sched ps;\n\tunsigned int next_uframe;\n\t__le32 splits;\n\tu16 uperiod;\n\tu16 maxp;\n\tunsigned int bandwidth;\n\t__le32 buf0;\n\t__le32 buf1;\n\t__le32 buf2;\n\t__le32 address;\n};\n\nstruct ehci_itd {\n\t__le32 hw_next;\n\t__le32 hw_transaction[8];\n\t__le32 hw_bufp[7];\n\t__le32 hw_bufp_hi[7];\n\tdma_addr_t itd_dma;\n\tunion ehci_shadow itd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head itd_list;\n\tunsigned int frame;\n\tunsigned int pg;\n\tunsigned int index[8];\n\tlong: 32;\n};\n\nstruct ehci_qtd;\n\nstruct ehci_qh {\n\tstruct ehci_qh_hw *hw;\n\tdma_addr_t qh_dma;\n\tunion ehci_shadow qh_next;\n\tstruct list_head qtd_list;\n\tstruct list_head intr_node;\n\tstruct ehci_qtd *dummy;\n\tstruct list_head unlink_node;\n\tstruct ehci_per_sched ps;\n\tunsigned int unlink_cycle;\n\tu8 qh_state;\n\tu8 xacterrs;\n\tu8 unlink_reason;\n\tu8 gap_uf;\n\tunsigned int is_out: 1;\n\tunsigned int clearing_tt: 1;\n\tunsigned int dequeue_during_giveback: 1;\n\tunsigned int should_be_inactive: 1;\n};\n\nstruct ehci_qh_hw {\n\t__le32 hw_next;\n\t__le32 hw_info1;\n\t__le32 hw_info2;\n\t__le32 hw_current;\n\t__le32 hw_qtd_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_qtd {\n\t__le32 hw_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tdma_addr_t qtd_dma;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tunion {\n\t\tu32 port_status[15];\n\t\tstruct {\n\t\t\tu32 reserved3[9];\n\t\t\tu32 usbmode;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved4;\n\t\t\tu32 hostpc[15];\n\t\t};\n\t\tu32 brcm_insnreg[4];\n\t};\n\tu32 reserved5[2];\n\tu32 usbmode_ex;\n};\n\nstruct ehci_sitd {\n\t__le32 hw_next;\n\t__le32 hw_fullspeed_ep;\n\t__le32 hw_uframe;\n\t__le32 hw_results;\n\t__le32 hw_buf[2];\n\t__le32 hw_backpointer;\n\t__le32 hw_buf_hi[2];\n\tdma_addr_t sitd_dma;\n\tunion ehci_shadow sitd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head sitd_list;\n\tunsigned int frame;\n\tunsigned int index;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_tt {\n\tu16 bandwidth[8];\n\tstruct list_head tt_list;\n\tstruct list_head ps_list;\n\tstruct usb_tt *usb_tt;\n\tint tt_port;\n};\n\nstruct elevator_queue;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf32_rel {\n\tElf32_Addr r_offset;\n\tElf32_Word r_info;\n};\n\ntypedef struct elf32_rel Elf32_Rel;\n\nstruct elf32_rela {\n\tElf32_Addr r_offset;\n\tElf32_Word r_info;\n\tElf32_Sword r_addend;\n};\n\ntypedef struct elf32_rela Elf32_Rela;\n\nstruct elf32_shdr {\n\tElf32_Word sh_name;\n\tElf32_Word sh_type;\n\tElf32_Word sh_flags;\n\tElf32_Addr sh_addr;\n\tElf32_Off sh_offset;\n\tElf32_Word sh_size;\n\tElf32_Word sh_link;\n\tElf32_Word sh_info;\n\tElf32_Word sh_addralign;\n\tElf32_Word sh_entsize;\n};\n\ntypedef struct elf32_shdr Elf32_Shdr;\n\nstruct elf32_sym {\n\tElf32_Word st_name;\n\tElf32_Addr st_value;\n\tElf32_Word st_size;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf32_Half st_shndx;\n};\n\ntypedef struct elf32_sym Elf32_Sym;\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_code;\n\t\t\tint si_errno;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct emuframe {\n\tmips_instruction emul;\n\tmips_instruction badinst;\n};\n\nstruct xdr_buf;\n\nstruct encryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tint pos;\n\tstruct xdr_buf *outbuf;\n\tstruct page **pages;\n\tstruct scatterlist infrags[4];\n\tstruct scatterlist outfrags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\nstruct usb_endpoint_descriptor;\n\nstruct ep_device {\n\tstruct usb_endpoint_descriptor *desc;\n\tstruct usb_device *udev;\n\tstruct device dev;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n};\n\nstruct epoll_event {\n\t__poll_t events;\n\tlong: 32;\n\t__u64 data;\n};\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct erase_info {\n\tuint64_t addr;\n\tuint64_t len;\n\tuint64_t fail_addr;\n};\n\nstruct erase_info_user {\n\t__u32 start;\n\t__u32 length;\n};\n\nstruct erase_info_user64 {\n\t__u64 start;\n\t__u64 length;\n};\n\nstruct errormap {\n\tchar *name;\n\tint val;\n\tint namelen;\n\tstruct hlist_node list;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n\tlong: 32;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[4];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[4];\n\t\tlong unsigned int advertising[4];\n\t\tlong unsigned int lp_advertising[4];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct ethtool_tunable;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n\tlong: 32;\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\tlong: 32;\n\t__u64 ring_cookie;\n\t__u32 location;\n\tlong: 32;\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n\tlong: 32;\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct input_handler;\n\nstruct input_value;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tlong: 32;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct event_dev {\n\tstruct input_dev *input;\n\tint irq;\n\tvoid *addr;\n\tchar name[0];\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tlong: 32;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n};\n\nstruct ewma_pkt_len {\n\tlong unsigned int internal;\n};\n\nstruct exar8250_board;\n\nstruct exar8250 {\n\tunsigned int nr;\n\tunsigned int osc_freq;\n\tstruct exar8250_board *board;\n\tstruct eeprom_93cx6 eeprom;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tconst struct serial_rs485 *rs485_supported;\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n\tvoid (*unregister_gpio)(struct uart_8250_port *);\n};\n\nstruct exception_table_entry {\n\tlong unsigned int insn;\n\tlong unsigned int nextinsn;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct iattr;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_buddy;\n\nstruct ext4_prealloc_space;\n\nstruct ext4_locality_group;\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\text4_grpblk_t ac_orig_goal_len;\n\text4_group_t ac_prefetch_grp;\n\tunsigned int ac_prefetch_ios;\n\tunsigned int ac_prefetch_nr;\n\tint ac_first_err;\n\t__u32 ac_flags;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_cX_found[5];\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct ext4_buddy *ac_e4b;\n\tstruct folio *ac_bitmap_folio;\n\tstruct folio *ac_buddy_folio;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\tlong: 32;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n\tlong: 32;\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_group_info;\n\nstruct ext4_buddy {\n\tstruct folio *bd_buddy_folio;\n\tvoid *bd_buddy;\n\tstruct folio *bd_bitmap_folio;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_hash {\n\t__le32 hash;\n\t__le32 minor_hash;\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\nstruct ext4_err_translation {\n\tint code;\n\tint errno;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tlong: 32;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct extent_status;\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_extent;\n\nstruct ext4_extent_idx;\n\nstruct ext4_extent_header;\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n\tlong: 32;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_fc_add_range {\n\t__le32 fc_ino;\n\t__u8 fc_ex[12];\n};\n\nstruct ext4_fc_alloc_region {\n\text4_lblk_t lblk;\n\tlong: 32;\n\text4_fsblk_t pblk;\n\tint ino;\n\tint len;\n};\n\nstruct ext4_fc_del_range {\n\t__le32 fc_ino;\n\t__le32 fc_lblk;\n\t__le32 fc_len;\n};\n\nstruct ext4_fc_dentry_info {\n\t__le32 fc_parent_ino;\n\t__le32 fc_ino;\n\t__u8 fc_dname[0];\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n\tlong: 32;\n};\n\nstruct ext4_fc_dentry_update {\n\tint fcd_op;\n\tint fcd_parent;\n\tint fcd_ino;\n\tlong: 32;\n\tstruct name_snapshot fcd_name;\n\tstruct list_head fcd_list;\n\tstruct list_head fcd_dilist;\n};\n\nstruct ext4_fc_head {\n\t__le32 fc_features;\n\t__le32 fc_tid;\n};\n\nstruct ext4_fc_inode {\n\t__le32 fc_ino;\n\t__u8 fc_raw_inode[0];\n};\n\nstruct ext4_fc_replay_state {\n\tint fc_replay_num_tags;\n\tint fc_replay_expected_off;\n\tint fc_current_pass;\n\tint fc_cur_tag;\n\tint fc_crc;\n\tstruct ext4_fc_alloc_region *fc_regions;\n\tint fc_regions_size;\n\tint fc_regions_used;\n\tint fc_regions_valid;\n\tint *fc_modified_inodes;\n\tint fc_modified_inodes_used;\n\tint fc_modified_inodes_size;\n};\n\nstruct ext4_fc_stats {\n\tunsigned int fc_ineligible_reason_count[13];\n\tlong unsigned int fc_num_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_failed_commits;\n\tlong unsigned int fc_skipped_commits;\n\tlong unsigned int fc_numblks;\n\tu64 s_fc_avg_commit_time;\n};\n\nstruct ext4_fc_tail {\n\t__le32 fc_tid;\n\t__le32 fc_crc;\n};\n\nstruct ext4_fc_tl {\n\t__le16 fc_tag;\n\t__le16 fc_len;\n};\n\nstruct ext4_fc_tl_mem {\n\tu16 fc_tag;\n\tu16 fc_len;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n\tstruct fscrypt_str crypto_buf;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nunion fscrypt_policy;\n\nstruct fscrypt_dummy_policy {\n\tconst union fscrypt_policy *policy;\n};\n\nstruct ext4_fs_context {\n\tchar *s_qf_names[3];\n\tstruct fscrypt_dummy_policy dummy_enc_policy;\n\tint s_jquota_fmt;\n\tshort unsigned int qname_spec;\n\tlong unsigned int vals_s_flags;\n\tlong unsigned int mask_s_flags;\n\tlong unsigned int journal_devnum;\n\tlong unsigned int s_commit_interval;\n\tlong unsigned int s_stripe;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_want_extra_isize;\n\tunsigned int s_li_wait_mult;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int journal_ioprio;\n\tunsigned int vals_s_mount_opt;\n\tunsigned int mask_s_mount_opt;\n\tunsigned int vals_s_mount_opt2;\n\tunsigned int mask_s_mount_opt2;\n\tunsigned int opt_flags;\n\tunsigned int spec;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\text4_fsblk_t s_sb_block;\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\nstruct ext4_getfsmap_info;\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\tlong: 32;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n\tlong: 32;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\tint bb_avg_fragment_size_order;\n\text4_grpblk_t bb_largest_free_order;\n\text4_group_t bb_group;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct qrwlock {\n\tunion {\n\t\tatomic_t cnts;\n\t\tstruct {\n\t\t\tu8 wlocked;\n\t\t\tu8 __lstate[3];\n\t\t};\n\t};\n\tarch_spinlock_t wait_lock;\n};\n\ntypedef struct qrwlock arch_rwlock_t;\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct jbd2_inode;\n\nstruct fscrypt_inode_info;\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_state_flags;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tunion {\n\t\tstruct list_head i_orphan;\n\t\tunsigned int i_orphan_idx;\n\t};\n\tstruct list_head i_fc_dilist;\n\tstruct list_head i_fc_list;\n\text4_lblk_t i_fc_lblk_start;\n\text4_lblk_t i_fc_lblk_len;\n\tspinlock_t i_raw_lock;\n\twait_queue_head_t i_fc_wait;\n\tspinlock_t i_fc_lock;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tlong: 32;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tlong: 32;\n\tstruct timespec64 i_crtime;\n\tatomic_t i_prealloc_active;\n\tunsigned int i_reserved_data_blocks;\n\tstruct rb_root i_prealloc_node;\n\trwlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\tu64 i_es_seq;\n\text4_group_t i_last_alloc_group;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tspinlock_t i_block_reservation_lock;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n\tstruct fscrypt_inode_info *i_crypt_info;\n\tlong: 32;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\trefcount_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n\tlong: 32;\n};\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tlong: 32;\n\tsector_t io_next_block;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct ext4_journal_trigger {\n\tstruct jbd2_buffer_trigger_type tr_triggers;\n\tstruct super_block *sb;\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tenum ext4_li_mode lr_mode;\n\text4_group_t lr_first_not_zeroed;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n\tlong: 32;\n\tu64 m_seq;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n};\n\nstruct ext4_new_group_data;\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t resize_bg;\n\text4_group_t count;\n};\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\tlong: 32;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n\tlong: 32;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\tlong: 32;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct ext4_orphan_block {\n\tatomic_t ob_free_entries;\n\tstruct buffer_head *ob_bh;\n};\n\nstruct ext4_orphan_block_tail {\n\t__le32 ob_magic;\n\t__le32 ob_checksum;\n};\n\nstruct ext4_orphan_info {\n\tint of_blocks;\n\t__u32 of_csum_seed;\n\tstruct ext4_orphan_block *of_binfo;\n};\n\nstruct ext4_prealloc_space {\n\tunion {\n\t\tstruct rb_node inode_node;\n\t\tstruct list_head lg_list;\n\t} pa_node;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tunion {\n\t\trwlock_t *inode_lock;\n\t\tspinlock_t *lg_lock;\n\t} pa_node_lock;\n\tstruct inode *pa_inode;\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct ext4_super_block;\n\nstruct journal_s;\n\nstruct ext4_system_blocks;\n\nstruct flex_groups;\n\nstruct shrinker;\n\nstruct mb_cache;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tlong: 32;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tlong unsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\tunsigned int s_def_mount_opt2;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tlong: 32;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct percpu_counter s_sra_exceeded_retry_limit;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct buffer_head *s_mmp_bh;\n\tstruct journal_s *s_journal;\n\tlong unsigned int s_ext4_flags;\n\tstruct mutex s_orphan_lock;\n\tstruct list_head s_orphan;\n\tstruct ext4_orphan_info s_orphan_info;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct file *s_journal_bdev_file;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *s_system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tatomic_t s_mb_free_pending;\n\tstruct list_head s_freed_data_list[2];\n\tstruct list_head s_discard_list;\n\tstruct work_struct s_discard_work;\n\tatomic_t s_retry_alloc_pending;\n\tstruct xarray *s_mb_avg_fragment_size;\n\tstruct xarray *s_mb_largest_free_orders;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_max_linear_groups;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int s_mb_prefetch;\n\tunsigned int s_mb_prefetch_limit;\n\tunsigned int s_mb_best_avail_max_trim_order;\n\tunsigned int s_sb_update_sec;\n\tunsigned int s_sb_update_kb;\n\text4_group_t *s_mb_last_groups;\n\tunsigned int s_mb_nr_global_goals;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_cX_ex_scanned[5];\n\tatomic_t s_bal_groups_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_stream_goals;\n\tatomic_t s_bal_len_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tlong: 32;\n\tatomic64_t s_bal_cX_groups_considered[5];\n\tatomic64_t s_bal_cX_hits[5];\n\tatomic64_t s_bal_cX_failed[5];\n\tatomic_t s_mb_buddies_generated;\n\tlong: 32;\n\tatomic64_t s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tlong unsigned int s_err_report_sec;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tlong unsigned int s_last_trim_minblks;\n\tu16 s_min_folio_order;\n\tu16 s_max_folio_order;\n\t__u32 s_csum_seed;\n\tstruct shrinker *s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tlong: 32;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache *s_ea_block_cache;\n\tstruct mb_cache *s_ea_inode_cache;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t s_es_lock;\n\tstruct ext4_journal_trigger s_journal_triggers[1];\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tatomic_t s_warning_count;\n\tatomic_t s_msg_count;\n\tstruct fscrypt_dummy_policy s_dummy_enc_policy;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tu64 s_dax_part_off;\n\terrseq_t s_bdev_wb_err;\n\tspinlock_t s_bdev_wb_lock;\n\tspinlock_t s_error_lock;\n\tint s_add_error_count;\n\tint s_first_error_code;\n\t__u32 s_first_error_line;\n\t__u32 s_first_error_ino;\n\tlong: 32;\n\t__u64 s_first_error_block;\n\tconst char *s_first_error_func;\n\tlong: 32;\n\ttime64_t s_first_error_time;\n\tint s_last_error_code;\n\t__u32 s_last_error_line;\n\t__u32 s_last_error_ino;\n\tlong: 32;\n\t__u64 s_last_error_block;\n\tconst char *s_last_error_func;\n\tlong: 32;\n\ttime64_t s_last_error_time;\n\tstruct work_struct s_sb_upd_work;\n\tunsigned int s_awu_min;\n\tunsigned int s_awu_max;\n\tatomic_t s_fc_subtid;\n\tstruct list_head s_fc_q[2];\n\tstruct list_head s_fc_dentry_q[2];\n\tunsigned int s_fc_bytes;\n\tstruct mutex s_fc_lock;\n\tstruct buffer_head *s_fc_bh;\n\tlong: 32;\n\tstruct ext4_fc_stats s_fc_stats;\n\ttid_t s_fc_ineligible_tid;\n\tstruct ext4_fc_replay_state s_fc_replay_state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_orphan_file_inum;\n\t__le16 s_def_resuid_hi;\n\t__le16 s_def_resgid_hi;\n\t__le32 s_reserved[93];\n\t__le32 s_checksum;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\tlong: 32;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n\tu32 ino;\n};\n\nstruct ext4_tune_sb_params {\n\t__u32 set_flags;\n\t__u32 checkinterval;\n\t__u16 errors_behavior;\n\t__u16 mnt_count;\n\t__u16 max_mnt_count;\n\t__u16 raid_stride;\n\t__u64 last_check_time;\n\t__u64 reserved_blocks;\n\t__u64 blocks_count;\n\t__u32 default_mnt_opts;\n\t__u32 reserved_uid;\n\t__u32 reserved_gid;\n\t__u32 raid_stripe_width;\n\t__u16 encoding;\n\t__u16 encoding_flags;\n\t__u8 def_hash_alg;\n\t__u8 pad_1;\n\t__u16 pad_2;\n\t__u32 feature_compat;\n\t__u32 feature_incompat;\n\t__u32 feature_ro_compat;\n\t__u32 set_feature_compat_mask;\n\t__u32 set_feature_incompat_mask;\n\t__u32 set_feature_ro_compat_mask;\n\t__u32 clear_feature_compat_mask;\n\t__u32 clear_feature_incompat_mask;\n\t__u32 clear_feature_ro_compat_mask;\n\t__u8 mount_opts[64];\n\t__u8 pad[68];\n};\n\nstruct ext4_xattr_entry;\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tlong: 32;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tlong: 32;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n\tlong: 32;\n};\n\nstruct extcontext {\n\tunsigned int magic;\n\tunsigned int size;\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\tlong: 32;\n\text4_fsblk_t es_pblk;\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct f_format {\n\tunsigned int func: 6;\n\tunsigned int re: 5;\n\tunsigned int rd: 5;\n\tunsigned int rt: 5;\n\tunsigned int fmt: 4;\n\tchar: 1;\n\tunsigned int opcode: 6;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct failover_ops;\n\nstruct failover {\n\tstruct list_head list;\n\tstruct net_device *failover_dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct failover_ops *ops;\n};\n\nstruct failover_ops {\n\tint (*slave_pre_register)(struct net_device *, struct net_device *);\n\tint (*slave_register)(struct net_device *, struct net_device *);\n\tint (*slave_pre_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_link_change)(struct net_device *, struct net_device *);\n\tint (*slave_name_change)(struct net_device *, struct net_device *);\n\trx_handler_result_t (*slave_handle_frame)(struct sk_buff **);\n};\n\nstruct fan_fsid {\n\tstruct super_block *sb;\n\t__kernel_fsid_t id;\n\tbool weak;\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct fanotify_event {\n\tstruct fsnotify_event fse;\n\tstruct hlist_node merge_list;\n\tu32 mask;\n\tstruct {\n\t\tunsigned int type: 3;\n\t\tunsigned int hash: 29;\n\t};\n\tstruct pid *pid;\n};\n\nstruct fanotify_fh {\n\tu8 type;\n\tu8 len;\n\tu8 flags;\n\tu8 pad;\n};\n\nstruct fanotify_error_event {\n\tstruct fanotify_event fae;\n\ts32 error;\n\tu32 err_count;\n\t__kernel_fsid_t fsid;\n\tstruct {\n\t\tstruct fanotify_fh object_fh;\n\t\tunsigned char _inline_fh_buf[128];\n\t};\n};\n\nstruct fanotify_event_info_header {\n\t__u8 info_type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_event_info_error {\n\tstruct fanotify_event_info_header hdr;\n\t__s32 error;\n\t__u32 error_count;\n};\n\nstruct fanotify_event_info_fid {\n\tstruct fanotify_event_info_header hdr;\n\t__kernel_fsid_t fsid;\n\tunsigned char handle[0];\n};\n\nstruct fanotify_event_info_mnt {\n\tstruct fanotify_event_info_header hdr;\n\tlong: 32;\n\t__u64 mnt_id;\n};\n\nstruct fanotify_event_info_pidfd {\n\tstruct fanotify_event_info_header hdr;\n\t__s32 pidfd;\n};\n\nstruct fanotify_event_info_range {\n\tstruct fanotify_event_info_header hdr;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 count;\n};\n\nstruct fanotify_event_metadata {\n\t__u32 event_len;\n\t__u8 vers;\n\t__u8 reserved;\n\t__u16 metadata_len;\n\t__u64 mask;\n\t__s32 fd;\n\t__s32 pid;\n};\n\nstruct fanotify_fid_event {\n\tstruct fanotify_event fae;\n\t__kernel_fsid_t fsid;\n\tstruct {\n\t\tstruct fanotify_fh object_fh;\n\t\tunsigned char _inline_fh_buf[12];\n\t};\n};\n\nstruct fanotify_group_private_data {\n\tstruct hlist_head *merge_hash;\n\tstruct list_head access_list;\n\twait_queue_head_t access_waitq;\n\tint flags;\n\tint f_flags;\n\tstruct ucounts *ucounts;\n\tmempool_t error_events_pool;\n\tstruct list_head perm_grp_list;\n};\n\nstruct fanotify_info {\n\tu8 dir_fh_totlen;\n\tu8 dir2_fh_totlen;\n\tu8 file_fh_totlen;\n\tu8 name_len;\n\tu8 name2_len;\n\tu8 pad[3];\n\tunsigned char buf[0];\n};\n\nstruct fanotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\t__kernel_fsid_t fsid;\n};\n\nstruct fanotify_mnt_event {\n\tstruct fanotify_event fae;\n\tlong: 32;\n\tu64 mnt_id;\n};\n\nstruct fanotify_name_event {\n\tstruct fanotify_event fae;\n\t__kernel_fsid_t fsid;\n\tstruct fanotify_info info;\n};\n\nstruct fanotify_path_event {\n\tstruct fanotify_event fae;\n\tstruct path path;\n};\n\nstruct fanotify_response_info_header {\n\t__u8 type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_response_info_audit_rule {\n\tstruct fanotify_response_info_header hdr;\n\t__u32 rule_number;\n\t__u32 subj_trust;\n\t__u32 obj_trust;\n};\n\nstruct fanotify_perm_event {\n\tstruct fanotify_event fae;\n\tstruct path path;\n\tconst loff_t *ppos;\n\tsize_t count;\n\tu32 response;\n\tshort unsigned int state;\n\tshort unsigned int watchdog_cnt;\n\tint fd;\n\tpid_t recv_pid;\n\tunion {\n\t\tstruct fanotify_response_info_header hdr;\n\t\tstruct fanotify_response_info_audit_rule audit_rule;\n\t};\n};\n\nstruct fanotify_response {\n\t__s32 fd;\n\t__u32 response;\n};\n\nstruct fanout_args {\n\t__u16 id;\n\t__u16 type_flags;\n\t__u32 max_num_members;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_bios_param_block {\n\tu16 fat_sector_size;\n\tu8 fat_sec_per_clus;\n\tu16 fat_reserved;\n\tu8 fat_fats;\n\tu16 fat_dir_entries;\n\tu16 fat_sectors;\n\tu16 fat_fat_length;\n\tu32 fat_total_sect;\n\tu8 fat16_state;\n\tu32 fat16_vol_id;\n\tu32 fat32_length;\n\tu32 fat32_root_cluster;\n\tu16 fat32_info_sector;\n\tu8 fat32_state;\n\tu32 fat32_vol_id;\n};\n\nstruct fat_boot_fsinfo {\n\t__le32 signature1;\n\t__le32 reserved1[120];\n\t__le32 signature2;\n\t__le32 free_clusters;\n\t__le32 next_cluster;\n\t__le32 reserved2[4];\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fat_cache {\n\tstruct list_head cache_list;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_cache_id {\n\tunsigned int id;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_entry {\n\tint entry;\n\tunion {\n\t\tu8 *ent12_p[2];\n\t\t__le16 *ent16_p;\n\t\t__le32 *ent32_p;\n\t} u;\n\tint nr_bhs;\n\tstruct buffer_head *bhs[2];\n\tstruct inode *fat_inode;\n};\n\nstruct fat_fid {\n\tu32 i_gen;\n\tu32 i_pos_low;\n\tu16 i_pos_hi;\n\tu16 parent_i_pos_hi;\n\tu32 parent_i_pos_low;\n\tu32 parent_i_gen;\n};\n\nstruct fat_floppy_defaults {\n\tunsigned int nr_sectors;\n\tunsigned int sec_per_clus;\n\tunsigned int dir_entries;\n\tunsigned int media;\n\tunsigned int fat_length;\n};\n\nstruct fat_ioctl_filldir_callback {\n\tstruct dir_context ctx;\n\tvoid *dirent;\n\tint result;\n\tconst char *longname;\n\tint long_len;\n\tconst char *shortname;\n\tint short_len;\n};\n\nstruct fat_mount_options {\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tshort unsigned int fs_fmask;\n\tshort unsigned int fs_dmask;\n\tshort unsigned int codepage;\n\tint time_offset;\n\tchar *iocharset;\n\tshort unsigned int shortname;\n\tunsigned char name_check;\n\tunsigned char errors;\n\tunsigned char nfs;\n\tshort unsigned int allow_utime;\n\tunsigned int quiet: 1;\n\tunsigned int showexec: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int dotsOK: 1;\n\tunsigned int isvfat: 1;\n\tunsigned int utf8: 1;\n\tunsigned int unicode_xlate: 1;\n\tunsigned int numtail: 1;\n\tunsigned int flush: 1;\n\tunsigned int nocase: 1;\n\tunsigned int usefree: 1;\n\tunsigned int tz_set: 1;\n\tunsigned int rodir: 1;\n\tunsigned int discard: 1;\n\tunsigned int dos1xfloppy: 1;\n\tunsigned int debug: 1;\n};\n\nstruct msdos_dir_entry;\n\nstruct fat_slot_info {\n\tloff_t i_pos;\n\tloff_t slot_off;\n\tint nr_slots;\n\tstruct msdos_dir_entry *de;\n\tstruct buffer_head *bh;\n\tlong: 32;\n};\n\nstruct fatent_operations {\n\tvoid (*ent_blocknr)(struct super_block *, int, int *, sector_t *);\n\tvoid (*ent_set_ptr)(struct fat_entry *, int);\n\tint (*ent_bread)(struct super_block *, struct fat_entry *, int, sector_t);\n\tint (*ent_get)(struct fat_entry *);\n\tvoid (*ent_put)(struct fat_entry *, int);\n\tint (*ent_next)(struct fat_entry *);\n};\n\nstruct fatent_ra {\n\tsector_t cur;\n\tsector_t limit;\n\tunsigned int ra_blocks;\n\tlong: 32;\n\tsector_t ra_advance;\n\tsector_t ra_next;\n\tsector_t ra_limit;\n};\n\nstruct fault_attr {};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_address {\n\tvoid *address;\n\tint bits;\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_bitmap4x_iter {\n\tconst u8 *data;\n\tu32 fgxcolor;\n\tu32 bgcolor;\n\tint width;\n\tint i;\n\tconst u32 *expand;\n\tint bpp;\n\tbool top;\n};\n\nstruct fb_bitmap_iter {\n\tconst u8 *data;\n\tlong unsigned int colors[2];\n\tint width;\n\tint i;\n};\n\nstruct fb_blit_caps {\n\tlong unsigned int x[2];\n\tlong unsigned int y[4];\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_reverse {\n\tbool byte;\n\tbool pixel;\n};\n\nstruct fb_color_iter {\n\tconst u8 *data;\n\tconst u32 *palette;\n\tstruct fb_reverse reverse;\n\tint shift;\n\tint width;\n\tint i;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_format {\n\tint simmediate: 16;\n\tunsigned int flag: 2;\n\tunsigned int cc: 3;\n\tunsigned int bc: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_videomode;\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_info;\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tlong unsigned int blit_x[2];\n\tlong unsigned int blit_y[4];\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct fbcon_par;\n\nstruct lcd_device;\n\nstruct fb_ops;\n\nstruct fb_info {\n\trefcount_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tint blank;\n\tstruct lcd_device *lcd_dev;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tstruct device *dev;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tstruct fbcon_par *fbcon_par;\n\tvoid *par;\n\tbool skip_vt_switch;\n\tbool skip_panic;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n};\n\nstruct fb_pattern {\n\tlong unsigned int pixels;\n\tint left;\n\tint right;\n\tstruct fb_reverse reverse;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdt_errtabent {\n\tconst char *str;\n};\n\nstruct fdt_header {\n\tfdt32_t magic;\n\tfdt32_t totalsize;\n\tfdt32_t off_dt_struct;\n\tfdt32_t off_dt_strings;\n\tfdt32_t off_mem_rsvmap;\n\tfdt32_t version;\n\tfdt32_t last_comp_version;\n\tfdt32_t boot_cpuid_phys;\n\tfdt32_t size_dt_strings;\n\tfdt32_t size_dt_struct;\n};\n\nstruct fdt_node_header {\n\tfdt32_t tag;\n\tchar name[0];\n};\n\nstruct fdt_property {\n\tfdt32_t tag;\n\tfdt32_t len;\n\tfdt32_t nameoff;\n\tchar data[0];\n};\n\nstruct fdt_reserve_entry {\n\tfdt64_t address;\n\tfdt64_t size;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n\tlong: 32;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[4];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tlong: 32;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[4];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct fib6_node;\n\nstruct fib6_walker {\n\tstruct list_head lh;\n\tstruct fib6_node *root;\n\tstruct fib6_node *node;\n\tstruct fib6_info *leaf;\n\tenum fib6_walk_state state;\n\tunsigned int skip;\n\tunsigned int count;\n\tunsigned int skip_in_node;\n\tint (*func)(struct fib6_walker *);\n\tvoid *args;\n};\n\nstruct fib6_cleaner {\n\tstruct fib6_walker w;\n\tstruct net *net;\n\tint (*func)(struct fib6_info *, void *);\n\tint sernum;\n\tvoid *arg;\n\tbool skip_notify;\n};\n\nstruct nlmsghdr;\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct fib6_dump_arg {\n\tstruct net *net;\n\tstruct notifier_block *nb;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib6_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib6_info *rt;\n\tunsigned int nsiblings;\n};\n\nstruct fib6_gc_args {\n\tint timeout;\n\tint more;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_nh_age_excptn_arg {\n\tstruct fib6_gc_args *gc_args;\n\tlong unsigned int now;\n};\n\nstruct fib6_nh_del_cached_rt_arg {\n\tstruct fib6_config *cfg;\n\tstruct fib6_info *f6i;\n};\n\nstruct fib6_nh_dm_arg {\n\tstruct net *net;\n\tconst struct in6_addr *saddr;\n\tint oif;\n\tint flags;\n\tstruct fib6_nh *nh;\n};\n\nstruct rt6_rtnl_dump_arg;\n\nstruct fib6_nh_exception_dump_walker {\n\tstruct rt6_rtnl_dump_arg *dump;\n\tstruct fib6_info *rt;\n\tunsigned int flags;\n\tunsigned int skip;\n\tunsigned int count;\n};\n\nstruct fib6_nh_excptn_arg {\n\tstruct rt6_info *rt;\n\tint plen;\n};\n\nstruct fib6_nh_frl_arg {\n\tu32 flags;\n\tint oif;\n\tint strict;\n\tint *mpri;\n\tbool *do_rr;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_match_arg {\n\tconst struct net_device *dev;\n\tconst struct in6_addr *gw;\n\tstruct fib6_nh *match;\n};\n\nstruct fib6_result;\n\nstruct flowi6;\n\nstruct fib6_nh_rd_arg {\n\tstruct fib6_result *res;\n\tstruct flowi6 *fl6;\n\tconst struct in6_addr *gw;\n\tstruct rt6_info **ret;\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tlong: 32;\n\tloff_t pos;\n\tt_key key;\n\tlong: 32;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct io_uring_cmd;\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct file_range {\n\tconst struct path *path;\n\tlong: 32;\n\tloff_t pos;\n\tsize_t count;\n\tlong: 32;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[180];\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[32];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct find_interface_arg {\n\tint minor;\n\tstruct device_driver *drv;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\nstruct fixed_dev_type {\n\tbool has_enable_clock;\n\tbool has_performance_state;\n};\n\nstruct fixed_partitions_quirks {\n\tint (*post_parse)(struct mtd_info *, struct mtd_partition *, int);\n};\n\nstruct fixed_phy_status {\n\tint speed;\n\tint duplex;\n\tbool link: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n};\n\nstruct fixed_phy {\n\tstruct phy_device *phydev;\n\tstruct fixed_phy_status status;\n\tint (*link_update)(struct net_device *, struct fixed_phy_status *);\n};\n\nstruct regulator_init_data;\n\nstruct fixed_voltage_config {\n\tconst char *supply_name;\n\tconst char *input_supply;\n\tint microvolts;\n\tunsigned int startup_delay;\n\tunsigned int off_on_delay;\n\tunsigned int enabled_at_boot: 1;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct regulator_state {\n\tint uV;\n\tint min_uV;\n\tint max_uV;\n\tunsigned int mode;\n\tint enabled;\n\tbool changeable;\n};\n\nstruct notification_limit {\n\tint prot;\n\tint err;\n\tint warn;\n};\n\nstruct regulation_constraints {\n\tconst char *name;\n\tint min_uV;\n\tint max_uV;\n\tint uV_offset;\n\tint min_uA;\n\tint max_uA;\n\tint ilim_uA;\n\tint pw_budget_mW;\n\tint system_load;\n\tu32 *max_spread;\n\tint max_uV_step;\n\tunsigned int valid_modes_mask;\n\tunsigned int valid_ops_mask;\n\tint input_uV;\n\tstruct regulator_state state_disk;\n\tstruct regulator_state state_mem;\n\tstruct regulator_state state_standby;\n\tstruct notification_limit over_curr_limits;\n\tstruct notification_limit over_voltage_limits;\n\tstruct notification_limit under_voltage_limits;\n\tstruct notification_limit temp_limits;\n\tsuspend_state_t initial_state;\n\tunsigned int initial_mode;\n\tunsigned int ramp_delay;\n\tunsigned int settling_time;\n\tunsigned int settling_time_up;\n\tunsigned int settling_time_down;\n\tunsigned int enable_time;\n\tunsigned int uv_less_critical_window_ms;\n\tunsigned int active_discharge;\n\tunsigned int always_on: 1;\n\tunsigned int boot_on: 1;\n\tunsigned int apply_uV: 1;\n\tunsigned int ramp_disable: 1;\n\tunsigned int soft_start: 1;\n\tunsigned int pull_down: 1;\n\tunsigned int system_critical: 1;\n\tunsigned int over_current_protection: 1;\n\tunsigned int over_current_detection: 1;\n\tunsigned int over_voltage_detection: 1;\n\tunsigned int under_voltage_detection: 1;\n\tunsigned int over_temp_detection: 1;\n};\n\nstruct regulator_consumer_supply;\n\nstruct regulator_init_data {\n\tconst char *supply_regulator;\n\tstruct regulation_constraints constraints;\n\tint num_consumer_supplies;\n\tstruct regulator_consumer_supply *consumer_supplies;\n\tvoid *driver_data;\n};\n\nstruct mfd_cell;\n\nstruct pdev_archdata {};\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tlong: 32;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct fixed_regulator_data {\n\tstruct fixed_voltage_config cfg;\n\tstruct regulator_init_data init_data;\n\tlong: 32;\n\tstruct platform_device pdev;\n};\n\nstruct regulator_config;\n\nstruct regulator_ops;\n\nstruct linear_range;\n\nstruct regulator_desc {\n\tconst char *name;\n\tconst char *supply_name;\n\tconst char *of_match;\n\tbool of_match_full_name;\n\tconst char *regulators_node;\n\tint (*of_parse_cb)(struct device_node *, const struct regulator_desc *, struct regulator_config *);\n\tint (*init_cb)(struct regulator_dev *, struct regulator_config *);\n\tint id;\n\tunsigned int continuous_voltage_range: 1;\n\tunsigned int n_voltages;\n\tunsigned int n_current_limits;\n\tconst struct regulator_ops *ops;\n\tint irq;\n\tenum regulator_type type;\n\tstruct module *owner;\n\tunsigned int min_uV;\n\tunsigned int uV_step;\n\tunsigned int linear_min_sel;\n\tint fixed_uV;\n\tunsigned int ramp_delay;\n\tint min_dropout_uV;\n\tconst struct linear_range *linear_ranges;\n\tconst unsigned int *linear_range_selectors_bitfield;\n\tint n_linear_ranges;\n\tconst unsigned int *volt_table;\n\tconst unsigned int *curr_table;\n\tunsigned int vsel_range_reg;\n\tunsigned int vsel_range_mask;\n\tbool range_applied_by_vsel;\n\tunsigned int vsel_reg;\n\tunsigned int vsel_mask;\n\tunsigned int vsel_step;\n\tunsigned int csel_reg;\n\tunsigned int csel_mask;\n\tunsigned int apply_reg;\n\tunsigned int apply_bit;\n\tunsigned int enable_reg;\n\tunsigned int enable_mask;\n\tunsigned int enable_val;\n\tunsigned int disable_val;\n\tbool enable_is_inverted;\n\tunsigned int bypass_reg;\n\tunsigned int bypass_mask;\n\tunsigned int bypass_val_on;\n\tunsigned int bypass_val_off;\n\tunsigned int active_discharge_on;\n\tunsigned int active_discharge_off;\n\tunsigned int active_discharge_mask;\n\tunsigned int active_discharge_reg;\n\tunsigned int soft_start_reg;\n\tunsigned int soft_start_mask;\n\tunsigned int soft_start_val_on;\n\tunsigned int pull_down_reg;\n\tunsigned int pull_down_mask;\n\tunsigned int pull_down_val_on;\n\tunsigned int ramp_reg;\n\tunsigned int ramp_mask;\n\tconst unsigned int *ramp_delay_table;\n\tunsigned int n_ramp_values;\n\tunsigned int enable_time;\n\tunsigned int off_on_delay;\n\tunsigned int poll_enabled_time;\n\tunsigned int (*of_map_mode)(unsigned int);\n};\n\nstruct fixed_voltage_data {\n\tstruct regulator_desc desc;\n\tstruct regulator_dev *dev;\n\tstruct clk *enable_clock;\n\tunsigned int enable_counter;\n\tint performance_state;\n};\n\nstruct spi_nor_id;\n\nstruct spi_nor_otp_organization;\n\nstruct spi_nor_fixups;\n\nstruct flash_info {\n\tchar *name;\n\tconst struct spi_nor_id *id;\n\tsize_t size;\n\tunsigned int sector_size;\n\tu16 page_size;\n\tu8 n_banks;\n\tu8 addr_nbytes;\n\tu16 flags;\n\tu8 no_sfdp_flags;\n\tu8 fixup_flags;\n\tu8 mfr_flags;\n\tconst struct spi_nor_otp_organization *otp;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct flash_platform_data {\n\tchar *name;\n\tstruct mtd_partition *parts;\n\tunsigned int nr_parts;\n\tchar *type;\n};\n\nstruct flchip_shared {\n\tstruct mutex lock;\n\tstruct flchip *writing;\n\tstruct flchip *erasing;\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n\tlong int l_sysid;\n\tlong int pad[4];\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\tlong: 32;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n\tlong: 32;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct psample_group;\n\nstruct nf_flowtable;\n\nstruct action_gate_entry;\n\nstruct ip_tunnel_info;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tlong: 32;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tlong: 32;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tlong: 32;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n\tlong: 32;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tlong: 32;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_cls_common_offload {\n\tu32 chain_index;\n\t__be16 protocol;\n\tu32 prio;\n\tbool skip_sw;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct flow_cls_offload {\n\tstruct flow_cls_common_offload common;\n\tenum flow_cls_command command;\n\tbool use_act_stats;\n\tlong unsigned int cookie;\n\tstruct flow_rule *rule;\n\tlong: 32;\n\tstruct flow_stats stats;\n\tu32 classid;\n\tlong: 32;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 32;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tlong: 32;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tlong: 32;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n\tlong: 32;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n\tlong: 32;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct flush_cache_page_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int addr;\n\tlong unsigned int pfn;\n};\n\nstruct flush_icache_range_args {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int type;\n\tbool user;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct flush_kernel_vmap_range_args {\n\tlong unsigned int vaddr;\n\tint size;\n};\n\nstruct flush_tlb_data {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int addr1;\n\tlong unsigned int addr2;\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nstruct page_pool;\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t\tlong unsigned int memcg_data;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t\tunsigned int _nr_pages;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t\tatomic_t _entire_mapcount;\n\t\t\tatomic_t _pincount;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct mem_cgroup;\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fp0_format {\n\tunsigned int func: 6;\n\tunsigned int fd: 5;\n\tunsigned int fs: 5;\n\tunsigned int ft: 5;\n\tunsigned int fmt: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct fp1_format {\n\tunsigned int func: 6;\n\tunsigned int fd: 5;\n\tunsigned int fs: 5;\n\tunsigned int rt: 5;\n\tunsigned int op: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct fp6_format {\n\tunsigned int func: 6;\n\tunsigned int fd: 5;\n\tunsigned int fs: 5;\n\tunsigned int ft: 5;\n\tunsigned int fr: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\nunion fpureg {\n\t__u32 val32[2];\n\t__u64 val64[1];\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct rhashtable rhashtable;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct frag_queue {\n\tstruct inet_frag_queue q;\n\tint iif;\n\t__u16 nhoffset;\n\tu8 ecn;\n};\n\nstruct free_area {\n\tstruct list_head free_list[4];\n\tlong unsigned int nr_free;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n\tlong: 32;\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tlong: 32;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fscache_cache_ops;\n\nstruct fscache_cache {\n\tconst struct fscache_cache_ops *ops;\n\tstruct list_head cache_link;\n\tvoid *cache_priv;\n\trefcount_t ref;\n\tatomic_t n_volumes;\n\tatomic_t n_accesses;\n\tatomic_t object_count;\n\tunsigned int debug_id;\n\tenum fscache_cache_state state;\n\tchar *name;\n};\n\nstruct fscache_volume;\n\nstruct fscache_cookie;\n\nstruct netfs_cache_resources;\n\nstruct fscache_cache_ops {\n\tconst char *name;\n\tvoid (*acquire_volume)(struct fscache_volume *);\n\tvoid (*free_volume)(struct fscache_volume *);\n\tbool (*lookup_cookie)(struct fscache_cookie *);\n\tvoid (*withdraw_cookie)(struct fscache_cookie *);\n\tvoid (*resize_cookie)(struct netfs_cache_resources *, loff_t);\n\tbool (*invalidate_cookie)(struct fscache_cookie *);\n\tbool (*begin_operation)(struct netfs_cache_resources *, enum fscache_want_state);\n\tvoid (*prepare_to_write)(struct fscache_cookie *);\n};\n\nstruct fscache_cookie {\n\trefcount_t ref;\n\tatomic_t n_active;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n\tspinlock_t lock;\n\tstruct fscache_volume *volume;\n\tvoid *cache_priv;\n\tstruct hlist_bl_node hash_link;\n\tstruct list_head proc_link;\n\tstruct list_head commit_link;\n\tstruct work_struct work;\n\tloff_t object_size;\n\tlong unsigned int unused_at;\n\tlong unsigned int flags;\n\tenum fscache_cookie_state state;\n\tu8 advice;\n\tu8 key_len;\n\tu8 aux_len;\n\tu32 key_hash;\n\tunion {\n\t\tvoid *key;\n\t\tu8 inline_key[16];\n\t};\n\tunion {\n\t\tvoid *aux;\n\t\tu8 inline_aux[8];\n\t};\n};\n\nstruct fscache_volume {\n\trefcount_t ref;\n\tatomic_t n_cookies;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int key_hash;\n\tu8 *key;\n\tstruct list_head proc_link;\n\tstruct hlist_bl_node hash_link;\n\tstruct work_struct work;\n\tstruct fscache_cache *cache;\n\tvoid *cache_priv;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu8 coherency_len;\n\tu8 coherency[0];\n};\n\nstruct fscrypt_key_specifier {\n\t__u32 type;\n\t__u32 __reserved;\n\tunion {\n\t\t__u8 __reserved[32];\n\t\t__u8 descriptor[8];\n\t\t__u8 identifier[16];\n\t} u;\n};\n\nstruct fscrypt_add_key_arg {\n\tstruct fscrypt_key_specifier key_spec;\n\t__u32 raw_size;\n\t__u32 key_id;\n\t__u32 flags;\n\t__u32 __reserved[7];\n\t__u8 raw[0];\n};\n\nstruct fscrypt_context_v1 {\n\tu8 version;\n\tu8 contents_encryption_mode;\n\tu8 filenames_encryption_mode;\n\tu8 flags;\n\tu8 master_key_descriptor[8];\n\tu8 nonce[16];\n};\n\nstruct fscrypt_context_v2 {\n\tu8 version;\n\tu8 contents_encryption_mode;\n\tu8 filenames_encryption_mode;\n\tu8 flags;\n\tu8 log2_data_unit_size;\n\tu8 __reserved[3];\n\tu8 master_key_identifier[16];\n\tu8 nonce[16];\n};\n\nunion fscrypt_context {\n\tu8 version;\n\tstruct fscrypt_context_v1 v1;\n\tstruct fscrypt_context_v2 v2;\n};\n\nstruct fscrypt_prepared_key {\n\tstruct crypto_sync_skcipher *tfm;\n};\n\nstruct fscrypt_mode;\n\nstruct fscrypt_direct_key {\n\tstruct super_block *dk_sb;\n\tstruct hlist_node dk_node;\n\trefcount_t dk_refcount;\n\tconst struct fscrypt_mode *dk_mode;\n\tstruct fscrypt_prepared_key dk_key;\n\tu8 dk_descriptor[8];\n\tu8 dk_raw[64];\n};\n\nstruct fscrypt_get_key_status_arg {\n\tstruct fscrypt_key_specifier key_spec;\n\t__u32 __reserved[6];\n\t__u32 status;\n\t__u32 status_flags;\n\t__u32 user_count;\n\t__u32 __out_reserved[13];\n};\n\nstruct fscrypt_policy_v1 {\n\t__u8 version;\n\t__u8 contents_encryption_mode;\n\t__u8 filenames_encryption_mode;\n\t__u8 flags;\n\t__u8 master_key_descriptor[8];\n};\n\nstruct fscrypt_policy_v2 {\n\t__u8 version;\n\t__u8 contents_encryption_mode;\n\t__u8 filenames_encryption_mode;\n\t__u8 flags;\n\t__u8 log2_data_unit_size;\n\t__u8 __reserved[3];\n\t__u8 master_key_identifier[16];\n};\n\nstruct fscrypt_get_policy_ex_arg {\n\t__u64 policy_size;\n\tunion {\n\t\t__u8 version;\n\t\tstruct fscrypt_policy_v1 v1;\n\t\tstruct fscrypt_policy_v2 v2;\n\t} policy;\n};\n\nunion fscrypt_policy {\n\tu8 version;\n\tstruct fscrypt_policy_v1 v1;\n\tstruct fscrypt_policy_v2 v2;\n};\n\nstruct fscrypt_master_key;\n\nstruct fscrypt_inode_info {\n\tstruct fscrypt_prepared_key ci_enc_key;\n\tu8 ci_owns_key: 1;\n\tu8 ci_dirhash_key_initialized: 1;\n\tu8 ci_data_unit_bits;\n\tu8 ci_data_units_per_block_bits;\n\tu32 ci_hashed_ino;\n\tstruct fscrypt_mode *ci_mode;\n\tstruct inode *ci_inode;\n\tstruct fscrypt_master_key *ci_master_key;\n\tstruct list_head ci_master_key_link;\n\tstruct fscrypt_direct_key *ci_direct_key;\n\tlong: 32;\n\tsiphash_key_t ci_dirhash_key;\n\tunion fscrypt_policy ci_policy;\n\tu8 ci_nonce[16];\n};\n\nunion fscrypt_iv {\n\tstruct {\n\t\t__le64 index;\n\t\tu8 nonce[16];\n\t};\n\tu8 raw[32];\n\t__le64 dun[4];\n};\n\nstruct fscrypt_key {\n\t__u32 mode;\n\t__u8 raw[64];\n\t__u32 size;\n};\n\nstruct fscrypt_keyring {\n\tspinlock_t lock;\n\tstruct hlist_head key_hashtable[128];\n};\n\nstruct hmac_sha512_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct fscrypt_master_key_secret {\n\tstruct hmac_sha512_key hkdf;\n\tbool is_hw_wrapped;\n\tu32 size;\n\tu8 bytes[128];\n};\n\nstruct fscrypt_master_key {\n\tstruct hlist_node mk_node;\n\tstruct rw_semaphore mk_sem;\n\trefcount_t mk_active_refs;\n\trefcount_t mk_struct_refs;\n\tstruct callback_head mk_rcu_head;\n\tlong: 32;\n\tstruct fscrypt_master_key_secret mk_secret;\n\tstruct fscrypt_key_specifier mk_spec;\n\tstruct key *mk_users;\n\tstruct list_head mk_decrypted_inodes;\n\tspinlock_t mk_decrypted_inodes_lock;\n\tstruct fscrypt_prepared_key mk_direct_keys[11];\n\tstruct fscrypt_prepared_key mk_iv_ino_lblk_64_keys[11];\n\tstruct fscrypt_prepared_key mk_iv_ino_lblk_32_keys[11];\n\tlong: 32;\n\tsiphash_key_t mk_ino_hash_key;\n\tbool mk_ino_hash_key_initialized;\n\tbool mk_present;\n\tlong: 32;\n};\n\nstruct fscrypt_mode {\n\tconst char *friendly_name;\n\tconst char *cipher_str;\n\tint keysize;\n\tint security_strength;\n\tint ivsize;\n\tint logged_cryptoapi_impl;\n\tint logged_blk_crypto_native;\n\tint logged_blk_crypto_fallback;\n\tenum blk_crypto_mode_num blk_crypto_mode;\n};\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_nokey_name;\n};\n\nstruct fscrypt_nokey_name {\n\tu32 dirhash[2];\n\tu8 bytes[149];\n\tu8 sha256[32];\n};\n\nstruct fscrypt_operations {\n\tptrdiff_t inode_info_offs;\n\tunsigned int needs_bounce_pages: 1;\n\tunsigned int has_32bit_inodes: 1;\n\tunsigned int supports_subblock_data_units: 1;\n\tconst char *legacy_key_prefix;\n\tint (*get_context)(struct inode *, void *, size_t);\n\tint (*set_context)(struct inode *, const void *, size_t, void *);\n\tconst union fscrypt_policy * (*get_dummy_policy)(struct super_block *);\n\tbool (*empty_dir)(struct inode *);\n\tbool (*has_stable_inodes)(struct super_block *);\n\tstruct block_device ** (*get_devices)(struct super_block *, unsigned int *);\n};\n\nstruct fscrypt_provisioning_key_payload {\n\t__u32 type;\n\t__u32 flags;\n\t__u8 raw[0];\n};\n\nstruct fscrypt_remove_key_arg {\n\tstruct fscrypt_key_specifier key_spec;\n\t__u32 removal_status_flags;\n\t__u32 __reserved[5];\n};\n\nstruct fscrypt_symlink_data {\n\t__le16 len;\n\tchar encrypted_path[0];\n};\n\nstruct fscrypt_zero_done {\n\tatomic_t pending;\n\tblk_status_t status;\n\tstruct completion done;\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\ntypedef struct fsnotify_group *class_fsnotify_group_t;\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t\tstruct fanotify_group_private_data fanotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tlong: 32;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct fsuuid {\n\t__u32 fsu_len;\n\t__u32 fsu_flags;\n\t__u8 fsu_uuid[0];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsverity_digest {\n\t__u16 digest_algorithm;\n\t__u16 digest_size;\n\t__u8 digest[0];\n};\n\nstruct fsverity_enable_arg {\n\t__u32 version;\n\t__u32 hash_algorithm;\n\t__u32 block_size;\n\t__u32 salt_size;\n\t__u64 salt_ptr;\n\t__u32 sig_size;\n\t__u32 __reserved1;\n\t__u64 sig_ptr;\n\t__u64 __reserved2[11];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct pinfunction;\n\nstruct function_desc {\n\tconst struct pinfunction *func;\n\tvoid *data;\n};\n\nstruct fuse_access_in {\n\tuint32_t mask;\n\tuint32_t padding;\n};\n\nstruct fuse_attr {\n\tuint64_t ino;\n\tuint64_t size;\n\tuint64_t blocks;\n\tuint64_t atime;\n\tuint64_t mtime;\n\tuint64_t ctime;\n\tuint32_t atimensec;\n\tuint32_t mtimensec;\n\tuint32_t ctimensec;\n\tuint32_t mode;\n\tuint32_t nlink;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t rdev;\n\tuint32_t blksize;\n\tuint32_t flags;\n};\n\nstruct fuse_attr_out {\n\tuint64_t attr_valid;\n\tuint32_t attr_valid_nsec;\n\tuint32_t dummy;\n\tstruct fuse_attr attr;\n};\n\nstruct fuse_backing {\n\tstruct file *file;\n\tstruct cred *cred;\n\trefcount_t count;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_backing_map {\n\tint32_t fd;\n\tuint32_t flags;\n\tuint64_t padding;\n};\n\nstruct fuse_batch_forget_in {\n\tuint32_t count;\n\tuint32_t dummy;\n};\n\nstruct fuse_bmap_in {\n\tuint64_t block;\n\tuint32_t blocksize;\n\tuint32_t padding;\n};\n\nstruct fuse_bmap_out {\n\tuint64_t block;\n};\n\nstruct fuse_copy_file_range_in {\n\tuint64_t fh_in;\n\tuint64_t off_in;\n\tuint64_t nodeid_out;\n\tuint64_t fh_out;\n\tuint64_t off_out;\n\tuint64_t len;\n\tuint64_t flags;\n};\n\nstruct fuse_copy_file_range_out {\n\tuint64_t bytes_copied;\n};\n\nstruct fuse_req;\n\nstruct pipe_buffer;\n\nstruct fuse_copy_state {\n\tstruct fuse_req *req;\n\tstruct iov_iter *iter;\n\tstruct pipe_buffer *pipebufs;\n\tstruct pipe_buffer *currbuf;\n\tstruct pipe_inode_info *pipe;\n\tlong unsigned int nr_segs;\n\tstruct page *pg;\n\tunsigned int len;\n\tunsigned int offset;\n\tbool write: 1;\n\tbool move_folios: 1;\n\tbool is_uring: 1;\n\tstruct {\n\t\tunsigned int copied_sz;\n\t} ring;\n};\n\nstruct fuse_create_in {\n\tuint32_t flags;\n\tuint32_t mode;\n\tuint32_t umask;\n\tuint32_t open_flags;\n};\n\nstruct fuse_dentry {\n\tu64 time;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rb_node node;\n\t};\n\tstruct dentry *dentry;\n};\n\nstruct fuse_pqueue {\n\tunsigned int connected;\n\tspinlock_t lock;\n\tstruct list_head *processing;\n\tstruct list_head io;\n};\n\nstruct fuse_dev {\n\tstruct fuse_conn *fc;\n\tstruct fuse_pqueue pq;\n\tstruct list_head entry;\n};\n\nstruct fuse_dirent {\n\tuint64_t ino;\n\tuint64_t off;\n\tuint32_t namelen;\n\tuint32_t type;\n\tchar name[0];\n};\n\nstruct fuse_entry_out {\n\tuint64_t nodeid;\n\tuint64_t generation;\n\tuint64_t entry_valid;\n\tuint64_t attr_valid;\n\tuint32_t entry_valid_nsec;\n\tuint32_t attr_valid_nsec;\n\tstruct fuse_attr attr;\n};\n\nstruct fuse_direntplus {\n\tstruct fuse_entry_out entry_out;\n\tstruct fuse_dirent dirent;\n};\n\nstruct fuse_ext_header {\n\tuint32_t size;\n\tuint32_t type;\n};\n\nstruct fuse_fallocate_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint64_t length;\n\tuint32_t mode;\n\tuint32_t padding;\n};\n\nunion fuse_file_args;\n\nstruct fuse_file {\n\tstruct fuse_mount *fm;\n\tunion fuse_file_args *args;\n\tu64 kh;\n\tu64 fh;\n\tu64 nodeid;\n\trefcount_t count;\n\tu32 open_flags;\n\tstruct list_head write_entry;\n\tstruct {\n\t\tloff_t pos;\n\t\tloff_t cache_off;\n\t\tu64 version;\n\t} readdir;\n\tstruct rb_node polled_node;\n\twait_queue_head_t poll_wait;\n\tenum {\n\t\tIOM_NONE = 0,\n\t\tIOM_CACHED = 1,\n\t\tIOM_UNCACHED = 2,\n\t} iomode;\n\tstruct file *passthrough;\n\tconst struct cred *cred;\n\tbool flock: 1;\n};\n\nstruct fuse_open_out {\n\tuint64_t fh;\n\tuint32_t open_flags;\n\tint32_t backing_id;\n};\n\nstruct fuse_release_in {\n\tuint64_t fh;\n\tuint32_t flags;\n\tuint32_t release_flags;\n\tuint64_t lock_owner;\n};\n\nstruct fuse_release_args {\n\tstruct fuse_args args;\n\tstruct fuse_release_in inarg;\n\tstruct inode *inode;\n\tlong: 32;\n};\n\nunion fuse_file_args {\n\tstruct fuse_open_out open_outarg;\n\tstruct fuse_release_args release_args;\n};\n\nstruct fuse_file_lock {\n\tuint64_t start;\n\tuint64_t end;\n\tuint32_t type;\n\tuint32_t pid;\n};\n\nstruct fuse_io_args;\n\nstruct fuse_fill_read_data {\n\tstruct file *file;\n\tstruct fuse_conn *fc;\n\tstruct fuse_io_args *ia;\n\tunsigned int nr_bytes;\n};\n\nstruct fuse_writepage_args;\n\nstruct fuse_fill_wb_data {\n\tstruct fuse_writepage_args *wpa;\n\tstruct fuse_file *ff;\n\tunsigned int max_folios;\n\tunsigned int nr_bytes;\n};\n\nstruct fuse_flush_in {\n\tuint64_t fh;\n\tuint32_t unused;\n\tuint32_t padding;\n\tuint64_t lock_owner;\n};\n\nstruct fuse_forget_in {\n\tuint64_t nlookup;\n};\n\nstruct fuse_fs_context {\n\tint fd;\n\tstruct file *file;\n\tunsigned int rootmode;\n\tkuid_t user_id;\n\tkgid_t group_id;\n\tbool is_bdev: 1;\n\tbool fd_present: 1;\n\tbool rootmode_present: 1;\n\tbool user_id_present: 1;\n\tbool group_id_present: 1;\n\tbool default_permissions: 1;\n\tbool allow_other: 1;\n\tbool destroy: 1;\n\tbool no_control: 1;\n\tbool no_force_umount: 1;\n\tbool legacy_opts_show: 1;\n\tenum fuse_dax_mode dax_mode;\n\tunsigned int max_read;\n\tunsigned int blksize;\n\tconst char *subtype;\n\tstruct dax_device *dax_dev;\n\tvoid **fudptr;\n};\n\nstruct fuse_fsync_in {\n\tuint64_t fh;\n\tuint32_t fsync_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_getattr_in {\n\tuint32_t getattr_flags;\n\tuint32_t dummy;\n\tuint64_t fh;\n};\n\nstruct fuse_getxattr_in {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_getxattr_out {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_in_header {\n\tuint32_t len;\n\tuint32_t opcode;\n\tuint64_t unique;\n\tuint64_t nodeid;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t pid;\n\tuint16_t total_extlen;\n\tuint16_t padding;\n};\n\nstruct fuse_init_in {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t max_readahead;\n\tuint32_t flags;\n\tuint32_t flags2;\n\tuint32_t unused[11];\n};\n\nstruct fuse_init_out {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t max_readahead;\n\tuint32_t flags;\n\tuint16_t max_background;\n\tuint16_t congestion_threshold;\n\tuint32_t max_write;\n\tuint32_t time_gran;\n\tuint16_t max_pages;\n\tuint16_t map_alignment;\n\tuint32_t flags2;\n\tuint32_t max_stack_depth;\n\tuint16_t request_timeout;\n\tuint16_t unused[11];\n};\n\nstruct fuse_init_args {\n\tstruct fuse_args args;\n\tstruct fuse_init_in in;\n\tstruct fuse_init_out out;\n};\n\nstruct fuse_submount_lookup;\n\nstruct fuse_inode {\n\tstruct inode inode;\n\tu64 nodeid;\n\tu64 nlookup;\n\tstruct fuse_forget_link *forget;\n\tlong: 32;\n\tu64 i_time;\n\tu32 inval_mask;\n\tumode_t orig_i_mode;\n\tstruct timespec64 i_btime;\n\tu64 orig_ino;\n\tu64 attr_version;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head write_files;\n\t\t\tstruct list_head queued_writes;\n\t\t\tint writectr;\n\t\t\tint iocachectr;\n\t\t\twait_queue_head_t page_waitq;\n\t\t\twait_queue_head_t direct_io_waitq;\n\t\t};\n\t\tstruct {\n\t\t\tbool cached;\n\t\t\tlong: 32;\n\t\t\tloff_t size;\n\t\t\tloff_t pos;\n\t\t\tu64 version;\n\t\t\tstruct timespec64 mtime;\n\t\t\tu64 iversion;\n\t\t\tspinlock_t lock;\n\t\t\tlong: 32;\n\t\t} rdc;\n\t};\n\tlong unsigned int state;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tstruct fuse_submount_lookup *submount_lookup;\n\tstruct fuse_backing *fb;\n\tu8 cached_i_blkbits;\n\tlong: 32;\n};\n\nstruct fuse_inode_handle {\n\tu64 nodeid;\n\tu32 generation;\n\tlong: 32;\n};\n\nstruct fuse_interrupt_in {\n\tuint64_t unique;\n};\n\nstruct fuse_read_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t read_flags;\n\tuint64_t lock_owner;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_write_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t write_flags;\n\tuint64_t lock_owner;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_write_out {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_io_priv;\n\nstruct fuse_io_args {\n\tunion {\n\t\tstruct {\n\t\t\tstruct fuse_read_in in;\n\t\t\tu64 attr_ver;\n\t\t} read;\n\t\tstruct {\n\t\t\tstruct fuse_write_in in;\n\t\t\tstruct fuse_write_out out;\n\t\t\tbool folio_locked;\n\t\t\tlong: 32;\n\t\t} write;\n\t};\n\tstruct fuse_args_pages ap;\n\tstruct fuse_io_priv *io;\n\tstruct fuse_file *ff;\n};\n\nstruct fuse_io_priv {\n\tstruct kref refcnt;\n\tint async;\n\tspinlock_t lock;\n\tunsigned int reqs;\n\tssize_t bytes;\n\tsize_t size;\n\t__u64 offset;\n\tbool write;\n\tbool should_dirty;\n\tint err;\n\tstruct kiocb *iocb;\n\tstruct completion *done;\n\tbool blocking;\n\tlong: 32;\n};\n\nstruct fuse_ioctl_in {\n\tuint64_t fh;\n\tuint32_t flags;\n\tuint32_t cmd;\n\tuint64_t arg;\n\tuint32_t in_size;\n\tuint32_t out_size;\n};\n\nstruct fuse_ioctl_iovec {\n\tuint64_t base;\n\tuint64_t len;\n};\n\nstruct fuse_ioctl_out {\n\tint32_t result;\n\tuint32_t flags;\n\tuint32_t in_iovs;\n\tuint32_t out_iovs;\n};\n\nstruct fuse_iqueue_ops {\n\tvoid (*send_forget)(struct fuse_iqueue *, struct fuse_forget_link *);\n\tvoid (*send_interrupt)(struct fuse_iqueue *, struct fuse_req *);\n\tvoid (*send_req)(struct fuse_iqueue *, struct fuse_req *);\n\tvoid (*release)(struct fuse_iqueue *);\n};\n\nstruct fuse_kstatfs {\n\tuint64_t blocks;\n\tuint64_t bfree;\n\tuint64_t bavail;\n\tuint64_t files;\n\tuint64_t ffree;\n\tuint32_t bsize;\n\tuint32_t namelen;\n\tuint32_t frsize;\n\tuint32_t padding;\n\tuint32_t spare[6];\n};\n\nstruct fuse_link_in {\n\tuint64_t oldnodeid;\n};\n\nstruct fuse_lk_in {\n\tuint64_t fh;\n\tuint64_t owner;\n\tstruct fuse_file_lock lk;\n\tuint32_t lk_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_lk_out {\n\tstruct fuse_file_lock lk;\n};\n\nstruct fuse_lseek_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t whence;\n\tuint32_t padding;\n};\n\nstruct fuse_lseek_out {\n\tuint64_t offset;\n};\n\nstruct fuse_mkdir_in {\n\tuint32_t mode;\n\tuint32_t umask;\n};\n\nstruct fuse_mknod_in {\n\tuint32_t mode;\n\tuint32_t rdev;\n\tuint32_t umask;\n\tuint32_t padding;\n};\n\nstruct fuse_notify_delete_out {\n\tuint64_t parent;\n\tuint64_t child;\n\tuint32_t namelen;\n\tuint32_t padding;\n};\n\nstruct fuse_notify_inval_entry_out {\n\tuint64_t parent;\n\tuint32_t namelen;\n\tuint32_t flags;\n};\n\nstruct fuse_notify_inval_inode_out {\n\tuint64_t ino;\n\tint64_t off;\n\tint64_t len;\n};\n\nstruct fuse_notify_poll_wakeup_out {\n\tuint64_t kh;\n};\n\nstruct fuse_notify_prune_out {\n\tuint32_t count;\n\tuint32_t padding;\n\tuint64_t spare;\n};\n\nstruct fuse_notify_retrieve_in {\n\tuint64_t dummy1;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t dummy2;\n\tuint64_t dummy3;\n\tuint64_t dummy4;\n};\n\nstruct fuse_notify_retrieve_out {\n\tuint64_t notify_unique;\n\tuint64_t nodeid;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_notify_store_out {\n\tuint64_t nodeid;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_open_in {\n\tuint32_t flags;\n\tuint32_t open_flags;\n};\n\nstruct fuse_out_header {\n\tuint32_t len;\n\tint32_t error;\n\tuint64_t unique;\n};\n\nstruct fuse_poll_in {\n\tuint64_t fh;\n\tuint64_t kh;\n\tuint32_t flags;\n\tuint32_t events;\n};\n\nstruct fuse_poll_out {\n\tuint32_t revents;\n\tuint32_t padding;\n};\n\nstruct fuse_rename2_in {\n\tuint64_t newdir;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_req {\n\tstruct list_head list;\n\tstruct list_head intr_entry;\n\tstruct fuse_args *args;\n\trefcount_t count;\n\tlong unsigned int flags;\n\tlong: 32;\n\tstruct {\n\t\tstruct fuse_in_header h;\n\t} in;\n\tstruct {\n\t\tstruct fuse_out_header h;\n\t} out;\n\twait_queue_head_t waitq;\n\tstruct fuse_mount *fm;\n\tvoid *ring_entry;\n\tvoid *ring_queue;\n\tlong unsigned int create_time;\n\tlong: 32;\n};\n\nstruct fuse_retrieve_args {\n\tstruct fuse_args_pages ap;\n\tstruct fuse_notify_retrieve_in inarg;\n};\n\nstruct fuse_ring_queue;\n\nstruct fuse_ring {\n\tstruct fuse_conn *fc;\n\tsize_t nr_queues;\n\tsize_t max_payload_sz;\n\tstruct fuse_ring_queue **queues;\n\tunsigned int stop_debug_log: 1;\n\twait_queue_head_t stop_waitq;\n\tstruct delayed_work async_teardown_work;\n\tlong unsigned int teardown_time;\n\tatomic_t queue_refs;\n\tbool ready;\n};\n\nstruct fuse_uring_req_header;\n\nstruct fuse_ring_ent {\n\tstruct fuse_uring_req_header *headers;\n\tvoid *payload;\n\tstruct fuse_ring_queue *queue;\n\tstruct io_uring_cmd *cmd;\n\tstruct list_head list;\n\tenum fuse_ring_req_state state;\n\tstruct fuse_req *fuse_req;\n};\n\nstruct fuse_ring_queue {\n\tstruct fuse_ring *ring;\n\tunsigned int qid;\n\tspinlock_t lock;\n\tstruct list_head ent_avail_queue;\n\tstruct list_head ent_w_req_queue;\n\tstruct list_head ent_commit_queue;\n\tstruct list_head ent_in_userspace;\n\tstruct list_head ent_released;\n\tstruct list_head fuse_req_queue;\n\tstruct list_head fuse_req_bg_queue;\n\tstruct fuse_pqueue fpq;\n\tunsigned int active_background;\n\tbool stopped;\n};\n\nstruct fuse_secctx {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_secctx_header {\n\tuint32_t size;\n\tuint32_t nr_secctx;\n};\n\nstruct fuse_setattr_in {\n\tuint32_t valid;\n\tuint32_t padding;\n\tuint64_t fh;\n\tuint64_t size;\n\tuint64_t lock_owner;\n\tuint64_t atime;\n\tuint64_t mtime;\n\tuint64_t ctime;\n\tuint32_t atimensec;\n\tuint32_t mtimensec;\n\tuint32_t ctimensec;\n\tuint32_t mode;\n\tuint32_t unused4;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t unused5;\n};\n\nstruct fuse_setxattr_in {\n\tuint32_t size;\n\tuint32_t flags;\n\tuint32_t setxattr_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_statfs_out {\n\tstruct fuse_kstatfs st;\n};\n\nstruct fuse_sx_time {\n\tint64_t tv_sec;\n\tuint32_t tv_nsec;\n\tint32_t __reserved;\n};\n\nstruct fuse_statx {\n\tuint32_t mask;\n\tuint32_t blksize;\n\tuint64_t attributes;\n\tuint32_t nlink;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint16_t mode;\n\tuint16_t __spare0[1];\n\tuint64_t ino;\n\tuint64_t size;\n\tuint64_t blocks;\n\tuint64_t attributes_mask;\n\tstruct fuse_sx_time atime;\n\tstruct fuse_sx_time btime;\n\tstruct fuse_sx_time ctime;\n\tstruct fuse_sx_time mtime;\n\tuint32_t rdev_major;\n\tuint32_t rdev_minor;\n\tuint32_t dev_major;\n\tuint32_t dev_minor;\n\tuint64_t __spare2[14];\n};\n\nstruct fuse_statx_in {\n\tuint32_t getattr_flags;\n\tuint32_t reserved;\n\tuint64_t fh;\n\tuint32_t sx_flags;\n\tuint32_t sx_mask;\n};\n\nstruct fuse_statx_out {\n\tuint64_t attr_valid;\n\tuint32_t attr_valid_nsec;\n\tuint32_t flags;\n\tuint64_t spare[2];\n\tstruct fuse_statx stat;\n};\n\nstruct fuse_submount_lookup {\n\trefcount_t count;\n\tlong: 32;\n\tu64 nodeid;\n\tstruct fuse_forget_link *forget;\n\tlong: 32;\n};\n\nstruct fuse_supp_groups {\n\tuint32_t nr_groups;\n\tuint32_t groups[0];\n};\n\nstruct fuse_sync_bucket {\n\tatomic_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_syncfs_in {\n\tuint64_t padding;\n};\n\nstruct fuse_uring_cmd_req {\n\tuint64_t flags;\n\tuint64_t commit_id;\n\tuint16_t qid;\n\tuint8_t padding[6];\n};\n\nstruct fuse_uring_ent_in_out {\n\tuint64_t flags;\n\tuint64_t commit_id;\n\tuint32_t payload_sz;\n\tuint32_t padding;\n\tuint64_t reserved;\n};\n\nstruct fuse_uring_pdu {\n\tstruct fuse_ring_ent *ent;\n};\n\nstruct fuse_uring_req_header {\n\tchar in_out[128];\n\tchar op_in[128];\n\tstruct fuse_uring_ent_in_out ring_ent_in_out;\n};\n\nstruct fuse_writepage_args {\n\tstruct fuse_io_args ia;\n\tstruct list_head queue_entry;\n\tstruct inode *inode;\n\tstruct fuse_sync_bucket *bucket;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t\tlong: 32;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tlong: 32;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tsize_t offset;\n\tu32 opt_flags;\n\tconst char *fw_name;\n};\n\nstruct fwh_xxlock_thunk {\n\tenum fwh_lock_state val;\n\tflstate_t state;\n};\n\nunion fwnet_hwaddr {\n\tu8 u[16];\n\tstruct {\n\t\t__be64 uniq_id;\n\t\tu8 max_rec;\n\t\tu8 sspd;\n\t\tu8 fifo[6];\n\t} uc;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_reference_args;\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct gen_pool;\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tlong: 32;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[128];\n\t\tu8 data[512];\n\t};\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n\tlong: 32;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tlong: 32;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n\tlong: 32;\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct gf_poly {\n\tunsigned int deg;\n\tunsigned int c[0];\n};\n\nstruct gf_poly_deg1 {\n\tstruct gf_poly poly;\n\tunsigned int c[2];\n};\n\nstruct gic_all_vpes_chip_data {\n\tu32 map;\n\tbool mask;\n};\n\nstruct giveback_urb_bh {\n\tbool running;\n\tbool high_prio;\n\tspinlock_t lock;\n\tstruct list_head head;\n\tstruct work_struct bh;\n\tstruct usb_host_endpoint *completing_ep;\n};\n\nstruct mtd_ecc_stats {\n\t__u32 corrected;\n\t__u32 failed;\n\t__u32 badblocks;\n\t__u32 bbtblocks;\n};\n\nstruct mtd_debug_info {\n\tstruct dentry *dfs_dir;\n};\n\nstruct mtd_part {\n\tstruct list_head node;\n\tu64 offset;\n\tu64 size;\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct mtd_master {\n\tstruct mutex partitions_lock;\n\tstruct mutex chrdev_lock;\n\tunsigned int suspended: 1;\n};\n\nstruct mtd_ooblayout_ops;\n\nstruct mtd_pairing_scheme;\n\nstruct mtd_erase_region_info;\n\nstruct mtd_oob_ops;\n\nstruct otp_info;\n\nstruct nvmem_device;\n\nstruct mtd_info {\n\tu_char type;\n\tuint32_t flags;\n\tuint64_t size;\n\tuint32_t erasesize;\n\tuint32_t writesize;\n\tuint32_t writebufsize;\n\tuint32_t oobsize;\n\tuint32_t oobavail;\n\tunsigned int erasesize_shift;\n\tunsigned int writesize_shift;\n\tunsigned int erasesize_mask;\n\tunsigned int writesize_mask;\n\tunsigned int bitflip_threshold;\n\tconst char *name;\n\tint index;\n\tconst struct mtd_ooblayout_ops *ooblayout;\n\tconst struct mtd_pairing_scheme *pairing;\n\tunsigned int ecc_step_size;\n\tunsigned int ecc_strength;\n\tint numeraseregions;\n\tstruct mtd_erase_region_info *eraseregions;\n\tint (*_erase)(struct mtd_info *, struct erase_info *);\n\tint (*_point)(struct mtd_info *, loff_t, size_t, size_t *, void **, resource_size_t *);\n\tint (*_unpoint)(struct mtd_info *, loff_t, size_t);\n\tint (*_read)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_panic_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_read_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_write_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_get_fact_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_fact_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_get_user_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_lock_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_erase_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_writev)(struct mtd_info *, const struct kvec *, long unsigned int, loff_t, size_t *);\n\tvoid (*_sync)(struct mtd_info *);\n\tint (*_lock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_unlock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_is_locked)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_block_isreserved)(struct mtd_info *, loff_t);\n\tint (*_block_isbad)(struct mtd_info *, loff_t);\n\tint (*_block_markbad)(struct mtd_info *, loff_t);\n\tint (*_max_bad_blocks)(struct mtd_info *, loff_t, size_t);\n\tint (*_suspend)(struct mtd_info *);\n\tvoid (*_resume)(struct mtd_info *);\n\tvoid (*_reboot)(struct mtd_info *);\n\tint (*_get_device)(struct mtd_info *);\n\tvoid (*_put_device)(struct mtd_info *);\n\tbool oops_panic_write;\n\tstruct notifier_block reboot_notifier;\n\tstruct mtd_ecc_stats ecc_stats;\n\tint subpage_sft;\n\tvoid *priv;\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct kref refcnt;\n\tstruct mtd_debug_info dbg;\n\tstruct nvmem_device *nvmem;\n\tstruct nvmem_device *otp_user_nvmem;\n\tstruct nvmem_device *otp_factory_nvmem;\n\tstruct mtd_info *parent;\n\tstruct list_head partitions;\n\tstruct mtd_part part;\n\tstruct mtd_master master;\n\tlong: 32;\n};\n\nstruct ubi_volume_desc;\n\nstruct gluebi_device {\n\tstruct mtd_info mtd;\n\tint refcnt;\n\tstruct ubi_volume_desc *desc;\n\tint ubi_num;\n\tint vol_id;\n\tstruct list_head list;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n\tlong: 32;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n\tlong: 32;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct power_supply;\n\nstruct goldfish_battery_data {\n\tvoid *reg_base;\n\tint irq;\n\tspinlock_t lock;\n\tstruct power_supply *battery;\n\tstruct power_supply *ac;\n};\n\nstruct goldfish_fb {\n\tvoid *reg_base;\n\tint irq;\n\tspinlock_t lock;\n\twait_queue_head_t wait;\n\tint base_update_count;\n\tint rotation;\n\tstruct fb_info fb;\n\tu32 cmap[16];\n};\n\nstruct goldfish_pic_data {\n\tvoid *base;\n\tstruct irq_domain *irq_domain;\n};\n\nstruct goldfish_pipe_command;\n\nstruct goldfish_pipe_dev;\n\nstruct goldfish_pipe {\n\tu32 id;\n\tlong unsigned int flags;\n\tlong unsigned int signalled_flags;\n\tstruct goldfish_pipe_command *command_buffer;\n\tstruct goldfish_pipe *prev_signalled;\n\tstruct goldfish_pipe *next_signalled;\n\tstruct mutex lock;\n\twait_queue_head_t wake_queue;\n\tstruct goldfish_pipe_dev *dev;\n\tstruct page *pages[336];\n};\n\nstruct goldfish_pipe_command {\n\ts32 cmd;\n\ts32 id;\n\ts32 status;\n\ts32 reserved;\n\tunion {\n\t\tstruct {\n\t\t\tu32 buffers_count;\n\t\t\ts32 consumed_size;\n\t\t\tu64 ptrs[336];\n\t\t\tu32 sizes[336];\n\t\t} rw_params;\n\t};\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct goldfish_pipe_dev_buffers;\n\nstruct goldfish_pipe_dev {\n\tvoid *magic;\n\tspinlock_t lock;\n\tstruct goldfish_pipe **pipes;\n\tu32 pipes_capacity;\n\tstruct goldfish_pipe_dev_buffers *buffers;\n\tstruct goldfish_pipe *first_signalled_pipe;\n\tstruct device *pdev_dev;\n\tint irq;\n\tint version;\n\tunsigned char *base;\n\tstruct miscdevice miscdev;\n};\n\nstruct open_command_param {\n\tu64 command_buffer_ptr;\n\tu32 rw_params_max_count;\n\tlong: 32;\n};\n\nstruct signalled_pipe_buffer {\n\tu32 id;\n\tu32 flags;\n};\n\nstruct goldfish_pipe_dev_buffers {\n\tstruct open_command_param open_command_params;\n\tstruct signalled_pipe_buffer signalled_pipe_buffers[64];\n};\n\nstruct rtc_device;\n\nstruct goldfish_rtc {\n\tvoid *base;\n\tint irq;\n\tstruct rtc_device *rtc;\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct goldfish_tty {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tvoid *base;\n\tu32 irq;\n\tint opencount;\n\tstruct console console;\n\tu32 version;\n\tstruct device *dev;\n};\n\nstruct gpio_device;\n\nstruct gpio_array {\n\tstruct gpio_desc **desc;\n\tunsigned int size;\n\tstruct gpio_device *gdev;\n\tlong unsigned int *get_mask;\n\tlong unsigned int *set_mask;\n\tlong unsigned int invert_mask[0];\n};\n\nstruct gpio_v2_line_attribute {\n\t__u32 id;\n\t__u32 padding;\n\tunion {\n\t\t__u64 flags;\n\t\t__u64 values;\n\t\t__u32 debounce_period_us;\n\t};\n};\n\nstruct gpio_v2_line_info {\n\tchar name[32];\n\tchar consumer[32];\n\t__u32 offset;\n\t__u32 num_attrs;\n\t__u64 flags;\n\tstruct gpio_v2_line_attribute attrs[10];\n\t__u32 padding[4];\n};\n\nstruct gpio_v2_line_info_changed {\n\tstruct gpio_v2_line_info info;\n\t__u64 timestamp_ns;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct gpio_chardev_data {\n\tstruct gpio_device *gdev;\n\twait_queue_head_t wait;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_info_changed *type;\n\t\t\tconst struct gpio_v2_line_info_changed *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_info_changed *ptr;\n\t\t\tconst struct gpio_v2_line_info_changed *ptr_const;\n\t\t};\n\t\tlong: 32;\n\t\tstruct gpio_v2_line_info_changed buf[32];\n\t} events;\n\tstruct notifier_block lineinfo_changed_nb;\n\tstruct notifier_block device_unregistered_nb;\n\tlong unsigned int *watched_lines;\n\tatomic_t watch_abi_version;\n\tstruct file *fp;\n\tlong: 32;\n};\n\nstruct irq_fwspec;\n\nstruct irq_data;\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nstruct irq_chip;\n\nstruct gpio_chip;\n\nunion gpio_irq_fwspec;\n\nstruct gpio_irq_chip {\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *parent_domain;\n\tint (*child_to_parent_hwirq)(struct gpio_chip *, unsigned int, unsigned int, unsigned int *, unsigned int *);\n\tint (*populate_parent_alloc_arg)(struct gpio_chip *, union gpio_irq_fwspec *, unsigned int, unsigned int);\n\tunsigned int (*child_offset_to_irq)(struct gpio_chip *, unsigned int);\n\tstruct irq_domain_ops child_irq_domain_ops;\n\tirq_flow_handler_t handler;\n\tunsigned int default_type;\n\tstruct lock_class_key *lock_key;\n\tstruct lock_class_key *request_key;\n\tirq_flow_handler_t parent_handler;\n\tunion {\n\t\tvoid *parent_handler_data;\n\t\tvoid **parent_handler_data_array;\n\t};\n\tunsigned int num_parents;\n\tunsigned int *parents;\n\tunsigned int *map;\n\tbool threaded;\n\tbool per_parent_data;\n\tbool initialized;\n\tbool domain_is_allocated_externally;\n\tint (*init_hw)(struct gpio_chip *);\n\tvoid (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tlong unsigned int *valid_mask;\n\tunsigned int first;\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n};\n\nstruct of_phandle_args;\n\nstruct gpio_chip {\n\tconst char *label;\n\tstruct gpio_device *gpiodev;\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tstruct module *owner;\n\tint (*request)(struct gpio_chip *, unsigned int);\n\tvoid (*free)(struct gpio_chip *, unsigned int);\n\tint (*get_direction)(struct gpio_chip *, unsigned int);\n\tint (*direction_input)(struct gpio_chip *, unsigned int);\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tint (*get)(struct gpio_chip *, unsigned int);\n\tint (*get_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n\tint (*set_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set_config)(struct gpio_chip *, unsigned int, long unsigned int);\n\tint (*to_irq)(struct gpio_chip *, unsigned int);\n\tvoid (*dbg_show)(struct seq_file *, struct gpio_chip *);\n\tint (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tint (*add_pin_ranges)(struct gpio_chip *);\n\tint (*en_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint (*dis_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint base;\n\tu16 ngpio;\n\tu16 offset;\n\tconst char * const *names;\n\tbool can_sleep;\n\tstruct gpio_irq_chip irq;\n\tunsigned int of_gpio_n_cells;\n\tbool (*of_node_instance_match)(struct gpio_chip *, unsigned int);\n\tint (*of_xlate)(struct gpio_chip *, const struct of_phandle_args *, u32 *);\n};\n\nstruct gpio_chip_guard {\n\tstruct gpio_device *gdev;\n\tstruct gpio_chip *gc;\n\tint idx;\n};\n\ntypedef struct gpio_chip_guard class_gpio_chip_guard_t;\n\nstruct gpio_desc_label;\n\nstruct gpio_desc {\n\tstruct gpio_device *gdev;\n\tlong unsigned int flags;\n\tstruct gpio_desc_label *label;\n\tconst char *name;\n\tunsigned int debounce_period_us;\n};\n\nstruct gpio_desc_label {\n\tstruct callback_head rh;\n\tchar str[0];\n};\n\nstruct gpio_descs {\n\tstruct gpio_array *info;\n\tunsigned int ndescs;\n\tstruct gpio_desc *desc[0];\n};\n\nstruct gpio_device {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tstruct module *owner;\n\tstruct gpio_chip *chip;\n\tstruct gpio_desc *descs;\n\tlong unsigned int *valid_mask;\n\tstruct srcu_struct desc_srcu;\n\tunsigned int base;\n\tu16 ngpio;\n\tbool can_sleep;\n\tconst char *label;\n\tvoid *data;\n\tstruct list_head list;\n\tstruct raw_notifier_head line_state_notifier;\n\trwlock_t line_state_lock;\n\tstruct workqueue_struct *line_state_wq;\n\tstruct blocking_notifier_head device_notifier;\n\tstruct srcu_struct srcu;\n\tstruct list_head pin_ranges;\n};\n\nstruct gpio_generic_chip {\n\tstruct gpio_chip gc;\n\tlong unsigned int (*read_reg)(void *);\n\tvoid (*write_reg)(void *, long unsigned int);\n\tbool be_bits;\n\tvoid *reg_dat;\n\tvoid *reg_set;\n\tvoid *reg_clr;\n\tvoid *reg_dir_out;\n\tvoid *reg_dir_in;\n\tbool dir_unreadable;\n\tbool pinctrl;\n\tint bits;\n\traw_spinlock_t lock;\n\tlong unsigned int sdata;\n\tlong unsigned int sdir;\n};\n\nstruct gpio_generic_chip_config {\n\tstruct device *dev;\n\tlong unsigned int sz;\n\tvoid *dat;\n\tvoid *set;\n\tvoid *clr;\n\tvoid *dirout;\n\tvoid *dirin;\n\tlong unsigned int flags;\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct msi_desc;\n\nstruct msi_alloc_info {\n\tstruct msi_desc *desc;\n\tirq_hw_number_t hwirq;\n\tlong unsigned int flags;\n\tunion {\n\t\tlong unsigned int ul;\n\t\tvoid *ptr;\n\t} scratchpad[2];\n};\n\ntypedef struct msi_alloc_info msi_alloc_info_t;\n\nunion gpio_irq_fwspec {\n\tstruct irq_fwspec fwspec;\n\tmsi_alloc_info_t msiinfo;\n};\n\nstruct gpio_nand_platdata {\n\tvoid (*adjust_parts)(struct gpio_nand_platdata *, size_t);\n\tstruct mtd_partition *parts;\n\tunsigned int num_parts;\n\tunsigned int options;\n\tint chip_delay;\n};\n\nstruct pinctrl_gpio_range {\n\tstruct list_head node;\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int base;\n\tunsigned int pin_base;\n\tunsigned int npins;\n\tconst unsigned int *pins;\n\tstruct gpio_chip *gc;\n};\n\nstruct pinctrl_dev;\n\nstruct gpio_pin_range {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_gpio_range range;\n};\n\nstruct gpio_v2_line_config_attribute {\n\tstruct gpio_v2_line_attribute attr;\n\t__u64 mask;\n};\n\nstruct gpio_v2_line_config {\n\t__u64 flags;\n\t__u32 num_attrs;\n\t__u32 padding[5];\n\tstruct gpio_v2_line_config_attribute attrs[10];\n};\n\nstruct gpio_v2_line_event {\n\t__u64 timestamp_ns;\n\t__u32 id;\n\t__u32 offset;\n\t__u32 seqno;\n\t__u32 line_seqno;\n\t__u32 padding[6];\n};\n\nstruct gpio_v2_line_request {\n\t__u32 offsets[64];\n\tchar consumer[32];\n\tstruct gpio_v2_line_config config;\n\t__u32 num_lines;\n\t__u32 event_buffer_size;\n\t__u32 padding[5];\n\t__s32 fd;\n};\n\nstruct gpio_v2_line_values {\n\t__u64 bits;\n\t__u64 mask;\n};\n\nstruct gpiochip_info {\n\tchar name[32];\n\tchar label[32];\n\t__u32 lines;\n};\n\nstruct gpiod_data {\n\tstruct list_head list;\n\tstruct gpio_desc *desc;\n\tstruct device *dev;\n\tstruct mutex mutex;\n\tstruct kernfs_node *value_kn;\n\tint irq;\n\tunsigned char irq_flags;\n\tbool direction_can_change;\n\tstruct kobject *parent;\n\tstruct device_attribute dir_attr;\n\tstruct device_attribute val_attr;\n\tstruct device_attribute edge_attr;\n\tstruct device_attribute active_low_attr;\n\tstruct attribute *class_attrs[5];\n\tstruct attribute_group class_attr_group;\n\tconst struct attribute_group *class_attr_groups[2];\n\tstruct attribute *chip_attrs[3];\n\tstruct attribute_group chip_attr_group;\n\tconst struct attribute_group *chip_attr_groups[2];\n};\n\nstruct gpiod_hog {\n\tstruct list_head list;\n\tconst char *chip_label;\n\tu16 chip_hwnum;\n\tconst char *line_name;\n\tlong unsigned int lflags;\n\tint dflags;\n};\n\nstruct gpiod_lookup {\n\tconst char *key;\n\tu16 chip_hwnum;\n\tconst char *con_id;\n\tunsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct gpiod_lookup_table {\n\tstruct list_head list;\n\tconst char *dev_id;\n\tstruct gpiod_lookup table[0];\n};\n\nstruct gpiodev_data {\n\tstruct list_head exported_lines;\n\tstruct gpio_device *gdev;\n\tstruct device *cdev_id;\n\tstruct device *cdev_base;\n};\n\nstruct gpioevent_data {\n\t__u64 timestamp;\n\t__u32 id;\n\tlong: 32;\n};\n\nstruct gpioevent_request {\n\t__u32 lineoffset;\n\t__u32 handleflags;\n\t__u32 eventflags;\n\tchar consumer_label[32];\n\tint fd;\n};\n\nstruct gpiohandle_config {\n\t__u32 flags;\n\t__u8 default_values[64];\n\t__u32 padding[4];\n};\n\nstruct gpiohandle_data {\n\t__u8 values[64];\n};\n\nstruct gpiohandle_request {\n\t__u32 lineoffsets[64];\n\t__u32 flags;\n\t__u8 default_values[64];\n\tchar consumer_label[32];\n\t__u32 lines;\n\tint fd;\n};\n\nstruct gpiolib_seq_priv {\n\tbool newline;\n\tint idx;\n};\n\nstruct gpioline_info {\n\t__u32 line_offset;\n\t__u32 flags;\n\tchar name[32];\n\tchar consumer[32];\n};\n\nstruct gpioline_info_changed {\n\tstruct gpioline_info info;\n\t__u64 timestamp;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct nand_controller_ops;\n\nstruct nand_controller {\n\tstruct mutex lock;\n\tconst struct nand_controller_ops *ops;\n\tstruct {\n\t\tunsigned int data_only_read: 1;\n\t\tunsigned int cont_read: 1;\n\t} supported_op;\n\tbool controller_wp;\n};\n\nstruct nand_memory_organization {\n\tunsigned int bits_per_cell;\n\tunsigned int pagesize;\n\tunsigned int oobsize;\n\tunsigned int pages_per_eraseblock;\n\tunsigned int eraseblocks_per_lun;\n\tunsigned int max_bad_eraseblocks_per_lun;\n\tunsigned int planes_per_lun;\n\tunsigned int luns_per_target;\n\tunsigned int ntargets;\n};\n\nstruct nand_ecc_props {\n\tenum nand_ecc_engine_type engine_type;\n\tenum nand_ecc_placement placement;\n\tenum nand_ecc_algo algo;\n\tunsigned int strength;\n\tunsigned int step_size;\n\tunsigned int flags;\n};\n\nstruct nand_ecc_context {\n\tstruct nand_ecc_props conf;\n\tunsigned int nsteps;\n\tunsigned int total;\n\tvoid *priv;\n};\n\nstruct nand_ecc_engine;\n\nstruct nand_ecc {\n\tstruct nand_ecc_props defaults;\n\tstruct nand_ecc_props requirements;\n\tstruct nand_ecc_props user_conf;\n\tstruct nand_ecc_context ctx;\n\tstruct nand_ecc_engine *ondie_engine;\n\tstruct nand_ecc_engine *engine;\n};\n\nstruct nand_row_converter {\n\tunsigned int lun_addr_shift;\n\tunsigned int eraseblock_addr_shift;\n};\n\nstruct nand_bbt {\n\tlong unsigned int *cache;\n};\n\nstruct nand_ops;\n\nstruct nand_device {\n\tstruct mtd_info mtd;\n\tstruct nand_memory_organization memorg;\n\tstruct nand_ecc ecc;\n\tstruct nand_row_converter rowconv;\n\tstruct nand_bbt bbt;\n\tconst struct nand_ops *ops;\n};\n\nstruct nand_id {\n\tu8 data[8];\n\tint len;\n};\n\nstruct onfi_params;\n\nstruct nand_parameters {\n\tconst char *model;\n\tbool supports_set_get_features;\n\tbool supports_read_cache;\n\tlong unsigned int set_feature_list[8];\n\tlong unsigned int get_feature_list[8];\n\tstruct onfi_params *onfi;\n};\n\nstruct nand_manufacturer_desc;\n\nstruct nand_manufacturer {\n\tconst struct nand_manufacturer_desc *desc;\n\tvoid *priv;\n};\n\nstruct nand_chip;\n\nstruct nand_interface_config;\n\nstruct nand_chip_ops {\n\tint (*suspend)(struct nand_chip *);\n\tvoid (*resume)(struct nand_chip *);\n\tint (*lock_area)(struct nand_chip *, loff_t, uint64_t);\n\tint (*unlock_area)(struct nand_chip *, loff_t, uint64_t);\n\tint (*setup_read_retry)(struct nand_chip *, int);\n\tint (*choose_interface_config)(struct nand_chip *, struct nand_interface_config *);\n};\n\nstruct nand_legacy {\n\tvoid *IO_ADDR_R;\n\tvoid *IO_ADDR_W;\n\tvoid (*select_chip)(struct nand_chip *, int);\n\tu8 (*read_byte)(struct nand_chip *);\n\tvoid (*write_byte)(struct nand_chip *, u8);\n\tvoid (*write_buf)(struct nand_chip *, const u8 *, int);\n\tvoid (*read_buf)(struct nand_chip *, u8 *, int);\n\tvoid (*cmd_ctrl)(struct nand_chip *, int, unsigned int);\n\tvoid (*cmdfunc)(struct nand_chip *, unsigned int, int, int);\n\tint (*dev_ready)(struct nand_chip *);\n\tint (*waitfunc)(struct nand_chip *);\n\tint (*block_bad)(struct nand_chip *, loff_t);\n\tint (*block_markbad)(struct nand_chip *, loff_t);\n\tint (*set_features)(struct nand_chip *, int, u8 *);\n\tint (*get_features)(struct nand_chip *, int, u8 *);\n\tint chip_delay;\n\tstruct nand_controller dummy_controller;\n};\n\nstruct nand_ecc_ctrl {\n\tenum nand_ecc_engine_type engine_type;\n\tenum nand_ecc_placement placement;\n\tenum nand_ecc_algo algo;\n\tint steps;\n\tint size;\n\tint bytes;\n\tint total;\n\tint strength;\n\tint prepad;\n\tint postpad;\n\tunsigned int options;\n\tu8 *calc_buf;\n\tu8 *code_buf;\n\tvoid (*hwctl)(struct nand_chip *, int);\n\tint (*calculate)(struct nand_chip *, const uint8_t *, uint8_t *);\n\tint (*correct)(struct nand_chip *, uint8_t *, uint8_t *, uint8_t *);\n\tint (*read_page_raw)(struct nand_chip *, uint8_t *, int, int);\n\tint (*write_page_raw)(struct nand_chip *, const uint8_t *, int, int);\n\tint (*read_page)(struct nand_chip *, uint8_t *, int, int);\n\tint (*read_subpage)(struct nand_chip *, uint32_t, uint32_t, uint8_t *, int);\n\tint (*write_subpage)(struct nand_chip *, uint32_t, uint32_t, const uint8_t *, int, int);\n\tint (*write_page)(struct nand_chip *, const uint8_t *, int, int);\n\tint (*write_oob_raw)(struct nand_chip *, int);\n\tint (*read_oob_raw)(struct nand_chip *, int);\n\tint (*read_oob)(struct nand_chip *, int);\n\tint (*write_oob)(struct nand_chip *, int);\n};\n\nstruct nand_bbt_descr;\n\nstruct nand_secure_region;\n\nstruct nand_chip {\n\tstruct nand_device base;\n\tstruct nand_id id;\n\tstruct nand_parameters parameters;\n\tstruct nand_manufacturer manufacturer;\n\tstruct nand_chip_ops ops;\n\tstruct nand_legacy legacy;\n\tunsigned int options;\n\tconst struct nand_interface_config *current_interface_config;\n\tstruct nand_interface_config *best_interface_config;\n\tunsigned int bbt_erase_shift;\n\tunsigned int bbt_options;\n\tunsigned int badblockpos;\n\tunsigned int badblockbits;\n\tstruct nand_bbt_descr *bbt_td;\n\tstruct nand_bbt_descr *bbt_md;\n\tstruct nand_bbt_descr *badblock_pattern;\n\tu8 *bbt;\n\tunsigned int page_shift;\n\tunsigned int phys_erase_shift;\n\tunsigned int chip_shift;\n\tunsigned int pagemask;\n\tunsigned int subpagesize;\n\tu8 *data_buf;\n\tu8 *oob_poi;\n\tstruct {\n\t\tunsigned int bitflips;\n\t\tint page;\n\t} pagecache;\n\tlong unsigned int buf_align;\n\tstruct mutex lock;\n\tunsigned int suspended: 1;\n\twait_queue_head_t resume_wq;\n\tint cur_cs;\n\tint read_retries;\n\tstruct nand_secure_region *secure_regions;\n\tu8 nr_secure_regions;\n\tstruct {\n\t\tbool ongoing;\n\t\tunsigned int first_page;\n\t\tunsigned int pause_page;\n\t\tunsigned int last_page;\n\t} cont_read;\n\tstruct nand_controller *controller;\n\tstruct nand_ecc_ctrl ecc;\n\tvoid *priv;\n};\n\nstruct gpiomtd {\n\tstruct nand_controller base;\n\tvoid *io;\n\tvoid *io_sync;\n\tlong: 32;\n\tstruct nand_chip nand_chip;\n\tstruct gpio_nand_platdata plat;\n\tstruct gpio_desc *nce;\n\tstruct gpio_desc *cle;\n\tstruct gpio_desc *ale;\n\tstruct gpio_desc *rdy;\n\tstruct gpio_desc *nwp;\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct napi_config;\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n\tlong: 32;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n};\n\nstruct pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tsize_t npins;\n};\n\nstruct group_desc {\n\tstruct pingroup grp;\n\tvoid *data;\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct rpc_clnt;\n\nstruct rpc_pipe_ops;\n\nstruct gss_alloc_pdo {\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tconst struct rpc_pipe_ops *upcall_ops;\n};\n\nstruct rpcsec_gss_oid {\n\tunsigned int len;\n\tu8 data[32];\n};\n\nstruct gss_api_ops;\n\nstruct pf_desc;\n\nstruct gss_api_mech {\n\tstruct list_head gm_list;\n\tstruct module *gm_owner;\n\tstruct rpcsec_gss_oid gm_oid;\n\tchar *gm_name;\n\tconst struct gss_api_ops *gm_ops;\n\tint gm_pf_num;\n\tstruct pf_desc *gm_pfs;\n\tconst char *gm_upcall_enctypes;\n};\n\nstruct gss_ctx;\n\nstruct xdr_netobj;\n\nstruct gss_api_ops {\n\tint (*gss_import_sec_context)(const void *, size_t, struct gss_ctx *, time64_t *, gfp_t);\n\tu32 (*gss_get_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_verify_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_wrap)(struct gss_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*gss_unwrap)(struct gss_ctx *, int, int, struct xdr_buf *);\n\tvoid (*gss_delete_sec_context)(void *);\n};\n\nstruct rpc_authops;\n\nstruct rpc_cred_cache;\n\nstruct rpc_auth {\n\tunsigned int au_cslack;\n\tunsigned int au_rslack;\n\tunsigned int au_verfsize;\n\tunsigned int au_ralign;\n\tlong unsigned int au_flags;\n\tconst struct rpc_authops *au_ops;\n\trpc_authflavor_t au_flavor;\n\trefcount_t au_count;\n\tstruct rpc_cred_cache *au_credcache;\n};\n\nstruct gss_pipe;\n\nstruct gss_auth {\n\tstruct kref kref;\n\tstruct hlist_node hash;\n\tstruct rpc_auth rpc_auth;\n\tstruct gss_api_mech *mech;\n\tenum rpc_gss_svc service;\n\tstruct rpc_clnt *client;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct gss_pipe *gss_pipe[2];\n\tconst char *target_name;\n};\n\nstruct xdr_netobj {\n\tunsigned int len;\n\tu8 *data;\n};\n\nstruct gss_cl_ctx {\n\trefcount_t count;\n\tenum rpc_gss_proc gc_proc;\n\tu32 gc_seq;\n\tu32 gc_seq_xmit;\n\tspinlock_t gc_seq_lock;\n\tstruct gss_ctx *gc_gss_ctx;\n\tstruct xdr_netobj gc_wire_ctx;\n\tstruct xdr_netobj gc_acceptor;\n\tu32 gc_win;\n\tlong unsigned int gc_expiry;\n\tstruct callback_head gc_rcu;\n};\n\nstruct rpc_credops;\n\nstruct rpc_cred {\n\tstruct hlist_node cr_hash;\n\tstruct list_head cr_lru;\n\tstruct callback_head cr_rcu;\n\tstruct rpc_auth *cr_auth;\n\tconst struct rpc_credops *cr_ops;\n\tlong unsigned int cr_expire;\n\tlong unsigned int cr_flags;\n\trefcount_t cr_count;\n\tconst struct cred *cr_cred;\n};\n\nstruct gss_upcall_msg;\n\nstruct gss_cred {\n\tstruct rpc_cred gc_base;\n\tenum rpc_gss_svc gc_service;\n\tstruct gss_cl_ctx *gc_ctx;\n\tstruct gss_upcall_msg *gc_upcall;\n\tconst char *gc_principal;\n\tlong unsigned int gc_upcall_timestamp;\n};\n\nstruct gss_ctx {\n\tstruct gss_api_mech *mech_type;\n\tvoid *internal_ctx_id;\n\tunsigned int slack;\n\tunsigned int align;\n};\n\nstruct gss_domain {\n\tstruct auth_domain h;\n\tu32 pseudoflavor;\n};\n\nstruct krb5_ctx;\n\nstruct gss_krb5_enctype {\n\tconst u32 etype;\n\tconst u32 ctype;\n\tconst char *name;\n\tconst char *encrypt_name;\n\tconst char *aux_cipher;\n\tconst char *cksum_name;\n\tconst u16 signalg;\n\tconst u16 sealalg;\n\tconst u32 cksumlength;\n\tconst u32 keyed_cksum;\n\tconst u32 keybytes;\n\tconst u32 keylength;\n\tconst u32 Kc_length;\n\tconst u32 Ke_length;\n\tconst u32 Ki_length;\n\tint (*derive_key)(const struct gss_krb5_enctype *, const struct xdr_netobj *, struct xdr_netobj *, const struct xdr_netobj *, gfp_t);\n\tu32 (*encrypt)(struct krb5_ctx *, u32, struct xdr_buf *, struct page **);\n\tu32 (*decrypt)(struct krb5_ctx *, u32, u32, struct xdr_buf *, u32 *, u32 *);\n\tu32 (*get_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*verify_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*wrap)(struct krb5_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*unwrap)(struct krb5_ctx *, int, int, struct xdr_buf *, unsigned int *, unsigned int *);\n};\n\nstruct rpc_pipe_dir_object_ops;\n\nstruct rpc_pipe_dir_object {\n\tstruct list_head pdo_head;\n\tconst struct rpc_pipe_dir_object_ops *pdo_ops;\n\tvoid *pdo_data;\n};\n\nstruct rpc_pipe;\n\nstruct gss_pipe {\n\tstruct rpc_pipe_dir_object pdo;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tstruct kref kref;\n};\n\nstruct rpc_gss_wire_cred {\n\tu32 gc_v;\n\tu32 gc_proc;\n\tu32 gc_seq;\n\tu32 gc_svc;\n\tstruct xdr_netobj gc_ctx;\n};\n\nstruct rsc;\n\nstruct gss_svc_data {\n\tstruct rpc_gss_wire_cred clcred;\n\tu32 gsd_databody_offset;\n\tstruct rsc *rsci;\n\t__be32 gsd_seq_num;\n\tu8 gsd_scratch[40];\n};\n\nstruct gss_svc_seq_data {\n\tu32 sd_max;\n\tlong unsigned int sd_win[4];\n\tspinlock_t sd_lock;\n};\n\nstruct rpc_pipe_msg {\n\tstruct list_head list;\n\tvoid *data;\n\tsize_t len;\n\tsize_t copied;\n\tint errno;\n};\n\nstruct rpc_timer {\n\tstruct list_head list;\n\tlong unsigned int expires;\n\tstruct delayed_work dwork;\n};\n\nstruct rpc_wait_queue {\n\tspinlock_t lock;\n\tstruct list_head tasks[4];\n\tunsigned char maxpriority;\n\tunsigned char priority;\n\tunsigned char nr;\n\tunsigned int qlen;\n\tstruct rpc_timer timer_list;\n};\n\nstruct gss_upcall_msg {\n\trefcount_t count;\n\tkuid_t uid;\n\tconst char *service_name;\n\tstruct rpc_pipe_msg msg;\n\tstruct list_head list;\n\tstruct gss_auth *auth;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_wait_queue rpc_waitqueue;\n\twait_queue_head_t waitqueue;\n\tstruct gss_cl_ctx *ctx;\n\tchar databuf[256];\n};\n\nstruct gssp_in_token {\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n};\n\nstruct svc_cred {\n\tkuid_t cr_uid;\n\tkgid_t cr_gid;\n\tstruct group_info *cr_group_info;\n\tu32 cr_flavor;\n\tchar *cr_raw_principal;\n\tchar *cr_principal;\n\tchar *cr_targ_princ;\n\tstruct gss_api_mech *cr_gss_mech;\n};\n\nstruct gssp_upcall_data {\n\tstruct xdr_netobj in_handle;\n\tstruct gssp_in_token in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tstruct rpcsec_gss_oid mech_oid;\n\tstruct svc_cred creds;\n\tint found_creds;\n\tint major_status;\n\tint minor_status;\n};\n\ntypedef struct xdr_netobj utf8string;\n\ntypedef struct xdr_netobj gssx_buffer;\n\nstruct gssx_option;\n\nstruct gssx_option_array {\n\tu32 count;\n\tstruct gssx_option *data;\n};\n\nstruct gssx_call_ctx {\n\tutf8string locale;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx;\n\nstruct gssx_cred;\n\nstruct gssx_cb;\n\nstruct gssx_arg_accept_sec_context {\n\tstruct gssx_call_ctx call_ctx;\n\tstruct gssx_ctx *context_handle;\n\tstruct gssx_cred *cred_handle;\n\tstruct gssp_in_token input_token;\n\tstruct gssx_cb *input_cb;\n\tu32 ret_deleg_cred;\n\tstruct gssx_option_array options;\n\tstruct page **pages;\n\tunsigned int npages;\n};\n\nstruct gssx_cb {\n\tu64 initiator_addrtype;\n\tgssx_buffer initiator_address;\n\tu64 acceptor_addrtype;\n\tgssx_buffer acceptor_address;\n\tgssx_buffer application_data;\n};\n\nstruct gssx_name {\n\tgssx_buffer display_name;\n};\n\ntypedef struct gssx_name gssx_name;\n\nstruct gssx_cred_element;\n\nstruct gssx_cred_element_array {\n\tu32 count;\n\tstruct gssx_cred_element *data;\n};\n\nstruct gssx_cred {\n\tgssx_name desired_name;\n\tstruct gssx_cred_element_array elements;\n\tgssx_buffer cred_handle_reference;\n\tu32 needs_release;\n};\n\ntypedef struct xdr_netobj gssx_OID;\n\nstruct gssx_cred_element {\n\tgssx_name MN;\n\tgssx_OID mech;\n\tu32 cred_usage;\n\tlong: 32;\n\tu64 initiator_time_rec;\n\tu64 acceptor_time_rec;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx {\n\tgssx_buffer exported_context_token;\n\tgssx_buffer state;\n\tu32 need_release;\n\tgssx_OID mech;\n\tgssx_name src_name;\n\tgssx_name targ_name;\n\tlong: 32;\n\tu64 lifetime;\n\tu64 ctx_flags;\n\tu32 locally_initiated;\n\tu32 open;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_name_attr {\n\tgssx_buffer attr;\n\tgssx_buffer value;\n\tstruct gssx_option_array extensions;\n};\n\nstruct gssx_name_attr_array {\n\tu32 count;\n\tstruct gssx_name_attr *data;\n};\n\nstruct gssx_option {\n\tgssx_buffer option;\n\tgssx_buffer value;\n};\n\nstruct gssx_status {\n\tu64 major_status;\n\tgssx_OID mech;\n\tu64 minor_status;\n\tutf8string major_status_string;\n\tutf8string minor_status_string;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_res_accept_sec_context {\n\tstruct gssx_status status;\n\tstruct gssx_ctx *context_handle;\n\tgssx_buffer *output_token;\n\tstruct gssx_option_array options;\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct handshake_net {\n\tspinlock_t hn_lock;\n\tint hn_pending;\n\tint hn_pending_max;\n\tstruct list_head hn_requests;\n\tlong unsigned int hn_flags;\n};\n\nstruct handshake_req;\n\nstruct handshake_proto {\n\tint hp_handler_class;\n\tsize_t hp_privsize;\n\tlong unsigned int hp_flags;\n\tint (*hp_accept)(struct handshake_req *, struct genl_info *, int);\n\tvoid (*hp_done)(struct handshake_req *, unsigned int, struct genl_info *);\n\tvoid (*hp_destroy)(struct handshake_req *);\n};\n\nstruct handshake_req {\n\tstruct list_head hr_list;\n\tstruct rhash_head hr_rhash;\n\tlong unsigned int hr_flags;\n\tconst struct handshake_proto *hr_proto;\n\tstruct sock *hr_sk;\n\tvoid (*hr_odestruct)(struct sock *);\n\tchar hr_priv[0];\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hc_driver {\n\tconst char *description;\n\tconst char *product_desc;\n\tsize_t hcd_priv_size;\n\tirqreturn_t (*irq)(struct usb_hcd *);\n\tint flags;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*pci_suspend)(struct usb_hcd *, bool);\n\tint (*pci_resume)(struct usb_hcd *, pm_message_t);\n\tint (*pci_poweroff_late)(struct usb_hcd *, bool);\n\tvoid (*stop)(struct usb_hcd *);\n\tvoid (*shutdown)(struct usb_hcd *);\n\tint (*get_frame_number)(struct usb_hcd *);\n\tint (*urb_enqueue)(struct usb_hcd *, struct urb *, gfp_t);\n\tint (*urb_dequeue)(struct usb_hcd *, struct urb *, int);\n\tint (*map_urb_for_dma)(struct usb_hcd *, struct urb *, gfp_t);\n\tvoid (*unmap_urb_for_dma)(struct usb_hcd *, struct urb *);\n\tvoid (*endpoint_disable)(struct usb_hcd *, struct usb_host_endpoint *);\n\tvoid (*endpoint_reset)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*hub_status_data)(struct usb_hcd *, char *);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n\tint (*bus_suspend)(struct usb_hcd *);\n\tint (*bus_resume)(struct usb_hcd *);\n\tint (*start_port_reset)(struct usb_hcd *, unsigned int);\n\tlong unsigned int (*get_resuming_ports)(struct usb_hcd *);\n\tvoid (*relinquish_port)(struct usb_hcd *, int);\n\tint (*port_handed_over)(struct usb_hcd *, int);\n\tvoid (*clear_tt_buffer_complete)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*alloc_dev)(struct usb_hcd *, struct usb_device *);\n\tvoid (*free_dev)(struct usb_hcd *, struct usb_device *);\n\tint (*alloc_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, unsigned int, gfp_t);\n\tint (*free_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, gfp_t);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*address_device)(struct usb_hcd *, struct usb_device *, unsigned int);\n\tint (*enable_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*reset_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_device)(struct usb_hcd *, struct usb_device *);\n\tint (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);\n\tint (*enable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*disable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*find_raw_port_number)(struct usb_hcd *, int);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n\tint (*submit_single_step_set_feature)(struct usb_hcd *, struct urb *, int);\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[24];\n};\n\nstruct hid_class_descriptor {\n\t__u8 bDescriptorType;\n\t__le16 wDescriptorLength;\n} __attribute__((packed));\n\nstruct hid_collection {\n\tint parent_idx;\n\tunsigned int type;\n\tunsigned int usage;\n\tunsigned int level;\n};\n\nstruct hid_control_fifo {\n\tunsigned char dir;\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_debug_list {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tchar *type;\n\t\t\tconst char *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tchar *ptr;\n\t\t\tconst char *ptr_const;\n\t\t};\n\t\tchar buf[0];\n\t} hid_debug_fifo;\n\tstruct fasync_struct *fasync;\n\tstruct hid_device *hdev;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct hid_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdHID;\n\t__u8 bCountryCode;\n\t__u8 bNumDescriptors;\n\tstruct hid_class_descriptor rpt_desc;\n\tstruct hid_class_descriptor opt_descs[0];\n} __attribute__((packed));\n\nstruct hid_report_enum {\n\tunsigned int numbered;\n\tstruct list_head report_list;\n\tstruct hid_report *report_id_hash[256];\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct hid_driver;\n\nstruct hid_ll_driver;\n\nstruct hid_field;\n\nstruct hid_usage;\n\nstruct hid_device {\n\tconst __u8 *dev_rdesc;\n\tconst __u8 *bpf_rdesc;\n\tconst __u8 *rdesc;\n\tunsigned int dev_rsize;\n\tunsigned int bpf_rsize;\n\tunsigned int rsize;\n\tunsigned int collection_size;\n\tstruct hid_collection *collection;\n\tunsigned int maxcollection;\n\tunsigned int maxapplication;\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\t__u32 version;\n\tenum hid_type type;\n\tunsigned int country;\n\tstruct hid_report_enum report_enum[3];\n\tstruct work_struct led_work;\n\tstruct semaphore driver_input_lock;\n\tlong: 32;\n\tstruct device dev;\n\tstruct hid_driver *driver;\n\tvoid *devres_group_id;\n\tconst struct hid_ll_driver *ll_driver;\n\tstruct mutex ll_open_lock;\n\tunsigned int ll_open_count;\n\tlong unsigned int status;\n\tunsigned int claimed;\n\tunsigned int quirks;\n\tunsigned int initial_quirks;\n\tbool io_started;\n\tstruct list_head inputs;\n\tvoid *hiddev;\n\tvoid *hidraw;\n\tchar name[128];\n\tchar phys[64];\n\tchar uniq[64];\n\tvoid *driver_data;\n\tint (*ff_init)(struct hid_device *);\n\tint (*hiddev_connect)(struct hid_device *, unsigned int);\n\tvoid (*hiddev_disconnect)(struct hid_device *);\n\tvoid (*hiddev_hid_event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*hiddev_report_event)(struct hid_device *, struct hid_report *);\n\tshort unsigned int debug;\n\tstruct dentry *debug_dir;\n\tstruct dentry *debug_rdesc;\n\tstruct dentry *debug_events;\n\tstruct list_head debug_list;\n\tspinlock_t debug_list_lock;\n\twait_queue_head_t debug_wait;\n\tstruct kref ref;\n\tunsigned int id;\n\tlong: 32;\n};\n\nstruct hid_device_id {\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hid_report_id;\n\nstruct hid_usage_id;\n\nstruct hid_input;\n\nstruct hid_driver {\n\tconst char *name;\n\tconst struct hid_device_id *id_table;\n\tstruct list_head dyn_list;\n\tspinlock_t dyn_lock;\n\tbool (*match)(struct hid_device *, bool);\n\tint (*probe)(struct hid_device *, const struct hid_device_id *);\n\tvoid (*remove)(struct hid_device *);\n\tconst struct hid_report_id *report_table;\n\tint (*raw_event)(struct hid_device *, struct hid_report *, u8 *, int);\n\tconst struct hid_usage_id *usage_table;\n\tint (*event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*report)(struct hid_device *, struct hid_report *);\n\tconst __u8 * (*report_fixup)(struct hid_device *, __u8 *, unsigned int *);\n\tint (*input_mapping)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_mapped)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_configured)(struct hid_device *, struct hid_input *);\n\tvoid (*feature_mapping)(struct hid_device *, struct hid_field *, struct hid_usage *);\n\tint (*suspend)(struct hid_device *, pm_message_t);\n\tint (*resume)(struct hid_device *);\n\tint (*reset_resume)(struct hid_device *);\n\tvoid (*on_hid_hw_open)(struct hid_device *);\n\tvoid (*on_hid_hw_close)(struct hid_device *);\n\tstruct device_driver driver;\n};\n\nstruct hid_dynid {\n\tstruct list_head list;\n\tstruct hid_device_id id;\n};\n\nstruct hid_field {\n\tunsigned int physical;\n\tunsigned int logical;\n\tunsigned int application;\n\tstruct hid_usage *usage;\n\tunsigned int maxusage;\n\tunsigned int flags;\n\tunsigned int report_offset;\n\tunsigned int report_size;\n\tunsigned int report_count;\n\tunsigned int report_type;\n\t__s32 *value;\n\t__s32 *new_value;\n\t__s32 *usages_priorities;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tbool ignored;\n\tstruct hid_report *report;\n\tunsigned int index;\n\tstruct hid_input *hidinput;\n\t__u16 dpad;\n\tunsigned int slot_idx;\n};\n\nstruct hid_field_entry {\n\tstruct list_head list;\n\tstruct hid_field *field;\n\tunsigned int index;\n\t__s32 priority;\n};\n\nstruct hid_global {\n\tunsigned int usage_page;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tunsigned int report_id;\n\tunsigned int report_size;\n\tunsigned int report_count;\n};\n\nstruct hid_input {\n\tstruct list_head list;\n\tstruct hid_report *report;\n\tstruct input_dev *input;\n\tconst char *name;\n\tstruct list_head reports;\n\tunsigned int application;\n\tbool registered;\n};\n\nstruct hid_item {\n\tunsigned int format;\n\t__u8 size;\n\t__u8 type;\n\t__u8 tag;\n\tunion {\n\t\t__u8 u8;\n\t\t__s8 s8;\n\t\t__u16 u16;\n\t\t__s16 s16;\n\t\t__u32 u32;\n\t\t__s32 s32;\n\t\tconst __u8 *longdata;\n\t} data;\n};\n\nstruct hid_ll_driver {\n\tint (*start)(struct hid_device *);\n\tvoid (*stop)(struct hid_device *);\n\tint (*open)(struct hid_device *);\n\tvoid (*close)(struct hid_device *);\n\tint (*power)(struct hid_device *, int);\n\tint (*parse)(struct hid_device *);\n\tvoid (*request)(struct hid_device *, struct hid_report *, int);\n\tint (*wait)(struct hid_device *);\n\tint (*raw_request)(struct hid_device *, unsigned char, __u8 *, size_t, unsigned char, int);\n\tint (*output_report)(struct hid_device *, __u8 *, size_t);\n\tint (*idle)(struct hid_device *, int, int, int);\n\tbool (*may_wakeup)(struct hid_device *);\n\tunsigned int max_buffer_size;\n};\n\nstruct hid_local {\n\tunsigned int usage[12288];\n\tu8 usage_size[12288];\n\tunsigned int collection_index[12288];\n\tunsigned int usage_index;\n\tunsigned int usage_minimum;\n\tunsigned int delimiter_depth;\n\tunsigned int delimiter_branch;\n};\n\nstruct hid_output_fifo {\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_parser {\n\tstruct hid_global global;\n\tstruct hid_global global_stack[4];\n\tunsigned int global_stack_ptr;\n\tstruct hid_local local;\n\tunsigned int *collection_stack;\n\tunsigned int collection_stack_ptr;\n\tunsigned int collection_stack_size;\n\tstruct hid_device *device;\n\tunsigned int scan_flags;\n};\n\nstruct hid_report {\n\tstruct list_head list;\n\tstruct list_head hidinput_list;\n\tstruct list_head field_entry_list;\n\tunsigned int id;\n\tenum hid_report_type type;\n\tunsigned int application;\n\tstruct hid_field *field[256];\n\tstruct hid_field_entry *field_entries;\n\tunsigned int maxfield;\n\tunsigned int size;\n\tstruct hid_device *device;\n\tbool tool_active;\n\tunsigned int tool;\n};\n\nstruct hid_report_id {\n\t__u32 report_type;\n};\n\nstruct hid_usage {\n\tunsigned int hid;\n\tunsigned int collection_index;\n\tunsigned int usage_index;\n\t__s8 resolution_multiplier;\n\t__s8 wheel_factor;\n\t__u16 code;\n\t__u8 type;\n\t__s16 hat_min;\n\t__s16 hat_max;\n\t__s16 hat_dir;\n\t__s16 wheel_accumulated;\n};\n\nstruct hid_usage_entry {\n\tunsigned int page;\n\tunsigned int usage;\n\tconst char *description;\n};\n\nstruct hid_usage_id {\n\t__u32 usage_hid;\n\t__u32 usage_type;\n\t__u32 usage_code;\n};\n\nstruct hiddev {\n\tint minor;\n\tint exist;\n\tint open;\n\tstruct mutex existancelock;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tbool initialized;\n};\n\nstruct hidraw {\n\tunsigned int minor;\n\tint exist;\n\tint open;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct device *dev;\n\tspinlock_t list_lock;\n\tstruct list_head list;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct md5_block_state {\n\tu32 h[4];\n};\n\nstruct md5_ctx {\n\tstruct md5_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_md5_ctx {\n\tstruct md5_ctx hash_ctx;\n\tstruct md5_block_state ostate;\n};\n\nstruct hmac_md5_key {\n\tstruct md5_block_state istate;\n\tstruct md5_block_state ostate;\n};\n\nstruct sha1_block_state {\n\tu32 h[5];\n};\n\nstruct sha1_ctx {\n\tstruct sha1_block_state state;\n\tlong: 32;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_sha1_ctx {\n\tstruct sha1_ctx sha_ctx;\n\tstruct sha1_block_state ostate;\n\tlong: 32;\n};\n\nstruct hmac_sha1_key {\n\tstruct sha1_block_state istate;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha384_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha384_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hmac_sha512_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tlong: 32;\n\tktime_t offset;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tlong: 32;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tlong: 32;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tlong: 32;\n\tstruct hrtimer_clock_base clock_base[8];\n\tlong: 32;\n\tlong: 32;\n\tcall_single_data_t csd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n\tlong: 32;\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tchar key[0];\n};\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct hynix_read_retry;\n\nstruct hynix_nand {\n\tconst struct hynix_read_retry *read_retry;\n};\n\nstruct hynix_read_retry {\n\tint nregs;\n\tconst u8 *regs;\n\tu8 values[0];\n};\n\nstruct hynix_read_retry_otp {\n\tint nregs;\n\tconst u8 *regs;\n\tconst u8 *values;\n\tint page;\n\tint size;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n\tlong: 32;\n};\n\nunion i2c_smbus_data;\n\nstruct i2c_algorithm {\n\tunion {\n\t\tint (*xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tunion {\n\t\tint (*xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n};\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tlong: 32;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n\tvoid *devres_group_id;\n\tstruct dentry *debugfs;\n};\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct i2c_dev {\n\tstruct list_head list;\n\tstruct i2c_adapter *adap;\n\tlong: 32;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tlong: 32;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *);\n\tvoid (*remove)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tu32 flags;\n};\n\nstruct i2c_dw_semaphore_callbacks {\n\tint (*probe)(struct dw_i2c_dev *);\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nstruct i2c_mux_core {\n\tstruct i2c_adapter *parent;\n\tstruct device *dev;\n\tunsigned int mux_locked: 1;\n\tunsigned int arbitrator: 1;\n\tunsigned int gate: 1;\n\tvoid *priv;\n\tint (*select)(struct i2c_mux_core *, u32);\n\tint (*deselect)(struct i2c_mux_core *, u32);\n\tint num_adapters;\n\tint max_adapters;\n\tstruct i2c_adapter *adapter[0];\n};\n\nstruct i2c_mux_priv {\n\tstruct i2c_adapter adap;\n\tstruct i2c_algorithm algo;\n\tstruct i2c_mux_core *muxc;\n\tu32 chan_id;\n\tlong: 32;\n};\n\nstruct i2c_rdwr_ioctl_data {\n\tstruct i2c_msg *msgs;\n\t__u32 nmsgs;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct i2c_smbus_ioctl_data {\n\t__u8 read_write;\n\t__u8 command;\n\t__u32 size;\n\tunion i2c_smbus_data *data;\n};\n\nstruct i_format {\n\tint simmediate: 16;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n\tlong: 32;\n};\n\nstruct ib_pd;\n\nstruct ib_uobject;\n\nstruct ib_gid_attr;\n\nstruct ib_ah {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tconst struct ib_gid_attr *sgid_attr;\n\tenum rdma_ah_attr_type type;\n};\n\nstruct ib_ah_attr {\n\tu16 dlid;\n\tu8 src_path_bits;\n};\n\nstruct ib_core_device {\n\tstruct device dev;\n\tpossible_net_t rdma_net;\n\tstruct kobject *ports_kobj;\n\tstruct list_head port_list;\n\tstruct ib_device *owner;\n\tlong: 32;\n};\n\nstruct ib_counters {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_counters_read_attr {\n\tu64 *counters_buff;\n\tu32 ncounters;\n\tu32 flags;\n};\n\nstruct ib_ucq_object;\n\nstruct ib_cq;\n\ntypedef void (*ib_comp_handler)(struct ib_cq *, void *);\n\nstruct irq_poll;\n\ntypedef int irq_poll_fn(struct irq_poll *, int);\n\nstruct irq_poll {\n\tstruct list_head list;\n\tlong unsigned int state;\n\tint weight;\n\tirq_poll_fn *poll;\n};\n\nstruct rdma_restrack_entry {\n\tbool valid;\n\tu8 no_track: 1;\n\tstruct kref kref;\n\tstruct completion comp;\n\tstruct task_struct *task;\n\tconst char *kern_name;\n\tenum rdma_restrack_type type;\n\tbool user;\n\tu32 id;\n};\n\nstruct ib_event;\n\nstruct ib_wc;\n\nstruct ib_cq {\n\tstruct ib_device *device;\n\tstruct ib_ucq_object *uobject;\n\tib_comp_handler comp_handler;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *cq_context;\n\tint cqe;\n\tunsigned int cqe_used;\n\tatomic_t usecnt;\n\tenum ib_poll_context poll_ctx;\n\tstruct ib_wc *wc;\n\tstruct list_head pool_entry;\n\tunion {\n\t\tstruct irq_poll iop;\n\t\tstruct work_struct work;\n\t};\n\tstruct workqueue_struct *comp_wq;\n\tstruct dim *dim;\n\tlong: 32;\n\tktime_t timestamp;\n\tu8 interrupt: 1;\n\tu8 shared: 1;\n\tunsigned int comp_vector;\n\tstruct rdma_restrack_entry res;\n\tlong: 32;\n};\n\nstruct ib_cq_caps {\n\tu16 max_cq_moderation_count;\n\tu16 max_cq_moderation_period;\n};\n\nstruct ib_cq_init_attr {\n\tunsigned int cqe;\n\tu32 comp_vector;\n\tu32 flags;\n};\n\nstruct ib_cqe {\n\tvoid (*done)(struct ib_cq *, struct ib_wc *);\n};\n\nstruct ib_mad;\n\nstruct uverbs_attr_bundle;\n\nstruct ib_umem;\n\nstruct rdma_cm_id;\n\nstruct iw_cm_id;\n\nstruct iw_cm_conn_param;\n\nstruct ib_uverbs_file;\n\nstruct ib_qp;\n\nstruct ib_send_wr;\n\nstruct ib_recv_wr;\n\nstruct ib_srq;\n\nstruct ib_grh;\n\nstruct ib_device_attr;\n\nstruct ib_udata;\n\nstruct ib_device_modify;\n\nstruct ib_port_attr;\n\nstruct ib_port_modify;\n\nstruct ib_port_immutable;\n\nstruct rdma_netdev_alloc_params;\n\nunion ib_gid;\n\nstruct ib_ucontext;\n\nstruct rdma_user_mmap_entry;\n\nstruct phys_vec;\n\nstruct rdma_ah_init_attr;\n\nstruct rdma_ah_attr;\n\nstruct ib_srq_init_attr;\n\nstruct ib_srq_attr;\n\nstruct ib_qp_init_attr;\n\nstruct ib_qp_attr;\n\nstruct ib_mr;\n\nstruct ib_dmah;\n\nstruct ib_sge;\n\nstruct ib_mr_status;\n\nstruct ib_mw;\n\nstruct ib_xrcd;\n\nstruct ib_flow;\n\nstruct ib_flow_attr;\n\nstruct ib_flow_action;\n\nstruct ifla_vf_info;\n\nstruct ifla_vf_stats;\n\nstruct ifla_vf_guid;\n\nstruct ib_wq;\n\nstruct ib_wq_init_attr;\n\nstruct ib_wq_attr;\n\nstruct ib_rwq_ind_table;\n\nstruct ib_rwq_ind_table_init_attr;\n\nstruct ib_dm;\n\nstruct ib_dm_alloc_attr;\n\nstruct ib_dm_mr_attr;\n\nstruct rdma_hw_stats;\n\nstruct rdma_counter;\n\nstruct ib_device_ops {\n\tstruct module *owner;\n\tenum rdma_driver_id driver_id;\n\tu32 uverbs_abi_ver;\n\tunsigned int uverbs_no_driver_id_binding: 1;\n\tconst struct attribute_group *device_group;\n\tconst struct attribute_group **port_groups;\n\tint (*post_send)(struct ib_qp *, const struct ib_send_wr *, const struct ib_send_wr **);\n\tint (*post_recv)(struct ib_qp *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tvoid (*drain_rq)(struct ib_qp *);\n\tvoid (*drain_sq)(struct ib_qp *);\n\tint (*poll_cq)(struct ib_cq *, int, struct ib_wc *);\n\tint (*peek_cq)(struct ib_cq *, int);\n\tint (*req_notify_cq)(struct ib_cq *, enum ib_cq_notify_flags);\n\tint (*post_srq_recv)(struct ib_srq *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tint (*process_mad)(struct ib_device *, int, u32, const struct ib_wc *, const struct ib_grh *, const struct ib_mad *, struct ib_mad *, size_t *, u16 *);\n\tint (*query_device)(struct ib_device *, struct ib_device_attr *, struct ib_udata *);\n\tint (*modify_device)(struct ib_device *, int, struct ib_device_modify *);\n\tvoid (*get_dev_fw_str)(struct ib_device *, char *);\n\tconst struct cpumask * (*get_vector_affinity)(struct ib_device *, int);\n\tint (*query_port)(struct ib_device *, u32, struct ib_port_attr *);\n\tint (*query_port_speed)(struct ib_device *, u32, u64 *);\n\tint (*modify_port)(struct ib_device *, u32, int, struct ib_port_modify *);\n\tint (*get_port_immutable)(struct ib_device *, u32, struct ib_port_immutable *);\n\tenum rdma_link_layer (*get_link_layer)(struct ib_device *, u32);\n\tstruct net_device * (*get_netdev)(struct ib_device *, u32);\n\tstruct net_device * (*alloc_rdma_netdev)(struct ib_device *, u32, enum rdma_netdev_t, const char *, unsigned char, void (*)(struct net_device *));\n\tint (*rdma_netdev_get_params)(struct ib_device *, u32, enum rdma_netdev_t, struct rdma_netdev_alloc_params *);\n\tint (*query_gid)(struct ib_device *, u32, int, union ib_gid *);\n\tint (*add_gid)(const struct ib_gid_attr *, void **);\n\tint (*del_gid)(const struct ib_gid_attr *, void **);\n\tint (*query_pkey)(struct ib_device *, u32, u16, u16 *);\n\tint (*alloc_ucontext)(struct ib_ucontext *, struct ib_udata *);\n\tvoid (*dealloc_ucontext)(struct ib_ucontext *);\n\tint (*mmap)(struct ib_ucontext *, struct vm_area_struct *);\n\tvoid (*mmap_free)(struct rdma_user_mmap_entry *);\n\tint (*mmap_get_pfns)(struct rdma_user_mmap_entry *, struct phys_vec *, struct p2pdma_provider **);\n\tstruct rdma_user_mmap_entry * (*pgoff_to_mmap_entry)(struct ib_ucontext *, off_t);\n\tvoid (*disassociate_ucontext)(struct ib_ucontext *);\n\tint (*alloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*dealloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*create_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*create_user_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*modify_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*query_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*destroy_ah)(struct ib_ah *, u32);\n\tint (*create_srq)(struct ib_srq *, struct ib_srq_init_attr *, struct ib_udata *);\n\tint (*modify_srq)(struct ib_srq *, struct ib_srq_attr *, enum ib_srq_attr_mask, struct ib_udata *);\n\tint (*query_srq)(struct ib_srq *, struct ib_srq_attr *);\n\tint (*destroy_srq)(struct ib_srq *, struct ib_udata *);\n\tint (*create_qp)(struct ib_qp *, struct ib_qp_init_attr *, struct ib_udata *);\n\tint (*modify_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);\n\tint (*query_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_qp_init_attr *);\n\tint (*destroy_qp)(struct ib_qp *, struct ib_udata *);\n\tint (*create_cq)(struct ib_cq *, const struct ib_cq_init_attr *, struct uverbs_attr_bundle *);\n\tint (*create_cq_umem)(struct ib_cq *, const struct ib_cq_init_attr *, struct ib_umem *, struct uverbs_attr_bundle *);\n\tint (*modify_cq)(struct ib_cq *, u16, u16);\n\tint (*destroy_cq)(struct ib_cq *, struct ib_udata *);\n\tint (*resize_cq)(struct ib_cq *, int, struct ib_udata *);\n\tint (*pre_destroy_cq)(struct ib_cq *);\n\tvoid (*post_destroy_cq)(struct ib_cq *);\n\tstruct ib_mr * (*get_dma_mr)(struct ib_pd *, int);\n\tstruct ib_mr * (*reg_user_mr)(struct ib_pd *, u64, u64, u64, int, struct ib_dmah *, struct ib_udata *);\n\tstruct ib_mr * (*reg_user_mr_dmabuf)(struct ib_pd *, u64, u64, u64, int, int, struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*rereg_user_mr)(struct ib_mr *, int, u64, u64, u64, int, struct ib_pd *, struct ib_udata *);\n\tint (*dereg_mr)(struct ib_mr *, struct ib_udata *);\n\tstruct ib_mr * (*alloc_mr)(struct ib_pd *, enum ib_mr_type, u32);\n\tstruct ib_mr * (*alloc_mr_integrity)(struct ib_pd *, u32, u32);\n\tint (*advise_mr)(struct ib_pd *, enum ib_uverbs_advise_mr_advice, u32, struct ib_sge *, u32, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg)(struct ib_mr *, struct scatterlist *, int, unsigned int *);\n\tint (*check_mr_status)(struct ib_mr *, u32, struct ib_mr_status *);\n\tint (*alloc_mw)(struct ib_mw *, struct ib_udata *);\n\tint (*dealloc_mw)(struct ib_mw *);\n\tint (*attach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*detach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*alloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tint (*dealloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tstruct ib_flow * (*create_flow)(struct ib_qp *, struct ib_flow_attr *, struct ib_udata *);\n\tint (*destroy_flow)(struct ib_flow *);\n\tint (*destroy_flow_action)(struct ib_flow_action *);\n\tint (*set_vf_link_state)(struct ib_device *, int, u32, int);\n\tint (*get_vf_config)(struct ib_device *, int, u32, struct ifla_vf_info *);\n\tint (*get_vf_stats)(struct ib_device *, int, u32, struct ifla_vf_stats *);\n\tint (*get_vf_guid)(struct ib_device *, int, u32, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*set_vf_guid)(struct ib_device *, int, u32, u64, int);\n\tstruct ib_wq * (*create_wq)(struct ib_pd *, struct ib_wq_init_attr *, struct ib_udata *);\n\tint (*destroy_wq)(struct ib_wq *, struct ib_udata *);\n\tint (*modify_wq)(struct ib_wq *, struct ib_wq_attr *, u32, struct ib_udata *);\n\tint (*create_rwq_ind_table)(struct ib_rwq_ind_table *, struct ib_rwq_ind_table_init_attr *, struct ib_udata *);\n\tint (*destroy_rwq_ind_table)(struct ib_rwq_ind_table *);\n\tstruct ib_dm * (*alloc_dm)(struct ib_device *, struct ib_ucontext *, struct ib_dm_alloc_attr *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dm)(struct ib_dm *, struct uverbs_attr_bundle *);\n\tint (*alloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*reg_dm_mr)(struct ib_pd *, struct ib_dm *, struct ib_dm_mr_attr *, struct uverbs_attr_bundle *);\n\tint (*create_counters)(struct ib_counters *, struct uverbs_attr_bundle *);\n\tint (*destroy_counters)(struct ib_counters *);\n\tint (*read_counters)(struct ib_counters *, struct ib_counters_read_attr *, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg_pi)(struct ib_mr *, struct scatterlist *, int, unsigned int *, struct scatterlist *, int, unsigned int *);\n\tstruct rdma_hw_stats * (*alloc_hw_device_stats)(struct ib_device *);\n\tstruct rdma_hw_stats * (*alloc_hw_port_stats)(struct ib_device *, u32);\n\tint (*get_hw_stats)(struct ib_device *, struct rdma_hw_stats *, u32, int);\n\tint (*modify_hw_stat)(struct ib_device *, u32, unsigned int, bool);\n\tint (*fill_res_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_mr_entry_raw)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_cq_entry)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_cq_entry_raw)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_qp_entry)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_qp_entry_raw)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_cm_id_entry)(struct sk_buff *, struct rdma_cm_id *);\n\tint (*fill_res_srq_entry)(struct sk_buff *, struct ib_srq *);\n\tint (*fill_res_srq_entry_raw)(struct sk_buff *, struct ib_srq *);\n\tint (*enable_driver)(struct ib_device *);\n\tvoid (*dealloc_driver)(struct ib_device *);\n\tvoid (*iw_add_ref)(struct ib_qp *);\n\tvoid (*iw_rem_ref)(struct ib_qp *);\n\tstruct ib_qp * (*iw_get_qp)(struct ib_device *, int);\n\tint (*iw_connect)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_accept)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_reject)(struct iw_cm_id *, const void *, u8);\n\tint (*iw_create_listen)(struct iw_cm_id *, int);\n\tint (*iw_destroy_listen)(struct iw_cm_id *);\n\tint (*counter_bind_qp)(struct rdma_counter *, struct ib_qp *, u32);\n\tint (*counter_unbind_qp)(struct ib_qp *, u32);\n\tint (*counter_dealloc)(struct rdma_counter *);\n\tstruct rdma_hw_stats * (*counter_alloc_stats)(struct rdma_counter *);\n\tint (*counter_update_stats)(struct rdma_counter *);\n\tvoid (*counter_init)(struct rdma_counter *);\n\tint (*fill_stat_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*query_ucontext)(struct ib_ucontext *, struct uverbs_attr_bundle *);\n\tint (*get_numa_node)(struct ib_device *);\n\tstruct ib_device * (*add_sub_dev)(struct ib_device *, enum rdma_nl_dev_type, const char *);\n\tvoid (*del_sub_dev)(struct ib_device *);\n\tvoid (*ufile_hw_cleanup)(struct ib_uverbs_file *);\n\tvoid (*report_port_event)(struct ib_device *, struct net_device *, long unsigned int);\n\tsize_t size_ib_ah;\n\tsize_t size_ib_counters;\n\tsize_t size_ib_cq;\n\tsize_t size_ib_dmah;\n\tsize_t size_ib_mw;\n\tsize_t size_ib_pd;\n\tsize_t size_ib_qp;\n\tsize_t size_ib_rwq_ind_table;\n\tsize_t size_ib_srq;\n\tsize_t size_ib_ucontext;\n\tsize_t size_ib_xrcd;\n\tsize_t size_rdma_counter;\n};\n\nstruct ib_odp_caps {\n\tuint64_t general_caps;\n\tstruct {\n\t\tuint32_t rc_odp_caps;\n\t\tuint32_t uc_odp_caps;\n\t\tuint32_t ud_odp_caps;\n\t\tuint32_t xrc_odp_caps;\n\t} per_transport_caps;\n};\n\nstruct ib_rss_caps {\n\tu32 supported_qpts;\n\tu32 max_rwq_indirection_tables;\n\tu32 max_rwq_indirection_table_size;\n};\n\nstruct ib_tm_caps {\n\tu32 max_rndv_hdr_size;\n\tu32 max_num_tags;\n\tu32 flags;\n\tu32 max_ops;\n\tu32 max_sge;\n};\n\nstruct ib_device_attr {\n\tu64 fw_ver;\n\t__be64 sys_image_guid;\n\tu64 max_mr_size;\n\tu64 page_size_cap;\n\tu32 vendor_id;\n\tu32 vendor_part_id;\n\tu32 hw_ver;\n\tint max_qp;\n\tint max_qp_wr;\n\tlong: 32;\n\tu64 device_cap_flags;\n\tu64 kernel_cap_flags;\n\tint max_send_sge;\n\tint max_recv_sge;\n\tint max_sge_rd;\n\tint max_cq;\n\tint max_cqe;\n\tint max_mr;\n\tint max_pd;\n\tint max_qp_rd_atom;\n\tint max_ee_rd_atom;\n\tint max_res_rd_atom;\n\tint max_qp_init_rd_atom;\n\tint max_ee_init_rd_atom;\n\tenum ib_atomic_cap atomic_cap;\n\tenum ib_atomic_cap masked_atomic_cap;\n\tint max_ee;\n\tint max_rdd;\n\tint max_mw;\n\tint max_raw_ipv6_qp;\n\tint max_raw_ethy_qp;\n\tint max_mcast_grp;\n\tint max_mcast_qp_attach;\n\tint max_total_mcast_qp_attach;\n\tint max_ah;\n\tint max_srq;\n\tint max_srq_wr;\n\tint max_srq_sge;\n\tunsigned int max_fast_reg_page_list_len;\n\tunsigned int max_pi_fast_reg_page_list_len;\n\tu16 max_pkeys;\n\tu8 local_ca_ack_delay;\n\tint sig_prot_cap;\n\tint sig_guard_cap;\n\tlong: 32;\n\tstruct ib_odp_caps odp_caps;\n\tuint64_t timestamp_mask;\n\tuint64_t hca_core_clock;\n\tstruct ib_rss_caps rss_caps;\n\tu32 max_wq_type_rq;\n\tu32 raw_packet_caps;\n\tstruct ib_tm_caps tm_caps;\n\tstruct ib_cq_caps cq_caps;\n\tlong: 32;\n\tu64 max_dm_size;\n\tu32 max_sgl_rd;\n\tlong: 32;\n};\n\nstruct hw_stats_device_data;\n\nstruct rdma_restrack_root;\n\nstruct uapi_definition;\n\nstruct ib_port_data;\n\nstruct rdma_link_ops;\n\nstruct ib_device {\n\tstruct device *dma_device;\n\tstruct ib_device_ops ops;\n\tchar name[64];\n\tstruct callback_head callback_head;\n\tstruct list_head event_handler_list;\n\tstruct rw_semaphore event_handler_rwsem;\n\tspinlock_t qp_open_list_lock;\n\tstruct rw_semaphore client_data_rwsem;\n\tstruct xarray client_data;\n\tstruct mutex unregistration_lock;\n\trwlock_t cache_lock;\n\tstruct ib_port_data *port_data;\n\tint num_comp_vectors;\n\tlong: 32;\n\tunion {\n\t\tstruct device dev;\n\t\tstruct ib_core_device coredev;\n\t};\n\tconst struct attribute_group *groups[4];\n\tu8 hw_stats_attr_index;\n\tlong: 32;\n\tu64 uverbs_cmd_mask;\n\tchar node_desc[64];\n\t__be64 node_guid;\n\tu32 local_dma_lkey;\n\tu16 is_switch: 1;\n\tu16 kverbs_provider: 1;\n\tu16 use_cq_dim: 1;\n\tu8 node_type;\n\tu32 phys_port_cnt;\n\tlong: 32;\n\tstruct ib_device_attr attrs;\n\tstruct hw_stats_device_data *hw_stats_data;\n\tu32 index;\n\tspinlock_t cq_pools_lock;\n\tstruct list_head cq_pools[3];\n\tstruct rdma_restrack_root *res;\n\tconst struct uapi_definition *driver_def;\n\trefcount_t refcount;\n\tstruct completion unreg_completion;\n\tstruct work_struct unregistration_work;\n\tconst struct rdma_link_ops *link_ops;\n\tstruct mutex compat_devs_mutex;\n\tstruct xarray compat_devs;\n\tchar iw_ifname[16];\n\tu32 iw_driver_flags;\n\tu32 lag_flags;\n\tstruct mutex subdev_lock;\n\tstruct list_head subdev_list_head;\n\tenum rdma_nl_dev_type type;\n\tstruct ib_device *parent;\n\tstruct list_head subdev_list;\n\tenum rdma_nl_name_assign_type name_assign_type;\n\tlong: 32;\n};\n\nstruct ib_device_modify {\n\tu64 sys_image_guid;\n\tchar node_desc[64];\n};\n\nstruct ib_dm {\n\tstruct ib_device *device;\n\tu32 length;\n\tu32 flags;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_dm_alloc_attr {\n\tu64 length;\n\tu32 alignment;\n\tu32 flags;\n};\n\nstruct ib_dm_mr_attr {\n\tu64 length;\n\tu64 offset;\n\tu32 access_flags;\n\tlong: 32;\n};\n\nstruct ib_dmah {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tstruct rdma_restrack_entry res;\n\tu32 cpu_id;\n\tenum tph_mem_type mem_type;\n\tatomic_t usecnt;\n\tu8 ph;\n\tu8 valid_fields;\n};\n\nstruct ib_event {\n\tstruct ib_device *device;\n\tunion {\n\t\tstruct ib_cq *cq;\n\t\tstruct ib_qp *qp;\n\t\tstruct ib_srq *srq;\n\t\tstruct ib_wq *wq;\n\t\tu32 port_num;\n\t} element;\n\tenum ib_event_type event;\n};\n\nstruct ib_flow {\n\tstruct ib_qp *qp;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n};\n\nstruct ib_flow_action {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tenum ib_flow_action_type type;\n\tatomic_t usecnt;\n};\n\nstruct ib_flow_eth_filter {\n\tu8 dst_mac[6];\n\tu8 src_mac[6];\n\t__be16 ether_type;\n\t__be16 vlan_tag;\n};\n\nstruct ib_flow_spec_eth {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_eth_filter val;\n\tstruct ib_flow_eth_filter mask;\n};\n\nstruct ib_flow_ib_filter {\n\t__be16 dlid;\n\t__u8 sl;\n};\n\nstruct ib_flow_spec_ib {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ib_filter val;\n\tstruct ib_flow_ib_filter mask;\n};\n\nstruct ib_flow_ipv4_filter {\n\t__be32 src_ip;\n\t__be32 dst_ip;\n\tu8 proto;\n\tu8 tos;\n\tu8 ttl;\n\tu8 flags;\n};\n\nstruct ib_flow_spec_ipv4 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv4_filter val;\n\tstruct ib_flow_ipv4_filter mask;\n};\n\nstruct ib_flow_tcp_udp_filter {\n\t__be16 dst_port;\n\t__be16 src_port;\n};\n\nstruct ib_flow_spec_tcp_udp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tcp_udp_filter val;\n\tstruct ib_flow_tcp_udp_filter mask;\n};\n\nstruct ib_flow_ipv6_filter {\n\tu8 src_ip[16];\n\tu8 dst_ip[16];\n\t__be32 flow_label;\n\tu8 next_hdr;\n\tu8 traffic_class;\n\tu8 hop_limit;\n} __attribute__((packed));\n\nstruct ib_flow_spec_ipv6 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv6_filter val;\n\tstruct ib_flow_ipv6_filter mask;\n};\n\nstruct ib_flow_tunnel_filter {\n\t__be32 tunnel_id;\n};\n\nstruct ib_flow_spec_tunnel {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tunnel_filter val;\n\tstruct ib_flow_tunnel_filter mask;\n};\n\nstruct ib_flow_esp_filter {\n\t__be32 spi;\n\t__be32 seq;\n};\n\nstruct ib_flow_spec_esp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_esp_filter val;\n\tstruct ib_flow_esp_filter mask;\n};\n\nstruct ib_flow_gre_filter {\n\t__be16 c_ks_res0_ver;\n\t__be16 protocol;\n\t__be32 key;\n};\n\nstruct ib_flow_spec_gre {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_gre_filter val;\n\tstruct ib_flow_gre_filter mask;\n};\n\nstruct ib_flow_mpls_filter {\n\t__be32 tag;\n};\n\nstruct ib_flow_spec_mpls {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_mpls_filter val;\n\tstruct ib_flow_mpls_filter mask;\n};\n\nstruct ib_flow_spec_action_tag {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tu32 tag_id;\n};\n\nstruct ib_flow_spec_action_drop {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n};\n\nstruct ib_flow_spec_action_handle {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_flow_action *act;\n};\n\nstruct ib_flow_spec_action_count {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_counters *counters;\n};\n\nunion ib_flow_spec {\n\tstruct {\n\t\tu32 type;\n\t\tu16 size;\n\t};\n\tstruct ib_flow_spec_eth eth;\n\tstruct ib_flow_spec_ib ib;\n\tstruct ib_flow_spec_ipv4 ipv4;\n\tstruct ib_flow_spec_tcp_udp tcp_udp;\n\tstruct ib_flow_spec_ipv6 ipv6;\n\tstruct ib_flow_spec_tunnel tunnel;\n\tstruct ib_flow_spec_esp esp;\n\tstruct ib_flow_spec_gre gre;\n\tstruct ib_flow_spec_mpls mpls;\n\tstruct ib_flow_spec_action_tag flow_tag;\n\tstruct ib_flow_spec_action_drop drop;\n\tstruct ib_flow_spec_action_handle action;\n\tstruct ib_flow_spec_action_count flow_count;\n};\n\nstruct ib_flow_attr {\n\tenum ib_flow_attr_type type;\n\tu16 size;\n\tu16 priority;\n\tu32 flags;\n\tu8 num_of_specs;\n\tu32 port;\n\tunion ib_flow_spec flows[0];\n};\n\nunion ib_gid {\n\tu8 raw[16];\n\tstruct {\n\t\t__be64 subnet_prefix;\n\t\t__be64 interface_id;\n\t} global;\n};\n\nstruct ib_gid_attr {\n\tstruct net_device *ndev;\n\tstruct ib_device *device;\n\tunion ib_gid gid;\n\tenum ib_gid_type gid_type;\n\tu16 index;\n\tu32 port_num;\n\tlong: 32;\n};\n\nstruct ib_global_route {\n\tconst struct ib_gid_attr *sgid_attr;\n\tlong: 32;\n\tunion ib_gid dgid;\n\tu32 flow_label;\n\tu8 sgid_index;\n\tu8 hop_limit;\n\tu8 traffic_class;\n};\n\nstruct ib_grh {\n\t__be32 version_tclass_flow;\n\t__be16 paylen;\n\tu8 next_hdr;\n\tu8 hop_limit;\n\tunion ib_gid sgid;\n\tunion ib_gid dgid;\n};\n\nstruct ib_sig_attrs;\n\nstruct ib_mr {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tu32 lkey;\n\tu32 rkey;\n\tu64 iova;\n\tu64 length;\n\tunsigned int page_size;\n\tenum ib_mr_type type;\n\tbool need_inval;\n\tunion {\n\t\tstruct ib_uobject *uobject;\n\t\tstruct list_head qp_entry;\n\t};\n\tstruct ib_dm *dm;\n\tstruct ib_sig_attrs *sig_attrs;\n\tstruct ib_dmah *dmah;\n\tstruct rdma_restrack_entry res;\n\tlong: 32;\n};\n\nstruct ib_sig_err {\n\tenum ib_sig_err_type err_type;\n\tu32 expected;\n\tu32 actual;\n\tlong: 32;\n\tu64 sig_err_offset;\n\tu32 key;\n\tlong: 32;\n};\n\nstruct ib_mr_status {\n\tu32 fail_status;\n\tlong: 32;\n\tstruct ib_sig_err sig_err;\n};\n\nstruct ib_mw {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tu32 rkey;\n\tenum ib_mw_type type;\n};\n\nstruct ib_pd {\n\tu32 local_dma_lkey;\n\tu32 flags;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 unsafe_global_rkey;\n\tstruct ib_mr *__internal_mr;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_port_attr {\n\tu64 subnet_prefix;\n\tenum ib_port_state state;\n\tenum ib_mtu max_mtu;\n\tenum ib_mtu active_mtu;\n\tu32 phys_mtu;\n\tint gid_tbl_len;\n\tunsigned int ip_gids: 1;\n\tu32 port_cap_flags;\n\tu32 max_msg_sz;\n\tu32 bad_pkey_cntr;\n\tu32 qkey_viol_cntr;\n\tu16 pkey_tbl_len;\n\tu32 sm_lid;\n\tu32 lid;\n\tu8 lmc;\n\tu8 max_vl_num;\n\tu8 sm_sl;\n\tu8 subnet_timeout;\n\tu8 init_type_reply;\n\tu8 active_width;\n\tu16 active_speed;\n\tu8 phys_state;\n\tu16 port_cap_flags2;\n};\n\nstruct ib_pkey_cache;\n\nstruct ib_gid_table;\n\nstruct ib_port_cache {\n\tu64 subnet_prefix;\n\tstruct ib_pkey_cache *pkey;\n\tstruct ib_gid_table *gid;\n\tu8 lmc;\n\tenum ib_port_state port_state;\n\tenum ib_port_state last_port_state;\n\tlong: 32;\n};\n\nstruct ib_port_immutable {\n\tint pkey_tbl_len;\n\tint gid_tbl_len;\n\tu32 core_cap_flags;\n\tu32 max_mad_size;\n};\n\nstruct rdma_counter_mode {\n\tenum rdma_nl_counter_mode mode;\n\tenum rdma_nl_counter_mask mask;\n\tstruct auto_mode_param param;\n\tbool bind_opcnt;\n};\n\nstruct rdma_port_counter {\n\tstruct rdma_counter_mode mode;\n\tstruct rdma_hw_stats *hstats;\n\tunsigned int num_counters;\n\tstruct mutex lock;\n};\n\nstruct ib_port;\n\nstruct ib_port_data {\n\tstruct ib_device *ib_dev;\n\tstruct ib_port_immutable immutable;\n\tspinlock_t pkey_list_lock;\n\tspinlock_t netdev_lock;\n\tstruct list_head pkey_list;\n\tlong: 32;\n\tstruct ib_port_cache cache;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\tstruct hlist_node ndev_hash_link;\n\tstruct rdma_port_counter port_counter;\n\tstruct ib_port *sysfs;\n};\n\nstruct ib_port_modify {\n\tu32 set_port_cap_mask;\n\tu32 clr_port_cap_mask;\n\tu8 init_type;\n};\n\nstruct ib_qp_security;\n\nstruct ib_port_pkey {\n\tenum port_pkey_state state;\n\tu16 pkey_index;\n\tu32 port_num;\n\tstruct list_head qp_list;\n\tstruct list_head to_error_list;\n\tstruct ib_qp_security *sec;\n};\n\nstruct ib_ports_pkeys {\n\tstruct ib_port_pkey main;\n\tstruct ib_port_pkey alt;\n};\n\nstruct ib_uqp_object;\n\nstruct ib_qp {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tspinlock_t mr_lock;\n\tint mrs_used;\n\tstruct list_head rdma_mrs;\n\tstruct list_head sig_mrs;\n\tstruct ib_srq *srq;\n\tstruct completion srq_completion;\n\tstruct ib_xrcd *xrcd;\n\tstruct list_head xrcd_list;\n\tatomic_t usecnt;\n\tstruct list_head open_list;\n\tstruct ib_qp *real_qp;\n\tstruct ib_uqp_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid (*registered_event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tconst struct ib_gid_attr *av_sgid_attr;\n\tconst struct ib_gid_attr *alt_path_sgid_attr;\n\tu32 qp_num;\n\tu32 max_write_sge;\n\tu32 max_read_sge;\n\tenum ib_qp_type qp_type;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tstruct ib_qp_security *qp_sec;\n\tu32 port;\n\tbool integrity_en;\n\tstruct rdma_restrack_entry res;\n\tstruct rdma_counter *counter;\n};\n\nstruct ib_qp_cap {\n\tu32 max_send_wr;\n\tu32 max_recv_wr;\n\tu32 max_send_sge;\n\tu32 max_recv_sge;\n\tu32 max_inline_data;\n\tu32 max_rdma_ctxs;\n};\n\nstruct roce_ah_attr {\n\tu8 dmac[6];\n};\n\nstruct opa_ah_attr {\n\tu32 dlid;\n\tu8 src_path_bits;\n\tbool make_grd;\n};\n\nstruct rdma_ah_attr {\n\tstruct ib_global_route grh;\n\tu8 sl;\n\tu8 static_rate;\n\tu32 port_num;\n\tu8 ah_flags;\n\tenum rdma_ah_attr_type type;\n\tunion {\n\t\tstruct ib_ah_attr ib;\n\t\tstruct roce_ah_attr roce;\n\t\tstruct opa_ah_attr opa;\n\t};\n};\n\nstruct ib_qp_attr {\n\tenum ib_qp_state qp_state;\n\tenum ib_qp_state cur_qp_state;\n\tenum ib_mtu path_mtu;\n\tenum ib_mig_state path_mig_state;\n\tu32 qkey;\n\tu32 rq_psn;\n\tu32 sq_psn;\n\tu32 dest_qp_num;\n\tint qp_access_flags;\n\tstruct ib_qp_cap cap;\n\tlong: 32;\n\tstruct rdma_ah_attr ah_attr;\n\tstruct rdma_ah_attr alt_ah_attr;\n\tu16 pkey_index;\n\tu16 alt_pkey_index;\n\tu8 en_sqd_async_notify;\n\tu8 sq_draining;\n\tu8 max_rd_atomic;\n\tu8 max_dest_rd_atomic;\n\tu8 min_rnr_timer;\n\tu32 port_num;\n\tu8 timeout;\n\tu8 retry_cnt;\n\tu8 rnr_retry;\n\tu32 alt_port_num;\n\tu8 alt_timeout;\n\tu32 rate_limit;\n\tstruct net_device *xmit_slave;\n\tlong: 32;\n};\n\nstruct ib_qp_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tstruct ib_srq *srq;\n\tstruct ib_xrcd *xrcd;\n\tstruct ib_qp_cap cap;\n\tenum ib_sig_type sq_sig_type;\n\tenum ib_qp_type qp_type;\n\tu32 create_flags;\n\tu32 port_num;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tu32 source_qpn;\n};\n\nstruct ib_qp_security {\n\tstruct ib_qp *qp;\n\tstruct ib_device *dev;\n\tstruct mutex mutex;\n\tstruct ib_ports_pkeys *ports_pkeys;\n\tstruct list_head shared_qp_list;\n\tvoid *security;\n\tbool destroying;\n\tatomic_t error_list_count;\n\tstruct completion error_complete;\n\tint error_comps_pending;\n};\n\nstruct ib_rdmacg_object {};\n\nstruct ib_recv_wr {\n\tstruct ib_recv_wr *next;\n\tlong: 32;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n};\n\nstruct ib_rwq_ind_table {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 ind_tbl_num;\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_rwq_ind_table_init_attr {\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_send_wr {\n\tstruct ib_send_wr *next;\n\tlong: 32;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n\tenum ib_wr_opcode opcode;\n\tint send_flags;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tlong: 32;\n};\n\nstruct ib_sge {\n\tu64 addr;\n\tu32 length;\n\tu32 lkey;\n};\n\nstruct ib_t10_dif_domain {\n\tenum ib_t10_dif_bg_type bg_type;\n\tu16 pi_interval;\n\tu16 bg;\n\tu16 app_tag;\n\tu32 ref_tag;\n\tbool ref_remap;\n\tbool app_escape;\n\tbool ref_escape;\n\tu16 apptag_check_mask;\n};\n\nstruct ib_sig_domain {\n\tenum ib_signature_type sig_type;\n\tunion {\n\t\tstruct ib_t10_dif_domain dif;\n\t} sig;\n};\n\nstruct ib_sig_attrs {\n\tu8 check_mask;\n\tstruct ib_sig_domain mem;\n\tstruct ib_sig_domain wire;\n\tint meta_length;\n};\n\nstruct ib_usrq_object;\n\nstruct ib_srq {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_usrq_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tenum ib_srq_type srq_type;\n\tatomic_t usecnt;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t\tu32 srq_num;\n\t\t\t} xrc;\n\t\t};\n\t} ext;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_srq_attr {\n\tu32 max_wr;\n\tu32 max_sge;\n\tu32 srq_limit;\n};\n\nstruct ib_srq_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tstruct ib_srq_attr attr;\n\tenum ib_srq_type srq_type;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t} xrc;\n\t\t\tstruct {\n\t\t\t\tu32 max_num_tags;\n\t\t\t} tag_matching;\n\t\t};\n\t} ext;\n};\n\nstruct ib_ucontext {\n\tstruct ib_device *device;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_rdmacg_object cg_obj;\n\tu64 enabled_caps;\n\tstruct rdma_restrack_entry res;\n\tstruct xarray mmap_xa;\n};\n\nstruct ib_udata {\n\tconst void *inbuf;\n\tvoid *outbuf;\n\tsize_t inlen;\n\tsize_t outlen;\n};\n\nstruct uverbs_api_object;\n\nstruct ib_uobject {\n\tu64 user_handle;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_ucontext *context;\n\tvoid *object;\n\tstruct list_head list;\n\tstruct ib_rdmacg_object cg_obj;\n\tint id;\n\tstruct kref ref;\n\tatomic_t usecnt;\n\tstruct callback_head rcu;\n\tconst struct uverbs_api_object *uapi_object;\n\tlong: 32;\n};\n\nstruct ib_wc {\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tenum ib_wc_status status;\n\tenum ib_wc_opcode opcode;\n\tu32 vendor_err;\n\tu32 byte_len;\n\tstruct ib_qp *qp;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tu32 src_qp;\n\tu32 slid;\n\tint wc_flags;\n\tu16 pkey_index;\n\tu8 sl;\n\tu8 dlid_path_bits;\n\tu32 port_num;\n\tu8 smac[6];\n\tu16 vlan_id;\n\tu8 network_hdr_type;\n};\n\nstruct ib_uwq_object;\n\nstruct ib_wq {\n\tstruct ib_device *device;\n\tstruct ib_uwq_object *uobject;\n\tvoid *wq_context;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tstruct ib_pd *pd;\n\tstruct ib_cq *cq;\n\tu32 wq_num;\n\tenum ib_wq_state state;\n\tenum ib_wq_type wq_type;\n\tatomic_t usecnt;\n};\n\nstruct ib_wq_attr {\n\tenum ib_wq_state wq_state;\n\tenum ib_wq_state curr_wq_state;\n\tu32 flags;\n\tu32 flags_mask;\n};\n\nstruct ib_wq_init_attr {\n\tvoid *wq_context;\n\tenum ib_wq_type wq_type;\n\tu32 max_wr;\n\tu32 max_sge;\n\tstruct ib_cq *cq;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tu32 create_flags;\n};\n\nstruct ib_xrcd {\n\tstruct ib_device *device;\n\tatomic_t usecnt;\n\tstruct inode *inode;\n\tstruct rw_semaphore tgt_qps_rwsem;\n\tstruct xarray tgt_qps;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct icmp6_err {\n\tint err;\n\tint fatal;\n};\n\nstruct icmp6_ext_iio_addr6_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\tstruct in6_addr addr6;\n};\n\nstruct icmp6_filter {\n\t__u32 data[8];\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 reserved1: 4;\n\t__u8 version: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[7];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6_msg {\n\tstruct sk_buff *skb;\n\tint offset;\n\tuint8_t type;\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[32];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n\tlong: 32;\n};\n\nstruct idmac_desc {\n\t__le32 des0;\n\t__le32 des1;\n\t__le32 des2;\n\t__le32 des3;\n};\n\nstruct idmac_desc_64addr {\n\tu32 des0;\n\tu32 des1;\n\tu32 des2;\n\tu32 des3;\n\tu32 des4;\n\tu32 des5;\n\tu32 des6;\n\tu32 des7;\n};\n\nstruct idmap_legacy_upcalldata;\n\nstruct idmap {\n\tstruct rpc_pipe_dir_object idmap_pdo;\n\tstruct rpc_pipe *idmap_pipe;\n\tstruct idmap_legacy_upcalldata *idmap_upcall_data;\n\tstruct mutex idmap_mutex;\n\tstruct user_namespace *user_ns;\n};\n\nstruct idmap_key {\n\tbool map_up;\n\tu32 id;\n\tu32 count;\n};\n\nstruct idmap_msg {\n\t__u8 im_type;\n\t__u8 im_conv;\n\tchar im_name[128];\n\t__u32 im_id;\n\t__u8 im_status;\n};\n\nstruct idmap_legacy_upcalldata {\n\tstruct rpc_pipe_msg pipe_msg;\n\tstruct idmap_msg idmap_msg;\n\tstruct key *authkey;\n\tstruct idmap *idmap;\n};\n\nunion ieee754dp {\n\tstruct {\n\t\tu64 mant: 52;\n\t\tunsigned int bexp: 11;\n\t\tunsigned int sign: 1;\n\t};\n\tu64 bits;\n};\n\nunion ieee754sp {\n\tstruct {\n\t\tunsigned int mant: 23;\n\t\tunsigned int bexp: 8;\n\t\tunsigned int sign: 1;\n\t};\n\tu32 bits;\n};\n\nstruct ieee_ets {\n\t__u8 willing;\n\t__u8 ets_cap;\n\t__u8 cbs;\n\t__u8 tc_tx_bw[8];\n\t__u8 tc_rx_bw[8];\n\t__u8 tc_tsa[8];\n\t__u8 prio_tc[8];\n\t__u8 tc_reco_bw[8];\n\t__u8 tc_reco_tsa[8];\n\t__u8 reco_prio_tc[8];\n};\n\nstruct ieee_maxrate {\n\t__u64 tc_maxrate[8];\n};\n\nstruct ieee_pfc {\n\t__u8 pfc_cap;\n\t__u8 pfc_en;\n\t__u8 mbc;\n\t__u16 delay;\n\t__u64 requests[8];\n\t__u64 indications[8];\n};\n\nstruct ieee_qcn {\n\t__u8 rpg_enable[8];\n\t__u32 rppp_max_rps[8];\n\t__u32 rpg_time_reset[8];\n\t__u32 rpg_byte_reset[8];\n\t__u32 rpg_threshold[8];\n\t__u32 rpg_max_rate[8];\n\t__u32 rpg_ai_rate[8];\n\t__u32 rpg_hai_rate[8];\n\t__u32 rpg_gd[8];\n\t__u32 rpg_min_dec_fac[8];\n\t__u32 rpg_min_rate[8];\n\t__u32 cndd_state_machine[8];\n};\n\nstruct ieee_qcn_stats {\n\t__u64 rppp_rp_centiseconds[8];\n\t__u32 rppp_created_rps[8];\n};\n\nstruct if6_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tint offset;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa6_config {\n\tconst struct in6_addr *pfx;\n\tunsigned int plen;\n\tu8 ifa_proto;\n\tconst struct in6_addr *peer_pfx;\n\tu32 rt_priority;\n\tu32 ifa_flags;\n\tu32 preferred_lft;\n\tu32 valid_lft;\n\tu16 scope;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifaddrlblmsg {\n\t__u8 ifal_family;\n\t__u8 __ifal_reserved;\n\t__u8 ifal_prefixlen;\n\t__u8 ifal_flags;\n\t__u32 ifal_index;\n\t__u32 ifal_seq;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifreq;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_cacheinfo {\n\t__u32 max_reasm_len;\n\t__u32 tstamp;\n\t__u32 reachable_time;\n\t__u32 retrans_time;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\tlong: 32;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct inet6_dev;\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct igmp6_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct igmp6_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *im;\n};\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 qrv: 3;\n\t__u8 suppress: 1;\n\t__u8 resv: 4;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct linedisp;\n\nstruct linedisp_ops {\n\tint (*get_map_type)(struct linedisp *);\n\tvoid (*update)(struct linedisp *);\n};\n\nstruct img_ascii_lcd_config {\n\tunsigned int num_chars;\n\tbool external_regmap;\n\tconst struct linedisp_ops ops;\n};\n\nstruct linedisp_map;\n\nstruct linedisp {\n\tstruct device dev;\n\tstruct timer_list timer;\n\tconst struct linedisp_ops *ops;\n\tstruct linedisp_map *map;\n\tchar *buf;\n\tchar *message;\n\tunsigned int num_chars;\n\tunsigned int message_len;\n\tunsigned int scroll_pos;\n\tunsigned int scroll_rate;\n\tunsigned int id;\n};\n\nstruct img_ascii_lcd_ctx {\n\tstruct linedisp linedisp;\n\tunion {\n\t\tvoid *base;\n\t\tstruct regmap *regmap;\n\t};\n\tu32 offset;\n};\n\nstruct img_hash_dev;\n\nstruct img_hash_ctx {\n\tstruct img_hash_dev *hdev;\n\tlong unsigned int flags;\n\tstruct crypto_ahash *fallback;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct img_hash_dev {\n\tstruct list_head list;\n\tstruct device *dev;\n\tstruct clk *hash_clk;\n\tstruct clk *sys_clk;\n\tvoid *io_base;\n\tphys_addr_t bus_addr;\n\tvoid *cpu_addr;\n\tspinlock_t lock;\n\tint err;\n\tstruct tasklet_struct done_task;\n\tstruct tasklet_struct dma_task;\n\tlong unsigned int flags;\n\tstruct crypto_queue queue;\n\tstruct ahash_request *req;\n\tstruct dma_chan *dma_lch;\n};\n\nstruct img_hash_drv {\n\tstruct list_head dev_list;\n\tspinlock_t lock;\n};\n\nstruct img_hash_request_ctx {\n\tstruct img_hash_dev *hdev;\n\tu8 digest[32];\n\tlong unsigned int flags;\n\tsize_t digsize;\n\tdma_addr_t dma_addr;\n\tsize_t dma_ct;\n\tstruct scatterlist *sgfirst;\n\tstruct scatterlist *sg;\n\tsize_t nents;\n\tsize_t offset;\n\tunsigned int total;\n\tsize_t sent;\n\tlong unsigned int op;\n\tsize_t bufcnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ahash_request fallback_req;\n\tu8 buffer[0];\n};\n\nstruct img_i2c {\n\tstruct i2c_adapter adap;\n\tvoid *base;\n\tstruct clk *scb_clk;\n\tstruct clk *sys_clk;\n\tunsigned int bitrate;\n\tbool need_wr_rd_fence;\n\tstruct completion msg_complete;\n\tspinlock_t lock;\n\tstruct i2c_msg msg;\n\tbool last_msg;\n\tint msg_status;\n\tenum img_i2c_mode mode;\n\tu32 int_enable;\n\tu32 line_status;\n\tstruct timer_list check_timer;\n\tbool t_halt;\n\tbool at_t_done;\n\tbool at_slave_event;\n\tint at_cur_cmd;\n\tu8 at_cur_data;\n\tu8 *seq;\n\tunsigned int raw_timeout;\n};\n\nstruct img_i2c_timings {\n\tconst char *name;\n\tunsigned int max_bitrate;\n\tunsigned int tckh;\n\tunsigned int tckl;\n\tunsigned int tsdh;\n\tunsigned int tsdl;\n\tunsigned int tp2s;\n\tunsigned int tpl;\n\tunsigned int tph;\n};\n\nstruct in6_flowlabel_req {\n\tstruct in6_addr flr_dst;\n\t__be32 flr_label;\n\t__u8 flr_action;\n\t__u8 flr_share;\n\t__u16 flr_flags;\n\t__u16 flr_expires;\n\t__u16 flr_linger;\n\t__u32 __flr_pad;\n};\n\nstruct in6_ifreq {\n\tstruct in6_addr ifr6_addr;\n\t__u32 ifr6_prefixlen;\n\tint ifr6_ifindex;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\t__u32 rtmsg_type;\n\t__u16 rtmsg_dst_len;\n\t__u16 rtmsg_src_len;\n\t__u32 rtmsg_metric;\n\tlong unsigned int rtmsg_info;\n\t__u32 rtmsg_flags;\n\tint rtmsg_ifindex;\n};\n\nstruct in6_validator_info {\n\tstruct in6_addr i6vi_addr;\n\tstruct inet6_dev *i6vi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[2];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv6_txoptions;\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n\tu8 dontfrag: 1;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n\tenum addr_type_t type;\n\tbool force_rt_scope_universe;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\tlong: 32;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_skb_parm;\n\nstruct inet6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tshort unsigned int addr_type;\n\tstruct in6_addr v6_rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n\tlong: 32;\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u16 offset;\n\t__u16 size;\n};\n\nstruct sock_cgroup_data {};\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct socket;\n\nstruct sock_reuseport;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\tstruct mem_cgroup *sk_memcg;\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tnetdev_features_t sk_route_caps;\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tlong: 32;\n\tktime_t sk_stamp;\n\tseqlock_t sk_stamp_seq;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n\tlong: 32;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n\tstruct inet6_cork base6;\n};\n\nstruct ipv6_pinfo;\n\nstruct ipv6_fl_socklist;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_diag_bc_op {\n\tunsigned char code;\n\tunsigned char yes;\n\tshort unsigned int no;\n};\n\nstruct inet_diag_dump_data {\n\tstruct nlattr *req_nlas[4];\n\tstruct bpf_sk_storage_diag *bpf_stg_diag;\n\tbool mark_needed;\n\tbool userlocks_needed;\n};\n\nstruct inet_diag_entry {\n\tconst __be32 *saddr;\n\tconst __be32 *daddr;\n\tu16 sport;\n\tu16 dport;\n\tu16 family;\n\tu16 userlocks;\n\tu32 ifindex;\n\tu32 mark;\n};\n\nstruct inet_diag_req_v2;\n\nstruct inet_diag_msg;\n\nstruct inet_diag_handler {\n\tstruct module *owner;\n\tvoid (*dump)(struct sk_buff *, struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tint (*dump_one)(struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tvoid (*idiag_get_info)(struct sock *, struct inet_diag_msg *, void *);\n\tint (*idiag_get_aux)(struct sock *, bool, struct sk_buff *);\n\tint (*destroy)(struct sk_buff *, const struct inet_diag_req_v2 *);\n\t__u16 idiag_type;\n\t__u16 idiag_info_size;\n};\n\nstruct inet_diag_hostcond {\n\t__u8 family;\n\t__u8 prefix_len;\n\tint port;\n\t__be32 addr[0];\n};\n\nstruct inet_diag_markcond {\n\t__u32 mark;\n\t__u32 mask;\n};\n\nstruct inet_diag_meminfo {\n\t__u32 idiag_rmem;\n\t__u32 idiag_wmem;\n\t__u32 idiag_fmem;\n\t__u32 idiag_tmem;\n};\n\nstruct inet_diag_sockid {\n\t__be16 idiag_sport;\n\t__be16 idiag_dport;\n\t__be32 idiag_src[4];\n\t__be32 idiag_dst[4];\n\t__u32 idiag_if;\n\t__u32 idiag_cookie[2];\n};\n\nstruct inet_diag_msg {\n\t__u8 idiag_family;\n\t__u8 idiag_state;\n\t__u8 idiag_timer;\n\t__u8 idiag_retrans;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_expires;\n\t__u32 idiag_rqueue;\n\t__u32 idiag_wqueue;\n\t__u32 idiag_uid;\n\t__u32 idiag_inode;\n};\n\nstruct inet_diag_req {\n\t__u8 idiag_family;\n\t__u8 idiag_src_len;\n\t__u8 idiag_dst_len;\n\t__u8 idiag_ext;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_states;\n\t__u32 idiag_dbs;\n};\n\nstruct inet_diag_req_v2 {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u8 idiag_ext;\n\t__u8 pad;\n\t__u32 idiag_states;\n\tstruct inet_diag_sockid id;\n};\n\nstruct inet_diag_sockopt {\n\t__u8 recverr: 1;\n\t__u8 is_icsk: 1;\n\t__u8 freebind: 1;\n\t__u8 hdrincl: 1;\n\t__u8 mc_loop: 1;\n\t__u8 transparent: 1;\n\t__u8 mc_all: 1;\n\t__u8 nodefrag: 1;\n\t__u8 bind_address_no_port: 1;\n\t__u8 recverr_rfc4884: 1;\n\t__u8 defer_connect: 1;\n\t__u8 unused: 5;\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct proto_ops;\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n\tlong: 32;\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct inode_switch_wbs_context {\n\tstruct llist_node list;\n\tstruct inode *inodes[0];\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[24];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[2];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[4];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[24];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tlong: 32;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n\tlong: 32;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[24];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[2];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[4];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_led {\n\tstruct led_classdev cdev;\n\tstruct input_handle *handle;\n\tunsigned int code;\n};\n\nstruct input_leds {\n\tstruct input_handle handle;\n\tunsigned int num_leds;\n\tstruct input_led leds[0];\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insn {\n\tu32 match;\n\tenum fields fields;\n};\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nstruct intel_host {\n\tu32 dsm_fns;\n\tint drv_strength;\n\tbool d3_retune;\n\tbool rpm_retune_ok;\n\tbool needs_pwr_off;\n\tu32 glk_rx_ctrl1;\n\tu32 glk_tun_val;\n\tu32 active_ltr;\n\tu32 idle_ltr;\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tlong: 32;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tlong: 32;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n\tlong: 32;\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tlong: 32;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tlong: 32;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n\tlong: 32;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tlong: 32;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n\tspinlock_t lock;\n\tstruct xarray icq_tree;\n\tstruct io_cq *icq_hint;\n\tstruct hlist_head icq_list;\n\tstruct work_struct release_work;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tlong: 32;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n\tlong: 32;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tlong: 32;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n\tlong: 32;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tlong: 32;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tlong: 32;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tlong: 32;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tlong: 32;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n\tlong: 32;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n\tlong: 32;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tlong: 32;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\tlong: 32;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[2];\n\tlong unsigned int sqe_op[3];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tlong: 32;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tlong: 32;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n\tlong: 32;\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tlong: 32;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tlong: 32;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n\tlong: 32;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n\tlong: 32;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tlong: 32;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tlong: 32;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tlong: 32;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tlong: 32;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tlong: 32;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[32];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ioam6_hdr {\n\t__u8 opt_type;\n\t__u8 opt_len;\n\tchar: 8;\n\t__u8 type;\n};\n\nstruct ioam6_schema;\n\nstruct ioam6_namespace {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_schema *schema;\n\t__be16 id;\n\t__be32 data;\n\t__be64 data_wide;\n};\n\nstruct ioam6_pernet_data {\n\tstruct mutex lock;\n\tstruct rhashtable namespaces;\n\tstruct rhashtable schemas;\n};\n\nstruct ioam6_schema {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_namespace *ns;\n\tu32 id;\n\tint len;\n\t__be32 hdr;\n\tu8 data[0];\n};\n\nstruct ioam6_trace_hdr {\n\t__be16 namespace_id;\n\tchar: 2;\n\t__u8 overflow: 1;\n\t__u8 nodelen: 5;\n\t__u8 remlen: 7;\n\tunion {\n\t\t__be32 type_be32;\n\t\tstruct {\n\t\t\t__u32 bit7: 1;\n\t\t\t__u32 bit6: 1;\n\t\t\t__u32 bit5: 1;\n\t\t\t__u32 bit4: 1;\n\t\t\t__u32 bit3: 1;\n\t\t\t__u32 bit2: 1;\n\t\t\t__u32 bit1: 1;\n\t\t\t__u32 bit0: 1;\n\t\t\t__u32 bit15: 1;\n\t\t\t__u32 bit14: 1;\n\t\t\t__u32 bit13: 1;\n\t\t\t__u32 bit12: 1;\n\t\t\t__u32 bit11: 1;\n\t\t\t__u32 bit10: 1;\n\t\t\t__u32 bit9: 1;\n\t\t\t__u32 bit8: 1;\n\t\t\t__u32 bit23: 1;\n\t\t\t__u32 bit22: 1;\n\t\t\t__u32 bit21: 1;\n\t\t\t__u32 bit20: 1;\n\t\t\t__u32 bit19: 1;\n\t\t\t__u32 bit18: 1;\n\t\t\t__u32 bit17: 1;\n\t\t\t__u32 bit16: 1;\n\t\t} type;\n\t};\n\t__u8 data[0];\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tlong: 32;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n\tlong: 32;\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tlong: 32;\n\tstruct bio io_bio;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tlong: 32;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tlong: 32;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n\tlong: 32;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n\tlong: 32;\n};\n\nstruct iommu_dirty_ops {};\n\nstruct iommu_domain_ops;\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommu_dma_cookie;\n\nstruct iommu_dma_msi_cookie;\n\nstruct iommufd_hw_pagetable;\n\nstruct iommu_domain;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_ops;\n\nstruct iopf_group;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tlong: 32;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iommu_fault_param {};\n\nstruct iommu_group {};\n\nstruct iommu_ops {};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iommu_attach_handle;\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct ip6_frag_state {\n\tu8 *prevhdr;\n\tunsigned int hlen;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\tint hroom;\n\tint troom;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ipv6hdr;\n\nstruct ip6_fraglist_iter {\n\tstruct ipv6hdr *tmp_hdr;\n\tstruct sk_buff *frag;\n\tint offset;\n\tunsigned int hlen;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct ip6_mtuinfo {\n\tstruct sockaddr_in6 ip6m_addr;\n\t__u32 ip6m_mtu;\n};\n\nstruct ip6_ra_chain {\n\tstruct ip6_ra_chain *next;\n\tstruct sock *sk;\n\tint sel;\n\tvoid (*destructor)(struct sock *);\n};\n\nstruct ip6_rt_info {\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\tu_int32_t mark;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap;\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip6addrlbl_entry {\n\tstruct in6_addr prefix;\n\tint prefixlen;\n\tint ifindex;\n\tint addrtype;\n\tu32 label;\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n};\n\nstruct ip6addrlbl_init_table {\n\tconst struct in6_addr *prefix;\n\tint prefixlen;\n\tu32 label;\n};\n\nstruct ip6fl_iter_state {\n\tstruct seq_net_private p;\n\tstruct pid_namespace *pid_ns;\n\tint bucket;\n};\n\nstruct ip6rd_flowi {\n\tstruct flowi6 fl6;\n\tstruct in6_addr gateway;\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct unix_domain;\n\nstruct ip_map {\n\tstruct cache_head h;\n\tchar m_class[8];\n\tstruct in6_addr m_addr;\n\tstruct unix_domain *m_client;\n\tstruct callback_head m_rcu;\n\tlong: 32;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_rt_info {\n\t__be32 daddr;\n\t__be32 saddr;\n\tu_int8_t tos;\n\tu_int32_t mark;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip_tunnel_prl_entry;\n\nstruct ip_tunnel {\n\tstruct ip_tunnel *next;\n\tstruct hlist_node hash_node;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tlong unsigned int err_time;\n\tint err_count;\n\tu32 i_seqno;\n\tatomic_t o_seqno;\n\tint tun_hlen;\n\tu32 index;\n\tu8 erspan_ver;\n\tu8 dir;\n\tu16 hwid;\n\tstruct dst_cache dst_cache;\n\tstruct ip_tunnel_parm_kern parms;\n\tint mlink;\n\tint encap_hlen;\n\tint hlen;\n\tstruct ip_tunnel_encap encap;\n\tstruct ip_tunnel_prl_entry *prl;\n\tunsigned int prl_count;\n\tunsigned int ip_tnl_net_id;\n\tstruct gro_cells gro_cells;\n\t__u32 fwmark;\n\tbool collect_md;\n\tbool ignore_df;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n\tlong: 32;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 32;\n\tu8 options[0];\n};\n\nstruct rtnl_link_ops;\n\nstruct ip_tunnel_net {\n\tstruct net_device *fb_tunnel_dev;\n\tstruct rtnl_link_ops *rtnl_link_ops;\n\tstruct hlist_head tunnels[128];\n\tstruct ip_tunnel *collect_md_tun;\n\tint type;\n};\n\nstruct ip_tunnel_parm {\n\tchar name[16];\n\tint link;\n\t__be16 i_flags;\n\t__be16 o_flags;\n\t__be32 i_key;\n\t__be32 o_key;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl {\n\t__be32 addr;\n\t__u16 flags;\n\t__u16 __reserved;\n\t__u32 datalen;\n\t__u32 __reserved2;\n};\n\nstruct ip_tunnel_prl_entry {\n\tstruct ip_tunnel_prl_entry *next;\n\t__be32 addr;\n\tu16 flags;\n\tstruct callback_head callback_head;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned char __pad1[0];\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\t__kernel_ulong_t __unused1;\n\t__kernel_ulong_t __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tstruct rhashtable key_ht;\n};\n\nstruct msgbuf;\n\nstruct ipc_kludge {\n\tstruct msgbuf *msgp;\n\tlong int msgtyp;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tlong: 32;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n\tlong: 32;\n};\n\nstruct ipcm6_cookie {\n\tstruct sockcm_cookie sockc;\n\t__s16 hlimit;\n\t__s16 tclass;\n\t__u16 gso_size;\n\t__s8 dontfrag;\n\tstruct ipv6_txoptions *opt;\n\tlong: 32;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n\tlong: 32;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mreq {\n\tstruct in6_addr ipv6mr_multiaddr;\n\tint ipv6mr_ifindex;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_params {\n\t__s32 disable_ipv6;\n\t__s32 autoconf;\n};\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib6_walker w;\n\tloff_t skip;\n\tstruct fib6_table *tbl;\n\tint sernum;\n};\n\nstruct ipv6_rpl_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u32 cmpre: 4;\n\t__u32 cmpri: 4;\n\t__u32 reserved: 4;\n\t__u32 pad: 4;\n\t__u32 reserved1: 16;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_addr;\n\t\t\tstruct in6_addr addr[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\t__u8 data[0];\n\t\t};\n\t} segments;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct ipv6_saddr_dst {\n\tconst struct in6_addr *addr;\n\tint ifindex;\n\tint scope;\n\tint label;\n\tunsigned int prefs;\n};\n\nstruct ipv6_saddr_score {\n\tint rule;\n\tint addr_type;\n\tstruct inet6_ifaddr *ifa;\n\tlong unsigned int scorebits[1];\n\tint scopedist;\n\tint matchlen;\n};\n\nstruct ipv6_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u8 first_segment;\n\t__u8 flags;\n\t__u16 tag;\n\tstruct in6_addr segments[0];\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n\tcpumask_var_t effective_affinity;\n\tunsigned int ipi_offset;\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_generic_chip_devres {\n\tstruct irq_chip_generic *gc;\n\tu32 msk;\n\tunsigned int clr;\n\tunsigned int set;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_info {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct j_format {\n\tunsigned int target: 26;\n\tunsigned int opcode: 6;\n};\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_s journal_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong: 32;\n\tlong long unsigned int blocknr;\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct transaction_stats_s;\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct jedec_ecc_info {\n\tu8 ecc_bits;\n\tu8 codeword_size;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 reserved[2];\n};\n\nstruct jit_context {\n\tstruct bpf_prog *program;\n\tu32 *descriptors;\n\tu32 *target;\n\tu32 bpf_index;\n\tu32 jit_index;\n\tu32 changes;\n\tu32 accessed;\n\tu32 clobbered;\n\tu32 stack_size;\n\tu32 saved_size;\n\tu32 stack_used;\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\twait_queue_head_t j_fc_wait;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tstruct shrinker *j_shrinker;\n\tlong: 32;\n\tstruct percpu_counter j_checkpoint_jh_count;\n\ttransaction_t *j_shrink_transaction;\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tlong unsigned int j_fc_first;\n\tlong unsigned int j_fc_off;\n\tlong unsigned int j_fc_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong: 32;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\terrseq_t j_fs_dev_wb_err;\n\tunsigned int j_total_len;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tint j_transaction_overhead_buffers;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tstruct buffer_head **j_fc_wbuf;\n\tint j_wbufsize;\n\tint j_fc_wbufsize;\n\tpid_t j_last_sync_writer;\n\tlong: 32;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tint (*j_submit_inode_data_buffers)(struct jbd2_inode *);\n\tint (*j_finish_inode_data_buffers)(struct jbd2_inode *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\t__u32 j_csum_seed;\n\tstruct lock_class_key jbd2_trans_commit_key;\n\tvoid (*j_fc_cleanup_callback)(struct journal_s *, int, tid_t);\n\tint (*j_fc_replay_callback)(struct journal_s *, struct buffer_head *, enum passtype, int, tid_t);\n\tint (*j_bmap)(struct journal_s *, sector_t *);\n};\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__be32 s_num_fc_blks;\n\t__be32 s_head;\n\t__u32 s_padding[40];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nstruct jump_entry {\n\tjump_label_t code;\n\tjump_label_t target;\n\tjump_label_t key;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_code;\n\t\tint si_errno;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\tlong: 32;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\nstruct sigaction {\n\tunsigned int sa_flags;\n\t__sighandler_t sa_handler;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[60];\n\tint exported;\n\tint show_value;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tlong: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[10];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tlong unsigned int value;\n\tconst char *name;\n\tconst char *namespace;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n\tlong: 32;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[256];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n\tlong: 32;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct vm_operations_struct;\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[2];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\tlong: 32;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\tlong: 32;\n\ttime64_t now;\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tlong: 32;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tlong: 32;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[3];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {\n\tint idx;\n\tpte_t pteval[16];\n};\n\ntypedef struct kmem_cache *kmem_buckets[14];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tstruct kmem_cache_node *node[1];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kpp_request;\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct kpp_instance {\n\tvoid (*free)(struct kpp_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct kpp_alg alg;\n\t};\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct krb5_ctx {\n\tint initiate;\n\tu32 enctype;\n\tu32 flags;\n\tconst struct gss_krb5_enctype *gk5e;\n\tstruct crypto_sync_skcipher *enc;\n\tstruct crypto_sync_skcipher *seq;\n\tstruct crypto_sync_skcipher *acceptor_enc;\n\tstruct crypto_sync_skcipher *initiator_enc;\n\tstruct crypto_sync_skcipher *acceptor_enc_aux;\n\tstruct crypto_sync_skcipher *initiator_enc_aux;\n\tstruct crypto_ahash *acceptor_sign;\n\tstruct crypto_ahash *initiator_sign;\n\tstruct crypto_ahash *initiator_integ;\n\tstruct crypto_ahash *acceptor_integ;\n\tu8 Ksess[32];\n\tu8 cksum[32];\n\tatomic_t seq_send;\n\tlong: 32;\n\tatomic64_t seq_send64;\n\ttime64_t endtime;\n\tstruct xdr_netobj mech_used;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n\tlong: 32;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n\tlong: 32;\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tlong: 32;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[23];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_worker;\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tlong: 32;\n\tu64 val[2];\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct lcd_properties {\n\tint max_contrast;\n};\n\nstruct lcd_ops;\n\nstruct lcd_device {\n\tstruct lcd_properties props;\n\tstruct mutex ops_lock;\n\tconst struct lcd_ops *ops;\n\tstruct mutex update_lock;\n\tstruct list_head entry;\n\tstruct device dev;\n};\n\nstruct lcd_ops {\n\tint (*get_power)(struct lcd_device *);\n\tint (*set_power)(struct lcd_device *, int);\n\tint (*get_contrast)(struct lcd_device *);\n\tint (*set_contrast)(struct lcd_device *, int);\n\tint (*set_mode)(struct lcd_device *, u32, u32);\n\tbool (*controls_device)(struct lcd_device *, struct device *);\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct mc_subled;\n\nstruct led_classdev_mc {\n\tstruct led_classdev led_cdev;\n\tunsigned int num_colors;\n\tstruct mc_subled *subled_info;\n};\n\nstruct led_init_data {\n\tstruct fwnode_handle *fwnode;\n\tconst char *default_label;\n\tconst char *devicename;\n\tbool devname_mandatory;\n};\n\nstruct led_lookup_data {\n\tstruct list_head list;\n\tconst char *provider;\n\tconst char *dev_id;\n\tconst char *con_id;\n};\n\nstruct led_pattern {\n\tu32 delta_t;\n\tint brightness;\n};\n\nstruct led_properties {\n\tu32 color;\n\tbool color_present;\n\tconst char *function;\n\tu32 func_enum;\n\tbool func_enum_present;\n\tconst char *label;\n};\n\nstruct led_trigger {};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linereq;\n\nstruct line {\n\tstruct gpio_desc *desc;\n\tstruct linereq *req;\n\tunsigned int irq;\n\tlong: 32;\n\tu64 edflags;\n\tu64 timestamp_ns;\n\tu32 req_seqno;\n\tu32 line_seqno;\n\tstruct delayed_work work;\n\tunsigned int sw_debounced;\n\tunsigned int level;\n\tlong: 32;\n};\n\nstruct linear_range {\n\tunsigned int min;\n\tunsigned int min_sel;\n\tunsigned int max_sel;\n\tunsigned int step;\n};\n\nstruct linedisp_attachment {\n\tstruct list_head list;\n\tstruct device *device;\n\tstruct linedisp *linedisp;\n\tbool direct;\n};\n\nstruct seg7_conversion_map {\n\tunsigned char table[128];\n};\n\nstruct seg14_conversion_map {\n\t__be16 table[128];\n};\n\nstruct linedisp_map {\n\tenum linedisp_map_type type;\n\tunion {\n\t\tstruct seg7_conversion_map seg7;\n\t\tstruct seg14_conversion_map seg14;\n\t} map;\n\tunsigned int size;\n};\n\nstruct lineevent_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *desc;\n\tu32 eflags;\n\tint irq;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tlong: 32;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpioevent_data *type;\n\t\t\tconst struct gpioevent_data *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpioevent_data *ptr;\n\t\t\tconst struct gpioevent_data *ptr_const;\n\t\t};\n\t\tlong: 32;\n\t\tstruct gpioevent_data buf[16];\n\t} events;\n\tu64 timestamp;\n};\n\nstruct linehandle_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *descs[64];\n\tu32 num_descs;\n};\n\nstruct lineinfo_changed_ctx {\n\tstruct work_struct work;\n\tstruct gpio_v2_line_info_changed chg;\n\tstruct gpio_device *gdev;\n\tstruct gpio_chardev_data *cdev;\n};\n\nstruct linereq {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tu32 num_lines;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tu32 event_buffer_size;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_event *type;\n\t\t\tconst struct gpio_v2_line_event *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_event *ptr;\n\t\t\tconst struct gpio_v2_line_event *ptr_const;\n\t\t};\n\t\tlong: 32;\n\t\tstruct gpio_v2_line_event buf[0];\n\t} events;\n\tatomic_t seqno;\n\tstruct mutex config_mutex;\n\tlong: 32;\n\tstruct line lines[0];\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_capabilities {\n\tint speed;\n\tunsigned int duplex;\n\tlong unsigned int linkmodes[4];\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n\tlong: 32;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n\tlong: 32;\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n\tstruct list_head list;\n\tint shrinker_id;\n\tbool memcg_aware;\n\tstruct xarray xa;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_memcg {\n\tstruct callback_head rcu;\n\tstruct list_lru_one node[0];\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct liteeth {\n\tvoid *base;\n\tstruct net_device *netdev;\n\tstruct device *dev;\n\tu32 slot_size;\n\tu32 tx_slot;\n\tu32 num_tx_slots;\n\tvoid *tx_base;\n\tu32 rx_slot;\n\tu32 num_rx_slots;\n\tvoid *rx_base;\n};\n\nstruct liteuart_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tu8 irq_reg;\n};\n\nstruct litex_mmc_host {\n\tstruct mmc_host *mmc;\n\tvoid *sdphy;\n\tvoid *sdcore;\n\tvoid *sdreader;\n\tvoid *sdwriter;\n\tvoid *sdirq;\n\tvoid *buffer;\n\tsize_t buf_size;\n\tdma_addr_t dma;\n\tstruct completion cmd_done;\n\tint irq;\n\tunsigned int ref_clk;\n\tunsigned int sd_clk;\n\tu32 resp[4];\n\tu16 rca;\n\tbool is_bus_width_set;\n\tbool app_cmd;\n};\n\nstruct litex_soc_ctrl_device {\n\tvoid *base;\n};\n\nstruct llc_addr {\n\tunsigned char lsap;\n\tunsigned char mac[6];\n};\n\nstruct llc_pdu_sn {\n\tu8 dsap;\n\tu8 ssap;\n\tu8 ctrl_1;\n\tu8 ctrl_2;\n};\n\nstruct llc_pdu_un {\n\tu8 dsap;\n\tu8 ssap;\n\tu8 ctrl_1;\n};\n\nstruct llc_sap {\n\tunsigned char state;\n\tunsigned char p_bit;\n\tunsigned char f_bit;\n\trefcount_t refcnt;\n\tint (*rcv_func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tstruct llc_addr laddr;\n\tstruct list_head node;\n\tspinlock_t sk_lock;\n\tint sk_count;\n\tstruct hlist_nulls_head sk_laddr_hash[64];\n\tstruct hlist_head sk_dev_hash[64];\n\tstruct callback_head rcu;\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf32_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf32_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct lock_manager {\n\tstruct list_head list;\n\tbool block_opens;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct lockd_net {\n\tunsigned int nlmsvc_users;\n\tlong unsigned int next_gc;\n\tlong unsigned int nrhosts;\n\tu32 gracetime;\n\tu16 tcp_port;\n\tu16 udp_port;\n\tstruct delayed_work grace_period_end;\n\tstruct lock_manager lockd_manager;\n\tstruct list_head nsm_handles;\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tlong: 32;\n\tloff_t li_pos;\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct lookup_args {\n\tint offset;\n\tconst struct in6_addr *addr;\n};\n\nstruct loongson3_lscsr_format {\n\tunsigned int func: 6;\n\tunsigned int fd: 5;\n\tunsigned int rd: 5;\n\tunsigned int fr: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct loongson3_lsdc2_format {\n\tunsigned int opcode1: 3;\n\tunsigned int offset: 8;\n\tunsigned int index: 5;\n\tunsigned int rt: 5;\n\tunsigned int base: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct loongson3_lswc2_format {\n\tunsigned int rq: 5;\n\tunsigned int ls: 1;\n\tunsigned int offset: 9;\n\tunsigned int fr: 1;\n\tunsigned int rt: 5;\n\tunsigned int base: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct loop_cmd {\n\tstruct list_head list_entry;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tlong: 32;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct cgroup_subsys_state *memcg_css;\n\tlong: 32;\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nstruct loop_device {\n\tint lo_number;\n\tlong: 32;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tchar lo_file_name[64];\n\tstruct file *lo_backing_file;\n\tunsigned int lo_min_dio_size;\n\tstruct block_device *lo_device;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tspinlock_t lo_work_lock;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rootcg_work;\n\tstruct list_head rootcg_cmd_list;\n\tstruct list_head idle_worker_list;\n\tstruct rb_root worker_tree;\n\tstruct timer_list timer;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n\tstruct mutex lo_mutex;\n\tbool idr_visible;\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_worker {\n\tstruct rb_node rb_node;\n\tstruct work_struct work;\n\tstruct list_head cmd_list;\n\tstruct list_head idle_list;\n\tstruct loop_device *lo;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tlong unsigned int last_ran_at;\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n\tlong: 32;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct zswap_lruvec_state {};\n\nstruct pglist_data;\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct pglist_data *pgdat;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct lruvec_stats {\n\tlong int state[31];\n\tlong int state_local[31];\n\tlong int state_pending[31];\n};\n\nstruct lruvec_stats_percpu {\n\tlong int state[31];\n\tlong int state_prev[31];\n};\n\nstruct skcipher_alg_common {\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int statesize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct lskcipher_alg {\n\tint (*setkey)(struct crypto_lskcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*decrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*init)(struct crypto_lskcipher *);\n\tvoid (*exit)(struct crypto_lskcipher *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct skcipher_alg_common co;\n};\n\nstruct lskcipher_instance {\n\tvoid (*free)(struct lskcipher_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[256];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct lskcipher_alg alg;\n\t};\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct ltchars {\n\tchar t_suspc;\n\tchar t_dsuspc;\n\tchar t_rprntc;\n\tchar t_flushc;\n\tchar t_werasc;\n\tchar t_lnextc;\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwq_node {\n\tstruct llist_node node;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct m16e_i64 {\n\tunsigned int imm: 8;\n\tunsigned int func: 3;\n\tunsigned int opcode: 5;\n};\n\nstruct m16e_i8 {\n\tunsigned int imm: 8;\n\tunsigned int func: 3;\n\tunsigned int opcode: 5;\n};\n\nstruct m16e_jal {\n\tint imm25_21: 5;\n\tunsigned int imm20_16: 5;\n\tunsigned int x: 1;\n\tunsigned int opcode: 5;\n};\n\nstruct m16e_ri {\n\tunsigned int imm: 8;\n\tunsigned int rx: 3;\n\tunsigned int opcode: 5;\n};\n\nstruct m16e_ri64 {\n\tunsigned int imm: 5;\n\tunsigned int ry: 3;\n\tunsigned int func: 3;\n\tunsigned int opcode: 5;\n};\n\nstruct m16e_rr {\n\tunsigned int func: 5;\n\tunsigned int ra: 1;\n\tunsigned int l: 1;\n\tunsigned int nd: 1;\n\tunsigned int rx: 3;\n\tunsigned int opcode: 5;\n};\n\nstruct m16e_rri {\n\tunsigned int imm: 5;\n\tunsigned int ry: 3;\n\tunsigned int rx: 3;\n\tunsigned int opcode: 5;\n};\n\nstruct m41t80_data {\n\tlong unsigned int features;\n\tstruct i2c_client *client;\n\tstruct rtc_device *rtc;\n\tstruct clk_hw sqw;\n\tlong unsigned int freq;\n\tunsigned int sqwe;\n};\n\nstruct ma_format {\n\tunsigned int fmt: 2;\n\tunsigned int func: 4;\n\tunsigned int fd: 5;\n\tunsigned int fs: 5;\n\tunsigned int ft: 5;\n\tunsigned int fr: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct maar_config {\n\tphys_addr_t lower;\n\tphys_addr_t upper;\n\tunsigned int attrs;\n};\n\nstruct maar_walk_info {\n\tstruct maar_config cfg[16];\n\tunsigned int num_cfg;\n};\n\nstruct mac_addr {\n\tunsigned char addr[6];\n};\n\ntypedef struct mac_addr mac_addr;\n\nstruct mii_regs {\n\tunsigned int addr;\n\tunsigned int data;\n\tunsigned int addr_shift;\n\tunsigned int reg_shift;\n\tunsigned int addr_mask;\n\tunsigned int reg_mask;\n\tunsigned int clk_csr_shift;\n\tunsigned int clk_csr_mask;\n};\n\nstruct mac_link {\n\tu32 caps;\n\tu32 speed_mask;\n\tu32 speed10;\n\tu32 speed100;\n\tu32 speed1000;\n\tu32 speed2500;\n\tu32 duplex;\n\tstruct {\n\t\tu32 speed2500;\n\t\tu32 speed5000;\n\t\tu32 speed10000;\n\t} xgmii;\n\tstruct {\n\t\tu32 speed25000;\n\t\tu32 speed40000;\n\t\tu32 speed50000;\n\t\tu32 speed100000;\n\t} xlgmii;\n};\n\nstruct stmmac_ops;\n\nstruct stmmac_desc_ops;\n\nstruct stmmac_dma_ops;\n\nstruct stmmac_mode_ops;\n\nstruct stmmac_hwtimestamp;\n\nstruct stmmac_tc_ops;\n\nstruct stmmac_mmc_ops;\n\nstruct stmmac_est_ops;\n\nstruct stmmac_vlan_ops;\n\nstruct mac_device_info {\n\tconst struct stmmac_ops *mac;\n\tconst struct stmmac_desc_ops *desc;\n\tconst struct stmmac_dma_ops *dma;\n\tconst struct stmmac_mode_ops *mode;\n\tconst struct stmmac_hwtimestamp *ptp;\n\tconst struct stmmac_tc_ops *tc;\n\tconst struct stmmac_mmc_ops *mmc;\n\tconst struct stmmac_est_ops *est;\n\tconst struct stmmac_vlan_ops *vlan;\n\tstruct dw_xpcs *xpcs;\n\tstruct phylink_pcs *phylink_pcs;\n\tstruct mii_regs mii;\n\tstruct mac_link link;\n\tvoid *pcsr;\n\tunsigned int multicast_filter_bins;\n\tunsigned int unicast_filter_entries;\n\tunsigned int mcast_bits_log2;\n\tunsigned int rx_csum;\n\tunsigned int pcs;\n\tunsigned int xlgmac;\n\tunsigned int num_vlan;\n\tu32 vlan_filter[32];\n\tbool vlan_fail_q_en;\n\tu8 vlan_fail_q;\n\tbool hw_vlan_en;\n\tbool reverse_sgmii_enable;\n\tspinlock_t irq_ctrl_lock;\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct mtd_chip_driver;\n\nstruct map_info {\n\tconst char *name;\n\tlong unsigned int size;\n\tresource_size_t phys;\n\tvoid *virt;\n\tvoid *cached;\n\tint swap;\n\tint bankwidth;\n\tvoid (*inval_cache)(struct map_info *, long unsigned int, ssize_t);\n\tvoid (*set_vpp)(struct map_info *, int);\n\tlong unsigned int pfow_base;\n\tlong unsigned int map_priv_1;\n\tlong unsigned int map_priv_2;\n\tstruct device_node *device_node;\n\tvoid *fldrv_priv;\n\tstruct mtd_chip_driver *fldrv;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[20];\n\tvoid *slot[21];\n\tlong unsigned int gap[21];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[65];\n\tunion {\n\t\tstruct maple_enode *slot[66];\n\t\tstruct {\n\t\t\tlong unsigned int padding[43];\n\t\t\tlong unsigned int gap[43];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[31];\n\tunion {\n\t\tvoid *slot[32];\n\t\tstruct {\n\t\t\tvoid *pad[31];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[63];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker *c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tlong unsigned int e_flags;\n\tlong: 32;\n\tu64 e_value;\n};\n\nstruct mc_subled {\n\tunsigned int color_index;\n\tunsigned int brightness;\n\tunsigned int intensity;\n\tunsigned int channel;\n};\n\nstruct mcs_spinlock {\n\tstruct mcs_spinlock *next;\n\tint locked;\n\tint count;\n};\n\nstruct mctrl_gpios {\n\tstruct uart_port *port;\n\tstruct gpio_desc *gpio[6];\n\tint irq[6];\n\tunsigned int mctrl_prev;\n\tbool mctrl_on;\n};\n\nstruct virt_dma_desc;\n\nstruct virt_dma_chan {\n\tstruct dma_chan chan;\n\tstruct tasklet_struct task;\n\tvoid (*desc_free)(struct virt_dma_desc *);\n\tspinlock_t lock;\n\tstruct list_head desc_allocated;\n\tstruct list_head desc_submitted;\n\tstruct list_head desc_issued;\n\tstruct list_head desc_completed;\n\tstruct list_head desc_terminated;\n\tstruct virt_dma_desc *cyclic;\n};\n\nstruct mdc_dma;\n\nstruct mdc_tx_desc;\n\nstruct mdc_chan {\n\tstruct mdc_dma *mdma;\n\tstruct virt_dma_chan vc;\n\tstruct dma_slave_config config;\n\tstruct mdc_tx_desc *desc;\n\tint irq;\n\tunsigned int periph;\n\tunsigned int thread;\n\tunsigned int chan_nr;\n};\n\nstruct mdc_dma_soc_data;\n\nstruct mdc_dma {\n\tstruct dma_device dma_dev;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct dma_pool *desc_pool;\n\tstruct regmap *periph_regs;\n\tspinlock_t lock;\n\tunsigned int nr_threads;\n\tunsigned int nr_channels;\n\tunsigned int bus_width;\n\tunsigned int max_burst_mult;\n\tunsigned int max_xfer_size;\n\tconst struct mdc_dma_soc_data *soc;\n\tstruct mdc_chan channels[32];\n};\n\nstruct mdc_dma_soc_data {\n\tvoid (*enable_chan)(struct mdc_chan *);\n\tvoid (*disable_chan)(struct mdc_chan *);\n};\n\nstruct mdc_hw_list_desc {\n\tu32 gen_conf;\n\tu32 readport_conf;\n\tu32 read_addr;\n\tu32 write_addr;\n\tu32 xfer_size;\n\tu32 node_addr;\n\tu32 cmds_done;\n\tu32 ctrl_status;\n\tstruct mdc_hw_list_desc *next_desc;\n};\n\nstruct virt_dma_desc {\n\tstruct dma_async_tx_descriptor tx;\n\tstruct dmaengine_result tx_result;\n\tstruct list_head node;\n};\n\nstruct mdc_tx_desc {\n\tstruct mdc_chan *chan;\n\tstruct virt_dma_desc vd;\n\tdma_addr_t list_phys;\n\tstruct mdc_hw_list_desc *list;\n\tbool cyclic;\n\tbool cmd_loaded;\n\tunsigned int list_len;\n\tunsigned int list_period_len;\n\tsize_t list_xfer_size;\n\tunsigned int list_cmds_done;\n};\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n\tlong: 32;\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n\tvoid (*shutdown)(struct mdio_device *);\n};\n\nstruct mdiobus_devres {\n\tstruct mii_bus *mii;\n};\n\nstruct mem_cgroup_private_id {\n\tint id;\n\trefcount_t ref;\n};\n\nstruct page_counter {\n\tatomic_long_t usage;\n\tlong unsigned int failcnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int emin;\n\tatomic_long_t min_usage;\n\tatomic_long_t children_min_usage;\n\tlong unsigned int elow;\n\tatomic_long_t low_usage;\n\tatomic_long_t children_low_usage;\n\tlong unsigned int watermark;\n\tlong unsigned int local_watermark;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad2_;\n\tbool protection_support;\n\tbool track_failcnt;\n\tlong unsigned int min;\n\tlong unsigned int low;\n\tlong unsigned int high;\n\tlong unsigned int max;\n\tstruct page_counter *parent;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct vmpressure {\n\tlong unsigned int scanned;\n\tlong unsigned int reclaimed;\n\tlong unsigned int tree_scanned;\n\tlong unsigned int tree_reclaimed;\n\tspinlock_t sr_lock;\n\tstruct list_head events;\n\tstruct mutex events_lock;\n\tstruct work_struct work;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tlong: 32;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct memcg_cgwb_frn {\n\tu64 bdi_id;\n\tint memcg_id;\n\tlong: 32;\n\tu64 at;\n\tstruct wb_completion done;\n};\n\nstruct memcg_vmstats;\n\nstruct memcg_vmstats_percpu;\n\nstruct mem_cgroup_per_node;\n\nstruct mem_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct mem_cgroup_private_id id;\n\tstruct page_counter memory;\n\tunion {\n\t\tstruct page_counter swap;\n\t\tstruct page_counter memsw;\n\t};\n\tstruct list_head memory_peaks;\n\tstruct list_head swap_peaks;\n\tspinlock_t peaks_lock;\n\tstruct work_struct high_work;\n\tstruct vmpressure vmpressure;\n\tbool oom_group;\n\tint swappiness;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct cgroup_file swap_events_file;\n\tstruct memcg_vmstats *vmstats;\n\tatomic_long_t memory_events[10];\n\tatomic_long_t memory_events_local[10];\n\tu64 socket_pressure;\n\tseqlock_t socket_pressure_seqlock;\n\tint kmemcg_id;\n\tstruct obj_cgroup *objcg;\n\tstruct obj_cgroup *orig_objcg;\n\tstruct list_head objcg_list;\n\tstruct memcg_vmstats_percpu *vmstats_percpu;\n\tstruct list_head cgwb_list;\n\tstruct wb_domain cgwb_domain;\n\tstruct memcg_cgwb_frn cgwb_frn[4];\n\tstruct mem_cgroup_per_node *nodeinfo[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mem_cgroup_reclaim_iter {\n\tstruct mem_cgroup *position;\n\tatomic_t generation;\n};\n\nstruct shrinker_info;\n\nstruct mem_cgroup_per_node {\n\tstruct mem_cgroup *memcg;\n\tstruct lruvec_stats_percpu *lruvec_stats_percpu;\n\tstruct lruvec_stats *lruvec_stats;\n\tstruct shrinker_info *shrinker_info;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad1_;\n\tstruct lruvec lruvec;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int lru_zone_size[15];\n\tstruct mem_cgroup_reclaim_iter iter;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tlong: 32;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n\tlong: 32;\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tlong: 32;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memcg_stock_pcp {\n\tlocal_trylock_t lock;\n\tuint8_t nr_pages[7];\n\tstruct mem_cgroup *cached[7];\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct memcg_vmstats {\n\tlong int state[38];\n\tlong unsigned int events[19];\n\tlong int state_local[38];\n\tlong unsigned int events_local[19];\n\tlong int state_pending[38];\n\tlong unsigned int events_pending[19];\n\tatomic_t stats_updates;\n};\n\nstruct memcg_vmstats_percpu {\n\tunsigned int stats_updates;\n\tstruct memcg_vmstats_percpu *parent_pcpu;\n\tstruct memcg_vmstats *vmstats;\n\tlong int state[38];\n\tlong unsigned int events[19];\n\tlong int state_prev[38];\n\tlong unsigned int events_prev[19];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct memory_stat {\n\tconst char *name;\n\tunsigned int idx;\n};\n\nstruct mempolicy {};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tlong: 32;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mext_data {\n\tstruct inode *orig_inode;\n\tstruct inode *donor_inode;\n\tstruct ext4_map_blocks orig_map;\n\text4_lblk_t donor_lblk;\n\tlong: 32;\n};\n\nstruct mfmc0_format {\n\tunsigned int sel: 3;\n\tchar: 2;\n\tunsigned int sc: 1;\n\tunsigned int re: 5;\n\tunsigned int rd: 5;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct micron_on_die_ecc {\n\tbool forced;\n\tbool enabled;\n\tvoid *rawbuf;\n};\n\nstruct micron_nand {\n\tstruct micron_on_die_ecc ecc;\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\tlong: 32;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct phy_package_shared;\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n\tstruct phy_package_shared *shared[32];\n\tlong: 32;\n};\n\nstruct mii_if_info {\n\tint phy_id;\n\tint advertising;\n\tint phy_id_mask;\n\tint reg_num_mask;\n\tunsigned int full_duplex: 1;\n\tunsigned int force_media: 1;\n\tunsigned int supports_gmii: 1;\n\tstruct net_device *dev;\n\tint (*mdio_read)(struct net_device *, int, int);\n\tvoid (*mdio_write)(struct net_device *, int, int, int);\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nstruct tcf_proto;\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minix_super_block {\n\t__u16 s_ninodes;\n\t__u16 s_nzones;\n\t__u16 s_imap_blocks;\n\t__u16 s_zmap_blocks;\n\t__u16 s_firstdatazone;\n\t__u16 s_log_zone_size;\n\t__u32 s_max_size;\n\t__u16 s_magic;\n\t__u16 s_state;\n\t__u32 s_zones;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nunion mips16e_instruction {\n\tunsigned int full: 16;\n\tstruct m16e_rr rr;\n\tstruct m16e_jal jal;\n\tstruct m16e_i64 i64;\n\tstruct m16e_ri64 ri64;\n\tstruct m16e_ri ri;\n\tstruct m16e_rri rri;\n\tstruct m16e_i8 i8;\n};\n\nstruct mips3264_watch_reg_state {\n\tlong unsigned int watchlo[4];\n\tu16 watchhi[4];\n};\n\nstruct mips32_watch_regs {\n\tunsigned int watchlo[8];\n\tshort unsigned int watchhi[8];\n\tshort unsigned int watch_masks[8];\n\tunsigned int num_valid;\n\tlong: 32;\n};\n\nstruct mips64_watch_regs {\n\tlong long unsigned int watchlo[8];\n\tshort unsigned int watchhi[8];\n\tshort unsigned int watch_masks[8];\n\tunsigned int num_valid;\n\tlong: 32;\n};\n\nstruct mips_vdso_image;\n\nstruct mips_abi {\n\tint (* const setup_frame)(void *, struct ksignal *, struct pt_regs *, sigset_t *);\n\tint (* const setup_rt_frame)(void *, struct ksignal *, struct pt_regs *, sigset_t *);\n\tconst long unsigned int restart;\n\tunsigned int off_sc_fpregs;\n\tunsigned int off_sc_fpc_csr;\n\tunsigned int off_sc_used_math;\n\tstruct mips_vdso_image *vdso;\n};\n\nstruct mips_dsp_state {\n\tdspreg_t dspr[6];\n\tunsigned int dspcontrol;\n};\n\nstruct mips_elf_abiflags_v0 {\n\tuint16_t version;\n\tuint8_t isa_level;\n\tuint8_t isa_rev;\n\tuint8_t gpr_size;\n\tuint8_t cpr1_size;\n\tuint8_t cpr2_size;\n\tuint8_t fp_abi;\n\tuint32_t isa_ext;\n\tuint32_t ases;\n\tuint32_t flags1;\n\tuint32_t flags2;\n};\n\nstruct mips_fdt_fixup {\n\tint (*apply)(void *);\n\tconst char *description;\n};\n\nstruct mips_fpu_emulator_stats {\n\tlong unsigned int emulated;\n\tlong unsigned int loads;\n\tlong unsigned int stores;\n\tlong unsigned int branches;\n\tlong unsigned int cp1ops;\n\tlong unsigned int cp1xops;\n\tlong unsigned int errors;\n\tlong unsigned int ieee754_inexact;\n\tlong unsigned int ieee754_underflow;\n\tlong unsigned int ieee754_overflow;\n\tlong unsigned int ieee754_zerodiv;\n\tlong unsigned int ieee754_invalidop;\n\tlong unsigned int ds_emul;\n\tlong unsigned int abs_s;\n\tlong unsigned int abs_d;\n\tlong unsigned int add_s;\n\tlong unsigned int add_d;\n\tlong unsigned int bc1eqz;\n\tlong unsigned int bc1nez;\n\tlong unsigned int ceil_w_s;\n\tlong unsigned int ceil_w_d;\n\tlong unsigned int ceil_l_s;\n\tlong unsigned int ceil_l_d;\n\tlong unsigned int class_s;\n\tlong unsigned int class_d;\n\tlong unsigned int cmp_af_s;\n\tlong unsigned int cmp_af_d;\n\tlong unsigned int cmp_eq_s;\n\tlong unsigned int cmp_eq_d;\n\tlong unsigned int cmp_le_s;\n\tlong unsigned int cmp_le_d;\n\tlong unsigned int cmp_lt_s;\n\tlong unsigned int cmp_lt_d;\n\tlong unsigned int cmp_ne_s;\n\tlong unsigned int cmp_ne_d;\n\tlong unsigned int cmp_or_s;\n\tlong unsigned int cmp_or_d;\n\tlong unsigned int cmp_ueq_s;\n\tlong unsigned int cmp_ueq_d;\n\tlong unsigned int cmp_ule_s;\n\tlong unsigned int cmp_ule_d;\n\tlong unsigned int cmp_ult_s;\n\tlong unsigned int cmp_ult_d;\n\tlong unsigned int cmp_un_s;\n\tlong unsigned int cmp_un_d;\n\tlong unsigned int cmp_une_s;\n\tlong unsigned int cmp_une_d;\n\tlong unsigned int cmp_saf_s;\n\tlong unsigned int cmp_saf_d;\n\tlong unsigned int cmp_seq_s;\n\tlong unsigned int cmp_seq_d;\n\tlong unsigned int cmp_sle_s;\n\tlong unsigned int cmp_sle_d;\n\tlong unsigned int cmp_slt_s;\n\tlong unsigned int cmp_slt_d;\n\tlong unsigned int cmp_sne_s;\n\tlong unsigned int cmp_sne_d;\n\tlong unsigned int cmp_sor_s;\n\tlong unsigned int cmp_sor_d;\n\tlong unsigned int cmp_sueq_s;\n\tlong unsigned int cmp_sueq_d;\n\tlong unsigned int cmp_sule_s;\n\tlong unsigned int cmp_sule_d;\n\tlong unsigned int cmp_sult_s;\n\tlong unsigned int cmp_sult_d;\n\tlong unsigned int cmp_sun_s;\n\tlong unsigned int cmp_sun_d;\n\tlong unsigned int cmp_sune_s;\n\tlong unsigned int cmp_sune_d;\n\tlong unsigned int cvt_d_l;\n\tlong unsigned int cvt_d_s;\n\tlong unsigned int cvt_d_w;\n\tlong unsigned int cvt_l_s;\n\tlong unsigned int cvt_l_d;\n\tlong unsigned int cvt_s_d;\n\tlong unsigned int cvt_s_l;\n\tlong unsigned int cvt_s_w;\n\tlong unsigned int cvt_w_s;\n\tlong unsigned int cvt_w_d;\n\tlong unsigned int div_s;\n\tlong unsigned int div_d;\n\tlong unsigned int floor_w_s;\n\tlong unsigned int floor_w_d;\n\tlong unsigned int floor_l_s;\n\tlong unsigned int floor_l_d;\n\tlong unsigned int maddf_s;\n\tlong unsigned int maddf_d;\n\tlong unsigned int max_s;\n\tlong unsigned int max_d;\n\tlong unsigned int maxa_s;\n\tlong unsigned int maxa_d;\n\tlong unsigned int min_s;\n\tlong unsigned int min_d;\n\tlong unsigned int mina_s;\n\tlong unsigned int mina_d;\n\tlong unsigned int mov_s;\n\tlong unsigned int mov_d;\n\tlong unsigned int msubf_s;\n\tlong unsigned int msubf_d;\n\tlong unsigned int mul_s;\n\tlong unsigned int mul_d;\n\tlong unsigned int neg_s;\n\tlong unsigned int neg_d;\n\tlong unsigned int recip_s;\n\tlong unsigned int recip_d;\n\tlong unsigned int rint_s;\n\tlong unsigned int rint_d;\n\tlong unsigned int round_w_s;\n\tlong unsigned int round_w_d;\n\tlong unsigned int round_l_s;\n\tlong unsigned int round_l_d;\n\tlong unsigned int rsqrt_s;\n\tlong unsigned int rsqrt_d;\n\tlong unsigned int sel_s;\n\tlong unsigned int sel_d;\n\tlong unsigned int seleqz_s;\n\tlong unsigned int seleqz_d;\n\tlong unsigned int selnez_s;\n\tlong unsigned int selnez_d;\n\tlong unsigned int sqrt_s;\n\tlong unsigned int sqrt_d;\n\tlong unsigned int sub_s;\n\tlong unsigned int sub_d;\n\tlong unsigned int trunc_w_s;\n\tlong unsigned int trunc_w_d;\n\tlong unsigned int trunc_l_s;\n\tlong unsigned int trunc_l_d;\n};\n\nstruct mips_fpu_struct {\n\tunion fpureg fpr[32];\n\tunsigned int fcr31;\n\tunsigned int msacsr;\n};\n\nstruct mips_frame_info {\n\tvoid *func;\n\tlong unsigned int func_size;\n\tint frame_size;\n\tint pc_offset;\n};\n\nstruct mips_hi16 {\n\tstruct mips_hi16 *next;\n\tElf32_Addr *addr;\n\tElf32_Addr value;\n};\n\nstruct mips_huge_tlb_info {\n\tint huge_pte;\n\tint restore_scratch;\n\tbool need_reload_pte;\n};\n\nstruct u_format {\n\tunsigned int uimmediate: 16;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct r_format {\n\tunsigned int func: 6;\n\tunsigned int re: 5;\n\tunsigned int rd: 5;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct p_format {\n\tunsigned int func: 6;\n\tunsigned int re: 5;\n\tunsigned int rd: 5;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct msa_mi10_format {\n\tunsigned int df: 2;\n\tunsigned int func: 4;\n\tunsigned int wd: 5;\n\tunsigned int rs: 5;\n\tint s10: 10;\n\tunsigned int opcode: 6;\n};\n\nstruct ps_format {\n\tunsigned int func: 6;\n\tunsigned int fd: 5;\n\tunsigned int fs: 5;\n\tunsigned int ft: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct v_format {\n\tunsigned int func: 6;\n\tunsigned int vd: 5;\n\tunsigned int vs: 5;\n\tunsigned int vt: 5;\n\tunsigned int fmt: 1;\n\tunsigned int sel: 4;\n\tunsigned int opcode: 6;\n};\n\nstruct spec3_format {\n\tunsigned int func: 7;\n\tint simmediate: 9;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_fp0_format {\n\tunsigned int func: 6;\n\tunsigned int op: 2;\n\tunsigned int fmt: 3;\n\tunsigned int fd: 5;\n\tunsigned int fs: 5;\n\tunsigned int ft: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_fp1_format {\n\tunsigned int func: 6;\n\tunsigned int op: 8;\n\tunsigned int fmt: 2;\n\tunsigned int fs: 5;\n\tunsigned int rt: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_fp2_format {\n\tunsigned int func: 6;\n\tunsigned int op: 3;\n\tunsigned int fmt: 2;\n\tunsigned int zero: 2;\n\tunsigned int cc: 3;\n\tunsigned int fs: 5;\n\tunsigned int fd: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_fp3_format {\n\tunsigned int func: 6;\n\tunsigned int op: 7;\n\tunsigned int fmt: 3;\n\tunsigned int fs: 5;\n\tunsigned int rt: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_fp4_format {\n\tunsigned int func: 6;\n\tunsigned int cond: 4;\n\tunsigned int fmt: 3;\n\tunsigned int cc: 3;\n\tunsigned int fs: 5;\n\tunsigned int rt: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_fp5_format {\n\tunsigned int func: 6;\n\tunsigned int op: 5;\n\tunsigned int fd: 5;\n\tunsigned int base: 5;\n\tunsigned int index: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_fp6_format {\n\tunsigned int func: 6;\n\tunsigned int fr: 5;\n\tunsigned int fd: 5;\n\tunsigned int fs: 5;\n\tunsigned int ft: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_i_format {\n\tint simmediate: 16;\n\tunsigned int rs: 5;\n\tunsigned int rt: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_m_format {\n\tint simmediate: 12;\n\tunsigned int func: 4;\n\tunsigned int base: 5;\n\tunsigned int rd: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_x_format {\n\tunsigned int func: 11;\n\tunsigned int rd: 5;\n\tunsigned int base: 5;\n\tunsigned int index: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_a_format {\n\tint simmediate: 23;\n\tunsigned int rs: 3;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_b0_format {\n\tshort: 16;\n\tint simmediate: 10;\n\tunsigned int opcode: 6;\n};\n\nstruct mm_b1_format {\n\tshort: 16;\n\tint simmediate: 7;\n\tunsigned int rs: 3;\n\tunsigned int opcode: 6;\n};\n\nstruct mm16_m_format {\n\tshort: 16;\n\tunsigned int imm: 4;\n\tunsigned int rlist: 2;\n\tunsigned int func: 4;\n\tunsigned int opcode: 6;\n};\n\nstruct mm16_rb_format {\n\tshort: 16;\n\tint simmediate: 4;\n\tunsigned int base: 3;\n\tunsigned int rt: 3;\n\tunsigned int opcode: 6;\n};\n\nstruct mm16_r3_format {\n\tshort: 16;\n\tint simmediate: 7;\n\tunsigned int rt: 3;\n\tunsigned int opcode: 6;\n};\n\nstruct mm16_r5_format {\n\tshort: 16;\n\tunsigned int imm: 5;\n\tunsigned int rt: 5;\n\tunsigned int opcode: 6;\n};\n\nstruct mxu_lx_format {\n\tunsigned int func: 6;\n\tunsigned int op: 3;\n\tunsigned int strd: 2;\n\tunsigned int rd: 5;\n\tunsigned int rt: 5;\n\tunsigned int rs: 5;\n\tunsigned int opcode: 6;\n};\n\nunion mips_instruction {\n\tunsigned int word;\n\tshort unsigned int halfword[2];\n\tunsigned char byte[4];\n\tstruct j_format j_format;\n\tstruct i_format i_format;\n\tstruct u_format u_format;\n\tstruct c_format c_format;\n\tstruct r_format r_format;\n\tstruct c0r_format c0r_format;\n\tstruct mfmc0_format mfmc0_format;\n\tstruct co_format co_format;\n\tstruct p_format p_format;\n\tstruct f_format f_format;\n\tstruct ma_format ma_format;\n\tstruct msa_mi10_format msa_mi10_format;\n\tstruct b_format b_format;\n\tstruct ps_format ps_format;\n\tstruct v_format v_format;\n\tstruct dsp_format dsp_format;\n\tstruct spec3_format spec3_format;\n\tstruct fb_format fb_format;\n\tstruct fp0_format fp0_format;\n\tstruct mm_fp0_format mm_fp0_format;\n\tstruct fp1_format fp1_format;\n\tstruct mm_fp1_format mm_fp1_format;\n\tstruct mm_fp2_format mm_fp2_format;\n\tstruct mm_fp3_format mm_fp3_format;\n\tstruct mm_fp4_format mm_fp4_format;\n\tstruct mm_fp5_format mm_fp5_format;\n\tstruct fp6_format fp6_format;\n\tstruct mm_fp6_format mm_fp6_format;\n\tstruct mm_i_format mm_i_format;\n\tstruct mm_m_format mm_m_format;\n\tstruct mm_x_format mm_x_format;\n\tstruct mm_a_format mm_a_format;\n\tstruct mm_b0_format mm_b0_format;\n\tstruct mm_b1_format mm_b1_format;\n\tstruct mm16_m_format mm16_m_format;\n\tstruct mm16_rb_format mm16_rb_format;\n\tstruct mm16_r3_format mm16_r3_format;\n\tstruct mm16_r5_format mm16_r5_format;\n\tstruct loongson3_lswc2_format loongson3_lswc2_format;\n\tstruct loongson3_lsdc2_format loongson3_lsdc2_format;\n\tstruct loongson3_lscsr_format loongson3_lscsr_format;\n\tstruct mxu_lx_format mxu_lx_format;\n};\n\nstruct mips_machine {\n\tconst struct of_device_id *matches;\n\tconst void *fdt;\n\tbool (*detect)(void);\n\tconst void * (*fixup_fdt)(const void *, const void *);\n\tunsigned int (*measure_hpt_freq)(void);\n};\n\nstruct mips_static_suspend_state {\n\tlong unsigned int sp;\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct mips_vdso_image {\n\tvoid *data;\n\tlong unsigned int size;\n\tlong unsigned int off_sigreturn;\n\tlong unsigned int off_rt_sigreturn;\n\tstruct vm_special_mapping mapping;\n};\n\nunion mips_watch_reg_state {\n\tstruct mips3264_watch_reg_state mips3264;\n};\n\nstruct ml_effect_state {\n\tstruct ff_effect *effect;\n\tlong unsigned int flags;\n\tint count;\n\tlong unsigned int play_at;\n\tlong unsigned int stop_at;\n\tlong unsigned int adj_at;\n};\n\nstruct ml_device {\n\tvoid *private;\n\tstruct ml_effect_state states[16];\n\tint gain;\n\tstruct timer_list timer;\n\tstruct input_dev *dev;\n\tint (*play_effect)(struct input_dev *, void *, struct ff_effect *);\n};\n\nstruct mld2_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\tstruct in6_addr grec_mca;\n\tstruct in6_addr grec_src[0];\n};\n\nstruct mld2_query {\n\tstruct icmp6hdr mld2q_hdr;\n\tstruct in6_addr mld2q_mca;\n\t__u8 mld2q_qrv: 3;\n\t__u8 mld2q_suppress: 1;\n\t__u8 mld2q_resv2: 4;\n\t__u8 mld2q_qqic;\n\t__be16 mld2q_nsrcs;\n\tstruct in6_addr mld2q_srcs[0];\n};\n\nstruct mld2_report {\n\tstruct icmp6hdr mld2r_hdr;\n\tstruct mld2_grec mld2r_grec[0];\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mm_decoded_insn {\n\tmips_instruction insn;\n\tmips_instruction next_insn;\n\tint pc_inc;\n\tint next_pc_inc;\n\tint micro_mips_mode;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tlong: 32;\n\tstruct ethtool_mm_stats stats;\n};\n\nstruct uprobes_state {};\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tlong: 32;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[48];\n\t\tlong: 32;\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tlong: 32;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct task_struct *owner;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tatomic_t tlb_flush_pending;\n\t\tstruct uprobes_state uprobes_state;\n\t\tstruct work_struct async_put_work;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n\tstruct task_struct *owner;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mmc_blk_busy_data {\n\tstruct mmc_card *card;\n\tu32 status;\n};\n\nstruct mmc_ctx {\n\tstruct task_struct *task;\n};\n\nstruct mmc_blk_data;\n\nstruct mmc_queue {\n\tstruct mmc_card *card;\n\tstruct mmc_ctx ctx;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct mmc_blk_data *blkdata;\n\tstruct request_queue *queue;\n\tspinlock_t lock;\n\tint in_flight[3];\n\tunsigned int cqe_busy;\n\tbool busy;\n\tbool recovery_needed;\n\tbool in_recovery;\n\tbool rw_wait;\n\tbool waiting;\n\tstruct work_struct recovery_work;\n\twait_queue_head_t wait;\n\tstruct request *recovery_req;\n\tstruct request *complete_req;\n\tstruct mutex complete_lock;\n\tstruct work_struct complete_work;\n};\n\nstruct mmc_blk_data {\n\tstruct device *parent;\n\tstruct gendisk *disk;\n\tstruct mmc_queue queue;\n\tstruct list_head part;\n\tstruct list_head rpmbs;\n\tunsigned int flags;\n\tstruct kref kref;\n\tunsigned int read_only;\n\tunsigned int part_type;\n\tunsigned int reset_done;\n\tunsigned int part_curr;\n\tint area_type;\n\tstruct dentry *status_dentry;\n\tstruct dentry *ext_csd_dentry;\n};\n\nstruct mmc_ioc_cmd {\n\tint write_flag;\n\tint is_acmd;\n\t__u32 opcode;\n\t__u32 arg;\n\t__u32 response[4];\n\tunsigned int flags;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int postsleep_min_us;\n\tunsigned int postsleep_max_us;\n\tunsigned int data_timeout_ns;\n\tunsigned int cmd_timeout_ms;\n\t__u32 __pad;\n\t__u64 data_ptr;\n};\n\nstruct mmc_rpmb_data;\n\nstruct mmc_blk_ioc_data {\n\tstruct mmc_ioc_cmd ic;\n\tunsigned char *buf;\n\tlong: 32;\n\tu64 buf_bytes;\n\tunsigned int flags;\n\tstruct mmc_rpmb_data *rpmb;\n};\n\nstruct uhs2_command {\n\tu16 header;\n\tu16 arg;\n\t__be32 payload[2];\n\tu8 payload_len;\n\tu8 packet_len;\n\tu8 tmode_half_duplex;\n\tu8 uhs2_resp[20];\n\tu8 uhs2_resp_len;\n};\n\nstruct mmc_request {\n\tstruct mmc_command *sbc;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command *stop;\n\tstruct completion completion;\n\tstruct completion cmd_completion;\n\tvoid (*done)(struct mmc_request *);\n\tvoid (*recovery_notifier)(struct mmc_request *);\n\tstruct mmc_host *host;\n\tbool cap_cmd_during_tfr;\n\tint tag;\n\tstruct uhs2_command uhs2_cmd;\n};\n\nstruct mmc_data {\n\tunsigned int timeout_ns;\n\tunsigned int timeout_clks;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int blk_addr;\n\tint error;\n\tunsigned int flags;\n\tunsigned int bytes_xfered;\n\tstruct mmc_command *stop;\n\tstruct mmc_request *mrq;\n\tunsigned int sg_len;\n\tint sg_count;\n\tstruct scatterlist *sg;\n\ts32 host_cookie;\n};\n\nstruct mmc_blk_request {\n\tstruct mmc_request mrq;\n\tstruct mmc_command sbc;\n\tstruct mmc_command cmd;\n\tstruct mmc_command stop;\n\tstruct mmc_data data;\n};\n\nstruct mmc_bus_ops {\n\tvoid (*remove)(struct mmc_host *);\n\tvoid (*detect)(struct mmc_host *);\n\tint (*pre_suspend)(struct mmc_host *);\n\tint (*suspend)(struct mmc_host *);\n\tint (*resume)(struct mmc_host *);\n\tint (*runtime_suspend)(struct mmc_host *);\n\tint (*runtime_resume)(struct mmc_host *);\n\tint (*alive)(struct mmc_host *);\n\tint (*shutdown)(struct mmc_host *);\n\tint (*hw_reset)(struct mmc_host *);\n\tint (*sw_reset)(struct mmc_host *);\n\tbool (*cache_enabled)(struct mmc_host *);\n\tint (*flush_cache)(struct mmc_host *);\n\tint (*handle_undervoltage)(struct mmc_host *);\n};\n\nstruct mmc_busy_data {\n\tstruct mmc_card *card;\n\tbool retry_crc_err;\n\tenum mmc_busy_cmd busy_cmd;\n};\n\nstruct mmc_cid {\n\tunsigned int manfid;\n\tchar prod_name[8];\n\tunsigned char prv;\n\tunsigned int serial;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char hwrev;\n\tunsigned char fwrev;\n\tunsigned char month;\n};\n\nstruct mmc_csd {\n\tunsigned char structure;\n\tunsigned char mmca_vsn;\n\tshort unsigned int cmdclass;\n\tshort unsigned int taac_clks;\n\tunsigned int taac_ns;\n\tunsigned int c_size;\n\tunsigned int r2w_factor;\n\tunsigned int max_dtr;\n\tunsigned int erase_size;\n\tunsigned int wp_grp_size;\n\tunsigned int read_blkbits;\n\tunsigned int write_blkbits;\n\tsector_t capacity;\n\tunsigned int read_partial: 1;\n\tunsigned int read_misalign: 1;\n\tunsigned int write_partial: 1;\n\tunsigned int write_misalign: 1;\n\tunsigned int dsr_imp: 1;\n\tlong: 32;\n};\n\nstruct mmc_ext_csd {\n\tu8 rev;\n\tu8 erase_group_def;\n\tu8 sec_feature_support;\n\tu8 rel_sectors;\n\tu8 rel_param;\n\tbool enhanced_rpmb_supported;\n\tu8 part_config;\n\tu8 cache_ctrl;\n\tu8 rst_n_function;\n\tunsigned int part_time;\n\tunsigned int sa_timeout;\n\tunsigned int generic_cmd6_time;\n\tunsigned int power_off_longtime;\n\tu8 power_off_notification;\n\tunsigned int hs_max_dtr;\n\tunsigned int hs200_max_dtr;\n\tunsigned int sectors;\n\tunsigned int hc_erase_size;\n\tunsigned int hc_erase_timeout;\n\tunsigned int sec_trim_mult;\n\tunsigned int sec_erase_mult;\n\tunsigned int trim_timeout;\n\tbool partition_setting_completed;\n\tlong: 32;\n\tlong long unsigned int enhanced_area_offset;\n\tunsigned int enhanced_area_size;\n\tunsigned int cache_size;\n\tbool hpi_en;\n\tbool hpi;\n\tunsigned int hpi_cmd;\n\tbool bkops;\n\tbool man_bkops_en;\n\tbool auto_bkops_en;\n\tunsigned int data_sector_size;\n\tunsigned int data_tag_unit_size;\n\tunsigned int boot_ro_lock;\n\tbool boot_ro_lockable;\n\tbool ffu_capable;\n\tbool cmdq_en;\n\tbool cmdq_support;\n\tunsigned int cmdq_depth;\n\tu8 fwrev[8];\n\tu8 raw_exception_status;\n\tu8 raw_partition_support;\n\tu8 raw_rpmb_size_mult;\n\tu8 raw_erased_mem_count;\n\tu8 strobe_support;\n\tu8 raw_ext_csd_structure;\n\tu8 raw_card_type;\n\tu8 raw_driver_strength;\n\tu8 out_of_int_time;\n\tu8 raw_pwr_cl_52_195;\n\tu8 raw_pwr_cl_26_195;\n\tu8 raw_pwr_cl_52_360;\n\tu8 raw_pwr_cl_26_360;\n\tu8 raw_s_a_timeout;\n\tu8 raw_hc_erase_gap_size;\n\tu8 raw_erase_timeout_mult;\n\tu8 raw_hc_erase_grp_size;\n\tu8 raw_boot_mult;\n\tu8 raw_sec_trim_mult;\n\tu8 raw_sec_erase_mult;\n\tu8 raw_sec_feature_support;\n\tu8 raw_trim_mult;\n\tu8 raw_pwr_cl_200_195;\n\tu8 raw_pwr_cl_200_360;\n\tu8 raw_pwr_cl_ddr_52_195;\n\tu8 raw_pwr_cl_ddr_52_360;\n\tu8 raw_pwr_cl_ddr_200_360;\n\tu8 raw_bkops_status;\n\tu8 raw_sectors[4];\n\tu8 pre_eol_info;\n\tu8 device_life_time_est_typ_a;\n\tu8 device_life_time_est_typ_b;\n\tunsigned int feature_support;\n};\n\nstruct sd_scr {\n\tunsigned char sda_vsn;\n\tunsigned char sda_spec3;\n\tunsigned char sda_spec4;\n\tunsigned char sda_specx;\n\tunsigned char bus_widths;\n\tunsigned char cmds;\n};\n\nstruct sd_ssr {\n\tunsigned int au;\n\tunsigned int erase_timeout;\n\tunsigned int erase_offset;\n};\n\nstruct sd_switch_caps {\n\tunsigned int hs_max_dtr;\n\tunsigned int uhs_max_dtr;\n\tunsigned int sd3_bus_mode;\n\tunsigned int sd3_drv_type;\n\tunsigned int sd3_curr_limit;\n};\n\nstruct sd_ext_reg {\n\tu8 fno;\n\tu8 page;\n\tu16 offset;\n\tu8 rev;\n\tu8 feature_enabled;\n\tu8 feature_support;\n};\n\nstruct sd_uhs2_config {\n\tu32 node_id;\n\tu32 n_fcu;\n\tu32 maxblk_len;\n\tu8 n_lanes;\n\tu8 dadr_len;\n\tu8 app_type;\n\tu8 phy_minor_rev;\n\tu8 phy_major_rev;\n\tu8 can_hibernate;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_minor_rev;\n\tu8 link_major_rev;\n\tu8 dev_type;\n\tu8 n_data_gap;\n\tu32 n_fcu_set;\n\tu32 maxblk_len_set;\n\tu8 n_lanes_set;\n\tu8 speed_range_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct sdio_cccr {\n\tunsigned int sdio_vsn;\n\tunsigned int sd_vsn;\n\tunsigned int multi_block: 1;\n\tunsigned int low_speed: 1;\n\tunsigned int wide_bus: 1;\n\tunsigned int high_power: 1;\n\tunsigned int high_speed: 1;\n\tunsigned int disable_cd: 1;\n\tunsigned int enable_async_irq: 1;\n};\n\nstruct sdio_cis {\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int blksize;\n\tunsigned int max_dtr;\n};\n\nstruct mmc_part {\n\tu64 size;\n\tunsigned int part_cfg;\n\tchar name[20];\n\tbool force_ro;\n\tunsigned int area_type;\n};\n\nstruct sdio_func_tuple;\n\nstruct mmc_card {\n\tstruct mmc_host *host;\n\tlong: 32;\n\tstruct device dev;\n\tu32 ocr;\n\tunsigned int rca;\n\tunsigned int type;\n\tunsigned int state;\n\tunsigned int quirks;\n\tunsigned int quirk_max_rate;\n\tbool written_flag;\n\tbool reenable_cmdq;\n\tunsigned int erase_size;\n\tunsigned int erase_shift;\n\tunsigned int pref_erase;\n\tunsigned int eg_boundary;\n\tunsigned int erase_arg;\n\tu8 erased_byte;\n\tunsigned int wp_grp_size;\n\tu32 raw_cid[4];\n\tu32 raw_csd[4];\n\tu32 raw_scr[2];\n\tu32 raw_ssr[16];\n\tstruct mmc_cid cid;\n\tlong: 32;\n\tstruct mmc_csd csd;\n\tstruct mmc_ext_csd ext_csd;\n\tstruct sd_scr scr;\n\tstruct sd_ssr ssr;\n\tstruct sd_switch_caps sw_caps;\n\tstruct sd_ext_reg ext_power;\n\tstruct sd_ext_reg ext_perf;\n\tstruct sd_uhs2_config uhs2_config;\n\tunsigned int sdio_funcs;\n\tatomic_t sdio_funcs_probed;\n\tstruct sdio_cccr cccr;\n\tstruct sdio_cis cis;\n\tstruct sdio_func *sdio_func[7];\n\tstruct sdio_func *sdio_single_irq;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n\tunsigned int sd_bus_speed;\n\tunsigned int mmc_avail_type;\n\tunsigned int drive_strength;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_part part[7];\n\tunsigned int nr_parts;\n\tstruct workqueue_struct *complete_wq;\n};\n\nstruct mmc_clk_phase {\n\tbool valid;\n\tu16 in_deg;\n\tu16 out_deg;\n};\n\nstruct mmc_clk_phase_map {\n\tstruct mmc_clk_phase phase[11];\n};\n\nstruct mmc_cqe_ops {\n\tint (*cqe_enable)(struct mmc_host *, struct mmc_card *);\n\tvoid (*cqe_disable)(struct mmc_host *);\n\tint (*cqe_request)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_post_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_off)(struct mmc_host *);\n\tint (*cqe_wait_for_idle)(struct mmc_host *);\n\tbool (*cqe_timeout)(struct mmc_host *, struct mmc_request *, bool *);\n\tvoid (*cqe_recovery_start)(struct mmc_host *);\n\tvoid (*cqe_recovery_finish)(struct mmc_host *);\n};\n\nstruct mmc_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct mmc_card *);\n\tvoid (*remove)(struct mmc_card *);\n\tvoid (*shutdown)(struct mmc_card *);\n};\n\nstruct mmc_fixup {\n\tconst char *name;\n\tlong: 32;\n\tu64 rev_start;\n\tu64 rev_end;\n\tunsigned int manfid;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char month;\n\tu16 cis_vendor;\n\tu16 cis_device;\n\tunsigned int ext_csd_rev;\n\tconst char *of_compatible;\n\tvoid (*vendor_fixup)(struct mmc_card *, int);\n\tint data;\n};\n\nstruct mmc_gpio {\n\tstruct gpio_desc *ro_gpio;\n\tstruct gpio_desc *cd_gpio;\n\tirq_handler_t cd_gpio_isr;\n\tchar *ro_label;\n\tchar *cd_label;\n\tu32 cd_debounce_delay_ms;\n\tint cd_irq;\n};\n\nstruct sd_uhs2_caps {\n\tu32 dap;\n\tu32 gap;\n\tu32 group_desc;\n\tu32 maxblk_len;\n\tu32 n_fcu;\n\tu8 n_lanes;\n\tu8 addr64;\n\tu8 card_type;\n\tu8 phy_rev;\n\tu8 speed_range;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_rev;\n\tu8 host_type;\n\tu8 n_data_gap;\n\tu32 maxblk_len_set;\n\tu32 n_fcu_set;\n\tu8 n_lanes_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct mmc_ios {\n\tunsigned int clock;\n\tshort unsigned int vdd;\n\tunsigned int power_delay_ms;\n\tunsigned char bus_mode;\n\tunsigned char chip_select;\n\tunsigned char power_mode;\n\tunsigned char bus_width;\n\tunsigned char timing;\n\tunsigned char signal_voltage;\n\tunsigned char vqmmc2_voltage;\n\tunsigned char drv_type;\n\tbool enhanced_strobe;\n};\n\nstruct mmc_slot {\n\tint cd_irq;\n\tbool cd_wake_enabled;\n\tvoid *handler_priv;\n};\n\nstruct mmc_supply {\n\tstruct regulator *vmmc;\n\tstruct regulator *vqmmc;\n\tstruct regulator *vqmmc2;\n\tstruct notifier_block vmmc_nb;\n\tstruct work_struct uv_work;\n};\n\nstruct mmc_host_ops;\n\nstruct mmc_pwrseq;\n\nstruct mmc_host {\n\tstruct device *parent;\n\tlong: 32;\n\tstruct device class_dev;\n\tint index;\n\tconst struct mmc_host_ops *ops;\n\tstruct mmc_pwrseq *pwrseq;\n\tunsigned int f_min;\n\tunsigned int f_max;\n\tunsigned int f_init;\n\tu32 ocr_avail;\n\tu32 ocr_avail_sdio;\n\tu32 ocr_avail_sd;\n\tu32 ocr_avail_mmc;\n\tstruct wakeup_source *ws;\n\tu32 max_current_330;\n\tu32 max_current_300;\n\tu32 max_current_180;\n\tu32 caps;\n\tu32 caps2;\n\tbool uhs2_sd_tran;\n\tbool uhs2_app_cmd;\n\tstruct sd_uhs2_caps uhs2_caps;\n\tint fixed_drv_type;\n\tmmc_pm_flag_t pm_caps;\n\tunsigned int max_seg_size;\n\tshort unsigned int max_segs;\n\tshort unsigned int unused;\n\tunsigned int max_req_size;\n\tunsigned int max_blk_size;\n\tunsigned int max_blk_count;\n\tunsigned int max_busy_timeout;\n\tspinlock_t lock;\n\tstruct mmc_ios ios;\n\tbool claimed;\n\tunsigned int use_spi_crc: 1;\n\tunsigned int doing_init_tune: 1;\n\tunsigned int doing_retune: 1;\n\tunsigned int retune_crc_disable: 1;\n\tunsigned int can_dma_map_merge: 1;\n\tunsigned int vqmmc_enabled: 1;\n\tunsigned int undervoltage: 1;\n\tint rescan_disable;\n\tint rescan_entered;\n\tbool can_retune;\n\tbool retune_now;\n\tbool retune_paused;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct timer_list retune_timer;\n\tbool trigger_card_event;\n\tstruct mmc_card *card;\n\twait_queue_head_t wq;\n\tstruct mmc_ctx *claimer;\n\tint claim_cnt;\n\tstruct mmc_ctx default_ctx;\n\tstruct delayed_work detect;\n\tint detect_change;\n\tstruct mmc_slot slot;\n\tconst struct mmc_bus_ops *bus_ops;\n\tunsigned int sdio_irqs;\n\tstruct task_struct *sdio_irq_thread;\n\tstruct work_struct sdio_irq_work;\n\tbool sdio_irq_pending;\n\tatomic_t sdio_irq_thread_abort;\n\tmmc_pm_flag_t pm_flags;\n\tstruct led_trigger *led;\n\tbool regulator_enabled;\n\tstruct mmc_supply supply;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_request *ongoing_mrq;\n\tunsigned int actual_clock;\n\tunsigned int slotno;\n\tint dsr_req;\n\tu32 dsr;\n\tconst struct mmc_cqe_ops *cqe_ops;\n\tvoid *cqe_private;\n\tint cqe_qdepth;\n\tbool cqe_enabled;\n\tbool cqe_on;\n\tbool hsq_enabled;\n\tint hsq_depth;\n\tu32 err_stats[15];\n\tu32 max_sd_hs_hz;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct mmc_host_ops {\n\tvoid (*post_req)(struct mmc_host *, struct mmc_request *, int);\n\tvoid (*pre_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*request)(struct mmc_host *, struct mmc_request *);\n\tint (*request_atomic)(struct mmc_host *, struct mmc_request *);\n\tvoid (*set_ios)(struct mmc_host *, struct mmc_ios *);\n\tint (*get_ro)(struct mmc_host *);\n\tint (*get_cd)(struct mmc_host *);\n\tvoid (*enable_sdio_irq)(struct mmc_host *, int);\n\tvoid (*ack_sdio_irq)(struct mmc_host *);\n\tvoid (*init_card)(struct mmc_host *, struct mmc_card *);\n\tint (*start_signal_voltage_switch)(struct mmc_host *, struct mmc_ios *);\n\tint (*card_busy)(struct mmc_host *);\n\tint (*execute_tuning)(struct mmc_host *, u32);\n\tint (*prepare_hs400_tuning)(struct mmc_host *, struct mmc_ios *);\n\tint (*execute_hs400_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*prepare_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*execute_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*hs400_prepare_ddr)(struct mmc_host *);\n\tvoid (*hs400_downgrade)(struct mmc_host *);\n\tvoid (*hs400_complete)(struct mmc_host *);\n\tvoid (*hs400_enhanced_strobe)(struct mmc_host *, struct mmc_ios *);\n\tint (*select_drive_strength)(struct mmc_card *, unsigned int, int, int, int *);\n\tvoid (*card_hw_reset)(struct mmc_host *);\n\tvoid (*card_event)(struct mmc_host *);\n\tint (*multi_io_quirk)(struct mmc_card *, unsigned int, int);\n\tint (*init_sd_express)(struct mmc_host *, struct mmc_ios *);\n\tint (*uhs2_control)(struct mmc_host *, enum sd_uhs2_operation);\n};\n\nstruct mmc_ioc_multi_cmd {\n\t__u64 num_of_cmds;\n\tstruct mmc_ioc_cmd cmds[0];\n};\n\nstruct mmc_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct mmc_pwrseq_ops;\n\nstruct mmc_pwrseq {\n\tconst struct mmc_pwrseq_ops *ops;\n\tstruct device *dev;\n\tstruct list_head pwrseq_node;\n\tstruct module *owner;\n};\n\nstruct mmc_pwrseq_emmc {\n\tstruct mmc_pwrseq pwrseq;\n\tstruct notifier_block reset_nb;\n\tstruct gpio_desc *reset_gpio;\n};\n\nstruct mmc_pwrseq_ops {\n\tvoid (*pre_power_on)(struct mmc_host *);\n\tvoid (*post_power_on)(struct mmc_host *);\n\tvoid (*power_off)(struct mmc_host *);\n\tvoid (*reset)(struct mmc_host *);\n};\n\nstruct mmc_pwrseq_simple {\n\tstruct mmc_pwrseq pwrseq;\n\tbool clk_enabled;\n\tu32 post_power_on_delay_ms;\n\tu32 power_off_delay_us;\n\tstruct clk *ext_clk;\n\tstruct gpio_descs *reset_gpios;\n\tstruct reset_control *reset_ctrl;\n};\n\nstruct mmc_queue_req {\n\tstruct mmc_blk_request brq;\n\tstruct scatterlist *sg;\n\tenum mmc_drv_op drv_op;\n\tint drv_op_result;\n\tvoid *drv_op_data;\n\tunsigned int ioc_count;\n\tint retries;\n};\n\nstruct rpmb_dev;\n\nstruct mmc_rpmb_data {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tunsigned int part_index;\n\tstruct mmc_blk_data *md;\n\tstruct rpmb_dev *rdev;\n\tstruct list_head node;\n\tlong: 32;\n};\n\nstruct spi_delay {\n\tu16 value;\n\tu8 unit;\n};\n\nstruct ptp_system_timestamp;\n\nstruct spi_transfer {\n\tconst void *tx_buf;\n\tvoid *rx_buf;\n\tunsigned int len;\n\tu16 error;\n\tbool tx_sg_mapped;\n\tbool rx_sg_mapped;\n\tstruct sg_table tx_sg;\n\tstruct sg_table rx_sg;\n\tdma_addr_t tx_dma;\n\tdma_addr_t rx_dma;\n\tunsigned int dummy_data: 1;\n\tunsigned int cs_off: 1;\n\tunsigned int cs_change: 1;\n\tunsigned int tx_nbits: 4;\n\tunsigned int rx_nbits: 4;\n\tunsigned int multi_lane_mode: 2;\n\tunsigned int timestamped: 1;\n\tbool dtr_mode;\n\tu8 bits_per_word;\n\tstruct spi_delay delay;\n\tstruct spi_delay cs_change_delay;\n\tstruct spi_delay word_delay;\n\tu32 speed_hz;\n\tu32 effective_speed_hz;\n\tunsigned int offload_flags;\n\tunsigned int ptp_sts_word_pre;\n\tunsigned int ptp_sts_word_post;\n\tstruct ptp_system_timestamp *ptp_sts;\n\tstruct list_head transfer_list;\n};\n\nstruct spi_offload;\n\nstruct spi_message {\n\tstruct list_head transfers;\n\tstruct spi_device *spi;\n\tbool pre_optimized;\n\tbool optimized;\n\tbool prepared;\n\tint status;\n\tvoid (*complete)(void *);\n\tvoid *context;\n\tunsigned int frame_length;\n\tunsigned int actual_length;\n\tstruct list_head queue;\n\tvoid *state;\n\tvoid *opt_state;\n\tstruct spi_offload *offload;\n\tstruct list_head resources;\n};\n\nstruct mmc_spi_platform_data;\n\nstruct scratch;\n\nstruct mmc_spi_host {\n\tstruct mmc_host *mmc;\n\tstruct spi_device *spi;\n\tunsigned char power_mode;\n\tu16 powerup_msecs;\n\tstruct mmc_spi_platform_data *pdata;\n\tstruct spi_transfer token;\n\tstruct spi_transfer t;\n\tstruct spi_transfer crc;\n\tstruct spi_transfer early_status;\n\tstruct spi_message m;\n\tstruct spi_transfer status;\n\tstruct spi_message readback;\n\tstruct scratch *data;\n\tvoid *ones;\n};\n\nstruct mmc_spi_platform_data {\n\tint (*init)(struct device *, irqreturn_t (*)(int, void *), void *);\n\tvoid (*exit)(struct device *, void *);\n\tlong unsigned int caps;\n\tlong unsigned int caps2;\n\tu16 detect_delay;\n\tu16 powerup_msecs;\n\tu32 ocr_mask;\n\tvoid (*setpower)(struct device *, unsigned int);\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct encoded_page;\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct encoded_page *encoded_pages[0];\n};\n\nstruct mmu_table_batch;\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tstruct mmu_table_batch *batch;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n};\n\nstruct mmu_notifier_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_table_batch {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tvoid *tables[0];\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tlong: 32;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct mod_arch_specific {\n\tstruct list_head dbe_list;\n\tconst struct exception_table_entry *dbe_start;\n\tconst struct exception_table_entry *dbe_end;\n\tstruct mips_hi16 *r_mips_hi16_list;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf32_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_root {\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct mode_info {\n\tconst char *mode;\n\tu32 magic;\n\tstruct list_head list;\n};\n\nstruct mode_req {\n\tbool single;\n\tbool soft;\n\tbool fr1;\n\tbool frdefault;\n\tbool fre;\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n};\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[60];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n\tlong: 32;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct mountres {\n\tint errno;\n\tstruct nfs_fh *fh;\n\tunsigned int *auth_count;\n\trpc_authflavor_t *auth_flavors;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tunsigned int can_map: 1;\n\tlong: 32;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tloff_t end_pos;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n\tunsigned int journalled_more_data: 1;\n\tlong: 32;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tlong: 32;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n\tlong: 32;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mptcp_out_options {};\n\nstruct mptcp_sock {};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct ms_data {\n\tlong unsigned int quirks;\n\tstruct hid_device *hdev;\n\tstruct work_struct ff_worker;\n\t__u8 strong;\n\t__u8 weak;\n\tvoid *output_report_dmabuf;\n};\n\nstruct mscc_miim_info;\n\nstruct mscc_miim_dev {\n\tstruct regmap *regs;\n\tint mii_status_offset;\n\tbool ignore_read_errors;\n\tstruct regmap *phy_regs;\n\tconst struct mscc_miim_info *info;\n\tstruct clk *clk;\n\tu32 bus_freq;\n};\n\nstruct mscc_miim_info {\n\tunsigned int phy_reset_offset;\n\tunsigned int phy_reset_bits;\n};\n\nstruct msdos_dir_entry {\n\t__u8 name[11];\n\t__u8 attr;\n\t__u8 lcase;\n\t__u8 ctime_cs;\n\t__le16 ctime;\n\t__le16 cdate;\n\t__le16 adate;\n\t__le16 starthi;\n\t__le16 time;\n\t__le16 date;\n\t__le16 start;\n\t__le32 size;\n};\n\nstruct msdos_dir_slot {\n\t__u8 id;\n\t__u8 name0_4[10];\n\t__u8 attr;\n\t__u8 reserved;\n\t__u8 alias_checksum;\n\t__u8 name5_10[12];\n\t__le16 start;\n\t__u8 name11_12[4];\n};\n\nstruct msdos_inode_info {\n\tspinlock_t cache_lru_lock;\n\tstruct list_head cache_lru;\n\tint nr_caches;\n\tunsigned int cache_valid_id;\n\tlong: 32;\n\tloff_t mmu_private;\n\tint i_start;\n\tint i_logstart;\n\tint i_attrs;\n\tlong: 32;\n\tloff_t i_pos;\n\tstruct hlist_node i_fat_hash;\n\tstruct hlist_node i_dir_hash;\n\tstruct rw_semaphore truncate_lock;\n\tlong: 32;\n\tstruct timespec64 i_crtime;\n\tstruct inode vfs_inode;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct nls_table;\n\nstruct msdos_sb_info {\n\tshort unsigned int sec_per_clus;\n\tshort unsigned int cluster_bits;\n\tunsigned int cluster_size;\n\tunsigned char fats;\n\tunsigned char fat_bits;\n\tshort unsigned int fat_start;\n\tlong unsigned int fat_length;\n\tlong unsigned int dir_start;\n\tshort unsigned int dir_entries;\n\tlong unsigned int data_start;\n\tlong unsigned int max_cluster;\n\tlong unsigned int root_cluster;\n\tlong unsigned int fsinfo_sector;\n\tstruct mutex fat_lock;\n\tstruct mutex nfs_build_inode_lock;\n\tstruct mutex s_lock;\n\tunsigned int prev_free;\n\tunsigned int free_clusters;\n\tunsigned int free_clus_valid;\n\tstruct fat_mount_options options;\n\tstruct nls_table *nls_disk;\n\tstruct nls_table *nls_io;\n\tconst void *dir_ops;\n\tint dir_per_block;\n\tint dir_per_block_bits;\n\tunsigned int vol_id;\n\tint fatent_shift;\n\tconst struct fatent_operations *fatent_ops;\n\tstruct inode *fat_inode;\n\tstruct inode *fsinfo_inode;\n\tstruct ratelimit_state ratelimit;\n\tspinlock_t inode_hash_lock;\n\tstruct hlist_head inode_hashtable[256];\n\tspinlock_t dir_hash_lock;\n\tstruct hlist_head dir_hashtable[256];\n\tunsigned int dirty;\n\tstruct callback_head rcu;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n\tlong: 32;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong: 32;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n\tlong: 32;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tlong: 32;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong unsigned int msg_stime;\n\tlong unsigned int msg_stime_high;\n\tlong unsigned int msg_rtime;\n\tlong unsigned int msg_rtime_high;\n\tlong unsigned int msg_ctime;\n\tlong unsigned int msg_ctime_high;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct mtd_blktrans_ops;\n\nstruct mtd_blktrans_dev {\n\tstruct mtd_blktrans_ops *tr;\n\tstruct list_head list;\n\tstruct mtd_info *mtd;\n\tstruct mutex lock;\n\tint devnum;\n\tbool bg_stop;\n\tlong unsigned int size;\n\tint readonly;\n\tint open;\n\tstruct kref ref;\n\tstruct gendisk *disk;\n\tstruct attribute_group *disk_attributes;\n\tstruct request_queue *rq;\n\tstruct list_head rq_list;\n\tstruct blk_mq_tag_set *tag_set;\n\tspinlock_t queue_lock;\n\tvoid *priv;\n\tbool writable;\n};\n\nstruct mtd_blktrans_ops {\n\tchar *name;\n\tint major;\n\tint part_bits;\n\tint blksize;\n\tint blkshift;\n\tint (*readsect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*writesect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*discard)(struct mtd_blktrans_dev *, long unsigned int, unsigned int);\n\tvoid (*background)(struct mtd_blktrans_dev *);\n\tint (*getgeo)(struct mtd_blktrans_dev *, struct hd_geometry *);\n\tint (*flush)(struct mtd_blktrans_dev *);\n\tint (*open)(struct mtd_blktrans_dev *);\n\tvoid (*release)(struct mtd_blktrans_dev *);\n\tvoid (*add_mtd)(struct mtd_blktrans_ops *, struct mtd_info *);\n\tvoid (*remove_dev)(struct mtd_blktrans_dev *);\n\tstruct list_head devs;\n\tstruct list_head list;\n\tstruct module *owner;\n};\n\nstruct mtd_chip_driver {\n\tstruct mtd_info * (*probe)(struct map_info *);\n\tvoid (*destroy)(struct mtd_info *);\n\tstruct module *module;\n\tchar *name;\n\tstruct list_head list;\n};\n\nstruct mtd_concat {\n\tstruct mtd_info mtd;\n\tint num_subdev;\n\tstruct mtd_info **subdev;\n};\n\nstruct mtd_dev_param {\n\tchar name[64];\n\tint ubi_num;\n\tint vid_hdr_offs;\n\tint max_beb_per1024;\n\tint enable_fm;\n\tint need_resv_pool;\n};\n\nstruct mtd_erase_region_info {\n\tuint64_t offset;\n\tuint32_t erasesize;\n\tuint32_t numblocks;\n\tlong unsigned int *lockmap;\n\tlong: 32;\n};\n\nstruct mtd_file_info {\n\tstruct mtd_info *mtd;\n\tenum mtd_file_modes mode;\n};\n\nstruct mtd_info_user {\n\t__u8 type;\n\t__u32 flags;\n\t__u32 size;\n\t__u32 erasesize;\n\t__u32 writesize;\n\t__u32 oobsize;\n\t__u64 padding;\n};\n\nstruct mtd_notifier {\n\tvoid (*add)(struct mtd_info *);\n\tvoid (*remove)(struct mtd_info *);\n\tstruct list_head list;\n};\n\nstruct mtd_oob_buf {\n\t__u32 start;\n\t__u32 length;\n\tunsigned char *ptr;\n};\n\nstruct mtd_oob_buf64 {\n\t__u64 start;\n\t__u32 pad;\n\t__u32 length;\n\t__u64 usr_ptr;\n};\n\nstruct mtd_req_stats;\n\nstruct mtd_oob_ops {\n\tunsigned int mode;\n\tsize_t len;\n\tsize_t retlen;\n\tsize_t ooblen;\n\tsize_t oobretlen;\n\tuint32_t ooboffs;\n\tuint8_t *datbuf;\n\tuint8_t *oobbuf;\n\tstruct mtd_req_stats *stats;\n};\n\nstruct mtd_oob_region {\n\tu32 offset;\n\tu32 length;\n};\n\nstruct mtd_ooblayout_ops {\n\tint (*ecc)(struct mtd_info *, int, struct mtd_oob_region *);\n\tint (*free)(struct mtd_info *, int, struct mtd_oob_region *);\n};\n\nstruct mtd_pairing_info {\n\tint pair;\n\tint group;\n};\n\nstruct mtd_pairing_scheme {\n\tint ngroups;\n\tint (*get_info)(struct mtd_info *, int, struct mtd_pairing_info *);\n\tint (*get_wunit)(struct mtd_info *, const struct mtd_pairing_info *);\n};\n\nstruct mtd_part_parser_data;\n\nstruct mtd_part_parser {\n\tstruct list_head list;\n\tstruct module *owner;\n\tconst char *name;\n\tconst struct of_device_id *of_match_table;\n\tint (*parse_fn)(struct mtd_info *, const struct mtd_partition **, struct mtd_part_parser_data *);\n\tvoid (*cleanup)(const struct mtd_partition *, int);\n};\n\nstruct mtd_part_parser_data {\n\tlong unsigned int origin;\n};\n\nstruct mtd_partition {\n\tconst char *name;\n\tconst char * const *types;\n\tuint64_t size;\n\tuint64_t offset;\n\tuint32_t mask_flags;\n\tuint32_t add_flags;\n\tstruct device_node *of_node;\n\tlong: 32;\n};\n\nstruct mtd_partitions {\n\tconst struct mtd_partition *parts;\n\tint nr_parts;\n\tconst struct mtd_part_parser *parser;\n};\n\nstruct mtd_read_req_ecc_stats {\n\t__u32 uncorrectable_errors;\n\t__u32 corrected_bitflips;\n\t__u32 max_bitflips;\n};\n\nstruct mtd_read_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n\tstruct mtd_read_req_ecc_stats ecc_stats;\n\tlong: 32;\n};\n\nstruct mtd_req_stats {\n\tunsigned int uncorrectable_errors;\n\tunsigned int corrected_bitflips;\n\tunsigned int max_bitflips;\n};\n\nstruct mtd_write_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n};\n\nstruct mtdblk_dev {\n\tstruct mtd_blktrans_dev mbd;\n\tint count;\n\tstruct mutex cache_mutex;\n\tunsigned char *cache_data;\n\tlong unsigned int cache_offset;\n\tunsigned int cache_size;\n\tenum {\n\t\tSTATE_EMPTY = 0,\n\t\tSTATE_CLEAN = 1,\n\t\tSTATE_DIRTY = 2,\n\t} cache_state;\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct ww_acquire_ctx;\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[8];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[128];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct nand_bbt_descr {\n\tint options;\n\tint pages[8];\n\tint offs;\n\tint veroffs;\n\tuint8_t version[8];\n\tint len;\n\tint maxblocks;\n\tint reserved_block_code;\n\tuint8_t *pattern;\n};\n\nstruct nand_operation;\n\nstruct nand_controller_ops {\n\tint (*attach_chip)(struct nand_chip *);\n\tvoid (*detach_chip)(struct nand_chip *);\n\tint (*exec_op)(struct nand_chip *, const struct nand_operation *, bool);\n\tint (*setup_interface)(struct nand_chip *, int, const struct nand_interface_config *);\n};\n\nstruct nand_ecc_step_info;\n\nstruct nand_ecc_caps {\n\tconst struct nand_ecc_step_info *stepinfos;\n\tint nstepinfos;\n\tint (*calc_ecc_bytes)(int, int);\n};\n\nstruct nand_ecc_engine_ops;\n\nstruct nand_ecc_engine {\n\tstruct device *dev;\n\tstruct list_head node;\n\tconst struct nand_ecc_engine_ops *ops;\n\tenum nand_ecc_engine_integration integration;\n\tvoid *priv;\n};\n\nstruct nand_page_io_req;\n\nstruct nand_ecc_engine_ops {\n\tint (*init_ctx)(struct nand_device *);\n\tvoid (*cleanup_ctx)(struct nand_device *);\n\tint (*prepare_io_req)(struct nand_device *, struct nand_page_io_req *);\n\tint (*finish_io_req)(struct nand_device *, struct nand_page_io_req *);\n};\n\nstruct nand_pos {\n\tunsigned int target;\n\tunsigned int lun;\n\tunsigned int plane;\n\tunsigned int eraseblock;\n\tunsigned int page;\n};\n\nstruct nand_page_io_req {\n\tenum nand_page_io_req_type type;\n\tstruct nand_pos pos;\n\tunsigned int dataoffs;\n\tunsigned int datalen;\n\tunion {\n\t\tconst void *out;\n\t\tvoid *in;\n\t} databuf;\n\tunsigned int ooboffs;\n\tunsigned int ooblen;\n\tunion {\n\t\tconst void *out;\n\t\tvoid *in;\n\t} oobbuf;\n\tint mode;\n\tbool continuous;\n};\n\nstruct nand_ecc_req_tweak_ctx {\n\tstruct nand_page_io_req orig_req;\n\tstruct nand_device *nand;\n\tunsigned int page_buffer_size;\n\tunsigned int oob_buffer_size;\n\tvoid *spare_databuf;\n\tvoid *spare_oobbuf;\n\tbool bounce_data;\n\tbool bounce_oob;\n};\n\nstruct nand_ecc_step_info {\n\tint stepsize;\n\tconst int *strengths;\n\tint nstrengths;\n};\n\nstruct nand_ecc_sw_bch_conf {\n\tstruct nand_ecc_req_tweak_ctx req_ctx;\n\tunsigned int code_size;\n\tu8 *calc_buf;\n\tu8 *code_buf;\n\tstruct bch_control *bch;\n\tunsigned int *errloc;\n\tunsigned char *eccmask;\n};\n\nstruct nand_ecc_sw_hamming_conf {\n\tstruct nand_ecc_req_tweak_ctx req_ctx;\n\tunsigned int code_size;\n\tu8 *calc_buf;\n\tu8 *code_buf;\n\tunsigned int sm_order;\n};\n\nstruct nand_oobfree {\n\t__u32 offset;\n\t__u32 length;\n};\n\nstruct nand_ecclayout_user {\n\t__u32 eccbytes;\n\t__u32 eccpos[64];\n\t__u32 oobavail;\n\tstruct nand_oobfree oobfree[8];\n};\n\nstruct nand_flash_dev {\n\tchar *name;\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t mfr_id;\n\t\t\tuint8_t dev_id;\n\t\t};\n\t\tuint8_t id[8];\n\t};\n\tunsigned int pagesize;\n\tunsigned int chipsize;\n\tunsigned int erasesize;\n\tunsigned int options;\n\tuint16_t id_len;\n\tuint16_t oobsize;\n\tstruct {\n\t\tuint16_t strength_ds;\n\t\tuint16_t step_ds;\n\t} ecc;\n};\n\nstruct nand_sdr_timings {\n\tu64 tBERS_max;\n\tu32 tCCS_min;\n\tlong: 32;\n\tu64 tPROG_max;\n\tu64 tR_max;\n\tu32 tALH_min;\n\tu32 tADL_min;\n\tu32 tALS_min;\n\tu32 tAR_min;\n\tu32 tCEA_max;\n\tu32 tCEH_min;\n\tu32 tCH_min;\n\tu32 tCHZ_max;\n\tu32 tCLH_min;\n\tu32 tCLR_min;\n\tu32 tCLS_min;\n\tu32 tCOH_min;\n\tu32 tCS_min;\n\tu32 tDH_min;\n\tu32 tDS_min;\n\tu32 tFEAT_max;\n\tu32 tIR_min;\n\tu32 tITC_max;\n\tu32 tRC_min;\n\tu32 tREA_max;\n\tu32 tREH_min;\n\tu32 tRHOH_min;\n\tu32 tRHW_min;\n\tu32 tRHZ_max;\n\tu32 tRLOH_min;\n\tu32 tRP_min;\n\tu32 tRR_min;\n\tlong: 32;\n\tu64 tRST_max;\n\tu32 tWB_max;\n\tu32 tWC_min;\n\tu32 tWH_min;\n\tu32 tWHR_min;\n\tu32 tWP_min;\n\tu32 tWW_min;\n};\n\nstruct nand_nvddr_timings {\n\tu64 tBERS_max;\n\tu32 tCCS_min;\n\tlong: 32;\n\tu64 tPROG_max;\n\tu64 tR_max;\n\tu32 tAC_min;\n\tu32 tAC_max;\n\tu32 tADL_min;\n\tu32 tCAD_min;\n\tu32 tCAH_min;\n\tu32 tCALH_min;\n\tu32 tCALS_min;\n\tu32 tCAS_min;\n\tu32 tCEH_min;\n\tu32 tCH_min;\n\tu32 tCK_min;\n\tu32 tCS_min;\n\tu32 tDH_min;\n\tu32 tDQSCK_min;\n\tu32 tDQSCK_max;\n\tu32 tDQSD_min;\n\tu32 tDQSD_max;\n\tu32 tDQSHZ_max;\n\tu32 tDQSQ_max;\n\tu32 tDS_min;\n\tu32 tDSC_min;\n\tu32 tFEAT_max;\n\tu32 tITC_max;\n\tu32 tQHS_max;\n\tu32 tRHW_min;\n\tu32 tRR_min;\n\tu32 tRST_max;\n\tu32 tWB_max;\n\tu32 tWHR_min;\n\tu32 tWRCK_min;\n\tu32 tWW_min;\n\tlong: 32;\n};\n\nstruct nand_timings {\n\tunsigned int mode;\n\tlong: 32;\n\tunion {\n\t\tstruct nand_sdr_timings sdr;\n\t\tstruct nand_nvddr_timings nvddr;\n\t};\n};\n\nstruct nand_interface_config {\n\tenum nand_interface_type type;\n\tlong: 32;\n\tstruct nand_timings timings;\n};\n\nstruct nand_jedec_params {\n\tu8 sig[4];\n\t__le16 revision;\n\t__le16 features;\n\tu8 opt_cmd[3];\n\t__le16 sec_cmd;\n\tu8 num_of_param_pages;\n\tu8 reserved0[18];\n\tchar manufacturer[12];\n\tchar model[20];\n\tu8 jedec_id[6];\n\tu8 reserved1[10];\n\t__le32 byte_per_page;\n\t__le16 spare_bytes_per_page;\n\tu8 reserved2[6];\n\t__le32 pages_per_block;\n\t__le32 blocks_per_lun;\n\tu8 lun_count;\n\tu8 addr_cycles;\n\tu8 bits_per_cell;\n\tu8 programs_per_page;\n\tu8 multi_plane_addr;\n\tu8 multi_plane_op_attr;\n\tu8 reserved3[38];\n\t__le16 async_sdr_speed_grade;\n\t__le16 toggle_ddr_speed_grade;\n\t__le16 sync_ddr_speed_grade;\n\tu8 async_sdr_features;\n\tu8 toggle_ddr_features;\n\tu8 sync_ddr_features;\n\t__le16 t_prog;\n\t__le16 t_bers;\n\t__le16 t_r;\n\t__le16 t_r_multi_plane;\n\t__le16 t_ccs;\n\t__le16 io_pin_capacitance_typ;\n\t__le16 input_pin_capacitance_typ;\n\t__le16 clk_pin_capacitance_typ;\n\tu8 driver_strength_support;\n\t__le16 t_adl;\n\tu8 reserved4[36];\n\tu8 guaranteed_good_blocks;\n\t__le16 guaranteed_block_endurance;\n\tstruct jedec_ecc_info ecc_info[4];\n\tu8 reserved5[29];\n\tu8 reserved6[148];\n\t__le16 vendor_rev_num;\n\tu8 reserved7[88];\n\t__le16 crc;\n} __attribute__((packed));\n\nstruct nand_manufacturer_ops;\n\nstruct nand_manufacturer_desc {\n\tint id;\n\tchar *name;\n\tconst struct nand_manufacturer_ops *ops;\n};\n\nstruct nand_onfi_params;\n\nstruct nand_manufacturer_ops {\n\tvoid (*detect)(struct nand_chip *);\n\tint (*init)(struct nand_chip *);\n\tvoid (*cleanup)(struct nand_chip *);\n\tvoid (*fixup_onfi_param_page)(struct nand_chip *, struct nand_onfi_params *);\n};\n\nstruct nand_onfi_params {\n\tu8 sig[4];\n\t__le16 revision;\n\t__le16 features;\n\t__le16 opt_cmd;\n\tu8 reserved0[2];\n\t__le16 ext_param_page_length;\n\tu8 num_of_param_pages;\n\tu8 reserved1[17];\n\tchar manufacturer[12];\n\tchar model[20];\n\tu8 jedec_id;\n\t__le16 date_code;\n\tu8 reserved2[13];\n\t__le32 byte_per_page;\n\t__le16 spare_bytes_per_page;\n\t__le32 data_bytes_per_ppage;\n\t__le16 spare_bytes_per_ppage;\n\t__le32 pages_per_block;\n\t__le32 blocks_per_lun;\n\tu8 lun_count;\n\tu8 addr_cycles;\n\tu8 bits_per_cell;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 guaranteed_good_blocks;\n\t__le16 guaranteed_block_endurance;\n\tu8 programs_per_page;\n\tu8 ppage_attr;\n\tu8 ecc_bits;\n\tu8 interleaved_bits;\n\tu8 interleaved_ops;\n\tu8 reserved3[13];\n\tu8 io_pin_capacitance_max;\n\t__le16 sdr_timing_modes;\n\t__le16 program_cache_timing_mode;\n\t__le16 t_prog;\n\t__le16 t_bers;\n\t__le16 t_r;\n\t__le16 t_ccs;\n\tu8 nvddr_timing_modes;\n\tu8 nvddr2_timing_modes;\n\tu8 nvddr_nvddr2_features;\n\t__le16 clk_pin_capacitance_typ;\n\t__le16 io_pin_capacitance_typ;\n\t__le16 input_pin_capacitance_typ;\n\tu8 input_pin_capacitance_max;\n\tu8 driver_strength_support;\n\t__le16 t_int_r;\n\t__le16 t_adl;\n\tu8 reserved4[8];\n\t__le16 vendor_revision;\n\tu8 vendor[88];\n\t__le16 crc;\n} __attribute__((packed));\n\nstruct nand_onfi_vendor_macronix {\n\tu8 reserved;\n\tu8 reliability_func;\n};\n\nstruct nand_onfi_vendor_micron {\n\tu8 two_plane_read;\n\tu8 read_cache;\n\tu8 read_unique_id;\n\tu8 dq_imped;\n\tu8 dq_imped_num_settings;\n\tu8 dq_imped_feat_addr;\n\tu8 rb_pulldown_strength;\n\tu8 rb_pulldown_strength_feat_addr;\n\tu8 rb_pulldown_strength_num_settings;\n\tu8 otp_mode;\n\tu8 otp_page_start;\n\tu8 otp_data_prot_addr;\n\tu8 otp_num_pages;\n\tu8 otp_feat_addr;\n\tu8 read_retry_options;\n\tu8 reserved[72];\n\tu8 param_revision;\n};\n\nstruct nand_oobinfo {\n\t__u32 useecc;\n\t__u32 eccbytes;\n\t__u32 oobfree[16];\n\t__u32 eccpos[32];\n};\n\nstruct nand_op_addr_instr {\n\tunsigned int naddrs;\n\tconst u8 *addrs;\n};\n\nstruct nand_op_cmd_instr {\n\tu8 opcode;\n};\n\nstruct nand_op_data_instr {\n\tunsigned int len;\n\tunion {\n\t\tvoid *in;\n\t\tconst void *out;\n\t} buf;\n\tbool force_8bit;\n};\n\nstruct nand_op_waitrdy_instr {\n\tunsigned int timeout_ms;\n};\n\nstruct nand_op_instr {\n\tenum nand_op_instr_type type;\n\tunion {\n\t\tstruct nand_op_cmd_instr cmd;\n\t\tstruct nand_op_addr_instr addr;\n\t\tstruct nand_op_data_instr data;\n\t\tstruct nand_op_waitrdy_instr waitrdy;\n\t} ctx;\n\tunsigned int delay_ns;\n};\n\nstruct nand_op_parser_pattern;\n\nstruct nand_op_parser {\n\tconst struct nand_op_parser_pattern *patterns;\n\tunsigned int npatterns;\n};\n\nstruct nand_op_parser_addr_constraints {\n\tunsigned int maxcycles;\n};\n\nstruct nand_subop {\n\tunsigned int cs;\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n\tunsigned int first_instr_start_off;\n\tunsigned int last_instr_end_off;\n};\n\nstruct nand_op_parser_ctx {\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n\tstruct nand_subop subop;\n};\n\nstruct nand_op_parser_data_constraints {\n\tunsigned int maxlen;\n};\n\nstruct nand_op_parser_pattern_elem;\n\nstruct nand_op_parser_pattern {\n\tconst struct nand_op_parser_pattern_elem *elems;\n\tunsigned int nelems;\n\tint (*exec)(struct nand_chip *, const struct nand_subop *);\n};\n\nstruct nand_op_parser_pattern_elem {\n\tenum nand_op_instr_type type;\n\tbool optional;\n\tunion {\n\t\tstruct nand_op_parser_addr_constraints addr;\n\t\tstruct nand_op_parser_data_constraints data;\n\t} ctx;\n};\n\nstruct nand_operation {\n\tunsigned int cs;\n\tbool deassert_wp;\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n};\n\nstruct nand_ops {\n\tint (*erase)(struct nand_device *, const struct nand_pos *);\n\tint (*markbad)(struct nand_device *, const struct nand_pos *);\n\tbool (*isbad)(struct nand_device *, const struct nand_pos *);\n};\n\nstruct nand_secure_region {\n\tu64 offset;\n\tu64 size;\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u16 offset;\n\t__u16 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n\tlong: 32;\n};\n\nstruct nd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\t__u8 opt[0];\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct nduseroptmsg {\n\tunsigned char nduseropt_family;\n\tunsigned char nduseropt_pad1;\n\tshort unsigned int nduseropt_opts_len;\n\tint nduseropt_ifindex;\n\t__u8 nduseropt_icmp_type;\n\t__u8 nduseropt_icmp_code;\n\tshort unsigned int nduseropt_pad2;\n\tunsigned int nduseropt_pad3;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tlong: 32;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct ref_tracker_dir {};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct udp_mib *udplite_statistics;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tlong: 32;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tu32 multipath_hash_fields;\n\tu8 multipath_hash_policy;\n\t__u8 __cacheline_group_begin__sysctl_ipv6_flowlabel[0];\n\tu8 flowlabel_consistency;\n\tu8 auto_flowlabels;\n\tu8 flowlabel_state_ranges;\n\t__u8 __cacheline_group_end__sysctl_ipv6_flowlabel[0];\n\tu8 icmpv6_echo_ignore_all;\n\tu8 icmpv6_echo_ignore_multicast;\n\tu8 icmpv6_echo_ignore_anycast;\n\tint icmpv6_time;\n\tlong unsigned int icmpv6_ratemask[8];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tu8 anycast_src_echo_reply;\n\tu8 bindv6only;\n\tu8 ip_nonlocal_bind;\n\tu8 fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tu32 ioam6_id;\n\tu64 ioam6_id_wide;\n\tu8 skip_notify_on_dev_down;\n\tu8 fib_notify_on_flag_change;\n\tu8 icmpv6_error_anycast_as_unicast;\n\tu8 icmpv6_errors_extension_mask;\n\tlong: 32;\n};\n\nstruct rt6_statistics;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct dst_ops ip6_dst_ops;\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tspinlock_t fib_table_hash_lock;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tatomic_t ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned char flowlabel_has_excl;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct hlist_head *inet6_addr_lst;\n\tspinlock_t addrconf_hash_lock;\n\tstruct delayed_work addr_chk_work;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tstruct ioam6_pernet_data *ioam6_data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct nf_logger;\n\nstruct nf_hook_entries;\n\nstruct netns_nf {\n\tstruct proc_dir_entry *proc_netfilter;\n\tconst struct nf_logger *nf_loggers[11];\n\tstruct ctl_table_header *nf_log_dir_header;\n\tstruct nf_hook_entries *hooks_ipv4[5];\n\tstruct nf_hook_entries *hooks_ipv6[5];\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct netns_nf nf;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tu64 net_cookie;\n\tstruct sock *diag_nlsk;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct net_bridge_vlan;\n\nstruct net_bridge_mcast {\n\tstruct net_bridge *br;\n\tstruct net_bridge_vlan *vlan;\n\tu32 multicast_last_member_count;\n\tu32 multicast_startup_query_count;\n\tu8 multicast_querier;\n\tu8 multicast_igmp_version;\n\tu8 multicast_router;\n\tu8 multicast_mld_version;\n\tlong unsigned int multicast_last_member_interval;\n\tlong unsigned int multicast_membership_interval;\n\tlong unsigned int multicast_querier_interval;\n\tlong unsigned int multicast_query_interval;\n\tlong unsigned int multicast_query_response_interval;\n\tlong unsigned int multicast_startup_query_interval;\n\tstruct hlist_head ip4_mc_router_list;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct bridge_mcast_other_query ip4_other_query;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct bridge_mcast_querier ip4_querier;\n\tstruct hlist_head ip6_mc_router_list;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct bridge_mcast_other_query ip6_other_query;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct bridge_mcast_querier ip6_querier;\n};\n\nstruct net_bridge {\n\tspinlock_t lock;\n\tspinlock_t hash_lock;\n\tstruct hlist_head frame_type_list;\n\tstruct net_device *dev;\n\tlong unsigned int options;\n\tstruct rhashtable fdb_hash_tbl;\n\tstruct list_head port_list;\n\tu16 group_fwd_mask;\n\tu16 group_fwd_mask_required;\n\tbridge_id designated_root;\n\tbridge_id bridge_id;\n\tunsigned char topology_change;\n\tunsigned char topology_change_detected;\n\tu16 root_port;\n\tlong unsigned int max_age;\n\tlong unsigned int hello_time;\n\tlong unsigned int forward_delay;\n\tlong unsigned int ageing_time;\n\tlong unsigned int bridge_max_age;\n\tlong unsigned int bridge_hello_time;\n\tlong unsigned int bridge_forward_delay;\n\tlong unsigned int bridge_ageing_time;\n\tu32 root_path_cost;\n\tu8 group_addr[6];\n\tenum {\n\t\tBR_NO_STP = 0,\n\t\tBR_KERNEL_STP = 1,\n\t\tBR_USER_STP = 2,\n\t} stp_enabled;\n\tstruct net_bridge_mcast multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 hash_max;\n\tspinlock_t multicast_lock;\n\tstruct rhashtable mdb_hash_tbl;\n\tstruct rhashtable sg_port_tbl;\n\tstruct hlist_head mcast_gc_list;\n\tstruct hlist_head mdb_list;\n\tstruct work_struct mcast_gc_work;\n\tstruct timer_list hello_timer;\n\tstruct timer_list tcn_timer;\n\tstruct timer_list topology_change_timer;\n\tstruct delayed_work gc_work;\n\tstruct kobject *ifobj;\n\tu32 auto_cnt;\n\tatomic_t fdb_n_learned;\n\tu32 fdb_max_learned;\n\tint last_hwdom;\n\tlong unsigned int busy_hwdoms;\n\tstruct hlist_head fdb_list;\n};\n\nunion net_bridge_eht_addr {\n\t__be32 ip4;\n\tstruct in6_addr ip6;\n};\n\nstruct net_bridge_fdb_key {\n\tmac_addr addr;\n\tu16 vlan_id;\n};\n\nstruct net_bridge_fdb_entry {\n\tstruct rhash_head rhnode;\n\tstruct net_bridge_port *dst;\n\tstruct net_bridge_fdb_key key;\n\tstruct hlist_node fdb_node;\n\tlong unsigned int flags;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct net_bridge_fdb_flush_desc {\n\tlong unsigned int flags;\n\tlong unsigned int flags_mask;\n\tint port_ifindex;\n\tu16 vlan_id;\n};\n\nstruct net_bridge_port_group;\n\nstruct net_bridge_group_eht_host {\n\tstruct rb_node rb_node;\n\tunion net_bridge_eht_addr h_addr;\n\tstruct hlist_head set_entries;\n\tunsigned int num_entries;\n\tunsigned char filter_mode;\n\tstruct net_bridge_port_group *pg;\n};\n\nstruct net_bridge_mcast_gc {\n\tstruct hlist_node gc_node;\n\tvoid (*destroy)(struct net_bridge_mcast_gc *);\n};\n\nstruct net_bridge_group_eht_set {\n\tstruct rb_node rb_node;\n\tunion net_bridge_eht_addr src_addr;\n\tstruct rb_root entry_tree;\n\tstruct timer_list timer;\n\tstruct net_bridge_port_group *pg;\n\tstruct net_bridge *br;\n\tstruct net_bridge_mcast_gc mcast_gc;\n};\n\nstruct net_bridge_group_eht_set_entry {\n\tstruct rb_node rb_node;\n\tstruct hlist_node host_list;\n\tunion net_bridge_eht_addr h_addr;\n\tstruct timer_list timer;\n\tstruct net_bridge *br;\n\tstruct net_bridge_group_eht_set *eht_set;\n\tstruct net_bridge_group_eht_host *h_parent;\n\tstruct net_bridge_mcast_gc mcast_gc;\n};\n\nstruct net_bridge_group_src {\n\tstruct hlist_node node;\n\tstruct br_ip addr;\n\tstruct net_bridge_port_group *pg;\n\tu8 flags;\n\tu8 src_query_rexmit_cnt;\n\tstruct timer_list timer;\n\tstruct net_bridge *br;\n\tstruct net_bridge_mcast_gc mcast_gc;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_mcast_port {\n\tstruct net_bridge_port *port;\n\tstruct net_bridge_vlan *vlan;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct hlist_node ip4_rlist;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct hlist_node ip6_rlist;\n\tunsigned char multicast_router;\n\tu32 mdb_n_entries;\n\tu32 mdb_max_entries;\n};\n\nstruct net_bridge_mdb_entry {\n\tstruct rhash_head rhnode;\n\tstruct net_bridge *br;\n\tstruct net_bridge_port_group *ports;\n\tstruct br_ip addr;\n\tbool host_joined;\n\tstruct timer_list timer;\n\tstruct hlist_node mdb_node;\n\tstruct net_bridge_mcast_gc mcast_gc;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_port {\n\tstruct net_bridge *br;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tstruct net_bridge_port *backup_port;\n\tu32 backup_nhid;\n\tu8 priority;\n\tu8 state;\n\tu16 port_no;\n\tunsigned char topology_change_ack;\n\tunsigned char config_pending;\n\tport_id port_id;\n\tport_id designated_port;\n\tbridge_id designated_root;\n\tbridge_id designated_bridge;\n\tu32 path_cost;\n\tu32 designated_cost;\n\tlong unsigned int designated_age;\n\tstruct timer_list forward_delay_timer;\n\tstruct timer_list hold_timer;\n\tstruct timer_list message_age_timer;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n\tstruct net_bridge_mcast_port multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 multicast_eht_hosts_limit;\n\tu32 multicast_eht_hosts_cnt;\n\tstruct hlist_head mglist;\n\tchar sysfs_name[16];\n\tint hwdom;\n\tint offload_count;\n\tstruct netdev_phys_item_id ppid;\n\tu16 group_fwd_mask;\n\tu16 backup_redirected_cnt;\n\tstruct bridge_stp_xstats stp_xstats;\n};\n\nstruct net_bridge_port_group_sg_key {\n\tstruct net_bridge_port *port;\n\tstruct br_ip addr;\n};\n\nstruct net_bridge_port_group {\n\tstruct net_bridge_port_group *next;\n\tstruct net_bridge_port_group_sg_key key;\n\tunsigned char eth_addr[6];\n\tunsigned char flags;\n\tunsigned char filter_mode;\n\tunsigned char grp_query_rexmit_cnt;\n\tunsigned char rt_protocol;\n\tstruct hlist_head src_list;\n\tunsigned int src_ents;\n\tstruct timer_list timer;\n\tstruct timer_list rexmit_timer;\n\tstruct hlist_node mglist;\n\tstruct rb_root eht_set_tree;\n\tstruct rb_root eht_host_tree;\n\tstruct rhash_head rhnode;\n\tstruct net_bridge_mcast_gc mcast_gc;\n\tstruct callback_head rcu;\n};\n\nstruct pcpu_sw_netstats;\n\nstruct net_bridge_vlan {\n\tstruct rhash_head vnode;\n\tstruct rhash_head tnode;\n\tu16 vid;\n\tu16 flags;\n\tu16 priv_flags;\n\tu8 state;\n\tstruct pcpu_sw_netstats *stats;\n\tunion {\n\t\tstruct net_bridge *br;\n\t\tstruct net_bridge_port *port;\n\t};\n\tunion {\n\t\trefcount_t refcnt;\n\t\tstruct net_bridge_vlan *brvlan;\n\t};\n\tlong: 32;\n\tstruct br_tunnel_info tinfo;\n\tunion {\n\t\tstruct net_bridge_mcast br_mcast_ctx;\n\t\tstruct net_bridge_mcast_port port_mcast_ctx;\n\t};\n\tu16 msti;\n\tstruct list_head vlist;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_vlan_group {\n\tstruct rhashtable vlan_hash;\n\tstruct rhashtable tunnel_hash;\n\tstruct list_head vlan_list;\n\tu16 num_vlans;\n\tu16 pvid;\n\tu8 pvid_state;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_dstats;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct xdp_dev_bulk_queue;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct phy_link_topology;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tlong: 32;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct nf_hook_entries *nf_hooks_egress;\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tstruct dsa_port *dsa_ptr;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tstruct nf_hook_entries *nf_hooks_ingress;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tlong: 32;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct netdev_bpf;\n\nstruct xdp_frame;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct net_failover_info {\n\tstruct net_device *primary_dev;\n\tstruct net_device *standby_dev;\n\tstruct rtnl_link_stats64 primary_stats;\n\tstruct rtnl_link_stats64 standby_stats;\n\tstruct rtnl_link_stats64 failover_stats;\n\tspinlock_t stats_lock;\n\tlong: 32;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct inet6_protocol tcpv6_protocol;\n\tstruct inet6_protocol udpv6_protocol;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_local {\n\tstruct net_device *ndev;\n\tbool tx_ping_pong;\n\tbool rx_ping_pong;\n\tu32 next_tx_buf_to_use;\n\tu32 next_rx_buf_to_use;\n\tvoid *base_addr;\n\tspinlock_t reset_lock;\n\tstruct sk_buff *deferred_skb;\n\tstruct phy_device *phy_dev;\n\tstruct device_node *phy_node;\n\tstruct mii_bus *mii_bus;\n\tint last_link;\n};\n\nstruct net_packet_attrs {\n\tconst unsigned char *src;\n\tconst unsigned char *dst;\n\tu32 ip_src;\n\tu32 ip_dst;\n\tbool tcp;\n\tu16 sport;\n\tu16 dport;\n\tint timeout;\n\tint size;\n\tint max_size;\n\tu8 id;\n\tu16 queue_mapping;\n\tbool bad_csum;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct net_test {\n\tchar name[32];\n\tint (*fn)(struct net_device *);\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct net_test_priv {\n\tstruct net_packet_attrs *packet;\n\tstruct packet_type pt;\n\tstruct completion comp;\n\tint double_vlan;\n\tint vlan_id;\n\tint ok;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct xsk_buff_pool;\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_lag_lower_state_info {\n\tu8 link_up: 1;\n\tu8 tx_enabled: 1;\n};\n\nstruct netdev_lag_upper_info {\n\tenum netdev_lag_tx_type tx_type;\n\tenum netdev_lag_hash hash_type;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n\tlong: 32;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n};\n\nstruct netevent_redirect {\n\tstruct dst_entry *old;\n\tstruct dst_entry *new;\n\tstruct neighbour *neigh;\n\tconst void *daddr;\n};\n\ntypedef void (*netfs_io_terminated_t)(void *, ssize_t);\n\nstruct netfs_io_subrequest;\n\nstruct netfs_cache_ops {\n\tvoid (*end_operation)(struct netfs_cache_resources *);\n\tint (*read)(struct netfs_cache_resources *, loff_t, struct iov_iter *, enum netfs_read_from_hole, netfs_io_terminated_t, void *);\n\tint (*write)(struct netfs_cache_resources *, loff_t, struct iov_iter *, netfs_io_terminated_t, void *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_cache_resources *, long long unsigned int *, long long unsigned int *, long long unsigned int);\n\tenum netfs_io_source (*prepare_read)(struct netfs_io_subrequest *, long long unsigned int);\n\tvoid (*prepare_write_subreq)(struct netfs_io_subrequest *);\n\tint (*prepare_write)(struct netfs_cache_resources *, loff_t *, size_t *, size_t, loff_t, bool);\n\tenum netfs_io_source (*prepare_ondemand_read)(struct netfs_cache_resources *, loff_t, size_t *, loff_t, long unsigned int *, ino_t);\n\tint (*query_occupancy)(struct netfs_cache_resources *, loff_t, size_t, size_t, loff_t *, size_t *);\n};\n\nstruct netfs_cache_resources {\n\tconst struct netfs_cache_ops *ops;\n\tvoid *cache_priv;\n\tvoid *cache_priv2;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n};\n\nstruct netfs_group;\n\nstruct netfs_folio {\n\tstruct netfs_group *netfs_group;\n\tunsigned int dirty_offset;\n\tunsigned int dirty_len;\n};\n\nstruct netfs_group {\n\trefcount_t ref;\n\tvoid (*free)(struct netfs_group *);\n};\n\nstruct netfs_request_ops;\n\nstruct netfs_inode {\n\tstruct inode inode;\n\tconst struct netfs_request_ops *ops;\n\tstruct mutex wb_lock;\n\tlong: 32;\n\tloff_t remote_i_size;\n\tloff_t zero_point;\n\tatomic_t io_count;\n\tlong unsigned int flags;\n};\n\nstruct netfs_io_stream {\n\tstruct netfs_io_subrequest *construct;\n\tsize_t sreq_max_len;\n\tunsigned int sreq_max_segs;\n\tunsigned int submit_off;\n\tunsigned int submit_len;\n\tunsigned int submit_extendable_to;\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tstruct list_head subrequests;\n\tstruct netfs_io_subrequest *front;\n\tlong: 32;\n\tlong long unsigned int collected_to;\n\tsize_t transferred;\n\tshort unsigned int error;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tbool avail;\n\tbool active;\n\tbool need_retry;\n\tbool failed;\n\tbool transferred_valid;\n};\n\nstruct rolling_buffer {\n\tstruct folio_queue *head;\n\tstruct folio_queue *tail;\n\tstruct iov_iter iter;\n\tu8 next_head_slot;\n\tu8 first_tail_slot;\n\tlong: 32;\n};\n\nstruct netfs_io_request {\n\tunion {\n\t\tstruct work_struct cleanup_work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct work_struct work;\n\tstruct inode *inode;\n\tstruct address_space *mapping;\n\tstruct kiocb *iocb;\n\tstruct netfs_cache_resources cache_resources;\n\tstruct netfs_io_request *copy_to_cache;\n\tstruct list_head proc_link;\n\tlong: 32;\n\tstruct netfs_io_stream io_streams[2];\n\tstruct netfs_group *group;\n\tlong: 32;\n\tstruct rolling_buffer buffer;\n\twait_queue_head_t waitq;\n\tvoid *netfs_priv;\n\tvoid *netfs_priv2;\n\tstruct bio_vec *direct_bv;\n\tlong long unsigned int submitted;\n\tlong long unsigned int len;\n\tsize_t transferred;\n\tlong int error;\n\tlong long unsigned int i_size;\n\tlong long unsigned int start;\n\tatomic64_t issued_to;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int abandon_to;\n\tlong unsigned int no_unlock_folio;\n\tunsigned int direct_bv_count;\n\tunsigned int debug_id;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tatomic_t subreq_counter;\n\tunsigned int nr_group_rel;\n\tspinlock_t lock;\n\tunsigned char front_folio_order;\n\tenum netfs_io_origin origin;\n\tbool direct_bv_unpin;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tconst struct netfs_request_ops *netfs_ops;\n};\n\nstruct netfs_io_subrequest {\n\tstruct netfs_io_request *rreq;\n\tstruct work_struct work;\n\tstruct list_head rreq_link;\n\tlong: 32;\n\tstruct iov_iter io_iter;\n\tlong long unsigned int start;\n\tsize_t len;\n\tsize_t transferred;\n\trefcount_t ref;\n\tshort int error;\n\tshort unsigned int debug_index;\n\tunsigned int nr_segs;\n\tu8 retry_count;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tlong unsigned int flags;\n\tlong: 32;\n};\n\nstruct netfs_request_ops {\n\tmempool_t *request_pool;\n\tmempool_t *subrequest_pool;\n\tint (*init_request)(struct netfs_io_request *, struct file *);\n\tvoid (*free_request)(struct netfs_io_request *);\n\tvoid (*free_subrequest)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_io_request *);\n\tint (*prepare_read)(struct netfs_io_subrequest *);\n\tvoid (*issue_read)(struct netfs_io_subrequest *);\n\tbool (*is_still_valid)(struct netfs_io_request *);\n\tint (*check_write_begin)(struct file *, loff_t, unsigned int, struct folio **, void **);\n\tvoid (*done)(struct netfs_io_request *);\n\tvoid (*update_i_size)(struct inode *, loff_t);\n\tvoid (*post_modify)(struct inode *);\n\tvoid (*begin_writeback)(struct netfs_io_request *);\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*retry_request)(struct netfs_io_request *, struct netfs_io_stream *);\n\tvoid (*invalidate_cache)(struct netfs_io_request *);\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netsfhdr {\n\t__be32 version;\n\t__be64 magic;\n\tu8 id;\n} __attribute__((packed));\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_br_ops {\n\tint (*br_dev_xmit_hook)(struct sk_buff *);\n};\n\nstruct nf_conntrack;\n\nstruct nf_conntrack_tuple;\n\nstruct nf_ct_hook {\n\tint (*update)(struct net *, struct sk_buff *);\n\tvoid (*destroy)(struct nf_conntrack *);\n\tbool (*get_tuple_skb)(struct nf_conntrack_tuple *, const struct sk_buff *);\n\tvoid (*attach)(struct sk_buff *, const struct sk_buff *);\n\tvoid (*set_closing)(struct nf_conntrack *);\n\tint (*confirm)(struct sk_buff *);\n\tu32 (*get_id)(const struct nf_conntrack *);\n};\n\nstruct nf_defrag_hook {\n\tstruct module *owner;\n\tint (*enable)(struct net *);\n\tvoid (*disable)(struct net *);\n};\n\nstruct nf_hook_entry {\n\tnf_hookfn *hook;\n\tvoid *priv;\n};\n\nstruct nf_hook_entries {\n\tu16 num_hook_entries;\n\tstruct nf_hook_entry hooks[0];\n};\n\nstruct nf_hook_entries_rcu_head {\n\tstruct callback_head head;\n\tvoid *allocation;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nf_queue_entry;\n\nstruct nf_ipv6_ops {\n\tvoid (*route_input)(struct sk_buff *);\n\tint (*fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tint (*reroute)(struct sk_buff *, const struct nf_queue_entry *);\n};\n\nstruct nf_log_buf {\n\tunsigned int count;\n\tchar buf[1020];\n};\n\nstruct nf_loginfo;\n\ntypedef void nf_logfn(struct net *, u_int8_t, unsigned int, const struct sk_buff *, const struct net_device *, const struct net_device *, const struct nf_loginfo *, const char *);\n\nstruct nf_logger {\n\tchar *name;\n\tenum nf_log_type type;\n\tnf_logfn *logfn;\n\tstruct module *me;\n};\n\nstruct nf_loginfo {\n\tu_int8_t type;\n\tunion {\n\t\tstruct {\n\t\t\tu_int32_t copy_len;\n\t\t\tu_int16_t group;\n\t\t\tu_int16_t qthreshold;\n\t\t\tu_int16_t flags;\n\t\t} ulog;\n\t\tstruct {\n\t\t\tu_int8_t level;\n\t\t\tu_int8_t logflags;\n\t\t} log;\n\t} u;\n};\n\nstruct nf_queue_entry {\n\tstruct list_head list;\n\tstruct rhash_head hash_node;\n\tstruct sk_buff *skb;\n\tunsigned int id;\n\tunsigned int hook_index;\n\tstruct nf_hook_state state;\n\tbool nf_ct_is_unconfirmed;\n\tu16 size;\n\tu16 queue_num;\n};\n\nstruct nf_queue_handler {\n\tint (*outfn)(struct nf_queue_entry *, unsigned int);\n\tvoid (*nf_hook_drop)(struct net *);\n};\n\nstruct nf_sockopt_ops {\n\tstruct list_head list;\n\tu_int8_t pf;\n\tint set_optmin;\n\tint set_optmax;\n\tint (*set)(struct sock *, int, sockptr_t, unsigned int);\n\tint get_optmin;\n\tint get_optmax;\n\tint (*get)(struct sock *, int, void *, int *);\n\tstruct module *owner;\n};\n\nstruct nf_conn;\n\nstruct nfnl_ct_hook {\n\tsize_t (*build_size)(const struct nf_conn *);\n\tint (*build)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, u_int16_t, u_int16_t);\n\tint (*parse)(const struct nlattr *, struct nf_conn *);\n\tint (*attach_expect)(const struct nlattr *, struct nf_conn *, u32, u32);\n\tvoid (*seq_adjust)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, s32);\n};\n\nstruct nfs2_fh {\n\tchar data[32];\n};\n\nstruct nfs3_accessargs {\n\tstruct nfs_fh *fh;\n\t__u32 access;\n};\n\nstruct nfs_fattr;\n\nstruct nfs3_accessres {\n\tstruct nfs_fattr *fattr;\n\t__u32 access;\n};\n\nstruct nfs3_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n\tenum nfs3_createmode createmode;\n\t__be32 verifier[2];\n};\n\nstruct rpc_procinfo;\n\nstruct rpc_message {\n\tconst struct rpc_procinfo *rpc_proc;\n\tvoid *rpc_argp;\n\tvoid *rpc_resp;\n\tconst struct cred *rpc_cred;\n};\n\nstruct nfs3_mkdirargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_mknodargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tenum nfs3_ftype type;\n\tstruct iattr *sattr;\n\tdev_t rdev;\n};\n\nstruct nfs3_diropres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs4_string;\n\nstruct nfs4_threshold;\n\nstruct nfs4_label;\n\nstruct nfs_fattr {\n\t__u64 valid;\n\tumode_t mode;\n\t__u32 nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tlong: 32;\n\t__u64 size;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 blocksize;\n\t\t\t__u32 blocks;\n\t\t} nfs2;\n\t\tstruct {\n\t\t\t__u64 used;\n\t\t} nfs3;\n\t} du;\n\tstruct nfs_fsid fsid;\n\t__u64 fileid;\n\t__u64 mounted_on_fileid;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\t__u64 change_attr;\n\t__u64 pre_change_attr;\n\t__u64 pre_size;\n\tstruct timespec64 pre_mtime;\n\tstruct timespec64 pre_ctime;\n\tlong unsigned int time_start;\n\tlong unsigned int gencount;\n\tstruct nfs4_string *owner_name;\n\tstruct nfs4_string *group_name;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs3_createdata {\n\tstruct rpc_message msg;\n\tunion {\n\t\tstruct nfs3_createargs create;\n\t\tstruct nfs3_mkdirargs mkdir;\n\t\tstruct nfs3_symlinkargs symlink;\n\t\tstruct nfs3_mknodargs mknod;\n\t} arg;\n\tstruct nfs3_diropres res;\n\tstruct nfs_fh fh;\n\tlong: 32;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_fattr dir_attr;\n};\n\nstruct nfs3_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs3_fh {\n\tshort unsigned int size;\n\tunsigned char data[64];\n};\n\nstruct nfs3_getaclargs {\n\tstruct nfs_fh *fh;\n\tint mask;\n\tstruct page **pages;\n};\n\nstruct nfs3_getaclres {\n\tstruct nfs_fattr *fattr;\n\tint mask;\n\tunsigned int acl_access_count;\n\tunsigned int acl_default_count;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n};\n\nstruct nfs3_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs3_linkres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_readdirargs {\n\tstruct nfs_fh *fh;\n\tlong: 32;\n\t__u64 cookie;\n\t__be32 verf[2];\n\tbool plus;\n\tunsigned int count;\n\tstruct page **pages;\n\tlong: 32;\n};\n\nstruct nfs3_readdirres {\n\tstruct nfs_fattr *dir_attr;\n\t__be32 *verf;\n\tbool plus;\n};\n\nstruct nfs3_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs3_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n\tunsigned int guard;\n\tlong: 32;\n\tstruct timespec64 guardtime;\n};\n\nstruct nfs3_setaclargs {\n\tstruct inode *inode;\n\tint mask;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n\tsize_t len;\n\tunsigned int npages;\n\tstruct page **pages;\n};\n\nstruct nfs41_bind_conn_to_session_args {\n\tstruct nfs_client *client;\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n\tint retries;\n};\n\nstruct nfs41_bind_conn_to_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n};\n\nstruct nfs4_channel_attrs {\n\tu32 max_rqst_sz;\n\tu32 max_resp_sz;\n\tu32 max_resp_sz_cached;\n\tu32 max_ops;\n\tu32 max_reqs;\n};\n\nstruct nfs41_create_session_args {\n\tstruct nfs_client *client;\n\tlong: 32;\n\tu64 clientid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tuint32_t cb_program;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tlong: 32;\n};\n\nstruct nfs41_create_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs4_op_map {\n\tunion {\n\t\tlong unsigned int longs[3];\n\t\tu32 words[3];\n\t} u;\n};\n\nstruct nfs41_state_protection {\n\tu32 how;\n\tstruct nfs4_op_map enforce;\n\tstruct nfs4_op_map allow;\n};\n\nstruct nfs41_exchange_id_args {\n\tstruct nfs_client *client;\n\tnfs4_verifier verifier;\n\tu32 flags;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_server_owner;\n\nstruct nfs41_server_scope;\n\nstruct nfs41_impl_id;\n\nstruct nfs41_exchange_id_res {\n\tu64 clientid;\n\tu32 seqid;\n\tu32 flags;\n\tstruct nfs41_server_owner *server_owner;\n\tstruct nfs41_server_scope *server_scope;\n\tstruct nfs41_impl_id *impl_id;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_exchange_id_data {\n\tstruct nfs41_exchange_id_res res;\n\tstruct nfs41_exchange_id_args args;\n\tlong: 32;\n};\n\nstruct nfs4_sequence_args {\n\tstruct nfs4_slot *sa_slot;\n\tu8 sa_cache_this: 1;\n\tu8 sa_privileged: 1;\n};\n\nstruct nfs41_free_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_sequence_slot_ops;\n\nstruct nfs4_sequence_res {\n\tconst struct nfs4_sequence_slot_ops *sr_slot_ops;\n\tstruct nfs4_slot *sr_slot;\n\tlong unsigned int sr_timestamp;\n\tint sr_status;\n\tu32 sr_status_flags;\n\tu32 sr_highest_slotid;\n\tu32 sr_target_highest_slotid;\n};\n\nstruct nfs41_free_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfstime4 {\n\tint64_t seconds;\n\tuint32_t nseconds;\n\tlong: 32;\n};\n\nstruct nfs41_impl_id {\n\tchar domain[1025];\n\tchar name[1025];\n\tlong: 32;\n\tstruct nfstime4 date;\n};\n\nstruct nfs41_reclaim_complete_args {\n\tstruct nfs4_sequence_args seq_args;\n\tunsigned char one_fs: 1;\n};\n\nstruct nfs41_reclaim_complete_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs41_secinfo_no_name_args {\n\tstruct nfs4_sequence_args seq_args;\n\tint style;\n};\n\nstruct nfs41_server_owner {\n\tuint64_t minor_id;\n\tuint32_t major_id_sz;\n\tchar major_id[1024];\n\tlong: 32;\n};\n\nstruct nfs41_server_scope {\n\tuint32_t server_scope_sz;\n\tchar server_scope[1024];\n};\n\nstruct nfs41_test_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs41_test_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfs42_clone_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid src_stateid;\n\tnfs4_stateid dst_stateid;\n\t__u64 src_offset;\n\t__u64 dst_offset;\n\t__u64 count;\n\tconst u32 *dst_bitmask;\n\tlong: 32;\n};\n\nstruct nfs_server;\n\nstruct nfs42_clone_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int rpc_status;\n\tstruct nfs_fattr *dst_fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nl4_server;\n\nstruct nfs42_copy_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tnfs4_stateid src_stateid;\n\tu64 src_pos;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid dst_stateid;\n\tu64 dst_pos;\n\tu64 count;\n\tbool sync;\n\tstruct nl4_server *cp_src;\n};\n\nstruct nfs42_netaddr {\n\tchar netid[5];\n\tchar addr[58];\n\tu32 netid_len;\n\tu32 addr_len;\n};\n\nstruct nl4_server {\n\tenum netloc_type4 nl4_type;\n\tunion {\n\t\tstruct {\n\t\t\tint nl4_str_sz;\n\t\t\tchar nl4_str[1025];\n\t\t};\n\t\tstruct nfs42_netaddr nl4_addr;\n\t} u;\n};\n\nstruct nfs42_copy_notify_args {\n\tstruct nfs4_sequence_args cna_seq_args;\n\tstruct nfs_fh *cna_src_fh;\n\tnfs4_stateid cna_src_stateid;\n\tstruct nl4_server cna_dst;\n};\n\nstruct nfs42_copy_notify_res {\n\tstruct nfs4_sequence_res cnr_seq_res;\n\tlong: 32;\n\tstruct nfstime4 cnr_lease_time;\n\tnfs4_stateid cnr_stateid;\n\tstruct nl4_server cnr_src;\n};\n\nstruct nfs42_write_res {\n\tnfs4_stateid stateid;\n\tlong: 32;\n\tu64 count;\n\tstruct nfs_writeverf verifier;\n\tlong: 32;\n};\n\nstruct nfs_commitres {\n\tstruct nfs4_sequence_res seq_res;\n\t__u32 op_status;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_writeverf *verf;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs42_copy_res {\n\tstruct nfs4_sequence_res seq_res;\n\tlong: 32;\n\tstruct nfs42_write_res write_res;\n\tbool consecutive;\n\tbool synchronous;\n\tstruct nfs_commitres commit_res;\n};\n\nstruct nfs42_device_error {\n\tstruct nfs4_deviceid dev_id;\n\tint status;\n\tenum nfs_opnum4 opnum;\n};\n\nstruct nfs42_falloc_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *falloc_fh;\n\tnfs4_stateid falloc_stateid;\n\tu64 falloc_offset;\n\tu64 falloc_length;\n\tconst u32 *falloc_bitmask;\n\tlong: 32;\n};\n\nstruct nfs42_falloc_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tstruct nfs_fattr *falloc_fattr;\n\tconst struct nfs_server *falloc_server;\n};\n\nstruct nfs42_getxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_getxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tsize_t xattr_len;\n};\n\nstruct nfs42_layout_error {\n\t__u64 offset;\n\t__u64 length;\n\tnfs4_stateid stateid;\n\tstruct nfs42_device_error errors[1];\n\tlong: 32;\n};\n\nstruct nfs42_layouterror_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct inode *inode;\n\tunsigned int num_errors;\n\tstruct nfs42_layout_error errors[5];\n};\n\nstruct nfs42_layouterror_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int num_errors;\n\tint rpc_status;\n};\n\nstruct pnfs_layout_segment;\n\nstruct nfs42_layouterror_data {\n\tstruct nfs42_layouterror_args args;\n\tstruct nfs42_layouterror_res res;\n\tstruct inode *inode;\n\tstruct pnfs_layout_segment *lseg;\n\tlong: 32;\n};\n\nstruct nfs42_layoutstat_devinfo;\n\nstruct nfs42_layoutstat_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tint num_dev;\n\tstruct nfs42_layoutstat_devinfo *devinfo;\n};\n\nstruct nfs42_layoutstat_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint num_dev;\n\tint rpc_status;\n};\n\nstruct nfs42_layoutstat_data {\n\tstruct inode *inode;\n\tstruct nfs42_layoutstat_args args;\n\tstruct nfs42_layoutstat_res res;\n};\n\nstruct nfs4_xdr_opaque_ops;\n\nstruct nfs4_xdr_opaque_data {\n\tconst struct nfs4_xdr_opaque_ops *ops;\n\tvoid *data;\n};\n\nstruct nfs42_layoutstat_devinfo {\n\tstruct nfs4_deviceid dev_id;\n\t__u64 offset;\n\t__u64 length;\n\t__u64 read_count;\n\t__u64 read_bytes;\n\t__u64 write_count;\n\t__u64 write_bytes;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data ld_private;\n\tlong: 32;\n};\n\nstruct nfs42_listxattrsargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tu32 count;\n\tu64 cookie;\n\tstruct page **xattr_pages;\n\tlong: 32;\n};\n\nstruct nfs42_listxattrsres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct folio *scratch;\n\tvoid *xattr_buf;\n\tsize_t xattr_len;\n\tu64 cookie;\n\tbool eof;\n\tsize_t copied;\n};\n\nstruct nfs42_offload_status_args {\n\tstruct nfs4_sequence_args osa_seq_args;\n\tstruct nfs_fh *osa_src_fh;\n\tnfs4_stateid osa_stateid;\n};\n\nstruct nfs42_offload_status_res {\n\tstruct nfs4_sequence_res osr_seq_res;\n\tlong: 32;\n\tu64 osr_count;\n\tint complete_count;\n\tu32 osr_complete;\n};\n\nstruct nfs42_offload_data {\n\tstruct nfs_server *seq_server;\n\tstruct nfs42_offload_status_args args;\n\tlong: 32;\n\tstruct nfs42_offload_status_res res;\n};\n\nstruct nfs42_removexattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n};\n\nstruct nfs4_change_info {\n\tu32 atomic;\n\tlong: 32;\n\tu64 before;\n\tu64 after;\n};\n\nstruct nfs42_removexattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs42_seek_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *sa_fh;\n\tnfs4_stateid sa_stateid;\n\tu64 sa_offset;\n\tu32 sa_what;\n\tlong: 32;\n};\n\nstruct nfs42_seek_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tu32 sr_eof;\n\tlong: 32;\n\tu64 sr_offset;\n};\n\nstruct nfs42_setxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tconst char *xattr_name;\n\tu32 xattr_flags;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_setxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs4_accessargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tu32 access;\n};\n\nstruct nfs4_accessres {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tu32 supported;\n\tu32 access;\n};\n\nstruct nfs4_add_xprt_data {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct nfs4_cached_acl {\n\tenum nfs4_acl_type type;\n\tint cached;\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct nfs4_call_sync_data {\n\tconst struct nfs_server *seq_server;\n\tstruct nfs4_sequence_args *seq_args;\n\tstruct nfs4_sequence_res *seq_res;\n};\n\nstruct nfs_seqid;\n\nstruct nfs4_layoutreturn_args;\n\nstruct nfs_closeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n\tfmode_t fmode;\n\tu32 share_access;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs4_layoutreturn_res;\n\nstruct nfs_closeres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct pnfs_layout_hdr;\n\nstruct nfs4_layoutreturn_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_layout_hdr *layout;\n\tstruct inode *inode;\n\tstruct pnfs_layout_range range;\n\tnfs4_stateid stateid;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data *ld_private;\n\tlong: 32;\n};\n\nstruct nfs4_layoutreturn_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 lrs_present;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_state;\n\nstruct nfs4_closedata {\n\tstruct inode *inode;\n\tstruct nfs4_state *state;\n\tstruct nfs_closeargs arg;\n\tstruct nfs_closeres res;\n\tlong: 32;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t\tlong: 32;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_copy_state {\n\tstruct list_head copies;\n\tstruct list_head src_copies;\n\tnfs4_stateid stateid;\n\tstruct completion completion;\n\tlong: 32;\n\tuint64_t count;\n\tstruct nfs_writeverf verf;\n\tint error;\n\tint flags;\n\tstruct nfs4_state *parent_src_state;\n\tstruct nfs4_state *parent_dst_state;\n\tlong: 32;\n};\n\nstruct nfs4_create_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tu32 ftype;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page **pages;\n\t\t\tunsigned int len;\n\t\t} symlink;\n\t\tstruct {\n\t\t\tu32 specdata1;\n\t\t\tu32 specdata2;\n\t\t} device;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst struct iattr *attrs;\n\tconst struct nfs_fh *dir_fh;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n};\n\nstruct nfs4_create_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info dir_cinfo;\n};\n\nstruct nfs4_createdata {\n\tstruct rpc_message msg;\n\tstruct nfs4_create_arg arg;\n\tstruct nfs4_create_res res;\n\tstruct nfs_fh fh;\n\tlong: 32;\n\tstruct nfs_fattr fattr;\n};\n\nstruct nfs4_delegattr {\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tbool atime_set;\n\tbool mtime_set;\n\tlong: 32;\n};\n\nstruct nfs4_delegreturnargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fhandle;\n\tconst nfs4_stateid *stateid;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n\tstruct nfs4_delegattr *sattr_args;\n};\n\nstruct nfs4_delegreturnres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n\tbool sattr_res;\n\tint sattr_ret;\n};\n\nstruct nfs4_delegreturndata {\n\tstruct nfs4_delegreturnargs args;\n\tstruct nfs4_delegreturnres res;\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tlong: 32;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t\tlong: 32;\n\t} lr;\n\tstruct nfs4_delegattr sattr;\n\tstruct nfs_fattr fattr;\n\tint rpc_status;\n\tstruct inode *inode;\n};\n\nstruct pnfs_layoutdriver_type;\n\nstruct nfs4_deviceid_node {\n\tstruct hlist_node node;\n\tstruct hlist_node tmpnode;\n\tconst struct pnfs_layoutdriver_type *ld;\n\tconst struct nfs_client *nfs_client;\n\tlong unsigned int flags;\n\tlong unsigned int timestamp_unavailable;\n\tstruct nfs4_deviceid deviceid;\n\tstruct callback_head rcu;\n\tatomic_t ref;\n};\n\nstruct nfs4_ds_server {\n\tstruct list_head list;\n\tstruct rpc_clnt *rpc_clnt;\n};\n\nstruct nfs4_exception {\n\tstruct nfs4_state *state;\n\tstruct inode *inode;\n\tnfs4_stateid *stateid;\n\tlong int timeout;\n\tshort unsigned int retrans;\n\tunsigned char task_is_privileged: 1;\n\tunsigned char delay: 1;\n\tunsigned char recovering: 1;\n\tunsigned char retry: 1;\n\tbool interruptible;\n};\n\nstruct nfs4_ff_busy_timer {\n\tktime_t start_time;\n\tatomic_t n_ops;\n\tlong: 32;\n};\n\nstruct nfs4_ff_ds_version {\n\tu32 version;\n\tu32 minor_version;\n\tu32 rsize;\n\tu32 wsize;\n\tbool tightly_coupled;\n};\n\nstruct nfs4_ff_io_stat {\n\t__u64 ops_requested;\n\t__u64 bytes_requested;\n\t__u64 ops_completed;\n\t__u64 bytes_completed;\n\t__u64 bytes_not_delivered;\n\tktime_t total_busy_time;\n\tktime_t aggregate_completion_time;\n};\n\nstruct nfs4_pnfs_ds;\n\nstruct nfs4_ff_layout_ds {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 ds_versions_cnt;\n\tstruct nfs4_ff_ds_version *ds_versions;\n\tstruct nfs4_pnfs_ds *ds;\n};\n\nstruct nfs4_ff_layout_ds_err {\n\tstruct list_head list;\n\tu64 offset;\n\tu64 length;\n\tint status;\n\tenum nfs_opnum4 opnum;\n\tnfs4_stateid stateid;\n\tstruct nfs4_deviceid deviceid;\n\tlong: 32;\n};\n\nstruct nfsd_file;\n\nstruct nfs_file_localio {\n\tstruct nfsd_file *ro_file;\n\tstruct nfsd_file *rw_file;\n\tstruct list_head list;\n\tvoid *nfs_uuid;\n};\n\nstruct nfs4_ff_layoutstat {\n\tstruct nfs4_ff_io_stat io_stat;\n\tstruct nfs4_ff_busy_timer busy_timer;\n};\n\nstruct nfs4_ff_layout_mirror;\n\nstruct nfs4_ff_layout_ds_stripe {\n\tstruct nfs4_ff_layout_mirror *mirror;\n\tstruct nfs4_deviceid devid;\n\tu32 efficiency;\n\tstruct nfs4_ff_layout_ds *mirror_ds;\n\tu32 fh_versions_cnt;\n\tstruct nfs_fh *fh_versions;\n\tnfs4_stateid stateid;\n\tconst struct cred *ro_cred;\n\tconst struct cred *rw_cred;\n\tstruct nfs_file_localio nfl;\n\tlong: 32;\n\tstruct nfs4_ff_layoutstat read_stat;\n\tstruct nfs4_ff_layoutstat write_stat;\n\tktime_t start_time;\n};\n\nstruct nfs4_ff_layout_mirror {\n\tstruct pnfs_layout_hdr *layout;\n\tstruct list_head mirrors;\n\tu32 dss_count;\n\tstruct nfs4_ff_layout_ds_stripe *dss;\n\trefcount_t ref;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu32 report_interval;\n};\n\nstruct pnfs_layout_segment {\n\tstruct list_head pls_list;\n\tstruct list_head pls_lc_list;\n\tstruct list_head pls_commits;\n\tstruct pnfs_layout_range pls_range;\n\trefcount_t pls_refcount;\n\tu32 pls_seq;\n\tlong unsigned int pls_flags;\n\tstruct pnfs_layout_hdr *pls_layout;\n};\n\nstruct nfs4_ff_layout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu64 stripe_unit;\n\tu32 flags;\n\tu32 mirror_array_cnt;\n\tstruct nfs4_ff_layout_mirror *mirror_array[0];\n};\n\nstruct nfs4_file_layout_dsaddr {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 stripe_count;\n\tu8 *stripe_indices;\n\tu32 ds_num;\n\tstruct nfs4_pnfs_ds *ds_list[0];\n};\n\nstruct pnfs_layout_hdr {\n\trefcount_t plh_refcount;\n\tatomic_t plh_outstanding;\n\tstruct list_head plh_layouts;\n\tstruct list_head plh_bulk_destroy;\n\tstruct list_head plh_segs;\n\tstruct list_head plh_return_segs;\n\tlong unsigned int plh_block_lgets;\n\tlong unsigned int plh_retry_timestamp;\n\tlong unsigned int plh_flags;\n\tnfs4_stateid plh_stateid;\n\tu32 plh_barrier;\n\tu32 plh_return_seq;\n\tenum pnfs_iomode plh_return_iomode;\n\tlong: 32;\n\tloff_t plh_lwb;\n\tconst struct cred *plh_lc_cred;\n\tstruct inode *plh_inode;\n\tstruct callback_head plh_rcu;\n};\n\nstruct pnfs_commit_ops;\n\nstruct pnfs_ds_commit_info {\n\tstruct list_head commits;\n\tunsigned int nwritten;\n\tunsigned int ncommitting;\n\tconst struct pnfs_commit_ops *ops;\n};\n\nstruct nfs4_filelayout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tlong: 32;\n};\n\nstruct nfs4_filelayout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu32 stripe_type;\n\tu32 commit_through_mds;\n\tu32 stripe_unit;\n\tu32 first_stripe_index;\n\tu64 pattern_offset;\n\tstruct nfs4_deviceid deviceid;\n\tstruct nfs4_file_layout_dsaddr *dsaddr;\n\tunsigned int num_fh;\n\tstruct nfs_fh **fh_array;\n\tlong: 32;\n};\n\nstruct nfs4_flexfile_layout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tstruct list_head mirrors;\n\tstruct list_head error_list;\n\tlong: 32;\n\tktime_t last_report_time;\n};\n\nstruct nfs4_flexfile_layoutreturn_args {\n\tstruct list_head errors;\n\tstruct nfs42_layoutstat_devinfo devinfo[4];\n\tunsigned int num_errors;\n\tunsigned int num_dev;\n\tstruct page *pages[1];\n\tlong: 32;\n};\n\nstruct nfs4_string {\n\tunsigned int len;\n\tchar *data;\n};\n\nstruct nfs4_pathname {\n\tunsigned int ncomponents;\n\tstruct nfs4_string components[512];\n};\n\nstruct nfs4_fs_location {\n\tunsigned int nservers;\n\tstruct nfs4_string servers[10];\n\tstruct nfs4_pathname rootpath;\n};\n\nstruct nfs4_fs_locations {\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tstruct nfs4_pathname fs_path;\n\tint nlocations;\n\tstruct nfs4_fs_location locations[10];\n};\n\nstruct nfs4_fs_locations_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct nfs_fh *fh;\n\tconst struct qstr *name;\n\tstruct page *page;\n\tconst u32 *bitmask;\n\tlong: 32;\n\tclientid4 clientid;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n\tlong: 32;\n};\n\nstruct nfs4_fs_locations_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_fs_locations *fs_locations;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tlong: 32;\n\tclientid4 clientid;\n\tunsigned char renew: 1;\n\tlong: 32;\n};\n\nstruct nfs4_fsid_present_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fh *fh;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsinfo;\n\nstruct nfs4_fsinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsinfo *fsinfo;\n};\n\nstruct nfs4_gdd_res {\n\tu32 status;\n\tnfs4_stateid deleg;\n};\n\nstruct nfs4_get_lease_time_args {\n\tstruct nfs4_sequence_args la_seq_args;\n};\n\nstruct nfs4_get_lease_time_res;\n\nstruct nfs4_get_lease_time_data {\n\tstruct nfs4_get_lease_time_args *args;\n\tstruct nfs4_get_lease_time_res *res;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_get_lease_time_res {\n\tstruct nfs4_sequence_res lr_seq_res;\n\tstruct nfs_fsinfo *lr_fsinfo;\n};\n\nstruct nfs4_getattr_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tbool get_dir_deleg;\n};\n\nstruct nfs4_getattr_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_gdd_res *gdd_res;\n};\n\nstruct pnfs_device;\n\nstruct nfs4_getdeviceinfo_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_device *pdev;\n\t__u32 notify_types;\n};\n\nstruct nfs4_getdeviceinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct pnfs_device *pdev;\n\t__u32 notification;\n};\n\nstruct nfs4_label {\n\tuint32_t lfs;\n\tuint32_t pi;\n\tu32 lsmid;\n\tu32 len;\n\tchar *label;\n};\n\nstruct nfs4_layoutcommit_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n\tlong: 32;\n\t__u64 lastbytewritten;\n\tstruct inode *inode;\n\tconst u32 *bitmask;\n\tsize_t layoutupdate_len;\n\tstruct page *layoutupdate_page;\n\tstruct page **layoutupdate_pages;\n\t__be32 *start_p;\n};\n\nstruct rpc_wait {\n\tstruct list_head list;\n\tstruct list_head links;\n\tstruct list_head timer_list;\n};\n\nstruct rpc_call_ops;\n\nstruct rpc_xprt;\n\nstruct rpc_rqst;\n\nstruct rpc_task {\n\tatomic_t tk_count;\n\tint tk_status;\n\tstruct list_head tk_task;\n\tvoid (*tk_callback)(struct rpc_task *);\n\tvoid (*tk_action)(struct rpc_task *);\n\tlong unsigned int tk_timeout;\n\tlong unsigned int tk_runstate;\n\tstruct rpc_wait_queue *tk_waitqueue;\n\tunion {\n\t\tstruct work_struct tk_work;\n\t\tstruct rpc_wait tk_wait;\n\t} u;\n\tstruct rpc_message tk_msg;\n\tvoid *tk_calldata;\n\tconst struct rpc_call_ops *tk_ops;\n\tstruct rpc_clnt *tk_client;\n\tstruct rpc_xprt *tk_xprt;\n\tstruct rpc_cred *tk_op_cred;\n\tstruct rpc_rqst *tk_rqstp;\n\tstruct workqueue_struct *tk_workqueue;\n\tktime_t tk_start;\n\tpid_t tk_owner;\n\tint tk_rpc_status;\n\tshort unsigned int tk_flags;\n\tshort unsigned int tk_timeouts;\n\tunsigned char tk_priority: 2;\n\tunsigned char tk_garb_retry: 2;\n\tunsigned char tk_cred_retry: 2;\n};\n\nstruct nfs4_layoutcommit_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tint status;\n};\n\nstruct nfs4_layoutcommit_data {\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct list_head lseg_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tstruct nfs4_layoutcommit_args args;\n\tstruct nfs4_layoutcommit_res res;\n};\n\nstruct nfs4_layoutdriver_data {\n\tstruct page **pages;\n\t__u32 pglen;\n\t__u32 len;\n};\n\nstruct nfs_open_context;\n\nstruct nfs4_layoutget_args {\n\tstruct nfs4_sequence_args seq_args;\n\t__u32 type;\n\tlong: 32;\n\tstruct pnfs_layout_range range;\n\t__u64 minlength;\n\t__u32 maxcount;\n\tstruct inode *inode;\n\tstruct nfs_open_context *ctx;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data layout;\n\tlong: 32;\n};\n\nstruct nfs4_layoutget_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint status;\n\t__u32 return_on_close;\n\tlong: 32;\n\tstruct pnfs_layout_range range;\n\t__u32 type;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data *layoutp;\n\tlong: 32;\n};\n\nstruct nfs4_layoutget {\n\tstruct nfs4_layoutget_args args;\n\tstruct nfs4_layoutget_res res;\n\tconst struct cred *cred;\n\tstruct pnfs_layout_hdr *lo;\n\tgfp_t gfp_flags;\n\tlong: 32;\n};\n\nstruct nfs4_layoutreturn {\n\tstruct nfs4_layoutreturn_args args;\n\tstruct nfs4_layoutreturn_res res;\n\tconst struct cred *cred;\n\tstruct nfs_client *clp;\n\tstruct inode *inode;\n\tint rpc_status;\n\tstruct nfs4_xdr_opaque_data ld_private;\n\tlong: 32;\n};\n\nstruct nfs4_link_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_link_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *dir_attr;\n\tlong: 32;\n};\n\nstruct nfs_seqid_counter {\n\tktime_t create_time;\n\tu64 owner_id;\n\tint flags;\n\tu32 counter;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct rpc_wait_queue wait;\n};\n\nstruct nfs4_lock_state {\n\tstruct list_head ls_locks;\n\tstruct nfs4_state *ls_state;\n\tlong unsigned int ls_flags;\n\tstruct nfs_seqid_counter ls_seqid;\n\tnfs4_stateid ls_stateid;\n\trefcount_t ls_count;\n\tfl_owner_t ls_owner;\n\tlong: 32;\n};\n\nstruct nfs4_lock_waiter {\n\tstruct inode *inode;\n\tlong: 32;\n\tstruct nfs_lowner owner;\n\twait_queue_entry_t wait;\n\tlong: 32;\n};\n\nstruct nfs_lock_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *lock_seqid;\n\tnfs4_stateid lock_stateid;\n\tstruct nfs_seqid *open_seqid;\n\tnfs4_stateid open_stateid;\n\tstruct nfs_lowner lock_owner;\n\tunsigned char block: 1;\n\tunsigned char reclaim: 1;\n\tunsigned char new_lock: 1;\n\tunsigned char new_lock_owner: 1;\n\tlong: 32;\n};\n\nstruct nfs_lock_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *lock_seqid;\n\tstruct nfs_seqid *open_seqid;\n};\n\nstruct nfs4_lockdata {\n\tstruct nfs_lock_args arg;\n\tstruct nfs_lock_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct file_lock fl;\n\tlong unsigned int timestamp;\n\tint rpc_status;\n\tint cancelled;\n\tstruct nfs_server *server;\n};\n\nstruct nfs4_lookup_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookup_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_lookup_root_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_mig_recovery_ops {\n\tint (*get_locations)(struct nfs_server *, struct nfs_fh *, struct nfs4_fs_locations *, struct page *, const struct cred *);\n\tint (*fsid_present)(struct inode *, const struct cred *);\n};\n\nstruct nfs4_state_recovery_ops;\n\nstruct nfs4_state_maintenance_ops;\n\nstruct nfs4_minor_version_ops {\n\tu32 minor_version;\n\tunsigned int init_caps;\n\tint (*init_client)(struct nfs_client *);\n\tvoid (*shutdown_client)(struct nfs_client *);\n\tbool (*match_stateid)(const nfs4_stateid *, const nfs4_stateid *);\n\tint (*find_root_sec)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *);\n\tvoid (*free_lock_state)(struct nfs_server *, struct nfs4_lock_state *);\n\tint (*test_and_free_expired)(struct nfs_server *, nfs4_stateid *, const struct cred *);\n\tstruct nfs_seqid * (*alloc_seqid)(struct nfs_seqid_counter *, gfp_t);\n\tvoid (*session_trunk)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tconst struct rpc_call_ops *call_sync_ops;\n\tconst struct nfs4_sequence_slot_ops *sequence_slot_ops;\n\tconst struct nfs4_state_recovery_ops *reboot_recovery_ops;\n\tconst struct nfs4_state_recovery_ops *nograce_recovery_ops;\n\tconst struct nfs4_state_maintenance_ops *state_renewal_ops;\n\tconst struct nfs4_mig_recovery_ops *mig_recovery_ops;\n};\n\nstruct nfs_string {\n\tunsigned int len;\n\tconst char *data;\n};\n\nstruct nfs4_mount_data {\n\tint version;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct nfs_string client_addr;\n\tstruct nfs_string mnt_path;\n\tstruct nfs_string hostname;\n\tunsigned int host_addrlen;\n\tstruct sockaddr *host_addr;\n\tint proto;\n\tint auth_flavourlen;\n\tint *auth_flavours;\n};\n\nstruct nfs4_open_caps {\n\tu32 oa_share_access[1];\n\tu32 oa_share_deny[1];\n\tu32 oa_share_access_want[1];\n\tu32 oa_open_claim[1];\n\tu32 oa_createmode[1];\n};\n\nstruct nfs4_open_createattrs {\n\tstruct nfs4_label *label;\n\tstruct iattr *sattr;\n\tconst __u32 verf[2];\n};\n\nstruct nfs4_open_delegation {\n\t__u32 open_delegation_type;\n\tunion {\n\t\tstruct {\n\t\t\tfmode_t type;\n\t\t\t__u32 do_recall;\n\t\t\tnfs4_stateid stateid;\n\t\t\tlong unsigned int pagemod_limit;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 why_no_delegation;\n\t\t\t__u32 will_notify;\n\t\t};\n\t};\n};\n\nstruct stateowner_id {\n\t__u64 create_time;\n\t__u64 uniquifier;\n};\n\nstruct nfs_openargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct nfs_seqid *seqid;\n\tint open_flags;\n\tfmode_t fmode;\n\tu32 share_access;\n\tu32 access;\n\t__u64 clientid;\n\tstruct stateowner_id id;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iattr *attrs;\n\t\t\tnfs4_verifier verifier;\n\t\t};\n\t\tnfs4_stateid delegation;\n\t\t__u32 delegation_type;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst u32 *open_bitmap;\n\tenum open_claim_type4 claim;\n\tenum createmode4 createmode;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n\tstruct nfs4_layoutget_args *lg_args;\n};\n\nstruct nfs_openres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fh fh;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n\t__u32 rflags;\n\tstruct nfs_fattr *f_attr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\t__u32 attrset[3];\n\tstruct nfs4_string *owner;\n\tstruct nfs4_string *group_owner;\n\tstruct nfs4_open_delegation delegation;\n\t__u32 access_request;\n\t__u32 access_supported;\n\t__u32 access_result;\n\tstruct nfs4_layoutget_res *lg_res;\n};\n\nstruct nfs_open_confirmargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tnfs4_stateid *stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_open_confirmres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs4_state_owner;\n\nstruct nfs4_opendata {\n\tstruct kref kref;\n\tlong: 32;\n\tstruct nfs_openargs o_arg;\n\tstruct nfs_openres o_res;\n\tstruct nfs_open_confirmargs c_arg;\n\tstruct nfs_open_confirmres c_res;\n\tstruct nfs4_string owner_name;\n\tstruct nfs4_string group_name;\n\tstruct nfs4_label *a_label;\n\tlong: 32;\n\tstruct nfs_fattr f_attr;\n\tstruct dentry *dir;\n\tstruct dentry *dentry;\n\tstruct nfs4_state_owner *owner;\n\tstruct nfs4_state *state;\n\tstruct iattr attrs;\n\tstruct nfs4_layoutget *lgp;\n\tlong unsigned int timestamp;\n\tbool rpc_done;\n\tbool file_created;\n\tbool is_recover;\n\tbool cancelled;\n\tint rpc_status;\n};\n\nstruct nfs4_pathconf_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_pathconf;\n\nstruct nfs4_pathconf_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_pathconf *pathconf;\n};\n\nstruct nfs4_pnfs_ds {\n\tstruct list_head ds_node;\n\tchar *ds_remotestr;\n\tstruct list_head ds_addrs;\n\tconst struct net *ds_net;\n\tstruct nfs_client *ds_clp;\n\trefcount_t ds_count;\n\tlong unsigned int ds_state;\n};\n\nstruct nfs4_pnfs_ds_addr {\n\tstruct __kernel_sockaddr_storage da_addr;\n\tsize_t da_addrlen;\n\tstruct list_head da_node;\n\tchar *da_remotestr;\n\tconst char *da_netid;\n\tint da_transport;\n};\n\nstruct nfs4_readdir_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tlong: 32;\n\tu64 cookie;\n\tnfs4_verifier verifier;\n\tu32 count;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tconst u32 *bitmask;\n\tbool plus;\n\tlong: 32;\n};\n\nstruct nfs4_readdir_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_verifier verifier;\n\tunsigned int pgbase;\n};\n\nstruct nfs4_readlink {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs4_readlink_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_reclaim_complete_data {\n\tstruct nfs_client *clp;\n\tstruct nfs41_reclaim_complete_args arg;\n\tstruct nfs41_reclaim_complete_res res;\n};\n\nstruct rpcsec_gss_info {\n\tstruct rpcsec_gss_oid oid;\n\tu32 qop;\n\tu32 service;\n};\n\nstruct nfs4_secinfo4 {\n\tu32 flavor;\n\tstruct rpcsec_gss_info flavor_info;\n};\n\nstruct nfs4_secinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n};\n\nstruct nfs4_secinfo_flavors {\n\tunsigned int num_flavors;\n\tstruct nfs4_secinfo4 flavors[0];\n};\n\nstruct nfs4_secinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_secinfo_flavors *flavors;\n};\n\nstruct nfs4_sequence_data {\n\tstruct nfs_client *clp;\n\tstruct nfs4_sequence_args args;\n\tstruct nfs4_sequence_res res;\n};\n\nstruct nfs4_sequence_slot_ops {\n\tint (*process)(struct rpc_task *, struct nfs4_sequence_res *);\n\tint (*done)(struct rpc_task *, struct nfs4_sequence_res *);\n\tvoid (*free_slot)(struct nfs4_sequence_res *);\n};\n\nstruct nfs4_server_caps_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fhandle;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_server_caps_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 attr_bitmask[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 has_links;\n\tu32 has_symlinks;\n\tu32 fh_expire_type;\n\tu32 case_insensitive;\n\tu32 case_preserving;\n\tstruct nfs4_open_caps open_caps;\n};\n\nstruct nfs4_session;\n\nstruct nfs4_slot_table {\n\tstruct nfs4_session *session;\n\tstruct nfs4_slot *slots;\n\tlong unsigned int used_slots[32];\n\tspinlock_t slot_tbl_lock;\n\tstruct rpc_wait_queue slot_tbl_waitq;\n\twait_queue_head_t slot_waitq;\n\tu32 max_slots;\n\tu32 max_slotid;\n\tu32 highest_used_slotid;\n\tu32 target_highest_slotid;\n\tu32 server_highest_slotid;\n\ts32 d_target_highest_slotid;\n\ts32 d2_target_highest_slotid;\n\tlong unsigned int generation;\n\tstruct completion complete;\n\tlong unsigned int slot_tbl_state;\n};\n\nstruct nfs4_session {\n\tstruct nfs4_sessionid sess_id;\n\tu32 flags;\n\tlong unsigned int session_state;\n\tu32 hash_alg;\n\tu32 ssv_len;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_slot_table fc_slot_table;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tstruct nfs4_slot_table bc_slot_table;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_setclientid {\n\tconst nfs4_verifier *sc_verifier;\n\tu32 sc_prog;\n\tunsigned int sc_netid_len;\n\tchar sc_netid[6];\n\tunsigned int sc_uaddr_len;\n\tchar sc_uaddr[58];\n\tstruct nfs_client *sc_clnt;\n\tstruct rpc_cred *sc_cred;\n};\n\nstruct nfs4_setclientid_res {\n\tu64 clientid;\n\tnfs4_verifier confirm;\n};\n\nstruct nfs4_slot {\n\tstruct nfs4_slot_table *table;\n\tstruct nfs4_slot *next;\n\tlong unsigned int generation;\n\tu32 slot_nr;\n\tu32 seq_nr;\n\tu32 seq_nr_last_acked;\n\tu32 seq_nr_highest_sent;\n\tunsigned int privileged: 1;\n\tunsigned int seq_done: 1;\n};\n\nstruct nfs4_ssc_client_ops {\n\tstruct file * (*sco_open)(struct vfsmount *, struct nfs_fh *, nfs4_stateid *);\n\tvoid (*sco_close)(struct file *);\n};\n\nstruct nfs4_state {\n\tstruct list_head open_states;\n\tstruct list_head inode_states;\n\tstruct list_head lock_states;\n\tstruct nfs4_state_owner *owner;\n\tstruct inode *inode;\n\tlong unsigned int flags;\n\tspinlock_t state_lock;\n\tseqlock_t seqlock;\n\tnfs4_stateid stateid;\n\tnfs4_stateid open_stateid;\n\tunsigned int n_rdonly;\n\tunsigned int n_wronly;\n\tunsigned int n_rdwr;\n\tfmode_t state;\n\trefcount_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs4_state_maintenance_ops {\n\tint (*sched_state_renewal)(struct nfs_client *, const struct cred *, unsigned int);\n\tconst struct cred * (*get_state_renewal_cred)(struct nfs_client *);\n\tint (*renew_lease)(struct nfs_client *, const struct cred *);\n};\n\nstruct nfs4_state_owner {\n\tstruct nfs_server *so_server;\n\tstruct list_head so_lru;\n\tlong unsigned int so_expires;\n\tstruct rb_node so_server_node;\n\tconst struct cred *so_cred;\n\tspinlock_t so_lock;\n\tatomic_t so_count;\n\tlong unsigned int so_flags;\n\tstruct list_head so_states;\n\tlong: 32;\n\tstruct nfs_seqid_counter so_seqid;\n\tstruct mutex so_delegreturn_mutex;\n};\n\nstruct nfs4_state_recovery_ops {\n\tint owner_flag_bit;\n\tint state_flag_bit;\n\tint (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);\n\tint (*recover_lock)(struct nfs4_state *, struct file_lock *);\n\tint (*establish_clid)(struct nfs_client *, const struct cred *);\n\tint (*reclaim_complete)(struct nfs_client *, const struct cred *);\n\tint (*detect_trunking)(struct nfs_client *, struct nfs_client **, const struct cred *);\n};\n\nstruct nfs4_statfs_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsstat;\n\nstruct nfs4_statfs_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsstat *fsstat;\n};\n\nstruct nfs4_threshold {\n\t__u32 bm;\n\t__u32 l_type;\n\t__u64 rd_sz;\n\t__u64 wr_sz;\n\t__u64 rd_io_sz;\n\t__u64 wr_io_sz;\n};\n\nstruct nfs_locku_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *seqid;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs_locku_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_lock_context;\n\nstruct nfs4_unlockdata {\n\tstruct nfs_locku_args arg;\n\tstruct nfs_locku_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct file_lock fl;\n\tstruct nfs_server *server;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tlong: 32;\n};\n\nstruct nfs4_xattr_cache;\n\nstruct nfs4_xattr_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n\tstruct nfs4_xattr_cache *cache;\n\tbool draining;\n};\n\nstruct nfs4_xattr_entry;\n\nstruct nfs4_xattr_cache {\n\tstruct kref ref;\n\tstruct nfs4_xattr_bucket buckets[64];\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tatomic_long_t nent;\n\tspinlock_t listxattr_lock;\n\tstruct inode *inode;\n\tstruct nfs4_xattr_entry *listxattr;\n};\n\nstruct nfs4_xattr_entry {\n\tstruct kref ref;\n\tstruct hlist_node hnode;\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tchar *xattr_name;\n\tvoid *xattr_value;\n\tsize_t xattr_size;\n\tstruct nfs4_xattr_bucket *bucket;\n\tuint32_t flags;\n};\n\nstruct nfs4_xdr_opaque_ops {\n\tvoid (*encode)(struct xdr_stream *, const void *, const struct nfs4_xdr_opaque_data *);\n\tvoid (*free)(struct nfs4_xdr_opaque_data *);\n};\n\nstruct nfs_access_entry {\n\tstruct rb_node rb_node;\n\tstruct list_head lru;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tstruct group_info *group_info;\n\tu64 timestamp;\n\t__u32 mask;\n\tstruct callback_head callback_head;\n\tlong: 32;\n};\n\nstruct nfs_auth_info {\n\tunsigned int flavor_len;\n\trpc_authflavor_t flavors[12];\n};\n\nstruct nfs_cache_array_entry {\n\tu64 cookie;\n\tu64 ino;\n\tconst char *name;\n\tunsigned int name_len;\n\tunsigned char d_type;\n\tlong: 32;\n};\n\nstruct nfs_cache_array {\n\tu64 change_attr;\n\tu64 last_cookie;\n\tunsigned int size;\n\tunsigned char folio_full: 1;\n\tunsigned char folio_is_eof: 1;\n\tunsigned char cookies_are_ordered: 1;\n\tstruct nfs_cache_array_entry array[0];\n};\n\nstruct svc_serv;\n\nstruct nfs_callback_data {\n\tunsigned int users;\n\tstruct svc_serv *serv;\n};\n\nstruct xprtsec_parms {\n\tenum xprtsec_policies policy;\n\tkey_serial_t cert_serial;\n\tkey_serial_t privkey_serial;\n};\n\nstruct nfs_rpc_ops;\n\nstruct nfs_subversion;\n\nstruct nfs_client {\n\trefcount_t cl_count;\n\tatomic_t cl_mds_count;\n\tint cl_cons_state;\n\tlong unsigned int cl_res_state;\n\tlong unsigned int cl_flags;\n\tstruct __kernel_sockaddr_storage cl_addr;\n\tsize_t cl_addrlen;\n\tchar *cl_hostname;\n\tchar *cl_acceptor;\n\tstruct list_head cl_share_link;\n\tstruct list_head cl_superblocks;\n\tstruct rpc_clnt *cl_rpcclient;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tint cl_proto;\n\tstruct nfs_subversion *cl_nfs_mod;\n\tu32 cl_minorversion;\n\tunsigned int cl_nconnect;\n\tunsigned int cl_max_connect;\n\tconst char *cl_principal;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct list_head cl_ds_clients;\n\tlong: 32;\n\tu64 cl_clientid;\n\tnfs4_verifier cl_confirm;\n\tlong unsigned int cl_state;\n\tspinlock_t cl_lock;\n\tlong unsigned int cl_lease_time;\n\tlong unsigned int cl_last_renewal;\n\tstruct delayed_work cl_renewd;\n\tstruct rpc_wait_queue cl_rpcwaitq;\n\tstruct idmap *cl_idmap;\n\tconst char *cl_owner_id;\n\tu32 cl_cb_ident;\n\tconst struct nfs4_minor_version_ops *cl_mvops;\n\tlong unsigned int cl_mig_gen;\n\tstruct nfs4_slot_table *cl_slot_tbl;\n\tu32 cl_seqid;\n\tu32 cl_exchange_flags;\n\tstruct nfs4_session *cl_session;\n\tbool cl_preserve_clid;\n\tstruct nfs41_server_owner *cl_serverowner;\n\tstruct nfs41_server_scope *cl_serverscope;\n\tstruct nfs41_impl_id *cl_implid;\n\tlong unsigned int cl_sp4_flags;\n\twait_queue_head_t cl_lock_waitq;\n\tchar cl_ipaddr[48];\n\tstruct net *cl_net;\n\tnetns_tracker cl_ns_tracker;\n\tstruct list_head pending_cb_stateids;\n\tstruct callback_head rcu;\n};\n\nstruct rpc_timeout;\n\nstruct nfs_client_initdata {\n\tlong unsigned int init_flags;\n\tconst char *hostname;\n\tconst struct __kernel_sockaddr_storage *addr;\n\tconst char *nodename;\n\tconst char *ip_addr;\n\tsize_t addrlen;\n\tstruct nfs_subversion *nfs_mod;\n\tint proto;\n\tu32 minorversion;\n\tunsigned int nconnect;\n\tunsigned int max_connect;\n\tstruct net *net;\n\tconst struct rpc_timeout *timeparms;\n\tconst struct cred *cred;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct nfs_clone_mount {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_commit_data;\n\nstruct nfs_commit_info;\n\nstruct nfs_page;\n\nstruct nfs_commit_completion_ops {\n\tvoid (*completion)(struct nfs_commit_data *);\n\tvoid (*resched_write)(struct nfs_commit_info *, struct nfs_page *);\n};\n\nstruct nfs_commitargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tlong: 32;\n\t__u64 offset;\n\t__u32 count;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_direct_req;\n\nstruct nfs_commit_data {\n\tstruct rpc_task task;\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_writeverf verf;\n\tstruct list_head pages;\n\tstruct list_head list;\n\tstruct nfs_direct_req *dreq;\n\tstruct nfs_commitargs args;\n\tstruct nfs_commitres res;\n\tstruct nfs_open_context *context;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_index;\n\tlong: 32;\n\tloff_t lwb;\n\tconst struct rpc_call_ops *mds_ops;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n\tint (*commit_done_cb)(struct rpc_task *, struct nfs_commit_data *);\n\tlong unsigned int flags;\n};\n\nstruct nfs_mds_commit_info;\n\nstruct nfs_commit_info {\n\tstruct inode *inode;\n\tstruct nfs_mds_commit_info *mds;\n\tstruct pnfs_ds_commit_info *ds;\n\tstruct nfs_direct_req *dreq;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n};\n\nstruct nfs_delegation {\n\tstruct hlist_node hash;\n\tstruct list_head super_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tfmode_t type;\n\tlong unsigned int pagemod_limit;\n\tlong: 32;\n\t__u64 change_attr;\n\tlong unsigned int test_gen;\n\tlong unsigned int flags;\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_mds_commit_info {\n\tatomic_t rpcs_out;\n\tatomic_long_t ncommit;\n\tstruct list_head list;\n};\n\nstruct nfs_direct_req {\n\tstruct kref kref;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct kiocb *iocb;\n\tstruct inode *inode;\n\tatomic_t io_count;\n\tspinlock_t lock;\n\tlong: 32;\n\tloff_t io_start;\n\tssize_t count;\n\tssize_t max_count;\n\tssize_t error;\n\tstruct completion completion;\n\tstruct nfs_mds_commit_info mds_cinfo;\n\tstruct pnfs_ds_commit_info ds_cinfo;\n\tstruct work_struct work;\n\tint flags;\n\tlong: 32;\n};\n\nstruct nfs_entry {\n\t__u64 ino;\n\t__u64 cookie;\n\tconst char *name;\n\tunsigned int len;\n\tint eof;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tunsigned char d_type;\n\tstruct nfs_server *server;\n\tlong: 32;\n};\n\nstruct nfs_find_desc {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_free_stateid_data {\n\tstruct nfs_server *server;\n\tstruct nfs41_free_stateid_args args;\n\tstruct nfs41_free_stateid_res res;\n};\n\nstruct nfs_fs_context {\n\tbool internal;\n\tbool skip_reconfig_option_check;\n\tbool need_mount;\n\tbool sloppy;\n\tunsigned int flags;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tunsigned int timeo;\n\tunsigned int retrans;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namlen;\n\tunsigned int options;\n\tunsigned int bsize;\n\tstruct nfs_auth_info auth_info;\n\trpc_authflavor_t selected_flavor;\n\tstruct xprtsec_parms xprtsec;\n\tchar *client_address;\n\tunsigned int version;\n\tunsigned int minorversion;\n\tchar *fscache_uniq;\n\tshort unsigned int protofamily;\n\tshort unsigned int mountfamily;\n\tbool has_sec_mnt_opts;\n\tint lock_status;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tu32 version;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t} mount_server;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tchar *export_path;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t\tshort unsigned int nconnect;\n\t\tshort unsigned int max_connect;\n\t\tshort unsigned int export_path_len;\n\t} nfs_server;\n\tstruct nfs_fh *mntfh;\n\tstruct nfs_server *server;\n\tstruct nfs_subversion *nfs_mod;\n\tstruct nfs_clone_mount clone_data;\n};\n\nstruct nfs_fsinfo {\n\tstruct nfs_fattr *fattr;\n\t__u32 rtmax;\n\t__u32 rtpref;\n\t__u32 rtmult;\n\t__u32 wtmax;\n\t__u32 wtpref;\n\t__u32 wtmult;\n\t__u32 dtpref;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\t__u32 lease_time;\n\t__u32 nlayouttypes;\n\t__u32 layouttype[8];\n\t__u32 blksize;\n\t__u32 clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\t__u32 xattr_support;\n};\n\nstruct nfs_fsstat {\n\tstruct nfs_fattr *fattr;\n\tlong: 32;\n\t__u64 tbytes;\n\t__u64 fbytes;\n\t__u64 abytes;\n\t__u64 tfiles;\n\t__u64 ffiles;\n\t__u64 afiles;\n};\n\nstruct nfs_getaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_getaclres {\n\tstruct nfs4_sequence_res seq_res;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tsize_t acl_data_offset;\n\tint acl_flags;\n\tstruct folio *acl_scratch;\n};\n\nstruct nfs_inode {\n\t__u64 fileid;\n\tstruct nfs_fh fh;\n\tlong unsigned int flags;\n\tlong unsigned int cache_validity;\n\tlong: 32;\n\tstruct timespec64 btime;\n\tlong unsigned int read_cache_jiffies;\n\tlong unsigned int attrtimeo;\n\tlong unsigned int attrtimeo_timestamp;\n\tlong unsigned int attr_gencount;\n\tstruct rb_root access_cache;\n\tstruct list_head access_cache_entry_lru;\n\tstruct list_head access_cache_inode_lru;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int cache_change_attribute;\n\t\t\t__be32 cookieverf[2];\n\t\t\tstruct rw_semaphore rmdir_sem;\n\t\t};\n\t\tstruct {\n\t\t\tatomic_long_t nrequests;\n\t\t\tatomic_long_t redirtied_pages;\n\t\t\tstruct nfs_mds_commit_info commit_info;\n\t\t\tstruct mutex commit_mutex;\n\t\t};\n\t};\n\tstruct list_head open_files;\n\tstruct {\n\t\tint cnt;\n\t\tlong: 32;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 end;\n\t\t} gap[16];\n\t} *ooo;\n\tstruct nfs4_cached_acl *nfs4_acl;\n\tstruct list_head open_states;\n\tstruct nfs_delegation *delegation;\n\tstruct rw_semaphore rwsem;\n\tstruct pnfs_layout_hdr *layout;\n\t__u64 write_io;\n\t__u64 read_io;\n\tstruct nfs4_xattr_cache *xattr_cache;\n\tlong: 32;\n\tunion {\n\t\tstruct inode vfs_inode;\n\t};\n};\n\nstruct nfs_io_completion {\n\tvoid (*complete)(void *);\n\tvoid *data;\n\tstruct kref refcount;\n};\n\nstruct nfs_iostats {\n\tlong long unsigned int bytes[8];\n\tlong unsigned int events[27];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct nfs_lock_context {\n\trefcount_t count;\n\tstruct list_head list;\n\tstruct nfs_open_context *open_context;\n\tfl_owner_t lockowner;\n\tatomic_t io_count;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_lockt_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_lockt_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct file_lock *denied;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct nfs_mount_data {\n\tint version;\n\tint fd;\n\tstruct nfs2_fh old_root;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct sockaddr_in addr;\n\tchar hostname[256];\n\tint namlen;\n\tunsigned int bsize;\n\tstruct nfs3_fh root;\n\tint pseudoflavor;\n\tchar context[257];\n};\n\nstruct nfs_mount_request {\n\tstruct __kernel_sockaddr_storage *sap;\n\tsize_t salen;\n\tchar *hostname;\n\tchar *dirpath;\n\tu32 version;\n\tshort unsigned int protocol;\n\tstruct nfs_fh *fh;\n\tint noresvport;\n\tunsigned int *auth_flav_len;\n\trpc_authflavor_t *auth_flavs;\n\tstruct net *net;\n};\n\nstruct rpc_program;\n\nstruct rpc_stat {\n\tconst struct rpc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int netreconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcretrans;\n\tunsigned int rpcauthrefresh;\n\tunsigned int rpcgarbage;\n};\n\nstruct nfs_netns_client;\n\nstruct nfs_net {\n\tstruct cache_detail *nfs_dns_resolve;\n\tstruct rpc_pipe *bl_device_pipe;\n\tstruct bl_dev_msg bl_mount_reply;\n\twait_queue_head_t bl_wq;\n\tstruct mutex bl_mutex;\n\tstruct list_head nfs_client_list;\n\tstruct list_head nfs_volume_list;\n\tstruct idr cb_ident_idr;\n\tshort unsigned int nfs_callback_tcpport;\n\tshort unsigned int nfs_callback_tcpport6;\n\tint cb_users[3];\n\tstruct list_head nfs4_data_server_cache;\n\tspinlock_t nfs4_data_server_lock;\n\tstruct nfs_netns_client *nfs_client;\n\tspinlock_t nfs_client_lock;\n\tktime_t boot_time;\n\tstruct rpc_stat rpcstats;\n\tstruct proc_dir_entry *proc_nfsfs;\n\tlong: 32;\n};\n\nstruct nfs_netns_client {\n\tstruct kobject kobject;\n\tstruct kobject nfs_net_kobj;\n\tstruct net *net;\n\tconst char *identifier;\n};\n\nstruct nfs_open_context {\n\tstruct nfs_lock_context lock_context;\n\tfl_owner_t flock_owner;\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\tstruct rpc_cred *ll_cred;\n\tstruct nfs4_state *state;\n\tfmode_t mode;\n\tint error;\n\tlong unsigned int flags;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tstruct nfs_file_localio nfl;\n};\n\nstruct nfs_open_dir_context {\n\tstruct list_head list;\n\tatomic_t cache_hits;\n\tatomic_t cache_misses;\n\tlong unsigned int attr_gencount;\n\t__be32 verf[2];\n\tlong: 32;\n\t__u64 dir_cookie;\n\t__u64 last_cookie;\n\tlong unsigned int page_index;\n\tunsigned int dtsize;\n\tbool force_clear;\n\tbool eof;\n\tstruct callback_head callback_head;\n\tlong: 32;\n};\n\nstruct nfs_page {\n\tstruct list_head wb_list;\n\tunion {\n\t\tstruct page *wb_page;\n\t\tstruct folio *wb_folio;\n\t};\n\tstruct nfs_lock_context *wb_lock_context;\n\tlong unsigned int wb_index;\n\tunsigned int wb_offset;\n\tunsigned int wb_pgbase;\n\tunsigned int wb_bytes;\n\tstruct kref wb_kref;\n\tlong unsigned int wb_flags;\n\tstruct nfs_write_verifier wb_verf;\n\tstruct nfs_page *wb_this_page;\n\tstruct nfs_page *wb_head;\n\tshort unsigned int wb_nio;\n};\n\nstruct nfs_page_array {\n\tstruct page **pagevec;\n\tunsigned int npages;\n\tstruct page *page_array[8];\n};\n\nstruct nfs_page_iter_page {\n\tconst struct nfs_page *req;\n\tsize_t count;\n};\n\nstruct nfs_pgio_mirror {\n\tstruct list_head pg_list;\n\tlong unsigned int pg_bytes_written;\n\tsize_t pg_count;\n\tsize_t pg_bsize;\n\tunsigned int pg_base;\n\tunsigned char pg_recoalesce: 1;\n};\n\nstruct nfs_pageio_ops;\n\nstruct nfs_rw_ops;\n\nstruct nfs_pgio_completion_ops;\n\nstruct nfs_pageio_descriptor {\n\tstruct inode *pg_inode;\n\tconst struct nfs_pageio_ops *pg_ops;\n\tconst struct nfs_rw_ops *pg_rw_ops;\n\tint pg_ioflags;\n\tint pg_error;\n\tconst struct rpc_call_ops *pg_rpc_callops;\n\tconst struct nfs_pgio_completion_ops *pg_completion_ops;\n\tstruct pnfs_layout_segment *pg_lseg;\n\tstruct nfs_io_completion *pg_io_completion;\n\tstruct nfs_direct_req *pg_dreq;\n\tunsigned int pg_bsize;\n\tu32 pg_mirror_count;\n\tstruct nfs_pgio_mirror *pg_mirrors;\n\tstruct nfs_pgio_mirror pg_mirrors_static[1];\n\tstruct nfs_pgio_mirror *pg_mirrors_dynamic;\n\tu32 pg_mirror_idx;\n\tshort unsigned int pg_maxretrans;\n\tunsigned char pg_moreio: 1;\n};\n\nstruct nfs_pageio_ops {\n\tvoid (*pg_init)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tsize_t (*pg_test)(struct nfs_pageio_descriptor *, struct nfs_page *, struct nfs_page *);\n\tint (*pg_doio)(struct nfs_pageio_descriptor *);\n\tunsigned int (*pg_get_mirror_count)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tvoid (*pg_cleanup)(struct nfs_pageio_descriptor *);\n\tstruct nfs_pgio_mirror * (*pg_get_mirror)(struct nfs_pageio_descriptor *, u32);\n\tu32 (*pg_set_mirror)(struct nfs_pageio_descriptor *, u32);\n};\n\nstruct nfs_pathconf {\n\tstruct nfs_fattr *fattr;\n\t__u32 max_link;\n\t__u32 max_namelen;\n};\n\nstruct nfs_pgio_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct nfs_open_context *context;\n\tstruct nfs_lock_context *lock_context;\n\tnfs4_stateid stateid;\n\t__u64 offset;\n\t__u32 count;\n\tunsigned int pgbase;\n\tstruct page **pages;\n\tunion {\n\t\tunsigned int replen;\n\t\tstruct {\n\t\t\tconst u32 *bitmask;\n\t\t\tu32 bitmask_store[3];\n\t\t\tenum nfs3_stable_how stable;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header;\n\nstruct nfs_pgio_completion_ops {\n\tvoid (*error_cleanup)(struct list_head *, int);\n\tvoid (*init_hdr)(struct nfs_pgio_header *);\n\tvoid (*completion)(struct nfs_pgio_header *);\n\tvoid (*reschedule_io)(struct nfs_pgio_header *);\n};\n\nstruct nfs_pgio_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\t__u64 count;\n\t__u32 op_status;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int replen;\n\t\t\tint eof;\n\t\t\tvoid *scratch;\n\t\t};\n\t\tstruct {\n\t\t\tstruct nfs_writeverf *verf;\n\t\t\tconst struct nfs_server *server;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header {\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct list_head pages;\n\tstruct nfs_page *req;\n\tstruct nfs_writeverf verf;\n\tfmode_t rw_mode;\n\tstruct pnfs_layout_segment *lseg;\n\tloff_t io_start;\n\tconst struct rpc_call_ops *mds_ops;\n\tvoid (*release)(struct nfs_pgio_header *);\n\tconst struct nfs_pgio_completion_ops *completion_ops;\n\tconst struct nfs_rw_ops *rw_ops;\n\tstruct nfs_io_completion *io_completion;\n\tstruct nfs_direct_req *dreq;\n\tshort unsigned int retrans;\n\tint pnfs_error;\n\tint error;\n\tunsigned int good_bytes;\n\tlong unsigned int flags;\n\tlong: 32;\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_pgio_args args;\n\tstruct nfs_pgio_res res;\n\tlong unsigned int timestamp;\n\tint (*pgio_done_cb)(struct rpc_task *, struct nfs_pgio_header *);\n\t__u64 mds_offset;\n\tstruct nfs_page_array page_array;\n\tstruct nfs_client *ds_clp;\n\tu32 ds_commit_idx;\n\tu32 pgio_mirror_idx;\n\tlong: 32;\n};\n\nstruct nfs_readdir_arg {\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\t__be32 *verf;\n\tlong: 32;\n\tu64 cookie;\n\tstruct page **pages;\n\tunsigned int page_len;\n\tbool plus;\n\tlong: 32;\n};\n\nstruct nfs_readdir_descriptor {\n\tstruct file *file;\n\tstruct folio *folio;\n\tstruct dir_context *ctx;\n\tlong unsigned int folio_index;\n\tlong unsigned int folio_index_max;\n\tlong: 32;\n\tu64 dir_cookie;\n\tu64 last_cookie;\n\tloff_t current_index;\n\t__be32 verf[2];\n\tlong unsigned int dir_verifier;\n\tlong unsigned int timestamp;\n\tlong unsigned int gencount;\n\tlong unsigned int attr_gencount;\n\tunsigned int cache_entry_index;\n\tunsigned int buffer_fills;\n\tunsigned int dtsize;\n\tbool clear_cache;\n\tbool plus;\n\tbool eob;\n\tbool eof;\n};\n\nstruct nfs_readdir_res {\n\t__be32 *verf;\n};\n\nstruct nfs_referral_count {\n\tstruct list_head list;\n\tconst struct task_struct *task;\n\tunsigned int referral_count;\n};\n\nstruct nfs_removeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tlong: 32;\n\tstruct qstr name;\n};\n\nstruct nfs_removeres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs_fattr *dir_attr;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs_renameargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *old_dir;\n\tconst struct nfs_fh *new_dir;\n\tconst struct qstr *old_name;\n\tconst struct qstr *new_name;\n};\n\nstruct nfs_renameres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs4_change_info old_cinfo;\n\tstruct nfs_fattr *old_fattr;\n\tlong: 32;\n\tstruct nfs4_change_info new_cinfo;\n\tstruct nfs_fattr *new_fattr;\n\tlong: 32;\n};\n\nstruct nfs_renamedata {\n\tstruct nfs_renameargs args;\n\tstruct nfs_renameres res;\n\tstruct rpc_task task;\n\tconst struct cred *cred;\n\tstruct inode *old_dir;\n\tstruct dentry *old_dentry;\n\tlong: 32;\n\tstruct nfs_fattr old_fattr;\n\tstruct inode *new_dir;\n\tstruct dentry *new_dentry;\n\tstruct nfs_fattr new_fattr;\n\tvoid (*complete)(struct rpc_task *, struct nfs_renamedata *);\n\tlong int timeout;\n\tbool cancelled;\n\tlong: 32;\n};\n\nstruct nlmclnt_operations;\n\nstruct nfs_unlinkdata;\n\nstruct nfs_rpc_ops {\n\tu32 version;\n\tconst struct dentry_operations *dentry_ops;\n\tconst struct inode_operations *dir_inode_ops;\n\tconst struct inode_operations *file_inode_ops;\n\tconst struct file_operations *file_ops;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tint (*getroot)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*submount)(struct fs_context *, struct nfs_server *);\n\tint (*try_get_tree)(struct fs_context *);\n\tint (*getattr)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, struct inode *);\n\tint (*setattr)(struct dentry *, struct nfs_fattr *, struct iattr *);\n\tint (*lookup)(struct inode *, struct dentry *, const struct qstr *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*lookupp)(struct inode *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*access)(struct inode *, struct nfs_access_entry *, const struct cred *);\n\tint (*readlink)(struct inode *, struct page *, unsigned int, unsigned int);\n\tint (*create)(struct inode *, struct dentry *, struct iattr *, int);\n\tint (*remove)(struct inode *, struct dentry *);\n\tvoid (*unlink_setup)(struct rpc_message *, struct dentry *, struct inode *);\n\tvoid (*unlink_rpc_prepare)(struct rpc_task *, struct nfs_unlinkdata *);\n\tint (*unlink_done)(struct rpc_task *, struct inode *);\n\tvoid (*rename_setup)(struct rpc_message *, struct dentry *, struct dentry *, struct inode *);\n\tvoid (*rename_rpc_prepare)(struct rpc_task *, struct nfs_renamedata *);\n\tint (*rename_done)(struct rpc_task *, struct inode *, struct inode *);\n\tint (*link)(struct inode *, struct inode *, const struct qstr *);\n\tint (*symlink)(struct inode *, struct dentry *, struct folio *, unsigned int, struct iattr *);\n\tstruct dentry * (*mkdir)(struct inode *, struct dentry *, struct iattr *);\n\tint (*rmdir)(struct inode *, const struct qstr *);\n\tint (*readdir)(struct nfs_readdir_arg *, struct nfs_readdir_res *);\n\tint (*mknod)(struct inode *, struct dentry *, struct iattr *, dev_t);\n\tint (*statfs)(struct nfs_server *, struct nfs_fh *, struct nfs_fsstat *);\n\tint (*fsinfo)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*pathconf)(struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *);\n\tint (*set_capabilities)(struct nfs_server *, struct nfs_fh *);\n\tint (*decode_dirent)(struct xdr_stream *, struct nfs_entry *, bool);\n\tint (*pgio_rpc_prepare)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*read_setup)(struct nfs_pgio_header *, struct rpc_message *);\n\tint (*read_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*write_setup)(struct nfs_pgio_header *, struct rpc_message *, struct rpc_clnt **);\n\tint (*write_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*commit_setup)(struct nfs_commit_data *, struct rpc_message *, struct rpc_clnt **);\n\tvoid (*commit_rpc_prepare)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*commit_done)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tint (*lock_check_bounds)(const struct file_lock *);\n\tvoid (*clear_acl_cache)(struct inode *);\n\tvoid (*close_context)(struct nfs_open_context *, int);\n\tstruct inode * (*open_context)(struct inode *, struct nfs_open_context *, int, struct iattr *, int *);\n\tint (*have_delegation)(struct inode *, fmode_t, int);\n\tvoid (*return_delegation)(struct inode *);\n\tstruct nfs_client * (*alloc_client)(const struct nfs_client_initdata *);\n\tstruct nfs_client * (*init_client)(struct nfs_client *, const struct nfs_client_initdata *);\n\tvoid (*free_client)(struct nfs_client *);\n\tstruct nfs_server * (*create_server)(struct fs_context *);\n\tstruct nfs_server * (*clone_server)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, rpc_authflavor_t);\n\tint (*discover_trunking)(struct nfs_server *, struct nfs_fh *);\n\tvoid (*enable_swap)(struct inode *);\n\tvoid (*disable_swap)(struct inode *);\n};\n\nstruct rpc_task_setup;\n\nstruct nfs_rw_ops {\n\tstruct nfs_pgio_header * (*rw_alloc_header)(void);\n\tvoid (*rw_free_header)(struct nfs_pgio_header *);\n\tint (*rw_done)(struct rpc_task *, struct nfs_pgio_header *, struct inode *);\n\tvoid (*rw_result)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*rw_initiate)(struct nfs_pgio_header *, struct rpc_message *, const struct nfs_rpc_ops *, struct rpc_task_setup *, int);\n};\n\nstruct nfs_seqid {\n\tstruct nfs_seqid_counter *sequence;\n\tstruct list_head list;\n\tstruct rpc_task *task;\n};\n\nstruct nlm_host;\n\nstruct nfs_server {\n\tstruct nfs_client *nfs_client;\n\tstruct list_head client_link;\n\tstruct list_head master_link;\n\tstruct rpc_clnt *client;\n\tstruct rpc_clnt *client_acl;\n\tstruct nlm_host *nlm_host;\n\tstruct nfs_iostats *io_stats;\n\twait_queue_head_t write_congestion_wait;\n\tatomic_long_t writeback;\n\tunsigned int write_congested;\n\tunsigned int flags;\n\tunsigned int automount_inherit;\n\tunsigned int caps;\n\tlong: 32;\n\t__u64 fattr_valid;\n\tunsigned int rsize;\n\tunsigned int rpages;\n\tunsigned int wsize;\n\tunsigned int wtmult;\n\tunsigned int dtsize;\n\tshort unsigned int port;\n\tunsigned int bsize;\n\tunsigned int gxasize;\n\tunsigned int sxasize;\n\tunsigned int lxasize;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namelen;\n\tunsigned int options;\n\tunsigned int clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\tstruct nfs_fsid fsid;\n\tint s_sysfs_id;\n\tlong: 32;\n\t__u64 maxfilesize;\n\tlong unsigned int mount_time;\n\tstruct super_block *super;\n\tdev_t s_dev;\n\tstruct nfs_auth_info auth_info;\n\tu32 fh_expire_type;\n\tu32 pnfs_blksize;\n\tu32 attr_bitmask[3];\n\tu32 attr_bitmask_nl[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 cache_consistency_bitmask[3];\n\tu32 acl_bitmask;\n\tstruct pnfs_layoutdriver_type *pnfs_curr_ld;\n\tstruct rpc_wait_queue roc_rpcwaitq;\n\tstruct rb_root state_owners;\n\tatomic64_t owner_ctr;\n\tstruct list_head state_owners_lru;\n\tstruct list_head layouts;\n\tstruct list_head delegations;\n\tspinlock_t delegations_lock;\n\tstruct list_head delegations_return;\n\tstruct list_head delegations_lru;\n\tstruct list_head delegations_delayed;\n\tatomic_long_t nr_active_delegations;\n\tunsigned int delegation_hash_mask;\n\tstruct hlist_head *delegation_hash_table;\n\tstruct list_head ss_copies;\n\tstruct list_head ss_src_copies;\n\tlong unsigned int delegation_flags;\n\tlong unsigned int delegation_gen;\n\tlong unsigned int mig_gen;\n\tlong unsigned int mig_status;\n\tvoid (*destroy)(struct nfs_server *);\n\tatomic_t active;\n\tstruct __kernel_sockaddr_storage mountd_address;\n\tsize_t mountd_addrlen;\n\tu32 mountd_version;\n\tshort unsigned int mountd_port;\n\tshort unsigned int mountd_protocol;\n\tstruct rpc_wait_queue uoc_rpcwaitq;\n\tunsigned int read_hdrsize;\n\tconst struct cred *cred;\n\tbool has_sec_mnt_opts;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_setaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_setaclres {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs_setattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct iattr *iap;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n};\n\nstruct nfs_setattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs_ssc_client_ops {\n\tvoid (*sco_sb_deactive)(struct super_block *);\n};\n\nstruct nfs_ssc_client_ops_tbl {\n\tconst struct nfs4_ssc_client_ops *ssc_nfs4_ops;\n\tconst struct nfs_ssc_client_ops *ssc_nfs_ops;\n};\n\nstruct rpc_version;\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct nfs_subversion {\n\tstruct module *owner;\n\tstruct file_system_type *nfs_fs;\n\tconst struct rpc_version *rpc_vers;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tconst struct super_operations *sops;\n\tconst struct xattr_handler * const *xattr;\n};\n\nstruct nfs_unlinkdata {\n\tstruct nfs_removeargs args;\n\tstruct nfs_removeres res;\n\tstruct dentry *dentry;\n\twait_queue_head_t wq;\n\tconst struct cred *cred;\n\tlong: 32;\n\tstruct nfs_fattr dir_attr;\n\tlong int timeout;\n\tlong: 32;\n};\n\nstruct xdr_array2_desc;\n\ntypedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *, void *);\n\nstruct xdr_array2_desc {\n\tunsigned int elem_size;\n\tunsigned int array_len;\n\tunsigned int array_maxlen;\n\txdr_xcode_elem_t xcode;\n};\n\nstruct nfsacl_decode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n};\n\nstruct nfsacl_encode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n\tint typeflag;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct nfsacl_simple_acl {\n\tstruct posix_acl_hdr acl;\n\tstruct posix_acl_entry ace[4];\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tlong: 32;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tlong: 32;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tlong: 32;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhlist_head;\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlm_cookie {\n\tunsigned char data[32];\n\tunsigned int len;\n};\n\nstruct nlm_lock {\n\tchar *caller;\n\tunsigned int len;\n\tstruct nfs_fh fh;\n\tstruct xdr_netobj oh;\n\tu32 svid;\n\tu64 lock_start;\n\tu64 lock_len;\n\tstruct file_lock fl;\n};\n\nstruct nlm_args {\n\tstruct nlm_cookie cookie;\n\tlong: 32;\n\tstruct nlm_lock lock;\n\tu32 block;\n\tu32 reclaim;\n\tu32 state;\n\tu32 monitor;\n\tu32 fsm_access;\n\tu32 fsm_mode;\n};\n\nstruct nlm_rqst;\n\nstruct nlm_file;\n\nstruct nlm_block {\n\tstruct kref b_count;\n\tstruct list_head b_list;\n\tstruct list_head b_flist;\n\tstruct nlm_rqst *b_call;\n\tstruct svc_serv *b_daemon;\n\tstruct nlm_host *b_host;\n\tlong unsigned int b_when;\n\tunsigned int b_id;\n\tunsigned char b_granted;\n\tstruct nlm_file *b_file;\n\tstruct cache_req *b_cache_req;\n\tstruct cache_deferred_req *b_deferred_req;\n\tunsigned int b_flags;\n};\n\nstruct nlm_share;\n\nstruct nlm_file {\n\tstruct hlist_node f_list;\n\tstruct nfs_fh f_handle;\n\tstruct file *f_file[2];\n\tstruct nlm_share *f_shares;\n\tstruct list_head f_blocks;\n\tunsigned int f_locks;\n\tunsigned int f_count;\n\tstruct mutex f_mutex;\n};\n\nstruct nsm_handle;\n\nstruct nlm_host {\n\tstruct hlist_node h_hash;\n\tstruct __kernel_sockaddr_storage h_addr;\n\tsize_t h_addrlen;\n\tstruct __kernel_sockaddr_storage h_srcaddr;\n\tsize_t h_srcaddrlen;\n\tstruct rpc_clnt *h_rpcclnt;\n\tchar *h_name;\n\tu32 h_version;\n\tshort unsigned int h_proto;\n\tshort unsigned int h_reclaiming: 1;\n\tshort unsigned int h_server: 1;\n\tshort unsigned int h_noresvport: 1;\n\tshort unsigned int h_inuse: 1;\n\twait_queue_head_t h_gracewait;\n\tstruct rw_semaphore h_rwsem;\n\tu32 h_state;\n\tu32 h_nsmstate;\n\tu32 h_pidcount;\n\trefcount_t h_count;\n\tstruct mutex h_mutex;\n\tlong unsigned int h_nextrebind;\n\tlong unsigned int h_expires;\n\tstruct list_head h_lockowners;\n\tspinlock_t h_lock;\n\tstruct list_head h_granted;\n\tstruct list_head h_reclaim;\n\tstruct nsm_handle *h_nsmhandle;\n\tchar *h_addrbuf;\n\tstruct net *net;\n\tconst struct cred *h_cred;\n\tchar nodename[65];\n\tconst struct nlmclnt_operations *h_nlmclnt_ops;\n};\n\nstruct nlm_lockowner {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct nlm_host *host;\n\tfl_owner_t owner;\n\tuint32_t pid;\n};\n\nstruct nlm_lookup_host_info {\n\tconst int server;\n\tconst struct sockaddr *sap;\n\tconst size_t salen;\n\tconst short unsigned int protocol;\n\tconst u32 version;\n\tconst char *hostname;\n\tconst size_t hostname_len;\n\tconst int noresvport;\n\tstruct net *net;\n\tconst struct cred *cred;\n};\n\nstruct nsm_private {\n\tunsigned char data[16];\n};\n\nstruct nlm_reboot {\n\tchar *mon;\n\tunsigned int len;\n\tu32 state;\n\tstruct nsm_private priv;\n};\n\nstruct nlm_res {\n\tstruct nlm_cookie cookie;\n\t__be32 status;\n\tstruct nlm_lock lock;\n};\n\nstruct nlm_rqst {\n\trefcount_t a_count;\n\tunsigned int a_flags;\n\tstruct nlm_host *a_host;\n\tlong: 32;\n\tstruct nlm_args a_args;\n\tstruct nlm_res a_res;\n\tstruct nlm_block *a_block;\n\tunsigned int a_retries;\n\tu8 a_owner[74];\n\tvoid *a_callback_data;\n};\n\nstruct nlm_share {\n\tstruct nlm_share *s_next;\n\tstruct nlm_host *s_host;\n\tstruct nlm_file *s_file;\n\tstruct xdr_netobj s_owner;\n\tu32 s_access;\n\tu32 s_mode;\n};\n\nstruct nlm_wait {\n\tstruct list_head b_list;\n\twait_queue_head_t b_wait;\n\tstruct nlm_host *b_host;\n\tstruct file_lock *b_lock;\n\t__be32 b_status;\n};\n\nstruct nlmclnt_initdata {\n\tconst char *hostname;\n\tconst struct sockaddr *address;\n\tsize_t addrlen;\n\tshort unsigned int protocol;\n\tu32 nfs_version;\n\tint noresvport;\n\tstruct net *net;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tconst struct cred *cred;\n};\n\nstruct nlmclnt_operations {\n\tvoid (*nlmclnt_alloc_call)(void *);\n\tbool (*nlmclnt_unlock_prepare)(struct rpc_task *, void *);\n\tvoid (*nlmclnt_release_call)(void *);\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nlmsvc_binding {\n\t__be32 (*fopen)(struct svc_rqst *, struct nfs_fh *, struct file **, int);\n\tvoid (*fclose)(struct file *);\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct nsm_args {\n\tstruct nsm_private *priv;\n\tu32 prog;\n\tu32 vers;\n\tu32 proc;\n\tchar *mon_name;\n\tconst char *nodename;\n};\n\nstruct nsm_handle {\n\tstruct list_head sm_link;\n\trefcount_t sm_count;\n\tchar *sm_mon_name;\n\tchar *sm_name;\n\tstruct __kernel_sockaddr_storage sm_addr;\n\tsize_t sm_addrlen;\n\tunsigned int sm_monitored: 1;\n\tunsigned int sm_sticky: 1;\n\tstruct nsm_private sm_priv;\n\tchar sm_addrbuf[51];\n};\n\nstruct nsm_res {\n\tu32 status;\n\tu32 state;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n};\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tlong: 32;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\tlong: 32;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\tlong: 32;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_t drops1;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct nvmem_cell_entry;\n\nstruct nvmem_cell {\n\tstruct nvmem_cell_entry *entry;\n\tconst char *id;\n\tint index;\n};\n\ntypedef int (*nvmem_cell_post_process_t)(void *, const char *, int, unsigned int, void *, size_t);\n\nstruct nvmem_cell_entry {\n\tconst char *name;\n\tint offset;\n\tsize_t raw_len;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n\tstruct device_node *np;\n\tstruct nvmem_device *nvmem;\n\tstruct list_head node;\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tsize_t raw_len;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n\tstruct device_node *np;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n};\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nstruct nvmem_keepout;\n\nstruct nvmem_layout;\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tbool add_legacy_fixed_of_cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool ignore_wp;\n\tstruct nvmem_layout *layout;\n\tstruct device_node *of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device {\n\tstruct module *owner;\n\tlong: 32;\n\tstruct device dev;\n\tstruct list_head node;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tstruct nvmem_layout *layout;\n\tvoid *priv;\n\tbool sysfs_cells_populated;\n\tlong: 32;\n};\n\nstruct nvmem_keepout {\n\tunsigned int start;\n\tunsigned int end;\n\tunsigned char value;\n};\n\nstruct nvmem_layout {\n\tstruct device dev;\n\tstruct nvmem_device *nvmem;\n\tint (*add_cells)(struct nvmem_layout *);\n};\n\nstruct nvmem_layout_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct nvmem_layout *);\n\tvoid (*remove)(struct nvmem_layout *);\n};\n\nstruct o2_host {\n\tu8 dll_adjust_count;\n};\n\nstruct obj_cgroup {\n\tstruct percpu_ref refcnt;\n\tstruct mem_cgroup *memcg;\n\tatomic_t nr_charged_bytes;\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct obj_stock_pcp {\n\tlocal_trylock_t lock;\n\tunsigned int nr_bytes;\n\tstruct obj_cgroup *cached_objcg;\n\tstruct pglist_data *cached_pgdat;\n\tint nr_slab_reclaimable_b;\n\tint nr_slab_unreclaimable_b;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct ocelot_vcap_block {\n\tstruct list_head rules;\n\tint count;\n};\n\nstruct ocelot_vcap_policer {\n\tstruct list_head pol_list;\n\tu16 base;\n\tu16 max;\n\tu16 base2;\n\tu16 max2;\n};\n\nstruct ocelot_psfp_list {\n\tstruct list_head stream_list;\n\tstruct list_head sfi_list;\n\tstruct list_head sgi_list;\n\tstruct mutex lock;\n};\n\nstruct ptp_pin_desc;\n\nstruct system_device_crosststamp;\n\nstruct ptp_clock_request;\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[32];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint n_per_lp;\n\tint pps;\n\tunsigned int supported_perout_flags;\n\tunsigned int supported_extts_flags;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\ts32 (*getmaxphase)(struct ptp_clock_info *);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*getcycles64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n\tint (*perout_loopback)(struct ptp_clock_info *, unsigned int, int);\n};\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct ocelot_ops;\n\nstruct regmap_field;\n\nstruct ocelot_port;\n\nstruct vcap_props;\n\nstruct ocelot_mirror;\n\nstruct ptp_clock;\n\nstruct ocelot_mm_state;\n\nstruct ocelot_fdma;\n\nstruct ocelot {\n\tstruct device *dev;\n\tstruct devlink *devlink;\n\tstruct devlink_port *devlink_ports;\n\tconst struct ocelot_ops *ops;\n\tstruct regmap *targets[14];\n\tstruct regmap_field *regfields[60];\n\tconst u32 * const *map;\n\tstruct list_head stats_regions;\n\tspinlock_t inj_lock;\n\tspinlock_t xtr_lock;\n\tu32 pool_size[4];\n\tint packet_buffer_size;\n\tint num_frame_refs;\n\tint num_mact_rows;\n\tstruct ocelot_port **ports;\n\tu8 base_mac[6];\n\tstruct list_head vlans;\n\tstruct list_head traps;\n\tstruct list_head lag_fdbs;\n\tint num_flooding_pgids;\n\tu8 num_phys_ports;\n\tint npi;\n\tenum ocelot_tag_prefix npi_inj_prefix;\n\tenum ocelot_tag_prefix npi_xtr_prefix;\n\tlong unsigned int bridges;\n\tstruct list_head multicast;\n\tstruct list_head pgids;\n\tstruct list_head dummy_rules;\n\tstruct ocelot_vcap_block block[3];\n\tstruct ocelot_vcap_policer vcap_pol;\n\tstruct vcap_props *vcap;\n\tstruct ocelot_mirror *mirror;\n\tstruct ocelot_psfp_list psfp;\n\tstruct delayed_work stats_work;\n\tstruct workqueue_struct *stats_queue;\n\tspinlock_t stats_lock;\n\tu64 *stats;\n\tstruct mutex stat_view_lock;\n\tstruct mutex mact_lock;\n\tstruct mutex fwd_domain_lock;\n\tstruct workqueue_struct *owq;\n\tu8 ptp: 1;\n\tu8 mm_supported: 1;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_info;\n\tunsigned int ptp_skbs_in_flight;\n\tspinlock_t ts_id_lock;\n\tspinlock_t ptp_clock_lock;\n\tstruct ptp_pin_desc ptp_pins[4];\n\tstruct ocelot_mm_state *mm;\n\tstruct ocelot_fdma *fdma;\n};\n\nstruct ocelot_bridge_vlan {\n\tu16 vid;\n\tlong unsigned int portmask;\n\tlong unsigned int untagged;\n\tstruct list_head list;\n};\n\nstruct ocelot_dump_ctx {\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tint idx;\n};\n\nstruct ocelot_fdma_tx_buf {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma_addr;\n};\n\nstruct ocelot_fdma_dcb;\n\nstruct ocelot_fdma_tx_ring {\n\tstruct ocelot_fdma_dcb *dcbs;\n\tdma_addr_t dcbs_dma;\n\tstruct ocelot_fdma_tx_buf bufs[128];\n\tspinlock_t xmit_lock;\n\tu16 next_to_clean;\n\tu16 next_to_use;\n};\n\nstruct ocelot_fdma_rx_buf {\n\tstruct page *page;\n\tu32 page_offset;\n\tdma_addr_t dma_addr;\n};\n\nstruct ocelot_fdma_rx_ring {\n\tstruct ocelot_fdma_dcb *dcbs;\n\tdma_addr_t dcbs_dma;\n\tstruct ocelot_fdma_rx_buf bufs[512];\n\tstruct sk_buff *skb;\n\tu16 next_to_clean;\n\tu16 next_to_use;\n\tu16 next_to_alloc;\n};\n\nstruct ocelot_fdma {\n\tint irq;\n\tstruct net_device *ndev;\n\tstruct ocelot_fdma_dcb *dcbs_base;\n\tdma_addr_t dcbs_dma_base;\n\tstruct ocelot_fdma_tx_ring tx_ring;\n\tstruct ocelot_fdma_rx_ring rx_ring;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tstruct ocelot *ocelot;\n\tlong: 32;\n};\n\nstruct ocelot_fdma_dcb {\n\tu32 llp;\n\tu32 datap;\n\tu32 datal;\n\tu32 stat;\n};\n\nstruct ocelot_ipv4 {\n\tu8 addr[4];\n};\n\nstruct ocelot_irq_work {\n\tstruct work_struct irq_work;\n\tstruct irq_desc *irq_desc;\n};\n\nstruct ocelot_lag_fdb {\n\tunsigned char addr[6];\n\tu16 vid;\n\tstruct net_device *bond;\n\tstruct list_head list;\n};\n\nstruct ocelot_mact_entry {\n\tu8 mac[6];\n\tu16 vid;\n\tenum macaccess_entry_type type;\n};\n\nstruct ocelot_mact_work_ctx {\n\tstruct work_struct work;\n\tstruct ocelot *ocelot;\n\tenum ocelot_action_type type;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char addr[6];\n\t\t\tu16 vid;\n\t\t\tenum macaccess_entry_type entry_type;\n\t\t\tint pgid;\n\t\t} learn;\n\t\tstruct {\n\t\t\tunsigned char addr[6];\n\t\t\tu16 vid;\n\t\t} forget;\n\t};\n};\n\nstruct pinctrl_pin_desc;\n\nstruct pinctrl_ops;\n\nstruct pinmux_ops;\n\nstruct pinconf_ops;\n\nstruct pinconf_generic_params;\n\nstruct pin_config_item;\n\nstruct pinctrl_desc {\n\tconst char *name;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct pinctrl_ops *pctlops;\n\tconst struct pinmux_ops *pmxops;\n\tconst struct pinconf_ops *confops;\n\tstruct module *owner;\n\tunsigned int num_custom_params;\n\tconst struct pinconf_generic_params *custom_params;\n\tconst struct pin_config_item *custom_conf_items;\n\tbool link_consumers;\n};\n\nstruct ocelot_pincfg_data {\n\tu8 pd_bit;\n\tu8 pu_bit;\n\tu8 drive_bits;\n\tu8 schmitt_bit;\n};\n\nstruct ocelot_match_data {\n\tstruct pinctrl_desc desc;\n\tstruct ocelot_pincfg_data pincfg_data;\n\tunsigned int n_alt_modes;\n};\n\nstruct ocelot_mirror {\n\trefcount_t refcount;\n\tint to;\n};\n\nstruct ocelot_mm_state {\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tu8 preemptible_tcs;\n\tu8 active_preemptible_tcs;\n};\n\nstruct ocelot_pgid;\n\nstruct ocelot_multicast {\n\tstruct list_head list;\n\tenum macaccess_entry_type entry_type;\n\tunsigned char addr[6];\n\tu16 vid;\n\tu16 ports;\n\tstruct ocelot_pgid *pgid;\n};\n\nstruct ocelot_ops {\n\tstruct net_device * (*port_to_netdev)(struct ocelot *, int);\n\tint (*netdev_to_port)(struct net_device *);\n\tint (*reset)(struct ocelot *);\n\tu16 (*wm_enc)(u16);\n\tu16 (*wm_dec)(u16);\n\tvoid (*wm_stat)(u32, u32 *, u32 *);\n\tvoid (*psfp_init)(struct ocelot *);\n\tint (*psfp_filter_add)(struct ocelot *, int, struct flow_cls_offload *);\n\tint (*psfp_filter_del)(struct ocelot *, struct flow_cls_offload *);\n\tint (*psfp_stats_get)(struct ocelot *, struct flow_cls_offload *, struct flow_stats *);\n\tvoid (*cut_through_fwd)(struct ocelot *);\n\tvoid (*tas_clock_adjust)(struct ocelot *);\n\tvoid (*tas_guard_bands_update)(struct ocelot *, int);\n\tvoid (*update_stats)(struct ocelot *);\n};\n\nstruct ocelot_pgid {\n\tlong unsigned int ports;\n\tint index;\n\trefcount_t refcount;\n\tstruct list_head list;\n};\n\nstruct ocelot_pin_caps {\n\tunsigned int pin;\n\tunsigned char functions[4];\n\tunsigned char a_functions[4];\n};\n\nstruct ocelot_pmx_func {\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct ocelot_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct gpio_chip gpio_chip;\n\tstruct regmap *map;\n\tstruct regmap *pincfg;\n\tstruct pinctrl_desc *desc;\n\tconst struct ocelot_pincfg_data *pincfg_data;\n\tstruct ocelot_pmx_func func[144];\n\tu8 stride;\n\tu8 altm_stride;\n\tstruct workqueue_struct *wq;\n};\n\nstruct ocelot_policer {\n\tu32 rate;\n\tu32 burst;\n};\n\nstruct tc_taprio_qopt_offload;\n\nstruct ocelot_ts_stats;\n\nstruct ocelot_port {\n\tstruct ocelot *ocelot;\n\tstruct regmap *target;\n\tstruct net_device *bond;\n\tstruct net_device *bridge;\n\tstruct ocelot_port *dsa_8021q_cpu;\n\tconst struct ocelot_bridge_vlan *pvid_vlan;\n\tstruct tc_taprio_qopt_offload *taprio;\n\tphy_interface_t phy_mode;\n\tstruct ocelot_ts_stats *ts_stats;\n\tstruct sk_buff_head tx_skbs;\n\tunsigned int trap_proto;\n\tu16 mrp_ring_id;\n\tu8 ptp_cmd;\n\tu8 index;\n\tu8 stp_state;\n\tbool vlan_aware;\n\tbool is_dsa_8021q_cpu;\n\tbool learn_ena;\n\tbool lag_tx_active;\n\tint bridge_num;\n\tint speed;\n};\n\nstruct ocelot_port_tc {\n\tbool block_shared;\n\tlong unsigned int offload_cnt;\n\tlong unsigned int ingress_mirred_id;\n\tlong unsigned int egress_mirred_id;\n\tlong unsigned int police_id;\n};\n\nstruct ocelot_port_private {\n\tstruct ocelot_port port;\n\tstruct net_device *dev;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tstruct ocelot_port_tc tc;\n};\n\nstruct reset_props;\n\nstruct ocelot_reset_context {\n\tvoid *base;\n\tstruct regmap *cpu_ctrl;\n\tconst struct reset_props *props;\n\tstruct notifier_block restart_handler;\n};\n\nstruct ocelot_skb_cb {\n\tstruct sk_buff *clone;\n\tunsigned int ptp_class;\n\tlong unsigned int ptp_tx_time;\n\tu32 tstamp_lo;\n\tu8 ptp_cmd;\n\tu8 ts_id;\n};\n\nstruct ocelot_stat_layout {\n\tenum ocelot_reg reg;\n\tchar name[32];\n};\n\nstruct ocelot_stats_region {\n\tstruct list_head node;\n\tenum ocelot_reg base;\n\tenum ocelot_stat first_stat;\n\tint count;\n\tu32 *buf;\n};\n\nstruct ocelot_ts_stats {\n\tu64 pkts;\n\tu64 onestep_pkts_unconfirmed;\n\tu64 lost;\n\tu64 err;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct ocelot_vcap_action {\n\tunion {\n\t\tstruct {\n\t\t\tenum ocelot_es0_tag push_outer_tag;\n\t\t\tenum ocelot_es0_tag push_inner_tag;\n\t\t\tenum ocelot_tag_tpid_sel tag_a_tpid_sel;\n\t\t\tint tag_a_vid_sel;\n\t\t\tint tag_a_pcp_sel;\n\t\t\tu16 vid_a_val;\n\t\t\tu8 pcp_a_val;\n\t\t\tu8 dei_a_val;\n\t\t\tenum ocelot_tag_tpid_sel tag_b_tpid_sel;\n\t\t\tint tag_b_vid_sel;\n\t\t\tint tag_b_pcp_sel;\n\t\t\tu16 vid_b_val;\n\t\t\tu8 pcp_b_val;\n\t\t\tu8 dei_b_val;\n\t\t};\n\t\tstruct {\n\t\t\tbool vid_replace_ena;\n\t\t\tu16 vid;\n\t\t\tbool vlan_pop_cnt_ena;\n\t\t\tint vlan_pop_cnt;\n\t\t\tbool pcp_dei_ena;\n\t\t\tu8 pcp;\n\t\t\tu8 dei;\n\t\t\tbool qos_ena;\n\t\t\tu8 qos_val;\n\t\t\tu8 pag_override_mask;\n\t\t\tu8 pag_val;\n\t\t};\n\t\tstruct {\n\t\t\tbool cpu_copy_ena;\n\t\t\tu8 cpu_qu_num;\n\t\t\tenum ocelot_mask_mode mask_mode;\n\t\t\tlong unsigned int port_mask;\n\t\t\tbool police_ena;\n\t\t\tbool mirror_ena;\n\t\t\tstruct ocelot_policer pol;\n\t\t\tu32 pol_ix;\n\t\t};\n\t};\n};\n\nstruct ocelot_vcap_id {\n\tlong unsigned int cookie;\n\tbool tc_offload;\n};\n\nstruct ocelot_vcap_stats {\n\tu64 bytes;\n\tu64 pkts;\n\tu64 used;\n};\n\nstruct ocelot_vcap_port {\n\tu8 value;\n\tu8 mask;\n};\n\nstruct ocelot_vcap_vid {\n\tu16 value;\n\tu16 mask;\n};\n\nstruct ocelot_vcap_u8 {\n\tu8 value[1];\n\tu8 mask[1];\n};\n\nstruct ocelot_vcap_key_vlan {\n\tstruct ocelot_vcap_vid vid;\n\tstruct ocelot_vcap_u8 pcp;\n\tenum ocelot_vcap_bit dei;\n\tenum ocelot_vcap_bit tagged;\n\tenum ocelot_vcap_bit tpid;\n};\n\nstruct ocelot_vcap_u48 {\n\tu8 value[6];\n\tu8 mask[6];\n};\n\nstruct ocelot_vcap_u16 {\n\tu8 value[2];\n\tu8 mask[2];\n};\n\nstruct ocelot_vcap_key_etype {\n\tstruct ocelot_vcap_u48 dmac;\n\tstruct ocelot_vcap_u48 smac;\n\tstruct ocelot_vcap_u16 etype;\n\tstruct ocelot_vcap_u16 data;\n};\n\nstruct ocelot_vcap_u32 {\n\tu8 value[4];\n\tu8 mask[4];\n};\n\nstruct ocelot_vcap_key_llc {\n\tstruct ocelot_vcap_u48 dmac;\n\tstruct ocelot_vcap_u48 smac;\n\tstruct ocelot_vcap_u32 llc;\n};\n\nstruct ocelot_vcap_u40 {\n\tu8 value[5];\n\tu8 mask[5];\n};\n\nstruct ocelot_vcap_key_snap {\n\tstruct ocelot_vcap_u48 dmac;\n\tstruct ocelot_vcap_u48 smac;\n\tstruct ocelot_vcap_u40 snap;\n};\n\nstruct ocelot_vcap_ipv4 {\n\tstruct ocelot_ipv4 value;\n\tstruct ocelot_ipv4 mask;\n};\n\nstruct ocelot_vcap_key_arp {\n\tstruct ocelot_vcap_u48 smac;\n\tenum ocelot_vcap_bit arp;\n\tenum ocelot_vcap_bit req;\n\tenum ocelot_vcap_bit unknown;\n\tenum ocelot_vcap_bit smac_match;\n\tenum ocelot_vcap_bit dmac_match;\n\tenum ocelot_vcap_bit length;\n\tenum ocelot_vcap_bit ip;\n\tenum ocelot_vcap_bit ethernet;\n\tstruct ocelot_vcap_ipv4 sip;\n\tstruct ocelot_vcap_ipv4 dip;\n};\n\nstruct ocelot_vcap_udp_tcp {\n\tu16 value;\n\tu16 mask;\n};\n\nstruct ocelot_vcap_key_ipv4 {\n\tenum ocelot_vcap_bit ttl;\n\tenum ocelot_vcap_bit fragment;\n\tenum ocelot_vcap_bit options;\n\tstruct ocelot_vcap_u8 ds;\n\tstruct ocelot_vcap_u8 proto;\n\tstruct ocelot_vcap_ipv4 sip;\n\tstruct ocelot_vcap_ipv4 dip;\n\tstruct ocelot_vcap_u48 data;\n\tstruct ocelot_vcap_udp_tcp sport;\n\tstruct ocelot_vcap_udp_tcp dport;\n\tenum ocelot_vcap_bit tcp_fin;\n\tenum ocelot_vcap_bit tcp_syn;\n\tenum ocelot_vcap_bit tcp_rst;\n\tenum ocelot_vcap_bit tcp_psh;\n\tenum ocelot_vcap_bit tcp_ack;\n\tenum ocelot_vcap_bit tcp_urg;\n\tenum ocelot_vcap_bit sip_eq_dip;\n\tenum ocelot_vcap_bit sport_eq_dport;\n\tenum ocelot_vcap_bit seq_zero;\n};\n\nstruct ocelot_vcap_u128 {\n\tu8 value[16];\n\tu8 mask[16];\n};\n\nstruct ocelot_vcap_key_ipv6 {\n\tstruct ocelot_vcap_u8 proto;\n\tstruct ocelot_vcap_u128 sip;\n\tstruct ocelot_vcap_u128 dip;\n\tenum ocelot_vcap_bit ttl;\n\tstruct ocelot_vcap_u8 ds;\n\tstruct ocelot_vcap_u48 data;\n\tstruct ocelot_vcap_udp_tcp sport;\n\tstruct ocelot_vcap_udp_tcp dport;\n\tenum ocelot_vcap_bit tcp_fin;\n\tenum ocelot_vcap_bit tcp_syn;\n\tenum ocelot_vcap_bit tcp_rst;\n\tenum ocelot_vcap_bit tcp_psh;\n\tenum ocelot_vcap_bit tcp_ack;\n\tenum ocelot_vcap_bit tcp_urg;\n\tenum ocelot_vcap_bit sip_eq_dip;\n\tenum ocelot_vcap_bit sport_eq_dport;\n\tenum ocelot_vcap_bit seq_zero;\n};\n\nstruct ocelot_vcap_filter {\n\tstruct list_head list;\n\tenum ocelot_vcap_filter_type type;\n\tint block_id;\n\tint goto_target;\n\tint lookup;\n\tu8 pag;\n\tu16 prio;\n\tstruct ocelot_vcap_id id;\n\tstruct ocelot_vcap_action action;\n\tlong: 32;\n\tstruct ocelot_vcap_stats stats;\n\tbool take_ts;\n\tbool is_trap;\n\tlong unsigned int ingress_port_mask;\n\tstruct ocelot_vcap_port ingress_port;\n\tstruct ocelot_vcap_port egress_port;\n\tenum ocelot_vcap_bit dmac_mc;\n\tenum ocelot_vcap_bit dmac_bc;\n\tstruct ocelot_vcap_key_vlan vlan;\n\tenum ocelot_vcap_key_type key_type;\n\tunion {\n\t\tstruct ocelot_vcap_key_etype etype;\n\t\tstruct ocelot_vcap_key_llc llc;\n\t\tstruct ocelot_vcap_key_snap snap;\n\t\tstruct ocelot_vcap_key_arp arp;\n\t\tstruct ocelot_vcap_key_ipv4 ipv4;\n\t\tstruct ocelot_vcap_key_ipv6 ipv6;\n\t} key;\n};\n\nstruct ocelot_vcap_u64 {\n\tu8 value[8];\n\tu8 mask[8];\n};\n\nstruct of_bus {\n\tvoid (*count_cells)(const void *, int, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n};\n\nstruct of_bus___2 {\n\tconst char *name;\n\tconst char *addresses;\n\tint (*match)(struct device_node *);\n\tvoid (*count_cells)(struct device_node *, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n\tint flag_cells;\n\tunsigned int (*get_flags)(const __be32 *);\n};\n\nstruct of_clk_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n\tstruct clk * (*get)(struct of_phandle_args *, void *);\n\tstruct clk_hw * (*get_hw)(struct of_phandle_args *, void *);\n\tvoid *data;\n};\n\nstruct of_dev_auxdata {\n\tchar *compatible;\n\tresource_size_t phys_addr;\n\tchar *name;\n\tvoid *platform_data;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_dma {\n\tstruct list_head of_dma_controllers;\n\tstruct device_node *of_node;\n\tstruct dma_chan * (*of_dma_xlate)(struct of_phandle_args *, struct of_dma *);\n\tvoid * (*of_dma_route_allocate)(struct of_phandle_args *, struct of_dma *);\n\tstruct dma_router *dma_router;\n\tvoid *of_dma_data;\n};\n\nstruct of_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct of_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct device_node *local_node;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct of_imap_item {\n\tstruct of_phandle_args parent_args;\n\tu32 child_imap_count;\n\tu32 child_imap[16];\n};\n\nstruct of_imap_parser {\n\tstruct device_node *node;\n\tconst __be32 *imap;\n\tconst __be32 *imap_end;\n\tu32 parent_offset;\n};\n\ntypedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *);\n\nstruct of_intc_desc {\n\tstruct list_head list;\n\tof_irq_init_cb_t irq_init_cb;\n\tstruct device_node *dev;\n\tstruct device_node *interrupt_parent;\n};\n\nstruct of_mmc_spi {\n\tstruct mmc_spi_platform_data pdata;\n\tint detect_irq;\n};\n\nstruct of_pci_range {\n\tunion {\n\t\tu64 pci_addr;\n\t\tu64 bus_addr;\n\t};\n\tu64 cpu_addr;\n\tu64 parent_bus_addr;\n\tu64 size;\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct of_pci_range_parser {\n\tstruct device_node *node;\n\tconst struct of_bus___2 *bus;\n\tconst __be32 *range;\n\tconst __be32 *end;\n\tint na;\n\tint ns;\n\tint pna;\n\tbool dma;\n};\n\nstruct of_phandle_iterator {\n\tconst char *cells_name;\n\tint cell_count;\n\tconst struct device_node *parent;\n\tconst __be32 *list_end;\n\tconst __be32 *phandle_end;\n\tconst __be32 *cur;\n\tuint32_t cur_count;\n\tphandle phandle;\n\tstruct device_node *node;\n};\n\nstruct of_regulator_match {\n\tconst char *name;\n\tvoid *driver_data;\n\tstruct regulator_init_data *init_data;\n\tstruct device_node *of_node;\n\tconst struct regulator_desc *desc;\n};\n\nstruct of_rename_gpio {\n\tconst char *con_id;\n\tconst char *legacy_id;\n\tconst char *compatible;\n};\n\nstruct of_serial_info {\n\tstruct clk *clk;\n\tstruct clk *bus_clk;\n\tstruct reset_control *rst;\n\tint type;\n\tint line;\n\tstruct notifier_block clk_notifier;\n};\n\nstruct of_timer_base {\n\tvoid *base;\n\tconst char *name;\n\tint index;\n};\n\nstruct of_timer_clk {\n\tstruct clk *clk;\n\tconst char *name;\n\tint index;\n\tlong unsigned int rate;\n\tlong unsigned int period;\n};\n\nstruct of_timer_irq {\n\tint irq;\n\tint index;\n\tconst char *name;\n\tlong unsigned int flags;\n\tirq_handler_t handler;\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nstruct ohci_driver_overrides {\n\tconst char *product_desc;\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n};\n\nstruct ohci_hcca {\n\t__hc32 int_table[32];\n\t__hc32 frame_no;\n\t__hc32 done_head;\n\tu8 reserved_for_hc[116];\n\tu8 what[4];\n};\n\nstruct ohci_regs;\n\nstruct ohci_hcd {\n\tspinlock_t lock;\n\tstruct ohci_regs *regs;\n\tstruct ohci_hcca *hcca;\n\tdma_addr_t hcca_dma;\n\tstruct ed *ed_rm_list;\n\tstruct ed *ed_bulktail;\n\tstruct ed *ed_controltail;\n\tstruct ed *periodic[32];\n\tvoid (*start_hnp)(struct ohci_hcd *);\n\tstruct dma_pool *td_cache;\n\tstruct dma_pool *ed_cache;\n\tstruct td *td_hash[64];\n\tstruct td *dl_start;\n\tstruct td *dl_end;\n\tstruct list_head pending;\n\tstruct list_head eds_in_use;\n\tenum ohci_rh_state rh_state;\n\tint num_ports;\n\tint load[32];\n\tu32 hc_control;\n\tlong unsigned int next_statechange;\n\tu32 fminterval;\n\tunsigned int autostop: 1;\n\tunsigned int working: 1;\n\tunsigned int restart_work: 1;\n\tlong unsigned int flags;\n\tunsigned int prev_frame_no;\n\tunsigned int wdh_cnt;\n\tunsigned int prev_wdh_cnt;\n\tu32 prev_donehead;\n\tstruct timer_list io_watchdog;\n\tstruct work_struct nec_work;\n\tstruct dentry *debug_dir;\n\tlong: 32;\n\tlong unsigned int priv[0];\n};\n\nstruct ohci_platform_priv {\n\tstruct clk *clks[4];\n\tstruct reset_control *resets;\n};\n\nstruct ohci_roothub_regs {\n\t__hc32 a;\n\t__hc32 b;\n\t__hc32 status;\n\t__hc32 portstatus[15];\n};\n\nstruct ohci_regs {\n\t__hc32 revision;\n\t__hc32 control;\n\t__hc32 cmdstatus;\n\t__hc32 intrstatus;\n\t__hc32 intrenable;\n\t__hc32 intrdisable;\n\t__hc32 hcca;\n\t__hc32 ed_periodcurrent;\n\t__hc32 ed_controlhead;\n\t__hc32 ed_controlcurrent;\n\t__hc32 ed_bulkhead;\n\t__hc32 ed_bulkcurrent;\n\t__hc32 donehead;\n\t__hc32 fminterval;\n\t__hc32 fmremaining;\n\t__hc32 fmnumber;\n\t__hc32 periodicstart;\n\t__hc32 lsthresh;\n\tstruct ohci_roothub_regs roothub;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tlong: 32;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct old_timex32 {\n\tu32 modes;\n\ts32 offset;\n\ts32 freq;\n\ts32 maxerror;\n\ts32 esterror;\n\ts32 status;\n\ts32 constant;\n\ts32 precision;\n\ts32 tolerance;\n\tstruct old_timeval32 time;\n\ts32 tick;\n\ts32 ppsfreq;\n\ts32 jitter;\n\ts32 shift;\n\ts32 stabil;\n\ts32 jitcnt;\n\ts32 calcnt;\n\ts32 errcnt;\n\ts32 stbcnt;\n\ts32 tai;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct old_utimbuf32 {\n\told_time32_t actime;\n\told_time32_t modtime;\n};\n\nstruct old_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n};\n\nstruct oldold_utsname {\n\tchar sysname[9];\n\tchar nodename[9];\n\tchar release[9];\n\tchar version[9];\n\tchar machine[9];\n};\n\nstruct static_key_true;\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct onfi_ext_ecc_info {\n\tu8 ecc_bits;\n\tu8 codeword_size;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 reserved[2];\n};\n\nstruct onfi_ext_section {\n\tu8 type;\n\tu8 length;\n};\n\nstruct onfi_ext_param_page {\n\t__le16 crc;\n\tu8 sig[4];\n\tu8 reserved0[10];\n\tstruct onfi_ext_section sections[8];\n};\n\nstruct onfi_params {\n\tint version;\n\tu16 tPROG;\n\tu16 tBERS;\n\tu16 tR;\n\tu16 tCCS;\n\tbool fast_tCAD;\n\tu16 sdr_timing_modes;\n\tu16 nvddr_timing_modes;\n\tu16 vendor_revision;\n\tu8 vendor[88];\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\nstruct otp_info {\n\t__u32 start;\n\t__u32 length;\n\t__u32 locked;\n};\n\nstruct ovl_cache_entry {\n\tunsigned int len;\n\tunsigned int type;\n\tu64 real_ino;\n\tu64 ino;\n\tstruct list_head l_node;\n\tstruct rb_node node;\n\tstruct ovl_cache_entry *next_maybe_whiteout;\n\tbool is_upper;\n\tbool is_whiteout;\n\tbool check_xwhiteout;\n\tconst char *c_name;\n\tint c_len;\n\tchar name[0];\n\tlong: 32;\n};\n\nstruct ovl_cattr {\n\tdev_t rdev;\n\tumode_t mode;\n\tconst char *link;\n\tstruct dentry *hardlink;\n};\n\nstruct ovl_config {\n\tchar *upperdir;\n\tchar *workdir;\n\tchar **lowerdirs;\n\tbool default_permissions;\n\tint redirect_mode;\n\tint verity_mode;\n\tbool index;\n\tint uuid;\n\tbool nfs_export;\n\tint xino;\n\tbool metacopy;\n\tbool userxattr;\n\tbool ovl_volatile;\n};\n\nstruct ovl_fh;\n\nstruct ovl_copy_up_ctx {\n\tstruct dentry *parent;\n\tstruct dentry *dentry;\n\tstruct path lowerpath;\n\tstruct kstat stat;\n\tstruct kstat pstat;\n\tconst char *link;\n\tstruct dentry *destdir;\n\tstruct qstr destname;\n\tstruct dentry *workdir;\n\tconst struct ovl_fh *origin_fh;\n\tbool origin;\n\tbool indexed;\n\tbool metacopy;\n\tbool metacopy_digest;\n\tbool metadata_fsync;\n};\n\nstruct ovl_dir_cache {\n\tlong int refcount;\n\tlong: 32;\n\tu64 version;\n\tstruct list_head entries;\n\tstruct rb_root root;\n\tlong: 32;\n};\n\nstruct ovl_dir_file {\n\tbool is_real;\n\tbool is_upper;\n\tstruct ovl_dir_cache *cache;\n\tstruct list_head *cursor;\n\tstruct file *realfile;\n\tstruct file *upperfile;\n};\n\nstruct ovl_layer;\n\nstruct ovl_path {\n\tconst struct ovl_layer *layer;\n\tstruct dentry *dentry;\n};\n\nstruct ovl_entry {\n\tunsigned int __numlower;\n\tstruct ovl_path __lowerstack[0];\n};\n\nstruct ovl_fb {\n\tu8 version;\n\tu8 magic;\n\tu8 len;\n\tu8 flags;\n\tu8 type;\n\tuuid_t uuid;\n\tu32 fid[0];\n} __attribute__((packed));\n\nstruct ovl_fh {\n\tu8 padding[3];\n\tunion {\n\t\tstruct ovl_fb fb;\n\t\tstruct {\n\t\t\tstruct {} __empty_buf;\n\t\t\tu8 buf[0];\n\t\t};\n\t};\n};\n\nstruct ovl_file {\n\tstruct file *realfile;\n\tstruct file *upperfile;\n};\n\nstruct ovl_sb;\n\nstruct ovl_fs {\n\tunsigned int numlayer;\n\tunsigned int numfs;\n\tunsigned int numdatalayer;\n\tstruct ovl_layer *layers;\n\tstruct ovl_sb *fs;\n\tstruct dentry *workbasedir;\n\tstruct dentry *workdir;\n\tlong int namelen;\n\tstruct ovl_config config;\n\tconst struct cred *creator_cred;\n\tbool tmpfile;\n\tbool noxattr;\n\tbool nofh;\n\tbool upperdir_locked;\n\tbool workdir_locked;\n\tstruct inode *workbasedir_trap;\n\tstruct inode *workdir_trap;\n\tint xino_mode;\n\tatomic_long_t last_ino;\n\tstruct dentry *whiteout;\n\tbool no_shared_whiteout;\n\tstruct mutex whiteout_lock;\n\terrseq_t errseq;\n\tbool casefold;\n};\n\nstruct ovl_opt_set {\n\tbool metacopy;\n\tbool redirect;\n\tbool nfs_export;\n\tbool index;\n};\n\nstruct ovl_fs_context_layer;\n\nstruct ovl_fs_context {\n\tstruct path upper;\n\tstruct path work;\n\tsize_t capacity;\n\tsize_t nr;\n\tsize_t nr_data;\n\tstruct ovl_opt_set set;\n\tstruct ovl_fs_context_layer *lower;\n\tchar *lowerdir_all;\n\tbool casefold_set;\n};\n\nstruct ovl_fs_context_layer {\n\tchar *name;\n\tstruct path path;\n};\n\nstruct ovl_inode {\n\tunion {\n\t\tstruct ovl_dir_cache *cache;\n\t\tconst char *lowerdata_redirect;\n\t};\n\tconst char *redirect;\n\tu64 version;\n\tlong unsigned int flags;\n\tlong: 32;\n\tstruct inode vfs_inode;\n\tstruct dentry *__upperdentry;\n\tstruct ovl_entry *oe;\n\tstruct mutex lock;\n};\n\nstruct ovl_inode_params {\n\tstruct inode *newinode;\n\tstruct dentry *upperdentry;\n\tstruct ovl_entry *oe;\n\tbool index;\n\tchar *redirect;\n\tchar *lowerdata_redirect;\n};\n\nstruct ovl_layer {\n\tstruct vfsmount *mnt;\n\tstruct inode *trap;\n\tstruct ovl_sb *fs;\n\tint idx;\n\tint fsid;\n\tbool has_xwhiteouts;\n};\n\nstruct ovl_lookup_ctx {\n\tstruct dentry *dentry;\n\tstruct ovl_entry *oe;\n\tstruct ovl_path *stack;\n\tstruct ovl_path *origin_path;\n\tstruct dentry *upperdentry;\n\tstruct dentry *index;\n\tstruct inode *inode;\n\tunsigned int ctr;\n};\n\nstruct ovl_lookup_data {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tconst struct ovl_layer *layer;\n\tlong: 32;\n\tstruct qstr name;\n\tbool is_dir;\n\tbool opaque;\n\tbool xwhiteouts;\n\tbool stop;\n\tbool last;\n\tchar *redirect;\n\tchar *upperredirect;\n\tint metacopy;\n\tbool absolute_redirect;\n};\n\nstruct ovl_metacopy {\n\tu8 version;\n\tu8 len;\n\tu8 flags;\n\tu8 digest_algo;\n\tu8 digest[64];\n};\n\nstruct unicode_map;\n\nstruct ovl_readdir_data {\n\tstruct dir_context ctx;\n\tstruct dentry *dentry;\n\tbool is_lowest;\n\tstruct rb_root *root;\n\tstruct list_head *list;\n\tstruct list_head middle;\n\tstruct ovl_cache_entry *first_maybe_whiteout;\n\tstruct unicode_map *map;\n\tint count;\n\tint err;\n\tbool is_upper;\n\tbool d_type_supported;\n\tbool in_xwhiteouts_dir;\n\tlong: 32;\n};\n\nstruct ovl_readdir_translate {\n\tstruct dir_context *orig_ctx;\n\tstruct ovl_dir_cache *cache;\n\tstruct dir_context ctx;\n\tu64 parent_ino;\n\tint fsid;\n\tint xinobits;\n\tbool xinowarn;\n\tlong: 32;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct ovl_renamedata {\n\tstruct renamedata;\n\tstruct dentry *opaquedir;\n\tbool cleanup_whiteout;\n\tbool update_nlink;\n\tbool overwrite;\n};\n\nstruct ovl_sb {\n\tstruct super_block *sb;\n\tdev_t pseudo_dev;\n\tbool bad_uuid;\n\tbool is_lower;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tlong: 32;\n\tu64 bus_offset;\n};\n\nstruct p9_trans_module;\n\nstruct p9_client {\n\tspinlock_t lock;\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n\tenum p9_trans_status status;\n\tvoid *trans;\n\tstruct kmem_cache *fcall_cache;\n\tunion {\n\t\tstruct {\n\t\t\tint rfd;\n\t\t\tint wfd;\n\t\t} fd;\n\t\tstruct {\n\t\t\tu16 port;\n\t\t\tbool privport;\n\t\t} tcp;\n\t} trans_opts;\n\tstruct idr fids;\n\tstruct idr reqs;\n\tchar name[65];\n};\n\nstruct p9_client_opts {\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n};\n\nstruct p9_fcall {\n\tu32 size;\n\tu8 id;\n\tu16 tag;\n\tsize_t offset;\n\tsize_t capacity;\n\tstruct kmem_cache *cache;\n\tu8 *sdata;\n\tbool zc;\n};\n\nstruct p9_conn;\n\nstruct p9_poll_wait {\n\tstruct p9_conn *conn;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_addr;\n};\n\nstruct p9_req_t;\n\nstruct p9_conn {\n\tstruct list_head mux_list;\n\tstruct p9_client *client;\n\tint err;\n\tspinlock_t req_lock;\n\tstruct list_head req_list;\n\tstruct list_head unsent_req_list;\n\tstruct p9_req_t *rreq;\n\tstruct p9_req_t *wreq;\n\tchar tmp_buf[7];\n\tstruct p9_fcall rc;\n\tint wpos;\n\tint wsize;\n\tchar *wbuf;\n\tstruct list_head poll_pending_link;\n\tstruct p9_poll_wait poll_wait[2];\n\tpoll_table pt;\n\tstruct work_struct rq;\n\tstruct work_struct wq;\n\tlong unsigned int wsched;\n};\n\nstruct p9_qid {\n\tu8 type;\n\tu32 version;\n\tu64 path;\n};\n\nstruct p9_dirent {\n\tstruct p9_qid qid;\n\tu64 d_off;\n\tunsigned char d_type;\n\tchar d_name[256];\n\tlong: 32;\n};\n\nstruct p9_fd_opts {\n\tint rfd;\n\tint wfd;\n\tu16 port;\n\tbool privport;\n};\n\nstruct p9_fid {\n\tstruct p9_client *clnt;\n\tu32 fid;\n\trefcount_t count;\n\tint mode;\n\tstruct p9_qid qid;\n\tu32 iounit;\n\tkuid_t uid;\n\tvoid *rdir;\n\tstruct hlist_node dlist;\n\tstruct hlist_node ilist;\n\tlong: 32;\n};\n\nstruct p9_flock {\n\tu8 type;\n\tu32 flags;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_getlock {\n\tu8 type;\n\tlong: 32;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_iattr_dotl {\n\tu32 valid;\n\tu32 mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tu64 size;\n\tu64 atime_sec;\n\tu64 atime_nsec;\n\tu64 mtime_sec;\n\tu64 mtime_nsec;\n};\n\nstruct p9_rdma_opts {\n\tshort int port;\n\tbool privport;\n\tint sq_depth;\n\tint rq_depth;\n\tlong int timeout;\n};\n\nstruct p9_req_t {\n\tint status;\n\tint t_err;\n\trefcount_t refcount;\n\twait_queue_head_t wq;\n\tstruct p9_fcall tc;\n\tstruct p9_fcall rc;\n\tstruct list_head req_list;\n};\n\nstruct p9_rstatfs {\n\tu32 type;\n\tu32 bsize;\n\tu64 blocks;\n\tu64 bfree;\n\tu64 bavail;\n\tu64 files;\n\tu64 ffree;\n\tu64 fsid;\n\tu32 namelen;\n\tlong: 32;\n};\n\nstruct p9_session_opts {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tlong int session_lock_timeout;\n};\n\nstruct p9_stat_dotl {\n\tu64 st_result_mask;\n\tstruct p9_qid qid;\n\tu32 st_mode;\n\tkuid_t st_uid;\n\tkgid_t st_gid;\n\tlong: 32;\n\tu64 st_nlink;\n\tu64 st_rdev;\n\tu64 st_size;\n\tu64 st_blksize;\n\tu64 st_blocks;\n\tu64 st_atime_sec;\n\tu64 st_atime_nsec;\n\tu64 st_mtime_sec;\n\tu64 st_mtime_nsec;\n\tu64 st_ctime_sec;\n\tu64 st_ctime_nsec;\n\tu64 st_btime_sec;\n\tu64 st_btime_nsec;\n\tu64 st_gen;\n\tu64 st_data_version;\n};\n\nstruct p9_trans_fd {\n\tstruct file *rd;\n\tstruct file *wr;\n\tstruct p9_conn conn;\n};\n\nstruct p9_trans_module {\n\tstruct list_head list;\n\tchar *name;\n\tint maxsize;\n\tbool pooled_rbuffers;\n\tbool def;\n\tbool supports_vmalloc;\n\tstruct module *owner;\n\tint (*create)(struct p9_client *, struct fs_context *);\n\tvoid (*close)(struct p9_client *);\n\tint (*request)(struct p9_client *, struct p9_req_t *);\n\tint (*cancel)(struct p9_client *, struct p9_req_t *);\n\tint (*cancelled)(struct p9_client *, struct p9_req_t *);\n\tint (*zc_request)(struct p9_client *, struct p9_req_t *, struct iov_iter *, struct iov_iter *, int, int, int);\n\tint (*show_options)(struct seq_file *, struct p9_client *);\n};\n\nstruct p9_wstat {\n\tu16 size;\n\tu16 type;\n\tu32 dev;\n\tstruct p9_qid qid;\n\tu32 mode;\n\tu32 atime;\n\tu32 mtime;\n\tlong: 32;\n\tu64 length;\n\tconst char *name;\n\tconst char *uid;\n\tconst char *gid;\n\tconst char *muid;\n\tchar *extension;\n\tkuid_t n_uid;\n\tkgid_t n_gid;\n\tkuid_t n_muid;\n};\n\nstruct packed_field_u16 {\n\tu16 startbit;\n\tu16 endbit;\n\tu16 offset;\n\tu16 size;\n};\n\nstruct packed_field_u8 {\n\tu8 startbit;\n\tu8 endbit;\n\tu8 offset;\n\tu8 size;\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tlong: 32;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tlong: 32;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu32 history[32];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct packet_type prot_hook;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_t tp_drops;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef struct page *pgtable_t;\n\nstruct page_address_map {\n\tstruct page *page;\n\tvoid *virtual;\n\tstruct list_head list;\n};\n\nstruct page_address_slot {\n\tstruct list_head lh;\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 32;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tu32 xdp_mem_id;\n\tlong: 32;\n\tstruct pp_alloc_cache alloc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tlong: 32;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tlong: 32;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t\tlong: 32;\n\t} user;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_reporting_dev_info {\n\tint (*report)(struct page_reporting_dev_info *, struct scatterlist *, unsigned int);\n\tstruct delayed_work work;\n\tatomic_t state;\n\tunsigned int order;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n\tlong: 32;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t\tlong: 32;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tlong: 32;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct pch_ts_regs;\n\nstruct pch_dev {\n\tstruct pch_ts_regs *regs;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info caps;\n\tint exts0_enabled;\n\tint exts1_enabled;\n\tu32 irq;\n\tstruct pci_dev *pdev;\n\tspinlock_t register_lock;\n};\n\nstruct pch_dma_slave {\n\tstruct device *dma_dev;\n\tunsigned int chan_id;\n\tdma_addr_t tx_reg;\n\tdma_addr_t rx_reg;\n\tenum pch_dma_width width;\n};\n\nstruct pch_gbe_mac_info {\n\tu8 addr[6];\n\tu8 fc;\n\tu8 fc_autoneg;\n\tu8 tx_fc_enable;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tu8 autoneg;\n\tu16 link_speed;\n\tu16 link_duplex;\n};\n\nstruct pch_gbe_phy_info {\n\tu32 addr;\n\tu32 id;\n\tu32 revision;\n\tu32 reset_delay_us;\n\tu16 autoneg_advertised;\n};\n\nstruct pch_gbe_regs;\n\nstruct pch_gbe_hw {\n\tvoid *back;\n\tstruct pch_gbe_regs *reg;\n\tspinlock_t miim_lock;\n\tstruct pch_gbe_mac_info mac;\n\tstruct pch_gbe_phy_info phy;\n};\n\nstruct pch_gbe_hw_stats {\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 rx_bytes;\n\tu32 tx_bytes;\n\tu32 rx_errors;\n\tu32 tx_errors;\n\tu32 rx_dropped;\n\tu32 tx_dropped;\n\tu32 multicast;\n\tu32 collisions;\n\tu32 rx_crc_errors;\n\tu32 rx_frame_errors;\n\tu32 rx_alloc_buff_failed;\n\tu32 tx_length_errors;\n\tu32 tx_aborted_errors;\n\tu32 tx_carrier_errors;\n\tu32 tx_timeout_count;\n\tu32 tx_restart_count;\n\tu32 intr_rx_dsc_empty_count;\n\tu32 intr_rx_frame_err_count;\n\tu32 intr_rx_fifo_err_count;\n\tu32 intr_rx_dma_err_count;\n\tu32 intr_tx_fifo_err_count;\n\tu32 intr_tx_dma_err_count;\n\tu32 intr_tcpip_err_count;\n};\n\nstruct pch_gbe_tx_ring;\n\nstruct pch_gbe_rx_ring;\n\nstruct pch_gbe_privdata;\n\nstruct pch_gbe_adapter {\n\tspinlock_t stats_lock;\n\tspinlock_t ethtool_lock;\n\tatomic_t irq_sem;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tint irq;\n\tstruct net_device *polling_netdev;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tstruct pch_gbe_hw hw;\n\tstruct pch_gbe_hw_stats stats;\n\tstruct work_struct reset_task;\n\tstruct mii_if_info mii;\n\tstruct timer_list watchdog_timer;\n\tu32 wake_up_evt;\n\tu32 *config_space;\n\tlong unsigned int led_status;\n\tstruct pch_gbe_tx_ring *tx_ring;\n\tstruct pch_gbe_rx_ring *rx_ring;\n\tlong unsigned int rx_buffer_len;\n\tlong unsigned int tx_queue_len;\n\tbool rx_stop_flag;\n\tint hwts_tx_en;\n\tint hwts_rx_en;\n\tstruct pci_dev *ptp_pdev;\n\tstruct pch_gbe_privdata *pdata;\n\tlong: 32;\n};\n\nstruct pch_gbe_buffer {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n\tunsigned char *rx_buffer;\n\tlong unsigned int time_stamp;\n\tu16 length;\n\tbool mapped;\n};\n\nstruct pch_gbe_opt_list {\n\tint i;\n\tchar *str;\n};\n\nstruct pch_gbe_option {\n\tenum {\n\t\tenable_option = 0,\n\t\trange_option = 1,\n\t\tlist_option = 2,\n\t} type;\n\tchar *name;\n\tchar *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tconst struct pch_gbe_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct pch_gbe_privdata {\n\tbool phy_tx_clk_delay;\n\tbool phy_disable_hibernate;\n\tint (*platform_init)(struct pci_dev *);\n};\n\nstruct pch_gbe_regs_mac_adr {\n\tu32 high;\n\tu32 low;\n};\n\nstruct pch_gbe_regs {\n\tu32 INT_ST;\n\tu32 INT_EN;\n\tu32 MODE;\n\tu32 RESET;\n\tu32 TCPIP_ACC;\n\tu32 EX_LIST;\n\tu32 INT_ST_HOLD;\n\tu32 PHY_INT_CTRL;\n\tu32 MAC_RX_EN;\n\tu32 RX_FCTRL;\n\tu32 PAUSE_REQ;\n\tu32 RX_MODE;\n\tu32 TX_MODE;\n\tu32 RX_FIFO_ST;\n\tu32 TX_FIFO_ST;\n\tu32 TX_FID;\n\tu32 TX_RESULT;\n\tu32 PAUSE_PKT1;\n\tu32 PAUSE_PKT2;\n\tu32 PAUSE_PKT3;\n\tu32 PAUSE_PKT4;\n\tu32 PAUSE_PKT5;\n\tu32 reserve[2];\n\tstruct pch_gbe_regs_mac_adr mac_adr[16];\n\tu32 ADDR_MASK;\n\tu32 MIIM;\n\tu32 MAC_ADDR_LOAD;\n\tu32 RGMII_ST;\n\tu32 RGMII_CTRL;\n\tu32 reserve3[3];\n\tu32 DMA_CTRL;\n\tu32 reserve4[3];\n\tu32 RX_DSC_BASE;\n\tu32 RX_DSC_SIZE;\n\tu32 RX_DSC_HW_P;\n\tu32 RX_DSC_HW_P_HLD;\n\tu32 RX_DSC_SW_P;\n\tu32 reserve5[3];\n\tu32 TX_DSC_BASE;\n\tu32 TX_DSC_SIZE;\n\tu32 TX_DSC_HW_P;\n\tu32 TX_DSC_HW_P_HLD;\n\tu32 TX_DSC_SW_P;\n\tu32 reserve6[3];\n\tu32 RX_DMA_ST;\n\tu32 TX_DMA_ST;\n\tu32 reserve7[2];\n\tu32 WOL_ST;\n\tu32 WOL_CTRL;\n\tu32 WOL_ADDR_MASK;\n};\n\nstruct pch_gbe_rx_desc {\n\tu32 buffer_addr;\n\tu32 tcp_ip_status;\n\tu16 rx_words_eob;\n\tu16 gbec_status;\n\tu8 dma_status;\n\tu8 reserved1;\n\tu16 reserved2;\n};\n\nstruct pch_gbe_rx_ring {\n\tstruct pch_gbe_rx_desc *desc;\n\tdma_addr_t dma;\n\tunsigned char *rx_buff_pool;\n\tdma_addr_t rx_buff_pool_logic;\n\tunsigned int rx_buff_pool_size;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct pch_gbe_buffer *buffer_info;\n};\n\nstruct pch_gbe_stats {\n\tchar string[32];\n\tsize_t size;\n\tsize_t offset;\n};\n\nstruct pch_gbe_tx_desc {\n\tu32 buffer_addr;\n\tu16 length;\n\tu16 reserved1;\n\tu16 tx_words_eob;\n\tu16 tx_frame_ctrl;\n\tu8 dma_status;\n\tu8 reserved2;\n\tu16 gbec_status;\n};\n\nstruct pch_gbe_tx_ring {\n\tstruct pch_gbe_tx_desc *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct pch_gbe_buffer *buffer_info;\n};\n\nstruct pch_gpio_reg_data {\n\tu32 ien_reg;\n\tu32 imask_reg;\n\tu32 po_reg;\n\tu32 pm_reg;\n\tu32 im0_reg;\n\tu32 im1_reg;\n\tu32 gpio_use_sel_reg;\n};\n\nstruct pch_regs;\n\nstruct pch_gpio {\n\tvoid *base;\n\tstruct pch_regs *reg;\n\tstruct device *dev;\n\tstruct gpio_chip gpio;\n\tstruct pch_gpio_reg_data pch_gpio_reg;\n\tint irq_base;\n\tenum pch_type_t ioh;\n\tspinlock_t spinlock;\n};\n\nstruct pch_params {\n\tu8 station[20];\n};\n\nstruct pch_spi_board_data;\n\nstruct pch_pd_dev_save {\n\tint num;\n\tstruct platform_device *pd_save[2];\n\tstruct pch_spi_board_data *board_dat;\n};\n\nstruct pch_phub_reg {\n\tu32 phub_id_reg;\n\tu32 q_pri_val_reg;\n\tu32 rc_q_maxsize_reg;\n\tu32 bri_q_maxsize_reg;\n\tu32 comp_resp_timeout_reg;\n\tu32 bus_slave_control_reg;\n\tu32 deadlock_avoid_type_reg;\n\tu32 intpin_reg_wpermit_reg0;\n\tu32 intpin_reg_wpermit_reg1;\n\tu32 intpin_reg_wpermit_reg2;\n\tu32 intpin_reg_wpermit_reg3;\n\tu32 int_reduce_control_reg[128];\n\tu32 clkcfg_reg;\n\tu32 funcsel_reg;\n\tvoid *pch_phub_base_address;\n\tvoid *pch_phub_extrom_base_address;\n\tu32 pch_mac_start_address;\n\tu32 pch_opt_rom_start_address;\n\tint ioh_type;\n\tstruct pci_dev *pdev;\n};\n\nstruct pch_regs {\n\tu32 ien;\n\tu32 istatus;\n\tu32 idisp;\n\tu32 iclr;\n\tu32 imask;\n\tu32 imaskclr;\n\tu32 po;\n\tu32 pi;\n\tu32 pm;\n\tu32 im0;\n\tu32 im1;\n\tu32 reserved[3];\n\tu32 gpio_use_sel;\n\tu32 reset;\n};\n\nstruct pch_spi_board_data {\n\tstruct pci_dev *pdev;\n\tu8 suspend_sts;\n\tint num;\n};\n\nstruct pch_spi_dma_ctrl {\n\tstruct pci_dev *dma_dev;\n\tstruct dma_async_tx_descriptor *desc_tx;\n\tstruct dma_async_tx_descriptor *desc_rx;\n\tstruct pch_dma_slave param_tx;\n\tstruct pch_dma_slave param_rx;\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n\tstruct scatterlist *sg_tx_p;\n\tstruct scatterlist *sg_rx_p;\n\tstruct scatterlist sg_tx;\n\tstruct scatterlist sg_rx;\n\tint nent;\n\tvoid *tx_buf_virt;\n\tvoid *rx_buf_virt;\n\tdma_addr_t tx_buf_dma;\n\tdma_addr_t rx_buf_dma;\n};\n\nstruct pch_spi_data {\n\tvoid *io_remap_addr;\n\tlong unsigned int io_base_addr;\n\tstruct spi_controller *host;\n\tstruct work_struct work;\n\twait_queue_head_t wait;\n\tu8 transfer_complete;\n\tu8 bcurrent_msg_processing;\n\tspinlock_t lock;\n\tstruct list_head queue;\n\tu8 status;\n\tu32 bpw_len;\n\tu8 transfer_active;\n\tu32 tx_index;\n\tu32 rx_index;\n\tu16 *pkt_tx_buff;\n\tu16 *pkt_rx_buff;\n\tu8 n_curnt_chip;\n\tstruct spi_device *current_chip;\n\tstruct spi_message *current_msg;\n\tstruct spi_transfer *cur_trans;\n\tstruct pch_spi_board_data *board_dat;\n\tstruct platform_device *plat_dev;\n\tint ch;\n\tstruct pch_spi_dma_ctrl dma;\n\tint use_dma;\n\tu8 irq_reg_sts;\n\tint save_total_len;\n};\n\nstruct pch_ts_regs {\n\tu32 control;\n\tu32 event;\n\tu32 addend;\n\tu32 accum;\n\tu32 test;\n\tu32 ts_compare;\n\tu32 rsystime_lo;\n\tu32 rsystime_hi;\n\tu32 systime_lo;\n\tu32 systime_hi;\n\tu32 trgt_lo;\n\tu32 trgt_hi;\n\tu32 asms_lo;\n\tu32 asms_hi;\n\tu32 amms_lo;\n\tu32 amms_hi;\n\tu32 ch_control;\n\tu32 ch_event;\n\tu32 tx_snap_lo;\n\tu32 tx_snap_hi;\n\tu32 rx_snap_lo;\n\tu32 rx_snap_hi;\n\tu32 src_uuid_lo;\n\tu32 src_uuid_hi;\n\tu32 can_status;\n\tu32 can_snap_lo;\n\tu32 can_snap_hi;\n\tu32 ts_sel;\n\tu32 ts_st[6];\n\tu32 reserve1[14];\n\tu32 stl_max_set_en;\n\tu32 stl_max_set;\n\tu32 reserve2[13];\n\tu32 srst;\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nstruct pci_ops;\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tint domain_nr;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tlong: 32;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n\tlong: 32;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_ecam_ops;\n\nstruct pci_config_window {\n\tstruct resource res;\n\tstruct resource busr;\n\tunsigned int bus_shift;\n\tvoid *priv;\n\tconst struct pci_ecam_ops *ops;\n\tunion {\n\t\tvoid *win;\n\t\tvoid **winp;\n\t};\n\tstruct device *parent;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct pcie_bwctrl_data;\n\nstruct pcie_link_state;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tstruct pcie_link_state *link_state;\n\tunsigned int aspm_l0s_support: 1;\n\tunsigned int aspm_l1_support: 1;\n\tunsigned int ltr_path: 1;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tlong: 32;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[11];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[11];\n\tstruct bin_attribute *res_attr_wc[11];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_host_bridge;\n\nstruct pci_ecam_ops {\n\tunsigned int bus_shift;\n\tstruct pci_ops pci_ops;\n\tint (*init)(struct pci_config_window *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n};\n\nstruct pci_eq_presets {\n\tu16 eq_presets_8gts[16];\n\tu8 eq_presets_Ngts[48];\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_filp_private {\n\tenum pci_mmap_state mmap_state;\n\tint write_combine;\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tvoid (*hook)(struct pci_dev *);\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct serial_private;\n\nstruct pciserial_board;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tlong: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[11];\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpuobj_ext;\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tstruct pcpuobj_ext *obj_exts;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tlong: 32;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcpuobj_ext {\n\tstruct obj_cgroup *cgroup;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[46];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tshort int free_count;\n\tstruct list_head lists[12];\n\tlong: 32;\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[10];\n\ts8 stat_threshold;\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\nstruct percpu_free_defer {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[1];\n\tlong unsigned int offset[1];\n\tlocal_lock_t lock;\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event {};\n\nstruct pericom8250 {\n\tvoid *virt;\n\tunsigned int nr;\n\tint line[0];\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct pf_desc {\n\tu32 pseudoflavor;\n\tu32 qop;\n\tu32 service;\n\tchar *name;\n\tchar *auth_domain_name;\n\tstruct auth_domain *domain;\n\tbool datatouch;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[3];\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int *pageblock_flags;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tconst char *name;\n\tint initialized;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[11];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[10];\n\tatomic_long_t vm_numa_event[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[4];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[3];\n\tstruct zonelist node_zonelists[1];\n\tint nr_zones;\n\tstruct page *node_mem_map;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad1_;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[46];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tu32 max_link_rate;\n\tenum phy_mode mode;\n};\n\nstruct phy_ops;\n\nstruct phy {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tstruct lock_class_key lockdep_key;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n\tstruct dentry *debugfs;\n\tlong: 32;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_lvds {\n\tunsigned int bits_per_lane_and_dclk_cycle;\n\tlong unsigned int differential_clk_rate;\n\tunsigned int lanes;\n\tbool is_slave;\n};\n\nstruct phy_configure_opts_hdmi {\n\tunsigned int bpc;\n\tlong: 32;\n\tunion {\n\t\tlong long unsigned int tmds_char_rate;\n\t\tstruct {\n\t\t\tu8 rate_per_lane;\n\t\t\tu8 lanes;\n\t\t} frl;\n\t};\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n\tstruct phy_configure_opts_lvds lvds;\n\tstruct phy_configure_opts_hdmi hdmi;\n};\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[2];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[4];\n\tlong unsigned int advertising[4];\n\tlong unsigned int lp_advertising[4];\n\tlong unsigned int adv_old[4];\n\tlong unsigned int supported_eee[4];\n\tlong unsigned int advertising_eee[4];\n\tlong unsigned int eee_disabled_modes[4];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[2];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct phy_package_shared *shared;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n\tlong: 32;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct phy_led {\n\tstruct list_head list;\n\tstruct phy_device *phydev;\n\tstruct led_classdev led_cdev;\n\tu8 index;\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nstruct phy_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct phy *phy;\n};\n\nunion phy_notify {\n\tenum phy_ufs_state ufs_state;\n};\n\nstruct phy_ops {\n\tint (*init)(struct phy *);\n\tint (*exit)(struct phy *);\n\tint (*power_on)(struct phy *);\n\tint (*power_off)(struct phy *);\n\tint (*set_mode)(struct phy *, enum phy_mode, int);\n\tint (*set_media)(struct phy *, enum phy_media);\n\tint (*set_speed)(struct phy *, int);\n\tint (*configure)(struct phy *, union phy_configure_opts *);\n\tint (*validate)(struct phy *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy *);\n\tint (*calibrate)(struct phy *);\n\tint (*connect)(struct phy *, int);\n\tint (*disconnect)(struct phy *, int);\n\tint (*notify_phystate)(struct phy *, union phy_notify);\n\tvoid (*release)(struct phy *);\n\tstruct module *owner;\n};\n\nstruct phy_package_shared {\n\tu8 base_addr;\n\tstruct device_node *np;\n\trefcount_t refcnt;\n\tlong unsigned int flags;\n\tsize_t priv_size;\n\tvoid *priv;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_port_ops;\n\nstruct phy_port {\n\tstruct list_head head;\n\tenum phy_port_parent parent_type;\n\tunion {\n\t\tstruct phy_device *phy;\n\t};\n\tconst struct phy_port_ops *ops;\n\tint pairs;\n\tlong unsigned int mediums;\n\tlong unsigned int supported[4];\n\tlong unsigned int interfaces[2];\n\tunsigned int not_described: 1;\n\tunsigned int active: 1;\n\tunsigned int is_mii: 1;\n\tunsigned int is_sfp: 1;\n};\n\nstruct phy_port_ops {\n\tvoid (*link_up)(struct phy_port *);\n\tvoid (*link_down)(struct phy_port *);\n\tint (*configure_mii)(struct phy_port *, bool, phy_interface_t);\n};\n\nstruct phy_provider {\n\tstruct device *dev;\n\tstruct device_node *children;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct phy * (*of_xlate)(struct device *, const struct of_phandle_args *);\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phylib_stubs {\n\tint (*hwtstamp_get)(struct phy_device *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct phy_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_ext_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n};\n\nstruct phylink_link_state {\n\tlong unsigned int advertising[4];\n\tlong unsigned int lp_advertising[4];\n\tphy_interface_t interface;\n\tint speed;\n\tint duplex;\n\tint pause;\n\tint rate_matching;\n\tunsigned int link: 1;\n\tunsigned int an_complete: 1;\n};\n\nstruct phylink {\n\tstruct net_device *netdev;\n\tconst struct phylink_mac_ops *mac_ops;\n\tstruct phylink_config *config;\n\tstruct phylink_pcs *pcs;\n\tstruct device *dev;\n\tunsigned int old_link_state: 1;\n\tlong unsigned int phylink_disable_state;\n\tstruct phy_device *phydev;\n\tphy_interface_t link_interface;\n\tu8 cfg_link_an_mode;\n\tu8 req_link_an_mode;\n\tu8 act_link_an_mode;\n\tu8 link_port;\n\tlong unsigned int supported[4];\n\tlong unsigned int supported_lpi[4];\n\tstruct phylink_link_state link_config;\n\tphy_interface_t cur_interface;\n\tstruct gpio_desc *link_gpio;\n\tunsigned int link_irq;\n\tstruct timer_list link_poll;\n\tstruct mutex state_mutex;\n\tstruct mutex phydev_mutex;\n\tstruct phylink_link_state phy_state;\n\tunsigned int phy_ib_mode;\n\tstruct work_struct resolve;\n\tunsigned int pcs_neg_mode;\n\tunsigned int pcs_state;\n\tbool link_failed;\n\tbool suspend_link_up;\n\tbool force_major_config;\n\tbool major_config_failed;\n\tbool mac_supports_eee_ops;\n\tbool mac_supports_eee;\n\tbool phy_enable_tx_lpi;\n\tbool mac_enable_tx_lpi;\n\tbool mac_tx_clk_stop;\n\tu32 mac_tx_lpi_timer;\n\tu8 mac_rx_clk_stop_blocked;\n\tstruct sfp_bus *sfp_bus;\n\tbool sfp_may_have_phy;\n\tlong unsigned int sfp_interfaces[2];\n\tlong unsigned int sfp_support[4];\n\tu8 sfp_port;\n\tstruct eee_config eee_cfg;\n\tu32 wolopts_mac;\n\tu8 wol_sopass[6];\n};\n\nstruct phylink_mac_ops {\n\tlong unsigned int (*mac_get_caps)(struct phylink_config *, phy_interface_t);\n\tstruct phylink_pcs * (*mac_select_pcs)(struct phylink_config *, phy_interface_t);\n\tint (*mac_prepare)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_config)(struct phylink_config *, unsigned int, const struct phylink_link_state *);\n\tint (*mac_finish)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_down)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_up)(struct phylink_config *, struct phy_device *, unsigned int, phy_interface_t, int, int, bool, bool);\n\tvoid (*mac_disable_tx_lpi)(struct phylink_config *);\n\tint (*mac_enable_tx_lpi)(struct phylink_config *, u32, bool);\n\tint (*mac_wol_set)(struct phylink_config *, u32, const u8 *);\n};\n\nstruct phylink_pcs_ops {\n\tint (*pcs_validate)(struct phylink_pcs *, long unsigned int *, const struct phylink_link_state *);\n\tunsigned int (*pcs_inband_caps)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_enable)(struct phylink_pcs *);\n\tvoid (*pcs_disable)(struct phylink_pcs *);\n\tvoid (*pcs_pre_config)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_post_config)(struct phylink_pcs *, phy_interface_t);\n\tvoid (*pcs_get_state)(struct phylink_pcs *, unsigned int, struct phylink_link_state *);\n\tint (*pcs_config)(struct phylink_pcs *, unsigned int, phy_interface_t, const long unsigned int *, bool);\n\tvoid (*pcs_an_restart)(struct phylink_pcs *);\n\tvoid (*pcs_link_up)(struct phylink_pcs *, unsigned int, phy_interface_t, int, int);\n\tvoid (*pcs_disable_eee)(struct phylink_pcs *);\n\tvoid (*pcs_enable_eee)(struct phylink_pcs *);\n\tint (*pcs_pre_init)(struct phylink_pcs *);\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct physmap_flash_data {\n\tunsigned int width;\n\tint (*init)(struct platform_device *);\n\tvoid (*exit)(struct platform_device *);\n\tvoid (*set_vpp)(struct platform_device *, int);\n\tunsigned int nr_parts;\n\tunsigned int pfow_base;\n\tchar *probe_type;\n\tstruct mtd_partition *parts;\n\tconst char * const *part_probe_types;\n};\n\nstruct physmap_flash_info {\n\tunsigned int nmaps;\n\tstruct mtd_info **mtds;\n\tstruct mtd_info *cmtd;\n\tstruct map_info *maps;\n\tspinlock_t vpp_lock;\n\tint vpp_refcnt;\n\tconst char *probe_type;\n\tconst char * const *part_types;\n\tunsigned int nparts;\n\tconst struct mtd_partition *parts;\n\tstruct gpio_descs *gpios;\n\tunsigned int gpio_values;\n\tunsigned int win_order;\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tlong: 32;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t\tlong: 32;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t\tlong: 32;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pids_cgroup {\n\tstruct cgroup_subsys_state css;\n\tatomic64_t counter;\n\tatomic64_t limit;\n\tint64_t watermark;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tatomic64_t events[2];\n\tatomic64_t events_local[2];\n};\n\nstruct pimhdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__be16 csum;\n};\n\nstruct pin_config_item {\n\tconst enum pin_config_param param;\n\tconst char * const display;\n\tconst char * const format;\n\tbool has_arg;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinctrl_setting_mux;\n\nstruct pin_desc {\n\tstruct pinctrl_dev *pctldev;\n\tconst char *name;\n\tbool dynamic_name;\n\tvoid *drv_data;\n\tunsigned int mux_usecount;\n\tconst char *mux_owner;\n\tconst struct pinctrl_setting_mux *mux_setting;\n\tconst char *gpio_owner;\n\tstruct mutex mux_lock;\n};\n\nstruct pinconf_generic_params {\n\tconst char * const property;\n\tenum pin_config_param param;\n\tu32 default_value;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinconf_ops {\n\tbool is_generic;\n\tint (*pin_config_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tint (*pin_config_group_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_group_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tvoid (*pin_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_group_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, long unsigned int);\n};\n\nstruct pinctrl {\n\tstruct list_head node;\n\tstruct device *dev;\n\tstruct list_head states;\n\tstruct pinctrl_state *state;\n\tstruct list_head dt_maps;\n\tstruct kref users;\n};\n\nstruct pinctrl_dev {\n\tstruct list_head node;\n\tconst struct pinctrl_desc *desc;\n\tstruct xarray pin_desc_tree;\n\tstruct xarray pin_group_tree;\n\tunsigned int num_groups;\n\tstruct xarray pin_function_tree;\n\tunsigned int num_functions;\n\tstruct list_head gpio_ranges;\n\tstruct device *dev;\n\tstruct module *owner;\n\tvoid *driver_data;\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *hog_default;\n\tstruct pinctrl_state *hog_sleep;\n\tstruct mutex mutex;\n\tstruct dentry *device_root;\n};\n\nstruct pinctrl_map;\n\nstruct pinctrl_dt_map {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_map *map;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_map_mux {\n\tconst char *group;\n\tconst char *function;\n};\n\nstruct pinctrl_map_configs {\n\tconst char *group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_map {\n\tconst char *dev_name;\n\tconst char *name;\n\tenum pinctrl_map_type type;\n\tconst char *ctrl_dev_name;\n\tunion {\n\t\tstruct pinctrl_map_mux mux;\n\t\tstruct pinctrl_map_configs configs;\n\t} data;\n};\n\nstruct pinctrl_maps {\n\tstruct list_head node;\n\tconst struct pinctrl_map *maps;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_ops {\n\tint (*get_groups_count)(struct pinctrl_dev *);\n\tconst char * (*get_group_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_group_pins)(struct pinctrl_dev *, unsigned int, const unsigned int **, unsigned int *);\n\tvoid (*pin_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tint (*dt_node_to_map)(struct pinctrl_dev *, struct device_node *, struct pinctrl_map **, unsigned int *);\n\tvoid (*dt_free_map)(struct pinctrl_dev *, struct pinctrl_map *, unsigned int);\n};\n\nstruct pinctrl_pin_desc {\n\tunsigned int number;\n\tconst char *name;\n\tvoid *drv_data;\n};\n\nstruct pinctrl_setting_mux {\n\tunsigned int group;\n\tunsigned int func;\n};\n\nstruct pinctrl_setting_configs {\n\tunsigned int group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_setting {\n\tstruct list_head node;\n\tenum pinctrl_map_type type;\n\tstruct pinctrl_dev *pctldev;\n\tconst char *dev_name;\n\tunion {\n\t\tstruct pinctrl_setting_mux mux;\n\t\tstruct pinctrl_setting_configs configs;\n\t} data;\n};\n\nstruct pinctrl_state {\n\tstruct list_head node;\n\tconst char *name;\n\tstruct list_head settings;\n};\n\nstruct pinfunction {\n\tconst char *name;\n\tconst char * const *groups;\n\tsize_t ngroups;\n\tlong unsigned int flags;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinmux_ops {\n\tint (*request)(struct pinctrl_dev *, unsigned int);\n\tint (*free)(struct pinctrl_dev *, unsigned int);\n\tint (*get_functions_count)(struct pinctrl_dev *);\n\tconst char * (*get_function_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_function_groups)(struct pinctrl_dev *, unsigned int, const char * const **, unsigned int *);\n\tbool (*function_is_gpio)(struct pinctrl_dev *, unsigned int);\n\tint (*set_mux)(struct pinctrl_dev *, unsigned int, unsigned int);\n\tint (*gpio_request_enable)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tvoid (*gpio_disable_free)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tint (*gpio_set_direction)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int, bool);\n\tbool strict;\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct pistachio_pll_rate_table;\n\nstruct pistachio_clk_pll {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct pistachio_pll_rate_table *rates;\n\tunsigned int nr_rates;\n};\n\nstruct pistachio_clk_provider {\n\tstruct device_node *node;\n\tvoid *base;\n\tstruct clk_onecell_data clk_data;\n};\n\nstruct pistachio_clocksource {\n\tvoid *base;\n\traw_spinlock_t lock;\n\tstruct clocksource cs;\n};\n\nstruct pistachio_div {\n\tunsigned int id;\n\tlong unsigned int reg;\n\tunsigned int width;\n\tunsigned int div_flags;\n\tconst char *name;\n\tconst char *parent;\n};\n\nstruct pistachio_fixed_factor {\n\tunsigned int id;\n\tunsigned int div;\n\tconst char *name;\n\tconst char *parent;\n};\n\nstruct pistachio_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n\tconst int *scenarios;\n\tunsigned int nscenarios;\n\tunsigned int scenario_reg;\n\tunsigned int scenario_shift;\n\tunsigned int scenario_mask;\n};\n\nstruct pistachio_gate {\n\tunsigned int id;\n\tlong unsigned int reg;\n\tunsigned int shift;\n\tconst char *name;\n\tconst char *parent;\n};\n\nstruct pistachio_pinctrl;\n\nstruct pistachio_gpio_bank {\n\tstruct pistachio_pinctrl *pctl;\n\tvoid *base;\n\tint instance;\n\tunsigned int pin_base;\n\tunsigned int npins;\n\tstruct gpio_chip gpio_chip;\n};\n\nstruct pistachio_mux {\n\tunsigned int id;\n\tlong unsigned int reg;\n\tunsigned int shift;\n\tunsigned int num_parents;\n\tconst char *name;\n\tconst char * const *parents;\n};\n\nstruct pistachio_pin_group {\n\tconst char *name;\n\tunsigned int pin;\n\tint mux_option[3];\n\tint mux_reg;\n\tint mux_shift;\n\tint mux_mask;\n};\n\nstruct pistachio_pinctrl {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct pinctrl_dev *pctldev;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct pistachio_function *functions;\n\tunsigned int nfunctions;\n\tconst struct pistachio_pin_group *groups;\n\tunsigned int ngroups;\n\tstruct pistachio_gpio_bank *gpio_banks;\n\tunsigned int nbanks;\n};\n\nstruct pistachio_pll {\n\tunsigned int id;\n\tlong unsigned int reg_base;\n\tenum pistachio_pll_type type;\n\tstruct pistachio_pll_rate_table *rates;\n\tunsigned int nr_rates;\n\tconst char *name;\n\tconst char *parent;\n};\n\nstruct pistachio_pll_rate_table {\n\tlong long unsigned int fref;\n\tlong long unsigned int fout;\n\tlong long unsigned int refdiv;\n\tlong long unsigned int fbdiv;\n\tlong long unsigned int postdiv1;\n\tlong long unsigned int postdiv2;\n\tlong long unsigned int frac;\n};\n\nstruct reset_control_ops;\n\nstruct reset_controller_dev {\n\tconst struct reset_control_ops *ops;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct list_head reset_control_head;\n\tstruct device *dev;\n\tstruct device_node *of_node;\n\tconst struct of_phandle_args *of_args;\n\tint of_reset_n_cells;\n\tint (*of_xlate)(struct reset_controller_dev *, const struct of_phandle_args *);\n\tunsigned int nr_resets;\n};\n\nstruct pistachio_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *periph_regs;\n};\n\nstruct pistachio_usb_phy {\n\tstruct device *dev;\n\tstruct regmap *cr_top;\n\tstruct clk *phy_clk;\n\tunsigned int refclk;\n};\n\nstruct plat_nand_data {\n\tstruct nand_controller controller;\n\tlong: 32;\n\tstruct nand_chip chip;\n\tvoid *io_base;\n\tlong: 32;\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tunsigned int uartclk;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tunsigned int type;\n\tupf_t flags;\n\tu16 bugs;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tlong: 32;\n};\n\nstruct plat_smp_ops {\n\tvoid (*send_ipi_single)(int, unsigned int);\n\tvoid (*send_ipi_mask)(const struct cpumask *, unsigned int);\n\tvoid (*init_secondary)(void);\n\tvoid (*smp_finish)(void);\n\tint (*boot_secondary)(int, struct task_struct *);\n\tvoid (*smp_setup)(void);\n\tvoid (*prepare_cpus)(unsigned int);\n\tvoid (*prepare_boot_cpu)(void);\n\tint (*cpu_disable)(void);\n\tvoid (*cpu_die)(unsigned int);\n\tvoid (*cleanup_dead_cpu)(unsigned int);\n};\n\nstruct stmmac_rxq_cfg {\n\tu8 mode_to_use;\n\tu32 chan;\n\tu8 pkt_route;\n\tbool use_prio;\n\tu32 prio;\n};\n\nstruct stmmac_txq_cfg {\n\tu32 weight;\n\tbool coe_unsupported;\n\tu8 mode_to_use;\n\tu32 send_slope;\n\tu32 idle_slope;\n\tu32 high_credit;\n\tu32 low_credit;\n\tbool use_prio;\n\tu32 prio;\n\tint tbs_en;\n};\n\nstruct stmmac_mdio_bus_data;\n\nstruct stmmac_dma_cfg;\n\nstruct stmmac_safety_feature_cfg;\n\nstruct stmmac_priv;\n\nstruct system_counterval_t;\n\nstruct stmmac_axi;\n\nstruct plat_stmmacenet_data {\n\tenum dwmac_core_type core_type;\n\tint bus_id;\n\tint phy_addr;\n\tphy_interface_t phy_interface;\n\tstruct stmmac_mdio_bus_data *mdio_bus_data;\n\tstruct device_node *phy_node;\n\tstruct fwnode_handle *port_node;\n\tstruct device_node *mdio_node;\n\tstruct stmmac_dma_cfg *dma_cfg;\n\tstruct stmmac_safety_feature_cfg *safety_feat_cfg;\n\tint clk_csr;\n\tint enh_desc;\n\tint tx_coe;\n\tint rx_coe;\n\tint bugged_jumbo;\n\tint pmt;\n\tint force_sf_dma_mode;\n\tint force_thresh_dma_mode;\n\tint riwt_off;\n\tint max_speed;\n\tint maxmtu;\n\tint multicast_filter_bins;\n\tint unicast_filter_entries;\n\tint tx_fifo_size;\n\tint rx_fifo_size;\n\tu32 host_dma_width;\n\tu32 rx_queues_to_use;\n\tu32 tx_queues_to_use;\n\tu8 rx_sched_algorithm;\n\tu8 tx_sched_algorithm;\n\tstruct stmmac_rxq_cfg rx_queues_cfg[8];\n\tstruct stmmac_txq_cfg tx_queues_cfg[8];\n\tvoid (*get_interfaces)(struct stmmac_priv *, void *, long unsigned int *);\n\tint (*set_phy_intf_sel)(void *, u8);\n\tint (*set_clk_tx_rate)(void *, struct clk *, phy_interface_t, int);\n\tvoid (*fix_mac_speed)(void *, int, unsigned int);\n\tint (*fix_soc_reset)(struct stmmac_priv *);\n\tint (*serdes_powerup)(struct net_device *, void *);\n\tvoid (*serdes_powerdown)(struct net_device *, void *);\n\tint (*mac_finish)(struct net_device *, void *, unsigned int, phy_interface_t);\n\tvoid (*ptp_clk_freq_config)(struct stmmac_priv *);\n\tint (*init)(struct device *, void *);\n\tvoid (*exit)(struct device *, void *);\n\tint (*suspend)(struct device *, void *);\n\tint (*resume)(struct device *, void *);\n\tint (*mac_setup)(void *, struct mac_device_info *);\n\tint (*clks_config)(void *, bool);\n\tint (*crosststamp)(ktime_t *, struct system_counterval_t *, void *);\n\tvoid (*dump_debug_regs)(void *);\n\tint (*pcs_init)(struct stmmac_priv *);\n\tvoid (*pcs_exit)(struct stmmac_priv *);\n\tstruct phylink_pcs * (*select_pcs)(struct stmmac_priv *, phy_interface_t);\n\tvoid *bsp_priv;\n\tstruct clk *stmmac_clk;\n\tstruct clk *pclk;\n\tstruct clk *clk_ptp_ref;\n\tstruct clk *clk_tx_i;\n\tlong unsigned int clk_ptp_rate;\n\tlong unsigned int clk_ref_rate;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tunsigned int mult_fact_100ns;\n\ts32 ptp_max_adj;\n\tu32 cdc_error_adj;\n\tstruct reset_control *stmmac_rst;\n\tstruct reset_control *stmmac_ahb_rst;\n\tstruct stmmac_axi *axi;\n\tint rss_en;\n\tint mac_port_sel_speed;\n\tu8 vlan_fail_q;\n\tstruct pci_dev *pdev;\n\tint int_snapshot_num;\n\tint msi_mac_vec;\n\tint msi_wol_vec;\n\tint msi_sfty_ce_vec;\n\tint msi_sfty_ue_vec;\n\tint msi_rx_base_vec;\n\tint msi_tx_base_vec;\n\tconst struct dwmac4_addrs *dwmac4_addrs;\n\tunsigned int flags;\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct property_entry;\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tlong: 32;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n\tlong: 32;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_nand_chip {\n\tint nr_chips;\n\tint chip_offset;\n\tint nr_partitions;\n\tstruct mtd_partition *partitions;\n\tint chip_delay;\n\tunsigned int options;\n\tunsigned int bbt_options;\n\tconst char **part_probe_types;\n};\n\nstruct platform_nand_ctrl {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tint (*dev_ready)(struct nand_chip *);\n\tvoid (*select_chip)(struct nand_chip *, int);\n\tvoid (*cmd_ctrl)(struct nand_chip *, int, unsigned int);\n\tvoid (*write_buf)(struct nand_chip *, const uint8_t *, int);\n\tvoid (*read_buf)(struct nand_chip *, uint8_t *, int);\n\tvoid *priv;\n};\n\nstruct platform_nand_data {\n\tstruct platform_nand_chip chip;\n\tstruct platform_nand_ctrl ctrl;\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)(void);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tvoid (*check)(void);\n\tbool (*wake)(void);\n\tvoid (*restore_early)(void);\n\tvoid (*restore)(void);\n\tvoid (*end)(void);\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)(void);\n\tvoid (*finish)(void);\n\tbool (*suspend_again)(void);\n\tvoid (*end)(void);\n\tvoid (*recover)(void);\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct pm_clk_notifier_block {\n\tstruct notifier_block nb;\n\tstruct dev_pm_domain *pm_domain;\n\tchar *con_ids[0];\n};\n\nstruct pm_clock_entry {\n\tstruct list_head node;\n\tchar *con_id;\n\tstruct clk *clk;\n\tenum pce_status status;\n\tbool enabled_when_prepared;\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n\tunsigned int clock_op_might_sleep;\n\tstruct mutex clock_mutex;\n\tstruct list_head clock_list;\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct pnfs_commit_bucket {\n\tstruct list_head written;\n\tstruct list_head committing;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_writeverf direct_verf;\n};\n\nstruct pnfs_commit_array {\n\tstruct list_head cinfo_list;\n\tstruct list_head lseg_list;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tunsigned int nbuckets;\n\tstruct pnfs_commit_bucket buckets[0];\n};\n\nstruct pnfs_commit_ops {\n\tvoid (*setup_ds_info)(struct pnfs_ds_commit_info *, struct pnfs_layout_segment *);\n\tvoid (*release_ds_info)(struct pnfs_ds_commit_info *, struct inode *);\n\tint (*commit_pagelist)(struct inode *, struct list_head *, int, struct nfs_commit_info *);\n\tvoid (*mark_request_commit)(struct nfs_page *, struct pnfs_layout_segment *, struct nfs_commit_info *, u32);\n\tvoid (*clear_request_commit)(struct nfs_page *, struct nfs_commit_info *);\n\tint (*scan_commit_lists)(struct nfs_commit_info *, int);\n\tvoid (*recover_commit_reqs)(struct list_head *, struct nfs_commit_info *);\n};\n\nstruct pnfs_device {\n\tstruct nfs4_deviceid dev_id;\n\tunsigned int layout_type;\n\tunsigned int mincount;\n\tunsigned int maxcount;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tunsigned char nocache: 1;\n};\n\nstruct pnfs_layoutdriver_type {\n\tstruct list_head pnfs_tblid;\n\tconst u32 id;\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int flags;\n\tunsigned int max_layoutget_response;\n\tint (*set_layoutdriver)(struct nfs_server *, const struct nfs_fh *);\n\tint (*clear_layoutdriver)(struct nfs_server *);\n\tstruct pnfs_layout_hdr * (*alloc_layout_hdr)(struct inode *, gfp_t);\n\tvoid (*free_layout_hdr)(struct pnfs_layout_hdr *);\n\tstruct pnfs_layout_segment * (*alloc_lseg)(struct pnfs_layout_hdr *, struct nfs4_layoutget_res *, gfp_t);\n\tvoid (*free_lseg)(struct pnfs_layout_segment *);\n\tvoid (*add_lseg)(struct pnfs_layout_hdr *, struct pnfs_layout_segment *, struct list_head *);\n\tvoid (*return_range)(struct pnfs_layout_hdr *, struct pnfs_layout_range *);\n\tconst struct nfs_pageio_ops *pg_read_ops;\n\tconst struct nfs_pageio_ops *pg_write_ops;\n\tstruct pnfs_ds_commit_info * (*get_ds_info)(struct inode *);\n\tint (*sync)(struct inode *, bool);\n\tenum pnfs_try_status (*read_pagelist)(struct nfs_pgio_header *);\n\tenum pnfs_try_status (*write_pagelist)(struct nfs_pgio_header *, int);\n\tvoid (*free_deviceid_node)(struct nfs4_deviceid_node *);\n\tstruct nfs4_deviceid_node * (*alloc_deviceid_node)(struct nfs_server *, struct pnfs_device *, gfp_t);\n\tint (*prepare_layoutreturn)(struct nfs4_layoutreturn_args *);\n\tvoid (*cleanup_layoutcommit)(struct nfs4_layoutcommit_data *);\n\tint (*prepare_layoutcommit)(struct nfs4_layoutcommit_args *);\n\tint (*prepare_layoutstats)(struct nfs42_layoutstat_args *);\n\tvoid (*cancel_io)(struct pnfs_layout_segment *);\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n\tlong: 32;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_device_id;\n\nstruct pnp_dev;\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_link;\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[18];\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tlong: 32;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct port_stats {\n\tlong unsigned int bytes_sent;\n\tlong unsigned int bytes_received;\n\tlong unsigned int bytes_discarded;\n};\n\nstruct ports_device;\n\nstruct port_buffer;\n\nstruct virtqueue;\n\nstruct port {\n\tstruct list_head list;\n\tstruct ports_device *portdev;\n\tstruct port_buffer *inbuf;\n\tspinlock_t inbuf_lock;\n\tspinlock_t outvq_lock;\n\tstruct virtqueue *in_vq;\n\tstruct virtqueue *out_vq;\n\tstruct dentry *debugfs_file;\n\tstruct port_stats stats;\n\tstruct console___2 cons;\n\tstruct cdev *cdev;\n\tstruct device *dev;\n\tstruct kref kref;\n\twait_queue_head_t waitqueue;\n\tchar *name;\n\tstruct fasync_struct *async_queue;\n\tu32 id;\n\tbool outvq_full;\n\tbool host_connected;\n\tbool guest_connected;\n};\n\nstruct port_buffer {\n\tchar *buf;\n\tsize_t size;\n\tsize_t len;\n\tsize_t offset;\n\tdma_addr_t dma;\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int sgpages;\n\tstruct scatterlist sg[0];\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct virtio_console_control {\n\t__virtio32 id;\n\t__virtio16 event;\n\t__virtio16 value;\n};\n\nstruct virtio_device;\n\nstruct ports_device {\n\tstruct list_head list;\n\tstruct work_struct control_work;\n\tstruct work_struct config_work;\n\tstruct list_head ports;\n\tspinlock_t ports_lock;\n\tspinlock_t c_ivq_lock;\n\tspinlock_t c_ovq_lock;\n\tu32 max_nr_ports;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *c_ivq;\n\tstruct virtqueue *c_ovq;\n\tstruct virtio_console_control cpkt;\n\tstruct virtqueue **in_vqs;\n\tstruct virtqueue **out_vqs;\n\tint chr_major;\n};\n\nstruct ports_driver_data {\n\tstruct dentry *debugfs_dir;\n\tstruct list_head portdevs;\n\tstruct list_head consoles;\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct power_supply_desc;\n\nstruct power_supply_battery_info;\n\nstruct power_supply {\n\tconst struct power_supply_desc *desc;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tchar **supplied_from;\n\tsize_t num_supplies;\n\tvoid *drv_data;\n\tstruct device dev;\n\tstruct work_struct changed_work;\n\tstruct delayed_work deferred_register_work;\n\tspinlock_t changed_lock;\n\tbool changed;\n\tbool update_groups;\n\tbool initialized;\n\tbool removing;\n\tatomic_t use_cnt;\n\tstruct power_supply_battery_info *battery_info;\n\tstruct rw_semaphore extensions_sem;\n\tstruct list_head extensions;\n};\n\nstruct power_supply_attr {\n\tconst char *prop_name;\n\tchar attr_name[31];\n\tstruct device_attribute dev_attr;\n\tconst char * const *text_values;\n\tint text_values_len;\n};\n\nstruct power_supply_maintenance_charge_table;\n\nstruct power_supply_battery_ocv_table;\n\nstruct power_supply_resistance_temp_table;\n\nstruct power_supply_vbat_ri_table;\n\nstruct power_supply_battery_info {\n\tunsigned int technology;\n\tint energy_full_design_uwh;\n\tint charge_full_design_uah;\n\tint voltage_min_design_uv;\n\tint voltage_max_design_uv;\n\tint tricklecharge_current_ua;\n\tint precharge_current_ua;\n\tint precharge_voltage_max_uv;\n\tint charge_term_current_ua;\n\tint charge_restart_voltage_uv;\n\tint overvoltage_limit_uv;\n\tint constant_charge_current_max_ua;\n\tint constant_charge_voltage_max_uv;\n\tconst struct power_supply_maintenance_charge_table *maintenance_charge;\n\tint maintenance_charge_size;\n\tint alert_low_temp_charge_current_ua;\n\tint alert_low_temp_charge_voltage_uv;\n\tint alert_high_temp_charge_current_ua;\n\tint alert_high_temp_charge_voltage_uv;\n\tint factory_internal_resistance_uohm;\n\tint factory_internal_resistance_charging_uohm;\n\tint ocv_temp[20];\n\tint temp_ambient_alert_min;\n\tint temp_ambient_alert_max;\n\tint temp_alert_min;\n\tint temp_alert_max;\n\tint temp_min;\n\tint temp_max;\n\tconst struct power_supply_battery_ocv_table *ocv_table[20];\n\tint ocv_table_size[20];\n\tconst struct power_supply_resistance_temp_table *resist_table;\n\tint resist_table_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_discharging;\n\tint vbat2ri_discharging_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_charging;\n\tint vbat2ri_charging_size;\n\tint bti_resistance_ohm;\n\tint bti_resistance_tolerance;\n};\n\nstruct power_supply_battery_ocv_table {\n\tint ocv;\n\tint capacity;\n};\n\nstruct power_supply_config {\n\tstruct fwnode_handle *fwnode;\n\tvoid *drv_data;\n\tconst struct attribute_group **attr_grp;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tbool no_wakeup_source;\n};\n\nunion power_supply_propval;\n\nstruct power_supply_desc {\n\tconst char *name;\n\tenum power_supply_type type;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tu32 usb_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, enum power_supply_property);\n\tvoid (*external_power_changed)(struct power_supply *);\n\tbool no_thermal;\n\tint use_for_apm;\n};\n\nstruct power_supply_ext {\n\tconst char * const name;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property);\n};\n\nstruct power_supply_ext_registration {\n\tstruct list_head list_head;\n\tconst struct power_supply_ext *ext;\n\tstruct device *dev;\n\tvoid *data;\n};\n\nstruct power_supply_maintenance_charge_table {\n\tint charge_current_max_ua;\n\tint charge_voltage_max_uv;\n\tint charge_safety_timer_minutes;\n};\n\nunion power_supply_propval {\n\tint intval;\n\tconst char *strval;\n};\n\nstruct power_supply_resistance_temp_table {\n\tint temp;\n\tint resistance;\n};\n\nstruct power_supply_vbat_ri_table {\n\tint vbat_uv;\n\tint ri_uohm;\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pps_bind_args {\n\tint tsformat;\n\tint edge;\n\tint consumer;\n};\n\nstruct pps_device;\n\nstruct pps_source_info {\n\tchar name[32];\n\tchar path[32];\n\tint mode;\n\tvoid (*echo)(struct pps_device *, int, void *);\n\tstruct module *owner;\n\tstruct device *dev;\n};\n\nstruct pps_ktime {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kparams {\n\tint api_version;\n\tint mode;\n\tstruct pps_ktime assert_off_tu;\n\tstruct pps_ktime clear_off_tu;\n};\n\nstruct pps_device {\n\tstruct pps_source_info info;\n\tstruct pps_kparams params;\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tunsigned int last_ev;\n\tunsigned int last_fetched_ev;\n\twait_queue_head_t queue;\n\tunsigned int id;\n\tconst void *lookup_cookie;\n\tstruct device dev;\n\tstruct fasync_struct *async_queue;\n\tspinlock_t lock;\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct pps_kinfo {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tlong: 32;\n};\n\nstruct pps_fdata {\n\tstruct pps_kinfo info;\n\tstruct pps_ktime timeout;\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n\tlong: 32;\n};\n\nstruct pre_voltage_change_data {\n\tlong unsigned int old_uV;\n\tlong unsigned int min_uV;\n\tlong unsigned int max_uV;\n};\n\nstruct prefix_cacheinfo {\n\t__u32 preferred_time;\n\t__u32 valid_time;\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\tunion {\n\t\t__u8 flags;\n\t\tstruct {\n\t\t\t__u8 reserved: 4;\n\t\t\t__u8 preferpd: 1;\n\t\t\t__u8 routeraddr: 1;\n\t\t\t__u8 autoconf: 1;\n\t\t\t__u8 onlink: 1;\n\t\t};\n\t};\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct prefixmsg {\n\tunsigned char prefix_family;\n\tunsigned char prefix_pad1;\n\tshort unsigned int prefix_pad2;\n\tint prefix_ifindex;\n\tunsigned char prefix_type;\n\tunsigned char prefix_len;\n\tunsigned char prefix_flags;\n\tunsigned char prefix_pad3;\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tlong: 32;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct proc_cpuinfo_notifier_args {\n\tstruct seq_file *m;\n\tlong unsigned int n;\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n\tlong: 32;\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tlong: 32;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tlong: 32;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_nfs_info {\n\tint flag;\n\tconst char *str;\n\tconst char *nostr;\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tlong: 32;\n\tstruct timespec64 val;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n\tstruct bin_attribute attr;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[2];\n\t\t} value;\n\t};\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n\tlong: 32;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psi_group {};\n\nstruct psmouse_protocol;\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct psy_am_i_supplied_data {\n\tstruct power_supply *psy;\n\tunsigned int count;\n};\n\nstruct psy_for_each_psy_cb_data {\n\tint (*fn)(struct power_supply *, void *);\n\tvoid *data;\n};\n\nstruct psy_get_supplier_prop_data {\n\tstruct power_supply *psy;\n\tenum power_supply_property psp;\n\tunion power_supply_propval *val;\n};\n\nstruct pt_regs {\n\tlong unsigned int args[8];\n\tlong unsigned int regs[32];\n\tlong unsigned int cp0_status;\n\tlong unsigned int hi;\n\tlong unsigned int lo;\n\tlong unsigned int cp0_badvaddr;\n\tlong unsigned int cp0_cause;\n\tlong unsigned int cp0_epc;\n\tlong unsigned int __last[0];\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\nstruct pt_watch_regs {\n\tenum pt_watch_style style;\n\tlong: 32;\n\tunion {\n\t\tstruct mips32_watch_regs mips32;\n\t\tstruct mips64_watch_regs mips64;\n\t};\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int pt_memcg_data;\n};\n\nstruct ptp_clock {\n\tstruct posix_clock clock;\n\tstruct device dev;\n\tstruct ptp_clock_info *info;\n\tdev_t devid;\n\tint index;\n\tstruct pps_device *pps_source;\n\tlong int dialed_frequency;\n\tstruct list_head tsevqs;\n\tspinlock_t tsevqs_lock;\n\tstruct mutex pincfg_mux;\n\twait_queue_head_t tsev_wq;\n\tint defunct;\n\tstruct device_attribute *pin_dev_attr;\n\tstruct attribute **pin_attr;\n\tstruct attribute_group pin_attr_group;\n\tconst struct attribute_group *pin_attr_groups[2];\n\tstruct kthread_worker *kworker;\n\tstruct kthread_delayed_work aux_work;\n\tunsigned int max_vclocks;\n\tunsigned int n_vclocks;\n\tint *vclock_index;\n\tstruct mutex n_vclocks_mux;\n\tbool is_virtual_clock;\n\tbool has_cycles;\n\tstruct dentry *debugfs_root;\n};\n\nstruct ptp_clock_caps {\n\tint max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint pps;\n\tint n_pins;\n\tint cross_timestamping;\n\tint adjust_phase;\n\tint max_phase_adj;\n\tint rsv[11];\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\ts64 offset;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_perout_request {\n\tunion {\n\t\tstruct ptp_clock_time start;\n\t\tstruct ptp_clock_time phase;\n\t};\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunion {\n\t\tstruct ptp_clock_time on;\n\t\tunsigned int rsv[4];\n\t};\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tlong: 32;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_extts_event {\n\tstruct ptp_clock_time t;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptp_sys_offset {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[51];\n};\n\nstruct ptp_sys_offset_extended {\n\tunsigned int n_samples;\n\t__kernel_clockid_t clockid;\n\tunsigned int rsv[2];\n\tstruct ptp_clock_time ts[75];\n};\n\nstruct ptp_sys_offset_precise {\n\tstruct ptp_clock_time device;\n\tstruct ptp_clock_time sys_realtime;\n\tstruct ptp_clock_time sys_monoraw;\n\tunsigned int rsv[4];\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n\tclockid_t clockid;\n\tlong: 32;\n};\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tlong: 32;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct ptp_vclock {\n\tstruct ptp_clock *pclock;\n\tstruct ptp_clock_info info;\n\tstruct ptp_clock *clock;\n\tstruct hlist_node vclock_hash_node;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct mutex lock;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t\tlong: 32;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tlong: 32;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n\tlong: 32;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong: 32;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tlong: 32;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct qnode {\n\tstruct mcs_spinlock mcs;\n};\n\nstruct qos_policer_conf {\n\tenum mscc_qos_rate_mode mode;\n\tbool dlb;\n\tbool cf;\n\tu32 cir;\n\tu32 cbs;\n\tu32 pir;\n\tu32 pbs;\n\tu8 ipg;\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quirk_entry {\n\tu16 vid;\n\tu16 pid;\n\tu32 flags;\n};\n\nstruct quirks_list_struct {\n\tstruct hid_device_id hid_bl_item;\n\tstruct list_head node;\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tlong: 32;\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n\tlong: 32;\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct ra_msg {\n\tstruct icmp6hdr icmph;\n\t__be32 reachable_time;\n\t__be32 retrans_timer;\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n\tlong: 32;\n};\n\nstruct raw6_frag_vec {\n\tstruct msghdr *msg;\n\tint hlen;\n\tchar c[4];\n};\n\nstruct raw6_sock {\n\tstruct inet_sock inet;\n\t__u32 checksum;\n\t__u32 offset;\n\tstruct icmp6_filter filter;\n\t__u32 ip6mr_table;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct numa_drop_counters drop_counters;\n\tstruct ipv6_pinfo inet6;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tlong: 32;\n\tlong: 32;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tlong: 32;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong: 32;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n\tlong: 32;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\traw_spinlock_t fqslock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[1];\n\tstruct rcu_node *level[2];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\tstruct in6_addr dest;\n\t__u8 opt[0];\n};\n\nstruct rdma_ah_init_attr {\n\tstruct rdma_ah_attr *ah_attr;\n\tu32 flags;\n\tstruct net_device *xmit_slave;\n};\n\nstruct rdma_counter {\n\tstruct rdma_restrack_entry res;\n\tstruct ib_device *device;\n\tuint32_t id;\n\tstruct kref kref;\n\tstruct rdma_counter_mode mode;\n\tstruct mutex lock;\n\tstruct rdma_hw_stats *stats;\n\tu32 port;\n};\n\nstruct rdma_stat_desc;\n\nstruct rdma_hw_stats {\n\tstruct mutex lock;\n\tlong unsigned int timestamp;\n\tlong unsigned int lifespan;\n\tconst struct rdma_stat_desc *descs;\n\tlong unsigned int *is_disabled;\n\tint num_counters;\n\tlong: 32;\n\tu64 value[0];\n};\n\nstruct rdma_link_ops {\n\tstruct list_head list;\n\tconst char *type;\n\tint (*newlink)(const char *, struct net_device *);\n};\n\nstruct rdma_netdev_alloc_params {\n\tsize_t sizeof_priv;\n\tunsigned int txqs;\n\tunsigned int rxqs;\n\tvoid *param;\n\tint (*initialize_rdma_netdev)(struct ib_device *, u32, struct net_device *, void *);\n};\n\nstruct rdma_stat_desc {\n\tconst char *name;\n\tunsigned int flags;\n\tconst void *priv;\n};\n\nstruct rdma_user_mmap_entry {\n\tstruct kref ref;\n\tstruct ib_ucontext *ucontext;\n\tlong unsigned int start_pgoff;\n\tsize_t npages;\n\tbool driver_removed;\n\tstruct mutex dmabufs_lock;\n\tstruct list_head dmabufs;\n};\n\nstruct read_plus_segment {\n\tenum data_content4 type;\n\tlong: 32;\n\tuint64_t offset;\n\tunion {\n\t\tstruct {\n\t\t\tuint64_t length;\n\t\t} hole;\n\t\tstruct {\n\t\t\tuint32_t length;\n\t\t\tunsigned int from;\n\t\t} data;\n\t};\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct readdir_callback {\n\tstruct dir_context ctx;\n\tstruct old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct reboot_mode_bits {\n\tu32 offset;\n\tu32 mask;\n\tu32 value;\n\tbool valid;\n};\n\nstruct reboot_data {\n\tstruct reboot_mode_bits mode_bits[4];\n\tstruct reboot_mode_bits catchall;\n};\n\nstruct reboot_mode_driver {\n\tstruct device *dev;\n\tstruct list_head head;\n\tint (*write)(struct reboot_mode_driver *, unsigned int);\n\tstruct notifier_block reboot_notifier;\n};\n\nstruct virtnet_rq_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t drops;\n\tu64_stats_t xdp_packets;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_redirects;\n\tu64_stats_t xdp_drops;\n\tu64_stats_t kicks;\n};\n\nstruct virtnet_interrupt_coalesce {\n\tu32 max_packets;\n\tu32 max_usecs;\n};\n\nstruct virtnet_rq_dma;\n\nstruct receive_queue {\n\tstruct virtqueue *vq;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tlong: 32;\n\tstruct virtnet_rq_stats stats;\n\tu16 calls;\n\tbool dim_enabled;\n\tstruct mutex dim_lock;\n\tlong: 32;\n\tstruct dim dim;\n\tu32 packets_in_napi;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct page *pages;\n\tstruct ewma_pkt_len mrg_avg_pkt_len;\n\tstruct page_frag alloc_frag;\n\tstruct scatterlist sg[19];\n\tunsigned int min_buf_len;\n\tchar name[16];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct virtnet_rq_dma *last_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xsk_rxq_info;\n\tstruct xdp_buff **xsk_buffs;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tlong unsigned int head_block;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\nstruct referring_call {\n\tuint32_t rc_sequenceid;\n\tuint32_t rc_slotid;\n};\n\nstruct referring_call_list {\n\tstruct nfs4_sessionid rcl_sessionid;\n\tuint32_t rcl_nrefcalls;\n\tstruct referring_call *rcl_refcalls;\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nstruct reg_val {\n\tu16 reg;\n\tu32 val;\n};\n\nstruct regcache_flat_data {\n\tlong unsigned int *valid;\n\tunsigned int data[0];\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tint (*populate)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regcache_rbtree_node;\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong unsigned int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\nstruct region_info_user {\n\t__u32 offset;\n\t__u32 erasesize;\n\t__u32 numblocks;\n\t__u32 regionindex;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\ts8 reg_shift;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct hwspinlock;\n\nstruct regmap_bus;\n\nstruct regmap_access_table;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_spinlock;\n\t\t\tlong unsigned int raw_spinlock_flags;\n\t\t};\n\t};\n\tstruct lock_class_key *lock_key;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tunsigned int reg_base;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool async;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool max_register_is_set;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tbool defer_caching;\n\tbool force_write_field;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool can_sleep;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regmap_range;\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_noinc_write)(void *, unsigned int, const void *, size_t);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_noinc_read)(void *, unsigned int, void *, size_t);\n\ntypedef void (*regmap_hw_free_context)(void *);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)(void);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tbool free_on_exit;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_noinc_write reg_noinc_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_reg_noinc_read reg_noinc_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint reg_shift;\n\tunsigned int reg_base;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tbool can_sleep;\n\tbool fast_io;\n\tbool io_port;\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tunsigned int max_register;\n\tbool max_register_is_0;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool use_relaxed_mmio;\n\tbool can_multi_write;\n\tbool use_hwlock;\n\tbool use_raw_spinlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tstruct list_head link;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_mmio_context {\n\tvoid *regs;\n\tunsigned int val_bytes;\n\tbool big_endian;\n\tbool attached_clk;\n\tstruct clk *clk;\n\tvoid (*reg_write)(struct regmap_mmio_context *, unsigned int, unsigned int);\n\tunsigned int (*reg_read)(struct regmap_mmio_context *, unsigned int);\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regulator_voltage {\n\tint min_uV;\n\tint max_uV;\n};\n\nstruct regulator {\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int always_on: 1;\n\tunsigned int bypass: 1;\n\tunsigned int device_link: 1;\n\tint uA_load;\n\tunsigned int enable_count;\n\tunsigned int deferred_disables;\n\tstruct regulator_voltage voltage[5];\n\tconst char *supply_name;\n\tstruct device_attribute dev_attr;\n\tstruct regulator_dev *rdev;\n\tstruct dentry *debugfs;\n};\n\nstruct regulator_bulk_devres {\n\tstruct regulator_bulk_data *consumers;\n\tint num_consumers;\n};\n\nstruct regulator_config {\n\tstruct device *dev;\n\tconst struct regulator_init_data *init_data;\n\tvoid *driver_data;\n\tstruct device_node *of_node;\n\tstruct regmap *regmap;\n\tstruct gpio_desc *ena_gpiod;\n};\n\nstruct regulator_consumer_supply {\n\tconst char *dev_name;\n\tconst char *supply;\n};\n\nstruct regulator_coupler {\n\tstruct list_head list;\n\tint (*attach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*detach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*balance_voltage)(struct regulator_coupler *, struct regulator_dev *, suspend_state_t);\n};\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n};\n\nstruct regulator_enable_gpio;\n\nstruct regulator_dev {\n\tconst struct regulator_desc *desc;\n\tint exclusive;\n\tu32 use_count;\n\tu32 open_count;\n\tu32 bypass_count;\n\tstruct list_head list;\n\tstruct list_head consumer_list;\n\tstruct coupling_desc coupling_desc;\n\tstruct blocking_notifier_head notifier;\n\tstruct ww_mutex mutex;\n\tstruct task_struct *mutex_owner;\n\tint ref_cnt;\n\tstruct module *owner;\n\tlong: 32;\n\tstruct device dev;\n\tstruct device bdev;\n\tstruct regulation_constraints *constraints;\n\tstruct regulator *supply;\n\tconst char *supply_name;\n\tstruct regmap *regmap;\n\tstruct delayed_work disable_work;\n\tvoid *reg_data;\n\tstruct dentry *debugfs;\n\tstruct regulator_enable_gpio *ena_pin;\n\tunsigned int ena_gpio_state: 1;\n\tunsigned int constraints_pending: 1;\n\tunsigned int is_switch: 1;\n\tlong: 32;\n\tktime_t last_off;\n\tint cached_err;\n\tbool use_cached_err;\n\tspinlock_t err_lock;\n\tint pw_requested_mW;\n\tstruct notifier_block supply_fwd_nb;\n\tlong: 32;\n};\n\nstruct regulator_enable_gpio {\n\tstruct list_head list;\n\tstruct gpio_desc *gpiod;\n\tu32 enable_count;\n\tu32 request_count;\n};\n\nstruct regulator_err_state {\n\tstruct regulator_dev *rdev;\n\tlong unsigned int notifs;\n\tlong unsigned int errors;\n\tint possible_errs;\n};\n\nstruct regulator_event_work {\n\tstruct work_struct work;\n\tstruct regulator_dev *rdev;\n\tlong unsigned int event;\n};\n\nstruct regulator_irq_data {\n\tstruct regulator_err_state *states;\n\tint num_states;\n\tvoid *data;\n\tlong int opaque;\n};\n\nstruct regulator_irq_desc {\n\tconst char *name;\n\tint fatal_cnt;\n\tint reread_ms;\n\tint irq_off_ms;\n\tbool skip_off;\n\tbool high_prio;\n\tvoid *data;\n\tint (*die)(struct regulator_irq_data *);\n\tint (*map_event)(int, struct regulator_irq_data *, long unsigned int *);\n\tint (*renable)(struct regulator_irq_data *);\n};\n\nstruct regulator_irq {\n\tstruct regulator_irq_data rdata;\n\tstruct regulator_irq_desc desc;\n\tint irq;\n\tint retry_cnt;\n\tstruct delayed_work isr_work;\n};\n\nstruct regulator_map {\n\tstruct list_head list;\n\tconst char *dev_name;\n\tconst char *supply;\n\tstruct regulator_dev *regulator;\n};\n\nstruct regulator_notifier_match {\n\tstruct regulator *regulator;\n\tstruct notifier_block *nb;\n};\n\nstruct regulator_ops {\n\tint (*list_voltage)(struct regulator_dev *, unsigned int);\n\tint (*set_voltage)(struct regulator_dev *, int, int, unsigned int *);\n\tint (*map_voltage)(struct regulator_dev *, int, int);\n\tint (*set_voltage_sel)(struct regulator_dev *, unsigned int);\n\tint (*get_voltage)(struct regulator_dev *);\n\tint (*get_voltage_sel)(struct regulator_dev *);\n\tint (*set_current_limit)(struct regulator_dev *, int, int);\n\tint (*get_current_limit)(struct regulator_dev *);\n\tint (*set_input_current_limit)(struct regulator_dev *, int);\n\tint (*set_over_current_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_over_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_under_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_thermal_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_active_discharge)(struct regulator_dev *, bool);\n\tint (*enable)(struct regulator_dev *);\n\tint (*disable)(struct regulator_dev *);\n\tint (*is_enabled)(struct regulator_dev *);\n\tint (*set_mode)(struct regulator_dev *, unsigned int);\n\tunsigned int (*get_mode)(struct regulator_dev *);\n\tint (*get_error_flags)(struct regulator_dev *, unsigned int *);\n\tint (*enable_time)(struct regulator_dev *);\n\tint (*set_ramp_delay)(struct regulator_dev *, int);\n\tint (*set_voltage_time)(struct regulator_dev *, int, int);\n\tint (*set_voltage_time_sel)(struct regulator_dev *, unsigned int, unsigned int);\n\tint (*set_soft_start)(struct regulator_dev *);\n\tint (*get_status)(struct regulator_dev *);\n\tunsigned int (*get_optimum_mode)(struct regulator_dev *, int, int, int);\n\tint (*set_load)(struct regulator_dev *, int);\n\tint (*set_bypass)(struct regulator_dev *, bool);\n\tint (*get_bypass)(struct regulator_dev *, bool *);\n\tint (*set_suspend_voltage)(struct regulator_dev *, int);\n\tint (*set_suspend_enable)(struct regulator_dev *);\n\tint (*set_suspend_disable)(struct regulator_dev *);\n\tint (*set_suspend_mode)(struct regulator_dev *, unsigned int);\n\tint (*resume)(struct regulator_dev *);\n\tint (*set_pull_down)(struct regulator_dev *);\n};\n\nstruct regulator_supply_alias {\n\tstruct list_head list;\n\tstruct device *src_dev;\n\tconst char *src_supply;\n\tstruct device *alias_dev;\n\tconst char *alias_supply;\n};\n\nstruct regulator_supply_alias_match {\n\tstruct device *dev;\n\tconst char *id;\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tlong: 32;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tlong: 32;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tlong: 32;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct rq_qos;\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tstruct device *dev;\n\tenum rpm_status rpm_status;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tlong unsigned int blkcg_pols[1];\n\tstruct blkcg_gq *root_blkg;\n\tstruct list_head blkg_list;\n\tstruct mutex blkcg_mutex;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\nstruct reserved_mem_ops;\n\nstruct reserved_mem {\n\tconst char *name;\n\tlong unsigned int fdt_node;\n\tconst struct reserved_mem_ops *ops;\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tvoid *priv;\n};\n\nstruct reserved_mem_ops {\n\tint (*device_init)(struct reserved_mem *, struct device *);\n\tvoid (*device_release)(struct reserved_mem *, struct device *);\n};\n\nstruct reset_control {\n\tstruct reset_controller_dev *rcdev;\n\tstruct list_head list;\n\tunsigned int id;\n\tstruct kref refcnt;\n\tbool acquired;\n\tbool shared;\n\tbool array;\n\tatomic_t deassert_count;\n\tatomic_t triggered_count;\n};\n\nstruct reset_control_array {\n\tstruct reset_control base;\n\tunsigned int num_rstcs;\n\tstruct reset_control *rstc[0];\n};\n\nstruct reset_control_bulk_data {\n\tconst char *id;\n\tstruct reset_control *rstc;\n};\n\nstruct reset_control_bulk_devres {\n\tint num_rstcs;\n\tstruct reset_control_bulk_data *rstcs;\n};\n\nstruct reset_control_ops {\n\tint (*reset)(struct reset_controller_dev *, long unsigned int);\n\tint (*assert)(struct reset_controller_dev *, long unsigned int);\n\tint (*deassert)(struct reset_controller_dev *, long unsigned int);\n\tint (*status)(struct reset_controller_dev *, long unsigned int);\n};\n\nstruct reset_props {\n\tconst char *syscon;\n\tu32 protect_reg;\n\tu32 vcore_protect;\n\tu32 if_si_owner_bit;\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t\tlong: 32;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tlong: 32;\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tlong: 32;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rmem_assigned_device {\n\tstruct device *dev;\n\tstruct reserved_mem *rmem;\n\tstruct list_head list;\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_gpio_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_gpio_data gpio_data;\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct romfs_super_block {\n\t__be32 word0;\n\t__be32 word1;\n\t__be32 size;\n\t__be32 checksum;\n\tchar name[0];\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tlong: 32;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tlong: 32;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct rpc_add_xprt_test {\n\tvoid (*add_xprt_test)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tvoid *data;\n};\n\nstruct rpc_auth_create_args {\n\trpc_authflavor_t pseudoflavor;\n\tconst char *target_name;\n};\n\nstruct rpc_authops {\n\tstruct module *owner;\n\trpc_authflavor_t au_flavor;\n\tchar *au_name;\n\tstruct rpc_auth * (*create)(const struct rpc_auth_create_args *, struct rpc_clnt *);\n\tvoid (*destroy)(struct rpc_auth *);\n\tint (*hash_cred)(struct auth_cred *, unsigned int);\n\tstruct rpc_cred * (*lookup_cred)(struct rpc_auth *, struct auth_cred *, int);\n\tstruct rpc_cred * (*crcreate)(struct rpc_auth *, struct auth_cred *, int, gfp_t);\n\trpc_authflavor_t (*info2flavor)(struct rpcsec_gss_info *);\n\tint (*flavor2info)(rpc_authflavor_t, struct rpcsec_gss_info *);\n\tint (*key_timeout)(struct rpc_auth *, struct rpc_cred *);\n\tint (*ping)(struct rpc_clnt *);\n};\n\nstruct rpc_bind_conn_calldata {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct rpc_buffer {\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct rpc_call_ops {\n\tvoid (*rpc_call_prepare)(struct rpc_task *, void *);\n\tvoid (*rpc_call_done)(struct rpc_task *, void *);\n\tvoid (*rpc_count_stats)(struct rpc_task *, void *);\n\tvoid (*rpc_release)(void *);\n};\n\nstruct rpc_xprt_switch;\n\nstruct rpc_cb_add_xprt_calldata {\n\tstruct rpc_xprt_switch *xps;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_pipe_dir_head {\n\tstruct list_head pdh_entries;\n\tstruct dentry *pdh_dentry;\n};\n\nstruct rpc_rtt {\n\tlong unsigned int timeo;\n\tlong unsigned int srtt[5];\n\tlong unsigned int sdrtt[5];\n\tint ntimeouts[5];\n};\n\nstruct rpc_timeout {\n\tlong unsigned int to_initval;\n\tlong unsigned int to_maxval;\n\tlong unsigned int to_increment;\n\tunsigned int to_retries;\n\tunsigned char to_exponential;\n};\n\nstruct rpc_xprt_iter_ops;\n\nstruct rpc_xprt_iter {\n\tstruct rpc_xprt_switch *xpi_xpswitch;\n\tstruct rpc_xprt *xpi_cursor;\n\tconst struct rpc_xprt_iter_ops *xpi_ops;\n};\n\nstruct rpc_iostats;\n\nstruct rpc_sysfs_client;\n\nstruct rpc_clnt {\n\trefcount_t cl_count;\n\tunsigned int cl_clid;\n\tstruct list_head cl_clients;\n\tstruct list_head cl_tasks;\n\tatomic_t cl_pid;\n\tspinlock_t cl_lock;\n\tstruct rpc_xprt *cl_xprt;\n\tconst struct rpc_procinfo *cl_procinfo;\n\tu32 cl_prog;\n\tu32 cl_vers;\n\tu32 cl_maxproc;\n\tstruct rpc_auth *cl_auth;\n\tstruct rpc_stat *cl_stats;\n\tstruct rpc_iostats *cl_metrics;\n\tunsigned int cl_softrtry: 1;\n\tunsigned int cl_softerr: 1;\n\tunsigned int cl_discrtry: 1;\n\tunsigned int cl_noretranstimeo: 1;\n\tunsigned int cl_autobind: 1;\n\tunsigned int cl_chatty: 1;\n\tunsigned int cl_shutdown: 1;\n\tunsigned int cl_netunreach_fatal: 1;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct rpc_rtt *cl_rtt;\n\tconst struct rpc_timeout *cl_timeout;\n\tatomic_t cl_swapper;\n\tint cl_nodelen;\n\tchar cl_nodename[65];\n\tstruct rpc_pipe_dir_head cl_pipedir_objects;\n\tstruct rpc_clnt *cl_parent;\n\tstruct rpc_rtt cl_rtt_default;\n\tstruct rpc_timeout cl_timeout_default;\n\tconst struct rpc_program *cl_program;\n\tconst char *cl_principal;\n\tstruct rpc_sysfs_client *cl_sysfs;\n\tunion {\n\t\tstruct rpc_xprt_iter cl_xpi;\n\t\tstruct work_struct cl_work;\n\t};\n\tconst struct cred *cl_cred;\n\tunsigned int cl_max_connect;\n\tstruct super_block *pipefs_sb;\n\tatomic_t cl_task_count;\n};\n\nstruct svc_xprt;\n\nstruct rpc_create_args {\n\tstruct net *net;\n\tint protocol;\n\tstruct sockaddr *address;\n\tsize_t addrsize;\n\tstruct sockaddr *saddress;\n\tconst struct rpc_timeout *timeout;\n\tconst char *servername;\n\tconst char *nodename;\n\tconst struct rpc_program *program;\n\tstruct rpc_stat *stats;\n\tu32 prognumber;\n\tu32 version;\n\trpc_authflavor_t authflavor;\n\tu32 nconnect;\n\tlong unsigned int flags;\n\tchar *client_name;\n\tstruct svc_xprt *bc_xprt;\n\tconst struct cred *cred;\n\tunsigned int max_connect;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct rpc_cred_cache {\n\tstruct hlist_head *hashtable;\n\tunsigned int hashbits;\n\tspinlock_t lock;\n};\n\nstruct rpc_credops {\n\tconst char *cr_name;\n\tint (*cr_init)(struct rpc_auth *, struct rpc_cred *);\n\tvoid (*crdestroy)(struct rpc_cred *);\n\tint (*crmatch)(struct auth_cred *, struct rpc_cred *, int);\n\tint (*crmarshal)(struct rpc_task *, struct xdr_stream *);\n\tint (*crrefresh)(struct rpc_task *);\n\tint (*crvalidate)(struct rpc_task *, struct xdr_stream *);\n\tint (*crwrap_req)(struct rpc_task *, struct xdr_stream *);\n\tint (*crunwrap_resp)(struct rpc_task *, struct xdr_stream *);\n\tint (*crkey_timeout)(struct rpc_cred *);\n\tchar * (*crstringify_acceptor)(struct rpc_cred *);\n\tbool (*crneed_reencode)(struct rpc_task *);\n};\n\nstruct rpc_filelist {\n\tconst char *name;\n\tconst struct file_operations *i_fop;\n\tumode_t mode;\n};\n\nstruct rpc_inode {\n\tstruct inode vfs_inode;\n\tvoid *private;\n\tstruct rpc_pipe *pipe;\n\twait_queue_head_t waitq;\n\tlong: 32;\n};\n\nstruct rpc_iostats {\n\tspinlock_t om_lock;\n\tlong unsigned int om_ops;\n\tlong unsigned int om_ntrans;\n\tlong unsigned int om_timeouts;\n\tlong long unsigned int om_bytes_sent;\n\tlong long unsigned int om_bytes_recv;\n\tktime_t om_queue;\n\tktime_t om_rtt;\n\tktime_t om_execute;\n\tlong unsigned int om_error_status;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rpc_pipe {\n\tstruct list_head pipe;\n\tstruct list_head in_upcall;\n\tstruct list_head in_downcall;\n\tint pipelen;\n\tint nreaders;\n\tint nwriters;\n\tint flags;\n\tstruct delayed_work queue_timeout;\n\tconst struct rpc_pipe_ops *ops;\n\tspinlock_t lock;\n\tstruct dentry *dentry;\n};\n\nstruct rpc_pipe_dir_object_ops {\n\tint (*create)(struct dentry *, struct rpc_pipe_dir_object *);\n\tvoid (*destroy)(struct dentry *, struct rpc_pipe_dir_object *);\n};\n\nstruct rpc_pipe_ops {\n\tssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char *, size_t);\n\tssize_t (*downcall)(struct file *, const char *, size_t);\n\tvoid (*release_pipe)(struct inode *);\n\tint (*open_pipe)(struct inode *);\n\tvoid (*destroy_msg)(struct rpc_pipe_msg *);\n};\n\ntypedef void (*kxdreproc_t)(struct rpc_rqst *, struct xdr_stream *, const void *);\n\ntypedef int (*kxdrdproc_t)(struct rpc_rqst *, struct xdr_stream *, void *);\n\nstruct rpc_procinfo {\n\tu32 p_proc;\n\tkxdreproc_t p_encode;\n\tkxdrdproc_t p_decode;\n\tunsigned int p_arglen;\n\tunsigned int p_replen;\n\tunsigned int p_timer;\n\tu32 p_statidx;\n\tconst char *p_name;\n};\n\nstruct rpc_program {\n\tconst char *name;\n\tu32 number;\n\tunsigned int nrvers;\n\tconst struct rpc_version **version;\n\tstruct rpc_stat *stats;\n\tconst char *pipe_dir_name;\n};\n\nstruct xdr_buf {\n\tstruct kvec head[1];\n\tstruct kvec tail[1];\n\tstruct bio_vec *bvec;\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int flags;\n\tunsigned int buflen;\n\tunsigned int len;\n};\n\nstruct rpc_rqst {\n\tstruct rpc_xprt *rq_xprt;\n\tstruct xdr_buf rq_snd_buf;\n\tstruct xdr_buf rq_rcv_buf;\n\tstruct rpc_task *rq_task;\n\tstruct rpc_cred *rq_cred;\n\t__be32 rq_xid;\n\tint rq_cong;\n\tu32 rq_seqnos[3];\n\tunsigned int rq_seqno_count;\n\tint rq_enc_pages_num;\n\tstruct page **rq_enc_pages;\n\tvoid (*rq_release_snd_buf)(struct rpc_rqst *);\n\tunion {\n\t\tstruct list_head rq_list;\n\t\tstruct rb_node rq_recv;\n\t};\n\tstruct list_head rq_xmit;\n\tstruct list_head rq_xmit2;\n\tvoid *rq_buffer;\n\tsize_t rq_callsize;\n\tvoid *rq_rbuffer;\n\tsize_t rq_rcvsize;\n\tsize_t rq_xmit_bytes_sent;\n\tsize_t rq_reply_bytes_recvd;\n\tstruct xdr_buf rq_private_buf;\n\tlong unsigned int rq_majortimeo;\n\tlong unsigned int rq_minortimeo;\n\tlong unsigned int rq_timeout;\n\tlong: 32;\n\tktime_t rq_rtt;\n\tunsigned int rq_retries;\n\tunsigned int rq_connect_cookie;\n\tatomic_t rq_pin;\n\tu32 rq_bytes_sent;\n\tktime_t rq_xtime;\n\tint rq_ntrans;\n\tstruct lwq_node rq_bc_list;\n\tlong unsigned int rq_bc_pa_state;\n\tstruct list_head rq_bc_pa_list;\n\tlong: 32;\n};\n\nstruct rpc_sysfs_client {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_clnt *clnt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt {\n\tstruct kobject kobject;\n\tstruct rpc_xprt *xprt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt_switch {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_xprt_switch *xprt_switch;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_task_setup {\n\tstruct rpc_task *task;\n\tstruct rpc_clnt *rpc_client;\n\tstruct rpc_xprt *rpc_xprt;\n\tstruct rpc_cred *rpc_op_cred;\n\tconst struct rpc_message *rpc_message;\n\tconst struct rpc_call_ops *callback_ops;\n\tvoid *callback_data;\n\tstruct workqueue_struct *workqueue;\n\tshort unsigned int flags;\n\tsigned char priority;\n};\n\nstruct rpc_version {\n\tu32 number;\n\tunsigned int nrprocs;\n\tconst struct rpc_procinfo *procs;\n\tunsigned int *counts;\n};\n\nstruct rpc_xprt_ops;\n\nstruct xprt_class;\n\nstruct rpc_xprt {\n\tstruct kref kref;\n\tconst struct rpc_xprt_ops *ops;\n\tunsigned int id;\n\tconst struct rpc_timeout *timeout;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tint prot;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tsize_t max_payload;\n\tstruct rpc_wait_queue binding;\n\tstruct rpc_wait_queue sending;\n\tstruct rpc_wait_queue pending;\n\tstruct rpc_wait_queue backlog;\n\tstruct list_head free;\n\tunsigned int max_reqs;\n\tunsigned int min_reqs;\n\tunsigned int num_reqs;\n\tlong unsigned int state;\n\tunsigned char resvport: 1;\n\tunsigned char reuseport: 1;\n\tatomic_t swapper;\n\tunsigned int bind_index;\n\tstruct list_head xprt_switch;\n\tlong unsigned int bind_timeout;\n\tlong unsigned int reestablish_timeout;\n\tstruct xprtsec_parms xprtsec;\n\tunsigned int connect_cookie;\n\tstruct work_struct task_cleanup;\n\tstruct timer_list timer;\n\tlong unsigned int last_used;\n\tlong unsigned int idle_timeout;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int max_reconnect_timeout;\n\tatomic_long_t queuelen;\n\tspinlock_t transport_lock;\n\tspinlock_t reserve_lock;\n\tspinlock_t queue_lock;\n\tu32 xid;\n\tstruct rpc_task *snd_task;\n\tstruct list_head xmit_queue;\n\tatomic_long_t xmit_queuelen;\n\tstruct svc_xprt *bc_xprt;\n\tstruct svc_serv *bc_serv;\n\tunsigned int bc_alloc_max;\n\tunsigned int bc_alloc_count;\n\tatomic_t bc_slot_count;\n\tspinlock_t bc_pa_lock;\n\tstruct list_head bc_pa_list;\n\tstruct rb_root recv_queue;\n\tlong: 32;\n\tstruct {\n\t\tlong unsigned int bind_count;\n\t\tlong unsigned int connect_count;\n\t\tlong unsigned int connect_start;\n\t\tlong unsigned int connect_time;\n\t\tlong unsigned int sends;\n\t\tlong unsigned int recvs;\n\t\tlong unsigned int bad_xids;\n\t\tlong unsigned int max_slots;\n\t\tlong long unsigned int req_u;\n\t\tlong long unsigned int bklog_u;\n\t\tlong long unsigned int sending_u;\n\t\tlong long unsigned int pending_u;\n\t} stat;\n\tstruct net *xprt_net;\n\tnetns_tracker ns_tracker;\n\tconst char *servername;\n\tconst char *address_strings[6];\n\tstruct callback_head rcu;\n\tconst struct xprt_class *xprt_class;\n\tstruct rpc_sysfs_xprt *xprt_sysfs;\n\tbool main;\n\tlong: 32;\n};\n\nstruct rpc_xprt_iter_ops {\n\tvoid (*xpi_rewind)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_xprt)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_next)(struct rpc_xprt_iter *);\n};\n\nstruct rpc_xprt_ops {\n\tvoid (*set_buffer_size)(struct rpc_xprt *, size_t, size_t);\n\tint (*reserve_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*alloc_slot)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*free_slot)(struct rpc_xprt *, struct rpc_rqst *);\n\tvoid (*rpcbind)(struct rpc_task *);\n\tvoid (*set_port)(struct rpc_xprt *, short unsigned int);\n\tvoid (*connect)(struct rpc_xprt *, struct rpc_task *);\n\tint (*get_srcaddr)(struct rpc_xprt *, char *, size_t);\n\tshort unsigned int (*get_srcport)(struct rpc_xprt *);\n\tint (*buf_alloc)(struct rpc_task *);\n\tvoid (*buf_free)(struct rpc_task *);\n\tint (*prepare_request)(struct rpc_rqst *, struct xdr_buf *);\n\tint (*send_request)(struct rpc_rqst *);\n\tvoid (*abort_send_request)(struct rpc_rqst *);\n\tvoid (*wait_for_reply_request)(struct rpc_task *);\n\tvoid (*timer)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_request)(struct rpc_task *);\n\tvoid (*close)(struct rpc_xprt *);\n\tvoid (*destroy)(struct rpc_xprt *);\n\tvoid (*set_connect_timeout)(struct rpc_xprt *, long unsigned int, long unsigned int);\n\tvoid (*print_stats)(struct rpc_xprt *, struct seq_file *);\n\tint (*enable_swap)(struct rpc_xprt *);\n\tvoid (*disable_swap)(struct rpc_xprt *);\n\tvoid (*inject_disconnect)(struct rpc_xprt *);\n\tint (*bc_setup)(struct rpc_xprt *, unsigned int);\n\tsize_t (*bc_maxpayload)(struct rpc_xprt *);\n\tunsigned int (*bc_num_slots)(struct rpc_xprt *);\n\tvoid (*bc_free_rqst)(struct rpc_rqst *);\n\tvoid (*bc_destroy)(struct rpc_xprt *, unsigned int);\n};\n\nstruct rpc_xprt_switch {\n\tspinlock_t xps_lock;\n\tstruct kref xps_kref;\n\tunsigned int xps_id;\n\tunsigned int xps_nxprts;\n\tunsigned int xps_nactive;\n\tunsigned int xps_nunique_destaddr_xprts;\n\tatomic_long_t xps_queuelen;\n\tstruct list_head xps_xprt_list;\n\tstruct net *xps_net;\n\tconst struct rpc_xprt_iter_ops *xps_iter_ops;\n\tstruct rpc_sysfs_xprt_switch *xps_sysfs;\n\tstruct callback_head xps_rcu;\n};\n\nstruct rpcb_info {\n\tu32 rpc_vers;\n\tconst struct rpc_procinfo *rpc_proc;\n};\n\nstruct rpcbind_args {\n\tstruct rpc_xprt *r_xprt;\n\tu32 r_prog;\n\tu32 r_vers;\n\tu32 r_prot;\n\tshort unsigned int r_port;\n\tconst char *r_netid;\n\tconst char *r_addr;\n\tconst char *r_owner;\n\tint r_status;\n};\n\nstruct rpmb_descr {\n\tenum rpmb_type type;\n\tint (*route_frames)(struct device *, u8 *, unsigned int, u8 *, unsigned int);\n\tu8 *dev_id;\n\tsize_t dev_id_len;\n\tu16 reliable_wr_count;\n\tu16 capacity;\n};\n\nstruct rpmb_dev {\n\tstruct device dev;\n\tint id;\n\tstruct list_head list_node;\n\tstruct rpmb_descr descr;\n};\n\nstruct rpmb_frame {\n\tu8 stuff[196];\n\tu8 key_mac[32];\n\tu8 data[256];\n\tu8 nonce[16];\n\t__be32 write_counter;\n\t__be16 addr;\n\t__be16 block_count;\n\t__be16 result;\n\t__be16 req_resp;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[4];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tlong: 32;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tlong: 32;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n\tlong: 32;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tlong: 32;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n\tlong: 32;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tlong: 32;\n\tcall_single_data_t nohz_csd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tlong: 32;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 clock_pelt_idle_copy;\n\tu64 clock_idle_copy;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tcpumask_var_t scratch_mask;\n\tlong: 32;\n\tlong: 32;\n\tcall_single_data_t cfsb_csd;\n\tstruct list_head cfsb_csd_list;\n\tatomic_t nr_iowait;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\nstruct rq_wait;\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n\tlong: 32;\n};\n\nstruct rs_msg {\n\tstruct icmp6hdr icmph;\n\t__u8 opt[0];\n};\n\nstruct rsc {\n\tstruct cache_head h;\n\tstruct xdr_netobj handle;\n\tstruct svc_cred cred;\n\tstruct gss_svc_seq_data seqdata;\n\tstruct gss_ctx *mechctx;\n\tstruct callback_head callback_head;\n\tlong: 32;\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tlong: 32;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rsi {\n\tstruct cache_head h;\n\tstruct xdr_netobj in_handle;\n\tstruct xdr_netobj in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tint major_status;\n\tint minor_status;\n\tstruct callback_head callback_head;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rsvd_count {\n\tint ndelayed;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct rt0_hdr {\n\tstruct ipv6_rt_hdr rt_hdr;\n\t__u32 reserved;\n\tstruct in6_addr addr[0];\n};\n\nstruct rt6_exception {\n\tstruct hlist_node hlist;\n\tstruct rt6_info *rt6i;\n\tlong unsigned int stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct rt6_mtu_change_arg {\n\tstruct net_device *dev;\n\tunsigned int mtu;\n\tstruct fib6_info *f6i;\n};\n\nstruct rt6_nh {\n\tstruct fib6_info *fib6_info;\n\tstruct fib6_config r_cfg;\n\tstruct list_head list;\n};\n\nstruct rt6_rtnl_dump_arg {\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct net *net;\n\tstruct fib_dump_filter filter;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\t__kernel_size_t ss_size;\n\tint ss_flags;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct sigcontext {\n\tunsigned int sc_regmask;\n\tunsigned int sc_status;\n\tlong long unsigned int sc_pc;\n\tlong long unsigned int sc_regs[32];\n\tlong long unsigned int sc_fpregs[32];\n\tunsigned int sc_acx;\n\tunsigned int sc_fpc_csr;\n\tunsigned int sc_fpc_eir;\n\tunsigned int sc_used_math;\n\tunsigned int sc_dsp;\n\tlong: 32;\n\tlong long unsigned int sc_mdhi;\n\tlong long unsigned int sc_mdlo;\n\tlong unsigned int sc_hi1;\n\tlong unsigned int sc_lo1;\n\tlong unsigned int sc_hi2;\n\tlong unsigned int sc_lo2;\n\tlong unsigned int sc_hi3;\n\tlong unsigned int sc_lo3;\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tlong: 32;\n\tstruct sigcontext uc_mcontext;\n\tsigset_t uc_sigmask;\n\tlong long unsigned int uc_extcontext[0];\n};\n\nstruct rt_sigframe {\n\tu32 rs_ass[4];\n\tu32 rs_pad[2];\n\tstruct siginfo rs_info;\n\tstruct ucontext rs_uc;\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rtc_time;\n\nstruct rtc_wkalrm;\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n\tlong: 32;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tlong: 32;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\tlong: 32;\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n\tlong: 32;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n\tlong: 32;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct s3_save {\n\tu32 command;\n\tu32 dev_nt;\n\tu64 dcbaa_ptr;\n\tu32 config_reg;\n\tlong: 32;\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tlong: 32;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tlong: 32;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_avg avg;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tlong: 32;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_info {};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct sched_statistics {};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scomp_alg {\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_acomp_streams streams;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tunion {\n\t\tvoid *src;\n\t\tlong unsigned int saddr;\n\t};\n};\n\nstruct scratch {\n\tu8 status[29];\n\tu8 data_token;\n\t__be16 crc_val;\n};\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n\tlong: 32;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tlong: 32;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_sense_hdr;\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tlong: 32;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tlong: 32;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tlong: 32;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 ic_enable: 1;\n\tu8 cs_enble: 1;\n\tu8 st_enble: 1;\n\tu8 reserved1: 3;\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved2[3];\n\tu8 lbm_descriptor_type: 4;\n\tu8 rlbsr: 2;\n\tu8 reserved3: 1;\n\tu8 acdlu: 1;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_proc_entry {\n\tstruct list_head entry;\n\tconst struct scsi_host_template *sht;\n\tstruct proc_dir_entry *proc_dir;\n\tunsigned int present;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 reserved1: 7;\n\tu8 perm: 1;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 rel_lifetime: 6;\n\tu8 reserved3: 2;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tlong: 32;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n\tlong: 32;\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tlong: 32;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tlong: 32;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tlong: 32;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tlong: 32;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\tlong: 32;\n\ts64 exit_code;\n\tconst char *reason;\n\tlong: 32;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct seq_buf;\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tlong: 32;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\tlong: 32;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n\tlong: 32;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[2];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tlong: 32;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work error_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tlong: 32;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tlong: 32;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n\tlong: 32;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n\tlong: 32;\n};\n\nstruct sd_app_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct sd_busy_data {\n\tstruct mmc_card *card;\n\tu8 *reg_buf;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct sd_uhs2_wait_active_state_data {\n\tstruct mmc_host *host;\n\tstruct mmc_command *cmd;\n};\n\nstruct sdhci_adma2_64_desc {\n\t__le16 cmd;\n\t__le16 len;\n\t__le32 addr_lo;\n\t__le32 addr_hi;\n};\n\nstruct sdhci_ops;\n\nstruct sdhci_host {\n\tconst char *hw_name;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tint irq;\n\tvoid *ioaddr;\n\tphys_addr_t mapbase;\n\tchar *bounce_buffer;\n\tdma_addr_t bounce_addr;\n\tunsigned int bounce_buffer_size;\n\tconst struct sdhci_ops *ops;\n\tstruct mmc_host *mmc;\n\tstruct mmc_host_ops mmc_host_ops;\n\tu64 dma_mask;\n\tstruct led_classdev led;\n\tchar led_name[32];\n\tspinlock_t lock;\n\tint flags;\n\tunsigned int version;\n\tunsigned int max_clk;\n\tunsigned int timeout_clk;\n\tu8 max_timeout_count;\n\tunsigned int clk_mul;\n\tunsigned int clock;\n\tu8 pwr;\n\tu8 drv_type;\n\tbool reinit_uhs;\n\tbool runtime_suspended;\n\tbool bus_on;\n\tbool preset_enabled;\n\tbool pending_reset;\n\tbool irq_wake_enabled;\n\tbool v4_mode;\n\tbool use_external_dma;\n\tbool always_defer_done;\n\tstruct mmc_request *mrqs_done[2];\n\tstruct mmc_command *cmd;\n\tstruct mmc_command *data_cmd;\n\tstruct mmc_command *deferred_cmd;\n\tstruct mmc_data *data;\n\tunsigned int data_early: 1;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int blocks;\n\tint sg_count;\n\tint max_adma;\n\tvoid *adma_table;\n\tvoid *align_buffer;\n\tsize_t adma_table_sz;\n\tsize_t align_buffer_sz;\n\tdma_addr_t adma_addr;\n\tdma_addr_t align_addr;\n\tunsigned int desc_sz;\n\tunsigned int alloc_desc_sz;\n\tstruct workqueue_struct *complete_wq;\n\tstruct work_struct complete_work;\n\tstruct timer_list timer;\n\tstruct timer_list data_timer;\n\tvoid (*complete_work_fn)(struct work_struct *);\n\tirqreturn_t (*thread_irq_fn)(int, void *);\n\tu32 caps;\n\tu32 caps1;\n\tbool read_caps;\n\tbool sdhci_core_to_disable_vqmmc;\n\tunsigned int ocr_avail_sdio;\n\tunsigned int ocr_avail_sd;\n\tunsigned int ocr_avail_mmc;\n\tu32 ocr_mask;\n\tunsigned int timing;\n\tu32 thread_isr;\n\tu32 ier;\n\tbool cqe_on;\n\tu32 cqe_ier;\n\tu32 cqe_err_ier;\n\twait_queue_head_t buf_ready_int;\n\tunsigned int tuning_done;\n\tunsigned int tuning_count;\n\tunsigned int tuning_mode;\n\tunsigned int tuning_err;\n\tint tuning_delay;\n\tint tuning_loop_count;\n\tu32 sdma_boundary;\n\tu32 adma_table_cnt;\n\tu64 data_timeout;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct sdhci_ops {\n\tu32 (*read_l)(struct sdhci_host *, int);\n\tu16 (*read_w)(struct sdhci_host *, int);\n\tu8 (*read_b)(struct sdhci_host *, int);\n\tvoid (*write_l)(struct sdhci_host *, u32, int);\n\tvoid (*write_w)(struct sdhci_host *, u16, int);\n\tvoid (*write_b)(struct sdhci_host *, u8, int);\n\tvoid (*set_clock)(struct sdhci_host *, unsigned int);\n\tvoid (*set_power)(struct sdhci_host *, unsigned char, short unsigned int);\n\tu32 (*irq)(struct sdhci_host *, u32);\n\tint (*set_dma_mask)(struct sdhci_host *);\n\tint (*enable_dma)(struct sdhci_host *);\n\tunsigned int (*get_max_clock)(struct sdhci_host *);\n\tunsigned int (*get_min_clock)(struct sdhci_host *);\n\tunsigned int (*get_timeout_clock)(struct sdhci_host *);\n\tunsigned int (*get_max_timeout_count)(struct sdhci_host *);\n\tvoid (*set_timeout)(struct sdhci_host *, struct mmc_command *);\n\tvoid (*set_bus_width)(struct sdhci_host *, int);\n\tvoid (*platform_send_init_74_clocks)(struct sdhci_host *, u8);\n\tunsigned int (*get_ro)(struct sdhci_host *);\n\tvoid (*reset)(struct sdhci_host *, u8);\n\tint (*platform_execute_tuning)(struct sdhci_host *, u32);\n\tvoid (*set_uhs_signaling)(struct sdhci_host *, unsigned int);\n\tvoid (*hw_reset)(struct sdhci_host *);\n\tvoid (*adma_workaround)(struct sdhci_host *, u32);\n\tvoid (*card_event)(struct sdhci_host *);\n\tvoid (*voltage_switch)(struct sdhci_host *);\n\tvoid (*adma_write_desc)(struct sdhci_host *, void **, dma_addr_t, int, unsigned int);\n\tvoid (*copy_to_bounce_buffer)(struct sdhci_host *, struct mmc_data *, unsigned int);\n\tvoid (*request_done)(struct sdhci_host *, struct mmc_request *);\n\tvoid (*dump_vendor_regs)(struct sdhci_host *);\n\tvoid (*dump_uhs2_regs)(struct sdhci_host *);\n\tvoid (*uhs2_pre_detect_init)(struct sdhci_host *);\n};\n\nstruct sdhci_pci_fixes;\n\nstruct sdhci_pci_slot;\n\nstruct sdhci_pci_chip {\n\tstruct pci_dev *pdev;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tbool allow_runtime_pm;\n\tbool pm_retune;\n\tbool rpm_retune;\n\tconst struct sdhci_pci_fixes *fixes;\n\tint num_slots;\n\tstruct sdhci_pci_slot *slots[8];\n};\n\nstruct sdhci_pci_fixes {\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tbool allow_runtime_pm;\n\tbool own_cd_for_runtime_pm;\n\tint (*probe)(struct sdhci_pci_chip *);\n\tint (*probe_slot)(struct sdhci_pci_slot *);\n\tint (*add_host)(struct sdhci_pci_slot *);\n\tvoid (*remove_slot)(struct sdhci_pci_slot *, int);\n\tvoid (*remove_host)(struct sdhci_pci_slot *, int);\n\tint (*suspend)(struct sdhci_pci_chip *);\n\tint (*resume)(struct sdhci_pci_chip *);\n\tint (*runtime_suspend)(struct sdhci_pci_chip *);\n\tint (*runtime_resume)(struct sdhci_pci_chip *);\n\tconst struct sdhci_ops *ops;\n\tconst struct dmi_system_id *cd_gpio_override;\n\tsize_t priv_size;\n};\n\nstruct sdhci_pci_slot {\n\tstruct sdhci_pci_chip *chip;\n\tstruct sdhci_host *host;\n\tint cd_idx;\n\tbool cd_override_level;\n\tvoid (*hw_reset)(struct sdhci_host *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct sdio_device_id {\n\t__u8 class;\n\t__u16 vendor;\n\t__u16 device;\n\tkernel_ulong_t driver_data;\n};\n\nstruct sdio_driver {\n\tchar *name;\n\tconst struct sdio_device_id *id_table;\n\tint (*probe)(struct sdio_func *, const struct sdio_device_id *);\n\tvoid (*remove)(struct sdio_func *);\n\tvoid (*shutdown)(struct sdio_func *);\n\tstruct device_driver drv;\n};\n\ntypedef void sdio_irq_handler_t(struct sdio_func *);\n\nstruct sdio_func {\n\tstruct mmc_card *card;\n\tlong: 32;\n\tstruct device dev;\n\tsdio_irq_handler_t *irq_handler;\n\tunsigned int num;\n\tunsigned char class;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tunsigned int max_blksize;\n\tunsigned int cur_blksize;\n\tunsigned int enable_timeout;\n\tunsigned int state;\n\tu8 *tmpbuf;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n\tlong: 32;\n};\n\nstruct sdio_func_tuple {\n\tstruct sdio_func_tuple *next;\n\tunsigned char code;\n\tunsigned char size;\n\tunsigned char data[0];\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct xfrm_state;\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tlong: 32;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n\tlong: 32;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tlong: 32;\n\ttime64_t sem_otime;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sembuf;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\tlong unsigned int sem_otime;\n\tlong unsigned int sem_ctime;\n\tlong unsigned int sem_nsems;\n\tlong unsigned int sem_otime_high;\n\tlong unsigned int sem_ctime_high;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct virtnet_sq_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_tx_drops;\n\tu64_stats_t kicks;\n\tu64_stats_t tx_timeouts;\n\tu64_stats_t stop;\n\tu64_stats_t wake;\n};\n\nstruct send_queue {\n\tstruct virtqueue *vq;\n\tstruct scatterlist sg[19];\n\tchar name[16];\n\tlong: 32;\n\tstruct virtnet_sq_stats stats;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct napi_struct napi;\n\tbool reset;\n\tstruct xsk_buff_pool *xsk_pool;\n\tdma_addr_t xsk_hdr_dma_addr;\n\tlong: 32;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct serial_ctrl_device {\n\tstruct device dev;\n\tstruct ida port_ida;\n\tlong: 32;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_port_device {\n\tstruct device dev;\n\tstruct uart_port *port;\n\tunsigned int tx_enabled: 1;\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\ntypedef struct serio *class_serio_pause_rx_t;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n\tlong: 32;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nstruct serport {\n\tstruct tty_struct *tty;\n\twait_queue_head_t wait;\n\tstruct serio *serio;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_config_request {\n\tstruct usb_device *udev;\n\tint config;\n\tstruct work_struct work;\n\tstruct list_head node;\n};\n\nstruct sfdp {\n\tsize_t num_dwords;\n\tu32 *dwords;\n};\n\nstruct sfdp_4bait {\n\tu32 hwcaps;\n\tu32 supported_bit;\n};\n\nstruct sfdp_bfpt {\n\tu32 dwords[20];\n};\n\nstruct sfdp_bfpt_erase {\n\tu32 dword;\n\tu32 shift;\n};\n\nstruct sfdp_bfpt_read {\n\tu32 hwcaps;\n\tu32 supported_dword;\n\tu32 supported_bit;\n\tu32 settings_dword;\n\tu32 settings_shift;\n\tenum spi_nor_protocol proto;\n};\n\nstruct sfdp_parameter_header {\n\tu8 id_lsb;\n\tu8 minor;\n\tu8 major;\n\tu8 length;\n\tu8 parameter_table_pointer[3];\n\tu8 id_msb;\n};\n\nstruct sfdp_header {\n\tu32 signature;\n\tu8 minor;\n\tu8 major;\n\tu8 nph;\n\tu8 unused;\n\tstruct sfdp_parameter_header bfpt_header;\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_module_caps {\n\tlong unsigned int interfaces[2];\n\tlong unsigned int link_modes[4];\n\tbool may_have_phy;\n\tu8 port;\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *, struct phy_device *);\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_list {\n\tunsigned int n;\n\tunsigned int size;\n\tsize_t len;\n\tstruct scatterlist *sg;\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sgttyb {\n\tchar sg_ispeed;\n\tchar sg_ospeed;\n\tchar sg_erase;\n\tchar sg_kill;\n\tint sg_flags;\n};\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha384_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct sha512_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct shared_policy {};\n\nstruct shash_desc;\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*export_core)(struct shash_desc *, void *);\n\tint (*import_core)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tint (*clone_tfm)(struct crypto_shash *, struct crypto_shash *);\n\tunsigned int descsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int digestsize;\n\t\t\tunsigned int statesize;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct hash_alg_common halg;\n\t};\n};\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[256];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tlong: 32;\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tlong: 32;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tlong: 32;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\t__kernel_size_t shm_segsz;\n\tlong unsigned int shm_atime;\n\tlong unsigned int shm_dtime;\n\tlong unsigned int shm_ctime;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tshort unsigned int shm_atime_high;\n\tshort unsigned int shm_dtime_high;\n\tshort unsigned int shm_ctime_high;\n\tshort unsigned int __unused1;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\tlong: 32;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct shortname_info {\n\tunsigned char lower: 1;\n\tunsigned char upper: 1;\n\tunsigned char valid: 1;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tint id;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct shrinker_info_unit;\n\nstruct shrinker_info {\n\tstruct callback_head rcu;\n\tint map_nr_max;\n\tstruct shrinker_info_unit *unit[0];\n};\n\nstruct shrinker_info_unit {\n\tatomic_long_t nr_deferred[32];\n\tlong unsigned int map[1];\n};\n\nstruct sig_alg {\n\tint (*sign)(struct crypto_sig *, const void *, unsigned int, void *, unsigned int);\n\tint (*verify)(struct crypto_sig *, const void *, unsigned int, const void *, unsigned int);\n\tint (*set_pub_key)(struct crypto_sig *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_sig *, const void *, unsigned int);\n\tunsigned int (*key_size)(struct crypto_sig *);\n\tunsigned int (*digest_size)(struct crypto_sig *);\n\tunsigned int (*max_size)(struct crypto_sig *);\n\tint (*init)(struct crypto_sig *);\n\tvoid (*exit)(struct crypto_sig *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct sig_instance {\n\tvoid (*free)(struct sig_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t};\n\t\tstruct sig_alg alg;\n\t};\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[13];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sigframe {\n\tu32 sf_ass[4];\n\tu32 sf_pad[2];\n\tstruct sigcontext sf_sc;\n\tsigset_t sf_mask;\n\tlong long unsigned int sf_extcontext[0];\n};\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[128];\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {};\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tlong: 32;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tstruct autogroup *autogroup;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n\tlong: 32;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_pm_bus {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct sit_net {\n\tstruct ip_tunnel *tunnels_r_l[16];\n\tstruct ip_tunnel *tunnels_r[16];\n\tstruct ip_tunnel *tunnels_l[16];\n\tstruct ip_tunnel *tunnels_wc[1];\n\tstruct ip_tunnel **tunnels[4];\n\tstruct net_device *fb_tunnel_dev;\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n\tlong: 32;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tlong: 32;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*export)(struct skcipher_request *, void *);\n\tint (*import)(struct skcipher_request *, const void *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int walksize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int min_keysize;\n\t\t\tunsigned int max_keysize;\n\t\t\tunsigned int ivsize;\n\t\t\tunsigned int chunksize;\n\t\t\tunsigned int statesize;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct skcipher_alg_common co;\n\t};\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[256];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int nbytes;\n\tunsigned int total;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int obj_exts;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabobj_ext {\n\tstruct obj_cgroup *objcg;\n\tlong: 32;\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct smsc911x_platform_config {\n\tunsigned int irq_polarity;\n\tunsigned int irq_type;\n\tunsigned int flags;\n\tunsigned int shift;\n\tphy_interface_t phy_interface;\n\tunsigned char mac[6];\n};\n\nstruct smsc911x_ops;\n\nstruct smsc911x_data {\n\tvoid *ioaddr;\n\tunsigned int idrev;\n\tunsigned int generation;\n\tstruct smsc911x_platform_config config;\n\tspinlock_t mac_lock;\n\tspinlock_t dev_lock;\n\tstruct mii_bus *mii_bus;\n\tunsigned int using_extphy;\n\tint last_duplex;\n\tint last_carrier;\n\tu32 msg_enable;\n\tunsigned int gpio_setting;\n\tunsigned int gpio_orig_setting;\n\tstruct net_device *dev;\n\tstruct napi_struct napi;\n\tunsigned int software_irq_signal;\n\tchar loopback_tx_pkt[64];\n\tchar loopback_rx_pkt[64];\n\tunsigned int resetcount;\n\tunsigned int multicast_update_pending;\n\tunsigned int set_bits_mask;\n\tunsigned int clear_bits_mask;\n\tunsigned int hashhi;\n\tunsigned int hashlo;\n\tconst struct smsc911x_ops *ops;\n\tstruct regulator_bulk_data supplies[2];\n\tstruct gpio_desc *reset_gpiod;\n\tstruct clk *clk;\n};\n\nstruct smsc911x_ops {\n\tu32 (*reg_read)(struct smsc911x_data *, u32);\n\tvoid (*reg_write)(struct smsc911x_data *, u32, u32);\n\tvoid (*rx_readfifo)(struct smsc911x_data *, unsigned int *, unsigned int);\n\tvoid (*tx_writefifo)(struct smsc911x_data *, unsigned int *, unsigned int);\n};\n\nstruct smsc_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct smsc_phy_priv {\n\tunsigned int edpd_enable: 1;\n\tunsigned int edpd_mode_set_by_user: 1;\n\tunsigned int edpd_max_wait_ms;\n\tbool wol_arp;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sock_xprt {\n\tstruct rpc_xprt xprt;\n\tstruct socket *sock;\n\tstruct sock *inet;\n\tstruct file *file;\n\tstruct {\n\t\tstruct {\n\t\t\t__be32 fraghdr;\n\t\t\t__be32 xid;\n\t\t\t__be32 calldir;\n\t\t};\n\t\tu32 offset;\n\t\tu32 len;\n\t\tlong unsigned int copied;\n\t} recv;\n\tstruct {\n\t\tu32 offset;\n\t} xmit;\n\tlong unsigned int sock_state;\n\tstruct delayed_work connect_worker;\n\tstruct work_struct error_worker;\n\tstruct work_struct recv_worker;\n\tstruct mutex recv_mutex;\n\tstruct completion handshake_done;\n\tstruct __kernel_sockaddr_storage srcaddr;\n\tshort unsigned int srcport;\n\tint xprt_err;\n\tstruct rpc_clnt *clnt;\n\tsize_t rcvsize;\n\tsize_t sndsize;\n\tstruct rpc_timeout tcp_timeout;\n\tvoid (*old_data_ready)(struct sock *);\n\tvoid (*old_state_change)(struct sock *);\n\tvoid (*old_write_space)(struct sock *);\n\tvoid (*old_error_report)(struct sock *);\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\tlong: 32;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunsigned int input_queue_head;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tcall_single_data_t defer_csd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tlong: 32;\n\tu64 args[16];\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\tlong: 32;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct spansion_nor_params {\n\tu8 clsr;\n};\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n\tlong: 32;\n};\n\ntypedef u32 (*spi_bb_txrx_word_fn)(struct spi_device *, unsigned int, u32, u8, unsigned int);\n\nstruct spi_bitbang {\n\tstruct mutex lock;\n\tu8 busy;\n\tu8 use_dma;\n\tu16 flags;\n\tstruct spi_controller *ctlr;\n\tint (*setup_transfer)(struct spi_device *, struct spi_transfer *);\n\tvoid (*chipselect)(struct spi_device *, int);\n\tvoid (*set_mosi_idle)(struct spi_device *);\n\tint (*txrx_bufs)(struct spi_device *, struct spi_transfer *);\n\tspi_bb_txrx_word_fn txrx_word[4];\n\tint (*set_line_direction)(struct spi_device *, bool);\n};\n\ntypedef unsigned int (*spi_bb_txrx_bufs_fn)(struct spi_device *, spi_bb_txrx_word_fn, unsigned int, struct spi_transfer *, unsigned int);\n\nstruct spi_bitbang_cs {\n\tunsigned int nsecs;\n\tspi_bb_txrx_word_fn txrx_word;\n\tspi_bb_txrx_bufs_fn txrx_bufs;\n};\n\nstruct spi_controller_mem_caps;\n\nstruct spi_offload_config;\n\nstruct spi_statistics;\n\nstruct spi_controller {\n\tstruct device dev;\n\tstruct list_head list;\n\ts16 bus_num;\n\tu16 num_chipselect;\n\tu16 num_data_lanes;\n\tu16 dma_alignment;\n\tu32 mode_bits;\n\tu32 buswidth_override_bits;\n\tu32 bits_per_word_mask;\n\tu32 min_speed_hz;\n\tu32 max_speed_hz;\n\tu16 flags;\n\tbool devm_allocated;\n\tunion {\n\t\tbool slave;\n\t\tbool target;\n\t};\n\tsize_t (*max_transfer_size)(struct spi_device *);\n\tsize_t (*max_message_size)(struct spi_device *);\n\tstruct mutex io_mutex;\n\tstruct mutex add_lock;\n\tspinlock_t bus_lock_spinlock;\n\tstruct mutex bus_lock_mutex;\n\tbool bus_lock_flag;\n\tint (*setup)(struct spi_device *);\n\tint (*set_cs_timing)(struct spi_device *);\n\tint (*transfer)(struct spi_device *, struct spi_message *);\n\tvoid (*cleanup)(struct spi_device *);\n\tbool (*can_dma)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tstruct device *dma_map_dev;\n\tstruct device *cur_rx_dma_dev;\n\tstruct device *cur_tx_dma_dev;\n\tbool queued;\n\tstruct kthread_worker *kworker;\n\tstruct kthread_work pump_messages;\n\tspinlock_t queue_lock;\n\tstruct list_head queue;\n\tstruct spi_message *cur_msg;\n\tstruct completion cur_msg_completion;\n\tbool cur_msg_incomplete;\n\tbool cur_msg_need_completion;\n\tbool busy;\n\tbool running;\n\tbool rt;\n\tbool auto_runtime_pm;\n\tbool fallback;\n\tbool last_cs_mode_high;\n\ts8 last_cs[4];\n\tu32 last_cs_index_mask: 4;\n\tstruct completion xfer_completion;\n\tsize_t max_dma_len;\n\tint (*optimize_message)(struct spi_message *);\n\tint (*unoptimize_message)(struct spi_message *);\n\tint (*prepare_transfer_hardware)(struct spi_controller *);\n\tint (*transfer_one_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_transfer_hardware)(struct spi_controller *);\n\tint (*prepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*target_abort)(struct spi_controller *);\n\tvoid (*set_cs)(struct spi_device *, bool);\n\tint (*transfer_one)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tvoid (*handle_err)(struct spi_controller *, struct spi_message *);\n\tconst struct spi_controller_mem_ops *mem_ops;\n\tconst struct spi_controller_mem_caps *mem_caps;\n\tbool dtr_caps;\n\tstruct spi_offload * (*get_offload)(struct spi_device *, const struct spi_offload_config *);\n\tvoid (*put_offload)(struct spi_offload *);\n\tstruct gpio_desc **cs_gpiods;\n\tbool use_gpio_descriptors;\n\ts8 unused_native_cs;\n\ts8 max_native_cs;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tvoid *dummy_rx;\n\tvoid *dummy_tx;\n\tint (*fw_translate_cs)(struct spi_controller *, unsigned int);\n\tbool ptp_sts_supported;\n\tlong unsigned int irq_flags;\n\tbool queue_empty;\n\tbool must_async;\n\tbool defer_optimize_message;\n\tlong: 32;\n};\n\nstruct spi_controller_mem_caps {\n\tbool dtr;\n\tbool ecc;\n\tbool swap16;\n\tbool per_op_freq;\n};\n\nstruct spi_device {\n\tstruct device dev;\n\tstruct spi_controller *controller;\n\tu32 max_speed_hz;\n\tu8 bits_per_word;\n\tbool rt;\n\tu32 mode;\n\tint irq;\n\tvoid *controller_state;\n\tvoid *controller_data;\n\tchar modalias[32];\n\tconst char *driver_override;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct spi_delay word_delay;\n\tstruct spi_delay cs_setup;\n\tstruct spi_delay cs_hold;\n\tstruct spi_delay cs_inactive;\n\tu8 chip_select[4];\n\tu8 num_chipselect;\n\tu32 cs_index_mask: 4;\n\tstruct gpio_desc *cs_gpiod[4];\n\tu8 tx_lane_map[8];\n\tu8 num_tx_lanes;\n\tu8 rx_lane_map[8];\n\tu8 num_rx_lanes;\n};\n\nstruct spi_device_id {\n\tchar name[32];\n\tkernel_ulong_t driver_data;\n};\n\nstruct spi_driver {\n\tconst struct spi_device_id *id_table;\n\tint (*probe)(struct spi_device *);\n\tvoid (*remove)(struct spi_device *);\n\tvoid (*shutdown)(struct spi_device *);\n\tstruct device_driver driver;\n};\n\nstruct spi_ioc_transfer {\n\t__u64 tx_buf;\n\t__u64 rx_buf;\n\t__u32 len;\n\t__u32 speed_hz;\n\t__u16 delay_usecs;\n\t__u8 bits_per_word;\n\t__u8 cs_change;\n\t__u8 tx_nbits;\n\t__u8 rx_nbits;\n\t__u8 word_delay_usecs;\n\t__u8 pad;\n};\n\nstruct spi_mem {\n\tstruct spi_device *spi;\n\tvoid *drvpriv;\n\tconst char *name;\n};\n\nstruct spi_mem_op {\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tu16 opcode;\n\t} cmd;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tlong: 32;\n\t\tu64 val;\n\t} addr;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t} dummy;\n\tstruct {\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 ecc: 1;\n\t\tu8 swap16: 1;\n\t\tu8 __pad: 5;\n\t\tenum spi_mem_data_dir dir;\n\t\tunsigned int nbytes;\n\t\tunion {\n\t\t\tvoid *in;\n\t\t\tconst void *out;\n\t\t} buf;\n\t} data;\n\tunsigned int max_freq;\n};\n\nstruct spi_mem_dirmap_info {\n\tstruct spi_mem_op op_tmpl;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct spi_mem_dirmap_desc {\n\tstruct spi_mem *mem;\n\tlong: 32;\n\tstruct spi_mem_dirmap_info info;\n\tunsigned int nodirmap;\n\tvoid *priv;\n};\n\nstruct spi_mem_driver {\n\tstruct spi_driver spidrv;\n\tint (*probe)(struct spi_mem *);\n\tint (*remove)(struct spi_mem *);\n\tvoid (*shutdown)(struct spi_mem *);\n};\n\nstruct spi_nor_rww {\n\twait_queue_head_t wait;\n\tbool ongoing_io;\n\tbool ongoing_rd;\n\tbool ongoing_pe;\n\tunsigned int used_banks;\n};\n\nstruct spi_nor_manufacturer;\n\nstruct spi_nor_controller_ops;\n\nstruct spi_nor_flash_parameter;\n\nstruct spi_nor {\n\tstruct mtd_info mtd;\n\tstruct mutex lock;\n\tstruct spi_nor_rww rww;\n\tstruct device *dev;\n\tstruct spi_mem *spimem;\n\tu8 *bouncebuf;\n\tsize_t bouncebuf_size;\n\tu8 *id;\n\tconst struct flash_info *info;\n\tconst struct spi_nor_manufacturer *manufacturer;\n\tu8 addr_nbytes;\n\tu8 erase_opcode;\n\tu8 read_opcode;\n\tu8 read_dummy;\n\tu8 program_opcode;\n\tenum spi_nor_protocol read_proto;\n\tenum spi_nor_protocol write_proto;\n\tenum spi_nor_protocol reg_proto;\n\tbool sst_write_second;\n\tu32 flags;\n\tenum spi_nor_cmd_ext cmd_ext_type;\n\tstruct sfdp *sfdp;\n\tstruct dentry *debugfs_root;\n\tconst struct spi_nor_controller_ops *controller_ops;\n\tstruct spi_nor_flash_parameter *params;\n\tstruct {\n\t\tstruct spi_mem_dirmap_desc *rdesc;\n\t\tstruct spi_mem_dirmap_desc *wdesc;\n\t} dirmap;\n\tvoid *priv;\n\tlong: 32;\n};\n\nstruct spi_nor_controller_ops {\n\tint (*prepare)(struct spi_nor *);\n\tvoid (*unprepare)(struct spi_nor *);\n\tint (*read_reg)(struct spi_nor *, u8, u8 *, size_t);\n\tint (*write_reg)(struct spi_nor *, u8, const u8 *, size_t);\n\tssize_t (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tssize_t (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*erase)(struct spi_nor *, loff_t);\n};\n\nstruct spi_nor_erase_command {\n\tstruct list_head list;\n\tu32 count;\n\tu32 size;\n\tu8 opcode;\n};\n\nstruct spi_nor_erase_region {\n\tu64 offset;\n\tu64 size;\n\tu8 erase_mask;\n\tbool overlaid;\n\tlong: 32;\n};\n\nstruct spi_nor_erase_type {\n\tu32 size;\n\tu32 size_shift;\n\tu32 size_mask;\n\tu8 opcode;\n\tu8 idx;\n};\n\nstruct spi_nor_erase_map {\n\tstruct spi_nor_erase_region *regions;\n\tlong: 32;\n\tstruct spi_nor_erase_region uniform_region;\n\tstruct spi_nor_erase_type erase_type[4];\n\tunsigned int n_regions;\n\tlong: 32;\n};\n\nstruct spi_nor_fixups {\n\tvoid (*default_init)(struct spi_nor *);\n\tint (*post_bfpt)(struct spi_nor *, const struct sfdp_parameter_header *, const struct sfdp_bfpt *);\n\tvoid (*smpt_read_dummy)(const struct spi_nor *, u8 *);\n\tvoid (*smpt_map_id)(const struct spi_nor *, u8 *);\n\tint (*post_sfdp)(struct spi_nor *);\n\tint (*late_init)(struct spi_nor *);\n};\n\nstruct spi_nor_hwcaps {\n\tu32 mask;\n};\n\nstruct spi_nor_read_command {\n\tu8 num_mode_clocks;\n\tu8 num_wait_states;\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_pp_command {\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_otp_ops;\n\nstruct spi_nor_otp {\n\tconst struct spi_nor_otp_organization *org;\n\tconst struct spi_nor_otp_ops *ops;\n};\n\nstruct spi_nor_locking_ops;\n\nstruct spi_nor_flash_parameter {\n\tu64 bank_size;\n\tu64 size;\n\tu32 writesize;\n\tu32 page_size;\n\tu8 addr_nbytes;\n\tu8 addr_mode_nbytes;\n\tu8 rdsr_dummy;\n\tu8 rdsr_addr_nbytes;\n\tu8 n_banks;\n\tu8 n_dice;\n\tu8 die_erase_opcode;\n\tu32 *vreg_offset;\n\tstruct spi_nor_hwcaps hwcaps;\n\tstruct spi_nor_read_command reads[16];\n\tstruct spi_nor_pp_command page_programs[8];\n\tstruct spi_nor_erase_map erase_map;\n\tstruct spi_nor_otp otp;\n\tint (*set_octal_dtr)(struct spi_nor *, bool);\n\tint (*quad_enable)(struct spi_nor *);\n\tint (*set_4byte_addr_mode)(struct spi_nor *, bool);\n\tint (*ready)(struct spi_nor *);\n\tconst struct spi_nor_locking_ops *locking_ops;\n\tvoid *priv;\n};\n\nstruct spi_nor_id {\n\tconst u8 *bytes;\n\tu8 len;\n};\n\nstruct spi_nor_locking_ops {\n\tint (*lock)(struct spi_nor *, loff_t, u64);\n\tint (*unlock)(struct spi_nor *, loff_t, u64);\n\tint (*is_locked)(struct spi_nor *, loff_t, u64);\n};\n\nstruct spi_nor_manufacturer {\n\tconst char *name;\n\tconst struct flash_info *parts;\n\tunsigned int nparts;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct spi_nor_otp_ops {\n\tint (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tint (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*lock)(struct spi_nor *, unsigned int);\n\tint (*erase)(struct spi_nor *, loff_t);\n\tint (*is_locked)(struct spi_nor *, unsigned int);\n};\n\nstruct spi_nor_otp_organization {\n\tsize_t len;\n\tlong: 32;\n\tloff_t base;\n\tloff_t offset;\n\tunsigned int n_regions;\n\tlong: 32;\n};\n\nstruct spi_offload_ops;\n\nstruct spi_offload {\n\tstruct device *provider_dev;\n\tvoid *priv;\n\tconst struct spi_offload_ops *ops;\n\tu32 xfer_flags;\n};\n\nstruct spi_offload_config {\n\tu32 capability_flags;\n};\n\nstruct spi_offload_ops {\n\tint (*trigger_enable)(struct spi_offload *);\n\tvoid (*trigger_disable)(struct spi_offload *);\n\tstruct dma_chan * (*tx_stream_request_dma_chan)(struct spi_offload *);\n\tstruct dma_chan * (*rx_stream_request_dma_chan)(struct spi_offload *);\n};\n\nstruct spi_replaced_transfers;\n\ntypedef void (*spi_replaced_release_t)(struct spi_controller *, struct spi_message *, struct spi_replaced_transfers *);\n\nstruct spi_replaced_transfers {\n\tspi_replaced_release_t release;\n\tvoid *extradata;\n\tstruct list_head replaced_transfers;\n\tstruct list_head *replaced_after;\n\tsize_t inserted;\n\tstruct spi_transfer inserted_transfers[0];\n};\n\ntypedef void (*spi_res_release_t)(struct spi_controller *, struct spi_message *, void *);\n\nstruct spi_res {\n\tstruct list_head entry;\n\tspi_res_release_t release;\n\tlong: 32;\n\tlong long unsigned int data[0];\n};\n\nstruct spi_statistics {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t messages;\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t timedout;\n\tu64_stats_t spi_sync;\n\tu64_stats_t spi_sync_immediate;\n\tu64_stats_t spi_async;\n\tu64_stats_t bytes;\n\tu64_stats_t bytes_rx;\n\tu64_stats_t bytes_tx;\n\tu64_stats_t transfer_bytes_histo[17];\n\tu64_stats_t transfers_split_maxsize;\n};\n\nstruct spidev_data {\n\tdev_t devt;\n\tstruct mutex spi_lock;\n\tstruct spi_device *spi;\n\tstruct list_head device_entry;\n\tunsigned int users;\n\tu8 *tx_buffer;\n\tu8 *rx_buffer;\n\tu32 speed_hz;\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tlong: 32;\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n\tlong: 32;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct squashfs_super_block {\n\t__le32 s_magic;\n\t__le32 inodes;\n\t__le32 mkfs_time;\n\t__le32 block_size;\n\t__le32 fragments;\n\t__le16 compression;\n\t__le16 block_log;\n\t__le16 flags;\n\t__le16 no_ids;\n\t__le16 s_major;\n\t__le16 s_minor;\n\t__le64 root_inode;\n\t__le64 bytes_used;\n\t__le64 id_table_start;\n\t__le64 xattr_id_table_start;\n\t__le64 inode_table_start;\n\t__le64 directory_table_start;\n\t__le64 fragment_table_start;\n\t__le64 lookup_table_start;\n};\n\nstruct sr6_tlv {\n\t__u8 type;\n\t__u8 len;\n\t__u8 data[0];\n};\n\nstruct sram_config {\n\tint (*init)(void);\n\tbool map_only_reserved;\n};\n\nstruct sram_partition;\n\nstruct sram_dev {\n\tconst struct sram_config *config;\n\tstruct device *dev;\n\tvoid *virt_base;\n\tbool no_memory_wc;\n\tstruct gen_pool *pool;\n\tstruct sram_partition *partition;\n\tu32 partitions;\n};\n\nstruct sram_partition {\n\tvoid *base;\n\tstruct gen_pool *pool;\n\tstruct bin_attribute battr;\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct sram_reserve {\n\tstruct list_head list;\n\tu32 start;\n\tu32 size;\n\tstruct resource res;\n\tbool export;\n\tbool pool;\n\tbool protect_exec;\n\tconst char *label;\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct stack_trace {\n\tunsigned int nr_entries;\n\tunsigned int max_entries;\n\tlong unsigned int *entries;\n\tunsigned int skip;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\tunsigned int st_dev;\n\tlong int st_pad1[3];\n\t__kernel_ino_t st_ino;\n\t__kernel_mode_t st_mode;\n\t__u32 st_nlink;\n\t__kernel_uid32_t st_uid;\n\t__kernel_gid32_t st_gid;\n\tunsigned int st_rdev;\n\tlong int st_pad2[2];\n\tlong int st_size;\n\tlong int st_pad3;\n\tlong int st_atime;\n\tlong int st_atime_nsec;\n\tlong int st_mtime;\n\tlong int st_mtime_nsec;\n\tlong int st_ctime;\n\tlong int st_ctime_nsec;\n\tlong int st_blksize;\n\tlong int st_blocks;\n\tlong int st_pad4[14];\n};\n\nstruct stat64 {\n\tlong unsigned int st_dev;\n\tlong unsigned int st_pad0[3];\n\tlong long unsigned int st_ino;\n\t__kernel_mode_t st_mode;\n\t__u32 st_nlink;\n\t__kernel_uid32_t st_uid;\n\t__kernel_gid32_t st_gid;\n\tlong unsigned int st_rdev;\n\tlong unsigned int st_pad1[3];\n\tlong long int st_size;\n\tlong int st_atime;\n\tlong unsigned int st_atime_nsec;\n\tlong int st_mtime;\n\tlong unsigned int st_mtime_nsec;\n\tlong int st_ctime;\n\tlong unsigned int st_ctime_nsec;\n\tlong unsigned int st_blksize;\n\tlong unsigned int st_pad2;\n\tlong long int st_blocks;\n};\n\nstruct statfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tlong int f_frsize;\n\tlong int f_blocks;\n\tlong int f_bfree;\n\tlong int f_files;\n\tlong int f_ffree;\n\tlong int f_bavail;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_flags;\n\tlong int f_spare[5];\n};\n\nstruct statfs64 {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u32 f_frsize;\n\t__u32 __pad;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__u64 f_bavail;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_flags;\n\t__u32 f_spare[5];\n\tlong: 32;\n};\n\nstruct static_call_key {\n\tvoid *func;\n};\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n\tlong: 32;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct stmmac_axi {\n\tbool axi_lpi_en;\n\tbool axi_xit_frm;\n\tu32 axi_wr_osr_lmt;\n\tu32 axi_rd_osr_lmt;\n\tbool axi_kbbe;\n\tu32 axi_blen_regval;\n\tbool axi_fb;\n\tbool axi_mb;\n\tbool axi_rb;\n};\n\nstruct stmmac_channel {\n\tstruct napi_struct rx_napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct napi_struct tx_napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct napi_struct rxtx_napi;\n\tstruct stmmac_priv *priv_data;\n\tspinlock_t lock;\n\tu32 index;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_counters {\n\tunsigned int mmc_tx_octetcount_gb;\n\tunsigned int mmc_tx_framecount_gb;\n\tunsigned int mmc_tx_broadcastframe_g;\n\tunsigned int mmc_tx_multicastframe_g;\n\tunsigned int mmc_tx_64_octets_gb;\n\tunsigned int mmc_tx_65_to_127_octets_gb;\n\tunsigned int mmc_tx_128_to_255_octets_gb;\n\tunsigned int mmc_tx_256_to_511_octets_gb;\n\tunsigned int mmc_tx_512_to_1023_octets_gb;\n\tunsigned int mmc_tx_1024_to_max_octets_gb;\n\tunsigned int mmc_tx_unicast_gb;\n\tunsigned int mmc_tx_multicast_gb;\n\tunsigned int mmc_tx_broadcast_gb;\n\tunsigned int mmc_tx_underflow_error;\n\tunsigned int mmc_tx_singlecol_g;\n\tunsigned int mmc_tx_multicol_g;\n\tunsigned int mmc_tx_deferred;\n\tunsigned int mmc_tx_latecol;\n\tunsigned int mmc_tx_exesscol;\n\tunsigned int mmc_tx_carrier_error;\n\tunsigned int mmc_tx_octetcount_g;\n\tunsigned int mmc_tx_framecount_g;\n\tunsigned int mmc_tx_excessdef;\n\tunsigned int mmc_tx_pause_frame;\n\tunsigned int mmc_tx_vlan_frame_g;\n\tunsigned int mmc_tx_oversize_g;\n\tunsigned int mmc_tx_lpi_usec;\n\tunsigned int mmc_tx_lpi_tran;\n\tunsigned int mmc_rx_framecount_gb;\n\tunsigned int mmc_rx_octetcount_gb;\n\tunsigned int mmc_rx_octetcount_g;\n\tunsigned int mmc_rx_broadcastframe_g;\n\tunsigned int mmc_rx_multicastframe_g;\n\tunsigned int mmc_rx_crc_error;\n\tunsigned int mmc_rx_align_error;\n\tunsigned int mmc_rx_run_error;\n\tunsigned int mmc_rx_jabber_error;\n\tunsigned int mmc_rx_undersize_g;\n\tunsigned int mmc_rx_oversize_g;\n\tunsigned int mmc_rx_64_octets_gb;\n\tunsigned int mmc_rx_65_to_127_octets_gb;\n\tunsigned int mmc_rx_128_to_255_octets_gb;\n\tunsigned int mmc_rx_256_to_511_octets_gb;\n\tunsigned int mmc_rx_512_to_1023_octets_gb;\n\tunsigned int mmc_rx_1024_to_max_octets_gb;\n\tunsigned int mmc_rx_unicast_g;\n\tunsigned int mmc_rx_length_error;\n\tunsigned int mmc_rx_autofrangetype;\n\tunsigned int mmc_rx_pause_frames;\n\tunsigned int mmc_rx_fifo_overflow;\n\tunsigned int mmc_rx_vlan_frames_gb;\n\tunsigned int mmc_rx_watchdog_error;\n\tunsigned int mmc_rx_error;\n\tunsigned int mmc_rx_lpi_usec;\n\tunsigned int mmc_rx_lpi_tran;\n\tunsigned int mmc_rx_discard_frames_gb;\n\tunsigned int mmc_rx_discard_octets_gb;\n\tunsigned int mmc_rx_align_err_frames;\n\tunsigned int mmc_rx_ipv4_gd;\n\tunsigned int mmc_rx_ipv4_hderr;\n\tunsigned int mmc_rx_ipv4_nopay;\n\tunsigned int mmc_rx_ipv4_frag;\n\tunsigned int mmc_rx_ipv4_udsbl;\n\tunsigned int mmc_rx_ipv4_gd_octets;\n\tunsigned int mmc_rx_ipv4_hderr_octets;\n\tunsigned int mmc_rx_ipv4_nopay_octets;\n\tunsigned int mmc_rx_ipv4_frag_octets;\n\tunsigned int mmc_rx_ipv4_udsbl_octets;\n\tunsigned int mmc_rx_ipv6_gd_octets;\n\tunsigned int mmc_rx_ipv6_hderr_octets;\n\tunsigned int mmc_rx_ipv6_nopay_octets;\n\tunsigned int mmc_rx_ipv6_gd;\n\tunsigned int mmc_rx_ipv6_hderr;\n\tunsigned int mmc_rx_ipv6_nopay;\n\tunsigned int mmc_rx_udp_gd;\n\tunsigned int mmc_rx_udp_err;\n\tunsigned int mmc_rx_tcp_gd;\n\tunsigned int mmc_rx_tcp_err;\n\tunsigned int mmc_rx_icmp_gd;\n\tunsigned int mmc_rx_icmp_err;\n\tunsigned int mmc_rx_udp_gd_octets;\n\tunsigned int mmc_rx_udp_err_octets;\n\tunsigned int mmc_rx_tcp_gd_octets;\n\tunsigned int mmc_rx_tcp_err_octets;\n\tunsigned int mmc_rx_icmp_gd_octets;\n\tunsigned int mmc_rx_icmp_err_octets;\n\tunsigned int mmc_sgf_pass_fragment_cntr;\n\tunsigned int mmc_sgf_fail_fragment_cntr;\n\tunsigned int mmc_tx_fpe_fragment_cntr;\n\tunsigned int mmc_tx_hold_req_cntr;\n\tunsigned int mmc_tx_gate_overrun_cntr;\n\tunsigned int mmc_rx_packet_assembly_err_cntr;\n\tunsigned int mmc_rx_packet_smd_err_cntr;\n\tunsigned int mmc_rx_packet_assembly_ok_cntr;\n\tunsigned int mmc_rx_fpe_fragment_cntr;\n};\n\nstruct stmmac_extra_stats;\n\nstruct stmmac_desc_ops {\n\tvoid (*init_rx_desc)(struct dma_desc *, int, int, int, int);\n\tvoid (*init_tx_desc)(struct dma_desc *, int, int);\n\tvoid (*prepare_tx_desc)(struct dma_desc *, int, int, bool, int, bool, bool, unsigned int);\n\tvoid (*prepare_tso_tx_desc)(struct dma_desc *, int, int, int, bool, bool, unsigned int, unsigned int);\n\tvoid (*set_tx_owner)(struct dma_desc *);\n\tint (*get_tx_owner)(struct dma_desc *);\n\tvoid (*release_tx_desc)(struct dma_desc *, int);\n\tvoid (*set_tx_ic)(struct dma_desc *);\n\tint (*get_tx_ls)(struct dma_desc *);\n\tu16 (*get_rx_vlan_tci)(struct dma_desc *);\n\tbool (*get_rx_vlan_valid)(struct dma_desc *);\n\tint (*tx_status)(struct stmmac_extra_stats *, struct dma_desc *, void *);\n\tint (*get_tx_len)(struct dma_desc *);\n\tvoid (*set_rx_owner)(struct dma_desc *, int);\n\tint (*get_rx_frame_len)(struct dma_desc *, int);\n\tint (*rx_status)(struct stmmac_extra_stats *, struct dma_desc *);\n\tvoid (*rx_extended_status)(struct stmmac_extra_stats *, struct dma_extended_desc *);\n\tvoid (*enable_tx_timestamp)(struct dma_desc *);\n\tint (*get_tx_timestamp_status)(struct dma_desc *);\n\tvoid (*get_timestamp)(void *, u32, u64 *);\n\tint (*get_rx_timestamp_status)(void *, void *, u32);\n\tvoid (*display_ring)(void *, unsigned int, bool, dma_addr_t, unsigned int);\n\tvoid (*set_mss)(struct dma_desc *, unsigned int);\n\tvoid (*set_addr)(struct dma_desc *, dma_addr_t);\n\tvoid (*clear)(struct dma_desc *);\n\tint (*get_rx_hash)(struct dma_desc *, u32 *, enum pkt_hash_types *);\n\tvoid (*get_rx_header_len)(struct dma_desc *, unsigned int *);\n\tvoid (*set_sec_addr)(struct dma_desc *, dma_addr_t, bool);\n\tvoid (*set_sarc)(struct dma_desc *, u32);\n\tvoid (*set_vlan_tag)(struct dma_desc *, u16, u16, u32);\n\tvoid (*set_vlan)(struct dma_desc *, u32);\n\tvoid (*set_tbs)(struct dma_edesc *, u32, u32);\n};\n\nstruct stmmac_devlink_priv {\n\tstruct stmmac_priv *stmmac_priv;\n};\n\nstruct stmmac_dma_cfg {\n\tint pbl;\n\tint txpbl;\n\tint rxpbl;\n\tbool pblx8;\n\tint fixed_burst;\n\tint mixed_burst;\n\tbool aal;\n\tbool eame;\n\tbool multi_msi_en;\n\tbool dche;\n\tbool atds;\n};\n\nstruct stmmac_rx_buffer;\n\nstruct stmmac_rx_queue {\n\tu32 rx_count_frames;\n\tu32 queue_index;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct xsk_buff_pool *xsk_pool;\n\tstruct page_pool *page_pool;\n\tstruct stmmac_rx_buffer *buf_pool;\n\tstruct stmmac_priv *priv_data;\n\tstruct dma_extended_desc *dma_erx;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct dma_desc *dma_rx;\n\tunsigned int cur_rx;\n\tunsigned int dirty_rx;\n\tunsigned int buf_alloc_num;\n\tunsigned int napi_skb_frag_size;\n\tdma_addr_t dma_rx_phy;\n\tu32 rx_tail_addr;\n\tunsigned int state_saved;\n\tstruct {\n\t\tstruct sk_buff *skb;\n\t\tunsigned int len;\n\t\tunsigned int error;\n\t} state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_tx_info;\n\nstruct stmmac_tx_queue {\n\tu32 tx_count_frames;\n\tint tbs;\n\tstruct hrtimer txtimer;\n\tu32 queue_index;\n\tstruct stmmac_priv *priv_data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct dma_extended_desc *dma_etx;\n\tstruct dma_edesc *dma_entx;\n\tstruct dma_desc *dma_tx;\n\tunion {\n\t\tstruct sk_buff **tx_skbuff;\n\t\tstruct xdp_frame **xdpf;\n\t};\n\tstruct stmmac_tx_info *tx_skbuff_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tu32 xsk_frames_done;\n\tunsigned int cur_tx;\n\tunsigned int dirty_tx;\n\tdma_addr_t dma_tx_phy;\n\tdma_addr_t tx_tail_addr;\n\tu32 mss;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_dma_conf {\n\tunsigned int dma_buf_sz;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_rx_queue rx_queue[8];\n\tunsigned int dma_rx_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_tx_queue tx_queue[8];\n\tunsigned int dma_tx_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_dma_ops {\n\tint (*reset)(void *);\n\tvoid (*init)(void *, struct stmmac_dma_cfg *);\n\tvoid (*init_chan)(struct stmmac_priv *, void *, struct stmmac_dma_cfg *, u32);\n\tvoid (*init_rx_chan)(struct stmmac_priv *, void *, struct stmmac_dma_cfg *, dma_addr_t, u32);\n\tvoid (*init_tx_chan)(struct stmmac_priv *, void *, struct stmmac_dma_cfg *, dma_addr_t, u32);\n\tvoid (*axi)(void *, struct stmmac_axi *);\n\tvoid (*dump_regs)(struct stmmac_priv *, void *, u32 *);\n\tvoid (*dma_rx_mode)(struct stmmac_priv *, void *, int, u32, int, u8);\n\tvoid (*dma_tx_mode)(struct stmmac_priv *, void *, int, u32, int, u8);\n\tvoid (*dma_diagnostic_fr)(struct stmmac_extra_stats *, void *);\n\tvoid (*enable_dma_transmission)(void *, u32);\n\tvoid (*enable_dma_reception)(void *, u32);\n\tvoid (*enable_dma_irq)(struct stmmac_priv *, void *, u32, bool, bool);\n\tvoid (*disable_dma_irq)(struct stmmac_priv *, void *, u32, bool, bool);\n\tvoid (*start_tx)(struct stmmac_priv *, void *, u32);\n\tvoid (*stop_tx)(struct stmmac_priv *, void *, u32);\n\tvoid (*start_rx)(struct stmmac_priv *, void *, u32);\n\tvoid (*stop_rx)(struct stmmac_priv *, void *, u32);\n\tint (*dma_interrupt)(struct stmmac_priv *, void *, struct stmmac_extra_stats *, u32, u32);\n\tint (*get_hw_feature)(void *, struct dma_features *);\n\tvoid (*rx_watchdog)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_tx_ring_len)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_rx_ring_len)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_rx_tail_ptr)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_tx_tail_ptr)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*enable_tso)(struct stmmac_priv *, void *, bool, u32);\n\tvoid (*qmode)(struct stmmac_priv *, void *, u32, u8);\n\tvoid (*set_bfsize)(struct stmmac_priv *, void *, int, u32);\n\tvoid (*enable_sph)(struct stmmac_priv *, void *, bool, u32);\n\tint (*enable_tbs)(struct stmmac_priv *, void *, bool, u32);\n};\n\nstruct stmmac_est {\n\tint enable;\n\tu32 btr_reserve[2];\n\tu32 btr_offset[2];\n\tu32 btr[2];\n\tu32 ctr[2];\n\tu32 ter;\n\tu32 gcl_unaligned[1024];\n\tu32 gcl[1024];\n\tu32 gcl_size;\n\tu32 max_sdu[8];\n};\n\nstruct stmmac_est_ops {\n\tint (*configure)(struct stmmac_priv *, struct stmmac_est *, unsigned int);\n\tvoid (*irq_status)(struct stmmac_priv *, struct net_device *, struct stmmac_extra_stats *, u32);\n};\n\nstruct stmmac_q_tx_stats {\n\tu64_stats_t tx_bytes;\n\tu64_stats_t tx_set_ic_bit;\n\tu64_stats_t tx_tso_frames;\n\tu64_stats_t tx_tso_nfrags;\n};\n\nstruct stmmac_napi_tx_stats {\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_pkt_n;\n\tu64_stats_t poll;\n\tu64_stats_t tx_clean;\n\tu64_stats_t tx_set_ic_bit;\n};\n\nstruct stmmac_txq_stats {\n\tstruct u64_stats_sync q_syncp;\n\tlong: 32;\n\tstruct stmmac_q_tx_stats q;\n\tstruct u64_stats_sync napi_syncp;\n\tlong: 32;\n\tstruct stmmac_napi_tx_stats napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_napi_rx_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_pkt_n;\n\tu64_stats_t poll;\n};\n\nstruct stmmac_rxq_stats {\n\tstruct u64_stats_sync napi_syncp;\n\tlong: 32;\n\tstruct stmmac_napi_rx_stats napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_pcpu_stats;\n\nstruct stmmac_extra_stats {\n\tlong unsigned int tx_underflow;\n\tlong unsigned int tx_carrier;\n\tlong unsigned int tx_losscarrier;\n\tlong unsigned int vlan_tag;\n\tlong unsigned int tx_deferred;\n\tlong unsigned int tx_vlan;\n\tlong unsigned int tx_jabber;\n\tlong unsigned int tx_frame_flushed;\n\tlong unsigned int tx_payload_error;\n\tlong unsigned int tx_ip_header_error;\n\tlong unsigned int tx_collision;\n\tlong unsigned int rx_desc;\n\tlong unsigned int sa_filter_fail;\n\tlong unsigned int overflow_error;\n\tlong unsigned int ipc_csum_error;\n\tlong unsigned int rx_collision;\n\tlong unsigned int rx_crc_errors;\n\tlong unsigned int dribbling_bit;\n\tlong unsigned int rx_length;\n\tlong unsigned int rx_mii;\n\tlong unsigned int rx_multicast;\n\tlong unsigned int rx_gmac_overflow;\n\tlong unsigned int rx_watchdog;\n\tlong unsigned int da_rx_filter_fail;\n\tlong unsigned int sa_rx_filter_fail;\n\tlong unsigned int rx_missed_cntr;\n\tlong unsigned int rx_overflow_cntr;\n\tlong unsigned int rx_vlan;\n\tlong unsigned int rx_split_hdr_pkt_n;\n\tlong unsigned int tx_undeflow_irq;\n\tlong unsigned int tx_process_stopped_irq;\n\tlong unsigned int tx_jabber_irq;\n\tlong unsigned int rx_overflow_irq;\n\tlong unsigned int rx_buf_unav_irq;\n\tlong unsigned int rx_process_stopped_irq;\n\tlong unsigned int rx_watchdog_irq;\n\tlong unsigned int tx_early_irq;\n\tlong unsigned int fatal_bus_error_irq;\n\tlong unsigned int rx_early_irq;\n\tlong unsigned int threshold;\n\tlong unsigned int irq_receive_pmt_irq_n;\n\tlong unsigned int mmc_tx_irq_n;\n\tlong unsigned int mmc_rx_irq_n;\n\tlong unsigned int mmc_rx_csum_offload_irq_n;\n\tlong unsigned int irq_tx_path_in_lpi_mode_n;\n\tlong unsigned int irq_tx_path_exit_lpi_mode_n;\n\tlong unsigned int irq_rx_path_in_lpi_mode_n;\n\tlong unsigned int irq_rx_path_exit_lpi_mode_n;\n\tlong unsigned int phy_eee_wakeup_error_n;\n\tlong unsigned int ip_hdr_err;\n\tlong unsigned int ip_payload_err;\n\tlong unsigned int ip_csum_bypassed;\n\tlong unsigned int ipv4_pkt_rcvd;\n\tlong unsigned int ipv6_pkt_rcvd;\n\tlong unsigned int no_ptp_rx_msg_type_ext;\n\tlong unsigned int ptp_rx_msg_type_sync;\n\tlong unsigned int ptp_rx_msg_type_follow_up;\n\tlong unsigned int ptp_rx_msg_type_delay_req;\n\tlong unsigned int ptp_rx_msg_type_delay_resp;\n\tlong unsigned int ptp_rx_msg_type_pdelay_req;\n\tlong unsigned int ptp_rx_msg_type_pdelay_resp;\n\tlong unsigned int ptp_rx_msg_type_pdelay_follow_up;\n\tlong unsigned int ptp_rx_msg_type_announce;\n\tlong unsigned int ptp_rx_msg_type_management;\n\tlong unsigned int ptp_rx_msg_pkt_reserved_type;\n\tlong unsigned int ptp_frame_type;\n\tlong unsigned int ptp_ver;\n\tlong unsigned int timestamp_dropped;\n\tlong unsigned int av_pkt_rcvd;\n\tlong unsigned int av_tagged_pkt_rcvd;\n\tlong unsigned int vlan_tag_priority_val;\n\tlong unsigned int l3_filter_match;\n\tlong unsigned int l4_filter_match;\n\tlong unsigned int l3_l4_filter_no_match;\n\tlong unsigned int irq_pcs_ane_n;\n\tlong unsigned int irq_pcs_link_n;\n\tlong unsigned int irq_rgmii_n;\n\tlong unsigned int mtl_tx_status_fifo_full;\n\tlong unsigned int mtl_tx_fifo_not_empty;\n\tlong unsigned int mmtl_fifo_ctrl;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_write;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_wait;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_read;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_idle;\n\tlong unsigned int mac_tx_in_pause;\n\tlong unsigned int mac_tx_frame_ctrl_xfer;\n\tlong unsigned int mac_tx_frame_ctrl_idle;\n\tlong unsigned int mac_tx_frame_ctrl_wait;\n\tlong unsigned int mac_tx_frame_ctrl_pause;\n\tlong unsigned int mac_gmii_tx_proto_engine;\n\tlong unsigned int mtl_rx_fifo_fill_level_full;\n\tlong unsigned int mtl_rx_fifo_fill_above_thresh;\n\tlong unsigned int mtl_rx_fifo_fill_below_thresh;\n\tlong unsigned int mtl_rx_fifo_fill_level_empty;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_flush;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_read_data;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_status;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_idle;\n\tlong unsigned int mtl_rx_fifo_ctrl_active;\n\tlong unsigned int mac_rx_frame_ctrl_fifo;\n\tlong unsigned int mac_gmii_rx_proto_engine;\n\tlong unsigned int mtl_est_cgce;\n\tlong unsigned int mtl_est_hlbs;\n\tlong unsigned int mtl_est_hlbf;\n\tlong unsigned int mtl_est_btre;\n\tlong unsigned int mtl_est_btrlm;\n\tlong unsigned int max_sdu_txq_drop[8];\n\tlong unsigned int mtl_est_txq_hlbf[8];\n\tlong unsigned int mtl_est_txq_hlbs[8];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_txq_stats txq_stats[8];\n\tstruct stmmac_rxq_stats rxq_stats[8];\n\tstruct stmmac_pcpu_stats *pcpu_stats;\n\tlong unsigned int rx_dropped;\n\tlong unsigned int rx_errors;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int tx_errors;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_flow_entry {\n\tlong unsigned int cookie;\n\tlong unsigned int action;\n\tu8 ip_proto;\n\tint in_use;\n\tint idx;\n\tint is_l4;\n};\n\nstruct stmmac_fpe_reg;\n\nstruct stmmac_fpe_cfg {\n\tstruct ethtool_mmsv mmsv;\n\tconst struct stmmac_fpe_reg *reg;\n\tu32 fpe_csr;\n};\n\nstruct stmmac_fpe_reg {\n\tconst u32 mac_fpe_reg;\n\tconst u32 mtl_fpe_reg;\n\tconst u32 rxq_ctrl1_reg;\n\tconst u32 fprq_mask;\n\tconst u32 int_en_reg;\n\tconst u32 int_en_bit;\n};\n\nstruct stmmac_regs_off {\n\tconst struct stmmac_fpe_reg *fpe_reg;\n\tu32 ptp_off;\n\tu32 mmc_off;\n\tu32 est_off;\n};\n\nstruct stmmac_hwif_entry {\n\tenum dwmac_core_type core_type;\n\tu32 min_id;\n\tu32 dev_id;\n\tconst struct stmmac_regs_off regs;\n\tconst void *desc;\n\tconst void *dma;\n\tconst void *mac;\n\tconst void *hwtimestamp;\n\tconst void *ptp;\n\tconst void *mode;\n\tconst void *tc;\n\tconst void *mmc;\n\tconst void *est;\n\tconst void *vlan;\n\tint (*setup)(struct stmmac_priv *);\n\tint (*quirks)(struct stmmac_priv *);\n};\n\nstruct stmmac_hwtimestamp {\n\tvoid (*config_hw_tstamping)(void *, u32);\n\tvoid (*config_sub_second_increment)(void *, u32, int, u32 *);\n\tint (*init_systime)(void *, u32, u32);\n\tint (*config_addend)(void *, u32);\n\tint (*adjust_systime)(void *, u32, u32, int, int);\n\tvoid (*get_systime)(void *, u64 *);\n\tvoid (*get_ptptime)(void *, u64 *);\n\tvoid (*timestamp_interrupt)(struct stmmac_priv *);\n\tvoid (*hwtstamp_correct_latency)(struct stmmac_priv *);\n};\n\nstruct stmmac_mdio_bus_data {\n\tunsigned int phy_mask;\n\tunsigned int pcs_mask;\n\tunsigned int default_an_inband;\n\tint *irqs;\n\tint probed_phy_irq;\n\tbool needs_reset;\n};\n\nstruct stmmac_metadata_request {\n\tstruct stmmac_priv *priv;\n\tstruct dma_desc *tx_desc;\n\tbool *set_ic;\n\tstruct dma_edesc *edesc;\n\tint tbs;\n};\n\nstruct stmmac_mmc_ops {\n\tvoid (*ctrl)(void *, unsigned int);\n\tvoid (*intr_all_mask)(void *);\n\tvoid (*read)(void *, struct stmmac_counters *);\n};\n\nstruct stmmac_mode_ops {\n\tvoid (*init)(void *, dma_addr_t, unsigned int, unsigned int);\n\tbool (*is_jumbo_frm)(unsigned int, bool);\n\tint (*jumbo_frm)(struct stmmac_tx_queue *, struct sk_buff *, int);\n\tint (*set_16kib_bfsize)(int);\n\tvoid (*init_desc3)(struct dma_desc *);\n\tvoid (*refill_desc3)(struct stmmac_rx_queue *, struct dma_desc *);\n\tvoid (*clean_desc3)(struct stmmac_tx_queue *, struct dma_desc *);\n};\n\nstruct stmmac_safety_stats;\n\nstruct stmmac_tc_entry;\n\nstruct stmmac_pps_cfg;\n\nstruct stmmac_rss;\n\nstruct stmmac_ops {\n\tint (*pcs_init)(struct stmmac_priv *);\n\tvoid (*core_init)(struct mac_device_info *, struct net_device *);\n\tvoid (*update_caps)(struct stmmac_priv *);\n\tvoid (*irq_modify)(struct mac_device_info *, u32, u32);\n\tvoid (*set_mac)(void *, bool);\n\tint (*rx_ipc)(struct mac_device_info *);\n\tvoid (*rx_queue_enable)(struct mac_device_info *, u8, u32);\n\tvoid (*rx_queue_prio)(struct mac_device_info *, u32, u32);\n\tvoid (*tx_queue_prio)(struct mac_device_info *, u32, u32);\n\tvoid (*rx_queue_routing)(struct mac_device_info *, u8, u32);\n\tvoid (*prog_mtl_rx_algorithms)(struct mac_device_info *, u32);\n\tvoid (*prog_mtl_tx_algorithms)(struct mac_device_info *, u32);\n\tvoid (*set_mtl_tx_queue_weight)(struct stmmac_priv *, struct mac_device_info *, u32, u32);\n\tvoid (*map_mtl_to_dma)(struct mac_device_info *, u32, u32);\n\tvoid (*config_cbs)(struct stmmac_priv *, struct mac_device_info *, u32, u32, u32, u32, u32);\n\tvoid (*dump_regs)(struct mac_device_info *, u32 *);\n\tint (*host_irq_status)(struct stmmac_priv *, struct stmmac_extra_stats *);\n\tint (*host_mtl_irq_status)(struct stmmac_priv *, struct mac_device_info *, u32);\n\tvoid (*set_filter)(struct mac_device_info *, struct net_device *);\n\tvoid (*flow_ctrl)(struct mac_device_info *, unsigned int, unsigned int, unsigned int, u32);\n\tvoid (*pmt)(struct mac_device_info *, long unsigned int);\n\tvoid (*set_umac_addr)(struct mac_device_info *, const unsigned char *, unsigned int);\n\tvoid (*get_umac_addr)(struct mac_device_info *, unsigned char *, unsigned int);\n\tint (*set_lpi_mode)(struct mac_device_info *, enum stmmac_lpi_mode, bool, u32);\n\tvoid (*set_eee_timer)(struct mac_device_info *, int, int);\n\tvoid (*set_eee_pls)(struct mac_device_info *, int);\n\tvoid (*debug)(struct stmmac_priv *, void *, struct stmmac_extra_stats *, u32, u32);\n\tvoid (*pcs_ctrl_ane)(struct stmmac_priv *, bool, bool);\n\tint (*safety_feat_config)(void *, unsigned int, struct stmmac_safety_feature_cfg *);\n\tint (*safety_feat_irq_status)(struct net_device *, void *, unsigned int, struct stmmac_safety_stats *);\n\tint (*safety_feat_dump)(struct stmmac_safety_stats *, int, long unsigned int *, const char **);\n\tint (*rxp_config)(void *, struct stmmac_tc_entry *, unsigned int);\n\tint (*flex_pps_config)(void *, int, struct stmmac_pps_cfg *, bool, u32, u32);\n\tvoid (*set_mac_loopback)(void *, bool);\n\tint (*rss_configure)(struct mac_device_info *, struct stmmac_rss *, u32);\n\tint (*get_mac_tx_timestamp)(struct mac_device_info *, u64 *);\n\tvoid (*sarc_configure)(void *, int);\n\tint (*config_l3_filter)(struct mac_device_info *, u32, bool, bool, bool, bool, u32);\n\tint (*config_l4_filter)(struct mac_device_info *, u32, bool, bool, bool, bool, u32);\n\tvoid (*set_arp_offload)(struct mac_device_info *, bool, u32);\n\tint (*fpe_map_preemption_class)(struct net_device *, struct netlink_ext_ack *, u32);\n};\n\nstruct stmmac_pcpu_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t rx_normal_irq_n[8];\n\tu64_stats_t tx_normal_irq_n[8];\n};\n\nstruct stmmac_pcs {\n\tstruct stmmac_priv *priv;\n\tvoid *base;\n\tu32 int_mask;\n\tstruct phylink_pcs pcs;\n};\n\nstruct stmmac_pps_cfg {\n\tbool available;\n\tlong: 32;\n\tstruct timespec64 start;\n\tstruct timespec64 period;\n};\n\nstruct stmmac_safety_stats {\n\tlong unsigned int mac_errors[32];\n\tlong unsigned int mtl_errors[32];\n\tlong unsigned int dma_errors[32];\n\tlong unsigned int dma_dpp_errors[32];\n};\n\nstruct stmmac_rss {\n\tint enable;\n\tu8 key[40];\n\tu32 table[256];\n};\n\nstruct stmmac_rfs_entry;\n\nstruct stmmac_priv {\n\tu32 tx_coal_frames[8];\n\tu32 tx_coal_timer[8];\n\tu32 rx_coal_frames[8];\n\tint hwts_tx_en;\n\tbool tx_path_in_lpi_mode;\n\tbool tso;\n\tbool sph_active;\n\tbool sph_capable;\n\tu32 sarc_type;\n\tu32 rx_riwt[8];\n\tint hwts_rx_en;\n\tbool tsfupdt_coarse;\n\tvoid *ioaddr;\n\tstruct net_device *dev;\n\tstruct device *device;\n\tstruct mac_device_info *hw;\n\tint (*hwif_quirks)(struct stmmac_priv *);\n\tstruct mutex lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_dma_conf dma_conf;\n\tstruct stmmac_channel channel[8];\n\tunsigned int pause_time;\n\tstruct mii_bus *mii;\n\tstruct stmmac_pcs *integrated_pcs;\n\tstruct phylink_config phylink_config;\n\tstruct phylink *phylink;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_extra_stats xstats;\n\tstruct stmmac_safety_stats sstats;\n\tstruct plat_stmmacenet_data *plat;\n\tstruct mutex est_lock;\n\tstruct stmmac_est *est;\n\tstruct dma_features dma_cap;\n\tstruct stmmac_counters mmc;\n\tint hw_cap_support;\n\tint synopsys_id;\n\tu32 msg_enable;\n\tint wolopts;\n\tint wol_irq;\n\tu32 gmii_address_bus_config;\n\tstruct timer_list eee_ctrl_timer;\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_clk_stop;\n\tbool eee_enabled;\n\tbool eee_active;\n\tbool eee_sw_timer_en;\n\tbool legacy_serdes_is_powered;\n\tunsigned int mode;\n\tunsigned int chain_mode;\n\tint extend_desc;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_ops;\n\tunsigned int default_addend;\n\tu32 sub_second_inc;\n\tu32 systime_flags;\n\tu32 adv_ts;\n\tint use_riwt;\n\tint irq_wake;\n\trwlock_t ptp_lock;\n\tstruct mutex aux_ts_lock;\n\twait_queue_head_t tstamp_busy_wait;\n\tvoid *mmcaddr;\n\tvoid *ptpaddr;\n\tvoid *estaddr;\n\tlong unsigned int active_vlans[128];\n\tunsigned int num_double_vlans;\n\tint sfty_irq;\n\tint sfty_ce_irq;\n\tint sfty_ue_irq;\n\tint rx_irq[8];\n\tint tx_irq[8];\n\tchar int_name_mac[25];\n\tchar int_name_wol[25];\n\tchar int_name_lpi[25];\n\tchar int_name_sfty[26];\n\tchar int_name_sfty_ce[26];\n\tchar int_name_sfty_ue[26];\n\tchar int_name_rx_irq[240];\n\tchar int_name_tx_irq[272];\n\tstruct dentry *dbgfs_dir;\n\tlong unsigned int state;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct service_task;\n\tstruct stmmac_fpe_cfg fpe_cfg;\n\tunsigned int tc_entries_max;\n\tunsigned int tc_off_max;\n\tstruct stmmac_tc_entry *tc_entries;\n\tunsigned int flow_entries_max;\n\tstruct stmmac_flow_entry *flow_entries;\n\tunsigned int rfs_entries_max[3];\n\tunsigned int rfs_entries_cnt[3];\n\tunsigned int rfs_entries_total;\n\tstruct stmmac_rfs_entry *rfs_entries;\n\tlong: 32;\n\tstruct stmmac_pps_cfg pps[4];\n\tstruct stmmac_rss rss;\n\tlong unsigned int *af_xdp_zc_qps;\n\tstruct bpf_prog *xdp_prog;\n\tstruct devlink *devlink;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_resources {\n\tvoid *addr;\n\tu8 mac[6];\n\tint wol_irq;\n\tint irq;\n\tint sfty_irq;\n\tint sfty_ce_irq;\n\tint sfty_ue_irq;\n\tint rx_irq[8];\n\tint tx_irq[8];\n};\n\nstruct stmmac_rfs_entry {\n\tlong unsigned int cookie;\n\tu16 etype;\n\tint in_use;\n\tint type;\n\tint tc;\n};\n\nstruct stmmac_rx_buffer {\n\tunion {\n\t\tstruct {\n\t\t\tstruct page *page;\n\t\t\tdma_addr_t addr;\n\t\t\t__u32 page_offset;\n\t\t};\n\t\tstruct xdp_buff *xdp;\n\t};\n\tstruct page *sec_page;\n\tdma_addr_t sec_addr;\n};\n\nstruct stmmac_rx_routing {\n\tu32 reg_mask;\n\tu32 reg_shift;\n};\n\nstruct stmmac_safety_feature_cfg {\n\tu32 tsoee;\n\tu32 mrxpee;\n\tu32 mestee;\n\tu32 mrxee;\n\tu32 mtxee;\n\tu32 epsi;\n\tu32 edpp;\n\tu32 prtyen;\n\tu32 tmouten;\n};\n\nstruct stmmac_stats {\n\tchar stat_string[32];\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct stmmac_tc_entry {\n\tbool in_use;\n\tbool in_hw;\n\tbool is_last;\n\tbool is_frag;\n\tvoid *frag_ptr;\n\tunsigned int table_pos;\n\tu32 handle;\n\tu32 prio;\n\tstruct {\n\t\tu32 match_data;\n\t\tu32 match_en;\n\t\tu8 af: 1;\n\t\tu8 rf: 1;\n\t\tu8 im: 1;\n\t\tu8 nc: 1;\n\t\tu8 res1: 4;\n\t\tu8 frame_offset;\n\t\tu8 ok_index;\n\t\tu8 dma_ch_no;\n\t\tu32 res2;\n\t} val;\n};\n\nstruct tc_cls_u32_offload;\n\nstruct tc_cbs_qopt_offload;\n\nstruct tc_etf_qopt_offload;\n\nstruct tc_query_caps_base;\n\nstruct tc_mqprio_qopt_offload;\n\nstruct stmmac_tc_ops {\n\tint (*init)(struct stmmac_priv *);\n\tint (*setup_cls_u32)(struct stmmac_priv *, struct tc_cls_u32_offload *);\n\tint (*setup_cbs)(struct stmmac_priv *, struct tc_cbs_qopt_offload *);\n\tint (*setup_cls)(struct stmmac_priv *, struct flow_cls_offload *);\n\tint (*setup_taprio)(struct stmmac_priv *, struct tc_taprio_qopt_offload *);\n\tint (*setup_etf)(struct stmmac_priv *, struct tc_etf_qopt_offload *);\n\tint (*query_caps)(struct stmmac_priv *, struct tc_query_caps_base *);\n\tint (*setup_mqprio)(struct stmmac_priv *, struct tc_mqprio_qopt_offload *);\n};\n\nstruct stmmac_tx_info {\n\tdma_addr_t buf;\n\tbool map_as_page;\n\tunsigned int len;\n\tbool last_segment;\n\tbool is_jumbo;\n\tenum stmmac_txbuf_type buf_type;\n\tstruct xsk_tx_metadata_compl xsk_meta;\n};\n\nstruct stmmac_version {\n\tu8 snpsver;\n\tu8 dev_id;\n};\n\nstruct stmmac_vlan_ops {\n\tvoid (*update_vlan_hash)(struct mac_device_info *, u32, u16, bool);\n\tvoid (*enable_vlan)(struct mac_device_info *, u32);\n\tvoid (*rx_hw_vlan)(struct mac_device_info *, struct dma_desc *, struct sk_buff *);\n\tvoid (*set_hw_vlan_mode)(struct mac_device_info *);\n\tint (*add_hw_vlan_rx_fltr)(struct net_device *, struct mac_device_info *, __be16, u16);\n\tint (*del_hw_vlan_rx_fltr)(struct net_device *, struct mac_device_info *, __be16, u16);\n\tvoid (*restore_hw_vlan_rx_fltr)(struct net_device *, struct mac_device_info *);\n};\n\nstruct stmmac_xdp_buff {\n\tstruct xdp_buff xdp;\n\tstruct stmmac_priv *priv;\n\tstruct dma_desc *desc;\n\tstruct dma_desc *ndesc;\n\tlong: 32;\n};\n\nstruct stmmac_xsk_tx_complete {\n\tstruct stmmac_priv *priv;\n\tstruct dma_desc *desc;\n};\n\nstruct stp_proto {\n\tunsigned char group_address[6];\n\tvoid (*rcv)(const struct stp_proto *, struct sk_buff *, struct net_device *);\n\tvoid *data;\n};\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\nstruct summary_data {\n\tstruct seq_file *s;\n\tstruct regulator_dev *parent;\n\tint level;\n};\n\nstruct summary_lock_data {\n\tstruct ww_acquire_ctx *ww_ctx;\n\tstruct regulator_dev **new_contended_rdev;\n\tstruct regulator_dev **old_contended_rdev;\n};\n\nstruct sunrpc_net {\n\tstruct proc_dir_entry *proc_net_rpc;\n\tstruct cache_detail *ip_map_cache;\n\tstruct cache_detail *unix_gid_cache;\n\tstruct cache_detail *rsc_cache;\n\tstruct cache_detail *rsi_cache;\n\tstruct super_block *pipefs_sb;\n\tstruct rpc_pipe *gssd_dummy;\n\tstruct mutex pipefs_sb_lock;\n\tstruct list_head all_clients;\n\tspinlock_t rpc_client_lock;\n\tstruct rpc_clnt *rpcb_local_clnt;\n\tstruct rpc_clnt *rpcb_local_clnt4;\n\tspinlock_t rpcb_clnt_lock;\n\tunsigned int rpcb_users;\n\tunsigned int rpcb_is_af_local: 1;\n\tstruct mutex gssp_lock;\n\tstruct rpc_clnt *gssp_clnt;\n\tint use_gss_proxy;\n\tint pipe_version;\n\tatomic_t pipe_users;\n\tstruct proc_dir_entry *use_gssp_proc;\n\tstruct proc_dir_entry *gss_krb5_enctypes;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tlong: 32;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tconst struct xattr_handler * const *s_xattr;\n\tconst struct fscrypt_operations *s_cop;\n\tstruct fscrypt_keyring *s_master_keys;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\tlong: 32;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct supplier_bindings {\n\tstruct device_node * (*parse_prop)(struct device_node *, const char *, int);\n\tstruct device_node * (*get_con_dev)(struct device_node *);\n\tbool optional;\n\tu8 fwlink_flags;\n};\n\nstruct suspend_stats {\n\tunsigned int step_failures[8];\n\tunsigned int success;\n\tunsigned int fail;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tlong: 32;\n\tu64 last_hw_sleep;\n\tu64 total_hw_sleep;\n\tu64 max_hw_sleep;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nstruct svc_deferred_req {\n\tu32 prot;\n\tstruct svc_xprt *xprt;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tstruct __kernel_sockaddr_storage daddr;\n\tsize_t daddrlen;\n\tvoid *xprt_ctxt;\n\tstruct cache_deferred_req handle;\n\tint argslen;\n\t__be32 args[0];\n};\n\nstruct svc_info {\n\tstruct svc_serv *serv;\n\tstruct mutex *mutex;\n};\n\nstruct svc_pool {\n\tunsigned int sp_id;\n\tunsigned int sp_nrthreads;\n\tunsigned int sp_nrthrmin;\n\tunsigned int sp_nrthrmax;\n\tstruct lwq sp_xprts;\n\tstruct list_head sp_all_threads;\n\tstruct llist_head sp_idle_threads;\n\tstruct percpu_counter sp_messages_arrived;\n\tstruct percpu_counter sp_sockets_queued;\n\tstruct percpu_counter sp_threads_woken;\n\tlong unsigned int sp_flags;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct svc_pool_map {\n\tint count;\n\tint mode;\n\tunsigned int npools;\n\tunsigned int *pool_to;\n\tunsigned int *to_pool;\n};\n\nstruct svc_procedure {\n\t__be32 (*pc_func)(struct svc_rqst *);\n\tbool (*pc_decode)(struct svc_rqst *, struct xdr_stream *);\n\tbool (*pc_encode)(struct svc_rqst *, struct xdr_stream *);\n\tvoid (*pc_release)(struct svc_rqst *);\n\tunsigned int pc_argsize;\n\tunsigned int pc_argzero;\n\tunsigned int pc_ressize;\n\tunsigned int pc_cachetype;\n\tunsigned int pc_xdrressize;\n\tconst char *pc_name;\n};\n\nstruct svc_process_info {\n\tunion {\n\t\tint (*dispatch)(struct svc_rqst *);\n\t\tstruct {\n\t\t\tunsigned int lovers;\n\t\t\tunsigned int hivers;\n\t\t} mismatch;\n\t};\n};\n\nstruct svc_version;\n\nstruct svc_program {\n\tu32 pg_prog;\n\tunsigned int pg_lovers;\n\tunsigned int pg_hivers;\n\tunsigned int pg_nvers;\n\tconst struct svc_version **pg_vers;\n\tchar *pg_name;\n\tchar *pg_class;\n\tenum svc_auth_status (*pg_authenticate)(struct svc_rqst *);\n\t__be32 (*pg_init_request)(struct svc_rqst *, const struct svc_program *, struct svc_process_info *);\n\tint (*pg_rpcbind_set)(struct net *, const struct svc_program *, u32, int, short unsigned int, short unsigned int);\n};\n\nstruct xdr_stream {\n\t__be32 *p;\n\tstruct xdr_buf *buf;\n\t__be32 *end;\n\tstruct kvec *iov;\n\tstruct kvec scratch;\n\tstruct page **page_ptr;\n\tvoid *page_kaddr;\n\tunsigned int nwords;\n\tstruct rpc_rqst *rqst;\n};\n\nstruct svc_rqst {\n\tstruct list_head rq_all;\n\tstruct llist_node rq_idle;\n\tstruct callback_head rq_rcu_head;\n\tstruct svc_xprt *rq_xprt;\n\tstruct __kernel_sockaddr_storage rq_addr;\n\tsize_t rq_addrlen;\n\tstruct __kernel_sockaddr_storage rq_daddr;\n\tsize_t rq_daddrlen;\n\tstruct svc_serv *rq_server;\n\tstruct svc_pool *rq_pool;\n\tconst struct svc_procedure *rq_procinfo;\n\tstruct auth_ops *rq_authop;\n\tstruct svc_cred rq_cred;\n\tvoid *rq_xprt_ctxt;\n\tstruct svc_deferred_req *rq_deferred;\n\tstruct xdr_buf rq_arg;\n\tstruct xdr_stream rq_arg_stream;\n\tstruct xdr_stream rq_res_stream;\n\tstruct folio *rq_scratch_folio;\n\tstruct xdr_buf rq_res;\n\tlong unsigned int rq_maxpages;\n\tstruct page **rq_pages;\n\tstruct page **rq_respages;\n\tstruct page **rq_next_page;\n\tstruct page **rq_page_end;\n\tstruct folio_batch rq_fbatch;\n\tstruct bio_vec *rq_bvec;\n\t__be32 rq_xid;\n\tu32 rq_prog;\n\tu32 rq_vers;\n\tu32 rq_proc;\n\tu32 rq_prot;\n\tint rq_cachetype;\n\tlong unsigned int rq_flags;\n\tktime_t rq_qtime;\n\tvoid *rq_argp;\n\tvoid *rq_resp;\n\t__be32 *rq_accept_statp;\n\tvoid *rq_auth_data;\n\t__be32 rq_auth_stat;\n\tint rq_auth_slack;\n\tint rq_reserved;\n\tlong: 32;\n\tktime_t rq_stime;\n\tstruct cache_req rq_chandle;\n\tstruct auth_domain *rq_client;\n\tstruct auth_domain *rq_gssclient;\n\tstruct task_struct *rq_task;\n\tstruct net *rq_bc_net;\n\tint rq_err;\n\tlong unsigned int bc_to_initval;\n\tunsigned int bc_to_retries;\n\tunsigned int rq_status_counter;\n\tvoid **rq_lease_breaker;\n\tlong: 32;\n};\n\nstruct svc_stat;\n\nstruct svc_serv {\n\tstruct svc_program *sv_programs;\n\tstruct svc_stat *sv_stats;\n\tspinlock_t sv_lock;\n\tunsigned int sv_nprogs;\n\tunsigned int sv_nrthreads;\n\tunsigned int sv_max_payload;\n\tunsigned int sv_max_mesg;\n\tunsigned int sv_xdrsize;\n\tstruct list_head sv_permsocks;\n\tstruct list_head sv_tempsocks;\n\tint sv_tmpcnt;\n\tstruct timer_list sv_temptimer;\n\tchar *sv_name;\n\tunsigned int sv_nrpools;\n\tbool sv_is_pooled;\n\tstruct svc_pool *sv_pools;\n\tint (*sv_threadfn)(void *);\n\tstruct lwq sv_cb_list;\n\tbool sv_bc_enabled;\n};\n\nstruct svc_xprt_class;\n\nstruct svc_xprt_ops;\n\nstruct svc_xprt {\n\tstruct svc_xprt_class *xpt_class;\n\tconst struct svc_xprt_ops *xpt_ops;\n\tstruct kref xpt_ref;\n\tlong: 32;\n\tktime_t xpt_qtime;\n\tstruct list_head xpt_list;\n\tstruct lwq_node xpt_ready;\n\tlong unsigned int xpt_flags;\n\tstruct svc_serv *xpt_server;\n\tatomic_t xpt_reserved;\n\tatomic_t xpt_nr_rqsts;\n\tstruct mutex xpt_mutex;\n\tspinlock_t xpt_lock;\n\tvoid *xpt_auth_cache;\n\tstruct list_head xpt_deferred;\n\tstruct __kernel_sockaddr_storage xpt_local;\n\tsize_t xpt_locallen;\n\tstruct __kernel_sockaddr_storage xpt_remote;\n\tsize_t xpt_remotelen;\n\tchar xpt_remotebuf[58];\n\tstruct list_head xpt_users;\n\tstruct net *xpt_net;\n\tnetns_tracker ns_tracker;\n\tconst struct cred *xpt_cred;\n\tstruct rpc_xprt *xpt_bc_xprt;\n\tstruct rpc_xprt_switch *xpt_bc_xps;\n};\n\nstruct svc_sock {\n\tstruct svc_xprt sk_xprt;\n\tstruct socket *sk_sock;\n\tstruct sock *sk_sk;\n\tvoid (*sk_ostate)(struct sock *);\n\tvoid (*sk_odata)(struct sock *);\n\tvoid (*sk_owspace)(struct sock *);\n\tstruct bio_vec *sk_bvec;\n\t__be32 sk_marker;\n\tu32 sk_tcplen;\n\tu32 sk_datalen;\n\tstruct page_frag_cache sk_frag_cache;\n\tstruct completion sk_handshake_done;\n\tlong unsigned int sk_maxpages;\n\tstruct page *sk_pages[0];\n};\n\nstruct svc_stat {\n\tstruct svc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcbadfmt;\n\tunsigned int rpcbadauth;\n\tunsigned int rpcbadclnt;\n};\n\nstruct svc_version {\n\tu32 vs_vers;\n\tu32 vs_nproc;\n\tconst struct svc_procedure *vs_proc;\n\tlong unsigned int *vs_count;\n\tu32 vs_xdrsize;\n\tbool vs_hidden;\n\tbool vs_rpcb_optnl;\n\tbool vs_need_cong_ctrl;\n\tint (*vs_dispatch)(struct svc_rqst *);\n};\n\nstruct svc_xprt_class {\n\tconst char *xcl_name;\n\tstruct module *xcl_owner;\n\tconst struct svc_xprt_ops *xcl_ops;\n\tstruct list_head xcl_list;\n\tu32 xcl_max_payload;\n\tint xcl_ident;\n};\n\nstruct svc_xprt_ops {\n\tstruct svc_xprt * (*xpo_create)(struct svc_serv *, struct net *, struct sockaddr *, int, int);\n\tstruct svc_xprt * (*xpo_accept)(struct svc_xprt *);\n\tint (*xpo_has_wspace)(struct svc_xprt *);\n\tint (*xpo_recvfrom)(struct svc_rqst *);\n\tint (*xpo_sendto)(struct svc_rqst *);\n\tint (*xpo_result_payload)(struct svc_rqst *, unsigned int, unsigned int);\n\tvoid (*xpo_release_ctxt)(struct svc_xprt *, void *);\n\tvoid (*xpo_detach)(struct svc_xprt *);\n\tvoid (*xpo_free)(struct svc_xprt *);\n\tvoid (*xpo_kill_temp_xprt)(struct svc_xprt *);\n\tvoid (*xpo_handshake)(struct svc_xprt *);\n};\n\nstruct svc_xpt_user {\n\tstruct list_head list;\n\tvoid (*callback)(struct svc_xpt_user *);\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cgroup {\n\tatomic_t ids;\n};\n\nstruct swap_cgroup_ctrl {\n\tstruct swap_cgroup *map;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tlong: 32;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[1];\n\tstruct list_head frag_clusters[1];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[1];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[256];\n};\n\nstruct switchdev_mst_state {\n\tu16 msti;\n\tu8 state;\n};\n\nstruct switchdev_brport_flags {\n\tlong unsigned int val;\n\tlong unsigned int mask;\n};\n\nstruct switchdev_vlan_msti {\n\tu16 vid;\n\tu16 msti;\n};\n\nstruct switchdev_attr {\n\tstruct net_device *orig_dev;\n\tenum switchdev_attr_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n\tunion {\n\t\tu8 stp_state;\n\t\tstruct switchdev_mst_state mst_state;\n\t\tstruct switchdev_brport_flags brport_flags;\n\t\tbool mrouter;\n\t\tclock_t ageing_time;\n\t\tbool vlan_filtering;\n\t\tu16 vlan_protocol;\n\t\tbool mst;\n\t\tbool mc_disabled;\n\t\tu8 mrp_port_role;\n\t\tstruct switchdev_vlan_msti vlan_msti;\n\t} u;\n};\n\nstruct switchdev_brport {\n\tstruct net_device *dev;\n\tconst void *ctx;\n\tstruct notifier_block *atomic_nb;\n\tstruct notifier_block *blocking_nb;\n\tbool tx_fwd_offload;\n};\n\ntypedef void switchdev_deferred_func_t(struct net_device *, const void *);\n\nstruct switchdev_deferred_item {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tswitchdev_deferred_func_t *func;\n\tlong unsigned int data[0];\n};\n\nstruct switchdev_nested_priv {\n\tbool (*check_cb)(const struct net_device *);\n\tbool (*foreign_dev_check_cb)(const struct net_device *, const struct net_device *);\n\tconst struct net_device *dev;\n\tstruct net_device *lower_dev;\n};\n\nstruct switchdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n\tconst void *ctx;\n};\n\nstruct switchdev_notifier_brport_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_brport brport;\n};\n\nstruct switchdev_notifier_fdb_info {\n\tstruct switchdev_notifier_info info;\n\tconst unsigned char *addr;\n\tu16 vid;\n\tu8 added_by_user: 1;\n\tu8 is_local: 1;\n\tu8 locked: 1;\n\tu8 offloaded: 1;\n};\n\nstruct switchdev_notifier_port_attr_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_attr *attr;\n\tbool handled;\n};\n\nstruct switchdev_obj;\n\nstruct switchdev_notifier_port_obj_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_obj *obj;\n\tbool handled;\n};\n\nstruct switchdev_obj {\n\tstruct list_head list;\n\tstruct net_device *orig_dev;\n\tenum switchdev_obj_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n};\n\nstruct switchdev_obj_mrp {\n\tstruct switchdev_obj obj;\n\tstruct net_device *p_port;\n\tstruct net_device *s_port;\n\tu32 ring_id;\n\tu16 prio;\n};\n\nstruct switchdev_obj_port_mdb {\n\tstruct switchdev_obj obj;\n\tunsigned char addr[6];\n\tu16 vid;\n};\n\nstruct switchdev_obj_port_vlan {\n\tstruct switchdev_obj obj;\n\tu16 flags;\n\tu16 vid;\n\tbool changed;\n};\n\nstruct switchdev_obj_ring_role_mrp {\n\tstruct switchdev_obj obj;\n\tu8 ring_role;\n\tu32 ring_id;\n\tu8 sw_backup;\n};\n\nstruct swmii_regs {\n\tu16 bmsr;\n\tu16 lpa;\n\tu16 lpagb;\n\tu16 estat;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tbool pt_port_open;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_user_dispatch {};\n\nstruct syscon {\n\tstruct device_node *np;\n\tstruct regmap *regmap;\n\tstruct reset_control *reset;\n\tstruct list_head list;\n};\n\nstruct syscon_led {\n\tstruct led_classdev cdev;\n\tstruct regmap *map;\n\tu32 offset;\n\tu32 mask;\n\tbool state;\n};\n\nstruct syscon_poweroff_data {\n\tstruct regmap *map;\n\tu32 offset;\n\tu32 value;\n\tu32 mask;\n};\n\nstruct syscon_reboot_context {\n\tstruct regmap *map;\n\tconst struct reboot_data *rd;\n\tstruct reboot_mode_bits catchall;\n\tstruct notifier_block restart_handler;\n};\n\nstruct syscon_reboot_mode {\n\tstruct regmap *map;\n\tstruct reboot_mode_driver reboot;\n\tu32 offset;\n\tu32 mask;\n};\n\nstruct syscore_ops;\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[8];\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[24];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tunsigned int shift;\n\tunsigned int shift_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[24];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tlong: 32;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t load_avg;\n\tlong: 32;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct autogroup *autogroup;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {};\n\nstruct thread_struct {\n\tlong unsigned int reg16;\n\tlong unsigned int reg17;\n\tlong unsigned int reg18;\n\tlong unsigned int reg19;\n\tlong unsigned int reg20;\n\tlong unsigned int reg21;\n\tlong unsigned int reg22;\n\tlong unsigned int reg23;\n\tlong unsigned int reg29;\n\tlong unsigned int reg30;\n\tlong unsigned int reg31;\n\tlong unsigned int cp0_status;\n\tstruct mips_fpu_struct fpu;\n\tatomic_t bd_emu_frame;\n\tlong unsigned int bd_emu_branch_pc;\n\tlong unsigned int bd_emu_cont_pc;\n\tlong unsigned int emulated_fp;\n\tcpumask_t user_cpus_allowed;\n\tstruct mips_dsp_state dsp;\n\tunion mips_watch_reg_state watch;\n\tlong unsigned int cp0_badvaddr;\n\tlong unsigned int cp0_baduaddr;\n\tlong unsigned int error_code;\n\tlong unsigned int trap_nr;\n\tstruct mips_abi *abi;\n\tlong: 32;\n};\n\nstruct task_struct {\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tlong: 32;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tlong: 32;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct task_group *sched_task_group;\n\tstruct callback_head sched_throttle_work;\n\tstruct list_head throttle_node;\n\tbool throttled;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_statistics stats;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int use_memdelay: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tlong: 32;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tlong: 32;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tlong: 32;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tunsigned int memcg_nr_pages_over_high;\n\tstruct mem_cgroup *active_memcg;\n\tstruct obj_cgroup *objcg;\n\tstruct gendisk *throttle_disk;\n\tstruct kmap_ctrl kmap_ctrl;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tstruct thread_struct thread;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tlong: 32;\n\tstruct tcf_t tcfa_tm;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_cbs_qopt_offload {\n\tu8 enable;\n\ts32 queue;\n\ts32 hicredit;\n\ts32 locredit;\n\ts32 idleslope;\n\ts32 sendslope;\n};\n\nstruct tc_cls_matchall_offload {\n\tstruct flow_cls_common_offload common;\n\tenum tc_matchall_command command;\n\tstruct flow_rule *rule;\n\tlong: 32;\n\tstruct flow_stats stats;\n\tbool use_act_stats;\n\tlong unsigned int cookie;\n};\n\nstruct tc_cls_u32_hnode {\n\tu32 handle;\n\tu32 prio;\n\tunsigned int divisor;\n};\n\nstruct tcf_exts;\n\nstruct tc_u32_sel;\n\nstruct tc_cls_u32_knode {\n\tstruct tcf_exts *exts;\n\tstruct tcf_result *res;\n\tstruct tc_u32_sel *sel;\n\tu32 handle;\n\tu32 val;\n\tu32 mask;\n\tu32 link_handle;\n\tu8 fshift;\n};\n\nstruct tc_cls_u32_offload {\n\tstruct flow_cls_common_offload common;\n\tenum tc_clsu32_command command;\n\tunion {\n\t\tstruct tc_cls_u32_knode knode;\n\t\tstruct tc_cls_u32_hnode hnode;\n\t};\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_etf_qopt_offload {\n\tu8 enable;\n\ts32 queue;\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_mqprio_caps {\n\tbool validate_queue_counts: 1;\n};\n\nstruct tc_mqprio_qopt {\n\t__u8 num_tc;\n\t__u8 prio_tc_map[16];\n\t__u8 hw;\n\t__u16 count[16];\n\t__u16 offset[16];\n};\n\nstruct tc_mqprio_qopt_offload {\n\tstruct tc_mqprio_qopt qopt;\n\tstruct netlink_ext_ack *extack;\n\tu16 mode;\n\tu16 shaper;\n\tu32 flags;\n\tu64 min_rate[16];\n\tu64 max_rate[16];\n\tlong unsigned int preemptible_tcs;\n\tlong: 32;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tc_taprio_caps {\n\tbool supports_queue_max_sdu: 1;\n\tbool gate_mask_per_txq: 1;\n\tbool broken_mqprio: 1;\n};\n\nstruct tc_taprio_qopt_stats {\n\tu64 window_drops;\n\tu64 tx_overruns;\n};\n\nstruct tc_taprio_qopt_queue_stats {\n\tint queue;\n\tlong: 32;\n\tstruct tc_taprio_qopt_stats stats;\n};\n\nstruct tc_taprio_sched_entry {\n\tu8 command;\n\tu32 gate_mask;\n\tu32 interval;\n};\n\nstruct tc_taprio_qopt_offload {\n\tenum tc_taprio_qopt_cmd cmd;\n\tlong: 32;\n\tunion {\n\t\tstruct tc_taprio_qopt_stats stats;\n\t\tstruct tc_taprio_qopt_queue_stats queue_stats;\n\t\tstruct {\n\t\t\tstruct tc_mqprio_qopt_offload mqprio;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t\tlong: 32;\n\t\t\tktime_t base_time;\n\t\t\tu64 cycle_time;\n\t\t\tu64 cycle_time_extension;\n\t\t\tu32 max_sdu[16];\n\t\t\tsize_t num_entries;\n\t\t\tstruct tc_taprio_sched_entry entries[0];\n\t\t\tlong: 32;\n\t\t};\n\t};\n};\n\nstruct tc_u32_key {\n\t__be32 mask;\n\t__be32 val;\n\tint off;\n\tint offmask;\n};\n\nstruct tc_u32_sel_hdr {\n\tunsigned char flags;\n\tunsigned char offshift;\n\tunsigned char nkeys;\n\t__be16 offmask;\n\t__u16 off;\n\tshort int offoff;\n\tshort int hoff;\n\t__be32 hmask;\n};\n\nstruct tc_u32_sel {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char flags;\n\t\t\tunsigned char offshift;\n\t\t\tunsigned char nkeys;\n\t\t\t__be16 offmask;\n\t\t\t__u16 off;\n\t\t\tshort int offoff;\n\t\t\tshort int hoff;\n\t\t\t__be32 hmask;\n\t\t};\n\t\tstruct tc_u32_sel_hdr hdr;\n\t};\n\tstruct tc_u32_key keys[0];\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_exts {\n\tint action;\n\tint police;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_walker;\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tlong: 32;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tlong: 32;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n\tlong: 32;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tlong: 32;\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tlong: 32;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t};\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 ae: 1;\n\t__u16 res1: 3;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tlong: 32;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tlong: 32;\n};\n\nstruct td {\n\t__hc32 hwINFO;\n\t__hc32 hwCBP;\n\t__hc32 hwNextTD;\n\t__hc32 hwBE;\n\t__hc16 hwPSW[2];\n\t__u8 index;\n\tstruct ed *ed;\n\tstruct td *td_hash;\n\tstruct td *next_dl_td;\n\tstruct urb *urb;\n\tdma_addr_t td_dma;\n\tdma_addr_t data_dma;\n\tstruct list_head td_list;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tchar c_line;\n\tunsigned char c_cc[23];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[23];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[23];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct thread_deferred_req {\n\tstruct cache_deferred_req handle;\n\tstruct completion completion;\n};\n\nstruct thread_info {\n\tstruct task_struct *task;\n\tlong unsigned int flags;\n\tlong unsigned int tp_value;\n\t__u32 cpu;\n\tint preempt_count;\n\tstruct pt_regs *regs;\n\tlong int syscall;\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tlong: 32;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tlong: 32;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tlong: 32;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tlong: 32;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tlong: 32;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[18];\n\tstruct hlist_head vectors[576];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_of {\n\tunsigned int flags;\n\tstruct device_node *np;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device clkevt;\n\tstruct of_timer_base of_base;\n\tstruct of_timer_irq of_irq;\n\tstruct of_timer_clk of_clk;\n\tvoid *private_data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tlong: 32;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timestamp_event_queue {\n\tstruct ptp_extts_event buf[128];\n\tint head;\n\tint tail;\n\tspinlock_t lock;\n\tstruct list_head qlist;\n\tlong unsigned int *mask;\n\tstruct dentry *debugfs_instance;\n\tstruct debugfs_u32_array dfs_bitmap;\n\tlong: 32;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct timing_regs {\n\tunsigned int tsusta;\n\tunsigned int tsusto;\n\tunsigned int thdsta;\n\tunsigned int tsudat;\n\tunsigned int tbuf;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tlong: 32;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tlong: 32;\n\tstruct tk_read_base base[2];\n};\n\nstruct tlb_reg_save {\n\tlong unsigned int a;\n\tlong unsigned int b;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\ntypedef void (*tls_done_func_t)(void *, int, key_serial_t);\n\nstruct tls_handshake_args {\n\tstruct socket *ta_sock;\n\ttls_done_func_t ta_done;\n\tvoid *ta_data;\n\tconst char *ta_peername;\n\tunsigned int ta_timeout_ms;\n\tkey_serial_t ta_keyring;\n\tkey_serial_t ta_my_cert;\n\tkey_serial_t ta_my_privkey;\n\tunsigned int ta_num_peerids;\n\tkey_serial_t ta_my_peerids[5];\n};\n\nstruct tls_handshake_req {\n\tvoid (*th_consumer_done)(void *, int, key_serial_t);\n\tvoid *th_consumer_data;\n\tint th_type;\n\tunsigned int th_timeout_ms;\n\tint th_auth_mode;\n\tconst char *th_peername;\n\tkey_serial_t th_keyring;\n\tkey_serial_t th_certificate;\n\tkey_serial_t th_privkey;\n\tunsigned int th_num_peerids;\n\tkey_serial_t th_peerid[5];\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n\tlong: 32;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tlong: 32;\n\tu64 now;\n\tbool check;\n\tlong: 32;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnl_ptk_info {\n\tlong unsigned int flags[1];\n\t__be16 proto;\n\t__be32 key;\n\t__be32 seq;\n\tint hdr_len;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8172];\n};\n\nstruct tracepoint_func;\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n};\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tlong: 32;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct typec_connector {\n\tvoid (*attach)(struct typec_connector *, struct device *);\n\tvoid (*deattach)(struct typec_connector *, struct device *);\n};\n\nstruct u32_fract {\n\t__u32 numerator;\n\t__u32 denominator;\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n\tlong: 32;\n};\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n\tvoid (*setup_timer)(struct uart_8250_port *);\n};\n\ntypedef struct uart_8250_port *class_serial8250_rpm_t;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tu16 bugs;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tu16 lsr_saved_flags;\n\tu16 lsr_save_mask;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *, bool);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *, bool);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*start_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\ntypedef struct uart_port *class_uart_port_lock_irq_t;\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct uasm_label {\n\tu32 *addr;\n\tint lab;\n};\n\nstruct uasm_reloc {\n\tu32 *addr;\n\tunsigned int type;\n\tint lab;\n};\n\nstruct ubi_ainf_peb {\n\tint ec;\n\tint pnum;\n\tint vol_id;\n\tint lnum;\n\tunsigned int scrub: 1;\n\tunsigned int copy_flag: 1;\n\tlong: 32;\n\tlong long unsigned int sqnum;\n\tunion {\n\t\tstruct rb_node rb;\n\t\tstruct list_head list;\n\t} u;\n\tlong: 32;\n};\n\nstruct ubi_ainf_volume {\n\tint vol_id;\n\tint highest_lnum;\n\tint leb_count;\n\tint vol_type;\n\tint used_ebs;\n\tint last_data_size;\n\tint data_pad;\n\tint compat;\n\tstruct rb_node rb;\n\tstruct rb_root root;\n};\n\nstruct ubi_ec_hdr;\n\nstruct ubi_vid_io_buf;\n\nstruct ubi_attach_info {\n\tstruct rb_root volumes;\n\tstruct list_head corr;\n\tstruct list_head free;\n\tstruct list_head erase;\n\tstruct list_head alien;\n\tstruct list_head fastmap;\n\tint corr_peb_count;\n\tint empty_peb_count;\n\tint alien_peb_count;\n\tint bad_peb_count;\n\tint maybe_bad_peb_count;\n\tint vols_found;\n\tint highest_vol_id;\n\tint is_empty;\n\tint force_full_scan;\n\tint min_ec;\n\tint max_ec;\n\tlong long unsigned int max_sqnum;\n\tint mean_ec;\n\tlong: 32;\n\tuint64_t ec_sum;\n\tint ec_count;\n\tstruct kmem_cache *aeb_slab_cache;\n\tstruct ubi_ec_hdr *ech;\n\tstruct ubi_vid_io_buf *vidb;\n};\n\nstruct ubi_attach_req {\n\t__s32 ubi_num;\n\t__s32 mtd_num;\n\t__s32 vid_hdr_offset;\n\t__s16 max_beb_per1024;\n\t__s8 disable_fm;\n\t__s8 need_resv_pool;\n\t__s8 padding[8];\n};\n\nstruct ubi_debug_info {\n\tunsigned int chk_gen: 1;\n\tunsigned int chk_io: 1;\n\tunsigned int chk_fastmap: 1;\n\tunsigned int disable_bgt: 1;\n\tunsigned int emulate_bitflips: 1;\n\tunsigned int emulate_io_failures: 1;\n\tunsigned int emulate_power_cut: 2;\n\tunsigned int power_cut_counter;\n\tunsigned int power_cut_min;\n\tunsigned int power_cut_max;\n\tunsigned int emulate_failures;\n\tchar dfs_dir_name[6];\n\tstruct dentry *dfs_dir;\n\tstruct dentry *dfs_chk_gen;\n\tstruct dentry *dfs_chk_io;\n\tstruct dentry *dfs_chk_fastmap;\n\tstruct dentry *dfs_disable_bgt;\n\tstruct dentry *dfs_emulate_bitflips;\n\tstruct dentry *dfs_emulate_io_failures;\n\tstruct dentry *dfs_emulate_power_cut;\n\tstruct dentry *dfs_power_cut_min;\n\tstruct dentry *dfs_power_cut_max;\n\tstruct dentry *dfs_emulate_failures;\n};\n\nstruct ubi_fm_pool {\n\tint pebs[256];\n\tint used;\n\tint size;\n\tint max_size;\n};\n\nstruct ubi_volume;\n\nstruct ubi_vtbl_record;\n\nstruct ubi_fastmap_layout;\n\nstruct ubi_wl_entry;\n\nstruct ubi_device {\n\tstruct cdev cdev;\n\tlong: 32;\n\tstruct device dev;\n\tint ubi_num;\n\tchar ubi_name[9];\n\tint vol_count;\n\tstruct ubi_volume *volumes[129];\n\tspinlock_t volumes_lock;\n\tint ref_count;\n\tint image_seq;\n\tbool is_dead;\n\tint rsvd_pebs;\n\tint avail_pebs;\n\tint beb_rsvd_pebs;\n\tint beb_rsvd_level;\n\tint bad_peb_limit;\n\tint autoresize_vol_id;\n\tint vtbl_slots;\n\tint vtbl_size;\n\tstruct ubi_vtbl_record *vtbl;\n\tstruct mutex device_mutex;\n\tint max_ec;\n\tint mean_ec;\n\tlong: 32;\n\tlong long unsigned int global_sqnum;\n\tspinlock_t ltree_lock;\n\tstruct rb_root ltree;\n\tstruct mutex alc_mutex;\n\tint fm_disabled;\n\tstruct ubi_fastmap_layout *fm;\n\tstruct ubi_fm_pool fm_pool;\n\tstruct ubi_fm_pool fm_wl_pool;\n\tstruct rw_semaphore fm_eba_sem;\n\tstruct rw_semaphore fm_protect;\n\tvoid *fm_buf;\n\tsize_t fm_size;\n\tstruct work_struct fm_work;\n\tint fm_work_scheduled;\n\tint fast_attach;\n\tstruct ubi_wl_entry *fm_anchor;\n\tint fm_do_produce_anchor;\n\tint fm_pool_rsv_cnt;\n\tstruct rb_root used;\n\tstruct rb_root erroneous;\n\tstruct rb_root free;\n\tint free_count;\n\tstruct rb_root scrub;\n\tstruct list_head pq[10];\n\tint pq_head;\n\tspinlock_t wl_lock;\n\tstruct mutex move_mutex;\n\tstruct rw_semaphore work_sem;\n\tint wl_scheduled;\n\tstruct ubi_wl_entry **lookuptbl;\n\tstruct ubi_wl_entry *move_from;\n\tstruct ubi_wl_entry *move_to;\n\tint move_to_put;\n\tstruct list_head works;\n\tint works_count;\n\tstruct task_struct *bgt_thread;\n\tint thread_enabled;\n\tchar bgt_name[13];\n\tlong: 32;\n\tlong long int flash_size;\n\tint peb_count;\n\tint peb_size;\n\tint bad_peb_count;\n\tint good_peb_count;\n\tint corr_peb_count;\n\tint erroneous_peb_count;\n\tint max_erroneous;\n\tint min_io_size;\n\tint hdrs_min_io_size;\n\tint ro_mode;\n\tint leb_size;\n\tint leb_start;\n\tint ec_hdr_alsize;\n\tint vid_hdr_alsize;\n\tint vid_hdr_offset;\n\tint vid_hdr_aloffset;\n\tint vid_hdr_shift;\n\tunsigned int bad_allowed: 1;\n\tunsigned int nor_flash: 1;\n\tint max_write_size;\n\tstruct mtd_info *mtd;\n\tvoid *peb_buf;\n\tstruct mutex buf_mutex;\n\tstruct mutex ckvol_mutex;\n\tstruct ubi_debug_info dbg;\n\tlong: 32;\n};\n\nstruct ubi_device_info {\n\tint ubi_num;\n\tint leb_size;\n\tint leb_start;\n\tint min_io_size;\n\tint max_write_size;\n\tint ro_mode;\n\tdev_t cdev;\n};\n\nstruct ubi_eba_entry {\n\tint pnum;\n};\n\nstruct ubi_eba_leb_desc {\n\tint lnum;\n\tint pnum;\n};\n\nstruct ubi_eba_table {\n\tstruct ubi_eba_entry *entries;\n};\n\nstruct ubi_ec_hdr {\n\t__be32 magic;\n\t__u8 version;\n\t__u8 padding1[3];\n\t__be64 ec;\n\t__be32 vid_hdr_offset;\n\t__be32 data_offset;\n\t__be32 image_seq;\n\t__u8 padding2[32];\n\t__be32 hdr_crc;\n};\n\nstruct ubi_ecinfo_req {\n\t__s32 start;\n\t__s32 length;\n\t__s32 read_length;\n\t__s8 padding[16];\n\t__s32 erase_counters[0];\n};\n\nstruct ubi_fastmap_layout {\n\tstruct ubi_wl_entry *e[32];\n\tint to_be_tortured[32];\n\tint used_blocks;\n\tint max_pool_size;\n\tint max_wl_pool_size;\n};\n\nstruct ubi_leb_change_req {\n\t__s32 lnum;\n\t__s32 bytes;\n\t__s8 dtype;\n\t__s8 padding[7];\n};\n\nstruct ubi_ltree_entry {\n\tstruct rb_node rb;\n\tint vol_id;\n\tint lnum;\n\tint users;\n\tstruct rw_semaphore mutex;\n};\n\nstruct ubi_map_req {\n\t__s32 lnum;\n\t__s8 dtype;\n\t__s8 padding[3];\n};\n\nstruct ubi_mkvol_req {\n\t__s32 vol_id;\n\t__s32 alignment;\n\t__s64 bytes;\n\t__s8 vol_type;\n\t__u8 flags;\n\t__s16 name_len;\n\t__s8 padding2[4];\n\tchar name[128];\n};\n\nstruct ubi_volume_info {\n\tint ubi_num;\n\tint vol_id;\n\tint size;\n\tlong: 32;\n\tlong long int used_bytes;\n\tint used_ebs;\n\tint vol_type;\n\tint corrupted;\n\tint upd_marker;\n\tint alignment;\n\tint usable_leb_size;\n\tint name_len;\n\tconst char *name;\n\tdev_t cdev;\n\tstruct device *dev;\n};\n\nstruct ubi_notification {\n\tstruct ubi_device_info di;\n\tlong: 32;\n\tstruct ubi_volume_info vi;\n};\n\nstruct ubi_rename_entry {\n\tint new_name_len;\n\tchar new_name[128];\n\tint remove;\n\tstruct ubi_volume_desc *desc;\n\tstruct list_head list;\n};\n\nstruct ubi_rnvol_req {\n\t__s32 count;\n\t__s8 padding1[12];\n\tstruct {\n\t\t__s32 vol_id;\n\t\t__s16 name_len;\n\t\t__s8 padding2[2];\n\t\tchar name[128];\n\t} ents[32];\n};\n\nstruct ubi_rsvol_req {\n\t__s64 bytes;\n\t__s32 vol_id;\n};\n\nstruct ubi_set_vol_prop_req {\n\t__u8 property;\n\t__u8 padding[7];\n\t__u64 value;\n};\n\nstruct ubi_sgl {\n\tint list_pos;\n\tint page_pos;\n\tstruct scatterlist sg[64];\n};\n\nstruct ubi_vid_hdr {\n\t__be32 magic;\n\t__u8 version;\n\t__u8 vol_type;\n\t__u8 copy_flag;\n\t__u8 compat;\n\t__be32 vol_id;\n\t__be32 lnum;\n\t__u8 padding1[4];\n\t__be32 data_size;\n\t__be32 used_ebs;\n\t__be32 data_pad;\n\t__be32 data_crc;\n\t__u8 padding2[4];\n\t__be64 sqnum;\n\t__u8 padding3[12];\n\t__be32 hdr_crc;\n};\n\nstruct ubi_vid_io_buf {\n\tstruct ubi_vid_hdr *hdr;\n\tvoid *buffer;\n};\n\nstruct ubi_volume {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct ubi_device *ubi;\n\tint vol_id;\n\tint ref_count;\n\tint readers;\n\tint writers;\n\tint exclusive;\n\tint metaonly;\n\tbool is_dead;\n\tint reserved_pebs;\n\tint vol_type;\n\tint usable_leb_size;\n\tint used_ebs;\n\tint last_eb_bytes;\n\tlong long int used_bytes;\n\tint alignment;\n\tint data_pad;\n\tint name_len;\n\tchar name[128];\n\tint upd_ebs;\n\tint ch_lnum;\n\tlong: 32;\n\tlong long int upd_bytes;\n\tlong long int upd_received;\n\tvoid *upd_buf;\n\tstruct ubi_eba_table *eba_tbl;\n\tunsigned int skip_check: 1;\n\tunsigned int checked: 1;\n\tunsigned int corrupted: 1;\n\tunsigned int upd_marker: 1;\n\tunsigned int updating: 1;\n\tunsigned int changing_leb: 1;\n\tunsigned int direct_writes: 1;\n\tlong: 32;\n};\n\nstruct ubi_volume_desc {\n\tstruct ubi_volume *vol;\n\tint mode;\n};\n\nstruct ubi_vtbl_record {\n\t__be32 reserved_pebs;\n\t__be32 alignment;\n\t__be32 data_pad;\n\t__u8 vol_type;\n\t__u8 upd_marker;\n\t__be16 name_len;\n\t__u8 name[128];\n\t__u8 flags;\n\t__u8 padding[23];\n\t__be32 crc;\n};\n\nstruct ubi_wl_entry {\n\tunion {\n\t\tstruct rb_node rb;\n\t\tstruct list_head list;\n\t} u;\n\tint ec;\n\tint pnum;\n};\n\nstruct ubi_work {\n\tstruct list_head list;\n\tint (*func)(struct ubi_device *, struct ubi_work *, int);\n\tstruct ubi_wl_entry *e;\n\tint vol_id;\n\tint lnum;\n\tint torture;\n};\n\nstruct ubiblock {\n\tstruct ubi_volume_desc *desc;\n\tint ubi_num;\n\tint vol_id;\n\tint refcnt;\n\tint leb_size;\n\tstruct gendisk *gd;\n\tstruct request_queue *rq;\n\tstruct mutex dev_mutex;\n\tstruct list_head list;\n\tstruct blk_mq_tag_set tag_set;\n};\n\nstruct ubiblock_param {\n\tint ubi_num;\n\tint vol_id;\n\tchar name[64];\n};\n\nstruct ubiblock_pdu {\n\tstruct ubi_sgl usgl;\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[12];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n\tlong: 32;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 32;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct uffd_msg {\n\t__u8 event;\n\t__u8 reserved1;\n\t__u16 reserved2;\n\t__u32 reserved3;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 address;\n\t\t\tunion {\n\t\t\t\t__u32 ptid;\n\t\t\t} feat;\n\t\t\tlong: 32;\n\t\t} pagefault;\n\t\tstruct {\n\t\t\t__u32 ufd;\n\t\t} fork;\n\t\tstruct {\n\t\t\t__u64 from;\n\t\t\t__u64 to;\n\t\t\t__u64 len;\n\t\t} remap;\n\t\tstruct {\n\t\t\t__u64 start;\n\t\t\t__u64 end;\n\t\t} remove;\n\t\tstruct {\n\t\t\t__u64 reserved1;\n\t\t\t__u64 reserved2;\n\t\t\t__u64 reserved3;\n\t\t} reserved;\n\t} arg;\n};\n\nstruct uffdio_api {\n\t__u64 api;\n\t__u64 features;\n\t__u64 ioctls;\n};\n\nstruct uffdio_range {\n\t__u64 start;\n\t__u64 len;\n};\n\nstruct uffdio_continue {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__s64 mapped;\n};\n\nstruct uffdio_copy {\n\t__u64 dst;\n\t__u64 src;\n\t__u64 len;\n\t__u64 mode;\n\t__s64 copy;\n};\n\nstruct uffdio_move {\n\t__u64 dst;\n\t__u64 src;\n\t__u64 len;\n\t__u64 mode;\n\t__s64 move;\n};\n\nstruct uffdio_poison {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__s64 updated;\n};\n\nstruct uffdio_register {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__u64 ioctls;\n};\n\nstruct uffdio_writeprotect {\n\tstruct uffdio_range range;\n\t__u64 mode;\n};\n\nstruct uffdio_zeropage {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__s64 zeropage;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct uncharge_gather {\n\tstruct mem_cgroup *memcg;\n\tlong unsigned int nr_memory;\n\tlong unsigned int pgpgout;\n\tlong unsigned int nr_kmem;\n\tint nid;\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct utf8data;\n\nstruct utf8data_table;\n\nstruct unicode_map {\n\tunsigned int version;\n\tconst struct utf8data *ntab[2];\n\tconst struct utf8data_table *tables;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_domain {\n\tstruct auth_domain h;\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_gid {\n\tstruct cache_head h;\n\tkuid_t uid;\n\tstruct group_info *gi;\n\tstruct callback_head rcu;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\ntypedef void (*usb_complete_t)(struct urb *);\n\nstruct usb_iso_packet_descriptor {\n\tunsigned int offset;\n\tunsigned int length;\n\tunsigned int actual_length;\n\tint status;\n};\n\nstruct usb_anchor;\n\nstruct urb {\n\tstruct kref kref;\n\tint unlinked;\n\tvoid *hcpriv;\n\tatomic_t use_count;\n\tatomic_t reject;\n\tstruct list_head urb_list;\n\tstruct list_head anchor_list;\n\tstruct usb_anchor *anchor;\n\tstruct usb_device *dev;\n\tstruct usb_host_endpoint *ep;\n\tunsigned int pipe;\n\tunsigned int stream_id;\n\tint status;\n\tunsigned int transfer_flags;\n\tvoid *transfer_buffer;\n\tdma_addr_t transfer_dma;\n\tstruct scatterlist *sg;\n\tstruct sg_table *sgt;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tu32 transfer_buffer_length;\n\tu32 actual_length;\n\tunsigned char *setup_packet;\n\tdma_addr_t setup_dma;\n\tint start_frame;\n\tint number_of_packets;\n\tint interval;\n\tint error_count;\n\tvoid *context;\n\tusb_complete_t complete;\n\tstruct usb_iso_packet_descriptor iso_frame_desc[0];\n};\n\nstruct urb_priv {\n\tstruct ed *ed;\n\tu16 length;\n\tu16 td_cnt;\n\tstruct list_head pending;\n\tstruct td *td[0];\n};\n\nstruct xhci_segment;\n\nunion xhci_trb;\n\nstruct xhci_td {\n\tstruct list_head td_list;\n\tstruct list_head cancelled_td_list;\n\tint status;\n\tenum xhci_cancelled_td_status cancel_status;\n\tstruct urb *urb;\n\tstruct xhci_segment *start_seg;\n\tunion xhci_trb *start_trb;\n\tstruct xhci_segment *end_seg;\n\tunion xhci_trb *end_trb;\n\tstruct xhci_segment *bounce_seg;\n\tbool urb_length_set;\n\tbool error_mid_td;\n};\n\nstruct urb_priv___2 {\n\tint num_tds;\n\tint num_tds_done;\n\tstruct xhci_td td[0];\n};\n\ntypedef struct urb_priv urb_priv_t;\n\nstruct usage_priority {\n\t__u32 usage;\n\tbool global;\n\tunsigned int slot_overwrite;\n};\n\nstruct usb2_lpm_parameters {\n\tunsigned int besl;\n\tint timeout;\n};\n\nstruct usb3_lpm_parameters {\n\tunsigned int mel;\n\tunsigned int pel;\n\tunsigned int sel;\n\tint timeout;\n};\n\nstruct usb_anchor {\n\tstruct list_head urb_list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tatomic_t suspend_wakeups;\n\tunsigned int poisoned: 1;\n};\n\nstruct usb_bos_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumDeviceCaps;\n} __attribute__((packed));\n\nstruct usb_bus {\n\tstruct device *controller;\n\tstruct device *sysdev;\n\tint busnum;\n\tconst char *bus_name;\n\tu8 uses_pio_for_control;\n\tu8 otg_port;\n\tunsigned int is_b_host: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int no_stop_on_short: 1;\n\tunsigned int no_sg_constraint: 1;\n\tunsigned int sg_tablesize;\n\tint devnum_next;\n\tstruct mutex devnum_next_mutex;\n\tlong unsigned int devmap[4];\n\tstruct usb_device *root_hub;\n\tstruct usb_bus *hs_companion;\n\tint bandwidth_allocated;\n\tint bandwidth_int_reqs;\n\tint bandwidth_isoc_reqs;\n\tunsigned int resuming_ports;\n};\n\nstruct usb_cdc_acm_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n};\n\nstruct usb_cdc_call_mgmt_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n\t__u8 bDataInterface;\n};\n\nstruct usb_cdc_country_functional_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iCountryCodeRelDate;\n\tunion {\n\t\t__le16 wCountryCode0;\n\t\tstruct {\n\t\t\tstruct {} __empty_wCountryCodes;\n\t\t\t__le16 wCountryCodes[0];\n\t\t};\n\t};\n};\n\nstruct usb_cdc_dmm_desc {\n\t__u8 bFunctionLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubtype;\n\t__u16 bcdVersion;\n\t__le16 wMaxCommand;\n} __attribute__((packed));\n\nstruct usb_cdc_ether_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iMACAddress;\n\t__le32 bmEthernetStatistics;\n\t__le16 wMaxSegmentSize;\n\t__le16 wNumberMCFilters;\n\t__u8 bNumberPowerFilters;\n} __attribute__((packed));\n\nstruct usb_cdc_header_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdCDC;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMVersion;\n\t__le16 wMaxControlMessage;\n\t__u8 bNumberFilters;\n\t__u8 bMaxFilterSize;\n\t__le16 wMaxSegmentSize;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_extended_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMExtendedVersion;\n\t__u8 bMaxOutstandingCommandMessages;\n\t__le16 wMTU;\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n\t__u8 bGUID[16];\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_detail_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bGuidDescriptorType;\n\t__u8 bDetailData[0];\n};\n\nstruct usb_cdc_ncm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdNcmVersion;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_network_terminal_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bEntityId;\n\t__u8 iName;\n\t__u8 bChannelIndex;\n\t__u8 bPhysicalInterface;\n};\n\nstruct usb_cdc_obex_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n} __attribute__((packed));\n\nstruct usb_cdc_union_desc;\n\nstruct usb_cdc_parsed_header {\n\tstruct usb_cdc_union_desc *usb_cdc_union_desc;\n\tstruct usb_cdc_header_desc *usb_cdc_header_desc;\n\tstruct usb_cdc_call_mgmt_descriptor *usb_cdc_call_mgmt_descriptor;\n\tstruct usb_cdc_acm_descriptor *usb_cdc_acm_descriptor;\n\tstruct usb_cdc_country_functional_desc *usb_cdc_country_functional_desc;\n\tstruct usb_cdc_network_terminal_desc *usb_cdc_network_terminal_desc;\n\tstruct usb_cdc_ether_desc *usb_cdc_ether_desc;\n\tstruct usb_cdc_dmm_desc *usb_cdc_dmm_desc;\n\tstruct usb_cdc_mdlm_desc *usb_cdc_mdlm_desc;\n\tstruct usb_cdc_mdlm_detail_desc *usb_cdc_mdlm_detail_desc;\n\tstruct usb_cdc_obex_desc *usb_cdc_obex_desc;\n\tstruct usb_cdc_ncm_desc *usb_cdc_ncm_desc;\n\tstruct usb_cdc_mbim_desc *usb_cdc_mbim_desc;\n\tstruct usb_cdc_mbim_extended_desc *usb_cdc_mbim_extended_desc;\n\tbool phonet_magic_present;\n};\n\nstruct usb_cdc_union_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bMasterInterface0;\n\tunion {\n\t\t__u8 bSlaveInterface0;\n\t\tstruct {\n\t\t\tstruct {} __empty_bSlaveInterfaces;\n\t\t\t__u8 bSlaveInterfaces[0];\n\t\t};\n\t};\n};\n\nstruct usb_charger_current {\n\tunsigned int sdp_min;\n\tunsigned int sdp_max;\n\tunsigned int dcp_min;\n\tunsigned int dcp_max;\n\tunsigned int cdp_min;\n\tunsigned int cdp_max;\n\tunsigned int aca_min;\n\tunsigned int aca_max;\n};\n\nstruct usb_class_driver {\n\tchar *name;\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tconst struct file_operations *fops;\n\tint minor_base;\n};\n\nstruct usb_config_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumInterfaces;\n\t__u8 bConfigurationValue;\n\t__u8 iConfiguration;\n\t__u8 bmAttributes;\n\t__u8 bMaxPower;\n} __attribute__((packed));\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_dcd_config_params {\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n\t__u8 besl_baseline;\n\t__u8 besl_deep;\n};\n\nstruct usb_descriptor_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n};\n\nstruct usb_dev_cap_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_dev_state {\n\tstruct list_head list;\n\tstruct usb_device *dev;\n\tstruct file *file;\n\tspinlock_t lock;\n\tstruct list_head async_pending;\n\tstruct list_head async_completed;\n\tstruct list_head memory_list;\n\twait_queue_head_t wait;\n\twait_queue_head_t wait_for_resume;\n\tunsigned int discsignr;\n\tstruct pid *disc_pid;\n\tconst struct cred *cred;\n\tsigval_t disccontext;\n\tlong unsigned int ifclaimed;\n\tu32 disabled_bulk_eps;\n\tlong unsigned int interface_allowed_mask;\n\tint not_yet_resumed;\n\tbool suspend_allowed;\n\tbool privileges_dropped;\n};\n\nstruct usb_endpoint_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bEndpointAddress;\n\t__u8 bmAttributes;\n\t__le16 wMaxPacketSize;\n\t__u8 bInterval;\n\t__u8 bRefresh;\n\t__u8 bSynchAddress;\n} __attribute__((packed));\n\nstruct usb_ss_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bMaxBurst;\n\t__u8 bmAttributes;\n\t__le16 wBytesPerInterval;\n};\n\nstruct usb_ssp_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wReseved;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_eusb2_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wMaxPacketSize;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_host_endpoint {\n\tstruct usb_endpoint_descriptor desc;\n\tstruct usb_ss_ep_comp_descriptor ss_ep_comp;\n\tstruct usb_ssp_isoc_ep_comp_descriptor ssp_isoc_ep_comp;\n\tstruct usb_eusb2_isoc_ep_comp_descriptor eusb2_isoc_ep_comp;\n\tlong: 0;\n\tstruct list_head urb_list;\n\tvoid *hcpriv;\n\tstruct ep_device *ep_dev;\n\tunsigned char *extra;\n\tint extralen;\n\tint enabled;\n\tint streams;\n} __attribute__((packed));\n\nstruct usb_device_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__le16 idVendor;\n\t__le16 idProduct;\n\t__le16 bcdDevice;\n\t__u8 iManufacturer;\n\t__u8 iProduct;\n\t__u8 iSerialNumber;\n\t__u8 bNumConfigurations;\n};\n\nstruct usb_host_bos;\n\nstruct usb_host_config;\n\nstruct usb_device {\n\tint devnum;\n\tchar devpath[16];\n\tu32 route;\n\tenum usb_device_state state;\n\tenum usb_device_speed speed;\n\tunsigned int rx_lanes;\n\tunsigned int tx_lanes;\n\tenum usb_ssp_rate ssp_rate;\n\tstruct usb_tt *tt;\n\tint ttport;\n\tunsigned int toggle[2];\n\tstruct usb_device *parent;\n\tstruct usb_bus *bus;\n\tstruct usb_host_endpoint ep0;\n\tlong: 32;\n\tstruct device dev;\n\tstruct usb_device_descriptor descriptor;\n\tstruct usb_host_bos *bos;\n\tstruct usb_host_config *config;\n\tstruct usb_host_config *actconfig;\n\tstruct usb_host_endpoint *ep_in[16];\n\tstruct usb_host_endpoint *ep_out[16];\n\tchar **rawdescriptors;\n\tshort unsigned int bus_mA;\n\tu8 portnum;\n\tu8 level;\n\tu8 devaddr;\n\tunsigned int can_submit: 1;\n\tunsigned int persist_enabled: 1;\n\tunsigned int reset_in_progress: 1;\n\tunsigned int have_langid: 1;\n\tunsigned int authorized: 1;\n\tunsigned int authenticated: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int lpm_devinit_allow: 1;\n\tunsigned int usb2_hw_lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_besl_capable: 1;\n\tunsigned int usb2_hw_lpm_enabled: 1;\n\tunsigned int usb2_hw_lpm_allowed: 1;\n\tunsigned int usb3_lpm_u1_enabled: 1;\n\tunsigned int usb3_lpm_u2_enabled: 1;\n\tint string_langid;\n\tchar *product;\n\tchar *manufacturer;\n\tchar *serial;\n\tstruct list_head filelist;\n\tint maxchild;\n\tu32 quirks;\n\tatomic_t urbnum;\n\tlong unsigned int active_duration;\n\tlong unsigned int connect_time;\n\tunsigned int do_remote_wakeup: 1;\n\tunsigned int reset_resume: 1;\n\tunsigned int port_is_suspended: 1;\n\tunsigned int offload_at_suspend: 1;\n\tint offload_usage;\n\tenum usb_link_tunnel_mode tunnel_mode;\n\tstruct device_link *usb4_link;\n\tint slot_id;\n\tstruct usb2_lpm_parameters l1_params;\n\tstruct usb3_lpm_parameters u1_params;\n\tstruct usb3_lpm_parameters u2_params;\n\tunsigned int lpm_disable_count;\n\tu16 hub_delay;\n\tunsigned int use_generic_driver: 1;\n\tlong: 32;\n};\n\nstruct usb_device_id;\n\nstruct usb_device_driver {\n\tconst char *name;\n\tbool (*match)(struct usb_device *);\n\tint (*probe)(struct usb_device *);\n\tvoid (*disconnect)(struct usb_device *);\n\tint (*suspend)(struct usb_device *, pm_message_t);\n\tint (*resume)(struct usb_device *, pm_message_t);\n\tint (*choose_configuration)(struct usb_device *);\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tconst struct usb_device_id *id_table;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int generic_subclass: 1;\n};\n\nstruct usb_device_id {\n\t__u16 match_flags;\n\t__u16 idVendor;\n\t__u16 idProduct;\n\t__u16 bcdDevice_lo;\n\t__u16 bcdDevice_hi;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 bInterfaceNumber;\n\tkernel_ulong_t driver_info;\n};\n\nstruct usb_dynids {\n\tstruct list_head list;\n};\n\nstruct usb_interface;\n\nstruct usb_driver {\n\tconst char *name;\n\tint (*probe)(struct usb_interface *, const struct usb_device_id *);\n\tvoid (*disconnect)(struct usb_interface *);\n\tint (*unlocked_ioctl)(struct usb_interface *, unsigned int, void *);\n\tint (*suspend)(struct usb_interface *, pm_message_t);\n\tint (*resume)(struct usb_interface *);\n\tint (*reset_resume)(struct usb_interface *);\n\tint (*pre_reset)(struct usb_interface *);\n\tint (*post_reset)(struct usb_interface *);\n\tvoid (*shutdown)(struct usb_interface *);\n\tconst struct usb_device_id *id_table;\n\tconst struct attribute_group **dev_groups;\n\tstruct usb_dynids dynids;\n\tstruct device_driver driver;\n\tunsigned int no_dynamic_id: 1;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int disable_hub_initiated_lpm: 1;\n\tunsigned int soft_unbind: 1;\n};\n\nstruct usb_dynid {\n\tstruct list_head node;\n\tstruct usb_device_id id;\n};\n\nstruct usb_ep_caps {\n\tunsigned int type_control: 1;\n\tunsigned int type_iso: 1;\n\tunsigned int type_bulk: 1;\n\tunsigned int type_int: 1;\n\tunsigned int dir_in: 1;\n\tunsigned int dir_out: 1;\n};\n\nstruct usb_ep_ops;\n\nstruct usb_ep {\n\tvoid *driver_data;\n\tconst char *name;\n\tconst struct usb_ep_ops *ops;\n\tconst struct usb_endpoint_descriptor *desc;\n\tconst struct usb_ss_ep_comp_descriptor *comp_desc;\n\tstruct list_head ep_list;\n\tstruct usb_ep_caps caps;\n\tbool claimed;\n\tbool enabled;\n\tunsigned int mult: 2;\n\tunsigned int maxburst: 5;\n\tu8 address;\n\tu16 maxpacket;\n\tu16 maxpacket_limit;\n\tu16 max_streams;\n};\n\nstruct usb_request;\n\nstruct usb_ep_ops {\n\tint (*enable)(struct usb_ep *, const struct usb_endpoint_descriptor *);\n\tint (*disable)(struct usb_ep *);\n\tvoid (*dispose)(struct usb_ep *);\n\tstruct usb_request * (*alloc_request)(struct usb_ep *, gfp_t);\n\tvoid (*free_request)(struct usb_ep *, struct usb_request *);\n\tint (*queue)(struct usb_ep *, struct usb_request *, gfp_t);\n\tint (*dequeue)(struct usb_ep *, struct usb_request *);\n\tint (*set_halt)(struct usb_ep *, int);\n\tint (*set_wedge)(struct usb_ep *);\n\tint (*fifo_status)(struct usb_ep *);\n\tvoid (*fifo_flush)(struct usb_ep *);\n};\n\nstruct usb_ext_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__le32 bmAttributes;\n} __attribute__((packed));\n\nstruct usb_udc;\n\nstruct usb_gadget_ops;\n\nstruct usb_gadget {\n\tstruct work_struct work;\n\tstruct usb_udc *udc;\n\tconst struct usb_gadget_ops *ops;\n\tstruct usb_ep *ep0;\n\tstruct list_head ep_list;\n\tenum usb_device_speed speed;\n\tenum usb_device_speed max_speed;\n\tenum usb_ssp_rate ssp_rate;\n\tenum usb_ssp_rate max_ssp_rate;\n\tenum usb_device_state state;\n\tspinlock_t state_lock;\n\tbool teardown;\n\tconst char *name;\n\tlong: 32;\n\tstruct device dev;\n\tunsigned int isoch_delay;\n\tunsigned int out_epnum;\n\tunsigned int in_epnum;\n\tunsigned int mA;\n\tstruct usb_otg_caps *otg_caps;\n\tunsigned int sg_supported: 1;\n\tunsigned int is_otg: 1;\n\tunsigned int is_a_peripheral: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int a_hnp_support: 1;\n\tunsigned int a_alt_hnp_support: 1;\n\tunsigned int hnp_polling_support: 1;\n\tunsigned int host_request_flag: 1;\n\tunsigned int quirk_ep_out_aligned_size: 1;\n\tunsigned int quirk_altset_not_supp: 1;\n\tunsigned int quirk_stall_not_supp: 1;\n\tunsigned int quirk_zlp_not_supp: 1;\n\tunsigned int quirk_avoids_skb_reserve: 1;\n\tunsigned int is_selfpowered: 1;\n\tunsigned int deactivated: 1;\n\tunsigned int connected: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int wakeup_capable: 1;\n\tunsigned int wakeup_armed: 1;\n\tint irq;\n\tint id_number;\n};\n\nstruct usb_gadget_driver {\n\tchar *function;\n\tenum usb_device_speed max_speed;\n\tint (*bind)(struct usb_gadget *, struct usb_gadget_driver *);\n\tvoid (*unbind)(struct usb_gadget *);\n\tint (*setup)(struct usb_gadget *, const struct usb_ctrlrequest *);\n\tvoid (*disconnect)(struct usb_gadget *);\n\tvoid (*suspend)(struct usb_gadget *);\n\tvoid (*resume)(struct usb_gadget *);\n\tvoid (*reset)(struct usb_gadget *);\n\tstruct device_driver driver;\n\tchar *udc_name;\n\tunsigned int match_existing_only: 1;\n\tbool is_bound: 1;\n};\n\nstruct usb_gadget_ops {\n\tint (*get_frame)(struct usb_gadget *);\n\tint (*wakeup)(struct usb_gadget *);\n\tint (*func_wakeup)(struct usb_gadget *, int);\n\tint (*set_remote_wakeup)(struct usb_gadget *, int);\n\tint (*set_selfpowered)(struct usb_gadget *, int);\n\tint (*vbus_session)(struct usb_gadget *, int);\n\tint (*vbus_draw)(struct usb_gadget *, unsigned int);\n\tint (*pullup)(struct usb_gadget *, int);\n\tint (*ioctl)(struct usb_gadget *, unsigned int, long unsigned int);\n\tvoid (*get_config_params)(struct usb_gadget *, struct usb_dcd_config_params *);\n\tint (*udc_start)(struct usb_gadget *, struct usb_gadget_driver *);\n\tint (*udc_stop)(struct usb_gadget *);\n\tvoid (*udc_set_speed)(struct usb_gadget *, enum usb_device_speed);\n\tvoid (*udc_set_ssp_rate)(struct usb_gadget *, enum usb_ssp_rate);\n\tvoid (*udc_async_callbacks)(struct usb_gadget *, bool);\n\tstruct usb_ep * (*match_ep)(struct usb_gadget *, struct usb_endpoint_descriptor *, struct usb_ss_ep_comp_descriptor *);\n\tint (*check_config)(struct usb_gadget *);\n};\n\nstruct usb_phy_roothub;\n\nstruct usb_hcd {\n\tstruct usb_bus self;\n\tstruct kref kref;\n\tconst char *product_desc;\n\tint speed;\n\tchar irq_descr[24];\n\tstruct timer_list rh_timer;\n\tstruct urb *status_urb;\n\tstruct work_struct wakeup_work;\n\tstruct work_struct died_work;\n\tconst struct hc_driver *driver;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_phy_roothub *phy_roothub;\n\tlong unsigned int flags;\n\tenum usb_dev_authorize_policy dev_policy;\n\tunsigned int rh_registered: 1;\n\tunsigned int rh_pollable: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int msi_enabled: 1;\n\tunsigned int skip_phy_initialization: 1;\n\tunsigned int uses_new_polling: 1;\n\tunsigned int has_tt: 1;\n\tunsigned int amd_resume_bug: 1;\n\tunsigned int can_do_streams: 1;\n\tunsigned int tpl_support: 1;\n\tunsigned int cant_recv_wakeups: 1;\n\tunsigned int irq;\n\tvoid *regs;\n\tresource_size_t rsrc_start;\n\tresource_size_t rsrc_len;\n\tunsigned int power_budget;\n\tstruct giveback_urb_bh high_prio_bh;\n\tstruct giveback_urb_bh low_prio_bh;\n\tstruct mutex *address0_mutex;\n\tstruct mutex *bandwidth_mutex;\n\tstruct usb_hcd *shared_hcd;\n\tstruct usb_hcd *primary_hcd;\n\tstruct dma_pool *pool[4];\n\tint state;\n\tstruct gen_pool *localmem_pool;\n\tlong: 32;\n\tlong unsigned int hcd_priv[0];\n};\n\nstruct usb_ss_cap_descriptor;\n\nstruct usb_ssp_cap_descriptor;\n\nstruct usb_ss_container_id_descriptor;\n\nstruct usb_ptm_cap_descriptor;\n\nstruct usb_host_bos {\n\tstruct usb_bos_descriptor *desc;\n\tstruct usb_ext_cap_descriptor *ext_cap;\n\tstruct usb_ss_cap_descriptor *ss_cap;\n\tstruct usb_ssp_cap_descriptor *ssp_cap;\n\tstruct usb_ss_container_id_descriptor *ss_id;\n\tstruct usb_ptm_cap_descriptor *ptm_cap;\n};\n\nstruct usb_interface_assoc_descriptor;\n\nstruct usb_interface_cache;\n\nstruct usb_host_config {\n\tstruct usb_config_descriptor desc;\n\tchar *string;\n\tstruct usb_interface_assoc_descriptor *intf_assoc[16];\n\tstruct usb_interface *interface[32];\n\tstruct usb_interface_cache *intf_cache[32];\n\tunsigned char *extra;\n\tint extralen;\n};\n\nstruct usb_interface_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bInterfaceNumber;\n\t__u8 bAlternateSetting;\n\t__u8 bNumEndpoints;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 iInterface;\n};\n\nstruct usb_host_interface {\n\tstruct usb_interface_descriptor desc;\n\tint extralen;\n\tunsigned char *extra;\n\tstruct usb_host_endpoint *endpoint;\n\tchar *string;\n};\n\nstruct usb_hub_status {\n\t__le16 wHubStatus;\n\t__le16 wHubChange;\n};\n\nstruct usb_port_status {\n\t__le16 wPortStatus;\n\t__le16 wPortChange;\n\t__le32 dwExtPortStatus;\n};\n\nstruct usb_tt {\n\tstruct usb_device *hub;\n\tint multi;\n\tunsigned int think_time;\n\tvoid *hcpriv;\n\tspinlock_t lock;\n\tstruct list_head clear_list;\n\tstruct work_struct clear_work;\n};\n\nstruct usb_hub_descriptor;\n\nstruct usb_port;\n\nstruct usb_hub {\n\tstruct device *intfdev;\n\tstruct usb_device *hdev;\n\tstruct kref kref;\n\tstruct urb *urb;\n\tu8 (*buffer)[8];\n\tunion {\n\t\tstruct usb_hub_status hub;\n\t\tstruct usb_port_status port;\n\t} *status;\n\tstruct mutex status_mutex;\n\tint error;\n\tint nerrors;\n\tlong unsigned int event_bits[1];\n\tlong unsigned int change_bits[1];\n\tlong unsigned int removed_bits[1];\n\tlong unsigned int wakeup_bits[1];\n\tlong unsigned int power_bits[1];\n\tlong unsigned int child_usage_bits[1];\n\tlong unsigned int warm_reset_bits[1];\n\tstruct usb_hub_descriptor *descriptor;\n\tstruct usb_tt tt;\n\tunsigned int mA_per_port;\n\tunsigned int wakeup_enabled_descendants;\n\tunsigned int limited_power: 1;\n\tunsigned int quiescing: 1;\n\tunsigned int disconnected: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int quirk_disable_autosuspend: 1;\n\tunsigned int quirk_check_port_auto_suspend: 1;\n\tunsigned int has_indicators: 1;\n\tu8 indicator[31];\n\tstruct delayed_work leds;\n\tstruct delayed_work init_work;\n\tstruct delayed_work post_resume_work;\n\tstruct work_struct events;\n\tspinlock_t irq_urb_lock;\n\tstruct timer_list irq_urb_retry;\n\tstruct usb_port **ports;\n\tstruct list_head onboard_devs;\n};\n\nstruct usb_hub_descriptor {\n\t__u8 bDescLength;\n\t__u8 bDescriptorType;\n\t__u8 bNbrPorts;\n\t__le16 wHubCharacteristics;\n\t__u8 bPwrOn2PwrGood;\n\t__u8 bHubContrCurrent;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 DeviceRemovable[4];\n\t\t\t__u8 PortPwrCtrlMask[4];\n\t\t} hs;\n\t\tstruct {\n\t\t\t__u8 bHubHdrDecLat;\n\t\t\t__le16 wHubDelay;\n\t\t\t__le16 DeviceRemovable;\n\t\t} __attribute__((packed)) ss;\n\t} u;\n} __attribute__((packed));\n\nstruct usb_interface {\n\tstruct usb_host_interface *altsetting;\n\tstruct usb_host_interface *cur_altsetting;\n\tunsigned int num_altsetting;\n\tstruct usb_interface_assoc_descriptor *intf_assoc;\n\tint minor;\n\tenum usb_interface_condition condition;\n\tunsigned int sysfs_files_created: 1;\n\tunsigned int ep_devs_created: 1;\n\tunsigned int unregistering: 1;\n\tunsigned int needs_remote_wakeup: 1;\n\tunsigned int needs_altsetting0: 1;\n\tunsigned int needs_binding: 1;\n\tunsigned int resetting_device: 1;\n\tunsigned int authorized: 1;\n\tenum usb_wireless_status wireless_status;\n\tstruct work_struct wireless_status_work;\n\tstruct device dev;\n\tstruct device *usb_dev;\n\tstruct work_struct reset_ws;\n\tlong: 32;\n};\n\nstruct usb_interface_assoc_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bFirstInterface;\n\t__u8 bInterfaceCount;\n\t__u8 bFunctionClass;\n\t__u8 bFunctionSubClass;\n\t__u8 bFunctionProtocol;\n\t__u8 iFunction;\n};\n\nstruct usb_interface_cache {\n\tunsigned int num_altsetting;\n\tstruct kref ref;\n\tstruct usb_host_interface altsetting[0];\n};\n\nstruct usb_memory {\n\tstruct list_head memlist;\n\tint vma_use_count;\n\tint urb_use_count;\n\tu32 size;\n\tvoid *mem;\n\tdma_addr_t dma_handle;\n\tlong unsigned int vm_start;\n\tstruct usb_dev_state *ps;\n};\n\nstruct usb_ohci_pdata {\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int no_big_frame_no: 1;\n\tunsigned int num_ports;\n\tint (*power_on)(struct platform_device *);\n\tvoid (*power_off)(struct platform_device *);\n\tvoid (*power_suspend)(struct platform_device *);\n};\n\nstruct usb_otg {\n\tu8 default_a;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_bus *host;\n\tstruct usb_gadget *gadget;\n\tenum usb_otg_state state;\n\tint (*set_host)(struct usb_otg *, struct usb_bus *);\n\tint (*set_peripheral)(struct usb_otg *, struct usb_gadget *);\n\tint (*set_vbus)(struct usb_otg *, bool);\n\tint (*start_srp)(struct usb_otg *);\n\tint (*start_hnp)(struct usb_otg *);\n};\n\nstruct extcon_dev;\n\nstruct usb_phy_io_ops;\n\nstruct usb_phy {\n\tstruct device *dev;\n\tconst char *label;\n\tunsigned int flags;\n\tenum usb_phy_type type;\n\tenum usb_phy_events last_event;\n\tstruct usb_otg *otg;\n\tstruct device *io_dev;\n\tstruct usb_phy_io_ops *io_ops;\n\tvoid *io_priv;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *id_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct notifier_block type_nb;\n\tenum usb_charger_type chg_type;\n\tenum usb_charger_state chg_state;\n\tstruct usb_charger_current chg_cur;\n\tstruct work_struct chg_work;\n\tstruct atomic_notifier_head notifier;\n\tu16 port_status;\n\tu16 port_change;\n\tstruct list_head head;\n\tint (*init)(struct usb_phy *);\n\tvoid (*shutdown)(struct usb_phy *);\n\tint (*set_vbus)(struct usb_phy *, int);\n\tint (*set_power)(struct usb_phy *, unsigned int);\n\tint (*set_suspend)(struct usb_phy *, int);\n\tint (*set_wakeup)(struct usb_phy *, bool);\n\tint (*notify_connect)(struct usb_phy *, enum usb_device_speed);\n\tint (*notify_disconnect)(struct usb_phy *, enum usb_device_speed);\n\tenum usb_charger_type (*charger_detect)(struct usb_phy *);\n};\n\nstruct usb_phy_io_ops {\n\tint (*read)(struct usb_phy *, u32);\n\tint (*write)(struct usb_phy *, u32, u32);\n};\n\nstruct usb_phy_roothub {\n\tstruct phy *phy;\n\tstruct list_head list;\n};\n\nstruct usb_port {\n\tstruct usb_device *child;\n\tlong: 32;\n\tstruct device dev;\n\tstruct usb_dev_state *port_owner;\n\tstruct usb_port *peer;\n\tstruct typec_connector *connector;\n\tstruct dev_pm_qos_request *req;\n\tenum usb_port_connect_type connect_type;\n\tenum usb_device_state state;\n\tstruct kernfs_node *state_kn;\n\tusb_port_location_t location;\n\tstruct mutex status_lock;\n\tu32 over_current_count;\n\tu8 portnum;\n\tu32 quirks;\n\tunsigned int early_stop: 1;\n\tunsigned int ignore_event: 1;\n\tunsigned int is_superspeed: 1;\n\tunsigned int usb3_lpm_u1_permit: 1;\n\tunsigned int usb3_lpm_u2_permit: 1;\n};\n\nstruct usb_ptm_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_qualifier_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__u8 bNumConfigurations;\n\t__u8 bRESERVED;\n};\n\nstruct usb_request {\n\tstruct usb_ep *ep;\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tstruct scatterlist *sg;\n\tunsigned int num_sgs;\n\tunsigned int num_mapped_sgs;\n\tunsigned int stream_id: 16;\n\tunsigned int is_last: 1;\n\tunsigned int no_interrupt: 1;\n\tunsigned int zero: 1;\n\tunsigned int short_not_ok: 1;\n\tunsigned int dma_mapped: 1;\n\tunsigned int sg_was_mapped: 1;\n\tvoid (*complete)(struct usb_ep *, struct usb_request *);\n\tvoid *context;\n\tstruct list_head list;\n\tunsigned int frame_number;\n\tint status;\n\tunsigned int actual;\n};\n\ntypedef int (*usb_role_switch_set_t)(struct usb_role_switch *, enum usb_role);\n\ntypedef enum usb_role (*usb_role_switch_get_t)(struct usb_role_switch *);\n\nstruct usb_role_switch {\n\tstruct device dev;\n\tstruct lock_class_key key;\n\tstruct mutex lock;\n\tstruct module *module;\n\tenum usb_role role;\n\tbool registered;\n\tstruct device *usb2_port;\n\tstruct device *usb3_port;\n\tstruct device *udc;\n\tusb_role_switch_set_t set;\n\tusb_role_switch_get_t get;\n\tbool allow_userspace_control;\n\tlong: 32;\n};\n\nstruct usb_role_switch_desc {\n\tstruct fwnode_handle *fwnode;\n\tstruct device *usb2_port;\n\tstruct device *usb3_port;\n\tstruct device *udc;\n\tusb_role_switch_set_t set;\n\tusb_role_switch_get_t get;\n\tbool allow_userspace_control;\n\tvoid *driver_data;\n\tconst char *name;\n};\n\nstruct usb_set_sel_req {\n\t__u8 u1_sel;\n\t__u8 u1_pel;\n\t__le16 u2_sel;\n\t__le16 u2_pel;\n};\n\nstruct usb_sg_request {\n\tint status;\n\tsize_t bytes;\n\tspinlock_t lock;\n\tstruct usb_device *dev;\n\tint pipe;\n\tint entries;\n\tstruct urb **urbs;\n\tint count;\n\tstruct completion complete;\n};\n\nstruct usb_ss_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bmAttributes;\n\t__le16 wSpeedSupported;\n\t__u8 bFunctionalitySupport;\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n};\n\nstruct usb_ss_container_id_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__u8 ContainerID[16];\n};\n\nstruct usb_ssp_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__le32 bmAttributes;\n\t__le16 wFunctionalitySupport;\n\t__le16 wReserved;\n\tunion {\n\t\t__le32 legacy_padding;\n\t\tstruct {\n\t\t\tstruct {} __empty_bmSublinkSpeedAttr;\n\t\t\t__le32 bmSublinkSpeedAttr[0];\n\t\t};\n\t};\n};\n\nstruct usb_tt_clear {\n\tstruct list_head clear_list;\n\tunsigned int tt;\n\tu16 devinfo;\n\tstruct usb_hcd *hcd;\n\tstruct usb_host_endpoint *ep;\n};\n\nstruct usbdevfs_bulktransfer {\n\tunsigned int ep;\n\tunsigned int len;\n\tunsigned int timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_connectinfo {\n\tunsigned int devnum;\n\tunsigned char slow;\n};\n\nstruct usbdevfs_conninfo_ex {\n\t__u32 size;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 speed;\n\t__u8 num_ports;\n\t__u8 ports[7];\n};\n\nstruct usbdevfs_ctrltransfer {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\t__u32 timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_disconnect_claim {\n\tunsigned int interface;\n\tunsigned int flags;\n\tchar driver[256];\n};\n\nstruct usbdevfs_disconnectsignal {\n\tunsigned int signr;\n\tvoid *context;\n};\n\nstruct usbdevfs_getdriver {\n\tunsigned int interface;\n\tchar driver[256];\n};\n\nstruct usbdevfs_hub_portinfo {\n\tchar nports;\n\tchar port[127];\n};\n\nstruct usbdevfs_ioctl {\n\tint ifno;\n\tint ioctl_code;\n\tvoid *data;\n};\n\nstruct usbdevfs_iso_packet_desc {\n\tunsigned int length;\n\tunsigned int actual_length;\n\tunsigned int status;\n};\n\nstruct usbdevfs_setinterface {\n\tunsigned int interface;\n\tunsigned int altsetting;\n};\n\nstruct usbdevfs_streams {\n\tunsigned int num_streams;\n\tunsigned int num_eps;\n\tunsigned char eps[0];\n};\n\nstruct usbdevfs_urb {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tint status;\n\tunsigned int flags;\n\tvoid *buffer;\n\tint buffer_length;\n\tint actual_length;\n\tint start_frame;\n\tunion {\n\t\tint number_of_packets;\n\t\tunsigned int stream_id;\n\t};\n\tint error_count;\n\tunsigned int signr;\n\tvoid *usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbhid_device {\n\tstruct hid_device *hid;\n\tstruct usb_interface *intf;\n\tint ifnum;\n\tunsigned int bufsize;\n\tstruct urb *urbin;\n\tchar *inbuf;\n\tdma_addr_t inbuf_dma;\n\tstruct urb *urbctrl;\n\tstruct usb_ctrlrequest *cr;\n\tstruct hid_control_fifo ctrl[256];\n\tunsigned char ctrlhead;\n\tunsigned char ctrltail;\n\tchar *ctrlbuf;\n\tdma_addr_t ctrlbuf_dma;\n\tlong unsigned int last_ctrl;\n\tstruct urb *urbout;\n\tstruct hid_output_fifo out[256];\n\tunsigned char outhead;\n\tunsigned char outtail;\n\tchar *outbuf;\n\tdma_addr_t outbuf_dma;\n\tlong unsigned int last_out;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tlong unsigned int iofl;\n\tstruct timer_list io_retry;\n\tlong unsigned int stop_retry;\n\tunsigned int retry_delay;\n\tstruct work_struct reset_work;\n\twait_queue_head_t wait;\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct used_entry {\n\tu32 id;\n\tu32 len;\n};\n\nstruct user_arg_ptr {\n\tunion {\n\t\tconst char * const *native;\n\t} ptr;\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 32;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[12];\n\tlong int rlimit_max[4];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct user_pt_regs {\n\t__u64 regs[32];\n\t__u64 lo;\n\t__u64 hi;\n\t__u64 cp0_epc;\n\t__u64 cp0_badvaddr;\n\t__u64 cp0_status;\n\t__u64 cp0_cause;\n};\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tlong: 32;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n\tlong: 32;\n};\n\nstruct userfaultfd_ctx {\n\twait_queue_head_t fault_pending_wqh;\n\twait_queue_head_t fault_wqh;\n\twait_queue_head_t fd_wqh;\n\twait_queue_head_t event_wqh;\n\tseqcount_spinlock_t refile_seq;\n\trefcount_t refcount;\n\tunsigned int flags;\n\tunsigned int features;\n\tbool released;\n\tstruct rw_semaphore map_changing_lock;\n\tatomic_t mmap_changing;\n\tstruct mm_struct *mm;\n};\n\nstruct userfaultfd_fork_ctx {\n\tstruct userfaultfd_ctx *orig;\n\tstruct userfaultfd_ctx *new;\n\tstruct list_head list;\n};\n\nstruct userfaultfd_unmap_ctx {\n\tstruct userfaultfd_ctx *ctx;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct list_head list;\n};\n\nstruct userfaultfd_wait_queue {\n\tstruct uffd_msg msg;\n\twait_queue_entry_t wq;\n\tstruct userfaultfd_ctx *ctx;\n\tbool waken;\n};\n\nstruct userfaultfd_wake_range {\n\tlong unsigned int start;\n\tlong unsigned int len;\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tlong unsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct utimbuf {\n\t__kernel_old_time_t actime;\n\t__kernel_old_time_t modtime;\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct v9fs_context {\n\tstruct p9_client_opts client_opts;\n\tstruct p9_fd_opts fd_opts;\n\tstruct p9_rdma_opts rdma_opts;\n\tstruct p9_session_opts session_opts;\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[8];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcap_data {\n\tu32 entry[12];\n\tu32 mask[12];\n\tu32 action[12];\n\tu32 counter[4];\n\tu32 tg;\n\tu32 type;\n\tu32 tg_sw;\n\tu32 cnt;\n\tu32 key_offset;\n\tu32 action_offset;\n\tu32 counter_offset;\n\tu32 tg_value;\n\tu32 tg_mask;\n};\n\nstruct vcap_field {\n\tint offset;\n\tint length;\n};\n\nstruct vcap_policer_entry {\n\tstruct list_head list;\n\trefcount_t refcount;\n\tu32 pol_ix;\n};\n\nstruct vcap_props {\n\tu16 tg_width;\n\tu16 sw_count;\n\tu16 entry_count;\n\tu16 entry_words;\n\tu16 entry_width;\n\tu16 action_count;\n\tu16 action_words;\n\tu16 action_width;\n\tu16 action_type_width;\n\tstruct {\n\t\tu16 width;\n\t\tu16 count;\n\t} action_table[2];\n\tu16 counter_words;\n\tu16 counter_width;\n\tenum ocelot_target target;\n\tconst struct vcap_field *keys;\n\tconst struct vcap_field *actions;\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tbool is_firmware_default;\n\tunsigned int (*set_decode)(struct pci_dev *, bool);\n};\n\nstruct virtio_blk_outhdr {\n\t__virtio32 type;\n\t__virtio32 ioprio;\n\t__virtio64 sector;\n};\n\nstruct virtblk_req {\n\tstruct virtio_blk_outhdr out_hdr;\n\tunion {\n\t\tu8 status;\n\t\tstruct {\n\t\t\t__virtio64 sector;\n\t\t\tu8 status;\n\t\t\tlong: 32;\n\t\t} zone_append;\n\t} in_hdr;\n\tsize_t in_hdr_len;\n\tstruct sg_table sg_table;\n\tstruct scatterlist sg[0];\n};\n\nstruct virtio_9p_config {\n\t__virtio16 tag_len;\n\t__u8 tag[0];\n};\n\nstruct virtio_admin_cmd {\n\t__le16 opcode;\n\t__le16 group_type;\n\tlong: 32;\n\t__le64 group_member_id;\n\tstruct scatterlist *data_sg;\n\tstruct scatterlist *result_sg;\n\tstruct completion completion;\n\tu32 result_sg_size;\n\tint ret;\n};\n\nstruct virtio_admin_cmd_cap_get_data {\n\t__le16 id;\n\t__u8 reserved[6];\n};\n\nstruct virtio_admin_cmd_cap_set_data {\n\t__le16 id;\n\t__u8 reserved[6];\n\t__u8 cap_specific_data[0];\n};\n\nstruct virtio_admin_cmd_dev_mode_set_data {\n\t__u8 flags;\n};\n\nstruct virtio_admin_cmd_resource_obj_cmd_hdr {\n\t__le16 type;\n\t__u8 reserved[2];\n\t__le32 id;\n};\n\nstruct virtio_dev_part_hdr {\n\t__le16 part_type;\n\t__u8 flags;\n\t__u8 reserved;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 offset;\n\t\t\t__le32 reserved;\n\t\t} pci_common_cfg;\n\t\tstruct {\n\t\t\t__le16 index;\n\t\t\t__u8 reserved[6];\n\t\t} vq_index;\n\t} selector;\n\t__le32 length;\n};\n\nstruct virtio_admin_cmd_dev_parts_get_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n\tstruct virtio_dev_part_hdr hdr_list[0];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_result {\n\tunion {\n\t\tstruct {\n\t\t\t__le32 size;\n\t\t\t__le32 reserved;\n\t\t} parts_size;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t} hdr_list_count;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t\tstruct virtio_dev_part_hdr hdrs[0];\n\t\t} hdr_list;\n\t};\n};\n\nstruct virtio_admin_cmd_hdr {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__u8 reserved1[12];\n\t__le64 group_member_id;\n};\n\nstruct virtio_admin_cmd_query_cap_id_result {\n\t__le64 supported_caps[1];\n};\n\nstruct virtio_admin_cmd_resource_obj_create_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__le64 flags;\n\t__u8 resource_obj_specific_data[0];\n};\n\nstruct virtio_admin_cmd_status {\n\t__le16 status;\n\t__le16 status_qualifier;\n\t__u8 reserved2[4];\n};\n\nstruct virtio_balloon_stat {\n\t__virtio16 tag;\n\t__virtio64 val;\n} __attribute__((packed));\n\nstruct virtio_balloon {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *inflate_vq;\n\tstruct virtqueue *deflate_vq;\n\tstruct virtqueue *stats_vq;\n\tstruct virtqueue *free_page_vq;\n\tstruct workqueue_struct *balloon_wq;\n\tstruct work_struct report_free_page_work;\n\tstruct work_struct update_balloon_stats_work;\n\tstruct work_struct update_balloon_size_work;\n\tspinlock_t stop_update_lock;\n\tbool stop_update;\n\tlong unsigned int config_read_bitmap;\n\tstruct list_head free_page_list;\n\tspinlock_t free_page_list_lock;\n\tlong unsigned int num_free_page_blocks;\n\tu32 cmd_id_received_cache;\n\t__virtio32 cmd_id_active;\n\t__virtio32 cmd_id_stop;\n\twait_queue_head_t acked;\n\tunsigned int num_pages;\n\tstruct balloon_dev_info vb_dev_info;\n\tstruct mutex balloon_lock;\n\tunsigned int num_pfns;\n\t__virtio32 pfns[256];\n\tstruct virtio_balloon_stat stats[16];\n\tstruct shrinker *shrinker;\n\tstruct notifier_block oom_nb;\n\tstruct virtqueue *reporting_vq;\n\tstruct page_reporting_dev_info pr_dev_info;\n\tspinlock_t wakeup_lock;\n\tbool processing_wakeup_event;\n\tu32 wakeup_signal_mask;\n};\n\nstruct virtio_balloon_config {\n\t__le32 num_pages;\n\t__le32 actual;\n\tunion {\n\t\t__le32 free_page_hint_cmd_id;\n\t\t__le32 free_page_report_cmd_id;\n\t};\n\t__le32 poison_val;\n};\n\nstruct virtio_blk_vq;\n\nstruct virtio_blk {\n\tstruct mutex vdev_mutex;\n\tstruct virtio_device *vdev;\n\tstruct gendisk *disk;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct work_struct config_work;\n\tint index;\n\tint num_vqs;\n\tint io_queues[3];\n\tstruct virtio_blk_vq *vqs;\n\tunsigned int zone_sectors;\n};\n\nstruct virtio_blk_geometry {\n\t__virtio16 cylinders;\n\t__u8 heads;\n\t__u8 sectors;\n};\n\nstruct virtio_blk_zoned_characteristics {\n\t__virtio32 zone_sectors;\n\t__virtio32 max_open_zones;\n\t__virtio32 max_active_zones;\n\t__virtio32 max_append_sectors;\n\t__virtio32 write_granularity;\n\t__u8 model;\n\t__u8 unused2[3];\n};\n\nstruct virtio_blk_config {\n\t__virtio64 capacity;\n\t__virtio32 size_max;\n\t__virtio32 seg_max;\n\tstruct virtio_blk_geometry geometry;\n\t__virtio32 blk_size;\n\t__u8 physical_block_exp;\n\t__u8 alignment_offset;\n\t__virtio16 min_io_size;\n\t__virtio32 opt_io_size;\n\t__u8 wce;\n\t__u8 unused;\n\t__virtio16 num_queues;\n\t__virtio32 max_discard_sectors;\n\t__virtio32 max_discard_seg;\n\t__virtio32 discard_sector_alignment;\n\t__virtio32 max_write_zeroes_sectors;\n\t__virtio32 max_write_zeroes_seg;\n\t__u8 write_zeroes_may_unmap;\n\t__u8 unused1[3];\n\t__virtio32 max_secure_erase_sectors;\n\t__virtio32 max_secure_erase_seg;\n\t__virtio32 secure_erase_sector_alignment;\n\tstruct virtio_blk_zoned_characteristics zoned;\n};\n\nstruct virtio_blk_discard_write_zeroes {\n\t__le64 sector;\n\t__le32 num_sectors;\n\t__le32 flags;\n};\n\nstruct virtio_blk_vq {\n\tstruct virtqueue *vq;\n\tspinlock_t lock;\n\tchar name[16];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct virtio_chan {\n\tbool inuse;\n\tspinlock_t lock;\n\tstruct p9_client *client;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *vq;\n\tint ring_bufs_avail;\n\twait_queue_head_t *vc_wq;\n\tlong unsigned int p9_max_pages;\n\tstruct scatterlist sg[128];\n\tchar *tag;\n\tstruct list_head chan_list;\n};\n\nstruct virtqueue_info;\n\nstruct virtio_shm_region;\n\nstruct virtio_config_ops {\n\tvoid (*get)(struct virtio_device *, unsigned int, void *, unsigned int);\n\tvoid (*set)(struct virtio_device *, unsigned int, const void *, unsigned int);\n\tu32 (*generation)(struct virtio_device *);\n\tu8 (*get_status)(struct virtio_device *);\n\tvoid (*set_status)(struct virtio_device *, u8);\n\tvoid (*reset)(struct virtio_device *);\n\tint (*find_vqs)(struct virtio_device *, unsigned int, struct virtqueue **, struct virtqueue_info *, struct irq_affinity *);\n\tvoid (*del_vqs)(struct virtio_device *);\n\tvoid (*synchronize_cbs)(struct virtio_device *);\n\tu64 (*get_features)(struct virtio_device *);\n\tvoid (*get_extended_features)(struct virtio_device *, u64 *);\n\tint (*finalize_features)(struct virtio_device *);\n\tconst char * (*bus_name)(struct virtio_device *);\n\tint (*set_vq_affinity)(struct virtqueue *, const struct cpumask *);\n\tconst struct cpumask * (*get_vq_affinity)(struct virtio_device *, int);\n\tbool (*get_shm_region)(struct virtio_device *, struct virtio_shm_region *, u8);\n\tint (*disable_vq_and_reset)(struct virtqueue *);\n\tint (*enable_vq_after_reset)(struct virtqueue *);\n};\n\nstruct virtio_console_config {\n\t__virtio16 cols;\n\t__virtio16 rows;\n\t__virtio32 max_nr_ports;\n\t__virtio32 emerg_wr;\n};\n\nstruct virtio_dev_parts_cap {\n\t__u8 get_parts_resource_objects_limit;\n\t__u8 set_parts_resource_objects_limit;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct vringh_config_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_map_ops;\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tlong: 32;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_driver {\n\tstruct device_driver driver;\n\tconst struct virtio_device_id *id_table;\n\tconst unsigned int *feature_table;\n\tunsigned int feature_table_size;\n\tconst unsigned int *feature_table_legacy;\n\tunsigned int feature_table_size_legacy;\n\tint (*validate)(struct virtio_device *);\n\tint (*probe)(struct virtio_device *);\n\tvoid (*scan)(struct virtio_device *);\n\tvoid (*remove)(struct virtio_device *);\n\tvoid (*config_changed)(struct virtio_device *);\n\tint (*freeze)(struct virtio_device *);\n\tint (*restore)(struct virtio_device *);\n\tint (*reset_prepare)(struct virtio_device *);\n\tint (*reset_done)(struct virtio_device *);\n\tvoid (*shutdown)(struct virtio_device *);\n};\n\nstruct virtio_map_ops {\n\tdma_addr_t (*map_page)(union virtio_map, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid * (*alloc)(union virtio_map, size_t, dma_addr_t *, gfp_t);\n\tvoid (*free)(union virtio_map, size_t, void *, dma_addr_t, long unsigned int);\n\tbool (*need_sync)(union virtio_map, dma_addr_t);\n\tint (*mapping_error)(union virtio_map, dma_addr_t);\n\tsize_t (*max_mapping_size)(union virtio_map);\n};\n\nstruct virtio_mmio_device {\n\tstruct virtio_device vdev;\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tlong unsigned int version;\n\tlong: 32;\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1 {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\tunion {\n\t\tstruct {\n\t\t\t__virtio16 csum_start;\n\t\t\t__virtio16 csum_offset;\n\t\t};\n\t\tstruct {\n\t\t\t__virtio16 start;\n\t\t\t__virtio16 offset;\n\t\t} csum;\n\t\tstruct {\n\t\t\t__le16 segments;\n\t\t\t__le16 dup_acks;\n\t\t} rsc;\n\t};\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1_hash {\n\tstruct virtio_net_hdr_v1 hdr;\n\t__le16 hash_value_lo;\n\t__le16 hash_value_hi;\n\t__le16 hash_report;\n\t__le16 padding;\n};\n\nstruct virtio_net_hdr_v1_hash_tunnel {\n\tstruct virtio_net_hdr_v1_hash hash_hdr;\n\t__le16 outer_th_offset;\n\t__le16 inner_nh_offset;\n};\n\nstruct virtio_net_common_hdr {\n\tunion {\n\t\tstruct virtio_net_hdr hdr;\n\t\tstruct virtio_net_hdr_mrg_rxbuf mrg_hdr;\n\t\tstruct virtio_net_hdr_v1_hash hash_v1_hdr;\n\t\tstruct virtio_net_hdr_v1_hash_tunnel tnl_hdr;\n\t};\n};\n\nstruct virtio_net_config {\n\t__u8 mac[6];\n\t__virtio16 status;\n\t__virtio16 max_virtqueue_pairs;\n\t__virtio16 mtu;\n\t__le32 speed;\n\t__u8 duplex;\n\t__u8 rss_max_key_size;\n\t__le16 rss_max_indirection_table_length;\n\t__le32 supported_hash_types;\n};\n\nstruct virtio_net_ctrl_coal {\n\t__le32 max_packets;\n\t__le32 max_usecs;\n};\n\nstruct virtio_net_ctrl_coal_rx {\n\t__le32 rx_max_packets;\n\t__le32 rx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_tx {\n\t__le32 tx_max_packets;\n\t__le32 tx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_vq {\n\t__le16 vqn;\n\t__le16 reserved;\n\tstruct virtio_net_ctrl_coal coal;\n};\n\nstruct virtio_net_ctrl_mac {\n\t__virtio32 entries;\n\t__u8 macs[0];\n};\n\nstruct virtio_net_ctrl_mq {\n\t__virtio16 virtqueue_pairs;\n};\n\nstruct virtio_net_ctrl_queue_stats {\n\tstruct {\n\t\t__le16 vq_index;\n\t\t__le16 reserved[3];\n\t\t__le64 types_bitmap[1];\n\t} stats[1];\n};\n\nstruct virtio_net_rss_config_hdr {\n\t__le32 hash_types;\n\t__le16 indirection_table_mask;\n\t__le16 unclassified_queue;\n\t__le16 indirection_table[0];\n};\n\nstruct virtio_net_rss_config_trailer {\n\t__le16 max_tx_vq;\n\t__u8 hash_key_length;\n\t__u8 hash_key_data[0];\n};\n\nstruct virtio_net_stats_capabilities {\n\t__le64 supported_stats_types[1];\n};\n\nstruct virtio_net_stats_reply_hdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__le16 vq_index;\n\t__le16 reserved1;\n\t__le16 size;\n};\n\nstruct virtio_pci_vq_info;\n\nstruct virtio_pci_admin_vq {\n\tstruct virtio_pci_vq_info *info;\n\tspinlock_t lock;\n\tu64 supported_cmds;\n\tu64 supported_caps;\n\tu8 max_dev_parts_objects;\n\tstruct ida dev_parts_ida;\n\tchar name[10];\n\tu16 vq_index;\n\tlong: 32;\n};\n\nstruct virtio_pci_common_cfg {\n\t__le32 device_feature_select;\n\t__le32 device_feature;\n\t__le32 guest_feature_select;\n\t__le32 guest_feature;\n\t__le16 msix_config;\n\t__le16 num_queues;\n\t__u8 device_status;\n\t__u8 config_generation;\n\t__le16 queue_select;\n\t__le16 queue_size;\n\t__le16 queue_msix_vector;\n\t__le16 queue_enable;\n\t__le16 queue_notify_off;\n\t__le32 queue_desc_lo;\n\t__le32 queue_desc_hi;\n\t__le32 queue_avail_lo;\n\t__le32 queue_avail_hi;\n\t__le32 queue_used_lo;\n\t__le32 queue_used_hi;\n};\n\nstruct virtio_pci_legacy_device {\n\tstruct pci_dev *pci_dev;\n\tu8 *isr;\n\tvoid *ioaddr;\n\tstruct virtio_device_id id;\n};\n\nstruct virtio_pci_modern_device {\n\tstruct pci_dev *pci_dev;\n\tstruct virtio_pci_common_cfg *common;\n\tvoid *device;\n\tvoid *notify_base;\n\tresource_size_t notify_pa;\n\tu8 *isr;\n\tsize_t notify_len;\n\tsize_t device_len;\n\tsize_t common_len;\n\tint notify_map_cap;\n\tu32 notify_offset_multiplier;\n\tint modern_bars;\n\tstruct virtio_device_id id;\n\tint (*device_id_check)(struct pci_dev *);\n\tlong: 32;\n\tu64 dma_mask;\n};\n\nstruct virtio_pci_device {\n\tstruct virtio_device vdev;\n\tstruct pci_dev *pci_dev;\n\tlong: 32;\n\tunion {\n\t\tstruct virtio_pci_legacy_device ldev;\n\t\tstruct virtio_pci_modern_device mdev;\n\t};\n\tbool is_legacy;\n\tu8 *isr;\n\tspinlock_t lock;\n\tstruct list_head virtqueues;\n\tstruct list_head slow_virtqueues;\n\tstruct virtio_pci_vq_info **vqs;\n\tstruct virtio_pci_admin_vq admin_vq;\n\tint msix_enabled;\n\tint intx_enabled;\n\tcpumask_var_t *msix_affinity_masks;\n\tchar (*msix_names)[256];\n\tunsigned int msix_vectors;\n\tunsigned int msix_used_vectors;\n\tbool per_vq_vectors;\n\tstruct virtqueue * (*setup_vq)(struct virtio_pci_device *, struct virtio_pci_vq_info *, unsigned int, void (*)(struct virtqueue *), const char *, bool, u16);\n\tvoid (*del_vq)(struct virtio_pci_vq_info *);\n\tu16 (*config_vector)(struct virtio_pci_device *, u16);\n\tint (*avq_index)(struct virtio_device *, u16 *, u16 *);\n\tlong: 32;\n};\n\nstruct virtio_pci_modern_common_cfg {\n\tstruct virtio_pci_common_cfg cfg;\n\t__le16 queue_notify_data;\n\t__le16 queue_reset;\n\t__le16 admin_queue_index;\n\t__le16 admin_queue_num;\n};\n\nstruct virtio_pci_vq_info {\n\tstruct virtqueue *vq;\n\tstruct list_head node;\n\tunsigned int msix_vector;\n};\n\nstruct virtio_resource_obj_dev_parts {\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_shm_region {\n\tu64 addr;\n\tu64 len;\n};\n\nstruct virtnet_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *cvq;\n\tstruct net_device *dev;\n\tstruct send_queue *sq;\n\tstruct receive_queue *rq;\n\tunsigned int status;\n\tu16 max_queue_pairs;\n\tu16 curr_queue_pairs;\n\tu16 xdp_queue_pairs;\n\tbool xdp_enabled;\n\tbool big_packets;\n\tunsigned int big_packets_num_skbfrags;\n\tbool mergeable_rx_bufs;\n\tbool has_rss;\n\tbool has_rss_hash_report;\n\tu8 rss_key_size;\n\tu16 rss_indir_table_size;\n\tu32 rss_hash_types_supported;\n\tu32 rss_hash_types_saved;\n\tbool has_cvq;\n\tstruct mutex cvq_lock;\n\tbool any_header_sg;\n\tu8 hdr_len;\n\tbool tx_tnl;\n\tbool rx_tnl;\n\tbool rx_tnl_csum;\n\tstruct work_struct config_work;\n\tstruct work_struct rx_mode_work;\n\tbool rx_mode_work_enabled;\n\tbool affinity_hint_set;\n\tstruct hlist_node node;\n\tstruct hlist_node node_dead;\n\tstruct control_buf *ctrl;\n\tu8 duplex;\n\tu32 speed;\n\tbool rx_dim_enabled;\n\tstruct virtnet_interrupt_coalesce intr_coal_tx;\n\tstruct virtnet_interrupt_coalesce intr_coal_rx;\n\tlong unsigned int guest_offloads;\n\tlong unsigned int guest_offloads_capable;\n\tstruct failover *failover;\n\tu64 device_stats_cap;\n\tstruct virtio_net_rss_config_hdr *rss_hdr;\n\tunion {\n\t\tstruct virtio_net_rss_config_trailer rss_trailer;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[3];\n\t\t\tu8 rss_hash_key_data[40];\n\t\t};\n\t};\n};\n\nstruct virtnet_rq_dma {\n\tdma_addr_t addr;\n\tu32 ref;\n\tu16 len;\n\tu16 need_sync;\n};\n\nstruct virtnet_sq_free_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 napi_packets;\n\tu64 napi_bytes;\n\tu64 xsk;\n};\n\nstruct virtnet_stat_desc {\n\tchar desc[32];\n\tsize_t offset;\n\tsize_t qstat_offset;\n};\n\nstruct virtnet_stats_ctx {\n\tbool to_qstat;\n\tu32 desc_num[3];\n\tu64 bitmap[3];\n\tu32 size[3];\n\tu64 *data;\n};\n\nstruct virtqueue {\n\tstruct list_head list;\n\tvoid (*callback)(struct virtqueue *);\n\tconst char *name;\n\tstruct virtio_device *vdev;\n\tunsigned int index;\n\tunsigned int num_free;\n\tunsigned int num_max;\n\tbool reset;\n\tvoid *priv;\n};\n\ntypedef void vq_callback_t(struct virtqueue *);\n\nstruct virtqueue_info {\n\tconst char *name;\n\tvq_callback_t *callback;\n\tbool ctx;\n};\n\nstruct vring_virtqueue;\n\nstruct virtqueue_ops {\n\tint (*add)(struct vring_virtqueue *, struct scatterlist **, unsigned int, unsigned int, unsigned int, void *, void *, bool, gfp_t, long unsigned int);\n\tvoid * (*get)(struct vring_virtqueue *, unsigned int *, void **);\n\tbool (*kick_prepare)(struct vring_virtqueue *);\n\tvoid (*disable_cb)(struct vring_virtqueue *);\n\tbool (*enable_cb_delayed)(struct vring_virtqueue *);\n\tunsigned int (*enable_cb_prepare)(struct vring_virtqueue *);\n\tbool (*poll)(const struct vring_virtqueue *, unsigned int);\n\tvoid * (*detach_unused_buf)(struct vring_virtqueue *);\n\tbool (*more_used)(const struct vring_virtqueue *);\n\tint (*resize)(struct vring_virtqueue *, u32);\n\tvoid (*reset)(struct vring_virtqueue *);\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {\n\tstruct userfaultfd_ctx *ctx;\n};\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[73];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n};\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[4];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmpressure_event {\n\tstruct eventfd_ctx *efd;\n\tenum vmpressure_levels level;\n\tenum vmpressure_modes mode;\n\tstruct list_head node;\n};\n\nstruct vpe_boot_config {\n\tlong unsigned int pc;\n\tlong unsigned int sp;\n\tlong unsigned int gp;\n};\n\nstruct vring_desc;\n\ntypedef struct vring_desc vring_desc_t;\n\nstruct vring_avail;\n\ntypedef struct vring_avail vring_avail_t;\n\nstruct vring_used;\n\ntypedef struct vring_used vring_used_t;\n\nstruct vring {\n\tunsigned int num;\n\tvring_desc_t *desc;\n\tvring_avail_t *avail;\n\tvring_used_t *used;\n};\n\nstruct vring_avail {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\t__virtio16 ring[0];\n};\n\nstruct vring_desc {\n\t__virtio64 addr;\n\t__virtio32 len;\n\t__virtio16 flags;\n\t__virtio16 next;\n};\n\nstruct vring_desc_extra {\n\tdma_addr_t addr;\n\tu32 len;\n\tu16 flags;\n\tu16 next;\n};\n\nstruct vring_packed_desc;\n\nstruct vring_desc_state_packed {\n\tvoid *data;\n\tstruct vring_packed_desc *indir_desc;\n\tu16 num;\n\tu16 last;\n\tu32 total_in_len;\n};\n\nstruct vring_desc_state_split {\n\tvoid *data;\n\tstruct vring_desc *indir_desc;\n\tu32 total_in_len;\n};\n\nstruct vring_packed_desc {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 id;\n\t__le16 flags;\n};\n\nstruct vring_packed_desc_event {\n\t__le16 off_wrap;\n\t__le16 flags;\n};\n\nstruct vring_used_elem {\n\t__virtio32 id;\n\t__virtio32 len;\n};\n\ntypedef struct vring_used_elem vring_used_elem_t;\n\nstruct vring_used {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\tvring_used_elem_t ring[0];\n};\n\nstruct vring_virtqueue_split {\n\tstruct vring vring;\n\tu16 avail_flags_shadow;\n\tu16 avail_idx_shadow;\n\tstruct vring_desc_state_split *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t queue_dma_addr;\n\tsize_t queue_size_in_bytes;\n\tu32 vring_align;\n\tbool may_reduce_num;\n};\n\nstruct vring_virtqueue_packed {\n\tstruct {\n\t\tunsigned int num;\n\t\tstruct vring_packed_desc *desc;\n\t\tstruct vring_packed_desc_event *driver;\n\t\tstruct vring_packed_desc_event *device;\n\t} vring;\n\tbool avail_wrap_counter;\n\tu16 avail_used_flags;\n\tu16 next_avail_idx;\n\tu16 event_flags_shadow;\n\tstruct vring_desc_state_packed *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t ring_dma_addr;\n\tdma_addr_t driver_event_dma_addr;\n\tdma_addr_t device_event_dma_addr;\n\tsize_t ring_size_in_bytes;\n\tsize_t event_size_in_bytes;\n};\n\nstruct vring_virtqueue {\n\tstruct virtqueue vq;\n\tbool use_map_api;\n\tbool weak_barriers;\n\tbool broken;\n\tbool indirect;\n\tbool event;\n\tenum vq_layout layout;\n\tunsigned int free_head;\n\tstruct used_entry batch_last;\n\tunsigned int num_added;\n\tu16 last_used_idx;\n\tu16 last_used;\n\tbool event_triggered;\n\tunion {\n\t\tstruct vring_virtqueue_split split;\n\t\tstruct vring_virtqueue_packed packed;\n\t};\n\tbool (*notify)(struct virtqueue *);\n\tbool we_own_ring;\n\tunion virtio_map map;\n};\n\nstruct vsc8531_edge_rate_table {\n\tu32 vddmac;\n\tu32 slowdown[8];\n};\n\nstruct vsc85xx_ptp;\n\nstruct vsc85xx_hw_stat;\n\nstruct vsc8531_private {\n\tint rate_magic;\n\tu16 supp_led_modes;\n\tu32 leds_mode[4];\n\tu8 nleds;\n\tconst struct vsc85xx_hw_stat *hw_stats;\n\tu64 *stats;\n\tint nstats;\n\tu8 addr;\n\tunsigned int base_addr;\n\tstruct mii_timestamper mii_ts;\n\tbool input_clk_init;\n\tstruct vsc85xx_ptp *ptp;\n\tstruct gpio_desc *load_save;\n\tunsigned int ts_base_addr;\n\tu8 ts_base_phy;\n\tstruct mutex ts_lock;\n\tstruct mutex phc_lock;\n\tstruct sk_buff_head rx_skbs_list;\n};\n\nstruct vsc85xx_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu16 page;\n\tu16 mask;\n};\n\nstruct vsc85xx_probe_config {\n\tconst struct vsc85xx_hw_stat *hw_stats;\n\tsize_t shared_size;\n\tsize_t nstats;\n\tu16 supp_led_modes;\n\tu8 nleds;\n\tbool check_rate_magic;\n\tbool use_package;\n\tbool has_ptp;\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vtunnel_info {\n\tu32 tunid;\n\tu16 vid;\n\tu16 flags;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n\tlong: 32;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int one_bits;\n\tconst long unsigned int high_bits;\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct work_registers {\n\tint r1;\n\tint r2;\n\tint r3;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tlong: 32;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n\tlong: 32;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tlong: 32;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct wrapper_priv_data {\n\tstruct dwc2_hsotg *hsotg;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n\tstruct bdi_writeback *wb;\n\tstruct inode *inode;\n\tint wb_id;\n\tint wb_lcand_id;\n\tint wb_tcand_id;\n\tsize_t wb_bytes;\n\tsize_t wb_lcand_bytes;\n\tsize_t wb_tcand_bytes;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[6];\n\t\tlong unsigned int marks[6];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xb1s_ff_report {\n\t__u8 report_id;\n\t__u8 enable;\n\t__u8 magnitude[4];\n\t__u8 duration_10ms;\n\t__u8 start_delay_10ms;\n\t__u8 loop_count;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n\tlong: 32;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tlong: 32;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n\tlong: 32;\n};\n\nstruct xdr_skb_reader {\n\tstruct sk_buff *skb;\n\tunsigned int offset;\n\tbool need_checksum;\n\tsize_t count;\n\t__wsum csum;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tlong: 32;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tlong: 32;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\tlong: 32;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_tunnel {\n\tint (*handler)(struct sk_buff *);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm_tunnel *next;\n\tint priority;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xgpio_instance {\n\tstruct gpio_chip gc;\n\tvoid *regs;\n\tlong unsigned int map[2];\n\tlong unsigned int state[2];\n\tlong unsigned int last_irq_read[2];\n\tlong unsigned int dir[2];\n\traw_spinlock_t gpio_lock;\n\tint irq;\n\tlong unsigned int enable[2];\n\tlong unsigned int rising_edge[2];\n\tlong unsigned int falling_edge[2];\n\tstruct clk *clk;\n};\n\nstruct xhci_bus_state {\n\tlong unsigned int bus_suspended;\n\tlong unsigned int next_statechange;\n\tu32 port_c_suspend;\n\tu32 suspended_ports;\n\tu32 port_remote_wakeup;\n\tlong unsigned int resuming_ports;\n};\n\nstruct xhci_bw_info {\n\tunsigned int ep_interval;\n\tunsigned int mult;\n\tunsigned int num_packets;\n\tunsigned int max_packet_size;\n\tunsigned int max_esit_payload;\n\tunsigned int type;\n};\n\nstruct xhci_cap_regs {\n\t__le32 hc_capbase;\n\t__le32 hcs_params1;\n\t__le32 hcs_params2;\n\t__le32 hcs_params3;\n\t__le32 hcc_params;\n\t__le32 db_off;\n\t__le32 run_regs_off;\n\t__le32 hcc_params2;\n};\n\nstruct xhci_container_ctx;\n\nstruct xhci_command {\n\tstruct xhci_container_ctx *in_ctx;\n\tu32 status;\n\tu32 comp_param;\n\tint slot_id;\n\tstruct completion *completion;\n\tunion xhci_trb *command_trb;\n\tstruct list_head cmd_list;\n\tunsigned int timeout_ms;\n};\n\nstruct xhci_container_ctx {\n\tunsigned int type;\n\tint size;\n\tu8 *bytes;\n\tdma_addr_t dma;\n};\n\nstruct xhci_device_context_array {\n\t__le64 dev_context_ptrs[256];\n\tdma_addr_t dma;\n\tlong: 32;\n};\n\nstruct xhci_doorbell_array {\n\t__le32 doorbell[256];\n};\n\nstruct xhci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n};\n\nstruct xhci_ep_ctx {\n\t__le32 ep_info;\n\t__le32 ep_info2;\n\t__le64 deq;\n\t__le32 tx_info;\n\t__le32 reserved[3];\n};\n\nstruct xhci_stream_info;\n\nstruct xhci_ring;\n\nstruct xhci_ep_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *show_ring;\n\tunsigned int stream_id;\n};\n\nstruct xhci_erst_entry;\n\nstruct xhci_erst {\n\tstruct xhci_erst_entry *entries;\n\tunsigned int num_entries;\n\tdma_addr_t erst_dma_addr;\n};\n\nstruct xhci_erst_entry {\n\t__le64 seg_addr;\n\t__le32 seg_size;\n\t__le32 rsvd;\n};\n\nstruct xhci_event_cmd {\n\t__le64 cmd_trb;\n\t__le32 status;\n\t__le32 flags;\n};\n\nstruct xhci_file_map {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct xhci_generic_trb {\n\t__le32 field[4];\n};\n\nstruct xhci_port;\n\nstruct xhci_hub {\n\tstruct xhci_port **ports;\n\tunsigned int num_ports;\n\tstruct usb_hcd *hcd;\n\tstruct xhci_bus_state bus_state;\n\tu8 maj_rev;\n\tu8 min_rev;\n};\n\nstruct xhci_op_regs;\n\nstruct xhci_run_regs;\n\nstruct xhci_interrupter;\n\nstruct xhci_scratchpad;\n\nstruct xhci_virt_device;\n\nstruct xhci_root_port_bw_info;\n\nstruct xhci_port_cap;\n\nstruct xhci_hcd {\n\tstruct usb_hcd *main_hcd;\n\tstruct usb_hcd *shared_hcd;\n\tstruct xhci_cap_regs *cap_regs;\n\tstruct xhci_op_regs *op_regs;\n\tstruct xhci_run_regs *run_regs;\n\tstruct xhci_doorbell_array *dba;\n\t__u32 hcs_params2;\n\t__u32 hcs_params3;\n\t__u32 hcc_params;\n\t__u32 hcc_params2;\n\tspinlock_t lock;\n\tu16 hci_version;\n\tu16 max_interrupters;\n\tu8 max_slots;\n\tu8 max_ports;\n\tu32 imod_interval;\n\tu32 page_size;\n\tint nvecs;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\tstruct reset_control *reset;\n\tstruct xhci_device_context_array *dcbaa;\n\tstruct xhci_interrupter **interrupters;\n\tstruct xhci_ring *cmd_ring;\n\tunsigned int cmd_ring_state;\n\tstruct list_head cmd_list;\n\tunsigned int cmd_ring_reserved_trbs;\n\tstruct delayed_work cmd_timer;\n\tstruct completion cmd_ring_stop_completion;\n\tstruct xhci_command *current_cmd;\n\tstruct xhci_scratchpad *scratchpad;\n\tstruct mutex mutex;\n\tstruct xhci_virt_device *devs[256];\n\tstruct xhci_root_port_bw_info *rh_bw;\n\tstruct dma_pool *device_pool;\n\tstruct dma_pool *segment_pool;\n\tstruct dma_pool *small_streams_pool;\n\tstruct dma_pool *port_bw_pool;\n\tstruct dma_pool *medium_streams_pool;\n\tunsigned int xhc_state;\n\tlong unsigned int run_graceperiod;\n\tlong: 32;\n\tstruct s3_save s3;\n\tlong long unsigned int quirks;\n\tunsigned int num_active_eps;\n\tunsigned int limit_active_eps;\n\tstruct xhci_port *hw_ports;\n\tstruct xhci_hub usb2_rhub;\n\tstruct xhci_hub usb3_rhub;\n\tunsigned int hw_lpm_support: 1;\n\tunsigned int broken_suspend: 1;\n\tunsigned int allow_single_roothub: 1;\n\tstruct xhci_port_cap *port_caps;\n\tunsigned int num_port_caps;\n\tstruct timer_list comp_mode_recovery_timer;\n\tu32 port_status_u0;\n\tu16 test_mode;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_slots;\n\tstruct list_head regset_list;\n\tvoid *dbc;\n\tlong unsigned int priv[0];\n};\n\nstruct xhci_input_control_ctx {\n\t__le32 drop_flags;\n\t__le32 add_flags;\n\t__le32 rsvd2[6];\n};\n\nstruct xhci_intr_reg;\n\nstruct xhci_interrupter {\n\tstruct xhci_ring *event_ring;\n\tstruct xhci_erst erst;\n\tstruct xhci_intr_reg *ir_set;\n\tunsigned int intr_num;\n\tbool ip_autoclear;\n\tu32 isoc_bei_interval;\n\tu32 s3_iman;\n\tu32 s3_imod;\n\tu32 s3_erst_size;\n\tlong: 32;\n\tu64 s3_erst_base;\n\tu64 s3_erst_dequeue;\n};\n\nstruct xhci_interval_bw {\n\tunsigned int num_packets;\n\tstruct list_head endpoints;\n\tunsigned int overhead[3];\n};\n\nstruct xhci_interval_bw_table {\n\tunsigned int interval0_esit_payload;\n\tstruct xhci_interval_bw interval_bw[16];\n\tunsigned int bw_used;\n\tunsigned int ss_bw_in;\n\tunsigned int ss_bw_out;\n};\n\nstruct xhci_intr_reg {\n\t__le32 iman;\n\t__le32 imod;\n\t__le32 erst_size;\n\t__le32 rsvd;\n\t__le64 erst_base;\n\t__le64 erst_dequeue;\n};\n\nstruct xhci_link_trb {\n\t__le64 segment_ptr;\n\t__le32 intr_target;\n\t__le32 control;\n};\n\nstruct xhci_port_regs {\n\t__le32 portsc;\n\t__le32 portpmsc;\n\t__le32 portli;\n\t__le32 porthlmpc;\n};\n\nstruct xhci_op_regs {\n\t__le32 command;\n\t__le32 status;\n\t__le32 page_size;\n\t__le32 reserved1;\n\t__le32 reserved2;\n\t__le32 dev_notification;\n\t__le64 cmd_ring;\n\t__le32 reserved3[4];\n\t__le64 dcbaa_ptr;\n\t__le32 config_reg;\n\t__le32 reserved4[241];\n\tstruct xhci_port_regs port_regs[0];\n};\n\nstruct xhci_port {\n\tstruct xhci_port_regs *port_reg;\n\tint hw_portnum;\n\tint hcd_portnum;\n\tstruct xhci_hub *rhub;\n\tstruct xhci_port_cap *port_cap;\n\tunsigned int lpm_incapable: 1;\n\tlong unsigned int resume_timestamp;\n\tbool rexit_active;\n\tint slot_id;\n\tstruct completion rexit_done;\n\tstruct completion u3exit_done;\n};\n\nstruct xhci_port_cap {\n\tu32 *psi;\n\tu8 psi_count;\n\tu8 psi_uid_count;\n\tu8 maj_rev;\n\tu8 min_rev;\n\tu32 protocol_caps;\n};\n\nstruct xhci_regset {\n\tchar name[32];\n\tstruct debugfs_regset32 regset;\n\tsize_t nregs;\n\tstruct list_head list;\n};\n\nstruct xhci_ring {\n\tstruct xhci_segment *first_seg;\n\tstruct xhci_segment *last_seg;\n\tunion xhci_trb *enqueue;\n\tstruct xhci_segment *enq_seg;\n\tunion xhci_trb *dequeue;\n\tstruct xhci_segment *deq_seg;\n\tstruct list_head td_list;\n\tu32 cycle_state;\n\tunsigned int stream_id;\n\tunsigned int num_segs;\n\tunsigned int num_trbs_free;\n\tunsigned int bounce_buf_len;\n\tenum xhci_ring_type type;\n\tu32 old_trb_comp_code;\n\tstruct xarray *trb_address_map;\n};\n\nstruct xhci_root_port_bw_info {\n\tstruct list_head tts;\n\tunsigned int num_active_tts;\n\tstruct xhci_interval_bw_table bw_table;\n};\n\nstruct xhci_run_regs {\n\t__le32 microframe_index;\n\t__le32 rsvd[7];\n\tstruct xhci_intr_reg ir_set[1024];\n};\n\nstruct xhci_scratchpad {\n\tu64 *sp_array;\n\tdma_addr_t sp_dma;\n\tvoid **sp_buffers;\n};\n\nstruct xhci_segment {\n\tunion xhci_trb *trbs;\n\tstruct xhci_segment *next;\n\tunsigned int num;\n\tdma_addr_t dma;\n\tdma_addr_t bounce_dma;\n\tvoid *bounce_buf;\n\tunsigned int bounce_offs;\n\tunsigned int bounce_len;\n};\n\nstruct xhci_virt_ep;\n\nstruct xhci_sideband_event;\n\nstruct xhci_sideband {\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_virt_device *vdev;\n\tstruct xhci_virt_ep *eps[31];\n\tstruct xhci_interrupter *ir;\n\tenum xhci_sideband_type type;\n\tstruct mutex mutex;\n\tstruct usb_interface *intf;\n\tint (*notify_client)(struct usb_interface *, struct xhci_sideband_event *);\n};\n\nstruct xhci_sideband_event {\n\tenum xhci_sideband_notify_type type;\n\tvoid *evt_data;\n};\n\nstruct xhci_slot_ctx {\n\t__le32 dev_info;\n\t__le32 dev_info2;\n\t__le32 tt_info;\n\t__le32 dev_state;\n\t__le32 reserved[4];\n};\n\nstruct xhci_slot_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_ep_priv *eps[31];\n\tstruct xhci_virt_device *dev;\n};\n\nstruct xhci_stream_ctx {\n\t__le64 stream_ring;\n\t__le32 reserved[2];\n};\n\nstruct xhci_stream_info {\n\tstruct xhci_ring **stream_rings;\n\tunsigned int num_streams;\n\tstruct xhci_stream_ctx *stream_ctx_array;\n\tunsigned int num_stream_ctxs;\n\tdma_addr_t ctx_array_dma;\n\tstruct xarray trb_address_map;\n\tstruct xhci_command *free_streams_command;\n};\n\nstruct xhci_transfer_event {\n\t__le64 buffer;\n\t__le32 transfer_len;\n\t__le32 flags;\n};\n\nunion xhci_trb {\n\tstruct xhci_link_trb link;\n\tstruct xhci_transfer_event trans_event;\n\tstruct xhci_event_cmd event_cmd;\n\tstruct xhci_generic_trb generic;\n};\n\nstruct xhci_tt_bw_info {\n\tstruct list_head tt_list;\n\tint slot_id;\n\tint ttport;\n\tstruct xhci_interval_bw_table bw_table;\n\tint active_eps;\n};\n\nstruct xhci_virt_ep {\n\tstruct xhci_virt_device *vdev;\n\tunsigned int ep_index;\n\tstruct xhci_ring *ring;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *new_ring;\n\tunsigned int err_count;\n\tunsigned int ep_state;\n\tstruct list_head cancelled_td_list;\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_segment *queued_deq_seg;\n\tunion xhci_trb *queued_deq_ptr;\n\tbool skip;\n\tstruct xhci_bw_info bw_info;\n\tstruct list_head bw_endpoint_list;\n\tlong unsigned int stop_time;\n\tint next_frame_id;\n\tbool use_extended_tbc;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xhci_virt_device {\n\tint slot_id;\n\tstruct usb_device *udev;\n\tstruct xhci_container_ctx *out_ctx;\n\tstruct xhci_container_ctx *in_ctx;\n\tstruct xhci_virt_ep eps[31];\n\tstruct xhci_port *rhub_port;\n\tstruct xhci_interval_bw_table *bw_table;\n\tstruct xhci_tt_bw_info *tt_info;\n\tlong unsigned int flags;\n\tu16 current_mel;\n\tvoid *debugfs_private;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xiic_i2c {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct completion completion;\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *tx_msg;\n\tstruct mutex lock;\n\tunsigned int tx_pos;\n\tunsigned int nmsgs;\n\tstruct i2c_msg *rx_msg;\n\tint rx_pos;\n\tenum xiic_endian endianness;\n\tstruct clk *clk;\n\tenum xilinx_i2c_state state;\n\tbool singlemaster;\n\tbool dynamic;\n\tbool prev_msg_tx;\n\tu32 quirks;\n\tbool smbus_block_read;\n\tlong unsigned int input_clk;\n\tunsigned int i2c_clk;\n\tbool atomic;\n\tspinlock_t atomic_lock;\n\tenum xilinx_i2c_state atomic_xfer_state;\n};\n\nstruct xiic_i2c_platform_data {\n\tu8 num_devices;\n\tconst struct i2c_board_info *devices;\n};\n\nstruct xiic_version_data {\n\tu32 quirks;\n};\n\nstruct xilinx_pcie {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tlong unsigned int msi_map[4];\n\tstruct mutex map_lock;\n\tstruct irq_domain *msi_domain;\n\tstruct irq_domain *leg_domain;\n\tstruct list_head resources;\n};\n\nstruct xprt_addr {\n\tconst char *addr;\n\tstruct callback_head rcu;\n};\n\nstruct xprt_create;\n\nstruct xprt_class {\n\tstruct list_head list;\n\tint ident;\n\tstruct rpc_xprt * (*setup)(struct xprt_create *);\n\tstruct module *owner;\n\tchar name[32];\n\tconst char *netid[0];\n};\n\nstruct xprt_create {\n\tint ident;\n\tstruct net *net;\n\tstruct sockaddr *srcaddr;\n\tstruct sockaddr *dstaddr;\n\tsize_t addrlen;\n\tconst char *servername;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rpc_xprt_switch *bc_xps;\n\tunsigned int flags;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tlong: 32;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xsk_tx_metadata {\n\t__u64 flags;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 csum_start;\n\t\t\t__u16 csum_offset;\n\t\t\tlong: 32;\n\t\t\t__u64 launch_time;\n\t\t} request;\n\t\tstruct {\n\t\t\t__u64 tx_timestamp;\n\t\t} completion;\n\t};\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xts_instance_ctx {\n\tstruct crypto_skcipher_spawn spawn;\n\tstruct crypto_cipher_spawn tweak_spawn;\n};\n\nstruct xts_request_ctx {\n\tle128 t;\n\tstruct scatterlist *tail;\n\tstruct scatterlist sg[2];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct skcipher_request subreq;\n};\n\nstruct xts_tfm_ctx {\n\tstruct crypto_skcipher *child;\n\tstruct crypto_cipher *tweak;\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n\tlong: 32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t\tlong: 32;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tlong: 32;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n\tlong: 32;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct yamon_mem_region {\n\tphys_addr_t start;\n\tphys_addr_t size;\n\tphys_addr_t discard;\n};\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\ntypedef struct mtd_info *cfi_cmdset_fn_t(struct map_info *, int);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef void (*companion_fn)(struct pci_dev *, struct usb_hcd *, struct pci_dev *, struct usb_hcd *);\n\ntypedef long unsigned int (*count_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef unsigned int (*cps_nc_entry_fn)(unsigned int, u32 *);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int devlink_chunk_fill_t(void *, u8 *, u32, u64, struct netlink_ext_ack *);\n\ntypedef int devlink_nl_dump_one_func_t(struct sk_buff *, struct devlink *, struct netlink_callback *, int);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\ntypedef void ext4_update_sb_callback(struct ext4_sb_info *, struct ext4_super_block *, const void *);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef bool (*hid_usage_cmp_t)(struct hid_usage *, unsigned int, unsigned int);\n\ntypedef u32 inet6_ehashfn_t(const struct net *, const struct in6_addr *, const u16, const struct in6_addr *, const __be16);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef int (*initcall_t)(void);\n\ntypedef initcall_t initcall_entry_t;\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *, const struct inet6_skb_parm *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*nlm_host_match_fn_t)(void *, struct nlm_host *);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef struct gpio_desc * (*of_find_gpio_quirk)(struct device_node *, const char *, unsigned int, enum of_gpio_flags *);\n\ntypedef void (*of_init_fn_1)(struct device_node *);\n\ntypedef int (*of_init_fn_1_ret)(struct device_node *);\n\ntypedef int (*of_init_fn_2)(struct device_node *, struct device_node *);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef int (*platform_irq_probe_t)(struct platform_device *, struct device_node *);\n\ntypedef int (*pm_callback_t)(struct device *);\n\ntypedef struct rt6_info * (*pol_lookup_t)(struct net *, struct fib6_table *, struct flowi6 *, const struct sk_buff *, int);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\ntypedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\ntypedef int (*reservedmem_of_init_fn)(struct reserved_mem *);\n\ntypedef void (*rpc_action)(struct rpc_task *);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef long unsigned int (*scan_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef void (*set_params_cb)(struct dwc2_hsotg *);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*varsize_frob_t)(struct map_info *, struct flchip *, long unsigned int, int, void *);\n\ntypedef void (*vi_handler_t)(void);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);\n\ntypedef struct rpc_xprt * (*xprt_switch_find_xprt_t)(struct rpc_xprt_switch *, const struct rpc_xprt *);\n\nstruct nf_bridge_frag_data;\n\nstruct acpi_device;\n\nstruct audit_buffer;\n\nstruct audit_context;\n\nstruct bpf_iter;\n\nstruct hugepage_subpool;\n\nstruct io_tlb_pool;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern struct cgroup *bpf_cgroup_from_id(u64 cgid) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_dynptr_adjust(const struct bpf_dynptr *p, u64 start, u64 end) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_copy(struct bpf_dynptr *dst_ptr, u64 dst_off, struct bpf_dynptr *src_ptr, u64 src_off, u64 size) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb(struct __sk_buff *s, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb_meta(struct __sk_buff *skb_, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_xdp(struct xdp_md *x, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_dynptr_memset(struct bpf_dynptr *p, u64 offset, u64 size, u8 val) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern void *bpf_dynptr_slice(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern void *bpf_dynptr_slice_rdwr(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern struct kmem_cache *bpf_get_kmem_cache(u64 addr) __weak __ksym;\nextern struct mem_cgroup *bpf_get_mem_cgroup(struct cgroup_subsys_state *css) __weak __ksym;\nextern struct mem_cgroup *bpf_get_root_mem_cgroup(void) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern int bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it, struct task_struct *task, u64 addr) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern struct bpf_key *bpf_lookup_system_key(u64 id) __weak __ksym;\nextern struct bpf_key *bpf_lookup_user_key(s32 serial, u64 flags) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern void bpf_mem_cgroup_flush_stats(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_memory_events(struct mem_cgroup *memcg, enum memcg_memory_event event) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_page_state(struct mem_cgroup *memcg, int idx) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_usage(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_vm_events(struct mem_cgroup *memcg, enum vm_event_item event) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_percpu_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern void bpf_put_mem_cgroup(struct mem_cgroup *memcg) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_sock_ops_enable_tx_tstamp(struct bpf_sock_ops_kern *skops, u64 flags) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern void bpf_throw(u64 cookie) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __weak __ksym;\nextern void scx_bpf_destroy_dsq(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_insert___v2(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local(u64 dsq_id) __weak __ksym;\nextern bool scx_bpf_dsq_move_vtime(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __weak __ksym;\nextern struct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern void scx_bpf_exit_bstr(s64 exit_code, char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern void scx_bpf_kick_cpu(s32 cpu, u64 flags) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern s32 scx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags, const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __weak __ksym;\nextern bool scx_bpf_sub_dispatch(u64 cgroup_id) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime) __weak __ksym;\nextern bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n#pragma clang diagnostic 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wmissing-declarations\"\n#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tA375_CPU_TO_DDR = 0,\n\tA375_CPU_TO_L2 = 1,\n};\n\nenum {\n\tA380_CPU_TO_DDR = 0,\n\tA380_CPU_TO_L2 = 1,\n};\n\nenum {\n\tA390_CPU_TO_NBCLK = 0,\n\tA390_CPU_TO_HCLK = 1,\n\tA390_CPU_TO_DCLK = 2,\n};\n\nenum {\n\tAC = 0,\n\tBAT = 1,\n};\n\nenum {\n\tACC_CONTROL_CACHE_MODE = 4194304,\n\tACC_CONTROL_PREFETCH = 8388608,\n\tACC_CONTROL_PAGE_HIT = 16777216,\n\tACC_CONTROL_WR_PREEMPT = 33554432,\n\tACC_CONTROL_PARTIAL_PAGE = 67108864,\n\tACC_CONTROL_RD_ERASED = 134217728,\n\tACC_CONTROL_FAST_PGM_RDIN = 268435456,\n\tACC_CONTROL_WR_ECC = 1073741824,\n\tACC_CONTROL_RD_ECC = 2147483648,\n};\n\nenum {\n\tACOMP_WALK_SLEEP = 1,\n\tACOMP_WALK_SRC_LINEAR = 2,\n\tACOMP_WALK_DST_LINEAR = 4,\n};\n\nenum {\n\tACT8600 = 0,\n\tACT8865 = 1,\n\tACT8846 = 2,\n};\n\nenum {\n\tACT8600_ID_DCDC1 = 0,\n\tACT8600_ID_DCDC2 = 1,\n\tACT8600_ID_DCDC3 = 2,\n\tACT8600_ID_SUDCDC4 = 3,\n\tACT8600_ID_LDO5 = 4,\n\tACT8600_ID_LDO6 = 5,\n\tACT8600_ID_LDO7 = 6,\n\tACT8600_ID_LDO8 = 7,\n\tACT8600_ID_LDO9 = 8,\n\tACT8600_ID_LDO10 = 9,\n};\n\nenum {\n\tACT8846_ID_REG1 = 0,\n\tACT8846_ID_REG2 = 1,\n\tACT8846_ID_REG3 = 2,\n\tACT8846_ID_REG4 = 3,\n\tACT8846_ID_REG5 = 4,\n\tACT8846_ID_REG6 = 5,\n\tACT8846_ID_REG7 = 6,\n\tACT8846_ID_REG8 = 7,\n\tACT8846_ID_REG9 = 8,\n\tACT8846_ID_REG10 = 9,\n\tACT8846_ID_REG11 = 10,\n\tACT8846_ID_REG12 = 11,\n\tACT8846_REG_NUM = 12,\n};\n\nenum {\n\tACT8865_ID_DCDC1 = 0,\n\tACT8865_ID_DCDC2 = 1,\n\tACT8865_ID_DCDC3 = 2,\n\tACT8865_ID_LDO1 = 3,\n\tACT8865_ID_LDO2 = 4,\n\tACT8865_ID_LDO3 = 5,\n\tACT8865_ID_LDO4 = 6,\n\tACT8865_REG_NUM = 7,\n};\n\nenum {\n\tACT8945A_ID_DCDC1 = 0,\n\tACT8945A_ID_DCDC2 = 1,\n\tACT8945A_ID_DCDC3 = 2,\n\tACT8945A_ID_LDO1 = 3,\n\tACT8945A_ID_LDO2 = 4,\n\tACT8945A_ID_LDO3 = 5,\n\tACT8945A_ID_LDO4 = 6,\n\tACT8945A_ID_MAX = 7,\n};\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tAHB1 = 0,\n\tAHB2 = 1,\n\tAPB1 = 2,\n\tAPB2 = 3,\n\tPARENT_MAX = 4,\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DMPS = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_CPD = 1048576,\n\tPORT_CMD_MPSP = 524288,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_CMD_CAP = 8126464,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_SUSPEND_PHYS = 33554432,\n\tAHCI_HFLAG_NO_SXS = 67108864,\n\tAHCI_HFLAG_43BIT_ONLY = 134217728,\n\tAHCI_HFLAG_INTEL_PCS_QUIRK = 268435456,\n\tAHCI_HFLAG_ATAPI_DMA_QUIRK = 536870912,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 15,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum {\n\tALE_ENT_VID_MEMBER_LIST = 0,\n\tALE_ENT_VID_UNREG_MCAST_MSK = 1,\n\tALE_ENT_VID_REG_MCAST_MSK = 2,\n\tALE_ENT_VID_FORCE_UNTAGGED_MSK = 3,\n\tALE_ENT_VID_UNREG_MCAST_IDX = 4,\n\tALE_ENT_VID_REG_MCAST_IDX = 5,\n\tALE_ENT_VID_LAST = 6,\n};\n\nenum {\n\tAM62A7_EFUSE_M_MPU_OPP = 13,\n\tAM62A7_EFUSE_N_MPU_OPP = 14,\n\tAM62A7_EFUSE_O_MPU_OPP = 15,\n\tAM62A7_EFUSE_P_MPU_OPP = 16,\n\tAM62A7_EFUSE_Q_MPU_OPP = 17,\n\tAM62A7_EFUSE_R_MPU_OPP = 18,\n\tAM62A7_EFUSE_S_MPU_OPP = 19,\n\tAM62A7_EFUSE_V_MPU_OPP = 20,\n\tAM62A7_EFUSE_U_MPU_OPP = 21,\n\tAM62A7_EFUSE_T_MPU_OPP = 22,\n};\n\nenum {\n\tARB_TIMER = 0,\n\tARB_BP_CAP_CLR = 1,\n\tARB_BP_CAP_HI_ADDR = 2,\n\tARB_BP_CAP_ADDR = 3,\n\tARB_BP_CAP_STATUS = 4,\n\tARB_BP_CAP_MASTER = 5,\n\tARB_ERR_CAP_CLR = 6,\n\tARB_ERR_CAP_HI_ADDR = 7,\n\tARB_ERR_CAP_ADDR = 8,\n\tARB_ERR_CAP_STATUS = 9,\n\tARB_ERR_CAP_MASTER = 10,\n};\n\nenum {\n\tAS3711_REGULATOR = 0,\n\tAS3711_BACKLIGHT = 1,\n};\n\nenum {\n\tAS3711_REGULATOR_SD_1 = 0,\n\tAS3711_REGULATOR_SD_2 = 1,\n\tAS3711_REGULATOR_SD_3 = 2,\n\tAS3711_REGULATOR_SD_4 = 3,\n\tAS3711_REGULATOR_LDO_1 = 4,\n\tAS3711_REGULATOR_LDO_2 = 5,\n\tAS3711_REGULATOR_LDO_3 = 6,\n\tAS3711_REGULATOR_LDO_4 = 7,\n\tAS3711_REGULATOR_LDO_5 = 8,\n\tAS3711_REGULATOR_LDO_6 = 9,\n\tAS3711_REGULATOR_LDO_7 = 10,\n\tAS3711_REGULATOR_LDO_8 = 11,\n\tAS3711_REGULATOR_MAX = 12,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tASSACT_REPORT = 0,\n\tASSACT_RO = 1,\n\tASSACT_PANIC = 2,\n};\n\nenum {\n\tASSUME_PERFECT = 255,\n\tASSUME_VALID_DTB = 1,\n\tASSUME_VALID_INPUT = 2,\n\tASSUME_LATEST = 4,\n\tASSUME_NO_ROLLBACK = 8,\n\tASSUME_LIBFDT_ORDER = 16,\n\tASSUME_LIBFDT_FLAWLESS = 32,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = -2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = -2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_CDL = 24,\n\tATA_LOG_CDL_SIZE = 512,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SENSE_NCQ = 15,\n\tATA_LOG_SENSE_NCQ_SIZE = 1024,\n\tATA_LOG_CONCURRENT_POSITIONING_RANGES = 71,\n\tATA_LOG_SUPPORTED_CAPABILITIES = 3,\n\tATA_LOG_CURRENT_SETTINGS = 4,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSETFEATURES_CDL = 13,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tSETFEATURE_SENSE_DATA_SUCC_NCQ = 196,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum {\n\tATA_QUIRK_DIAGNOSTIC = 1,\n\tATA_QUIRK_NODMA = 2,\n\tATA_QUIRK_NONCQ = 4,\n\tATA_QUIRK_BROKEN_HPA = 8,\n\tATA_QUIRK_DISABLE = 16,\n\tATA_QUIRK_HPA_SIZE = 32,\n\tATA_QUIRK_IVB = 64,\n\tATA_QUIRK_STUCK_ERR = 128,\n\tATA_QUIRK_BRIDGE_OK = 256,\n\tATA_QUIRK_ATAPI_MOD16_DMA = 512,\n\tATA_QUIRK_FIRMWARE_WARN = 1024,\n\tATA_QUIRK_1_5_GBPS = 2048,\n\tATA_QUIRK_NOSETXFER = 4096,\n\tATA_QUIRK_BROKEN_FPDMA_AA = 8192,\n\tATA_QUIRK_DUMP_ID = 16384,\n\tATA_QUIRK_MAX_SEC_LBA48 = 32768,\n\tATA_QUIRK_ATAPI_DMADIR = 65536,\n\tATA_QUIRK_NO_NCQ_TRIM = 131072,\n\tATA_QUIRK_NOLPM = 262144,\n\tATA_QUIRK_WD_BROKEN_LPM = 524288,\n\tATA_QUIRK_ZERO_AFTER_TRIM = 1048576,\n\tATA_QUIRK_NO_DMA_LOG = 2097152,\n\tATA_QUIRK_NOTRIM = 4194304,\n\tATA_QUIRK_MAX_SEC = 8388608,\n\tATA_QUIRK_MAX_TRIM_128M = 16777216,\n\tATA_QUIRK_NO_NCQ_ON_ATI = 33554432,\n\tATA_QUIRK_NO_LPM_ON_ATI = 67108864,\n\tATA_QUIRK_NO_ID_DEV_LOG = 134217728,\n\tATA_QUIRK_NO_LOG_DIR = 268435456,\n\tATA_QUIRK_NO_FUA = 536870912,\n};\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = -2147483648,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAUTO = 0,\n\tSPDIF = 1,\n\tHDA = 2,\n};\n\nenum {\n\tAUTOFS_DEV_IOCTL_VERSION_CMD = 113,\n\tAUTOFS_DEV_IOCTL_PROTOVER_CMD = 114,\n\tAUTOFS_DEV_IOCTL_PROTOSUBVER_CMD = 115,\n\tAUTOFS_DEV_IOCTL_OPENMOUNT_CMD = 116,\n\tAUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD = 117,\n\tAUTOFS_DEV_IOCTL_READY_CMD = 118,\n\tAUTOFS_DEV_IOCTL_FAIL_CMD = 119,\n\tAUTOFS_DEV_IOCTL_SETPIPEFD_CMD = 120,\n\tAUTOFS_DEV_IOCTL_CATATONIC_CMD = 121,\n\tAUTOFS_DEV_IOCTL_TIMEOUT_CMD = 122,\n\tAUTOFS_DEV_IOCTL_REQUESTER_CMD = 123,\n\tAUTOFS_DEV_IOCTL_EXPIRE_CMD = 124,\n\tAUTOFS_DEV_IOCTL_ASKUMOUNT_CMD = 125,\n\tAUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD = 126,\n};\n\nenum {\n\tAUTOFS_IOC_EXPIRE_MULTI_CMD = 102,\n\tAUTOFS_IOC_PROTOSUBVER_CMD = 103,\n\tAUTOFS_IOC_ASKUMOUNT_CMD = 112,\n};\n\nenum {\n\tAUTOFS_IOC_READY_CMD = 96,\n\tAUTOFS_IOC_FAIL_CMD = 97,\n\tAUTOFS_IOC_CATATONIC_CMD = 98,\n\tAUTOFS_IOC_PROTOVER_CMD = 99,\n\tAUTOFS_IOC_SETTIMEOUT_CMD = 100,\n\tAUTOFS_IOC_EXPIRE_CMD = 101,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tAXP15060_DCDC1 = 0,\n\tAXP15060_DCDC2 = 1,\n\tAXP15060_DCDC3 = 2,\n\tAXP15060_DCDC4 = 3,\n\tAXP15060_DCDC5 = 4,\n\tAXP15060_DCDC6 = 5,\n\tAXP15060_ALDO1 = 6,\n\tAXP15060_ALDO2 = 7,\n\tAXP15060_ALDO3 = 8,\n\tAXP15060_ALDO4 = 9,\n\tAXP15060_ALDO5 = 10,\n\tAXP15060_BLDO1 = 11,\n\tAXP15060_BLDO2 = 12,\n\tAXP15060_BLDO3 = 13,\n\tAXP15060_BLDO4 = 14,\n\tAXP15060_BLDO5 = 15,\n\tAXP15060_CLDO1 = 16,\n\tAXP15060_CLDO2 = 17,\n\tAXP15060_CLDO3 = 18,\n\tAXP15060_CLDO4 = 19,\n\tAXP15060_CPUSLDO = 20,\n\tAXP15060_SW = 21,\n\tAXP15060_RTC_LDO = 22,\n\tAXP15060_REG_ID_MAX = 23,\n};\n\nenum {\n\tAXP152_IRQ_LDO0IN_CONNECT = 1,\n\tAXP152_IRQ_LDO0IN_REMOVAL = 2,\n\tAXP152_IRQ_ALDO0IN_CONNECT = 3,\n\tAXP152_IRQ_ALDO0IN_REMOVAL = 4,\n\tAXP152_IRQ_DCDC1_V_LOW = 5,\n\tAXP152_IRQ_DCDC2_V_LOW = 6,\n\tAXP152_IRQ_DCDC3_V_LOW = 7,\n\tAXP152_IRQ_DCDC4_V_LOW = 8,\n\tAXP152_IRQ_PEK_SHORT = 9,\n\tAXP152_IRQ_PEK_LONG = 10,\n\tAXP152_IRQ_TIMER = 11,\n\tAXP152_IRQ_PEK_FAL_EDGE = 12,\n\tAXP152_IRQ_PEK_RIS_EDGE = 13,\n\tAXP152_IRQ_GPIO3_INPUT = 14,\n\tAXP152_IRQ_GPIO2_INPUT = 15,\n\tAXP152_IRQ_GPIO1_INPUT = 16,\n\tAXP152_IRQ_GPIO0_INPUT = 17,\n};\n\nenum {\n\tAXP20X_IRQ_ACIN_OVER_V = 1,\n\tAXP20X_IRQ_ACIN_PLUGIN = 2,\n\tAXP20X_IRQ_ACIN_REMOVAL = 3,\n\tAXP20X_IRQ_VBUS_OVER_V = 4,\n\tAXP20X_IRQ_VBUS_PLUGIN = 5,\n\tAXP20X_IRQ_VBUS_REMOVAL = 6,\n\tAXP20X_IRQ_VBUS_V_LOW = 7,\n\tAXP20X_IRQ_BATT_PLUGIN = 8,\n\tAXP20X_IRQ_BATT_REMOVAL = 9,\n\tAXP20X_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP20X_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP20X_IRQ_CHARG = 12,\n\tAXP20X_IRQ_CHARG_DONE = 13,\n\tAXP20X_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP20X_IRQ_BATT_TEMP_LOW = 15,\n\tAXP20X_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP20X_IRQ_CHARG_I_LOW = 17,\n\tAXP20X_IRQ_DCDC1_V_LONG = 18,\n\tAXP20X_IRQ_DCDC2_V_LONG = 19,\n\tAXP20X_IRQ_DCDC3_V_LONG = 20,\n\tAXP20X_IRQ_PEK_SHORT = 22,\n\tAXP20X_IRQ_PEK_LONG = 23,\n\tAXP20X_IRQ_N_OE_PWR_ON = 24,\n\tAXP20X_IRQ_N_OE_PWR_OFF = 25,\n\tAXP20X_IRQ_VBUS_VALID = 26,\n\tAXP20X_IRQ_VBUS_NOT_VALID = 27,\n\tAXP20X_IRQ_VBUS_SESS_VALID = 28,\n\tAXP20X_IRQ_VBUS_SESS_END = 29,\n\tAXP20X_IRQ_LOW_PWR_LVL1 = 30,\n\tAXP20X_IRQ_LOW_PWR_LVL2 = 31,\n\tAXP20X_IRQ_TIMER = 32,\n\tAXP20X_IRQ_PEK_FAL_EDGE = 33,\n\tAXP20X_IRQ_PEK_RIS_EDGE = 34,\n\tAXP20X_IRQ_GPIO3_INPUT = 35,\n\tAXP20X_IRQ_GPIO2_INPUT = 36,\n\tAXP20X_IRQ_GPIO1_INPUT = 37,\n\tAXP20X_IRQ_GPIO0_INPUT = 38,\n};\n\nenum {\n\tAXP20X_LDO1 = 0,\n\tAXP20X_LDO2 = 1,\n\tAXP20X_LDO3 = 2,\n\tAXP20X_LDO4 = 3,\n\tAXP20X_LDO5 = 4,\n\tAXP20X_DCDC2 = 5,\n\tAXP20X_DCDC3 = 6,\n\tAXP20X_REG_ID_MAX = 7,\n};\n\nenum {\n\tAXP22X_DCDC1 = 0,\n\tAXP22X_DCDC2 = 1,\n\tAXP22X_DCDC3 = 2,\n\tAXP22X_DCDC4 = 3,\n\tAXP22X_DCDC5 = 4,\n\tAXP22X_DC1SW = 5,\n\tAXP22X_DC5LDO = 6,\n\tAXP22X_ALDO1 = 7,\n\tAXP22X_ALDO2 = 8,\n\tAXP22X_ALDO3 = 9,\n\tAXP22X_ELDO1 = 10,\n\tAXP22X_ELDO2 = 11,\n\tAXP22X_ELDO3 = 12,\n\tAXP22X_DLDO1 = 13,\n\tAXP22X_DLDO2 = 14,\n\tAXP22X_DLDO3 = 15,\n\tAXP22X_DLDO4 = 16,\n\tAXP22X_RTC_LDO = 17,\n\tAXP22X_LDO_IO0 = 18,\n\tAXP22X_LDO_IO1 = 19,\n\tAXP22X_REG_ID_MAX = 20,\n};\n\nenum {\n\tAXP313A_DCDC1 = 0,\n\tAXP313A_DCDC2 = 1,\n\tAXP313A_DCDC3 = 2,\n\tAXP313A_ALDO1 = 3,\n\tAXP313A_DLDO1 = 4,\n\tAXP313A_RTC_LDO = 5,\n\tAXP313A_REG_ID_MAX = 6,\n};\n\nenum {\n\tAXP717_DCDC1 = 0,\n\tAXP717_DCDC2 = 1,\n\tAXP717_DCDC3 = 2,\n\tAXP717_DCDC4 = 3,\n\tAXP717_ALDO1 = 4,\n\tAXP717_ALDO2 = 5,\n\tAXP717_ALDO3 = 6,\n\tAXP717_ALDO4 = 7,\n\tAXP717_BLDO1 = 8,\n\tAXP717_BLDO2 = 9,\n\tAXP717_BLDO3 = 10,\n\tAXP717_BLDO4 = 11,\n\tAXP717_CLDO1 = 12,\n\tAXP717_CLDO2 = 13,\n\tAXP717_CLDO3 = 14,\n\tAXP717_CLDO4 = 15,\n\tAXP717_CPUSLDO = 16,\n\tAXP717_BOOST = 17,\n\tAXP717_REG_ID_MAX = 18,\n};\n\nenum {\n\tAXP803_DCDC1 = 0,\n\tAXP803_DCDC2 = 1,\n\tAXP803_DCDC3 = 2,\n\tAXP803_DCDC4 = 3,\n\tAXP803_DCDC5 = 4,\n\tAXP803_DCDC6 = 5,\n\tAXP803_DC1SW = 6,\n\tAXP803_ALDO1 = 7,\n\tAXP803_ALDO2 = 8,\n\tAXP803_ALDO3 = 9,\n\tAXP803_DLDO1 = 10,\n\tAXP803_DLDO2 = 11,\n\tAXP803_DLDO3 = 12,\n\tAXP803_DLDO4 = 13,\n\tAXP803_ELDO1 = 14,\n\tAXP803_ELDO2 = 15,\n\tAXP803_ELDO3 = 16,\n\tAXP803_FLDO1 = 17,\n\tAXP803_FLDO2 = 18,\n\tAXP803_RTC_LDO = 19,\n\tAXP803_LDO_IO0 = 20,\n\tAXP803_LDO_IO1 = 21,\n\tAXP803_REG_ID_MAX = 22,\n};\n\nenum {\n\tAXP806_DCDCA = 0,\n\tAXP806_DCDCB = 1,\n\tAXP806_DCDCC = 2,\n\tAXP806_DCDCD = 3,\n\tAXP806_DCDCE = 4,\n\tAXP806_ALDO1 = 5,\n\tAXP806_ALDO2 = 6,\n\tAXP806_ALDO3 = 7,\n\tAXP806_BLDO1 = 8,\n\tAXP806_BLDO2 = 9,\n\tAXP806_BLDO3 = 10,\n\tAXP806_BLDO4 = 11,\n\tAXP806_CLDO1 = 12,\n\tAXP806_CLDO2 = 13,\n\tAXP806_CLDO3 = 14,\n\tAXP806_SW = 15,\n\tAXP806_REG_ID_MAX = 16,\n};\n\nenum {\n\tAXP809_DCDC1 = 0,\n\tAXP809_DCDC2 = 1,\n\tAXP809_DCDC3 = 2,\n\tAXP809_DCDC4 = 3,\n\tAXP809_DCDC5 = 4,\n\tAXP809_DC1SW = 5,\n\tAXP809_DC5LDO = 6,\n\tAXP809_ALDO1 = 7,\n\tAXP809_ALDO2 = 8,\n\tAXP809_ALDO3 = 9,\n\tAXP809_ELDO1 = 10,\n\tAXP809_ELDO2 = 11,\n\tAXP809_ELDO3 = 12,\n\tAXP809_DLDO1 = 13,\n\tAXP809_DLDO2 = 14,\n\tAXP809_RTC_LDO = 15,\n\tAXP809_LDO_IO0 = 16,\n\tAXP809_LDO_IO1 = 17,\n\tAXP809_SW = 18,\n\tAXP809_REG_ID_MAX = 19,\n};\n\nenum {\n\tAXP813_DCDC1 = 0,\n\tAXP813_DCDC2 = 1,\n\tAXP813_DCDC3 = 2,\n\tAXP813_DCDC4 = 3,\n\tAXP813_DCDC5 = 4,\n\tAXP813_DCDC6 = 5,\n\tAXP813_DCDC7 = 6,\n\tAXP813_ALDO1 = 7,\n\tAXP813_ALDO2 = 8,\n\tAXP813_ALDO3 = 9,\n\tAXP813_DLDO1 = 10,\n\tAXP813_DLDO2 = 11,\n\tAXP813_DLDO3 = 12,\n\tAXP813_DLDO4 = 13,\n\tAXP813_ELDO1 = 14,\n\tAXP813_ELDO2 = 15,\n\tAXP813_ELDO3 = 16,\n\tAXP813_FLDO1 = 17,\n\tAXP813_FLDO2 = 18,\n\tAXP813_FLDO3 = 19,\n\tAXP813_RTC_LDO = 20,\n\tAXP813_LDO_IO0 = 21,\n\tAXP813_LDO_IO1 = 22,\n\tAXP813_SW = 23,\n\tAXP813_REG_ID_MAX = 24,\n};\n\nenum {\n\tAXP_CPU_TO_NBCLK = 0,\n\tAXP_CPU_TO_HCLK = 1,\n\tAXP_CPU_TO_DRAMCLK = 2,\n};\n\nenum {\n\tBCMBCA_CTLRDY = 16,\n};\n\nenum {\n\tBCM_MSG_FUNC_LINK_START = 0,\n\tBCM_MSG_FUNC_LINK_STOP = 1,\n\tBCM_MSG_FUNC_SHMEM_TX = 2,\n\tBCM_MSG_FUNC_SHMEM_RX = 3,\n\tBCM_MSG_FUNC_SHMEM_STOP = 4,\n\tBCM_MSG_FUNC_MAX = 5,\n};\n\nenum {\n\tBCM_MSG_SVC_INIT = 0,\n\tBCM_MSG_SVC_PMC = 1,\n\tBCM_MSG_SVC_SCMI = 2,\n\tBCM_MSG_SVC_DPFE = 3,\n\tBCM_MSG_SVC_MAX = 4,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nenum {\n\tBOOST_ILMIN_75MA = 0,\n\tBOOST_ILMIN_100MA = 1,\n\tBOOST_ILMIN_125MA = 2,\n\tBOOST_ILMIN_150MA = 3,\n\tBOOST_ILMIN_175MA = 4,\n\tBOOST_ILMIN_200MA = 5,\n\tBOOST_ILMIN_225MA = 6,\n\tBOOST_ILMIN_250MA = 7,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_CURRENT_NETNS = -1,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 38,\n};\n\nenum {\n\tBPF_R2_HI = 0,\n\tBPF_R2_LO = 1,\n\tBPF_R3_HI = 2,\n\tBPF_R3_LO = 3,\n\tBPF_R4_HI = 4,\n\tBPF_R4_LO = 5,\n\tBPF_R5_HI = 6,\n\tBPF_R5_LO = 7,\n\tBPF_R7_HI = 8,\n\tBPF_R7_LO = 9,\n\tBPF_R8_HI = 10,\n\tBPF_R8_LO = 11,\n\tBPF_R9_HI = 12,\n\tBPF_R9_LO = 13,\n\tBPF_FP_HI = 14,\n\tBPF_FP_LO = 15,\n\tBPF_TC_HI = 16,\n\tBPF_TC_LO = 17,\n\tBPF_AX_HI = 18,\n\tBPF_AX_LO = 19,\n\tBPF_JIT_SCRATCH_REGS = 20,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBPF_XFRM_STATE_OPTS_SZ = 36,\n};\n\nenum {\n\tBRCMNAND_HAS_1K_SECTORS = 1,\n\tBRCMNAND_HAS_PREFETCH = 2,\n\tBRCMNAND_HAS_CACHE_MODE = 4,\n\tBRCMNAND_HAS_WP = 8,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tBUCK_ILMIN_50MA = 0,\n\tBUCK_ILMIN_100MA = 1,\n\tBUCK_ILMIN_150MA = 2,\n\tBUCK_ILMIN_200MA = 3,\n\tBUCK_ILMIN_250MA = 4,\n\tBUCK_ILMIN_300MA = 5,\n\tBUCK_ILMIN_350MA = 6,\n\tBUCK_ILMIN_400MA = 7,\n};\n\nenum {\n\tCACHE_VALID = 0,\n\tCACHE_NEGATIVE = 1,\n\tCACHE_PENDING = 2,\n\tCACHE_CLEANED = 3,\n};\n\nenum {\n\tCAN_RAW_FILTER = 1,\n\tCAN_RAW_ERR_FILTER = 2,\n\tCAN_RAW_LOOPBACK = 3,\n\tCAN_RAW_RECV_OWN_MSGS = 4,\n\tCAN_RAW_FD_FRAMES = 5,\n\tCAN_RAW_JOIN_FILTERS = 6,\n\tCAN_RAW_XL_FRAMES = 7,\n\tCAN_RAW_XL_VCID_OPTS = 8,\n};\n\nenum {\n\tCAPS_0_SUPPORT_LL123 = 1048576,\n\tCAPS_0_SUPPORT_LL4 = 2097152,\n\tCCR_FS = 32,\n\tCCR_READ_PRIORITY = 64,\n\tCCR_ENABLE = 128,\n\tCCR_AUTO_INIT = 256,\n\tCCR_REPEAT = 512,\n\tCCR_OMAP31_DISABLE = 1024,\n\tCCR_SUSPEND_SENSITIVE = 256,\n\tCCR_RD_ACTIVE = 512,\n\tCCR_WR_ACTIVE = 1024,\n\tCCR_SRC_AMODE_CONSTANT = 0,\n\tCCR_SRC_AMODE_POSTINC = 4096,\n\tCCR_SRC_AMODE_SGLIDX = 8192,\n\tCCR_SRC_AMODE_DBLIDX = 12288,\n\tCCR_DST_AMODE_CONSTANT = 0,\n\tCCR_DST_AMODE_POSTINC = 16384,\n\tCCR_DST_AMODE_SGLIDX = 32768,\n\tCCR_DST_AMODE_DBLIDX = 49152,\n\tCCR_CONSTANT_FILL = 65536,\n\tCCR_TRANSPARENT_COPY = 131072,\n\tCCR_BS = 262144,\n\tCCR_SUPERVISOR = 4194304,\n\tCCR_PREFETCH = 8388608,\n\tCCR_TRIGGER_SRC = 16777216,\n\tCCR_BUFFERING_DISABLE = 33554432,\n\tCCR_WRITE_PRIORITY = 67108864,\n\tCCR_SYNC_ELEMENT = 0,\n\tCCR_SYNC_FRAME = 32,\n\tCCR_SYNC_BLOCK = 262144,\n\tCCR_SYNC_PACKET = 262176,\n\tCSDP_DATA_TYPE_8 = 0,\n\tCSDP_DATA_TYPE_16 = 1,\n\tCSDP_DATA_TYPE_32 = 2,\n\tCSDP_SRC_PORT_EMIFF = 0,\n\tCSDP_SRC_PORT_EMIFS = 4,\n\tCSDP_SRC_PORT_OCP_T1 = 8,\n\tCSDP_SRC_PORT_TIPB = 12,\n\tCSDP_SRC_PORT_OCP_T2 = 16,\n\tCSDP_SRC_PORT_MPUI = 20,\n\tCSDP_SRC_PACKED = 64,\n\tCSDP_SRC_BURST_1 = 0,\n\tCSDP_SRC_BURST_16 = 128,\n\tCSDP_SRC_BURST_32 = 256,\n\tCSDP_SRC_BURST_64 = 384,\n\tCSDP_DST_PORT_EMIFF = 0,\n\tCSDP_DST_PORT_EMIFS = 512,\n\tCSDP_DST_PORT_OCP_T1 = 1024,\n\tCSDP_DST_PORT_TIPB = 1536,\n\tCSDP_DST_PORT_OCP_T2 = 2048,\n\tCSDP_DST_PORT_MPUI = 2560,\n\tCSDP_DST_PACKED = 8192,\n\tCSDP_DST_BURST_1 = 0,\n\tCSDP_DST_BURST_16 = 16384,\n\tCSDP_DST_BURST_32 = 32768,\n\tCSDP_DST_BURST_64 = 49152,\n\tCSDP_WRITE_NON_POSTED = 0,\n\tCSDP_WRITE_POSTED = 65536,\n\tCSDP_WRITE_LAST_NON_POSTED = 131072,\n\tCICR_TOUT_IE = 1,\n\tCICR_DROP_IE = 2,\n\tCICR_HALF_IE = 4,\n\tCICR_FRAME_IE = 8,\n\tCICR_LAST_IE = 16,\n\tCICR_BLOCK_IE = 32,\n\tCICR_PKT_IE = 128,\n\tCICR_TRANS_ERR_IE = 256,\n\tCICR_SUPERVISOR_ERR_IE = 1024,\n\tCICR_MISALIGNED_ERR_IE = 2048,\n\tCICR_DRAIN_IE = 4096,\n\tCICR_SUPER_BLOCK_IE = 16384,\n\tCLNK_CTRL_ENABLE_LNK = 32768,\n\tCDP_DST_VALID_INC = 0,\n\tCDP_DST_VALID_RELOAD = 1,\n\tCDP_DST_VALID_REUSE = 2,\n\tCDP_SRC_VALID_INC = 0,\n\tCDP_SRC_VALID_RELOAD = 4,\n\tCDP_SRC_VALID_REUSE = 8,\n\tCDP_NTYPE_TYPE1 = 16,\n\tCDP_NTYPE_TYPE2 = 32,\n\tCDP_NTYPE_TYPE3 = 48,\n\tCDP_TMODE_NORMAL = 0,\n\tCDP_TMODE_LLIST = 256,\n\tCDP_FAST = 1024,\n};\n\nenum {\n\tCFG_BLK_ADR_BYTES_SHIFT = 8,\n\tCFG_COL_ADR_BYTES_SHIFT = 12,\n\tCFG_FUL_ADR_BYTES_SHIFT = 16,\n\tCFG_BUS_WIDTH_SHIFT = 23,\n\tCFG_BUS_WIDTH = 8388608,\n\tCFG_DEVICE_SIZE_SHIFT = 24,\n\tCFG_PAGE_SIZE_SHIFT_v2_1 = 30,\n\tCFG_PAGE_SIZE_SHIFT = 20,\n\tCFG_BLK_SIZE_SHIFT = 28,\n\tCFG_EXT_PAGE_SIZE_SHIFT = 0,\n\tCFG_EXT_BLK_SIZE_SHIFT = 4,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCGW_CRC8PRF_UNSPEC = 0,\n\tCGW_CRC8PRF_1U8 = 1,\n\tCGW_CRC8PRF_16U8 = 2,\n\tCGW_CRC8PRF_SFFID_XOR = 3,\n\t__CGW_CRC8PRF_MAX = 4,\n};\n\nenum {\n\tCGW_TYPE_UNSPEC = 0,\n\tCGW_TYPE_CAN_CAN = 1,\n\t__CGW_TYPE_MAX = 2,\n};\n\nenum {\n\tCGW_UNSPEC = 0,\n\tCGW_MOD_AND = 1,\n\tCGW_MOD_OR = 2,\n\tCGW_MOD_XOR = 3,\n\tCGW_MOD_SET = 4,\n\tCGW_CS_XOR = 5,\n\tCGW_CS_CRC8 = 6,\n\tCGW_HANDLED = 7,\n\tCGW_DROPPED = 8,\n\tCGW_SRC_IF = 9,\n\tCGW_DST_IF = 10,\n\tCGW_FILTER = 11,\n\tCGW_DELETED = 12,\n\tCGW_LIM_HOPS = 13,\n\tCGW_MOD_UID = 14,\n\tCGW_FDMOD_AND = 15,\n\tCGW_FDMOD_OR = 16,\n\tCGW_FDMOD_XOR = 17,\n\tCGW_FDMOD_SET = 18,\n\t__CGW_MAX = 19,\n};\n\nenum {\n\tCLK_ALPHA_PLL_TYPE_DEFAULT = 0,\n\tCLK_ALPHA_PLL_TYPE_HUAYRA = 1,\n\tCLK_ALPHA_PLL_TYPE_HUAYRA_APSS = 2,\n\tCLK_ALPHA_PLL_TYPE_HUAYRA_2290 = 3,\n\tCLK_ALPHA_PLL_TYPE_BRAMMO = 4,\n\tCLK_ALPHA_PLL_TYPE_FABIA = 5,\n\tCLK_ALPHA_PLL_TYPE_TRION = 6,\n\tCLK_ALPHA_PLL_TYPE_LUCID = 6,\n\tCLK_ALPHA_PLL_TYPE_AGERA = 7,\n\tCLK_ALPHA_PLL_TYPE_ZONDA = 8,\n\tCLK_ALPHA_PLL_TYPE_REGERA = 8,\n\tCLK_ALPHA_PLL_TYPE_ZONDA_OLE = 9,\n\tCLK_ALPHA_PLL_TYPE_LUCID_EVO = 10,\n\tCLK_ALPHA_PLL_TYPE_LUCID_OLE = 11,\n\tCLK_ALPHA_PLL_TYPE_PONGO_ELU = 12,\n\tCLK_ALPHA_PLL_TYPE_PONGO_EKO_T = 12,\n\tCLK_ALPHA_PLL_TYPE_TAYCAN_ELU = 13,\n\tCLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = 13,\n\tCLK_ALPHA_PLL_TYPE_RIVIAN_EVO = 14,\n\tCLK_ALPHA_PLL_TYPE_RIVIAN_ELU = 15,\n\tCLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T = 15,\n\tCLK_ALPHA_PLL_TYPE_DEFAULT_EVO = 16,\n\tCLK_ALPHA_PLL_TYPE_BRAMMO_EVO = 17,\n\tCLK_ALPHA_PLL_TYPE_STROMER = 18,\n\tCLK_ALPHA_PLL_TYPE_STROMER_PLUS = 19,\n\tCLK_ALPHA_PLL_TYPE_NSS_HUAYRA = 20,\n\tCLK_ALPHA_PLL_TYPE_MAX = 21,\n};\n\nenum {\n\tCLK_COMPONENT_TYPE_GATE = 0,\n\tCLK_COMPONENT_TYPE_DIVIDER = 1,\n\tCLK_COMPONENT_TYPE_MUX = 2,\n\tCLK_COMPONENT_TYPE_MAX = 3,\n};\n\nenum {\n\tCLK_QSPI_REF = 0,\n\tCLK_QSPI_APB = 1,\n\tCLK_QSPI_AHB = 2,\n\tCLK_QSPI_NUM = 3,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCOHERENCY_FABRIC_TYPE_NONE = 0,\n\tCOHERENCY_FABRIC_TYPE_ARMADA_370_XP = 1,\n\tCOHERENCY_FABRIC_TYPE_ARMADA_375 = 2,\n\tCOHERENCY_FABRIC_TYPE_ARMADA_380 = 3,\n};\n\nenum {\n\tCOMMIT_RESTING = 0,\n\tCOMMIT_BACKGROUND = 1,\n\tCOMMIT_REQUIRED = 2,\n\tCOMMIT_RUNNING_BACKGROUND = 3,\n\tCOMMIT_RUNNING_REQUIRED = 4,\n\tCOMMIT_BROKEN = 5,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCPSW_ALE_F_STATUS_REG = 1,\n\tCPSW_ALE_F_HW_AUTOAGING = 2,\n\tCPSW_ALE_F_COUNT = 3,\n};\n\nenum {\n\tCPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,\n\tCPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV = 1,\n\tCPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG = 2,\n\tCPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG = 3,\n};\n\nenum {\n\tCPSW_SL_CTL_FULLDUPLEX = 1,\n\tCPSW_SL_CTL_LOOPBACK = 2,\n\tCPSW_SL_CTL_MTEST = 4,\n\tCPSW_SL_CTL_RX_FLOW_EN = 8,\n\tCPSW_SL_CTL_TX_FLOW_EN = 16,\n\tCPSW_SL_CTL_GMII_EN = 32,\n\tCPSW_SL_CTL_TX_PACE = 64,\n\tCPSW_SL_CTL_GIG = 128,\n\tCPSW_SL_CTL_XGIG = 256,\n\tCPSW_SL_CTL_TX_SHORT_GAP_EN = 1024,\n\tCPSW_SL_CTL_CMD_IDLE = 2048,\n\tCPSW_SL_CTL_CRC_TYPE = 4096,\n\tCPSW_SL_CTL_XGMII_EN = 8192,\n\tCPSW_SL_CTL_IFCTL_A = 32768,\n\tCPSW_SL_CTL_IFCTL_B = 65536,\n\tCPSW_SL_CTL_GIG_FORCE = 131072,\n\tCPSW_SL_CTL_EXT_EN = 262144,\n\tCPSW_SL_CTL_EXT_EN_RX_FLO = 524288,\n\tCPSW_SL_CTL_EXT_EN_TX_FLO = 1048576,\n\tCPSW_SL_CTL_TX_SG_LIM_EN = 2097152,\n\tCPSW_SL_CTL_RX_CEF_EN = 4194304,\n\tCPSW_SL_CTL_RX_CSF_EN = 8388608,\n\tCPSW_SL_CTL_RX_CMF_EN = 16777216,\n\tCPSW_SL_CTL_EXT_EN_XGIG = 33554432,\n\tCPSW_SL_CTL_FUNCS_COUNT = 33554433,\n};\n\nenum {\n\tCPSW_STATS = 0,\n\tCPDMA_RX_STATS = 1,\n\tCPDMA_TX_STATS = 2,\n};\n\nenum {\n\tCPTS_EV_PUSH = 0,\n\tCPTS_EV_ROLL = 1,\n\tCPTS_EV_HALF = 2,\n\tCPTS_EV_HW = 3,\n\tCPTS_EV_RX = 4,\n\tCPTS_EV_TX = 5,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 100,\n\tCRNG_RESEED_INTERVAL = 6000,\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\t__CRYPTOA_MAX = 3,\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCS_SELECT_NAND_WP = 536870912,\n\tCS_SELECT_AUTO_DEVICE_ID_CFG = 1073741824,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tDAD_PROCESS = 0,\n\tDAD_BEGIN = 1,\n\tDAD_ABORT = 2,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEVCONF_FORWARDING = 0,\n\tDEVCONF_HOPLIMIT = 1,\n\tDEVCONF_MTU6 = 2,\n\tDEVCONF_ACCEPT_RA = 3,\n\tDEVCONF_ACCEPT_REDIRECTS = 4,\n\tDEVCONF_AUTOCONF = 5,\n\tDEVCONF_DAD_TRANSMITS = 6,\n\tDEVCONF_RTR_SOLICITS = 7,\n\tDEVCONF_RTR_SOLICIT_INTERVAL = 8,\n\tDEVCONF_RTR_SOLICIT_DELAY = 9,\n\tDEVCONF_USE_TEMPADDR = 10,\n\tDEVCONF_TEMP_VALID_LFT = 11,\n\tDEVCONF_TEMP_PREFERED_LFT = 12,\n\tDEVCONF_REGEN_MAX_RETRY = 13,\n\tDEVCONF_MAX_DESYNC_FACTOR = 14,\n\tDEVCONF_MAX_ADDRESSES = 15,\n\tDEVCONF_FORCE_MLD_VERSION = 16,\n\tDEVCONF_ACCEPT_RA_DEFRTR = 17,\n\tDEVCONF_ACCEPT_RA_PINFO = 18,\n\tDEVCONF_ACCEPT_RA_RTR_PREF = 19,\n\tDEVCONF_RTR_PROBE_INTERVAL = 20,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN = 21,\n\tDEVCONF_PROXY_NDP = 22,\n\tDEVCONF_OPTIMISTIC_DAD = 23,\n\tDEVCONF_ACCEPT_SOURCE_ROUTE = 24,\n\tDEVCONF_MC_FORWARDING = 25,\n\tDEVCONF_DISABLE_IPV6 = 26,\n\tDEVCONF_ACCEPT_DAD = 27,\n\tDEVCONF_FORCE_TLLAO = 28,\n\tDEVCONF_NDISC_NOTIFY = 29,\n\tDEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL = 30,\n\tDEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL = 31,\n\tDEVCONF_SUPPRESS_FRAG_NDISC = 32,\n\tDEVCONF_ACCEPT_RA_FROM_LOCAL = 33,\n\tDEVCONF_USE_OPTIMISTIC = 34,\n\tDEVCONF_ACCEPT_RA_MTU = 35,\n\tDEVCONF_STABLE_SECRET = 36,\n\tDEVCONF_USE_OIF_ADDRS_ONLY = 37,\n\tDEVCONF_ACCEPT_RA_MIN_HOP_LIMIT = 38,\n\tDEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 39,\n\tDEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 40,\n\tDEVCONF_DROP_UNSOLICITED_NA = 41,\n\tDEVCONF_KEEP_ADDR_ON_DOWN = 42,\n\tDEVCONF_RTR_SOLICIT_MAX_INTERVAL = 43,\n\tDEVCONF_SEG6_ENABLED = 44,\n\tDEVCONF_SEG6_REQUIRE_HMAC = 45,\n\tDEVCONF_ENHANCED_DAD = 46,\n\tDEVCONF_ADDR_GEN_MODE = 47,\n\tDEVCONF_DISABLE_POLICY = 48,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN = 49,\n\tDEVCONF_NDISC_TCLASS = 50,\n\tDEVCONF_RPL_SEG_ENABLED = 51,\n\tDEVCONF_RA_DEFRTR_METRIC = 52,\n\tDEVCONF_IOAM6_ENABLED = 53,\n\tDEVCONF_IOAM6_ID = 54,\n\tDEVCONF_IOAM6_ID_WIDE = 55,\n\tDEVCONF_NDISC_EVICT_NOCARRIER = 56,\n\tDEVCONF_ACCEPT_UNTRACKED_NA = 57,\n\tDEVCONF_ACCEPT_RA_MIN_LFT = 58,\n\tDEVCONF_FORCE_FORWARDING = 59,\n\tDEVCONF_MAX = 60,\n};\n\nenum {\n\tDEVLINK_ATTR_STATS_RX_PACKETS = 0,\n\tDEVLINK_ATTR_STATS_RX_BYTES = 1,\n\tDEVLINK_ATTR_STATS_RX_DROPPED = 2,\n\t__DEVLINK_ATTR_STATS_MAX = 3,\n\tDEVLINK_ATTR_STATS_MAX = 2,\n};\n\nenum {\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_IN_PORT = 0,\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_FA_COOKIE = 1,\n};\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIRTY_CNODE = 0,\n\tOBSOLETE_CNODE = 1,\n\tCOW_CNODE = 2,\n};\n\nenum {\n\tDIRTY_ZNODE = 0,\n\tCOW_ZNODE = 1,\n\tOBSOLETE_ZNODE = 2,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDIV_CTRL0 = 0,\n\tDIV_CTRL1 = 4,\n\tDIV_CTRL1_N_RESET_MASK = 1024,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDOVE_CPU_TO_L2 = 0,\n\tDOVE_CPU_TO_DDR = 1,\n};\n\nenum {\n\tDOWN = 0,\n\tUP = 1,\n};\n\nenum {\n\tDP83867_PORT_MIRROING_KEEP = 0,\n\tDP83867_PORT_MIRROING_EN = 1,\n\tDP83867_PORT_MIRROING_DIS = 2,\n};\n\nenum {\n\tDRV_FIXED = 0,\n\tDRV_GRP0 = 1,\n\tDRV_GRP1 = 2,\n\tDRV_GRP2 = 3,\n\tDRV_GRP3 = 4,\n\tDRV_GRP4 = 5,\n\tDRV_GRP_MAX = 6,\n};\n\nenum {\n\tDS3231_CLK_SQW = 0,\n\tDS3231_CLK_32KHZ = 1,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tEDSR = 0,\n\tEDMR = 1,\n\tEDTRR = 2,\n\tEDRRR = 3,\n\tEESR = 4,\n\tEESIPR = 5,\n\tTDLAR = 6,\n\tTDFAR = 7,\n\tTDFXR = 8,\n\tTDFFR = 9,\n\tRDLAR = 10,\n\tRDFAR = 11,\n\tRDFXR = 12,\n\tRDFFR = 13,\n\tTRSCER = 14,\n\tRMFCR = 15,\n\tTFTR = 16,\n\tFDR = 17,\n\tRMCR = 18,\n\tEDOCR = 19,\n\tTFUCR = 20,\n\tRFOCR = 21,\n\tRMIIMODE = 22,\n\tFCFTR = 23,\n\tRPADIR = 24,\n\tTRIMD = 25,\n\tRBWAR = 26,\n\tTBRAR = 27,\n\tECMR = 28,\n\tECSR = 29,\n\tECSIPR = 30,\n\tPIR = 31,\n\tPSR = 32,\n\tRDMLR = 33,\n\tPIPR = 34,\n\tRFLR = 35,\n\tIPGR = 36,\n\tAPR = 37,\n\tMPR = 38,\n\tPFTCR = 39,\n\tPFRCR = 40,\n\tRFCR = 41,\n\tRFCF = 42,\n\tTPAUSER = 43,\n\tTPAUSECR = 44,\n\tBCFR = 45,\n\tBCFRR = 46,\n\tGECMR = 47,\n\tBCULR = 48,\n\tMAHR = 49,\n\tMALR = 50,\n\tTROCR = 51,\n\tCDCR = 52,\n\tLCCR = 53,\n\tCNDCR = 54,\n\tCEFCR = 55,\n\tFRECR = 56,\n\tTSFRCR = 57,\n\tTLFRCR = 58,\n\tCERCR = 59,\n\tCEECR = 60,\n\tMAFCR = 61,\n\tRTRATE = 62,\n\tCSMR = 63,\n\tRMII_MII = 64,\n\tARSTR = 65,\n\tTSU_CTRST = 66,\n\tTSU_FWEN0 = 67,\n\tTSU_FWEN1 = 68,\n\tTSU_FCM = 69,\n\tTSU_BSYSL0 = 70,\n\tTSU_BSYSL1 = 71,\n\tTSU_PRISL0 = 72,\n\tTSU_PRISL1 = 73,\n\tTSU_FWSL0 = 74,\n\tTSU_FWSL1 = 75,\n\tTSU_FWSLC = 76,\n\tTSU_QTAG0 = 77,\n\tTSU_QTAG1 = 78,\n\tTSU_QTAGM0 = 79,\n\tTSU_QTAGM1 = 80,\n\tTSU_FWSR = 81,\n\tTSU_FWINMK = 82,\n\tTSU_ADQT0 = 83,\n\tTSU_ADQT1 = 84,\n\tTSU_VTAG0 = 85,\n\tTSU_VTAG1 = 86,\n\tTSU_ADSBSY = 87,\n\tTSU_TEN = 88,\n\tTSU_POST1 = 89,\n\tTSU_POST2 = 90,\n\tTSU_POST3 = 91,\n\tTSU_POST4 = 92,\n\tTSU_ADRH0 = 93,\n\tTXNLCR0 = 94,\n\tTXALCR0 = 95,\n\tRXNLCR0 = 96,\n\tRXALCR0 = 97,\n\tFWNLCR0 = 98,\n\tFWALCR0 = 99,\n\tTXNLCR1 = 100,\n\tTXALCR1 = 101,\n\tRXNLCR1 = 102,\n\tRXALCR1 = 103,\n\tFWNLCR1 = 104,\n\tFWALCR1 = 105,\n\tSH_ETH_MAX_REGISTER_OFFSET = 106,\n};\n\nenum {\n\tELANTECH_SMBUS_NOT_SET = -1,\n\tELANTECH_SMBUS_OFF = 0,\n\tELANTECH_SMBUS_ON = 1,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_CODE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_CODE_OK = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE_OPEN = 2,\n\tETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT = 3,\n\tETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT = 4,\n\tETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH = 5,\n\tETHTOOL_A_CABLE_RESULT_CODE_NOISE = 6,\n\tETHTOOL_A_CABLE_RESULT_CODE_RESOLUTION_NOT_POSSIBLE = 7,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_STAT_EEE_WAKEUP = 0,\n\tETHTOOL_STAT_SKB_ALLOC_ERR = 1,\n\tETHTOOL_STAT_REFILL_ERR = 2,\n\tETHTOOL_XDP_REDIRECT = 3,\n\tETHTOOL_XDP_PASS = 4,\n\tETHTOOL_XDP_DROP = 5,\n\tETHTOOL_XDP_TX = 6,\n\tETHTOOL_XDP_TX_ERR = 7,\n\tETHTOOL_XDP_XMIT = 8,\n\tETHTOOL_XDP_XMIT_ERR = 9,\n\tETHTOOL_MAX_STATS = 10,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENTFS_SAVE_MODE = 65536,\n\tEVENTFS_SAVE_UID = 131072,\n\tEVENTFS_SAVE_GID = 262144,\n};\n\nenum {\n\tEVENT_CMD_COMPLETE = 0,\n\tEVENT_XFER_COMPLETE = 1,\n\tEVENT_DATA_COMPLETE = 2,\n\tEVENT_DATA_ERROR = 3,\n};\n\nenum {\n\tEVENT_CMD_RDY = 0,\n\tEVENT_XFER_COMPLETE___2 = 1,\n\tEVENT_NOTBUSY = 2,\n\tEVENT_DATA_ERROR___2 = 3,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_DISABLED = 32,\n\tEVENT_FILE_FL_TRIGGER_MODE = 64,\n\tEVENT_FILE_FL_TRIGGER_COND = 128,\n\tEVENT_FILE_FL_PID_FILTER = 256,\n\tEVENT_FILE_FL_WAS_ENABLED = 512,\n\tEVENT_FILE_FL_FREED = 1024,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEVENT_TRIGGER_FL_PROBE = 1,\n\tEVENT_TRIGGER_FL_COUNT = 2,\n};\n\nenum {\n\tEXT4_FC_REASON_XATTR = 0,\n\tEXT4_FC_REASON_CROSS_RENAME = 1,\n\tEXT4_FC_REASON_JOURNAL_FLAG_CHANGE = 2,\n\tEXT4_FC_REASON_NOMEM = 3,\n\tEXT4_FC_REASON_SWAP_BOOT = 4,\n\tEXT4_FC_REASON_RESIZE = 5,\n\tEXT4_FC_REASON_RENAME_DIR = 6,\n\tEXT4_FC_REASON_FALLOC_RANGE = 7,\n\tEXT4_FC_REASON_INODE_JOURNAL_DATA = 8,\n\tEXT4_FC_REASON_ENCRYPTED_FILENAME = 9,\n\tEXT4_FC_REASON_MIGRATE = 10,\n\tEXT4_FC_REASON_VERITY = 11,\n\tEXT4_FC_REASON_MOVE_EXT = 12,\n\tEXT4_FC_REASON_MAX = 13,\n};\n\nenum {\n\tEXT4_FC_STATUS_OK = 0,\n\tEXT4_FC_STATUS_INELIGIBLE = 1,\n\tEXT4_FC_STATUS_SKIPPED = 2,\n\tEXT4_FC_STATUS_FAILED = 3,\n};\n\nenum {\n\tEXT4_FLAGS_RESIZING = 0,\n\tEXT4_FLAGS_SHUTDOWN = 1,\n\tEXT4_FLAGS_BDEV_IS_DAX = 2,\n\tEXT4_FLAGS_EMERGENCY_RO = 3,\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nenum {\n\tEXT4_MF_MNTDIR_SAMPLED = 0,\n\tEXT4_MF_FC_INELIGIBLE = 1,\n\tEXT4_MF_JOURNAL_DESTROY = 2,\n};\n\nenum {\n\tEXT4_STATE_NEW = 0,\n\tEXT4_STATE_XATTR = 1,\n\tEXT4_STATE_NO_EXPAND = 2,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 3,\n\tEXT4_STATE_EXT_MIGRATE = 4,\n\tEXT4_STATE_NEWENTRY = 5,\n\tEXT4_STATE_MAY_INLINE_DATA = 6,\n\tEXT4_STATE_EXT_PRECACHED = 7,\n\tEXT4_STATE_LUSTRE_EA_INODE = 8,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 9,\n\tEXT4_STATE_FC_COMMITTING = 10,\n\tEXT4_STATE_FC_FLUSHING_DATA = 11,\n\tEXT4_STATE_ORPHAN_FILE = 12,\n};\n\nenum {\n\tEXYNOS_ASV_SUBSYS_ID_ARM = 0,\n\tEXYNOS_ASV_SUBSYS_ID_KFC = 1,\n\tEXYNOS_ASV_SUBSYS_ID_MAX = 2,\n};\n\nenum {\n\tFAN53526_CHIP_ID_01 = 1,\n};\n\nenum {\n\tFAN53526_CHIP_REV_08 = 8,\n};\n\nenum {\n\tFAN53555_CHIP_ID_00 = 0,\n\tFAN53555_CHIP_ID_01 = 1,\n\tFAN53555_CHIP_ID_02 = 2,\n\tFAN53555_CHIP_ID_03 = 3,\n\tFAN53555_CHIP_ID_04 = 4,\n\tFAN53555_CHIP_ID_05 = 5,\n\tFAN53555_CHIP_ID_08 = 8,\n};\n\nenum {\n\tFAN53555_CHIP_REV_00 = 3,\n\tFAN53555_CHIP_REV_13 = 15,\n};\n\nenum {\n\tFAN53555_VSEL_ID_0 = 0,\n\tFAN53555_VSEL_ID_1 = 1,\n};\n\nenum {\n\tFATTR4_CLONE_BLKSIZE = 77,\n\tFATTR4_SPACE_FREED = 78,\n\tFATTR4_CHANGE_ATTR_TYPE = 79,\n\tFATTR4_SEC_LABEL = 80,\n};\n\nenum {\n\tFATTR4_DIR_NOTIF_DELAY = 56,\n\tFATTR4_DIRENT_NOTIF_DELAY = 57,\n\tFATTR4_DACL = 58,\n\tFATTR4_SACL = 59,\n\tFATTR4_CHANGE_POLICY = 60,\n\tFATTR4_FS_STATUS = 61,\n\tFATTR4_FS_LAYOUT_TYPES = 62,\n\tFATTR4_LAYOUT_HINT = 63,\n\tFATTR4_LAYOUT_TYPES = 64,\n\tFATTR4_LAYOUT_BLKSIZE = 65,\n\tFATTR4_LAYOUT_ALIGNMENT = 66,\n\tFATTR4_FS_LOCATIONS_INFO = 67,\n\tFATTR4_MDSTHRESHOLD = 68,\n\tFATTR4_RETENTION_GET = 69,\n\tFATTR4_RETENTION_SET = 70,\n\tFATTR4_RETENTEVT_GET = 71,\n\tFATTR4_RETENTEVT_SET = 72,\n\tFATTR4_RETENTION_HOLD = 73,\n\tFATTR4_MODE_SET_MASKED = 74,\n\tFATTR4_SUPPATTR_EXCLCREAT = 75,\n\tFATTR4_FS_CHARSET_CAP = 76,\n};\n\nenum {\n\tFATTR4_MODE_UMASK = 81,\n};\n\nenum {\n\tFATTR4_OPEN_ARGUMENTS = 86,\n};\n\nenum {\n\tFATTR4_SUPPORTED_ATTRS = 0,\n\tFATTR4_TYPE = 1,\n\tFATTR4_FH_EXPIRE_TYPE = 2,\n\tFATTR4_CHANGE = 3,\n\tFATTR4_SIZE = 4,\n\tFATTR4_LINK_SUPPORT = 5,\n\tFATTR4_SYMLINK_SUPPORT = 6,\n\tFATTR4_NAMED_ATTR = 7,\n\tFATTR4_FSID = 8,\n\tFATTR4_UNIQUE_HANDLES = 9,\n\tFATTR4_LEASE_TIME = 10,\n\tFATTR4_RDATTR_ERROR = 11,\n\tFATTR4_ACL = 12,\n\tFATTR4_ACLSUPPORT = 13,\n\tFATTR4_ARCHIVE = 14,\n\tFATTR4_CANSETTIME = 15,\n\tFATTR4_CASE_INSENSITIVE = 16,\n\tFATTR4_CASE_PRESERVING = 17,\n\tFATTR4_CHOWN_RESTRICTED = 18,\n\tFATTR4_FILEHANDLE = 19,\n\tFATTR4_FILEID = 20,\n\tFATTR4_FILES_AVAIL = 21,\n\tFATTR4_FILES_FREE = 22,\n\tFATTR4_FILES_TOTAL = 23,\n\tFATTR4_FS_LOCATIONS = 24,\n\tFATTR4_HIDDEN = 25,\n\tFATTR4_HOMOGENEOUS = 26,\n\tFATTR4_MAXFILESIZE = 27,\n\tFATTR4_MAXLINK = 28,\n\tFATTR4_MAXNAME = 29,\n\tFATTR4_MAXREAD = 30,\n\tFATTR4_MAXWRITE = 31,\n\tFATTR4_MIMETYPE = 32,\n\tFATTR4_MODE = 33,\n\tFATTR4_NO_TRUNC = 34,\n\tFATTR4_NUMLINKS = 35,\n\tFATTR4_OWNER = 36,\n\tFATTR4_OWNER_GROUP = 37,\n\tFATTR4_QUOTA_AVAIL_HARD = 38,\n\tFATTR4_QUOTA_AVAIL_SOFT = 39,\n\tFATTR4_QUOTA_USED = 40,\n\tFATTR4_RAWDEV = 41,\n\tFATTR4_SPACE_AVAIL = 42,\n\tFATTR4_SPACE_FREE = 43,\n\tFATTR4_SPACE_TOTAL = 44,\n\tFATTR4_SPACE_USED = 45,\n\tFATTR4_SYSTEM = 46,\n\tFATTR4_TIME_ACCESS = 47,\n\tFATTR4_TIME_ACCESS_SET = 48,\n\tFATTR4_TIME_BACKUP = 49,\n\tFATTR4_TIME_CREATE = 50,\n\tFATTR4_TIME_DELTA = 51,\n\tFATTR4_TIME_METADATA = 52,\n\tFATTR4_TIME_MODIFY = 53,\n\tFATTR4_TIME_MODIFY_SET = 54,\n\tFATTR4_MOUNTED_ON_FILEID = 55,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_ACCESS = 84,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_MODIFY = 85,\n};\n\nenum {\n\tFATTR4_XATTR_SUPPORT = 82,\n};\n\nenum {\n\tFBCON_LOGO_CANSHOW = -1,\n\tFBCON_LOGO_DRAW = -2,\n\tFBCON_LOGO_DONTSHOW = -3,\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nenum {\n\tFIB6_NO_SERNUM_CHANGE = 0,\n};\n\nenum {\n\tFILEID_HIGH_OFF = 0,\n\tFILEID_LOW_OFF = 1,\n\tFILE_I_TYPE_OFF = 2,\n\tEMBED_FH_OFF = 3,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_RDYN_STRING = 3,\n\tFILTER_PTR_STRING = 4,\n\tFILTER_TRACE_FN = 5,\n\tFILTER_CPUMASK = 6,\n\tFILTER_COMM = 7,\n\tFILTER_CPU = 8,\n\tFILTER_STACKTRACE = 9,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_MISSING_BRACE_OPEN = 5,\n\tFILT_ERR_MISSING_BRACE_CLOSE = 6,\n\tFILT_ERR_OPERAND_TOO_LONG = 7,\n\tFILT_ERR_EXPECT_STRING = 8,\n\tFILT_ERR_EXPECT_DIGIT = 9,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 10,\n\tFILT_ERR_FIELD_NOT_FOUND = 11,\n\tFILT_ERR_ILLEGAL_INTVAL = 12,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 13,\n\tFILT_ERR_TOO_MANY_PREDS = 14,\n\tFILT_ERR_INVALID_FILTER = 15,\n\tFILT_ERR_INVALID_CPULIST = 16,\n\tFILT_ERR_IP_FIELD_ONLY = 17,\n\tFILT_ERR_INVALID_VALUE = 18,\n\tFILT_ERR_NO_FUNCTION = 19,\n\tFILT_ERR_ERRNO = 20,\n\tFILT_ERR_NO_FILTER = 21,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\nenum {\n\tFRA_UNSPEC = 0,\n\tFRA_DST = 1,\n\tFRA_SRC = 2,\n\tFRA_IIFNAME = 3,\n\tFRA_GOTO = 4,\n\tFRA_UNUSED2 = 5,\n\tFRA_PRIORITY = 6,\n\tFRA_UNUSED3 = 7,\n\tFRA_UNUSED4 = 8,\n\tFRA_UNUSED5 = 9,\n\tFRA_FWMARK = 10,\n\tFRA_FLOW = 11,\n\tFRA_TUN_ID = 12,\n\tFRA_SUPPRESS_IFGROUP = 13,\n\tFRA_SUPPRESS_PREFIXLEN = 14,\n\tFRA_TABLE = 15,\n\tFRA_FWMASK = 16,\n\tFRA_OIFNAME = 17,\n\tFRA_PAD = 18,\n\tFRA_L3MDEV = 19,\n\tFRA_UID_RANGE = 20,\n\tFRA_PROTOCOL = 21,\n\tFRA_IP_PROTO = 22,\n\tFRA_SPORT_RANGE = 23,\n\tFRA_DPORT_RANGE = 24,\n\tFRA_DSCP = 25,\n\tFRA_FLOWLABEL = 26,\n\tFRA_FLOWLABEL_MASK = 27,\n\tFRA_SPORT_MASK = 28,\n\tFRA_DPORT_MASK = 29,\n\tFRA_DSCP_MASK = 30,\n\t__FRA_MAX = 31,\n};\n\nenum {\n\tFR_ACT_UNSPEC = 0,\n\tFR_ACT_TO_TBL = 1,\n\tFR_ACT_GOTO = 2,\n\tFR_ACT_NOP = 3,\n\tFR_ACT_RES3 = 4,\n\tFR_ACT_RES4 = 5,\n\tFR_ACT_BLACKHOLE = 6,\n\tFR_ACT_UNREACHABLE = 7,\n\tFR_ACT_PROHIBIT = 8,\n\t__FR_ACT_MAX = 9,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFUNC_CAN0_a = 0,\n\tFUNC_CAN0_b = 1,\n\tFUNC_CAN1 = 2,\n\tFUNC_CLKMON = 3,\n\tFUNC_NONE = 4,\n\tFUNC_FAN = 5,\n\tFUNC_FC = 6,\n\tFUNC_FC0_a = 7,\n\tFUNC_FC0_b = 8,\n\tFUNC_FC0_c = 9,\n\tFUNC_FC1_a = 10,\n\tFUNC_FC1_b = 11,\n\tFUNC_FC1_c = 12,\n\tFUNC_FC2_a = 13,\n\tFUNC_FC2_b = 14,\n\tFUNC_FC3_a = 15,\n\tFUNC_FC3_b = 16,\n\tFUNC_FC3_c = 17,\n\tFUNC_FC4_a = 18,\n\tFUNC_FC4_b = 19,\n\tFUNC_FC4_c = 20,\n\tFUNC_FC_SHRD = 21,\n\tFUNC_FC_SHRD0 = 22,\n\tFUNC_FC_SHRD1 = 23,\n\tFUNC_FC_SHRD2 = 24,\n\tFUNC_FC_SHRD3 = 25,\n\tFUNC_FC_SHRD4 = 26,\n\tFUNC_FC_SHRD5 = 27,\n\tFUNC_FC_SHRD6 = 28,\n\tFUNC_FC_SHRD7 = 29,\n\tFUNC_FC_SHRD8 = 30,\n\tFUNC_FC_SHRD9 = 31,\n\tFUNC_FC_SHRD10 = 32,\n\tFUNC_FC_SHRD11 = 33,\n\tFUNC_FC_SHRD12 = 34,\n\tFUNC_FC_SHRD13 = 35,\n\tFUNC_FC_SHRD14 = 36,\n\tFUNC_FC_SHRD15 = 37,\n\tFUNC_FC_SHRD16 = 38,\n\tFUNC_FC_SHRD17 = 39,\n\tFUNC_FC_SHRD18 = 40,\n\tFUNC_FC_SHRD19 = 41,\n\tFUNC_FC_SHRD20 = 42,\n\tFUNC_FUSA = 43,\n\tFUNC_GPIO = 44,\n\tFUNC_I2C = 45,\n\tFUNC_I2C_Sa = 46,\n\tFUNC_IB_TRG_a = 47,\n\tFUNC_IB_TRG_b = 48,\n\tFUNC_IB_TRG_c = 49,\n\tFUNC_IRQ0 = 50,\n\tFUNC_IRQ_IN_a = 51,\n\tFUNC_IRQ_IN_b = 52,\n\tFUNC_IRQ_IN_c = 53,\n\tFUNC_IRQ0_IN = 54,\n\tFUNC_IRQ_OUT_a = 55,\n\tFUNC_IRQ_OUT_b = 56,\n\tFUNC_IRQ_OUT_c = 57,\n\tFUNC_IRQ0_OUT = 58,\n\tFUNC_IRQ1 = 59,\n\tFUNC_IRQ1_IN = 60,\n\tFUNC_IRQ1_OUT = 61,\n\tFUNC_IRQ2 = 62,\n\tFUNC_IRQ3 = 63,\n\tFUNC_IRQ4 = 64,\n\tFUNC_EXT_IRQ = 65,\n\tFUNC_MACLED = 66,\n\tFUNC_MIIM = 67,\n\tFUNC_MIIM_a = 68,\n\tFUNC_MIIM_b = 69,\n\tFUNC_MIIM_c = 70,\n\tFUNC_MIIM_Sa = 71,\n\tFUNC_MIIM_Sb = 72,\n\tFUNC_MIIM_IRQ = 73,\n\tFUNC_OB_TRG = 74,\n\tFUNC_OB_TRG_a = 75,\n\tFUNC_OB_TRG_b = 76,\n\tFUNC_PHY_LED = 77,\n\tFUNC_PHY_DBG = 78,\n\tFUNC_PCI_WAKE = 79,\n\tFUNC_MD = 80,\n\tFUNC_PCIE_PERST = 81,\n\tFUNC_PTP0 = 82,\n\tFUNC_PTP1 = 83,\n\tFUNC_PTP2 = 84,\n\tFUNC_PTP3 = 85,\n\tFUNC_PTPSYNC_0 = 86,\n\tFUNC_PTPSYNC_1 = 87,\n\tFUNC_PTPSYNC_2 = 88,\n\tFUNC_PTPSYNC_3 = 89,\n\tFUNC_PTPSYNC_4 = 90,\n\tFUNC_PTPSYNC_5 = 91,\n\tFUNC_PTPSYNC_6 = 92,\n\tFUNC_PTPSYNC_7 = 93,\n\tFUNC_PWM = 94,\n\tFUNC_PWM_a = 95,\n\tFUNC_PWM_b = 96,\n\tFUNC_QSPI1 = 97,\n\tFUNC_QSPI2 = 98,\n\tFUNC_R = 99,\n\tFUNC_RECO_a = 100,\n\tFUNC_RECO_b = 101,\n\tFUNC_RECO_CLK = 102,\n\tFUNC_SD = 103,\n\tFUNC_SFP = 104,\n\tFUNC_SFP_SD = 105,\n\tFUNC_SG0 = 106,\n\tFUNC_SG1 = 107,\n\tFUNC_SG2 = 108,\n\tFUNC_SPI = 109,\n\tFUNC_SGPIO_a = 110,\n\tFUNC_SGPIO_b = 111,\n\tFUNC_SI = 112,\n\tFUNC_SI2 = 113,\n\tFUNC_SI_Sa = 114,\n\tFUNC_SYNCE = 115,\n\tFUNC_TACHO = 116,\n\tFUNC_TACHO_a = 117,\n\tFUNC_TACHO_b = 118,\n\tFUNC_TWI = 119,\n\tFUNC_TWI2 = 120,\n\tFUNC_TWI3 = 121,\n\tFUNC_TWI_SCL_M = 122,\n\tFUNC_TWI_SLC_GATE = 123,\n\tFUNC_TWI_SLC_GATE_AD = 124,\n\tFUNC_UART = 125,\n\tFUNC_UART2 = 126,\n\tFUNC_UART3 = 127,\n\tFUNC_USB_H_a = 128,\n\tFUNC_USB_H_b = 129,\n\tFUNC_USB_H_c = 130,\n\tFUNC_USB_S_a = 131,\n\tFUNC_USB_S_b = 132,\n\tFUNC_USB_S_c = 133,\n\tFUNC_USB_POWER = 134,\n\tFUNC_USB2PHY_RST = 135,\n\tFUNC_USB_OVER_DETECT = 136,\n\tFUNC_USB_ULPI = 137,\n\tFUNC_PLL_STAT = 138,\n\tFUNC_EMMC = 139,\n\tFUNC_EMMC_SD = 140,\n\tFUNC_REF_CLK = 141,\n\tFUNC_RCVRD_CLK = 142,\n\tFUNC_RGMII = 143,\n\tFUNC_MAX = 144,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tFW_DO_IDLE_SLEEP = 0,\n\tFW_DO_IDLE_AFTR = 1,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tGP_LAST = 154,\n\tPIN_CLKOUT = 155,\n\tPIN_CS0 = 156,\n\tPIN_CS1_A26 = 157,\n};\n\nenum {\n\tGP_LAST___2 = 217,\n\tPIN_ASEBRK_N_ACK = 218,\n\tPIN_TCK = 219,\n\tPIN_TDI = 220,\n\tPIN_TMS = 221,\n\tPIN_TRST_N = 222,\n};\n\nenum {\n\tGP_LAST___3 = 249,\n\tPIN_ASEBRK_N_ACK___2 = 250,\n\tPIN_AVS1 = 251,\n\tPIN_AVS2 = 252,\n\tPIN_TCK___2 = 253,\n\tPIN_TDI___2 = 254,\n\tPIN_TMS___2 = 255,\n\tPIN_TRST_N___2 = 256,\n};\n\nenum {\n\tGP_LAST___4 = 191,\n\tPIN_ASEBRK_N_ACK___3 = 192,\n\tPIN_IIC0_SDA = 193,\n\tPIN_IIC0_SCL = 194,\n\tPIN_IIC3_SDA = 195,\n\tPIN_IIC3_SCL = 196,\n\tPIN_TCK___3 = 197,\n\tPIN_TDI___3 = 198,\n\tPIN_TMS___3 = 199,\n\tPIN_TRST_N___3 = 200,\n};\n\nenum {\n\tGP_LAST___5 = 200,\n\tPIN_ASEBRK_N_ACK___4 = 201,\n\tPIN_D0 = 202,\n\tPIN_D1 = 203,\n\tPIN_D2 = 204,\n\tPIN_D3 = 205,\n\tPIN_D4 = 206,\n\tPIN_D5 = 207,\n\tPIN_D6 = 208,\n\tPIN_D7 = 209,\n\tPIN_D8 = 210,\n\tPIN_D9 = 211,\n\tPIN_D10 = 212,\n\tPIN_D11 = 213,\n\tPIN_D12 = 214,\n\tPIN_D13 = 215,\n\tPIN_D14 = 216,\n\tPIN_D15 = 217,\n\tPIN_PRESETOUT_N = 218,\n\tPIN_TCK___4 = 219,\n\tPIN_TDI___4 = 220,\n\tPIN_TDO = 221,\n\tPIN_TMS___4 = 222,\n\tPIN_TRST_N___4 = 223,\n};\n\nenum {\n\tGP_LAST___6 = 381,\n\tPIN_DU0_DOTCLKIN = 382,\n\tPIN_DU0_DOTCLKOUT = 383,\n\tPIN_DU1_DOTCLKIN = 384,\n\tPIN_DU1_DOTCLKOUT = 385,\n\tPIN_EDBGREQ = 386,\n\tPIN_TCK___5 = 387,\n\tPIN_TDI___5 = 388,\n\tPIN_TMS___5 = 389,\n\tPIN_TRST_N___5 = 390,\n};\n\nenum {\n\tGP_LAST___7 = 191,\n\tPIN_ASEBRK_N_ACK___5 = 192,\n\tPIN_NMI = 193,\n\tPIN_PRESETOUT_N___2 = 194,\n\tPIN_TCK___6 = 195,\n\tPIN_TDI___6 = 196,\n\tPIN_TDO___2 = 197,\n\tPIN_TMS___6 = 198,\n\tPIN_TRST_N___6 = 199,\n};\n\nenum {\n\tGSSX_NULL = 0,\n\tGSSX_INDICATE_MECHS = 1,\n\tGSSX_GET_CALL_CONTEXT = 2,\n\tGSSX_IMPORT_AND_CANON_NAME = 3,\n\tGSSX_EXPORT_CRED = 4,\n\tGSSX_IMPORT_CRED = 5,\n\tGSSX_ACQUIRE_CRED = 6,\n\tGSSX_STORE_CRED = 7,\n\tGSSX_INIT_SEC_CONTEXT = 8,\n\tGSSX_ACCEPT_SEC_CONTEXT = 9,\n\tGSSX_RELEASE_HANDLE = 10,\n\tGSSX_GET_MIC = 11,\n\tGSSX_VERIFY = 12,\n\tGSSX_WRAP = 13,\n\tGSSX_UNWRAP = 14,\n\tGSSX_WRAP_SIZE_LIMIT = 15,\n};\n\nenum {\n\tG_SAI1 = 0,\n\tG_SAI2 = 1,\n\tG_SAI3 = 2,\n\tG_SAI4 = 3,\n\tG_SPI1 = 4,\n\tG_SPI2 = 5,\n\tG_SPI3 = 6,\n\tG_SPI4 = 7,\n\tG_SPI5 = 8,\n\tG_SPI6 = 9,\n\tG_SPDIF = 10,\n\tG_I2C1 = 11,\n\tG_I2C2 = 12,\n\tG_I2C3 = 13,\n\tG_I2C4 = 14,\n\tG_I2C5 = 15,\n\tG_I2C6 = 16,\n\tG_USART2 = 17,\n\tG_UART4 = 18,\n\tG_USART3 = 19,\n\tG_UART5 = 20,\n\tG_USART1 = 21,\n\tG_USART6 = 22,\n\tG_UART7 = 23,\n\tG_UART8 = 24,\n\tG_LPTIM1 = 25,\n\tG_LPTIM2 = 26,\n\tG_LPTIM3 = 27,\n\tG_LPTIM4 = 28,\n\tG_LPTIM5 = 29,\n\tG_LTDC = 30,\n\tG_DSI = 31,\n\tG_QSPI = 32,\n\tG_FMC = 33,\n\tG_SDMMC1 = 34,\n\tG_SDMMC2 = 35,\n\tG_SDMMC3 = 36,\n\tG_USBO = 37,\n\tG_USBPHY = 38,\n\tG_RNG1 = 39,\n\tG_RNG2 = 40,\n\tG_FDCAN = 41,\n\tG_DAC12 = 42,\n\tG_CEC = 43,\n\tG_ADC12 = 44,\n\tG_GPU = 45,\n\tG_STGEN = 46,\n\tG_DFSDM = 47,\n\tG_ADFSDM = 48,\n\tG_TIM2 = 49,\n\tG_TIM3 = 50,\n\tG_TIM4 = 51,\n\tG_TIM5 = 52,\n\tG_TIM6 = 53,\n\tG_TIM7 = 54,\n\tG_TIM12 = 55,\n\tG_TIM13 = 56,\n\tG_TIM14 = 57,\n\tG_MDIO = 58,\n\tG_TIM1 = 59,\n\tG_TIM8 = 60,\n\tG_TIM15 = 61,\n\tG_TIM16 = 62,\n\tG_TIM17 = 63,\n\tG_SYSCFG = 64,\n\tG_VREF = 65,\n\tG_TMPSENS = 66,\n\tG_PMBCTRL = 67,\n\tG_HDP = 68,\n\tG_IWDG2 = 69,\n\tG_STGENRO = 70,\n\tG_DMA1 = 71,\n\tG_DMA2 = 72,\n\tG_DMAMUX = 73,\n\tG_DCMI = 74,\n\tG_CRYP2 = 75,\n\tG_HASH2 = 76,\n\tG_CRC2 = 77,\n\tG_HSEM = 78,\n\tG_IPCC = 79,\n\tG_GPIOA = 80,\n\tG_GPIOB = 81,\n\tG_GPIOC = 82,\n\tG_GPIOD = 83,\n\tG_GPIOE = 84,\n\tG_GPIOF = 85,\n\tG_GPIOG = 86,\n\tG_GPIOH = 87,\n\tG_GPIOI = 88,\n\tG_GPIOJ = 89,\n\tG_GPIOK = 90,\n\tG_MDMA = 91,\n\tG_ETHCK = 92,\n\tG_ETHTX = 93,\n\tG_ETHRX = 94,\n\tG_ETHMAC = 95,\n\tG_CRC1 = 96,\n\tG_USBH = 97,\n\tG_ETHSTP = 98,\n\tG_RTCAPB = 99,\n\tG_TZC1 = 100,\n\tG_TZC2 = 101,\n\tG_TZPC = 102,\n\tG_IWDG1 = 103,\n\tG_BSEC = 104,\n\tG_GPIOZ = 105,\n\tG_CRYP1 = 106,\n\tG_HASH1 = 107,\n\tG_BKPSRAM = 108,\n\tG_DDRPERFM = 109,\n\tG_LAST = 110,\n};\n\nenum {\n\tHANDSHAKE_A_ACCEPT_SOCKFD = 1,\n\tHANDSHAKE_A_ACCEPT_HANDLER_CLASS = 2,\n\tHANDSHAKE_A_ACCEPT_MESSAGE_TYPE = 3,\n\tHANDSHAKE_A_ACCEPT_TIMEOUT = 4,\n\tHANDSHAKE_A_ACCEPT_AUTH_MODE = 5,\n\tHANDSHAKE_A_ACCEPT_PEER_IDENTITY = 6,\n\tHANDSHAKE_A_ACCEPT_CERTIFICATE = 7,\n\tHANDSHAKE_A_ACCEPT_PEERNAME = 8,\n\tHANDSHAKE_A_ACCEPT_KEYRING = 9,\n\t__HANDSHAKE_A_ACCEPT_MAX = 10,\n\tHANDSHAKE_A_ACCEPT_MAX = 9,\n};\n\nenum {\n\tHANDSHAKE_A_DONE_STATUS = 1,\n\tHANDSHAKE_A_DONE_SOCKFD = 2,\n\tHANDSHAKE_A_DONE_REMOTE_AUTH = 3,\n\t__HANDSHAKE_A_DONE_MAX = 4,\n\tHANDSHAKE_A_DONE_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_A_X509_CERT = 1,\n\tHANDSHAKE_A_X509_PRIVKEY = 2,\n\t__HANDSHAKE_A_X509_MAX = 3,\n\tHANDSHAKE_A_X509_MAX = 2,\n};\n\nenum {\n\tHANDSHAKE_CMD_READY = 1,\n\tHANDSHAKE_CMD_ACCEPT = 2,\n\tHANDSHAKE_CMD_DONE = 3,\n\t__HANDSHAKE_CMD_MAX = 4,\n\tHANDSHAKE_CMD_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_NLGRP_NONE = 0,\n\tHANDSHAKE_NLGRP_TLSHD = 1,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHI3620_CTRL = 0,\n\tERROR_CTRL = 1,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK = 0,\n\tHOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 1,\n};\n\nenum {\n\tHOST1X_OPCODE_SETCLASS = 0,\n\tHOST1X_OPCODE_INCR = 1,\n\tHOST1X_OPCODE_NONINCR = 2,\n\tHOST1X_OPCODE_MASK = 3,\n\tHOST1X_OPCODE_IMM = 4,\n\tHOST1X_OPCODE_RESTART = 5,\n\tHOST1X_OPCODE_GATHER = 6,\n\tHOST1X_OPCODE_SETSTRMID = 7,\n\tHOST1X_OPCODE_SETAPPID = 8,\n\tHOST1X_OPCODE_SETPYLD = 9,\n\tHOST1X_OPCODE_INCR_W = 10,\n\tHOST1X_OPCODE_NONINCR_W = 11,\n\tHOST1X_OPCODE_GATHER_W = 12,\n\tHOST1X_OPCODE_RESTART_W = 13,\n\tHOST1X_OPCODE_EXTEND = 14,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHSE = 0,\n\tHSI = 1,\n\tMSI = 2,\n\tLSE = 3,\n\tLSI = 4,\n\tHSE_DIV2 = 5,\n\tICN_HS_MCU = 6,\n\tICN_LS_MCU = 7,\n\tICN_SDMMC = 8,\n\tICN_DDR = 9,\n\tICN_DISPLAY = 10,\n\tICN_HSL = 11,\n\tICN_NIC = 12,\n\tFLEXGEN_07 = 13,\n\tFLEXGEN_08 = 14,\n\tFLEXGEN_09 = 15,\n\tFLEXGEN_10 = 16,\n\tFLEXGEN_11 = 17,\n\tFLEXGEN_12 = 18,\n\tFLEXGEN_13 = 19,\n\tFLEXGEN_14 = 20,\n\tFLEXGEN_16 = 21,\n\tFLEXGEN_17 = 22,\n\tFLEXGEN_18 = 23,\n\tFLEXGEN_19 = 24,\n\tFLEXGEN_20 = 25,\n\tFLEXGEN_21 = 26,\n\tFLEXGEN_22 = 27,\n\tFLEXGEN_23 = 28,\n\tFLEXGEN_24 = 29,\n\tFLEXGEN_25 = 30,\n\tFLEXGEN_26 = 31,\n\tFLEXGEN_27 = 32,\n\tFLEXGEN_29 = 33,\n\tFLEXGEN_30 = 34,\n\tFLEXGEN_31 = 35,\n\tFLEXGEN_33 = 36,\n\tFLEXGEN_36 = 37,\n\tFLEXGEN_37 = 38,\n\tFLEXGEN_38 = 39,\n\tFLEXGEN_39 = 40,\n\tFLEXGEN_40 = 41,\n\tFLEXGEN_41 = 42,\n\tFLEXGEN_42 = 43,\n\tFLEXGEN_43 = 44,\n\tFLEXGEN_44 = 45,\n\tFLEXGEN_45 = 46,\n\tFLEXGEN_46 = 47,\n\tFLEXGEN_47 = 48,\n\tFLEXGEN_48 = 49,\n\tFLEXGEN_50 = 50,\n\tFLEXGEN_51 = 51,\n\tFLEXGEN_52 = 52,\n\tFLEXGEN_53 = 53,\n\tFLEXGEN_54 = 54,\n\tFLEXGEN_55 = 55,\n\tFLEXGEN_56 = 56,\n\tFLEXGEN_57 = 57,\n\tFLEXGEN_58 = 58,\n\tFLEXGEN_61 = 59,\n\tFLEXGEN_62 = 60,\n\tFLEXGEN_63 = 61,\n\tICN_APB1 = 62,\n\tICN_APB2 = 63,\n\tICN_APB3 = 64,\n\tICN_APB4 = 65,\n\tICN_APB5 = 66,\n\tICN_APBDBG = 67,\n\tTIMG1 = 68,\n\tTIMG2 = 69,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tHW_BREAKPOINT_EMPTY = 0,\n\tHW_BREAKPOINT_R = 1,\n\tHW_BREAKPOINT_W = 2,\n\tHW_BREAKPOINT_RW = 3,\n\tHW_BREAKPOINT_X = 4,\n\tHW_BREAKPOINT_INVALID = 7,\n};\n\nenum {\n\tHW_BREAKPOINT_LEN_1 = 1,\n\tHW_BREAKPOINT_LEN_2 = 2,\n\tHW_BREAKPOINT_LEN_3 = 3,\n\tHW_BREAKPOINT_LEN_4 = 4,\n\tHW_BREAKPOINT_LEN_5 = 5,\n\tHW_BREAKPOINT_LEN_6 = 6,\n\tHW_BREAKPOINT_LEN_7 = 7,\n\tHW_BREAKPOINT_LEN_8 = 8,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tICQ_EXITED = 4,\n\tICQ_DESTROYED = 8,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIFAL_ADDRESS = 1,\n\tIFAL_LABEL = 2,\n\t__IFAL_MAX = 3,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_CAN_CTRLMODE_UNSPEC = 0,\n\tIFLA_CAN_CTRLMODE_SUPPORTED = 1,\n\t__IFLA_CAN_CTRLMODE = 2,\n\tIFLA_CAN_CTRLMODE_MAX = 1,\n};\n\nenum {\n\tIFLA_CAN_PWM_UNSPEC = 0,\n\tIFLA_CAN_PWM_PWMS_MIN = 1,\n\tIFLA_CAN_PWM_PWMS_MAX = 2,\n\tIFLA_CAN_PWM_PWML_MIN = 3,\n\tIFLA_CAN_PWM_PWML_MAX = 4,\n\tIFLA_CAN_PWM_PWMO_MIN = 5,\n\tIFLA_CAN_PWM_PWMO_MAX = 6,\n\tIFLA_CAN_PWM_PWMS = 7,\n\tIFLA_CAN_PWM_PWML = 8,\n\tIFLA_CAN_PWM_PWMO = 9,\n\t__IFLA_CAN_PWM = 10,\n\tIFLA_CAN_PWM_MAX = 9,\n};\n\nenum {\n\tIFLA_CAN_TDC_UNSPEC = 0,\n\tIFLA_CAN_TDC_TDCV_MIN = 1,\n\tIFLA_CAN_TDC_TDCV_MAX = 2,\n\tIFLA_CAN_TDC_TDCO_MIN = 3,\n\tIFLA_CAN_TDC_TDCO_MAX = 4,\n\tIFLA_CAN_TDC_TDCF_MIN = 5,\n\tIFLA_CAN_TDC_TDCF_MAX = 6,\n\tIFLA_CAN_TDC_TDCV = 7,\n\tIFLA_CAN_TDC_TDCO = 8,\n\tIFLA_CAN_TDC_TDCF = 9,\n\t__IFLA_CAN_TDC = 10,\n\tIFLA_CAN_TDC_MAX = 9,\n};\n\nenum {\n\tIFLA_CAN_UNSPEC = 0,\n\tIFLA_CAN_BITTIMING = 1,\n\tIFLA_CAN_BITTIMING_CONST = 2,\n\tIFLA_CAN_CLOCK = 3,\n\tIFLA_CAN_STATE = 4,\n\tIFLA_CAN_CTRLMODE = 5,\n\tIFLA_CAN_RESTART_MS = 6,\n\tIFLA_CAN_RESTART = 7,\n\tIFLA_CAN_BERR_COUNTER = 8,\n\tIFLA_CAN_DATA_BITTIMING = 9,\n\tIFLA_CAN_DATA_BITTIMING_CONST = 10,\n\tIFLA_CAN_TERMINATION = 11,\n\tIFLA_CAN_TERMINATION_CONST = 12,\n\tIFLA_CAN_BITRATE_CONST = 13,\n\tIFLA_CAN_DATA_BITRATE_CONST = 14,\n\tIFLA_CAN_BITRATE_MAX = 15,\n\tIFLA_CAN_TDC = 16,\n\tIFLA_CAN_CTRLMODE_EXT = 17,\n\tIFLA_CAN_XL_DATA_BITTIMING = 18,\n\tIFLA_CAN_XL_DATA_BITTIMING_CONST = 19,\n\tIFLA_CAN_XL_DATA_BITRATE_CONST = 20,\n\tIFLA_CAN_XL_TDC = 21,\n\tIFLA_CAN_XL_PWM = 22,\n\t__IFLA_CAN_MAX = 23,\n\tIFLA_CAN_MAX = 22,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET6_UNSPEC = 0,\n\tIFLA_INET6_FLAGS = 1,\n\tIFLA_INET6_CONF = 2,\n\tIFLA_INET6_STATS = 3,\n\tIFLA_INET6_MCAST = 4,\n\tIFLA_INET6_CACHEINFO = 5,\n\tIFLA_INET6_ICMP6STATS = 6,\n\tIFLA_INET6_TOKEN = 7,\n\tIFLA_INET6_ADDR_GEN_MODE = 8,\n\tIFLA_INET6_RA_MTU = 9,\n\t__IFLA_INET6_MAX = 10,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_ACT_NONE = -1,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tIF_PORT_UNKNOWN = 0,\n\tIF_PORT_10BASE2 = 1,\n\tIF_PORT_10BASET = 2,\n\tIF_PORT_AUI = 3,\n\tIF_PORT_100BASET = 4,\n\tIF_PORT_100BASETX = 5,\n\tIF_PORT_100BASEFX = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nenum {\n\tIMX_TIMER1MS = 224,\n\tIMX_P0PHYCR = 376,\n\tIMX_P0PHYCR_TEST_PDDQ = 1048576,\n\tIMX_P0PHYCR_CR_READ = 524288,\n\tIMX_P0PHYCR_CR_WRITE = 262144,\n\tIMX_P0PHYCR_CR_CAP_DATA = 131072,\n\tIMX_P0PHYCR_CR_CAP_ADDR = 65536,\n\tIMX_P0PHYSR = 380,\n\tIMX_P0PHYSR_CR_ACK = 262144,\n\tIMX_P0PHYSR_CR_DATA_OUT = 65535,\n\tIMX_LANE0_OUT_STAT = 8195,\n\tIMX_LANE0_OUT_STAT_RX_PLL_STATE = 2,\n\tIMX_CLOCK_RESET = 32575,\n\tIMX_CLOCK_RESET_RESET = 1,\n\tIMX8QM_SATA_AHCI_PTC = 200,\n\tIMX8QM_SATA_AHCI_PTC_RXWM_MASK = 127,\n\tIMX8QM_SATA_AHCI_PTC_RXWM = 41,\n};\n\nenum {\n\tINET6_IFADDR_STATE_PREDAD = 0,\n\tINET6_IFADDR_STATE_DAD = 1,\n\tINET6_IFADDR_STATE_POSTDAD = 2,\n\tINET6_IFADDR_STATE_ERRDAD = 3,\n\tINET6_IFADDR_STATE_DEAD = 4,\n};\n\nenum {\n\tINET_DIAG_BC_NOP = 0,\n\tINET_DIAG_BC_JMP = 1,\n\tINET_DIAG_BC_S_GE = 2,\n\tINET_DIAG_BC_S_LE = 3,\n\tINET_DIAG_BC_D_GE = 4,\n\tINET_DIAG_BC_D_LE = 5,\n\tINET_DIAG_BC_AUTO = 6,\n\tINET_DIAG_BC_S_COND = 7,\n\tINET_DIAG_BC_D_COND = 8,\n\tINET_DIAG_BC_DEV_COND = 9,\n\tINET_DIAG_BC_MARK_COND = 10,\n\tINET_DIAG_BC_S_EQ = 11,\n\tINET_DIAG_BC_D_EQ = 12,\n\tINET_DIAG_BC_CGROUP_COND = 13,\n};\n\nenum {\n\tINET_DIAG_NONE = 0,\n\tINET_DIAG_MEMINFO = 1,\n\tINET_DIAG_INFO = 2,\n\tINET_DIAG_VEGASINFO = 3,\n\tINET_DIAG_CONG = 4,\n\tINET_DIAG_TOS = 5,\n\tINET_DIAG_TCLASS = 6,\n\tINET_DIAG_SKMEMINFO = 7,\n\tINET_DIAG_SHUTDOWN = 8,\n\tINET_DIAG_DCTCPINFO = 9,\n\tINET_DIAG_PROTOCOL = 10,\n\tINET_DIAG_SKV6ONLY = 11,\n\tINET_DIAG_LOCALS = 12,\n\tINET_DIAG_PEERS = 13,\n\tINET_DIAG_PAD = 14,\n\tINET_DIAG_MARK = 15,\n\tINET_DIAG_BBRINFO = 16,\n\tINET_DIAG_CLASS_ID = 17,\n\tINET_DIAG_MD5SIG = 18,\n\tINET_DIAG_ULP_INFO = 19,\n\tINET_DIAG_SK_BPF_STORAGES = 20,\n\tINET_DIAG_CGROUP_ID = 21,\n\tINET_DIAG_SOCKOPT = 22,\n\t__INET_DIAG_MAX = 23,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINET_ULP_INFO_UNSPEC = 0,\n\tINET_ULP_INFO_NAME = 1,\n\tINET_ULP_INFO_TLS = 2,\n\tINET_ULP_INFO_MPTCP = 3,\n\t__INET_ULP_INFO_MAX = 4,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINTFC_FLASH_STATUS = 255,\n\tINTFC_ERASED = 134217728,\n\tINTFC_OOB_VALID = 268435456,\n\tINTFC_CACHE_VALID = 536870912,\n\tINTFC_FLASH_READY = 1073741824,\n\tINTFC_CTLR_READY = 2147483648,\n};\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tIOAM6_ATTR_UNSPEC = 0,\n\tIOAM6_ATTR_NS_ID = 1,\n\tIOAM6_ATTR_NS_DATA = 2,\n\tIOAM6_ATTR_NS_DATA_WIDE = 3,\n\tIOAM6_ATTR_SC_ID = 4,\n\tIOAM6_ATTR_SC_DATA = 5,\n\tIOAM6_ATTR_SC_NONE = 6,\n\tIOAM6_ATTR_PAD = 7,\n\t__IOAM6_ATTR_MAX = 8,\n};\n\nenum {\n\tIOAM6_CMD_UNSPEC = 0,\n\tIOAM6_CMD_ADD_NAMESPACE = 1,\n\tIOAM6_CMD_DEL_NAMESPACE = 2,\n\tIOAM6_CMD_DUMP_NAMESPACES = 3,\n\tIOAM6_CMD_ADD_SCHEMA = 4,\n\tIOAM6_CMD_DEL_SCHEMA = 5,\n\tIOAM6_CMD_DUMP_SCHEMAS = 6,\n\tIOAM6_CMD_NS_SET_SCHEMA = 7,\n\t__IOAM6_CMD_MAX = 8,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOMMU_PASID_ARRAY_DOMAIN = 0,\n\tIOMMU_PASID_ARRAY_HANDLE = 1,\n};\n\nenum {\n\tIOMMU_SET_DOMAIN_MUST_SUCCEED = 1,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIPV6_SADDR_RULE_INIT = 0,\n\tIPV6_SADDR_RULE_LOCAL = 1,\n\tIPV6_SADDR_RULE_SCOPE = 2,\n\tIPV6_SADDR_RULE_PREFERRED = 3,\n\tIPV6_SADDR_RULE_OIF = 4,\n\tIPV6_SADDR_RULE_LABEL = 5,\n\tIPV6_SADDR_RULE_PRIVACY = 6,\n\tIPV6_SADDR_RULE_ORCHID = 7,\n\tIPV6_SADDR_RULE_PREFIX = 8,\n\tIPV6_SADDR_RULE_NOT_OPTIMISTIC = 9,\n\tIPV6_SADDR_RULE_MAX = 10,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLEB_FREED = 0,\n\tLEB_FREED_IDX = 1,\n\tLEB_RETAINED = 2,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = -1,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_FUA = 512,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_NCQ_SEND_RECV = 2048,\n\tATA_DFLAG_NCQ_PRIO = 4096,\n\tATA_DFLAG_CDL = 8192,\n\tATA_DFLAG_CFG_MASK = 16383,\n\tATA_DFLAG_PIO = 16384,\n\tATA_DFLAG_NCQ_OFF = 32768,\n\tATA_DFLAG_SLEEPING = 65536,\n\tATA_DFLAG_DUBIOUS_XFER = 131072,\n\tATA_DFLAG_NO_UNLOAD = 262144,\n\tATA_DFLAG_UNLOCK_HPA = 524288,\n\tATA_DFLAG_INIT_MASK = 1048575,\n\tATA_DFLAG_NCQ_PRIO_ENABLED = 1048576,\n\tATA_DFLAG_CDL_ENABLED = 2097152,\n\tATA_DFLAG_RESUMING = 4194304,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_FEATURES_MASK = 201341696,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DEBOUNCE_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_RESUMING = 65536,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_RTF_FILLED = 4,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_HAS_CDL = 256,\n\tATA_QCFLAG_EH = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_QCFLAG_EH_SUCCESS_CMD = 524288,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_HOST_NO_PART = 16,\n\tATA_HOST_NO_SSC = 32,\n\tATA_HOST_NO_DEVSLP = 64,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 10000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_GET_SUCCESS_SENSE = 64,\n\tATA_EH_SET_ACTIVE = 128,\n\tATA_EH_PERDEV_MASK = 225,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_PRINT_QUIRKS = 2097152,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum {\n\tLINK_CAPA_10HD = 0,\n\tLINK_CAPA_10FD = 1,\n\tLINK_CAPA_100HD = 2,\n\tLINK_CAPA_100FD = 3,\n\tLINK_CAPA_1000HD = 4,\n\tLINK_CAPA_1000FD = 5,\n\tLINK_CAPA_2500FD = 6,\n\tLINK_CAPA_5000FD = 7,\n\tLINK_CAPA_10000FD = 8,\n\tLINK_CAPA_20000FD = 9,\n\tLINK_CAPA_25000FD = 10,\n\tLINK_CAPA_40000FD = 11,\n\tLINK_CAPA_50000FD = 12,\n\tLINK_CAPA_56000FD = 13,\n\tLINK_CAPA_80000FD = 14,\n\tLINK_CAPA_100000FD = 15,\n\tLINK_CAPA_200000FD = 16,\n\tLINK_CAPA_400000FD = 17,\n\tLINK_CAPA_800000FD = 18,\n\tLINK_CAPA_1600000FD = 19,\n\t__LINK_CAPA_MAX = 20,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLK_STATE_IN_USE = 0,\n\tNFS_DELEGATED_STATE = 1,\n\tNFS_OPEN_STATE = 2,\n\tNFS_O_RDONLY_STATE = 3,\n\tNFS_O_WRONLY_STATE = 4,\n\tNFS_O_RDWR_STATE = 5,\n\tNFS_STATE_RECLAIM_REBOOT = 6,\n\tNFS_STATE_RECLAIM_NOGRACE = 7,\n\tNFS_STATE_POSIX_LOCKS = 8,\n\tNFS_STATE_RECOVERY_FAILED = 9,\n\tNFS_STATE_MAY_NOTIFY_LOCK = 10,\n\tNFS_STATE_CHANGE_WAIT = 11,\n\tNFS_CLNT_DST_SSC_COPY_STATE = 12,\n\tNFS_CLNT_SRC_SSC_COPY_STATE = 13,\n\tNFS_SRV_SSC_COPY_STATE = 14,\n};\n\nenum {\n\tLLOP_RE = 65536,\n\tLLOP_WE = 131072,\n\tLLOP_ALE = 262144,\n\tLLOP_CLE = 524288,\n\tLLOP_RETURN_IDLE = 2147483648,\n\tLLOP_DATA_MASK = 65535,\n};\n\nenum {\n\tLOCKD_A_SERVER_GRACETIME = 1,\n\tLOCKD_A_SERVER_TCP_PORT = 2,\n\tLOCKD_A_SERVER_UDP_PORT = 3,\n\t__LOCKD_A_SERVER_MAX = 4,\n\tLOCKD_A_SERVER_MAX = 3,\n};\n\nenum {\n\tLOCKD_CMD_SERVER_SET = 1,\n\tLOCKD_CMD_SERVER_GET = 2,\n\t__LOCKD_CMD_MAX = 3,\n\tLOCKD_CMD_MAX = 2,\n};\n\nenum {\n\tLOCK_LEVEL1 = 1,\n\tLOCK_LEVEL2 = 2,\n\tLOCK_ALL = 3,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nenum {\n\tLPROPS_UNCAT = 0,\n\tLPROPS_DIRTY = 1,\n\tLPROPS_DIRTY_IDX = 2,\n\tLPROPS_FREE = 3,\n\tLPROPS_HEAP_CNT = 3,\n\tLPROPS_EMPTY = 4,\n\tLPROPS_FREEABLE = 5,\n\tLPROPS_FRDI_IDX = 6,\n\tLPROPS_CAT_MASK = 15,\n\tLPROPS_TAKEN = 16,\n\tLPROPS_INDEX = 32,\n};\n\nenum {\n\tLPT_SCAN_CONTINUE = 0,\n\tLPT_SCAN_ADD = 1,\n\tLPT_SCAN_STOP = 2,\n};\n\nenum {\n\tLSB = 0,\n\tCSB = 1,\n\tMSB = 2,\n};\n\nenum {\n\tLTAB_DIRTY = 1,\n\tLSAVE_DIRTY = 2,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n\tLo_deleting = 3,\n};\n\nenum {\n\tM88E3082_VCT_OFF = 0,\n\tM88E3082_VCT_PHASE1 = 1,\n\tM88E3082_VCT_PHASE2 = 2,\n};\n\nenum {\n\tMAX8907_IRQ_VCHG_DC_OVP = 0,\n\tMAX8907_IRQ_VCHG_DC_F = 1,\n\tMAX8907_IRQ_VCHG_DC_R = 2,\n\tMAX8907_IRQ_VCHG_THM_OK_R = 3,\n\tMAX8907_IRQ_VCHG_THM_OK_F = 4,\n\tMAX8907_IRQ_VCHG_MBATTLOW_F = 5,\n\tMAX8907_IRQ_VCHG_MBATTLOW_R = 6,\n\tMAX8907_IRQ_VCHG_RST = 7,\n\tMAX8907_IRQ_VCHG_DONE = 8,\n\tMAX8907_IRQ_VCHG_TOPOFF = 9,\n\tMAX8907_IRQ_VCHG_TMR_FAULT = 10,\n\tMAX8907_IRQ_GPM_RSTIN = 0,\n\tMAX8907_IRQ_GPM_MPL = 1,\n\tMAX8907_IRQ_GPM_SW_3SEC = 2,\n\tMAX8907_IRQ_GPM_EXTON_F = 3,\n\tMAX8907_IRQ_GPM_EXTON_R = 4,\n\tMAX8907_IRQ_GPM_SW_1SEC = 5,\n\tMAX8907_IRQ_GPM_SW_F = 6,\n\tMAX8907_IRQ_GPM_SW_R = 7,\n\tMAX8907_IRQ_GPM_SYSCKEN_F = 8,\n\tMAX8907_IRQ_GPM_SYSCKEN_R = 9,\n\tMAX8907_IRQ_RTC_ALARM1 = 0,\n\tMAX8907_IRQ_RTC_ALARM0 = 1,\n};\n\nenum {\n\tMAX8998_IRQ_DCINF = 0,\n\tMAX8998_IRQ_DCINR = 1,\n\tMAX8998_IRQ_JIGF = 2,\n\tMAX8998_IRQ_JIGR = 3,\n\tMAX8998_IRQ_PWRONF = 4,\n\tMAX8998_IRQ_PWRONR = 5,\n\tMAX8998_IRQ_WTSREVNT = 6,\n\tMAX8998_IRQ_SMPLEVNT = 7,\n\tMAX8998_IRQ_ALARM1 = 8,\n\tMAX8998_IRQ_ALARM0 = 9,\n\tMAX8998_IRQ_ONKEY1S = 10,\n\tMAX8998_IRQ_TOPOFFR = 11,\n\tMAX8998_IRQ_DCINOVPR = 12,\n\tMAX8998_IRQ_CHGRSTF = 13,\n\tMAX8998_IRQ_DONER = 14,\n\tMAX8998_IRQ_CHGFAULT = 15,\n\tMAX8998_IRQ_LOBAT1 = 16,\n\tMAX8998_IRQ_LOBAT2 = 17,\n\tMAX8998_IRQ_NR = 18,\n};\n\nenum {\n\tMAX8998_REG_IRQ1 = 0,\n\tMAX8998_REG_IRQ2 = 1,\n\tMAX8998_REG_IRQ3 = 2,\n\tMAX8998_REG_IRQ4 = 3,\n\tMAX8998_REG_IRQM1 = 4,\n\tMAX8998_REG_IRQM2 = 5,\n\tMAX8998_REG_IRQM3 = 6,\n\tMAX8998_REG_IRQM4 = 7,\n\tMAX8998_REG_STATUS1 = 8,\n\tMAX8998_REG_STATUS2 = 9,\n\tMAX8998_REG_STATUSM1 = 10,\n\tMAX8998_REG_STATUSM2 = 11,\n\tMAX8998_REG_CHGR1 = 12,\n\tMAX8998_REG_CHGR2 = 13,\n\tMAX8998_REG_LDO_ACTIVE_DISCHARGE1 = 14,\n\tMAX8998_REG_LDO_ACTIVE_DISCHARGE2 = 15,\n\tMAX8998_REG_BUCK_ACTIVE_DISCHARGE3 = 16,\n\tMAX8998_REG_ONOFF1 = 17,\n\tMAX8998_REG_ONOFF2 = 18,\n\tMAX8998_REG_ONOFF3 = 19,\n\tMAX8998_REG_ONOFF4 = 20,\n\tMAX8998_REG_BUCK1_VOLTAGE1 = 21,\n\tMAX8998_REG_BUCK1_VOLTAGE2 = 22,\n\tMAX8998_REG_BUCK1_VOLTAGE3 = 23,\n\tMAX8998_REG_BUCK1_VOLTAGE4 = 24,\n\tMAX8998_REG_BUCK2_VOLTAGE1 = 25,\n\tMAX8998_REG_BUCK2_VOLTAGE2 = 26,\n\tMAX8998_REG_BUCK3 = 27,\n\tMAX8998_REG_BUCK4 = 28,\n\tMAX8998_REG_LDO2_LDO3 = 29,\n\tMAX8998_REG_LDO4 = 30,\n\tMAX8998_REG_LDO5 = 31,\n\tMAX8998_REG_LDO6 = 32,\n\tMAX8998_REG_LDO7 = 33,\n\tMAX8998_REG_LDO8_LDO9 = 34,\n\tMAX8998_REG_LDO10_LDO11 = 35,\n\tMAX8998_REG_LDO12 = 36,\n\tMAX8998_REG_LDO13 = 37,\n\tMAX8998_REG_LDO14 = 38,\n\tMAX8998_REG_LDO15 = 39,\n\tMAX8998_REG_LDO16 = 40,\n\tMAX8998_REG_LDO17 = 41,\n\tMAX8998_REG_BKCHR = 42,\n\tMAX8998_REG_LBCNFG1 = 43,\n\tMAX8998_REG_LBCNFG2 = 44,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMBE_REFERENCED_B = 0,\n\tMBE_REUSABLE_B = 1,\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nenum {\n\tMCP251X_GPIO_TX0RTS = 0,\n\tMCP251X_GPIO_TX1RTS = 1,\n\tMCP251X_GPIO_TX2RTS = 2,\n\tMCP251X_GPIO_RX0BF = 3,\n\tMCP251X_GPIO_RX1BF = 4,\n};\n\nenum {\n\tMCT_INT_SPI = 0,\n\tMCT_INT_PPI = 1,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMFP_PIN_INVALID = -1,\n\tMFP_PIN_GPIO0 = 0,\n\tMFP_PIN_GPIO1 = 1,\n\tMFP_PIN_GPIO2 = 2,\n\tMFP_PIN_GPIO3 = 3,\n\tMFP_PIN_GPIO4 = 4,\n\tMFP_PIN_GPIO5 = 5,\n\tMFP_PIN_GPIO6 = 6,\n\tMFP_PIN_GPIO7 = 7,\n\tMFP_PIN_GPIO8 = 8,\n\tMFP_PIN_GPIO9 = 9,\n\tMFP_PIN_GPIO10 = 10,\n\tMFP_PIN_GPIO11 = 11,\n\tMFP_PIN_GPIO12 = 12,\n\tMFP_PIN_GPIO13 = 13,\n\tMFP_PIN_GPIO14 = 14,\n\tMFP_PIN_GPIO15 = 15,\n\tMFP_PIN_GPIO16 = 16,\n\tMFP_PIN_GPIO17 = 17,\n\tMFP_PIN_GPIO18 = 18,\n\tMFP_PIN_GPIO19 = 19,\n\tMFP_PIN_GPIO20 = 20,\n\tMFP_PIN_GPIO21 = 21,\n\tMFP_PIN_GPIO22 = 22,\n\tMFP_PIN_GPIO23 = 23,\n\tMFP_PIN_GPIO24 = 24,\n\tMFP_PIN_GPIO25 = 25,\n\tMFP_PIN_GPIO26 = 26,\n\tMFP_PIN_GPIO27 = 27,\n\tMFP_PIN_GPIO28 = 28,\n\tMFP_PIN_GPIO29 = 29,\n\tMFP_PIN_GPIO30 = 30,\n\tMFP_PIN_GPIO31 = 31,\n\tMFP_PIN_GPIO32 = 32,\n\tMFP_PIN_GPIO33 = 33,\n\tMFP_PIN_GPIO34 = 34,\n\tMFP_PIN_GPIO35 = 35,\n\tMFP_PIN_GPIO36 = 36,\n\tMFP_PIN_GPIO37 = 37,\n\tMFP_PIN_GPIO38 = 38,\n\tMFP_PIN_GPIO39 = 39,\n\tMFP_PIN_GPIO40 = 40,\n\tMFP_PIN_GPIO41 = 41,\n\tMFP_PIN_GPIO42 = 42,\n\tMFP_PIN_GPIO43 = 43,\n\tMFP_PIN_GPIO44 = 44,\n\tMFP_PIN_GPIO45 = 45,\n\tMFP_PIN_GPIO46 = 46,\n\tMFP_PIN_GPIO47 = 47,\n\tMFP_PIN_GPIO48 = 48,\n\tMFP_PIN_GPIO49 = 49,\n\tMFP_PIN_GPIO50 = 50,\n\tMFP_PIN_GPIO51 = 51,\n\tMFP_PIN_GPIO52 = 52,\n\tMFP_PIN_GPIO53 = 53,\n\tMFP_PIN_GPIO54 = 54,\n\tMFP_PIN_GPIO55 = 55,\n\tMFP_PIN_GPIO56 = 56,\n\tMFP_PIN_GPIO57 = 57,\n\tMFP_PIN_GPIO58 = 58,\n\tMFP_PIN_GPIO59 = 59,\n\tMFP_PIN_GPIO60 = 60,\n\tMFP_PIN_GPIO61 = 61,\n\tMFP_PIN_GPIO62 = 62,\n\tMFP_PIN_GPIO63 = 63,\n\tMFP_PIN_GPIO64 = 64,\n\tMFP_PIN_GPIO65 = 65,\n\tMFP_PIN_GPIO66 = 66,\n\tMFP_PIN_GPIO67 = 67,\n\tMFP_PIN_GPIO68 = 68,\n\tMFP_PIN_GPIO69 = 69,\n\tMFP_PIN_GPIO70 = 70,\n\tMFP_PIN_GPIO71 = 71,\n\tMFP_PIN_GPIO72 = 72,\n\tMFP_PIN_GPIO73 = 73,\n\tMFP_PIN_GPIO74 = 74,\n\tMFP_PIN_GPIO75 = 75,\n\tMFP_PIN_GPIO76 = 76,\n\tMFP_PIN_GPIO77 = 77,\n\tMFP_PIN_GPIO78 = 78,\n\tMFP_PIN_GPIO79 = 79,\n\tMFP_PIN_GPIO80 = 80,\n\tMFP_PIN_GPIO81 = 81,\n\tMFP_PIN_GPIO82 = 82,\n\tMFP_PIN_GPIO83 = 83,\n\tMFP_PIN_GPIO84 = 84,\n\tMFP_PIN_GPIO85 = 85,\n\tMFP_PIN_GPIO86 = 86,\n\tMFP_PIN_GPIO87 = 87,\n\tMFP_PIN_GPIO88 = 88,\n\tMFP_PIN_GPIO89 = 89,\n\tMFP_PIN_GPIO90 = 90,\n\tMFP_PIN_GPIO91 = 91,\n\tMFP_PIN_GPIO92 = 92,\n\tMFP_PIN_GPIO93 = 93,\n\tMFP_PIN_GPIO94 = 94,\n\tMFP_PIN_GPIO95 = 95,\n\tMFP_PIN_GPIO96 = 96,\n\tMFP_PIN_GPIO97 = 97,\n\tMFP_PIN_GPIO98 = 98,\n\tMFP_PIN_GPIO99 = 99,\n\tMFP_PIN_GPIO100 = 100,\n\tMFP_PIN_GPIO101 = 101,\n\tMFP_PIN_GPIO102 = 102,\n\tMFP_PIN_GPIO103 = 103,\n\tMFP_PIN_GPIO104 = 104,\n\tMFP_PIN_GPIO105 = 105,\n\tMFP_PIN_GPIO106 = 106,\n\tMFP_PIN_GPIO107 = 107,\n\tMFP_PIN_GPIO108 = 108,\n\tMFP_PIN_GPIO109 = 109,\n\tMFP_PIN_GPIO110 = 110,\n\tMFP_PIN_GPIO111 = 111,\n\tMFP_PIN_GPIO112 = 112,\n\tMFP_PIN_GPIO113 = 113,\n\tMFP_PIN_GPIO114 = 114,\n\tMFP_PIN_GPIO115 = 115,\n\tMFP_PIN_GPIO116 = 116,\n\tMFP_PIN_GPIO117 = 117,\n\tMFP_PIN_GPIO118 = 118,\n\tMFP_PIN_GPIO119 = 119,\n\tMFP_PIN_GPIO120 = 120,\n\tMFP_PIN_GPIO121 = 121,\n\tMFP_PIN_GPIO122 = 122,\n\tMFP_PIN_GPIO123 = 123,\n\tMFP_PIN_GPIO124 = 124,\n\tMFP_PIN_GPIO125 = 125,\n\tMFP_PIN_GPIO126 = 126,\n\tMFP_PIN_GPIO127 = 127,\n\tMFP_PIN_GPIO128 = 128,\n\tMFP_PIN_GPIO129 = 129,\n\tMFP_PIN_GPIO130 = 130,\n\tMFP_PIN_GPIO131 = 131,\n\tMFP_PIN_GPIO132 = 132,\n\tMFP_PIN_GPIO133 = 133,\n\tMFP_PIN_GPIO134 = 134,\n\tMFP_PIN_GPIO135 = 135,\n\tMFP_PIN_GPIO136 = 136,\n\tMFP_PIN_GPIO137 = 137,\n\tMFP_PIN_GPIO138 = 138,\n\tMFP_PIN_GPIO139 = 139,\n\tMFP_PIN_GPIO140 = 140,\n\tMFP_PIN_GPIO141 = 141,\n\tMFP_PIN_GPIO142 = 142,\n\tMFP_PIN_GPIO143 = 143,\n\tMFP_PIN_GPIO144 = 144,\n\tMFP_PIN_GPIO145 = 145,\n\tMFP_PIN_GPIO146 = 146,\n\tMFP_PIN_GPIO147 = 147,\n\tMFP_PIN_GPIO148 = 148,\n\tMFP_PIN_GPIO149 = 149,\n\tMFP_PIN_GPIO150 = 150,\n\tMFP_PIN_GPIO151 = 151,\n\tMFP_PIN_GPIO152 = 152,\n\tMFP_PIN_GPIO153 = 153,\n\tMFP_PIN_GPIO154 = 154,\n\tMFP_PIN_GPIO155 = 155,\n\tMFP_PIN_GPIO156 = 156,\n\tMFP_PIN_GPIO157 = 157,\n\tMFP_PIN_GPIO158 = 158,\n\tMFP_PIN_GPIO159 = 159,\n\tMFP_PIN_GPIO160 = 160,\n\tMFP_PIN_GPIO161 = 161,\n\tMFP_PIN_GPIO162 = 162,\n\tMFP_PIN_GPIO163 = 163,\n\tMFP_PIN_GPIO164 = 164,\n\tMFP_PIN_GPIO165 = 165,\n\tMFP_PIN_GPIO166 = 166,\n\tMFP_PIN_GPIO167 = 167,\n\tMFP_PIN_GPIO168 = 168,\n\tMFP_PIN_GPIO169 = 169,\n\tMFP_PIN_GPIO170 = 170,\n\tMFP_PIN_GPIO171 = 171,\n\tMFP_PIN_GPIO172 = 172,\n\tMFP_PIN_GPIO173 = 173,\n\tMFP_PIN_GPIO174 = 174,\n\tMFP_PIN_GPIO175 = 175,\n\tMFP_PIN_GPIO176 = 176,\n\tMFP_PIN_GPIO177 = 177,\n\tMFP_PIN_GPIO178 = 178,\n\tMFP_PIN_GPIO179 = 179,\n\tMFP_PIN_GPIO180 = 180,\n\tMFP_PIN_GPIO181 = 181,\n\tMFP_PIN_GPIO182 = 182,\n\tMFP_PIN_GPIO183 = 183,\n\tMFP_PIN_GPIO184 = 184,\n\tMFP_PIN_GPIO185 = 185,\n\tMFP_PIN_GPIO186 = 186,\n\tMFP_PIN_GPIO187 = 187,\n\tMFP_PIN_GPIO188 = 188,\n\tMFP_PIN_GPIO189 = 189,\n\tMFP_PIN_GPIO190 = 190,\n\tMFP_PIN_GPIO191 = 191,\n\tMFP_PIN_GPIO255 = 255,\n\tMFP_PIN_GPIO0_2 = 256,\n\tMFP_PIN_GPIO1_2 = 257,\n\tMFP_PIN_GPIO2_2 = 258,\n\tMFP_PIN_GPIO3_2 = 259,\n\tMFP_PIN_GPIO4_2 = 260,\n\tMFP_PIN_GPIO5_2 = 261,\n\tMFP_PIN_GPIO6_2 = 262,\n\tMFP_PIN_GPIO7_2 = 263,\n\tMFP_PIN_GPIO8_2 = 264,\n\tMFP_PIN_GPIO9_2 = 265,\n\tMFP_PIN_GPIO10_2 = 266,\n\tMFP_PIN_GPIO11_2 = 267,\n\tMFP_PIN_GPIO12_2 = 268,\n\tMFP_PIN_GPIO13_2 = 269,\n\tMFP_PIN_GPIO14_2 = 270,\n\tMFP_PIN_GPIO15_2 = 271,\n\tMFP_PIN_GPIO16_2 = 272,\n\tMFP_PIN_GPIO17_2 = 273,\n\tMFP_PIN_ULPI_STP = 274,\n\tMFP_PIN_ULPI_NXT = 275,\n\tMFP_PIN_ULPI_DIR = 276,\n\tMFP_PIN_nXCVREN = 277,\n\tMFP_PIN_DF_CLE_nOE = 278,\n\tMFP_PIN_DF_nADV1_ALE = 279,\n\tMFP_PIN_DF_SCLK_E = 280,\n\tMFP_PIN_DF_SCLK_S = 281,\n\tMFP_PIN_nBE0 = 282,\n\tMFP_PIN_nBE1 = 283,\n\tMFP_PIN_DF_nADV2_ALE = 284,\n\tMFP_PIN_DF_INT_RnB = 285,\n\tMFP_PIN_DF_nCS0 = 286,\n\tMFP_PIN_DF_nCS1 = 287,\n\tMFP_PIN_nLUA = 288,\n\tMFP_PIN_nLLA = 289,\n\tMFP_PIN_DF_nWE = 290,\n\tMFP_PIN_DF_ALE_nWE = 291,\n\tMFP_PIN_DF_nRE_nOE = 292,\n\tMFP_PIN_DF_ADDR0 = 293,\n\tMFP_PIN_DF_ADDR1 = 294,\n\tMFP_PIN_DF_ADDR2 = 295,\n\tMFP_PIN_DF_ADDR3 = 296,\n\tMFP_PIN_DF_IO0 = 297,\n\tMFP_PIN_DF_IO1 = 298,\n\tMFP_PIN_DF_IO2 = 299,\n\tMFP_PIN_DF_IO3 = 300,\n\tMFP_PIN_DF_IO4 = 301,\n\tMFP_PIN_DF_IO5 = 302,\n\tMFP_PIN_DF_IO6 = 303,\n\tMFP_PIN_DF_IO7 = 304,\n\tMFP_PIN_DF_IO8 = 305,\n\tMFP_PIN_DF_IO9 = 306,\n\tMFP_PIN_DF_IO10 = 307,\n\tMFP_PIN_DF_IO11 = 308,\n\tMFP_PIN_DF_IO12 = 309,\n\tMFP_PIN_DF_IO13 = 310,\n\tMFP_PIN_DF_IO14 = 311,\n\tMFP_PIN_DF_IO15 = 312,\n\tMFP_PIN_DF_nCS0_SM_nCS2 = 313,\n\tMFP_PIN_DF_nCS1_SM_nCS3 = 314,\n\tMFP_PIN_SM_nCS0 = 315,\n\tMFP_PIN_SM_nCS1 = 316,\n\tMFP_PIN_DF_WEn = 317,\n\tMFP_PIN_DF_REn = 318,\n\tMFP_PIN_DF_CLE_SM_OEn = 319,\n\tMFP_PIN_DF_ALE_SM_WEn = 320,\n\tMFP_PIN_DF_RDY0 = 321,\n\tMFP_PIN_DF_RDY1 = 322,\n\tMFP_PIN_SM_SCLK = 323,\n\tMFP_PIN_SM_BE0 = 324,\n\tMFP_PIN_SM_BE1 = 325,\n\tMFP_PIN_SM_ADV = 326,\n\tMFP_PIN_SM_ADVMUX = 327,\n\tMFP_PIN_SM_RDY = 328,\n\tMFP_PIN_MMC1_DAT7 = 329,\n\tMFP_PIN_MMC1_DAT6 = 330,\n\tMFP_PIN_MMC1_DAT5 = 331,\n\tMFP_PIN_MMC1_DAT4 = 332,\n\tMFP_PIN_MMC1_DAT3 = 333,\n\tMFP_PIN_MMC1_DAT2 = 334,\n\tMFP_PIN_MMC1_DAT1 = 335,\n\tMFP_PIN_MMC1_DAT0 = 336,\n\tMFP_PIN_MMC1_CMD = 337,\n\tMFP_PIN_MMC1_CLK = 338,\n\tMFP_PIN_MMC1_CD = 339,\n\tMFP_PIN_MMC1_WP = 340,\n\tMFP_PIN_GSIM_UIO = 341,\n\tMFP_PIN_GSIM_UCLK = 342,\n\tMFP_PIN_GSIM_UDET = 343,\n\tMFP_PIN_GSIM_nURST = 344,\n\tMFP_PIN_PMIC_INT = 345,\n\tMFP_PIN_RDY = 346,\n\tMFP_PIN_TWSI1_SCL = 347,\n\tMFP_PIN_TWSI1_SDA = 348,\n\tMFP_PIN_TWSI4_SCL = 349,\n\tMFP_PIN_TWSI4_SDA = 350,\n\tMFP_PIN_CLK_REQ = 351,\n\tMFP_PIN_MAX = 352,\n};\n\nenum {\n\tMICRON_ON_DIE_UNSUPPORTED = 0,\n\tMICRON_ON_DIE_SUPPORTED = 1,\n\tMICRON_ON_DIE_MANDATORY = 2,\n};\n\nenum {\n\tMIPI_DCS_NOP = 0,\n\tMIPI_DCS_SOFT_RESET = 1,\n\tMIPI_DCS_GET_COMPRESSION_MODE = 3,\n\tMIPI_DCS_GET_DISPLAY_ID = 4,\n\tMIPI_DCS_GET_ERROR_COUNT_ON_DSI = 5,\n\tMIPI_DCS_GET_RED_CHANNEL = 6,\n\tMIPI_DCS_GET_GREEN_CHANNEL = 7,\n\tMIPI_DCS_GET_BLUE_CHANNEL = 8,\n\tMIPI_DCS_GET_DISPLAY_STATUS = 9,\n\tMIPI_DCS_GET_POWER_MODE = 10,\n\tMIPI_DCS_GET_ADDRESS_MODE = 11,\n\tMIPI_DCS_GET_PIXEL_FORMAT = 12,\n\tMIPI_DCS_GET_DISPLAY_MODE = 13,\n\tMIPI_DCS_GET_SIGNAL_MODE = 14,\n\tMIPI_DCS_GET_DIAGNOSTIC_RESULT = 15,\n\tMIPI_DCS_ENTER_SLEEP_MODE = 16,\n\tMIPI_DCS_EXIT_SLEEP_MODE = 17,\n\tMIPI_DCS_ENTER_PARTIAL_MODE = 18,\n\tMIPI_DCS_ENTER_NORMAL_MODE = 19,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 20,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_CT = 21,\n\tMIPI_DCS_EXIT_INVERT_MODE = 32,\n\tMIPI_DCS_ENTER_INVERT_MODE = 33,\n\tMIPI_DCS_SET_GAMMA_CURVE = 38,\n\tMIPI_DCS_SET_DISPLAY_OFF = 40,\n\tMIPI_DCS_SET_DISPLAY_ON = 41,\n\tMIPI_DCS_SET_COLUMN_ADDRESS = 42,\n\tMIPI_DCS_SET_PAGE_ADDRESS = 43,\n\tMIPI_DCS_WRITE_MEMORY_START = 44,\n\tMIPI_DCS_WRITE_LUT = 45,\n\tMIPI_DCS_READ_MEMORY_START = 46,\n\tMIPI_DCS_SET_PARTIAL_ROWS = 48,\n\tMIPI_DCS_SET_PARTIAL_COLUMNS = 49,\n\tMIPI_DCS_SET_SCROLL_AREA = 51,\n\tMIPI_DCS_SET_TEAR_OFF = 52,\n\tMIPI_DCS_SET_TEAR_ON = 53,\n\tMIPI_DCS_SET_ADDRESS_MODE = 54,\n\tMIPI_DCS_SET_SCROLL_START = 55,\n\tMIPI_DCS_EXIT_IDLE_MODE = 56,\n\tMIPI_DCS_ENTER_IDLE_MODE = 57,\n\tMIPI_DCS_SET_PIXEL_FORMAT = 58,\n\tMIPI_DCS_WRITE_MEMORY_CONTINUE = 60,\n\tMIPI_DCS_SET_3D_CONTROL = 61,\n\tMIPI_DCS_READ_MEMORY_CONTINUE = 62,\n\tMIPI_DCS_GET_3D_CONTROL = 63,\n\tMIPI_DCS_SET_VSYNC_TIMING = 64,\n\tMIPI_DCS_SET_TEAR_SCANLINE = 68,\n\tMIPI_DCS_GET_SCANLINE = 69,\n\tMIPI_DCS_SET_DISPLAY_BRIGHTNESS = 81,\n\tMIPI_DCS_GET_DISPLAY_BRIGHTNESS = 82,\n\tMIPI_DCS_WRITE_CONTROL_DISPLAY = 83,\n\tMIPI_DCS_GET_CONTROL_DISPLAY = 84,\n\tMIPI_DCS_WRITE_POWER_SAVE = 85,\n\tMIPI_DCS_GET_POWER_SAVE = 86,\n\tMIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 94,\n\tMIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 95,\n\tMIPI_DCS_READ_DDB_START = 161,\n\tMIPI_DCS_READ_PPS_START = 162,\n\tMIPI_DCS_READ_DDB_CONTINUE = 168,\n\tMIPI_DCS_READ_PPS_CONTINUE = 169,\n};\n\nenum {\n\tMIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 2,\n\tMIPI_DSI_RX_END_OF_TRANSMISSION = 8,\n\tMIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 17,\n\tMIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 18,\n\tMIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 26,\n\tMIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 28,\n\tMIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 33,\n\tMIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 34,\n};\n\nenum {\n\tMIPI_DSI_V_SYNC_START = 1,\n\tMIPI_DSI_V_SYNC_END = 17,\n\tMIPI_DSI_H_SYNC_START = 33,\n\tMIPI_DSI_H_SYNC_END = 49,\n\tMIPI_DSI_COMPRESSION_MODE = 7,\n\tMIPI_DSI_END_OF_TRANSMISSION = 8,\n\tMIPI_DSI_COLOR_MODE_OFF = 2,\n\tMIPI_DSI_COLOR_MODE_ON = 18,\n\tMIPI_DSI_SHUTDOWN_PERIPHERAL = 34,\n\tMIPI_DSI_TURN_ON_PERIPHERAL = 50,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 3,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 19,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 35,\n\tMIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 4,\n\tMIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 20,\n\tMIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 36,\n\tMIPI_DSI_DCS_SHORT_WRITE = 5,\n\tMIPI_DSI_DCS_SHORT_WRITE_PARAM = 21,\n\tMIPI_DSI_DCS_READ = 6,\n\tMIPI_DSI_EXECUTE_QUEUE = 22,\n\tMIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 55,\n\tMIPI_DSI_NULL_PACKET = 9,\n\tMIPI_DSI_BLANKING_PACKET = 25,\n\tMIPI_DSI_GENERIC_LONG_WRITE = 41,\n\tMIPI_DSI_DCS_LONG_WRITE = 57,\n\tMIPI_DSI_PICTURE_PARAMETER_SET = 10,\n\tMIPI_DSI_COMPRESSED_PIXEL_STREAM = 11,\n\tMIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 12,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 28,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 44,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_30 = 13,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_36 = 29,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 61,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_16 = 14,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_18 = 30,\n\tMIPI_DSI_PIXEL_STREAM_3BYTE_18 = 46,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_24 = 62,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMLO_PAUSE_NONE = 0,\n\tMLO_PAUSE_RX = 1,\n\tMLO_PAUSE_TX = 2,\n\tMLO_PAUSE_TXRX_MASK = 3,\n\tMLO_PAUSE_AN = 4,\n\tMLO_AN_PHY = 0,\n\tMLO_AN_FIXED = 1,\n\tMLO_AN_INBAND = 2,\n\tPHYLINK_PCS_NEG_NONE = 0,\n\tPHYLINK_PCS_NEG_ENABLED = 16,\n\tPHYLINK_PCS_NEG_OUTBAND = 32,\n\tPHYLINK_PCS_NEG_INBAND = 64,\n\tPHYLINK_PCS_NEG_INBAND_DISABLED = 64,\n\tPHYLINK_PCS_NEG_INBAND_ENABLED = 80,\n\tMAC_SYM_PAUSE = 1,\n\tMAC_ASYM_PAUSE = 2,\n\tMAC_10HD = 4,\n\tMAC_10FD = 8,\n\tMAC_10 = 12,\n\tMAC_100HD = 16,\n\tMAC_100FD = 32,\n\tMAC_100 = 48,\n\tMAC_1000HD = 64,\n\tMAC_1000FD = 128,\n\tMAC_1000 = 192,\n\tMAC_2500FD = 256,\n\tMAC_5000FD = 512,\n\tMAC_10000FD = 1024,\n\tMAC_20000FD = 2048,\n\tMAC_25000FD = 4096,\n\tMAC_40000FD = 8192,\n\tMAC_50000FD = 16384,\n\tMAC_56000FD = 32768,\n\tMAC_80000FD = 65536,\n\tMAC_100000FD = 131072,\n\tMAC_200000FD = 262144,\n\tMAC_400000FD = 524288,\n};\n\nenum {\n\tMMP_CLK_MIX_TYPE_V1 = 0,\n\tMMP_CLK_MIX_TYPE_V2 = 1,\n\tMMP_CLK_MIX_TYPE_V3 = 2,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMOUNTPROC3_NULL = 0,\n\tMOUNTPROC3_MNT = 1,\n\tMOUNTPROC3_DUMP = 2,\n\tMOUNTPROC3_UMNT = 3,\n\tMOUNTPROC3_UMNTALL = 4,\n\tMOUNTPROC3_EXPORT = 5,\n};\n\nenum {\n\tMOUNTPROC_NULL = 0,\n\tMOUNTPROC_MNT = 1,\n\tMOUNTPROC_DUMP = 2,\n\tMOUNTPROC_UMNT = 3,\n\tMOUNTPROC_UMNTALL = 4,\n\tMOUNTPROC_EXPORT = 5,\n};\n\nenum {\n\tMOVE_CANCEL_RACE = 1,\n\tMOVE_SOURCE_RD_ERR = 2,\n\tMOVE_TARGET_RD_ERR = 3,\n\tMOVE_TARGET_WR_ERR = 4,\n\tMOVE_TARGET_BITFLIPS = 5,\n\tMOVE_RETRY = 6,\n};\n\nenum {\n\tMOXA_SUPP_RS232 = 1,\n\tMOXA_SUPP_RS422 = 2,\n\tMOXA_SUPP_RS485 = 4,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tMSM8916_BIMC_SNOC_MAS = 1,\n\tMSM8916_BIMC_SNOC_SLV = 2,\n\tMSM8916_MASTER_AMPSS_M0 = 3,\n\tMSM8916_MASTER_LPASS = 4,\n\tMSM8916_MASTER_BLSP_1 = 5,\n\tMSM8916_MASTER_DEHR = 6,\n\tMSM8916_MASTER_GRAPHICS_3D = 7,\n\tMSM8916_MASTER_JPEG = 8,\n\tMSM8916_MASTER_MDP_PORT0 = 9,\n\tMSM8916_MASTER_CRYPTO_CORE0 = 10,\n\tMSM8916_MASTER_SDCC_1 = 11,\n\tMSM8916_MASTER_SDCC_2 = 12,\n\tMSM8916_MASTER_QDSS_BAM = 13,\n\tMSM8916_MASTER_QDSS_ETR = 14,\n\tMSM8916_MASTER_SNOC_CFG = 15,\n\tMSM8916_MASTER_SPDM = 16,\n\tMSM8916_MASTER_TCU0 = 17,\n\tMSM8916_MASTER_TCU1 = 18,\n\tMSM8916_MASTER_USB_HS = 19,\n\tMSM8916_MASTER_VFE = 20,\n\tMSM8916_MASTER_VIDEO_P0 = 21,\n\tMSM8916_SNOC_MM_INT_0 = 22,\n\tMSM8916_SNOC_MM_INT_1 = 23,\n\tMSM8916_SNOC_MM_INT_2 = 24,\n\tMSM8916_SNOC_MM_INT_BIMC = 25,\n\tMSM8916_PNOC_INT_0 = 26,\n\tMSM8916_PNOC_INT_1 = 27,\n\tMSM8916_PNOC_MAS_0 = 28,\n\tMSM8916_PNOC_MAS_1 = 29,\n\tMSM8916_PNOC_SLV_0 = 30,\n\tMSM8916_PNOC_SLV_1 = 31,\n\tMSM8916_PNOC_SLV_2 = 32,\n\tMSM8916_PNOC_SLV_3 = 33,\n\tMSM8916_PNOC_SLV_4 = 34,\n\tMSM8916_PNOC_SLV_8 = 35,\n\tMSM8916_PNOC_SLV_9 = 36,\n\tMSM8916_PNOC_SNOC_MAS = 37,\n\tMSM8916_PNOC_SNOC_SLV = 38,\n\tMSM8916_SNOC_QDSS_INT = 39,\n\tMSM8916_SLAVE_AMPSS_L2 = 40,\n\tMSM8916_SLAVE_APSS = 41,\n\tMSM8916_SLAVE_LPASS = 42,\n\tMSM8916_SLAVE_BIMC_CFG = 43,\n\tMSM8916_SLAVE_BLSP_1 = 44,\n\tMSM8916_SLAVE_BOOT_ROM = 45,\n\tMSM8916_SLAVE_CAMERA_CFG = 46,\n\tMSM8916_SLAVE_CATS_128 = 47,\n\tMSM8916_SLAVE_OCMEM_64 = 48,\n\tMSM8916_SLAVE_CLK_CTL = 49,\n\tMSM8916_SLAVE_CRYPTO_0_CFG = 50,\n\tMSM8916_SLAVE_DEHR_CFG = 51,\n\tMSM8916_SLAVE_DISPLAY_CFG = 52,\n\tMSM8916_SLAVE_EBI_CH0 = 53,\n\tMSM8916_SLAVE_GRAPHICS_3D_CFG = 54,\n\tMSM8916_SLAVE_IMEM_CFG = 55,\n\tMSM8916_SLAVE_IMEM = 56,\n\tMSM8916_SLAVE_MPM = 57,\n\tMSM8916_SLAVE_MSG_RAM = 58,\n\tMSM8916_SLAVE_MSS = 59,\n\tMSM8916_SLAVE_PDM = 60,\n\tMSM8916_SLAVE_PMIC_ARB = 61,\n\tMSM8916_SLAVE_PNOC_CFG = 62,\n\tMSM8916_SLAVE_PRNG = 63,\n\tMSM8916_SLAVE_QDSS_CFG = 64,\n\tMSM8916_SLAVE_QDSS_STM = 65,\n\tMSM8916_SLAVE_RBCPR_CFG = 66,\n\tMSM8916_SLAVE_SDCC_1 = 67,\n\tMSM8916_SLAVE_SDCC_2 = 68,\n\tMSM8916_SLAVE_SECURITY = 69,\n\tMSM8916_SLAVE_SNOC_CFG = 70,\n\tMSM8916_SLAVE_SPDM = 71,\n\tMSM8916_SLAVE_SRVC_SNOC = 72,\n\tMSM8916_SLAVE_TCSR = 73,\n\tMSM8916_SLAVE_TLMM = 74,\n\tMSM8916_SLAVE_USB_HS = 75,\n\tMSM8916_SLAVE_VENUS_CFG = 76,\n\tMSM8916_SNOC_BIMC_0_MAS = 77,\n\tMSM8916_SNOC_BIMC_0_SLV = 78,\n\tMSM8916_SNOC_BIMC_1_MAS = 79,\n\tMSM8916_SNOC_BIMC_1_SLV = 80,\n\tMSM8916_SNOC_INT_0 = 81,\n\tMSM8916_SNOC_INT_1 = 82,\n\tMSM8916_SNOC_INT_BIMC = 83,\n\tMSM8916_SNOC_PNOC_MAS = 84,\n\tMSM8916_SNOC_PNOC_SLV = 85,\n};\n\nenum {\n\tMSPI_DONE = 1,\n\tBSPI_DONE = 2,\n\tBSPI_ERR = 4,\n\tMSPI_BSPI_DONE = 7,\n};\n\nenum {\n\tMTD_OPS_PLACE_OOB = 0,\n\tMTD_OPS_AUTO_OOB = 1,\n\tMTD_OPS_RAW = 2,\n};\n\nenum {\n\tMTK_UART_FC_NONE = 0,\n\tMTK_UART_FC_SW = 1,\n\tMTK_UART_FC_HW = 2,\n};\n\nenum {\n\tMT_UNCACHED = 4,\n\tMT_CACHECLEAN = 5,\n\tMT_MINICLEAN = 6,\n\tMT_LOW_VECTORS = 7,\n\tMT_HIGH_VECTORS = 8,\n\tMT_MEMORY_RWX = 9,\n\tMT_MEMORY_RW = 10,\n\tMT_MEMORY_RO = 11,\n\tMT_ROM = 12,\n\tMT_MEMORY_RWX_NONCACHED = 13,\n\tMT_MEMORY_RW_DTCM = 14,\n\tMT_MEMORY_RWX_ITCM = 15,\n\tMT_MEMORY_RW_SO = 16,\n\tMT_MEMORY_DMA_READY = 17,\n};\n\nenum {\n\tMV64XXX_I2C_ACTION_INVALID = 0,\n\tMV64XXX_I2C_ACTION_CONTINUE = 1,\n\tMV64XXX_I2C_ACTION_SEND_RESTART = 2,\n\tMV64XXX_I2C_ACTION_SEND_ADDR_1 = 3,\n\tMV64XXX_I2C_ACTION_SEND_ADDR_2 = 4,\n\tMV64XXX_I2C_ACTION_SEND_DATA = 5,\n\tMV64XXX_I2C_ACTION_RCV_DATA = 6,\n\tMV64XXX_I2C_ACTION_RCV_DATA_STOP = 7,\n\tMV64XXX_I2C_ACTION_SEND_STOP = 8,\n};\n\nenum {\n\tMV64XXX_I2C_STATE_INVALID = 0,\n\tMV64XXX_I2C_STATE_IDLE = 1,\n\tMV64XXX_I2C_STATE_WAITING_FOR_START_COND = 2,\n\tMV64XXX_I2C_STATE_WAITING_FOR_RESTART = 3,\n\tMV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK = 4,\n\tMV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK = 5,\n\tMV64XXX_I2C_STATE_WAITING_FOR_TARGET_ACK = 6,\n\tMV64XXX_I2C_STATE_WAITING_FOR_TARGET_DATA = 7,\n};\n\nenum {\n\tMV98DX3236_CPU_TO_DDR = 0,\n\tMV98DX3236_CPU_TO_MPLL = 1,\n};\n\nenum {\n\tMV_DMA_BOUNDARY = 65535,\n\tEDMA_REQ_Q_BASE_LO_MASK = 4294966272,\n\tEDMA_RSP_Q_BASE_LO_MASK = 4294967040,\n};\n\nenum {\n\tMV_PRIMARY_BAR = 0,\n\tMV_IO_BAR = 2,\n\tMV_MISC_BAR = 3,\n\tMV_MAJOR_REG_AREA_SZ = 65536,\n\tMV_MINOR_REG_AREA_SZ = 8192,\n\tCOAL_CLOCKS_PER_USEC = 150,\n\tMAX_COAL_TIME_THRESHOLD = 16777215,\n\tMAX_COAL_IO_COUNT = 255,\n\tMV_PCI_REG_BASE = 0,\n\tCOAL_REG_BASE = 98304,\n\tIRQ_COAL_CAUSE = 98312,\n\tALL_PORTS_COAL_IRQ = 16,\n\tIRQ_COAL_IO_THRESHOLD = 98508,\n\tIRQ_COAL_TIME_THRESHOLD = 98512,\n\tTRAN_COAL_CAUSE_LO = 98440,\n\tTRAN_COAL_CAUSE_HI = 98444,\n\tSATAHC0_REG_BASE = 131072,\n\tFLASH_CTL = 66668,\n\tGPIO_PORT_CTL = 66800,\n\tRESET_CFG = 98520,\n\tMV_PCI_REG_SZ = 65536,\n\tMV_SATAHC_REG_SZ = 65536,\n\tMV_SATAHC_ARBTR_REG_SZ = 8192,\n\tMV_PORT_REG_SZ = 8192,\n\tMV_MAX_Q_DEPTH = 32,\n\tMV_MAX_Q_DEPTH_MASK = 31,\n\tMV_CRQB_Q_SZ = 1024,\n\tMV_CRPB_Q_SZ = 256,\n\tMV_MAX_SG_CT = 256,\n\tMV_SG_TBL_SZ = 4096,\n\tMV_PORT_HC_SHIFT = 2,\n\tMV_PORTS_PER_HC = 4,\n\tMV_PORT_MASK = 3,\n\tMV_FLAG_DUAL_HC = 1073741824,\n\tMV_COMMON_FLAGS = 514,\n\tMV_GEN_I_FLAGS = 578,\n\tMV_GEN_II_FLAGS = 656898,\n\tMV_GEN_IIE_FLAGS = 919042,\n\tCRQB_FLAG_READ = 1,\n\tCRQB_TAG_SHIFT = 1,\n\tCRQB_IOID_SHIFT = 6,\n\tCRQB_PMP_SHIFT = 12,\n\tCRQB_HOSTQ_SHIFT = 17,\n\tCRQB_CMD_ADDR_SHIFT = 8,\n\tCRQB_CMD_CS = 4096,\n\tCRQB_CMD_LAST = 32768,\n\tCRPB_FLAG_STATUS_SHIFT = 8,\n\tCRPB_IOID_SHIFT_6 = 5,\n\tCRPB_IOID_SHIFT_7 = 7,\n\tEPRD_FLAG_END_OF_TBL = -2147483648,\n\tMV_PCI_COMMAND = 3072,\n\tMV_PCI_COMMAND_MWRCOM = 16,\n\tMV_PCI_COMMAND_MRDTRIG = 128,\n\tPCI_MAIN_CMD_STS = 3376,\n\tSTOP_PCI_MASTER = 4,\n\tPCI_MASTER_EMPTY = 8,\n\tGLOB_SFT_RST = 16,\n\tMV_PCI_MODE = 3328,\n\tMV_PCI_MODE_MASK = 48,\n\tMV_PCI_EXP_ROM_BAR_CTL = 3372,\n\tMV_PCI_DISC_TIMER = 3332,\n\tMV_PCI_MSI_TRIGGER = 3128,\n\tMV_PCI_SERR_MASK = 3112,\n\tMV_PCI_XBAR_TMOUT = 7428,\n\tMV_PCI_ERR_LOW_ADDRESS = 7488,\n\tMV_PCI_ERR_HIGH_ADDRESS = 7492,\n\tMV_PCI_ERR_ATTRIBUTE = 7496,\n\tMV_PCI_ERR_COMMAND = 7504,\n\tPCI_IRQ_CAUSE = 7512,\n\tPCI_IRQ_MASK = 7516,\n\tPCI_UNMASK_ALL_IRQS = 8388607,\n\tPCIE_IRQ_CAUSE = 6400,\n\tPCIE_IRQ_MASK = 6416,\n\tPCIE_UNMASK_ALL_IRQS = 1034,\n\tPCI_HC_MAIN_IRQ_CAUSE = 7520,\n\tPCI_HC_MAIN_IRQ_MASK = 7524,\n\tSOC_HC_MAIN_IRQ_CAUSE = 131104,\n\tSOC_HC_MAIN_IRQ_MASK = 131108,\n\tERR_IRQ = 1,\n\tDONE_IRQ = 2,\n\tHC0_IRQ_PEND = 511,\n\tHC_SHIFT = 9,\n\tDONE_IRQ_0_3 = 170,\n\tDONE_IRQ_4_7 = 87040,\n\tPCI_ERR = 262144,\n\tTRAN_COAL_LO_DONE = 524288,\n\tTRAN_COAL_HI_DONE = 1048576,\n\tPORTS_0_3_COAL_DONE = 256,\n\tPORTS_4_7_COAL_DONE = 131072,\n\tALL_PORTS_COAL_DONE = 2097152,\n\tGPIO_INT = 4194304,\n\tSELF_INT = 8388608,\n\tTWSI_INT = 16777216,\n\tHC_MAIN_RSVD = -33554432,\n\tHC_MAIN_RSVD_5 = -524288,\n\tHC_MAIN_RSVD_SOC = -320,\n\tHC_CFG = 0,\n\tHC_IRQ_CAUSE = 20,\n\tDMA_IRQ = 1,\n\tHC_COAL_IRQ = 16,\n\tDEV_IRQ = 256,\n\tHC_IRQ_COAL_IO_THRESHOLD = 12,\n\tHC_IRQ_COAL_TIME_THRESHOLD = 16,\n\tSOC_LED_CTRL = 44,\n\tSOC_LED_CTRL_BLINK = 1,\n\tSOC_LED_CTRL_ACT_PRESENCE = 4,\n\tSHD_BLK = 256,\n\tSHD_CTL_AST = 32,\n\tSATA_STATUS = 768,\n\tSATA_ACTIVE = 848,\n\tFIS_IRQ_CAUSE = 868,\n\tFIS_IRQ_CAUSE_AN = 512,\n\tLTMODE = 780,\n\tLTMODE_BIT8 = 256,\n\tPHY_MODE2 = 816,\n\tPHY_MODE3 = 784,\n\tPHY_MODE4 = 788,\n\tPHY_MODE4_CFG_MASK = 3,\n\tPHY_MODE4_CFG_VALUE = 1,\n\tPHY_MODE4_RSVD_ZEROS = 1575223290,\n\tPHY_MODE4_RSVD_ONES = 5,\n\tSATA_IFCTL = 836,\n\tSATA_TESTCTL = 840,\n\tSATA_IFSTAT = 844,\n\tVENDOR_UNIQUE_FIS = 860,\n\tFISCFG = 864,\n\tFISCFG_WAIT_DEV_ERR = 256,\n\tFISCFG_SINGLE_SYNC = 65536,\n\tPHY_MODE9_GEN2 = 920,\n\tPHY_MODE9_GEN1 = 924,\n\tPHYCFG_OFS = 928,\n\tMV5_PHY_MODE = 116,\n\tMV5_LTMODE = 48,\n\tMV5_PHY_CTL = 12,\n\tSATA_IFCFG = 80,\n\tLP_PHY_CTL = 88,\n\tLP_PHY_CTL_PIN_PU_PLL = 1,\n\tLP_PHY_CTL_PIN_PU_RX = 2,\n\tLP_PHY_CTL_PIN_PU_TX = 4,\n\tLP_PHY_CTL_GEN_TX_3G = 32,\n\tLP_PHY_CTL_GEN_RX_3G = 512,\n\tMV_M2_PREAMP_MASK = 2016,\n\tEDMA_CFG = 0,\n\tEDMA_CFG_Q_DEPTH = 31,\n\tEDMA_CFG_NCQ = 32,\n\tEDMA_CFG_NCQ_GO_ON_ERR = 16384,\n\tEDMA_CFG_RD_BRST_EXT = 2048,\n\tEDMA_CFG_WR_BUFF_LEN = 8192,\n\tEDMA_CFG_EDMA_FBS = 65536,\n\tEDMA_CFG_FBS = 67108864,\n\tEDMA_ERR_IRQ_CAUSE = 8,\n\tEDMA_ERR_IRQ_MASK = 12,\n\tEDMA_ERR_D_PAR = 1,\n\tEDMA_ERR_PRD_PAR = 2,\n\tEDMA_ERR_DEV = 4,\n\tEDMA_ERR_DEV_DCON = 8,\n\tEDMA_ERR_DEV_CON = 16,\n\tEDMA_ERR_SERR = 32,\n\tEDMA_ERR_SELF_DIS = 128,\n\tEDMA_ERR_SELF_DIS_5 = 256,\n\tEDMA_ERR_BIST_ASYNC = 256,\n\tEDMA_ERR_TRANS_IRQ_7 = 256,\n\tEDMA_ERR_CRQB_PAR = 512,\n\tEDMA_ERR_CRPB_PAR = 1024,\n\tEDMA_ERR_INTRL_PAR = 2048,\n\tEDMA_ERR_IORDY = 4096,\n\tEDMA_ERR_LNK_CTRL_RX = 122880,\n\tEDMA_ERR_LNK_CTRL_RX_0 = 8192,\n\tEDMA_ERR_LNK_CTRL_RX_1 = 16384,\n\tEDMA_ERR_LNK_CTRL_RX_2 = 32768,\n\tEDMA_ERR_LNK_CTRL_RX_3 = 65536,\n\tEDMA_ERR_LNK_DATA_RX = 1966080,\n\tEDMA_ERR_LNK_CTRL_TX = 65011712,\n\tEDMA_ERR_LNK_CTRL_TX_0 = 2097152,\n\tEDMA_ERR_LNK_CTRL_TX_1 = 4194304,\n\tEDMA_ERR_LNK_CTRL_TX_2 = 8388608,\n\tEDMA_ERR_LNK_CTRL_TX_3 = 16777216,\n\tEDMA_ERR_LNK_CTRL_TX_4 = 33554432,\n\tEDMA_ERR_LNK_DATA_TX = 2080374784,\n\tEDMA_ERR_TRANS_PROTO = -2147483648,\n\tEDMA_ERR_OVERRUN_5 = 32,\n\tEDMA_ERR_UNDERRUN_5 = 64,\n\tEDMA_ERR_IRQ_TRANSIENT = 65101824,\n\tEDMA_EH_FREEZE = -65102149,\n\tEDMA_EH_FREEZE_5 = 8059,\n\tEDMA_REQ_Q_BASE_HI = 16,\n\tEDMA_REQ_Q_IN_PTR = 20,\n\tEDMA_REQ_Q_OUT_PTR = 24,\n\tEDMA_REQ_Q_PTR_SHIFT = 5,\n\tEDMA_RSP_Q_BASE_HI = 28,\n\tEDMA_RSP_Q_IN_PTR = 32,\n\tEDMA_RSP_Q_OUT_PTR = 36,\n\tEDMA_RSP_Q_PTR_SHIFT = 3,\n\tEDMA_CMD = 40,\n\tEDMA_EN = 1,\n\tEDMA_DS = 2,\n\tEDMA_RESET = 4,\n\tEDMA_STATUS = 48,\n\tEDMA_STATUS_CACHE_EMPTY = 64,\n\tEDMA_STATUS_IDLE = 128,\n\tEDMA_IORDY_TMOUT = 52,\n\tEDMA_ARB_CFG = 56,\n\tEDMA_HALTCOND = 96,\n\tEDMA_UNKNOWN_RSVD = 108,\n\tBMDMA_CMD = 548,\n\tBMDMA_STATUS = 552,\n\tBMDMA_PRD_LOW = 556,\n\tBMDMA_PRD_HIGH = 560,\n\tMV_HP_FLAG_MSI = 1,\n\tMV_HP_ERRATA_50XXB0 = 2,\n\tMV_HP_ERRATA_50XXB2 = 4,\n\tMV_HP_ERRATA_60X1B2 = 8,\n\tMV_HP_ERRATA_60X1C0 = 16,\n\tMV_HP_GEN_I = 64,\n\tMV_HP_GEN_II = 128,\n\tMV_HP_GEN_IIE = 256,\n\tMV_HP_PCIE = 512,\n\tMV_HP_CUT_THROUGH = 1024,\n\tMV_HP_FLAG_SOC = 2048,\n\tMV_HP_QUIRK_LED_BLINK_EN = 4096,\n\tMV_HP_FIX_LP_PHY_CTL = 8192,\n\tMV_PP_FLAG_EDMA_EN = 1,\n\tMV_PP_FLAG_NCQ_EN = 2,\n\tMV_PP_FLAG_FBS_EN = 4,\n\tMV_PP_FLAG_DELAYED_EH = 8,\n\tMV_PP_FLAG_FAKE_ATA_BUSY = 16,\n};\n\nenum {\n\tM_I17 = 0,\n\tM_I20 = 1,\n\tM_I20_SR = 2,\n\tM_I24 = 3,\n\tM_I24_8_1 = 4,\n\tM_I24_10_1 = 5,\n\tM_I27_11_1 = 6,\n\tM_MINI = 7,\n\tM_MINI_3_1 = 8,\n\tM_MINI_4_1 = 9,\n\tM_MB = 10,\n\tM_MB_2 = 11,\n\tM_MB_3 = 12,\n\tM_MB_5_1 = 13,\n\tM_MB_6_1 = 14,\n\tM_MB_7_1 = 15,\n\tM_MB_SR = 16,\n\tM_MBA = 17,\n\tM_MBA_3 = 18,\n\tM_MBP = 19,\n\tM_MBP_2 = 20,\n\tM_MBP_2_2 = 21,\n\tM_MBP_SR = 22,\n\tM_MBP_4 = 23,\n\tM_MBP_5_1 = 24,\n\tM_MBP_5_2 = 25,\n\tM_MBP_5_3 = 26,\n\tM_MBP_6_1 = 27,\n\tM_MBP_6_2 = 28,\n\tM_MBP_7_1 = 29,\n\tM_MBP_8_2 = 30,\n\tM_UNKNOWN = 31,\n};\n\nenum {\n\tM_SDMMC12 = 0,\n\tM_SDMMC3 = 1,\n\tM_FMC = 2,\n\tM_QSPI = 3,\n\tM_RNG1 = 4,\n\tM_RNG2 = 5,\n\tM_USBPHY = 6,\n\tM_USBO = 7,\n\tM_STGEN = 8,\n\tM_SPDIF = 9,\n\tM_SPI1 = 10,\n\tM_SPI23 = 11,\n\tM_SPI45 = 12,\n\tM_SPI6 = 13,\n\tM_CEC = 14,\n\tM_I2C12 = 15,\n\tM_I2C35 = 16,\n\tM_I2C46 = 17,\n\tM_LPTIM1 = 18,\n\tM_LPTIM23 = 19,\n\tM_LPTIM45 = 20,\n\tM_USART1 = 21,\n\tM_UART24 = 22,\n\tM_UART35 = 23,\n\tM_USART6 = 24,\n\tM_UART78 = 25,\n\tM_SAI1 = 26,\n\tM_SAI2 = 27,\n\tM_SAI3 = 28,\n\tM_SAI4 = 29,\n\tM_DSI = 30,\n\tM_FDCAN = 31,\n\tM_ADC12 = 32,\n\tM_ETHCK = 33,\n\tM_CKPER = 34,\n\tM_LAST = 35,\n};\n\nenum {\n\tNAME_LESS = 0,\n\tNAME_MATCHES = 1,\n\tNAME_GREATER = 2,\n\tNOT_ON_MEDIA = 3,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNDUSEROPT_UNSPEC = 0,\n\tNDUSEROPT_SRCADDR = 1,\n\t__NDUSEROPT_MAX = 2,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETDEV_STATS = 0,\n\tE1000_STATS = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNFSPROC4_CLNT_NULL = 0,\n\tNFSPROC4_CLNT_READ = 1,\n\tNFSPROC4_CLNT_WRITE = 2,\n\tNFSPROC4_CLNT_COMMIT = 3,\n\tNFSPROC4_CLNT_OPEN = 4,\n\tNFSPROC4_CLNT_OPEN_CONFIRM = 5,\n\tNFSPROC4_CLNT_OPEN_NOATTR = 6,\n\tNFSPROC4_CLNT_OPEN_DOWNGRADE = 7,\n\tNFSPROC4_CLNT_CLOSE = 8,\n\tNFSPROC4_CLNT_SETATTR = 9,\n\tNFSPROC4_CLNT_FSINFO = 10,\n\tNFSPROC4_CLNT_RENEW = 11,\n\tNFSPROC4_CLNT_SETCLIENTID = 12,\n\tNFSPROC4_CLNT_SETCLIENTID_CONFIRM = 13,\n\tNFSPROC4_CLNT_LOCK = 14,\n\tNFSPROC4_CLNT_LOCKT = 15,\n\tNFSPROC4_CLNT_LOCKU = 16,\n\tNFSPROC4_CLNT_ACCESS = 17,\n\tNFSPROC4_CLNT_GETATTR = 18,\n\tNFSPROC4_CLNT_LOOKUP = 19,\n\tNFSPROC4_CLNT_LOOKUP_ROOT = 20,\n\tNFSPROC4_CLNT_REMOVE = 21,\n\tNFSPROC4_CLNT_RENAME = 22,\n\tNFSPROC4_CLNT_LINK = 23,\n\tNFSPROC4_CLNT_SYMLINK = 24,\n\tNFSPROC4_CLNT_CREATE = 25,\n\tNFSPROC4_CLNT_PATHCONF = 26,\n\tNFSPROC4_CLNT_STATFS = 27,\n\tNFSPROC4_CLNT_READLINK = 28,\n\tNFSPROC4_CLNT_READDIR = 29,\n\tNFSPROC4_CLNT_SERVER_CAPS = 30,\n\tNFSPROC4_CLNT_DELEGRETURN = 31,\n\tNFSPROC4_CLNT_GETACL = 32,\n\tNFSPROC4_CLNT_SETACL = 33,\n\tNFSPROC4_CLNT_FS_LOCATIONS = 34,\n\tNFSPROC4_CLNT_RELEASE_LOCKOWNER = 35,\n\tNFSPROC4_CLNT_SECINFO = 36,\n\tNFSPROC4_CLNT_FSID_PRESENT = 37,\n\tNFSPROC4_CLNT_EXCHANGE_ID = 38,\n\tNFSPROC4_CLNT_CREATE_SESSION = 39,\n\tNFSPROC4_CLNT_DESTROY_SESSION = 40,\n\tNFSPROC4_CLNT_SEQUENCE = 41,\n\tNFSPROC4_CLNT_GET_LEASE_TIME = 42,\n\tNFSPROC4_CLNT_RECLAIM_COMPLETE = 43,\n\tNFSPROC4_CLNT_LAYOUTGET = 44,\n\tNFSPROC4_CLNT_GETDEVICEINFO = 45,\n\tNFSPROC4_CLNT_LAYOUTCOMMIT = 46,\n\tNFSPROC4_CLNT_LAYOUTRETURN = 47,\n\tNFSPROC4_CLNT_SECINFO_NO_NAME = 48,\n\tNFSPROC4_CLNT_TEST_STATEID = 49,\n\tNFSPROC4_CLNT_FREE_STATEID = 50,\n\tNFSPROC4_CLNT_GETDEVICELIST = 51,\n\tNFSPROC4_CLNT_BIND_CONN_TO_SESSION = 52,\n\tNFSPROC4_CLNT_DESTROY_CLIENTID = 53,\n\tNFSPROC4_CLNT_SEEK = 54,\n\tNFSPROC4_CLNT_ALLOCATE = 55,\n\tNFSPROC4_CLNT_DEALLOCATE = 56,\n\tNFSPROC4_CLNT_ZERO_RANGE = 57,\n\tNFSPROC4_CLNT_LAYOUTSTATS = 58,\n\tNFSPROC4_CLNT_CLONE = 59,\n\tNFSPROC4_CLNT_COPY = 60,\n\tNFSPROC4_CLNT_OFFLOAD_CANCEL = 61,\n\tNFSPROC4_CLNT_LOOKUPP = 62,\n\tNFSPROC4_CLNT_LAYOUTERROR = 63,\n\tNFSPROC4_CLNT_COPY_NOTIFY = 64,\n\tNFSPROC4_CLNT_GETXATTR = 65,\n\tNFSPROC4_CLNT_SETXATTR = 66,\n\tNFSPROC4_CLNT_LISTXATTRS = 67,\n\tNFSPROC4_CLNT_REMOVEXATTR = 68,\n\tNFSPROC4_CLNT_READ_PLUS = 69,\n\tNFSPROC4_CLNT_OFFLOAD_STATUS = 70,\n};\n\nenum {\n\tNFS_DELEGATION_NEED_RECLAIM = 0,\n\tNFS_DELEGATION_RETURN_IF_CLOSED = 1,\n\tNFS_DELEGATION_REFERENCED = 2,\n\tNFS_DELEGATION_RETURNING = 3,\n\tNFS_DELEGATION_REVOKED = 4,\n\tNFS_DELEGATION_TEST_EXPIRED = 5,\n\tNFS_DELEGATION_DELEGTIME = 6,\n};\n\nenum {\n\tNFS_DEVICEID_INVALID = 0,\n\tNFS_DEVICEID_UNAVAILABLE = 1,\n\tNFS_DEVICEID_NOCACHE = 2,\n};\n\nenum {\n\tNFS_IOHDR_ERROR = 0,\n\tNFS_IOHDR_EOF = 1,\n\tNFS_IOHDR_REDO = 2,\n\tNFS_IOHDR_STAT = 3,\n\tNFS_IOHDR_RESEND_PNFS = 4,\n\tNFS_IOHDR_RESEND_MDS = 5,\n\tNFS_IOHDR_UNSTABLE_WRITES = 6,\n\tNFS_IOHDR_ODIRECT = 7,\n};\n\nenum {\n\tNFS_LAYOUT_RO_FAILED = 0,\n\tNFS_LAYOUT_RW_FAILED = 1,\n\tNFS_LAYOUT_BULK_RECALL = 2,\n\tNFS_LAYOUT_RETURN = 3,\n\tNFS_LAYOUT_RETURN_LOCK = 4,\n\tNFS_LAYOUT_RETURN_REQUESTED = 5,\n\tNFS_LAYOUT_INVALID_STID = 6,\n\tNFS_LAYOUT_FIRST_LAYOUTGET = 7,\n\tNFS_LAYOUT_INODE_FREEING = 8,\n\tNFS_LAYOUT_HASHED = 9,\n\tNFS_LAYOUT_DRAIN = 10,\n};\n\nenum {\n\tNFS_LSEG_VALID = 0,\n\tNFS_LSEG_ROC = 1,\n\tNFS_LSEG_LAYOUTCOMMIT = 2,\n\tNFS_LSEG_LAYOUTRETURN = 3,\n\tNFS_LSEG_UNAVAILABLE = 4,\n};\n\nenum {\n\tNFS_OWNER_RECLAIM_REBOOT = 0,\n\tNFS_OWNER_RECLAIM_NOGRACE = 1,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNLM_LCK_GRANTED = 0,\n\tNLM_LCK_DENIED = 1,\n\tNLM_LCK_DENIED_NOLOCKS = 2,\n\tNLM_LCK_BLOCKED = 3,\n\tNLM_LCK_DENIED_GRACE_PERIOD = 4,\n\tNLM_DEADLCK = 5,\n\tNLM_ROFS = 6,\n\tNLM_STALE_FH = 7,\n\tNLM_FBIG = 8,\n\tNLM_FAILED = 9,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNSMPROC_NULL = 0,\n\tNSMPROC_STAT = 1,\n\tNSMPROC_MON = 2,\n\tNSMPROC_UNMON = 3,\n\tNSMPROC_UNMON_ALL = 4,\n\tNSMPROC_SIMU_CRASH = 5,\n\tNSMPROC_NOTIFY = 6,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 6,\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n\tNVMEM_LAYOUT_ADD = 5,\n\tNVMEM_LAYOUT_REMOVE = 6,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tOD_NORMAL_SAMPLE = 0,\n\tOD_SUB_SAMPLE = 1,\n};\n\nenum {\n\tOMAP3_SOC_AM35XX = 0,\n\tOMAP3_SOC_OMAP3430_ES1 = 1,\n\tOMAP3_SOC_OMAP3430_ES2_PLUS = 2,\n\tOMAP3_SOC_OMAP3630 = 3,\n};\n\nenum {\n\tOMAP_DMA_REG_NONE = 0,\n\tOMAP_DMA_REG_16BIT = 1,\n\tOMAP_DMA_REG_2X16BIT = 2,\n\tOMAP_DMA_REG_32BIT = 3,\n};\n\nenum {\n\tOMAP_I2C_REV_REG = 0,\n\tOMAP_I2C_IE_REG = 1,\n\tOMAP_I2C_STAT_REG = 2,\n\tOMAP_I2C_IV_REG = 3,\n\tOMAP_I2C_WE_REG = 4,\n\tOMAP_I2C_SYSS_REG = 5,\n\tOMAP_I2C_BUF_REG = 6,\n\tOMAP_I2C_CNT_REG = 7,\n\tOMAP_I2C_DATA_REG = 8,\n\tOMAP_I2C_SYSC_REG = 9,\n\tOMAP_I2C_CON_REG = 10,\n\tOMAP_I2C_OA_REG = 11,\n\tOMAP_I2C_SA_REG = 12,\n\tOMAP_I2C_PSC_REG = 13,\n\tOMAP_I2C_SCLL_REG = 14,\n\tOMAP_I2C_SCLH_REG = 15,\n\tOMAP_I2C_SYSTEST_REG = 16,\n\tOMAP_I2C_BUFSTAT_REG = 17,\n\tOMAP_I2C_IP_V2_REVNB_LO = 18,\n\tOMAP_I2C_IP_V2_REVNB_HI = 19,\n\tOMAP_I2C_IP_V2_IRQSTATUS_RAW = 20,\n\tOMAP_I2C_IP_V2_IRQENABLE_SET = 21,\n\tOMAP_I2C_IP_V2_IRQENABLE_CLR = 22,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOVERRIDE_NONE = 0,\n\tOVERRIDE_BASE = 1,\n\tOVERRIDE_STRIDE = 2,\n\tOVERRIDE_HEIGHT = 4,\n\tOVERRIDE_WIDTH = 8,\n};\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid = 2,\n\tOpt_nogrpid = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb = 6,\n\tOpt_nouid32 = 7,\n\tOpt_debug = 8,\n\tOpt_removed = 9,\n\tOpt_user_xattr = 10,\n\tOpt_acl = 11,\n\tOpt_auto_da_alloc = 12,\n\tOpt_noauto_da_alloc = 13,\n\tOpt_noload = 14,\n\tOpt_commit = 15,\n\tOpt_min_batch_time = 16,\n\tOpt_max_batch_time = 17,\n\tOpt_journal_dev = 18,\n\tOpt_journal_path = 19,\n\tOpt_journal_checksum = 20,\n\tOpt_journal_async_commit = 21,\n\tOpt_abort = 22,\n\tOpt_data_journal = 23,\n\tOpt_data_ordered = 24,\n\tOpt_data_writeback = 25,\n\tOpt_data_err_abort = 26,\n\tOpt_data_err_ignore = 27,\n\tOpt_test_dummy_encryption = 28,\n\tOpt_inlinecrypt = 29,\n\tOpt_usrjquota = 30,\n\tOpt_grpjquota = 31,\n\tOpt_quota = 32,\n\tOpt_noquota = 33,\n\tOpt_barrier = 34,\n\tOpt_nobarrier = 35,\n\tOpt_err = 36,\n\tOpt_usrquota = 37,\n\tOpt_grpquota = 38,\n\tOpt_prjquota = 39,\n\tOpt_dax = 40,\n\tOpt_dax_always = 41,\n\tOpt_dax_inode = 42,\n\tOpt_dax_never = 43,\n\tOpt_stripe = 44,\n\tOpt_delalloc = 45,\n\tOpt_nodelalloc = 46,\n\tOpt_warn_on_error = 47,\n\tOpt_nowarn_on_error = 48,\n\tOpt_mblk_io_submit = 49,\n\tOpt_debug_want_extra_isize = 50,\n\tOpt_nomblk_io_submit = 51,\n\tOpt_block_validity = 52,\n\tOpt_noblock_validity = 53,\n\tOpt_inode_readahead_blks = 54,\n\tOpt_journal_ioprio = 55,\n\tOpt_dioread_nolock = 56,\n\tOpt_dioread_lock = 57,\n\tOpt_discard = 58,\n\tOpt_nodiscard = 59,\n\tOpt_init_itable = 60,\n\tOpt_noinit_itable = 61,\n\tOpt_max_dir_size_kb = 62,\n\tOpt_nojournal_checksum = 63,\n\tOpt_nombcache = 64,\n\tOpt_no_prefetch_block_bitmaps = 65,\n\tOpt_mb_optimize_scan = 66,\n\tOpt_errors = 67,\n\tOpt_data = 68,\n\tOpt_data_err = 69,\n\tOpt_jqfmt = 70,\n\tOpt_dax_type = 71,\n};\n\nenum {\n\tOpt_check = 0,\n\tOpt_uid = 1,\n\tOpt_gid = 2,\n\tOpt_umask = 3,\n\tOpt_dmask = 4,\n\tOpt_fmask = 5,\n\tOpt_allow_utime = 6,\n\tOpt_codepage = 7,\n\tOpt_usefree = 8,\n\tOpt_nocase = 9,\n\tOpt_quiet = 10,\n\tOpt_showexec = 11,\n\tOpt_debug___2 = 12,\n\tOpt_immutable = 13,\n\tOpt_dots = 14,\n\tOpt_dotsOK = 15,\n\tOpt_charset = 16,\n\tOpt_shortname = 17,\n\tOpt_utf8 = 18,\n\tOpt_utf8_bool = 19,\n\tOpt_uni_xl = 20,\n\tOpt_uni_xl_bool = 21,\n\tOpt_nonumtail = 22,\n\tOpt_nonumtail_bool = 23,\n\tOpt_obsolete = 24,\n\tOpt_flush = 25,\n\tOpt_tz = 26,\n\tOpt_rodir = 27,\n\tOpt_errors___2 = 28,\n\tOpt_discard___2 = 29,\n\tOpt_nfs = 30,\n\tOpt_nfs_enum = 31,\n\tOpt_time_offset = 32,\n\tOpt_dos1xfloppy = 33,\n};\n\nenum {\n\tOpt_direct = 0,\n\tOpt_fd = 1,\n\tOpt_gid___2 = 2,\n\tOpt_ignore = 3,\n\tOpt_indirect = 4,\n\tOpt_maxproto = 5,\n\tOpt_minproto = 6,\n\tOpt_offset = 7,\n\tOpt_pgrp = 8,\n\tOpt_strictexpire = 9,\n\tOpt_uid___2 = 10,\n};\n\nenum {\n\tOpt_err___2 = 0,\n\tOpt_enc = 1,\n\tOpt_hash = 2,\n};\n\nenum {\n\tOpt_fast_unmount = 0,\n\tOpt_norm_unmount = 1,\n\tOpt_bulk_read = 2,\n\tOpt_no_bulk_read = 3,\n\tOpt_chk_data_crc = 4,\n\tOpt_no_chk_data_crc = 5,\n\tOpt_override_compr = 6,\n\tOpt_assert = 7,\n\tOpt_auth_key = 8,\n\tOpt_auth_hash_name = 9,\n\tOpt_ignore___2 = 10,\n};\n\nenum {\n\tOpt_fatal_neterrors_default = 0,\n\tOpt_fatal_neterrors_enetunreach = 1,\n\tOpt_fatal_neterrors_none = 2,\n};\n\nenum {\n\tOpt_find_uid = 0,\n\tOpt_find_gid = 1,\n\tOpt_find_user = 2,\n\tOpt_find_group = 3,\n\tOpt_find_err = 4,\n};\n\nenum {\n\tOpt_kmsg_bytes = 0,\n};\n\nenum {\n\tOpt_local_lock_all = 0,\n\tOpt_local_lock_flock = 1,\n\tOpt_local_lock_none = 2,\n\tOpt_local_lock_posix = 3,\n};\n\nenum {\n\tOpt_lookupcache_all = 0,\n\tOpt_lookupcache_none = 1,\n\tOpt_lookupcache_positive = 2,\n};\n\nenum {\n\tOpt_sec_krb5 = 0,\n\tOpt_sec_krb5i = 1,\n\tOpt_sec_krb5p = 2,\n\tOpt_sec_lkey = 3,\n\tOpt_sec_lkeyi = 4,\n\tOpt_sec_lkeyp = 5,\n\tOpt_sec_none = 6,\n\tOpt_sec_spkm = 7,\n\tOpt_sec_spkmi = 8,\n\tOpt_sec_spkmp = 9,\n\tOpt_sec_sys = 10,\n\tnr__Opt_sec = 11,\n};\n\nenum {\n\tOpt_uid___3 = 0,\n\tOpt_gid___3 = 1,\n\tOpt_mode = 2,\n};\n\nenum {\n\tOpt_uid___4 = 0,\n\tOpt_gid___4 = 1,\n\tOpt_mode___2 = 2,\n\tOpt_source = 3,\n};\n\nenum {\n\tOpt_uid___5 = 0,\n\tOpt_gid___5 = 1,\n\tOpt_mode___3 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___3 = 6,\n};\n\nenum {\n\tOpt_vers_2 = 0,\n\tOpt_vers_3 = 1,\n\tOpt_vers_4 = 2,\n\tOpt_vers_4_0 = 3,\n\tOpt_vers_4_1 = 4,\n\tOpt_vers_4_2 = 5,\n};\n\nenum {\n\tOpt_write_lazy = 0,\n\tOpt_write_eager = 1,\n\tOpt_write_wait = 2,\n};\n\nenum {\n\tOpt_xprt_rdma = 0,\n\tOpt_xprt_rdma6 = 1,\n\tOpt_xprt_tcp = 2,\n\tOpt_xprt_tcp6 = 3,\n\tOpt_xprt_udp = 4,\n\tOpt_xprt_udp6 = 5,\n\tnr__Opt_xprt = 6,\n};\n\nenum {\n\tOpt_xprtsec_none = 0,\n\tOpt_xprtsec_tls = 1,\n\tOpt_xprtsec_mtls = 2,\n\tnr__Opt_xprtsec = 3,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPALMAS_EXT_CONTROL_ENABLE1 = 1,\n\tPALMAS_EXT_CONTROL_ENABLE2 = 2,\n\tPALMAS_EXT_CONTROL_NSLEEP = 4,\n};\n\nenum {\n\tPARSE_INVALID = 1,\n\tPARSE_NOT_LONGNAME = 2,\n\tPARSE_EOF = 3,\n};\n\nenum {\n\tPCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = 1,\n\tPCI_BRIDGE_EMUL_NO_IO_FORWARD = 2,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_BRIDGE_RESOURCES = 7,\n\tPCI_BRIDGE_RESOURCE_END = 10,\n\tPCI_NUM_RESOURCES = 11,\n\tDEVICE_COUNT_RESOURCE = 11,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPERF_FC_LEVEL = 0,\n\tPERF_FC_LIMIT = 1,\n\tPERF_FC_MAX = 2,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPG_BUSY = 0,\n\tPG_MAPPED = 1,\n\tPG_FOLIO = 2,\n\tPG_CLEAN = 3,\n\tPG_COMMIT_TO_DS = 4,\n\tPG_INODE_REF = 5,\n\tPG_HEADLOCK = 6,\n\tPG_TEARDOWN = 7,\n\tPG_UNLOCKPAGE = 8,\n\tPG_UPTODATE = 9,\n\tPG_WB_END = 10,\n\tPG_REMOVE = 11,\n\tPG_CONTENDED1 = 12,\n\tPG_CONTENDED2 = 13,\n};\n\nenum {\n\tPHYLINK_DISABLE_STOPPED = 0,\n\tPHYLINK_DISABLE_LINK = 1,\n\tPHYLINK_DISABLE_MAC_WOL = 2,\n\tPHYLINK_DISABLE_REPLAY = 3,\n\tPCS_STATE_DOWN = 0,\n\tPCS_STATE_STARTING = 1,\n\tPCS_STATE_STARTED = 2,\n};\n\nenum {\n\tPHY_GMII_SEL_PORT_MODE = 0,\n\tPHY_GMII_SEL_RGMII_ID_MODE = 1,\n\tPHY_GMII_SEL_RMII_IO_CLK_EN = 2,\n\tPHY_GMII_SEL_FIXED_TX_DELAY = 3,\n\tPHY_GMII_SEL_LAST = 4,\n};\n\nenum {\n\tPINCONF_BIAS = 0,\n\tPINCONF_SCHMITT = 1,\n\tPINCONF_DRIVE_STRENGTH = 2,\n};\n\nenum {\n\tPINCTRL_PIN_REG_MODE = 0,\n\tPINCTRL_PIN_REG_DIR = 1,\n\tPINCTRL_PIN_REG_DI = 2,\n\tPINCTRL_PIN_REG_DO = 3,\n\tPINCTRL_PIN_REG_SR = 4,\n\tPINCTRL_PIN_REG_SMT = 5,\n\tPINCTRL_PIN_REG_PD = 6,\n\tPINCTRL_PIN_REG_PU = 7,\n\tPINCTRL_PIN_REG_E4 = 8,\n\tPINCTRL_PIN_REG_E8 = 9,\n\tPINCTRL_PIN_REG_TDSEL = 10,\n\tPINCTRL_PIN_REG_RDSEL = 11,\n\tPINCTRL_PIN_REG_DRV = 12,\n\tPINCTRL_PIN_REG_PUPD = 13,\n\tPINCTRL_PIN_REG_R0 = 14,\n\tPINCTRL_PIN_REG_R1 = 15,\n\tPINCTRL_PIN_REG_IES = 16,\n\tPINCTRL_PIN_REG_PULLEN = 17,\n\tPINCTRL_PIN_REG_PULLSEL = 18,\n\tPINCTRL_PIN_REG_DRV_EN = 19,\n\tPINCTRL_PIN_REG_DRV_E0 = 20,\n\tPINCTRL_PIN_REG_DRV_E1 = 21,\n\tPINCTRL_PIN_REG_DRV_ADV = 22,\n\tPINCTRL_PIN_REG_RSEL = 23,\n\tPINCTRL_PIN_REG_MAX = 24,\n};\n\nenum {\n\tPINMUX_RESERVED = 0,\n\tPINMUX_DATA_BEGIN = 1,\n\tGP_0_0_DATA = 2,\n\tGP_0_1_DATA = 3,\n\tGP_0_2_DATA = 4,\n\tGP_0_3_DATA = 5,\n\tGP_0_4_DATA = 6,\n\tGP_0_5_DATA = 7,\n\tGP_0_6_DATA = 8,\n\tGP_0_7_DATA = 9,\n\tGP_0_8_DATA = 10,\n\tGP_0_9_DATA = 11,\n\tGP_0_10_DATA = 12,\n\tGP_0_11_DATA = 13,\n\tGP_0_12_DATA = 14,\n\tGP_0_13_DATA = 15,\n\tGP_0_14_DATA = 16,\n\tGP_0_15_DATA = 17,\n\tGP_0_16_DATA = 18,\n\tGP_0_17_DATA = 19,\n\tGP_0_18_DATA = 20,\n\tGP_0_19_DATA = 21,\n\tGP_0_20_DATA = 22,\n\tGP_0_21_DATA = 23,\n\tGP_0_22_DATA = 24,\n\tGP_0_23_DATA = 25,\n\tGP_0_24_DATA = 26,\n\tGP_0_25_DATA = 27,\n\tGP_0_26_DATA = 28,\n\tGP_0_27_DATA = 29,\n\tGP_0_28_DATA = 30,\n\tGP_0_29_DATA = 31,\n\tGP_0_30_DATA = 32,\n\tGP_0_31_DATA = 33,\n\tGP_1_0_DATA = 34,\n\tGP_1_1_DATA = 35,\n\tGP_1_2_DATA = 36,\n\tGP_1_3_DATA = 37,\n\tGP_1_4_DATA = 38,\n\tGP_1_5_DATA = 39,\n\tGP_1_6_DATA = 40,\n\tGP_1_7_DATA = 41,\n\tGP_1_8_DATA = 42,\n\tGP_1_9_DATA = 43,\n\tGP_1_10_DATA = 44,\n\tGP_1_11_DATA = 45,\n\tGP_1_12_DATA = 46,\n\tGP_1_13_DATA = 47,\n\tGP_1_14_DATA = 48,\n\tGP_1_15_DATA = 49,\n\tGP_1_16_DATA = 50,\n\tGP_1_17_DATA = 51,\n\tGP_1_18_DATA = 52,\n\tGP_1_19_DATA = 53,\n\tGP_1_20_DATA = 54,\n\tGP_1_21_DATA = 55,\n\tGP_1_22_DATA = 56,\n\tGP_1_23_DATA = 57,\n\tGP_1_24_DATA = 58,\n\tGP_1_25_DATA = 59,\n\tGP_2_0_DATA = 60,\n\tGP_2_1_DATA = 61,\n\tGP_2_2_DATA = 62,\n\tGP_2_3_DATA = 63,\n\tGP_2_4_DATA = 64,\n\tGP_2_5_DATA = 65,\n\tGP_2_6_DATA = 66,\n\tGP_2_7_DATA = 67,\n\tGP_2_8_DATA = 68,\n\tGP_2_9_DATA = 69,\n\tGP_2_10_DATA = 70,\n\tGP_2_11_DATA = 71,\n\tGP_2_12_DATA = 72,\n\tGP_2_13_DATA = 73,\n\tGP_2_14_DATA = 74,\n\tGP_2_15_DATA = 75,\n\tGP_2_16_DATA = 76,\n\tGP_2_17_DATA = 77,\n\tGP_2_18_DATA = 78,\n\tGP_2_19_DATA = 79,\n\tGP_2_20_DATA = 80,\n\tGP_2_21_DATA = 81,\n\tGP_2_22_DATA = 82,\n\tGP_2_23_DATA = 83,\n\tGP_2_24_DATA = 84,\n\tGP_2_25_DATA = 85,\n\tGP_2_26_DATA = 86,\n\tGP_2_27_DATA = 87,\n\tGP_2_28_DATA = 88,\n\tGP_2_29_DATA = 89,\n\tGP_2_30_DATA = 90,\n\tGP_2_31_DATA = 91,\n\tGP_3_0_DATA = 92,\n\tGP_3_1_DATA = 93,\n\tGP_3_2_DATA = 94,\n\tGP_3_3_DATA = 95,\n\tGP_3_4_DATA = 96,\n\tGP_3_5_DATA = 97,\n\tGP_3_6_DATA = 98,\n\tGP_3_7_DATA = 99,\n\tGP_3_8_DATA = 100,\n\tGP_3_9_DATA = 101,\n\tGP_3_10_DATA = 102,\n\tGP_3_11_DATA = 103,\n\tGP_3_12_DATA = 104,\n\tGP_3_13_DATA = 105,\n\tGP_3_14_DATA = 106,\n\tGP_3_15_DATA = 107,\n\tGP_3_16_DATA = 108,\n\tGP_3_17_DATA = 109,\n\tGP_3_18_DATA = 110,\n\tGP_3_19_DATA = 111,\n\tGP_3_20_DATA = 112,\n\tGP_3_21_DATA = 113,\n\tGP_3_22_DATA = 114,\n\tGP_3_23_DATA = 115,\n\tGP_3_24_DATA = 116,\n\tGP_3_25_DATA = 117,\n\tGP_3_26_DATA = 118,\n\tGP_3_27_DATA = 119,\n\tGP_3_28_DATA = 120,\n\tGP_3_29_DATA = 121,\n\tGP_3_30_DATA = 122,\n\tGP_3_31_DATA = 123,\n\tGP_4_0_DATA = 124,\n\tGP_4_1_DATA = 125,\n\tGP_4_2_DATA = 126,\n\tGP_4_3_DATA = 127,\n\tGP_4_4_DATA = 128,\n\tGP_4_5_DATA = 129,\n\tGP_4_6_DATA = 130,\n\tGP_4_7_DATA = 131,\n\tGP_4_8_DATA = 132,\n\tGP_4_9_DATA = 133,\n\tGP_4_10_DATA = 134,\n\tGP_4_11_DATA = 135,\n\tGP_4_12_DATA = 136,\n\tGP_4_13_DATA = 137,\n\tGP_4_14_DATA = 138,\n\tGP_4_15_DATA = 139,\n\tGP_4_16_DATA = 140,\n\tGP_4_17_DATA = 141,\n\tGP_4_18_DATA = 142,\n\tGP_4_19_DATA = 143,\n\tGP_4_20_DATA = 144,\n\tGP_4_21_DATA = 145,\n\tGP_4_22_DATA = 146,\n\tGP_4_23_DATA = 147,\n\tGP_4_24_DATA = 148,\n\tGP_4_25_DATA = 149,\n\tGP_4_26_DATA = 150,\n\tGP_4_27_DATA = 151,\n\tGP_4_28_DATA = 152,\n\tGP_4_29_DATA = 153,\n\tGP_4_30_DATA = 154,\n\tGP_4_31_DATA = 155,\n\tGP_5_0_DATA = 156,\n\tGP_5_1_DATA = 157,\n\tGP_5_2_DATA = 158,\n\tGP_5_3_DATA = 159,\n\tGP_5_4_DATA = 160,\n\tGP_5_5_DATA = 161,\n\tGP_5_6_DATA = 162,\n\tGP_5_7_DATA = 163,\n\tGP_5_8_DATA = 164,\n\tGP_5_9_DATA = 165,\n\tGP_5_10_DATA = 166,\n\tGP_5_11_DATA = 167,\n\tGP_5_12_DATA = 168,\n\tGP_5_13_DATA = 169,\n\tGP_5_14_DATA = 170,\n\tGP_5_15_DATA = 171,\n\tGP_5_16_DATA = 172,\n\tGP_5_17_DATA = 173,\n\tGP_5_18_DATA = 174,\n\tGP_5_19_DATA = 175,\n\tGP_5_20_DATA = 176,\n\tGP_5_21_DATA = 177,\n\tGP_5_22_DATA = 178,\n\tGP_5_23_DATA = 179,\n\tGP_5_24_DATA = 180,\n\tGP_5_25_DATA = 181,\n\tGP_5_26_DATA = 182,\n\tGP_5_27_DATA = 183,\n\tGP_6_0_DATA = 184,\n\tGP_6_1_DATA = 185,\n\tGP_6_2_DATA = 186,\n\tGP_6_3_DATA = 187,\n\tGP_6_4_DATA = 188,\n\tGP_6_5_DATA = 189,\n\tGP_6_6_DATA = 190,\n\tGP_6_7_DATA = 191,\n\tGP_6_8_DATA = 192,\n\tGP_6_9_DATA = 193,\n\tGP_6_10_DATA = 194,\n\tGP_6_11_DATA = 195,\n\tGP_6_12_DATA = 196,\n\tGP_6_13_DATA = 197,\n\tGP_6_14_DATA = 198,\n\tGP_6_15_DATA = 199,\n\tGP_6_16_DATA = 200,\n\tGP_6_17_DATA = 201,\n\tGP_6_18_DATA = 202,\n\tGP_6_19_DATA = 203,\n\tGP_6_20_DATA = 204,\n\tGP_6_21_DATA = 205,\n\tGP_6_22_DATA = 206,\n\tGP_6_23_DATA = 207,\n\tGP_6_24_DATA = 208,\n\tGP_6_25_DATA = 209,\n\tPINMUX_DATA_END = 210,\n\tPINMUX_FUNCTION_BEGIN = 211,\n\tGP_0_0_FN = 212,\n\tGP_0_1_FN = 213,\n\tGP_0_2_FN = 214,\n\tGP_0_3_FN = 215,\n\tGP_0_4_FN = 216,\n\tGP_0_5_FN = 217,\n\tGP_0_6_FN = 218,\n\tGP_0_7_FN = 219,\n\tGP_0_8_FN = 220,\n\tGP_0_9_FN = 221,\n\tGP_0_10_FN = 222,\n\tGP_0_11_FN = 223,\n\tGP_0_12_FN = 224,\n\tGP_0_13_FN = 225,\n\tGP_0_14_FN = 226,\n\tGP_0_15_FN = 227,\n\tGP_0_16_FN = 228,\n\tGP_0_17_FN = 229,\n\tGP_0_18_FN = 230,\n\tGP_0_19_FN = 231,\n\tGP_0_20_FN = 232,\n\tGP_0_21_FN = 233,\n\tGP_0_22_FN = 234,\n\tGP_0_23_FN = 235,\n\tGP_0_24_FN = 236,\n\tGP_0_25_FN = 237,\n\tGP_0_26_FN = 238,\n\tGP_0_27_FN = 239,\n\tGP_0_28_FN = 240,\n\tGP_0_29_FN = 241,\n\tGP_0_30_FN = 242,\n\tGP_0_31_FN = 243,\n\tGP_1_0_FN = 244,\n\tGP_1_1_FN = 245,\n\tGP_1_2_FN = 246,\n\tGP_1_3_FN = 247,\n\tGP_1_4_FN = 248,\n\tGP_1_5_FN = 249,\n\tGP_1_6_FN = 250,\n\tGP_1_7_FN = 251,\n\tGP_1_8_FN = 252,\n\tGP_1_9_FN = 253,\n\tGP_1_10_FN = 254,\n\tGP_1_11_FN = 255,\n\tGP_1_12_FN = 256,\n\tGP_1_13_FN = 257,\n\tGP_1_14_FN = 258,\n\tGP_1_15_FN = 259,\n\tGP_1_16_FN = 260,\n\tGP_1_17_FN = 261,\n\tGP_1_18_FN = 262,\n\tGP_1_19_FN = 263,\n\tGP_1_20_FN = 264,\n\tGP_1_21_FN = 265,\n\tGP_1_22_FN = 266,\n\tGP_1_23_FN = 267,\n\tGP_1_24_FN = 268,\n\tGP_1_25_FN = 269,\n\tGP_2_0_FN = 270,\n\tGP_2_1_FN = 271,\n\tGP_2_2_FN = 272,\n\tGP_2_3_FN = 273,\n\tGP_2_4_FN = 274,\n\tGP_2_5_FN = 275,\n\tGP_2_6_FN = 276,\n\tGP_2_7_FN = 277,\n\tGP_2_8_FN = 278,\n\tGP_2_9_FN = 279,\n\tGP_2_10_FN = 280,\n\tGP_2_11_FN = 281,\n\tGP_2_12_FN = 282,\n\tGP_2_13_FN = 283,\n\tGP_2_14_FN = 284,\n\tGP_2_15_FN = 285,\n\tGP_2_16_FN = 286,\n\tGP_2_17_FN = 287,\n\tGP_2_18_FN = 288,\n\tGP_2_19_FN = 289,\n\tGP_2_20_FN = 290,\n\tGP_2_21_FN = 291,\n\tGP_2_22_FN = 292,\n\tGP_2_23_FN = 293,\n\tGP_2_24_FN = 294,\n\tGP_2_25_FN = 295,\n\tGP_2_26_FN = 296,\n\tGP_2_27_FN = 297,\n\tGP_2_28_FN = 298,\n\tGP_2_29_FN = 299,\n\tGP_2_30_FN = 300,\n\tGP_2_31_FN = 301,\n\tGP_3_0_FN = 302,\n\tGP_3_1_FN = 303,\n\tGP_3_2_FN = 304,\n\tGP_3_3_FN = 305,\n\tGP_3_4_FN = 306,\n\tGP_3_5_FN = 307,\n\tGP_3_6_FN = 308,\n\tGP_3_7_FN = 309,\n\tGP_3_8_FN = 310,\n\tGP_3_9_FN = 311,\n\tGP_3_10_FN = 312,\n\tGP_3_11_FN = 313,\n\tGP_3_12_FN = 314,\n\tGP_3_13_FN = 315,\n\tGP_3_14_FN = 316,\n\tGP_3_15_FN = 317,\n\tGP_3_16_FN = 318,\n\tGP_3_17_FN = 319,\n\tGP_3_18_FN = 320,\n\tGP_3_19_FN = 321,\n\tGP_3_20_FN = 322,\n\tGP_3_21_FN = 323,\n\tGP_3_22_FN = 324,\n\tGP_3_23_FN = 325,\n\tGP_3_24_FN = 326,\n\tGP_3_25_FN = 327,\n\tGP_3_26_FN = 328,\n\tGP_3_27_FN = 329,\n\tGP_3_28_FN = 330,\n\tGP_3_29_FN = 331,\n\tGP_3_30_FN = 332,\n\tGP_3_31_FN = 333,\n\tGP_4_0_FN = 334,\n\tGP_4_1_FN = 335,\n\tGP_4_2_FN = 336,\n\tGP_4_3_FN = 337,\n\tGP_4_4_FN = 338,\n\tGP_4_5_FN = 339,\n\tGP_4_6_FN = 340,\n\tGP_4_7_FN = 341,\n\tGP_4_8_FN = 342,\n\tGP_4_9_FN = 343,\n\tGP_4_10_FN = 344,\n\tGP_4_11_FN = 345,\n\tGP_4_12_FN = 346,\n\tGP_4_13_FN = 347,\n\tGP_4_14_FN = 348,\n\tGP_4_15_FN = 349,\n\tGP_4_16_FN = 350,\n\tGP_4_17_FN = 351,\n\tGP_4_18_FN = 352,\n\tGP_4_19_FN = 353,\n\tGP_4_20_FN = 354,\n\tGP_4_21_FN = 355,\n\tGP_4_22_FN = 356,\n\tGP_4_23_FN = 357,\n\tGP_4_24_FN = 358,\n\tGP_4_25_FN = 359,\n\tGP_4_26_FN = 360,\n\tGP_4_27_FN = 361,\n\tGP_4_28_FN = 362,\n\tGP_4_29_FN = 363,\n\tGP_4_30_FN = 364,\n\tGP_4_31_FN = 365,\n\tGP_5_0_FN = 366,\n\tGP_5_1_FN = 367,\n\tGP_5_2_FN = 368,\n\tGP_5_3_FN = 369,\n\tGP_5_4_FN = 370,\n\tGP_5_5_FN = 371,\n\tGP_5_6_FN = 372,\n\tGP_5_7_FN = 373,\n\tGP_5_8_FN = 374,\n\tGP_5_9_FN = 375,\n\tGP_5_10_FN = 376,\n\tGP_5_11_FN = 377,\n\tGP_5_12_FN = 378,\n\tGP_5_13_FN = 379,\n\tGP_5_14_FN = 380,\n\tGP_5_15_FN = 381,\n\tGP_5_16_FN = 382,\n\tGP_5_17_FN = 383,\n\tGP_5_18_FN = 384,\n\tGP_5_19_FN = 385,\n\tGP_5_20_FN = 386,\n\tGP_5_21_FN = 387,\n\tGP_5_22_FN = 388,\n\tGP_5_23_FN = 389,\n\tGP_5_24_FN = 390,\n\tGP_5_25_FN = 391,\n\tGP_5_26_FN = 392,\n\tGP_5_27_FN = 393,\n\tGP_6_0_FN = 394,\n\tGP_6_1_FN = 395,\n\tGP_6_2_FN = 396,\n\tGP_6_3_FN = 397,\n\tGP_6_4_FN = 398,\n\tGP_6_5_FN = 399,\n\tGP_6_6_FN = 400,\n\tGP_6_7_FN = 401,\n\tGP_6_8_FN = 402,\n\tGP_6_9_FN = 403,\n\tGP_6_10_FN = 404,\n\tGP_6_11_FN = 405,\n\tGP_6_12_FN = 406,\n\tGP_6_13_FN = 407,\n\tGP_6_14_FN = 408,\n\tGP_6_15_FN = 409,\n\tGP_6_16_FN = 410,\n\tGP_6_17_FN = 411,\n\tGP_6_18_FN = 412,\n\tGP_6_19_FN = 413,\n\tGP_6_20_FN = 414,\n\tGP_6_21_FN = 415,\n\tGP_6_22_FN = 416,\n\tGP_6_23_FN = 417,\n\tGP_6_24_FN = 418,\n\tGP_6_25_FN = 419,\n\tFN_IP0_23_22 = 420,\n\tFN_IP0_24 = 421,\n\tFN_IP0_25 = 422,\n\tFN_IP0_27_26 = 423,\n\tFN_IP0_29_28 = 424,\n\tFN_IP0_31_30 = 425,\n\tFN_IP1_1_0 = 426,\n\tFN_IP1_3_2 = 427,\n\tFN_IP1_5_4 = 428,\n\tFN_IP1_7_6 = 429,\n\tFN_IP1_10_8 = 430,\n\tFN_IP1_12_11 = 431,\n\tFN_IP1_14_13 = 432,\n\tFN_IP1_17_15 = 433,\n\tFN_IP1_19_18 = 434,\n\tFN_IP1_21_20 = 435,\n\tFN_IP1_23_22 = 436,\n\tFN_IP1_24 = 437,\n\tFN_A2 = 438,\n\tFN_IP1_26 = 439,\n\tFN_IP1_27 = 440,\n\tFN_IP1_29_28 = 441,\n\tFN_IP1_31_30 = 442,\n\tFN_IP2_1_0 = 443,\n\tFN_IP2_3_2 = 444,\n\tFN_IP2_5_4 = 445,\n\tFN_IP2_7_6 = 446,\n\tFN_IP2_9_8 = 447,\n\tFN_IP2_11_10 = 448,\n\tFN_IP2_13_12 = 449,\n\tFN_IP2_15_14 = 450,\n\tFN_IP2_17_16 = 451,\n\tFN_IP2_20_18 = 452,\n\tFN_IP2_23_21 = 453,\n\tFN_IP2_26_24 = 454,\n\tFN_IP2_29_27 = 455,\n\tFN_IP2_31_30 = 456,\n\tFN_IP3_1_0 = 457,\n\tFN_IP3_3_2 = 458,\n\tFN_IP3_5_4 = 459,\n\tFN_IP3_7_6 = 460,\n\tFN_IP3_9_8 = 461,\n\tFN_IP3_10 = 462,\n\tFN_IP3_11 = 463,\n\tFN_IP3_12 = 464,\n\tFN_IP3_14_13 = 465,\n\tFN_IP3_17_15 = 466,\n\tFN_IP3_20_18 = 467,\n\tFN_IP3_23_21 = 468,\n\tFN_IP3_26_24 = 469,\n\tFN_IP3_29_27 = 470,\n\tFN_IP3_30 = 471,\n\tFN_IP3_31 = 472,\n\tFN_WE0_N = 473,\n\tFN_WE1_N = 474,\n\tFN_IP4_1_0 = 475,\n\tFN_IP7_31 = 476,\n\tFN_DACK0 = 477,\n\tFN_IP4_4_2 = 478,\n\tFN_IP4_7_5 = 479,\n\tFN_IP4_9_8 = 480,\n\tFN_IP4_11_10 = 481,\n\tFN_IP4_13_12 = 482,\n\tFN_IP4_15_14 = 483,\n\tFN_IP4_17_16 = 484,\n\tFN_IP4_19_18 = 485,\n\tFN_IP4_22_20 = 486,\n\tFN_IP4_25_23 = 487,\n\tFN_IP4_27_26 = 488,\n\tFN_IP4_29_28 = 489,\n\tFN_IP4_31_30 = 490,\n\tFN_IP5_1_0 = 491,\n\tFN_IP5_3_2 = 492,\n\tFN_IP5_5_4 = 493,\n\tFN_IP5_8_6 = 494,\n\tFN_IP5_11_9 = 495,\n\tFN_IP5_13_12 = 496,\n\tFN_IP5_15_14 = 497,\n\tFN_IP5_17_16 = 498,\n\tFN_IP5_19_18 = 499,\n\tFN_IP5_21_20 = 500,\n\tFN_IP5_23_22 = 501,\n\tFN_IP5_25_24 = 502,\n\tFN_IP5_27_26 = 503,\n\tFN_IP5_29_28 = 504,\n\tFN_IP5_31_30 = 505,\n\tFN_IP6_1_0 = 506,\n\tFN_IP6_3_2 = 507,\n\tFN_IP6_5_4 = 508,\n\tFN_IP6_7_6 = 509,\n\tFN_IP6_8 = 510,\n\tFN_IP6_9 = 511,\n\tFN_IP6_10 = 512,\n\tFN_IP6_11 = 513,\n\tFN_IP6_12 = 514,\n\tFN_IP6_13 = 515,\n\tFN_IP6_14 = 516,\n\tFN_IP6_15 = 517,\n\tFN_IP6_16 = 518,\n\tFN_IP6_19_17 = 519,\n\tFN_IP6_22_20 = 520,\n\tFN_IP6_25_23 = 521,\n\tFN_IP6_28_26 = 522,\n\tFN_IP6_31_29 = 523,\n\tFN_IP7_2_0 = 524,\n\tFN_IP7_5_3 = 525,\n\tFN_IP7_8_6 = 526,\n\tFN_IP7_11_9 = 527,\n\tFN_IP7_14_12 = 528,\n\tFN_IP7_17_15 = 529,\n\tFN_IP7_20_18 = 530,\n\tFN_IP7_23_21 = 531,\n\tFN_IP7_26_24 = 532,\n\tFN_IP7_29_27 = 533,\n\tFN_IP8_2_0 = 534,\n\tFN_IP8_5_3 = 535,\n\tFN_IP8_8_6 = 536,\n\tFN_IP8_11_9 = 537,\n\tFN_IP8_14_12 = 538,\n\tFN_IP8_16_15 = 539,\n\tFN_IP8_19_17 = 540,\n\tFN_IP8_22_20 = 541,\n\tFN_IP8_25_23 = 542,\n\tFN_IP8_28_26 = 543,\n\tFN_IP8_31_29 = 544,\n\tFN_IP9_2_0 = 545,\n\tFN_IP9_5_3 = 546,\n\tFN_IP9_8_6 = 547,\n\tFN_IP9_11_9 = 548,\n\tFN_IP9_14_12 = 549,\n\tFN_IP9_16_15 = 550,\n\tFN_IP9_18_17 = 551,\n\tFN_IP9_21_19 = 552,\n\tFN_IP9_24_22 = 553,\n\tFN_IP9_27_25 = 554,\n\tFN_IP9_30_28 = 555,\n\tFN_IP10_2_0 = 556,\n\tFN_IP10_5_3 = 557,\n\tFN_IP10_8_6 = 558,\n\tFN_IP10_11_9 = 559,\n\tFN_IP10_14_12 = 560,\n\tFN_IP10_17_15 = 561,\n\tFN_IP10_20_18 = 562,\n\tFN_IP10_23_21 = 563,\n\tFN_IP10_26_24 = 564,\n\tFN_IP10_29_27 = 565,\n\tFN_IP10_31_30 = 566,\n\tFN_IP11_2_0 = 567,\n\tFN_IP11_5_3 = 568,\n\tFN_IP11_7_6 = 569,\n\tFN_IP11_10_8 = 570,\n\tFN_IP11_13_11 = 571,\n\tFN_IP11_15_14 = 572,\n\tFN_IP11_17_16 = 573,\n\tFN_IP11_20_18 = 574,\n\tFN_IP11_23_21 = 575,\n\tFN_IP11_26_24 = 576,\n\tFN_IP11_29_27 = 577,\n\tFN_IP12_2_0 = 578,\n\tFN_IP12_5_3 = 579,\n\tFN_IP12_8_6 = 580,\n\tFN_IP12_10_9 = 581,\n\tFN_IP12_12_11 = 582,\n\tFN_IP12_14_13 = 583,\n\tFN_IP12_17_15 = 584,\n\tFN_IP12_20_18 = 585,\n\tFN_IP12_23_21 = 586,\n\tFN_IP12_26_24 = 587,\n\tFN_IP12_29_27 = 588,\n\tFN_IP13_2_0 = 589,\n\tFN_IP13_5_3 = 590,\n\tFN_IP13_8_6 = 591,\n\tFN_IP13_11_9 = 592,\n\tFN_IP13_14_12 = 593,\n\tFN_IP13_17_15 = 594,\n\tFN_IP13_20_18 = 595,\n\tFN_IP13_23_21 = 596,\n\tFN_IP13_26_24 = 597,\n\tFN_USB0_PWEN = 598,\n\tFN_USB0_OVC = 599,\n\tFN_USB1_PWEN = 600,\n\tFN_USB1_OVC = 601,\n\tFN_SD0_CLK = 602,\n\tFN_SD0_CMD = 603,\n\tFN_SD0_DATA0 = 604,\n\tFN_SD0_DATA1 = 605,\n\tFN_SD0_DATA2 = 606,\n\tFN_SD0_DATA3 = 607,\n\tFN_SD0_CD = 608,\n\tFN_SD0_WP = 609,\n\tFN_SD1_CLK = 610,\n\tFN_SD1_CMD = 611,\n\tFN_SD1_DATA0 = 612,\n\tFN_SD1_DATA1 = 613,\n\tFN_SD1_DATA2 = 614,\n\tFN_SD1_DATA3 = 615,\n\tFN_IP0_0 = 616,\n\tFN_IP0_9_8 = 617,\n\tFN_IP0_10 = 618,\n\tFN_IP0_11 = 619,\n\tFN_IP0_12 = 620,\n\tFN_IP0_13 = 621,\n\tFN_IP0_14 = 622,\n\tFN_IP0_15 = 623,\n\tFN_IP0_16 = 624,\n\tFN_IP0_17 = 625,\n\tFN_IP0_19_18 = 626,\n\tFN_IP0_21_20 = 627,\n\tFN_SD1_CD = 628,\n\tFN_CAN0_RX = 629,\n\tFN_SD1_WP = 630,\n\tFN_IRQ7 = 631,\n\tFN_CAN0_TX = 632,\n\tFN_MMC_CLK = 633,\n\tFN_SD2_CLK = 634,\n\tFN_MMC_CMD = 635,\n\tFN_SD2_CMD = 636,\n\tFN_MMC_D0 = 637,\n\tFN_SD2_DATA0 = 638,\n\tFN_MMC_D1 = 639,\n\tFN_SD2_DATA1 = 640,\n\tFN_MMC_D2 = 641,\n\tFN_SD2_DATA2 = 642,\n\tFN_MMC_D3 = 643,\n\tFN_SD2_DATA3 = 644,\n\tFN_MMC_D4 = 645,\n\tFN_SD2_CD = 646,\n\tFN_MMC_D5 = 647,\n\tFN_SD2_WP = 648,\n\tFN_MMC_D6 = 649,\n\tFN_SCIF0_RXD = 650,\n\tFN_I2C2_SCL_B = 651,\n\tFN_CAN1_RX = 652,\n\tFN_MMC_D7 = 653,\n\tFN_SCIF0_TXD = 654,\n\tFN_I2C2_SDA_B = 655,\n\tFN_CAN1_TX = 656,\n\tFN_D0 = 657,\n\tFN_SCIFA3_SCK_B = 658,\n\tFN_IRQ4 = 659,\n\tFN_D1 = 660,\n\tFN_SCIFA3_RXD_B = 661,\n\tFN_D2 = 662,\n\tFN_SCIFA3_TXD_B = 663,\n\tFN_D3 = 664,\n\tFN_I2C3_SCL_B = 665,\n\tFN_SCIF5_RXD_B = 666,\n\tFN_D4 = 667,\n\tFN_I2C3_SDA_B = 668,\n\tFN_SCIF5_TXD_B = 669,\n\tFN_D5 = 670,\n\tFN_SCIF4_RXD_B = 671,\n\tFN_I2C0_SCL_D = 672,\n\tFN_D6 = 673,\n\tFN_SCIF4_TXD_B = 674,\n\tFN_I2C0_SDA_D = 675,\n\tFN_D7 = 676,\n\tFN_IRQ3 = 677,\n\tFN_TCLK1 = 678,\n\tFN_PWM6_B = 679,\n\tFN_D8 = 680,\n\tFN_HSCIF2_HRX = 681,\n\tFN_I2C1_SCL_B = 682,\n\tFN_D9 = 683,\n\tFN_HSCIF2_HTX = 684,\n\tFN_I2C1_SDA_B = 685,\n\tFN_D10 = 686,\n\tFN_HSCIF2_HSCK = 687,\n\tFN_SCIF1_SCK_C = 688,\n\tFN_IRQ6 = 689,\n\tFN_PWM5_C = 690,\n\tFN_D11 = 691,\n\tFN_HSCIF2_HCTS_N = 692,\n\tFN_SCIF1_RXD_C = 693,\n\tFN_I2C1_SCL_D = 694,\n\tFN_D12 = 695,\n\tFN_HSCIF2_HRTS_N = 696,\n\tFN_SCIF1_TXD_C = 697,\n\tFN_I2C1_SDA_D = 698,\n\tFN_D13 = 699,\n\tFN_SCIFA1_SCK = 700,\n\tFN_PWM2_C = 701,\n\tFN_TCLK2_B = 702,\n\tFN_D14 = 703,\n\tFN_SCIFA1_RXD = 704,\n\tFN_I2C5_SCL_B = 705,\n\tFN_D15 = 706,\n\tFN_SCIFA1_TXD = 707,\n\tFN_I2C5_SDA_B = 708,\n\tFN_A0 = 709,\n\tFN_SCIFB1_SCK = 710,\n\tFN_PWM3_B = 711,\n\tFN_A1 = 712,\n\tFN_SCIFB1_TXD = 713,\n\tFN_A3 = 714,\n\tFN_SCIFB0_SCK = 715,\n\tFN_A4 = 716,\n\tFN_SCIFB0_TXD = 717,\n\tFN_A5 = 718,\n\tFN_SCIFB0_RXD = 719,\n\tFN_PWM4_B = 720,\n\tFN_TPUTO3_C = 721,\n\tFN_A6 = 722,\n\tFN_SCIFB0_CTS_N = 723,\n\tFN_SCIFA4_RXD_B = 724,\n\tFN_TPUTO2_C = 725,\n\tFN_A7 = 726,\n\tFN_SCIFB0_RTS_N = 727,\n\tFN_SCIFA4_TXD_B = 728,\n\tFN_A8 = 729,\n\tFN_MSIOF1_RXD = 730,\n\tFN_SCIFA0_RXD_B = 731,\n\tFN_A9 = 732,\n\tFN_MSIOF1_TXD = 733,\n\tFN_SCIFA0_TXD_B = 734,\n\tFN_A10 = 735,\n\tFN_MSIOF1_SCK = 736,\n\tFN_IIC0_SCL_B = 737,\n\tFN_A11 = 738,\n\tFN_MSIOF1_SYNC = 739,\n\tFN_IIC0_SDA_B = 740,\n\tFN_A12 = 741,\n\tFN_MSIOF1_SS1 = 742,\n\tFN_SCIFA5_RXD_B = 743,\n\tFN_A13 = 744,\n\tFN_MSIOF1_SS2 = 745,\n\tFN_SCIFA5_TXD_B = 746,\n\tFN_A14 = 747,\n\tFN_MSIOF2_RXD = 748,\n\tFN_HSCIF0_HRX_B = 749,\n\tFN_DREQ1_N = 750,\n\tFN_A15 = 751,\n\tFN_MSIOF2_TXD = 752,\n\tFN_HSCIF0_HTX_B = 753,\n\tFN_DACK1 = 754,\n\tFN_A16 = 755,\n\tFN_MSIOF2_SCK = 756,\n\tFN_HSCIF0_HSCK_B = 757,\n\tFN_SPEEDIN = 758,\n\tFN_CAN_CLK_C = 759,\n\tFN_TPUTO2_B = 760,\n\tFN_A17 = 761,\n\tFN_MSIOF2_SYNC = 762,\n\tFN_SCIF4_RXD_E = 763,\n\tFN_CAN1_RX_B = 764,\n\tFN_A18 = 765,\n\tFN_MSIOF2_SS1 = 766,\n\tFN_SCIF4_TXD_E = 767,\n\tFN_CAN1_TX_B = 768,\n\tFN_A19 = 769,\n\tFN_MSIOF2_SS2 = 770,\n\tFN_PWM4 = 771,\n\tFN_TPUTO2 = 772,\n\tFN_A20 = 773,\n\tFN_SPCLK = 774,\n\tFN_A21 = 775,\n\tFN_MOSI_IO0 = 776,\n\tFN_A22 = 777,\n\tFN_MISO_IO1 = 778,\n\tFN_ATADIR1_N = 779,\n\tFN_A23 = 780,\n\tFN_IO2 = 781,\n\tFN_ATAWR1_N = 782,\n\tFN_A24 = 783,\n\tFN_IO3 = 784,\n\tFN_EX_WAIT2 = 785,\n\tFN_A25 = 786,\n\tFN_SSL = 787,\n\tFN_ATARD1_N = 788,\n\tFN_CS0_N = 789,\n\tFN_VI1_DATA8 = 790,\n\tFN_CS1_N_A26 = 791,\n\tFN_VI1_DATA9 = 792,\n\tFN_EX_CS0_N = 793,\n\tFN_VI1_DATA10 = 794,\n\tFN_EX_CS1_N = 795,\n\tFN_TPUTO3_B = 796,\n\tFN_SCIFB2_RXD = 797,\n\tFN_VI1_DATA11 = 798,\n\tFN_EX_CS2_N = 799,\n\tFN_PWM0 = 800,\n\tFN_SCIF4_RXD_C = 801,\n\tFN_TS_SDATA_B = 802,\n\tFN_TPUTO3 = 803,\n\tFN_SCIFB2_TXD = 804,\n\tFN_EX_CS3_N = 805,\n\tFN_SCIFA2_SCK = 806,\n\tFN_SCIF4_TXD_C = 807,\n\tFN_TS_SCK_B = 808,\n\tFN_BPFCLK = 809,\n\tFN_SCIFB2_SCK = 810,\n\tFN_EX_CS4_N = 811,\n\tFN_SCIFA2_RXD = 812,\n\tFN_I2C2_SCL_E = 813,\n\tFN_TS_SDEN_B = 814,\n\tFN_FMCLK = 815,\n\tFN_SCIFB2_CTS_N = 816,\n\tFN_EX_CS5_N = 817,\n\tFN_SCIFA2_TXD = 818,\n\tFN_I2C2_SDA_E = 819,\n\tFN_TS_SPSYNC_B = 820,\n\tFN_FMIN = 821,\n\tFN_SCIFB2_RTS_N = 822,\n\tFN_BS_N = 823,\n\tFN_DRACK0 = 824,\n\tFN_PWM1_C = 825,\n\tFN_TPUTO0_C = 826,\n\tFN_ATACS01_N = 827,\n\tFN_RD_N = 828,\n\tFN_ATACS11_N = 829,\n\tFN_RD_WR_N = 830,\n\tFN_ATAG1_N = 831,\n\tFN_EX_WAIT0 = 832,\n\tFN_CAN_CLK_B = 833,\n\tFN_SCIF_CLK = 834,\n\tFN_DU0_DR0 = 835,\n\tFN_LCDOUT16 = 836,\n\tFN_SCIF5_RXD_C = 837,\n\tFN_I2C2_SCL_D = 838,\n\tFN_DU0_DR1 = 839,\n\tFN_LCDOUT17 = 840,\n\tFN_SCIF5_TXD_C = 841,\n\tFN_I2C2_SDA_D = 842,\n\tFN_DU0_DR2 = 843,\n\tFN_LCDOUT18 = 844,\n\tFN_DU0_DR3 = 845,\n\tFN_LCDOUT19 = 846,\n\tFN_DU0_DR4 = 847,\n\tFN_LCDOUT20 = 848,\n\tFN_DU0_DR5 = 849,\n\tFN_LCDOUT21 = 850,\n\tFN_DU0_DR6 = 851,\n\tFN_LCDOUT22 = 852,\n\tFN_DU0_DR7 = 853,\n\tFN_LCDOUT23 = 854,\n\tFN_DU0_DG0 = 855,\n\tFN_LCDOUT8 = 856,\n\tFN_SCIFA0_RXD_C = 857,\n\tFN_I2C3_SCL_D = 858,\n\tFN_DU0_DG1 = 859,\n\tFN_LCDOUT9 = 860,\n\tFN_SCIFA0_TXD_C = 861,\n\tFN_I2C3_SDA_D = 862,\n\tFN_DU0_DG2 = 863,\n\tFN_LCDOUT10 = 864,\n\tFN_DU0_DG3 = 865,\n\tFN_LCDOUT11 = 866,\n\tFN_DU0_DG4 = 867,\n\tFN_LCDOUT12 = 868,\n\tFN_DU0_DG5 = 869,\n\tFN_LCDOUT13 = 870,\n\tFN_DU0_DG6 = 871,\n\tFN_LCDOUT14 = 872,\n\tFN_DU0_DG7 = 873,\n\tFN_LCDOUT15 = 874,\n\tFN_DU0_DB0 = 875,\n\tFN_LCDOUT0 = 876,\n\tFN_SCIFA4_RXD_C = 877,\n\tFN_I2C4_SCL_D = 878,\n\tFN_CAN0_RX_C = 879,\n\tFN_DU0_DB1 = 880,\n\tFN_LCDOUT1 = 881,\n\tFN_SCIFA4_TXD_C = 882,\n\tFN_I2C4_SDA_D = 883,\n\tFN_CAN0_TX_C = 884,\n\tFN_DU0_DB2 = 885,\n\tFN_LCDOUT2 = 886,\n\tFN_DU0_DB3 = 887,\n\tFN_LCDOUT3 = 888,\n\tFN_DU0_DB4 = 889,\n\tFN_LCDOUT4 = 890,\n\tFN_DU0_DB5 = 891,\n\tFN_LCDOUT5 = 892,\n\tFN_DU0_DB6 = 893,\n\tFN_LCDOUT6 = 894,\n\tFN_DU0_DB7 = 895,\n\tFN_LCDOUT7 = 896,\n\tFN_DU0_DOTCLKIN = 897,\n\tFN_QSTVA_QVS = 898,\n\tFN_DU0_DOTCLKOUT0 = 899,\n\tFN_QCLK = 900,\n\tFN_DU0_DOTCLKOUT1 = 901,\n\tFN_QSTVB_QVE = 902,\n\tFN_DU0_EXHSYNC_DU0_HSYNC = 903,\n\tFN_QSTH_QHS = 904,\n\tFN_DU0_EXVSYNC_DU0_VSYNC = 905,\n\tFN_QSTB_QHE = 906,\n\tFN_DU0_EXODDF_DU0_ODDF_DISP_CDE = 907,\n\tFN_QCPV_QDE = 908,\n\tFN_DU0_DISP = 909,\n\tFN_QPOLA = 910,\n\tFN_DU0_CDE = 911,\n\tFN_QPOLB = 912,\n\tFN_VI0_CLK = 913,\n\tFN_AVB_RX_CLK = 914,\n\tFN_VI0_DATA0_VI0_B0 = 915,\n\tFN_AVB_RX_DV = 916,\n\tFN_VI0_DATA1_VI0_B1 = 917,\n\tFN_AVB_RXD0 = 918,\n\tFN_VI0_DATA2_VI0_B2 = 919,\n\tFN_AVB_RXD1 = 920,\n\tFN_VI0_DATA3_VI0_B3 = 921,\n\tFN_AVB_RXD2 = 922,\n\tFN_VI0_DATA4_VI0_B4 = 923,\n\tFN_AVB_RXD3 = 924,\n\tFN_VI0_DATA5_VI0_B5 = 925,\n\tFN_AVB_RXD4 = 926,\n\tFN_VI0_DATA6_VI0_B6 = 927,\n\tFN_AVB_RXD5 = 928,\n\tFN_VI0_DATA7_VI0_B7 = 929,\n\tFN_AVB_RXD6 = 930,\n\tFN_VI0_CLKENB = 931,\n\tFN_I2C3_SCL = 932,\n\tFN_SCIFA5_RXD_C = 933,\n\tFN_IETX_C = 934,\n\tFN_AVB_RXD7 = 935,\n\tFN_VI0_FIELD = 936,\n\tFN_I2C3_SDA = 937,\n\tFN_SCIFA5_TXD_C = 938,\n\tFN_IECLK_C = 939,\n\tFN_AVB_RX_ER = 940,\n\tFN_VI0_HSYNC_N = 941,\n\tFN_SCIF0_RXD_B = 942,\n\tFN_I2C0_SCL_C = 943,\n\tFN_IERX_C = 944,\n\tFN_AVB_COL = 945,\n\tFN_VI0_VSYNC_N = 946,\n\tFN_SCIF0_TXD_B = 947,\n\tFN_I2C0_SDA_C = 948,\n\tFN_AUDIO_CLKOUT_B = 949,\n\tFN_AVB_TX_EN = 950,\n\tFN_ETH_MDIO = 951,\n\tFN_VI0_G0 = 952,\n\tFN_MSIOF2_RXD_B = 953,\n\tFN_I2C5_SCL_D = 954,\n\tFN_AVB_TX_CLK = 955,\n\tFN_ADIDATA = 956,\n\tFN_ETH_CRS_DV = 957,\n\tFN_VI0_G1 = 958,\n\tFN_MSIOF2_TXD_B = 959,\n\tFN_I2C5_SDA_D = 960,\n\tFN_AVB_TXD0 = 961,\n\tFN_ADICS_SAMP = 962,\n\tFN_ETH_RX_ER = 963,\n\tFN_VI0_G2 = 964,\n\tFN_MSIOF2_SCK_B = 965,\n\tFN_CAN0_RX_B = 966,\n\tFN_AVB_TXD1 = 967,\n\tFN_ADICLK = 968,\n\tFN_ETH_RXD0 = 969,\n\tFN_VI0_G3 = 970,\n\tFN_MSIOF2_SYNC_B = 971,\n\tFN_CAN0_TX_B = 972,\n\tFN_AVB_TXD2 = 973,\n\tFN_ADICHS0 = 974,\n\tFN_ETH_RXD1 = 975,\n\tFN_VI0_G4 = 976,\n\tFN_MSIOF2_SS1_B = 977,\n\tFN_SCIF4_RXD_D = 978,\n\tFN_AVB_TXD3 = 979,\n\tFN_ADICHS1 = 980,\n\tFN_ETH_LINK = 981,\n\tFN_VI0_G5 = 982,\n\tFN_MSIOF2_SS2_B = 983,\n\tFN_SCIF4_TXD_D = 984,\n\tFN_AVB_TXD4 = 985,\n\tFN_ADICHS2 = 986,\n\tFN_ETH_REFCLK = 987,\n\tFN_VI0_G6 = 988,\n\tFN_SCIF2_SCK_C = 989,\n\tFN_AVB_TXD5 = 990,\n\tFN_SSI_SCK5_B = 991,\n\tFN_ETH_TXD1 = 992,\n\tFN_VI0_G7 = 993,\n\tFN_SCIF2_RXD_C = 994,\n\tFN_IIC0_SCL_D = 995,\n\tFN_AVB_TXD6 = 996,\n\tFN_SSI_WS5_B = 997,\n\tFN_ETH_TX_EN = 998,\n\tFN_VI0_R0 = 999,\n\tFN_SCIF2_TXD_C = 1000,\n\tFN_IIC0_SDA_D = 1001,\n\tFN_AVB_TXD7 = 1002,\n\tFN_SSI_SDATA5_B = 1003,\n\tFN_ETH_MAGIC = 1004,\n\tFN_VI0_R1 = 1005,\n\tFN_SCIF3_SCK_B = 1006,\n\tFN_AVB_TX_ER = 1007,\n\tFN_SSI_SCK6_B = 1008,\n\tFN_ETH_TXD0 = 1009,\n\tFN_VI0_R2 = 1010,\n\tFN_SCIF3_RXD_B = 1011,\n\tFN_I2C4_SCL_E = 1012,\n\tFN_AVB_GTX_CLK = 1013,\n\tFN_SSI_WS6_B = 1014,\n\tFN_DREQ0_N = 1015,\n\tFN_SCIFB1_RXD = 1016,\n\tFN_ETH_MDC = 1017,\n\tFN_VI0_R3 = 1018,\n\tFN_SCIF3_TXD_B = 1019,\n\tFN_I2C4_SDA_E = 1020,\n\tFN_AVB_MDC = 1021,\n\tFN_SSI_SDATA6_B = 1022,\n\tFN_HSCIF0_HRX = 1023,\n\tFN_VI0_R4 = 1024,\n\tFN_I2C1_SCL_C = 1025,\n\tFN_AUDIO_CLKA_B = 1026,\n\tFN_AVB_MDIO = 1027,\n\tFN_SSI_SCK78_B = 1028,\n\tFN_HSCIF0_HTX = 1029,\n\tFN_VI0_R5 = 1030,\n\tFN_I2C1_SDA_C = 1031,\n\tFN_AUDIO_CLKB_B = 1032,\n\tFN_AVB_LINK = 1033,\n\tFN_SSI_WS78_B = 1034,\n\tFN_HSCIF0_HCTS_N = 1035,\n\tFN_VI0_R6 = 1036,\n\tFN_SCIF0_RXD_D = 1037,\n\tFN_I2C0_SCL_E = 1038,\n\tFN_AVB_MAGIC = 1039,\n\tFN_SSI_SDATA7_B = 1040,\n\tFN_HSCIF0_HRTS_N = 1041,\n\tFN_VI0_R7 = 1042,\n\tFN_SCIF0_TXD_D = 1043,\n\tFN_I2C0_SDA_E = 1044,\n\tFN_AVB_PHY_INT = 1045,\n\tFN_SSI_SDATA8_B = 1046,\n\tFN_HSCIF0_HSCK = 1047,\n\tFN_SCIF_CLK_B = 1048,\n\tFN_AVB_CRS = 1049,\n\tFN_AUDIO_CLKC_B = 1050,\n\tFN_I2C0_SCL = 1051,\n\tFN_SCIF0_RXD_C = 1052,\n\tFN_PWM5 = 1053,\n\tFN_TCLK1_B = 1054,\n\tFN_AVB_GTXREFCLK = 1055,\n\tFN_CAN1_RX_D = 1056,\n\tFN_TPUTO0_B = 1057,\n\tFN_I2C0_SDA = 1058,\n\tFN_SCIF0_TXD_C = 1059,\n\tFN_TPUTO0 = 1060,\n\tFN_CAN_CLK = 1061,\n\tFN_DVC_MUTE = 1062,\n\tFN_CAN1_TX_D = 1063,\n\tFN_I2C1_SCL = 1064,\n\tFN_SCIF4_RXD = 1065,\n\tFN_PWM5_B = 1066,\n\tFN_DU1_DR0 = 1067,\n\tFN_TS_SDATA_D = 1068,\n\tFN_TPUTO1_B = 1069,\n\tFN_I2C1_SDA = 1070,\n\tFN_SCIF4_TXD = 1071,\n\tFN_IRQ5 = 1072,\n\tFN_DU1_DR1 = 1073,\n\tFN_TS_SCK_D = 1074,\n\tFN_BPFCLK_C = 1075,\n\tFN_MSIOF0_RXD = 1076,\n\tFN_SCIF5_RXD = 1077,\n\tFN_I2C2_SCL_C = 1078,\n\tFN_DU1_DR2 = 1079,\n\tFN_TS_SDEN_D = 1080,\n\tFN_FMCLK_C = 1081,\n\tFN_MSIOF0_TXD = 1082,\n\tFN_SCIF5_TXD = 1083,\n\tFN_I2C2_SDA_C = 1084,\n\tFN_DU1_DR3 = 1085,\n\tFN_TS_SPSYNC_D = 1086,\n\tFN_FMIN_C = 1087,\n\tFN_MSIOF0_SCK = 1088,\n\tFN_IRQ0 = 1089,\n\tFN_TS_SDATA = 1090,\n\tFN_DU1_DR4 = 1091,\n\tFN_TPUTO1_C = 1092,\n\tFN_MSIOF0_SYNC = 1093,\n\tFN_PWM1 = 1094,\n\tFN_TS_SCK = 1095,\n\tFN_DU1_DR5 = 1096,\n\tFN_BPFCLK_B = 1097,\n\tFN_MSIOF0_SS1 = 1098,\n\tFN_SCIFA0_RXD = 1099,\n\tFN_TS_SDEN = 1100,\n\tFN_DU1_DR6 = 1101,\n\tFN_FMCLK_B = 1102,\n\tFN_MSIOF0_SS2 = 1103,\n\tFN_SCIFA0_TXD = 1104,\n\tFN_TS_SPSYNC = 1105,\n\tFN_DU1_DR7 = 1106,\n\tFN_FMIN_B = 1107,\n\tFN_HSCIF1_HRX = 1108,\n\tFN_I2C4_SCL = 1109,\n\tFN_PWM6 = 1110,\n\tFN_DU1_DG0 = 1111,\n\tFN_HSCIF1_HTX = 1112,\n\tFN_I2C4_SDA = 1113,\n\tFN_TPUTO1 = 1114,\n\tFN_DU1_DG1 = 1115,\n\tFN_HSCIF1_HSCK = 1116,\n\tFN_PWM2 = 1117,\n\tFN_IETX = 1118,\n\tFN_DU1_DG2 = 1119,\n\tFN_REMOCON_B = 1120,\n\tFN_SPEEDIN_B = 1121,\n\tFN_HSCIF1_HCTS_N = 1122,\n\tFN_SCIFA4_RXD = 1123,\n\tFN_IECLK = 1124,\n\tFN_DU1_DG3 = 1125,\n\tFN_SSI_SCK1_B = 1126,\n\tFN_HSCIF1_HRTS_N = 1127,\n\tFN_SCIFA4_TXD = 1128,\n\tFN_IERX = 1129,\n\tFN_DU1_DG4 = 1130,\n\tFN_SSI_WS1_B = 1131,\n\tFN_SCIF1_SCK = 1132,\n\tFN_PWM3 = 1133,\n\tFN_TCLK2 = 1134,\n\tFN_DU1_DG5 = 1135,\n\tFN_SSI_SDATA1_B = 1136,\n\tFN_SCIF1_RXD = 1137,\n\tFN_I2C5_SCL = 1138,\n\tFN_DU1_DG6 = 1139,\n\tFN_SSI_SCK2_B = 1140,\n\tFN_SCIF1_TXD = 1141,\n\tFN_I2C5_SDA = 1142,\n\tFN_DU1_DG7 = 1143,\n\tFN_SSI_WS2_B = 1144,\n\tFN_SCIF2_RXD = 1145,\n\tFN_IIC0_SCL = 1146,\n\tFN_DU1_DB0 = 1147,\n\tFN_SSI_SDATA2_B = 1148,\n\tFN_SCIF2_TXD = 1149,\n\tFN_IIC0_SDA = 1150,\n\tFN_DU1_DB1 = 1151,\n\tFN_SSI_SCK9_B = 1152,\n\tFN_SCIF2_SCK = 1153,\n\tFN_IRQ1 = 1154,\n\tFN_DU1_DB2 = 1155,\n\tFN_SSI_WS9_B = 1156,\n\tFN_SCIF3_SCK = 1157,\n\tFN_IRQ2 = 1158,\n\tFN_BPFCLK_D = 1159,\n\tFN_DU1_DB3 = 1160,\n\tFN_SSI_SDATA9_B = 1161,\n\tFN_SCIF3_RXD = 1162,\n\tFN_I2C1_SCL_E = 1163,\n\tFN_FMCLK_D = 1164,\n\tFN_DU1_DB4 = 1165,\n\tFN_AUDIO_CLKA_C = 1166,\n\tFN_SSI_SCK4_B = 1167,\n\tFN_SCIF3_TXD = 1168,\n\tFN_I2C1_SDA_E = 1169,\n\tFN_FMIN_D = 1170,\n\tFN_DU1_DB5 = 1171,\n\tFN_AUDIO_CLKB_C = 1172,\n\tFN_SSI_WS4_B = 1173,\n\tFN_I2C2_SCL = 1174,\n\tFN_SCIFA5_RXD = 1175,\n\tFN_DU1_DB6 = 1176,\n\tFN_AUDIO_CLKC_C = 1177,\n\tFN_SSI_SDATA4_B = 1178,\n\tFN_I2C2_SDA = 1179,\n\tFN_SCIFA5_TXD = 1180,\n\tFN_DU1_DB7 = 1181,\n\tFN_AUDIO_CLKOUT_C = 1182,\n\tFN_SSI_SCK5 = 1183,\n\tFN_SCIFA3_SCK = 1184,\n\tFN_DU1_DOTCLKIN = 1185,\n\tFN_SSI_WS5 = 1186,\n\tFN_SCIFA3_RXD = 1187,\n\tFN_I2C3_SCL_C = 1188,\n\tFN_DU1_DOTCLKOUT0 = 1189,\n\tFN_SSI_SDATA5 = 1190,\n\tFN_SCIFA3_TXD = 1191,\n\tFN_I2C3_SDA_C = 1192,\n\tFN_DU1_DOTCLKOUT1 = 1193,\n\tFN_SSI_SCK6 = 1194,\n\tFN_SCIFA1_SCK_B = 1195,\n\tFN_DU1_EXHSYNC_DU1_HSYNC = 1196,\n\tFN_SSI_WS6 = 1197,\n\tFN_SCIFA1_RXD_B = 1198,\n\tFN_I2C4_SCL_C = 1199,\n\tFN_DU1_EXVSYNC_DU1_VSYNC = 1200,\n\tFN_SSI_SDATA6 = 1201,\n\tFN_SCIFA1_TXD_B = 1202,\n\tFN_I2C4_SDA_C = 1203,\n\tFN_DU1_EXODDF_DU1_ODDF_DISP_CDE = 1204,\n\tFN_SSI_SCK78 = 1205,\n\tFN_SCIFA2_SCK_B = 1206,\n\tFN_I2C5_SDA_C = 1207,\n\tFN_DU1_DISP = 1208,\n\tFN_SSI_WS78 = 1209,\n\tFN_SCIFA2_RXD_B = 1210,\n\tFN_I2C5_SCL_C = 1211,\n\tFN_DU1_CDE = 1212,\n\tFN_SSI_SDATA7 = 1213,\n\tFN_SCIFA2_TXD_B = 1214,\n\tFN_IRQ8 = 1215,\n\tFN_AUDIO_CLKA_D = 1216,\n\tFN_CAN_CLK_D = 1217,\n\tFN_SSI_SCK0129 = 1218,\n\tFN_MSIOF1_RXD_B = 1219,\n\tFN_SCIF5_RXD_D = 1220,\n\tFN_ADIDATA_B = 1221,\n\tFN_SSI_WS0129 = 1222,\n\tFN_MSIOF1_TXD_B = 1223,\n\tFN_SCIF5_TXD_D = 1224,\n\tFN_ADICS_SAMP_B = 1225,\n\tFN_SSI_SDATA0 = 1226,\n\tFN_MSIOF1_SCK_B = 1227,\n\tFN_PWM0_B = 1228,\n\tFN_ADICLK_B = 1229,\n\tFN_SSI_SCK34 = 1230,\n\tFN_MSIOF1_SYNC_B = 1231,\n\tFN_SCIFA1_SCK_C = 1232,\n\tFN_ADICHS0_B = 1233,\n\tFN_DREQ1_N_B = 1234,\n\tFN_SSI_WS34 = 1235,\n\tFN_MSIOF1_SS1_B = 1236,\n\tFN_SCIFA1_RXD_C = 1237,\n\tFN_ADICHS1_B = 1238,\n\tFN_CAN1_RX_C = 1239,\n\tFN_DACK1_B = 1240,\n\tFN_SSI_SDATA3 = 1241,\n\tFN_MSIOF1_SS2_B = 1242,\n\tFN_SCIFA1_TXD_C = 1243,\n\tFN_ADICHS2_B = 1244,\n\tFN_CAN1_TX_C = 1245,\n\tFN_DREQ2_N = 1246,\n\tFN_SSI_SCK4 = 1247,\n\tFN_MLB_CLK = 1248,\n\tFN_IETX_B = 1249,\n\tFN_SSI_WS4 = 1250,\n\tFN_MLB_SIG = 1251,\n\tFN_IECLK_B = 1252,\n\tFN_SSI_SDATA4 = 1253,\n\tFN_MLB_DAT = 1254,\n\tFN_IERX_B = 1255,\n\tFN_SSI_SDATA8 = 1256,\n\tFN_SCIF1_SCK_B = 1257,\n\tFN_PWM1_B = 1258,\n\tFN_IRQ9 = 1259,\n\tFN_REMOCON = 1260,\n\tFN_DACK2 = 1261,\n\tFN_ETH_MDIO_B = 1262,\n\tFN_SSI_SCK1 = 1263,\n\tFN_SCIF1_RXD_B = 1264,\n\tFN_IIC0_SCL_C = 1265,\n\tFN_VI1_CLK = 1266,\n\tFN_CAN0_RX_D = 1267,\n\tFN_ETH_CRS_DV_B = 1268,\n\tFN_SSI_WS1 = 1269,\n\tFN_SCIF1_TXD_B = 1270,\n\tFN_IIC0_SDA_C = 1271,\n\tFN_VI1_DATA0 = 1272,\n\tFN_CAN0_TX_D = 1273,\n\tFN_ETH_RX_ER_B = 1274,\n\tFN_SSI_SDATA1 = 1275,\n\tFN_HSCIF1_HRX_B = 1276,\n\tFN_VI1_DATA1 = 1277,\n\tFN_ATAWR0_N = 1278,\n\tFN_ETH_RXD0_B = 1279,\n\tFN_SSI_SCK2 = 1280,\n\tFN_HSCIF1_HTX_B = 1281,\n\tFN_VI1_DATA2 = 1282,\n\tFN_ATAG0_N = 1283,\n\tFN_ETH_RXD1_B = 1284,\n\tFN_SSI_WS2 = 1285,\n\tFN_HSCIF1_HCTS_N_B = 1286,\n\tFN_SCIFA0_RXD_D = 1287,\n\tFN_VI1_DATA3 = 1288,\n\tFN_ATACS00_N = 1289,\n\tFN_ETH_LINK_B = 1290,\n\tFN_SSI_SDATA2 = 1291,\n\tFN_HSCIF1_HRTS_N_B = 1292,\n\tFN_SCIFA0_TXD_D = 1293,\n\tFN_VI1_DATA4 = 1294,\n\tFN_ATACS10_N = 1295,\n\tFN_ETH_REFCLK_B = 1296,\n\tFN_SSI_SCK9 = 1297,\n\tFN_SCIF2_SCK_B = 1298,\n\tFN_PWM2_B = 1299,\n\tFN_VI1_DATA5 = 1300,\n\tFN_EX_WAIT1 = 1301,\n\tFN_ETH_TXD1_B = 1302,\n\tFN_SSI_WS9 = 1303,\n\tFN_SCIF2_RXD_B = 1304,\n\tFN_I2C3_SCL_E = 1305,\n\tFN_VI1_DATA6 = 1306,\n\tFN_ATARD0_N = 1307,\n\tFN_ETH_TX_EN_B = 1308,\n\tFN_SSI_SDATA9 = 1309,\n\tFN_SCIF2_TXD_B = 1310,\n\tFN_I2C3_SDA_E = 1311,\n\tFN_VI1_DATA7 = 1312,\n\tFN_ATADIR0_N = 1313,\n\tFN_ETH_MAGIC_B = 1314,\n\tFN_AUDIO_CLKA = 1315,\n\tFN_I2C0_SCL_B = 1316,\n\tFN_SCIFA4_RXD_D = 1317,\n\tFN_VI1_CLKENB = 1318,\n\tFN_TS_SDATA_C = 1319,\n\tFN_ETH_TXD0_B = 1320,\n\tFN_AUDIO_CLKB = 1321,\n\tFN_I2C0_SDA_B = 1322,\n\tFN_SCIFA4_TXD_D = 1323,\n\tFN_VI1_FIELD = 1324,\n\tFN_TS_SCK_C = 1325,\n\tFN_BPFCLK_E = 1326,\n\tFN_ETH_MDC_B = 1327,\n\tFN_AUDIO_CLKC = 1328,\n\tFN_I2C4_SCL_B = 1329,\n\tFN_SCIFA5_RXD_D = 1330,\n\tFN_VI1_HSYNC_N = 1331,\n\tFN_TS_SDEN_C = 1332,\n\tFN_FMCLK_E = 1333,\n\tFN_AUDIO_CLKOUT = 1334,\n\tFN_I2C4_SDA_B = 1335,\n\tFN_SCIFA5_TXD_D = 1336,\n\tFN_VI1_VSYNC_N = 1337,\n\tFN_TS_SPSYNC_C = 1338,\n\tFN_FMIN_E = 1339,\n\tFN_SEL_ADG_0 = 1340,\n\tFN_SEL_ADG_1 = 1341,\n\tFN_SEL_ADG_2 = 1342,\n\tFN_SEL_ADG_3 = 1343,\n\tFN_SEL_CAN_0 = 1344,\n\tFN_SEL_CAN_1 = 1345,\n\tFN_SEL_CAN_2 = 1346,\n\tFN_SEL_CAN_3 = 1347,\n\tFN_SEL_DARC_0 = 1348,\n\tFN_SEL_DARC_1 = 1349,\n\tFN_SEL_DARC_2 = 1350,\n\tFN_SEL_DARC_3 = 1351,\n\tFN_SEL_DARC_4 = 1352,\n\tFN_SEL_ETH_0 = 1353,\n\tFN_SEL_ETH_1 = 1354,\n\tFN_SEL_I2C00_0 = 1355,\n\tFN_SEL_I2C00_1 = 1356,\n\tFN_SEL_I2C00_2 = 1357,\n\tFN_SEL_I2C00_3 = 1358,\n\tFN_SEL_I2C00_4 = 1359,\n\tFN_SEL_I2C01_0 = 1360,\n\tFN_SEL_I2C01_1 = 1361,\n\tFN_SEL_I2C01_2 = 1362,\n\tFN_SEL_I2C01_3 = 1363,\n\tFN_SEL_I2C01_4 = 1364,\n\tFN_SEL_I2C02_0 = 1365,\n\tFN_SEL_I2C02_1 = 1366,\n\tFN_SEL_I2C02_2 = 1367,\n\tFN_SEL_I2C02_3 = 1368,\n\tFN_SEL_I2C02_4 = 1369,\n\tFN_SEL_I2C03_0 = 1370,\n\tFN_SEL_I2C03_1 = 1371,\n\tFN_SEL_I2C03_2 = 1372,\n\tFN_SEL_I2C03_3 = 1373,\n\tFN_SEL_I2C03_4 = 1374,\n\tFN_SEL_I2C04_0 = 1375,\n\tFN_SEL_I2C04_1 = 1376,\n\tFN_SEL_I2C04_2 = 1377,\n\tFN_SEL_I2C04_3 = 1378,\n\tFN_SEL_I2C04_4 = 1379,\n\tFN_SEL_I2C05_0 = 1380,\n\tFN_SEL_I2C05_1 = 1381,\n\tFN_SEL_I2C05_2 = 1382,\n\tFN_SEL_I2C05_3 = 1383,\n\tFN_SEL_IEB_0 = 1384,\n\tFN_SEL_IEB_1 = 1385,\n\tFN_SEL_IEB_2 = 1386,\n\tFN_SEL_IIC0_0 = 1387,\n\tFN_SEL_IIC0_1 = 1388,\n\tFN_SEL_IIC0_2 = 1389,\n\tFN_SEL_IIC0_3 = 1390,\n\tFN_SEL_LBS_0 = 1391,\n\tFN_SEL_LBS_1 = 1392,\n\tFN_SEL_MSI1_0 = 1393,\n\tFN_SEL_MSI1_1 = 1394,\n\tFN_SEL_MSI2_0 = 1395,\n\tFN_SEL_MSI2_1 = 1396,\n\tFN_SEL_RAD_0 = 1397,\n\tFN_SEL_RAD_1 = 1398,\n\tFN_SEL_RCN_0 = 1399,\n\tFN_SEL_RCN_1 = 1400,\n\tFN_SEL_RSP_0 = 1401,\n\tFN_SEL_RSP_1 = 1402,\n\tFN_SEL_SCIFA0_0 = 1403,\n\tFN_SEL_SCIFA0_1 = 1404,\n\tFN_SEL_SCIFA0_2 = 1405,\n\tFN_SEL_SCIFA0_3 = 1406,\n\tFN_SEL_SCIFA1_0 = 1407,\n\tFN_SEL_SCIFA1_1 = 1408,\n\tFN_SEL_SCIFA1_2 = 1409,\n\tFN_SEL_SCIFA2_0 = 1410,\n\tFN_SEL_SCIFA2_1 = 1411,\n\tFN_SEL_SCIFA3_0 = 1412,\n\tFN_SEL_SCIFA3_1 = 1413,\n\tFN_SEL_SCIFA4_0 = 1414,\n\tFN_SEL_SCIFA4_1 = 1415,\n\tFN_SEL_SCIFA4_2 = 1416,\n\tFN_SEL_SCIFA4_3 = 1417,\n\tFN_SEL_SCIFA5_0 = 1418,\n\tFN_SEL_SCIFA5_1 = 1419,\n\tFN_SEL_SCIFA5_2 = 1420,\n\tFN_SEL_SCIFA5_3 = 1421,\n\tFN_SEL_TMU_0 = 1422,\n\tFN_SEL_TMU_1 = 1423,\n\tFN_SEL_TSIF0_0 = 1424,\n\tFN_SEL_TSIF0_1 = 1425,\n\tFN_SEL_TSIF0_2 = 1426,\n\tFN_SEL_TSIF0_3 = 1427,\n\tFN_SEL_CAN0_0 = 1428,\n\tFN_SEL_CAN0_1 = 1429,\n\tFN_SEL_CAN0_2 = 1430,\n\tFN_SEL_CAN0_3 = 1431,\n\tFN_SEL_CAN1_0 = 1432,\n\tFN_SEL_CAN1_1 = 1433,\n\tFN_SEL_CAN1_2 = 1434,\n\tFN_SEL_CAN1_3 = 1435,\n\tFN_SEL_HSCIF0_0 = 1436,\n\tFN_SEL_HSCIF0_1 = 1437,\n\tFN_SEL_HSCIF1_0 = 1438,\n\tFN_SEL_HSCIF1_1 = 1439,\n\tFN_SEL_SCIF0_0 = 1440,\n\tFN_SEL_SCIF0_1 = 1441,\n\tFN_SEL_SCIF0_2 = 1442,\n\tFN_SEL_SCIF0_3 = 1443,\n\tFN_SEL_SCIF1_0 = 1444,\n\tFN_SEL_SCIF1_1 = 1445,\n\tFN_SEL_SCIF1_2 = 1446,\n\tFN_SEL_SCIF2_0 = 1447,\n\tFN_SEL_SCIF2_1 = 1448,\n\tFN_SEL_SCIF2_2 = 1449,\n\tFN_SEL_SCIF3_0 = 1450,\n\tFN_SEL_SCIF3_1 = 1451,\n\tFN_SEL_SCIF4_0 = 1452,\n\tFN_SEL_SCIF4_1 = 1453,\n\tFN_SEL_SCIF4_2 = 1454,\n\tFN_SEL_SCIF4_3 = 1455,\n\tFN_SEL_SCIF4_4 = 1456,\n\tFN_SEL_SCIF5_0 = 1457,\n\tFN_SEL_SCIF5_1 = 1458,\n\tFN_SEL_SCIF5_2 = 1459,\n\tFN_SEL_SCIF5_3 = 1460,\n\tFN_SEL_SSI1_0 = 1461,\n\tFN_SEL_SSI1_1 = 1462,\n\tFN_SEL_SSI2_0 = 1463,\n\tFN_SEL_SSI2_1 = 1464,\n\tFN_SEL_SSI4_0 = 1465,\n\tFN_SEL_SSI4_1 = 1466,\n\tFN_SEL_SSI5_0 = 1467,\n\tFN_SEL_SSI5_1 = 1468,\n\tFN_SEL_SSI6_0 = 1469,\n\tFN_SEL_SSI6_1 = 1470,\n\tFN_SEL_SSI7_0 = 1471,\n\tFN_SEL_SSI7_1 = 1472,\n\tFN_SEL_SSI8_0 = 1473,\n\tFN_SEL_SSI8_1 = 1474,\n\tFN_SEL_SSI9_0 = 1475,\n\tFN_SEL_SSI9_1 = 1476,\n\tPINMUX_FUNCTION_END = 1477,\n\tPINMUX_MARK_BEGIN = 1478,\n\tA2_MARK = 1479,\n\tWE0_N_MARK = 1480,\n\tWE1_N_MARK = 1481,\n\tDACK0_MARK = 1482,\n\tUSB0_PWEN_MARK = 1483,\n\tUSB0_OVC_MARK = 1484,\n\tUSB1_PWEN_MARK = 1485,\n\tUSB1_OVC_MARK = 1486,\n\tSD0_CLK_MARK = 1487,\n\tSD0_CMD_MARK = 1488,\n\tSD0_DATA0_MARK = 1489,\n\tSD0_DATA1_MARK = 1490,\n\tSD0_DATA2_MARK = 1491,\n\tSD0_DATA3_MARK = 1492,\n\tSD0_CD_MARK = 1493,\n\tSD0_WP_MARK = 1494,\n\tSD1_CLK_MARK = 1495,\n\tSD1_CMD_MARK = 1496,\n\tSD1_DATA0_MARK = 1497,\n\tSD1_DATA1_MARK = 1498,\n\tSD1_DATA2_MARK = 1499,\n\tSD1_DATA3_MARK = 1500,\n\tSD1_CD_MARK = 1501,\n\tCAN0_RX_MARK = 1502,\n\tSD1_WP_MARK = 1503,\n\tIRQ7_MARK = 1504,\n\tCAN0_TX_MARK = 1505,\n\tMMC_CLK_MARK = 1506,\n\tSD2_CLK_MARK = 1507,\n\tMMC_CMD_MARK = 1508,\n\tSD2_CMD_MARK = 1509,\n\tMMC_D0_MARK = 1510,\n\tSD2_DATA0_MARK = 1511,\n\tMMC_D1_MARK = 1512,\n\tSD2_DATA1_MARK = 1513,\n\tMMC_D2_MARK = 1514,\n\tSD2_DATA2_MARK = 1515,\n\tMMC_D3_MARK = 1516,\n\tSD2_DATA3_MARK = 1517,\n\tMMC_D4_MARK = 1518,\n\tSD2_CD_MARK = 1519,\n\tMMC_D5_MARK = 1520,\n\tSD2_WP_MARK = 1521,\n\tMMC_D6_MARK = 1522,\n\tSCIF0_RXD_MARK = 1523,\n\tI2C2_SCL_B_MARK = 1524,\n\tCAN1_RX_MARK = 1525,\n\tMMC_D7_MARK = 1526,\n\tSCIF0_TXD_MARK = 1527,\n\tI2C2_SDA_B_MARK = 1528,\n\tCAN1_TX_MARK = 1529,\n\tD0_MARK = 1530,\n\tSCIFA3_SCK_B_MARK = 1531,\n\tIRQ4_MARK = 1532,\n\tD1_MARK = 1533,\n\tSCIFA3_RXD_B_MARK = 1534,\n\tD2_MARK = 1535,\n\tSCIFA3_TXD_B_MARK = 1536,\n\tD3_MARK = 1537,\n\tI2C3_SCL_B_MARK = 1538,\n\tSCIF5_RXD_B_MARK = 1539,\n\tD4_MARK = 1540,\n\tI2C3_SDA_B_MARK = 1541,\n\tSCIF5_TXD_B_MARK = 1542,\n\tD5_MARK = 1543,\n\tSCIF4_RXD_B_MARK = 1544,\n\tI2C0_SCL_D_MARK = 1545,\n\tD6_MARK = 1546,\n\tSCIF4_TXD_B_MARK = 1547,\n\tI2C0_SDA_D_MARK = 1548,\n\tD7_MARK = 1549,\n\tIRQ3_MARK = 1550,\n\tTCLK1_MARK = 1551,\n\tPWM6_B_MARK = 1552,\n\tD8_MARK = 1553,\n\tHSCIF2_HRX_MARK = 1554,\n\tI2C1_SCL_B_MARK = 1555,\n\tD9_MARK = 1556,\n\tHSCIF2_HTX_MARK = 1557,\n\tI2C1_SDA_B_MARK = 1558,\n\tD10_MARK = 1559,\n\tHSCIF2_HSCK_MARK = 1560,\n\tSCIF1_SCK_C_MARK = 1561,\n\tIRQ6_MARK = 1562,\n\tPWM5_C_MARK = 1563,\n\tD11_MARK = 1564,\n\tHSCIF2_HCTS_N_MARK = 1565,\n\tSCIF1_RXD_C_MARK = 1566,\n\tI2C1_SCL_D_MARK = 1567,\n\tD12_MARK = 1568,\n\tHSCIF2_HRTS_N_MARK = 1569,\n\tSCIF1_TXD_C_MARK = 1570,\n\tI2C1_SDA_D_MARK = 1571,\n\tD13_MARK = 1572,\n\tSCIFA1_SCK_MARK = 1573,\n\tPWM2_C_MARK = 1574,\n\tTCLK2_B_MARK = 1575,\n\tD14_MARK = 1576,\n\tSCIFA1_RXD_MARK = 1577,\n\tI2C5_SCL_B_MARK = 1578,\n\tD15_MARK = 1579,\n\tSCIFA1_TXD_MARK = 1580,\n\tI2C5_SDA_B_MARK = 1581,\n\tA0_MARK = 1582,\n\tSCIFB1_SCK_MARK = 1583,\n\tPWM3_B_MARK = 1584,\n\tA1_MARK = 1585,\n\tSCIFB1_TXD_MARK = 1586,\n\tA3_MARK = 1587,\n\tSCIFB0_SCK_MARK = 1588,\n\tA4_MARK = 1589,\n\tSCIFB0_TXD_MARK = 1590,\n\tA5_MARK = 1591,\n\tSCIFB0_RXD_MARK = 1592,\n\tPWM4_B_MARK = 1593,\n\tTPUTO3_C_MARK = 1594,\n\tA6_MARK = 1595,\n\tSCIFB0_CTS_N_MARK = 1596,\n\tSCIFA4_RXD_B_MARK = 1597,\n\tTPUTO2_C_MARK = 1598,\n\tA7_MARK = 1599,\n\tSCIFB0_RTS_N_MARK = 1600,\n\tSCIFA4_TXD_B_MARK = 1601,\n\tA8_MARK = 1602,\n\tMSIOF1_RXD_MARK = 1603,\n\tSCIFA0_RXD_B_MARK = 1604,\n\tA9_MARK = 1605,\n\tMSIOF1_TXD_MARK = 1606,\n\tSCIFA0_TXD_B_MARK = 1607,\n\tA10_MARK = 1608,\n\tMSIOF1_SCK_MARK = 1609,\n\tIIC0_SCL_B_MARK = 1610,\n\tA11_MARK = 1611,\n\tMSIOF1_SYNC_MARK = 1612,\n\tIIC0_SDA_B_MARK = 1613,\n\tA12_MARK = 1614,\n\tMSIOF1_SS1_MARK = 1615,\n\tSCIFA5_RXD_B_MARK = 1616,\n\tA13_MARK = 1617,\n\tMSIOF1_SS2_MARK = 1618,\n\tSCIFA5_TXD_B_MARK = 1619,\n\tA14_MARK = 1620,\n\tMSIOF2_RXD_MARK = 1621,\n\tHSCIF0_HRX_B_MARK = 1622,\n\tDREQ1_N_MARK = 1623,\n\tA15_MARK = 1624,\n\tMSIOF2_TXD_MARK = 1625,\n\tHSCIF0_HTX_B_MARK = 1626,\n\tDACK1_MARK = 1627,\n\tA16_MARK = 1628,\n\tMSIOF2_SCK_MARK = 1629,\n\tHSCIF0_HSCK_B_MARK = 1630,\n\tSPEEDIN_MARK = 1631,\n\tCAN_CLK_C_MARK = 1632,\n\tTPUTO2_B_MARK = 1633,\n\tA17_MARK = 1634,\n\tMSIOF2_SYNC_MARK = 1635,\n\tSCIF4_RXD_E_MARK = 1636,\n\tCAN1_RX_B_MARK = 1637,\n\tA18_MARK = 1638,\n\tMSIOF2_SS1_MARK = 1639,\n\tSCIF4_TXD_E_MARK = 1640,\n\tCAN1_TX_B_MARK = 1641,\n\tA19_MARK = 1642,\n\tMSIOF2_SS2_MARK = 1643,\n\tPWM4_MARK = 1644,\n\tTPUTO2_MARK = 1645,\n\tA20_MARK = 1646,\n\tSPCLK_MARK = 1647,\n\tA21_MARK = 1648,\n\tMOSI_IO0_MARK = 1649,\n\tA22_MARK = 1650,\n\tMISO_IO1_MARK = 1651,\n\tATADIR1_N_MARK = 1652,\n\tA23_MARK = 1653,\n\tIO2_MARK = 1654,\n\tATAWR1_N_MARK = 1655,\n\tA24_MARK = 1656,\n\tIO3_MARK = 1657,\n\tEX_WAIT2_MARK = 1658,\n\tA25_MARK = 1659,\n\tSSL_MARK = 1660,\n\tATARD1_N_MARK = 1661,\n\tCS0_N_MARK = 1662,\n\tVI1_DATA8_MARK = 1663,\n\tCS1_N_A26_MARK = 1664,\n\tVI1_DATA9_MARK = 1665,\n\tEX_CS0_N_MARK = 1666,\n\tVI1_DATA10_MARK = 1667,\n\tEX_CS1_N_MARK = 1668,\n\tTPUTO3_B_MARK = 1669,\n\tSCIFB2_RXD_MARK = 1670,\n\tVI1_DATA11_MARK = 1671,\n\tEX_CS2_N_MARK = 1672,\n\tPWM0_MARK = 1673,\n\tSCIF4_RXD_C_MARK = 1674,\n\tTS_SDATA_B_MARK = 1675,\n\tTPUTO3_MARK = 1676,\n\tSCIFB2_TXD_MARK = 1677,\n\tEX_CS3_N_MARK = 1678,\n\tSCIFA2_SCK_MARK = 1679,\n\tSCIF4_TXD_C_MARK = 1680,\n\tTS_SCK_B_MARK = 1681,\n\tBPFCLK_MARK = 1682,\n\tSCIFB2_SCK_MARK = 1683,\n\tEX_CS4_N_MARK = 1684,\n\tSCIFA2_RXD_MARK = 1685,\n\tI2C2_SCL_E_MARK = 1686,\n\tTS_SDEN_B_MARK = 1687,\n\tFMCLK_MARK = 1688,\n\tSCIFB2_CTS_N_MARK = 1689,\n\tEX_CS5_N_MARK = 1690,\n\tSCIFA2_TXD_MARK = 1691,\n\tI2C2_SDA_E_MARK = 1692,\n\tTS_SPSYNC_B_MARK = 1693,\n\tFMIN_MARK = 1694,\n\tSCIFB2_RTS_N_MARK = 1695,\n\tBS_N_MARK = 1696,\n\tDRACK0_MARK = 1697,\n\tPWM1_C_MARK = 1698,\n\tTPUTO0_C_MARK = 1699,\n\tATACS01_N_MARK = 1700,\n\tRD_N_MARK = 1701,\n\tATACS11_N_MARK = 1702,\n\tRD_WR_N_MARK = 1703,\n\tATAG1_N_MARK = 1704,\n\tEX_WAIT0_MARK = 1705,\n\tCAN_CLK_B_MARK = 1706,\n\tSCIF_CLK_MARK = 1707,\n\tDU0_DR0_MARK = 1708,\n\tLCDOUT16_MARK = 1709,\n\tSCIF5_RXD_C_MARK = 1710,\n\tI2C2_SCL_D_MARK = 1711,\n\tDU0_DR1_MARK = 1712,\n\tLCDOUT17_MARK = 1713,\n\tSCIF5_TXD_C_MARK = 1714,\n\tI2C2_SDA_D_MARK = 1715,\n\tDU0_DR2_MARK = 1716,\n\tLCDOUT18_MARK = 1717,\n\tDU0_DR3_MARK = 1718,\n\tLCDOUT19_MARK = 1719,\n\tDU0_DR4_MARK = 1720,\n\tLCDOUT20_MARK = 1721,\n\tDU0_DR5_MARK = 1722,\n\tLCDOUT21_MARK = 1723,\n\tDU0_DR6_MARK = 1724,\n\tLCDOUT22_MARK = 1725,\n\tDU0_DR7_MARK = 1726,\n\tLCDOUT23_MARK = 1727,\n\tDU0_DG0_MARK = 1728,\n\tLCDOUT8_MARK = 1729,\n\tSCIFA0_RXD_C_MARK = 1730,\n\tI2C3_SCL_D_MARK = 1731,\n\tDU0_DG1_MARK = 1732,\n\tLCDOUT9_MARK = 1733,\n\tSCIFA0_TXD_C_MARK = 1734,\n\tI2C3_SDA_D_MARK = 1735,\n\tDU0_DG2_MARK = 1736,\n\tLCDOUT10_MARK = 1737,\n\tDU0_DG3_MARK = 1738,\n\tLCDOUT11_MARK = 1739,\n\tDU0_DG4_MARK = 1740,\n\tLCDOUT12_MARK = 1741,\n\tDU0_DG5_MARK = 1742,\n\tLCDOUT13_MARK = 1743,\n\tDU0_DG6_MARK = 1744,\n\tLCDOUT14_MARK = 1745,\n\tDU0_DG7_MARK = 1746,\n\tLCDOUT15_MARK = 1747,\n\tDU0_DB0_MARK = 1748,\n\tLCDOUT0_MARK = 1749,\n\tSCIFA4_RXD_C_MARK = 1750,\n\tI2C4_SCL_D_MARK = 1751,\n\tCAN0_RX_C_MARK = 1752,\n\tDU0_DB1_MARK = 1753,\n\tLCDOUT1_MARK = 1754,\n\tSCIFA4_TXD_C_MARK = 1755,\n\tI2C4_SDA_D_MARK = 1756,\n\tCAN0_TX_C_MARK = 1757,\n\tDU0_DB2_MARK = 1758,\n\tLCDOUT2_MARK = 1759,\n\tDU0_DB3_MARK = 1760,\n\tLCDOUT3_MARK = 1761,\n\tDU0_DB4_MARK = 1762,\n\tLCDOUT4_MARK = 1763,\n\tDU0_DB5_MARK = 1764,\n\tLCDOUT5_MARK = 1765,\n\tDU0_DB6_MARK = 1766,\n\tLCDOUT6_MARK = 1767,\n\tDU0_DB7_MARK = 1768,\n\tLCDOUT7_MARK = 1769,\n\tDU0_DOTCLKIN_MARK = 1770,\n\tQSTVA_QVS_MARK = 1771,\n\tDU0_DOTCLKOUT0_MARK = 1772,\n\tQCLK_MARK = 1773,\n\tDU0_DOTCLKOUT1_MARK = 1774,\n\tQSTVB_QVE_MARK = 1775,\n\tDU0_EXHSYNC_DU0_HSYNC_MARK = 1776,\n\tQSTH_QHS_MARK = 1777,\n\tDU0_EXVSYNC_DU0_VSYNC_MARK = 1778,\n\tQSTB_QHE_MARK = 1779,\n\tDU0_EXODDF_DU0_ODDF_DISP_CDE_MARK = 1780,\n\tQCPV_QDE_MARK = 1781,\n\tDU0_DISP_MARK = 1782,\n\tQPOLA_MARK = 1783,\n\tDU0_CDE_MARK = 1784,\n\tQPOLB_MARK = 1785,\n\tVI0_CLK_MARK = 1786,\n\tAVB_RX_CLK_MARK = 1787,\n\tVI0_DATA0_VI0_B0_MARK = 1788,\n\tAVB_RX_DV_MARK = 1789,\n\tVI0_DATA1_VI0_B1_MARK = 1790,\n\tAVB_RXD0_MARK = 1791,\n\tVI0_DATA2_VI0_B2_MARK = 1792,\n\tAVB_RXD1_MARK = 1793,\n\tVI0_DATA3_VI0_B3_MARK = 1794,\n\tAVB_RXD2_MARK = 1795,\n\tVI0_DATA4_VI0_B4_MARK = 1796,\n\tAVB_RXD3_MARK = 1797,\n\tVI0_DATA5_VI0_B5_MARK = 1798,\n\tAVB_RXD4_MARK = 1799,\n\tVI0_DATA6_VI0_B6_MARK = 1800,\n\tAVB_RXD5_MARK = 1801,\n\tVI0_DATA7_VI0_B7_MARK = 1802,\n\tAVB_RXD6_MARK = 1803,\n\tVI0_CLKENB_MARK = 1804,\n\tI2C3_SCL_MARK = 1805,\n\tSCIFA5_RXD_C_MARK = 1806,\n\tIETX_C_MARK = 1807,\n\tAVB_RXD7_MARK = 1808,\n\tVI0_FIELD_MARK = 1809,\n\tI2C3_SDA_MARK = 1810,\n\tSCIFA5_TXD_C_MARK = 1811,\n\tIECLK_C_MARK = 1812,\n\tAVB_RX_ER_MARK = 1813,\n\tVI0_HSYNC_N_MARK = 1814,\n\tSCIF0_RXD_B_MARK = 1815,\n\tI2C0_SCL_C_MARK = 1816,\n\tIERX_C_MARK = 1817,\n\tAVB_COL_MARK = 1818,\n\tVI0_VSYNC_N_MARK = 1819,\n\tSCIF0_TXD_B_MARK = 1820,\n\tI2C0_SDA_C_MARK = 1821,\n\tAUDIO_CLKOUT_B_MARK = 1822,\n\tAVB_TX_EN_MARK = 1823,\n\tETH_MDIO_MARK = 1824,\n\tVI0_G0_MARK = 1825,\n\tMSIOF2_RXD_B_MARK = 1826,\n\tI2C5_SCL_D_MARK = 1827,\n\tAVB_TX_CLK_MARK = 1828,\n\tADIDATA_MARK = 1829,\n\tETH_CRS_DV_MARK = 1830,\n\tVI0_G1_MARK = 1831,\n\tMSIOF2_TXD_B_MARK = 1832,\n\tI2C5_SDA_D_MARK = 1833,\n\tAVB_TXD0_MARK = 1834,\n\tADICS_SAMP_MARK = 1835,\n\tETH_RX_ER_MARK = 1836,\n\tVI0_G2_MARK = 1837,\n\tMSIOF2_SCK_B_MARK = 1838,\n\tCAN0_RX_B_MARK = 1839,\n\tAVB_TXD1_MARK = 1840,\n\tADICLK_MARK = 1841,\n\tETH_RXD0_MARK = 1842,\n\tVI0_G3_MARK = 1843,\n\tMSIOF2_SYNC_B_MARK = 1844,\n\tCAN0_TX_B_MARK = 1845,\n\tAVB_TXD2_MARK = 1846,\n\tADICHS0_MARK = 1847,\n\tETH_RXD1_MARK = 1848,\n\tVI0_G4_MARK = 1849,\n\tMSIOF2_SS1_B_MARK = 1850,\n\tSCIF4_RXD_D_MARK = 1851,\n\tAVB_TXD3_MARK = 1852,\n\tADICHS1_MARK = 1853,\n\tETH_LINK_MARK = 1854,\n\tVI0_G5_MARK = 1855,\n\tMSIOF2_SS2_B_MARK = 1856,\n\tSCIF4_TXD_D_MARK = 1857,\n\tAVB_TXD4_MARK = 1858,\n\tADICHS2_MARK = 1859,\n\tETH_REFCLK_MARK = 1860,\n\tVI0_G6_MARK = 1861,\n\tSCIF2_SCK_C_MARK = 1862,\n\tAVB_TXD5_MARK = 1863,\n\tSSI_SCK5_B_MARK = 1864,\n\tETH_TXD1_MARK = 1865,\n\tVI0_G7_MARK = 1866,\n\tSCIF2_RXD_C_MARK = 1867,\n\tIIC0_SCL_D_MARK = 1868,\n\tAVB_TXD6_MARK = 1869,\n\tSSI_WS5_B_MARK = 1870,\n\tETH_TX_EN_MARK = 1871,\n\tVI0_R0_MARK = 1872,\n\tSCIF2_TXD_C_MARK = 1873,\n\tIIC0_SDA_D_MARK = 1874,\n\tAVB_TXD7_MARK = 1875,\n\tSSI_SDATA5_B_MARK = 1876,\n\tETH_MAGIC_MARK = 1877,\n\tVI0_R1_MARK = 1878,\n\tSCIF3_SCK_B_MARK = 1879,\n\tAVB_TX_ER_MARK = 1880,\n\tSSI_SCK6_B_MARK = 1881,\n\tETH_TXD0_MARK = 1882,\n\tVI0_R2_MARK = 1883,\n\tSCIF3_RXD_B_MARK = 1884,\n\tI2C4_SCL_E_MARK = 1885,\n\tAVB_GTX_CLK_MARK = 1886,\n\tSSI_WS6_B_MARK = 1887,\n\tDREQ0_N_MARK = 1888,\n\tSCIFB1_RXD_MARK = 1889,\n\tETH_MDC_MARK = 1890,\n\tVI0_R3_MARK = 1891,\n\tSCIF3_TXD_B_MARK = 1892,\n\tI2C4_SDA_E_MARK = 1893,\n\tAVB_MDC_MARK = 1894,\n\tSSI_SDATA6_B_MARK = 1895,\n\tHSCIF0_HRX_MARK = 1896,\n\tVI0_R4_MARK = 1897,\n\tI2C1_SCL_C_MARK = 1898,\n\tAUDIO_CLKA_B_MARK = 1899,\n\tAVB_MDIO_MARK = 1900,\n\tSSI_SCK78_B_MARK = 1901,\n\tHSCIF0_HTX_MARK = 1902,\n\tVI0_R5_MARK = 1903,\n\tI2C1_SDA_C_MARK = 1904,\n\tAUDIO_CLKB_B_MARK = 1905,\n\tAVB_LINK_MARK = 1906,\n\tSSI_WS78_B_MARK = 1907,\n\tHSCIF0_HCTS_N_MARK = 1908,\n\tVI0_R6_MARK = 1909,\n\tSCIF0_RXD_D_MARK = 1910,\n\tI2C0_SCL_E_MARK = 1911,\n\tAVB_MAGIC_MARK = 1912,\n\tSSI_SDATA7_B_MARK = 1913,\n\tHSCIF0_HRTS_N_MARK = 1914,\n\tVI0_R7_MARK = 1915,\n\tSCIF0_TXD_D_MARK = 1916,\n\tI2C0_SDA_E_MARK = 1917,\n\tAVB_PHY_INT_MARK = 1918,\n\tSSI_SDATA8_B_MARK = 1919,\n\tHSCIF0_HSCK_MARK = 1920,\n\tSCIF_CLK_B_MARK = 1921,\n\tAVB_CRS_MARK = 1922,\n\tAUDIO_CLKC_B_MARK = 1923,\n\tI2C0_SCL_MARK = 1924,\n\tSCIF0_RXD_C_MARK = 1925,\n\tPWM5_MARK = 1926,\n\tTCLK1_B_MARK = 1927,\n\tAVB_GTXREFCLK_MARK = 1928,\n\tCAN1_RX_D_MARK = 1929,\n\tTPUTO0_B_MARK = 1930,\n\tI2C0_SDA_MARK = 1931,\n\tSCIF0_TXD_C_MARK = 1932,\n\tTPUTO0_MARK = 1933,\n\tCAN_CLK_MARK = 1934,\n\tDVC_MUTE_MARK = 1935,\n\tCAN1_TX_D_MARK = 1936,\n\tI2C1_SCL_MARK = 1937,\n\tSCIF4_RXD_MARK = 1938,\n\tPWM5_B_MARK = 1939,\n\tDU1_DR0_MARK = 1940,\n\tTS_SDATA_D_MARK = 1941,\n\tTPUTO1_B_MARK = 1942,\n\tI2C1_SDA_MARK = 1943,\n\tSCIF4_TXD_MARK = 1944,\n\tIRQ5_MARK = 1945,\n\tDU1_DR1_MARK = 1946,\n\tTS_SCK_D_MARK = 1947,\n\tBPFCLK_C_MARK = 1948,\n\tMSIOF0_RXD_MARK = 1949,\n\tSCIF5_RXD_MARK = 1950,\n\tI2C2_SCL_C_MARK = 1951,\n\tDU1_DR2_MARK = 1952,\n\tTS_SDEN_D_MARK = 1953,\n\tFMCLK_C_MARK = 1954,\n\tMSIOF0_TXD_MARK = 1955,\n\tSCIF5_TXD_MARK = 1956,\n\tI2C2_SDA_C_MARK = 1957,\n\tDU1_DR3_MARK = 1958,\n\tTS_SPSYNC_D_MARK = 1959,\n\tFMIN_C_MARK = 1960,\n\tMSIOF0_SCK_MARK = 1961,\n\tIRQ0_MARK = 1962,\n\tTS_SDATA_MARK = 1963,\n\tDU1_DR4_MARK = 1964,\n\tTPUTO1_C_MARK = 1965,\n\tMSIOF0_SYNC_MARK = 1966,\n\tPWM1_MARK = 1967,\n\tTS_SCK_MARK = 1968,\n\tDU1_DR5_MARK = 1969,\n\tBPFCLK_B_MARK = 1970,\n\tMSIOF0_SS1_MARK = 1971,\n\tSCIFA0_RXD_MARK = 1972,\n\tTS_SDEN_MARK = 1973,\n\tDU1_DR6_MARK = 1974,\n\tFMCLK_B_MARK = 1975,\n\tMSIOF0_SS2_MARK = 1976,\n\tSCIFA0_TXD_MARK = 1977,\n\tTS_SPSYNC_MARK = 1978,\n\tDU1_DR7_MARK = 1979,\n\tFMIN_B_MARK = 1980,\n\tHSCIF1_HRX_MARK = 1981,\n\tI2C4_SCL_MARK = 1982,\n\tPWM6_MARK = 1983,\n\tDU1_DG0_MARK = 1984,\n\tHSCIF1_HTX_MARK = 1985,\n\tI2C4_SDA_MARK = 1986,\n\tTPUTO1_MARK = 1987,\n\tDU1_DG1_MARK = 1988,\n\tHSCIF1_HSCK_MARK = 1989,\n\tPWM2_MARK = 1990,\n\tIETX_MARK = 1991,\n\tDU1_DG2_MARK = 1992,\n\tREMOCON_B_MARK = 1993,\n\tSPEEDIN_B_MARK = 1994,\n\tHSCIF1_HCTS_N_MARK = 1995,\n\tSCIFA4_RXD_MARK = 1996,\n\tIECLK_MARK = 1997,\n\tDU1_DG3_MARK = 1998,\n\tSSI_SCK1_B_MARK = 1999,\n\tHSCIF1_HRTS_N_MARK = 2000,\n\tSCIFA4_TXD_MARK = 2001,\n\tIERX_MARK = 2002,\n\tDU1_DG4_MARK = 2003,\n\tSSI_WS1_B_MARK = 2004,\n\tSCIF1_SCK_MARK = 2005,\n\tPWM3_MARK = 2006,\n\tTCLK2_MARK = 2007,\n\tDU1_DG5_MARK = 2008,\n\tSSI_SDATA1_B_MARK = 2009,\n\tCAN_TXCLK_MARK = 2010,\n\tSCIF1_RXD_MARK = 2011,\n\tI2C5_SCL_MARK = 2012,\n\tDU1_DG6_MARK = 2013,\n\tSSI_SCK2_B_MARK = 2014,\n\tSCIF1_TXD_MARK = 2015,\n\tI2C5_SDA_MARK = 2016,\n\tDU1_DG7_MARK = 2017,\n\tSSI_WS2_B_MARK = 2018,\n\tSCIF2_RXD_MARK = 2019,\n\tIIC0_SCL_MARK = 2020,\n\tDU1_DB0_MARK = 2021,\n\tSSI_SDATA2_B_MARK = 2022,\n\tSCIF2_TXD_MARK = 2023,\n\tIIC0_SDA_MARK = 2024,\n\tDU1_DB1_MARK = 2025,\n\tSSI_SCK9_B_MARK = 2026,\n\tSCIF2_SCK_MARK = 2027,\n\tIRQ1_MARK = 2028,\n\tDU1_DB2_MARK = 2029,\n\tSSI_WS9_B_MARK = 2030,\n\tSCIF3_SCK_MARK = 2031,\n\tIRQ2_MARK = 2032,\n\tBPFCLK_D_MARK = 2033,\n\tDU1_DB3_MARK = 2034,\n\tSSI_SDATA9_B_MARK = 2035,\n\tSCIF3_RXD_MARK = 2036,\n\tI2C1_SCL_E_MARK = 2037,\n\tFMCLK_D_MARK = 2038,\n\tDU1_DB4_MARK = 2039,\n\tAUDIO_CLKA_C_MARK = 2040,\n\tSSI_SCK4_B_MARK = 2041,\n\tSCIF3_TXD_MARK = 2042,\n\tI2C1_SDA_E_MARK = 2043,\n\tFMIN_D_MARK = 2044,\n\tDU1_DB5_MARK = 2045,\n\tAUDIO_CLKB_C_MARK = 2046,\n\tSSI_WS4_B_MARK = 2047,\n\tI2C2_SCL_MARK = 2048,\n\tSCIFA5_RXD_MARK = 2049,\n\tDU1_DB6_MARK = 2050,\n\tAUDIO_CLKC_C_MARK = 2051,\n\tSSI_SDATA4_B_MARK = 2052,\n\tI2C2_SDA_MARK = 2053,\n\tSCIFA5_TXD_MARK = 2054,\n\tDU1_DB7_MARK = 2055,\n\tAUDIO_CLKOUT_C_MARK = 2056,\n\tSSI_SCK5_MARK = 2057,\n\tSCIFA3_SCK_MARK = 2058,\n\tDU1_DOTCLKIN_MARK = 2059,\n\tSSI_WS5_MARK = 2060,\n\tSCIFA3_RXD_MARK = 2061,\n\tI2C3_SCL_C_MARK = 2062,\n\tDU1_DOTCLKOUT0_MARK = 2063,\n\tSSI_SDATA5_MARK = 2064,\n\tSCIFA3_TXD_MARK = 2065,\n\tI2C3_SDA_C_MARK = 2066,\n\tDU1_DOTCLKOUT1_MARK = 2067,\n\tSSI_SCK6_MARK = 2068,\n\tSCIFA1_SCK_B_MARK = 2069,\n\tDU1_EXHSYNC_DU1_HSYNC_MARK = 2070,\n\tSSI_WS6_MARK = 2071,\n\tSCIFA1_RXD_B_MARK = 2072,\n\tI2C4_SCL_C_MARK = 2073,\n\tDU1_EXVSYNC_DU1_VSYNC_MARK = 2074,\n\tSSI_SDATA6_MARK = 2075,\n\tSCIFA1_TXD_B_MARK = 2076,\n\tI2C4_SDA_C_MARK = 2077,\n\tDU1_EXODDF_DU1_ODDF_DISP_CDE_MARK = 2078,\n\tSSI_SCK78_MARK = 2079,\n\tSCIFA2_SCK_B_MARK = 2080,\n\tI2C5_SDA_C_MARK = 2081,\n\tDU1_DISP_MARK = 2082,\n\tSSI_WS78_MARK = 2083,\n\tSCIFA2_RXD_B_MARK = 2084,\n\tI2C5_SCL_C_MARK = 2085,\n\tDU1_CDE_MARK = 2086,\n\tSSI_SDATA7_MARK = 2087,\n\tSCIFA2_TXD_B_MARK = 2088,\n\tIRQ8_MARK = 2089,\n\tAUDIO_CLKA_D_MARK = 2090,\n\tCAN_CLK_D_MARK = 2091,\n\tSSI_SCK0129_MARK = 2092,\n\tMSIOF1_RXD_B_MARK = 2093,\n\tSCIF5_RXD_D_MARK = 2094,\n\tADIDATA_B_MARK = 2095,\n\tSSI_WS0129_MARK = 2096,\n\tMSIOF1_TXD_B_MARK = 2097,\n\tSCIF5_TXD_D_MARK = 2098,\n\tADICS_SAMP_B_MARK = 2099,\n\tSSI_SDATA0_MARK = 2100,\n\tMSIOF1_SCK_B_MARK = 2101,\n\tPWM0_B_MARK = 2102,\n\tADICLK_B_MARK = 2103,\n\tSSI_SCK34_MARK = 2104,\n\tMSIOF1_SYNC_B_MARK = 2105,\n\tSCIFA1_SCK_C_MARK = 2106,\n\tADICHS0_B_MARK = 2107,\n\tDREQ1_N_B_MARK = 2108,\n\tSSI_WS34_MARK = 2109,\n\tMSIOF1_SS1_B_MARK = 2110,\n\tSCIFA1_RXD_C_MARK = 2111,\n\tADICHS1_B_MARK = 2112,\n\tCAN1_RX_C_MARK = 2113,\n\tDACK1_B_MARK = 2114,\n\tSSI_SDATA3_MARK = 2115,\n\tMSIOF1_SS2_B_MARK = 2116,\n\tSCIFA1_TXD_C_MARK = 2117,\n\tADICHS2_B_MARK = 2118,\n\tCAN1_TX_C_MARK = 2119,\n\tDREQ2_N_MARK = 2120,\n\tSSI_SCK4_MARK = 2121,\n\tMLB_CLK_MARK = 2122,\n\tIETX_B_MARK = 2123,\n\tSSI_WS4_MARK = 2124,\n\tMLB_SIG_MARK = 2125,\n\tIECLK_B_MARK = 2126,\n\tSSI_SDATA4_MARK = 2127,\n\tMLB_DAT_MARK = 2128,\n\tIERX_B_MARK = 2129,\n\tSSI_SDATA8_MARK = 2130,\n\tSCIF1_SCK_B_MARK = 2131,\n\tPWM1_B_MARK = 2132,\n\tIRQ9_MARK = 2133,\n\tREMOCON_MARK = 2134,\n\tDACK2_MARK = 2135,\n\tETH_MDIO_B_MARK = 2136,\n\tSSI_SCK1_MARK = 2137,\n\tSCIF1_RXD_B_MARK = 2138,\n\tIIC0_SCL_C_MARK = 2139,\n\tVI1_CLK_MARK = 2140,\n\tCAN0_RX_D_MARK = 2141,\n\tETH_CRS_DV_B_MARK = 2142,\n\tSSI_WS1_MARK = 2143,\n\tSCIF1_TXD_B_MARK = 2144,\n\tIIC0_SDA_C_MARK = 2145,\n\tVI1_DATA0_MARK = 2146,\n\tCAN0_TX_D_MARK = 2147,\n\tETH_RX_ER_B_MARK = 2148,\n\tSSI_SDATA1_MARK = 2149,\n\tHSCIF1_HRX_B_MARK = 2150,\n\tVI1_DATA1_MARK = 2151,\n\tATAWR0_N_MARK = 2152,\n\tETH_RXD0_B_MARK = 2153,\n\tSSI_SCK2_MARK = 2154,\n\tHSCIF1_HTX_B_MARK = 2155,\n\tVI1_DATA2_MARK = 2156,\n\tATAG0_N_MARK = 2157,\n\tETH_RXD1_B_MARK = 2158,\n\tSSI_WS2_MARK = 2159,\n\tHSCIF1_HCTS_N_B_MARK = 2160,\n\tSCIFA0_RXD_D_MARK = 2161,\n\tVI1_DATA3_MARK = 2162,\n\tATACS00_N_MARK = 2163,\n\tETH_LINK_B_MARK = 2164,\n\tSSI_SDATA2_MARK = 2165,\n\tHSCIF1_HRTS_N_B_MARK = 2166,\n\tSCIFA0_TXD_D_MARK = 2167,\n\tVI1_DATA4_MARK = 2168,\n\tATACS10_N_MARK = 2169,\n\tETH_REFCLK_B_MARK = 2170,\n\tSSI_SCK9_MARK = 2171,\n\tSCIF2_SCK_B_MARK = 2172,\n\tPWM2_B_MARK = 2173,\n\tVI1_DATA5_MARK = 2174,\n\tEX_WAIT1_MARK = 2175,\n\tETH_TXD1_B_MARK = 2176,\n\tSSI_WS9_MARK = 2177,\n\tSCIF2_RXD_B_MARK = 2178,\n\tI2C3_SCL_E_MARK = 2179,\n\tVI1_DATA6_MARK = 2180,\n\tATARD0_N_MARK = 2181,\n\tETH_TX_EN_B_MARK = 2182,\n\tSSI_SDATA9_MARK = 2183,\n\tSCIF2_TXD_B_MARK = 2184,\n\tI2C3_SDA_E_MARK = 2185,\n\tVI1_DATA7_MARK = 2186,\n\tATADIR0_N_MARK = 2187,\n\tETH_MAGIC_B_MARK = 2188,\n\tAUDIO_CLKA_MARK = 2189,\n\tI2C0_SCL_B_MARK = 2190,\n\tSCIFA4_RXD_D_MARK = 2191,\n\tVI1_CLKENB_MARK = 2192,\n\tTS_SDATA_C_MARK = 2193,\n\tETH_TXD0_B_MARK = 2194,\n\tAUDIO_CLKB_MARK = 2195,\n\tI2C0_SDA_B_MARK = 2196,\n\tSCIFA4_TXD_D_MARK = 2197,\n\tVI1_FIELD_MARK = 2198,\n\tTS_SCK_C_MARK = 2199,\n\tBPFCLK_E_MARK = 2200,\n\tETH_MDC_B_MARK = 2201,\n\tAUDIO_CLKC_MARK = 2202,\n\tI2C4_SCL_B_MARK = 2203,\n\tSCIFA5_RXD_D_MARK = 2204,\n\tVI1_HSYNC_N_MARK = 2205,\n\tTS_SDEN_C_MARK = 2206,\n\tFMCLK_E_MARK = 2207,\n\tAUDIO_CLKOUT_MARK = 2208,\n\tI2C4_SDA_B_MARK = 2209,\n\tSCIFA5_TXD_D_MARK = 2210,\n\tVI1_VSYNC_N_MARK = 2211,\n\tTS_SPSYNC_C_MARK = 2212,\n\tFMIN_E_MARK = 2213,\n\tPINMUX_MARK_END = 2214,\n};\n\nenum {\n\tPINMUX_RESERVED___2 = 0,\n\tPINMUX_DATA_BEGIN___2 = 1,\n\tPORT0_DATA = 2,\n\tPORT1_DATA = 3,\n\tPORT2_DATA = 4,\n\tPORT3_DATA = 5,\n\tPORT4_DATA = 6,\n\tPORT5_DATA = 7,\n\tPORT6_DATA = 8,\n\tPORT7_DATA = 9,\n\tPORT8_DATA = 10,\n\tPORT9_DATA = 11,\n\tPORT10_DATA = 12,\n\tPORT11_DATA = 13,\n\tPORT12_DATA = 14,\n\tPORT13_DATA = 15,\n\tPORT14_DATA = 16,\n\tPORT15_DATA = 17,\n\tPORT16_DATA = 18,\n\tPORT17_DATA = 19,\n\tPORT18_DATA = 20,\n\tPORT19_DATA = 21,\n\tPORT20_DATA = 22,\n\tPORT21_DATA = 23,\n\tPORT22_DATA = 24,\n\tPORT23_DATA = 25,\n\tPORT24_DATA = 26,\n\tPORT25_DATA = 27,\n\tPORT26_DATA = 28,\n\tPORT27_DATA = 29,\n\tPORT28_DATA = 30,\n\tPORT29_DATA = 31,\n\tPORT30_DATA = 32,\n\tPORT31_DATA = 33,\n\tPORT32_DATA = 34,\n\tPORT33_DATA = 35,\n\tPORT34_DATA = 36,\n\tPORT35_DATA = 37,\n\tPORT36_DATA = 38,\n\tPORT37_DATA = 39,\n\tPORT38_DATA = 40,\n\tPORT39_DATA = 41,\n\tPORT40_DATA = 42,\n\tPORT41_DATA = 43,\n\tPORT42_DATA = 44,\n\tPORT43_DATA = 45,\n\tPORT44_DATA = 46,\n\tPORT45_DATA = 47,\n\tPORT46_DATA = 48,\n\tPORT47_DATA = 49,\n\tPORT48_DATA = 50,\n\tPORT49_DATA = 51,\n\tPORT50_DATA = 52,\n\tPORT51_DATA = 53,\n\tPORT52_DATA = 54,\n\tPORT53_DATA = 55,\n\tPORT54_DATA = 56,\n\tPORT55_DATA = 57,\n\tPORT56_DATA = 58,\n\tPORT57_DATA = 59,\n\tPORT58_DATA = 60,\n\tPORT59_DATA = 61,\n\tPORT60_DATA = 62,\n\tPORT61_DATA = 63,\n\tPORT62_DATA = 64,\n\tPORT63_DATA = 65,\n\tPORT64_DATA = 66,\n\tPORT65_DATA = 67,\n\tPORT66_DATA = 68,\n\tPORT67_DATA = 69,\n\tPORT68_DATA = 70,\n\tPORT69_DATA = 71,\n\tPORT70_DATA = 72,\n\tPORT71_DATA = 73,\n\tPORT72_DATA = 74,\n\tPORT73_DATA = 75,\n\tPORT74_DATA = 76,\n\tPORT75_DATA = 77,\n\tPORT76_DATA = 78,\n\tPORT77_DATA = 79,\n\tPORT78_DATA = 80,\n\tPORT79_DATA = 81,\n\tPORT80_DATA = 82,\n\tPORT81_DATA = 83,\n\tPORT82_DATA = 84,\n\tPORT83_DATA = 85,\n\tPORT84_DATA = 86,\n\tPORT85_DATA = 87,\n\tPORT86_DATA = 88,\n\tPORT87_DATA = 89,\n\tPORT88_DATA = 90,\n\tPORT89_DATA = 91,\n\tPORT90_DATA = 92,\n\tPORT91_DATA = 93,\n\tPORT92_DATA = 94,\n\tPORT93_DATA = 95,\n\tPORT94_DATA = 96,\n\tPORT95_DATA = 97,\n\tPORT96_DATA = 98,\n\tPORT97_DATA = 99,\n\tPORT98_DATA = 100,\n\tPORT99_DATA = 101,\n\tPORT100_DATA = 102,\n\tPORT101_DATA = 103,\n\tPORT102_DATA = 104,\n\tPORT103_DATA = 105,\n\tPORT104_DATA = 106,\n\tPORT105_DATA = 107,\n\tPORT106_DATA = 108,\n\tPORT107_DATA = 109,\n\tPORT108_DATA = 110,\n\tPORT109_DATA = 111,\n\tPORT110_DATA = 112,\n\tPORT111_DATA = 113,\n\tPORT112_DATA = 114,\n\tPORT113_DATA = 115,\n\tPORT114_DATA = 116,\n\tPORT115_DATA = 117,\n\tPORT116_DATA = 118,\n\tPORT117_DATA = 119,\n\tPORT118_DATA = 120,\n\tPORT128_DATA = 121,\n\tPORT129_DATA = 122,\n\tPORT130_DATA = 123,\n\tPORT131_DATA = 124,\n\tPORT132_DATA = 125,\n\tPORT133_DATA = 126,\n\tPORT134_DATA = 127,\n\tPORT135_DATA = 128,\n\tPORT136_DATA = 129,\n\tPORT137_DATA = 130,\n\tPORT138_DATA = 131,\n\tPORT139_DATA = 132,\n\tPORT140_DATA = 133,\n\tPORT141_DATA = 134,\n\tPORT142_DATA = 135,\n\tPORT143_DATA = 136,\n\tPORT144_DATA = 137,\n\tPORT145_DATA = 138,\n\tPORT146_DATA = 139,\n\tPORT147_DATA = 140,\n\tPORT148_DATA = 141,\n\tPORT149_DATA = 142,\n\tPORT150_DATA = 143,\n\tPORT151_DATA = 144,\n\tPORT152_DATA = 145,\n\tPORT153_DATA = 146,\n\tPORT154_DATA = 147,\n\tPORT155_DATA = 148,\n\tPORT156_DATA = 149,\n\tPORT157_DATA = 150,\n\tPORT158_DATA = 151,\n\tPORT159_DATA = 152,\n\tPORT160_DATA = 153,\n\tPORT161_DATA = 154,\n\tPORT162_DATA = 155,\n\tPORT163_DATA = 156,\n\tPORT164_DATA = 157,\n\tPORT192_DATA = 158,\n\tPORT193_DATA = 159,\n\tPORT194_DATA = 160,\n\tPORT195_DATA = 161,\n\tPORT196_DATA = 162,\n\tPORT197_DATA = 163,\n\tPORT198_DATA = 164,\n\tPORT199_DATA = 165,\n\tPORT200_DATA = 166,\n\tPORT201_DATA = 167,\n\tPORT202_DATA = 168,\n\tPORT203_DATA = 169,\n\tPORT204_DATA = 170,\n\tPORT205_DATA = 171,\n\tPORT206_DATA = 172,\n\tPORT207_DATA = 173,\n\tPORT208_DATA = 174,\n\tPORT209_DATA = 175,\n\tPORT210_DATA = 176,\n\tPORT211_DATA = 177,\n\tPORT212_DATA = 178,\n\tPORT213_DATA = 179,\n\tPORT214_DATA = 180,\n\tPORT215_DATA = 181,\n\tPORT216_DATA = 182,\n\tPORT217_DATA = 183,\n\tPORT218_DATA = 184,\n\tPORT219_DATA = 185,\n\tPORT220_DATA = 186,\n\tPORT221_DATA = 187,\n\tPORT222_DATA = 188,\n\tPORT223_DATA = 189,\n\tPORT224_DATA = 190,\n\tPORT225_DATA = 191,\n\tPORT226_DATA = 192,\n\tPORT227_DATA = 193,\n\tPORT228_DATA = 194,\n\tPORT229_DATA = 195,\n\tPORT230_DATA = 196,\n\tPORT231_DATA = 197,\n\tPORT232_DATA = 198,\n\tPORT233_DATA = 199,\n\tPORT234_DATA = 200,\n\tPORT235_DATA = 201,\n\tPORT236_DATA = 202,\n\tPORT237_DATA = 203,\n\tPORT238_DATA = 204,\n\tPORT239_DATA = 205,\n\tPORT240_DATA = 206,\n\tPORT241_DATA = 207,\n\tPORT242_DATA = 208,\n\tPORT243_DATA = 209,\n\tPORT244_DATA = 210,\n\tPORT245_DATA = 211,\n\tPORT246_DATA = 212,\n\tPORT247_DATA = 213,\n\tPORT248_DATA = 214,\n\tPORT249_DATA = 215,\n\tPORT250_DATA = 216,\n\tPORT251_DATA = 217,\n\tPORT252_DATA = 218,\n\tPORT253_DATA = 219,\n\tPORT254_DATA = 220,\n\tPORT255_DATA = 221,\n\tPORT256_DATA = 222,\n\tPORT257_DATA = 223,\n\tPORT258_DATA = 224,\n\tPORT259_DATA = 225,\n\tPORT260_DATA = 226,\n\tPORT261_DATA = 227,\n\tPORT262_DATA = 228,\n\tPORT263_DATA = 229,\n\tPORT264_DATA = 230,\n\tPORT265_DATA = 231,\n\tPORT266_DATA = 232,\n\tPORT267_DATA = 233,\n\tPORT268_DATA = 234,\n\tPORT269_DATA = 235,\n\tPORT270_DATA = 236,\n\tPORT271_DATA = 237,\n\tPORT272_DATA = 238,\n\tPORT273_DATA = 239,\n\tPORT274_DATA = 240,\n\tPORT275_DATA = 241,\n\tPORT276_DATA = 242,\n\tPORT277_DATA = 243,\n\tPORT278_DATA = 244,\n\tPORT279_DATA = 245,\n\tPORT280_DATA = 246,\n\tPORT281_DATA = 247,\n\tPORT282_DATA = 248,\n\tPORT288_DATA = 249,\n\tPORT289_DATA = 250,\n\tPORT290_DATA = 251,\n\tPORT291_DATA = 252,\n\tPORT292_DATA = 253,\n\tPORT293_DATA = 254,\n\tPORT294_DATA = 255,\n\tPORT295_DATA = 256,\n\tPORT296_DATA = 257,\n\tPORT297_DATA = 258,\n\tPORT298_DATA = 259,\n\tPORT299_DATA = 260,\n\tPORT300_DATA = 261,\n\tPORT301_DATA = 262,\n\tPORT302_DATA = 263,\n\tPORT303_DATA = 264,\n\tPORT304_DATA = 265,\n\tPORT305_DATA = 266,\n\tPORT306_DATA = 267,\n\tPORT307_DATA = 268,\n\tPORT308_DATA = 269,\n\tPORT309_DATA = 270,\n\tPINMUX_DATA_END___2 = 271,\n\tPINMUX_INPUT_BEGIN = 272,\n\tPORT0_IN = 273,\n\tPORT1_IN = 274,\n\tPORT2_IN = 275,\n\tPORT3_IN = 276,\n\tPORT4_IN = 277,\n\tPORT5_IN = 278,\n\tPORT6_IN = 279,\n\tPORT7_IN = 280,\n\tPORT8_IN = 281,\n\tPORT9_IN = 282,\n\tPORT10_IN = 283,\n\tPORT11_IN = 284,\n\tPORT12_IN = 285,\n\tPORT13_IN = 286,\n\tPORT14_IN = 287,\n\tPORT15_IN = 288,\n\tPORT16_IN = 289,\n\tPORT17_IN = 290,\n\tPORT18_IN = 291,\n\tPORT19_IN = 292,\n\tPORT20_IN = 293,\n\tPORT21_IN = 294,\n\tPORT22_IN = 295,\n\tPORT23_IN = 296,\n\tPORT24_IN = 297,\n\tPORT25_IN = 298,\n\tPORT26_IN = 299,\n\tPORT27_IN = 300,\n\tPORT28_IN = 301,\n\tPORT29_IN = 302,\n\tPORT30_IN = 303,\n\tPORT31_IN = 304,\n\tPORT32_IN = 305,\n\tPORT33_IN = 306,\n\tPORT34_IN = 307,\n\tPORT35_IN = 308,\n\tPORT36_IN = 309,\n\tPORT37_IN = 310,\n\tPORT38_IN = 311,\n\tPORT39_IN = 312,\n\tPORT40_IN = 313,\n\tPORT41_IN = 314,\n\tPORT42_IN = 315,\n\tPORT43_IN = 316,\n\tPORT44_IN = 317,\n\tPORT45_IN = 318,\n\tPORT46_IN = 319,\n\tPORT47_IN = 320,\n\tPORT48_IN = 321,\n\tPORT49_IN = 322,\n\tPORT50_IN = 323,\n\tPORT51_IN = 324,\n\tPORT52_IN = 325,\n\tPORT53_IN = 326,\n\tPORT54_IN = 327,\n\tPORT55_IN = 328,\n\tPORT56_IN = 329,\n\tPORT57_IN = 330,\n\tPORT58_IN = 331,\n\tPORT59_IN = 332,\n\tPORT60_IN = 333,\n\tPORT61_IN = 334,\n\tPORT62_IN = 335,\n\tPORT63_IN = 336,\n\tPORT64_IN = 337,\n\tPORT65_IN = 338,\n\tPORT66_IN = 339,\n\tPORT67_IN = 340,\n\tPORT68_IN = 341,\n\tPORT69_IN = 342,\n\tPORT70_IN = 343,\n\tPORT71_IN = 344,\n\tPORT72_IN = 345,\n\tPORT73_IN = 346,\n\tPORT74_IN = 347,\n\tPORT75_IN = 348,\n\tPORT76_IN = 349,\n\tPORT77_IN = 350,\n\tPORT78_IN = 351,\n\tPORT79_IN = 352,\n\tPORT80_IN = 353,\n\tPORT81_IN = 354,\n\tPORT82_IN = 355,\n\tPORT83_IN = 356,\n\tPORT84_IN = 357,\n\tPORT85_IN = 358,\n\tPORT86_IN = 359,\n\tPORT87_IN = 360,\n\tPORT88_IN = 361,\n\tPORT89_IN = 362,\n\tPORT90_IN = 363,\n\tPORT91_IN = 364,\n\tPORT92_IN = 365,\n\tPORT93_IN = 366,\n\tPORT94_IN = 367,\n\tPORT95_IN = 368,\n\tPORT96_IN = 369,\n\tPORT97_IN = 370,\n\tPORT98_IN = 371,\n\tPORT99_IN = 372,\n\tPORT100_IN = 373,\n\tPORT101_IN = 374,\n\tPORT102_IN = 375,\n\tPORT103_IN = 376,\n\tPORT104_IN = 377,\n\tPORT105_IN = 378,\n\tPORT106_IN = 379,\n\tPORT107_IN = 380,\n\tPORT108_IN = 381,\n\tPORT109_IN = 382,\n\tPORT110_IN = 383,\n\tPORT111_IN = 384,\n\tPORT112_IN = 385,\n\tPORT113_IN = 386,\n\tPORT114_IN = 387,\n\tPORT115_IN = 388,\n\tPORT116_IN = 389,\n\tPORT117_IN = 390,\n\tPORT118_IN = 391,\n\tPORT128_IN = 392,\n\tPORT129_IN = 393,\n\tPORT130_IN = 394,\n\tPORT131_IN = 395,\n\tPORT132_IN = 396,\n\tPORT133_IN = 397,\n\tPORT134_IN = 398,\n\tPORT135_IN = 399,\n\tPORT136_IN = 400,\n\tPORT137_IN = 401,\n\tPORT138_IN = 402,\n\tPORT139_IN = 403,\n\tPORT140_IN = 404,\n\tPORT141_IN = 405,\n\tPORT142_IN = 406,\n\tPORT143_IN = 407,\n\tPORT144_IN = 408,\n\tPORT145_IN = 409,\n\tPORT146_IN = 410,\n\tPORT147_IN = 411,\n\tPORT148_IN = 412,\n\tPORT149_IN = 413,\n\tPORT150_IN = 414,\n\tPORT151_IN = 415,\n\tPORT152_IN = 416,\n\tPORT153_IN = 417,\n\tPORT154_IN = 418,\n\tPORT155_IN = 419,\n\tPORT156_IN = 420,\n\tPORT157_IN = 421,\n\tPORT158_IN = 422,\n\tPORT159_IN = 423,\n\tPORT160_IN = 424,\n\tPORT161_IN = 425,\n\tPORT162_IN = 426,\n\tPORT163_IN = 427,\n\tPORT164_IN = 428,\n\tPORT192_IN = 429,\n\tPORT193_IN = 430,\n\tPORT194_IN = 431,\n\tPORT195_IN = 432,\n\tPORT196_IN = 433,\n\tPORT197_IN = 434,\n\tPORT198_IN = 435,\n\tPORT199_IN = 436,\n\tPORT200_IN = 437,\n\tPORT201_IN = 438,\n\tPORT202_IN = 439,\n\tPORT203_IN = 440,\n\tPORT204_IN = 441,\n\tPORT205_IN = 442,\n\tPORT206_IN = 443,\n\tPORT207_IN = 444,\n\tPORT208_IN = 445,\n\tPORT209_IN = 446,\n\tPORT210_IN = 447,\n\tPORT211_IN = 448,\n\tPORT212_IN = 449,\n\tPORT213_IN = 450,\n\tPORT214_IN = 451,\n\tPORT215_IN = 452,\n\tPORT216_IN = 453,\n\tPORT217_IN = 454,\n\tPORT218_IN = 455,\n\tPORT219_IN = 456,\n\tPORT220_IN = 457,\n\tPORT221_IN = 458,\n\tPORT222_IN = 459,\n\tPORT223_IN = 460,\n\tPORT224_IN = 461,\n\tPORT225_IN = 462,\n\tPORT226_IN = 463,\n\tPORT227_IN = 464,\n\tPORT228_IN = 465,\n\tPORT229_IN = 466,\n\tPORT230_IN = 467,\n\tPORT231_IN = 468,\n\tPORT232_IN = 469,\n\tPORT233_IN = 470,\n\tPORT234_IN = 471,\n\tPORT235_IN = 472,\n\tPORT236_IN = 473,\n\tPORT237_IN = 474,\n\tPORT238_IN = 475,\n\tPORT239_IN = 476,\n\tPORT240_IN = 477,\n\tPORT241_IN = 478,\n\tPORT242_IN = 479,\n\tPORT243_IN = 480,\n\tPORT244_IN = 481,\n\tPORT245_IN = 482,\n\tPORT246_IN = 483,\n\tPORT247_IN = 484,\n\tPORT248_IN = 485,\n\tPORT249_IN = 486,\n\tPORT250_IN = 487,\n\tPORT251_IN = 488,\n\tPORT252_IN = 489,\n\tPORT253_IN = 490,\n\tPORT254_IN = 491,\n\tPORT255_IN = 492,\n\tPORT256_IN = 493,\n\tPORT257_IN = 494,\n\tPORT258_IN = 495,\n\tPORT259_IN = 496,\n\tPORT260_IN = 497,\n\tPORT261_IN = 498,\n\tPORT262_IN = 499,\n\tPORT263_IN = 500,\n\tPORT264_IN = 501,\n\tPORT265_IN = 502,\n\tPORT266_IN = 503,\n\tPORT267_IN = 504,\n\tPORT268_IN = 505,\n\tPORT269_IN = 506,\n\tPORT270_IN = 507,\n\tPORT271_IN = 508,\n\tPORT272_IN = 509,\n\tPORT273_IN = 510,\n\tPORT274_IN = 511,\n\tPORT275_IN = 512,\n\tPORT276_IN = 513,\n\tPORT277_IN = 514,\n\tPORT278_IN = 515,\n\tPORT279_IN = 516,\n\tPORT280_IN = 517,\n\tPORT281_IN = 518,\n\tPORT282_IN = 519,\n\tPORT288_IN = 520,\n\tPORT289_IN = 521,\n\tPORT290_IN = 522,\n\tPORT291_IN = 523,\n\tPORT292_IN = 524,\n\tPORT293_IN = 525,\n\tPORT294_IN = 526,\n\tPORT295_IN = 527,\n\tPORT296_IN = 528,\n\tPORT297_IN = 529,\n\tPORT298_IN = 530,\n\tPORT299_IN = 531,\n\tPORT300_IN = 532,\n\tPORT301_IN = 533,\n\tPORT302_IN = 534,\n\tPORT303_IN = 535,\n\tPORT304_IN = 536,\n\tPORT305_IN = 537,\n\tPORT306_IN = 538,\n\tPORT307_IN = 539,\n\tPORT308_IN = 540,\n\tPORT309_IN = 541,\n\tPINMUX_INPUT_END = 542,\n\tPINMUX_OUTPUT_BEGIN = 543,\n\tPORT0_OUT = 544,\n\tPORT1_OUT = 545,\n\tPORT2_OUT = 546,\n\tPORT3_OUT = 547,\n\tPORT4_OUT = 548,\n\tPORT5_OUT = 549,\n\tPORT6_OUT = 550,\n\tPORT7_OUT = 551,\n\tPORT8_OUT = 552,\n\tPORT9_OUT = 553,\n\tPORT10_OUT = 554,\n\tPORT11_OUT = 555,\n\tPORT12_OUT = 556,\n\tPORT13_OUT = 557,\n\tPORT14_OUT = 558,\n\tPORT15_OUT = 559,\n\tPORT16_OUT = 560,\n\tPORT17_OUT = 561,\n\tPORT18_OUT = 562,\n\tPORT19_OUT = 563,\n\tPORT20_OUT = 564,\n\tPORT21_OUT = 565,\n\tPORT22_OUT = 566,\n\tPORT23_OUT = 567,\n\tPORT24_OUT = 568,\n\tPORT25_OUT = 569,\n\tPORT26_OUT = 570,\n\tPORT27_OUT = 571,\n\tPORT28_OUT = 572,\n\tPORT29_OUT = 573,\n\tPORT30_OUT = 574,\n\tPORT31_OUT = 575,\n\tPORT32_OUT = 576,\n\tPORT33_OUT = 577,\n\tPORT34_OUT = 578,\n\tPORT35_OUT = 579,\n\tPORT36_OUT = 580,\n\tPORT37_OUT = 581,\n\tPORT38_OUT = 582,\n\tPORT39_OUT = 583,\n\tPORT40_OUT = 584,\n\tPORT41_OUT = 585,\n\tPORT42_OUT = 586,\n\tPORT43_OUT = 587,\n\tPORT44_OUT = 588,\n\tPORT45_OUT = 589,\n\tPORT46_OUT = 590,\n\tPORT47_OUT = 591,\n\tPORT48_OUT = 592,\n\tPORT49_OUT = 593,\n\tPORT50_OUT = 594,\n\tPORT51_OUT = 595,\n\tPORT52_OUT = 596,\n\tPORT53_OUT = 597,\n\tPORT54_OUT = 598,\n\tPORT55_OUT = 599,\n\tPORT56_OUT = 600,\n\tPORT57_OUT = 601,\n\tPORT58_OUT = 602,\n\tPORT59_OUT = 603,\n\tPORT60_OUT = 604,\n\tPORT61_OUT = 605,\n\tPORT62_OUT = 606,\n\tPORT63_OUT = 607,\n\tPORT64_OUT = 608,\n\tPORT65_OUT = 609,\n\tPORT66_OUT = 610,\n\tPORT67_OUT = 611,\n\tPORT68_OUT = 612,\n\tPORT69_OUT = 613,\n\tPORT70_OUT = 614,\n\tPORT71_OUT = 615,\n\tPORT72_OUT = 616,\n\tPORT73_OUT = 617,\n\tPORT74_OUT = 618,\n\tPORT75_OUT = 619,\n\tPORT76_OUT = 620,\n\tPORT77_OUT = 621,\n\tPORT78_OUT = 622,\n\tPORT79_OUT = 623,\n\tPORT80_OUT = 624,\n\tPORT81_OUT = 625,\n\tPORT82_OUT = 626,\n\tPORT83_OUT = 627,\n\tPORT84_OUT = 628,\n\tPORT85_OUT = 629,\n\tPORT86_OUT = 630,\n\tPORT87_OUT = 631,\n\tPORT88_OUT = 632,\n\tPORT89_OUT = 633,\n\tPORT90_OUT = 634,\n\tPORT91_OUT = 635,\n\tPORT92_OUT = 636,\n\tPORT93_OUT = 637,\n\tPORT94_OUT = 638,\n\tPORT95_OUT = 639,\n\tPORT96_OUT = 640,\n\tPORT97_OUT = 641,\n\tPORT98_OUT = 642,\n\tPORT99_OUT = 643,\n\tPORT100_OUT = 644,\n\tPORT101_OUT = 645,\n\tPORT102_OUT = 646,\n\tPORT103_OUT = 647,\n\tPORT104_OUT = 648,\n\tPORT105_OUT = 649,\n\tPORT106_OUT = 650,\n\tPORT107_OUT = 651,\n\tPORT108_OUT = 652,\n\tPORT109_OUT = 653,\n\tPORT110_OUT = 654,\n\tPORT111_OUT = 655,\n\tPORT112_OUT = 656,\n\tPORT113_OUT = 657,\n\tPORT114_OUT = 658,\n\tPORT115_OUT = 659,\n\tPORT116_OUT = 660,\n\tPORT117_OUT = 661,\n\tPORT118_OUT = 662,\n\tPORT128_OUT = 663,\n\tPORT129_OUT = 664,\n\tPORT130_OUT = 665,\n\tPORT131_OUT = 666,\n\tPORT132_OUT = 667,\n\tPORT133_OUT = 668,\n\tPORT134_OUT = 669,\n\tPORT135_OUT = 670,\n\tPORT136_OUT = 671,\n\tPORT137_OUT = 672,\n\tPORT138_OUT = 673,\n\tPORT139_OUT = 674,\n\tPORT140_OUT = 675,\n\tPORT141_OUT = 676,\n\tPORT142_OUT = 677,\n\tPORT143_OUT = 678,\n\tPORT144_OUT = 679,\n\tPORT145_OUT = 680,\n\tPORT146_OUT = 681,\n\tPORT147_OUT = 682,\n\tPORT148_OUT = 683,\n\tPORT149_OUT = 684,\n\tPORT150_OUT = 685,\n\tPORT151_OUT = 686,\n\tPORT152_OUT = 687,\n\tPORT153_OUT = 688,\n\tPORT154_OUT = 689,\n\tPORT155_OUT = 690,\n\tPORT156_OUT = 691,\n\tPORT157_OUT = 692,\n\tPORT158_OUT = 693,\n\tPORT159_OUT = 694,\n\tPORT160_OUT = 695,\n\tPORT161_OUT = 696,\n\tPORT162_OUT = 697,\n\tPORT163_OUT = 698,\n\tPORT164_OUT = 699,\n\tPORT192_OUT = 700,\n\tPORT193_OUT = 701,\n\tPORT194_OUT = 702,\n\tPORT195_OUT = 703,\n\tPORT196_OUT = 704,\n\tPORT197_OUT = 705,\n\tPORT198_OUT = 706,\n\tPORT199_OUT = 707,\n\tPORT200_OUT = 708,\n\tPORT201_OUT = 709,\n\tPORT202_OUT = 710,\n\tPORT203_OUT = 711,\n\tPORT204_OUT = 712,\n\tPORT205_OUT = 713,\n\tPORT206_OUT = 714,\n\tPORT207_OUT = 715,\n\tPORT208_OUT = 716,\n\tPORT209_OUT = 717,\n\tPORT210_OUT = 718,\n\tPORT211_OUT = 719,\n\tPORT212_OUT = 720,\n\tPORT213_OUT = 721,\n\tPORT214_OUT = 722,\n\tPORT215_OUT = 723,\n\tPORT216_OUT = 724,\n\tPORT217_OUT = 725,\n\tPORT218_OUT = 726,\n\tPORT219_OUT = 727,\n\tPORT220_OUT = 728,\n\tPORT221_OUT = 729,\n\tPORT222_OUT = 730,\n\tPORT223_OUT = 731,\n\tPORT224_OUT = 732,\n\tPORT225_OUT = 733,\n\tPORT226_OUT = 734,\n\tPORT227_OUT = 735,\n\tPORT228_OUT = 736,\n\tPORT229_OUT = 737,\n\tPORT230_OUT = 738,\n\tPORT231_OUT = 739,\n\tPORT232_OUT = 740,\n\tPORT233_OUT = 741,\n\tPORT234_OUT = 742,\n\tPORT235_OUT = 743,\n\tPORT236_OUT = 744,\n\tPORT237_OUT = 745,\n\tPORT238_OUT = 746,\n\tPORT239_OUT = 747,\n\tPORT240_OUT = 748,\n\tPORT241_OUT = 749,\n\tPORT242_OUT = 750,\n\tPORT243_OUT = 751,\n\tPORT244_OUT = 752,\n\tPORT245_OUT = 753,\n\tPORT246_OUT = 754,\n\tPORT247_OUT = 755,\n\tPORT248_OUT = 756,\n\tPORT249_OUT = 757,\n\tPORT250_OUT = 758,\n\tPORT251_OUT = 759,\n\tPORT252_OUT = 760,\n\tPORT253_OUT = 761,\n\tPORT254_OUT = 762,\n\tPORT255_OUT = 763,\n\tPORT256_OUT = 764,\n\tPORT257_OUT = 765,\n\tPORT258_OUT = 766,\n\tPORT259_OUT = 767,\n\tPORT260_OUT = 768,\n\tPORT261_OUT = 769,\n\tPORT262_OUT = 770,\n\tPORT263_OUT = 771,\n\tPORT264_OUT = 772,\n\tPORT265_OUT = 773,\n\tPORT266_OUT = 774,\n\tPORT267_OUT = 775,\n\tPORT268_OUT = 776,\n\tPORT269_OUT = 777,\n\tPORT270_OUT = 778,\n\tPORT271_OUT = 779,\n\tPORT272_OUT = 780,\n\tPORT273_OUT = 781,\n\tPORT274_OUT = 782,\n\tPORT275_OUT = 783,\n\tPORT276_OUT = 784,\n\tPORT277_OUT = 785,\n\tPORT278_OUT = 786,\n\tPORT279_OUT = 787,\n\tPORT280_OUT = 788,\n\tPORT281_OUT = 789,\n\tPORT282_OUT = 790,\n\tPORT288_OUT = 791,\n\tPORT289_OUT = 792,\n\tPORT290_OUT = 793,\n\tPORT291_OUT = 794,\n\tPORT292_OUT = 795,\n\tPORT293_OUT = 796,\n\tPORT294_OUT = 797,\n\tPORT295_OUT = 798,\n\tPORT296_OUT = 799,\n\tPORT297_OUT = 800,\n\tPORT298_OUT = 801,\n\tPORT299_OUT = 802,\n\tPORT300_OUT = 803,\n\tPORT301_OUT = 804,\n\tPORT302_OUT = 805,\n\tPORT303_OUT = 806,\n\tPORT304_OUT = 807,\n\tPORT305_OUT = 808,\n\tPORT306_OUT = 809,\n\tPORT307_OUT = 810,\n\tPORT308_OUT = 811,\n\tPORT309_OUT = 812,\n\tPINMUX_OUTPUT_END = 813,\n\tPINMUX_FUNCTION_BEGIN___2 = 814,\n\tPORT0_FN_IN = 815,\n\tPORT1_FN_IN = 816,\n\tPORT2_FN_IN = 817,\n\tPORT3_FN_IN = 818,\n\tPORT4_FN_IN = 819,\n\tPORT5_FN_IN = 820,\n\tPORT6_FN_IN = 821,\n\tPORT7_FN_IN = 822,\n\tPORT8_FN_IN = 823,\n\tPORT9_FN_IN = 824,\n\tPORT10_FN_IN = 825,\n\tPORT11_FN_IN = 826,\n\tPORT12_FN_IN = 827,\n\tPORT13_FN_IN = 828,\n\tPORT14_FN_IN = 829,\n\tPORT15_FN_IN = 830,\n\tPORT16_FN_IN = 831,\n\tPORT17_FN_IN = 832,\n\tPORT18_FN_IN = 833,\n\tPORT19_FN_IN = 834,\n\tPORT20_FN_IN = 835,\n\tPORT21_FN_IN = 836,\n\tPORT22_FN_IN = 837,\n\tPORT23_FN_IN = 838,\n\tPORT24_FN_IN = 839,\n\tPORT25_FN_IN = 840,\n\tPORT26_FN_IN = 841,\n\tPORT27_FN_IN = 842,\n\tPORT28_FN_IN = 843,\n\tPORT29_FN_IN = 844,\n\tPORT30_FN_IN = 845,\n\tPORT31_FN_IN = 846,\n\tPORT32_FN_IN = 847,\n\tPORT33_FN_IN = 848,\n\tPORT34_FN_IN = 849,\n\tPORT35_FN_IN = 850,\n\tPORT36_FN_IN = 851,\n\tPORT37_FN_IN = 852,\n\tPORT38_FN_IN = 853,\n\tPORT39_FN_IN = 854,\n\tPORT40_FN_IN = 855,\n\tPORT41_FN_IN = 856,\n\tPORT42_FN_IN = 857,\n\tPORT43_FN_IN = 858,\n\tPORT44_FN_IN = 859,\n\tPORT45_FN_IN = 860,\n\tPORT46_FN_IN = 861,\n\tPORT47_FN_IN = 862,\n\tPORT48_FN_IN = 863,\n\tPORT49_FN_IN = 864,\n\tPORT50_FN_IN = 865,\n\tPORT51_FN_IN = 866,\n\tPORT52_FN_IN = 867,\n\tPORT53_FN_IN = 868,\n\tPORT54_FN_IN = 869,\n\tPORT55_FN_IN = 870,\n\tPORT56_FN_IN = 871,\n\tPORT57_FN_IN = 872,\n\tPORT58_FN_IN = 873,\n\tPORT59_FN_IN = 874,\n\tPORT60_FN_IN = 875,\n\tPORT61_FN_IN = 876,\n\tPORT62_FN_IN = 877,\n\tPORT63_FN_IN = 878,\n\tPORT64_FN_IN = 879,\n\tPORT65_FN_IN = 880,\n\tPORT66_FN_IN = 881,\n\tPORT67_FN_IN = 882,\n\tPORT68_FN_IN = 883,\n\tPORT69_FN_IN = 884,\n\tPORT70_FN_IN = 885,\n\tPORT71_FN_IN = 886,\n\tPORT72_FN_IN = 887,\n\tPORT73_FN_IN = 888,\n\tPORT74_FN_IN = 889,\n\tPORT75_FN_IN = 890,\n\tPORT76_FN_IN = 891,\n\tPORT77_FN_IN = 892,\n\tPORT78_FN_IN = 893,\n\tPORT79_FN_IN = 894,\n\tPORT80_FN_IN = 895,\n\tPORT81_FN_IN = 896,\n\tPORT82_FN_IN = 897,\n\tPORT83_FN_IN = 898,\n\tPORT84_FN_IN = 899,\n\tPORT85_FN_IN = 900,\n\tPORT86_FN_IN = 901,\n\tPORT87_FN_IN = 902,\n\tPORT88_FN_IN = 903,\n\tPORT89_FN_IN = 904,\n\tPORT90_FN_IN = 905,\n\tPORT91_FN_IN = 906,\n\tPORT92_FN_IN = 907,\n\tPORT93_FN_IN = 908,\n\tPORT94_FN_IN = 909,\n\tPORT95_FN_IN = 910,\n\tPORT96_FN_IN = 911,\n\tPORT97_FN_IN = 912,\n\tPORT98_FN_IN = 913,\n\tPORT99_FN_IN = 914,\n\tPORT100_FN_IN = 915,\n\tPORT101_FN_IN = 916,\n\tPORT102_FN_IN = 917,\n\tPORT103_FN_IN = 918,\n\tPORT104_FN_IN = 919,\n\tPORT105_FN_IN = 920,\n\tPORT106_FN_IN = 921,\n\tPORT107_FN_IN = 922,\n\tPORT108_FN_IN = 923,\n\tPORT109_FN_IN = 924,\n\tPORT110_FN_IN = 925,\n\tPORT111_FN_IN = 926,\n\tPORT112_FN_IN = 927,\n\tPORT113_FN_IN = 928,\n\tPORT114_FN_IN = 929,\n\tPORT115_FN_IN = 930,\n\tPORT116_FN_IN = 931,\n\tPORT117_FN_IN = 932,\n\tPORT118_FN_IN = 933,\n\tPORT128_FN_IN = 934,\n\tPORT129_FN_IN = 935,\n\tPORT130_FN_IN = 936,\n\tPORT131_FN_IN = 937,\n\tPORT132_FN_IN = 938,\n\tPORT133_FN_IN = 939,\n\tPORT134_FN_IN = 940,\n\tPORT135_FN_IN = 941,\n\tPORT136_FN_IN = 942,\n\tPORT137_FN_IN = 943,\n\tPORT138_FN_IN = 944,\n\tPORT139_FN_IN = 945,\n\tPORT140_FN_IN = 946,\n\tPORT141_FN_IN = 947,\n\tPORT142_FN_IN = 948,\n\tPORT143_FN_IN = 949,\n\tPORT144_FN_IN = 950,\n\tPORT145_FN_IN = 951,\n\tPORT146_FN_IN = 952,\n\tPORT147_FN_IN = 953,\n\tPORT148_FN_IN = 954,\n\tPORT149_FN_IN = 955,\n\tPORT150_FN_IN = 956,\n\tPORT151_FN_IN = 957,\n\tPORT152_FN_IN = 958,\n\tPORT153_FN_IN = 959,\n\tPORT154_FN_IN = 960,\n\tPORT155_FN_IN = 961,\n\tPORT156_FN_IN = 962,\n\tPORT157_FN_IN = 963,\n\tPORT158_FN_IN = 964,\n\tPORT159_FN_IN = 965,\n\tPORT160_FN_IN = 966,\n\tPORT161_FN_IN = 967,\n\tPORT162_FN_IN = 968,\n\tPORT163_FN_IN = 969,\n\tPORT164_FN_IN = 970,\n\tPORT192_FN_IN = 971,\n\tPORT193_FN_IN = 972,\n\tPORT194_FN_IN = 973,\n\tPORT195_FN_IN = 974,\n\tPORT196_FN_IN = 975,\n\tPORT197_FN_IN = 976,\n\tPORT198_FN_IN = 977,\n\tPORT199_FN_IN = 978,\n\tPORT200_FN_IN = 979,\n\tPORT201_FN_IN = 980,\n\tPORT202_FN_IN = 981,\n\tPORT203_FN_IN = 982,\n\tPORT204_FN_IN = 983,\n\tPORT205_FN_IN = 984,\n\tPORT206_FN_IN = 985,\n\tPORT207_FN_IN = 986,\n\tPORT208_FN_IN = 987,\n\tPORT209_FN_IN = 988,\n\tPORT210_FN_IN = 989,\n\tPORT211_FN_IN = 990,\n\tPORT212_FN_IN = 991,\n\tPORT213_FN_IN = 992,\n\tPORT214_FN_IN = 993,\n\tPORT215_FN_IN = 994,\n\tPORT216_FN_IN = 995,\n\tPORT217_FN_IN = 996,\n\tPORT218_FN_IN = 997,\n\tPORT219_FN_IN = 998,\n\tPORT220_FN_IN = 999,\n\tPORT221_FN_IN = 1000,\n\tPORT222_FN_IN = 1001,\n\tPORT223_FN_IN = 1002,\n\tPORT224_FN_IN = 1003,\n\tPORT225_FN_IN = 1004,\n\tPORT226_FN_IN = 1005,\n\tPORT227_FN_IN = 1006,\n\tPORT228_FN_IN = 1007,\n\tPORT229_FN_IN = 1008,\n\tPORT230_FN_IN = 1009,\n\tPORT231_FN_IN = 1010,\n\tPORT232_FN_IN = 1011,\n\tPORT233_FN_IN = 1012,\n\tPORT234_FN_IN = 1013,\n\tPORT235_FN_IN = 1014,\n\tPORT236_FN_IN = 1015,\n\tPORT237_FN_IN = 1016,\n\tPORT238_FN_IN = 1017,\n\tPORT239_FN_IN = 1018,\n\tPORT240_FN_IN = 1019,\n\tPORT241_FN_IN = 1020,\n\tPORT242_FN_IN = 1021,\n\tPORT243_FN_IN = 1022,\n\tPORT244_FN_IN = 1023,\n\tPORT245_FN_IN = 1024,\n\tPORT246_FN_IN = 1025,\n\tPORT247_FN_IN = 1026,\n\tPORT248_FN_IN = 1027,\n\tPORT249_FN_IN = 1028,\n\tPORT250_FN_IN = 1029,\n\tPORT251_FN_IN = 1030,\n\tPORT252_FN_IN = 1031,\n\tPORT253_FN_IN = 1032,\n\tPORT254_FN_IN = 1033,\n\tPORT255_FN_IN = 1034,\n\tPORT256_FN_IN = 1035,\n\tPORT257_FN_IN = 1036,\n\tPORT258_FN_IN = 1037,\n\tPORT259_FN_IN = 1038,\n\tPORT260_FN_IN = 1039,\n\tPORT261_FN_IN = 1040,\n\tPORT262_FN_IN = 1041,\n\tPORT263_FN_IN = 1042,\n\tPORT264_FN_IN = 1043,\n\tPORT265_FN_IN = 1044,\n\tPORT266_FN_IN = 1045,\n\tPORT267_FN_IN = 1046,\n\tPORT268_FN_IN = 1047,\n\tPORT269_FN_IN = 1048,\n\tPORT270_FN_IN = 1049,\n\tPORT271_FN_IN = 1050,\n\tPORT272_FN_IN = 1051,\n\tPORT273_FN_IN = 1052,\n\tPORT274_FN_IN = 1053,\n\tPORT275_FN_IN = 1054,\n\tPORT276_FN_IN = 1055,\n\tPORT277_FN_IN = 1056,\n\tPORT278_FN_IN = 1057,\n\tPORT279_FN_IN = 1058,\n\tPORT280_FN_IN = 1059,\n\tPORT281_FN_IN = 1060,\n\tPORT282_FN_IN = 1061,\n\tPORT288_FN_IN = 1062,\n\tPORT289_FN_IN = 1063,\n\tPORT290_FN_IN = 1064,\n\tPORT291_FN_IN = 1065,\n\tPORT292_FN_IN = 1066,\n\tPORT293_FN_IN = 1067,\n\tPORT294_FN_IN = 1068,\n\tPORT295_FN_IN = 1069,\n\tPORT296_FN_IN = 1070,\n\tPORT297_FN_IN = 1071,\n\tPORT298_FN_IN = 1072,\n\tPORT299_FN_IN = 1073,\n\tPORT300_FN_IN = 1074,\n\tPORT301_FN_IN = 1075,\n\tPORT302_FN_IN = 1076,\n\tPORT303_FN_IN = 1077,\n\tPORT304_FN_IN = 1078,\n\tPORT305_FN_IN = 1079,\n\tPORT306_FN_IN = 1080,\n\tPORT307_FN_IN = 1081,\n\tPORT308_FN_IN = 1082,\n\tPORT309_FN_IN = 1083,\n\tPORT0_FN_OUT = 1084,\n\tPORT1_FN_OUT = 1085,\n\tPORT2_FN_OUT = 1086,\n\tPORT3_FN_OUT = 1087,\n\tPORT4_FN_OUT = 1088,\n\tPORT5_FN_OUT = 1089,\n\tPORT6_FN_OUT = 1090,\n\tPORT7_FN_OUT = 1091,\n\tPORT8_FN_OUT = 1092,\n\tPORT9_FN_OUT = 1093,\n\tPORT10_FN_OUT = 1094,\n\tPORT11_FN_OUT = 1095,\n\tPORT12_FN_OUT = 1096,\n\tPORT13_FN_OUT = 1097,\n\tPORT14_FN_OUT = 1098,\n\tPORT15_FN_OUT = 1099,\n\tPORT16_FN_OUT = 1100,\n\tPORT17_FN_OUT = 1101,\n\tPORT18_FN_OUT = 1102,\n\tPORT19_FN_OUT = 1103,\n\tPORT20_FN_OUT = 1104,\n\tPORT21_FN_OUT = 1105,\n\tPORT22_FN_OUT = 1106,\n\tPORT23_FN_OUT = 1107,\n\tPORT24_FN_OUT = 1108,\n\tPORT25_FN_OUT = 1109,\n\tPORT26_FN_OUT = 1110,\n\tPORT27_FN_OUT = 1111,\n\tPORT28_FN_OUT = 1112,\n\tPORT29_FN_OUT = 1113,\n\tPORT30_FN_OUT = 1114,\n\tPORT31_FN_OUT = 1115,\n\tPORT32_FN_OUT = 1116,\n\tPORT33_FN_OUT = 1117,\n\tPORT34_FN_OUT = 1118,\n\tPORT35_FN_OUT = 1119,\n\tPORT36_FN_OUT = 1120,\n\tPORT37_FN_OUT = 1121,\n\tPORT38_FN_OUT = 1122,\n\tPORT39_FN_OUT = 1123,\n\tPORT40_FN_OUT = 1124,\n\tPORT41_FN_OUT = 1125,\n\tPORT42_FN_OUT = 1126,\n\tPORT43_FN_OUT = 1127,\n\tPORT44_FN_OUT = 1128,\n\tPORT45_FN_OUT = 1129,\n\tPORT46_FN_OUT = 1130,\n\tPORT47_FN_OUT = 1131,\n\tPORT48_FN_OUT = 1132,\n\tPORT49_FN_OUT = 1133,\n\tPORT50_FN_OUT = 1134,\n\tPORT51_FN_OUT = 1135,\n\tPORT52_FN_OUT = 1136,\n\tPORT53_FN_OUT = 1137,\n\tPORT54_FN_OUT = 1138,\n\tPORT55_FN_OUT = 1139,\n\tPORT56_FN_OUT = 1140,\n\tPORT57_FN_OUT = 1141,\n\tPORT58_FN_OUT = 1142,\n\tPORT59_FN_OUT = 1143,\n\tPORT60_FN_OUT = 1144,\n\tPORT61_FN_OUT = 1145,\n\tPORT62_FN_OUT = 1146,\n\tPORT63_FN_OUT = 1147,\n\tPORT64_FN_OUT = 1148,\n\tPORT65_FN_OUT = 1149,\n\tPORT66_FN_OUT = 1150,\n\tPORT67_FN_OUT = 1151,\n\tPORT68_FN_OUT = 1152,\n\tPORT69_FN_OUT = 1153,\n\tPORT70_FN_OUT = 1154,\n\tPORT71_FN_OUT = 1155,\n\tPORT72_FN_OUT = 1156,\n\tPORT73_FN_OUT = 1157,\n\tPORT74_FN_OUT = 1158,\n\tPORT75_FN_OUT = 1159,\n\tPORT76_FN_OUT = 1160,\n\tPORT77_FN_OUT = 1161,\n\tPORT78_FN_OUT = 1162,\n\tPORT79_FN_OUT = 1163,\n\tPORT80_FN_OUT = 1164,\n\tPORT81_FN_OUT = 1165,\n\tPORT82_FN_OUT = 1166,\n\tPORT83_FN_OUT = 1167,\n\tPORT84_FN_OUT = 1168,\n\tPORT85_FN_OUT = 1169,\n\tPORT86_FN_OUT = 1170,\n\tPORT87_FN_OUT = 1171,\n\tPORT88_FN_OUT = 1172,\n\tPORT89_FN_OUT = 1173,\n\tPORT90_FN_OUT = 1174,\n\tPORT91_FN_OUT = 1175,\n\tPORT92_FN_OUT = 1176,\n\tPORT93_FN_OUT = 1177,\n\tPORT94_FN_OUT = 1178,\n\tPORT95_FN_OUT = 1179,\n\tPORT96_FN_OUT = 1180,\n\tPORT97_FN_OUT = 1181,\n\tPORT98_FN_OUT = 1182,\n\tPORT99_FN_OUT = 1183,\n\tPORT100_FN_OUT = 1184,\n\tPORT101_FN_OUT = 1185,\n\tPORT102_FN_OUT = 1186,\n\tPORT103_FN_OUT = 1187,\n\tPORT104_FN_OUT = 1188,\n\tPORT105_FN_OUT = 1189,\n\tPORT106_FN_OUT = 1190,\n\tPORT107_FN_OUT = 1191,\n\tPORT108_FN_OUT = 1192,\n\tPORT109_FN_OUT = 1193,\n\tPORT110_FN_OUT = 1194,\n\tPORT111_FN_OUT = 1195,\n\tPORT112_FN_OUT = 1196,\n\tPORT113_FN_OUT = 1197,\n\tPORT114_FN_OUT = 1198,\n\tPORT115_FN_OUT = 1199,\n\tPORT116_FN_OUT = 1200,\n\tPORT117_FN_OUT = 1201,\n\tPORT118_FN_OUT = 1202,\n\tPORT128_FN_OUT = 1203,\n\tPORT129_FN_OUT = 1204,\n\tPORT130_FN_OUT = 1205,\n\tPORT131_FN_OUT = 1206,\n\tPORT132_FN_OUT = 1207,\n\tPORT133_FN_OUT = 1208,\n\tPORT134_FN_OUT = 1209,\n\tPORT135_FN_OUT = 1210,\n\tPORT136_FN_OUT = 1211,\n\tPORT137_FN_OUT = 1212,\n\tPORT138_FN_OUT = 1213,\n\tPORT139_FN_OUT = 1214,\n\tPORT140_FN_OUT = 1215,\n\tPORT141_FN_OUT = 1216,\n\tPORT142_FN_OUT = 1217,\n\tPORT143_FN_OUT = 1218,\n\tPORT144_FN_OUT = 1219,\n\tPORT145_FN_OUT = 1220,\n\tPORT146_FN_OUT = 1221,\n\tPORT147_FN_OUT = 1222,\n\tPORT148_FN_OUT = 1223,\n\tPORT149_FN_OUT = 1224,\n\tPORT150_FN_OUT = 1225,\n\tPORT151_FN_OUT = 1226,\n\tPORT152_FN_OUT = 1227,\n\tPORT153_FN_OUT = 1228,\n\tPORT154_FN_OUT = 1229,\n\tPORT155_FN_OUT = 1230,\n\tPORT156_FN_OUT = 1231,\n\tPORT157_FN_OUT = 1232,\n\tPORT158_FN_OUT = 1233,\n\tPORT159_FN_OUT = 1234,\n\tPORT160_FN_OUT = 1235,\n\tPORT161_FN_OUT = 1236,\n\tPORT162_FN_OUT = 1237,\n\tPORT163_FN_OUT = 1238,\n\tPORT164_FN_OUT = 1239,\n\tPORT192_FN_OUT = 1240,\n\tPORT193_FN_OUT = 1241,\n\tPORT194_FN_OUT = 1242,\n\tPORT195_FN_OUT = 1243,\n\tPORT196_FN_OUT = 1244,\n\tPORT197_FN_OUT = 1245,\n\tPORT198_FN_OUT = 1246,\n\tPORT199_FN_OUT = 1247,\n\tPORT200_FN_OUT = 1248,\n\tPORT201_FN_OUT = 1249,\n\tPORT202_FN_OUT = 1250,\n\tPORT203_FN_OUT = 1251,\n\tPORT204_FN_OUT = 1252,\n\tPORT205_FN_OUT = 1253,\n\tPORT206_FN_OUT = 1254,\n\tPORT207_FN_OUT = 1255,\n\tPORT208_FN_OUT = 1256,\n\tPORT209_FN_OUT = 1257,\n\tPORT210_FN_OUT = 1258,\n\tPORT211_FN_OUT = 1259,\n\tPORT212_FN_OUT = 1260,\n\tPORT213_FN_OUT = 1261,\n\tPORT214_FN_OUT = 1262,\n\tPORT215_FN_OUT = 1263,\n\tPORT216_FN_OUT = 1264,\n\tPORT217_FN_OUT = 1265,\n\tPORT218_FN_OUT = 1266,\n\tPORT219_FN_OUT = 1267,\n\tPORT220_FN_OUT = 1268,\n\tPORT221_FN_OUT = 1269,\n\tPORT222_FN_OUT = 1270,\n\tPORT223_FN_OUT = 1271,\n\tPORT224_FN_OUT = 1272,\n\tPORT225_FN_OUT = 1273,\n\tPORT226_FN_OUT = 1274,\n\tPORT227_FN_OUT = 1275,\n\tPORT228_FN_OUT = 1276,\n\tPORT229_FN_OUT = 1277,\n\tPORT230_FN_OUT = 1278,\n\tPORT231_FN_OUT = 1279,\n\tPORT232_FN_OUT = 1280,\n\tPORT233_FN_OUT = 1281,\n\tPORT234_FN_OUT = 1282,\n\tPORT235_FN_OUT = 1283,\n\tPORT236_FN_OUT = 1284,\n\tPORT237_FN_OUT = 1285,\n\tPORT238_FN_OUT = 1286,\n\tPORT239_FN_OUT = 1287,\n\tPORT240_FN_OUT = 1288,\n\tPORT241_FN_OUT = 1289,\n\tPORT242_FN_OUT = 1290,\n\tPORT243_FN_OUT = 1291,\n\tPORT244_FN_OUT = 1292,\n\tPORT245_FN_OUT = 1293,\n\tPORT246_FN_OUT = 1294,\n\tPORT247_FN_OUT = 1295,\n\tPORT248_FN_OUT = 1296,\n\tPORT249_FN_OUT = 1297,\n\tPORT250_FN_OUT = 1298,\n\tPORT251_FN_OUT = 1299,\n\tPORT252_FN_OUT = 1300,\n\tPORT253_FN_OUT = 1301,\n\tPORT254_FN_OUT = 1302,\n\tPORT255_FN_OUT = 1303,\n\tPORT256_FN_OUT = 1304,\n\tPORT257_FN_OUT = 1305,\n\tPORT258_FN_OUT = 1306,\n\tPORT259_FN_OUT = 1307,\n\tPORT260_FN_OUT = 1308,\n\tPORT261_FN_OUT = 1309,\n\tPORT262_FN_OUT = 1310,\n\tPORT263_FN_OUT = 1311,\n\tPORT264_FN_OUT = 1312,\n\tPORT265_FN_OUT = 1313,\n\tPORT266_FN_OUT = 1314,\n\tPORT267_FN_OUT = 1315,\n\tPORT268_FN_OUT = 1316,\n\tPORT269_FN_OUT = 1317,\n\tPORT270_FN_OUT = 1318,\n\tPORT271_FN_OUT = 1319,\n\tPORT272_FN_OUT = 1320,\n\tPORT273_FN_OUT = 1321,\n\tPORT274_FN_OUT = 1322,\n\tPORT275_FN_OUT = 1323,\n\tPORT276_FN_OUT = 1324,\n\tPORT277_FN_OUT = 1325,\n\tPORT278_FN_OUT = 1326,\n\tPORT279_FN_OUT = 1327,\n\tPORT280_FN_OUT = 1328,\n\tPORT281_FN_OUT = 1329,\n\tPORT282_FN_OUT = 1330,\n\tPORT288_FN_OUT = 1331,\n\tPORT289_FN_OUT = 1332,\n\tPORT290_FN_OUT = 1333,\n\tPORT291_FN_OUT = 1334,\n\tPORT292_FN_OUT = 1335,\n\tPORT293_FN_OUT = 1336,\n\tPORT294_FN_OUT = 1337,\n\tPORT295_FN_OUT = 1338,\n\tPORT296_FN_OUT = 1339,\n\tPORT297_FN_OUT = 1340,\n\tPORT298_FN_OUT = 1341,\n\tPORT299_FN_OUT = 1342,\n\tPORT300_FN_OUT = 1343,\n\tPORT301_FN_OUT = 1344,\n\tPORT302_FN_OUT = 1345,\n\tPORT303_FN_OUT = 1346,\n\tPORT304_FN_OUT = 1347,\n\tPORT305_FN_OUT = 1348,\n\tPORT306_FN_OUT = 1349,\n\tPORT307_FN_OUT = 1350,\n\tPORT308_FN_OUT = 1351,\n\tPORT309_FN_OUT = 1352,\n\tPORT0_FN0 = 1353,\n\tPORT1_FN0 = 1354,\n\tPORT2_FN0 = 1355,\n\tPORT3_FN0 = 1356,\n\tPORT4_FN0 = 1357,\n\tPORT5_FN0 = 1358,\n\tPORT6_FN0 = 1359,\n\tPORT7_FN0 = 1360,\n\tPORT8_FN0 = 1361,\n\tPORT9_FN0 = 1362,\n\tPORT10_FN0 = 1363,\n\tPORT11_FN0 = 1364,\n\tPORT12_FN0 = 1365,\n\tPORT13_FN0 = 1366,\n\tPORT14_FN0 = 1367,\n\tPORT15_FN0 = 1368,\n\tPORT16_FN0 = 1369,\n\tPORT17_FN0 = 1370,\n\tPORT18_FN0 = 1371,\n\tPORT19_FN0 = 1372,\n\tPORT20_FN0 = 1373,\n\tPORT21_FN0 = 1374,\n\tPORT22_FN0 = 1375,\n\tPORT23_FN0 = 1376,\n\tPORT24_FN0 = 1377,\n\tPORT25_FN0 = 1378,\n\tPORT26_FN0 = 1379,\n\tPORT27_FN0 = 1380,\n\tPORT28_FN0 = 1381,\n\tPORT29_FN0 = 1382,\n\tPORT30_FN0 = 1383,\n\tPORT31_FN0 = 1384,\n\tPORT32_FN0 = 1385,\n\tPORT33_FN0 = 1386,\n\tPORT34_FN0 = 1387,\n\tPORT35_FN0 = 1388,\n\tPORT36_FN0 = 1389,\n\tPORT37_FN0 = 1390,\n\tPORT38_FN0 = 1391,\n\tPORT39_FN0 = 1392,\n\tPORT40_FN0 = 1393,\n\tPORT41_FN0 = 1394,\n\tPORT42_FN0 = 1395,\n\tPORT43_FN0 = 1396,\n\tPORT44_FN0 = 1397,\n\tPORT45_FN0 = 1398,\n\tPORT46_FN0 = 1399,\n\tPORT47_FN0 = 1400,\n\tPORT48_FN0 = 1401,\n\tPORT49_FN0 = 1402,\n\tPORT50_FN0 = 1403,\n\tPORT51_FN0 = 1404,\n\tPORT52_FN0 = 1405,\n\tPORT53_FN0 = 1406,\n\tPORT54_FN0 = 1407,\n\tPORT55_FN0 = 1408,\n\tPORT56_FN0 = 1409,\n\tPORT57_FN0 = 1410,\n\tPORT58_FN0 = 1411,\n\tPORT59_FN0 = 1412,\n\tPORT60_FN0 = 1413,\n\tPORT61_FN0 = 1414,\n\tPORT62_FN0 = 1415,\n\tPORT63_FN0 = 1416,\n\tPORT64_FN0 = 1417,\n\tPORT65_FN0 = 1418,\n\tPORT66_FN0 = 1419,\n\tPORT67_FN0 = 1420,\n\tPORT68_FN0 = 1421,\n\tPORT69_FN0 = 1422,\n\tPORT70_FN0 = 1423,\n\tPORT71_FN0 = 1424,\n\tPORT72_FN0 = 1425,\n\tPORT73_FN0 = 1426,\n\tPORT74_FN0 = 1427,\n\tPORT75_FN0 = 1428,\n\tPORT76_FN0 = 1429,\n\tPORT77_FN0 = 1430,\n\tPORT78_FN0 = 1431,\n\tPORT79_FN0 = 1432,\n\tPORT80_FN0 = 1433,\n\tPORT81_FN0 = 1434,\n\tPORT82_FN0 = 1435,\n\tPORT83_FN0 = 1436,\n\tPORT84_FN0 = 1437,\n\tPORT85_FN0 = 1438,\n\tPORT86_FN0 = 1439,\n\tPORT87_FN0 = 1440,\n\tPORT88_FN0 = 1441,\n\tPORT89_FN0 = 1442,\n\tPORT90_FN0 = 1443,\n\tPORT91_FN0 = 1444,\n\tPORT92_FN0 = 1445,\n\tPORT93_FN0 = 1446,\n\tPORT94_FN0 = 1447,\n\tPORT95_FN0 = 1448,\n\tPORT96_FN0 = 1449,\n\tPORT97_FN0 = 1450,\n\tPORT98_FN0 = 1451,\n\tPORT99_FN0 = 1452,\n\tPORT100_FN0 = 1453,\n\tPORT101_FN0 = 1454,\n\tPORT102_FN0 = 1455,\n\tPORT103_FN0 = 1456,\n\tPORT104_FN0 = 1457,\n\tPORT105_FN0 = 1458,\n\tPORT106_FN0 = 1459,\n\tPORT107_FN0 = 1460,\n\tPORT108_FN0 = 1461,\n\tPORT109_FN0 = 1462,\n\tPORT110_FN0 = 1463,\n\tPORT111_FN0 = 1464,\n\tPORT112_FN0 = 1465,\n\tPORT113_FN0 = 1466,\n\tPORT114_FN0 = 1467,\n\tPORT115_FN0 = 1468,\n\tPORT116_FN0 = 1469,\n\tPORT117_FN0 = 1470,\n\tPORT118_FN0 = 1471,\n\tPORT128_FN0 = 1472,\n\tPORT129_FN0 = 1473,\n\tPORT130_FN0 = 1474,\n\tPORT131_FN0 = 1475,\n\tPORT132_FN0 = 1476,\n\tPORT133_FN0 = 1477,\n\tPORT134_FN0 = 1478,\n\tPORT135_FN0 = 1479,\n\tPORT136_FN0 = 1480,\n\tPORT137_FN0 = 1481,\n\tPORT138_FN0 = 1482,\n\tPORT139_FN0 = 1483,\n\tPORT140_FN0 = 1484,\n\tPORT141_FN0 = 1485,\n\tPORT142_FN0 = 1486,\n\tPORT143_FN0 = 1487,\n\tPORT144_FN0 = 1488,\n\tPORT145_FN0 = 1489,\n\tPORT146_FN0 = 1490,\n\tPORT147_FN0 = 1491,\n\tPORT148_FN0 = 1492,\n\tPORT149_FN0 = 1493,\n\tPORT150_FN0 = 1494,\n\tPORT151_FN0 = 1495,\n\tPORT152_FN0 = 1496,\n\tPORT153_FN0 = 1497,\n\tPORT154_FN0 = 1498,\n\tPORT155_FN0 = 1499,\n\tPORT156_FN0 = 1500,\n\tPORT157_FN0 = 1501,\n\tPORT158_FN0 = 1502,\n\tPORT159_FN0 = 1503,\n\tPORT160_FN0 = 1504,\n\tPORT161_FN0 = 1505,\n\tPORT162_FN0 = 1506,\n\tPORT163_FN0 = 1507,\n\tPORT164_FN0 = 1508,\n\tPORT192_FN0 = 1509,\n\tPORT193_FN0 = 1510,\n\tPORT194_FN0 = 1511,\n\tPORT195_FN0 = 1512,\n\tPORT196_FN0 = 1513,\n\tPORT197_FN0 = 1514,\n\tPORT198_FN0 = 1515,\n\tPORT199_FN0 = 1516,\n\tPORT200_FN0 = 1517,\n\tPORT201_FN0 = 1518,\n\tPORT202_FN0 = 1519,\n\tPORT203_FN0 = 1520,\n\tPORT204_FN0 = 1521,\n\tPORT205_FN0 = 1522,\n\tPORT206_FN0 = 1523,\n\tPORT207_FN0 = 1524,\n\tPORT208_FN0 = 1525,\n\tPORT209_FN0 = 1526,\n\tPORT210_FN0 = 1527,\n\tPORT211_FN0 = 1528,\n\tPORT212_FN0 = 1529,\n\tPORT213_FN0 = 1530,\n\tPORT214_FN0 = 1531,\n\tPORT215_FN0 = 1532,\n\tPORT216_FN0 = 1533,\n\tPORT217_FN0 = 1534,\n\tPORT218_FN0 = 1535,\n\tPORT219_FN0 = 1536,\n\tPORT220_FN0 = 1537,\n\tPORT221_FN0 = 1538,\n\tPORT222_FN0 = 1539,\n\tPORT223_FN0 = 1540,\n\tPORT224_FN0 = 1541,\n\tPORT225_FN0 = 1542,\n\tPORT226_FN0 = 1543,\n\tPORT227_FN0 = 1544,\n\tPORT228_FN0 = 1545,\n\tPORT229_FN0 = 1546,\n\tPORT230_FN0 = 1547,\n\tPORT231_FN0 = 1548,\n\tPORT232_FN0 = 1549,\n\tPORT233_FN0 = 1550,\n\tPORT234_FN0 = 1551,\n\tPORT235_FN0 = 1552,\n\tPORT236_FN0 = 1553,\n\tPORT237_FN0 = 1554,\n\tPORT238_FN0 = 1555,\n\tPORT239_FN0 = 1556,\n\tPORT240_FN0 = 1557,\n\tPORT241_FN0 = 1558,\n\tPORT242_FN0 = 1559,\n\tPORT243_FN0 = 1560,\n\tPORT244_FN0 = 1561,\n\tPORT245_FN0 = 1562,\n\tPORT246_FN0 = 1563,\n\tPORT247_FN0 = 1564,\n\tPORT248_FN0 = 1565,\n\tPORT249_FN0 = 1566,\n\tPORT250_FN0 = 1567,\n\tPORT251_FN0 = 1568,\n\tPORT252_FN0 = 1569,\n\tPORT253_FN0 = 1570,\n\tPORT254_FN0 = 1571,\n\tPORT255_FN0 = 1572,\n\tPORT256_FN0 = 1573,\n\tPORT257_FN0 = 1574,\n\tPORT258_FN0 = 1575,\n\tPORT259_FN0 = 1576,\n\tPORT260_FN0 = 1577,\n\tPORT261_FN0 = 1578,\n\tPORT262_FN0 = 1579,\n\tPORT263_FN0 = 1580,\n\tPORT264_FN0 = 1581,\n\tPORT265_FN0 = 1582,\n\tPORT266_FN0 = 1583,\n\tPORT267_FN0 = 1584,\n\tPORT268_FN0 = 1585,\n\tPORT269_FN0 = 1586,\n\tPORT270_FN0 = 1587,\n\tPORT271_FN0 = 1588,\n\tPORT272_FN0 = 1589,\n\tPORT273_FN0 = 1590,\n\tPORT274_FN0 = 1591,\n\tPORT275_FN0 = 1592,\n\tPORT276_FN0 = 1593,\n\tPORT277_FN0 = 1594,\n\tPORT278_FN0 = 1595,\n\tPORT279_FN0 = 1596,\n\tPORT280_FN0 = 1597,\n\tPORT281_FN0 = 1598,\n\tPORT282_FN0 = 1599,\n\tPORT288_FN0 = 1600,\n\tPORT289_FN0 = 1601,\n\tPORT290_FN0 = 1602,\n\tPORT291_FN0 = 1603,\n\tPORT292_FN0 = 1604,\n\tPORT293_FN0 = 1605,\n\tPORT294_FN0 = 1606,\n\tPORT295_FN0 = 1607,\n\tPORT296_FN0 = 1608,\n\tPORT297_FN0 = 1609,\n\tPORT298_FN0 = 1610,\n\tPORT299_FN0 = 1611,\n\tPORT300_FN0 = 1612,\n\tPORT301_FN0 = 1613,\n\tPORT302_FN0 = 1614,\n\tPORT303_FN0 = 1615,\n\tPORT304_FN0 = 1616,\n\tPORT305_FN0 = 1617,\n\tPORT306_FN0 = 1618,\n\tPORT307_FN0 = 1619,\n\tPORT308_FN0 = 1620,\n\tPORT309_FN0 = 1621,\n\tPORT0_FN1 = 1622,\n\tPORT1_FN1 = 1623,\n\tPORT2_FN1 = 1624,\n\tPORT3_FN1 = 1625,\n\tPORT4_FN1 = 1626,\n\tPORT5_FN1 = 1627,\n\tPORT6_FN1 = 1628,\n\tPORT7_FN1 = 1629,\n\tPORT8_FN1 = 1630,\n\tPORT9_FN1 = 1631,\n\tPORT10_FN1 = 1632,\n\tPORT11_FN1 = 1633,\n\tPORT12_FN1 = 1634,\n\tPORT13_FN1 = 1635,\n\tPORT14_FN1 = 1636,\n\tPORT15_FN1 = 1637,\n\tPORT16_FN1 = 1638,\n\tPORT17_FN1 = 1639,\n\tPORT18_FN1 = 1640,\n\tPORT19_FN1 = 1641,\n\tPORT20_FN1 = 1642,\n\tPORT21_FN1 = 1643,\n\tPORT22_FN1 = 1644,\n\tPORT23_FN1 = 1645,\n\tPORT24_FN1 = 1646,\n\tPORT25_FN1 = 1647,\n\tPORT26_FN1 = 1648,\n\tPORT27_FN1 = 1649,\n\tPORT28_FN1 = 1650,\n\tPORT29_FN1 = 1651,\n\tPORT30_FN1 = 1652,\n\tPORT31_FN1 = 1653,\n\tPORT32_FN1 = 1654,\n\tPORT33_FN1 = 1655,\n\tPORT34_FN1 = 1656,\n\tPORT35_FN1 = 1657,\n\tPORT36_FN1 = 1658,\n\tPORT37_FN1 = 1659,\n\tPORT38_FN1 = 1660,\n\tPORT39_FN1 = 1661,\n\tPORT40_FN1 = 1662,\n\tPORT41_FN1 = 1663,\n\tPORT42_FN1 = 1664,\n\tPORT43_FN1 = 1665,\n\tPORT44_FN1 = 1666,\n\tPORT45_FN1 = 1667,\n\tPORT46_FN1 = 1668,\n\tPORT47_FN1 = 1669,\n\tPORT48_FN1 = 1670,\n\tPORT49_FN1 = 1671,\n\tPORT50_FN1 = 1672,\n\tPORT51_FN1 = 1673,\n\tPORT52_FN1 = 1674,\n\tPORT53_FN1 = 1675,\n\tPORT54_FN1 = 1676,\n\tPORT55_FN1 = 1677,\n\tPORT56_FN1 = 1678,\n\tPORT57_FN1 = 1679,\n\tPORT58_FN1 = 1680,\n\tPORT59_FN1 = 1681,\n\tPORT60_FN1 = 1682,\n\tPORT61_FN1 = 1683,\n\tPORT62_FN1 = 1684,\n\tPORT63_FN1 = 1685,\n\tPORT64_FN1 = 1686,\n\tPORT65_FN1 = 1687,\n\tPORT66_FN1 = 1688,\n\tPORT67_FN1 = 1689,\n\tPORT68_FN1 = 1690,\n\tPORT69_FN1 = 1691,\n\tPORT70_FN1 = 1692,\n\tPORT71_FN1 = 1693,\n\tPORT72_FN1 = 1694,\n\tPORT73_FN1 = 1695,\n\tPORT74_FN1 = 1696,\n\tPORT75_FN1 = 1697,\n\tPORT76_FN1 = 1698,\n\tPORT77_FN1 = 1699,\n\tPORT78_FN1 = 1700,\n\tPORT79_FN1 = 1701,\n\tPORT80_FN1 = 1702,\n\tPORT81_FN1 = 1703,\n\tPORT82_FN1 = 1704,\n\tPORT83_FN1 = 1705,\n\tPORT84_FN1 = 1706,\n\tPORT85_FN1 = 1707,\n\tPORT86_FN1 = 1708,\n\tPORT87_FN1 = 1709,\n\tPORT88_FN1 = 1710,\n\tPORT89_FN1 = 1711,\n\tPORT90_FN1 = 1712,\n\tPORT91_FN1 = 1713,\n\tPORT92_FN1 = 1714,\n\tPORT93_FN1 = 1715,\n\tPORT94_FN1 = 1716,\n\tPORT95_FN1 = 1717,\n\tPORT96_FN1 = 1718,\n\tPORT97_FN1 = 1719,\n\tPORT98_FN1 = 1720,\n\tPORT99_FN1 = 1721,\n\tPORT100_FN1 = 1722,\n\tPORT101_FN1 = 1723,\n\tPORT102_FN1 = 1724,\n\tPORT103_FN1 = 1725,\n\tPORT104_FN1 = 1726,\n\tPORT105_FN1 = 1727,\n\tPORT106_FN1 = 1728,\n\tPORT107_FN1 = 1729,\n\tPORT108_FN1 = 1730,\n\tPORT109_FN1 = 1731,\n\tPORT110_FN1 = 1732,\n\tPORT111_FN1 = 1733,\n\tPORT112_FN1 = 1734,\n\tPORT113_FN1 = 1735,\n\tPORT114_FN1 = 1736,\n\tPORT115_FN1 = 1737,\n\tPORT116_FN1 = 1738,\n\tPORT117_FN1 = 1739,\n\tPORT118_FN1 = 1740,\n\tPORT128_FN1 = 1741,\n\tPORT129_FN1 = 1742,\n\tPORT130_FN1 = 1743,\n\tPORT131_FN1 = 1744,\n\tPORT132_FN1 = 1745,\n\tPORT133_FN1 = 1746,\n\tPORT134_FN1 = 1747,\n\tPORT135_FN1 = 1748,\n\tPORT136_FN1 = 1749,\n\tPORT137_FN1 = 1750,\n\tPORT138_FN1 = 1751,\n\tPORT139_FN1 = 1752,\n\tPORT140_FN1 = 1753,\n\tPORT141_FN1 = 1754,\n\tPORT142_FN1 = 1755,\n\tPORT143_FN1 = 1756,\n\tPORT144_FN1 = 1757,\n\tPORT145_FN1 = 1758,\n\tPORT146_FN1 = 1759,\n\tPORT147_FN1 = 1760,\n\tPORT148_FN1 = 1761,\n\tPORT149_FN1 = 1762,\n\tPORT150_FN1 = 1763,\n\tPORT151_FN1 = 1764,\n\tPORT152_FN1 = 1765,\n\tPORT153_FN1 = 1766,\n\tPORT154_FN1 = 1767,\n\tPORT155_FN1 = 1768,\n\tPORT156_FN1 = 1769,\n\tPORT157_FN1 = 1770,\n\tPORT158_FN1 = 1771,\n\tPORT159_FN1 = 1772,\n\tPORT160_FN1 = 1773,\n\tPORT161_FN1 = 1774,\n\tPORT162_FN1 = 1775,\n\tPORT163_FN1 = 1776,\n\tPORT164_FN1 = 1777,\n\tPORT192_FN1 = 1778,\n\tPORT193_FN1 = 1779,\n\tPORT194_FN1 = 1780,\n\tPORT195_FN1 = 1781,\n\tPORT196_FN1 = 1782,\n\tPORT197_FN1 = 1783,\n\tPORT198_FN1 = 1784,\n\tPORT199_FN1 = 1785,\n\tPORT200_FN1 = 1786,\n\tPORT201_FN1 = 1787,\n\tPORT202_FN1 = 1788,\n\tPORT203_FN1 = 1789,\n\tPORT204_FN1 = 1790,\n\tPORT205_FN1 = 1791,\n\tPORT206_FN1 = 1792,\n\tPORT207_FN1 = 1793,\n\tPORT208_FN1 = 1794,\n\tPORT209_FN1 = 1795,\n\tPORT210_FN1 = 1796,\n\tPORT211_FN1 = 1797,\n\tPORT212_FN1 = 1798,\n\tPORT213_FN1 = 1799,\n\tPORT214_FN1 = 1800,\n\tPORT215_FN1 = 1801,\n\tPORT216_FN1 = 1802,\n\tPORT217_FN1 = 1803,\n\tPORT218_FN1 = 1804,\n\tPORT219_FN1 = 1805,\n\tPORT220_FN1 = 1806,\n\tPORT221_FN1 = 1807,\n\tPORT222_FN1 = 1808,\n\tPORT223_FN1 = 1809,\n\tPORT224_FN1 = 1810,\n\tPORT225_FN1 = 1811,\n\tPORT226_FN1 = 1812,\n\tPORT227_FN1 = 1813,\n\tPORT228_FN1 = 1814,\n\tPORT229_FN1 = 1815,\n\tPORT230_FN1 = 1816,\n\tPORT231_FN1 = 1817,\n\tPORT232_FN1 = 1818,\n\tPORT233_FN1 = 1819,\n\tPORT234_FN1 = 1820,\n\tPORT235_FN1 = 1821,\n\tPORT236_FN1 = 1822,\n\tPORT237_FN1 = 1823,\n\tPORT238_FN1 = 1824,\n\tPORT239_FN1 = 1825,\n\tPORT240_FN1 = 1826,\n\tPORT241_FN1 = 1827,\n\tPORT242_FN1 = 1828,\n\tPORT243_FN1 = 1829,\n\tPORT244_FN1 = 1830,\n\tPORT245_FN1 = 1831,\n\tPORT246_FN1 = 1832,\n\tPORT247_FN1 = 1833,\n\tPORT248_FN1 = 1834,\n\tPORT249_FN1 = 1835,\n\tPORT250_FN1 = 1836,\n\tPORT251_FN1 = 1837,\n\tPORT252_FN1 = 1838,\n\tPORT253_FN1 = 1839,\n\tPORT254_FN1 = 1840,\n\tPORT255_FN1 = 1841,\n\tPORT256_FN1 = 1842,\n\tPORT257_FN1 = 1843,\n\tPORT258_FN1 = 1844,\n\tPORT259_FN1 = 1845,\n\tPORT260_FN1 = 1846,\n\tPORT261_FN1 = 1847,\n\tPORT262_FN1 = 1848,\n\tPORT263_FN1 = 1849,\n\tPORT264_FN1 = 1850,\n\tPORT265_FN1 = 1851,\n\tPORT266_FN1 = 1852,\n\tPORT267_FN1 = 1853,\n\tPORT268_FN1 = 1854,\n\tPORT269_FN1 = 1855,\n\tPORT270_FN1 = 1856,\n\tPORT271_FN1 = 1857,\n\tPORT272_FN1 = 1858,\n\tPORT273_FN1 = 1859,\n\tPORT274_FN1 = 1860,\n\tPORT275_FN1 = 1861,\n\tPORT276_FN1 = 1862,\n\tPORT277_FN1 = 1863,\n\tPORT278_FN1 = 1864,\n\tPORT279_FN1 = 1865,\n\tPORT280_FN1 = 1866,\n\tPORT281_FN1 = 1867,\n\tPORT282_FN1 = 1868,\n\tPORT288_FN1 = 1869,\n\tPORT289_FN1 = 1870,\n\tPORT290_FN1 = 1871,\n\tPORT291_FN1 = 1872,\n\tPORT292_FN1 = 1873,\n\tPORT293_FN1 = 1874,\n\tPORT294_FN1 = 1875,\n\tPORT295_FN1 = 1876,\n\tPORT296_FN1 = 1877,\n\tPORT297_FN1 = 1878,\n\tPORT298_FN1 = 1879,\n\tPORT299_FN1 = 1880,\n\tPORT300_FN1 = 1881,\n\tPORT301_FN1 = 1882,\n\tPORT302_FN1 = 1883,\n\tPORT303_FN1 = 1884,\n\tPORT304_FN1 = 1885,\n\tPORT305_FN1 = 1886,\n\tPORT306_FN1 = 1887,\n\tPORT307_FN1 = 1888,\n\tPORT308_FN1 = 1889,\n\tPORT309_FN1 = 1890,\n\tPORT0_FN2 = 1891,\n\tPORT1_FN2 = 1892,\n\tPORT2_FN2 = 1893,\n\tPORT3_FN2 = 1894,\n\tPORT4_FN2 = 1895,\n\tPORT5_FN2 = 1896,\n\tPORT6_FN2 = 1897,\n\tPORT7_FN2 = 1898,\n\tPORT8_FN2 = 1899,\n\tPORT9_FN2 = 1900,\n\tPORT10_FN2 = 1901,\n\tPORT11_FN2 = 1902,\n\tPORT12_FN2 = 1903,\n\tPORT13_FN2 = 1904,\n\tPORT14_FN2 = 1905,\n\tPORT15_FN2 = 1906,\n\tPORT16_FN2 = 1907,\n\tPORT17_FN2 = 1908,\n\tPORT18_FN2 = 1909,\n\tPORT19_FN2 = 1910,\n\tPORT20_FN2 = 1911,\n\tPORT21_FN2 = 1912,\n\tPORT22_FN2 = 1913,\n\tPORT23_FN2 = 1914,\n\tPORT24_FN2 = 1915,\n\tPORT25_FN2 = 1916,\n\tPORT26_FN2 = 1917,\n\tPORT27_FN2 = 1918,\n\tPORT28_FN2 = 1919,\n\tPORT29_FN2 = 1920,\n\tPORT30_FN2 = 1921,\n\tPORT31_FN2 = 1922,\n\tPORT32_FN2 = 1923,\n\tPORT33_FN2 = 1924,\n\tPORT34_FN2 = 1925,\n\tPORT35_FN2 = 1926,\n\tPORT36_FN2 = 1927,\n\tPORT37_FN2 = 1928,\n\tPORT38_FN2 = 1929,\n\tPORT39_FN2 = 1930,\n\tPORT40_FN2 = 1931,\n\tPORT41_FN2 = 1932,\n\tPORT42_FN2 = 1933,\n\tPORT43_FN2 = 1934,\n\tPORT44_FN2 = 1935,\n\tPORT45_FN2 = 1936,\n\tPORT46_FN2 = 1937,\n\tPORT47_FN2 = 1938,\n\tPORT48_FN2 = 1939,\n\tPORT49_FN2 = 1940,\n\tPORT50_FN2 = 1941,\n\tPORT51_FN2 = 1942,\n\tPORT52_FN2 = 1943,\n\tPORT53_FN2 = 1944,\n\tPORT54_FN2 = 1945,\n\tPORT55_FN2 = 1946,\n\tPORT56_FN2 = 1947,\n\tPORT57_FN2 = 1948,\n\tPORT58_FN2 = 1949,\n\tPORT59_FN2 = 1950,\n\tPORT60_FN2 = 1951,\n\tPORT61_FN2 = 1952,\n\tPORT62_FN2 = 1953,\n\tPORT63_FN2 = 1954,\n\tPORT64_FN2 = 1955,\n\tPORT65_FN2 = 1956,\n\tPORT66_FN2 = 1957,\n\tPORT67_FN2 = 1958,\n\tPORT68_FN2 = 1959,\n\tPORT69_FN2 = 1960,\n\tPORT70_FN2 = 1961,\n\tPORT71_FN2 = 1962,\n\tPORT72_FN2 = 1963,\n\tPORT73_FN2 = 1964,\n\tPORT74_FN2 = 1965,\n\tPORT75_FN2 = 1966,\n\tPORT76_FN2 = 1967,\n\tPORT77_FN2 = 1968,\n\tPORT78_FN2 = 1969,\n\tPORT79_FN2 = 1970,\n\tPORT80_FN2 = 1971,\n\tPORT81_FN2 = 1972,\n\tPORT82_FN2 = 1973,\n\tPORT83_FN2 = 1974,\n\tPORT84_FN2 = 1975,\n\tPORT85_FN2 = 1976,\n\tPORT86_FN2 = 1977,\n\tPORT87_FN2 = 1978,\n\tPORT88_FN2 = 1979,\n\tPORT89_FN2 = 1980,\n\tPORT90_FN2 = 1981,\n\tPORT91_FN2 = 1982,\n\tPORT92_FN2 = 1983,\n\tPORT93_FN2 = 1984,\n\tPORT94_FN2 = 1985,\n\tPORT95_FN2 = 1986,\n\tPORT96_FN2 = 1987,\n\tPORT97_FN2 = 1988,\n\tPORT98_FN2 = 1989,\n\tPORT99_FN2 = 1990,\n\tPORT100_FN2 = 1991,\n\tPORT101_FN2 = 1992,\n\tPORT102_FN2 = 1993,\n\tPORT103_FN2 = 1994,\n\tPORT104_FN2 = 1995,\n\tPORT105_FN2 = 1996,\n\tPORT106_FN2 = 1997,\n\tPORT107_FN2 = 1998,\n\tPORT108_FN2 = 1999,\n\tPORT109_FN2 = 2000,\n\tPORT110_FN2 = 2001,\n\tPORT111_FN2 = 2002,\n\tPORT112_FN2 = 2003,\n\tPORT113_FN2 = 2004,\n\tPORT114_FN2 = 2005,\n\tPORT115_FN2 = 2006,\n\tPORT116_FN2 = 2007,\n\tPORT117_FN2 = 2008,\n\tPORT118_FN2 = 2009,\n\tPORT128_FN2 = 2010,\n\tPORT129_FN2 = 2011,\n\tPORT130_FN2 = 2012,\n\tPORT131_FN2 = 2013,\n\tPORT132_FN2 = 2014,\n\tPORT133_FN2 = 2015,\n\tPORT134_FN2 = 2016,\n\tPORT135_FN2 = 2017,\n\tPORT136_FN2 = 2018,\n\tPORT137_FN2 = 2019,\n\tPORT138_FN2 = 2020,\n\tPORT139_FN2 = 2021,\n\tPORT140_FN2 = 2022,\n\tPORT141_FN2 = 2023,\n\tPORT142_FN2 = 2024,\n\tPORT143_FN2 = 2025,\n\tPORT144_FN2 = 2026,\n\tPORT145_FN2 = 2027,\n\tPORT146_FN2 = 2028,\n\tPORT147_FN2 = 2029,\n\tPORT148_FN2 = 2030,\n\tPORT149_FN2 = 2031,\n\tPORT150_FN2 = 2032,\n\tPORT151_FN2 = 2033,\n\tPORT152_FN2 = 2034,\n\tPORT153_FN2 = 2035,\n\tPORT154_FN2 = 2036,\n\tPORT155_FN2 = 2037,\n\tPORT156_FN2 = 2038,\n\tPORT157_FN2 = 2039,\n\tPORT158_FN2 = 2040,\n\tPORT159_FN2 = 2041,\n\tPORT160_FN2 = 2042,\n\tPORT161_FN2 = 2043,\n\tPORT162_FN2 = 2044,\n\tPORT163_FN2 = 2045,\n\tPORT164_FN2 = 2046,\n\tPORT192_FN2 = 2047,\n\tPORT193_FN2 = 2048,\n\tPORT194_FN2 = 2049,\n\tPORT195_FN2 = 2050,\n\tPORT196_FN2 = 2051,\n\tPORT197_FN2 = 2052,\n\tPORT198_FN2 = 2053,\n\tPORT199_FN2 = 2054,\n\tPORT200_FN2 = 2055,\n\tPORT201_FN2 = 2056,\n\tPORT202_FN2 = 2057,\n\tPORT203_FN2 = 2058,\n\tPORT204_FN2 = 2059,\n\tPORT205_FN2 = 2060,\n\tPORT206_FN2 = 2061,\n\tPORT207_FN2 = 2062,\n\tPORT208_FN2 = 2063,\n\tPORT209_FN2 = 2064,\n\tPORT210_FN2 = 2065,\n\tPORT211_FN2 = 2066,\n\tPORT212_FN2 = 2067,\n\tPORT213_FN2 = 2068,\n\tPORT214_FN2 = 2069,\n\tPORT215_FN2 = 2070,\n\tPORT216_FN2 = 2071,\n\tPORT217_FN2 = 2072,\n\tPORT218_FN2 = 2073,\n\tPORT219_FN2 = 2074,\n\tPORT220_FN2 = 2075,\n\tPORT221_FN2 = 2076,\n\tPORT222_FN2 = 2077,\n\tPORT223_FN2 = 2078,\n\tPORT224_FN2 = 2079,\n\tPORT225_FN2 = 2080,\n\tPORT226_FN2 = 2081,\n\tPORT227_FN2 = 2082,\n\tPORT228_FN2 = 2083,\n\tPORT229_FN2 = 2084,\n\tPORT230_FN2 = 2085,\n\tPORT231_FN2 = 2086,\n\tPORT232_FN2 = 2087,\n\tPORT233_FN2 = 2088,\n\tPORT234_FN2 = 2089,\n\tPORT235_FN2 = 2090,\n\tPORT236_FN2 = 2091,\n\tPORT237_FN2 = 2092,\n\tPORT238_FN2 = 2093,\n\tPORT239_FN2 = 2094,\n\tPORT240_FN2 = 2095,\n\tPORT241_FN2 = 2096,\n\tPORT242_FN2 = 2097,\n\tPORT243_FN2 = 2098,\n\tPORT244_FN2 = 2099,\n\tPORT245_FN2 = 2100,\n\tPORT246_FN2 = 2101,\n\tPORT247_FN2 = 2102,\n\tPORT248_FN2 = 2103,\n\tPORT249_FN2 = 2104,\n\tPORT250_FN2 = 2105,\n\tPORT251_FN2 = 2106,\n\tPORT252_FN2 = 2107,\n\tPORT253_FN2 = 2108,\n\tPORT254_FN2 = 2109,\n\tPORT255_FN2 = 2110,\n\tPORT256_FN2 = 2111,\n\tPORT257_FN2 = 2112,\n\tPORT258_FN2 = 2113,\n\tPORT259_FN2 = 2114,\n\tPORT260_FN2 = 2115,\n\tPORT261_FN2 = 2116,\n\tPORT262_FN2 = 2117,\n\tPORT263_FN2 = 2118,\n\tPORT264_FN2 = 2119,\n\tPORT265_FN2 = 2120,\n\tPORT266_FN2 = 2121,\n\tPORT267_FN2 = 2122,\n\tPORT268_FN2 = 2123,\n\tPORT269_FN2 = 2124,\n\tPORT270_FN2 = 2125,\n\tPORT271_FN2 = 2126,\n\tPORT272_FN2 = 2127,\n\tPORT273_FN2 = 2128,\n\tPORT274_FN2 = 2129,\n\tPORT275_FN2 = 2130,\n\tPORT276_FN2 = 2131,\n\tPORT277_FN2 = 2132,\n\tPORT278_FN2 = 2133,\n\tPORT279_FN2 = 2134,\n\tPORT280_FN2 = 2135,\n\tPORT281_FN2 = 2136,\n\tPORT282_FN2 = 2137,\n\tPORT288_FN2 = 2138,\n\tPORT289_FN2 = 2139,\n\tPORT290_FN2 = 2140,\n\tPORT291_FN2 = 2141,\n\tPORT292_FN2 = 2142,\n\tPORT293_FN2 = 2143,\n\tPORT294_FN2 = 2144,\n\tPORT295_FN2 = 2145,\n\tPORT296_FN2 = 2146,\n\tPORT297_FN2 = 2147,\n\tPORT298_FN2 = 2148,\n\tPORT299_FN2 = 2149,\n\tPORT300_FN2 = 2150,\n\tPORT301_FN2 = 2151,\n\tPORT302_FN2 = 2152,\n\tPORT303_FN2 = 2153,\n\tPORT304_FN2 = 2154,\n\tPORT305_FN2 = 2155,\n\tPORT306_FN2 = 2156,\n\tPORT307_FN2 = 2157,\n\tPORT308_FN2 = 2158,\n\tPORT309_FN2 = 2159,\n\tPORT0_FN3 = 2160,\n\tPORT1_FN3 = 2161,\n\tPORT2_FN3 = 2162,\n\tPORT3_FN3 = 2163,\n\tPORT4_FN3 = 2164,\n\tPORT5_FN3 = 2165,\n\tPORT6_FN3 = 2166,\n\tPORT7_FN3 = 2167,\n\tPORT8_FN3 = 2168,\n\tPORT9_FN3 = 2169,\n\tPORT10_FN3 = 2170,\n\tPORT11_FN3 = 2171,\n\tPORT12_FN3 = 2172,\n\tPORT13_FN3 = 2173,\n\tPORT14_FN3 = 2174,\n\tPORT15_FN3 = 2175,\n\tPORT16_FN3 = 2176,\n\tPORT17_FN3 = 2177,\n\tPORT18_FN3 = 2178,\n\tPORT19_FN3 = 2179,\n\tPORT20_FN3 = 2180,\n\tPORT21_FN3 = 2181,\n\tPORT22_FN3 = 2182,\n\tPORT23_FN3 = 2183,\n\tPORT24_FN3 = 2184,\n\tPORT25_FN3 = 2185,\n\tPORT26_FN3 = 2186,\n\tPORT27_FN3 = 2187,\n\tPORT28_FN3 = 2188,\n\tPORT29_FN3 = 2189,\n\tPORT30_FN3 = 2190,\n\tPORT31_FN3 = 2191,\n\tPORT32_FN3 = 2192,\n\tPORT33_FN3 = 2193,\n\tPORT34_FN3 = 2194,\n\tPORT35_FN3 = 2195,\n\tPORT36_FN3 = 2196,\n\tPORT37_FN3 = 2197,\n\tPORT38_FN3 = 2198,\n\tPORT39_FN3 = 2199,\n\tPORT40_FN3 = 2200,\n\tPORT41_FN3 = 2201,\n\tPORT42_FN3 = 2202,\n\tPORT43_FN3 = 2203,\n\tPORT44_FN3 = 2204,\n\tPORT45_FN3 = 2205,\n\tPORT46_FN3 = 2206,\n\tPORT47_FN3 = 2207,\n\tPORT48_FN3 = 2208,\n\tPORT49_FN3 = 2209,\n\tPORT50_FN3 = 2210,\n\tPORT51_FN3 = 2211,\n\tPORT52_FN3 = 2212,\n\tPORT53_FN3 = 2213,\n\tPORT54_FN3 = 2214,\n\tPORT55_FN3 = 2215,\n\tPORT56_FN3 = 2216,\n\tPORT57_FN3 = 2217,\n\tPORT58_FN3 = 2218,\n\tPORT59_FN3 = 2219,\n\tPORT60_FN3 = 2220,\n\tPORT61_FN3 = 2221,\n\tPORT62_FN3 = 2222,\n\tPORT63_FN3 = 2223,\n\tPORT64_FN3 = 2224,\n\tPORT65_FN3 = 2225,\n\tPORT66_FN3 = 2226,\n\tPORT67_FN3 = 2227,\n\tPORT68_FN3 = 2228,\n\tPORT69_FN3 = 2229,\n\tPORT70_FN3 = 2230,\n\tPORT71_FN3 = 2231,\n\tPORT72_FN3 = 2232,\n\tPORT73_FN3 = 2233,\n\tPORT74_FN3 = 2234,\n\tPORT75_FN3 = 2235,\n\tPORT76_FN3 = 2236,\n\tPORT77_FN3 = 2237,\n\tPORT78_FN3 = 2238,\n\tPORT79_FN3 = 2239,\n\tPORT80_FN3 = 2240,\n\tPORT81_FN3 = 2241,\n\tPORT82_FN3 = 2242,\n\tPORT83_FN3 = 2243,\n\tPORT84_FN3 = 2244,\n\tPORT85_FN3 = 2245,\n\tPORT86_FN3 = 2246,\n\tPORT87_FN3 = 2247,\n\tPORT88_FN3 = 2248,\n\tPORT89_FN3 = 2249,\n\tPORT90_FN3 = 2250,\n\tPORT91_FN3 = 2251,\n\tPORT92_FN3 = 2252,\n\tPORT93_FN3 = 2253,\n\tPORT94_FN3 = 2254,\n\tPORT95_FN3 = 2255,\n\tPORT96_FN3 = 2256,\n\tPORT97_FN3 = 2257,\n\tPORT98_FN3 = 2258,\n\tPORT99_FN3 = 2259,\n\tPORT100_FN3 = 2260,\n\tPORT101_FN3 = 2261,\n\tPORT102_FN3 = 2262,\n\tPORT103_FN3 = 2263,\n\tPORT104_FN3 = 2264,\n\tPORT105_FN3 = 2265,\n\tPORT106_FN3 = 2266,\n\tPORT107_FN3 = 2267,\n\tPORT108_FN3 = 2268,\n\tPORT109_FN3 = 2269,\n\tPORT110_FN3 = 2270,\n\tPORT111_FN3 = 2271,\n\tPORT112_FN3 = 2272,\n\tPORT113_FN3 = 2273,\n\tPORT114_FN3 = 2274,\n\tPORT115_FN3 = 2275,\n\tPORT116_FN3 = 2276,\n\tPORT117_FN3 = 2277,\n\tPORT118_FN3 = 2278,\n\tPORT128_FN3 = 2279,\n\tPORT129_FN3 = 2280,\n\tPORT130_FN3 = 2281,\n\tPORT131_FN3 = 2282,\n\tPORT132_FN3 = 2283,\n\tPORT133_FN3 = 2284,\n\tPORT134_FN3 = 2285,\n\tPORT135_FN3 = 2286,\n\tPORT136_FN3 = 2287,\n\tPORT137_FN3 = 2288,\n\tPORT138_FN3 = 2289,\n\tPORT139_FN3 = 2290,\n\tPORT140_FN3 = 2291,\n\tPORT141_FN3 = 2292,\n\tPORT142_FN3 = 2293,\n\tPORT143_FN3 = 2294,\n\tPORT144_FN3 = 2295,\n\tPORT145_FN3 = 2296,\n\tPORT146_FN3 = 2297,\n\tPORT147_FN3 = 2298,\n\tPORT148_FN3 = 2299,\n\tPORT149_FN3 = 2300,\n\tPORT150_FN3 = 2301,\n\tPORT151_FN3 = 2302,\n\tPORT152_FN3 = 2303,\n\tPORT153_FN3 = 2304,\n\tPORT154_FN3 = 2305,\n\tPORT155_FN3 = 2306,\n\tPORT156_FN3 = 2307,\n\tPORT157_FN3 = 2308,\n\tPORT158_FN3 = 2309,\n\tPORT159_FN3 = 2310,\n\tPORT160_FN3 = 2311,\n\tPORT161_FN3 = 2312,\n\tPORT162_FN3 = 2313,\n\tPORT163_FN3 = 2314,\n\tPORT164_FN3 = 2315,\n\tPORT192_FN3 = 2316,\n\tPORT193_FN3 = 2317,\n\tPORT194_FN3 = 2318,\n\tPORT195_FN3 = 2319,\n\tPORT196_FN3 = 2320,\n\tPORT197_FN3 = 2321,\n\tPORT198_FN3 = 2322,\n\tPORT199_FN3 = 2323,\n\tPORT200_FN3 = 2324,\n\tPORT201_FN3 = 2325,\n\tPORT202_FN3 = 2326,\n\tPORT203_FN3 = 2327,\n\tPORT204_FN3 = 2328,\n\tPORT205_FN3 = 2329,\n\tPORT206_FN3 = 2330,\n\tPORT207_FN3 = 2331,\n\tPORT208_FN3 = 2332,\n\tPORT209_FN3 = 2333,\n\tPORT210_FN3 = 2334,\n\tPORT211_FN3 = 2335,\n\tPORT212_FN3 = 2336,\n\tPORT213_FN3 = 2337,\n\tPORT214_FN3 = 2338,\n\tPORT215_FN3 = 2339,\n\tPORT216_FN3 = 2340,\n\tPORT217_FN3 = 2341,\n\tPORT218_FN3 = 2342,\n\tPORT219_FN3 = 2343,\n\tPORT220_FN3 = 2344,\n\tPORT221_FN3 = 2345,\n\tPORT222_FN3 = 2346,\n\tPORT223_FN3 = 2347,\n\tPORT224_FN3 = 2348,\n\tPORT225_FN3 = 2349,\n\tPORT226_FN3 = 2350,\n\tPORT227_FN3 = 2351,\n\tPORT228_FN3 = 2352,\n\tPORT229_FN3 = 2353,\n\tPORT230_FN3 = 2354,\n\tPORT231_FN3 = 2355,\n\tPORT232_FN3 = 2356,\n\tPORT233_FN3 = 2357,\n\tPORT234_FN3 = 2358,\n\tPORT235_FN3 = 2359,\n\tPORT236_FN3 = 2360,\n\tPORT237_FN3 = 2361,\n\tPORT238_FN3 = 2362,\n\tPORT239_FN3 = 2363,\n\tPORT240_FN3 = 2364,\n\tPORT241_FN3 = 2365,\n\tPORT242_FN3 = 2366,\n\tPORT243_FN3 = 2367,\n\tPORT244_FN3 = 2368,\n\tPORT245_FN3 = 2369,\n\tPORT246_FN3 = 2370,\n\tPORT247_FN3 = 2371,\n\tPORT248_FN3 = 2372,\n\tPORT249_FN3 = 2373,\n\tPORT250_FN3 = 2374,\n\tPORT251_FN3 = 2375,\n\tPORT252_FN3 = 2376,\n\tPORT253_FN3 = 2377,\n\tPORT254_FN3 = 2378,\n\tPORT255_FN3 = 2379,\n\tPORT256_FN3 = 2380,\n\tPORT257_FN3 = 2381,\n\tPORT258_FN3 = 2382,\n\tPORT259_FN3 = 2383,\n\tPORT260_FN3 = 2384,\n\tPORT261_FN3 = 2385,\n\tPORT262_FN3 = 2386,\n\tPORT263_FN3 = 2387,\n\tPORT264_FN3 = 2388,\n\tPORT265_FN3 = 2389,\n\tPORT266_FN3 = 2390,\n\tPORT267_FN3 = 2391,\n\tPORT268_FN3 = 2392,\n\tPORT269_FN3 = 2393,\n\tPORT270_FN3 = 2394,\n\tPORT271_FN3 = 2395,\n\tPORT272_FN3 = 2396,\n\tPORT273_FN3 = 2397,\n\tPORT274_FN3 = 2398,\n\tPORT275_FN3 = 2399,\n\tPORT276_FN3 = 2400,\n\tPORT277_FN3 = 2401,\n\tPORT278_FN3 = 2402,\n\tPORT279_FN3 = 2403,\n\tPORT280_FN3 = 2404,\n\tPORT281_FN3 = 2405,\n\tPORT282_FN3 = 2406,\n\tPORT288_FN3 = 2407,\n\tPORT289_FN3 = 2408,\n\tPORT290_FN3 = 2409,\n\tPORT291_FN3 = 2410,\n\tPORT292_FN3 = 2411,\n\tPORT293_FN3 = 2412,\n\tPORT294_FN3 = 2413,\n\tPORT295_FN3 = 2414,\n\tPORT296_FN3 = 2415,\n\tPORT297_FN3 = 2416,\n\tPORT298_FN3 = 2417,\n\tPORT299_FN3 = 2418,\n\tPORT300_FN3 = 2419,\n\tPORT301_FN3 = 2420,\n\tPORT302_FN3 = 2421,\n\tPORT303_FN3 = 2422,\n\tPORT304_FN3 = 2423,\n\tPORT305_FN3 = 2424,\n\tPORT306_FN3 = 2425,\n\tPORT307_FN3 = 2426,\n\tPORT308_FN3 = 2427,\n\tPORT309_FN3 = 2428,\n\tPORT0_FN4 = 2429,\n\tPORT1_FN4 = 2430,\n\tPORT2_FN4 = 2431,\n\tPORT3_FN4 = 2432,\n\tPORT4_FN4 = 2433,\n\tPORT5_FN4 = 2434,\n\tPORT6_FN4 = 2435,\n\tPORT7_FN4 = 2436,\n\tPORT8_FN4 = 2437,\n\tPORT9_FN4 = 2438,\n\tPORT10_FN4 = 2439,\n\tPORT11_FN4 = 2440,\n\tPORT12_FN4 = 2441,\n\tPORT13_FN4 = 2442,\n\tPORT14_FN4 = 2443,\n\tPORT15_FN4 = 2444,\n\tPORT16_FN4 = 2445,\n\tPORT17_FN4 = 2446,\n\tPORT18_FN4 = 2447,\n\tPORT19_FN4 = 2448,\n\tPORT20_FN4 = 2449,\n\tPORT21_FN4 = 2450,\n\tPORT22_FN4 = 2451,\n\tPORT23_FN4 = 2452,\n\tPORT24_FN4 = 2453,\n\tPORT25_FN4 = 2454,\n\tPORT26_FN4 = 2455,\n\tPORT27_FN4 = 2456,\n\tPORT28_FN4 = 2457,\n\tPORT29_FN4 = 2458,\n\tPORT30_FN4 = 2459,\n\tPORT31_FN4 = 2460,\n\tPORT32_FN4 = 2461,\n\tPORT33_FN4 = 2462,\n\tPORT34_FN4 = 2463,\n\tPORT35_FN4 = 2464,\n\tPORT36_FN4 = 2465,\n\tPORT37_FN4 = 2466,\n\tPORT38_FN4 = 2467,\n\tPORT39_FN4 = 2468,\n\tPORT40_FN4 = 2469,\n\tPORT41_FN4 = 2470,\n\tPORT42_FN4 = 2471,\n\tPORT43_FN4 = 2472,\n\tPORT44_FN4 = 2473,\n\tPORT45_FN4 = 2474,\n\tPORT46_FN4 = 2475,\n\tPORT47_FN4 = 2476,\n\tPORT48_FN4 = 2477,\n\tPORT49_FN4 = 2478,\n\tPORT50_FN4 = 2479,\n\tPORT51_FN4 = 2480,\n\tPORT52_FN4 = 2481,\n\tPORT53_FN4 = 2482,\n\tPORT54_FN4 = 2483,\n\tPORT55_FN4 = 2484,\n\tPORT56_FN4 = 2485,\n\tPORT57_FN4 = 2486,\n\tPORT58_FN4 = 2487,\n\tPORT59_FN4 = 2488,\n\tPORT60_FN4 = 2489,\n\tPORT61_FN4 = 2490,\n\tPORT62_FN4 = 2491,\n\tPORT63_FN4 = 2492,\n\tPORT64_FN4 = 2493,\n\tPORT65_FN4 = 2494,\n\tPORT66_FN4 = 2495,\n\tPORT67_FN4 = 2496,\n\tPORT68_FN4 = 2497,\n\tPORT69_FN4 = 2498,\n\tPORT70_FN4 = 2499,\n\tPORT71_FN4 = 2500,\n\tPORT72_FN4 = 2501,\n\tPORT73_FN4 = 2502,\n\tPORT74_FN4 = 2503,\n\tPORT75_FN4 = 2504,\n\tPORT76_FN4 = 2505,\n\tPORT77_FN4 = 2506,\n\tPORT78_FN4 = 2507,\n\tPORT79_FN4 = 2508,\n\tPORT80_FN4 = 2509,\n\tPORT81_FN4 = 2510,\n\tPORT82_FN4 = 2511,\n\tPORT83_FN4 = 2512,\n\tPORT84_FN4 = 2513,\n\tPORT85_FN4 = 2514,\n\tPORT86_FN4 = 2515,\n\tPORT87_FN4 = 2516,\n\tPORT88_FN4 = 2517,\n\tPORT89_FN4 = 2518,\n\tPORT90_FN4 = 2519,\n\tPORT91_FN4 = 2520,\n\tPORT92_FN4 = 2521,\n\tPORT93_FN4 = 2522,\n\tPORT94_FN4 = 2523,\n\tPORT95_FN4 = 2524,\n\tPORT96_FN4 = 2525,\n\tPORT97_FN4 = 2526,\n\tPORT98_FN4 = 2527,\n\tPORT99_FN4 = 2528,\n\tPORT100_FN4 = 2529,\n\tPORT101_FN4 = 2530,\n\tPORT102_FN4 = 2531,\n\tPORT103_FN4 = 2532,\n\tPORT104_FN4 = 2533,\n\tPORT105_FN4 = 2534,\n\tPORT106_FN4 = 2535,\n\tPORT107_FN4 = 2536,\n\tPORT108_FN4 = 2537,\n\tPORT109_FN4 = 2538,\n\tPORT110_FN4 = 2539,\n\tPORT111_FN4 = 2540,\n\tPORT112_FN4 = 2541,\n\tPORT113_FN4 = 2542,\n\tPORT114_FN4 = 2543,\n\tPORT115_FN4 = 2544,\n\tPORT116_FN4 = 2545,\n\tPORT117_FN4 = 2546,\n\tPORT118_FN4 = 2547,\n\tPORT128_FN4 = 2548,\n\tPORT129_FN4 = 2549,\n\tPORT130_FN4 = 2550,\n\tPORT131_FN4 = 2551,\n\tPORT132_FN4 = 2552,\n\tPORT133_FN4 = 2553,\n\tPORT134_FN4 = 2554,\n\tPORT135_FN4 = 2555,\n\tPORT136_FN4 = 2556,\n\tPORT137_FN4 = 2557,\n\tPORT138_FN4 = 2558,\n\tPORT139_FN4 = 2559,\n\tPORT140_FN4 = 2560,\n\tPORT141_FN4 = 2561,\n\tPORT142_FN4 = 2562,\n\tPORT143_FN4 = 2563,\n\tPORT144_FN4 = 2564,\n\tPORT145_FN4 = 2565,\n\tPORT146_FN4 = 2566,\n\tPORT147_FN4 = 2567,\n\tPORT148_FN4 = 2568,\n\tPORT149_FN4 = 2569,\n\tPORT150_FN4 = 2570,\n\tPORT151_FN4 = 2571,\n\tPORT152_FN4 = 2572,\n\tPORT153_FN4 = 2573,\n\tPORT154_FN4 = 2574,\n\tPORT155_FN4 = 2575,\n\tPORT156_FN4 = 2576,\n\tPORT157_FN4 = 2577,\n\tPORT158_FN4 = 2578,\n\tPORT159_FN4 = 2579,\n\tPORT160_FN4 = 2580,\n\tPORT161_FN4 = 2581,\n\tPORT162_FN4 = 2582,\n\tPORT163_FN4 = 2583,\n\tPORT164_FN4 = 2584,\n\tPORT192_FN4 = 2585,\n\tPORT193_FN4 = 2586,\n\tPORT194_FN4 = 2587,\n\tPORT195_FN4 = 2588,\n\tPORT196_FN4 = 2589,\n\tPORT197_FN4 = 2590,\n\tPORT198_FN4 = 2591,\n\tPORT199_FN4 = 2592,\n\tPORT200_FN4 = 2593,\n\tPORT201_FN4 = 2594,\n\tPORT202_FN4 = 2595,\n\tPORT203_FN4 = 2596,\n\tPORT204_FN4 = 2597,\n\tPORT205_FN4 = 2598,\n\tPORT206_FN4 = 2599,\n\tPORT207_FN4 = 2600,\n\tPORT208_FN4 = 2601,\n\tPORT209_FN4 = 2602,\n\tPORT210_FN4 = 2603,\n\tPORT211_FN4 = 2604,\n\tPORT212_FN4 = 2605,\n\tPORT213_FN4 = 2606,\n\tPORT214_FN4 = 2607,\n\tPORT215_FN4 = 2608,\n\tPORT216_FN4 = 2609,\n\tPORT217_FN4 = 2610,\n\tPORT218_FN4 = 2611,\n\tPORT219_FN4 = 2612,\n\tPORT220_FN4 = 2613,\n\tPORT221_FN4 = 2614,\n\tPORT222_FN4 = 2615,\n\tPORT223_FN4 = 2616,\n\tPORT224_FN4 = 2617,\n\tPORT225_FN4 = 2618,\n\tPORT226_FN4 = 2619,\n\tPORT227_FN4 = 2620,\n\tPORT228_FN4 = 2621,\n\tPORT229_FN4 = 2622,\n\tPORT230_FN4 = 2623,\n\tPORT231_FN4 = 2624,\n\tPORT232_FN4 = 2625,\n\tPORT233_FN4 = 2626,\n\tPORT234_FN4 = 2627,\n\tPORT235_FN4 = 2628,\n\tPORT236_FN4 = 2629,\n\tPORT237_FN4 = 2630,\n\tPORT238_FN4 = 2631,\n\tPORT239_FN4 = 2632,\n\tPORT240_FN4 = 2633,\n\tPORT241_FN4 = 2634,\n\tPORT242_FN4 = 2635,\n\tPORT243_FN4 = 2636,\n\tPORT244_FN4 = 2637,\n\tPORT245_FN4 = 2638,\n\tPORT246_FN4 = 2639,\n\tPORT247_FN4 = 2640,\n\tPORT248_FN4 = 2641,\n\tPORT249_FN4 = 2642,\n\tPORT250_FN4 = 2643,\n\tPORT251_FN4 = 2644,\n\tPORT252_FN4 = 2645,\n\tPORT253_FN4 = 2646,\n\tPORT254_FN4 = 2647,\n\tPORT255_FN4 = 2648,\n\tPORT256_FN4 = 2649,\n\tPORT257_FN4 = 2650,\n\tPORT258_FN4 = 2651,\n\tPORT259_FN4 = 2652,\n\tPORT260_FN4 = 2653,\n\tPORT261_FN4 = 2654,\n\tPORT262_FN4 = 2655,\n\tPORT263_FN4 = 2656,\n\tPORT264_FN4 = 2657,\n\tPORT265_FN4 = 2658,\n\tPORT266_FN4 = 2659,\n\tPORT267_FN4 = 2660,\n\tPORT268_FN4 = 2661,\n\tPORT269_FN4 = 2662,\n\tPORT270_FN4 = 2663,\n\tPORT271_FN4 = 2664,\n\tPORT272_FN4 = 2665,\n\tPORT273_FN4 = 2666,\n\tPORT274_FN4 = 2667,\n\tPORT275_FN4 = 2668,\n\tPORT276_FN4 = 2669,\n\tPORT277_FN4 = 2670,\n\tPORT278_FN4 = 2671,\n\tPORT279_FN4 = 2672,\n\tPORT280_FN4 = 2673,\n\tPORT281_FN4 = 2674,\n\tPORT282_FN4 = 2675,\n\tPORT288_FN4 = 2676,\n\tPORT289_FN4 = 2677,\n\tPORT290_FN4 = 2678,\n\tPORT291_FN4 = 2679,\n\tPORT292_FN4 = 2680,\n\tPORT293_FN4 = 2681,\n\tPORT294_FN4 = 2682,\n\tPORT295_FN4 = 2683,\n\tPORT296_FN4 = 2684,\n\tPORT297_FN4 = 2685,\n\tPORT298_FN4 = 2686,\n\tPORT299_FN4 = 2687,\n\tPORT300_FN4 = 2688,\n\tPORT301_FN4 = 2689,\n\tPORT302_FN4 = 2690,\n\tPORT303_FN4 = 2691,\n\tPORT304_FN4 = 2692,\n\tPORT305_FN4 = 2693,\n\tPORT306_FN4 = 2694,\n\tPORT307_FN4 = 2695,\n\tPORT308_FN4 = 2696,\n\tPORT309_FN4 = 2697,\n\tPORT0_FN5 = 2698,\n\tPORT1_FN5 = 2699,\n\tPORT2_FN5 = 2700,\n\tPORT3_FN5 = 2701,\n\tPORT4_FN5 = 2702,\n\tPORT5_FN5 = 2703,\n\tPORT6_FN5 = 2704,\n\tPORT7_FN5 = 2705,\n\tPORT8_FN5 = 2706,\n\tPORT9_FN5 = 2707,\n\tPORT10_FN5 = 2708,\n\tPORT11_FN5 = 2709,\n\tPORT12_FN5 = 2710,\n\tPORT13_FN5 = 2711,\n\tPORT14_FN5 = 2712,\n\tPORT15_FN5 = 2713,\n\tPORT16_FN5 = 2714,\n\tPORT17_FN5 = 2715,\n\tPORT18_FN5 = 2716,\n\tPORT19_FN5 = 2717,\n\tPORT20_FN5 = 2718,\n\tPORT21_FN5 = 2719,\n\tPORT22_FN5 = 2720,\n\tPORT23_FN5 = 2721,\n\tPORT24_FN5 = 2722,\n\tPORT25_FN5 = 2723,\n\tPORT26_FN5 = 2724,\n\tPORT27_FN5 = 2725,\n\tPORT28_FN5 = 2726,\n\tPORT29_FN5 = 2727,\n\tPORT30_FN5 = 2728,\n\tPORT31_FN5 = 2729,\n\tPORT32_FN5 = 2730,\n\tPORT33_FN5 = 2731,\n\tPORT34_FN5 = 2732,\n\tPORT35_FN5 = 2733,\n\tPORT36_FN5 = 2734,\n\tPORT37_FN5 = 2735,\n\tPORT38_FN5 = 2736,\n\tPORT39_FN5 = 2737,\n\tPORT40_FN5 = 2738,\n\tPORT41_FN5 = 2739,\n\tPORT42_FN5 = 2740,\n\tPORT43_FN5 = 2741,\n\tPORT44_FN5 = 2742,\n\tPORT45_FN5 = 2743,\n\tPORT46_FN5 = 2744,\n\tPORT47_FN5 = 2745,\n\tPORT48_FN5 = 2746,\n\tPORT49_FN5 = 2747,\n\tPORT50_FN5 = 2748,\n\tPORT51_FN5 = 2749,\n\tPORT52_FN5 = 2750,\n\tPORT53_FN5 = 2751,\n\tPORT54_FN5 = 2752,\n\tPORT55_FN5 = 2753,\n\tPORT56_FN5 = 2754,\n\tPORT57_FN5 = 2755,\n\tPORT58_FN5 = 2756,\n\tPORT59_FN5 = 2757,\n\tPORT60_FN5 = 2758,\n\tPORT61_FN5 = 2759,\n\tPORT62_FN5 = 2760,\n\tPORT63_FN5 = 2761,\n\tPORT64_FN5 = 2762,\n\tPORT65_FN5 = 2763,\n\tPORT66_FN5 = 2764,\n\tPORT67_FN5 = 2765,\n\tPORT68_FN5 = 2766,\n\tPORT69_FN5 = 2767,\n\tPORT70_FN5 = 2768,\n\tPORT71_FN5 = 2769,\n\tPORT72_FN5 = 2770,\n\tPORT73_FN5 = 2771,\n\tPORT74_FN5 = 2772,\n\tPORT75_FN5 = 2773,\n\tPORT76_FN5 = 2774,\n\tPORT77_FN5 = 2775,\n\tPORT78_FN5 = 2776,\n\tPORT79_FN5 = 2777,\n\tPORT80_FN5 = 2778,\n\tPORT81_FN5 = 2779,\n\tPORT82_FN5 = 2780,\n\tPORT83_FN5 = 2781,\n\tPORT84_FN5 = 2782,\n\tPORT85_FN5 = 2783,\n\tPORT86_FN5 = 2784,\n\tPORT87_FN5 = 2785,\n\tPORT88_FN5 = 2786,\n\tPORT89_FN5 = 2787,\n\tPORT90_FN5 = 2788,\n\tPORT91_FN5 = 2789,\n\tPORT92_FN5 = 2790,\n\tPORT93_FN5 = 2791,\n\tPORT94_FN5 = 2792,\n\tPORT95_FN5 = 2793,\n\tPORT96_FN5 = 2794,\n\tPORT97_FN5 = 2795,\n\tPORT98_FN5 = 2796,\n\tPORT99_FN5 = 2797,\n\tPORT100_FN5 = 2798,\n\tPORT101_FN5 = 2799,\n\tPORT102_FN5 = 2800,\n\tPORT103_FN5 = 2801,\n\tPORT104_FN5 = 2802,\n\tPORT105_FN5 = 2803,\n\tPORT106_FN5 = 2804,\n\tPORT107_FN5 = 2805,\n\tPORT108_FN5 = 2806,\n\tPORT109_FN5 = 2807,\n\tPORT110_FN5 = 2808,\n\tPORT111_FN5 = 2809,\n\tPORT112_FN5 = 2810,\n\tPORT113_FN5 = 2811,\n\tPORT114_FN5 = 2812,\n\tPORT115_FN5 = 2813,\n\tPORT116_FN5 = 2814,\n\tPORT117_FN5 = 2815,\n\tPORT118_FN5 = 2816,\n\tPORT128_FN5 = 2817,\n\tPORT129_FN5 = 2818,\n\tPORT130_FN5 = 2819,\n\tPORT131_FN5 = 2820,\n\tPORT132_FN5 = 2821,\n\tPORT133_FN5 = 2822,\n\tPORT134_FN5 = 2823,\n\tPORT135_FN5 = 2824,\n\tPORT136_FN5 = 2825,\n\tPORT137_FN5 = 2826,\n\tPORT138_FN5 = 2827,\n\tPORT139_FN5 = 2828,\n\tPORT140_FN5 = 2829,\n\tPORT141_FN5 = 2830,\n\tPORT142_FN5 = 2831,\n\tPORT143_FN5 = 2832,\n\tPORT144_FN5 = 2833,\n\tPORT145_FN5 = 2834,\n\tPORT146_FN5 = 2835,\n\tPORT147_FN5 = 2836,\n\tPORT148_FN5 = 2837,\n\tPORT149_FN5 = 2838,\n\tPORT150_FN5 = 2839,\n\tPORT151_FN5 = 2840,\n\tPORT152_FN5 = 2841,\n\tPORT153_FN5 = 2842,\n\tPORT154_FN5 = 2843,\n\tPORT155_FN5 = 2844,\n\tPORT156_FN5 = 2845,\n\tPORT157_FN5 = 2846,\n\tPORT158_FN5 = 2847,\n\tPORT159_FN5 = 2848,\n\tPORT160_FN5 = 2849,\n\tPORT161_FN5 = 2850,\n\tPORT162_FN5 = 2851,\n\tPORT163_FN5 = 2852,\n\tPORT164_FN5 = 2853,\n\tPORT192_FN5 = 2854,\n\tPORT193_FN5 = 2855,\n\tPORT194_FN5 = 2856,\n\tPORT195_FN5 = 2857,\n\tPORT196_FN5 = 2858,\n\tPORT197_FN5 = 2859,\n\tPORT198_FN5 = 2860,\n\tPORT199_FN5 = 2861,\n\tPORT200_FN5 = 2862,\n\tPORT201_FN5 = 2863,\n\tPORT202_FN5 = 2864,\n\tPORT203_FN5 = 2865,\n\tPORT204_FN5 = 2866,\n\tPORT205_FN5 = 2867,\n\tPORT206_FN5 = 2868,\n\tPORT207_FN5 = 2869,\n\tPORT208_FN5 = 2870,\n\tPORT209_FN5 = 2871,\n\tPORT210_FN5 = 2872,\n\tPORT211_FN5 = 2873,\n\tPORT212_FN5 = 2874,\n\tPORT213_FN5 = 2875,\n\tPORT214_FN5 = 2876,\n\tPORT215_FN5 = 2877,\n\tPORT216_FN5 = 2878,\n\tPORT217_FN5 = 2879,\n\tPORT218_FN5 = 2880,\n\tPORT219_FN5 = 2881,\n\tPORT220_FN5 = 2882,\n\tPORT221_FN5 = 2883,\n\tPORT222_FN5 = 2884,\n\tPORT223_FN5 = 2885,\n\tPORT224_FN5 = 2886,\n\tPORT225_FN5 = 2887,\n\tPORT226_FN5 = 2888,\n\tPORT227_FN5 = 2889,\n\tPORT228_FN5 = 2890,\n\tPORT229_FN5 = 2891,\n\tPORT230_FN5 = 2892,\n\tPORT231_FN5 = 2893,\n\tPORT232_FN5 = 2894,\n\tPORT233_FN5 = 2895,\n\tPORT234_FN5 = 2896,\n\tPORT235_FN5 = 2897,\n\tPORT236_FN5 = 2898,\n\tPORT237_FN5 = 2899,\n\tPORT238_FN5 = 2900,\n\tPORT239_FN5 = 2901,\n\tPORT240_FN5 = 2902,\n\tPORT241_FN5 = 2903,\n\tPORT242_FN5 = 2904,\n\tPORT243_FN5 = 2905,\n\tPORT244_FN5 = 2906,\n\tPORT245_FN5 = 2907,\n\tPORT246_FN5 = 2908,\n\tPORT247_FN5 = 2909,\n\tPORT248_FN5 = 2910,\n\tPORT249_FN5 = 2911,\n\tPORT250_FN5 = 2912,\n\tPORT251_FN5 = 2913,\n\tPORT252_FN5 = 2914,\n\tPORT253_FN5 = 2915,\n\tPORT254_FN5 = 2916,\n\tPORT255_FN5 = 2917,\n\tPORT256_FN5 = 2918,\n\tPORT257_FN5 = 2919,\n\tPORT258_FN5 = 2920,\n\tPORT259_FN5 = 2921,\n\tPORT260_FN5 = 2922,\n\tPORT261_FN5 = 2923,\n\tPORT262_FN5 = 2924,\n\tPORT263_FN5 = 2925,\n\tPORT264_FN5 = 2926,\n\tPORT265_FN5 = 2927,\n\tPORT266_FN5 = 2928,\n\tPORT267_FN5 = 2929,\n\tPORT268_FN5 = 2930,\n\tPORT269_FN5 = 2931,\n\tPORT270_FN5 = 2932,\n\tPORT271_FN5 = 2933,\n\tPORT272_FN5 = 2934,\n\tPORT273_FN5 = 2935,\n\tPORT274_FN5 = 2936,\n\tPORT275_FN5 = 2937,\n\tPORT276_FN5 = 2938,\n\tPORT277_FN5 = 2939,\n\tPORT278_FN5 = 2940,\n\tPORT279_FN5 = 2941,\n\tPORT280_FN5 = 2942,\n\tPORT281_FN5 = 2943,\n\tPORT282_FN5 = 2944,\n\tPORT288_FN5 = 2945,\n\tPORT289_FN5 = 2946,\n\tPORT290_FN5 = 2947,\n\tPORT291_FN5 = 2948,\n\tPORT292_FN5 = 2949,\n\tPORT293_FN5 = 2950,\n\tPORT294_FN5 = 2951,\n\tPORT295_FN5 = 2952,\n\tPORT296_FN5 = 2953,\n\tPORT297_FN5 = 2954,\n\tPORT298_FN5 = 2955,\n\tPORT299_FN5 = 2956,\n\tPORT300_FN5 = 2957,\n\tPORT301_FN5 = 2958,\n\tPORT302_FN5 = 2959,\n\tPORT303_FN5 = 2960,\n\tPORT304_FN5 = 2961,\n\tPORT305_FN5 = 2962,\n\tPORT306_FN5 = 2963,\n\tPORT307_FN5 = 2964,\n\tPORT308_FN5 = 2965,\n\tPORT309_FN5 = 2966,\n\tPORT0_FN6 = 2967,\n\tPORT1_FN6 = 2968,\n\tPORT2_FN6 = 2969,\n\tPORT3_FN6 = 2970,\n\tPORT4_FN6 = 2971,\n\tPORT5_FN6 = 2972,\n\tPORT6_FN6 = 2973,\n\tPORT7_FN6 = 2974,\n\tPORT8_FN6 = 2975,\n\tPORT9_FN6 = 2976,\n\tPORT10_FN6 = 2977,\n\tPORT11_FN6 = 2978,\n\tPORT12_FN6 = 2979,\n\tPORT13_FN6 = 2980,\n\tPORT14_FN6 = 2981,\n\tPORT15_FN6 = 2982,\n\tPORT16_FN6 = 2983,\n\tPORT17_FN6 = 2984,\n\tPORT18_FN6 = 2985,\n\tPORT19_FN6 = 2986,\n\tPORT20_FN6 = 2987,\n\tPORT21_FN6 = 2988,\n\tPORT22_FN6 = 2989,\n\tPORT23_FN6 = 2990,\n\tPORT24_FN6 = 2991,\n\tPORT25_FN6 = 2992,\n\tPORT26_FN6 = 2993,\n\tPORT27_FN6 = 2994,\n\tPORT28_FN6 = 2995,\n\tPORT29_FN6 = 2996,\n\tPORT30_FN6 = 2997,\n\tPORT31_FN6 = 2998,\n\tPORT32_FN6 = 2999,\n\tPORT33_FN6 = 3000,\n\tPORT34_FN6 = 3001,\n\tPORT35_FN6 = 3002,\n\tPORT36_FN6 = 3003,\n\tPORT37_FN6 = 3004,\n\tPORT38_FN6 = 3005,\n\tPORT39_FN6 = 3006,\n\tPORT40_FN6 = 3007,\n\tPORT41_FN6 = 3008,\n\tPORT42_FN6 = 3009,\n\tPORT43_FN6 = 3010,\n\tPORT44_FN6 = 3011,\n\tPORT45_FN6 = 3012,\n\tPORT46_FN6 = 3013,\n\tPORT47_FN6 = 3014,\n\tPORT48_FN6 = 3015,\n\tPORT49_FN6 = 3016,\n\tPORT50_FN6 = 3017,\n\tPORT51_FN6 = 3018,\n\tPORT52_FN6 = 3019,\n\tPORT53_FN6 = 3020,\n\tPORT54_FN6 = 3021,\n\tPORT55_FN6 = 3022,\n\tPORT56_FN6 = 3023,\n\tPORT57_FN6 = 3024,\n\tPORT58_FN6 = 3025,\n\tPORT59_FN6 = 3026,\n\tPORT60_FN6 = 3027,\n\tPORT61_FN6 = 3028,\n\tPORT62_FN6 = 3029,\n\tPORT63_FN6 = 3030,\n\tPORT64_FN6 = 3031,\n\tPORT65_FN6 = 3032,\n\tPORT66_FN6 = 3033,\n\tPORT67_FN6 = 3034,\n\tPORT68_FN6 = 3035,\n\tPORT69_FN6 = 3036,\n\tPORT70_FN6 = 3037,\n\tPORT71_FN6 = 3038,\n\tPORT72_FN6 = 3039,\n\tPORT73_FN6 = 3040,\n\tPORT74_FN6 = 3041,\n\tPORT75_FN6 = 3042,\n\tPORT76_FN6 = 3043,\n\tPORT77_FN6 = 3044,\n\tPORT78_FN6 = 3045,\n\tPORT79_FN6 = 3046,\n\tPORT80_FN6 = 3047,\n\tPORT81_FN6 = 3048,\n\tPORT82_FN6 = 3049,\n\tPORT83_FN6 = 3050,\n\tPORT84_FN6 = 3051,\n\tPORT85_FN6 = 3052,\n\tPORT86_FN6 = 3053,\n\tPORT87_FN6 = 3054,\n\tPORT88_FN6 = 3055,\n\tPORT89_FN6 = 3056,\n\tPORT90_FN6 = 3057,\n\tPORT91_FN6 = 3058,\n\tPORT92_FN6 = 3059,\n\tPORT93_FN6 = 3060,\n\tPORT94_FN6 = 3061,\n\tPORT95_FN6 = 3062,\n\tPORT96_FN6 = 3063,\n\tPORT97_FN6 = 3064,\n\tPORT98_FN6 = 3065,\n\tPORT99_FN6 = 3066,\n\tPORT100_FN6 = 3067,\n\tPORT101_FN6 = 3068,\n\tPORT102_FN6 = 3069,\n\tPORT103_FN6 = 3070,\n\tPORT104_FN6 = 3071,\n\tPORT105_FN6 = 3072,\n\tPORT106_FN6 = 3073,\n\tPORT107_FN6 = 3074,\n\tPORT108_FN6 = 3075,\n\tPORT109_FN6 = 3076,\n\tPORT110_FN6 = 3077,\n\tPORT111_FN6 = 3078,\n\tPORT112_FN6 = 3079,\n\tPORT113_FN6 = 3080,\n\tPORT114_FN6 = 3081,\n\tPORT115_FN6 = 3082,\n\tPORT116_FN6 = 3083,\n\tPORT117_FN6 = 3084,\n\tPORT118_FN6 = 3085,\n\tPORT128_FN6 = 3086,\n\tPORT129_FN6 = 3087,\n\tPORT130_FN6 = 3088,\n\tPORT131_FN6 = 3089,\n\tPORT132_FN6 = 3090,\n\tPORT133_FN6 = 3091,\n\tPORT134_FN6 = 3092,\n\tPORT135_FN6 = 3093,\n\tPORT136_FN6 = 3094,\n\tPORT137_FN6 = 3095,\n\tPORT138_FN6 = 3096,\n\tPORT139_FN6 = 3097,\n\tPORT140_FN6 = 3098,\n\tPORT141_FN6 = 3099,\n\tPORT142_FN6 = 3100,\n\tPORT143_FN6 = 3101,\n\tPORT144_FN6 = 3102,\n\tPORT145_FN6 = 3103,\n\tPORT146_FN6 = 3104,\n\tPORT147_FN6 = 3105,\n\tPORT148_FN6 = 3106,\n\tPORT149_FN6 = 3107,\n\tPORT150_FN6 = 3108,\n\tPORT151_FN6 = 3109,\n\tPORT152_FN6 = 3110,\n\tPORT153_FN6 = 3111,\n\tPORT154_FN6 = 3112,\n\tPORT155_FN6 = 3113,\n\tPORT156_FN6 = 3114,\n\tPORT157_FN6 = 3115,\n\tPORT158_FN6 = 3116,\n\tPORT159_FN6 = 3117,\n\tPORT160_FN6 = 3118,\n\tPORT161_FN6 = 3119,\n\tPORT162_FN6 = 3120,\n\tPORT163_FN6 = 3121,\n\tPORT164_FN6 = 3122,\n\tPORT192_FN6 = 3123,\n\tPORT193_FN6 = 3124,\n\tPORT194_FN6 = 3125,\n\tPORT195_FN6 = 3126,\n\tPORT196_FN6 = 3127,\n\tPORT197_FN6 = 3128,\n\tPORT198_FN6 = 3129,\n\tPORT199_FN6 = 3130,\n\tPORT200_FN6 = 3131,\n\tPORT201_FN6 = 3132,\n\tPORT202_FN6 = 3133,\n\tPORT203_FN6 = 3134,\n\tPORT204_FN6 = 3135,\n\tPORT205_FN6 = 3136,\n\tPORT206_FN6 = 3137,\n\tPORT207_FN6 = 3138,\n\tPORT208_FN6 = 3139,\n\tPORT209_FN6 = 3140,\n\tPORT210_FN6 = 3141,\n\tPORT211_FN6 = 3142,\n\tPORT212_FN6 = 3143,\n\tPORT213_FN6 = 3144,\n\tPORT214_FN6 = 3145,\n\tPORT215_FN6 = 3146,\n\tPORT216_FN6 = 3147,\n\tPORT217_FN6 = 3148,\n\tPORT218_FN6 = 3149,\n\tPORT219_FN6 = 3150,\n\tPORT220_FN6 = 3151,\n\tPORT221_FN6 = 3152,\n\tPORT222_FN6 = 3153,\n\tPORT223_FN6 = 3154,\n\tPORT224_FN6 = 3155,\n\tPORT225_FN6 = 3156,\n\tPORT226_FN6 = 3157,\n\tPORT227_FN6 = 3158,\n\tPORT228_FN6 = 3159,\n\tPORT229_FN6 = 3160,\n\tPORT230_FN6 = 3161,\n\tPORT231_FN6 = 3162,\n\tPORT232_FN6 = 3163,\n\tPORT233_FN6 = 3164,\n\tPORT234_FN6 = 3165,\n\tPORT235_FN6 = 3166,\n\tPORT236_FN6 = 3167,\n\tPORT237_FN6 = 3168,\n\tPORT238_FN6 = 3169,\n\tPORT239_FN6 = 3170,\n\tPORT240_FN6 = 3171,\n\tPORT241_FN6 = 3172,\n\tPORT242_FN6 = 3173,\n\tPORT243_FN6 = 3174,\n\tPORT244_FN6 = 3175,\n\tPORT245_FN6 = 3176,\n\tPORT246_FN6 = 3177,\n\tPORT247_FN6 = 3178,\n\tPORT248_FN6 = 3179,\n\tPORT249_FN6 = 3180,\n\tPORT250_FN6 = 3181,\n\tPORT251_FN6 = 3182,\n\tPORT252_FN6 = 3183,\n\tPORT253_FN6 = 3184,\n\tPORT254_FN6 = 3185,\n\tPORT255_FN6 = 3186,\n\tPORT256_FN6 = 3187,\n\tPORT257_FN6 = 3188,\n\tPORT258_FN6 = 3189,\n\tPORT259_FN6 = 3190,\n\tPORT260_FN6 = 3191,\n\tPORT261_FN6 = 3192,\n\tPORT262_FN6 = 3193,\n\tPORT263_FN6 = 3194,\n\tPORT264_FN6 = 3195,\n\tPORT265_FN6 = 3196,\n\tPORT266_FN6 = 3197,\n\tPORT267_FN6 = 3198,\n\tPORT268_FN6 = 3199,\n\tPORT269_FN6 = 3200,\n\tPORT270_FN6 = 3201,\n\tPORT271_FN6 = 3202,\n\tPORT272_FN6 = 3203,\n\tPORT273_FN6 = 3204,\n\tPORT274_FN6 = 3205,\n\tPORT275_FN6 = 3206,\n\tPORT276_FN6 = 3207,\n\tPORT277_FN6 = 3208,\n\tPORT278_FN6 = 3209,\n\tPORT279_FN6 = 3210,\n\tPORT280_FN6 = 3211,\n\tPORT281_FN6 = 3212,\n\tPORT282_FN6 = 3213,\n\tPORT288_FN6 = 3214,\n\tPORT289_FN6 = 3215,\n\tPORT290_FN6 = 3216,\n\tPORT291_FN6 = 3217,\n\tPORT292_FN6 = 3218,\n\tPORT293_FN6 = 3219,\n\tPORT294_FN6 = 3220,\n\tPORT295_FN6 = 3221,\n\tPORT296_FN6 = 3222,\n\tPORT297_FN6 = 3223,\n\tPORT298_FN6 = 3224,\n\tPORT299_FN6 = 3225,\n\tPORT300_FN6 = 3226,\n\tPORT301_FN6 = 3227,\n\tPORT302_FN6 = 3228,\n\tPORT303_FN6 = 3229,\n\tPORT304_FN6 = 3230,\n\tPORT305_FN6 = 3231,\n\tPORT306_FN6 = 3232,\n\tPORT307_FN6 = 3233,\n\tPORT308_FN6 = 3234,\n\tPORT309_FN6 = 3235,\n\tPORT0_FN7 = 3236,\n\tPORT1_FN7 = 3237,\n\tPORT2_FN7 = 3238,\n\tPORT3_FN7 = 3239,\n\tPORT4_FN7 = 3240,\n\tPORT5_FN7 = 3241,\n\tPORT6_FN7 = 3242,\n\tPORT7_FN7 = 3243,\n\tPORT8_FN7 = 3244,\n\tPORT9_FN7 = 3245,\n\tPORT10_FN7 = 3246,\n\tPORT11_FN7 = 3247,\n\tPORT12_FN7 = 3248,\n\tPORT13_FN7 = 3249,\n\tPORT14_FN7 = 3250,\n\tPORT15_FN7 = 3251,\n\tPORT16_FN7 = 3252,\n\tPORT17_FN7 = 3253,\n\tPORT18_FN7 = 3254,\n\tPORT19_FN7 = 3255,\n\tPORT20_FN7 = 3256,\n\tPORT21_FN7 = 3257,\n\tPORT22_FN7 = 3258,\n\tPORT23_FN7 = 3259,\n\tPORT24_FN7 = 3260,\n\tPORT25_FN7 = 3261,\n\tPORT26_FN7 = 3262,\n\tPORT27_FN7 = 3263,\n\tPORT28_FN7 = 3264,\n\tPORT29_FN7 = 3265,\n\tPORT30_FN7 = 3266,\n\tPORT31_FN7 = 3267,\n\tPORT32_FN7 = 3268,\n\tPORT33_FN7 = 3269,\n\tPORT34_FN7 = 3270,\n\tPORT35_FN7 = 3271,\n\tPORT36_FN7 = 3272,\n\tPORT37_FN7 = 3273,\n\tPORT38_FN7 = 3274,\n\tPORT39_FN7 = 3275,\n\tPORT40_FN7 = 3276,\n\tPORT41_FN7 = 3277,\n\tPORT42_FN7 = 3278,\n\tPORT43_FN7 = 3279,\n\tPORT44_FN7 = 3280,\n\tPORT45_FN7 = 3281,\n\tPORT46_FN7 = 3282,\n\tPORT47_FN7 = 3283,\n\tPORT48_FN7 = 3284,\n\tPORT49_FN7 = 3285,\n\tPORT50_FN7 = 3286,\n\tPORT51_FN7 = 3287,\n\tPORT52_FN7 = 3288,\n\tPORT53_FN7 = 3289,\n\tPORT54_FN7 = 3290,\n\tPORT55_FN7 = 3291,\n\tPORT56_FN7 = 3292,\n\tPORT57_FN7 = 3293,\n\tPORT58_FN7 = 3294,\n\tPORT59_FN7 = 3295,\n\tPORT60_FN7 = 3296,\n\tPORT61_FN7 = 3297,\n\tPORT62_FN7 = 3298,\n\tPORT63_FN7 = 3299,\n\tPORT64_FN7 = 3300,\n\tPORT65_FN7 = 3301,\n\tPORT66_FN7 = 3302,\n\tPORT67_FN7 = 3303,\n\tPORT68_FN7 = 3304,\n\tPORT69_FN7 = 3305,\n\tPORT70_FN7 = 3306,\n\tPORT71_FN7 = 3307,\n\tPORT72_FN7 = 3308,\n\tPORT73_FN7 = 3309,\n\tPORT74_FN7 = 3310,\n\tPORT75_FN7 = 3311,\n\tPORT76_FN7 = 3312,\n\tPORT77_FN7 = 3313,\n\tPORT78_FN7 = 3314,\n\tPORT79_FN7 = 3315,\n\tPORT80_FN7 = 3316,\n\tPORT81_FN7 = 3317,\n\tPORT82_FN7 = 3318,\n\tPORT83_FN7 = 3319,\n\tPORT84_FN7 = 3320,\n\tPORT85_FN7 = 3321,\n\tPORT86_FN7 = 3322,\n\tPORT87_FN7 = 3323,\n\tPORT88_FN7 = 3324,\n\tPORT89_FN7 = 3325,\n\tPORT90_FN7 = 3326,\n\tPORT91_FN7 = 3327,\n\tPORT92_FN7 = 3328,\n\tPORT93_FN7 = 3329,\n\tPORT94_FN7 = 3330,\n\tPORT95_FN7 = 3331,\n\tPORT96_FN7 = 3332,\n\tPORT97_FN7 = 3333,\n\tPORT98_FN7 = 3334,\n\tPORT99_FN7 = 3335,\n\tPORT100_FN7 = 3336,\n\tPORT101_FN7 = 3337,\n\tPORT102_FN7 = 3338,\n\tPORT103_FN7 = 3339,\n\tPORT104_FN7 = 3340,\n\tPORT105_FN7 = 3341,\n\tPORT106_FN7 = 3342,\n\tPORT107_FN7 = 3343,\n\tPORT108_FN7 = 3344,\n\tPORT109_FN7 = 3345,\n\tPORT110_FN7 = 3346,\n\tPORT111_FN7 = 3347,\n\tPORT112_FN7 = 3348,\n\tPORT113_FN7 = 3349,\n\tPORT114_FN7 = 3350,\n\tPORT115_FN7 = 3351,\n\tPORT116_FN7 = 3352,\n\tPORT117_FN7 = 3353,\n\tPORT118_FN7 = 3354,\n\tPORT128_FN7 = 3355,\n\tPORT129_FN7 = 3356,\n\tPORT130_FN7 = 3357,\n\tPORT131_FN7 = 3358,\n\tPORT132_FN7 = 3359,\n\tPORT133_FN7 = 3360,\n\tPORT134_FN7 = 3361,\n\tPORT135_FN7 = 3362,\n\tPORT136_FN7 = 3363,\n\tPORT137_FN7 = 3364,\n\tPORT138_FN7 = 3365,\n\tPORT139_FN7 = 3366,\n\tPORT140_FN7 = 3367,\n\tPORT141_FN7 = 3368,\n\tPORT142_FN7 = 3369,\n\tPORT143_FN7 = 3370,\n\tPORT144_FN7 = 3371,\n\tPORT145_FN7 = 3372,\n\tPORT146_FN7 = 3373,\n\tPORT147_FN7 = 3374,\n\tPORT148_FN7 = 3375,\n\tPORT149_FN7 = 3376,\n\tPORT150_FN7 = 3377,\n\tPORT151_FN7 = 3378,\n\tPORT152_FN7 = 3379,\n\tPORT153_FN7 = 3380,\n\tPORT154_FN7 = 3381,\n\tPORT155_FN7 = 3382,\n\tPORT156_FN7 = 3383,\n\tPORT157_FN7 = 3384,\n\tPORT158_FN7 = 3385,\n\tPORT159_FN7 = 3386,\n\tPORT160_FN7 = 3387,\n\tPORT161_FN7 = 3388,\n\tPORT162_FN7 = 3389,\n\tPORT163_FN7 = 3390,\n\tPORT164_FN7 = 3391,\n\tPORT192_FN7 = 3392,\n\tPORT193_FN7 = 3393,\n\tPORT194_FN7 = 3394,\n\tPORT195_FN7 = 3395,\n\tPORT196_FN7 = 3396,\n\tPORT197_FN7 = 3397,\n\tPORT198_FN7 = 3398,\n\tPORT199_FN7 = 3399,\n\tPORT200_FN7 = 3400,\n\tPORT201_FN7 = 3401,\n\tPORT202_FN7 = 3402,\n\tPORT203_FN7 = 3403,\n\tPORT204_FN7 = 3404,\n\tPORT205_FN7 = 3405,\n\tPORT206_FN7 = 3406,\n\tPORT207_FN7 = 3407,\n\tPORT208_FN7 = 3408,\n\tPORT209_FN7 = 3409,\n\tPORT210_FN7 = 3410,\n\tPORT211_FN7 = 3411,\n\tPORT212_FN7 = 3412,\n\tPORT213_FN7 = 3413,\n\tPORT214_FN7 = 3414,\n\tPORT215_FN7 = 3415,\n\tPORT216_FN7 = 3416,\n\tPORT217_FN7 = 3417,\n\tPORT218_FN7 = 3418,\n\tPORT219_FN7 = 3419,\n\tPORT220_FN7 = 3420,\n\tPORT221_FN7 = 3421,\n\tPORT222_FN7 = 3422,\n\tPORT223_FN7 = 3423,\n\tPORT224_FN7 = 3424,\n\tPORT225_FN7 = 3425,\n\tPORT226_FN7 = 3426,\n\tPORT227_FN7 = 3427,\n\tPORT228_FN7 = 3428,\n\tPORT229_FN7 = 3429,\n\tPORT230_FN7 = 3430,\n\tPORT231_FN7 = 3431,\n\tPORT232_FN7 = 3432,\n\tPORT233_FN7 = 3433,\n\tPORT234_FN7 = 3434,\n\tPORT235_FN7 = 3435,\n\tPORT236_FN7 = 3436,\n\tPORT237_FN7 = 3437,\n\tPORT238_FN7 = 3438,\n\tPORT239_FN7 = 3439,\n\tPORT240_FN7 = 3440,\n\tPORT241_FN7 = 3441,\n\tPORT242_FN7 = 3442,\n\tPORT243_FN7 = 3443,\n\tPORT244_FN7 = 3444,\n\tPORT245_FN7 = 3445,\n\tPORT246_FN7 = 3446,\n\tPORT247_FN7 = 3447,\n\tPORT248_FN7 = 3448,\n\tPORT249_FN7 = 3449,\n\tPORT250_FN7 = 3450,\n\tPORT251_FN7 = 3451,\n\tPORT252_FN7 = 3452,\n\tPORT253_FN7 = 3453,\n\tPORT254_FN7 = 3454,\n\tPORT255_FN7 = 3455,\n\tPORT256_FN7 = 3456,\n\tPORT257_FN7 = 3457,\n\tPORT258_FN7 = 3458,\n\tPORT259_FN7 = 3459,\n\tPORT260_FN7 = 3460,\n\tPORT261_FN7 = 3461,\n\tPORT262_FN7 = 3462,\n\tPORT263_FN7 = 3463,\n\tPORT264_FN7 = 3464,\n\tPORT265_FN7 = 3465,\n\tPORT266_FN7 = 3466,\n\tPORT267_FN7 = 3467,\n\tPORT268_FN7 = 3468,\n\tPORT269_FN7 = 3469,\n\tPORT270_FN7 = 3470,\n\tPORT271_FN7 = 3471,\n\tPORT272_FN7 = 3472,\n\tPORT273_FN7 = 3473,\n\tPORT274_FN7 = 3474,\n\tPORT275_FN7 = 3475,\n\tPORT276_FN7 = 3476,\n\tPORT277_FN7 = 3477,\n\tPORT278_FN7 = 3478,\n\tPORT279_FN7 = 3479,\n\tPORT280_FN7 = 3480,\n\tPORT281_FN7 = 3481,\n\tPORT282_FN7 = 3482,\n\tPORT288_FN7 = 3483,\n\tPORT289_FN7 = 3484,\n\tPORT290_FN7 = 3485,\n\tPORT291_FN7 = 3486,\n\tPORT292_FN7 = 3487,\n\tPORT293_FN7 = 3488,\n\tPORT294_FN7 = 3489,\n\tPORT295_FN7 = 3490,\n\tPORT296_FN7 = 3491,\n\tPORT297_FN7 = 3492,\n\tPORT298_FN7 = 3493,\n\tPORT299_FN7 = 3494,\n\tPORT300_FN7 = 3495,\n\tPORT301_FN7 = 3496,\n\tPORT302_FN7 = 3497,\n\tPORT303_FN7 = 3498,\n\tPORT304_FN7 = 3499,\n\tPORT305_FN7 = 3500,\n\tPORT306_FN7 = 3501,\n\tPORT307_FN7 = 3502,\n\tPORT308_FN7 = 3503,\n\tPORT309_FN7 = 3504,\n\tMSEL2CR_MSEL19_0 = 3505,\n\tMSEL2CR_MSEL19_1 = 3506,\n\tMSEL2CR_MSEL18_0 = 3507,\n\tMSEL2CR_MSEL18_1 = 3508,\n\tMSEL2CR_MSEL17_0 = 3509,\n\tMSEL2CR_MSEL17_1 = 3510,\n\tMSEL2CR_MSEL16_0 = 3511,\n\tMSEL2CR_MSEL16_1 = 3512,\n\tMSEL2CR_MSEL14_0 = 3513,\n\tMSEL2CR_MSEL14_1 = 3514,\n\tMSEL2CR_MSEL13_0 = 3515,\n\tMSEL2CR_MSEL13_1 = 3516,\n\tMSEL2CR_MSEL12_0 = 3517,\n\tMSEL2CR_MSEL12_1 = 3518,\n\tMSEL2CR_MSEL11_0 = 3519,\n\tMSEL2CR_MSEL11_1 = 3520,\n\tMSEL2CR_MSEL10_0 = 3521,\n\tMSEL2CR_MSEL10_1 = 3522,\n\tMSEL2CR_MSEL9_0 = 3523,\n\tMSEL2CR_MSEL9_1 = 3524,\n\tMSEL2CR_MSEL8_0 = 3525,\n\tMSEL2CR_MSEL8_1 = 3526,\n\tMSEL2CR_MSEL7_0 = 3527,\n\tMSEL2CR_MSEL7_1 = 3528,\n\tMSEL2CR_MSEL6_0 = 3529,\n\tMSEL2CR_MSEL6_1 = 3530,\n\tMSEL2CR_MSEL4_0 = 3531,\n\tMSEL2CR_MSEL4_1 = 3532,\n\tMSEL2CR_MSEL5_0 = 3533,\n\tMSEL2CR_MSEL5_1 = 3534,\n\tMSEL2CR_MSEL3_0 = 3535,\n\tMSEL2CR_MSEL3_1 = 3536,\n\tMSEL2CR_MSEL2_0 = 3537,\n\tMSEL2CR_MSEL2_1 = 3538,\n\tMSEL2CR_MSEL1_0 = 3539,\n\tMSEL2CR_MSEL1_1 = 3540,\n\tMSEL2CR_MSEL0_0 = 3541,\n\tMSEL2CR_MSEL0_1 = 3542,\n\tMSEL3CR_MSEL28_0 = 3543,\n\tMSEL3CR_MSEL28_1 = 3544,\n\tMSEL3CR_MSEL15_0 = 3545,\n\tMSEL3CR_MSEL15_1 = 3546,\n\tMSEL3CR_MSEL11_0 = 3547,\n\tMSEL3CR_MSEL11_1 = 3548,\n\tMSEL3CR_MSEL9_0 = 3549,\n\tMSEL3CR_MSEL9_1 = 3550,\n\tMSEL3CR_MSEL6_0 = 3551,\n\tMSEL3CR_MSEL6_1 = 3552,\n\tMSEL3CR_MSEL2_0 = 3553,\n\tMSEL3CR_MSEL2_1 = 3554,\n\tMSEL4CR_MSEL29_0 = 3555,\n\tMSEL4CR_MSEL29_1 = 3556,\n\tMSEL4CR_MSEL27_0 = 3557,\n\tMSEL4CR_MSEL27_1 = 3558,\n\tMSEL4CR_MSEL26_0 = 3559,\n\tMSEL4CR_MSEL26_1 = 3560,\n\tMSEL4CR_MSEL22_0 = 3561,\n\tMSEL4CR_MSEL22_1 = 3562,\n\tMSEL4CR_MSEL21_0 = 3563,\n\tMSEL4CR_MSEL21_1 = 3564,\n\tMSEL4CR_MSEL20_0 = 3565,\n\tMSEL4CR_MSEL20_1 = 3566,\n\tMSEL4CR_MSEL19_0 = 3567,\n\tMSEL4CR_MSEL19_1 = 3568,\n\tMSEL4CR_MSEL15_0 = 3569,\n\tMSEL4CR_MSEL15_1 = 3570,\n\tMSEL4CR_MSEL13_0 = 3571,\n\tMSEL4CR_MSEL13_1 = 3572,\n\tMSEL4CR_MSEL12_0 = 3573,\n\tMSEL4CR_MSEL12_1 = 3574,\n\tMSEL4CR_MSEL11_0 = 3575,\n\tMSEL4CR_MSEL11_1 = 3576,\n\tMSEL4CR_MSEL10_0 = 3577,\n\tMSEL4CR_MSEL10_1 = 3578,\n\tMSEL4CR_MSEL9_0 = 3579,\n\tMSEL4CR_MSEL9_1 = 3580,\n\tMSEL4CR_MSEL8_0 = 3581,\n\tMSEL4CR_MSEL8_1 = 3582,\n\tMSEL4CR_MSEL7_0 = 3583,\n\tMSEL4CR_MSEL7_1 = 3584,\n\tMSEL4CR_MSEL4_0 = 3585,\n\tMSEL4CR_MSEL4_1 = 3586,\n\tMSEL4CR_MSEL1_0 = 3587,\n\tMSEL4CR_MSEL1_1 = 3588,\n\tPINMUX_FUNCTION_END___2 = 3589,\n\tPINMUX_MARK_BEGIN___2 = 3590,\n\tVBUS_0_MARK = 3591,\n\tGPI0_MARK = 3592,\n\tGPI1_MARK = 3593,\n\tGPI2_MARK = 3594,\n\tGPI3_MARK = 3595,\n\tGPI4_MARK = 3596,\n\tGPI5_MARK = 3597,\n\tGPI6_MARK = 3598,\n\tGPI7_MARK = 3599,\n\tSCIFA7_RXD_MARK = 3600,\n\tSCIFA7_CTS__MARK = 3601,\n\tGPO7_MARK = 3602,\n\tMFG0_OUT2_MARK = 3603,\n\tGPO6_MARK = 3604,\n\tMFG1_OUT2_MARK = 3605,\n\tGPO5_MARK = 3606,\n\tSCIFA0_SCK_MARK = 3607,\n\tFSICOSLDT3_MARK = 3608,\n\tPORT16_VIO_CKOR_MARK = 3609,\n\tSCIFA0_TXD_MARK___2 = 3610,\n\tSCIFA7_TXD_MARK = 3611,\n\tSCIFA7_RTS__MARK = 3612,\n\tPORT19_VIO_CKO2_MARK = 3613,\n\tGPO0_MARK = 3614,\n\tGPO1_MARK = 3615,\n\tGPO2_MARK = 3616,\n\tSTATUS0_MARK = 3617,\n\tGPO3_MARK = 3618,\n\tSTATUS1_MARK = 3619,\n\tGPO4_MARK = 3620,\n\tSTATUS2_MARK = 3621,\n\tVINT_MARK = 3622,\n\tTCKON_MARK = 3623,\n\tXDVFS1_MARK = 3624,\n\tPORT27_I2C_SCL2_MARK = 3625,\n\tPORT27_I2C_SCL3_MARK = 3626,\n\tMFG0_OUT1_MARK = 3627,\n\tPORT27_IROUT_MARK = 3628,\n\tXDVFS2_MARK = 3629,\n\tPORT28_I2C_SDA2_MARK = 3630,\n\tPORT28_I2C_SDA3_MARK = 3631,\n\tPORT28_TPU1TO1_MARK = 3632,\n\tSIM_RST_MARK = 3633,\n\tPORT29_TPU1TO1_MARK = 3634,\n\tSIM_CLK_MARK = 3635,\n\tPORT30_VIO_CKOR_MARK = 3636,\n\tSIM_D_MARK = 3637,\n\tPORT31_IROUT_MARK = 3638,\n\tSCIFA4_TXD_MARK___2 = 3639,\n\tSCIFA4_RXD_MARK___2 = 3640,\n\tXWUP_MARK = 3641,\n\tSCIFA4_RTS__MARK = 3642,\n\tSCIFA4_CTS__MARK = 3643,\n\tFSIBOBT_MARK = 3644,\n\tFSIBIBT_MARK = 3645,\n\tFSIBOLR_MARK = 3646,\n\tFSIBILR_MARK = 3647,\n\tFSIBOSLD_MARK = 3648,\n\tFSIBISLD_MARK = 3649,\n\tVACK_MARK = 3650,\n\tXTAL1L_MARK = 3651,\n\tSCIFA0_RTS__MARK = 3652,\n\tFSICOSLDT2_MARK = 3653,\n\tSCIFA0_RXD_MARK___2 = 3654,\n\tSCIFA0_CTS__MARK = 3655,\n\tFSICOSLDT1_MARK = 3656,\n\tFSICOBT_MARK = 3657,\n\tFSICIBT_MARK = 3658,\n\tFSIDOBT_MARK = 3659,\n\tFSIDIBT_MARK = 3660,\n\tFSICOLR_MARK = 3661,\n\tFSICILR_MARK = 3662,\n\tFSIDOLR_MARK = 3663,\n\tFSIDILR_MARK = 3664,\n\tFSICOSLD_MARK = 3665,\n\tPORT47_FSICSPDIF_MARK = 3666,\n\tFSICISLD_MARK = 3667,\n\tFSIDISLD_MARK = 3668,\n\tFSIACK_MARK = 3669,\n\tPORT49_IRDA_OUT_MARK = 3670,\n\tPORT49_IROUT_MARK = 3671,\n\tFSIAOMC_MARK = 3672,\n\tFSIAOLR_MARK = 3673,\n\tBBIF2_TSYNC2_MARK = 3674,\n\tTPU2TO2_MARK = 3675,\n\tFSIAILR_MARK = 3676,\n\tFSIAOBT_MARK = 3677,\n\tBBIF2_TSCK2_MARK = 3678,\n\tTPU2TO3_MARK = 3679,\n\tFSIAIBT_MARK = 3680,\n\tFSIAOSLD_MARK = 3681,\n\tBBIF2_TXD2_MARK = 3682,\n\tFSIASPDIF_MARK = 3683,\n\tPORT53_IRDA_IN_MARK = 3684,\n\tTPU3TO3_MARK = 3685,\n\tFSIBSPDIF_MARK = 3686,\n\tPORT53_FSICSPDIF_MARK = 3687,\n\tFSIBCK_MARK = 3688,\n\tPORT54_IRDA_FIRSEL_MARK = 3689,\n\tTPU3TO2_MARK = 3690,\n\tFSIBOMC_MARK = 3691,\n\tFSICCK_MARK = 3692,\n\tFSICOMC_MARK = 3693,\n\tFSIAISLD_MARK = 3694,\n\tTPU0TO0_MARK = 3695,\n\tA0_MARK___2 = 3696,\n\tBS__MARK = 3697,\n\tA12_MARK___2 = 3698,\n\tPORT58_KEYOUT7_MARK = 3699,\n\tTPU4TO2_MARK = 3700,\n\tA13_MARK___2 = 3701,\n\tPORT59_KEYOUT6_MARK = 3702,\n\tTPU0TO1_MARK = 3703,\n\tA14_MARK___2 = 3704,\n\tKEYOUT5_MARK = 3705,\n\tA15_MARK___2 = 3706,\n\tKEYOUT4_MARK = 3707,\n\tA16_MARK___2 = 3708,\n\tKEYOUT3_MARK = 3709,\n\tMSIOF0_SS1_MARK___2 = 3710,\n\tA17_MARK___2 = 3711,\n\tKEYOUT2_MARK = 3712,\n\tMSIOF0_TSYNC_MARK = 3713,\n\tA18_MARK___2 = 3714,\n\tKEYOUT1_MARK = 3715,\n\tMSIOF0_TSCK_MARK = 3716,\n\tA19_MARK___2 = 3717,\n\tKEYOUT0_MARK = 3718,\n\tMSIOF0_TXD_MARK___2 = 3719,\n\tA20_MARK___2 = 3720,\n\tKEYIN0_MARK = 3721,\n\tMSIOF0_RSCK_MARK = 3722,\n\tA21_MARK___2 = 3723,\n\tKEYIN1_MARK = 3724,\n\tMSIOF0_RSYNC_MARK = 3725,\n\tA22_MARK___2 = 3726,\n\tKEYIN2_MARK = 3727,\n\tMSIOF0_MCK0_MARK = 3728,\n\tA23_MARK___2 = 3729,\n\tKEYIN3_MARK = 3730,\n\tMSIOF0_MCK1_MARK = 3731,\n\tA24_MARK___2 = 3732,\n\tKEYIN4_MARK = 3733,\n\tMSIOF0_RXD_MARK___2 = 3734,\n\tA25_MARK___2 = 3735,\n\tKEYIN5_MARK = 3736,\n\tMSIOF0_SS2_MARK___2 = 3737,\n\tA26_MARK = 3738,\n\tKEYIN6_MARK = 3739,\n\tKEYIN7_MARK = 3740,\n\tD0_NAF0_MARK = 3741,\n\tD1_NAF1_MARK = 3742,\n\tD2_NAF2_MARK = 3743,\n\tD3_NAF3_MARK = 3744,\n\tD4_NAF4_MARK = 3745,\n\tD5_NAF5_MARK = 3746,\n\tD6_NAF6_MARK = 3747,\n\tD7_NAF7_MARK = 3748,\n\tD8_NAF8_MARK = 3749,\n\tD9_NAF9_MARK = 3750,\n\tD10_NAF10_MARK = 3751,\n\tD11_NAF11_MARK = 3752,\n\tD12_NAF12_MARK = 3753,\n\tD13_NAF13_MARK = 3754,\n\tD14_NAF14_MARK = 3755,\n\tD15_NAF15_MARK = 3756,\n\tCS4__MARK = 3757,\n\tCS5A__MARK = 3758,\n\tPORT91_RDWR_MARK = 3759,\n\tCS5B__MARK = 3760,\n\tFCE1__MARK = 3761,\n\tCS6B__MARK = 3762,\n\tDACK0_MARK___2 = 3763,\n\tFCE0__MARK = 3764,\n\tCS6A__MARK = 3765,\n\tWAIT__MARK = 3766,\n\tDREQ0_MARK = 3767,\n\tRD__FSC_MARK = 3768,\n\tWE0__FWE_MARK = 3769,\n\tRDWR_FWE_MARK = 3770,\n\tWE1__MARK = 3771,\n\tFRB_MARK = 3772,\n\tCKO_MARK = 3773,\n\tNBRSTOUT__MARK = 3774,\n\tNBRST__MARK = 3775,\n\tBBIF2_TXD_MARK = 3776,\n\tBBIF2_RXD_MARK = 3777,\n\tBBIF2_SYNC_MARK = 3778,\n\tBBIF2_SCK_MARK = 3779,\n\tSCIFA3_CTS__MARK = 3780,\n\tMFG3_IN2_MARK = 3781,\n\tSCIFA3_RXD_MARK___2 = 3782,\n\tMFG3_IN1_MARK = 3783,\n\tBBIF1_SS2_MARK = 3784,\n\tSCIFA3_RTS__MARK = 3785,\n\tMFG3_OUT1_MARK = 3786,\n\tSCIFA3_TXD_MARK___2 = 3787,\n\tHSI_RX_DATA_MARK = 3788,\n\tBBIF1_RXD_MARK = 3789,\n\tHSI_TX_WAKE_MARK = 3790,\n\tBBIF1_TSCK_MARK = 3791,\n\tHSI_TX_DATA_MARK = 3792,\n\tBBIF1_TSYNC_MARK = 3793,\n\tHSI_TX_READY_MARK = 3794,\n\tBBIF1_TXD_MARK = 3795,\n\tHSI_RX_READY_MARK = 3796,\n\tBBIF1_RSCK_MARK = 3797,\n\tPORT115_I2C_SCL2_MARK = 3798,\n\tPORT115_I2C_SCL3_MARK = 3799,\n\tHSI_RX_WAKE_MARK = 3800,\n\tBBIF1_RSYNC_MARK = 3801,\n\tPORT116_I2C_SDA2_MARK = 3802,\n\tPORT116_I2C_SDA3_MARK = 3803,\n\tHSI_RX_FLAG_MARK = 3804,\n\tBBIF1_SS1_MARK = 3805,\n\tBBIF1_FLOW_MARK = 3806,\n\tHSI_TX_FLAG_MARK = 3807,\n\tVIO_VD_MARK = 3808,\n\tPORT128_LCD2VSYN_MARK = 3809,\n\tVIO2_VD_MARK = 3810,\n\tLCD2D0_MARK = 3811,\n\tVIO_HD_MARK = 3812,\n\tPORT129_LCD2HSYN_MARK = 3813,\n\tPORT129_LCD2CS__MARK = 3814,\n\tVIO2_HD_MARK = 3815,\n\tLCD2D1_MARK = 3816,\n\tVIO_D0_MARK = 3817,\n\tPORT130_MSIOF2_RXD_MARK = 3818,\n\tLCD2D10_MARK = 3819,\n\tVIO_D1_MARK = 3820,\n\tPORT131_KEYOUT6_MARK = 3821,\n\tPORT131_MSIOF2_SS1_MARK = 3822,\n\tPORT131_KEYOUT11_MARK = 3823,\n\tLCD2D11_MARK = 3824,\n\tVIO_D2_MARK = 3825,\n\tPORT132_KEYOUT7_MARK = 3826,\n\tPORT132_MSIOF2_SS2_MARK = 3827,\n\tPORT132_KEYOUT10_MARK = 3828,\n\tLCD2D12_MARK = 3829,\n\tVIO_D3_MARK = 3830,\n\tMSIOF2_TSYNC_MARK = 3831,\n\tLCD2D13_MARK = 3832,\n\tVIO_D4_MARK = 3833,\n\tMSIOF2_TXD_MARK___2 = 3834,\n\tLCD2D14_MARK = 3835,\n\tVIO_D5_MARK = 3836,\n\tMSIOF2_TSCK_MARK = 3837,\n\tLCD2D15_MARK = 3838,\n\tVIO_D6_MARK = 3839,\n\tPORT136_KEYOUT8_MARK = 3840,\n\tLCD2D16_MARK = 3841,\n\tVIO_D7_MARK = 3842,\n\tPORT137_KEYOUT9_MARK = 3843,\n\tLCD2D17_MARK = 3844,\n\tVIO_D8_MARK = 3845,\n\tPORT138_KEYOUT8_MARK = 3846,\n\tVIO2_D0_MARK = 3847,\n\tLCD2D6_MARK = 3848,\n\tVIO_D9_MARK = 3849,\n\tPORT139_KEYOUT9_MARK = 3850,\n\tVIO2_D1_MARK = 3851,\n\tLCD2D7_MARK = 3852,\n\tVIO_D10_MARK = 3853,\n\tTPU0TO2_MARK = 3854,\n\tVIO2_D2_MARK = 3855,\n\tLCD2D8_MARK = 3856,\n\tVIO_D11_MARK = 3857,\n\tTPU0TO3_MARK = 3858,\n\tVIO2_D3_MARK = 3859,\n\tLCD2D9_MARK = 3860,\n\tVIO_D12_MARK = 3861,\n\tPORT142_KEYOUT10_MARK = 3862,\n\tVIO2_D4_MARK = 3863,\n\tLCD2D2_MARK = 3864,\n\tVIO_D13_MARK = 3865,\n\tPORT143_KEYOUT11_MARK = 3866,\n\tPORT143_KEYOUT6_MARK = 3867,\n\tVIO2_D5_MARK = 3868,\n\tLCD2D3_MARK = 3869,\n\tVIO_D14_MARK = 3870,\n\tPORT144_KEYOUT7_MARK = 3871,\n\tVIO2_D6_MARK = 3872,\n\tLCD2D4_MARK = 3873,\n\tVIO_D15_MARK = 3874,\n\tTPU1TO3_MARK = 3875,\n\tPORT145_LCD2DISP_MARK = 3876,\n\tPORT145_LCD2RS_MARK = 3877,\n\tVIO2_D7_MARK = 3878,\n\tLCD2D5_MARK = 3879,\n\tVIO_CLK_MARK = 3880,\n\tLCD2DCK_MARK = 3881,\n\tPORT146_LCD2WR__MARK = 3882,\n\tVIO2_CLK_MARK = 3883,\n\tLCD2D18_MARK = 3884,\n\tVIO_FIELD_MARK = 3885,\n\tLCD2RD__MARK = 3886,\n\tVIO2_FIELD_MARK = 3887,\n\tLCD2D19_MARK = 3888,\n\tVIO_CKO_MARK = 3889,\n\tA27_MARK = 3890,\n\tPORT149_RDWR_MARK = 3891,\n\tMFG0_IN1_MARK = 3892,\n\tPORT149_KEYOUT9_MARK = 3893,\n\tMFG0_IN2_MARK = 3894,\n\tTS_SPSYNC3_MARK = 3895,\n\tMSIOF2_RSCK_MARK = 3896,\n\tTS_SDAT3_MARK = 3897,\n\tMSIOF2_RSYNC_MARK = 3898,\n\tTPU1TO2_MARK = 3899,\n\tTS_SDEN3_MARK = 3900,\n\tPORT153_MSIOF2_SS1_MARK = 3901,\n\tSCIFA2_TXD1_MARK = 3902,\n\tMSIOF2_MCK0_MARK = 3903,\n\tSCIFA2_RXD1_MARK = 3904,\n\tMSIOF2_MCK1_MARK = 3905,\n\tSCIFA2_RTS1__MARK = 3906,\n\tPORT156_MSIOF2_SS2_MARK = 3907,\n\tSCIFA2_CTS1__MARK = 3908,\n\tPORT157_MSIOF2_RXD_MARK = 3909,\n\tDINT__MARK = 3910,\n\tSCIFA2_SCK1_MARK = 3911,\n\tTS_SCK3_MARK = 3912,\n\tPORT159_SCIFB_SCK_MARK = 3913,\n\tPORT159_SCIFA5_SCK_MARK = 3914,\n\tNMI_MARK = 3915,\n\tPORT160_SCIFB_TXD_MARK = 3916,\n\tPORT160_SCIFA5_TXD_MARK = 3917,\n\tPORT161_SCIFB_CTS__MARK = 3918,\n\tPORT161_SCIFA5_CTS__MARK = 3919,\n\tPORT162_SCIFB_RXD_MARK = 3920,\n\tPORT162_SCIFA5_RXD_MARK = 3921,\n\tPORT163_SCIFB_RTS__MARK = 3922,\n\tPORT163_SCIFA5_RTS__MARK = 3923,\n\tTPU3TO0_MARK = 3924,\n\tLCDD0_MARK = 3925,\n\tLCDD1_MARK = 3926,\n\tPORT193_SCIFA5_CTS__MARK = 3927,\n\tBBIF2_TSYNC1_MARK = 3928,\n\tLCDD2_MARK = 3929,\n\tPORT194_SCIFA5_RTS__MARK = 3930,\n\tBBIF2_TSCK1_MARK = 3931,\n\tLCDD3_MARK = 3932,\n\tPORT195_SCIFA5_RXD_MARK = 3933,\n\tBBIF2_TXD1_MARK = 3934,\n\tLCDD4_MARK = 3935,\n\tPORT196_SCIFA5_TXD_MARK = 3936,\n\tLCDD5_MARK = 3937,\n\tPORT197_SCIFA5_SCK_MARK = 3938,\n\tMFG2_OUT2_MARK = 3939,\n\tTPU2TO1_MARK = 3940,\n\tLCDD6_MARK = 3941,\n\tLCDD7_MARK = 3942,\n\tTPU4TO1_MARK = 3943,\n\tMFG4_OUT2_MARK = 3944,\n\tLCDD8_MARK = 3945,\n\tD16_MARK = 3946,\n\tLCDD9_MARK = 3947,\n\tD17_MARK = 3948,\n\tLCDD10_MARK = 3949,\n\tD18_MARK = 3950,\n\tLCDD11_MARK = 3951,\n\tD19_MARK = 3952,\n\tLCDD12_MARK = 3953,\n\tD20_MARK = 3954,\n\tLCDD13_MARK = 3955,\n\tD21_MARK = 3956,\n\tLCDD14_MARK = 3957,\n\tD22_MARK = 3958,\n\tLCDD15_MARK = 3959,\n\tPORT207_MSIOF0L_SS1_MARK = 3960,\n\tD23_MARK = 3961,\n\tLCDD16_MARK = 3962,\n\tPORT208_MSIOF0L_SS2_MARK = 3963,\n\tD24_MARK = 3964,\n\tLCDD17_MARK = 3965,\n\tD25_MARK = 3966,\n\tLCDD18_MARK = 3967,\n\tDREQ2_MARK = 3968,\n\tPORT210_MSIOF0L_SS1_MARK = 3969,\n\tD26_MARK = 3970,\n\tLCDD19_MARK = 3971,\n\tPORT211_MSIOF0L_SS2_MARK = 3972,\n\tD27_MARK = 3973,\n\tLCDD20_MARK = 3974,\n\tTS_SPSYNC1_MARK = 3975,\n\tMSIOF0L_MCK0_MARK = 3976,\n\tD28_MARK = 3977,\n\tLCDD21_MARK = 3978,\n\tTS_SDAT1_MARK = 3979,\n\tMSIOF0L_MCK1_MARK = 3980,\n\tD29_MARK = 3981,\n\tLCDD22_MARK = 3982,\n\tTS_SDEN1_MARK = 3983,\n\tMSIOF0L_RSCK_MARK = 3984,\n\tD30_MARK = 3985,\n\tLCDD23_MARK = 3986,\n\tTS_SCK1_MARK = 3987,\n\tMSIOF0L_RSYNC_MARK = 3988,\n\tD31_MARK = 3989,\n\tLCDDCK_MARK = 3990,\n\tLCDWR__MARK = 3991,\n\tLCDRD__MARK = 3992,\n\tDACK2_MARK___2 = 3993,\n\tPORT217_LCD2RS_MARK = 3994,\n\tMSIOF0L_TSYNC_MARK = 3995,\n\tVIO2_FIELD3_MARK = 3996,\n\tPORT217_LCD2DISP_MARK = 3997,\n\tLCDHSYN_MARK = 3998,\n\tLCDCS__MARK = 3999,\n\tLCDCS2__MARK = 4000,\n\tDACK3_MARK = 4001,\n\tPORT218_VIO_CKOR_MARK = 4002,\n\tLCDDISP_MARK = 4003,\n\tLCDRS_MARK = 4004,\n\tPORT219_LCD2WR__MARK = 4005,\n\tDREQ3_MARK = 4006,\n\tMSIOF0L_TSCK_MARK = 4007,\n\tVIO2_CLK3_MARK = 4008,\n\tLCD2DCK_2_MARK = 4009,\n\tLCDVSYN_MARK = 4010,\n\tLCDVSYN2_MARK = 4011,\n\tLCDLCLK_MARK = 4012,\n\tDREQ1_MARK = 4013,\n\tPORT221_LCD2CS__MARK = 4014,\n\tPWEN_MARK = 4015,\n\tMSIOF0L_RXD_MARK = 4016,\n\tVIO2_HD3_MARK = 4017,\n\tPORT221_LCD2HSYN_MARK = 4018,\n\tLCDDON_MARK = 4019,\n\tLCDDON2_MARK = 4020,\n\tDACK1_MARK___2 = 4021,\n\tOVCN_MARK = 4022,\n\tMSIOF0L_TXD_MARK = 4023,\n\tVIO2_VD3_MARK = 4024,\n\tPORT222_LCD2VSYN_MARK = 4025,\n\tSCIFA1_TXD_MARK___2 = 4026,\n\tOVCN2_MARK = 4027,\n\tEXTLP_MARK = 4028,\n\tSCIFA1_SCK_MARK___2 = 4029,\n\tPORT226_VIO_CKO2_MARK = 4030,\n\tSCIFA1_RTS__MARK = 4031,\n\tIDIN_MARK = 4032,\n\tSCIFA1_RXD_MARK___2 = 4033,\n\tSCIFA1_CTS__MARK = 4034,\n\tMFG1_IN1_MARK = 4035,\n\tMSIOF1_TXD_MARK___2 = 4036,\n\tSCIFA2_TXD2_MARK = 4037,\n\tMSIOF1_TSYNC_MARK = 4038,\n\tSCIFA2_CTS2__MARK = 4039,\n\tMSIOF1_TSCK_MARK = 4040,\n\tSCIFA2_SCK2_MARK = 4041,\n\tMSIOF1_RXD_MARK___2 = 4042,\n\tSCIFA2_RXD2_MARK = 4043,\n\tMSIOF1_RSCK_MARK = 4044,\n\tSCIFA2_RTS2__MARK = 4045,\n\tVIO2_CLK2_MARK = 4046,\n\tLCD2D20_MARK = 4047,\n\tMSIOF1_RSYNC_MARK = 4048,\n\tMFG1_IN2_MARK = 4049,\n\tVIO2_VD2_MARK = 4050,\n\tLCD2D21_MARK = 4051,\n\tMSIOF1_MCK0_MARK = 4052,\n\tPORT236_I2C_SDA2_MARK = 4053,\n\tMSIOF1_MCK1_MARK = 4054,\n\tPORT237_I2C_SCL2_MARK = 4055,\n\tMSIOF1_SS1_MARK___2 = 4056,\n\tVIO2_FIELD2_MARK = 4057,\n\tLCD2D22_MARK = 4058,\n\tMSIOF1_SS2_MARK___2 = 4059,\n\tVIO2_HD2_MARK = 4060,\n\tLCD2D23_MARK = 4061,\n\tSCIFA6_TXD_MARK = 4062,\n\tPORT241_IRDA_OUT_MARK = 4063,\n\tPORT241_IROUT_MARK = 4064,\n\tMFG4_OUT1_MARK = 4065,\n\tTPU4TO0_MARK = 4066,\n\tPORT242_IRDA_IN_MARK = 4067,\n\tMFG4_IN2_MARK = 4068,\n\tPORT243_IRDA_FIRSEL_MARK = 4069,\n\tPORT243_VIO_CKO2_MARK = 4070,\n\tPORT244_SCIFA5_CTS__MARK = 4071,\n\tMFG2_IN1_MARK = 4072,\n\tPORT244_SCIFB_CTS__MARK = 4073,\n\tMSIOF2R_RXD_MARK = 4074,\n\tPORT245_SCIFA5_RTS__MARK = 4075,\n\tMFG2_IN2_MARK = 4076,\n\tPORT245_SCIFB_RTS__MARK = 4077,\n\tMSIOF2R_TXD_MARK = 4078,\n\tPORT246_SCIFA5_RXD_MARK = 4079,\n\tMFG1_OUT1_MARK = 4080,\n\tPORT246_SCIFB_RXD_MARK = 4081,\n\tTPU1TO0_MARK = 4082,\n\tPORT247_SCIFA5_TXD_MARK = 4083,\n\tMFG3_OUT2_MARK = 4084,\n\tPORT247_SCIFB_TXD_MARK = 4085,\n\tTPU3TO1_MARK = 4086,\n\tPORT248_SCIFA5_SCK_MARK = 4087,\n\tMFG2_OUT1_MARK = 4088,\n\tPORT248_SCIFB_SCK_MARK = 4089,\n\tTPU2TO0_MARK = 4090,\n\tPORT248_I2C_SCL3_MARK = 4091,\n\tMSIOF2R_TSCK_MARK = 4092,\n\tPORT249_IROUT_MARK = 4093,\n\tMFG4_IN1_MARK = 4094,\n\tPORT249_I2C_SDA3_MARK = 4095,\n\tMSIOF2R_TSYNC_MARK = 4096,\n\tSDHICLK0_MARK = 4097,\n\tSDHICD0_MARK = 4098,\n\tSDHID0_0_MARK = 4099,\n\tSDHID0_1_MARK = 4100,\n\tSDHID0_2_MARK = 4101,\n\tSDHID0_3_MARK = 4102,\n\tSDHICMD0_MARK = 4103,\n\tSDHIWP0_MARK = 4104,\n\tSDHICLK1_MARK = 4105,\n\tSDHID1_0_MARK = 4106,\n\tTS_SPSYNC2_MARK = 4107,\n\tSDHID1_1_MARK = 4108,\n\tTS_SDAT2_MARK = 4109,\n\tSDHID1_2_MARK = 4110,\n\tTS_SDEN2_MARK = 4111,\n\tSDHID1_3_MARK = 4112,\n\tTS_SCK2_MARK = 4113,\n\tSDHICMD1_MARK = 4114,\n\tSDHICLK2_MARK = 4115,\n\tSDHID2_0_MARK = 4116,\n\tTS_SPSYNC4_MARK = 4117,\n\tSDHID2_1_MARK = 4118,\n\tTS_SDAT4_MARK = 4119,\n\tSDHID2_2_MARK = 4120,\n\tTS_SDEN4_MARK = 4121,\n\tSDHID2_3_MARK = 4122,\n\tTS_SCK4_MARK = 4123,\n\tSDHICMD2_MARK = 4124,\n\tMMCCLK0_MARK = 4125,\n\tMMCD0_0_MARK = 4126,\n\tMMCD0_1_MARK = 4127,\n\tMMCD0_2_MARK = 4128,\n\tMMCD0_3_MARK = 4129,\n\tMMCD0_4_MARK = 4130,\n\tTS_SPSYNC5_MARK = 4131,\n\tMMCD0_5_MARK = 4132,\n\tTS_SDAT5_MARK = 4133,\n\tMMCD0_6_MARK = 4134,\n\tTS_SDEN5_MARK = 4135,\n\tMMCD0_7_MARK = 4136,\n\tTS_SCK5_MARK = 4137,\n\tMMCCMD0_MARK = 4138,\n\tRESETOUTS__MARK = 4139,\n\tEXTAL2OUT_MARK = 4140,\n\tMCP_WAIT__MCP_FRB_MARK = 4141,\n\tMCP_CKO_MARK = 4142,\n\tMMCCLK1_MARK = 4143,\n\tMCP_D15_MCP_NAF15_MARK = 4144,\n\tMCP_D14_MCP_NAF14_MARK = 4145,\n\tMCP_D13_MCP_NAF13_MARK = 4146,\n\tMCP_D12_MCP_NAF12_MARK = 4147,\n\tMCP_D11_MCP_NAF11_MARK = 4148,\n\tMCP_D10_MCP_NAF10_MARK = 4149,\n\tMCP_D9_MCP_NAF9_MARK = 4150,\n\tMCP_D8_MCP_NAF8_MARK = 4151,\n\tMMCCMD1_MARK = 4152,\n\tMCP_D7_MCP_NAF7_MARK = 4153,\n\tMMCD1_7_MARK = 4154,\n\tMCP_D6_MCP_NAF6_MARK = 4155,\n\tMMCD1_6_MARK = 4156,\n\tMCP_D5_MCP_NAF5_MARK = 4157,\n\tMMCD1_5_MARK = 4158,\n\tMCP_D4_MCP_NAF4_MARK = 4159,\n\tMMCD1_4_MARK = 4160,\n\tMCP_D3_MCP_NAF3_MARK = 4161,\n\tMMCD1_3_MARK = 4162,\n\tMCP_D2_MCP_NAF2_MARK = 4163,\n\tMMCD1_2_MARK = 4164,\n\tMCP_D1_MCP_NAF1_MARK = 4165,\n\tMMCD1_1_MARK = 4166,\n\tMCP_D0_MCP_NAF0_MARK = 4167,\n\tMMCD1_0_MARK = 4168,\n\tMCP_NBRSTOUT__MARK = 4169,\n\tMCP_WE0__MCP_FWE_MARK = 4170,\n\tMCP_RDWR_MCP_FWE_MARK = 4171,\n\tTSIF2_TS_XX1_MARK = 4172,\n\tTSIF2_TS_XX2_MARK = 4173,\n\tTSIF2_TS_XX3_MARK = 4174,\n\tTSIF2_TS_XX4_MARK = 4175,\n\tTSIF2_TS_XX5_MARK = 4176,\n\tTSIF1_TS_XX1_MARK = 4177,\n\tTSIF1_TS_XX2_MARK = 4178,\n\tTSIF1_TS_XX3_MARK = 4179,\n\tTSIF1_TS_XX4_MARK = 4180,\n\tTSIF1_TS_XX5_MARK = 4181,\n\tTSIF0_TS_XX1_MARK = 4182,\n\tTSIF0_TS_XX2_MARK = 4183,\n\tTSIF0_TS_XX3_MARK = 4184,\n\tTSIF0_TS_XX4_MARK = 4185,\n\tTSIF0_TS_XX5_MARK = 4186,\n\tMST1_TS_XX1_MARK = 4187,\n\tMST1_TS_XX2_MARK = 4188,\n\tMST1_TS_XX3_MARK = 4189,\n\tMST1_TS_XX4_MARK = 4190,\n\tMST1_TS_XX5_MARK = 4191,\n\tMST0_TS_XX1_MARK = 4192,\n\tMST0_TS_XX2_MARK = 4193,\n\tMST0_TS_XX3_MARK = 4194,\n\tMST0_TS_XX4_MARK = 4195,\n\tMST0_TS_XX5_MARK = 4196,\n\tSDHI0_VCCQ_MC0_ON_MARK = 4197,\n\tSDHI0_VCCQ_MC0_OFF_MARK = 4198,\n\tDEBUG_MON_VIO_MARK = 4199,\n\tDEBUG_MON_LCDD_MARK = 4200,\n\tLCDC_LCDC0_MARK = 4201,\n\tLCDC_LCDC1_MARK = 4202,\n\tIRQ9_MEM_INT_MARK = 4203,\n\tIRQ9_MCP_INT_MARK = 4204,\n\tA11_MARK___2 = 4205,\n\tKEYOUT8_MARK = 4206,\n\tTPU4TO3_MARK = 4207,\n\tRESETA_N_PU_ON_MARK = 4208,\n\tRESETA_N_PU_OFF_MARK = 4209,\n\tEDBGREQ_PD_MARK = 4210,\n\tEDBGREQ_PU_MARK = 4211,\n\tPINMUX_MARK_END___2 = 4212,\n};\n\nenum {\n\tPINMUX_RESERVED___3 = 0,\n\tPINMUX_DATA_BEGIN___3 = 1,\n\tGP_0_0_DATA___2 = 2,\n\tGP_0_1_DATA___2 = 3,\n\tGP_0_2_DATA___2 = 4,\n\tGP_0_3_DATA___2 = 5,\n\tGP_0_4_DATA___2 = 6,\n\tGP_0_5_DATA___2 = 7,\n\tGP_0_6_DATA___2 = 8,\n\tGP_0_7_DATA___2 = 9,\n\tGP_0_8_DATA___2 = 10,\n\tGP_0_9_DATA___2 = 11,\n\tGP_0_10_DATA___2 = 12,\n\tGP_0_11_DATA___2 = 13,\n\tGP_0_12_DATA___2 = 14,\n\tGP_0_13_DATA___2 = 15,\n\tGP_0_14_DATA___2 = 16,\n\tGP_0_15_DATA___2 = 17,\n\tGP_0_16_DATA___2 = 18,\n\tGP_0_17_DATA___2 = 19,\n\tGP_0_18_DATA___2 = 20,\n\tGP_0_19_DATA___2 = 21,\n\tGP_0_20_DATA___2 = 22,\n\tGP_0_21_DATA___2 = 23,\n\tGP_0_22_DATA___2 = 24,\n\tGP_0_23_DATA___2 = 25,\n\tGP_0_24_DATA___2 = 26,\n\tGP_0_25_DATA___2 = 27,\n\tGP_0_26_DATA___2 = 28,\n\tGP_0_27_DATA___2 = 29,\n\tGP_0_28_DATA___2 = 30,\n\tGP_0_29_DATA___2 = 31,\n\tGP_0_30_DATA___2 = 32,\n\tGP_0_31_DATA___2 = 33,\n\tGP_1_0_DATA___2 = 34,\n\tGP_1_1_DATA___2 = 35,\n\tGP_1_2_DATA___2 = 36,\n\tGP_1_3_DATA___2 = 37,\n\tGP_1_4_DATA___2 = 38,\n\tGP_1_5_DATA___2 = 39,\n\tGP_1_6_DATA___2 = 40,\n\tGP_1_7_DATA___2 = 41,\n\tGP_1_8_DATA___2 = 42,\n\tGP_1_9_DATA___2 = 43,\n\tGP_1_10_DATA___2 = 44,\n\tGP_1_11_DATA___2 = 45,\n\tGP_1_12_DATA___2 = 46,\n\tGP_1_13_DATA___2 = 47,\n\tGP_1_14_DATA___2 = 48,\n\tGP_1_15_DATA___2 = 49,\n\tGP_1_16_DATA___2 = 50,\n\tGP_1_17_DATA___2 = 51,\n\tGP_1_18_DATA___2 = 52,\n\tGP_1_19_DATA___2 = 53,\n\tGP_1_20_DATA___2 = 54,\n\tGP_1_21_DATA___2 = 55,\n\tGP_1_22_DATA___2 = 56,\n\tGP_1_23_DATA___2 = 57,\n\tGP_1_24_DATA___2 = 58,\n\tGP_1_25_DATA___2 = 59,\n\tGP_2_0_DATA___2 = 60,\n\tGP_2_1_DATA___2 = 61,\n\tGP_2_2_DATA___2 = 62,\n\tGP_2_3_DATA___2 = 63,\n\tGP_2_4_DATA___2 = 64,\n\tGP_2_5_DATA___2 = 65,\n\tGP_2_6_DATA___2 = 66,\n\tGP_2_7_DATA___2 = 67,\n\tGP_2_8_DATA___2 = 68,\n\tGP_2_9_DATA___2 = 69,\n\tGP_2_10_DATA___2 = 70,\n\tGP_2_11_DATA___2 = 71,\n\tGP_2_12_DATA___2 = 72,\n\tGP_2_13_DATA___2 = 73,\n\tGP_2_14_DATA___2 = 74,\n\tGP_2_15_DATA___2 = 75,\n\tGP_2_16_DATA___2 = 76,\n\tGP_2_17_DATA___2 = 77,\n\tGP_2_18_DATA___2 = 78,\n\tGP_2_19_DATA___2 = 79,\n\tGP_2_20_DATA___2 = 80,\n\tGP_2_21_DATA___2 = 81,\n\tGP_2_22_DATA___2 = 82,\n\tGP_2_23_DATA___2 = 83,\n\tGP_2_24_DATA___2 = 84,\n\tGP_2_25_DATA___2 = 85,\n\tGP_2_26_DATA___2 = 86,\n\tGP_2_27_DATA___2 = 87,\n\tGP_2_28_DATA___2 = 88,\n\tGP_2_29_DATA___2 = 89,\n\tGP_2_30_DATA___2 = 90,\n\tGP_2_31_DATA___2 = 91,\n\tGP_3_0_DATA___2 = 92,\n\tGP_3_1_DATA___2 = 93,\n\tGP_3_2_DATA___2 = 94,\n\tGP_3_3_DATA___2 = 95,\n\tGP_3_4_DATA___2 = 96,\n\tGP_3_5_DATA___2 = 97,\n\tGP_3_6_DATA___2 = 98,\n\tGP_3_7_DATA___2 = 99,\n\tGP_3_8_DATA___2 = 100,\n\tGP_3_9_DATA___2 = 101,\n\tGP_3_10_DATA___2 = 102,\n\tGP_3_11_DATA___2 = 103,\n\tGP_3_12_DATA___2 = 104,\n\tGP_3_13_DATA___2 = 105,\n\tGP_3_14_DATA___2 = 106,\n\tGP_3_15_DATA___2 = 107,\n\tGP_3_16_DATA___2 = 108,\n\tGP_3_17_DATA___2 = 109,\n\tGP_3_18_DATA___2 = 110,\n\tGP_3_19_DATA___2 = 111,\n\tGP_3_20_DATA___2 = 112,\n\tGP_3_21_DATA___2 = 113,\n\tGP_3_22_DATA___2 = 114,\n\tGP_3_23_DATA___2 = 115,\n\tGP_3_24_DATA___2 = 116,\n\tGP_3_25_DATA___2 = 117,\n\tGP_3_26_DATA___2 = 118,\n\tGP_3_27_DATA___2 = 119,\n\tGP_3_28_DATA___2 = 120,\n\tGP_3_29_DATA___2 = 121,\n\tGP_3_30_DATA___2 = 122,\n\tGP_3_31_DATA___2 = 123,\n\tGP_4_0_DATA___2 = 124,\n\tGP_4_1_DATA___2 = 125,\n\tGP_4_2_DATA___2 = 126,\n\tGP_4_3_DATA___2 = 127,\n\tGP_4_4_DATA___2 = 128,\n\tGP_4_5_DATA___2 = 129,\n\tGP_4_6_DATA___2 = 130,\n\tGP_4_7_DATA___2 = 131,\n\tGP_4_8_DATA___2 = 132,\n\tGP_4_9_DATA___2 = 133,\n\tGP_4_10_DATA___2 = 134,\n\tGP_4_11_DATA___2 = 135,\n\tGP_4_12_DATA___2 = 136,\n\tGP_4_13_DATA___2 = 137,\n\tGP_4_14_DATA___2 = 138,\n\tGP_4_15_DATA___2 = 139,\n\tGP_4_16_DATA___2 = 140,\n\tGP_4_17_DATA___2 = 141,\n\tGP_4_18_DATA___2 = 142,\n\tGP_4_19_DATA___2 = 143,\n\tGP_4_20_DATA___2 = 144,\n\tGP_4_21_DATA___2 = 145,\n\tGP_4_22_DATA___2 = 146,\n\tGP_4_23_DATA___2 = 147,\n\tGP_4_24_DATA___2 = 148,\n\tGP_4_25_DATA___2 = 149,\n\tGP_4_26_DATA___2 = 150,\n\tGP_4_27_DATA___2 = 151,\n\tGP_4_28_DATA___2 = 152,\n\tGP_4_29_DATA___2 = 153,\n\tGP_4_30_DATA___2 = 154,\n\tGP_4_31_DATA___2 = 155,\n\tGP_5_0_DATA___2 = 156,\n\tGP_5_1_DATA___2 = 157,\n\tGP_5_2_DATA___2 = 158,\n\tGP_5_3_DATA___2 = 159,\n\tGP_5_4_DATA___2 = 160,\n\tGP_5_5_DATA___2 = 161,\n\tGP_5_6_DATA___2 = 162,\n\tGP_5_7_DATA___2 = 163,\n\tGP_5_8_DATA___2 = 164,\n\tGP_5_9_DATA___2 = 165,\n\tGP_5_10_DATA___2 = 166,\n\tGP_5_11_DATA___2 = 167,\n\tGP_5_12_DATA___2 = 168,\n\tGP_5_13_DATA___2 = 169,\n\tGP_5_14_DATA___2 = 170,\n\tGP_5_15_DATA___2 = 171,\n\tGP_5_16_DATA___2 = 172,\n\tGP_5_17_DATA___2 = 173,\n\tGP_5_18_DATA___2 = 174,\n\tGP_5_19_DATA___2 = 175,\n\tGP_5_20_DATA___2 = 176,\n\tGP_5_21_DATA___2 = 177,\n\tGP_5_22_DATA___2 = 178,\n\tGP_5_23_DATA___2 = 179,\n\tGP_5_24_DATA___2 = 180,\n\tGP_5_25_DATA___2 = 181,\n\tGP_5_26_DATA___2 = 182,\n\tGP_5_27_DATA___2 = 183,\n\tGP_5_28_DATA = 184,\n\tGP_5_29_DATA = 185,\n\tGP_5_30_DATA = 186,\n\tGP_5_31_DATA = 187,\n\tGP_6_0_DATA___2 = 188,\n\tGP_6_1_DATA___2 = 189,\n\tGP_6_2_DATA___2 = 190,\n\tGP_6_3_DATA___2 = 191,\n\tGP_6_4_DATA___2 = 192,\n\tGP_6_5_DATA___2 = 193,\n\tGP_6_6_DATA___2 = 194,\n\tGP_6_7_DATA___2 = 195,\n\tGP_6_8_DATA___2 = 196,\n\tGP_6_9_DATA___2 = 197,\n\tGP_6_10_DATA___2 = 198,\n\tGP_6_11_DATA___2 = 199,\n\tGP_6_12_DATA___2 = 200,\n\tGP_6_13_DATA___2 = 201,\n\tGP_6_14_DATA___2 = 202,\n\tGP_6_15_DATA___2 = 203,\n\tGP_6_16_DATA___2 = 204,\n\tGP_6_17_DATA___2 = 205,\n\tGP_6_18_DATA___2 = 206,\n\tGP_6_19_DATA___2 = 207,\n\tGP_6_20_DATA___2 = 208,\n\tGP_6_21_DATA___2 = 209,\n\tGP_6_22_DATA___2 = 210,\n\tGP_6_23_DATA___2 = 211,\n\tGP_6_24_DATA___2 = 212,\n\tGP_6_25_DATA___2 = 213,\n\tGP_6_26_DATA = 214,\n\tGP_6_27_DATA = 215,\n\tGP_6_28_DATA = 216,\n\tGP_6_29_DATA = 217,\n\tGP_6_30_DATA = 218,\n\tGP_6_31_DATA = 219,\n\tGP_7_0_DATA = 220,\n\tGP_7_1_DATA = 221,\n\tGP_7_2_DATA = 222,\n\tGP_7_3_DATA = 223,\n\tGP_7_4_DATA = 224,\n\tGP_7_5_DATA = 225,\n\tGP_7_6_DATA = 226,\n\tGP_7_7_DATA = 227,\n\tGP_7_8_DATA = 228,\n\tGP_7_9_DATA = 229,\n\tGP_7_10_DATA = 230,\n\tGP_7_11_DATA = 231,\n\tGP_7_12_DATA = 232,\n\tGP_7_13_DATA = 233,\n\tGP_7_14_DATA = 234,\n\tGP_7_15_DATA = 235,\n\tGP_7_16_DATA = 236,\n\tGP_7_17_DATA = 237,\n\tGP_7_18_DATA = 238,\n\tGP_7_19_DATA = 239,\n\tGP_7_20_DATA = 240,\n\tGP_7_21_DATA = 241,\n\tGP_7_22_DATA = 242,\n\tGP_7_23_DATA = 243,\n\tGP_7_24_DATA = 244,\n\tGP_7_25_DATA = 245,\n\tPINMUX_DATA_END___3 = 246,\n\tPINMUX_FUNCTION_BEGIN___3 = 247,\n\tGP_0_0_FN___2 = 248,\n\tGP_0_1_FN___2 = 249,\n\tGP_0_2_FN___2 = 250,\n\tGP_0_3_FN___2 = 251,\n\tGP_0_4_FN___2 = 252,\n\tGP_0_5_FN___2 = 253,\n\tGP_0_6_FN___2 = 254,\n\tGP_0_7_FN___2 = 255,\n\tGP_0_8_FN___2 = 256,\n\tGP_0_9_FN___2 = 257,\n\tGP_0_10_FN___2 = 258,\n\tGP_0_11_FN___2 = 259,\n\tGP_0_12_FN___2 = 260,\n\tGP_0_13_FN___2 = 261,\n\tGP_0_14_FN___2 = 262,\n\tGP_0_15_FN___2 = 263,\n\tGP_0_16_FN___2 = 264,\n\tGP_0_17_FN___2 = 265,\n\tGP_0_18_FN___2 = 266,\n\tGP_0_19_FN___2 = 267,\n\tGP_0_20_FN___2 = 268,\n\tGP_0_21_FN___2 = 269,\n\tGP_0_22_FN___2 = 270,\n\tGP_0_23_FN___2 = 271,\n\tGP_0_24_FN___2 = 272,\n\tGP_0_25_FN___2 = 273,\n\tGP_0_26_FN___2 = 274,\n\tGP_0_27_FN___2 = 275,\n\tGP_0_28_FN___2 = 276,\n\tGP_0_29_FN___2 = 277,\n\tGP_0_30_FN___2 = 278,\n\tGP_0_31_FN___2 = 279,\n\tGP_1_0_FN___2 = 280,\n\tGP_1_1_FN___2 = 281,\n\tGP_1_2_FN___2 = 282,\n\tGP_1_3_FN___2 = 283,\n\tGP_1_4_FN___2 = 284,\n\tGP_1_5_FN___2 = 285,\n\tGP_1_6_FN___2 = 286,\n\tGP_1_7_FN___2 = 287,\n\tGP_1_8_FN___2 = 288,\n\tGP_1_9_FN___2 = 289,\n\tGP_1_10_FN___2 = 290,\n\tGP_1_11_FN___2 = 291,\n\tGP_1_12_FN___2 = 292,\n\tGP_1_13_FN___2 = 293,\n\tGP_1_14_FN___2 = 294,\n\tGP_1_15_FN___2 = 295,\n\tGP_1_16_FN___2 = 296,\n\tGP_1_17_FN___2 = 297,\n\tGP_1_18_FN___2 = 298,\n\tGP_1_19_FN___2 = 299,\n\tGP_1_20_FN___2 = 300,\n\tGP_1_21_FN___2 = 301,\n\tGP_1_22_FN___2 = 302,\n\tGP_1_23_FN___2 = 303,\n\tGP_1_24_FN___2 = 304,\n\tGP_1_25_FN___2 = 305,\n\tGP_2_0_FN___2 = 306,\n\tGP_2_1_FN___2 = 307,\n\tGP_2_2_FN___2 = 308,\n\tGP_2_3_FN___2 = 309,\n\tGP_2_4_FN___2 = 310,\n\tGP_2_5_FN___2 = 311,\n\tGP_2_6_FN___2 = 312,\n\tGP_2_7_FN___2 = 313,\n\tGP_2_8_FN___2 = 314,\n\tGP_2_9_FN___2 = 315,\n\tGP_2_10_FN___2 = 316,\n\tGP_2_11_FN___2 = 317,\n\tGP_2_12_FN___2 = 318,\n\tGP_2_13_FN___2 = 319,\n\tGP_2_14_FN___2 = 320,\n\tGP_2_15_FN___2 = 321,\n\tGP_2_16_FN___2 = 322,\n\tGP_2_17_FN___2 = 323,\n\tGP_2_18_FN___2 = 324,\n\tGP_2_19_FN___2 = 325,\n\tGP_2_20_FN___2 = 326,\n\tGP_2_21_FN___2 = 327,\n\tGP_2_22_FN___2 = 328,\n\tGP_2_23_FN___2 = 329,\n\tGP_2_24_FN___2 = 330,\n\tGP_2_25_FN___2 = 331,\n\tGP_2_26_FN___2 = 332,\n\tGP_2_27_FN___2 = 333,\n\tGP_2_28_FN___2 = 334,\n\tGP_2_29_FN___2 = 335,\n\tGP_2_30_FN___2 = 336,\n\tGP_2_31_FN___2 = 337,\n\tGP_3_0_FN___2 = 338,\n\tGP_3_1_FN___2 = 339,\n\tGP_3_2_FN___2 = 340,\n\tGP_3_3_FN___2 = 341,\n\tGP_3_4_FN___2 = 342,\n\tGP_3_5_FN___2 = 343,\n\tGP_3_6_FN___2 = 344,\n\tGP_3_7_FN___2 = 345,\n\tGP_3_8_FN___2 = 346,\n\tGP_3_9_FN___2 = 347,\n\tGP_3_10_FN___2 = 348,\n\tGP_3_11_FN___2 = 349,\n\tGP_3_12_FN___2 = 350,\n\tGP_3_13_FN___2 = 351,\n\tGP_3_14_FN___2 = 352,\n\tGP_3_15_FN___2 = 353,\n\tGP_3_16_FN___2 = 354,\n\tGP_3_17_FN___2 = 355,\n\tGP_3_18_FN___2 = 356,\n\tGP_3_19_FN___2 = 357,\n\tGP_3_20_FN___2 = 358,\n\tGP_3_21_FN___2 = 359,\n\tGP_3_22_FN___2 = 360,\n\tGP_3_23_FN___2 = 361,\n\tGP_3_24_FN___2 = 362,\n\tGP_3_25_FN___2 = 363,\n\tGP_3_26_FN___2 = 364,\n\tGP_3_27_FN___2 = 365,\n\tGP_3_28_FN___2 = 366,\n\tGP_3_29_FN___2 = 367,\n\tGP_3_30_FN___2 = 368,\n\tGP_3_31_FN___2 = 369,\n\tGP_4_0_FN___2 = 370,\n\tGP_4_1_FN___2 = 371,\n\tGP_4_2_FN___2 = 372,\n\tGP_4_3_FN___2 = 373,\n\tGP_4_4_FN___2 = 374,\n\tGP_4_5_FN___2 = 375,\n\tGP_4_6_FN___2 = 376,\n\tGP_4_7_FN___2 = 377,\n\tGP_4_8_FN___2 = 378,\n\tGP_4_9_FN___2 = 379,\n\tGP_4_10_FN___2 = 380,\n\tGP_4_11_FN___2 = 381,\n\tGP_4_12_FN___2 = 382,\n\tGP_4_13_FN___2 = 383,\n\tGP_4_14_FN___2 = 384,\n\tGP_4_15_FN___2 = 385,\n\tGP_4_16_FN___2 = 386,\n\tGP_4_17_FN___2 = 387,\n\tGP_4_18_FN___2 = 388,\n\tGP_4_19_FN___2 = 389,\n\tGP_4_20_FN___2 = 390,\n\tGP_4_21_FN___2 = 391,\n\tGP_4_22_FN___2 = 392,\n\tGP_4_23_FN___2 = 393,\n\tGP_4_24_FN___2 = 394,\n\tGP_4_25_FN___2 = 395,\n\tGP_4_26_FN___2 = 396,\n\tGP_4_27_FN___2 = 397,\n\tGP_4_28_FN___2 = 398,\n\tGP_4_29_FN___2 = 399,\n\tGP_4_30_FN___2 = 400,\n\tGP_4_31_FN___2 = 401,\n\tGP_5_0_FN___2 = 402,\n\tGP_5_1_FN___2 = 403,\n\tGP_5_2_FN___2 = 404,\n\tGP_5_3_FN___2 = 405,\n\tGP_5_4_FN___2 = 406,\n\tGP_5_5_FN___2 = 407,\n\tGP_5_6_FN___2 = 408,\n\tGP_5_7_FN___2 = 409,\n\tGP_5_8_FN___2 = 410,\n\tGP_5_9_FN___2 = 411,\n\tGP_5_10_FN___2 = 412,\n\tGP_5_11_FN___2 = 413,\n\tGP_5_12_FN___2 = 414,\n\tGP_5_13_FN___2 = 415,\n\tGP_5_14_FN___2 = 416,\n\tGP_5_15_FN___2 = 417,\n\tGP_5_16_FN___2 = 418,\n\tGP_5_17_FN___2 = 419,\n\tGP_5_18_FN___2 = 420,\n\tGP_5_19_FN___2 = 421,\n\tGP_5_20_FN___2 = 422,\n\tGP_5_21_FN___2 = 423,\n\tGP_5_22_FN___2 = 424,\n\tGP_5_23_FN___2 = 425,\n\tGP_5_24_FN___2 = 426,\n\tGP_5_25_FN___2 = 427,\n\tGP_5_26_FN___2 = 428,\n\tGP_5_27_FN___2 = 429,\n\tGP_5_28_FN = 430,\n\tGP_5_29_FN = 431,\n\tGP_5_30_FN = 432,\n\tGP_5_31_FN = 433,\n\tGP_6_0_FN___2 = 434,\n\tGP_6_1_FN___2 = 435,\n\tGP_6_2_FN___2 = 436,\n\tGP_6_3_FN___2 = 437,\n\tGP_6_4_FN___2 = 438,\n\tGP_6_5_FN___2 = 439,\n\tGP_6_6_FN___2 = 440,\n\tGP_6_7_FN___2 = 441,\n\tGP_6_8_FN___2 = 442,\n\tGP_6_9_FN___2 = 443,\n\tGP_6_10_FN___2 = 444,\n\tGP_6_11_FN___2 = 445,\n\tGP_6_12_FN___2 = 446,\n\tGP_6_13_FN___2 = 447,\n\tGP_6_14_FN___2 = 448,\n\tGP_6_15_FN___2 = 449,\n\tGP_6_16_FN___2 = 450,\n\tGP_6_17_FN___2 = 451,\n\tGP_6_18_FN___2 = 452,\n\tGP_6_19_FN___2 = 453,\n\tGP_6_20_FN___2 = 454,\n\tGP_6_21_FN___2 = 455,\n\tGP_6_22_FN___2 = 456,\n\tGP_6_23_FN___2 = 457,\n\tGP_6_24_FN___2 = 458,\n\tGP_6_25_FN___2 = 459,\n\tGP_6_26_FN = 460,\n\tGP_6_27_FN = 461,\n\tGP_6_28_FN = 462,\n\tGP_6_29_FN = 463,\n\tGP_6_30_FN = 464,\n\tGP_6_31_FN = 465,\n\tGP_7_0_FN = 466,\n\tGP_7_1_FN = 467,\n\tGP_7_2_FN = 468,\n\tGP_7_3_FN = 469,\n\tGP_7_4_FN = 470,\n\tGP_7_5_FN = 471,\n\tGP_7_6_FN = 472,\n\tGP_7_7_FN = 473,\n\tGP_7_8_FN = 474,\n\tGP_7_9_FN = 475,\n\tGP_7_10_FN = 476,\n\tGP_7_11_FN = 477,\n\tGP_7_12_FN = 478,\n\tGP_7_13_FN = 479,\n\tGP_7_14_FN = 480,\n\tGP_7_15_FN = 481,\n\tGP_7_16_FN = 482,\n\tGP_7_17_FN = 483,\n\tGP_7_18_FN = 484,\n\tGP_7_19_FN = 485,\n\tGP_7_20_FN = 486,\n\tGP_7_21_FN = 487,\n\tGP_7_22_FN = 488,\n\tGP_7_23_FN = 489,\n\tGP_7_24_FN = 490,\n\tGP_7_25_FN = 491,\n\tFN_IP0_0___2 = 492,\n\tFN_IP0_1 = 493,\n\tFN_IP0_2 = 494,\n\tFN_IP0_3 = 495,\n\tFN_IP0_4 = 496,\n\tFN_IP0_5 = 497,\n\tFN_IP0_6 = 498,\n\tFN_IP0_7 = 499,\n\tFN_IP0_8 = 500,\n\tFN_IP0_9 = 501,\n\tFN_IP0_10___2 = 502,\n\tFN_IP0_11___2 = 503,\n\tFN_IP0_12___2 = 504,\n\tFN_IP0_13___2 = 505,\n\tFN_IP0_14___2 = 506,\n\tFN_IP0_15___2 = 507,\n\tFN_IP0_18_16 = 508,\n\tFN_IP0_20_19 = 509,\n\tFN_IP0_22_21 = 510,\n\tFN_IP0_24_23 = 511,\n\tFN_IP0_26_25 = 512,\n\tFN_IP0_28_27 = 513,\n\tFN_IP0_30_29 = 514,\n\tFN_IP1_1_0___2 = 515,\n\tFN_IP1_3_2___2 = 516,\n\tFN_IP1_5_4___2 = 517,\n\tFN_IP1_7_6___2 = 518,\n\tFN_IP1_10_8___2 = 519,\n\tFN_IP1_13_11 = 520,\n\tFN_IP1_16_14 = 521,\n\tFN_IP1_19_17 = 522,\n\tFN_IP1_22_20 = 523,\n\tFN_IP1_25_23 = 524,\n\tFN_IP1_28_26 = 525,\n\tFN_IP1_31_29 = 526,\n\tFN_IP2_2_0 = 527,\n\tFN_IP2_4_3 = 528,\n\tFN_IP2_6_5 = 529,\n\tFN_IP2_9_7 = 530,\n\tFN_IP2_12_10 = 531,\n\tFN_IP2_15_13 = 532,\n\tFN_IP2_18_16 = 533,\n\tFN_IP2_20_19 = 534,\n\tFN_IP2_22_21 = 535,\n\tFN_EX_CS0_N___2 = 536,\n\tFN_IP2_24_23 = 537,\n\tFN_IP2_26_25 = 538,\n\tFN_IP2_29_27___2 = 539,\n\tFN_IP3_2_0 = 540,\n\tFN_IP3_5_3 = 541,\n\tFN_IP3_8_6 = 542,\n\tFN_RD_N___2 = 543,\n\tFN_IP3_11_9 = 544,\n\tFN_IP3_13_12 = 545,\n\tFN_IP3_15_14 = 546,\n\tFN_IP3_17_16 = 547,\n\tFN_IP3_19_18 = 548,\n\tFN_IP3_21_20 = 549,\n\tFN_IP3_27_25 = 550,\n\tFN_IP3_30_28 = 551,\n\tFN_IP4_1_0___2 = 552,\n\tFN_IP4_4_2___2 = 553,\n\tFN_IP4_7_5___2 = 554,\n\tFN_IP4_9_8___2 = 555,\n\tFN_IP4_12_10 = 556,\n\tFN_IP4_15_13 = 557,\n\tFN_IP4_18_16 = 558,\n\tFN_IP4_19 = 559,\n\tFN_IP4_20 = 560,\n\tFN_IP4_21 = 561,\n\tFN_IP4_23_22 = 562,\n\tFN_IP4_25_24 = 563,\n\tFN_IP4_27_26___2 = 564,\n\tFN_IP4_30_28 = 565,\n\tFN_IP5_2_0 = 566,\n\tFN_IP5_5_3 = 567,\n\tFN_IP5_8_6___2 = 568,\n\tFN_IP5_11_9___2 = 569,\n\tFN_IP5_14_12 = 570,\n\tFN_IP5_16_15 = 571,\n\tFN_IP5_19_17 = 572,\n\tFN_IP5_21_20___2 = 573,\n\tFN_IP5_23_22___2 = 574,\n\tFN_IP5_25_24___2 = 575,\n\tFN_IP5_28_26 = 576,\n\tFN_IP5_31_29 = 577,\n\tFN_AUDIO_CLKA___2 = 578,\n\tFN_IP6_2_0 = 579,\n\tFN_IP6_5_3 = 580,\n\tFN_IP6_7_6___2 = 581,\n\tFN_IP7_5_3___2 = 582,\n\tFN_IP7_8_6___2 = 583,\n\tFN_IP7_10_9 = 584,\n\tFN_IP7_12_11 = 585,\n\tFN_IP7_14_13 = 586,\n\tFN_IP7_16_15 = 587,\n\tFN_IP7_18_17 = 588,\n\tFN_IP7_20_19 = 589,\n\tFN_IP7_23_21___2 = 590,\n\tFN_IP7_26_24___2 = 591,\n\tFN_IP7_29_27___2 = 592,\n\tFN_IP8_2_0___2 = 593,\n\tFN_IP8_5_3___2 = 594,\n\tFN_IP8_8_6___2 = 595,\n\tFN_IP8_11_9___2 = 596,\n\tFN_IP8_14_12___2 = 597,\n\tFN_IP8_17_15 = 598,\n\tFN_IP8_20_18 = 599,\n\tFN_IP8_23_21 = 600,\n\tFN_IP8_25_24 = 601,\n\tFN_IP8_27_26 = 602,\n\tFN_IP8_30_28 = 603,\n\tFN_IP9_2_0___2 = 604,\n\tFN_IP9_5_3___2 = 605,\n\tFN_IP9_6 = 606,\n\tFN_IP9_7 = 607,\n\tFN_IP9_10_8 = 608,\n\tFN_IP9_11 = 609,\n\tFN_IP9_12 = 610,\n\tFN_IP9_15_13 = 611,\n\tFN_IP9_16 = 612,\n\tFN_IP9_18_17___2 = 613,\n\tFN_VI0_CLK___2 = 614,\n\tFN_IP9_20_19 = 615,\n\tFN_IP9_22_21 = 616,\n\tFN_IP9_24_23 = 617,\n\tFN_IP9_26_25 = 618,\n\tFN_VI0_DATA0_VI0_B0___2 = 619,\n\tFN_VI0_DATA1_VI0_B1___2 = 620,\n\tFN_VI0_DATA2_VI0_B2___2 = 621,\n\tFN_IP9_28_27 = 622,\n\tFN_VI0_DATA4_VI0_B4___2 = 623,\n\tFN_VI0_DATA5_VI0_B5___2 = 624,\n\tFN_VI0_DATA6_VI0_B6___2 = 625,\n\tFN_VI0_DATA7_VI0_B7___2 = 626,\n\tFN_IP9_31_29 = 627,\n\tFN_IP10_2_0___2 = 628,\n\tFN_IP10_5_3___2 = 629,\n\tFN_IP10_8_6___2 = 630,\n\tFN_IP10_11_9___2 = 631,\n\tFN_IP10_14_12___2 = 632,\n\tFN_IP10_16_15 = 633,\n\tFN_IP10_18_17 = 634,\n\tFN_IP10_21_19 = 635,\n\tFN_IP10_24_22 = 636,\n\tFN_IP10_26_25 = 637,\n\tFN_IP10_28_27 = 638,\n\tFN_IP10_31_29 = 639,\n\tFN_IP11_2_0___2 = 640,\n\tFN_IP11_5_3___2 = 641,\n\tFN_IP11_8_6 = 642,\n\tFN_IP15_1_0 = 643,\n\tFN_IP15_3_2 = 644,\n\tFN_IP15_5_4 = 645,\n\tFN_IP11_11_9 = 646,\n\tFN_IP11_14_12 = 647,\n\tFN_IP11_16_15 = 648,\n\tFN_IP11_18_17 = 649,\n\tFN_IP11_19 = 650,\n\tFN_IP11_20 = 651,\n\tFN_IP11_21 = 652,\n\tFN_IP11_22 = 653,\n\tFN_IP11_23 = 654,\n\tFN_IP11_24 = 655,\n\tFN_IP11_25 = 656,\n\tFN_IP11_26 = 657,\n\tFN_IP11_27 = 658,\n\tFN_IP11_29_28 = 659,\n\tFN_IP11_31_30 = 660,\n\tFN_IP12_1_0 = 661,\n\tFN_IP12_3_2 = 662,\n\tFN_IP12_6_4 = 663,\n\tFN_IP12_9_7 = 664,\n\tFN_IP12_12_10 = 665,\n\tFN_IP12_15_13 = 666,\n\tFN_IP12_17_16 = 667,\n\tFN_IP12_19_18 = 668,\n\tFN_IP12_21_20 = 669,\n\tFN_IP12_23_22 = 670,\n\tFN_IP12_26_24___2 = 671,\n\tFN_IP12_29_27___2 = 672,\n\tFN_IP13_2_0___2 = 673,\n\tFN_IP13_4_3 = 674,\n\tFN_IP13_6_5 = 675,\n\tFN_IP13_9_7 = 676,\n\tFN_IP3_24_22 = 677,\n\tFN_IP13_10 = 678,\n\tFN_IP13_11 = 679,\n\tFN_IP13_12 = 680,\n\tFN_IP13_13 = 681,\n\tFN_IP13_14 = 682,\n\tFN_IP13_15 = 683,\n\tFN_IP13_18_16 = 684,\n\tFN_IP13_21_19 = 685,\n\tFN_IP13_22 = 686,\n\tFN_IP13_24_23 = 687,\n\tFN_SD1_CLK___2 = 688,\n\tFN_IP13_25 = 689,\n\tFN_IP13_26 = 690,\n\tFN_IP13_27 = 691,\n\tFN_IP13_30_28 = 692,\n\tFN_IP14_1_0 = 693,\n\tFN_IP14_2 = 694,\n\tFN_IP14_3 = 695,\n\tFN_IP14_4 = 696,\n\tFN_IP14_5 = 697,\n\tFN_IP14_6 = 698,\n\tFN_IP14_7 = 699,\n\tFN_IP14_10_8 = 700,\n\tFN_IP14_13_11 = 701,\n\tFN_IP14_16_14 = 702,\n\tFN_IP14_19_17 = 703,\n\tFN_IP14_22_20 = 704,\n\tFN_IP14_25_23 = 705,\n\tFN_IP14_28_26 = 706,\n\tFN_IP14_31_29 = 707,\n\tFN_USB1_OVC___2 = 708,\n\tFN_DU0_DOTCLKIN___2 = 709,\n\tFN_IP15_17_15 = 710,\n\tFN_IP15_20_18 = 711,\n\tFN_IP15_23_21 = 712,\n\tFN_IP15_26_24 = 713,\n\tFN_IP15_29_27 = 714,\n\tFN_IP16_2_0 = 715,\n\tFN_IP16_5_3 = 716,\n\tFN_IP16_7_6 = 717,\n\tFN_IP16_9_8 = 718,\n\tFN_IP16_11_10 = 719,\n\tFN_IP6_9_8 = 720,\n\tFN_IP6_11_10 = 721,\n\tFN_IP6_13_12 = 722,\n\tFN_IP6_15_14 = 723,\n\tFN_IP6_18_16 = 724,\n\tFN_IP6_20_19 = 725,\n\tFN_IP6_23_21 = 726,\n\tFN_IP6_26_24 = 727,\n\tFN_IP6_29_27 = 728,\n\tFN_IP7_2_0___2 = 729,\n\tFN_IP15_8_6 = 730,\n\tFN_IP15_11_9 = 731,\n\tFN_IP15_14_12 = 732,\n\tFN_USB0_PWEN___2 = 733,\n\tFN_USB0_OVC___2 = 734,\n\tFN_USB1_PWEN___2 = 735,\n\tFN_D0___2 = 736,\n\tFN_D1___2 = 737,\n\tFN_D2___2 = 738,\n\tFN_D3___2 = 739,\n\tFN_D4___2 = 740,\n\tFN_D5___2 = 741,\n\tFN_D6___2 = 742,\n\tFN_D7___2 = 743,\n\tFN_D8___2 = 744,\n\tFN_D9___2 = 745,\n\tFN_D10___2 = 746,\n\tFN_D11___2 = 747,\n\tFN_D12___2 = 748,\n\tFN_D13___2 = 749,\n\tFN_D14___2 = 750,\n\tFN_D15___2 = 751,\n\tFN_A0___2 = 752,\n\tFN_ATAWR0_N_C = 753,\n\tFN_MSIOF0_SCK_B = 754,\n\tFN_I2C0_SCL_C___2 = 755,\n\tFN_PWM2_B___2 = 756,\n\tFN_A1___2 = 757,\n\tFN_MSIOF0_SYNC_B = 758,\n\tFN_A2___2 = 759,\n\tFN_MSIOF0_SS1_B = 760,\n\tFN_A3___2 = 761,\n\tFN_MSIOF0_SS2_B = 762,\n\tFN_A4___2 = 763,\n\tFN_MSIOF0_TXD_B = 764,\n\tFN_A5___2 = 765,\n\tFN_MSIOF0_RXD_B = 766,\n\tFN_A6___2 = 767,\n\tFN_MSIOF1_SCK___2 = 768,\n\tFN_A7___2 = 769,\n\tFN_MSIOF1_SYNC___2 = 770,\n\tFN_A8___2 = 771,\n\tFN_MSIOF1_SS1___2 = 772,\n\tFN_I2C0_SCL___2 = 773,\n\tFN_A9___2 = 774,\n\tFN_MSIOF1_SS2___2 = 775,\n\tFN_I2C0_SDA___2 = 776,\n\tFN_A10___2 = 777,\n\tFN_MSIOF1_TXD___2 = 778,\n\tFN_MSIOF1_TXD_D = 779,\n\tFN_A11___2 = 780,\n\tFN_MSIOF1_RXD___2 = 781,\n\tFN_I2C3_SCL_D___2 = 782,\n\tFN_MSIOF1_RXD_D = 783,\n\tFN_A12___2 = 784,\n\tFN_FMCLK___2 = 785,\n\tFN_I2C3_SDA_D___2 = 786,\n\tFN_MSIOF1_SCK_D = 787,\n\tFN_A13___2 = 788,\n\tFN_ATAG0_N_C = 789,\n\tFN_BPFCLK___2 = 790,\n\tFN_MSIOF1_SS1_D = 791,\n\tFN_A14___2 = 792,\n\tFN_ATADIR0_N_C = 793,\n\tFN_FMIN___2 = 794,\n\tFN_FMIN_C___2 = 795,\n\tFN_MSIOF1_SYNC_D = 796,\n\tFN_A15___2 = 797,\n\tFN_BPFCLK_C___2 = 798,\n\tFN_A16___2 = 799,\n\tFN_DREQ2_B = 800,\n\tFN_FMCLK_C___2 = 801,\n\tFN_SCIFA1_SCK_B___2 = 802,\n\tFN_A17___2 = 803,\n\tFN_DACK2_B = 804,\n\tFN_I2C0_SDA_C___2 = 805,\n\tFN_A18___2 = 806,\n\tFN_DREQ1 = 807,\n\tFN_SCIFA1_RXD_C___2 = 808,\n\tFN_SCIFB1_RXD_C = 809,\n\tFN_A19___2 = 810,\n\tFN_DACK1___2 = 811,\n\tFN_SCIFA1_TXD_C___2 = 812,\n\tFN_SCIFB1_TXD_C = 813,\n\tFN_SCIFB1_SCK_B = 814,\n\tFN_A20___2 = 815,\n\tFN_SPCLK___2 = 816,\n\tFN_A21___2 = 817,\n\tFN_ATAWR0_N_B = 818,\n\tFN_MOSI_IO0___2 = 819,\n\tFN_A22___2 = 820,\n\tFN_MISO_IO1___2 = 821,\n\tFN_FMCLK_B___2 = 822,\n\tFN_TX0 = 823,\n\tFN_SCIFA0_TXD___2 = 824,\n\tFN_A23___2 = 825,\n\tFN_IO2___2 = 826,\n\tFN_BPFCLK_B___2 = 827,\n\tFN_RX0 = 828,\n\tFN_SCIFA0_RXD___2 = 829,\n\tFN_A24___2 = 830,\n\tFN_DREQ2 = 831,\n\tFN_IO3___2 = 832,\n\tFN_TX1 = 833,\n\tFN_SCIFA1_TXD___2 = 834,\n\tFN_A25___2 = 835,\n\tFN_DACK2___2 = 836,\n\tFN_SSL___2 = 837,\n\tFN_DREQ1_C = 838,\n\tFN_RX1 = 839,\n\tFN_SCIFA1_RXD___2 = 840,\n\tFN_CS0_N___2 = 841,\n\tFN_ATAG0_N_B = 842,\n\tFN_I2C1_SCL___2 = 843,\n\tFN_CS1_N_A26___2 = 844,\n\tFN_ATADIR0_N_B = 845,\n\tFN_I2C1_SDA___2 = 846,\n\tFN_EX_CS1_N___2 = 847,\n\tFN_MSIOF2_SCK___2 = 848,\n\tFN_EX_CS2_N___2 = 849,\n\tFN_ATAWR0_N___2 = 850,\n\tFN_MSIOF2_SYNC___2 = 851,\n\tFN_EX_CS3_N___2 = 852,\n\tFN_ATADIR0_N___2 = 853,\n\tFN_MSIOF2_TXD___2 = 854,\n\tFN_ATAG0_N___2 = 855,\n\tFN_EX_WAIT1___2 = 856,\n\tFN_EX_CS4_N___2 = 857,\n\tFN_ATARD0_N___2 = 858,\n\tFN_MSIOF2_RXD___2 = 859,\n\tFN_EX_WAIT2___2 = 860,\n\tFN_EX_CS5_N___2 = 861,\n\tFN_ATACS00_N___2 = 862,\n\tFN_MSIOF2_SS1___2 = 863,\n\tFN_HRX1_B = 864,\n\tFN_SCIFB1_RXD_B = 865,\n\tFN_PWM1___2 = 866,\n\tFN_TPU_TO1 = 867,\n\tFN_BS_N___2 = 868,\n\tFN_ATACS10_N___2 = 869,\n\tFN_MSIOF2_SS2___2 = 870,\n\tFN_HTX1_B = 871,\n\tFN_SCIFB1_TXD_B = 872,\n\tFN_PWM2___2 = 873,\n\tFN_TPU_TO2 = 874,\n\tFN_RD_WR_N___2 = 875,\n\tFN_HRX2_B = 876,\n\tFN_FMIN_B___2 = 877,\n\tFN_SCIFB0_RXD_B = 878,\n\tFN_DREQ1_D = 879,\n\tFN_WE0_N___2 = 880,\n\tFN_HCTS2_N_B = 881,\n\tFN_SCIFB0_TXD_B = 882,\n\tFN_WE1_N___2 = 883,\n\tFN_ATARD0_N_B = 884,\n\tFN_HTX2_B = 885,\n\tFN_SCIFB0_RTS_N_B = 886,\n\tFN_EX_WAIT0___2 = 887,\n\tFN_HRTS2_N_B = 888,\n\tFN_SCIFB0_CTS_N_B = 889,\n\tFN_DREQ0 = 890,\n\tFN_PWM3___2 = 891,\n\tFN_TPU_TO3 = 892,\n\tFN_DACK0___2 = 893,\n\tFN_DRACK0___2 = 894,\n\tFN_REMOCON___2 = 895,\n\tFN_SPEEDIN___2 = 896,\n\tFN_HSCK0_C = 897,\n\tFN_HSCK2_C = 898,\n\tFN_SCIFB0_SCK_B = 899,\n\tFN_SCIFB2_SCK_B = 900,\n\tFN_DREQ2_C = 901,\n\tFN_HTX2_D = 902,\n\tFN_SSI_SCK0129___2 = 903,\n\tFN_HRX0_C = 904,\n\tFN_HRX2_C = 905,\n\tFN_SCIFB0_RXD_C = 906,\n\tFN_SCIFB2_RXD_C = 907,\n\tFN_SSI_WS0129___2 = 908,\n\tFN_HTX0_C = 909,\n\tFN_HTX2_C = 910,\n\tFN_SCIFB0_TXD_C = 911,\n\tFN_SCIFB2_TXD_C = 912,\n\tFN_SSI_SDATA0___2 = 913,\n\tFN_I2C0_SCL_B___2 = 914,\n\tFN_IIC0_SCL_B___2 = 915,\n\tFN_MSIOF2_SCK_C = 916,\n\tFN_SSI_SCK1___2 = 917,\n\tFN_I2C0_SDA_B___2 = 918,\n\tFN_IIC0_SDA_B___2 = 919,\n\tFN_MSIOF2_SYNC_C = 920,\n\tFN_GLO_I0_D = 921,\n\tFN_SSI_WS1___2 = 922,\n\tFN_I2C1_SCL_B___2 = 923,\n\tFN_IIC1_SCL_B = 924,\n\tFN_MSIOF2_TXD_C = 925,\n\tFN_GLO_I1_D = 926,\n\tFN_SSI_SDATA1___2 = 927,\n\tFN_I2C1_SDA_B___2 = 928,\n\tFN_IIC1_SDA_B = 929,\n\tFN_MSIOF2_RXD_C = 930,\n\tFN_SSI_SCK2___2 = 931,\n\tFN_I2C2_SCL___2 = 932,\n\tFN_GPS_CLK_B = 933,\n\tFN_GLO_Q0_D = 934,\n\tFN_HSCK1_E = 935,\n\tFN_SSI_WS2___2 = 936,\n\tFN_I2C2_SDA___2 = 937,\n\tFN_GPS_SIGN_B = 938,\n\tFN_RX2_E = 939,\n\tFN_GLO_Q1_D = 940,\n\tFN_HCTS1_N_E = 941,\n\tFN_SSI_SDATA2___2 = 942,\n\tFN_GPS_MAG_B = 943,\n\tFN_TX2_E = 944,\n\tFN_HRTS1_N_E = 945,\n\tFN_SSI_SCK34___2 = 946,\n\tFN_SSI_WS34___2 = 947,\n\tFN_SSI_SDATA3___2 = 948,\n\tFN_SSI_SCK4___2 = 949,\n\tFN_GLO_SS_D = 950,\n\tFN_SSI_WS4___2 = 951,\n\tFN_GLO_RFON_D = 952,\n\tFN_SSI_SDATA4___2 = 953,\n\tFN_MSIOF2_SCK_D = 954,\n\tFN_SSI_SCK5___2 = 955,\n\tFN_MSIOF1_SCK_C = 956,\n\tFN_TS_SDATA0 = 957,\n\tFN_GLO_I0 = 958,\n\tFN_MSIOF2_SYNC_D = 959,\n\tFN_VI1_R2_B = 960,\n\tFN_SSI_WS5___2 = 961,\n\tFN_MSIOF1_SYNC_C = 962,\n\tFN_TS_SCK0 = 963,\n\tFN_GLO_I1 = 964,\n\tFN_MSIOF2_TXD_D = 965,\n\tFN_VI1_R3_B = 966,\n\tFN_SSI_SDATA5___2 = 967,\n\tFN_MSIOF1_TXD_C = 968,\n\tFN_TS_SDEN0 = 969,\n\tFN_GLO_Q0 = 970,\n\tFN_MSIOF2_SS1_D = 971,\n\tFN_VI1_R4_B = 972,\n\tFN_SSI_SCK6___2 = 973,\n\tFN_MSIOF1_RXD_C = 974,\n\tFN_TS_SPSYNC0 = 975,\n\tFN_GLO_Q1 = 976,\n\tFN_MSIOF2_RXD_D = 977,\n\tFN_VI1_R5_B = 978,\n\tFN_SSI_WS6___2 = 979,\n\tFN_GLO_SCLK = 980,\n\tFN_MSIOF2_SS2_D = 981,\n\tFN_VI1_R6_B = 982,\n\tFN_SSI_SDATA6___2 = 983,\n\tFN_STP_IVCXO27_0_B = 984,\n\tFN_GLO_SDATA = 985,\n\tFN_VI1_R7_B = 986,\n\tFN_SSI_SCK78___2 = 987,\n\tFN_STP_ISCLK_0_B = 988,\n\tFN_GLO_SS = 989,\n\tFN_SSI_WS78___2 = 990,\n\tFN_TX0_D = 991,\n\tFN_STP_ISD_0_B = 992,\n\tFN_GLO_RFON = 993,\n\tFN_SSI_SDATA7___2 = 994,\n\tFN_RX0_D = 995,\n\tFN_STP_ISEN_0_B = 996,\n\tFN_SSI_SDATA8___2 = 997,\n\tFN_TX1_D = 998,\n\tFN_STP_ISSYNC_0_B = 999,\n\tFN_SSI_SCK9___2 = 1000,\n\tFN_RX1_D = 1001,\n\tFN_GLO_SCLK_D = 1002,\n\tFN_SSI_WS9___2 = 1003,\n\tFN_TX3_D = 1004,\n\tFN_CAN0_TX_D___2 = 1005,\n\tFN_GLO_SDATA_D = 1006,\n\tFN_SSI_SDATA9___2 = 1007,\n\tFN_RX3_D = 1008,\n\tFN_CAN0_RX_D___2 = 1009,\n\tFN_AUDIO_CLKB___2 = 1010,\n\tFN_STP_OPWM_0_B = 1011,\n\tFN_MSIOF1_SCK_B___2 = 1012,\n\tFN_SCIF_CLK___2 = 1013,\n\tFN_DVC_MUTE___2 = 1014,\n\tFN_BPFCLK_E___2 = 1015,\n\tFN_AUDIO_CLKC___2 = 1016,\n\tFN_SCIFB0_SCK_C = 1017,\n\tFN_MSIOF1_SYNC_B___2 = 1018,\n\tFN_RX2 = 1019,\n\tFN_SCIFA2_RXD___2 = 1020,\n\tFN_FMIN_E___2 = 1021,\n\tFN_AUDIO_CLKOUT___2 = 1022,\n\tFN_MSIOF1_SS1_B___2 = 1023,\n\tFN_TX2 = 1024,\n\tFN_SCIFA2_TXD___2 = 1025,\n\tFN_IRQ0___2 = 1026,\n\tFN_SCIFB1_RXD_D = 1027,\n\tFN_IRQ1___2 = 1028,\n\tFN_SCIFB1_SCK_C = 1029,\n\tFN_IRQ2___2 = 1030,\n\tFN_SCIFB1_TXD_D = 1031,\n\tFN_IRQ3___2 = 1032,\n\tFN_I2C4_SCL_C___2 = 1033,\n\tFN_MSIOF2_TXD_E = 1034,\n\tFN_IRQ4___2 = 1035,\n\tFN_HRX1_C = 1036,\n\tFN_I2C4_SDA_C___2 = 1037,\n\tFN_MSIOF2_RXD_E = 1038,\n\tFN_IRQ5___2 = 1039,\n\tFN_HTX1_C = 1040,\n\tFN_I2C1_SCL_E___2 = 1041,\n\tFN_MSIOF2_SCK_E = 1042,\n\tFN_IRQ6___2 = 1043,\n\tFN_HSCK1_C = 1044,\n\tFN_MSIOF1_SS2_B___2 = 1045,\n\tFN_I2C1_SDA_E___2 = 1046,\n\tFN_MSIOF2_SYNC_E = 1047,\n\tFN_IRQ7___2 = 1048,\n\tFN_HCTS1_N_C = 1049,\n\tFN_MSIOF1_TXD_B___2 = 1050,\n\tFN_GPS_CLK_C = 1051,\n\tFN_GPS_CLK_D = 1052,\n\tFN_IRQ8___2 = 1053,\n\tFN_HRTS1_N_C = 1054,\n\tFN_MSIOF1_RXD_B___2 = 1055,\n\tFN_GPS_SIGN_C = 1056,\n\tFN_GPS_SIGN_D = 1057,\n\tFN_IRQ9___2 = 1058,\n\tFN_DU1_DOTCLKIN_B = 1059,\n\tFN_CAN_CLK_D___2 = 1060,\n\tFN_GPS_MAG_C = 1061,\n\tFN_SCIF_CLK_B___2 = 1062,\n\tFN_GPS_MAG_D = 1063,\n\tFN_DU1_DR0___2 = 1064,\n\tFN_LCDOUT0___2 = 1065,\n\tFN_VI1_DATA0_B = 1066,\n\tFN_TX0_B = 1067,\n\tFN_SCIFA0_TXD_B___2 = 1068,\n\tFN_MSIOF2_SCK_B___2 = 1069,\n\tFN_DU1_DR1___2 = 1070,\n\tFN_LCDOUT1___2 = 1071,\n\tFN_VI1_DATA1_B = 1072,\n\tFN_RX0_B = 1073,\n\tFN_SCIFA0_RXD_B___2 = 1074,\n\tFN_MSIOF2_SYNC_B___2 = 1075,\n\tFN_DU1_DR2___2 = 1076,\n\tFN_LCDOUT2___2 = 1077,\n\tFN_SSI_SCK0129_B = 1078,\n\tFN_DU1_DR3___2 = 1079,\n\tFN_LCDOUT3___2 = 1080,\n\tFN_SSI_WS0129_B = 1081,\n\tFN_DU1_DR4___2 = 1082,\n\tFN_LCDOUT4___2 = 1083,\n\tFN_SSI_SDATA0_B = 1084,\n\tFN_DU1_DR5___2 = 1085,\n\tFN_LCDOUT5___2 = 1086,\n\tFN_SSI_SCK1_B___2 = 1087,\n\tFN_DU1_DR6___2 = 1088,\n\tFN_LCDOUT6___2 = 1089,\n\tFN_SSI_WS1_B___2 = 1090,\n\tFN_DU1_DR7___2 = 1091,\n\tFN_LCDOUT7___2 = 1092,\n\tFN_SSI_SDATA1_B___2 = 1093,\n\tFN_DU1_DG0___2 = 1094,\n\tFN_LCDOUT8___2 = 1095,\n\tFN_VI1_DATA2_B = 1096,\n\tFN_TX1_B = 1097,\n\tFN_SCIFA1_TXD_B___2 = 1098,\n\tFN_MSIOF2_SS1_B___2 = 1099,\n\tFN_DU1_DG1___2 = 1100,\n\tFN_LCDOUT9___2 = 1101,\n\tFN_VI1_DATA3_B = 1102,\n\tFN_RX1_B = 1103,\n\tFN_SCIFA1_RXD_B___2 = 1104,\n\tFN_MSIOF2_SS2_B___2 = 1105,\n\tFN_DU1_DG2___2 = 1106,\n\tFN_LCDOUT10___2 = 1107,\n\tFN_VI1_DATA4_B = 1108,\n\tFN_SCIF1_SCK_B___2 = 1109,\n\tFN_SCIFA1_SCK___2 = 1110,\n\tFN_SSI_SCK78_B___2 = 1111,\n\tFN_DU1_DG3___2 = 1112,\n\tFN_LCDOUT11___2 = 1113,\n\tFN_VI1_DATA5_B = 1114,\n\tFN_SSI_WS78_B___2 = 1115,\n\tFN_DU1_DG4___2 = 1116,\n\tFN_LCDOUT12___2 = 1117,\n\tFN_VI1_DATA6_B = 1118,\n\tFN_HRX0_B = 1119,\n\tFN_SCIFB2_RXD_B = 1120,\n\tFN_SSI_SDATA7_B___2 = 1121,\n\tFN_DU1_DG5___2 = 1122,\n\tFN_LCDOUT13___2 = 1123,\n\tFN_VI1_DATA7_B = 1124,\n\tFN_HCTS0_N_B = 1125,\n\tFN_SCIFB2_TXD_B = 1126,\n\tFN_SSI_SDATA8_B___2 = 1127,\n\tFN_DU1_DG6___2 = 1128,\n\tFN_LCDOUT14___2 = 1129,\n\tFN_HRTS0_N_B = 1130,\n\tFN_SCIFB2_CTS_N_B = 1131,\n\tFN_SSI_SCK9_B___2 = 1132,\n\tFN_DU1_DG7___2 = 1133,\n\tFN_LCDOUT15___2 = 1134,\n\tFN_HTX0_B = 1135,\n\tFN_SCIFB2_RTS_N_B = 1136,\n\tFN_SSI_WS9_B___2 = 1137,\n\tFN_DU1_DB0___2 = 1138,\n\tFN_LCDOUT16___2 = 1139,\n\tFN_VI1_CLK_B = 1140,\n\tFN_TX2_B = 1141,\n\tFN_SCIFA2_TXD_B___2 = 1142,\n\tFN_MSIOF2_TXD_B___2 = 1143,\n\tFN_DU1_DB1___2 = 1144,\n\tFN_LCDOUT17___2 = 1145,\n\tFN_VI1_HSYNC_N_B = 1146,\n\tFN_RX2_B = 1147,\n\tFN_SCIFA2_RXD_B___2 = 1148,\n\tFN_MSIOF2_RXD_B___2 = 1149,\n\tFN_DU1_DB2___2 = 1150,\n\tFN_LCDOUT18___2 = 1151,\n\tFN_VI1_VSYNC_N_B = 1152,\n\tFN_SCIF2_SCK_B___2 = 1153,\n\tFN_SCIFA2_SCK___2 = 1154,\n\tFN_SSI_SDATA9_B___2 = 1155,\n\tFN_DU1_DB3___2 = 1156,\n\tFN_LCDOUT19___2 = 1157,\n\tFN_VI1_CLKENB_B = 1158,\n\tFN_DU1_DB4___2 = 1159,\n\tFN_LCDOUT20___2 = 1160,\n\tFN_VI1_FIELD_B = 1161,\n\tFN_CAN1_RX___2 = 1162,\n\tFN_DU1_DB5___2 = 1163,\n\tFN_LCDOUT21___2 = 1164,\n\tFN_TX3 = 1165,\n\tFN_SCIFA3_TXD___2 = 1166,\n\tFN_CAN1_TX___2 = 1167,\n\tFN_DU1_DB6___2 = 1168,\n\tFN_LCDOUT22___2 = 1169,\n\tFN_I2C3_SCL_C___2 = 1170,\n\tFN_RX3 = 1171,\n\tFN_SCIFA3_RXD___2 = 1172,\n\tFN_DU1_DB7___2 = 1173,\n\tFN_LCDOUT23___2 = 1174,\n\tFN_I2C3_SDA_C___2 = 1175,\n\tFN_SCIF3_SCK___2 = 1176,\n\tFN_SCIFA3_SCK___2 = 1177,\n\tFN_DU1_DOTCLKIN___2 = 1178,\n\tFN_QSTVA_QVS___2 = 1179,\n\tFN_DU1_DOTCLKOUT0___2 = 1180,\n\tFN_QCLK___2 = 1181,\n\tFN_DU1_DOTCLKOUT1___2 = 1182,\n\tFN_QSTVB_QVE___2 = 1183,\n\tFN_CAN0_TX___2 = 1184,\n\tFN_TX3_B = 1185,\n\tFN_I2C2_SCL_B___2 = 1186,\n\tFN_PWM4___2 = 1187,\n\tFN_DU1_EXHSYNC_DU1_HSYNC___2 = 1188,\n\tFN_QSTH_QHS___2 = 1189,\n\tFN_DU1_EXVSYNC_DU1_VSYNC___2 = 1190,\n\tFN_QSTB_QHE___2 = 1191,\n\tFN_DU1_EXODDF_DU1_ODDF_DISP_CDE___2 = 1192,\n\tFN_QCPV_QDE___2 = 1193,\n\tFN_CAN0_RX___2 = 1194,\n\tFN_RX3_B = 1195,\n\tFN_I2C2_SDA_B___2 = 1196,\n\tFN_DU1_DISP___2 = 1197,\n\tFN_QPOLA___2 = 1198,\n\tFN_DU1_CDE___2 = 1199,\n\tFN_QPOLB___2 = 1200,\n\tFN_PWM4_B___2 = 1201,\n\tFN_VI0_CLKENB___2 = 1202,\n\tFN_TX4 = 1203,\n\tFN_SCIFA4_TXD___2 = 1204,\n\tFN_TS_SDATA0_D = 1205,\n\tFN_VI0_FIELD___2 = 1206,\n\tFN_RX4 = 1207,\n\tFN_SCIFA4_RXD___2 = 1208,\n\tFN_TS_SCK0_D = 1209,\n\tFN_VI0_HSYNC_N___2 = 1210,\n\tFN_TX5 = 1211,\n\tFN_SCIFA5_TXD___2 = 1212,\n\tFN_TS_SDEN0_D = 1213,\n\tFN_VI0_VSYNC_N___2 = 1214,\n\tFN_RX5 = 1215,\n\tFN_SCIFA5_RXD___2 = 1216,\n\tFN_TS_SPSYNC0_D = 1217,\n\tFN_VI0_DATA3_VI0_B3___2 = 1218,\n\tFN_SCIF3_SCK_B___2 = 1219,\n\tFN_SCIFA3_SCK_B___2 = 1220,\n\tFN_VI0_G0___2 = 1221,\n\tFN_IIC1_SCL = 1222,\n\tFN_STP_IVCXO27_0_C = 1223,\n\tFN_I2C4_SCL___2 = 1224,\n\tFN_HCTS2_N = 1225,\n\tFN_SCIFB2_CTS_N___2 = 1226,\n\tFN_ATAWR1_N___2 = 1227,\n\tFN_VI0_G1___2 = 1228,\n\tFN_IIC1_SDA = 1229,\n\tFN_STP_ISCLK_0_C = 1230,\n\tFN_I2C4_SDA___2 = 1231,\n\tFN_HRTS2_N = 1232,\n\tFN_SCIFB2_RTS_N___2 = 1233,\n\tFN_ATADIR1_N___2 = 1234,\n\tFN_VI0_G2___2 = 1235,\n\tFN_VI2_HSYNC_N = 1236,\n\tFN_STP_ISD_0_C = 1237,\n\tFN_I2C3_SCL_B___2 = 1238,\n\tFN_HSCK2 = 1239,\n\tFN_SCIFB2_SCK___2 = 1240,\n\tFN_ATARD1_N___2 = 1241,\n\tFN_VI0_G3___2 = 1242,\n\tFN_VI2_VSYNC_N = 1243,\n\tFN_STP_ISEN_0_C = 1244,\n\tFN_I2C3_SDA_B___2 = 1245,\n\tFN_HRX2 = 1246,\n\tFN_SCIFB2_RXD___2 = 1247,\n\tFN_ATACS01_N___2 = 1248,\n\tFN_VI0_G4___2 = 1249,\n\tFN_VI2_CLKENB = 1250,\n\tFN_STP_ISSYNC_0_C = 1251,\n\tFN_HTX2 = 1252,\n\tFN_SCIFB2_TXD___2 = 1253,\n\tFN_SCIFB0_SCK_D = 1254,\n\tFN_VI0_G5___2 = 1255,\n\tFN_VI2_FIELD = 1256,\n\tFN_STP_OPWM_0_C = 1257,\n\tFN_FMCLK_D___2 = 1258,\n\tFN_CAN0_TX_E = 1259,\n\tFN_HTX1_D = 1260,\n\tFN_SCIFB0_TXD_D = 1261,\n\tFN_VI0_G6___2 = 1262,\n\tFN_VI2_CLK = 1263,\n\tFN_BPFCLK_D___2 = 1264,\n\tFN_VI0_G7___2 = 1265,\n\tFN_VI2_DATA0 = 1266,\n\tFN_FMIN_D___2 = 1267,\n\tFN_VI0_R0___2 = 1268,\n\tFN_VI2_DATA1 = 1269,\n\tFN_GLO_I0_B = 1270,\n\tFN_TS_SDATA0_C = 1271,\n\tFN_ATACS11_N___2 = 1272,\n\tFN_VI0_R1___2 = 1273,\n\tFN_VI2_DATA2 = 1274,\n\tFN_GLO_I1_B = 1275,\n\tFN_TS_SCK0_C = 1276,\n\tFN_ATAG1_N___2 = 1277,\n\tFN_VI0_R2___2 = 1278,\n\tFN_VI2_DATA3 = 1279,\n\tFN_GLO_Q0_B = 1280,\n\tFN_TS_SDEN0_C = 1281,\n\tFN_VI0_R3___2 = 1282,\n\tFN_VI2_DATA4 = 1283,\n\tFN_GLO_Q1_B = 1284,\n\tFN_TS_SPSYNC0_C = 1285,\n\tFN_VI0_R4___2 = 1286,\n\tFN_VI2_DATA5 = 1287,\n\tFN_GLO_SCLK_B = 1288,\n\tFN_TX0_C = 1289,\n\tFN_I2C1_SCL_D___2 = 1290,\n\tFN_VI0_R5___2 = 1291,\n\tFN_VI2_DATA6 = 1292,\n\tFN_GLO_SDATA_B = 1293,\n\tFN_RX0_C = 1294,\n\tFN_I2C1_SDA_D___2 = 1295,\n\tFN_VI0_R6___2 = 1296,\n\tFN_VI2_DATA7 = 1297,\n\tFN_GLO_SS_B = 1298,\n\tFN_TX1_C = 1299,\n\tFN_I2C4_SCL_B___2 = 1300,\n\tFN_VI0_R7___2 = 1301,\n\tFN_GLO_RFON_B = 1302,\n\tFN_RX1_C = 1303,\n\tFN_CAN0_RX_E = 1304,\n\tFN_I2C4_SDA_B___2 = 1305,\n\tFN_HRX1_D = 1306,\n\tFN_SCIFB0_RXD_D = 1307,\n\tFN_VI1_HSYNC_N___2 = 1308,\n\tFN_AVB_RXD0___2 = 1309,\n\tFN_TS_SDATA0_B = 1310,\n\tFN_TX4_B = 1311,\n\tFN_SCIFA4_TXD_B___2 = 1312,\n\tFN_VI1_VSYNC_N___2 = 1313,\n\tFN_AVB_RXD1___2 = 1314,\n\tFN_TS_SCK0_B = 1315,\n\tFN_RX4_B = 1316,\n\tFN_SCIFA4_RXD_B___2 = 1317,\n\tFN_VI1_CLKENB___2 = 1318,\n\tFN_AVB_RXD2___2 = 1319,\n\tFN_TS_SDEN0_B = 1320,\n\tFN_VI1_FIELD___2 = 1321,\n\tFN_AVB_RXD3___2 = 1322,\n\tFN_TS_SPSYNC0_B = 1323,\n\tFN_VI1_CLK___2 = 1324,\n\tFN_AVB_RXD4___2 = 1325,\n\tFN_VI1_DATA0___2 = 1326,\n\tFN_AVB_RXD5___2 = 1327,\n\tFN_VI1_DATA1___2 = 1328,\n\tFN_AVB_RXD6___2 = 1329,\n\tFN_VI1_DATA2___2 = 1330,\n\tFN_AVB_RXD7___2 = 1331,\n\tFN_VI1_DATA3___2 = 1332,\n\tFN_AVB_RX_ER___2 = 1333,\n\tFN_VI1_DATA4___2 = 1334,\n\tFN_AVB_MDIO___2 = 1335,\n\tFN_VI1_DATA5___2 = 1336,\n\tFN_AVB_RX_DV___2 = 1337,\n\tFN_VI1_DATA6___2 = 1338,\n\tFN_AVB_MAGIC___2 = 1339,\n\tFN_VI1_DATA7___2 = 1340,\n\tFN_AVB_MDC___2 = 1341,\n\tFN_ETH_MDIO___2 = 1342,\n\tFN_AVB_RX_CLK___2 = 1343,\n\tFN_I2C2_SCL_C___2 = 1344,\n\tFN_ETH_CRS_DV___2 = 1345,\n\tFN_AVB_LINK___2 = 1346,\n\tFN_I2C2_SDA_C___2 = 1347,\n\tFN_ETH_RX_ER___2 = 1348,\n\tFN_AVB_CRS___2 = 1349,\n\tFN_I2C3_SCL___2 = 1350,\n\tFN_IIC0_SCL___2 = 1351,\n\tFN_ETH_RXD0___2 = 1352,\n\tFN_AVB_PHY_INT___2 = 1353,\n\tFN_I2C3_SDA___2 = 1354,\n\tFN_IIC0_SDA___2 = 1355,\n\tFN_ETH_RXD1___2 = 1356,\n\tFN_AVB_GTXREFCLK___2 = 1357,\n\tFN_CAN0_TX_C___2 = 1358,\n\tFN_I2C2_SCL_D___2 = 1359,\n\tFN_MSIOF1_RXD_E = 1360,\n\tFN_ETH_LINK___2 = 1361,\n\tFN_AVB_TXD0___2 = 1362,\n\tFN_CAN0_RX_C___2 = 1363,\n\tFN_I2C2_SDA_D___2 = 1364,\n\tFN_MSIOF1_SCK_E = 1365,\n\tFN_ETH_REFCLK___2 = 1366,\n\tFN_AVB_TXD1___2 = 1367,\n\tFN_SCIFA3_RXD_B___2 = 1368,\n\tFN_CAN1_RX_C___2 = 1369,\n\tFN_MSIOF1_SYNC_E = 1370,\n\tFN_ETH_TXD1___2 = 1371,\n\tFN_AVB_TXD2___2 = 1372,\n\tFN_SCIFA3_TXD_B___2 = 1373,\n\tFN_CAN1_TX_C___2 = 1374,\n\tFN_MSIOF1_TXD_E = 1375,\n\tFN_ETH_TX_EN___2 = 1376,\n\tFN_AVB_TXD3___2 = 1377,\n\tFN_TCLK1_B___2 = 1378,\n\tFN_CAN_CLK_B___2 = 1379,\n\tFN_ETH_MAGIC___2 = 1380,\n\tFN_AVB_TXD4___2 = 1381,\n\tFN_IETX_C___2 = 1382,\n\tFN_ETH_TXD0___2 = 1383,\n\tFN_AVB_TXD5___2 = 1384,\n\tFN_IECLK_C___2 = 1385,\n\tFN_ETH_MDC___2 = 1386,\n\tFN_AVB_TXD6___2 = 1387,\n\tFN_IERX_C___2 = 1388,\n\tFN_STP_IVCXO27_0 = 1389,\n\tFN_AVB_TXD7___2 = 1390,\n\tFN_SCIFB2_TXD_D = 1391,\n\tFN_ADIDATA_B___2 = 1392,\n\tFN_MSIOF0_SYNC_C = 1393,\n\tFN_STP_ISCLK_0 = 1394,\n\tFN_AVB_TX_EN___2 = 1395,\n\tFN_SCIFB2_RXD_D = 1396,\n\tFN_ADICS_SAMP_B___2 = 1397,\n\tFN_MSIOF0_SCK_C = 1398,\n\tFN_STP_ISD_0 = 1399,\n\tFN_AVB_TX_ER___2 = 1400,\n\tFN_SCIFB2_SCK_C = 1401,\n\tFN_ADICLK_B___2 = 1402,\n\tFN_MSIOF0_SS1_C = 1403,\n\tFN_STP_ISEN_0 = 1404,\n\tFN_AVB_TX_CLK___2 = 1405,\n\tFN_ADICHS0_B___2 = 1406,\n\tFN_MSIOF0_SS2_C = 1407,\n\tFN_STP_ISSYNC_0 = 1408,\n\tFN_AVB_COL___2 = 1409,\n\tFN_ADICHS1_B___2 = 1410,\n\tFN_MSIOF0_RXD_C = 1411,\n\tFN_STP_OPWM_0 = 1412,\n\tFN_AVB_GTX_CLK___2 = 1413,\n\tFN_PWM0_B___2 = 1414,\n\tFN_ADICHS2_B___2 = 1415,\n\tFN_MSIOF0_TXD_C = 1416,\n\tFN_SD0_CLK___2 = 1417,\n\tFN_SPCLK_B = 1418,\n\tFN_SD0_CMD___2 = 1419,\n\tFN_MOSI_IO0_B = 1420,\n\tFN_SD0_DATA0___2 = 1421,\n\tFN_MISO_IO1_B = 1422,\n\tFN_SD0_DATA1___2 = 1423,\n\tFN_IO2_B = 1424,\n\tFN_SD0_DATA2___2 = 1425,\n\tFN_IO3_B = 1426,\n\tFN_SD0_DATA3___2 = 1427,\n\tFN_SSL_B = 1428,\n\tFN_SD0_CD___2 = 1429,\n\tFN_MMC_D6_B = 1430,\n\tFN_SIM0_RST_B = 1431,\n\tFN_CAN0_RX_F = 1432,\n\tFN_SCIFA5_TXD_B___2 = 1433,\n\tFN_TX3_C = 1434,\n\tFN_SD0_WP___2 = 1435,\n\tFN_MMC_D7_B = 1436,\n\tFN_SIM0_D_B = 1437,\n\tFN_CAN0_TX_F = 1438,\n\tFN_SCIFA5_RXD_B___2 = 1439,\n\tFN_RX3_C = 1440,\n\tFN_SD1_CMD___2 = 1441,\n\tFN_REMOCON_B___2 = 1442,\n\tFN_SD1_DATA0___2 = 1443,\n\tFN_SPEEDIN_B___2 = 1444,\n\tFN_SD1_DATA1___2 = 1445,\n\tFN_IETX_B___2 = 1446,\n\tFN_SD1_DATA2___2 = 1447,\n\tFN_IECLK_B___2 = 1448,\n\tFN_SD1_DATA3___2 = 1449,\n\tFN_IERX_B___2 = 1450,\n\tFN_SD1_CD___2 = 1451,\n\tFN_PWM0___2 = 1452,\n\tFN_TPU_TO0 = 1453,\n\tFN_I2C1_SCL_C___2 = 1454,\n\tFN_SD1_WP___2 = 1455,\n\tFN_PWM1_B___2 = 1456,\n\tFN_I2C1_SDA_C___2 = 1457,\n\tFN_SD2_CLK___2 = 1458,\n\tFN_MMC_CLK___2 = 1459,\n\tFN_SD2_CMD___2 = 1460,\n\tFN_MMC_CMD___2 = 1461,\n\tFN_SD2_DATA0___2 = 1462,\n\tFN_MMC_D0___2 = 1463,\n\tFN_SD2_DATA1___2 = 1464,\n\tFN_MMC_D1___2 = 1465,\n\tFN_SD2_DATA2___2 = 1466,\n\tFN_MMC_D2___2 = 1467,\n\tFN_SD2_DATA3___2 = 1468,\n\tFN_MMC_D3___2 = 1469,\n\tFN_SD2_CD___2 = 1470,\n\tFN_MMC_D4___2 = 1471,\n\tFN_IIC1_SCL_C = 1472,\n\tFN_TX5_B = 1473,\n\tFN_SCIFA5_TXD_C___2 = 1474,\n\tFN_SD2_WP___2 = 1475,\n\tFN_MMC_D5___2 = 1476,\n\tFN_IIC1_SDA_C = 1477,\n\tFN_RX5_B = 1478,\n\tFN_SCIFA5_RXD_C___2 = 1479,\n\tFN_MSIOF0_SCK___2 = 1480,\n\tFN_RX2_C = 1481,\n\tFN_ADIDATA___2 = 1482,\n\tFN_VI1_CLK_C = 1483,\n\tFN_VI1_G0_B = 1484,\n\tFN_MSIOF0_SYNC___2 = 1485,\n\tFN_TX2_C = 1486,\n\tFN_ADICS_SAMP___2 = 1487,\n\tFN_VI1_CLKENB_C = 1488,\n\tFN_VI1_G1_B = 1489,\n\tFN_MSIOF0_TXD___2 = 1490,\n\tFN_ADICLK___2 = 1491,\n\tFN_VI1_FIELD_C = 1492,\n\tFN_VI1_G2_B = 1493,\n\tFN_MSIOF0_RXD___2 = 1494,\n\tFN_ADICHS0___2 = 1495,\n\tFN_VI1_DATA0_C = 1496,\n\tFN_VI1_G3_B = 1497,\n\tFN_MSIOF0_SS1___2 = 1498,\n\tFN_MMC_D6___2 = 1499,\n\tFN_ADICHS1___2 = 1500,\n\tFN_TX0_E = 1501,\n\tFN_VI1_HSYNC_N_C = 1502,\n\tFN_IIC0_SCL_C___2 = 1503,\n\tFN_VI1_G4_B = 1504,\n\tFN_MSIOF0_SS2___2 = 1505,\n\tFN_MMC_D7___2 = 1506,\n\tFN_ADICHS2___2 = 1507,\n\tFN_RX0_E = 1508,\n\tFN_VI1_VSYNC_N_C = 1509,\n\tFN_IIC0_SDA_C___2 = 1510,\n\tFN_VI1_G5_B = 1511,\n\tFN_SIM0_RST = 1512,\n\tFN_IETX___2 = 1513,\n\tFN_CAN1_TX_D___2 = 1514,\n\tFN_SIM0_CLK = 1515,\n\tFN_IECLK___2 = 1516,\n\tFN_CAN_CLK_C___2 = 1517,\n\tFN_SIM0_D = 1518,\n\tFN_IERX___2 = 1519,\n\tFN_CAN1_RX_D___2 = 1520,\n\tFN_GPS_CLK = 1521,\n\tFN_DU1_DOTCLKIN_C = 1522,\n\tFN_AUDIO_CLKB_B___2 = 1523,\n\tFN_PWM5_B___2 = 1524,\n\tFN_SCIFA3_TXD_C = 1525,\n\tFN_GPS_SIGN = 1526,\n\tFN_TX4_C = 1527,\n\tFN_SCIFA4_TXD_C___2 = 1528,\n\tFN_PWM5___2 = 1529,\n\tFN_VI1_G6_B = 1530,\n\tFN_SCIFA3_RXD_C = 1531,\n\tFN_GPS_MAG = 1532,\n\tFN_RX4_C = 1533,\n\tFN_SCIFA4_RXD_C___2 = 1534,\n\tFN_PWM6___2 = 1535,\n\tFN_VI1_G7_B = 1536,\n\tFN_SCIFA3_SCK_C = 1537,\n\tFN_HCTS0_N = 1538,\n\tFN_SCIFB0_CTS_N___2 = 1539,\n\tFN_GLO_I0_C = 1540,\n\tFN_TCLK1___2 = 1541,\n\tFN_VI1_DATA1_C = 1542,\n\tFN_HRTS0_N = 1543,\n\tFN_SCIFB0_RTS_N___2 = 1544,\n\tFN_GLO_I1_C = 1545,\n\tFN_VI1_DATA2_C = 1546,\n\tFN_HSCK0 = 1547,\n\tFN_SCIFB0_SCK___2 = 1548,\n\tFN_GLO_Q0_C = 1549,\n\tFN_CAN_CLK___2 = 1550,\n\tFN_TCLK2___2 = 1551,\n\tFN_VI1_DATA3_C = 1552,\n\tFN_HRX0 = 1553,\n\tFN_SCIFB0_RXD___2 = 1554,\n\tFN_GLO_Q1_C = 1555,\n\tFN_CAN0_RX_B___2 = 1556,\n\tFN_VI1_DATA4_C = 1557,\n\tFN_HTX0 = 1558,\n\tFN_SCIFB0_TXD___2 = 1559,\n\tFN_GLO_SCLK_C = 1560,\n\tFN_CAN0_TX_B___2 = 1561,\n\tFN_VI1_DATA5_C = 1562,\n\tFN_HRX1 = 1563,\n\tFN_SCIFB1_RXD___2 = 1564,\n\tFN_VI1_R0_B = 1565,\n\tFN_GLO_SDATA_C = 1566,\n\tFN_VI1_DATA6_C = 1567,\n\tFN_HTX1 = 1568,\n\tFN_SCIFB1_TXD___2 = 1569,\n\tFN_VI1_R1_B = 1570,\n\tFN_GLO_SS_C = 1571,\n\tFN_VI1_DATA7_C = 1572,\n\tFN_HSCK1 = 1573,\n\tFN_SCIFB1_SCK___2 = 1574,\n\tFN_MLB_CLK___2 = 1575,\n\tFN_GLO_RFON_C = 1576,\n\tFN_HCTS1_N = 1577,\n\tFN_SCIFB1_CTS_N = 1578,\n\tFN_MLB_SIG___2 = 1579,\n\tFN_CAN1_TX_B___2 = 1580,\n\tFN_HRTS1_N = 1581,\n\tFN_SCIFB1_RTS_N = 1582,\n\tFN_MLB_DAT___2 = 1583,\n\tFN_CAN1_RX_B___2 = 1584,\n\tFN_SEL_SCIF1_0___2 = 1585,\n\tFN_SEL_SCIF1_1___2 = 1586,\n\tFN_SEL_SCIF1_2___2 = 1587,\n\tFN_SEL_SCIF1_3 = 1588,\n\tFN_SEL_SCIFB_0 = 1589,\n\tFN_SEL_SCIFB_1 = 1590,\n\tFN_SEL_SCIFB_2 = 1591,\n\tFN_SEL_SCIFB_3 = 1592,\n\tFN_SEL_SCIFB2_0 = 1593,\n\tFN_SEL_SCIFB2_1 = 1594,\n\tFN_SEL_SCIFB2_2 = 1595,\n\tFN_SEL_SCIFB2_3 = 1596,\n\tFN_SEL_SCIFB1_0 = 1597,\n\tFN_SEL_SCIFB1_1 = 1598,\n\tFN_SEL_SCIFB1_2 = 1599,\n\tFN_SEL_SCIFB1_3 = 1600,\n\tFN_SEL_SCIFA1_0___2 = 1601,\n\tFN_SEL_SCIFA1_1___2 = 1602,\n\tFN_SEL_SCIFA1_2___2 = 1603,\n\tFN_SEL_SSI9_0___2 = 1604,\n\tFN_SEL_SSI9_1___2 = 1605,\n\tFN_SEL_SCFA_0 = 1606,\n\tFN_SEL_SCFA_1 = 1607,\n\tFN_SEL_QSP_0 = 1608,\n\tFN_SEL_QSP_1 = 1609,\n\tFN_SEL_SSI7_0___2 = 1610,\n\tFN_SEL_SSI7_1___2 = 1611,\n\tFN_SEL_HSCIF1_0___2 = 1612,\n\tFN_SEL_HSCIF1_1___2 = 1613,\n\tFN_SEL_HSCIF1_2 = 1614,\n\tFN_SEL_HSCIF1_3 = 1615,\n\tFN_SEL_HSCIF1_4 = 1616,\n\tFN_SEL_VI1_0 = 1617,\n\tFN_SEL_VI1_1 = 1618,\n\tFN_SEL_VI1_2 = 1619,\n\tFN_SEL_TMU1_0 = 1620,\n\tFN_SEL_TMU1_1 = 1621,\n\tFN_SEL_LBS_0___2 = 1622,\n\tFN_SEL_LBS_1___2 = 1623,\n\tFN_SEL_LBS_2 = 1624,\n\tFN_SEL_LBS_3 = 1625,\n\tFN_SEL_TSIF0_0___2 = 1626,\n\tFN_SEL_TSIF0_1___2 = 1627,\n\tFN_SEL_TSIF0_2___2 = 1628,\n\tFN_SEL_TSIF0_3___2 = 1629,\n\tFN_SEL_SOF0_0 = 1630,\n\tFN_SEL_SOF0_1 = 1631,\n\tFN_SEL_SOF0_2 = 1632,\n\tFN_SEL_SCIF0_0___2 = 1633,\n\tFN_SEL_SCIF0_1___2 = 1634,\n\tFN_SEL_SCIF0_2___2 = 1635,\n\tFN_SEL_SCIF0_3___2 = 1636,\n\tFN_SEL_SCIF0_4 = 1637,\n\tFN_SEL_SCIF_0 = 1638,\n\tFN_SEL_SCIF_1 = 1639,\n\tFN_SEL_CAN0_0___2 = 1640,\n\tFN_SEL_CAN0_1___2 = 1641,\n\tFN_SEL_CAN0_2___2 = 1642,\n\tFN_SEL_CAN0_3___2 = 1643,\n\tFN_SEL_CAN0_4 = 1644,\n\tFN_SEL_CAN0_5 = 1645,\n\tFN_SEL_CAN1_0___2 = 1646,\n\tFN_SEL_CAN1_1___2 = 1647,\n\tFN_SEL_CAN1_2___2 = 1648,\n\tFN_SEL_CAN1_3___2 = 1649,\n\tFN_SEL_SCIFA2_0___2 = 1650,\n\tFN_SEL_SCIFA2_1___2 = 1651,\n\tFN_SEL_SCIF4_0___2 = 1652,\n\tFN_SEL_SCIF4_1___2 = 1653,\n\tFN_SEL_SCIF4_2___2 = 1654,\n\tFN_SEL_ADG_0___2 = 1655,\n\tFN_SEL_ADG_1___2 = 1656,\n\tFN_SEL_FM_0 = 1657,\n\tFN_SEL_FM_1 = 1658,\n\tFN_SEL_FM_2 = 1659,\n\tFN_SEL_FM_3 = 1660,\n\tFN_SEL_FM_4 = 1661,\n\tFN_SEL_SCIFA5_0___2 = 1662,\n\tFN_SEL_SCIFA5_1___2 = 1663,\n\tFN_SEL_SCIFA5_2___2 = 1664,\n\tFN_SEL_GPS_0 = 1665,\n\tFN_SEL_GPS_1 = 1666,\n\tFN_SEL_GPS_2 = 1667,\n\tFN_SEL_GPS_3 = 1668,\n\tFN_SEL_SCIFA4_0___2 = 1669,\n\tFN_SEL_SCIFA4_1___2 = 1670,\n\tFN_SEL_SCIFA4_2___2 = 1671,\n\tFN_SEL_SCIFA3_0___2 = 1672,\n\tFN_SEL_SCIFA3_1___2 = 1673,\n\tFN_SEL_SCIFA3_2 = 1674,\n\tFN_SEL_SIM_0 = 1675,\n\tFN_SEL_SIM_1 = 1676,\n\tFN_SEL_SSI8_0___2 = 1677,\n\tFN_SEL_SSI8_1___2 = 1678,\n\tFN_SEL_HSCIF2_0 = 1679,\n\tFN_SEL_HSCIF2_1 = 1680,\n\tFN_SEL_HSCIF2_2 = 1681,\n\tFN_SEL_HSCIF2_3 = 1682,\n\tFN_SEL_CANCLK_0 = 1683,\n\tFN_SEL_CANCLK_1 = 1684,\n\tFN_SEL_CANCLK_2 = 1685,\n\tFN_SEL_CANCLK_3 = 1686,\n\tFN_SEL_IIC1_0 = 1687,\n\tFN_SEL_IIC1_1 = 1688,\n\tFN_SEL_IIC1_2 = 1689,\n\tFN_SEL_IIC0_0___2 = 1690,\n\tFN_SEL_IIC0_1___2 = 1691,\n\tFN_SEL_IIC0_2___2 = 1692,\n\tFN_SEL_I2C4_0 = 1693,\n\tFN_SEL_I2C4_1 = 1694,\n\tFN_SEL_I2C4_2 = 1695,\n\tFN_SEL_I2C3_0 = 1696,\n\tFN_SEL_I2C3_1 = 1697,\n\tFN_SEL_I2C3_2 = 1698,\n\tFN_SEL_I2C3_3 = 1699,\n\tFN_SEL_SCIF3_0___2 = 1700,\n\tFN_SEL_SCIF3_1___2 = 1701,\n\tFN_SEL_SCIF3_2 = 1702,\n\tFN_SEL_SCIF3_3 = 1703,\n\tFN_SEL_IEB_0___2 = 1704,\n\tFN_SEL_IEB_1___2 = 1705,\n\tFN_SEL_IEB_2___2 = 1706,\n\tFN_SEL_MMC_0 = 1707,\n\tFN_SEL_MMC_1 = 1708,\n\tFN_SEL_SCIF5_0___2 = 1709,\n\tFN_SEL_SCIF5_1___2 = 1710,\n\tFN_SEL_I2C2_0 = 1711,\n\tFN_SEL_I2C2_1 = 1712,\n\tFN_SEL_I2C2_2 = 1713,\n\tFN_SEL_I2C2_3 = 1714,\n\tFN_SEL_I2C1_0 = 1715,\n\tFN_SEL_I2C1_1 = 1716,\n\tFN_SEL_I2C1_2 = 1717,\n\tFN_SEL_I2C1_3 = 1718,\n\tFN_SEL_I2C1_4 = 1719,\n\tFN_SEL_I2C0_0 = 1720,\n\tFN_SEL_I2C0_1 = 1721,\n\tFN_SEL_I2C0_2 = 1722,\n\tFN_SEL_SOF1_0 = 1723,\n\tFN_SEL_SOF1_1 = 1724,\n\tFN_SEL_SOF1_2 = 1725,\n\tFN_SEL_SOF1_3 = 1726,\n\tFN_SEL_SOF1_4 = 1727,\n\tFN_SEL_HSCIF0_0___2 = 1728,\n\tFN_SEL_HSCIF0_1___2 = 1729,\n\tFN_SEL_HSCIF0_2 = 1730,\n\tFN_SEL_DIS_0 = 1731,\n\tFN_SEL_DIS_1 = 1732,\n\tFN_SEL_DIS_2 = 1733,\n\tFN_SEL_RAD_0___2 = 1734,\n\tFN_SEL_RAD_1___2 = 1735,\n\tFN_SEL_RCN_0___2 = 1736,\n\tFN_SEL_RCN_1___2 = 1737,\n\tFN_SEL_RSP_0___2 = 1738,\n\tFN_SEL_RSP_1___2 = 1739,\n\tFN_SEL_SCIF2_0___2 = 1740,\n\tFN_SEL_SCIF2_1___2 = 1741,\n\tFN_SEL_SCIF2_2___2 = 1742,\n\tFN_SEL_SCIF2_3 = 1743,\n\tFN_SEL_SCIF2_4 = 1744,\n\tFN_SEL_SOF2_0 = 1745,\n\tFN_SEL_SOF2_1 = 1746,\n\tFN_SEL_SOF2_2 = 1747,\n\tFN_SEL_SOF2_3 = 1748,\n\tFN_SEL_SOF2_4 = 1749,\n\tFN_SEL_SSI1_0___2 = 1750,\n\tFN_SEL_SSI1_1___2 = 1751,\n\tFN_SEL_SSI0_0 = 1752,\n\tFN_SEL_SSI0_1 = 1753,\n\tFN_SEL_SSP_0 = 1754,\n\tFN_SEL_SSP_1 = 1755,\n\tFN_SEL_SSP_2 = 1756,\n\tPINMUX_FUNCTION_END___3 = 1757,\n\tPINMUX_MARK_BEGIN___3 = 1758,\n\tEX_CS0_N_MARK___2 = 1759,\n\tRD_N_MARK___2 = 1760,\n\tAUDIO_CLKA_MARK___2 = 1761,\n\tVI0_CLK_MARK___2 = 1762,\n\tVI0_DATA0_VI0_B0_MARK___2 = 1763,\n\tVI0_DATA1_VI0_B1_MARK___2 = 1764,\n\tVI0_DATA2_VI0_B2_MARK___2 = 1765,\n\tVI0_DATA4_VI0_B4_MARK___2 = 1766,\n\tVI0_DATA5_VI0_B5_MARK___2 = 1767,\n\tVI0_DATA6_VI0_B6_MARK___2 = 1768,\n\tVI0_DATA7_VI0_B7_MARK___2 = 1769,\n\tSD1_CLK_MARK___2 = 1770,\n\tUSB0_PWEN_MARK___2 = 1771,\n\tUSB0_OVC_MARK___2 = 1772,\n\tUSB1_PWEN_MARK___2 = 1773,\n\tUSB1_OVC_MARK___2 = 1774,\n\tDU0_DOTCLKIN_MARK___2 = 1775,\n\tD0_MARK___2 = 1776,\n\tD1_MARK___2 = 1777,\n\tD2_MARK___2 = 1778,\n\tD3_MARK___2 = 1779,\n\tD4_MARK___2 = 1780,\n\tD5_MARK___2 = 1781,\n\tD6_MARK___2 = 1782,\n\tD7_MARK___2 = 1783,\n\tD8_MARK___2 = 1784,\n\tD9_MARK___2 = 1785,\n\tD10_MARK___2 = 1786,\n\tD11_MARK___2 = 1787,\n\tD12_MARK___2 = 1788,\n\tD13_MARK___2 = 1789,\n\tD14_MARK___2 = 1790,\n\tD15_MARK___2 = 1791,\n\tA0_MARK___3 = 1792,\n\tATAWR0_N_C_MARK = 1793,\n\tMSIOF0_SCK_B_MARK = 1794,\n\tI2C0_SCL_C_MARK___2 = 1795,\n\tPWM2_B_MARK___2 = 1796,\n\tA1_MARK___2 = 1797,\n\tMSIOF0_SYNC_B_MARK = 1798,\n\tA2_MARK___2 = 1799,\n\tMSIOF0_SS1_B_MARK = 1800,\n\tA3_MARK___2 = 1801,\n\tMSIOF0_SS2_B_MARK = 1802,\n\tA4_MARK___2 = 1803,\n\tMSIOF0_TXD_B_MARK = 1804,\n\tA5_MARK___2 = 1805,\n\tMSIOF0_RXD_B_MARK = 1806,\n\tA6_MARK___2 = 1807,\n\tMSIOF1_SCK_MARK___2 = 1808,\n\tA7_MARK___2 = 1809,\n\tMSIOF1_SYNC_MARK___2 = 1810,\n\tA8_MARK___2 = 1811,\n\tMSIOF1_SS1_MARK___3 = 1812,\n\tI2C0_SCL_MARK___2 = 1813,\n\tA9_MARK___2 = 1814,\n\tMSIOF1_SS2_MARK___3 = 1815,\n\tI2C0_SDA_MARK___2 = 1816,\n\tA10_MARK___2 = 1817,\n\tMSIOF1_TXD_MARK___3 = 1818,\n\tMSIOF1_TXD_D_MARK = 1819,\n\tA11_MARK___3 = 1820,\n\tMSIOF1_RXD_MARK___3 = 1821,\n\tI2C3_SCL_D_MARK___2 = 1822,\n\tMSIOF1_RXD_D_MARK = 1823,\n\tA12_MARK___3 = 1824,\n\tFMCLK_MARK___2 = 1825,\n\tI2C3_SDA_D_MARK___2 = 1826,\n\tMSIOF1_SCK_D_MARK = 1827,\n\tA13_MARK___3 = 1828,\n\tATAG0_N_C_MARK = 1829,\n\tBPFCLK_MARK___2 = 1830,\n\tMSIOF1_SS1_D_MARK = 1831,\n\tA14_MARK___3 = 1832,\n\tATADIR0_N_C_MARK = 1833,\n\tFMIN_MARK___2 = 1834,\n\tFMIN_C_MARK___2 = 1835,\n\tMSIOF1_SYNC_D_MARK = 1836,\n\tA15_MARK___3 = 1837,\n\tBPFCLK_C_MARK___2 = 1838,\n\tA16_MARK___3 = 1839,\n\tDREQ2_B_MARK = 1840,\n\tFMCLK_C_MARK___2 = 1841,\n\tSCIFA1_SCK_B_MARK___2 = 1842,\n\tA17_MARK___3 = 1843,\n\tDACK2_B_MARK = 1844,\n\tI2C0_SDA_C_MARK___2 = 1845,\n\tA18_MARK___3 = 1846,\n\tDREQ1_MARK___2 = 1847,\n\tSCIFA1_RXD_C_MARK___2 = 1848,\n\tSCIFB1_RXD_C_MARK = 1849,\n\tA19_MARK___3 = 1850,\n\tDACK1_MARK___3 = 1851,\n\tSCIFA1_TXD_C_MARK___2 = 1852,\n\tSCIFB1_TXD_C_MARK = 1853,\n\tSCIFB1_SCK_B_MARK = 1854,\n\tA20_MARK___3 = 1855,\n\tSPCLK_MARK___2 = 1856,\n\tA21_MARK___3 = 1857,\n\tATAWR0_N_B_MARK = 1858,\n\tMOSI_IO0_MARK___2 = 1859,\n\tA22_MARK___3 = 1860,\n\tMISO_IO1_MARK___2 = 1861,\n\tFMCLK_B_MARK___2 = 1862,\n\tTX0_MARK = 1863,\n\tSCIFA0_TXD_MARK___3 = 1864,\n\tA23_MARK___3 = 1865,\n\tIO2_MARK___2 = 1866,\n\tBPFCLK_B_MARK___2 = 1867,\n\tRX0_MARK = 1868,\n\tSCIFA0_RXD_MARK___3 = 1869,\n\tA24_MARK___3 = 1870,\n\tDREQ2_MARK___2 = 1871,\n\tIO3_MARK___2 = 1872,\n\tTX1_MARK = 1873,\n\tSCIFA1_TXD_MARK___3 = 1874,\n\tA25_MARK___3 = 1875,\n\tDACK2_MARK___3 = 1876,\n\tSSL_MARK___2 = 1877,\n\tDREQ1_C_MARK = 1878,\n\tRX1_MARK = 1879,\n\tSCIFA1_RXD_MARK___3 = 1880,\n\tCS0_N_MARK___2 = 1881,\n\tATAG0_N_B_MARK = 1882,\n\tI2C1_SCL_MARK___2 = 1883,\n\tCS1_N_A26_MARK___2 = 1884,\n\tATADIR0_N_B_MARK = 1885,\n\tI2C1_SDA_MARK___2 = 1886,\n\tEX_CS1_N_MARK___2 = 1887,\n\tMSIOF2_SCK_MARK___2 = 1888,\n\tEX_CS2_N_MARK___2 = 1889,\n\tATAWR0_N_MARK___2 = 1890,\n\tMSIOF2_SYNC_MARK___2 = 1891,\n\tEX_CS3_N_MARK___2 = 1892,\n\tATADIR0_N_MARK___2 = 1893,\n\tMSIOF2_TXD_MARK___3 = 1894,\n\tATAG0_N_MARK___2 = 1895,\n\tEX_WAIT1_MARK___2 = 1896,\n\tEX_CS4_N_MARK___2 = 1897,\n\tATARD0_N_MARK___2 = 1898,\n\tMSIOF2_RXD_MARK___2 = 1899,\n\tEX_WAIT2_MARK___2 = 1900,\n\tEX_CS5_N_MARK___2 = 1901,\n\tATACS00_N_MARK___2 = 1902,\n\tMSIOF2_SS1_MARK___2 = 1903,\n\tHRX1_B_MARK = 1904,\n\tSCIFB1_RXD_B_MARK = 1905,\n\tPWM1_MARK___2 = 1906,\n\tTPU_TO1_MARK = 1907,\n\tBS_N_MARK___2 = 1908,\n\tATACS10_N_MARK___2 = 1909,\n\tMSIOF2_SS2_MARK___2 = 1910,\n\tHTX1_B_MARK = 1911,\n\tSCIFB1_TXD_B_MARK = 1912,\n\tPWM2_MARK___2 = 1913,\n\tTPU_TO2_MARK = 1914,\n\tRD_WR_N_MARK___2 = 1915,\n\tHRX2_B_MARK = 1916,\n\tFMIN_B_MARK___2 = 1917,\n\tSCIFB0_RXD_B_MARK = 1918,\n\tDREQ1_D_MARK = 1919,\n\tWE0_N_MARK___2 = 1920,\n\tHCTS2_N_B_MARK = 1921,\n\tSCIFB0_TXD_B_MARK = 1922,\n\tWE1_N_MARK___2 = 1923,\n\tATARD0_N_B_MARK = 1924,\n\tHTX2_B_MARK = 1925,\n\tSCIFB0_RTS_N_B_MARK = 1926,\n\tEX_WAIT0_MARK___2 = 1927,\n\tHRTS2_N_B_MARK = 1928,\n\tSCIFB0_CTS_N_B_MARK = 1929,\n\tDREQ0_MARK___2 = 1930,\n\tPWM3_MARK___2 = 1931,\n\tTPU_TO3_MARK = 1932,\n\tDACK0_MARK___3 = 1933,\n\tDRACK0_MARK___2 = 1934,\n\tREMOCON_MARK___2 = 1935,\n\tSPEEDIN_MARK___2 = 1936,\n\tHSCK0_C_MARK = 1937,\n\tHSCK2_C_MARK = 1938,\n\tSCIFB0_SCK_B_MARK = 1939,\n\tSCIFB2_SCK_B_MARK = 1940,\n\tDREQ2_C_MARK = 1941,\n\tHTX2_D_MARK = 1942,\n\tSSI_SCK0129_MARK___2 = 1943,\n\tHRX0_C_MARK = 1944,\n\tHRX2_C_MARK = 1945,\n\tSCIFB0_RXD_C_MARK = 1946,\n\tSCIFB2_RXD_C_MARK = 1947,\n\tSSI_WS0129_MARK___2 = 1948,\n\tHTX0_C_MARK = 1949,\n\tHTX2_C_MARK = 1950,\n\tSCIFB0_TXD_C_MARK = 1951,\n\tSCIFB2_TXD_C_MARK = 1952,\n\tSSI_SDATA0_MARK___2 = 1953,\n\tI2C0_SCL_B_MARK___2 = 1954,\n\tIIC0_SCL_B_MARK___2 = 1955,\n\tMSIOF2_SCK_C_MARK = 1956,\n\tSSI_SCK1_MARK___2 = 1957,\n\tI2C0_SDA_B_MARK___2 = 1958,\n\tIIC0_SDA_B_MARK___2 = 1959,\n\tMSIOF2_SYNC_C_MARK = 1960,\n\tGLO_I0_D_MARK = 1961,\n\tSSI_WS1_MARK___2 = 1962,\n\tI2C1_SCL_B_MARK___2 = 1963,\n\tIIC1_SCL_B_MARK = 1964,\n\tMSIOF2_TXD_C_MARK = 1965,\n\tGLO_I1_D_MARK = 1966,\n\tSSI_SDATA1_MARK___2 = 1967,\n\tI2C1_SDA_B_MARK___2 = 1968,\n\tIIC1_SDA_B_MARK = 1969,\n\tMSIOF2_RXD_C_MARK = 1970,\n\tSSI_SCK2_MARK___2 = 1971,\n\tI2C2_SCL_MARK___2 = 1972,\n\tGPS_CLK_B_MARK = 1973,\n\tGLO_Q0_D_MARK = 1974,\n\tHSCK1_E_MARK = 1975,\n\tSSI_WS2_MARK___2 = 1976,\n\tI2C2_SDA_MARK___2 = 1977,\n\tGPS_SIGN_B_MARK = 1978,\n\tRX2_E_MARK = 1979,\n\tGLO_Q1_D_MARK = 1980,\n\tHCTS1_N_E_MARK = 1981,\n\tSSI_SDATA2_MARK___2 = 1982,\n\tGPS_MAG_B_MARK = 1983,\n\tTX2_E_MARK = 1984,\n\tHRTS1_N_E_MARK = 1985,\n\tSSI_SCK34_MARK___2 = 1986,\n\tSSI_WS34_MARK___2 = 1987,\n\tSSI_SDATA3_MARK___2 = 1988,\n\tSSI_SCK4_MARK___2 = 1989,\n\tGLO_SS_D_MARK = 1990,\n\tSSI_WS4_MARK___2 = 1991,\n\tGLO_RFON_D_MARK = 1992,\n\tSSI_SDATA4_MARK___2 = 1993,\n\tMSIOF2_SCK_D_MARK = 1994,\n\tSSI_SCK5_MARK___2 = 1995,\n\tMSIOF1_SCK_C_MARK = 1996,\n\tTS_SDATA0_MARK = 1997,\n\tGLO_I0_MARK = 1998,\n\tMSIOF2_SYNC_D_MARK = 1999,\n\tVI1_R2_B_MARK = 2000,\n\tSSI_WS5_MARK___2 = 2001,\n\tMSIOF1_SYNC_C_MARK = 2002,\n\tTS_SCK0_MARK = 2003,\n\tGLO_I1_MARK = 2004,\n\tMSIOF2_TXD_D_MARK = 2005,\n\tVI1_R3_B_MARK = 2006,\n\tSSI_SDATA5_MARK___2 = 2007,\n\tMSIOF1_TXD_C_MARK = 2008,\n\tTS_SDEN0_MARK = 2009,\n\tGLO_Q0_MARK = 2010,\n\tMSIOF2_SS1_D_MARK = 2011,\n\tVI1_R4_B_MARK = 2012,\n\tSSI_SCK6_MARK___2 = 2013,\n\tMSIOF1_RXD_C_MARK = 2014,\n\tTS_SPSYNC0_MARK = 2015,\n\tGLO_Q1_MARK = 2016,\n\tMSIOF2_RXD_D_MARK = 2017,\n\tVI1_R5_B_MARK = 2018,\n\tSSI_WS6_MARK___2 = 2019,\n\tGLO_SCLK_MARK = 2020,\n\tMSIOF2_SS2_D_MARK = 2021,\n\tVI1_R6_B_MARK = 2022,\n\tSSI_SDATA6_MARK___2 = 2023,\n\tSTP_IVCXO27_0_B_MARK = 2024,\n\tGLO_SDATA_MARK = 2025,\n\tVI1_R7_B_MARK = 2026,\n\tSSI_SCK78_MARK___2 = 2027,\n\tSTP_ISCLK_0_B_MARK = 2028,\n\tGLO_SS_MARK = 2029,\n\tSSI_WS78_MARK___2 = 2030,\n\tTX0_D_MARK = 2031,\n\tSTP_ISD_0_B_MARK = 2032,\n\tGLO_RFON_MARK = 2033,\n\tSSI_SDATA7_MARK___2 = 2034,\n\tRX0_D_MARK = 2035,\n\tSTP_ISEN_0_B_MARK = 2036,\n\tSSI_SDATA8_MARK___2 = 2037,\n\tTX1_D_MARK = 2038,\n\tSTP_ISSYNC_0_B_MARK = 2039,\n\tSSI_SCK9_MARK___2 = 2040,\n\tRX1_D_MARK = 2041,\n\tGLO_SCLK_D_MARK = 2042,\n\tSSI_WS9_MARK___2 = 2043,\n\tTX3_D_MARK = 2044,\n\tCAN0_TX_D_MARK___2 = 2045,\n\tGLO_SDATA_D_MARK = 2046,\n\tSSI_SDATA9_MARK___2 = 2047,\n\tRX3_D_MARK = 2048,\n\tCAN0_RX_D_MARK___2 = 2049,\n\tAUDIO_CLKB_MARK___2 = 2050,\n\tSTP_OPWM_0_B_MARK = 2051,\n\tMSIOF1_SCK_B_MARK___2 = 2052,\n\tSCIF_CLK_MARK___2 = 2053,\n\tDVC_MUTE_MARK___2 = 2054,\n\tBPFCLK_E_MARK___2 = 2055,\n\tAUDIO_CLKC_MARK___2 = 2056,\n\tSCIFB0_SCK_C_MARK = 2057,\n\tMSIOF1_SYNC_B_MARK___2 = 2058,\n\tRX2_MARK = 2059,\n\tSCIFA2_RXD_MARK___2 = 2060,\n\tFMIN_E_MARK___2 = 2061,\n\tAUDIO_CLKOUT_MARK___2 = 2062,\n\tMSIOF1_SS1_B_MARK___2 = 2063,\n\tTX2_MARK = 2064,\n\tSCIFA2_TXD_MARK___2 = 2065,\n\tIRQ0_MARK___2 = 2066,\n\tSCIFB1_RXD_D_MARK = 2067,\n\tIRQ1_MARK___2 = 2068,\n\tSCIFB1_SCK_C_MARK = 2069,\n\tIRQ2_MARK___2 = 2070,\n\tSCIFB1_TXD_D_MARK = 2071,\n\tIRQ3_MARK___2 = 2072,\n\tI2C4_SCL_C_MARK___2 = 2073,\n\tMSIOF2_TXD_E_MARK = 2074,\n\tIRQ4_MARK___2 = 2075,\n\tHRX1_C_MARK = 2076,\n\tI2C4_SDA_C_MARK___2 = 2077,\n\tMSIOF2_RXD_E_MARK = 2078,\n\tIRQ5_MARK___2 = 2079,\n\tHTX1_C_MARK = 2080,\n\tI2C1_SCL_E_MARK___2 = 2081,\n\tMSIOF2_SCK_E_MARK = 2082,\n\tIRQ6_MARK___2 = 2083,\n\tHSCK1_C_MARK = 2084,\n\tMSIOF1_SS2_B_MARK___2 = 2085,\n\tI2C1_SDA_E_MARK___2 = 2086,\n\tMSIOF2_SYNC_E_MARK = 2087,\n\tIRQ7_MARK___2 = 2088,\n\tHCTS1_N_C_MARK = 2089,\n\tMSIOF1_TXD_B_MARK___2 = 2090,\n\tGPS_CLK_C_MARK = 2091,\n\tGPS_CLK_D_MARK = 2092,\n\tIRQ8_MARK___2 = 2093,\n\tHRTS1_N_C_MARK = 2094,\n\tMSIOF1_RXD_B_MARK___2 = 2095,\n\tGPS_SIGN_C_MARK = 2096,\n\tGPS_SIGN_D_MARK = 2097,\n\tIRQ9_MARK___2 = 2098,\n\tDU1_DOTCLKIN_B_MARK = 2099,\n\tCAN_CLK_D_MARK___2 = 2100,\n\tGPS_MAG_C_MARK = 2101,\n\tSCIF_CLK_B_MARK___2 = 2102,\n\tGPS_MAG_D_MARK = 2103,\n\tDU1_DR0_MARK___2 = 2104,\n\tLCDOUT0_MARK___2 = 2105,\n\tVI1_DATA0_B_MARK = 2106,\n\tTX0_B_MARK = 2107,\n\tSCIFA0_TXD_B_MARK___2 = 2108,\n\tMSIOF2_SCK_B_MARK___2 = 2109,\n\tDU1_DR1_MARK___2 = 2110,\n\tLCDOUT1_MARK___2 = 2111,\n\tVI1_DATA1_B_MARK = 2112,\n\tRX0_B_MARK = 2113,\n\tSCIFA0_RXD_B_MARK___2 = 2114,\n\tMSIOF2_SYNC_B_MARK___2 = 2115,\n\tDU1_DR2_MARK___2 = 2116,\n\tLCDOUT2_MARK___2 = 2117,\n\tSSI_SCK0129_B_MARK = 2118,\n\tDU1_DR3_MARK___2 = 2119,\n\tLCDOUT3_MARK___2 = 2120,\n\tSSI_WS0129_B_MARK = 2121,\n\tDU1_DR4_MARK___2 = 2122,\n\tLCDOUT4_MARK___2 = 2123,\n\tSSI_SDATA0_B_MARK = 2124,\n\tDU1_DR5_MARK___2 = 2125,\n\tLCDOUT5_MARK___2 = 2126,\n\tSSI_SCK1_B_MARK___2 = 2127,\n\tDU1_DR6_MARK___2 = 2128,\n\tLCDOUT6_MARK___2 = 2129,\n\tSSI_WS1_B_MARK___2 = 2130,\n\tDU1_DR7_MARK___2 = 2131,\n\tLCDOUT7_MARK___2 = 2132,\n\tSSI_SDATA1_B_MARK___2 = 2133,\n\tDU1_DG0_MARK___2 = 2134,\n\tLCDOUT8_MARK___2 = 2135,\n\tVI1_DATA2_B_MARK = 2136,\n\tTX1_B_MARK = 2137,\n\tSCIFA1_TXD_B_MARK___2 = 2138,\n\tMSIOF2_SS1_B_MARK___2 = 2139,\n\tDU1_DG1_MARK___2 = 2140,\n\tLCDOUT9_MARK___2 = 2141,\n\tVI1_DATA3_B_MARK = 2142,\n\tRX1_B_MARK = 2143,\n\tSCIFA1_RXD_B_MARK___2 = 2144,\n\tMSIOF2_SS2_B_MARK___2 = 2145,\n\tDU1_DG2_MARK___2 = 2146,\n\tLCDOUT10_MARK___2 = 2147,\n\tVI1_DATA4_B_MARK = 2148,\n\tSCIF1_SCK_B_MARK___2 = 2149,\n\tSCIFA1_SCK_MARK___3 = 2150,\n\tSSI_SCK78_B_MARK___2 = 2151,\n\tDU1_DG3_MARK___2 = 2152,\n\tLCDOUT11_MARK___2 = 2153,\n\tVI1_DATA5_B_MARK = 2154,\n\tSSI_WS78_B_MARK___2 = 2155,\n\tDU1_DG4_MARK___2 = 2156,\n\tLCDOUT12_MARK___2 = 2157,\n\tVI1_DATA6_B_MARK = 2158,\n\tHRX0_B_MARK = 2159,\n\tSCIFB2_RXD_B_MARK = 2160,\n\tSSI_SDATA7_B_MARK___2 = 2161,\n\tDU1_DG5_MARK___2 = 2162,\n\tLCDOUT13_MARK___2 = 2163,\n\tVI1_DATA7_B_MARK = 2164,\n\tHCTS0_N_B_MARK = 2165,\n\tSCIFB2_TXD_B_MARK = 2166,\n\tSSI_SDATA8_B_MARK___2 = 2167,\n\tDU1_DG6_MARK___2 = 2168,\n\tLCDOUT14_MARK___2 = 2169,\n\tHRTS0_N_B_MARK = 2170,\n\tSCIFB2_CTS_N_B_MARK = 2171,\n\tSSI_SCK9_B_MARK___2 = 2172,\n\tDU1_DG7_MARK___2 = 2173,\n\tLCDOUT15_MARK___2 = 2174,\n\tHTX0_B_MARK = 2175,\n\tSCIFB2_RTS_N_B_MARK = 2176,\n\tSSI_WS9_B_MARK___2 = 2177,\n\tDU1_DB0_MARK___2 = 2178,\n\tLCDOUT16_MARK___2 = 2179,\n\tVI1_CLK_B_MARK = 2180,\n\tTX2_B_MARK = 2181,\n\tSCIFA2_TXD_B_MARK___2 = 2182,\n\tMSIOF2_TXD_B_MARK___2 = 2183,\n\tDU1_DB1_MARK___2 = 2184,\n\tLCDOUT17_MARK___2 = 2185,\n\tVI1_HSYNC_N_B_MARK = 2186,\n\tRX2_B_MARK = 2187,\n\tSCIFA2_RXD_B_MARK___2 = 2188,\n\tMSIOF2_RXD_B_MARK___2 = 2189,\n\tDU1_DB2_MARK___2 = 2190,\n\tLCDOUT18_MARK___2 = 2191,\n\tVI1_VSYNC_N_B_MARK = 2192,\n\tSCIF2_SCK_B_MARK___2 = 2193,\n\tSCIFA2_SCK_MARK___2 = 2194,\n\tSSI_SDATA9_B_MARK___2 = 2195,\n\tDU1_DB3_MARK___2 = 2196,\n\tLCDOUT19_MARK___2 = 2197,\n\tVI1_CLKENB_B_MARK = 2198,\n\tDU1_DB4_MARK___2 = 2199,\n\tLCDOUT20_MARK___2 = 2200,\n\tVI1_FIELD_B_MARK = 2201,\n\tCAN1_RX_MARK___2 = 2202,\n\tDU1_DB5_MARK___2 = 2203,\n\tLCDOUT21_MARK___2 = 2204,\n\tTX3_MARK = 2205,\n\tSCIFA3_TXD_MARK___3 = 2206,\n\tCAN1_TX_MARK___2 = 2207,\n\tDU1_DB6_MARK___2 = 2208,\n\tLCDOUT22_MARK___2 = 2209,\n\tI2C3_SCL_C_MARK___2 = 2210,\n\tRX3_MARK = 2211,\n\tSCIFA3_RXD_MARK___3 = 2212,\n\tDU1_DB7_MARK___2 = 2213,\n\tLCDOUT23_MARK___2 = 2214,\n\tI2C3_SDA_C_MARK___2 = 2215,\n\tSCIF3_SCK_MARK___2 = 2216,\n\tSCIFA3_SCK_MARK___2 = 2217,\n\tDU1_DOTCLKIN_MARK___2 = 2218,\n\tQSTVA_QVS_MARK___2 = 2219,\n\tDU1_DOTCLKOUT0_MARK___2 = 2220,\n\tQCLK_MARK___2 = 2221,\n\tDU1_DOTCLKOUT1_MARK___2 = 2222,\n\tQSTVB_QVE_MARK___2 = 2223,\n\tCAN0_TX_MARK___2 = 2224,\n\tTX3_B_MARK = 2225,\n\tI2C2_SCL_B_MARK___2 = 2226,\n\tPWM4_MARK___2 = 2227,\n\tDU1_EXHSYNC_DU1_HSYNC_MARK___2 = 2228,\n\tQSTH_QHS_MARK___2 = 2229,\n\tDU1_EXVSYNC_DU1_VSYNC_MARK___2 = 2230,\n\tQSTB_QHE_MARK___2 = 2231,\n\tDU1_EXODDF_DU1_ODDF_DISP_CDE_MARK___2 = 2232,\n\tQCPV_QDE_MARK___2 = 2233,\n\tCAN0_RX_MARK___2 = 2234,\n\tRX3_B_MARK = 2235,\n\tI2C2_SDA_B_MARK___2 = 2236,\n\tDU1_DISP_MARK___2 = 2237,\n\tQPOLA_MARK___2 = 2238,\n\tDU1_CDE_MARK___2 = 2239,\n\tQPOLB_MARK___2 = 2240,\n\tPWM4_B_MARK___2 = 2241,\n\tVI0_CLKENB_MARK___2 = 2242,\n\tTX4_MARK = 2243,\n\tSCIFA4_TXD_MARK___3 = 2244,\n\tTS_SDATA0_D_MARK = 2245,\n\tVI0_FIELD_MARK___2 = 2246,\n\tRX4_MARK = 2247,\n\tSCIFA4_RXD_MARK___3 = 2248,\n\tTS_SCK0_D_MARK = 2249,\n\tVI0_HSYNC_N_MARK___2 = 2250,\n\tTX5_MARK = 2251,\n\tSCIFA5_TXD_MARK___2 = 2252,\n\tTS_SDEN0_D_MARK = 2253,\n\tVI0_VSYNC_N_MARK___2 = 2254,\n\tRX5_MARK = 2255,\n\tSCIFA5_RXD_MARK___2 = 2256,\n\tTS_SPSYNC0_D_MARK = 2257,\n\tVI0_DATA3_VI0_B3_MARK___2 = 2258,\n\tSCIF3_SCK_B_MARK___2 = 2259,\n\tSCIFA3_SCK_B_MARK___2 = 2260,\n\tVI0_G0_MARK___2 = 2261,\n\tIIC1_SCL_MARK = 2262,\n\tSTP_IVCXO27_0_C_MARK = 2263,\n\tI2C4_SCL_MARK___2 = 2264,\n\tHCTS2_N_MARK = 2265,\n\tSCIFB2_CTS_N_MARK___2 = 2266,\n\tATAWR1_N_MARK___2 = 2267,\n\tVI0_G1_MARK___2 = 2268,\n\tIIC1_SDA_MARK = 2269,\n\tSTP_ISCLK_0_C_MARK = 2270,\n\tI2C4_SDA_MARK___2 = 2271,\n\tHRTS2_N_MARK = 2272,\n\tSCIFB2_RTS_N_MARK___2 = 2273,\n\tATADIR1_N_MARK___2 = 2274,\n\tVI0_G2_MARK___2 = 2275,\n\tVI2_HSYNC_N_MARK = 2276,\n\tSTP_ISD_0_C_MARK = 2277,\n\tI2C3_SCL_B_MARK___2 = 2278,\n\tHSCK2_MARK = 2279,\n\tSCIFB2_SCK_MARK___2 = 2280,\n\tATARD1_N_MARK___2 = 2281,\n\tVI0_G3_MARK___2 = 2282,\n\tVI2_VSYNC_N_MARK = 2283,\n\tSTP_ISEN_0_C_MARK = 2284,\n\tI2C3_SDA_B_MARK___2 = 2285,\n\tHRX2_MARK = 2286,\n\tSCIFB2_RXD_MARK___2 = 2287,\n\tATACS01_N_MARK___2 = 2288,\n\tVI0_G4_MARK___2 = 2289,\n\tVI2_CLKENB_MARK = 2290,\n\tSTP_ISSYNC_0_C_MARK = 2291,\n\tHTX2_MARK = 2292,\n\tSCIFB2_TXD_MARK___2 = 2293,\n\tSCIFB0_SCK_D_MARK = 2294,\n\tVI0_G5_MARK___2 = 2295,\n\tVI2_FIELD_MARK = 2296,\n\tSTP_OPWM_0_C_MARK = 2297,\n\tFMCLK_D_MARK___2 = 2298,\n\tCAN0_TX_E_MARK = 2299,\n\tHTX1_D_MARK = 2300,\n\tSCIFB0_TXD_D_MARK = 2301,\n\tVI0_G6_MARK___2 = 2302,\n\tVI2_CLK_MARK = 2303,\n\tBPFCLK_D_MARK___2 = 2304,\n\tVI0_G7_MARK___2 = 2305,\n\tVI2_DATA0_MARK = 2306,\n\tFMIN_D_MARK___2 = 2307,\n\tVI0_R0_MARK___2 = 2308,\n\tVI2_DATA1_MARK = 2309,\n\tGLO_I0_B_MARK = 2310,\n\tTS_SDATA0_C_MARK = 2311,\n\tATACS11_N_MARK___2 = 2312,\n\tVI0_R1_MARK___2 = 2313,\n\tVI2_DATA2_MARK = 2314,\n\tGLO_I1_B_MARK = 2315,\n\tTS_SCK0_C_MARK = 2316,\n\tATAG1_N_MARK___2 = 2317,\n\tVI0_R2_MARK___2 = 2318,\n\tVI2_DATA3_MARK = 2319,\n\tGLO_Q0_B_MARK = 2320,\n\tTS_SDEN0_C_MARK = 2321,\n\tVI0_R3_MARK___2 = 2322,\n\tVI2_DATA4_MARK = 2323,\n\tGLO_Q1_B_MARK = 2324,\n\tTS_SPSYNC0_C_MARK = 2325,\n\tVI0_R4_MARK___2 = 2326,\n\tVI2_DATA5_MARK = 2327,\n\tGLO_SCLK_B_MARK = 2328,\n\tTX0_C_MARK = 2329,\n\tI2C1_SCL_D_MARK___2 = 2330,\n\tVI0_R5_MARK___2 = 2331,\n\tVI2_DATA6_MARK = 2332,\n\tGLO_SDATA_B_MARK = 2333,\n\tRX0_C_MARK = 2334,\n\tI2C1_SDA_D_MARK___2 = 2335,\n\tVI0_R6_MARK___2 = 2336,\n\tVI2_DATA7_MARK = 2337,\n\tGLO_SS_B_MARK = 2338,\n\tTX1_C_MARK = 2339,\n\tI2C4_SCL_B_MARK___2 = 2340,\n\tVI0_R7_MARK___2 = 2341,\n\tGLO_RFON_B_MARK = 2342,\n\tRX1_C_MARK = 2343,\n\tCAN0_RX_E_MARK = 2344,\n\tI2C4_SDA_B_MARK___2 = 2345,\n\tHRX1_D_MARK = 2346,\n\tSCIFB0_RXD_D_MARK = 2347,\n\tVI1_HSYNC_N_MARK___2 = 2348,\n\tAVB_RXD0_MARK___2 = 2349,\n\tTS_SDATA0_B_MARK = 2350,\n\tTX4_B_MARK = 2351,\n\tSCIFA4_TXD_B_MARK___2 = 2352,\n\tVI1_VSYNC_N_MARK___2 = 2353,\n\tAVB_RXD1_MARK___2 = 2354,\n\tTS_SCK0_B_MARK = 2355,\n\tRX4_B_MARK = 2356,\n\tSCIFA4_RXD_B_MARK___2 = 2357,\n\tVI1_CLKENB_MARK___2 = 2358,\n\tAVB_RXD2_MARK___2 = 2359,\n\tTS_SDEN0_B_MARK = 2360,\n\tVI1_FIELD_MARK___2 = 2361,\n\tAVB_RXD3_MARK___2 = 2362,\n\tTS_SPSYNC0_B_MARK = 2363,\n\tVI1_CLK_MARK___2 = 2364,\n\tAVB_RXD4_MARK___2 = 2365,\n\tVI1_DATA0_MARK___2 = 2366,\n\tAVB_RXD5_MARK___2 = 2367,\n\tVI1_DATA1_MARK___2 = 2368,\n\tAVB_RXD6_MARK___2 = 2369,\n\tVI1_DATA2_MARK___2 = 2370,\n\tAVB_RXD7_MARK___2 = 2371,\n\tVI1_DATA3_MARK___2 = 2372,\n\tAVB_RX_ER_MARK___2 = 2373,\n\tVI1_DATA4_MARK___2 = 2374,\n\tAVB_MDIO_MARK___2 = 2375,\n\tVI1_DATA5_MARK___2 = 2376,\n\tAVB_RX_DV_MARK___2 = 2377,\n\tVI1_DATA6_MARK___2 = 2378,\n\tAVB_MAGIC_MARK___2 = 2379,\n\tVI1_DATA7_MARK___2 = 2380,\n\tAVB_MDC_MARK___2 = 2381,\n\tETH_MDIO_MARK___2 = 2382,\n\tAVB_RX_CLK_MARK___2 = 2383,\n\tI2C2_SCL_C_MARK___2 = 2384,\n\tETH_CRS_DV_MARK___2 = 2385,\n\tAVB_LINK_MARK___2 = 2386,\n\tI2C2_SDA_C_MARK___2 = 2387,\n\tETH_RX_ER_MARK___2 = 2388,\n\tAVB_CRS_MARK___2 = 2389,\n\tI2C3_SCL_MARK___2 = 2390,\n\tIIC0_SCL_MARK___2 = 2391,\n\tETH_RXD0_MARK___2 = 2392,\n\tAVB_PHY_INT_MARK___2 = 2393,\n\tI2C3_SDA_MARK___2 = 2394,\n\tIIC0_SDA_MARK___2 = 2395,\n\tETH_RXD1_MARK___2 = 2396,\n\tAVB_GTXREFCLK_MARK___2 = 2397,\n\tCAN0_TX_C_MARK___2 = 2398,\n\tI2C2_SCL_D_MARK___2 = 2399,\n\tMSIOF1_RXD_E_MARK = 2400,\n\tETH_LINK_MARK___2 = 2401,\n\tAVB_TXD0_MARK___2 = 2402,\n\tCAN0_RX_C_MARK___2 = 2403,\n\tI2C2_SDA_D_MARK___2 = 2404,\n\tMSIOF1_SCK_E_MARK = 2405,\n\tETH_REFCLK_MARK___2 = 2406,\n\tAVB_TXD1_MARK___2 = 2407,\n\tSCIFA3_RXD_B_MARK___2 = 2408,\n\tCAN1_RX_C_MARK___2 = 2409,\n\tMSIOF1_SYNC_E_MARK = 2410,\n\tETH_TXD1_MARK___2 = 2411,\n\tAVB_TXD2_MARK___2 = 2412,\n\tSCIFA3_TXD_B_MARK___2 = 2413,\n\tCAN1_TX_C_MARK___2 = 2414,\n\tMSIOF1_TXD_E_MARK = 2415,\n\tETH_TX_EN_MARK___2 = 2416,\n\tAVB_TXD3_MARK___2 = 2417,\n\tTCLK1_B_MARK___2 = 2418,\n\tCAN_CLK_B_MARK___2 = 2419,\n\tETH_MAGIC_MARK___2 = 2420,\n\tAVB_TXD4_MARK___2 = 2421,\n\tIETX_C_MARK___2 = 2422,\n\tETH_TXD0_MARK___2 = 2423,\n\tAVB_TXD5_MARK___2 = 2424,\n\tIECLK_C_MARK___2 = 2425,\n\tETH_MDC_MARK___2 = 2426,\n\tAVB_TXD6_MARK___2 = 2427,\n\tIERX_C_MARK___2 = 2428,\n\tSTP_IVCXO27_0_MARK = 2429,\n\tAVB_TXD7_MARK___2 = 2430,\n\tSCIFB2_TXD_D_MARK = 2431,\n\tADIDATA_B_MARK___2 = 2432,\n\tMSIOF0_SYNC_C_MARK = 2433,\n\tSTP_ISCLK_0_MARK = 2434,\n\tAVB_TX_EN_MARK___2 = 2435,\n\tSCIFB2_RXD_D_MARK = 2436,\n\tADICS_SAMP_B_MARK___2 = 2437,\n\tMSIOF0_SCK_C_MARK = 2438,\n\tSTP_ISD_0_MARK = 2439,\n\tAVB_TX_ER_MARK___2 = 2440,\n\tSCIFB2_SCK_C_MARK = 2441,\n\tADICLK_B_MARK___2 = 2442,\n\tMSIOF0_SS1_C_MARK = 2443,\n\tSTP_ISEN_0_MARK = 2444,\n\tAVB_TX_CLK_MARK___2 = 2445,\n\tADICHS0_B_MARK___2 = 2446,\n\tMSIOF0_SS2_C_MARK = 2447,\n\tSTP_ISSYNC_0_MARK = 2448,\n\tAVB_COL_MARK___2 = 2449,\n\tADICHS1_B_MARK___2 = 2450,\n\tMSIOF0_RXD_C_MARK = 2451,\n\tSTP_OPWM_0_MARK = 2452,\n\tAVB_GTX_CLK_MARK___2 = 2453,\n\tPWM0_B_MARK___2 = 2454,\n\tADICHS2_B_MARK___2 = 2455,\n\tMSIOF0_TXD_C_MARK = 2456,\n\tSD0_CLK_MARK___2 = 2457,\n\tSPCLK_B_MARK = 2458,\n\tSD0_CMD_MARK___2 = 2459,\n\tMOSI_IO0_B_MARK = 2460,\n\tSD0_DATA0_MARK___2 = 2461,\n\tMISO_IO1_B_MARK = 2462,\n\tSD0_DATA1_MARK___2 = 2463,\n\tIO2_B_MARK = 2464,\n\tSD0_DATA2_MARK___2 = 2465,\n\tIO3_B_MARK = 2466,\n\tSD0_DATA3_MARK___2 = 2467,\n\tSSL_B_MARK = 2468,\n\tSD0_CD_MARK___2 = 2469,\n\tMMC_D6_B_MARK = 2470,\n\tSIM0_RST_B_MARK = 2471,\n\tCAN0_RX_F_MARK = 2472,\n\tSCIFA5_TXD_B_MARK___2 = 2473,\n\tTX3_C_MARK = 2474,\n\tSD0_WP_MARK___2 = 2475,\n\tMMC_D7_B_MARK = 2476,\n\tSIM0_D_B_MARK = 2477,\n\tCAN0_TX_F_MARK = 2478,\n\tSCIFA5_RXD_B_MARK___2 = 2479,\n\tRX3_C_MARK = 2480,\n\tSD1_CMD_MARK___2 = 2481,\n\tREMOCON_B_MARK___2 = 2482,\n\tSD1_DATA0_MARK___2 = 2483,\n\tSPEEDIN_B_MARK___2 = 2484,\n\tSD1_DATA1_MARK___2 = 2485,\n\tIETX_B_MARK___2 = 2486,\n\tSD1_DATA2_MARK___2 = 2487,\n\tIECLK_B_MARK___2 = 2488,\n\tSD1_DATA3_MARK___2 = 2489,\n\tIERX_B_MARK___2 = 2490,\n\tSD1_CD_MARK___2 = 2491,\n\tPWM0_MARK___2 = 2492,\n\tTPU_TO0_MARK = 2493,\n\tI2C1_SCL_C_MARK___2 = 2494,\n\tSD1_WP_MARK___2 = 2495,\n\tPWM1_B_MARK___2 = 2496,\n\tI2C1_SDA_C_MARK___2 = 2497,\n\tSD2_CLK_MARK___2 = 2498,\n\tMMC_CLK_MARK___2 = 2499,\n\tSD2_CMD_MARK___2 = 2500,\n\tMMC_CMD_MARK___2 = 2501,\n\tSD2_DATA0_MARK___2 = 2502,\n\tMMC_D0_MARK___2 = 2503,\n\tSD2_DATA1_MARK___2 = 2504,\n\tMMC_D1_MARK___2 = 2505,\n\tSD2_DATA2_MARK___2 = 2506,\n\tMMC_D2_MARK___2 = 2507,\n\tSD2_DATA3_MARK___2 = 2508,\n\tMMC_D3_MARK___2 = 2509,\n\tSD2_CD_MARK___2 = 2510,\n\tMMC_D4_MARK___2 = 2511,\n\tIIC1_SCL_C_MARK = 2512,\n\tTX5_B_MARK = 2513,\n\tSCIFA5_TXD_C_MARK___2 = 2514,\n\tSD2_WP_MARK___2 = 2515,\n\tMMC_D5_MARK___2 = 2516,\n\tIIC1_SDA_C_MARK = 2517,\n\tRX5_B_MARK = 2518,\n\tSCIFA5_RXD_C_MARK___2 = 2519,\n\tMSIOF0_SCK_MARK___2 = 2520,\n\tRX2_C_MARK = 2521,\n\tADIDATA_MARK___2 = 2522,\n\tVI1_CLK_C_MARK = 2523,\n\tVI1_G0_B_MARK = 2524,\n\tMSIOF0_SYNC_MARK___2 = 2525,\n\tTX2_C_MARK = 2526,\n\tADICS_SAMP_MARK___2 = 2527,\n\tVI1_CLKENB_C_MARK = 2528,\n\tVI1_G1_B_MARK = 2529,\n\tMSIOF0_TXD_MARK___3 = 2530,\n\tADICLK_MARK___2 = 2531,\n\tVI1_FIELD_C_MARK = 2532,\n\tVI1_G2_B_MARK = 2533,\n\tMSIOF0_RXD_MARK___3 = 2534,\n\tADICHS0_MARK___2 = 2535,\n\tVI1_DATA0_C_MARK = 2536,\n\tVI1_G3_B_MARK = 2537,\n\tMSIOF0_SS1_MARK___3 = 2538,\n\tMMC_D6_MARK___2 = 2539,\n\tADICHS1_MARK___2 = 2540,\n\tTX0_E_MARK = 2541,\n\tVI1_HSYNC_N_C_MARK = 2542,\n\tIIC0_SCL_C_MARK___2 = 2543,\n\tVI1_G4_B_MARK = 2544,\n\tMSIOF0_SS2_MARK___3 = 2545,\n\tMMC_D7_MARK___2 = 2546,\n\tADICHS2_MARK___2 = 2547,\n\tRX0_E_MARK = 2548,\n\tVI1_VSYNC_N_C_MARK = 2549,\n\tIIC0_SDA_C_MARK___2 = 2550,\n\tVI1_G5_B_MARK = 2551,\n\tSIM0_RST_MARK = 2552,\n\tIETX_MARK___2 = 2553,\n\tCAN1_TX_D_MARK___2 = 2554,\n\tSIM0_CLK_MARK = 2555,\n\tIECLK_MARK___2 = 2556,\n\tCAN_CLK_C_MARK___2 = 2557,\n\tSIM0_D_MARK = 2558,\n\tIERX_MARK___2 = 2559,\n\tCAN1_RX_D_MARK___2 = 2560,\n\tGPS_CLK_MARK = 2561,\n\tDU1_DOTCLKIN_C_MARK = 2562,\n\tAUDIO_CLKB_B_MARK___2 = 2563,\n\tPWM5_B_MARK___2 = 2564,\n\tSCIFA3_TXD_C_MARK = 2565,\n\tGPS_SIGN_MARK = 2566,\n\tTX4_C_MARK = 2567,\n\tSCIFA4_TXD_C_MARK___2 = 2568,\n\tPWM5_MARK___2 = 2569,\n\tVI1_G6_B_MARK = 2570,\n\tSCIFA3_RXD_C_MARK = 2571,\n\tGPS_MAG_MARK = 2572,\n\tRX4_C_MARK = 2573,\n\tSCIFA4_RXD_C_MARK___2 = 2574,\n\tPWM6_MARK___2 = 2575,\n\tVI1_G7_B_MARK = 2576,\n\tSCIFA3_SCK_C_MARK = 2577,\n\tHCTS0_N_MARK = 2578,\n\tSCIFB0_CTS_N_MARK___2 = 2579,\n\tGLO_I0_C_MARK = 2580,\n\tTCLK1_MARK___2 = 2581,\n\tVI1_DATA1_C_MARK = 2582,\n\tHRTS0_N_MARK = 2583,\n\tSCIFB0_RTS_N_MARK___2 = 2584,\n\tGLO_I1_C_MARK = 2585,\n\tVI1_DATA2_C_MARK = 2586,\n\tHSCK0_MARK = 2587,\n\tSCIFB0_SCK_MARK___2 = 2588,\n\tGLO_Q0_C_MARK = 2589,\n\tCAN_CLK_MARK___2 = 2590,\n\tTCLK2_MARK___2 = 2591,\n\tVI1_DATA3_C_MARK = 2592,\n\tHRX0_MARK = 2593,\n\tSCIFB0_RXD_MARK___2 = 2594,\n\tGLO_Q1_C_MARK = 2595,\n\tCAN0_RX_B_MARK___2 = 2596,\n\tVI1_DATA4_C_MARK = 2597,\n\tHTX0_MARK = 2598,\n\tSCIFB0_TXD_MARK___2 = 2599,\n\tGLO_SCLK_C_MARK = 2600,\n\tCAN0_TX_B_MARK___2 = 2601,\n\tVI1_DATA5_C_MARK = 2602,\n\tHRX1_MARK = 2603,\n\tSCIFB1_RXD_MARK___2 = 2604,\n\tVI1_R0_B_MARK = 2605,\n\tGLO_SDATA_C_MARK = 2606,\n\tVI1_DATA6_C_MARK = 2607,\n\tHTX1_MARK = 2608,\n\tSCIFB1_TXD_MARK___2 = 2609,\n\tVI1_R1_B_MARK = 2610,\n\tGLO_SS_C_MARK = 2611,\n\tVI1_DATA7_C_MARK = 2612,\n\tHSCK1_MARK = 2613,\n\tSCIFB1_SCK_MARK___2 = 2614,\n\tMLB_CLK_MARK___2 = 2615,\n\tGLO_RFON_C_MARK = 2616,\n\tHCTS1_N_MARK = 2617,\n\tSCIFB1_CTS_N_MARK = 2618,\n\tMLB_SIG_MARK___2 = 2619,\n\tCAN1_TX_B_MARK___2 = 2620,\n\tHRTS1_N_MARK = 2621,\n\tSCIFB1_RTS_N_MARK = 2622,\n\tMLB_DAT_MARK___2 = 2623,\n\tCAN1_RX_B_MARK___2 = 2624,\n\tPINMUX_MARK_END___3 = 2625,\n};\n\nenum {\n\tPINMUX_RESERVED___4 = 0,\n\tPINMUX_DATA_BEGIN___4 = 1,\n\tGP_0_0_DATA___3 = 2,\n\tGP_0_1_DATA___3 = 3,\n\tGP_0_2_DATA___3 = 4,\n\tGP_0_3_DATA___3 = 5,\n\tGP_0_4_DATA___3 = 6,\n\tGP_0_5_DATA___3 = 7,\n\tGP_0_6_DATA___3 = 8,\n\tGP_0_7_DATA___3 = 9,\n\tGP_0_8_DATA___3 = 10,\n\tGP_0_9_DATA___3 = 11,\n\tGP_0_10_DATA___3 = 12,\n\tGP_0_11_DATA___3 = 13,\n\tGP_0_12_DATA___3 = 14,\n\tGP_0_13_DATA___3 = 15,\n\tGP_0_14_DATA___3 = 16,\n\tGP_0_15_DATA___3 = 17,\n\tGP_0_16_DATA___3 = 18,\n\tGP_0_17_DATA___3 = 19,\n\tGP_0_18_DATA___3 = 20,\n\tGP_0_19_DATA___3 = 21,\n\tGP_0_20_DATA___3 = 22,\n\tGP_0_21_DATA___3 = 23,\n\tGP_0_22_DATA___3 = 24,\n\tGP_0_23_DATA___3 = 25,\n\tGP_0_24_DATA___3 = 26,\n\tGP_0_25_DATA___3 = 27,\n\tGP_0_26_DATA___3 = 28,\n\tGP_0_27_DATA___3 = 29,\n\tGP_0_28_DATA___3 = 30,\n\tGP_0_29_DATA___3 = 31,\n\tGP_0_30_DATA___3 = 32,\n\tGP_0_31_DATA___3 = 33,\n\tGP_1_0_DATA___3 = 34,\n\tGP_1_1_DATA___3 = 35,\n\tGP_1_2_DATA___3 = 36,\n\tGP_1_3_DATA___3 = 37,\n\tGP_1_4_DATA___3 = 38,\n\tGP_1_5_DATA___3 = 39,\n\tGP_1_6_DATA___3 = 40,\n\tGP_1_7_DATA___3 = 41,\n\tGP_1_8_DATA___3 = 42,\n\tGP_1_9_DATA___3 = 43,\n\tGP_1_10_DATA___3 = 44,\n\tGP_1_11_DATA___3 = 45,\n\tGP_1_12_DATA___3 = 46,\n\tGP_1_13_DATA___3 = 47,\n\tGP_1_14_DATA___3 = 48,\n\tGP_1_15_DATA___3 = 49,\n\tGP_1_16_DATA___3 = 50,\n\tGP_1_17_DATA___3 = 51,\n\tGP_1_18_DATA___3 = 52,\n\tGP_1_19_DATA___3 = 53,\n\tGP_1_20_DATA___3 = 54,\n\tGP_1_21_DATA___3 = 55,\n\tGP_1_22_DATA___3 = 56,\n\tGP_1_23_DATA___3 = 57,\n\tGP_1_24_DATA___3 = 58,\n\tGP_1_25_DATA___3 = 59,\n\tGP_1_26_DATA = 60,\n\tGP_1_27_DATA = 61,\n\tGP_1_28_DATA = 62,\n\tGP_1_29_DATA = 63,\n\tGP_1_30_DATA = 64,\n\tGP_1_31_DATA = 65,\n\tGP_2_0_DATA___3 = 66,\n\tGP_2_1_DATA___3 = 67,\n\tGP_2_2_DATA___3 = 68,\n\tGP_2_3_DATA___3 = 69,\n\tGP_2_4_DATA___3 = 70,\n\tGP_2_5_DATA___3 = 71,\n\tGP_2_6_DATA___3 = 72,\n\tGP_2_7_DATA___3 = 73,\n\tGP_2_8_DATA___3 = 74,\n\tGP_2_9_DATA___3 = 75,\n\tGP_2_10_DATA___3 = 76,\n\tGP_2_11_DATA___3 = 77,\n\tGP_2_12_DATA___3 = 78,\n\tGP_2_13_DATA___3 = 79,\n\tGP_2_14_DATA___3 = 80,\n\tGP_2_15_DATA___3 = 81,\n\tGP_2_16_DATA___3 = 82,\n\tGP_2_17_DATA___3 = 83,\n\tGP_2_18_DATA___3 = 84,\n\tGP_2_19_DATA___3 = 85,\n\tGP_2_20_DATA___3 = 86,\n\tGP_2_21_DATA___3 = 87,\n\tGP_2_22_DATA___3 = 88,\n\tGP_2_23_DATA___3 = 89,\n\tGP_2_24_DATA___3 = 90,\n\tGP_2_25_DATA___3 = 91,\n\tGP_2_26_DATA___3 = 92,\n\tGP_2_27_DATA___3 = 93,\n\tGP_2_28_DATA___3 = 94,\n\tGP_2_29_DATA___3 = 95,\n\tGP_2_30_DATA___3 = 96,\n\tGP_2_31_DATA___3 = 97,\n\tGP_3_0_DATA___3 = 98,\n\tGP_3_1_DATA___3 = 99,\n\tGP_3_2_DATA___3 = 100,\n\tGP_3_3_DATA___3 = 101,\n\tGP_3_4_DATA___3 = 102,\n\tGP_3_5_DATA___3 = 103,\n\tGP_3_6_DATA___3 = 104,\n\tGP_3_7_DATA___3 = 105,\n\tGP_3_8_DATA___3 = 106,\n\tGP_3_9_DATA___3 = 107,\n\tGP_3_10_DATA___3 = 108,\n\tGP_3_11_DATA___3 = 109,\n\tGP_3_12_DATA___3 = 110,\n\tGP_3_13_DATA___3 = 111,\n\tGP_3_14_DATA___3 = 112,\n\tGP_3_15_DATA___3 = 113,\n\tGP_3_16_DATA___3 = 114,\n\tGP_3_17_DATA___3 = 115,\n\tGP_3_18_DATA___3 = 116,\n\tGP_3_19_DATA___3 = 117,\n\tGP_3_20_DATA___3 = 118,\n\tGP_3_21_DATA___3 = 119,\n\tGP_3_22_DATA___3 = 120,\n\tGP_3_23_DATA___3 = 121,\n\tGP_3_24_DATA___3 = 122,\n\tGP_3_25_DATA___3 = 123,\n\tGP_3_26_DATA___3 = 124,\n\tGP_3_27_DATA___3 = 125,\n\tGP_3_28_DATA___3 = 126,\n\tGP_3_29_DATA___3 = 127,\n\tGP_3_30_DATA___3 = 128,\n\tGP_3_31_DATA___3 = 129,\n\tGP_4_0_DATA___3 = 130,\n\tGP_4_1_DATA___3 = 131,\n\tGP_4_2_DATA___3 = 132,\n\tGP_4_3_DATA___3 = 133,\n\tGP_4_4_DATA___3 = 134,\n\tGP_4_5_DATA___3 = 135,\n\tGP_4_6_DATA___3 = 136,\n\tGP_4_7_DATA___3 = 137,\n\tGP_4_8_DATA___3 = 138,\n\tGP_4_9_DATA___3 = 139,\n\tGP_4_10_DATA___3 = 140,\n\tGP_4_11_DATA___3 = 141,\n\tGP_4_12_DATA___3 = 142,\n\tGP_4_13_DATA___3 = 143,\n\tGP_4_14_DATA___3 = 144,\n\tGP_4_15_DATA___3 = 145,\n\tGP_4_16_DATA___3 = 146,\n\tGP_4_17_DATA___3 = 147,\n\tGP_4_18_DATA___3 = 148,\n\tGP_4_19_DATA___3 = 149,\n\tGP_4_20_DATA___3 = 150,\n\tGP_4_21_DATA___3 = 151,\n\tGP_4_22_DATA___3 = 152,\n\tGP_4_23_DATA___3 = 153,\n\tGP_4_24_DATA___3 = 154,\n\tGP_4_25_DATA___3 = 155,\n\tGP_4_26_DATA___3 = 156,\n\tGP_4_27_DATA___3 = 157,\n\tGP_4_28_DATA___3 = 158,\n\tGP_4_29_DATA___3 = 159,\n\tGP_4_30_DATA___3 = 160,\n\tGP_4_31_DATA___3 = 161,\n\tGP_5_0_DATA___3 = 162,\n\tGP_5_1_DATA___3 = 163,\n\tGP_5_2_DATA___3 = 164,\n\tGP_5_3_DATA___3 = 165,\n\tGP_5_4_DATA___3 = 166,\n\tGP_5_5_DATA___3 = 167,\n\tGP_5_6_DATA___3 = 168,\n\tGP_5_7_DATA___3 = 169,\n\tGP_5_8_DATA___3 = 170,\n\tGP_5_9_DATA___3 = 171,\n\tGP_5_10_DATA___3 = 172,\n\tGP_5_11_DATA___3 = 173,\n\tGP_5_12_DATA___3 = 174,\n\tGP_5_13_DATA___3 = 175,\n\tGP_5_14_DATA___3 = 176,\n\tGP_5_15_DATA___3 = 177,\n\tGP_5_16_DATA___3 = 178,\n\tGP_5_17_DATA___3 = 179,\n\tGP_5_18_DATA___3 = 180,\n\tGP_5_19_DATA___3 = 181,\n\tGP_5_20_DATA___3 = 182,\n\tGP_5_21_DATA___3 = 183,\n\tGP_5_22_DATA___3 = 184,\n\tGP_5_23_DATA___3 = 185,\n\tGP_5_24_DATA___3 = 186,\n\tGP_5_25_DATA___3 = 187,\n\tGP_5_26_DATA___3 = 188,\n\tGP_5_27_DATA___3 = 189,\n\tGP_5_28_DATA___2 = 190,\n\tGP_5_29_DATA___2 = 191,\n\tGP_5_30_DATA___2 = 192,\n\tGP_5_31_DATA___2 = 193,\n\tGP_6_0_DATA___3 = 194,\n\tGP_6_1_DATA___3 = 195,\n\tGP_6_2_DATA___3 = 196,\n\tGP_6_3_DATA___3 = 197,\n\tGP_6_4_DATA___3 = 198,\n\tGP_6_5_DATA___3 = 199,\n\tGP_6_6_DATA___3 = 200,\n\tGP_6_7_DATA___3 = 201,\n\tGP_6_8_DATA___3 = 202,\n\tPINMUX_DATA_END___4 = 203,\n\tPINMUX_FUNCTION_BEGIN___4 = 204,\n\tGP_0_0_FN___3 = 205,\n\tGP_0_1_FN___3 = 206,\n\tGP_0_2_FN___3 = 207,\n\tGP_0_3_FN___3 = 208,\n\tGP_0_4_FN___3 = 209,\n\tGP_0_5_FN___3 = 210,\n\tGP_0_6_FN___3 = 211,\n\tGP_0_7_FN___3 = 212,\n\tGP_0_8_FN___3 = 213,\n\tGP_0_9_FN___3 = 214,\n\tGP_0_10_FN___3 = 215,\n\tGP_0_11_FN___3 = 216,\n\tGP_0_12_FN___3 = 217,\n\tGP_0_13_FN___3 = 218,\n\tGP_0_14_FN___3 = 219,\n\tGP_0_15_FN___3 = 220,\n\tGP_0_16_FN___3 = 221,\n\tGP_0_17_FN___3 = 222,\n\tGP_0_18_FN___3 = 223,\n\tGP_0_19_FN___3 = 224,\n\tGP_0_20_FN___3 = 225,\n\tGP_0_21_FN___3 = 226,\n\tGP_0_22_FN___3 = 227,\n\tGP_0_23_FN___3 = 228,\n\tGP_0_24_FN___3 = 229,\n\tGP_0_25_FN___3 = 230,\n\tGP_0_26_FN___3 = 231,\n\tGP_0_27_FN___3 = 232,\n\tGP_0_28_FN___3 = 233,\n\tGP_0_29_FN___3 = 234,\n\tGP_0_30_FN___3 = 235,\n\tGP_0_31_FN___3 = 236,\n\tGP_1_0_FN___3 = 237,\n\tGP_1_1_FN___3 = 238,\n\tGP_1_2_FN___3 = 239,\n\tGP_1_3_FN___3 = 240,\n\tGP_1_4_FN___3 = 241,\n\tGP_1_5_FN___3 = 242,\n\tGP_1_6_FN___3 = 243,\n\tGP_1_7_FN___3 = 244,\n\tGP_1_8_FN___3 = 245,\n\tGP_1_9_FN___3 = 246,\n\tGP_1_10_FN___3 = 247,\n\tGP_1_11_FN___3 = 248,\n\tGP_1_12_FN___3 = 249,\n\tGP_1_13_FN___3 = 250,\n\tGP_1_14_FN___3 = 251,\n\tGP_1_15_FN___3 = 252,\n\tGP_1_16_FN___3 = 253,\n\tGP_1_17_FN___3 = 254,\n\tGP_1_18_FN___3 = 255,\n\tGP_1_19_FN___3 = 256,\n\tGP_1_20_FN___3 = 257,\n\tGP_1_21_FN___3 = 258,\n\tGP_1_22_FN___3 = 259,\n\tGP_1_23_FN___3 = 260,\n\tGP_1_24_FN___3 = 261,\n\tGP_1_25_FN___3 = 262,\n\tGP_1_26_FN = 263,\n\tGP_1_27_FN = 264,\n\tGP_1_28_FN = 265,\n\tGP_1_29_FN = 266,\n\tGP_1_30_FN = 267,\n\tGP_1_31_FN = 268,\n\tGP_2_0_FN___3 = 269,\n\tGP_2_1_FN___3 = 270,\n\tGP_2_2_FN___3 = 271,\n\tGP_2_3_FN___3 = 272,\n\tGP_2_4_FN___3 = 273,\n\tGP_2_5_FN___3 = 274,\n\tGP_2_6_FN___3 = 275,\n\tGP_2_7_FN___3 = 276,\n\tGP_2_8_FN___3 = 277,\n\tGP_2_9_FN___3 = 278,\n\tGP_2_10_FN___3 = 279,\n\tGP_2_11_FN___3 = 280,\n\tGP_2_12_FN___3 = 281,\n\tGP_2_13_FN___3 = 282,\n\tGP_2_14_FN___3 = 283,\n\tGP_2_15_FN___3 = 284,\n\tGP_2_16_FN___3 = 285,\n\tGP_2_17_FN___3 = 286,\n\tGP_2_18_FN___3 = 287,\n\tGP_2_19_FN___3 = 288,\n\tGP_2_20_FN___3 = 289,\n\tGP_2_21_FN___3 = 290,\n\tGP_2_22_FN___3 = 291,\n\tGP_2_23_FN___3 = 292,\n\tGP_2_24_FN___3 = 293,\n\tGP_2_25_FN___3 = 294,\n\tGP_2_26_FN___3 = 295,\n\tGP_2_27_FN___3 = 296,\n\tGP_2_28_FN___3 = 297,\n\tGP_2_29_FN___3 = 298,\n\tGP_2_30_FN___3 = 299,\n\tGP_2_31_FN___3 = 300,\n\tGP_3_0_FN___3 = 301,\n\tGP_3_1_FN___3 = 302,\n\tGP_3_2_FN___3 = 303,\n\tGP_3_3_FN___3 = 304,\n\tGP_3_4_FN___3 = 305,\n\tGP_3_5_FN___3 = 306,\n\tGP_3_6_FN___3 = 307,\n\tGP_3_7_FN___3 = 308,\n\tGP_3_8_FN___3 = 309,\n\tGP_3_9_FN___3 = 310,\n\tGP_3_10_FN___3 = 311,\n\tGP_3_11_FN___3 = 312,\n\tGP_3_12_FN___3 = 313,\n\tGP_3_13_FN___3 = 314,\n\tGP_3_14_FN___3 = 315,\n\tGP_3_15_FN___3 = 316,\n\tGP_3_16_FN___3 = 317,\n\tGP_3_17_FN___3 = 318,\n\tGP_3_18_FN___3 = 319,\n\tGP_3_19_FN___3 = 320,\n\tGP_3_20_FN___3 = 321,\n\tGP_3_21_FN___3 = 322,\n\tGP_3_22_FN___3 = 323,\n\tGP_3_23_FN___3 = 324,\n\tGP_3_24_FN___3 = 325,\n\tGP_3_25_FN___3 = 326,\n\tGP_3_26_FN___3 = 327,\n\tGP_3_27_FN___3 = 328,\n\tGP_3_28_FN___3 = 329,\n\tGP_3_29_FN___3 = 330,\n\tGP_3_30_FN___3 = 331,\n\tGP_3_31_FN___3 = 332,\n\tGP_4_0_FN___3 = 333,\n\tGP_4_1_FN___3 = 334,\n\tGP_4_2_FN___3 = 335,\n\tGP_4_3_FN___3 = 336,\n\tGP_4_4_FN___3 = 337,\n\tGP_4_5_FN___3 = 338,\n\tGP_4_6_FN___3 = 339,\n\tGP_4_7_FN___3 = 340,\n\tGP_4_8_FN___3 = 341,\n\tGP_4_9_FN___3 = 342,\n\tGP_4_10_FN___3 = 343,\n\tGP_4_11_FN___3 = 344,\n\tGP_4_12_FN___3 = 345,\n\tGP_4_13_FN___3 = 346,\n\tGP_4_14_FN___3 = 347,\n\tGP_4_15_FN___3 = 348,\n\tGP_4_16_FN___3 = 349,\n\tGP_4_17_FN___3 = 350,\n\tGP_4_18_FN___3 = 351,\n\tGP_4_19_FN___3 = 352,\n\tGP_4_20_FN___3 = 353,\n\tGP_4_21_FN___3 = 354,\n\tGP_4_22_FN___3 = 355,\n\tGP_4_23_FN___3 = 356,\n\tGP_4_24_FN___3 = 357,\n\tGP_4_25_FN___3 = 358,\n\tGP_4_26_FN___3 = 359,\n\tGP_4_27_FN___3 = 360,\n\tGP_4_28_FN___3 = 361,\n\tGP_4_29_FN___3 = 362,\n\tGP_4_30_FN___3 = 363,\n\tGP_4_31_FN___3 = 364,\n\tGP_5_0_FN___3 = 365,\n\tGP_5_1_FN___3 = 366,\n\tGP_5_2_FN___3 = 367,\n\tGP_5_3_FN___3 = 368,\n\tGP_5_4_FN___3 = 369,\n\tGP_5_5_FN___3 = 370,\n\tGP_5_6_FN___3 = 371,\n\tGP_5_7_FN___3 = 372,\n\tGP_5_8_FN___3 = 373,\n\tGP_5_9_FN___3 = 374,\n\tGP_5_10_FN___3 = 375,\n\tGP_5_11_FN___3 = 376,\n\tGP_5_12_FN___3 = 377,\n\tGP_5_13_FN___3 = 378,\n\tGP_5_14_FN___3 = 379,\n\tGP_5_15_FN___3 = 380,\n\tGP_5_16_FN___3 = 381,\n\tGP_5_17_FN___3 = 382,\n\tGP_5_18_FN___3 = 383,\n\tGP_5_19_FN___3 = 384,\n\tGP_5_20_FN___3 = 385,\n\tGP_5_21_FN___3 = 386,\n\tGP_5_22_FN___3 = 387,\n\tGP_5_23_FN___3 = 388,\n\tGP_5_24_FN___3 = 389,\n\tGP_5_25_FN___3 = 390,\n\tGP_5_26_FN___3 = 391,\n\tGP_5_27_FN___3 = 392,\n\tGP_5_28_FN___2 = 393,\n\tGP_5_29_FN___2 = 394,\n\tGP_5_30_FN___2 = 395,\n\tGP_5_31_FN___2 = 396,\n\tGP_6_0_FN___3 = 397,\n\tGP_6_1_FN___3 = 398,\n\tGP_6_2_FN___3 = 399,\n\tGP_6_3_FN___3 = 400,\n\tGP_6_4_FN___3 = 401,\n\tGP_6_5_FN___3 = 402,\n\tGP_6_6_FN___3 = 403,\n\tGP_6_7_FN___3 = 404,\n\tGP_6_8_FN___3 = 405,\n\tFN_AVS1 = 406,\n\tFN_AVS2 = 407,\n\tFN_IP0_7_6 = 408,\n\tFN_A17___3 = 409,\n\tFN_A18___3 = 410,\n\tFN_A19___3 = 411,\n\tFN_IP0_9_8___2 = 412,\n\tFN_IP0_11_10 = 413,\n\tFN_IP0_13_12 = 414,\n\tFN_IP0_15_14 = 415,\n\tFN_IP0_18_16___2 = 416,\n\tFN_IP0_22_19 = 417,\n\tFN_IP0_24_23___2 = 418,\n\tFN_IP0_25___2 = 419,\n\tFN_IP0_27_26___2 = 420,\n\tFN_IP1_1_0___3 = 421,\n\tFN_IP1_3_2___3 = 422,\n\tFN_IP1_6_4 = 423,\n\tFN_IP1_10_7 = 424,\n\tFN_IP1_14_11 = 425,\n\tFN_IP1_18_15 = 426,\n\tFN_IP0_5_3 = 427,\n\tFN_IP0_30_28 = 428,\n\tFN_IP2_18_16___2 = 429,\n\tFN_IP2_21_19 = 430,\n\tFN_IP2_30_28 = 431,\n\tFN_IP3_2_0___2 = 432,\n\tFN_IP3_11_9___2 = 433,\n\tFN_IP3_14_12 = 434,\n\tFN_IP3_22_21 = 435,\n\tFN_IP3_26_24___2 = 436,\n\tFN_IP3_31_29 = 437,\n\tFN_IP4_1_0___3 = 438,\n\tFN_IP4_4_2___3 = 439,\n\tFN_IP4_7_5___3 = 440,\n\tFN_IP4_10_8 = 441,\n\tFN_IP4_11 = 442,\n\tFN_IP4_12 = 443,\n\tFN_IP4_13 = 444,\n\tFN_IP4_14 = 445,\n\tFN_IP4_15 = 446,\n\tFN_IP4_16 = 447,\n\tFN_IP4_19_17 = 448,\n\tFN_IP4_22_20___2 = 449,\n\tFN_IP4_23 = 450,\n\tFN_IP4_24 = 451,\n\tFN_IP4_25 = 452,\n\tFN_IP4_26 = 453,\n\tFN_IP4_27 = 454,\n\tFN_IP4_28 = 455,\n\tFN_IP4_31_29 = 456,\n\tFN_IP5_2_0___2 = 457,\n\tFN_IP5_3 = 458,\n\tFN_IP5_4 = 459,\n\tFN_IP5_5 = 460,\n\tFN_IP5_6 = 461,\n\tFN_IP5_7 = 462,\n\tFN_IP5_8 = 463,\n\tFN_IP5_10_9 = 464,\n\tFN_IP5_12_11 = 465,\n\tFN_IP5_14_13 = 466,\n\tFN_IP5_16_15___2 = 467,\n\tFN_IP5_20_17 = 468,\n\tFN_IP5_23_21 = 469,\n\tFN_IP5_27_24 = 470,\n\tFN_IP8_20 = 471,\n\tFN_IP8_22_21 = 472,\n\tFN_IP8_24_23 = 473,\n\tFN_IP8_27_25 = 474,\n\tFN_IP8_30_28___2 = 475,\n\tFN_IP9_1_0 = 476,\n\tFN_IP9_3_2 = 477,\n\tFN_IP9_4 = 478,\n\tFN_IP9_5 = 479,\n\tFN_IP9_6___2 = 480,\n\tFN_IP9_7___2 = 481,\n\tFN_IP9_9_8 = 482,\n\tFN_IP9_11_10 = 483,\n\tFN_IP9_13_12 = 484,\n\tFN_IP9_15_14 = 485,\n\tFN_IP9_18_16 = 486,\n\tFN_IP9_21_19___2 = 487,\n\tFN_IP9_23_22 = 488,\n\tFN_IP9_25_24 = 489,\n\tFN_IP9_27_26 = 490,\n\tFN_IP9_29_28 = 491,\n\tFN_IP10_2_0___3 = 492,\n\tFN_IP10_5_3___3 = 493,\n\tFN_IP10_8_6___3 = 494,\n\tFN_IP10_11_9___3 = 495,\n\tFN_IP10_14_12___3 = 496,\n\tFN_IP10_17_15___2 = 497,\n\tFN_IP10_20_18___2 = 498,\n\tFN_IP10_23_21___2 = 499,\n\tFN_IP10_25_24 = 500,\n\tFN_IP10_28_26 = 501,\n\tFN_IP10_31_29___2 = 502,\n\tFN_IP11_2_0___3 = 503,\n\tFN_IP11_5_3___3 = 504,\n\tFN_IP11_8_6___2 = 505,\n\tFN_IP11_11_9___2 = 506,\n\tFN_IP11_14_12___2 = 507,\n\tFN_IP11_17_15 = 508,\n\tFN_IP11_20_18___2 = 509,\n\tFN_IP11_23_21___2 = 510,\n\tFN_IP11_26_24___2 = 511,\n\tFN_IP11_29_27___2 = 512,\n\tFN_IP12_2_0___2 = 513,\n\tFN_IP12_5_3___2 = 514,\n\tFN_IP12_8_6___2 = 515,\n\tFN_IP12_11_9 = 516,\n\tFN_IP12_14_12 = 517,\n\tFN_IP12_17_15___2 = 518,\n\tFN_IP7_16_15___2 = 519,\n\tFN_IP7_18_17___2 = 520,\n\tFN_IP7_28_27 = 521,\n\tFN_IP7_30_29 = 522,\n\tFN_IP7_20_19___2 = 523,\n\tFN_IP7_22_21 = 524,\n\tFN_IP7_24_23 = 525,\n\tFN_IP7_26_25 = 526,\n\tFN_IP1_20_19 = 527,\n\tFN_IP1_22_21 = 528,\n\tFN_IP1_24_23 = 529,\n\tFN_IP5_28 = 530,\n\tFN_IP5_30_29 = 531,\n\tFN_IP6_1_0___2 = 532,\n\tFN_IP6_3_2___2 = 533,\n\tFN_IP6_5_4___2 = 534,\n\tFN_IP6_7_6___3 = 535,\n\tFN_IP6_8___2 = 536,\n\tFN_IP6_11_9 = 537,\n\tFN_IP6_14_12 = 538,\n\tFN_IP6_17_15 = 539,\n\tFN_IP6_19_18 = 540,\n\tFN_IP6_22_20___2 = 541,\n\tFN_IP6_24_23 = 542,\n\tFN_IP6_26_25 = 543,\n\tFN_IP6_30_29 = 544,\n\tFN_IP7_1_0 = 545,\n\tFN_IP7_3_2 = 546,\n\tFN_IP7_6_4 = 547,\n\tFN_IP7_9_7 = 548,\n\tFN_IP7_12_10 = 549,\n\tFN_IP7_14_13___2 = 550,\n\tFN_IP2_7_4 = 551,\n\tFN_IP2_11_8 = 552,\n\tFN_IP2_15_12 = 553,\n\tFN_IP1_28_25 = 554,\n\tFN_IP2_3_0 = 555,\n\tFN_IP8_3_0 = 556,\n\tFN_IP8_7_4 = 557,\n\tFN_IP8_11_8 = 558,\n\tFN_IP8_15_12 = 559,\n\tFN_USB_PENC0 = 560,\n\tFN_USB_PENC1 = 561,\n\tFN_IP0_2_0 = 562,\n\tFN_IP8_17_16 = 563,\n\tFN_IP8_18 = 564,\n\tFN_IP8_19 = 565,\n\tFN_A1___3 = 566,\n\tFN_A2___3 = 567,\n\tFN_A3___3 = 568,\n\tFN_A4___3 = 569,\n\tFN_A5___3 = 570,\n\tFN_A6___3 = 571,\n\tFN_A7___3 = 572,\n\tFN_A8___3 = 573,\n\tFN_A9___3 = 574,\n\tFN_A10___3 = 575,\n\tFN_A11___3 = 576,\n\tFN_A12___3 = 577,\n\tFN_A13___3 = 578,\n\tFN_A14___3 = 579,\n\tFN_A15___3 = 580,\n\tFN_A16___3 = 581,\n\tFN_RD = 582,\n\tFN_WE0 = 583,\n\tFN_WE1 = 584,\n\tFN_EX_WAIT0___3 = 585,\n\tFN_IP3_23 = 586,\n\tFN_IP3_27 = 587,\n\tFN_IP3_28 = 588,\n\tFN_IP2_22 = 589,\n\tFN_IP2_23 = 590,\n\tFN_IP2_24 = 591,\n\tFN_IP2_25 = 592,\n\tFN_IP2_26 = 593,\n\tFN_IP2_27 = 594,\n\tFN_IP3_3 = 595,\n\tFN_IP3_4 = 596,\n\tFN_IP3_5 = 597,\n\tFN_IP3_6 = 598,\n\tFN_IP3_7 = 599,\n\tFN_IP3_8 = 600,\n\tFN_IP3_15 = 601,\n\tFN_IP3_16 = 602,\n\tFN_IP3_17 = 603,\n\tFN_IP3_18 = 604,\n\tFN_IP3_19 = 605,\n\tFN_IP3_20 = 606,\n\tFN_RD_WR = 607,\n\tFN_FWE = 608,\n\tFN_ATAG0 = 609,\n\tFN_VI1_R7 = 610,\n\tFN_HRTS1 = 611,\n\tFN_RX4_C___2 = 612,\n\tFN_CS1_A26 = 613,\n\tFN_HSPI_TX2 = 614,\n\tFN_SDSELF_B = 615,\n\tFN_CS0 = 616,\n\tFN_HSPI_CS2_B = 617,\n\tFN_CLKOUT = 618,\n\tFN_TX3C_IRDA_TX_C = 619,\n\tFN_PWM0_B___3 = 620,\n\tFN_A25___3 = 621,\n\tFN_SD1_WP___3 = 622,\n\tFN_MMC0_D5 = 623,\n\tFN_FD5 = 624,\n\tFN_HSPI_RX2 = 625,\n\tFN_VI1_R3 = 626,\n\tFN_TX5_B___2 = 627,\n\tFN_SSI_SDATA7_B___3 = 628,\n\tFN_CTS0_B = 629,\n\tFN_A24___3 = 630,\n\tFN_SD1_CD___3 = 631,\n\tFN_MMC0_D4 = 632,\n\tFN_FD4 = 633,\n\tFN_HSPI_CS2 = 634,\n\tFN_VI1_R2 = 635,\n\tFN_SSI_WS78_B___3 = 636,\n\tFN_A23___3 = 637,\n\tFN_FCLE = 638,\n\tFN_HSPI_CLK2 = 639,\n\tFN_VI1_R1 = 640,\n\tFN_A22___3 = 641,\n\tFN_RX5_D = 642,\n\tFN_HSPI_RX2_B = 643,\n\tFN_VI1_R0 = 644,\n\tFN_A21___3 = 645,\n\tFN_SCK5_D = 646,\n\tFN_HSPI_CLK2_B = 647,\n\tFN_A20___3 = 648,\n\tFN_TX5_D = 649,\n\tFN_HSPI_TX2_B = 650,\n\tFN_A0___3 = 651,\n\tFN_SD1_DAT3 = 652,\n\tFN_MMC0_D3 = 653,\n\tFN_FD3 = 654,\n\tFN_BS = 655,\n\tFN_SD1_DAT2 = 656,\n\tFN_MMC0_D2 = 657,\n\tFN_FD2 = 658,\n\tFN_ATADIR0 = 659,\n\tFN_SDSELF = 660,\n\tFN_HCTS1 = 661,\n\tFN_TX4_C___2 = 662,\n\tFN_USB_PENC2 = 663,\n\tFN_SCK0 = 664,\n\tFN_PWM1___3 = 665,\n\tFN_PWMFSW0 = 666,\n\tFN_SCIF_CLK___3 = 667,\n\tFN_TCLK0_C = 668,\n\tFN_EX_CS0 = 669,\n\tFN_RX3_C_IRDA_RX_C = 670,\n\tFN_MMC0_D6 = 671,\n\tFN_FD6 = 672,\n\tFN_EX_CS1 = 673,\n\tFN_MMC0_D7 = 674,\n\tFN_FD7 = 675,\n\tFN_EX_CS2 = 676,\n\tFN_SD1_CLK___3 = 677,\n\tFN_MMC0_CLK = 678,\n\tFN_FALE = 679,\n\tFN_ATACS00 = 680,\n\tFN_EX_CS3 = 681,\n\tFN_SD1_CMD___3 = 682,\n\tFN_MMC0_CMD = 683,\n\tFN_FRE = 684,\n\tFN_ATACS10 = 685,\n\tFN_VI1_R4 = 686,\n\tFN_RX5_B___2 = 687,\n\tFN_HSCK1___2 = 688,\n\tFN_SSI_SDATA8_B___3 = 689,\n\tFN_RTS0_B_TANS_B = 690,\n\tFN_SSI_SDATA9___3 = 691,\n\tFN_EX_CS4 = 692,\n\tFN_SD1_DAT0 = 693,\n\tFN_MMC0_D0 = 694,\n\tFN_FD0 = 695,\n\tFN_ATARD0 = 696,\n\tFN_VI1_R5 = 697,\n\tFN_SCK5_B = 698,\n\tFN_HTX1___2 = 699,\n\tFN_TX2_E___2 = 700,\n\tFN_TX0_B___2 = 701,\n\tFN_SSI_SCK9___3 = 702,\n\tFN_EX_CS5 = 703,\n\tFN_SD1_DAT1 = 704,\n\tFN_MMC0_D1 = 705,\n\tFN_FD1 = 706,\n\tFN_ATAWR0 = 707,\n\tFN_VI1_R6 = 708,\n\tFN_HRX1___2 = 709,\n\tFN_RX2_E___2 = 710,\n\tFN_RX0_B___2 = 711,\n\tFN_SSI_WS9___3 = 712,\n\tFN_MLB_CLK___3 = 713,\n\tFN_PWM2___3 = 714,\n\tFN_SCK4 = 715,\n\tFN_MLB_SIG___3 = 716,\n\tFN_PWM3___3 = 717,\n\tFN_TX4___2 = 718,\n\tFN_MLB_DAT___3 = 719,\n\tFN_PWM4___3 = 720,\n\tFN_RX4___2 = 721,\n\tFN_HTX0___2 = 722,\n\tFN_TX1___2 = 723,\n\tFN_SDATA = 724,\n\tFN_CTS0_C = 725,\n\tFN_SUB_TCK = 726,\n\tFN_CC5_STATE2 = 727,\n\tFN_CC5_STATE10 = 728,\n\tFN_CC5_STATE18 = 729,\n\tFN_CC5_STATE26 = 730,\n\tFN_CC5_STATE34 = 731,\n\tFN_HRX0___2 = 732,\n\tFN_RX1___2 = 733,\n\tFN_SCKZ = 734,\n\tFN_RTS0_C_TANS_C = 735,\n\tFN_SUB_TDI = 736,\n\tFN_CC5_STATE3 = 737,\n\tFN_CC5_STATE11 = 738,\n\tFN_CC5_STATE19 = 739,\n\tFN_CC5_STATE27 = 740,\n\tFN_CC5_STATE35 = 741,\n\tFN_HSCK0___2 = 742,\n\tFN_SCK1 = 743,\n\tFN_MTS = 744,\n\tFN_PWM5___3 = 745,\n\tFN_SCK0_C = 746,\n\tFN_SSI_SDATA9_B___3 = 747,\n\tFN_SUB_TDO = 748,\n\tFN_CC5_STATE0 = 749,\n\tFN_CC5_STATE8 = 750,\n\tFN_CC5_STATE16 = 751,\n\tFN_CC5_STATE24 = 752,\n\tFN_CC5_STATE32 = 753,\n\tFN_HCTS0 = 754,\n\tFN_CTS1 = 755,\n\tFN_STM = 756,\n\tFN_PWM0_D = 757,\n\tFN_RX0_C___2 = 758,\n\tFN_SCIF_CLK_C = 759,\n\tFN_SUB_TRST = 760,\n\tFN_TCLK1_B___3 = 761,\n\tFN_CC5_OSCOUT = 762,\n\tFN_HRTS0 = 763,\n\tFN_RTS1_TANS = 764,\n\tFN_MDATA = 765,\n\tFN_TX0_C___2 = 766,\n\tFN_SUB_TMS = 767,\n\tFN_CC5_STATE1 = 768,\n\tFN_CC5_STATE9 = 769,\n\tFN_CC5_STATE17 = 770,\n\tFN_CC5_STATE25 = 771,\n\tFN_CC5_STATE33 = 772,\n\tFN_DU0_DR0___2 = 773,\n\tFN_LCDOUT0___3 = 774,\n\tFN_DREQ0___2 = 775,\n\tFN_GPS_CLK_B___2 = 776,\n\tFN_AUDATA0 = 777,\n\tFN_TX5_C = 778,\n\tFN_DU0_DR1___2 = 779,\n\tFN_LCDOUT1___3 = 780,\n\tFN_DACK0___3 = 781,\n\tFN_DRACK0___3 = 782,\n\tFN_GPS_SIGN_B___2 = 783,\n\tFN_AUDATA1 = 784,\n\tFN_RX5_C = 785,\n\tFN_DU0_DR2___2 = 786,\n\tFN_LCDOUT2___3 = 787,\n\tFN_DU0_DR3___2 = 788,\n\tFN_LCDOUT3___3 = 789,\n\tFN_DU0_DR4___2 = 790,\n\tFN_LCDOUT4___3 = 791,\n\tFN_DU0_DR5___2 = 792,\n\tFN_LCDOUT5___3 = 793,\n\tFN_DU0_DR6___2 = 794,\n\tFN_LCDOUT6___3 = 795,\n\tFN_DU0_DR7___2 = 796,\n\tFN_LCDOUT7___3 = 797,\n\tFN_DU0_DG0___2 = 798,\n\tFN_LCDOUT8___3 = 799,\n\tFN_DREQ1___2 = 800,\n\tFN_SCL2 = 801,\n\tFN_AUDATA2 = 802,\n\tFN_DU0_DG1___2 = 803,\n\tFN_LCDOUT9___3 = 804,\n\tFN_DACK1___3 = 805,\n\tFN_SDA2 = 806,\n\tFN_AUDATA3 = 807,\n\tFN_DU0_DG2___2 = 808,\n\tFN_LCDOUT10___3 = 809,\n\tFN_DU0_DG3___2 = 810,\n\tFN_LCDOUT11___3 = 811,\n\tFN_DU0_DG4___2 = 812,\n\tFN_LCDOUT12___3 = 813,\n\tFN_DU0_DG5___2 = 814,\n\tFN_LCDOUT13___3 = 815,\n\tFN_DU0_DG6___2 = 816,\n\tFN_LCDOUT14___3 = 817,\n\tFN_DU0_DG7___2 = 818,\n\tFN_LCDOUT15___3 = 819,\n\tFN_DU0_DB0___2 = 820,\n\tFN_LCDOUT16___3 = 821,\n\tFN_EX_WAIT1___3 = 822,\n\tFN_SCL1 = 823,\n\tFN_TCLK1___3 = 824,\n\tFN_AUDATA4 = 825,\n\tFN_DU0_DB1___2 = 826,\n\tFN_LCDOUT17___3 = 827,\n\tFN_EX_WAIT2___3 = 828,\n\tFN_SDA1 = 829,\n\tFN_GPS_MAG_B___2 = 830,\n\tFN_AUDATA5 = 831,\n\tFN_SCK5_C = 832,\n\tFN_DU0_DB2___2 = 833,\n\tFN_LCDOUT18___3 = 834,\n\tFN_DU0_DB3___2 = 835,\n\tFN_LCDOUT19___3 = 836,\n\tFN_DU0_DB4___2 = 837,\n\tFN_LCDOUT20___3 = 838,\n\tFN_DU0_DB5___2 = 839,\n\tFN_LCDOUT21___3 = 840,\n\tFN_DU0_DB6___2 = 841,\n\tFN_LCDOUT22___3 = 842,\n\tFN_DU0_DB7___2 = 843,\n\tFN_LCDOUT23___3 = 844,\n\tFN_DU0_DOTCLKIN___3 = 845,\n\tFN_QSTVA_QVS___3 = 846,\n\tFN_TX3_D_IRDA_TX_D = 847,\n\tFN_SCL3_B = 848,\n\tFN_DU0_DOTCLKOUT0___2 = 849,\n\tFN_QCLK___3 = 850,\n\tFN_DU0_DOTCLKOUT1___2 = 851,\n\tFN_QSTVB_QVE___3 = 852,\n\tFN_RX3_D_IRDA_RX_D = 853,\n\tFN_SDA3_B = 854,\n\tFN_SDA2_C = 855,\n\tFN_DACK0_B = 856,\n\tFN_DRACK0_B = 857,\n\tFN_DU0_EXHSYNC_DU0_HSYNC___2 = 858,\n\tFN_QSTH_QHS___3 = 859,\n\tFN_DU0_EXVSYNC_DU0_VSYNC___2 = 860,\n\tFN_QSTB_QHE___3 = 861,\n\tFN_DU0_EXODDF_DU0_ODDF_DISP_CDE___2 = 862,\n\tFN_QCPV_QDE___3 = 863,\n\tFN_CAN1_TX___3 = 864,\n\tFN_TX2_C___2 = 865,\n\tFN_SCL2_C = 866,\n\tFN_REMOCON___3 = 867,\n\tFN_DU0_DISP___2 = 868,\n\tFN_QPOLA___3 = 869,\n\tFN_CAN_CLK_C___3 = 870,\n\tFN_SCK2_C = 871,\n\tFN_DU0_CDE___2 = 872,\n\tFN_QPOLB___3 = 873,\n\tFN_CAN1_RX___3 = 874,\n\tFN_RX2_C___2 = 875,\n\tFN_DREQ0_B = 876,\n\tFN_SSI_SCK78_B___3 = 877,\n\tFN_SCK0_B = 878,\n\tFN_DU1_DR0___3 = 879,\n\tFN_VI2_DATA0_VI2_B0 = 880,\n\tFN_PWM6___3 = 881,\n\tFN_SD3_CLK = 882,\n\tFN_TX3_E_IRDA_TX_E = 883,\n\tFN_AUDCK = 884,\n\tFN_PWMFSW0_B = 885,\n\tFN_DU1_DR1___3 = 886,\n\tFN_VI2_DATA1_VI2_B1 = 887,\n\tFN_PWM0___3 = 888,\n\tFN_SD3_CMD = 889,\n\tFN_RX3_E_IRDA_RX_E = 890,\n\tFN_AUDSYNC = 891,\n\tFN_CTS0_D = 892,\n\tFN_DU1_DR2___3 = 893,\n\tFN_VI2_G0 = 894,\n\tFN_DU1_DR3___3 = 895,\n\tFN_VI2_G1 = 896,\n\tFN_DU1_DR4___3 = 897,\n\tFN_VI2_G2 = 898,\n\tFN_DU1_DR5___3 = 899,\n\tFN_VI2_G3 = 900,\n\tFN_DU1_DR6___3 = 901,\n\tFN_VI2_G4 = 902,\n\tFN_DU1_DR7___3 = 903,\n\tFN_VI2_G5 = 904,\n\tFN_DU1_DG0___3 = 905,\n\tFN_VI2_DATA2_VI2_B2 = 906,\n\tFN_SCL1_B = 907,\n\tFN_SD3_DAT2 = 908,\n\tFN_SCK3_E = 909,\n\tFN_AUDATA6 = 910,\n\tFN_TX0_D___2 = 911,\n\tFN_DU1_DG1___3 = 912,\n\tFN_VI2_DATA3_VI2_B3 = 913,\n\tFN_SDA1_B = 914,\n\tFN_SD3_DAT3 = 915,\n\tFN_SCK5 = 916,\n\tFN_AUDATA7 = 917,\n\tFN_RX0_D___2 = 918,\n\tFN_DU1_DG2___3 = 919,\n\tFN_VI2_G6 = 920,\n\tFN_DU1_DG3___3 = 921,\n\tFN_VI2_G7 = 922,\n\tFN_DU1_DG4___3 = 923,\n\tFN_VI2_R0 = 924,\n\tFN_DU1_DG5___3 = 925,\n\tFN_VI2_R1 = 926,\n\tFN_DU1_DG6___3 = 927,\n\tFN_VI2_R2 = 928,\n\tFN_DU1_DG7___3 = 929,\n\tFN_VI2_R3 = 930,\n\tFN_DU1_DB0___3 = 931,\n\tFN_VI2_DATA4_VI2_B4 = 932,\n\tFN_SCL2_B = 933,\n\tFN_SD3_DAT0 = 934,\n\tFN_TX5___2 = 935,\n\tFN_SCK0_D = 936,\n\tFN_DU1_DB1___3 = 937,\n\tFN_VI2_DATA5_VI2_B5 = 938,\n\tFN_SDA2_B = 939,\n\tFN_SD3_DAT1 = 940,\n\tFN_RX5___2 = 941,\n\tFN_RTS0_D_TANS_D = 942,\n\tFN_DU1_DB2___3 = 943,\n\tFN_VI2_R4 = 944,\n\tFN_DU1_DB3___3 = 945,\n\tFN_VI2_R5 = 946,\n\tFN_DU1_DB4___3 = 947,\n\tFN_VI2_R6 = 948,\n\tFN_DU1_DB5___3 = 949,\n\tFN_VI2_R7 = 950,\n\tFN_DU1_DB6___3 = 951,\n\tFN_SCL2_D = 952,\n\tFN_DU1_DB7___3 = 953,\n\tFN_SDA2_D = 954,\n\tFN_DU1_DOTCLKIN___3 = 955,\n\tFN_VI2_CLKENB___2 = 956,\n\tFN_HSPI_CS1 = 957,\n\tFN_SCL1_D = 958,\n\tFN_DU1_DOTCLKOUT = 959,\n\tFN_VI2_FIELD___2 = 960,\n\tFN_SDA1_D = 961,\n\tFN_DU1_EXHSYNC_DU1_HSYNC___3 = 962,\n\tFN_VI2_HSYNC = 963,\n\tFN_VI3_HSYNC = 964,\n\tFN_DU1_EXVSYNC_DU1_VSYNC___3 = 965,\n\tFN_VI2_VSYNC = 966,\n\tFN_VI3_VSYNC = 967,\n\tFN_DU1_EXODDF_DU1_ODDF_DISP_CDE___3 = 968,\n\tFN_VI2_CLK___2 = 969,\n\tFN_TX3_B_IRDA_TX_B = 970,\n\tFN_SD3_CD = 971,\n\tFN_HSPI_TX1 = 972,\n\tFN_VI1_CLKENB___3 = 973,\n\tFN_VI3_CLKENB = 974,\n\tFN_AUDIO_CLKC___3 = 975,\n\tFN_TX2_D = 976,\n\tFN_SPEEDIN___3 = 977,\n\tFN_GPS_SIGN_D___2 = 978,\n\tFN_DU1_DISP___3 = 979,\n\tFN_VI2_DATA6_VI2_B6 = 980,\n\tFN_TCLK0 = 981,\n\tFN_QSTVA_B_QVS_B = 982,\n\tFN_HSPI_CLK1 = 983,\n\tFN_SCK2_D = 984,\n\tFN_AUDIO_CLKOUT_B___2 = 985,\n\tFN_GPS_MAG_D___2 = 986,\n\tFN_DU1_CDE___3 = 987,\n\tFN_VI2_DATA7_VI2_B7 = 988,\n\tFN_RX3_B_IRDA_RX_B = 989,\n\tFN_SD3_WP = 990,\n\tFN_HSPI_RX1 = 991,\n\tFN_VI1_FIELD___3 = 992,\n\tFN_VI3_FIELD = 993,\n\tFN_AUDIO_CLKOUT___3 = 994,\n\tFN_RX2_D = 995,\n\tFN_GPS_CLK_C___2 = 996,\n\tFN_GPS_CLK_D___2 = 997,\n\tFN_AUDIO_CLKA___3 = 998,\n\tFN_CAN_TXCLK = 999,\n\tFN_AUDIO_CLKB___3 = 1000,\n\tFN_USB_OVC2 = 1001,\n\tFN_CAN_DEBUGOUT0 = 1002,\n\tFN_MOUT0 = 1003,\n\tFN_SSI_SCK0129___3 = 1004,\n\tFN_CAN_DEBUGOUT1 = 1005,\n\tFN_MOUT1 = 1006,\n\tFN_SSI_WS0129___3 = 1007,\n\tFN_CAN_DEBUGOUT2 = 1008,\n\tFN_MOUT2 = 1009,\n\tFN_SSI_SDATA0___3 = 1010,\n\tFN_CAN_DEBUGOUT3 = 1011,\n\tFN_MOUT5 = 1012,\n\tFN_SSI_SDATA1___3 = 1013,\n\tFN_CAN_DEBUGOUT4 = 1014,\n\tFN_MOUT6 = 1015,\n\tFN_SSI_SDATA2___3 = 1016,\n\tFN_CAN_DEBUGOUT5 = 1017,\n\tFN_SSI_SCK34___3 = 1018,\n\tFN_CAN_DEBUGOUT6 = 1019,\n\tFN_CAN0_TX_B___3 = 1020,\n\tFN_IERX___3 = 1021,\n\tFN_SSI_SCK9_C = 1022,\n\tFN_SSI_WS34___3 = 1023,\n\tFN_CAN_DEBUGOUT7 = 1024,\n\tFN_CAN0_RX_B___3 = 1025,\n\tFN_IETX___3 = 1026,\n\tFN_SSI_WS9_C = 1027,\n\tFN_SSI_SDATA3___3 = 1028,\n\tFN_PWM0_C = 1029,\n\tFN_CAN_DEBUGOUT8 = 1030,\n\tFN_CAN_CLK_B___3 = 1031,\n\tFN_IECLK___3 = 1032,\n\tFN_SCIF_CLK_B___3 = 1033,\n\tFN_TCLK0_B = 1034,\n\tFN_SSI_SDATA4___3 = 1035,\n\tFN_CAN_DEBUGOUT9 = 1036,\n\tFN_SSI_SDATA9_C = 1037,\n\tFN_SSI_SCK5___3 = 1038,\n\tFN_ADICLK___3 = 1039,\n\tFN_CAN_DEBUGOUT10 = 1040,\n\tFN_SCK3 = 1041,\n\tFN_TCLK0_D = 1042,\n\tFN_SSI_WS5___3 = 1043,\n\tFN_ADICS_SAMP___3 = 1044,\n\tFN_CAN_DEBUGOUT11 = 1045,\n\tFN_TX3_IRDA_TX = 1046,\n\tFN_SSI_SDATA5___3 = 1047,\n\tFN_ADIDATA___3 = 1048,\n\tFN_CAN_DEBUGOUT12 = 1049,\n\tFN_RX3_IRDA_RX = 1050,\n\tFN_SSI_SCK6___3 = 1051,\n\tFN_ADICHS0___3 = 1052,\n\tFN_CAN0_TX___3 = 1053,\n\tFN_IERX_B___3 = 1054,\n\tFN_SSI_WS6___3 = 1055,\n\tFN_ADICHS1___3 = 1056,\n\tFN_CAN0_RX___3 = 1057,\n\tFN_IETX_B___3 = 1058,\n\tFN_SSI_SDATA6___3 = 1059,\n\tFN_ADICHS2___3 = 1060,\n\tFN_CAN_CLK___3 = 1061,\n\tFN_IECLK_B___3 = 1062,\n\tFN_SSI_SCK78___3 = 1063,\n\tFN_CAN_DEBUGOUT13 = 1064,\n\tFN_IRQ0_B = 1065,\n\tFN_SSI_SCK9_B___3 = 1066,\n\tFN_HSPI_CLK1_C = 1067,\n\tFN_SSI_WS78___3 = 1068,\n\tFN_CAN_DEBUGOUT14 = 1069,\n\tFN_IRQ1_B = 1070,\n\tFN_SSI_WS9_B___3 = 1071,\n\tFN_HSPI_CS1_C = 1072,\n\tFN_SSI_SDATA7___3 = 1073,\n\tFN_CAN_DEBUGOUT15 = 1074,\n\tFN_IRQ2_B = 1075,\n\tFN_TCLK1_C = 1076,\n\tFN_HSPI_TX1_C = 1077,\n\tFN_SSI_SDATA8___3 = 1078,\n\tFN_VSP = 1079,\n\tFN_IRQ3_B = 1080,\n\tFN_HSPI_RX1_C = 1081,\n\tFN_SD0_CLK___3 = 1082,\n\tFN_ATACS01 = 1083,\n\tFN_SCK1_B = 1084,\n\tFN_SD0_CMD___3 = 1085,\n\tFN_ATACS11 = 1086,\n\tFN_TX1_B___2 = 1087,\n\tFN_CC5_TDO = 1088,\n\tFN_SD0_DAT0 = 1089,\n\tFN_ATADIR1 = 1090,\n\tFN_RX1_B___2 = 1091,\n\tFN_CC5_TRST = 1092,\n\tFN_SD0_DAT1 = 1093,\n\tFN_ATAG1 = 1094,\n\tFN_SCK2_B = 1095,\n\tFN_CC5_TMS = 1096,\n\tFN_SD0_DAT2 = 1097,\n\tFN_ATARD1 = 1098,\n\tFN_TX2_B___2 = 1099,\n\tFN_CC5_TCK = 1100,\n\tFN_SD0_DAT3 = 1101,\n\tFN_ATAWR1 = 1102,\n\tFN_RX2_B___2 = 1103,\n\tFN_CC5_TDI = 1104,\n\tFN_SD0_CD___3 = 1105,\n\tFN_DREQ2___2 = 1106,\n\tFN_RTS1_B_TANS_B = 1107,\n\tFN_SD0_WP___3 = 1108,\n\tFN_DACK2___3 = 1109,\n\tFN_CTS1_B = 1110,\n\tFN_HSPI_CLK0 = 1111,\n\tFN_CTS0 = 1112,\n\tFN_USB_OVC0 = 1113,\n\tFN_AD_CLK = 1114,\n\tFN_CC5_STATE4 = 1115,\n\tFN_CC5_STATE12 = 1116,\n\tFN_CC5_STATE20 = 1117,\n\tFN_CC5_STATE28 = 1118,\n\tFN_CC5_STATE36 = 1119,\n\tFN_HSPI_CS0 = 1120,\n\tFN_RTS0_TANS = 1121,\n\tFN_USB_OVC1 = 1122,\n\tFN_AD_DI = 1123,\n\tFN_CC5_STATE5 = 1124,\n\tFN_CC5_STATE13 = 1125,\n\tFN_CC5_STATE21 = 1126,\n\tFN_CC5_STATE29 = 1127,\n\tFN_CC5_STATE37 = 1128,\n\tFN_HSPI_TX0 = 1129,\n\tFN_TX0___2 = 1130,\n\tFN_CAN_DEBUG_HW_TRIGGER = 1131,\n\tFN_AD_DO = 1132,\n\tFN_CC5_STATE6 = 1133,\n\tFN_CC5_STATE14 = 1134,\n\tFN_CC5_STATE22 = 1135,\n\tFN_CC5_STATE30 = 1136,\n\tFN_CC5_STATE38 = 1137,\n\tFN_HSPI_RX0 = 1138,\n\tFN_RX0___2 = 1139,\n\tFN_CAN_STEP0 = 1140,\n\tFN_AD_NCS = 1141,\n\tFN_CC5_STATE7 = 1142,\n\tFN_CC5_STATE15 = 1143,\n\tFN_CC5_STATE23 = 1144,\n\tFN_CC5_STATE31 = 1145,\n\tFN_CC5_STATE39 = 1146,\n\tFN_FMCLK___3 = 1147,\n\tFN_RDS_CLK = 1148,\n\tFN_PCMOE = 1149,\n\tFN_BPFCLK___3 = 1150,\n\tFN_PCMWE = 1151,\n\tFN_FMIN___3 = 1152,\n\tFN_RDS_DATA = 1153,\n\tFN_VI0_CLK___3 = 1154,\n\tFN_MMC1_CLK = 1155,\n\tFN_VI0_CLKENB___3 = 1156,\n\tFN_TX1_C___2 = 1157,\n\tFN_HTX1_B___2 = 1158,\n\tFN_MT1_SYNC = 1159,\n\tFN_VI0_FIELD___3 = 1160,\n\tFN_RX1_C___2 = 1161,\n\tFN_HRX1_B___2 = 1162,\n\tFN_VI0_HSYNC = 1163,\n\tFN_VI0_DATA0_B_VI0_B0_B = 1164,\n\tFN_CTS1_C = 1165,\n\tFN_TX4_D = 1166,\n\tFN_MMC1_CMD = 1167,\n\tFN_HSCK1_B = 1168,\n\tFN_VI0_VSYNC = 1169,\n\tFN_VI0_DATA1_B_VI0_B1_B = 1170,\n\tFN_RTS1_C_TANS_C = 1171,\n\tFN_RX4_D = 1172,\n\tFN_PWMFSW0_C = 1173,\n\tFN_VI0_DATA0_VI0_B0___3 = 1174,\n\tFN_HRTS1_B = 1175,\n\tFN_MT1_VCXO = 1176,\n\tFN_VI0_DATA1_VI0_B1___3 = 1177,\n\tFN_HCTS1_B = 1178,\n\tFN_MT1_PWM = 1179,\n\tFN_VI0_DATA2_VI0_B2___3 = 1180,\n\tFN_MMC1_D0 = 1181,\n\tFN_VI0_DATA3_VI0_B3___3 = 1182,\n\tFN_MMC1_D1 = 1183,\n\tFN_VI0_DATA4_VI0_B4___3 = 1184,\n\tFN_MMC1_D2 = 1185,\n\tFN_VI0_DATA5_VI0_B5___3 = 1186,\n\tFN_MMC1_D3 = 1187,\n\tFN_VI0_DATA6_VI0_B6___3 = 1188,\n\tFN_MMC1_D4 = 1189,\n\tFN_ARM_TRACEDATA_0 = 1190,\n\tFN_VI0_DATA7_VI0_B7___3 = 1191,\n\tFN_MMC1_D5 = 1192,\n\tFN_ARM_TRACEDATA_1 = 1193,\n\tFN_VI0_G0___3 = 1194,\n\tFN_SSI_SCK78_C = 1195,\n\tFN_IRQ0___3 = 1196,\n\tFN_ARM_TRACEDATA_2 = 1197,\n\tFN_VI0_G1___3 = 1198,\n\tFN_SSI_WS78_C = 1199,\n\tFN_IRQ1___3 = 1200,\n\tFN_ARM_TRACEDATA_3 = 1201,\n\tFN_VI0_G2___3 = 1202,\n\tFN_ETH_TXD1___3 = 1203,\n\tFN_MMC1_D6 = 1204,\n\tFN_ARM_TRACEDATA_4 = 1205,\n\tFN_TS_SPSYNC0___2 = 1206,\n\tFN_VI0_G3___3 = 1207,\n\tFN_ETH_CRS_DV___3 = 1208,\n\tFN_MMC1_D7 = 1209,\n\tFN_ARM_TRACEDATA_5 = 1210,\n\tFN_TS_SDAT0 = 1211,\n\tFN_VI0_G4___3 = 1212,\n\tFN_ETH_TX_EN___3 = 1213,\n\tFN_SD2_DAT0_B = 1214,\n\tFN_ARM_TRACEDATA_6 = 1215,\n\tFN_VI0_G5___3 = 1216,\n\tFN_ETH_RX_ER___3 = 1217,\n\tFN_SD2_DAT1_B = 1218,\n\tFN_ARM_TRACEDATA_7 = 1219,\n\tFN_VI0_G6___3 = 1220,\n\tFN_ETH_RXD0___3 = 1221,\n\tFN_SD2_DAT2_B = 1222,\n\tFN_ARM_TRACEDATA_8 = 1223,\n\tFN_VI0_G7___3 = 1224,\n\tFN_ETH_RXD1___3 = 1225,\n\tFN_SD2_DAT3_B = 1226,\n\tFN_ARM_TRACEDATA_9 = 1227,\n\tFN_VI0_R0___3 = 1228,\n\tFN_SSI_SDATA7_C = 1229,\n\tFN_SCK1_C = 1230,\n\tFN_DREQ1_B = 1231,\n\tFN_ARM_TRACEDATA_10 = 1232,\n\tFN_DREQ0_C = 1233,\n\tFN_VI0_R1___3 = 1234,\n\tFN_SSI_SDATA8_C = 1235,\n\tFN_DACK1_B___2 = 1236,\n\tFN_ARM_TRACEDATA_11 = 1237,\n\tFN_DACK0_C = 1238,\n\tFN_DRACK0_C = 1239,\n\tFN_VI0_R2___3 = 1240,\n\tFN_ETH_LINK___3 = 1241,\n\tFN_SD2_CLK_B = 1242,\n\tFN_IRQ2___3 = 1243,\n\tFN_ARM_TRACEDATA_12 = 1244,\n\tFN_VI0_R3___3 = 1245,\n\tFN_ETH_MAGIC___3 = 1246,\n\tFN_SD2_CMD_B = 1247,\n\tFN_IRQ3___3 = 1248,\n\tFN_ARM_TRACEDATA_13 = 1249,\n\tFN_VI0_R4___3 = 1250,\n\tFN_ETH_REFCLK___3 = 1251,\n\tFN_SD2_CD_B = 1252,\n\tFN_HSPI_CLK1_B = 1253,\n\tFN_ARM_TRACEDATA_14 = 1254,\n\tFN_MT1_CLK = 1255,\n\tFN_TS_SCK0___2 = 1256,\n\tFN_VI0_R5___3 = 1257,\n\tFN_ETH_TXD0___3 = 1258,\n\tFN_SD2_WP_B = 1259,\n\tFN_HSPI_CS1_B = 1260,\n\tFN_ARM_TRACEDATA_15 = 1261,\n\tFN_MT1_D = 1262,\n\tFN_TS_SDEN0___2 = 1263,\n\tFN_VI0_R6___3 = 1264,\n\tFN_ETH_MDC___3 = 1265,\n\tFN_DREQ2_C___2 = 1266,\n\tFN_HSPI_TX1_B = 1267,\n\tFN_TRACECLK = 1268,\n\tFN_MT1_BEN = 1269,\n\tFN_PWMFSW0_D = 1270,\n\tFN_VI0_R7___3 = 1271,\n\tFN_ETH_MDIO___3 = 1272,\n\tFN_DACK2_C = 1273,\n\tFN_HSPI_RX1_B = 1274,\n\tFN_SCIF_CLK_D = 1275,\n\tFN_TRACECTL = 1276,\n\tFN_MT1_PEN = 1277,\n\tFN_VI1_CLK___3 = 1278,\n\tFN_SIM_D = 1279,\n\tFN_SDA3 = 1280,\n\tFN_VI1_HSYNC = 1281,\n\tFN_VI3_CLK = 1282,\n\tFN_SSI_SCK4___3 = 1283,\n\tFN_GPS_SIGN_C___2 = 1284,\n\tFN_PWMFSW0_E = 1285,\n\tFN_VI1_VSYNC = 1286,\n\tFN_AUDIO_CLKOUT_C___2 = 1287,\n\tFN_SSI_WS4___3 = 1288,\n\tFN_SIM_CLK = 1289,\n\tFN_GPS_MAG_C___2 = 1290,\n\tFN_SPV_TRST = 1291,\n\tFN_SCL3 = 1292,\n\tFN_VI1_DATA0_VI1_B0 = 1293,\n\tFN_SD2_DAT0 = 1294,\n\tFN_SIM_RST = 1295,\n\tFN_SPV_TCK = 1296,\n\tFN_ADICLK_B___3 = 1297,\n\tFN_VI1_DATA1_VI1_B1 = 1298,\n\tFN_SD2_DAT1 = 1299,\n\tFN_MT0_CLK = 1300,\n\tFN_SPV_TMS = 1301,\n\tFN_ADICS_B_SAMP_B = 1302,\n\tFN_VI1_DATA2_VI1_B2 = 1303,\n\tFN_SD2_DAT2 = 1304,\n\tFN_MT0_D = 1305,\n\tFN_SPVTDI = 1306,\n\tFN_ADIDATA_B___3 = 1307,\n\tFN_VI1_DATA3_VI1_B3 = 1308,\n\tFN_SD2_DAT3 = 1309,\n\tFN_MT0_BEN = 1310,\n\tFN_SPV_TDO = 1311,\n\tFN_ADICHS0_B___3 = 1312,\n\tFN_VI1_DATA4_VI1_B4 = 1313,\n\tFN_SD2_CLK___3 = 1314,\n\tFN_MT0_PEN = 1315,\n\tFN_SPA_TRST = 1316,\n\tFN_HSPI_CLK1_D = 1317,\n\tFN_ADICHS1_B___3 = 1318,\n\tFN_VI1_DATA5_VI1_B5 = 1319,\n\tFN_SD2_CMD___3 = 1320,\n\tFN_MT0_SYNC = 1321,\n\tFN_SPA_TCK = 1322,\n\tFN_HSPI_CS1_D = 1323,\n\tFN_ADICHS2_B___3 = 1324,\n\tFN_VI1_DATA6_VI1_B6 = 1325,\n\tFN_SD2_CD___3 = 1326,\n\tFN_MT0_VCXO = 1327,\n\tFN_SPA_TMS = 1328,\n\tFN_HSPI_TX1_D = 1329,\n\tFN_VI1_DATA7_VI1_B7 = 1330,\n\tFN_SD2_WP___3 = 1331,\n\tFN_MT0_PWM = 1332,\n\tFN_SPA_TDI = 1333,\n\tFN_HSPI_RX1_D = 1334,\n\tFN_VI1_G0 = 1335,\n\tFN_VI3_DATA0 = 1336,\n\tFN_TS_SCK1 = 1337,\n\tFN_DREQ2_B___2 = 1338,\n\tFN_TX2___2 = 1339,\n\tFN_SPA_TDO = 1340,\n\tFN_HCTS0_B = 1341,\n\tFN_VI1_G1 = 1342,\n\tFN_VI3_DATA1 = 1343,\n\tFN_SSI_SCK1___3 = 1344,\n\tFN_TS_SDEN1 = 1345,\n\tFN_DACK2_B___2 = 1346,\n\tFN_RX2___2 = 1347,\n\tFN_HRTS0_B = 1348,\n\tFN_VI1_G2 = 1349,\n\tFN_VI3_DATA2 = 1350,\n\tFN_SSI_WS1___3 = 1351,\n\tFN_TS_SPSYNC1 = 1352,\n\tFN_SCK2 = 1353,\n\tFN_HSCK0_B = 1354,\n\tFN_VI1_G3 = 1355,\n\tFN_VI3_DATA3 = 1356,\n\tFN_SSI_SCK2___3 = 1357,\n\tFN_TS_SDAT1 = 1358,\n\tFN_SCL1_C = 1359,\n\tFN_HTX0_B___2 = 1360,\n\tFN_VI1_G4 = 1361,\n\tFN_VI3_DATA4 = 1362,\n\tFN_SSI_WS2___3 = 1363,\n\tFN_SDA1_C = 1364,\n\tFN_SIM_RST_B = 1365,\n\tFN_HRX0_B___2 = 1366,\n\tFN_VI1_G5 = 1367,\n\tFN_VI3_DATA5 = 1368,\n\tFN_GPS_CLK___2 = 1369,\n\tFN_FSE = 1370,\n\tFN_TX4_B___2 = 1371,\n\tFN_SIM_D_B = 1372,\n\tFN_VI1_G6 = 1373,\n\tFN_VI3_DATA6 = 1374,\n\tFN_GPS_SIGN___2 = 1375,\n\tFN_FRB = 1376,\n\tFN_RX4_B___2 = 1377,\n\tFN_SIM_CLK_B = 1378,\n\tFN_VI1_G7 = 1379,\n\tFN_VI3_DATA7 = 1380,\n\tFN_GPS_MAG___2 = 1381,\n\tFN_FCE = 1382,\n\tFN_SCK4_B = 1383,\n\tFN_SEL_SCIF5_0___3 = 1384,\n\tFN_SEL_SCIF5_1___3 = 1385,\n\tFN_SEL_SCIF5_2___2 = 1386,\n\tFN_SEL_SCIF5_3___2 = 1387,\n\tFN_SEL_SCIF4_0___3 = 1388,\n\tFN_SEL_SCIF4_1___3 = 1389,\n\tFN_SEL_SCIF4_2___3 = 1390,\n\tFN_SEL_SCIF4_3___2 = 1391,\n\tFN_SEL_SCIF3_0___3 = 1392,\n\tFN_SEL_SCIF3_1___3 = 1393,\n\tFN_SEL_SCIF3_2___2 = 1394,\n\tFN_SEL_SCIF3_3___2 = 1395,\n\tFN_SEL_SCIF3_4 = 1396,\n\tFN_SEL_SCIF2_0___3 = 1397,\n\tFN_SEL_SCIF2_1___3 = 1398,\n\tFN_SEL_SCIF2_2___3 = 1399,\n\tFN_SEL_SCIF2_3___2 = 1400,\n\tFN_SEL_SCIF2_4___2 = 1401,\n\tFN_SEL_SCIF1_0___3 = 1402,\n\tFN_SEL_SCIF1_1___3 = 1403,\n\tFN_SEL_SCIF1_2___3 = 1404,\n\tFN_SEL_SCIF0_0___3 = 1405,\n\tFN_SEL_SCIF0_1___3 = 1406,\n\tFN_SEL_SCIF0_2___3 = 1407,\n\tFN_SEL_SCIF0_3___3 = 1408,\n\tFN_SEL_SSI9_0___3 = 1409,\n\tFN_SEL_SSI9_1___3 = 1410,\n\tFN_SEL_SSI9_2 = 1411,\n\tFN_SEL_SSI8_0___3 = 1412,\n\tFN_SEL_SSI8_1___3 = 1413,\n\tFN_SEL_SSI8_2 = 1414,\n\tFN_SEL_SSI7_0___3 = 1415,\n\tFN_SEL_SSI7_1___3 = 1416,\n\tFN_SEL_SSI7_2 = 1417,\n\tFN_SEL_VI0_0 = 1418,\n\tFN_SEL_VI0_1 = 1419,\n\tFN_SEL_SD2_0 = 1420,\n\tFN_SEL_SD2_1 = 1421,\n\tFN_SEL_INT3_0 = 1422,\n\tFN_SEL_INT3_1 = 1423,\n\tFN_SEL_INT2_0 = 1424,\n\tFN_SEL_INT2_1 = 1425,\n\tFN_SEL_INT1_0 = 1426,\n\tFN_SEL_INT1_1 = 1427,\n\tFN_SEL_INT0_0 = 1428,\n\tFN_SEL_INT0_1 = 1429,\n\tFN_SEL_IE_0 = 1430,\n\tFN_SEL_IE_1 = 1431,\n\tFN_SEL_EXBUS2_0 = 1432,\n\tFN_SEL_EXBUS2_1 = 1433,\n\tFN_SEL_EXBUS2_2 = 1434,\n\tFN_SEL_EXBUS1_0 = 1435,\n\tFN_SEL_EXBUS1_1 = 1436,\n\tFN_SEL_EXBUS0_0 = 1437,\n\tFN_SEL_EXBUS0_1 = 1438,\n\tFN_SEL_EXBUS0_2 = 1439,\n\tFN_SEL_TMU1_0___2 = 1440,\n\tFN_SEL_TMU1_1___2 = 1441,\n\tFN_SEL_TMU1_2 = 1442,\n\tFN_SEL_TMU0_0 = 1443,\n\tFN_SEL_TMU0_1 = 1444,\n\tFN_SEL_TMU0_2 = 1445,\n\tFN_SEL_TMU0_3 = 1446,\n\tFN_SEL_SCIF_0___2 = 1447,\n\tFN_SEL_SCIF_1___2 = 1448,\n\tFN_SEL_SCIF_2 = 1449,\n\tFN_SEL_SCIF_3 = 1450,\n\tFN_SEL_CANCLK_0___2 = 1451,\n\tFN_SEL_CANCLK_1___2 = 1452,\n\tFN_SEL_CANCLK_2___2 = 1453,\n\tFN_SEL_CAN0_0___3 = 1454,\n\tFN_SEL_CAN0_1___3 = 1455,\n\tFN_SEL_HSCIF1_0___3 = 1456,\n\tFN_SEL_HSCIF1_1___3 = 1457,\n\tFN_SEL_HSCIF0_0___3 = 1458,\n\tFN_SEL_HSCIF0_1___3 = 1459,\n\tFN_SEL_PWMFSW_0 = 1460,\n\tFN_SEL_PWMFSW_1 = 1461,\n\tFN_SEL_PWMFSW_2 = 1462,\n\tFN_SEL_PWMFSW_3 = 1463,\n\tFN_SEL_PWMFSW_4 = 1464,\n\tFN_SEL_ADI_0 = 1465,\n\tFN_SEL_ADI_1 = 1466,\n\tFN_SEL_GPS_0___2 = 1467,\n\tFN_SEL_GPS_1___2 = 1468,\n\tFN_SEL_GPS_2___2 = 1469,\n\tFN_SEL_GPS_3___2 = 1470,\n\tFN_SEL_SIM_0___2 = 1471,\n\tFN_SEL_SIM_1___2 = 1472,\n\tFN_SEL_HSPI2_0 = 1473,\n\tFN_SEL_HSPI2_1 = 1474,\n\tFN_SEL_HSPI1_0 = 1475,\n\tFN_SEL_HSPI1_1 = 1476,\n\tFN_SEL_HSPI1_2 = 1477,\n\tFN_SEL_HSPI1_3 = 1478,\n\tFN_SEL_I2C3_0___2 = 1479,\n\tFN_SEL_I2C3_1___2 = 1480,\n\tFN_SEL_I2C2_0___2 = 1481,\n\tFN_SEL_I2C2_1___2 = 1482,\n\tFN_SEL_I2C2_2___2 = 1483,\n\tFN_SEL_I2C2_3___2 = 1484,\n\tFN_SEL_I2C1_0___2 = 1485,\n\tFN_SEL_I2C1_1___2 = 1486,\n\tFN_SEL_I2C1_2___2 = 1487,\n\tFN_SEL_I2C1_3___2 = 1488,\n\tPINMUX_FUNCTION_END___4 = 1489,\n\tPINMUX_MARK_BEGIN___4 = 1490,\n\tAVS1_MARK = 1491,\n\tAVS2_MARK = 1492,\n\tA17_MARK___4 = 1493,\n\tA18_MARK___4 = 1494,\n\tA19_MARK___4 = 1495,\n\tRD_WR_MARK = 1496,\n\tFWE_MARK = 1497,\n\tATAG0_MARK = 1498,\n\tVI1_R7_MARK = 1499,\n\tHRTS1_MARK = 1500,\n\tRX4_C_MARK___2 = 1501,\n\tCS1_A26_MARK = 1502,\n\tHSPI_TX2_MARK = 1503,\n\tSDSELF_B_MARK = 1504,\n\tCS0_MARK = 1505,\n\tHSPI_CS2_B_MARK = 1506,\n\tCLKOUT_MARK = 1507,\n\tTX3C_IRDA_TX_C_MARK = 1508,\n\tPWM0_B_MARK___3 = 1509,\n\tA25_MARK___4 = 1510,\n\tSD1_WP_MARK___3 = 1511,\n\tMMC0_D5_MARK = 1512,\n\tFD5_MARK = 1513,\n\tHSPI_RX2_MARK = 1514,\n\tVI1_R3_MARK = 1515,\n\tTX5_B_MARK___2 = 1516,\n\tSSI_SDATA7_B_MARK___3 = 1517,\n\tCTS0_B_MARK = 1518,\n\tA24_MARK___4 = 1519,\n\tSD1_CD_MARK___3 = 1520,\n\tMMC0_D4_MARK = 1521,\n\tFD4_MARK = 1522,\n\tHSPI_CS2_MARK = 1523,\n\tVI1_R2_MARK = 1524,\n\tSSI_WS78_B_MARK___3 = 1525,\n\tA23_MARK___4 = 1526,\n\tFCLE_MARK = 1527,\n\tHSPI_CLK2_MARK = 1528,\n\tVI1_R1_MARK = 1529,\n\tA22_MARK___4 = 1530,\n\tRX5_D_MARK = 1531,\n\tHSPI_RX2_B_MARK = 1532,\n\tVI1_R0_MARK = 1533,\n\tA21_MARK___4 = 1534,\n\tSCK5_D_MARK = 1535,\n\tHSPI_CLK2_B_MARK = 1536,\n\tA20_MARK___4 = 1537,\n\tTX5_D_MARK = 1538,\n\tHSPI_TX2_B_MARK = 1539,\n\tA0_MARK___4 = 1540,\n\tSD1_DAT3_MARK = 1541,\n\tMMC0_D3_MARK = 1542,\n\tFD3_MARK = 1543,\n\tBS_MARK = 1544,\n\tSD1_DAT2_MARK = 1545,\n\tMMC0_D2_MARK = 1546,\n\tFD2_MARK = 1547,\n\tATADIR0_MARK = 1548,\n\tSDSELF_MARK = 1549,\n\tHCTS1_MARK = 1550,\n\tTX4_C_MARK___2 = 1551,\n\tUSB_PENC0_MARK = 1552,\n\tUSB_PENC1_MARK = 1553,\n\tUSB_PENC2_MARK = 1554,\n\tSCK0_MARK = 1555,\n\tPWM1_MARK___3 = 1556,\n\tPWMFSW0_MARK = 1557,\n\tSCIF_CLK_MARK___3 = 1558,\n\tTCLK0_C_MARK = 1559,\n\tEX_CS0_MARK = 1560,\n\tRX3_C_IRDA_RX_C_MARK = 1561,\n\tMMC0_D6_MARK = 1562,\n\tFD6_MARK = 1563,\n\tEX_CS1_MARK = 1564,\n\tMMC0_D7_MARK = 1565,\n\tFD7_MARK = 1566,\n\tEX_CS2_MARK = 1567,\n\tSD1_CLK_MARK___3 = 1568,\n\tMMC0_CLK_MARK = 1569,\n\tFALE_MARK = 1570,\n\tATACS00_MARK = 1571,\n\tEX_CS3_MARK = 1572,\n\tSD1_CMD_MARK___3 = 1573,\n\tMMC0_CMD_MARK = 1574,\n\tFRE_MARK = 1575,\n\tATACS10_MARK = 1576,\n\tVI1_R4_MARK = 1577,\n\tRX5_B_MARK___2 = 1578,\n\tHSCK1_MARK___2 = 1579,\n\tSSI_SDATA8_B_MARK___3 = 1580,\n\tRTS0_B_TANS_B_MARK = 1581,\n\tSSI_SDATA9_MARK___3 = 1582,\n\tEX_CS4_MARK = 1583,\n\tSD1_DAT0_MARK = 1584,\n\tMMC0_D0_MARK = 1585,\n\tFD0_MARK = 1586,\n\tATARD0_MARK = 1587,\n\tVI1_R5_MARK = 1588,\n\tSCK5_B_MARK = 1589,\n\tHTX1_MARK___2 = 1590,\n\tTX2_E_MARK___2 = 1591,\n\tTX0_B_MARK___2 = 1592,\n\tSSI_SCK9_MARK___3 = 1593,\n\tEX_CS5_MARK = 1594,\n\tSD1_DAT1_MARK = 1595,\n\tMMC0_D1_MARK = 1596,\n\tFD1_MARK = 1597,\n\tATAWR0_MARK = 1598,\n\tVI1_R6_MARK = 1599,\n\tHRX1_MARK___2 = 1600,\n\tRX2_E_MARK___2 = 1601,\n\tRX0_B_MARK___2 = 1602,\n\tSSI_WS9_MARK___3 = 1603,\n\tMLB_CLK_MARK___3 = 1604,\n\tPWM2_MARK___3 = 1605,\n\tSCK4_MARK = 1606,\n\tMLB_SIG_MARK___3 = 1607,\n\tPWM3_MARK___3 = 1608,\n\tTX4_MARK___2 = 1609,\n\tMLB_DAT_MARK___3 = 1610,\n\tPWM4_MARK___3 = 1611,\n\tRX4_MARK___2 = 1612,\n\tHTX0_MARK___2 = 1613,\n\tTX1_MARK___2 = 1614,\n\tSDATA_MARK = 1615,\n\tCTS0_C_MARK = 1616,\n\tSUB_TCK_MARK = 1617,\n\tCC5_STATE2_MARK = 1618,\n\tCC5_STATE10_MARK = 1619,\n\tCC5_STATE18_MARK = 1620,\n\tCC5_STATE26_MARK = 1621,\n\tCC5_STATE34_MARK = 1622,\n\tHRX0_MARK___2 = 1623,\n\tRX1_MARK___2 = 1624,\n\tSCKZ_MARK = 1625,\n\tRTS0_C_TANS_C_MARK = 1626,\n\tSUB_TDI_MARK = 1627,\n\tCC5_STATE3_MARK = 1628,\n\tCC5_STATE11_MARK = 1629,\n\tCC5_STATE19_MARK = 1630,\n\tCC5_STATE27_MARK = 1631,\n\tCC5_STATE35_MARK = 1632,\n\tHSCK0_MARK___2 = 1633,\n\tSCK1_MARK = 1634,\n\tMTS_MARK = 1635,\n\tPWM5_MARK___3 = 1636,\n\tSCK0_C_MARK = 1637,\n\tSSI_SDATA9_B_MARK___3 = 1638,\n\tSUB_TDO_MARK = 1639,\n\tCC5_STATE0_MARK = 1640,\n\tCC5_STATE8_MARK = 1641,\n\tCC5_STATE16_MARK = 1642,\n\tCC5_STATE24_MARK = 1643,\n\tCC5_STATE32_MARK = 1644,\n\tHCTS0_MARK = 1645,\n\tCTS1_MARK = 1646,\n\tSTM_MARK = 1647,\n\tPWM0_D_MARK = 1648,\n\tRX0_C_MARK___2 = 1649,\n\tSCIF_CLK_C_MARK = 1650,\n\tSUB_TRST_MARK = 1651,\n\tTCLK1_B_MARK___3 = 1652,\n\tCC5_OSCOUT_MARK = 1653,\n\tHRTS0_MARK = 1654,\n\tRTS1_TANS_MARK = 1655,\n\tMDATA_MARK = 1656,\n\tTX0_C_MARK___2 = 1657,\n\tSUB_TMS_MARK = 1658,\n\tCC5_STATE1_MARK = 1659,\n\tCC5_STATE9_MARK = 1660,\n\tCC5_STATE17_MARK = 1661,\n\tCC5_STATE25_MARK = 1662,\n\tCC5_STATE33_MARK = 1663,\n\tDU0_DR0_MARK___2 = 1664,\n\tLCDOUT0_MARK___3 = 1665,\n\tDREQ0_MARK___3 = 1666,\n\tGPS_CLK_B_MARK___2 = 1667,\n\tAUDATA0_MARK = 1668,\n\tTX5_C_MARK = 1669,\n\tDU0_DR1_MARK___2 = 1670,\n\tLCDOUT1_MARK___3 = 1671,\n\tDACK0_MARK___4 = 1672,\n\tDRACK0_MARK___3 = 1673,\n\tGPS_SIGN_B_MARK___2 = 1674,\n\tAUDATA1_MARK = 1675,\n\tRX5_C_MARK = 1676,\n\tDU0_DR2_MARK___2 = 1677,\n\tLCDOUT2_MARK___3 = 1678,\n\tDU0_DR3_MARK___2 = 1679,\n\tLCDOUT3_MARK___3 = 1680,\n\tDU0_DR4_MARK___2 = 1681,\n\tLCDOUT4_MARK___3 = 1682,\n\tDU0_DR5_MARK___2 = 1683,\n\tLCDOUT5_MARK___3 = 1684,\n\tDU0_DR6_MARK___2 = 1685,\n\tLCDOUT6_MARK___3 = 1686,\n\tDU0_DR7_MARK___2 = 1687,\n\tLCDOUT7_MARK___3 = 1688,\n\tDU0_DG0_MARK___2 = 1689,\n\tLCDOUT8_MARK___3 = 1690,\n\tDREQ1_MARK___3 = 1691,\n\tSCL2_MARK = 1692,\n\tAUDATA2_MARK = 1693,\n\tDU0_DG1_MARK___2 = 1694,\n\tLCDOUT9_MARK___3 = 1695,\n\tDACK1_MARK___4 = 1696,\n\tSDA2_MARK = 1697,\n\tAUDATA3_MARK = 1698,\n\tDU0_DG2_MARK___2 = 1699,\n\tLCDOUT10_MARK___3 = 1700,\n\tDU0_DG3_MARK___2 = 1701,\n\tLCDOUT11_MARK___3 = 1702,\n\tDU0_DG4_MARK___2 = 1703,\n\tLCDOUT12_MARK___3 = 1704,\n\tDU0_DG5_MARK___2 = 1705,\n\tLCDOUT13_MARK___3 = 1706,\n\tDU0_DG6_MARK___2 = 1707,\n\tLCDOUT14_MARK___3 = 1708,\n\tDU0_DG7_MARK___2 = 1709,\n\tLCDOUT15_MARK___3 = 1710,\n\tDU0_DB0_MARK___2 = 1711,\n\tLCDOUT16_MARK___3 = 1712,\n\tEX_WAIT1_MARK___3 = 1713,\n\tSCL1_MARK = 1714,\n\tTCLK1_MARK___3 = 1715,\n\tAUDATA4_MARK = 1716,\n\tDU0_DB1_MARK___2 = 1717,\n\tLCDOUT17_MARK___3 = 1718,\n\tEX_WAIT2_MARK___3 = 1719,\n\tSDA1_MARK = 1720,\n\tGPS_MAG_B_MARK___2 = 1721,\n\tAUDATA5_MARK = 1722,\n\tSCK5_C_MARK = 1723,\n\tDU0_DB2_MARK___2 = 1724,\n\tLCDOUT18_MARK___3 = 1725,\n\tDU0_DB3_MARK___2 = 1726,\n\tLCDOUT19_MARK___3 = 1727,\n\tDU0_DB4_MARK___2 = 1728,\n\tLCDOUT20_MARK___3 = 1729,\n\tDU0_DB5_MARK___2 = 1730,\n\tLCDOUT21_MARK___3 = 1731,\n\tDU0_DB6_MARK___2 = 1732,\n\tLCDOUT22_MARK___3 = 1733,\n\tDU0_DB7_MARK___2 = 1734,\n\tLCDOUT23_MARK___3 = 1735,\n\tDU0_DOTCLKIN_MARK___3 = 1736,\n\tQSTVA_QVS_MARK___3 = 1737,\n\tTX3_D_IRDA_TX_D_MARK = 1738,\n\tSCL3_B_MARK = 1739,\n\tDU0_DOTCLKOUT0_MARK___2 = 1740,\n\tQCLK_MARK___3 = 1741,\n\tDU0_DOTCLKOUT1_MARK___2 = 1742,\n\tQSTVB_QVE_MARK___3 = 1743,\n\tRX3_D_IRDA_RX_D_MARK = 1744,\n\tSDA3_B_MARK = 1745,\n\tSDA2_C_MARK = 1746,\n\tDACK0_B_MARK = 1747,\n\tDRACK0_B_MARK = 1748,\n\tDU0_EXHSYNC_DU0_HSYNC_MARK___2 = 1749,\n\tQSTH_QHS_MARK___3 = 1750,\n\tDU0_EXVSYNC_DU0_VSYNC_MARK___2 = 1751,\n\tQSTB_QHE_MARK___3 = 1752,\n\tDU0_EXODDF_DU0_ODDF_DISP_CDE_MARK___2 = 1753,\n\tQCPV_QDE_MARK___3 = 1754,\n\tCAN1_TX_MARK___3 = 1755,\n\tTX2_C_MARK___2 = 1756,\n\tSCL2_C_MARK = 1757,\n\tREMOCON_MARK___3 = 1758,\n\tDU0_DISP_MARK___2 = 1759,\n\tQPOLA_MARK___3 = 1760,\n\tCAN_CLK_C_MARK___3 = 1761,\n\tSCK2_C_MARK = 1762,\n\tDU0_CDE_MARK___2 = 1763,\n\tQPOLB_MARK___3 = 1764,\n\tCAN1_RX_MARK___3 = 1765,\n\tRX2_C_MARK___2 = 1766,\n\tDREQ0_B_MARK = 1767,\n\tSSI_SCK78_B_MARK___3 = 1768,\n\tSCK0_B_MARK = 1769,\n\tDU1_DR0_MARK___3 = 1770,\n\tVI2_DATA0_VI2_B0_MARK = 1771,\n\tPWM6_MARK___3 = 1772,\n\tSD3_CLK_MARK = 1773,\n\tTX3_E_IRDA_TX_E_MARK = 1774,\n\tAUDCK_MARK = 1775,\n\tPWMFSW0_B_MARK = 1776,\n\tDU1_DR1_MARK___3 = 1777,\n\tVI2_DATA1_VI2_B1_MARK = 1778,\n\tPWM0_MARK___3 = 1779,\n\tSD3_CMD_MARK = 1780,\n\tRX3_E_IRDA_RX_E_MARK = 1781,\n\tAUDSYNC_MARK = 1782,\n\tCTS0_D_MARK = 1783,\n\tDU1_DR2_MARK___3 = 1784,\n\tVI2_G0_MARK = 1785,\n\tDU1_DR3_MARK___3 = 1786,\n\tVI2_G1_MARK = 1787,\n\tDU1_DR4_MARK___3 = 1788,\n\tVI2_G2_MARK = 1789,\n\tDU1_DR5_MARK___3 = 1790,\n\tVI2_G3_MARK = 1791,\n\tDU1_DR6_MARK___3 = 1792,\n\tVI2_G4_MARK = 1793,\n\tDU1_DR7_MARK___3 = 1794,\n\tVI2_G5_MARK = 1795,\n\tDU1_DG0_MARK___3 = 1796,\n\tVI2_DATA2_VI2_B2_MARK = 1797,\n\tSCL1_B_MARK = 1798,\n\tSD3_DAT2_MARK = 1799,\n\tSCK3_E_MARK = 1800,\n\tAUDATA6_MARK = 1801,\n\tTX0_D_MARK___2 = 1802,\n\tDU1_DG1_MARK___3 = 1803,\n\tVI2_DATA3_VI2_B3_MARK = 1804,\n\tSDA1_B_MARK = 1805,\n\tSD3_DAT3_MARK = 1806,\n\tSCK5_MARK = 1807,\n\tAUDATA7_MARK = 1808,\n\tRX0_D_MARK___2 = 1809,\n\tDU1_DG2_MARK___3 = 1810,\n\tVI2_G6_MARK = 1811,\n\tDU1_DG3_MARK___3 = 1812,\n\tVI2_G7_MARK = 1813,\n\tDU1_DG4_MARK___3 = 1814,\n\tVI2_R0_MARK = 1815,\n\tDU1_DG5_MARK___3 = 1816,\n\tVI2_R1_MARK = 1817,\n\tDU1_DG6_MARK___3 = 1818,\n\tVI2_R2_MARK = 1819,\n\tDU1_DG7_MARK___3 = 1820,\n\tVI2_R3_MARK = 1821,\n\tDU1_DB0_MARK___3 = 1822,\n\tVI2_DATA4_VI2_B4_MARK = 1823,\n\tSCL2_B_MARK = 1824,\n\tSD3_DAT0_MARK = 1825,\n\tTX5_MARK___2 = 1826,\n\tSCK0_D_MARK = 1827,\n\tDU1_DB1_MARK___3 = 1828,\n\tVI2_DATA5_VI2_B5_MARK = 1829,\n\tSDA2_B_MARK = 1830,\n\tSD3_DAT1_MARK = 1831,\n\tRX5_MARK___2 = 1832,\n\tRTS0_D_TANS_D_MARK = 1833,\n\tDU1_DB2_MARK___3 = 1834,\n\tVI2_R4_MARK = 1835,\n\tDU1_DB3_MARK___3 = 1836,\n\tVI2_R5_MARK = 1837,\n\tDU1_DB4_MARK___3 = 1838,\n\tVI2_R6_MARK = 1839,\n\tDU1_DB5_MARK___3 = 1840,\n\tVI2_R7_MARK = 1841,\n\tDU1_DB6_MARK___3 = 1842,\n\tSCL2_D_MARK = 1843,\n\tDU1_DB7_MARK___3 = 1844,\n\tSDA2_D_MARK = 1845,\n\tDU1_DOTCLKIN_MARK___3 = 1846,\n\tVI2_CLKENB_MARK___2 = 1847,\n\tHSPI_CS1_MARK = 1848,\n\tSCL1_D_MARK = 1849,\n\tDU1_DOTCLKOUT_MARK = 1850,\n\tVI2_FIELD_MARK___2 = 1851,\n\tSDA1_D_MARK = 1852,\n\tDU1_EXHSYNC_DU1_HSYNC_MARK___3 = 1853,\n\tVI2_HSYNC_MARK = 1854,\n\tVI3_HSYNC_MARK = 1855,\n\tDU1_EXVSYNC_DU1_VSYNC_MARK___3 = 1856,\n\tVI2_VSYNC_MARK = 1857,\n\tVI3_VSYNC_MARK = 1858,\n\tDU1_EXODDF_DU1_ODDF_DISP_CDE_MARK___3 = 1859,\n\tVI2_CLK_MARK___2 = 1860,\n\tTX3_B_IRDA_TX_B_MARK = 1861,\n\tSD3_CD_MARK = 1862,\n\tHSPI_TX1_MARK = 1863,\n\tVI1_CLKENB_MARK___3 = 1864,\n\tVI3_CLKENB_MARK = 1865,\n\tAUDIO_CLKC_MARK___3 = 1866,\n\tTX2_D_MARK = 1867,\n\tSPEEDIN_MARK___3 = 1868,\n\tGPS_SIGN_D_MARK___2 = 1869,\n\tDU1_DISP_MARK___3 = 1870,\n\tVI2_DATA6_VI2_B6_MARK = 1871,\n\tTCLK0_MARK = 1872,\n\tQSTVA_B_QVS_B_MARK = 1873,\n\tHSPI_CLK1_MARK = 1874,\n\tSCK2_D_MARK = 1875,\n\tAUDIO_CLKOUT_B_MARK___2 = 1876,\n\tGPS_MAG_D_MARK___2 = 1877,\n\tDU1_CDE_MARK___3 = 1878,\n\tVI2_DATA7_VI2_B7_MARK = 1879,\n\tRX3_B_IRDA_RX_B_MARK = 1880,\n\tSD3_WP_MARK = 1881,\n\tHSPI_RX1_MARK = 1882,\n\tVI1_FIELD_MARK___3 = 1883,\n\tVI3_FIELD_MARK = 1884,\n\tAUDIO_CLKOUT_MARK___3 = 1885,\n\tRX2_D_MARK = 1886,\n\tGPS_CLK_C_MARK___2 = 1887,\n\tGPS_CLK_D_MARK___2 = 1888,\n\tAUDIO_CLKA_MARK___3 = 1889,\n\tCAN_TXCLK_MARK___2 = 1890,\n\tAUDIO_CLKB_MARK___3 = 1891,\n\tUSB_OVC2_MARK = 1892,\n\tCAN_DEBUGOUT0_MARK = 1893,\n\tMOUT0_MARK = 1894,\n\tSSI_SCK0129_MARK___3 = 1895,\n\tCAN_DEBUGOUT1_MARK = 1896,\n\tMOUT1_MARK = 1897,\n\tSSI_WS0129_MARK___3 = 1898,\n\tCAN_DEBUGOUT2_MARK = 1899,\n\tMOUT2_MARK = 1900,\n\tSSI_SDATA0_MARK___3 = 1901,\n\tCAN_DEBUGOUT3_MARK = 1902,\n\tMOUT5_MARK = 1903,\n\tSSI_SDATA1_MARK___3 = 1904,\n\tCAN_DEBUGOUT4_MARK = 1905,\n\tMOUT6_MARK = 1906,\n\tSSI_SDATA2_MARK___3 = 1907,\n\tCAN_DEBUGOUT5_MARK = 1908,\n\tSSI_SCK34_MARK___3 = 1909,\n\tCAN_DEBUGOUT6_MARK = 1910,\n\tCAN0_TX_B_MARK___3 = 1911,\n\tIERX_MARK___3 = 1912,\n\tSSI_SCK9_C_MARK = 1913,\n\tSSI_WS34_MARK___3 = 1914,\n\tCAN_DEBUGOUT7_MARK = 1915,\n\tCAN0_RX_B_MARK___3 = 1916,\n\tIETX_MARK___3 = 1917,\n\tSSI_WS9_C_MARK = 1918,\n\tSSI_SDATA3_MARK___3 = 1919,\n\tPWM0_C_MARK = 1920,\n\tCAN_DEBUGOUT8_MARK = 1921,\n\tCAN_CLK_B_MARK___3 = 1922,\n\tIECLK_MARK___3 = 1923,\n\tSCIF_CLK_B_MARK___3 = 1924,\n\tTCLK0_B_MARK = 1925,\n\tSSI_SDATA4_MARK___3 = 1926,\n\tCAN_DEBUGOUT9_MARK = 1927,\n\tSSI_SDATA9_C_MARK = 1928,\n\tSSI_SCK5_MARK___3 = 1929,\n\tADICLK_MARK___3 = 1930,\n\tCAN_DEBUGOUT10_MARK = 1931,\n\tSCK3_MARK = 1932,\n\tTCLK0_D_MARK = 1933,\n\tSSI_WS5_MARK___3 = 1934,\n\tADICS_SAMP_MARK___3 = 1935,\n\tCAN_DEBUGOUT11_MARK = 1936,\n\tTX3_IRDA_TX_MARK = 1937,\n\tSSI_SDATA5_MARK___3 = 1938,\n\tADIDATA_MARK___3 = 1939,\n\tCAN_DEBUGOUT12_MARK = 1940,\n\tRX3_IRDA_RX_MARK = 1941,\n\tSSI_SCK6_MARK___3 = 1942,\n\tADICHS0_MARK___3 = 1943,\n\tCAN0_TX_MARK___3 = 1944,\n\tIERX_B_MARK___3 = 1945,\n\tSSI_WS6_MARK___3 = 1946,\n\tADICHS1_MARK___3 = 1947,\n\tCAN0_RX_MARK___3 = 1948,\n\tIETX_B_MARK___3 = 1949,\n\tSSI_SDATA6_MARK___3 = 1950,\n\tADICHS2_MARK___3 = 1951,\n\tCAN_CLK_MARK___3 = 1952,\n\tIECLK_B_MARK___3 = 1953,\n\tSSI_SCK78_MARK___3 = 1954,\n\tCAN_DEBUGOUT13_MARK = 1955,\n\tIRQ0_B_MARK = 1956,\n\tSSI_SCK9_B_MARK___3 = 1957,\n\tHSPI_CLK1_C_MARK = 1958,\n\tSSI_WS78_MARK___3 = 1959,\n\tCAN_DEBUGOUT14_MARK = 1960,\n\tIRQ1_B_MARK = 1961,\n\tSSI_WS9_B_MARK___3 = 1962,\n\tHSPI_CS1_C_MARK = 1963,\n\tSSI_SDATA7_MARK___3 = 1964,\n\tCAN_DEBUGOUT15_MARK = 1965,\n\tIRQ2_B_MARK = 1966,\n\tTCLK1_C_MARK = 1967,\n\tHSPI_TX1_C_MARK = 1968,\n\tSSI_SDATA8_MARK___3 = 1969,\n\tVSP_MARK = 1970,\n\tIRQ3_B_MARK = 1971,\n\tHSPI_RX1_C_MARK = 1972,\n\tSD0_CLK_MARK___3 = 1973,\n\tATACS01_MARK = 1974,\n\tSCK1_B_MARK = 1975,\n\tSD0_CMD_MARK___3 = 1976,\n\tATACS11_MARK = 1977,\n\tTX1_B_MARK___2 = 1978,\n\tCC5_TDO_MARK = 1979,\n\tSD0_DAT0_MARK = 1980,\n\tATADIR1_MARK = 1981,\n\tRX1_B_MARK___2 = 1982,\n\tCC5_TRST_MARK = 1983,\n\tSD0_DAT1_MARK = 1984,\n\tATAG1_MARK = 1985,\n\tSCK2_B_MARK = 1986,\n\tCC5_TMS_MARK = 1987,\n\tSD0_DAT2_MARK = 1988,\n\tATARD1_MARK = 1989,\n\tTX2_B_MARK___2 = 1990,\n\tCC5_TCK_MARK = 1991,\n\tSD0_DAT3_MARK = 1992,\n\tATAWR1_MARK = 1993,\n\tRX2_B_MARK___2 = 1994,\n\tCC5_TDI_MARK = 1995,\n\tSD0_CD_MARK___3 = 1996,\n\tDREQ2_MARK___3 = 1997,\n\tRTS1_B_TANS_B_MARK = 1998,\n\tSD0_WP_MARK___3 = 1999,\n\tDACK2_MARK___4 = 2000,\n\tCTS1_B_MARK = 2001,\n\tHSPI_CLK0_MARK = 2002,\n\tCTS0_MARK = 2003,\n\tUSB_OVC0_MARK = 2004,\n\tAD_CLK_MARK = 2005,\n\tCC5_STATE4_MARK = 2006,\n\tCC5_STATE12_MARK = 2007,\n\tCC5_STATE20_MARK = 2008,\n\tCC5_STATE28_MARK = 2009,\n\tCC5_STATE36_MARK = 2010,\n\tHSPI_CS0_MARK = 2011,\n\tRTS0_TANS_MARK = 2012,\n\tUSB_OVC1_MARK = 2013,\n\tAD_DI_MARK = 2014,\n\tCC5_STATE5_MARK = 2015,\n\tCC5_STATE13_MARK = 2016,\n\tCC5_STATE21_MARK = 2017,\n\tCC5_STATE29_MARK = 2018,\n\tCC5_STATE37_MARK = 2019,\n\tHSPI_TX0_MARK = 2020,\n\tTX0_MARK___2 = 2021,\n\tCAN_DEBUG_HW_TRIGGER_MARK = 2022,\n\tAD_DO_MARK = 2023,\n\tCC5_STATE6_MARK = 2024,\n\tCC5_STATE14_MARK = 2025,\n\tCC5_STATE22_MARK = 2026,\n\tCC5_STATE30_MARK = 2027,\n\tCC5_STATE38_MARK = 2028,\n\tHSPI_RX0_MARK = 2029,\n\tRX0_MARK___2 = 2030,\n\tCAN_STEP0_MARK = 2031,\n\tAD_NCS_MARK = 2032,\n\tCC5_STATE7_MARK = 2033,\n\tCC5_STATE15_MARK = 2034,\n\tCC5_STATE23_MARK = 2035,\n\tCC5_STATE31_MARK = 2036,\n\tCC5_STATE39_MARK = 2037,\n\tFMCLK_MARK___3 = 2038,\n\tRDS_CLK_MARK = 2039,\n\tPCMOE_MARK = 2040,\n\tBPFCLK_MARK___3 = 2041,\n\tPCMWE_MARK = 2042,\n\tFMIN_MARK___3 = 2043,\n\tRDS_DATA_MARK = 2044,\n\tVI0_CLK_MARK___3 = 2045,\n\tMMC1_CLK_MARK = 2046,\n\tVI0_CLKENB_MARK___3 = 2047,\n\tTX1_C_MARK___2 = 2048,\n\tHTX1_B_MARK___2 = 2049,\n\tMT1_SYNC_MARK = 2050,\n\tVI0_FIELD_MARK___3 = 2051,\n\tRX1_C_MARK___2 = 2052,\n\tHRX1_B_MARK___2 = 2053,\n\tVI0_HSYNC_MARK = 2054,\n\tVI0_DATA0_B_VI0_B0_B_MARK = 2055,\n\tCTS1_C_MARK = 2056,\n\tTX4_D_MARK = 2057,\n\tMMC1_CMD_MARK = 2058,\n\tHSCK1_B_MARK = 2059,\n\tVI0_VSYNC_MARK = 2060,\n\tVI0_DATA1_B_VI0_B1_B_MARK = 2061,\n\tRTS1_C_TANS_C_MARK = 2062,\n\tRX4_D_MARK = 2063,\n\tPWMFSW0_C_MARK = 2064,\n\tVI0_DATA0_VI0_B0_MARK___3 = 2065,\n\tHRTS1_B_MARK = 2066,\n\tMT1_VCXO_MARK = 2067,\n\tVI0_DATA1_VI0_B1_MARK___3 = 2068,\n\tHCTS1_B_MARK = 2069,\n\tMT1_PWM_MARK = 2070,\n\tVI0_DATA2_VI0_B2_MARK___3 = 2071,\n\tMMC1_D0_MARK = 2072,\n\tVI0_DATA3_VI0_B3_MARK___3 = 2073,\n\tMMC1_D1_MARK = 2074,\n\tVI0_DATA4_VI0_B4_MARK___3 = 2075,\n\tMMC1_D2_MARK = 2076,\n\tVI0_DATA5_VI0_B5_MARK___3 = 2077,\n\tMMC1_D3_MARK = 2078,\n\tVI0_DATA6_VI0_B6_MARK___3 = 2079,\n\tMMC1_D4_MARK = 2080,\n\tARM_TRACEDATA_0_MARK = 2081,\n\tVI0_DATA7_VI0_B7_MARK___3 = 2082,\n\tMMC1_D5_MARK = 2083,\n\tARM_TRACEDATA_1_MARK = 2084,\n\tVI0_G0_MARK___3 = 2085,\n\tSSI_SCK78_C_MARK = 2086,\n\tIRQ0_MARK___3 = 2087,\n\tARM_TRACEDATA_2_MARK = 2088,\n\tVI0_G1_MARK___3 = 2089,\n\tSSI_WS78_C_MARK = 2090,\n\tIRQ1_MARK___3 = 2091,\n\tARM_TRACEDATA_3_MARK = 2092,\n\tVI0_G2_MARK___3 = 2093,\n\tETH_TXD1_MARK___3 = 2094,\n\tMMC1_D6_MARK = 2095,\n\tARM_TRACEDATA_4_MARK = 2096,\n\tTS_SPSYNC0_MARK___2 = 2097,\n\tVI0_G3_MARK___3 = 2098,\n\tETH_CRS_DV_MARK___3 = 2099,\n\tMMC1_D7_MARK = 2100,\n\tARM_TRACEDATA_5_MARK = 2101,\n\tTS_SDAT0_MARK = 2102,\n\tVI0_G4_MARK___3 = 2103,\n\tETH_TX_EN_MARK___3 = 2104,\n\tSD2_DAT0_B_MARK = 2105,\n\tARM_TRACEDATA_6_MARK = 2106,\n\tVI0_G5_MARK___3 = 2107,\n\tETH_RX_ER_MARK___3 = 2108,\n\tSD2_DAT1_B_MARK = 2109,\n\tARM_TRACEDATA_7_MARK = 2110,\n\tVI0_G6_MARK___3 = 2111,\n\tETH_RXD0_MARK___3 = 2112,\n\tSD2_DAT2_B_MARK = 2113,\n\tARM_TRACEDATA_8_MARK = 2114,\n\tVI0_G7_MARK___3 = 2115,\n\tETH_RXD1_MARK___3 = 2116,\n\tSD2_DAT3_B_MARK = 2117,\n\tARM_TRACEDATA_9_MARK = 2118,\n\tVI0_R0_MARK___3 = 2119,\n\tSSI_SDATA7_C_MARK = 2120,\n\tSCK1_C_MARK = 2121,\n\tDREQ1_B_MARK = 2122,\n\tARM_TRACEDATA_10_MARK = 2123,\n\tDREQ0_C_MARK = 2124,\n\tVI0_R1_MARK___3 = 2125,\n\tSSI_SDATA8_C_MARK = 2126,\n\tDACK1_B_MARK___2 = 2127,\n\tARM_TRACEDATA_11_MARK = 2128,\n\tDACK0_C_MARK = 2129,\n\tDRACK0_C_MARK = 2130,\n\tVI0_R2_MARK___3 = 2131,\n\tETH_LINK_MARK___3 = 2132,\n\tSD2_CLK_B_MARK = 2133,\n\tIRQ2_MARK___3 = 2134,\n\tARM_TRACEDATA_12_MARK = 2135,\n\tVI0_R3_MARK___3 = 2136,\n\tETH_MAGIC_MARK___3 = 2137,\n\tSD2_CMD_B_MARK = 2138,\n\tIRQ3_MARK___3 = 2139,\n\tARM_TRACEDATA_13_MARK = 2140,\n\tVI0_R4_MARK___3 = 2141,\n\tETH_REFCLK_MARK___3 = 2142,\n\tSD2_CD_B_MARK = 2143,\n\tHSPI_CLK1_B_MARK = 2144,\n\tARM_TRACEDATA_14_MARK = 2145,\n\tMT1_CLK_MARK = 2146,\n\tTS_SCK0_MARK___2 = 2147,\n\tVI0_R5_MARK___3 = 2148,\n\tETH_TXD0_MARK___3 = 2149,\n\tSD2_WP_B_MARK = 2150,\n\tHSPI_CS1_B_MARK = 2151,\n\tARM_TRACEDATA_15_MARK = 2152,\n\tMT1_D_MARK = 2153,\n\tTS_SDEN0_MARK___2 = 2154,\n\tVI0_R6_MARK___3 = 2155,\n\tETH_MDC_MARK___3 = 2156,\n\tDREQ2_C_MARK___2 = 2157,\n\tHSPI_TX1_B_MARK = 2158,\n\tTRACECLK_MARK = 2159,\n\tMT1_BEN_MARK = 2160,\n\tPWMFSW0_D_MARK = 2161,\n\tVI0_R7_MARK___3 = 2162,\n\tETH_MDIO_MARK___3 = 2163,\n\tDACK2_C_MARK = 2164,\n\tHSPI_RX1_B_MARK = 2165,\n\tSCIF_CLK_D_MARK = 2166,\n\tTRACECTL_MARK = 2167,\n\tMT1_PEN_MARK = 2168,\n\tVI1_CLK_MARK___3 = 2169,\n\tSIM_D_MARK___2 = 2170,\n\tSDA3_MARK = 2171,\n\tVI1_HSYNC_MARK = 2172,\n\tVI3_CLK_MARK = 2173,\n\tSSI_SCK4_MARK___3 = 2174,\n\tGPS_SIGN_C_MARK___2 = 2175,\n\tPWMFSW0_E_MARK = 2176,\n\tVI1_VSYNC_MARK = 2177,\n\tAUDIO_CLKOUT_C_MARK___2 = 2178,\n\tSSI_WS4_MARK___3 = 2179,\n\tSIM_CLK_MARK___2 = 2180,\n\tGPS_MAG_C_MARK___2 = 2181,\n\tSPV_TRST_MARK = 2182,\n\tSCL3_MARK = 2183,\n\tVI1_DATA0_VI1_B0_MARK = 2184,\n\tSD2_DAT0_MARK = 2185,\n\tSIM_RST_MARK___2 = 2186,\n\tSPV_TCK_MARK = 2187,\n\tADICLK_B_MARK___3 = 2188,\n\tVI1_DATA1_VI1_B1_MARK = 2189,\n\tSD2_DAT1_MARK = 2190,\n\tMT0_CLK_MARK = 2191,\n\tSPV_TMS_MARK = 2192,\n\tADICS_B_SAMP_B_MARK = 2193,\n\tVI1_DATA2_VI1_B2_MARK = 2194,\n\tSD2_DAT2_MARK = 2195,\n\tMT0_D_MARK = 2196,\n\tSPVTDI_MARK = 2197,\n\tADIDATA_B_MARK___3 = 2198,\n\tVI1_DATA3_VI1_B3_MARK = 2199,\n\tSD2_DAT3_MARK = 2200,\n\tMT0_BEN_MARK = 2201,\n\tSPV_TDO_MARK = 2202,\n\tADICHS0_B_MARK___3 = 2203,\n\tVI1_DATA4_VI1_B4_MARK = 2204,\n\tSD2_CLK_MARK___3 = 2205,\n\tMT0_PEN_MARK = 2206,\n\tSPA_TRST_MARK = 2207,\n\tHSPI_CLK1_D_MARK = 2208,\n\tADICHS1_B_MARK___3 = 2209,\n\tVI1_DATA5_VI1_B5_MARK = 2210,\n\tSD2_CMD_MARK___3 = 2211,\n\tMT0_SYNC_MARK = 2212,\n\tSPA_TCK_MARK = 2213,\n\tHSPI_CS1_D_MARK = 2214,\n\tADICHS2_B_MARK___3 = 2215,\n\tVI1_DATA6_VI1_B6_MARK = 2216,\n\tSD2_CD_MARK___3 = 2217,\n\tMT0_VCXO_MARK = 2218,\n\tSPA_TMS_MARK = 2219,\n\tHSPI_TX1_D_MARK = 2220,\n\tVI1_DATA7_VI1_B7_MARK = 2221,\n\tSD2_WP_MARK___3 = 2222,\n\tMT0_PWM_MARK = 2223,\n\tSPA_TDI_MARK = 2224,\n\tHSPI_RX1_D_MARK = 2225,\n\tVI1_G0_MARK = 2226,\n\tVI3_DATA0_MARK = 2227,\n\tTS_SCK1_MARK___2 = 2228,\n\tDREQ2_B_MARK___2 = 2229,\n\tTX2_MARK___2 = 2230,\n\tSPA_TDO_MARK = 2231,\n\tHCTS0_B_MARK = 2232,\n\tVI1_G1_MARK = 2233,\n\tVI3_DATA1_MARK = 2234,\n\tSSI_SCK1_MARK___3 = 2235,\n\tTS_SDEN1_MARK___2 = 2236,\n\tDACK2_B_MARK___2 = 2237,\n\tRX2_MARK___2 = 2238,\n\tHRTS0_B_MARK = 2239,\n\tVI1_G2_MARK = 2240,\n\tVI3_DATA2_MARK = 2241,\n\tSSI_WS1_MARK___3 = 2242,\n\tTS_SPSYNC1_MARK___2 = 2243,\n\tSCK2_MARK = 2244,\n\tHSCK0_B_MARK = 2245,\n\tVI1_G3_MARK = 2246,\n\tVI3_DATA3_MARK = 2247,\n\tSSI_SCK2_MARK___3 = 2248,\n\tTS_SDAT1_MARK___2 = 2249,\n\tSCL1_C_MARK = 2250,\n\tHTX0_B_MARK___2 = 2251,\n\tVI1_G4_MARK = 2252,\n\tVI3_DATA4_MARK = 2253,\n\tSSI_WS2_MARK___3 = 2254,\n\tSDA1_C_MARK = 2255,\n\tSIM_RST_B_MARK = 2256,\n\tHRX0_B_MARK___2 = 2257,\n\tVI1_G5_MARK = 2258,\n\tVI3_DATA5_MARK = 2259,\n\tGPS_CLK_MARK___2 = 2260,\n\tFSE_MARK = 2261,\n\tTX4_B_MARK___2 = 2262,\n\tSIM_D_B_MARK = 2263,\n\tVI1_G6_MARK = 2264,\n\tVI3_DATA6_MARK = 2265,\n\tGPS_SIGN_MARK___2 = 2266,\n\tFRB_MARK___2 = 2267,\n\tRX4_B_MARK___2 = 2268,\n\tSIM_CLK_B_MARK = 2269,\n\tVI1_G7_MARK = 2270,\n\tVI3_DATA7_MARK = 2271,\n\tGPS_MAG_MARK___2 = 2272,\n\tFCE_MARK = 2273,\n\tSCK4_B_MARK = 2274,\n\tPINMUX_MARK_END___4 = 2275,\n};\n\nenum {\n\tPINMUX_RESERVED___5 = 0,\n\tPINMUX_DATA_BEGIN___5 = 1,\n\tPORT0_DATA___2 = 2,\n\tPORT1_DATA___2 = 3,\n\tPORT2_DATA___2 = 4,\n\tPORT3_DATA___2 = 5,\n\tPORT4_DATA___2 = 6,\n\tPORT5_DATA___2 = 7,\n\tPORT6_DATA___2 = 8,\n\tPORT7_DATA___2 = 9,\n\tPORT8_DATA___2 = 10,\n\tPORT9_DATA___2 = 11,\n\tPORT10_DATA___2 = 12,\n\tPORT11_DATA___2 = 13,\n\tPORT12_DATA___2 = 14,\n\tPORT13_DATA___2 = 15,\n\tPORT14_DATA___2 = 16,\n\tPORT15_DATA___2 = 17,\n\tPORT16_DATA___2 = 18,\n\tPORT17_DATA___2 = 19,\n\tPORT18_DATA___2 = 20,\n\tPORT19_DATA___2 = 21,\n\tPORT20_DATA___2 = 22,\n\tPORT21_DATA___2 = 23,\n\tPORT22_DATA___2 = 24,\n\tPORT23_DATA___2 = 25,\n\tPORT24_DATA___2 = 26,\n\tPORT25_DATA___2 = 27,\n\tPORT26_DATA___2 = 28,\n\tPORT27_DATA___2 = 29,\n\tPORT28_DATA___2 = 30,\n\tPORT29_DATA___2 = 31,\n\tPORT30_DATA___2 = 32,\n\tPORT32_DATA___2 = 33,\n\tPORT33_DATA___2 = 34,\n\tPORT34_DATA___2 = 35,\n\tPORT35_DATA___2 = 36,\n\tPORT36_DATA___2 = 37,\n\tPORT37_DATA___2 = 38,\n\tPORT38_DATA___2 = 39,\n\tPORT39_DATA___2 = 40,\n\tPORT40_DATA___2 = 41,\n\tPORT64_DATA___2 = 42,\n\tPORT65_DATA___2 = 43,\n\tPORT66_DATA___2 = 44,\n\tPORT67_DATA___2 = 45,\n\tPORT68_DATA___2 = 46,\n\tPORT69_DATA___2 = 47,\n\tPORT70_DATA___2 = 48,\n\tPORT71_DATA___2 = 49,\n\tPORT72_DATA___2 = 50,\n\tPORT73_DATA___2 = 51,\n\tPORT74_DATA___2 = 52,\n\tPORT75_DATA___2 = 53,\n\tPORT76_DATA___2 = 54,\n\tPORT77_DATA___2 = 55,\n\tPORT78_DATA___2 = 56,\n\tPORT79_DATA___2 = 57,\n\tPORT80_DATA___2 = 58,\n\tPORT81_DATA___2 = 59,\n\tPORT82_DATA___2 = 60,\n\tPORT83_DATA___2 = 61,\n\tPORT84_DATA___2 = 62,\n\tPORT85_DATA___2 = 63,\n\tPORT96_DATA___2 = 64,\n\tPORT97_DATA___2 = 65,\n\tPORT98_DATA___2 = 66,\n\tPORT99_DATA___2 = 67,\n\tPORT100_DATA___2 = 68,\n\tPORT101_DATA___2 = 69,\n\tPORT102_DATA___2 = 70,\n\tPORT103_DATA___2 = 71,\n\tPORT104_DATA___2 = 72,\n\tPORT105_DATA___2 = 73,\n\tPORT106_DATA___2 = 74,\n\tPORT107_DATA___2 = 75,\n\tPORT108_DATA___2 = 76,\n\tPORT109_DATA___2 = 77,\n\tPORT110_DATA___2 = 78,\n\tPORT111_DATA___2 = 79,\n\tPORT112_DATA___2 = 80,\n\tPORT113_DATA___2 = 81,\n\tPORT114_DATA___2 = 82,\n\tPORT115_DATA___2 = 83,\n\tPORT116_DATA___2 = 84,\n\tPORT117_DATA___2 = 85,\n\tPORT118_DATA___2 = 86,\n\tPORT119_DATA = 87,\n\tPORT120_DATA = 88,\n\tPORT121_DATA = 89,\n\tPORT122_DATA = 90,\n\tPORT123_DATA = 91,\n\tPORT124_DATA = 92,\n\tPORT125_DATA = 93,\n\tPORT126_DATA = 94,\n\tPORT128_DATA___2 = 95,\n\tPORT129_DATA___2 = 96,\n\tPORT130_DATA___2 = 97,\n\tPORT131_DATA___2 = 98,\n\tPORT132_DATA___2 = 99,\n\tPORT133_DATA___2 = 100,\n\tPORT134_DATA___2 = 101,\n\tPORT160_DATA___2 = 102,\n\tPORT161_DATA___2 = 103,\n\tPORT162_DATA___2 = 104,\n\tPORT163_DATA___2 = 105,\n\tPORT164_DATA___2 = 106,\n\tPORT165_DATA = 107,\n\tPORT166_DATA = 108,\n\tPORT167_DATA = 109,\n\tPORT168_DATA = 110,\n\tPORT169_DATA = 111,\n\tPORT170_DATA = 112,\n\tPORT171_DATA = 113,\n\tPORT172_DATA = 114,\n\tPORT173_DATA = 115,\n\tPORT174_DATA = 116,\n\tPORT175_DATA = 117,\n\tPORT176_DATA = 118,\n\tPORT177_DATA = 119,\n\tPORT178_DATA = 120,\n\tPORT192_DATA___2 = 121,\n\tPORT193_DATA___2 = 122,\n\tPORT194_DATA___2 = 123,\n\tPORT195_DATA___2 = 124,\n\tPORT196_DATA___2 = 125,\n\tPORT197_DATA___2 = 126,\n\tPORT198_DATA___2 = 127,\n\tPORT199_DATA___2 = 128,\n\tPORT200_DATA___2 = 129,\n\tPORT201_DATA___2 = 130,\n\tPORT202_DATA___2 = 131,\n\tPORT203_DATA___2 = 132,\n\tPORT204_DATA___2 = 133,\n\tPORT205_DATA___2 = 134,\n\tPORT206_DATA___2 = 135,\n\tPORT207_DATA___2 = 136,\n\tPORT208_DATA___2 = 137,\n\tPORT209_DATA___2 = 138,\n\tPORT210_DATA___2 = 139,\n\tPORT211_DATA___2 = 140,\n\tPORT212_DATA___2 = 141,\n\tPORT213_DATA___2 = 142,\n\tPORT214_DATA___2 = 143,\n\tPORT215_DATA___2 = 144,\n\tPORT216_DATA___2 = 145,\n\tPORT217_DATA___2 = 146,\n\tPORT218_DATA___2 = 147,\n\tPORT219_DATA___2 = 148,\n\tPORT220_DATA___2 = 149,\n\tPORT221_DATA___2 = 150,\n\tPORT222_DATA___2 = 151,\n\tPORT224_DATA___2 = 152,\n\tPORT225_DATA___2 = 153,\n\tPORT226_DATA___2 = 154,\n\tPORT227_DATA___2 = 155,\n\tPORT228_DATA___2 = 156,\n\tPORT229_DATA___2 = 157,\n\tPORT230_DATA___2 = 158,\n\tPORT231_DATA___2 = 159,\n\tPORT232_DATA___2 = 160,\n\tPORT233_DATA___2 = 161,\n\tPORT234_DATA___2 = 162,\n\tPORT235_DATA___2 = 163,\n\tPORT236_DATA___2 = 164,\n\tPORT237_DATA___2 = 165,\n\tPORT238_DATA___2 = 166,\n\tPORT239_DATA___2 = 167,\n\tPORT240_DATA___2 = 168,\n\tPORT241_DATA___2 = 169,\n\tPORT242_DATA___2 = 170,\n\tPORT243_DATA___2 = 171,\n\tPORT244_DATA___2 = 172,\n\tPORT245_DATA___2 = 173,\n\tPORT246_DATA___2 = 174,\n\tPORT247_DATA___2 = 175,\n\tPORT248_DATA___2 = 176,\n\tPORT249_DATA___2 = 177,\n\tPORT250_DATA___2 = 178,\n\tPORT256_DATA___2 = 179,\n\tPORT257_DATA___2 = 180,\n\tPORT258_DATA___2 = 181,\n\tPORT259_DATA___2 = 182,\n\tPORT260_DATA___2 = 183,\n\tPORT261_DATA___2 = 184,\n\tPORT262_DATA___2 = 185,\n\tPORT263_DATA___2 = 186,\n\tPORT264_DATA___2 = 187,\n\tPORT265_DATA___2 = 188,\n\tPORT266_DATA___2 = 189,\n\tPORT267_DATA___2 = 190,\n\tPORT268_DATA___2 = 191,\n\tPORT269_DATA___2 = 192,\n\tPORT270_DATA___2 = 193,\n\tPORT271_DATA___2 = 194,\n\tPORT272_DATA___2 = 195,\n\tPORT273_DATA___2 = 196,\n\tPORT274_DATA___2 = 197,\n\tPORT275_DATA___2 = 198,\n\tPORT276_DATA___2 = 199,\n\tPORT277_DATA___2 = 200,\n\tPORT278_DATA___2 = 201,\n\tPORT279_DATA___2 = 202,\n\tPORT280_DATA___2 = 203,\n\tPORT281_DATA___2 = 204,\n\tPORT282_DATA___2 = 205,\n\tPORT283_DATA = 206,\n\tPORT288_DATA___2 = 207,\n\tPORT289_DATA___2 = 208,\n\tPORT290_DATA___2 = 209,\n\tPORT291_DATA___2 = 210,\n\tPORT292_DATA___2 = 211,\n\tPORT293_DATA___2 = 212,\n\tPORT294_DATA___2 = 213,\n\tPORT295_DATA___2 = 214,\n\tPORT296_DATA___2 = 215,\n\tPORT297_DATA___2 = 216,\n\tPORT298_DATA___2 = 217,\n\tPORT299_DATA___2 = 218,\n\tPORT300_DATA___2 = 219,\n\tPORT301_DATA___2 = 220,\n\tPORT302_DATA___2 = 221,\n\tPORT303_DATA___2 = 222,\n\tPORT304_DATA___2 = 223,\n\tPORT305_DATA___2 = 224,\n\tPORT306_DATA___2 = 225,\n\tPORT307_DATA___2 = 226,\n\tPORT308_DATA___2 = 227,\n\tPORT320_DATA = 228,\n\tPORT321_DATA = 229,\n\tPORT322_DATA = 230,\n\tPORT323_DATA = 231,\n\tPORT324_DATA = 232,\n\tPORT325_DATA = 233,\n\tPORT326_DATA = 234,\n\tPORT327_DATA = 235,\n\tPORT328_DATA = 236,\n\tPORT329_DATA = 237,\n\tPINMUX_DATA_END___5 = 238,\n\tPINMUX_INPUT_BEGIN___2 = 239,\n\tPORT0_IN___2 = 240,\n\tPORT1_IN___2 = 241,\n\tPORT2_IN___2 = 242,\n\tPORT3_IN___2 = 243,\n\tPORT4_IN___2 = 244,\n\tPORT5_IN___2 = 245,\n\tPORT6_IN___2 = 246,\n\tPORT7_IN___2 = 247,\n\tPORT8_IN___2 = 248,\n\tPORT9_IN___2 = 249,\n\tPORT10_IN___2 = 250,\n\tPORT11_IN___2 = 251,\n\tPORT12_IN___2 = 252,\n\tPORT13_IN___2 = 253,\n\tPORT14_IN___2 = 254,\n\tPORT15_IN___2 = 255,\n\tPORT16_IN___2 = 256,\n\tPORT17_IN___2 = 257,\n\tPORT18_IN___2 = 258,\n\tPORT19_IN___2 = 259,\n\tPORT20_IN___2 = 260,\n\tPORT21_IN___2 = 261,\n\tPORT22_IN___2 = 262,\n\tPORT23_IN___2 = 263,\n\tPORT24_IN___2 = 264,\n\tPORT25_IN___2 = 265,\n\tPORT26_IN___2 = 266,\n\tPORT27_IN___2 = 267,\n\tPORT28_IN___2 = 268,\n\tPORT29_IN___2 = 269,\n\tPORT30_IN___2 = 270,\n\tPORT32_IN___2 = 271,\n\tPORT33_IN___2 = 272,\n\tPORT34_IN___2 = 273,\n\tPORT35_IN___2 = 274,\n\tPORT36_IN___2 = 275,\n\tPORT37_IN___2 = 276,\n\tPORT38_IN___2 = 277,\n\tPORT39_IN___2 = 278,\n\tPORT40_IN___2 = 279,\n\tPORT64_IN___2 = 280,\n\tPORT65_IN___2 = 281,\n\tPORT66_IN___2 = 282,\n\tPORT67_IN___2 = 283,\n\tPORT68_IN___2 = 284,\n\tPORT69_IN___2 = 285,\n\tPORT70_IN___2 = 286,\n\tPORT71_IN___2 = 287,\n\tPORT72_IN___2 = 288,\n\tPORT73_IN___2 = 289,\n\tPORT74_IN___2 = 290,\n\tPORT75_IN___2 = 291,\n\tPORT76_IN___2 = 292,\n\tPORT77_IN___2 = 293,\n\tPORT78_IN___2 = 294,\n\tPORT79_IN___2 = 295,\n\tPORT80_IN___2 = 296,\n\tPORT81_IN___2 = 297,\n\tPORT82_IN___2 = 298,\n\tPORT83_IN___2 = 299,\n\tPORT84_IN___2 = 300,\n\tPORT85_IN___2 = 301,\n\tPORT96_IN___2 = 302,\n\tPORT97_IN___2 = 303,\n\tPORT98_IN___2 = 304,\n\tPORT99_IN___2 = 305,\n\tPORT100_IN___2 = 306,\n\tPORT101_IN___2 = 307,\n\tPORT102_IN___2 = 308,\n\tPORT103_IN___2 = 309,\n\tPORT104_IN___2 = 310,\n\tPORT105_IN___2 = 311,\n\tPORT106_IN___2 = 312,\n\tPORT107_IN___2 = 313,\n\tPORT108_IN___2 = 314,\n\tPORT109_IN___2 = 315,\n\tPORT110_IN___2 = 316,\n\tPORT111_IN___2 = 317,\n\tPORT112_IN___2 = 318,\n\tPORT113_IN___2 = 319,\n\tPORT114_IN___2 = 320,\n\tPORT115_IN___2 = 321,\n\tPORT116_IN___2 = 322,\n\tPORT117_IN___2 = 323,\n\tPORT118_IN___2 = 324,\n\tPORT119_IN = 325,\n\tPORT120_IN = 326,\n\tPORT121_IN = 327,\n\tPORT122_IN = 328,\n\tPORT123_IN = 329,\n\tPORT124_IN = 330,\n\tPORT125_IN = 331,\n\tPORT126_IN = 332,\n\tPORT128_IN___2 = 333,\n\tPORT129_IN___2 = 334,\n\tPORT130_IN___2 = 335,\n\tPORT131_IN___2 = 336,\n\tPORT132_IN___2 = 337,\n\tPORT133_IN___2 = 338,\n\tPORT134_IN___2 = 339,\n\tPORT160_IN___2 = 340,\n\tPORT161_IN___2 = 341,\n\tPORT162_IN___2 = 342,\n\tPORT163_IN___2 = 343,\n\tPORT164_IN___2 = 344,\n\tPORT165_IN = 345,\n\tPORT166_IN = 346,\n\tPORT167_IN = 347,\n\tPORT168_IN = 348,\n\tPORT169_IN = 349,\n\tPORT170_IN = 350,\n\tPORT171_IN = 351,\n\tPORT172_IN = 352,\n\tPORT173_IN = 353,\n\tPORT174_IN = 354,\n\tPORT175_IN = 355,\n\tPORT176_IN = 356,\n\tPORT177_IN = 357,\n\tPORT178_IN = 358,\n\tPORT192_IN___2 = 359,\n\tPORT193_IN___2 = 360,\n\tPORT194_IN___2 = 361,\n\tPORT195_IN___2 = 362,\n\tPORT196_IN___2 = 363,\n\tPORT197_IN___2 = 364,\n\tPORT198_IN___2 = 365,\n\tPORT199_IN___2 = 366,\n\tPORT200_IN___2 = 367,\n\tPORT201_IN___2 = 368,\n\tPORT202_IN___2 = 369,\n\tPORT203_IN___2 = 370,\n\tPORT204_IN___2 = 371,\n\tPORT205_IN___2 = 372,\n\tPORT206_IN___2 = 373,\n\tPORT207_IN___2 = 374,\n\tPORT208_IN___2 = 375,\n\tPORT209_IN___2 = 376,\n\tPORT210_IN___2 = 377,\n\tPORT211_IN___2 = 378,\n\tPORT212_IN___2 = 379,\n\tPORT213_IN___2 = 380,\n\tPORT214_IN___2 = 381,\n\tPORT215_IN___2 = 382,\n\tPORT216_IN___2 = 383,\n\tPORT217_IN___2 = 384,\n\tPORT218_IN___2 = 385,\n\tPORT219_IN___2 = 386,\n\tPORT220_IN___2 = 387,\n\tPORT221_IN___2 = 388,\n\tPORT222_IN___2 = 389,\n\tPORT224_IN___2 = 390,\n\tPORT225_IN___2 = 391,\n\tPORT226_IN___2 = 392,\n\tPORT227_IN___2 = 393,\n\tPORT228_IN___2 = 394,\n\tPORT229_IN___2 = 395,\n\tPORT230_IN___2 = 396,\n\tPORT231_IN___2 = 397,\n\tPORT232_IN___2 = 398,\n\tPORT233_IN___2 = 399,\n\tPORT234_IN___2 = 400,\n\tPORT235_IN___2 = 401,\n\tPORT236_IN___2 = 402,\n\tPORT237_IN___2 = 403,\n\tPORT238_IN___2 = 404,\n\tPORT239_IN___2 = 405,\n\tPORT240_IN___2 = 406,\n\tPORT241_IN___2 = 407,\n\tPORT242_IN___2 = 408,\n\tPORT243_IN___2 = 409,\n\tPORT244_IN___2 = 410,\n\tPORT245_IN___2 = 411,\n\tPORT246_IN___2 = 412,\n\tPORT247_IN___2 = 413,\n\tPORT248_IN___2 = 414,\n\tPORT249_IN___2 = 415,\n\tPORT250_IN___2 = 416,\n\tPORT256_IN___2 = 417,\n\tPORT257_IN___2 = 418,\n\tPORT258_IN___2 = 419,\n\tPORT259_IN___2 = 420,\n\tPORT260_IN___2 = 421,\n\tPORT261_IN___2 = 422,\n\tPORT262_IN___2 = 423,\n\tPORT263_IN___2 = 424,\n\tPORT264_IN___2 = 425,\n\tPORT265_IN___2 = 426,\n\tPORT266_IN___2 = 427,\n\tPORT267_IN___2 = 428,\n\tPORT268_IN___2 = 429,\n\tPORT269_IN___2 = 430,\n\tPORT270_IN___2 = 431,\n\tPORT271_IN___2 = 432,\n\tPORT272_IN___2 = 433,\n\tPORT273_IN___2 = 434,\n\tPORT274_IN___2 = 435,\n\tPORT275_IN___2 = 436,\n\tPORT276_IN___2 = 437,\n\tPORT277_IN___2 = 438,\n\tPORT278_IN___2 = 439,\n\tPORT279_IN___2 = 440,\n\tPORT280_IN___2 = 441,\n\tPORT281_IN___2 = 442,\n\tPORT282_IN___2 = 443,\n\tPORT283_IN = 444,\n\tPORT288_IN___2 = 445,\n\tPORT289_IN___2 = 446,\n\tPORT290_IN___2 = 447,\n\tPORT291_IN___2 = 448,\n\tPORT292_IN___2 = 449,\n\tPORT293_IN___2 = 450,\n\tPORT294_IN___2 = 451,\n\tPORT295_IN___2 = 452,\n\tPORT296_IN___2 = 453,\n\tPORT297_IN___2 = 454,\n\tPORT298_IN___2 = 455,\n\tPORT299_IN___2 = 456,\n\tPORT300_IN___2 = 457,\n\tPORT301_IN___2 = 458,\n\tPORT302_IN___2 = 459,\n\tPORT303_IN___2 = 460,\n\tPORT304_IN___2 = 461,\n\tPORT305_IN___2 = 462,\n\tPORT306_IN___2 = 463,\n\tPORT307_IN___2 = 464,\n\tPORT308_IN___2 = 465,\n\tPORT320_IN = 466,\n\tPORT321_IN = 467,\n\tPORT322_IN = 468,\n\tPORT323_IN = 469,\n\tPORT324_IN = 470,\n\tPORT325_IN = 471,\n\tPORT326_IN = 472,\n\tPORT327_IN = 473,\n\tPORT328_IN = 474,\n\tPORT329_IN = 475,\n\tPINMUX_INPUT_END___2 = 476,\n\tPINMUX_OUTPUT_BEGIN___2 = 477,\n\tPORT0_OUT___2 = 478,\n\tPORT1_OUT___2 = 479,\n\tPORT2_OUT___2 = 480,\n\tPORT3_OUT___2 = 481,\n\tPORT4_OUT___2 = 482,\n\tPORT5_OUT___2 = 483,\n\tPORT6_OUT___2 = 484,\n\tPORT7_OUT___2 = 485,\n\tPORT8_OUT___2 = 486,\n\tPORT9_OUT___2 = 487,\n\tPORT10_OUT___2 = 488,\n\tPORT11_OUT___2 = 489,\n\tPORT12_OUT___2 = 490,\n\tPORT13_OUT___2 = 491,\n\tPORT14_OUT___2 = 492,\n\tPORT15_OUT___2 = 493,\n\tPORT16_OUT___2 = 494,\n\tPORT17_OUT___2 = 495,\n\tPORT18_OUT___2 = 496,\n\tPORT19_OUT___2 = 497,\n\tPORT20_OUT___2 = 498,\n\tPORT21_OUT___2 = 499,\n\tPORT22_OUT___2 = 500,\n\tPORT23_OUT___2 = 501,\n\tPORT24_OUT___2 = 502,\n\tPORT25_OUT___2 = 503,\n\tPORT26_OUT___2 = 504,\n\tPORT27_OUT___2 = 505,\n\tPORT28_OUT___2 = 506,\n\tPORT29_OUT___2 = 507,\n\tPORT30_OUT___2 = 508,\n\tPORT32_OUT___2 = 509,\n\tPORT33_OUT___2 = 510,\n\tPORT34_OUT___2 = 511,\n\tPORT35_OUT___2 = 512,\n\tPORT36_OUT___2 = 513,\n\tPORT37_OUT___2 = 514,\n\tPORT38_OUT___2 = 515,\n\tPORT39_OUT___2 = 516,\n\tPORT40_OUT___2 = 517,\n\tPORT64_OUT___2 = 518,\n\tPORT65_OUT___2 = 519,\n\tPORT66_OUT___2 = 520,\n\tPORT67_OUT___2 = 521,\n\tPORT68_OUT___2 = 522,\n\tPORT69_OUT___2 = 523,\n\tPORT70_OUT___2 = 524,\n\tPORT71_OUT___2 = 525,\n\tPORT72_OUT___2 = 526,\n\tPORT73_OUT___2 = 527,\n\tPORT74_OUT___2 = 528,\n\tPORT75_OUT___2 = 529,\n\tPORT76_OUT___2 = 530,\n\tPORT77_OUT___2 = 531,\n\tPORT78_OUT___2 = 532,\n\tPORT79_OUT___2 = 533,\n\tPORT80_OUT___2 = 534,\n\tPORT81_OUT___2 = 535,\n\tPORT82_OUT___2 = 536,\n\tPORT83_OUT___2 = 537,\n\tPORT84_OUT___2 = 538,\n\tPORT85_OUT___2 = 539,\n\tPORT96_OUT___2 = 540,\n\tPORT97_OUT___2 = 541,\n\tPORT98_OUT___2 = 542,\n\tPORT99_OUT___2 = 543,\n\tPORT100_OUT___2 = 544,\n\tPORT101_OUT___2 = 545,\n\tPORT102_OUT___2 = 546,\n\tPORT103_OUT___2 = 547,\n\tPORT104_OUT___2 = 548,\n\tPORT105_OUT___2 = 549,\n\tPORT106_OUT___2 = 550,\n\tPORT107_OUT___2 = 551,\n\tPORT108_OUT___2 = 552,\n\tPORT109_OUT___2 = 553,\n\tPORT110_OUT___2 = 554,\n\tPORT111_OUT___2 = 555,\n\tPORT112_OUT___2 = 556,\n\tPORT113_OUT___2 = 557,\n\tPORT114_OUT___2 = 558,\n\tPORT115_OUT___2 = 559,\n\tPORT116_OUT___2 = 560,\n\tPORT117_OUT___2 = 561,\n\tPORT118_OUT___2 = 562,\n\tPORT119_OUT = 563,\n\tPORT120_OUT = 564,\n\tPORT121_OUT = 565,\n\tPORT122_OUT = 566,\n\tPORT123_OUT = 567,\n\tPORT124_OUT = 568,\n\tPORT125_OUT = 569,\n\tPORT126_OUT = 570,\n\tPORT128_OUT___2 = 571,\n\tPORT129_OUT___2 = 572,\n\tPORT130_OUT___2 = 573,\n\tPORT131_OUT___2 = 574,\n\tPORT132_OUT___2 = 575,\n\tPORT133_OUT___2 = 576,\n\tPORT134_OUT___2 = 577,\n\tPORT160_OUT___2 = 578,\n\tPORT161_OUT___2 = 579,\n\tPORT162_OUT___2 = 580,\n\tPORT163_OUT___2 = 581,\n\tPORT164_OUT___2 = 582,\n\tPORT165_OUT = 583,\n\tPORT166_OUT = 584,\n\tPORT167_OUT = 585,\n\tPORT168_OUT = 586,\n\tPORT169_OUT = 587,\n\tPORT170_OUT = 588,\n\tPORT171_OUT = 589,\n\tPORT172_OUT = 590,\n\tPORT173_OUT = 591,\n\tPORT174_OUT = 592,\n\tPORT175_OUT = 593,\n\tPORT176_OUT = 594,\n\tPORT177_OUT = 595,\n\tPORT178_OUT = 596,\n\tPORT192_OUT___2 = 597,\n\tPORT193_OUT___2 = 598,\n\tPORT194_OUT___2 = 599,\n\tPORT195_OUT___2 = 600,\n\tPORT196_OUT___2 = 601,\n\tPORT197_OUT___2 = 602,\n\tPORT198_OUT___2 = 603,\n\tPORT199_OUT___2 = 604,\n\tPORT200_OUT___2 = 605,\n\tPORT201_OUT___2 = 606,\n\tPORT202_OUT___2 = 607,\n\tPORT203_OUT___2 = 608,\n\tPORT204_OUT___2 = 609,\n\tPORT205_OUT___2 = 610,\n\tPORT206_OUT___2 = 611,\n\tPORT207_OUT___2 = 612,\n\tPORT208_OUT___2 = 613,\n\tPORT209_OUT___2 = 614,\n\tPORT210_OUT___2 = 615,\n\tPORT211_OUT___2 = 616,\n\tPORT212_OUT___2 = 617,\n\tPORT213_OUT___2 = 618,\n\tPORT214_OUT___2 = 619,\n\tPORT215_OUT___2 = 620,\n\tPORT216_OUT___2 = 621,\n\tPORT217_OUT___2 = 622,\n\tPORT218_OUT___2 = 623,\n\tPORT219_OUT___2 = 624,\n\tPORT220_OUT___2 = 625,\n\tPORT221_OUT___2 = 626,\n\tPORT222_OUT___2 = 627,\n\tPORT224_OUT___2 = 628,\n\tPORT225_OUT___2 = 629,\n\tPORT226_OUT___2 = 630,\n\tPORT227_OUT___2 = 631,\n\tPORT228_OUT___2 = 632,\n\tPORT229_OUT___2 = 633,\n\tPORT230_OUT___2 = 634,\n\tPORT231_OUT___2 = 635,\n\tPORT232_OUT___2 = 636,\n\tPORT233_OUT___2 = 637,\n\tPORT234_OUT___2 = 638,\n\tPORT235_OUT___2 = 639,\n\tPORT236_OUT___2 = 640,\n\tPORT237_OUT___2 = 641,\n\tPORT238_OUT___2 = 642,\n\tPORT239_OUT___2 = 643,\n\tPORT240_OUT___2 = 644,\n\tPORT241_OUT___2 = 645,\n\tPORT242_OUT___2 = 646,\n\tPORT243_OUT___2 = 647,\n\tPORT244_OUT___2 = 648,\n\tPORT245_OUT___2 = 649,\n\tPORT246_OUT___2 = 650,\n\tPORT247_OUT___2 = 651,\n\tPORT248_OUT___2 = 652,\n\tPORT249_OUT___2 = 653,\n\tPORT250_OUT___2 = 654,\n\tPORT256_OUT___2 = 655,\n\tPORT257_OUT___2 = 656,\n\tPORT258_OUT___2 = 657,\n\tPORT259_OUT___2 = 658,\n\tPORT260_OUT___2 = 659,\n\tPORT261_OUT___2 = 660,\n\tPORT262_OUT___2 = 661,\n\tPORT263_OUT___2 = 662,\n\tPORT264_OUT___2 = 663,\n\tPORT265_OUT___2 = 664,\n\tPORT266_OUT___2 = 665,\n\tPORT267_OUT___2 = 666,\n\tPORT268_OUT___2 = 667,\n\tPORT269_OUT___2 = 668,\n\tPORT270_OUT___2 = 669,\n\tPORT271_OUT___2 = 670,\n\tPORT272_OUT___2 = 671,\n\tPORT273_OUT___2 = 672,\n\tPORT274_OUT___2 = 673,\n\tPORT275_OUT___2 = 674,\n\tPORT276_OUT___2 = 675,\n\tPORT277_OUT___2 = 676,\n\tPORT278_OUT___2 = 677,\n\tPORT279_OUT___2 = 678,\n\tPORT280_OUT___2 = 679,\n\tPORT281_OUT___2 = 680,\n\tPORT282_OUT___2 = 681,\n\tPORT283_OUT = 682,\n\tPORT288_OUT___2 = 683,\n\tPORT289_OUT___2 = 684,\n\tPORT290_OUT___2 = 685,\n\tPORT291_OUT___2 = 686,\n\tPORT292_OUT___2 = 687,\n\tPORT293_OUT___2 = 688,\n\tPORT294_OUT___2 = 689,\n\tPORT295_OUT___2 = 690,\n\tPORT296_OUT___2 = 691,\n\tPORT297_OUT___2 = 692,\n\tPORT298_OUT___2 = 693,\n\tPORT299_OUT___2 = 694,\n\tPORT300_OUT___2 = 695,\n\tPORT301_OUT___2 = 696,\n\tPORT302_OUT___2 = 697,\n\tPORT303_OUT___2 = 698,\n\tPORT304_OUT___2 = 699,\n\tPORT305_OUT___2 = 700,\n\tPORT306_OUT___2 = 701,\n\tPORT307_OUT___2 = 702,\n\tPORT308_OUT___2 = 703,\n\tPORT320_OUT = 704,\n\tPORT321_OUT = 705,\n\tPORT322_OUT = 706,\n\tPORT323_OUT = 707,\n\tPORT324_OUT = 708,\n\tPORT325_OUT = 709,\n\tPORT326_OUT = 710,\n\tPORT327_OUT = 711,\n\tPORT328_OUT = 712,\n\tPORT329_OUT = 713,\n\tPINMUX_OUTPUT_END___2 = 714,\n\tPINMUX_FUNCTION_BEGIN___5 = 715,\n\tPORT0_FN_IN___2 = 716,\n\tPORT1_FN_IN___2 = 717,\n\tPORT2_FN_IN___2 = 718,\n\tPORT3_FN_IN___2 = 719,\n\tPORT4_FN_IN___2 = 720,\n\tPORT5_FN_IN___2 = 721,\n\tPORT6_FN_IN___2 = 722,\n\tPORT7_FN_IN___2 = 723,\n\tPORT8_FN_IN___2 = 724,\n\tPORT9_FN_IN___2 = 725,\n\tPORT10_FN_IN___2 = 726,\n\tPORT11_FN_IN___2 = 727,\n\tPORT12_FN_IN___2 = 728,\n\tPORT13_FN_IN___2 = 729,\n\tPORT14_FN_IN___2 = 730,\n\tPORT15_FN_IN___2 = 731,\n\tPORT16_FN_IN___2 = 732,\n\tPORT17_FN_IN___2 = 733,\n\tPORT18_FN_IN___2 = 734,\n\tPORT19_FN_IN___2 = 735,\n\tPORT20_FN_IN___2 = 736,\n\tPORT21_FN_IN___2 = 737,\n\tPORT22_FN_IN___2 = 738,\n\tPORT23_FN_IN___2 = 739,\n\tPORT24_FN_IN___2 = 740,\n\tPORT25_FN_IN___2 = 741,\n\tPORT26_FN_IN___2 = 742,\n\tPORT27_FN_IN___2 = 743,\n\tPORT28_FN_IN___2 = 744,\n\tPORT29_FN_IN___2 = 745,\n\tPORT30_FN_IN___2 = 746,\n\tPORT32_FN_IN___2 = 747,\n\tPORT33_FN_IN___2 = 748,\n\tPORT34_FN_IN___2 = 749,\n\tPORT35_FN_IN___2 = 750,\n\tPORT36_FN_IN___2 = 751,\n\tPORT37_FN_IN___2 = 752,\n\tPORT38_FN_IN___2 = 753,\n\tPORT39_FN_IN___2 = 754,\n\tPORT40_FN_IN___2 = 755,\n\tPORT64_FN_IN___2 = 756,\n\tPORT65_FN_IN___2 = 757,\n\tPORT66_FN_IN___2 = 758,\n\tPORT67_FN_IN___2 = 759,\n\tPORT68_FN_IN___2 = 760,\n\tPORT69_FN_IN___2 = 761,\n\tPORT70_FN_IN___2 = 762,\n\tPORT71_FN_IN___2 = 763,\n\tPORT72_FN_IN___2 = 764,\n\tPORT73_FN_IN___2 = 765,\n\tPORT74_FN_IN___2 = 766,\n\tPORT75_FN_IN___2 = 767,\n\tPORT76_FN_IN___2 = 768,\n\tPORT77_FN_IN___2 = 769,\n\tPORT78_FN_IN___2 = 770,\n\tPORT79_FN_IN___2 = 771,\n\tPORT80_FN_IN___2 = 772,\n\tPORT81_FN_IN___2 = 773,\n\tPORT82_FN_IN___2 = 774,\n\tPORT83_FN_IN___2 = 775,\n\tPORT84_FN_IN___2 = 776,\n\tPORT85_FN_IN___2 = 777,\n\tPORT96_FN_IN___2 = 778,\n\tPORT97_FN_IN___2 = 779,\n\tPORT98_FN_IN___2 = 780,\n\tPORT99_FN_IN___2 = 781,\n\tPORT100_FN_IN___2 = 782,\n\tPORT101_FN_IN___2 = 783,\n\tPORT102_FN_IN___2 = 784,\n\tPORT103_FN_IN___2 = 785,\n\tPORT104_FN_IN___2 = 786,\n\tPORT105_FN_IN___2 = 787,\n\tPORT106_FN_IN___2 = 788,\n\tPORT107_FN_IN___2 = 789,\n\tPORT108_FN_IN___2 = 790,\n\tPORT109_FN_IN___2 = 791,\n\tPORT110_FN_IN___2 = 792,\n\tPORT111_FN_IN___2 = 793,\n\tPORT112_FN_IN___2 = 794,\n\tPORT113_FN_IN___2 = 795,\n\tPORT114_FN_IN___2 = 796,\n\tPORT115_FN_IN___2 = 797,\n\tPORT116_FN_IN___2 = 798,\n\tPORT117_FN_IN___2 = 799,\n\tPORT118_FN_IN___2 = 800,\n\tPORT119_FN_IN = 801,\n\tPORT120_FN_IN = 802,\n\tPORT121_FN_IN = 803,\n\tPORT122_FN_IN = 804,\n\tPORT123_FN_IN = 805,\n\tPORT124_FN_IN = 806,\n\tPORT125_FN_IN = 807,\n\tPORT126_FN_IN = 808,\n\tPORT128_FN_IN___2 = 809,\n\tPORT129_FN_IN___2 = 810,\n\tPORT130_FN_IN___2 = 811,\n\tPORT131_FN_IN___2 = 812,\n\tPORT132_FN_IN___2 = 813,\n\tPORT133_FN_IN___2 = 814,\n\tPORT134_FN_IN___2 = 815,\n\tPORT160_FN_IN___2 = 816,\n\tPORT161_FN_IN___2 = 817,\n\tPORT162_FN_IN___2 = 818,\n\tPORT163_FN_IN___2 = 819,\n\tPORT164_FN_IN___2 = 820,\n\tPORT165_FN_IN = 821,\n\tPORT166_FN_IN = 822,\n\tPORT167_FN_IN = 823,\n\tPORT168_FN_IN = 824,\n\tPORT169_FN_IN = 825,\n\tPORT170_FN_IN = 826,\n\tPORT171_FN_IN = 827,\n\tPORT172_FN_IN = 828,\n\tPORT173_FN_IN = 829,\n\tPORT174_FN_IN = 830,\n\tPORT175_FN_IN = 831,\n\tPORT176_FN_IN = 832,\n\tPORT177_FN_IN = 833,\n\tPORT178_FN_IN = 834,\n\tPORT192_FN_IN___2 = 835,\n\tPORT193_FN_IN___2 = 836,\n\tPORT194_FN_IN___2 = 837,\n\tPORT195_FN_IN___2 = 838,\n\tPORT196_FN_IN___2 = 839,\n\tPORT197_FN_IN___2 = 840,\n\tPORT198_FN_IN___2 = 841,\n\tPORT199_FN_IN___2 = 842,\n\tPORT200_FN_IN___2 = 843,\n\tPORT201_FN_IN___2 = 844,\n\tPORT202_FN_IN___2 = 845,\n\tPORT203_FN_IN___2 = 846,\n\tPORT204_FN_IN___2 = 847,\n\tPORT205_FN_IN___2 = 848,\n\tPORT206_FN_IN___2 = 849,\n\tPORT207_FN_IN___2 = 850,\n\tPORT208_FN_IN___2 = 851,\n\tPORT209_FN_IN___2 = 852,\n\tPORT210_FN_IN___2 = 853,\n\tPORT211_FN_IN___2 = 854,\n\tPORT212_FN_IN___2 = 855,\n\tPORT213_FN_IN___2 = 856,\n\tPORT214_FN_IN___2 = 857,\n\tPORT215_FN_IN___2 = 858,\n\tPORT216_FN_IN___2 = 859,\n\tPORT217_FN_IN___2 = 860,\n\tPORT218_FN_IN___2 = 861,\n\tPORT219_FN_IN___2 = 862,\n\tPORT220_FN_IN___2 = 863,\n\tPORT221_FN_IN___2 = 864,\n\tPORT222_FN_IN___2 = 865,\n\tPORT224_FN_IN___2 = 866,\n\tPORT225_FN_IN___2 = 867,\n\tPORT226_FN_IN___2 = 868,\n\tPORT227_FN_IN___2 = 869,\n\tPORT228_FN_IN___2 = 870,\n\tPORT229_FN_IN___2 = 871,\n\tPORT230_FN_IN___2 = 872,\n\tPORT231_FN_IN___2 = 873,\n\tPORT232_FN_IN___2 = 874,\n\tPORT233_FN_IN___2 = 875,\n\tPORT234_FN_IN___2 = 876,\n\tPORT235_FN_IN___2 = 877,\n\tPORT236_FN_IN___2 = 878,\n\tPORT237_FN_IN___2 = 879,\n\tPORT238_FN_IN___2 = 880,\n\tPORT239_FN_IN___2 = 881,\n\tPORT240_FN_IN___2 = 882,\n\tPORT241_FN_IN___2 = 883,\n\tPORT242_FN_IN___2 = 884,\n\tPORT243_FN_IN___2 = 885,\n\tPORT244_FN_IN___2 = 886,\n\tPORT245_FN_IN___2 = 887,\n\tPORT246_FN_IN___2 = 888,\n\tPORT247_FN_IN___2 = 889,\n\tPORT248_FN_IN___2 = 890,\n\tPORT249_FN_IN___2 = 891,\n\tPORT250_FN_IN___2 = 892,\n\tPORT256_FN_IN___2 = 893,\n\tPORT257_FN_IN___2 = 894,\n\tPORT258_FN_IN___2 = 895,\n\tPORT259_FN_IN___2 = 896,\n\tPORT260_FN_IN___2 = 897,\n\tPORT261_FN_IN___2 = 898,\n\tPORT262_FN_IN___2 = 899,\n\tPORT263_FN_IN___2 = 900,\n\tPORT264_FN_IN___2 = 901,\n\tPORT265_FN_IN___2 = 902,\n\tPORT266_FN_IN___2 = 903,\n\tPORT267_FN_IN___2 = 904,\n\tPORT268_FN_IN___2 = 905,\n\tPORT269_FN_IN___2 = 906,\n\tPORT270_FN_IN___2 = 907,\n\tPORT271_FN_IN___2 = 908,\n\tPORT272_FN_IN___2 = 909,\n\tPORT273_FN_IN___2 = 910,\n\tPORT274_FN_IN___2 = 911,\n\tPORT275_FN_IN___2 = 912,\n\tPORT276_FN_IN___2 = 913,\n\tPORT277_FN_IN___2 = 914,\n\tPORT278_FN_IN___2 = 915,\n\tPORT279_FN_IN___2 = 916,\n\tPORT280_FN_IN___2 = 917,\n\tPORT281_FN_IN___2 = 918,\n\tPORT282_FN_IN___2 = 919,\n\tPORT283_FN_IN = 920,\n\tPORT288_FN_IN___2 = 921,\n\tPORT289_FN_IN___2 = 922,\n\tPORT290_FN_IN___2 = 923,\n\tPORT291_FN_IN___2 = 924,\n\tPORT292_FN_IN___2 = 925,\n\tPORT293_FN_IN___2 = 926,\n\tPORT294_FN_IN___2 = 927,\n\tPORT295_FN_IN___2 = 928,\n\tPORT296_FN_IN___2 = 929,\n\tPORT297_FN_IN___2 = 930,\n\tPORT298_FN_IN___2 = 931,\n\tPORT299_FN_IN___2 = 932,\n\tPORT300_FN_IN___2 = 933,\n\tPORT301_FN_IN___2 = 934,\n\tPORT302_FN_IN___2 = 935,\n\tPORT303_FN_IN___2 = 936,\n\tPORT304_FN_IN___2 = 937,\n\tPORT305_FN_IN___2 = 938,\n\tPORT306_FN_IN___2 = 939,\n\tPORT307_FN_IN___2 = 940,\n\tPORT308_FN_IN___2 = 941,\n\tPORT320_FN_IN = 942,\n\tPORT321_FN_IN = 943,\n\tPORT322_FN_IN = 944,\n\tPORT323_FN_IN = 945,\n\tPORT324_FN_IN = 946,\n\tPORT325_FN_IN = 947,\n\tPORT326_FN_IN = 948,\n\tPORT327_FN_IN = 949,\n\tPORT328_FN_IN = 950,\n\tPORT329_FN_IN = 951,\n\tPORT0_FN_OUT___2 = 952,\n\tPORT1_FN_OUT___2 = 953,\n\tPORT2_FN_OUT___2 = 954,\n\tPORT3_FN_OUT___2 = 955,\n\tPORT4_FN_OUT___2 = 956,\n\tPORT5_FN_OUT___2 = 957,\n\tPORT6_FN_OUT___2 = 958,\n\tPORT7_FN_OUT___2 = 959,\n\tPORT8_FN_OUT___2 = 960,\n\tPORT9_FN_OUT___2 = 961,\n\tPORT10_FN_OUT___2 = 962,\n\tPORT11_FN_OUT___2 = 963,\n\tPORT12_FN_OUT___2 = 964,\n\tPORT13_FN_OUT___2 = 965,\n\tPORT14_FN_OUT___2 = 966,\n\tPORT15_FN_OUT___2 = 967,\n\tPORT16_FN_OUT___2 = 968,\n\tPORT17_FN_OUT___2 = 969,\n\tPORT18_FN_OUT___2 = 970,\n\tPORT19_FN_OUT___2 = 971,\n\tPORT20_FN_OUT___2 = 972,\n\tPORT21_FN_OUT___2 = 973,\n\tPORT22_FN_OUT___2 = 974,\n\tPORT23_FN_OUT___2 = 975,\n\tPORT24_FN_OUT___2 = 976,\n\tPORT25_FN_OUT___2 = 977,\n\tPORT26_FN_OUT___2 = 978,\n\tPORT27_FN_OUT___2 = 979,\n\tPORT28_FN_OUT___2 = 980,\n\tPORT29_FN_OUT___2 = 981,\n\tPORT30_FN_OUT___2 = 982,\n\tPORT32_FN_OUT___2 = 983,\n\tPORT33_FN_OUT___2 = 984,\n\tPORT34_FN_OUT___2 = 985,\n\tPORT35_FN_OUT___2 = 986,\n\tPORT36_FN_OUT___2 = 987,\n\tPORT37_FN_OUT___2 = 988,\n\tPORT38_FN_OUT___2 = 989,\n\tPORT39_FN_OUT___2 = 990,\n\tPORT40_FN_OUT___2 = 991,\n\tPORT64_FN_OUT___2 = 992,\n\tPORT65_FN_OUT___2 = 993,\n\tPORT66_FN_OUT___2 = 994,\n\tPORT67_FN_OUT___2 = 995,\n\tPORT68_FN_OUT___2 = 996,\n\tPORT69_FN_OUT___2 = 997,\n\tPORT70_FN_OUT___2 = 998,\n\tPORT71_FN_OUT___2 = 999,\n\tPORT72_FN_OUT___2 = 1000,\n\tPORT73_FN_OUT___2 = 1001,\n\tPORT74_FN_OUT___2 = 1002,\n\tPORT75_FN_OUT___2 = 1003,\n\tPORT76_FN_OUT___2 = 1004,\n\tPORT77_FN_OUT___2 = 1005,\n\tPORT78_FN_OUT___2 = 1006,\n\tPORT79_FN_OUT___2 = 1007,\n\tPORT80_FN_OUT___2 = 1008,\n\tPORT81_FN_OUT___2 = 1009,\n\tPORT82_FN_OUT___2 = 1010,\n\tPORT83_FN_OUT___2 = 1011,\n\tPORT84_FN_OUT___2 = 1012,\n\tPORT85_FN_OUT___2 = 1013,\n\tPORT96_FN_OUT___2 = 1014,\n\tPORT97_FN_OUT___2 = 1015,\n\tPORT98_FN_OUT___2 = 1016,\n\tPORT99_FN_OUT___2 = 1017,\n\tPORT100_FN_OUT___2 = 1018,\n\tPORT101_FN_OUT___2 = 1019,\n\tPORT102_FN_OUT___2 = 1020,\n\tPORT103_FN_OUT___2 = 1021,\n\tPORT104_FN_OUT___2 = 1022,\n\tPORT105_FN_OUT___2 = 1023,\n\tPORT106_FN_OUT___2 = 1024,\n\tPORT107_FN_OUT___2 = 1025,\n\tPORT108_FN_OUT___2 = 1026,\n\tPORT109_FN_OUT___2 = 1027,\n\tPORT110_FN_OUT___2 = 1028,\n\tPORT111_FN_OUT___2 = 1029,\n\tPORT112_FN_OUT___2 = 1030,\n\tPORT113_FN_OUT___2 = 1031,\n\tPORT114_FN_OUT___2 = 1032,\n\tPORT115_FN_OUT___2 = 1033,\n\tPORT116_FN_OUT___2 = 1034,\n\tPORT117_FN_OUT___2 = 1035,\n\tPORT118_FN_OUT___2 = 1036,\n\tPORT119_FN_OUT = 1037,\n\tPORT120_FN_OUT = 1038,\n\tPORT121_FN_OUT = 1039,\n\tPORT122_FN_OUT = 1040,\n\tPORT123_FN_OUT = 1041,\n\tPORT124_FN_OUT = 1042,\n\tPORT125_FN_OUT = 1043,\n\tPORT126_FN_OUT = 1044,\n\tPORT128_FN_OUT___2 = 1045,\n\tPORT129_FN_OUT___2 = 1046,\n\tPORT130_FN_OUT___2 = 1047,\n\tPORT131_FN_OUT___2 = 1048,\n\tPORT132_FN_OUT___2 = 1049,\n\tPORT133_FN_OUT___2 = 1050,\n\tPORT134_FN_OUT___2 = 1051,\n\tPORT160_FN_OUT___2 = 1052,\n\tPORT161_FN_OUT___2 = 1053,\n\tPORT162_FN_OUT___2 = 1054,\n\tPORT163_FN_OUT___2 = 1055,\n\tPORT164_FN_OUT___2 = 1056,\n\tPORT165_FN_OUT = 1057,\n\tPORT166_FN_OUT = 1058,\n\tPORT167_FN_OUT = 1059,\n\tPORT168_FN_OUT = 1060,\n\tPORT169_FN_OUT = 1061,\n\tPORT170_FN_OUT = 1062,\n\tPORT171_FN_OUT = 1063,\n\tPORT172_FN_OUT = 1064,\n\tPORT173_FN_OUT = 1065,\n\tPORT174_FN_OUT = 1066,\n\tPORT175_FN_OUT = 1067,\n\tPORT176_FN_OUT = 1068,\n\tPORT177_FN_OUT = 1069,\n\tPORT178_FN_OUT = 1070,\n\tPORT192_FN_OUT___2 = 1071,\n\tPORT193_FN_OUT___2 = 1072,\n\tPORT194_FN_OUT___2 = 1073,\n\tPORT195_FN_OUT___2 = 1074,\n\tPORT196_FN_OUT___2 = 1075,\n\tPORT197_FN_OUT___2 = 1076,\n\tPORT198_FN_OUT___2 = 1077,\n\tPORT199_FN_OUT___2 = 1078,\n\tPORT200_FN_OUT___2 = 1079,\n\tPORT201_FN_OUT___2 = 1080,\n\tPORT202_FN_OUT___2 = 1081,\n\tPORT203_FN_OUT___2 = 1082,\n\tPORT204_FN_OUT___2 = 1083,\n\tPORT205_FN_OUT___2 = 1084,\n\tPORT206_FN_OUT___2 = 1085,\n\tPORT207_FN_OUT___2 = 1086,\n\tPORT208_FN_OUT___2 = 1087,\n\tPORT209_FN_OUT___2 = 1088,\n\tPORT210_FN_OUT___2 = 1089,\n\tPORT211_FN_OUT___2 = 1090,\n\tPORT212_FN_OUT___2 = 1091,\n\tPORT213_FN_OUT___2 = 1092,\n\tPORT214_FN_OUT___2 = 1093,\n\tPORT215_FN_OUT___2 = 1094,\n\tPORT216_FN_OUT___2 = 1095,\n\tPORT217_FN_OUT___2 = 1096,\n\tPORT218_FN_OUT___2 = 1097,\n\tPORT219_FN_OUT___2 = 1098,\n\tPORT220_FN_OUT___2 = 1099,\n\tPORT221_FN_OUT___2 = 1100,\n\tPORT222_FN_OUT___2 = 1101,\n\tPORT224_FN_OUT___2 = 1102,\n\tPORT225_FN_OUT___2 = 1103,\n\tPORT226_FN_OUT___2 = 1104,\n\tPORT227_FN_OUT___2 = 1105,\n\tPORT228_FN_OUT___2 = 1106,\n\tPORT229_FN_OUT___2 = 1107,\n\tPORT230_FN_OUT___2 = 1108,\n\tPORT231_FN_OUT___2 = 1109,\n\tPORT232_FN_OUT___2 = 1110,\n\tPORT233_FN_OUT___2 = 1111,\n\tPORT234_FN_OUT___2 = 1112,\n\tPORT235_FN_OUT___2 = 1113,\n\tPORT236_FN_OUT___2 = 1114,\n\tPORT237_FN_OUT___2 = 1115,\n\tPORT238_FN_OUT___2 = 1116,\n\tPORT239_FN_OUT___2 = 1117,\n\tPORT240_FN_OUT___2 = 1118,\n\tPORT241_FN_OUT___2 = 1119,\n\tPORT242_FN_OUT___2 = 1120,\n\tPORT243_FN_OUT___2 = 1121,\n\tPORT244_FN_OUT___2 = 1122,\n\tPORT245_FN_OUT___2 = 1123,\n\tPORT246_FN_OUT___2 = 1124,\n\tPORT247_FN_OUT___2 = 1125,\n\tPORT248_FN_OUT___2 = 1126,\n\tPORT249_FN_OUT___2 = 1127,\n\tPORT250_FN_OUT___2 = 1128,\n\tPORT256_FN_OUT___2 = 1129,\n\tPORT257_FN_OUT___2 = 1130,\n\tPORT258_FN_OUT___2 = 1131,\n\tPORT259_FN_OUT___2 = 1132,\n\tPORT260_FN_OUT___2 = 1133,\n\tPORT261_FN_OUT___2 = 1134,\n\tPORT262_FN_OUT___2 = 1135,\n\tPORT263_FN_OUT___2 = 1136,\n\tPORT264_FN_OUT___2 = 1137,\n\tPORT265_FN_OUT___2 = 1138,\n\tPORT266_FN_OUT___2 = 1139,\n\tPORT267_FN_OUT___2 = 1140,\n\tPORT268_FN_OUT___2 = 1141,\n\tPORT269_FN_OUT___2 = 1142,\n\tPORT270_FN_OUT___2 = 1143,\n\tPORT271_FN_OUT___2 = 1144,\n\tPORT272_FN_OUT___2 = 1145,\n\tPORT273_FN_OUT___2 = 1146,\n\tPORT274_FN_OUT___2 = 1147,\n\tPORT275_FN_OUT___2 = 1148,\n\tPORT276_FN_OUT___2 = 1149,\n\tPORT277_FN_OUT___2 = 1150,\n\tPORT278_FN_OUT___2 = 1151,\n\tPORT279_FN_OUT___2 = 1152,\n\tPORT280_FN_OUT___2 = 1153,\n\tPORT281_FN_OUT___2 = 1154,\n\tPORT282_FN_OUT___2 = 1155,\n\tPORT283_FN_OUT = 1156,\n\tPORT288_FN_OUT___2 = 1157,\n\tPORT289_FN_OUT___2 = 1158,\n\tPORT290_FN_OUT___2 = 1159,\n\tPORT291_FN_OUT___2 = 1160,\n\tPORT292_FN_OUT___2 = 1161,\n\tPORT293_FN_OUT___2 = 1162,\n\tPORT294_FN_OUT___2 = 1163,\n\tPORT295_FN_OUT___2 = 1164,\n\tPORT296_FN_OUT___2 = 1165,\n\tPORT297_FN_OUT___2 = 1166,\n\tPORT298_FN_OUT___2 = 1167,\n\tPORT299_FN_OUT___2 = 1168,\n\tPORT300_FN_OUT___2 = 1169,\n\tPORT301_FN_OUT___2 = 1170,\n\tPORT302_FN_OUT___2 = 1171,\n\tPORT303_FN_OUT___2 = 1172,\n\tPORT304_FN_OUT___2 = 1173,\n\tPORT305_FN_OUT___2 = 1174,\n\tPORT306_FN_OUT___2 = 1175,\n\tPORT307_FN_OUT___2 = 1176,\n\tPORT308_FN_OUT___2 = 1177,\n\tPORT320_FN_OUT = 1178,\n\tPORT321_FN_OUT = 1179,\n\tPORT322_FN_OUT = 1180,\n\tPORT323_FN_OUT = 1181,\n\tPORT324_FN_OUT = 1182,\n\tPORT325_FN_OUT = 1183,\n\tPORT326_FN_OUT = 1184,\n\tPORT327_FN_OUT = 1185,\n\tPORT328_FN_OUT = 1186,\n\tPORT329_FN_OUT = 1187,\n\tPORT0_FN0___2 = 1188,\n\tPORT1_FN0___2 = 1189,\n\tPORT2_FN0___2 = 1190,\n\tPORT3_FN0___2 = 1191,\n\tPORT4_FN0___2 = 1192,\n\tPORT5_FN0___2 = 1193,\n\tPORT6_FN0___2 = 1194,\n\tPORT7_FN0___2 = 1195,\n\tPORT8_FN0___2 = 1196,\n\tPORT9_FN0___2 = 1197,\n\tPORT10_FN0___2 = 1198,\n\tPORT11_FN0___2 = 1199,\n\tPORT12_FN0___2 = 1200,\n\tPORT13_FN0___2 = 1201,\n\tPORT14_FN0___2 = 1202,\n\tPORT15_FN0___2 = 1203,\n\tPORT16_FN0___2 = 1204,\n\tPORT17_FN0___2 = 1205,\n\tPORT18_FN0___2 = 1206,\n\tPORT19_FN0___2 = 1207,\n\tPORT20_FN0___2 = 1208,\n\tPORT21_FN0___2 = 1209,\n\tPORT22_FN0___2 = 1210,\n\tPORT23_FN0___2 = 1211,\n\tPORT24_FN0___2 = 1212,\n\tPORT25_FN0___2 = 1213,\n\tPORT26_FN0___2 = 1214,\n\tPORT27_FN0___2 = 1215,\n\tPORT28_FN0___2 = 1216,\n\tPORT29_FN0___2 = 1217,\n\tPORT30_FN0___2 = 1218,\n\tPORT32_FN0___2 = 1219,\n\tPORT33_FN0___2 = 1220,\n\tPORT34_FN0___2 = 1221,\n\tPORT35_FN0___2 = 1222,\n\tPORT36_FN0___2 = 1223,\n\tPORT37_FN0___2 = 1224,\n\tPORT38_FN0___2 = 1225,\n\tPORT39_FN0___2 = 1226,\n\tPORT40_FN0___2 = 1227,\n\tPORT64_FN0___2 = 1228,\n\tPORT65_FN0___2 = 1229,\n\tPORT66_FN0___2 = 1230,\n\tPORT67_FN0___2 = 1231,\n\tPORT68_FN0___2 = 1232,\n\tPORT69_FN0___2 = 1233,\n\tPORT70_FN0___2 = 1234,\n\tPORT71_FN0___2 = 1235,\n\tPORT72_FN0___2 = 1236,\n\tPORT73_FN0___2 = 1237,\n\tPORT74_FN0___2 = 1238,\n\tPORT75_FN0___2 = 1239,\n\tPORT76_FN0___2 = 1240,\n\tPORT77_FN0___2 = 1241,\n\tPORT78_FN0___2 = 1242,\n\tPORT79_FN0___2 = 1243,\n\tPORT80_FN0___2 = 1244,\n\tPORT81_FN0___2 = 1245,\n\tPORT82_FN0___2 = 1246,\n\tPORT83_FN0___2 = 1247,\n\tPORT84_FN0___2 = 1248,\n\tPORT85_FN0___2 = 1249,\n\tPORT96_FN0___2 = 1250,\n\tPORT97_FN0___2 = 1251,\n\tPORT98_FN0___2 = 1252,\n\tPORT99_FN0___2 = 1253,\n\tPORT100_FN0___2 = 1254,\n\tPORT101_FN0___2 = 1255,\n\tPORT102_FN0___2 = 1256,\n\tPORT103_FN0___2 = 1257,\n\tPORT104_FN0___2 = 1258,\n\tPORT105_FN0___2 = 1259,\n\tPORT106_FN0___2 = 1260,\n\tPORT107_FN0___2 = 1261,\n\tPORT108_FN0___2 = 1262,\n\tPORT109_FN0___2 = 1263,\n\tPORT110_FN0___2 = 1264,\n\tPORT111_FN0___2 = 1265,\n\tPORT112_FN0___2 = 1266,\n\tPORT113_FN0___2 = 1267,\n\tPORT114_FN0___2 = 1268,\n\tPORT115_FN0___2 = 1269,\n\tPORT116_FN0___2 = 1270,\n\tPORT117_FN0___2 = 1271,\n\tPORT118_FN0___2 = 1272,\n\tPORT119_FN0 = 1273,\n\tPORT120_FN0 = 1274,\n\tPORT121_FN0 = 1275,\n\tPORT122_FN0 = 1276,\n\tPORT123_FN0 = 1277,\n\tPORT124_FN0 = 1278,\n\tPORT125_FN0 = 1279,\n\tPORT126_FN0 = 1280,\n\tPORT128_FN0___2 = 1281,\n\tPORT129_FN0___2 = 1282,\n\tPORT130_FN0___2 = 1283,\n\tPORT131_FN0___2 = 1284,\n\tPORT132_FN0___2 = 1285,\n\tPORT133_FN0___2 = 1286,\n\tPORT134_FN0___2 = 1287,\n\tPORT160_FN0___2 = 1288,\n\tPORT161_FN0___2 = 1289,\n\tPORT162_FN0___2 = 1290,\n\tPORT163_FN0___2 = 1291,\n\tPORT164_FN0___2 = 1292,\n\tPORT165_FN0 = 1293,\n\tPORT166_FN0 = 1294,\n\tPORT167_FN0 = 1295,\n\tPORT168_FN0 = 1296,\n\tPORT169_FN0 = 1297,\n\tPORT170_FN0 = 1298,\n\tPORT171_FN0 = 1299,\n\tPORT172_FN0 = 1300,\n\tPORT173_FN0 = 1301,\n\tPORT174_FN0 = 1302,\n\tPORT175_FN0 = 1303,\n\tPORT176_FN0 = 1304,\n\tPORT177_FN0 = 1305,\n\tPORT178_FN0 = 1306,\n\tPORT192_FN0___2 = 1307,\n\tPORT193_FN0___2 = 1308,\n\tPORT194_FN0___2 = 1309,\n\tPORT195_FN0___2 = 1310,\n\tPORT196_FN0___2 = 1311,\n\tPORT197_FN0___2 = 1312,\n\tPORT198_FN0___2 = 1313,\n\tPORT199_FN0___2 = 1314,\n\tPORT200_FN0___2 = 1315,\n\tPORT201_FN0___2 = 1316,\n\tPORT202_FN0___2 = 1317,\n\tPORT203_FN0___2 = 1318,\n\tPORT204_FN0___2 = 1319,\n\tPORT205_FN0___2 = 1320,\n\tPORT206_FN0___2 = 1321,\n\tPORT207_FN0___2 = 1322,\n\tPORT208_FN0___2 = 1323,\n\tPORT209_FN0___2 = 1324,\n\tPORT210_FN0___2 = 1325,\n\tPORT211_FN0___2 = 1326,\n\tPORT212_FN0___2 = 1327,\n\tPORT213_FN0___2 = 1328,\n\tPORT214_FN0___2 = 1329,\n\tPORT215_FN0___2 = 1330,\n\tPORT216_FN0___2 = 1331,\n\tPORT217_FN0___2 = 1332,\n\tPORT218_FN0___2 = 1333,\n\tPORT219_FN0___2 = 1334,\n\tPORT220_FN0___2 = 1335,\n\tPORT221_FN0___2 = 1336,\n\tPORT222_FN0___2 = 1337,\n\tPORT224_FN0___2 = 1338,\n\tPORT225_FN0___2 = 1339,\n\tPORT226_FN0___2 = 1340,\n\tPORT227_FN0___2 = 1341,\n\tPORT228_FN0___2 = 1342,\n\tPORT229_FN0___2 = 1343,\n\tPORT230_FN0___2 = 1344,\n\tPORT231_FN0___2 = 1345,\n\tPORT232_FN0___2 = 1346,\n\tPORT233_FN0___2 = 1347,\n\tPORT234_FN0___2 = 1348,\n\tPORT235_FN0___2 = 1349,\n\tPORT236_FN0___2 = 1350,\n\tPORT237_FN0___2 = 1351,\n\tPORT238_FN0___2 = 1352,\n\tPORT239_FN0___2 = 1353,\n\tPORT240_FN0___2 = 1354,\n\tPORT241_FN0___2 = 1355,\n\tPORT242_FN0___2 = 1356,\n\tPORT243_FN0___2 = 1357,\n\tPORT244_FN0___2 = 1358,\n\tPORT245_FN0___2 = 1359,\n\tPORT246_FN0___2 = 1360,\n\tPORT247_FN0___2 = 1361,\n\tPORT248_FN0___2 = 1362,\n\tPORT249_FN0___2 = 1363,\n\tPORT250_FN0___2 = 1364,\n\tPORT256_FN0___2 = 1365,\n\tPORT257_FN0___2 = 1366,\n\tPORT258_FN0___2 = 1367,\n\tPORT259_FN0___2 = 1368,\n\tPORT260_FN0___2 = 1369,\n\tPORT261_FN0___2 = 1370,\n\tPORT262_FN0___2 = 1371,\n\tPORT263_FN0___2 = 1372,\n\tPORT264_FN0___2 = 1373,\n\tPORT265_FN0___2 = 1374,\n\tPORT266_FN0___2 = 1375,\n\tPORT267_FN0___2 = 1376,\n\tPORT268_FN0___2 = 1377,\n\tPORT269_FN0___2 = 1378,\n\tPORT270_FN0___2 = 1379,\n\tPORT271_FN0___2 = 1380,\n\tPORT272_FN0___2 = 1381,\n\tPORT273_FN0___2 = 1382,\n\tPORT274_FN0___2 = 1383,\n\tPORT275_FN0___2 = 1384,\n\tPORT276_FN0___2 = 1385,\n\tPORT277_FN0___2 = 1386,\n\tPORT278_FN0___2 = 1387,\n\tPORT279_FN0___2 = 1388,\n\tPORT280_FN0___2 = 1389,\n\tPORT281_FN0___2 = 1390,\n\tPORT282_FN0___2 = 1391,\n\tPORT283_FN0 = 1392,\n\tPORT288_FN0___2 = 1393,\n\tPORT289_FN0___2 = 1394,\n\tPORT290_FN0___2 = 1395,\n\tPORT291_FN0___2 = 1396,\n\tPORT292_FN0___2 = 1397,\n\tPORT293_FN0___2 = 1398,\n\tPORT294_FN0___2 = 1399,\n\tPORT295_FN0___2 = 1400,\n\tPORT296_FN0___2 = 1401,\n\tPORT297_FN0___2 = 1402,\n\tPORT298_FN0___2 = 1403,\n\tPORT299_FN0___2 = 1404,\n\tPORT300_FN0___2 = 1405,\n\tPORT301_FN0___2 = 1406,\n\tPORT302_FN0___2 = 1407,\n\tPORT303_FN0___2 = 1408,\n\tPORT304_FN0___2 = 1409,\n\tPORT305_FN0___2 = 1410,\n\tPORT306_FN0___2 = 1411,\n\tPORT307_FN0___2 = 1412,\n\tPORT308_FN0___2 = 1413,\n\tPORT320_FN0 = 1414,\n\tPORT321_FN0 = 1415,\n\tPORT322_FN0 = 1416,\n\tPORT323_FN0 = 1417,\n\tPORT324_FN0 = 1418,\n\tPORT325_FN0 = 1419,\n\tPORT326_FN0 = 1420,\n\tPORT327_FN0 = 1421,\n\tPORT328_FN0 = 1422,\n\tPORT329_FN0 = 1423,\n\tPORT0_FN1___2 = 1424,\n\tPORT1_FN1___2 = 1425,\n\tPORT2_FN1___2 = 1426,\n\tPORT3_FN1___2 = 1427,\n\tPORT4_FN1___2 = 1428,\n\tPORT5_FN1___2 = 1429,\n\tPORT6_FN1___2 = 1430,\n\tPORT7_FN1___2 = 1431,\n\tPORT8_FN1___2 = 1432,\n\tPORT9_FN1___2 = 1433,\n\tPORT10_FN1___2 = 1434,\n\tPORT11_FN1___2 = 1435,\n\tPORT12_FN1___2 = 1436,\n\tPORT13_FN1___2 = 1437,\n\tPORT14_FN1___2 = 1438,\n\tPORT15_FN1___2 = 1439,\n\tPORT16_FN1___2 = 1440,\n\tPORT17_FN1___2 = 1441,\n\tPORT18_FN1___2 = 1442,\n\tPORT19_FN1___2 = 1443,\n\tPORT20_FN1___2 = 1444,\n\tPORT21_FN1___2 = 1445,\n\tPORT22_FN1___2 = 1446,\n\tPORT23_FN1___2 = 1447,\n\tPORT24_FN1___2 = 1448,\n\tPORT25_FN1___2 = 1449,\n\tPORT26_FN1___2 = 1450,\n\tPORT27_FN1___2 = 1451,\n\tPORT28_FN1___2 = 1452,\n\tPORT29_FN1___2 = 1453,\n\tPORT30_FN1___2 = 1454,\n\tPORT32_FN1___2 = 1455,\n\tPORT33_FN1___2 = 1456,\n\tPORT34_FN1___2 = 1457,\n\tPORT35_FN1___2 = 1458,\n\tPORT36_FN1___2 = 1459,\n\tPORT37_FN1___2 = 1460,\n\tPORT38_FN1___2 = 1461,\n\tPORT39_FN1___2 = 1462,\n\tPORT40_FN1___2 = 1463,\n\tPORT64_FN1___2 = 1464,\n\tPORT65_FN1___2 = 1465,\n\tPORT66_FN1___2 = 1466,\n\tPORT67_FN1___2 = 1467,\n\tPORT68_FN1___2 = 1468,\n\tPORT69_FN1___2 = 1469,\n\tPORT70_FN1___2 = 1470,\n\tPORT71_FN1___2 = 1471,\n\tPORT72_FN1___2 = 1472,\n\tPORT73_FN1___2 = 1473,\n\tPORT74_FN1___2 = 1474,\n\tPORT75_FN1___2 = 1475,\n\tPORT76_FN1___2 = 1476,\n\tPORT77_FN1___2 = 1477,\n\tPORT78_FN1___2 = 1478,\n\tPORT79_FN1___2 = 1479,\n\tPORT80_FN1___2 = 1480,\n\tPORT81_FN1___2 = 1481,\n\tPORT82_FN1___2 = 1482,\n\tPORT83_FN1___2 = 1483,\n\tPORT84_FN1___2 = 1484,\n\tPORT85_FN1___2 = 1485,\n\tPORT96_FN1___2 = 1486,\n\tPORT97_FN1___2 = 1487,\n\tPORT98_FN1___2 = 1488,\n\tPORT99_FN1___2 = 1489,\n\tPORT100_FN1___2 = 1490,\n\tPORT101_FN1___2 = 1491,\n\tPORT102_FN1___2 = 1492,\n\tPORT103_FN1___2 = 1493,\n\tPORT104_FN1___2 = 1494,\n\tPORT105_FN1___2 = 1495,\n\tPORT106_FN1___2 = 1496,\n\tPORT107_FN1___2 = 1497,\n\tPORT108_FN1___2 = 1498,\n\tPORT109_FN1___2 = 1499,\n\tPORT110_FN1___2 = 1500,\n\tPORT111_FN1___2 = 1501,\n\tPORT112_FN1___2 = 1502,\n\tPORT113_FN1___2 = 1503,\n\tPORT114_FN1___2 = 1504,\n\tPORT115_FN1___2 = 1505,\n\tPORT116_FN1___2 = 1506,\n\tPORT117_FN1___2 = 1507,\n\tPORT118_FN1___2 = 1508,\n\tPORT119_FN1 = 1509,\n\tPORT120_FN1 = 1510,\n\tPORT121_FN1 = 1511,\n\tPORT122_FN1 = 1512,\n\tPORT123_FN1 = 1513,\n\tPORT124_FN1 = 1514,\n\tPORT125_FN1 = 1515,\n\tPORT126_FN1 = 1516,\n\tPORT128_FN1___2 = 1517,\n\tPORT129_FN1___2 = 1518,\n\tPORT130_FN1___2 = 1519,\n\tPORT131_FN1___2 = 1520,\n\tPORT132_FN1___2 = 1521,\n\tPORT133_FN1___2 = 1522,\n\tPORT134_FN1___2 = 1523,\n\tPORT160_FN1___2 = 1524,\n\tPORT161_FN1___2 = 1525,\n\tPORT162_FN1___2 = 1526,\n\tPORT163_FN1___2 = 1527,\n\tPORT164_FN1___2 = 1528,\n\tPORT165_FN1 = 1529,\n\tPORT166_FN1 = 1530,\n\tPORT167_FN1 = 1531,\n\tPORT168_FN1 = 1532,\n\tPORT169_FN1 = 1533,\n\tPORT170_FN1 = 1534,\n\tPORT171_FN1 = 1535,\n\tPORT172_FN1 = 1536,\n\tPORT173_FN1 = 1537,\n\tPORT174_FN1 = 1538,\n\tPORT175_FN1 = 1539,\n\tPORT176_FN1 = 1540,\n\tPORT177_FN1 = 1541,\n\tPORT178_FN1 = 1542,\n\tPORT192_FN1___2 = 1543,\n\tPORT193_FN1___2 = 1544,\n\tPORT194_FN1___2 = 1545,\n\tPORT195_FN1___2 = 1546,\n\tPORT196_FN1___2 = 1547,\n\tPORT197_FN1___2 = 1548,\n\tPORT198_FN1___2 = 1549,\n\tPORT199_FN1___2 = 1550,\n\tPORT200_FN1___2 = 1551,\n\tPORT201_FN1___2 = 1552,\n\tPORT202_FN1___2 = 1553,\n\tPORT203_FN1___2 = 1554,\n\tPORT204_FN1___2 = 1555,\n\tPORT205_FN1___2 = 1556,\n\tPORT206_FN1___2 = 1557,\n\tPORT207_FN1___2 = 1558,\n\tPORT208_FN1___2 = 1559,\n\tPORT209_FN1___2 = 1560,\n\tPORT210_FN1___2 = 1561,\n\tPORT211_FN1___2 = 1562,\n\tPORT212_FN1___2 = 1563,\n\tPORT213_FN1___2 = 1564,\n\tPORT214_FN1___2 = 1565,\n\tPORT215_FN1___2 = 1566,\n\tPORT216_FN1___2 = 1567,\n\tPORT217_FN1___2 = 1568,\n\tPORT218_FN1___2 = 1569,\n\tPORT219_FN1___2 = 1570,\n\tPORT220_FN1___2 = 1571,\n\tPORT221_FN1___2 = 1572,\n\tPORT222_FN1___2 = 1573,\n\tPORT224_FN1___2 = 1574,\n\tPORT225_FN1___2 = 1575,\n\tPORT226_FN1___2 = 1576,\n\tPORT227_FN1___2 = 1577,\n\tPORT228_FN1___2 = 1578,\n\tPORT229_FN1___2 = 1579,\n\tPORT230_FN1___2 = 1580,\n\tPORT231_FN1___2 = 1581,\n\tPORT232_FN1___2 = 1582,\n\tPORT233_FN1___2 = 1583,\n\tPORT234_FN1___2 = 1584,\n\tPORT235_FN1___2 = 1585,\n\tPORT236_FN1___2 = 1586,\n\tPORT237_FN1___2 = 1587,\n\tPORT238_FN1___2 = 1588,\n\tPORT239_FN1___2 = 1589,\n\tPORT240_FN1___2 = 1590,\n\tPORT241_FN1___2 = 1591,\n\tPORT242_FN1___2 = 1592,\n\tPORT243_FN1___2 = 1593,\n\tPORT244_FN1___2 = 1594,\n\tPORT245_FN1___2 = 1595,\n\tPORT246_FN1___2 = 1596,\n\tPORT247_FN1___2 = 1597,\n\tPORT248_FN1___2 = 1598,\n\tPORT249_FN1___2 = 1599,\n\tPORT250_FN1___2 = 1600,\n\tPORT256_FN1___2 = 1601,\n\tPORT257_FN1___2 = 1602,\n\tPORT258_FN1___2 = 1603,\n\tPORT259_FN1___2 = 1604,\n\tPORT260_FN1___2 = 1605,\n\tPORT261_FN1___2 = 1606,\n\tPORT262_FN1___2 = 1607,\n\tPORT263_FN1___2 = 1608,\n\tPORT264_FN1___2 = 1609,\n\tPORT265_FN1___2 = 1610,\n\tPORT266_FN1___2 = 1611,\n\tPORT267_FN1___2 = 1612,\n\tPORT268_FN1___2 = 1613,\n\tPORT269_FN1___2 = 1614,\n\tPORT270_FN1___2 = 1615,\n\tPORT271_FN1___2 = 1616,\n\tPORT272_FN1___2 = 1617,\n\tPORT273_FN1___2 = 1618,\n\tPORT274_FN1___2 = 1619,\n\tPORT275_FN1___2 = 1620,\n\tPORT276_FN1___2 = 1621,\n\tPORT277_FN1___2 = 1622,\n\tPORT278_FN1___2 = 1623,\n\tPORT279_FN1___2 = 1624,\n\tPORT280_FN1___2 = 1625,\n\tPORT281_FN1___2 = 1626,\n\tPORT282_FN1___2 = 1627,\n\tPORT283_FN1 = 1628,\n\tPORT288_FN1___2 = 1629,\n\tPORT289_FN1___2 = 1630,\n\tPORT290_FN1___2 = 1631,\n\tPORT291_FN1___2 = 1632,\n\tPORT292_FN1___2 = 1633,\n\tPORT293_FN1___2 = 1634,\n\tPORT294_FN1___2 = 1635,\n\tPORT295_FN1___2 = 1636,\n\tPORT296_FN1___2 = 1637,\n\tPORT297_FN1___2 = 1638,\n\tPORT298_FN1___2 = 1639,\n\tPORT299_FN1___2 = 1640,\n\tPORT300_FN1___2 = 1641,\n\tPORT301_FN1___2 = 1642,\n\tPORT302_FN1___2 = 1643,\n\tPORT303_FN1___2 = 1644,\n\tPORT304_FN1___2 = 1645,\n\tPORT305_FN1___2 = 1646,\n\tPORT306_FN1___2 = 1647,\n\tPORT307_FN1___2 = 1648,\n\tPORT308_FN1___2 = 1649,\n\tPORT320_FN1 = 1650,\n\tPORT321_FN1 = 1651,\n\tPORT322_FN1 = 1652,\n\tPORT323_FN1 = 1653,\n\tPORT324_FN1 = 1654,\n\tPORT325_FN1 = 1655,\n\tPORT326_FN1 = 1656,\n\tPORT327_FN1 = 1657,\n\tPORT328_FN1 = 1658,\n\tPORT329_FN1 = 1659,\n\tPORT0_FN2___2 = 1660,\n\tPORT1_FN2___2 = 1661,\n\tPORT2_FN2___2 = 1662,\n\tPORT3_FN2___2 = 1663,\n\tPORT4_FN2___2 = 1664,\n\tPORT5_FN2___2 = 1665,\n\tPORT6_FN2___2 = 1666,\n\tPORT7_FN2___2 = 1667,\n\tPORT8_FN2___2 = 1668,\n\tPORT9_FN2___2 = 1669,\n\tPORT10_FN2___2 = 1670,\n\tPORT11_FN2___2 = 1671,\n\tPORT12_FN2___2 = 1672,\n\tPORT13_FN2___2 = 1673,\n\tPORT14_FN2___2 = 1674,\n\tPORT15_FN2___2 = 1675,\n\tPORT16_FN2___2 = 1676,\n\tPORT17_FN2___2 = 1677,\n\tPORT18_FN2___2 = 1678,\n\tPORT19_FN2___2 = 1679,\n\tPORT20_FN2___2 = 1680,\n\tPORT21_FN2___2 = 1681,\n\tPORT22_FN2___2 = 1682,\n\tPORT23_FN2___2 = 1683,\n\tPORT24_FN2___2 = 1684,\n\tPORT25_FN2___2 = 1685,\n\tPORT26_FN2___2 = 1686,\n\tPORT27_FN2___2 = 1687,\n\tPORT28_FN2___2 = 1688,\n\tPORT29_FN2___2 = 1689,\n\tPORT30_FN2___2 = 1690,\n\tPORT32_FN2___2 = 1691,\n\tPORT33_FN2___2 = 1692,\n\tPORT34_FN2___2 = 1693,\n\tPORT35_FN2___2 = 1694,\n\tPORT36_FN2___2 = 1695,\n\tPORT37_FN2___2 = 1696,\n\tPORT38_FN2___2 = 1697,\n\tPORT39_FN2___2 = 1698,\n\tPORT40_FN2___2 = 1699,\n\tPORT64_FN2___2 = 1700,\n\tPORT65_FN2___2 = 1701,\n\tPORT66_FN2___2 = 1702,\n\tPORT67_FN2___2 = 1703,\n\tPORT68_FN2___2 = 1704,\n\tPORT69_FN2___2 = 1705,\n\tPORT70_FN2___2 = 1706,\n\tPORT71_FN2___2 = 1707,\n\tPORT72_FN2___2 = 1708,\n\tPORT73_FN2___2 = 1709,\n\tPORT74_FN2___2 = 1710,\n\tPORT75_FN2___2 = 1711,\n\tPORT76_FN2___2 = 1712,\n\tPORT77_FN2___2 = 1713,\n\tPORT78_FN2___2 = 1714,\n\tPORT79_FN2___2 = 1715,\n\tPORT80_FN2___2 = 1716,\n\tPORT81_FN2___2 = 1717,\n\tPORT82_FN2___2 = 1718,\n\tPORT83_FN2___2 = 1719,\n\tPORT84_FN2___2 = 1720,\n\tPORT85_FN2___2 = 1721,\n\tPORT96_FN2___2 = 1722,\n\tPORT97_FN2___2 = 1723,\n\tPORT98_FN2___2 = 1724,\n\tPORT99_FN2___2 = 1725,\n\tPORT100_FN2___2 = 1726,\n\tPORT101_FN2___2 = 1727,\n\tPORT102_FN2___2 = 1728,\n\tPORT103_FN2___2 = 1729,\n\tPORT104_FN2___2 = 1730,\n\tPORT105_FN2___2 = 1731,\n\tPORT106_FN2___2 = 1732,\n\tPORT107_FN2___2 = 1733,\n\tPORT108_FN2___2 = 1734,\n\tPORT109_FN2___2 = 1735,\n\tPORT110_FN2___2 = 1736,\n\tPORT111_FN2___2 = 1737,\n\tPORT112_FN2___2 = 1738,\n\tPORT113_FN2___2 = 1739,\n\tPORT114_FN2___2 = 1740,\n\tPORT115_FN2___2 = 1741,\n\tPORT116_FN2___2 = 1742,\n\tPORT117_FN2___2 = 1743,\n\tPORT118_FN2___2 = 1744,\n\tPORT119_FN2 = 1745,\n\tPORT120_FN2 = 1746,\n\tPORT121_FN2 = 1747,\n\tPORT122_FN2 = 1748,\n\tPORT123_FN2 = 1749,\n\tPORT124_FN2 = 1750,\n\tPORT125_FN2 = 1751,\n\tPORT126_FN2 = 1752,\n\tPORT128_FN2___2 = 1753,\n\tPORT129_FN2___2 = 1754,\n\tPORT130_FN2___2 = 1755,\n\tPORT131_FN2___2 = 1756,\n\tPORT132_FN2___2 = 1757,\n\tPORT133_FN2___2 = 1758,\n\tPORT134_FN2___2 = 1759,\n\tPORT160_FN2___2 = 1760,\n\tPORT161_FN2___2 = 1761,\n\tPORT162_FN2___2 = 1762,\n\tPORT163_FN2___2 = 1763,\n\tPORT164_FN2___2 = 1764,\n\tPORT165_FN2 = 1765,\n\tPORT166_FN2 = 1766,\n\tPORT167_FN2 = 1767,\n\tPORT168_FN2 = 1768,\n\tPORT169_FN2 = 1769,\n\tPORT170_FN2 = 1770,\n\tPORT171_FN2 = 1771,\n\tPORT172_FN2 = 1772,\n\tPORT173_FN2 = 1773,\n\tPORT174_FN2 = 1774,\n\tPORT175_FN2 = 1775,\n\tPORT176_FN2 = 1776,\n\tPORT177_FN2 = 1777,\n\tPORT178_FN2 = 1778,\n\tPORT192_FN2___2 = 1779,\n\tPORT193_FN2___2 = 1780,\n\tPORT194_FN2___2 = 1781,\n\tPORT195_FN2___2 = 1782,\n\tPORT196_FN2___2 = 1783,\n\tPORT197_FN2___2 = 1784,\n\tPORT198_FN2___2 = 1785,\n\tPORT199_FN2___2 = 1786,\n\tPORT200_FN2___2 = 1787,\n\tPORT201_FN2___2 = 1788,\n\tPORT202_FN2___2 = 1789,\n\tPORT203_FN2___2 = 1790,\n\tPORT204_FN2___2 = 1791,\n\tPORT205_FN2___2 = 1792,\n\tPORT206_FN2___2 = 1793,\n\tPORT207_FN2___2 = 1794,\n\tPORT208_FN2___2 = 1795,\n\tPORT209_FN2___2 = 1796,\n\tPORT210_FN2___2 = 1797,\n\tPORT211_FN2___2 = 1798,\n\tPORT212_FN2___2 = 1799,\n\tPORT213_FN2___2 = 1800,\n\tPORT214_FN2___2 = 1801,\n\tPORT215_FN2___2 = 1802,\n\tPORT216_FN2___2 = 1803,\n\tPORT217_FN2___2 = 1804,\n\tPORT218_FN2___2 = 1805,\n\tPORT219_FN2___2 = 1806,\n\tPORT220_FN2___2 = 1807,\n\tPORT221_FN2___2 = 1808,\n\tPORT222_FN2___2 = 1809,\n\tPORT224_FN2___2 = 1810,\n\tPORT225_FN2___2 = 1811,\n\tPORT226_FN2___2 = 1812,\n\tPORT227_FN2___2 = 1813,\n\tPORT228_FN2___2 = 1814,\n\tPORT229_FN2___2 = 1815,\n\tPORT230_FN2___2 = 1816,\n\tPORT231_FN2___2 = 1817,\n\tPORT232_FN2___2 = 1818,\n\tPORT233_FN2___2 = 1819,\n\tPORT234_FN2___2 = 1820,\n\tPORT235_FN2___2 = 1821,\n\tPORT236_FN2___2 = 1822,\n\tPORT237_FN2___2 = 1823,\n\tPORT238_FN2___2 = 1824,\n\tPORT239_FN2___2 = 1825,\n\tPORT240_FN2___2 = 1826,\n\tPORT241_FN2___2 = 1827,\n\tPORT242_FN2___2 = 1828,\n\tPORT243_FN2___2 = 1829,\n\tPORT244_FN2___2 = 1830,\n\tPORT245_FN2___2 = 1831,\n\tPORT246_FN2___2 = 1832,\n\tPORT247_FN2___2 = 1833,\n\tPORT248_FN2___2 = 1834,\n\tPORT249_FN2___2 = 1835,\n\tPORT250_FN2___2 = 1836,\n\tPORT256_FN2___2 = 1837,\n\tPORT257_FN2___2 = 1838,\n\tPORT258_FN2___2 = 1839,\n\tPORT259_FN2___2 = 1840,\n\tPORT260_FN2___2 = 1841,\n\tPORT261_FN2___2 = 1842,\n\tPORT262_FN2___2 = 1843,\n\tPORT263_FN2___2 = 1844,\n\tPORT264_FN2___2 = 1845,\n\tPORT265_FN2___2 = 1846,\n\tPORT266_FN2___2 = 1847,\n\tPORT267_FN2___2 = 1848,\n\tPORT268_FN2___2 = 1849,\n\tPORT269_FN2___2 = 1850,\n\tPORT270_FN2___2 = 1851,\n\tPORT271_FN2___2 = 1852,\n\tPORT272_FN2___2 = 1853,\n\tPORT273_FN2___2 = 1854,\n\tPORT274_FN2___2 = 1855,\n\tPORT275_FN2___2 = 1856,\n\tPORT276_FN2___2 = 1857,\n\tPORT277_FN2___2 = 1858,\n\tPORT278_FN2___2 = 1859,\n\tPORT279_FN2___2 = 1860,\n\tPORT280_FN2___2 = 1861,\n\tPORT281_FN2___2 = 1862,\n\tPORT282_FN2___2 = 1863,\n\tPORT283_FN2 = 1864,\n\tPORT288_FN2___2 = 1865,\n\tPORT289_FN2___2 = 1866,\n\tPORT290_FN2___2 = 1867,\n\tPORT291_FN2___2 = 1868,\n\tPORT292_FN2___2 = 1869,\n\tPORT293_FN2___2 = 1870,\n\tPORT294_FN2___2 = 1871,\n\tPORT295_FN2___2 = 1872,\n\tPORT296_FN2___2 = 1873,\n\tPORT297_FN2___2 = 1874,\n\tPORT298_FN2___2 = 1875,\n\tPORT299_FN2___2 = 1876,\n\tPORT300_FN2___2 = 1877,\n\tPORT301_FN2___2 = 1878,\n\tPORT302_FN2___2 = 1879,\n\tPORT303_FN2___2 = 1880,\n\tPORT304_FN2___2 = 1881,\n\tPORT305_FN2___2 = 1882,\n\tPORT306_FN2___2 = 1883,\n\tPORT307_FN2___2 = 1884,\n\tPORT308_FN2___2 = 1885,\n\tPORT320_FN2 = 1886,\n\tPORT321_FN2 = 1887,\n\tPORT322_FN2 = 1888,\n\tPORT323_FN2 = 1889,\n\tPORT324_FN2 = 1890,\n\tPORT325_FN2 = 1891,\n\tPORT326_FN2 = 1892,\n\tPORT327_FN2 = 1893,\n\tPORT328_FN2 = 1894,\n\tPORT329_FN2 = 1895,\n\tPORT0_FN3___2 = 1896,\n\tPORT1_FN3___2 = 1897,\n\tPORT2_FN3___2 = 1898,\n\tPORT3_FN3___2 = 1899,\n\tPORT4_FN3___2 = 1900,\n\tPORT5_FN3___2 = 1901,\n\tPORT6_FN3___2 = 1902,\n\tPORT7_FN3___2 = 1903,\n\tPORT8_FN3___2 = 1904,\n\tPORT9_FN3___2 = 1905,\n\tPORT10_FN3___2 = 1906,\n\tPORT11_FN3___2 = 1907,\n\tPORT12_FN3___2 = 1908,\n\tPORT13_FN3___2 = 1909,\n\tPORT14_FN3___2 = 1910,\n\tPORT15_FN3___2 = 1911,\n\tPORT16_FN3___2 = 1912,\n\tPORT17_FN3___2 = 1913,\n\tPORT18_FN3___2 = 1914,\n\tPORT19_FN3___2 = 1915,\n\tPORT20_FN3___2 = 1916,\n\tPORT21_FN3___2 = 1917,\n\tPORT22_FN3___2 = 1918,\n\tPORT23_FN3___2 = 1919,\n\tPORT24_FN3___2 = 1920,\n\tPORT25_FN3___2 = 1921,\n\tPORT26_FN3___2 = 1922,\n\tPORT27_FN3___2 = 1923,\n\tPORT28_FN3___2 = 1924,\n\tPORT29_FN3___2 = 1925,\n\tPORT30_FN3___2 = 1926,\n\tPORT32_FN3___2 = 1927,\n\tPORT33_FN3___2 = 1928,\n\tPORT34_FN3___2 = 1929,\n\tPORT35_FN3___2 = 1930,\n\tPORT36_FN3___2 = 1931,\n\tPORT37_FN3___2 = 1932,\n\tPORT38_FN3___2 = 1933,\n\tPORT39_FN3___2 = 1934,\n\tPORT40_FN3___2 = 1935,\n\tPORT64_FN3___2 = 1936,\n\tPORT65_FN3___2 = 1937,\n\tPORT66_FN3___2 = 1938,\n\tPORT67_FN3___2 = 1939,\n\tPORT68_FN3___2 = 1940,\n\tPORT69_FN3___2 = 1941,\n\tPORT70_FN3___2 = 1942,\n\tPORT71_FN3___2 = 1943,\n\tPORT72_FN3___2 = 1944,\n\tPORT73_FN3___2 = 1945,\n\tPORT74_FN3___2 = 1946,\n\tPORT75_FN3___2 = 1947,\n\tPORT76_FN3___2 = 1948,\n\tPORT77_FN3___2 = 1949,\n\tPORT78_FN3___2 = 1950,\n\tPORT79_FN3___2 = 1951,\n\tPORT80_FN3___2 = 1952,\n\tPORT81_FN3___2 = 1953,\n\tPORT82_FN3___2 = 1954,\n\tPORT83_FN3___2 = 1955,\n\tPORT84_FN3___2 = 1956,\n\tPORT85_FN3___2 = 1957,\n\tPORT96_FN3___2 = 1958,\n\tPORT97_FN3___2 = 1959,\n\tPORT98_FN3___2 = 1960,\n\tPORT99_FN3___2 = 1961,\n\tPORT100_FN3___2 = 1962,\n\tPORT101_FN3___2 = 1963,\n\tPORT102_FN3___2 = 1964,\n\tPORT103_FN3___2 = 1965,\n\tPORT104_FN3___2 = 1966,\n\tPORT105_FN3___2 = 1967,\n\tPORT106_FN3___2 = 1968,\n\tPORT107_FN3___2 = 1969,\n\tPORT108_FN3___2 = 1970,\n\tPORT109_FN3___2 = 1971,\n\tPORT110_FN3___2 = 1972,\n\tPORT111_FN3___2 = 1973,\n\tPORT112_FN3___2 = 1974,\n\tPORT113_FN3___2 = 1975,\n\tPORT114_FN3___2 = 1976,\n\tPORT115_FN3___2 = 1977,\n\tPORT116_FN3___2 = 1978,\n\tPORT117_FN3___2 = 1979,\n\tPORT118_FN3___2 = 1980,\n\tPORT119_FN3 = 1981,\n\tPORT120_FN3 = 1982,\n\tPORT121_FN3 = 1983,\n\tPORT122_FN3 = 1984,\n\tPORT123_FN3 = 1985,\n\tPORT124_FN3 = 1986,\n\tPORT125_FN3 = 1987,\n\tPORT126_FN3 = 1988,\n\tPORT128_FN3___2 = 1989,\n\tPORT129_FN3___2 = 1990,\n\tPORT130_FN3___2 = 1991,\n\tPORT131_FN3___2 = 1992,\n\tPORT132_FN3___2 = 1993,\n\tPORT133_FN3___2 = 1994,\n\tPORT134_FN3___2 = 1995,\n\tPORT160_FN3___2 = 1996,\n\tPORT161_FN3___2 = 1997,\n\tPORT162_FN3___2 = 1998,\n\tPORT163_FN3___2 = 1999,\n\tPORT164_FN3___2 = 2000,\n\tPORT165_FN3 = 2001,\n\tPORT166_FN3 = 2002,\n\tPORT167_FN3 = 2003,\n\tPORT168_FN3 = 2004,\n\tPORT169_FN3 = 2005,\n\tPORT170_FN3 = 2006,\n\tPORT171_FN3 = 2007,\n\tPORT172_FN3 = 2008,\n\tPORT173_FN3 = 2009,\n\tPORT174_FN3 = 2010,\n\tPORT175_FN3 = 2011,\n\tPORT176_FN3 = 2012,\n\tPORT177_FN3 = 2013,\n\tPORT178_FN3 = 2014,\n\tPORT192_FN3___2 = 2015,\n\tPORT193_FN3___2 = 2016,\n\tPORT194_FN3___2 = 2017,\n\tPORT195_FN3___2 = 2018,\n\tPORT196_FN3___2 = 2019,\n\tPORT197_FN3___2 = 2020,\n\tPORT198_FN3___2 = 2021,\n\tPORT199_FN3___2 = 2022,\n\tPORT200_FN3___2 = 2023,\n\tPORT201_FN3___2 = 2024,\n\tPORT202_FN3___2 = 2025,\n\tPORT203_FN3___2 = 2026,\n\tPORT204_FN3___2 = 2027,\n\tPORT205_FN3___2 = 2028,\n\tPORT206_FN3___2 = 2029,\n\tPORT207_FN3___2 = 2030,\n\tPORT208_FN3___2 = 2031,\n\tPORT209_FN3___2 = 2032,\n\tPORT210_FN3___2 = 2033,\n\tPORT211_FN3___2 = 2034,\n\tPORT212_FN3___2 = 2035,\n\tPORT213_FN3___2 = 2036,\n\tPORT214_FN3___2 = 2037,\n\tPORT215_FN3___2 = 2038,\n\tPORT216_FN3___2 = 2039,\n\tPORT217_FN3___2 = 2040,\n\tPORT218_FN3___2 = 2041,\n\tPORT219_FN3___2 = 2042,\n\tPORT220_FN3___2 = 2043,\n\tPORT221_FN3___2 = 2044,\n\tPORT222_FN3___2 = 2045,\n\tPORT224_FN3___2 = 2046,\n\tPORT225_FN3___2 = 2047,\n\tPORT226_FN3___2 = 2048,\n\tPORT227_FN3___2 = 2049,\n\tPORT228_FN3___2 = 2050,\n\tPORT229_FN3___2 = 2051,\n\tPORT230_FN3___2 = 2052,\n\tPORT231_FN3___2 = 2053,\n\tPORT232_FN3___2 = 2054,\n\tPORT233_FN3___2 = 2055,\n\tPORT234_FN3___2 = 2056,\n\tPORT235_FN3___2 = 2057,\n\tPORT236_FN3___2 = 2058,\n\tPORT237_FN3___2 = 2059,\n\tPORT238_FN3___2 = 2060,\n\tPORT239_FN3___2 = 2061,\n\tPORT240_FN3___2 = 2062,\n\tPORT241_FN3___2 = 2063,\n\tPORT242_FN3___2 = 2064,\n\tPORT243_FN3___2 = 2065,\n\tPORT244_FN3___2 = 2066,\n\tPORT245_FN3___2 = 2067,\n\tPORT246_FN3___2 = 2068,\n\tPORT247_FN3___2 = 2069,\n\tPORT248_FN3___2 = 2070,\n\tPORT249_FN3___2 = 2071,\n\tPORT250_FN3___2 = 2072,\n\tPORT256_FN3___2 = 2073,\n\tPORT257_FN3___2 = 2074,\n\tPORT258_FN3___2 = 2075,\n\tPORT259_FN3___2 = 2076,\n\tPORT260_FN3___2 = 2077,\n\tPORT261_FN3___2 = 2078,\n\tPORT262_FN3___2 = 2079,\n\tPORT263_FN3___2 = 2080,\n\tPORT264_FN3___2 = 2081,\n\tPORT265_FN3___2 = 2082,\n\tPORT266_FN3___2 = 2083,\n\tPORT267_FN3___2 = 2084,\n\tPORT268_FN3___2 = 2085,\n\tPORT269_FN3___2 = 2086,\n\tPORT270_FN3___2 = 2087,\n\tPORT271_FN3___2 = 2088,\n\tPORT272_FN3___2 = 2089,\n\tPORT273_FN3___2 = 2090,\n\tPORT274_FN3___2 = 2091,\n\tPORT275_FN3___2 = 2092,\n\tPORT276_FN3___2 = 2093,\n\tPORT277_FN3___2 = 2094,\n\tPORT278_FN3___2 = 2095,\n\tPORT279_FN3___2 = 2096,\n\tPORT280_FN3___2 = 2097,\n\tPORT281_FN3___2 = 2098,\n\tPORT282_FN3___2 = 2099,\n\tPORT283_FN3 = 2100,\n\tPORT288_FN3___2 = 2101,\n\tPORT289_FN3___2 = 2102,\n\tPORT290_FN3___2 = 2103,\n\tPORT291_FN3___2 = 2104,\n\tPORT292_FN3___2 = 2105,\n\tPORT293_FN3___2 = 2106,\n\tPORT294_FN3___2 = 2107,\n\tPORT295_FN3___2 = 2108,\n\tPORT296_FN3___2 = 2109,\n\tPORT297_FN3___2 = 2110,\n\tPORT298_FN3___2 = 2111,\n\tPORT299_FN3___2 = 2112,\n\tPORT300_FN3___2 = 2113,\n\tPORT301_FN3___2 = 2114,\n\tPORT302_FN3___2 = 2115,\n\tPORT303_FN3___2 = 2116,\n\tPORT304_FN3___2 = 2117,\n\tPORT305_FN3___2 = 2118,\n\tPORT306_FN3___2 = 2119,\n\tPORT307_FN3___2 = 2120,\n\tPORT308_FN3___2 = 2121,\n\tPORT320_FN3 = 2122,\n\tPORT321_FN3 = 2123,\n\tPORT322_FN3 = 2124,\n\tPORT323_FN3 = 2125,\n\tPORT324_FN3 = 2126,\n\tPORT325_FN3 = 2127,\n\tPORT326_FN3 = 2128,\n\tPORT327_FN3 = 2129,\n\tPORT328_FN3 = 2130,\n\tPORT329_FN3 = 2131,\n\tPORT0_FN4___2 = 2132,\n\tPORT1_FN4___2 = 2133,\n\tPORT2_FN4___2 = 2134,\n\tPORT3_FN4___2 = 2135,\n\tPORT4_FN4___2 = 2136,\n\tPORT5_FN4___2 = 2137,\n\tPORT6_FN4___2 = 2138,\n\tPORT7_FN4___2 = 2139,\n\tPORT8_FN4___2 = 2140,\n\tPORT9_FN4___2 = 2141,\n\tPORT10_FN4___2 = 2142,\n\tPORT11_FN4___2 = 2143,\n\tPORT12_FN4___2 = 2144,\n\tPORT13_FN4___2 = 2145,\n\tPORT14_FN4___2 = 2146,\n\tPORT15_FN4___2 = 2147,\n\tPORT16_FN4___2 = 2148,\n\tPORT17_FN4___2 = 2149,\n\tPORT18_FN4___2 = 2150,\n\tPORT19_FN4___2 = 2151,\n\tPORT20_FN4___2 = 2152,\n\tPORT21_FN4___2 = 2153,\n\tPORT22_FN4___2 = 2154,\n\tPORT23_FN4___2 = 2155,\n\tPORT24_FN4___2 = 2156,\n\tPORT25_FN4___2 = 2157,\n\tPORT26_FN4___2 = 2158,\n\tPORT27_FN4___2 = 2159,\n\tPORT28_FN4___2 = 2160,\n\tPORT29_FN4___2 = 2161,\n\tPORT30_FN4___2 = 2162,\n\tPORT32_FN4___2 = 2163,\n\tPORT33_FN4___2 = 2164,\n\tPORT34_FN4___2 = 2165,\n\tPORT35_FN4___2 = 2166,\n\tPORT36_FN4___2 = 2167,\n\tPORT37_FN4___2 = 2168,\n\tPORT38_FN4___2 = 2169,\n\tPORT39_FN4___2 = 2170,\n\tPORT40_FN4___2 = 2171,\n\tPORT64_FN4___2 = 2172,\n\tPORT65_FN4___2 = 2173,\n\tPORT66_FN4___2 = 2174,\n\tPORT67_FN4___2 = 2175,\n\tPORT68_FN4___2 = 2176,\n\tPORT69_FN4___2 = 2177,\n\tPORT70_FN4___2 = 2178,\n\tPORT71_FN4___2 = 2179,\n\tPORT72_FN4___2 = 2180,\n\tPORT73_FN4___2 = 2181,\n\tPORT74_FN4___2 = 2182,\n\tPORT75_FN4___2 = 2183,\n\tPORT76_FN4___2 = 2184,\n\tPORT77_FN4___2 = 2185,\n\tPORT78_FN4___2 = 2186,\n\tPORT79_FN4___2 = 2187,\n\tPORT80_FN4___2 = 2188,\n\tPORT81_FN4___2 = 2189,\n\tPORT82_FN4___2 = 2190,\n\tPORT83_FN4___2 = 2191,\n\tPORT84_FN4___2 = 2192,\n\tPORT85_FN4___2 = 2193,\n\tPORT96_FN4___2 = 2194,\n\tPORT97_FN4___2 = 2195,\n\tPORT98_FN4___2 = 2196,\n\tPORT99_FN4___2 = 2197,\n\tPORT100_FN4___2 = 2198,\n\tPORT101_FN4___2 = 2199,\n\tPORT102_FN4___2 = 2200,\n\tPORT103_FN4___2 = 2201,\n\tPORT104_FN4___2 = 2202,\n\tPORT105_FN4___2 = 2203,\n\tPORT106_FN4___2 = 2204,\n\tPORT107_FN4___2 = 2205,\n\tPORT108_FN4___2 = 2206,\n\tPORT109_FN4___2 = 2207,\n\tPORT110_FN4___2 = 2208,\n\tPORT111_FN4___2 = 2209,\n\tPORT112_FN4___2 = 2210,\n\tPORT113_FN4___2 = 2211,\n\tPORT114_FN4___2 = 2212,\n\tPORT115_FN4___2 = 2213,\n\tPORT116_FN4___2 = 2214,\n\tPORT117_FN4___2 = 2215,\n\tPORT118_FN4___2 = 2216,\n\tPORT119_FN4 = 2217,\n\tPORT120_FN4 = 2218,\n\tPORT121_FN4 = 2219,\n\tPORT122_FN4 = 2220,\n\tPORT123_FN4 = 2221,\n\tPORT124_FN4 = 2222,\n\tPORT125_FN4 = 2223,\n\tPORT126_FN4 = 2224,\n\tPORT128_FN4___2 = 2225,\n\tPORT129_FN4___2 = 2226,\n\tPORT130_FN4___2 = 2227,\n\tPORT131_FN4___2 = 2228,\n\tPORT132_FN4___2 = 2229,\n\tPORT133_FN4___2 = 2230,\n\tPORT134_FN4___2 = 2231,\n\tPORT160_FN4___2 = 2232,\n\tPORT161_FN4___2 = 2233,\n\tPORT162_FN4___2 = 2234,\n\tPORT163_FN4___2 = 2235,\n\tPORT164_FN4___2 = 2236,\n\tPORT165_FN4 = 2237,\n\tPORT166_FN4 = 2238,\n\tPORT167_FN4 = 2239,\n\tPORT168_FN4 = 2240,\n\tPORT169_FN4 = 2241,\n\tPORT170_FN4 = 2242,\n\tPORT171_FN4 = 2243,\n\tPORT172_FN4 = 2244,\n\tPORT173_FN4 = 2245,\n\tPORT174_FN4 = 2246,\n\tPORT175_FN4 = 2247,\n\tPORT176_FN4 = 2248,\n\tPORT177_FN4 = 2249,\n\tPORT178_FN4 = 2250,\n\tPORT192_FN4___2 = 2251,\n\tPORT193_FN4___2 = 2252,\n\tPORT194_FN4___2 = 2253,\n\tPORT195_FN4___2 = 2254,\n\tPORT196_FN4___2 = 2255,\n\tPORT197_FN4___2 = 2256,\n\tPORT198_FN4___2 = 2257,\n\tPORT199_FN4___2 = 2258,\n\tPORT200_FN4___2 = 2259,\n\tPORT201_FN4___2 = 2260,\n\tPORT202_FN4___2 = 2261,\n\tPORT203_FN4___2 = 2262,\n\tPORT204_FN4___2 = 2263,\n\tPORT205_FN4___2 = 2264,\n\tPORT206_FN4___2 = 2265,\n\tPORT207_FN4___2 = 2266,\n\tPORT208_FN4___2 = 2267,\n\tPORT209_FN4___2 = 2268,\n\tPORT210_FN4___2 = 2269,\n\tPORT211_FN4___2 = 2270,\n\tPORT212_FN4___2 = 2271,\n\tPORT213_FN4___2 = 2272,\n\tPORT214_FN4___2 = 2273,\n\tPORT215_FN4___2 = 2274,\n\tPORT216_FN4___2 = 2275,\n\tPORT217_FN4___2 = 2276,\n\tPORT218_FN4___2 = 2277,\n\tPORT219_FN4___2 = 2278,\n\tPORT220_FN4___2 = 2279,\n\tPORT221_FN4___2 = 2280,\n\tPORT222_FN4___2 = 2281,\n\tPORT224_FN4___2 = 2282,\n\tPORT225_FN4___2 = 2283,\n\tPORT226_FN4___2 = 2284,\n\tPORT227_FN4___2 = 2285,\n\tPORT228_FN4___2 = 2286,\n\tPORT229_FN4___2 = 2287,\n\tPORT230_FN4___2 = 2288,\n\tPORT231_FN4___2 = 2289,\n\tPORT232_FN4___2 = 2290,\n\tPORT233_FN4___2 = 2291,\n\tPORT234_FN4___2 = 2292,\n\tPORT235_FN4___2 = 2293,\n\tPORT236_FN4___2 = 2294,\n\tPORT237_FN4___2 = 2295,\n\tPORT238_FN4___2 = 2296,\n\tPORT239_FN4___2 = 2297,\n\tPORT240_FN4___2 = 2298,\n\tPORT241_FN4___2 = 2299,\n\tPORT242_FN4___2 = 2300,\n\tPORT243_FN4___2 = 2301,\n\tPORT244_FN4___2 = 2302,\n\tPORT245_FN4___2 = 2303,\n\tPORT246_FN4___2 = 2304,\n\tPORT247_FN4___2 = 2305,\n\tPORT248_FN4___2 = 2306,\n\tPORT249_FN4___2 = 2307,\n\tPORT250_FN4___2 = 2308,\n\tPORT256_FN4___2 = 2309,\n\tPORT257_FN4___2 = 2310,\n\tPORT258_FN4___2 = 2311,\n\tPORT259_FN4___2 = 2312,\n\tPORT260_FN4___2 = 2313,\n\tPORT261_FN4___2 = 2314,\n\tPORT262_FN4___2 = 2315,\n\tPORT263_FN4___2 = 2316,\n\tPORT264_FN4___2 = 2317,\n\tPORT265_FN4___2 = 2318,\n\tPORT266_FN4___2 = 2319,\n\tPORT267_FN4___2 = 2320,\n\tPORT268_FN4___2 = 2321,\n\tPORT269_FN4___2 = 2322,\n\tPORT270_FN4___2 = 2323,\n\tPORT271_FN4___2 = 2324,\n\tPORT272_FN4___2 = 2325,\n\tPORT273_FN4___2 = 2326,\n\tPORT274_FN4___2 = 2327,\n\tPORT275_FN4___2 = 2328,\n\tPORT276_FN4___2 = 2329,\n\tPORT277_FN4___2 = 2330,\n\tPORT278_FN4___2 = 2331,\n\tPORT279_FN4___2 = 2332,\n\tPORT280_FN4___2 = 2333,\n\tPORT281_FN4___2 = 2334,\n\tPORT282_FN4___2 = 2335,\n\tPORT283_FN4 = 2336,\n\tPORT288_FN4___2 = 2337,\n\tPORT289_FN4___2 = 2338,\n\tPORT290_FN4___2 = 2339,\n\tPORT291_FN4___2 = 2340,\n\tPORT292_FN4___2 = 2341,\n\tPORT293_FN4___2 = 2342,\n\tPORT294_FN4___2 = 2343,\n\tPORT295_FN4___2 = 2344,\n\tPORT296_FN4___2 = 2345,\n\tPORT297_FN4___2 = 2346,\n\tPORT298_FN4___2 = 2347,\n\tPORT299_FN4___2 = 2348,\n\tPORT300_FN4___2 = 2349,\n\tPORT301_FN4___2 = 2350,\n\tPORT302_FN4___2 = 2351,\n\tPORT303_FN4___2 = 2352,\n\tPORT304_FN4___2 = 2353,\n\tPORT305_FN4___2 = 2354,\n\tPORT306_FN4___2 = 2355,\n\tPORT307_FN4___2 = 2356,\n\tPORT308_FN4___2 = 2357,\n\tPORT320_FN4 = 2358,\n\tPORT321_FN4 = 2359,\n\tPORT322_FN4 = 2360,\n\tPORT323_FN4 = 2361,\n\tPORT324_FN4 = 2362,\n\tPORT325_FN4 = 2363,\n\tPORT326_FN4 = 2364,\n\tPORT327_FN4 = 2365,\n\tPORT328_FN4 = 2366,\n\tPORT329_FN4 = 2367,\n\tPORT0_FN5___2 = 2368,\n\tPORT1_FN5___2 = 2369,\n\tPORT2_FN5___2 = 2370,\n\tPORT3_FN5___2 = 2371,\n\tPORT4_FN5___2 = 2372,\n\tPORT5_FN5___2 = 2373,\n\tPORT6_FN5___2 = 2374,\n\tPORT7_FN5___2 = 2375,\n\tPORT8_FN5___2 = 2376,\n\tPORT9_FN5___2 = 2377,\n\tPORT10_FN5___2 = 2378,\n\tPORT11_FN5___2 = 2379,\n\tPORT12_FN5___2 = 2380,\n\tPORT13_FN5___2 = 2381,\n\tPORT14_FN5___2 = 2382,\n\tPORT15_FN5___2 = 2383,\n\tPORT16_FN5___2 = 2384,\n\tPORT17_FN5___2 = 2385,\n\tPORT18_FN5___2 = 2386,\n\tPORT19_FN5___2 = 2387,\n\tPORT20_FN5___2 = 2388,\n\tPORT21_FN5___2 = 2389,\n\tPORT22_FN5___2 = 2390,\n\tPORT23_FN5___2 = 2391,\n\tPORT24_FN5___2 = 2392,\n\tPORT25_FN5___2 = 2393,\n\tPORT26_FN5___2 = 2394,\n\tPORT27_FN5___2 = 2395,\n\tPORT28_FN5___2 = 2396,\n\tPORT29_FN5___2 = 2397,\n\tPORT30_FN5___2 = 2398,\n\tPORT32_FN5___2 = 2399,\n\tPORT33_FN5___2 = 2400,\n\tPORT34_FN5___2 = 2401,\n\tPORT35_FN5___2 = 2402,\n\tPORT36_FN5___2 = 2403,\n\tPORT37_FN5___2 = 2404,\n\tPORT38_FN5___2 = 2405,\n\tPORT39_FN5___2 = 2406,\n\tPORT40_FN5___2 = 2407,\n\tPORT64_FN5___2 = 2408,\n\tPORT65_FN5___2 = 2409,\n\tPORT66_FN5___2 = 2410,\n\tPORT67_FN5___2 = 2411,\n\tPORT68_FN5___2 = 2412,\n\tPORT69_FN5___2 = 2413,\n\tPORT70_FN5___2 = 2414,\n\tPORT71_FN5___2 = 2415,\n\tPORT72_FN5___2 = 2416,\n\tPORT73_FN5___2 = 2417,\n\tPORT74_FN5___2 = 2418,\n\tPORT75_FN5___2 = 2419,\n\tPORT76_FN5___2 = 2420,\n\tPORT77_FN5___2 = 2421,\n\tPORT78_FN5___2 = 2422,\n\tPORT79_FN5___2 = 2423,\n\tPORT80_FN5___2 = 2424,\n\tPORT81_FN5___2 = 2425,\n\tPORT82_FN5___2 = 2426,\n\tPORT83_FN5___2 = 2427,\n\tPORT84_FN5___2 = 2428,\n\tPORT85_FN5___2 = 2429,\n\tPORT96_FN5___2 = 2430,\n\tPORT97_FN5___2 = 2431,\n\tPORT98_FN5___2 = 2432,\n\tPORT99_FN5___2 = 2433,\n\tPORT100_FN5___2 = 2434,\n\tPORT101_FN5___2 = 2435,\n\tPORT102_FN5___2 = 2436,\n\tPORT103_FN5___2 = 2437,\n\tPORT104_FN5___2 = 2438,\n\tPORT105_FN5___2 = 2439,\n\tPORT106_FN5___2 = 2440,\n\tPORT107_FN5___2 = 2441,\n\tPORT108_FN5___2 = 2442,\n\tPORT109_FN5___2 = 2443,\n\tPORT110_FN5___2 = 2444,\n\tPORT111_FN5___2 = 2445,\n\tPORT112_FN5___2 = 2446,\n\tPORT113_FN5___2 = 2447,\n\tPORT114_FN5___2 = 2448,\n\tPORT115_FN5___2 = 2449,\n\tPORT116_FN5___2 = 2450,\n\tPORT117_FN5___2 = 2451,\n\tPORT118_FN5___2 = 2452,\n\tPORT119_FN5 = 2453,\n\tPORT120_FN5 = 2454,\n\tPORT121_FN5 = 2455,\n\tPORT122_FN5 = 2456,\n\tPORT123_FN5 = 2457,\n\tPORT124_FN5 = 2458,\n\tPORT125_FN5 = 2459,\n\tPORT126_FN5 = 2460,\n\tPORT128_FN5___2 = 2461,\n\tPORT129_FN5___2 = 2462,\n\tPORT130_FN5___2 = 2463,\n\tPORT131_FN5___2 = 2464,\n\tPORT132_FN5___2 = 2465,\n\tPORT133_FN5___2 = 2466,\n\tPORT134_FN5___2 = 2467,\n\tPORT160_FN5___2 = 2468,\n\tPORT161_FN5___2 = 2469,\n\tPORT162_FN5___2 = 2470,\n\tPORT163_FN5___2 = 2471,\n\tPORT164_FN5___2 = 2472,\n\tPORT165_FN5 = 2473,\n\tPORT166_FN5 = 2474,\n\tPORT167_FN5 = 2475,\n\tPORT168_FN5 = 2476,\n\tPORT169_FN5 = 2477,\n\tPORT170_FN5 = 2478,\n\tPORT171_FN5 = 2479,\n\tPORT172_FN5 = 2480,\n\tPORT173_FN5 = 2481,\n\tPORT174_FN5 = 2482,\n\tPORT175_FN5 = 2483,\n\tPORT176_FN5 = 2484,\n\tPORT177_FN5 = 2485,\n\tPORT178_FN5 = 2486,\n\tPORT192_FN5___2 = 2487,\n\tPORT193_FN5___2 = 2488,\n\tPORT194_FN5___2 = 2489,\n\tPORT195_FN5___2 = 2490,\n\tPORT196_FN5___2 = 2491,\n\tPORT197_FN5___2 = 2492,\n\tPORT198_FN5___2 = 2493,\n\tPORT199_FN5___2 = 2494,\n\tPORT200_FN5___2 = 2495,\n\tPORT201_FN5___2 = 2496,\n\tPORT202_FN5___2 = 2497,\n\tPORT203_FN5___2 = 2498,\n\tPORT204_FN5___2 = 2499,\n\tPORT205_FN5___2 = 2500,\n\tPORT206_FN5___2 = 2501,\n\tPORT207_FN5___2 = 2502,\n\tPORT208_FN5___2 = 2503,\n\tPORT209_FN5___2 = 2504,\n\tPORT210_FN5___2 = 2505,\n\tPORT211_FN5___2 = 2506,\n\tPORT212_FN5___2 = 2507,\n\tPORT213_FN5___2 = 2508,\n\tPORT214_FN5___2 = 2509,\n\tPORT215_FN5___2 = 2510,\n\tPORT216_FN5___2 = 2511,\n\tPORT217_FN5___2 = 2512,\n\tPORT218_FN5___2 = 2513,\n\tPORT219_FN5___2 = 2514,\n\tPORT220_FN5___2 = 2515,\n\tPORT221_FN5___2 = 2516,\n\tPORT222_FN5___2 = 2517,\n\tPORT224_FN5___2 = 2518,\n\tPORT225_FN5___2 = 2519,\n\tPORT226_FN5___2 = 2520,\n\tPORT227_FN5___2 = 2521,\n\tPORT228_FN5___2 = 2522,\n\tPORT229_FN5___2 = 2523,\n\tPORT230_FN5___2 = 2524,\n\tPORT231_FN5___2 = 2525,\n\tPORT232_FN5___2 = 2526,\n\tPORT233_FN5___2 = 2527,\n\tPORT234_FN5___2 = 2528,\n\tPORT235_FN5___2 = 2529,\n\tPORT236_FN5___2 = 2530,\n\tPORT237_FN5___2 = 2531,\n\tPORT238_FN5___2 = 2532,\n\tPORT239_FN5___2 = 2533,\n\tPORT240_FN5___2 = 2534,\n\tPORT241_FN5___2 = 2535,\n\tPORT242_FN5___2 = 2536,\n\tPORT243_FN5___2 = 2537,\n\tPORT244_FN5___2 = 2538,\n\tPORT245_FN5___2 = 2539,\n\tPORT246_FN5___2 = 2540,\n\tPORT247_FN5___2 = 2541,\n\tPORT248_FN5___2 = 2542,\n\tPORT249_FN5___2 = 2543,\n\tPORT250_FN5___2 = 2544,\n\tPORT256_FN5___2 = 2545,\n\tPORT257_FN5___2 = 2546,\n\tPORT258_FN5___2 = 2547,\n\tPORT259_FN5___2 = 2548,\n\tPORT260_FN5___2 = 2549,\n\tPORT261_FN5___2 = 2550,\n\tPORT262_FN5___2 = 2551,\n\tPORT263_FN5___2 = 2552,\n\tPORT264_FN5___2 = 2553,\n\tPORT265_FN5___2 = 2554,\n\tPORT266_FN5___2 = 2555,\n\tPORT267_FN5___2 = 2556,\n\tPORT268_FN5___2 = 2557,\n\tPORT269_FN5___2 = 2558,\n\tPORT270_FN5___2 = 2559,\n\tPORT271_FN5___2 = 2560,\n\tPORT272_FN5___2 = 2561,\n\tPORT273_FN5___2 = 2562,\n\tPORT274_FN5___2 = 2563,\n\tPORT275_FN5___2 = 2564,\n\tPORT276_FN5___2 = 2565,\n\tPORT277_FN5___2 = 2566,\n\tPORT278_FN5___2 = 2567,\n\tPORT279_FN5___2 = 2568,\n\tPORT280_FN5___2 = 2569,\n\tPORT281_FN5___2 = 2570,\n\tPORT282_FN5___2 = 2571,\n\tPORT283_FN5 = 2572,\n\tPORT288_FN5___2 = 2573,\n\tPORT289_FN5___2 = 2574,\n\tPORT290_FN5___2 = 2575,\n\tPORT291_FN5___2 = 2576,\n\tPORT292_FN5___2 = 2577,\n\tPORT293_FN5___2 = 2578,\n\tPORT294_FN5___2 = 2579,\n\tPORT295_FN5___2 = 2580,\n\tPORT296_FN5___2 = 2581,\n\tPORT297_FN5___2 = 2582,\n\tPORT298_FN5___2 = 2583,\n\tPORT299_FN5___2 = 2584,\n\tPORT300_FN5___2 = 2585,\n\tPORT301_FN5___2 = 2586,\n\tPORT302_FN5___2 = 2587,\n\tPORT303_FN5___2 = 2588,\n\tPORT304_FN5___2 = 2589,\n\tPORT305_FN5___2 = 2590,\n\tPORT306_FN5___2 = 2591,\n\tPORT307_FN5___2 = 2592,\n\tPORT308_FN5___2 = 2593,\n\tPORT320_FN5 = 2594,\n\tPORT321_FN5 = 2595,\n\tPORT322_FN5 = 2596,\n\tPORT323_FN5 = 2597,\n\tPORT324_FN5 = 2598,\n\tPORT325_FN5 = 2599,\n\tPORT326_FN5 = 2600,\n\tPORT327_FN5 = 2601,\n\tPORT328_FN5 = 2602,\n\tPORT329_FN5 = 2603,\n\tPORT0_FN6___2 = 2604,\n\tPORT1_FN6___2 = 2605,\n\tPORT2_FN6___2 = 2606,\n\tPORT3_FN6___2 = 2607,\n\tPORT4_FN6___2 = 2608,\n\tPORT5_FN6___2 = 2609,\n\tPORT6_FN6___2 = 2610,\n\tPORT7_FN6___2 = 2611,\n\tPORT8_FN6___2 = 2612,\n\tPORT9_FN6___2 = 2613,\n\tPORT10_FN6___2 = 2614,\n\tPORT11_FN6___2 = 2615,\n\tPORT12_FN6___2 = 2616,\n\tPORT13_FN6___2 = 2617,\n\tPORT14_FN6___2 = 2618,\n\tPORT15_FN6___2 = 2619,\n\tPORT16_FN6___2 = 2620,\n\tPORT17_FN6___2 = 2621,\n\tPORT18_FN6___2 = 2622,\n\tPORT19_FN6___2 = 2623,\n\tPORT20_FN6___2 = 2624,\n\tPORT21_FN6___2 = 2625,\n\tPORT22_FN6___2 = 2626,\n\tPORT23_FN6___2 = 2627,\n\tPORT24_FN6___2 = 2628,\n\tPORT25_FN6___2 = 2629,\n\tPORT26_FN6___2 = 2630,\n\tPORT27_FN6___2 = 2631,\n\tPORT28_FN6___2 = 2632,\n\tPORT29_FN6___2 = 2633,\n\tPORT30_FN6___2 = 2634,\n\tPORT32_FN6___2 = 2635,\n\tPORT33_FN6___2 = 2636,\n\tPORT34_FN6___2 = 2637,\n\tPORT35_FN6___2 = 2638,\n\tPORT36_FN6___2 = 2639,\n\tPORT37_FN6___2 = 2640,\n\tPORT38_FN6___2 = 2641,\n\tPORT39_FN6___2 = 2642,\n\tPORT40_FN6___2 = 2643,\n\tPORT64_FN6___2 = 2644,\n\tPORT65_FN6___2 = 2645,\n\tPORT66_FN6___2 = 2646,\n\tPORT67_FN6___2 = 2647,\n\tPORT68_FN6___2 = 2648,\n\tPORT69_FN6___2 = 2649,\n\tPORT70_FN6___2 = 2650,\n\tPORT71_FN6___2 = 2651,\n\tPORT72_FN6___2 = 2652,\n\tPORT73_FN6___2 = 2653,\n\tPORT74_FN6___2 = 2654,\n\tPORT75_FN6___2 = 2655,\n\tPORT76_FN6___2 = 2656,\n\tPORT77_FN6___2 = 2657,\n\tPORT78_FN6___2 = 2658,\n\tPORT79_FN6___2 = 2659,\n\tPORT80_FN6___2 = 2660,\n\tPORT81_FN6___2 = 2661,\n\tPORT82_FN6___2 = 2662,\n\tPORT83_FN6___2 = 2663,\n\tPORT84_FN6___2 = 2664,\n\tPORT85_FN6___2 = 2665,\n\tPORT96_FN6___2 = 2666,\n\tPORT97_FN6___2 = 2667,\n\tPORT98_FN6___2 = 2668,\n\tPORT99_FN6___2 = 2669,\n\tPORT100_FN6___2 = 2670,\n\tPORT101_FN6___2 = 2671,\n\tPORT102_FN6___2 = 2672,\n\tPORT103_FN6___2 = 2673,\n\tPORT104_FN6___2 = 2674,\n\tPORT105_FN6___2 = 2675,\n\tPORT106_FN6___2 = 2676,\n\tPORT107_FN6___2 = 2677,\n\tPORT108_FN6___2 = 2678,\n\tPORT109_FN6___2 = 2679,\n\tPORT110_FN6___2 = 2680,\n\tPORT111_FN6___2 = 2681,\n\tPORT112_FN6___2 = 2682,\n\tPORT113_FN6___2 = 2683,\n\tPORT114_FN6___2 = 2684,\n\tPORT115_FN6___2 = 2685,\n\tPORT116_FN6___2 = 2686,\n\tPORT117_FN6___2 = 2687,\n\tPORT118_FN6___2 = 2688,\n\tPORT119_FN6 = 2689,\n\tPORT120_FN6 = 2690,\n\tPORT121_FN6 = 2691,\n\tPORT122_FN6 = 2692,\n\tPORT123_FN6 = 2693,\n\tPORT124_FN6 = 2694,\n\tPORT125_FN6 = 2695,\n\tPORT126_FN6 = 2696,\n\tPORT128_FN6___2 = 2697,\n\tPORT129_FN6___2 = 2698,\n\tPORT130_FN6___2 = 2699,\n\tPORT131_FN6___2 = 2700,\n\tPORT132_FN6___2 = 2701,\n\tPORT133_FN6___2 = 2702,\n\tPORT134_FN6___2 = 2703,\n\tPORT160_FN6___2 = 2704,\n\tPORT161_FN6___2 = 2705,\n\tPORT162_FN6___2 = 2706,\n\tPORT163_FN6___2 = 2707,\n\tPORT164_FN6___2 = 2708,\n\tPORT165_FN6 = 2709,\n\tPORT166_FN6 = 2710,\n\tPORT167_FN6 = 2711,\n\tPORT168_FN6 = 2712,\n\tPORT169_FN6 = 2713,\n\tPORT170_FN6 = 2714,\n\tPORT171_FN6 = 2715,\n\tPORT172_FN6 = 2716,\n\tPORT173_FN6 = 2717,\n\tPORT174_FN6 = 2718,\n\tPORT175_FN6 = 2719,\n\tPORT176_FN6 = 2720,\n\tPORT177_FN6 = 2721,\n\tPORT178_FN6 = 2722,\n\tPORT192_FN6___2 = 2723,\n\tPORT193_FN6___2 = 2724,\n\tPORT194_FN6___2 = 2725,\n\tPORT195_FN6___2 = 2726,\n\tPORT196_FN6___2 = 2727,\n\tPORT197_FN6___2 = 2728,\n\tPORT198_FN6___2 = 2729,\n\tPORT199_FN6___2 = 2730,\n\tPORT200_FN6___2 = 2731,\n\tPORT201_FN6___2 = 2732,\n\tPORT202_FN6___2 = 2733,\n\tPORT203_FN6___2 = 2734,\n\tPORT204_FN6___2 = 2735,\n\tPORT205_FN6___2 = 2736,\n\tPORT206_FN6___2 = 2737,\n\tPORT207_FN6___2 = 2738,\n\tPORT208_FN6___2 = 2739,\n\tPORT209_FN6___2 = 2740,\n\tPORT210_FN6___2 = 2741,\n\tPORT211_FN6___2 = 2742,\n\tPORT212_FN6___2 = 2743,\n\tPORT213_FN6___2 = 2744,\n\tPORT214_FN6___2 = 2745,\n\tPORT215_FN6___2 = 2746,\n\tPORT216_FN6___2 = 2747,\n\tPORT217_FN6___2 = 2748,\n\tPORT218_FN6___2 = 2749,\n\tPORT219_FN6___2 = 2750,\n\tPORT220_FN6___2 = 2751,\n\tPORT221_FN6___2 = 2752,\n\tPORT222_FN6___2 = 2753,\n\tPORT224_FN6___2 = 2754,\n\tPORT225_FN6___2 = 2755,\n\tPORT226_FN6___2 = 2756,\n\tPORT227_FN6___2 = 2757,\n\tPORT228_FN6___2 = 2758,\n\tPORT229_FN6___2 = 2759,\n\tPORT230_FN6___2 = 2760,\n\tPORT231_FN6___2 = 2761,\n\tPORT232_FN6___2 = 2762,\n\tPORT233_FN6___2 = 2763,\n\tPORT234_FN6___2 = 2764,\n\tPORT235_FN6___2 = 2765,\n\tPORT236_FN6___2 = 2766,\n\tPORT237_FN6___2 = 2767,\n\tPORT238_FN6___2 = 2768,\n\tPORT239_FN6___2 = 2769,\n\tPORT240_FN6___2 = 2770,\n\tPORT241_FN6___2 = 2771,\n\tPORT242_FN6___2 = 2772,\n\tPORT243_FN6___2 = 2773,\n\tPORT244_FN6___2 = 2774,\n\tPORT245_FN6___2 = 2775,\n\tPORT246_FN6___2 = 2776,\n\tPORT247_FN6___2 = 2777,\n\tPORT248_FN6___2 = 2778,\n\tPORT249_FN6___2 = 2779,\n\tPORT250_FN6___2 = 2780,\n\tPORT256_FN6___2 = 2781,\n\tPORT257_FN6___2 = 2782,\n\tPORT258_FN6___2 = 2783,\n\tPORT259_FN6___2 = 2784,\n\tPORT260_FN6___2 = 2785,\n\tPORT261_FN6___2 = 2786,\n\tPORT262_FN6___2 = 2787,\n\tPORT263_FN6___2 = 2788,\n\tPORT264_FN6___2 = 2789,\n\tPORT265_FN6___2 = 2790,\n\tPORT266_FN6___2 = 2791,\n\tPORT267_FN6___2 = 2792,\n\tPORT268_FN6___2 = 2793,\n\tPORT269_FN6___2 = 2794,\n\tPORT270_FN6___2 = 2795,\n\tPORT271_FN6___2 = 2796,\n\tPORT272_FN6___2 = 2797,\n\tPORT273_FN6___2 = 2798,\n\tPORT274_FN6___2 = 2799,\n\tPORT275_FN6___2 = 2800,\n\tPORT276_FN6___2 = 2801,\n\tPORT277_FN6___2 = 2802,\n\tPORT278_FN6___2 = 2803,\n\tPORT279_FN6___2 = 2804,\n\tPORT280_FN6___2 = 2805,\n\tPORT281_FN6___2 = 2806,\n\tPORT282_FN6___2 = 2807,\n\tPORT283_FN6 = 2808,\n\tPORT288_FN6___2 = 2809,\n\tPORT289_FN6___2 = 2810,\n\tPORT290_FN6___2 = 2811,\n\tPORT291_FN6___2 = 2812,\n\tPORT292_FN6___2 = 2813,\n\tPORT293_FN6___2 = 2814,\n\tPORT294_FN6___2 = 2815,\n\tPORT295_FN6___2 = 2816,\n\tPORT296_FN6___2 = 2817,\n\tPORT297_FN6___2 = 2818,\n\tPORT298_FN6___2 = 2819,\n\tPORT299_FN6___2 = 2820,\n\tPORT300_FN6___2 = 2821,\n\tPORT301_FN6___2 = 2822,\n\tPORT302_FN6___2 = 2823,\n\tPORT303_FN6___2 = 2824,\n\tPORT304_FN6___2 = 2825,\n\tPORT305_FN6___2 = 2826,\n\tPORT306_FN6___2 = 2827,\n\tPORT307_FN6___2 = 2828,\n\tPORT308_FN6___2 = 2829,\n\tPORT320_FN6 = 2830,\n\tPORT321_FN6 = 2831,\n\tPORT322_FN6 = 2832,\n\tPORT323_FN6 = 2833,\n\tPORT324_FN6 = 2834,\n\tPORT325_FN6 = 2835,\n\tPORT326_FN6 = 2836,\n\tPORT327_FN6 = 2837,\n\tPORT328_FN6 = 2838,\n\tPORT329_FN6 = 2839,\n\tPORT0_FN7___2 = 2840,\n\tPORT1_FN7___2 = 2841,\n\tPORT2_FN7___2 = 2842,\n\tPORT3_FN7___2 = 2843,\n\tPORT4_FN7___2 = 2844,\n\tPORT5_FN7___2 = 2845,\n\tPORT6_FN7___2 = 2846,\n\tPORT7_FN7___2 = 2847,\n\tPORT8_FN7___2 = 2848,\n\tPORT9_FN7___2 = 2849,\n\tPORT10_FN7___2 = 2850,\n\tPORT11_FN7___2 = 2851,\n\tPORT12_FN7___2 = 2852,\n\tPORT13_FN7___2 = 2853,\n\tPORT14_FN7___2 = 2854,\n\tPORT15_FN7___2 = 2855,\n\tPORT16_FN7___2 = 2856,\n\tPORT17_FN7___2 = 2857,\n\tPORT18_FN7___2 = 2858,\n\tPORT19_FN7___2 = 2859,\n\tPORT20_FN7___2 = 2860,\n\tPORT21_FN7___2 = 2861,\n\tPORT22_FN7___2 = 2862,\n\tPORT23_FN7___2 = 2863,\n\tPORT24_FN7___2 = 2864,\n\tPORT25_FN7___2 = 2865,\n\tPORT26_FN7___2 = 2866,\n\tPORT27_FN7___2 = 2867,\n\tPORT28_FN7___2 = 2868,\n\tPORT29_FN7___2 = 2869,\n\tPORT30_FN7___2 = 2870,\n\tPORT32_FN7___2 = 2871,\n\tPORT33_FN7___2 = 2872,\n\tPORT34_FN7___2 = 2873,\n\tPORT35_FN7___2 = 2874,\n\tPORT36_FN7___2 = 2875,\n\tPORT37_FN7___2 = 2876,\n\tPORT38_FN7___2 = 2877,\n\tPORT39_FN7___2 = 2878,\n\tPORT40_FN7___2 = 2879,\n\tPORT64_FN7___2 = 2880,\n\tPORT65_FN7___2 = 2881,\n\tPORT66_FN7___2 = 2882,\n\tPORT67_FN7___2 = 2883,\n\tPORT68_FN7___2 = 2884,\n\tPORT69_FN7___2 = 2885,\n\tPORT70_FN7___2 = 2886,\n\tPORT71_FN7___2 = 2887,\n\tPORT72_FN7___2 = 2888,\n\tPORT73_FN7___2 = 2889,\n\tPORT74_FN7___2 = 2890,\n\tPORT75_FN7___2 = 2891,\n\tPORT76_FN7___2 = 2892,\n\tPORT77_FN7___2 = 2893,\n\tPORT78_FN7___2 = 2894,\n\tPORT79_FN7___2 = 2895,\n\tPORT80_FN7___2 = 2896,\n\tPORT81_FN7___2 = 2897,\n\tPORT82_FN7___2 = 2898,\n\tPORT83_FN7___2 = 2899,\n\tPORT84_FN7___2 = 2900,\n\tPORT85_FN7___2 = 2901,\n\tPORT96_FN7___2 = 2902,\n\tPORT97_FN7___2 = 2903,\n\tPORT98_FN7___2 = 2904,\n\tPORT99_FN7___2 = 2905,\n\tPORT100_FN7___2 = 2906,\n\tPORT101_FN7___2 = 2907,\n\tPORT102_FN7___2 = 2908,\n\tPORT103_FN7___2 = 2909,\n\tPORT104_FN7___2 = 2910,\n\tPORT105_FN7___2 = 2911,\n\tPORT106_FN7___2 = 2912,\n\tPORT107_FN7___2 = 2913,\n\tPORT108_FN7___2 = 2914,\n\tPORT109_FN7___2 = 2915,\n\tPORT110_FN7___2 = 2916,\n\tPORT111_FN7___2 = 2917,\n\tPORT112_FN7___2 = 2918,\n\tPORT113_FN7___2 = 2919,\n\tPORT114_FN7___2 = 2920,\n\tPORT115_FN7___2 = 2921,\n\tPORT116_FN7___2 = 2922,\n\tPORT117_FN7___2 = 2923,\n\tPORT118_FN7___2 = 2924,\n\tPORT119_FN7 = 2925,\n\tPORT120_FN7 = 2926,\n\tPORT121_FN7 = 2927,\n\tPORT122_FN7 = 2928,\n\tPORT123_FN7 = 2929,\n\tPORT124_FN7 = 2930,\n\tPORT125_FN7 = 2931,\n\tPORT126_FN7 = 2932,\n\tPORT128_FN7___2 = 2933,\n\tPORT129_FN7___2 = 2934,\n\tPORT130_FN7___2 = 2935,\n\tPORT131_FN7___2 = 2936,\n\tPORT132_FN7___2 = 2937,\n\tPORT133_FN7___2 = 2938,\n\tPORT134_FN7___2 = 2939,\n\tPORT160_FN7___2 = 2940,\n\tPORT161_FN7___2 = 2941,\n\tPORT162_FN7___2 = 2942,\n\tPORT163_FN7___2 = 2943,\n\tPORT164_FN7___2 = 2944,\n\tPORT165_FN7 = 2945,\n\tPORT166_FN7 = 2946,\n\tPORT167_FN7 = 2947,\n\tPORT168_FN7 = 2948,\n\tPORT169_FN7 = 2949,\n\tPORT170_FN7 = 2950,\n\tPORT171_FN7 = 2951,\n\tPORT172_FN7 = 2952,\n\tPORT173_FN7 = 2953,\n\tPORT174_FN7 = 2954,\n\tPORT175_FN7 = 2955,\n\tPORT176_FN7 = 2956,\n\tPORT177_FN7 = 2957,\n\tPORT178_FN7 = 2958,\n\tPORT192_FN7___2 = 2959,\n\tPORT193_FN7___2 = 2960,\n\tPORT194_FN7___2 = 2961,\n\tPORT195_FN7___2 = 2962,\n\tPORT196_FN7___2 = 2963,\n\tPORT197_FN7___2 = 2964,\n\tPORT198_FN7___2 = 2965,\n\tPORT199_FN7___2 = 2966,\n\tPORT200_FN7___2 = 2967,\n\tPORT201_FN7___2 = 2968,\n\tPORT202_FN7___2 = 2969,\n\tPORT203_FN7___2 = 2970,\n\tPORT204_FN7___2 = 2971,\n\tPORT205_FN7___2 = 2972,\n\tPORT206_FN7___2 = 2973,\n\tPORT207_FN7___2 = 2974,\n\tPORT208_FN7___2 = 2975,\n\tPORT209_FN7___2 = 2976,\n\tPORT210_FN7___2 = 2977,\n\tPORT211_FN7___2 = 2978,\n\tPORT212_FN7___2 = 2979,\n\tPORT213_FN7___2 = 2980,\n\tPORT214_FN7___2 = 2981,\n\tPORT215_FN7___2 = 2982,\n\tPORT216_FN7___2 = 2983,\n\tPORT217_FN7___2 = 2984,\n\tPORT218_FN7___2 = 2985,\n\tPORT219_FN7___2 = 2986,\n\tPORT220_FN7___2 = 2987,\n\tPORT221_FN7___2 = 2988,\n\tPORT222_FN7___2 = 2989,\n\tPORT224_FN7___2 = 2990,\n\tPORT225_FN7___2 = 2991,\n\tPORT226_FN7___2 = 2992,\n\tPORT227_FN7___2 = 2993,\n\tPORT228_FN7___2 = 2994,\n\tPORT229_FN7___2 = 2995,\n\tPORT230_FN7___2 = 2996,\n\tPORT231_FN7___2 = 2997,\n\tPORT232_FN7___2 = 2998,\n\tPORT233_FN7___2 = 2999,\n\tPORT234_FN7___2 = 3000,\n\tPORT235_FN7___2 = 3001,\n\tPORT236_FN7___2 = 3002,\n\tPORT237_FN7___2 = 3003,\n\tPORT238_FN7___2 = 3004,\n\tPORT239_FN7___2 = 3005,\n\tPORT240_FN7___2 = 3006,\n\tPORT241_FN7___2 = 3007,\n\tPORT242_FN7___2 = 3008,\n\tPORT243_FN7___2 = 3009,\n\tPORT244_FN7___2 = 3010,\n\tPORT245_FN7___2 = 3011,\n\tPORT246_FN7___2 = 3012,\n\tPORT247_FN7___2 = 3013,\n\tPORT248_FN7___2 = 3014,\n\tPORT249_FN7___2 = 3015,\n\tPORT250_FN7___2 = 3016,\n\tPORT256_FN7___2 = 3017,\n\tPORT257_FN7___2 = 3018,\n\tPORT258_FN7___2 = 3019,\n\tPORT259_FN7___2 = 3020,\n\tPORT260_FN7___2 = 3021,\n\tPORT261_FN7___2 = 3022,\n\tPORT262_FN7___2 = 3023,\n\tPORT263_FN7___2 = 3024,\n\tPORT264_FN7___2 = 3025,\n\tPORT265_FN7___2 = 3026,\n\tPORT266_FN7___2 = 3027,\n\tPORT267_FN7___2 = 3028,\n\tPORT268_FN7___2 = 3029,\n\tPORT269_FN7___2 = 3030,\n\tPORT270_FN7___2 = 3031,\n\tPORT271_FN7___2 = 3032,\n\tPORT272_FN7___2 = 3033,\n\tPORT273_FN7___2 = 3034,\n\tPORT274_FN7___2 = 3035,\n\tPORT275_FN7___2 = 3036,\n\tPORT276_FN7___2 = 3037,\n\tPORT277_FN7___2 = 3038,\n\tPORT278_FN7___2 = 3039,\n\tPORT279_FN7___2 = 3040,\n\tPORT280_FN7___2 = 3041,\n\tPORT281_FN7___2 = 3042,\n\tPORT282_FN7___2 = 3043,\n\tPORT283_FN7 = 3044,\n\tPORT288_FN7___2 = 3045,\n\tPORT289_FN7___2 = 3046,\n\tPORT290_FN7___2 = 3047,\n\tPORT291_FN7___2 = 3048,\n\tPORT292_FN7___2 = 3049,\n\tPORT293_FN7___2 = 3050,\n\tPORT294_FN7___2 = 3051,\n\tPORT295_FN7___2 = 3052,\n\tPORT296_FN7___2 = 3053,\n\tPORT297_FN7___2 = 3054,\n\tPORT298_FN7___2 = 3055,\n\tPORT299_FN7___2 = 3056,\n\tPORT300_FN7___2 = 3057,\n\tPORT301_FN7___2 = 3058,\n\tPORT302_FN7___2 = 3059,\n\tPORT303_FN7___2 = 3060,\n\tPORT304_FN7___2 = 3061,\n\tPORT305_FN7___2 = 3062,\n\tPORT306_FN7___2 = 3063,\n\tPORT307_FN7___2 = 3064,\n\tPORT308_FN7___2 = 3065,\n\tPORT320_FN7 = 3066,\n\tPORT321_FN7 = 3067,\n\tPORT322_FN7 = 3068,\n\tPORT323_FN7 = 3069,\n\tPORT324_FN7 = 3070,\n\tPORT325_FN7 = 3071,\n\tPORT326_FN7 = 3072,\n\tPORT327_FN7 = 3073,\n\tPORT328_FN7 = 3074,\n\tPORT329_FN7 = 3075,\n\tMSEL1CR_31_0 = 3076,\n\tMSEL1CR_31_1 = 3077,\n\tMSEL1CR_27_0 = 3078,\n\tMSEL1CR_27_1 = 3079,\n\tMSEL1CR_25_0 = 3080,\n\tMSEL1CR_25_1 = 3081,\n\tMSEL1CR_24_0 = 3082,\n\tMSEL1CR_24_1 = 3083,\n\tMSEL1CR_22_0 = 3084,\n\tMSEL1CR_22_1 = 3085,\n\tMSEL1CR_21_0 = 3086,\n\tMSEL1CR_21_1 = 3087,\n\tMSEL1CR_20_0 = 3088,\n\tMSEL1CR_20_1 = 3089,\n\tMSEL1CR_19_0 = 3090,\n\tMSEL1CR_19_1 = 3091,\n\tMSEL1CR_18_0 = 3092,\n\tMSEL1CR_18_1 = 3093,\n\tMSEL1CR_17_0 = 3094,\n\tMSEL1CR_17_1 = 3095,\n\tMSEL1CR_16_0 = 3096,\n\tMSEL1CR_16_1 = 3097,\n\tMSEL1CR_15_0 = 3098,\n\tMSEL1CR_15_1 = 3099,\n\tMSEL1CR_14_0 = 3100,\n\tMSEL1CR_14_1 = 3101,\n\tMSEL1CR_13_0 = 3102,\n\tMSEL1CR_13_1 = 3103,\n\tMSEL1CR_12_0 = 3104,\n\tMSEL1CR_12_1 = 3105,\n\tMSEL1CR_11_0 = 3106,\n\tMSEL1CR_11_1 = 3107,\n\tMSEL1CR_10_0 = 3108,\n\tMSEL1CR_10_1 = 3109,\n\tMSEL1CR_09_0 = 3110,\n\tMSEL1CR_09_1 = 3111,\n\tMSEL1CR_08_0 = 3112,\n\tMSEL1CR_08_1 = 3113,\n\tMSEL1CR_07_0 = 3114,\n\tMSEL1CR_07_1 = 3115,\n\tMSEL1CR_06_0 = 3116,\n\tMSEL1CR_06_1 = 3117,\n\tMSEL1CR_05_0 = 3118,\n\tMSEL1CR_05_1 = 3119,\n\tMSEL1CR_04_0 = 3120,\n\tMSEL1CR_04_1 = 3121,\n\tMSEL1CR_03_0 = 3122,\n\tMSEL1CR_03_1 = 3123,\n\tMSEL1CR_02_0 = 3124,\n\tMSEL1CR_02_1 = 3125,\n\tMSEL1CR_01_0 = 3126,\n\tMSEL1CR_01_1 = 3127,\n\tMSEL1CR_00_0 = 3128,\n\tMSEL1CR_00_1 = 3129,\n\tMSEL3CR_31_0 = 3130,\n\tMSEL3CR_31_1 = 3131,\n\tMSEL3CR_28_0 = 3132,\n\tMSEL3CR_28_1 = 3133,\n\tMSEL3CR_27_0 = 3134,\n\tMSEL3CR_27_1 = 3135,\n\tMSEL3CR_26_0 = 3136,\n\tMSEL3CR_26_1 = 3137,\n\tMSEL3CR_23_0 = 3138,\n\tMSEL3CR_23_1 = 3139,\n\tMSEL3CR_22_0 = 3140,\n\tMSEL3CR_22_1 = 3141,\n\tMSEL3CR_21_0 = 3142,\n\tMSEL3CR_21_1 = 3143,\n\tMSEL3CR_20_0 = 3144,\n\tMSEL3CR_20_1 = 3145,\n\tMSEL3CR_19_0 = 3146,\n\tMSEL3CR_19_1 = 3147,\n\tMSEL3CR_18_0 = 3148,\n\tMSEL3CR_18_1 = 3149,\n\tMSEL3CR_17_0 = 3150,\n\tMSEL3CR_17_1 = 3151,\n\tMSEL3CR_16_0 = 3152,\n\tMSEL3CR_16_1 = 3153,\n\tMSEL3CR_15_0 = 3154,\n\tMSEL3CR_15_1 = 3155,\n\tMSEL3CR_12_0 = 3156,\n\tMSEL3CR_12_1 = 3157,\n\tMSEL3CR_11_0 = 3158,\n\tMSEL3CR_11_1 = 3159,\n\tMSEL3CR_10_0 = 3160,\n\tMSEL3CR_10_1 = 3161,\n\tMSEL3CR_09_0 = 3162,\n\tMSEL3CR_09_1 = 3163,\n\tMSEL3CR_06_0 = 3164,\n\tMSEL3CR_06_1 = 3165,\n\tMSEL3CR_03_0 = 3166,\n\tMSEL3CR_03_1 = 3167,\n\tMSEL3CR_01_0 = 3168,\n\tMSEL3CR_01_1 = 3169,\n\tMSEL3CR_00_0 = 3170,\n\tMSEL3CR_00_1 = 3171,\n\tMSEL4CR_30_0 = 3172,\n\tMSEL4CR_30_1 = 3173,\n\tMSEL4CR_29_0 = 3174,\n\tMSEL4CR_29_1 = 3175,\n\tMSEL4CR_28_0 = 3176,\n\tMSEL4CR_28_1 = 3177,\n\tMSEL4CR_27_0 = 3178,\n\tMSEL4CR_27_1 = 3179,\n\tMSEL4CR_26_0 = 3180,\n\tMSEL4CR_26_1 = 3181,\n\tMSEL4CR_25_0 = 3182,\n\tMSEL4CR_25_1 = 3183,\n\tMSEL4CR_24_0 = 3184,\n\tMSEL4CR_24_1 = 3185,\n\tMSEL4CR_23_0 = 3186,\n\tMSEL4CR_23_1 = 3187,\n\tMSEL4CR_22_0 = 3188,\n\tMSEL4CR_22_1 = 3189,\n\tMSEL4CR_21_0 = 3190,\n\tMSEL4CR_21_1 = 3191,\n\tMSEL4CR_20_0 = 3192,\n\tMSEL4CR_20_1 = 3193,\n\tMSEL4CR_19_0 = 3194,\n\tMSEL4CR_19_1 = 3195,\n\tMSEL4CR_18_0 = 3196,\n\tMSEL4CR_18_1 = 3197,\n\tMSEL4CR_17_0 = 3198,\n\tMSEL4CR_17_1 = 3199,\n\tMSEL4CR_16_0 = 3200,\n\tMSEL4CR_16_1 = 3201,\n\tMSEL4CR_15_0 = 3202,\n\tMSEL4CR_15_1 = 3203,\n\tMSEL4CR_14_0 = 3204,\n\tMSEL4CR_14_1 = 3205,\n\tMSEL4CR_13_0 = 3206,\n\tMSEL4CR_13_1 = 3207,\n\tMSEL4CR_12_0 = 3208,\n\tMSEL4CR_12_1 = 3209,\n\tMSEL4CR_11_0 = 3210,\n\tMSEL4CR_11_1 = 3211,\n\tMSEL4CR_10_0 = 3212,\n\tMSEL4CR_10_1 = 3213,\n\tMSEL4CR_09_0 = 3214,\n\tMSEL4CR_09_1 = 3215,\n\tMSEL4CR_07_0 = 3216,\n\tMSEL4CR_07_1 = 3217,\n\tMSEL4CR_04_0 = 3218,\n\tMSEL4CR_04_1 = 3219,\n\tMSEL4CR_01_0 = 3220,\n\tMSEL4CR_01_1 = 3221,\n\tMSEL5CR_31_0 = 3222,\n\tMSEL5CR_31_1 = 3223,\n\tMSEL5CR_30_0 = 3224,\n\tMSEL5CR_30_1 = 3225,\n\tMSEL5CR_29_0 = 3226,\n\tMSEL5CR_29_1 = 3227,\n\tMSEL5CR_28_0 = 3228,\n\tMSEL5CR_28_1 = 3229,\n\tMSEL5CR_27_0 = 3230,\n\tMSEL5CR_27_1 = 3231,\n\tMSEL5CR_26_0 = 3232,\n\tMSEL5CR_26_1 = 3233,\n\tMSEL5CR_25_0 = 3234,\n\tMSEL5CR_25_1 = 3235,\n\tMSEL5CR_24_0 = 3236,\n\tMSEL5CR_24_1 = 3237,\n\tMSEL5CR_23_0 = 3238,\n\tMSEL5CR_23_1 = 3239,\n\tMSEL5CR_22_0 = 3240,\n\tMSEL5CR_22_1 = 3241,\n\tMSEL5CR_21_0 = 3242,\n\tMSEL5CR_21_1 = 3243,\n\tMSEL5CR_20_0 = 3244,\n\tMSEL5CR_20_1 = 3245,\n\tMSEL5CR_19_0 = 3246,\n\tMSEL5CR_19_1 = 3247,\n\tMSEL5CR_18_0 = 3248,\n\tMSEL5CR_18_1 = 3249,\n\tMSEL5CR_17_0 = 3250,\n\tMSEL5CR_17_1 = 3251,\n\tMSEL5CR_16_0 = 3252,\n\tMSEL5CR_16_1 = 3253,\n\tMSEL5CR_15_0 = 3254,\n\tMSEL5CR_15_1 = 3255,\n\tMSEL5CR_14_0 = 3256,\n\tMSEL5CR_14_1 = 3257,\n\tMSEL5CR_13_0 = 3258,\n\tMSEL5CR_13_1 = 3259,\n\tMSEL5CR_12_0 = 3260,\n\tMSEL5CR_12_1 = 3261,\n\tMSEL5CR_11_0 = 3262,\n\tMSEL5CR_11_1 = 3263,\n\tMSEL5CR_10_0 = 3264,\n\tMSEL5CR_10_1 = 3265,\n\tMSEL5CR_09_0 = 3266,\n\tMSEL5CR_09_1 = 3267,\n\tMSEL5CR_08_0 = 3268,\n\tMSEL5CR_08_1 = 3269,\n\tMSEL5CR_07_0 = 3270,\n\tMSEL5CR_07_1 = 3271,\n\tMSEL5CR_06_0 = 3272,\n\tMSEL5CR_06_1 = 3273,\n\tMSEL8CR_16_0 = 3274,\n\tMSEL8CR_16_1 = 3275,\n\tMSEL8CR_01_0 = 3276,\n\tMSEL8CR_01_1 = 3277,\n\tMSEL8CR_00_0 = 3278,\n\tMSEL8CR_00_1 = 3279,\n\tPINMUX_FUNCTION_END___5 = 3280,\n\tPINMUX_MARK_BEGIN___5 = 3281,\n\tLCDD0_MARK___2 = 3282,\n\tPDM2_CLK_0_MARK = 3283,\n\tDU0_DR0_MARK___3 = 3284,\n\tIRQ0_MARK___4 = 3285,\n\tLCDD1_MARK___2 = 3286,\n\tPDM2_DATA_1_MARK = 3287,\n\tDU0_DR19_MARK = 3288,\n\tIRQ1_MARK___4 = 3289,\n\tLCDD2_MARK___2 = 3290,\n\tPDM3_CLK_2_MARK = 3291,\n\tDU0_DR2_MARK___3 = 3292,\n\tIRQ2_MARK___4 = 3293,\n\tLCDD3_MARK___2 = 3294,\n\tPDM3_DATA_3_MARK = 3295,\n\tDU0_DR3_MARK___3 = 3296,\n\tIRQ3_MARK___4 = 3297,\n\tLCDD4_MARK___2 = 3298,\n\tPDM4_CLK_4_MARK = 3299,\n\tDU0_DR4_MARK___3 = 3300,\n\tIRQ4_MARK___3 = 3301,\n\tLCDD5_MARK___2 = 3302,\n\tPDM4_DATA_5_MARK = 3303,\n\tDU0_DR5_MARK___3 = 3304,\n\tIRQ5_MARK___3 = 3305,\n\tLCDD6_MARK___2 = 3306,\n\tPDM0_OUTCLK_6_MARK = 3307,\n\tDU0_DR6_MARK___3 = 3308,\n\tIRQ6_MARK___3 = 3309,\n\tLCDD7_MARK___2 = 3310,\n\tPDM0_OUTDATA_7_MARK = 3311,\n\tDU0_DR7_MARK___3 = 3312,\n\tIRQ7_MARK___3 = 3313,\n\tLCDD8_MARK___2 = 3314,\n\tPDM1_OUTCLK_8_MARK = 3315,\n\tDU0_DG0_MARK___3 = 3316,\n\tIRQ8_MARK___3 = 3317,\n\tLCDD9_MARK___2 = 3318,\n\tPDM1_OUTDATA_9_MARK = 3319,\n\tDU0_DG1_MARK___3 = 3320,\n\tIRQ9_MARK___3 = 3321,\n\tLCDD10_MARK___2 = 3322,\n\tFSICCK_MARK___2 = 3323,\n\tDU0_DG2_MARK___3 = 3324,\n\tIRQ10_MARK = 3325,\n\tLCDD11_MARK___2 = 3326,\n\tFSICISLD_MARK___2 = 3327,\n\tDU0_DG3_MARK___3 = 3328,\n\tIRQ11_MARK = 3329,\n\tLCDD12_MARK___2 = 3330,\n\tFSICOMC_MARK___2 = 3331,\n\tDU0_DG4_MARK___3 = 3332,\n\tIRQ12_MARK = 3333,\n\tLCDD13_MARK___2 = 3334,\n\tFSICOLR_MARK___2 = 3335,\n\tFSICILR_MARK___2 = 3336,\n\tDU0_DG5_MARK___3 = 3337,\n\tIRQ13_MARK = 3338,\n\tLCDD14_MARK___2 = 3339,\n\tFSICOBT_MARK___2 = 3340,\n\tFSICIBT_MARK___2 = 3341,\n\tDU0_DG6_MARK___3 = 3342,\n\tIRQ14_MARK = 3343,\n\tLCDD15_MARK___2 = 3344,\n\tFSICOSLD_MARK___2 = 3345,\n\tDU0_DG7_MARK___3 = 3346,\n\tIRQ15_MARK = 3347,\n\tLCDD16_MARK___2 = 3348,\n\tTPU1TO1_MARK = 3349,\n\tDU0_DB0_MARK___3 = 3350,\n\tLCDD17_MARK___2 = 3351,\n\tSF_IRQ_00_MARK = 3352,\n\tDU0_DB1_MARK___3 = 3353,\n\tLCDD18_MARK___2 = 3354,\n\tSF_IRQ_01_MARK = 3355,\n\tDU0_DB2_MARK___3 = 3356,\n\tLCDD19_MARK___2 = 3357,\n\tSCIFB3_RTS_19_MARK = 3358,\n\tDU0_DB3_MARK___3 = 3359,\n\tLCDD20_MARK___2 = 3360,\n\tSCIFB3_CTS_20_MARK = 3361,\n\tDU0_DB4_MARK___3 = 3362,\n\tLCDD21_MARK___2 = 3363,\n\tSCIFB3_TXD_21_MARK = 3364,\n\tDU0_DB5_MARK___3 = 3365,\n\tLCDD22_MARK___2 = 3366,\n\tSCIFB3_RXD_22_MARK = 3367,\n\tDU0_DB6_MARK___3 = 3368,\n\tLCDD23_MARK___2 = 3369,\n\tSCIFB3_SCK_23_MARK = 3370,\n\tDU0_DB7_MARK___3 = 3371,\n\tLCDHSYN_MARK___2 = 3372,\n\tLCDCS_MARK = 3373,\n\tSCIFB1_RTS_24_MARK = 3374,\n\tDU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK = 3375,\n\tLCDVSYN_MARK___2 = 3376,\n\tSCIFB1_CTS_25_MARK = 3377,\n\tDU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK = 3378,\n\tLCDDCK_MARK___2 = 3379,\n\tLCDWR_MARK = 3380,\n\tSCIFB1_TXD_26_MARK = 3381,\n\tDU0_DOTCLKIN_MARK___4 = 3382,\n\tLCDDISP_MARK___2 = 3383,\n\tLCDRS_MARK___2 = 3384,\n\tSCIFB1_RXD_27_MARK = 3385,\n\tDU0_DOTCLKOUT_MARK = 3386,\n\tLCDRD_N_MARK = 3387,\n\tSCIFB1_SCK_28_MARK = 3388,\n\tDU0_DOTCLKOUTB_MARK = 3389,\n\tLCDLCLK_MARK___2 = 3390,\n\tSF_IRQ_02_MARK = 3391,\n\tDU0_DISP_CSYNC_N_DE_MARK = 3392,\n\tLCDDON_MARK___2 = 3393,\n\tSF_IRQ_03_MARK = 3394,\n\tDU0_ODDF_N_CLAMP_MARK = 3395,\n\tSCIFA0_RTS_MARK = 3396,\n\tSIM0_DET_MARK = 3397,\n\tCSCIF0_RTS_MARK = 3398,\n\tSCIFA0_CTS_MARK = 3399,\n\tSIM1_DET_MARK = 3400,\n\tCSCIF0_CTS_MARK = 3401,\n\tSCIFA0_SCK_MARK___2 = 3402,\n\tSIM0_PWRON_MARK = 3403,\n\tCSCIF0_SCK_MARK = 3404,\n\tSCIFA1_RTS_MARK = 3405,\n\tCSCIF1_RTS_MARK = 3406,\n\tSCIFA1_CTS_MARK = 3407,\n\tCSCIF1_CTS_MARK = 3408,\n\tSCIFA1_SCK_MARK___4 = 3409,\n\tCSCIF1_SCK_MARK = 3410,\n\tSCIFB0_RTS_MARK = 3411,\n\tTPU0TO1_MARK___2 = 3412,\n\tSCIFB3_RTS_38_MARK = 3413,\n\tCHSCIF0_HRTS_MARK = 3414,\n\tSCIFB0_CTS_MARK = 3415,\n\tTPU0TO2_MARK___2 = 3416,\n\tSCIFB3_CTS_39_MARK = 3417,\n\tCHSCIF0_HCTS_MARK = 3418,\n\tSCIFB0_SCK_MARK___3 = 3419,\n\tTPU0TO3_MARK___2 = 3420,\n\tSCIFB3_SCK_40_MARK = 3421,\n\tCHSCIF0_HSCK_MARK = 3422,\n\tPDM0_DATA_MARK = 3423,\n\tPDM1_DATA_MARK = 3424,\n\tHSI_RX_WAKE_MARK___2 = 3425,\n\tSCIFB2_CTS_66_MARK = 3426,\n\tMSIOF3_SYNC_MARK = 3427,\n\tGenIO4_MARK = 3428,\n\tIRQ40_MARK = 3429,\n\tHSI_RX_READY_MARK___2 = 3430,\n\tSCIFB1_TXD_67_MARK = 3431,\n\tGIO_OUT3_67_MARK = 3432,\n\tCHSCIF1_HTX_MARK = 3433,\n\tHSI_RX_FLAG_MARK___2 = 3434,\n\tSCIFB2_TXD_68_MARK = 3435,\n\tMSIOF3_TXD_MARK = 3436,\n\tGIO_OUT4_68_MARK = 3437,\n\tHSI_RX_DATA_MARK___2 = 3438,\n\tSCIFB2_RXD_69_MARK = 3439,\n\tMSIOF3_RXD_MARK = 3440,\n\tGIO_OUT5_69_MARK = 3441,\n\tHSI_TX_FLAG_MARK___2 = 3442,\n\tSCIFB1_RTS_70_MARK = 3443,\n\tGIO_OUT1_70_MARK = 3444,\n\tHSIC_TSTCLK0_MARK = 3445,\n\tCHSCIF1_HRTS_MARK = 3446,\n\tHSI_TX_DATA_MARK___2 = 3447,\n\tSCIFB1_CTS_71_MARK = 3448,\n\tGIO_OUT2_71_MARK = 3449,\n\tHSIC_TSTCLK1_MARK = 3450,\n\tCHSCIF1_HCTS_MARK = 3451,\n\tHSI_TX_WAKE_MARK___2 = 3452,\n\tSCIFB1_RXD_72_MARK = 3453,\n\tGenIO8_MARK = 3454,\n\tCHSCIF1_HRX_MARK = 3455,\n\tHSI_TX_READY_MARK___2 = 3456,\n\tSCIFB2_RTS_73_MARK = 3457,\n\tMSIOF3_SCK_MARK = 3458,\n\tGIO_OUT0_73_MARK = 3459,\n\tIRDA_OUT_MARK = 3460,\n\tIRDA_IN_MARK = 3461,\n\tIRDA_FIRSEL_MARK = 3462,\n\tTPU0TO0_MARK___2 = 3463,\n\tDIGRFEN_MARK = 3464,\n\tGPS_TIMESTAMP_MARK = 3465,\n\tTXP_MARK = 3466,\n\tTXP2_MARK = 3467,\n\tCOEX_0_MARK = 3468,\n\tCOEX_1_MARK = 3469,\n\tIRQ19_MARK = 3470,\n\tIRQ18_MARK = 3471,\n\tKEYIN0_MARK___2 = 3472,\n\tKEYIN1_MARK___2 = 3473,\n\tKEYIN2_MARK___2 = 3474,\n\tKEYIN3_MARK___2 = 3475,\n\tKEYIN4_MARK___2 = 3476,\n\tKEYIN5_MARK___2 = 3477,\n\tKEYIN6_MARK___2 = 3478,\n\tIRQ41_MARK = 3479,\n\tKEYIN7_MARK___2 = 3480,\n\tIRQ42_MARK = 3481,\n\tKEYOUT0_MARK___2 = 3482,\n\tKEYOUT1_MARK___2 = 3483,\n\tKEYOUT2_MARK___2 = 3484,\n\tKEYOUT3_MARK___2 = 3485,\n\tKEYOUT4_MARK___2 = 3486,\n\tKEYOUT5_MARK___2 = 3487,\n\tIRQ43_MARK = 3488,\n\tKEYOUT6_MARK = 3489,\n\tIRQ44_MARK = 3490,\n\tKEYOUT7_MARK = 3491,\n\tRFANAEN_MARK = 3492,\n\tIRQ45_MARK = 3493,\n\tKEYIN8_MARK = 3494,\n\tKEYOUT8_MARK___2 = 3495,\n\tSF_IRQ_04_MARK = 3496,\n\tIRQ46_MARK = 3497,\n\tKEYIN9_MARK = 3498,\n\tKEYOUT9_MARK = 3499,\n\tSF_IRQ_05_MARK = 3500,\n\tIRQ47_MARK = 3501,\n\tKEYIN10_MARK = 3502,\n\tKEYOUT10_MARK = 3503,\n\tSF_IRQ_06_MARK = 3504,\n\tIRQ48_MARK = 3505,\n\tKEYIN11_MARK = 3506,\n\tKEYOUT11_MARK = 3507,\n\tSF_IRQ_07_MARK = 3508,\n\tIRQ49_MARK = 3509,\n\tSCIFA0_TXD_MARK___4 = 3510,\n\tCSCIF0_TX_MARK = 3511,\n\tSCIFA0_RXD_MARK___4 = 3512,\n\tCSCIF0_RX_MARK = 3513,\n\tSCIFA1_TXD_MARK___4 = 3514,\n\tCSCIF1_TX_MARK = 3515,\n\tSCIFA1_RXD_MARK___4 = 3516,\n\tCSCIF1_RX_MARK = 3517,\n\tSF_PORT_1_120_MARK = 3518,\n\tSCIFB3_RXD_120_MARK = 3519,\n\tDU0_CDE_MARK___3 = 3520,\n\tSF_PORT_0_121_MARK = 3521,\n\tSCIFB3_TXD_121_MARK = 3522,\n\tSCIFB0_TXD_MARK___3 = 3523,\n\tCHSCIF0_HTX_MARK = 3524,\n\tSCIFB0_RXD_MARK___3 = 3525,\n\tCHSCIF0_HRX_MARK = 3526,\n\tISP_STROBE_124_MARK = 3527,\n\tSTP_ISD_0_MARK___2 = 3528,\n\tPDM4_CLK_125_MARK = 3529,\n\tMSIOF2_TXD_MARK___4 = 3530,\n\tSIM0_VOLTSEL0_MARK = 3531,\n\tTS_SDEN_MARK___2 = 3532,\n\tMSIOF7_SYNC_MARK = 3533,\n\tSTP_ISEN_1_MARK = 3534,\n\tSTP_ISEN_0_MARK___2 = 3535,\n\tPDM1_OUTDATA_128_MARK = 3536,\n\tMSIOF2_SYNC_MARK___3 = 3537,\n\tSIM1_VOLTSEL1_MARK = 3538,\n\tTS_SPSYNC_MARK___2 = 3539,\n\tMSIOF7_RXD_MARK = 3540,\n\tSTP_ISSYNC_1_MARK = 3541,\n\tSTP_ISSYNC_0_MARK___2 = 3542,\n\tPDM4_DATA_130_MARK = 3543,\n\tMSIOF2_RXD_MARK___3 = 3544,\n\tSIM0_VOLTSEL1_MARK = 3545,\n\tSTP_OPWM_0_MARK___2 = 3546,\n\tSIM1_PWRON_MARK = 3547,\n\tTS_SCK_MARK___2 = 3548,\n\tMSIOF7_SCK_MARK = 3549,\n\tSTP_ISCLK_1_MARK = 3550,\n\tSTP_ISCLK_0_MARK___2 = 3551,\n\tPDM1_OUTCLK_133_MARK = 3552,\n\tMSIOF2_SCK_MARK___3 = 3553,\n\tSIM1_VOLTSEL0_MARK = 3554,\n\tTS_SDAT_MARK = 3555,\n\tMSIOF7_TXD_MARK = 3556,\n\tSTP_ISD_1_MARK = 3557,\n\tIRQ20_MARK = 3558,\n\tIRQ21_MARK = 3559,\n\tIRQ22_MARK = 3560,\n\tIRQ23_MARK = 3561,\n\tMMCD0_0_MARK___2 = 3562,\n\tMMCD0_1_MARK___2 = 3563,\n\tMMCD0_2_MARK___2 = 3564,\n\tMMCD0_3_MARK___2 = 3565,\n\tMMCD0_4_MARK___2 = 3566,\n\tMMCD0_5_MARK___2 = 3567,\n\tMMCD0_6_MARK___2 = 3568,\n\tMMCD0_7_MARK___2 = 3569,\n\tMMCCMD0_MARK___2 = 3570,\n\tMMCCLK0_MARK___2 = 3571,\n\tMMCRST_MARK = 3572,\n\tIRQ24_MARK = 3573,\n\tIRQ25_MARK = 3574,\n\tIRQ26_MARK = 3575,\n\tIRQ27_MARK = 3576,\n\tA10_MARK___3 = 3577,\n\tMMCD1_7_MARK___2 = 3578,\n\tIRQ31_MARK = 3579,\n\tA9_MARK___3 = 3580,\n\tMMCD1_6_MARK___2 = 3581,\n\tIRQ32_MARK = 3582,\n\tA8_MARK___3 = 3583,\n\tMMCD1_5_MARK___2 = 3584,\n\tIRQ33_MARK = 3585,\n\tA7_MARK___3 = 3586,\n\tMMCD1_4_MARK___2 = 3587,\n\tIRQ34_MARK = 3588,\n\tA6_MARK___3 = 3589,\n\tMMCD1_3_MARK___2 = 3590,\n\tIRQ35_MARK = 3591,\n\tA5_MARK___3 = 3592,\n\tMMCD1_2_MARK___2 = 3593,\n\tIRQ36_MARK = 3594,\n\tA4_MARK___3 = 3595,\n\tMMCD1_1_MARK___2 = 3596,\n\tIRQ37_MARK = 3597,\n\tA3_MARK___3 = 3598,\n\tMMCD1_0_MARK___2 = 3599,\n\tIRQ38_MARK = 3600,\n\tA2_MARK___3 = 3601,\n\tMMCCMD1_MARK___2 = 3602,\n\tIRQ39_MARK = 3603,\n\tA1_MARK___3 = 3604,\n\tA0_MARK___5 = 3605,\n\tBS_MARK___2 = 3606,\n\tCKO_MARK___2 = 3607,\n\tMMCCLK1_MARK___2 = 3608,\n\tCS0_N_MARK___3 = 3609,\n\tSIM0_GPO1_MARK = 3610,\n\tCS2_N_MARK = 3611,\n\tSIM0_GPO2_MARK = 3612,\n\tCS4_N_MARK = 3613,\n\tVIO_VD_MARK___2 = 3614,\n\tSIM1_GPO0_MARK = 3615,\n\tD15_MARK___3 = 3616,\n\tGIO_OUT15_MARK = 3617,\n\tD14_MARK___3 = 3618,\n\tGIO_OUT14_MARK = 3619,\n\tD13_MARK___3 = 3620,\n\tGIO_OUT13_MARK = 3621,\n\tD12_MARK___3 = 3622,\n\tGIO_OUT12_MARK = 3623,\n\tD11_MARK___3 = 3624,\n\tWGM_TXP2_MARK = 3625,\n\tD10_MARK___3 = 3626,\n\tWGM_GPS_TIMEM_ASK_RFCLK_MARK = 3627,\n\tD9_MARK___3 = 3628,\n\tVIO_D9_MARK___2 = 3629,\n\tGIO_OUT9_MARK = 3630,\n\tD8_MARK___3 = 3631,\n\tVIO_D8_MARK___2 = 3632,\n\tGIO_OUT8_MARK = 3633,\n\tD7_MARK___3 = 3634,\n\tVIO_D7_MARK___2 = 3635,\n\tGIO_OUT7_MARK = 3636,\n\tD6_MARK___3 = 3637,\n\tVIO_D6_MARK___2 = 3638,\n\tGIO_OUT6_MARK = 3639,\n\tD5_MARK___3 = 3640,\n\tVIO_D5_MARK___2 = 3641,\n\tGIO_OUT5_217_MARK = 3642,\n\tD4_MARK___3 = 3643,\n\tVIO_D4_MARK___2 = 3644,\n\tGIO_OUT4_218_MARK = 3645,\n\tD3_MARK___3 = 3646,\n\tVIO_D3_MARK___2 = 3647,\n\tGIO_OUT3_219_MARK = 3648,\n\tD2_MARK___3 = 3649,\n\tVIO_D2_MARK___2 = 3650,\n\tGIO_OUT2_220_MARK = 3651,\n\tD1_MARK___3 = 3652,\n\tVIO_D1_MARK___2 = 3653,\n\tGIO_OUT1_221_MARK = 3654,\n\tD0_MARK___3 = 3655,\n\tVIO_D0_MARK___2 = 3656,\n\tGIO_OUT0_222_MARK = 3657,\n\tRDWR_224_MARK = 3658,\n\tVIO_HD_MARK___2 = 3659,\n\tSIM1_GPO2_MARK = 3660,\n\tRD_N_MARK___3 = 3661,\n\tWAIT_N_MARK = 3662,\n\tVIO_CLK_MARK___2 = 3663,\n\tSIM1_GPO1_MARK = 3664,\n\tWE0_N_MARK___3 = 3665,\n\tRDWR_227_MARK = 3666,\n\tWE1_N_MARK___3 = 3667,\n\tSIM0_GPO0_MARK = 3668,\n\tPWMO_MARK = 3669,\n\tVIO_CKO1_229_MARK = 3670,\n\tSLIM_CLK_MARK = 3671,\n\tVIO_CKO4_230_MARK = 3672,\n\tSLIM_DATA_MARK = 3673,\n\tVIO_CKO5_231_MARK = 3674,\n\tVIO_CKO2_232_MARK = 3675,\n\tSF_PORT_0_232_MARK = 3676,\n\tVIO_CKO3_233_MARK = 3677,\n\tSF_PORT_1_233_MARK = 3678,\n\tFSIACK_MARK___2 = 3679,\n\tPDM3_CLK_234_MARK = 3680,\n\tISP_IRIS1_234_MARK = 3681,\n\tFSIAISLD_MARK___2 = 3682,\n\tPDM3_DATA_235_MARK = 3683,\n\tFSIAOMC_MARK___2 = 3684,\n\tPDM0_OUTCLK_236_MARK = 3685,\n\tISP_IRIS0_236_MARK = 3686,\n\tFSIAOLR_MARK___2 = 3687,\n\tFSIAILR_MARK___2 = 3688,\n\tFSIAOBT_MARK___2 = 3689,\n\tFSIAIBT_MARK___2 = 3690,\n\tFSIAOSLD_MARK___2 = 3691,\n\tPDM0_OUTDATA_239_MARK = 3692,\n\tFSIBISLD_MARK___2 = 3693,\n\tFSIBOLR_MARK___2 = 3694,\n\tFSIBILR_MARK___2 = 3695,\n\tFSIBOMC_MARK___2 = 3696,\n\tISP_SHUTTER1_242_MARK = 3697,\n\tFSIBOBT_MARK___2 = 3698,\n\tFSIBIBT_MARK___2 = 3699,\n\tFSIBOSLD_MARK___2 = 3700,\n\tFSIASPDIF_MARK___2 = 3701,\n\tFSIBCK_MARK___2 = 3702,\n\tISP_SHUTTER0_245_MARK = 3703,\n\tISP_IRIS1_246_MARK = 3704,\n\tISP_IRIS0_247_MARK = 3705,\n\tISP_SHUTTER1_248_MARK = 3706,\n\tISP_SHUTTER0_249_MARK = 3707,\n\tISP_STROBE_250_MARK = 3708,\n\tMSIOF0_SYNC_MARK___3 = 3709,\n\tMSIOF0_RXD_MARK___4 = 3710,\n\tMSIOF0_SCK_MARK___3 = 3711,\n\tMSIOF0_SS2_MARK___4 = 3712,\n\tVIO_CKO3_259_MARK = 3713,\n\tMSIOF0_TXD_MARK___4 = 3714,\n\tSCIFB1_SCK_261_MARK = 3715,\n\tCHSCIF1_HSCK_MARK = 3716,\n\tSCIFB2_SCK_262_MARK = 3717,\n\tMSIOF1_SS2_MARK___4 = 3718,\n\tMSIOF5_SS2_MARK = 3719,\n\tMSIOF1_TXD_MARK___4 = 3720,\n\tMSIOF5_TXD_MARK = 3721,\n\tMSIOF1_RXD_MARK___4 = 3722,\n\tMSIOF5_RXD_MARK = 3723,\n\tMSIOF1_SS1_MARK___4 = 3724,\n\tMSIOF5_SS1_MARK = 3725,\n\tMSIOF0_SS1_MARK___4 = 3726,\n\tMSIOF1_SCK_MARK___3 = 3727,\n\tMSIOF5_SCK_MARK = 3728,\n\tMSIOF1_SYNC_MARK___3 = 3729,\n\tMSIOF5_SYNC_MARK = 3730,\n\tMSIOF2_SS1_MARK___3 = 3731,\n\tVIO_CKO5_270_MARK = 3732,\n\tMSIOF2_SS2_MARK___3 = 3733,\n\tVIO_CKO2_271_MARK = 3734,\n\tMSIOF3_SS2_MARK = 3735,\n\tVIO_CKO1_272_MARK = 3736,\n\tMSIOF3_SS1_MARK = 3737,\n\tVIO_CKO4_273_MARK = 3738,\n\tMSIOF4_SS2_MARK = 3739,\n\tTPU1TO0_MARK___2 = 3740,\n\tIC_DP_MARK = 3741,\n\tSIM0_RST_MARK___2 = 3742,\n\tIC_DM_MARK = 3743,\n\tSIM0_BSICOMP_MARK = 3744,\n\tSIM0_CLK_MARK___2 = 3745,\n\tSIM0_IO_MARK = 3746,\n\tSIM1_IO_MARK = 3747,\n\tPDM2_DATA_281_MARK = 3748,\n\tSIM1_CLK_MARK = 3749,\n\tPDM2_CLK_282_MARK = 3750,\n\tSIM1_RST_MARK = 3751,\n\tSDHID1_0_MARK___2 = 3752,\n\tSTMDATA0_2_MARK = 3753,\n\tSDHID1_1_MARK___2 = 3754,\n\tSTMDATA1_2_MARK = 3755,\n\tIRQ51_MARK = 3756,\n\tSDHID1_2_MARK___2 = 3757,\n\tSTMDATA2_2_MARK = 3758,\n\tSDHID1_3_MARK___2 = 3759,\n\tSTMDATA3_2_MARK = 3760,\n\tSDHICLK1_MARK___2 = 3761,\n\tSTMCLK_2_MARK = 3762,\n\tSDHICMD1_MARK___2 = 3763,\n\tSTMSIDI_2_MARK = 3764,\n\tSDHID2_0_MARK___2 = 3765,\n\tMSIOF4_TXD_MARK = 3766,\n\tSCIFB2_TXD_295_MARK = 3767,\n\tMSIOF6_TXD_MARK = 3768,\n\tSDHID2_1_MARK___2 = 3769,\n\tMSIOF6_SS2_MARK = 3770,\n\tIRQ52_MARK = 3771,\n\tSDHID2_2_MARK___2 = 3772,\n\tMSIOF4_RXD_MARK = 3773,\n\tSCIFB2_RXD_297_MARK = 3774,\n\tMSIOF6_RXD_MARK = 3775,\n\tSDHID2_3_MARK___2 = 3776,\n\tMSIOF4_SYNC_MARK = 3777,\n\tSCIFB2_CTS_298_MARK = 3778,\n\tMSIOF6_SYNC_MARK = 3779,\n\tSDHICLK2_MARK___2 = 3780,\n\tMSIOF4_SCK_MARK = 3781,\n\tSCIFB2_SCK_299_MARK = 3782,\n\tMSIOF6_SCK_MARK = 3783,\n\tSDHICMD2_MARK___2 = 3784,\n\tMSIOF4_SS1_MARK = 3785,\n\tSCIFB2_RTS_300_MARK = 3786,\n\tMSIOF6_SS1_MARK = 3787,\n\tSDHICD0_MARK___2 = 3788,\n\tIRQ50_MARK = 3789,\n\tSDHID0_0_MARK___2 = 3790,\n\tSTMDATA0_1_MARK = 3791,\n\tSDHID0_1_MARK___2 = 3792,\n\tSTMDATA1_1_MARK = 3793,\n\tSDHID0_2_MARK___2 = 3794,\n\tSTMDATA2_1_MARK = 3795,\n\tSDHID0_3_MARK___2 = 3796,\n\tSTMDATA3_1_MARK = 3797,\n\tSDHICMD0_MARK___2 = 3798,\n\tSTMSIDI_1_MARK = 3799,\n\tSDHIWP0_MARK___2 = 3800,\n\tSDHICLK0_MARK___2 = 3801,\n\tSTMCLK_1_MARK = 3802,\n\tIRQ16_MARK = 3803,\n\tIRQ17_MARK = 3804,\n\tIRQ28_MARK = 3805,\n\tIRQ29_MARK = 3806,\n\tIRQ30_MARK = 3807,\n\tIRQ53_MARK = 3808,\n\tIRQ54_MARK = 3809,\n\tIRQ55_MARK = 3810,\n\tIRQ56_MARK = 3811,\n\tIRQ57_MARK = 3812,\n\tPINMUX_MARK_END___5 = 3813,\n};\n\nenum {\n\tPINMUX_RESERVED___6 = 0,\n\tPINMUX_DATA_BEGIN___6 = 1,\n\tPORT0_DATA___3 = 2,\n\tPORT1_DATA___3 = 3,\n\tPORT2_DATA___3 = 4,\n\tPORT3_DATA___3 = 5,\n\tPORT4_DATA___3 = 6,\n\tPORT5_DATA___3 = 7,\n\tPORT6_DATA___3 = 8,\n\tPORT7_DATA___3 = 9,\n\tPORT8_DATA___3 = 10,\n\tPORT9_DATA___3 = 11,\n\tPORT10_DATA___3 = 12,\n\tPORT11_DATA___3 = 13,\n\tPORT12_DATA___3 = 14,\n\tPORT13_DATA___3 = 15,\n\tPORT14_DATA___3 = 16,\n\tPORT15_DATA___3 = 17,\n\tPORT16_DATA___3 = 18,\n\tPORT17_DATA___3 = 19,\n\tPORT18_DATA___3 = 20,\n\tPORT19_DATA___3 = 21,\n\tPORT20_DATA___3 = 22,\n\tPORT21_DATA___3 = 23,\n\tPORT22_DATA___3 = 24,\n\tPORT23_DATA___3 = 25,\n\tPORT24_DATA___3 = 26,\n\tPORT25_DATA___3 = 27,\n\tPORT26_DATA___3 = 28,\n\tPORT27_DATA___3 = 29,\n\tPORT28_DATA___3 = 30,\n\tPORT29_DATA___3 = 31,\n\tPORT30_DATA___3 = 32,\n\tPORT31_DATA___2 = 33,\n\tPORT32_DATA___3 = 34,\n\tPORT33_DATA___3 = 35,\n\tPORT34_DATA___3 = 36,\n\tPORT35_DATA___3 = 37,\n\tPORT36_DATA___3 = 38,\n\tPORT37_DATA___3 = 39,\n\tPORT38_DATA___3 = 40,\n\tPORT39_DATA___3 = 41,\n\tPORT40_DATA___3 = 42,\n\tPORT41_DATA___2 = 43,\n\tPORT42_DATA___2 = 44,\n\tPORT43_DATA___2 = 45,\n\tPORT44_DATA___2 = 46,\n\tPORT45_DATA___2 = 47,\n\tPORT46_DATA___2 = 48,\n\tPORT47_DATA___2 = 49,\n\tPORT48_DATA___2 = 50,\n\tPORT49_DATA___2 = 51,\n\tPORT50_DATA___2 = 52,\n\tPORT51_DATA___2 = 53,\n\tPORT52_DATA___2 = 54,\n\tPORT53_DATA___2 = 55,\n\tPORT54_DATA___2 = 56,\n\tPORT55_DATA___2 = 57,\n\tPORT56_DATA___2 = 58,\n\tPORT57_DATA___2 = 59,\n\tPORT58_DATA___2 = 60,\n\tPORT59_DATA___2 = 61,\n\tPORT60_DATA___2 = 62,\n\tPORT61_DATA___2 = 63,\n\tPORT62_DATA___2 = 64,\n\tPORT63_DATA___2 = 65,\n\tPORT64_DATA___3 = 66,\n\tPORT65_DATA___3 = 67,\n\tPORT66_DATA___3 = 68,\n\tPORT67_DATA___3 = 69,\n\tPORT68_DATA___3 = 70,\n\tPORT69_DATA___3 = 71,\n\tPORT70_DATA___3 = 72,\n\tPORT71_DATA___3 = 73,\n\tPORT72_DATA___3 = 74,\n\tPORT73_DATA___3 = 75,\n\tPORT74_DATA___3 = 76,\n\tPORT75_DATA___3 = 77,\n\tPORT76_DATA___3 = 78,\n\tPORT77_DATA___3 = 79,\n\tPORT78_DATA___3 = 80,\n\tPORT79_DATA___3 = 81,\n\tPORT80_DATA___3 = 82,\n\tPORT81_DATA___3 = 83,\n\tPORT82_DATA___3 = 84,\n\tPORT83_DATA___3 = 85,\n\tPORT84_DATA___3 = 86,\n\tPORT85_DATA___3 = 87,\n\tPORT86_DATA___2 = 88,\n\tPORT87_DATA___2 = 89,\n\tPORT88_DATA___2 = 90,\n\tPORT89_DATA___2 = 91,\n\tPORT90_DATA___2 = 92,\n\tPORT91_DATA___2 = 93,\n\tPORT92_DATA___2 = 94,\n\tPORT93_DATA___2 = 95,\n\tPORT94_DATA___2 = 96,\n\tPORT95_DATA___2 = 97,\n\tPORT96_DATA___3 = 98,\n\tPORT97_DATA___3 = 99,\n\tPORT98_DATA___3 = 100,\n\tPORT99_DATA___3 = 101,\n\tPORT100_DATA___3 = 102,\n\tPORT101_DATA___3 = 103,\n\tPORT102_DATA___3 = 104,\n\tPORT103_DATA___3 = 105,\n\tPORT104_DATA___3 = 106,\n\tPORT105_DATA___3 = 107,\n\tPORT106_DATA___3 = 108,\n\tPORT107_DATA___3 = 109,\n\tPORT108_DATA___3 = 110,\n\tPORT109_DATA___3 = 111,\n\tPORT110_DATA___3 = 112,\n\tPORT111_DATA___3 = 113,\n\tPORT112_DATA___3 = 114,\n\tPORT113_DATA___3 = 115,\n\tPORT114_DATA___3 = 116,\n\tPORT115_DATA___3 = 117,\n\tPORT116_DATA___3 = 118,\n\tPORT117_DATA___3 = 119,\n\tPORT118_DATA___3 = 120,\n\tPORT119_DATA___2 = 121,\n\tPORT120_DATA___2 = 122,\n\tPORT121_DATA___2 = 123,\n\tPORT122_DATA___2 = 124,\n\tPORT123_DATA___2 = 125,\n\tPORT124_DATA___2 = 126,\n\tPORT125_DATA___2 = 127,\n\tPORT126_DATA___2 = 128,\n\tPORT127_DATA = 129,\n\tPORT128_DATA___3 = 130,\n\tPORT129_DATA___3 = 131,\n\tPORT130_DATA___3 = 132,\n\tPORT131_DATA___3 = 133,\n\tPORT132_DATA___3 = 134,\n\tPORT133_DATA___3 = 135,\n\tPORT134_DATA___3 = 136,\n\tPORT135_DATA___2 = 137,\n\tPORT136_DATA___2 = 138,\n\tPORT137_DATA___2 = 139,\n\tPORT138_DATA___2 = 140,\n\tPORT139_DATA___2 = 141,\n\tPORT140_DATA___2 = 142,\n\tPORT141_DATA___2 = 143,\n\tPORT142_DATA___2 = 144,\n\tPORT143_DATA___2 = 145,\n\tPORT144_DATA___2 = 146,\n\tPORT145_DATA___2 = 147,\n\tPORT146_DATA___2 = 148,\n\tPORT147_DATA___2 = 149,\n\tPORT148_DATA___2 = 150,\n\tPORT149_DATA___2 = 151,\n\tPORT150_DATA___2 = 152,\n\tPORT151_DATA___2 = 153,\n\tPORT152_DATA___2 = 154,\n\tPORT153_DATA___2 = 155,\n\tPORT154_DATA___2 = 156,\n\tPORT155_DATA___2 = 157,\n\tPORT156_DATA___2 = 158,\n\tPORT157_DATA___2 = 159,\n\tPORT158_DATA___2 = 160,\n\tPORT159_DATA___2 = 161,\n\tPORT160_DATA___3 = 162,\n\tPORT161_DATA___3 = 163,\n\tPORT162_DATA___3 = 164,\n\tPORT163_DATA___3 = 165,\n\tPORT164_DATA___3 = 166,\n\tPORT165_DATA___2 = 167,\n\tPORT166_DATA___2 = 168,\n\tPORT167_DATA___2 = 169,\n\tPORT168_DATA___2 = 170,\n\tPORT169_DATA___2 = 171,\n\tPORT170_DATA___2 = 172,\n\tPORT171_DATA___2 = 173,\n\tPORT172_DATA___2 = 174,\n\tPORT173_DATA___2 = 175,\n\tPORT174_DATA___2 = 176,\n\tPORT175_DATA___2 = 177,\n\tPORT176_DATA___2 = 178,\n\tPORT177_DATA___2 = 179,\n\tPORT178_DATA___2 = 180,\n\tPORT179_DATA = 181,\n\tPORT180_DATA = 182,\n\tPORT181_DATA = 183,\n\tPORT182_DATA = 184,\n\tPORT183_DATA = 185,\n\tPORT184_DATA = 186,\n\tPORT185_DATA = 187,\n\tPORT186_DATA = 188,\n\tPORT187_DATA = 189,\n\tPORT188_DATA = 190,\n\tPORT189_DATA = 191,\n\tPORT190_DATA = 192,\n\tPORT191_DATA = 193,\n\tPORT192_DATA___3 = 194,\n\tPORT193_DATA___3 = 195,\n\tPORT194_DATA___3 = 196,\n\tPORT195_DATA___3 = 197,\n\tPORT196_DATA___3 = 198,\n\tPORT197_DATA___3 = 199,\n\tPORT198_DATA___3 = 200,\n\tPORT199_DATA___3 = 201,\n\tPORT200_DATA___3 = 202,\n\tPORT201_DATA___3 = 203,\n\tPORT202_DATA___3 = 204,\n\tPORT203_DATA___3 = 205,\n\tPORT204_DATA___3 = 206,\n\tPORT205_DATA___3 = 207,\n\tPORT206_DATA___3 = 208,\n\tPORT207_DATA___3 = 209,\n\tPORT208_DATA___3 = 210,\n\tPORT209_DATA___3 = 211,\n\tPORT210_DATA___3 = 212,\n\tPORT211_DATA___3 = 213,\n\tPINMUX_DATA_END___6 = 214,\n\tPINMUX_INPUT_BEGIN___3 = 215,\n\tPORT0_IN___3 = 216,\n\tPORT1_IN___3 = 217,\n\tPORT2_IN___3 = 218,\n\tPORT3_IN___3 = 219,\n\tPORT4_IN___3 = 220,\n\tPORT5_IN___3 = 221,\n\tPORT6_IN___3 = 222,\n\tPORT7_IN___3 = 223,\n\tPORT8_IN___3 = 224,\n\tPORT9_IN___3 = 225,\n\tPORT10_IN___3 = 226,\n\tPORT11_IN___3 = 227,\n\tPORT12_IN___3 = 228,\n\tPORT13_IN___3 = 229,\n\tPORT14_IN___3 = 230,\n\tPORT15_IN___3 = 231,\n\tPORT16_IN___3 = 232,\n\tPORT17_IN___3 = 233,\n\tPORT18_IN___3 = 234,\n\tPORT19_IN___3 = 235,\n\tPORT20_IN___3 = 236,\n\tPORT21_IN___3 = 237,\n\tPORT22_IN___3 = 238,\n\tPORT23_IN___3 = 239,\n\tPORT24_IN___3 = 240,\n\tPORT25_IN___3 = 241,\n\tPORT26_IN___3 = 242,\n\tPORT27_IN___3 = 243,\n\tPORT28_IN___3 = 244,\n\tPORT29_IN___3 = 245,\n\tPORT30_IN___3 = 246,\n\tPORT31_IN___2 = 247,\n\tPORT32_IN___3 = 248,\n\tPORT33_IN___3 = 249,\n\tPORT34_IN___3 = 250,\n\tPORT35_IN___3 = 251,\n\tPORT36_IN___3 = 252,\n\tPORT37_IN___3 = 253,\n\tPORT38_IN___3 = 254,\n\tPORT39_IN___3 = 255,\n\tPORT40_IN___3 = 256,\n\tPORT41_IN___2 = 257,\n\tPORT42_IN___2 = 258,\n\tPORT43_IN___2 = 259,\n\tPORT44_IN___2 = 260,\n\tPORT45_IN___2 = 261,\n\tPORT46_IN___2 = 262,\n\tPORT47_IN___2 = 263,\n\tPORT48_IN___2 = 264,\n\tPORT49_IN___2 = 265,\n\tPORT50_IN___2 = 266,\n\tPORT51_IN___2 = 267,\n\tPORT52_IN___2 = 268,\n\tPORT53_IN___2 = 269,\n\tPORT54_IN___2 = 270,\n\tPORT55_IN___2 = 271,\n\tPORT56_IN___2 = 272,\n\tPORT57_IN___2 = 273,\n\tPORT58_IN___2 = 274,\n\tPORT59_IN___2 = 275,\n\tPORT60_IN___2 = 276,\n\tPORT61_IN___2 = 277,\n\tPORT62_IN___2 = 278,\n\tPORT63_IN___2 = 279,\n\tPORT64_IN___3 = 280,\n\tPORT65_IN___3 = 281,\n\tPORT66_IN___3 = 282,\n\tPORT67_IN___3 = 283,\n\tPORT68_IN___3 = 284,\n\tPORT69_IN___3 = 285,\n\tPORT70_IN___3 = 286,\n\tPORT71_IN___3 = 287,\n\tPORT72_IN___3 = 288,\n\tPORT73_IN___3 = 289,\n\tPORT74_IN___3 = 290,\n\tPORT75_IN___3 = 291,\n\tPORT76_IN___3 = 292,\n\tPORT77_IN___3 = 293,\n\tPORT78_IN___3 = 294,\n\tPORT79_IN___3 = 295,\n\tPORT80_IN___3 = 296,\n\tPORT81_IN___3 = 297,\n\tPORT82_IN___3 = 298,\n\tPORT83_IN___3 = 299,\n\tPORT84_IN___3 = 300,\n\tPORT85_IN___3 = 301,\n\tPORT86_IN___2 = 302,\n\tPORT87_IN___2 = 303,\n\tPORT88_IN___2 = 304,\n\tPORT89_IN___2 = 305,\n\tPORT90_IN___2 = 306,\n\tPORT91_IN___2 = 307,\n\tPORT92_IN___2 = 308,\n\tPORT93_IN___2 = 309,\n\tPORT94_IN___2 = 310,\n\tPORT95_IN___2 = 311,\n\tPORT96_IN___3 = 312,\n\tPORT97_IN___3 = 313,\n\tPORT98_IN___3 = 314,\n\tPORT99_IN___3 = 315,\n\tPORT100_IN___3 = 316,\n\tPORT101_IN___3 = 317,\n\tPORT102_IN___3 = 318,\n\tPORT103_IN___3 = 319,\n\tPORT104_IN___3 = 320,\n\tPORT105_IN___3 = 321,\n\tPORT106_IN___3 = 322,\n\tPORT107_IN___3 = 323,\n\tPORT108_IN___3 = 324,\n\tPORT109_IN___3 = 325,\n\tPORT110_IN___3 = 326,\n\tPORT111_IN___3 = 327,\n\tPORT112_IN___3 = 328,\n\tPORT113_IN___3 = 329,\n\tPORT114_IN___3 = 330,\n\tPORT115_IN___3 = 331,\n\tPORT116_IN___3 = 332,\n\tPORT117_IN___3 = 333,\n\tPORT118_IN___3 = 334,\n\tPORT119_IN___2 = 335,\n\tPORT120_IN___2 = 336,\n\tPORT121_IN___2 = 337,\n\tPORT122_IN___2 = 338,\n\tPORT123_IN___2 = 339,\n\tPORT124_IN___2 = 340,\n\tPORT125_IN___2 = 341,\n\tPORT126_IN___2 = 342,\n\tPORT127_IN = 343,\n\tPORT128_IN___3 = 344,\n\tPORT129_IN___3 = 345,\n\tPORT130_IN___3 = 346,\n\tPORT131_IN___3 = 347,\n\tPORT132_IN___3 = 348,\n\tPORT133_IN___3 = 349,\n\tPORT134_IN___3 = 350,\n\tPORT135_IN___2 = 351,\n\tPORT136_IN___2 = 352,\n\tPORT137_IN___2 = 353,\n\tPORT138_IN___2 = 354,\n\tPORT139_IN___2 = 355,\n\tPORT140_IN___2 = 356,\n\tPORT141_IN___2 = 357,\n\tPORT142_IN___2 = 358,\n\tPORT143_IN___2 = 359,\n\tPORT144_IN___2 = 360,\n\tPORT145_IN___2 = 361,\n\tPORT146_IN___2 = 362,\n\tPORT147_IN___2 = 363,\n\tPORT148_IN___2 = 364,\n\tPORT149_IN___2 = 365,\n\tPORT150_IN___2 = 366,\n\tPORT151_IN___2 = 367,\n\tPORT152_IN___2 = 368,\n\tPORT153_IN___2 = 369,\n\tPORT154_IN___2 = 370,\n\tPORT155_IN___2 = 371,\n\tPORT156_IN___2 = 372,\n\tPORT157_IN___2 = 373,\n\tPORT158_IN___2 = 374,\n\tPORT159_IN___2 = 375,\n\tPORT160_IN___3 = 376,\n\tPORT161_IN___3 = 377,\n\tPORT162_IN___3 = 378,\n\tPORT163_IN___3 = 379,\n\tPORT164_IN___3 = 380,\n\tPORT165_IN___2 = 381,\n\tPORT166_IN___2 = 382,\n\tPORT167_IN___2 = 383,\n\tPORT168_IN___2 = 384,\n\tPORT169_IN___2 = 385,\n\tPORT170_IN___2 = 386,\n\tPORT171_IN___2 = 387,\n\tPORT172_IN___2 = 388,\n\tPORT173_IN___2 = 389,\n\tPORT174_IN___2 = 390,\n\tPORT175_IN___2 = 391,\n\tPORT176_IN___2 = 392,\n\tPORT177_IN___2 = 393,\n\tPORT178_IN___2 = 394,\n\tPORT179_IN = 395,\n\tPORT180_IN = 396,\n\tPORT181_IN = 397,\n\tPORT182_IN = 398,\n\tPORT183_IN = 399,\n\tPORT184_IN = 400,\n\tPORT185_IN = 401,\n\tPORT186_IN = 402,\n\tPORT187_IN = 403,\n\tPORT188_IN = 404,\n\tPORT189_IN = 405,\n\tPORT190_IN = 406,\n\tPORT191_IN = 407,\n\tPORT192_IN___3 = 408,\n\tPORT193_IN___3 = 409,\n\tPORT194_IN___3 = 410,\n\tPORT195_IN___3 = 411,\n\tPORT196_IN___3 = 412,\n\tPORT197_IN___3 = 413,\n\tPORT198_IN___3 = 414,\n\tPORT199_IN___3 = 415,\n\tPORT200_IN___3 = 416,\n\tPORT201_IN___3 = 417,\n\tPORT202_IN___3 = 418,\n\tPORT203_IN___3 = 419,\n\tPORT204_IN___3 = 420,\n\tPORT205_IN___3 = 421,\n\tPORT206_IN___3 = 422,\n\tPORT207_IN___3 = 423,\n\tPORT208_IN___3 = 424,\n\tPORT209_IN___3 = 425,\n\tPORT210_IN___3 = 426,\n\tPORT211_IN___3 = 427,\n\tPINMUX_INPUT_END___3 = 428,\n\tPINMUX_OUTPUT_BEGIN___3 = 429,\n\tPORT0_OUT___3 = 430,\n\tPORT1_OUT___3 = 431,\n\tPORT2_OUT___3 = 432,\n\tPORT3_OUT___3 = 433,\n\tPORT4_OUT___3 = 434,\n\tPORT5_OUT___3 = 435,\n\tPORT6_OUT___3 = 436,\n\tPORT7_OUT___3 = 437,\n\tPORT8_OUT___3 = 438,\n\tPORT9_OUT___3 = 439,\n\tPORT10_OUT___3 = 440,\n\tPORT11_OUT___3 = 441,\n\tPORT12_OUT___3 = 442,\n\tPORT13_OUT___3 = 443,\n\tPORT14_OUT___3 = 444,\n\tPORT15_OUT___3 = 445,\n\tPORT16_OUT___3 = 446,\n\tPORT17_OUT___3 = 447,\n\tPORT18_OUT___3 = 448,\n\tPORT19_OUT___3 = 449,\n\tPORT20_OUT___3 = 450,\n\tPORT21_OUT___3 = 451,\n\tPORT22_OUT___3 = 452,\n\tPORT23_OUT___3 = 453,\n\tPORT24_OUT___3 = 454,\n\tPORT25_OUT___3 = 455,\n\tPORT26_OUT___3 = 456,\n\tPORT27_OUT___3 = 457,\n\tPORT28_OUT___3 = 458,\n\tPORT29_OUT___3 = 459,\n\tPORT30_OUT___3 = 460,\n\tPORT31_OUT___2 = 461,\n\tPORT32_OUT___3 = 462,\n\tPORT33_OUT___3 = 463,\n\tPORT34_OUT___3 = 464,\n\tPORT35_OUT___3 = 465,\n\tPORT36_OUT___3 = 466,\n\tPORT37_OUT___3 = 467,\n\tPORT38_OUT___3 = 468,\n\tPORT39_OUT___3 = 469,\n\tPORT40_OUT___3 = 470,\n\tPORT41_OUT___2 = 471,\n\tPORT42_OUT___2 = 472,\n\tPORT43_OUT___2 = 473,\n\tPORT44_OUT___2 = 474,\n\tPORT45_OUT___2 = 475,\n\tPORT46_OUT___2 = 476,\n\tPORT47_OUT___2 = 477,\n\tPORT48_OUT___2 = 478,\n\tPORT49_OUT___2 = 479,\n\tPORT50_OUT___2 = 480,\n\tPORT51_OUT___2 = 481,\n\tPORT52_OUT___2 = 482,\n\tPORT53_OUT___2 = 483,\n\tPORT54_OUT___2 = 484,\n\tPORT55_OUT___2 = 485,\n\tPORT56_OUT___2 = 486,\n\tPORT57_OUT___2 = 487,\n\tPORT58_OUT___2 = 488,\n\tPORT59_OUT___2 = 489,\n\tPORT60_OUT___2 = 490,\n\tPORT61_OUT___2 = 491,\n\tPORT62_OUT___2 = 492,\n\tPORT63_OUT___2 = 493,\n\tPORT64_OUT___3 = 494,\n\tPORT65_OUT___3 = 495,\n\tPORT66_OUT___3 = 496,\n\tPORT67_OUT___3 = 497,\n\tPORT68_OUT___3 = 498,\n\tPORT69_OUT___3 = 499,\n\tPORT70_OUT___3 = 500,\n\tPORT71_OUT___3 = 501,\n\tPORT72_OUT___3 = 502,\n\tPORT73_OUT___3 = 503,\n\tPORT74_OUT___3 = 504,\n\tPORT75_OUT___3 = 505,\n\tPORT76_OUT___3 = 506,\n\tPORT77_OUT___3 = 507,\n\tPORT78_OUT___3 = 508,\n\tPORT79_OUT___3 = 509,\n\tPORT80_OUT___3 = 510,\n\tPORT81_OUT___3 = 511,\n\tPORT82_OUT___3 = 512,\n\tPORT83_OUT___3 = 513,\n\tPORT84_OUT___3 = 514,\n\tPORT85_OUT___3 = 515,\n\tPORT86_OUT___2 = 516,\n\tPORT87_OUT___2 = 517,\n\tPORT88_OUT___2 = 518,\n\tPORT89_OUT___2 = 519,\n\tPORT90_OUT___2 = 520,\n\tPORT91_OUT___2 = 521,\n\tPORT92_OUT___2 = 522,\n\tPORT93_OUT___2 = 523,\n\tPORT94_OUT___2 = 524,\n\tPORT95_OUT___2 = 525,\n\tPORT96_OUT___3 = 526,\n\tPORT97_OUT___3 = 527,\n\tPORT98_OUT___3 = 528,\n\tPORT99_OUT___3 = 529,\n\tPORT100_OUT___3 = 530,\n\tPORT101_OUT___3 = 531,\n\tPORT102_OUT___3 = 532,\n\tPORT103_OUT___3 = 533,\n\tPORT104_OUT___3 = 534,\n\tPORT105_OUT___3 = 535,\n\tPORT106_OUT___3 = 536,\n\tPORT107_OUT___3 = 537,\n\tPORT108_OUT___3 = 538,\n\tPORT109_OUT___3 = 539,\n\tPORT110_OUT___3 = 540,\n\tPORT111_OUT___3 = 541,\n\tPORT112_OUT___3 = 542,\n\tPORT113_OUT___3 = 543,\n\tPORT114_OUT___3 = 544,\n\tPORT115_OUT___3 = 545,\n\tPORT116_OUT___3 = 546,\n\tPORT117_OUT___3 = 547,\n\tPORT118_OUT___3 = 548,\n\tPORT119_OUT___2 = 549,\n\tPORT120_OUT___2 = 550,\n\tPORT121_OUT___2 = 551,\n\tPORT122_OUT___2 = 552,\n\tPORT123_OUT___2 = 553,\n\tPORT124_OUT___2 = 554,\n\tPORT125_OUT___2 = 555,\n\tPORT126_OUT___2 = 556,\n\tPORT127_OUT = 557,\n\tPORT128_OUT___3 = 558,\n\tPORT129_OUT___3 = 559,\n\tPORT130_OUT___3 = 560,\n\tPORT131_OUT___3 = 561,\n\tPORT132_OUT___3 = 562,\n\tPORT133_OUT___3 = 563,\n\tPORT134_OUT___3 = 564,\n\tPORT135_OUT___2 = 565,\n\tPORT136_OUT___2 = 566,\n\tPORT137_OUT___2 = 567,\n\tPORT138_OUT___2 = 568,\n\tPORT139_OUT___2 = 569,\n\tPORT140_OUT___2 = 570,\n\tPORT141_OUT___2 = 571,\n\tPORT142_OUT___2 = 572,\n\tPORT143_OUT___2 = 573,\n\tPORT144_OUT___2 = 574,\n\tPORT145_OUT___2 = 575,\n\tPORT146_OUT___2 = 576,\n\tPORT147_OUT___2 = 577,\n\tPORT148_OUT___2 = 578,\n\tPORT149_OUT___2 = 579,\n\tPORT150_OUT___2 = 580,\n\tPORT151_OUT___2 = 581,\n\tPORT152_OUT___2 = 582,\n\tPORT153_OUT___2 = 583,\n\tPORT154_OUT___2 = 584,\n\tPORT155_OUT___2 = 585,\n\tPORT156_OUT___2 = 586,\n\tPORT157_OUT___2 = 587,\n\tPORT158_OUT___2 = 588,\n\tPORT159_OUT___2 = 589,\n\tPORT160_OUT___3 = 590,\n\tPORT161_OUT___3 = 591,\n\tPORT162_OUT___3 = 592,\n\tPORT163_OUT___3 = 593,\n\tPORT164_OUT___3 = 594,\n\tPORT165_OUT___2 = 595,\n\tPORT166_OUT___2 = 596,\n\tPORT167_OUT___2 = 597,\n\tPORT168_OUT___2 = 598,\n\tPORT169_OUT___2 = 599,\n\tPORT170_OUT___2 = 600,\n\tPORT171_OUT___2 = 601,\n\tPORT172_OUT___2 = 602,\n\tPORT173_OUT___2 = 603,\n\tPORT174_OUT___2 = 604,\n\tPORT175_OUT___2 = 605,\n\tPORT176_OUT___2 = 606,\n\tPORT177_OUT___2 = 607,\n\tPORT178_OUT___2 = 608,\n\tPORT179_OUT = 609,\n\tPORT180_OUT = 610,\n\tPORT181_OUT = 611,\n\tPORT182_OUT = 612,\n\tPORT183_OUT = 613,\n\tPORT184_OUT = 614,\n\tPORT185_OUT = 615,\n\tPORT186_OUT = 616,\n\tPORT187_OUT = 617,\n\tPORT188_OUT = 618,\n\tPORT189_OUT = 619,\n\tPORT190_OUT = 620,\n\tPORT191_OUT = 621,\n\tPORT192_OUT___3 = 622,\n\tPORT193_OUT___3 = 623,\n\tPORT194_OUT___3 = 624,\n\tPORT195_OUT___3 = 625,\n\tPORT196_OUT___3 = 626,\n\tPORT197_OUT___3 = 627,\n\tPORT198_OUT___3 = 628,\n\tPORT199_OUT___3 = 629,\n\tPORT200_OUT___3 = 630,\n\tPORT201_OUT___3 = 631,\n\tPORT202_OUT___3 = 632,\n\tPORT203_OUT___3 = 633,\n\tPORT204_OUT___3 = 634,\n\tPORT205_OUT___3 = 635,\n\tPORT206_OUT___3 = 636,\n\tPORT207_OUT___3 = 637,\n\tPORT208_OUT___3 = 638,\n\tPORT209_OUT___3 = 639,\n\tPORT210_OUT___3 = 640,\n\tPORT211_OUT___3 = 641,\n\tPINMUX_OUTPUT_END___3 = 642,\n\tPINMUX_FUNCTION_BEGIN___6 = 643,\n\tPORT0_FN_IN___3 = 644,\n\tPORT1_FN_IN___3 = 645,\n\tPORT2_FN_IN___3 = 646,\n\tPORT3_FN_IN___3 = 647,\n\tPORT4_FN_IN___3 = 648,\n\tPORT5_FN_IN___3 = 649,\n\tPORT6_FN_IN___3 = 650,\n\tPORT7_FN_IN___3 = 651,\n\tPORT8_FN_IN___3 = 652,\n\tPORT9_FN_IN___3 = 653,\n\tPORT10_FN_IN___3 = 654,\n\tPORT11_FN_IN___3 = 655,\n\tPORT12_FN_IN___3 = 656,\n\tPORT13_FN_IN___3 = 657,\n\tPORT14_FN_IN___3 = 658,\n\tPORT15_FN_IN___3 = 659,\n\tPORT16_FN_IN___3 = 660,\n\tPORT17_FN_IN___3 = 661,\n\tPORT18_FN_IN___3 = 662,\n\tPORT19_FN_IN___3 = 663,\n\tPORT20_FN_IN___3 = 664,\n\tPORT21_FN_IN___3 = 665,\n\tPORT22_FN_IN___3 = 666,\n\tPORT23_FN_IN___3 = 667,\n\tPORT24_FN_IN___3 = 668,\n\tPORT25_FN_IN___3 = 669,\n\tPORT26_FN_IN___3 = 670,\n\tPORT27_FN_IN___3 = 671,\n\tPORT28_FN_IN___3 = 672,\n\tPORT29_FN_IN___3 = 673,\n\tPORT30_FN_IN___3 = 674,\n\tPORT31_FN_IN___2 = 675,\n\tPORT32_FN_IN___3 = 676,\n\tPORT33_FN_IN___3 = 677,\n\tPORT34_FN_IN___3 = 678,\n\tPORT35_FN_IN___3 = 679,\n\tPORT36_FN_IN___3 = 680,\n\tPORT37_FN_IN___3 = 681,\n\tPORT38_FN_IN___3 = 682,\n\tPORT39_FN_IN___3 = 683,\n\tPORT40_FN_IN___3 = 684,\n\tPORT41_FN_IN___2 = 685,\n\tPORT42_FN_IN___2 = 686,\n\tPORT43_FN_IN___2 = 687,\n\tPORT44_FN_IN___2 = 688,\n\tPORT45_FN_IN___2 = 689,\n\tPORT46_FN_IN___2 = 690,\n\tPORT47_FN_IN___2 = 691,\n\tPORT48_FN_IN___2 = 692,\n\tPORT49_FN_IN___2 = 693,\n\tPORT50_FN_IN___2 = 694,\n\tPORT51_FN_IN___2 = 695,\n\tPORT52_FN_IN___2 = 696,\n\tPORT53_FN_IN___2 = 697,\n\tPORT54_FN_IN___2 = 698,\n\tPORT55_FN_IN___2 = 699,\n\tPORT56_FN_IN___2 = 700,\n\tPORT57_FN_IN___2 = 701,\n\tPORT58_FN_IN___2 = 702,\n\tPORT59_FN_IN___2 = 703,\n\tPORT60_FN_IN___2 = 704,\n\tPORT61_FN_IN___2 = 705,\n\tPORT62_FN_IN___2 = 706,\n\tPORT63_FN_IN___2 = 707,\n\tPORT64_FN_IN___3 = 708,\n\tPORT65_FN_IN___3 = 709,\n\tPORT66_FN_IN___3 = 710,\n\tPORT67_FN_IN___3 = 711,\n\tPORT68_FN_IN___3 = 712,\n\tPORT69_FN_IN___3 = 713,\n\tPORT70_FN_IN___3 = 714,\n\tPORT71_FN_IN___3 = 715,\n\tPORT72_FN_IN___3 = 716,\n\tPORT73_FN_IN___3 = 717,\n\tPORT74_FN_IN___3 = 718,\n\tPORT75_FN_IN___3 = 719,\n\tPORT76_FN_IN___3 = 720,\n\tPORT77_FN_IN___3 = 721,\n\tPORT78_FN_IN___3 = 722,\n\tPORT79_FN_IN___3 = 723,\n\tPORT80_FN_IN___3 = 724,\n\tPORT81_FN_IN___3 = 725,\n\tPORT82_FN_IN___3 = 726,\n\tPORT83_FN_IN___3 = 727,\n\tPORT84_FN_IN___3 = 728,\n\tPORT85_FN_IN___3 = 729,\n\tPORT86_FN_IN___2 = 730,\n\tPORT87_FN_IN___2 = 731,\n\tPORT88_FN_IN___2 = 732,\n\tPORT89_FN_IN___2 = 733,\n\tPORT90_FN_IN___2 = 734,\n\tPORT91_FN_IN___2 = 735,\n\tPORT92_FN_IN___2 = 736,\n\tPORT93_FN_IN___2 = 737,\n\tPORT94_FN_IN___2 = 738,\n\tPORT95_FN_IN___2 = 739,\n\tPORT96_FN_IN___3 = 740,\n\tPORT97_FN_IN___3 = 741,\n\tPORT98_FN_IN___3 = 742,\n\tPORT99_FN_IN___3 = 743,\n\tPORT100_FN_IN___3 = 744,\n\tPORT101_FN_IN___3 = 745,\n\tPORT102_FN_IN___3 = 746,\n\tPORT103_FN_IN___3 = 747,\n\tPORT104_FN_IN___3 = 748,\n\tPORT105_FN_IN___3 = 749,\n\tPORT106_FN_IN___3 = 750,\n\tPORT107_FN_IN___3 = 751,\n\tPORT108_FN_IN___3 = 752,\n\tPORT109_FN_IN___3 = 753,\n\tPORT110_FN_IN___3 = 754,\n\tPORT111_FN_IN___3 = 755,\n\tPORT112_FN_IN___3 = 756,\n\tPORT113_FN_IN___3 = 757,\n\tPORT114_FN_IN___3 = 758,\n\tPORT115_FN_IN___3 = 759,\n\tPORT116_FN_IN___3 = 760,\n\tPORT117_FN_IN___3 = 761,\n\tPORT118_FN_IN___3 = 762,\n\tPORT119_FN_IN___2 = 763,\n\tPORT120_FN_IN___2 = 764,\n\tPORT121_FN_IN___2 = 765,\n\tPORT122_FN_IN___2 = 766,\n\tPORT123_FN_IN___2 = 767,\n\tPORT124_FN_IN___2 = 768,\n\tPORT125_FN_IN___2 = 769,\n\tPORT126_FN_IN___2 = 770,\n\tPORT127_FN_IN = 771,\n\tPORT128_FN_IN___3 = 772,\n\tPORT129_FN_IN___3 = 773,\n\tPORT130_FN_IN___3 = 774,\n\tPORT131_FN_IN___3 = 775,\n\tPORT132_FN_IN___3 = 776,\n\tPORT133_FN_IN___3 = 777,\n\tPORT134_FN_IN___3 = 778,\n\tPORT135_FN_IN___2 = 779,\n\tPORT136_FN_IN___2 = 780,\n\tPORT137_FN_IN___2 = 781,\n\tPORT138_FN_IN___2 = 782,\n\tPORT139_FN_IN___2 = 783,\n\tPORT140_FN_IN___2 = 784,\n\tPORT141_FN_IN___2 = 785,\n\tPORT142_FN_IN___2 = 786,\n\tPORT143_FN_IN___2 = 787,\n\tPORT144_FN_IN___2 = 788,\n\tPORT145_FN_IN___2 = 789,\n\tPORT146_FN_IN___2 = 790,\n\tPORT147_FN_IN___2 = 791,\n\tPORT148_FN_IN___2 = 792,\n\tPORT149_FN_IN___2 = 793,\n\tPORT150_FN_IN___2 = 794,\n\tPORT151_FN_IN___2 = 795,\n\tPORT152_FN_IN___2 = 796,\n\tPORT153_FN_IN___2 = 797,\n\tPORT154_FN_IN___2 = 798,\n\tPORT155_FN_IN___2 = 799,\n\tPORT156_FN_IN___2 = 800,\n\tPORT157_FN_IN___2 = 801,\n\tPORT158_FN_IN___2 = 802,\n\tPORT159_FN_IN___2 = 803,\n\tPORT160_FN_IN___3 = 804,\n\tPORT161_FN_IN___3 = 805,\n\tPORT162_FN_IN___3 = 806,\n\tPORT163_FN_IN___3 = 807,\n\tPORT164_FN_IN___3 = 808,\n\tPORT165_FN_IN___2 = 809,\n\tPORT166_FN_IN___2 = 810,\n\tPORT167_FN_IN___2 = 811,\n\tPORT168_FN_IN___2 = 812,\n\tPORT169_FN_IN___2 = 813,\n\tPORT170_FN_IN___2 = 814,\n\tPORT171_FN_IN___2 = 815,\n\tPORT172_FN_IN___2 = 816,\n\tPORT173_FN_IN___2 = 817,\n\tPORT174_FN_IN___2 = 818,\n\tPORT175_FN_IN___2 = 819,\n\tPORT176_FN_IN___2 = 820,\n\tPORT177_FN_IN___2 = 821,\n\tPORT178_FN_IN___2 = 822,\n\tPORT179_FN_IN = 823,\n\tPORT180_FN_IN = 824,\n\tPORT181_FN_IN = 825,\n\tPORT182_FN_IN = 826,\n\tPORT183_FN_IN = 827,\n\tPORT184_FN_IN = 828,\n\tPORT185_FN_IN = 829,\n\tPORT186_FN_IN = 830,\n\tPORT187_FN_IN = 831,\n\tPORT188_FN_IN = 832,\n\tPORT189_FN_IN = 833,\n\tPORT190_FN_IN = 834,\n\tPORT191_FN_IN = 835,\n\tPORT192_FN_IN___3 = 836,\n\tPORT193_FN_IN___3 = 837,\n\tPORT194_FN_IN___3 = 838,\n\tPORT195_FN_IN___3 = 839,\n\tPORT196_FN_IN___3 = 840,\n\tPORT197_FN_IN___3 = 841,\n\tPORT198_FN_IN___3 = 842,\n\tPORT199_FN_IN___3 = 843,\n\tPORT200_FN_IN___3 = 844,\n\tPORT201_FN_IN___3 = 845,\n\tPORT202_FN_IN___3 = 846,\n\tPORT203_FN_IN___3 = 847,\n\tPORT204_FN_IN___3 = 848,\n\tPORT205_FN_IN___3 = 849,\n\tPORT206_FN_IN___3 = 850,\n\tPORT207_FN_IN___3 = 851,\n\tPORT208_FN_IN___3 = 852,\n\tPORT209_FN_IN___3 = 853,\n\tPORT210_FN_IN___3 = 854,\n\tPORT211_FN_IN___3 = 855,\n\tPORT0_FN_OUT___3 = 856,\n\tPORT1_FN_OUT___3 = 857,\n\tPORT2_FN_OUT___3 = 858,\n\tPORT3_FN_OUT___3 = 859,\n\tPORT4_FN_OUT___3 = 860,\n\tPORT5_FN_OUT___3 = 861,\n\tPORT6_FN_OUT___3 = 862,\n\tPORT7_FN_OUT___3 = 863,\n\tPORT8_FN_OUT___3 = 864,\n\tPORT9_FN_OUT___3 = 865,\n\tPORT10_FN_OUT___3 = 866,\n\tPORT11_FN_OUT___3 = 867,\n\tPORT12_FN_OUT___3 = 868,\n\tPORT13_FN_OUT___3 = 869,\n\tPORT14_FN_OUT___3 = 870,\n\tPORT15_FN_OUT___3 = 871,\n\tPORT16_FN_OUT___3 = 872,\n\tPORT17_FN_OUT___3 = 873,\n\tPORT18_FN_OUT___3 = 874,\n\tPORT19_FN_OUT___3 = 875,\n\tPORT20_FN_OUT___3 = 876,\n\tPORT21_FN_OUT___3 = 877,\n\tPORT22_FN_OUT___3 = 878,\n\tPORT23_FN_OUT___3 = 879,\n\tPORT24_FN_OUT___3 = 880,\n\tPORT25_FN_OUT___3 = 881,\n\tPORT26_FN_OUT___3 = 882,\n\tPORT27_FN_OUT___3 = 883,\n\tPORT28_FN_OUT___3 = 884,\n\tPORT29_FN_OUT___3 = 885,\n\tPORT30_FN_OUT___3 = 886,\n\tPORT31_FN_OUT___2 = 887,\n\tPORT32_FN_OUT___3 = 888,\n\tPORT33_FN_OUT___3 = 889,\n\tPORT34_FN_OUT___3 = 890,\n\tPORT35_FN_OUT___3 = 891,\n\tPORT36_FN_OUT___3 = 892,\n\tPORT37_FN_OUT___3 = 893,\n\tPORT38_FN_OUT___3 = 894,\n\tPORT39_FN_OUT___3 = 895,\n\tPORT40_FN_OUT___3 = 896,\n\tPORT41_FN_OUT___2 = 897,\n\tPORT42_FN_OUT___2 = 898,\n\tPORT43_FN_OUT___2 = 899,\n\tPORT44_FN_OUT___2 = 900,\n\tPORT45_FN_OUT___2 = 901,\n\tPORT46_FN_OUT___2 = 902,\n\tPORT47_FN_OUT___2 = 903,\n\tPORT48_FN_OUT___2 = 904,\n\tPORT49_FN_OUT___2 = 905,\n\tPORT50_FN_OUT___2 = 906,\n\tPORT51_FN_OUT___2 = 907,\n\tPORT52_FN_OUT___2 = 908,\n\tPORT53_FN_OUT___2 = 909,\n\tPORT54_FN_OUT___2 = 910,\n\tPORT55_FN_OUT___2 = 911,\n\tPORT56_FN_OUT___2 = 912,\n\tPORT57_FN_OUT___2 = 913,\n\tPORT58_FN_OUT___2 = 914,\n\tPORT59_FN_OUT___2 = 915,\n\tPORT60_FN_OUT___2 = 916,\n\tPORT61_FN_OUT___2 = 917,\n\tPORT62_FN_OUT___2 = 918,\n\tPORT63_FN_OUT___2 = 919,\n\tPORT64_FN_OUT___3 = 920,\n\tPORT65_FN_OUT___3 = 921,\n\tPORT66_FN_OUT___3 = 922,\n\tPORT67_FN_OUT___3 = 923,\n\tPORT68_FN_OUT___3 = 924,\n\tPORT69_FN_OUT___3 = 925,\n\tPORT70_FN_OUT___3 = 926,\n\tPORT71_FN_OUT___3 = 927,\n\tPORT72_FN_OUT___3 = 928,\n\tPORT73_FN_OUT___3 = 929,\n\tPORT74_FN_OUT___3 = 930,\n\tPORT75_FN_OUT___3 = 931,\n\tPORT76_FN_OUT___3 = 932,\n\tPORT77_FN_OUT___3 = 933,\n\tPORT78_FN_OUT___3 = 934,\n\tPORT79_FN_OUT___3 = 935,\n\tPORT80_FN_OUT___3 = 936,\n\tPORT81_FN_OUT___3 = 937,\n\tPORT82_FN_OUT___3 = 938,\n\tPORT83_FN_OUT___3 = 939,\n\tPORT84_FN_OUT___3 = 940,\n\tPORT85_FN_OUT___3 = 941,\n\tPORT86_FN_OUT___2 = 942,\n\tPORT87_FN_OUT___2 = 943,\n\tPORT88_FN_OUT___2 = 944,\n\tPORT89_FN_OUT___2 = 945,\n\tPORT90_FN_OUT___2 = 946,\n\tPORT91_FN_OUT___2 = 947,\n\tPORT92_FN_OUT___2 = 948,\n\tPORT93_FN_OUT___2 = 949,\n\tPORT94_FN_OUT___2 = 950,\n\tPORT95_FN_OUT___2 = 951,\n\tPORT96_FN_OUT___3 = 952,\n\tPORT97_FN_OUT___3 = 953,\n\tPORT98_FN_OUT___3 = 954,\n\tPORT99_FN_OUT___3 = 955,\n\tPORT100_FN_OUT___3 = 956,\n\tPORT101_FN_OUT___3 = 957,\n\tPORT102_FN_OUT___3 = 958,\n\tPORT103_FN_OUT___3 = 959,\n\tPORT104_FN_OUT___3 = 960,\n\tPORT105_FN_OUT___3 = 961,\n\tPORT106_FN_OUT___3 = 962,\n\tPORT107_FN_OUT___3 = 963,\n\tPORT108_FN_OUT___3 = 964,\n\tPORT109_FN_OUT___3 = 965,\n\tPORT110_FN_OUT___3 = 966,\n\tPORT111_FN_OUT___3 = 967,\n\tPORT112_FN_OUT___3 = 968,\n\tPORT113_FN_OUT___3 = 969,\n\tPORT114_FN_OUT___3 = 970,\n\tPORT115_FN_OUT___3 = 971,\n\tPORT116_FN_OUT___3 = 972,\n\tPORT117_FN_OUT___3 = 973,\n\tPORT118_FN_OUT___3 = 974,\n\tPORT119_FN_OUT___2 = 975,\n\tPORT120_FN_OUT___2 = 976,\n\tPORT121_FN_OUT___2 = 977,\n\tPORT122_FN_OUT___2 = 978,\n\tPORT123_FN_OUT___2 = 979,\n\tPORT124_FN_OUT___2 = 980,\n\tPORT125_FN_OUT___2 = 981,\n\tPORT126_FN_OUT___2 = 982,\n\tPORT127_FN_OUT = 983,\n\tPORT128_FN_OUT___3 = 984,\n\tPORT129_FN_OUT___3 = 985,\n\tPORT130_FN_OUT___3 = 986,\n\tPORT131_FN_OUT___3 = 987,\n\tPORT132_FN_OUT___3 = 988,\n\tPORT133_FN_OUT___3 = 989,\n\tPORT134_FN_OUT___3 = 990,\n\tPORT135_FN_OUT___2 = 991,\n\tPORT136_FN_OUT___2 = 992,\n\tPORT137_FN_OUT___2 = 993,\n\tPORT138_FN_OUT___2 = 994,\n\tPORT139_FN_OUT___2 = 995,\n\tPORT140_FN_OUT___2 = 996,\n\tPORT141_FN_OUT___2 = 997,\n\tPORT142_FN_OUT___2 = 998,\n\tPORT143_FN_OUT___2 = 999,\n\tPORT144_FN_OUT___2 = 1000,\n\tPORT145_FN_OUT___2 = 1001,\n\tPORT146_FN_OUT___2 = 1002,\n\tPORT147_FN_OUT___2 = 1003,\n\tPORT148_FN_OUT___2 = 1004,\n\tPORT149_FN_OUT___2 = 1005,\n\tPORT150_FN_OUT___2 = 1006,\n\tPORT151_FN_OUT___2 = 1007,\n\tPORT152_FN_OUT___2 = 1008,\n\tPORT153_FN_OUT___2 = 1009,\n\tPORT154_FN_OUT___2 = 1010,\n\tPORT155_FN_OUT___2 = 1011,\n\tPORT156_FN_OUT___2 = 1012,\n\tPORT157_FN_OUT___2 = 1013,\n\tPORT158_FN_OUT___2 = 1014,\n\tPORT159_FN_OUT___2 = 1015,\n\tPORT160_FN_OUT___3 = 1016,\n\tPORT161_FN_OUT___3 = 1017,\n\tPORT162_FN_OUT___3 = 1018,\n\tPORT163_FN_OUT___3 = 1019,\n\tPORT164_FN_OUT___3 = 1020,\n\tPORT165_FN_OUT___2 = 1021,\n\tPORT166_FN_OUT___2 = 1022,\n\tPORT167_FN_OUT___2 = 1023,\n\tPORT168_FN_OUT___2 = 1024,\n\tPORT169_FN_OUT___2 = 1025,\n\tPORT170_FN_OUT___2 = 1026,\n\tPORT171_FN_OUT___2 = 1027,\n\tPORT172_FN_OUT___2 = 1028,\n\tPORT173_FN_OUT___2 = 1029,\n\tPORT174_FN_OUT___2 = 1030,\n\tPORT175_FN_OUT___2 = 1031,\n\tPORT176_FN_OUT___2 = 1032,\n\tPORT177_FN_OUT___2 = 1033,\n\tPORT178_FN_OUT___2 = 1034,\n\tPORT179_FN_OUT = 1035,\n\tPORT180_FN_OUT = 1036,\n\tPORT181_FN_OUT = 1037,\n\tPORT182_FN_OUT = 1038,\n\tPORT183_FN_OUT = 1039,\n\tPORT184_FN_OUT = 1040,\n\tPORT185_FN_OUT = 1041,\n\tPORT186_FN_OUT = 1042,\n\tPORT187_FN_OUT = 1043,\n\tPORT188_FN_OUT = 1044,\n\tPORT189_FN_OUT = 1045,\n\tPORT190_FN_OUT = 1046,\n\tPORT191_FN_OUT = 1047,\n\tPORT192_FN_OUT___3 = 1048,\n\tPORT193_FN_OUT___3 = 1049,\n\tPORT194_FN_OUT___3 = 1050,\n\tPORT195_FN_OUT___3 = 1051,\n\tPORT196_FN_OUT___3 = 1052,\n\tPORT197_FN_OUT___3 = 1053,\n\tPORT198_FN_OUT___3 = 1054,\n\tPORT199_FN_OUT___3 = 1055,\n\tPORT200_FN_OUT___3 = 1056,\n\tPORT201_FN_OUT___3 = 1057,\n\tPORT202_FN_OUT___3 = 1058,\n\tPORT203_FN_OUT___3 = 1059,\n\tPORT204_FN_OUT___3 = 1060,\n\tPORT205_FN_OUT___3 = 1061,\n\tPORT206_FN_OUT___3 = 1062,\n\tPORT207_FN_OUT___3 = 1063,\n\tPORT208_FN_OUT___3 = 1064,\n\tPORT209_FN_OUT___3 = 1065,\n\tPORT210_FN_OUT___3 = 1066,\n\tPORT211_FN_OUT___3 = 1067,\n\tPORT0_FN0___3 = 1068,\n\tPORT1_FN0___3 = 1069,\n\tPORT2_FN0___3 = 1070,\n\tPORT3_FN0___3 = 1071,\n\tPORT4_FN0___3 = 1072,\n\tPORT5_FN0___3 = 1073,\n\tPORT6_FN0___3 = 1074,\n\tPORT7_FN0___3 = 1075,\n\tPORT8_FN0___3 = 1076,\n\tPORT9_FN0___3 = 1077,\n\tPORT10_FN0___3 = 1078,\n\tPORT11_FN0___3 = 1079,\n\tPORT12_FN0___3 = 1080,\n\tPORT13_FN0___3 = 1081,\n\tPORT14_FN0___3 = 1082,\n\tPORT15_FN0___3 = 1083,\n\tPORT16_FN0___3 = 1084,\n\tPORT17_FN0___3 = 1085,\n\tPORT18_FN0___3 = 1086,\n\tPORT19_FN0___3 = 1087,\n\tPORT20_FN0___3 = 1088,\n\tPORT21_FN0___3 = 1089,\n\tPORT22_FN0___3 = 1090,\n\tPORT23_FN0___3 = 1091,\n\tPORT24_FN0___3 = 1092,\n\tPORT25_FN0___3 = 1093,\n\tPORT26_FN0___3 = 1094,\n\tPORT27_FN0___3 = 1095,\n\tPORT28_FN0___3 = 1096,\n\tPORT29_FN0___3 = 1097,\n\tPORT30_FN0___3 = 1098,\n\tPORT31_FN0___2 = 1099,\n\tPORT32_FN0___3 = 1100,\n\tPORT33_FN0___3 = 1101,\n\tPORT34_FN0___3 = 1102,\n\tPORT35_FN0___3 = 1103,\n\tPORT36_FN0___3 = 1104,\n\tPORT37_FN0___3 = 1105,\n\tPORT38_FN0___3 = 1106,\n\tPORT39_FN0___3 = 1107,\n\tPORT40_FN0___3 = 1108,\n\tPORT41_FN0___2 = 1109,\n\tPORT42_FN0___2 = 1110,\n\tPORT43_FN0___2 = 1111,\n\tPORT44_FN0___2 = 1112,\n\tPORT45_FN0___2 = 1113,\n\tPORT46_FN0___2 = 1114,\n\tPORT47_FN0___2 = 1115,\n\tPORT48_FN0___2 = 1116,\n\tPORT49_FN0___2 = 1117,\n\tPORT50_FN0___2 = 1118,\n\tPORT51_FN0___2 = 1119,\n\tPORT52_FN0___2 = 1120,\n\tPORT53_FN0___2 = 1121,\n\tPORT54_FN0___2 = 1122,\n\tPORT55_FN0___2 = 1123,\n\tPORT56_FN0___2 = 1124,\n\tPORT57_FN0___2 = 1125,\n\tPORT58_FN0___2 = 1126,\n\tPORT59_FN0___2 = 1127,\n\tPORT60_FN0___2 = 1128,\n\tPORT61_FN0___2 = 1129,\n\tPORT62_FN0___2 = 1130,\n\tPORT63_FN0___2 = 1131,\n\tPORT64_FN0___3 = 1132,\n\tPORT65_FN0___3 = 1133,\n\tPORT66_FN0___3 = 1134,\n\tPORT67_FN0___3 = 1135,\n\tPORT68_FN0___3 = 1136,\n\tPORT69_FN0___3 = 1137,\n\tPORT70_FN0___3 = 1138,\n\tPORT71_FN0___3 = 1139,\n\tPORT72_FN0___3 = 1140,\n\tPORT73_FN0___3 = 1141,\n\tPORT74_FN0___3 = 1142,\n\tPORT75_FN0___3 = 1143,\n\tPORT76_FN0___3 = 1144,\n\tPORT77_FN0___3 = 1145,\n\tPORT78_FN0___3 = 1146,\n\tPORT79_FN0___3 = 1147,\n\tPORT80_FN0___3 = 1148,\n\tPORT81_FN0___3 = 1149,\n\tPORT82_FN0___3 = 1150,\n\tPORT83_FN0___3 = 1151,\n\tPORT84_FN0___3 = 1152,\n\tPORT85_FN0___3 = 1153,\n\tPORT86_FN0___2 = 1154,\n\tPORT87_FN0___2 = 1155,\n\tPORT88_FN0___2 = 1156,\n\tPORT89_FN0___2 = 1157,\n\tPORT90_FN0___2 = 1158,\n\tPORT91_FN0___2 = 1159,\n\tPORT92_FN0___2 = 1160,\n\tPORT93_FN0___2 = 1161,\n\tPORT94_FN0___2 = 1162,\n\tPORT95_FN0___2 = 1163,\n\tPORT96_FN0___3 = 1164,\n\tPORT97_FN0___3 = 1165,\n\tPORT98_FN0___3 = 1166,\n\tPORT99_FN0___3 = 1167,\n\tPORT100_FN0___3 = 1168,\n\tPORT101_FN0___3 = 1169,\n\tPORT102_FN0___3 = 1170,\n\tPORT103_FN0___3 = 1171,\n\tPORT104_FN0___3 = 1172,\n\tPORT105_FN0___3 = 1173,\n\tPORT106_FN0___3 = 1174,\n\tPORT107_FN0___3 = 1175,\n\tPORT108_FN0___3 = 1176,\n\tPORT109_FN0___3 = 1177,\n\tPORT110_FN0___3 = 1178,\n\tPORT111_FN0___3 = 1179,\n\tPORT112_FN0___3 = 1180,\n\tPORT113_FN0___3 = 1181,\n\tPORT114_FN0___3 = 1182,\n\tPORT115_FN0___3 = 1183,\n\tPORT116_FN0___3 = 1184,\n\tPORT117_FN0___3 = 1185,\n\tPORT118_FN0___3 = 1186,\n\tPORT119_FN0___2 = 1187,\n\tPORT120_FN0___2 = 1188,\n\tPORT121_FN0___2 = 1189,\n\tPORT122_FN0___2 = 1190,\n\tPORT123_FN0___2 = 1191,\n\tPORT124_FN0___2 = 1192,\n\tPORT125_FN0___2 = 1193,\n\tPORT126_FN0___2 = 1194,\n\tPORT127_FN0 = 1195,\n\tPORT128_FN0___3 = 1196,\n\tPORT129_FN0___3 = 1197,\n\tPORT130_FN0___3 = 1198,\n\tPORT131_FN0___3 = 1199,\n\tPORT132_FN0___3 = 1200,\n\tPORT133_FN0___3 = 1201,\n\tPORT134_FN0___3 = 1202,\n\tPORT135_FN0___2 = 1203,\n\tPORT136_FN0___2 = 1204,\n\tPORT137_FN0___2 = 1205,\n\tPORT138_FN0___2 = 1206,\n\tPORT139_FN0___2 = 1207,\n\tPORT140_FN0___2 = 1208,\n\tPORT141_FN0___2 = 1209,\n\tPORT142_FN0___2 = 1210,\n\tPORT143_FN0___2 = 1211,\n\tPORT144_FN0___2 = 1212,\n\tPORT145_FN0___2 = 1213,\n\tPORT146_FN0___2 = 1214,\n\tPORT147_FN0___2 = 1215,\n\tPORT148_FN0___2 = 1216,\n\tPORT149_FN0___2 = 1217,\n\tPORT150_FN0___2 = 1218,\n\tPORT151_FN0___2 = 1219,\n\tPORT152_FN0___2 = 1220,\n\tPORT153_FN0___2 = 1221,\n\tPORT154_FN0___2 = 1222,\n\tPORT155_FN0___2 = 1223,\n\tPORT156_FN0___2 = 1224,\n\tPORT157_FN0___2 = 1225,\n\tPORT158_FN0___2 = 1226,\n\tPORT159_FN0___2 = 1227,\n\tPORT160_FN0___3 = 1228,\n\tPORT161_FN0___3 = 1229,\n\tPORT162_FN0___3 = 1230,\n\tPORT163_FN0___3 = 1231,\n\tPORT164_FN0___3 = 1232,\n\tPORT165_FN0___2 = 1233,\n\tPORT166_FN0___2 = 1234,\n\tPORT167_FN0___2 = 1235,\n\tPORT168_FN0___2 = 1236,\n\tPORT169_FN0___2 = 1237,\n\tPORT170_FN0___2 = 1238,\n\tPORT171_FN0___2 = 1239,\n\tPORT172_FN0___2 = 1240,\n\tPORT173_FN0___2 = 1241,\n\tPORT174_FN0___2 = 1242,\n\tPORT175_FN0___2 = 1243,\n\tPORT176_FN0___2 = 1244,\n\tPORT177_FN0___2 = 1245,\n\tPORT178_FN0___2 = 1246,\n\tPORT179_FN0 = 1247,\n\tPORT180_FN0 = 1248,\n\tPORT181_FN0 = 1249,\n\tPORT182_FN0 = 1250,\n\tPORT183_FN0 = 1251,\n\tPORT184_FN0 = 1252,\n\tPORT185_FN0 = 1253,\n\tPORT186_FN0 = 1254,\n\tPORT187_FN0 = 1255,\n\tPORT188_FN0 = 1256,\n\tPORT189_FN0 = 1257,\n\tPORT190_FN0 = 1258,\n\tPORT191_FN0 = 1259,\n\tPORT192_FN0___3 = 1260,\n\tPORT193_FN0___3 = 1261,\n\tPORT194_FN0___3 = 1262,\n\tPORT195_FN0___3 = 1263,\n\tPORT196_FN0___3 = 1264,\n\tPORT197_FN0___3 = 1265,\n\tPORT198_FN0___3 = 1266,\n\tPORT199_FN0___3 = 1267,\n\tPORT200_FN0___3 = 1268,\n\tPORT201_FN0___3 = 1269,\n\tPORT202_FN0___3 = 1270,\n\tPORT203_FN0___3 = 1271,\n\tPORT204_FN0___3 = 1272,\n\tPORT205_FN0___3 = 1273,\n\tPORT206_FN0___3 = 1274,\n\tPORT207_FN0___3 = 1275,\n\tPORT208_FN0___3 = 1276,\n\tPORT209_FN0___3 = 1277,\n\tPORT210_FN0___3 = 1278,\n\tPORT211_FN0___3 = 1279,\n\tPORT0_FN1___3 = 1280,\n\tPORT1_FN1___3 = 1281,\n\tPORT2_FN1___3 = 1282,\n\tPORT3_FN1___3 = 1283,\n\tPORT4_FN1___3 = 1284,\n\tPORT5_FN1___3 = 1285,\n\tPORT6_FN1___3 = 1286,\n\tPORT7_FN1___3 = 1287,\n\tPORT8_FN1___3 = 1288,\n\tPORT9_FN1___3 = 1289,\n\tPORT10_FN1___3 = 1290,\n\tPORT11_FN1___3 = 1291,\n\tPORT12_FN1___3 = 1292,\n\tPORT13_FN1___3 = 1293,\n\tPORT14_FN1___3 = 1294,\n\tPORT15_FN1___3 = 1295,\n\tPORT16_FN1___3 = 1296,\n\tPORT17_FN1___3 = 1297,\n\tPORT18_FN1___3 = 1298,\n\tPORT19_FN1___3 = 1299,\n\tPORT20_FN1___3 = 1300,\n\tPORT21_FN1___3 = 1301,\n\tPORT22_FN1___3 = 1302,\n\tPORT23_FN1___3 = 1303,\n\tPORT24_FN1___3 = 1304,\n\tPORT25_FN1___3 = 1305,\n\tPORT26_FN1___3 = 1306,\n\tPORT27_FN1___3 = 1307,\n\tPORT28_FN1___3 = 1308,\n\tPORT29_FN1___3 = 1309,\n\tPORT30_FN1___3 = 1310,\n\tPORT31_FN1___2 = 1311,\n\tPORT32_FN1___3 = 1312,\n\tPORT33_FN1___3 = 1313,\n\tPORT34_FN1___3 = 1314,\n\tPORT35_FN1___3 = 1315,\n\tPORT36_FN1___3 = 1316,\n\tPORT37_FN1___3 = 1317,\n\tPORT38_FN1___3 = 1318,\n\tPORT39_FN1___3 = 1319,\n\tPORT40_FN1___3 = 1320,\n\tPORT41_FN1___2 = 1321,\n\tPORT42_FN1___2 = 1322,\n\tPORT43_FN1___2 = 1323,\n\tPORT44_FN1___2 = 1324,\n\tPORT45_FN1___2 = 1325,\n\tPORT46_FN1___2 = 1326,\n\tPORT47_FN1___2 = 1327,\n\tPORT48_FN1___2 = 1328,\n\tPORT49_FN1___2 = 1329,\n\tPORT50_FN1___2 = 1330,\n\tPORT51_FN1___2 = 1331,\n\tPORT52_FN1___2 = 1332,\n\tPORT53_FN1___2 = 1333,\n\tPORT54_FN1___2 = 1334,\n\tPORT55_FN1___2 = 1335,\n\tPORT56_FN1___2 = 1336,\n\tPORT57_FN1___2 = 1337,\n\tPORT58_FN1___2 = 1338,\n\tPORT59_FN1___2 = 1339,\n\tPORT60_FN1___2 = 1340,\n\tPORT61_FN1___2 = 1341,\n\tPORT62_FN1___2 = 1342,\n\tPORT63_FN1___2 = 1343,\n\tPORT64_FN1___3 = 1344,\n\tPORT65_FN1___3 = 1345,\n\tPORT66_FN1___3 = 1346,\n\tPORT67_FN1___3 = 1347,\n\tPORT68_FN1___3 = 1348,\n\tPORT69_FN1___3 = 1349,\n\tPORT70_FN1___3 = 1350,\n\tPORT71_FN1___3 = 1351,\n\tPORT72_FN1___3 = 1352,\n\tPORT73_FN1___3 = 1353,\n\tPORT74_FN1___3 = 1354,\n\tPORT75_FN1___3 = 1355,\n\tPORT76_FN1___3 = 1356,\n\tPORT77_FN1___3 = 1357,\n\tPORT78_FN1___3 = 1358,\n\tPORT79_FN1___3 = 1359,\n\tPORT80_FN1___3 = 1360,\n\tPORT81_FN1___3 = 1361,\n\tPORT82_FN1___3 = 1362,\n\tPORT83_FN1___3 = 1363,\n\tPORT84_FN1___3 = 1364,\n\tPORT85_FN1___3 = 1365,\n\tPORT86_FN1___2 = 1366,\n\tPORT87_FN1___2 = 1367,\n\tPORT88_FN1___2 = 1368,\n\tPORT89_FN1___2 = 1369,\n\tPORT90_FN1___2 = 1370,\n\tPORT91_FN1___2 = 1371,\n\tPORT92_FN1___2 = 1372,\n\tPORT93_FN1___2 = 1373,\n\tPORT94_FN1___2 = 1374,\n\tPORT95_FN1___2 = 1375,\n\tPORT96_FN1___3 = 1376,\n\tPORT97_FN1___3 = 1377,\n\tPORT98_FN1___3 = 1378,\n\tPORT99_FN1___3 = 1379,\n\tPORT100_FN1___3 = 1380,\n\tPORT101_FN1___3 = 1381,\n\tPORT102_FN1___3 = 1382,\n\tPORT103_FN1___3 = 1383,\n\tPORT104_FN1___3 = 1384,\n\tPORT105_FN1___3 = 1385,\n\tPORT106_FN1___3 = 1386,\n\tPORT107_FN1___3 = 1387,\n\tPORT108_FN1___3 = 1388,\n\tPORT109_FN1___3 = 1389,\n\tPORT110_FN1___3 = 1390,\n\tPORT111_FN1___3 = 1391,\n\tPORT112_FN1___3 = 1392,\n\tPORT113_FN1___3 = 1393,\n\tPORT114_FN1___3 = 1394,\n\tPORT115_FN1___3 = 1395,\n\tPORT116_FN1___3 = 1396,\n\tPORT117_FN1___3 = 1397,\n\tPORT118_FN1___3 = 1398,\n\tPORT119_FN1___2 = 1399,\n\tPORT120_FN1___2 = 1400,\n\tPORT121_FN1___2 = 1401,\n\tPORT122_FN1___2 = 1402,\n\tPORT123_FN1___2 = 1403,\n\tPORT124_FN1___2 = 1404,\n\tPORT125_FN1___2 = 1405,\n\tPORT126_FN1___2 = 1406,\n\tPORT127_FN1 = 1407,\n\tPORT128_FN1___3 = 1408,\n\tPORT129_FN1___3 = 1409,\n\tPORT130_FN1___3 = 1410,\n\tPORT131_FN1___3 = 1411,\n\tPORT132_FN1___3 = 1412,\n\tPORT133_FN1___3 = 1413,\n\tPORT134_FN1___3 = 1414,\n\tPORT135_FN1___2 = 1415,\n\tPORT136_FN1___2 = 1416,\n\tPORT137_FN1___2 = 1417,\n\tPORT138_FN1___2 = 1418,\n\tPORT139_FN1___2 = 1419,\n\tPORT140_FN1___2 = 1420,\n\tPORT141_FN1___2 = 1421,\n\tPORT142_FN1___2 = 1422,\n\tPORT143_FN1___2 = 1423,\n\tPORT144_FN1___2 = 1424,\n\tPORT145_FN1___2 = 1425,\n\tPORT146_FN1___2 = 1426,\n\tPORT147_FN1___2 = 1427,\n\tPORT148_FN1___2 = 1428,\n\tPORT149_FN1___2 = 1429,\n\tPORT150_FN1___2 = 1430,\n\tPORT151_FN1___2 = 1431,\n\tPORT152_FN1___2 = 1432,\n\tPORT153_FN1___2 = 1433,\n\tPORT154_FN1___2 = 1434,\n\tPORT155_FN1___2 = 1435,\n\tPORT156_FN1___2 = 1436,\n\tPORT157_FN1___2 = 1437,\n\tPORT158_FN1___2 = 1438,\n\tPORT159_FN1___2 = 1439,\n\tPORT160_FN1___3 = 1440,\n\tPORT161_FN1___3 = 1441,\n\tPORT162_FN1___3 = 1442,\n\tPORT163_FN1___3 = 1443,\n\tPORT164_FN1___3 = 1444,\n\tPORT165_FN1___2 = 1445,\n\tPORT166_FN1___2 = 1446,\n\tPORT167_FN1___2 = 1447,\n\tPORT168_FN1___2 = 1448,\n\tPORT169_FN1___2 = 1449,\n\tPORT170_FN1___2 = 1450,\n\tPORT171_FN1___2 = 1451,\n\tPORT172_FN1___2 = 1452,\n\tPORT173_FN1___2 = 1453,\n\tPORT174_FN1___2 = 1454,\n\tPORT175_FN1___2 = 1455,\n\tPORT176_FN1___2 = 1456,\n\tPORT177_FN1___2 = 1457,\n\tPORT178_FN1___2 = 1458,\n\tPORT179_FN1 = 1459,\n\tPORT180_FN1 = 1460,\n\tPORT181_FN1 = 1461,\n\tPORT182_FN1 = 1462,\n\tPORT183_FN1 = 1463,\n\tPORT184_FN1 = 1464,\n\tPORT185_FN1 = 1465,\n\tPORT186_FN1 = 1466,\n\tPORT187_FN1 = 1467,\n\tPORT188_FN1 = 1468,\n\tPORT189_FN1 = 1469,\n\tPORT190_FN1 = 1470,\n\tPORT191_FN1 = 1471,\n\tPORT192_FN1___3 = 1472,\n\tPORT193_FN1___3 = 1473,\n\tPORT194_FN1___3 = 1474,\n\tPORT195_FN1___3 = 1475,\n\tPORT196_FN1___3 = 1476,\n\tPORT197_FN1___3 = 1477,\n\tPORT198_FN1___3 = 1478,\n\tPORT199_FN1___3 = 1479,\n\tPORT200_FN1___3 = 1480,\n\tPORT201_FN1___3 = 1481,\n\tPORT202_FN1___3 = 1482,\n\tPORT203_FN1___3 = 1483,\n\tPORT204_FN1___3 = 1484,\n\tPORT205_FN1___3 = 1485,\n\tPORT206_FN1___3 = 1486,\n\tPORT207_FN1___3 = 1487,\n\tPORT208_FN1___3 = 1488,\n\tPORT209_FN1___3 = 1489,\n\tPORT210_FN1___3 = 1490,\n\tPORT211_FN1___3 = 1491,\n\tPORT0_FN2___3 = 1492,\n\tPORT1_FN2___3 = 1493,\n\tPORT2_FN2___3 = 1494,\n\tPORT3_FN2___3 = 1495,\n\tPORT4_FN2___3 = 1496,\n\tPORT5_FN2___3 = 1497,\n\tPORT6_FN2___3 = 1498,\n\tPORT7_FN2___3 = 1499,\n\tPORT8_FN2___3 = 1500,\n\tPORT9_FN2___3 = 1501,\n\tPORT10_FN2___3 = 1502,\n\tPORT11_FN2___3 = 1503,\n\tPORT12_FN2___3 = 1504,\n\tPORT13_FN2___3 = 1505,\n\tPORT14_FN2___3 = 1506,\n\tPORT15_FN2___3 = 1507,\n\tPORT16_FN2___3 = 1508,\n\tPORT17_FN2___3 = 1509,\n\tPORT18_FN2___3 = 1510,\n\tPORT19_FN2___3 = 1511,\n\tPORT20_FN2___3 = 1512,\n\tPORT21_FN2___3 = 1513,\n\tPORT22_FN2___3 = 1514,\n\tPORT23_FN2___3 = 1515,\n\tPORT24_FN2___3 = 1516,\n\tPORT25_FN2___3 = 1517,\n\tPORT26_FN2___3 = 1518,\n\tPORT27_FN2___3 = 1519,\n\tPORT28_FN2___3 = 1520,\n\tPORT29_FN2___3 = 1521,\n\tPORT30_FN2___3 = 1522,\n\tPORT31_FN2___2 = 1523,\n\tPORT32_FN2___3 = 1524,\n\tPORT33_FN2___3 = 1525,\n\tPORT34_FN2___3 = 1526,\n\tPORT35_FN2___3 = 1527,\n\tPORT36_FN2___3 = 1528,\n\tPORT37_FN2___3 = 1529,\n\tPORT38_FN2___3 = 1530,\n\tPORT39_FN2___3 = 1531,\n\tPORT40_FN2___3 = 1532,\n\tPORT41_FN2___2 = 1533,\n\tPORT42_FN2___2 = 1534,\n\tPORT43_FN2___2 = 1535,\n\tPORT44_FN2___2 = 1536,\n\tPORT45_FN2___2 = 1537,\n\tPORT46_FN2___2 = 1538,\n\tPORT47_FN2___2 = 1539,\n\tPORT48_FN2___2 = 1540,\n\tPORT49_FN2___2 = 1541,\n\tPORT50_FN2___2 = 1542,\n\tPORT51_FN2___2 = 1543,\n\tPORT52_FN2___2 = 1544,\n\tPORT53_FN2___2 = 1545,\n\tPORT54_FN2___2 = 1546,\n\tPORT55_FN2___2 = 1547,\n\tPORT56_FN2___2 = 1548,\n\tPORT57_FN2___2 = 1549,\n\tPORT58_FN2___2 = 1550,\n\tPORT59_FN2___2 = 1551,\n\tPORT60_FN2___2 = 1552,\n\tPORT61_FN2___2 = 1553,\n\tPORT62_FN2___2 = 1554,\n\tPORT63_FN2___2 = 1555,\n\tPORT64_FN2___3 = 1556,\n\tPORT65_FN2___3 = 1557,\n\tPORT66_FN2___3 = 1558,\n\tPORT67_FN2___3 = 1559,\n\tPORT68_FN2___3 = 1560,\n\tPORT69_FN2___3 = 1561,\n\tPORT70_FN2___3 = 1562,\n\tPORT71_FN2___3 = 1563,\n\tPORT72_FN2___3 = 1564,\n\tPORT73_FN2___3 = 1565,\n\tPORT74_FN2___3 = 1566,\n\tPORT75_FN2___3 = 1567,\n\tPORT76_FN2___3 = 1568,\n\tPORT77_FN2___3 = 1569,\n\tPORT78_FN2___3 = 1570,\n\tPORT79_FN2___3 = 1571,\n\tPORT80_FN2___3 = 1572,\n\tPORT81_FN2___3 = 1573,\n\tPORT82_FN2___3 = 1574,\n\tPORT83_FN2___3 = 1575,\n\tPORT84_FN2___3 = 1576,\n\tPORT85_FN2___3 = 1577,\n\tPORT86_FN2___2 = 1578,\n\tPORT87_FN2___2 = 1579,\n\tPORT88_FN2___2 = 1580,\n\tPORT89_FN2___2 = 1581,\n\tPORT90_FN2___2 = 1582,\n\tPORT91_FN2___2 = 1583,\n\tPORT92_FN2___2 = 1584,\n\tPORT93_FN2___2 = 1585,\n\tPORT94_FN2___2 = 1586,\n\tPORT95_FN2___2 = 1587,\n\tPORT96_FN2___3 = 1588,\n\tPORT97_FN2___3 = 1589,\n\tPORT98_FN2___3 = 1590,\n\tPORT99_FN2___3 = 1591,\n\tPORT100_FN2___3 = 1592,\n\tPORT101_FN2___3 = 1593,\n\tPORT102_FN2___3 = 1594,\n\tPORT103_FN2___3 = 1595,\n\tPORT104_FN2___3 = 1596,\n\tPORT105_FN2___3 = 1597,\n\tPORT106_FN2___3 = 1598,\n\tPORT107_FN2___3 = 1599,\n\tPORT108_FN2___3 = 1600,\n\tPORT109_FN2___3 = 1601,\n\tPORT110_FN2___3 = 1602,\n\tPORT111_FN2___3 = 1603,\n\tPORT112_FN2___3 = 1604,\n\tPORT113_FN2___3 = 1605,\n\tPORT114_FN2___3 = 1606,\n\tPORT115_FN2___3 = 1607,\n\tPORT116_FN2___3 = 1608,\n\tPORT117_FN2___3 = 1609,\n\tPORT118_FN2___3 = 1610,\n\tPORT119_FN2___2 = 1611,\n\tPORT120_FN2___2 = 1612,\n\tPORT121_FN2___2 = 1613,\n\tPORT122_FN2___2 = 1614,\n\tPORT123_FN2___2 = 1615,\n\tPORT124_FN2___2 = 1616,\n\tPORT125_FN2___2 = 1617,\n\tPORT126_FN2___2 = 1618,\n\tPORT127_FN2 = 1619,\n\tPORT128_FN2___3 = 1620,\n\tPORT129_FN2___3 = 1621,\n\tPORT130_FN2___3 = 1622,\n\tPORT131_FN2___3 = 1623,\n\tPORT132_FN2___3 = 1624,\n\tPORT133_FN2___3 = 1625,\n\tPORT134_FN2___3 = 1626,\n\tPORT135_FN2___2 = 1627,\n\tPORT136_FN2___2 = 1628,\n\tPORT137_FN2___2 = 1629,\n\tPORT138_FN2___2 = 1630,\n\tPORT139_FN2___2 = 1631,\n\tPORT140_FN2___2 = 1632,\n\tPORT141_FN2___2 = 1633,\n\tPORT142_FN2___2 = 1634,\n\tPORT143_FN2___2 = 1635,\n\tPORT144_FN2___2 = 1636,\n\tPORT145_FN2___2 = 1637,\n\tPORT146_FN2___2 = 1638,\n\tPORT147_FN2___2 = 1639,\n\tPORT148_FN2___2 = 1640,\n\tPORT149_FN2___2 = 1641,\n\tPORT150_FN2___2 = 1642,\n\tPORT151_FN2___2 = 1643,\n\tPORT152_FN2___2 = 1644,\n\tPORT153_FN2___2 = 1645,\n\tPORT154_FN2___2 = 1646,\n\tPORT155_FN2___2 = 1647,\n\tPORT156_FN2___2 = 1648,\n\tPORT157_FN2___2 = 1649,\n\tPORT158_FN2___2 = 1650,\n\tPORT159_FN2___2 = 1651,\n\tPORT160_FN2___3 = 1652,\n\tPORT161_FN2___3 = 1653,\n\tPORT162_FN2___3 = 1654,\n\tPORT163_FN2___3 = 1655,\n\tPORT164_FN2___3 = 1656,\n\tPORT165_FN2___2 = 1657,\n\tPORT166_FN2___2 = 1658,\n\tPORT167_FN2___2 = 1659,\n\tPORT168_FN2___2 = 1660,\n\tPORT169_FN2___2 = 1661,\n\tPORT170_FN2___2 = 1662,\n\tPORT171_FN2___2 = 1663,\n\tPORT172_FN2___2 = 1664,\n\tPORT173_FN2___2 = 1665,\n\tPORT174_FN2___2 = 1666,\n\tPORT175_FN2___2 = 1667,\n\tPORT176_FN2___2 = 1668,\n\tPORT177_FN2___2 = 1669,\n\tPORT178_FN2___2 = 1670,\n\tPORT179_FN2 = 1671,\n\tPORT180_FN2 = 1672,\n\tPORT181_FN2 = 1673,\n\tPORT182_FN2 = 1674,\n\tPORT183_FN2 = 1675,\n\tPORT184_FN2 = 1676,\n\tPORT185_FN2 = 1677,\n\tPORT186_FN2 = 1678,\n\tPORT187_FN2 = 1679,\n\tPORT188_FN2 = 1680,\n\tPORT189_FN2 = 1681,\n\tPORT190_FN2 = 1682,\n\tPORT191_FN2 = 1683,\n\tPORT192_FN2___3 = 1684,\n\tPORT193_FN2___3 = 1685,\n\tPORT194_FN2___3 = 1686,\n\tPORT195_FN2___3 = 1687,\n\tPORT196_FN2___3 = 1688,\n\tPORT197_FN2___3 = 1689,\n\tPORT198_FN2___3 = 1690,\n\tPORT199_FN2___3 = 1691,\n\tPORT200_FN2___3 = 1692,\n\tPORT201_FN2___3 = 1693,\n\tPORT202_FN2___3 = 1694,\n\tPORT203_FN2___3 = 1695,\n\tPORT204_FN2___3 = 1696,\n\tPORT205_FN2___3 = 1697,\n\tPORT206_FN2___3 = 1698,\n\tPORT207_FN2___3 = 1699,\n\tPORT208_FN2___3 = 1700,\n\tPORT209_FN2___3 = 1701,\n\tPORT210_FN2___3 = 1702,\n\tPORT211_FN2___3 = 1703,\n\tPORT0_FN3___3 = 1704,\n\tPORT1_FN3___3 = 1705,\n\tPORT2_FN3___3 = 1706,\n\tPORT3_FN3___3 = 1707,\n\tPORT4_FN3___3 = 1708,\n\tPORT5_FN3___3 = 1709,\n\tPORT6_FN3___3 = 1710,\n\tPORT7_FN3___3 = 1711,\n\tPORT8_FN3___3 = 1712,\n\tPORT9_FN3___3 = 1713,\n\tPORT10_FN3___3 = 1714,\n\tPORT11_FN3___3 = 1715,\n\tPORT12_FN3___3 = 1716,\n\tPORT13_FN3___3 = 1717,\n\tPORT14_FN3___3 = 1718,\n\tPORT15_FN3___3 = 1719,\n\tPORT16_FN3___3 = 1720,\n\tPORT17_FN3___3 = 1721,\n\tPORT18_FN3___3 = 1722,\n\tPORT19_FN3___3 = 1723,\n\tPORT20_FN3___3 = 1724,\n\tPORT21_FN3___3 = 1725,\n\tPORT22_FN3___3 = 1726,\n\tPORT23_FN3___3 = 1727,\n\tPORT24_FN3___3 = 1728,\n\tPORT25_FN3___3 = 1729,\n\tPORT26_FN3___3 = 1730,\n\tPORT27_FN3___3 = 1731,\n\tPORT28_FN3___3 = 1732,\n\tPORT29_FN3___3 = 1733,\n\tPORT30_FN3___3 = 1734,\n\tPORT31_FN3___2 = 1735,\n\tPORT32_FN3___3 = 1736,\n\tPORT33_FN3___3 = 1737,\n\tPORT34_FN3___3 = 1738,\n\tPORT35_FN3___3 = 1739,\n\tPORT36_FN3___3 = 1740,\n\tPORT37_FN3___3 = 1741,\n\tPORT38_FN3___3 = 1742,\n\tPORT39_FN3___3 = 1743,\n\tPORT40_FN3___3 = 1744,\n\tPORT41_FN3___2 = 1745,\n\tPORT42_FN3___2 = 1746,\n\tPORT43_FN3___2 = 1747,\n\tPORT44_FN3___2 = 1748,\n\tPORT45_FN3___2 = 1749,\n\tPORT46_FN3___2 = 1750,\n\tPORT47_FN3___2 = 1751,\n\tPORT48_FN3___2 = 1752,\n\tPORT49_FN3___2 = 1753,\n\tPORT50_FN3___2 = 1754,\n\tPORT51_FN3___2 = 1755,\n\tPORT52_FN3___2 = 1756,\n\tPORT53_FN3___2 = 1757,\n\tPORT54_FN3___2 = 1758,\n\tPORT55_FN3___2 = 1759,\n\tPORT56_FN3___2 = 1760,\n\tPORT57_FN3___2 = 1761,\n\tPORT58_FN3___2 = 1762,\n\tPORT59_FN3___2 = 1763,\n\tPORT60_FN3___2 = 1764,\n\tPORT61_FN3___2 = 1765,\n\tPORT62_FN3___2 = 1766,\n\tPORT63_FN3___2 = 1767,\n\tPORT64_FN3___3 = 1768,\n\tPORT65_FN3___3 = 1769,\n\tPORT66_FN3___3 = 1770,\n\tPORT67_FN3___3 = 1771,\n\tPORT68_FN3___3 = 1772,\n\tPORT69_FN3___3 = 1773,\n\tPORT70_FN3___3 = 1774,\n\tPORT71_FN3___3 = 1775,\n\tPORT72_FN3___3 = 1776,\n\tPORT73_FN3___3 = 1777,\n\tPORT74_FN3___3 = 1778,\n\tPORT75_FN3___3 = 1779,\n\tPORT76_FN3___3 = 1780,\n\tPORT77_FN3___3 = 1781,\n\tPORT78_FN3___3 = 1782,\n\tPORT79_FN3___3 = 1783,\n\tPORT80_FN3___3 = 1784,\n\tPORT81_FN3___3 = 1785,\n\tPORT82_FN3___3 = 1786,\n\tPORT83_FN3___3 = 1787,\n\tPORT84_FN3___3 = 1788,\n\tPORT85_FN3___3 = 1789,\n\tPORT86_FN3___2 = 1790,\n\tPORT87_FN3___2 = 1791,\n\tPORT88_FN3___2 = 1792,\n\tPORT89_FN3___2 = 1793,\n\tPORT90_FN3___2 = 1794,\n\tPORT91_FN3___2 = 1795,\n\tPORT92_FN3___2 = 1796,\n\tPORT93_FN3___2 = 1797,\n\tPORT94_FN3___2 = 1798,\n\tPORT95_FN3___2 = 1799,\n\tPORT96_FN3___3 = 1800,\n\tPORT97_FN3___3 = 1801,\n\tPORT98_FN3___3 = 1802,\n\tPORT99_FN3___3 = 1803,\n\tPORT100_FN3___3 = 1804,\n\tPORT101_FN3___3 = 1805,\n\tPORT102_FN3___3 = 1806,\n\tPORT103_FN3___3 = 1807,\n\tPORT104_FN3___3 = 1808,\n\tPORT105_FN3___3 = 1809,\n\tPORT106_FN3___3 = 1810,\n\tPORT107_FN3___3 = 1811,\n\tPORT108_FN3___3 = 1812,\n\tPORT109_FN3___3 = 1813,\n\tPORT110_FN3___3 = 1814,\n\tPORT111_FN3___3 = 1815,\n\tPORT112_FN3___3 = 1816,\n\tPORT113_FN3___3 = 1817,\n\tPORT114_FN3___3 = 1818,\n\tPORT115_FN3___3 = 1819,\n\tPORT116_FN3___3 = 1820,\n\tPORT117_FN3___3 = 1821,\n\tPORT118_FN3___3 = 1822,\n\tPORT119_FN3___2 = 1823,\n\tPORT120_FN3___2 = 1824,\n\tPORT121_FN3___2 = 1825,\n\tPORT122_FN3___2 = 1826,\n\tPORT123_FN3___2 = 1827,\n\tPORT124_FN3___2 = 1828,\n\tPORT125_FN3___2 = 1829,\n\tPORT126_FN3___2 = 1830,\n\tPORT127_FN3 = 1831,\n\tPORT128_FN3___3 = 1832,\n\tPORT129_FN3___3 = 1833,\n\tPORT130_FN3___3 = 1834,\n\tPORT131_FN3___3 = 1835,\n\tPORT132_FN3___3 = 1836,\n\tPORT133_FN3___3 = 1837,\n\tPORT134_FN3___3 = 1838,\n\tPORT135_FN3___2 = 1839,\n\tPORT136_FN3___2 = 1840,\n\tPORT137_FN3___2 = 1841,\n\tPORT138_FN3___2 = 1842,\n\tPORT139_FN3___2 = 1843,\n\tPORT140_FN3___2 = 1844,\n\tPORT141_FN3___2 = 1845,\n\tPORT142_FN3___2 = 1846,\n\tPORT143_FN3___2 = 1847,\n\tPORT144_FN3___2 = 1848,\n\tPORT145_FN3___2 = 1849,\n\tPORT146_FN3___2 = 1850,\n\tPORT147_FN3___2 = 1851,\n\tPORT148_FN3___2 = 1852,\n\tPORT149_FN3___2 = 1853,\n\tPORT150_FN3___2 = 1854,\n\tPORT151_FN3___2 = 1855,\n\tPORT152_FN3___2 = 1856,\n\tPORT153_FN3___2 = 1857,\n\tPORT154_FN3___2 = 1858,\n\tPORT155_FN3___2 = 1859,\n\tPORT156_FN3___2 = 1860,\n\tPORT157_FN3___2 = 1861,\n\tPORT158_FN3___2 = 1862,\n\tPORT159_FN3___2 = 1863,\n\tPORT160_FN3___3 = 1864,\n\tPORT161_FN3___3 = 1865,\n\tPORT162_FN3___3 = 1866,\n\tPORT163_FN3___3 = 1867,\n\tPORT164_FN3___3 = 1868,\n\tPORT165_FN3___2 = 1869,\n\tPORT166_FN3___2 = 1870,\n\tPORT167_FN3___2 = 1871,\n\tPORT168_FN3___2 = 1872,\n\tPORT169_FN3___2 = 1873,\n\tPORT170_FN3___2 = 1874,\n\tPORT171_FN3___2 = 1875,\n\tPORT172_FN3___2 = 1876,\n\tPORT173_FN3___2 = 1877,\n\tPORT174_FN3___2 = 1878,\n\tPORT175_FN3___2 = 1879,\n\tPORT176_FN3___2 = 1880,\n\tPORT177_FN3___2 = 1881,\n\tPORT178_FN3___2 = 1882,\n\tPORT179_FN3 = 1883,\n\tPORT180_FN3 = 1884,\n\tPORT181_FN3 = 1885,\n\tPORT182_FN3 = 1886,\n\tPORT183_FN3 = 1887,\n\tPORT184_FN3 = 1888,\n\tPORT185_FN3 = 1889,\n\tPORT186_FN3 = 1890,\n\tPORT187_FN3 = 1891,\n\tPORT188_FN3 = 1892,\n\tPORT189_FN3 = 1893,\n\tPORT190_FN3 = 1894,\n\tPORT191_FN3 = 1895,\n\tPORT192_FN3___3 = 1896,\n\tPORT193_FN3___3 = 1897,\n\tPORT194_FN3___3 = 1898,\n\tPORT195_FN3___3 = 1899,\n\tPORT196_FN3___3 = 1900,\n\tPORT197_FN3___3 = 1901,\n\tPORT198_FN3___3 = 1902,\n\tPORT199_FN3___3 = 1903,\n\tPORT200_FN3___3 = 1904,\n\tPORT201_FN3___3 = 1905,\n\tPORT202_FN3___3 = 1906,\n\tPORT203_FN3___3 = 1907,\n\tPORT204_FN3___3 = 1908,\n\tPORT205_FN3___3 = 1909,\n\tPORT206_FN3___3 = 1910,\n\tPORT207_FN3___3 = 1911,\n\tPORT208_FN3___3 = 1912,\n\tPORT209_FN3___3 = 1913,\n\tPORT210_FN3___3 = 1914,\n\tPORT211_FN3___3 = 1915,\n\tPORT0_FN4___3 = 1916,\n\tPORT1_FN4___3 = 1917,\n\tPORT2_FN4___3 = 1918,\n\tPORT3_FN4___3 = 1919,\n\tPORT4_FN4___3 = 1920,\n\tPORT5_FN4___3 = 1921,\n\tPORT6_FN4___3 = 1922,\n\tPORT7_FN4___3 = 1923,\n\tPORT8_FN4___3 = 1924,\n\tPORT9_FN4___3 = 1925,\n\tPORT10_FN4___3 = 1926,\n\tPORT11_FN4___3 = 1927,\n\tPORT12_FN4___3 = 1928,\n\tPORT13_FN4___3 = 1929,\n\tPORT14_FN4___3 = 1930,\n\tPORT15_FN4___3 = 1931,\n\tPORT16_FN4___3 = 1932,\n\tPORT17_FN4___3 = 1933,\n\tPORT18_FN4___3 = 1934,\n\tPORT19_FN4___3 = 1935,\n\tPORT20_FN4___3 = 1936,\n\tPORT21_FN4___3 = 1937,\n\tPORT22_FN4___3 = 1938,\n\tPORT23_FN4___3 = 1939,\n\tPORT24_FN4___3 = 1940,\n\tPORT25_FN4___3 = 1941,\n\tPORT26_FN4___3 = 1942,\n\tPORT27_FN4___3 = 1943,\n\tPORT28_FN4___3 = 1944,\n\tPORT29_FN4___3 = 1945,\n\tPORT30_FN4___3 = 1946,\n\tPORT31_FN4___2 = 1947,\n\tPORT32_FN4___3 = 1948,\n\tPORT33_FN4___3 = 1949,\n\tPORT34_FN4___3 = 1950,\n\tPORT35_FN4___3 = 1951,\n\tPORT36_FN4___3 = 1952,\n\tPORT37_FN4___3 = 1953,\n\tPORT38_FN4___3 = 1954,\n\tPORT39_FN4___3 = 1955,\n\tPORT40_FN4___3 = 1956,\n\tPORT41_FN4___2 = 1957,\n\tPORT42_FN4___2 = 1958,\n\tPORT43_FN4___2 = 1959,\n\tPORT44_FN4___2 = 1960,\n\tPORT45_FN4___2 = 1961,\n\tPORT46_FN4___2 = 1962,\n\tPORT47_FN4___2 = 1963,\n\tPORT48_FN4___2 = 1964,\n\tPORT49_FN4___2 = 1965,\n\tPORT50_FN4___2 = 1966,\n\tPORT51_FN4___2 = 1967,\n\tPORT52_FN4___2 = 1968,\n\tPORT53_FN4___2 = 1969,\n\tPORT54_FN4___2 = 1970,\n\tPORT55_FN4___2 = 1971,\n\tPORT56_FN4___2 = 1972,\n\tPORT57_FN4___2 = 1973,\n\tPORT58_FN4___2 = 1974,\n\tPORT59_FN4___2 = 1975,\n\tPORT60_FN4___2 = 1976,\n\tPORT61_FN4___2 = 1977,\n\tPORT62_FN4___2 = 1978,\n\tPORT63_FN4___2 = 1979,\n\tPORT64_FN4___3 = 1980,\n\tPORT65_FN4___3 = 1981,\n\tPORT66_FN4___3 = 1982,\n\tPORT67_FN4___3 = 1983,\n\tPORT68_FN4___3 = 1984,\n\tPORT69_FN4___3 = 1985,\n\tPORT70_FN4___3 = 1986,\n\tPORT71_FN4___3 = 1987,\n\tPORT72_FN4___3 = 1988,\n\tPORT73_FN4___3 = 1989,\n\tPORT74_FN4___3 = 1990,\n\tPORT75_FN4___3 = 1991,\n\tPORT76_FN4___3 = 1992,\n\tPORT77_FN4___3 = 1993,\n\tPORT78_FN4___3 = 1994,\n\tPORT79_FN4___3 = 1995,\n\tPORT80_FN4___3 = 1996,\n\tPORT81_FN4___3 = 1997,\n\tPORT82_FN4___3 = 1998,\n\tPORT83_FN4___3 = 1999,\n\tPORT84_FN4___3 = 2000,\n\tPORT85_FN4___3 = 2001,\n\tPORT86_FN4___2 = 2002,\n\tPORT87_FN4___2 = 2003,\n\tPORT88_FN4___2 = 2004,\n\tPORT89_FN4___2 = 2005,\n\tPORT90_FN4___2 = 2006,\n\tPORT91_FN4___2 = 2007,\n\tPORT92_FN4___2 = 2008,\n\tPORT93_FN4___2 = 2009,\n\tPORT94_FN4___2 = 2010,\n\tPORT95_FN4___2 = 2011,\n\tPORT96_FN4___3 = 2012,\n\tPORT97_FN4___3 = 2013,\n\tPORT98_FN4___3 = 2014,\n\tPORT99_FN4___3 = 2015,\n\tPORT100_FN4___3 = 2016,\n\tPORT101_FN4___3 = 2017,\n\tPORT102_FN4___3 = 2018,\n\tPORT103_FN4___3 = 2019,\n\tPORT104_FN4___3 = 2020,\n\tPORT105_FN4___3 = 2021,\n\tPORT106_FN4___3 = 2022,\n\tPORT107_FN4___3 = 2023,\n\tPORT108_FN4___3 = 2024,\n\tPORT109_FN4___3 = 2025,\n\tPORT110_FN4___3 = 2026,\n\tPORT111_FN4___3 = 2027,\n\tPORT112_FN4___3 = 2028,\n\tPORT113_FN4___3 = 2029,\n\tPORT114_FN4___3 = 2030,\n\tPORT115_FN4___3 = 2031,\n\tPORT116_FN4___3 = 2032,\n\tPORT117_FN4___3 = 2033,\n\tPORT118_FN4___3 = 2034,\n\tPORT119_FN4___2 = 2035,\n\tPORT120_FN4___2 = 2036,\n\tPORT121_FN4___2 = 2037,\n\tPORT122_FN4___2 = 2038,\n\tPORT123_FN4___2 = 2039,\n\tPORT124_FN4___2 = 2040,\n\tPORT125_FN4___2 = 2041,\n\tPORT126_FN4___2 = 2042,\n\tPORT127_FN4 = 2043,\n\tPORT128_FN4___3 = 2044,\n\tPORT129_FN4___3 = 2045,\n\tPORT130_FN4___3 = 2046,\n\tPORT131_FN4___3 = 2047,\n\tPORT132_FN4___3 = 2048,\n\tPORT133_FN4___3 = 2049,\n\tPORT134_FN4___3 = 2050,\n\tPORT135_FN4___2 = 2051,\n\tPORT136_FN4___2 = 2052,\n\tPORT137_FN4___2 = 2053,\n\tPORT138_FN4___2 = 2054,\n\tPORT139_FN4___2 = 2055,\n\tPORT140_FN4___2 = 2056,\n\tPORT141_FN4___2 = 2057,\n\tPORT142_FN4___2 = 2058,\n\tPORT143_FN4___2 = 2059,\n\tPORT144_FN4___2 = 2060,\n\tPORT145_FN4___2 = 2061,\n\tPORT146_FN4___2 = 2062,\n\tPORT147_FN4___2 = 2063,\n\tPORT148_FN4___2 = 2064,\n\tPORT149_FN4___2 = 2065,\n\tPORT150_FN4___2 = 2066,\n\tPORT151_FN4___2 = 2067,\n\tPORT152_FN4___2 = 2068,\n\tPORT153_FN4___2 = 2069,\n\tPORT154_FN4___2 = 2070,\n\tPORT155_FN4___2 = 2071,\n\tPORT156_FN4___2 = 2072,\n\tPORT157_FN4___2 = 2073,\n\tPORT158_FN4___2 = 2074,\n\tPORT159_FN4___2 = 2075,\n\tPORT160_FN4___3 = 2076,\n\tPORT161_FN4___3 = 2077,\n\tPORT162_FN4___3 = 2078,\n\tPORT163_FN4___3 = 2079,\n\tPORT164_FN4___3 = 2080,\n\tPORT165_FN4___2 = 2081,\n\tPORT166_FN4___2 = 2082,\n\tPORT167_FN4___2 = 2083,\n\tPORT168_FN4___2 = 2084,\n\tPORT169_FN4___2 = 2085,\n\tPORT170_FN4___2 = 2086,\n\tPORT171_FN4___2 = 2087,\n\tPORT172_FN4___2 = 2088,\n\tPORT173_FN4___2 = 2089,\n\tPORT174_FN4___2 = 2090,\n\tPORT175_FN4___2 = 2091,\n\tPORT176_FN4___2 = 2092,\n\tPORT177_FN4___2 = 2093,\n\tPORT178_FN4___2 = 2094,\n\tPORT179_FN4 = 2095,\n\tPORT180_FN4 = 2096,\n\tPORT181_FN4 = 2097,\n\tPORT182_FN4 = 2098,\n\tPORT183_FN4 = 2099,\n\tPORT184_FN4 = 2100,\n\tPORT185_FN4 = 2101,\n\tPORT186_FN4 = 2102,\n\tPORT187_FN4 = 2103,\n\tPORT188_FN4 = 2104,\n\tPORT189_FN4 = 2105,\n\tPORT190_FN4 = 2106,\n\tPORT191_FN4 = 2107,\n\tPORT192_FN4___3 = 2108,\n\tPORT193_FN4___3 = 2109,\n\tPORT194_FN4___3 = 2110,\n\tPORT195_FN4___3 = 2111,\n\tPORT196_FN4___3 = 2112,\n\tPORT197_FN4___3 = 2113,\n\tPORT198_FN4___3 = 2114,\n\tPORT199_FN4___3 = 2115,\n\tPORT200_FN4___3 = 2116,\n\tPORT201_FN4___3 = 2117,\n\tPORT202_FN4___3 = 2118,\n\tPORT203_FN4___3 = 2119,\n\tPORT204_FN4___3 = 2120,\n\tPORT205_FN4___3 = 2121,\n\tPORT206_FN4___3 = 2122,\n\tPORT207_FN4___3 = 2123,\n\tPORT208_FN4___3 = 2124,\n\tPORT209_FN4___3 = 2125,\n\tPORT210_FN4___3 = 2126,\n\tPORT211_FN4___3 = 2127,\n\tPORT0_FN5___3 = 2128,\n\tPORT1_FN5___3 = 2129,\n\tPORT2_FN5___3 = 2130,\n\tPORT3_FN5___3 = 2131,\n\tPORT4_FN5___3 = 2132,\n\tPORT5_FN5___3 = 2133,\n\tPORT6_FN5___3 = 2134,\n\tPORT7_FN5___3 = 2135,\n\tPORT8_FN5___3 = 2136,\n\tPORT9_FN5___3 = 2137,\n\tPORT10_FN5___3 = 2138,\n\tPORT11_FN5___3 = 2139,\n\tPORT12_FN5___3 = 2140,\n\tPORT13_FN5___3 = 2141,\n\tPORT14_FN5___3 = 2142,\n\tPORT15_FN5___3 = 2143,\n\tPORT16_FN5___3 = 2144,\n\tPORT17_FN5___3 = 2145,\n\tPORT18_FN5___3 = 2146,\n\tPORT19_FN5___3 = 2147,\n\tPORT20_FN5___3 = 2148,\n\tPORT21_FN5___3 = 2149,\n\tPORT22_FN5___3 = 2150,\n\tPORT23_FN5___3 = 2151,\n\tPORT24_FN5___3 = 2152,\n\tPORT25_FN5___3 = 2153,\n\tPORT26_FN5___3 = 2154,\n\tPORT27_FN5___3 = 2155,\n\tPORT28_FN5___3 = 2156,\n\tPORT29_FN5___3 = 2157,\n\tPORT30_FN5___3 = 2158,\n\tPORT31_FN5___2 = 2159,\n\tPORT32_FN5___3 = 2160,\n\tPORT33_FN5___3 = 2161,\n\tPORT34_FN5___3 = 2162,\n\tPORT35_FN5___3 = 2163,\n\tPORT36_FN5___3 = 2164,\n\tPORT37_FN5___3 = 2165,\n\tPORT38_FN5___3 = 2166,\n\tPORT39_FN5___3 = 2167,\n\tPORT40_FN5___3 = 2168,\n\tPORT41_FN5___2 = 2169,\n\tPORT42_FN5___2 = 2170,\n\tPORT43_FN5___2 = 2171,\n\tPORT44_FN5___2 = 2172,\n\tPORT45_FN5___2 = 2173,\n\tPORT46_FN5___2 = 2174,\n\tPORT47_FN5___2 = 2175,\n\tPORT48_FN5___2 = 2176,\n\tPORT49_FN5___2 = 2177,\n\tPORT50_FN5___2 = 2178,\n\tPORT51_FN5___2 = 2179,\n\tPORT52_FN5___2 = 2180,\n\tPORT53_FN5___2 = 2181,\n\tPORT54_FN5___2 = 2182,\n\tPORT55_FN5___2 = 2183,\n\tPORT56_FN5___2 = 2184,\n\tPORT57_FN5___2 = 2185,\n\tPORT58_FN5___2 = 2186,\n\tPORT59_FN5___2 = 2187,\n\tPORT60_FN5___2 = 2188,\n\tPORT61_FN5___2 = 2189,\n\tPORT62_FN5___2 = 2190,\n\tPORT63_FN5___2 = 2191,\n\tPORT64_FN5___3 = 2192,\n\tPORT65_FN5___3 = 2193,\n\tPORT66_FN5___3 = 2194,\n\tPORT67_FN5___3 = 2195,\n\tPORT68_FN5___3 = 2196,\n\tPORT69_FN5___3 = 2197,\n\tPORT70_FN5___3 = 2198,\n\tPORT71_FN5___3 = 2199,\n\tPORT72_FN5___3 = 2200,\n\tPORT73_FN5___3 = 2201,\n\tPORT74_FN5___3 = 2202,\n\tPORT75_FN5___3 = 2203,\n\tPORT76_FN5___3 = 2204,\n\tPORT77_FN5___3 = 2205,\n\tPORT78_FN5___3 = 2206,\n\tPORT79_FN5___3 = 2207,\n\tPORT80_FN5___3 = 2208,\n\tPORT81_FN5___3 = 2209,\n\tPORT82_FN5___3 = 2210,\n\tPORT83_FN5___3 = 2211,\n\tPORT84_FN5___3 = 2212,\n\tPORT85_FN5___3 = 2213,\n\tPORT86_FN5___2 = 2214,\n\tPORT87_FN5___2 = 2215,\n\tPORT88_FN5___2 = 2216,\n\tPORT89_FN5___2 = 2217,\n\tPORT90_FN5___2 = 2218,\n\tPORT91_FN5___2 = 2219,\n\tPORT92_FN5___2 = 2220,\n\tPORT93_FN5___2 = 2221,\n\tPORT94_FN5___2 = 2222,\n\tPORT95_FN5___2 = 2223,\n\tPORT96_FN5___3 = 2224,\n\tPORT97_FN5___3 = 2225,\n\tPORT98_FN5___3 = 2226,\n\tPORT99_FN5___3 = 2227,\n\tPORT100_FN5___3 = 2228,\n\tPORT101_FN5___3 = 2229,\n\tPORT102_FN5___3 = 2230,\n\tPORT103_FN5___3 = 2231,\n\tPORT104_FN5___3 = 2232,\n\tPORT105_FN5___3 = 2233,\n\tPORT106_FN5___3 = 2234,\n\tPORT107_FN5___3 = 2235,\n\tPORT108_FN5___3 = 2236,\n\tPORT109_FN5___3 = 2237,\n\tPORT110_FN5___3 = 2238,\n\tPORT111_FN5___3 = 2239,\n\tPORT112_FN5___3 = 2240,\n\tPORT113_FN5___3 = 2241,\n\tPORT114_FN5___3 = 2242,\n\tPORT115_FN5___3 = 2243,\n\tPORT116_FN5___3 = 2244,\n\tPORT117_FN5___3 = 2245,\n\tPORT118_FN5___3 = 2246,\n\tPORT119_FN5___2 = 2247,\n\tPORT120_FN5___2 = 2248,\n\tPORT121_FN5___2 = 2249,\n\tPORT122_FN5___2 = 2250,\n\tPORT123_FN5___2 = 2251,\n\tPORT124_FN5___2 = 2252,\n\tPORT125_FN5___2 = 2253,\n\tPORT126_FN5___2 = 2254,\n\tPORT127_FN5 = 2255,\n\tPORT128_FN5___3 = 2256,\n\tPORT129_FN5___3 = 2257,\n\tPORT130_FN5___3 = 2258,\n\tPORT131_FN5___3 = 2259,\n\tPORT132_FN5___3 = 2260,\n\tPORT133_FN5___3 = 2261,\n\tPORT134_FN5___3 = 2262,\n\tPORT135_FN5___2 = 2263,\n\tPORT136_FN5___2 = 2264,\n\tPORT137_FN5___2 = 2265,\n\tPORT138_FN5___2 = 2266,\n\tPORT139_FN5___2 = 2267,\n\tPORT140_FN5___2 = 2268,\n\tPORT141_FN5___2 = 2269,\n\tPORT142_FN5___2 = 2270,\n\tPORT143_FN5___2 = 2271,\n\tPORT144_FN5___2 = 2272,\n\tPORT145_FN5___2 = 2273,\n\tPORT146_FN5___2 = 2274,\n\tPORT147_FN5___2 = 2275,\n\tPORT148_FN5___2 = 2276,\n\tPORT149_FN5___2 = 2277,\n\tPORT150_FN5___2 = 2278,\n\tPORT151_FN5___2 = 2279,\n\tPORT152_FN5___2 = 2280,\n\tPORT153_FN5___2 = 2281,\n\tPORT154_FN5___2 = 2282,\n\tPORT155_FN5___2 = 2283,\n\tPORT156_FN5___2 = 2284,\n\tPORT157_FN5___2 = 2285,\n\tPORT158_FN5___2 = 2286,\n\tPORT159_FN5___2 = 2287,\n\tPORT160_FN5___3 = 2288,\n\tPORT161_FN5___3 = 2289,\n\tPORT162_FN5___3 = 2290,\n\tPORT163_FN5___3 = 2291,\n\tPORT164_FN5___3 = 2292,\n\tPORT165_FN5___2 = 2293,\n\tPORT166_FN5___2 = 2294,\n\tPORT167_FN5___2 = 2295,\n\tPORT168_FN5___2 = 2296,\n\tPORT169_FN5___2 = 2297,\n\tPORT170_FN5___2 = 2298,\n\tPORT171_FN5___2 = 2299,\n\tPORT172_FN5___2 = 2300,\n\tPORT173_FN5___2 = 2301,\n\tPORT174_FN5___2 = 2302,\n\tPORT175_FN5___2 = 2303,\n\tPORT176_FN5___2 = 2304,\n\tPORT177_FN5___2 = 2305,\n\tPORT178_FN5___2 = 2306,\n\tPORT179_FN5 = 2307,\n\tPORT180_FN5 = 2308,\n\tPORT181_FN5 = 2309,\n\tPORT182_FN5 = 2310,\n\tPORT183_FN5 = 2311,\n\tPORT184_FN5 = 2312,\n\tPORT185_FN5 = 2313,\n\tPORT186_FN5 = 2314,\n\tPORT187_FN5 = 2315,\n\tPORT188_FN5 = 2316,\n\tPORT189_FN5 = 2317,\n\tPORT190_FN5 = 2318,\n\tPORT191_FN5 = 2319,\n\tPORT192_FN5___3 = 2320,\n\tPORT193_FN5___3 = 2321,\n\tPORT194_FN5___3 = 2322,\n\tPORT195_FN5___3 = 2323,\n\tPORT196_FN5___3 = 2324,\n\tPORT197_FN5___3 = 2325,\n\tPORT198_FN5___3 = 2326,\n\tPORT199_FN5___3 = 2327,\n\tPORT200_FN5___3 = 2328,\n\tPORT201_FN5___3 = 2329,\n\tPORT202_FN5___3 = 2330,\n\tPORT203_FN5___3 = 2331,\n\tPORT204_FN5___3 = 2332,\n\tPORT205_FN5___3 = 2333,\n\tPORT206_FN5___3 = 2334,\n\tPORT207_FN5___3 = 2335,\n\tPORT208_FN5___3 = 2336,\n\tPORT209_FN5___3 = 2337,\n\tPORT210_FN5___3 = 2338,\n\tPORT211_FN5___3 = 2339,\n\tPORT0_FN6___3 = 2340,\n\tPORT1_FN6___3 = 2341,\n\tPORT2_FN6___3 = 2342,\n\tPORT3_FN6___3 = 2343,\n\tPORT4_FN6___3 = 2344,\n\tPORT5_FN6___3 = 2345,\n\tPORT6_FN6___3 = 2346,\n\tPORT7_FN6___3 = 2347,\n\tPORT8_FN6___3 = 2348,\n\tPORT9_FN6___3 = 2349,\n\tPORT10_FN6___3 = 2350,\n\tPORT11_FN6___3 = 2351,\n\tPORT12_FN6___3 = 2352,\n\tPORT13_FN6___3 = 2353,\n\tPORT14_FN6___3 = 2354,\n\tPORT15_FN6___3 = 2355,\n\tPORT16_FN6___3 = 2356,\n\tPORT17_FN6___3 = 2357,\n\tPORT18_FN6___3 = 2358,\n\tPORT19_FN6___3 = 2359,\n\tPORT20_FN6___3 = 2360,\n\tPORT21_FN6___3 = 2361,\n\tPORT22_FN6___3 = 2362,\n\tPORT23_FN6___3 = 2363,\n\tPORT24_FN6___3 = 2364,\n\tPORT25_FN6___3 = 2365,\n\tPORT26_FN6___3 = 2366,\n\tPORT27_FN6___3 = 2367,\n\tPORT28_FN6___3 = 2368,\n\tPORT29_FN6___3 = 2369,\n\tPORT30_FN6___3 = 2370,\n\tPORT31_FN6___2 = 2371,\n\tPORT32_FN6___3 = 2372,\n\tPORT33_FN6___3 = 2373,\n\tPORT34_FN6___3 = 2374,\n\tPORT35_FN6___3 = 2375,\n\tPORT36_FN6___3 = 2376,\n\tPORT37_FN6___3 = 2377,\n\tPORT38_FN6___3 = 2378,\n\tPORT39_FN6___3 = 2379,\n\tPORT40_FN6___3 = 2380,\n\tPORT41_FN6___2 = 2381,\n\tPORT42_FN6___2 = 2382,\n\tPORT43_FN6___2 = 2383,\n\tPORT44_FN6___2 = 2384,\n\tPORT45_FN6___2 = 2385,\n\tPORT46_FN6___2 = 2386,\n\tPORT47_FN6___2 = 2387,\n\tPORT48_FN6___2 = 2388,\n\tPORT49_FN6___2 = 2389,\n\tPORT50_FN6___2 = 2390,\n\tPORT51_FN6___2 = 2391,\n\tPORT52_FN6___2 = 2392,\n\tPORT53_FN6___2 = 2393,\n\tPORT54_FN6___2 = 2394,\n\tPORT55_FN6___2 = 2395,\n\tPORT56_FN6___2 = 2396,\n\tPORT57_FN6___2 = 2397,\n\tPORT58_FN6___2 = 2398,\n\tPORT59_FN6___2 = 2399,\n\tPORT60_FN6___2 = 2400,\n\tPORT61_FN6___2 = 2401,\n\tPORT62_FN6___2 = 2402,\n\tPORT63_FN6___2 = 2403,\n\tPORT64_FN6___3 = 2404,\n\tPORT65_FN6___3 = 2405,\n\tPORT66_FN6___3 = 2406,\n\tPORT67_FN6___3 = 2407,\n\tPORT68_FN6___3 = 2408,\n\tPORT69_FN6___3 = 2409,\n\tPORT70_FN6___3 = 2410,\n\tPORT71_FN6___3 = 2411,\n\tPORT72_FN6___3 = 2412,\n\tPORT73_FN6___3 = 2413,\n\tPORT74_FN6___3 = 2414,\n\tPORT75_FN6___3 = 2415,\n\tPORT76_FN6___3 = 2416,\n\tPORT77_FN6___3 = 2417,\n\tPORT78_FN6___3 = 2418,\n\tPORT79_FN6___3 = 2419,\n\tPORT80_FN6___3 = 2420,\n\tPORT81_FN6___3 = 2421,\n\tPORT82_FN6___3 = 2422,\n\tPORT83_FN6___3 = 2423,\n\tPORT84_FN6___3 = 2424,\n\tPORT85_FN6___3 = 2425,\n\tPORT86_FN6___2 = 2426,\n\tPORT87_FN6___2 = 2427,\n\tPORT88_FN6___2 = 2428,\n\tPORT89_FN6___2 = 2429,\n\tPORT90_FN6___2 = 2430,\n\tPORT91_FN6___2 = 2431,\n\tPORT92_FN6___2 = 2432,\n\tPORT93_FN6___2 = 2433,\n\tPORT94_FN6___2 = 2434,\n\tPORT95_FN6___2 = 2435,\n\tPORT96_FN6___3 = 2436,\n\tPORT97_FN6___3 = 2437,\n\tPORT98_FN6___3 = 2438,\n\tPORT99_FN6___3 = 2439,\n\tPORT100_FN6___3 = 2440,\n\tPORT101_FN6___3 = 2441,\n\tPORT102_FN6___3 = 2442,\n\tPORT103_FN6___3 = 2443,\n\tPORT104_FN6___3 = 2444,\n\tPORT105_FN6___3 = 2445,\n\tPORT106_FN6___3 = 2446,\n\tPORT107_FN6___3 = 2447,\n\tPORT108_FN6___3 = 2448,\n\tPORT109_FN6___3 = 2449,\n\tPORT110_FN6___3 = 2450,\n\tPORT111_FN6___3 = 2451,\n\tPORT112_FN6___3 = 2452,\n\tPORT113_FN6___3 = 2453,\n\tPORT114_FN6___3 = 2454,\n\tPORT115_FN6___3 = 2455,\n\tPORT116_FN6___3 = 2456,\n\tPORT117_FN6___3 = 2457,\n\tPORT118_FN6___3 = 2458,\n\tPORT119_FN6___2 = 2459,\n\tPORT120_FN6___2 = 2460,\n\tPORT121_FN6___2 = 2461,\n\tPORT122_FN6___2 = 2462,\n\tPORT123_FN6___2 = 2463,\n\tPORT124_FN6___2 = 2464,\n\tPORT125_FN6___2 = 2465,\n\tPORT126_FN6___2 = 2466,\n\tPORT127_FN6 = 2467,\n\tPORT128_FN6___3 = 2468,\n\tPORT129_FN6___3 = 2469,\n\tPORT130_FN6___3 = 2470,\n\tPORT131_FN6___3 = 2471,\n\tPORT132_FN6___3 = 2472,\n\tPORT133_FN6___3 = 2473,\n\tPORT134_FN6___3 = 2474,\n\tPORT135_FN6___2 = 2475,\n\tPORT136_FN6___2 = 2476,\n\tPORT137_FN6___2 = 2477,\n\tPORT138_FN6___2 = 2478,\n\tPORT139_FN6___2 = 2479,\n\tPORT140_FN6___2 = 2480,\n\tPORT141_FN6___2 = 2481,\n\tPORT142_FN6___2 = 2482,\n\tPORT143_FN6___2 = 2483,\n\tPORT144_FN6___2 = 2484,\n\tPORT145_FN6___2 = 2485,\n\tPORT146_FN6___2 = 2486,\n\tPORT147_FN6___2 = 2487,\n\tPORT148_FN6___2 = 2488,\n\tPORT149_FN6___2 = 2489,\n\tPORT150_FN6___2 = 2490,\n\tPORT151_FN6___2 = 2491,\n\tPORT152_FN6___2 = 2492,\n\tPORT153_FN6___2 = 2493,\n\tPORT154_FN6___2 = 2494,\n\tPORT155_FN6___2 = 2495,\n\tPORT156_FN6___2 = 2496,\n\tPORT157_FN6___2 = 2497,\n\tPORT158_FN6___2 = 2498,\n\tPORT159_FN6___2 = 2499,\n\tPORT160_FN6___3 = 2500,\n\tPORT161_FN6___3 = 2501,\n\tPORT162_FN6___3 = 2502,\n\tPORT163_FN6___3 = 2503,\n\tPORT164_FN6___3 = 2504,\n\tPORT165_FN6___2 = 2505,\n\tPORT166_FN6___2 = 2506,\n\tPORT167_FN6___2 = 2507,\n\tPORT168_FN6___2 = 2508,\n\tPORT169_FN6___2 = 2509,\n\tPORT170_FN6___2 = 2510,\n\tPORT171_FN6___2 = 2511,\n\tPORT172_FN6___2 = 2512,\n\tPORT173_FN6___2 = 2513,\n\tPORT174_FN6___2 = 2514,\n\tPORT175_FN6___2 = 2515,\n\tPORT176_FN6___2 = 2516,\n\tPORT177_FN6___2 = 2517,\n\tPORT178_FN6___2 = 2518,\n\tPORT179_FN6 = 2519,\n\tPORT180_FN6 = 2520,\n\tPORT181_FN6 = 2521,\n\tPORT182_FN6 = 2522,\n\tPORT183_FN6 = 2523,\n\tPORT184_FN6 = 2524,\n\tPORT185_FN6 = 2525,\n\tPORT186_FN6 = 2526,\n\tPORT187_FN6 = 2527,\n\tPORT188_FN6 = 2528,\n\tPORT189_FN6 = 2529,\n\tPORT190_FN6 = 2530,\n\tPORT191_FN6 = 2531,\n\tPORT192_FN6___3 = 2532,\n\tPORT193_FN6___3 = 2533,\n\tPORT194_FN6___3 = 2534,\n\tPORT195_FN6___3 = 2535,\n\tPORT196_FN6___3 = 2536,\n\tPORT197_FN6___3 = 2537,\n\tPORT198_FN6___3 = 2538,\n\tPORT199_FN6___3 = 2539,\n\tPORT200_FN6___3 = 2540,\n\tPORT201_FN6___3 = 2541,\n\tPORT202_FN6___3 = 2542,\n\tPORT203_FN6___3 = 2543,\n\tPORT204_FN6___3 = 2544,\n\tPORT205_FN6___3 = 2545,\n\tPORT206_FN6___3 = 2546,\n\tPORT207_FN6___3 = 2547,\n\tPORT208_FN6___3 = 2548,\n\tPORT209_FN6___3 = 2549,\n\tPORT210_FN6___3 = 2550,\n\tPORT211_FN6___3 = 2551,\n\tPORT0_FN7___3 = 2552,\n\tPORT1_FN7___3 = 2553,\n\tPORT2_FN7___3 = 2554,\n\tPORT3_FN7___3 = 2555,\n\tPORT4_FN7___3 = 2556,\n\tPORT5_FN7___3 = 2557,\n\tPORT6_FN7___3 = 2558,\n\tPORT7_FN7___3 = 2559,\n\tPORT8_FN7___3 = 2560,\n\tPORT9_FN7___3 = 2561,\n\tPORT10_FN7___3 = 2562,\n\tPORT11_FN7___3 = 2563,\n\tPORT12_FN7___3 = 2564,\n\tPORT13_FN7___3 = 2565,\n\tPORT14_FN7___3 = 2566,\n\tPORT15_FN7___3 = 2567,\n\tPORT16_FN7___3 = 2568,\n\tPORT17_FN7___3 = 2569,\n\tPORT18_FN7___3 = 2570,\n\tPORT19_FN7___3 = 2571,\n\tPORT20_FN7___3 = 2572,\n\tPORT21_FN7___3 = 2573,\n\tPORT22_FN7___3 = 2574,\n\tPORT23_FN7___3 = 2575,\n\tPORT24_FN7___3 = 2576,\n\tPORT25_FN7___3 = 2577,\n\tPORT26_FN7___3 = 2578,\n\tPORT27_FN7___3 = 2579,\n\tPORT28_FN7___3 = 2580,\n\tPORT29_FN7___3 = 2581,\n\tPORT30_FN7___3 = 2582,\n\tPORT31_FN7___2 = 2583,\n\tPORT32_FN7___3 = 2584,\n\tPORT33_FN7___3 = 2585,\n\tPORT34_FN7___3 = 2586,\n\tPORT35_FN7___3 = 2587,\n\tPORT36_FN7___3 = 2588,\n\tPORT37_FN7___3 = 2589,\n\tPORT38_FN7___3 = 2590,\n\tPORT39_FN7___3 = 2591,\n\tPORT40_FN7___3 = 2592,\n\tPORT41_FN7___2 = 2593,\n\tPORT42_FN7___2 = 2594,\n\tPORT43_FN7___2 = 2595,\n\tPORT44_FN7___2 = 2596,\n\tPORT45_FN7___2 = 2597,\n\tPORT46_FN7___2 = 2598,\n\tPORT47_FN7___2 = 2599,\n\tPORT48_FN7___2 = 2600,\n\tPORT49_FN7___2 = 2601,\n\tPORT50_FN7___2 = 2602,\n\tPORT51_FN7___2 = 2603,\n\tPORT52_FN7___2 = 2604,\n\tPORT53_FN7___2 = 2605,\n\tPORT54_FN7___2 = 2606,\n\tPORT55_FN7___2 = 2607,\n\tPORT56_FN7___2 = 2608,\n\tPORT57_FN7___2 = 2609,\n\tPORT58_FN7___2 = 2610,\n\tPORT59_FN7___2 = 2611,\n\tPORT60_FN7___2 = 2612,\n\tPORT61_FN7___2 = 2613,\n\tPORT62_FN7___2 = 2614,\n\tPORT63_FN7___2 = 2615,\n\tPORT64_FN7___3 = 2616,\n\tPORT65_FN7___3 = 2617,\n\tPORT66_FN7___3 = 2618,\n\tPORT67_FN7___3 = 2619,\n\tPORT68_FN7___3 = 2620,\n\tPORT69_FN7___3 = 2621,\n\tPORT70_FN7___3 = 2622,\n\tPORT71_FN7___3 = 2623,\n\tPORT72_FN7___3 = 2624,\n\tPORT73_FN7___3 = 2625,\n\tPORT74_FN7___3 = 2626,\n\tPORT75_FN7___3 = 2627,\n\tPORT76_FN7___3 = 2628,\n\tPORT77_FN7___3 = 2629,\n\tPORT78_FN7___3 = 2630,\n\tPORT79_FN7___3 = 2631,\n\tPORT80_FN7___3 = 2632,\n\tPORT81_FN7___3 = 2633,\n\tPORT82_FN7___3 = 2634,\n\tPORT83_FN7___3 = 2635,\n\tPORT84_FN7___3 = 2636,\n\tPORT85_FN7___3 = 2637,\n\tPORT86_FN7___2 = 2638,\n\tPORT87_FN7___2 = 2639,\n\tPORT88_FN7___2 = 2640,\n\tPORT89_FN7___2 = 2641,\n\tPORT90_FN7___2 = 2642,\n\tPORT91_FN7___2 = 2643,\n\tPORT92_FN7___2 = 2644,\n\tPORT93_FN7___2 = 2645,\n\tPORT94_FN7___2 = 2646,\n\tPORT95_FN7___2 = 2647,\n\tPORT96_FN7___3 = 2648,\n\tPORT97_FN7___3 = 2649,\n\tPORT98_FN7___3 = 2650,\n\tPORT99_FN7___3 = 2651,\n\tPORT100_FN7___3 = 2652,\n\tPORT101_FN7___3 = 2653,\n\tPORT102_FN7___3 = 2654,\n\tPORT103_FN7___3 = 2655,\n\tPORT104_FN7___3 = 2656,\n\tPORT105_FN7___3 = 2657,\n\tPORT106_FN7___3 = 2658,\n\tPORT107_FN7___3 = 2659,\n\tPORT108_FN7___3 = 2660,\n\tPORT109_FN7___3 = 2661,\n\tPORT110_FN7___3 = 2662,\n\tPORT111_FN7___3 = 2663,\n\tPORT112_FN7___3 = 2664,\n\tPORT113_FN7___3 = 2665,\n\tPORT114_FN7___3 = 2666,\n\tPORT115_FN7___3 = 2667,\n\tPORT116_FN7___3 = 2668,\n\tPORT117_FN7___3 = 2669,\n\tPORT118_FN7___3 = 2670,\n\tPORT119_FN7___2 = 2671,\n\tPORT120_FN7___2 = 2672,\n\tPORT121_FN7___2 = 2673,\n\tPORT122_FN7___2 = 2674,\n\tPORT123_FN7___2 = 2675,\n\tPORT124_FN7___2 = 2676,\n\tPORT125_FN7___2 = 2677,\n\tPORT126_FN7___2 = 2678,\n\tPORT127_FN7 = 2679,\n\tPORT128_FN7___3 = 2680,\n\tPORT129_FN7___3 = 2681,\n\tPORT130_FN7___3 = 2682,\n\tPORT131_FN7___3 = 2683,\n\tPORT132_FN7___3 = 2684,\n\tPORT133_FN7___3 = 2685,\n\tPORT134_FN7___3 = 2686,\n\tPORT135_FN7___2 = 2687,\n\tPORT136_FN7___2 = 2688,\n\tPORT137_FN7___2 = 2689,\n\tPORT138_FN7___2 = 2690,\n\tPORT139_FN7___2 = 2691,\n\tPORT140_FN7___2 = 2692,\n\tPORT141_FN7___2 = 2693,\n\tPORT142_FN7___2 = 2694,\n\tPORT143_FN7___2 = 2695,\n\tPORT144_FN7___2 = 2696,\n\tPORT145_FN7___2 = 2697,\n\tPORT146_FN7___2 = 2698,\n\tPORT147_FN7___2 = 2699,\n\tPORT148_FN7___2 = 2700,\n\tPORT149_FN7___2 = 2701,\n\tPORT150_FN7___2 = 2702,\n\tPORT151_FN7___2 = 2703,\n\tPORT152_FN7___2 = 2704,\n\tPORT153_FN7___2 = 2705,\n\tPORT154_FN7___2 = 2706,\n\tPORT155_FN7___2 = 2707,\n\tPORT156_FN7___2 = 2708,\n\tPORT157_FN7___2 = 2709,\n\tPORT158_FN7___2 = 2710,\n\tPORT159_FN7___2 = 2711,\n\tPORT160_FN7___3 = 2712,\n\tPORT161_FN7___3 = 2713,\n\tPORT162_FN7___3 = 2714,\n\tPORT163_FN7___3 = 2715,\n\tPORT164_FN7___3 = 2716,\n\tPORT165_FN7___2 = 2717,\n\tPORT166_FN7___2 = 2718,\n\tPORT167_FN7___2 = 2719,\n\tPORT168_FN7___2 = 2720,\n\tPORT169_FN7___2 = 2721,\n\tPORT170_FN7___2 = 2722,\n\tPORT171_FN7___2 = 2723,\n\tPORT172_FN7___2 = 2724,\n\tPORT173_FN7___2 = 2725,\n\tPORT174_FN7___2 = 2726,\n\tPORT175_FN7___2 = 2727,\n\tPORT176_FN7___2 = 2728,\n\tPORT177_FN7___2 = 2729,\n\tPORT178_FN7___2 = 2730,\n\tPORT179_FN7 = 2731,\n\tPORT180_FN7 = 2732,\n\tPORT181_FN7 = 2733,\n\tPORT182_FN7 = 2734,\n\tPORT183_FN7 = 2735,\n\tPORT184_FN7 = 2736,\n\tPORT185_FN7 = 2737,\n\tPORT186_FN7 = 2738,\n\tPORT187_FN7 = 2739,\n\tPORT188_FN7 = 2740,\n\tPORT189_FN7 = 2741,\n\tPORT190_FN7 = 2742,\n\tPORT191_FN7 = 2743,\n\tPORT192_FN7___3 = 2744,\n\tPORT193_FN7___3 = 2745,\n\tPORT194_FN7___3 = 2746,\n\tPORT195_FN7___3 = 2747,\n\tPORT196_FN7___3 = 2748,\n\tPORT197_FN7___3 = 2749,\n\tPORT198_FN7___3 = 2750,\n\tPORT199_FN7___3 = 2751,\n\tPORT200_FN7___3 = 2752,\n\tPORT201_FN7___3 = 2753,\n\tPORT202_FN7___3 = 2754,\n\tPORT203_FN7___3 = 2755,\n\tPORT204_FN7___3 = 2756,\n\tPORT205_FN7___3 = 2757,\n\tPORT206_FN7___3 = 2758,\n\tPORT207_FN7___3 = 2759,\n\tPORT208_FN7___3 = 2760,\n\tPORT209_FN7___3 = 2761,\n\tPORT210_FN7___3 = 2762,\n\tPORT211_FN7___3 = 2763,\n\tMSEL1CR_31_0___2 = 2764,\n\tMSEL1CR_31_1___2 = 2765,\n\tMSEL1CR_30_0 = 2766,\n\tMSEL1CR_30_1 = 2767,\n\tMSEL1CR_29_0 = 2768,\n\tMSEL1CR_29_1 = 2769,\n\tMSEL1CR_28_0 = 2770,\n\tMSEL1CR_28_1 = 2771,\n\tMSEL1CR_27_0___2 = 2772,\n\tMSEL1CR_27_1___2 = 2773,\n\tMSEL1CR_26_0 = 2774,\n\tMSEL1CR_26_1 = 2775,\n\tMSEL1CR_16_0___2 = 2776,\n\tMSEL1CR_16_1___2 = 2777,\n\tMSEL1CR_15_0___2 = 2778,\n\tMSEL1CR_15_1___2 = 2779,\n\tMSEL1CR_14_0___2 = 2780,\n\tMSEL1CR_14_1___2 = 2781,\n\tMSEL1CR_13_0___2 = 2782,\n\tMSEL1CR_13_1___2 = 2783,\n\tMSEL1CR_12_0___2 = 2784,\n\tMSEL1CR_12_1___2 = 2785,\n\tMSEL1CR_9_0 = 2786,\n\tMSEL1CR_9_1 = 2787,\n\tMSEL1CR_7_0 = 2788,\n\tMSEL1CR_7_1 = 2789,\n\tMSEL1CR_6_0 = 2790,\n\tMSEL1CR_6_1 = 2791,\n\tMSEL1CR_5_0 = 2792,\n\tMSEL1CR_5_1 = 2793,\n\tMSEL1CR_4_0 = 2794,\n\tMSEL1CR_4_1 = 2795,\n\tMSEL1CR_3_0 = 2796,\n\tMSEL1CR_3_1 = 2797,\n\tMSEL1CR_2_0 = 2798,\n\tMSEL1CR_2_1 = 2799,\n\tMSEL1CR_0_0 = 2800,\n\tMSEL1CR_0_1 = 2801,\n\tMSEL3CR_15_0___2 = 2802,\n\tMSEL3CR_15_1___2 = 2803,\n\tMSEL3CR_6_0 = 2804,\n\tMSEL3CR_6_1 = 2805,\n\tMSEL4CR_19_0___2 = 2806,\n\tMSEL4CR_19_1___2 = 2807,\n\tMSEL4CR_18_0___2 = 2808,\n\tMSEL4CR_18_1___2 = 2809,\n\tMSEL4CR_15_0___2 = 2810,\n\tMSEL4CR_15_1___2 = 2811,\n\tMSEL4CR_10_0___2 = 2812,\n\tMSEL4CR_10_1___2 = 2813,\n\tMSEL4CR_6_0 = 2814,\n\tMSEL4CR_6_1 = 2815,\n\tMSEL4CR_4_0 = 2816,\n\tMSEL4CR_4_1 = 2817,\n\tMSEL4CR_1_0 = 2818,\n\tMSEL4CR_1_1 = 2819,\n\tMSEL5CR_31_0___2 = 2820,\n\tMSEL5CR_31_1___2 = 2821,\n\tMSEL5CR_30_0___2 = 2822,\n\tMSEL5CR_30_1___2 = 2823,\n\tMSEL5CR_29_0___2 = 2824,\n\tMSEL5CR_29_1___2 = 2825,\n\tMSEL5CR_27_0___2 = 2826,\n\tMSEL5CR_27_1___2 = 2827,\n\tMSEL5CR_25_0___2 = 2828,\n\tMSEL5CR_25_1___2 = 2829,\n\tMSEL5CR_23_0___2 = 2830,\n\tMSEL5CR_23_1___2 = 2831,\n\tMSEL5CR_21_0___2 = 2832,\n\tMSEL5CR_21_1___2 = 2833,\n\tMSEL5CR_19_0___2 = 2834,\n\tMSEL5CR_19_1___2 = 2835,\n\tMSEL5CR_17_0___2 = 2836,\n\tMSEL5CR_17_1___2 = 2837,\n\tMSEL5CR_15_0___2 = 2838,\n\tMSEL5CR_15_1___2 = 2839,\n\tMSEL5CR_14_0___2 = 2840,\n\tMSEL5CR_14_1___2 = 2841,\n\tMSEL5CR_13_0___2 = 2842,\n\tMSEL5CR_13_1___2 = 2843,\n\tMSEL5CR_12_0___2 = 2844,\n\tMSEL5CR_12_1___2 = 2845,\n\tMSEL5CR_11_0___2 = 2846,\n\tMSEL5CR_11_1___2 = 2847,\n\tMSEL5CR_10_0___2 = 2848,\n\tMSEL5CR_10_1___2 = 2849,\n\tMSEL5CR_8_0 = 2850,\n\tMSEL5CR_8_1 = 2851,\n\tMSEL5CR_7_0 = 2852,\n\tMSEL5CR_7_1 = 2853,\n\tMSEL5CR_6_0 = 2854,\n\tMSEL5CR_6_1 = 2855,\n\tMSEL5CR_5_0 = 2856,\n\tMSEL5CR_5_1 = 2857,\n\tMSEL5CR_4_0 = 2858,\n\tMSEL5CR_4_1 = 2859,\n\tMSEL5CR_3_0 = 2860,\n\tMSEL5CR_3_1 = 2861,\n\tMSEL5CR_2_0 = 2862,\n\tMSEL5CR_2_1 = 2863,\n\tMSEL5CR_0_0 = 2864,\n\tMSEL5CR_0_1 = 2865,\n\tPINMUX_FUNCTION_END___6 = 2866,\n\tPINMUX_MARK_BEGIN___6 = 2867,\n\tIRQ0_PORT2_MARK = 2868,\n\tIRQ0_PORT13_MARK = 2869,\n\tIRQ1_MARK___5 = 2870,\n\tIRQ2_PORT11_MARK = 2871,\n\tIRQ2_PORT12_MARK = 2872,\n\tIRQ3_PORT10_MARK = 2873,\n\tIRQ3_PORT14_MARK = 2874,\n\tIRQ4_PORT15_MARK = 2875,\n\tIRQ4_PORT172_MARK = 2876,\n\tIRQ5_PORT0_MARK = 2877,\n\tIRQ5_PORT1_MARK = 2878,\n\tIRQ6_PORT121_MARK = 2879,\n\tIRQ6_PORT173_MARK = 2880,\n\tIRQ7_PORT120_MARK = 2881,\n\tIRQ7_PORT209_MARK = 2882,\n\tIRQ8_MARK___4 = 2883,\n\tIRQ9_PORT118_MARK = 2884,\n\tIRQ9_PORT210_MARK = 2885,\n\tIRQ10_MARK___2 = 2886,\n\tIRQ11_MARK___2 = 2887,\n\tIRQ12_PORT42_MARK = 2888,\n\tIRQ12_PORT97_MARK = 2889,\n\tIRQ13_PORT64_MARK = 2890,\n\tIRQ13_PORT98_MARK = 2891,\n\tIRQ14_PORT63_MARK = 2892,\n\tIRQ14_PORT99_MARK = 2893,\n\tIRQ15_PORT62_MARK = 2894,\n\tIRQ15_PORT100_MARK = 2895,\n\tIRQ16_PORT68_MARK = 2896,\n\tIRQ16_PORT211_MARK = 2897,\n\tIRQ17_MARK___2 = 2898,\n\tIRQ18_MARK___2 = 2899,\n\tIRQ19_MARK___2 = 2900,\n\tIRQ20_MARK___2 = 2901,\n\tIRQ21_MARK___2 = 2902,\n\tIRQ22_MARK___2 = 2903,\n\tIRQ23_MARK___2 = 2904,\n\tIRQ24_MARK___2 = 2905,\n\tIRQ25_MARK___2 = 2906,\n\tIRQ26_PORT58_MARK = 2907,\n\tIRQ26_PORT81_MARK = 2908,\n\tIRQ27_PORT57_MARK = 2909,\n\tIRQ27_PORT168_MARK = 2910,\n\tIRQ28_PORT56_MARK = 2911,\n\tIRQ28_PORT169_MARK = 2912,\n\tIRQ29_PORT50_MARK = 2913,\n\tIRQ29_PORT170_MARK = 2914,\n\tIRQ30_PORT49_MARK = 2915,\n\tIRQ30_PORT171_MARK = 2916,\n\tIRQ31_PORT41_MARK = 2917,\n\tIRQ31_PORT167_MARK = 2918,\n\tDBGMDT2_MARK = 2919,\n\tDBGMDT1_MARK = 2920,\n\tDBGMDT0_MARK = 2921,\n\tDBGMD10_MARK = 2922,\n\tDBGMD11_MARK = 2923,\n\tDBGMD20_MARK = 2924,\n\tDBGMD21_MARK = 2925,\n\tFSIAISLD_PORT0_MARK = 2926,\n\tFSIAISLD_PORT5_MARK = 2927,\n\tFSIASPDIF_PORT9_MARK = 2928,\n\tFSIASPDIF_PORT18_MARK = 2929,\n\tFSIAOSLD1_MARK = 2930,\n\tFSIAOSLD2_MARK = 2931,\n\tFSIAOLR_MARK___3 = 2932,\n\tFSIAOBT_MARK___3 = 2933,\n\tFSIAOSLD_MARK___3 = 2934,\n\tFSIAOMC_MARK___3 = 2935,\n\tFSIACK_MARK___3 = 2936,\n\tFSIAILR_MARK___3 = 2937,\n\tFSIAIBT_MARK___3 = 2938,\n\tFSIBCK_MARK___3 = 2939,\n\tFMSISLD_PORT1_MARK = 2940,\n\tFMSISLD_PORT6_MARK = 2941,\n\tFMSIILR_MARK = 2942,\n\tFMSIIBT_MARK = 2943,\n\tFMSIOLR_MARK = 2944,\n\tFMSIOBT_MARK = 2945,\n\tFMSICK_MARK = 2946,\n\tFMSOILR_MARK = 2947,\n\tFMSOIBT_MARK = 2948,\n\tFMSOOLR_MARK = 2949,\n\tFMSOOBT_MARK = 2950,\n\tFMSOSLD_MARK = 2951,\n\tFMSOCK_MARK = 2952,\n\tSCIFA0_SCK_MARK___3 = 2953,\n\tSCIFA0_CTS_MARK___2 = 2954,\n\tSCIFA0_RTS_MARK___2 = 2955,\n\tSCIFA0_RXD_MARK___5 = 2956,\n\tSCIFA0_TXD_MARK___5 = 2957,\n\tSCIFA1_CTS_MARK___2 = 2958,\n\tSCIFA1_SCK_MARK___5 = 2959,\n\tSCIFA1_RXD_MARK___5 = 2960,\n\tSCIFA1_TXD_MARK___5 = 2961,\n\tSCIFA1_RTS_MARK___2 = 2962,\n\tSCIFA2_SCK_PORT22_MARK = 2963,\n\tSCIFA2_SCK_PORT199_MARK = 2964,\n\tSCIFA2_RXD_MARK___3 = 2965,\n\tSCIFA2_TXD_MARK___3 = 2966,\n\tSCIFA2_CTS_MARK = 2967,\n\tSCIFA2_RTS_MARK = 2968,\n\tSCIFA3_RTS_PORT105_MARK = 2969,\n\tSCIFA3_SCK_PORT116_MARK = 2970,\n\tSCIFA3_CTS_PORT117_MARK = 2971,\n\tSCIFA3_RXD_PORT174_MARK = 2972,\n\tSCIFA3_TXD_PORT175_MARK = 2973,\n\tSCIFA3_RTS_PORT161_MARK = 2974,\n\tSCIFA3_SCK_PORT158_MARK = 2975,\n\tSCIFA3_CTS_PORT162_MARK = 2976,\n\tSCIFA3_RXD_PORT159_MARK = 2977,\n\tSCIFA3_TXD_PORT160_MARK = 2978,\n\tSCIFA4_RXD_PORT12_MARK = 2979,\n\tSCIFA4_TXD_PORT13_MARK = 2980,\n\tSCIFA4_RXD_PORT204_MARK = 2981,\n\tSCIFA4_TXD_PORT203_MARK = 2982,\n\tSCIFA4_RXD_PORT94_MARK = 2983,\n\tSCIFA4_TXD_PORT93_MARK = 2984,\n\tSCIFA4_SCK_PORT21_MARK = 2985,\n\tSCIFA4_SCK_PORT205_MARK = 2986,\n\tSCIFA5_TXD_PORT20_MARK = 2987,\n\tSCIFA5_RXD_PORT10_MARK = 2988,\n\tSCIFA5_RXD_PORT207_MARK = 2989,\n\tSCIFA5_TXD_PORT208_MARK = 2990,\n\tSCIFA5_TXD_PORT91_MARK = 2991,\n\tSCIFA5_RXD_PORT92_MARK = 2992,\n\tSCIFA5_SCK_PORT23_MARK = 2993,\n\tSCIFA5_SCK_PORT206_MARK = 2994,\n\tSCIFA6_SCK_MARK = 2995,\n\tSCIFA6_RXD_MARK = 2996,\n\tSCIFA6_TXD_MARK___2 = 2997,\n\tSCIFA7_TXD_MARK___2 = 2998,\n\tSCIFA7_RXD_MARK___2 = 2999,\n\tSCIFB_SCK_PORT190_MARK = 3000,\n\tSCIFB_RXD_PORT191_MARK = 3001,\n\tSCIFB_TXD_PORT192_MARK = 3002,\n\tSCIFB_RTS_PORT186_MARK = 3003,\n\tSCIFB_CTS_PORT187_MARK = 3004,\n\tSCIFB_SCK_PORT2_MARK = 3005,\n\tSCIFB_RXD_PORT3_MARK = 3006,\n\tSCIFB_TXD_PORT4_MARK = 3007,\n\tSCIFB_RTS_PORT172_MARK = 3008,\n\tSCIFB_CTS_PORT173_MARK = 3009,\n\tLCD0_D0_MARK = 3010,\n\tLCD0_D1_MARK = 3011,\n\tLCD0_D2_MARK = 3012,\n\tLCD0_D3_MARK = 3013,\n\tLCD0_D4_MARK = 3014,\n\tLCD0_D5_MARK = 3015,\n\tLCD0_D6_MARK = 3016,\n\tLCD0_D7_MARK = 3017,\n\tLCD0_D8_MARK = 3018,\n\tLCD0_D9_MARK = 3019,\n\tLCD0_D10_MARK = 3020,\n\tLCD0_D11_MARK = 3021,\n\tLCD0_D12_MARK = 3022,\n\tLCD0_D13_MARK = 3023,\n\tLCD0_D14_MARK = 3024,\n\tLCD0_D15_MARK = 3025,\n\tLCD0_D16_MARK = 3026,\n\tLCD0_D17_MARK = 3027,\n\tLCD0_DON_MARK = 3028,\n\tLCD0_VCPWC_MARK = 3029,\n\tLCD0_VEPWC_MARK = 3030,\n\tLCD0_DCK_MARK = 3031,\n\tLCD0_VSYN_MARK = 3032,\n\tLCD0_HSYN_MARK = 3033,\n\tLCD0_DISP_MARK = 3034,\n\tLCD0_WR_MARK = 3035,\n\tLCD0_RD_MARK = 3036,\n\tLCD0_CS_MARK = 3037,\n\tLCD0_RS_MARK = 3038,\n\tLCD0_D21_PORT158_MARK = 3039,\n\tLCD0_D23_PORT159_MARK = 3040,\n\tLCD0_D22_PORT160_MARK = 3041,\n\tLCD0_D20_PORT161_MARK = 3042,\n\tLCD0_D19_PORT162_MARK = 3043,\n\tLCD0_D18_PORT163_MARK = 3044,\n\tLCD0_LCLK_PORT165_MARK = 3045,\n\tLCD0_D18_PORT40_MARK = 3046,\n\tLCD0_D22_PORT0_MARK = 3047,\n\tLCD0_D23_PORT1_MARK = 3048,\n\tLCD0_D21_PORT2_MARK = 3049,\n\tLCD0_D20_PORT3_MARK = 3050,\n\tLCD0_D19_PORT4_MARK = 3051,\n\tLCD0_LCLK_PORT102_MARK = 3052,\n\tLCD1_D0_MARK = 3053,\n\tLCD1_D1_MARK = 3054,\n\tLCD1_D2_MARK = 3055,\n\tLCD1_D3_MARK = 3056,\n\tLCD1_D4_MARK = 3057,\n\tLCD1_D5_MARK = 3058,\n\tLCD1_D6_MARK = 3059,\n\tLCD1_D7_MARK = 3060,\n\tLCD1_D8_MARK = 3061,\n\tLCD1_D9_MARK = 3062,\n\tLCD1_D10_MARK = 3063,\n\tLCD1_D11_MARK = 3064,\n\tLCD1_D12_MARK = 3065,\n\tLCD1_D13_MARK = 3066,\n\tLCD1_D14_MARK = 3067,\n\tLCD1_D15_MARK = 3068,\n\tLCD1_D16_MARK = 3069,\n\tLCD1_D17_MARK = 3070,\n\tLCD1_D18_MARK = 3071,\n\tLCD1_D19_MARK = 3072,\n\tLCD1_D20_MARK = 3073,\n\tLCD1_D21_MARK = 3074,\n\tLCD1_D22_MARK = 3075,\n\tLCD1_D23_MARK = 3076,\n\tLCD1_DON_MARK = 3077,\n\tLCD1_VCPWC_MARK = 3078,\n\tLCD1_LCLK_MARK = 3079,\n\tLCD1_VEPWC_MARK = 3080,\n\tLCD1_DCK_MARK = 3081,\n\tLCD1_VSYN_MARK = 3082,\n\tLCD1_HSYN_MARK = 3083,\n\tLCD1_DISP_MARK = 3084,\n\tLCD1_RS_MARK = 3085,\n\tLCD1_CS_MARK = 3086,\n\tLCD1_RD_MARK = 3087,\n\tLCD1_WR_MARK = 3088,\n\tRSPI_SSL0_A_MARK = 3089,\n\tRSPI_SSL1_A_MARK = 3090,\n\tRSPI_SSL2_A_MARK = 3091,\n\tRSPI_SSL3_A_MARK = 3092,\n\tRSPI_CK_A_MARK = 3093,\n\tRSPI_MOSI_A_MARK = 3094,\n\tRSPI_MISO_A_MARK = 3095,\n\tVIO_CKO1_MARK = 3096,\n\tVIO_CKO2_MARK = 3097,\n\tVIO_CKO_1_MARK = 3098,\n\tVIO_CKO_MARK___2 = 3099,\n\tVIO0_D0_MARK = 3100,\n\tVIO0_D1_MARK = 3101,\n\tVIO0_D2_MARK = 3102,\n\tVIO0_D3_MARK = 3103,\n\tVIO0_D4_MARK = 3104,\n\tVIO0_D5_MARK = 3105,\n\tVIO0_D6_MARK = 3106,\n\tVIO0_D7_MARK = 3107,\n\tVIO0_D8_MARK = 3108,\n\tVIO0_D9_MARK = 3109,\n\tVIO0_D10_MARK = 3110,\n\tVIO0_D11_MARK = 3111,\n\tVIO0_D12_MARK = 3112,\n\tVIO0_VD_MARK = 3113,\n\tVIO0_HD_MARK = 3114,\n\tVIO0_CLK_MARK = 3115,\n\tVIO0_FIELD_MARK = 3116,\n\tVIO0_D13_PORT26_MARK = 3117,\n\tVIO0_D14_PORT25_MARK = 3118,\n\tVIO0_D15_PORT24_MARK = 3119,\n\tVIO0_D13_PORT22_MARK = 3120,\n\tVIO0_D14_PORT95_MARK = 3121,\n\tVIO0_D15_PORT96_MARK = 3122,\n\tVIO1_D0_MARK = 3123,\n\tVIO1_D1_MARK = 3124,\n\tVIO1_D2_MARK = 3125,\n\tVIO1_D3_MARK = 3126,\n\tVIO1_D4_MARK = 3127,\n\tVIO1_D5_MARK = 3128,\n\tVIO1_D6_MARK = 3129,\n\tVIO1_D7_MARK = 3130,\n\tVIO1_VD_MARK = 3131,\n\tVIO1_HD_MARK = 3132,\n\tVIO1_CLK_MARK = 3133,\n\tVIO1_FIELD_MARK = 3134,\n\tTPU0TO0_MARK___3 = 3135,\n\tTPU0TO1_MARK___3 = 3136,\n\tTPU0TO3_MARK___3 = 3137,\n\tTPU0TO2_PORT66_MARK = 3138,\n\tTPU0TO2_PORT202_MARK = 3139,\n\tSTP0_IPD0_MARK = 3140,\n\tSTP0_IPD1_MARK = 3141,\n\tSTP0_IPD2_MARK = 3142,\n\tSTP0_IPD3_MARK = 3143,\n\tSTP0_IPD4_MARK = 3144,\n\tSTP0_IPD5_MARK = 3145,\n\tSTP0_IPD6_MARK = 3146,\n\tSTP0_IPD7_MARK = 3147,\n\tSTP0_IPEN_MARK = 3148,\n\tSTP0_IPCLK_MARK = 3149,\n\tSTP0_IPSYNC_MARK = 3150,\n\tSTP1_IPD1_MARK = 3151,\n\tSTP1_IPD2_MARK = 3152,\n\tSTP1_IPD3_MARK = 3153,\n\tSTP1_IPD4_MARK = 3154,\n\tSTP1_IPD5_MARK = 3155,\n\tSTP1_IPD6_MARK = 3156,\n\tSTP1_IPD7_MARK = 3157,\n\tSTP1_IPCLK_MARK = 3158,\n\tSTP1_IPSYNC_MARK = 3159,\n\tSTP1_IPD0_PORT186_MARK = 3160,\n\tSTP1_IPEN_PORT187_MARK = 3161,\n\tSTP1_IPD0_PORT194_MARK = 3162,\n\tSTP1_IPEN_PORT193_MARK = 3163,\n\tSIM_RST_MARK___3 = 3164,\n\tSIM_CLK_MARK___3 = 3165,\n\tSIM_D_PORT22_MARK = 3166,\n\tSIM_D_PORT199_MARK = 3167,\n\tSDHI0_D0_MARK = 3168,\n\tSDHI0_D1_MARK = 3169,\n\tSDHI0_D2_MARK = 3170,\n\tSDHI0_D3_MARK = 3171,\n\tSDHI0_CD_MARK = 3172,\n\tSDHI0_WP_MARK = 3173,\n\tSDHI0_CMD_MARK = 3174,\n\tSDHI0_CLK_MARK = 3175,\n\tSDHI1_D0_MARK = 3176,\n\tSDHI1_D1_MARK = 3177,\n\tSDHI1_D2_MARK = 3178,\n\tSDHI1_D3_MARK = 3179,\n\tSDHI1_CD_MARK = 3180,\n\tSDHI1_WP_MARK = 3181,\n\tSDHI1_CMD_MARK = 3182,\n\tSDHI1_CLK_MARK = 3183,\n\tSDHI2_D0_MARK = 3184,\n\tSDHI2_D1_MARK = 3185,\n\tSDHI2_D2_MARK = 3186,\n\tSDHI2_D3_MARK = 3187,\n\tSDHI2_CLK_MARK = 3188,\n\tSDHI2_CMD_MARK = 3189,\n\tSDHI2_CD_PORT24_MARK = 3190,\n\tSDHI2_WP_PORT25_MARK = 3191,\n\tSDHI2_WP_PORT177_MARK = 3192,\n\tSDHI2_CD_PORT202_MARK = 3193,\n\tMSIOF2_TXD_MARK___5 = 3194,\n\tMSIOF2_RXD_MARK___4 = 3195,\n\tMSIOF2_TSCK_MARK___2 = 3196,\n\tMSIOF2_SS2_MARK___4 = 3197,\n\tMSIOF2_TSYNC_MARK___2 = 3198,\n\tMSIOF2_SS1_MARK___4 = 3199,\n\tMSIOF2_MCK1_MARK___2 = 3200,\n\tMSIOF2_MCK0_MARK___2 = 3201,\n\tMSIOF2_RSYNC_MARK___2 = 3202,\n\tMSIOF2_RSCK_MARK___2 = 3203,\n\tKEYIN4_MARK___3 = 3204,\n\tKEYIN5_MARK___3 = 3205,\n\tKEYIN6_MARK___3 = 3206,\n\tKEYIN7_MARK___3 = 3207,\n\tKEYOUT0_MARK___3 = 3208,\n\tKEYOUT1_MARK___3 = 3209,\n\tKEYOUT2_MARK___3 = 3210,\n\tKEYOUT3_MARK___3 = 3211,\n\tKEYOUT4_MARK___3 = 3212,\n\tKEYOUT5_MARK___3 = 3213,\n\tKEYOUT6_MARK___2 = 3214,\n\tKEYOUT7_MARK___2 = 3215,\n\tKEYIN0_PORT43_MARK = 3216,\n\tKEYIN1_PORT44_MARK = 3217,\n\tKEYIN2_PORT45_MARK = 3218,\n\tKEYIN3_PORT46_MARK = 3219,\n\tKEYIN0_PORT58_MARK = 3220,\n\tKEYIN1_PORT57_MARK = 3221,\n\tKEYIN2_PORT56_MARK = 3222,\n\tKEYIN3_PORT55_MARK = 3223,\n\tDV_D0_MARK = 3224,\n\tDV_D1_MARK = 3225,\n\tDV_D2_MARK = 3226,\n\tDV_D3_MARK = 3227,\n\tDV_D4_MARK = 3228,\n\tDV_D5_MARK = 3229,\n\tDV_D6_MARK = 3230,\n\tDV_D7_MARK = 3231,\n\tDV_D8_MARK = 3232,\n\tDV_D9_MARK = 3233,\n\tDV_D10_MARK = 3234,\n\tDV_D11_MARK = 3235,\n\tDV_D12_MARK = 3236,\n\tDV_D13_MARK = 3237,\n\tDV_D14_MARK = 3238,\n\tDV_D15_MARK = 3239,\n\tDV_CLK_MARK = 3240,\n\tDV_VSYNC_MARK = 3241,\n\tDV_HSYNC_MARK = 3242,\n\tMEMC_AD0_MARK = 3243,\n\tMEMC_AD1_MARK = 3244,\n\tMEMC_AD2_MARK = 3245,\n\tMEMC_AD3_MARK = 3246,\n\tMEMC_AD4_MARK = 3247,\n\tMEMC_AD5_MARK = 3248,\n\tMEMC_AD6_MARK = 3249,\n\tMEMC_AD7_MARK = 3250,\n\tMEMC_AD8_MARK = 3251,\n\tMEMC_AD9_MARK = 3252,\n\tMEMC_AD10_MARK = 3253,\n\tMEMC_AD11_MARK = 3254,\n\tMEMC_AD12_MARK = 3255,\n\tMEMC_AD13_MARK = 3256,\n\tMEMC_AD14_MARK = 3257,\n\tMEMC_AD15_MARK = 3258,\n\tMEMC_CS0_MARK = 3259,\n\tMEMC_INT_MARK = 3260,\n\tMEMC_NWE_MARK = 3261,\n\tMEMC_NOE_MARK = 3262,\n\tMEMC_CS1_MARK = 3263,\n\tMEMC_ADV_MARK = 3264,\n\tMEMC_WAIT_MARK = 3265,\n\tMEMC_BUSCLK_MARK = 3266,\n\tMEMC_A1_MARK = 3267,\n\tMEMC_DREQ0_MARK = 3268,\n\tMEMC_DREQ1_MARK = 3269,\n\tMEMC_A0_MARK = 3270,\n\tMMC0_D0_PORT68_MARK = 3271,\n\tMMC0_D1_PORT69_MARK = 3272,\n\tMMC0_D2_PORT70_MARK = 3273,\n\tMMC0_D3_PORT71_MARK = 3274,\n\tMMC0_D4_PORT72_MARK = 3275,\n\tMMC0_D5_PORT73_MARK = 3276,\n\tMMC0_D6_PORT74_MARK = 3277,\n\tMMC0_D7_PORT75_MARK = 3278,\n\tMMC0_CLK_PORT66_MARK = 3279,\n\tMMC0_CMD_PORT67_MARK = 3280,\n\tMMC1_D0_PORT149_MARK = 3281,\n\tMMC1_D1_PORT148_MARK = 3282,\n\tMMC1_D2_PORT147_MARK = 3283,\n\tMMC1_D3_PORT146_MARK = 3284,\n\tMMC1_D4_PORT145_MARK = 3285,\n\tMMC1_D5_PORT144_MARK = 3286,\n\tMMC1_D6_PORT143_MARK = 3287,\n\tMMC1_D7_PORT142_MARK = 3288,\n\tMMC1_CLK_PORT103_MARK = 3289,\n\tMMC1_CMD_PORT104_MARK = 3290,\n\tMSIOF0_SS1_MARK___5 = 3291,\n\tMSIOF0_SS2_MARK___5 = 3292,\n\tMSIOF0_RXD_MARK___5 = 3293,\n\tMSIOF0_TXD_MARK___5 = 3294,\n\tMSIOF0_MCK0_MARK___2 = 3295,\n\tMSIOF0_MCK1_MARK___2 = 3296,\n\tMSIOF0_RSYNC_MARK___2 = 3297,\n\tMSIOF0_RSCK_MARK___2 = 3298,\n\tMSIOF0_TSCK_MARK___2 = 3299,\n\tMSIOF0_TSYNC_MARK___2 = 3300,\n\tMSIOF1_RSCK_MARK___2 = 3301,\n\tMSIOF1_RSYNC_MARK___2 = 3302,\n\tMSIOF1_MCK0_MARK___2 = 3303,\n\tMSIOF1_MCK1_MARK___2 = 3304,\n\tMSIOF1_SS2_PORT116_MARK = 3305,\n\tMSIOF1_SS1_PORT117_MARK = 3306,\n\tMSIOF1_RXD_PORT118_MARK = 3307,\n\tMSIOF1_TXD_PORT119_MARK = 3308,\n\tMSIOF1_TSYNC_PORT120_MARK = 3309,\n\tMSIOF1_TSCK_PORT121_MARK = 3310,\n\tMSIOF1_SS1_PORT67_MARK = 3311,\n\tMSIOF1_TSCK_PORT72_MARK = 3312,\n\tMSIOF1_TSYNC_PORT73_MARK = 3313,\n\tMSIOF1_TXD_PORT74_MARK = 3314,\n\tMSIOF1_RXD_PORT75_MARK = 3315,\n\tMSIOF1_SS2_PORT202_MARK = 3316,\n\tGPO0_MARK___2 = 3317,\n\tGPI0_MARK___2 = 3318,\n\tGPO1_MARK___2 = 3319,\n\tGPI1_MARK___2 = 3320,\n\tUSB0_OCI_MARK = 3321,\n\tUSB0_PPON_MARK = 3322,\n\tVBUS_MARK = 3323,\n\tUSB1_OCI_MARK = 3324,\n\tUSB1_PPON_MARK = 3325,\n\tBBIF1_RXD_MARK___2 = 3326,\n\tBBIF1_TXD_MARK___2 = 3327,\n\tBBIF1_TSYNC_MARK___2 = 3328,\n\tBBIF1_TSCK_MARK___2 = 3329,\n\tBBIF1_RSCK_MARK___2 = 3330,\n\tBBIF1_RSYNC_MARK___2 = 3331,\n\tBBIF1_FLOW_MARK___2 = 3332,\n\tBBIF1_RX_FLOW_N_MARK = 3333,\n\tBBIF2_TXD2_PORT5_MARK = 3334,\n\tBBIF2_RXD2_PORT60_MARK = 3335,\n\tBBIF2_TSYNC2_PORT6_MARK = 3336,\n\tBBIF2_TSCK2_PORT59_MARK = 3337,\n\tBBIF2_RXD2_PORT90_MARK = 3338,\n\tBBIF2_TXD2_PORT183_MARK = 3339,\n\tBBIF2_TSCK2_PORT89_MARK = 3340,\n\tBBIF2_TSYNC2_PORT184_MARK = 3341,\n\tCS0_MARK___2 = 3342,\n\tCS2_MARK = 3343,\n\tCS4_MARK = 3344,\n\tCS5B_MARK = 3345,\n\tCS6A_MARK = 3346,\n\tCS5A_PORT105_MARK = 3347,\n\tCS5A_PORT19_MARK = 3348,\n\tIOIS16_MARK = 3349,\n\tA0_MARK___6 = 3350,\n\tA1_MARK___4 = 3351,\n\tA2_MARK___4 = 3352,\n\tA3_MARK___4 = 3353,\n\tA4_FOE_MARK = 3354,\n\tA5_FCDE_MARK = 3355,\n\tA6_MARK___4 = 3356,\n\tA7_MARK___4 = 3357,\n\tA8_MARK___4 = 3358,\n\tA9_MARK___4 = 3359,\n\tA10_MARK___4 = 3360,\n\tA11_MARK___4 = 3361,\n\tA12_MARK___4 = 3362,\n\tA13_MARK___4 = 3363,\n\tA14_MARK___4 = 3364,\n\tA15_MARK___4 = 3365,\n\tA16_MARK___4 = 3366,\n\tA17_MARK___5 = 3367,\n\tA18_MARK___5 = 3368,\n\tA19_MARK___5 = 3369,\n\tA20_MARK___5 = 3370,\n\tA21_MARK___5 = 3371,\n\tA22_MARK___5 = 3372,\n\tA23_MARK___5 = 3373,\n\tA24_MARK___5 = 3374,\n\tA25_MARK___5 = 3375,\n\tA26_MARK___2 = 3376,\n\tD0_NAF0_MARK___2 = 3377,\n\tD1_NAF1_MARK___2 = 3378,\n\tD2_NAF2_MARK___2 = 3379,\n\tD3_NAF3_MARK___2 = 3380,\n\tD4_NAF4_MARK___2 = 3381,\n\tD5_NAF5_MARK___2 = 3382,\n\tD6_NAF6_MARK___2 = 3383,\n\tD7_NAF7_MARK___2 = 3384,\n\tD8_NAF8_MARK___2 = 3385,\n\tD9_NAF9_MARK___2 = 3386,\n\tD10_NAF10_MARK___2 = 3387,\n\tD11_NAF11_MARK___2 = 3388,\n\tD12_NAF12_MARK___2 = 3389,\n\tD13_NAF13_MARK___2 = 3390,\n\tD14_NAF14_MARK___2 = 3391,\n\tD15_NAF15_MARK___2 = 3392,\n\tD16_MARK___2 = 3393,\n\tD17_MARK___2 = 3394,\n\tD18_MARK___2 = 3395,\n\tD19_MARK___2 = 3396,\n\tD20_MARK___2 = 3397,\n\tD21_MARK___2 = 3398,\n\tD22_MARK___2 = 3399,\n\tD23_MARK___2 = 3400,\n\tD24_MARK___2 = 3401,\n\tD25_MARK___2 = 3402,\n\tD26_MARK___2 = 3403,\n\tD27_MARK___2 = 3404,\n\tD28_MARK___2 = 3405,\n\tD29_MARK___2 = 3406,\n\tD30_MARK___2 = 3407,\n\tD31_MARK___2 = 3408,\n\tWE0_FWE_MARK = 3409,\n\tWE1_MARK = 3410,\n\tWE2_ICIORD_MARK = 3411,\n\tWE3_ICIOWR_MARK = 3412,\n\tCKO_MARK___3 = 3413,\n\tBS_MARK___3 = 3414,\n\tRDWR_MARK = 3415,\n\tRD_FSC_MARK = 3416,\n\tWAIT_PORT177_MARK = 3417,\n\tWAIT_PORT90_MARK = 3418,\n\tFCE0_MARK = 3419,\n\tFCE1_MARK = 3420,\n\tFRB_MARK___3 = 3421,\n\tIRDA_FIRSEL_MARK___2 = 3422,\n\tIRDA_IN_MARK___2 = 3423,\n\tIRDA_OUT_MARK___2 = 3424,\n\tIDE_D0_MARK = 3425,\n\tIDE_D1_MARK = 3426,\n\tIDE_D2_MARK = 3427,\n\tIDE_D3_MARK = 3428,\n\tIDE_D4_MARK = 3429,\n\tIDE_D5_MARK = 3430,\n\tIDE_D6_MARK = 3431,\n\tIDE_D7_MARK = 3432,\n\tIDE_D8_MARK = 3433,\n\tIDE_D9_MARK = 3434,\n\tIDE_D10_MARK = 3435,\n\tIDE_D11_MARK = 3436,\n\tIDE_D12_MARK = 3437,\n\tIDE_D13_MARK = 3438,\n\tIDE_D14_MARK = 3439,\n\tIDE_D15_MARK = 3440,\n\tIDE_A0_MARK = 3441,\n\tIDE_A1_MARK = 3442,\n\tIDE_A2_MARK = 3443,\n\tIDE_CS0_MARK = 3444,\n\tIDE_CS1_MARK = 3445,\n\tIDE_IOWR_MARK = 3446,\n\tIDE_IORD_MARK = 3447,\n\tIDE_IORDY_MARK = 3448,\n\tIDE_INT_MARK = 3449,\n\tIDE_RST_MARK = 3450,\n\tIDE_DIRECTION_MARK = 3451,\n\tIDE_EXBUF_ENB_MARK = 3452,\n\tIDE_IODACK_MARK = 3453,\n\tIDE_IODREQ_MARK = 3454,\n\tRMII_CRS_DV_MARK = 3455,\n\tRMII_RX_ER_MARK = 3456,\n\tRMII_RXD0_MARK = 3457,\n\tRMII_RXD1_MARK = 3458,\n\tRMII_TX_EN_MARK = 3459,\n\tRMII_TXD0_MARK = 3460,\n\tRMII_MDC_MARK = 3461,\n\tRMII_TXD1_MARK = 3462,\n\tRMII_MDIO_MARK = 3463,\n\tRMII_REF50CK_MARK = 3464,\n\tRMII_REF125CK_MARK = 3465,\n\tET_TX_CLK_MARK = 3466,\n\tET_TX_EN_MARK = 3467,\n\tET_ETXD0_MARK = 3468,\n\tET_ETXD1_MARK = 3469,\n\tET_ETXD2_MARK = 3470,\n\tET_ETXD3_MARK = 3471,\n\tET_ETXD4_MARK = 3472,\n\tET_ETXD5_MARK = 3473,\n\tET_ETXD6_MARK = 3474,\n\tET_ETXD7_MARK = 3475,\n\tET_COL_MARK = 3476,\n\tET_TX_ER_MARK = 3477,\n\tET_RX_CLK_MARK = 3478,\n\tET_RX_DV_MARK = 3479,\n\tET_ERXD0_MARK = 3480,\n\tET_ERXD1_MARK = 3481,\n\tET_ERXD2_MARK = 3482,\n\tET_ERXD3_MARK = 3483,\n\tET_ERXD4_MARK = 3484,\n\tET_ERXD5_MARK = 3485,\n\tET_ERXD6_MARK = 3486,\n\tET_ERXD7_MARK = 3487,\n\tET_RX_ER_MARK = 3488,\n\tET_CRS_MARK = 3489,\n\tET_MDC_MARK = 3490,\n\tET_MDIO_MARK = 3491,\n\tET_LINK_MARK = 3492,\n\tET_PHY_INT_MARK = 3493,\n\tET_WOL_MARK = 3494,\n\tET_GTX_CLK_MARK = 3495,\n\tDREQ0_MARK___4 = 3496,\n\tDACK0_MARK___5 = 3497,\n\tDREQ1_MARK___4 = 3498,\n\tDACK1_MARK___5 = 3499,\n\tRESETOUTS_MARK = 3500,\n\tRESETP_PULLUP_MARK = 3501,\n\tRESETP_PLAIN_MARK = 3502,\n\tIROUT_MARK = 3503,\n\tSDENC_CPG_MARK = 3504,\n\tSDENC_DV_CLKI_MARK = 3505,\n\tHDMI_HPD_MARK = 3506,\n\tHDMI_CEC_MARK = 3507,\n\tEDEBGREQ_PULLUP_MARK = 3508,\n\tEDEBGREQ_PULLDOWN_MARK = 3509,\n\tTRACEAUD_FROM_VIO_MARK = 3510,\n\tTRACEAUD_FROM_LCDC0_MARK = 3511,\n\tTRACEAUD_FROM_MEMC_MARK = 3512,\n\tPINMUX_MARK_END___6 = 3513,\n};\n\nenum {\n\tPINMUX_RESERVED___7 = 0,\n\tPINMUX_DATA_BEGIN___7 = 1,\n\tGP_0_0_DATA___4 = 2,\n\tGP_0_1_DATA___4 = 3,\n\tGP_0_2_DATA___4 = 4,\n\tGP_0_3_DATA___4 = 5,\n\tGP_0_4_DATA___4 = 6,\n\tGP_0_5_DATA___4 = 7,\n\tGP_0_6_DATA___4 = 8,\n\tGP_0_7_DATA___4 = 9,\n\tGP_0_8_DATA___4 = 10,\n\tGP_0_9_DATA___4 = 11,\n\tGP_0_10_DATA___4 = 12,\n\tGP_0_11_DATA___4 = 13,\n\tGP_0_12_DATA___4 = 14,\n\tGP_0_13_DATA___4 = 15,\n\tGP_0_14_DATA___4 = 16,\n\tGP_0_15_DATA___4 = 17,\n\tGP_0_16_DATA___4 = 18,\n\tGP_0_17_DATA___4 = 19,\n\tGP_0_18_DATA___4 = 20,\n\tGP_0_19_DATA___4 = 21,\n\tGP_0_20_DATA___4 = 22,\n\tGP_0_21_DATA___4 = 23,\n\tGP_0_22_DATA___4 = 24,\n\tGP_1_0_DATA___4 = 25,\n\tGP_1_1_DATA___4 = 26,\n\tGP_1_2_DATA___4 = 27,\n\tGP_1_3_DATA___4 = 28,\n\tGP_1_4_DATA___4 = 29,\n\tGP_1_5_DATA___4 = 30,\n\tGP_1_6_DATA___4 = 31,\n\tGP_1_7_DATA___4 = 32,\n\tGP_1_8_DATA___4 = 33,\n\tGP_1_9_DATA___4 = 34,\n\tGP_1_10_DATA___4 = 35,\n\tGP_1_11_DATA___4 = 36,\n\tGP_1_12_DATA___4 = 37,\n\tGP_1_13_DATA___4 = 38,\n\tGP_1_14_DATA___4 = 39,\n\tGP_1_15_DATA___4 = 40,\n\tGP_1_16_DATA___4 = 41,\n\tGP_1_17_DATA___4 = 42,\n\tGP_1_18_DATA___4 = 43,\n\tGP_1_19_DATA___4 = 44,\n\tGP_1_20_DATA___4 = 45,\n\tGP_1_21_DATA___4 = 46,\n\tGP_1_22_DATA___4 = 47,\n\tGP_2_0_DATA___4 = 48,\n\tGP_2_1_DATA___4 = 49,\n\tGP_2_2_DATA___4 = 50,\n\tGP_2_3_DATA___4 = 51,\n\tGP_2_4_DATA___4 = 52,\n\tGP_2_5_DATA___4 = 53,\n\tGP_2_6_DATA___4 = 54,\n\tGP_2_7_DATA___4 = 55,\n\tGP_2_8_DATA___4 = 56,\n\tGP_2_9_DATA___4 = 57,\n\tGP_2_10_DATA___4 = 58,\n\tGP_2_11_DATA___4 = 59,\n\tGP_2_12_DATA___4 = 60,\n\tGP_2_13_DATA___4 = 61,\n\tGP_2_14_DATA___4 = 62,\n\tGP_2_15_DATA___4 = 63,\n\tGP_2_16_DATA___4 = 64,\n\tGP_2_17_DATA___4 = 65,\n\tGP_2_18_DATA___4 = 66,\n\tGP_2_19_DATA___4 = 67,\n\tGP_2_20_DATA___4 = 68,\n\tGP_2_21_DATA___4 = 69,\n\tGP_2_22_DATA___4 = 70,\n\tGP_2_23_DATA___4 = 71,\n\tGP_2_24_DATA___4 = 72,\n\tGP_2_25_DATA___4 = 73,\n\tGP_2_26_DATA___4 = 74,\n\tGP_2_27_DATA___4 = 75,\n\tGP_2_28_DATA___4 = 76,\n\tGP_2_29_DATA___4 = 77,\n\tGP_2_30_DATA___4 = 78,\n\tGP_2_31_DATA___4 = 79,\n\tGP_3_0_DATA___4 = 80,\n\tGP_3_1_DATA___4 = 81,\n\tGP_3_2_DATA___4 = 82,\n\tGP_3_3_DATA___4 = 83,\n\tGP_3_4_DATA___4 = 84,\n\tGP_3_5_DATA___4 = 85,\n\tGP_3_6_DATA___4 = 86,\n\tGP_3_7_DATA___4 = 87,\n\tGP_3_8_DATA___4 = 88,\n\tGP_3_9_DATA___4 = 89,\n\tGP_3_10_DATA___4 = 90,\n\tGP_3_11_DATA___4 = 91,\n\tGP_3_12_DATA___4 = 92,\n\tGP_3_13_DATA___4 = 93,\n\tGP_3_14_DATA___4 = 94,\n\tGP_3_15_DATA___4 = 95,\n\tGP_3_16_DATA___4 = 96,\n\tGP_3_27_DATA___4 = 97,\n\tGP_3_28_DATA___4 = 98,\n\tGP_3_29_DATA___4 = 99,\n\tGP_4_0_DATA___4 = 100,\n\tGP_4_1_DATA___4 = 101,\n\tGP_4_2_DATA___4 = 102,\n\tGP_4_3_DATA___4 = 103,\n\tGP_4_4_DATA___4 = 104,\n\tGP_4_5_DATA___4 = 105,\n\tGP_4_6_DATA___4 = 106,\n\tGP_4_7_DATA___4 = 107,\n\tGP_4_8_DATA___4 = 108,\n\tGP_4_9_DATA___4 = 109,\n\tGP_4_10_DATA___4 = 110,\n\tGP_4_11_DATA___4 = 111,\n\tGP_4_12_DATA___4 = 112,\n\tGP_4_13_DATA___4 = 113,\n\tGP_4_14_DATA___4 = 114,\n\tGP_4_15_DATA___4 = 115,\n\tGP_4_16_DATA___4 = 116,\n\tGP_4_17_DATA___4 = 117,\n\tGP_4_18_DATA___4 = 118,\n\tGP_4_19_DATA___4 = 119,\n\tGP_4_20_DATA___4 = 120,\n\tGP_4_21_DATA___4 = 121,\n\tGP_4_22_DATA___4 = 122,\n\tGP_4_23_DATA___4 = 123,\n\tGP_4_24_DATA___4 = 124,\n\tGP_4_25_DATA___4 = 125,\n\tGP_5_0_DATA___4 = 126,\n\tGP_5_1_DATA___4 = 127,\n\tGP_5_2_DATA___4 = 128,\n\tGP_5_3_DATA___4 = 129,\n\tGP_5_4_DATA___4 = 130,\n\tGP_5_5_DATA___4 = 131,\n\tGP_5_6_DATA___4 = 132,\n\tGP_5_7_DATA___4 = 133,\n\tGP_5_8_DATA___4 = 134,\n\tGP_5_9_DATA___4 = 135,\n\tGP_5_10_DATA___4 = 136,\n\tGP_5_11_DATA___4 = 137,\n\tGP_5_12_DATA___4 = 138,\n\tGP_5_13_DATA___4 = 139,\n\tGP_5_14_DATA___4 = 140,\n\tGP_5_15_DATA___4 = 141,\n\tGP_5_16_DATA___4 = 142,\n\tGP_5_17_DATA___4 = 143,\n\tGP_5_18_DATA___4 = 144,\n\tGP_5_19_DATA___4 = 145,\n\tGP_5_20_DATA___4 = 146,\n\tGP_5_21_DATA___4 = 147,\n\tGP_5_22_DATA___4 = 148,\n\tGP_5_23_DATA___4 = 149,\n\tGP_5_24_DATA___4 = 150,\n\tGP_5_25_DATA___4 = 151,\n\tGP_5_26_DATA___4 = 152,\n\tGP_5_27_DATA___4 = 153,\n\tGP_5_28_DATA___3 = 154,\n\tGP_5_29_DATA___3 = 155,\n\tGP_5_30_DATA___3 = 156,\n\tGP_5_31_DATA___3 = 157,\n\tPINMUX_DATA_END___7 = 158,\n\tPINMUX_FUNCTION_BEGIN___7 = 159,\n\tGP_0_0_FN___4 = 160,\n\tGP_0_1_FN___4 = 161,\n\tGP_0_2_FN___4 = 162,\n\tGP_0_3_FN___4 = 163,\n\tGP_0_4_FN___4 = 164,\n\tGP_0_5_FN___4 = 165,\n\tGP_0_6_FN___4 = 166,\n\tGP_0_7_FN___4 = 167,\n\tGP_0_8_FN___4 = 168,\n\tGP_0_9_FN___4 = 169,\n\tGP_0_10_FN___4 = 170,\n\tGP_0_11_FN___4 = 171,\n\tGP_0_12_FN___4 = 172,\n\tGP_0_13_FN___4 = 173,\n\tGP_0_14_FN___4 = 174,\n\tGP_0_15_FN___4 = 175,\n\tGP_0_16_FN___4 = 176,\n\tGP_0_17_FN___4 = 177,\n\tGP_0_18_FN___4 = 178,\n\tGP_0_19_FN___4 = 179,\n\tGP_0_20_FN___4 = 180,\n\tGP_0_21_FN___4 = 181,\n\tGP_0_22_FN___4 = 182,\n\tGP_1_0_FN___4 = 183,\n\tGP_1_1_FN___4 = 184,\n\tGP_1_2_FN___4 = 185,\n\tGP_1_3_FN___4 = 186,\n\tGP_1_4_FN___4 = 187,\n\tGP_1_5_FN___4 = 188,\n\tGP_1_6_FN___4 = 189,\n\tGP_1_7_FN___4 = 190,\n\tGP_1_8_FN___4 = 191,\n\tGP_1_9_FN___4 = 192,\n\tGP_1_10_FN___4 = 193,\n\tGP_1_11_FN___4 = 194,\n\tGP_1_12_FN___4 = 195,\n\tGP_1_13_FN___4 = 196,\n\tGP_1_14_FN___4 = 197,\n\tGP_1_15_FN___4 = 198,\n\tGP_1_16_FN___4 = 199,\n\tGP_1_17_FN___4 = 200,\n\tGP_1_18_FN___4 = 201,\n\tGP_1_19_FN___4 = 202,\n\tGP_1_20_FN___4 = 203,\n\tGP_1_21_FN___4 = 204,\n\tGP_1_22_FN___4 = 205,\n\tGP_2_0_FN___4 = 206,\n\tGP_2_1_FN___4 = 207,\n\tGP_2_2_FN___4 = 208,\n\tGP_2_3_FN___4 = 209,\n\tGP_2_4_FN___4 = 210,\n\tGP_2_5_FN___4 = 211,\n\tGP_2_6_FN___4 = 212,\n\tGP_2_7_FN___4 = 213,\n\tGP_2_8_FN___4 = 214,\n\tGP_2_9_FN___4 = 215,\n\tGP_2_10_FN___4 = 216,\n\tGP_2_11_FN___4 = 217,\n\tGP_2_12_FN___4 = 218,\n\tGP_2_13_FN___4 = 219,\n\tGP_2_14_FN___4 = 220,\n\tGP_2_15_FN___4 = 221,\n\tGP_2_16_FN___4 = 222,\n\tGP_2_17_FN___4 = 223,\n\tGP_2_18_FN___4 = 224,\n\tGP_2_19_FN___4 = 225,\n\tGP_2_20_FN___4 = 226,\n\tGP_2_21_FN___4 = 227,\n\tGP_2_22_FN___4 = 228,\n\tGP_2_23_FN___4 = 229,\n\tGP_2_24_FN___4 = 230,\n\tGP_2_25_FN___4 = 231,\n\tGP_2_26_FN___4 = 232,\n\tGP_2_27_FN___4 = 233,\n\tGP_2_28_FN___4 = 234,\n\tGP_2_29_FN___4 = 235,\n\tGP_2_30_FN___4 = 236,\n\tGP_2_31_FN___4 = 237,\n\tGP_3_0_FN___4 = 238,\n\tGP_3_1_FN___4 = 239,\n\tGP_3_2_FN___4 = 240,\n\tGP_3_3_FN___4 = 241,\n\tGP_3_4_FN___4 = 242,\n\tGP_3_5_FN___4 = 243,\n\tGP_3_6_FN___4 = 244,\n\tGP_3_7_FN___4 = 245,\n\tGP_3_8_FN___4 = 246,\n\tGP_3_9_FN___4 = 247,\n\tGP_3_10_FN___4 = 248,\n\tGP_3_11_FN___4 = 249,\n\tGP_3_12_FN___4 = 250,\n\tGP_3_13_FN___4 = 251,\n\tGP_3_14_FN___4 = 252,\n\tGP_3_15_FN___4 = 253,\n\tGP_3_16_FN___4 = 254,\n\tGP_3_27_FN___4 = 255,\n\tGP_3_28_FN___4 = 256,\n\tGP_3_29_FN___4 = 257,\n\tGP_4_0_FN___4 = 258,\n\tGP_4_1_FN___4 = 259,\n\tGP_4_2_FN___4 = 260,\n\tGP_4_3_FN___4 = 261,\n\tGP_4_4_FN___4 = 262,\n\tGP_4_5_FN___4 = 263,\n\tGP_4_6_FN___4 = 264,\n\tGP_4_7_FN___4 = 265,\n\tGP_4_8_FN___4 = 266,\n\tGP_4_9_FN___4 = 267,\n\tGP_4_10_FN___4 = 268,\n\tGP_4_11_FN___4 = 269,\n\tGP_4_12_FN___4 = 270,\n\tGP_4_13_FN___4 = 271,\n\tGP_4_14_FN___4 = 272,\n\tGP_4_15_FN___4 = 273,\n\tGP_4_16_FN___4 = 274,\n\tGP_4_17_FN___4 = 275,\n\tGP_4_18_FN___4 = 276,\n\tGP_4_19_FN___4 = 277,\n\tGP_4_20_FN___4 = 278,\n\tGP_4_21_FN___4 = 279,\n\tGP_4_22_FN___4 = 280,\n\tGP_4_23_FN___4 = 281,\n\tGP_4_24_FN___4 = 282,\n\tGP_4_25_FN___4 = 283,\n\tGP_5_0_FN___4 = 284,\n\tGP_5_1_FN___4 = 285,\n\tGP_5_2_FN___4 = 286,\n\tGP_5_3_FN___4 = 287,\n\tGP_5_4_FN___4 = 288,\n\tGP_5_5_FN___4 = 289,\n\tGP_5_6_FN___4 = 290,\n\tGP_5_7_FN___4 = 291,\n\tGP_5_8_FN___4 = 292,\n\tGP_5_9_FN___4 = 293,\n\tGP_5_10_FN___4 = 294,\n\tGP_5_11_FN___4 = 295,\n\tGP_5_12_FN___4 = 296,\n\tGP_5_13_FN___4 = 297,\n\tGP_5_14_FN___4 = 298,\n\tGP_5_15_FN___4 = 299,\n\tGP_5_16_FN___4 = 300,\n\tGP_5_17_FN___4 = 301,\n\tGP_5_18_FN___4 = 302,\n\tGP_5_19_FN___4 = 303,\n\tGP_5_20_FN___4 = 304,\n\tGP_5_21_FN___4 = 305,\n\tGP_5_22_FN___4 = 306,\n\tGP_5_23_FN___4 = 307,\n\tGP_5_24_FN___4 = 308,\n\tGP_5_25_FN___4 = 309,\n\tGP_5_26_FN___4 = 310,\n\tGP_5_27_FN___4 = 311,\n\tGP_5_28_FN___3 = 312,\n\tGP_5_29_FN___3 = 313,\n\tGP_5_30_FN___3 = 314,\n\tGP_5_31_FN___3 = 315,\n\tFN_USB0_PWEN___3 = 316,\n\tFN_USB0_OVC___3 = 317,\n\tFN_USB1_PWEN___3 = 318,\n\tFN_USB1_OVC___3 = 319,\n\tFN_CLKOUT___2 = 320,\n\tFN_IP0_3_0 = 321,\n\tFN_IP0_7_4 = 322,\n\tFN_IP0_11_8 = 323,\n\tFN_IP0_15_12 = 324,\n\tFN_IP0_19_16 = 325,\n\tFN_IP0_23_20 = 326,\n\tFN_IP0_27_24 = 327,\n\tFN_IP0_31_28 = 328,\n\tFN_MMC0_CLK_SDHI1_CLK = 329,\n\tFN_MMC0_CMD_SDHI1_CMD = 330,\n\tFN_MMC0_D0_SDHI1_D0 = 331,\n\tFN_MMC0_D1_SDHI1_D1 = 332,\n\tFN_MMC0_D2_SDHI1_D2 = 333,\n\tFN_MMC0_D3_SDHI1_D3 = 334,\n\tFN_IP1_3_0 = 335,\n\tFN_IP1_7_4 = 336,\n\tFN_MMC0_D6___2 = 337,\n\tFN_MMC0_D7___2 = 338,\n\tFN_IP1_11_8 = 339,\n\tFN_IP1_15_12 = 340,\n\tFN_IP1_19_16 = 341,\n\tFN_IP1_23_20 = 342,\n\tFN_IP1_27_24 = 343,\n\tFN_IP1_31_28 = 344,\n\tFN_IP2_3_0___2 = 345,\n\tFN_IP2_7_4___2 = 346,\n\tFN_IP2_11_8___2 = 347,\n\tFN_IP2_15_12___2 = 348,\n\tFN_IP2_19_16 = 349,\n\tFN_IP2_23_20 = 350,\n\tFN_IP2_27_24 = 351,\n\tFN_IP2_31_28 = 352,\n\tFN_IP3_3_0 = 353,\n\tFN_IP3_7_4 = 354,\n\tFN_IP3_11_8 = 355,\n\tFN_IP3_15_12 = 356,\n\tFN_IP3_19_16 = 357,\n\tFN_IP3_23_20 = 358,\n\tFN_IP3_27_24 = 359,\n\tFN_IP3_31_28 = 360,\n\tFN_IP4_3_0 = 361,\n\tFN_IP4_7_4 = 362,\n\tFN_IP4_11_8 = 363,\n\tFN_IP4_15_12 = 364,\n\tFN_IP4_19_16 = 365,\n\tFN_IP4_23_20 = 366,\n\tFN_IP4_27_24 = 367,\n\tFN_IP4_31_28 = 368,\n\tFN_IP5_3_0 = 369,\n\tFN_IP5_7_4 = 370,\n\tFN_IP5_11_8 = 371,\n\tFN_IP5_15_12 = 372,\n\tFN_IP5_19_16 = 373,\n\tFN_IP5_23_20 = 374,\n\tFN_IP5_27_24___2 = 375,\n\tFN_IP5_31_28 = 376,\n\tFN_IP6_3_0 = 377,\n\tFN_IP6_7_4 = 378,\n\tFN_IP6_11_8 = 379,\n\tFN_IP6_15_12 = 380,\n\tFN_IP6_19_16 = 381,\n\tFN_IP6_23_20 = 382,\n\tFN_IP6_27_24 = 383,\n\tFN_IP6_31_28 = 384,\n\tFN_IP7_3_0 = 385,\n\tFN_IP7_7_4 = 386,\n\tFN_IP7_11_8 = 387,\n\tFN_IP7_15_12 = 388,\n\tFN_IP7_19_16 = 389,\n\tFN_IP7_23_20 = 390,\n\tFN_IP7_27_24 = 391,\n\tFN_IP7_31_28 = 392,\n\tFN_IP8_3_0___2 = 393,\n\tFN_IP8_7_4___2 = 394,\n\tFN_IP8_11_8___2 = 395,\n\tFN_IP8_15_12___2 = 396,\n\tFN_IP8_19_16 = 397,\n\tFN_IP8_23_20 = 398,\n\tFN_IP8_27_24 = 399,\n\tFN_IP8_31_28 = 400,\n\tFN_IP9_3_0 = 401,\n\tFN_IP9_7_4 = 402,\n\tFN_IP9_11_8 = 403,\n\tFN_IP9_15_12 = 404,\n\tFN_IP9_19_16 = 405,\n\tFN_IP9_23_20 = 406,\n\tFN_IP9_27_24 = 407,\n\tFN_IP9_31_28 = 408,\n\tFN_IP10_3_0 = 409,\n\tFN_IP10_7_4 = 410,\n\tFN_IP10_11_8 = 411,\n\tFN_IP10_15_12 = 412,\n\tFN_IP10_19_16 = 413,\n\tFN_IP10_23_20 = 414,\n\tFN_IP10_27_24 = 415,\n\tFN_IP10_31_28 = 416,\n\tFN_IP11_3_0 = 417,\n\tFN_IP11_7_4 = 418,\n\tFN_IP11_11_8 = 419,\n\tFN_IP11_15_12 = 420,\n\tFN_IP11_19_16 = 421,\n\tFN_IP11_23_20 = 422,\n\tFN_IP11_27_24 = 423,\n\tFN_IP11_31_28 = 424,\n\tFN_IP12_3_0 = 425,\n\tFN_IP12_7_4 = 426,\n\tFN_IP12_11_8 = 427,\n\tFN_IP12_15_12 = 428,\n\tFN_IP12_19_16 = 429,\n\tFN_IP12_23_20 = 430,\n\tFN_IP12_27_24 = 431,\n\tFN_IP12_31_28 = 432,\n\tFN_IP13_3_0 = 433,\n\tFN_IP13_7_4 = 434,\n\tFN_IP13_11_8 = 435,\n\tFN_IP13_15_12 = 436,\n\tFN_IP13_19_16 = 437,\n\tFN_IP13_23_20 = 438,\n\tFN_IP13_27_24 = 439,\n\tFN_IP13_31_28 = 440,\n\tFN_IP14_3_0 = 441,\n\tFN_IP14_7_4 = 442,\n\tFN_IP14_11_8 = 443,\n\tFN_IP14_15_12 = 444,\n\tFN_IP14_19_16 = 445,\n\tFN_IP14_23_20 = 446,\n\tFN_IP14_27_24 = 447,\n\tFN_IP14_31_28 = 448,\n\tFN_IP15_3_0 = 449,\n\tFN_IP15_7_4 = 450,\n\tFN_IP15_11_8 = 451,\n\tFN_IP15_15_12 = 452,\n\tFN_IP15_19_16 = 453,\n\tFN_IP15_23_20 = 454,\n\tFN_IP15_27_24 = 455,\n\tFN_IP15_31_28 = 456,\n\tFN_IP16_3_0 = 457,\n\tFN_IP16_7_4 = 458,\n\tFN_IP16_11_8 = 459,\n\tFN_IP16_15_12 = 460,\n\tFN_IP16_19_16 = 461,\n\tFN_IP16_23_20 = 462,\n\tFN_IP16_27_24 = 463,\n\tFN_IP16_31_28 = 464,\n\tFN_IP17_3_0 = 465,\n\tFN_IP17_7_4 = 466,\n\tFN_IP17_11_8 = 467,\n\tFN_IP17_15_12 = 468,\n\tFN_IP17_19_16 = 469,\n\tFN_IP17_23_20 = 470,\n\tFN_IP17_27_24 = 471,\n\tFN_SD0_CLK___4 = 472,\n\tFN_SSI_SCK1_C = 473,\n\tFN_RX3_C___2 = 474,\n\tFN_SD0_CMD___4 = 475,\n\tFN_SSI_WS1_C = 476,\n\tFN_TX3_C___2 = 477,\n\tFN_SD0_DAT0___2 = 478,\n\tFN_SSI_SDATA1_C = 479,\n\tFN_RX4_E = 480,\n\tFN_SD0_DAT1___2 = 481,\n\tFN_SSI_SCK0129_B___2 = 482,\n\tFN_TX4_E = 483,\n\tFN_SD0_DAT2___2 = 484,\n\tFN_SSI_WS0129_B___2 = 485,\n\tFN_RX5_E = 486,\n\tFN_SD0_DAT3___2 = 487,\n\tFN_SSI_SDATA0_B___2 = 488,\n\tFN_TX5_E = 489,\n\tFN_SD0_CD___4 = 490,\n\tFN_CAN0_RX_A = 491,\n\tFN_SD0_WP___4 = 492,\n\tFN_IRQ7___3 = 493,\n\tFN_CAN0_TX_A = 494,\n\tFN_MMC0_D4___2 = 495,\n\tFN_SD1_CD___4 = 496,\n\tFN_MMC0_D5___2 = 497,\n\tFN_SD1_WP___4 = 498,\n\tFN_D0___3 = 499,\n\tFN_SCL3_B___2 = 500,\n\tFN_RX5_B___3 = 501,\n\tFN_IRQ4___3 = 502,\n\tFN_MSIOF2_RXD_C___2 = 503,\n\tFN_SSI_SDATA5_B___2 = 504,\n\tFN_D1___3 = 505,\n\tFN_SDA3_B___2 = 506,\n\tFN_TX5_B___3 = 507,\n\tFN_MSIOF2_TXD_C___2 = 508,\n\tFN_SSI_WS5_B___2 = 509,\n\tFN_D2___3 = 510,\n\tFN_RX4_B___3 = 511,\n\tFN_SCL0_D = 512,\n\tFN_PWM1_C___2 = 513,\n\tFN_MSIOF2_SCK_C___2 = 514,\n\tFN_SSI_SCK5_B___2 = 515,\n\tFN_D3___3 = 516,\n\tFN_TX4_B___3 = 517,\n\tFN_SDA0_D = 518,\n\tFN_PWM0_A = 519,\n\tFN_MSIOF2_SYNC_C___2 = 520,\n\tFN_D4___3 = 521,\n\tFN_IRQ3___4 = 522,\n\tFN_TCLK1_A = 523,\n\tFN_PWM6_C = 524,\n\tFN_D5___3 = 525,\n\tFN_HRX2___2 = 526,\n\tFN_SCL1_B___2 = 527,\n\tFN_PWM2_C___2 = 528,\n\tFN_TCLK2_B___2 = 529,\n\tFN_D6___3 = 530,\n\tFN_HTX2___2 = 531,\n\tFN_SDA1_B___2 = 532,\n\tFN_PWM4_C = 533,\n\tFN_D7___3 = 534,\n\tFN_HSCK2___2 = 535,\n\tFN_SCIF1_SCK_C___2 = 536,\n\tFN_IRQ6___3 = 537,\n\tFN_PWM5_C___2 = 538,\n\tFN_D8___3 = 539,\n\tFN_HCTS2_N___2 = 540,\n\tFN_RX1_C___3 = 541,\n\tFN_SCL1_D___2 = 542,\n\tFN_PWM3_C = 543,\n\tFN_D9___3 = 544,\n\tFN_HRTS2_N___2 = 545,\n\tFN_TX1_C___3 = 546,\n\tFN_SDA1_D___2 = 547,\n\tFN_D10___3 = 548,\n\tFN_MSIOF2_RXD_A = 549,\n\tFN_HRX0_B___3 = 550,\n\tFN_D11___3 = 551,\n\tFN_MSIOF2_TXD_A = 552,\n\tFN_HTX0_B___3 = 553,\n\tFN_D12___3 = 554,\n\tFN_MSIOF2_SCK_A = 555,\n\tFN_HSCK0___3 = 556,\n\tFN_CAN_CLK_C___4 = 557,\n\tFN_D13___3 = 558,\n\tFN_MSIOF2_SYNC_A = 559,\n\tFN_RX4_C___3 = 560,\n\tFN_D14___3 = 561,\n\tFN_MSIOF2_SS1___3 = 562,\n\tFN_TX4_C___3 = 563,\n\tFN_CAN1_RX_B___3 = 564,\n\tFN_AVB_AVTP_CAPTURE_A = 565,\n\tFN_D15___3 = 566,\n\tFN_MSIOF2_SS2___3 = 567,\n\tFN_PWM4_A = 568,\n\tFN_CAN1_TX_B___3 = 569,\n\tFN_IRQ2___4 = 570,\n\tFN_AVB_AVTP_MATCH_A = 571,\n\tFN_QSPI0_SPCLK = 572,\n\tFN_WE0_N___3 = 573,\n\tFN_QSPI0_MOSI_QSPI0_IO0 = 574,\n\tFN_BS_N___3 = 575,\n\tFN_QSPI0_MISO_QSPI0_IO1 = 576,\n\tFN_RD_WR_N___3 = 577,\n\tFN_QSPI0_IO2 = 578,\n\tFN_CS0_N___3 = 579,\n\tFN_QSPI0_IO3 = 580,\n\tFN_RD_N___3 = 581,\n\tFN_QSPI0_SSL = 582,\n\tFN_WE1_N___3 = 583,\n\tFN_EX_WAIT0___4 = 584,\n\tFN_CAN_CLK_B___4 = 585,\n\tFN_SCIF_CLK_A = 586,\n\tFN_DU0_DR0___3 = 587,\n\tFN_RX5_C___2 = 588,\n\tFN_SCL2_D___2 = 589,\n\tFN_A0___4 = 590,\n\tFN_DU0_DR1___3 = 591,\n\tFN_TX5_C___2 = 592,\n\tFN_SDA2_D___2 = 593,\n\tFN_A1___4 = 594,\n\tFN_DU0_DR2___3 = 595,\n\tFN_RX0_D___3 = 596,\n\tFN_SCL0_E = 597,\n\tFN_A2___4 = 598,\n\tFN_DU0_DR3___3 = 599,\n\tFN_TX0_D___3 = 600,\n\tFN_SDA0_E = 601,\n\tFN_PWM0_B___4 = 602,\n\tFN_A3___4 = 603,\n\tFN_DU0_DR4___3 = 604,\n\tFN_RX1_D___2 = 605,\n\tFN_A4___4 = 606,\n\tFN_DU0_DR5___3 = 607,\n\tFN_TX1_D___2 = 608,\n\tFN_PWM1_B___3 = 609,\n\tFN_A5___4 = 610,\n\tFN_DU0_DR6___3 = 611,\n\tFN_RX2_C___3 = 612,\n\tFN_A6___4 = 613,\n\tFN_DU0_DR7___3 = 614,\n\tFN_TX2_C___3 = 615,\n\tFN_PWM2_B___3 = 616,\n\tFN_A7___4 = 617,\n\tFN_DU0_DG0___3 = 618,\n\tFN_RX3_B___2 = 619,\n\tFN_SCL3_D = 620,\n\tFN_A8___4 = 621,\n\tFN_DU0_DG1___3 = 622,\n\tFN_TX3_B___2 = 623,\n\tFN_SDA3_D = 624,\n\tFN_PWM3_B___2 = 625,\n\tFN_A9___4 = 626,\n\tFN_DU0_DG2___3 = 627,\n\tFN_RX4_D___2 = 628,\n\tFN_A10___4 = 629,\n\tFN_DU0_DG3___3 = 630,\n\tFN_TX4_D___2 = 631,\n\tFN_PWM4_B___3 = 632,\n\tFN_A11___4 = 633,\n\tFN_DU0_DG4___3 = 634,\n\tFN_HRX0_A = 635,\n\tFN_A12___4 = 636,\n\tFN_DU0_DG5___3 = 637,\n\tFN_HTX0_A = 638,\n\tFN_PWM5_B___3 = 639,\n\tFN_A13___4 = 640,\n\tFN_DU0_DG6___3 = 641,\n\tFN_HRX1_C___2 = 642,\n\tFN_A14___4 = 643,\n\tFN_DU0_DG7___3 = 644,\n\tFN_HTX1_C___2 = 645,\n\tFN_PWM6_B___2 = 646,\n\tFN_A15___4 = 647,\n\tFN_DU0_DB0___3 = 648,\n\tFN_SCL4_D = 649,\n\tFN_CAN0_RX_C___3 = 650,\n\tFN_A16___4 = 651,\n\tFN_DU0_DB1___3 = 652,\n\tFN_SDA4_D = 653,\n\tFN_CAN0_TX_C___3 = 654,\n\tFN_A17___4 = 655,\n\tFN_DU0_DB2___3 = 656,\n\tFN_HCTS0_N___2 = 657,\n\tFN_A18___4 = 658,\n\tFN_DU0_DB3___3 = 659,\n\tFN_HRTS0_N___2 = 660,\n\tFN_A19___4 = 661,\n\tFN_DU0_DB4___3 = 662,\n\tFN_HCTS1_N_C___2 = 663,\n\tFN_A20___4 = 664,\n\tFN_DU0_DB5___3 = 665,\n\tFN_HRTS1_N_C___2 = 666,\n\tFN_A21___4 = 667,\n\tFN_DU0_DB6___3 = 668,\n\tFN_A22___4 = 669,\n\tFN_DU0_DB7___3 = 670,\n\tFN_A23___4 = 671,\n\tFN_DU0_DOTCLKIN___4 = 672,\n\tFN_A24___4 = 673,\n\tFN_DU0_DOTCLKOUT0___3 = 674,\n\tFN_A25___4 = 675,\n\tFN_DU0_DOTCLKOUT1___3 = 676,\n\tFN_MSIOF2_RXD_B___3 = 677,\n\tFN_CS1_N_A26___3 = 678,\n\tFN_DU0_EXHSYNC_DU0_HSYNC___3 = 679,\n\tFN_MSIOF2_TXD_B___3 = 680,\n\tFN_DREQ0_N___2 = 681,\n\tFN_DU0_EXVSYNC_DU0_VSYNC___3 = 682,\n\tFN_MSIOF2_SYNC_B___3 = 683,\n\tFN_DACK0___4 = 684,\n\tFN_DU0_EXODDF_DU0_ODDF_DISP_CDE___3 = 685,\n\tFN_MSIOF2_SCK_B___3 = 686,\n\tFN_DRACK0___4 = 687,\n\tFN_DU0_DISP___3 = 688,\n\tFN_CAN1_RX_C___3 = 689,\n\tFN_DU0_CDE___3 = 690,\n\tFN_CAN1_TX_C___3 = 691,\n\tFN_VI1_CLK___4 = 692,\n\tFN_AVB_RX_CLK___3 = 693,\n\tFN_ETH_REF_CLK = 694,\n\tFN_VI1_DATA0___3 = 695,\n\tFN_AVB_RX_DV___3 = 696,\n\tFN_ETH_CRS_DV___4 = 697,\n\tFN_VI1_DATA1___3 = 698,\n\tFN_AVB_RXD0___3 = 699,\n\tFN_ETH_RXD0___4 = 700,\n\tFN_VI1_DATA2___3 = 701,\n\tFN_AVB_RXD1___3 = 702,\n\tFN_ETH_RXD1___4 = 703,\n\tFN_VI1_DATA3___3 = 704,\n\tFN_AVB_RXD2___3 = 705,\n\tFN_ETH_MDIO___4 = 706,\n\tFN_VI1_DATA4___3 = 707,\n\tFN_AVB_RXD3___3 = 708,\n\tFN_ETH_RX_ER___4 = 709,\n\tFN_VI1_DATA5___3 = 710,\n\tFN_AVB_RXD4___3 = 711,\n\tFN_ETH_LINK___4 = 712,\n\tFN_VI1_DATA6___3 = 713,\n\tFN_AVB_RXD5___3 = 714,\n\tFN_ETH_TXD1___4 = 715,\n\tFN_VI1_DATA7___3 = 716,\n\tFN_AVB_RXD6___3 = 717,\n\tFN_ETH_TX_EN___4 = 718,\n\tFN_VI1_CLKENB___4 = 719,\n\tFN_SCL3_A = 720,\n\tFN_AVB_RXD7___3 = 721,\n\tFN_ETH_MAGIC___4 = 722,\n\tFN_VI1_FIELD___4 = 723,\n\tFN_SDA3_A = 724,\n\tFN_AVB_RX_ER___3 = 725,\n\tFN_ETH_TXD0___4 = 726,\n\tFN_VI1_HSYNC_N___3 = 727,\n\tFN_RX0_B___3 = 728,\n\tFN_SCL0_C = 729,\n\tFN_AVB_GTXREFCLK___3 = 730,\n\tFN_ETH_MDC___4 = 731,\n\tFN_VI1_VSYNC_N___3 = 732,\n\tFN_TX0_B___3 = 733,\n\tFN_SDA0_C = 734,\n\tFN_AUDIO_CLKOUT_B___3 = 735,\n\tFN_AVB_TX_CLK___3 = 736,\n\tFN_VI1_DATA8___2 = 737,\n\tFN_SCL2_B___2 = 738,\n\tFN_AVB_TX_EN___3 = 739,\n\tFN_VI1_DATA9___2 = 740,\n\tFN_SDA2_B___2 = 741,\n\tFN_AVB_TXD0___3 = 742,\n\tFN_VI1_DATA10___2 = 743,\n\tFN_CAN0_RX_B___4 = 744,\n\tFN_AVB_TXD1___3 = 745,\n\tFN_VI1_DATA11___2 = 746,\n\tFN_CAN0_TX_B___4 = 747,\n\tFN_AVB_TXD2___3 = 748,\n\tFN_AVB_TXD3___3 = 749,\n\tFN_AUDIO_CLKA_B___2 = 750,\n\tFN_SSI_SCK1_D = 751,\n\tFN_RX5_F = 752,\n\tFN_MSIOF0_RXD_B___2 = 753,\n\tFN_AVB_TXD4___3 = 754,\n\tFN_AUDIO_CLKB_B___3 = 755,\n\tFN_SSI_WS1_D = 756,\n\tFN_TX5_F = 757,\n\tFN_MSIOF0_TXD_B___2 = 758,\n\tFN_AVB_TXD5___3 = 759,\n\tFN_SCIF_CLK_B___4 = 760,\n\tFN_AUDIO_CLKC_B___2 = 761,\n\tFN_SSI_SDATA1_D = 762,\n\tFN_MSIOF0_SCK_B___2 = 763,\n\tFN_SCL0_A = 764,\n\tFN_RX0_C___3 = 765,\n\tFN_PWM5_A = 766,\n\tFN_TCLK1_B___4 = 767,\n\tFN_AVB_TXD6___3 = 768,\n\tFN_CAN1_RX_D___3 = 769,\n\tFN_MSIOF0_SYNC_B___2 = 770,\n\tFN_SDA0_A = 771,\n\tFN_TX0_C___3 = 772,\n\tFN_IRQ5___3 = 773,\n\tFN_CAN_CLK_A = 774,\n\tFN_AVB_GTX_CLK___3 = 775,\n\tFN_CAN1_TX_D___3 = 776,\n\tFN_DVC_MUTE___3 = 777,\n\tFN_SCL1_A = 778,\n\tFN_RX4_A = 779,\n\tFN_PWM5_D = 780,\n\tFN_DU1_DR0___4 = 781,\n\tFN_SSI_SCK6_B___2 = 782,\n\tFN_VI0_G0___4 = 783,\n\tFN_SDA1_A = 784,\n\tFN_TX4_A = 785,\n\tFN_DU1_DR1___4 = 786,\n\tFN_SSI_WS6_B___2 = 787,\n\tFN_VI0_G1___4 = 788,\n\tFN_MSIOF0_RXD_A = 789,\n\tFN_RX5_A = 790,\n\tFN_SCL2_C___2 = 791,\n\tFN_DU1_DR2___4 = 792,\n\tFN_QSPI1_MOSI_QSPI1_IO0 = 793,\n\tFN_SSI_SDATA6_B___2 = 794,\n\tFN_VI0_G2___4 = 795,\n\tFN_MSIOF0_TXD_A = 796,\n\tFN_TX5_A = 797,\n\tFN_SDA2_C___2 = 798,\n\tFN_DU1_DR3___4 = 799,\n\tFN_QSPI1_MISO_QSPI1_IO1 = 800,\n\tFN_SSI_WS78_B___4 = 801,\n\tFN_VI0_G3___4 = 802,\n\tFN_MSIOF0_SCK_A = 803,\n\tFN_IRQ0___4 = 804,\n\tFN_DU1_DR4___4 = 805,\n\tFN_QSPI1_SPCLK = 806,\n\tFN_SSI_SCK78_B___4 = 807,\n\tFN_VI0_G4___4 = 808,\n\tFN_MSIOF0_SYNC_A = 809,\n\tFN_PWM1_A = 810,\n\tFN_DU1_DR5___4 = 811,\n\tFN_QSPI1_IO2 = 812,\n\tFN_SSI_SDATA7_B___4 = 813,\n\tFN_MSIOF0_SS1_A = 814,\n\tFN_DU1_DR6___4 = 815,\n\tFN_QSPI1_IO3 = 816,\n\tFN_SSI_SDATA8_B___4 = 817,\n\tFN_MSIOF0_SS2_A = 818,\n\tFN_DU1_DR7___4 = 819,\n\tFN_QSPI1_SSL = 820,\n\tFN_HRX1_A = 821,\n\tFN_SCL4_A = 822,\n\tFN_PWM6_A = 823,\n\tFN_DU1_DG0___4 = 824,\n\tFN_RX0_A = 825,\n\tFN_HTX1_A = 826,\n\tFN_SDA4_A = 827,\n\tFN_DU1_DG1___4 = 828,\n\tFN_TX0_A = 829,\n\tFN_HCTS1_N_A = 830,\n\tFN_PWM2_A = 831,\n\tFN_DU1_DG2___4 = 832,\n\tFN_REMOCON_B___3 = 833,\n\tFN_HRTS1_N_A = 834,\n\tFN_DU1_DG3___4 = 835,\n\tFN_SSI_WS1_B___3 = 836,\n\tFN_IRQ1___4 = 837,\n\tFN_SD2_CLK___4 = 838,\n\tFN_HSCK1___3 = 839,\n\tFN_DU1_DG4___4 = 840,\n\tFN_SSI_SCK1_B___3 = 841,\n\tFN_SD2_CMD___4 = 842,\n\tFN_SCIF1_SCK_A = 843,\n\tFN_TCLK2_A = 844,\n\tFN_DU1_DG5___4 = 845,\n\tFN_SSI_SCK2_B___2 = 846,\n\tFN_PWM3_A = 847,\n\tFN_SD2_DAT0___2 = 848,\n\tFN_RX1_A = 849,\n\tFN_SCL1_E = 850,\n\tFN_DU1_DG6___4 = 851,\n\tFN_SSI_SDATA1_B___3 = 852,\n\tFN_SD2_DAT1___2 = 853,\n\tFN_TX1_A = 854,\n\tFN_SDA1_E = 855,\n\tFN_DU1_DG7___4 = 856,\n\tFN_SSI_WS2_B___2 = 857,\n\tFN_SD2_DAT2___2 = 858,\n\tFN_RX2_A = 859,\n\tFN_DU1_DB0___4 = 860,\n\tFN_SSI_SDATA2_B___2 = 861,\n\tFN_SD2_DAT3___2 = 862,\n\tFN_TX2_A = 863,\n\tFN_DU1_DB1___4 = 864,\n\tFN_SSI_WS9_B___4 = 865,\n\tFN_SD2_CD___4 = 866,\n\tFN_SCIF2_SCK_A = 867,\n\tFN_DU1_DB2___4 = 868,\n\tFN_SSI_SCK9_B___4 = 869,\n\tFN_SD2_WP___4 = 870,\n\tFN_SCIF3_SCK___3 = 871,\n\tFN_DU1_DB3___4 = 872,\n\tFN_SSI_SDATA9_B___4 = 873,\n\tFN_RX3_A = 874,\n\tFN_SCL1_C___2 = 875,\n\tFN_MSIOF1_RXD_B___3 = 876,\n\tFN_DU1_DB4___4 = 877,\n\tFN_AUDIO_CLKA_C___2 = 878,\n\tFN_SSI_SDATA4_B___2 = 879,\n\tFN_TX3_A = 880,\n\tFN_SDA1_C___2 = 881,\n\tFN_MSIOF1_TXD_B___3 = 882,\n\tFN_DU1_DB5___4 = 883,\n\tFN_AUDIO_CLKB_C___2 = 884,\n\tFN_SSI_WS4_B___2 = 885,\n\tFN_SCL2_A = 886,\n\tFN_MSIOF1_SCK_B___3 = 887,\n\tFN_DU1_DB6___4 = 888,\n\tFN_AUDIO_CLKC_C___2 = 889,\n\tFN_SSI_SCK4_B___2 = 890,\n\tFN_SDA2_A = 891,\n\tFN_MSIOF1_SYNC_B___3 = 892,\n\tFN_DU1_DB7___4 = 893,\n\tFN_AUDIO_CLKOUT_C___3 = 894,\n\tFN_SSI_SCK5_A = 895,\n\tFN_DU1_DOTCLKOUT1___3 = 896,\n\tFN_SSI_WS5_A = 897,\n\tFN_SCL3_C = 898,\n\tFN_DU1_DOTCLKIN___4 = 899,\n\tFN_SSI_SDATA5_A = 900,\n\tFN_SDA3_C = 901,\n\tFN_DU1_DOTCLKOUT0___3 = 902,\n\tFN_SSI_SCK6_A = 903,\n\tFN_DU1_EXODDF_DU1_ODDF_DISP_CDE___4 = 904,\n\tFN_SSI_WS6_A = 905,\n\tFN_SCL4_C = 906,\n\tFN_DU1_EXHSYNC_DU1_HSYNC___4 = 907,\n\tFN_SSI_SDATA6_A = 908,\n\tFN_SDA4_C = 909,\n\tFN_DU1_EXVSYNC_DU1_VSYNC___4 = 910,\n\tFN_SSI_SCK78_A = 911,\n\tFN_SDA4_E = 912,\n\tFN_DU1_DISP___4 = 913,\n\tFN_SSI_WS78_A = 914,\n\tFN_SCL4_E = 915,\n\tFN_DU1_CDE___4 = 916,\n\tFN_SSI_SDATA7_A = 917,\n\tFN_IRQ8___3 = 918,\n\tFN_AUDIO_CLKA_D___2 = 919,\n\tFN_CAN_CLK_D___3 = 920,\n\tFN_VI0_G5___4 = 921,\n\tFN_SSI_SCK0129_A = 922,\n\tFN_MSIOF1_RXD_A = 923,\n\tFN_RX5_D___2 = 924,\n\tFN_VI0_G6___4 = 925,\n\tFN_SSI_WS0129_A = 926,\n\tFN_MSIOF1_TXD_A = 927,\n\tFN_TX5_D___2 = 928,\n\tFN_VI0_G7___4 = 929,\n\tFN_SSI_SDATA0_A = 930,\n\tFN_MSIOF1_SYNC_A = 931,\n\tFN_PWM0_C___2 = 932,\n\tFN_VI0_R0___4 = 933,\n\tFN_SSI_SCK34___4 = 934,\n\tFN_MSIOF1_SCK_A = 935,\n\tFN_AVB_MDC___3 = 936,\n\tFN_DACK1___4 = 937,\n\tFN_VI0_R1___4 = 938,\n\tFN_SSI_WS34___4 = 939,\n\tFN_MSIOF1_SS1_A = 940,\n\tFN_AVB_MDIO___3 = 941,\n\tFN_CAN1_RX_A = 942,\n\tFN_DREQ1_N___2 = 943,\n\tFN_VI0_R2___4 = 944,\n\tFN_SSI_SDATA3___4 = 945,\n\tFN_MSIOF1_SS2_A = 946,\n\tFN_AVB_LINK___3 = 947,\n\tFN_CAN1_TX_A = 948,\n\tFN_DREQ2_N___2 = 949,\n\tFN_VI0_R3___4 = 950,\n\tFN_SSI_SCK4_A = 951,\n\tFN_AVB_MAGIC___3 = 952,\n\tFN_VI0_R4___4 = 953,\n\tFN_SSI_WS4_A = 954,\n\tFN_AVB_PHY_INT___3 = 955,\n\tFN_VI0_R5___4 = 956,\n\tFN_SSI_SDATA4_A = 957,\n\tFN_AVB_CRS___3 = 958,\n\tFN_VI0_R6___4 = 959,\n\tFN_SSI_SCK1_A = 960,\n\tFN_SCIF1_SCK_B___3 = 961,\n\tFN_PWM1_D = 962,\n\tFN_IRQ9___3 = 963,\n\tFN_REMOCON_A = 964,\n\tFN_DACK2___4 = 965,\n\tFN_VI0_CLK___4 = 966,\n\tFN_AVB_COL___3 = 967,\n\tFN_SSI_SDATA8_A = 968,\n\tFN_RX1_B___3 = 969,\n\tFN_CAN0_RX_D___3 = 970,\n\tFN_AVB_AVTP_CAPTURE_B = 971,\n\tFN_VI0_R7___4 = 972,\n\tFN_SSI_WS1_A = 973,\n\tFN_TX1_B___3 = 974,\n\tFN_CAN0_TX_D___3 = 975,\n\tFN_AVB_AVTP_MATCH_B = 976,\n\tFN_VI0_DATA0_VI0_B0___4 = 977,\n\tFN_SSI_SDATA1_A = 978,\n\tFN_HRX1_B___3 = 979,\n\tFN_VI0_DATA1_VI0_B1___4 = 980,\n\tFN_SSI_SCK2_A = 981,\n\tFN_HTX1_B___3 = 982,\n\tFN_AVB_TXD7___3 = 983,\n\tFN_VI0_DATA2_VI0_B2___4 = 984,\n\tFN_SSI_WS2_A = 985,\n\tFN_HCTS1_N_B = 986,\n\tFN_AVB_TX_ER___3 = 987,\n\tFN_VI0_DATA3_VI0_B3___4 = 988,\n\tFN_SSI_SDATA2_A = 989,\n\tFN_HRTS1_N_B = 990,\n\tFN_VI0_DATA4_VI0_B4___4 = 991,\n\tFN_SSI_SCK9_A = 992,\n\tFN_RX2_B___3 = 993,\n\tFN_SCL3_E = 994,\n\tFN_EX_WAIT1___4 = 995,\n\tFN_VI0_DATA5_VI0_B5___4 = 996,\n\tFN_SSI_WS9_A = 997,\n\tFN_TX2_B___3 = 998,\n\tFN_SDA3_E = 999,\n\tFN_VI0_DATA6_VI0_B6___4 = 1000,\n\tFN_SSI_SDATA9_A = 1001,\n\tFN_SCIF2_SCK_B___3 = 1002,\n\tFN_PWM2_D = 1003,\n\tFN_VI0_DATA7_VI0_B7___4 = 1004,\n\tFN_AUDIO_CLKA_A = 1005,\n\tFN_SCL0_B = 1006,\n\tFN_VI0_CLKENB___4 = 1007,\n\tFN_AUDIO_CLKB_A = 1008,\n\tFN_SDA0_B = 1009,\n\tFN_VI0_FIELD___4 = 1010,\n\tFN_AUDIO_CLKC_A = 1011,\n\tFN_SCL4_B = 1012,\n\tFN_VI0_HSYNC_N___3 = 1013,\n\tFN_AUDIO_CLKOUT_A = 1014,\n\tFN_SDA4_B = 1015,\n\tFN_VI0_VSYNC_N___3 = 1016,\n\tFN_SEL_ADGA_0 = 1017,\n\tFN_SEL_ADGA_1 = 1018,\n\tFN_SEL_ADGA_2 = 1019,\n\tFN_SEL_ADGA_3 = 1020,\n\tFN_SEL_CANCLK_0___3 = 1021,\n\tFN_SEL_CANCLK_1___3 = 1022,\n\tFN_SEL_CANCLK_2___3 = 1023,\n\tFN_SEL_CANCLK_3___2 = 1024,\n\tFN_SEL_CAN1_0___3 = 1025,\n\tFN_SEL_CAN1_1___3 = 1026,\n\tFN_SEL_CAN1_2___3 = 1027,\n\tFN_SEL_CAN1_3___3 = 1028,\n\tFN_SEL_CAN0_0___4 = 1029,\n\tFN_SEL_CAN0_1___4 = 1030,\n\tFN_SEL_CAN0_2___3 = 1031,\n\tFN_SEL_CAN0_3___3 = 1032,\n\tFN_SEL_I2C04_0___2 = 1033,\n\tFN_SEL_I2C04_1___2 = 1034,\n\tFN_SEL_I2C04_2___2 = 1035,\n\tFN_SEL_I2C04_3___2 = 1036,\n\tFN_SEL_I2C04_4___2 = 1037,\n\tFN_SEL_I2C03_0___2 = 1038,\n\tFN_SEL_I2C03_1___2 = 1039,\n\tFN_SEL_I2C03_2___2 = 1040,\n\tFN_SEL_I2C03_3___2 = 1041,\n\tFN_SEL_I2C03_4___2 = 1042,\n\tFN_SEL_I2C02_0___2 = 1043,\n\tFN_SEL_I2C02_1___2 = 1044,\n\tFN_SEL_I2C02_2___2 = 1045,\n\tFN_SEL_I2C02_3___2 = 1046,\n\tFN_SEL_I2C01_0___2 = 1047,\n\tFN_SEL_I2C01_1___2 = 1048,\n\tFN_SEL_I2C01_2___2 = 1049,\n\tFN_SEL_I2C01_3___2 = 1050,\n\tFN_SEL_I2C01_4___2 = 1051,\n\tFN_SEL_I2C00_0___2 = 1052,\n\tFN_SEL_I2C00_1___2 = 1053,\n\tFN_SEL_I2C00_2___2 = 1054,\n\tFN_SEL_I2C00_3___2 = 1055,\n\tFN_SEL_I2C00_4___2 = 1056,\n\tFN_SEL_AVB_0 = 1057,\n\tFN_SEL_AVB_1 = 1058,\n\tFN_SEL_SCIFCLK_0 = 1059,\n\tFN_SEL_SCIFCLK_1 = 1060,\n\tFN_SEL_SCIF5_0___4 = 1061,\n\tFN_SEL_SCIF5_1___4 = 1062,\n\tFN_SEL_SCIF5_2___3 = 1063,\n\tFN_SEL_SCIF5_3___3 = 1064,\n\tFN_SEL_SCIF5_4 = 1065,\n\tFN_SEL_SCIF5_5 = 1066,\n\tFN_SEL_SCIF4_0___4 = 1067,\n\tFN_SEL_SCIF4_1___4 = 1068,\n\tFN_SEL_SCIF4_2___4 = 1069,\n\tFN_SEL_SCIF4_3___3 = 1070,\n\tFN_SEL_SCIF4_4___2 = 1071,\n\tFN_SEL_SCIF3_0___4 = 1072,\n\tFN_SEL_SCIF3_1___4 = 1073,\n\tFN_SEL_SCIF3_2___3 = 1074,\n\tFN_SEL_SCIF2_0___4 = 1075,\n\tFN_SEL_SCIF2_1___4 = 1076,\n\tFN_SEL_SCIF2_2___4 = 1077,\n\tFN_SEL_SCIF2_CLK_0 = 1078,\n\tFN_SEL_SCIF2_CLK_1 = 1079,\n\tFN_SEL_SCIF1_0___4 = 1080,\n\tFN_SEL_SCIF1_1___4 = 1081,\n\tFN_SEL_SCIF1_2___4 = 1082,\n\tFN_SEL_SCIF1_3___2 = 1083,\n\tFN_SEL_SCIF0_0___4 = 1084,\n\tFN_SEL_SCIF0_1___4 = 1085,\n\tFN_SEL_SCIF0_2___4 = 1086,\n\tFN_SEL_SCIF0_3___4 = 1087,\n\tFN_SEL_MSIOF2_0 = 1088,\n\tFN_SEL_MSIOF2_1 = 1089,\n\tFN_SEL_MSIOF2_2 = 1090,\n\tFN_SEL_MSIOF1_0 = 1091,\n\tFN_SEL_MSIOF1_1 = 1092,\n\tFN_SEL_MSIOF0_0 = 1093,\n\tFN_SEL_MSIOF0_1 = 1094,\n\tFN_SEL_RCN_0___3 = 1095,\n\tFN_SEL_RCN_1___3 = 1096,\n\tFN_SEL_TMU2_0 = 1097,\n\tFN_SEL_TMU2_1 = 1098,\n\tFN_SEL_TMU1_0___3 = 1099,\n\tFN_SEL_TMU1_1___3 = 1100,\n\tFN_SEL_HSCIF1_0___4 = 1101,\n\tFN_SEL_HSCIF1_1___4 = 1102,\n\tFN_SEL_HSCIF1_2___2 = 1103,\n\tFN_SEL_HSCIF0_0___4 = 1104,\n\tFN_SEL_HSCIF0_1___4 = 1105,\n\tFN_SEL_ADGB_0 = 1106,\n\tFN_SEL_ADGB_1 = 1107,\n\tFN_SEL_ADGB_2 = 1108,\n\tFN_SEL_ADGC_0 = 1109,\n\tFN_SEL_ADGC_1 = 1110,\n\tFN_SEL_ADGC_2 = 1111,\n\tFN_SEL_SSI9_0___4 = 1112,\n\tFN_SEL_SSI9_1___4 = 1113,\n\tFN_SEL_SSI8_0___4 = 1114,\n\tFN_SEL_SSI8_1___4 = 1115,\n\tFN_SEL_SSI7_0___4 = 1116,\n\tFN_SEL_SSI7_1___4 = 1117,\n\tFN_SEL_SSI6_0___2 = 1118,\n\tFN_SEL_SSI6_1___2 = 1119,\n\tFN_SEL_SSI5_0___2 = 1120,\n\tFN_SEL_SSI5_1___2 = 1121,\n\tFN_SEL_SSI4_0___2 = 1122,\n\tFN_SEL_SSI4_1___2 = 1123,\n\tFN_SEL_SSI2_0___2 = 1124,\n\tFN_SEL_SSI2_1___2 = 1125,\n\tFN_SEL_SSI1_0___3 = 1126,\n\tFN_SEL_SSI1_1___3 = 1127,\n\tFN_SEL_SSI1_2 = 1128,\n\tFN_SEL_SSI1_3 = 1129,\n\tFN_SEL_SSI0_0___2 = 1130,\n\tFN_SEL_SSI0_1___2 = 1131,\n\tPINMUX_FUNCTION_END___7 = 1132,\n\tPINMUX_MARK_BEGIN___7 = 1133,\n\tUSB0_PWEN_MARK___3 = 1134,\n\tUSB0_OVC_MARK___3 = 1135,\n\tUSB1_PWEN_MARK___3 = 1136,\n\tUSB1_OVC_MARK___3 = 1137,\n\tCLKOUT_MARK___2 = 1138,\n\tMMC0_CLK_SDHI1_CLK_MARK = 1139,\n\tMMC0_CMD_SDHI1_CMD_MARK = 1140,\n\tMMC0_D0_SDHI1_D0_MARK = 1141,\n\tMMC0_D1_SDHI1_D1_MARK = 1142,\n\tMMC0_D2_SDHI1_D2_MARK = 1143,\n\tMMC0_D3_SDHI1_D3_MARK = 1144,\n\tMMC0_D6_MARK___2 = 1145,\n\tMMC0_D7_MARK___2 = 1146,\n\tSD0_CLK_MARK___4 = 1147,\n\tSSI_SCK1_C_MARK = 1148,\n\tRX3_C_MARK___2 = 1149,\n\tSD0_CMD_MARK___4 = 1150,\n\tSSI_WS1_C_MARK = 1151,\n\tTX3_C_MARK___2 = 1152,\n\tSD0_DAT0_MARK___2 = 1153,\n\tSSI_SDATA1_C_MARK = 1154,\n\tRX4_E_MARK = 1155,\n\tSD0_DAT1_MARK___2 = 1156,\n\tSSI_SCK0129_B_MARK___2 = 1157,\n\tTX4_E_MARK = 1158,\n\tSD0_DAT2_MARK___2 = 1159,\n\tSSI_WS0129_B_MARK___2 = 1160,\n\tRX5_E_MARK = 1161,\n\tSD0_DAT3_MARK___2 = 1162,\n\tSSI_SDATA0_B_MARK___2 = 1163,\n\tTX5_E_MARK = 1164,\n\tSD0_CD_MARK___4 = 1165,\n\tCAN0_RX_A_MARK = 1166,\n\tSD0_WP_MARK___4 = 1167,\n\tIRQ7_MARK___4 = 1168,\n\tCAN0_TX_A_MARK = 1169,\n\tMMC0_D4_MARK___2 = 1170,\n\tSD1_CD_MARK___4 = 1171,\n\tMMC0_D5_MARK___2 = 1172,\n\tSD1_WP_MARK___4 = 1173,\n\tD0_MARK___4 = 1174,\n\tSCL3_B_MARK___2 = 1175,\n\tRX5_B_MARK___3 = 1176,\n\tIRQ4_MARK___4 = 1177,\n\tMSIOF2_RXD_C_MARK___2 = 1178,\n\tSSI_SDATA5_B_MARK___2 = 1179,\n\tD1_MARK___4 = 1180,\n\tSDA3_B_MARK___2 = 1181,\n\tTX5_B_MARK___3 = 1182,\n\tMSIOF2_TXD_C_MARK___2 = 1183,\n\tSSI_WS5_B_MARK___2 = 1184,\n\tD2_MARK___4 = 1185,\n\tRX4_B_MARK___3 = 1186,\n\tSCL0_D_MARK = 1187,\n\tPWM1_C_MARK___2 = 1188,\n\tMSIOF2_SCK_C_MARK___2 = 1189,\n\tSSI_SCK5_B_MARK___2 = 1190,\n\tD3_MARK___4 = 1191,\n\tTX4_B_MARK___3 = 1192,\n\tSDA0_D_MARK = 1193,\n\tPWM0_A_MARK = 1194,\n\tMSIOF2_SYNC_C_MARK___2 = 1195,\n\tD4_MARK___4 = 1196,\n\tIRQ3_MARK___5 = 1197,\n\tTCLK1_A_MARK = 1198,\n\tPWM6_C_MARK = 1199,\n\tD5_MARK___4 = 1200,\n\tHRX2_MARK___2 = 1201,\n\tSCL1_B_MARK___2 = 1202,\n\tPWM2_C_MARK___2 = 1203,\n\tTCLK2_B_MARK___2 = 1204,\n\tD6_MARK___4 = 1205,\n\tHTX2_MARK___2 = 1206,\n\tSDA1_B_MARK___2 = 1207,\n\tPWM4_C_MARK = 1208,\n\tD7_MARK___4 = 1209,\n\tHSCK2_MARK___2 = 1210,\n\tSCIF1_SCK_C_MARK___2 = 1211,\n\tIRQ6_MARK___4 = 1212,\n\tPWM5_C_MARK___2 = 1213,\n\tD8_MARK___4 = 1214,\n\tHCTS2_N_MARK___2 = 1215,\n\tRX1_C_MARK___3 = 1216,\n\tSCL1_D_MARK___2 = 1217,\n\tPWM3_C_MARK = 1218,\n\tD9_MARK___4 = 1219,\n\tHRTS2_N_MARK___2 = 1220,\n\tTX1_C_MARK___3 = 1221,\n\tSDA1_D_MARK___2 = 1222,\n\tD10_MARK___4 = 1223,\n\tMSIOF2_RXD_A_MARK = 1224,\n\tHRX0_B_MARK___3 = 1225,\n\tD11_MARK___4 = 1226,\n\tMSIOF2_TXD_A_MARK = 1227,\n\tHTX0_B_MARK___3 = 1228,\n\tD12_MARK___4 = 1229,\n\tMSIOF2_SCK_A_MARK = 1230,\n\tHSCK0_MARK___3 = 1231,\n\tCAN_CLK_C_MARK___4 = 1232,\n\tD13_MARK___4 = 1233,\n\tMSIOF2_SYNC_A_MARK = 1234,\n\tRX4_C_MARK___3 = 1235,\n\tD14_MARK___4 = 1236,\n\tMSIOF2_SS1_MARK___5 = 1237,\n\tTX4_C_MARK___3 = 1238,\n\tCAN1_RX_B_MARK___3 = 1239,\n\tAVB_AVTP_CAPTURE_A_MARK = 1240,\n\tD15_MARK___4 = 1241,\n\tMSIOF2_SS2_MARK___5 = 1242,\n\tPWM4_A_MARK = 1243,\n\tCAN1_TX_B_MARK___3 = 1244,\n\tIRQ2_MARK___5 = 1245,\n\tAVB_AVTP_MATCH_A_MARK = 1246,\n\tQSPI0_SPCLK_MARK = 1247,\n\tWE0_N_MARK___4 = 1248,\n\tQSPI0_MOSI_QSPI0_IO0_MARK = 1249,\n\tBS_N_MARK___3 = 1250,\n\tQSPI0_MISO_QSPI0_IO1_MARK = 1251,\n\tRD_WR_N_MARK___3 = 1252,\n\tQSPI0_IO2_MARK = 1253,\n\tCS0_N_MARK___4 = 1254,\n\tQSPI0_IO3_MARK = 1255,\n\tRD_N_MARK___4 = 1256,\n\tQSPI0_SSL_MARK = 1257,\n\tWE1_N_MARK___4 = 1258,\n\tEX_WAIT0_MARK___3 = 1259,\n\tCAN_CLK_B_MARK___4 = 1260,\n\tSCIF_CLK_A_MARK = 1261,\n\tDU0_DR0_MARK___4 = 1262,\n\tRX5_C_MARK___2 = 1263,\n\tSCL2_D_MARK___2 = 1264,\n\tA0_MARK___7 = 1265,\n\tDU0_DR1_MARK___3 = 1266,\n\tTX5_C_MARK___2 = 1267,\n\tSDA2_D_MARK___2 = 1268,\n\tA1_MARK___5 = 1269,\n\tDU0_DR2_MARK___4 = 1270,\n\tRX0_D_MARK___3 = 1271,\n\tSCL0_E_MARK = 1272,\n\tA2_MARK___5 = 1273,\n\tDU0_DR3_MARK___4 = 1274,\n\tTX0_D_MARK___3 = 1275,\n\tSDA0_E_MARK = 1276,\n\tPWM0_B_MARK___4 = 1277,\n\tA3_MARK___5 = 1278,\n\tDU0_DR4_MARK___4 = 1279,\n\tRX1_D_MARK___2 = 1280,\n\tA4_MARK___4 = 1281,\n\tDU0_DR5_MARK___4 = 1282,\n\tTX1_D_MARK___2 = 1283,\n\tPWM1_B_MARK___3 = 1284,\n\tA5_MARK___4 = 1285,\n\tDU0_DR6_MARK___4 = 1286,\n\tRX2_C_MARK___3 = 1287,\n\tA6_MARK___5 = 1288,\n\tDU0_DR7_MARK___4 = 1289,\n\tTX2_C_MARK___3 = 1290,\n\tPWM2_B_MARK___3 = 1291,\n\tA7_MARK___5 = 1292,\n\tDU0_DG0_MARK___4 = 1293,\n\tRX3_B_MARK___2 = 1294,\n\tSCL3_D_MARK = 1295,\n\tA8_MARK___5 = 1296,\n\tDU0_DG1_MARK___4 = 1297,\n\tTX3_B_MARK___2 = 1298,\n\tSDA3_D_MARK = 1299,\n\tPWM3_B_MARK___2 = 1300,\n\tA9_MARK___5 = 1301,\n\tDU0_DG2_MARK___4 = 1302,\n\tRX4_D_MARK___2 = 1303,\n\tA10_MARK___5 = 1304,\n\tDU0_DG3_MARK___4 = 1305,\n\tTX4_D_MARK___2 = 1306,\n\tPWM4_B_MARK___3 = 1307,\n\tA11_MARK___5 = 1308,\n\tDU0_DG4_MARK___4 = 1309,\n\tHRX0_A_MARK = 1310,\n\tA12_MARK___5 = 1311,\n\tDU0_DG5_MARK___4 = 1312,\n\tHTX0_A_MARK = 1313,\n\tPWM5_B_MARK___3 = 1314,\n\tA13_MARK___5 = 1315,\n\tDU0_DG6_MARK___4 = 1316,\n\tHRX1_C_MARK___2 = 1317,\n\tA14_MARK___5 = 1318,\n\tDU0_DG7_MARK___4 = 1319,\n\tHTX1_C_MARK___2 = 1320,\n\tPWM6_B_MARK___2 = 1321,\n\tA15_MARK___5 = 1322,\n\tDU0_DB0_MARK___4 = 1323,\n\tSCL4_D_MARK = 1324,\n\tCAN0_RX_C_MARK___3 = 1325,\n\tA16_MARK___5 = 1326,\n\tDU0_DB1_MARK___4 = 1327,\n\tSDA4_D_MARK = 1328,\n\tCAN0_TX_C_MARK___3 = 1329,\n\tA17_MARK___6 = 1330,\n\tDU0_DB2_MARK___4 = 1331,\n\tHCTS0_N_MARK___2 = 1332,\n\tA18_MARK___6 = 1333,\n\tDU0_DB3_MARK___4 = 1334,\n\tHRTS0_N_MARK___2 = 1335,\n\tA19_MARK___6 = 1336,\n\tDU0_DB4_MARK___4 = 1337,\n\tHCTS1_N_C_MARK___2 = 1338,\n\tA20_MARK___6 = 1339,\n\tDU0_DB5_MARK___4 = 1340,\n\tHRTS1_N_C_MARK___2 = 1341,\n\tA21_MARK___6 = 1342,\n\tDU0_DB6_MARK___4 = 1343,\n\tA22_MARK___6 = 1344,\n\tDU0_DB7_MARK___4 = 1345,\n\tA23_MARK___6 = 1346,\n\tDU0_DOTCLKIN_MARK___5 = 1347,\n\tA24_MARK___6 = 1348,\n\tDU0_DOTCLKOUT0_MARK___3 = 1349,\n\tA25_MARK___6 = 1350,\n\tDU0_DOTCLKOUT1_MARK___3 = 1351,\n\tMSIOF2_RXD_B_MARK___3 = 1352,\n\tCS1_N_A26_MARK___3 = 1353,\n\tDU0_EXHSYNC_DU0_HSYNC_MARK___3 = 1354,\n\tMSIOF2_TXD_B_MARK___3 = 1355,\n\tDREQ0_N_MARK___2 = 1356,\n\tDU0_EXVSYNC_DU0_VSYNC_MARK___3 = 1357,\n\tMSIOF2_SYNC_B_MARK___3 = 1358,\n\tDACK0_MARK___6 = 1359,\n\tDU0_EXODDF_DU0_ODDF_DISP_CDE_MARK___3 = 1360,\n\tMSIOF2_SCK_B_MARK___3 = 1361,\n\tDRACK0_MARK___4 = 1362,\n\tDU0_DISP_MARK___3 = 1363,\n\tCAN1_RX_C_MARK___3 = 1364,\n\tDU0_CDE_MARK___4 = 1365,\n\tCAN1_TX_C_MARK___3 = 1366,\n\tVI1_CLK_MARK___4 = 1367,\n\tAVB_RX_CLK_MARK___3 = 1368,\n\tETH_REF_CLK_MARK = 1369,\n\tVI1_DATA0_MARK___3 = 1370,\n\tAVB_RX_DV_MARK___3 = 1371,\n\tETH_CRS_DV_MARK___4 = 1372,\n\tVI1_DATA1_MARK___3 = 1373,\n\tAVB_RXD0_MARK___3 = 1374,\n\tETH_RXD0_MARK___4 = 1375,\n\tVI1_DATA2_MARK___3 = 1376,\n\tAVB_RXD1_MARK___3 = 1377,\n\tETH_RXD1_MARK___4 = 1378,\n\tVI1_DATA3_MARK___3 = 1379,\n\tAVB_RXD2_MARK___3 = 1380,\n\tETH_MDIO_MARK___4 = 1381,\n\tVI1_DATA4_MARK___3 = 1382,\n\tAVB_RXD3_MARK___3 = 1383,\n\tETH_RX_ER_MARK___4 = 1384,\n\tVI1_DATA5_MARK___3 = 1385,\n\tAVB_RXD4_MARK___3 = 1386,\n\tETH_LINK_MARK___4 = 1387,\n\tVI1_DATA6_MARK___3 = 1388,\n\tAVB_RXD5_MARK___3 = 1389,\n\tETH_TXD1_MARK___4 = 1390,\n\tVI1_DATA7_MARK___3 = 1391,\n\tAVB_RXD6_MARK___3 = 1392,\n\tETH_TX_EN_MARK___4 = 1393,\n\tVI1_CLKENB_MARK___4 = 1394,\n\tSCL3_A_MARK = 1395,\n\tAVB_RXD7_MARK___3 = 1396,\n\tETH_MAGIC_MARK___4 = 1397,\n\tVI1_FIELD_MARK___4 = 1398,\n\tSDA3_A_MARK = 1399,\n\tAVB_RX_ER_MARK___3 = 1400,\n\tETH_TXD0_MARK___4 = 1401,\n\tVI1_HSYNC_N_MARK___3 = 1402,\n\tRX0_B_MARK___3 = 1403,\n\tSCL0_C_MARK = 1404,\n\tAVB_GTXREFCLK_MARK___3 = 1405,\n\tETH_MDC_MARK___4 = 1406,\n\tVI1_VSYNC_N_MARK___3 = 1407,\n\tTX0_B_MARK___3 = 1408,\n\tSDA0_C_MARK = 1409,\n\tAUDIO_CLKOUT_B_MARK___3 = 1410,\n\tAVB_TX_CLK_MARK___3 = 1411,\n\tVI1_DATA8_MARK___2 = 1412,\n\tSCL2_B_MARK___2 = 1413,\n\tAVB_TX_EN_MARK___3 = 1414,\n\tVI1_DATA9_MARK___2 = 1415,\n\tSDA2_B_MARK___2 = 1416,\n\tAVB_TXD0_MARK___3 = 1417,\n\tVI1_DATA10_MARK___2 = 1418,\n\tCAN0_RX_B_MARK___4 = 1419,\n\tAVB_TXD1_MARK___3 = 1420,\n\tVI1_DATA11_MARK___2 = 1421,\n\tCAN0_TX_B_MARK___4 = 1422,\n\tAVB_TXD2_MARK___3 = 1423,\n\tAVB_TXD3_MARK___3 = 1424,\n\tAUDIO_CLKA_B_MARK___2 = 1425,\n\tSSI_SCK1_D_MARK = 1426,\n\tRX5_F_MARK = 1427,\n\tMSIOF0_RXD_B_MARK___2 = 1428,\n\tAVB_TXD4_MARK___3 = 1429,\n\tAUDIO_CLKB_B_MARK___3 = 1430,\n\tSSI_WS1_D_MARK = 1431,\n\tTX5_F_MARK = 1432,\n\tMSIOF0_TXD_B_MARK___2 = 1433,\n\tAVB_TXD5_MARK___3 = 1434,\n\tSCIF_CLK_B_MARK___4 = 1435,\n\tAUDIO_CLKC_B_MARK___2 = 1436,\n\tSSI_SDATA1_D_MARK = 1437,\n\tMSIOF0_SCK_B_MARK___2 = 1438,\n\tSCL0_A_MARK = 1439,\n\tRX0_C_MARK___3 = 1440,\n\tPWM5_A_MARK = 1441,\n\tTCLK1_B_MARK___4 = 1442,\n\tAVB_TXD6_MARK___3 = 1443,\n\tCAN1_RX_D_MARK___3 = 1444,\n\tMSIOF0_SYNC_B_MARK___2 = 1445,\n\tSDA0_A_MARK = 1446,\n\tTX0_C_MARK___3 = 1447,\n\tIRQ5_MARK___4 = 1448,\n\tCAN_CLK_A_MARK = 1449,\n\tAVB_GTX_CLK_MARK___3 = 1450,\n\tCAN1_TX_D_MARK___3 = 1451,\n\tDVC_MUTE_MARK___3 = 1452,\n\tSCL1_A_MARK = 1453,\n\tRX4_A_MARK = 1454,\n\tPWM5_D_MARK = 1455,\n\tDU1_DR0_MARK___4 = 1456,\n\tSSI_SCK6_B_MARK___2 = 1457,\n\tVI0_G0_MARK___4 = 1458,\n\tSDA1_A_MARK = 1459,\n\tTX4_A_MARK = 1460,\n\tDU1_DR1_MARK___4 = 1461,\n\tSSI_WS6_B_MARK___2 = 1462,\n\tVI0_G1_MARK___4 = 1463,\n\tMSIOF0_RXD_A_MARK = 1464,\n\tRX5_A_MARK = 1465,\n\tSCL2_C_MARK___2 = 1466,\n\tDU1_DR2_MARK___4 = 1467,\n\tQSPI1_MOSI_QSPI1_IO0_MARK = 1468,\n\tSSI_SDATA6_B_MARK___2 = 1469,\n\tVI0_G2_MARK___4 = 1470,\n\tMSIOF0_TXD_A_MARK = 1471,\n\tTX5_A_MARK = 1472,\n\tSDA2_C_MARK___2 = 1473,\n\tDU1_DR3_MARK___4 = 1474,\n\tQSPI1_MISO_QSPI1_IO1_MARK = 1475,\n\tSSI_WS78_B_MARK___4 = 1476,\n\tVI0_G3_MARK___4 = 1477,\n\tMSIOF0_SCK_A_MARK = 1478,\n\tIRQ0_MARK___5 = 1479,\n\tDU1_DR4_MARK___4 = 1480,\n\tQSPI1_SPCLK_MARK = 1481,\n\tSSI_SCK78_B_MARK___4 = 1482,\n\tVI0_G4_MARK___4 = 1483,\n\tMSIOF0_SYNC_A_MARK = 1484,\n\tPWM1_A_MARK = 1485,\n\tDU1_DR5_MARK___4 = 1486,\n\tQSPI1_IO2_MARK = 1487,\n\tSSI_SDATA7_B_MARK___4 = 1488,\n\tMSIOF0_SS1_A_MARK = 1489,\n\tDU1_DR6_MARK___4 = 1490,\n\tQSPI1_IO3_MARK = 1491,\n\tSSI_SDATA8_B_MARK___4 = 1492,\n\tMSIOF0_SS2_A_MARK = 1493,\n\tDU1_DR7_MARK___4 = 1494,\n\tQSPI1_SSL_MARK = 1495,\n\tHRX1_A_MARK = 1496,\n\tSCL4_A_MARK = 1497,\n\tPWM6_A_MARK = 1498,\n\tDU1_DG0_MARK___4 = 1499,\n\tRX0_A_MARK = 1500,\n\tHTX1_A_MARK = 1501,\n\tSDA4_A_MARK = 1502,\n\tDU1_DG1_MARK___4 = 1503,\n\tTX0_A_MARK = 1504,\n\tHCTS1_N_A_MARK = 1505,\n\tPWM2_A_MARK = 1506,\n\tDU1_DG2_MARK___4 = 1507,\n\tREMOCON_B_MARK___3 = 1508,\n\tHRTS1_N_A_MARK = 1509,\n\tDU1_DG3_MARK___4 = 1510,\n\tSSI_WS1_B_MARK___3 = 1511,\n\tIRQ1_MARK___6 = 1512,\n\tSD2_CLK_MARK___4 = 1513,\n\tHSCK1_MARK___3 = 1514,\n\tDU1_DG4_MARK___4 = 1515,\n\tSSI_SCK1_B_MARK___3 = 1516,\n\tSD2_CMD_MARK___4 = 1517,\n\tSCIF1_SCK_A_MARK = 1518,\n\tTCLK2_A_MARK = 1519,\n\tDU1_DG5_MARK___4 = 1520,\n\tSSI_SCK2_B_MARK___2 = 1521,\n\tPWM3_A_MARK = 1522,\n\tSD2_DAT0_MARK___2 = 1523,\n\tRX1_A_MARK = 1524,\n\tSCL1_E_MARK = 1525,\n\tDU1_DG6_MARK___4 = 1526,\n\tSSI_SDATA1_B_MARK___3 = 1527,\n\tSD2_DAT1_MARK___2 = 1528,\n\tTX1_A_MARK = 1529,\n\tSDA1_E_MARK = 1530,\n\tDU1_DG7_MARK___4 = 1531,\n\tSSI_WS2_B_MARK___2 = 1532,\n\tSD2_DAT2_MARK___2 = 1533,\n\tRX2_A_MARK = 1534,\n\tDU1_DB0_MARK___4 = 1535,\n\tSSI_SDATA2_B_MARK___2 = 1536,\n\tSD2_DAT3_MARK___2 = 1537,\n\tTX2_A_MARK = 1538,\n\tDU1_DB1_MARK___4 = 1539,\n\tSSI_WS9_B_MARK___4 = 1540,\n\tSD2_CD_MARK___4 = 1541,\n\tSCIF2_SCK_A_MARK = 1542,\n\tDU1_DB2_MARK___4 = 1543,\n\tSSI_SCK9_B_MARK___4 = 1544,\n\tSD2_WP_MARK___4 = 1545,\n\tSCIF3_SCK_MARK___3 = 1546,\n\tDU1_DB3_MARK___4 = 1547,\n\tSSI_SDATA9_B_MARK___4 = 1548,\n\tRX3_A_MARK = 1549,\n\tSCL1_C_MARK___2 = 1550,\n\tMSIOF1_RXD_B_MARK___3 = 1551,\n\tDU1_DB4_MARK___4 = 1552,\n\tAUDIO_CLKA_C_MARK___2 = 1553,\n\tSSI_SDATA4_B_MARK___2 = 1554,\n\tTX3_A_MARK = 1555,\n\tSDA1_C_MARK___2 = 1556,\n\tMSIOF1_TXD_B_MARK___3 = 1557,\n\tDU1_DB5_MARK___4 = 1558,\n\tAUDIO_CLKB_C_MARK___2 = 1559,\n\tSSI_WS4_B_MARK___2 = 1560,\n\tSCL2_A_MARK = 1561,\n\tMSIOF1_SCK_B_MARK___3 = 1562,\n\tDU1_DB6_MARK___4 = 1563,\n\tAUDIO_CLKC_C_MARK___2 = 1564,\n\tSSI_SCK4_B_MARK___2 = 1565,\n\tSDA2_A_MARK = 1566,\n\tMSIOF1_SYNC_B_MARK___3 = 1567,\n\tDU1_DB7_MARK___4 = 1568,\n\tAUDIO_CLKOUT_C_MARK___3 = 1569,\n\tSSI_SCK5_A_MARK = 1570,\n\tDU1_DOTCLKOUT1_MARK___3 = 1571,\n\tSSI_WS5_A_MARK = 1572,\n\tSCL3_C_MARK = 1573,\n\tDU1_DOTCLKIN_MARK___4 = 1574,\n\tSSI_SDATA5_A_MARK = 1575,\n\tSDA3_C_MARK = 1576,\n\tDU1_DOTCLKOUT0_MARK___3 = 1577,\n\tSSI_SCK6_A_MARK = 1578,\n\tDU1_EXODDF_DU1_ODDF_DISP_CDE_MARK___4 = 1579,\n\tSSI_WS6_A_MARK = 1580,\n\tSCL4_C_MARK = 1581,\n\tDU1_EXHSYNC_DU1_HSYNC_MARK___4 = 1582,\n\tSSI_SDATA6_A_MARK = 1583,\n\tSDA4_C_MARK = 1584,\n\tDU1_EXVSYNC_DU1_VSYNC_MARK___4 = 1585,\n\tSSI_SCK78_A_MARK = 1586,\n\tSDA4_E_MARK = 1587,\n\tDU1_DISP_MARK___4 = 1588,\n\tSSI_WS78_A_MARK = 1589,\n\tSCL4_E_MARK = 1590,\n\tDU1_CDE_MARK___4 = 1591,\n\tSSI_SDATA7_A_MARK = 1592,\n\tIRQ8_MARK___5 = 1593,\n\tAUDIO_CLKA_D_MARK___2 = 1594,\n\tCAN_CLK_D_MARK___3 = 1595,\n\tVI0_G5_MARK___4 = 1596,\n\tSSI_SCK0129_A_MARK = 1597,\n\tMSIOF1_RXD_A_MARK = 1598,\n\tRX5_D_MARK___2 = 1599,\n\tVI0_G6_MARK___4 = 1600,\n\tSSI_WS0129_A_MARK = 1601,\n\tMSIOF1_TXD_A_MARK = 1602,\n\tTX5_D_MARK___2 = 1603,\n\tVI0_G7_MARK___4 = 1604,\n\tSSI_SDATA0_A_MARK = 1605,\n\tMSIOF1_SYNC_A_MARK = 1606,\n\tPWM0_C_MARK___2 = 1607,\n\tVI0_R0_MARK___4 = 1608,\n\tSSI_SCK34_MARK___4 = 1609,\n\tMSIOF1_SCK_A_MARK = 1610,\n\tAVB_MDC_MARK___3 = 1611,\n\tDACK1_MARK___6 = 1612,\n\tVI0_R1_MARK___4 = 1613,\n\tSSI_WS34_MARK___4 = 1614,\n\tMSIOF1_SS1_A_MARK = 1615,\n\tAVB_MDIO_MARK___3 = 1616,\n\tCAN1_RX_A_MARK = 1617,\n\tDREQ1_N_MARK___2 = 1618,\n\tVI0_R2_MARK___4 = 1619,\n\tSSI_SDATA3_MARK___4 = 1620,\n\tMSIOF1_SS2_A_MARK = 1621,\n\tAVB_LINK_MARK___3 = 1622,\n\tCAN1_TX_A_MARK = 1623,\n\tDREQ2_N_MARK___2 = 1624,\n\tVI0_R3_MARK___4 = 1625,\n\tSSI_SCK4_A_MARK = 1626,\n\tAVB_MAGIC_MARK___3 = 1627,\n\tVI0_R4_MARK___4 = 1628,\n\tSSI_WS4_A_MARK = 1629,\n\tAVB_PHY_INT_MARK___3 = 1630,\n\tVI0_R5_MARK___4 = 1631,\n\tSSI_SDATA4_A_MARK = 1632,\n\tAVB_CRS_MARK___3 = 1633,\n\tVI0_R6_MARK___4 = 1634,\n\tSSI_SCK1_A_MARK = 1635,\n\tSCIF1_SCK_B_MARK___3 = 1636,\n\tPWM1_D_MARK = 1637,\n\tIRQ9_MARK___4 = 1638,\n\tREMOCON_A_MARK = 1639,\n\tDACK2_MARK___5 = 1640,\n\tVI0_CLK_MARK___4 = 1641,\n\tAVB_COL_MARK___3 = 1642,\n\tSSI_SDATA8_A_MARK = 1643,\n\tRX1_B_MARK___3 = 1644,\n\tCAN0_RX_D_MARK___3 = 1645,\n\tAVB_AVTP_CAPTURE_B_MARK = 1646,\n\tVI0_R7_MARK___4 = 1647,\n\tSSI_WS1_A_MARK = 1648,\n\tTX1_B_MARK___3 = 1649,\n\tCAN0_TX_D_MARK___3 = 1650,\n\tAVB_AVTP_MATCH_B_MARK = 1651,\n\tVI0_DATA0_VI0_B0_MARK___4 = 1652,\n\tSSI_SDATA1_A_MARK = 1653,\n\tHRX1_B_MARK___3 = 1654,\n\tVI0_DATA1_VI0_B1_MARK___4 = 1655,\n\tSSI_SCK2_A_MARK = 1656,\n\tHTX1_B_MARK___3 = 1657,\n\tAVB_TXD7_MARK___3 = 1658,\n\tVI0_DATA2_VI0_B2_MARK___4 = 1659,\n\tSSI_WS2_A_MARK = 1660,\n\tHCTS1_N_B_MARK = 1661,\n\tAVB_TX_ER_MARK___3 = 1662,\n\tVI0_DATA3_VI0_B3_MARK___4 = 1663,\n\tSSI_SDATA2_A_MARK = 1664,\n\tHRTS1_N_B_MARK = 1665,\n\tVI0_DATA4_VI0_B4_MARK___4 = 1666,\n\tSSI_SCK9_A_MARK = 1667,\n\tRX2_B_MARK___3 = 1668,\n\tSCL3_E_MARK = 1669,\n\tEX_WAIT1_MARK___4 = 1670,\n\tVI0_DATA5_VI0_B5_MARK___4 = 1671,\n\tSSI_WS9_A_MARK = 1672,\n\tTX2_B_MARK___3 = 1673,\n\tSDA3_E_MARK = 1674,\n\tVI0_DATA6_VI0_B6_MARK___4 = 1675,\n\tSSI_SDATA9_A_MARK = 1676,\n\tSCIF2_SCK_B_MARK___3 = 1677,\n\tPWM2_D_MARK = 1678,\n\tVI0_DATA7_VI0_B7_MARK___4 = 1679,\n\tAUDIO_CLKA_A_MARK = 1680,\n\tSCL0_B_MARK = 1681,\n\tVI0_CLKENB_MARK___4 = 1682,\n\tAUDIO_CLKB_A_MARK = 1683,\n\tSDA0_B_MARK = 1684,\n\tVI0_FIELD_MARK___4 = 1685,\n\tAUDIO_CLKC_A_MARK = 1686,\n\tSCL4_B_MARK = 1687,\n\tVI0_HSYNC_N_MARK___3 = 1688,\n\tAUDIO_CLKOUT_A_MARK = 1689,\n\tSDA4_B_MARK = 1690,\n\tVI0_VSYNC_N_MARK___3 = 1691,\n\tPINMUX_MARK_END___7 = 1692,\n};\n\nenum {\n\tPINMUX_RESERVED___8 = 0,\n\tPINMUX_DATA_BEGIN___8 = 1,\n\tGP_0_0_DATA___5 = 2,\n\tGP_0_1_DATA___5 = 3,\n\tGP_0_2_DATA___5 = 4,\n\tGP_0_3_DATA___5 = 5,\n\tGP_0_4_DATA___5 = 6,\n\tGP_0_5_DATA___5 = 7,\n\tGP_0_6_DATA___5 = 8,\n\tGP_0_7_DATA___5 = 9,\n\tGP_0_8_DATA___5 = 10,\n\tGP_0_9_DATA___5 = 11,\n\tGP_0_10_DATA___5 = 12,\n\tGP_0_11_DATA___5 = 13,\n\tGP_0_12_DATA___5 = 14,\n\tGP_0_13_DATA___5 = 15,\n\tGP_0_14_DATA___5 = 16,\n\tGP_0_15_DATA___5 = 17,\n\tGP_0_16_DATA___5 = 18,\n\tGP_0_17_DATA___5 = 19,\n\tGP_0_18_DATA___5 = 20,\n\tGP_0_19_DATA___5 = 21,\n\tGP_0_20_DATA___5 = 22,\n\tGP_0_21_DATA___5 = 23,\n\tGP_0_22_DATA___5 = 24,\n\tGP_0_23_DATA___4 = 25,\n\tGP_0_24_DATA___4 = 26,\n\tGP_0_25_DATA___4 = 27,\n\tGP_0_26_DATA___4 = 28,\n\tGP_0_27_DATA___4 = 29,\n\tGP_0_28_DATA___4 = 30,\n\tGP_0_29_DATA___4 = 31,\n\tGP_0_30_DATA___4 = 32,\n\tGP_0_31_DATA___4 = 33,\n\tGP_1_0_DATA___5 = 34,\n\tGP_1_1_DATA___5 = 35,\n\tGP_1_2_DATA___5 = 36,\n\tGP_1_3_DATA___5 = 37,\n\tGP_1_4_DATA___5 = 38,\n\tGP_1_5_DATA___5 = 39,\n\tGP_1_6_DATA___5 = 40,\n\tGP_1_7_DATA___5 = 41,\n\tGP_1_8_DATA___5 = 42,\n\tGP_1_9_DATA___5 = 43,\n\tGP_1_10_DATA___5 = 44,\n\tGP_1_11_DATA___5 = 45,\n\tGP_1_12_DATA___5 = 46,\n\tGP_1_13_DATA___5 = 47,\n\tGP_1_14_DATA___5 = 48,\n\tGP_1_15_DATA___5 = 49,\n\tGP_1_16_DATA___5 = 50,\n\tGP_1_17_DATA___5 = 51,\n\tGP_1_18_DATA___5 = 52,\n\tGP_1_19_DATA___5 = 53,\n\tGP_1_20_DATA___5 = 54,\n\tGP_1_21_DATA___5 = 55,\n\tGP_1_22_DATA___5 = 56,\n\tGP_1_23_DATA___4 = 57,\n\tGP_1_24_DATA___4 = 58,\n\tGP_1_25_DATA___4 = 59,\n\tGP_1_26_DATA___2 = 60,\n\tGP_1_27_DATA___2 = 61,\n\tGP_1_28_DATA___2 = 62,\n\tGP_1_29_DATA___2 = 63,\n\tGP_1_30_DATA___2 = 64,\n\tGP_1_31_DATA___2 = 65,\n\tGP_2_0_DATA___5 = 66,\n\tGP_2_1_DATA___5 = 67,\n\tGP_2_2_DATA___5 = 68,\n\tGP_2_3_DATA___5 = 69,\n\tGP_2_4_DATA___5 = 70,\n\tGP_2_5_DATA___5 = 71,\n\tGP_2_6_DATA___5 = 72,\n\tGP_2_7_DATA___5 = 73,\n\tGP_2_8_DATA___5 = 74,\n\tGP_2_9_DATA___5 = 75,\n\tGP_2_10_DATA___5 = 76,\n\tGP_2_11_DATA___5 = 77,\n\tGP_2_12_DATA___5 = 78,\n\tGP_2_13_DATA___5 = 79,\n\tGP_2_14_DATA___5 = 80,\n\tGP_2_15_DATA___5 = 81,\n\tGP_2_16_DATA___5 = 82,\n\tGP_2_17_DATA___5 = 83,\n\tGP_2_18_DATA___5 = 84,\n\tGP_2_19_DATA___5 = 85,\n\tGP_2_20_DATA___5 = 86,\n\tGP_2_21_DATA___5 = 87,\n\tGP_2_22_DATA___5 = 88,\n\tGP_2_23_DATA___5 = 89,\n\tGP_2_24_DATA___5 = 90,\n\tGP_2_25_DATA___5 = 91,\n\tGP_2_26_DATA___5 = 92,\n\tGP_2_27_DATA___5 = 93,\n\tGP_2_28_DATA___5 = 94,\n\tGP_2_29_DATA___5 = 95,\n\tGP_2_30_DATA___5 = 96,\n\tGP_2_31_DATA___5 = 97,\n\tGP_3_0_DATA___5 = 98,\n\tGP_3_1_DATA___5 = 99,\n\tGP_3_2_DATA___5 = 100,\n\tGP_3_3_DATA___5 = 101,\n\tGP_3_4_DATA___5 = 102,\n\tGP_3_5_DATA___5 = 103,\n\tGP_3_6_DATA___5 = 104,\n\tGP_3_7_DATA___5 = 105,\n\tGP_3_8_DATA___5 = 106,\n\tGP_3_9_DATA___5 = 107,\n\tGP_3_10_DATA___5 = 108,\n\tGP_3_11_DATA___5 = 109,\n\tGP_3_12_DATA___5 = 110,\n\tGP_3_13_DATA___5 = 111,\n\tGP_3_14_DATA___5 = 112,\n\tGP_3_15_DATA___5 = 113,\n\tGP_3_16_DATA___5 = 114,\n\tGP_3_17_DATA___4 = 115,\n\tGP_3_18_DATA___4 = 116,\n\tGP_3_19_DATA___4 = 117,\n\tGP_3_20_DATA___4 = 118,\n\tGP_3_21_DATA___4 = 119,\n\tGP_3_22_DATA___4 = 120,\n\tGP_3_23_DATA___4 = 121,\n\tGP_3_24_DATA___4 = 122,\n\tGP_3_25_DATA___4 = 123,\n\tGP_3_26_DATA___4 = 124,\n\tGP_3_27_DATA___5 = 125,\n\tGP_3_28_DATA___5 = 126,\n\tGP_3_29_DATA___5 = 127,\n\tGP_3_30_DATA___4 = 128,\n\tGP_3_31_DATA___4 = 129,\n\tGP_4_0_DATA___5 = 130,\n\tGP_4_1_DATA___5 = 131,\n\tGP_4_2_DATA___5 = 132,\n\tGP_4_3_DATA___5 = 133,\n\tGP_4_4_DATA___5 = 134,\n\tGP_4_5_DATA___5 = 135,\n\tGP_4_6_DATA___5 = 136,\n\tGP_4_7_DATA___5 = 137,\n\tGP_4_8_DATA___5 = 138,\n\tGP_4_9_DATA___5 = 139,\n\tGP_4_10_DATA___5 = 140,\n\tGP_4_11_DATA___5 = 141,\n\tGP_4_12_DATA___5 = 142,\n\tGP_4_13_DATA___5 = 143,\n\tGP_4_14_DATA___5 = 144,\n\tGP_4_15_DATA___5 = 145,\n\tGP_4_16_DATA___5 = 146,\n\tGP_4_17_DATA___5 = 147,\n\tGP_4_18_DATA___5 = 148,\n\tGP_4_19_DATA___5 = 149,\n\tGP_4_20_DATA___5 = 150,\n\tGP_4_21_DATA___5 = 151,\n\tGP_4_22_DATA___5 = 152,\n\tGP_4_23_DATA___5 = 153,\n\tGP_4_24_DATA___5 = 154,\n\tGP_4_25_DATA___5 = 155,\n\tGP_4_26_DATA___4 = 156,\n\tPINMUX_DATA_END___8 = 157,\n\tPINMUX_FUNCTION_BEGIN___8 = 158,\n\tGP_0_0_FN___5 = 159,\n\tGP_0_1_FN___5 = 160,\n\tGP_0_2_FN___5 = 161,\n\tGP_0_3_FN___5 = 162,\n\tGP_0_4_FN___5 = 163,\n\tGP_0_5_FN___5 = 164,\n\tGP_0_6_FN___5 = 165,\n\tGP_0_7_FN___5 = 166,\n\tGP_0_8_FN___5 = 167,\n\tGP_0_9_FN___5 = 168,\n\tGP_0_10_FN___5 = 169,\n\tGP_0_11_FN___5 = 170,\n\tGP_0_12_FN___5 = 171,\n\tGP_0_13_FN___5 = 172,\n\tGP_0_14_FN___5 = 173,\n\tGP_0_15_FN___5 = 174,\n\tGP_0_16_FN___5 = 175,\n\tGP_0_17_FN___5 = 176,\n\tGP_0_18_FN___5 = 177,\n\tGP_0_19_FN___5 = 178,\n\tGP_0_20_FN___5 = 179,\n\tGP_0_21_FN___5 = 180,\n\tGP_0_22_FN___5 = 181,\n\tGP_0_23_FN___4 = 182,\n\tGP_0_24_FN___4 = 183,\n\tGP_0_25_FN___4 = 184,\n\tGP_0_26_FN___4 = 185,\n\tGP_0_27_FN___4 = 186,\n\tGP_0_28_FN___4 = 187,\n\tGP_0_29_FN___4 = 188,\n\tGP_0_30_FN___4 = 189,\n\tGP_0_31_FN___4 = 190,\n\tGP_1_0_FN___5 = 191,\n\tGP_1_1_FN___5 = 192,\n\tGP_1_2_FN___5 = 193,\n\tGP_1_3_FN___5 = 194,\n\tGP_1_4_FN___5 = 195,\n\tGP_1_5_FN___5 = 196,\n\tGP_1_6_FN___5 = 197,\n\tGP_1_7_FN___5 = 198,\n\tGP_1_8_FN___5 = 199,\n\tGP_1_9_FN___5 = 200,\n\tGP_1_10_FN___5 = 201,\n\tGP_1_11_FN___5 = 202,\n\tGP_1_12_FN___5 = 203,\n\tGP_1_13_FN___5 = 204,\n\tGP_1_14_FN___5 = 205,\n\tGP_1_15_FN___5 = 206,\n\tGP_1_16_FN___5 = 207,\n\tGP_1_17_FN___5 = 208,\n\tGP_1_18_FN___5 = 209,\n\tGP_1_19_FN___5 = 210,\n\tGP_1_20_FN___5 = 211,\n\tGP_1_21_FN___5 = 212,\n\tGP_1_22_FN___5 = 213,\n\tGP_1_23_FN___4 = 214,\n\tGP_1_24_FN___4 = 215,\n\tGP_1_25_FN___4 = 216,\n\tGP_1_26_FN___2 = 217,\n\tGP_1_27_FN___2 = 218,\n\tGP_1_28_FN___2 = 219,\n\tGP_1_29_FN___2 = 220,\n\tGP_1_30_FN___2 = 221,\n\tGP_1_31_FN___2 = 222,\n\tGP_2_0_FN___5 = 223,\n\tGP_2_1_FN___5 = 224,\n\tGP_2_2_FN___5 = 225,\n\tGP_2_3_FN___5 = 226,\n\tGP_2_4_FN___5 = 227,\n\tGP_2_5_FN___5 = 228,\n\tGP_2_6_FN___5 = 229,\n\tGP_2_7_FN___5 = 230,\n\tGP_2_8_FN___5 = 231,\n\tGP_2_9_FN___5 = 232,\n\tGP_2_10_FN___5 = 233,\n\tGP_2_11_FN___5 = 234,\n\tGP_2_12_FN___5 = 235,\n\tGP_2_13_FN___5 = 236,\n\tGP_2_14_FN___5 = 237,\n\tGP_2_15_FN___5 = 238,\n\tGP_2_16_FN___5 = 239,\n\tGP_2_17_FN___5 = 240,\n\tGP_2_18_FN___5 = 241,\n\tGP_2_19_FN___5 = 242,\n\tGP_2_20_FN___5 = 243,\n\tGP_2_21_FN___5 = 244,\n\tGP_2_22_FN___5 = 245,\n\tGP_2_23_FN___5 = 246,\n\tGP_2_24_FN___5 = 247,\n\tGP_2_25_FN___5 = 248,\n\tGP_2_26_FN___5 = 249,\n\tGP_2_27_FN___5 = 250,\n\tGP_2_28_FN___5 = 251,\n\tGP_2_29_FN___5 = 252,\n\tGP_2_30_FN___5 = 253,\n\tGP_2_31_FN___5 = 254,\n\tGP_3_0_FN___5 = 255,\n\tGP_3_1_FN___5 = 256,\n\tGP_3_2_FN___5 = 257,\n\tGP_3_3_FN___5 = 258,\n\tGP_3_4_FN___5 = 259,\n\tGP_3_5_FN___5 = 260,\n\tGP_3_6_FN___5 = 261,\n\tGP_3_7_FN___5 = 262,\n\tGP_3_8_FN___5 = 263,\n\tGP_3_9_FN___5 = 264,\n\tGP_3_10_FN___5 = 265,\n\tGP_3_11_FN___5 = 266,\n\tGP_3_12_FN___5 = 267,\n\tGP_3_13_FN___5 = 268,\n\tGP_3_14_FN___5 = 269,\n\tGP_3_15_FN___5 = 270,\n\tGP_3_16_FN___5 = 271,\n\tGP_3_17_FN___4 = 272,\n\tGP_3_18_FN___4 = 273,\n\tGP_3_19_FN___4 = 274,\n\tGP_3_20_FN___4 = 275,\n\tGP_3_21_FN___4 = 276,\n\tGP_3_22_FN___4 = 277,\n\tGP_3_23_FN___4 = 278,\n\tGP_3_24_FN___4 = 279,\n\tGP_3_25_FN___4 = 280,\n\tGP_3_26_FN___4 = 281,\n\tGP_3_27_FN___5 = 282,\n\tGP_3_28_FN___5 = 283,\n\tGP_3_29_FN___5 = 284,\n\tGP_3_30_FN___4 = 285,\n\tGP_3_31_FN___4 = 286,\n\tGP_4_0_FN___5 = 287,\n\tGP_4_1_FN___5 = 288,\n\tGP_4_2_FN___5 = 289,\n\tGP_4_3_FN___5 = 290,\n\tGP_4_4_FN___5 = 291,\n\tGP_4_5_FN___5 = 292,\n\tGP_4_6_FN___5 = 293,\n\tGP_4_7_FN___5 = 294,\n\tGP_4_8_FN___5 = 295,\n\tGP_4_9_FN___5 = 296,\n\tGP_4_10_FN___5 = 297,\n\tGP_4_11_FN___5 = 298,\n\tGP_4_12_FN___5 = 299,\n\tGP_4_13_FN___5 = 300,\n\tGP_4_14_FN___5 = 301,\n\tGP_4_15_FN___5 = 302,\n\tGP_4_16_FN___5 = 303,\n\tGP_4_17_FN___5 = 304,\n\tGP_4_18_FN___5 = 305,\n\tGP_4_19_FN___5 = 306,\n\tGP_4_20_FN___5 = 307,\n\tGP_4_21_FN___5 = 308,\n\tGP_4_22_FN___5 = 309,\n\tGP_4_23_FN___5 = 310,\n\tGP_4_24_FN___5 = 311,\n\tGP_4_25_FN___5 = 312,\n\tGP_4_26_FN___4 = 313,\n\tFN_IP0_1_0 = 314,\n\tFN_PENC0 = 315,\n\tFN_PENC1 = 316,\n\tFN_IP0_4_2 = 317,\n\tFN_IP0_7_5 = 318,\n\tFN_IP0_11_8___2 = 319,\n\tFN_IP0_14_12 = 320,\n\tFN_A1___5 = 321,\n\tFN_A2___5 = 322,\n\tFN_A3___5 = 323,\n\tFN_IP0_15___3 = 324,\n\tFN_IP0_16___2 = 325,\n\tFN_IP0_17___2 = 326,\n\tFN_IP0_18 = 327,\n\tFN_IP0_19 = 328,\n\tFN_IP0_20 = 329,\n\tFN_IP0_21 = 330,\n\tFN_IP0_22 = 331,\n\tFN_IP0_23 = 332,\n\tFN_IP0_24___2 = 333,\n\tFN_IP0_25___3 = 334,\n\tFN_IP0_26 = 335,\n\tFN_IP0_27 = 336,\n\tFN_IP0_28 = 337,\n\tFN_IP0_29 = 338,\n\tFN_IP0_30 = 339,\n\tFN_IP1_0 = 340,\n\tFN_IP1_1 = 341,\n\tFN_IP1_4_2 = 342,\n\tFN_IP1_7_5 = 343,\n\tFN_IP1_10_8___3 = 344,\n\tFN_IP1_14_11___2 = 345,\n\tFN_IP1_23_21 = 346,\n\tFN_WE0___2 = 347,\n\tFN_IP1_24___2 = 348,\n\tFN_IP1_27_25 = 349,\n\tFN_IP1_29_28___2 = 350,\n\tFN_IP2_2_0___2 = 351,\n\tFN_IP2_5_3 = 352,\n\tFN_IP2_8_6 = 353,\n\tFN_IP2_11_9 = 354,\n\tFN_IP2_13_12___2 = 355,\n\tFN_IP2_16_14 = 356,\n\tFN_IP2_17 = 357,\n\tFN_IP2_30 = 358,\n\tFN_IP2_31 = 359,\n\tFN_IP3_1_0___2 = 360,\n\tFN_IP3_4_2 = 361,\n\tFN_IP3_7_5 = 362,\n\tFN_IP3_9_8___2 = 363,\n\tFN_IP3_12_10 = 364,\n\tFN_IP3_15_13 = 365,\n\tFN_IP3_18_16 = 366,\n\tFN_IP3_20_19 = 367,\n\tFN_IP3_23_21___2 = 368,\n\tFN_IP3_26_24___3 = 369,\n\tFN_IP3_27___2 = 370,\n\tFN_IP3_28___2 = 371,\n\tFN_IP3_29 = 372,\n\tFN_IP3_30___2 = 373,\n\tFN_IP3_31___2 = 374,\n\tFN_IP4_0 = 375,\n\tFN_IP4_3_1 = 376,\n\tFN_IP4_6_4 = 377,\n\tFN_IP4_7 = 378,\n\tFN_IP4_8 = 379,\n\tFN_IP4_10_9 = 380,\n\tFN_IP4_12_11 = 381,\n\tFN_IP4_14_13 = 382,\n\tFN_IP4_16_15 = 383,\n\tFN_IP4_20_17 = 384,\n\tFN_IP4_24_21 = 385,\n\tFN_IP4_26_25 = 386,\n\tFN_IP4_28_27 = 387,\n\tFN_IP4_30_29 = 388,\n\tFN_IP5_1_0___2 = 389,\n\tFN_IP5_3_2___2 = 390,\n\tFN_IP5_5_4___2 = 391,\n\tFN_IP5_6___2 = 392,\n\tFN_IP5_7___2 = 393,\n\tFN_IP5_9_8 = 394,\n\tFN_IP5_11_10 = 395,\n\tFN_IP5_12 = 396,\n\tFN_IP5_14_13___2 = 397,\n\tFN_IP5_17_15 = 398,\n\tFN_IP5_20_18 = 399,\n\tFN_AUDIO_CLKA___4 = 400,\n\tFN_AUDIO_CLKB___4 = 401,\n\tFN_IP5_22_21 = 402,\n\tFN_IP5_25_23 = 403,\n\tFN_IP5_28_26___2 = 404,\n\tFN_IP5_30_29___2 = 405,\n\tFN_IP6_1_0___3 = 406,\n\tFN_IP6_4_2 = 407,\n\tFN_IP6_6_5 = 408,\n\tFN_IP6_7 = 409,\n\tFN_IP6_8___3 = 410,\n\tFN_IP6_9___2 = 411,\n\tFN_SSI_SCK34___5 = 412,\n\tFN_IP6_10___2 = 413,\n\tFN_IP6_12_11 = 414,\n\tFN_IP6_13___2 = 415,\n\tFN_IP6_15_14___2 = 416,\n\tFN_IP6_16___2 = 417,\n\tFN_IP6_18_17 = 418,\n\tFN_IP6_20_19___2 = 419,\n\tFN_IP6_21 = 420,\n\tFN_IP6_23_22 = 421,\n\tFN_IP6_25_24 = 422,\n\tFN_IP6_27_26 = 423,\n\tFN_IP6_29_28 = 424,\n\tFN_IP6_31_30 = 425,\n\tFN_IP7_1_0___2 = 426,\n\tFN_IP7_3_2___2 = 427,\n\tFN_IP7_5_4 = 428,\n\tFN_IP7_8_6___3 = 429,\n\tFN_IP7_11_9___2 = 430,\n\tFN_IP7_14_12___2 = 431,\n\tFN_IP7_17_15___2 = 432,\n\tFN_IP7_20_18___2 = 433,\n\tFN_IP7_21 = 434,\n\tFN_IP7_24_22 = 435,\n\tFN_IP7_28_25 = 436,\n\tFN_IP7_31_29 = 437,\n\tFN_IP8_2_0___3 = 438,\n\tFN_IP8_5_3___3 = 439,\n\tFN_IP8_8_6___3 = 440,\n\tFN_IP8_10_9 = 441,\n\tFN_IP8_13_11 = 442,\n\tFN_IP8_15_14 = 443,\n\tFN_IP8_18_16 = 444,\n\tFN_IP8_21_19 = 445,\n\tFN_IP8_23_22 = 446,\n\tFN_IP8_26_24 = 447,\n\tFN_IP8_29_27 = 448,\n\tFN_IP9_2_0___3 = 449,\n\tFN_IP9_5_3___3 = 450,\n\tFN_IP9_8_6___2 = 451,\n\tFN_IP9_11_9___2 = 452,\n\tFN_IP9_14_12___2 = 453,\n\tFN_IP9_17_15 = 454,\n\tFN_IP9_20_18 = 455,\n\tFN_IP9_23_21 = 456,\n\tFN_IP9_26_24 = 457,\n\tFN_IP9_29_27 = 458,\n\tFN_IP10_2_0___4 = 459,\n\tFN_IP10_5_3___4 = 460,\n\tFN_IP10_8_6___4 = 461,\n\tFN_IP10_12_9 = 462,\n\tFN_IP10_15_13 = 463,\n\tFN_IP10_18_16 = 464,\n\tFN_IP10_21_19___2 = 465,\n\tFN_IP10_24_22___2 = 466,\n\tFN_AVS1___2 = 467,\n\tFN_AVS2___2 = 468,\n\tFN_PRESETOUT = 469,\n\tFN_PWM1___4 = 470,\n\tFN_AUDATA0___2 = 471,\n\tFN_ARM_TRACEDATA_0___2 = 472,\n\tFN_GPSCLK_C = 473,\n\tFN_USB_OVC0___2 = 474,\n\tFN_TX2_E___3 = 475,\n\tFN_SDA2_B___3 = 476,\n\tFN_AUDATA1___2 = 477,\n\tFN_ARM_TRACEDATA_1___2 = 478,\n\tFN_GPSIN_C = 479,\n\tFN_USB_OVC1___2 = 480,\n\tFN_RX2_E___3 = 481,\n\tFN_SCL2_B___3 = 482,\n\tFN_SD1_DAT2_A = 483,\n\tFN_MMC_D2___3 = 484,\n\tFN_BS___2 = 485,\n\tFN_ATADIR0_A = 486,\n\tFN_SDSELF_A = 487,\n\tFN_PWM4_B___4 = 488,\n\tFN_SD1_DAT3_A = 489,\n\tFN_MMC_D3___3 = 490,\n\tFN_A0___5 = 491,\n\tFN_ATAG0_A = 492,\n\tFN_REMOCON_B___4 = 493,\n\tFN_A4___5 = 494,\n\tFN_A5___5 = 495,\n\tFN_A6___5 = 496,\n\tFN_A7___5 = 497,\n\tFN_A8___5 = 498,\n\tFN_A9___5 = 499,\n\tFN_A10___5 = 500,\n\tFN_A11___5 = 501,\n\tFN_A12___5 = 502,\n\tFN_A13___5 = 503,\n\tFN_A14___5 = 504,\n\tFN_A15___5 = 505,\n\tFN_A16___5 = 506,\n\tFN_A17___5 = 507,\n\tFN_A18___5 = 508,\n\tFN_A19___5 = 509,\n\tFN_A20___5 = 510,\n\tFN_HSPI_CS1_B___2 = 511,\n\tFN_A21___5 = 512,\n\tFN_HSPI_CLK1_B___2 = 513,\n\tFN_A22___5 = 514,\n\tFN_HRTS0_B___2 = 515,\n\tFN_RX2_B___4 = 516,\n\tFN_DREQ2_A = 517,\n\tFN_A23___5 = 518,\n\tFN_HTX0_B___4 = 519,\n\tFN_TX2_B___4 = 520,\n\tFN_DACK2_A = 521,\n\tFN_TS_SDEN0_A = 522,\n\tFN_SD1_CD_A = 523,\n\tFN_MMC_D6___3 = 524,\n\tFN_A24___5 = 525,\n\tFN_DREQ1_A = 526,\n\tFN_HRX0_B___4 = 527,\n\tFN_TS_SPSYNC0_A = 528,\n\tFN_SD1_WP_A = 529,\n\tFN_MMC_D7___3 = 530,\n\tFN_A25___5 = 531,\n\tFN_DACK1_A = 532,\n\tFN_HCTS0_B___2 = 533,\n\tFN_RX3_C___3 = 534,\n\tFN_TS_SDAT0_A = 535,\n\tFN_CLKOUT___3 = 536,\n\tFN_HSPI_TX1_B___2 = 537,\n\tFN_PWM0_B___5 = 538,\n\tFN_CS0___2 = 539,\n\tFN_HSPI_RX1_B___2 = 540,\n\tFN_SSI_SCK1_B___4 = 541,\n\tFN_ATAG0_B = 542,\n\tFN_CS1_A26___2 = 543,\n\tFN_SDA2_A___2 = 544,\n\tFN_SCK2_B___2 = 545,\n\tFN_MMC_D5___3 = 546,\n\tFN_ATADIR0_B = 547,\n\tFN_RD_WR___2 = 548,\n\tFN_WE1___2 = 549,\n\tFN_ATAWR0_B = 550,\n\tFN_SSI_WS1_B___4 = 551,\n\tFN_EX_CS0___2 = 552,\n\tFN_SCL2_A___2 = 553,\n\tFN_TX3_C___3 = 554,\n\tFN_TS_SCK0_A = 555,\n\tFN_EX_CS1___2 = 556,\n\tFN_MMC_D4___3 = 557,\n\tFN_SD1_CLK_A = 558,\n\tFN_MMC_CLK___3 = 559,\n\tFN_ATACS00___2 = 560,\n\tFN_EX_CS2___2 = 561,\n\tFN_SD1_CMD_A = 562,\n\tFN_MMC_CMD___3 = 563,\n\tFN_ATACS10___2 = 564,\n\tFN_EX_CS3___2 = 565,\n\tFN_SD1_DAT0_A = 566,\n\tFN_MMC_D0___3 = 567,\n\tFN_ATARD0___2 = 568,\n\tFN_EX_CS4___2 = 569,\n\tFN_EX_WAIT1_A = 570,\n\tFN_SD1_DAT1_A = 571,\n\tFN_MMC_D1___3 = 572,\n\tFN_ATAWR0_A = 573,\n\tFN_EX_CS5___2 = 574,\n\tFN_EX_WAIT2_A = 575,\n\tFN_DREQ0_A = 576,\n\tFN_RX3_A___2 = 577,\n\tFN_DACK0___5 = 578,\n\tFN_TX3_A___2 = 579,\n\tFN_DRACK0___5 = 580,\n\tFN_EX_WAIT0___5 = 581,\n\tFN_PWM0_C___3 = 582,\n\tFN_D0___4 = 583,\n\tFN_D1___4 = 584,\n\tFN_D2___4 = 585,\n\tFN_D3___4 = 586,\n\tFN_D4___4 = 587,\n\tFN_D5___4 = 588,\n\tFN_D6___4 = 589,\n\tFN_D7___4 = 590,\n\tFN_D8___4 = 591,\n\tFN_D9___4 = 592,\n\tFN_D10___4 = 593,\n\tFN_D11___4 = 594,\n\tFN_RD_WR_B = 595,\n\tFN_IRQ0___5 = 596,\n\tFN_MLB_CLK___4 = 597,\n\tFN_IRQ1_A = 598,\n\tFN_MLB_SIG___4 = 599,\n\tFN_RX5_B___4 = 600,\n\tFN_SDA3_A___2 = 601,\n\tFN_IRQ2_A = 602,\n\tFN_MLB_DAT___4 = 603,\n\tFN_TX5_B___4 = 604,\n\tFN_SCL3_A___2 = 605,\n\tFN_IRQ3_A = 606,\n\tFN_SDSELF_B___2 = 607,\n\tFN_SD1_CMD_B = 608,\n\tFN_SCIF_CLK___4 = 609,\n\tFN_AUDIO_CLKOUT_B___4 = 610,\n\tFN_CAN_CLK_B___5 = 611,\n\tFN_SDA3_B___3 = 612,\n\tFN_SD1_CLK_B = 613,\n\tFN_HTX0_A___2 = 614,\n\tFN_TX0_A___2 = 615,\n\tFN_SD1_DAT0_B = 616,\n\tFN_HRX0_A___2 = 617,\n\tFN_RX0_A___2 = 618,\n\tFN_SD1_DAT1_B = 619,\n\tFN_HSCK0___4 = 620,\n\tFN_SCK0___2 = 621,\n\tFN_SCL3_B___3 = 622,\n\tFN_SD1_DAT2_B = 623,\n\tFN_HCTS0_A = 624,\n\tFN_CTS0___2 = 625,\n\tFN_SD1_DAT3_B = 626,\n\tFN_HRTS0_A = 627,\n\tFN_RTS0 = 628,\n\tFN_SSI_SCK4___4 = 629,\n\tFN_DU0_DR0___4 = 630,\n\tFN_LCDOUT0___4 = 631,\n\tFN_AUDATA2___2 = 632,\n\tFN_ARM_TRACEDATA_2___2 = 633,\n\tFN_SDA3_C___2 = 634,\n\tFN_ADICHS1___4 = 635,\n\tFN_TS_SDEN0_B___2 = 636,\n\tFN_SSI_WS4___4 = 637,\n\tFN_DU0_DR1___4 = 638,\n\tFN_LCDOUT1___4 = 639,\n\tFN_AUDATA3___2 = 640,\n\tFN_ARM_TRACEDATA_3___2 = 641,\n\tFN_SCL3_C___2 = 642,\n\tFN_ADICHS2___4 = 643,\n\tFN_TS_SPSYNC0_B___2 = 644,\n\tFN_DU0_DR2___4 = 645,\n\tFN_LCDOUT2___4 = 646,\n\tFN_DU0_DR3___4 = 647,\n\tFN_LCDOUT3___4 = 648,\n\tFN_DU0_DR4___4 = 649,\n\tFN_LCDOUT4___4 = 650,\n\tFN_DU0_DR5___4 = 651,\n\tFN_LCDOUT5___4 = 652,\n\tFN_DU0_DR6___4 = 653,\n\tFN_LCDOUT6___4 = 654,\n\tFN_DU0_DR7___4 = 655,\n\tFN_LCDOUT7___4 = 656,\n\tFN_DU0_DG0___4 = 657,\n\tFN_LCDOUT8___4 = 658,\n\tFN_AUDATA4___2 = 659,\n\tFN_ARM_TRACEDATA_4___2 = 660,\n\tFN_TX1_D___3 = 661,\n\tFN_CAN0_TX_A___2 = 662,\n\tFN_ADICHS0___4 = 663,\n\tFN_DU0_DG1___4 = 664,\n\tFN_LCDOUT9___4 = 665,\n\tFN_AUDATA5___2 = 666,\n\tFN_ARM_TRACEDATA_5___2 = 667,\n\tFN_RX1_D___3 = 668,\n\tFN_CAN0_RX_A___2 = 669,\n\tFN_ADIDATA___4 = 670,\n\tFN_DU0_DG2___4 = 671,\n\tFN_LCDOUT10___4 = 672,\n\tFN_DU0_DG3___4 = 673,\n\tFN_LCDOUT11___4 = 674,\n\tFN_DU0_DG4___4 = 675,\n\tFN_LCDOUT12___4 = 676,\n\tFN_RX0_B___4 = 677,\n\tFN_DU0_DG5___4 = 678,\n\tFN_LCDOUT13___4 = 679,\n\tFN_TX0_B___4 = 680,\n\tFN_DU0_DG6___4 = 681,\n\tFN_LCDOUT14___4 = 682,\n\tFN_RX4_A___2 = 683,\n\tFN_DU0_DG7___4 = 684,\n\tFN_LCDOUT15___4 = 685,\n\tFN_TX4_A___2 = 686,\n\tFN_SSI_SCK2_B___3 = 687,\n\tFN_VI0_R0_B = 688,\n\tFN_DU0_DB0___4 = 689,\n\tFN_LCDOUT16___4 = 690,\n\tFN_AUDATA6___2 = 691,\n\tFN_ARM_TRACEDATA_6___2 = 692,\n\tFN_GPSCLK_A = 693,\n\tFN_PWM0_A___2 = 694,\n\tFN_ADICLK___4 = 695,\n\tFN_TS_SDAT0_B = 696,\n\tFN_AUDIO_CLKC___4 = 697,\n\tFN_VI0_R1_B = 698,\n\tFN_DU0_DB1___4 = 699,\n\tFN_LCDOUT17___4 = 700,\n\tFN_AUDATA7___2 = 701,\n\tFN_ARM_TRACEDATA_7___2 = 702,\n\tFN_GPSIN_A = 703,\n\tFN_ADICS_SAMP___4 = 704,\n\tFN_TS_SCK0_B___2 = 705,\n\tFN_VI0_R2_B = 706,\n\tFN_DU0_DB2___4 = 707,\n\tFN_LCDOUT18___4 = 708,\n\tFN_VI0_R3_B = 709,\n\tFN_DU0_DB3___4 = 710,\n\tFN_LCDOUT19___4 = 711,\n\tFN_VI0_R4_B = 712,\n\tFN_DU0_DB4___4 = 713,\n\tFN_LCDOUT20___4 = 714,\n\tFN_VI0_R5_B = 715,\n\tFN_DU0_DB5___4 = 716,\n\tFN_LCDOUT21___4 = 717,\n\tFN_VI1_DATA10_B = 718,\n\tFN_DU0_DB6___4 = 719,\n\tFN_LCDOUT22___4 = 720,\n\tFN_VI1_DATA11_B = 721,\n\tFN_DU0_DB7___4 = 722,\n\tFN_LCDOUT23___4 = 723,\n\tFN_DU0_DOTCLKIN___5 = 724,\n\tFN_QSTVA_QVS___4 = 725,\n\tFN_DU0_DOTCLKO_UT0 = 726,\n\tFN_QCLK___4 = 727,\n\tFN_DU0_DOTCLKO_UT1 = 728,\n\tFN_QSTVB_QVE___4 = 729,\n\tFN_AUDIO_CLKOUT_A___2 = 730,\n\tFN_REMOCON_C = 731,\n\tFN_SSI_WS2_B___3 = 732,\n\tFN_DU0_EXHSYNC_DU0_HSYNC___4 = 733,\n\tFN_QSTH_QHS___4 = 734,\n\tFN_DU0_EXVSYNC_DU0_VSYNC___4 = 735,\n\tFN_QSTB_QHE___4 = 736,\n\tFN_DU0_EXODDF_DU0_ODDF_DISP_CDE___4 = 737,\n\tFN_QCPV_QDE___4 = 738,\n\tFN_FMCLK_D___3 = 739,\n\tFN_SSI_SCK1_A___2 = 740,\n\tFN_DU0_DISP___4 = 741,\n\tFN_QPOLA___4 = 742,\n\tFN_AUDCK___2 = 743,\n\tFN_ARM_TRACECLK = 744,\n\tFN_BPFCLK_D___3 = 745,\n\tFN_SSI_WS1_A___2 = 746,\n\tFN_DU0_CDE___4 = 747,\n\tFN_QPOLB___4 = 748,\n\tFN_AUDSYNC___2 = 749,\n\tFN_ARM_TRACECTL = 750,\n\tFN_FMIN_D___3 = 751,\n\tFN_SD1_CD_B = 752,\n\tFN_SSI_SCK78___4 = 753,\n\tFN_HSPI_RX0_B = 754,\n\tFN_TX1_B___4 = 755,\n\tFN_SD1_WP_B = 756,\n\tFN_SSI_WS78___4 = 757,\n\tFN_HSPI_CLK0_B = 758,\n\tFN_RX1_B___4 = 759,\n\tFN_CAN_CLK_D___4 = 760,\n\tFN_SSI_SDATA8___4 = 761,\n\tFN_SSI_SCK2_A___2 = 762,\n\tFN_HSPI_CS0_B = 763,\n\tFN_TX2_A___2 = 764,\n\tFN_CAN0_TX_B___5 = 765,\n\tFN_SSI_SDATA7___4 = 766,\n\tFN_HSPI_TX0_B = 767,\n\tFN_RX2_A___2 = 768,\n\tFN_CAN0_RX_B___5 = 769,\n\tFN_SSI_SCK6___4 = 770,\n\tFN_HSPI_RX2_A = 771,\n\tFN_FMCLK_B___3 = 772,\n\tFN_CAN1_TX_B___4 = 773,\n\tFN_SSI_WS6___4 = 774,\n\tFN_HSPI_CLK2_A = 775,\n\tFN_BPFCLK_B___3 = 776,\n\tFN_CAN1_RX_B___4 = 777,\n\tFN_SSI_SDATA6___4 = 778,\n\tFN_HSPI_TX2_A = 779,\n\tFN_FMIN_B___3 = 780,\n\tFN_SSI_SCK5___4 = 781,\n\tFN_RX4_C___4 = 782,\n\tFN_SSI_WS5___4 = 783,\n\tFN_TX4_C___4 = 784,\n\tFN_SSI_SDATA5___4 = 785,\n\tFN_RX0_D___4 = 786,\n\tFN_SSI_WS34___5 = 787,\n\tFN_ARM_TRACEDATA_8___2 = 788,\n\tFN_SSI_SDATA4___4 = 789,\n\tFN_SSI_WS2_A___2 = 790,\n\tFN_ARM_TRACEDATA_9___2 = 791,\n\tFN_SSI_SDATA3___5 = 792,\n\tFN_ARM_TRACEDATA_10___2 = 793,\n\tFN_SSI_SCK012 = 794,\n\tFN_ARM_TRACEDATA_11___2 = 795,\n\tFN_TX0_D___4 = 796,\n\tFN_SSI_WS012 = 797,\n\tFN_ARM_TRACEDATA_12___2 = 798,\n\tFN_SSI_SDATA2___4 = 799,\n\tFN_HSPI_CS2_A = 800,\n\tFN_ARM_TRACEDATA_13___2 = 801,\n\tFN_SDA1_A___2 = 802,\n\tFN_SSI_SDATA1___4 = 803,\n\tFN_ARM_TRACEDATA_14___2 = 804,\n\tFN_SCL1_A___2 = 805,\n\tFN_SCK2_A = 806,\n\tFN_SSI_SDATA0___4 = 807,\n\tFN_ARM_TRACEDATA_15___2 = 808,\n\tFN_SD0_CLK___5 = 809,\n\tFN_SUB_TDO___2 = 810,\n\tFN_SD0_CMD___5 = 811,\n\tFN_SUB_TRST___2 = 812,\n\tFN_SD0_DAT0___3 = 813,\n\tFN_SUB_TMS___2 = 814,\n\tFN_SD0_DAT1___3 = 815,\n\tFN_SUB_TCK___2 = 816,\n\tFN_SD0_DAT2___3 = 817,\n\tFN_SUB_TDI___2 = 818,\n\tFN_SD0_DAT3___3 = 819,\n\tFN_IRQ1_B___2 = 820,\n\tFN_SD0_CD___5 = 821,\n\tFN_TX5_A___2 = 822,\n\tFN_SD0_WP___5 = 823,\n\tFN_RX5_A___2 = 824,\n\tFN_VI1_CLKENB___5 = 825,\n\tFN_HSPI_CLK0_A = 826,\n\tFN_HTX1_A___2 = 827,\n\tFN_RTS1_C = 828,\n\tFN_VI1_FIELD___5 = 829,\n\tFN_HSPI_CS0_A = 830,\n\tFN_HRX1_A___2 = 831,\n\tFN_SCK1_C___2 = 832,\n\tFN_VI1_HSYNC___2 = 833,\n\tFN_HSPI_RX0_A = 834,\n\tFN_HRTS1_A = 835,\n\tFN_FMCLK_A = 836,\n\tFN_RX1_C___4 = 837,\n\tFN_VI1_VSYNC___2 = 838,\n\tFN_HSPI_TX0___2 = 839,\n\tFN_HCTS1_A = 840,\n\tFN_BPFCLK_A = 841,\n\tFN_TX1_C___4 = 842,\n\tFN_TCLK0___2 = 843,\n\tFN_HSCK1_A = 844,\n\tFN_FMIN_A = 845,\n\tFN_IRQ2_C = 846,\n\tFN_CTS1_C___2 = 847,\n\tFN_SPEEDIN___4 = 848,\n\tFN_VI0_CLK___5 = 849,\n\tFN_CAN_CLK_A___2 = 850,\n\tFN_VI0_CLKENB___5 = 851,\n\tFN_SD2_DAT2_B___2 = 852,\n\tFN_VI1_DATA0___4 = 853,\n\tFN_DU1_DG6___5 = 854,\n\tFN_HSPI_RX1_A = 855,\n\tFN_RX4_B___4 = 856,\n\tFN_VI0_FIELD___5 = 857,\n\tFN_SD2_DAT3_B___2 = 858,\n\tFN_VI0_R3_C = 859,\n\tFN_VI1_DATA1___4 = 860,\n\tFN_DU1_DG7___5 = 861,\n\tFN_HSPI_CLK1_A = 862,\n\tFN_TX4_B___4 = 863,\n\tFN_VI0_HSYNC___2 = 864,\n\tFN_SD2_CD_B___2 = 865,\n\tFN_VI1_DATA2___4 = 866,\n\tFN_DU1_DR2___5 = 867,\n\tFN_HSPI_CS1_A = 868,\n\tFN_RX3_B___3 = 869,\n\tFN_VI0_VSYNC___2 = 870,\n\tFN_SD2_WP_B___2 = 871,\n\tFN_VI1_DATA3___4 = 872,\n\tFN_DU1_DR3___5 = 873,\n\tFN_HSPI_TX1_A = 874,\n\tFN_TX3_B___3 = 875,\n\tFN_VI0_DATA0_VI0_B0___5 = 876,\n\tFN_DU1_DG2___5 = 877,\n\tFN_IRQ2_B___2 = 878,\n\tFN_RX3_D___2 = 879,\n\tFN_VI0_DATA1_VI0_B1___5 = 880,\n\tFN_DU1_DG3___5 = 881,\n\tFN_IRQ3_B___2 = 882,\n\tFN_TX3_D___2 = 883,\n\tFN_VI0_DATA2_VI0_B2___5 = 884,\n\tFN_DU1_DG4___5 = 885,\n\tFN_RX0_C___4 = 886,\n\tFN_VI0_DATA3_VI0_B3___5 = 887,\n\tFN_DU1_DG5___5 = 888,\n\tFN_TX1_A___2 = 889,\n\tFN_TX0_C___4 = 890,\n\tFN_VI0_DATA4_VI0_B4___5 = 891,\n\tFN_DU1_DB2___5 = 892,\n\tFN_RX1_A___2 = 893,\n\tFN_VI0_DATA5_VI0_B5___5 = 894,\n\tFN_DU1_DB3___5 = 895,\n\tFN_SCK1_A = 896,\n\tFN_PWM4___4 = 897,\n\tFN_HSCK1_B___2 = 898,\n\tFN_VI0_DATA6_VI0_G0 = 899,\n\tFN_DU1_DB4___5 = 900,\n\tFN_CTS1_A = 901,\n\tFN_PWM5___4 = 902,\n\tFN_VI0_DATA7_VI0_G1 = 903,\n\tFN_DU1_DB5___5 = 904,\n\tFN_RTS1_A = 905,\n\tFN_VI0_G2___5 = 906,\n\tFN_SD2_CLK_B___2 = 907,\n\tFN_VI1_DATA4___4 = 908,\n\tFN_DU1_DR4___5 = 909,\n\tFN_HTX1_B___4 = 910,\n\tFN_VI0_G3___5 = 911,\n\tFN_SD2_CMD_B___2 = 912,\n\tFN_VI1_DATA5___4 = 913,\n\tFN_DU1_DR5___5 = 914,\n\tFN_HRX1_B___4 = 915,\n\tFN_VI0_G4___5 = 916,\n\tFN_SD2_DAT0_B___2 = 917,\n\tFN_VI1_DATA6___4 = 918,\n\tFN_DU1_DR6___5 = 919,\n\tFN_HRTS1_B___2 = 920,\n\tFN_VI0_G5___5 = 921,\n\tFN_SD2_DAT1_B___2 = 922,\n\tFN_VI1_DATA7___4 = 923,\n\tFN_DU1_DR7___5 = 924,\n\tFN_HCTS1_B___2 = 925,\n\tFN_VI0_R0_A = 926,\n\tFN_VI1_CLK___5 = 927,\n\tFN_ETH_REF_CLK___2 = 928,\n\tFN_DU1_DOTCLKIN___5 = 929,\n\tFN_VI0_R1_A = 930,\n\tFN_VI1_DATA8___3 = 931,\n\tFN_DU1_DB6___5 = 932,\n\tFN_ETH_TXD0___5 = 933,\n\tFN_PWM2___4 = 934,\n\tFN_TCLK1___4 = 935,\n\tFN_VI0_R2_A = 936,\n\tFN_VI1_DATA9___3 = 937,\n\tFN_DU1_DB7___5 = 938,\n\tFN_ETH_TXD1___5 = 939,\n\tFN_PWM3___4 = 940,\n\tFN_VI0_R3_A = 941,\n\tFN_ETH_CRS_DV___5 = 942,\n\tFN_IECLK___4 = 943,\n\tFN_SCK2_C___2 = 944,\n\tFN_VI0_R4_A = 945,\n\tFN_ETH_TX_EN___5 = 946,\n\tFN_IETX___4 = 947,\n\tFN_TX2_C___4 = 948,\n\tFN_VI0_R5_A = 949,\n\tFN_ETH_RX_ER___5 = 950,\n\tFN_FMCLK_C___3 = 951,\n\tFN_IERX___4 = 952,\n\tFN_RX2_C___4 = 953,\n\tFN_VI1_DATA10_A = 954,\n\tFN_DU1_DOTCLKOUT___2 = 955,\n\tFN_ETH_RXD0___5 = 956,\n\tFN_BPFCLK_C___3 = 957,\n\tFN_TX2_D___2 = 958,\n\tFN_SDA2_C___3 = 959,\n\tFN_VI1_DATA11_A = 960,\n\tFN_DU1_EXHSYNC_DU1_HSYNC___5 = 961,\n\tFN_ETH_RXD1___5 = 962,\n\tFN_FMIN_C___3 = 963,\n\tFN_RX2_D___2 = 964,\n\tFN_SCL2_C___3 = 965,\n\tFN_SD2_CLK_A = 966,\n\tFN_DU1_EXVSYNC_DU1_VSYNC___5 = 967,\n\tFN_ATARD1___2 = 968,\n\tFN_ETH_MDC___5 = 969,\n\tFN_SDA1_B___3 = 970,\n\tFN_SD2_CMD_A = 971,\n\tFN_DU1_EXODDF_DU1_ODDF_DISP_CDE___5 = 972,\n\tFN_ATAWR1___2 = 973,\n\tFN_ETH_MDIO___5 = 974,\n\tFN_SCL1_B___3 = 975,\n\tFN_SD2_DAT0_A = 976,\n\tFN_DU1_DISP___5 = 977,\n\tFN_ATACS01___2 = 978,\n\tFN_DREQ1_B___2 = 979,\n\tFN_ETH_LINK___5 = 980,\n\tFN_CAN1_RX_A___2 = 981,\n\tFN_SD2_DAT1_A = 982,\n\tFN_DU1_CDE___5 = 983,\n\tFN_ATACS11___2 = 984,\n\tFN_DACK1_B___3 = 985,\n\tFN_ETH_MAGIC___5 = 986,\n\tFN_CAN1_TX_A___2 = 987,\n\tFN_PWM6___4 = 988,\n\tFN_SD2_DAT2_A = 989,\n\tFN_VI1_DATA12 = 990,\n\tFN_DREQ2_B___3 = 991,\n\tFN_ATADIR1___2 = 992,\n\tFN_HSPI_CLK2_B___2 = 993,\n\tFN_GPSCLK_B = 994,\n\tFN_SD2_DAT3_A = 995,\n\tFN_VI1_DATA13 = 996,\n\tFN_DACK2_B___3 = 997,\n\tFN_ATAG1___2 = 998,\n\tFN_HSPI_CS2_B___2 = 999,\n\tFN_GPSIN_B = 1000,\n\tFN_SD2_CD_A = 1001,\n\tFN_VI1_DATA14 = 1002,\n\tFN_EX_WAIT1_B = 1003,\n\tFN_DREQ0_B___2 = 1004,\n\tFN_HSPI_RX2_B___2 = 1005,\n\tFN_REMOCON_A___2 = 1006,\n\tFN_SD2_WP_A = 1007,\n\tFN_VI1_DATA15 = 1008,\n\tFN_EX_WAIT2_B = 1009,\n\tFN_DACK0_B___2 = 1010,\n\tFN_HSPI_TX2_B___2 = 1011,\n\tFN_CAN_CLK_C___5 = 1012,\n\tFN_SEL_SCIF5_A = 1013,\n\tFN_SEL_SCIF5_B = 1014,\n\tFN_SEL_SCIF4_A = 1015,\n\tFN_SEL_SCIF4_B = 1016,\n\tFN_SEL_SCIF4_C = 1017,\n\tFN_SEL_SCIF3_A = 1018,\n\tFN_SEL_SCIF3_B = 1019,\n\tFN_SEL_SCIF3_C = 1020,\n\tFN_SEL_SCIF3_D = 1021,\n\tFN_SEL_SCIF2_A = 1022,\n\tFN_SEL_SCIF2_B = 1023,\n\tFN_SEL_SCIF2_C = 1024,\n\tFN_SEL_SCIF2_D = 1025,\n\tFN_SEL_SCIF2_E = 1026,\n\tFN_SEL_SCIF1_A = 1027,\n\tFN_SEL_SCIF1_B = 1028,\n\tFN_SEL_SCIF1_C = 1029,\n\tFN_SEL_SCIF1_D = 1030,\n\tFN_SEL_SCIF0_A = 1031,\n\tFN_SEL_SCIF0_B = 1032,\n\tFN_SEL_SCIF0_C = 1033,\n\tFN_SEL_SCIF0_D = 1034,\n\tFN_SEL_SSI2_A = 1035,\n\tFN_SEL_SSI2_B = 1036,\n\tFN_SEL_SSI1_A = 1037,\n\tFN_SEL_SSI1_B = 1038,\n\tFN_SEL_VI1_A = 1039,\n\tFN_SEL_VI1_B = 1040,\n\tFN_SEL_VI0_A = 1041,\n\tFN_SEL_VI0_B = 1042,\n\tFN_SEL_VI0_C = 1043,\n\tFN_SEL_VI0_D = 1044,\n\tFN_SEL_SD2_A = 1045,\n\tFN_SEL_SD2_B = 1046,\n\tFN_SEL_SD1_A = 1047,\n\tFN_SEL_SD1_B = 1048,\n\tFN_SEL_IRQ3_A = 1049,\n\tFN_SEL_IRQ3_B = 1050,\n\tFN_SEL_IRQ2_A = 1051,\n\tFN_SEL_IRQ2_B = 1052,\n\tFN_SEL_IRQ2_C = 1053,\n\tFN_SEL_IRQ1_A = 1054,\n\tFN_SEL_IRQ1_B = 1055,\n\tFN_SEL_DREQ2_A = 1056,\n\tFN_SEL_DREQ2_B = 1057,\n\tFN_SEL_DREQ1_A = 1058,\n\tFN_SEL_DREQ1_B = 1059,\n\tFN_SEL_DREQ0_A = 1060,\n\tFN_SEL_DREQ0_B = 1061,\n\tFN_SEL_WAIT2_A = 1062,\n\tFN_SEL_WAIT2_B = 1063,\n\tFN_SEL_WAIT1_A = 1064,\n\tFN_SEL_WAIT1_B = 1065,\n\tFN_SEL_CAN1_A = 1066,\n\tFN_SEL_CAN1_B = 1067,\n\tFN_SEL_CAN0_A = 1068,\n\tFN_SEL_CAN0_B = 1069,\n\tFN_SEL_CANCLK_A = 1070,\n\tFN_SEL_CANCLK_B = 1071,\n\tFN_SEL_CANCLK_C = 1072,\n\tFN_SEL_CANCLK_D = 1073,\n\tFN_SEL_HSCIF1_A = 1074,\n\tFN_SEL_HSCIF1_B = 1075,\n\tFN_SEL_HSCIF0_A = 1076,\n\tFN_SEL_HSCIF0_B = 1077,\n\tFN_SEL_REMOCON_A = 1078,\n\tFN_SEL_REMOCON_B = 1079,\n\tFN_SEL_REMOCON_C = 1080,\n\tFN_SEL_FM_A = 1081,\n\tFN_SEL_FM_B = 1082,\n\tFN_SEL_FM_C = 1083,\n\tFN_SEL_FM_D = 1084,\n\tFN_SEL_GPS_A = 1085,\n\tFN_SEL_GPS_B = 1086,\n\tFN_SEL_GPS_C = 1087,\n\tFN_SEL_TSIF0_A = 1088,\n\tFN_SEL_TSIF0_B = 1089,\n\tFN_SEL_HSPI2_A = 1090,\n\tFN_SEL_HSPI2_B = 1091,\n\tFN_SEL_HSPI1_A = 1092,\n\tFN_SEL_HSPI1_B = 1093,\n\tFN_SEL_HSPI0_A = 1094,\n\tFN_SEL_HSPI0_B = 1095,\n\tFN_SEL_I2C3_A = 1096,\n\tFN_SEL_I2C3_B = 1097,\n\tFN_SEL_I2C3_C = 1098,\n\tFN_SEL_I2C2_A = 1099,\n\tFN_SEL_I2C2_B = 1100,\n\tFN_SEL_I2C2_C = 1101,\n\tFN_SEL_I2C1_A = 1102,\n\tFN_SEL_I2C1_B = 1103,\n\tPINMUX_FUNCTION_END___8 = 1104,\n\tPINMUX_MARK_BEGIN___8 = 1105,\n\tPENC0_MARK = 1106,\n\tPENC1_MARK = 1107,\n\tA1_MARK___6 = 1108,\n\tA2_MARK___6 = 1109,\n\tA3_MARK___6 = 1110,\n\tWE0_MARK = 1111,\n\tAUDIO_CLKA_MARK___4 = 1112,\n\tAUDIO_CLKB_MARK___4 = 1113,\n\tSSI_SCK34_MARK___5 = 1114,\n\tAVS1_MARK___2 = 1115,\n\tAVS2_MARK___2 = 1116,\n\tVI0_R0_C_MARK = 1117,\n\tVI0_R1_C_MARK = 1118,\n\tVI0_R2_C_MARK = 1119,\n\tVI0_R4_C_MARK = 1120,\n\tVI0_R5_C_MARK = 1121,\n\tVI0_R0_D_MARK = 1122,\n\tVI0_R1_D_MARK = 1123,\n\tVI0_R2_D_MARK = 1124,\n\tVI0_R3_D_MARK = 1125,\n\tVI0_R4_D_MARK = 1126,\n\tVI0_R5_D_MARK = 1127,\n\tPRESETOUT_MARK = 1128,\n\tPWM1_MARK___4 = 1129,\n\tAUDATA0_MARK___2 = 1130,\n\tARM_TRACEDATA_0_MARK___2 = 1131,\n\tGPSCLK_C_MARK = 1132,\n\tUSB_OVC0_MARK___2 = 1133,\n\tTX2_E_MARK___3 = 1134,\n\tSDA2_B_MARK___3 = 1135,\n\tAUDATA1_MARK___2 = 1136,\n\tARM_TRACEDATA_1_MARK___2 = 1137,\n\tGPSIN_C_MARK = 1138,\n\tUSB_OVC1_MARK___2 = 1139,\n\tRX2_E_MARK___3 = 1140,\n\tSCL2_B_MARK___3 = 1141,\n\tSD1_DAT2_A_MARK = 1142,\n\tMMC_D2_MARK___3 = 1143,\n\tBS_MARK___4 = 1144,\n\tATADIR0_A_MARK = 1145,\n\tSDSELF_A_MARK = 1146,\n\tPWM4_B_MARK___4 = 1147,\n\tSD1_DAT3_A_MARK = 1148,\n\tMMC_D3_MARK___3 = 1149,\n\tA0_MARK___8 = 1150,\n\tATAG0_A_MARK = 1151,\n\tREMOCON_B_MARK___4 = 1152,\n\tA4_MARK___5 = 1153,\n\tA5_MARK___5 = 1154,\n\tA6_MARK___6 = 1155,\n\tA7_MARK___6 = 1156,\n\tA8_MARK___6 = 1157,\n\tA9_MARK___6 = 1158,\n\tA10_MARK___6 = 1159,\n\tA11_MARK___6 = 1160,\n\tA12_MARK___6 = 1161,\n\tA13_MARK___6 = 1162,\n\tA14_MARK___6 = 1163,\n\tA15_MARK___6 = 1164,\n\tA16_MARK___6 = 1165,\n\tA17_MARK___7 = 1166,\n\tA18_MARK___7 = 1167,\n\tA19_MARK___7 = 1168,\n\tA20_MARK___7 = 1169,\n\tHSPI_CS1_B_MARK___2 = 1170,\n\tA21_MARK___7 = 1171,\n\tHSPI_CLK1_B_MARK___2 = 1172,\n\tA22_MARK___7 = 1173,\n\tHRTS0_B_MARK___2 = 1174,\n\tRX2_B_MARK___4 = 1175,\n\tDREQ2_A_MARK = 1176,\n\tA23_MARK___7 = 1177,\n\tHTX0_B_MARK___4 = 1178,\n\tTX2_B_MARK___4 = 1179,\n\tDACK2_A_MARK = 1180,\n\tTS_SDEN0_A_MARK = 1181,\n\tSD1_CD_A_MARK = 1182,\n\tMMC_D6_MARK___3 = 1183,\n\tA24_MARK___7 = 1184,\n\tDREQ1_A_MARK = 1185,\n\tHRX0_B_MARK___4 = 1186,\n\tTS_SPSYNC0_A_MARK = 1187,\n\tSD1_WP_A_MARK = 1188,\n\tMMC_D7_MARK___3 = 1189,\n\tA25_MARK___7 = 1190,\n\tDACK1_A_MARK = 1191,\n\tHCTS0_B_MARK___2 = 1192,\n\tRX3_C_MARK___3 = 1193,\n\tTS_SDAT0_A_MARK = 1194,\n\tCLKOUT_MARK___3 = 1195,\n\tHSPI_TX1_B_MARK___2 = 1196,\n\tPWM0_B_MARK___5 = 1197,\n\tCS0_MARK___3 = 1198,\n\tHSPI_RX1_B_MARK___2 = 1199,\n\tSSI_SCK1_B_MARK___4 = 1200,\n\tATAG0_B_MARK = 1201,\n\tCS1_A26_MARK___2 = 1202,\n\tSDA2_A_MARK___2 = 1203,\n\tSCK2_B_MARK___2 = 1204,\n\tMMC_D5_MARK___3 = 1205,\n\tATADIR0_B_MARK = 1206,\n\tRD_WR_MARK___2 = 1207,\n\tWE1_MARK___2 = 1208,\n\tATAWR0_B_MARK = 1209,\n\tSSI_WS1_B_MARK___4 = 1210,\n\tEX_CS0_MARK___2 = 1211,\n\tSCL2_A_MARK___2 = 1212,\n\tTX3_C_MARK___3 = 1213,\n\tTS_SCK0_A_MARK = 1214,\n\tEX_CS1_MARK___2 = 1215,\n\tMMC_D4_MARK___3 = 1216,\n\tSD1_CLK_A_MARK = 1217,\n\tMMC_CLK_MARK___3 = 1218,\n\tATACS00_MARK___2 = 1219,\n\tEX_CS2_MARK___2 = 1220,\n\tSD1_CMD_A_MARK = 1221,\n\tMMC_CMD_MARK___3 = 1222,\n\tATACS10_MARK___2 = 1223,\n\tEX_CS3_MARK___2 = 1224,\n\tSD1_DAT0_A_MARK = 1225,\n\tMMC_D0_MARK___3 = 1226,\n\tATARD0_MARK___2 = 1227,\n\tEX_CS4_MARK___2 = 1228,\n\tEX_WAIT1_A_MARK = 1229,\n\tSD1_DAT1_A_MARK = 1230,\n\tMMC_D1_MARK___3 = 1231,\n\tATAWR0_A_MARK = 1232,\n\tEX_CS5_MARK___2 = 1233,\n\tEX_WAIT2_A_MARK = 1234,\n\tDREQ0_A_MARK = 1235,\n\tRX3_A_MARK___2 = 1236,\n\tDACK0_MARK___7 = 1237,\n\tTX3_A_MARK___2 = 1238,\n\tDRACK0_MARK___5 = 1239,\n\tEX_WAIT0_MARK___4 = 1240,\n\tPWM0_C_MARK___3 = 1241,\n\tD0_MARK___5 = 1242,\n\tD1_MARK___5 = 1243,\n\tD2_MARK___5 = 1244,\n\tD3_MARK___5 = 1245,\n\tD4_MARK___5 = 1246,\n\tD5_MARK___5 = 1247,\n\tD6_MARK___5 = 1248,\n\tD7_MARK___5 = 1249,\n\tD8_MARK___5 = 1250,\n\tD9_MARK___5 = 1251,\n\tD10_MARK___5 = 1252,\n\tD11_MARK___5 = 1253,\n\tRD_WR_B_MARK = 1254,\n\tIRQ0_MARK___6 = 1255,\n\tMLB_CLK_MARK___4 = 1256,\n\tIRQ1_A_MARK = 1257,\n\tMLB_SIG_MARK___4 = 1258,\n\tRX5_B_MARK___4 = 1259,\n\tSDA3_A_MARK___2 = 1260,\n\tIRQ2_A_MARK = 1261,\n\tMLB_DAT_MARK___4 = 1262,\n\tTX5_B_MARK___4 = 1263,\n\tSCL3_A_MARK___2 = 1264,\n\tIRQ3_A_MARK = 1265,\n\tSDSELF_B_MARK___2 = 1266,\n\tSD1_CMD_B_MARK = 1267,\n\tSCIF_CLK_MARK___4 = 1268,\n\tAUDIO_CLKOUT_B_MARK___4 = 1269,\n\tCAN_CLK_B_MARK___5 = 1270,\n\tSDA3_B_MARK___3 = 1271,\n\tSD1_CLK_B_MARK = 1272,\n\tHTX0_A_MARK___2 = 1273,\n\tTX0_A_MARK___2 = 1274,\n\tSD1_DAT0_B_MARK = 1275,\n\tHRX0_A_MARK___2 = 1276,\n\tRX0_A_MARK___2 = 1277,\n\tSD1_DAT1_B_MARK = 1278,\n\tHSCK0_MARK___4 = 1279,\n\tSCK0_MARK___2 = 1280,\n\tSCL3_B_MARK___3 = 1281,\n\tSD1_DAT2_B_MARK = 1282,\n\tHCTS0_A_MARK = 1283,\n\tCTS0_MARK___2 = 1284,\n\tSD1_DAT3_B_MARK = 1285,\n\tHRTS0_A_MARK = 1286,\n\tRTS0_MARK = 1287,\n\tSSI_SCK4_MARK___4 = 1288,\n\tDU0_DR0_MARK___5 = 1289,\n\tLCDOUT0_MARK___4 = 1290,\n\tAUDATA2_MARK___2 = 1291,\n\tARM_TRACEDATA_2_MARK___2 = 1292,\n\tSDA3_C_MARK___2 = 1293,\n\tADICHS1_MARK___4 = 1294,\n\tTS_SDEN0_B_MARK___2 = 1295,\n\tSSI_WS4_MARK___4 = 1296,\n\tDU0_DR1_MARK___4 = 1297,\n\tLCDOUT1_MARK___4 = 1298,\n\tAUDATA3_MARK___2 = 1299,\n\tARM_TRACEDATA_3_MARK___2 = 1300,\n\tSCL3_C_MARK___2 = 1301,\n\tADICHS2_MARK___4 = 1302,\n\tTS_SPSYNC0_B_MARK___2 = 1303,\n\tDU0_DR2_MARK___5 = 1304,\n\tLCDOUT2_MARK___4 = 1305,\n\tDU0_DR3_MARK___5 = 1306,\n\tLCDOUT3_MARK___4 = 1307,\n\tDU0_DR4_MARK___5 = 1308,\n\tLCDOUT4_MARK___4 = 1309,\n\tDU0_DR5_MARK___5 = 1310,\n\tLCDOUT5_MARK___4 = 1311,\n\tDU0_DR6_MARK___5 = 1312,\n\tLCDOUT6_MARK___4 = 1313,\n\tDU0_DR7_MARK___5 = 1314,\n\tLCDOUT7_MARK___4 = 1315,\n\tDU0_DG0_MARK___5 = 1316,\n\tLCDOUT8_MARK___4 = 1317,\n\tAUDATA4_MARK___2 = 1318,\n\tARM_TRACEDATA_4_MARK___2 = 1319,\n\tTX1_D_MARK___3 = 1320,\n\tCAN0_TX_A_MARK___2 = 1321,\n\tADICHS0_MARK___4 = 1322,\n\tDU0_DG1_MARK___5 = 1323,\n\tLCDOUT9_MARK___4 = 1324,\n\tAUDATA5_MARK___2 = 1325,\n\tARM_TRACEDATA_5_MARK___2 = 1326,\n\tRX1_D_MARK___3 = 1327,\n\tCAN0_RX_A_MARK___2 = 1328,\n\tADIDATA_MARK___4 = 1329,\n\tDU0_DG2_MARK___5 = 1330,\n\tLCDOUT10_MARK___4 = 1331,\n\tDU0_DG3_MARK___5 = 1332,\n\tLCDOUT11_MARK___4 = 1333,\n\tDU0_DG4_MARK___5 = 1334,\n\tLCDOUT12_MARK___4 = 1335,\n\tRX0_B_MARK___4 = 1336,\n\tDU0_DG5_MARK___5 = 1337,\n\tLCDOUT13_MARK___4 = 1338,\n\tTX0_B_MARK___4 = 1339,\n\tDU0_DG6_MARK___5 = 1340,\n\tLCDOUT14_MARK___4 = 1341,\n\tRX4_A_MARK___2 = 1342,\n\tDU0_DG7_MARK___5 = 1343,\n\tLCDOUT15_MARK___4 = 1344,\n\tTX4_A_MARK___2 = 1345,\n\tSSI_SCK2_B_MARK___3 = 1346,\n\tVI0_R0_B_MARK = 1347,\n\tDU0_DB0_MARK___5 = 1348,\n\tLCDOUT16_MARK___4 = 1349,\n\tAUDATA6_MARK___2 = 1350,\n\tARM_TRACEDATA_6_MARK___2 = 1351,\n\tGPSCLK_A_MARK = 1352,\n\tPWM0_A_MARK___2 = 1353,\n\tADICLK_MARK___4 = 1354,\n\tTS_SDAT0_B_MARK = 1355,\n\tAUDIO_CLKC_MARK___4 = 1356,\n\tVI0_R1_B_MARK = 1357,\n\tDU0_DB1_MARK___5 = 1358,\n\tLCDOUT17_MARK___4 = 1359,\n\tAUDATA7_MARK___2 = 1360,\n\tARM_TRACEDATA_7_MARK___2 = 1361,\n\tGPSIN_A_MARK = 1362,\n\tADICS_SAMP_MARK___4 = 1363,\n\tTS_SCK0_B_MARK___2 = 1364,\n\tVI0_R2_B_MARK = 1365,\n\tDU0_DB2_MARK___5 = 1366,\n\tLCDOUT18_MARK___4 = 1367,\n\tVI0_R3_B_MARK = 1368,\n\tDU0_DB3_MARK___5 = 1369,\n\tLCDOUT19_MARK___4 = 1370,\n\tVI0_R4_B_MARK = 1371,\n\tDU0_DB4_MARK___5 = 1372,\n\tLCDOUT20_MARK___4 = 1373,\n\tVI0_R5_B_MARK = 1374,\n\tDU0_DB5_MARK___5 = 1375,\n\tLCDOUT21_MARK___4 = 1376,\n\tVI1_DATA10_B_MARK = 1377,\n\tDU0_DB6_MARK___5 = 1378,\n\tLCDOUT22_MARK___4 = 1379,\n\tVI1_DATA11_B_MARK = 1380,\n\tDU0_DB7_MARK___5 = 1381,\n\tLCDOUT23_MARK___4 = 1382,\n\tDU0_DOTCLKIN_MARK___6 = 1383,\n\tQSTVA_QVS_MARK___4 = 1384,\n\tDU0_DOTCLKO_UT0_MARK = 1385,\n\tQCLK_MARK___4 = 1386,\n\tDU0_DOTCLKO_UT1_MARK = 1387,\n\tQSTVB_QVE_MARK___4 = 1388,\n\tAUDIO_CLKOUT_A_MARK___2 = 1389,\n\tREMOCON_C_MARK = 1390,\n\tSSI_WS2_B_MARK___3 = 1391,\n\tDU0_EXHSYNC_DU0_HSYNC_MARK___4 = 1392,\n\tQSTH_QHS_MARK___4 = 1393,\n\tDU0_EXVSYNC_DU0_VSYNC_MARK___4 = 1394,\n\tQSTB_QHE_MARK___4 = 1395,\n\tDU0_EXODDF_DU0_ODDF_DISP_CDE_MARK___4 = 1396,\n\tQCPV_QDE_MARK___4 = 1397,\n\tFMCLK_D_MARK___3 = 1398,\n\tSSI_SCK1_A_MARK___2 = 1399,\n\tDU0_DISP_MARK___4 = 1400,\n\tQPOLA_MARK___4 = 1401,\n\tAUDCK_MARK___2 = 1402,\n\tARM_TRACECLK_MARK = 1403,\n\tBPFCLK_D_MARK___3 = 1404,\n\tSSI_WS1_A_MARK___2 = 1405,\n\tDU0_CDE_MARK___5 = 1406,\n\tQPOLB_MARK___4 = 1407,\n\tAUDSYNC_MARK___2 = 1408,\n\tARM_TRACECTL_MARK = 1409,\n\tFMIN_D_MARK___3 = 1410,\n\tSD1_CD_B_MARK = 1411,\n\tSSI_SCK78_MARK___4 = 1412,\n\tHSPI_RX0_B_MARK = 1413,\n\tTX1_B_MARK___4 = 1414,\n\tSD1_WP_B_MARK = 1415,\n\tSSI_WS78_MARK___4 = 1416,\n\tHSPI_CLK0_B_MARK = 1417,\n\tRX1_B_MARK___4 = 1418,\n\tCAN_CLK_D_MARK___4 = 1419,\n\tSSI_SDATA8_MARK___4 = 1420,\n\tSSI_SCK2_A_MARK___2 = 1421,\n\tHSPI_CS0_B_MARK = 1422,\n\tTX2_A_MARK___2 = 1423,\n\tCAN0_TX_B_MARK___5 = 1424,\n\tSSI_SDATA7_MARK___4 = 1425,\n\tHSPI_TX0_B_MARK = 1426,\n\tRX2_A_MARK___2 = 1427,\n\tCAN0_RX_B_MARK___5 = 1428,\n\tSSI_SCK6_MARK___4 = 1429,\n\tHSPI_RX2_A_MARK = 1430,\n\tFMCLK_B_MARK___3 = 1431,\n\tCAN1_TX_B_MARK___4 = 1432,\n\tSSI_WS6_MARK___4 = 1433,\n\tHSPI_CLK2_A_MARK = 1434,\n\tBPFCLK_B_MARK___3 = 1435,\n\tCAN1_RX_B_MARK___4 = 1436,\n\tSSI_SDATA6_MARK___4 = 1437,\n\tHSPI_TX2_A_MARK = 1438,\n\tFMIN_B_MARK___3 = 1439,\n\tSSI_SCK5_MARK___4 = 1440,\n\tRX4_C_MARK___4 = 1441,\n\tSSI_WS5_MARK___4 = 1442,\n\tTX4_C_MARK___4 = 1443,\n\tSSI_SDATA5_MARK___4 = 1444,\n\tRX0_D_MARK___4 = 1445,\n\tSSI_WS34_MARK___5 = 1446,\n\tARM_TRACEDATA_8_MARK___2 = 1447,\n\tSSI_SDATA4_MARK___4 = 1448,\n\tSSI_WS2_A_MARK___2 = 1449,\n\tARM_TRACEDATA_9_MARK___2 = 1450,\n\tSSI_SDATA3_MARK___5 = 1451,\n\tARM_TRACEDATA_10_MARK___2 = 1452,\n\tSSI_SCK012_MARK = 1453,\n\tARM_TRACEDATA_11_MARK___2 = 1454,\n\tTX0_D_MARK___4 = 1455,\n\tSSI_WS012_MARK = 1456,\n\tARM_TRACEDATA_12_MARK___2 = 1457,\n\tSSI_SDATA2_MARK___4 = 1458,\n\tHSPI_CS2_A_MARK = 1459,\n\tARM_TRACEDATA_13_MARK___2 = 1460,\n\tSDA1_A_MARK___2 = 1461,\n\tSSI_SDATA1_MARK___4 = 1462,\n\tARM_TRACEDATA_14_MARK___2 = 1463,\n\tSCL1_A_MARK___2 = 1464,\n\tSCK2_A_MARK = 1465,\n\tSSI_SDATA0_MARK___4 = 1466,\n\tARM_TRACEDATA_15_MARK___2 = 1467,\n\tSD0_CLK_MARK___5 = 1468,\n\tSUB_TDO_MARK___2 = 1469,\n\tSD0_CMD_MARK___5 = 1470,\n\tSUB_TRST_MARK___2 = 1471,\n\tSD0_DAT0_MARK___3 = 1472,\n\tSUB_TMS_MARK___2 = 1473,\n\tSD0_DAT1_MARK___3 = 1474,\n\tSUB_TCK_MARK___2 = 1475,\n\tSD0_DAT2_MARK___3 = 1476,\n\tSUB_TDI_MARK___2 = 1477,\n\tSD0_DAT3_MARK___3 = 1478,\n\tIRQ1_B_MARK___2 = 1479,\n\tSD0_CD_MARK___5 = 1480,\n\tTX5_A_MARK___2 = 1481,\n\tSD0_WP_MARK___5 = 1482,\n\tRX5_A_MARK___2 = 1483,\n\tVI1_CLKENB_MARK___5 = 1484,\n\tHSPI_CLK0_A_MARK = 1485,\n\tHTX1_A_MARK___2 = 1486,\n\tRTS1_C_MARK = 1487,\n\tVI1_FIELD_MARK___5 = 1488,\n\tHSPI_CS0_A_MARK = 1489,\n\tHRX1_A_MARK___2 = 1490,\n\tSCK1_C_MARK___2 = 1491,\n\tVI1_HSYNC_MARK___2 = 1492,\n\tHSPI_RX0_A_MARK = 1493,\n\tHRTS1_A_MARK = 1494,\n\tFMCLK_A_MARK = 1495,\n\tRX1_C_MARK___4 = 1496,\n\tVI1_VSYNC_MARK___2 = 1497,\n\tHSPI_TX0_MARK___2 = 1498,\n\tHCTS1_A_MARK = 1499,\n\tBPFCLK_A_MARK = 1500,\n\tTX1_C_MARK___4 = 1501,\n\tTCLK0_MARK___2 = 1502,\n\tHSCK1_A_MARK = 1503,\n\tFMIN_A_MARK = 1504,\n\tIRQ2_C_MARK = 1505,\n\tCTS1_C_MARK___2 = 1506,\n\tSPEEDIN_MARK___4 = 1507,\n\tVI0_CLK_MARK___5 = 1508,\n\tCAN_CLK_A_MARK___2 = 1509,\n\tVI0_CLKENB_MARK___5 = 1510,\n\tSD2_DAT2_B_MARK___2 = 1511,\n\tVI1_DATA0_MARK___4 = 1512,\n\tDU1_DG6_MARK___5 = 1513,\n\tHSPI_RX1_A_MARK = 1514,\n\tRX4_B_MARK___4 = 1515,\n\tVI0_FIELD_MARK___5 = 1516,\n\tSD2_DAT3_B_MARK___2 = 1517,\n\tVI0_R3_C_MARK = 1518,\n\tVI1_DATA1_MARK___4 = 1519,\n\tDU1_DG7_MARK___5 = 1520,\n\tHSPI_CLK1_A_MARK = 1521,\n\tTX4_B_MARK___4 = 1522,\n\tVI0_HSYNC_MARK___2 = 1523,\n\tSD2_CD_B_MARK___2 = 1524,\n\tVI1_DATA2_MARK___4 = 1525,\n\tDU1_DR2_MARK___5 = 1526,\n\tHSPI_CS1_A_MARK = 1527,\n\tRX3_B_MARK___3 = 1528,\n\tVI0_VSYNC_MARK___2 = 1529,\n\tSD2_WP_B_MARK___2 = 1530,\n\tVI1_DATA3_MARK___4 = 1531,\n\tDU1_DR3_MARK___5 = 1532,\n\tHSPI_TX1_A_MARK = 1533,\n\tTX3_B_MARK___3 = 1534,\n\tVI0_DATA0_VI0_B0_MARK___5 = 1535,\n\tDU1_DG2_MARK___5 = 1536,\n\tIRQ2_B_MARK___2 = 1537,\n\tRX3_D_MARK___2 = 1538,\n\tVI0_DATA1_VI0_B1_MARK___5 = 1539,\n\tDU1_DG3_MARK___5 = 1540,\n\tIRQ3_B_MARK___2 = 1541,\n\tTX3_D_MARK___2 = 1542,\n\tVI0_DATA2_VI0_B2_MARK___5 = 1543,\n\tDU1_DG4_MARK___5 = 1544,\n\tRX0_C_MARK___4 = 1545,\n\tVI0_DATA3_VI0_B3_MARK___5 = 1546,\n\tDU1_DG5_MARK___5 = 1547,\n\tTX1_A_MARK___2 = 1548,\n\tTX0_C_MARK___4 = 1549,\n\tVI0_DATA4_VI0_B4_MARK___5 = 1550,\n\tDU1_DB2_MARK___5 = 1551,\n\tRX1_A_MARK___2 = 1552,\n\tVI0_DATA5_VI0_B5_MARK___5 = 1553,\n\tDU1_DB3_MARK___5 = 1554,\n\tSCK1_A_MARK = 1555,\n\tPWM4_MARK___4 = 1556,\n\tHSCK1_B_MARK___2 = 1557,\n\tVI0_DATA6_VI0_G0_MARK = 1558,\n\tDU1_DB4_MARK___5 = 1559,\n\tCTS1_A_MARK = 1560,\n\tPWM5_MARK___4 = 1561,\n\tVI0_DATA7_VI0_G1_MARK = 1562,\n\tDU1_DB5_MARK___5 = 1563,\n\tRTS1_A_MARK = 1564,\n\tVI0_G2_MARK___5 = 1565,\n\tSD2_CLK_B_MARK___2 = 1566,\n\tVI1_DATA4_MARK___4 = 1567,\n\tDU1_DR4_MARK___5 = 1568,\n\tHTX1_B_MARK___4 = 1569,\n\tVI0_G3_MARK___5 = 1570,\n\tSD2_CMD_B_MARK___2 = 1571,\n\tVI1_DATA5_MARK___4 = 1572,\n\tDU1_DR5_MARK___5 = 1573,\n\tHRX1_B_MARK___4 = 1574,\n\tVI0_G4_MARK___5 = 1575,\n\tSD2_DAT0_B_MARK___2 = 1576,\n\tVI1_DATA6_MARK___4 = 1577,\n\tDU1_DR6_MARK___5 = 1578,\n\tHRTS1_B_MARK___2 = 1579,\n\tVI0_G5_MARK___5 = 1580,\n\tSD2_DAT1_B_MARK___2 = 1581,\n\tVI1_DATA7_MARK___4 = 1582,\n\tDU1_DR7_MARK___5 = 1583,\n\tHCTS1_B_MARK___2 = 1584,\n\tVI0_R0_A_MARK = 1585,\n\tVI1_CLK_MARK___5 = 1586,\n\tETH_REF_CLK_MARK___2 = 1587,\n\tDU1_DOTCLKIN_MARK___5 = 1588,\n\tVI0_R1_A_MARK = 1589,\n\tVI1_DATA8_MARK___3 = 1590,\n\tDU1_DB6_MARK___5 = 1591,\n\tETH_TXD0_MARK___5 = 1592,\n\tPWM2_MARK___4 = 1593,\n\tTCLK1_MARK___4 = 1594,\n\tVI0_R2_A_MARK = 1595,\n\tVI1_DATA9_MARK___3 = 1596,\n\tDU1_DB7_MARK___5 = 1597,\n\tETH_TXD1_MARK___5 = 1598,\n\tPWM3_MARK___4 = 1599,\n\tVI0_R3_A_MARK = 1600,\n\tETH_CRS_DV_MARK___5 = 1601,\n\tIECLK_MARK___4 = 1602,\n\tSCK2_C_MARK___2 = 1603,\n\tVI0_R4_A_MARK = 1604,\n\tETH_TX_EN_MARK___5 = 1605,\n\tIETX_MARK___4 = 1606,\n\tTX2_C_MARK___4 = 1607,\n\tVI0_R5_A_MARK = 1608,\n\tETH_RX_ER_MARK___5 = 1609,\n\tFMCLK_C_MARK___3 = 1610,\n\tIERX_MARK___4 = 1611,\n\tRX2_C_MARK___4 = 1612,\n\tVI1_DATA10_A_MARK = 1613,\n\tDU1_DOTCLKOUT_MARK___2 = 1614,\n\tETH_RXD0_MARK___5 = 1615,\n\tBPFCLK_C_MARK___3 = 1616,\n\tTX2_D_MARK___2 = 1617,\n\tSDA2_C_MARK___3 = 1618,\n\tVI1_DATA11_A_MARK = 1619,\n\tDU1_EXHSYNC_DU1_HSYNC_MARK___5 = 1620,\n\tETH_RXD1_MARK___5 = 1621,\n\tFMIN_C_MARK___3 = 1622,\n\tRX2_D_MARK___2 = 1623,\n\tSCL2_C_MARK___3 = 1624,\n\tSD2_CLK_A_MARK = 1625,\n\tDU1_EXVSYNC_DU1_VSYNC_MARK___5 = 1626,\n\tATARD1_MARK___2 = 1627,\n\tETH_MDC_MARK___5 = 1628,\n\tSDA1_B_MARK___3 = 1629,\n\tSD2_CMD_A_MARK = 1630,\n\tDU1_EXODDF_DU1_ODDF_DISP_CDE_MARK___5 = 1631,\n\tATAWR1_MARK___2 = 1632,\n\tETH_MDIO_MARK___5 = 1633,\n\tSCL1_B_MARK___3 = 1634,\n\tSD2_DAT0_A_MARK = 1635,\n\tDU1_DISP_MARK___5 = 1636,\n\tATACS01_MARK___2 = 1637,\n\tDREQ1_B_MARK___2 = 1638,\n\tETH_LINK_MARK___5 = 1639,\n\tCAN1_RX_A_MARK___2 = 1640,\n\tSD2_DAT1_A_MARK = 1641,\n\tDU1_CDE_MARK___5 = 1642,\n\tATACS11_MARK___2 = 1643,\n\tDACK1_B_MARK___3 = 1644,\n\tETH_MAGIC_MARK___5 = 1645,\n\tCAN1_TX_A_MARK___2 = 1646,\n\tPWM6_MARK___4 = 1647,\n\tSD2_DAT2_A_MARK = 1648,\n\tVI1_DATA12_MARK = 1649,\n\tDREQ2_B_MARK___3 = 1650,\n\tATADIR1_MARK___2 = 1651,\n\tHSPI_CLK2_B_MARK___2 = 1652,\n\tGPSCLK_B_MARK = 1653,\n\tSD2_DAT3_A_MARK = 1654,\n\tVI1_DATA13_MARK = 1655,\n\tDACK2_B_MARK___3 = 1656,\n\tATAG1_MARK___2 = 1657,\n\tHSPI_CS2_B_MARK___2 = 1658,\n\tGPSIN_B_MARK = 1659,\n\tSD2_CD_A_MARK = 1660,\n\tVI1_DATA14_MARK = 1661,\n\tEX_WAIT1_B_MARK = 1662,\n\tDREQ0_B_MARK___2 = 1663,\n\tHSPI_RX2_B_MARK___2 = 1664,\n\tREMOCON_A_MARK___2 = 1665,\n\tSD2_WP_A_MARK = 1666,\n\tVI1_DATA15_MARK = 1667,\n\tEX_WAIT2_B_MARK = 1668,\n\tDACK0_B_MARK___2 = 1669,\n\tHSPI_TX2_B_MARK___2 = 1670,\n\tCAN_CLK_C_MARK___5 = 1671,\n\tPINMUX_MARK_END___8 = 1672,\n};\n\nenum {\n\tPINMUX_RESERVED___9 = 0,\n\tPINMUX_DATA_BEGIN___9 = 1,\n\tPORT0_DATA___4 = 2,\n\tPORT1_DATA___4 = 3,\n\tPORT2_DATA___4 = 4,\n\tPORT3_DATA___4 = 5,\n\tPORT4_DATA___4 = 6,\n\tPORT5_DATA___4 = 7,\n\tPORT6_DATA___4 = 8,\n\tPORT7_DATA___4 = 9,\n\tPORT8_DATA___4 = 10,\n\tPORT9_DATA___4 = 11,\n\tPORT10_DATA___4 = 12,\n\tPORT11_DATA___4 = 13,\n\tPORT12_DATA___4 = 14,\n\tPORT13_DATA___4 = 15,\n\tPORT14_DATA___4 = 16,\n\tPORT15_DATA___4 = 17,\n\tPORT16_DATA___4 = 18,\n\tPORT17_DATA___4 = 19,\n\tPORT18_DATA___4 = 20,\n\tPORT19_DATA___4 = 21,\n\tPORT20_DATA___4 = 22,\n\tPORT21_DATA___4 = 23,\n\tPORT22_DATA___4 = 24,\n\tPORT23_DATA___4 = 25,\n\tPORT24_DATA___4 = 26,\n\tPORT25_DATA___4 = 27,\n\tPORT26_DATA___4 = 28,\n\tPORT27_DATA___4 = 29,\n\tPORT28_DATA___4 = 30,\n\tPORT29_DATA___4 = 31,\n\tPORT30_DATA___4 = 32,\n\tPORT31_DATA___3 = 33,\n\tPORT32_DATA___4 = 34,\n\tPORT33_DATA___4 = 35,\n\tPORT34_DATA___4 = 36,\n\tPORT35_DATA___4 = 37,\n\tPORT36_DATA___4 = 38,\n\tPORT37_DATA___4 = 39,\n\tPORT38_DATA___4 = 40,\n\tPORT39_DATA___4 = 41,\n\tPORT40_DATA___4 = 42,\n\tPORT41_DATA___3 = 43,\n\tPORT42_DATA___3 = 44,\n\tPORT43_DATA___3 = 45,\n\tPORT44_DATA___3 = 46,\n\tPORT45_DATA___3 = 47,\n\tPORT46_DATA___3 = 48,\n\tPORT47_DATA___3 = 49,\n\tPORT48_DATA___3 = 50,\n\tPORT49_DATA___3 = 51,\n\tPORT50_DATA___3 = 52,\n\tPORT51_DATA___3 = 53,\n\tPORT52_DATA___3 = 54,\n\tPORT53_DATA___3 = 55,\n\tPORT54_DATA___3 = 56,\n\tPORT55_DATA___3 = 57,\n\tPORT56_DATA___3 = 58,\n\tPORT57_DATA___3 = 59,\n\tPORT58_DATA___3 = 60,\n\tPORT59_DATA___3 = 61,\n\tPORT60_DATA___3 = 62,\n\tPORT61_DATA___3 = 63,\n\tPORT62_DATA___3 = 64,\n\tPORT63_DATA___3 = 65,\n\tPORT64_DATA___4 = 66,\n\tPORT65_DATA___4 = 67,\n\tPORT66_DATA___4 = 68,\n\tPORT67_DATA___4 = 69,\n\tPORT68_DATA___4 = 70,\n\tPORT69_DATA___4 = 71,\n\tPORT70_DATA___4 = 72,\n\tPORT71_DATA___4 = 73,\n\tPORT72_DATA___4 = 74,\n\tPORT73_DATA___4 = 75,\n\tPORT74_DATA___4 = 76,\n\tPORT75_DATA___4 = 77,\n\tPORT76_DATA___4 = 78,\n\tPORT77_DATA___4 = 79,\n\tPORT78_DATA___4 = 80,\n\tPORT79_DATA___4 = 81,\n\tPORT80_DATA___4 = 82,\n\tPORT81_DATA___4 = 83,\n\tPORT82_DATA___4 = 84,\n\tPORT83_DATA___4 = 85,\n\tPORT84_DATA___4 = 86,\n\tPORT85_DATA___4 = 87,\n\tPORT86_DATA___3 = 88,\n\tPORT87_DATA___3 = 89,\n\tPORT88_DATA___3 = 90,\n\tPORT89_DATA___3 = 91,\n\tPORT90_DATA___3 = 92,\n\tPORT91_DATA___3 = 93,\n\tPORT92_DATA___3 = 94,\n\tPORT93_DATA___3 = 95,\n\tPORT94_DATA___3 = 96,\n\tPORT95_DATA___3 = 97,\n\tPORT96_DATA___4 = 98,\n\tPORT97_DATA___4 = 99,\n\tPORT98_DATA___4 = 100,\n\tPORT99_DATA___4 = 101,\n\tPORT100_DATA___4 = 102,\n\tPORT101_DATA___4 = 103,\n\tPORT102_DATA___4 = 104,\n\tPORT103_DATA___4 = 105,\n\tPORT104_DATA___4 = 106,\n\tPORT105_DATA___4 = 107,\n\tPORT106_DATA___4 = 108,\n\tPORT107_DATA___4 = 109,\n\tPORT108_DATA___4 = 110,\n\tPORT109_DATA___4 = 111,\n\tPORT110_DATA___4 = 112,\n\tPORT111_DATA___4 = 113,\n\tPORT112_DATA___4 = 114,\n\tPORT113_DATA___4 = 115,\n\tPORT114_DATA___4 = 116,\n\tPORT115_DATA___4 = 117,\n\tPORT116_DATA___4 = 118,\n\tPORT117_DATA___4 = 119,\n\tPORT118_DATA___4 = 120,\n\tPORT119_DATA___3 = 121,\n\tPORT120_DATA___3 = 122,\n\tPORT121_DATA___3 = 123,\n\tPORT122_DATA___3 = 124,\n\tPORT123_DATA___3 = 125,\n\tPORT124_DATA___3 = 126,\n\tPORT125_DATA___3 = 127,\n\tPORT126_DATA___3 = 128,\n\tPORT127_DATA___2 = 129,\n\tPORT128_DATA___4 = 130,\n\tPORT129_DATA___4 = 131,\n\tPORT130_DATA___4 = 132,\n\tPORT131_DATA___4 = 133,\n\tPORT132_DATA___4 = 134,\n\tPORT133_DATA___4 = 135,\n\tPORT134_DATA___4 = 136,\n\tPORT135_DATA___3 = 137,\n\tPORT136_DATA___3 = 138,\n\tPORT137_DATA___3 = 139,\n\tPORT138_DATA___3 = 140,\n\tPORT139_DATA___3 = 141,\n\tPORT140_DATA___3 = 142,\n\tPORT141_DATA___3 = 143,\n\tPORT142_DATA___3 = 144,\n\tPORT143_DATA___3 = 145,\n\tPORT144_DATA___3 = 146,\n\tPORT145_DATA___3 = 147,\n\tPORT146_DATA___3 = 148,\n\tPORT147_DATA___3 = 149,\n\tPORT148_DATA___3 = 150,\n\tPORT149_DATA___3 = 151,\n\tPORT150_DATA___3 = 152,\n\tPORT151_DATA___3 = 153,\n\tPORT152_DATA___3 = 154,\n\tPORT153_DATA___3 = 155,\n\tPORT154_DATA___3 = 156,\n\tPORT155_DATA___3 = 157,\n\tPORT156_DATA___3 = 158,\n\tPORT157_DATA___3 = 159,\n\tPORT158_DATA___3 = 160,\n\tPINMUX_DATA_END___9 = 161,\n\tPINMUX_FUNCTION_BEGIN___9 = 162,\n\tPORT0_FN = 163,\n\tPORT1_FN = 164,\n\tPORT2_FN = 165,\n\tPORT3_FN = 166,\n\tPORT4_FN = 167,\n\tPORT5_FN = 168,\n\tPORT6_FN = 169,\n\tPORT7_FN = 170,\n\tPORT8_FN = 171,\n\tPORT9_FN = 172,\n\tPORT10_FN = 173,\n\tPORT11_FN = 174,\n\tPORT12_FN = 175,\n\tPORT13_FN = 176,\n\tPORT14_FN = 177,\n\tPORT15_FN = 178,\n\tPORT16_FN = 179,\n\tPORT17_FN = 180,\n\tPORT18_FN = 181,\n\tPORT19_FN = 182,\n\tPORT20_FN = 183,\n\tPORT21_FN = 184,\n\tPORT22_FN = 185,\n\tPORT23_FN = 186,\n\tPORT24_FN = 187,\n\tPORT25_FN = 188,\n\tPORT26_FN = 189,\n\tPORT27_FN = 190,\n\tPORT28_FN = 191,\n\tPORT29_FN = 192,\n\tPORT30_FN = 193,\n\tPORT31_FN = 194,\n\tPORT32_FN = 195,\n\tPORT33_FN = 196,\n\tPORT34_FN = 197,\n\tPORT35_FN = 198,\n\tPORT36_FN = 199,\n\tPORT37_FN = 200,\n\tPORT38_FN = 201,\n\tPORT39_FN = 202,\n\tPORT40_FN = 203,\n\tPORT41_FN = 204,\n\tPORT42_FN = 205,\n\tPORT43_FN = 206,\n\tPORT44_FN = 207,\n\tPORT45_FN = 208,\n\tPORT46_FN = 209,\n\tPORT47_FN = 210,\n\tPORT48_FN = 211,\n\tPORT49_FN = 212,\n\tPORT50_FN = 213,\n\tPORT51_FN = 214,\n\tPORT52_FN = 215,\n\tPORT53_FN = 216,\n\tPORT54_FN = 217,\n\tPORT55_FN = 218,\n\tPORT56_FN = 219,\n\tPORT57_FN = 220,\n\tPORT58_FN = 221,\n\tPORT59_FN = 222,\n\tPORT60_FN = 223,\n\tPORT61_FN = 224,\n\tPORT62_FN = 225,\n\tPORT63_FN = 226,\n\tPORT64_FN = 227,\n\tPORT65_FN = 228,\n\tPORT66_FN = 229,\n\tPORT67_FN = 230,\n\tPORT68_FN = 231,\n\tPORT69_FN = 232,\n\tPORT70_FN = 233,\n\tPORT71_FN = 234,\n\tPORT72_FN = 235,\n\tPORT73_FN = 236,\n\tPORT74_FN = 237,\n\tPORT75_FN = 238,\n\tPORT76_FN = 239,\n\tPORT77_FN = 240,\n\tPORT78_FN = 241,\n\tPORT79_FN = 242,\n\tPORT80_FN = 243,\n\tPORT81_FN = 244,\n\tPORT82_FN = 245,\n\tPORT83_FN = 246,\n\tPORT84_FN = 247,\n\tPORT85_FN = 248,\n\tPORT86_FN = 249,\n\tPORT87_FN = 250,\n\tPORT88_FN = 251,\n\tPORT89_FN = 252,\n\tPORT90_FN = 253,\n\tPORT91_FN = 254,\n\tPORT92_FN = 255,\n\tPORT93_FN = 256,\n\tPORT94_FN = 257,\n\tPORT95_FN = 258,\n\tPORT96_FN = 259,\n\tPORT97_FN = 260,\n\tPORT98_FN = 261,\n\tPORT99_FN = 262,\n\tPORT100_FN = 263,\n\tPORT101_FN = 264,\n\tPORT102_FN = 265,\n\tPORT103_FN = 266,\n\tPORT104_FN = 267,\n\tPORT105_FN = 268,\n\tPORT106_FN = 269,\n\tPORT107_FN = 270,\n\tPORT108_FN = 271,\n\tPORT109_FN = 272,\n\tPORT110_FN = 273,\n\tPORT111_FN = 274,\n\tPORT112_FN = 275,\n\tPORT113_FN = 276,\n\tPORT114_FN = 277,\n\tPORT115_FN = 278,\n\tPORT116_FN = 279,\n\tPORT117_FN = 280,\n\tPORT118_FN = 281,\n\tPORT119_FN = 282,\n\tPORT120_FN = 283,\n\tPORT121_FN = 284,\n\tPORT122_FN = 285,\n\tPORT123_FN = 286,\n\tPORT124_FN = 287,\n\tPORT125_FN = 288,\n\tPORT126_FN = 289,\n\tPORT127_FN = 290,\n\tPORT128_FN = 291,\n\tPORT129_FN = 292,\n\tPORT130_FN = 293,\n\tPORT131_FN = 294,\n\tPORT132_FN = 295,\n\tPORT133_FN = 296,\n\tPORT134_FN = 297,\n\tPORT135_FN = 298,\n\tPORT136_FN = 299,\n\tPORT137_FN = 300,\n\tPORT138_FN = 301,\n\tPORT139_FN = 302,\n\tPORT140_FN = 303,\n\tPORT141_FN = 304,\n\tPORT142_FN = 305,\n\tPORT143_FN = 306,\n\tPORT144_FN = 307,\n\tPORT145_FN = 308,\n\tPORT146_FN = 309,\n\tPORT147_FN = 310,\n\tPORT148_FN = 311,\n\tPORT149_FN = 312,\n\tPORT150_FN = 313,\n\tPORT151_FN = 314,\n\tPORT152_FN = 315,\n\tPORT153_FN = 316,\n\tPORT154_FN = 317,\n\tPORT155_FN = 318,\n\tPORT156_FN = 319,\n\tPORT157_FN = 320,\n\tPORT158_FN = 321,\n\tFN_LCD3_1_0_PORT18 = 322,\n\tFN_LCD3_1_0_PORT20 = 323,\n\tFN_LCD3_1_0_PORT21 = 324,\n\tFN_LCD3_1_0_PORT22 = 325,\n\tFN_LCD3_1_0_PORT23 = 326,\n\tFN_JT_SEL = 327,\n\tFN_ERR_RST_REQB = 328,\n\tFN_REF_CLKO = 329,\n\tFN_EXT_CLKI = 330,\n\tFN_LCD3_PXCLKB = 331,\n\tFN_LCD3_9_8_PORT38 = 332,\n\tFN_LCD3_9_8_PORT39 = 333,\n\tFN_LCD3_11_10_PORT40 = 334,\n\tFN_LCD3_11_10_PORT41 = 335,\n\tFN_LCD3_11_10_PORT42 = 336,\n\tFN_LCD3_11_10_PORT43 = 337,\n\tFN_IIC_1_0_PORT46 = 338,\n\tFN_IIC_1_0_PORT47 = 339,\n\tFN_LCD3_R0 = 340,\n\tFN_LCD3_R1 = 341,\n\tFN_LCD3_R2 = 342,\n\tFN_LCD3_R3 = 343,\n\tFN_LCD3_R4 = 344,\n\tFN_LCD3_R5 = 345,\n\tFN_IIC0_SCL___3 = 346,\n\tFN_IIC0_SDA___3 = 347,\n\tFN_SD_CKI = 348,\n\tFN_SDI0_CKO = 349,\n\tFN_SDI0_CKI = 350,\n\tFN_SDI0_CMD = 351,\n\tFN_SDI0_DATA0 = 352,\n\tFN_SDI0_DATA1 = 353,\n\tFN_SDI0_DATA2 = 354,\n\tFN_SDI0_DATA3 = 355,\n\tFN_SDI0_DATA4 = 356,\n\tFN_SDI0_DATA5 = 357,\n\tFN_SDI0_DATA6 = 358,\n\tFN_SDI0_DATA7 = 359,\n\tFN_SDI1_CKO = 360,\n\tFN_SDI1_CKI = 361,\n\tFN_SDI1_CMD = 362,\n\tFN_AB_1_0_PORT71 = 363,\n\tFN_AB_1_0_PORT72 = 364,\n\tFN_AB_1_0_PORT73 = 365,\n\tFN_AB_1_0_PORT74 = 366,\n\tFN_AB_1_0_PORT75 = 367,\n\tFN_AB_1_0_PORT76 = 368,\n\tFN_AB_1_0_PORT77 = 369,\n\tFN_AB_1_0_PORT78 = 370,\n\tFN_AB_1_0_PORT79 = 371,\n\tFN_AB_1_0_PORT80 = 372,\n\tFN_AB_1_0_PORT81 = 373,\n\tFN_AB_1_0_PORT82 = 374,\n\tFN_AB_1_0_PORT83 = 375,\n\tFN_AB_1_0_PORT84 = 376,\n\tFN_AB_3_2_PORT85 = 377,\n\tFN_AB_3_2_PORT86 = 378,\n\tFN_AB_3_2_PORT87 = 379,\n\tFN_AB_3_2_PORT88 = 380,\n\tFN_AB_5_4_PORT89 = 381,\n\tFN_AB_5_4_PORT90 = 382,\n\tFN_AB_7_6_PORT91 = 383,\n\tFN_AB_7_6_PORT92 = 384,\n\tFN_AB_1_0_PORT93 = 385,\n\tFN_AB_1_0_PORT94 = 386,\n\tFN_AB_1_0_PORT95 = 387,\n\tFN_SDI1_DATA0 = 388,\n\tFN_SDI1_DATA1 = 389,\n\tFN_SDI1_DATA2 = 390,\n\tFN_SDI1_DATA3 = 391,\n\tFN_AB_CLK = 392,\n\tFN_AB_CSB0 = 393,\n\tFN_AB_CSB1 = 394,\n\tFN_AB_13_12_PORT104 = 395,\n\tFN_AB_13_12_PORT103 = 396,\n\tFN_AB_11_10_PORT102 = 397,\n\tFN_AB_11_10_PORT101 = 398,\n\tFN_AB_11_10_PORT100 = 399,\n\tFN_AB_9_8_PORT99 = 400,\n\tFN_AB_9_8_PORT98 = 401,\n\tFN_AB_9_8_PORT97 = 402,\n\tFN_USI_1_0_PORT109 = 403,\n\tFN_USI_1_0_PORT110 = 404,\n\tFN_USI_1_0_PORT111 = 405,\n\tFN_USI_1_0_PORT112 = 406,\n\tFN_USI_3_2_PORT113 = 407,\n\tFN_USI_3_2_PORT114 = 408,\n\tFN_USI_5_4_PORT115 = 409,\n\tFN_USI_5_4_PORT116 = 410,\n\tFN_USI_5_4_PORT117 = 411,\n\tFN_USI_5_4_PORT118 = 412,\n\tFN_USI_7_6_PORT119 = 413,\n\tFN_USI_9_8_PORT120 = 414,\n\tFN_USI_9_8_PORT121 = 415,\n\tFN_AB_A20 = 416,\n\tFN_USI0_CS1 = 417,\n\tFN_USI0_CS2 = 418,\n\tFN_USI1_DI = 419,\n\tFN_USI1_DO = 420,\n\tFN_NTSC_CLK = 421,\n\tFN_NTSC_DATA0 = 422,\n\tFN_NTSC_DATA1 = 423,\n\tFN_NTSC_DATA2 = 424,\n\tFN_NTSC_DATA3 = 425,\n\tFN_NTSC_DATA4 = 426,\n\tFN_HSI_1_0_PORT143 = 427,\n\tFN_HSI_1_0_PORT144 = 428,\n\tFN_HSI_1_0_PORT145 = 429,\n\tFN_HSI_1_0_PORT146 = 430,\n\tFN_HSI_1_0_PORT147 = 431,\n\tFN_HSI_1_0_PORT148 = 432,\n\tFN_HSI_1_0_PORT149 = 433,\n\tFN_HSI_1_0_PORT150 = 434,\n\tFN_UART_1_0_PORT157 = 435,\n\tFN_UART_1_0_PORT158 = 436,\n\tFN_NTSC_DATA5 = 437,\n\tFN_NTSC_DATA6 = 438,\n\tFN_NTSC_DATA7 = 439,\n\tFN_CAM_CLKO = 440,\n\tFN_CAM_CLKI = 441,\n\tFN_CAM_VS = 442,\n\tFN_CAM_HS = 443,\n\tFN_CAM_YUV0 = 444,\n\tFN_CAM_YUV1 = 445,\n\tFN_CAM_YUV2 = 446,\n\tFN_CAM_YUV3 = 447,\n\tFN_CAM_YUV4 = 448,\n\tFN_CAM_YUV5 = 449,\n\tFN_CAM_YUV6 = 450,\n\tFN_CAM_YUV7 = 451,\n\tFN_JT_TDO = 452,\n\tFN_JT_TDOEN = 453,\n\tFN_LOWPWR = 454,\n\tFN_USB_VBUS = 455,\n\tFN_UART1_RX = 456,\n\tFN_UART1_TX = 457,\n\tFN_SEL_LCD3_1_0_00 = 458,\n\tFN_SEL_LCD3_1_0_01 = 459,\n\tFN_SEL_LCD3_9_8_00 = 460,\n\tFN_SEL_LCD3_9_8_10 = 461,\n\tFN_SEL_LCD3_11_10_00 = 462,\n\tFN_SEL_LCD3_11_10_01 = 463,\n\tFN_SEL_LCD3_11_10_10 = 464,\n\tFN_SEL_IIC_1_0_00 = 465,\n\tFN_SEL_IIC_1_0_01 = 466,\n\tFN_SEL_AB_1_0_00 = 467,\n\tFN_SEL_AB_1_0_10 = 468,\n\tFN_SEL_AB_3_2_00 = 469,\n\tFN_SEL_AB_3_2_01 = 470,\n\tFN_SEL_AB_3_2_10 = 471,\n\tFN_SEL_AB_3_2_11 = 472,\n\tFN_SEL_AB_5_4_00 = 473,\n\tFN_SEL_AB_5_4_01 = 474,\n\tFN_SEL_AB_5_4_10 = 475,\n\tFN_SEL_AB_5_4_11 = 476,\n\tFN_SEL_AB_7_6_00 = 477,\n\tFN_SEL_AB_7_6_01 = 478,\n\tFN_SEL_AB_7_6_10 = 479,\n\tFN_SEL_AB_9_8_00 = 480,\n\tFN_SEL_AB_9_8_01 = 481,\n\tFN_SEL_AB_9_8_10 = 482,\n\tFN_SEL_AB_11_10_00 = 483,\n\tFN_SEL_AB_11_10_10 = 484,\n\tFN_SEL_AB_13_12_00 = 485,\n\tFN_SEL_AB_13_12_10 = 486,\n\tFN_SEL_USI_1_0_00 = 487,\n\tFN_SEL_USI_1_0_01 = 488,\n\tFN_SEL_USI_3_2_00 = 489,\n\tFN_SEL_USI_3_2_01 = 490,\n\tFN_SEL_USI_5_4_00 = 491,\n\tFN_SEL_USI_5_4_01 = 492,\n\tFN_SEL_USI_7_6_00 = 493,\n\tFN_SEL_USI_7_6_01 = 494,\n\tFN_SEL_USI_9_8_00 = 495,\n\tFN_SEL_USI_9_8_01 = 496,\n\tFN_SEL_HSI_1_0_00 = 497,\n\tFN_SEL_HSI_1_0_01 = 498,\n\tFN_SEL_UART_1_0_00 = 499,\n\tFN_SEL_UART_1_0_01 = 500,\n\tPINMUX_FUNCTION_END___9 = 501,\n\tPINMUX_MARK_BEGIN___9 = 502,\n\tJT_SEL_MARK = 503,\n\tERR_RST_REQB_MARK = 504,\n\tREF_CLKO_MARK = 505,\n\tEXT_CLKI_MARK = 506,\n\tLCD3_PXCLKB_MARK = 507,\n\tSD_CKI_MARK = 508,\n\tLCD3_R0_MARK = 509,\n\tLCD3_R1_MARK = 510,\n\tLCD3_R2_MARK = 511,\n\tLCD3_R3_MARK = 512,\n\tLCD3_R4_MARK = 513,\n\tLCD3_R5_MARK = 514,\n\tIIC0_SCL_MARK___3 = 515,\n\tIIC0_SDA_MARK___3 = 516,\n\tSDI0_CKO_MARK = 517,\n\tSDI0_CKI_MARK = 518,\n\tSDI0_CMD_MARK = 519,\n\tSDI0_DATA0_MARK = 520,\n\tSDI0_DATA1_MARK = 521,\n\tSDI0_DATA2_MARK = 522,\n\tSDI0_DATA3_MARK = 523,\n\tSDI0_DATA4_MARK = 524,\n\tSDI0_DATA5_MARK = 525,\n\tSDI0_DATA6_MARK = 526,\n\tSDI0_DATA7_MARK = 527,\n\tSDI1_CKO_MARK = 528,\n\tSDI1_CKI_MARK = 529,\n\tSDI1_CMD_MARK = 530,\n\tSDI1_DATA0_MARK = 531,\n\tSDI1_DATA1_MARK = 532,\n\tSDI1_DATA2_MARK = 533,\n\tSDI1_DATA3_MARK = 534,\n\tAB_CLK_MARK = 535,\n\tAB_CSB0_MARK = 536,\n\tAB_CSB1_MARK = 537,\n\tAB_A20_MARK = 538,\n\tUSI0_CS1_MARK = 539,\n\tUSI0_CS2_MARK = 540,\n\tUSI1_DI_MARK = 541,\n\tUSI1_DO_MARK = 542,\n\tNTSC_CLK_MARK = 543,\n\tNTSC_DATA0_MARK = 544,\n\tNTSC_DATA1_MARK = 545,\n\tNTSC_DATA2_MARK = 546,\n\tNTSC_DATA3_MARK = 547,\n\tNTSC_DATA4_MARK = 548,\n\tNTSC_DATA5_MARK = 549,\n\tNTSC_DATA6_MARK = 550,\n\tNTSC_DATA7_MARK = 551,\n\tCAM_CLKO_MARK = 552,\n\tCAM_CLKI_MARK = 553,\n\tCAM_VS_MARK = 554,\n\tCAM_HS_MARK = 555,\n\tCAM_YUV0_MARK = 556,\n\tCAM_YUV1_MARK = 557,\n\tCAM_YUV2_MARK = 558,\n\tCAM_YUV3_MARK = 559,\n\tCAM_YUV4_MARK = 560,\n\tCAM_YUV5_MARK = 561,\n\tCAM_YUV6_MARK = 562,\n\tCAM_YUV7_MARK = 563,\n\tJT_TDO_MARK = 564,\n\tJT_TDOEN_MARK = 565,\n\tUSB_VBUS_MARK = 566,\n\tLOWPWR_MARK = 567,\n\tUART1_RX_MARK = 568,\n\tUART1_TX_MARK = 569,\n\tLCD3_PXCLK_MARK = 570,\n\tLCD3_CLK_I_MARK = 571,\n\tLCD3_HS_MARK = 572,\n\tLCD3_VS_MARK = 573,\n\tLCD3_DE_MARK = 574,\n\tLCD3_R6_MARK = 575,\n\tLCD3_R7_MARK = 576,\n\tLCD3_G0_MARK = 577,\n\tLCD3_G1_MARK = 578,\n\tLCD3_G2_MARK = 579,\n\tLCD3_G3_MARK = 580,\n\tLCD3_G4_MARK = 581,\n\tLCD3_G5_MARK = 582,\n\tLCD3_G6_MARK = 583,\n\tLCD3_G7_MARK = 584,\n\tLCD3_B0_MARK = 585,\n\tLCD3_B1_MARK = 586,\n\tLCD3_B2_MARK = 587,\n\tLCD3_B3_MARK = 588,\n\tLCD3_B4_MARK = 589,\n\tLCD3_B5_MARK = 590,\n\tLCD3_B6_MARK = 591,\n\tLCD3_B7_MARK = 592,\n\tYUV3_CLK_O_MARK = 593,\n\tYUV3_CLK_I_MARK = 594,\n\tYUV3_HS_MARK = 595,\n\tYUV3_VS_MARK = 596,\n\tYUV3_DE_MARK = 597,\n\tYUV3_D0_MARK = 598,\n\tYUV3_D1_MARK = 599,\n\tYUV3_D2_MARK = 600,\n\tYUV3_D3_MARK = 601,\n\tYUV3_D4_MARK = 602,\n\tYUV3_D5_MARK = 603,\n\tYUV3_D6_MARK = 604,\n\tYUV3_D7_MARK = 605,\n\tYUV3_D8_MARK = 606,\n\tYUV3_D9_MARK = 607,\n\tYUV3_D10_MARK = 608,\n\tYUV3_D11_MARK = 609,\n\tYUV3_D12_MARK = 610,\n\tYUV3_D13_MARK = 611,\n\tYUV3_D14_MARK = 612,\n\tYUV3_D15_MARK = 613,\n\tTP33_CLK_MARK = 614,\n\tTP33_CTRL_MARK = 615,\n\tTP33_DATA0_MARK = 616,\n\tTP33_DATA1_MARK = 617,\n\tTP33_DATA2_MARK = 618,\n\tTP33_DATA3_MARK = 619,\n\tTP33_DATA4_MARK = 620,\n\tTP33_DATA5_MARK = 621,\n\tTP33_DATA6_MARK = 622,\n\tTP33_DATA7_MARK = 623,\n\tTP33_DATA8_MARK = 624,\n\tTP33_DATA9_MARK = 625,\n\tTP33_DATA10_MARK = 626,\n\tTP33_DATA11_MARK = 627,\n\tTP33_DATA12_MARK = 628,\n\tTP33_DATA13_MARK = 629,\n\tTP33_DATA14_MARK = 630,\n\tTP33_DATA15_MARK = 631,\n\tIIC1_SCL_MARK___2 = 632,\n\tIIC1_SDA_MARK___2 = 633,\n\tUART3_RX_MARK = 634,\n\tUART3_TX_MARK = 635,\n\tAB_CSB2_MARK = 636,\n\tAB_CSB3_MARK = 637,\n\tAB_RDB_MARK = 638,\n\tAB_WRB_MARK = 639,\n\tAB_WAIT_MARK = 640,\n\tAB_ADV_MARK = 641,\n\tAB_AD0_MARK = 642,\n\tAB_AD1_MARK = 643,\n\tAB_AD2_MARK = 644,\n\tAB_AD3_MARK = 645,\n\tAB_AD4_MARK = 646,\n\tAB_AD5_MARK = 647,\n\tAB_AD6_MARK = 648,\n\tAB_AD7_MARK = 649,\n\tAB_AD8_MARK = 650,\n\tAB_AD9_MARK = 651,\n\tAB_AD10_MARK = 652,\n\tAB_AD11_MARK = 653,\n\tAB_AD12_MARK = 654,\n\tAB_AD13_MARK = 655,\n\tAB_AD14_MARK = 656,\n\tAB_AD15_MARK = 657,\n\tAB_A17_MARK = 658,\n\tAB_A18_MARK = 659,\n\tAB_A19_MARK = 660,\n\tAB_A21_MARK = 661,\n\tAB_A22_MARK = 662,\n\tAB_A23_MARK = 663,\n\tAB_A24_MARK = 664,\n\tAB_A25_MARK = 665,\n\tAB_A26_MARK = 666,\n\tAB_A27_MARK = 667,\n\tAB_A28_MARK = 668,\n\tAB_BEN0_MARK = 669,\n\tAB_BEN1_MARK = 670,\n\tDTV_BCLK_A_MARK = 671,\n\tDTV_PSYNC_A_MARK = 672,\n\tDTV_VALID_A_MARK = 673,\n\tDTV_DATA_A_MARK = 674,\n\tSDI2_CKO_MARK = 675,\n\tSDI2_CKI_MARK = 676,\n\tSDI2_CMD_MARK = 677,\n\tSDI2_DATA0_MARK = 678,\n\tSDI2_DATA1_MARK = 679,\n\tSDI2_DATA2_MARK = 680,\n\tSDI2_DATA3_MARK = 681,\n\tCF_CSB0_MARK = 682,\n\tCF_CSB1_MARK = 683,\n\tCF_IORDB_MARK = 684,\n\tCF_IOWRB_MARK = 685,\n\tCF_IORDY_MARK = 686,\n\tCF_RESET_MARK = 687,\n\tCF_D00_MARK = 688,\n\tCF_D01_MARK = 689,\n\tCF_D02_MARK = 690,\n\tCF_D03_MARK = 691,\n\tCF_D04_MARK = 692,\n\tCF_D05_MARK = 693,\n\tCF_D06_MARK = 694,\n\tCF_D07_MARK = 695,\n\tCF_D08_MARK = 696,\n\tCF_D09_MARK = 697,\n\tCF_D10_MARK = 698,\n\tCF_D11_MARK = 699,\n\tCF_D12_MARK = 700,\n\tCF_D13_MARK = 701,\n\tCF_D14_MARK = 702,\n\tCF_D15_MARK = 703,\n\tCF_A00_MARK = 704,\n\tCF_A01_MARK = 705,\n\tCF_A02_MARK = 706,\n\tCF_INTRQ_MARK = 707,\n\tCF_INPACKB_MARK = 708,\n\tCF_CDB1_MARK = 709,\n\tCF_CDB2_MARK = 710,\n\tUSI5_CLK_A_MARK = 711,\n\tUSI5_DI_A_MARK = 712,\n\tUSI5_DO_A_MARK = 713,\n\tUSI5_CS0_A_MARK = 714,\n\tUSI5_CS1_A_MARK = 715,\n\tUSI5_CS2_A_MARK = 716,\n\tUSI0_CS3_MARK = 717,\n\tUSI0_CS4_MARK = 718,\n\tUSI0_CS5_MARK = 719,\n\tUSI0_CS6_MARK = 720,\n\tUSI2_CLK_MARK = 721,\n\tUSI2_DI_MARK = 722,\n\tUSI2_DO_MARK = 723,\n\tUSI2_CS0_MARK = 724,\n\tUSI2_CS1_MARK = 725,\n\tUSI2_CS2_MARK = 726,\n\tUSI3_CLK_MARK = 727,\n\tUSI3_DI_MARK = 728,\n\tUSI3_DO_MARK = 729,\n\tUSI3_CS0_MARK = 730,\n\tUSI4_CLK_MARK = 731,\n\tUSI4_DI_MARK = 732,\n\tUSI4_DO_MARK = 733,\n\tUSI4_CS0_MARK = 734,\n\tUSI4_CS1_MARK = 735,\n\tPWM0_MARK___4 = 736,\n\tPWM1_MARK___5 = 737,\n\tDTV_BCLK_B_MARK = 738,\n\tDTV_PSYNC_B_MARK = 739,\n\tDTV_VALID_B_MARK = 740,\n\tDTV_DATA_B_MARK = 741,\n\tUSI5_CLK_B_MARK = 742,\n\tUSI5_DO_B_MARK = 743,\n\tUSI5_CS0_B_MARK = 744,\n\tUSI5_CS1_B_MARK = 745,\n\tUSI5_CS2_B_MARK = 746,\n\tUSI5_CS3_B_MARK = 747,\n\tUSI5_CS4_B_MARK = 748,\n\tUSI5_DI_B_MARK = 749,\n\tUART1_CTSB_MARK = 750,\n\tUART1_RTSB_MARK = 751,\n\tUART2_RX_MARK = 752,\n\tUART2_TX_MARK = 753,\n\tPINMUX_MARK_END___9 = 754,\n};\n\nenum {\n\tPINMUX_RESERVED___10 = 0,\n\tPINMUX_DATA_BEGIN___10 = 1,\n\tGP_0_0_DATA___6 = 2,\n\tGP_0_1_DATA___6 = 3,\n\tGP_0_2_DATA___6 = 4,\n\tGP_0_3_DATA___6 = 5,\n\tGP_0_4_DATA___6 = 6,\n\tGP_0_5_DATA___6 = 7,\n\tGP_0_6_DATA___6 = 8,\n\tGP_0_7_DATA___6 = 9,\n\tGP_0_8_DATA___6 = 10,\n\tGP_0_9_DATA___6 = 11,\n\tGP_0_10_DATA___6 = 12,\n\tGP_0_11_DATA___6 = 13,\n\tGP_0_12_DATA___6 = 14,\n\tGP_0_13_DATA___6 = 15,\n\tGP_0_14_DATA___6 = 16,\n\tGP_0_15_DATA___6 = 17,\n\tGP_0_16_DATA___6 = 18,\n\tGP_0_17_DATA___6 = 19,\n\tGP_0_18_DATA___6 = 20,\n\tGP_0_19_DATA___6 = 21,\n\tGP_0_20_DATA___6 = 22,\n\tGP_0_21_DATA___6 = 23,\n\tGP_0_22_DATA___6 = 24,\n\tGP_0_23_DATA___5 = 25,\n\tGP_0_24_DATA___5 = 26,\n\tGP_0_25_DATA___5 = 27,\n\tGP_0_26_DATA___5 = 28,\n\tGP_0_27_DATA___5 = 29,\n\tGP_0_28_DATA___5 = 30,\n\tGP_1_0_DATA___6 = 31,\n\tGP_1_1_DATA___6 = 32,\n\tGP_1_2_DATA___6 = 33,\n\tGP_1_3_DATA___6 = 34,\n\tGP_1_4_DATA___6 = 35,\n\tGP_1_5_DATA___6 = 36,\n\tGP_1_6_DATA___6 = 37,\n\tGP_1_7_DATA___6 = 38,\n\tGP_1_8_DATA___6 = 39,\n\tGP_1_9_DATA___6 = 40,\n\tGP_1_10_DATA___6 = 41,\n\tGP_1_11_DATA___6 = 42,\n\tGP_1_12_DATA___6 = 43,\n\tGP_1_13_DATA___6 = 44,\n\tGP_1_14_DATA___6 = 45,\n\tGP_1_15_DATA___6 = 46,\n\tGP_1_16_DATA___6 = 47,\n\tGP_1_17_DATA___6 = 48,\n\tGP_1_18_DATA___6 = 49,\n\tGP_1_19_DATA___6 = 50,\n\tGP_1_20_DATA___6 = 51,\n\tGP_1_21_DATA___6 = 52,\n\tGP_1_22_DATA___6 = 53,\n\tGP_2_0_DATA___6 = 54,\n\tGP_2_1_DATA___6 = 55,\n\tGP_2_2_DATA___6 = 56,\n\tGP_2_3_DATA___6 = 57,\n\tGP_2_4_DATA___6 = 58,\n\tGP_2_5_DATA___6 = 59,\n\tGP_2_6_DATA___6 = 60,\n\tGP_2_7_DATA___6 = 61,\n\tGP_2_8_DATA___6 = 62,\n\tGP_2_9_DATA___6 = 63,\n\tGP_2_10_DATA___6 = 64,\n\tGP_2_11_DATA___6 = 65,\n\tGP_2_12_DATA___6 = 66,\n\tGP_2_13_DATA___6 = 67,\n\tGP_2_14_DATA___6 = 68,\n\tGP_2_15_DATA___6 = 69,\n\tGP_2_16_DATA___6 = 70,\n\tGP_2_17_DATA___6 = 71,\n\tGP_2_18_DATA___6 = 72,\n\tGP_2_19_DATA___6 = 73,\n\tGP_2_20_DATA___6 = 74,\n\tGP_2_21_DATA___6 = 75,\n\tGP_2_22_DATA___6 = 76,\n\tGP_2_23_DATA___6 = 77,\n\tGP_2_24_DATA___6 = 78,\n\tGP_2_25_DATA___6 = 79,\n\tGP_2_26_DATA___6 = 80,\n\tGP_2_27_DATA___6 = 81,\n\tGP_2_28_DATA___6 = 82,\n\tGP_2_29_DATA___6 = 83,\n\tGP_2_30_DATA___6 = 84,\n\tGP_2_31_DATA___6 = 85,\n\tGP_3_0_DATA___6 = 86,\n\tGP_3_1_DATA___6 = 87,\n\tGP_3_2_DATA___6 = 88,\n\tGP_3_3_DATA___6 = 89,\n\tGP_3_4_DATA___6 = 90,\n\tGP_3_5_DATA___6 = 91,\n\tGP_3_6_DATA___6 = 92,\n\tGP_3_7_DATA___6 = 93,\n\tGP_3_8_DATA___6 = 94,\n\tGP_3_9_DATA___6 = 95,\n\tGP_3_10_DATA___6 = 96,\n\tGP_3_11_DATA___6 = 97,\n\tGP_3_12_DATA___6 = 98,\n\tGP_3_13_DATA___6 = 99,\n\tGP_3_14_DATA___6 = 100,\n\tGP_3_15_DATA___6 = 101,\n\tGP_3_16_DATA___6 = 102,\n\tGP_3_17_DATA___5 = 103,\n\tGP_3_18_DATA___5 = 104,\n\tGP_3_19_DATA___5 = 105,\n\tGP_3_20_DATA___5 = 106,\n\tGP_3_21_DATA___5 = 107,\n\tGP_3_22_DATA___5 = 108,\n\tGP_3_23_DATA___5 = 109,\n\tGP_3_24_DATA___5 = 110,\n\tGP_3_25_DATA___5 = 111,\n\tGP_3_26_DATA___5 = 112,\n\tGP_3_27_DATA___6 = 113,\n\tGP_4_0_DATA___6 = 114,\n\tGP_4_1_DATA___6 = 115,\n\tGP_4_2_DATA___6 = 116,\n\tGP_4_3_DATA___6 = 117,\n\tGP_4_4_DATA___6 = 118,\n\tGP_4_5_DATA___6 = 119,\n\tGP_4_6_DATA___6 = 120,\n\tGP_4_7_DATA___6 = 121,\n\tGP_4_8_DATA___6 = 122,\n\tGP_4_9_DATA___6 = 123,\n\tGP_4_10_DATA___6 = 124,\n\tGP_4_11_DATA___6 = 125,\n\tGP_4_12_DATA___6 = 126,\n\tGP_4_13_DATA___6 = 127,\n\tGP_4_14_DATA___6 = 128,\n\tGP_4_15_DATA___6 = 129,\n\tGP_4_16_DATA___6 = 130,\n\tGP_5_0_DATA___5 = 131,\n\tGP_5_1_DATA___5 = 132,\n\tGP_5_2_DATA___5 = 133,\n\tGP_5_3_DATA___5 = 134,\n\tGP_5_4_DATA___5 = 135,\n\tGP_5_5_DATA___5 = 136,\n\tGP_5_6_DATA___5 = 137,\n\tGP_5_7_DATA___5 = 138,\n\tGP_5_8_DATA___5 = 139,\n\tGP_5_9_DATA___5 = 140,\n\tGP_5_10_DATA___5 = 141,\n\tGP_5_11_DATA___5 = 142,\n\tGP_5_12_DATA___5 = 143,\n\tGP_5_13_DATA___5 = 144,\n\tGP_5_14_DATA___5 = 145,\n\tGP_5_15_DATA___5 = 146,\n\tGP_5_16_DATA___5 = 147,\n\tGP_6_0_DATA___4 = 148,\n\tGP_6_1_DATA___4 = 149,\n\tGP_6_2_DATA___4 = 150,\n\tGP_6_3_DATA___4 = 151,\n\tGP_6_4_DATA___4 = 152,\n\tGP_6_5_DATA___4 = 153,\n\tGP_6_6_DATA___4 = 154,\n\tGP_6_7_DATA___4 = 155,\n\tGP_6_8_DATA___4 = 156,\n\tGP_6_9_DATA___3 = 157,\n\tGP_6_10_DATA___3 = 158,\n\tGP_6_11_DATA___3 = 159,\n\tGP_6_12_DATA___3 = 160,\n\tGP_6_13_DATA___3 = 161,\n\tGP_6_14_DATA___3 = 162,\n\tGP_6_15_DATA___3 = 163,\n\tGP_6_16_DATA___3 = 164,\n\tGP_7_0_DATA___2 = 165,\n\tGP_7_1_DATA___2 = 166,\n\tGP_7_2_DATA___2 = 167,\n\tGP_7_3_DATA___2 = 168,\n\tGP_7_4_DATA___2 = 169,\n\tGP_7_5_DATA___2 = 170,\n\tGP_7_6_DATA___2 = 171,\n\tGP_7_7_DATA___2 = 172,\n\tGP_7_8_DATA___2 = 173,\n\tGP_7_9_DATA___2 = 174,\n\tGP_7_10_DATA___2 = 175,\n\tGP_7_11_DATA___2 = 176,\n\tGP_7_12_DATA___2 = 177,\n\tGP_7_13_DATA___2 = 178,\n\tGP_7_14_DATA___2 = 179,\n\tGP_7_15_DATA___2 = 180,\n\tGP_7_16_DATA___2 = 181,\n\tGP_8_0_DATA = 182,\n\tGP_8_1_DATA = 183,\n\tGP_8_2_DATA = 184,\n\tGP_8_3_DATA = 185,\n\tGP_8_4_DATA = 186,\n\tGP_8_5_DATA = 187,\n\tGP_8_6_DATA = 188,\n\tGP_8_7_DATA = 189,\n\tGP_8_8_DATA = 190,\n\tGP_8_9_DATA = 191,\n\tGP_8_10_DATA = 192,\n\tGP_8_11_DATA = 193,\n\tGP_8_12_DATA = 194,\n\tGP_8_13_DATA = 195,\n\tGP_8_14_DATA = 196,\n\tGP_8_15_DATA = 197,\n\tGP_8_16_DATA = 198,\n\tGP_9_0_DATA = 199,\n\tGP_9_1_DATA = 200,\n\tGP_9_2_DATA = 201,\n\tGP_9_3_DATA = 202,\n\tGP_9_4_DATA = 203,\n\tGP_9_5_DATA = 204,\n\tGP_9_6_DATA = 205,\n\tGP_9_7_DATA = 206,\n\tGP_9_8_DATA = 207,\n\tGP_9_9_DATA = 208,\n\tGP_9_10_DATA = 209,\n\tGP_9_11_DATA = 210,\n\tGP_9_12_DATA = 211,\n\tGP_9_13_DATA = 212,\n\tGP_9_14_DATA = 213,\n\tGP_9_15_DATA = 214,\n\tGP_9_16_DATA = 215,\n\tGP_10_0_DATA = 216,\n\tGP_10_1_DATA = 217,\n\tGP_10_2_DATA = 218,\n\tGP_10_3_DATA = 219,\n\tGP_10_4_DATA = 220,\n\tGP_10_5_DATA = 221,\n\tGP_10_6_DATA = 222,\n\tGP_10_7_DATA = 223,\n\tGP_10_8_DATA = 224,\n\tGP_10_9_DATA = 225,\n\tGP_10_10_DATA = 226,\n\tGP_10_11_DATA = 227,\n\tGP_10_12_DATA = 228,\n\tGP_10_13_DATA = 229,\n\tGP_10_14_DATA = 230,\n\tGP_10_15_DATA = 231,\n\tGP_10_16_DATA = 232,\n\tGP_10_17_DATA = 233,\n\tGP_10_18_DATA = 234,\n\tGP_10_19_DATA = 235,\n\tGP_10_20_DATA = 236,\n\tGP_10_21_DATA = 237,\n\tGP_10_22_DATA = 238,\n\tGP_10_23_DATA = 239,\n\tGP_10_24_DATA = 240,\n\tGP_10_25_DATA = 241,\n\tGP_10_26_DATA = 242,\n\tGP_10_27_DATA = 243,\n\tGP_10_28_DATA = 244,\n\tGP_10_29_DATA = 245,\n\tGP_10_30_DATA = 246,\n\tGP_10_31_DATA = 247,\n\tGP_11_0_DATA = 248,\n\tGP_11_1_DATA = 249,\n\tGP_11_2_DATA = 250,\n\tGP_11_3_DATA = 251,\n\tGP_11_4_DATA = 252,\n\tGP_11_5_DATA = 253,\n\tGP_11_6_DATA = 254,\n\tGP_11_7_DATA = 255,\n\tGP_11_8_DATA = 256,\n\tGP_11_9_DATA = 257,\n\tGP_11_10_DATA = 258,\n\tGP_11_11_DATA = 259,\n\tGP_11_12_DATA = 260,\n\tGP_11_13_DATA = 261,\n\tGP_11_14_DATA = 262,\n\tGP_11_15_DATA = 263,\n\tGP_11_16_DATA = 264,\n\tGP_11_17_DATA = 265,\n\tGP_11_18_DATA = 266,\n\tGP_11_19_DATA = 267,\n\tGP_11_20_DATA = 268,\n\tGP_11_21_DATA = 269,\n\tGP_11_22_DATA = 270,\n\tGP_11_23_DATA = 271,\n\tGP_11_24_DATA = 272,\n\tGP_11_25_DATA = 273,\n\tGP_11_26_DATA = 274,\n\tGP_11_27_DATA = 275,\n\tGP_11_28_DATA = 276,\n\tGP_11_29_DATA = 277,\n\tPINMUX_DATA_END___10 = 278,\n\tPINMUX_FUNCTION_BEGIN___10 = 279,\n\tGP_0_0_FN___6 = 280,\n\tGP_0_1_FN___6 = 281,\n\tGP_0_2_FN___6 = 282,\n\tGP_0_3_FN___6 = 283,\n\tGP_0_4_FN___6 = 284,\n\tGP_0_5_FN___6 = 285,\n\tGP_0_6_FN___6 = 286,\n\tGP_0_7_FN___6 = 287,\n\tGP_0_8_FN___6 = 288,\n\tGP_0_9_FN___6 = 289,\n\tGP_0_10_FN___6 = 290,\n\tGP_0_11_FN___6 = 291,\n\tGP_0_12_FN___6 = 292,\n\tGP_0_13_FN___6 = 293,\n\tGP_0_14_FN___6 = 294,\n\tGP_0_15_FN___6 = 295,\n\tGP_0_16_FN___6 = 296,\n\tGP_0_17_FN___6 = 297,\n\tGP_0_18_FN___6 = 298,\n\tGP_0_19_FN___6 = 299,\n\tGP_0_20_FN___6 = 300,\n\tGP_0_21_FN___6 = 301,\n\tGP_0_22_FN___6 = 302,\n\tGP_0_23_FN___5 = 303,\n\tGP_0_24_FN___5 = 304,\n\tGP_0_25_FN___5 = 305,\n\tGP_0_26_FN___5 = 306,\n\tGP_0_27_FN___5 = 307,\n\tGP_0_28_FN___5 = 308,\n\tGP_1_0_FN___6 = 309,\n\tGP_1_1_FN___6 = 310,\n\tGP_1_2_FN___6 = 311,\n\tGP_1_3_FN___6 = 312,\n\tGP_1_4_FN___6 = 313,\n\tGP_1_5_FN___6 = 314,\n\tGP_1_6_FN___6 = 315,\n\tGP_1_7_FN___6 = 316,\n\tGP_1_8_FN___6 = 317,\n\tGP_1_9_FN___6 = 318,\n\tGP_1_10_FN___6 = 319,\n\tGP_1_11_FN___6 = 320,\n\tGP_1_12_FN___6 = 321,\n\tGP_1_13_FN___6 = 322,\n\tGP_1_14_FN___6 = 323,\n\tGP_1_15_FN___6 = 324,\n\tGP_1_16_FN___6 = 325,\n\tGP_1_17_FN___6 = 326,\n\tGP_1_18_FN___6 = 327,\n\tGP_1_19_FN___6 = 328,\n\tGP_1_20_FN___6 = 329,\n\tGP_1_21_FN___6 = 330,\n\tGP_1_22_FN___6 = 331,\n\tGP_2_0_FN___6 = 332,\n\tGP_2_1_FN___6 = 333,\n\tGP_2_2_FN___6 = 334,\n\tGP_2_3_FN___6 = 335,\n\tGP_2_4_FN___6 = 336,\n\tGP_2_5_FN___6 = 337,\n\tGP_2_6_FN___6 = 338,\n\tGP_2_7_FN___6 = 339,\n\tGP_2_8_FN___6 = 340,\n\tGP_2_9_FN___6 = 341,\n\tGP_2_10_FN___6 = 342,\n\tGP_2_11_FN___6 = 343,\n\tGP_2_12_FN___6 = 344,\n\tGP_2_13_FN___6 = 345,\n\tGP_2_14_FN___6 = 346,\n\tGP_2_15_FN___6 = 347,\n\tGP_2_16_FN___6 = 348,\n\tGP_2_17_FN___6 = 349,\n\tGP_2_18_FN___6 = 350,\n\tGP_2_19_FN___6 = 351,\n\tGP_2_20_FN___6 = 352,\n\tGP_2_21_FN___6 = 353,\n\tGP_2_22_FN___6 = 354,\n\tGP_2_23_FN___6 = 355,\n\tGP_2_24_FN___6 = 356,\n\tGP_2_25_FN___6 = 357,\n\tGP_2_26_FN___6 = 358,\n\tGP_2_27_FN___6 = 359,\n\tGP_2_28_FN___6 = 360,\n\tGP_2_29_FN___6 = 361,\n\tGP_2_30_FN___6 = 362,\n\tGP_2_31_FN___6 = 363,\n\tGP_3_0_FN___6 = 364,\n\tGP_3_1_FN___6 = 365,\n\tGP_3_2_FN___6 = 366,\n\tGP_3_3_FN___6 = 367,\n\tGP_3_4_FN___6 = 368,\n\tGP_3_5_FN___6 = 369,\n\tGP_3_6_FN___6 = 370,\n\tGP_3_7_FN___6 = 371,\n\tGP_3_8_FN___6 = 372,\n\tGP_3_9_FN___6 = 373,\n\tGP_3_10_FN___6 = 374,\n\tGP_3_11_FN___6 = 375,\n\tGP_3_12_FN___6 = 376,\n\tGP_3_13_FN___6 = 377,\n\tGP_3_14_FN___6 = 378,\n\tGP_3_15_FN___6 = 379,\n\tGP_3_16_FN___6 = 380,\n\tGP_3_17_FN___5 = 381,\n\tGP_3_18_FN___5 = 382,\n\tGP_3_19_FN___5 = 383,\n\tGP_3_20_FN___5 = 384,\n\tGP_3_21_FN___5 = 385,\n\tGP_3_22_FN___5 = 386,\n\tGP_3_23_FN___5 = 387,\n\tGP_3_24_FN___5 = 388,\n\tGP_3_25_FN___5 = 389,\n\tGP_3_26_FN___5 = 390,\n\tGP_3_27_FN___6 = 391,\n\tGP_4_0_FN___6 = 392,\n\tGP_4_1_FN___6 = 393,\n\tGP_4_2_FN___6 = 394,\n\tGP_4_3_FN___6 = 395,\n\tGP_4_4_FN___6 = 396,\n\tGP_4_5_FN___6 = 397,\n\tGP_4_6_FN___6 = 398,\n\tGP_4_7_FN___6 = 399,\n\tGP_4_8_FN___6 = 400,\n\tGP_4_9_FN___6 = 401,\n\tGP_4_10_FN___6 = 402,\n\tGP_4_11_FN___6 = 403,\n\tGP_4_12_FN___6 = 404,\n\tGP_4_13_FN___6 = 405,\n\tGP_4_14_FN___6 = 406,\n\tGP_4_15_FN___6 = 407,\n\tGP_4_16_FN___6 = 408,\n\tGP_5_0_FN___5 = 409,\n\tGP_5_1_FN___5 = 410,\n\tGP_5_2_FN___5 = 411,\n\tGP_5_3_FN___5 = 412,\n\tGP_5_4_FN___5 = 413,\n\tGP_5_5_FN___5 = 414,\n\tGP_5_6_FN___5 = 415,\n\tGP_5_7_FN___5 = 416,\n\tGP_5_8_FN___5 = 417,\n\tGP_5_9_FN___5 = 418,\n\tGP_5_10_FN___5 = 419,\n\tGP_5_11_FN___5 = 420,\n\tGP_5_12_FN___5 = 421,\n\tGP_5_13_FN___5 = 422,\n\tGP_5_14_FN___5 = 423,\n\tGP_5_15_FN___5 = 424,\n\tGP_5_16_FN___5 = 425,\n\tGP_6_0_FN___4 = 426,\n\tGP_6_1_FN___4 = 427,\n\tGP_6_2_FN___4 = 428,\n\tGP_6_3_FN___4 = 429,\n\tGP_6_4_FN___4 = 430,\n\tGP_6_5_FN___4 = 431,\n\tGP_6_6_FN___4 = 432,\n\tGP_6_7_FN___4 = 433,\n\tGP_6_8_FN___4 = 434,\n\tGP_6_9_FN___3 = 435,\n\tGP_6_10_FN___3 = 436,\n\tGP_6_11_FN___3 = 437,\n\tGP_6_12_FN___3 = 438,\n\tGP_6_13_FN___3 = 439,\n\tGP_6_14_FN___3 = 440,\n\tGP_6_15_FN___3 = 441,\n\tGP_6_16_FN___3 = 442,\n\tGP_7_0_FN___2 = 443,\n\tGP_7_1_FN___2 = 444,\n\tGP_7_2_FN___2 = 445,\n\tGP_7_3_FN___2 = 446,\n\tGP_7_4_FN___2 = 447,\n\tGP_7_5_FN___2 = 448,\n\tGP_7_6_FN___2 = 449,\n\tGP_7_7_FN___2 = 450,\n\tGP_7_8_FN___2 = 451,\n\tGP_7_9_FN___2 = 452,\n\tGP_7_10_FN___2 = 453,\n\tGP_7_11_FN___2 = 454,\n\tGP_7_12_FN___2 = 455,\n\tGP_7_13_FN___2 = 456,\n\tGP_7_14_FN___2 = 457,\n\tGP_7_15_FN___2 = 458,\n\tGP_7_16_FN___2 = 459,\n\tGP_8_0_FN = 460,\n\tGP_8_1_FN = 461,\n\tGP_8_2_FN = 462,\n\tGP_8_3_FN = 463,\n\tGP_8_4_FN = 464,\n\tGP_8_5_FN = 465,\n\tGP_8_6_FN = 466,\n\tGP_8_7_FN = 467,\n\tGP_8_8_FN = 468,\n\tGP_8_9_FN = 469,\n\tGP_8_10_FN = 470,\n\tGP_8_11_FN = 471,\n\tGP_8_12_FN = 472,\n\tGP_8_13_FN = 473,\n\tGP_8_14_FN = 474,\n\tGP_8_15_FN = 475,\n\tGP_8_16_FN = 476,\n\tGP_9_0_FN = 477,\n\tGP_9_1_FN = 478,\n\tGP_9_2_FN = 479,\n\tGP_9_3_FN = 480,\n\tGP_9_4_FN = 481,\n\tGP_9_5_FN = 482,\n\tGP_9_6_FN = 483,\n\tGP_9_7_FN = 484,\n\tGP_9_8_FN = 485,\n\tGP_9_9_FN = 486,\n\tGP_9_10_FN = 487,\n\tGP_9_11_FN = 488,\n\tGP_9_12_FN = 489,\n\tGP_9_13_FN = 490,\n\tGP_9_14_FN = 491,\n\tGP_9_15_FN = 492,\n\tGP_9_16_FN = 493,\n\tGP_10_0_FN = 494,\n\tGP_10_1_FN = 495,\n\tGP_10_2_FN = 496,\n\tGP_10_3_FN = 497,\n\tGP_10_4_FN = 498,\n\tGP_10_5_FN = 499,\n\tGP_10_6_FN = 500,\n\tGP_10_7_FN = 501,\n\tGP_10_8_FN = 502,\n\tGP_10_9_FN = 503,\n\tGP_10_10_FN = 504,\n\tGP_10_11_FN = 505,\n\tGP_10_12_FN = 506,\n\tGP_10_13_FN = 507,\n\tGP_10_14_FN = 508,\n\tGP_10_15_FN = 509,\n\tGP_10_16_FN = 510,\n\tGP_10_17_FN = 511,\n\tGP_10_18_FN = 512,\n\tGP_10_19_FN = 513,\n\tGP_10_20_FN = 514,\n\tGP_10_21_FN = 515,\n\tGP_10_22_FN = 516,\n\tGP_10_23_FN = 517,\n\tGP_10_24_FN = 518,\n\tGP_10_25_FN = 519,\n\tGP_10_26_FN = 520,\n\tGP_10_27_FN = 521,\n\tGP_10_28_FN = 522,\n\tGP_10_29_FN = 523,\n\tGP_10_30_FN = 524,\n\tGP_10_31_FN = 525,\n\tGP_11_0_FN = 526,\n\tGP_11_1_FN = 527,\n\tGP_11_2_FN = 528,\n\tGP_11_3_FN = 529,\n\tGP_11_4_FN = 530,\n\tGP_11_5_FN = 531,\n\tGP_11_6_FN = 532,\n\tGP_11_7_FN = 533,\n\tGP_11_8_FN = 534,\n\tGP_11_9_FN = 535,\n\tGP_11_10_FN = 536,\n\tGP_11_11_FN = 537,\n\tGP_11_12_FN = 538,\n\tGP_11_13_FN = 539,\n\tGP_11_14_FN = 540,\n\tGP_11_15_FN = 541,\n\tGP_11_16_FN = 542,\n\tGP_11_17_FN = 543,\n\tGP_11_18_FN = 544,\n\tGP_11_19_FN = 545,\n\tGP_11_20_FN = 546,\n\tGP_11_21_FN = 547,\n\tGP_11_22_FN = 548,\n\tGP_11_23_FN = 549,\n\tGP_11_24_FN = 550,\n\tGP_11_25_FN = 551,\n\tGP_11_26_FN = 552,\n\tGP_11_27_FN = 553,\n\tGP_11_28_FN = 554,\n\tGP_11_29_FN = 555,\n\tFN_IP0_0___3 = 556,\n\tFN_IP0_1___2 = 557,\n\tFN_IP0_2___2 = 558,\n\tFN_IP0_3___2 = 559,\n\tFN_IP0_4___2 = 560,\n\tFN_IP0_5___2 = 561,\n\tFN_IP0_6___2 = 562,\n\tFN_IP0_7___2 = 563,\n\tFN_IP0_8___2 = 564,\n\tFN_IP0_9___2 = 565,\n\tFN_IP0_10___3 = 566,\n\tFN_IP0_11___3 = 567,\n\tFN_IP0_12___3 = 568,\n\tFN_IP0_13___3 = 569,\n\tFN_IP0_14___3 = 570,\n\tFN_IP0_15___4 = 571,\n\tFN_IP0_16___3 = 572,\n\tFN_IP0_17___3 = 573,\n\tFN_IP0_18___2 = 574,\n\tFN_IP0_19___2 = 575,\n\tFN_IP0_20___2 = 576,\n\tFN_IP0_21___2 = 577,\n\tFN_IP0_22___2 = 578,\n\tFN_IP0_23___2 = 579,\n\tFN_IP1_0___2 = 580,\n\tFN_IP1_1___2 = 581,\n\tFN_IP1_2 = 582,\n\tFN_IP1_3 = 583,\n\tFN_IP1_4 = 584,\n\tFN_IP1_5 = 585,\n\tFN_IP1_6 = 586,\n\tFN_IP1_7 = 587,\n\tFN_IP1_8 = 588,\n\tFN_IP1_9 = 589,\n\tFN_IP1_10 = 590,\n\tFN_IP1_11 = 591,\n\tFN_IP1_12 = 592,\n\tFN_IP1_13 = 593,\n\tFN_IP1_14 = 594,\n\tFN_IP1_15 = 595,\n\tFN_IP1_16 = 596,\n\tFN_DU1_DB2_C0_DATA12 = 597,\n\tFN_DU1_DB3_C1_DATA13 = 598,\n\tFN_DU1_DB4_C2_DATA14 = 599,\n\tFN_DU1_DB5_C3_DATA15 = 600,\n\tFN_DU1_DB6_C4 = 601,\n\tFN_DU1_DB7_C5 = 602,\n\tFN_DU1_EXHSYNC_DU1_HSYNC___6 = 603,\n\tFN_DU1_EXVSYNC_DU1_VSYNC___6 = 604,\n\tFN_DU1_EXODDF_DU1_ODDF_DISP_CDE___6 = 605,\n\tFN_DU1_DISP___6 = 606,\n\tFN_DU1_CDE___6 = 607,\n\tFN_D0___5 = 608,\n\tFN_D1___5 = 609,\n\tFN_D2___5 = 610,\n\tFN_D3___5 = 611,\n\tFN_D4___5 = 612,\n\tFN_D5___5 = 613,\n\tFN_D6___5 = 614,\n\tFN_D7___5 = 615,\n\tFN_D8___5 = 616,\n\tFN_D9___5 = 617,\n\tFN_D10___5 = 618,\n\tFN_D11___5 = 619,\n\tFN_D12___4 = 620,\n\tFN_D13___4 = 621,\n\tFN_D14___4 = 622,\n\tFN_D15___4 = 623,\n\tFN_A0___6 = 624,\n\tFN_A1___6 = 625,\n\tFN_A2___6 = 626,\n\tFN_A3___6 = 627,\n\tFN_A4___6 = 628,\n\tFN_A5___6 = 629,\n\tFN_A6___6 = 630,\n\tFN_A7___6 = 631,\n\tFN_A8___6 = 632,\n\tFN_A9___6 = 633,\n\tFN_A10___6 = 634,\n\tFN_A11___6 = 635,\n\tFN_A12___6 = 636,\n\tFN_A13___6 = 637,\n\tFN_A14___6 = 638,\n\tFN_A15___6 = 639,\n\tFN_A16___6 = 640,\n\tFN_A17___6 = 641,\n\tFN_A18___6 = 642,\n\tFN_A19___6 = 643,\n\tFN_IP1_17 = 644,\n\tFN_IP1_18 = 645,\n\tFN_CS1_N_A26___4 = 646,\n\tFN_EX_CS0_N___3 = 647,\n\tFN_EX_CS1_N___3 = 648,\n\tFN_EX_CS2_N___3 = 649,\n\tFN_EX_CS3_N___3 = 650,\n\tFN_EX_CS4_N___3 = 651,\n\tFN_EX_CS5_N___3 = 652,\n\tFN_BS_N___4 = 653,\n\tFN_RD_N___4 = 654,\n\tFN_RD_WR_N___4 = 655,\n\tFN_WE0_N___4 = 656,\n\tFN_WE1_N___4 = 657,\n\tFN_EX_WAIT0___6 = 658,\n\tFN_IRQ0___6 = 659,\n\tFN_IRQ1___5 = 660,\n\tFN_IRQ2___5 = 661,\n\tFN_IRQ3___5 = 662,\n\tFN_IP1_19 = 663,\n\tFN_IP1_20 = 664,\n\tFN_IP1_21 = 665,\n\tFN_IP1_22 = 666,\n\tFN_CS0_N___4 = 667,\n\tFN_VI0_CLK___6 = 668,\n\tFN_VI0_CLKENB___6 = 669,\n\tFN_VI0_HSYNC_N___4 = 670,\n\tFN_VI0_VSYNC_N___4 = 671,\n\tFN_VI0_D0_B0_C0 = 672,\n\tFN_VI0_D1_B1_C1 = 673,\n\tFN_VI0_D2_B2_C2 = 674,\n\tFN_VI0_D3_B3_C3 = 675,\n\tFN_VI0_D4_B4_C4 = 676,\n\tFN_VI0_D5_B5_C5 = 677,\n\tFN_VI0_D6_B6_C6 = 678,\n\tFN_VI0_D7_B7_C7 = 679,\n\tFN_VI0_D8_G0_Y0 = 680,\n\tFN_VI0_D9_G1_Y1 = 681,\n\tFN_VI0_D10_G2_Y2 = 682,\n\tFN_VI0_D11_G3_Y3 = 683,\n\tFN_VI0_FIELD___6 = 684,\n\tFN_VI1_CLK___6 = 685,\n\tFN_VI1_CLKENB___6 = 686,\n\tFN_VI1_HSYNC_N___4 = 687,\n\tFN_VI1_VSYNC_N___4 = 688,\n\tFN_VI1_D0_B0_C0 = 689,\n\tFN_VI1_D1_B1_C1 = 690,\n\tFN_VI1_D2_B2_C2 = 691,\n\tFN_VI1_D3_B3_C3 = 692,\n\tFN_VI1_D4_B4_C4 = 693,\n\tFN_VI1_D5_B5_C5 = 694,\n\tFN_VI1_D6_B6_C6 = 695,\n\tFN_VI1_D7_B7_C7 = 696,\n\tFN_VI1_D8_G0_Y0 = 697,\n\tFN_VI1_D9_G1_Y1 = 698,\n\tFN_VI1_D10_G2_Y2 = 699,\n\tFN_VI1_D11_G3_Y3 = 700,\n\tFN_VI1_FIELD___6 = 701,\n\tFN_IP2_0 = 702,\n\tFN_IP2_1 = 703,\n\tFN_IP2_2 = 704,\n\tFN_IP2_3 = 705,\n\tFN_IP2_4 = 706,\n\tFN_IP2_5 = 707,\n\tFN_IP2_6 = 708,\n\tFN_IP2_7 = 709,\n\tFN_IP2_8 = 710,\n\tFN_IP2_9 = 711,\n\tFN_IP2_10 = 712,\n\tFN_IP2_11 = 713,\n\tFN_IP2_12 = 714,\n\tFN_IP2_13 = 715,\n\tFN_IP2_14 = 716,\n\tFN_IP2_15 = 717,\n\tFN_IP2_16 = 718,\n\tFN_IP3_0 = 719,\n\tFN_IP3_1 = 720,\n\tFN_IP3_2 = 721,\n\tFN_IP3_3___2 = 722,\n\tFN_IP3_4___2 = 723,\n\tFN_IP3_5___2 = 724,\n\tFN_IP3_6___2 = 725,\n\tFN_IP3_7___2 = 726,\n\tFN_IP3_8___2 = 727,\n\tFN_IP3_9 = 728,\n\tFN_IP3_10___2 = 729,\n\tFN_IP3_11___2 = 730,\n\tFN_IP3_12___2 = 731,\n\tFN_IP3_13 = 732,\n\tFN_VI3_D10_Y2 = 733,\n\tFN_IP3_14 = 734,\n\tFN_VI3_FIELD___2 = 735,\n\tFN_VI4_CLK = 736,\n\tFN_IP4_0___2 = 737,\n\tFN_IP4_1 = 738,\n\tFN_IP4_3_2 = 739,\n\tFN_IP4_4 = 740,\n\tFN_IP4_6_5 = 741,\n\tFN_IP4_8_7 = 742,\n\tFN_IP4_10_9___2 = 743,\n\tFN_IP4_12_11___2 = 744,\n\tFN_IP4_14_13___2 = 745,\n\tFN_IP4_16_15___2 = 746,\n\tFN_IP4_18_17 = 747,\n\tFN_IP4_20_19 = 748,\n\tFN_IP4_21___2 = 749,\n\tFN_IP4_22 = 750,\n\tFN_IP4_23___2 = 751,\n\tFN_IP4_24___2 = 752,\n\tFN_VI5_CLK = 753,\n\tFN_IP5_0 = 754,\n\tFN_IP5_1 = 755,\n\tFN_IP5_2 = 756,\n\tFN_IP5_3___2 = 757,\n\tFN_IP5_4___2 = 758,\n\tFN_IP5_5___2 = 759,\n\tFN_IP5_6___3 = 760,\n\tFN_IP5_7___3 = 761,\n\tFN_IP5_8___2 = 762,\n\tFN_IP5_9 = 763,\n\tFN_IP5_10 = 764,\n\tFN_IP5_11 = 765,\n\tFN_VI5_D9_Y1 = 766,\n\tFN_VI5_D10_Y2 = 767,\n\tFN_VI5_D11_Y3 = 768,\n\tFN_VI5_FIELD = 769,\n\tFN_IP6_0 = 770,\n\tFN_IP6_1 = 771,\n\tFN_HRTS0_N___3 = 772,\n\tFN_IP6_2 = 773,\n\tFN_IP6_3 = 774,\n\tFN_IP6_4 = 775,\n\tFN_IP6_5 = 776,\n\tFN_HCTS1_N___2 = 777,\n\tFN_IP6_6 = 778,\n\tFN_IP6_7___2 = 779,\n\tFN_SCK0___3 = 780,\n\tFN_CTS0_N = 781,\n\tFN_RTS0_N = 782,\n\tFN_TX0___3 = 783,\n\tFN_RX0___3 = 784,\n\tFN_SCK1___2 = 785,\n\tFN_CTS1_N = 786,\n\tFN_RTS1_N = 787,\n\tFN_TX1___3 = 788,\n\tFN_RX1___3 = 789,\n\tFN_IP6_9_8___2 = 790,\n\tFN_IP6_11_10___2 = 791,\n\tFN_IP6_13_12___2 = 792,\n\tFN_IP6_15_14___3 = 793,\n\tFN_IP6_16___3 = 794,\n\tFN_IP6_18_17___2 = 795,\n\tFN_SCIF_CLK___5 = 796,\n\tFN_CAN0_TX___4 = 797,\n\tFN_CAN0_RX___4 = 798,\n\tFN_CAN_CLK___4 = 799,\n\tFN_CAN1_TX___4 = 800,\n\tFN_CAN1_RX___4 = 801,\n\tFN_IP7_1_0___3 = 802,\n\tFN_IP7_3_2___3 = 803,\n\tFN_IP7_5_4___2 = 804,\n\tFN_IP7_6 = 805,\n\tFN_IP7_7 = 806,\n\tFN_SD0_CLK___6 = 807,\n\tFN_SD0_CMD___6 = 808,\n\tFN_SD0_DAT0___4 = 809,\n\tFN_SD0_DAT1___4 = 810,\n\tFN_SD0_DAT2___4 = 811,\n\tFN_SD0_DAT3___4 = 812,\n\tFN_SD0_CD___6 = 813,\n\tFN_SD0_WP___6 = 814,\n\tFN_IP7_9_8 = 815,\n\tFN_IP7_11_10 = 816,\n\tFN_IP7_13_12 = 817,\n\tFN_IP7_15_14 = 818,\n\tFN_IP7_16 = 819,\n\tFN_IP7_17 = 820,\n\tFN_IP7_18 = 821,\n\tFN_IP7_19 = 822,\n\tFN_IP7_20 = 823,\n\tFN_ADICLK___5 = 824,\n\tFN_ADICS_SAMP___5 = 825,\n\tFN_ADIDATA___5 = 826,\n\tFN_ADICHS0___5 = 827,\n\tFN_ADICHS1___5 = 828,\n\tFN_ADICHS2___5 = 829,\n\tFN_AVS1___3 = 830,\n\tFN_AVS2___3 = 831,\n\tFN_DU0_DR0_DATA0 = 832,\n\tFN_DU0_DR1_DATA1 = 833,\n\tFN_DU0_DR2_Y4_DATA2 = 834,\n\tFN_DU0_DR3_Y5_DATA3 = 835,\n\tFN_DU0_DR4_Y6_DATA4 = 836,\n\tFN_DU0_DR5_Y7_DATA5 = 837,\n\tFN_DU0_DR6_Y8_DATA6 = 838,\n\tFN_DU0_DR7_Y9_DATA7 = 839,\n\tFN_DU0_DG0_DATA8 = 840,\n\tFN_DU0_DG1_DATA9 = 841,\n\tFN_DU0_DG2_C6_DATA10 = 842,\n\tFN_DU0_DG3_C7_DATA11 = 843,\n\tFN_DU0_DG4_Y0_DATA12 = 844,\n\tFN_DU0_DG5_Y1_DATA13 = 845,\n\tFN_DU0_DG6_Y2_DATA14 = 846,\n\tFN_DU0_DG7_Y3_DATA15 = 847,\n\tFN_DU0_DB0___5 = 848,\n\tFN_DU0_DB1___5 = 849,\n\tFN_DU0_DB2_C0 = 850,\n\tFN_DU0_DB3_C1 = 851,\n\tFN_DU0_DB4_C2 = 852,\n\tFN_DU0_DB5_C3 = 853,\n\tFN_DU0_DB6_C4 = 854,\n\tFN_DU0_DB7_C5 = 855,\n\tFN_DU0_EXHSYNC_DU0_HSYNC___5 = 856,\n\tFN_DU0_EXVSYNC_DU0_VSYNC___5 = 857,\n\tFN_DU0_EXODDF_DU0_ODDF_DISP_CDE___5 = 858,\n\tFN_DU0_DISP___5 = 859,\n\tFN_DU0_CDE___5 = 860,\n\tFN_DU1_DR2_Y4_DATA0 = 861,\n\tFN_DU1_DR3_Y5_DATA1 = 862,\n\tFN_DU1_DR4_Y6_DATA2 = 863,\n\tFN_DU1_DR5_Y7_DATA3 = 864,\n\tFN_DU1_DR6_DATA4 = 865,\n\tFN_DU1_DR7_DATA5 = 866,\n\tFN_DU1_DG2_C6_DATA6 = 867,\n\tFN_DU1_DG3_C7_DATA7 = 868,\n\tFN_DU1_DG4_Y0_DATA8 = 869,\n\tFN_DU1_DG5_Y1_DATA9 = 870,\n\tFN_DU1_DG6_Y2_DATA10 = 871,\n\tFN_DU1_DG7_Y3_DATA11 = 872,\n\tFN_A20___6 = 873,\n\tFN_MOSI_IO0___3 = 874,\n\tFN_A21___6 = 875,\n\tFN_MISO_IO1___3 = 876,\n\tFN_A22___6 = 877,\n\tFN_IO2___3 = 878,\n\tFN_A23___6 = 879,\n\tFN_IO3___3 = 880,\n\tFN_A24___6 = 881,\n\tFN_SPCLK___3 = 882,\n\tFN_A25___6 = 883,\n\tFN_SSL___3 = 884,\n\tFN_VI2_CLK___3 = 885,\n\tFN_AVB_RX_CLK___4 = 886,\n\tFN_VI2_CLKENB___3 = 887,\n\tFN_AVB_RX_DV___4 = 888,\n\tFN_VI2_HSYNC_N___2 = 889,\n\tFN_AVB_RXD0___4 = 890,\n\tFN_VI2_VSYNC_N___2 = 891,\n\tFN_AVB_RXD1___4 = 892,\n\tFN_VI2_D0_C0 = 893,\n\tFN_AVB_RXD2___4 = 894,\n\tFN_VI2_D1_C1 = 895,\n\tFN_AVB_RXD3___4 = 896,\n\tFN_VI2_D2_C2 = 897,\n\tFN_AVB_RXD4___4 = 898,\n\tFN_VI2_D3_C3 = 899,\n\tFN_AVB_RXD5___4 = 900,\n\tFN_VI2_D4_C4 = 901,\n\tFN_AVB_RXD6___4 = 902,\n\tFN_VI2_D5_C5 = 903,\n\tFN_AVB_RXD7___4 = 904,\n\tFN_VI2_D6_C6 = 905,\n\tFN_AVB_RX_ER___4 = 906,\n\tFN_VI2_D7_C7 = 907,\n\tFN_AVB_COL___4 = 908,\n\tFN_VI2_D8_Y0 = 909,\n\tFN_AVB_TXD3___4 = 910,\n\tFN_VI2_D9_Y1 = 911,\n\tFN_AVB_TX_EN___4 = 912,\n\tFN_VI2_D10_Y2 = 913,\n\tFN_AVB_TXD0___4 = 914,\n\tFN_VI2_D11_Y3 = 915,\n\tFN_AVB_TXD1___4 = 916,\n\tFN_VI2_FIELD___3 = 917,\n\tFN_AVB_TXD2___4 = 918,\n\tFN_VI3_CLK___2 = 919,\n\tFN_AVB_TX_CLK___4 = 920,\n\tFN_VI3_CLKENB___2 = 921,\n\tFN_AVB_TXD4___4 = 922,\n\tFN_VI3_HSYNC_N = 923,\n\tFN_AVB_TXD5___4 = 924,\n\tFN_VI3_VSYNC_N = 925,\n\tFN_AVB_TXD6___4 = 926,\n\tFN_VI3_D0_C0 = 927,\n\tFN_AVB_TXD7___4 = 928,\n\tFN_VI3_D1_C1 = 929,\n\tFN_AVB_TX_ER___4 = 930,\n\tFN_VI3_D2_C2 = 931,\n\tFN_AVB_GTX_CLK___4 = 932,\n\tFN_VI3_D3_C3 = 933,\n\tFN_AVB_MDC___4 = 934,\n\tFN_VI3_D4_C4 = 935,\n\tFN_AVB_MDIO___4 = 936,\n\tFN_VI3_D5_C5 = 937,\n\tFN_AVB_LINK___4 = 938,\n\tFN_VI3_D6_C6 = 939,\n\tFN_AVB_MAGIC___4 = 940,\n\tFN_VI3_D7_C7 = 941,\n\tFN_AVB_PHY_INT___4 = 942,\n\tFN_VI3_D8_Y0 = 943,\n\tFN_AVB_CRS___4 = 944,\n\tFN_VI3_D9_Y1 = 945,\n\tFN_AVB_GTXREFCLK___4 = 946,\n\tFN_VI3_D11_Y3 = 947,\n\tFN_AVB_AVTP_MATCH = 948,\n\tFN_VI4_CLKENB = 949,\n\tFN_VI0_D12_G4_Y4 = 950,\n\tFN_VI4_HSYNC_N = 951,\n\tFN_VI0_D13_G5_Y5 = 952,\n\tFN_VI4_VSYNC_N = 953,\n\tFN_VI0_D14_G6_Y6 = 954,\n\tFN_RDR_CLKOUT = 955,\n\tFN_VI4_D0_C0 = 956,\n\tFN_VI0_D15_G7_Y7 = 957,\n\tFN_VI4_D1_C1 = 958,\n\tFN_VI0_D16_R0 = 959,\n\tFN_VI1_D12_G4_Y4 = 960,\n\tFN_VI4_D2_C2 = 961,\n\tFN_VI0_D17_R1 = 962,\n\tFN_VI1_D13_G5_Y5 = 963,\n\tFN_VI4_D3_C3 = 964,\n\tFN_VI0_D18_R2 = 965,\n\tFN_VI1_D14_G6_Y6 = 966,\n\tFN_VI4_D4_C4 = 967,\n\tFN_VI0_D19_R3 = 968,\n\tFN_VI1_D15_G7_Y7 = 969,\n\tFN_VI4_D5_C5 = 970,\n\tFN_VI0_D20_R4 = 971,\n\tFN_VI2_D12_Y4 = 972,\n\tFN_VI4_D6_C6 = 973,\n\tFN_VI0_D21_R5 = 974,\n\tFN_VI2_D13_Y5 = 975,\n\tFN_VI4_D7_C7 = 976,\n\tFN_VI0_D22_R6 = 977,\n\tFN_VI2_D14_Y6 = 978,\n\tFN_VI4_D8_Y0 = 979,\n\tFN_VI0_D23_R7 = 980,\n\tFN_VI2_D15_Y7 = 981,\n\tFN_VI4_D9_Y1 = 982,\n\tFN_VI3_D12_Y4 = 983,\n\tFN_VI4_D10_Y2 = 984,\n\tFN_VI3_D13_Y5 = 985,\n\tFN_VI4_D11_Y3 = 986,\n\tFN_VI3_D14_Y6 = 987,\n\tFN_VI4_FIELD = 988,\n\tFN_VI3_D15_Y7 = 989,\n\tFN_VI5_CLKENB = 990,\n\tFN_VI1_D12_G4_Y4_B = 991,\n\tFN_VI5_HSYNC_N = 992,\n\tFN_VI1_D13_G5_Y5_B = 993,\n\tFN_VI5_VSYNC_N = 994,\n\tFN_VI1_D14_G6_Y6_B = 995,\n\tFN_VI5_D0_C0 = 996,\n\tFN_VI1_D15_G7_Y7_B = 997,\n\tFN_VI5_D1_C1 = 998,\n\tFN_VI1_D16_R0 = 999,\n\tFN_VI5_D2_C2 = 1000,\n\tFN_VI1_D17_R1 = 1001,\n\tFN_VI5_D3_C3 = 1002,\n\tFN_VI1_D18_R2 = 1003,\n\tFN_VI5_D4_C4 = 1004,\n\tFN_VI1_D19_R3 = 1005,\n\tFN_VI5_D5_C5 = 1006,\n\tFN_VI1_D20_R4 = 1007,\n\tFN_VI5_D6_C6 = 1008,\n\tFN_VI1_D21_R5 = 1009,\n\tFN_VI5_D7_C7 = 1010,\n\tFN_VI1_D22_R6 = 1011,\n\tFN_VI5_D8_Y0 = 1012,\n\tFN_VI1_D23_R7 = 1013,\n\tFN_MSIOF0_SCK___3 = 1014,\n\tFN_HSCK0___5 = 1015,\n\tFN_MSIOF0_SYNC___3 = 1016,\n\tFN_HCTS0_N___3 = 1017,\n\tFN_MSIOF0_TXD___3 = 1018,\n\tFN_HTX0___3 = 1019,\n\tFN_MSIOF0_RXD___3 = 1020,\n\tFN_HRX0___3 = 1021,\n\tFN_MSIOF1_SCK___3 = 1022,\n\tFN_HSCK1___4 = 1023,\n\tFN_MSIOF1_SYNC___3 = 1024,\n\tFN_HRTS1_N___2 = 1025,\n\tFN_MSIOF1_TXD___3 = 1026,\n\tFN_HTX1___3 = 1027,\n\tFN_MSIOF1_RXD___3 = 1028,\n\tFN_HRX1___3 = 1029,\n\tFN_DRACK0___6 = 1030,\n\tFN_SCK2___2 = 1031,\n\tFN_DACK0___6 = 1032,\n\tFN_TX2___3 = 1033,\n\tFN_DREQ0_N___3 = 1034,\n\tFN_RX2___3 = 1035,\n\tFN_DACK1___5 = 1036,\n\tFN_SCK3___2 = 1037,\n\tFN_TX3___2 = 1038,\n\tFN_DREQ1_N___3 = 1039,\n\tFN_RX3___2 = 1040,\n\tFN_PWM0___4 = 1041,\n\tFN_TCLK1___5 = 1042,\n\tFN_FSO_CFE_0 = 1043,\n\tFN_PWM1___5 = 1044,\n\tFN_TCLK2___3 = 1045,\n\tFN_FSO_CFE_1 = 1046,\n\tFN_PWM2___5 = 1047,\n\tFN_TCLK3 = 1048,\n\tFN_FSO_TOE = 1049,\n\tFN_PWM3___5 = 1050,\n\tFN_PWM4___5 = 1051,\n\tFN_SSI_SCK34___6 = 1052,\n\tFN_TPU0TO0 = 1053,\n\tFN_SSI_WS34___6 = 1054,\n\tFN_TPU0TO1 = 1055,\n\tFN_SSI_SDATA3___6 = 1056,\n\tFN_TPU0TO2 = 1057,\n\tFN_SSI_SCK4___5 = 1058,\n\tFN_TPU0TO3 = 1059,\n\tFN_SSI_WS4___5 = 1060,\n\tFN_SSI_SDATA4___5 = 1061,\n\tFN_AUDIO_CLKOUT___4 = 1062,\n\tFN_AUDIO_CLKA___5 = 1063,\n\tFN_AUDIO_CLKB___5 = 1064,\n\tFN_SEL_VI1_0___2 = 1065,\n\tFN_SEL_VI1_1___2 = 1066,\n\tPINMUX_FUNCTION_END___10 = 1067,\n\tPINMUX_MARK_BEGIN___10 = 1068,\n\tDU1_DB2_C0_DATA12_MARK = 1069,\n\tDU1_DB3_C1_DATA13_MARK = 1070,\n\tDU1_DB4_C2_DATA14_MARK = 1071,\n\tDU1_DB5_C3_DATA15_MARK = 1072,\n\tDU1_DB6_C4_MARK = 1073,\n\tDU1_DB7_C5_MARK = 1074,\n\tDU1_EXHSYNC_DU1_HSYNC_MARK___6 = 1075,\n\tDU1_EXVSYNC_DU1_VSYNC_MARK___6 = 1076,\n\tDU1_EXODDF_DU1_ODDF_DISP_CDE_MARK___6 = 1077,\n\tDU1_DISP_MARK___6 = 1078,\n\tDU1_CDE_MARK___6 = 1079,\n\tD0_MARK___6 = 1080,\n\tD1_MARK___6 = 1081,\n\tD2_MARK___6 = 1082,\n\tD3_MARK___6 = 1083,\n\tD4_MARK___6 = 1084,\n\tD5_MARK___6 = 1085,\n\tD6_MARK___6 = 1086,\n\tD7_MARK___6 = 1087,\n\tD8_MARK___6 = 1088,\n\tD9_MARK___6 = 1089,\n\tD10_MARK___6 = 1090,\n\tD11_MARK___6 = 1091,\n\tD12_MARK___5 = 1092,\n\tD13_MARK___5 = 1093,\n\tD14_MARK___5 = 1094,\n\tD15_MARK___5 = 1095,\n\tA0_MARK___9 = 1096,\n\tA1_MARK___7 = 1097,\n\tA2_MARK___7 = 1098,\n\tA3_MARK___7 = 1099,\n\tA4_MARK___6 = 1100,\n\tA5_MARK___6 = 1101,\n\tA6_MARK___7 = 1102,\n\tA7_MARK___7 = 1103,\n\tA8_MARK___7 = 1104,\n\tA9_MARK___7 = 1105,\n\tA10_MARK___7 = 1106,\n\tA11_MARK___7 = 1107,\n\tA12_MARK___7 = 1108,\n\tA13_MARK___7 = 1109,\n\tA14_MARK___7 = 1110,\n\tA15_MARK___7 = 1111,\n\tA16_MARK___7 = 1112,\n\tA17_MARK___8 = 1113,\n\tA18_MARK___8 = 1114,\n\tA19_MARK___8 = 1115,\n\tCS1_N_A26_MARK___4 = 1116,\n\tEX_CS0_N_MARK___3 = 1117,\n\tEX_CS1_N_MARK___3 = 1118,\n\tEX_CS2_N_MARK___3 = 1119,\n\tEX_CS3_N_MARK___3 = 1120,\n\tEX_CS4_N_MARK___3 = 1121,\n\tEX_CS5_N_MARK___3 = 1122,\n\tBS_N_MARK___4 = 1123,\n\tRD_N_MARK___5 = 1124,\n\tRD_WR_N_MARK___4 = 1125,\n\tWE0_N_MARK___5 = 1126,\n\tWE1_N_MARK___5 = 1127,\n\tEX_WAIT0_MARK___5 = 1128,\n\tIRQ0_MARK___7 = 1129,\n\tIRQ1_MARK___7 = 1130,\n\tIRQ2_MARK___6 = 1131,\n\tIRQ3_MARK___6 = 1132,\n\tCS0_N_MARK___5 = 1133,\n\tVI0_CLK_MARK___6 = 1134,\n\tVI0_CLKENB_MARK___6 = 1135,\n\tVI0_HSYNC_N_MARK___4 = 1136,\n\tVI0_VSYNC_N_MARK___4 = 1137,\n\tVI0_D0_B0_C0_MARK = 1138,\n\tVI0_D1_B1_C1_MARK = 1139,\n\tVI0_D2_B2_C2_MARK = 1140,\n\tVI0_D3_B3_C3_MARK = 1141,\n\tVI0_D4_B4_C4_MARK = 1142,\n\tVI0_D5_B5_C5_MARK = 1143,\n\tVI0_D6_B6_C6_MARK = 1144,\n\tVI0_D7_B7_C7_MARK = 1145,\n\tVI0_D8_G0_Y0_MARK = 1146,\n\tVI0_D9_G1_Y1_MARK = 1147,\n\tVI0_D10_G2_Y2_MARK = 1148,\n\tVI0_D11_G3_Y3_MARK = 1149,\n\tVI0_FIELD_MARK___6 = 1150,\n\tVI1_CLK_MARK___6 = 1151,\n\tVI1_CLKENB_MARK___6 = 1152,\n\tVI1_HSYNC_N_MARK___4 = 1153,\n\tVI1_VSYNC_N_MARK___4 = 1154,\n\tVI1_D0_B0_C0_MARK = 1155,\n\tVI1_D1_B1_C1_MARK = 1156,\n\tVI1_D2_B2_C2_MARK = 1157,\n\tVI1_D3_B3_C3_MARK = 1158,\n\tVI1_D4_B4_C4_MARK = 1159,\n\tVI1_D5_B5_C5_MARK = 1160,\n\tVI1_D6_B6_C6_MARK = 1161,\n\tVI1_D7_B7_C7_MARK = 1162,\n\tVI1_D8_G0_Y0_MARK = 1163,\n\tVI1_D9_G1_Y1_MARK = 1164,\n\tVI1_D10_G2_Y2_MARK = 1165,\n\tVI1_D11_G3_Y3_MARK = 1166,\n\tVI1_FIELD_MARK___6 = 1167,\n\tVI3_D10_Y2_MARK = 1168,\n\tVI3_FIELD_MARK___2 = 1169,\n\tVI4_CLK_MARK = 1170,\n\tVI5_CLK_MARK = 1171,\n\tVI5_D9_Y1_MARK = 1172,\n\tVI5_D10_Y2_MARK = 1173,\n\tVI5_D11_Y3_MARK = 1174,\n\tVI5_FIELD_MARK = 1175,\n\tHRTS0_N_MARK___3 = 1176,\n\tHCTS1_N_MARK___2 = 1177,\n\tSCK0_MARK___3 = 1178,\n\tCTS0_N_MARK = 1179,\n\tRTS0_N_MARK = 1180,\n\tTX0_MARK___3 = 1181,\n\tRX0_MARK___3 = 1182,\n\tSCK1_MARK___2 = 1183,\n\tCTS1_N_MARK = 1184,\n\tRTS1_N_MARK = 1185,\n\tTX1_MARK___3 = 1186,\n\tRX1_MARK___3 = 1187,\n\tSCIF_CLK_MARK___5 = 1188,\n\tCAN0_TX_MARK___4 = 1189,\n\tCAN0_RX_MARK___4 = 1190,\n\tCAN_CLK_MARK___4 = 1191,\n\tCAN1_TX_MARK___4 = 1192,\n\tCAN1_RX_MARK___4 = 1193,\n\tSD0_CLK_MARK___6 = 1194,\n\tSD0_CMD_MARK___6 = 1195,\n\tSD0_DAT0_MARK___4 = 1196,\n\tSD0_DAT1_MARK___4 = 1197,\n\tSD0_DAT2_MARK___4 = 1198,\n\tSD0_DAT3_MARK___4 = 1199,\n\tSD0_CD_MARK___6 = 1200,\n\tSD0_WP_MARK___6 = 1201,\n\tADICLK_MARK___5 = 1202,\n\tADICS_SAMP_MARK___5 = 1203,\n\tADIDATA_MARK___5 = 1204,\n\tADICHS0_MARK___5 = 1205,\n\tADICHS1_MARK___5 = 1206,\n\tADICHS2_MARK___5 = 1207,\n\tAVS1_MARK___3 = 1208,\n\tAVS2_MARK___3 = 1209,\n\tDU0_DR0_DATA0_MARK = 1210,\n\tDU0_DR1_DATA1_MARK = 1211,\n\tDU0_DR2_Y4_DATA2_MARK = 1212,\n\tDU0_DR3_Y5_DATA3_MARK = 1213,\n\tDU0_DR4_Y6_DATA4_MARK = 1214,\n\tDU0_DR5_Y7_DATA5_MARK = 1215,\n\tDU0_DR6_Y8_DATA6_MARK = 1216,\n\tDU0_DR7_Y9_DATA7_MARK = 1217,\n\tDU0_DG0_DATA8_MARK = 1218,\n\tDU0_DG1_DATA9_MARK = 1219,\n\tDU0_DG2_C6_DATA10_MARK = 1220,\n\tDU0_DG3_C7_DATA11_MARK = 1221,\n\tDU0_DG4_Y0_DATA12_MARK = 1222,\n\tDU0_DG5_Y1_DATA13_MARK = 1223,\n\tDU0_DG6_Y2_DATA14_MARK = 1224,\n\tDU0_DG7_Y3_DATA15_MARK = 1225,\n\tDU0_DB0_MARK___6 = 1226,\n\tDU0_DB1_MARK___6 = 1227,\n\tDU0_DB2_C0_MARK = 1228,\n\tDU0_DB3_C1_MARK = 1229,\n\tDU0_DB4_C2_MARK = 1230,\n\tDU0_DB5_C3_MARK = 1231,\n\tDU0_DB6_C4_MARK = 1232,\n\tDU0_DB7_C5_MARK = 1233,\n\tDU0_EXHSYNC_DU0_HSYNC_MARK___5 = 1234,\n\tDU0_EXVSYNC_DU0_VSYNC_MARK___5 = 1235,\n\tDU0_EXODDF_DU0_ODDF_DISP_CDE_MARK___5 = 1236,\n\tDU0_DISP_MARK___5 = 1237,\n\tDU0_CDE_MARK___6 = 1238,\n\tDU1_DR2_Y4_DATA0_MARK = 1239,\n\tDU1_DR3_Y5_DATA1_MARK = 1240,\n\tDU1_DR4_Y6_DATA2_MARK = 1241,\n\tDU1_DR5_Y7_DATA3_MARK = 1242,\n\tDU1_DR6_DATA4_MARK = 1243,\n\tDU1_DR7_DATA5_MARK = 1244,\n\tDU1_DG2_C6_DATA6_MARK = 1245,\n\tDU1_DG3_C7_DATA7_MARK = 1246,\n\tDU1_DG4_Y0_DATA8_MARK = 1247,\n\tDU1_DG5_Y1_DATA9_MARK = 1248,\n\tDU1_DG6_Y2_DATA10_MARK = 1249,\n\tDU1_DG7_Y3_DATA11_MARK = 1250,\n\tA20_MARK___8 = 1251,\n\tMOSI_IO0_MARK___3 = 1252,\n\tA21_MARK___8 = 1253,\n\tMISO_IO1_MARK___3 = 1254,\n\tA22_MARK___8 = 1255,\n\tIO2_MARK___3 = 1256,\n\tA23_MARK___8 = 1257,\n\tIO3_MARK___3 = 1258,\n\tA24_MARK___8 = 1259,\n\tSPCLK_MARK___3 = 1260,\n\tA25_MARK___8 = 1261,\n\tSSL_MARK___3 = 1262,\n\tVI2_CLK_MARK___3 = 1263,\n\tAVB_RX_CLK_MARK___4 = 1264,\n\tVI2_CLKENB_MARK___3 = 1265,\n\tAVB_RX_DV_MARK___4 = 1266,\n\tVI2_HSYNC_N_MARK___2 = 1267,\n\tAVB_RXD0_MARK___4 = 1268,\n\tVI2_VSYNC_N_MARK___2 = 1269,\n\tAVB_RXD1_MARK___4 = 1270,\n\tVI2_D0_C0_MARK = 1271,\n\tAVB_RXD2_MARK___4 = 1272,\n\tVI2_D1_C1_MARK = 1273,\n\tAVB_TX_CLK_MARK___4 = 1274,\n\tVI2_D2_C2_MARK = 1275,\n\tAVB_RXD4_MARK___4 = 1276,\n\tVI2_D3_C3_MARK = 1277,\n\tAVB_RXD5_MARK___4 = 1278,\n\tVI2_D4_C4_MARK = 1279,\n\tAVB_RXD6_MARK___4 = 1280,\n\tVI2_D5_C5_MARK = 1281,\n\tAVB_RXD7_MARK___4 = 1282,\n\tVI2_D6_C6_MARK = 1283,\n\tAVB_RX_ER_MARK___4 = 1284,\n\tVI2_D7_C7_MARK = 1285,\n\tAVB_COL_MARK___4 = 1286,\n\tVI2_D8_Y0_MARK = 1287,\n\tAVB_RXD3_MARK___4 = 1288,\n\tVI2_D9_Y1_MARK = 1289,\n\tAVB_TX_EN_MARK___4 = 1290,\n\tVI2_D10_Y2_MARK = 1291,\n\tAVB_TXD0_MARK___4 = 1292,\n\tVI2_D11_Y3_MARK = 1293,\n\tAVB_TXD1_MARK___4 = 1294,\n\tVI2_FIELD_MARK___3 = 1295,\n\tAVB_TXD2_MARK___4 = 1296,\n\tVI3_CLK_MARK___2 = 1297,\n\tAVB_TXD3_MARK___4 = 1298,\n\tVI3_CLKENB_MARK___2 = 1299,\n\tAVB_TXD4_MARK___4 = 1300,\n\tVI3_HSYNC_N_MARK = 1301,\n\tAVB_TXD5_MARK___4 = 1302,\n\tVI3_VSYNC_N_MARK = 1303,\n\tAVB_TXD6_MARK___4 = 1304,\n\tVI3_D0_C0_MARK = 1305,\n\tAVB_TXD7_MARK___4 = 1306,\n\tVI3_D1_C1_MARK = 1307,\n\tAVB_TX_ER_MARK___4 = 1308,\n\tVI3_D2_C2_MARK = 1309,\n\tAVB_GTX_CLK_MARK___4 = 1310,\n\tVI3_D3_C3_MARK = 1311,\n\tAVB_MDC_MARK___4 = 1312,\n\tVI3_D4_C4_MARK = 1313,\n\tAVB_MDIO_MARK___4 = 1314,\n\tVI3_D5_C5_MARK = 1315,\n\tAVB_LINK_MARK___4 = 1316,\n\tVI3_D6_C6_MARK = 1317,\n\tAVB_MAGIC_MARK___4 = 1318,\n\tVI3_D7_C7_MARK = 1319,\n\tAVB_PHY_INT_MARK___4 = 1320,\n\tVI3_D8_Y0_MARK = 1321,\n\tAVB_CRS_MARK___4 = 1322,\n\tVI3_D9_Y1_MARK = 1323,\n\tAVB_GTXREFCLK_MARK___4 = 1324,\n\tVI3_D11_Y3_MARK = 1325,\n\tAVB_AVTP_MATCH_MARK = 1326,\n\tVI4_CLKENB_MARK = 1327,\n\tVI0_D12_G4_Y4_MARK = 1328,\n\tVI4_HSYNC_N_MARK = 1329,\n\tVI0_D13_G5_Y5_MARK = 1330,\n\tVI4_VSYNC_N_MARK = 1331,\n\tVI0_D14_G6_Y6_MARK = 1332,\n\tRDR_CLKOUT_MARK = 1333,\n\tVI4_D0_C0_MARK = 1334,\n\tVI0_D15_G7_Y7_MARK = 1335,\n\tVI4_D1_C1_MARK = 1336,\n\tVI0_D16_R0_MARK = 1337,\n\tVI1_D12_G4_Y4_MARK = 1338,\n\tVI4_D2_C2_MARK = 1339,\n\tVI0_D17_R1_MARK = 1340,\n\tVI1_D13_G5_Y5_MARK = 1341,\n\tVI4_D3_C3_MARK = 1342,\n\tVI0_D18_R2_MARK = 1343,\n\tVI1_D14_G6_Y6_MARK = 1344,\n\tVI4_D4_C4_MARK = 1345,\n\tVI0_D19_R3_MARK = 1346,\n\tVI1_D15_G7_Y7_MARK = 1347,\n\tVI4_D5_C5_MARK = 1348,\n\tVI0_D20_R4_MARK = 1349,\n\tVI2_D12_Y4_MARK = 1350,\n\tVI4_D6_C6_MARK = 1351,\n\tVI0_D21_R5_MARK = 1352,\n\tVI2_D13_Y5_MARK = 1353,\n\tVI4_D7_C7_MARK = 1354,\n\tVI0_D22_R6_MARK = 1355,\n\tVI2_D14_Y6_MARK = 1356,\n\tVI4_D8_Y0_MARK = 1357,\n\tVI0_D23_R7_MARK = 1358,\n\tVI2_D15_Y7_MARK = 1359,\n\tVI4_D9_Y1_MARK = 1360,\n\tVI3_D12_Y4_MARK = 1361,\n\tVI4_D10_Y2_MARK = 1362,\n\tVI3_D13_Y5_MARK = 1363,\n\tVI4_D11_Y3_MARK = 1364,\n\tVI3_D14_Y6_MARK = 1365,\n\tVI4_FIELD_MARK = 1366,\n\tVI3_D15_Y7_MARK = 1367,\n\tVI5_CLKENB_MARK = 1368,\n\tVI1_D12_G4_Y4_B_MARK = 1369,\n\tVI5_HSYNC_N_MARK = 1370,\n\tVI1_D13_G5_Y5_B_MARK = 1371,\n\tVI5_VSYNC_N_MARK = 1372,\n\tVI1_D14_G6_Y6_B_MARK = 1373,\n\tVI5_D0_C0_MARK = 1374,\n\tVI1_D15_G7_Y7_B_MARK = 1375,\n\tVI5_D1_C1_MARK = 1376,\n\tVI1_D16_R0_MARK = 1377,\n\tVI5_D2_C2_MARK = 1378,\n\tVI1_D17_R1_MARK = 1379,\n\tVI5_D3_C3_MARK = 1380,\n\tVI1_D18_R2_MARK = 1381,\n\tVI5_D4_C4_MARK = 1382,\n\tVI1_D19_R3_MARK = 1383,\n\tVI5_D5_C5_MARK = 1384,\n\tVI1_D20_R4_MARK = 1385,\n\tVI5_D6_C6_MARK = 1386,\n\tVI1_D21_R5_MARK = 1387,\n\tVI5_D7_C7_MARK = 1388,\n\tVI1_D22_R6_MARK = 1389,\n\tVI5_D8_Y0_MARK = 1390,\n\tVI1_D23_R7_MARK = 1391,\n\tMSIOF0_SCK_MARK___4 = 1392,\n\tHSCK0_MARK___5 = 1393,\n\tMSIOF0_SYNC_MARK___4 = 1394,\n\tHCTS0_N_MARK___3 = 1395,\n\tMSIOF0_TXD_MARK___6 = 1396,\n\tHTX0_MARK___3 = 1397,\n\tMSIOF0_RXD_MARK___6 = 1398,\n\tHRX0_MARK___3 = 1399,\n\tMSIOF1_SCK_MARK___4 = 1400,\n\tHSCK1_MARK___4 = 1401,\n\tMSIOF1_SYNC_MARK___4 = 1402,\n\tHRTS1_N_MARK___2 = 1403,\n\tMSIOF1_TXD_MARK___5 = 1404,\n\tHTX1_MARK___3 = 1405,\n\tMSIOF1_RXD_MARK___5 = 1406,\n\tHRX1_MARK___3 = 1407,\n\tDRACK0_MARK___6 = 1408,\n\tSCK2_MARK___2 = 1409,\n\tDACK0_MARK___8 = 1410,\n\tTX2_MARK___3 = 1411,\n\tDREQ0_N_MARK___3 = 1412,\n\tRX2_MARK___3 = 1413,\n\tDACK1_MARK___7 = 1414,\n\tSCK3_MARK___2 = 1415,\n\tTX3_MARK___2 = 1416,\n\tDREQ1_N_MARK___3 = 1417,\n\tRX3_MARK___2 = 1418,\n\tPWM0_MARK___5 = 1419,\n\tTCLK1_MARK___5 = 1420,\n\tFSO_CFE_0_MARK = 1421,\n\tPWM1_MARK___6 = 1422,\n\tTCLK2_MARK___3 = 1423,\n\tFSO_CFE_1_MARK = 1424,\n\tPWM2_MARK___5 = 1425,\n\tTCLK3_MARK = 1426,\n\tFSO_TOE_MARK = 1427,\n\tPWM3_MARK___5 = 1428,\n\tPWM4_MARK___5 = 1429,\n\tSSI_SCK34_MARK___6 = 1430,\n\tTPU0TO0_MARK___4 = 1431,\n\tSSI_WS34_MARK___6 = 1432,\n\tTPU0TO1_MARK___4 = 1433,\n\tSSI_SDATA3_MARK___6 = 1434,\n\tTPU0TO2_MARK___3 = 1435,\n\tSSI_SCK4_MARK___5 = 1436,\n\tTPU0TO3_MARK___4 = 1437,\n\tSSI_WS4_MARK___5 = 1438,\n\tSSI_SDATA4_MARK___5 = 1439,\n\tAUDIO_CLKOUT_MARK___4 = 1440,\n\tAUDIO_CLKA_MARK___5 = 1441,\n\tAUDIO_CLKB_MARK___5 = 1442,\n\tPINMUX_MARK_END___10 = 1443,\n};\n\nenum {\n\tPINMUX_RESERVED___11 = 0,\n\tPINMUX_DATA_BEGIN___11 = 1,\n\tGP_0_0_DATA___7 = 2,\n\tGP_0_1_DATA___7 = 3,\n\tGP_0_2_DATA___7 = 4,\n\tGP_0_3_DATA___7 = 5,\n\tGP_0_4_DATA___7 = 6,\n\tGP_0_5_DATA___7 = 7,\n\tGP_0_6_DATA___7 = 8,\n\tGP_0_7_DATA___7 = 9,\n\tGP_0_8_DATA___7 = 10,\n\tGP_0_9_DATA___7 = 11,\n\tGP_0_10_DATA___7 = 12,\n\tGP_0_11_DATA___7 = 13,\n\tGP_0_12_DATA___7 = 14,\n\tGP_0_13_DATA___7 = 15,\n\tGP_0_14_DATA___7 = 16,\n\tGP_0_15_DATA___7 = 17,\n\tGP_0_16_DATA___7 = 18,\n\tGP_0_17_DATA___7 = 19,\n\tGP_0_18_DATA___7 = 20,\n\tGP_0_19_DATA___7 = 21,\n\tGP_0_20_DATA___7 = 22,\n\tGP_0_21_DATA___7 = 23,\n\tGP_0_22_DATA___7 = 24,\n\tGP_0_23_DATA___6 = 25,\n\tGP_0_24_DATA___6 = 26,\n\tGP_0_25_DATA___6 = 27,\n\tGP_0_26_DATA___6 = 28,\n\tGP_0_27_DATA___6 = 29,\n\tGP_0_28_DATA___6 = 30,\n\tGP_0_29_DATA___5 = 31,\n\tGP_0_30_DATA___5 = 32,\n\tGP_0_31_DATA___5 = 33,\n\tGP_1_0_DATA___7 = 34,\n\tGP_1_1_DATA___7 = 35,\n\tGP_1_2_DATA___7 = 36,\n\tGP_1_3_DATA___7 = 37,\n\tGP_1_4_DATA___7 = 38,\n\tGP_1_5_DATA___7 = 39,\n\tGP_1_6_DATA___7 = 40,\n\tGP_1_7_DATA___7 = 41,\n\tGP_1_8_DATA___7 = 42,\n\tGP_1_9_DATA___7 = 43,\n\tGP_1_10_DATA___7 = 44,\n\tGP_1_11_DATA___7 = 45,\n\tGP_1_12_DATA___7 = 46,\n\tGP_1_13_DATA___7 = 47,\n\tGP_1_14_DATA___7 = 48,\n\tGP_1_15_DATA___7 = 49,\n\tGP_1_16_DATA___7 = 50,\n\tGP_1_17_DATA___7 = 51,\n\tGP_1_18_DATA___7 = 52,\n\tGP_1_19_DATA___7 = 53,\n\tGP_1_20_DATA___7 = 54,\n\tGP_1_21_DATA___7 = 55,\n\tGP_1_22_DATA___7 = 56,\n\tGP_1_23_DATA___5 = 57,\n\tGP_1_24_DATA___5 = 58,\n\tGP_1_25_DATA___5 = 59,\n\tGP_1_26_DATA___3 = 60,\n\tGP_1_27_DATA___3 = 61,\n\tGP_1_28_DATA___3 = 62,\n\tGP_1_29_DATA___3 = 63,\n\tGP_2_0_DATA___7 = 64,\n\tGP_2_1_DATA___7 = 65,\n\tGP_2_2_DATA___7 = 66,\n\tGP_2_3_DATA___7 = 67,\n\tGP_2_4_DATA___7 = 68,\n\tGP_2_5_DATA___7 = 69,\n\tGP_2_6_DATA___7 = 70,\n\tGP_2_7_DATA___7 = 71,\n\tGP_2_8_DATA___7 = 72,\n\tGP_2_9_DATA___7 = 73,\n\tGP_2_10_DATA___7 = 74,\n\tGP_2_11_DATA___7 = 75,\n\tGP_2_12_DATA___7 = 76,\n\tGP_2_13_DATA___7 = 77,\n\tGP_2_14_DATA___7 = 78,\n\tGP_2_15_DATA___7 = 79,\n\tGP_2_16_DATA___7 = 80,\n\tGP_2_17_DATA___7 = 81,\n\tGP_2_18_DATA___7 = 82,\n\tGP_2_19_DATA___7 = 83,\n\tGP_2_20_DATA___7 = 84,\n\tGP_2_21_DATA___7 = 85,\n\tGP_2_22_DATA___7 = 86,\n\tGP_2_23_DATA___7 = 87,\n\tGP_2_24_DATA___7 = 88,\n\tGP_2_25_DATA___7 = 89,\n\tGP_2_26_DATA___7 = 90,\n\tGP_2_27_DATA___7 = 91,\n\tGP_2_28_DATA___7 = 92,\n\tGP_2_29_DATA___7 = 93,\n\tGP_3_0_DATA___7 = 94,\n\tGP_3_1_DATA___7 = 95,\n\tGP_3_2_DATA___7 = 96,\n\tGP_3_3_DATA___7 = 97,\n\tGP_3_4_DATA___7 = 98,\n\tGP_3_5_DATA___7 = 99,\n\tGP_3_6_DATA___7 = 100,\n\tGP_3_7_DATA___7 = 101,\n\tGP_3_8_DATA___7 = 102,\n\tGP_3_9_DATA___7 = 103,\n\tGP_3_10_DATA___7 = 104,\n\tGP_3_11_DATA___7 = 105,\n\tGP_3_12_DATA___7 = 106,\n\tGP_3_13_DATA___7 = 107,\n\tGP_3_14_DATA___7 = 108,\n\tGP_3_15_DATA___7 = 109,\n\tGP_3_16_DATA___7 = 110,\n\tGP_3_17_DATA___6 = 111,\n\tGP_3_18_DATA___6 = 112,\n\tGP_3_19_DATA___6 = 113,\n\tGP_3_20_DATA___6 = 114,\n\tGP_3_21_DATA___6 = 115,\n\tGP_3_22_DATA___6 = 116,\n\tGP_3_23_DATA___6 = 117,\n\tGP_3_24_DATA___6 = 118,\n\tGP_3_25_DATA___6 = 119,\n\tGP_3_26_DATA___6 = 120,\n\tGP_3_27_DATA___7 = 121,\n\tGP_3_28_DATA___6 = 122,\n\tGP_3_29_DATA___6 = 123,\n\tGP_3_30_DATA___5 = 124,\n\tGP_3_31_DATA___5 = 125,\n\tGP_4_0_DATA___7 = 126,\n\tGP_4_1_DATA___7 = 127,\n\tGP_4_2_DATA___7 = 128,\n\tGP_4_3_DATA___7 = 129,\n\tGP_4_4_DATA___7 = 130,\n\tGP_4_5_DATA___7 = 131,\n\tGP_4_6_DATA___7 = 132,\n\tGP_4_7_DATA___7 = 133,\n\tGP_4_8_DATA___7 = 134,\n\tGP_4_9_DATA___7 = 135,\n\tGP_4_10_DATA___7 = 136,\n\tGP_4_11_DATA___7 = 137,\n\tGP_4_12_DATA___7 = 138,\n\tGP_4_13_DATA___7 = 139,\n\tGP_4_14_DATA___7 = 140,\n\tGP_4_15_DATA___7 = 141,\n\tGP_4_16_DATA___7 = 142,\n\tGP_4_17_DATA___6 = 143,\n\tGP_4_18_DATA___6 = 144,\n\tGP_4_19_DATA___6 = 145,\n\tGP_4_20_DATA___6 = 146,\n\tGP_4_21_DATA___6 = 147,\n\tGP_4_22_DATA___6 = 148,\n\tGP_4_23_DATA___6 = 149,\n\tGP_4_24_DATA___6 = 150,\n\tGP_4_25_DATA___6 = 151,\n\tGP_4_26_DATA___5 = 152,\n\tGP_4_27_DATA___4 = 153,\n\tGP_4_28_DATA___4 = 154,\n\tGP_4_29_DATA___4 = 155,\n\tGP_4_30_DATA___4 = 156,\n\tGP_4_31_DATA___4 = 157,\n\tGP_5_0_DATA___6 = 158,\n\tGP_5_1_DATA___6 = 159,\n\tGP_5_2_DATA___6 = 160,\n\tGP_5_3_DATA___6 = 161,\n\tGP_5_4_DATA___6 = 162,\n\tGP_5_5_DATA___6 = 163,\n\tGP_5_6_DATA___6 = 164,\n\tGP_5_7_DATA___6 = 165,\n\tGP_5_8_DATA___6 = 166,\n\tGP_5_9_DATA___6 = 167,\n\tGP_5_10_DATA___6 = 168,\n\tGP_5_11_DATA___6 = 169,\n\tGP_5_12_DATA___6 = 170,\n\tGP_5_13_DATA___6 = 171,\n\tGP_5_14_DATA___6 = 172,\n\tGP_5_15_DATA___6 = 173,\n\tGP_5_16_DATA___6 = 174,\n\tGP_5_17_DATA___5 = 175,\n\tGP_5_18_DATA___5 = 176,\n\tGP_5_19_DATA___5 = 177,\n\tGP_5_20_DATA___5 = 178,\n\tGP_5_21_DATA___5 = 179,\n\tGP_5_22_DATA___5 = 180,\n\tGP_5_23_DATA___5 = 181,\n\tGP_5_24_DATA___5 = 182,\n\tGP_5_25_DATA___5 = 183,\n\tGP_5_26_DATA___5 = 184,\n\tGP_5_27_DATA___5 = 185,\n\tGP_5_28_DATA___4 = 186,\n\tGP_5_29_DATA___4 = 187,\n\tGP_5_30_DATA___4 = 188,\n\tGP_5_31_DATA___4 = 189,\n\tPINMUX_DATA_END___11 = 190,\n\tPINMUX_FUNCTION_BEGIN___11 = 191,\n\tGP_0_0_FN___7 = 192,\n\tGP_0_1_FN___7 = 193,\n\tGP_0_2_FN___7 = 194,\n\tGP_0_3_FN___7 = 195,\n\tGP_0_4_FN___7 = 196,\n\tGP_0_5_FN___7 = 197,\n\tGP_0_6_FN___7 = 198,\n\tGP_0_7_FN___7 = 199,\n\tGP_0_8_FN___7 = 200,\n\tGP_0_9_FN___7 = 201,\n\tGP_0_10_FN___7 = 202,\n\tGP_0_11_FN___7 = 203,\n\tGP_0_12_FN___7 = 204,\n\tGP_0_13_FN___7 = 205,\n\tGP_0_14_FN___7 = 206,\n\tGP_0_15_FN___7 = 207,\n\tGP_0_16_FN___7 = 208,\n\tGP_0_17_FN___7 = 209,\n\tGP_0_18_FN___7 = 210,\n\tGP_0_19_FN___7 = 211,\n\tGP_0_20_FN___7 = 212,\n\tGP_0_21_FN___7 = 213,\n\tGP_0_22_FN___7 = 214,\n\tGP_0_23_FN___6 = 215,\n\tGP_0_24_FN___6 = 216,\n\tGP_0_25_FN___6 = 217,\n\tGP_0_26_FN___6 = 218,\n\tGP_0_27_FN___6 = 219,\n\tGP_0_28_FN___6 = 220,\n\tGP_0_29_FN___5 = 221,\n\tGP_0_30_FN___5 = 222,\n\tGP_0_31_FN___5 = 223,\n\tGP_1_0_FN___7 = 224,\n\tGP_1_1_FN___7 = 225,\n\tGP_1_2_FN___7 = 226,\n\tGP_1_3_FN___7 = 227,\n\tGP_1_4_FN___7 = 228,\n\tGP_1_5_FN___7 = 229,\n\tGP_1_6_FN___7 = 230,\n\tGP_1_7_FN___7 = 231,\n\tGP_1_8_FN___7 = 232,\n\tGP_1_9_FN___7 = 233,\n\tGP_1_10_FN___7 = 234,\n\tGP_1_11_FN___7 = 235,\n\tGP_1_12_FN___7 = 236,\n\tGP_1_13_FN___7 = 237,\n\tGP_1_14_FN___7 = 238,\n\tGP_1_15_FN___7 = 239,\n\tGP_1_16_FN___7 = 240,\n\tGP_1_17_FN___7 = 241,\n\tGP_1_18_FN___7 = 242,\n\tGP_1_19_FN___7 = 243,\n\tGP_1_20_FN___7 = 244,\n\tGP_1_21_FN___7 = 245,\n\tGP_1_22_FN___7 = 246,\n\tGP_1_23_FN___5 = 247,\n\tGP_1_24_FN___5 = 248,\n\tGP_1_25_FN___5 = 249,\n\tGP_1_26_FN___3 = 250,\n\tGP_1_27_FN___3 = 251,\n\tGP_1_28_FN___3 = 252,\n\tGP_1_29_FN___3 = 253,\n\tGP_2_0_FN___7 = 254,\n\tGP_2_1_FN___7 = 255,\n\tGP_2_2_FN___7 = 256,\n\tGP_2_3_FN___7 = 257,\n\tGP_2_4_FN___7 = 258,\n\tGP_2_5_FN___7 = 259,\n\tGP_2_6_FN___7 = 260,\n\tGP_2_7_FN___7 = 261,\n\tGP_2_8_FN___7 = 262,\n\tGP_2_9_FN___7 = 263,\n\tGP_2_10_FN___7 = 264,\n\tGP_2_11_FN___7 = 265,\n\tGP_2_12_FN___7 = 266,\n\tGP_2_13_FN___7 = 267,\n\tGP_2_14_FN___7 = 268,\n\tGP_2_15_FN___7 = 269,\n\tGP_2_16_FN___7 = 270,\n\tGP_2_17_FN___7 = 271,\n\tGP_2_18_FN___7 = 272,\n\tGP_2_19_FN___7 = 273,\n\tGP_2_20_FN___7 = 274,\n\tGP_2_21_FN___7 = 275,\n\tGP_2_22_FN___7 = 276,\n\tGP_2_23_FN___7 = 277,\n\tGP_2_24_FN___7 = 278,\n\tGP_2_25_FN___7 = 279,\n\tGP_2_26_FN___7 = 280,\n\tGP_2_27_FN___7 = 281,\n\tGP_2_28_FN___7 = 282,\n\tGP_2_29_FN___7 = 283,\n\tGP_3_0_FN___7 = 284,\n\tGP_3_1_FN___7 = 285,\n\tGP_3_2_FN___7 = 286,\n\tGP_3_3_FN___7 = 287,\n\tGP_3_4_FN___7 = 288,\n\tGP_3_5_FN___7 = 289,\n\tGP_3_6_FN___7 = 290,\n\tGP_3_7_FN___7 = 291,\n\tGP_3_8_FN___7 = 292,\n\tGP_3_9_FN___7 = 293,\n\tGP_3_10_FN___7 = 294,\n\tGP_3_11_FN___7 = 295,\n\tGP_3_12_FN___7 = 296,\n\tGP_3_13_FN___7 = 297,\n\tGP_3_14_FN___7 = 298,\n\tGP_3_15_FN___7 = 299,\n\tGP_3_16_FN___7 = 300,\n\tGP_3_17_FN___6 = 301,\n\tGP_3_18_FN___6 = 302,\n\tGP_3_19_FN___6 = 303,\n\tGP_3_20_FN___6 = 304,\n\tGP_3_21_FN___6 = 305,\n\tGP_3_22_FN___6 = 306,\n\tGP_3_23_FN___6 = 307,\n\tGP_3_24_FN___6 = 308,\n\tGP_3_25_FN___6 = 309,\n\tGP_3_26_FN___6 = 310,\n\tGP_3_27_FN___7 = 311,\n\tGP_3_28_FN___6 = 312,\n\tGP_3_29_FN___6 = 313,\n\tGP_3_30_FN___5 = 314,\n\tGP_3_31_FN___5 = 315,\n\tGP_4_0_FN___7 = 316,\n\tGP_4_1_FN___7 = 317,\n\tGP_4_2_FN___7 = 318,\n\tGP_4_3_FN___7 = 319,\n\tGP_4_4_FN___7 = 320,\n\tGP_4_5_FN___7 = 321,\n\tGP_4_6_FN___7 = 322,\n\tGP_4_7_FN___7 = 323,\n\tGP_4_8_FN___7 = 324,\n\tGP_4_9_FN___7 = 325,\n\tGP_4_10_FN___7 = 326,\n\tGP_4_11_FN___7 = 327,\n\tGP_4_12_FN___7 = 328,\n\tGP_4_13_FN___7 = 329,\n\tGP_4_14_FN___7 = 330,\n\tGP_4_15_FN___7 = 331,\n\tGP_4_16_FN___7 = 332,\n\tGP_4_17_FN___6 = 333,\n\tGP_4_18_FN___6 = 334,\n\tGP_4_19_FN___6 = 335,\n\tGP_4_20_FN___6 = 336,\n\tGP_4_21_FN___6 = 337,\n\tGP_4_22_FN___6 = 338,\n\tGP_4_23_FN___6 = 339,\n\tGP_4_24_FN___6 = 340,\n\tGP_4_25_FN___6 = 341,\n\tGP_4_26_FN___5 = 342,\n\tGP_4_27_FN___4 = 343,\n\tGP_4_28_FN___4 = 344,\n\tGP_4_29_FN___4 = 345,\n\tGP_4_30_FN___4 = 346,\n\tGP_4_31_FN___4 = 347,\n\tGP_5_0_FN___6 = 348,\n\tGP_5_1_FN___6 = 349,\n\tGP_5_2_FN___6 = 350,\n\tGP_5_3_FN___6 = 351,\n\tGP_5_4_FN___6 = 352,\n\tGP_5_5_FN___6 = 353,\n\tGP_5_6_FN___6 = 354,\n\tGP_5_7_FN___6 = 355,\n\tGP_5_8_FN___6 = 356,\n\tGP_5_9_FN___6 = 357,\n\tGP_5_10_FN___6 = 358,\n\tGP_5_11_FN___6 = 359,\n\tGP_5_12_FN___6 = 360,\n\tGP_5_13_FN___6 = 361,\n\tGP_5_14_FN___6 = 362,\n\tGP_5_15_FN___6 = 363,\n\tGP_5_16_FN___6 = 364,\n\tGP_5_17_FN___5 = 365,\n\tGP_5_18_FN___5 = 366,\n\tGP_5_19_FN___5 = 367,\n\tGP_5_20_FN___5 = 368,\n\tGP_5_21_FN___5 = 369,\n\tGP_5_22_FN___5 = 370,\n\tGP_5_23_FN___5 = 371,\n\tGP_5_24_FN___5 = 372,\n\tGP_5_25_FN___5 = 373,\n\tGP_5_26_FN___5 = 374,\n\tGP_5_27_FN___5 = 375,\n\tGP_5_28_FN___4 = 376,\n\tGP_5_29_FN___4 = 377,\n\tGP_5_30_FN___4 = 378,\n\tGP_5_31_FN___4 = 379,\n\tFN_IP0_2_0___2 = 380,\n\tFN_IP0_5_3___2 = 381,\n\tFN_IP0_8_6 = 382,\n\tFN_IP0_11_9 = 383,\n\tFN_IP0_15_12___2 = 384,\n\tFN_IP0_19_16___2 = 385,\n\tFN_IP0_22_20 = 386,\n\tFN_IP0_26_23 = 387,\n\tFN_IP0_30_27 = 388,\n\tFN_IP1_3_0___2 = 389,\n\tFN_IP1_7_4___2 = 390,\n\tFN_IP1_11_8___2 = 391,\n\tFN_IP1_14_12 = 392,\n\tFN_IP1_17_15___2 = 393,\n\tFN_IP1_21_18 = 394,\n\tFN_IP1_25_22 = 395,\n\tFN_IP1_27_26 = 396,\n\tFN_IP1_29_28___3 = 397,\n\tFN_IP2_2_0___3 = 398,\n\tFN_IP2_5_3___2 = 399,\n\tFN_IP2_8_6___2 = 400,\n\tFN_IP2_11_9___2 = 401,\n\tFN_IP2_14_12 = 402,\n\tFN_IP2_17_15 = 403,\n\tFN_IP2_21_18 = 404,\n\tFN_IP2_25_22 = 405,\n\tFN_IP2_28_26 = 406,\n\tFN_IP3_3_0___2 = 407,\n\tFN_IP3_7_4___2 = 408,\n\tFN_IP3_11_8___2 = 409,\n\tFN_IP3_14_12___2 = 410,\n\tFN_IP3_17_15___2 = 411,\n\tFN_IP3_19_18___2 = 412,\n\tFN_IP3_22_20 = 413,\n\tFN_IP3_25_23 = 414,\n\tFN_IP3_28_26 = 415,\n\tFN_IP3_31_29___2 = 416,\n\tFN_IP4_2_0 = 417,\n\tFN_IP4_5_3 = 418,\n\tFN_IP4_8_6 = 419,\n\tFN_IP4_11_9 = 420,\n\tFN_IP4_14_12 = 421,\n\tFN_IP4_17_15 = 422,\n\tFN_IP4_20_18 = 423,\n\tFN_IP4_23_21 = 424,\n\tFN_IP4_26_24 = 425,\n\tFN_IP4_29_27 = 426,\n\tFN_IP5_2_0___3 = 427,\n\tFN_IP5_5_3___2 = 428,\n\tFN_IP5_9_6 = 429,\n\tFN_IP5_12_10 = 430,\n\tFN_IP5_14_13___3 = 431,\n\tFN_IP5_17_15___2 = 432,\n\tFN_IP5_20_18___2 = 433,\n\tFN_IP5_23_21___2 = 434,\n\tFN_IP5_26_24 = 435,\n\tFN_IP5_29_27 = 436,\n\tFN_IP6_2_0___2 = 437,\n\tFN_IP6_5_3___2 = 438,\n\tFN_IP6_8_6 = 439,\n\tFN_IP6_10_9 = 440,\n\tFN_IP6_13_11 = 441,\n\tFN_IP7_28_27___2 = 442,\n\tFN_IP7_30_29___2 = 443,\n\tFN_IP8_1_0 = 444,\n\tFN_IP8_3_2 = 445,\n\tFN_IP8_5_4 = 446,\n\tFN_IP8_7_6 = 447,\n\tFN_IP8_9_8 = 448,\n\tFN_IP8_11_10 = 449,\n\tFN_IP8_13_12 = 450,\n\tFN_IP8_15_14___2 = 451,\n\tFN_IP8_17_16___2 = 452,\n\tFN_IP8_19_18 = 453,\n\tFN_IP8_21_20 = 454,\n\tFN_IP8_23_22___2 = 455,\n\tFN_IP8_25_24___2 = 456,\n\tFN_IP8_26 = 457,\n\tFN_IP8_27 = 458,\n\tFN_VI1_DATA7_VI1_B7___2 = 459,\n\tFN_IP6_16_14 = 460,\n\tFN_IP6_19_17___2 = 461,\n\tFN_IP6_22_20___3 = 462,\n\tFN_IP6_25_23___2 = 463,\n\tFN_IP6_28_26___2 = 464,\n\tFN_IP6_31_29___2 = 465,\n\tFN_IP7_2_0___3 = 466,\n\tFN_IP7_5_3___3 = 467,\n\tFN_IP7_7_6 = 468,\n\tFN_IP7_9_8___2 = 469,\n\tFN_IP7_12_10___2 = 470,\n\tFN_IP7_15_13 = 471,\n\tFN_IP8_28 = 472,\n\tFN_IP8_30_29 = 473,\n\tFN_IP9_1_0___2 = 474,\n\tFN_IP9_3_2___2 = 475,\n\tFN_IP9_5_4 = 476,\n\tFN_IP9_7_6 = 477,\n\tFN_IP9_11_8___2 = 478,\n\tFN_IP9_15_12___2 = 479,\n\tFN_IP9_17_16 = 480,\n\tFN_IP9_19_18 = 481,\n\tFN_IP9_21_20 = 482,\n\tFN_IP9_23_22___2 = 483,\n\tFN_IP9_25_24___2 = 484,\n\tFN_IP9_27_26___2 = 485,\n\tFN_IP9_31_28___2 = 486,\n\tFN_IP10_3_0___2 = 487,\n\tFN_IP10_6_4 = 488,\n\tFN_IP10_10_7 = 489,\n\tFN_IP10_14_11 = 490,\n\tFN_IP10_18_15 = 491,\n\tFN_IP10_22_19 = 492,\n\tFN_IP10_25_23 = 493,\n\tFN_IP10_29_26 = 494,\n\tFN_IP11_3_0___2 = 495,\n\tFN_IP11_4 = 496,\n\tFN_IP11_6_5 = 497,\n\tFN_IP11_8_7 = 498,\n\tFN_IP11_10_9 = 499,\n\tFN_IP11_12_11 = 500,\n\tFN_IP11_14_13 = 501,\n\tFN_IP11_17_15___2 = 502,\n\tFN_IP11_21_18 = 503,\n\tFN_IP11_23_22 = 504,\n\tFN_IP11_26_24___3 = 505,\n\tFN_IP11_29_27___3 = 506,\n\tFN_IP11_31_30___2 = 507,\n\tFN_IP12_1_0___2 = 508,\n\tFN_IP12_3_2___2 = 509,\n\tFN_IP12_5_4 = 510,\n\tFN_IP12_7_6 = 511,\n\tFN_IP12_10_8 = 512,\n\tFN_IP12_13_11 = 513,\n\tFN_IP12_16_14 = 514,\n\tFN_IP12_19_17 = 515,\n\tFN_IP12_22_20 = 516,\n\tFN_IP12_24_23 = 517,\n\tFN_IP12_27_25 = 518,\n\tFN_IP12_30_28 = 519,\n\tFN_IP13_2_0___3 = 520,\n\tFN_IP13_6_3 = 521,\n\tFN_IP13_9_7___2 = 522,\n\tFN_IP13_12_10 = 523,\n\tFN_IP13_15_13 = 524,\n\tFN_IP13_18_16___2 = 525,\n\tFN_IP13_22_19 = 526,\n\tFN_IP13_25_23 = 527,\n\tFN_IP13_28_26 = 528,\n\tFN_IP13_30_29 = 529,\n\tFN_IP14_2_0 = 530,\n\tFN_IP14_5_3 = 531,\n\tFN_IP14_8_6 = 532,\n\tFN_IP14_11_9 = 533,\n\tFN_IP14_15_12___2 = 534,\n\tFN_IP14_18_16 = 535,\n\tFN_IP14_21_19 = 536,\n\tFN_IP14_24_22 = 537,\n\tFN_IP14_27_25 = 538,\n\tFN_IP14_30_28 = 539,\n\tFN_IP15_2_0 = 540,\n\tFN_IP15_5_3 = 541,\n\tFN_IP15_8_6___2 = 542,\n\tFN_IP15_11_9___2 = 543,\n\tFN_IP15_13_12 = 544,\n\tFN_IP15_15_14 = 545,\n\tFN_IP15_17_16 = 546,\n\tFN_IP15_19_18 = 547,\n\tFN_IP15_22_20 = 548,\n\tFN_IP15_25_23 = 549,\n\tFN_IP15_27_26 = 550,\n\tFN_IP15_29_28 = 551,\n\tFN_IP16_2_0___2 = 552,\n\tFN_IP16_5_3___2 = 553,\n\tFN_USB0_PWEN___4 = 554,\n\tFN_USB0_OVC_VBUS = 555,\n\tFN_IP16_6 = 556,\n\tFN_IP16_7 = 557,\n\tFN_USB2_PWEN = 558,\n\tFN_USB2_OVC = 559,\n\tFN_AVS1___4 = 560,\n\tFN_AVS2___4 = 561,\n\tFN_DU_DOTCLKIN0 = 562,\n\tFN_IP7_26_25___2 = 563,\n\tFN_DU_DOTCLKIN2 = 564,\n\tFN_IP7_18_16 = 565,\n\tFN_IP7_21_19 = 566,\n\tFN_IP7_24_22___2 = 567,\n\tFN_D0___6 = 568,\n\tFN_MSIOF3_SCK_B = 569,\n\tFN_VI3_DATA0___2 = 570,\n\tFN_VI0_G4___6 = 571,\n\tFN_VI0_G4_B = 572,\n\tFN_D1___6 = 573,\n\tFN_MSIOF3_SYNC_B = 574,\n\tFN_VI3_DATA1___2 = 575,\n\tFN_VI0_G5___6 = 576,\n\tFN_VI0_G5_B = 577,\n\tFN_D2___6 = 578,\n\tFN_MSIOF3_RXD_B = 579,\n\tFN_VI3_DATA2___2 = 580,\n\tFN_VI0_G6___5 = 581,\n\tFN_VI0_G6_B = 582,\n\tFN_D3___6 = 583,\n\tFN_MSIOF3_TXD_B = 584,\n\tFN_VI3_DATA3___2 = 585,\n\tFN_VI0_G7___5 = 586,\n\tFN_VI0_G7_B = 587,\n\tFN_D4___6 = 588,\n\tFN_SCIFB1_RXD_F = 589,\n\tFN_SCIFB0_RXD_C___2 = 590,\n\tFN_VI3_DATA4___2 = 591,\n\tFN_VI0_R0___5 = 592,\n\tFN_VI0_R0_B___2 = 593,\n\tFN_RX0_B___5 = 594,\n\tFN_D5___6 = 595,\n\tFN_SCIFB1_TXD_F = 596,\n\tFN_SCIFB0_TXD_C___2 = 597,\n\tFN_VI3_DATA5___2 = 598,\n\tFN_VI0_R1___5 = 599,\n\tFN_VI0_R1_B___2 = 600,\n\tFN_TX0_B___5 = 601,\n\tFN_D6___6 = 602,\n\tFN_IIC2_SCL_C = 603,\n\tFN_VI3_DATA6___2 = 604,\n\tFN_VI0_R2___5 = 605,\n\tFN_VI0_R2_B___2 = 606,\n\tFN_I2C2_SCL_C___3 = 607,\n\tFN_D7___6 = 608,\n\tFN_AD_DI_B = 609,\n\tFN_IIC2_SDA_C = 610,\n\tFN_VI3_DATA7___2 = 611,\n\tFN_VI0_R3___5 = 612,\n\tFN_VI0_R3_B___2 = 613,\n\tFN_I2C2_SDA_C___3 = 614,\n\tFN_TCLK1___6 = 615,\n\tFN_D8___6 = 616,\n\tFN_SCIFA1_SCK_C___2 = 617,\n\tFN_AVB_TXD0___5 = 618,\n\tFN_VI0_G0___5 = 619,\n\tFN_VI0_G0_B = 620,\n\tFN_VI2_DATA0_VI2_B0___2 = 621,\n\tFN_D9___6 = 622,\n\tFN_SCIFA1_RXD_C___3 = 623,\n\tFN_AVB_TXD1___5 = 624,\n\tFN_VI0_G1___5 = 625,\n\tFN_VI0_G1_B = 626,\n\tFN_VI2_DATA1_VI2_B1___2 = 627,\n\tFN_D10___6 = 628,\n\tFN_SCIFA1_TXD_C___3 = 629,\n\tFN_AVB_TXD2___5 = 630,\n\tFN_VI0_G2___6 = 631,\n\tFN_VI0_G2_B = 632,\n\tFN_VI2_DATA2_VI2_B2___2 = 633,\n\tFN_D11___6 = 634,\n\tFN_SCIFA1_CTS_N_C = 635,\n\tFN_AVB_TXD3___5 = 636,\n\tFN_VI0_G3___6 = 637,\n\tFN_VI0_G3_B = 638,\n\tFN_VI2_DATA3_VI2_B3___2 = 639,\n\tFN_D12___5 = 640,\n\tFN_SCIFA1_RTS_N_C = 641,\n\tFN_AVB_TXD4___5 = 642,\n\tFN_VI0_HSYNC_N___5 = 643,\n\tFN_VI0_HSYNC_N_B = 644,\n\tFN_VI2_DATA4_VI2_B4___2 = 645,\n\tFN_D13___5 = 646,\n\tFN_AVB_TXD5___5 = 647,\n\tFN_VI0_VSYNC_N___5 = 648,\n\tFN_VI0_VSYNC_N_B = 649,\n\tFN_VI2_DATA5_VI2_B5___2 = 650,\n\tFN_D14___5 = 651,\n\tFN_SCIFB1_RXD_C___2 = 652,\n\tFN_AVB_TXD6___5 = 653,\n\tFN_RX1_B___5 = 654,\n\tFN_VI0_CLKENB___7 = 655,\n\tFN_VI0_CLKENB_B = 656,\n\tFN_VI2_DATA6_VI2_B6___2 = 657,\n\tFN_D15___5 = 658,\n\tFN_SCIFB1_TXD_C___2 = 659,\n\tFN_AVB_TXD7___5 = 660,\n\tFN_TX1_B___5 = 661,\n\tFN_VI0_FIELD___7 = 662,\n\tFN_VI0_FIELD_B = 663,\n\tFN_VI2_DATA7_VI2_B7___2 = 664,\n\tFN_A0___7 = 665,\n\tFN_PWM3___6 = 666,\n\tFN_A1___7 = 667,\n\tFN_PWM4___6 = 668,\n\tFN_A2___7 = 669,\n\tFN_PWM5___5 = 670,\n\tFN_MSIOF1_SS1_B___3 = 671,\n\tFN_A3___7 = 672,\n\tFN_PWM6___5 = 673,\n\tFN_MSIOF1_SS2_B___3 = 674,\n\tFN_A4___7 = 675,\n\tFN_MSIOF1_TXD_B___4 = 676,\n\tFN_TPU0TO0___2 = 677,\n\tFN_A5___7 = 678,\n\tFN_SCIFA1_TXD_B___3 = 679,\n\tFN_TPU0TO1___2 = 680,\n\tFN_A6___7 = 681,\n\tFN_SCIFA1_RTS_N_B = 682,\n\tFN_TPU0TO2___2 = 683,\n\tFN_A7___7 = 684,\n\tFN_SCIFA1_SCK_B___3 = 685,\n\tFN_AUDIO_CLKOUT_B___5 = 686,\n\tFN_TPU0TO3___2 = 687,\n\tFN_A8___7 = 688,\n\tFN_SCIFA1_RXD_B___3 = 689,\n\tFN_SSI_SCK5_B___3 = 690,\n\tFN_VI0_R4___5 = 691,\n\tFN_VI0_R4_B___2 = 692,\n\tFN_SCIFB2_RXD_C___2 = 693,\n\tFN_RX2_B___5 = 694,\n\tFN_VI2_DATA0_VI2_B0_B = 695,\n\tFN_A9___7 = 696,\n\tFN_SCIFA1_CTS_N_B = 697,\n\tFN_SSI_WS5_B___3 = 698,\n\tFN_VI0_R5___5 = 699,\n\tFN_VI0_R5_B___2 = 700,\n\tFN_SCIFB2_TXD_C___2 = 701,\n\tFN_TX2_B___5 = 702,\n\tFN_VI2_DATA1_VI2_B1_B = 703,\n\tFN_A10___7 = 704,\n\tFN_SSI_SDATA5_B___3 = 705,\n\tFN_MSIOF2_SYNC___3 = 706,\n\tFN_VI0_R6___5 = 707,\n\tFN_VI0_R6_B = 708,\n\tFN_VI2_DATA2_VI2_B2_B = 709,\n\tFN_A11___7 = 710,\n\tFN_SCIFB2_CTS_N_B___2 = 711,\n\tFN_MSIOF2_SCK___3 = 712,\n\tFN_VI1_R0___2 = 713,\n\tFN_VI1_R0_B___2 = 714,\n\tFN_VI2_G0___2 = 715,\n\tFN_VI2_DATA3_VI2_B3_B = 716,\n\tFN_A12___7 = 717,\n\tFN_SCIFB2_RXD_B___2 = 718,\n\tFN_MSIOF2_TXD___3 = 719,\n\tFN_VI1_R1___2 = 720,\n\tFN_VI1_R1_B___2 = 721,\n\tFN_VI2_G1___2 = 722,\n\tFN_VI2_DATA4_VI2_B4_B = 723,\n\tFN_A13___7 = 724,\n\tFN_SCIFB2_RTS_N_B___2 = 725,\n\tFN_EX_WAIT2___4 = 726,\n\tFN_MSIOF2_RXD___3 = 727,\n\tFN_VI1_R2___2 = 728,\n\tFN_VI1_R2_B___2 = 729,\n\tFN_VI2_G2___2 = 730,\n\tFN_VI2_DATA5_VI2_B5_B = 731,\n\tFN_A14___7 = 732,\n\tFN_SCIFB2_TXD_B___2 = 733,\n\tFN_ATACS11_N___3 = 734,\n\tFN_MSIOF2_SS1___4 = 735,\n\tFN_A15___7 = 736,\n\tFN_SCIFB2_SCK_B___2 = 737,\n\tFN_ATARD1_N___3 = 738,\n\tFN_MSIOF2_SS2___4 = 739,\n\tFN_A16___7 = 740,\n\tFN_ATAWR1_N___3 = 741,\n\tFN_A17___7 = 742,\n\tFN_AD_DO_B = 743,\n\tFN_ATADIR1_N___3 = 744,\n\tFN_A18___7 = 745,\n\tFN_AD_CLK_B = 746,\n\tFN_ATAG1_N___3 = 747,\n\tFN_A19___7 = 748,\n\tFN_AD_NCS_N_B = 749,\n\tFN_ATACS01_N___3 = 750,\n\tFN_EX_WAIT0_B = 751,\n\tFN_A20___7 = 752,\n\tFN_SPCLK___4 = 753,\n\tFN_VI1_R3___2 = 754,\n\tFN_VI1_R3_B___2 = 755,\n\tFN_VI2_G4___2 = 756,\n\tFN_A21___7 = 757,\n\tFN_MOSI_IO0___4 = 758,\n\tFN_VI1_R4___2 = 759,\n\tFN_VI1_R4_B___2 = 760,\n\tFN_VI2_G5___2 = 761,\n\tFN_A22___7 = 762,\n\tFN_MISO_IO1___4 = 763,\n\tFN_VI1_R5___2 = 764,\n\tFN_VI1_R5_B___2 = 765,\n\tFN_VI2_G6___2 = 766,\n\tFN_A23___7 = 767,\n\tFN_IO2___4 = 768,\n\tFN_VI1_G7___2 = 769,\n\tFN_VI1_G7_B___2 = 770,\n\tFN_VI2_G7___2 = 771,\n\tFN_A24___7 = 772,\n\tFN_IO3___4 = 773,\n\tFN_VI1_R7___2 = 774,\n\tFN_VI1_R7_B___2 = 775,\n\tFN_VI2_CLKENB___4 = 776,\n\tFN_VI2_CLKENB_B = 777,\n\tFN_A25___7 = 778,\n\tFN_SSL___4 = 779,\n\tFN_VI1_G6___2 = 780,\n\tFN_VI1_G6_B___2 = 781,\n\tFN_VI2_FIELD___4 = 782,\n\tFN_VI2_FIELD_B = 783,\n\tFN_CS0_N___5 = 784,\n\tFN_VI1_R6___2 = 785,\n\tFN_VI1_R6_B___2 = 786,\n\tFN_VI2_G3___2 = 787,\n\tFN_MSIOF0_SS2_B___2 = 788,\n\tFN_CS1_N_A26___5 = 789,\n\tFN_SPEEDIN___5 = 790,\n\tFN_VI0_R7___5 = 791,\n\tFN_VI0_R7_B = 792,\n\tFN_VI2_CLK___4 = 793,\n\tFN_VI2_CLK_B = 794,\n\tFN_EX_CS0_N___4 = 795,\n\tFN_HRX1_B___5 = 796,\n\tFN_VI1_G5___2 = 797,\n\tFN_VI1_G5_B___2 = 798,\n\tFN_VI2_R0___2 = 799,\n\tFN_HTX0_B___5 = 800,\n\tFN_MSIOF0_SS1_B___2 = 801,\n\tFN_EX_CS1_N___4 = 802,\n\tFN_GPS_CLK___3 = 803,\n\tFN_HCTS1_N_B___2 = 804,\n\tFN_VI1_FIELD___7 = 805,\n\tFN_VI1_FIELD_B___2 = 806,\n\tFN_VI2_R1___2 = 807,\n\tFN_EX_CS2_N___4 = 808,\n\tFN_GPS_SIGN___3 = 809,\n\tFN_HRTS1_N_B___2 = 810,\n\tFN_VI3_CLKENB___3 = 811,\n\tFN_VI1_G0___2 = 812,\n\tFN_VI1_G0_B___2 = 813,\n\tFN_VI2_R2___2 = 814,\n\tFN_EX_CS3_N___4 = 815,\n\tFN_GPS_MAG___3 = 816,\n\tFN_VI3_FIELD___3 = 817,\n\tFN_VI1_G1___2 = 818,\n\tFN_VI1_G1_B___2 = 819,\n\tFN_VI2_R3___2 = 820,\n\tFN_EX_CS4_N___4 = 821,\n\tFN_MSIOF1_SCK_B___4 = 822,\n\tFN_VI3_HSYNC_N___2 = 823,\n\tFN_VI2_HSYNC_N___3 = 824,\n\tFN_IIC1_SCL___2 = 825,\n\tFN_VI2_HSYNC_N_B = 826,\n\tFN_INTC_EN0_N = 827,\n\tFN_I2C1_SCL___3 = 828,\n\tFN_EX_CS5_N___4 = 829,\n\tFN_CAN0_RX___5 = 830,\n\tFN_MSIOF1_RXD_B___4 = 831,\n\tFN_VI3_VSYNC_N___2 = 832,\n\tFN_VI1_G2___2 = 833,\n\tFN_VI1_G2_B___2 = 834,\n\tFN_VI2_R4___2 = 835,\n\tFN_IIC1_SDA___2 = 836,\n\tFN_INTC_EN1_N = 837,\n\tFN_I2C1_SDA___3 = 838,\n\tFN_BS_N___5 = 839,\n\tFN_IETX___5 = 840,\n\tFN_HTX1_B___5 = 841,\n\tFN_CAN1_TX___5 = 842,\n\tFN_DRACK0___7 = 843,\n\tFN_IETX_C___3 = 844,\n\tFN_RD_N___5 = 845,\n\tFN_CAN0_TX___5 = 846,\n\tFN_SCIFA0_SCK_B = 847,\n\tFN_RD_WR_N___5 = 848,\n\tFN_VI1_G3___2 = 849,\n\tFN_VI1_G3_B___2 = 850,\n\tFN_VI2_R5___2 = 851,\n\tFN_SCIFA0_RXD_B___3 = 852,\n\tFN_WE0_N___5 = 853,\n\tFN_IECLK___5 = 854,\n\tFN_CAN_CLK___5 = 855,\n\tFN_VI2_VSYNC_N___3 = 856,\n\tFN_SCIFA0_TXD_B___3 = 857,\n\tFN_VI2_VSYNC_N_B = 858,\n\tFN_WE1_N___5 = 859,\n\tFN_IERX___5 = 860,\n\tFN_CAN1_RX___5 = 861,\n\tFN_VI1_G4___2 = 862,\n\tFN_VI1_G4_B___2 = 863,\n\tFN_VI2_R6___2 = 864,\n\tFN_SCIFA0_CTS_N_B = 865,\n\tFN_IERX_C___3 = 866,\n\tFN_EX_WAIT0___7 = 867,\n\tFN_IRQ3___6 = 868,\n\tFN_VI3_CLK___3 = 869,\n\tFN_SCIFA0_RTS_N_B = 870,\n\tFN_HRX0_B___5 = 871,\n\tFN_MSIOF0_SCK_B___3 = 872,\n\tFN_DREQ0_N___4 = 873,\n\tFN_VI1_HSYNC_N___5 = 874,\n\tFN_VI1_HSYNC_N_B___2 = 875,\n\tFN_VI2_R7___2 = 876,\n\tFN_SSI_SCK78_C___2 = 877,\n\tFN_SSI_WS78_B___5 = 878,\n\tFN_DACK0___7 = 879,\n\tFN_IRQ0___7 = 880,\n\tFN_SSI_SCK6_B___3 = 881,\n\tFN_VI1_VSYNC_N___5 = 882,\n\tFN_VI1_VSYNC_N_B___2 = 883,\n\tFN_SSI_WS78_C___2 = 884,\n\tFN_DREQ1_N___4 = 885,\n\tFN_VI1_CLKENB___7 = 886,\n\tFN_VI1_CLKENB_B___2 = 887,\n\tFN_SSI_SDATA7_C___2 = 888,\n\tFN_SSI_SCK78_B___5 = 889,\n\tFN_DACK1___6 = 890,\n\tFN_IRQ1___6 = 891,\n\tFN_SSI_WS6_B___3 = 892,\n\tFN_SSI_SDATA8_C___2 = 893,\n\tFN_DREQ2_N___3 = 894,\n\tFN_HSCK1_B___3 = 895,\n\tFN_HCTS0_N_B___2 = 896,\n\tFN_MSIOF0_TXD_B___3 = 897,\n\tFN_DACK2___5 = 898,\n\tFN_IRQ2___6 = 899,\n\tFN_SSI_SDATA6_B___3 = 900,\n\tFN_HRTS0_N_B___2 = 901,\n\tFN_MSIOF0_RXD_B___3 = 902,\n\tFN_ETH_CRS_DV___6 = 903,\n\tFN_STP_ISCLK_0_B___2 = 904,\n\tFN_TS_SDEN0_D___2 = 905,\n\tFN_GLO_Q0_C___2 = 906,\n\tFN_IIC2_SCL_E = 907,\n\tFN_I2C2_SCL_E___2 = 908,\n\tFN_ETH_RX_ER___6 = 909,\n\tFN_STP_ISD_0_B___2 = 910,\n\tFN_TS_SPSYNC0_D___2 = 911,\n\tFN_GLO_Q1_C___2 = 912,\n\tFN_IIC2_SDA_E = 913,\n\tFN_I2C2_SDA_E___2 = 914,\n\tFN_ETH_RXD0___6 = 915,\n\tFN_STP_ISEN_0_B___2 = 916,\n\tFN_TS_SDAT0_D = 917,\n\tFN_GLO_I0_C___2 = 918,\n\tFN_SCIFB1_SCK_G = 919,\n\tFN_SCK1_E = 920,\n\tFN_ETH_RXD1___6 = 921,\n\tFN_HRX0_E = 922,\n\tFN_STP_ISSYNC_0_B___2 = 923,\n\tFN_TS_SCK0_D___2 = 924,\n\tFN_GLO_I1_C___2 = 925,\n\tFN_SCIFB1_RXD_G = 926,\n\tFN_RX1_E = 927,\n\tFN_ETH_LINK___6 = 928,\n\tFN_HTX0_E = 929,\n\tFN_STP_IVCXO27_0_B___2 = 930,\n\tFN_SCIFB1_TXD_G = 931,\n\tFN_TX1_E = 932,\n\tFN_ETH_REF_CLK___3 = 933,\n\tFN_HCTS0_N_E = 934,\n\tFN_STP_IVCXO27_1_B = 935,\n\tFN_HRX0_F = 936,\n\tFN_ETH_MDIO___6 = 937,\n\tFN_HRTS0_N_E = 938,\n\tFN_SIM0_D_C = 939,\n\tFN_HCTS0_N_F = 940,\n\tFN_ETH_TXD1___6 = 941,\n\tFN_HTX0_F = 942,\n\tFN_BPFCLK_G = 943,\n\tFN_ETH_TX_EN___6 = 944,\n\tFN_SIM0_CLK_C = 945,\n\tFN_HRTS0_N_F = 946,\n\tFN_ETH_MAGIC___6 = 947,\n\tFN_SIM0_RST_C = 948,\n\tFN_ETH_TXD0___6 = 949,\n\tFN_STP_ISCLK_1_B = 950,\n\tFN_TS_SDEN1_C = 951,\n\tFN_GLO_SCLK_C___2 = 952,\n\tFN_ETH_MDC___6 = 953,\n\tFN_STP_ISD_1_B = 954,\n\tFN_TS_SPSYNC1_C = 955,\n\tFN_GLO_SDATA_C___2 = 956,\n\tFN_PWM0___5 = 957,\n\tFN_SCIFA2_SCK_C = 958,\n\tFN_STP_ISEN_1_B = 959,\n\tFN_TS_SDAT1_C = 960,\n\tFN_GLO_SS_C___2 = 961,\n\tFN_PWM1___6 = 962,\n\tFN_SCIFA2_TXD_C = 963,\n\tFN_STP_ISSYNC_1_B = 964,\n\tFN_TS_SCK1_C = 965,\n\tFN_GLO_RFON_C___2 = 966,\n\tFN_PCMOE_N = 967,\n\tFN_PWM2___6 = 968,\n\tFN_PWMFSW0___2 = 969,\n\tFN_SCIFA2_RXD_C = 970,\n\tFN_PCMWE_N = 971,\n\tFN_IECLK_C___3 = 972,\n\tFN_DU_DOTCLKIN1 = 973,\n\tFN_AUDIO_CLKC___5 = 974,\n\tFN_AUDIO_CLKOUT_C___4 = 975,\n\tFN_VI0_CLK___7 = 976,\n\tFN_ATACS00_N___3 = 977,\n\tFN_AVB_RXD1___5 = 978,\n\tFN_VI0_DATA0_VI0_B0___6 = 979,\n\tFN_ATACS10_N___3 = 980,\n\tFN_AVB_RXD2___5 = 981,\n\tFN_VI0_DATA1_VI0_B1___6 = 982,\n\tFN_ATARD0_N___3 = 983,\n\tFN_AVB_RXD3___5 = 984,\n\tFN_VI0_DATA2_VI0_B2___6 = 985,\n\tFN_ATAWR0_N___3 = 986,\n\tFN_AVB_RXD4___5 = 987,\n\tFN_VI0_DATA3_VI0_B3___6 = 988,\n\tFN_ATADIR0_N___3 = 989,\n\tFN_AVB_RXD5___5 = 990,\n\tFN_VI0_DATA4_VI0_B4___6 = 991,\n\tFN_ATAG0_N___3 = 992,\n\tFN_AVB_RXD6___5 = 993,\n\tFN_VI0_DATA5_VI0_B5___6 = 994,\n\tFN_EX_WAIT1___5 = 995,\n\tFN_AVB_RXD7___5 = 996,\n\tFN_VI0_DATA6_VI0_B6___5 = 997,\n\tFN_AVB_RX_ER___5 = 998,\n\tFN_VI0_DATA7_VI0_B7___5 = 999,\n\tFN_AVB_RX_CLK___5 = 1000,\n\tFN_VI1_CLK___7 = 1001,\n\tFN_AVB_RX_DV___5 = 1002,\n\tFN_VI1_DATA0_VI1_B0___2 = 1003,\n\tFN_SCIFA1_SCK_D = 1004,\n\tFN_AVB_CRS___5 = 1005,\n\tFN_VI1_DATA1_VI1_B1___2 = 1006,\n\tFN_SCIFA1_RXD_D = 1007,\n\tFN_AVB_MDC___5 = 1008,\n\tFN_VI1_DATA2_VI1_B2___2 = 1009,\n\tFN_SCIFA1_TXD_D = 1010,\n\tFN_AVB_MDIO___5 = 1011,\n\tFN_VI1_DATA3_VI1_B3___2 = 1012,\n\tFN_SCIFA1_CTS_N_D = 1013,\n\tFN_AVB_GTX_CLK___5 = 1014,\n\tFN_VI1_DATA4_VI1_B4___2 = 1015,\n\tFN_SCIFA1_RTS_N_D = 1016,\n\tFN_AVB_MAGIC___5 = 1017,\n\tFN_VI1_DATA5_VI1_B5___2 = 1018,\n\tFN_AVB_PHY_INT___5 = 1019,\n\tFN_VI1_DATA6_VI1_B6___2 = 1020,\n\tFN_AVB_GTXREFCLK___5 = 1021,\n\tFN_SD0_CLK___7 = 1022,\n\tFN_VI1_DATA0_VI1_B0_B = 1023,\n\tFN_SD0_CMD___7 = 1024,\n\tFN_SCIFB1_SCK_B___2 = 1025,\n\tFN_VI1_DATA1_VI1_B1_B = 1026,\n\tFN_SD0_DAT0___5 = 1027,\n\tFN_SCIFB1_RXD_B___2 = 1028,\n\tFN_VI1_DATA2_VI1_B2_B = 1029,\n\tFN_SD0_DAT1___5 = 1030,\n\tFN_SCIFB1_TXD_B___2 = 1031,\n\tFN_VI1_DATA3_VI1_B3_B = 1032,\n\tFN_SD0_DAT2___5 = 1033,\n\tFN_SCIFB1_CTS_N_B = 1034,\n\tFN_VI1_DATA4_VI1_B4_B = 1035,\n\tFN_SD0_DAT3___5 = 1036,\n\tFN_SCIFB1_RTS_N_B = 1037,\n\tFN_VI1_DATA5_VI1_B5_B = 1038,\n\tFN_SD0_CD___7 = 1039,\n\tFN_MMC0_D6___3 = 1040,\n\tFN_TS_SDEN0_B___3 = 1041,\n\tFN_USB0_EXTP = 1042,\n\tFN_GLO_SCLK___2 = 1043,\n\tFN_VI1_DATA6_VI1_B6_B = 1044,\n\tFN_IIC1_SCL_B___2 = 1045,\n\tFN_I2C1_SCL_B___3 = 1046,\n\tFN_VI2_DATA6_VI2_B6_B = 1047,\n\tFN_SD0_WP___7 = 1048,\n\tFN_MMC0_D7___3 = 1049,\n\tFN_TS_SPSYNC0_B___3 = 1050,\n\tFN_USB0_IDIN = 1051,\n\tFN_GLO_SDATA___2 = 1052,\n\tFN_VI1_DATA7_VI1_B7_B = 1053,\n\tFN_IIC1_SDA_B___2 = 1054,\n\tFN_I2C1_SDA_B___3 = 1055,\n\tFN_VI2_DATA7_VI2_B7_B = 1056,\n\tFN_SD1_CLK___4 = 1057,\n\tFN_AVB_TX_EN___5 = 1058,\n\tFN_SD1_CMD___4 = 1059,\n\tFN_AVB_TX_ER___5 = 1060,\n\tFN_SCIFB0_SCK_B___2 = 1061,\n\tFN_SD1_DAT0___2 = 1062,\n\tFN_AVB_TX_CLK___5 = 1063,\n\tFN_SCIFB0_RXD_B___2 = 1064,\n\tFN_SD1_DAT1___2 = 1065,\n\tFN_AVB_LINK___5 = 1066,\n\tFN_SCIFB0_TXD_B___2 = 1067,\n\tFN_SD1_DAT2___2 = 1068,\n\tFN_AVB_COL___5 = 1069,\n\tFN_SCIFB0_CTS_N_B___2 = 1070,\n\tFN_SD1_DAT3___2 = 1071,\n\tFN_AVB_RXD0___5 = 1072,\n\tFN_SCIFB0_RTS_N_B___2 = 1073,\n\tFN_SD1_CD___5 = 1074,\n\tFN_MMC1_D6___2 = 1075,\n\tFN_TS_SDEN1___2 = 1076,\n\tFN_USB1_EXTP = 1077,\n\tFN_GLO_SS___2 = 1078,\n\tFN_VI0_CLK_B = 1079,\n\tFN_IIC2_SCL_D = 1080,\n\tFN_I2C2_SCL_D___3 = 1081,\n\tFN_SIM0_CLK_B = 1082,\n\tFN_VI3_CLK_B = 1083,\n\tFN_SD1_WP___5 = 1084,\n\tFN_MMC1_D7___2 = 1085,\n\tFN_TS_SPSYNC1___2 = 1086,\n\tFN_USB1_IDIN = 1087,\n\tFN_GLO_RFON___2 = 1088,\n\tFN_VI1_CLK_B___2 = 1089,\n\tFN_IIC2_SDA_D = 1090,\n\tFN_I2C2_SDA_D___3 = 1091,\n\tFN_SIM0_D_B___2 = 1092,\n\tFN_SD2_CLK___5 = 1093,\n\tFN_MMC0_CLK___2 = 1094,\n\tFN_SIM0_CLK___2 = 1095,\n\tFN_VI0_DATA0_VI0_B0_B = 1096,\n\tFN_TS_SDEN0_C___2 = 1097,\n\tFN_GLO_SCLK_B___2 = 1098,\n\tFN_VI3_DATA0_B = 1099,\n\tFN_SD2_CMD___5 = 1100,\n\tFN_MMC0_CMD___2 = 1101,\n\tFN_SIM0_D___2 = 1102,\n\tFN_VI0_DATA1_VI0_B1_B = 1103,\n\tFN_SCIFB1_SCK_E = 1104,\n\tFN_SCK1_D = 1105,\n\tFN_TS_SPSYNC0_C___2 = 1106,\n\tFN_GLO_SDATA_B___2 = 1107,\n\tFN_VI3_DATA1_B = 1108,\n\tFN_SD2_DAT0___3 = 1109,\n\tFN_MMC0_D0___2 = 1110,\n\tFN_FMCLK_B___4 = 1111,\n\tFN_VI0_DATA2_VI0_B2_B = 1112,\n\tFN_SCIFB1_RXD_E = 1113,\n\tFN_RX1_D___4 = 1114,\n\tFN_TS_SDAT0_C = 1115,\n\tFN_GLO_SS_B___2 = 1116,\n\tFN_VI3_DATA2_B = 1117,\n\tFN_SD2_DAT1___3 = 1118,\n\tFN_MMC0_D1___2 = 1119,\n\tFN_FMIN_B___4 = 1120,\n\tFN_VI0_DATA3_VI0_B3_B = 1121,\n\tFN_SCIFB1_TXD_E = 1122,\n\tFN_TX1_D___4 = 1123,\n\tFN_TS_SCK0_C___2 = 1124,\n\tFN_GLO_RFON_B___2 = 1125,\n\tFN_VI3_DATA3_B = 1126,\n\tFN_SD2_DAT2___3 = 1127,\n\tFN_MMC0_D2___2 = 1128,\n\tFN_BPFCLK_B___4 = 1129,\n\tFN_VI0_DATA4_VI0_B4_B = 1130,\n\tFN_HRX0_D = 1131,\n\tFN_TS_SDEN1_B = 1132,\n\tFN_GLO_Q0_B___2 = 1133,\n\tFN_VI3_DATA4_B = 1134,\n\tFN_SD2_DAT3___3 = 1135,\n\tFN_MMC0_D3___2 = 1136,\n\tFN_SIM0_RST___2 = 1137,\n\tFN_VI0_DATA5_VI0_B5_B = 1138,\n\tFN_HTX0_D = 1139,\n\tFN_TS_SPSYNC1_B = 1140,\n\tFN_GLO_Q1_B___2 = 1141,\n\tFN_VI3_DATA5_B = 1142,\n\tFN_SD2_CD___5 = 1143,\n\tFN_MMC0_D4___3 = 1144,\n\tFN_TS_SDAT0_B___2 = 1145,\n\tFN_USB2_EXTP = 1146,\n\tFN_GLO_I0___2 = 1147,\n\tFN_VI0_DATA6_VI0_B6_B = 1148,\n\tFN_HCTS0_N_D = 1149,\n\tFN_TS_SDAT1_B = 1150,\n\tFN_GLO_I0_B___2 = 1151,\n\tFN_VI3_DATA6_B = 1152,\n\tFN_SD2_WP___5 = 1153,\n\tFN_MMC0_D5___3 = 1154,\n\tFN_TS_SCK0_B___3 = 1155,\n\tFN_USB2_IDIN = 1156,\n\tFN_GLO_I1___2 = 1157,\n\tFN_VI0_DATA7_VI0_B7_B = 1158,\n\tFN_HRTS0_N_D = 1159,\n\tFN_TS_SCK1_B = 1160,\n\tFN_GLO_I1_B___2 = 1161,\n\tFN_VI3_DATA7_B = 1162,\n\tFN_SD3_CLK___2 = 1163,\n\tFN_MMC1_CLK___2 = 1164,\n\tFN_SD3_CMD___2 = 1165,\n\tFN_MMC1_CMD___2 = 1166,\n\tFN_MTS_N = 1167,\n\tFN_SD3_DAT0___2 = 1168,\n\tFN_MMC1_D0___2 = 1169,\n\tFN_STM_N = 1170,\n\tFN_SD3_DAT1___2 = 1171,\n\tFN_MMC1_D1___2 = 1172,\n\tFN_MDATA___2 = 1173,\n\tFN_SD3_DAT2___2 = 1174,\n\tFN_MMC1_D2___2 = 1175,\n\tFN_SDATA___2 = 1176,\n\tFN_SD3_DAT3___2 = 1177,\n\tFN_MMC1_D3___2 = 1178,\n\tFN_SCKZ___2 = 1179,\n\tFN_SD3_CD___2 = 1180,\n\tFN_MMC1_D4___2 = 1181,\n\tFN_TS_SDAT1___2 = 1182,\n\tFN_VSP___2 = 1183,\n\tFN_GLO_Q0___2 = 1184,\n\tFN_SIM0_RST_B___2 = 1185,\n\tFN_SD3_WP___2 = 1186,\n\tFN_MMC1_D5___2 = 1187,\n\tFN_TS_SCK1___2 = 1188,\n\tFN_GLO_Q1___2 = 1189,\n\tFN_FMIN_C___4 = 1190,\n\tFN_FMIN_E___3 = 1191,\n\tFN_FMIN_F = 1192,\n\tFN_MLB_CLK___5 = 1193,\n\tFN_IIC2_SCL_B = 1194,\n\tFN_I2C2_SCL_B___3 = 1195,\n\tFN_MLB_SIG___5 = 1196,\n\tFN_SCIFB1_RXD_D___2 = 1197,\n\tFN_RX1_C___5 = 1198,\n\tFN_IIC2_SDA_B = 1199,\n\tFN_I2C2_SDA_B___3 = 1200,\n\tFN_MLB_DAT___5 = 1201,\n\tFN_SCIFB1_TXD_D___2 = 1202,\n\tFN_TX1_C___5 = 1203,\n\tFN_BPFCLK_C___4 = 1204,\n\tFN_SSI_SCK0129___4 = 1205,\n\tFN_CAN_CLK_B___6 = 1206,\n\tFN_MOUT0___2 = 1207,\n\tFN_SSI_WS0129___4 = 1208,\n\tFN_CAN0_TX_B___6 = 1209,\n\tFN_MOUT1___2 = 1210,\n\tFN_SSI_SDATA0___5 = 1211,\n\tFN_CAN0_RX_B___6 = 1212,\n\tFN_MOUT2___2 = 1213,\n\tFN_SSI_SDATA1___5 = 1214,\n\tFN_CAN1_TX_B___5 = 1215,\n\tFN_MOUT5___2 = 1216,\n\tFN_SSI_SDATA2___5 = 1217,\n\tFN_CAN1_RX_B___5 = 1218,\n\tFN_SSI_SCK1___4 = 1219,\n\tFN_MOUT6___2 = 1220,\n\tFN_SSI_SCK34___7 = 1221,\n\tFN_STP_OPWM_0___2 = 1222,\n\tFN_SCIFB0_SCK___3 = 1223,\n\tFN_MSIOF1_SCK___4 = 1224,\n\tFN_CAN_DEBUG_HW_TRIGGER___2 = 1225,\n\tFN_SSI_WS34___7 = 1226,\n\tFN_STP_IVCXO27_0___2 = 1227,\n\tFN_SCIFB0_RXD___3 = 1228,\n\tFN_MSIOF1_SYNC___4 = 1229,\n\tFN_CAN_STEP0___2 = 1230,\n\tFN_SSI_SDATA3___7 = 1231,\n\tFN_STP_ISCLK_0___2 = 1232,\n\tFN_SCIFB0_TXD___3 = 1233,\n\tFN_MSIOF1_SS1___3 = 1234,\n\tFN_CAN_TXCLK___2 = 1235,\n\tFN_SSI_SCK4___6 = 1236,\n\tFN_STP_ISD_0___2 = 1237,\n\tFN_SCIFB0_CTS_N___3 = 1238,\n\tFN_MSIOF1_SS2___3 = 1239,\n\tFN_SSI_SCK5_C = 1240,\n\tFN_CAN_DEBUGOUT0___2 = 1241,\n\tFN_SSI_WS4___6 = 1242,\n\tFN_STP_ISEN_0___2 = 1243,\n\tFN_SCIFB0_RTS_N___3 = 1244,\n\tFN_MSIOF1_TXD___4 = 1245,\n\tFN_SSI_WS5_C = 1246,\n\tFN_CAN_DEBUGOUT1___2 = 1247,\n\tFN_SSI_SDATA4___6 = 1248,\n\tFN_STP_ISSYNC_0___2 = 1249,\n\tFN_MSIOF1_RXD___4 = 1250,\n\tFN_CAN_DEBUGOUT2___2 = 1251,\n\tFN_SSI_SCK5___5 = 1252,\n\tFN_SCIFB1_SCK___3 = 1253,\n\tFN_IERX_B___4 = 1254,\n\tFN_DU2_EXHSYNC_DU2_HSYNC = 1255,\n\tFN_QSTH_QHS___5 = 1256,\n\tFN_CAN_DEBUGOUT3___2 = 1257,\n\tFN_SSI_WS5___5 = 1258,\n\tFN_SCIFB1_RXD___3 = 1259,\n\tFN_IECLK_B___4 = 1260,\n\tFN_DU2_EXVSYNC_DU2_VSYNC = 1261,\n\tFN_QSTB_QHE___5 = 1262,\n\tFN_CAN_DEBUGOUT4___2 = 1263,\n\tFN_SSI_SDATA5___5 = 1264,\n\tFN_SCIFB1_TXD___3 = 1265,\n\tFN_IETX_B___4 = 1266,\n\tFN_DU2_DR2 = 1267,\n\tFN_LCDOUT2___5 = 1268,\n\tFN_CAN_DEBUGOUT5___2 = 1269,\n\tFN_SSI_SCK6___5 = 1270,\n\tFN_SCIFB1_CTS_N___2 = 1271,\n\tFN_BPFCLK_D___4 = 1272,\n\tFN_DU2_DR3 = 1273,\n\tFN_LCDOUT3___5 = 1274,\n\tFN_CAN_DEBUGOUT6___2 = 1275,\n\tFN_BPFCLK_F = 1276,\n\tFN_SSI_WS6___5 = 1277,\n\tFN_SCIFB1_RTS_N___2 = 1278,\n\tFN_CAN0_TX_D___4 = 1279,\n\tFN_DU2_DR4 = 1280,\n\tFN_LCDOUT4___5 = 1281,\n\tFN_CAN_DEBUGOUT7___2 = 1282,\n\tFN_SSI_SDATA6___5 = 1283,\n\tFN_FMIN_D___4 = 1284,\n\tFN_DU2_DR5 = 1285,\n\tFN_LCDOUT5___5 = 1286,\n\tFN_CAN_DEBUGOUT8___2 = 1287,\n\tFN_SSI_SCK78___5 = 1288,\n\tFN_STP_IVCXO27_1 = 1289,\n\tFN_SCK1___3 = 1290,\n\tFN_SCIFA1_SCK___3 = 1291,\n\tFN_DU2_DR6 = 1292,\n\tFN_LCDOUT6___5 = 1293,\n\tFN_CAN_DEBUGOUT9___2 = 1294,\n\tFN_SSI_WS78___5 = 1295,\n\tFN_STP_ISCLK_1 = 1296,\n\tFN_SCIFB2_SCK___3 = 1297,\n\tFN_SCIFA2_CTS_N = 1298,\n\tFN_DU2_DR7 = 1299,\n\tFN_LCDOUT7___5 = 1300,\n\tFN_CAN_DEBUGOUT10___2 = 1301,\n\tFN_SSI_SDATA7___5 = 1302,\n\tFN_STP_ISD_1 = 1303,\n\tFN_SCIFB2_RXD___3 = 1304,\n\tFN_SCIFA2_RTS_N = 1305,\n\tFN_TCLK2___4 = 1306,\n\tFN_QSTVA_QVS___5 = 1307,\n\tFN_CAN_DEBUGOUT11___2 = 1308,\n\tFN_BPFCLK_E___3 = 1309,\n\tFN_SSI_SDATA7_B___5 = 1310,\n\tFN_FMIN_G = 1311,\n\tFN_SSI_SDATA8___5 = 1312,\n\tFN_STP_ISEN_1 = 1313,\n\tFN_SCIFB2_TXD___3 = 1314,\n\tFN_CAN0_TX_C___4 = 1315,\n\tFN_CAN_DEBUGOUT12___2 = 1316,\n\tFN_SSI_SDATA8_B___5 = 1317,\n\tFN_SSI_SDATA9___4 = 1318,\n\tFN_STP_ISSYNC_1 = 1319,\n\tFN_SCIFB2_CTS_N___3 = 1320,\n\tFN_SSI_WS1___4 = 1321,\n\tFN_SSI_SDATA5_C = 1322,\n\tFN_CAN_DEBUGOUT13___2 = 1323,\n\tFN_AUDIO_CLKA___6 = 1324,\n\tFN_SCIFB2_RTS_N___3 = 1325,\n\tFN_CAN_DEBUGOUT14___2 = 1326,\n\tFN_AUDIO_CLKB___6 = 1327,\n\tFN_SCIF_CLK___6 = 1328,\n\tFN_CAN0_RX_D___4 = 1329,\n\tFN_DVC_MUTE___4 = 1330,\n\tFN_CAN0_RX_C___4 = 1331,\n\tFN_CAN_DEBUGOUT15___2 = 1332,\n\tFN_REMOCON___4 = 1333,\n\tFN_SCIFA0_SCK = 1334,\n\tFN_HSCK1___5 = 1335,\n\tFN_SCK0___4 = 1336,\n\tFN_MSIOF3_SS2 = 1337,\n\tFN_DU2_DG2 = 1338,\n\tFN_LCDOUT10___5 = 1339,\n\tFN_IIC1_SDA_C___2 = 1340,\n\tFN_I2C1_SDA_C___3 = 1341,\n\tFN_SCIFA0_RXD___3 = 1342,\n\tFN_HRX1___4 = 1343,\n\tFN_RX0___4 = 1344,\n\tFN_DU2_DR0 = 1345,\n\tFN_LCDOUT0___5 = 1346,\n\tFN_SCIFA0_TXD___3 = 1347,\n\tFN_HTX1___4 = 1348,\n\tFN_TX0___4 = 1349,\n\tFN_DU2_DR1 = 1350,\n\tFN_LCDOUT1___5 = 1351,\n\tFN_SCIFA0_CTS_N = 1352,\n\tFN_HCTS1_N___3 = 1353,\n\tFN_CTS0_N___2 = 1354,\n\tFN_MSIOF3_SYNC = 1355,\n\tFN_DU2_DG3 = 1356,\n\tFN_LCDOUT11___5 = 1357,\n\tFN_PWM0_B___6 = 1358,\n\tFN_IIC1_SCL_C___2 = 1359,\n\tFN_I2C1_SCL_C___3 = 1360,\n\tFN_SCIFA0_RTS_N = 1361,\n\tFN_HRTS1_N___3 = 1362,\n\tFN_RTS0_N___2 = 1363,\n\tFN_MSIOF3_SS1 = 1364,\n\tFN_DU2_DG0 = 1365,\n\tFN_LCDOUT8___5 = 1366,\n\tFN_PWM1_B___4 = 1367,\n\tFN_SCIFA1_RXD___3 = 1368,\n\tFN_AD_DI___2 = 1369,\n\tFN_RX1___4 = 1370,\n\tFN_DU2_EXODDF_DU2_ODDF_DISP_CDE = 1371,\n\tFN_QCPV_QDE___5 = 1372,\n\tFN_SCIFA1_TXD___3 = 1373,\n\tFN_AD_DO___2 = 1374,\n\tFN_TX1___4 = 1375,\n\tFN_DU2_DG1 = 1376,\n\tFN_LCDOUT9___5 = 1377,\n\tFN_SCIFA1_CTS_N = 1378,\n\tFN_AD_CLK___2 = 1379,\n\tFN_CTS1_N___2 = 1380,\n\tFN_MSIOF3_RXD = 1381,\n\tFN_DU0_DOTCLKOUT = 1382,\n\tFN_QCLK___5 = 1383,\n\tFN_SCIFA1_RTS_N = 1384,\n\tFN_AD_NCS_N = 1385,\n\tFN_RTS1_N___2 = 1386,\n\tFN_MSIOF3_TXD = 1387,\n\tFN_DU1_DOTCLKOUT___3 = 1388,\n\tFN_QSTVB_QVE___5 = 1389,\n\tFN_HRTS0_N_C = 1390,\n\tFN_SCIFA2_SCK___3 = 1391,\n\tFN_FMCLK___4 = 1392,\n\tFN_SCK2___3 = 1393,\n\tFN_MSIOF3_SCK = 1394,\n\tFN_DU2_DG7 = 1395,\n\tFN_LCDOUT15___5 = 1396,\n\tFN_SCIF_CLK_B___5 = 1397,\n\tFN_SCIFA2_RXD___3 = 1398,\n\tFN_FMIN___4 = 1399,\n\tFN_TX2___4 = 1400,\n\tFN_DU2_DB0 = 1401,\n\tFN_LCDOUT16___5 = 1402,\n\tFN_IIC2_SCL = 1403,\n\tFN_I2C2_SCL___3 = 1404,\n\tFN_SCIFA2_TXD___3 = 1405,\n\tFN_BPFCLK___4 = 1406,\n\tFN_RX2___4 = 1407,\n\tFN_DU2_DB1 = 1408,\n\tFN_LCDOUT17___5 = 1409,\n\tFN_IIC2_SDA = 1410,\n\tFN_I2C2_SDA___3 = 1411,\n\tFN_HSCK0___6 = 1412,\n\tFN_TS_SDEN0___3 = 1413,\n\tFN_DU2_DG4 = 1414,\n\tFN_LCDOUT12___5 = 1415,\n\tFN_HCTS0_N_C = 1416,\n\tFN_HRX0___4 = 1417,\n\tFN_DU2_DB2 = 1418,\n\tFN_LCDOUT18___5 = 1419,\n\tFN_HTX0___4 = 1420,\n\tFN_DU2_DB3 = 1421,\n\tFN_LCDOUT19___5 = 1422,\n\tFN_HCTS0_N___4 = 1423,\n\tFN_SSI_SCK9___4 = 1424,\n\tFN_DU2_DB4 = 1425,\n\tFN_LCDOUT20___5 = 1426,\n\tFN_HRTS0_N___4 = 1427,\n\tFN_SSI_WS9___4 = 1428,\n\tFN_DU2_DB5 = 1429,\n\tFN_LCDOUT21___5 = 1430,\n\tFN_MSIOF0_SCK___4 = 1431,\n\tFN_TS_SDAT0___2 = 1432,\n\tFN_ADICLK___6 = 1433,\n\tFN_DU2_DB6 = 1434,\n\tFN_LCDOUT22___5 = 1435,\n\tFN_MSIOF0_SYNC___4 = 1436,\n\tFN_TS_SCK0___3 = 1437,\n\tFN_SSI_SCK2___4 = 1438,\n\tFN_ADIDATA___6 = 1439,\n\tFN_DU2_DB7 = 1440,\n\tFN_LCDOUT23___5 = 1441,\n\tFN_HRX0_C___2 = 1442,\n\tFN_MSIOF0_SS1___3 = 1443,\n\tFN_ADICHS0___6 = 1444,\n\tFN_DU2_DG5 = 1445,\n\tFN_LCDOUT13___5 = 1446,\n\tFN_MSIOF0_TXD___4 = 1447,\n\tFN_ADICHS1___6 = 1448,\n\tFN_DU2_DG6 = 1449,\n\tFN_LCDOUT14___5 = 1450,\n\tFN_MSIOF0_SS2___3 = 1451,\n\tFN_AUDIO_CLKOUT___5 = 1452,\n\tFN_ADICHS2___6 = 1453,\n\tFN_DU2_DISP = 1454,\n\tFN_QPOLA___5 = 1455,\n\tFN_HTX0_C___2 = 1456,\n\tFN_SCIFA2_TXD_B___3 = 1457,\n\tFN_MSIOF0_RXD___4 = 1458,\n\tFN_TS_SPSYNC0___3 = 1459,\n\tFN_SSI_WS2___4 = 1460,\n\tFN_ADICS_SAMP___6 = 1461,\n\tFN_DU2_CDE = 1462,\n\tFN_QPOLB___5 = 1463,\n\tFN_SCIFA2_RXD_B___3 = 1464,\n\tFN_USB1_PWEN___4 = 1465,\n\tFN_AUDIO_CLKOUT_D = 1466,\n\tFN_USB1_OVC___4 = 1467,\n\tFN_TCLK1_B___5 = 1468,\n\tFN_SEL_SCIF1_0___5 = 1469,\n\tFN_SEL_SCIF1_1___5 = 1470,\n\tFN_SEL_SCIF1_2___5 = 1471,\n\tFN_SEL_SCIF1_3___3 = 1472,\n\tFN_SEL_SCIF1_4 = 1473,\n\tFN_SEL_SCIFB_0___2 = 1474,\n\tFN_SEL_SCIFB_1___2 = 1475,\n\tFN_SEL_SCIFB_2___2 = 1476,\n\tFN_SEL_SCIFB2_0___2 = 1477,\n\tFN_SEL_SCIFB2_1___2 = 1478,\n\tFN_SEL_SCIFB2_2___2 = 1479,\n\tFN_SEL_SCIFB1_0___2 = 1480,\n\tFN_SEL_SCIFB1_1___2 = 1481,\n\tFN_SEL_SCIFB1_2___2 = 1482,\n\tFN_SEL_SCIFB1_3___2 = 1483,\n\tFN_SEL_SCIFB1_4 = 1484,\n\tFN_SEL_SCIFB1_5 = 1485,\n\tFN_SEL_SCIFB1_6 = 1486,\n\tFN_SEL_SCIFA1_0___3 = 1487,\n\tFN_SEL_SCIFA1_1___3 = 1488,\n\tFN_SEL_SCIFA1_2___3 = 1489,\n\tFN_SEL_SCIFA1_3 = 1490,\n\tFN_SEL_SCIF0_0___5 = 1491,\n\tFN_SEL_SCIF0_1___5 = 1492,\n\tFN_SEL_SCFA_0___2 = 1493,\n\tFN_SEL_SCFA_1___2 = 1494,\n\tFN_SEL_SOF1_0___2 = 1495,\n\tFN_SEL_SOF1_1___2 = 1496,\n\tFN_SEL_SSI7_0___5 = 1497,\n\tFN_SEL_SSI7_1___5 = 1498,\n\tFN_SEL_SSI7_2___2 = 1499,\n\tFN_SEL_SSI6_0___3 = 1500,\n\tFN_SEL_SSI6_1___3 = 1501,\n\tFN_SEL_SSI5_0___3 = 1502,\n\tFN_SEL_SSI5_1___3 = 1503,\n\tFN_SEL_SSI5_2 = 1504,\n\tFN_SEL_VI3_0 = 1505,\n\tFN_SEL_VI3_1 = 1506,\n\tFN_SEL_VI2_0 = 1507,\n\tFN_SEL_VI2_1 = 1508,\n\tFN_SEL_VI1_0___3 = 1509,\n\tFN_SEL_VI1_1___3 = 1510,\n\tFN_SEL_VI0_0___2 = 1511,\n\tFN_SEL_VI0_1___2 = 1512,\n\tFN_SEL_TSIF1_0 = 1513,\n\tFN_SEL_TSIF1_1 = 1514,\n\tFN_SEL_TSIF1_2 = 1515,\n\tFN_SEL_LBS_0___3 = 1516,\n\tFN_SEL_LBS_1___3 = 1517,\n\tFN_SEL_TSIF0_0___3 = 1518,\n\tFN_SEL_TSIF0_1___3 = 1519,\n\tFN_SEL_TSIF0_2___3 = 1520,\n\tFN_SEL_TSIF0_3___3 = 1521,\n\tFN_SEL_SOF3_0 = 1522,\n\tFN_SEL_SOF3_1 = 1523,\n\tFN_SEL_SOF0_0___2 = 1524,\n\tFN_SEL_SOF0_1___2 = 1525,\n\tFN_SEL_TMU1_0___4 = 1526,\n\tFN_SEL_TMU1_1___4 = 1527,\n\tFN_SEL_HSCIF1_0___5 = 1528,\n\tFN_SEL_HSCIF1_1___5 = 1529,\n\tFN_SEL_SCIFCLK_0___2 = 1530,\n\tFN_SEL_SCIFCLK_1___2 = 1531,\n\tFN_SEL_CAN0_0___5 = 1532,\n\tFN_SEL_CAN0_1___5 = 1533,\n\tFN_SEL_CAN0_2___4 = 1534,\n\tFN_SEL_CAN0_3___4 = 1535,\n\tFN_SEL_CANCLK_0___4 = 1536,\n\tFN_SEL_CANCLK_1___4 = 1537,\n\tFN_SEL_SCIFA2_0___3 = 1538,\n\tFN_SEL_SCIFA2_1___3 = 1539,\n\tFN_SEL_SCIFA2_2 = 1540,\n\tFN_SEL_CAN1_0___4 = 1541,\n\tFN_SEL_CAN1_1___4 = 1542,\n\tFN_SEL_SCIF2_0___5 = 1543,\n\tFN_SEL_SCIF2_1___5 = 1544,\n\tFN_SEL_ADI_0___2 = 1545,\n\tFN_SEL_ADI_1___2 = 1546,\n\tFN_SEL_SSP_0___2 = 1547,\n\tFN_SEL_SSP_1___2 = 1548,\n\tFN_SEL_FM_0___2 = 1549,\n\tFN_SEL_FM_1___2 = 1550,\n\tFN_SEL_FM_2___2 = 1551,\n\tFN_SEL_FM_3___2 = 1552,\n\tFN_SEL_FM_4___2 = 1553,\n\tFN_SEL_FM_5 = 1554,\n\tFN_SEL_FM_6 = 1555,\n\tFN_SEL_HSCIF0_0___5 = 1556,\n\tFN_SEL_HSCIF0_1___5 = 1557,\n\tFN_SEL_HSCIF0_2___2 = 1558,\n\tFN_SEL_HSCIF0_3 = 1559,\n\tFN_SEL_HSCIF0_4 = 1560,\n\tFN_SEL_HSCIF0_5 = 1561,\n\tFN_SEL_GPS_0___3 = 1562,\n\tFN_SEL_GPS_1___3 = 1563,\n\tFN_SEL_GPS_2___3 = 1564,\n\tFN_SEL_SIM_0___3 = 1565,\n\tFN_SEL_SIM_1___3 = 1566,\n\tFN_SEL_SIM_2 = 1567,\n\tFN_SEL_SSI8_0___5 = 1568,\n\tFN_SEL_SSI8_1___5 = 1569,\n\tFN_SEL_SSI8_2___2 = 1570,\n\tFN_SEL_IICDVFS_0 = 1571,\n\tFN_SEL_IICDVFS_1 = 1572,\n\tFN_SEL_IIC0_0___3 = 1573,\n\tFN_SEL_IIC0_1___3 = 1574,\n\tFN_SEL_IEB_0___3 = 1575,\n\tFN_SEL_IEB_1___3 = 1576,\n\tFN_SEL_IEB_2___3 = 1577,\n\tFN_SEL_IIC2_0 = 1578,\n\tFN_SEL_IIC2_1 = 1579,\n\tFN_SEL_IIC2_2 = 1580,\n\tFN_SEL_IIC2_3 = 1581,\n\tFN_SEL_IIC2_4 = 1582,\n\tFN_SEL_IIC1_0___2 = 1583,\n\tFN_SEL_IIC1_1___2 = 1584,\n\tFN_SEL_IIC1_2___2 = 1585,\n\tFN_SEL_I2C2_0___3 = 1586,\n\tFN_SEL_I2C2_1___3 = 1587,\n\tFN_SEL_I2C2_2___3 = 1588,\n\tFN_SEL_I2C2_3___3 = 1589,\n\tFN_SEL_I2C2_4 = 1590,\n\tFN_SEL_I2C1_0___3 = 1591,\n\tFN_SEL_I2C1_1___3 = 1592,\n\tFN_SEL_I2C1_2___3 = 1593,\n\tPINMUX_FUNCTION_END___11 = 1594,\n\tPINMUX_MARK_BEGIN___11 = 1595,\n\tVI1_DATA7_VI1_B7_MARK___2 = 1596,\n\tUSB0_PWEN_MARK___4 = 1597,\n\tUSB0_OVC_VBUS_MARK = 1598,\n\tUSB2_PWEN_MARK = 1599,\n\tUSB2_OVC_MARK = 1600,\n\tAVS1_MARK___4 = 1601,\n\tAVS2_MARK___4 = 1602,\n\tDU_DOTCLKIN0_MARK = 1603,\n\tDU_DOTCLKIN2_MARK = 1604,\n\tD0_MARK___7 = 1605,\n\tMSIOF3_SCK_B_MARK = 1606,\n\tVI3_DATA0_MARK___2 = 1607,\n\tVI0_G4_MARK___6 = 1608,\n\tVI0_G4_B_MARK = 1609,\n\tD1_MARK___7 = 1610,\n\tMSIOF3_SYNC_B_MARK = 1611,\n\tVI3_DATA1_MARK___2 = 1612,\n\tVI0_G5_MARK___6 = 1613,\n\tVI0_G5_B_MARK = 1614,\n\tD2_MARK___7 = 1615,\n\tMSIOF3_RXD_B_MARK = 1616,\n\tVI3_DATA2_MARK___2 = 1617,\n\tVI0_G6_MARK___5 = 1618,\n\tVI0_G6_B_MARK = 1619,\n\tD3_MARK___7 = 1620,\n\tMSIOF3_TXD_B_MARK = 1621,\n\tVI3_DATA3_MARK___2 = 1622,\n\tVI0_G7_MARK___5 = 1623,\n\tVI0_G7_B_MARK = 1624,\n\tD4_MARK___7 = 1625,\n\tSCIFB1_RXD_F_MARK = 1626,\n\tSCIFB0_RXD_C_MARK___2 = 1627,\n\tVI3_DATA4_MARK___2 = 1628,\n\tVI0_R0_MARK___5 = 1629,\n\tVI0_R0_B_MARK___2 = 1630,\n\tRX0_B_MARK___5 = 1631,\n\tD5_MARK___7 = 1632,\n\tSCIFB1_TXD_F_MARK = 1633,\n\tSCIFB0_TXD_C_MARK___2 = 1634,\n\tVI3_DATA5_MARK___2 = 1635,\n\tVI0_R1_MARK___5 = 1636,\n\tVI0_R1_B_MARK___2 = 1637,\n\tTX0_B_MARK___5 = 1638,\n\tD6_MARK___7 = 1639,\n\tIIC2_SCL_C_MARK = 1640,\n\tVI3_DATA6_MARK___2 = 1641,\n\tVI0_R2_MARK___5 = 1642,\n\tVI0_R2_B_MARK___2 = 1643,\n\tI2C2_SCL_C_MARK___3 = 1644,\n\tD7_MARK___7 = 1645,\n\tAD_DI_B_MARK = 1646,\n\tIIC2_SDA_C_MARK = 1647,\n\tVI3_DATA7_MARK___2 = 1648,\n\tVI0_R3_MARK___5 = 1649,\n\tVI0_R3_B_MARK___2 = 1650,\n\tI2C2_SDA_C_MARK___3 = 1651,\n\tTCLK1_MARK___6 = 1652,\n\tD8_MARK___7 = 1653,\n\tSCIFA1_SCK_C_MARK___2 = 1654,\n\tAVB_TXD0_MARK___5 = 1655,\n\tVI0_G0_MARK___5 = 1656,\n\tVI0_G0_B_MARK = 1657,\n\tVI2_DATA0_VI2_B0_MARK___2 = 1658,\n\tD9_MARK___7 = 1659,\n\tSCIFA1_RXD_C_MARK___3 = 1660,\n\tAVB_TXD1_MARK___5 = 1661,\n\tVI0_G1_MARK___5 = 1662,\n\tVI0_G1_B_MARK = 1663,\n\tVI2_DATA1_VI2_B1_MARK___2 = 1664,\n\tD10_MARK___7 = 1665,\n\tSCIFA1_TXD_C_MARK___3 = 1666,\n\tAVB_TXD2_MARK___5 = 1667,\n\tVI0_G2_MARK___6 = 1668,\n\tVI0_G2_B_MARK = 1669,\n\tVI2_DATA2_VI2_B2_MARK___2 = 1670,\n\tD11_MARK___7 = 1671,\n\tSCIFA1_CTS_N_C_MARK = 1672,\n\tAVB_TXD3_MARK___5 = 1673,\n\tVI0_G3_MARK___6 = 1674,\n\tVI0_G3_B_MARK = 1675,\n\tVI2_DATA3_VI2_B3_MARK___2 = 1676,\n\tD12_MARK___6 = 1677,\n\tSCIFA1_RTS_N_C_MARK = 1678,\n\tAVB_TXD4_MARK___5 = 1679,\n\tVI0_HSYNC_N_MARK___5 = 1680,\n\tVI0_HSYNC_N_B_MARK = 1681,\n\tVI2_DATA4_VI2_B4_MARK___2 = 1682,\n\tD13_MARK___6 = 1683,\n\tAVB_TXD5_MARK___5 = 1684,\n\tVI0_VSYNC_N_MARK___5 = 1685,\n\tVI0_VSYNC_N_B_MARK = 1686,\n\tVI2_DATA5_VI2_B5_MARK___2 = 1687,\n\tD14_MARK___6 = 1688,\n\tSCIFB1_RXD_C_MARK___2 = 1689,\n\tAVB_TXD6_MARK___5 = 1690,\n\tRX1_B_MARK___5 = 1691,\n\tVI0_CLKENB_MARK___7 = 1692,\n\tVI0_CLKENB_B_MARK = 1693,\n\tVI2_DATA6_VI2_B6_MARK___2 = 1694,\n\tD15_MARK___6 = 1695,\n\tSCIFB1_TXD_C_MARK___2 = 1696,\n\tAVB_TXD7_MARK___5 = 1697,\n\tTX1_B_MARK___5 = 1698,\n\tVI0_FIELD_MARK___7 = 1699,\n\tVI0_FIELD_B_MARK = 1700,\n\tVI2_DATA7_VI2_B7_MARK___2 = 1701,\n\tA0_MARK___10 = 1702,\n\tPWM3_MARK___6 = 1703,\n\tA1_MARK___8 = 1704,\n\tPWM4_MARK___6 = 1705,\n\tA2_MARK___8 = 1706,\n\tPWM5_MARK___5 = 1707,\n\tMSIOF1_SS1_B_MARK___3 = 1708,\n\tA3_MARK___8 = 1709,\n\tPWM6_MARK___5 = 1710,\n\tMSIOF1_SS2_B_MARK___3 = 1711,\n\tA4_MARK___7 = 1712,\n\tMSIOF1_TXD_B_MARK___4 = 1713,\n\tTPU0TO0_MARK___5 = 1714,\n\tA5_MARK___7 = 1715,\n\tSCIFA1_TXD_B_MARK___3 = 1716,\n\tTPU0TO1_MARK___5 = 1717,\n\tA6_MARK___8 = 1718,\n\tSCIFA1_RTS_N_B_MARK = 1719,\n\tTPU0TO2_MARK___4 = 1720,\n\tA7_MARK___8 = 1721,\n\tSCIFA1_SCK_B_MARK___3 = 1722,\n\tAUDIO_CLKOUT_B_MARK___5 = 1723,\n\tTPU0TO3_MARK___5 = 1724,\n\tA8_MARK___8 = 1725,\n\tSCIFA1_RXD_B_MARK___3 = 1726,\n\tSSI_SCK5_B_MARK___3 = 1727,\n\tVI0_R4_MARK___5 = 1728,\n\tVI0_R4_B_MARK___2 = 1729,\n\tSCIFB2_RXD_C_MARK___2 = 1730,\n\tRX2_B_MARK___5 = 1731,\n\tVI2_DATA0_VI2_B0_B_MARK = 1732,\n\tA9_MARK___8 = 1733,\n\tSCIFA1_CTS_N_B_MARK = 1734,\n\tSSI_WS5_B_MARK___3 = 1735,\n\tVI0_R5_MARK___5 = 1736,\n\tVI0_R5_B_MARK___2 = 1737,\n\tSCIFB2_TXD_C_MARK___2 = 1738,\n\tTX2_B_MARK___5 = 1739,\n\tVI2_DATA1_VI2_B1_B_MARK = 1740,\n\tA10_MARK___8 = 1741,\n\tSSI_SDATA5_B_MARK___3 = 1742,\n\tMSIOF2_SYNC_MARK___4 = 1743,\n\tVI0_R6_MARK___5 = 1744,\n\tVI0_R6_B_MARK = 1745,\n\tVI2_DATA2_VI2_B2_B_MARK = 1746,\n\tA11_MARK___8 = 1747,\n\tSCIFB2_CTS_N_B_MARK___2 = 1748,\n\tMSIOF2_SCK_MARK___4 = 1749,\n\tVI1_R0_MARK___2 = 1750,\n\tVI1_R0_B_MARK___2 = 1751,\n\tVI2_G0_MARK___2 = 1752,\n\tVI2_DATA3_VI2_B3_B_MARK = 1753,\n\tA12_MARK___8 = 1754,\n\tSCIFB2_RXD_B_MARK___2 = 1755,\n\tMSIOF2_TXD_MARK___6 = 1756,\n\tVI1_R1_MARK___2 = 1757,\n\tVI1_R1_B_MARK___2 = 1758,\n\tVI2_G1_MARK___2 = 1759,\n\tVI2_DATA4_VI2_B4_B_MARK = 1760,\n\tA13_MARK___8 = 1761,\n\tSCIFB2_RTS_N_B_MARK___2 = 1762,\n\tEX_WAIT2_MARK___4 = 1763,\n\tMSIOF2_RXD_MARK___5 = 1764,\n\tVI1_R2_MARK___2 = 1765,\n\tVI1_R2_B_MARK___2 = 1766,\n\tVI2_G2_MARK___2 = 1767,\n\tVI2_DATA5_VI2_B5_B_MARK = 1768,\n\tA14_MARK___8 = 1769,\n\tSCIFB2_TXD_B_MARK___2 = 1770,\n\tATACS11_N_MARK___3 = 1771,\n\tMSIOF2_SS1_MARK___6 = 1772,\n\tA15_MARK___8 = 1773,\n\tSCIFB2_SCK_B_MARK___2 = 1774,\n\tATARD1_N_MARK___3 = 1775,\n\tMSIOF2_SS2_MARK___6 = 1776,\n\tA16_MARK___8 = 1777,\n\tATAWR1_N_MARK___3 = 1778,\n\tA17_MARK___9 = 1779,\n\tAD_DO_B_MARK = 1780,\n\tATADIR1_N_MARK___3 = 1781,\n\tA18_MARK___9 = 1782,\n\tAD_CLK_B_MARK = 1783,\n\tATAG1_N_MARK___3 = 1784,\n\tA19_MARK___9 = 1785,\n\tAD_NCS_N_B_MARK = 1786,\n\tATACS01_N_MARK___3 = 1787,\n\tEX_WAIT0_B_MARK = 1788,\n\tA20_MARK___9 = 1789,\n\tSPCLK_MARK___4 = 1790,\n\tVI1_R3_MARK___2 = 1791,\n\tVI1_R3_B_MARK___2 = 1792,\n\tVI2_G4_MARK___2 = 1793,\n\tA21_MARK___9 = 1794,\n\tMOSI_IO0_MARK___4 = 1795,\n\tVI1_R4_MARK___2 = 1796,\n\tVI1_R4_B_MARK___2 = 1797,\n\tVI2_G5_MARK___2 = 1798,\n\tA22_MARK___9 = 1799,\n\tMISO_IO1_MARK___4 = 1800,\n\tVI1_R5_MARK___2 = 1801,\n\tVI1_R5_B_MARK___2 = 1802,\n\tVI2_G6_MARK___2 = 1803,\n\tA23_MARK___9 = 1804,\n\tIO2_MARK___4 = 1805,\n\tVI1_G7_MARK___2 = 1806,\n\tVI1_G7_B_MARK___2 = 1807,\n\tVI2_G7_MARK___2 = 1808,\n\tA24_MARK___9 = 1809,\n\tIO3_MARK___4 = 1810,\n\tVI1_R7_MARK___2 = 1811,\n\tVI1_R7_B_MARK___2 = 1812,\n\tVI2_CLKENB_MARK___4 = 1813,\n\tVI2_CLKENB_B_MARK = 1814,\n\tA25_MARK___9 = 1815,\n\tSSL_MARK___4 = 1816,\n\tVI1_G6_MARK___2 = 1817,\n\tVI1_G6_B_MARK___2 = 1818,\n\tVI2_FIELD_MARK___4 = 1819,\n\tVI2_FIELD_B_MARK = 1820,\n\tCS0_N_MARK___6 = 1821,\n\tVI1_R6_MARK___2 = 1822,\n\tVI1_R6_B_MARK___2 = 1823,\n\tVI2_G3_MARK___2 = 1824,\n\tMSIOF0_SS2_B_MARK___2 = 1825,\n\tCS1_N_A26_MARK___5 = 1826,\n\tSPEEDIN_MARK___5 = 1827,\n\tVI0_R7_MARK___5 = 1828,\n\tVI0_R7_B_MARK = 1829,\n\tVI2_CLK_MARK___4 = 1830,\n\tVI2_CLK_B_MARK = 1831,\n\tEX_CS0_N_MARK___4 = 1832,\n\tHRX1_B_MARK___5 = 1833,\n\tVI1_G5_MARK___2 = 1834,\n\tVI1_G5_B_MARK___2 = 1835,\n\tVI2_R0_MARK___2 = 1836,\n\tHTX0_B_MARK___5 = 1837,\n\tMSIOF0_SS1_B_MARK___2 = 1838,\n\tEX_CS1_N_MARK___4 = 1839,\n\tGPS_CLK_MARK___3 = 1840,\n\tHCTS1_N_B_MARK___2 = 1841,\n\tVI1_FIELD_MARK___7 = 1842,\n\tVI1_FIELD_B_MARK___2 = 1843,\n\tVI2_R1_MARK___2 = 1844,\n\tEX_CS2_N_MARK___4 = 1845,\n\tGPS_SIGN_MARK___3 = 1846,\n\tHRTS1_N_B_MARK___2 = 1847,\n\tVI3_CLKENB_MARK___3 = 1848,\n\tVI1_G0_MARK___2 = 1849,\n\tVI1_G0_B_MARK___2 = 1850,\n\tVI2_R2_MARK___2 = 1851,\n\tEX_CS3_N_MARK___4 = 1852,\n\tGPS_MAG_MARK___3 = 1853,\n\tVI3_FIELD_MARK___3 = 1854,\n\tVI1_G1_MARK___2 = 1855,\n\tVI1_G1_B_MARK___2 = 1856,\n\tVI2_R3_MARK___2 = 1857,\n\tEX_CS4_N_MARK___4 = 1858,\n\tMSIOF1_SCK_B_MARK___4 = 1859,\n\tVI3_HSYNC_N_MARK___2 = 1860,\n\tVI2_HSYNC_N_MARK___3 = 1861,\n\tIIC1_SCL_MARK___3 = 1862,\n\tVI2_HSYNC_N_B_MARK = 1863,\n\tINTC_EN0_N_MARK = 1864,\n\tI2C1_SCL_MARK___3 = 1865,\n\tEX_CS5_N_MARK___4 = 1866,\n\tCAN0_RX_MARK___5 = 1867,\n\tMSIOF1_RXD_B_MARK___4 = 1868,\n\tVI3_VSYNC_N_MARK___2 = 1869,\n\tVI1_G2_MARK___2 = 1870,\n\tVI1_G2_B_MARK___2 = 1871,\n\tVI2_R4_MARK___2 = 1872,\n\tIIC1_SDA_MARK___3 = 1873,\n\tINTC_EN1_N_MARK = 1874,\n\tI2C1_SDA_MARK___3 = 1875,\n\tBS_N_MARK___5 = 1876,\n\tIETX_MARK___5 = 1877,\n\tHTX1_B_MARK___5 = 1878,\n\tCAN1_TX_MARK___5 = 1879,\n\tDRACK0_MARK___7 = 1880,\n\tIETX_C_MARK___3 = 1881,\n\tRD_N_MARK___6 = 1882,\n\tCAN0_TX_MARK___5 = 1883,\n\tSCIFA0_SCK_B_MARK = 1884,\n\tRD_WR_N_MARK___5 = 1885,\n\tVI1_G3_MARK___2 = 1886,\n\tVI1_G3_B_MARK___2 = 1887,\n\tVI2_R5_MARK___2 = 1888,\n\tSCIFA0_RXD_B_MARK___3 = 1889,\n\tWE0_N_MARK___6 = 1890,\n\tIECLK_MARK___5 = 1891,\n\tCAN_CLK_MARK___5 = 1892,\n\tVI2_VSYNC_N_MARK___3 = 1893,\n\tSCIFA0_TXD_B_MARK___3 = 1894,\n\tVI2_VSYNC_N_B_MARK = 1895,\n\tWE1_N_MARK___6 = 1896,\n\tIERX_MARK___5 = 1897,\n\tCAN1_RX_MARK___5 = 1898,\n\tVI1_G4_MARK___2 = 1899,\n\tVI1_G4_B_MARK___2 = 1900,\n\tVI2_R6_MARK___2 = 1901,\n\tSCIFA0_CTS_N_B_MARK = 1902,\n\tIERX_C_MARK___3 = 1903,\n\tEX_WAIT0_MARK___6 = 1904,\n\tIRQ3_MARK___7 = 1905,\n\tVI3_CLK_MARK___3 = 1906,\n\tSCIFA0_RTS_N_B_MARK = 1907,\n\tHRX0_B_MARK___5 = 1908,\n\tMSIOF0_SCK_B_MARK___3 = 1909,\n\tDREQ0_N_MARK___4 = 1910,\n\tVI1_HSYNC_N_MARK___5 = 1911,\n\tVI1_HSYNC_N_B_MARK___2 = 1912,\n\tVI2_R7_MARK___2 = 1913,\n\tSSI_SCK78_C_MARK___2 = 1914,\n\tSSI_WS78_B_MARK___5 = 1915,\n\tDACK0_MARK___9 = 1916,\n\tIRQ0_MARK___8 = 1917,\n\tSSI_SCK6_B_MARK___3 = 1918,\n\tVI1_VSYNC_N_MARK___5 = 1919,\n\tVI1_VSYNC_N_B_MARK___2 = 1920,\n\tSSI_WS78_C_MARK___2 = 1921,\n\tDREQ1_N_MARK___4 = 1922,\n\tVI1_CLKENB_MARK___7 = 1923,\n\tVI1_CLKENB_B_MARK___2 = 1924,\n\tSSI_SDATA7_C_MARK___2 = 1925,\n\tSSI_SCK78_B_MARK___5 = 1926,\n\tDACK1_MARK___8 = 1927,\n\tIRQ1_MARK___8 = 1928,\n\tSSI_WS6_B_MARK___3 = 1929,\n\tSSI_SDATA8_C_MARK___2 = 1930,\n\tDREQ2_N_MARK___3 = 1931,\n\tHSCK1_B_MARK___3 = 1932,\n\tHCTS0_N_B_MARK___2 = 1933,\n\tMSIOF0_TXD_B_MARK___3 = 1934,\n\tDACK2_MARK___6 = 1935,\n\tIRQ2_MARK___7 = 1936,\n\tSSI_SDATA6_B_MARK___3 = 1937,\n\tHRTS0_N_B_MARK___2 = 1938,\n\tMSIOF0_RXD_B_MARK___3 = 1939,\n\tETH_CRS_DV_MARK___6 = 1940,\n\tSTP_ISCLK_0_B_MARK___2 = 1941,\n\tTS_SDEN0_D_MARK___2 = 1942,\n\tGLO_Q0_C_MARK___2 = 1943,\n\tIIC2_SCL_E_MARK = 1944,\n\tI2C2_SCL_E_MARK___2 = 1945,\n\tETH_RX_ER_MARK___6 = 1946,\n\tSTP_ISD_0_B_MARK___2 = 1947,\n\tTS_SPSYNC0_D_MARK___2 = 1948,\n\tGLO_Q1_C_MARK___2 = 1949,\n\tIIC2_SDA_E_MARK = 1950,\n\tI2C2_SDA_E_MARK___2 = 1951,\n\tETH_RXD0_MARK___6 = 1952,\n\tSTP_ISEN_0_B_MARK___2 = 1953,\n\tTS_SDAT0_D_MARK = 1954,\n\tGLO_I0_C_MARK___2 = 1955,\n\tSCIFB1_SCK_G_MARK = 1956,\n\tSCK1_E_MARK = 1957,\n\tETH_RXD1_MARK___6 = 1958,\n\tHRX0_E_MARK = 1959,\n\tSTP_ISSYNC_0_B_MARK___2 = 1960,\n\tTS_SCK0_D_MARK___2 = 1961,\n\tGLO_I1_C_MARK___2 = 1962,\n\tSCIFB1_RXD_G_MARK = 1963,\n\tRX1_E_MARK = 1964,\n\tETH_LINK_MARK___6 = 1965,\n\tHTX0_E_MARK = 1966,\n\tSTP_IVCXO27_0_B_MARK___2 = 1967,\n\tSCIFB1_TXD_G_MARK = 1968,\n\tTX1_E_MARK = 1969,\n\tETH_REF_CLK_MARK___3 = 1970,\n\tHCTS0_N_E_MARK = 1971,\n\tSTP_IVCXO27_1_B_MARK = 1972,\n\tHRX0_F_MARK = 1973,\n\tETH_MDIO_MARK___6 = 1974,\n\tHRTS0_N_E_MARK = 1975,\n\tSIM0_D_C_MARK = 1976,\n\tHCTS0_N_F_MARK = 1977,\n\tETH_TXD1_MARK___6 = 1978,\n\tHTX0_F_MARK = 1979,\n\tBPFCLK_G_MARK = 1980,\n\tETH_TX_EN_MARK___6 = 1981,\n\tSIM0_CLK_C_MARK = 1982,\n\tHRTS0_N_F_MARK = 1983,\n\tETH_MAGIC_MARK___6 = 1984,\n\tSIM0_RST_C_MARK = 1985,\n\tETH_TXD0_MARK___6 = 1986,\n\tSTP_ISCLK_1_B_MARK = 1987,\n\tTS_SDEN1_C_MARK = 1988,\n\tGLO_SCLK_C_MARK___2 = 1989,\n\tETH_MDC_MARK___6 = 1990,\n\tSTP_ISD_1_B_MARK = 1991,\n\tTS_SPSYNC1_C_MARK = 1992,\n\tGLO_SDATA_C_MARK___2 = 1993,\n\tPWM0_MARK___6 = 1994,\n\tSCIFA2_SCK_C_MARK = 1995,\n\tSTP_ISEN_1_B_MARK = 1996,\n\tTS_SDAT1_C_MARK = 1997,\n\tGLO_SS_C_MARK___2 = 1998,\n\tPWM1_MARK___7 = 1999,\n\tSCIFA2_TXD_C_MARK = 2000,\n\tSTP_ISSYNC_1_B_MARK = 2001,\n\tTS_SCK1_C_MARK = 2002,\n\tGLO_RFON_C_MARK___2 = 2003,\n\tPCMOE_N_MARK = 2004,\n\tPWM2_MARK___6 = 2005,\n\tPWMFSW0_MARK___2 = 2006,\n\tSCIFA2_RXD_C_MARK = 2007,\n\tPCMWE_N_MARK = 2008,\n\tIECLK_C_MARK___3 = 2009,\n\tDU_DOTCLKIN1_MARK = 2010,\n\tAUDIO_CLKC_MARK___5 = 2011,\n\tAUDIO_CLKOUT_C_MARK___4 = 2012,\n\tVI0_CLK_MARK___7 = 2013,\n\tATACS00_N_MARK___3 = 2014,\n\tAVB_RXD1_MARK___5 = 2015,\n\tVI0_DATA0_VI0_B0_MARK___6 = 2016,\n\tATACS10_N_MARK___3 = 2017,\n\tAVB_RXD2_MARK___5 = 2018,\n\tVI0_DATA1_VI0_B1_MARK___6 = 2019,\n\tATARD0_N_MARK___3 = 2020,\n\tAVB_RXD3_MARK___5 = 2021,\n\tVI0_DATA2_VI0_B2_MARK___6 = 2022,\n\tATAWR0_N_MARK___3 = 2023,\n\tAVB_RXD4_MARK___5 = 2024,\n\tVI0_DATA3_VI0_B3_MARK___6 = 2025,\n\tATADIR0_N_MARK___3 = 2026,\n\tAVB_RXD5_MARK___5 = 2027,\n\tVI0_DATA4_VI0_B4_MARK___6 = 2028,\n\tATAG0_N_MARK___3 = 2029,\n\tAVB_RXD6_MARK___5 = 2030,\n\tVI0_DATA5_VI0_B5_MARK___6 = 2031,\n\tEX_WAIT1_MARK___5 = 2032,\n\tAVB_RXD7_MARK___5 = 2033,\n\tVI0_DATA6_VI0_B6_MARK___5 = 2034,\n\tAVB_RX_ER_MARK___5 = 2035,\n\tVI0_DATA7_VI0_B7_MARK___5 = 2036,\n\tAVB_RX_CLK_MARK___5 = 2037,\n\tVI1_CLK_MARK___7 = 2038,\n\tAVB_RX_DV_MARK___5 = 2039,\n\tVI1_DATA0_VI1_B0_MARK___2 = 2040,\n\tSCIFA1_SCK_D_MARK = 2041,\n\tAVB_CRS_MARK___5 = 2042,\n\tVI1_DATA1_VI1_B1_MARK___2 = 2043,\n\tSCIFA1_RXD_D_MARK = 2044,\n\tAVB_MDC_MARK___5 = 2045,\n\tVI1_DATA2_VI1_B2_MARK___2 = 2046,\n\tSCIFA1_TXD_D_MARK = 2047,\n\tAVB_MDIO_MARK___5 = 2048,\n\tVI1_DATA3_VI1_B3_MARK___2 = 2049,\n\tSCIFA1_CTS_N_D_MARK = 2050,\n\tAVB_GTX_CLK_MARK___5 = 2051,\n\tVI1_DATA4_VI1_B4_MARK___2 = 2052,\n\tSCIFA1_RTS_N_D_MARK = 2053,\n\tAVB_MAGIC_MARK___5 = 2054,\n\tVI1_DATA5_VI1_B5_MARK___2 = 2055,\n\tAVB_PHY_INT_MARK___5 = 2056,\n\tVI1_DATA6_VI1_B6_MARK___2 = 2057,\n\tAVB_GTXREFCLK_MARK___5 = 2058,\n\tSD0_CLK_MARK___7 = 2059,\n\tVI1_DATA0_VI1_B0_B_MARK = 2060,\n\tSD0_CMD_MARK___7 = 2061,\n\tSCIFB1_SCK_B_MARK___2 = 2062,\n\tVI1_DATA1_VI1_B1_B_MARK = 2063,\n\tSD0_DAT0_MARK___5 = 2064,\n\tSCIFB1_RXD_B_MARK___2 = 2065,\n\tVI1_DATA2_VI1_B2_B_MARK = 2066,\n\tSD0_DAT1_MARK___5 = 2067,\n\tSCIFB1_TXD_B_MARK___2 = 2068,\n\tVI1_DATA3_VI1_B3_B_MARK = 2069,\n\tSD0_DAT2_MARK___5 = 2070,\n\tSCIFB1_CTS_N_B_MARK = 2071,\n\tVI1_DATA4_VI1_B4_B_MARK = 2072,\n\tSD0_DAT3_MARK___5 = 2073,\n\tSCIFB1_RTS_N_B_MARK = 2074,\n\tVI1_DATA5_VI1_B5_B_MARK = 2075,\n\tSD0_CD_MARK___7 = 2076,\n\tMMC0_D6_MARK___3 = 2077,\n\tTS_SDEN0_B_MARK___3 = 2078,\n\tUSB0_EXTP_MARK = 2079,\n\tGLO_SCLK_MARK___2 = 2080,\n\tVI1_DATA6_VI1_B6_B_MARK = 2081,\n\tIIC1_SCL_B_MARK___2 = 2082,\n\tI2C1_SCL_B_MARK___3 = 2083,\n\tVI2_DATA6_VI2_B6_B_MARK = 2084,\n\tSD0_WP_MARK___7 = 2085,\n\tMMC0_D7_MARK___3 = 2086,\n\tTS_SPSYNC0_B_MARK___3 = 2087,\n\tUSB0_IDIN_MARK = 2088,\n\tGLO_SDATA_MARK___2 = 2089,\n\tVI1_DATA7_VI1_B7_B_MARK = 2090,\n\tIIC1_SDA_B_MARK___2 = 2091,\n\tI2C1_SDA_B_MARK___3 = 2092,\n\tVI2_DATA7_VI2_B7_B_MARK = 2093,\n\tSD1_CLK_MARK___4 = 2094,\n\tAVB_TX_EN_MARK___5 = 2095,\n\tSD1_CMD_MARK___4 = 2096,\n\tAVB_TX_ER_MARK___5 = 2097,\n\tSCIFB0_SCK_B_MARK___2 = 2098,\n\tSD1_DAT0_MARK___2 = 2099,\n\tAVB_TX_CLK_MARK___5 = 2100,\n\tSCIFB0_RXD_B_MARK___2 = 2101,\n\tSD1_DAT1_MARK___2 = 2102,\n\tAVB_LINK_MARK___5 = 2103,\n\tSCIFB0_TXD_B_MARK___2 = 2104,\n\tSD1_DAT2_MARK___2 = 2105,\n\tAVB_COL_MARK___5 = 2106,\n\tSCIFB0_CTS_N_B_MARK___2 = 2107,\n\tSD1_DAT3_MARK___2 = 2108,\n\tAVB_RXD0_MARK___5 = 2109,\n\tSCIFB0_RTS_N_B_MARK___2 = 2110,\n\tSD1_CD_MARK___5 = 2111,\n\tMMC1_D6_MARK___2 = 2112,\n\tTS_SDEN1_MARK___3 = 2113,\n\tUSB1_EXTP_MARK = 2114,\n\tGLO_SS_MARK___2 = 2115,\n\tVI0_CLK_B_MARK = 2116,\n\tIIC2_SCL_D_MARK = 2117,\n\tI2C2_SCL_D_MARK___3 = 2118,\n\tSIM0_CLK_B_MARK = 2119,\n\tVI3_CLK_B_MARK = 2120,\n\tSD1_WP_MARK___5 = 2121,\n\tMMC1_D7_MARK___2 = 2122,\n\tTS_SPSYNC1_MARK___3 = 2123,\n\tUSB1_IDIN_MARK = 2124,\n\tGLO_RFON_MARK___2 = 2125,\n\tVI1_CLK_B_MARK___2 = 2126,\n\tIIC2_SDA_D_MARK = 2127,\n\tI2C2_SDA_D_MARK___3 = 2128,\n\tSIM0_D_B_MARK___2 = 2129,\n\tSD2_CLK_MARK___5 = 2130,\n\tMMC0_CLK_MARK___2 = 2131,\n\tSIM0_CLK_MARK___3 = 2132,\n\tVI0_DATA0_VI0_B0_B_MARK = 2133,\n\tTS_SDEN0_C_MARK___2 = 2134,\n\tGLO_SCLK_B_MARK___2 = 2135,\n\tVI3_DATA0_B_MARK = 2136,\n\tSD2_CMD_MARK___5 = 2137,\n\tMMC0_CMD_MARK___2 = 2138,\n\tSIM0_D_MARK___2 = 2139,\n\tVI0_DATA1_VI0_B1_B_MARK = 2140,\n\tSCIFB1_SCK_E_MARK = 2141,\n\tSCK1_D_MARK = 2142,\n\tTS_SPSYNC0_C_MARK___2 = 2143,\n\tGLO_SDATA_B_MARK___2 = 2144,\n\tVI3_DATA1_B_MARK = 2145,\n\tSD2_DAT0_MARK___3 = 2146,\n\tMMC0_D0_MARK___2 = 2147,\n\tFMCLK_B_MARK___4 = 2148,\n\tVI0_DATA2_VI0_B2_B_MARK = 2149,\n\tSCIFB1_RXD_E_MARK = 2150,\n\tRX1_D_MARK___4 = 2151,\n\tTS_SDAT0_C_MARK = 2152,\n\tGLO_SS_B_MARK___2 = 2153,\n\tVI3_DATA2_B_MARK = 2154,\n\tSD2_DAT1_MARK___3 = 2155,\n\tMMC0_D1_MARK___2 = 2156,\n\tFMIN_B_MARK___4 = 2157,\n\tVI0_DATA3_VI0_B3_B_MARK = 2158,\n\tSCIFB1_TXD_E_MARK = 2159,\n\tTX1_D_MARK___4 = 2160,\n\tTS_SCK0_C_MARK___2 = 2161,\n\tGLO_RFON_B_MARK___2 = 2162,\n\tVI3_DATA3_B_MARK = 2163,\n\tSD2_DAT2_MARK___3 = 2164,\n\tMMC0_D2_MARK___2 = 2165,\n\tBPFCLK_B_MARK___4 = 2166,\n\tVI0_DATA4_VI0_B4_B_MARK = 2167,\n\tHRX0_D_MARK = 2168,\n\tTS_SDEN1_B_MARK = 2169,\n\tGLO_Q0_B_MARK___2 = 2170,\n\tVI3_DATA4_B_MARK = 2171,\n\tSD2_DAT3_MARK___3 = 2172,\n\tMMC0_D3_MARK___2 = 2173,\n\tSIM0_RST_MARK___3 = 2174,\n\tVI0_DATA5_VI0_B5_B_MARK = 2175,\n\tHTX0_D_MARK = 2176,\n\tTS_SPSYNC1_B_MARK = 2177,\n\tGLO_Q1_B_MARK___2 = 2178,\n\tVI3_DATA5_B_MARK = 2179,\n\tSD2_CD_MARK___5 = 2180,\n\tMMC0_D4_MARK___3 = 2181,\n\tTS_SDAT0_B_MARK___2 = 2182,\n\tUSB2_EXTP_MARK = 2183,\n\tGLO_I0_MARK___2 = 2184,\n\tVI0_DATA6_VI0_B6_B_MARK = 2185,\n\tHCTS0_N_D_MARK = 2186,\n\tTS_SDAT1_B_MARK = 2187,\n\tGLO_I0_B_MARK___2 = 2188,\n\tVI3_DATA6_B_MARK = 2189,\n\tSD2_WP_MARK___5 = 2190,\n\tMMC0_D5_MARK___3 = 2191,\n\tTS_SCK0_B_MARK___3 = 2192,\n\tUSB2_IDIN_MARK = 2193,\n\tGLO_I1_MARK___2 = 2194,\n\tVI0_DATA7_VI0_B7_B_MARK = 2195,\n\tHRTS0_N_D_MARK = 2196,\n\tTS_SCK1_B_MARK = 2197,\n\tGLO_I1_B_MARK___2 = 2198,\n\tVI3_DATA7_B_MARK = 2199,\n\tSD3_CLK_MARK___2 = 2200,\n\tMMC1_CLK_MARK___2 = 2201,\n\tSD3_CMD_MARK___2 = 2202,\n\tMMC1_CMD_MARK___2 = 2203,\n\tMTS_N_MARK = 2204,\n\tSD3_DAT0_MARK___2 = 2205,\n\tMMC1_D0_MARK___2 = 2206,\n\tSTM_N_MARK = 2207,\n\tSD3_DAT1_MARK___2 = 2208,\n\tMMC1_D1_MARK___2 = 2209,\n\tMDATA_MARK___2 = 2210,\n\tSD3_DAT2_MARK___2 = 2211,\n\tMMC1_D2_MARK___2 = 2212,\n\tSDATA_MARK___2 = 2213,\n\tSD3_DAT3_MARK___2 = 2214,\n\tMMC1_D3_MARK___2 = 2215,\n\tSCKZ_MARK___2 = 2216,\n\tSD3_CD_MARK___2 = 2217,\n\tMMC1_D4_MARK___2 = 2218,\n\tTS_SDAT1_MARK___3 = 2219,\n\tVSP_MARK___2 = 2220,\n\tGLO_Q0_MARK___2 = 2221,\n\tSIM0_RST_B_MARK___2 = 2222,\n\tSD3_WP_MARK___2 = 2223,\n\tMMC1_D5_MARK___2 = 2224,\n\tTS_SCK1_MARK___3 = 2225,\n\tGLO_Q1_MARK___2 = 2226,\n\tFMIN_C_MARK___4 = 2227,\n\tFMIN_E_MARK___3 = 2228,\n\tFMIN_F_MARK = 2229,\n\tMLB_CLK_MARK___5 = 2230,\n\tIIC2_SCL_B_MARK = 2231,\n\tI2C2_SCL_B_MARK___3 = 2232,\n\tMLB_SIG_MARK___5 = 2233,\n\tSCIFB1_RXD_D_MARK___2 = 2234,\n\tRX1_C_MARK___5 = 2235,\n\tIIC2_SDA_B_MARK = 2236,\n\tI2C2_SDA_B_MARK___3 = 2237,\n\tMLB_DAT_MARK___5 = 2238,\n\tSCIFB1_TXD_D_MARK___2 = 2239,\n\tTX1_C_MARK___5 = 2240,\n\tBPFCLK_C_MARK___4 = 2241,\n\tSSI_SCK0129_MARK___4 = 2242,\n\tCAN_CLK_B_MARK___6 = 2243,\n\tMOUT0_MARK___2 = 2244,\n\tSSI_WS0129_MARK___4 = 2245,\n\tCAN0_TX_B_MARK___6 = 2246,\n\tMOUT1_MARK___2 = 2247,\n\tSSI_SDATA0_MARK___5 = 2248,\n\tCAN0_RX_B_MARK___6 = 2249,\n\tMOUT2_MARK___2 = 2250,\n\tSSI_SDATA1_MARK___5 = 2251,\n\tCAN1_TX_B_MARK___5 = 2252,\n\tMOUT5_MARK___2 = 2253,\n\tSSI_SDATA2_MARK___5 = 2254,\n\tCAN1_RX_B_MARK___5 = 2255,\n\tSSI_SCK1_MARK___4 = 2256,\n\tMOUT6_MARK___2 = 2257,\n\tSSI_SCK34_MARK___7 = 2258,\n\tSTP_OPWM_0_MARK___3 = 2259,\n\tSCIFB0_SCK_MARK___4 = 2260,\n\tMSIOF1_SCK_MARK___5 = 2261,\n\tCAN_DEBUG_HW_TRIGGER_MARK___2 = 2262,\n\tSSI_WS34_MARK___7 = 2263,\n\tSTP_IVCXO27_0_MARK___2 = 2264,\n\tSCIFB0_RXD_MARK___4 = 2265,\n\tMSIOF1_SYNC_MARK___5 = 2266,\n\tCAN_STEP0_MARK___2 = 2267,\n\tSSI_SDATA3_MARK___7 = 2268,\n\tSTP_ISCLK_0_MARK___3 = 2269,\n\tSCIFB0_TXD_MARK___4 = 2270,\n\tMSIOF1_SS1_MARK___5 = 2271,\n\tCAN_TXCLK_MARK___3 = 2272,\n\tSSI_SCK4_MARK___6 = 2273,\n\tSTP_ISD_0_MARK___3 = 2274,\n\tSCIFB0_CTS_N_MARK___3 = 2275,\n\tMSIOF1_SS2_MARK___5 = 2276,\n\tSSI_SCK5_C_MARK = 2277,\n\tCAN_DEBUGOUT0_MARK___2 = 2278,\n\tSSI_WS4_MARK___6 = 2279,\n\tSTP_ISEN_0_MARK___3 = 2280,\n\tSCIFB0_RTS_N_MARK___3 = 2281,\n\tMSIOF1_TXD_MARK___6 = 2282,\n\tSSI_WS5_C_MARK = 2283,\n\tCAN_DEBUGOUT1_MARK___2 = 2284,\n\tSSI_SDATA4_MARK___6 = 2285,\n\tSTP_ISSYNC_0_MARK___3 = 2286,\n\tMSIOF1_RXD_MARK___6 = 2287,\n\tCAN_DEBUGOUT2_MARK___2 = 2288,\n\tSSI_SCK5_MARK___5 = 2289,\n\tSCIFB1_SCK_MARK___3 = 2290,\n\tIERX_B_MARK___4 = 2291,\n\tDU2_EXHSYNC_DU2_HSYNC_MARK = 2292,\n\tQSTH_QHS_MARK___5 = 2293,\n\tCAN_DEBUGOUT3_MARK___2 = 2294,\n\tSSI_WS5_MARK___5 = 2295,\n\tSCIFB1_RXD_MARK___3 = 2296,\n\tIECLK_B_MARK___4 = 2297,\n\tDU2_EXVSYNC_DU2_VSYNC_MARK = 2298,\n\tQSTB_QHE_MARK___5 = 2299,\n\tCAN_DEBUGOUT4_MARK___2 = 2300,\n\tSSI_SDATA5_MARK___5 = 2301,\n\tSCIFB1_TXD_MARK___3 = 2302,\n\tIETX_B_MARK___4 = 2303,\n\tDU2_DR2_MARK = 2304,\n\tLCDOUT2_MARK___5 = 2305,\n\tCAN_DEBUGOUT5_MARK___2 = 2306,\n\tSSI_SCK6_MARK___5 = 2307,\n\tSCIFB1_CTS_N_MARK___2 = 2308,\n\tBPFCLK_D_MARK___4 = 2309,\n\tDU2_DR3_MARK = 2310,\n\tLCDOUT3_MARK___5 = 2311,\n\tCAN_DEBUGOUT6_MARK___2 = 2312,\n\tBPFCLK_F_MARK = 2313,\n\tSSI_WS6_MARK___5 = 2314,\n\tSCIFB1_RTS_N_MARK___2 = 2315,\n\tCAN0_TX_D_MARK___4 = 2316,\n\tDU2_DR4_MARK = 2317,\n\tLCDOUT4_MARK___5 = 2318,\n\tCAN_DEBUGOUT7_MARK___2 = 2319,\n\tSSI_SDATA6_MARK___5 = 2320,\n\tFMIN_D_MARK___4 = 2321,\n\tDU2_DR5_MARK = 2322,\n\tLCDOUT5_MARK___5 = 2323,\n\tCAN_DEBUGOUT8_MARK___2 = 2324,\n\tSSI_SCK78_MARK___5 = 2325,\n\tSTP_IVCXO27_1_MARK = 2326,\n\tSCK1_MARK___3 = 2327,\n\tSCIFA1_SCK_MARK___6 = 2328,\n\tDU2_DR6_MARK = 2329,\n\tLCDOUT6_MARK___5 = 2330,\n\tCAN_DEBUGOUT9_MARK___2 = 2331,\n\tSSI_WS78_MARK___5 = 2332,\n\tSTP_ISCLK_1_MARK___2 = 2333,\n\tSCIFB2_SCK_MARK___3 = 2334,\n\tSCIFA2_CTS_N_MARK = 2335,\n\tDU2_DR7_MARK = 2336,\n\tLCDOUT7_MARK___5 = 2337,\n\tCAN_DEBUGOUT10_MARK___2 = 2338,\n\tSSI_SDATA7_MARK___5 = 2339,\n\tSTP_ISD_1_MARK___2 = 2340,\n\tSCIFB2_RXD_MARK___3 = 2341,\n\tSCIFA2_RTS_N_MARK = 2342,\n\tTCLK2_MARK___4 = 2343,\n\tQSTVA_QVS_MARK___5 = 2344,\n\tCAN_DEBUGOUT11_MARK___2 = 2345,\n\tBPFCLK_E_MARK___3 = 2346,\n\tSSI_SDATA7_B_MARK___5 = 2347,\n\tFMIN_G_MARK = 2348,\n\tSSI_SDATA8_MARK___5 = 2349,\n\tSTP_ISEN_1_MARK___2 = 2350,\n\tSCIFB2_TXD_MARK___3 = 2351,\n\tCAN0_TX_C_MARK___4 = 2352,\n\tCAN_DEBUGOUT12_MARK___2 = 2353,\n\tSSI_SDATA8_B_MARK___5 = 2354,\n\tSSI_SDATA9_MARK___4 = 2355,\n\tSTP_ISSYNC_1_MARK___2 = 2356,\n\tSCIFB2_CTS_N_MARK___3 = 2357,\n\tSSI_WS1_MARK___4 = 2358,\n\tSSI_SDATA5_C_MARK = 2359,\n\tCAN_DEBUGOUT13_MARK___2 = 2360,\n\tAUDIO_CLKA_MARK___6 = 2361,\n\tSCIFB2_RTS_N_MARK___3 = 2362,\n\tCAN_DEBUGOUT14_MARK___2 = 2363,\n\tAUDIO_CLKB_MARK___6 = 2364,\n\tSCIF_CLK_MARK___6 = 2365,\n\tCAN0_RX_D_MARK___4 = 2366,\n\tDVC_MUTE_MARK___4 = 2367,\n\tCAN0_RX_C_MARK___4 = 2368,\n\tCAN_DEBUGOUT15_MARK___2 = 2369,\n\tREMOCON_MARK___4 = 2370,\n\tSCIFA0_SCK_MARK___4 = 2371,\n\tHSCK1_MARK___5 = 2372,\n\tSCK0_MARK___4 = 2373,\n\tMSIOF3_SS2_MARK___2 = 2374,\n\tDU2_DG2_MARK = 2375,\n\tLCDOUT10_MARK___5 = 2376,\n\tIIC1_SDA_C_MARK___2 = 2377,\n\tI2C1_SDA_C_MARK___3 = 2378,\n\tSCIFA0_RXD_MARK___6 = 2379,\n\tHRX1_MARK___4 = 2380,\n\tRX0_MARK___4 = 2381,\n\tDU2_DR0_MARK = 2382,\n\tLCDOUT0_MARK___5 = 2383,\n\tSCIFA0_TXD_MARK___6 = 2384,\n\tHTX1_MARK___4 = 2385,\n\tTX0_MARK___4 = 2386,\n\tDU2_DR1_MARK = 2387,\n\tLCDOUT1_MARK___5 = 2388,\n\tSCIFA0_CTS_N_MARK = 2389,\n\tHCTS1_N_MARK___3 = 2390,\n\tCTS0_N_MARK___2 = 2391,\n\tMSIOF3_SYNC_MARK___2 = 2392,\n\tDU2_DG3_MARK = 2393,\n\tLCDOUT11_MARK___5 = 2394,\n\tPWM0_B_MARK___6 = 2395,\n\tIIC1_SCL_C_MARK___2 = 2396,\n\tI2C1_SCL_C_MARK___3 = 2397,\n\tSCIFA0_RTS_N_MARK = 2398,\n\tHRTS1_N_MARK___3 = 2399,\n\tRTS0_N_MARK___2 = 2400,\n\tMSIOF3_SS1_MARK___2 = 2401,\n\tDU2_DG0_MARK = 2402,\n\tLCDOUT8_MARK___5 = 2403,\n\tPWM1_B_MARK___4 = 2404,\n\tSCIFA1_RXD_MARK___6 = 2405,\n\tAD_DI_MARK___2 = 2406,\n\tRX1_MARK___4 = 2407,\n\tDU2_EXODDF_DU2_ODDF_DISP_CDE_MARK = 2408,\n\tQCPV_QDE_MARK___5 = 2409,\n\tSCIFA1_TXD_MARK___6 = 2410,\n\tAD_DO_MARK___2 = 2411,\n\tTX1_MARK___4 = 2412,\n\tDU2_DG1_MARK = 2413,\n\tLCDOUT9_MARK___5 = 2414,\n\tSCIFA1_CTS_N_MARK = 2415,\n\tAD_CLK_MARK___2 = 2416,\n\tCTS1_N_MARK___2 = 2417,\n\tMSIOF3_RXD_MARK___2 = 2418,\n\tDU0_DOTCLKOUT_MARK___2 = 2419,\n\tQCLK_MARK___5 = 2420,\n\tSCIFA1_RTS_N_MARK = 2421,\n\tAD_NCS_N_MARK = 2422,\n\tRTS1_N_MARK___2 = 2423,\n\tMSIOF3_TXD_MARK___2 = 2424,\n\tDU1_DOTCLKOUT_MARK___3 = 2425,\n\tQSTVB_QVE_MARK___5 = 2426,\n\tHRTS0_N_C_MARK = 2427,\n\tSCIFA2_SCK_MARK___3 = 2428,\n\tFMCLK_MARK___4 = 2429,\n\tSCK2_MARK___3 = 2430,\n\tMSIOF3_SCK_MARK___2 = 2431,\n\tDU2_DG7_MARK = 2432,\n\tLCDOUT15_MARK___5 = 2433,\n\tSCIF_CLK_B_MARK___5 = 2434,\n\tSCIFA2_RXD_MARK___4 = 2435,\n\tFMIN_MARK___4 = 2436,\n\tTX2_MARK___4 = 2437,\n\tDU2_DB0_MARK = 2438,\n\tLCDOUT16_MARK___5 = 2439,\n\tIIC2_SCL_MARK = 2440,\n\tI2C2_SCL_MARK___3 = 2441,\n\tSCIFA2_TXD_MARK___4 = 2442,\n\tBPFCLK_MARK___4 = 2443,\n\tRX2_MARK___4 = 2444,\n\tDU2_DB1_MARK = 2445,\n\tLCDOUT17_MARK___5 = 2446,\n\tIIC2_SDA_MARK = 2447,\n\tI2C2_SDA_MARK___3 = 2448,\n\tHSCK0_MARK___6 = 2449,\n\tTS_SDEN0_MARK___3 = 2450,\n\tDU2_DG4_MARK = 2451,\n\tLCDOUT12_MARK___5 = 2452,\n\tHCTS0_N_C_MARK = 2453,\n\tHRX0_MARK___4 = 2454,\n\tDU2_DB2_MARK = 2455,\n\tLCDOUT18_MARK___5 = 2456,\n\tHTX0_MARK___4 = 2457,\n\tDU2_DB3_MARK = 2458,\n\tLCDOUT19_MARK___5 = 2459,\n\tHCTS0_N_MARK___4 = 2460,\n\tSSI_SCK9_MARK___4 = 2461,\n\tDU2_DB4_MARK = 2462,\n\tLCDOUT20_MARK___5 = 2463,\n\tHRTS0_N_MARK___4 = 2464,\n\tSSI_WS9_MARK___4 = 2465,\n\tDU2_DB5_MARK = 2466,\n\tLCDOUT21_MARK___5 = 2467,\n\tMSIOF0_SCK_MARK___5 = 2468,\n\tTS_SDAT0_MARK___2 = 2469,\n\tADICLK_MARK___6 = 2470,\n\tDU2_DB6_MARK = 2471,\n\tLCDOUT22_MARK___5 = 2472,\n\tMSIOF0_SYNC_MARK___5 = 2473,\n\tTS_SCK0_MARK___3 = 2474,\n\tSSI_SCK2_MARK___4 = 2475,\n\tADIDATA_MARK___6 = 2476,\n\tDU2_DB7_MARK = 2477,\n\tLCDOUT23_MARK___5 = 2478,\n\tHRX0_C_MARK___2 = 2479,\n\tMSIOF0_SS1_MARK___6 = 2480,\n\tADICHS0_MARK___6 = 2481,\n\tDU2_DG5_MARK = 2482,\n\tLCDOUT13_MARK___5 = 2483,\n\tMSIOF0_TXD_MARK___7 = 2484,\n\tADICHS1_MARK___6 = 2485,\n\tDU2_DG6_MARK = 2486,\n\tLCDOUT14_MARK___5 = 2487,\n\tMSIOF0_SS2_MARK___6 = 2488,\n\tAUDIO_CLKOUT_MARK___5 = 2489,\n\tADICHS2_MARK___6 = 2490,\n\tDU2_DISP_MARK = 2491,\n\tQPOLA_MARK___5 = 2492,\n\tHTX0_C_MARK___2 = 2493,\n\tSCIFA2_TXD_B_MARK___3 = 2494,\n\tMSIOF0_RXD_MARK___7 = 2495,\n\tTS_SPSYNC0_MARK___3 = 2496,\n\tSSI_WS2_MARK___4 = 2497,\n\tADICS_SAMP_MARK___6 = 2498,\n\tDU2_CDE_MARK = 2499,\n\tQPOLB_MARK___5 = 2500,\n\tSCIFA2_RXD_B_MARK___3 = 2501,\n\tUSB1_PWEN_MARK___4 = 2502,\n\tAUDIO_CLKOUT_D_MARK = 2503,\n\tUSB1_OVC_MARK___4 = 2504,\n\tTCLK1_B_MARK___5 = 2505,\n\tIIC0_SCL_MARK___4 = 2506,\n\tIIC0_SDA_MARK___4 = 2507,\n\tI2C0_SCL_MARK___3 = 2508,\n\tI2C0_SDA_MARK___3 = 2509,\n\tIIC3_SCL_MARK = 2510,\n\tIIC3_SDA_MARK = 2511,\n\tI2C3_SCL_MARK___3 = 2512,\n\tI2C3_SDA_MARK___3 = 2513,\n\tPINMUX_MARK_END___11 = 2514,\n};\n\nenum {\n\tPINMUX_TYPE_NONE = 0,\n\tPINMUX_TYPE_FUNCTION = 1,\n\tPINMUX_TYPE_GPIO = 2,\n\tPINMUX_TYPE_OUTPUT = 3,\n\tPINMUX_TYPE_INPUT = 4,\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = -1,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nenum {\n\tPLL_OFF_L_VAL = 0,\n\tPLL_OFF_CAL_L_VAL = 1,\n\tPLL_OFF_ALPHA_VAL = 2,\n\tPLL_OFF_ALPHA_VAL_U = 3,\n\tPLL_OFF_USER_CTL = 4,\n\tPLL_OFF_USER_CTL_U = 5,\n\tPLL_OFF_USER_CTL_U1 = 6,\n\tPLL_OFF_CONFIG_CTL = 7,\n\tPLL_OFF_CONFIG_CTL_U = 8,\n\tPLL_OFF_CONFIG_CTL_U1 = 9,\n\tPLL_OFF_CONFIG_CTL_U2 = 10,\n\tPLL_OFF_TEST_CTL = 11,\n\tPLL_OFF_TEST_CTL_U = 12,\n\tPLL_OFF_TEST_CTL_U1 = 13,\n\tPLL_OFF_TEST_CTL_U2 = 14,\n\tPLL_OFF_TEST_CTL_U3 = 15,\n\tPLL_OFF_STATE = 16,\n\tPLL_OFF_STATUS = 17,\n\tPLL_OFF_OPMODE = 18,\n\tPLL_OFF_FRAC = 19,\n\tPLL_OFF_CAL_VAL = 20,\n\tPLL_OFF_MAX_REGS = 21,\n};\n\nenum {\n\tPLL_RAW = 0,\n\tPLL_FIX = 1,\n\tPLL_DIV = 2,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPORT_LAST = 309,\n\tPIN_A11 = 310,\n};\n\nenum {\n\tPORT_LAST___2 = 158,\n\tPIN_LCD3_B2 = 159,\n\tPIN_LCD3_B3 = 160,\n\tPIN_LCD3_B4 = 161,\n\tPIN_LCD3_B5 = 162,\n\tPIN_LCD3_B6 = 163,\n\tPIN_LCD3_B7 = 164,\n\tPIN_LCD3_G2 = 165,\n\tPIN_LCD3_G3 = 166,\n\tPIN_LCD3_G4 = 167,\n\tPIN_LCD3_G5 = 168,\n\tPIN_LCD3_G6 = 169,\n\tPIN_LCD3_G7 = 170,\n};\n\nenum {\n\tPOWERCAP_FC_CAP = 0,\n\tPOWERCAP_FC_PAI = 1,\n\tPOWERCAP_FC_MAX = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_LOW = 2,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_FULL = 5,\n};\n\nenum {\n\tPOWER_SUPPLY_HEALTH_UNKNOWN = 0,\n\tPOWER_SUPPLY_HEALTH_GOOD = 1,\n\tPOWER_SUPPLY_HEALTH_OVERHEAT = 2,\n\tPOWER_SUPPLY_HEALTH_DEAD = 3,\n\tPOWER_SUPPLY_HEALTH_OVERVOLTAGE = 4,\n\tPOWER_SUPPLY_HEALTH_UNDERVOLTAGE = 5,\n\tPOWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 6,\n\tPOWER_SUPPLY_HEALTH_COLD = 7,\n\tPOWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 8,\n\tPOWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 9,\n\tPOWER_SUPPLY_HEALTH_OVERCURRENT = 10,\n\tPOWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 11,\n\tPOWER_SUPPLY_HEALTH_WARM = 12,\n\tPOWER_SUPPLY_HEALTH_COOL = 13,\n\tPOWER_SUPPLY_HEALTH_HOT = 14,\n\tPOWER_SUPPLY_HEALTH_NO_BATTERY = 15,\n\tPOWER_SUPPLY_HEALTH_BLOWN_FUSE = 16,\n\tPOWER_SUPPLY_HEALTH_CELL_IMBALANCE = 17,\n};\n\nenum {\n\tPOWER_SUPPLY_SCOPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_SCOPE_SYSTEM = 1,\n\tPOWER_SUPPLY_SCOPE_DEVICE = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_STATUS_UNKNOWN = 0,\n\tPOWER_SUPPLY_STATUS_CHARGING = 1,\n\tPOWER_SUPPLY_STATUS_DISCHARGING = 2,\n\tPOWER_SUPPLY_STATUS_NOT_CHARGING = 3,\n\tPOWER_SUPPLY_STATUS_FULL = 4,\n};\n\nenum {\n\tPOWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,\n\tPOWER_SUPPLY_TECHNOLOGY_NiMH = 1,\n\tPOWER_SUPPLY_TECHNOLOGY_LION = 2,\n\tPOWER_SUPPLY_TECHNOLOGY_LIPO = 3,\n\tPOWER_SUPPLY_TECHNOLOGY_LiFe = 4,\n\tPOWER_SUPPLY_TECHNOLOGY_NiCd = 5,\n\tPOWER_SUPPLY_TECHNOLOGY_LiMn = 6,\n};\n\nenum {\n\tPREFIX_UNSPEC = 0,\n\tPREFIX_ADDRESS = 1,\n\tPREFIX_CACHEINFO = 2,\n\t__PREFIX_MAX = 3,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tPWMCLK_PRESCALE_LOW = 0,\n\tPWMCLK_PRESCALE_HIGH = 1,\n\tCPTCLK_PRESCALE = 2,\n\tPWM_OUT_EN = 3,\n\tPWM_CPT_EN = 4,\n\tPWM_CPT_INT_EN = 5,\n\tPWM_CPT_INT_STAT = 6,\n\tMAX_REGFIELDS = 7,\n};\n\nenum {\n\tPWMF_REQUESTED = 0,\n\tPWMF_EXPORTED = 1,\n};\n\nenum {\n\tPWRDM_STATE_NOW = 0,\n\tPWRDM_STATE_PREV = 1,\n};\n\nenum {\n\tPWR_REG11 = 0,\n\tPWR_REG18 = 1,\n\tPWR_USB33 = 2,\n\tSTM32PWR_REG_NUM_REGS = 3,\n};\n\nenum {\n\tP_PXO = 0,\n\tP_PLL8 = 1,\n\tP_CXO = 2,\n};\n\nenum {\n\tP_PXO___2 = 0,\n\tP_PLL8___2 = 1,\n\tP_PLL3 = 2,\n\tP_CXO___2 = 3,\n};\n\nenum {\n\tP_PXO___3 = 0,\n\tP_PLL8___3 = 1,\n\tP_PLL2 = 2,\n\tP_PLL3___2 = 3,\n\tP_PLL15 = 4,\n\tP_HDMI_PLL = 5,\n\tP_DSI1_PLL_DSICLK = 6,\n\tP_DSI2_PLL_DSICLK = 7,\n\tP_DSI1_PLL_BYTECLK = 8,\n\tP_DSI2_PLL_BYTECLK = 9,\n\tP_LVDS_PLL = 10,\n};\n\nenum {\n\tP_XO = 0,\n\tP_GPLL0 = 1,\n\tP_GPLL1 = 2,\n\tP_GPLL4 = 3,\n};\n\nenum {\n\tP_XO___2 = 0,\n\tP_GPLL0___2 = 1,\n\tP_GPLL0_AUX = 2,\n\tP_BIMC = 3,\n\tP_GPLL1___2 = 4,\n\tP_GPLL1_AUX = 5,\n\tP_GPLL2 = 6,\n\tP_GPLL2_AUX = 7,\n\tP_SLEEP_CLK = 8,\n\tP_DSI0_PHYPLL_BYTE = 9,\n\tP_DSI0_PHYPLL_DSI = 10,\n\tP_EXT_PRI_I2S = 11,\n\tP_EXT_SEC_I2S = 12,\n\tP_EXT_MCLK = 13,\n};\n\nenum {\n\tP_XO___3 = 0,\n\tP_GPLL0___3 = 1,\n\tP_GPLL1___3 = 2,\n\tP_GPLL4___2 = 3,\n\tP_PCIE_0_1_PIPE_CLK = 4,\n\tP_SATA_ASIC0_CLK = 5,\n\tP_SATA_RX_CLK = 6,\n\tP_SLEEP_CLK___2 = 7,\n};\n\nenum {\n\tP_XO___4 = 0,\n\tP_MMPLL0 = 1,\n\tP_EDPLINK = 2,\n\tP_MMPLL1 = 3,\n\tP_HDMIPLL = 4,\n\tP_GPLL0___4 = 5,\n\tP_EDPVCO = 6,\n\tP_MMPLL4 = 7,\n\tP_DSI0PLL = 8,\n\tP_DSI0PLL_BYTE = 9,\n\tP_MMPLL2 = 10,\n\tP_MMPLL3 = 11,\n\tP_GPLL1___4 = 12,\n\tP_DSI1PLL = 13,\n\tP_DSI1PLL_BYTE = 14,\n\tP_MMSLEEP = 15,\n};\n\nenum {\n\tP_XO___5 = 0,\n\tP_MMPLL0___2 = 1,\n\tP_EDPLINK___2 = 2,\n\tP_MMPLL1___2 = 3,\n\tP_HDMIPLL___2 = 4,\n\tP_GPLL0___5 = 5,\n\tP_EDPVCO___2 = 6,\n\tP_GPLL1___5 = 7,\n\tP_DSI0PLL___2 = 8,\n\tP_DSI0PLL_BYTE___2 = 9,\n\tP_MMPLL2___2 = 10,\n\tP_MMPLL3___2 = 11,\n\tP_DSI1PLL___2 = 12,\n\tP_DSI1PLL_BYTE___2 = 13,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQUIRK_IGNORE_CHECKSUM = 0,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tRB_ADD_STAMP_NONE = 0,\n\tRB_ADD_STAMP_EXTEND = 2,\n\tRB_ADD_STAMP_ABSOLUTE = 4,\n\tRB_ADD_STAMP_FORCE = 8,\n};\n\nenum {\n\tRB_CTX_TRANSITION = 0,\n\tRB_CTX_NMI = 1,\n\tRB_CTX_IRQ = 2,\n\tRB_CTX_SOFTIRQ = 3,\n\tRB_CTX_NORMAL = 4,\n\tRB_CTX_MAX = 5,\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nenum {\n\tRCAR_PCI_ACCESS_READ = 0,\n\tRCAR_PCI_ACCESS_WRITE = 1,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREFCLK = 0,\n\tSYSPLL = 1,\n\tCPUPLL = 2,\n\tAVPLL_B1 = 3,\n\tAVPLL_B2 = 4,\n\tAVPLL_B3 = 5,\n\tAVPLL_B4 = 6,\n\tAVPLL_B5 = 7,\n\tAVPLL_B6 = 8,\n\tAVPLL_B7 = 9,\n\tAVPLL_B8 = 10,\n};\n\nenum {\n\tREFCLK___2 = 0,\n\tVIDEO_EXT0 = 1,\n\tSYSPLL___2 = 2,\n\tMEMPLL = 3,\n\tCPUPLL___2 = 4,\n\tAVPLL_A1 = 5,\n\tAVPLL_A2 = 6,\n\tAVPLL_A3 = 7,\n\tAVPLL_A4 = 8,\n\tAVPLL_A5 = 9,\n\tAVPLL_A6 = 10,\n\tAVPLL_A7 = 11,\n\tAVPLL_A8 = 12,\n\tAVPLL_B1___2 = 13,\n\tAVPLL_B2___2 = 14,\n\tAVPLL_B3___2 = 15,\n\tAVPLL_B4___2 = 16,\n\tAVPLL_B5___2 = 17,\n\tAVPLL_B6___2 = 18,\n\tAVPLL_B7___2 = 19,\n\tAVPLL_B8___2 = 20,\n\tAUDIO1_PLL = 21,\n\tAUDIO_FAST_PLL = 22,\n\tVIDEO0_PLL = 23,\n\tVIDEO0_IN = 24,\n\tVIDEO1_PLL = 25,\n\tVIDEO1_IN = 26,\n\tVIDEO2_PLL = 27,\n\tVIDEO2_IN = 28,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tREGULATOR_ERROR_CLEARED = 0,\n\tREGULATOR_FAILED_RETRY = 1,\n\tREGULATOR_ERROR_ON = 2,\n};\n\nenum {\n\tREG_CON_MOD_TX = 0,\n\tREG_CON_MOD_REGISTER_TX = 1,\n\tREG_CON_MOD_RX = 2,\n\tREG_CON_MOD_REGISTER_RX = 3,\n};\n\nenum {\n\tREG_DR = 0,\n\tREG_ST_DMAWM = 1,\n\tREG_ST_TIMEOUT = 2,\n\tREG_FR = 3,\n\tREG_LCRH_RX = 4,\n\tREG_LCRH_TX = 5,\n\tREG_IBRD = 6,\n\tREG_FBRD = 7,\n\tREG_CR = 8,\n\tREG_IFLS = 9,\n\tREG_IMSC = 10,\n\tREG_RIS = 11,\n\tREG_MIS = 12,\n\tREG_ICR = 13,\n\tREG_DMACR = 14,\n\tREG_ST_XFCR = 15,\n\tREG_ST_XON1 = 16,\n\tREG_ST_XON2 = 17,\n\tREG_ST_XOFF1 = 18,\n\tREG_ST_XOFF2 = 19,\n\tREG_ST_ITCR = 20,\n\tREG_ST_ITIP = 21,\n\tREG_ST_ABCR = 22,\n\tREG_ST_ABIMSC = 23,\n\tREG_ARRAY_SIZE = 24,\n};\n\nenum {\n\tREG_INPUT_DATA = 0,\n\tREG_PORT_CONFIG = 1,\n\tREG_PORT_ENABLE = 2,\n\tREG_SIO_CONFIG = 3,\n\tREG_SIO_CLOCK = 4,\n\tREG_INT_POLARITY = 5,\n\tREG_INT_TRIGGER = 6,\n\tREG_INT_ACK = 7,\n\tREG_INT_ENABLE = 8,\n\tREG_INT_IDENT = 9,\n\tMAXREG = 10,\n};\n\nenum {\n\tREG_MANUFACTURER_DATA = 0,\n\tREG_BATTERY_MODE = 1,\n\tREG_TEMPERATURE = 2,\n\tREG_VOLTAGE = 3,\n\tREG_CURRENT_NOW = 4,\n\tREG_CURRENT_AVG = 5,\n\tREG_MAX_ERR = 6,\n\tREG_CAPACITY = 7,\n\tREG_TIME_TO_EMPTY_NOW = 8,\n\tREG_TIME_TO_EMPTY_AVG = 9,\n\tREG_TIME_TO_FULL_AVG = 10,\n\tREG_STATUS = 11,\n\tREG_CAPACITY_LEVEL = 12,\n\tREG_CYCLE_COUNT = 13,\n\tREG_SERIAL_NUMBER = 14,\n\tREG_REMAINING_CAPACITY = 15,\n\tREG_REMAINING_CAPACITY_CHARGE = 16,\n\tREG_FULL_CHARGE_CAPACITY = 17,\n\tREG_FULL_CHARGE_CAPACITY_CHARGE = 18,\n\tREG_DESIGN_CAPACITY = 19,\n\tREG_DESIGN_CAPACITY_CHARGE = 20,\n\tREG_DESIGN_VOLTAGE_MIN = 21,\n\tREG_DESIGN_VOLTAGE_MAX = 22,\n\tREG_CHEMISTRY = 23,\n\tREG_MANUFACTURER = 24,\n\tREG_MODEL_NAME = 25,\n\tREG_CHARGE_CURRENT = 26,\n\tREG_CHARGE_VOLTAGE = 27,\n};\n\nenum {\n\tREG_RE = 0,\n\tREG_FE = 1,\n\tREG_IE = 2,\n};\n\nenum {\n\tREG_SECONDS_REG = 0,\n\tREG_MINUTES_REG = 1,\n\tREG_HOURS_REG = 2,\n\tREG_DAYS_REG = 3,\n\tREG_MONTHS_REG = 4,\n\tREG_YEARS_REG = 5,\n\tREG_WEEKS_REG = 6,\n\tREG_ALARM_SECONDS_REG = 7,\n\tREG_ALARM_MINUTES_REG = 8,\n\tREG_ALARM_HOURS_REG = 9,\n\tREG_ALARM_DAYS_REG = 10,\n\tREG_ALARM_MONTHS_REG = 11,\n\tREG_ALARM_YEARS_REG = 12,\n\tREG_RTC_CTRL_REG = 13,\n\tREG_RTC_STATUS_REG = 14,\n\tREG_RTC_INTERRUPTS_REG = 15,\n\tREG_RTC_COMP_LSB_REG = 16,\n\tREG_RTC_COMP_MSB_REG = 17,\n};\n\nenum {\n\tREQUEST_ANY = 0,\n\tREQUEST_BY_ID = 1,\n\tREQUEST_BY_CAP = 2,\n\tREQUEST_BY_NODE = 3,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 500,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRGR1_SW_INIT_1 = 0,\n\tEXT_CFG_INDEX = 1,\n\tEXT_CFG_DATA = 2,\n\tPCIE_HARD_DEBUG = 3,\n\tPCIE_INTR2_CPU_BASE = 4,\n};\n\nenum {\n\tRK801_ID = 32784,\n\tRK805_ID = 32848,\n\tRK806_ID = 32864,\n\tRK808_ID = 0,\n\tRK809_ID = 32912,\n\tRK816_ID = 33120,\n\tRK817_ID = 33136,\n\tRK818_ID = 33152,\n};\n\nenum {\n\tRK805_BUCK1_2_ILMAX_2500MA = 0,\n\tRK805_BUCK1_2_ILMAX_3000MA = 1,\n\tRK805_BUCK1_2_ILMAX_3500MA = 2,\n\tRK805_BUCK1_2_ILMAX_4000MA = 3,\n};\n\nenum {\n\tRK805_BUCK3_ILMAX_1500MA = 0,\n\tRK805_BUCK3_ILMAX_2000MA = 1,\n\tRK805_BUCK3_ILMAX_2500MA = 2,\n\tRK805_BUCK3_ILMAX_3000MA = 3,\n};\n\nenum {\n\tRK805_BUCK4_ILMAX_2000MA = 0,\n\tRK805_BUCK4_ILMAX_2500MA = 1,\n\tRK805_BUCK4_ILMAX_3000MA = 2,\n\tRK805_BUCK4_ILMAX_3500MA = 3,\n};\n\nenum {\n\tRK8600_CHIP_ID_08 = 8,\n};\n\nenum {\n\tRK8602_CHIP_ID_10 = 10,\n};\n\nenum {\n\tRN5T567 = 0,\n\tRN5T618 = 1,\n\tRC5T619 = 2,\n};\n\nenum {\n\tRN5T618_DCDC1 = 0,\n\tRN5T618_DCDC2 = 1,\n\tRN5T618_DCDC3 = 2,\n\tRN5T618_DCDC4 = 3,\n\tRN5T618_DCDC5 = 4,\n\tRN5T618_LDO1 = 5,\n\tRN5T618_LDO2 = 6,\n\tRN5T618_LDO3 = 7,\n\tRN5T618_LDO4 = 8,\n\tRN5T618_LDO5 = 9,\n\tRN5T618_LDO6 = 10,\n\tRN5T618_LDO7 = 11,\n\tRN5T618_LDO8 = 12,\n\tRN5T618_LDO9 = 13,\n\tRN5T618_LDO10 = 14,\n\tRN5T618_LDORTC1 = 15,\n\tRN5T618_LDORTC2 = 16,\n\tRN5T618_REG_NUM = 17,\n};\n\nenum {\n\tRN5T618_IRQ_SYS = 0,\n\tRN5T618_IRQ_DCDC = 1,\n\tRN5T618_IRQ_RTC = 2,\n\tRN5T618_IRQ_ADC = 3,\n\tRN5T618_IRQ_GPIO = 4,\n\tRN5T618_IRQ_CHG = 5,\n\tRN5T618_NR_IRQS = 6,\n};\n\nenum {\n\tRNG_OUTPUT_0_REG = 0,\n\tRNG_OUTPUT_1_REG = 1,\n\tRNG_OUTPUT_2_REG = 2,\n\tRNG_OUTPUT_3_REG = 3,\n\tRNG_STATUS_REG = 4,\n\tRNG_INTMASK_REG = 5,\n\tRNG_INTACK_REG = 6,\n\tRNG_CONTROL_REG = 7,\n\tRNG_CONFIG_REG = 8,\n\tRNG_ALARMCNT_REG = 9,\n\tRNG_FROENABLE_REG = 10,\n\tRNG_FRODETUNE_REG = 11,\n\tRNG_ALARMMASK_REG = 12,\n\tRNG_ALARMSTOP_REG = 13,\n\tRNG_REV_REG = 14,\n\tRNG_SYSCONFIG_REG = 15,\n};\n\nenum {\n\tROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,\n\tROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,\n};\n\nenum {\n\tRPCAUTH_lockd = 0,\n\tRPCAUTH_mount = 1,\n\tRPCAUTH_nfs = 2,\n\tRPCAUTH_portmap = 3,\n\tRPCAUTH_statd = 4,\n\tRPCAUTH_nfsd4_cb = 5,\n\tRPCAUTH_cache = 6,\n\tRPCAUTH_nfsd = 7,\n\tRPCAUTH_RootEOF = 8,\n};\n\nenum {\n\tRPCBPROC_NULL = 0,\n\tRPCBPROC_SET = 1,\n\tRPCBPROC_UNSET = 2,\n\tRPCBPROC_GETPORT = 3,\n\tRPCBPROC_GETADDR = 3,\n\tRPCBPROC_DUMP = 4,\n\tRPCBPROC_CALLIT = 5,\n\tRPCBPROC_BCAST = 5,\n\tRPCBPROC_GETTIME = 6,\n\tRPCBPROC_UADDR2TADDR = 7,\n\tRPCBPROC_TADDR2UADDR = 8,\n\tRPCBPROC_GETVERSADDR = 9,\n\tRPCBPROC_INDIRECT = 10,\n\tRPCBPROC_GETADDRLIST = 11,\n\tRPCBPROC_GETSTAT = 12,\n};\n\nenum {\n\tRPCSVC_MAXPAYLOAD = 4194304,\n\tRPCSVC_MAXPAYLOAD_TCP = 4194304,\n\tRPCSVC_MAXPAYLOAD_UDP = 32768,\n};\n\nenum {\n\tRPC_PIPEFS_MOUNT = 0,\n\tRPC_PIPEFS_UMOUNT = 1,\n};\n\nenum {\n\tRPC_TASK_RUNNING = 0,\n\tRPC_TASK_QUEUED = 1,\n\tRPC_TASK_ACTIVE = 2,\n\tRPC_TASK_NEED_XMIT = 3,\n\tRPC_TASK_NEED_RECV = 4,\n\tRPC_TASK_MSG_PIN_WAIT = 5,\n};\n\nenum {\n\tRQ_SECURE = 0,\n\tRQ_LOCAL = 1,\n\tRQ_USEDEFERRAL = 2,\n\tRQ_DROPME = 3,\n\tRQ_VICTIM = 4,\n\tRQ_DATA = 5,\n};\n\nenum {\n\tRST_MC = 0,\n\tRST_GR2D = 1,\n\tRST_GR2D_MAX = 2,\n};\n\nenum {\n\tRST_MC___2 = 0,\n\tRST_GR3D = 1,\n\tRST_MC2 = 2,\n\tRST_GR3D2 = 3,\n\tRST_GR3D_MAX = 4,\n};\n\nenum {\n\tRS_DECODE_LAMBDA = 0,\n\tRS_DECODE_SYN = 1,\n\tRS_DECODE_B = 2,\n\tRS_DECODE_T = 3,\n\tRS_DECODE_OMEGA = 4,\n\tRS_DECODE_ROOT = 5,\n\tRS_DECODE_REG = 6,\n\tRS_DECODE_LOC = 7,\n\tRS_DECODE_NUM_BUFFERS = 8,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTC_SEC = 0,\n\tRTC_MIN = 1,\n\tRTC_HOUR = 2,\n\tRTC_WEEKDAY = 3,\n\tRTC_MONTH = 4,\n\tRTC_YEAR = 5,\n\tRTC_MONTHDAY = 6,\n\tRTC_NR_TIME = 7,\n};\n\nenum {\n\tRTC_SEC___2 = 0,\n\tRTC_MIN___2 = 1,\n\tRTC_HOUR___2 = 2,\n\tRTC_WEEKDAY___2 = 3,\n\tRTC_DATE = 4,\n\tRTC_MONTH___2 = 5,\n\tRTC_YEAR1 = 6,\n\tRTC_YEAR2 = 7,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRX_ERR = 0,\n\tRX_ALL = 1,\n\tRX_FIL = 2,\n\tRX_INV = 3,\n\tRX_MAX = 4,\n};\n\nenum {\n\tRX_XDP_REDIRECT = 0,\n\tRX_XDP_PASS = 1,\n\tRX_XDP_DROP = 2,\n\tRX_XDP_TX = 3,\n\tRX_XDP_TX_ERRORS = 4,\n\tTX_XDP_XMIT = 5,\n\tTX_XDP_XMIT_ERRORS = 6,\n\tXDP_STATS_TOTAL = 7,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tS2MPG10_REGULATOR_OPS_STD = 0,\n\tS2MPG10_REGULATOR_OPS_EXTCONTROL = 1,\n};\n\nenum {\n\tSATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 1,\n\tSATA_PHY_CR_CLOCK_DAC_CTL = 8,\n\tSATA_PHY_CR_CLOCK_RTUNE_CTL = 9,\n\tSATA_PHY_CR_CLOCK_ADC_OUT = 10,\n\tSATA_PHY_CR_CLOCK_MPLL_TST = 23,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCANNED_GARBAGE = 0,\n\tSCANNED_EMPTY_SPACE = -1,\n\tSCANNED_A_NODE = -2,\n\tSCANNED_A_CORRUPT_NODE = -3,\n\tSCANNED_A_BAD_PAD_NODE = -4,\n};\n\nenum {\n\tSCIx_ERI_IRQ = 0,\n\tSCIx_RXI_IRQ = 1,\n\tSCIx_TXI_IRQ = 2,\n\tSCIx_BRI_IRQ = 3,\n\tSCIx_DRI_IRQ = 4,\n\tSCIx_TEI_IRQ = 5,\n\tSCIx_NR_IRQS = 6,\n\tSCIx_MUX_IRQ = 6,\n};\n\nenum {\n\tSCIx_PROBE_REGTYPE = 0,\n\tSCIx_SCI_REGTYPE = 1,\n\tSCIx_IRDA_REGTYPE = 2,\n\tSCIx_SCIFA_REGTYPE = 3,\n\tSCIx_SCIFB_REGTYPE = 4,\n\tSCIx_SH2_SCIF_FIFODATA_REGTYPE = 5,\n\tSCIx_SH3_SCIF_REGTYPE = 6,\n\tSCIx_SH4_SCIF_REGTYPE = 7,\n\tSCIx_SH4_SCIF_BRG_REGTYPE = 8,\n\tSCIx_SH4_SCIF_NO_SCSPTR_REGTYPE = 9,\n\tSCIx_SH4_SCIF_FIFODATA_REGTYPE = 10,\n\tSCIx_SH7705_SCIF_REGTYPE = 11,\n\tSCIx_HSCIF_REGTYPE = 12,\n\tSCIx_RZ_SCIFA_REGTYPE = 13,\n\tSCIx_RZV2H_SCIF_REGTYPE = 14,\n\tSCIx_NR_REGTYPES = 15,\n};\n\nenum {\n\tSCMI_RAW_REPLY_QUEUE = 0,\n\tSCMI_RAW_NOTIF_QUEUE = 1,\n\tSCMI_RAW_ERRS_QUEUE = 2,\n\tSCMI_RAW_MAX_QUEUE = 3,\n};\n\nenum {\n\tSCM_CAN_RAW_ERRQUEUE = 1,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSCSMR = 0,\n\tSCBRR = 1,\n\tSCSCR = 2,\n\tSCxSR = 3,\n\tSCFCR = 4,\n\tSCFDR = 5,\n\tSCxTDR = 6,\n\tSCxRDR = 7,\n\tSCLSR = 8,\n\tSCTFDR = 9,\n\tSCRFDR = 10,\n\tSCSPTR = 11,\n\tHSSRR = 12,\n\tSCPCR = 13,\n\tSCPDR = 14,\n\tSCDL = 15,\n\tSCCKS = 16,\n\tHSRTRGR = 17,\n\tHSTTRGR = 18,\n\tSEMR = 19,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSEG6_ATTR_UNSPEC = 0,\n\tSEG6_ATTR_DST = 1,\n\tSEG6_ATTR_DSTLEN = 2,\n\tSEG6_ATTR_HMACKEYID = 3,\n\tSEG6_ATTR_SECRET = 4,\n\tSEG6_ATTR_SECRETLEN = 5,\n\tSEG6_ATTR_ALGID = 6,\n\tSEG6_ATTR_HMACINFO = 7,\n\t__SEG6_ATTR_MAX = 8,\n};\n\nenum {\n\tSEG6_CMD_UNSPEC = 0,\n\tSEG6_CMD_SETHMAC = 1,\n\tSEG6_CMD_DUMPHMAC = 2,\n\tSEG6_CMD_SET_TUNSRC = 3,\n\tSEG6_CMD_GET_TUNSRC = 4,\n\t__SEG6_CMD_MAX = 5,\n};\n\nenum {\n\tSEL_FRA = 0,\n\tSDM_MOD = 1,\n\tPH_SEL = 2,\n\tNFRA = 3,\n\tDIVR = 4,\n\tDIVN = 5,\n\tDIVM = 6,\n\tP_MAX = 7,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSGPIO_ARCH_LUTON = 0,\n\tSGPIO_ARCH_OCELOT = 1,\n\tSGPIO_ARCH_SPARX5 = 2,\n};\n\nenum {\n\tSGPIO_FLAGS_HAS_IRQ = 1,\n};\n\nenum {\n\tSH_ETH_REG_GIGABIT = 0,\n\tSH_ETH_REG_FAST_RCAR = 1,\n\tSH_ETH_REG_FAST_SH4 = 2,\n\tSH_ETH_REG_FAST_SH3_SH2 = 3,\n};\n\nenum {\n\tSILERGY_SYR82X = 8,\n\tSILERGY_SYR83X = 9,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSKCIPHER_WALK_SLOW = 1,\n\tSKCIPHER_WALK_COPY = 2,\n\tSKCIPHER_WALK_DIFF = 4,\n\tSKCIPHER_WALK_SLEEP = 8,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSLOT_STATUS = 0,\n\tVOLTAGE = 1,\n\tTIME_REMAINING = 2,\n\tCURRENT = 3,\n\tAVERAGE_CURRENT = 4,\n\tAVERAGING_TIME_INTERVAL = 5,\n\tCAPACITY_REMAINING = 6,\n\tLAST_FULL_CHARGE_CAPACITY = 7,\n\tDESIGN_CAPACITY = 8,\n\tCRITICAL_CAPACITY = 9,\n\tTEMPERATURE = 10,\n\tMANUFACTURER = 11,\n\tMODEL = 12,\n\tTYPE = 13,\n};\n\nenum {\n\tSNDRV_PCM_STREAM_PLAYBACK = 0,\n\tSNDRV_PCM_STREAM_CAPTURE = 1,\n\tSNDRV_PCM_STREAM_LAST = 1,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSPECTRE_UNAFFECTED = 0,\n\tSPECTRE_MITIGATED = 1,\n\tSPECTRE_VULNERABLE = 2,\n};\n\nenum {\n\tSPECTRE_V2_METHOD_BPIALL = 1,\n\tSPECTRE_V2_METHOD_ICIALLU = 2,\n\tSPECTRE_V2_METHOD_SMC = 4,\n\tSPECTRE_V2_METHOD_HVC = 8,\n\tSPECTRE_V2_METHOD_LOOP8 = 16,\n};\n\nenum {\n\tSPEEDO_ID_0 = 0,\n\tSPEEDO_ID_1 = 1,\n\tSPEEDO_ID_2 = 2,\n\tSPEEDO_ID_COUNT = 3,\n};\n\nenum {\n\tSPI_VERSION_1 = 0,\n\tSPI_VERSION_2 = 1,\n};\n\nenum {\n\tSP_TASK_PENDING = 0,\n\tSP_NEED_VICTIM = 1,\n\tSP_VICTIM_REMAINS = 2,\n\tSP_TASK_STARTING = 3,\n};\n\nenum {\n\tSQ_SG_MODE = 0,\n\tMQ_MG_MODE = 1,\n};\n\nenum {\n\tSTATE_IDLE = 0,\n\tSTATE_READ = 1,\n\tSTATE_WRITE = 2,\n};\n\nenum {\n\tSTM32F7_SLAVE_HOSTNOTIFY = 0,\n\tSTM32F7_SLAVE_7_10_BITS_ADDR = 1,\n\tSTM32F7_SLAVE_7_BITS_ADDR = 2,\n\tSTM32F7_I2C_MAX_SLAVE = 3,\n};\n\nenum {\n\tSTMPE_IDX_CHIP_ID = 0,\n\tSTMPE_IDX_SYS_CTRL = 1,\n\tSTMPE_IDX_SYS_CTRL2 = 2,\n\tSTMPE_IDX_ICR_LSB = 3,\n\tSTMPE_IDX_IER_LSB = 4,\n\tSTMPE_IDX_IER_MSB = 5,\n\tSTMPE_IDX_ISR_LSB = 6,\n\tSTMPE_IDX_ISR_MSB = 7,\n\tSTMPE_IDX_GPMR_LSB = 8,\n\tSTMPE_IDX_GPMR_CSB = 9,\n\tSTMPE_IDX_GPMR_MSB = 10,\n\tSTMPE_IDX_GPSR_LSB = 11,\n\tSTMPE_IDX_GPSR_CSB = 12,\n\tSTMPE_IDX_GPSR_MSB = 13,\n\tSTMPE_IDX_GPCR_LSB = 14,\n\tSTMPE_IDX_GPCR_CSB = 15,\n\tSTMPE_IDX_GPCR_MSB = 16,\n\tSTMPE_IDX_GPDR_LSB = 17,\n\tSTMPE_IDX_GPDR_CSB = 18,\n\tSTMPE_IDX_GPDR_MSB = 19,\n\tSTMPE_IDX_GPEDR_LSB = 20,\n\tSTMPE_IDX_GPEDR_CSB = 21,\n\tSTMPE_IDX_GPEDR_MSB = 22,\n\tSTMPE_IDX_GPRER_LSB = 23,\n\tSTMPE_IDX_GPRER_CSB = 24,\n\tSTMPE_IDX_GPRER_MSB = 25,\n\tSTMPE_IDX_GPFER_LSB = 26,\n\tSTMPE_IDX_GPFER_CSB = 27,\n\tSTMPE_IDX_GPFER_MSB = 28,\n\tSTMPE_IDX_GPPUR_LSB = 29,\n\tSTMPE_IDX_GPPDR_LSB = 30,\n\tSTMPE_IDX_GPAFR_U_MSB = 31,\n\tSTMPE_IDX_IEGPIOR_LSB = 32,\n\tSTMPE_IDX_IEGPIOR_CSB = 33,\n\tSTMPE_IDX_IEGPIOR_MSB = 34,\n\tSTMPE_IDX_ISGPIOR_LSB = 35,\n\tSTMPE_IDX_ISGPIOR_CSB = 36,\n\tSTMPE_IDX_ISGPIOR_MSB = 37,\n\tSTMPE_IDX_MAX = 38,\n};\n\nenum {\n\tSTPMIC1_BUCK1 = 0,\n\tSTPMIC1_BUCK2 = 1,\n\tSTPMIC1_BUCK3 = 2,\n\tSTPMIC1_BUCK4 = 3,\n\tSTPMIC1_LDO1 = 4,\n\tSTPMIC1_LDO2 = 5,\n\tSTPMIC1_LDO3 = 6,\n\tSTPMIC1_LDO4 = 7,\n\tSTPMIC1_LDO5 = 8,\n\tSTPMIC1_LDO6 = 9,\n\tSTPMIC1_VREF_DDR = 10,\n\tSTPMIC1_BOOST = 11,\n\tSTPMIC1_VBUS_OTG = 12,\n\tSTPMIC1_SW_OUT = 13,\n};\n\nenum {\n\tSUNRPC_MAX_UDP_SENDPAGES = 11,\n};\n\nenum {\n\tSUNRPC_PIPEFS_NFS_PRIO = 0,\n\tSUNRPC_PIPEFS_RPC_PRIO = 1,\n};\n\nenum {\n\tSUNXI_SRC_TYPE_LEVEL_LOW = 0,\n\tSUNXI_SRC_TYPE_EDGE_FALLING = 1,\n\tSUNXI_SRC_TYPE_LEVEL_HIGH = 2,\n\tSUNXI_SRC_TYPE_EDGE_RISING = 3,\n};\n\nenum {\n\tSVC_HANDSHAKE_TO = 500,\n};\n\nenum {\n\tSVC_POOL_AUTO = -1,\n\tSVC_POOL_GLOBAL = 0,\n\tSVC_POOL_PERCPU = 1,\n\tSVC_POOL_PERNODE = 2,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWMII_SPEED_10 = 0,\n\tSWMII_SPEED_100 = 1,\n\tSWMII_SPEED_1000 = 2,\n\tSWMII_DUPLEX_HALF = 0,\n\tSWMII_DUPLEX_FULL = 1,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = -1,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nenum {\n\tSYSCFG_CTRL = 0,\n\tSYSCFG_STATUS = 1,\n\tSYSCFG_PCI = 2,\n\tSYSCFG_SATA = 3,\n\tSYSCFG_REG_MAX = 4,\n};\n\nenum {\n\tSYSTAB = 0,\n\tMMBASE = 1,\n\tMMSIZE = 2,\n\tDCSIZE = 3,\n\tDCVERS = 4,\n\tPARAMCOUNT = 5,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 1,\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 14,\n\tTCP_DATA_OFFSET = 240,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTCS4525_CHIP_ID_12 = 12,\n};\n\nenum {\n\tTCS4526_CHIP_ID_00 = 0,\n};\n\nenum {\n\tTC_MQPRIO_HW_OFFLOAD_NONE = 0,\n\tTC_MQPRIO_HW_OFFLOAD_TCS = 1,\n\t__TC_MQPRIO_HW_OFFLOAD_MAX = 2,\n};\n\nenum {\n\tTC_MQPRIO_MODE_DCB = 0,\n\tTC_MQPRIO_MODE_CHANNEL = 1,\n\t__TC_MQPRIO_MODE_MAX = 2,\n};\n\nenum {\n\tTC_MQPRIO_SHAPER_DCB = 0,\n\tTC_MQPRIO_SHAPER_BW_RATE = 1,\n\t__TC_MQPRIO_SHAPER_MAX = 2,\n};\n\nenum {\n\tTC_TAPRIO_CMD_SET_GATES = 0,\n\tTC_TAPRIO_CMD_SET_AND_HOLD = 1,\n\tTC_TAPRIO_CMD_SET_AND_RELEASE = 2,\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nenum {\n\tTHRESHOLD_INDEX_0 = 0,\n\tTHRESHOLD_INDEX_1 = 1,\n\tTHRESHOLD_INDEX_2 = 2,\n\tTHRESHOLD_INDEX_3 = 3,\n\tTHRESHOLD_INDEX_4 = 4,\n\tTHRESHOLD_INDEX_5 = 5,\n\tTHRESHOLD_INDEX_6 = 6,\n\tTHRESHOLD_INDEX_7 = 7,\n\tTHRESHOLD_INDEX_8 = 8,\n\tTHRESHOLD_INDEX_9 = 9,\n\tTHRESHOLD_INDEX_10 = 10,\n\tTHRESHOLD_INDEX_11 = 11,\n\tTHRESHOLD_INDEX_COUNT = 12,\n};\n\nenum {\n\tTHRESHOLD_INDEX_0___2 = 0,\n\tTHRESHOLD_INDEX_1___2 = 1,\n\tTHRESHOLD_INDEX_COUNT___2 = 2,\n};\n\nenum {\n\tTIMER_A = 0,\n\tTIMER_B = 1,\n\tTIMER_C = 2,\n\tTIMER_D = 3,\n\tTIMER_E = 4,\n\tTIMER_F = 5,\n\tTIMER_G = 6,\n\tTIMER_H = 7,\n};\n\nenum {\n\tTI_CLKM_CM = 0,\n\tTI_CLKM_CM2 = 1,\n\tTI_CLKM_PRM = 2,\n\tTI_CLKM_SCRM = 3,\n\tTI_CLKM_CTRL = 4,\n\tTI_CLKM_CTRL_AUX = 5,\n\tTI_CLKM_PLLSS = 6,\n\tCLK_MAX_MEMMAPS = 7,\n};\n\nenum {\n\tTI_CLK_FIXED = 0,\n\tTI_CLK_MUX = 1,\n\tTI_CLK_DIVIDER = 2,\n\tTI_CLK_COMPOSITE = 3,\n\tTI_CLK_FIXED_FACTOR = 4,\n\tTI_CLK_GATE = 5,\n\tTI_CLK_DPLL = 6,\n};\n\nenum {\n\tTLS_ALERT_DESC_CLOSE_NOTIFY = 0,\n\tTLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10,\n\tTLS_ALERT_DESC_BAD_RECORD_MAC = 20,\n\tTLS_ALERT_DESC_RECORD_OVERFLOW = 22,\n\tTLS_ALERT_DESC_HANDSHAKE_FAILURE = 40,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE = 42,\n\tTLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43,\n\tTLS_ALERT_DESC_CERTIFICATE_REVOKED = 44,\n\tTLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45,\n\tTLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46,\n\tTLS_ALERT_DESC_ILLEGAL_PARAMETER = 47,\n\tTLS_ALERT_DESC_UNKNOWN_CA = 48,\n\tTLS_ALERT_DESC_ACCESS_DENIED = 49,\n\tTLS_ALERT_DESC_DECODE_ERROR = 50,\n\tTLS_ALERT_DESC_DECRYPT_ERROR = 51,\n\tTLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52,\n\tTLS_ALERT_DESC_PROTOCOL_VERSION = 70,\n\tTLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71,\n\tTLS_ALERT_DESC_INTERNAL_ERROR = 80,\n\tTLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86,\n\tTLS_ALERT_DESC_USER_CANCELED = 90,\n\tTLS_ALERT_DESC_MISSING_EXTENSION = 109,\n\tTLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110,\n\tTLS_ALERT_DESC_UNRECOGNIZED_NAME = 112,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113,\n\tTLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115,\n\tTLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116,\n\tTLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120,\n};\n\nenum {\n\tTLS_ALERT_LEVEL_WARNING = 1,\n\tTLS_ALERT_LEVEL_FATAL = 2,\n};\n\nenum {\n\tTLS_NO_KEYRING = 0,\n\tTLS_NO_PEERID = 0,\n\tTLS_NO_CERT = 0,\n\tTLS_NO_PRIVKEY = 0,\n};\n\nenum {\n\tTLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20,\n\tTLS_RECORD_TYPE_ALERT = 21,\n\tTLS_RECORD_TYPE_HANDSHAKE = 22,\n\tTLS_RECORD_TYPE_DATA = 23,\n\tTLS_RECORD_TYPE_HEARTBEAT = 24,\n\tTLS_RECORD_TYPE_TLS12_CID = 25,\n\tTLS_RECORD_TYPE_ACK = 26,\n};\n\nenum {\n\tTOKEN_END = 0,\n\tTOKEN_START = 1,\n\tTOKEN_SLAVE_ADDR_WRITE = 2,\n\tTOKEN_SLAVE_ADDR_READ = 3,\n\tTOKEN_DATA = 4,\n\tTOKEN_DATA_LAST = 5,\n\tTOKEN_STOP = 6,\n};\n\nenum {\n\tTOO_MANY_CLOSE = -1,\n\tTOO_MANY_OPEN = -2,\n\tMISSING_QUOTE = -3,\n};\n\nenum {\n\tTPS65090_IRQ_INTERRUPT = 0,\n\tTPS65090_IRQ_VAC_STATUS_CHANGE = 1,\n\tTPS65090_IRQ_VSYS_STATUS_CHANGE = 2,\n\tTPS65090_IRQ_BAT_STATUS_CHANGE = 3,\n\tTPS65090_IRQ_CHARGING_STATUS_CHANGE = 4,\n\tTPS65090_IRQ_CHARGING_COMPLETE = 5,\n\tTPS65090_IRQ_OVERLOAD_DCDC1 = 6,\n\tTPS65090_IRQ_OVERLOAD_DCDC2 = 7,\n\tTPS65090_IRQ_OVERLOAD_DCDC3 = 8,\n\tTPS65090_IRQ_OVERLOAD_FET1 = 9,\n\tTPS65090_IRQ_OVERLOAD_FET2 = 10,\n\tTPS65090_IRQ_OVERLOAD_FET3 = 11,\n\tTPS65090_IRQ_OVERLOAD_FET4 = 12,\n\tTPS65090_IRQ_OVERLOAD_FET5 = 13,\n\tTPS65090_IRQ_OVERLOAD_FET6 = 14,\n\tTPS65090_IRQ_OVERLOAD_FET7 = 15,\n};\n\nenum {\n\tTPS65090_REGULATOR_DCDC1 = 0,\n\tTPS65090_REGULATOR_DCDC2 = 1,\n\tTPS65090_REGULATOR_DCDC3 = 2,\n\tTPS65090_REGULATOR_FET1 = 3,\n\tTPS65090_REGULATOR_FET2 = 4,\n\tTPS65090_REGULATOR_FET3 = 5,\n\tTPS65090_REGULATOR_FET4 = 6,\n\tTPS65090_REGULATOR_FET5 = 7,\n\tTPS65090_REGULATOR_FET6 = 8,\n\tTPS65090_REGULATOR_FET7 = 9,\n\tTPS65090_REGULATOR_LDO1 = 10,\n\tTPS65090_REGULATOR_LDO2 = 11,\n\tTPS65090_REGULATOR_MAX = 12,\n};\n\nenum {\n\tTPS65219_INT_LDO3_SCG = 0,\n\tTPS65219_INT_LDO3_OC = 1,\n\tTPS65219_INT_LDO3_UV = 2,\n\tTPS65219_INT_LDO4_SCG = 3,\n\tTPS65219_INT_LDO4_OC = 4,\n\tTPS65219_INT_LDO4_UV = 5,\n\tTPS65215_INT_LDO1_SCG = 6,\n\tTPS65215_INT_LDO1_OC = 7,\n\tTPS65215_INT_LDO1_UV = 8,\n\tTPS65215_INT_LDO2_SCG = 9,\n\tTPS65215_INT_LDO2_OC = 10,\n\tTPS65215_INT_LDO2_UV = 11,\n\tTPS65219_INT_LDO1_SCG = 12,\n\tTPS65219_INT_LDO1_OC = 13,\n\tTPS65219_INT_LDO1_UV = 14,\n\tTPS65219_INT_LDO2_SCG = 15,\n\tTPS65219_INT_LDO2_OC = 16,\n\tTPS65219_INT_LDO2_UV = 17,\n\tTPS65219_INT_BUCK3_SCG = 18,\n\tTPS65219_INT_BUCK3_OC = 19,\n\tTPS65219_INT_BUCK3_NEG_OC = 20,\n\tTPS65219_INT_BUCK3_UV = 21,\n\tTPS65219_INT_BUCK1_SCG = 22,\n\tTPS65219_INT_BUCK1_OC = 23,\n\tTPS65219_INT_BUCK1_NEG_OC = 24,\n\tTPS65219_INT_BUCK1_UV = 25,\n\tTPS65219_INT_BUCK2_SCG = 26,\n\tTPS65219_INT_BUCK2_OC = 27,\n\tTPS65219_INT_BUCK2_NEG_OC = 28,\n\tTPS65219_INT_BUCK2_UV = 29,\n\tTPS65219_INT_SENSOR_3_WARM = 30,\n\tTPS65219_INT_SENSOR_2_WARM = 31,\n\tTPS65219_INT_SENSOR_1_WARM = 32,\n\tTPS65219_INT_SENSOR_0_WARM = 33,\n\tTPS65219_INT_SENSOR_3_HOT = 34,\n\tTPS65219_INT_SENSOR_2_HOT = 35,\n\tTPS65219_INT_SENSOR_1_HOT = 36,\n\tTPS65219_INT_SENSOR_0_HOT = 37,\n\tTPS65219_INT_BUCK1_RV = 38,\n\tTPS65219_INT_BUCK2_RV = 39,\n\tTPS65219_INT_BUCK3_RV = 40,\n\tTPS65219_INT_LDO1_RV = 41,\n\tTPS65219_INT_LDO2_RV = 42,\n\tTPS65215_INT_LDO2_RV = 43,\n\tTPS65214_INT_LDO2_RV = 44,\n\tTPS65219_INT_LDO3_RV = 45,\n\tTPS65219_INT_LDO4_RV = 46,\n\tTPS65219_INT_BUCK1_RV_SD = 47,\n\tTPS65219_INT_BUCK2_RV_SD = 48,\n\tTPS65219_INT_BUCK3_RV_SD = 49,\n\tTPS65219_INT_LDO1_RV_SD = 50,\n\tTPS65214_INT_LDO1_RV_SD = 51,\n\tTPS65215_INT_LDO2_RV_SD = 52,\n\tTPS65219_INT_LDO2_RV_SD = 53,\n\tTPS65219_INT_LDO3_RV_SD = 54,\n\tTPS65219_INT_LDO4_RV_SD = 55,\n\tTPS65219_INT_TIMEOUT = 56,\n\tTPS65219_INT_PB_FALLING_EDGE_DETECT = 57,\n\tTPS65219_INT_PB_RISING_EDGE_DETECT = 58,\n};\n\nenum {\n\tTPS6586X_ID_SYS = 0,\n\tTPS6586X_ID_SM_0 = 1,\n\tTPS6586X_ID_SM_1 = 2,\n\tTPS6586X_ID_SM_2 = 3,\n\tTPS6586X_ID_LDO_0 = 4,\n\tTPS6586X_ID_LDO_1 = 5,\n\tTPS6586X_ID_LDO_2 = 6,\n\tTPS6586X_ID_LDO_3 = 7,\n\tTPS6586X_ID_LDO_4 = 8,\n\tTPS6586X_ID_LDO_5 = 9,\n\tTPS6586X_ID_LDO_6 = 10,\n\tTPS6586X_ID_LDO_7 = 11,\n\tTPS6586X_ID_LDO_8 = 12,\n\tTPS6586X_ID_LDO_9 = 13,\n\tTPS6586X_ID_LDO_RTC = 14,\n\tTPS6586X_ID_MAX_REGULATOR = 15,\n};\n\nenum {\n\tTPS6586X_INT_PLDO_0 = 0,\n\tTPS6586X_INT_PLDO_1 = 1,\n\tTPS6586X_INT_PLDO_2 = 2,\n\tTPS6586X_INT_PLDO_3 = 3,\n\tTPS6586X_INT_PLDO_4 = 4,\n\tTPS6586X_INT_PLDO_5 = 5,\n\tTPS6586X_INT_PLDO_6 = 6,\n\tTPS6586X_INT_PLDO_7 = 7,\n\tTPS6586X_INT_COMP_DET = 8,\n\tTPS6586X_INT_ADC = 9,\n\tTPS6586X_INT_PLDO_8 = 10,\n\tTPS6586X_INT_PLDO_9 = 11,\n\tTPS6586X_INT_PSM_0 = 12,\n\tTPS6586X_INT_PSM_1 = 13,\n\tTPS6586X_INT_PSM_2 = 14,\n\tTPS6586X_INT_PSM_3 = 15,\n\tTPS6586X_INT_RTC_ALM1 = 16,\n\tTPS6586X_INT_ACUSB_OVP = 17,\n\tTPS6586X_INT_USB_DET = 18,\n\tTPS6586X_INT_AC_DET = 19,\n\tTPS6586X_INT_BAT_DET = 20,\n\tTPS6586X_INT_CHG_STAT = 21,\n\tTPS6586X_INT_CHG_TEMP = 22,\n\tTPS6586X_INT_PP = 23,\n\tTPS6586X_INT_RESUME = 24,\n\tTPS6586X_INT_LOW_SYS = 25,\n\tTPS6586X_INT_RTC_ALM2 = 26,\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_BAD_MAXACT_TYPE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_NON_UNIQ_SYMBOL = 10,\n\tTP_ERR_BAD_RETPROBE = 11,\n\tTP_ERR_NO_TRACEPOINT = 12,\n\tTP_ERR_BAD_TP_NAME = 13,\n\tTP_ERR_BAD_ADDR_SUFFIX = 14,\n\tTP_ERR_NO_GROUP_NAME = 15,\n\tTP_ERR_GROUP_TOO_LONG = 16,\n\tTP_ERR_BAD_GROUP_NAME = 17,\n\tTP_ERR_NO_EVENT_NAME = 18,\n\tTP_ERR_EVENT_TOO_LONG = 19,\n\tTP_ERR_BAD_EVENT_NAME = 20,\n\tTP_ERR_EVENT_EXIST = 21,\n\tTP_ERR_RETVAL_ON_PROBE = 22,\n\tTP_ERR_NO_RETVAL = 23,\n\tTP_ERR_BAD_STACK_NUM = 24,\n\tTP_ERR_BAD_ARG_NUM = 25,\n\tTP_ERR_BAD_VAR = 26,\n\tTP_ERR_BAD_REG_NAME = 27,\n\tTP_ERR_BAD_MEM_ADDR = 28,\n\tTP_ERR_BAD_IMM = 29,\n\tTP_ERR_IMMSTR_NO_CLOSE = 30,\n\tTP_ERR_FILE_ON_KPROBE = 31,\n\tTP_ERR_BAD_FILE_OFFS = 32,\n\tTP_ERR_SYM_ON_UPROBE = 33,\n\tTP_ERR_TOO_MANY_OPS = 34,\n\tTP_ERR_DEREF_NEED_BRACE = 35,\n\tTP_ERR_BAD_DEREF_OFFS = 36,\n\tTP_ERR_DEREF_OPEN_BRACE = 37,\n\tTP_ERR_COMM_CANT_DEREF = 38,\n\tTP_ERR_BAD_FETCH_ARG = 39,\n\tTP_ERR_ARRAY_NO_CLOSE = 40,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 41,\n\tTP_ERR_BAD_ARRAY_NUM = 42,\n\tTP_ERR_ARRAY_TOO_BIG = 43,\n\tTP_ERR_BAD_TYPE = 44,\n\tTP_ERR_BAD_STRING = 45,\n\tTP_ERR_BAD_SYMSTRING = 46,\n\tTP_ERR_BAD_BITFIELD = 47,\n\tTP_ERR_ARG_NAME_TOO_LONG = 48,\n\tTP_ERR_NO_ARG_NAME = 49,\n\tTP_ERR_BAD_ARG_NAME = 50,\n\tTP_ERR_USED_ARG_NAME = 51,\n\tTP_ERR_ARG_TOO_LONG = 52,\n\tTP_ERR_NO_ARG_BODY = 53,\n\tTP_ERR_BAD_INSN_BNDRY = 54,\n\tTP_ERR_FAIL_REG_PROBE = 55,\n\tTP_ERR_DIFF_PROBE_TYPE = 56,\n\tTP_ERR_DIFF_ARG_TYPE = 57,\n\tTP_ERR_SAME_PROBE = 58,\n\tTP_ERR_NO_EVENT_INFO = 59,\n\tTP_ERR_BAD_ATTACH_EVENT = 60,\n\tTP_ERR_BAD_ATTACH_ARG = 61,\n\tTP_ERR_NO_EP_FILTER = 62,\n\tTP_ERR_NOSUP_BTFARG = 63,\n\tTP_ERR_NO_BTFARG = 64,\n\tTP_ERR_NO_BTF_ENTRY = 65,\n\tTP_ERR_BAD_VAR_ARGS = 66,\n\tTP_ERR_NOFENTRY_ARGS = 67,\n\tTP_ERR_DOUBLE_ARGS = 68,\n\tTP_ERR_ARGS_2LONG = 69,\n\tTP_ERR_ARGIDX_2BIG = 70,\n\tTP_ERR_NO_PTR_STRCT = 71,\n\tTP_ERR_NOSUP_DAT_ARG = 72,\n\tTP_ERR_BAD_HYPHEN = 73,\n\tTP_ERR_NO_BTF_FIELD = 74,\n\tTP_ERR_BAD_BTF_TID = 75,\n\tTP_ERR_BAD_TYPE4STR = 76,\n\tTP_ERR_NEED_STRING_TYPE = 77,\n\tTP_ERR_TOO_MANY_ARGS = 78,\n\tTP_ERR_TOO_MANY_EARGS = 79,\n};\n\nenum {\n\tTRACEFS_EVENT_INODE = 2,\n\tTRACEFS_GID_PERM_SET = 4,\n\tTRACEFS_UID_PERM_SET = 8,\n\tTRACEFS_INSTANCE_INODE = 16,\n};\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n\tTRACE_ARRAY_FL_BOOT = 2,\n\tTRACE_ARRAY_FL_LAST_BOOT = 4,\n\tTRACE_ARRAY_FL_MOD_INIT = 8,\n\tTRACE_ARRAY_FL_MEMMAP = 16,\n\tTRACE_ARRAY_FL_VMALLOC = 32,\n};\n\nenum {\n\tTRACE_CTX_NMI = 0,\n\tTRACE_CTX_IRQ = 1,\n\tTRACE_CTX_SOFTIRQ = 2,\n\tTRACE_CTX_NORMAL = 3,\n\tTRACE_CTX_TRANSITION = 4,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 4,\n\tTRACE_EVENT_FL_TRACEPOINT = 8,\n\tTRACE_EVENT_FL_DYNAMIC = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n\tTRACE_EVENT_FL_EPROBE = 128,\n\tTRACE_EVENT_FL_FPROBE = 256,\n\tTRACE_EVENT_FL_CUSTOM = 512,\n\tTRACE_EVENT_FL_TEST_STR = 1024,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_FTRACE_BIT = 0,\n\tTRACE_FTRACE_NMI_BIT = 1,\n\tTRACE_FTRACE_IRQ_BIT = 2,\n\tTRACE_FTRACE_SIRQ_BIT = 3,\n\tTRACE_FTRACE_TRANSITION_BIT = 4,\n\tTRACE_INTERNAL_BIT = 5,\n\tTRACE_INTERNAL_NMI_BIT = 6,\n\tTRACE_INTERNAL_IRQ_BIT = 7,\n\tTRACE_INTERNAL_SIRQ_BIT = 8,\n\tTRACE_INTERNAL_TRANSITION_BIT = 9,\n\tTRACE_INTERNAL_EVENT_BIT = 10,\n\tTRACE_INTERNAL_EVENT_NMI_BIT = 11,\n\tTRACE_INTERNAL_EVENT_IRQ_BIT = 12,\n\tTRACE_INTERNAL_EVENT_SIRQ_BIT = 13,\n\tTRACE_INTERNAL_EVENT_TRANSITION_BIT = 14,\n\tTRACE_BRANCH_BIT = 15,\n\tTRACE_IRQ_BIT = 16,\n\tTRACE_RECORD_RECURSION_BIT = 17,\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tTRANS_MODE_PIO = 0,\n\tTRANS_MODE_IDMAC = 1,\n\tTRANS_MODE_EDMAC = 2,\n};\n\nenum {\n\tTWL_REMAP_OFF = 0,\n\tTWL_REMAP_SLEEP = 8,\n\tTWL_REMAP_ACTIVE = 9,\n};\n\nenum {\n\tTX_RETIME_SRC_NA = 0,\n\tTX_RETIME_SRC_TXCLK = 1,\n\tTX_RETIME_SRC_CLK_125 = 2,\n\tTX_RETIME_SRC_PHYCLK = 3,\n\tTX_RETIME_SRC_CLKGEN = 4,\n};\n\nenum {\n\tTX_SETUP = 1,\n\tTX_DELETE = 2,\n\tTX_READ = 3,\n\tTX_SEND = 4,\n\tRX_SETUP = 5,\n\tRX_DELETE = 6,\n\tRX_READ = 7,\n\tTX_STATUS = 8,\n\tTX_EXPIRED = 9,\n\tRX_STATUS = 10,\n\tRX_TIMEOUT = 11,\n\tRX_CHANGED = 12,\n};\n\nenum {\n\tTYPE_MAX8998 = 0,\n\tTYPE_LP3974 = 1,\n\tTYPE_LP3979 = 2,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUARTDM_1P1 = 1,\n\tUARTDM_1P2 = 2,\n\tUARTDM_1P3 = 3,\n\tUARTDM_1P4 = 4,\n};\n\nenum {\n\tUBIFS_COMPR_FL = 1,\n\tUBIFS_SYNC_FL = 2,\n\tUBIFS_IMMUTABLE_FL = 4,\n\tUBIFS_APPEND_FL = 8,\n\tUBIFS_DIRSYNC_FL = 16,\n\tUBIFS_XATTR_FL = 32,\n\tUBIFS_CRYPT_FL = 64,\n};\n\nenum {\n\tUBIFS_COMPR_NONE = 0,\n\tUBIFS_COMPR_LZO = 1,\n\tUBIFS_COMPR_ZLIB = 2,\n\tUBIFS_COMPR_ZSTD = 3,\n\tUBIFS_COMPR_TYPES_CNT = 4,\n};\n\nenum {\n\tUBIFS_FLG_BIGLPT = 2,\n\tUBIFS_FLG_SPACE_FIXUP = 4,\n\tUBIFS_FLG_DOUBLE_HASH = 8,\n\tUBIFS_FLG_ENCRYPTION = 16,\n\tUBIFS_FLG_AUTHENTICATION = 32,\n};\n\nenum {\n\tUBIFS_INO_KEY = 0,\n\tUBIFS_DATA_KEY = 1,\n\tUBIFS_DENT_KEY = 2,\n\tUBIFS_XENT_KEY = 3,\n\tUBIFS_KEY_TYPES_CNT = 4,\n};\n\nenum {\n\tUBIFS_INO_NODE = 0,\n\tUBIFS_DATA_NODE = 1,\n\tUBIFS_DENT_NODE = 2,\n\tUBIFS_XENT_NODE = 3,\n\tUBIFS_TRUN_NODE = 4,\n\tUBIFS_PAD_NODE = 5,\n\tUBIFS_SB_NODE = 6,\n\tUBIFS_MST_NODE = 7,\n\tUBIFS_REF_NODE = 8,\n\tUBIFS_IDX_NODE = 9,\n\tUBIFS_CS_NODE = 10,\n\tUBIFS_ORPH_NODE = 11,\n\tUBIFS_AUTH_NODE = 12,\n\tUBIFS_SIG_NODE = 13,\n\tUBIFS_NODE_TYPES_CNT = 14,\n};\n\nenum {\n\tUBIFS_ITYPE_REG = 0,\n\tUBIFS_ITYPE_DIR = 1,\n\tUBIFS_ITYPE_LNK = 2,\n\tUBIFS_ITYPE_BLK = 3,\n\tUBIFS_ITYPE_CHR = 4,\n\tUBIFS_ITYPE_FIFO = 5,\n\tUBIFS_ITYPE_SOCK = 6,\n\tUBIFS_ITYPES_CNT = 7,\n};\n\nenum {\n\tUBIFS_KEY_HASH_R5 = 0,\n\tUBIFS_KEY_HASH_TEST = 1,\n};\n\nenum {\n\tUBIFS_LPT_PNODE = 0,\n\tUBIFS_LPT_NNODE = 1,\n\tUBIFS_LPT_LTAB = 2,\n\tUBIFS_LPT_LSAVE = 3,\n\tUBIFS_LPT_NODE_CNT = 4,\n\tUBIFS_LPT_NOT_A_NODE = 15,\n};\n\nenum {\n\tUBIFS_MST_DIRTY = 1,\n\tUBIFS_MST_NO_ORPHS = 2,\n\tUBIFS_MST_RCVRY = 4,\n};\n\nenum {\n\tUBIFS_NO_NODE_GROUP = 0,\n\tUBIFS_IN_NODE_GROUP = 1,\n\tUBIFS_LAST_OF_NODE_GROUP = 2,\n};\n\nenum {\n\tUBIFS_SIMPLE_KEY_FMT = 0,\n};\n\nenum {\n\tUBI_COMPAT_DELETE = 1,\n\tUBI_COMPAT_RO = 2,\n\tUBI_COMPAT_PRESERVE = 4,\n\tUBI_COMPAT_REJECT = 5,\n};\n\nenum {\n\tUBI_DYNAMIC_VOLUME = 3,\n\tUBI_STATIC_VOLUME = 4,\n};\n\nenum {\n\tUBI_IO_FF = 1,\n\tUBI_IO_FF_BITFLIPS = 2,\n\tUBI_IO_BAD_HDR = 3,\n\tUBI_IO_BAD_HDR_EBADMSG = 4,\n\tUBI_IO_BITFLIPS = 5,\n};\n\nenum {\n\tUBI_READONLY = 1,\n\tUBI_READWRITE = 2,\n\tUBI_EXCLUSIVE = 3,\n\tUBI_METAONLY = 4,\n};\n\nenum {\n\tUBI_VID_DYNAMIC = 1,\n\tUBI_VID_STATIC = 2,\n};\n\nenum {\n\tUBI_VOLUME_ADDED = 0,\n\tUBI_VOLUME_REMOVED = 1,\n\tUBI_VOLUME_RESIZED = 2,\n\tUBI_VOLUME_RENAMED = 3,\n\tUBI_VOLUME_SHUTDOWN = 4,\n\tUBI_VOLUME_UPDATED = 5,\n};\n\nenum {\n\tUBI_VOL_PROP_DIRECT_WRITE = 1,\n};\n\nenum {\n\tUBI_VOL_SKIP_CRC_CHECK_FLG = 1,\n};\n\nenum {\n\tUBI_VTBL_AUTORESIZE_FLG = 1,\n\tUBI_VTBL_SKIP_CRC_CHECK_FLG = 2,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tUSER_CLOCKSOURCE = 0,\n\tUSER_CLOCKEVENT = 1,\n\tUSER_NR = 2,\n};\n\nenum {\n\tUS_FL_SINGLE_LUN = 1,\n\tUS_FL_NEED_OVERRIDE = 2,\n\tUS_FL_SCM_MULT_TARG = 4,\n\tUS_FL_FIX_INQUIRY = 8,\n\tUS_FL_FIX_CAPACITY = 16,\n\tUS_FL_IGNORE_RESIDUE = 32,\n\tUS_FL_BULK32 = 64,\n\tUS_FL_NOT_LOCKABLE = 128,\n\tUS_FL_GO_SLOW = 256,\n\tUS_FL_NO_WP_DETECT = 512,\n\tUS_FL_MAX_SECTORS_64 = 1024,\n\tUS_FL_IGNORE_DEVICE = 2048,\n\tUS_FL_CAPACITY_HEURISTICS = 4096,\n\tUS_FL_MAX_SECTORS_MIN = 8192,\n\tUS_FL_BULK_IGNORE_TAG = 16384,\n\tUS_FL_SANE_SENSE = 32768,\n\tUS_FL_CAPACITY_OK = 65536,\n\tUS_FL_BAD_SENSE = 131072,\n\tUS_FL_NO_READ_DISC_INFO = 262144,\n\tUS_FL_NO_READ_CAPACITY_16 = 524288,\n\tUS_FL_INITIAL_READ10 = 1048576,\n\tUS_FL_WRITE_CACHE = 2097152,\n\tUS_FL_NEEDS_CAP16 = 4194304,\n\tUS_FL_IGNORE_UAS = 8388608,\n\tUS_FL_BROKEN_FUA = 16777216,\n\tUS_FL_NO_ATA_1X = 33554432,\n\tUS_FL_NO_REPORT_OPCODES = 67108864,\n\tUS_FL_MAX_SECTORS_240 = 134217728,\n\tUS_FL_NO_REPORT_LUNS = 268435456,\n\tUS_FL_ALWAYS_SYNC = 536870912,\n\tUS_FL_NO_SAME = 1073741824,\n\tUS_FL_SENSE_AFTER_SYNC = 2147483648,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tVP_MSIX_CONFIG_VECTOR = 0,\n\tVP_MSIX_VQ_VECTOR = 1,\n};\n\nenum {\n\tV_88F6810 = 1,\n\tV_88F6820 = 2,\n\tV_88F6828 = 4,\n\tV_88F6810_PLUS = 7,\n\tV_88F6820_PLUS = 6,\n};\n\nenum {\n\tV_88F6920 = 1,\n\tV_88F6925 = 2,\n\tV_88F6928 = 4,\n\tV_88F6920_PLUS = 7,\n\tV_88F6925_PLUS = 6,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_DEV_OFFLOAD_UNSPECIFIED = 0,\n\tXFRM_DEV_OFFLOAD_CRYPTO = 1,\n\tXFRM_DEV_OFFLOAD_PACKET = 2,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MODE_FLAG_TUNNEL = 1,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tXFRM_STATE_VOID = 0,\n\tXFRM_STATE_ACQ = 1,\n\tXFRM_STATE_VALID = 2,\n\tXFRM_STATE_ERROR = 3,\n\tXFRM_STATE_EXPIRED = 4,\n\tXFRM_STATE_DEAD = 5,\n};\n\nenum {\n\tXPT_BUSY = 0,\n\tXPT_CONN = 1,\n\tXPT_CLOSE = 2,\n\tXPT_DATA = 3,\n\tXPT_TEMP = 4,\n\tXPT_DEAD = 5,\n\tXPT_CHNGBUF = 6,\n\tXPT_DEFERRED = 7,\n\tXPT_OLD = 8,\n\tXPT_LISTENER = 9,\n\tXPT_CACHE_AUTH = 10,\n\tXPT_LOCAL = 11,\n\tXPT_KILL_TEMP = 12,\n\tXPT_CONG_CTRL = 13,\n\tXPT_HANDSHAKE = 14,\n\tXPT_TLS_SESSION = 15,\n\tXPT_PEER_AUTH = 16,\n\tXPT_PEER_VALID = 17,\n\tXPT_RPCB_UNREG = 18,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tMAX_ZONELISTS = 1,\n};\n\nenum {\n\tZONE_MAN_CLKEN_MASK = 1,\n\tZONE_MAN_RESET_CNTL_MASK = 2,\n\tZONE_MAN_MEM_PWR_MASK = 16,\n\tZONE_RESERVED_1_MASK = 32,\n\tZONE_MAN_ISO_CNTL_MASK = 64,\n\tZONE_MANUAL_CONTROL_MASK = 128,\n\tZONE_PWR_DN_REQ_MASK = 512,\n\tZONE_PWR_UP_REQ_MASK = 1024,\n\tZONE_BLK_RST_ASSERT_MASK = 4096,\n\tZONE_PWR_OFF_STATE_MASK = 33554432,\n\tZONE_PWR_ON_STATE_MASK = 67108864,\n\tZONE_DPG_PWR_STATE_MASK = 268435456,\n\tZONE_MEM_PWR_STATE_MASK = 536870912,\n\tZONE_RESET_STATE_MASK = 2147483648,\n\tCPU0_PWR_ZONE_CTRL_REG = 1,\n\tCPU_RESET_CONFIG_REG = 2,\n};\n\nenum {\n\tZSTDbss_compress = 0,\n\tZSTDbss_noCompress = 1,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 3072,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t_IS_EDGE = 0,\n\t_IS_LOW = 1,\n\t_IS_ACTIVE = 2,\n};\n\nenum {\n\t__MVNETA_DOWN = 0,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 10,\n\t__SCHED_FEAT_HRTICK = 11,\n\t__SCHED_FEAT_HRTICK_DL = 12,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 13,\n\t__SCHED_FEAT_TTWU_QUEUE = 14,\n\t__SCHED_FEAT_SIS_UTIL = 15,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 16,\n\t__SCHED_FEAT_RT_PUSH_IPI = 17,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 18,\n\t__SCHED_FEAT_LB_MIN = 19,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 20,\n\t__SCHED_FEAT_WA_IDLE = 21,\n\t__SCHED_FEAT_WA_WEIGHT = 22,\n\t__SCHED_FEAT_WA_BIAS = 23,\n\t__SCHED_FEAT_UTIL_EST = 24,\n\t__SCHED_FEAT_LATENCY_WARN = 25,\n\t__SCHED_FEAT_NI_RANDOM = 26,\n\t__SCHED_FEAT_NR = 27,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t__SPECTRE_V2_METHOD_BPIALL = 0,\n\t__SPECTRE_V2_METHOD_ICIALLU = 1,\n\t__SPECTRE_V2_METHOD_SMC = 2,\n\t__SPECTRE_V2_METHOD_HVC = 3,\n\t__SPECTRE_V2_METHOD_LOOP8 = 4,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NO_OBJ_EXT_BIT = 24,\n\t___GFP_LAST_BIT = 25,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 4,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 5,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 7,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 8,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 9,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 10,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 11,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 12,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 13,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 14,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 15,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 16,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 17,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 18,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 19,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 20,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 21,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 22,\n\t__ctx_convert_unused = 23,\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_sra_exceeded_retry_limit = 5,\n\tattr_inode_readahead = 6,\n\tattr_trigger_test_error = 7,\n\tattr_first_error_time = 8,\n\tattr_last_error_time = 9,\n\tattr_clusters_in_group = 10,\n\tattr_mb_order = 11,\n\tattr_feature = 12,\n\tattr_pointer_pi = 13,\n\tattr_pointer_ui = 14,\n\tattr_pointer_ul = 15,\n\tattr_pointer_u64 = 16,\n\tattr_pointer_u8 = 17,\n\tattr_pointer_string = 18,\n\tattr_pointer_atomic = 19,\n\tattr_journal_task = 20,\n\tattr_err_report_sec = 21,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\tisl29018 = 0,\n\tisl29023 = 1,\n\tisl29035 = 2,\n};\n\nenum {\n\tlcb_ctx_undo_next = 0,\n\tlcb_ctx_prev = 1,\n\tlcb_ctx_next = 2,\n};\n\nenum {\n\tmechtype_caddy = 0,\n\tmechtype_tray = 1,\n\tmechtype_popup = 2,\n\tmechtype_individual_changer = 4,\n\tmechtype_cartridge_changer = 5,\n};\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tFSE_repeat_none = 0,\n\tFSE_repeat_check = 1,\n\tFSE_repeat_valid = 2,\n} FSE_repeat;\n\ntypedef enum {\n\ttrustInput = 0,\n\tcheckMaxSymbolValue = 1,\n} HIST_checkInput_e;\n\ntypedef enum {\n\tHUF_singleStream = 0,\n\tHUF_fourStreams = 1,\n} HUF_nbStreams_e;\n\ntypedef enum {\n\tHUF_repeat_none = 0,\n\tHUF_repeat_check = 1,\n\tHUF_repeat_valid = 2,\n} HUF_repeat;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_cpm_noAttachDict = 0,\n\tZSTD_cpm_attachDict = 1,\n\tZSTD_cpm_createCDict = 2,\n\tZSTD_cpm_unknown = 3,\n} ZSTD_CParamMode_e;\n\ntypedef enum {\n\tZSTD_defaultDisallowed = 0,\n\tZSTD_defaultAllowed = 1,\n} ZSTD_DefaultPolicy_e;\n\ntypedef enum {\n\tZSTD_e_continue = 0,\n\tZSTD_e_flush = 1,\n\tZSTD_e_end = 2,\n} ZSTD_EndDirective;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tzop_dynamic = 0,\n\tzop_predef = 1,\n} ZSTD_OptPrice_e;\n\ntypedef enum {\n\tZSTD_ps_auto = 0,\n\tZSTD_ps_enable = 1,\n\tZSTD_ps_disable = 2,\n} ZSTD_ParamSwitch_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_sf_noBlockDelimiters = 0,\n\tZSTD_sf_explicitBlockDelimiters = 1,\n} ZSTD_SequenceFormat_e;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTDb_not_buffered = 0,\n\tZSTDb_buffered = 1,\n} ZSTD_buffered_policy_e;\n\ntypedef enum {\n\tZSTD_c_compressionLevel = 100,\n\tZSTD_c_windowLog = 101,\n\tZSTD_c_hashLog = 102,\n\tZSTD_c_chainLog = 103,\n\tZSTD_c_searchLog = 104,\n\tZSTD_c_minMatch = 105,\n\tZSTD_c_targetLength = 106,\n\tZSTD_c_strategy = 107,\n\tZSTD_c_targetCBlockSize = 130,\n\tZSTD_c_enableLongDistanceMatching = 160,\n\tZSTD_c_ldmHashLog = 161,\n\tZSTD_c_ldmMinMatch = 162,\n\tZSTD_c_ldmBucketSizeLog = 163,\n\tZSTD_c_ldmHashRateLog = 164,\n\tZSTD_c_contentSizeFlag = 200,\n\tZSTD_c_checksumFlag = 201,\n\tZSTD_c_dictIDFlag = 202,\n\tZSTD_c_nbWorkers = 400,\n\tZSTD_c_jobSize = 401,\n\tZSTD_c_overlapLog = 402,\n\tZSTD_c_experimentalParam1 = 500,\n\tZSTD_c_experimentalParam2 = 10,\n\tZSTD_c_experimentalParam3 = 1000,\n\tZSTD_c_experimentalParam4 = 1001,\n\tZSTD_c_experimentalParam5 = 1002,\n\tZSTD_c_experimentalParam7 = 1004,\n\tZSTD_c_experimentalParam8 = 1005,\n\tZSTD_c_experimentalParam9 = 1006,\n\tZSTD_c_experimentalParam10 = 1007,\n\tZSTD_c_experimentalParam11 = 1008,\n\tZSTD_c_experimentalParam12 = 1009,\n\tZSTD_c_experimentalParam13 = 1010,\n\tZSTD_c_experimentalParam14 = 1011,\n\tZSTD_c_experimentalParam15 = 1012,\n\tZSTD_c_experimentalParam16 = 1013,\n\tZSTD_c_experimentalParam17 = 1014,\n\tZSTD_c_experimentalParam18 = 1015,\n\tZSTD_c_experimentalParam19 = 1016,\n\tZSTD_c_experimentalParam20 = 1017,\n} ZSTD_cParameter;\n\ntypedef enum {\n\tzcss_init = 0,\n\tzcss_load = 1,\n\tzcss_flush = 2,\n} ZSTD_cStreamStage;\n\ntypedef enum {\n\tZSTDcrp_makeClean = 0,\n\tZSTDcrp_leaveDirty = 1,\n} ZSTD_compResetPolicy_e;\n\ntypedef enum {\n\tZSTDcs_created = 0,\n\tZSTDcs_init = 1,\n\tZSTDcs_ongoing = 2,\n\tZSTDcs_ending = 3,\n} ZSTD_compressionStage_e;\n\ntypedef enum {\n\tZSTD_cwksp_alloc_objects = 0,\n\tZSTD_cwksp_alloc_aligned_init_once = 1,\n\tZSTD_cwksp_alloc_aligned = 2,\n\tZSTD_cwksp_alloc_buffers = 3,\n} ZSTD_cwksp_alloc_phase_e;\n\ntypedef enum {\n\tZSTD_cwksp_dynamic_alloc = 0,\n\tZSTD_cwksp_static_alloc = 1,\n} ZSTD_cwksp_static_alloc_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dictDefaultAttach = 0,\n\tZSTD_dictForceAttach = 1,\n\tZSTD_dictForceCopy = 2,\n\tZSTD_dictForceLoad = 3,\n} ZSTD_dictAttachPref_e;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_noDict = 0,\n\tZSTD_extDict = 1,\n\tZSTD_dictMatchState = 2,\n\tZSTD_dedicatedDictSearch = 3,\n} ZSTD_dictMode_e;\n\ntypedef enum {\n\tZSTD_dtlm_fast = 0,\n\tZSTD_dtlm_full = 1,\n} ZSTD_dictTableLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTDirp_continue = 0,\n\tZSTDirp_reset = 1,\n} ZSTD_indexResetPolicy_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_llt_none = 0,\n\tZSTD_llt_literalLength = 1,\n\tZSTD_llt_matchLength = 2,\n} ZSTD_longLengthType_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tZSTD_resetTarget_CDict = 0,\n\tZSTD_resetTarget_CCtx = 1,\n} ZSTD_resetTarget_e;\n\ntypedef enum {\n\tZSTD_fast = 1,\n\tZSTD_dfast = 2,\n\tZSTD_greedy = 3,\n\tZSTD_lazy = 4,\n\tZSTD_lazy2 = 5,\n\tZSTD_btlazy2 = 6,\n\tZSTD_btopt = 7,\n\tZSTD_btultra = 8,\n\tZSTD_btultra2 = 9,\n} ZSTD_strategy;\n\ntypedef enum {\n\tZSTD_tfp_forCCtx = 0,\n\tZSTD_tfp_forCDict = 1,\n} ZSTD_tableFillPurpose_e;\n\ntypedef enum {\n\tbase_0possible = 0,\n\tbase_1guaranteed = 1,\n} base_directive_e;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tneed_more = 0,\n\tblock_done = 1,\n\tfinish_started = 2,\n\tfinish_done = 3,\n} block_state;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n\tEXT4_IGET_BAD = 4,\n\tEXT4_IGET_EA_INODE = 8,\n} ext4_iget_flags;\n\ntypedef enum {\n\tFL_READY = 0,\n\tFL_STATUS = 1,\n\tFL_CFI_QUERY = 2,\n\tFL_JEDEC_QUERY = 3,\n\tFL_ERASING = 4,\n\tFL_ERASE_SUSPENDING = 5,\n\tFL_ERASE_SUSPENDED = 6,\n\tFL_WRITING = 7,\n\tFL_WRITING_TO_BUFFER = 8,\n\tFL_OTP_WRITE = 9,\n\tFL_WRITE_SUSPENDING = 10,\n\tFL_WRITE_SUSPENDED = 11,\n\tFL_PM_SUSPENDED = 12,\n\tFL_SYNCING = 13,\n\tFL_UNLOADING = 14,\n\tFL_LOCKING = 15,\n\tFL_UNLOCKING = 16,\n\tFL_POINT = 17,\n\tFL_XIP_WHILE_ERASING = 18,\n\tFL_XIP_WHILE_WRITING = 19,\n\tFL_SHUTDOWN = 20,\n\tFL_READING = 21,\n\tFL_CACHEDPRG = 22,\n\tFL_RESETTING = 23,\n\tFL_OTPING = 24,\n\tFL_PREPARING_ERASE = 25,\n\tFL_VERIFYING_ERASE = 26,\n\tFL_UNKNOWN = 27,\n} flstate_t;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE___2 = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tIRQ_TX = 1,\n\tIRQ_RX = 2,\n} omap_mbox_irq_t;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPCI_BRIDGE_EMUL_HANDLED = 0,\n\tPCI_BRIDGE_EMUL_NOT_HANDLED = 1,\n} pci_bridge_emul_read_status_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\ntypedef enum {\n\tsearch_hashChain = 0,\n\tsearch_binaryTree = 1,\n\tsearch_rowHash = 2,\n} searchMethod_e;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum ALLOCATE_OPT {\n\tALLOCATE_DEF = 0,\n\tALLOCATE_MFT = 1,\n\tALLOCATE_ZERO = 2,\n\tALLOCATE_ONE_FR = 4,\n};\n\nenum APSR_BIT {\n\tAPSR_MEMS = 2,\n\tAPSR_CMSW = 16,\n\tAPSR_RDM = 8192,\n\tAPSR_TDM = 16384,\n\tAPSR_MIISELECT = 16777216,\n};\n\nenum ARSTR_BIT {\n\tARSTR_ARST = 1,\n};\n\nenum ATTR_TYPE {\n\tATTR_ZERO = 0,\n\tATTR_STD = 16,\n\tATTR_LIST = 32,\n\tATTR_NAME = 48,\n\tATTR_ID = 64,\n\tATTR_SECURE = 80,\n\tATTR_LABEL = 96,\n\tATTR_VOL_INFO = 112,\n\tATTR_DATA = 128,\n\tATTR_ROOT = 144,\n\tATTR_ALLOC = 160,\n\tATTR_BITMAP = 176,\n\tATTR_REPARSE = 192,\n\tATTR_EA_INFO = 208,\n\tATTR_EA = 224,\n\tATTR_PROPERTYSET = 240,\n\tATTR_LOGGED_UTILITY_STREAM = 256,\n\tATTR_END = 4294967295,\n};\n\nenum CCC_BIT {\n\tCCC_OPC = 3,\n\tCCC_OPC_RESET = 0,\n\tCCC_OPC_CONFIG = 1,\n\tCCC_OPC_OPERATION = 2,\n\tCCC_GAC = 128,\n\tCCC_DTSR = 256,\n\tCCC_CSEL = 196608,\n\tCCC_CSEL_HPB = 65536,\n\tCCC_CSEL_ETH_TX = 131072,\n\tCCC_CSEL_GMII_REF = 196608,\n\tCCC_LBME = 16777216,\n};\n\nenum CIE_BIT {\n\tCIE_CRIE = 1,\n\tCIE_CTIE = 256,\n\tCIE_RQFM = 65536,\n\tCIE_CL0M = 131072,\n\tCIE_RFWL = 262144,\n\tCIE_RFFL = 524288,\n};\n\nenum COLLATION_RULE {\n\tNTFS_COLLATION_TYPE_BINARY = 0,\n\tNTFS_COLLATION_TYPE_FILENAME = 1,\n\tNTFS_COLLATION_TYPE_UINT = 16,\n\tNTFS_COLLATION_TYPE_SID = 17,\n\tNTFS_COLLATION_TYPE_SECURITY_HASH = 18,\n\tNTFS_COLLATION_TYPE_UINTS = 19,\n};\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum CSR0_BIT {\n\tCSR0_TPE = 16,\n\tCSR0_RPE = 32,\n};\n\nenum CSR1_BIT {\n\tCSR1_TIP4 = 1,\n\tCSR1_TTCP4 = 16,\n\tCSR1_TUDP4 = 32,\n\tCSR1_TICMP4 = 64,\n\tCSR1_TTCP6 = 1048576,\n\tCSR1_TUDP6 = 2097152,\n\tCSR1_TICMP6 = 4194304,\n\tCSR1_THOP = 16777216,\n\tCSR1_TROUT = 33554432,\n\tCSR1_TAHD = 67108864,\n\tCSR1_TDHD = 134217728,\n};\n\nenum CSR2_BIT {\n\tCSR2_RIP4 = 1,\n\tCSR2_RTCP4 = 16,\n\tCSR2_RUDP4 = 32,\n\tCSR2_RICMP4 = 64,\n\tCSR2_RTCP6 = 1048576,\n\tCSR2_RUDP6 = 2097152,\n\tCSR2_RICMP6 = 4194304,\n\tCSR2_RHOP = 16777216,\n\tCSR2_RROUT = 33554432,\n\tCSR2_RAHD = 67108864,\n\tCSR2_RDHD = 134217728,\n};\n\nenum CSR_BIT {\n\tCSR_OPS = 15,\n\tCSR_OPS_RESET = 1,\n\tCSR_OPS_CONFIG = 2,\n\tCSR_OPS_OPERATION = 4,\n\tCSR_OPS_STANDBY = 8,\n\tCSR_DTS = 256,\n\tCSR_TPO0 = 65536,\n\tCSR_TPO1 = 131072,\n\tCSR_TPO2 = 262144,\n\tCSR_TPO3 = 524288,\n\tCSR_RPO = 1048576,\n};\n\nenum CXR31_BIT {\n\tCXR31_SEL_LINK0 = 1,\n\tCXR31_SEL_LINK1 = 8,\n};\n\nenum CXR35_BIT {\n\tCXR35_SEL_XMII = 3,\n\tCXR35_SEL_XMII_RGMII = 0,\n\tCXR35_SEL_XMII_MII = 2,\n\tCXR35_HALFCYC_CLKSW = 4294901760,\n};\n\nenum DIE_DT {\n\tDT_FMID = 64,\n\tDT_FSTART = 80,\n\tDT_FEND = 96,\n\tDT_FSINGLE = 112,\n\tDT_LINK = 128,\n\tDT_LINKFIX = 144,\n\tDT_EOS = 160,\n\tDT_FEMPTY = 192,\n\tDT_FEMPTY_IS = 208,\n\tDT_FEMPTY_IC = 224,\n\tDT_FEMPTY_ND = 240,\n\tDT_LEMPTY = 32,\n\tDT_EEMPTY = 48,\n};\n\nenum E1000_INVM_STRUCTURE_TYPE {\n\tE1000_INVM_UNINITIALIZED_STRUCTURE = 0,\n\tE1000_INVM_WORD_AUTOLOAD_STRUCTURE = 1,\n\tE1000_INVM_CSR_AUTOLOAD_STRUCTURE = 2,\n\tE1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 3,\n\tE1000_INVM_RSA_KEY_SHA256_STRUCTURE = 4,\n\tE1000_INVM_INVALIDATED_STRUCTURE = 15,\n};\n\nenum ECMR_BIT {\n\tECMR_PRM = 1,\n\tECMR_DM = 2,\n\tECMR_TE = 32,\n\tECMR_RE = 64,\n\tECMR_MPDE = 512,\n\tECMR_TXF = 65536,\n\tECMR_RXF = 131072,\n\tECMR_PFR = 262144,\n\tECMR_ZPF = 524288,\n\tECMR_RZPF = 1048576,\n\tECMR_DPAD = 2097152,\n\tECMR_RCSC = 8388608,\n\tECMR_RCPT = 33554432,\n\tECMR_TRCCM = 67108864,\n};\n\nenum ECMR_BIT___2 {\n\tECMR_TRCCM___2 = 67108864,\n\tECMR_RCSC___2 = 8388608,\n\tECMR_DPAD___2 = 2097152,\n\tECMR_RZPF___2 = 1048576,\n\tECMR_ZPF___2 = 524288,\n\tECMR_PFR___2 = 262144,\n\tECMR_RXF___2 = 131072,\n\tECMR_TXF___2 = 65536,\n\tECMR_MCT = 8192,\n\tECMR_PRCEF = 4096,\n\tECMR_MPDE___2 = 512,\n\tECMR_RE___2 = 64,\n\tECMR_TE___2 = 32,\n\tECMR_RTM = 16,\n\tECMR_ILB = 8,\n\tECMR_ELB = 4,\n\tECMR_DM___2 = 2,\n\tECMR_PRM___2 = 1,\n};\n\nenum ECSIPR_BIT {\n\tECSIPR_ICDIP = 1,\n\tECSIPR_MPDIP = 2,\n\tECSIPR_LCHNGIP = 4,\n};\n\nenum ECSIPR_BIT___2 {\n\tECSIPR_BRCRXIP = 32,\n\tECSIPR_PSRTOIP = 16,\n\tECSIPR_LCHNGIP___2 = 4,\n\tECSIPR_MPDIP___2 = 2,\n\tECSIPR_ICDIP___2 = 1,\n};\n\nenum ECSR_BIT {\n\tECSR_ICD = 1,\n\tECSR_MPD = 2,\n\tECSR_LCHNG = 4,\n\tECSR_PHYI = 8,\n\tECSR_PFRI = 16,\n};\n\nenum ECSR_BIT___2 {\n\tECSR_BRCRX = 32,\n\tECSR_PSRTO = 16,\n\tECSR_LCHNG___2 = 4,\n\tECSR_MPD___2 = 2,\n\tECSR_ICD___2 = 1,\n};\n\nenum EDMR_BIT {\n\tEDMR_NBST = 128,\n\tEDMR_EL = 64,\n\tEDMR_DL1 = 32,\n\tEDMR_DL0 = 16,\n\tEDMR_SRST_GETHER = 3,\n\tEDMR_SRST_ETHER = 1,\n};\n\nenum EDRRR_BIT {\n\tEDRRR_R = 1,\n};\n\nenum EDSR_BIT {\n\tEDSR_ENT = 1,\n\tEDSR_ENR = 2,\n};\n\nenum EDTRR_BIT {\n\tEDTRR_TRNS_GETHER = 3,\n\tEDTRR_TRNS_ETHER = 1,\n};\n\nenum EESIPR_BIT {\n\tEESIPR_TWB1IP = 2147483648,\n\tEESIPR_TWBIP = 1073741824,\n\tEESIPR_TC1IP = 536870912,\n\tEESIPR_TUCIP = 268435456,\n\tEESIPR_ROCIP = 134217728,\n\tEESIPR_TABTIP = 67108864,\n\tEESIPR_RABTIP = 33554432,\n\tEESIPR_RFCOFIP = 16777216,\n\tEESIPR_ADEIP = 8388608,\n\tEESIPR_ECIIP = 4194304,\n\tEESIPR_FTCIP = 2097152,\n\tEESIPR_TDEIP = 1048576,\n\tEESIPR_TFUFIP = 524288,\n\tEESIPR_FRIP = 262144,\n\tEESIPR_RDEIP = 131072,\n\tEESIPR_RFOFIP = 65536,\n\tEESIPR_CNDIP = 2048,\n\tEESIPR_DLCIP = 1024,\n\tEESIPR_CDIP = 512,\n\tEESIPR_TROIP = 256,\n\tEESIPR_RMAFIP = 128,\n\tEESIPR_CEEFIP = 64,\n\tEESIPR_CELFIP = 32,\n\tEESIPR_RRFIP = 16,\n\tEESIPR_RTLFIP = 8,\n\tEESIPR_RTSFIP = 4,\n\tEESIPR_PREIP = 2,\n\tEESIPR_CERFIP = 1,\n};\n\nenum EESR_BIT {\n\tEESR_TWB1 = 2147483648,\n\tEESR_TWB = 1073741824,\n\tEESR_TC1 = 536870912,\n\tEESR_TUC = 268435456,\n\tEESR_ROC = 134217728,\n\tEESR_TABT = 67108864,\n\tEESR_RABT = 33554432,\n\tEESR_RFRMER = 16777216,\n\tEESR_ADE = 8388608,\n\tEESR_ECI = 4194304,\n\tEESR_FTC = 2097152,\n\tEESR_TDE = 1048576,\n\tEESR_TFE = 524288,\n\tEESR_FRC = 262144,\n\tEESR_RDE = 131072,\n\tEESR_RFE = 65536,\n\tEESR_CND = 2048,\n\tEESR_DLC = 1024,\n\tEESR_CD = 512,\n\tEESR_TRO = 256,\n\tEESR_RMAF = 128,\n\tEESR_CEEF = 64,\n\tEESR_CELF = 32,\n\tEESR_RRF = 16,\n\tEESR_RTLF = 8,\n\tEESR_RTSF = 4,\n\tEESR_PRE = 2,\n\tEESR_CERF = 1,\n};\n\nenum EIS_BIT {\n\tEIS_MREF = 1,\n\tEIS_MTEF = 2,\n\tEIS_QEF = 4,\n\tEIS_SEF = 8,\n\tEIS_CLLF0 = 16,\n\tEIS_CLLF1 = 32,\n\tEIS_CULF0 = 64,\n\tEIS_CULF1 = 128,\n\tEIS_TFFF = 256,\n\tEIS_QFS = 65536,\n\tEIS_RESERVED = 4294899712,\n};\n\nenum FCFTR_BIT {\n\tFCFTR_RFF2 = 262144,\n\tFCFTR_RFF1 = 131072,\n\tFCFTR_RFF0 = 65536,\n\tFCFTR_RFD2 = 4,\n\tFCFTR_RFD1 = 2,\n\tFCFTR_RFD0 = 1,\n};\n\nenum FILE_ATTRIBUTE {\n\tFILE_ATTRIBUTE_READONLY = 1,\n\tFILE_ATTRIBUTE_HIDDEN = 2,\n\tFILE_ATTRIBUTE_SYSTEM = 4,\n\tFILE_ATTRIBUTE_ARCHIVE = 32,\n\tFILE_ATTRIBUTE_DEVICE = 64,\n\tFILE_ATTRIBUTE_TEMPORARY = 256,\n\tFILE_ATTRIBUTE_SPARSE_FILE = 512,\n\tFILE_ATTRIBUTE_REPARSE_POINT = 1024,\n\tFILE_ATTRIBUTE_COMPRESSED = 2048,\n\tFILE_ATTRIBUTE_OFFLINE = 4096,\n\tFILE_ATTRIBUTE_NOT_CONTENT_INDEXED = 8192,\n\tFILE_ATTRIBUTE_ENCRYPTED = 16384,\n\tFILE_ATTRIBUTE_VALID_FLAGS = 32695,\n\tFILE_ATTRIBUTE_DIRECTORY = 268435456,\n\tFILE_ATTRIBUTE_INDEX = 536870912,\n};\n\nenum GCCR_BIT {\n\tGCCR_TCR = 3,\n\tGCCR_TCR_NOREQ = 0,\n\tGCCR_TCR_RESET = 1,\n\tGCCR_TCR_CAPTURE = 3,\n\tGCCR_LTO = 4,\n\tGCCR_LTI = 8,\n\tGCCR_LPTC = 16,\n\tGCCR_LMTT = 32,\n\tGCCR_TCSS = 768,\n\tGCCR_TCSS_GPTP = 0,\n\tGCCR_TCSS_ADJGPTP = 256,\n\tGCCR_TCSS_AVTP = 512,\n};\n\nenum GECMR_BIT {\n\tGECMR_10 = 0,\n\tGECMR_100 = 4,\n\tGECMR_1000 = 1,\n};\n\nenum GECMR_BIT___2 {\n\tGECMR_SPEED = 1,\n\tGECMR_SPEED_100 = 0,\n\tGECMR_SPEED_1000 = 1,\n\tGBETH_GECMR_SPEED = 48,\n\tGBETH_GECMR_SPEED_10 = 0,\n\tGBETH_GECMR_SPEED_100 = 16,\n\tGBETH_GECMR_SPEED_1000 = 32,\n};\n\nenum GIC_BIT {\n\tGIC_PTCE = 1,\n\tGIC_PTME = 4,\n};\n\nenum GID_BIT {\n\tGID_PTCD = 1,\n\tGID_PTOD = 2,\n\tGID_PTMD0 = 4,\n\tGID_PTMD1 = 8,\n\tGID_PTMD2 = 16,\n\tGID_PTMD3 = 32,\n\tGID_PTMD4 = 64,\n\tGID_PTMD5 = 128,\n\tGID_PTMD6 = 256,\n\tGID_PTMD7 = 512,\n\tGID_ATCD0 = 65536,\n\tGID_ATCD1 = 131072,\n\tGID_ATCD2 = 262144,\n\tGID_ATCD3 = 524288,\n\tGID_ATCD4 = 1048576,\n\tGID_ATCD5 = 2097152,\n\tGID_ATCD6 = 4194304,\n\tGID_ATCD7 = 8388608,\n\tGID_ATCD8 = 16777216,\n\tGID_ATCD9 = 33554432,\n\tGID_ATCD10 = 67108864,\n\tGID_ATCD11 = 134217728,\n\tGID_ATCD12 = 268435456,\n\tGID_ATCD13 = 536870912,\n\tGID_ATCD14 = 1073741824,\n\tGID_ATCD15 = 2147483648,\n};\n\nenum GIE_BIT {\n\tGIE_PTCS = 1,\n\tGIE_PTOS = 2,\n\tGIE_PTMS0 = 4,\n\tGIE_PTMS1 = 8,\n\tGIE_PTMS2 = 16,\n\tGIE_PTMS3 = 32,\n\tGIE_PTMS4 = 64,\n\tGIE_PTMS5 = 128,\n\tGIE_PTMS6 = 256,\n\tGIE_PTMS7 = 512,\n\tGIE_ATCS0 = 65536,\n\tGIE_ATCS1 = 131072,\n\tGIE_ATCS2 = 262144,\n\tGIE_ATCS3 = 524288,\n\tGIE_ATCS4 = 1048576,\n\tGIE_ATCS5 = 2097152,\n\tGIE_ATCS6 = 4194304,\n\tGIE_ATCS7 = 8388608,\n\tGIE_ATCS8 = 16777216,\n\tGIE_ATCS9 = 33554432,\n\tGIE_ATCS10 = 67108864,\n\tGIE_ATCS11 = 134217728,\n\tGIE_ATCS12 = 268435456,\n\tGIE_ATCS13 = 536870912,\n\tGIE_ATCS14 = 1073741824,\n\tGIE_ATCS15 = 2147483648,\n};\n\nenum GIS_BIT {\n\tGIS_PTCF = 1,\n\tGIS_PTMF = 4,\n\tGIS_RESERVED = 64512,\n};\n\nenum GTI_BIT {\n\tGTI_TIV = 268435455,\n};\n\nenum IMX6_CPUFREQ_CLKS {\n\tARM = 0,\n\tPLL1_SYS = 1,\n\tSTEP = 2,\n\tPLL1_SW = 3,\n\tPLL2_PFD2_396M = 4,\n\tPLL2_BUS = 5,\n\tSECONDARY_SEL = 6,\n};\n\nenum IO_REPARSE_TAG {\n\tIO_REPARSE_TAG_SYMBOLIC_LINK = 0,\n\tIO_REPARSE_TAG_NAME_SURROGATE = 536870912,\n\tIO_REPARSE_TAG_MICROSOFT = 2147483648,\n\tIO_REPARSE_TAG_MOUNT_POINT = 2684354563,\n\tIO_REPARSE_TAG_SYMLINK = 2684354572,\n\tIO_REPARSE_TAG_HSM = 3221225476,\n\tIO_REPARSE_TAG_SIS = 2147483655,\n\tIO_REPARSE_TAG_DEDUP = 2147483667,\n\tIO_REPARSE_TAG_COMPRESS = 2147483671,\n\tIO_REPARSE_TAG_DFS = 2147483658,\n\tIO_REPARSE_TAG_FILTER_MANAGER = 2147483659,\n\tIO_REPARSE_TAG_IFSTEST_CONGRUENT = 9,\n\tIO_REPARSE_TAG_ARKIVIO = 12,\n\tIO_REPARSE_TAG_SOLUTIONSOFT = 536870925,\n\tIO_REPARSE_TAG_COMMVAULT = 14,\n\tIO_REPARSE_TAG_CLOUD = 2415919130,\n\tIO_REPARSE_TAG_CLOUD_1 = 2415923226,\n\tIO_REPARSE_TAG_CLOUD_2 = 2415927322,\n\tIO_REPARSE_TAG_CLOUD_3 = 2415931418,\n\tIO_REPARSE_TAG_CLOUD_4 = 2415935514,\n\tIO_REPARSE_TAG_CLOUD_5 = 2415939610,\n\tIO_REPARSE_TAG_CLOUD_6 = 2415943706,\n\tIO_REPARSE_TAG_CLOUD_7 = 2415947802,\n\tIO_REPARSE_TAG_CLOUD_8 = 2415951898,\n\tIO_REPARSE_TAG_CLOUD_9 = 2415955994,\n\tIO_REPARSE_TAG_CLOUD_A = 2415960090,\n\tIO_REPARSE_TAG_CLOUD_B = 2415964186,\n\tIO_REPARSE_TAG_CLOUD_C = 2415968282,\n\tIO_REPARSE_TAG_CLOUD_D = 2415972378,\n\tIO_REPARSE_TAG_CLOUD_E = 2415976474,\n\tIO_REPARSE_TAG_CLOUD_F = 2415980570,\n};\n\nenum ISS_BIT {\n\tISS_FRS = 1,\n\tISS_FTS = 4,\n\tISS_ES = 64,\n\tISS_MS = 128,\n\tISS_TFUS = 256,\n\tISS_TFWS = 512,\n\tISS_RFWS = 4096,\n\tISS_CGIS = 8192,\n\tISS_DPS1 = 131072,\n\tISS_DPS2 = 262144,\n\tISS_DPS3 = 524288,\n\tISS_DPS4 = 1048576,\n\tISS_DPS5 = 2097152,\n\tISS_DPS6 = 4194304,\n\tISS_DPS7 = 8388608,\n\tISS_DPS8 = 16777216,\n\tISS_DPS9 = 33554432,\n\tISS_DPS10 = 67108864,\n\tISS_DPS11 = 134217728,\n\tISS_DPS12 = 268435456,\n\tISS_DPS13 = 536870912,\n\tISS_DPS14 = 1073741824,\n\tISS_DPS15 = 2147483648,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum MAX77686_RTC_OP {\n\tMAX77686_RTC_WRITE = 0,\n\tMAX77686_RTC_READ = 1,\n};\n\nenum MSC_BIT {\n\tMSC_CRC = 1,\n\tMSC_RFE = 2,\n\tMSC_RTSF = 4,\n\tMSC_RTLF = 8,\n\tMSC_FRE = 16,\n\tMSC_CRL = 32,\n\tMSC_CEEF = 64,\n\tMSC_MC = 128,\n};\n\nenum NTFS_DIRTY_FLAGS {\n\tNTFS_DIRTY_CLEAR = 0,\n\tNTFS_DIRTY_DIRTY = 1,\n\tNTFS_DIRTY_ERROR = 2,\n};\n\nenum NTFS_LOG_OPERATION {\n\tNoop = 0,\n\tCompensationLogRecord = 1,\n\tInitializeFileRecordSegment = 2,\n\tDeallocateFileRecordSegment = 3,\n\tWriteEndOfFileRecordSegment = 4,\n\tCreateAttribute = 5,\n\tDeleteAttribute = 6,\n\tUpdateResidentValue = 7,\n\tUpdateNonresidentValue = 8,\n\tUpdateMappingPairs = 9,\n\tDeleteDirtyClusters = 10,\n\tSetNewAttributeSizes = 11,\n\tAddIndexEntryRoot = 12,\n\tDeleteIndexEntryRoot = 13,\n\tAddIndexEntryAllocation = 14,\n\tDeleteIndexEntryAllocation = 15,\n\tWriteEndOfIndexBuffer = 16,\n\tSetIndexEntryVcnRoot = 17,\n\tSetIndexEntryVcnAllocation = 18,\n\tUpdateFileNameRoot = 19,\n\tUpdateFileNameAllocation = 20,\n\tSetBitsInNonresidentBitMap = 21,\n\tClearBitsInNonresidentBitMap = 22,\n\tHotFix = 23,\n\tEndTopLevelAction = 24,\n\tPrepareTransaction = 25,\n\tCommitTransaction = 26,\n\tForgetTransaction = 27,\n\tOpenNonresidentAttribute = 28,\n\tOpenAttributeTableDump = 29,\n\tAttributeNamesDump = 30,\n\tDirtyPageTableDump = 31,\n\tTransactionTableDump = 32,\n\tUpdateRecordDataRoot = 33,\n\tUpdateRecordDataAllocation = 34,\n\tUpdateRelativeDataInIndex = 35,\n\tUpdateRelativeDataInIndex2 = 36,\n\tZeroEndOfFileRecord = 37,\n};\n\nenum NTFS_SIGNATURE {\n\tNTFS_FILE_SIGNATURE = 1162627398,\n\tNTFS_INDX_SIGNATURE = 1480871497,\n\tNTFS_CHKD_SIGNATURE = 1145784387,\n\tNTFS_RSTR_SIGNATURE = 1381258066,\n\tNTFS_RCRD_SIGNATURE = 1146241874,\n\tNTFS_BAAD_SIGNATURE = 1145127234,\n\tNTFS_HOLE_SIGNATURE = 1162628936,\n\tNTFS_FFFF_SIGNATURE = 4294967295,\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecPublicKey = 2,\n\tOID_id_prime192v1 = 3,\n\tOID_id_prime256v1 = 4,\n\tOID_id_ecdsa_with_sha1 = 5,\n\tOID_id_ecdsa_with_sha224 = 6,\n\tOID_id_ecdsa_with_sha256 = 7,\n\tOID_id_ecdsa_with_sha384 = 8,\n\tOID_id_ecdsa_with_sha512 = 9,\n\tOID_rsaEncryption = 10,\n\tOID_sha1WithRSAEncryption = 11,\n\tOID_sha256WithRSAEncryption = 12,\n\tOID_sha384WithRSAEncryption = 13,\n\tOID_sha512WithRSAEncryption = 14,\n\tOID_sha224WithRSAEncryption = 15,\n\tOID_data = 16,\n\tOID_signed_data = 17,\n\tOID_email_address = 18,\n\tOID_contentType = 19,\n\tOID_messageDigest = 20,\n\tOID_signingTime = 21,\n\tOID_smimeCapabilites = 22,\n\tOID_smimeAuthenticatedAttrs = 23,\n\tOID_mskrb5 = 24,\n\tOID_krb5 = 25,\n\tOID_krb5u2u = 26,\n\tOID_msIndirectData = 27,\n\tOID_msStatementType = 28,\n\tOID_msSpOpusInfo = 29,\n\tOID_msPeImageDataObjId = 30,\n\tOID_msIndividualSPKeyPurpose = 31,\n\tOID_msOutlookExpress = 32,\n\tOID_ntlmssp = 33,\n\tOID_negoex = 34,\n\tOID_spnego = 35,\n\tOID_IAKerb = 36,\n\tOID_PKU2U = 37,\n\tOID_Scram = 38,\n\tOID_certAuthInfoAccess = 39,\n\tOID_sha1 = 40,\n\tOID_id_ansip384r1 = 41,\n\tOID_id_ansip521r1 = 42,\n\tOID_sha256 = 43,\n\tOID_sha384 = 44,\n\tOID_sha512 = 45,\n\tOID_sha224 = 46,\n\tOID_commonName = 47,\n\tOID_surname = 48,\n\tOID_countryName = 49,\n\tOID_locality = 50,\n\tOID_stateOrProvinceName = 51,\n\tOID_organizationName = 52,\n\tOID_organizationUnitName = 53,\n\tOID_title = 54,\n\tOID_description = 55,\n\tOID_name = 56,\n\tOID_givenName = 57,\n\tOID_initials = 58,\n\tOID_generationalQualifier = 59,\n\tOID_subjectKeyIdentifier = 60,\n\tOID_keyUsage = 61,\n\tOID_subjectAltName = 62,\n\tOID_issuerAltName = 63,\n\tOID_basicConstraints = 64,\n\tOID_crlDistributionPoints = 65,\n\tOID_certPolicies = 66,\n\tOID_authorityKeyIdentifier = 67,\n\tOID_extKeyUsage = 68,\n\tOID_NetlogonMechanism = 69,\n\tOID_appleLocalKdcSupported = 70,\n\tOID_gostCPSignA = 71,\n\tOID_gostCPSignB = 72,\n\tOID_gostCPSignC = 73,\n\tOID_gost2012PKey256 = 74,\n\tOID_gost2012PKey512 = 75,\n\tOID_gost2012Digest256 = 76,\n\tOID_gost2012Digest512 = 77,\n\tOID_gost2012Signature256 = 78,\n\tOID_gost2012Signature512 = 79,\n\tOID_gostTC26Sign256A = 80,\n\tOID_gostTC26Sign256B = 81,\n\tOID_gostTC26Sign256C = 82,\n\tOID_gostTC26Sign256D = 83,\n\tOID_gostTC26Sign512A = 84,\n\tOID_gostTC26Sign512B = 85,\n\tOID_gostTC26Sign512C = 86,\n\tOID_sm2 = 87,\n\tOID_sm3 = 88,\n\tOID_SM2_with_SM3 = 89,\n\tOID_sm3WithRSAEncryption = 90,\n\tOID_TPMLoadableKey = 91,\n\tOID_TPMImportableKey = 92,\n\tOID_TPMSealedData = 93,\n\tOID_sha3_256 = 94,\n\tOID_sha3_384 = 95,\n\tOID_sha3_512 = 96,\n\tOID_id_ecdsa_with_sha3_256 = 97,\n\tOID_id_ecdsa_with_sha3_384 = 98,\n\tOID_id_ecdsa_with_sha3_512 = 99,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102,\n\tOID_id_ml_dsa_44 = 103,\n\tOID_id_ml_dsa_65 = 104,\n\tOID_id_ml_dsa_87 = 105,\n\tOID__NR = 106,\n};\n\nenum Opt {\n\tOpt_uid___6 = 0,\n\tOpt_gid___6 = 1,\n\tOpt_umask___2 = 2,\n\tOpt_dmask___2 = 3,\n\tOpt_fmask___2 = 4,\n\tOpt_immutable___2 = 5,\n\tOpt_discard___3 = 6,\n\tOpt_force = 7,\n\tOpt_sparse = 8,\n\tOpt_nohidden = 9,\n\tOpt_hide_dot_files = 10,\n\tOpt_windows_names = 11,\n\tOpt_showmeta = 12,\n\tOpt_acl___2 = 13,\n\tOpt_acl_bool = 14,\n\tOpt_iocharset = 15,\n\tOpt_prealloc = 16,\n\tOpt_prealloc_bool = 17,\n\tOpt_nocase___2 = 18,\n\tOpt_delalloc___2 = 19,\n\tOpt_delalloc_bool = 20,\n\tOpt_err___4 = 21,\n};\n\nenum Opt_errors {\n\tOpt_errors_continue = 0,\n\tOpt_errors_panic = 1,\n};\n\nenum PIR_BIT {\n\tPIR_MDI = 8,\n\tPIR_MDO = 4,\n\tPIR_MMD = 2,\n\tPIR_MDC = 1,\n};\n\nenum PIR_BIT___2 {\n\tPIR_MDC___2 = 1,\n\tPIR_MMD___2 = 2,\n\tPIR_MDO___2 = 4,\n\tPIR_MDI___2 = 8,\n};\n\nenum PSR_BIT {\n\tPSR_LMON = 1,\n};\n\nenum RAVB_QUEUE {\n\tRAVB_BE = 0,\n\tRAVB_NC = 1,\n};\n\nenum RCR_BIT {\n\tRCR_EFFS = 1,\n\tRCR_ENCF = 2,\n\tRCR_ESF = 12,\n\tRCR_ETS0 = 16,\n\tRCR_ETS2 = 32,\n\tRCR_RFCL = 536805376,\n};\n\nenum RD_LEN_BIT {\n\tRD_RFL = 65535,\n\tRD_RBL = 4294901760,\n};\n\nenum RD_STS_BIT {\n\tRD_RACT = 2147483648,\n\tRD_RDLE = 1073741824,\n\tRD_RFP1 = 536870912,\n\tRD_RFP0 = 268435456,\n\tRD_RFE = 134217728,\n\tRD_RFS10 = 512,\n\tRD_RFS9 = 256,\n\tRD_RFS8 = 128,\n\tRD_RFS7 = 64,\n\tRD_RFS6 = 32,\n\tRD_RFS5 = 16,\n\tRD_RFS4 = 8,\n\tRD_RFS3 = 4,\n\tRD_RFS2 = 2,\n\tRD_RFS1 = 1,\n};\n\nenum RECORD_FLAG {\n\tRECORD_FLAG_IN_USE = 1,\n\tRECORD_FLAG_DIR = 2,\n\tRECORD_FLAG_SYSTEM = 4,\n\tRECORD_FLAG_INDEX = 8,\n};\n\nenum RECORD_NUM {\n\tMFT_REC_MFT = 0,\n\tMFT_REC_MIRR = 1,\n\tMFT_REC_LOG = 2,\n\tMFT_REC_VOL = 3,\n\tMFT_REC_ATTR = 4,\n\tMFT_REC_ROOT = 5,\n\tMFT_REC_BITMAP = 6,\n\tMFT_REC_BOOT = 7,\n\tMFT_REC_BADCLUST = 8,\n\tMFT_REC_SECURE = 9,\n\tMFT_REC_UPCASE = 10,\n\tMFT_REC_EXTEND = 11,\n\tMFT_REC_RESERVED = 12,\n\tMFT_REC_FREE = 16,\n\tMFT_REC_USER = 24,\n};\n\nenum REPARSE_SIGN {\n\tREPARSE_NONE = 0,\n\tREPARSE_COMPRESSED = 1,\n\tREPARSE_DEDUPLICATED = 2,\n\tREPARSE_LINK = 3,\n};\n\nenum RIC0_BIT {\n\tRIC0_FRE0 = 1,\n\tRIC0_FRE1 = 2,\n\tRIC0_FRE2 = 4,\n\tRIC0_FRE3 = 8,\n\tRIC0_FRE4 = 16,\n\tRIC0_FRE5 = 32,\n\tRIC0_FRE6 = 64,\n\tRIC0_FRE7 = 128,\n\tRIC0_FRE8 = 256,\n\tRIC0_FRE9 = 512,\n\tRIC0_FRE10 = 1024,\n\tRIC0_FRE11 = 2048,\n\tRIC0_FRE12 = 4096,\n\tRIC0_FRE13 = 8192,\n\tRIC0_FRE14 = 16384,\n\tRIC0_FRE15 = 32768,\n\tRIC0_FRE16 = 65536,\n\tRIC0_FRE17 = 131072,\n};\n\nenum RIC2_BIT {\n\tRIC2_QFE0 = 1,\n\tRIC2_QFE1 = 2,\n\tRIC2_QFE2 = 4,\n\tRIC2_QFE3 = 8,\n\tRIC2_QFE4 = 16,\n\tRIC2_QFE5 = 32,\n\tRIC2_QFE6 = 64,\n\tRIC2_QFE7 = 128,\n\tRIC2_QFE8 = 256,\n\tRIC2_QFE9 = 512,\n\tRIC2_QFE10 = 1024,\n\tRIC2_QFE11 = 2048,\n\tRIC2_QFE12 = 4096,\n\tRIC2_QFE13 = 8192,\n\tRIC2_QFE14 = 16384,\n\tRIC2_QFE15 = 32768,\n\tRIC2_QFE16 = 65536,\n\tRIC2_QFE17 = 131072,\n\tRIC2_RFFE = 2147483648,\n};\n\nenum RIS0_BIT {\n\tRIS0_FRF0 = 1,\n\tRIS0_FRF1 = 2,\n\tRIS0_FRF2 = 4,\n\tRIS0_FRF3 = 8,\n\tRIS0_FRF4 = 16,\n\tRIS0_FRF5 = 32,\n\tRIS0_FRF6 = 64,\n\tRIS0_FRF7 = 128,\n\tRIS0_FRF8 = 256,\n\tRIS0_FRF9 = 512,\n\tRIS0_FRF10 = 1024,\n\tRIS0_FRF11 = 2048,\n\tRIS0_FRF12 = 4096,\n\tRIS0_FRF13 = 8192,\n\tRIS0_FRF14 = 16384,\n\tRIS0_FRF15 = 32768,\n\tRIS0_FRF16 = 65536,\n\tRIS0_FRF17 = 131072,\n\tRIS0_RESERVED = 4294705152,\n};\n\nenum RIS2_BIT {\n\tRIS2_QFF0 = 1,\n\tRIS2_QFF1 = 2,\n\tRIS2_QFF2 = 4,\n\tRIS2_QFF3 = 8,\n\tRIS2_QFF4 = 16,\n\tRIS2_QFF5 = 32,\n\tRIS2_QFF6 = 64,\n\tRIS2_QFF7 = 128,\n\tRIS2_QFF8 = 256,\n\tRIS2_QFF9 = 512,\n\tRIS2_QFF10 = 1024,\n\tRIS2_QFF11 = 2048,\n\tRIS2_QFF12 = 4096,\n\tRIS2_QFF13 = 8192,\n\tRIS2_QFF14 = 16384,\n\tRIS2_QFF15 = 32768,\n\tRIS2_QFF16 = 65536,\n\tRIS2_QFF17 = 131072,\n\tRIS2_RFFF = 2147483648,\n\tRIS2_RESERVED = 2147221504,\n};\n\nenum RMCR_BIT {\n\tRMCR_RNC = 1,\n};\n\nenum RX_DS_CC_BIT {\n\tRX_DS = 4095,\n\tRX_TR = 4096,\n\tRX_EI = 8192,\n\tRX_PS = 49152,\n};\n\nenum S2MPU02_reg {\n\tS2MPU02_REG_ID = 0,\n\tS2MPU02_REG_INT1 = 1,\n\tS2MPU02_REG_INT2 = 2,\n\tS2MPU02_REG_INT3 = 3,\n\tS2MPU02_REG_INT1M = 4,\n\tS2MPU02_REG_INT2M = 5,\n\tS2MPU02_REG_INT3M = 6,\n\tS2MPU02_REG_ST1 = 7,\n\tS2MPU02_REG_ST2 = 8,\n\tS2MPU02_REG_PWRONSRC = 9,\n\tS2MPU02_REG_OFFSRC = 10,\n\tS2MPU02_REG_BU_CHG = 11,\n\tS2MPU02_REG_RTCCTRL = 12,\n\tS2MPU02_REG_PMCTRL1 = 13,\n\tS2MPU02_REG_RSVD1 = 14,\n\tS2MPU02_REG_RSVD2 = 15,\n\tS2MPU02_REG_RSVD3 = 16,\n\tS2MPU02_REG_RSVD4 = 17,\n\tS2MPU02_REG_RSVD5 = 18,\n\tS2MPU02_REG_RSVD6 = 19,\n\tS2MPU02_REG_RSVD7 = 20,\n\tS2MPU02_REG_WRSTEN = 21,\n\tS2MPU02_REG_RSVD8 = 22,\n\tS2MPU02_REG_RSVD9 = 23,\n\tS2MPU02_REG_RSVD10 = 24,\n\tS2MPU02_REG_B1CTRL1 = 25,\n\tS2MPU02_REG_B1CTRL2 = 26,\n\tS2MPU02_REG_B2CTRL1 = 27,\n\tS2MPU02_REG_B2CTRL2 = 28,\n\tS2MPU02_REG_B3CTRL1 = 29,\n\tS2MPU02_REG_B3CTRL2 = 30,\n\tS2MPU02_REG_B4CTRL1 = 31,\n\tS2MPU02_REG_B4CTRL2 = 32,\n\tS2MPU02_REG_B5CTRL1 = 33,\n\tS2MPU02_REG_B5CTRL2 = 34,\n\tS2MPU02_REG_B5CTRL3 = 35,\n\tS2MPU02_REG_B5CTRL4 = 36,\n\tS2MPU02_REG_B5CTRL5 = 37,\n\tS2MPU02_REG_B6CTRL1 = 38,\n\tS2MPU02_REG_B6CTRL2 = 39,\n\tS2MPU02_REG_B7CTRL1 = 40,\n\tS2MPU02_REG_B7CTRL2 = 41,\n\tS2MPU02_REG_RAMP1 = 42,\n\tS2MPU02_REG_RAMP2 = 43,\n\tS2MPU02_REG_L1CTRL = 44,\n\tS2MPU02_REG_L2CTRL1 = 45,\n\tS2MPU02_REG_L2CTRL2 = 46,\n\tS2MPU02_REG_L2CTRL3 = 47,\n\tS2MPU02_REG_L2CTRL4 = 48,\n\tS2MPU02_REG_L3CTRL = 49,\n\tS2MPU02_REG_L4CTRL = 50,\n\tS2MPU02_REG_L5CTRL = 51,\n\tS2MPU02_REG_L6CTRL = 52,\n\tS2MPU02_REG_L7CTRL = 53,\n\tS2MPU02_REG_L8CTRL = 54,\n\tS2MPU02_REG_L9CTRL = 55,\n\tS2MPU02_REG_L10CTRL = 56,\n\tS2MPU02_REG_L11CTRL = 57,\n\tS2MPU02_REG_L12CTRL = 58,\n\tS2MPU02_REG_L13CTRL = 59,\n\tS2MPU02_REG_L14CTRL = 60,\n\tS2MPU02_REG_L15CTRL = 61,\n\tS2MPU02_REG_L16CTRL = 62,\n\tS2MPU02_REG_L17CTRL = 63,\n\tS2MPU02_REG_L18CTRL = 64,\n\tS2MPU02_REG_L19CTRL = 65,\n\tS2MPU02_REG_L20CTRL = 66,\n\tS2MPU02_REG_L21CTRL = 67,\n\tS2MPU02_REG_L22CTRL = 68,\n\tS2MPU02_REG_L23CTRL = 69,\n\tS2MPU02_REG_L24CTRL = 70,\n\tS2MPU02_REG_L25CTRL = 71,\n\tS2MPU02_REG_L26CTRL = 72,\n\tS2MPU02_REG_L27CTRL = 73,\n\tS2MPU02_REG_L28CTRL = 74,\n\tS2MPU02_REG_LDODSCH1 = 75,\n\tS2MPU02_REG_LDODSCH2 = 76,\n\tS2MPU02_REG_LDODSCH3 = 77,\n\tS2MPU02_REG_LDODSCH4 = 78,\n\tS2MPU02_REG_SELMIF = 79,\n\tS2MPU02_REG_RSVD11 = 80,\n\tS2MPU02_REG_RSVD12 = 81,\n\tS2MPU02_REG_RSVD13 = 82,\n\tS2MPU02_REG_DVSSEL = 83,\n\tS2MPU02_REG_DVSPTR = 84,\n\tS2MPU02_REG_DVSDATA = 85,\n};\n\nenum S2MPU02_regulators {\n\tS2MPU02_LDO1 = 0,\n\tS2MPU02_LDO2 = 1,\n\tS2MPU02_LDO3 = 2,\n\tS2MPU02_LDO4 = 3,\n\tS2MPU02_LDO5 = 4,\n\tS2MPU02_LDO6 = 5,\n\tS2MPU02_LDO7 = 6,\n\tS2MPU02_LDO8 = 7,\n\tS2MPU02_LDO9 = 8,\n\tS2MPU02_LDO10 = 9,\n\tS2MPU02_LDO11 = 10,\n\tS2MPU02_LDO12 = 11,\n\tS2MPU02_LDO13 = 12,\n\tS2MPU02_LDO14 = 13,\n\tS2MPU02_LDO15 = 14,\n\tS2MPU02_LDO16 = 15,\n\tS2MPU02_LDO17 = 16,\n\tS2MPU02_LDO18 = 17,\n\tS2MPU02_LDO19 = 18,\n\tS2MPU02_LDO20 = 19,\n\tS2MPU02_LDO21 = 20,\n\tS2MPU02_LDO22 = 21,\n\tS2MPU02_LDO23 = 22,\n\tS2MPU02_LDO24 = 23,\n\tS2MPU02_LDO25 = 24,\n\tS2MPU02_LDO26 = 25,\n\tS2MPU02_LDO27 = 26,\n\tS2MPU02_LDO28 = 27,\n\tS2MPU02_BUCK1 = 28,\n\tS2MPU02_BUCK2 = 29,\n\tS2MPU02_BUCK3 = 30,\n\tS2MPU02_BUCK4 = 31,\n\tS2MPU02_BUCK5 = 32,\n\tS2MPU02_BUCK6 = 33,\n\tS2MPU02_BUCK7 = 34,\n\tS2MPU02_REGULATOR_MAX = 35,\n};\n\nenum S2MPU05_reg {\n\tS2MPU05_REG_ID = 0,\n\tS2MPU05_REG_INT1 = 1,\n\tS2MPU05_REG_INT2 = 2,\n\tS2MPU05_REG_INT3 = 3,\n\tS2MPU05_REG_INT1M = 4,\n\tS2MPU05_REG_INT2M = 5,\n\tS2MPU05_REG_INT3M = 6,\n\tS2MPU05_REG_ST1 = 7,\n\tS2MPU05_REG_ST2 = 8,\n\tS2MPU05_REG_PWRONSRC = 9,\n\tS2MPU05_REG_OFFSRC = 10,\n\tS2MPU05_REG_BU_CHG = 11,\n\tS2MPU05_REG_RTC_BUF = 12,\n\tS2MPU05_REG_CTRL1 = 13,\n\tS2MPU05_REG_CTRL2 = 14,\n\tS2MPU05_REG_ETC_TEST = 15,\n\tS2MPU05_REG_OTP_ADRL = 16,\n\tS2MPU05_REG_OTP_ADRH = 17,\n\tS2MPU05_REG_OTP_DATA = 18,\n\tS2MPU05_REG_MON1SEL = 19,\n\tS2MPU05_REG_MON2SEL = 20,\n\tS2MPU05_REG_CTRL3 = 21,\n\tS2MPU05_REG_ETC_OTP = 22,\n\tS2MPU05_REG_UVLO = 23,\n\tS2MPU05_REG_TIME_CTRL1 = 24,\n\tS2MPU05_REG_TIME_CTRL2 = 25,\n\tS2MPU05_REG_B1CTRL1 = 26,\n\tS2MPU05_REG_B1CTRL2 = 27,\n\tS2MPU05_REG_B2CTRL1 = 28,\n\tS2MPU05_REG_B2CTRL2 = 29,\n\tS2MPU05_REG_B2CTRL3 = 30,\n\tS2MPU05_REG_B2CTRL4 = 31,\n\tS2MPU05_REG_B3CTRL1 = 32,\n\tS2MPU05_REG_B3CTRL2 = 33,\n\tS2MPU05_REG_B3CTRL3 = 34,\n\tS2MPU05_REG_B4CTRL1 = 35,\n\tS2MPU05_REG_B4CTRL2 = 36,\n\tS2MPU05_REG_B5CTRL1 = 37,\n\tS2MPU05_REG_B5CTRL2 = 38,\n\tS2MPU05_REG_BUCK_RAMP = 39,\n\tS2MPU05_REG_LDO_DVS1 = 40,\n\tS2MPU05_REG_LDO_DVS9 = 41,\n\tS2MPU05_REG_LDO_DVS10 = 42,\n\tS2MPU05_REG_L1CTRL = 43,\n\tS2MPU05_REG_L2CTRL = 44,\n\tS2MPU05_REG_L3CTRL = 45,\n\tS2MPU05_REG_L4CTRL = 46,\n\tS2MPU05_REG_L5CTRL = 47,\n\tS2MPU05_REG_L6CTRL = 48,\n\tS2MPU05_REG_L7CTRL = 49,\n\tS2MPU05_REG_L8CTRL = 50,\n\tS2MPU05_REG_L9CTRL1 = 51,\n\tS2MPU05_REG_L9CTRL2 = 52,\n\tS2MPU05_REG_L10CTRL = 53,\n\tS2MPU05_REG_L11CTRL1 = 54,\n\tS2MPU05_REG_L11CTRL2 = 55,\n\tS2MPU05_REG_L12CTRL = 56,\n\tS2MPU05_REG_L13CTRL = 57,\n\tS2MPU05_REG_L14CTRL = 58,\n\tS2MPU05_REG_L15CTRL = 59,\n\tS2MPU05_REG_L16CTRL = 60,\n\tS2MPU05_REG_L17CTRL1 = 61,\n\tS2MPU05_REG_L17CTRL2 = 62,\n\tS2MPU05_REG_L18CTRL1 = 63,\n\tS2MPU05_REG_L18CTRL2 = 64,\n\tS2MPU05_REG_L19CTRL = 65,\n\tS2MPU05_REG_L20CTRL = 66,\n\tS2MPU05_REG_L21CTRL = 67,\n\tS2MPU05_REG_L22CTRL = 68,\n\tS2MPU05_REG_L23CTRL = 69,\n\tS2MPU05_REG_L24CTRL = 70,\n\tS2MPU05_REG_L25CTRL = 71,\n\tS2MPU05_REG_L26CTRL = 72,\n\tS2MPU05_REG_L27CTRL = 73,\n\tS2MPU05_REG_L28CTRL = 74,\n\tS2MPU05_REG_L29CTRL = 75,\n\tS2MPU05_REG_L30CTRL = 76,\n\tS2MPU05_REG_L31CTRL = 77,\n\tS2MPU05_REG_L32CTRL = 78,\n\tS2MPU05_REG_L33CTRL = 79,\n\tS2MPU05_REG_L34CTRL = 80,\n\tS2MPU05_REG_L35CTRL = 81,\n\tS2MPU05_REG_LDO_DSCH1 = 82,\n\tS2MPU05_REG_LDO_DSCH2 = 83,\n\tS2MPU05_REG_LDO_DSCH3 = 84,\n\tS2MPU05_REG_LDO_DSCH4 = 85,\n\tS2MPU05_REG_LDO_DSCH5 = 86,\n\tS2MPU05_REG_LDO_CTRL1 = 87,\n\tS2MPU05_REG_LDO_CTRL2 = 88,\n\tS2MPU05_REG_TCXO_CTRL = 89,\n\tS2MPU05_REG_SELMIF = 90,\n};\n\nenum S2MPU05_regulators {\n\tS2MPU05_LDO1 = 0,\n\tS2MPU05_LDO2 = 1,\n\tS2MPU05_LDO3 = 2,\n\tS2MPU05_LDO4 = 3,\n\tS2MPU05_LDO5 = 4,\n\tS2MPU05_LDO6 = 5,\n\tS2MPU05_LDO7 = 6,\n\tS2MPU05_LDO8 = 7,\n\tS2MPU05_LDO9 = 8,\n\tS2MPU05_LDO10 = 9,\n\tS2MPU05_LDO11 = 10,\n\tS2MPU05_LDO12 = 11,\n\tS2MPU05_LDO13 = 12,\n\tS2MPU05_LDO14 = 13,\n\tS2MPU05_LDO15 = 14,\n\tS2MPU05_LDO16 = 15,\n\tS2MPU05_LDO17 = 16,\n\tS2MPU05_LDO18 = 17,\n\tS2MPU05_LDO19 = 18,\n\tS2MPU05_LDO20 = 19,\n\tS2MPU05_LDO21 = 20,\n\tS2MPU05_LDO22 = 21,\n\tS2MPU05_LDO23 = 22,\n\tS2MPU05_LDO24 = 23,\n\tS2MPU05_LDO25 = 24,\n\tS2MPU05_LDO26 = 25,\n\tS2MPU05_LDO27 = 26,\n\tS2MPU05_LDO28 = 27,\n\tS2MPU05_LDO29 = 28,\n\tS2MPU05_LDO30 = 29,\n\tS2MPU05_LDO31 = 30,\n\tS2MPU05_LDO32 = 31,\n\tS2MPU05_LDO33 = 32,\n\tS2MPU05_LDO34 = 33,\n\tS2MPU05_LDO35 = 34,\n\tS2MPU05_BUCK1 = 35,\n\tS2MPU05_BUCK2 = 36,\n\tS2MPU05_BUCK3 = 37,\n\tS2MPU05_BUCK4 = 38,\n\tS2MPU05_BUCK5 = 39,\n\tS2MPU05_REGULATOR_MAX = 40,\n};\n\nenum SCI_CLKS {\n\tSCI_FCK = 0,\n\tSCI_SCK = 1,\n\tSCI_BRG_INT = 2,\n\tSCI_SCIF_CLK = 3,\n\tSCI_FCK_DIV4 = 4,\n\tSCI_FCK_DIV16 = 5,\n\tSCI_FCK_DIV64 = 6,\n\tSCI_NUM_CLKS = 7,\n};\n\nenum SCI_PORT_TYPE {\n\tRSCI_PORT_SCIF16 = 128,\n\tRSCI_PORT_SCIF32 = 129,\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum TCCR_BIT {\n\tTCCR_TSRQ0 = 1,\n\tTCCR_TSRQ1 = 2,\n\tTCCR_TSRQ2 = 4,\n\tTCCR_TSRQ3 = 8,\n\tTCCR_TFEN = 256,\n\tTCCR_TFR = 512,\n};\n\nenum TD_STS_BIT {\n\tTD_TACT = 2147483648,\n\tTD_TDLE = 1073741824,\n\tTD_TFP1 = 536870912,\n\tTD_TFP0 = 268435456,\n\tTD_TFE = 134217728,\n\tTD_TWBI = 67108864,\n};\n\nenum TFA2_BIT {\n\tTFA2_TSV = 65535,\n\tTFA2_TST = 67043328,\n};\n\nenum TGC_BIT {\n\tTGC_TSM0 = 1,\n\tTGC_TSM1 = 2,\n\tTGC_TSM2 = 4,\n\tTGC_TSM3 = 8,\n\tTGC_TQP = 48,\n\tTGC_TQP_NONAVB = 0,\n\tTGC_TQP_AVBMODE1 = 16,\n\tTGC_TQP_AVBMODE2 = 48,\n\tTGC_TBD0 = 768,\n\tTGC_TBD1 = 12288,\n\tTGC_TBD2 = 196608,\n\tTGC_TBD3 = 3145728,\n};\n\nenum TIC_BIT {\n\tTIC_FTE0 = 1,\n\tTIC_FTE1 = 2,\n\tTIC_TFUE = 256,\n\tTIC_TFWE = 512,\n};\n\nenum TIS_BIT {\n\tTIS_FTF0 = 1,\n\tTIS_FTF1 = 2,\n\tTIS_TFUF = 256,\n\tTIS_TFWF = 512,\n\tTIS_RESERVED = 4293980400,\n};\n\nenum TPAUSER_BIT {\n\tTPAUSER_TPAUSE = 65535,\n\tTPAUSER_UNLIMITED = 0,\n};\n\nenum TRSCER_BIT {\n\tTRSCER_CNDCE = 2048,\n\tTRSCER_DLCCE = 1024,\n\tTRSCER_CDCE = 512,\n\tTRSCER_TROCE = 256,\n\tTRSCER_RMAFCE = 128,\n\tTRSCER_RRFCE = 16,\n\tTRSCER_RTLFCE = 8,\n\tTRSCER_RTSFCE = 4,\n\tTRSCER_PRECE = 2,\n\tTRSCER_CERFCE = 1,\n};\n\nenum TSR_BIT {\n\tTSR_CCS0 = 3,\n\tTSR_CCS1 = 12,\n\tTSR_TFFL = 1792,\n};\n\nenum TSU_ADSBSY_BIT {\n\tTSU_ADSBSY_0 = 1,\n};\n\nenum TSU_FWSLC_BIT {\n\tTSU_FWSLC_POSTENU = 8192,\n\tTSU_FWSLC_POSTENL = 4096,\n\tTSU_FWSLC_CAMSEL03 = 128,\n\tTSU_FWSLC_CAMSEL02 = 64,\n\tTSU_FWSLC_CAMSEL01 = 32,\n\tTSU_FWSLC_CAMSEL00 = 16,\n\tTSU_FWSLC_CAMSEL13 = 8,\n\tTSU_FWSLC_CAMSEL12 = 4,\n\tTSU_FWSLC_CAMSEL11 = 2,\n\tTSU_FWSLC_CAMSEL10 = 1,\n};\n\nenum TX_DS_TAGL_BIT {\n\tTX_DS = 4095,\n\tTX_TAGL = 61440,\n};\n\nenum TX_TAGH_TSR_BIT {\n\tTX_TAGH = 63,\n\tTX_TSR = 64,\n};\n\nenum UART_TX_FLAGS {\n\tUART_TX_NOSTOP = 1,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_NO_USER_FLAGS = 13,\n\t_SLAB_RECLAIM_ACCOUNT = 14,\n\t_SLAB_OBJECT_POISON = 15,\n\t_SLAB_CMPXCHG_DOUBLE = 16,\n\t_SLAB_NO_OBJ_EXT = 17,\n\t_SLAB_FLAGS_LAST_BIT = 18,\n};\n\nenum ab8500_cal_channels {\n\tAB8500_CAL_VMAIN = 0,\n\tAB8500_CAL_BTEMP = 1,\n\tAB8500_CAL_VBAT = 2,\n\tAB8500_CAL_IBAT = 3,\n\tAB8500_CAL_NR = 4,\n};\n\nenum ab8500_ext_regulator_id {\n\tAB8500_EXT_SUPPLY1 = 0,\n\tAB8500_EXT_SUPPLY2 = 1,\n\tAB8500_EXT_SUPPLY3 = 2,\n\tAB8500_NUM_EXT_REGULATORS = 3,\n};\n\nenum ab8500_gpadc_channel {\n\tAB8500_GPADC_CHAN_UNUSED = 0,\n\tAB8500_GPADC_CHAN_BAT_CTRL = 1,\n\tAB8500_GPADC_CHAN_BAT_TEMP = 2,\n\tAB8500_GPADC_CHAN_MAIN_CHARGER = 3,\n\tAB8500_GPADC_CHAN_ACC_DET_1 = 4,\n\tAB8500_GPADC_CHAN_ACC_DET_2 = 5,\n\tAB8500_GPADC_CHAN_ADC_AUX_1 = 6,\n\tAB8500_GPADC_CHAN_ADC_AUX_2 = 7,\n\tAB8500_GPADC_CHAN_VBAT_A = 8,\n\tAB8500_GPADC_CHAN_VBUS = 9,\n\tAB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT = 10,\n\tAB8500_GPADC_CHAN_USB_CHARGER_CURRENT = 11,\n\tAB8500_GPADC_CHAN_BACKUP_BAT = 12,\n\tAB8505_GPADC_CHAN_DIE_TEMP = 13,\n\tAB8500_GPADC_CHAN_ID = 14,\n\tAB8500_GPADC_CHAN_INTERNAL_TEST_1 = 15,\n\tAB8500_GPADC_CHAN_INTERNAL_TEST_2 = 16,\n\tAB8500_GPADC_CHAN_INTERNAL_TEST_3 = 17,\n\tAB8500_GPADC_CHAN_XTAL_TEMP = 18,\n\tAB8500_GPADC_CHAN_VBAT_TRUE_MEAS = 19,\n\tAB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT = 28,\n\tAB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT = 29,\n\tAB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT = 30,\n\tAB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT = 31,\n\tAB8500_GPADC_CHAN_IBAT_VIRTUAL = 255,\n};\n\nenum ab8500_regulator_id {\n\tAB8500_LDO_AUX1 = 0,\n\tAB8500_LDO_AUX2 = 1,\n\tAB8500_LDO_AUX3 = 2,\n\tAB8500_LDO_INTCORE = 3,\n\tAB8500_LDO_TVOUT = 4,\n\tAB8500_LDO_AUDIO = 5,\n\tAB8500_LDO_ANAMIC1 = 6,\n\tAB8500_LDO_ANAMIC2 = 7,\n\tAB8500_LDO_DMIC = 8,\n\tAB8500_LDO_ANA = 9,\n\tAB8500_NUM_REGULATORS = 10,\n};\n\nenum ab8500_regulator_reg {\n\tAB8500_REGUREQUESTCTRL2 = 0,\n\tAB8500_REGUREQUESTCTRL3 = 1,\n\tAB8500_REGUREQUESTCTRL4 = 2,\n\tAB8500_REGUSYSCLKREQ1HPVALID1 = 3,\n\tAB8500_REGUSYSCLKREQ1HPVALID2 = 4,\n\tAB8500_REGUHWHPREQ1VALID1 = 5,\n\tAB8500_REGUHWHPREQ1VALID2 = 6,\n\tAB8500_REGUHWHPREQ2VALID1 = 7,\n\tAB8500_REGUHWHPREQ2VALID2 = 8,\n\tAB8500_REGUSWHPREQVALID1 = 9,\n\tAB8500_REGUSWHPREQVALID2 = 10,\n\tAB8500_REGUSYSCLKREQVALID1 = 11,\n\tAB8500_REGUSYSCLKREQVALID2 = 12,\n\tAB8500_REGUMISC1 = 13,\n\tAB8500_VAUDIOSUPPLY = 14,\n\tAB8500_REGUCTRL1VAMIC = 15,\n\tAB8500_VPLLVANAREGU = 16,\n\tAB8500_VREFDDR = 17,\n\tAB8500_EXTSUPPLYREGU = 18,\n\tAB8500_VAUX12REGU = 19,\n\tAB8500_VRF1VAUX3REGU = 20,\n\tAB8500_VAUX1SEL = 21,\n\tAB8500_VAUX2SEL = 22,\n\tAB8500_VRF1VAUX3SEL = 23,\n\tAB8500_REGUCTRL2SPARE = 24,\n\tAB8500_REGUCTRLDISCH = 25,\n\tAB8500_REGUCTRLDISCH2 = 26,\n\tAB8500_NUM_REGULATOR_REGISTERS = 27,\n};\n\nenum ab8500_usb_link_status {\n\tUSB_LINK_NOT_CONFIGURED_8500 = 0,\n\tUSB_LINK_STD_HOST_NC_8500 = 1,\n\tUSB_LINK_STD_HOST_C_NS_8500 = 2,\n\tUSB_LINK_STD_HOST_C_S_8500 = 3,\n\tUSB_LINK_HOST_CHG_NM_8500 = 4,\n\tUSB_LINK_HOST_CHG_HS_8500 = 5,\n\tUSB_LINK_HOST_CHG_HS_CHIRP_8500 = 6,\n\tUSB_LINK_DEDICATED_CHG_8500 = 7,\n\tUSB_LINK_ACA_RID_A_8500 = 8,\n\tUSB_LINK_ACA_RID_B_8500 = 9,\n\tUSB_LINK_ACA_RID_C_NM_8500 = 10,\n\tUSB_LINK_ACA_RID_C_HS_8500 = 11,\n\tUSB_LINK_ACA_RID_C_HS_CHIRP_8500 = 12,\n\tUSB_LINK_HM_IDGND_8500 = 13,\n\tUSB_LINK_RESERVED_8500 = 14,\n\tUSB_LINK_NOT_VALID_LINK_8500 = 15,\n};\n\nenum ab8500_usb_mode {\n\tUSB_IDLE = 0,\n\tUSB_PERIPHERAL = 1,\n\tUSB_HOST = 2,\n\tUSB_DEDICATED_CHG = 3,\n\tUSB_UART = 4,\n};\n\nenum ab8500_version {\n\tAB8500_VERSION_AB8500 = 0,\n\tAB8500_VERSION_AB8505 = 1,\n\tAB8500_VERSION_AB9540 = 2,\n\tAB8500_VERSION_AB8540 = 4,\n\tAB8500_VERSION_UNDEFINED = 5,\n};\n\nenum ab8505_regulator_id {\n\tAB8505_LDO_AUX1 = 0,\n\tAB8505_LDO_AUX2 = 1,\n\tAB8505_LDO_AUX3 = 2,\n\tAB8505_LDO_AUX4 = 3,\n\tAB8505_LDO_AUX5 = 4,\n\tAB8505_LDO_AUX6 = 5,\n\tAB8505_LDO_INTCORE = 6,\n\tAB8505_LDO_ADC = 7,\n\tAB8505_LDO_AUDIO = 8,\n\tAB8505_LDO_ANAMIC1 = 9,\n\tAB8505_LDO_ANAMIC2 = 10,\n\tAB8505_LDO_AUX8 = 11,\n\tAB8505_LDO_ANA = 12,\n\tAB8505_NUM_REGULATORS = 13,\n};\n\nenum ab8505_regulator_reg {\n\tAB8505_REGUREQUESTCTRL1 = 0,\n\tAB8505_REGUREQUESTCTRL2 = 1,\n\tAB8505_REGUREQUESTCTRL3 = 2,\n\tAB8505_REGUREQUESTCTRL4 = 3,\n\tAB8505_REGUSYSCLKREQ1HPVALID1 = 4,\n\tAB8505_REGUSYSCLKREQ1HPVALID2 = 5,\n\tAB8505_REGUHWHPREQ1VALID1 = 6,\n\tAB8505_REGUHWHPREQ1VALID2 = 7,\n\tAB8505_REGUHWHPREQ2VALID1 = 8,\n\tAB8505_REGUHWHPREQ2VALID2 = 9,\n\tAB8505_REGUSWHPREQVALID1 = 10,\n\tAB8505_REGUSWHPREQVALID2 = 11,\n\tAB8505_REGUSYSCLKREQVALID1 = 12,\n\tAB8505_REGUSYSCLKREQVALID2 = 13,\n\tAB8505_REGUVAUX4REQVALID = 14,\n\tAB8505_REGUMISC1 = 15,\n\tAB8505_VAUDIOSUPPLY = 16,\n\tAB8505_REGUCTRL1VAMIC = 17,\n\tAB8505_VSMPSAREGU = 18,\n\tAB8505_VSMPSBREGU = 19,\n\tAB8505_VSAFEREGU = 20,\n\tAB8505_VPLLVANAREGU = 21,\n\tAB8505_EXTSUPPLYREGU = 22,\n\tAB8505_VAUX12REGU = 23,\n\tAB8505_VRF1VAUX3REGU = 24,\n\tAB8505_VSMPSASEL1 = 25,\n\tAB8505_VSMPSASEL2 = 26,\n\tAB8505_VSMPSASEL3 = 27,\n\tAB8505_VSMPSBSEL1 = 28,\n\tAB8505_VSMPSBSEL2 = 29,\n\tAB8505_VSMPSBSEL3 = 30,\n\tAB8505_VSAFESEL1 = 31,\n\tAB8505_VSAFESEL2 = 32,\n\tAB8505_VSAFESEL3 = 33,\n\tAB8505_VAUX1SEL = 34,\n\tAB8505_VAUX2SEL = 35,\n\tAB8505_VRF1VAUX3SEL = 36,\n\tAB8505_VAUX4REQCTRL = 37,\n\tAB8505_VAUX4REGU = 38,\n\tAB8505_VAUX4SEL = 39,\n\tAB8505_REGUCTRLDISCH = 40,\n\tAB8505_REGUCTRLDISCH2 = 41,\n\tAB8505_REGUCTRLDISCH3 = 42,\n\tAB8505_CTRLVAUX5 = 43,\n\tAB8505_CTRLVAUX6 = 44,\n\tAB8505_NUM_REGULATOR_REGISTERS = 45,\n};\n\nenum ab8505_usb_link_status {\n\tUSB_LINK_NOT_CONFIGURED_8505 = 0,\n\tUSB_LINK_STD_HOST_NC_8505 = 1,\n\tUSB_LINK_STD_HOST_C_NS_8505 = 2,\n\tUSB_LINK_STD_HOST_C_S_8505 = 3,\n\tUSB_LINK_CDP_8505 = 4,\n\tUSB_LINK_RESERVED0_8505 = 5,\n\tUSB_LINK_RESERVED1_8505 = 6,\n\tUSB_LINK_DEDICATED_CHG_8505 = 7,\n\tUSB_LINK_ACA_RID_A_8505 = 8,\n\tUSB_LINK_ACA_RID_B_8505 = 9,\n\tUSB_LINK_ACA_RID_C_NM_8505 = 10,\n\tUSB_LINK_RESERVED2_8505 = 11,\n\tUSB_LINK_RESERVED3_8505 = 12,\n\tUSB_LINK_HM_IDGND_8505 = 13,\n\tUSB_LINK_CHARGERPORT_NOT_OK_8505 = 14,\n\tUSB_LINK_CHARGER_DM_HIGH_8505 = 15,\n\tUSB_LINK_PHYEN_NO_VBUS_NO_IDGND_8505 = 16,\n\tUSB_LINK_STD_UPSTREAM_NO_IDGNG_NO_VBUS_8505 = 17,\n\tUSB_LINK_STD_UPSTREAM_8505 = 18,\n\tUSB_LINK_CHARGER_SE1_8505 = 19,\n\tUSB_LINK_CARKIT_CHGR_1_8505 = 20,\n\tUSB_LINK_CARKIT_CHGR_2_8505 = 21,\n\tUSB_LINK_ACA_DOCK_CHGR_8505 = 22,\n\tUSB_LINK_SAMSUNG_BOOT_CBL_PHY_EN_8505 = 23,\n\tUSB_LINK_SAMSUNG_BOOT_CBL_PHY_DISB_8505 = 24,\n\tUSB_LINK_SAMSUNG_UART_CBL_PHY_EN_8505 = 25,\n\tUSB_LINK_SAMSUNG_UART_CBL_PHY_DISB_8505 = 26,\n\tUSB_LINK_MOTOROLA_FACTORY_CBL_PHY_EN_8505 = 27,\n};\n\nenum abx500_gpio_pull_updown {\n\tABX500_GPIO_PULL_DOWN = 0,\n\tABX500_GPIO_PULL_NONE = 1,\n\tABX500_GPIO_PULL_UP = 3,\n};\n\nenum abx500_pin_func {\n\tABX500_DEFAULT = 0,\n\tABX500_ALT_A = 1,\n\tABX500_ALT_B = 2,\n\tABX500_ALT_C = 3,\n};\n\nenum adc_sort_mode {\n\tADC_DECREMENT = 0,\n\tADC_INCREMENT = 1,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum addr_type_t {\n\tUNICAST_ADDR = 0,\n\tMULTICAST_ADDR = 1,\n\tANYCAST_ADDR = 2,\n};\n\nenum ahci_imx_type {\n\tAHCI_IMX53 = 0,\n\tAHCI_IMX6Q = 1,\n\tAHCI_IMX6QP = 2,\n\tAHCI_IMX8QM = 3,\n};\n\nenum ahci_qoriq_type {\n\tAHCI_LS1021A = 0,\n\tAHCI_LS1028A = 1,\n\tAHCI_LS1043A = 2,\n\tAHCI_LS2080A = 3,\n\tAHCI_LS1046A = 4,\n\tAHCI_LS1088A = 5,\n\tAHCI_LS2088A = 6,\n\tAHCI_LX2160A = 7,\n};\n\nenum ak_ctrl_mode {\n\tPOWER_DOWN = 0,\n\tMODE_ONCE = 1,\n\tSELF_TEST = 2,\n\tFUSE_ROM = 3,\n\tMODE_END = 4,\n};\n\nenum ak_ctrl_reg_addr {\n\tST1 = 0,\n\tST2 = 1,\n\tCNTL = 2,\n\tASA_BASE = 3,\n\tMAX_REGS = 4,\n\tREGS_END = 5,\n};\n\nenum ak_ctrl_reg_mask {\n\tST1_DRDY = 0,\n\tST2_HOFL = 1,\n\tST2_DERR = 2,\n\tCNTL_MODE = 3,\n\tMASK_END = 4,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum ale_fields {\n\tMINOR_VER = 0,\n\tMAJOR_VER = 1,\n\tALE_ENTRIES = 2,\n\tALE_POLICERS = 3,\n\tPOL_PORT_MEN = 4,\n\tPOL_TRUNK_ID = 5,\n\tPOL_PORT_NUM = 6,\n\tPOL_PRI_MEN = 7,\n\tPOL_PRI_VAL = 8,\n\tPOL_OUI_MEN = 9,\n\tPOL_OUI_INDEX = 10,\n\tPOL_DST_MEN = 11,\n\tPOL_DST_INDEX = 12,\n\tPOL_SRC_MEN = 13,\n\tPOL_SRC_INDEX = 14,\n\tPOL_OVLAN_MEN = 15,\n\tPOL_OVLAN_INDEX = 16,\n\tPOL_IVLAN_MEN = 17,\n\tPOL_IVLAN_INDEX = 18,\n\tPOL_ETHERTYPE_MEN = 19,\n\tPOL_ETHERTYPE_INDEX = 20,\n\tPOL_IPSRC_MEN = 21,\n\tPOL_IPSRC_INDEX = 22,\n\tPOL_IPDST_MEN = 23,\n\tPOL_IPDST_INDEX = 24,\n\tPOL_EN = 25,\n\tPOL_RED_DROP_EN = 26,\n\tPOL_YELLOW_DROP_EN = 27,\n\tPOL_YELLOW_THRESH = 28,\n\tPOL_POL_MATCH_MODE = 29,\n\tPOL_PRIORITY_THREAD_EN = 30,\n\tPOL_MAC_ONLY_DEF_DIS = 31,\n\tPOL_TEST_CLR = 32,\n\tPOL_TEST_CLR_RED = 33,\n\tPOL_TEST_CLR_YELLOW = 34,\n\tPOL_TEST_CLR_SELECTED = 35,\n\tPOL_TEST_ENTRY = 36,\n\tPOL_STATUS_HIT = 37,\n\tPOL_STATUS_HIT_RED = 38,\n\tPOL_STATUS_HIT_YELLOW = 39,\n\tALE_DEFAULT_THREAD_EN = 40,\n\tALE_DEFAULT_THREAD_VAL = 41,\n\tALE_THREAD_CLASS_INDEX = 42,\n\tALE_THREAD_ENABLE = 43,\n\tALE_THREAD_VALUE = 44,\n\tALE_FIELDS_MAX = 45,\n};\n\nenum amba_vendor {\n\tAMBA_VENDOR_ARM = 65,\n\tAMBA_VENDOR_ST = 128,\n\tAMBA_VENDOR_QCOM = 81,\n\tAMBA_VENDOR_LSI = 182,\n};\n\nenum ap_pwrst {\n\tNO_PWRST = 0,\n\tAP_BOOT = 1,\n\tAP_EXECUTE = 2,\n\tAP_DEEP_SLEEP = 3,\n\tAP_SLEEP = 4,\n\tAP_IDLE = 5,\n\tAP_RESET = 6,\n};\n\nenum ap_pwrst_trans {\n\tPRCMU_AP_NO_CHANGE = 0,\n\tAPEXECUTE_TO_APSLEEP = 1,\n\tAPIDLE_TO_APSLEEP = 2,\n\tPRCMU_AP_SLEEP = 1,\n\tAPBOOT_TO_APEXECUTE = 3,\n\tAPEXECUTE_TO_APDEEPSLEEP = 4,\n\tPRCMU_AP_DEEP_SLEEP = 4,\n\tAPEXECUTE_TO_APIDLE = 5,\n\tPRCMU_AP_IDLE = 5,\n\tPRCMU_AP_DEEP_IDLE = 7,\n};\n\nenum ape_opp {\n\tAPE_OPP_INIT = 0,\n\tAPE_NO_CHANGE = 1,\n\tAPE_100_OPP = 2,\n\tAPE_50_OPP = 3,\n\tAPE_50_PARTLY_25_OPP = 255,\n};\n\nenum apq8064_functions {\n\tAPQ_MUX_cam_mclk = 0,\n\tAPQ_MUX_codec_mic_i2s = 1,\n\tAPQ_MUX_codec_spkr_i2s = 2,\n\tAPQ_MUX_gp_clk_0a = 3,\n\tAPQ_MUX_gp_clk_0b = 4,\n\tAPQ_MUX_gp_clk_1a = 5,\n\tAPQ_MUX_gp_clk_1b = 6,\n\tAPQ_MUX_gp_clk_2a = 7,\n\tAPQ_MUX_gp_clk_2b = 8,\n\tAPQ_MUX_gpio = 9,\n\tAPQ_MUX_gsbi1 = 10,\n\tAPQ_MUX_gsbi2 = 11,\n\tAPQ_MUX_gsbi3 = 12,\n\tAPQ_MUX_gsbi4 = 13,\n\tAPQ_MUX_gsbi4_cam_i2c = 14,\n\tAPQ_MUX_gsbi5 = 15,\n\tAPQ_MUX_gsbi5_spi_cs1 = 16,\n\tAPQ_MUX_gsbi5_spi_cs2 = 17,\n\tAPQ_MUX_gsbi5_spi_cs3 = 18,\n\tAPQ_MUX_gsbi6 = 19,\n\tAPQ_MUX_gsbi6_spi_cs1 = 20,\n\tAPQ_MUX_gsbi6_spi_cs2 = 21,\n\tAPQ_MUX_gsbi6_spi_cs3 = 22,\n\tAPQ_MUX_gsbi7 = 23,\n\tAPQ_MUX_gsbi7_spi_cs1 = 24,\n\tAPQ_MUX_gsbi7_spi_cs2 = 25,\n\tAPQ_MUX_gsbi7_spi_cs3 = 26,\n\tAPQ_MUX_gsbi_cam_i2c = 27,\n\tAPQ_MUX_hdmi = 28,\n\tAPQ_MUX_mi2s = 29,\n\tAPQ_MUX_riva_bt = 30,\n\tAPQ_MUX_riva_fm = 31,\n\tAPQ_MUX_riva_wlan = 32,\n\tAPQ_MUX_sdc2 = 33,\n\tAPQ_MUX_sdc4 = 34,\n\tAPQ_MUX_slimbus = 35,\n\tAPQ_MUX_spkr_i2s = 36,\n\tAPQ_MUX_tsif1 = 37,\n\tAPQ_MUX_tsif2 = 38,\n\tAPQ_MUX_usb2_hsic = 39,\n\tAPQ_MUX_ps_hold = 40,\n\tAPQ_MUX_NA = 41,\n};\n\nenum apq8084_functions {\n\tAPQ_MUX_adsp_ext = 0,\n\tAPQ_MUX_audio_ref = 1,\n\tAPQ_MUX_blsp_i2c1 = 2,\n\tAPQ_MUX_blsp_i2c2 = 3,\n\tAPQ_MUX_blsp_i2c3 = 4,\n\tAPQ_MUX_blsp_i2c4 = 5,\n\tAPQ_MUX_blsp_i2c5 = 6,\n\tAPQ_MUX_blsp_i2c6 = 7,\n\tAPQ_MUX_blsp_i2c7 = 8,\n\tAPQ_MUX_blsp_i2c8 = 9,\n\tAPQ_MUX_blsp_i2c9 = 10,\n\tAPQ_MUX_blsp_i2c10 = 11,\n\tAPQ_MUX_blsp_i2c11 = 12,\n\tAPQ_MUX_blsp_i2c12 = 13,\n\tAPQ_MUX_blsp_spi1 = 14,\n\tAPQ_MUX_blsp_spi1_cs1 = 15,\n\tAPQ_MUX_blsp_spi1_cs2 = 16,\n\tAPQ_MUX_blsp_spi1_cs3 = 17,\n\tAPQ_MUX_blsp_spi2 = 18,\n\tAPQ_MUX_blsp_spi3 = 19,\n\tAPQ_MUX_blsp_spi3_cs1 = 20,\n\tAPQ_MUX_blsp_spi3_cs2 = 21,\n\tAPQ_MUX_blsp_spi3_cs3 = 22,\n\tAPQ_MUX_blsp_spi4 = 23,\n\tAPQ_MUX_blsp_spi5 = 24,\n\tAPQ_MUX_blsp_spi6 = 25,\n\tAPQ_MUX_blsp_spi7 = 26,\n\tAPQ_MUX_blsp_spi8 = 27,\n\tAPQ_MUX_blsp_spi9 = 28,\n\tAPQ_MUX_blsp_spi10 = 29,\n\tAPQ_MUX_blsp_spi10_cs1 = 30,\n\tAPQ_MUX_blsp_spi10_cs2 = 31,\n\tAPQ_MUX_blsp_spi10_cs3 = 32,\n\tAPQ_MUX_blsp_spi11 = 33,\n\tAPQ_MUX_blsp_spi12 = 34,\n\tAPQ_MUX_blsp_uart1 = 35,\n\tAPQ_MUX_blsp_uart2 = 36,\n\tAPQ_MUX_blsp_uart3 = 37,\n\tAPQ_MUX_blsp_uart4 = 38,\n\tAPQ_MUX_blsp_uart5 = 39,\n\tAPQ_MUX_blsp_uart6 = 40,\n\tAPQ_MUX_blsp_uart7 = 41,\n\tAPQ_MUX_blsp_uart8 = 42,\n\tAPQ_MUX_blsp_uart9 = 43,\n\tAPQ_MUX_blsp_uart10 = 44,\n\tAPQ_MUX_blsp_uart11 = 45,\n\tAPQ_MUX_blsp_uart12 = 46,\n\tAPQ_MUX_blsp_uim1 = 47,\n\tAPQ_MUX_blsp_uim2 = 48,\n\tAPQ_MUX_blsp_uim3 = 49,\n\tAPQ_MUX_blsp_uim4 = 50,\n\tAPQ_MUX_blsp_uim5 = 51,\n\tAPQ_MUX_blsp_uim6 = 52,\n\tAPQ_MUX_blsp_uim7 = 53,\n\tAPQ_MUX_blsp_uim8 = 54,\n\tAPQ_MUX_blsp_uim9 = 55,\n\tAPQ_MUX_blsp_uim10 = 56,\n\tAPQ_MUX_blsp_uim11 = 57,\n\tAPQ_MUX_blsp_uim12 = 58,\n\tAPQ_MUX_cam_mclk0 = 59,\n\tAPQ_MUX_cam_mclk1 = 60,\n\tAPQ_MUX_cam_mclk2 = 61,\n\tAPQ_MUX_cam_mclk3 = 62,\n\tAPQ_MUX_cci_async = 63,\n\tAPQ_MUX_cci_async_in0 = 64,\n\tAPQ_MUX_cci_i2c0 = 65,\n\tAPQ_MUX_cci_i2c1 = 66,\n\tAPQ_MUX_cci_timer0 = 67,\n\tAPQ_MUX_cci_timer1 = 68,\n\tAPQ_MUX_cci_timer2 = 69,\n\tAPQ_MUX_cci_timer3 = 70,\n\tAPQ_MUX_cci_timer4 = 71,\n\tAPQ_MUX_edp_hpd = 72,\n\tAPQ_MUX_gcc_gp1 = 73,\n\tAPQ_MUX_gcc_gp2 = 74,\n\tAPQ_MUX_gcc_gp3 = 75,\n\tAPQ_MUX_gcc_obt = 76,\n\tAPQ_MUX_gcc_vtt = 77,\n\tAPQ_MUX_gp_mn = 78,\n\tAPQ_MUX_gp_pdm0 = 79,\n\tAPQ_MUX_gp_pdm1 = 80,\n\tAPQ_MUX_gp_pdm2 = 81,\n\tAPQ_MUX_gp0_clk = 82,\n\tAPQ_MUX_gp1_clk = 83,\n\tAPQ_MUX_gpio___2 = 84,\n\tAPQ_MUX_hdmi_cec = 85,\n\tAPQ_MUX_hdmi_ddc = 86,\n\tAPQ_MUX_hdmi_dtest = 87,\n\tAPQ_MUX_hdmi_hpd = 88,\n\tAPQ_MUX_hdmi_rcv = 89,\n\tAPQ_MUX_hsic = 90,\n\tAPQ_MUX_ldo_en = 91,\n\tAPQ_MUX_ldo_update = 92,\n\tAPQ_MUX_mdp_vsync = 93,\n\tAPQ_MUX_pci_e0 = 94,\n\tAPQ_MUX_pci_e0_n = 95,\n\tAPQ_MUX_pci_e0_rst = 96,\n\tAPQ_MUX_pci_e1 = 97,\n\tAPQ_MUX_pci_e1_rst = 98,\n\tAPQ_MUX_pci_e1_rst_n = 99,\n\tAPQ_MUX_pci_e1_clkreq_n = 100,\n\tAPQ_MUX_pri_mi2s = 101,\n\tAPQ_MUX_qua_mi2s = 102,\n\tAPQ_MUX_sata_act = 103,\n\tAPQ_MUX_sata_devsleep = 104,\n\tAPQ_MUX_sata_devsleep_n = 105,\n\tAPQ_MUX_sd_write = 106,\n\tAPQ_MUX_sdc_emmc_mode = 107,\n\tAPQ_MUX_sdc3 = 108,\n\tAPQ_MUX_sdc4___2 = 109,\n\tAPQ_MUX_sec_mi2s = 110,\n\tAPQ_MUX_slimbus___2 = 111,\n\tAPQ_MUX_spdif_tx = 112,\n\tAPQ_MUX_spkr_i2s___2 = 113,\n\tAPQ_MUX_spkr_i2s_ws = 114,\n\tAPQ_MUX_spss_geni = 115,\n\tAPQ_MUX_ter_mi2s = 116,\n\tAPQ_MUX_tsif1___2 = 117,\n\tAPQ_MUX_tsif2___2 = 118,\n\tAPQ_MUX_uim = 119,\n\tAPQ_MUX_uim_batt_alarm = 120,\n\tAPQ_MUX_NA___2 = 121,\n};\n\nenum arch_timer_access {\n\tPHYS_ACCESS = 0,\n\tVIRT_ACCESS = 1,\n};\n\nenum arch_timer_ppi_nr {\n\tARCH_TIMER_PHYS_SECURE_PPI = 0,\n\tARCH_TIMER_PHYS_NONSECURE_PPI = 1,\n\tARCH_TIMER_VIRT_PPI = 2,\n\tARCH_TIMER_HYP_PPI = 3,\n\tARCH_TIMER_HYP_VIRT_PPI = 4,\n\tARCH_TIMER_MAX_TIMER_PPI = 5,\n};\n\nenum arch_timer_reg {\n\tARCH_TIMER_REG_CTRL = 0,\n\tARCH_TIMER_REG_CVAL = 1,\n};\n\nenum arm_opp {\n\tARM_OPP_INIT = 0,\n\tARM_NO_CHANGE = 1,\n\tARM_100_OPP = 2,\n\tARM_50_OPP = 3,\n\tARM_MAX_OPP = 4,\n\tARM_MAX_FREQ100OPP = 5,\n\tARM_EXTCLK = 7,\n};\n\nenum arm_regset {\n\tREGSET_GPR = 0,\n\tREGSET_FPR = 1,\n\tREGSET_VFP = 2,\n};\n\nenum arm_smccc_conduit {\n\tSMCCC_CONDUIT_NONE = 0,\n\tSMCCC_CONDUIT_SMC = 1,\n\tSMCCC_CONDUIT_HVC = 2,\n};\n\nenum armada_xp_variant {\n\tV_MV78230 = 1,\n\tV_MV78260 = 2,\n\tV_MV78460 = 4,\n\tV_MV78230_PLUS = 7,\n\tV_MV78260_PLUS = 6,\n\tV_98DX3236 = 8,\n\tV_98DX3336 = 16,\n\tV_98DX4251 = 32,\n\tV_98DX3236_PLUS = 56,\n};\n\nenum armpmu_attr_groups {\n\tARMPMU_ATTR_GROUP_COMMON = 0,\n\tARMPMU_ATTR_GROUP_EVENTS = 1,\n\tARMPMU_ATTR_GROUP_FORMATS = 2,\n\tARMPMU_ATTR_GROUP_CAPS = 3,\n\tARMPMU_NR_ATTR_GROUPS = 4,\n};\n\nenum as3711_bl_type {\n\tAS3711_BL_SU1 = 0,\n\tAS3711_BL_SU2 = 1,\n};\n\nenum as3711_su2_fbprot {\n\tAS3711_SU2_LX_SD4 = 0,\n\tAS3711_SU2_GPIO2 = 1,\n\tAS3711_SU2_GPIO3 = 2,\n\tAS3711_SU2_GPIO4 = 3,\n};\n\nenum as3711_su2_feedback {\n\tAS3711_SU2_VOLTAGE = 0,\n\tAS3711_SU2_CURR1 = 1,\n\tAS3711_SU2_CURR2 = 2,\n\tAS3711_SU2_CURR3 = 3,\n\tAS3711_SU2_CURR_AUTO = 4,\n};\n\nenum as3722_irq {\n\tAS3722_IRQ_LID = 0,\n\tAS3722_IRQ_ACOK = 1,\n\tAS3722_IRQ_ENABLE1 = 2,\n\tAS3722_IRQ_OCCUR_ALARM_SD0 = 3,\n\tAS3722_IRQ_ONKEY_LONG_PRESS = 4,\n\tAS3722_IRQ_ONKEY = 5,\n\tAS3722_IRQ_OVTMP = 6,\n\tAS3722_IRQ_LOWBAT = 7,\n\tAS3722_IRQ_SD0_LV = 8,\n\tAS3722_IRQ_SD1_LV = 9,\n\tAS3722_IRQ_SD2_LV = 10,\n\tAS3722_IRQ_PWM1_OV_PROT = 11,\n\tAS3722_IRQ_PWM2_OV_PROT = 12,\n\tAS3722_IRQ_ENABLE2 = 13,\n\tAS3722_IRQ_SD6_LV = 14,\n\tAS3722_IRQ_RTC_REP = 15,\n\tAS3722_IRQ_RTC_ALARM = 16,\n\tAS3722_IRQ_GPIO1 = 17,\n\tAS3722_IRQ_GPIO2 = 18,\n\tAS3722_IRQ_GPIO3 = 19,\n\tAS3722_IRQ_GPIO4 = 20,\n\tAS3722_IRQ_GPIO5 = 21,\n\tAS3722_IRQ_WATCHDOG = 22,\n\tAS3722_IRQ_ENABLE3 = 23,\n\tAS3722_IRQ_TEMP_SD0_SHUTDOWN = 24,\n\tAS3722_IRQ_TEMP_SD1_SHUTDOWN = 25,\n\tAS3722_IRQ_TEMP_SD2_SHUTDOWN = 26,\n\tAS3722_IRQ_TEMP_SD0_ALARM = 27,\n\tAS3722_IRQ_TEMP_SD1_ALARM = 28,\n\tAS3722_IRQ_TEMP_SD6_ALARM = 29,\n\tAS3722_IRQ_OCCUR_ALARM_SD6 = 30,\n\tAS3722_IRQ_ADC = 31,\n\tAS3722_IRQ_MAX = 32,\n};\n\nenum as3722_pinmux_option {\n\tAS3722_PINMUX_GPIO = 0,\n\tAS3722_PINMUX_INTERRUPT_OUT = 1,\n\tAS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,\n\tAS3722_PINMUX_GPIO_INTERRUPT = 3,\n\tAS3722_PINMUX_PWM_INPUT = 4,\n\tAS3722_PINMUX_VOLTAGE_IN_STBY = 5,\n\tAS3722_PINMUX_OC_PG_SD0 = 6,\n\tAS3722_PINMUX_PG_OUT = 7,\n\tAS3722_PINMUX_CLK32K_OUT = 8,\n\tAS3722_PINMUX_WATCHDOG_INPUT = 9,\n\tAS3722_PINMUX_SOFT_RESET_IN = 11,\n\tAS3722_PINMUX_PWM_OUTPUT = 12,\n\tAS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,\n\tAS3722_PINMUX_OC_PG_SD6 = 14,\n};\n\nenum as3722_regulators_id {\n\tAS3722_REGULATOR_ID_SD0 = 0,\n\tAS3722_REGULATOR_ID_SD1 = 1,\n\tAS3722_REGULATOR_ID_SD2 = 2,\n\tAS3722_REGULATOR_ID_SD3 = 3,\n\tAS3722_REGULATOR_ID_SD4 = 4,\n\tAS3722_REGULATOR_ID_SD5 = 5,\n\tAS3722_REGULATOR_ID_SD6 = 6,\n\tAS3722_REGULATOR_ID_LDO0 = 7,\n\tAS3722_REGULATOR_ID_LDO1 = 8,\n\tAS3722_REGULATOR_ID_LDO2 = 9,\n\tAS3722_REGULATOR_ID_LDO3 = 10,\n\tAS3722_REGULATOR_ID_LDO4 = 11,\n\tAS3722_REGULATOR_ID_LDO5 = 12,\n\tAS3722_REGULATOR_ID_LDO6 = 13,\n\tAS3722_REGULATOR_ID_LDO7 = 14,\n\tAS3722_REGULATOR_ID_LDO9 = 15,\n\tAS3722_REGULATOR_ID_LDO10 = 16,\n\tAS3722_REGULATOR_ID_LDO11 = 17,\n\tAS3722_REGULATOR_ID_MAX = 18,\n};\n\nenum asahi_compass_chipset {\n\tAK8975 = 0,\n\tAK8963 = 1,\n\tAK09911 = 2,\n\tAK09912 = 3,\n\tAK09916 = 4,\n\tAK09918 = 5,\n};\n\nenum asn1_class {\n\tASN1_UNIV = 0,\n\tASN1_APPL = 1,\n\tASN1_CONT = 2,\n\tASN1_PRIV = 3,\n};\n\nenum asn1_method {\n\tASN1_PRIM = 0,\n\tASN1_CONS = 1,\n};\n\nenum asn1_opcode {\n\tASN1_OP_MATCH = 0,\n\tASN1_OP_MATCH_OR_SKIP = 1,\n\tASN1_OP_MATCH_ACT = 2,\n\tASN1_OP_MATCH_ACT_OR_SKIP = 3,\n\tASN1_OP_MATCH_JUMP = 4,\n\tASN1_OP_MATCH_JUMP_OR_SKIP = 5,\n\tASN1_OP_MATCH_ANY = 8,\n\tASN1_OP_MATCH_ANY_OR_SKIP = 9,\n\tASN1_OP_MATCH_ANY_ACT = 10,\n\tASN1_OP_MATCH_ANY_ACT_OR_SKIP = 11,\n\tASN1_OP_COND_MATCH_OR_SKIP = 17,\n\tASN1_OP_COND_MATCH_ACT_OR_SKIP = 19,\n\tASN1_OP_COND_MATCH_JUMP_OR_SKIP = 21,\n\tASN1_OP_COND_MATCH_ANY = 24,\n\tASN1_OP_COND_MATCH_ANY_OR_SKIP = 25,\n\tASN1_OP_COND_MATCH_ANY_ACT = 26,\n\tASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 27,\n\tASN1_OP_COND_FAIL = 28,\n\tASN1_OP_COMPLETE = 29,\n\tASN1_OP_ACT = 30,\n\tASN1_OP_MAYBE_ACT = 31,\n\tASN1_OP_END_SEQ = 32,\n\tASN1_OP_END_SET = 33,\n\tASN1_OP_END_SEQ_OF = 34,\n\tASN1_OP_END_SET_OF = 35,\n\tASN1_OP_END_SEQ_ACT = 36,\n\tASN1_OP_END_SET_ACT = 37,\n\tASN1_OP_END_SEQ_OF_ACT = 38,\n\tASN1_OP_END_SET_OF_ACT = 39,\n\tASN1_OP_RETURN = 40,\n\tASN1_OP__NR = 41,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\nenum asp_netfilt_reg_type {\n\tASP_NETFILT_MATCH = 0,\n\tASP_NETFILT_MASK = 1,\n\tASP_NETFILT_MAX = 2,\n};\n\nenum asp_rx_filter_id {\n\tASP_RX_FILTER_MDA_PROMISC = 0,\n\tASP_RX_FILTER_MDA_ALLMULTI = 1,\n\tASP_RX_FILTER_MDA_BROADCAST = 2,\n\tASP_RX_FILTER_MDA_OWN_ADDR = 3,\n\tASP_RX_FILTER_MDA_RES_MAX = 4,\n};\n\nenum asp_rx_net_filter_block {\n\tASP_RX_FILTER_NET_L2 = 0,\n\tASP_RX_FILTER_NET_L3_0 = 1,\n\tASP_RX_FILTER_NET_L3_1 = 2,\n\tASP_RX_FILTER_NET_L4 = 3,\n\tASP_RX_FILTER_NET_BLOCK_MAX = 4,\n};\n\nenum aspeed_pin_config_map_type {\n\tMAP_TYPE_ARG = 0,\n\tMAP_TYPE_VAL = 1,\n};\n\nenum aspeed_sgpio_reg {\n\treg_val = 0,\n\treg_rdata = 1,\n\treg_irq_enable = 2,\n\treg_irq_type0 = 3,\n\treg_irq_type1 = 4,\n\treg_irq_type2 = 5,\n\treg_irq_status = 6,\n\treg_tolerance = 7,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum asymmetric_payload_bits {\n\tasym_crypto = 0,\n\tasym_subtype = 1,\n\tasym_key_ids = 2,\n\tasym_auth = 3,\n};\n\nenum at91_mux {\n\tAT91_MUX_GPIO = 0,\n\tAT91_MUX_PERIPH_A = 1,\n\tAT91_MUX_PERIPH_B = 2,\n\tAT91_MUX_PERIPH_C = 3,\n\tAT91_MUX_PERIPH_D = 4,\n};\n\nenum at91_pm_eth {\n\tAT91_PM_G_ETH = 0,\n\tAT91_PM_E_ETH = 1,\n\tAT91_PM_MAX_ETH = 2,\n};\n\nenum at91_pm_eth_clk {\n\tAT91_PM_ETH_PCLK = 0,\n\tAT91_PM_ETH_HCLK = 1,\n\tAT91_PM_ETH_MAX_CLK = 2,\n};\n\nenum at91_pm_iomaps {\n\tAT91_PM_IOMAP_SHDWC = 0,\n\tAT91_PM_IOMAP_SFRBU = 1,\n\tAT91_PM_IOMAP_ETHC = 2,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nenum ata_quirks {\n\t__ATA_QUIRK_DIAGNOSTIC = 0,\n\t__ATA_QUIRK_NODMA = 1,\n\t__ATA_QUIRK_NONCQ = 2,\n\t__ATA_QUIRK_BROKEN_HPA = 3,\n\t__ATA_QUIRK_DISABLE = 4,\n\t__ATA_QUIRK_HPA_SIZE = 5,\n\t__ATA_QUIRK_IVB = 6,\n\t__ATA_QUIRK_STUCK_ERR = 7,\n\t__ATA_QUIRK_BRIDGE_OK = 8,\n\t__ATA_QUIRK_ATAPI_MOD16_DMA = 9,\n\t__ATA_QUIRK_FIRMWARE_WARN = 10,\n\t__ATA_QUIRK_1_5_GBPS = 11,\n\t__ATA_QUIRK_NOSETXFER = 12,\n\t__ATA_QUIRK_BROKEN_FPDMA_AA = 13,\n\t__ATA_QUIRK_DUMP_ID = 14,\n\t__ATA_QUIRK_MAX_SEC_LBA48 = 15,\n\t__ATA_QUIRK_ATAPI_DMADIR = 16,\n\t__ATA_QUIRK_NO_NCQ_TRIM = 17,\n\t__ATA_QUIRK_NOLPM = 18,\n\t__ATA_QUIRK_WD_BROKEN_LPM = 19,\n\t__ATA_QUIRK_ZERO_AFTER_TRIM = 20,\n\t__ATA_QUIRK_NO_DMA_LOG = 21,\n\t__ATA_QUIRK_NOTRIM = 22,\n\t__ATA_QUIRK_MAX_SEC = 23,\n\t__ATA_QUIRK_MAX_TRIM_128M = 24,\n\t__ATA_QUIRK_NO_NCQ_ON_ATI = 25,\n\t__ATA_QUIRK_NO_LPM_ON_ATI = 26,\n\t__ATA_QUIRK_NO_ID_DEV_LOG = 27,\n\t__ATA_QUIRK_NO_LOG_DIR = 28,\n\t__ATA_QUIRK_NO_FUA = 29,\n\t__ATA_QUIRK_MAX = 30,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum atc_status {\n\tAT_XDMAC_CHAN_IS_CYCLIC = 0,\n\tAT_XDMAC_CHAN_IS_PAUSED = 1,\n\tAT_XDMAC_CHAN_IS_PAUSED_INTERNAL = 2,\n};\n\nenum atc_status___2 {\n\tATC_IS_PAUSED = 1,\n\tATC_IS_CYCLIC = 24,\n};\n\nenum atmci_pdc_buf {\n\tPDC_FIRST_BUF = 0,\n\tPDC_SECOND_BUF = 1,\n};\n\nenum atmci_xfer_dir {\n\tXFER_RECEIVE = 0,\n\tXFER_TRANSMIT = 1,\n};\n\nenum atmel_mci_state {\n\tSTATE_IDLE___2 = 0,\n\tSTATE_SENDING_CMD = 1,\n\tSTATE_DATA_XFER = 2,\n\tSTATE_WAITING_NOTBUSY = 3,\n\tSTATE_SENDING_STOP = 4,\n\tSTATE_END_REQUEST = 5,\n};\n\nenum atmel_nand_rb_type {\n\tATMEL_NAND_NO_RB = 0,\n\tATMEL_NAND_NATIVE_RB = 1,\n\tATMEL_NAND_GPIO_RB = 2,\n};\n\nenum atmel_nfc_data_xfer {\n\tATMEL_NFC_NO_DATA = 0,\n\tATMEL_NFC_READ_DATA = 1,\n\tATMEL_NFC_WRITE_DATA = 2,\n};\n\nenum attr_id_t {\n\tattr_errors_magic = 0,\n\tattr_errors_node = 1,\n\tattr_errors_crc = 2,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum autofs_notify {\n\tNFY_NONE = 0,\n\tNFY_MOUNT = 1,\n\tNFY_EXPIRE = 2,\n};\n\nenum aux_snapshot {\n\tAUX_SNAPSHOT0 = 16,\n\tAUX_SNAPSHOT1 = 32,\n\tAUX_SNAPSHOT2 = 64,\n\tAUX_SNAPSHOT3 = 128,\n};\n\nenum axp15060_irqs {\n\tAXP15060_IRQ_DIE_TEMP_HIGH_LV1 = 1,\n\tAXP15060_IRQ_DIE_TEMP_HIGH_LV2 = 2,\n\tAXP15060_IRQ_DCDC1_V_LOW = 3,\n\tAXP15060_IRQ_DCDC2_V_LOW = 4,\n\tAXP15060_IRQ_DCDC3_V_LOW = 5,\n\tAXP15060_IRQ_DCDC4_V_LOW = 6,\n\tAXP15060_IRQ_DCDC5_V_LOW = 7,\n\tAXP15060_IRQ_DCDC6_V_LOW = 8,\n\tAXP15060_IRQ_PEK_LONG = 9,\n\tAXP15060_IRQ_PEK_SHORT = 10,\n\tAXP15060_IRQ_GPIO1_INPUT = 11,\n\tAXP15060_IRQ_PEK_FAL_EDGE = 12,\n\tAXP15060_IRQ_PEK_RIS_EDGE = 13,\n\tAXP15060_IRQ_GPIO2_INPUT = 14,\n};\n\nenum axp192_irqs {\n\tAXP192_IRQ_ACIN_OVER_V = 1,\n\tAXP192_IRQ_ACIN_PLUGIN = 2,\n\tAXP192_IRQ_ACIN_REMOVAL = 3,\n\tAXP192_IRQ_VBUS_OVER_V = 4,\n\tAXP192_IRQ_VBUS_PLUGIN = 5,\n\tAXP192_IRQ_VBUS_REMOVAL = 6,\n\tAXP192_IRQ_VBUS_V_LOW = 7,\n\tAXP192_IRQ_BATT_PLUGIN = 8,\n\tAXP192_IRQ_BATT_REMOVAL = 9,\n\tAXP192_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP192_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP192_IRQ_CHARG = 12,\n\tAXP192_IRQ_CHARG_DONE = 13,\n\tAXP192_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP192_IRQ_BATT_TEMP_LOW = 15,\n\tAXP192_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP192_IRQ_CHARG_I_LOW = 17,\n\tAXP192_IRQ_DCDC1_V_LONG = 18,\n\tAXP192_IRQ_DCDC2_V_LONG = 19,\n\tAXP192_IRQ_DCDC3_V_LONG = 20,\n\tAXP192_IRQ_PEK_SHORT = 22,\n\tAXP192_IRQ_PEK_LONG = 23,\n\tAXP192_IRQ_N_OE_PWR_ON = 24,\n\tAXP192_IRQ_N_OE_PWR_OFF = 25,\n\tAXP192_IRQ_VBUS_VALID = 26,\n\tAXP192_IRQ_VBUS_NOT_VALID = 27,\n\tAXP192_IRQ_VBUS_SESS_VALID = 28,\n\tAXP192_IRQ_VBUS_SESS_END = 29,\n\tAXP192_IRQ_LOW_PWR_LVL = 31,\n\tAXP192_IRQ_TIMER = 32,\n\tAXP192_IRQ_GPIO2_INPUT = 37,\n\tAXP192_IRQ_GPIO1_INPUT = 38,\n\tAXP192_IRQ_GPIO0_INPUT = 39,\n};\n\nenum axp20x_variants {\n\tAXP152_ID = 0,\n\tAXP192_ID = 1,\n\tAXP202_ID = 2,\n\tAXP209_ID = 3,\n\tAXP221_ID = 4,\n\tAXP223_ID = 5,\n\tAXP288_ID = 6,\n\tAXP313A_ID = 7,\n\tAXP323_ID = 8,\n\tAXP717_ID = 9,\n\tAXP803_ID = 10,\n\tAXP806_ID = 11,\n\tAXP809_ID = 12,\n\tAXP813_ID = 13,\n\tAXP15060_ID = 14,\n\tNR_AXP20X_VARIANTS = 15,\n};\n\nenum axp22x_irqs {\n\tAXP22X_IRQ_ACIN_OVER_V = 1,\n\tAXP22X_IRQ_ACIN_PLUGIN = 2,\n\tAXP22X_IRQ_ACIN_REMOVAL = 3,\n\tAXP22X_IRQ_VBUS_OVER_V = 4,\n\tAXP22X_IRQ_VBUS_PLUGIN = 5,\n\tAXP22X_IRQ_VBUS_REMOVAL = 6,\n\tAXP22X_IRQ_VBUS_V_LOW = 7,\n\tAXP22X_IRQ_BATT_PLUGIN = 8,\n\tAXP22X_IRQ_BATT_REMOVAL = 9,\n\tAXP22X_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP22X_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP22X_IRQ_CHARG = 12,\n\tAXP22X_IRQ_CHARG_DONE = 13,\n\tAXP22X_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP22X_IRQ_BATT_TEMP_LOW = 15,\n\tAXP22X_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP22X_IRQ_PEK_SHORT = 17,\n\tAXP22X_IRQ_PEK_LONG = 18,\n\tAXP22X_IRQ_LOW_PWR_LVL1 = 19,\n\tAXP22X_IRQ_LOW_PWR_LVL2 = 20,\n\tAXP22X_IRQ_TIMER = 21,\n\tAXP22X_IRQ_PEK_FAL_EDGE = 22,\n\tAXP22X_IRQ_PEK_RIS_EDGE = 23,\n\tAXP22X_IRQ_GPIO1_INPUT = 24,\n\tAXP22X_IRQ_GPIO0_INPUT = 25,\n};\n\nenum axp288_irqs {\n\tAXP288_IRQ_VBUS_FALL = 2,\n\tAXP288_IRQ_VBUS_RISE = 3,\n\tAXP288_IRQ_OV = 4,\n\tAXP288_IRQ_FALLING_ALT = 5,\n\tAXP288_IRQ_RISING_ALT = 6,\n\tAXP288_IRQ_OV_ALT = 7,\n\tAXP288_IRQ_DONE = 10,\n\tAXP288_IRQ_CHARGING = 11,\n\tAXP288_IRQ_SAFE_QUIT = 12,\n\tAXP288_IRQ_SAFE_ENTER = 13,\n\tAXP288_IRQ_ABSENT = 14,\n\tAXP288_IRQ_APPEND = 15,\n\tAXP288_IRQ_QWBTU = 16,\n\tAXP288_IRQ_WBTU = 17,\n\tAXP288_IRQ_QWBTO = 18,\n\tAXP288_IRQ_WBTO = 19,\n\tAXP288_IRQ_QCBTU = 20,\n\tAXP288_IRQ_CBTU = 21,\n\tAXP288_IRQ_QCBTO = 22,\n\tAXP288_IRQ_CBTO = 23,\n\tAXP288_IRQ_WL2 = 24,\n\tAXP288_IRQ_WL1 = 25,\n\tAXP288_IRQ_GPADC = 26,\n\tAXP288_IRQ_OT = 31,\n\tAXP288_IRQ_GPIO0 = 32,\n\tAXP288_IRQ_GPIO1 = 33,\n\tAXP288_IRQ_POKO = 34,\n\tAXP288_IRQ_POKL = 35,\n\tAXP288_IRQ_POKS = 36,\n\tAXP288_IRQ_POKN = 37,\n\tAXP288_IRQ_POKP = 38,\n\tAXP288_IRQ_TIMER = 39,\n\tAXP288_IRQ_MV_CHNG = 40,\n\tAXP288_IRQ_BC_USB_CHNG = 41,\n};\n\nenum axp313a_irqs {\n\tAXP313A_IRQ_DIE_TEMP_HIGH = 0,\n\tAXP313A_IRQ_DCDC2_V_LOW = 2,\n\tAXP313A_IRQ_DCDC3_V_LOW = 3,\n\tAXP313A_IRQ_PEK_LONG = 4,\n\tAXP313A_IRQ_PEK_SHORT = 5,\n\tAXP313A_IRQ_PEK_FAL_EDGE = 6,\n\tAXP313A_IRQ_PEK_RIS_EDGE = 7,\n};\n\nenum axp717_irqs {\n\tAXP717_IRQ_VBUS_FAULT = 0,\n\tAXP717_IRQ_VBUS_OVER_V = 1,\n\tAXP717_IRQ_BOOST_OVER_V = 2,\n\tAXP717_IRQ_GAUGE_NEW_SOC = 4,\n\tAXP717_IRQ_SOC_DROP_LVL1 = 6,\n\tAXP717_IRQ_SOC_DROP_LVL2 = 7,\n\tAXP717_IRQ_PEK_RIS_EDGE = 8,\n\tAXP717_IRQ_PEK_FAL_EDGE = 9,\n\tAXP717_IRQ_PEK_LONG = 10,\n\tAXP717_IRQ_PEK_SHORT = 11,\n\tAXP717_IRQ_BATT_REMOVAL = 12,\n\tAXP717_IRQ_BATT_PLUGIN = 13,\n\tAXP717_IRQ_VBUS_REMOVAL = 14,\n\tAXP717_IRQ_VBUS_PLUGIN = 15,\n\tAXP717_IRQ_BATT_OVER_V = 16,\n\tAXP717_IRQ_CHARG_TIMER = 17,\n\tAXP717_IRQ_DIE_TEMP_HIGH = 18,\n\tAXP717_IRQ_CHARG = 19,\n\tAXP717_IRQ_CHARG_DONE = 20,\n\tAXP717_IRQ_BATT_OVER_CURR = 21,\n\tAXP717_IRQ_LDO_OVER_CURR = 22,\n\tAXP717_IRQ_WDOG_EXPIRE = 23,\n\tAXP717_IRQ_BATT_ACT_TEMP_LOW = 24,\n\tAXP717_IRQ_BATT_ACT_TEMP_HIGH = 25,\n\tAXP717_IRQ_BATT_CHG_TEMP_LOW = 26,\n\tAXP717_IRQ_BATT_CHG_TEMP_HIGH = 27,\n\tAXP717_IRQ_BATT_QUIT_TEMP_HIGH = 28,\n\tAXP717_IRQ_BC_USB_CHNG = 30,\n\tAXP717_IRQ_BC_USB_DONE = 31,\n\tAXP717_IRQ_TYPEC_PLUGIN = 37,\n\tAXP717_IRQ_TYPEC_REMOVE = 38,\n};\n\nenum axp803_irqs {\n\tAXP803_IRQ_ACIN_OVER_V = 1,\n\tAXP803_IRQ_ACIN_PLUGIN = 2,\n\tAXP803_IRQ_ACIN_REMOVAL = 3,\n\tAXP803_IRQ_VBUS_OVER_V = 4,\n\tAXP803_IRQ_VBUS_PLUGIN = 5,\n\tAXP803_IRQ_VBUS_REMOVAL = 6,\n\tAXP803_IRQ_BATT_PLUGIN = 7,\n\tAXP803_IRQ_BATT_REMOVAL = 8,\n\tAXP803_IRQ_BATT_ENT_ACT_MODE = 9,\n\tAXP803_IRQ_BATT_EXIT_ACT_MODE = 10,\n\tAXP803_IRQ_CHARG = 11,\n\tAXP803_IRQ_CHARG_DONE = 12,\n\tAXP803_IRQ_BATT_CHG_TEMP_HIGH = 13,\n\tAXP803_IRQ_BATT_CHG_TEMP_HIGH_END = 14,\n\tAXP803_IRQ_BATT_CHG_TEMP_LOW = 15,\n\tAXP803_IRQ_BATT_CHG_TEMP_LOW_END = 16,\n\tAXP803_IRQ_BATT_ACT_TEMP_HIGH = 17,\n\tAXP803_IRQ_BATT_ACT_TEMP_HIGH_END = 18,\n\tAXP803_IRQ_BATT_ACT_TEMP_LOW = 19,\n\tAXP803_IRQ_BATT_ACT_TEMP_LOW_END = 20,\n\tAXP803_IRQ_DIE_TEMP_HIGH = 21,\n\tAXP803_IRQ_GPADC = 22,\n\tAXP803_IRQ_LOW_PWR_LVL1 = 23,\n\tAXP803_IRQ_LOW_PWR_LVL2 = 24,\n\tAXP803_IRQ_TIMER = 25,\n\tAXP803_IRQ_PEK_FAL_EDGE = 26,\n\tAXP803_IRQ_PEK_RIS_EDGE = 27,\n\tAXP803_IRQ_PEK_SHORT = 28,\n\tAXP803_IRQ_PEK_LONG = 29,\n\tAXP803_IRQ_PEK_OVER_OFF = 30,\n\tAXP803_IRQ_GPIO1_INPUT = 31,\n\tAXP803_IRQ_GPIO0_INPUT = 32,\n\tAXP803_IRQ_BC_USB_CHNG = 33,\n\tAXP803_IRQ_MV_CHNG = 34,\n};\n\nenum axp806_irqs {\n\tAXP806_IRQ_DIE_TEMP_HIGH_LV1 = 0,\n\tAXP806_IRQ_DIE_TEMP_HIGH_LV2 = 1,\n\tAXP806_IRQ_DCDCA_V_LOW = 2,\n\tAXP806_IRQ_DCDCB_V_LOW = 3,\n\tAXP806_IRQ_DCDCC_V_LOW = 4,\n\tAXP806_IRQ_DCDCD_V_LOW = 5,\n\tAXP806_IRQ_DCDCE_V_LOW = 6,\n\tAXP806_IRQ_POK_LONG = 7,\n\tAXP806_IRQ_POK_SHORT = 8,\n\tAXP806_IRQ_WAKEUP = 9,\n\tAXP806_IRQ_POK_FALL = 10,\n\tAXP806_IRQ_POK_RISE = 11,\n};\n\nenum axp809_irqs {\n\tAXP809_IRQ_ACIN_OVER_V = 1,\n\tAXP809_IRQ_ACIN_PLUGIN = 2,\n\tAXP809_IRQ_ACIN_REMOVAL = 3,\n\tAXP809_IRQ_VBUS_OVER_V = 4,\n\tAXP809_IRQ_VBUS_PLUGIN = 5,\n\tAXP809_IRQ_VBUS_REMOVAL = 6,\n\tAXP809_IRQ_VBUS_V_LOW = 7,\n\tAXP809_IRQ_BATT_PLUGIN = 8,\n\tAXP809_IRQ_BATT_REMOVAL = 9,\n\tAXP809_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP809_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP809_IRQ_CHARG = 12,\n\tAXP809_IRQ_CHARG_DONE = 13,\n\tAXP809_IRQ_BATT_CHG_TEMP_HIGH = 14,\n\tAXP809_IRQ_BATT_CHG_TEMP_HIGH_END = 15,\n\tAXP809_IRQ_BATT_CHG_TEMP_LOW = 16,\n\tAXP809_IRQ_BATT_CHG_TEMP_LOW_END = 17,\n\tAXP809_IRQ_BATT_ACT_TEMP_HIGH = 18,\n\tAXP809_IRQ_BATT_ACT_TEMP_HIGH_END = 19,\n\tAXP809_IRQ_BATT_ACT_TEMP_LOW = 20,\n\tAXP809_IRQ_BATT_ACT_TEMP_LOW_END = 21,\n\tAXP809_IRQ_DIE_TEMP_HIGH = 22,\n\tAXP809_IRQ_LOW_PWR_LVL1 = 23,\n\tAXP809_IRQ_LOW_PWR_LVL2 = 24,\n\tAXP809_IRQ_TIMER = 25,\n\tAXP809_IRQ_PEK_FAL_EDGE = 26,\n\tAXP809_IRQ_PEK_RIS_EDGE = 27,\n\tAXP809_IRQ_PEK_SHORT = 28,\n\tAXP809_IRQ_PEK_LONG = 29,\n\tAXP809_IRQ_PEK_OVER_OFF = 30,\n\tAXP809_IRQ_GPIO1_INPUT = 31,\n\tAXP809_IRQ_GPIO0_INPUT = 32,\n};\n\nenum backlight_scale {\n\tBACKLIGHT_SCALE_UNKNOWN = 0,\n\tBACKLIGHT_SCALE_LINEAR = 1,\n\tBACKLIGHT_SCALE_NON_LINEAR = 2,\n};\n\nenum backlight_type {\n\tBACKLIGHT_RAW = 1,\n\tBACKLIGHT_PLATFORM = 2,\n\tBACKLIGHT_FIRMWARE = 3,\n\tBACKLIGHT_TYPE_MAX = 4,\n};\n\nenum backlight_update_reason {\n\tBACKLIGHT_UPDATE_HOTKEY = 0,\n\tBACKLIGHT_UPDATE_SYSFS = 1,\n};\n\nenum bam_reg {\n\tBAM_CTRL = 0,\n\tBAM_REVISION = 1,\n\tBAM_NUM_PIPES = 2,\n\tBAM_DESC_CNT_TRSHLD = 3,\n\tBAM_IRQ_SRCS = 4,\n\tBAM_IRQ_SRCS_MSK = 5,\n\tBAM_IRQ_SRCS_UNMASKED = 6,\n\tBAM_IRQ_STTS = 7,\n\tBAM_IRQ_CLR = 8,\n\tBAM_IRQ_EN = 9,\n\tBAM_CNFG_BITS = 10,\n\tBAM_IRQ_SRCS_EE = 11,\n\tBAM_IRQ_SRCS_MSK_EE = 12,\n\tBAM_P_CTRL = 13,\n\tBAM_P_RST = 14,\n\tBAM_P_HALT = 15,\n\tBAM_P_IRQ_STTS = 16,\n\tBAM_P_IRQ_CLR = 17,\n\tBAM_P_IRQ_EN = 18,\n\tBAM_P_EVNT_DEST_ADDR = 19,\n\tBAM_P_EVNT_REG = 20,\n\tBAM_P_SW_OFSTS = 21,\n\tBAM_P_DATA_FIFO_ADDR = 22,\n\tBAM_P_DESC_FIFO_ADDR = 23,\n\tBAM_P_EVNT_GEN_TRSHLD = 24,\n\tBAM_P_FIFO_SIZES = 25,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum base_type {\n\tREG = 0,\n\tIO_CTRL = 1,\n};\n\nenum base_type___2 {\n\tMSPI = 0,\n\tBSPI = 1,\n\tCHIP_SELECT = 2,\n\tBASEMAX = 3,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum bch_ecc {\n\tBCH4_ECC = 0,\n\tBCH8_ECC = 1,\n\tBCH16_ECC = 2,\n};\n\nenum bcm281xx_pin_type {\n\tBCM281XX_PIN_TYPE_UNKNOWN = 0,\n\tBCM281XX_PIN_TYPE_STD = 1,\n\tBCM281XX_PIN_TYPE_I2C = 2,\n\tBCM281XX_PIN_TYPE_HDMI = 3,\n};\n\nenum bcm281xx_pinctrl_type {\n\tBCM281XX_PINCTRL_TYPE = 0,\n\tBCM21664_PINCTRL_TYPE = 1,\n};\n\nenum bcm2835_fsel {\n\tBCM2835_FSEL_COUNT = 8,\n\tBCM2835_FSEL_MASK = 7,\n};\n\nenum bcm590xx_reg_type {\n\tBCM590XX_REG_TYPE_LDO = 0,\n\tBCM590XX_REG_TYPE_GPLDO = 1,\n\tBCM590XX_REG_TYPE_SR = 2,\n\tBCM590XX_REG_TYPE_VBUS = 3,\n};\n\nenum bcm590xx_regmap_type {\n\tBCM590XX_REGMAP_PRI = 0,\n\tBCM590XX_REGMAP_SEC = 1,\n};\n\nenum bcm_clk_type {\n\tbcm_clk_none = 0,\n\tbcm_clk_bus = 1,\n\tbcm_clk_core = 2,\n\tbcm_clk_peri = 3,\n};\n\nenum bcm_iproc_i2c_type {\n\tIPROC_I2C = 0,\n\tIPROC_I2C_NIC = 1,\n};\n\nenum bcm_kona_cmd_t {\n\tBCM_CMD_NOACTION = 0,\n\tBCM_CMD_START = 1,\n\tBCM_CMD_RESTART = 2,\n\tBCM_CMD_STOP = 3,\n};\n\nenum bcm_usb_phy_ctrl_bits {\n\tCORERDY = 0,\n\tPHY_RESETB = 1,\n\tPHY_PCTL = 2,\n};\n\nenum bcm_usb_phy_reg {\n\tPLL_CTRL = 0,\n\tPHY_CTRL = 1,\n\tPHY_PLL_CTRL = 2,\n};\n\nenum bcm_usb_phy_type {\n\tUSB_HS_PHY = 0,\n\tUSB_SS_PHY = 1,\n};\n\nenum bcm_usb_phy_version {\n\tBCM_SR_USB_COMBO_PHY = 0,\n\tBCM_SR_USB_HS_PHY = 1,\n};\n\nenum bcma_clkmode {\n\tBCMA_CLKMODE_FAST = 0,\n\tBCMA_CLKMODE_DYNAMIC = 1,\n};\n\nenum bcma_hosttype {\n\tBCMA_HOSTTYPE_PCI = 0,\n\tBCMA_HOSTTYPE_SDIO = 1,\n\tBCMA_HOSTTYPE_SOC = 2,\n};\n\nenum bcmasp_stat_type {\n\tBCMASP_STAT_RX_CTRL = 0,\n\tBCMASP_STAT_RX_CTRL_PER_INTF = 1,\n\tBCMASP_STAT_SOFT = 2,\n};\n\nenum bdc_ep0_state {\n\tWAIT_FOR_SETUP = 0,\n\tWAIT_FOR_DATA_START = 1,\n\tWAIT_FOR_DATA_XMIT = 2,\n\tWAIT_FOR_STATUS_START = 3,\n\tWAIT_FOR_STATUS_XMIT = 4,\n\tSTATUS_PENDING = 5,\n};\n\nenum bdc_link_state {\n\tBDC_LINK_STATE_U0 = 0,\n\tBDC_LINK_STATE_U3 = 3,\n\tBDC_LINK_STATE_RX_DET = 5,\n\tBDC_LINK_STATE_RESUME = 15,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bfqq_expiration {\n\tBFQQE_TOO_IDLE = 0,\n\tBFQQE_BUDGET_TIMEOUT = 1,\n\tBFQQE_BUDGET_EXHAUSTED = 2,\n\tBFQQE_NO_MORE_REQUESTS = 3,\n\tBFQQE_PREEMPTED = 4,\n};\n\nenum bfqq_state_flags {\n\tBFQQF_just_created = 0,\n\tBFQQF_busy = 1,\n\tBFQQF_wait_request = 2,\n\tBFQQF_non_blocking_wait_rq = 3,\n\tBFQQF_fifo_expire = 4,\n\tBFQQF_has_short_ttime = 5,\n\tBFQQF_sync = 6,\n\tBFQQF_IO_bound = 7,\n\tBFQQF_in_large_burst = 8,\n\tBFQQF_softrt_update = 9,\n\tBFQQF_coop = 10,\n\tBFQQF_split_coop = 11,\n};\n\nenum bgmac_dma_ring_type {\n\tBGMAC_DMA_RING_TX = 0,\n\tBGMAC_DMA_RING_RX = 1,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum blacklist_hash_type {\n\tBLACKLIST_HASH_X509_TBS = 1,\n\tBLACKLIST_HASH_BINARY = 2,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_43bit_dma = 1,\n\tboard_ahci_ign_iferr = 2,\n\tboard_ahci_no_debounce_delay = 3,\n\tboard_ahci_no_msi = 4,\n\tboard_ahci_pcs_quirk = 5,\n\tboard_ahci_pcs_quirk_no_devslp = 6,\n\tboard_ahci_pcs_quirk_no_sntf = 7,\n\tboard_ahci_yes_fbs = 8,\n\tboard_ahci_yes_fbs_atapi_dma = 9,\n\tboard_ahci_al = 10,\n\tboard_ahci_avn = 11,\n\tboard_ahci_mcp65 = 12,\n\tboard_ahci_mcp77 = 13,\n\tboard_ahci_mcp89 = 14,\n\tboard_ahci_mv = 15,\n\tboard_ahci_sb600 = 16,\n\tboard_ahci_sb700 = 17,\n\tboard_ahci_vt8251 = 18,\n\tboard_ahci_mcp_linux = 12,\n\tboard_ahci_mcp67 = 12,\n\tboard_ahci_mcp73 = 12,\n\tboard_ahci_mcp79 = 13,\n};\n\nenum boosting_vals {\n\tBOOST_1000_UA = 1000,\n\tBOOST_2000_UA = 2000,\n};\n\nenum bp_type_idx {\n\tTYPE_INST = 0,\n\tTYPE_DATA = 1,\n\tTYPE_MAX = 2,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_perf_event_type {\n\tBPF_PERF_EVENT_UNSPEC = 0,\n\tBPF_PERF_EVENT_UPROBE = 1,\n\tBPF_PERF_EVENT_URETPROBE = 2,\n\tBPF_PERF_EVENT_KPROBE = 3,\n\tBPF_PERF_EVENT_KRETPROBE = 4,\n\tBPF_PERF_EVENT_TRACEPOINT = 5,\n\tBPF_PERF_EVENT_EVENT = 6,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum brcm_ahci_quirks {\n\tBRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = 1,\n};\n\nenum brcm_ahci_version {\n\tBRCM_SATA_BCM7425 = 1,\n\tBRCM_SATA_BCM7445 = 2,\n\tBRCM_SATA_NSP = 3,\n\tBRCM_SATA_BCM7216 = 4,\n};\n\nenum brcm_sata_phy_rxaeq_mode {\n\tRXAEQ_MODE_OFF = 0,\n\tRXAEQ_MODE_AUTO = 1,\n\tRXAEQ_MODE_MANUAL = 2,\n};\n\nenum brcm_sata_phy_version {\n\tBRCM_SATA_PHY_STB_16NM = 0,\n\tBRCM_SATA_PHY_STB_28NM = 1,\n\tBRCM_SATA_PHY_STB_40NM = 2,\n\tBRCM_SATA_PHY_IPROC_NS2 = 3,\n\tBRCM_SATA_PHY_IPROC_NSP = 4,\n\tBRCM_SATA_PHY_IPROC_SR = 5,\n\tBRCM_SATA_PHY_DSL_28NM = 6,\n};\n\nenum brcmnand_cs_reg {\n\tBRCMNAND_CS_CFG_EXT = 0,\n\tBRCMNAND_CS_CFG = 1,\n\tBRCMNAND_CS_ACC_CONTROL = 2,\n\tBRCMNAND_CS_TIMING1 = 3,\n\tBRCMNAND_CS_TIMING2 = 4,\n};\n\nenum brcmnand_llop_type {\n\tLL_OP_CMD = 0,\n\tLL_OP_ADDR = 1,\n\tLL_OP_WR = 2,\n\tLL_OP_RD = 3,\n};\n\nenum brcmnand_reg {\n\tBRCMNAND_CMD_START = 0,\n\tBRCMNAND_CMD_EXT_ADDRESS = 1,\n\tBRCMNAND_CMD_ADDRESS = 2,\n\tBRCMNAND_INTFC_STATUS = 3,\n\tBRCMNAND_CS_SELECT = 4,\n\tBRCMNAND_CS_XOR = 5,\n\tBRCMNAND_LL_OP = 6,\n\tBRCMNAND_CS0_BASE = 7,\n\tBRCMNAND_CS1_BASE = 8,\n\tBRCMNAND_CORR_THRESHOLD = 9,\n\tBRCMNAND_CORR_THRESHOLD_EXT = 10,\n\tBRCMNAND_UNCORR_COUNT = 11,\n\tBRCMNAND_CORR_COUNT = 12,\n\tBRCMNAND_READ_ERROR_COUNT = 13,\n\tBRCMNAND_CORR_EXT_ADDR = 14,\n\tBRCMNAND_CORR_ADDR = 15,\n\tBRCMNAND_UNCORR_EXT_ADDR = 16,\n\tBRCMNAND_UNCORR_ADDR = 17,\n\tBRCMNAND_SEMAPHORE = 18,\n\tBRCMNAND_ID = 19,\n\tBRCMNAND_ID_EXT = 20,\n\tBRCMNAND_LL_RDATA = 21,\n\tBRCMNAND_OOB_READ_BASE = 22,\n\tBRCMNAND_OOB_READ_10_BASE = 23,\n\tBRCMNAND_OOB_WRITE_BASE = 24,\n\tBRCMNAND_OOB_WRITE_10_BASE = 25,\n\tBRCMNAND_FC_BASE = 26,\n};\n\nenum brcmstb_memc_hwtype {\n\tBRCMSTB_MEMC_V21 = 0,\n\tBRCMSTB_MEMC_V20 = 1,\n\tBRCMSTB_MEMC_V1X = 2,\n};\n\nenum bsc_xfer_cmd {\n\tCMD_WR = 0,\n\tCMD_RD = 1,\n\tCMD_WR_NOACK = 2,\n\tCMD_RD_NOACK = 3,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum bus_speed_index {\n\tBCM_SPD_100K = 0,\n\tBCM_SPD_400K = 1,\n\tBCM_SPD_1MHZ = 2,\n};\n\nenum bus_speeds {\n\tSPD_375K = 0,\n\tSPD_390K = 1,\n\tSPD_187K = 2,\n\tSPD_200K = 3,\n\tSPD_93K = 4,\n\tSPD_97K = 5,\n\tSPD_46K = 6,\n\tSPD_50K = 7,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum can_mode {\n\tCAN_MODE_STOP = 0,\n\tCAN_MODE_START = 1,\n\tCAN_MODE_SLEEP = 2,\n};\n\nenum can_state {\n\tCAN_STATE_ERROR_ACTIVE = 0,\n\tCAN_STATE_ERROR_WARNING = 1,\n\tCAN_STATE_ERROR_PASSIVE = 2,\n\tCAN_STATE_BUS_OFF = 3,\n\tCAN_STATE_STOPPED = 4,\n\tCAN_STATE_SLEEPING = 5,\n\tCAN_STATE_MAX = 6,\n};\n\nenum can_termination_gpio {\n\tCAN_TERMINATION_GPIO_DISABLED = 0,\n\tCAN_TERMINATION_GPIO_ENABLED = 1,\n\tCAN_TERMINATION_GPIO_MAX = 2,\n};\n\nenum cc_attr {\n\tCC_ATTR_MEM_ENCRYPT = 0,\n\tCC_ATTR_HOST_MEM_ENCRYPT = 1,\n\tCC_ATTR_GUEST_MEM_ENCRYPT = 2,\n\tCC_ATTR_GUEST_STATE_ENCRYPT = 3,\n\tCC_ATTR_GUEST_UNROLL_STRING_IO = 4,\n\tCC_ATTR_GUEST_SEV_SNP = 5,\n\tCC_ATTR_GUEST_SNP_SECURE_TSC = 6,\n\tCC_ATTR_HOST_SEV_SNP = 7,\n\tCC_ATTR_SNP_SECURE_AVIC = 8,\n};\n\nenum cci_ace_port_type {\n\tACE_INVALID_PORT = 0,\n\tACE_PORT = 1,\n\tACE_LITE_PORT = 2,\n};\n\nenum cd_types {\n\tS3C_SDHCI_CD_INTERNAL = 0,\n\tS3C_SDHCI_CD_EXTERNAL = 1,\n\tS3C_SDHCI_CD_GPIO = 2,\n\tS3C_SDHCI_CD_NONE = 3,\n\tS3C_SDHCI_CD_PERMANENT = 4,\n};\n\nenum cd_types___2 {\n\tESDHC_CD_NONE = 0,\n\tESDHC_CD_CONTROLLER = 1,\n\tESDHC_CD_GPIO = 2,\n\tESDHC_CD_PERMANENT = 3,\n};\n\nenum cdma_event {\n\tCDMA_EVENT_NONE = 0,\n\tCDMA_EVENT_SYNC_QUEUE_EMPTY = 1,\n\tCDMA_EVENT_PUSH_BUFFER_SPACE = 2,\n};\n\nenum cdns_i2c_mode {\n\tCDNS_I2C_MODE_SLAVE = 0,\n\tCDNS_I2C_MODE_MASTER = 1,\n};\n\nenum cdns_i2c_slave_state {\n\tCDNS_I2C_SLAVE_STATE_IDLE = 0,\n\tCDNS_I2C_SLAVE_STATE_SEND = 1,\n\tCDNS_I2C_SLAVE_STATE_RECV = 2,\n};\n\nenum cdns_spi_frame_n_bytes {\n\tCDNS_SPI_N_BYTES_NULL = 0,\n\tCDNS_SPI_N_BYTES_U8 = 1,\n\tCDNS_SPI_N_BYTES_U16 = 2,\n\tCDNS_SPI_N_BYTES_U32 = 4,\n};\n\nenum cdrom_print_option {\n\tCTL_NAME = 0,\n\tCTL_SPEED = 1,\n\tCTL_SLOTS = 2,\n\tCTL_CAPABILITY = 3,\n};\n\nenum cfg_core_ver {\n\tSDIO_CFG_CORE_V1 = 1,\n\tSDIO_CFG_CORE_V2 = 2,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_COUNT = 0,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tCGROUP_SUBSYS_COUNT = 2,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum chip_type {\n\tchip_504x = 0,\n\tchip_508x = 1,\n\tchip_5080 = 2,\n\tchip_604x = 3,\n\tchip_608x = 4,\n\tchip_6042 = 5,\n\tchip_7042 = 6,\n\tchip_soc = 7,\n};\n\nenum chips {\n\tTPS62360 = 0,\n\tTPS62361 = 1,\n\tTPS62362 = 2,\n\tTPS62363 = 3,\n};\n\nenum chips___2 {\n\tadm1023 = 0,\n\tadm1032 = 1,\n\tadt7461 = 2,\n\tadt7461a = 3,\n\tadt7481 = 4,\n\tg781 = 5,\n\tlm84 = 6,\n\tlm90 = 7,\n\tlm99 = 8,\n\tmax1617 = 9,\n\tmax6642 = 10,\n\tmax6646 = 11,\n\tmax6648 = 12,\n\tmax6654 = 13,\n\tmax6657 = 14,\n\tmax6659 = 15,\n\tmax6680 = 16,\n\tmax6696 = 17,\n\tnct210 = 18,\n\tnct72 = 19,\n\tnct7716 = 20,\n\tnct7717 = 21,\n\tnct7718 = 22,\n\tne1618 = 23,\n\tsa56004 = 24,\n\ttmp451 = 25,\n\ttmp461 = 26,\n\tw83l771 = 27,\n};\n\nenum ci_hw_regs {\n\tCAP_CAPLENGTH = 0,\n\tCAP_HCCPARAMS = 1,\n\tCAP_DCCPARAMS = 2,\n\tCAP_TESTMODE = 3,\n\tCAP_LAST = 3,\n\tOP_USBCMD = 4,\n\tOP_USBSTS = 5,\n\tOP_USBINTR = 6,\n\tOP_FRINDEX = 7,\n\tOP_DEVICEADDR = 8,\n\tOP_ENDPTLISTADDR = 9,\n\tOP_TTCTRL = 10,\n\tOP_BURSTSIZE = 11,\n\tOP_ULPI_VIEWPORT = 12,\n\tOP_PORTSC = 13,\n\tOP_DEVLC = 14,\n\tOP_OTGSC = 15,\n\tOP_USBMODE = 16,\n\tOP_ENDPTSETUPSTAT = 17,\n\tOP_ENDPTPRIME = 18,\n\tOP_ENDPTFLUSH = 19,\n\tOP_ENDPTSTAT = 20,\n\tOP_ENDPTCOMPLETE = 21,\n\tOP_ENDPTCTRL = 22,\n\tOP_LAST = 38,\n};\n\nenum ci_revision {\n\tCI_REVISION_1X = 10,\n\tCI_REVISION_20 = 20,\n\tCI_REVISION_21 = 21,\n\tCI_REVISION_22 = 22,\n\tCI_REVISION_23 = 23,\n\tCI_REVISION_24 = 24,\n\tCI_REVISION_25 = 25,\n\tCI_REVISION_25_PLUS = 26,\n\tCI_REVISION_UNKNOWN = 99,\n};\n\nenum ci_role {\n\tCI_ROLE_HOST = 0,\n\tCI_ROLE_GADGET = 1,\n\tCI_ROLE_END = 2,\n};\n\nenum class_map_type {\n\tDD_CLASS_TYPE_DISJOINT_BITS = 0,\n\tDD_CLASS_TYPE_LEVEL_NUM = 1,\n\tDD_CLASS_TYPE_DISJOINT_NAMES = 2,\n\tDD_CLASS_TYPE_LEVEL_NAMES = 3,\n};\n\nenum cleanup_prefix_rt_t {\n\tCLEANUP_PREFIX_RT_NOP = 0,\n\tCLEANUP_PREFIX_RT_DEL = 1,\n\tCLEANUP_PREFIX_RT_EXPIRE = 2,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clk_id {\n\ttegra_clk_actmon = 0,\n\ttegra_clk_adx = 1,\n\ttegra_clk_adx1 = 2,\n\ttegra_clk_afi = 3,\n\ttegra_clk_amx = 4,\n\ttegra_clk_amx1 = 5,\n\ttegra_clk_apb2ape = 6,\n\ttegra_clk_ahbdma = 7,\n\ttegra_clk_apbdma = 8,\n\ttegra_clk_apbif = 9,\n\ttegra_clk_ape = 10,\n\ttegra_clk_audio0 = 11,\n\ttegra_clk_audio0_2x = 12,\n\ttegra_clk_audio0_mux = 13,\n\ttegra_clk_audio1 = 14,\n\ttegra_clk_audio1_2x = 15,\n\ttegra_clk_audio1_mux = 16,\n\ttegra_clk_audio2 = 17,\n\ttegra_clk_audio2_2x = 18,\n\ttegra_clk_audio2_mux = 19,\n\ttegra_clk_audio3 = 20,\n\ttegra_clk_audio3_2x = 21,\n\ttegra_clk_audio3_mux = 22,\n\ttegra_clk_audio4 = 23,\n\ttegra_clk_audio4_2x = 24,\n\ttegra_clk_audio4_mux = 25,\n\ttegra_clk_bsea = 26,\n\ttegra_clk_bsev = 27,\n\ttegra_clk_cclk_g = 28,\n\ttegra_clk_cclk_lp = 29,\n\ttegra_clk_cilab = 30,\n\ttegra_clk_cilcd = 31,\n\ttegra_clk_cile = 32,\n\ttegra_clk_clk_32k = 33,\n\ttegra_clk_clk72Mhz = 34,\n\ttegra_clk_clk72Mhz_8 = 35,\n\ttegra_clk_clk_m = 36,\n\ttegra_clk_osc = 37,\n\ttegra_clk_osc_div2 = 38,\n\ttegra_clk_osc_div4 = 39,\n\ttegra_clk_cml0 = 40,\n\ttegra_clk_cml1 = 41,\n\ttegra_clk_csi = 42,\n\ttegra_clk_csite = 43,\n\ttegra_clk_csite_8 = 44,\n\ttegra_clk_csus = 45,\n\ttegra_clk_cve = 46,\n\ttegra_clk_dam0 = 47,\n\ttegra_clk_dam1 = 48,\n\ttegra_clk_dam2 = 49,\n\ttegra_clk_d_audio = 50,\n\ttegra_clk_dbgapb = 51,\n\ttegra_clk_dds = 52,\n\ttegra_clk_dfll_ref = 53,\n\ttegra_clk_dfll_soc = 54,\n\ttegra_clk_disp1 = 55,\n\ttegra_clk_disp1_8 = 56,\n\ttegra_clk_disp2 = 57,\n\ttegra_clk_disp2_8 = 58,\n\ttegra_clk_dp2 = 59,\n\ttegra_clk_dpaux = 60,\n\ttegra_clk_dpaux1 = 61,\n\ttegra_clk_dsialp = 62,\n\ttegra_clk_dsia_mux = 63,\n\ttegra_clk_dsiblp = 64,\n\ttegra_clk_dsib_mux = 65,\n\ttegra_clk_dtv = 66,\n\ttegra_clk_emc = 67,\n\ttegra_clk_entropy = 68,\n\ttegra_clk_entropy_8 = 69,\n\ttegra_clk_epp = 70,\n\ttegra_clk_epp_8 = 71,\n\ttegra_clk_extern1 = 72,\n\ttegra_clk_extern2 = 73,\n\ttegra_clk_extern3 = 74,\n\ttegra_clk_fuse = 75,\n\ttegra_clk_fuse_burn = 76,\n\ttegra_clk_gpu = 77,\n\ttegra_clk_gr2d = 78,\n\ttegra_clk_gr2d_8 = 79,\n\ttegra_clk_gr3d = 80,\n\ttegra_clk_gr3d_8 = 81,\n\ttegra_clk_hclk = 82,\n\ttegra_clk_hda = 83,\n\ttegra_clk_hda_8 = 84,\n\ttegra_clk_hda2codec_2x = 85,\n\ttegra_clk_hda2codec_2x_8 = 86,\n\ttegra_clk_hda2hdmi = 87,\n\ttegra_clk_hdmi = 88,\n\ttegra_clk_hdmi_audio = 89,\n\ttegra_clk_host1x = 90,\n\ttegra_clk_host1x_8 = 91,\n\ttegra_clk_host1x_9 = 92,\n\ttegra_clk_hsic_trk = 93,\n\ttegra_clk_i2c1 = 94,\n\ttegra_clk_i2c2 = 95,\n\ttegra_clk_i2c3 = 96,\n\ttegra_clk_i2c4 = 97,\n\ttegra_clk_i2c5 = 98,\n\ttegra_clk_i2c6 = 99,\n\ttegra_clk_i2cslow = 100,\n\ttegra_clk_i2s0 = 101,\n\ttegra_clk_i2s0_sync = 102,\n\ttegra_clk_i2s1 = 103,\n\ttegra_clk_i2s1_sync = 104,\n\ttegra_clk_i2s2 = 105,\n\ttegra_clk_i2s2_sync = 106,\n\ttegra_clk_i2s3 = 107,\n\ttegra_clk_i2s3_sync = 108,\n\ttegra_clk_i2s4 = 109,\n\ttegra_clk_i2s4_sync = 110,\n\ttegra_clk_isp = 111,\n\ttegra_clk_isp_8 = 112,\n\ttegra_clk_isp_9 = 113,\n\ttegra_clk_ispb = 114,\n\ttegra_clk_kbc = 115,\n\ttegra_clk_kfuse = 116,\n\ttegra_clk_la = 117,\n\ttegra_clk_maud = 118,\n\ttegra_clk_mipi = 119,\n\ttegra_clk_mipibif = 120,\n\ttegra_clk_mipi_cal = 121,\n\ttegra_clk_mpe = 122,\n\ttegra_clk_mselect = 123,\n\ttegra_clk_msenc = 124,\n\ttegra_clk_ndflash = 125,\n\ttegra_clk_ndflash_8 = 126,\n\ttegra_clk_ndspeed = 127,\n\ttegra_clk_ndspeed_8 = 128,\n\ttegra_clk_nor = 129,\n\ttegra_clk_nvdec = 130,\n\ttegra_clk_nvenc = 131,\n\ttegra_clk_nvjpg = 132,\n\ttegra_clk_owr = 133,\n\ttegra_clk_owr_8 = 134,\n\ttegra_clk_pcie = 135,\n\ttegra_clk_pclk = 136,\n\ttegra_clk_pll_a = 137,\n\ttegra_clk_pll_a_out0 = 138,\n\ttegra_clk_pll_a1 = 139,\n\ttegra_clk_pll_c = 140,\n\ttegra_clk_pll_c2 = 141,\n\ttegra_clk_pll_c3 = 142,\n\ttegra_clk_pll_c4 = 143,\n\ttegra_clk_pll_c4_out0 = 144,\n\ttegra_clk_pll_c4_out1 = 145,\n\ttegra_clk_pll_c4_out2 = 146,\n\ttegra_clk_pll_c4_out3 = 147,\n\ttegra_clk_pll_c_out1 = 148,\n\ttegra_clk_pll_d = 149,\n\ttegra_clk_pll_d2 = 150,\n\ttegra_clk_pll_d2_out0 = 151,\n\ttegra_clk_pll_d_out0 = 152,\n\ttegra_clk_pll_dp = 153,\n\ttegra_clk_pll_e_out0 = 154,\n\ttegra_clk_pll_g_ref = 155,\n\ttegra_clk_pll_m = 156,\n\ttegra_clk_pll_m_out1 = 157,\n\ttegra_clk_pll_mb = 158,\n\ttegra_clk_pll_p = 159,\n\ttegra_clk_pll_p_out1 = 160,\n\ttegra_clk_pll_p_out2 = 161,\n\ttegra_clk_pll_p_out2_int = 162,\n\ttegra_clk_pll_p_out3 = 163,\n\ttegra_clk_pll_p_out4 = 164,\n\ttegra_clk_pll_p_out4_cpu = 165,\n\ttegra_clk_pll_p_out5 = 166,\n\ttegra_clk_pll_p_out_hsio = 167,\n\ttegra_clk_pll_p_out_xusb = 168,\n\ttegra_clk_pll_p_out_cpu = 169,\n\ttegra_clk_pll_p_out_adsp = 170,\n\ttegra_clk_pll_ref = 171,\n\ttegra_clk_pll_re_out = 172,\n\ttegra_clk_pll_re_vco = 173,\n\ttegra_clk_pll_u = 174,\n\ttegra_clk_pll_u_out = 175,\n\ttegra_clk_pll_u_out1 = 176,\n\ttegra_clk_pll_u_out2 = 177,\n\ttegra_clk_pll_u_12m = 178,\n\ttegra_clk_pll_u_480m = 179,\n\ttegra_clk_pll_u_48m = 180,\n\ttegra_clk_pll_u_60m = 181,\n\ttegra_clk_pll_x = 182,\n\ttegra_clk_pll_x_out0 = 183,\n\ttegra_clk_pwm = 184,\n\ttegra_clk_qspi = 185,\n\ttegra_clk_rtc = 186,\n\ttegra_clk_sata = 187,\n\ttegra_clk_sata_8 = 188,\n\ttegra_clk_sata_cold = 189,\n\ttegra_clk_sata_oob = 190,\n\ttegra_clk_sata_oob_8 = 191,\n\ttegra_clk_sbc1 = 192,\n\ttegra_clk_sbc1_8 = 193,\n\ttegra_clk_sbc1_9 = 194,\n\ttegra_clk_sbc2 = 195,\n\ttegra_clk_sbc2_8 = 196,\n\ttegra_clk_sbc2_9 = 197,\n\ttegra_clk_sbc3 = 198,\n\ttegra_clk_sbc3_8 = 199,\n\ttegra_clk_sbc3_9 = 200,\n\ttegra_clk_sbc4 = 201,\n\ttegra_clk_sbc4_8 = 202,\n\ttegra_clk_sbc4_9 = 203,\n\ttegra_clk_sbc5 = 204,\n\ttegra_clk_sbc5_8 = 205,\n\ttegra_clk_sbc6 = 206,\n\ttegra_clk_sbc6_8 = 207,\n\ttegra_clk_sclk = 208,\n\ttegra_clk_sdmmc_legacy = 209,\n\ttegra_clk_sdmmc1 = 210,\n\ttegra_clk_sdmmc1_8 = 211,\n\ttegra_clk_sdmmc1_9 = 212,\n\ttegra_clk_sdmmc2 = 213,\n\ttegra_clk_sdmmc2_8 = 214,\n\ttegra_clk_sdmmc3 = 215,\n\ttegra_clk_sdmmc3_8 = 216,\n\ttegra_clk_sdmmc3_9 = 217,\n\ttegra_clk_sdmmc4 = 218,\n\ttegra_clk_sdmmc4_8 = 219,\n\ttegra_clk_se = 220,\n\ttegra_clk_se_10 = 221,\n\ttegra_clk_soc_therm = 222,\n\ttegra_clk_soc_therm_8 = 223,\n\ttegra_clk_sor0 = 224,\n\ttegra_clk_sor0_out = 225,\n\ttegra_clk_sor1 = 226,\n\ttegra_clk_sor1_out = 227,\n\ttegra_clk_spdif = 228,\n\ttegra_clk_spdif_2x = 229,\n\ttegra_clk_spdif_in = 230,\n\ttegra_clk_spdif_in_8 = 231,\n\ttegra_clk_spdif_in_sync = 232,\n\ttegra_clk_spdif_mux = 233,\n\ttegra_clk_spdif_out = 234,\n\ttegra_clk_timer = 235,\n\ttegra_clk_trace = 236,\n\ttegra_clk_tsec = 237,\n\ttegra_clk_tsec_8 = 238,\n\ttegra_clk_tsecb = 239,\n\ttegra_clk_tsensor = 240,\n\ttegra_clk_tvdac = 241,\n\ttegra_clk_tvo = 242,\n\ttegra_clk_uarta = 243,\n\ttegra_clk_uarta_8 = 244,\n\ttegra_clk_uartb = 245,\n\ttegra_clk_uartb_8 = 246,\n\ttegra_clk_uartc = 247,\n\ttegra_clk_uartc_8 = 248,\n\ttegra_clk_uartd = 249,\n\ttegra_clk_uartd_8 = 250,\n\ttegra_clk_uarte = 251,\n\ttegra_clk_uarte_8 = 252,\n\ttegra_clk_uartape = 253,\n\ttegra_clk_usb2 = 254,\n\ttegra_clk_usb2_hsic_trk = 255,\n\ttegra_clk_usb2_trk = 256,\n\ttegra_clk_usb3 = 257,\n\ttegra_clk_usbd = 258,\n\ttegra_clk_vcp = 259,\n\ttegra_clk_vde = 260,\n\ttegra_clk_vde_8 = 261,\n\ttegra_clk_vfir = 262,\n\ttegra_clk_vi = 263,\n\ttegra_clk_vi_8 = 264,\n\ttegra_clk_vi_9 = 265,\n\ttegra_clk_vi_10 = 266,\n\ttegra_clk_vi_i2c = 267,\n\ttegra_clk_vic03 = 268,\n\ttegra_clk_vic03_8 = 269,\n\ttegra_clk_vim2_clk = 270,\n\ttegra_clk_vimclk_sync = 271,\n\ttegra_clk_vi_sensor = 272,\n\ttegra_clk_vi_sensor_8 = 273,\n\ttegra_clk_vi_sensor_9 = 274,\n\ttegra_clk_vi_sensor2 = 275,\n\ttegra_clk_vi_sensor2_8 = 276,\n\ttegra_clk_xusb_dev = 277,\n\ttegra_clk_xusb_dev_src = 278,\n\ttegra_clk_xusb_dev_src_8 = 279,\n\ttegra_clk_xusb_falcon_src = 280,\n\ttegra_clk_xusb_falcon_src_8 = 281,\n\ttegra_clk_xusb_fs_src = 282,\n\ttegra_clk_xusb_gate = 283,\n\ttegra_clk_xusb_host = 284,\n\ttegra_clk_xusb_host_src = 285,\n\ttegra_clk_xusb_host_src_8 = 286,\n\ttegra_clk_xusb_hs_src = 287,\n\ttegra_clk_xusb_hs_src_4 = 288,\n\ttegra_clk_xusb_ss = 289,\n\ttegra_clk_xusb_ss_src = 290,\n\ttegra_clk_xusb_ss_src_8 = 291,\n\ttegra_clk_xusb_ss_div2 = 292,\n\ttegra_clk_xusb_ssp_src = 293,\n\ttegra_clk_sclk_mux = 294,\n\ttegra_clk_sor_safe = 295,\n\ttegra_clk_cec = 296,\n\ttegra_clk_ispa = 297,\n\ttegra_clk_dmic1 = 298,\n\ttegra_clk_dmic2 = 299,\n\ttegra_clk_dmic3 = 300,\n\ttegra_clk_dmic1_sync_clk = 301,\n\ttegra_clk_dmic2_sync_clk = 302,\n\ttegra_clk_dmic3_sync_clk = 303,\n\ttegra_clk_dmic1_sync_clk_mux = 304,\n\ttegra_clk_dmic2_sync_clk_mux = 305,\n\ttegra_clk_dmic3_sync_clk_mux = 306,\n\ttegra_clk_iqc1 = 307,\n\ttegra_clk_iqc2 = 308,\n\ttegra_clk_pll_a_out_adsp = 309,\n\ttegra_clk_pll_a_out0_out_adsp = 310,\n\ttegra_clk_adsp = 311,\n\ttegra_clk_adsp_neon = 312,\n\ttegra_clk_max = 313,\n};\n\nenum clk_id___2 {\n\tCLK_NONE = 0,\n\tCLK_MM = 1,\n\tCLK_MFG = 2,\n\tCLK_VENC = 3,\n\tCLK_VENC_LT = 4,\n\tCLK_ETHIF = 5,\n\tCLK_VDEC = 6,\n\tCLK_HIFSEL = 7,\n\tCLK_JPGDEC = 8,\n\tCLK_AUDIO = 9,\n\tCLK_MAX = 10,\n};\n\nenum clk_ids {\n\tLAST_DT_CORE_CLK = 25,\n\tCLK_EXTAL = 26,\n\tCLK_MAIN = 27,\n\tCLK_PLL0 = 28,\n\tCLK_PLL1 = 29,\n\tCLK_PLL3 = 30,\n\tCLK_PLL1_DIV2 = 31,\n\tMOD_CLK_BASE = 32,\n};\n\nenum clk_ids___2 {\n\tLAST_DT_CORE_CLK___2 = 29,\n\tCLK_EXTAL___2 = 30,\n\tCLK_USB_EXTAL = 31,\n\tCLK_MAIN___2 = 32,\n\tCLK_PLL0___2 = 33,\n\tCLK_PLL1___2 = 34,\n\tCLK_PLL3___2 = 35,\n\tCLK_PLL1_DIV2___2 = 36,\n\tMOD_CLK_BASE___2 = 37,\n};\n\nenum clk_ids___3 {\n\tLAST_DT_CORE_CLK___3 = 30,\n\tCLK_EXTAL___3 = 31,\n\tCLK_USB_EXTAL___2 = 32,\n\tCLK_MAIN___3 = 33,\n\tCLK_PLL0___3 = 34,\n\tCLK_PLL1___3 = 35,\n\tCLK_PLL3___3 = 36,\n\tCLK_PLL1_DIV2___3 = 37,\n\tMOD_CLK_BASE___3 = 38,\n};\n\nenum clk_ids___4 {\n\tLAST_DT_CORE_CLK___4 = 23,\n\tCLK_EXTAL___4 = 24,\n\tCLK_USB_EXTAL___3 = 25,\n\tCLK_MAIN___4 = 26,\n\tCLK_PLL0___4 = 27,\n\tCLK_PLL1___4 = 28,\n\tCLK_PLL3___4 = 29,\n\tCLK_PLL1_DIV2___4 = 30,\n\tMOD_CLK_BASE___4 = 31,\n};\n\nenum clk_ids___5 {\n\tLAST_DT_CORE_CLK___5 = 34,\n\tCLK_EXTAL___5 = 35,\n\tCLK_USB_EXTAL___4 = 36,\n\tCLK_MAIN___5 = 37,\n\tCLK_PLL0___5 = 38,\n\tCLK_PLL1___5 = 39,\n\tCLK_PLL3___5 = 40,\n\tCLK_PLL1_DIV2___5 = 41,\n\tMOD_CLK_BASE___5 = 42,\n};\n\nenum clk_ids___6 {\n\tLAST_DT_CORE_CLK___6 = 5,\n\tCLK_EXTAL___6 = 6,\n\tCLK_MAIN___6 = 7,\n\tCLK_PLL = 8,\n\tMOD_CLK_BASE___6 = 9,\n};\n\nenum clk_reg_layout {\n\tCLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,\n\tCLK_REG_LAYOUT_RZ_A = 1,\n\tCLK_REG_LAYOUT_RCAR_GEN4 = 2,\n\tCLK_REG_LAYOUT_RZ_T2H = 3,\n};\n\nenum clk_state {\n\tCLK_STATE_DISABLE = 0,\n\tCLK_STATE_ENABLE = 1,\n\tCLK_STATE_RESERVED = 2,\n\tCLK_STATE_UNCHANGED = 3,\n};\n\nenum clk_types {\n\tCLK_TYPE_IN = 0,\n\tCLK_TYPE_FF = 1,\n\tCLK_TYPE_DIV6P1 = 2,\n\tCLK_TYPE_DIV6_RO = 3,\n\tCLK_TYPE_FR = 4,\n\tCLK_TYPE_CUSTOM = 5,\n};\n\nenum clkrst_index {\n\tCLKRST1_INDEX = 0,\n\tCLKRST2_INDEX = 1,\n\tCLKRST3_INDEX = 2,\n\tCLKRST5_INDEX = 3,\n\tCLKRST6_INDEX = 4,\n\tCLKRST_MAX = 5,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum cma_flags {\n\tCMA_RESERVE_PAGES_ON_ERROR = 0,\n\tCMA_ZONES_VALID = 1,\n\tCMA_ZONES_INVALID = 2,\n\tCMA_ACTIVATED = 3,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cpcap_regulator_id {\n\tCPCAP_SW1 = 0,\n\tCPCAP_SW2 = 1,\n\tCPCAP_SW3 = 2,\n\tCPCAP_SW4 = 3,\n\tCPCAP_SW5 = 4,\n\tCPCAP_SW6 = 5,\n\tCPCAP_VCAM = 6,\n\tCPCAP_VCSI = 7,\n\tCPCAP_VDAC = 8,\n\tCPCAP_VDIG = 9,\n\tCPCAP_VFUSE = 10,\n\tCPCAP_VHVIO = 11,\n\tCPCAP_VSDIO = 12,\n\tCPCAP_VPLL = 13,\n\tCPCAP_VRF1 = 14,\n\tCPCAP_VRF2 = 15,\n\tCPCAP_VRFREF = 16,\n\tCPCAP_VWLAN1 = 17,\n\tCPCAP_VWLAN2 = 18,\n\tCPCAP_VSIM = 19,\n\tCPCAP_VSIMCARD = 20,\n\tCPCAP_VVIB = 21,\n\tCPCAP_VUSB = 22,\n\tCPCAP_VAUDIO = 23,\n\tCPCAP_NR_REGULATORS = 24,\n};\n\nenum cpdma_control {\n\tCPDMA_TX_RLIM = 0,\n\tCPDMA_CMD_IDLE = 1,\n\tCPDMA_COPY_ERROR_FRAMES = 2,\n\tCPDMA_RX_OFF_LEN_UPDATE = 3,\n\tCPDMA_RX_OWNERSHIP_FLIP = 4,\n\tCPDMA_TX_PRIO_FIXED = 5,\n\tCPDMA_STAT_IDLE = 6,\n\tCPDMA_STAT_TX_ERR_CHAN = 7,\n\tCPDMA_STAT_TX_ERR_CODE = 8,\n\tCPDMA_STAT_RX_ERR_CHAN = 9,\n\tCPDMA_STAT_RX_ERR_CODE = 10,\n\tCPDMA_RX_BUFFER_OFFSET = 11,\n};\n\nenum cpdma_state {\n\tCPDMA_STATE_IDLE = 0,\n\tCPDMA_STATE_ACTIVE = 1,\n\tCPDMA_STATE_TEARDOWN = 2,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cpsw_ale_control {\n\tALE_ENABLE = 0,\n\tALE_CLEAR = 1,\n\tALE_AGEOUT = 2,\n\tALE_P0_UNI_FLOOD = 3,\n\tALE_VLAN_NOLEARN = 4,\n\tALE_NO_PORT_VLAN = 5,\n\tALE_OUI_DENY = 6,\n\tALE_BYPASS = 7,\n\tALE_RATE_LIMIT_TX = 8,\n\tALE_VLAN_AWARE = 9,\n\tALE_AUTH_ENABLE = 10,\n\tALE_RATE_LIMIT = 11,\n\tALE_PORT_STATE = 12,\n\tALE_PORT_DROP_UNTAGGED = 13,\n\tALE_PORT_DROP_UNKNOWN_VLAN = 14,\n\tALE_PORT_NOLEARN = 15,\n\tALE_PORT_NO_SA_UPDATE = 16,\n\tALE_PORT_UNKNOWN_VLAN_MEMBER = 17,\n\tALE_PORT_UNKNOWN_MCAST_FLOOD = 18,\n\tALE_PORT_UNKNOWN_REG_MCAST_FLOOD = 19,\n\tALE_PORT_UNTAGGED_EGRESS = 20,\n\tALE_PORT_MACONLY = 21,\n\tALE_PORT_MACONLY_CAF = 22,\n\tALE_PORT_BCAST_LIMIT = 23,\n\tALE_PORT_MCAST_LIMIT = 24,\n\tALE_DEFAULT_THREAD_ID = 25,\n\tALE_DEFAULT_THREAD_ENABLE = 26,\n\tALE_NUM_CONTROLS = 27,\n};\n\nenum cpsw_ale_port_state {\n\tALE_PORT_STATE_DISABLE = 0,\n\tALE_PORT_STATE_BLOCK = 1,\n\tALE_PORT_STATE_LEARN = 2,\n\tALE_PORT_STATE_FORWARD = 3,\n};\n\nenum cpsw_devlink_param_id {\n\tCPSW_DEVLINK_PARAM_ID_BASE = 21,\n\tCPSW_DL_PARAM_SWITCH_MODE = 22,\n\tCPSW_DL_PARAM_ALE_BYPASS = 23,\n};\n\nenum cpsw_sl_regs {\n\tCPSW_SL_IDVER = 0,\n\tCPSW_SL_MACCONTROL = 1,\n\tCPSW_SL_MACSTATUS = 2,\n\tCPSW_SL_SOFT_RESET = 3,\n\tCPSW_SL_RX_MAXLEN = 4,\n\tCPSW_SL_BOFFTEST = 5,\n\tCPSW_SL_RX_PAUSE = 6,\n\tCPSW_SL_TX_PAUSE = 7,\n\tCPSW_SL_EMCONTROL = 8,\n\tCPSW_SL_RX_PRI_MAP = 9,\n\tCPSW_SL_TX_GAP = 10,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_led_event {\n\tCPU_LED_IDLE_START = 0,\n\tCPU_LED_IDLE_END = 1,\n\tCPU_LED_START = 2,\n\tCPU_LED_STOP = 3,\n\tCPU_LED_HALTED = 4,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_pm_event {\n\tCPU_PM_ENTER = 0,\n\tCPU_PM_ENTER_FAILED = 1,\n\tCPU_PM_EXIT = 2,\n\tCPU_CLUSTER_PM_ENTER = 3,\n\tCPU_CLUSTER_PM_ENTER_FAILED = 4,\n\tCPU_CLUSTER_PM_EXIT = 5,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tNR_STATS = 10,\n};\n\nenum cpubiuctrl_regs {\n\tCPU_CREDIT_REG = 0,\n\tCPU_MCP_FLOW_REG = 1,\n\tCPU_WRITEBACK_CTRL_REG = 2,\n\tRAC_CONFIG0_REG = 3,\n\tRAC_CONFIG1_REG = 4,\n\tNUM_CPU_BIUCTRL_REGS = 5,\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum createmode4 {\n\tNFS4_CREATE_UNCHECKED = 0,\n\tNFS4_CREATE_GUARDED = 1,\n\tNFS4_CREATE_EXCLUSIVE = 2,\n\tNFS4_CREATE_EXCLUSIVE4_1 = 3,\n};\n\nenum criteria {\n\tCR_POWER2_ALIGNED = 0,\n\tCR_GOAL_LEN_FAST = 1,\n\tCR_BEST_AVAIL_LEN = 2,\n\tCR_GOAL_LEN_SLOW = 3,\n\tCR_ANY_FREE = 4,\n\tEXT4_MB_NUM_CRS = 5,\n};\n\nenum crypto_attr_type_t {\n\tCRYPTOCFGA_UNSPEC = 0,\n\tCRYPTOCFGA_PRIORITY_VAL = 1,\n\tCRYPTOCFGA_REPORT_LARVAL = 2,\n\tCRYPTOCFGA_REPORT_HASH = 3,\n\tCRYPTOCFGA_REPORT_BLKCIPHER = 4,\n\tCRYPTOCFGA_REPORT_AEAD = 5,\n\tCRYPTOCFGA_REPORT_COMPRESS = 6,\n\tCRYPTOCFGA_REPORT_RNG = 7,\n\tCRYPTOCFGA_REPORT_CIPHER = 8,\n\tCRYPTOCFGA_REPORT_AKCIPHER = 9,\n\tCRYPTOCFGA_REPORT_KPP = 10,\n\tCRYPTOCFGA_REPORT_ACOMP = 11,\n\tCRYPTOCFGA_STAT_LARVAL = 12,\n\tCRYPTOCFGA_STAT_HASH = 13,\n\tCRYPTOCFGA_STAT_BLKCIPHER = 14,\n\tCRYPTOCFGA_STAT_AEAD = 15,\n\tCRYPTOCFGA_STAT_COMPRESS = 16,\n\tCRYPTOCFGA_STAT_RNG = 17,\n\tCRYPTOCFGA_STAT_CIPHER = 18,\n\tCRYPTOCFGA_STAT_AKCIPHER = 19,\n\tCRYPTOCFGA_STAT_KPP = 20,\n\tCRYPTOCFGA_STAT_ACOMP = 21,\n\tCRYPTOCFGA_REPORT_SIG = 22,\n\t__CRYPTOCFGA_MAX = 23,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum cti_port_type {\n\tCTI_PORT_TYPE_NONE = 0,\n\tCTI_PORT_TYPE_RS232 = 1,\n\tCTI_PORT_TYPE_RS422_485 = 2,\n\tCTI_PORT_TYPE_RS232_422_485_HW = 3,\n\tCTI_PORT_TYPE_RS232_422_485_SW = 4,\n\tCTI_PORT_TYPE_RS232_422_485_4B = 5,\n\tCTI_PORT_TYPE_RS232_422_485_2B = 6,\n\tCTI_PORT_TYPE_MAX = 7,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum current_trim {\n\tCUR_NOMINAL = 0,\n\tCUR_PLUS_1_56_PCT = 1,\n\tCUR_PLUS_3_12_PCT = 2,\n\tCUR_PLUS_4_68_PCT = 3,\n\tCUR_PLUS_6_24_PCT = 4,\n\tCUR_PLUS_7_8_PCT = 5,\n\tCUR_PLUS_9_36_PCT = 6,\n\tCUR_PLUS_10_92_PCT = 7,\n\tCUR_PLUS_12_48_PCT = 8,\n\tCUR_PLUS_14_04_PCT = 9,\n\tCUR_PLUS_15_6_PCT = 10,\n\tCUR_PLUS_17_16_PCT = 11,\n\tCUR_PLUS_19_01_PCT = 12,\n\tCUR_PLUS_20_58_PCT = 13,\n\tCUR_PLUS_22_16_PCT = 14,\n\tCUR_PLUS_23_73_PCT = 15,\n\tCUR_MAX = 16,\n};\n\nenum cygnus_pcie_phy_id {\n\tCYGNUS_PHY_PCIE0 = 0,\n\tCYGNUS_PHY_PCIE1 = 1,\n\tMAX_NUM_PHYS = 2,\n};\n\nenum d40_command {\n\tD40_DMA_STOP = 0,\n\tD40_DMA_RUN = 1,\n\tD40_DMA_SUSPEND_REQ = 2,\n\tD40_DMA_SUSPENDED = 3,\n};\n\nenum d40_events {\n\tD40_DEACTIVATE_EVENTLINE = 0,\n\tD40_ACTIVATE_EVENTLINE = 1,\n\tD40_SUSPEND_REQ_EVENTLINE = 2,\n\tD40_ROUND_EVENTLINE = 3,\n};\n\nenum d40_lli_flags {\n\tLLI_ADDR_INC = 1,\n\tLLI_TERM_INT = 2,\n\tLLI_CYCLIC = 4,\n\tLLI_LAST_LINK = 8,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum da9052_chip_id {\n\tDA9052 = 0,\n\tDA9053_AA = 1,\n\tDA9053_BA = 2,\n\tDA9053_BB = 3,\n\tDA9053_BC = 4,\n};\n\nenum data_content4 {\n\tNFS4_CONTENT_DATA = 0,\n\tNFS4_CONTENT_HOLE = 1,\n};\n\nenum db8500_regulator_id {\n\tDB8500_REGULATOR_VAPE = 0,\n\tDB8500_REGULATOR_VARM = 1,\n\tDB8500_REGULATOR_VMODEM = 2,\n\tDB8500_REGULATOR_VPLL = 3,\n\tDB8500_REGULATOR_VSMPS1 = 4,\n\tDB8500_REGULATOR_VSMPS2 = 5,\n\tDB8500_REGULATOR_VSMPS3 = 6,\n\tDB8500_REGULATOR_VRF1 = 7,\n\tDB8500_REGULATOR_SWITCH_SVAMMDSP = 8,\n\tDB8500_REGULATOR_SWITCH_SVAMMDSPRET = 9,\n\tDB8500_REGULATOR_SWITCH_SVAPIPE = 10,\n\tDB8500_REGULATOR_SWITCH_SIAMMDSP = 11,\n\tDB8500_REGULATOR_SWITCH_SIAMMDSPRET = 12,\n\tDB8500_REGULATOR_SWITCH_SIAPIPE = 13,\n\tDB8500_REGULATOR_SWITCH_SGA = 14,\n\tDB8500_REGULATOR_SWITCH_B2R2_MCDE = 15,\n\tDB8500_REGULATOR_SWITCH_ESRAM12 = 16,\n\tDB8500_REGULATOR_SWITCH_ESRAM12RET = 17,\n\tDB8500_REGULATOR_SWITCH_ESRAM34 = 18,\n\tDB8500_REGULATOR_SWITCH_ESRAM34RET = 19,\n\tDB8500_NUM_REGULATORS = 20,\n};\n\nenum dbc_state {\n\tDS_DISABLED = 0,\n\tDS_INITIALIZED = 1,\n\tDS_ENABLED = 2,\n\tDS_CONNECTED = 3,\n\tDS_CONFIGURED = 4,\n\tDS_MAX = 5,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dc_level_vals {\n\tDC_NOMINAL = 0,\n\tDC_PLUS_5_TO_7_MV = 1,\n\tDC_PLUS_10_TO_14_MV = 2,\n\tDC_MINUS_5_TO_7_MV = 3,\n\tDC_MAX = 4,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum ddr_pwrst {\n\tDDR_PWR_STATE_UNCHANGED = 0,\n\tDDR_PWR_STATE_ON = 1,\n\tDDR_PWR_STATE_OFFLOWLAT = 2,\n\tDDR_PWR_STATE_OFFHIGHLAT = 3,\n};\n\nenum debug_counters {\n\tSENT_OK = 0,\n\tSENT_FAIL = 1,\n\tSENT_FAIL_POLLING_UNSUPPORTED = 2,\n\tSENT_FAIL_CHANNEL_NOT_FOUND = 3,\n\tRESPONSE_OK = 4,\n\tNOTIFICATION_OK = 5,\n\tDELAYED_RESPONSE_OK = 6,\n\tXFERS_RESPONSE_TIMEOUT = 7,\n\tXFERS_RESPONSE_POLLED_TIMEOUT = 8,\n\tRESPONSE_POLLED_OK = 9,\n\tERR_MSG_UNEXPECTED = 10,\n\tERR_MSG_INVALID = 11,\n\tERR_MSG_NOMEM = 12,\n\tERR_PROTOCOL = 13,\n\tXFERS_INFLIGHT = 14,\n\tSCMI_DEBUG_COUNTERS_LAST = 15,\n};\n\nenum decode_reg_type {\n\tREG_TYPE_NONE = 0,\n\tREG_TYPE_ANY = 1,\n\tREG_TYPE_SAMEAS16 = 2,\n\tREG_TYPE_SP = 3,\n\tREG_TYPE_PC = 4,\n\tREG_TYPE_NOSP = 5,\n\tREG_TYPE_NOSPPC = 6,\n\tREG_TYPE_NOPC = 7,\n\tREG_TYPE_NOPCWB = 8,\n\tREG_TYPE_NOPCX = 9,\n\tREG_TYPE_NOSPPCX = 10,\n\tREG_TYPE_0 = 0,\n};\n\nenum decode_type {\n\tDECODE_TYPE_END = 0,\n\tDECODE_TYPE_TABLE = 1,\n\tDECODE_TYPE_CUSTOM = 2,\n\tDECODE_TYPE_SIMULATE = 3,\n\tDECODE_TYPE_EMULATE = 4,\n\tDECODE_TYPE_OR = 5,\n\tDECODE_TYPE_REJECT = 6,\n\tNUM_DECODE_TYPES = 7,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum depot_counter_id {\n\tDEPOT_COUNTER_REFD_ALLOCS = 0,\n\tDEPOT_COUNTER_REFD_FREES = 1,\n\tDEPOT_COUNTER_REFD_INUSE = 2,\n\tDEPOT_COUNTER_FREELIST_SIZE = 3,\n\tDEPOT_COUNTER_PERSIST_COUNT = 4,\n\tDEPOT_COUNTER_PERSIST_BYTES = 5,\n\tDEPOT_COUNTER_COUNT = 6,\n};\n\nenum desc_id {\n\tAVE_DESCID_RX = 0,\n\tAVE_DESCID_TX = 1,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum desc_state___2 {\n\tAVE_DESC_RX_PERMIT = 0,\n\tAVE_DESC_RX_SUSPEND = 1,\n\tAVE_DESC_START = 2,\n\tAVE_DESC_STOP = 3,\n};\n\nenum desc_status {\n\tFREE = 0,\n\tPREP = 1,\n\tBUSY = 2,\n\tPAUSED = 3,\n\tDONE___2 = 4,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_pm_opp_event {\n\tOPP_EVENT_ADD = 0,\n\tOPP_EVENT_REMOVE = 1,\n\tOPP_EVENT_ENABLE = 2,\n\tOPP_EVENT_DISABLE = 3,\n\tOPP_EVENT_ADJUST_VOLTAGE = 4,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum dev_type {\n\tDEV_UNKNOWN = 0,\n\tDEV_X1 = 1,\n\tDEV_X2 = 2,\n\tDEV_X4 = 3,\n\tDEV_X8 = 4,\n\tDEV_X16 = 5,\n\tDEV_X32 = 6,\n\tDEV_X64 = 7,\n};\n\nenum devfreq_parent_dev_type {\n\tDEVFREQ_PARENT_DEV = 0,\n\tCPUFREQ_PARENT_DEV = 1,\n};\n\nenum devfreq_timer {\n\tDEVFREQ_TIMER_DEFERRABLE = 0,\n\tDEVFREQ_TIMER_DELAYED = 1,\n\tDEVFREQ_TIMER_NUM = 2,\n};\n\nenum device_id {\n\tMAX8973 = 0,\n\tMAX77621 = 1,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_attr {\n\tDEVLINK_ATTR_UNSPEC = 0,\n\tDEVLINK_ATTR_BUS_NAME = 1,\n\tDEVLINK_ATTR_DEV_NAME = 2,\n\tDEVLINK_ATTR_PORT_INDEX = 3,\n\tDEVLINK_ATTR_PORT_TYPE = 4,\n\tDEVLINK_ATTR_PORT_DESIRED_TYPE = 5,\n\tDEVLINK_ATTR_PORT_NETDEV_IFINDEX = 6,\n\tDEVLINK_ATTR_PORT_NETDEV_NAME = 7,\n\tDEVLINK_ATTR_PORT_IBDEV_NAME = 8,\n\tDEVLINK_ATTR_PORT_SPLIT_COUNT = 9,\n\tDEVLINK_ATTR_PORT_SPLIT_GROUP = 10,\n\tDEVLINK_ATTR_SB_INDEX = 11,\n\tDEVLINK_ATTR_SB_SIZE = 12,\n\tDEVLINK_ATTR_SB_INGRESS_POOL_COUNT = 13,\n\tDEVLINK_ATTR_SB_EGRESS_POOL_COUNT = 14,\n\tDEVLINK_ATTR_SB_INGRESS_TC_COUNT = 15,\n\tDEVLINK_ATTR_SB_EGRESS_TC_COUNT = 16,\n\tDEVLINK_ATTR_SB_POOL_INDEX = 17,\n\tDEVLINK_ATTR_SB_POOL_TYPE = 18,\n\tDEVLINK_ATTR_SB_POOL_SIZE = 19,\n\tDEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE = 20,\n\tDEVLINK_ATTR_SB_THRESHOLD = 21,\n\tDEVLINK_ATTR_SB_TC_INDEX = 22,\n\tDEVLINK_ATTR_SB_OCC_CUR = 23,\n\tDEVLINK_ATTR_SB_OCC_MAX = 24,\n\tDEVLINK_ATTR_ESWITCH_MODE = 25,\n\tDEVLINK_ATTR_ESWITCH_INLINE_MODE = 26,\n\tDEVLINK_ATTR_DPIPE_TABLES = 27,\n\tDEVLINK_ATTR_DPIPE_TABLE = 28,\n\tDEVLINK_ATTR_DPIPE_TABLE_NAME = 29,\n\tDEVLINK_ATTR_DPIPE_TABLE_SIZE = 30,\n\tDEVLINK_ATTR_DPIPE_TABLE_MATCHES = 31,\n\tDEVLINK_ATTR_DPIPE_TABLE_ACTIONS = 32,\n\tDEVLINK_ATTR_DPIPE_TABLE_COUNTERS_ENABLED = 33,\n\tDEVLINK_ATTR_DPIPE_ENTRIES = 34,\n\tDEVLINK_ATTR_DPIPE_ENTRY = 35,\n\tDEVLINK_ATTR_DPIPE_ENTRY_INDEX = 36,\n\tDEVLINK_ATTR_DPIPE_ENTRY_MATCH_VALUES = 37,\n\tDEVLINK_ATTR_DPIPE_ENTRY_ACTION_VALUES = 38,\n\tDEVLINK_ATTR_DPIPE_ENTRY_COUNTER = 39,\n\tDEVLINK_ATTR_DPIPE_MATCH = 40,\n\tDEVLINK_ATTR_DPIPE_MATCH_VALUE = 41,\n\tDEVLINK_ATTR_DPIPE_MATCH_TYPE = 42,\n\tDEVLINK_ATTR_DPIPE_ACTION = 43,\n\tDEVLINK_ATTR_DPIPE_ACTION_VALUE = 44,\n\tDEVLINK_ATTR_DPIPE_ACTION_TYPE = 45,\n\tDEVLINK_ATTR_DPIPE_VALUE = 46,\n\tDEVLINK_ATTR_DPIPE_VALUE_MASK = 47,\n\tDEVLINK_ATTR_DPIPE_VALUE_MAPPING = 48,\n\tDEVLINK_ATTR_DPIPE_HEADERS = 49,\n\tDEVLINK_ATTR_DPIPE_HEADER = 50,\n\tDEVLINK_ATTR_DPIPE_HEADER_NAME = 51,\n\tDEVLINK_ATTR_DPIPE_HEADER_ID = 52,\n\tDEVLINK_ATTR_DPIPE_HEADER_FIELDS = 53,\n\tDEVLINK_ATTR_DPIPE_HEADER_GLOBAL = 54,\n\tDEVLINK_ATTR_DPIPE_HEADER_INDEX = 55,\n\tDEVLINK_ATTR_DPIPE_FIELD = 56,\n\tDEVLINK_ATTR_DPIPE_FIELD_NAME = 57,\n\tDEVLINK_ATTR_DPIPE_FIELD_ID = 58,\n\tDEVLINK_ATTR_DPIPE_FIELD_BITWIDTH = 59,\n\tDEVLINK_ATTR_DPIPE_FIELD_MAPPING_TYPE = 60,\n\tDEVLINK_ATTR_PAD = 61,\n\tDEVLINK_ATTR_ESWITCH_ENCAP_MODE = 62,\n\tDEVLINK_ATTR_RESOURCE_LIST = 63,\n\tDEVLINK_ATTR_RESOURCE = 64,\n\tDEVLINK_ATTR_RESOURCE_NAME = 65,\n\tDEVLINK_ATTR_RESOURCE_ID = 66,\n\tDEVLINK_ATTR_RESOURCE_SIZE = 67,\n\tDEVLINK_ATTR_RESOURCE_SIZE_NEW = 68,\n\tDEVLINK_ATTR_RESOURCE_SIZE_VALID = 69,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MIN = 70,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MAX = 71,\n\tDEVLINK_ATTR_RESOURCE_SIZE_GRAN = 72,\n\tDEVLINK_ATTR_RESOURCE_UNIT = 73,\n\tDEVLINK_ATTR_RESOURCE_OCC = 74,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID = 75,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS = 76,\n\tDEVLINK_ATTR_PORT_FLAVOUR = 77,\n\tDEVLINK_ATTR_PORT_NUMBER = 78,\n\tDEVLINK_ATTR_PORT_SPLIT_SUBPORT_NUMBER = 79,\n\tDEVLINK_ATTR_PARAM = 80,\n\tDEVLINK_ATTR_PARAM_NAME = 81,\n\tDEVLINK_ATTR_PARAM_GENERIC = 82,\n\tDEVLINK_ATTR_PARAM_TYPE = 83,\n\tDEVLINK_ATTR_PARAM_VALUES_LIST = 84,\n\tDEVLINK_ATTR_PARAM_VALUE = 85,\n\tDEVLINK_ATTR_PARAM_VALUE_DATA = 86,\n\tDEVLINK_ATTR_PARAM_VALUE_CMODE = 87,\n\tDEVLINK_ATTR_REGION_NAME = 88,\n\tDEVLINK_ATTR_REGION_SIZE = 89,\n\tDEVLINK_ATTR_REGION_SNAPSHOTS = 90,\n\tDEVLINK_ATTR_REGION_SNAPSHOT = 91,\n\tDEVLINK_ATTR_REGION_SNAPSHOT_ID = 92,\n\tDEVLINK_ATTR_REGION_CHUNKS = 93,\n\tDEVLINK_ATTR_REGION_CHUNK = 94,\n\tDEVLINK_ATTR_REGION_CHUNK_DATA = 95,\n\tDEVLINK_ATTR_REGION_CHUNK_ADDR = 96,\n\tDEVLINK_ATTR_REGION_CHUNK_LEN = 97,\n\tDEVLINK_ATTR_INFO_DRIVER_NAME = 98,\n\tDEVLINK_ATTR_INFO_SERIAL_NUMBER = 99,\n\tDEVLINK_ATTR_INFO_VERSION_FIXED = 100,\n\tDEVLINK_ATTR_INFO_VERSION_RUNNING = 101,\n\tDEVLINK_ATTR_INFO_VERSION_STORED = 102,\n\tDEVLINK_ATTR_INFO_VERSION_NAME = 103,\n\tDEVLINK_ATTR_INFO_VERSION_VALUE = 104,\n\tDEVLINK_ATTR_SB_POOL_CELL_SIZE = 105,\n\tDEVLINK_ATTR_FMSG = 106,\n\tDEVLINK_ATTR_FMSG_OBJ_NEST_START = 107,\n\tDEVLINK_ATTR_FMSG_PAIR_NEST_START = 108,\n\tDEVLINK_ATTR_FMSG_ARR_NEST_START = 109,\n\tDEVLINK_ATTR_FMSG_NEST_END = 110,\n\tDEVLINK_ATTR_FMSG_OBJ_NAME = 111,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_TYPE = 112,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_DATA = 113,\n\tDEVLINK_ATTR_HEALTH_REPORTER = 114,\n\tDEVLINK_ATTR_HEALTH_REPORTER_NAME = 115,\n\tDEVLINK_ATTR_HEALTH_REPORTER_STATE = 116,\n\tDEVLINK_ATTR_HEALTH_REPORTER_ERR_COUNT = 117,\n\tDEVLINK_ATTR_HEALTH_REPORTER_RECOVER_COUNT = 118,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS = 119,\n\tDEVLINK_ATTR_HEALTH_REPORTER_GRACEFUL_PERIOD = 120,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_RECOVER = 121,\n\tDEVLINK_ATTR_FLASH_UPDATE_FILE_NAME = 122,\n\tDEVLINK_ATTR_FLASH_UPDATE_COMPONENT = 123,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_MSG = 124,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_DONE = 125,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TOTAL = 126,\n\tDEVLINK_ATTR_PORT_PCI_PF_NUMBER = 127,\n\tDEVLINK_ATTR_PORT_PCI_VF_NUMBER = 128,\n\tDEVLINK_ATTR_STATS = 129,\n\tDEVLINK_ATTR_TRAP_NAME = 130,\n\tDEVLINK_ATTR_TRAP_ACTION = 131,\n\tDEVLINK_ATTR_TRAP_TYPE = 132,\n\tDEVLINK_ATTR_TRAP_GENERIC = 133,\n\tDEVLINK_ATTR_TRAP_METADATA = 134,\n\tDEVLINK_ATTR_TRAP_GROUP_NAME = 135,\n\tDEVLINK_ATTR_RELOAD_FAILED = 136,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS_NS = 137,\n\tDEVLINK_ATTR_NETNS_FD = 138,\n\tDEVLINK_ATTR_NETNS_PID = 139,\n\tDEVLINK_ATTR_NETNS_ID = 140,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_DUMP = 141,\n\tDEVLINK_ATTR_TRAP_POLICER_ID = 142,\n\tDEVLINK_ATTR_TRAP_POLICER_RATE = 143,\n\tDEVLINK_ATTR_TRAP_POLICER_BURST = 144,\n\tDEVLINK_ATTR_PORT_FUNCTION = 145,\n\tDEVLINK_ATTR_INFO_BOARD_SERIAL_NUMBER = 146,\n\tDEVLINK_ATTR_PORT_LANES = 147,\n\tDEVLINK_ATTR_PORT_SPLITTABLE = 148,\n\tDEVLINK_ATTR_PORT_EXTERNAL = 149,\n\tDEVLINK_ATTR_PORT_CONTROLLER_NUMBER = 150,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TIMEOUT = 151,\n\tDEVLINK_ATTR_FLASH_UPDATE_OVERWRITE_MASK = 152,\n\tDEVLINK_ATTR_RELOAD_ACTION = 153,\n\tDEVLINK_ATTR_RELOAD_ACTIONS_PERFORMED = 154,\n\tDEVLINK_ATTR_RELOAD_LIMITS = 155,\n\tDEVLINK_ATTR_DEV_STATS = 156,\n\tDEVLINK_ATTR_RELOAD_STATS = 157,\n\tDEVLINK_ATTR_RELOAD_STATS_ENTRY = 158,\n\tDEVLINK_ATTR_RELOAD_STATS_LIMIT = 159,\n\tDEVLINK_ATTR_RELOAD_STATS_VALUE = 160,\n\tDEVLINK_ATTR_REMOTE_RELOAD_STATS = 161,\n\tDEVLINK_ATTR_RELOAD_ACTION_INFO = 162,\n\tDEVLINK_ATTR_RELOAD_ACTION_STATS = 163,\n\tDEVLINK_ATTR_PORT_PCI_SF_NUMBER = 164,\n\tDEVLINK_ATTR_RATE_TYPE = 165,\n\tDEVLINK_ATTR_RATE_TX_SHARE = 166,\n\tDEVLINK_ATTR_RATE_TX_MAX = 167,\n\tDEVLINK_ATTR_RATE_NODE_NAME = 168,\n\tDEVLINK_ATTR_RATE_PARENT_NODE_NAME = 169,\n\tDEVLINK_ATTR_REGION_MAX_SNAPSHOTS = 170,\n\tDEVLINK_ATTR_LINECARD_INDEX = 171,\n\tDEVLINK_ATTR_LINECARD_STATE = 172,\n\tDEVLINK_ATTR_LINECARD_TYPE = 173,\n\tDEVLINK_ATTR_LINECARD_SUPPORTED_TYPES = 174,\n\tDEVLINK_ATTR_NESTED_DEVLINK = 175,\n\tDEVLINK_ATTR_SELFTESTS = 176,\n\tDEVLINK_ATTR_RATE_TX_PRIORITY = 177,\n\tDEVLINK_ATTR_RATE_TX_WEIGHT = 178,\n\tDEVLINK_ATTR_REGION_DIRECT = 179,\n\tDEVLINK_ATTR_RATE_TC_BWS = 180,\n\tDEVLINK_ATTR_HEALTH_REPORTER_BURST_PERIOD = 181,\n\tDEVLINK_ATTR_PARAM_VALUE_DEFAULT = 182,\n\tDEVLINK_ATTR_PARAM_RESET_DEFAULT = 183,\n\t__DEVLINK_ATTR_MAX = 184,\n\tDEVLINK_ATTR_MAX = 183,\n};\n\nenum devlink_attr_selftest_id {\n\tDEVLINK_ATTR_SELFTEST_ID_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_ID_FLASH = 1,\n\t__DEVLINK_ATTR_SELFTEST_ID_MAX = 2,\n\tDEVLINK_ATTR_SELFTEST_ID_MAX = 1,\n};\n\nenum devlink_attr_selftest_result {\n\tDEVLINK_ATTR_SELFTEST_RESULT_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_RESULT = 1,\n\tDEVLINK_ATTR_SELFTEST_RESULT_ID = 2,\n\tDEVLINK_ATTR_SELFTEST_RESULT_STATUS = 3,\n\t__DEVLINK_ATTR_SELFTEST_RESULT_MAX = 4,\n\tDEVLINK_ATTR_SELFTEST_RESULT_MAX = 3,\n};\n\nenum devlink_command {\n\tDEVLINK_CMD_UNSPEC = 0,\n\tDEVLINK_CMD_GET = 1,\n\tDEVLINK_CMD_SET = 2,\n\tDEVLINK_CMD_NEW = 3,\n\tDEVLINK_CMD_DEL = 4,\n\tDEVLINK_CMD_PORT_GET = 5,\n\tDEVLINK_CMD_PORT_SET = 6,\n\tDEVLINK_CMD_PORT_NEW = 7,\n\tDEVLINK_CMD_PORT_DEL = 8,\n\tDEVLINK_CMD_PORT_SPLIT = 9,\n\tDEVLINK_CMD_PORT_UNSPLIT = 10,\n\tDEVLINK_CMD_SB_GET = 11,\n\tDEVLINK_CMD_SB_SET = 12,\n\tDEVLINK_CMD_SB_NEW = 13,\n\tDEVLINK_CMD_SB_DEL = 14,\n\tDEVLINK_CMD_SB_POOL_GET = 15,\n\tDEVLINK_CMD_SB_POOL_SET = 16,\n\tDEVLINK_CMD_SB_POOL_NEW = 17,\n\tDEVLINK_CMD_SB_POOL_DEL = 18,\n\tDEVLINK_CMD_SB_PORT_POOL_GET = 19,\n\tDEVLINK_CMD_SB_PORT_POOL_SET = 20,\n\tDEVLINK_CMD_SB_PORT_POOL_NEW = 21,\n\tDEVLINK_CMD_SB_PORT_POOL_DEL = 22,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_GET = 23,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_SET = 24,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_NEW = 25,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_DEL = 26,\n\tDEVLINK_CMD_SB_OCC_SNAPSHOT = 27,\n\tDEVLINK_CMD_SB_OCC_MAX_CLEAR = 28,\n\tDEVLINK_CMD_ESWITCH_GET = 29,\n\tDEVLINK_CMD_ESWITCH_SET = 30,\n\tDEVLINK_CMD_DPIPE_TABLE_GET = 31,\n\tDEVLINK_CMD_DPIPE_ENTRIES_GET = 32,\n\tDEVLINK_CMD_DPIPE_HEADERS_GET = 33,\n\tDEVLINK_CMD_DPIPE_TABLE_COUNTERS_SET = 34,\n\tDEVLINK_CMD_RESOURCE_SET = 35,\n\tDEVLINK_CMD_RESOURCE_DUMP = 36,\n\tDEVLINK_CMD_RELOAD = 37,\n\tDEVLINK_CMD_PARAM_GET = 38,\n\tDEVLINK_CMD_PARAM_SET = 39,\n\tDEVLINK_CMD_PARAM_NEW = 40,\n\tDEVLINK_CMD_PARAM_DEL = 41,\n\tDEVLINK_CMD_REGION_GET = 42,\n\tDEVLINK_CMD_REGION_SET = 43,\n\tDEVLINK_CMD_REGION_NEW = 44,\n\tDEVLINK_CMD_REGION_DEL = 45,\n\tDEVLINK_CMD_REGION_READ = 46,\n\tDEVLINK_CMD_PORT_PARAM_GET = 47,\n\tDEVLINK_CMD_PORT_PARAM_SET = 48,\n\tDEVLINK_CMD_PORT_PARAM_NEW = 49,\n\tDEVLINK_CMD_PORT_PARAM_DEL = 50,\n\tDEVLINK_CMD_INFO_GET = 51,\n\tDEVLINK_CMD_HEALTH_REPORTER_GET = 52,\n\tDEVLINK_CMD_HEALTH_REPORTER_SET = 53,\n\tDEVLINK_CMD_HEALTH_REPORTER_RECOVER = 54,\n\tDEVLINK_CMD_HEALTH_REPORTER_DIAGNOSE = 55,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_GET = 56,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_CLEAR = 57,\n\tDEVLINK_CMD_FLASH_UPDATE = 58,\n\tDEVLINK_CMD_FLASH_UPDATE_END = 59,\n\tDEVLINK_CMD_FLASH_UPDATE_STATUS = 60,\n\tDEVLINK_CMD_TRAP_GET = 61,\n\tDEVLINK_CMD_TRAP_SET = 62,\n\tDEVLINK_CMD_TRAP_NEW = 63,\n\tDEVLINK_CMD_TRAP_DEL = 64,\n\tDEVLINK_CMD_TRAP_GROUP_GET = 65,\n\tDEVLINK_CMD_TRAP_GROUP_SET = 66,\n\tDEVLINK_CMD_TRAP_GROUP_NEW = 67,\n\tDEVLINK_CMD_TRAP_GROUP_DEL = 68,\n\tDEVLINK_CMD_TRAP_POLICER_GET = 69,\n\tDEVLINK_CMD_TRAP_POLICER_SET = 70,\n\tDEVLINK_CMD_TRAP_POLICER_NEW = 71,\n\tDEVLINK_CMD_TRAP_POLICER_DEL = 72,\n\tDEVLINK_CMD_HEALTH_REPORTER_TEST = 73,\n\tDEVLINK_CMD_RATE_GET = 74,\n\tDEVLINK_CMD_RATE_SET = 75,\n\tDEVLINK_CMD_RATE_NEW = 76,\n\tDEVLINK_CMD_RATE_DEL = 77,\n\tDEVLINK_CMD_LINECARD_GET = 78,\n\tDEVLINK_CMD_LINECARD_SET = 79,\n\tDEVLINK_CMD_LINECARD_NEW = 80,\n\tDEVLINK_CMD_LINECARD_DEL = 81,\n\tDEVLINK_CMD_SELFTESTS_GET = 82,\n\tDEVLINK_CMD_SELFTESTS_RUN = 83,\n\tDEVLINK_CMD_NOTIFY_FILTER_SET = 84,\n\t__DEVLINK_CMD_MAX = 85,\n\tDEVLINK_CMD_MAX = 84,\n};\n\nenum devlink_dpipe_action_type {\n\tDEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY = 0,\n};\n\nenum devlink_dpipe_field_ethernet_id {\n\tDEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC = 0,\n};\n\nenum devlink_dpipe_field_ipv4_id {\n\tDEVLINK_DPIPE_FIELD_IPV4_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_ipv6_id {\n\tDEVLINK_DPIPE_FIELD_IPV6_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_mapping_type {\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0,\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1,\n};\n\nenum devlink_dpipe_header_id {\n\tDEVLINK_DPIPE_HEADER_ETHERNET = 0,\n\tDEVLINK_DPIPE_HEADER_IPV4 = 1,\n\tDEVLINK_DPIPE_HEADER_IPV6 = 2,\n};\n\nenum devlink_dpipe_match_type {\n\tDEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT = 0,\n};\n\nenum devlink_eswitch_encap_mode {\n\tDEVLINK_ESWITCH_ENCAP_MODE_NONE = 0,\n\tDEVLINK_ESWITCH_ENCAP_MODE_BASIC = 1,\n};\n\nenum devlink_health_reporter_state {\n\tDEVLINK_HEALTH_REPORTER_STATE_HEALTHY = 0,\n\tDEVLINK_HEALTH_REPORTER_STATE_ERROR = 1,\n};\n\nenum devlink_info_version_type {\n\tDEVLINK_INFO_VERSION_TYPE_NONE = 0,\n\tDEVLINK_INFO_VERSION_TYPE_COMPONENT = 1,\n};\n\nenum devlink_linecard_state {\n\tDEVLINK_LINECARD_STATE_UNSPEC = 0,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONED = 1,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONING = 2,\n\tDEVLINK_LINECARD_STATE_PROVISIONING = 3,\n\tDEVLINK_LINECARD_STATE_PROVISIONING_FAILED = 4,\n\tDEVLINK_LINECARD_STATE_PROVISIONED = 5,\n\tDEVLINK_LINECARD_STATE_ACTIVE = 6,\n\t__DEVLINK_LINECARD_STATE_MAX = 7,\n\tDEVLINK_LINECARD_STATE_MAX = 6,\n};\n\nenum devlink_multicast_groups {\n\tDEVLINK_MCGRP_CONFIG = 0,\n};\n\nenum devlink_param_cmode {\n\tDEVLINK_PARAM_CMODE_RUNTIME = 0,\n\tDEVLINK_PARAM_CMODE_DRIVERINIT = 1,\n\tDEVLINK_PARAM_CMODE_PERMANENT = 2,\n\t__DEVLINK_PARAM_CMODE_MAX = 3,\n\tDEVLINK_PARAM_CMODE_MAX = 2,\n};\n\nenum devlink_param_generic_id {\n\tDEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET = 0,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MACS = 1,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_SRIOV = 2,\n\tDEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT = 3,\n\tDEVLINK_PARAM_GENERIC_ID_IGNORE_ARI = 4,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX = 5,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN = 6,\n\tDEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY = 7,\n\tDEVLINK_PARAM_GENERIC_ID_RESET_DEV_ON_DRV_PROBE = 8,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE = 9,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_REMOTE_DEV_RESET = 10,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ETH = 11,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA = 12,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_VNET = 13,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_IWARP = 14,\n\tDEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE = 15,\n\tDEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE = 16,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_PHC = 17,\n\tDEVLINK_PARAM_GENERIC_ID_CLOCK_ID = 18,\n\tDEVLINK_PARAM_GENERIC_ID_TOTAL_VFS = 19,\n\tDEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS = 20,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF = 21,\n\t__DEVLINK_PARAM_GENERIC_ID_MAX = 22,\n\tDEVLINK_PARAM_GENERIC_ID_MAX = 21,\n};\n\nenum devlink_param_type {\n\tDEVLINK_PARAM_TYPE_U8 = 1,\n\tDEVLINK_PARAM_TYPE_U16 = 2,\n\tDEVLINK_PARAM_TYPE_U32 = 3,\n\tDEVLINK_PARAM_TYPE_U64 = 4,\n\tDEVLINK_PARAM_TYPE_STRING = 5,\n\tDEVLINK_PARAM_TYPE_BOOL = 6,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_attr_cap {\n\tDEVLINK_PORT_FN_ATTR_CAP_ROCE_BIT = 0,\n\tDEVLINK_PORT_FN_ATTR_CAP_MIGRATABLE_BIT = 1,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_CRYPTO_BIT = 2,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_PACKET_BIT = 3,\n\t__DEVLINK_PORT_FN_ATTR_CAPS_MAX = 4,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_function_attr {\n\tDEVLINK_PORT_FUNCTION_ATTR_UNSPEC = 0,\n\tDEVLINK_PORT_FUNCTION_ATTR_HW_ADDR = 1,\n\tDEVLINK_PORT_FN_ATTR_STATE = 2,\n\tDEVLINK_PORT_FN_ATTR_OPSTATE = 3,\n\tDEVLINK_PORT_FN_ATTR_CAPS = 4,\n\tDEVLINK_PORT_FN_ATTR_DEVLINK = 5,\n\tDEVLINK_PORT_FN_ATTR_MAX_IO_EQS = 6,\n\t__DEVLINK_PORT_FUNCTION_ATTR_MAX = 7,\n\tDEVLINK_PORT_FUNCTION_ATTR_MAX = 6,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_tc_attr {\n\tDEVLINK_RATE_TC_ATTR_UNSPEC = 0,\n\tDEVLINK_RATE_TC_ATTR_INDEX = 1,\n\tDEVLINK_RATE_TC_ATTR_BW = 2,\n\t__DEVLINK_RATE_TC_ATTR_MAX = 3,\n\tDEVLINK_RATE_TC_ATTR_MAX = 2,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devlink_reload_action {\n\tDEVLINK_RELOAD_ACTION_UNSPEC = 0,\n\tDEVLINK_RELOAD_ACTION_DRIVER_REINIT = 1,\n\tDEVLINK_RELOAD_ACTION_FW_ACTIVATE = 2,\n\t__DEVLINK_RELOAD_ACTION_MAX = 3,\n\tDEVLINK_RELOAD_ACTION_MAX = 2,\n};\n\nenum devlink_reload_limit {\n\tDEVLINK_RELOAD_LIMIT_UNSPEC = 0,\n\tDEVLINK_RELOAD_LIMIT_NO_RESET = 1,\n\t__DEVLINK_RELOAD_LIMIT_MAX = 2,\n\tDEVLINK_RELOAD_LIMIT_MAX = 1,\n};\n\nenum devlink_resource_unit {\n\tDEVLINK_RESOURCE_UNIT_ENTRY = 0,\n};\n\nenum devlink_sb_pool_type {\n\tDEVLINK_SB_POOL_TYPE_INGRESS = 0,\n\tDEVLINK_SB_POOL_TYPE_EGRESS = 1,\n};\n\nenum devlink_sb_threshold_type {\n\tDEVLINK_SB_THRESHOLD_TYPE_STATIC = 0,\n\tDEVLINK_SB_THRESHOLD_TYPE_DYNAMIC = 1,\n};\n\nenum devlink_selftest_status {\n\tDEVLINK_SELFTEST_STATUS_SKIP = 0,\n\tDEVLINK_SELFTEST_STATUS_PASS = 1,\n\tDEVLINK_SELFTEST_STATUS_FAIL = 2,\n};\n\nenum devlink_trap_action {\n\tDEVLINK_TRAP_ACTION_DROP = 0,\n\tDEVLINK_TRAP_ACTION_TRAP = 1,\n\tDEVLINK_TRAP_ACTION_MIRROR = 2,\n};\n\nenum devlink_trap_generic_id {\n\tDEVLINK_TRAP_GENERIC_ID_SMAC_MC = 0,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_TAG_MISMATCH = 1,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_VLAN_FILTER = 2,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_STP_FILTER = 3,\n\tDEVLINK_TRAP_GENERIC_ID_EMPTY_TX_LIST = 4,\n\tDEVLINK_TRAP_GENERIC_ID_PORT_LOOPBACK_FILTER = 5,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_ROUTE = 6,\n\tDEVLINK_TRAP_GENERIC_ID_TTL_ERROR = 7,\n\tDEVLINK_TRAP_GENERIC_ID_TAIL_DROP = 8,\n\tDEVLINK_TRAP_GENERIC_ID_NON_IP_PACKET = 9,\n\tDEVLINK_TRAP_GENERIC_ID_UC_DIP_MC_DMAC = 10,\n\tDEVLINK_TRAP_GENERIC_ID_DIP_LB = 11,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_MC = 12,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_LB = 13,\n\tDEVLINK_TRAP_GENERIC_ID_CORRUPTED_IP_HDR = 14,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_SIP_BC = 15,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_RESERVED_SCOPE = 16,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_INTERFACE_LOCAL_SCOPE = 17,\n\tDEVLINK_TRAP_GENERIC_ID_MTU_ERROR = 18,\n\tDEVLINK_TRAP_GENERIC_ID_UNRESOLVED_NEIGH = 19,\n\tDEVLINK_TRAP_GENERIC_ID_RPF = 20,\n\tDEVLINK_TRAP_GENERIC_ID_REJECT_ROUTE = 21,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_LPM_UNICAST_MISS = 22,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_LPM_UNICAST_MISS = 23,\n\tDEVLINK_TRAP_GENERIC_ID_NON_ROUTABLE = 24,\n\tDEVLINK_TRAP_GENERIC_ID_DECAP_ERROR = 25,\n\tDEVLINK_TRAP_GENERIC_ID_OVERLAY_SMAC_MC = 26,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_FLOW_ACTION_DROP = 27,\n\tDEVLINK_TRAP_GENERIC_ID_EGRESS_FLOW_ACTION_DROP = 28,\n\tDEVLINK_TRAP_GENERIC_ID_STP = 29,\n\tDEVLINK_TRAP_GENERIC_ID_LACP = 30,\n\tDEVLINK_TRAP_GENERIC_ID_LLDP = 31,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_QUERY = 32,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V1_REPORT = 33,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_REPORT = 34,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V3_REPORT = 35,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_LEAVE = 36,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_QUERY = 37,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_REPORT = 38,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V2_REPORT = 39,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_DONE = 40,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_DHCP = 41,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DHCP = 42,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_REQUEST = 43,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_RESPONSE = 44,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_OVERLAY = 45,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_SOLICIT = 46,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_ADVERT = 47,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BFD = 48,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BFD = 49,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_OSPF = 50,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_OSPF = 51,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BGP = 52,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BGP = 53,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_VRRP = 54,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_VRRP = 55,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_PIM = 56,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_PIM = 57,\n\tDEVLINK_TRAP_GENERIC_ID_UC_LB = 58,\n\tDEVLINK_TRAP_GENERIC_ID_LOCAL_ROUTE = 59,\n\tDEVLINK_TRAP_GENERIC_ID_EXTERNAL_ROUTE = 60,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_UC_DIP_LINK_LOCAL_SCOPE = 61,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_NODES = 62,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_ROUTERS = 63,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_SOLICIT = 64,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ADVERT = 65,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_REDIRECT = 66,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_ROUTER_ALERT = 67,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ALERT = 68,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_EVENT = 69,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_GENERAL = 70,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_SAMPLE = 71,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_TRAP = 72,\n\tDEVLINK_TRAP_GENERIC_ID_EARLY_DROP = 73,\n\tDEVLINK_TRAP_GENERIC_ID_VXLAN_PARSING = 74,\n\tDEVLINK_TRAP_GENERIC_ID_LLC_SNAP_PARSING = 75,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_PARSING = 76,\n\tDEVLINK_TRAP_GENERIC_ID_PPPOE_PPP_PARSING = 77,\n\tDEVLINK_TRAP_GENERIC_ID_MPLS_PARSING = 78,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_PARSING = 79,\n\tDEVLINK_TRAP_GENERIC_ID_IP_1_PARSING = 80,\n\tDEVLINK_TRAP_GENERIC_ID_IP_N_PARSING = 81,\n\tDEVLINK_TRAP_GENERIC_ID_GRE_PARSING = 82,\n\tDEVLINK_TRAP_GENERIC_ID_UDP_PARSING = 83,\n\tDEVLINK_TRAP_GENERIC_ID_TCP_PARSING = 84,\n\tDEVLINK_TRAP_GENERIC_ID_IPSEC_PARSING = 85,\n\tDEVLINK_TRAP_GENERIC_ID_SCTP_PARSING = 86,\n\tDEVLINK_TRAP_GENERIC_ID_DCCP_PARSING = 87,\n\tDEVLINK_TRAP_GENERIC_ID_GTP_PARSING = 88,\n\tDEVLINK_TRAP_GENERIC_ID_ESP_PARSING = 89,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_NEXTHOP = 90,\n\tDEVLINK_TRAP_GENERIC_ID_DMAC_FILTER = 91,\n\tDEVLINK_TRAP_GENERIC_ID_EAPOL = 92,\n\tDEVLINK_TRAP_GENERIC_ID_LOCKED_PORT = 93,\n\t__DEVLINK_TRAP_GENERIC_ID_MAX = 94,\n\tDEVLINK_TRAP_GENERIC_ID_MAX = 93,\n};\n\nenum devlink_trap_group_generic_id {\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L2_DROPS = 0,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_DROPS = 1,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_EXCEPTIONS = 2,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BUFFER_DROPS = 3,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_TUNNEL_DROPS = 4,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_DROPS = 5,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_STP = 6,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LACP = 7,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LLDP = 8,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MC_SNOOPING = 9,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_DHCP = 10,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_NEIGH_DISCOVERY = 11,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BFD = 12,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_OSPF = 13,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BGP = 14,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_VRRP = 15,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PIM = 16,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_UC_LB = 17,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LOCAL_DELIVERY = 18,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EXTERNAL_DELIVERY = 19,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_IPV6 = 20,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_EVENT = 21,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_GENERAL = 22,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_SAMPLE = 23,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_TRAP = 24,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PARSER_ERROR_DROPS = 25,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EAPOL = 26,\n\t__DEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 27,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 26,\n};\n\nenum devlink_trap_type {\n\tDEVLINK_TRAP_TYPE_DROP = 0,\n\tDEVLINK_TRAP_TYPE_EXCEPTION = 1,\n\tDEVLINK_TRAP_TYPE_CONTROL = 2,\n};\n\nenum devlink_var_attr_type {\n\tDEVLINK_VAR_ATTR_TYPE_U8 = 1,\n\tDEVLINK_VAR_ATTR_TYPE_U16 = 2,\n\tDEVLINK_VAR_ATTR_TYPE_U32 = 3,\n\tDEVLINK_VAR_ATTR_TYPE_U64 = 4,\n\tDEVLINK_VAR_ATTR_TYPE_STRING = 5,\n\tDEVLINK_VAR_ATTR_TYPE_FLAG = 6,\n\tDEVLINK_VAR_ATTR_TYPE_NUL_STRING = 10,\n\tDEVLINK_VAR_ATTR_TYPE_BINARY = 11,\n\t__DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE = 128,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum dfll_ctrl_mode {\n\tDFLL_UNINITIALIZED = 0,\n\tDFLL_DISABLED = 1,\n\tDFLL_OPEN_LOOP = 2,\n\tDFLL_CLOSED_LOOP = 3,\n};\n\nenum dfll_tune_range {\n\tDFLL_TUNE_UNINITIALIZED = 0,\n\tDFLL_TUNE_LOW = 1,\n};\n\nenum die_val {\n\tDIE_UNUSED = 0,\n\tDIE_OOPS = 1,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum display_flags {\n\tDISPLAY_FLAGS_HSYNC_LOW = 1,\n\tDISPLAY_FLAGS_HSYNC_HIGH = 2,\n\tDISPLAY_FLAGS_VSYNC_LOW = 4,\n\tDISPLAY_FLAGS_VSYNC_HIGH = 8,\n\tDISPLAY_FLAGS_DE_LOW = 16,\n\tDISPLAY_FLAGS_DE_HIGH = 32,\n\tDISPLAY_FLAGS_PIXDATA_POSEDGE = 64,\n\tDISPLAY_FLAGS_PIXDATA_NEGEDGE = 128,\n\tDISPLAY_FLAGS_INTERLACED = 256,\n\tDISPLAY_FLAGS_DOUBLESCAN = 512,\n\tDISPLAY_FLAGS_DOUBLECLK = 1024,\n\tDISPLAY_FLAGS_SYNC_POSEDGE = 2048,\n\tDISPLAY_FLAGS_SYNC_NEGEDGE = 4096,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dll_reset_type {\n\tPM_DLL_RESET_ASSERT = 0,\n\tPM_DLL_RESET_RELEASE = 1,\n\tPM_DLL_RESET_PULSE = 2,\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n\tDMA_PREP_REPEAT = 256,\n\tDMA_PREP_LOAD_EOT = 512,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nenum dma_event_q {\n\tEVENTQ_0 = 0,\n\tEVENTQ_1 = 1,\n\tEVENTQ_2 = 2,\n\tEVENTQ_3 = 3,\n\tEVENTQ_DEFAULT = -1,\n};\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SEQNO64_BIT = 0,\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 1,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 2,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 3,\n\tDMA_FENCE_FLAG_USER_BITS = 4,\n};\n\nenum dma_irq_dir {\n\tDMA_DIR_RX = 1,\n\tDMA_DIR_TX = 2,\n\tDMA_DIR_RXTX = 3,\n};\n\nenum dma_irq_status {\n\ttx_hard_error = 1,\n\ttx_hard_error_bump_tc = 2,\n\thandle_rx = 4,\n\thandle_tx = 8,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nenum dma_resv_usage {\n\tDMA_RESV_USAGE_KERNEL = 0,\n\tDMA_RESV_USAGE_WRITE = 1,\n\tDMA_RESV_USAGE_READ = 2,\n\tDMA_RESV_USAGE_BOOKKEEP = 3,\n};\n\nenum dma_rx_status {\n\tDMA_RX_START = 0,\n\tDMA_RX_RUNNING = 1,\n\tDMA_RX_SHUTDOWN = 2,\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n\tDMA_SLAVE_BUSWIDTH_128_BYTES = 128,\n};\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n\tDMA_OUT_OF_ORDER = 4,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_COMPLETION_NO_ORDER = 13,\n\tDMA_REPEAT = 14,\n\tDMA_LOAD_EOT = 15,\n\tDMA_TX_TYPE_END = 16,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n\tDMAENGINE_ALIGN_128_BYTES = 7,\n\tDMAENGINE_ALIGN_256_BYTES = 8,\n};\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nenum dmamov_dst {\n\tSAR = 0,\n\tCCR = 1,\n\tDAR = 2,\n};\n\nenum dmi_device_type {\n\tDMI_DEV_TYPE_ANY = 0,\n\tDMI_DEV_TYPE_OTHER = 1,\n\tDMI_DEV_TYPE_UNKNOWN = 2,\n\tDMI_DEV_TYPE_VIDEO = 3,\n\tDMI_DEV_TYPE_SCSI = 4,\n\tDMI_DEV_TYPE_ETHERNET = 5,\n\tDMI_DEV_TYPE_TOKENRING = 6,\n\tDMI_DEV_TYPE_SOUND = 7,\n\tDMI_DEV_TYPE_PATA = 8,\n\tDMI_DEV_TYPE_SATA = 9,\n\tDMI_DEV_TYPE_SAS = 10,\n\tDMI_DEV_TYPE_IPMI = -1,\n\tDMI_DEV_TYPE_OEM_STRING = -2,\n\tDMI_DEV_TYPE_DEV_ONBOARD = -3,\n\tDMI_DEV_TYPE_DEV_SLOT = -4,\n};\n\nenum dmi_entry_type {\n\tDMI_ENTRY_BIOS = 0,\n\tDMI_ENTRY_SYSTEM = 1,\n\tDMI_ENTRY_BASEBOARD = 2,\n\tDMI_ENTRY_CHASSIS = 3,\n\tDMI_ENTRY_PROCESSOR = 4,\n\tDMI_ENTRY_MEM_CONTROLLER = 5,\n\tDMI_ENTRY_MEM_MODULE = 6,\n\tDMI_ENTRY_CACHE = 7,\n\tDMI_ENTRY_PORT_CONNECTOR = 8,\n\tDMI_ENTRY_SYSTEM_SLOT = 9,\n\tDMI_ENTRY_ONBOARD_DEVICE = 10,\n\tDMI_ENTRY_OEMSTRINGS = 11,\n\tDMI_ENTRY_SYSCONF = 12,\n\tDMI_ENTRY_BIOS_LANG = 13,\n\tDMI_ENTRY_GROUP_ASSOC = 14,\n\tDMI_ENTRY_SYSTEM_EVENT_LOG = 15,\n\tDMI_ENTRY_PHYS_MEM_ARRAY = 16,\n\tDMI_ENTRY_MEM_DEVICE = 17,\n\tDMI_ENTRY_32_MEM_ERROR = 18,\n\tDMI_ENTRY_MEM_ARRAY_MAPPED_ADDR = 19,\n\tDMI_ENTRY_MEM_DEV_MAPPED_ADDR = 20,\n\tDMI_ENTRY_BUILTIN_POINTING_DEV = 21,\n\tDMI_ENTRY_PORTABLE_BATTERY = 22,\n\tDMI_ENTRY_SYSTEM_RESET = 23,\n\tDMI_ENTRY_HW_SECURITY = 24,\n\tDMI_ENTRY_SYSTEM_POWER_CONTROLS = 25,\n\tDMI_ENTRY_VOLTAGE_PROBE = 26,\n\tDMI_ENTRY_COOLING_DEV = 27,\n\tDMI_ENTRY_TEMP_PROBE = 28,\n\tDMI_ENTRY_ELECTRICAL_CURRENT_PROBE = 29,\n\tDMI_ENTRY_OOB_REMOTE_ACCESS = 30,\n\tDMI_ENTRY_BIS_ENTRY = 31,\n\tDMI_ENTRY_SYSTEM_BOOT = 32,\n\tDMI_ENTRY_MGMT_DEV = 33,\n\tDMI_ENTRY_MGMT_DEV_COMPONENT = 34,\n\tDMI_ENTRY_MGMT_DEV_THRES = 35,\n\tDMI_ENTRY_MEM_CHANNEL = 36,\n\tDMI_ENTRY_IPMI_DEV = 37,\n\tDMI_ENTRY_SYS_POWER_SUPPLY = 38,\n\tDMI_ENTRY_ADDITIONAL = 39,\n\tDMI_ENTRY_ONBOARD_DEV_EXT = 40,\n\tDMI_ENTRY_MGMT_CONTROLLER_HOST = 41,\n\tDMI_ENTRY_INACTIVE = 126,\n\tDMI_ENTRY_END_OF_TABLE = 127,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dp_colorimetry {\n\tDP_COLORIMETRY_DEFAULT = 0,\n\tDP_COLORIMETRY_RGB_WIDE_FIXED = 1,\n\tDP_COLORIMETRY_BT709_YCC = 1,\n\tDP_COLORIMETRY_RGB_WIDE_FLOAT = 2,\n\tDP_COLORIMETRY_XVYCC_601 = 2,\n\tDP_COLORIMETRY_OPRGB = 3,\n\tDP_COLORIMETRY_XVYCC_709 = 3,\n\tDP_COLORIMETRY_DCI_P3_RGB = 4,\n\tDP_COLORIMETRY_SYCC_601 = 4,\n\tDP_COLORIMETRY_RGB_CUSTOM = 5,\n\tDP_COLORIMETRY_OPYCC_601 = 5,\n\tDP_COLORIMETRY_BT2020_RGB = 6,\n\tDP_COLORIMETRY_BT2020_CYCC = 6,\n\tDP_COLORIMETRY_BT2020_YCC = 7,\n};\n\nenum dp_content_type {\n\tDP_CONTENT_TYPE_NOT_DEFINED = 0,\n\tDP_CONTENT_TYPE_GRAPHICS = 1,\n\tDP_CONTENT_TYPE_PHOTO = 2,\n\tDP_CONTENT_TYPE_VIDEO = 3,\n\tDP_CONTENT_TYPE_GAME = 4,\n};\n\nenum dp_dynamic_range {\n\tDP_DYNAMIC_RANGE_VESA = 0,\n\tDP_DYNAMIC_RANGE_CTA = 1,\n};\n\nenum dp_pixelformat {\n\tDP_PIXELFORMAT_RGB = 0,\n\tDP_PIXELFORMAT_YUV444 = 1,\n\tDP_PIXELFORMAT_YUV422 = 2,\n\tDP_PIXELFORMAT_YUV420 = 3,\n\tDP_PIXELFORMAT_Y_ONLY = 4,\n\tDP_PIXELFORMAT_RAW = 5,\n\tDP_PIXELFORMAT_RESERVED = 6,\n};\n\nenum dpfe_commands {\n\tDPFE_CMD_GET_INFO = 0,\n\tDPFE_CMD_GET_REFRESH = 1,\n\tDPFE_CMD_GET_VENDOR = 2,\n\tDPFE_CMD_MAX = 3,\n};\n\nenum dpfe_msg_fields {\n\tMSG_HEADER = 0,\n\tMSG_COMMAND = 1,\n\tMSG_ARG_COUNT = 2,\n\tMSG_ARG0 = 3,\n\tMSG_FIELD_MAX = 16,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum dpot_devid {\n\tAD5258_ID = 6817152,\n\tAD5259_ID = 6817281,\n\tAD5251_ID = 7088514,\n\tAD5252_ID = 7088643,\n\tAD5253_ID = 7093636,\n\tAD5254_ID = 7093765,\n\tAD5255_ID = 7085638,\n\tAD5160_ID = 58721799,\n\tAD5161_ID = 58721800,\n\tAD5162_ID = 92278281,\n\tAD5165_ID = 58721802,\n\tAD5200_ID = 58721803,\n\tAD5201_ID = 58721612,\n\tAD5203_ID = 58736013,\n\tAD5204_ID = 92290574,\n\tAD5206_ID = 92339727,\n\tAD5207_ID = 92278288,\n\tAD5231_ID = 139200145,\n\tAD5232_ID = 72093202,\n\tAD5233_ID = 72105363,\n\tAD5235_ID = 139202196,\n\tAD5260_ID = 58721813,\n\tAD5262_ID = 92278294,\n\tAD5263_ID = 92290583,\n\tAD5290_ID = 58721816,\n\tAD5291_ID = 72353305,\n\tAD5292_ID = 72353434,\n\tAD5293_ID = 71304859,\n\tAD7376_ID = 58721756,\n\tAD8400_ID = 92276253,\n\tAD8402_ID = 92278302,\n\tAD8403_ID = 92282399,\n\tADN2850_ID = 139202208,\n\tAD5241_ID = 4195873,\n\tAD5242_ID = 4197922,\n\tAD5243_ID = 4197923,\n\tAD5245_ID = 4195876,\n\tAD5246_ID = 4195813,\n\tAD5247_ID = 4195814,\n\tAD5248_ID = 4197927,\n\tAD5280_ID = 4195880,\n\tAD5282_ID = 4197929,\n\tADN2860_ID = 7085674,\n\tAD5273_ID = 5244331,\n\tAD5171_ID = 5244332,\n\tAD5170_ID = 5244461,\n\tAD5172_ID = 5246510,\n\tAD5173_ID = 5246511,\n\tAD5270_ID = 72353456,\n\tAD5271_ID = 72353329,\n\tAD5272_ID = 5244594,\n\tAD5274_ID = 5244467,\n};\n\nenum drive_strength_bit {\n\tDRIVE_STRENGTH_BIT_DEF = 0,\n\tDRIVE_STRENGTH_BIT_LOW = 1,\n\tDRIVE_STRENGTH_BIT_MED = 2,\n\tDRIVE_STRENGTH_BIT_HI = 3,\n};\n\nenum drm_bridge_attach_flags {\n\tDRM_BRIDGE_ATTACH_NO_CONNECTOR = 1,\n};\n\nenum drm_bridge_ops {\n\tDRM_BRIDGE_OP_DETECT = 1,\n\tDRM_BRIDGE_OP_EDID = 2,\n\tDRM_BRIDGE_OP_HPD = 4,\n\tDRM_BRIDGE_OP_MODES = 8,\n\tDRM_BRIDGE_OP_HDMI = 16,\n\tDRM_BRIDGE_OP_HDMI_AUDIO = 32,\n\tDRM_BRIDGE_OP_DP_AUDIO = 64,\n\tDRM_BRIDGE_OP_HDMI_CEC_NOTIFIER = 128,\n\tDRM_BRIDGE_OP_HDMI_CEC_ADAPTER = 256,\n\tDRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME = 512,\n\tDRM_BRIDGE_OP_HDMI_SPD_INFOFRAME = 1024,\n};\n\nenum drm_bus_flags {\n\tDRM_BUS_FLAG_DE_LOW = 1,\n\tDRM_BUS_FLAG_DE_HIGH = 2,\n\tDRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = 4,\n\tDRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = 8,\n\tDRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = 8,\n\tDRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE = 4,\n\tDRM_BUS_FLAG_DATA_MSB_TO_LSB = 16,\n\tDRM_BUS_FLAG_DATA_LSB_TO_MSB = 32,\n\tDRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = 64,\n\tDRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = 128,\n\tDRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = 128,\n\tDRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = 64,\n\tDRM_BUS_FLAG_SHARP_SIGNALS = 256,\n};\n\nenum drm_color_encoding {\n\tDRM_COLOR_YCBCR_BT601 = 0,\n\tDRM_COLOR_YCBCR_BT709 = 1,\n\tDRM_COLOR_YCBCR_BT2020 = 2,\n\tDRM_COLOR_ENCODING_MAX = 3,\n};\n\nenum drm_color_lut_tests {\n\tDRM_COLOR_LUT_EQUAL_CHANNELS = 1,\n\tDRM_COLOR_LUT_NON_DECREASING = 2,\n};\n\nenum drm_color_range {\n\tDRM_COLOR_YCBCR_LIMITED_RANGE = 0,\n\tDRM_COLOR_YCBCR_FULL_RANGE = 1,\n\tDRM_COLOR_RANGE_MAX = 2,\n};\n\nenum drm_colorop_curve_1d_type {\n\tDRM_COLOROP_1D_CURVE_SRGB_EOTF = 0,\n\tDRM_COLOROP_1D_CURVE_SRGB_INV_EOTF = 1,\n\tDRM_COLOROP_1D_CURVE_PQ_125_EOTF = 2,\n\tDRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF = 3,\n\tDRM_COLOROP_1D_CURVE_BT2020_INV_OETF = 4,\n\tDRM_COLOROP_1D_CURVE_BT2020_OETF = 5,\n\tDRM_COLOROP_1D_CURVE_GAMMA22 = 6,\n\tDRM_COLOROP_1D_CURVE_GAMMA22_INV = 7,\n\tDRM_COLOROP_1D_CURVE_COUNT = 8,\n};\n\nenum drm_colorop_lut1d_interpolation_type {\n\tDRM_COLOROP_LUT1D_INTERPOLATION_LINEAR = 0,\n};\n\nenum drm_colorop_lut3d_interpolation_type {\n\tDRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL = 0,\n};\n\nenum drm_colorop_type {\n\tDRM_COLOROP_1D_CURVE = 0,\n\tDRM_COLOROP_1D_LUT = 1,\n\tDRM_COLOROP_CTM_3X4 = 2,\n\tDRM_COLOROP_MULTIPLIER = 3,\n\tDRM_COLOROP_3D_LUT = 4,\n};\n\nenum drm_colorspace {\n\tDRM_MODE_COLORIMETRY_DEFAULT = 0,\n\tDRM_MODE_COLORIMETRY_NO_DATA = 0,\n\tDRM_MODE_COLORIMETRY_SMPTE_170M_YCC = 1,\n\tDRM_MODE_COLORIMETRY_BT709_YCC = 2,\n\tDRM_MODE_COLORIMETRY_XVYCC_601 = 3,\n\tDRM_MODE_COLORIMETRY_XVYCC_709 = 4,\n\tDRM_MODE_COLORIMETRY_SYCC_601 = 5,\n\tDRM_MODE_COLORIMETRY_OPYCC_601 = 6,\n\tDRM_MODE_COLORIMETRY_OPRGB = 7,\n\tDRM_MODE_COLORIMETRY_BT2020_CYCC = 8,\n\tDRM_MODE_COLORIMETRY_BT2020_RGB = 9,\n\tDRM_MODE_COLORIMETRY_BT2020_YCC = 10,\n\tDRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 = 11,\n\tDRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER = 12,\n\tDRM_MODE_COLORIMETRY_RGB_WIDE_FIXED = 13,\n\tDRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT = 14,\n\tDRM_MODE_COLORIMETRY_BT601_YCC = 15,\n\tDRM_MODE_COLORIMETRY_COUNT = 16,\n};\n\nenum drm_connector_force {\n\tDRM_FORCE_UNSPECIFIED = 0,\n\tDRM_FORCE_OFF = 1,\n\tDRM_FORCE_ON = 2,\n\tDRM_FORCE_ON_DIGITAL = 3,\n};\n\nenum drm_connector_registration_state {\n\tDRM_CONNECTOR_INITIALIZING = 0,\n\tDRM_CONNECTOR_REGISTERED = 1,\n\tDRM_CONNECTOR_UNREGISTERED = 2,\n};\n\nenum drm_connector_status {\n\tconnector_status_connected = 1,\n\tconnector_status_disconnected = 2,\n\tconnector_status_unknown = 3,\n};\n\nenum drm_connector_tv_mode {\n\tDRM_MODE_TV_MODE_NTSC = 0,\n\tDRM_MODE_TV_MODE_NTSC_443 = 1,\n\tDRM_MODE_TV_MODE_NTSC_J = 2,\n\tDRM_MODE_TV_MODE_PAL = 3,\n\tDRM_MODE_TV_MODE_PAL_M = 4,\n\tDRM_MODE_TV_MODE_PAL_N = 5,\n\tDRM_MODE_TV_MODE_SECAM = 6,\n\tDRM_MODE_TV_MODE_MONOCHROME = 7,\n\tDRM_MODE_TV_MODE_MAX = 8,\n};\n\nenum drm_debug_category {\n\tDRM_UT_CORE = 0,\n\tDRM_UT_DRIVER = 1,\n\tDRM_UT_KMS = 2,\n\tDRM_UT_PRIME = 3,\n\tDRM_UT_ATOMIC = 4,\n\tDRM_UT_VBL = 5,\n\tDRM_UT_STATE = 6,\n\tDRM_UT_LEASE = 7,\n\tDRM_UT_DP = 8,\n\tDRM_UT_DRMRES = 9,\n};\n\nenum drm_dp_dual_mode_type {\n\tDRM_DP_DUAL_MODE_NONE = 0,\n\tDRM_DP_DUAL_MODE_UNKNOWN = 1,\n\tDRM_DP_DUAL_MODE_TYPE1_DVI = 2,\n\tDRM_DP_DUAL_MODE_TYPE1_HDMI = 3,\n\tDRM_DP_DUAL_MODE_TYPE2_DVI = 4,\n\tDRM_DP_DUAL_MODE_TYPE2_HDMI = 5,\n\tDRM_DP_DUAL_MODE_LSPCON = 6,\n};\n\nenum drm_dp_mst_mode {\n\tDRM_DP_SST = 0,\n\tDRM_DP_MST = 1,\n\tDRM_DP_SST_SIDEBAND_MSG = 2,\n};\n\nenum drm_dp_mst_payload_allocation {\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_NONE = 0,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_LOCAL = 1,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_DFP = 2,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_REMOTE = 3,\n};\n\nenum drm_dp_phy {\n\tDP_PHY_DPRX = 0,\n\tDP_PHY_LTTPR1 = 1,\n\tDP_PHY_LTTPR2 = 2,\n\tDP_PHY_LTTPR3 = 3,\n\tDP_PHY_LTTPR4 = 4,\n\tDP_PHY_LTTPR5 = 5,\n\tDP_PHY_LTTPR6 = 6,\n\tDP_PHY_LTTPR7 = 7,\n\tDP_PHY_LTTPR8 = 8,\n\tDP_MAX_LTTPR_COUNT = 8,\n};\n\nenum drm_dp_quirk {\n\tDP_DPCD_QUIRK_CONSTANT_N = 0,\n\tDP_DPCD_QUIRK_NO_PSR = 1,\n\tDP_DPCD_QUIRK_NO_SINK_COUNT = 2,\n\tDP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD = 3,\n\tDP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS = 4,\n\tDP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC = 5,\n\tDP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT = 6,\n};\n\nenum drm_driver_feature {\n\tDRIVER_GEM = 1,\n\tDRIVER_MODESET = 2,\n\tDRIVER_RENDER = 8,\n\tDRIVER_ATOMIC = 16,\n\tDRIVER_SYNCOBJ = 32,\n\tDRIVER_SYNCOBJ_TIMELINE = 64,\n\tDRIVER_COMPUTE_ACCEL = 128,\n\tDRIVER_GEM_GPUVA = 256,\n\tDRIVER_CURSOR_HOTSPOT = 512,\n\tDRIVER_USE_AGP = 33554432,\n\tDRIVER_LEGACY = 67108864,\n\tDRIVER_PCI_DMA = 134217728,\n\tDRIVER_SG = 268435456,\n\tDRIVER_HAVE_DMA = 536870912,\n\tDRIVER_HAVE_IRQ = 1073741824,\n};\n\nenum drm_dsc_params_type {\n\tDRM_DSC_1_2_444 = 0,\n\tDRM_DSC_1_1_PRE_SCR = 1,\n\tDRM_DSC_1_2_422 = 2,\n\tDRM_DSC_1_2_420 = 3,\n};\n\nenum drm_edid_internal_quirk {\n\tEDID_QUIRK_PREFER_LARGE_60 = 1,\n\tEDID_QUIRK_135_CLOCK_TOO_HIGH = 2,\n\tEDID_QUIRK_PREFER_LARGE_75 = 3,\n\tEDID_QUIRK_DETAILED_IN_CM = 4,\n\tEDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 5,\n\tEDID_QUIRK_DETAILED_SYNC_PP = 6,\n\tEDID_QUIRK_FORCE_REDUCED_BLANKING = 7,\n\tEDID_QUIRK_FORCE_8BPC = 8,\n\tEDID_QUIRK_FORCE_12BPC = 9,\n\tEDID_QUIRK_FORCE_6BPC = 10,\n\tEDID_QUIRK_FORCE_10BPC = 11,\n\tEDID_QUIRK_NON_DESKTOP = 12,\n\tEDID_QUIRK_CAP_DSC_15BPP = 13,\n};\n\nenum drm_edid_quirk {\n\tDRM_EDID_QUIRK_DP_DPCD_PROBE = 0,\n\tDRM_EDID_QUIRK_NUM = 1,\n};\n\nenum drm_gem_object_status {\n\tDRM_GEM_OBJECT_RESIDENT = 1,\n\tDRM_GEM_OBJECT_PURGEABLE = 2,\n\tDRM_GEM_OBJECT_ACTIVE = 4,\n};\n\nenum drm_gpuva_flags {\n\tDRM_GPUVA_INVALIDATED = 1,\n\tDRM_GPUVA_SPARSE = 2,\n\tDRM_GPUVA_USERBITS = 4,\n};\n\nenum drm_gpuva_op_type {\n\tDRM_GPUVA_OP_MAP = 0,\n\tDRM_GPUVA_OP_REMAP = 1,\n\tDRM_GPUVA_OP_UNMAP = 2,\n\tDRM_GPUVA_OP_PREFETCH = 3,\n\tDRM_GPUVA_OP_DRIVER = 4,\n};\n\nenum drm_gpuvm_flags {\n\tDRM_GPUVM_RESV_PROTECTED = 1,\n\tDRM_GPUVM_IMMEDIATE_MODE = 2,\n\tDRM_GPUVM_USERBITS = 4,\n};\n\nenum drm_hdmi_broadcast_rgb {\n\tDRM_HDMI_BROADCAST_RGB_AUTO = 0,\n\tDRM_HDMI_BROADCAST_RGB_FULL = 1,\n\tDRM_HDMI_BROADCAST_RGB_LIMITED = 2,\n};\n\nenum drm_ioctl_flags {\n\tDRM_AUTH = 1,\n\tDRM_MASTER = 2,\n\tDRM_ROOT_ONLY = 4,\n\tDRM_RENDER_ALLOW = 32,\n};\n\nenum drm_link_status {\n\tDRM_LINK_STATUS_GOOD = 0,\n\tDRM_LINK_STATUS_BAD = 1,\n};\n\nenum drm_lspcon_mode {\n\tDRM_LSPCON_MODE_INVALID = 0,\n\tDRM_LSPCON_MODE_LS = 1,\n\tDRM_LSPCON_MODE_PCON = 2,\n};\n\nenum drm_lvds_dual_link_pixels {\n\tDRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 0,\n\tDRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 1,\n};\n\nenum drm_minor_type {\n\tDRM_MINOR_PRIMARY = 0,\n\tDRM_MINOR_CONTROL = 1,\n\tDRM_MINOR_RENDER = 2,\n\tDRM_MINOR_ACCEL = 32,\n};\n\nenum drm_mm_insert_mode {\n\tDRM_MM_INSERT_BEST = 0,\n\tDRM_MM_INSERT_LOW = 1,\n\tDRM_MM_INSERT_HIGH = 2,\n\tDRM_MM_INSERT_EVICT = 3,\n\tDRM_MM_INSERT_ONCE = 2147483648,\n\tDRM_MM_INSERT_HIGHEST = 2147483650,\n\tDRM_MM_INSERT_LOWEST = 2147483649,\n};\n\nenum drm_mode_analog {\n\tDRM_MODE_ANALOG_NTSC = 0,\n\tDRM_MODE_ANALOG_PAL = 1,\n};\n\nenum drm_mode_status {\n\tMODE_OK = 0,\n\tMODE_HSYNC = 1,\n\tMODE_VSYNC = 2,\n\tMODE_H_ILLEGAL = 3,\n\tMODE_V_ILLEGAL = 4,\n\tMODE_BAD_WIDTH = 5,\n\tMODE_NOMODE = 6,\n\tMODE_NO_INTERLACE = 7,\n\tMODE_NO_DBLESCAN = 8,\n\tMODE_NO_VSCAN = 9,\n\tMODE_MEM = 10,\n\tMODE_VIRTUAL_X = 11,\n\tMODE_VIRTUAL_Y = 12,\n\tMODE_MEM_VIRT = 13,\n\tMODE_NOCLOCK = 14,\n\tMODE_CLOCK_HIGH = 15,\n\tMODE_CLOCK_LOW = 16,\n\tMODE_CLOCK_RANGE = 17,\n\tMODE_BAD_HVALUE = 18,\n\tMODE_BAD_VVALUE = 19,\n\tMODE_BAD_VSCAN = 20,\n\tMODE_HSYNC_NARROW = 21,\n\tMODE_HSYNC_WIDE = 22,\n\tMODE_HBLANK_NARROW = 23,\n\tMODE_HBLANK_WIDE = 24,\n\tMODE_VSYNC_NARROW = 25,\n\tMODE_VSYNC_WIDE = 26,\n\tMODE_VBLANK_NARROW = 27,\n\tMODE_VBLANK_WIDE = 28,\n\tMODE_PANEL = 29,\n\tMODE_INTERLACE_WIDTH = 30,\n\tMODE_ONE_WIDTH = 31,\n\tMODE_ONE_HEIGHT = 32,\n\tMODE_ONE_SIZE = 33,\n\tMODE_NO_REDUCED = 34,\n\tMODE_NO_STEREO = 35,\n\tMODE_NO_420 = 36,\n\tMODE_STALE = -3,\n\tMODE_BAD = -2,\n\tMODE_ERROR = -1,\n};\n\nenum drm_mode_subconnector {\n\tDRM_MODE_SUBCONNECTOR_Automatic = 0,\n\tDRM_MODE_SUBCONNECTOR_Unknown = 0,\n\tDRM_MODE_SUBCONNECTOR_VGA = 1,\n\tDRM_MODE_SUBCONNECTOR_DVID = 3,\n\tDRM_MODE_SUBCONNECTOR_DVIA = 4,\n\tDRM_MODE_SUBCONNECTOR_Composite = 5,\n\tDRM_MODE_SUBCONNECTOR_SVIDEO = 6,\n\tDRM_MODE_SUBCONNECTOR_Component = 8,\n\tDRM_MODE_SUBCONNECTOR_SCART = 9,\n\tDRM_MODE_SUBCONNECTOR_DisplayPort = 10,\n\tDRM_MODE_SUBCONNECTOR_HDMIA = 11,\n\tDRM_MODE_SUBCONNECTOR_Native = 15,\n\tDRM_MODE_SUBCONNECTOR_Wireless = 18,\n};\n\nenum drm_of_lvds_pixels {\n\tDRM_OF_LVDS_EVEN = 1,\n\tDRM_OF_LVDS_ODD = 2,\n};\n\nenum drm_panel_orientation {\n\tDRM_MODE_PANEL_ORIENTATION_UNKNOWN = -1,\n\tDRM_MODE_PANEL_ORIENTATION_NORMAL = 0,\n\tDRM_MODE_PANEL_ORIENTATION_BOTTOM_UP = 1,\n\tDRM_MODE_PANEL_ORIENTATION_LEFT_UP = 2,\n\tDRM_MODE_PANEL_ORIENTATION_RIGHT_UP = 3,\n};\n\nenum drm_plane_type {\n\tDRM_PLANE_TYPE_OVERLAY = 0,\n\tDRM_PLANE_TYPE_PRIMARY = 1,\n\tDRM_PLANE_TYPE_CURSOR = 2,\n};\n\nenum drm_privacy_screen_status {\n\tPRIVACY_SCREEN_DISABLED = 0,\n\tPRIVACY_SCREEN_ENABLED = 1,\n\tPRIVACY_SCREEN_DISABLED_LOCKED = 2,\n\tPRIVACY_SCREEN_ENABLED_LOCKED = 3,\n};\n\nenum drm_scaling_filter {\n\tDRM_SCALING_FILTER_DEFAULT = 0,\n\tDRM_SCALING_FILTER_NEAREST_NEIGHBOR = 1,\n};\n\nenum drm_stat_type {\n\t_DRM_STAT_LOCK = 0,\n\t_DRM_STAT_OPENS = 1,\n\t_DRM_STAT_CLOSES = 2,\n\t_DRM_STAT_IOCTLS = 3,\n\t_DRM_STAT_LOCKS = 4,\n\t_DRM_STAT_UNLOCKS = 5,\n\t_DRM_STAT_VALUE = 6,\n\t_DRM_STAT_BYTE = 7,\n\t_DRM_STAT_COUNT = 8,\n\t_DRM_STAT_IRQ = 9,\n\t_DRM_STAT_PRIMARY = 10,\n\t_DRM_STAT_SECONDARY = 11,\n\t_DRM_STAT_DMA = 12,\n\t_DRM_STAT_SPECIAL = 13,\n\t_DRM_STAT_MISSED = 14,\n};\n\nenum drm_vblank_seq_type {\n\t_DRM_VBLANK_ABSOLUTE = 0,\n\t_DRM_VBLANK_RELATIVE = 1,\n\t_DRM_VBLANK_HIGH_CRTC_MASK = 62,\n\t_DRM_VBLANK_EVENT = 67108864,\n\t_DRM_VBLANK_FLIP = 134217728,\n\t_DRM_VBLANK_NEXTONMISS = 268435456,\n\t_DRM_VBLANK_SECONDARY = 536870912,\n\t_DRM_VBLANK_SIGNAL = 1073741824,\n};\n\nenum drvtype {\n\tLEGACY = 0,\n\tSYSCON = 1,\n};\n\nenum ds_type {\n\tunknown_ds_type = 0,\n\tds_1307 = 1,\n\tds_1308 = 2,\n\tds_1337 = 3,\n\tds_1338 = 4,\n\tds_1339 = 5,\n\tds_1340 = 6,\n\tds_1341 = 7,\n\tds_1388 = 8,\n\tds_3231 = 9,\n\tm41t0 = 10,\n\tm41t00 = 11,\n\tm41t11 = 12,\n\tmcp794xx = 13,\n\trx_8025 = 14,\n\trx_8130 = 15,\n\tlast_ds_type = 16,\n};\n\nenum dsa_db_type {\n\tDSA_DB_PORT = 0,\n\tDSA_DB_LAG = 1,\n\tDSA_DB_BRIDGE = 2,\n};\n\nenum dsa_tag_protocol {\n\tDSA_TAG_PROTO_NONE = 0,\n\tDSA_TAG_PROTO_BRCM = 1,\n\tDSA_TAG_PROTO_BRCM_LEGACY = 22,\n\tDSA_TAG_PROTO_BRCM_LEGACY_FCS = 29,\n\tDSA_TAG_PROTO_BRCM_PREPEND = 2,\n\tDSA_TAG_PROTO_DSA = 3,\n\tDSA_TAG_PROTO_EDSA = 4,\n\tDSA_TAG_PROTO_GSWIP = 5,\n\tDSA_TAG_PROTO_KSZ9477 = 6,\n\tDSA_TAG_PROTO_KSZ9893 = 7,\n\tDSA_TAG_PROTO_LAN9303 = 8,\n\tDSA_TAG_PROTO_MTK = 9,\n\tDSA_TAG_PROTO_QCA = 10,\n\tDSA_TAG_PROTO_TRAILER = 11,\n\tDSA_TAG_PROTO_8021Q = 12,\n\tDSA_TAG_PROTO_SJA1105 = 13,\n\tDSA_TAG_PROTO_KSZ8795 = 14,\n\tDSA_TAG_PROTO_OCELOT = 15,\n\tDSA_TAG_PROTO_AR9331 = 16,\n\tDSA_TAG_PROTO_RTL4_A = 17,\n\tDSA_TAG_PROTO_HELLCREEK = 18,\n\tDSA_TAG_PROTO_XRS700X = 19,\n\tDSA_TAG_PROTO_OCELOT_8021Q = 20,\n\tDSA_TAG_PROTO_SEVILLE = 21,\n\tDSA_TAG_PROTO_SJA1110 = 23,\n\tDSA_TAG_PROTO_RTL8_4 = 24,\n\tDSA_TAG_PROTO_RTL8_4T = 25,\n\tDSA_TAG_PROTO_RZN1_A5PSW = 26,\n\tDSA_TAG_PROTO_LAN937X = 27,\n\tDSA_TAG_PROTO_VSC73XX_8021Q = 28,\n\tDSA_TAG_PROTO_YT921X = 30,\n\tDSA_TAG_PROTO_MXL_GSW1XX = 31,\n\tDSA_TAG_PROTO_MXL862 = 32,\n};\n\nenum dw_dma_fc {\n\tDW_DMA_FC_D_M2M = 0,\n\tDW_DMA_FC_D_M2P = 1,\n\tDW_DMA_FC_D_P2M = 2,\n\tDW_DMA_FC_D_P2P = 3,\n\tDW_DMA_FC_P_P2M = 4,\n\tDW_DMA_FC_SP_P2P = 5,\n\tDW_DMA_FC_P_M2P = 6,\n\tDW_DMA_FC_DP_P2P = 7,\n};\n\nenum dw_dmac_flags {\n\tDW_DMA_IS_CYCLIC = 0,\n\tDW_DMA_IS_SOFT_LLP = 1,\n\tDW_DMA_IS_PAUSED = 2,\n\tDW_DMA_IS_INITIALIZED = 3,\n};\n\nenum dw_edma_chip_flags {\n\tDW_EDMA_CHIP_LOCAL = 1,\n};\n\nenum dw_edma_map_format {\n\tEDMA_MF_EDMA_LEGACY = 0,\n\tEDMA_MF_EDMA_UNROLL = 1,\n\tEDMA_MF_HDMA_COMPAT = 5,\n\tEDMA_MF_HDMA_NATIVE = 7,\n};\n\nenum dw_mci_cookie {\n\tCOOKIE_UNMAPPED = 0,\n\tCOOKIE_PRE_MAPPED = 1,\n\tCOOKIE_MAPPED = 2,\n};\n\nenum dw_mci_exynos_type {\n\tDW_MCI_TYPE_EXYNOS4210 = 0,\n\tDW_MCI_TYPE_EXYNOS4412 = 1,\n\tDW_MCI_TYPE_EXYNOS5250 = 2,\n\tDW_MCI_TYPE_EXYNOS5420 = 3,\n\tDW_MCI_TYPE_EXYNOS5420_SMU = 4,\n\tDW_MCI_TYPE_EXYNOS7 = 5,\n\tDW_MCI_TYPE_EXYNOS7_SMU = 6,\n\tDW_MCI_TYPE_EXYNOS7870 = 7,\n\tDW_MCI_TYPE_EXYNOS7870_SMU = 8,\n\tDW_MCI_TYPE_ARTPEC8 = 9,\n};\n\nenum dw_mci_state {\n\tSTATE_IDLE___3 = 0,\n\tSTATE_SENDING_CMD___2 = 1,\n\tSTATE_SENDING_DATA = 2,\n\tSTATE_DATA_BUSY = 3,\n\tSTATE_SENDING_STOP___2 = 4,\n\tSTATE_DATA_ERROR = 5,\n\tSTATE_SENDING_CMD11 = 6,\n\tSTATE_WAITING_CMD11_DONE = 7,\n};\n\nenum dw_pcie_app_clk {\n\tDW_PCIE_DBI_CLK = 0,\n\tDW_PCIE_MSTR_CLK = 1,\n\tDW_PCIE_SLV_CLK = 2,\n\tDW_PCIE_NUM_APP_CLKS = 3,\n};\n\nenum dw_pcie_app_rst {\n\tDW_PCIE_DBI_RST = 0,\n\tDW_PCIE_MSTR_RST = 1,\n\tDW_PCIE_SLV_RST = 2,\n\tDW_PCIE_NUM_APP_RSTS = 3,\n};\n\nenum dw_pcie_core_clk {\n\tDW_PCIE_PIPE_CLK = 0,\n\tDW_PCIE_CORE_CLK = 1,\n\tDW_PCIE_AUX_CLK = 2,\n\tDW_PCIE_REF_CLK = 3,\n\tDW_PCIE_NUM_CORE_CLKS = 4,\n};\n\nenum dw_pcie_core_rst {\n\tDW_PCIE_NON_STICKY_RST = 0,\n\tDW_PCIE_STICKY_RST = 1,\n\tDW_PCIE_CORE_RST = 2,\n\tDW_PCIE_PIPE_RST = 3,\n\tDW_PCIE_PHY_RST = 4,\n\tDW_PCIE_HOT_RST = 5,\n\tDW_PCIE_PWR_RST = 6,\n\tDW_PCIE_NUM_CORE_RSTS = 7,\n};\n\nenum dw_pcie_device_mode {\n\tDW_PCIE_UNKNOWN_TYPE = 0,\n\tDW_PCIE_EP_TYPE = 1,\n\tDW_PCIE_LEG_EP_TYPE = 2,\n\tDW_PCIE_RC_TYPE = 3,\n};\n\nenum dw_pcie_ltssm {\n\tDW_PCIE_LTSSM_DETECT_QUIET = 0,\n\tDW_PCIE_LTSSM_DETECT_ACT = 1,\n\tDW_PCIE_LTSSM_POLL_ACTIVE = 2,\n\tDW_PCIE_LTSSM_POLL_COMPLIANCE = 3,\n\tDW_PCIE_LTSSM_POLL_CONFIG = 4,\n\tDW_PCIE_LTSSM_PRE_DETECT_QUIET = 5,\n\tDW_PCIE_LTSSM_DETECT_WAIT = 6,\n\tDW_PCIE_LTSSM_CFG_LINKWD_START = 7,\n\tDW_PCIE_LTSSM_CFG_LINKWD_ACEPT = 8,\n\tDW_PCIE_LTSSM_CFG_LANENUM_WAI = 9,\n\tDW_PCIE_LTSSM_CFG_LANENUM_ACEPT = 10,\n\tDW_PCIE_LTSSM_CFG_COMPLETE = 11,\n\tDW_PCIE_LTSSM_CFG_IDLE = 12,\n\tDW_PCIE_LTSSM_RCVRY_LOCK = 13,\n\tDW_PCIE_LTSSM_RCVRY_SPEED = 14,\n\tDW_PCIE_LTSSM_RCVRY_RCVRCFG = 15,\n\tDW_PCIE_LTSSM_RCVRY_IDLE = 16,\n\tDW_PCIE_LTSSM_L0 = 17,\n\tDW_PCIE_LTSSM_L0S = 18,\n\tDW_PCIE_LTSSM_L123_SEND_EIDLE = 19,\n\tDW_PCIE_LTSSM_L1_IDLE = 20,\n\tDW_PCIE_LTSSM_L2_IDLE = 21,\n\tDW_PCIE_LTSSM_L2_WAKE = 22,\n\tDW_PCIE_LTSSM_DISABLED_ENTRY = 23,\n\tDW_PCIE_LTSSM_DISABLED_IDLE = 24,\n\tDW_PCIE_LTSSM_DISABLED = 25,\n\tDW_PCIE_LTSSM_LPBK_ENTRY = 26,\n\tDW_PCIE_LTSSM_LPBK_ACTIVE = 27,\n\tDW_PCIE_LTSSM_LPBK_EXIT = 28,\n\tDW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT = 29,\n\tDW_PCIE_LTSSM_HOT_RESET_ENTRY = 30,\n\tDW_PCIE_LTSSM_HOT_RESET = 31,\n\tDW_PCIE_LTSSM_RCVRY_EQ0 = 32,\n\tDW_PCIE_LTSSM_RCVRY_EQ1 = 33,\n\tDW_PCIE_LTSSM_RCVRY_EQ2 = 34,\n\tDW_PCIE_LTSSM_RCVRY_EQ3 = 35,\n\tDW_PCIE_LTSSM_L1_1 = 321,\n\tDW_PCIE_LTSSM_L1_2 = 322,\n\tDW_PCIE_LTSSM_UNKNOWN = 4294967295,\n};\n\nenum dw_wdt_rmod {\n\tDW_WDT_RMOD_RESET = 1,\n\tDW_WDT_RMOD_IRQ = 2,\n};\n\nenum dw_xpcs_clock {\n\tDW_XPCS_CORE_CLK = 0,\n\tDW_XPCS_PAD_CLK = 1,\n\tDW_XPCS_NUM_CLKS = 2,\n};\n\nenum dw_xpcs_pcs_id {\n\tDW_XPCS_ID_NATIVE = 0,\n\tNXP_SJA1105_XPCS_ID = 16,\n\tNXP_SJA1110_XPCS_ID = 32,\n\tDW_XPCS_ID = 2039926480,\n\tDW_XPCS_ID_MASK = 4294967295,\n};\n\nenum dw_xpcs_pma_id {\n\tDW_XPCS_PMA_ID_NATIVE = 0,\n\tDW_XPCS_PMA_GEN1_3G_ID = 1,\n\tDW_XPCS_PMA_GEN2_3G_ID = 2,\n\tDW_XPCS_PMA_GEN2_6G_ID = 3,\n\tDW_XPCS_PMA_GEN4_3G_ID = 4,\n\tDW_XPCS_PMA_GEN4_6G_ID = 5,\n\tDW_XPCS_PMA_GEN5_10G_ID = 6,\n\tDW_XPCS_PMA_GEN5_12G_ID = 7,\n\tWX_TXGBE_XPCS_PMA_10G_ID = 4236271616,\n\tMP_FBNIC_XPCS_PMA_100G_ID = 1183858688,\n};\n\nenum dwc2_control_phase {\n\tDWC2_CONTROL_SETUP = 0,\n\tDWC2_CONTROL_DATA = 1,\n\tDWC2_CONTROL_STATUS = 2,\n};\n\nenum dwc2_ep0_state {\n\tDWC2_EP0_SETUP = 0,\n\tDWC2_EP0_DATA_IN = 1,\n\tDWC2_EP0_DATA_OUT = 2,\n\tDWC2_EP0_STATUS_IN = 3,\n\tDWC2_EP0_STATUS_OUT = 4,\n};\n\nenum dwc2_halt_status {\n\tDWC2_HC_XFER_NO_HALT_STATUS = 0,\n\tDWC2_HC_XFER_COMPLETE = 1,\n\tDWC2_HC_XFER_URB_COMPLETE = 2,\n\tDWC2_HC_XFER_ACK = 3,\n\tDWC2_HC_XFER_NAK = 4,\n\tDWC2_HC_XFER_NYET = 5,\n\tDWC2_HC_XFER_STALL = 6,\n\tDWC2_HC_XFER_XACT_ERR = 7,\n\tDWC2_HC_XFER_FRAME_OVERRUN = 8,\n\tDWC2_HC_XFER_BABBLE_ERR = 9,\n\tDWC2_HC_XFER_DATA_TOGGLE_ERR = 10,\n\tDWC2_HC_XFER_AHB_ERR = 11,\n\tDWC2_HC_XFER_PERIODIC_INCOMPLETE = 12,\n\tDWC2_HC_XFER_URB_DEQUEUE = 13,\n};\n\nenum dwc2_hsotg_dmamode {\n\tS3C_HSOTG_DMA_NONE = 0,\n\tS3C_HSOTG_DMA_ONLY = 1,\n\tS3C_HSOTG_DMA_DRV = 2,\n};\n\nenum dwc2_lx_state {\n\tDWC2_L0 = 0,\n\tDWC2_L1 = 1,\n\tDWC2_L2 = 2,\n\tDWC2_L3 = 3,\n};\n\nenum dwc2_transaction_type {\n\tDWC2_TRANSACTION_NONE = 0,\n\tDWC2_TRANSACTION_PERIODIC = 1,\n\tDWC2_TRANSACTION_NON_PERIODIC = 2,\n\tDWC2_TRANSACTION_ALL = 3,\n};\n\nenum dwc3_ep0_next {\n\tDWC3_EP0_UNKNOWN = 0,\n\tDWC3_EP0_COMPLETE = 1,\n\tDWC3_EP0_NRDY_DATA = 2,\n\tDWC3_EP0_NRDY_STATUS = 3,\n};\n\nenum dwc3_ep0_state {\n\tEP0_UNCONNECTED = 0,\n\tEP0_SETUP_PHASE = 1,\n\tEP0_DATA_PHASE = 2,\n\tEP0_STATUS_PHASE = 3,\n};\n\nenum dwc3_link_state {\n\tDWC3_LINK_STATE_U0 = 0,\n\tDWC3_LINK_STATE_U1 = 1,\n\tDWC3_LINK_STATE_U2 = 2,\n\tDWC3_LINK_STATE_U3 = 3,\n\tDWC3_LINK_STATE_SS_DIS = 4,\n\tDWC3_LINK_STATE_RX_DET = 5,\n\tDWC3_LINK_STATE_SS_INACT = 6,\n\tDWC3_LINK_STATE_POLL = 7,\n\tDWC3_LINK_STATE_RECOV = 8,\n\tDWC3_LINK_STATE_HRESET = 9,\n\tDWC3_LINK_STATE_CMPLY = 10,\n\tDWC3_LINK_STATE_LPBK = 11,\n\tDWC3_LINK_STATE_RESET = 14,\n\tDWC3_LINK_STATE_RESUME = 15,\n\tDWC3_LINK_STATE_MASK = 15,\n};\n\nenum dwc3_omap_utmi_mode {\n\tDWC3_OMAP_UTMI_MODE_UNKNOWN = 0,\n\tDWC3_OMAP_UTMI_MODE_HW = 1,\n\tDWC3_OMAP_UTMI_MODE_SW = 2,\n};\n\nenum dwmac4_irq_status {\n\ttime_stamp_irq = 4096,\n\tmmc_rx_csum_offload_irq = 2048,\n\tmmc_tx_irq = 1024,\n\tmmc_rx_irq = 512,\n\tmmc_irq = 256,\n\tlpi_irq = 32,\n\tpmt_irq = 16,\n};\n\nenum dwmac_core_type {\n\tDWMAC_CORE_MAC100 = 0,\n\tDWMAC_CORE_GMAC = 1,\n\tDWMAC_CORE_GMAC4 = 2,\n\tDWMAC_CORE_XGMAC = 3,\n};\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok = 1,\n\te1000_1000t_rx_status_undefined = 255,\n};\n\nenum e1000_boards {\n\tboard_82571 = 0,\n\tboard_82572 = 1,\n\tboard_82573 = 2,\n\tboard_82574 = 3,\n\tboard_82583 = 4,\n\tboard_80003es2lan = 5,\n\tboard_ich8lan = 6,\n\tboard_ich9lan = 7,\n\tboard_ich10lan = 8,\n\tboard_pchlan = 9,\n\tboard_pch2lan = 10,\n\tboard_pch_lpt = 11,\n\tboard_pch_spt = 12,\n\tboard_pch_cnp = 13,\n\tboard_pch_tgp = 14,\n\tboard_pch_adp = 15,\n\tboard_pch_mtp = 16,\n\tboard_pch_ptp = 17,\n};\n\nenum e1000_bus_speed {\n\te1000_bus_speed_unknown = 0,\n\te1000_bus_speed_33 = 1,\n\te1000_bus_speed_66 = 2,\n\te1000_bus_speed_100 = 3,\n\te1000_bus_speed_120 = 4,\n\te1000_bus_speed_133 = 5,\n\te1000_bus_speed_2500 = 6,\n\te1000_bus_speed_5000 = 7,\n\te1000_bus_speed_reserved = 8,\n};\n\nenum e1000_bus_type {\n\te1000_bus_type_unknown = 0,\n\te1000_bus_type_pci = 1,\n\te1000_bus_type_pcix = 2,\n\te1000_bus_type_pci_express = 3,\n\te1000_bus_type_reserved = 4,\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_pcie_x1 = 1,\n\te1000_bus_width_pcie_x2 = 2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32 = 9,\n\te1000_bus_width_64 = 10,\n\te1000_bus_width_reserved = 11,\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause = 1,\n\te1000_fc_tx_pause = 2,\n\te1000_fc_full = 3,\n\te1000_fc_default = 255,\n};\n\nenum e1000_mac_type {\n\te1000_82571 = 0,\n\te1000_82572 = 1,\n\te1000_82573 = 2,\n\te1000_82574 = 3,\n\te1000_82583 = 4,\n\te1000_80003es2lan = 5,\n\te1000_ich8lan = 6,\n\te1000_ich9lan = 7,\n\te1000_ich10lan = 8,\n\te1000_pchlan = 9,\n\te1000_pch2lan = 10,\n\te1000_pch_lpt = 11,\n\te1000_pch_spt = 12,\n\te1000_pch_cnp = 13,\n\te1000_pch_tgp = 14,\n\te1000_pch_adp = 15,\n\te1000_pch_mtp = 16,\n\te1000_pch_lnp = 17,\n\te1000_pch_ptp = 18,\n\te1000_pch_nvp = 19,\n};\n\nenum e1000_mac_type___2 {\n\te1000_undefined = 0,\n\te1000_82575 = 1,\n\te1000_82576 = 2,\n\te1000_82580 = 3,\n\te1000_i350 = 4,\n\te1000_i354 = 5,\n\te1000_i210 = 6,\n\te1000_i211 = 7,\n\te1000_num_macs = 8,\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper = 1,\n\te1000_media_type_fiber = 2,\n\te1000_media_type_internal_serdes = 3,\n\te1000_num_media_types = 4,\n};\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf = 1,\n\te1000_mng_mode_pt = 2,\n\te1000_mng_mode_ipmi = 3,\n\te1000_mng_mode_host_if_only = 4,\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master = 1,\n\te1000_ms_force_slave = 2,\n\te1000_ms_auto = 3,\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small = 1,\n\te1000_nvm_override_spi_large = 2,\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none = 1,\n\te1000_nvm_eeprom_spi = 2,\n\te1000_nvm_flash_hw = 3,\n\te1000_nvm_invm = 4,\n\te1000_nvm_flash_sw = 5,\n};\n\nenum e1000_nvm_type___2 {\n\te1000_nvm_unknown___2 = 0,\n\te1000_nvm_none___2 = 1,\n\te1000_nvm_eeprom_spi___2 = 2,\n\te1000_nvm_flash_hw___2 = 3,\n\te1000_nvm_flash_sw___2 = 4,\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none = 1,\n\te1000_phy_m88 = 2,\n\te1000_phy_igp = 3,\n\te1000_phy_igp_2 = 4,\n\te1000_phy_gg82563 = 5,\n\te1000_phy_igp_3 = 6,\n\te1000_phy_ife = 7,\n\te1000_phy_bm = 8,\n\te1000_phy_82578 = 9,\n\te1000_phy_82577 = 10,\n\te1000_phy_82579 = 11,\n\te1000_phy_i217 = 12,\n};\n\nenum e1000_phy_type___2 {\n\te1000_phy_unknown___2 = 0,\n\te1000_phy_none___2 = 1,\n\te1000_phy_m88___2 = 2,\n\te1000_phy_igp___2 = 3,\n\te1000_phy_igp_2___2 = 4,\n\te1000_phy_gg82563___2 = 5,\n\te1000_phy_igp_3___2 = 6,\n\te1000_phy_ife___2 = 7,\n\te1000_phy_82580 = 8,\n\te1000_phy_i210 = 9,\n\te1000_phy_bcm54616 = 10,\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed = 1,\n\te1000_rev_polarity_undefined = 255,\n};\n\nenum e1000_ring_flags_t {\n\tIGB_RING_FLAG_RX_3K_BUFFER = 0,\n\tIGB_RING_FLAG_RX_BUILD_SKB_ENABLED = 1,\n\tIGB_RING_FLAG_RX_SCTP_CSUM = 2,\n\tIGB_RING_FLAG_RX_LB_VLAN_BSWAP = 3,\n\tIGB_RING_FLAG_TX_CTX_IDX = 4,\n\tIGB_RING_FLAG_TX_DETECT_HANG = 5,\n\tIGB_RING_FLAG_TX_DISABLED = 6,\n\tIGB_RING_FLAG_RX_ALLOC_FAILED = 7,\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress = 1,\n\te1000_serdes_link_autoneg_complete = 2,\n\te1000_serdes_link_forced_up = 3,\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on = 1,\n\te1000_smart_speed_off = 2,\n};\n\nenum e1000_state_t {\n\t__E1000_TESTING = 0,\n\t__E1000_RESETTING = 1,\n\t__E1000_ACCESS_SHARED_RESOURCE = 2,\n\t__E1000_DOWN = 3,\n};\n\nenum e1000_state_t___2 {\n\t__IGB_TESTING = 0,\n\t__IGB_RESETTING = 1,\n\t__IGB_DOWN = 2,\n\t__IGB_PTP_TX_IN_PROGRESS = 3,\n};\n\nenum e1000_ulp_state {\n\te1000_ulp_state_unknown = 0,\n\te1000_ulp_state_off = 1,\n\te1000_ulp_state_on = 2,\n};\n\nenum edac_dev_feat {\n\tRAS_FEAT_SCRUB = 0,\n\tRAS_FEAT_ECS = 1,\n\tRAS_FEAT_MEM_REPAIR = 2,\n\tRAS_FEAT_MAX = 3,\n};\n\nenum edac_mc_layer_type {\n\tEDAC_MC_LAYER_BRANCH = 0,\n\tEDAC_MC_LAYER_CHANNEL = 1,\n\tEDAC_MC_LAYER_SLOT = 2,\n\tEDAC_MC_LAYER_CHIP_SELECT = 3,\n\tEDAC_MC_LAYER_ALL_MEM = 4,\n};\n\nenum edac_type {\n\tEDAC_UNKNOWN = 0,\n\tEDAC_NONE = 1,\n\tEDAC_RESERVED = 2,\n\tEDAC_PARITY = 3,\n\tEDAC_EC = 4,\n\tEDAC_SECDED = 5,\n\tEDAC_S2ECD2ED = 6,\n\tEDAC_S4ECD4ED = 7,\n\tEDAC_S8ECD8ED = 8,\n\tEDAC_S16ECD16ED = 9,\n};\n\nenum edid_block_status {\n\tEDID_BLOCK_OK = 0,\n\tEDID_BLOCK_READ_FAIL = 1,\n\tEDID_BLOCK_NULL = 2,\n\tEDID_BLOCK_ZERO = 3,\n\tEDID_BLOCK_HEADER_CORRUPT = 4,\n\tEDID_BLOCK_HEADER_REPAIR = 5,\n\tEDID_BLOCK_HEADER_FIXED = 6,\n\tEDID_BLOCK_CHECKSUM = 7,\n\tEDID_BLOCK_VERSION = 8,\n};\n\nenum edu_reg {\n\tEDU_CONFIG = 0,\n\tEDU_DRAM_ADDR = 1,\n\tEDU_EXT_ADDR = 2,\n\tEDU_LENGTH = 3,\n\tEDU_CMD = 4,\n\tEDU_STOP = 5,\n\tEDU_STATUS = 6,\n\tEDU_DONE = 7,\n\tEDU_ERR_STATUS = 8,\n};\n\nenum efi_rts_ids {\n\tEFI_NONE = 0,\n\tEFI_GET_TIME = 1,\n\tEFI_SET_TIME = 2,\n\tEFI_GET_WAKEUP_TIME = 3,\n\tEFI_SET_WAKEUP_TIME = 4,\n\tEFI_GET_VARIABLE = 5,\n\tEFI_GET_NEXT_VARIABLE = 6,\n\tEFI_SET_VARIABLE = 7,\n\tEFI_QUERY_VARIABLE_INFO = 8,\n\tEFI_GET_NEXT_HIGH_MONO_COUNT = 9,\n\tEFI_RESET_SYSTEM = 10,\n\tEFI_UPDATE_CAPSULE = 11,\n\tEFI_QUERY_CAPSULE_CAPS = 12,\n\tEFI_ACPI_PRM_HANDLER = 13,\n};\n\nenum ehci_hrtimer_event {\n\tEHCI_HRTIMER_POLL_ASS = 0,\n\tEHCI_HRTIMER_POLL_PSS = 1,\n\tEHCI_HRTIMER_POLL_DEAD = 2,\n\tEHCI_HRTIMER_UNLINK_INTR = 3,\n\tEHCI_HRTIMER_FREE_ITDS = 4,\n\tEHCI_HRTIMER_ACTIVE_UNLINK = 5,\n\tEHCI_HRTIMER_START_UNLINK_INTR = 6,\n\tEHCI_HRTIMER_ASYNC_UNLINKS = 7,\n\tEHCI_HRTIMER_IAA_WATCHDOG = 8,\n\tEHCI_HRTIMER_DISABLE_PERIODIC = 9,\n\tEHCI_HRTIMER_DISABLE_ASYNC = 10,\n\tEHCI_HRTIMER_IO_WATCHDOG = 11,\n\tEHCI_HRTIMER_NUM_EVENTS = 12,\n};\n\nenum ehci_rh_state {\n\tEHCI_RH_HALTED = 0,\n\tEHCI_RH_SUSPENDED = 1,\n\tEHCI_RH_RUNNING = 2,\n\tEHCI_RH_STOPPING = 3,\n};\n\nenum eint_type {\n\tEINT_TYPE_NONE = 0,\n\tEINT_TYPE_GPIO = 1,\n\tEINT_TYPE_WKUP = 2,\n\tEINT_TYPE_WKUP_MUX = 3,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum emc_dll_change {\n\tDLL_CHANGE_NONE = 0,\n\tDLL_CHANGE_ON = 1,\n\tDLL_CHANGE_OFF = 2,\n};\n\nenum emc_dram_type {\n\tDRAM_TYPE_DDR3 = 0,\n\tDRAM_TYPE_DDR1 = 1,\n\tDRAM_TYPE_LPDDR2 = 2,\n\tDRAM_TYPE_DDR2 = 3,\n};\n\nenum emc_dram_type___2 {\n\tDRAM_TYPE_DDR3___2 = 0,\n\tDRAM_TYPE_DDR1___2 = 1,\n\tDRAM_TYPE_LPDDR3 = 2,\n\tDRAM_TYPE_DDR2___2 = 3,\n};\n\nenum emc_dram_type___3 {\n\tDRAM_TYPE_RESERVED = 0,\n\tDRAM_TYPE_DDR1___3 = 1,\n\tDRAM_TYPE_LPDDR2___2 = 2,\n\tDRAM_TYPE_DDR2___3 = 3,\n};\n\nenum emc_rate_request_type {\n\tEMC_RATE_DEVFREQ = 0,\n\tEMC_RATE_DEBUG = 1,\n\tEMC_RATE_ICC = 2,\n\tEMC_RATE_TYPE_MAX = 3,\n};\n\nenum emc_rate_request_type___2 {\n\tEMC_RATE_DEBUG___2 = 0,\n\tEMC_RATE_ICC___2 = 1,\n\tEMC_RATE_TYPE_MAX___2 = 2,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum enum_div_cfg {\n\tDIV_RTC = 0,\n\tDIV_HSI = 1,\n\tDIV_MCO1 = 2,\n\tDIV_MCO2 = 3,\n\tDIV_TRACE = 4,\n\tDIV_ETH1PTP = 5,\n\tDIV_ETH2PTP = 6,\n\tDIV_NB = 7,\n};\n\nenum enum_gate_cfg {\n\tGATE_ADC1 = 0,\n\tGATE_ADC2 = 1,\n\tGATE_CRC = 2,\n\tGATE_CRYP1 = 3,\n\tGATE_CRYP2 = 4,\n\tGATE_CSI = 5,\n\tGATE_DCMIPP = 6,\n\tGATE_DCMIPSSI = 7,\n\tGATE_DDRPERFM = 8,\n\tGATE_DTS = 9,\n\tGATE_ETH1 = 10,\n\tGATE_ETH1MAC = 11,\n\tGATE_ETH1RX = 12,\n\tGATE_ETH1STP = 13,\n\tGATE_ETH1TX = 14,\n\tGATE_ETH2 = 15,\n\tGATE_ETH2MAC = 16,\n\tGATE_ETH2RX = 17,\n\tGATE_ETH2STP = 18,\n\tGATE_ETH2TX = 19,\n\tGATE_FDCAN = 20,\n\tGATE_HASH1 = 21,\n\tGATE_HASH2 = 22,\n\tGATE_HDP = 23,\n\tGATE_I2C1 = 24,\n\tGATE_I2C2 = 25,\n\tGATE_I2C3 = 26,\n\tGATE_I3C1 = 27,\n\tGATE_I3C2 = 28,\n\tGATE_I3C3 = 29,\n\tGATE_IWDG1 = 30,\n\tGATE_IWDG2 = 31,\n\tGATE_IWDG3 = 32,\n\tGATE_IWDG4 = 33,\n\tGATE_LPTIM1 = 34,\n\tGATE_LPTIM2 = 35,\n\tGATE_LPTIM3 = 36,\n\tGATE_LPTIM4 = 37,\n\tGATE_LPTIM5 = 38,\n\tGATE_LPUART1 = 39,\n\tGATE_LTDC = 40,\n\tGATE_MCO1 = 41,\n\tGATE_MCO2 = 42,\n\tGATE_MDF1 = 43,\n\tGATE_OTG = 44,\n\tGATE_PKA = 45,\n\tGATE_RNG1 = 46,\n\tGATE_RNG2 = 47,\n\tGATE_SAES = 48,\n\tGATE_SAI1 = 49,\n\tGATE_SAI2 = 50,\n\tGATE_SAI3 = 51,\n\tGATE_SAI4 = 52,\n\tGATE_SDMMC1 = 53,\n\tGATE_SDMMC2 = 54,\n\tGATE_SDMMC3 = 55,\n\tGATE_SERC = 56,\n\tGATE_SPDIFRX = 57,\n\tGATE_SPI1 = 58,\n\tGATE_SPI2 = 59,\n\tGATE_SPI3 = 60,\n\tGATE_SPI4 = 61,\n\tGATE_SPI5 = 62,\n\tGATE_SPI6 = 63,\n\tGATE_TIM1 = 64,\n\tGATE_TIM10 = 65,\n\tGATE_TIM11 = 66,\n\tGATE_TIM12 = 67,\n\tGATE_TIM13 = 68,\n\tGATE_TIM14 = 69,\n\tGATE_TIM15 = 70,\n\tGATE_TIM16 = 71,\n\tGATE_TIM17 = 72,\n\tGATE_TIM2 = 73,\n\tGATE_TIM3 = 74,\n\tGATE_TIM4 = 75,\n\tGATE_TIM5 = 76,\n\tGATE_TIM6 = 77,\n\tGATE_TIM7 = 78,\n\tGATE_TIM8 = 79,\n\tGATE_UART4 = 80,\n\tGATE_UART5 = 81,\n\tGATE_UART7 = 82,\n\tGATE_USART1 = 83,\n\tGATE_USART2 = 84,\n\tGATE_USART3 = 85,\n\tGATE_USART6 = 86,\n\tGATE_USB2PHY1 = 87,\n\tGATE_USB2PHY2 = 88,\n\tGATE_USBH = 89,\n\tGATE_VREF = 90,\n\tGATE_WWDG1 = 91,\n\tGATE_NB = 92,\n};\n\nenum enum_gate_cfg___2 {\n\tGATE_MCO1___2 = 0,\n\tGATE_MCO2___2 = 1,\n\tGATE_DBGCK = 2,\n\tGATE_TRACECK = 3,\n\tGATE_DDRC1 = 4,\n\tGATE_DDRC1LP = 5,\n\tGATE_DDRPHYC = 6,\n\tGATE_DDRPHYCLP = 7,\n\tGATE_DDRCAPB = 8,\n\tGATE_DDRCAPBLP = 9,\n\tGATE_AXIDCG = 10,\n\tGATE_DDRPHYCAPB = 11,\n\tGATE_DDRPHYCAPBLP = 12,\n\tGATE_TIM2___2 = 13,\n\tGATE_TIM3___2 = 14,\n\tGATE_TIM4___2 = 15,\n\tGATE_TIM5___2 = 16,\n\tGATE_TIM6___2 = 17,\n\tGATE_TIM7___2 = 18,\n\tGATE_LPTIM1___2 = 19,\n\tGATE_SPI2___2 = 20,\n\tGATE_SPI3___2 = 21,\n\tGATE_USART3___2 = 22,\n\tGATE_UART4___2 = 23,\n\tGATE_UART5___2 = 24,\n\tGATE_UART7___2 = 25,\n\tGATE_UART8 = 26,\n\tGATE_I2C1___2 = 27,\n\tGATE_I2C2___2 = 28,\n\tGATE_SPDIF = 29,\n\tGATE_TIM1___2 = 30,\n\tGATE_TIM8___2 = 31,\n\tGATE_SPI1___2 = 32,\n\tGATE_USART6___2 = 33,\n\tGATE_SAI1___2 = 34,\n\tGATE_SAI2___2 = 35,\n\tGATE_DFSDM = 36,\n\tGATE_ADFSDM = 37,\n\tGATE_FDCAN___2 = 38,\n\tGATE_LPTIM2___2 = 39,\n\tGATE_LPTIM3___2 = 40,\n\tGATE_LPTIM4___2 = 41,\n\tGATE_LPTIM5___2 = 42,\n\tGATE_VREF___2 = 43,\n\tGATE_DTS___2 = 44,\n\tGATE_PMBCTRL = 45,\n\tGATE_HDP___2 = 46,\n\tGATE_SYSCFG = 47,\n\tGATE_DCMIPP___2 = 48,\n\tGATE_DDRPERFM___2 = 49,\n\tGATE_IWDG2APB = 50,\n\tGATE_USBPHY = 51,\n\tGATE_STGENRO = 52,\n\tGATE_LTDC___2 = 53,\n\tGATE_RTCAPB = 54,\n\tGATE_TZC = 55,\n\tGATE_ETZPC = 56,\n\tGATE_IWDG1APB = 57,\n\tGATE_BSEC = 58,\n\tGATE_STGENC = 59,\n\tGATE_USART1___2 = 60,\n\tGATE_USART2___2 = 61,\n\tGATE_SPI4___2 = 62,\n\tGATE_SPI5___2 = 63,\n\tGATE_I2C3___2 = 64,\n\tGATE_I2C4 = 65,\n\tGATE_I2C5 = 66,\n\tGATE_TIM12___2 = 67,\n\tGATE_TIM13___2 = 68,\n\tGATE_TIM14___2 = 69,\n\tGATE_TIM15___2 = 70,\n\tGATE_TIM16___2 = 71,\n\tGATE_TIM17___2 = 72,\n\tGATE_DMA1 = 73,\n\tGATE_DMA2 = 74,\n\tGATE_DMAMUX1 = 75,\n\tGATE_DMA3 = 76,\n\tGATE_DMAMUX2 = 77,\n\tGATE_ADC1___2 = 78,\n\tGATE_ADC2___2 = 79,\n\tGATE_USBO = 80,\n\tGATE_TSC = 81,\n\tGATE_GPIOA = 82,\n\tGATE_GPIOB = 83,\n\tGATE_GPIOC = 84,\n\tGATE_GPIOD = 85,\n\tGATE_GPIOE = 86,\n\tGATE_GPIOF = 87,\n\tGATE_GPIOG = 88,\n\tGATE_GPIOH = 89,\n\tGATE_GPIOI = 90,\n\tGATE_PKA___2 = 91,\n\tGATE_SAES___2 = 92,\n\tGATE_CRYP1___2 = 93,\n\tGATE_HASH1___2 = 94,\n\tGATE_RNG1___2 = 95,\n\tGATE_BKPSRAM = 96,\n\tGATE_AXIMC = 97,\n\tGATE_MCE = 98,\n\tGATE_ETH1CK = 99,\n\tGATE_ETH1TX___2 = 100,\n\tGATE_ETH1RX___2 = 101,\n\tGATE_ETH1MAC___2 = 102,\n\tGATE_FMC = 103,\n\tGATE_QSPI = 104,\n\tGATE_SDMMC1___2 = 105,\n\tGATE_SDMMC2___2 = 106,\n\tGATE_CRC1 = 107,\n\tGATE_USBH___2 = 108,\n\tGATE_ETH2CK = 109,\n\tGATE_ETH2TX___2 = 110,\n\tGATE_ETH2RX___2 = 111,\n\tGATE_ETH2MAC___2 = 112,\n\tGATE_ETH1STP___2 = 113,\n\tGATE_ETH2STP___2 = 114,\n\tGATE_MDMA = 115,\n\tGATE_NB___2 = 116,\n};\n\nenum enum_mux_cfg {\n\tMUX_ADC1 = 0,\n\tMUX_ADC2 = 1,\n\tMUX_DCMIPP = 2,\n\tMUX_ETH1 = 3,\n\tMUX_ETH2 = 4,\n\tMUX_FDCAN = 5,\n\tMUX_FMC = 6,\n\tMUX_I2C12 = 7,\n\tMUX_I2C3 = 8,\n\tMUX_I2C4 = 9,\n\tMUX_I2C5 = 10,\n\tMUX_LPTIM1 = 11,\n\tMUX_LPTIM2 = 12,\n\tMUX_LPTIM3 = 13,\n\tMUX_LPTIM45 = 14,\n\tMUX_MCO1 = 15,\n\tMUX_MCO2 = 16,\n\tMUX_QSPI = 17,\n\tMUX_RNG1 = 18,\n\tMUX_SAES = 19,\n\tMUX_SAI1 = 20,\n\tMUX_SAI2 = 21,\n\tMUX_SDMMC1 = 22,\n\tMUX_SDMMC2 = 23,\n\tMUX_SPDIF = 24,\n\tMUX_SPI1 = 25,\n\tMUX_SPI23 = 26,\n\tMUX_SPI4 = 27,\n\tMUX_SPI5 = 28,\n\tMUX_STGEN = 29,\n\tMUX_UART1 = 30,\n\tMUX_UART2 = 31,\n\tMUX_UART4 = 32,\n\tMUX_UART6 = 33,\n\tMUX_UART35 = 34,\n\tMUX_UART78 = 35,\n\tMUX_USBO = 36,\n\tMUX_USBPHY = 37,\n\tMUX_NB = 38,\n};\n\nenum enum_mux_cfg___2 {\n\tMUX_ADC1___2 = 0,\n\tMUX_ADC2___2 = 1,\n\tMUX_DTS = 2,\n\tMUX_MCO1___2 = 3,\n\tMUX_MCO2___2 = 4,\n\tMUX_USB2PHY1 = 5,\n\tMUX_USB2PHY2 = 6,\n\tMUX_NB___2 = 7,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n\tETT_EVENT_EPROBE = 64,\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_FROZEN = 8,\n\tEVENT_CPU = 16,\n\tEVENT_CGROUP = 32,\n\tEVENT_GUEST = 64,\n\tEVENT_FLAGS = 96,\n\tEVENT_ALL = 3,\n\tEVENT_TIME_FROZEN = 12,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum ext4_journal_trigger_type {\n\tEXT4_JTR_ORPHAN_FILE = 0,\n\tEXT4_JTR_NONE = 1,\n};\n\nenum ext4_li_mode {\n\tEXT4_LI_MODE_PREFETCH_BBITMAP = 0,\n\tEXT4_LI_MODE_ITABLE = 1,\n};\n\nenum exynos4_plls {\n\tapll = 0,\n\tmpll = 1,\n\tepll = 2,\n\tvpll = 3,\n\tnr_plls = 4,\n};\n\nenum exynos4_soc {\n\tEXYNOS4210 = 0,\n\tEXYNOS4212 = 1,\n\tEXYNOS4412 = 2,\n};\n\nenum exynos5250_plls {\n\tapll___2 = 0,\n\tmpll___2 = 1,\n\tcpll = 2,\n\tepll___2 = 3,\n\tvpll___2 = 4,\n\tgpll = 5,\n\tbpll = 6,\n\tnr_plls___2 = 7,\n};\n\nenum exynos5410_plls {\n\tapll___3 = 0,\n\tcpll___2 = 1,\n\tepll___3 = 2,\n\tmpll___3 = 3,\n\tbpll___2 = 4,\n\tkpll = 5,\n\tnr_plls___3 = 6,\n};\n\nenum exynos5x_plls {\n\tapll___4 = 0,\n\tcpll___3 = 1,\n\tdpll = 2,\n\tepll___4 = 3,\n\trpll = 4,\n\tipll = 5,\n\tspll = 6,\n\tvpll___3 = 7,\n\tmpll___4 = 8,\n\tbpll___3 = 9,\n\tkpll___2 = 10,\n\tnr_plls___4 = 11,\n};\n\nenum exynos5x_soc {\n\tEXYNOS5420 = 0,\n\tEXYNOS5800 = 1,\n};\n\nenum exynos_cpuclk_layout {\n\tCPUCLK_LAYOUT_E4210 = 0,\n\tCPUCLK_LAYOUT_E5433 = 1,\n\tCPUCLK_LAYOUT_E850_CL0 = 2,\n\tCPUCLK_LAYOUT_E850_CL1 = 3,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum falcon_memory {\n\tFALCON_MEMORY_IMEM = 0,\n\tFALCON_MEMORY_DATA = 1,\n};\n\nenum fan53555_vendor {\n\tFAN53526_VENDOR_FAIRCHILD = 0,\n\tFAN53555_VENDOR_FAIRCHILD = 1,\n\tFAN53555_VENDOR_ROCKCHIP = 2,\n\tRK8602_VENDOR_ROCKCHIP = 3,\n\tFAN53555_VENDOR_SILERGY = 4,\n\tFAN53526_VENDOR_TCS = 5,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fec_txbuf_type {\n\tFEC_TXBUF_T_SKB = 0,\n\tFEC_TXBUF_T_XDP_NDO = 1,\n\tFEC_TXBUF_T_XDP_TX = 2,\n\tFEC_TXBUF_T_XSK_XMIT = 3,\n\tFEC_TXBUF_T_XSK_TX = 4,\n};\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_EDATA = 10,\n\tFETCH_OP_DEREF = 11,\n\tFETCH_OP_UDEREF = 12,\n\tFETCH_OP_ST_RAW = 13,\n\tFETCH_OP_ST_MEM = 14,\n\tFETCH_OP_ST_UMEM = 15,\n\tFETCH_OP_ST_STRING = 16,\n\tFETCH_OP_ST_USTRING = 17,\n\tFETCH_OP_ST_SYMSTR = 18,\n\tFETCH_OP_ST_EDATA = 19,\n\tFETCH_OP_MOD_BF = 20,\n\tFETCH_OP_LP_ARRAY = 21,\n\tFETCH_OP_TP_ARG = 22,\n\tFETCH_OP_END = 23,\n\tFETCH_NOP_SYMBOL = 24,\n};\n\nenum fh_pll_id {\n\tFH_CA53PLL_LL = 0,\n\tFH_CA53PLL_BL = 1,\n\tFH_MAINPLL = 2,\n\tFH_MPLL = 3,\n\tFH_MSDCPLL = 4,\n\tFH_MMPLL = 5,\n\tFH_VENCPLL = 6,\n\tFH_TVDPLL = 7,\n\tFH_VCODECPLL = 8,\n\tFH_NR_FH = 9,\n};\n\nenum fhctl_variant {\n\tFHCTL_PLLFH_V1 = 0,\n\tFHCTL_PLLFH_V2 = 1,\n};\n\nenum fib6_walk_state {\n\tFWS_L = 0,\n\tFWS_R = 1,\n\tFWS_C = 2,\n\tFWS_U = 3,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum filter_pred_fn {\n\tFILTER_PRED_FN_NOP = 0,\n\tFILTER_PRED_FN_64 = 1,\n\tFILTER_PRED_FN_64_CPUMASK = 2,\n\tFILTER_PRED_FN_S64 = 3,\n\tFILTER_PRED_FN_U64 = 4,\n\tFILTER_PRED_FN_32 = 5,\n\tFILTER_PRED_FN_32_CPUMASK = 6,\n\tFILTER_PRED_FN_S32 = 7,\n\tFILTER_PRED_FN_U32 = 8,\n\tFILTER_PRED_FN_16 = 9,\n\tFILTER_PRED_FN_16_CPUMASK = 10,\n\tFILTER_PRED_FN_S16 = 11,\n\tFILTER_PRED_FN_U16 = 12,\n\tFILTER_PRED_FN_8 = 13,\n\tFILTER_PRED_FN_8_CPUMASK = 14,\n\tFILTER_PRED_FN_S8 = 15,\n\tFILTER_PRED_FN_U8 = 16,\n\tFILTER_PRED_FN_COMM = 17,\n\tFILTER_PRED_FN_STRING = 18,\n\tFILTER_PRED_FN_STRLOC = 19,\n\tFILTER_PRED_FN_STRRELLOC = 20,\n\tFILTER_PRED_FN_PCHAR_USER = 21,\n\tFILTER_PRED_FN_PCHAR = 22,\n\tFILTER_PRED_FN_CPU = 23,\n\tFILTER_PRED_FN_CPU_CPUMASK = 24,\n\tFILTER_PRED_FN_CPUMASK = 25,\n\tFILTER_PRED_FN_CPUMASK_CPU = 26,\n\tFILTER_PRED_FN_FUNCTION = 27,\n\tFILTER_PRED_FN_ = 28,\n\tFILTER_PRED_TEST_VISITED = 29,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum fixed_addresses {\n\tFIX_EARLYCON_MEM_BASE = 0,\n\t__end_of_permanent_fixed_addresses = 1,\n\tFIX_KMAP_BEGIN = 1,\n\tFIX_KMAP_END = 256,\n\tFIX_TEXT_POKE0 = 257,\n\tFIX_TEXT_POKE1 = 258,\n\t__end_of_fixmap_region = 259,\n\tFIX_BTMAP_END = 1,\n\tFIX_BTMAP_BEGIN = 224,\n\t__end_of_early_ioremap_region = 225,\n};\n\nenum flash_dma_reg {\n\tFLASH_DMA_REVISION = 0,\n\tFLASH_DMA_FIRST_DESC = 1,\n\tFLASH_DMA_FIRST_DESC_EXT = 2,\n\tFLASH_DMA_CTRL = 3,\n\tFLASH_DMA_MODE = 4,\n\tFLASH_DMA_STATUS = 5,\n\tFLASH_DMA_INTERRUPT_DESC = 6,\n\tFLASH_DMA_INTERRUPT_DESC_EXT = 7,\n\tFLASH_DMA_ERROR_STATUS = 8,\n\tFLASH_DMA_CURRENT_DESC = 9,\n\tFLASH_DMA_CURRENT_DESC_EXT = 10,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_cls_command {\n\tFLOW_CLS_REPLACE = 0,\n\tFLOW_CLS_DESTROY = 1,\n\tFLOW_CLS_STATS = 2,\n\tFLOW_CLS_TMPLT_CREATE = 3,\n\tFLOW_CLS_TMPLT_DESTROY = 4,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum flowlabel_reflect {\n\tFLOWLABEL_REFLECT_ESTABLISHED = 1,\n\tFLOWLABEL_REFLECT_TCP_RESET = 2,\n\tFLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freq_policy {\n\tFLOOR = 0,\n\tCEIL = 1,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsl_edma_pm_state {\n\tRUNNING = 0,\n\tSUSPENDED = 1,\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n\tFW_OPT_PARTIAL = 128,\n};\n\nenum fw_resource_type {\n\tRSC_CARVEOUT = 0,\n\tRSC_DEVMEM = 1,\n\tRSC_TRACE = 2,\n\tRSC_VDEV = 3,\n\tRSC_LAST = 4,\n\tRSC_VENDOR_START = 128,\n\tRSC_VENDOR_END = 512,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nenum fwh_lock_state {\n\tFWH_UNLOCKED = 0,\n\tFWH_DENY_WRITE = 1,\n\tFWH_IMMUTABLE = 2,\n\tFWH_DENY_READ = 4,\n};\n\nenum gate_type {\n\tK_GATE = 0,\n\tK_FFC = 1,\n\tK_DIV = 2,\n\tK_BITSEL = 3,\n\tK_DUALGATE = 4,\n};\n\nenum gddrnf4_status {\n\tGDD4_OK = 0,\n\tGDD4_UNAVAIL = 1,\n};\n\nenum gdsc_status {\n\tGDSC_OFF = 0,\n\tGDSC_ON = 1,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum genpd_notication {\n\tGENPD_NOTIFY_PRE_OFF = 0,\n\tGENPD_NOTIFY_OFF = 1,\n\tGENPD_NOTIFY_PRE_ON = 2,\n\tGENPD_NOTIFY_ON = 3,\n};\n\nenum genpd_sync_state {\n\tGENPD_SYNC_STATE_OFF = 0,\n\tGENPD_SYNC_STATE_SIMPLE = 1,\n\tGENPD_SYNC_STATE_ONECELL = 2,\n};\n\nenum gfar_dev_state {\n\tGFAR_DOWN = 1,\n\tGFAR_RESETTING = 2,\n};\n\nenum gfar_errata {\n\tGFAR_ERRATA_74 = 1,\n\tGFAR_ERRATA_76 = 2,\n\tGFAR_ERRATA_A002 = 4,\n\tGFAR_ERRATA_12 = 8,\n};\n\nenum gfar_irqinfo_id {\n\tGFAR_TX = 0,\n\tGFAR_RX = 1,\n\tGFAR_ER = 2,\n\tGFAR_NUM_IRQS = 3,\n};\n\nenum gic_intid_range {\n\tSGI_RANGE = 0,\n\tPPI_RANGE = 1,\n\tSPI_RANGE = 2,\n\tEPPI_RANGE = 3,\n\tESPI_RANGE = 4,\n\tLPI_RANGE = 5,\n\t__INVALID_RANGE__ = 6,\n};\n\nenum gic_type {\n\tGIC_V2 = 0,\n\tGIC_V3 = 1,\n\tGIC_V5 = 2,\n};\n\nenum gio_reg_index {\n\tGIO_REG_ODEN = 0,\n\tGIO_REG_DATA = 1,\n\tGIO_REG_IODIR = 2,\n\tGIO_REG_EC = 3,\n\tGIO_REG_EI = 4,\n\tGIO_REG_MASK = 5,\n\tGIO_REG_LEVEL = 6,\n\tGIO_REG_STAT = 7,\n\tNUMBER_OF_GIO_REGISTERS = 8,\n};\n\nenum gpd_status {\n\tGENPD_STATE_ON = 0,\n\tGENPD_STATE_OFF = 1,\n};\n\nenum gpio_lookup_flags {\n\tGPIO_ACTIVE_HIGH = 0,\n\tGPIO_ACTIVE_LOW = 1,\n\tGPIO_OPEN_DRAIN = 2,\n\tGPIO_OPEN_SOURCE = 4,\n\tGPIO_PERSISTENT = 0,\n\tGPIO_TRANSITORY = 8,\n\tGPIO_PULL_UP = 16,\n\tGPIO_PULL_DOWN = 32,\n\tGPIO_PULL_DISABLE = 64,\n\tGPIO_LOOKUP_FLAGS_DEFAULT = 0,\n};\n\nenum gpio_v2_line_attr_id {\n\tGPIO_V2_LINE_ATTR_ID_FLAGS = 1,\n\tGPIO_V2_LINE_ATTR_ID_OUTPUT_VALUES = 2,\n\tGPIO_V2_LINE_ATTR_ID_DEBOUNCE = 3,\n};\n\nenum gpio_v2_line_changed_type {\n\tGPIO_V2_LINE_CHANGED_REQUESTED = 1,\n\tGPIO_V2_LINE_CHANGED_RELEASED = 2,\n\tGPIO_V2_LINE_CHANGED_CONFIG = 3,\n};\n\nenum gpio_v2_line_event_id {\n\tGPIO_V2_LINE_EVENT_RISING_EDGE = 1,\n\tGPIO_V2_LINE_EVENT_FALLING_EDGE = 2,\n};\n\nenum gpio_v2_line_flag {\n\tGPIO_V2_LINE_FLAG_USED = 1,\n\tGPIO_V2_LINE_FLAG_ACTIVE_LOW = 2,\n\tGPIO_V2_LINE_FLAG_INPUT = 4,\n\tGPIO_V2_LINE_FLAG_OUTPUT = 8,\n\tGPIO_V2_LINE_FLAG_EDGE_RISING = 16,\n\tGPIO_V2_LINE_FLAG_EDGE_FALLING = 32,\n\tGPIO_V2_LINE_FLAG_OPEN_DRAIN = 64,\n\tGPIO_V2_LINE_FLAG_OPEN_SOURCE = 128,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_UP = 256,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_DOWN = 512,\n\tGPIO_V2_LINE_FLAG_BIAS_DISABLED = 1024,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME = 2048,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE = 4096,\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nenum gpmc_clk_domain {\n\tGPMC_CD_FCLK = 0,\n\tGPMC_CD_CLK = 1,\n};\n\nenum gpmi_type {\n\tIS_MX23 = 0,\n\tIS_MX28 = 1,\n\tIS_MX6Q = 2,\n\tIS_MX6SX = 3,\n\tIS_MX7D = 4,\n\tIS_MX8QXP = 5,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum handshake_auth {\n\tHANDSHAKE_AUTH_UNSPEC = 0,\n\tHANDSHAKE_AUTH_UNAUTH = 1,\n\tHANDSHAKE_AUTH_PSK = 2,\n\tHANDSHAKE_AUTH_X509 = 3,\n};\n\nenum handshake_handler_class {\n\tHANDSHAKE_HANDLER_CLASS_NONE = 0,\n\tHANDSHAKE_HANDLER_CLASS_TLSHD = 1,\n\tHANDSHAKE_HANDLER_CLASS_MAX = 2,\n};\n\nenum handshake_msg_type {\n\tHANDSHAKE_MSG_TYPE_UNSPEC = 0,\n\tHANDSHAKE_MSG_TYPE_CLIENTHELLO = 1,\n\tHANDSHAKE_MSG_TYPE_SERVERHELLO = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum hdmi_3d_structure {\n\tHDMI_3D_STRUCTURE_INVALID = -1,\n\tHDMI_3D_STRUCTURE_FRAME_PACKING = 0,\n\tHDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1,\n\tHDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3,\n\tHDMI_3D_STRUCTURE_L_DEPTH = 4,\n\tHDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5,\n\tHDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8,\n};\n\nenum hdmi_active_aspect {\n\tHDMI_ACTIVE_ASPECT_16_9_TOP = 2,\n\tHDMI_ACTIVE_ASPECT_14_9_TOP = 3,\n\tHDMI_ACTIVE_ASPECT_16_9_CENTER = 4,\n\tHDMI_ACTIVE_ASPECT_PICTURE = 8,\n\tHDMI_ACTIVE_ASPECT_4_3 = 9,\n\tHDMI_ACTIVE_ASPECT_16_9 = 10,\n\tHDMI_ACTIVE_ASPECT_14_9 = 11,\n\tHDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15,\n};\n\nenum hdmi_audio_coding_type {\n\tHDMI_AUDIO_CODING_TYPE_STREAM = 0,\n\tHDMI_AUDIO_CODING_TYPE_PCM = 1,\n\tHDMI_AUDIO_CODING_TYPE_AC3 = 2,\n\tHDMI_AUDIO_CODING_TYPE_MPEG1 = 3,\n\tHDMI_AUDIO_CODING_TYPE_MP3 = 4,\n\tHDMI_AUDIO_CODING_TYPE_MPEG2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_DTS = 7,\n\tHDMI_AUDIO_CODING_TYPE_ATRAC = 8,\n\tHDMI_AUDIO_CODING_TYPE_DSD = 9,\n\tHDMI_AUDIO_CODING_TYPE_EAC3 = 10,\n\tHDMI_AUDIO_CODING_TYPE_DTS_HD = 11,\n\tHDMI_AUDIO_CODING_TYPE_MLP = 12,\n\tHDMI_AUDIO_CODING_TYPE_DST = 13,\n\tHDMI_AUDIO_CODING_TYPE_WMA_PRO = 14,\n\tHDMI_AUDIO_CODING_TYPE_CXT = 15,\n};\n\nenum hdmi_audio_coding_type_ext {\n\tHDMI_AUDIO_CODING_TYPE_EXT_CT = 0,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_EXT_DRA = 7,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10,\n};\n\nenum hdmi_audio_sample_frequency {\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7,\n};\n\nenum hdmi_audio_sample_size {\n\tHDMI_AUDIO_SAMPLE_SIZE_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_SIZE_16 = 1,\n\tHDMI_AUDIO_SAMPLE_SIZE_20 = 2,\n\tHDMI_AUDIO_SAMPLE_SIZE_24 = 3,\n};\n\nenum hdmi_colorimetry {\n\tHDMI_COLORIMETRY_NONE = 0,\n\tHDMI_COLORIMETRY_ITU_601 = 1,\n\tHDMI_COLORIMETRY_ITU_709 = 2,\n\tHDMI_COLORIMETRY_EXTENDED = 3,\n};\n\nenum hdmi_colorspace {\n\tHDMI_COLORSPACE_RGB = 0,\n\tHDMI_COLORSPACE_YUV422 = 1,\n\tHDMI_COLORSPACE_YUV444 = 2,\n\tHDMI_COLORSPACE_YUV420 = 3,\n\tHDMI_COLORSPACE_RESERVED4 = 4,\n\tHDMI_COLORSPACE_RESERVED5 = 5,\n\tHDMI_COLORSPACE_RESERVED6 = 6,\n\tHDMI_COLORSPACE_IDO_DEFINED = 7,\n};\n\nenum hdmi_content_type {\n\tHDMI_CONTENT_TYPE_GRAPHICS = 0,\n\tHDMI_CONTENT_TYPE_PHOTO = 1,\n\tHDMI_CONTENT_TYPE_CINEMA = 2,\n\tHDMI_CONTENT_TYPE_GAME = 3,\n};\n\nenum hdmi_eotf {\n\tHDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0,\n\tHDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1,\n\tHDMI_EOTF_SMPTE_ST2084 = 2,\n\tHDMI_EOTF_BT_2100_HLG = 3,\n};\n\nenum hdmi_extended_colorimetry {\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0,\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1,\n\tHDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2,\n\tHDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3,\n\tHDMI_EXTENDED_COLORIMETRY_OPRGB = 4,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020 = 6,\n\tHDMI_EXTENDED_COLORIMETRY_RESERVED = 7,\n};\n\nenum hdmi_infoframe_type {\n\tHDMI_INFOFRAME_TYPE_VENDOR = 129,\n\tHDMI_INFOFRAME_TYPE_AVI = 130,\n\tHDMI_INFOFRAME_TYPE_SPD = 131,\n\tHDMI_INFOFRAME_TYPE_AUDIO = 132,\n\tHDMI_INFOFRAME_TYPE_DRM = 135,\n};\n\nenum hdmi_metadata_type {\n\tHDMI_STATIC_METADATA_TYPE1 = 0,\n};\n\nenum hdmi_nups {\n\tHDMI_NUPS_UNKNOWN = 0,\n\tHDMI_NUPS_HORIZONTAL = 1,\n\tHDMI_NUPS_VERTICAL = 2,\n\tHDMI_NUPS_BOTH = 3,\n};\n\nenum hdmi_picture_aspect {\n\tHDMI_PICTURE_ASPECT_NONE = 0,\n\tHDMI_PICTURE_ASPECT_4_3 = 1,\n\tHDMI_PICTURE_ASPECT_16_9 = 2,\n\tHDMI_PICTURE_ASPECT_64_27 = 3,\n\tHDMI_PICTURE_ASPECT_256_135 = 4,\n\tHDMI_PICTURE_ASPECT_RESERVED = 5,\n};\n\nenum hdmi_quantization_range {\n\tHDMI_QUANTIZATION_RANGE_DEFAULT = 0,\n\tHDMI_QUANTIZATION_RANGE_LIMITED = 1,\n\tHDMI_QUANTIZATION_RANGE_FULL = 2,\n\tHDMI_QUANTIZATION_RANGE_RESERVED = 3,\n};\n\nenum hdmi_scan_mode {\n\tHDMI_SCAN_MODE_NONE = 0,\n\tHDMI_SCAN_MODE_OVERSCAN = 1,\n\tHDMI_SCAN_MODE_UNDERSCAN = 2,\n\tHDMI_SCAN_MODE_RESERVED = 3,\n};\n\nenum hdmi_spd_sdi {\n\tHDMI_SPD_SDI_UNKNOWN = 0,\n\tHDMI_SPD_SDI_DSTB = 1,\n\tHDMI_SPD_SDI_DVDP = 2,\n\tHDMI_SPD_SDI_DVHS = 3,\n\tHDMI_SPD_SDI_HDDVR = 4,\n\tHDMI_SPD_SDI_DVC = 5,\n\tHDMI_SPD_SDI_DSC = 6,\n\tHDMI_SPD_SDI_VCD = 7,\n\tHDMI_SPD_SDI_GAME = 8,\n\tHDMI_SPD_SDI_PC = 9,\n\tHDMI_SPD_SDI_BD = 10,\n\tHDMI_SPD_SDI_SACD = 11,\n\tHDMI_SPD_SDI_HDDVD = 12,\n\tHDMI_SPD_SDI_PMP = 13,\n};\n\nenum hdmi_ycc_quantization_range {\n\tHDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0,\n\tHDMI_YCC_QUANTIZATION_RANGE_FULL = 1,\n};\n\nenum hi6220_reset_ctrl_type {\n\tPERIPHERAL = 0,\n\tMEDIA = 1,\n\tAO = 2,\n};\n\nenum hid_class_request {\n\tHID_REQ_GET_REPORT = 1,\n\tHID_REQ_GET_IDLE = 2,\n\tHID_REQ_GET_PROTOCOL = 3,\n\tHID_REQ_SET_REPORT = 9,\n\tHID_REQ_SET_IDLE = 10,\n\tHID_REQ_SET_PROTOCOL = 11,\n};\n\nenum hid_report_type {\n\tHID_INPUT_REPORT = 0,\n\tHID_OUTPUT_REPORT = 1,\n\tHID_FEATURE_REPORT = 2,\n\tHID_REPORT_TYPES = 3,\n};\n\nenum hid_type {\n\tHID_TYPE_OTHER = 0,\n\tHID_TYPE_USBMOUSE = 1,\n\tHID_TYPE_USBNONE = 2,\n};\n\nenum hix5hd2_clk_type {\n\tTYPE_COMPLEX = 0,\n\tTYPE_ETHER = 1,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hn_flags_bits {\n\tHANDSHAKE_F_NET_DRAINING = 0,\n};\n\nenum host1x_class {\n\tHOST1X_CLASS_HOST1X = 1,\n\tHOST1X_CLASS_NVJPG1 = 7,\n\tHOST1X_CLASS_NVENC = 33,\n\tHOST1X_CLASS_NVENC1 = 34,\n\tHOST1X_CLASS_GR2D = 81,\n\tHOST1X_CLASS_GR2D_SB = 82,\n\tHOST1X_CLASS_VIC = 93,\n\tHOST1X_CLASS_GR3D = 96,\n\tHOST1X_CLASS_NVJPG = 192,\n\tHOST1X_CLASS_NVDEC = 240,\n\tHOST1X_CLASS_NVDEC1 = 245,\n\tHOST1X_CLASS_OFA = 248,\n};\n\nenum hp_flags_bits {\n\tHANDSHAKE_F_PROTO_NOTIFY = 0,\n};\n\nenum hprobe_state {\n\tHPROBE_LEASED = 0,\n\tHPROBE_STABLE = 1,\n\tHPROBE_GONE = 2,\n\tHPROBE_CONSUMED = 3,\n};\n\nenum hr_flags_bits {\n\tHANDSHAKE_F_REQ_COMPLETED = 0,\n\tHANDSHAKE_F_REQ_SESSION = 1,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hs_bus_speed_index {\n\tBCM_SPD_3P4MHZ = 0,\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nenum hub_activation_type {\n\tHUB_INIT = 0,\n\tHUB_INIT2 = 1,\n\tHUB_INIT3 = 2,\n\tHUB_POST_RESET = 3,\n\tHUB_RESUME = 4,\n\tHUB_RESET_RESUME = 5,\n};\n\nenum hub_led_mode {\n\tINDICATOR_AUTO = 0,\n\tINDICATOR_CYCLE = 1,\n\tINDICATOR_GREEN_BLINK = 2,\n\tINDICATOR_GREEN_BLINK_OFF = 3,\n\tINDICATOR_AMBER_BLINK = 4,\n\tINDICATOR_AMBER_BLINK_OFF = 5,\n\tINDICATOR_ALT_BLINK = 6,\n\tINDICATOR_ALT_BLINK_OFF = 7,\n} __attribute__((mode(byte)));\n\nenum hub_quiescing_type {\n\tHUB_DISCONNECT = 0,\n\tHUB_PRE_RESET = 1,\n\tHUB_SUSPEND = 2,\n};\n\nenum hw_event_mc_err_type {\n\tHW_EVENT_ERR_CORRECTED = 0,\n\tHW_EVENT_ERR_UNCORRECTED = 1,\n\tHW_EVENT_ERR_DEFERRED = 2,\n\tHW_EVENT_ERR_FATAL = 3,\n\tHW_EVENT_ERR_INFO = 4,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwerr_error_type {\n\tHWERR_RECOV_CPU = 0,\n\tHWERR_RECOV_MEMORY = 1,\n\tHWERR_RECOV_PCI = 2,\n\tHWERR_RECOV_CXL = 3,\n\tHWERR_RECOV_OTHERS = 4,\n\tHWERR_RECOV_MAX = 5,\n};\n\nenum hwmon_chip_attributes {\n\thwmon_chip_temp_reset_history = 0,\n\thwmon_chip_in_reset_history = 1,\n\thwmon_chip_curr_reset_history = 2,\n\thwmon_chip_power_reset_history = 3,\n\thwmon_chip_register_tz = 4,\n\thwmon_chip_update_interval = 5,\n\thwmon_chip_alarms = 6,\n\thwmon_chip_samples = 7,\n\thwmon_chip_curr_samples = 8,\n\thwmon_chip_in_samples = 9,\n\thwmon_chip_power_samples = 10,\n\thwmon_chip_temp_samples = 11,\n\thwmon_chip_beep_enable = 12,\n\thwmon_chip_pec = 13,\n};\n\nenum hwmon_curr_attributes {\n\thwmon_curr_enable = 0,\n\thwmon_curr_input = 1,\n\thwmon_curr_min = 2,\n\thwmon_curr_max = 3,\n\thwmon_curr_lcrit = 4,\n\thwmon_curr_crit = 5,\n\thwmon_curr_average = 6,\n\thwmon_curr_lowest = 7,\n\thwmon_curr_highest = 8,\n\thwmon_curr_reset_history = 9,\n\thwmon_curr_label = 10,\n\thwmon_curr_alarm = 11,\n\thwmon_curr_min_alarm = 12,\n\thwmon_curr_max_alarm = 13,\n\thwmon_curr_lcrit_alarm = 14,\n\thwmon_curr_crit_alarm = 15,\n\thwmon_curr_rated_min = 16,\n\thwmon_curr_rated_max = 17,\n\thwmon_curr_beep = 18,\n};\n\nenum hwmon_energy_attributes {\n\thwmon_energy_enable = 0,\n\thwmon_energy_input = 1,\n\thwmon_energy_label = 2,\n};\n\nenum hwmon_fan_attributes {\n\thwmon_fan_enable = 0,\n\thwmon_fan_input = 1,\n\thwmon_fan_label = 2,\n\thwmon_fan_min = 3,\n\thwmon_fan_max = 4,\n\thwmon_fan_div = 5,\n\thwmon_fan_pulses = 6,\n\thwmon_fan_target = 7,\n\thwmon_fan_alarm = 8,\n\thwmon_fan_min_alarm = 9,\n\thwmon_fan_max_alarm = 10,\n\thwmon_fan_fault = 11,\n\thwmon_fan_beep = 12,\n};\n\nenum hwmon_humidity_attributes {\n\thwmon_humidity_enable = 0,\n\thwmon_humidity_input = 1,\n\thwmon_humidity_label = 2,\n\thwmon_humidity_min = 3,\n\thwmon_humidity_min_hyst = 4,\n\thwmon_humidity_max = 5,\n\thwmon_humidity_max_hyst = 6,\n\thwmon_humidity_alarm = 7,\n\thwmon_humidity_fault = 8,\n\thwmon_humidity_rated_min = 9,\n\thwmon_humidity_rated_max = 10,\n\thwmon_humidity_min_alarm = 11,\n\thwmon_humidity_max_alarm = 12,\n};\n\nenum hwmon_in_attributes {\n\thwmon_in_enable = 0,\n\thwmon_in_input = 1,\n\thwmon_in_min = 2,\n\thwmon_in_max = 3,\n\thwmon_in_lcrit = 4,\n\thwmon_in_crit = 5,\n\thwmon_in_average = 6,\n\thwmon_in_lowest = 7,\n\thwmon_in_highest = 8,\n\thwmon_in_reset_history = 9,\n\thwmon_in_label = 10,\n\thwmon_in_alarm = 11,\n\thwmon_in_min_alarm = 12,\n\thwmon_in_max_alarm = 13,\n\thwmon_in_lcrit_alarm = 14,\n\thwmon_in_crit_alarm = 15,\n\thwmon_in_rated_min = 16,\n\thwmon_in_rated_max = 17,\n\thwmon_in_beep = 18,\n\thwmon_in_fault = 19,\n};\n\nenum hwmon_intrusion_attributes {\n\thwmon_intrusion_alarm = 0,\n\thwmon_intrusion_beep = 1,\n};\n\nenum hwmon_power_attributes {\n\thwmon_power_enable = 0,\n\thwmon_power_average = 1,\n\thwmon_power_average_interval = 2,\n\thwmon_power_average_interval_max = 3,\n\thwmon_power_average_interval_min = 4,\n\thwmon_power_average_highest = 5,\n\thwmon_power_average_lowest = 6,\n\thwmon_power_average_max = 7,\n\thwmon_power_average_min = 8,\n\thwmon_power_input = 9,\n\thwmon_power_input_highest = 10,\n\thwmon_power_input_lowest = 11,\n\thwmon_power_reset_history = 12,\n\thwmon_power_accuracy = 13,\n\thwmon_power_cap = 14,\n\thwmon_power_cap_hyst = 15,\n\thwmon_power_cap_max = 16,\n\thwmon_power_cap_min = 17,\n\thwmon_power_min = 18,\n\thwmon_power_max = 19,\n\thwmon_power_crit = 20,\n\thwmon_power_lcrit = 21,\n\thwmon_power_label = 22,\n\thwmon_power_alarm = 23,\n\thwmon_power_cap_alarm = 24,\n\thwmon_power_min_alarm = 25,\n\thwmon_power_max_alarm = 26,\n\thwmon_power_lcrit_alarm = 27,\n\thwmon_power_crit_alarm = 28,\n\thwmon_power_rated_min = 29,\n\thwmon_power_rated_max = 30,\n};\n\nenum hwmon_pwm_attributes {\n\thwmon_pwm_input = 0,\n\thwmon_pwm_enable = 1,\n\thwmon_pwm_mode = 2,\n\thwmon_pwm_freq = 3,\n\thwmon_pwm_auto_channels_temp = 4,\n};\n\nenum hwmon_sensor_types {\n\thwmon_chip = 0,\n\thwmon_temp = 1,\n\thwmon_in = 2,\n\thwmon_curr = 3,\n\thwmon_power = 4,\n\thwmon_energy = 5,\n\thwmon_energy64 = 6,\n\thwmon_humidity = 7,\n\thwmon_fan = 8,\n\thwmon_pwm = 9,\n\thwmon_intrusion = 10,\n\thwmon_max = 11,\n};\n\nenum hwmon_temp_attributes {\n\thwmon_temp_enable = 0,\n\thwmon_temp_input = 1,\n\thwmon_temp_type = 2,\n\thwmon_temp_lcrit = 3,\n\thwmon_temp_lcrit_hyst = 4,\n\thwmon_temp_min = 5,\n\thwmon_temp_min_hyst = 6,\n\thwmon_temp_max = 7,\n\thwmon_temp_max_hyst = 8,\n\thwmon_temp_crit = 9,\n\thwmon_temp_crit_hyst = 10,\n\thwmon_temp_emergency = 11,\n\thwmon_temp_emergency_hyst = 12,\n\thwmon_temp_alarm = 13,\n\thwmon_temp_lcrit_alarm = 14,\n\thwmon_temp_min_alarm = 15,\n\thwmon_temp_max_alarm = 16,\n\thwmon_temp_crit_alarm = 17,\n\thwmon_temp_emergency_alarm = 18,\n\thwmon_temp_fault = 19,\n\thwmon_temp_offset = 20,\n\thwmon_temp_label = 21,\n\thwmon_temp_lowest = 22,\n\thwmon_temp_highest = 23,\n\thwmon_temp_reset_history = 24,\n\thwmon_temp_rated_min = 25,\n\thwmon_temp_rated_max = 26,\n\thwmon_temp_beep = 27,\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nenum i2c_driver_flags {\n\tI2C_DRV_ACPI_WAIVE_D0_PROBE = 1,\n};\n\nenum i2c_eyeq5_speed {\n\tI2C_EYEQ5_SPEED_FAST = 0,\n\tI2C_EYEQ5_SPEED_FAST_PLUS = 1,\n\tI2C_EYEQ5_SPEED_HIGH_SPEED = 2,\n};\n\nenum i2c_freq_mode {\n\tI2C_FREQ_MODE_STANDARD = 0,\n\tI2C_FREQ_MODE_FAST = 1,\n\tI2C_FREQ_MODE_HIGH_SPEED = 2,\n\tI2C_FREQ_MODE_FAST_PLUS = 3,\n};\n\nenum i2c_operating_mode {\n\tI2C_OM_SLAVE = 0,\n\tI2C_OM_MASTER = 1,\n\tI2C_OM_MASTER_OR_SLAVE = 2,\n};\n\nenum i2c_operation {\n\tI2C_NO_OPERATION = 255,\n\tI2C_WRITE = 0,\n\tI2C_READ = 1,\n};\n\nenum i2c_scl_freq {\n\tREG_VALUES_100KHZ = 0,\n\tREG_VALUES_400KHZ = 1,\n\tREG_VALUES_1MHZ = 2,\n};\n\nenum i2c_slave_event {\n\tI2C_SLAVE_READ_REQUESTED = 0,\n\tI2C_SLAVE_WRITE_REQUESTED = 1,\n\tI2C_SLAVE_READ_PROCESSED = 2,\n\tI2C_SLAVE_WRITE_RECEIVED = 3,\n\tI2C_SLAVE_STOP = 4,\n};\n\nenum i2c_slave_read_status {\n\tI2C_SLAVE_RX_FIFO_EMPTY = 0,\n\tI2C_SLAVE_RX_START = 1,\n\tI2C_SLAVE_RX_DATA = 2,\n\tI2C_SLAVE_RX_END = 3,\n};\n\nenum i2c_status {\n\tI2C_NOP = 0,\n\tI2C_ON_GOING = 1,\n\tI2C_OK = 2,\n\tI2C_ABORT = 3,\n};\n\nenum i2c_type_exynos {\n\tI2C_TYPE_EXYNOS5 = 0,\n\tI2C_TYPE_EXYNOS7 = 1,\n\tI2C_TYPE_EXYNOSAUTOV9 = 2,\n\tI2C_TYPE_EXYNOS8895 = 3,\n};\n\nenum ib_atomic_cap {\n\tIB_ATOMIC_NONE = 0,\n\tIB_ATOMIC_HCA = 1,\n\tIB_ATOMIC_GLOB = 2,\n};\n\nenum ib_cq_notify_flags {\n\tIB_CQ_SOLICITED = 1,\n\tIB_CQ_NEXT_COMP = 2,\n\tIB_CQ_SOLICITED_MASK = 3,\n\tIB_CQ_REPORT_MISSED_EVENTS = 4,\n};\n\nenum ib_event_type {\n\tIB_EVENT_CQ_ERR = 0,\n\tIB_EVENT_QP_FATAL = 1,\n\tIB_EVENT_QP_REQ_ERR = 2,\n\tIB_EVENT_QP_ACCESS_ERR = 3,\n\tIB_EVENT_COMM_EST = 4,\n\tIB_EVENT_SQ_DRAINED = 5,\n\tIB_EVENT_PATH_MIG = 6,\n\tIB_EVENT_PATH_MIG_ERR = 7,\n\tIB_EVENT_DEVICE_FATAL = 8,\n\tIB_EVENT_PORT_ACTIVE = 9,\n\tIB_EVENT_PORT_ERR = 10,\n\tIB_EVENT_LID_CHANGE = 11,\n\tIB_EVENT_PKEY_CHANGE = 12,\n\tIB_EVENT_SM_CHANGE = 13,\n\tIB_EVENT_SRQ_ERR = 14,\n\tIB_EVENT_SRQ_LIMIT_REACHED = 15,\n\tIB_EVENT_QP_LAST_WQE_REACHED = 16,\n\tIB_EVENT_CLIENT_REREGISTER = 17,\n\tIB_EVENT_GID_CHANGE = 18,\n\tIB_EVENT_WQ_FATAL = 19,\n\tIB_EVENT_DEVICE_SPEED_CHANGE = 20,\n};\n\nenum ib_flow_action_type {\n\tIB_FLOW_ACTION_UNSPECIFIED = 0,\n\tIB_FLOW_ACTION_ESP = 1,\n};\n\nenum ib_flow_attr_type {\n\tIB_FLOW_ATTR_NORMAL = 0,\n\tIB_FLOW_ATTR_ALL_DEFAULT = 1,\n\tIB_FLOW_ATTR_MC_DEFAULT = 2,\n\tIB_FLOW_ATTR_SNIFFER = 3,\n};\n\nenum ib_flow_spec_type {\n\tIB_FLOW_SPEC_ETH = 32,\n\tIB_FLOW_SPEC_IB = 34,\n\tIB_FLOW_SPEC_IPV4 = 48,\n\tIB_FLOW_SPEC_IPV6 = 49,\n\tIB_FLOW_SPEC_ESP = 52,\n\tIB_FLOW_SPEC_TCP = 64,\n\tIB_FLOW_SPEC_UDP = 65,\n\tIB_FLOW_SPEC_VXLAN_TUNNEL = 80,\n\tIB_FLOW_SPEC_GRE = 81,\n\tIB_FLOW_SPEC_MPLS = 96,\n\tIB_FLOW_SPEC_INNER = 256,\n\tIB_FLOW_SPEC_ACTION_TAG = 4096,\n\tIB_FLOW_SPEC_ACTION_DROP = 4097,\n\tIB_FLOW_SPEC_ACTION_HANDLE = 4098,\n\tIB_FLOW_SPEC_ACTION_COUNT = 4099,\n};\n\nenum ib_gid_type {\n\tIB_GID_TYPE_IB = 0,\n\tIB_GID_TYPE_ROCE = 1,\n\tIB_GID_TYPE_ROCE_UDP_ENCAP = 2,\n\tIB_GID_TYPE_SIZE = 3,\n};\n\nenum ib_mig_state {\n\tIB_MIG_MIGRATED = 0,\n\tIB_MIG_REARM = 1,\n\tIB_MIG_ARMED = 2,\n};\n\nenum ib_mr_type {\n\tIB_MR_TYPE_MEM_REG = 0,\n\tIB_MR_TYPE_SG_GAPS = 1,\n\tIB_MR_TYPE_DM = 2,\n\tIB_MR_TYPE_USER = 3,\n\tIB_MR_TYPE_DMA = 4,\n\tIB_MR_TYPE_INTEGRITY = 5,\n};\n\nenum ib_mtu {\n\tIB_MTU_256 = 1,\n\tIB_MTU_512 = 2,\n\tIB_MTU_1024 = 3,\n\tIB_MTU_2048 = 4,\n\tIB_MTU_4096 = 5,\n};\n\nenum ib_mw_type {\n\tIB_MW_TYPE_1 = 1,\n\tIB_MW_TYPE_2 = 2,\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nenum ib_port_state {\n\tIB_PORT_NOP = 0,\n\tIB_PORT_DOWN = 1,\n\tIB_PORT_INIT = 2,\n\tIB_PORT_ARMED = 3,\n\tIB_PORT_ACTIVE = 4,\n\tIB_PORT_ACTIVE_DEFER = 5,\n};\n\nenum ib_qp_state {\n\tIB_QPS_RESET = 0,\n\tIB_QPS_INIT = 1,\n\tIB_QPS_RTR = 2,\n\tIB_QPS_RTS = 3,\n\tIB_QPS_SQD = 4,\n\tIB_QPS_SQE = 5,\n\tIB_QPS_ERR = 6,\n};\n\nenum ib_qp_type {\n\tIB_QPT_SMI = 0,\n\tIB_QPT_GSI = 1,\n\tIB_QPT_RC = 2,\n\tIB_QPT_UC = 3,\n\tIB_QPT_UD = 4,\n\tIB_QPT_RAW_IPV6 = 5,\n\tIB_QPT_RAW_ETHERTYPE = 6,\n\tIB_QPT_RAW_PACKET = 8,\n\tIB_QPT_XRC_INI = 9,\n\tIB_QPT_XRC_TGT = 10,\n\tIB_QPT_MAX = 11,\n\tIB_QPT_DRIVER = 255,\n\tIB_QPT_RESERVED1 = 4096,\n\tIB_QPT_RESERVED2 = 4097,\n\tIB_QPT_RESERVED3 = 4098,\n\tIB_QPT_RESERVED4 = 4099,\n\tIB_QPT_RESERVED5 = 4100,\n\tIB_QPT_RESERVED6 = 4101,\n\tIB_QPT_RESERVED7 = 4102,\n\tIB_QPT_RESERVED8 = 4103,\n\tIB_QPT_RESERVED9 = 4104,\n\tIB_QPT_RESERVED10 = 4105,\n};\n\nenum ib_sig_err_type {\n\tIB_SIG_BAD_GUARD = 0,\n\tIB_SIG_BAD_REFTAG = 1,\n\tIB_SIG_BAD_APPTAG = 2,\n};\n\nenum ib_sig_type {\n\tIB_SIGNAL_ALL_WR = 0,\n\tIB_SIGNAL_REQ_WR = 1,\n};\n\nenum ib_signature_type {\n\tIB_SIG_TYPE_NONE = 0,\n\tIB_SIG_TYPE_T10_DIF = 1,\n};\n\nenum ib_srq_attr_mask {\n\tIB_SRQ_MAX_WR = 1,\n\tIB_SRQ_LIMIT = 2,\n};\n\nenum ib_srq_type {\n\tIB_SRQT_BASIC = 0,\n\tIB_SRQT_XRC = 1,\n\tIB_SRQT_TM = 2,\n};\n\nenum ib_t10_dif_bg_type {\n\tIB_T10DIF_CRC = 0,\n\tIB_T10DIF_CSUM = 1,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_FLUSH_GLOBAL = 256,\n\tIB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_advise_mr_advice {\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2,\n};\n\nenum ib_uverbs_device_cap_flags {\n\tIB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL,\n\tIB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL,\n\tIB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL,\n\tIB_UVERBS_DEVICE_RAW_MULTI = 8ULL,\n\tIB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL,\n\tIB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL,\n\tIB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL,\n\tIB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL,\n\tIB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL,\n\tIB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL,\n\tIB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL,\n\tIB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL,\n\tIB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL,\n\tIB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL,\n\tIB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL,\n\tIB_UVERBS_DEVICE_XRC = 1048576ULL,\n\tIB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL,\n\tIB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL,\n\tIB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL,\n\tIB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL,\n\tIB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL,\n\tIB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL,\n\tIB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL,\n\tIB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL,\n\tIB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL,\n};\n\nenum ib_uverbs_gid_type {\n\tIB_UVERBS_GID_TYPE_IB = 0,\n\tIB_UVERBS_GID_TYPE_ROCE_V1 = 1,\n\tIB_UVERBS_GID_TYPE_ROCE_V2 = 2,\n};\n\nenum ib_uverbs_odp_general_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT = 1,\n\tIB_UVERBS_ODP_SUPPORT_IMPLICIT = 2,\n};\n\nenum ib_uverbs_odp_transport_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT_SEND = 1,\n\tIB_UVERBS_ODP_SUPPORT_RECV = 2,\n\tIB_UVERBS_ODP_SUPPORT_WRITE = 4,\n\tIB_UVERBS_ODP_SUPPORT_READ = 8,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC = 16,\n\tIB_UVERBS_ODP_SUPPORT_SRQ_RECV = 32,\n\tIB_UVERBS_ODP_SUPPORT_FLUSH = 64,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 128,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_raw_packet_caps {\n\tIB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2,\n\tIB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4,\n\tIB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wc_opcode {\n\tIB_UVERBS_WC_SEND = 0,\n\tIB_UVERBS_WC_RDMA_WRITE = 1,\n\tIB_UVERBS_WC_RDMA_READ = 2,\n\tIB_UVERBS_WC_COMP_SWAP = 3,\n\tIB_UVERBS_WC_FETCH_ADD = 4,\n\tIB_UVERBS_WC_BIND_MW = 5,\n\tIB_UVERBS_WC_LOCAL_INV = 6,\n\tIB_UVERBS_WC_TSO = 7,\n\tIB_UVERBS_WC_FLUSH = 8,\n\tIB_UVERBS_WC_ATOMIC_WRITE = 9,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_UVERBS_WR_FLUSH = 14,\n\tIB_UVERBS_WR_ATOMIC_WRITE = 15,\n};\n\nenum ib_wc_opcode {\n\tIB_WC_SEND = 0,\n\tIB_WC_RDMA_WRITE = 1,\n\tIB_WC_RDMA_READ = 2,\n\tIB_WC_COMP_SWAP = 3,\n\tIB_WC_FETCH_ADD = 4,\n\tIB_WC_BIND_MW = 5,\n\tIB_WC_LOCAL_INV = 6,\n\tIB_WC_LSO = 7,\n\tIB_WC_ATOMIC_WRITE = 9,\n\tIB_WC_REG_MR = 10,\n\tIB_WC_MASKED_COMP_SWAP = 11,\n\tIB_WC_MASKED_FETCH_ADD = 12,\n\tIB_WC_FLUSH = 8,\n\tIB_WC_RECV = 128,\n\tIB_WC_RECV_RDMA_WITH_IMM = 129,\n};\n\nenum ib_wc_status {\n\tIB_WC_SUCCESS = 0,\n\tIB_WC_LOC_LEN_ERR = 1,\n\tIB_WC_LOC_QP_OP_ERR = 2,\n\tIB_WC_LOC_EEC_OP_ERR = 3,\n\tIB_WC_LOC_PROT_ERR = 4,\n\tIB_WC_WR_FLUSH_ERR = 5,\n\tIB_WC_MW_BIND_ERR = 6,\n\tIB_WC_BAD_RESP_ERR = 7,\n\tIB_WC_LOC_ACCESS_ERR = 8,\n\tIB_WC_REM_INV_REQ_ERR = 9,\n\tIB_WC_REM_ACCESS_ERR = 10,\n\tIB_WC_REM_OP_ERR = 11,\n\tIB_WC_RETRY_EXC_ERR = 12,\n\tIB_WC_RNR_RETRY_EXC_ERR = 13,\n\tIB_WC_LOC_RDD_VIOL_ERR = 14,\n\tIB_WC_REM_INV_RD_REQ_ERR = 15,\n\tIB_WC_REM_ABORT_ERR = 16,\n\tIB_WC_INV_EECN_ERR = 17,\n\tIB_WC_INV_EEC_STATE_ERR = 18,\n\tIB_WC_FATAL_ERR = 19,\n\tIB_WC_RESP_TIMEOUT_ERR = 20,\n\tIB_WC_GENERAL_ERR = 21,\n};\n\nenum ib_wq_state {\n\tIB_WQS_RESET = 0,\n\tIB_WQS_RDY = 1,\n\tIB_WQS_ERR = 2,\n};\n\nenum ib_wq_type {\n\tIB_WQT_RQ = 0,\n};\n\nenum ib_wr_opcode {\n\tIB_WR_RDMA_WRITE = 0,\n\tIB_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_WR_SEND = 2,\n\tIB_WR_SEND_WITH_IMM = 3,\n\tIB_WR_RDMA_READ = 4,\n\tIB_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_WR_BIND_MW = 8,\n\tIB_WR_LSO = 10,\n\tIB_WR_SEND_WITH_INV = 9,\n\tIB_WR_RDMA_READ_WITH_INV = 11,\n\tIB_WR_LOCAL_INV = 7,\n\tIB_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_WR_FLUSH = 14,\n\tIB_WR_ATOMIC_WRITE = 15,\n\tIB_WR_REG_MR = 32,\n\tIB_WR_REG_MR_INTEGRITY = 33,\n\tIB_WR_RESERVED1 = 240,\n\tIB_WR_RESERVED2 = 241,\n\tIB_WR_RESERVED3 = 242,\n\tIB_WR_RESERVED4 = 243,\n\tIB_WR_RESERVED5 = 244,\n\tIB_WR_RESERVED6 = 245,\n\tIB_WR_RESERVED7 = 246,\n\tIB_WR_RESERVED8 = 247,\n\tIB_WR_RESERVED9 = 248,\n\tIB_WR_RESERVED10 = 249,\n};\n\nenum icst_control_type {\n\tICST_VERSATILE = 0,\n\tICST_INTEGRATOR_AP_CM = 1,\n\tICST_INTEGRATOR_AP_SYS = 2,\n\tICST_INTEGRATOR_AP_PCI = 3,\n\tICST_INTEGRATOR_CP_CM_CORE = 4,\n\tICST_INTEGRATOR_CP_CM_MEM = 5,\n\tICST_INTEGRATOR_IM_PD1 = 6,\n};\n\nenum igb_boards {\n\tboard_82575 = 0,\n};\n\nenum igb_diagnostics_results {\n\tTEST_REG = 0,\n\tTEST_EEP = 1,\n\tTEST_IRQ = 2,\n\tTEST_LOOP = 3,\n\tTEST_LINK = 4,\n};\n\nenum igb_filter_match_flags {\n\tIGB_FILTER_FLAG_ETHER_TYPE = 1,\n\tIGB_FILTER_FLAG_VLAN_TCI = 2,\n\tIGB_FILTER_FLAG_SRC_MAC_ADDR = 4,\n\tIGB_FILTER_FLAG_DST_MAC_ADDR = 8,\n};\n\nenum igb_tx_buf_type {\n\tIGB_TYPE_SKB = 0,\n\tIGB_TYPE_XDP = 1,\n\tIGB_TYPE_XSK = 2,\n};\n\nenum igb_tx_flags {\n\tIGB_TX_FLAGS_VLAN = 1,\n\tIGB_TX_FLAGS_TSO = 2,\n\tIGB_TX_FLAGS_TSTAMP = 4,\n\tIGB_TX_FLAGS_IPV4 = 16,\n\tIGB_TX_FLAGS_CSUM = 32,\n};\n\nenum iio_available_type {\n\tIIO_AVAIL_LIST = 0,\n\tIIO_AVAIL_RANGE = 1,\n};\n\nenum iio_buffer_direction {\n\tIIO_BUFFER_DIRECTION_IN = 0,\n\tIIO_BUFFER_DIRECTION_OUT = 1,\n};\n\nenum iio_chan_info_enum {\n\tIIO_CHAN_INFO_RAW = 0,\n\tIIO_CHAN_INFO_PROCESSED = 1,\n\tIIO_CHAN_INFO_SCALE = 2,\n\tIIO_CHAN_INFO_OFFSET = 3,\n\tIIO_CHAN_INFO_CALIBSCALE = 4,\n\tIIO_CHAN_INFO_CALIBBIAS = 5,\n\tIIO_CHAN_INFO_PEAK = 6,\n\tIIO_CHAN_INFO_PEAK_SCALE = 7,\n\tIIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW = 8,\n\tIIO_CHAN_INFO_AVERAGE_RAW = 9,\n\tIIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY = 10,\n\tIIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY = 11,\n\tIIO_CHAN_INFO_SAMP_FREQ = 12,\n\tIIO_CHAN_INFO_FREQUENCY = 13,\n\tIIO_CHAN_INFO_PHASE = 14,\n\tIIO_CHAN_INFO_HARDWAREGAIN = 15,\n\tIIO_CHAN_INFO_HYSTERESIS = 16,\n\tIIO_CHAN_INFO_HYSTERESIS_RELATIVE = 17,\n\tIIO_CHAN_INFO_INT_TIME = 18,\n\tIIO_CHAN_INFO_ENABLE = 19,\n\tIIO_CHAN_INFO_CALIBHEIGHT = 20,\n\tIIO_CHAN_INFO_CALIBWEIGHT = 21,\n\tIIO_CHAN_INFO_DEBOUNCE_COUNT = 22,\n\tIIO_CHAN_INFO_DEBOUNCE_TIME = 23,\n\tIIO_CHAN_INFO_CALIBEMISSIVITY = 24,\n\tIIO_CHAN_INFO_OVERSAMPLING_RATIO = 25,\n\tIIO_CHAN_INFO_THERMOCOUPLE_TYPE = 26,\n\tIIO_CHAN_INFO_CALIBAMBIENT = 27,\n\tIIO_CHAN_INFO_ZEROPOINT = 28,\n\tIIO_CHAN_INFO_TROUGH = 29,\n\tIIO_CHAN_INFO_CONVDELAY = 30,\n\tIIO_CHAN_INFO_POWERFACTOR = 31,\n};\n\nenum iio_chan_type {\n\tIIO_VOLTAGE = 0,\n\tIIO_CURRENT = 1,\n\tIIO_POWER = 2,\n\tIIO_ACCEL = 3,\n\tIIO_ANGL_VEL = 4,\n\tIIO_MAGN = 5,\n\tIIO_LIGHT = 6,\n\tIIO_INTENSITY = 7,\n\tIIO_PROXIMITY = 8,\n\tIIO_TEMP = 9,\n\tIIO_INCLI = 10,\n\tIIO_ROT = 11,\n\tIIO_ANGL = 12,\n\tIIO_TIMESTAMP = 13,\n\tIIO_CAPACITANCE = 14,\n\tIIO_ALTVOLTAGE = 15,\n\tIIO_CCT = 16,\n\tIIO_PRESSURE = 17,\n\tIIO_HUMIDITYRELATIVE = 18,\n\tIIO_ACTIVITY = 19,\n\tIIO_STEPS = 20,\n\tIIO_ENERGY = 21,\n\tIIO_DISTANCE = 22,\n\tIIO_VELOCITY = 23,\n\tIIO_CONCENTRATION = 24,\n\tIIO_RESISTANCE = 25,\n\tIIO_PH = 26,\n\tIIO_UVINDEX = 27,\n\tIIO_ELECTRICALCONDUCTIVITY = 28,\n\tIIO_COUNT = 29,\n\tIIO_INDEX = 30,\n\tIIO_GRAVITY = 31,\n\tIIO_POSITIONRELATIVE = 32,\n\tIIO_PHASE = 33,\n\tIIO_MASSCONCENTRATION = 34,\n\tIIO_DELTA_ANGL = 35,\n\tIIO_DELTA_VELOCITY = 36,\n\tIIO_COLORTEMP = 37,\n\tIIO_CHROMATICITY = 38,\n\tIIO_ATTENTION = 39,\n\tIIO_ALTCURRENT = 40,\n};\n\nenum iio_endian {\n\tIIO_CPU = 0,\n\tIIO_BE = 1,\n\tIIO_LE = 2,\n};\n\nenum iio_event_direction {\n\tIIO_EV_DIR_EITHER = 0,\n\tIIO_EV_DIR_RISING = 1,\n\tIIO_EV_DIR_FALLING = 2,\n\tIIO_EV_DIR_NONE = 3,\n\tIIO_EV_DIR_SINGLETAP = 4,\n\tIIO_EV_DIR_DOUBLETAP = 5,\n\tIIO_EV_DIR_FAULT_OPENWIRE = 6,\n};\n\nenum iio_event_info {\n\tIIO_EV_INFO_ENABLE = 0,\n\tIIO_EV_INFO_VALUE = 1,\n\tIIO_EV_INFO_HYSTERESIS = 2,\n\tIIO_EV_INFO_PERIOD = 3,\n\tIIO_EV_INFO_HIGH_PASS_FILTER_3DB = 4,\n\tIIO_EV_INFO_LOW_PASS_FILTER_3DB = 5,\n\tIIO_EV_INFO_TIMEOUT = 6,\n\tIIO_EV_INFO_RESET_TIMEOUT = 7,\n\tIIO_EV_INFO_TAP2_MIN_DELAY = 8,\n\tIIO_EV_INFO_RUNNING_PERIOD = 9,\n\tIIO_EV_INFO_RUNNING_COUNT = 10,\n};\n\nenum iio_event_type {\n\tIIO_EV_TYPE_THRESH = 0,\n\tIIO_EV_TYPE_MAG = 1,\n\tIIO_EV_TYPE_ROC = 2,\n\tIIO_EV_TYPE_THRESH_ADAPTIVE = 3,\n\tIIO_EV_TYPE_MAG_ADAPTIVE = 4,\n\tIIO_EV_TYPE_CHANGE = 5,\n\tIIO_EV_TYPE_MAG_REFERENCED = 6,\n\tIIO_EV_TYPE_GESTURE = 7,\n\tIIO_EV_TYPE_FAULT = 8,\n};\n\nenum iio_modifier {\n\tIIO_NO_MOD = 0,\n\tIIO_MOD_X = 1,\n\tIIO_MOD_Y = 2,\n\tIIO_MOD_Z = 3,\n\tIIO_MOD_X_AND_Y = 4,\n\tIIO_MOD_X_AND_Z = 5,\n\tIIO_MOD_Y_AND_Z = 6,\n\tIIO_MOD_X_AND_Y_AND_Z = 7,\n\tIIO_MOD_X_OR_Y = 8,\n\tIIO_MOD_X_OR_Z = 9,\n\tIIO_MOD_Y_OR_Z = 10,\n\tIIO_MOD_X_OR_Y_OR_Z = 11,\n\tIIO_MOD_LIGHT_BOTH = 12,\n\tIIO_MOD_LIGHT_IR = 13,\n\tIIO_MOD_ROOT_SUM_SQUARED_X_Y = 14,\n\tIIO_MOD_SUM_SQUARED_X_Y_Z = 15,\n\tIIO_MOD_LIGHT_CLEAR = 16,\n\tIIO_MOD_LIGHT_RED = 17,\n\tIIO_MOD_LIGHT_GREEN = 18,\n\tIIO_MOD_LIGHT_BLUE = 19,\n\tIIO_MOD_QUATERNION = 20,\n\tIIO_MOD_TEMP_AMBIENT = 21,\n\tIIO_MOD_TEMP_OBJECT = 22,\n\tIIO_MOD_NORTH_MAGN = 23,\n\tIIO_MOD_NORTH_TRUE = 24,\n\tIIO_MOD_NORTH_MAGN_TILT_COMP = 25,\n\tIIO_MOD_NORTH_TRUE_TILT_COMP = 26,\n\tIIO_MOD_RUNNING = 27,\n\tIIO_MOD_JOGGING = 28,\n\tIIO_MOD_WALKING = 29,\n\tIIO_MOD_STILL = 30,\n\tIIO_MOD_ROOT_SUM_SQUARED_X_Y_Z = 31,\n\tIIO_MOD_I = 32,\n\tIIO_MOD_Q = 33,\n\tIIO_MOD_CO2 = 34,\n\tIIO_MOD_VOC = 35,\n\tIIO_MOD_LIGHT_UV = 36,\n\tIIO_MOD_LIGHT_DUV = 37,\n\tIIO_MOD_PM1 = 38,\n\tIIO_MOD_PM2P5 = 39,\n\tIIO_MOD_PM4 = 40,\n\tIIO_MOD_PM10 = 41,\n\tIIO_MOD_ETHANOL = 42,\n\tIIO_MOD_H2 = 43,\n\tIIO_MOD_O2 = 44,\n\tIIO_MOD_LINEAR_X = 45,\n\tIIO_MOD_LINEAR_Y = 46,\n\tIIO_MOD_LINEAR_Z = 47,\n\tIIO_MOD_PITCH = 48,\n\tIIO_MOD_YAW = 49,\n\tIIO_MOD_ROLL = 50,\n\tIIO_MOD_LIGHT_UVA = 51,\n\tIIO_MOD_LIGHT_UVB = 52,\n\tIIO_MOD_RMS = 53,\n\tIIO_MOD_ACTIVE = 54,\n\tIIO_MOD_REACTIVE = 55,\n\tIIO_MOD_APPARENT = 56,\n};\n\nenum iio_shared_by {\n\tIIO_SEPARATE = 0,\n\tIIO_SHARED_BY_TYPE = 1,\n\tIIO_SHARED_BY_DIR = 2,\n\tIIO_SHARED_BY_ALL = 3,\n};\n\nenum impedance_trim {\n\tIMP_NOMINAL = 0,\n\tIMP_MINUS_2_OHMS = 1,\n\tIMP_MINUS_4_OMHS = 2,\n\tIMP_MINUS_6_OHMS = 3,\n\tIMP_MAX = 4,\n};\n\nenum imx50_pads {\n\tMX50_PAD_RESERVE0 = 0,\n\tMX50_PAD_RESERVE1 = 1,\n\tMX50_PAD_RESERVE2 = 2,\n\tMX50_PAD_RESERVE3 = 3,\n\tMX50_PAD_RESERVE4 = 4,\n\tMX50_PAD_RESERVE5 = 5,\n\tMX50_PAD_RESERVE6 = 6,\n\tMX50_PAD_RESERVE7 = 7,\n\tMX50_PAD_KEY_COL0 = 8,\n\tMX50_PAD_KEY_ROW0 = 9,\n\tMX50_PAD_KEY_COL1 = 10,\n\tMX50_PAD_KEY_ROW1 = 11,\n\tMX50_PAD_KEY_COL2 = 12,\n\tMX50_PAD_KEY_ROW2 = 13,\n\tMX50_PAD_KEY_COL3 = 14,\n\tMX50_PAD_KEY_ROW3 = 15,\n\tMX50_PAD_I2C1_SCL = 16,\n\tMX50_PAD_I2C1_SDA = 17,\n\tMX50_PAD_I2C2_SCL = 18,\n\tMX50_PAD_I2C2_SDA = 19,\n\tMX50_PAD_I2C3_SCL = 20,\n\tMX50_PAD_I2C3_SDA = 21,\n\tMX50_PAD_PWM1 = 22,\n\tMX50_PAD_PWM2 = 23,\n\tMX50_PAD_0WIRE = 24,\n\tMX50_PAD_EPITO = 25,\n\tMX50_PAD_WDOG = 26,\n\tMX50_PAD_SSI_TXFS = 27,\n\tMX50_PAD_SSI_TXC = 28,\n\tMX50_PAD_SSI_TXD = 29,\n\tMX50_PAD_SSI_RXD = 30,\n\tMX50_PAD_SSI_RXF = 31,\n\tMX50_PAD_SSI_RXC = 32,\n\tMX50_PAD_UART1_TXD = 33,\n\tMX50_PAD_UART1_RXD = 34,\n\tMX50_PAD_UART1_CTS = 35,\n\tMX50_PAD_UART1_RTS = 36,\n\tMX50_PAD_UART2_TXD = 37,\n\tMX50_PAD_UART2_RXD = 38,\n\tMX50_PAD_UART2_CTS = 39,\n\tMX50_PAD_UART2_RTS = 40,\n\tMX50_PAD_UART3_TXD = 41,\n\tMX50_PAD_UART3_RXD = 42,\n\tMX50_PAD_UART4_TXD = 43,\n\tMX50_PAD_UART4_RXD = 44,\n\tMX50_PAD_CSPI_CLK = 45,\n\tMX50_PAD_CSPI_MOSI = 46,\n\tMX50_PAD_CSPI_MISO = 47,\n\tMX50_PAD_CSPI_SS0 = 48,\n\tMX50_PAD_ECSPI1_CLK = 49,\n\tMX50_PAD_ECSPI1_MOSI = 50,\n\tMX50_PAD_ECSPI1_MISO = 51,\n\tMX50_PAD_ECSPI1_SS0 = 52,\n\tMX50_PAD_ECSPI2_CLK = 53,\n\tMX50_PAD_ECSPI2_MOSI = 54,\n\tMX50_PAD_ECSPI2_MISO = 55,\n\tMX50_PAD_ECSPI2_SS0 = 56,\n\tMX50_PAD_SD1_CLK = 57,\n\tMX50_PAD_SD1_CMD = 58,\n\tMX50_PAD_SD1_D0 = 59,\n\tMX50_PAD_SD1_D1 = 60,\n\tMX50_PAD_SD1_D2 = 61,\n\tMX50_PAD_SD1_D3 = 62,\n\tMX50_PAD_SD2_CLK = 63,\n\tMX50_PAD_SD2_CMD = 64,\n\tMX50_PAD_SD2_D0 = 65,\n\tMX50_PAD_SD2_D1 = 66,\n\tMX50_PAD_SD2_D2 = 67,\n\tMX50_PAD_SD2_D3 = 68,\n\tMX50_PAD_SD2_D4 = 69,\n\tMX50_PAD_SD2_D5 = 70,\n\tMX50_PAD_SD2_D6 = 71,\n\tMX50_PAD_SD2_D7 = 72,\n\tMX50_PAD_SD2_WP = 73,\n\tMX50_PAD_SD2_CD = 74,\n\tMX50_PAD_DISP_D0 = 75,\n\tMX50_PAD_DISP_D1 = 76,\n\tMX50_PAD_DISP_D2 = 77,\n\tMX50_PAD_DISP_D3 = 78,\n\tMX50_PAD_DISP_D4 = 79,\n\tMX50_PAD_DISP_D5 = 80,\n\tMX50_PAD_DISP_D6 = 81,\n\tMX50_PAD_DISP_D7 = 82,\n\tMX50_PAD_DISP_WR = 83,\n\tMX50_PAD_DISP_RD = 84,\n\tMX50_PAD_DISP_RS = 85,\n\tMX50_PAD_DISP_CS = 86,\n\tMX50_PAD_DISP_BUSY = 87,\n\tMX50_PAD_DISP_RESET = 88,\n\tMX50_PAD_SD3_CLK = 89,\n\tMX50_PAD_SD3_CMD = 90,\n\tMX50_PAD_SD3_D0 = 91,\n\tMX50_PAD_SD3_D1 = 92,\n\tMX50_PAD_SD3_D2 = 93,\n\tMX50_PAD_SD3_D3 = 94,\n\tMX50_PAD_SD3_D4 = 95,\n\tMX50_PAD_SD3_D5 = 96,\n\tMX50_PAD_SD3_D6 = 97,\n\tMX50_PAD_SD3_D7 = 98,\n\tMX50_PAD_SD3_WP = 99,\n\tMX50_PAD_DISP_D8 = 100,\n\tMX50_PAD_DISP_D9 = 101,\n\tMX50_PAD_DISP_D10 = 102,\n\tMX50_PAD_DISP_D11 = 103,\n\tMX50_PAD_DISP_D12 = 104,\n\tMX50_PAD_DISP_D13 = 105,\n\tMX50_PAD_DISP_D14 = 106,\n\tMX50_PAD_DISP_D15 = 107,\n\tMX50_PAD_EPDC_D0 = 108,\n\tMX50_PAD_EPDC_D1 = 109,\n\tMX50_PAD_EPDC_D2 = 110,\n\tMX50_PAD_EPDC_D3 = 111,\n\tMX50_PAD_EPDC_D4 = 112,\n\tMX50_PAD_EPDC_D5 = 113,\n\tMX50_PAD_EPDC_D6 = 114,\n\tMX50_PAD_EPDC_D7 = 115,\n\tMX50_PAD_EPDC_D8 = 116,\n\tMX50_PAD_EPDC_D9 = 117,\n\tMX50_PAD_EPDC_D10 = 118,\n\tMX50_PAD_EPDC_D11 = 119,\n\tMX50_PAD_EPDC_D12 = 120,\n\tMX50_PAD_EPDC_D13 = 121,\n\tMX50_PAD_EPDC_D14 = 122,\n\tMX50_PAD_EPDC_D15 = 123,\n\tMX50_PAD_EPDC_GDCLK = 124,\n\tMX50_PAD_EPDC_GDSP = 125,\n\tMX50_PAD_EPDC_GDOE = 126,\n\tMX50_PAD_EPDC_GDRL = 127,\n\tMX50_PAD_EPDC_SDCLK = 128,\n\tMX50_PAD_EPDC_SDOEZ = 129,\n\tMX50_PAD_EPDC_SDOED = 130,\n\tMX50_PAD_EPDC_SDOE = 131,\n\tMX50_PAD_EPDC_SDLE = 132,\n\tMX50_PAD_EPDC_SDCLKN = 133,\n\tMX50_PAD_EPDC_SDSHR = 134,\n\tMX50_PAD_EPDC_PWRCOM = 135,\n\tMX50_PAD_EPDC_PWRSTAT = 136,\n\tMX50_PAD_EPDC_PWRCTRL0 = 137,\n\tMX50_PAD_EPDC_PWRCTRL1 = 138,\n\tMX50_PAD_EPDC_PWRCTRL2 = 139,\n\tMX50_PAD_EPDC_PWRCTRL3 = 140,\n\tMX50_PAD_EPDC_VCOM0 = 141,\n\tMX50_PAD_EPDC_VCOM1 = 142,\n\tMX50_PAD_EPDC_BDR0 = 143,\n\tMX50_PAD_EPDC_BDR1 = 144,\n\tMX50_PAD_EPDC_SDCE0 = 145,\n\tMX50_PAD_EPDC_SDCE1 = 146,\n\tMX50_PAD_EPDC_SDCE2 = 147,\n\tMX50_PAD_EPDC_SDCE3 = 148,\n\tMX50_PAD_EPDC_SDCE4 = 149,\n\tMX50_PAD_EPDC_SDCE5 = 150,\n\tMX50_PAD_EIM_DA0 = 151,\n\tMX50_PAD_EIM_DA1 = 152,\n\tMX50_PAD_EIM_DA2 = 153,\n\tMX50_PAD_EIM_DA3 = 154,\n\tMX50_PAD_EIM_DA4 = 155,\n\tMX50_PAD_EIM_DA5 = 156,\n\tMX50_PAD_EIM_DA6 = 157,\n\tMX50_PAD_EIM_DA7 = 158,\n\tMX50_PAD_EIM_DA8 = 159,\n\tMX50_PAD_EIM_DA9 = 160,\n\tMX50_PAD_EIM_DA10 = 161,\n\tMX50_PAD_EIM_DA11 = 162,\n\tMX50_PAD_EIM_DA12 = 163,\n\tMX50_PAD_EIM_DA13 = 164,\n\tMX50_PAD_EIM_DA14 = 165,\n\tMX50_PAD_EIM_DA15 = 166,\n\tMX50_PAD_EIM_CS2 = 167,\n\tMX50_PAD_EIM_CS1 = 168,\n\tMX50_PAD_EIM_CS0 = 169,\n\tMX50_PAD_EIM_EB0 = 170,\n\tMX50_PAD_EIM_EB1 = 171,\n\tMX50_PAD_EIM_WAIT = 172,\n\tMX50_PAD_EIM_BCLK = 173,\n\tMX50_PAD_EIM_RDY = 174,\n\tMX50_PAD_EIM_OE = 175,\n\tMX50_PAD_EIM_RW = 176,\n\tMX50_PAD_EIM_LBA = 177,\n\tMX50_PAD_EIM_CRE = 178,\n};\n\nenum imx51_pads {\n\tMX51_PAD_RESERVE0 = 0,\n\tMX51_PAD_RESERVE1 = 1,\n\tMX51_PAD_RESERVE2 = 2,\n\tMX51_PAD_RESERVE3 = 3,\n\tMX51_PAD_RESERVE4 = 4,\n\tMX51_PAD_RESERVE5 = 5,\n\tMX51_PAD_RESERVE6 = 6,\n\tMX51_PAD_EIM_DA0 = 7,\n\tMX51_PAD_EIM_DA1 = 8,\n\tMX51_PAD_EIM_DA2 = 9,\n\tMX51_PAD_EIM_DA3 = 10,\n\tMX51_PAD_EIM_DA4 = 11,\n\tMX51_PAD_EIM_DA5 = 12,\n\tMX51_PAD_EIM_DA6 = 13,\n\tMX51_PAD_EIM_DA7 = 14,\n\tMX51_PAD_EIM_DA8 = 15,\n\tMX51_PAD_EIM_DA9 = 16,\n\tMX51_PAD_EIM_DA10 = 17,\n\tMX51_PAD_EIM_DA11 = 18,\n\tMX51_PAD_EIM_DA12 = 19,\n\tMX51_PAD_EIM_DA13 = 20,\n\tMX51_PAD_EIM_DA14 = 21,\n\tMX51_PAD_EIM_DA15 = 22,\n\tMX51_PAD_EIM_D16 = 23,\n\tMX51_PAD_EIM_D17 = 24,\n\tMX51_PAD_EIM_D18 = 25,\n\tMX51_PAD_EIM_D19 = 26,\n\tMX51_PAD_EIM_D20 = 27,\n\tMX51_PAD_EIM_D21 = 28,\n\tMX51_PAD_EIM_D22 = 29,\n\tMX51_PAD_EIM_D23 = 30,\n\tMX51_PAD_EIM_D24 = 31,\n\tMX51_PAD_EIM_D25 = 32,\n\tMX51_PAD_EIM_D26 = 33,\n\tMX51_PAD_EIM_D27 = 34,\n\tMX51_PAD_EIM_D28 = 35,\n\tMX51_PAD_EIM_D29 = 36,\n\tMX51_PAD_EIM_D30 = 37,\n\tMX51_PAD_EIM_D31 = 38,\n\tMX51_PAD_EIM_A16 = 39,\n\tMX51_PAD_EIM_A17 = 40,\n\tMX51_PAD_EIM_A18 = 41,\n\tMX51_PAD_EIM_A19 = 42,\n\tMX51_PAD_EIM_A20 = 43,\n\tMX51_PAD_EIM_A21 = 44,\n\tMX51_PAD_EIM_A22 = 45,\n\tMX51_PAD_EIM_A23 = 46,\n\tMX51_PAD_EIM_A24 = 47,\n\tMX51_PAD_EIM_A25 = 48,\n\tMX51_PAD_EIM_A26 = 49,\n\tMX51_PAD_EIM_A27 = 50,\n\tMX51_PAD_EIM_EB0 = 51,\n\tMX51_PAD_EIM_EB1 = 52,\n\tMX51_PAD_EIM_EB2 = 53,\n\tMX51_PAD_EIM_EB3 = 54,\n\tMX51_PAD_EIM_OE = 55,\n\tMX51_PAD_EIM_CS0 = 56,\n\tMX51_PAD_EIM_CS1 = 57,\n\tMX51_PAD_EIM_CS2 = 58,\n\tMX51_PAD_EIM_CS3 = 59,\n\tMX51_PAD_EIM_CS4 = 60,\n\tMX51_PAD_EIM_CS5 = 61,\n\tMX51_PAD_EIM_DTACK = 62,\n\tMX51_PAD_EIM_LBA = 63,\n\tMX51_PAD_EIM_CRE = 64,\n\tMX51_PAD_DRAM_CS1 = 65,\n\tMX51_PAD_NANDF_WE_B = 66,\n\tMX51_PAD_NANDF_RE_B = 67,\n\tMX51_PAD_NANDF_ALE = 68,\n\tMX51_PAD_NANDF_CLE = 69,\n\tMX51_PAD_NANDF_WP_B = 70,\n\tMX51_PAD_NANDF_RB0 = 71,\n\tMX51_PAD_NANDF_RB1 = 72,\n\tMX51_PAD_NANDF_RB2 = 73,\n\tMX51_PAD_NANDF_RB3 = 74,\n\tMX51_PAD_GPIO_NAND = 75,\n\tMX51_PAD_NANDF_CS0 = 76,\n\tMX51_PAD_NANDF_CS1 = 77,\n\tMX51_PAD_NANDF_CS2 = 78,\n\tMX51_PAD_NANDF_CS3 = 79,\n\tMX51_PAD_NANDF_CS4 = 80,\n\tMX51_PAD_NANDF_CS5 = 81,\n\tMX51_PAD_NANDF_CS6 = 82,\n\tMX51_PAD_NANDF_CS7 = 83,\n\tMX51_PAD_NANDF_RDY_INT = 84,\n\tMX51_PAD_NANDF_D15 = 85,\n\tMX51_PAD_NANDF_D14 = 86,\n\tMX51_PAD_NANDF_D13 = 87,\n\tMX51_PAD_NANDF_D12 = 88,\n\tMX51_PAD_NANDF_D11 = 89,\n\tMX51_PAD_NANDF_D10 = 90,\n\tMX51_PAD_NANDF_D9 = 91,\n\tMX51_PAD_NANDF_D8 = 92,\n\tMX51_PAD_NANDF_D7 = 93,\n\tMX51_PAD_NANDF_D6 = 94,\n\tMX51_PAD_NANDF_D5 = 95,\n\tMX51_PAD_NANDF_D4 = 96,\n\tMX51_PAD_NANDF_D3 = 97,\n\tMX51_PAD_NANDF_D2 = 98,\n\tMX51_PAD_NANDF_D1 = 99,\n\tMX51_PAD_NANDF_D0 = 100,\n\tMX51_PAD_CSI1_D8 = 101,\n\tMX51_PAD_CSI1_D9 = 102,\n\tMX51_PAD_CSI1_D10 = 103,\n\tMX51_PAD_CSI1_D11 = 104,\n\tMX51_PAD_CSI1_D12 = 105,\n\tMX51_PAD_CSI1_D13 = 106,\n\tMX51_PAD_CSI1_D14 = 107,\n\tMX51_PAD_CSI1_D15 = 108,\n\tMX51_PAD_CSI1_D16 = 109,\n\tMX51_PAD_CSI1_D17 = 110,\n\tMX51_PAD_CSI1_D18 = 111,\n\tMX51_PAD_CSI1_D19 = 112,\n\tMX51_PAD_CSI1_VSYNC = 113,\n\tMX51_PAD_CSI1_HSYNC = 114,\n\tMX51_PAD_CSI2_D12 = 115,\n\tMX51_PAD_CSI2_D13 = 116,\n\tMX51_PAD_CSI2_D14 = 117,\n\tMX51_PAD_CSI2_D15 = 118,\n\tMX51_PAD_CSI2_D16 = 119,\n\tMX51_PAD_CSI2_D17 = 120,\n\tMX51_PAD_CSI2_D18 = 121,\n\tMX51_PAD_CSI2_D19 = 122,\n\tMX51_PAD_CSI2_VSYNC = 123,\n\tMX51_PAD_CSI2_HSYNC = 124,\n\tMX51_PAD_CSI2_PIXCLK = 125,\n\tMX51_PAD_I2C1_CLK = 126,\n\tMX51_PAD_I2C1_DAT = 127,\n\tMX51_PAD_AUD3_BB_TXD = 128,\n\tMX51_PAD_AUD3_BB_RXD = 129,\n\tMX51_PAD_AUD3_BB_CK = 130,\n\tMX51_PAD_AUD3_BB_FS = 131,\n\tMX51_PAD_CSPI1_MOSI = 132,\n\tMX51_PAD_CSPI1_MISO = 133,\n\tMX51_PAD_CSPI1_SS0 = 134,\n\tMX51_PAD_CSPI1_SS1 = 135,\n\tMX51_PAD_CSPI1_RDY = 136,\n\tMX51_PAD_CSPI1_SCLK = 137,\n\tMX51_PAD_UART1_RXD = 138,\n\tMX51_PAD_UART1_TXD = 139,\n\tMX51_PAD_UART1_RTS = 140,\n\tMX51_PAD_UART1_CTS = 141,\n\tMX51_PAD_UART2_RXD = 142,\n\tMX51_PAD_UART2_TXD = 143,\n\tMX51_PAD_UART3_RXD = 144,\n\tMX51_PAD_UART3_TXD = 145,\n\tMX51_PAD_OWIRE_LINE = 146,\n\tMX51_PAD_KEY_ROW0 = 147,\n\tMX51_PAD_KEY_ROW1 = 148,\n\tMX51_PAD_KEY_ROW2 = 149,\n\tMX51_PAD_KEY_ROW3 = 150,\n\tMX51_PAD_KEY_COL0 = 151,\n\tMX51_PAD_KEY_COL1 = 152,\n\tMX51_PAD_KEY_COL2 = 153,\n\tMX51_PAD_KEY_COL3 = 154,\n\tMX51_PAD_KEY_COL4 = 155,\n\tMX51_PAD_KEY_COL5 = 156,\n\tMX51_PAD_RESERVE7 = 157,\n\tMX51_PAD_USBH1_CLK = 158,\n\tMX51_PAD_USBH1_DIR = 159,\n\tMX51_PAD_USBH1_STP = 160,\n\tMX51_PAD_USBH1_NXT = 161,\n\tMX51_PAD_USBH1_DATA0 = 162,\n\tMX51_PAD_USBH1_DATA1 = 163,\n\tMX51_PAD_USBH1_DATA2 = 164,\n\tMX51_PAD_USBH1_DATA3 = 165,\n\tMX51_PAD_USBH1_DATA4 = 166,\n\tMX51_PAD_USBH1_DATA5 = 167,\n\tMX51_PAD_USBH1_DATA6 = 168,\n\tMX51_PAD_USBH1_DATA7 = 169,\n\tMX51_PAD_DI1_PIN11 = 170,\n\tMX51_PAD_DI1_PIN12 = 171,\n\tMX51_PAD_DI1_PIN13 = 172,\n\tMX51_PAD_DI1_D0_CS = 173,\n\tMX51_PAD_DI1_D1_CS = 174,\n\tMX51_PAD_DISPB2_SER_DIN = 175,\n\tMX51_PAD_DISPB2_SER_DIO = 176,\n\tMX51_PAD_DISPB2_SER_CLK = 177,\n\tMX51_PAD_DISPB2_SER_RS = 178,\n\tMX51_PAD_DISP1_DAT0 = 179,\n\tMX51_PAD_DISP1_DAT1 = 180,\n\tMX51_PAD_DISP1_DAT2 = 181,\n\tMX51_PAD_DISP1_DAT3 = 182,\n\tMX51_PAD_DISP1_DAT4 = 183,\n\tMX51_PAD_DISP1_DAT5 = 184,\n\tMX51_PAD_DISP1_DAT6 = 185,\n\tMX51_PAD_DISP1_DAT7 = 186,\n\tMX51_PAD_DISP1_DAT8 = 187,\n\tMX51_PAD_DISP1_DAT9 = 188,\n\tMX51_PAD_DISP1_DAT10 = 189,\n\tMX51_PAD_DISP1_DAT11 = 190,\n\tMX51_PAD_DISP1_DAT12 = 191,\n\tMX51_PAD_DISP1_DAT13 = 192,\n\tMX51_PAD_DISP1_DAT14 = 193,\n\tMX51_PAD_DISP1_DAT15 = 194,\n\tMX51_PAD_DISP1_DAT16 = 195,\n\tMX51_PAD_DISP1_DAT17 = 196,\n\tMX51_PAD_DISP1_DAT18 = 197,\n\tMX51_PAD_DISP1_DAT19 = 198,\n\tMX51_PAD_DISP1_DAT20 = 199,\n\tMX51_PAD_DISP1_DAT21 = 200,\n\tMX51_PAD_DISP1_DAT22 = 201,\n\tMX51_PAD_DISP1_DAT23 = 202,\n\tMX51_PAD_DI1_PIN3 = 203,\n\tMX51_PAD_DI1_PIN2 = 204,\n\tMX51_PAD_RESERVE8 = 205,\n\tMX51_PAD_DI_GP2 = 206,\n\tMX51_PAD_DI_GP3 = 207,\n\tMX51_PAD_DI2_PIN4 = 208,\n\tMX51_PAD_DI2_PIN2 = 209,\n\tMX51_PAD_DI2_PIN3 = 210,\n\tMX51_PAD_DI2_DISP_CLK = 211,\n\tMX51_PAD_DI_GP4 = 212,\n\tMX51_PAD_DISP2_DAT0 = 213,\n\tMX51_PAD_DISP2_DAT1 = 214,\n\tMX51_PAD_DISP2_DAT2 = 215,\n\tMX51_PAD_DISP2_DAT3 = 216,\n\tMX51_PAD_DISP2_DAT4 = 217,\n\tMX51_PAD_DISP2_DAT5 = 218,\n\tMX51_PAD_DISP2_DAT6 = 219,\n\tMX51_PAD_DISP2_DAT7 = 220,\n\tMX51_PAD_DISP2_DAT8 = 221,\n\tMX51_PAD_DISP2_DAT9 = 222,\n\tMX51_PAD_DISP2_DAT10 = 223,\n\tMX51_PAD_DISP2_DAT11 = 224,\n\tMX51_PAD_DISP2_DAT12 = 225,\n\tMX51_PAD_DISP2_DAT13 = 226,\n\tMX51_PAD_DISP2_DAT14 = 227,\n\tMX51_PAD_DISP2_DAT15 = 228,\n\tMX51_PAD_SD1_CMD = 229,\n\tMX51_PAD_SD1_CLK = 230,\n\tMX51_PAD_SD1_DATA0 = 231,\n\tMX51_PAD_SD1_DATA1 = 232,\n\tMX51_PAD_SD1_DATA2 = 233,\n\tMX51_PAD_SD1_DATA3 = 234,\n\tMX51_PAD_GPIO1_0 = 235,\n\tMX51_PAD_GPIO1_1 = 236,\n\tMX51_PAD_SD2_CMD = 237,\n\tMX51_PAD_SD2_CLK = 238,\n\tMX51_PAD_SD2_DATA0 = 239,\n\tMX51_PAD_SD2_DATA1 = 240,\n\tMX51_PAD_SD2_DATA2 = 241,\n\tMX51_PAD_SD2_DATA3 = 242,\n\tMX51_PAD_GPIO1_2 = 243,\n\tMX51_PAD_GPIO1_3 = 244,\n\tMX51_PAD_PMIC_INT_REQ = 245,\n\tMX51_PAD_GPIO1_4 = 246,\n\tMX51_PAD_GPIO1_5 = 247,\n\tMX51_PAD_GPIO1_6 = 248,\n\tMX51_PAD_GPIO1_7 = 249,\n\tMX51_PAD_GPIO1_8 = 250,\n\tMX51_PAD_GPIO1_9 = 251,\n\tMX51_PAD_RESERVE9 = 252,\n\tMX51_PAD_RESERVE10 = 253,\n\tMX51_PAD_RESERVE11 = 254,\n\tMX51_PAD_RESERVE12 = 255,\n\tMX51_PAD_RESERVE13 = 256,\n\tMX51_PAD_RESERVE14 = 257,\n\tMX51_PAD_RESERVE15 = 258,\n\tMX51_PAD_RESERVE16 = 259,\n\tMX51_PAD_RESERVE17 = 260,\n\tMX51_PAD_RESERVE18 = 261,\n\tMX51_PAD_RESERVE19 = 262,\n\tMX51_PAD_RESERVE20 = 263,\n\tMX51_PAD_RESERVE21 = 264,\n\tMX51_PAD_RESERVE22 = 265,\n\tMX51_PAD_RESERVE23 = 266,\n\tMX51_PAD_RESERVE24 = 267,\n\tMX51_PAD_RESERVE25 = 268,\n\tMX51_PAD_RESERVE26 = 269,\n\tMX51_PAD_RESERVE27 = 270,\n\tMX51_PAD_RESERVE28 = 271,\n\tMX51_PAD_RESERVE29 = 272,\n\tMX51_PAD_RESERVE30 = 273,\n\tMX51_PAD_RESERVE31 = 274,\n\tMX51_PAD_RESERVE32 = 275,\n\tMX51_PAD_RESERVE33 = 276,\n\tMX51_PAD_RESERVE34 = 277,\n\tMX51_PAD_RESERVE35 = 278,\n\tMX51_PAD_RESERVE36 = 279,\n\tMX51_PAD_RESERVE37 = 280,\n\tMX51_PAD_RESERVE38 = 281,\n\tMX51_PAD_RESERVE39 = 282,\n\tMX51_PAD_RESERVE40 = 283,\n\tMX51_PAD_RESERVE41 = 284,\n\tMX51_PAD_RESERVE42 = 285,\n\tMX51_PAD_RESERVE43 = 286,\n\tMX51_PAD_RESERVE44 = 287,\n\tMX51_PAD_RESERVE45 = 288,\n\tMX51_PAD_RESERVE46 = 289,\n\tMX51_PAD_RESERVE47 = 290,\n\tMX51_PAD_RESERVE48 = 291,\n\tMX51_PAD_RESERVE49 = 292,\n\tMX51_PAD_RESERVE50 = 293,\n\tMX51_PAD_RESERVE51 = 294,\n\tMX51_PAD_RESERVE52 = 295,\n\tMX51_PAD_RESERVE53 = 296,\n\tMX51_PAD_RESERVE54 = 297,\n\tMX51_PAD_RESERVE55 = 298,\n\tMX51_PAD_RESERVE56 = 299,\n\tMX51_PAD_RESERVE57 = 300,\n\tMX51_PAD_RESERVE58 = 301,\n\tMX51_PAD_RESERVE59 = 302,\n\tMX51_PAD_RESERVE60 = 303,\n\tMX51_PAD_RESERVE61 = 304,\n\tMX51_PAD_RESERVE62 = 305,\n\tMX51_PAD_RESERVE63 = 306,\n\tMX51_PAD_RESERVE64 = 307,\n\tMX51_PAD_RESERVE65 = 308,\n\tMX51_PAD_RESERVE66 = 309,\n\tMX51_PAD_RESERVE67 = 310,\n\tMX51_PAD_RESERVE68 = 311,\n\tMX51_PAD_RESERVE69 = 312,\n\tMX51_PAD_RESERVE70 = 313,\n\tMX51_PAD_RESERVE71 = 314,\n\tMX51_PAD_RESERVE72 = 315,\n\tMX51_PAD_RESERVE73 = 316,\n\tMX51_PAD_RESERVE74 = 317,\n\tMX51_PAD_RESERVE75 = 318,\n\tMX51_PAD_RESERVE76 = 319,\n\tMX51_PAD_RESERVE77 = 320,\n\tMX51_PAD_RESERVE78 = 321,\n\tMX51_PAD_RESERVE79 = 322,\n\tMX51_PAD_RESERVE80 = 323,\n\tMX51_PAD_RESERVE81 = 324,\n\tMX51_PAD_RESERVE82 = 325,\n\tMX51_PAD_RESERVE83 = 326,\n\tMX51_PAD_RESERVE84 = 327,\n\tMX51_PAD_RESERVE85 = 328,\n\tMX51_PAD_RESERVE86 = 329,\n\tMX51_PAD_RESERVE87 = 330,\n\tMX51_PAD_RESERVE88 = 331,\n\tMX51_PAD_RESERVE89 = 332,\n\tMX51_PAD_RESERVE90 = 333,\n\tMX51_PAD_RESERVE91 = 334,\n\tMX51_PAD_RESERVE92 = 335,\n\tMX51_PAD_RESERVE93 = 336,\n\tMX51_PAD_RESERVE94 = 337,\n\tMX51_PAD_RESERVE95 = 338,\n\tMX51_PAD_RESERVE96 = 339,\n\tMX51_PAD_RESERVE97 = 340,\n\tMX51_PAD_RESERVE98 = 341,\n\tMX51_PAD_RESERVE99 = 342,\n\tMX51_PAD_RESERVE100 = 343,\n\tMX51_PAD_RESERVE101 = 344,\n\tMX51_PAD_RESERVE102 = 345,\n\tMX51_PAD_RESERVE103 = 346,\n\tMX51_PAD_RESERVE104 = 347,\n\tMX51_PAD_RESERVE105 = 348,\n\tMX51_PAD_RESERVE106 = 349,\n\tMX51_PAD_RESERVE107 = 350,\n\tMX51_PAD_RESERVE108 = 351,\n\tMX51_PAD_RESERVE109 = 352,\n\tMX51_PAD_RESERVE110 = 353,\n\tMX51_PAD_RESERVE111 = 354,\n\tMX51_PAD_RESERVE112 = 355,\n\tMX51_PAD_RESERVE113 = 356,\n\tMX51_PAD_RESERVE114 = 357,\n\tMX51_PAD_RESERVE115 = 358,\n\tMX51_PAD_RESERVE116 = 359,\n\tMX51_PAD_RESERVE117 = 360,\n\tMX51_PAD_RESERVE118 = 361,\n\tMX51_PAD_RESERVE119 = 362,\n\tMX51_PAD_RESERVE120 = 363,\n\tMX51_PAD_RESERVE121 = 364,\n\tMX51_PAD_CSI1_PIXCLK = 365,\n\tMX51_PAD_CSI1_MCLK = 366,\n};\n\nenum imx53_pads {\n\tMX53_PAD_RESERVE0 = 0,\n\tMX53_PAD_RESERVE1 = 1,\n\tMX53_PAD_RESERVE2 = 2,\n\tMX53_PAD_RESERVE3 = 3,\n\tMX53_PAD_RESERVE4 = 4,\n\tMX53_PAD_RESERVE5 = 5,\n\tMX53_PAD_RESERVE6 = 6,\n\tMX53_PAD_RESERVE7 = 7,\n\tMX53_PAD_GPIO_19 = 8,\n\tMX53_PAD_KEY_COL0 = 9,\n\tMX53_PAD_KEY_ROW0 = 10,\n\tMX53_PAD_KEY_COL1 = 11,\n\tMX53_PAD_KEY_ROW1 = 12,\n\tMX53_PAD_KEY_COL2 = 13,\n\tMX53_PAD_KEY_ROW2 = 14,\n\tMX53_PAD_KEY_COL3 = 15,\n\tMX53_PAD_KEY_ROW3 = 16,\n\tMX53_PAD_KEY_COL4 = 17,\n\tMX53_PAD_KEY_ROW4 = 18,\n\tMX53_PAD_DI0_DISP_CLK = 19,\n\tMX53_PAD_DI0_PIN15 = 20,\n\tMX53_PAD_DI0_PIN2 = 21,\n\tMX53_PAD_DI0_PIN3 = 22,\n\tMX53_PAD_DI0_PIN4 = 23,\n\tMX53_PAD_DISP0_DAT0 = 24,\n\tMX53_PAD_DISP0_DAT1 = 25,\n\tMX53_PAD_DISP0_DAT2 = 26,\n\tMX53_PAD_DISP0_DAT3 = 27,\n\tMX53_PAD_DISP0_DAT4 = 28,\n\tMX53_PAD_DISP0_DAT5 = 29,\n\tMX53_PAD_DISP0_DAT6 = 30,\n\tMX53_PAD_DISP0_DAT7 = 31,\n\tMX53_PAD_DISP0_DAT8 = 32,\n\tMX53_PAD_DISP0_DAT9 = 33,\n\tMX53_PAD_DISP0_DAT10 = 34,\n\tMX53_PAD_DISP0_DAT11 = 35,\n\tMX53_PAD_DISP0_DAT12 = 36,\n\tMX53_PAD_DISP0_DAT13 = 37,\n\tMX53_PAD_DISP0_DAT14 = 38,\n\tMX53_PAD_DISP0_DAT15 = 39,\n\tMX53_PAD_DISP0_DAT16 = 40,\n\tMX53_PAD_DISP0_DAT17 = 41,\n\tMX53_PAD_DISP0_DAT18 = 42,\n\tMX53_PAD_DISP0_DAT19 = 43,\n\tMX53_PAD_DISP0_DAT20 = 44,\n\tMX53_PAD_DISP0_DAT21 = 45,\n\tMX53_PAD_DISP0_DAT22 = 46,\n\tMX53_PAD_DISP0_DAT23 = 47,\n\tMX53_PAD_CSI0_PIXCLK = 48,\n\tMX53_PAD_CSI0_MCLK = 49,\n\tMX53_PAD_CSI0_DATA_EN = 50,\n\tMX53_PAD_CSI0_VSYNC = 51,\n\tMX53_PAD_CSI0_DAT4 = 52,\n\tMX53_PAD_CSI0_DAT5 = 53,\n\tMX53_PAD_CSI0_DAT6 = 54,\n\tMX53_PAD_CSI0_DAT7 = 55,\n\tMX53_PAD_CSI0_DAT8 = 56,\n\tMX53_PAD_CSI0_DAT9 = 57,\n\tMX53_PAD_CSI0_DAT10 = 58,\n\tMX53_PAD_CSI0_DAT11 = 59,\n\tMX53_PAD_CSI0_DAT12 = 60,\n\tMX53_PAD_CSI0_DAT13 = 61,\n\tMX53_PAD_CSI0_DAT14 = 62,\n\tMX53_PAD_CSI0_DAT15 = 63,\n\tMX53_PAD_CSI0_DAT16 = 64,\n\tMX53_PAD_CSI0_DAT17 = 65,\n\tMX53_PAD_CSI0_DAT18 = 66,\n\tMX53_PAD_CSI0_DAT19 = 67,\n\tMX53_PAD_EIM_A25 = 68,\n\tMX53_PAD_EIM_EB2 = 69,\n\tMX53_PAD_EIM_D16 = 70,\n\tMX53_PAD_EIM_D17 = 71,\n\tMX53_PAD_EIM_D18 = 72,\n\tMX53_PAD_EIM_D19 = 73,\n\tMX53_PAD_EIM_D20 = 74,\n\tMX53_PAD_EIM_D21 = 75,\n\tMX53_PAD_EIM_D22 = 76,\n\tMX53_PAD_EIM_D23 = 77,\n\tMX53_PAD_EIM_EB3 = 78,\n\tMX53_PAD_EIM_D24 = 79,\n\tMX53_PAD_EIM_D25 = 80,\n\tMX53_PAD_EIM_D26 = 81,\n\tMX53_PAD_EIM_D27 = 82,\n\tMX53_PAD_EIM_D28 = 83,\n\tMX53_PAD_EIM_D29 = 84,\n\tMX53_PAD_EIM_D30 = 85,\n\tMX53_PAD_EIM_D31 = 86,\n\tMX53_PAD_EIM_A24 = 87,\n\tMX53_PAD_EIM_A23 = 88,\n\tMX53_PAD_EIM_A22 = 89,\n\tMX53_PAD_EIM_A21 = 90,\n\tMX53_PAD_EIM_A20 = 91,\n\tMX53_PAD_EIM_A19 = 92,\n\tMX53_PAD_EIM_A18 = 93,\n\tMX53_PAD_EIM_A17 = 94,\n\tMX53_PAD_EIM_A16 = 95,\n\tMX53_PAD_EIM_CS0 = 96,\n\tMX53_PAD_EIM_CS1 = 97,\n\tMX53_PAD_EIM_OE = 98,\n\tMX53_PAD_EIM_RW = 99,\n\tMX53_PAD_EIM_LBA = 100,\n\tMX53_PAD_EIM_EB0 = 101,\n\tMX53_PAD_EIM_EB1 = 102,\n\tMX53_PAD_EIM_DA0 = 103,\n\tMX53_PAD_EIM_DA1 = 104,\n\tMX53_PAD_EIM_DA2 = 105,\n\tMX53_PAD_EIM_DA3 = 106,\n\tMX53_PAD_EIM_DA4 = 107,\n\tMX53_PAD_EIM_DA5 = 108,\n\tMX53_PAD_EIM_DA6 = 109,\n\tMX53_PAD_EIM_DA7 = 110,\n\tMX53_PAD_EIM_DA8 = 111,\n\tMX53_PAD_EIM_DA9 = 112,\n\tMX53_PAD_EIM_DA10 = 113,\n\tMX53_PAD_EIM_DA11 = 114,\n\tMX53_PAD_EIM_DA12 = 115,\n\tMX53_PAD_EIM_DA13 = 116,\n\tMX53_PAD_EIM_DA14 = 117,\n\tMX53_PAD_EIM_DA15 = 118,\n\tMX53_PAD_NANDF_WE_B = 119,\n\tMX53_PAD_NANDF_RE_B = 120,\n\tMX53_PAD_EIM_WAIT = 121,\n\tMX53_PAD_RESERVE8 = 122,\n\tMX53_PAD_LVDS1_TX3_P = 123,\n\tMX53_PAD_LVDS1_TX2_P = 124,\n\tMX53_PAD_LVDS1_CLK_P = 125,\n\tMX53_PAD_LVDS1_TX1_P = 126,\n\tMX53_PAD_LVDS1_TX0_P = 127,\n\tMX53_PAD_LVDS0_TX3_P = 128,\n\tMX53_PAD_LVDS0_CLK_P = 129,\n\tMX53_PAD_LVDS0_TX2_P = 130,\n\tMX53_PAD_LVDS0_TX1_P = 131,\n\tMX53_PAD_LVDS0_TX0_P = 132,\n\tMX53_PAD_GPIO_10 = 133,\n\tMX53_PAD_GPIO_11 = 134,\n\tMX53_PAD_GPIO_12 = 135,\n\tMX53_PAD_GPIO_13 = 136,\n\tMX53_PAD_GPIO_14 = 137,\n\tMX53_PAD_NANDF_CLE = 138,\n\tMX53_PAD_NANDF_ALE = 139,\n\tMX53_PAD_NANDF_WP_B = 140,\n\tMX53_PAD_NANDF_RB0 = 141,\n\tMX53_PAD_NANDF_CS0 = 142,\n\tMX53_PAD_NANDF_CS1 = 143,\n\tMX53_PAD_NANDF_CS2 = 144,\n\tMX53_PAD_NANDF_CS3 = 145,\n\tMX53_PAD_FEC_MDIO = 146,\n\tMX53_PAD_FEC_REF_CLK = 147,\n\tMX53_PAD_FEC_RX_ER = 148,\n\tMX53_PAD_FEC_CRS_DV = 149,\n\tMX53_PAD_FEC_RXD1 = 150,\n\tMX53_PAD_FEC_RXD0 = 151,\n\tMX53_PAD_FEC_TX_EN = 152,\n\tMX53_PAD_FEC_TXD1 = 153,\n\tMX53_PAD_FEC_TXD0 = 154,\n\tMX53_PAD_FEC_MDC = 155,\n\tMX53_PAD_PATA_DIOW = 156,\n\tMX53_PAD_PATA_DMACK = 157,\n\tMX53_PAD_PATA_DMARQ = 158,\n\tMX53_PAD_PATA_BUFFER_EN = 159,\n\tMX53_PAD_PATA_INTRQ = 160,\n\tMX53_PAD_PATA_DIOR = 161,\n\tMX53_PAD_PATA_RESET_B = 162,\n\tMX53_PAD_PATA_IORDY = 163,\n\tMX53_PAD_PATA_DA_0 = 164,\n\tMX53_PAD_PATA_DA_1 = 165,\n\tMX53_PAD_PATA_DA_2 = 166,\n\tMX53_PAD_PATA_CS_0 = 167,\n\tMX53_PAD_PATA_CS_1 = 168,\n\tMX53_PAD_PATA_DATA0 = 169,\n\tMX53_PAD_PATA_DATA1 = 170,\n\tMX53_PAD_PATA_DATA2 = 171,\n\tMX53_PAD_PATA_DATA3 = 172,\n\tMX53_PAD_PATA_DATA4 = 173,\n\tMX53_PAD_PATA_DATA5 = 174,\n\tMX53_PAD_PATA_DATA6 = 175,\n\tMX53_PAD_PATA_DATA7 = 176,\n\tMX53_PAD_PATA_DATA8 = 177,\n\tMX53_PAD_PATA_DATA9 = 178,\n\tMX53_PAD_PATA_DATA10 = 179,\n\tMX53_PAD_PATA_DATA11 = 180,\n\tMX53_PAD_PATA_DATA12 = 181,\n\tMX53_PAD_PATA_DATA13 = 182,\n\tMX53_PAD_PATA_DATA14 = 183,\n\tMX53_PAD_PATA_DATA15 = 184,\n\tMX53_PAD_SD1_DATA0 = 185,\n\tMX53_PAD_SD1_DATA1 = 186,\n\tMX53_PAD_SD1_CMD = 187,\n\tMX53_PAD_SD1_DATA2 = 188,\n\tMX53_PAD_SD1_CLK = 189,\n\tMX53_PAD_SD1_DATA3 = 190,\n\tMX53_PAD_SD2_CLK = 191,\n\tMX53_PAD_SD2_CMD = 192,\n\tMX53_PAD_SD2_DATA3 = 193,\n\tMX53_PAD_SD2_DATA2 = 194,\n\tMX53_PAD_SD2_DATA1 = 195,\n\tMX53_PAD_SD2_DATA0 = 196,\n\tMX53_PAD_GPIO_0 = 197,\n\tMX53_PAD_GPIO_1 = 198,\n\tMX53_PAD_GPIO_9 = 199,\n\tMX53_PAD_GPIO_3 = 200,\n\tMX53_PAD_GPIO_6 = 201,\n\tMX53_PAD_GPIO_2 = 202,\n\tMX53_PAD_GPIO_4 = 203,\n\tMX53_PAD_GPIO_5 = 204,\n\tMX53_PAD_GPIO_7 = 205,\n\tMX53_PAD_GPIO_8 = 206,\n\tMX53_PAD_GPIO_16 = 207,\n\tMX53_PAD_GPIO_17 = 208,\n\tMX53_PAD_GPIO_18 = 209,\n};\n\nenum imx6dl_pads {\n\tMX6DL_PAD_RESERVE0 = 0,\n\tMX6DL_PAD_RESERVE1 = 1,\n\tMX6DL_PAD_RESERVE2 = 2,\n\tMX6DL_PAD_RESERVE3 = 3,\n\tMX6DL_PAD_RESERVE4 = 4,\n\tMX6DL_PAD_RESERVE5 = 5,\n\tMX6DL_PAD_RESERVE6 = 6,\n\tMX6DL_PAD_RESERVE7 = 7,\n\tMX6DL_PAD_RESERVE8 = 8,\n\tMX6DL_PAD_RESERVE9 = 9,\n\tMX6DL_PAD_RESERVE10 = 10,\n\tMX6DL_PAD_RESERVE11 = 11,\n\tMX6DL_PAD_RESERVE12 = 12,\n\tMX6DL_PAD_RESERVE13 = 13,\n\tMX6DL_PAD_RESERVE14 = 14,\n\tMX6DL_PAD_RESERVE15 = 15,\n\tMX6DL_PAD_RESERVE16 = 16,\n\tMX6DL_PAD_RESERVE17 = 17,\n\tMX6DL_PAD_RESERVE18 = 18,\n\tMX6DL_PAD_CSI0_DAT10 = 19,\n\tMX6DL_PAD_CSI0_DAT11 = 20,\n\tMX6DL_PAD_CSI0_DAT12 = 21,\n\tMX6DL_PAD_CSI0_DAT13 = 22,\n\tMX6DL_PAD_CSI0_DAT14 = 23,\n\tMX6DL_PAD_CSI0_DAT15 = 24,\n\tMX6DL_PAD_CSI0_DAT16 = 25,\n\tMX6DL_PAD_CSI0_DAT17 = 26,\n\tMX6DL_PAD_CSI0_DAT18 = 27,\n\tMX6DL_PAD_CSI0_DAT19 = 28,\n\tMX6DL_PAD_CSI0_DAT4 = 29,\n\tMX6DL_PAD_CSI0_DAT5 = 30,\n\tMX6DL_PAD_CSI0_DAT6 = 31,\n\tMX6DL_PAD_CSI0_DAT7 = 32,\n\tMX6DL_PAD_CSI0_DAT8 = 33,\n\tMX6DL_PAD_CSI0_DAT9 = 34,\n\tMX6DL_PAD_CSI0_DATA_EN = 35,\n\tMX6DL_PAD_CSI0_MCLK = 36,\n\tMX6DL_PAD_CSI0_PIXCLK = 37,\n\tMX6DL_PAD_CSI0_VSYNC = 38,\n\tMX6DL_PAD_DI0_DISP_CLK = 39,\n\tMX6DL_PAD_DI0_PIN15 = 40,\n\tMX6DL_PAD_DI0_PIN2 = 41,\n\tMX6DL_PAD_DI0_PIN3 = 42,\n\tMX6DL_PAD_DI0_PIN4 = 43,\n\tMX6DL_PAD_DISP0_DAT0 = 44,\n\tMX6DL_PAD_DISP0_DAT1 = 45,\n\tMX6DL_PAD_DISP0_DAT10 = 46,\n\tMX6DL_PAD_DISP0_DAT11 = 47,\n\tMX6DL_PAD_DISP0_DAT12 = 48,\n\tMX6DL_PAD_DISP0_DAT13 = 49,\n\tMX6DL_PAD_DISP0_DAT14 = 50,\n\tMX6DL_PAD_DISP0_DAT15 = 51,\n\tMX6DL_PAD_DISP0_DAT16 = 52,\n\tMX6DL_PAD_DISP0_DAT17 = 53,\n\tMX6DL_PAD_DISP0_DAT18 = 54,\n\tMX6DL_PAD_DISP0_DAT19 = 55,\n\tMX6DL_PAD_DISP0_DAT2 = 56,\n\tMX6DL_PAD_DISP0_DAT20 = 57,\n\tMX6DL_PAD_DISP0_DAT21 = 58,\n\tMX6DL_PAD_DISP0_DAT22 = 59,\n\tMX6DL_PAD_DISP0_DAT23 = 60,\n\tMX6DL_PAD_DISP0_DAT3 = 61,\n\tMX6DL_PAD_DISP0_DAT4 = 62,\n\tMX6DL_PAD_DISP0_DAT5 = 63,\n\tMX6DL_PAD_DISP0_DAT6 = 64,\n\tMX6DL_PAD_DISP0_DAT7 = 65,\n\tMX6DL_PAD_DISP0_DAT8 = 66,\n\tMX6DL_PAD_DISP0_DAT9 = 67,\n\tMX6DL_PAD_EIM_A16 = 68,\n\tMX6DL_PAD_EIM_A17 = 69,\n\tMX6DL_PAD_EIM_A18 = 70,\n\tMX6DL_PAD_EIM_A19 = 71,\n\tMX6DL_PAD_EIM_A20 = 72,\n\tMX6DL_PAD_EIM_A21 = 73,\n\tMX6DL_PAD_EIM_A22 = 74,\n\tMX6DL_PAD_EIM_A23 = 75,\n\tMX6DL_PAD_EIM_A24 = 76,\n\tMX6DL_PAD_EIM_A25 = 77,\n\tMX6DL_PAD_EIM_BCLK = 78,\n\tMX6DL_PAD_EIM_CS0 = 79,\n\tMX6DL_PAD_EIM_CS1 = 80,\n\tMX6DL_PAD_EIM_D16 = 81,\n\tMX6DL_PAD_EIM_D17 = 82,\n\tMX6DL_PAD_EIM_D18 = 83,\n\tMX6DL_PAD_EIM_D19 = 84,\n\tMX6DL_PAD_EIM_D20 = 85,\n\tMX6DL_PAD_EIM_D21 = 86,\n\tMX6DL_PAD_EIM_D22 = 87,\n\tMX6DL_PAD_EIM_D23 = 88,\n\tMX6DL_PAD_EIM_D24 = 89,\n\tMX6DL_PAD_EIM_D25 = 90,\n\tMX6DL_PAD_EIM_D26 = 91,\n\tMX6DL_PAD_EIM_D27 = 92,\n\tMX6DL_PAD_EIM_D28 = 93,\n\tMX6DL_PAD_EIM_D29 = 94,\n\tMX6DL_PAD_EIM_D30 = 95,\n\tMX6DL_PAD_EIM_D31 = 96,\n\tMX6DL_PAD_EIM_DA0 = 97,\n\tMX6DL_PAD_EIM_DA1 = 98,\n\tMX6DL_PAD_EIM_DA10 = 99,\n\tMX6DL_PAD_EIM_DA11 = 100,\n\tMX6DL_PAD_EIM_DA12 = 101,\n\tMX6DL_PAD_EIM_DA13 = 102,\n\tMX6DL_PAD_EIM_DA14 = 103,\n\tMX6DL_PAD_EIM_DA15 = 104,\n\tMX6DL_PAD_EIM_DA2 = 105,\n\tMX6DL_PAD_EIM_DA3 = 106,\n\tMX6DL_PAD_EIM_DA4 = 107,\n\tMX6DL_PAD_EIM_DA5 = 108,\n\tMX6DL_PAD_EIM_DA6 = 109,\n\tMX6DL_PAD_EIM_DA7 = 110,\n\tMX6DL_PAD_EIM_DA8 = 111,\n\tMX6DL_PAD_EIM_DA9 = 112,\n\tMX6DL_PAD_EIM_EB0 = 113,\n\tMX6DL_PAD_EIM_EB1 = 114,\n\tMX6DL_PAD_EIM_EB2 = 115,\n\tMX6DL_PAD_EIM_EB3 = 116,\n\tMX6DL_PAD_EIM_LBA = 117,\n\tMX6DL_PAD_EIM_OE = 118,\n\tMX6DL_PAD_EIM_RW = 119,\n\tMX6DL_PAD_EIM_WAIT = 120,\n\tMX6DL_PAD_ENET_CRS_DV = 121,\n\tMX6DL_PAD_ENET_MDC = 122,\n\tMX6DL_PAD_ENET_MDIO = 123,\n\tMX6DL_PAD_ENET_REF_CLK = 124,\n\tMX6DL_PAD_ENET_RX_ER = 125,\n\tMX6DL_PAD_ENET_RXD0 = 126,\n\tMX6DL_PAD_ENET_RXD1 = 127,\n\tMX6DL_PAD_ENET_TX_EN = 128,\n\tMX6DL_PAD_ENET_TXD0 = 129,\n\tMX6DL_PAD_ENET_TXD1 = 130,\n\tMX6DL_PAD_GPIO_0 = 131,\n\tMX6DL_PAD_GPIO_1 = 132,\n\tMX6DL_PAD_GPIO_16 = 133,\n\tMX6DL_PAD_GPIO_17 = 134,\n\tMX6DL_PAD_GPIO_18 = 135,\n\tMX6DL_PAD_GPIO_19 = 136,\n\tMX6DL_PAD_GPIO_2 = 137,\n\tMX6DL_PAD_GPIO_3 = 138,\n\tMX6DL_PAD_GPIO_4 = 139,\n\tMX6DL_PAD_GPIO_5 = 140,\n\tMX6DL_PAD_GPIO_6 = 141,\n\tMX6DL_PAD_GPIO_7 = 142,\n\tMX6DL_PAD_GPIO_8 = 143,\n\tMX6DL_PAD_GPIO_9 = 144,\n\tMX6DL_PAD_KEY_COL0 = 145,\n\tMX6DL_PAD_KEY_COL1 = 146,\n\tMX6DL_PAD_KEY_COL2 = 147,\n\tMX6DL_PAD_KEY_COL3 = 148,\n\tMX6DL_PAD_KEY_COL4 = 149,\n\tMX6DL_PAD_KEY_ROW0 = 150,\n\tMX6DL_PAD_KEY_ROW1 = 151,\n\tMX6DL_PAD_KEY_ROW2 = 152,\n\tMX6DL_PAD_KEY_ROW3 = 153,\n\tMX6DL_PAD_KEY_ROW4 = 154,\n\tMX6DL_PAD_NANDF_ALE = 155,\n\tMX6DL_PAD_NANDF_CLE = 156,\n\tMX6DL_PAD_NANDF_CS0 = 157,\n\tMX6DL_PAD_NANDF_CS1 = 158,\n\tMX6DL_PAD_NANDF_CS2 = 159,\n\tMX6DL_PAD_NANDF_CS3 = 160,\n\tMX6DL_PAD_NANDF_D0 = 161,\n\tMX6DL_PAD_NANDF_D1 = 162,\n\tMX6DL_PAD_NANDF_D2 = 163,\n\tMX6DL_PAD_NANDF_D3 = 164,\n\tMX6DL_PAD_NANDF_D4 = 165,\n\tMX6DL_PAD_NANDF_D5 = 166,\n\tMX6DL_PAD_NANDF_D6 = 167,\n\tMX6DL_PAD_NANDF_D7 = 168,\n\tMX6DL_PAD_NANDF_RB0 = 169,\n\tMX6DL_PAD_NANDF_WP_B = 170,\n\tMX6DL_PAD_RGMII_RD0 = 171,\n\tMX6DL_PAD_RGMII_RD1 = 172,\n\tMX6DL_PAD_RGMII_RD2 = 173,\n\tMX6DL_PAD_RGMII_RD3 = 174,\n\tMX6DL_PAD_RGMII_RX_CTL = 175,\n\tMX6DL_PAD_RGMII_RXC = 176,\n\tMX6DL_PAD_RGMII_TD0 = 177,\n\tMX6DL_PAD_RGMII_TD1 = 178,\n\tMX6DL_PAD_RGMII_TD2 = 179,\n\tMX6DL_PAD_RGMII_TD3 = 180,\n\tMX6DL_PAD_RGMII_TX_CTL = 181,\n\tMX6DL_PAD_RGMII_TXC = 182,\n\tMX6DL_PAD_SD1_CLK = 183,\n\tMX6DL_PAD_SD1_CMD = 184,\n\tMX6DL_PAD_SD1_DAT0 = 185,\n\tMX6DL_PAD_SD1_DAT1 = 186,\n\tMX6DL_PAD_SD1_DAT2 = 187,\n\tMX6DL_PAD_SD1_DAT3 = 188,\n\tMX6DL_PAD_SD2_CLK = 189,\n\tMX6DL_PAD_SD2_CMD = 190,\n\tMX6DL_PAD_SD2_DAT0 = 191,\n\tMX6DL_PAD_SD2_DAT1 = 192,\n\tMX6DL_PAD_SD2_DAT2 = 193,\n\tMX6DL_PAD_SD2_DAT3 = 194,\n\tMX6DL_PAD_SD3_CLK = 195,\n\tMX6DL_PAD_SD3_CMD = 196,\n\tMX6DL_PAD_SD3_DAT0 = 197,\n\tMX6DL_PAD_SD3_DAT1 = 198,\n\tMX6DL_PAD_SD3_DAT2 = 199,\n\tMX6DL_PAD_SD3_DAT3 = 200,\n\tMX6DL_PAD_SD3_DAT4 = 201,\n\tMX6DL_PAD_SD3_DAT5 = 202,\n\tMX6DL_PAD_SD3_DAT6 = 203,\n\tMX6DL_PAD_SD3_DAT7 = 204,\n\tMX6DL_PAD_SD3_RST = 205,\n\tMX6DL_PAD_SD4_CLK = 206,\n\tMX6DL_PAD_SD4_CMD = 207,\n\tMX6DL_PAD_SD4_DAT0 = 208,\n\tMX6DL_PAD_SD4_DAT1 = 209,\n\tMX6DL_PAD_SD4_DAT2 = 210,\n\tMX6DL_PAD_SD4_DAT3 = 211,\n\tMX6DL_PAD_SD4_DAT4 = 212,\n\tMX6DL_PAD_SD4_DAT5 = 213,\n\tMX6DL_PAD_SD4_DAT6 = 214,\n\tMX6DL_PAD_SD4_DAT7 = 215,\n};\n\nenum imx6q_pads {\n\tMX6Q_PAD_RESERVE0 = 0,\n\tMX6Q_PAD_RESERVE1 = 1,\n\tMX6Q_PAD_RESERVE2 = 2,\n\tMX6Q_PAD_RESERVE3 = 3,\n\tMX6Q_PAD_RESERVE4 = 4,\n\tMX6Q_PAD_RESERVE5 = 5,\n\tMX6Q_PAD_RESERVE6 = 6,\n\tMX6Q_PAD_RESERVE7 = 7,\n\tMX6Q_PAD_RESERVE8 = 8,\n\tMX6Q_PAD_RESERVE9 = 9,\n\tMX6Q_PAD_RESERVE10 = 10,\n\tMX6Q_PAD_RESERVE11 = 11,\n\tMX6Q_PAD_RESERVE12 = 12,\n\tMX6Q_PAD_RESERVE13 = 13,\n\tMX6Q_PAD_RESERVE14 = 14,\n\tMX6Q_PAD_RESERVE15 = 15,\n\tMX6Q_PAD_RESERVE16 = 16,\n\tMX6Q_PAD_RESERVE17 = 17,\n\tMX6Q_PAD_RESERVE18 = 18,\n\tMX6Q_PAD_SD2_DAT1 = 19,\n\tMX6Q_PAD_SD2_DAT2 = 20,\n\tMX6Q_PAD_SD2_DAT0 = 21,\n\tMX6Q_PAD_RGMII_TXC = 22,\n\tMX6Q_PAD_RGMII_TD0 = 23,\n\tMX6Q_PAD_RGMII_TD1 = 24,\n\tMX6Q_PAD_RGMII_TD2 = 25,\n\tMX6Q_PAD_RGMII_TD3 = 26,\n\tMX6Q_PAD_RGMII_RX_CTL = 27,\n\tMX6Q_PAD_RGMII_RD0 = 28,\n\tMX6Q_PAD_RGMII_TX_CTL = 29,\n\tMX6Q_PAD_RGMII_RD1 = 30,\n\tMX6Q_PAD_RGMII_RD2 = 31,\n\tMX6Q_PAD_RGMII_RD3 = 32,\n\tMX6Q_PAD_RGMII_RXC = 33,\n\tMX6Q_PAD_EIM_A25 = 34,\n\tMX6Q_PAD_EIM_EB2 = 35,\n\tMX6Q_PAD_EIM_D16 = 36,\n\tMX6Q_PAD_EIM_D17 = 37,\n\tMX6Q_PAD_EIM_D18 = 38,\n\tMX6Q_PAD_EIM_D19 = 39,\n\tMX6Q_PAD_EIM_D20 = 40,\n\tMX6Q_PAD_EIM_D21 = 41,\n\tMX6Q_PAD_EIM_D22 = 42,\n\tMX6Q_PAD_EIM_D23 = 43,\n\tMX6Q_PAD_EIM_EB3 = 44,\n\tMX6Q_PAD_EIM_D24 = 45,\n\tMX6Q_PAD_EIM_D25 = 46,\n\tMX6Q_PAD_EIM_D26 = 47,\n\tMX6Q_PAD_EIM_D27 = 48,\n\tMX6Q_PAD_EIM_D28 = 49,\n\tMX6Q_PAD_EIM_D29 = 50,\n\tMX6Q_PAD_EIM_D30 = 51,\n\tMX6Q_PAD_EIM_D31 = 52,\n\tMX6Q_PAD_EIM_A24 = 53,\n\tMX6Q_PAD_EIM_A23 = 54,\n\tMX6Q_PAD_EIM_A22 = 55,\n\tMX6Q_PAD_EIM_A21 = 56,\n\tMX6Q_PAD_EIM_A20 = 57,\n\tMX6Q_PAD_EIM_A19 = 58,\n\tMX6Q_PAD_EIM_A18 = 59,\n\tMX6Q_PAD_EIM_A17 = 60,\n\tMX6Q_PAD_EIM_A16 = 61,\n\tMX6Q_PAD_EIM_CS0 = 62,\n\tMX6Q_PAD_EIM_CS1 = 63,\n\tMX6Q_PAD_EIM_OE = 64,\n\tMX6Q_PAD_EIM_RW = 65,\n\tMX6Q_PAD_EIM_LBA = 66,\n\tMX6Q_PAD_EIM_EB0 = 67,\n\tMX6Q_PAD_EIM_EB1 = 68,\n\tMX6Q_PAD_EIM_DA0 = 69,\n\tMX6Q_PAD_EIM_DA1 = 70,\n\tMX6Q_PAD_EIM_DA2 = 71,\n\tMX6Q_PAD_EIM_DA3 = 72,\n\tMX6Q_PAD_EIM_DA4 = 73,\n\tMX6Q_PAD_EIM_DA5 = 74,\n\tMX6Q_PAD_EIM_DA6 = 75,\n\tMX6Q_PAD_EIM_DA7 = 76,\n\tMX6Q_PAD_EIM_DA8 = 77,\n\tMX6Q_PAD_EIM_DA9 = 78,\n\tMX6Q_PAD_EIM_DA10 = 79,\n\tMX6Q_PAD_EIM_DA11 = 80,\n\tMX6Q_PAD_EIM_DA12 = 81,\n\tMX6Q_PAD_EIM_DA13 = 82,\n\tMX6Q_PAD_EIM_DA14 = 83,\n\tMX6Q_PAD_EIM_DA15 = 84,\n\tMX6Q_PAD_EIM_WAIT = 85,\n\tMX6Q_PAD_EIM_BCLK = 86,\n\tMX6Q_PAD_DI0_DISP_CLK = 87,\n\tMX6Q_PAD_DI0_PIN15 = 88,\n\tMX6Q_PAD_DI0_PIN2 = 89,\n\tMX6Q_PAD_DI0_PIN3 = 90,\n\tMX6Q_PAD_DI0_PIN4 = 91,\n\tMX6Q_PAD_DISP0_DAT0 = 92,\n\tMX6Q_PAD_DISP0_DAT1 = 93,\n\tMX6Q_PAD_DISP0_DAT2 = 94,\n\tMX6Q_PAD_DISP0_DAT3 = 95,\n\tMX6Q_PAD_DISP0_DAT4 = 96,\n\tMX6Q_PAD_DISP0_DAT5 = 97,\n\tMX6Q_PAD_DISP0_DAT6 = 98,\n\tMX6Q_PAD_DISP0_DAT7 = 99,\n\tMX6Q_PAD_DISP0_DAT8 = 100,\n\tMX6Q_PAD_DISP0_DAT9 = 101,\n\tMX6Q_PAD_DISP0_DAT10 = 102,\n\tMX6Q_PAD_DISP0_DAT11 = 103,\n\tMX6Q_PAD_DISP0_DAT12 = 104,\n\tMX6Q_PAD_DISP0_DAT13 = 105,\n\tMX6Q_PAD_DISP0_DAT14 = 106,\n\tMX6Q_PAD_DISP0_DAT15 = 107,\n\tMX6Q_PAD_DISP0_DAT16 = 108,\n\tMX6Q_PAD_DISP0_DAT17 = 109,\n\tMX6Q_PAD_DISP0_DAT18 = 110,\n\tMX6Q_PAD_DISP0_DAT19 = 111,\n\tMX6Q_PAD_DISP0_DAT20 = 112,\n\tMX6Q_PAD_DISP0_DAT21 = 113,\n\tMX6Q_PAD_DISP0_DAT22 = 114,\n\tMX6Q_PAD_DISP0_DAT23 = 115,\n\tMX6Q_PAD_ENET_MDIO = 116,\n\tMX6Q_PAD_ENET_REF_CLK = 117,\n\tMX6Q_PAD_ENET_RX_ER = 118,\n\tMX6Q_PAD_ENET_CRS_DV = 119,\n\tMX6Q_PAD_ENET_RXD1 = 120,\n\tMX6Q_PAD_ENET_RXD0 = 121,\n\tMX6Q_PAD_ENET_TX_EN = 122,\n\tMX6Q_PAD_ENET_TXD1 = 123,\n\tMX6Q_PAD_ENET_TXD0 = 124,\n\tMX6Q_PAD_ENET_MDC = 125,\n\tMX6Q_PAD_KEY_COL0 = 126,\n\tMX6Q_PAD_KEY_ROW0 = 127,\n\tMX6Q_PAD_KEY_COL1 = 128,\n\tMX6Q_PAD_KEY_ROW1 = 129,\n\tMX6Q_PAD_KEY_COL2 = 130,\n\tMX6Q_PAD_KEY_ROW2 = 131,\n\tMX6Q_PAD_KEY_COL3 = 132,\n\tMX6Q_PAD_KEY_ROW3 = 133,\n\tMX6Q_PAD_KEY_COL4 = 134,\n\tMX6Q_PAD_KEY_ROW4 = 135,\n\tMX6Q_PAD_GPIO_0 = 136,\n\tMX6Q_PAD_GPIO_1 = 137,\n\tMX6Q_PAD_GPIO_9 = 138,\n\tMX6Q_PAD_GPIO_3 = 139,\n\tMX6Q_PAD_GPIO_6 = 140,\n\tMX6Q_PAD_GPIO_2 = 141,\n\tMX6Q_PAD_GPIO_4 = 142,\n\tMX6Q_PAD_GPIO_5 = 143,\n\tMX6Q_PAD_GPIO_7 = 144,\n\tMX6Q_PAD_GPIO_8 = 145,\n\tMX6Q_PAD_GPIO_16 = 146,\n\tMX6Q_PAD_GPIO_17 = 147,\n\tMX6Q_PAD_GPIO_18 = 148,\n\tMX6Q_PAD_GPIO_19 = 149,\n\tMX6Q_PAD_CSI0_PIXCLK = 150,\n\tMX6Q_PAD_CSI0_MCLK = 151,\n\tMX6Q_PAD_CSI0_DATA_EN = 152,\n\tMX6Q_PAD_CSI0_VSYNC = 153,\n\tMX6Q_PAD_CSI0_DAT4 = 154,\n\tMX6Q_PAD_CSI0_DAT5 = 155,\n\tMX6Q_PAD_CSI0_DAT6 = 156,\n\tMX6Q_PAD_CSI0_DAT7 = 157,\n\tMX6Q_PAD_CSI0_DAT8 = 158,\n\tMX6Q_PAD_CSI0_DAT9 = 159,\n\tMX6Q_PAD_CSI0_DAT10 = 160,\n\tMX6Q_PAD_CSI0_DAT11 = 161,\n\tMX6Q_PAD_CSI0_DAT12 = 162,\n\tMX6Q_PAD_CSI0_DAT13 = 163,\n\tMX6Q_PAD_CSI0_DAT14 = 164,\n\tMX6Q_PAD_CSI0_DAT15 = 165,\n\tMX6Q_PAD_CSI0_DAT16 = 166,\n\tMX6Q_PAD_CSI0_DAT17 = 167,\n\tMX6Q_PAD_CSI0_DAT18 = 168,\n\tMX6Q_PAD_CSI0_DAT19 = 169,\n\tMX6Q_PAD_SD3_DAT7 = 170,\n\tMX6Q_PAD_SD3_DAT6 = 171,\n\tMX6Q_PAD_SD3_DAT5 = 172,\n\tMX6Q_PAD_SD3_DAT4 = 173,\n\tMX6Q_PAD_SD3_CMD = 174,\n\tMX6Q_PAD_SD3_CLK = 175,\n\tMX6Q_PAD_SD3_DAT0 = 176,\n\tMX6Q_PAD_SD3_DAT1 = 177,\n\tMX6Q_PAD_SD3_DAT2 = 178,\n\tMX6Q_PAD_SD3_DAT3 = 179,\n\tMX6Q_PAD_SD3_RST = 180,\n\tMX6Q_PAD_NANDF_CLE = 181,\n\tMX6Q_PAD_NANDF_ALE = 182,\n\tMX6Q_PAD_NANDF_WP_B = 183,\n\tMX6Q_PAD_NANDF_RB0 = 184,\n\tMX6Q_PAD_NANDF_CS0 = 185,\n\tMX6Q_PAD_NANDF_CS1 = 186,\n\tMX6Q_PAD_NANDF_CS2 = 187,\n\tMX6Q_PAD_NANDF_CS3 = 188,\n\tMX6Q_PAD_SD4_CMD = 189,\n\tMX6Q_PAD_SD4_CLK = 190,\n\tMX6Q_PAD_NANDF_D0 = 191,\n\tMX6Q_PAD_NANDF_D1 = 192,\n\tMX6Q_PAD_NANDF_D2 = 193,\n\tMX6Q_PAD_NANDF_D3 = 194,\n\tMX6Q_PAD_NANDF_D4 = 195,\n\tMX6Q_PAD_NANDF_D5 = 196,\n\tMX6Q_PAD_NANDF_D6 = 197,\n\tMX6Q_PAD_NANDF_D7 = 198,\n\tMX6Q_PAD_SD4_DAT0 = 199,\n\tMX6Q_PAD_SD4_DAT1 = 200,\n\tMX6Q_PAD_SD4_DAT2 = 201,\n\tMX6Q_PAD_SD4_DAT3 = 202,\n\tMX6Q_PAD_SD4_DAT4 = 203,\n\tMX6Q_PAD_SD4_DAT5 = 204,\n\tMX6Q_PAD_SD4_DAT6 = 205,\n\tMX6Q_PAD_SD4_DAT7 = 206,\n\tMX6Q_PAD_SD1_DAT1 = 207,\n\tMX6Q_PAD_SD1_DAT0 = 208,\n\tMX6Q_PAD_SD1_DAT3 = 209,\n\tMX6Q_PAD_SD1_CMD = 210,\n\tMX6Q_PAD_SD1_DAT2 = 211,\n\tMX6Q_PAD_SD1_CLK = 212,\n\tMX6Q_PAD_SD2_CLK = 213,\n\tMX6Q_PAD_SD2_CMD = 214,\n\tMX6Q_PAD_SD2_DAT3 = 215,\n};\n\nenum imx6sl_pads {\n\tMX6SL_PAD_RESERVE0 = 0,\n\tMX6SL_PAD_RESERVE1 = 1,\n\tMX6SL_PAD_RESERVE2 = 2,\n\tMX6SL_PAD_RESERVE3 = 3,\n\tMX6SL_PAD_RESERVE4 = 4,\n\tMX6SL_PAD_RESERVE5 = 5,\n\tMX6SL_PAD_RESERVE6 = 6,\n\tMX6SL_PAD_RESERVE7 = 7,\n\tMX6SL_PAD_RESERVE8 = 8,\n\tMX6SL_PAD_RESERVE9 = 9,\n\tMX6SL_PAD_RESERVE10 = 10,\n\tMX6SL_PAD_RESERVE11 = 11,\n\tMX6SL_PAD_RESERVE12 = 12,\n\tMX6SL_PAD_RESERVE13 = 13,\n\tMX6SL_PAD_RESERVE14 = 14,\n\tMX6SL_PAD_RESERVE15 = 15,\n\tMX6SL_PAD_RESERVE16 = 16,\n\tMX6SL_PAD_RESERVE17 = 17,\n\tMX6SL_PAD_RESERVE18 = 18,\n\tMX6SL_PAD_AUD_MCLK = 19,\n\tMX6SL_PAD_AUD_RXC = 20,\n\tMX6SL_PAD_AUD_RXD = 21,\n\tMX6SL_PAD_AUD_RXFS = 22,\n\tMX6SL_PAD_AUD_TXC = 23,\n\tMX6SL_PAD_AUD_TXD = 24,\n\tMX6SL_PAD_AUD_TXFS = 25,\n\tMX6SL_PAD_ECSPI1_MISO = 26,\n\tMX6SL_PAD_ECSPI1_MOSI = 27,\n\tMX6SL_PAD_ECSPI1_SCLK = 28,\n\tMX6SL_PAD_ECSPI1_SS0 = 29,\n\tMX6SL_PAD_ECSPI2_MISO = 30,\n\tMX6SL_PAD_ECSPI2_MOSI = 31,\n\tMX6SL_PAD_ECSPI2_SCLK = 32,\n\tMX6SL_PAD_ECSPI2_SS0 = 33,\n\tMX6SL_PAD_EPDC_BDR0 = 34,\n\tMX6SL_PAD_EPDC_BDR1 = 35,\n\tMX6SL_PAD_EPDC_D0 = 36,\n\tMX6SL_PAD_EPDC_D1 = 37,\n\tMX6SL_PAD_EPDC_D10 = 38,\n\tMX6SL_PAD_EPDC_D11 = 39,\n\tMX6SL_PAD_EPDC_D12 = 40,\n\tMX6SL_PAD_EPDC_D13 = 41,\n\tMX6SL_PAD_EPDC_D14 = 42,\n\tMX6SL_PAD_EPDC_D15 = 43,\n\tMX6SL_PAD_EPDC_D2 = 44,\n\tMX6SL_PAD_EPDC_D3 = 45,\n\tMX6SL_PAD_EPDC_D4 = 46,\n\tMX6SL_PAD_EPDC_D5 = 47,\n\tMX6SL_PAD_EPDC_D6 = 48,\n\tMX6SL_PAD_EPDC_D7 = 49,\n\tMX6SL_PAD_EPDC_D8 = 50,\n\tMX6SL_PAD_EPDC_D9 = 51,\n\tMX6SL_PAD_EPDC_GDCLK = 52,\n\tMX6SL_PAD_EPDC_GDOE = 53,\n\tMX6SL_PAD_EPDC_GDRL = 54,\n\tMX6SL_PAD_EPDC_GDSP = 55,\n\tMX6SL_PAD_EPDC_PWRCOM = 56,\n\tMX6SL_PAD_EPDC_PWRCTRL0 = 57,\n\tMX6SL_PAD_EPDC_PWRCTRL1 = 58,\n\tMX6SL_PAD_EPDC_PWRCTRL2 = 59,\n\tMX6SL_PAD_EPDC_PWRCTRL3 = 60,\n\tMX6SL_PAD_EPDC_PWRINT = 61,\n\tMX6SL_PAD_EPDC_PWRSTAT = 62,\n\tMX6SL_PAD_EPDC_PWRWAKEUP = 63,\n\tMX6SL_PAD_EPDC_SDCE0 = 64,\n\tMX6SL_PAD_EPDC_SDCE1 = 65,\n\tMX6SL_PAD_EPDC_SDCE2 = 66,\n\tMX6SL_PAD_EPDC_SDCE3 = 67,\n\tMX6SL_PAD_EPDC_SDCLK = 68,\n\tMX6SL_PAD_EPDC_SDLE = 69,\n\tMX6SL_PAD_EPDC_SDOE = 70,\n\tMX6SL_PAD_EPDC_SDSHR = 71,\n\tMX6SL_PAD_EPDC_VCOM0 = 72,\n\tMX6SL_PAD_EPDC_VCOM1 = 73,\n\tMX6SL_PAD_FEC_CRS_DV = 74,\n\tMX6SL_PAD_FEC_MDC = 75,\n\tMX6SL_PAD_FEC_MDIO = 76,\n\tMX6SL_PAD_FEC_REF_CLK = 77,\n\tMX6SL_PAD_FEC_RX_ER = 78,\n\tMX6SL_PAD_FEC_RXD0 = 79,\n\tMX6SL_PAD_FEC_RXD1 = 80,\n\tMX6SL_PAD_FEC_TX_CLK = 81,\n\tMX6SL_PAD_FEC_TX_EN = 82,\n\tMX6SL_PAD_FEC_TXD0 = 83,\n\tMX6SL_PAD_FEC_TXD1 = 84,\n\tMX6SL_PAD_HSIC_DAT = 85,\n\tMX6SL_PAD_HSIC_STROBE = 86,\n\tMX6SL_PAD_I2C1_SCL = 87,\n\tMX6SL_PAD_I2C1_SDA = 88,\n\tMX6SL_PAD_I2C2_SCL = 89,\n\tMX6SL_PAD_I2C2_SDA = 90,\n\tMX6SL_PAD_KEY_COL0 = 91,\n\tMX6SL_PAD_KEY_COL1 = 92,\n\tMX6SL_PAD_KEY_COL2 = 93,\n\tMX6SL_PAD_KEY_COL3 = 94,\n\tMX6SL_PAD_KEY_COL4 = 95,\n\tMX6SL_PAD_KEY_COL5 = 96,\n\tMX6SL_PAD_KEY_COL6 = 97,\n\tMX6SL_PAD_KEY_COL7 = 98,\n\tMX6SL_PAD_KEY_ROW0 = 99,\n\tMX6SL_PAD_KEY_ROW1 = 100,\n\tMX6SL_PAD_KEY_ROW2 = 101,\n\tMX6SL_PAD_KEY_ROW3 = 102,\n\tMX6SL_PAD_KEY_ROW4 = 103,\n\tMX6SL_PAD_KEY_ROW5 = 104,\n\tMX6SL_PAD_KEY_ROW6 = 105,\n\tMX6SL_PAD_KEY_ROW7 = 106,\n\tMX6SL_PAD_LCD_CLK = 107,\n\tMX6SL_PAD_LCD_DAT0 = 108,\n\tMX6SL_PAD_LCD_DAT1 = 109,\n\tMX6SL_PAD_LCD_DAT10 = 110,\n\tMX6SL_PAD_LCD_DAT11 = 111,\n\tMX6SL_PAD_LCD_DAT12 = 112,\n\tMX6SL_PAD_LCD_DAT13 = 113,\n\tMX6SL_PAD_LCD_DAT14 = 114,\n\tMX6SL_PAD_LCD_DAT15 = 115,\n\tMX6SL_PAD_LCD_DAT16 = 116,\n\tMX6SL_PAD_LCD_DAT17 = 117,\n\tMX6SL_PAD_LCD_DAT18 = 118,\n\tMX6SL_PAD_LCD_DAT19 = 119,\n\tMX6SL_PAD_LCD_DAT2 = 120,\n\tMX6SL_PAD_LCD_DAT20 = 121,\n\tMX6SL_PAD_LCD_DAT21 = 122,\n\tMX6SL_PAD_LCD_DAT22 = 123,\n\tMX6SL_PAD_LCD_DAT23 = 124,\n\tMX6SL_PAD_LCD_DAT3 = 125,\n\tMX6SL_PAD_LCD_DAT4 = 126,\n\tMX6SL_PAD_LCD_DAT5 = 127,\n\tMX6SL_PAD_LCD_DAT6 = 128,\n\tMX6SL_PAD_LCD_DAT7 = 129,\n\tMX6SL_PAD_LCD_DAT8 = 130,\n\tMX6SL_PAD_LCD_DAT9 = 131,\n\tMX6SL_PAD_LCD_ENABLE = 132,\n\tMX6SL_PAD_LCD_HSYNC = 133,\n\tMX6SL_PAD_LCD_RESET = 134,\n\tMX6SL_PAD_LCD_VSYNC = 135,\n\tMX6SL_PAD_PWM1 = 136,\n\tMX6SL_PAD_REF_CLK_24M = 137,\n\tMX6SL_PAD_REF_CLK_32K = 138,\n\tMX6SL_PAD_SD1_CLK = 139,\n\tMX6SL_PAD_SD1_CMD = 140,\n\tMX6SL_PAD_SD1_DAT0 = 141,\n\tMX6SL_PAD_SD1_DAT1 = 142,\n\tMX6SL_PAD_SD1_DAT2 = 143,\n\tMX6SL_PAD_SD1_DAT3 = 144,\n\tMX6SL_PAD_SD1_DAT4 = 145,\n\tMX6SL_PAD_SD1_DAT5 = 146,\n\tMX6SL_PAD_SD1_DAT6 = 147,\n\tMX6SL_PAD_SD1_DAT7 = 148,\n\tMX6SL_PAD_SD2_CLK = 149,\n\tMX6SL_PAD_SD2_CMD = 150,\n\tMX6SL_PAD_SD2_DAT0 = 151,\n\tMX6SL_PAD_SD2_DAT1 = 152,\n\tMX6SL_PAD_SD2_DAT2 = 153,\n\tMX6SL_PAD_SD2_DAT3 = 154,\n\tMX6SL_PAD_SD2_DAT4 = 155,\n\tMX6SL_PAD_SD2_DAT5 = 156,\n\tMX6SL_PAD_SD2_DAT6 = 157,\n\tMX6SL_PAD_SD2_DAT7 = 158,\n\tMX6SL_PAD_SD2_RST = 159,\n\tMX6SL_PAD_SD3_CLK = 160,\n\tMX6SL_PAD_SD3_CMD = 161,\n\tMX6SL_PAD_SD3_DAT0 = 162,\n\tMX6SL_PAD_SD3_DAT1 = 163,\n\tMX6SL_PAD_SD3_DAT2 = 164,\n\tMX6SL_PAD_SD3_DAT3 = 165,\n\tMX6SL_PAD_UART1_RXD = 166,\n\tMX6SL_PAD_UART1_TXD = 167,\n\tMX6SL_PAD_WDOG_B = 168,\n};\n\nenum imx6sll_pads {\n\tMX6SLL_PAD_RESERVE0 = 0,\n\tMX6SLL_PAD_RESERVE1 = 1,\n\tMX6SLL_PAD_RESERVE2 = 2,\n\tMX6SLL_PAD_RESERVE3 = 3,\n\tMX6SLL_PAD_RESERVE4 = 4,\n\tMX6SLL_PAD_WDOG_B = 5,\n\tMX6SLL_PAD_REF_CLK_24M = 6,\n\tMX6SLL_PAD_REF_CLK_32K = 7,\n\tMX6SLL_PAD_PWM1 = 8,\n\tMX6SLL_PAD_KEY_COL0 = 9,\n\tMX6SLL_PAD_KEY_ROW0 = 10,\n\tMX6SLL_PAD_KEY_COL1 = 11,\n\tMX6SLL_PAD_KEY_ROW1 = 12,\n\tMX6SLL_PAD_KEY_COL2 = 13,\n\tMX6SLL_PAD_KEY_ROW2 = 14,\n\tMX6SLL_PAD_KEY_COL3 = 15,\n\tMX6SLL_PAD_KEY_ROW3 = 16,\n\tMX6SLL_PAD_KEY_COL4 = 17,\n\tMX6SLL_PAD_KEY_ROW4 = 18,\n\tMX6SLL_PAD_KEY_COL5 = 19,\n\tMX6SLL_PAD_KEY_ROW5 = 20,\n\tMX6SLL_PAD_KEY_COL6 = 21,\n\tMX6SLL_PAD_KEY_ROW6 = 22,\n\tMX6SLL_PAD_KEY_COL7 = 23,\n\tMX6SLL_PAD_KEY_ROW7 = 24,\n\tMX6SLL_PAD_EPDC_DATA00 = 25,\n\tMX6SLL_PAD_EPDC_DATA01 = 26,\n\tMX6SLL_PAD_EPDC_DATA02 = 27,\n\tMX6SLL_PAD_EPDC_DATA03 = 28,\n\tMX6SLL_PAD_EPDC_DATA04 = 29,\n\tMX6SLL_PAD_EPDC_DATA05 = 30,\n\tMX6SLL_PAD_EPDC_DATA06 = 31,\n\tMX6SLL_PAD_EPDC_DATA07 = 32,\n\tMX6SLL_PAD_EPDC_DATA08 = 33,\n\tMX6SLL_PAD_EPDC_DATA09 = 34,\n\tMX6SLL_PAD_EPDC_DATA10 = 35,\n\tMX6SLL_PAD_EPDC_DATA11 = 36,\n\tMX6SLL_PAD_EPDC_DATA12 = 37,\n\tMX6SLL_PAD_EPDC_DATA13 = 38,\n\tMX6SLL_PAD_EPDC_DATA14 = 39,\n\tMX6SLL_PAD_EPDC_DATA15 = 40,\n\tMX6SLL_PAD_EPDC_SDCLK = 41,\n\tMX6SLL_PAD_EPDC_SDLE = 42,\n\tMX6SLL_PAD_EPDC_SDOE = 43,\n\tMX6SLL_PAD_EPDC_SDSHR = 44,\n\tMX6SLL_PAD_EPDC_SDCE0 = 45,\n\tMX6SLL_PAD_EPDC_SDCE1 = 46,\n\tMX6SLL_PAD_EPDC_SDCE2 = 47,\n\tMX6SLL_PAD_EPDC_SDCE3 = 48,\n\tMX6SLL_PAD_EPDC_GDCLK = 49,\n\tMX6SLL_PAD_EPDC_GDOE = 50,\n\tMX6SLL_PAD_EPDC_GDRL = 51,\n\tMX6SLL_PAD_EPDC_GDSP = 52,\n\tMX6SLL_PAD_EPDC_VCOM0 = 53,\n\tMX6SLL_PAD_EPDC_VCOM1 = 54,\n\tMX6SLL_PAD_EPDC_BDR0 = 55,\n\tMX6SLL_PAD_EPDC_BDR1 = 56,\n\tMX6SLL_PAD_EPDC_PWR_CTRL0 = 57,\n\tMX6SLL_PAD_EPDC_PWR_CTRL1 = 58,\n\tMX6SLL_PAD_EPDC_PWR_CTRL2 = 59,\n\tMX6SLL_PAD_EPDC_PWR_CTRL3 = 60,\n\tMX6SLL_PAD_EPDC_PWR_COM = 61,\n\tMX6SLL_PAD_EPDC_PWR_INT = 62,\n\tMX6SLL_PAD_EPDC_PWR_STAT = 63,\n\tMX6SLL_PAD_EPDC_PWR_WAKE = 64,\n\tMX6SLL_PAD_LCD_CLK = 65,\n\tMX6SLL_PAD_LCD_ENABLE = 66,\n\tMX6SLL_PAD_LCD_HSYNC = 67,\n\tMX6SLL_PAD_LCD_VSYNC = 68,\n\tMX6SLL_PAD_LCD_RESET = 69,\n\tMX6SLL_PAD_LCD_DATA00 = 70,\n\tMX6SLL_PAD_LCD_DATA01 = 71,\n\tMX6SLL_PAD_LCD_DATA02 = 72,\n\tMX6SLL_PAD_LCD_DATA03 = 73,\n\tMX6SLL_PAD_LCD_DATA04 = 74,\n\tMX6SLL_PAD_LCD_DATA05 = 75,\n\tMX6SLL_PAD_LCD_DATA06 = 76,\n\tMX6SLL_PAD_LCD_DATA07 = 77,\n\tMX6SLL_PAD_LCD_DATA08 = 78,\n\tMX6SLL_PAD_LCD_DATA09 = 79,\n\tMX6SLL_PAD_LCD_DATA10 = 80,\n\tMX6SLL_PAD_LCD_DATA11 = 81,\n\tMX6SLL_PAD_LCD_DATA12 = 82,\n\tMX6SLL_PAD_LCD_DATA13 = 83,\n\tMX6SLL_PAD_LCD_DATA14 = 84,\n\tMX6SLL_PAD_LCD_DATA15 = 85,\n\tMX6SLL_PAD_LCD_DATA16 = 86,\n\tMX6SLL_PAD_LCD_DATA17 = 87,\n\tMX6SLL_PAD_LCD_DATA18 = 88,\n\tMX6SLL_PAD_LCD_DATA19 = 89,\n\tMX6SLL_PAD_LCD_DATA20 = 90,\n\tMX6SLL_PAD_LCD_DATA21 = 91,\n\tMX6SLL_PAD_LCD_DATA22 = 92,\n\tMX6SLL_PAD_LCD_DATA23 = 93,\n\tMX6SLL_PAD_AUD_RXFS = 94,\n\tMX6SLL_PAD_AUD_RXC = 95,\n\tMX6SLL_PAD_AUD_RXD = 96,\n\tMX6SLL_PAD_AUD_TXC = 97,\n\tMX6SLL_PAD_AUD_TXFS = 98,\n\tMX6SLL_PAD_AUD_TXD = 99,\n\tMX6SLL_PAD_AUD_MCLK = 100,\n\tMX6SLL_PAD_UART1_RXD = 101,\n\tMX6SLL_PAD_UART1_TXD = 102,\n\tMX6SLL_PAD_I2C1_SCL = 103,\n\tMX6SLL_PAD_I2C1_SDA = 104,\n\tMX6SLL_PAD_I2C2_SCL = 105,\n\tMX6SLL_PAD_I2C2_SDA = 106,\n\tMX6SLL_PAD_ECSPI1_SCLK = 107,\n\tMX6SLL_PAD_ECSPI1_MOSI = 108,\n\tMX6SLL_PAD_ECSPI1_MISO = 109,\n\tMX6SLL_PAD_ECSPI1_SS0 = 110,\n\tMX6SLL_PAD_ECSPI2_SCLK = 111,\n\tMX6SLL_PAD_ECSPI2_MOSI = 112,\n\tMX6SLL_PAD_ECSPI2_MISO = 113,\n\tMX6SLL_PAD_ECSPI2_SS0 = 114,\n\tMX6SLL_PAD_SD1_CLK = 115,\n\tMX6SLL_PAD_SD1_CMD = 116,\n\tMX6SLL_PAD_SD1_DATA0 = 117,\n\tMX6SLL_PAD_SD1_DATA1 = 118,\n\tMX6SLL_PAD_SD1_DATA2 = 119,\n\tMX6SLL_PAD_SD1_DATA3 = 120,\n\tMX6SLL_PAD_SD1_DATA4 = 121,\n\tMX6SLL_PAD_SD1_DATA5 = 122,\n\tMX6SLL_PAD_SD1_DATA6 = 123,\n\tMX6SLL_PAD_SD1_DATA7 = 124,\n\tMX6SLL_PAD_SD2_RESET = 125,\n\tMX6SLL_PAD_SD2_CLK = 126,\n\tMX6SLL_PAD_SD2_CMD = 127,\n\tMX6SLL_PAD_SD2_DATA0 = 128,\n\tMX6SLL_PAD_SD2_DATA1 = 129,\n\tMX6SLL_PAD_SD2_DATA2 = 130,\n\tMX6SLL_PAD_SD2_DATA3 = 131,\n\tMX6SLL_PAD_SD2_DATA4 = 132,\n\tMX6SLL_PAD_SD2_DATA5 = 133,\n\tMX6SLL_PAD_SD2_DATA6 = 134,\n\tMX6SLL_PAD_SD2_DATA7 = 135,\n\tMX6SLL_PAD_SD3_CLK = 136,\n\tMX6SLL_PAD_SD3_CMD = 137,\n\tMX6SLL_PAD_SD3_DATA0 = 138,\n\tMX6SLL_PAD_SD3_DATA1 = 139,\n\tMX6SLL_PAD_SD3_DATA2 = 140,\n\tMX6SLL_PAD_SD3_DATA3 = 141,\n\tMX6SLL_PAD_GPIO4_IO20 = 142,\n\tMX6SLL_PAD_GPIO4_IO21 = 143,\n\tMX6SLL_PAD_GPIO4_IO19 = 144,\n\tMX6SLL_PAD_GPIO4_IO25 = 145,\n\tMX6SLL_PAD_GPIO4_IO18 = 146,\n\tMX6SLL_PAD_GPIO4_IO24 = 147,\n\tMX6SLL_PAD_GPIO4_IO23 = 148,\n\tMX6SLL_PAD_GPIO4_IO17 = 149,\n\tMX6SLL_PAD_GPIO4_IO22 = 150,\n\tMX6SLL_PAD_GPIO4_IO16 = 151,\n\tMX6SLL_PAD_GPIO4_IO26 = 152,\n};\n\nenum imx6sx_pads {\n\tMX6Sx_PAD_RESERVE0 = 0,\n\tMX6Sx_PAD_RESERVE1 = 1,\n\tMX6Sx_PAD_RESERVE2 = 2,\n\tMX6Sx_PAD_RESERVE3 = 3,\n\tMX6Sx_PAD_RESERVE4 = 4,\n\tMX6SX_PAD_GPIO1_IO00 = 5,\n\tMX6SX_PAD_GPIO1_IO01 = 6,\n\tMX6SX_PAD_GPIO1_IO02 = 7,\n\tMX6SX_PAD_GPIO1_IO03 = 8,\n\tMX6SX_PAD_GPIO1_IO04 = 9,\n\tMX6SX_PAD_GPIO1_IO05 = 10,\n\tMX6SX_PAD_GPIO1_IO06 = 11,\n\tMX6SX_PAD_GPIO1_IO07 = 12,\n\tMX6SX_PAD_GPIO1_IO08 = 13,\n\tMX6SX_PAD_GPIO1_IO09 = 14,\n\tMX6SX_PAD_GPIO1_IO10 = 15,\n\tMX6SX_PAD_GPIO1_IO11 = 16,\n\tMX6SX_PAD_GPIO1_IO12 = 17,\n\tMX6SX_PAD_GPIO1_IO13 = 18,\n\tMX6SX_PAD_CSI_DATA00 = 19,\n\tMX6SX_PAD_CSI_DATA01 = 20,\n\tMX6SX_PAD_CSI_DATA02 = 21,\n\tMX6SX_PAD_CSI_DATA03 = 22,\n\tMX6SX_PAD_CSI_DATA04 = 23,\n\tMX6SX_PAD_CSI_DATA05 = 24,\n\tMX6SX_PAD_CSI_DATA06 = 25,\n\tMX6SX_PAD_CSI_DATA07 = 26,\n\tMX6SX_PAD_CSI_HSYNC = 27,\n\tMX6SX_PAD_CSI_MCLK = 28,\n\tMX6SX_PAD_CSI_PIXCLK = 29,\n\tMX6SX_PAD_CSI_VSYNC = 30,\n\tMX6SX_PAD_ENET1_COL = 31,\n\tMX6SX_PAD_ENET1_CRS = 32,\n\tMX6SX_PAD_ENET1_MDC = 33,\n\tMX6SX_PAD_ENET1_MDIO = 34,\n\tMX6SX_PAD_ENET1_RX_CLK = 35,\n\tMX6SX_PAD_ENET1_TX_CLK = 36,\n\tMX6SX_PAD_ENET2_COL = 37,\n\tMX6SX_PAD_ENET2_CRS = 38,\n\tMX6SX_PAD_ENET2_RX_CLK = 39,\n\tMX6SX_PAD_ENET2_TX_CLK = 40,\n\tMX6SX_PAD_KEY_COL0 = 41,\n\tMX6SX_PAD_KEY_COL1 = 42,\n\tMX6SX_PAD_KEY_COL2 = 43,\n\tMX6SX_PAD_KEY_COL3 = 44,\n\tMX6SX_PAD_KEY_COL4 = 45,\n\tMX6SX_PAD_KEY_ROW0 = 46,\n\tMX6SX_PAD_KEY_ROW1 = 47,\n\tMX6SX_PAD_KEY_ROW2 = 48,\n\tMX6SX_PAD_KEY_ROW3 = 49,\n\tMX6SX_PAD_KEY_ROW4 = 50,\n\tMX6SX_PAD_LCD1_CLK = 51,\n\tMX6SX_PAD_LCD1_DATA00 = 52,\n\tMX6SX_PAD_LCD1_DATA01 = 53,\n\tMX6SX_PAD_LCD1_DATA02 = 54,\n\tMX6SX_PAD_LCD1_DATA03 = 55,\n\tMX6SX_PAD_LCD1_DATA04 = 56,\n\tMX6SX_PAD_LCD1_DATA05 = 57,\n\tMX6SX_PAD_LCD1_DATA06 = 58,\n\tMX6SX_PAD_LCD1_DATA07 = 59,\n\tMX6SX_PAD_LCD1_DATA08 = 60,\n\tMX6SX_PAD_LCD1_DATA09 = 61,\n\tMX6SX_PAD_LCD1_DATA10 = 62,\n\tMX6SX_PAD_LCD1_DATA11 = 63,\n\tMX6SX_PAD_LCD1_DATA12 = 64,\n\tMX6SX_PAD_LCD1_DATA13 = 65,\n\tMX6SX_PAD_LCD1_DATA14 = 66,\n\tMX6SX_PAD_LCD1_DATA15 = 67,\n\tMX6SX_PAD_LCD1_DATA16 = 68,\n\tMX6SX_PAD_LCD1_DATA17 = 69,\n\tMX6SX_PAD_LCD1_DATA18 = 70,\n\tMX6SX_PAD_LCD1_DATA19 = 71,\n\tMX6SX_PAD_LCD1_DATA20 = 72,\n\tMX6SX_PAD_LCD1_DATA21 = 73,\n\tMX6SX_PAD_LCD1_DATA22 = 74,\n\tMX6SX_PAD_LCD1_DATA23 = 75,\n\tMX6SX_PAD_LCD1_ENABLE = 76,\n\tMX6SX_PAD_LCD1_HSYNC = 77,\n\tMX6SX_PAD_LCD1_RESET = 78,\n\tMX6SX_PAD_LCD1_VSYNC = 79,\n\tMX6SX_PAD_NAND_ALE = 80,\n\tMX6SX_PAD_NAND_CE0_B = 81,\n\tMX6SX_PAD_NAND_CE1_B = 82,\n\tMX6SX_PAD_NAND_CLE = 83,\n\tMX6SX_PAD_NAND_DATA00 = 84,\n\tMX6SX_PAD_NAND_DATA01 = 85,\n\tMX6SX_PAD_NAND_DATA02 = 86,\n\tMX6SX_PAD_NAND_DATA03 = 87,\n\tMX6SX_PAD_NAND_DATA04 = 88,\n\tMX6SX_PAD_NAND_DATA05 = 89,\n\tMX6SX_PAD_NAND_DATA06 = 90,\n\tMX6SX_PAD_NAND_DATA07 = 91,\n\tMX6SX_PAD_NAND_RE_B = 92,\n\tMX6SX_PAD_NAND_READY_B = 93,\n\tMX6SX_PAD_NAND_WE_B = 94,\n\tMX6SX_PAD_NAND_WP_B = 95,\n\tMX6SX_PAD_QSPI1A_DATA0 = 96,\n\tMX6SX_PAD_QSPI1A_DATA1 = 97,\n\tMX6SX_PAD_QSPI1A_DATA2 = 98,\n\tMX6SX_PAD_QSPI1A_DATA3 = 99,\n\tMX6SX_PAD_QSPI1A_DQS = 100,\n\tMX6SX_PAD_QSPI1A_SCLK = 101,\n\tMX6SX_PAD_QSPI1A_SS0_B = 102,\n\tMX6SX_PAD_QSPI1A_SS1_B = 103,\n\tMX6SX_PAD_QSPI1B_DATA0 = 104,\n\tMX6SX_PAD_QSPI1B_DATA1 = 105,\n\tMX6SX_PAD_QSPI1B_DATA2 = 106,\n\tMX6SX_PAD_QSPI1B_DATA3 = 107,\n\tMX6SX_PAD_QSPI1B_DQS = 108,\n\tMX6SX_PAD_QSPI1B_SCLK = 109,\n\tMX6SX_PAD_QSPI1B_SS0_B = 110,\n\tMX6SX_PAD_QSPI1B_SS1_B = 111,\n\tMX6SX_PAD_RGMII1_RD0 = 112,\n\tMX6SX_PAD_RGMII1_RD1 = 113,\n\tMX6SX_PAD_RGMII1_RD2 = 114,\n\tMX6SX_PAD_RGMII1_RD3 = 115,\n\tMX6SX_PAD_RGMII1_RX_CTL = 116,\n\tMX6SX_PAD_RGMII1_RXC = 117,\n\tMX6SX_PAD_RGMII1_TD0 = 118,\n\tMX6SX_PAD_RGMII1_TD1 = 119,\n\tMX6SX_PAD_RGMII1_TD2 = 120,\n\tMX6SX_PAD_RGMII1_TD3 = 121,\n\tMX6SX_PAD_RGMII1_TX_CTL = 122,\n\tMX6SX_PAD_RGMII1_TXC = 123,\n\tMX6SX_PAD_RGMII2_RD0 = 124,\n\tMX6SX_PAD_RGMII2_RD1 = 125,\n\tMX6SX_PAD_RGMII2_RD2 = 126,\n\tMX6SX_PAD_RGMII2_RD3 = 127,\n\tMX6SX_PAD_RGMII2_RX_CTL = 128,\n\tMX6SX_PAD_RGMII2_RXC = 129,\n\tMX6SX_PAD_RGMII2_TD0 = 130,\n\tMX6SX_PAD_RGMII2_TD1 = 131,\n\tMX6SX_PAD_RGMII2_TD2 = 132,\n\tMX6SX_PAD_RGMII2_TD3 = 133,\n\tMX6SX_PAD_RGMII2_TX_CTL = 134,\n\tMX6SX_PAD_RGMII2_TXC = 135,\n\tMX6SX_PAD_SD1_CLK = 136,\n\tMX6SX_PAD_SD1_CMD = 137,\n\tMX6SX_PAD_SD1_DATA0 = 138,\n\tMX6SX_PAD_SD1_DATA1 = 139,\n\tMX6SX_PAD_SD1_DATA2 = 140,\n\tMX6SX_PAD_SD1_DATA3 = 141,\n\tMX6SX_PAD_SD2_CLK = 142,\n\tMX6SX_PAD_SD2_CMD = 143,\n\tMX6SX_PAD_SD2_DATA0 = 144,\n\tMX6SX_PAD_SD2_DATA1 = 145,\n\tMX6SX_PAD_SD2_DATA2 = 146,\n\tMX6SX_PAD_SD2_DATA3 = 147,\n\tMX6SX_PAD_SD3_CLK = 148,\n\tMX6SX_PAD_SD3_CMD = 149,\n\tMX6SX_PAD_SD3_DATA0 = 150,\n\tMX6SX_PAD_SD3_DATA1 = 151,\n\tMX6SX_PAD_SD3_DATA2 = 152,\n\tMX6SX_PAD_SD3_DATA3 = 153,\n\tMX6SX_PAD_SD3_DATA4 = 154,\n\tMX6SX_PAD_SD3_DATA5 = 155,\n\tMX6SX_PAD_SD3_DATA6 = 156,\n\tMX6SX_PAD_SD3_DATA7 = 157,\n\tMX6SX_PAD_SD4_CLK = 158,\n\tMX6SX_PAD_SD4_CMD = 159,\n\tMX6SX_PAD_SD4_DATA0 = 160,\n\tMX6SX_PAD_SD4_DATA1 = 161,\n\tMX6SX_PAD_SD4_DATA2 = 162,\n\tMX6SX_PAD_SD4_DATA3 = 163,\n\tMX6SX_PAD_SD4_DATA4 = 164,\n\tMX6SX_PAD_SD4_DATA5 = 165,\n\tMX6SX_PAD_SD4_DATA6 = 166,\n\tMX6SX_PAD_SD4_DATA7 = 167,\n\tMX6SX_PAD_SD4_RESET_B = 168,\n\tMX6SX_PAD_USB_H_DATA = 169,\n\tMX6SX_PAD_USB_H_STROBE = 170,\n};\n\nenum imx6ul_pads {\n\tMX6UL_PAD_RESERVE0 = 0,\n\tMX6UL_PAD_RESERVE1 = 1,\n\tMX6UL_PAD_RESERVE2 = 2,\n\tMX6UL_PAD_RESERVE3 = 3,\n\tMX6UL_PAD_RESERVE4 = 4,\n\tMX6UL_PAD_RESERVE5 = 5,\n\tMX6UL_PAD_RESERVE6 = 6,\n\tMX6UL_PAD_RESERVE7 = 7,\n\tMX6UL_PAD_RESERVE8 = 8,\n\tMX6UL_PAD_RESERVE9 = 9,\n\tMX6UL_PAD_RESERVE10 = 10,\n\tMX6UL_PAD_SNVS_TAMPER4 = 11,\n\tMX6UL_PAD_RESERVE12 = 12,\n\tMX6UL_PAD_RESERVE13 = 13,\n\tMX6UL_PAD_RESERVE14 = 14,\n\tMX6UL_PAD_RESERVE15 = 15,\n\tMX6UL_PAD_RESERVE16 = 16,\n\tMX6UL_PAD_JTAG_MOD = 17,\n\tMX6UL_PAD_JTAG_TMS = 18,\n\tMX6UL_PAD_JTAG_TDO = 19,\n\tMX6UL_PAD_JTAG_TDI = 20,\n\tMX6UL_PAD_JTAG_TCK = 21,\n\tMX6UL_PAD_JTAG_TRST_B = 22,\n\tMX6UL_PAD_GPIO1_IO00 = 23,\n\tMX6UL_PAD_GPIO1_IO01 = 24,\n\tMX6UL_PAD_GPIO1_IO02 = 25,\n\tMX6UL_PAD_GPIO1_IO03 = 26,\n\tMX6UL_PAD_GPIO1_IO04 = 27,\n\tMX6UL_PAD_GPIO1_IO05 = 28,\n\tMX6UL_PAD_GPIO1_IO06 = 29,\n\tMX6UL_PAD_GPIO1_IO07 = 30,\n\tMX6UL_PAD_GPIO1_IO08 = 31,\n\tMX6UL_PAD_GPIO1_IO09 = 32,\n\tMX6UL_PAD_UART1_TX_DATA = 33,\n\tMX6UL_PAD_UART1_RX_DATA = 34,\n\tMX6UL_PAD_UART1_CTS_B = 35,\n\tMX6UL_PAD_UART1_RTS_B = 36,\n\tMX6UL_PAD_UART2_TX_DATA = 37,\n\tMX6UL_PAD_UART2_RX_DATA = 38,\n\tMX6UL_PAD_UART2_CTS_B = 39,\n\tMX6UL_PAD_UART2_RTS_B = 40,\n\tMX6UL_PAD_UART3_TX_DATA = 41,\n\tMX6UL_PAD_UART3_RX_DATA = 42,\n\tMX6UL_PAD_UART3_CTS_B = 43,\n\tMX6UL_PAD_UART3_RTS_B = 44,\n\tMX6UL_PAD_UART4_TX_DATA = 45,\n\tMX6UL_PAD_UART4_RX_DATA = 46,\n\tMX6UL_PAD_UART5_TX_DATA = 47,\n\tMX6UL_PAD_UART5_RX_DATA = 48,\n\tMX6UL_PAD_ENET1_RX_DATA0 = 49,\n\tMX6UL_PAD_ENET1_RX_DATA1 = 50,\n\tMX6UL_PAD_ENET1_RX_EN = 51,\n\tMX6UL_PAD_ENET1_TX_DATA0 = 52,\n\tMX6UL_PAD_ENET1_TX_DATA1 = 53,\n\tMX6UL_PAD_ENET1_TX_EN = 54,\n\tMX6UL_PAD_ENET1_TX_CLK = 55,\n\tMX6UL_PAD_ENET1_RX_ER = 56,\n\tMX6UL_PAD_ENET2_RX_DATA0 = 57,\n\tMX6UL_PAD_ENET2_RX_DATA1 = 58,\n\tMX6UL_PAD_ENET2_RX_EN = 59,\n\tMX6UL_PAD_ENET2_TX_DATA0 = 60,\n\tMX6UL_PAD_ENET2_TX_DATA1 = 61,\n\tMX6UL_PAD_ENET2_TX_EN = 62,\n\tMX6UL_PAD_ENET2_TX_CLK = 63,\n\tMX6UL_PAD_ENET2_RX_ER = 64,\n\tMX6UL_PAD_LCD_CLK = 65,\n\tMX6UL_PAD_LCD_ENABLE = 66,\n\tMX6UL_PAD_LCD_HSYNC = 67,\n\tMX6UL_PAD_LCD_VSYNC = 68,\n\tMX6UL_PAD_LCD_RESET = 69,\n\tMX6UL_PAD_LCD_DATA00 = 70,\n\tMX6UL_PAD_LCD_DATA01 = 71,\n\tMX6UL_PAD_LCD_DATA02 = 72,\n\tMX6UL_PAD_LCD_DATA03 = 73,\n\tMX6UL_PAD_LCD_DATA04 = 74,\n\tMX6UL_PAD_LCD_DATA05 = 75,\n\tMX6UL_PAD_LCD_DATA06 = 76,\n\tMX6UL_PAD_LCD_DATA07 = 77,\n\tMX6UL_PAD_LCD_DATA08 = 78,\n\tMX6UL_PAD_LCD_DATA09 = 79,\n\tMX6UL_PAD_LCD_DATA10 = 80,\n\tMX6UL_PAD_LCD_DATA11 = 81,\n\tMX6UL_PAD_LCD_DATA12 = 82,\n\tMX6UL_PAD_LCD_DATA13 = 83,\n\tMX6UL_PAD_LCD_DATA14 = 84,\n\tMX6UL_PAD_LCD_DATA15 = 85,\n\tMX6UL_PAD_LCD_DATA16 = 86,\n\tMX6UL_PAD_LCD_DATA17 = 87,\n\tMX6UL_PAD_LCD_DATA18 = 88,\n\tMX6UL_PAD_LCD_DATA19 = 89,\n\tMX6UL_PAD_LCD_DATA20 = 90,\n\tMX6UL_PAD_LCD_DATA21 = 91,\n\tMX6UL_PAD_LCD_DATA22 = 92,\n\tMX6UL_PAD_LCD_DATA23 = 93,\n\tMX6UL_PAD_NAND_RE_B = 94,\n\tMX6UL_PAD_NAND_WE_B = 95,\n\tMX6UL_PAD_NAND_DATA00 = 96,\n\tMX6UL_PAD_NAND_DATA01 = 97,\n\tMX6UL_PAD_NAND_DATA02 = 98,\n\tMX6UL_PAD_NAND_DATA03 = 99,\n\tMX6UL_PAD_NAND_DATA04 = 100,\n\tMX6UL_PAD_NAND_DATA05 = 101,\n\tMX6UL_PAD_NAND_DATA06 = 102,\n\tMX6UL_PAD_NAND_DATA07 = 103,\n\tMX6UL_PAD_NAND_ALE = 104,\n\tMX6UL_PAD_NAND_WP_B = 105,\n\tMX6UL_PAD_NAND_READY_B = 106,\n\tMX6UL_PAD_NAND_CE0_B = 107,\n\tMX6UL_PAD_NAND_CE1_B = 108,\n\tMX6UL_PAD_NAND_CLE = 109,\n\tMX6UL_PAD_NAND_DQS = 110,\n\tMX6UL_PAD_SD1_CMD = 111,\n\tMX6UL_PAD_SD1_CLK = 112,\n\tMX6UL_PAD_SD1_DATA0 = 113,\n\tMX6UL_PAD_SD1_DATA1 = 114,\n\tMX6UL_PAD_SD1_DATA2 = 115,\n\tMX6UL_PAD_SD1_DATA3 = 116,\n\tMX6UL_PAD_CSI_MCLK = 117,\n\tMX6UL_PAD_CSI_PIXCLK = 118,\n\tMX6UL_PAD_CSI_VSYNC = 119,\n\tMX6UL_PAD_CSI_HSYNC = 120,\n\tMX6UL_PAD_CSI_DATA00 = 121,\n\tMX6UL_PAD_CSI_DATA01 = 122,\n\tMX6UL_PAD_CSI_DATA02 = 123,\n\tMX6UL_PAD_CSI_DATA03 = 124,\n\tMX6UL_PAD_CSI_DATA04 = 125,\n\tMX6UL_PAD_CSI_DATA05 = 126,\n\tMX6UL_PAD_CSI_DATA06 = 127,\n\tMX6UL_PAD_CSI_DATA07 = 128,\n};\n\nenum imx6ull_lpsr_pads {\n\tMX6ULL_PAD_BOOT_MODE0 = 0,\n\tMX6ULL_PAD_BOOT_MODE1 = 1,\n\tMX6ULL_PAD_SNVS_TAMPER0 = 2,\n\tMX6ULL_PAD_SNVS_TAMPER1 = 3,\n\tMX6ULL_PAD_SNVS_TAMPER2 = 4,\n\tMX6ULL_PAD_SNVS_TAMPER3 = 5,\n\tMX6ULL_PAD_SNVS_TAMPER4 = 6,\n\tMX6ULL_PAD_SNVS_TAMPER5 = 7,\n\tMX6ULL_PAD_SNVS_TAMPER6 = 8,\n\tMX6ULL_PAD_SNVS_TAMPER7 = 9,\n\tMX6ULL_PAD_SNVS_TAMPER8 = 10,\n\tMX6ULL_PAD_SNVS_TAMPER9 = 11,\n};\n\nenum imx7_src_registers {\n\tSRC_A7RCR0 = 4,\n\tSRC_M4RCR = 12,\n\tSRC_ERCR = 20,\n\tSRC_HSICPHY_RCR = 28,\n\tSRC_USBOPHY1_RCR = 32,\n\tSRC_USBOPHY2_RCR = 36,\n\tSRC_MIPIPHY_RCR = 40,\n\tSRC_PCIEPHY_RCR = 44,\n\tSRC_DDRC_RCR = 4096,\n};\n\nenum imx7d_lpsr_pads {\n\tMX7D_PAD_GPIO1_IO00 = 0,\n\tMX7D_PAD_GPIO1_IO01 = 1,\n\tMX7D_PAD_GPIO1_IO02 = 2,\n\tMX7D_PAD_GPIO1_IO03 = 3,\n\tMX7D_PAD_GPIO1_IO04 = 4,\n\tMX7D_PAD_GPIO1_IO05 = 5,\n\tMX7D_PAD_GPIO1_IO06 = 6,\n\tMX7D_PAD_GPIO1_IO07 = 7,\n};\n\nenum imx7d_pads {\n\tMX7D_PAD_RESERVE0 = 0,\n\tMX7D_PAD_RESERVE1 = 1,\n\tMX7D_PAD_RESERVE2 = 2,\n\tMX7D_PAD_RESERVE3 = 3,\n\tMX7D_PAD_RESERVE4 = 4,\n\tMX7D_PAD_GPIO1_IO08 = 5,\n\tMX7D_PAD_GPIO1_IO09 = 6,\n\tMX7D_PAD_GPIO1_IO10 = 7,\n\tMX7D_PAD_GPIO1_IO11 = 8,\n\tMX7D_PAD_GPIO1_IO12 = 9,\n\tMX7D_PAD_GPIO1_IO13 = 10,\n\tMX7D_PAD_GPIO1_IO14 = 11,\n\tMX7D_PAD_GPIO1_IO15 = 12,\n\tMX7D_PAD_EPDC_DATA00 = 13,\n\tMX7D_PAD_EPDC_DATA01 = 14,\n\tMX7D_PAD_EPDC_DATA02 = 15,\n\tMX7D_PAD_EPDC_DATA03 = 16,\n\tMX7D_PAD_EPDC_DATA04 = 17,\n\tMX7D_PAD_EPDC_DATA05 = 18,\n\tMX7D_PAD_EPDC_DATA06 = 19,\n\tMX7D_PAD_EPDC_DATA07 = 20,\n\tMX7D_PAD_EPDC_DATA08 = 21,\n\tMX7D_PAD_EPDC_DATA09 = 22,\n\tMX7D_PAD_EPDC_DATA10 = 23,\n\tMX7D_PAD_EPDC_DATA11 = 24,\n\tMX7D_PAD_EPDC_DATA12 = 25,\n\tMX7D_PAD_EPDC_DATA13 = 26,\n\tMX7D_PAD_EPDC_DATA14 = 27,\n\tMX7D_PAD_EPDC_DATA15 = 28,\n\tMX7D_PAD_EPDC_SDCLK = 29,\n\tMX7D_PAD_EPDC_SDLE = 30,\n\tMX7D_PAD_EPDC_SDOE = 31,\n\tMX7D_PAD_EPDC_SDSHR = 32,\n\tMX7D_PAD_EPDC_SDCE0 = 33,\n\tMX7D_PAD_EPDC_SDCE1 = 34,\n\tMX7D_PAD_EPDC_SDCE2 = 35,\n\tMX7D_PAD_EPDC_SDCE3 = 36,\n\tMX7D_PAD_EPDC_GDCLK = 37,\n\tMX7D_PAD_EPDC_GDOE = 38,\n\tMX7D_PAD_EPDC_GDRL = 39,\n\tMX7D_PAD_EPDC_GDSP = 40,\n\tMX7D_PAD_EPDC_BDR0 = 41,\n\tMX7D_PAD_EPDC_BDR1 = 42,\n\tMX7D_PAD_EPDC_PWR_COM = 43,\n\tMX7D_PAD_EPDC_PWR_STAT = 44,\n\tMX7D_PAD_LCD_CLK = 45,\n\tMX7D_PAD_LCD_ENABLE = 46,\n\tMX7D_PAD_LCD_HSYNC = 47,\n\tMX7D_PAD_LCD_VSYNC = 48,\n\tMX7D_PAD_LCD_RESET = 49,\n\tMX7D_PAD_LCD_DATA00 = 50,\n\tMX7D_PAD_LCD_DATA01 = 51,\n\tMX7D_PAD_LCD_DATA02 = 52,\n\tMX7D_PAD_LCD_DATA03 = 53,\n\tMX7D_PAD_LCD_DATA04 = 54,\n\tMX7D_PAD_LCD_DATA05 = 55,\n\tMX7D_PAD_LCD_DATA06 = 56,\n\tMX7D_PAD_LCD_DATA07 = 57,\n\tMX7D_PAD_LCD_DATA08 = 58,\n\tMX7D_PAD_LCD_DATA09 = 59,\n\tMX7D_PAD_LCD_DATA10 = 60,\n\tMX7D_PAD_LCD_DATA11 = 61,\n\tMX7D_PAD_LCD_DATA12 = 62,\n\tMX7D_PAD_LCD_DATA13 = 63,\n\tMX7D_PAD_LCD_DATA14 = 64,\n\tMX7D_PAD_LCD_DATA15 = 65,\n\tMX7D_PAD_LCD_DATA16 = 66,\n\tMX7D_PAD_LCD_DATA17 = 67,\n\tMX7D_PAD_LCD_DATA18 = 68,\n\tMX7D_PAD_LCD_DATA19 = 69,\n\tMX7D_PAD_LCD_DATA20 = 70,\n\tMX7D_PAD_LCD_DATA21 = 71,\n\tMX7D_PAD_LCD_DATA22 = 72,\n\tMX7D_PAD_LCD_DATA23 = 73,\n\tMX7D_PAD_UART1_RX_DATA = 74,\n\tMX7D_PAD_UART1_TX_DATA = 75,\n\tMX7D_PAD_UART2_RX_DATA = 76,\n\tMX7D_PAD_UART2_TX_DATA = 77,\n\tMX7D_PAD_UART3_RX_DATA = 78,\n\tMX7D_PAD_UART3_TX_DATA = 79,\n\tMX7D_PAD_UART3_RTS_B = 80,\n\tMX7D_PAD_UART3_CTS_B = 81,\n\tMX7D_PAD_I2C1_SCL = 82,\n\tMX7D_PAD_I2C1_SDA = 83,\n\tMX7D_PAD_I2C2_SCL = 84,\n\tMX7D_PAD_I2C2_SDA = 85,\n\tMX7D_PAD_I2C3_SCL = 86,\n\tMX7D_PAD_I2C3_SDA = 87,\n\tMX7D_PAD_I2C4_SCL = 88,\n\tMX7D_PAD_I2C4_SDA = 89,\n\tMX7D_PAD_ECSPI1_SCLK = 90,\n\tMX7D_PAD_ECSPI1_MOSI = 91,\n\tMX7D_PAD_ECSPI1_MISO = 92,\n\tMX7D_PAD_ECSPI1_SS0 = 93,\n\tMX7D_PAD_ECSPI2_SCLK = 94,\n\tMX7D_PAD_ECSPI2_MOSI = 95,\n\tMX7D_PAD_ECSPI2_MISO = 96,\n\tMX7D_PAD_ECSPI2_SS0 = 97,\n\tMX7D_PAD_SD1_CD_B = 98,\n\tMX7D_PAD_SD1_WP = 99,\n\tMX7D_PAD_SD1_RESET_B = 100,\n\tMX7D_PAD_SD1_CLK = 101,\n\tMX7D_PAD_SD1_CMD = 102,\n\tMX7D_PAD_SD1_DATA0 = 103,\n\tMX7D_PAD_SD1_DATA1 = 104,\n\tMX7D_PAD_SD1_DATA2 = 105,\n\tMX7D_PAD_SD1_DATA3 = 106,\n\tMX7D_PAD_SD2_CD_B = 107,\n\tMX7D_PAD_SD2_WP = 108,\n\tMX7D_PAD_SD2_RESET_B = 109,\n\tMX7D_PAD_SD2_CLK = 110,\n\tMX7D_PAD_SD2_CMD = 111,\n\tMX7D_PAD_SD2_DATA0 = 112,\n\tMX7D_PAD_SD2_DATA1 = 113,\n\tMX7D_PAD_SD2_DATA2 = 114,\n\tMX7D_PAD_SD2_DATA3 = 115,\n\tMX7D_PAD_SD3_CLK = 116,\n\tMX7D_PAD_SD3_CMD = 117,\n\tMX7D_PAD_SD3_DATA0 = 118,\n\tMX7D_PAD_SD3_DATA1 = 119,\n\tMX7D_PAD_SD3_DATA2 = 120,\n\tMX7D_PAD_SD3_DATA3 = 121,\n\tMX7D_PAD_SD3_DATA4 = 122,\n\tMX7D_PAD_SD3_DATA5 = 123,\n\tMX7D_PAD_SD3_DATA6 = 124,\n\tMX7D_PAD_SD3_DATA7 = 125,\n\tMX7D_PAD_SD3_STROBE = 126,\n\tMX7D_PAD_SD3_RESET_B = 127,\n\tMX7D_PAD_SAI1_RX_DATA = 128,\n\tMX7D_PAD_SAI1_TX_BCLK = 129,\n\tMX7D_PAD_SAI1_TX_SYNC = 130,\n\tMX7D_PAD_SAI1_TX_DATA = 131,\n\tMX7D_PAD_SAI1_RX_SYNC = 132,\n\tMX7D_PAD_SAI1_RX_BCLK = 133,\n\tMX7D_PAD_SAI1_MCLK = 134,\n\tMX7D_PAD_SAI2_TX_SYNC = 135,\n\tMX7D_PAD_SAI2_TX_BCLK = 136,\n\tMX7D_PAD_SAI2_RX_DATA = 137,\n\tMX7D_PAD_SAI2_TX_DATA = 138,\n\tMX7D_PAD_ENET1_RGMII_RD0 = 139,\n\tMX7D_PAD_ENET1_RGMII_RD1 = 140,\n\tMX7D_PAD_ENET1_RGMII_RD2 = 141,\n\tMX7D_PAD_ENET1_RGMII_RD3 = 142,\n\tMX7D_PAD_ENET1_RGMII_RX_CTL = 143,\n\tMX7D_PAD_ENET1_RGMII_RXC = 144,\n\tMX7D_PAD_ENET1_RGMII_TD0 = 145,\n\tMX7D_PAD_ENET1_RGMII_TD1 = 146,\n\tMX7D_PAD_ENET1_RGMII_TD2 = 147,\n\tMX7D_PAD_ENET1_RGMII_TD3 = 148,\n\tMX7D_PAD_ENET1_RGMII_TX_CTL = 149,\n\tMX7D_PAD_ENET1_RGMII_TXC = 150,\n\tMX7D_PAD_ENET1_TX_CLK = 151,\n\tMX7D_PAD_ENET1_RX_CLK = 152,\n\tMX7D_PAD_ENET1_CRS = 153,\n\tMX7D_PAD_ENET1_COL = 154,\n};\n\nenum imx7ulp_pads {\n\tIMX7ULP_PAD_PTC0 = 0,\n\tIMX7ULP_PAD_PTC1 = 1,\n\tIMX7ULP_PAD_PTC2 = 2,\n\tIMX7ULP_PAD_PTC3 = 3,\n\tIMX7ULP_PAD_PTC4 = 4,\n\tIMX7ULP_PAD_PTC5 = 5,\n\tIMX7ULP_PAD_PTC6 = 6,\n\tIMX7ULP_PAD_PTC7 = 7,\n\tIMX7ULP_PAD_PTC8 = 8,\n\tIMX7ULP_PAD_PTC9 = 9,\n\tIMX7ULP_PAD_PTC10 = 10,\n\tIMX7ULP_PAD_PTC11 = 11,\n\tIMX7ULP_PAD_PTC12 = 12,\n\tIMX7ULP_PAD_PTC13 = 13,\n\tIMX7ULP_PAD_PTC14 = 14,\n\tIMX7ULP_PAD_PTC15 = 15,\n\tIMX7ULP_PAD_PTC16 = 16,\n\tIMX7ULP_PAD_PTC17 = 17,\n\tIMX7ULP_PAD_PTC18 = 18,\n\tIMX7ULP_PAD_PTC19 = 19,\n\tIMX7ULP_PAD_RESERVE0 = 20,\n\tIMX7ULP_PAD_RESERVE1 = 21,\n\tIMX7ULP_PAD_RESERVE2 = 22,\n\tIMX7ULP_PAD_RESERVE3 = 23,\n\tIMX7ULP_PAD_RESERVE4 = 24,\n\tIMX7ULP_PAD_RESERVE5 = 25,\n\tIMX7ULP_PAD_RESERVE6 = 26,\n\tIMX7ULP_PAD_RESERVE7 = 27,\n\tIMX7ULP_PAD_RESERVE8 = 28,\n\tIMX7ULP_PAD_RESERVE9 = 29,\n\tIMX7ULP_PAD_RESERVE10 = 30,\n\tIMX7ULP_PAD_RESERVE11 = 31,\n\tIMX7ULP_PAD_PTD0 = 32,\n\tIMX7ULP_PAD_PTD1 = 33,\n\tIMX7ULP_PAD_PTD2 = 34,\n\tIMX7ULP_PAD_PTD3 = 35,\n\tIMX7ULP_PAD_PTD4 = 36,\n\tIMX7ULP_PAD_PTD5 = 37,\n\tIMX7ULP_PAD_PTD6 = 38,\n\tIMX7ULP_PAD_PTD7 = 39,\n\tIMX7ULP_PAD_PTD8 = 40,\n\tIMX7ULP_PAD_PTD9 = 41,\n\tIMX7ULP_PAD_PTD10 = 42,\n\tIMX7ULP_PAD_PTD11 = 43,\n\tIMX7ULP_PAD_RESERVE12 = 44,\n\tIMX7ULP_PAD_RESERVE13 = 45,\n\tIMX7ULP_PAD_RESERVE14 = 46,\n\tIMX7ULP_PAD_RESERVE15 = 47,\n\tIMX7ULP_PAD_RESERVE16 = 48,\n\tIMX7ULP_PAD_RESERVE17 = 49,\n\tIMX7ULP_PAD_RESERVE18 = 50,\n\tIMX7ULP_PAD_RESERVE19 = 51,\n\tIMX7ULP_PAD_RESERVE20 = 52,\n\tIMX7ULP_PAD_RESERVE21 = 53,\n\tIMX7ULP_PAD_RESERVE22 = 54,\n\tIMX7ULP_PAD_RESERVE23 = 55,\n\tIMX7ULP_PAD_RESERVE24 = 56,\n\tIMX7ULP_PAD_RESERVE25 = 57,\n\tIMX7ULP_PAD_RESERVE26 = 58,\n\tIMX7ULP_PAD_RESERVE27 = 59,\n\tIMX7ULP_PAD_RESERVE28 = 60,\n\tIMX7ULP_PAD_RESERVE29 = 61,\n\tIMX7ULP_PAD_RESERVE30 = 62,\n\tIMX7ULP_PAD_RESERVE31 = 63,\n\tIMX7ULP_PAD_PTE0 = 64,\n\tIMX7ULP_PAD_PTE1 = 65,\n\tIMX7ULP_PAD_PTE2 = 66,\n\tIMX7ULP_PAD_PTE3 = 67,\n\tIMX7ULP_PAD_PTE4 = 68,\n\tIMX7ULP_PAD_PTE5 = 69,\n\tIMX7ULP_PAD_PTE6 = 70,\n\tIMX7ULP_PAD_PTE7 = 71,\n\tIMX7ULP_PAD_PTE8 = 72,\n\tIMX7ULP_PAD_PTE9 = 73,\n\tIMX7ULP_PAD_PTE10 = 74,\n\tIMX7ULP_PAD_PTE11 = 75,\n\tIMX7ULP_PAD_PTE12 = 76,\n\tIMX7ULP_PAD_PTE13 = 77,\n\tIMX7ULP_PAD_PTE14 = 78,\n\tIMX7ULP_PAD_PTE15 = 79,\n\tIMX7ULP_PAD_RESERVE32 = 80,\n\tIMX7ULP_PAD_RESERVE33 = 81,\n\tIMX7ULP_PAD_RESERVE34 = 82,\n\tIMX7ULP_PAD_RESERVE35 = 83,\n\tIMX7ULP_PAD_RESERVE36 = 84,\n\tIMX7ULP_PAD_RESERVE37 = 85,\n\tIMX7ULP_PAD_RESERVE38 = 86,\n\tIMX7ULP_PAD_RESERVE39 = 87,\n\tIMX7ULP_PAD_RESERVE40 = 88,\n\tIMX7ULP_PAD_RESERVE41 = 89,\n\tIMX7ULP_PAD_RESERVE42 = 90,\n\tIMX7ULP_PAD_RESERVE43 = 91,\n\tIMX7ULP_PAD_RESERVE44 = 92,\n\tIMX7ULP_PAD_RESERVE45 = 93,\n\tIMX7ULP_PAD_RESERVE46 = 94,\n\tIMX7ULP_PAD_RESERVE47 = 95,\n\tIMX7ULP_PAD_PTF0 = 96,\n\tIMX7ULP_PAD_PTF1 = 97,\n\tIMX7ULP_PAD_PTF2 = 98,\n\tIMX7ULP_PAD_PTF3 = 99,\n\tIMX7ULP_PAD_PTF4 = 100,\n\tIMX7ULP_PAD_PTF5 = 101,\n\tIMX7ULP_PAD_PTF6 = 102,\n\tIMX7ULP_PAD_PTF7 = 103,\n\tIMX7ULP_PAD_PTF8 = 104,\n\tIMX7ULP_PAD_PTF9 = 105,\n\tIMX7ULP_PAD_PTF10 = 106,\n\tIMX7ULP_PAD_PTF11 = 107,\n\tIMX7ULP_PAD_PTF12 = 108,\n\tIMX7ULP_PAD_PTF13 = 109,\n\tIMX7ULP_PAD_PTF14 = 110,\n\tIMX7ULP_PAD_PTF15 = 111,\n\tIMX7ULP_PAD_PTF16 = 112,\n\tIMX7ULP_PAD_PTF17 = 113,\n\tIMX7ULP_PAD_PTF18 = 114,\n\tIMX7ULP_PAD_PTF19 = 115,\n};\n\nenum imx8mp_src_registers {\n\tSRC_SUPERMIX_RCR = 24,\n\tSRC_AUDIOMIX_RCR = 28,\n\tSRC_MLMIX_RCR = 40,\n\tSRC_GPU2D_RCR = 56,\n\tSRC_GPU3D_RCR = 60,\n\tSRC_VPU_G1_RCR = 72,\n\tSRC_VPU_G2_RCR = 76,\n\tSRC_VPUVC8KE_RCR = 80,\n\tSRC_NOC_RCR = 84,\n};\n\nenum imx8mq_src_registers {\n\tSRC_A53RCR0 = 4,\n\tSRC_HDMI_RCR = 48,\n\tSRC_DISP_RCR = 52,\n\tSRC_GPU_RCR = 64,\n\tSRC_VPU_RCR = 68,\n\tSRC_PCIE2_RCR = 72,\n\tSRC_MIPIPHY1_RCR = 76,\n\tSRC_MIPIPHY2_RCR = 80,\n\tSRC_DDRC2_RCR = 4100,\n};\n\nenum imx8ulp_pads {\n\tIMX8ULP_PAD_PTD0 = 0,\n\tIMX8ULP_PAD_PTD1 = 1,\n\tIMX8ULP_PAD_PTD2 = 2,\n\tIMX8ULP_PAD_PTD3 = 3,\n\tIMX8ULP_PAD_PTD4 = 4,\n\tIMX8ULP_PAD_PTD5 = 5,\n\tIMX8ULP_PAD_PTD6 = 6,\n\tIMX8ULP_PAD_PTD7 = 7,\n\tIMX8ULP_PAD_PTD8 = 8,\n\tIMX8ULP_PAD_PTD9 = 9,\n\tIMX8ULP_PAD_PTD10 = 10,\n\tIMX8ULP_PAD_PTD11 = 11,\n\tIMX8ULP_PAD_PTD12 = 12,\n\tIMX8ULP_PAD_PTD13 = 13,\n\tIMX8ULP_PAD_PTD14 = 14,\n\tIMX8ULP_PAD_PTD15 = 15,\n\tIMX8ULP_PAD_PTD16 = 16,\n\tIMX8ULP_PAD_PTD17 = 17,\n\tIMX8ULP_PAD_PTD18 = 18,\n\tIMX8ULP_PAD_PTD19 = 19,\n\tIMX8ULP_PAD_PTD20 = 20,\n\tIMX8ULP_PAD_PTD21 = 21,\n\tIMX8ULP_PAD_PTD22 = 22,\n\tIMX8ULP_PAD_PTD23 = 23,\n\tIMX8ULP_PAD_RESERVE0 = 24,\n\tIMX8ULP_PAD_RESERVE1 = 25,\n\tIMX8ULP_PAD_RESERVE2 = 26,\n\tIMX8ULP_PAD_RESERVE3 = 27,\n\tIMX8ULP_PAD_RESERVE4 = 28,\n\tIMX8ULP_PAD_RESERVE5 = 29,\n\tIMX8ULP_PAD_RESERVE6 = 30,\n\tIMX8ULP_PAD_RESERVE7 = 31,\n\tIMX8ULP_PAD_PTE0 = 32,\n\tIMX8ULP_PAD_PTE1 = 33,\n\tIMX8ULP_PAD_PTE2 = 34,\n\tIMX8ULP_PAD_PTE3 = 35,\n\tIMX8ULP_PAD_PTE4 = 36,\n\tIMX8ULP_PAD_PTE5 = 37,\n\tIMX8ULP_PAD_PTE6 = 38,\n\tIMX8ULP_PAD_PTE7 = 39,\n\tIMX8ULP_PAD_PTE8 = 40,\n\tIMX8ULP_PAD_PTE9 = 41,\n\tIMX8ULP_PAD_PTE10 = 42,\n\tIMX8ULP_PAD_PTE11 = 43,\n\tIMX8ULP_PAD_PTE12 = 44,\n\tIMX8ULP_PAD_PTE13 = 45,\n\tIMX8ULP_PAD_PTE14 = 46,\n\tIMX8ULP_PAD_PTE15 = 47,\n\tIMX8ULP_PAD_PTE16 = 48,\n\tIMX8ULP_PAD_PTE17 = 49,\n\tIMX8ULP_PAD_PTE18 = 50,\n\tIMX8ULP_PAD_PTE19 = 51,\n\tIMX8ULP_PAD_PTE20 = 52,\n\tIMX8ULP_PAD_PTE21 = 53,\n\tIMX8ULP_PAD_PTE22 = 54,\n\tIMX8ULP_PAD_PTE23 = 55,\n\tIMX8ULP_PAD_RESERVE8 = 56,\n\tIMX8ULP_PAD_RESERVE9 = 57,\n\tIMX8ULP_PAD_RESERVE10 = 58,\n\tIMX8ULP_PAD_RESERVE11 = 59,\n\tIMX8ULP_PAD_RESERVE12 = 60,\n\tIMX8ULP_PAD_RESERVE13 = 61,\n\tIMX8ULP_PAD_RESERVE14 = 62,\n\tIMX8ULP_PAD_RESERVE15 = 63,\n\tIMX8ULP_PAD_PTF0 = 64,\n\tIMX8ULP_PAD_PTF1 = 65,\n\tIMX8ULP_PAD_PTF2 = 66,\n\tIMX8ULP_PAD_PTF3 = 67,\n\tIMX8ULP_PAD_PTF4 = 68,\n\tIMX8ULP_PAD_PTF5 = 69,\n\tIMX8ULP_PAD_PTF6 = 70,\n\tIMX8ULP_PAD_PTF7 = 71,\n\tIMX8ULP_PAD_PTF8 = 72,\n\tIMX8ULP_PAD_PTF9 = 73,\n\tIMX8ULP_PAD_PTF10 = 74,\n\tIMX8ULP_PAD_PTF11 = 75,\n\tIMX8ULP_PAD_PTF12 = 76,\n\tIMX8ULP_PAD_PTF13 = 77,\n\tIMX8ULP_PAD_PTF14 = 78,\n\tIMX8ULP_PAD_PTF15 = 79,\n\tIMX8ULP_PAD_PTF16 = 80,\n\tIMX8ULP_PAD_PTF17 = 81,\n\tIMX8ULP_PAD_PTF18 = 82,\n\tIMX8ULP_PAD_PTF19 = 83,\n\tIMX8ULP_PAD_PTF20 = 84,\n\tIMX8ULP_PAD_PTF21 = 85,\n\tIMX8ULP_PAD_PTF22 = 86,\n\tIMX8ULP_PAD_PTF23 = 87,\n\tIMX8ULP_PAD_PTF24 = 88,\n\tIMX8ULP_PAD_PTF25 = 89,\n\tIMX8ULP_PAD_PTF26 = 90,\n\tIMX8ULP_PAD_PTF27 = 91,\n\tIMX8ULP_PAD_PTF28 = 92,\n\tIMX8ULP_PAD_PTF29 = 93,\n\tIMX8ULP_PAD_PTF30 = 94,\n\tIMX8ULP_PAD_PTF31 = 95,\n};\n\nenum imx_dma_prio {\n\tDMA_PRIO_HIGH = 0,\n\tDMA_PRIO_MEDIUM = 1,\n\tDMA_PRIO_LOW = 2,\n};\n\nenum imx_dma_type {\n\tIMX1_DMA = 0,\n\tIMX27_DMA = 1,\n};\n\nenum imx_gpt_type {\n\tGPT_TYPE_IMX1 = 0,\n\tGPT_TYPE_IMX21 = 1,\n\tGPT_TYPE_IMX31 = 2,\n\tGPT_TYPE_IMX6DL = 3,\n};\n\nenum imx_i2c_state {\n\tIMX_I2C_STATE_DONE = 0,\n\tIMX_I2C_STATE_FAILED = 1,\n\tIMX_I2C_STATE_WRITE = 2,\n\tIMX_I2C_STATE_DMA = 3,\n\tIMX_I2C_STATE_READ = 4,\n\tIMX_I2C_STATE_READ_CONTINUE = 5,\n\tIMX_I2C_STATE_READ_BLOCK_DATA = 6,\n\tIMX_I2C_STATE_READ_BLOCK_DATA_LEN = 7,\n};\n\nenum imx_i2c_type {\n\tIMX1_I2C = 0,\n\tIMX21_I2C = 1,\n\tS32G_I2C = 2,\n\tVF610_I2C = 3,\n};\n\nenum imx_pfdv2_type {\n\tIMX_PFDV2_IMX7ULP = 0,\n\tIMX_PFDV2_IMX8ULP = 1,\n};\n\nenum imx_pll14xx_type {\n\tPLL_1416X = 0,\n\tPLL_1443X = 1,\n};\n\nenum imx_pllv1_type {\n\tIMX_PLLV1_IMX1 = 0,\n\tIMX_PLLV1_IMX21 = 1,\n\tIMX_PLLV1_IMX25 = 2,\n\tIMX_PLLV1_IMX27 = 3,\n\tIMX_PLLV1_IMX31 = 4,\n\tIMX_PLLV1_IMX35 = 5,\n};\n\nenum imx_pllv3_type {\n\tIMX_PLLV3_GENERIC = 0,\n\tIMX_PLLV3_SYS = 1,\n\tIMX_PLLV3_USB = 2,\n\tIMX_PLLV3_USB_VF610 = 3,\n\tIMX_PLLV3_AV = 4,\n\tIMX_PLLV3_ENET = 5,\n\tIMX_PLLV3_ENET_IMX7 = 6,\n\tIMX_PLLV3_SYS_VF610 = 7,\n\tIMX_PLLV3_DDR_IMX7 = 8,\n\tIMX_PLLV3_AV_IMX7 = 9,\n};\n\nenum imx_pllv4_type {\n\tIMX_PLLV4_IMX7ULP = 0,\n\tIMX_PLLV4_IMX8ULP = 1,\n\tIMX_PLLV4_IMX8ULP_1GHZ = 2,\n};\n\nenum imx_thermal_trip {\n\tIMX_TRIP_PASSIVE = 0,\n\tIMX_TRIP_CRITICAL = 1,\n};\n\nenum imx_tx_state {\n\tOFF = 0,\n\tWAIT_AFTER_RTS = 1,\n\tSEND = 2,\n\tWAIT_AFTER_SEND = 3,\n};\n\nenum imx_uart_type {\n\tIMX1_UART = 0,\n\tIMX21_UART = 1,\n};\n\nenum imxdma_prep_type {\n\tIMXDMA_DESC_MEMCPY = 0,\n\tIMXDMA_DESC_INTERLEAVED = 1,\n\tIMXDMA_DESC_SLAVE_SG = 2,\n\tIMXDMA_DESC_CYCLIC = 3,\n};\n\nenum in6_addr_gen_mode {\n\tIN6_ADDR_GEN_MODE_EUI64 = 0,\n\tIN6_ADDR_GEN_MODE_NONE = 1,\n\tIN6_ADDR_GEN_MODE_STABLE_PRIVACY = 2,\n\tIN6_ADDR_GEN_MODE_RANDOM = 3,\n};\n\nenum inband_type {\n\tINBAND_NONE = 0,\n\tINBAND_CISCO_SGMII = 1,\n\tINBAND_BASEX = 2,\n};\n\nenum index_mutex_classed {\n\tINDEX_MUTEX_I30 = 0,\n\tINDEX_MUTEX_SII = 1,\n\tINDEX_MUTEX_SDH = 2,\n\tINDEX_MUTEX_SO = 3,\n\tINDEX_MUTEX_SQ = 4,\n\tINDEX_MUTEX_SR = 5,\n\tINDEX_MUTEX_TOTAL = 6,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum io_pgtable_caps {\n\tIO_PGTABLE_CAP_CUSTOM_ALLOCATOR = 1,\n};\n\nenum io_pgtable_fmt {\n\tARM_32_LPAE_S1 = 0,\n\tARM_32_LPAE_S2 = 1,\n\tARM_64_LPAE_S1 = 2,\n\tARM_64_LPAE_S2 = 3,\n\tARM_V7S = 4,\n\tARM_MALI_LPAE = 5,\n\tAPPLE_DART = 6,\n\tAPPLE_DART2 = 7,\n\tIO_PGTABLE_NUM_FMTS = 8,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioam6_event_attr {\n\tIOAM6_EVENT_ATTR_UNSPEC = 0,\n\tIOAM6_EVENT_ATTR_TRACE_NAMESPACE = 1,\n\tIOAM6_EVENT_ATTR_TRACE_NODELEN = 2,\n\tIOAM6_EVENT_ATTR_TRACE_TYPE = 3,\n\tIOAM6_EVENT_ATTR_TRACE_DATA = 4,\n\t__IOAM6_EVENT_ATTR_MAX = 5,\n};\n\nenum ioam6_event_type {\n\tIOAM6_EVENT_UNSPEC = 0,\n\tIOAM6_EVENT_TRACE = 1,\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_NOEXEC = 1,\n\tIOMMU_CAP_PRE_BOOT_PROTECTION = 2,\n\tIOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3,\n\tIOMMU_CAP_DEFERRED_FLUSH = 4,\n\tIOMMU_CAP_DIRTY_TRACKING = 5,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum iommu_hw_info_type {\n\tIOMMU_HW_INFO_TYPE_NONE = 0,\n\tIOMMU_HW_INFO_TYPE_DEFAULT = 0,\n\tIOMMU_HW_INFO_TYPE_INTEL_VTD = 1,\n\tIOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,\n\tIOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,\n\tIOMMU_HW_INFO_TYPE_AMD = 4,\n};\n\nenum iommu_hw_queue_type {\n\tIOMMU_HW_QUEUE_TYPE_DEFAULT = 0,\n\tIOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,\n};\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nenum iommu_viommu_type {\n\tIOMMU_VIOMMU_TYPE_DEFAULT = 0,\n\tIOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,\n\tIOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,\n};\n\nenum iommufd_hwpt_alloc_flags {\n\tIOMMU_HWPT_ALLOC_NEST_PARENT = 1,\n\tIOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2,\n\tIOMMU_HWPT_FAULT_ID_VALID = 4,\n\tIOMMU_HWPT_ALLOC_PASID = 8,\n};\n\nenum iommufd_object_type {\n\tIOMMUFD_OBJ_NONE = 0,\n\tIOMMUFD_OBJ_ANY = 0,\n\tIOMMUFD_OBJ_DEVICE = 1,\n\tIOMMUFD_OBJ_HWPT_PAGING = 2,\n\tIOMMUFD_OBJ_HWPT_NESTED = 3,\n\tIOMMUFD_OBJ_IOAS = 4,\n\tIOMMUFD_OBJ_ACCESS = 5,\n\tIOMMUFD_OBJ_FAULT = 6,\n\tIOMMUFD_OBJ_VIOMMU = 7,\n\tIOMMUFD_OBJ_VDEVICE = 8,\n\tIOMMUFD_OBJ_VEVENTQ = 9,\n\tIOMMUFD_OBJ_HW_QUEUE = 10,\n\tIOMMUFD_OBJ_MAX = 11,\n};\n\nenum ip101gr_sel_intr32 {\n\tIP101GR_SEL_INTR32_KEEP = 0,\n\tIP101GR_SEL_INTR32_INTR = 1,\n\tIP101GR_SEL_INTR32_RXER = 2,\n};\n\nenum ip6_defrag_users {\n\tIP6_DEFRAG_LOCAL_DELIVER = 0,\n\tIP6_DEFRAG_CONNTRACK_IN = 1,\n\t__IP6_DEFRAG_CONNTRACK_IN = 65536,\n\tIP6_DEFRAG_CONNTRACK_OUT = 65537,\n\t__IP6_DEFRAG_CONNTRACK_OUT = 131072,\n\tIP6_DEFRAG_CONNTRACK_BRIDGE_IN = 131073,\n\t__IP6_DEFRAG_CONNTRACK_BRIDGE_IN = 196608,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum ipi_msg_type {\n\tIPI_WAKEUP = 0,\n\tIPI_TIMER = 1,\n\tIPI_RESCHEDULE = 2,\n\tIPI_CALL_FUNC = 3,\n\tIPI_CPU_STOP = 4,\n\tIPI_IRQ_WORK = 5,\n\tIPI_COMPLETION = 6,\n\tNR_IPI = 7,\n\tIPI_CPU_BACKTRACE = 7,\n\tMAX_IPI = 8,\n};\n\nenum ipq8064_functions {\n\tIPQ_MUX_gpio = 0,\n\tIPQ_MUX_mdio = 1,\n\tIPQ_MUX_mi2s = 2,\n\tIPQ_MUX_pdm = 3,\n\tIPQ_MUX_ssbi = 4,\n\tIPQ_MUX_spmi = 5,\n\tIPQ_MUX_audio_pcm = 6,\n\tIPQ_MUX_gsbi1 = 7,\n\tIPQ_MUX_gsbi2 = 8,\n\tIPQ_MUX_gsbi4 = 9,\n\tIPQ_MUX_gsbi5 = 10,\n\tIPQ_MUX_gsbi5_spi_cs1 = 11,\n\tIPQ_MUX_gsbi5_spi_cs2 = 12,\n\tIPQ_MUX_gsbi5_spi_cs3 = 13,\n\tIPQ_MUX_gsbi6 = 14,\n\tIPQ_MUX_gsbi7 = 15,\n\tIPQ_MUX_nss_spi = 16,\n\tIPQ_MUX_sdc1 = 17,\n\tIPQ_MUX_spdif = 18,\n\tIPQ_MUX_nand = 19,\n\tIPQ_MUX_tsif1 = 20,\n\tIPQ_MUX_tsif2 = 21,\n\tIPQ_MUX_usb_fs_n = 22,\n\tIPQ_MUX_usb_fs = 23,\n\tIPQ_MUX_usb2_hsic = 24,\n\tIPQ_MUX_rgmii2 = 25,\n\tIPQ_MUX_sata = 26,\n\tIPQ_MUX_pcie1_rst = 27,\n\tIPQ_MUX_pcie1_prsnt = 28,\n\tIPQ_MUX_pcie1_pwrflt = 29,\n\tIPQ_MUX_pcie1_pwren_n = 30,\n\tIPQ_MUX_pcie1_pwren = 31,\n\tIPQ_MUX_pcie1_clk_req = 32,\n\tIPQ_MUX_pcie2_rst = 33,\n\tIPQ_MUX_pcie2_prsnt = 34,\n\tIPQ_MUX_pcie2_pwrflt = 35,\n\tIPQ_MUX_pcie2_pwren_n = 36,\n\tIPQ_MUX_pcie2_pwren = 37,\n\tIPQ_MUX_pcie2_clk_req = 38,\n\tIPQ_MUX_pcie3_rst = 39,\n\tIPQ_MUX_pcie3_prsnt = 40,\n\tIPQ_MUX_pcie3_pwrflt = 41,\n\tIPQ_MUX_pcie3_pwren_n = 42,\n\tIPQ_MUX_pcie3_pwren = 43,\n\tIPQ_MUX_pcie3_clk_req = 44,\n\tIPQ_MUX_ps_hold = 45,\n\tIPQ_MUX_NA = 46,\n};\n\nenum ipq806x_versions {\n\tIPQ8062_VERSION = 0,\n\tIPQ8064_VERSION = 1,\n\tIPQ8065_VERSION = 2,\n};\n\nenum ipq8074_versions {\n\tIPQ8074_HAWKEYE_VERSION = 0,\n\tIPQ8074_ACORN_VERSION = 1,\n};\n\nenum iproc_arm_pll_fid {\n\tARM_PLL_FID_CRYSTAL_CLK = 0,\n\tARM_PLL_FID_SYS_CLK = 2,\n\tARM_PLL_FID_CH0_SLOW_CLK = 6,\n\tARM_PLL_FID_CH1_FAST_CLK = 7,\n};\n\nenum iproc_msi_reg {\n\tIPROC_MSI_EQ_PAGE = 0,\n\tIPROC_MSI_EQ_PAGE_UPPER = 1,\n\tIPROC_MSI_PAGE = 2,\n\tIPROC_MSI_PAGE_UPPER = 3,\n\tIPROC_MSI_CTRL = 4,\n\tIPROC_MSI_EQ_HEAD = 5,\n\tIPROC_MSI_EQ_TAIL = 6,\n\tIPROC_MSI_INTS_EN = 7,\n\tIPROC_MSI_REG_SIZE = 8,\n};\n\nenum iproc_pcie_ib_map_type {\n\tIPROC_PCIE_IB_MAP_MEM = 0,\n\tIPROC_PCIE_IB_MAP_IO = 1,\n\tIPROC_PCIE_IB_MAP_INVALID = 2,\n};\n\nenum iproc_pcie_reg {\n\tIPROC_PCIE_CLK_CTRL = 0,\n\tIPROC_PCIE_MSI_GIC_MODE = 1,\n\tIPROC_PCIE_MSI_BASE_ADDR = 2,\n\tIPROC_PCIE_MSI_WINDOW_SIZE = 3,\n\tIPROC_PCIE_MSI_ADDR_LO = 4,\n\tIPROC_PCIE_MSI_ADDR_HI = 5,\n\tIPROC_PCIE_MSI_EN_CFG = 6,\n\tIPROC_PCIE_CFG_IND_ADDR = 7,\n\tIPROC_PCIE_CFG_IND_DATA = 8,\n\tIPROC_PCIE_CFG_ADDR = 9,\n\tIPROC_PCIE_CFG_DATA = 10,\n\tIPROC_PCIE_INTX_EN = 11,\n\tIPROC_PCIE_OARR0 = 12,\n\tIPROC_PCIE_OMAP0 = 13,\n\tIPROC_PCIE_OARR1 = 14,\n\tIPROC_PCIE_OMAP1 = 15,\n\tIPROC_PCIE_OARR2 = 16,\n\tIPROC_PCIE_OMAP2 = 17,\n\tIPROC_PCIE_OARR3 = 18,\n\tIPROC_PCIE_OMAP3 = 19,\n\tIPROC_PCIE_IARR0 = 20,\n\tIPROC_PCIE_IMAP0 = 21,\n\tIPROC_PCIE_IARR1 = 22,\n\tIPROC_PCIE_IMAP1 = 23,\n\tIPROC_PCIE_IARR2 = 24,\n\tIPROC_PCIE_IMAP2 = 25,\n\tIPROC_PCIE_IARR3 = 26,\n\tIPROC_PCIE_IMAP3 = 27,\n\tIPROC_PCIE_IARR4 = 28,\n\tIPROC_PCIE_IMAP4 = 29,\n\tIPROC_PCIE_CFG_RD_STATUS = 30,\n\tIPROC_PCIE_LINK_STATUS = 31,\n\tIPROC_PCIE_APB_ERR_EN = 32,\n\tIPROC_PCIE_MAX_NUM_REG = 33,\n};\n\nenum iproc_pcie_type {\n\tIPROC_PCIE_PAXB_BCMA = 0,\n\tIPROC_PCIE_PAXB = 1,\n\tIPROC_PCIE_PAXB_V2 = 2,\n\tIPROC_PCIE_PAXC = 3,\n\tIPROC_PCIE_PAXC_V2 = 4,\n};\n\nenum iproc_pinconf_ctrl_type {\n\tIOCTRL_TYPE_AON = 1,\n\tIOCTRL_TYPE_CDRU = 2,\n\tIOCTRL_TYPE_INVALID = 3,\n};\n\nenum iproc_pinconf_param {\n\tIPROC_PINCONF_DRIVE_STRENGTH = 0,\n\tIPROC_PINCONF_BIAS_DISABLE = 1,\n\tIPROC_PINCONF_BIAS_PULL_UP = 2,\n\tIPROC_PINCONF_BIAS_PULL_DOWN = 3,\n\tIPROC_PINCON_MAX = 4,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irq_source {\n\tSINGLE_L2 = 0,\n\tMUXED_L1 = 1,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum isl29018_int_time {\n\tISL29018_INT_TIME_16 = 0,\n\tISL29018_INT_TIME_12 = 1,\n\tISL29018_INT_TIME_8 = 2,\n\tISL29018_INT_TIME_4 = 3,\n};\n\nenum isl29028_als_ir_mode {\n\tISL29028_MODE_NONE = 0,\n\tISL29028_MODE_ALS = 1,\n\tISL29028_MODE_IR = 2,\n};\n\nenum isp1760_ctrl_state {\n\tISP1760_CTRL_SETUP = 0,\n\tISP1760_CTRL_DATA_IN = 1,\n\tISP1760_CTRL_DATA_OUT = 2,\n\tISP1760_CTRL_STATUS = 3,\n};\n\nenum isp1760_queue_head_types {\n\tQH_CONTROL = 0,\n\tQH_BULK = 1,\n\tQH_INTERRUPT = 2,\n\tQH_END = 3,\n};\n\nenum isp176x_device_controller_fields {\n\tDC_DEVEN = 0,\n\tDC_DEVADDR = 1,\n\tDC_VBUSSTAT = 2,\n\tDC_SFRESET = 3,\n\tDC_GLINTENA = 4,\n\tDC_CDBGMOD_ACK = 5,\n\tDC_DDBGMODIN_ACK = 6,\n\tDC_DDBGMODOUT_ACK = 7,\n\tDC_INTPOL = 8,\n\tDC_IEPRXTX_7 = 9,\n\tDC_IEPRXTX_6 = 10,\n\tDC_IEPRXTX_5 = 11,\n\tDC_IEPRXTX_4 = 12,\n\tDC_IEPRXTX_3 = 13,\n\tDC_IEPRXTX_2 = 14,\n\tDC_IEPRXTX_1 = 15,\n\tDC_IEPRXTX_0 = 16,\n\tDC_IEP0SETUP = 17,\n\tDC_IEVBUS = 18,\n\tDC_IEHS_STA = 19,\n\tDC_IERESM = 20,\n\tDC_IESUSP = 21,\n\tDC_IEBRST = 22,\n\tDC_EP0SETUP = 23,\n\tDC_ENDPIDX = 24,\n\tDC_EPDIR = 25,\n\tDC_CLBUF = 26,\n\tDC_VENDP = 27,\n\tDC_DSEN = 28,\n\tDC_STATUS = 29,\n\tDC_STALL = 30,\n\tDC_BUFLEN = 31,\n\tDC_FFOSZ = 32,\n\tDC_EPENABLE = 33,\n\tDC_ENDPTYP = 34,\n\tDC_FRAMENUM = 35,\n\tDC_UFRAMENUM = 36,\n\tDC_CHIP_ID_HIGH = 37,\n\tDC_CHIP_ID_LOW = 38,\n\tDC_SCRATCH = 39,\n\tDC_FIELD_MAX = 40,\n};\n\nenum isp176x_host_controller_fields {\n\tPORT_OWNER = 0,\n\tPORT_POWER = 1,\n\tPORT_LSTATUS = 2,\n\tPORT_RESET = 3,\n\tPORT_SUSPEND = 4,\n\tPORT_RESUME = 5,\n\tPORT_PE = 6,\n\tPORT_CSC = 7,\n\tPORT_CONNECT = 8,\n\tHCS_PPC = 9,\n\tHCS_N_PORTS = 10,\n\tHCC_ISOC_CACHE = 11,\n\tHCC_ISOC_THRES = 12,\n\tCMD_LRESET = 13,\n\tCMD_RESET = 14,\n\tCMD_RUN = 15,\n\tSTS_PCD = 16,\n\tHC_FRINDEX = 17,\n\tFLAG_CF = 18,\n\tHC_ISO_PTD_DONEMAP = 19,\n\tHC_ISO_PTD_SKIPMAP = 20,\n\tHC_ISO_PTD_LASTPTD = 21,\n\tHC_INT_PTD_DONEMAP = 22,\n\tHC_INT_PTD_SKIPMAP = 23,\n\tHC_INT_PTD_LASTPTD = 24,\n\tHC_ATL_PTD_DONEMAP = 25,\n\tHC_ATL_PTD_SKIPMAP = 26,\n\tHC_ATL_PTD_LASTPTD = 27,\n\tALL_ATX_RESET = 28,\n\tHW_ANA_DIGI_OC = 29,\n\tHW_DEV_DMA = 30,\n\tHW_COMN_IRQ = 31,\n\tHW_COMN_DMA = 32,\n\tHW_DATA_BUS_WIDTH = 33,\n\tHW_DACK_POL_HIGH = 34,\n\tHW_DREQ_POL_HIGH = 35,\n\tHW_INTR_HIGH_ACT = 36,\n\tHW_INTF_LOCK = 37,\n\tHW_INTR_EDGE_TRIG = 38,\n\tHW_GLOBAL_INTR_EN = 39,\n\tHC_CHIP_ID_HIGH = 40,\n\tHC_CHIP_ID_LOW = 41,\n\tHC_CHIP_REV = 42,\n\tHC_SCRATCH = 43,\n\tSW_RESET_RESET_ATX = 44,\n\tSW_RESET_RESET_HC = 45,\n\tSW_RESET_RESET_ALL = 46,\n\tISO_BUF_FILL = 47,\n\tINT_BUF_FILL = 48,\n\tATL_BUF_FILL = 49,\n\tMEM_BANK_SEL = 50,\n\tMEM_START_ADDR = 51,\n\tHC_DATA = 52,\n\tHC_INTERRUPT = 53,\n\tHC_INT_IRQ_ENABLE = 54,\n\tHC_ATL_IRQ_ENABLE = 55,\n\tHC_ISO_IRQ_MASK_OR = 56,\n\tHC_INT_IRQ_MASK_OR = 57,\n\tHC_ATL_IRQ_MASK_OR = 58,\n\tHC_ISO_IRQ_MASK_AND = 59,\n\tHC_INT_IRQ_MASK_AND = 60,\n\tHC_ATL_IRQ_MASK_AND = 61,\n\tHW_OTG_DISABLE = 62,\n\tHW_SW_SEL_HC_DC = 63,\n\tHW_VBUS_DRV = 64,\n\tHW_SEL_CP_EXT = 65,\n\tHW_DM_PULLDOWN = 66,\n\tHW_DP_PULLDOWN = 67,\n\tHW_DP_PULLUP = 68,\n\tHW_HC_2_DIS = 69,\n\tHW_OTG_DISABLE_CLEAR = 70,\n\tHW_SW_SEL_HC_DC_CLEAR = 71,\n\tHW_VBUS_DRV_CLEAR = 72,\n\tHW_SEL_CP_EXT_CLEAR = 73,\n\tHW_DM_PULLDOWN_CLEAR = 74,\n\tHW_DP_PULLDOWN_CLEAR = 75,\n\tHW_DP_PULLUP_CLEAR = 76,\n\tHW_HC_2_DIS_CLEAR = 77,\n\tHC_FIELD_MAX = 78,\n};\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum its_vcpu_info_cmd_type {\n\tMAP_VLPI = 0,\n\tGET_VLPI = 1,\n\tPROP_UPDATE_VLPI = 2,\n\tPROP_UPDATE_AND_INV_VLPI = 3,\n\tSCHEDULE_VPE = 4,\n\tDESCHEDULE_VPE = 5,\n\tCOMMIT_VPE = 6,\n\tINVALL_VPE = 7,\n\tPROP_UPDATE_VSGI = 8,\n};\n\nenum jbd2_shrink_type {\n\tJBD2_SHRINK_DESTROY = 0,\n\tJBD2_SHRINK_BUSY_STOP = 1,\n\tJBD2_SHRINK_BUSY_SKIP = 2,\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 17,\n\tBH_JWrite = 18,\n\tBH_Freed = 19,\n\tBH_Revoked = 20,\n\tBH_RevokeValid = 21,\n\tBH_JBDDirty = 22,\n\tBH_JournalHead = 23,\n\tBH_Shadow = 24,\n\tBH_Verified = 25,\n\tBH_JBDPrivateStart = 26,\n};\n\nenum kbd_subcmds {\n\tCNFG_WAKE = 3,\n\tCNFG_WAKE_KEY_REPORTING = 4,\n\tSET_LEDS = 237,\n\tENABLE_KBD = 244,\n\tDISABLE_KBD = 245,\n};\n\nenum kcmp_type {\n\tKCMP_FILE = 0,\n\tKCMP_VM = 1,\n\tKCMP_FILES = 2,\n\tKCMP_FS = 3,\n\tKCMP_SIGHAND = 4,\n\tKCMP_IO = 5,\n\tKCMP_SYSVSEM = 6,\n\tKCMP_EPOLL_TFD = 7,\n\tKCMP_TYPES = 8,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_being_used_for {\n\tVERIFYING_MODULE_SIGNATURE = 0,\n\tVERIFYING_FIRMWARE_SIGNATURE = 1,\n\tVERIFYING_KEXEC_PE_SIGNATURE = 2,\n\tVERIFYING_KEY_SIGNATURE = 3,\n\tVERIFYING_KEY_SELF_SIGNATURE = 4,\n\tVERIFYING_UNSPECIFIED_SIGNATURE = 5,\n\tVERIFYING_BPF_SIGNATURE = 6,\n\tNR__KEY_BEING_USED_FOR = 7,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_CGROUP = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_DMA = 2,\n\tNR_KMALLOC_TYPES = 3,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum knav_acc_result {\n\tACC_RET_IDLE = 0,\n\tACC_RET_SUCCESS = 1,\n\tACC_RET_INVALID_COMMAND = 2,\n\tACC_RET_INVALID_CHANNEL = 3,\n\tACC_RET_INACTIVE_CHANNEL = 4,\n\tACC_RET_ACTIVE_CHANNEL = 5,\n\tACC_RET_INVALID_QUEUE = 6,\n\tACC_RET_INVALID_RET = 7,\n};\n\nenum knav_dma_desc_type {\n\tDMA_DESC_HOST = 0,\n\tDMA_DESC_MONOLITHIC = 2,\n};\n\nenum knav_dma_rx_err_mode {\n\tDMA_DROP = 0,\n\tDMA_RETRY = 1,\n};\n\nenum knav_dma_rx_thresholds {\n\tDMA_THRESH_NONE = 0,\n\tDMA_THRESH_0 = 1,\n\tDMA_THRESH_0_1 = 3,\n\tDMA_THRESH_0_1_2 = 7,\n};\n\nenum knav_dma_tx_priority {\n\tDMA_PRIO_HIGH___2 = 0,\n\tDMA_PRIO_MED_H = 1,\n\tDMA_PRIO_MED_L = 2,\n\tDMA_PRIO_LOW___2 = 3,\n};\n\nenum knav_queue_ctrl_cmd {\n\tKNAV_QUEUE_GET_ID = 0,\n\tKNAV_QUEUE_FLUSH = 1,\n\tKNAV_QUEUE_SET_NOTIFIER = 2,\n\tKNAV_QUEUE_ENABLE_NOTIFY = 3,\n\tKNAV_QUEUE_DISABLE_NOTIFY = 4,\n\tKNAV_QUEUE_GET_COUNT = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kp_band {\n\tKP_BAND_MID = 0,\n\tKP_BAND_HIGH = 1,\n\tKP_BAND_HIGH_HIGH = 2,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum latency_range {\n\tlowest_latency = 0,\n\tlow_latency = 1,\n\tbulk_latency = 2,\n\tlatency_invalid = 255,\n};\n\nenum layoutdriver_policy_flags {\n\tPNFS_LAYOUTRET_ON_SETATTR = 1,\n\tPNFS_LAYOUTRET_ON_ERROR = 2,\n\tPNFS_READ_WHOLE_PAGE = 4,\n\tPNFS_LAYOUTGET_ON_OPEN = 8,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum led_default_state {\n\tLEDS_DEFSTATE_OFF = 0,\n\tLEDS_DEFSTATE_ON = 1,\n\tLEDS_DEFSTATE_KEEP = 2,\n};\n\nenum led_trigger_netdev_modes {\n\tTRIGGER_NETDEV_LINK = 0,\n\tTRIGGER_NETDEV_LINK_10 = 1,\n\tTRIGGER_NETDEV_LINK_100 = 2,\n\tTRIGGER_NETDEV_LINK_1000 = 3,\n\tTRIGGER_NETDEV_LINK_2500 = 4,\n\tTRIGGER_NETDEV_LINK_5000 = 5,\n\tTRIGGER_NETDEV_LINK_10000 = 6,\n\tTRIGGER_NETDEV_HALF_DUPLEX = 7,\n\tTRIGGER_NETDEV_FULL_DUPLEX = 8,\n\tTRIGGER_NETDEV_TX = 9,\n\tTRIGGER_NETDEV_RX = 10,\n\tTRIGGER_NETDEV_TX_ERR = 11,\n\tTRIGGER_NETDEV_RX_ERR = 12,\n\t__TRIGGER_NETDEV_MAX = 13,\n};\n\nenum limit_by4 {\n\tNFS4_LIMIT_SIZE = 1,\n\tNFS4_LIMIT_BLOCKS = 2,\n};\n\nenum link_inband_signalling {\n\tLINK_INBAND_DISABLE = 1,\n\tLINK_INBAND_ENABLE = 2,\n\tLINK_INBAND_BYPASS = 4,\n};\n\nenum lm90_temp_reg_index {\n\tLOCAL_LOW = 0,\n\tLOCAL_HIGH = 1,\n\tLOCAL_CRIT = 2,\n\tREMOTE_CRIT = 3,\n\tLOCAL_EMERG = 4,\n\tREMOTE_EMERG = 5,\n\tREMOTE2_CRIT = 6,\n\tREMOTE2_EMERG = 7,\n\tREMOTE_TEMP = 8,\n\tREMOTE_LOW = 9,\n\tREMOTE_HIGH = 10,\n\tREMOTE_OFFSET = 11,\n\tLOCAL_TEMP = 12,\n\tREMOTE2_TEMP = 13,\n\tREMOTE2_LOW = 14,\n\tREMOTE2_HIGH = 15,\n\tREMOTE2_OFFSET = 16,\n\tTEMP_REG_NUM = 17,\n};\n\nenum lock_type4 {\n\tNFS4_UNLOCK_LT = 0,\n\tNFS4_READ_LT = 1,\n\tNFS4_WRITE_LT = 2,\n\tNFS4_READW_LT = 3,\n\tNFS4_WRITEW_LT = 4,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum lp872x_dvs_sel {\n\tSEL_V1 = 0,\n\tSEL_V2 = 1,\n};\n\nenum lp872x_id {\n\tLP8720 = 0,\n\tLP8725 = 1,\n};\n\nenum lp872x_regulator_id {\n\tLP8720_ID_BASE = 0,\n\tLP8720_ID_LDO1 = 0,\n\tLP8720_ID_LDO2 = 1,\n\tLP8720_ID_LDO3 = 2,\n\tLP8720_ID_LDO4 = 3,\n\tLP8720_ID_LDO5 = 4,\n\tLP8720_ID_BUCK = 5,\n\tLP8725_ID_BASE = 6,\n\tLP8725_ID_LDO1 = 6,\n\tLP8725_ID_LDO2 = 7,\n\tLP8725_ID_LDO3 = 8,\n\tLP8725_ID_LDO4 = 9,\n\tLP8725_ID_LDO5 = 10,\n\tLP8725_ID_LILO1 = 11,\n\tLP8725_ID_LILO2 = 12,\n\tLP8725_ID_BUCK1 = 13,\n\tLP8725_ID_BUCK2 = 14,\n\tLP872X_ID_MAX = 15,\n};\n\nenum lpuart_type {\n\tVF610_LPUART = 0,\n\tLS1021A_LPUART = 1,\n\tLS1028A_LPUART = 2,\n\tIMX7ULP_LPUART = 3,\n\tIMX8ULP_LPUART = 4,\n\tIMX8QXP_LPUART = 5,\n\tIMXRT1050_LPUART = 6,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum mac_version {\n\tRTL_GIGA_MAC_VER_02 = 0,\n\tRTL_GIGA_MAC_VER_03 = 1,\n\tRTL_GIGA_MAC_VER_04 = 2,\n\tRTL_GIGA_MAC_VER_05 = 3,\n\tRTL_GIGA_MAC_VER_06 = 4,\n\tRTL_GIGA_MAC_VER_07 = 5,\n\tRTL_GIGA_MAC_VER_08 = 6,\n\tRTL_GIGA_MAC_VER_09 = 7,\n\tRTL_GIGA_MAC_VER_10 = 8,\n\tRTL_GIGA_MAC_VER_14 = 9,\n\tRTL_GIGA_MAC_VER_17 = 10,\n\tRTL_GIGA_MAC_VER_18 = 11,\n\tRTL_GIGA_MAC_VER_19 = 12,\n\tRTL_GIGA_MAC_VER_20 = 13,\n\tRTL_GIGA_MAC_VER_21 = 14,\n\tRTL_GIGA_MAC_VER_22 = 15,\n\tRTL_GIGA_MAC_VER_23 = 16,\n\tRTL_GIGA_MAC_VER_24 = 17,\n\tRTL_GIGA_MAC_VER_25 = 18,\n\tRTL_GIGA_MAC_VER_26 = 19,\n\tRTL_GIGA_MAC_VER_28 = 20,\n\tRTL_GIGA_MAC_VER_29 = 21,\n\tRTL_GIGA_MAC_VER_30 = 22,\n\tRTL_GIGA_MAC_VER_31 = 23,\n\tRTL_GIGA_MAC_VER_32 = 24,\n\tRTL_GIGA_MAC_VER_33 = 25,\n\tRTL_GIGA_MAC_VER_34 = 26,\n\tRTL_GIGA_MAC_VER_35 = 27,\n\tRTL_GIGA_MAC_VER_36 = 28,\n\tRTL_GIGA_MAC_VER_37 = 29,\n\tRTL_GIGA_MAC_VER_38 = 30,\n\tRTL_GIGA_MAC_VER_39 = 31,\n\tRTL_GIGA_MAC_VER_40 = 32,\n\tRTL_GIGA_MAC_VER_42 = 33,\n\tRTL_GIGA_MAC_VER_43 = 34,\n\tRTL_GIGA_MAC_VER_44 = 35,\n\tRTL_GIGA_MAC_VER_46 = 36,\n\tRTL_GIGA_MAC_VER_48 = 37,\n\tRTL_GIGA_MAC_VER_51 = 38,\n\tRTL_GIGA_MAC_VER_52 = 39,\n\tRTL_GIGA_MAC_VER_61 = 40,\n\tRTL_GIGA_MAC_VER_63 = 41,\n\tRTL_GIGA_MAC_VER_64 = 42,\n\tRTL_GIGA_MAC_VER_66 = 43,\n\tRTL_GIGA_MAC_VER_70 = 44,\n\tRTL_GIGA_MAC_VER_80 = 45,\n\tRTL_GIGA_MAC_NONE = 46,\n\tRTL_GIGA_MAC_VER_LAST = 45,\n\tRTL_GIGA_MAC_VER_EXTENDED = 46,\n};\n\nenum macb_bd_control {\n\tTSTAMP_DISABLED = 0,\n\tTSTAMP_FRAME_PTP_EVENT_ONLY = 1,\n\tTSTAMP_ALL_PTP_FRAMES = 2,\n\tTSTAMP_ALL_FRAMES = 3,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum max14577_reg {\n\tMAX14577_REG_DEVICEID = 0,\n\tMAX14577_REG_INT1 = 1,\n\tMAX14577_REG_INT2 = 2,\n\tMAX14577_REG_INT3 = 3,\n\tMAX14577_REG_STATUS1 = 4,\n\tMAX14577_REG_STATUS2 = 5,\n\tMAX14577_REG_STATUS3 = 6,\n\tMAX14577_REG_INTMASK1 = 7,\n\tMAX14577_REG_INTMASK2 = 8,\n\tMAX14577_REG_INTMASK3 = 9,\n\tMAX14577_REG_CDETCTRL1 = 10,\n\tMAX14577_REG_RFU = 11,\n\tMAX14577_REG_CONTROL1 = 12,\n\tMAX14577_REG_CONTROL2 = 13,\n\tMAX14577_REG_CONTROL3 = 14,\n\tMAX14577_REG_CHGCTRL1 = 15,\n\tMAX14577_REG_CHGCTRL2 = 16,\n\tMAX14577_REG_CHGCTRL3 = 17,\n\tMAX14577_REG_CHGCTRL4 = 18,\n\tMAX14577_REG_CHGCTRL5 = 19,\n\tMAX14577_REG_CHGCTRL6 = 20,\n\tMAX14577_REG_CHGCTRL7 = 21,\n\tMAX14577_REG_END = 22,\n};\n\nenum max77686_chip_name {\n\tCHIP_MAX77686 = 0,\n\tCHIP_MAX77802 = 1,\n\tCHIP_MAX77620 = 2,\n};\n\nenum max77686_irq {\n\tMAX77686_PMICIRQ_PWRONF = 0,\n\tMAX77686_PMICIRQ_PWRONR = 1,\n\tMAX77686_PMICIRQ_JIGONBF = 2,\n\tMAX77686_PMICIRQ_JIGONBR = 3,\n\tMAX77686_PMICIRQ_ACOKBF = 4,\n\tMAX77686_PMICIRQ_ACOKBR = 5,\n\tMAX77686_PMICIRQ_ONKEY1S = 6,\n\tMAX77686_PMICIRQ_MRSTB = 7,\n\tMAX77686_PMICIRQ_140C = 8,\n\tMAX77686_PMICIRQ_120C = 9,\n\tMAX77686_RTCIRQ_RTC60S = 0,\n\tMAX77686_RTCIRQ_RTCA1 = 1,\n\tMAX77686_RTCIRQ_RTCA2 = 2,\n\tMAX77686_RTCIRQ_SMPL = 3,\n\tMAX77686_RTCIRQ_RTC1S = 4,\n\tMAX77686_RTCIRQ_WTSR = 5,\n};\n\nenum max77686_irq_source {\n\tPMIC_INT1 = 0,\n\tPMIC_INT2 = 1,\n\tRTC_INT = 2,\n\tMAX77686_IRQ_GROUP_NR = 3,\n};\n\nenum max77686_pmic_reg {\n\tMAX77686_REG_DEVICE_ID = 0,\n\tMAX77686_REG_INTSRC = 1,\n\tMAX77686_REG_INT1 = 2,\n\tMAX77686_REG_INT2 = 3,\n\tMAX77686_REG_INT1MSK = 4,\n\tMAX77686_REG_INT2MSK = 5,\n\tMAX77686_REG_STATUS1 = 6,\n\tMAX77686_REG_STATUS2 = 7,\n\tMAX77686_REG_PWRON = 8,\n\tMAX77686_REG_ONOFF_DELAY = 9,\n\tMAX77686_REG_MRSTB = 10,\n\tMAX77686_REG_BUCK1CTRL = 16,\n\tMAX77686_REG_BUCK1OUT = 17,\n\tMAX77686_REG_BUCK2CTRL1 = 18,\n\tMAX77686_REG_BUCK234FREQ = 19,\n\tMAX77686_REG_BUCK2DVS1 = 20,\n\tMAX77686_REG_BUCK2DVS2 = 21,\n\tMAX77686_REG_BUCK2DVS3 = 22,\n\tMAX77686_REG_BUCK2DVS4 = 23,\n\tMAX77686_REG_BUCK2DVS5 = 24,\n\tMAX77686_REG_BUCK2DVS6 = 25,\n\tMAX77686_REG_BUCK2DVS7 = 26,\n\tMAX77686_REG_BUCK2DVS8 = 27,\n\tMAX77686_REG_BUCK3CTRL1 = 28,\n\tMAX77686_REG_BUCK3DVS1 = 30,\n\tMAX77686_REG_BUCK3DVS2 = 31,\n\tMAX77686_REG_BUCK3DVS3 = 32,\n\tMAX77686_REG_BUCK3DVS4 = 33,\n\tMAX77686_REG_BUCK3DVS5 = 34,\n\tMAX77686_REG_BUCK3DVS6 = 35,\n\tMAX77686_REG_BUCK3DVS7 = 36,\n\tMAX77686_REG_BUCK3DVS8 = 37,\n\tMAX77686_REG_BUCK4CTRL1 = 38,\n\tMAX77686_REG_BUCK4DVS1 = 40,\n\tMAX77686_REG_BUCK4DVS2 = 41,\n\tMAX77686_REG_BUCK4DVS3 = 42,\n\tMAX77686_REG_BUCK4DVS4 = 43,\n\tMAX77686_REG_BUCK4DVS5 = 44,\n\tMAX77686_REG_BUCK4DVS6 = 45,\n\tMAX77686_REG_BUCK4DVS7 = 46,\n\tMAX77686_REG_BUCK4DVS8 = 47,\n\tMAX77686_REG_BUCK5CTRL = 48,\n\tMAX77686_REG_BUCK5OUT = 49,\n\tMAX77686_REG_BUCK6CTRL = 50,\n\tMAX77686_REG_BUCK6OUT = 51,\n\tMAX77686_REG_BUCK7CTRL = 52,\n\tMAX77686_REG_BUCK7OUT = 53,\n\tMAX77686_REG_BUCK8CTRL = 54,\n\tMAX77686_REG_BUCK8OUT = 55,\n\tMAX77686_REG_BUCK9CTRL = 56,\n\tMAX77686_REG_BUCK9OUT = 57,\n\tMAX77686_REG_LDO1CTRL1 = 64,\n\tMAX77686_REG_LDO2CTRL1 = 65,\n\tMAX77686_REG_LDO3CTRL1 = 66,\n\tMAX77686_REG_LDO4CTRL1 = 67,\n\tMAX77686_REG_LDO5CTRL1 = 68,\n\tMAX77686_REG_LDO6CTRL1 = 69,\n\tMAX77686_REG_LDO7CTRL1 = 70,\n\tMAX77686_REG_LDO8CTRL1 = 71,\n\tMAX77686_REG_LDO9CTRL1 = 72,\n\tMAX77686_REG_LDO10CTRL1 = 73,\n\tMAX77686_REG_LDO11CTRL1 = 74,\n\tMAX77686_REG_LDO12CTRL1 = 75,\n\tMAX77686_REG_LDO13CTRL1 = 76,\n\tMAX77686_REG_LDO14CTRL1 = 77,\n\tMAX77686_REG_LDO15CTRL1 = 78,\n\tMAX77686_REG_LDO16CTRL1 = 79,\n\tMAX77686_REG_LDO17CTRL1 = 80,\n\tMAX77686_REG_LDO18CTRL1 = 81,\n\tMAX77686_REG_LDO19CTRL1 = 82,\n\tMAX77686_REG_LDO20CTRL1 = 83,\n\tMAX77686_REG_LDO21CTRL1 = 84,\n\tMAX77686_REG_LDO22CTRL1 = 85,\n\tMAX77686_REG_LDO23CTRL1 = 86,\n\tMAX77686_REG_LDO24CTRL1 = 87,\n\tMAX77686_REG_LDO25CTRL1 = 88,\n\tMAX77686_REG_LDO26CTRL1 = 89,\n\tMAX77686_REG_LDO1CTRL2 = 96,\n\tMAX77686_REG_LDO2CTRL2 = 97,\n\tMAX77686_REG_LDO3CTRL2 = 98,\n\tMAX77686_REG_LDO4CTRL2 = 99,\n\tMAX77686_REG_LDO5CTRL2 = 100,\n\tMAX77686_REG_LDO6CTRL2 = 101,\n\tMAX77686_REG_LDO7CTRL2 = 102,\n\tMAX77686_REG_LDO8CTRL2 = 103,\n\tMAX77686_REG_LDO9CTRL2 = 104,\n\tMAX77686_REG_LDO10CTRL2 = 105,\n\tMAX77686_REG_LDO11CTRL2 = 106,\n\tMAX77686_REG_LDO12CTRL2 = 107,\n\tMAX77686_REG_LDO13CTRL2 = 108,\n\tMAX77686_REG_LDO14CTRL2 = 109,\n\tMAX77686_REG_LDO15CTRL2 = 110,\n\tMAX77686_REG_LDO16CTRL2 = 111,\n\tMAX77686_REG_LDO17CTRL2 = 112,\n\tMAX77686_REG_LDO18CTRL2 = 113,\n\tMAX77686_REG_LDO19CTRL2 = 114,\n\tMAX77686_REG_LDO20CTRL2 = 115,\n\tMAX77686_REG_LDO21CTRL2 = 116,\n\tMAX77686_REG_LDO22CTRL2 = 117,\n\tMAX77686_REG_LDO23CTRL2 = 118,\n\tMAX77686_REG_LDO24CTRL2 = 119,\n\tMAX77686_REG_LDO25CTRL2 = 120,\n\tMAX77686_REG_LDO26CTRL2 = 121,\n\tMAX77686_REG_BBAT_CHG = 126,\n\tMAX77686_REG_32KHZ = 127,\n\tMAX77686_REG_PMIC_END = 128,\n};\n\nenum max77686_regulators {\n\tMAX77686_LDO1 = 0,\n\tMAX77686_LDO2 = 1,\n\tMAX77686_LDO3 = 2,\n\tMAX77686_LDO4 = 3,\n\tMAX77686_LDO5 = 4,\n\tMAX77686_LDO6 = 5,\n\tMAX77686_LDO7 = 6,\n\tMAX77686_LDO8 = 7,\n\tMAX77686_LDO9 = 8,\n\tMAX77686_LDO10 = 9,\n\tMAX77686_LDO11 = 10,\n\tMAX77686_LDO12 = 11,\n\tMAX77686_LDO13 = 12,\n\tMAX77686_LDO14 = 13,\n\tMAX77686_LDO15 = 14,\n\tMAX77686_LDO16 = 15,\n\tMAX77686_LDO17 = 16,\n\tMAX77686_LDO18 = 17,\n\tMAX77686_LDO19 = 18,\n\tMAX77686_LDO20 = 19,\n\tMAX77686_LDO21 = 20,\n\tMAX77686_LDO22 = 21,\n\tMAX77686_LDO23 = 22,\n\tMAX77686_LDO24 = 23,\n\tMAX77686_LDO25 = 24,\n\tMAX77686_LDO26 = 25,\n\tMAX77686_BUCK1 = 26,\n\tMAX77686_BUCK2 = 27,\n\tMAX77686_BUCK3 = 28,\n\tMAX77686_BUCK4 = 29,\n\tMAX77686_BUCK5 = 30,\n\tMAX77686_BUCK6 = 31,\n\tMAX77686_BUCK7 = 32,\n\tMAX77686_BUCK8 = 33,\n\tMAX77686_BUCK9 = 34,\n\tMAX77686_REG_MAX = 35,\n};\n\nenum max77686_rtc_reg {\n\tMAX77686_RTC_INT = 0,\n\tMAX77686_RTC_INTM = 1,\n\tMAX77686_RTC_CONTROLM = 2,\n\tMAX77686_RTC_CONTROL = 3,\n\tMAX77686_RTC_UPDATE0 = 4,\n\tMAX77686_WTSR_SMPL_CNTL = 6,\n\tMAX77686_RTC_SEC = 7,\n\tMAX77686_RTC_MIN = 8,\n\tMAX77686_RTC_HOUR = 9,\n\tMAX77686_RTC_WEEKDAY = 10,\n\tMAX77686_RTC_MONTH = 11,\n\tMAX77686_RTC_YEAR = 12,\n\tMAX77686_RTC_MONTHDAY = 13,\n\tMAX77686_ALARM1_SEC = 14,\n\tMAX77686_ALARM1_MIN = 15,\n\tMAX77686_ALARM1_HOUR = 16,\n\tMAX77686_ALARM1_WEEKDAY = 17,\n\tMAX77686_ALARM1_MONTH = 18,\n\tMAX77686_ALARM1_YEAR = 19,\n\tMAX77686_ALARM1_DATE = 20,\n\tMAX77686_ALARM2_SEC = 21,\n\tMAX77686_ALARM2_MIN = 22,\n\tMAX77686_ALARM2_HOUR = 23,\n\tMAX77686_ALARM2_WEEKDAY = 24,\n\tMAX77686_ALARM2_MONTH = 25,\n\tMAX77686_ALARM2_YEAR = 26,\n\tMAX77686_ALARM2_DATE = 27,\n};\n\nenum max77686_rtc_reg_offset {\n\tREG_RTC_CONTROLM = 0,\n\tREG_RTC_CONTROL = 1,\n\tREG_RTC_UPDATE0 = 2,\n\tREG_WTSR_SMPL_CNTL = 3,\n\tREG_RTC_SEC = 4,\n\tREG_RTC_MIN = 5,\n\tREG_RTC_HOUR = 6,\n\tREG_RTC_WEEKDAY = 7,\n\tREG_RTC_MONTH = 8,\n\tREG_RTC_YEAR = 9,\n\tREG_RTC_MONTHDAY = 10,\n\tREG_ALARM1_SEC = 11,\n\tREG_ALARM1_MIN = 12,\n\tREG_ALARM1_HOUR = 13,\n\tREG_ALARM1_WEEKDAY = 14,\n\tREG_ALARM1_MONTH = 15,\n\tREG_ALARM1_YEAR = 16,\n\tREG_ALARM1_DATE = 17,\n\tREG_ALARM2_SEC = 18,\n\tREG_ALARM2_MIN = 19,\n\tREG_ALARM2_HOUR = 20,\n\tREG_ALARM2_WEEKDAY = 21,\n\tREG_ALARM2_MONTH = 22,\n\tREG_ALARM2_YEAR = 23,\n\tREG_ALARM2_DATE = 24,\n\tREG_RTC_AE1 = 25,\n\tREG_RTC_END = 26,\n};\n\nenum max77686_types {\n\tTYPE_MAX77686 = 0,\n\tTYPE_MAX77802 = 1,\n};\n\nenum max77802_pmic_reg {\n\tMAX77802_REG_DEVICE_ID = 0,\n\tMAX77802_REG_INTSRC = 1,\n\tMAX77802_REG_INT1 = 2,\n\tMAX77802_REG_INT2 = 3,\n\tMAX77802_REG_INT1MSK = 4,\n\tMAX77802_REG_INT2MSK = 5,\n\tMAX77802_REG_STATUS1 = 6,\n\tMAX77802_REG_STATUS2 = 7,\n\tMAX77802_REG_PWRON = 8,\n\tMAX77802_REG_MRSTB = 10,\n\tMAX77802_REG_EPWRHOLD = 11,\n\tMAX77802_REG_BOOSTCTRL = 14,\n\tMAX77802_REG_BOOSTOUT = 15,\n\tMAX77802_REG_BUCK1CTRL = 16,\n\tMAX77802_REG_BUCK1DVS1 = 17,\n\tMAX77802_REG_BUCK1DVS2 = 18,\n\tMAX77802_REG_BUCK1DVS3 = 19,\n\tMAX77802_REG_BUCK1DVS4 = 20,\n\tMAX77802_REG_BUCK1DVS5 = 21,\n\tMAX77802_REG_BUCK1DVS6 = 22,\n\tMAX77802_REG_BUCK1DVS7 = 23,\n\tMAX77802_REG_BUCK1DVS8 = 24,\n\tMAX77802_REG_BUCK2CTRL1 = 26,\n\tMAX77802_REG_BUCK2CTRL2 = 27,\n\tMAX77802_REG_BUCK2PHTRAN = 28,\n\tMAX77802_REG_BUCK2DVS1 = 29,\n\tMAX77802_REG_BUCK2DVS2 = 30,\n\tMAX77802_REG_BUCK2DVS3 = 31,\n\tMAX77802_REG_BUCK2DVS4 = 32,\n\tMAX77802_REG_BUCK2DVS5 = 33,\n\tMAX77802_REG_BUCK2DVS6 = 34,\n\tMAX77802_REG_BUCK2DVS7 = 35,\n\tMAX77802_REG_BUCK2DVS8 = 36,\n\tMAX77802_REG_BUCK3CTRL1 = 39,\n\tMAX77802_REG_BUCK3DVS1 = 40,\n\tMAX77802_REG_BUCK3DVS2 = 41,\n\tMAX77802_REG_BUCK3DVS3 = 42,\n\tMAX77802_REG_BUCK3DVS4 = 43,\n\tMAX77802_REG_BUCK3DVS5 = 44,\n\tMAX77802_REG_BUCK3DVS6 = 45,\n\tMAX77802_REG_BUCK3DVS7 = 46,\n\tMAX77802_REG_BUCK3DVS8 = 47,\n\tMAX77802_REG_BUCK4CTRL1 = 55,\n\tMAX77802_REG_BUCK4DVS1 = 56,\n\tMAX77802_REG_BUCK4DVS2 = 57,\n\tMAX77802_REG_BUCK4DVS3 = 58,\n\tMAX77802_REG_BUCK4DVS4 = 59,\n\tMAX77802_REG_BUCK4DVS5 = 60,\n\tMAX77802_REG_BUCK4DVS6 = 61,\n\tMAX77802_REG_BUCK4DVS7 = 62,\n\tMAX77802_REG_BUCK4DVS8 = 63,\n\tMAX77802_REG_BUCK5CTRL = 65,\n\tMAX77802_REG_BUCK5OUT = 66,\n\tMAX77802_REG_BUCK6CTRL = 68,\n\tMAX77802_REG_BUCK6DVS1 = 69,\n\tMAX77802_REG_BUCK6DVS2 = 70,\n\tMAX77802_REG_BUCK6DVS3 = 71,\n\tMAX77802_REG_BUCK6DVS4 = 72,\n\tMAX77802_REG_BUCK6DVS5 = 73,\n\tMAX77802_REG_BUCK6DVS6 = 74,\n\tMAX77802_REG_BUCK6DVS7 = 75,\n\tMAX77802_REG_BUCK6DVS8 = 76,\n\tMAX77802_REG_BUCK7CTRL = 78,\n\tMAX77802_REG_BUCK7OUT = 79,\n\tMAX77802_REG_BUCK8CTRL = 81,\n\tMAX77802_REG_BUCK8OUT = 82,\n\tMAX77802_REG_BUCK9CTRL = 84,\n\tMAX77802_REG_BUCK9OUT = 85,\n\tMAX77802_REG_BUCK10CTRL = 87,\n\tMAX77802_REG_BUCK10OUT = 88,\n\tMAX77802_REG_LDO1CTRL1 = 96,\n\tMAX77802_REG_LDO2CTRL1 = 97,\n\tMAX77802_REG_LDO3CTRL1 = 98,\n\tMAX77802_REG_LDO4CTRL1 = 99,\n\tMAX77802_REG_LDO5CTRL1 = 100,\n\tMAX77802_REG_LDO6CTRL1 = 101,\n\tMAX77802_REG_LDO7CTRL1 = 102,\n\tMAX77802_REG_LDO8CTRL1 = 103,\n\tMAX77802_REG_LDO9CTRL1 = 104,\n\tMAX77802_REG_LDO10CTRL1 = 105,\n\tMAX77802_REG_LDO11CTRL1 = 106,\n\tMAX77802_REG_LDO12CTRL1 = 107,\n\tMAX77802_REG_LDO13CTRL1 = 108,\n\tMAX77802_REG_LDO14CTRL1 = 109,\n\tMAX77802_REG_LDO15CTRL1 = 110,\n\tMAX77802_REG_LDO17CTRL1 = 112,\n\tMAX77802_REG_LDO18CTRL1 = 113,\n\tMAX77802_REG_LDO19CTRL1 = 114,\n\tMAX77802_REG_LDO20CTRL1 = 115,\n\tMAX77802_REG_LDO21CTRL1 = 116,\n\tMAX77802_REG_LDO22CTRL1 = 117,\n\tMAX77802_REG_LDO23CTRL1 = 118,\n\tMAX77802_REG_LDO24CTRL1 = 119,\n\tMAX77802_REG_LDO25CTRL1 = 120,\n\tMAX77802_REG_LDO26CTRL1 = 121,\n\tMAX77802_REG_LDO27CTRL1 = 122,\n\tMAX77802_REG_LDO28CTRL1 = 123,\n\tMAX77802_REG_LDO29CTRL1 = 124,\n\tMAX77802_REG_LDO30CTRL1 = 125,\n\tMAX77802_REG_LDO32CTRL1 = 127,\n\tMAX77802_REG_LDO33CTRL1 = 128,\n\tMAX77802_REG_LDO34CTRL1 = 129,\n\tMAX77802_REG_LDO35CTRL1 = 130,\n\tMAX77802_REG_LDO1CTRL2 = 144,\n\tMAX77802_REG_LDO2CTRL2 = 145,\n\tMAX77802_REG_LDO3CTRL2 = 146,\n\tMAX77802_REG_LDO4CTRL2 = 147,\n\tMAX77802_REG_LDO5CTRL2 = 148,\n\tMAX77802_REG_LDO6CTRL2 = 149,\n\tMAX77802_REG_LDO7CTRL2 = 150,\n\tMAX77802_REG_LDO8CTRL2 = 151,\n\tMAX77802_REG_LDO9CTRL2 = 152,\n\tMAX77802_REG_LDO10CTRL2 = 153,\n\tMAX77802_REG_LDO11CTRL2 = 154,\n\tMAX77802_REG_LDO12CTRL2 = 155,\n\tMAX77802_REG_LDO13CTRL2 = 156,\n\tMAX77802_REG_LDO14CTRL2 = 157,\n\tMAX77802_REG_LDO15CTRL2 = 158,\n\tMAX77802_REG_LDO17CTRL2 = 160,\n\tMAX77802_REG_LDO18CTRL2 = 161,\n\tMAX77802_REG_LDO19CTRL2 = 162,\n\tMAX77802_REG_LDO20CTRL2 = 163,\n\tMAX77802_REG_LDO21CTRL2 = 164,\n\tMAX77802_REG_LDO22CTRL2 = 165,\n\tMAX77802_REG_LDO23CTRL2 = 166,\n\tMAX77802_REG_LDO24CTRL2 = 167,\n\tMAX77802_REG_LDO25CTRL2 = 168,\n\tMAX77802_REG_LDO26CTRL2 = 169,\n\tMAX77802_REG_LDO27CTRL2 = 170,\n\tMAX77802_REG_LDO28CTRL2 = 171,\n\tMAX77802_REG_LDO29CTRL2 = 172,\n\tMAX77802_REG_LDO30CTRL2 = 173,\n\tMAX77802_REG_LDO32CTRL2 = 175,\n\tMAX77802_REG_LDO33CTRL2 = 176,\n\tMAX77802_REG_LDO34CTRL2 = 177,\n\tMAX77802_REG_LDO35CTRL2 = 178,\n\tMAX77802_REG_BBAT_CHG = 180,\n\tMAX77802_REG_32KHZ = 181,\n\tMAX77802_REG_PMIC_END = 182,\n};\n\nenum max77802_regulators {\n\tMAX77802_BUCK1 = 0,\n\tMAX77802_BUCK2 = 1,\n\tMAX77802_BUCK3 = 2,\n\tMAX77802_BUCK4 = 3,\n\tMAX77802_BUCK5 = 4,\n\tMAX77802_BUCK6 = 5,\n\tMAX77802_BUCK7 = 6,\n\tMAX77802_BUCK8 = 7,\n\tMAX77802_BUCK9 = 8,\n\tMAX77802_BUCK10 = 9,\n\tMAX77802_LDO1 = 10,\n\tMAX77802_LDO2 = 11,\n\tMAX77802_LDO3 = 12,\n\tMAX77802_LDO4 = 13,\n\tMAX77802_LDO5 = 14,\n\tMAX77802_LDO6 = 15,\n\tMAX77802_LDO7 = 16,\n\tMAX77802_LDO8 = 17,\n\tMAX77802_LDO9 = 18,\n\tMAX77802_LDO10 = 19,\n\tMAX77802_LDO11 = 20,\n\tMAX77802_LDO12 = 21,\n\tMAX77802_LDO13 = 22,\n\tMAX77802_LDO14 = 23,\n\tMAX77802_LDO15 = 24,\n\tMAX77802_LDO17 = 25,\n\tMAX77802_LDO18 = 26,\n\tMAX77802_LDO19 = 27,\n\tMAX77802_LDO20 = 28,\n\tMAX77802_LDO21 = 29,\n\tMAX77802_LDO23 = 30,\n\tMAX77802_LDO24 = 31,\n\tMAX77802_LDO25 = 32,\n\tMAX77802_LDO26 = 33,\n\tMAX77802_LDO27 = 34,\n\tMAX77802_LDO28 = 35,\n\tMAX77802_LDO29 = 36,\n\tMAX77802_LDO30 = 37,\n\tMAX77802_LDO32 = 38,\n\tMAX77802_LDO33 = 39,\n\tMAX77802_LDO34 = 40,\n\tMAX77802_LDO35 = 41,\n\tMAX77802_REG_MAX = 42,\n};\n\nenum max77802_rtc_reg {\n\tMAX77802_RTC_INT = 192,\n\tMAX77802_RTC_INTM = 193,\n\tMAX77802_RTC_CONTROLM = 194,\n\tMAX77802_RTC_CONTROL = 195,\n\tMAX77802_RTC_UPDATE0 = 196,\n\tMAX77802_RTC_UPDATE1 = 197,\n\tMAX77802_WTSR_SMPL_CNTL = 198,\n\tMAX77802_RTC_SEC = 199,\n\tMAX77802_RTC_MIN = 200,\n\tMAX77802_RTC_HOUR = 201,\n\tMAX77802_RTC_WEEKDAY = 202,\n\tMAX77802_RTC_MONTH = 203,\n\tMAX77802_RTC_YEAR = 204,\n\tMAX77802_RTC_MONTHDAY = 205,\n\tMAX77802_RTC_AE1 = 206,\n\tMAX77802_ALARM1_SEC = 207,\n\tMAX77802_ALARM1_MIN = 208,\n\tMAX77802_ALARM1_HOUR = 209,\n\tMAX77802_ALARM1_WEEKDAY = 210,\n\tMAX77802_ALARM1_MONTH = 211,\n\tMAX77802_ALARM1_YEAR = 212,\n\tMAX77802_ALARM1_DATE = 213,\n\tMAX77802_RTC_AE2 = 214,\n\tMAX77802_ALARM2_SEC = 215,\n\tMAX77802_ALARM2_MIN = 216,\n\tMAX77802_ALARM2_HOUR = 217,\n\tMAX77802_ALARM2_WEEKDAY = 218,\n\tMAX77802_ALARM2_MONTH = 219,\n\tMAX77802_ALARM2_YEAR = 220,\n\tMAX77802_ALARM2_DATE = 221,\n\tMAX77802_RTC_END = 223,\n};\n\nenum max77836_fg_reg {\n\tMAX77836_FG_REG_VCELL_MSB = 2,\n\tMAX77836_FG_REG_VCELL_LSB = 3,\n\tMAX77836_FG_REG_SOC_MSB = 4,\n\tMAX77836_FG_REG_SOC_LSB = 5,\n\tMAX77836_FG_REG_MODE_H = 6,\n\tMAX77836_FG_REG_MODE_L = 7,\n\tMAX77836_FG_REG_VERSION_MSB = 8,\n\tMAX77836_FG_REG_VERSION_LSB = 9,\n\tMAX77836_FG_REG_HIBRT_H = 10,\n\tMAX77836_FG_REG_HIBRT_L = 11,\n\tMAX77836_FG_REG_CONFIG_H = 12,\n\tMAX77836_FG_REG_CONFIG_L = 13,\n\tMAX77836_FG_REG_VALRT_MIN = 20,\n\tMAX77836_FG_REG_VALRT_MAX = 21,\n\tMAX77836_FG_REG_CRATE_MSB = 22,\n\tMAX77836_FG_REG_CRATE_LSB = 23,\n\tMAX77836_FG_REG_VRESET = 24,\n\tMAX77836_FG_REG_FGID = 25,\n\tMAX77836_FG_REG_STATUS_H = 26,\n\tMAX77836_FG_REG_STATUS_L = 27,\n\tMAX77836_FG_REG_END = 28,\n};\n\nenum max77836_pmic_reg {\n\tMAX77836_PMIC_REG_PMIC_ID = 32,\n\tMAX77836_PMIC_REG_PMIC_REV = 33,\n\tMAX77836_PMIC_REG_INTSRC = 34,\n\tMAX77836_PMIC_REG_INTSRC_MASK = 35,\n\tMAX77836_PMIC_REG_TOPSYS_INT = 36,\n\tMAX77836_PMIC_REG_TOPSYS_INT_MASK = 38,\n\tMAX77836_PMIC_REG_TOPSYS_STAT = 40,\n\tMAX77836_PMIC_REG_MRSTB_CNTL = 42,\n\tMAX77836_PMIC_REG_LSCNFG = 43,\n\tMAX77836_LDO_REG_CNFG1_LDO1 = 81,\n\tMAX77836_LDO_REG_CNFG2_LDO1 = 82,\n\tMAX77836_LDO_REG_CNFG1_LDO2 = 83,\n\tMAX77836_LDO_REG_CNFG2_LDO2 = 84,\n\tMAX77836_LDO_REG_CNFG_LDO_BIAS = 85,\n\tMAX77836_COMP_REG_COMP1 = 96,\n\tMAX77836_PMIC_REG_END = 97,\n};\n\nenum max8997_haptic_motor_type {\n\tMAX8997_HAPTIC_ERM = 0,\n\tMAX8997_HAPTIC_LRA = 1,\n};\n\nenum max8997_haptic_pulse_mode {\n\tMAX8997_EXTERNAL_MODE = 0,\n\tMAX8997_INTERNAL_MODE = 1,\n};\n\nenum max8997_haptic_pwm_divisor {\n\tMAX8997_PWM_DIVISOR_32 = 0,\n\tMAX8997_PWM_DIVISOR_64 = 1,\n\tMAX8997_PWM_DIVISOR_128 = 2,\n\tMAX8997_PWM_DIVISOR_256 = 3,\n};\n\nenum max8997_haptic_reg {\n\tMAX8997_HAPTIC_REG_GENERAL = 0,\n\tMAX8997_HAPTIC_REG_CONF1 = 1,\n\tMAX8997_HAPTIC_REG_CONF2 = 2,\n\tMAX8997_HAPTIC_REG_DRVCONF = 3,\n\tMAX8997_HAPTIC_REG_CYCLECONF1 = 4,\n\tMAX8997_HAPTIC_REG_CYCLECONF2 = 5,\n\tMAX8997_HAPTIC_REG_SIGCONF1 = 6,\n\tMAX8997_HAPTIC_REG_SIGCONF2 = 7,\n\tMAX8997_HAPTIC_REG_SIGCONF3 = 8,\n\tMAX8997_HAPTIC_REG_SIGCONF4 = 9,\n\tMAX8997_HAPTIC_REG_SIGDC1 = 10,\n\tMAX8997_HAPTIC_REG_SIGDC2 = 11,\n\tMAX8997_HAPTIC_REG_SIGPWMDC1 = 12,\n\tMAX8997_HAPTIC_REG_SIGPWMDC2 = 13,\n\tMAX8997_HAPTIC_REG_SIGPWMDC3 = 14,\n\tMAX8997_HAPTIC_REG_SIGPWMDC4 = 15,\n\tMAX8997_HAPTIC_REG_MTR_REV = 16,\n\tMAX8997_HAPTIC_REG_END = 17,\n};\n\nenum max8997_irq {\n\tMAX8997_PMICIRQ_PWRONR = 0,\n\tMAX8997_PMICIRQ_PWRONF = 1,\n\tMAX8997_PMICIRQ_PWRON1SEC = 2,\n\tMAX8997_PMICIRQ_JIGONR = 3,\n\tMAX8997_PMICIRQ_JIGONF = 4,\n\tMAX8997_PMICIRQ_LOWBAT2 = 5,\n\tMAX8997_PMICIRQ_LOWBAT1 = 6,\n\tMAX8997_PMICIRQ_JIGR = 7,\n\tMAX8997_PMICIRQ_JIGF = 8,\n\tMAX8997_PMICIRQ_MR = 9,\n\tMAX8997_PMICIRQ_DVS1OK = 10,\n\tMAX8997_PMICIRQ_DVS2OK = 11,\n\tMAX8997_PMICIRQ_DVS3OK = 12,\n\tMAX8997_PMICIRQ_DVS4OK = 13,\n\tMAX8997_PMICIRQ_CHGINS = 14,\n\tMAX8997_PMICIRQ_CHGRM = 15,\n\tMAX8997_PMICIRQ_DCINOVP = 16,\n\tMAX8997_PMICIRQ_TOPOFFR = 17,\n\tMAX8997_PMICIRQ_CHGRSTF = 18,\n\tMAX8997_PMICIRQ_MBCHGTMEXPD = 19,\n\tMAX8997_PMICIRQ_RTC60S = 20,\n\tMAX8997_PMICIRQ_RTCA1 = 21,\n\tMAX8997_PMICIRQ_RTCA2 = 22,\n\tMAX8997_PMICIRQ_SMPL_INT = 23,\n\tMAX8997_PMICIRQ_RTC1S = 24,\n\tMAX8997_PMICIRQ_WTSR = 25,\n\tMAX8997_MUICIRQ_ADCError = 26,\n\tMAX8997_MUICIRQ_ADCLow = 27,\n\tMAX8997_MUICIRQ_ADC = 28,\n\tMAX8997_MUICIRQ_VBVolt = 29,\n\tMAX8997_MUICIRQ_DBChg = 30,\n\tMAX8997_MUICIRQ_DCDTmr = 31,\n\tMAX8997_MUICIRQ_ChgDetRun = 32,\n\tMAX8997_MUICIRQ_ChgTyp = 33,\n\tMAX8997_MUICIRQ_OVP = 34,\n\tMAX8997_IRQ_NR = 35,\n};\n\nenum max8997_irq_source {\n\tPMIC_INT1___2 = 0,\n\tPMIC_INT2___2 = 1,\n\tPMIC_INT3 = 2,\n\tPMIC_INT4 = 3,\n\tFUEL_GAUGE = 4,\n\tMUIC_INT1 = 5,\n\tMUIC_INT2 = 6,\n\tMUIC_INT3 = 7,\n\tGPIO_LOW = 8,\n\tGPIO_HI = 9,\n\tFLASH_STATUS = 10,\n\tMAX8997_IRQ_GROUP_NR = 11,\n};\n\nenum max8997_led_mode {\n\tMAX8997_NONE = 0,\n\tMAX8997_FLASH_MODE = 1,\n\tMAX8997_MOVIE_MODE = 2,\n\tMAX8997_FLASH_PIN_CONTROL_MODE = 3,\n\tMAX8997_MOVIE_PIN_CONTROL_MODE = 4,\n};\n\nenum max8997_muic_reg {\n\tMAX8997_MUIC_REG_ID = 0,\n\tMAX8997_MUIC_REG_INT1 = 1,\n\tMAX8997_MUIC_REG_INT2 = 2,\n\tMAX8997_MUIC_REG_INT3 = 3,\n\tMAX8997_MUIC_REG_STATUS1 = 4,\n\tMAX8997_MUIC_REG_STATUS2 = 5,\n\tMAX8997_MUIC_REG_STATUS3 = 6,\n\tMAX8997_MUIC_REG_INTMASK1 = 7,\n\tMAX8997_MUIC_REG_INTMASK2 = 8,\n\tMAX8997_MUIC_REG_INTMASK3 = 9,\n\tMAX8997_MUIC_REG_CDETCTRL = 10,\n\tMAX8997_MUIC_REG_CONTROL1 = 12,\n\tMAX8997_MUIC_REG_CONTROL2 = 13,\n\tMAX8997_MUIC_REG_CONTROL3 = 14,\n\tMAX8997_MUIC_REG_END = 15,\n};\n\nenum max8997_pmic_reg {\n\tMAX8997_REG_PMIC_ID0 = 0,\n\tMAX8997_REG_PMIC_ID1 = 1,\n\tMAX8997_REG_INTSRC = 2,\n\tMAX8997_REG_INT1 = 3,\n\tMAX8997_REG_INT2 = 4,\n\tMAX8997_REG_INT3 = 5,\n\tMAX8997_REG_INT4 = 6,\n\tMAX8997_REG_INT1MSK = 8,\n\tMAX8997_REG_INT2MSK = 9,\n\tMAX8997_REG_INT3MSK = 10,\n\tMAX8997_REG_INT4MSK = 11,\n\tMAX8997_REG_STATUS1 = 13,\n\tMAX8997_REG_STATUS2 = 14,\n\tMAX8997_REG_STATUS3 = 15,\n\tMAX8997_REG_STATUS4 = 16,\n\tMAX8997_REG_MAINCON1 = 19,\n\tMAX8997_REG_MAINCON2 = 20,\n\tMAX8997_REG_BUCKRAMP = 21,\n\tMAX8997_REG_BUCK1CTRL = 24,\n\tMAX8997_REG_BUCK1DVS1 = 25,\n\tMAX8997_REG_BUCK1DVS2 = 26,\n\tMAX8997_REG_BUCK1DVS3 = 27,\n\tMAX8997_REG_BUCK1DVS4 = 28,\n\tMAX8997_REG_BUCK1DVS5 = 29,\n\tMAX8997_REG_BUCK1DVS6 = 30,\n\tMAX8997_REG_BUCK1DVS7 = 31,\n\tMAX8997_REG_BUCK1DVS8 = 32,\n\tMAX8997_REG_BUCK2CTRL = 33,\n\tMAX8997_REG_BUCK2DVS1 = 34,\n\tMAX8997_REG_BUCK2DVS2 = 35,\n\tMAX8997_REG_BUCK2DVS3 = 36,\n\tMAX8997_REG_BUCK2DVS4 = 37,\n\tMAX8997_REG_BUCK2DVS5 = 38,\n\tMAX8997_REG_BUCK2DVS6 = 39,\n\tMAX8997_REG_BUCK2DVS7 = 40,\n\tMAX8997_REG_BUCK2DVS8 = 41,\n\tMAX8997_REG_BUCK3CTRL = 42,\n\tMAX8997_REG_BUCK3DVS = 43,\n\tMAX8997_REG_BUCK4CTRL = 44,\n\tMAX8997_REG_BUCK4DVS = 45,\n\tMAX8997_REG_BUCK5CTRL = 46,\n\tMAX8997_REG_BUCK5DVS1 = 47,\n\tMAX8997_REG_BUCK5DVS2 = 48,\n\tMAX8997_REG_BUCK5DVS3 = 49,\n\tMAX8997_REG_BUCK5DVS4 = 50,\n\tMAX8997_REG_BUCK5DVS5 = 51,\n\tMAX8997_REG_BUCK5DVS6 = 52,\n\tMAX8997_REG_BUCK5DVS7 = 53,\n\tMAX8997_REG_BUCK5DVS8 = 54,\n\tMAX8997_REG_BUCK6CTRL = 55,\n\tMAX8997_REG_BUCK6BPSKIPCTRL = 56,\n\tMAX8997_REG_BUCK7CTRL = 57,\n\tMAX8997_REG_BUCK7DVS = 58,\n\tMAX8997_REG_LDO1CTRL = 59,\n\tMAX8997_REG_LDO2CTRL = 60,\n\tMAX8997_REG_LDO3CTRL = 61,\n\tMAX8997_REG_LDO4CTRL = 62,\n\tMAX8997_REG_LDO5CTRL = 63,\n\tMAX8997_REG_LDO6CTRL = 64,\n\tMAX8997_REG_LDO7CTRL = 65,\n\tMAX8997_REG_LDO8CTRL = 66,\n\tMAX8997_REG_LDO9CTRL = 67,\n\tMAX8997_REG_LDO10CTRL = 68,\n\tMAX8997_REG_LDO11CTRL = 69,\n\tMAX8997_REG_LDO12CTRL = 70,\n\tMAX8997_REG_LDO13CTRL = 71,\n\tMAX8997_REG_LDO14CTRL = 72,\n\tMAX8997_REG_LDO15CTRL = 73,\n\tMAX8997_REG_LDO16CTRL = 74,\n\tMAX8997_REG_LDO17CTRL = 75,\n\tMAX8997_REG_LDO18CTRL = 76,\n\tMAX8997_REG_LDO21CTRL = 77,\n\tMAX8997_REG_MBCCTRL1 = 80,\n\tMAX8997_REG_MBCCTRL2 = 81,\n\tMAX8997_REG_MBCCTRL3 = 82,\n\tMAX8997_REG_MBCCTRL4 = 83,\n\tMAX8997_REG_MBCCTRL5 = 84,\n\tMAX8997_REG_MBCCTRL6 = 85,\n\tMAX8997_REG_OTPCGHCVS = 86,\n\tMAX8997_REG_SAFEOUTCTRL = 90,\n\tMAX8997_REG_LBCNFG1 = 94,\n\tMAX8997_REG_LBCNFG2 = 95,\n\tMAX8997_REG_BBCCTRL = 96,\n\tMAX8997_REG_FLASH1_CUR = 99,\n\tMAX8997_REG_FLASH2_CUR = 100,\n\tMAX8997_REG_MOVIE_CUR = 101,\n\tMAX8997_REG_GSMB_CUR = 102,\n\tMAX8997_REG_BOOST_CNTL = 103,\n\tMAX8997_REG_LEN_CNTL = 104,\n\tMAX8997_REG_FLASH_CNTL = 105,\n\tMAX8997_REG_WDT_CNTL = 106,\n\tMAX8997_REG_MAXFLASH1 = 107,\n\tMAX8997_REG_MAXFLASH2 = 108,\n\tMAX8997_REG_FLASHSTATUS = 109,\n\tMAX8997_REG_FLASHSTATUSMASK = 110,\n\tMAX8997_REG_GPIOCNTL1 = 112,\n\tMAX8997_REG_GPIOCNTL2 = 113,\n\tMAX8997_REG_GPIOCNTL3 = 114,\n\tMAX8997_REG_GPIOCNTL4 = 115,\n\tMAX8997_REG_GPIOCNTL5 = 116,\n\tMAX8997_REG_GPIOCNTL6 = 117,\n\tMAX8997_REG_GPIOCNTL7 = 118,\n\tMAX8997_REG_GPIOCNTL8 = 119,\n\tMAX8997_REG_GPIOCNTL9 = 120,\n\tMAX8997_REG_GPIOCNTL10 = 121,\n\tMAX8997_REG_GPIOCNTL11 = 122,\n\tMAX8997_REG_GPIOCNTL12 = 123,\n\tMAX8997_REG_LDO1CONFIG = 128,\n\tMAX8997_REG_LDO2CONFIG = 129,\n\tMAX8997_REG_LDO3CONFIG = 130,\n\tMAX8997_REG_LDO4CONFIG = 131,\n\tMAX8997_REG_LDO5CONFIG = 132,\n\tMAX8997_REG_LDO6CONFIG = 133,\n\tMAX8997_REG_LDO7CONFIG = 134,\n\tMAX8997_REG_LDO8CONFIG = 135,\n\tMAX8997_REG_LDO9CONFIG = 136,\n\tMAX8997_REG_LDO10CONFIG = 137,\n\tMAX8997_REG_LDO11CONFIG = 138,\n\tMAX8997_REG_LDO12CONFIG = 139,\n\tMAX8997_REG_LDO13CONFIG = 140,\n\tMAX8997_REG_LDO14CONFIG = 141,\n\tMAX8997_REG_LDO15CONFIG = 142,\n\tMAX8997_REG_LDO16CONFIG = 143,\n\tMAX8997_REG_LDO17CONFIG = 144,\n\tMAX8997_REG_LDO18CONFIG = 145,\n\tMAX8997_REG_LDO21CONFIG = 146,\n\tMAX8997_REG_DVSOKTIMER1 = 151,\n\tMAX8997_REG_DVSOKTIMER2 = 152,\n\tMAX8997_REG_DVSOKTIMER4 = 153,\n\tMAX8997_REG_DVSOKTIMER5 = 154,\n\tMAX8997_REG_PMIC_END = 155,\n};\n\nenum max8997_types {\n\tTYPE_MAX8997 = 0,\n\tTYPE_MAX8966 = 1,\n};\n\nenum maxim_device_type {\n\tMAXIM_DEVICE_TYPE_UNKNOWN = 0,\n\tMAXIM_DEVICE_TYPE_MAX14577 = 1,\n\tMAXIM_DEVICE_TYPE_MAX77836 = 2,\n\tMAXIM_DEVICE_TYPE_NUM = 3,\n};\n\nenum mcp251x_model {\n\tCAN_MCP251X_MCP2510 = 9488,\n\tCAN_MCP251X_MCP2515 = 9493,\n\tCAN_MCP251X_MCP25625 = 153125,\n};\n\nenum mctrl_gpio_idx {\n\tUART_GPIO_CTS = 0,\n\tUART_GPIO_DSR = 1,\n\tUART_GPIO_DCD = 2,\n\tUART_GPIO_RNG = 3,\n\tUART_GPIO_RI = 3,\n\tUART_GPIO_RTS = 4,\n\tUART_GPIO_DTR = 5,\n\tUART_GPIO_MAX = 6,\n};\n\nenum mem_type {\n\tMEM_EMPTY = 0,\n\tMEM_RESERVED = 1,\n\tMEM_UNKNOWN = 2,\n\tMEM_FPM = 3,\n\tMEM_EDO = 4,\n\tMEM_BEDO = 5,\n\tMEM_SDR = 6,\n\tMEM_RDR = 7,\n\tMEM_DDR = 8,\n\tMEM_RDDR = 9,\n\tMEM_RMBS = 10,\n\tMEM_DDR2 = 11,\n\tMEM_FB_DDR2 = 12,\n\tMEM_RDDR2 = 13,\n\tMEM_XDR = 14,\n\tMEM_DDR3 = 15,\n\tMEM_RDDR3 = 16,\n\tMEM_LRDDR3 = 17,\n\tMEM_LPDDR3 = 18,\n\tMEM_DDR4 = 19,\n\tMEM_RDDR4 = 20,\n\tMEM_LRDDR4 = 21,\n\tMEM_LPDDR4 = 22,\n\tMEM_DDR5 = 23,\n\tMEM_RDDR5 = 24,\n\tMEM_LRDDR5 = 25,\n\tMEM_NVDIMM = 26,\n\tMEM_WIO2 = 27,\n\tMEM_HBM2 = 28,\n\tMEM_HBM3 = 29,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 47,\n\tMEMCG_SOCK = 48,\n\tMEMCG_PERCPU_B = 49,\n\tMEMCG_VMALLOC = 50,\n\tMEMCG_KMEM = 51,\n\tMEMCG_ZSWAP_B = 52,\n\tMEMCG_ZSWAPPED = 53,\n\tMEMCG_NR_STAT = 54,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum meson_pinconf_drv {\n\tMESON_PINCONF_DRV_500UA = 0,\n\tMESON_PINCONF_DRV_2500UA = 1,\n\tMESON_PINCONF_DRV_3000UA = 2,\n\tMESON_PINCONF_DRV_4000UA = 3,\n};\n\nenum meson_reg_type {\n\tMESON_REG_PULLEN = 0,\n\tMESON_REG_PULL = 1,\n\tMESON_REG_DIR = 2,\n\tMESON_REG_OUT = 3,\n\tMESON_REG_IN = 4,\n\tMESON_REG_DS = 5,\n\tMESON_NUM_REG = 6,\n};\n\nenum meson_soc_id {\n\tMESON_SOC_G12A = 0,\n\tMESON_SOC_A1 = 1,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mext_move_type {\n\tMEXT_SKIP_EXTENT = 0,\n\tMEXT_MOVE_EXTENT = 1,\n\tMEXT_COPY_DATA = 2,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\tMIGRATE_CMA = 4,\n\t__MIGRATE_TYPE_END = 4,\n\tMIGRATE_ISOLATE = 5,\n\tMIGRATE_TYPES = 6,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum miic_type {\n\tMIIC_TYPE_RZN1 = 0,\n\tMIIC_TYPE_RZT2H = 1,\n};\n\nenum miphy_sata_gen {\n\tSATA_GEN1 = 0,\n\tSATA_GEN2 = 1,\n\tSATA_GEN3 = 2,\n};\n\nenum mipi_dsi_compression_algo {\n\tMIPI_DSI_COMPRESSION_DSC = 0,\n\tMIPI_DSI_COMPRESSION_VENDOR = 3,\n};\n\nenum mipi_dsi_dcs_tear_mode {\n\tMIPI_DSI_DCS_TEAR_MODE_VBLANK = 0,\n\tMIPI_DSI_DCS_TEAR_MODE_VHBLANK = 1,\n};\n\nenum mipi_dsi_pixel_format {\n\tMIPI_DSI_FMT_RGB888 = 0,\n\tMIPI_DSI_FMT_RGB666 = 1,\n\tMIPI_DSI_FMT_RGB666_PACKED = 2,\n\tMIPI_DSI_FMT_RGB565 = 3,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mmc_busy_cmd {\n\tMMC_BUSY_CMD6 = 0,\n\tMMC_BUSY_ERASE = 1,\n\tMMC_BUSY_HPI = 2,\n\tMMC_BUSY_EXTR_SINGLE = 3,\n\tMMC_BUSY_IO = 4,\n};\n\nenum mmc_drv_op {\n\tMMC_DRV_OP_IOCTL = 0,\n\tMMC_DRV_OP_IOCTL_RPMB = 1,\n\tMMC_DRV_OP_BOOT_WP = 2,\n\tMMC_DRV_OP_GET_CARD_STATUS = 3,\n\tMMC_DRV_OP_GET_EXT_CSD = 4,\n};\n\nenum mmc_err_stat {\n\tMMC_ERR_CMD_TIMEOUT = 0,\n\tMMC_ERR_CMD_CRC = 1,\n\tMMC_ERR_DAT_TIMEOUT = 2,\n\tMMC_ERR_DAT_CRC = 3,\n\tMMC_ERR_AUTO_CMD = 4,\n\tMMC_ERR_ADMA = 5,\n\tMMC_ERR_TUNING = 6,\n\tMMC_ERR_CMDQ_RED = 7,\n\tMMC_ERR_CMDQ_GCE = 8,\n\tMMC_ERR_CMDQ_ICCE = 9,\n\tMMC_ERR_REQ_TIMEOUT = 10,\n\tMMC_ERR_CMDQ_REQ_TIMEOUT = 11,\n\tMMC_ERR_ICE_CFG = 12,\n\tMMC_ERR_CTRL_TIMEOUT = 13,\n\tMMC_ERR_UNEXPECTED_IRQ = 14,\n\tMMC_ERR_MAX = 15,\n};\n\nenum mmc_issue_type {\n\tMMC_ISSUE_SYNC = 0,\n\tMMC_ISSUE_DCMD = 1,\n\tMMC_ISSUE_ASYNC = 2,\n\tMMC_ISSUE_MAX = 3,\n};\n\nenum mmc_issued {\n\tMMC_REQ_STARTED = 0,\n\tMMC_REQ_BUSY = 1,\n\tMMC_REQ_FAILED_TO_START = 2,\n\tMMC_REQ_FINISHED = 3,\n};\n\nenum mmc_poweroff_type {\n\tMMC_POWEROFF_SUSPEND = 0,\n\tMMC_POWEROFF_SHUTDOWN = 1,\n\tMMC_POWEROFF_UNDERVOLTAGE = 2,\n\tMMC_POWEROFF_UNBIND = 3,\n};\n\nenum mmci_busy_state {\n\tMMCI_BUSY_WAITING_FOR_START_IRQ = 0,\n\tMMCI_BUSY_WAITING_FOR_END_IRQ = 1,\n\tMMCI_BUSY_DONE = 2,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mmp2_clk_model {\n\tCLK_MODEL_MMP2 = 0,\n\tCLK_MODEL_MMP3 = 1,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mountstat {\n\tMNT_OK = 0,\n\tMNT_EPERM = 1,\n\tMNT_ENOENT = 2,\n\tMNT_EACCES = 13,\n\tMNT_EINVAL = 22,\n};\n\nenum mountstat3 {\n\tMNT3_OK = 0,\n\tMNT3ERR_PERM = 1,\n\tMNT3ERR_NOENT = 2,\n\tMNT3ERR_IO = 5,\n\tMNT3ERR_ACCES = 13,\n\tMNT3ERR_NOTDIR = 20,\n\tMNT3ERR_INVAL = 22,\n\tMNT3ERR_NAMETOOLONG = 63,\n\tMNT3ERR_NOTSUPP = 10004,\n\tMNT3ERR_SERVERFAULT = 10006,\n};\n\nenum mpu3050_fullscale {\n\tFS_250_DPS = 0,\n\tFS_500_DPS = 1,\n\tFS_1000_DPS = 2,\n\tFS_2000_DPS = 3,\n};\n\nenum mpu3050_lpf {\n\tLPF_256_HZ_NOLPF = 0,\n\tLPF_188_HZ = 1,\n\tLPF_98_HZ = 2,\n\tLPF_42_HZ = 3,\n\tLPF_20_HZ = 4,\n\tLPF_10_HZ = 5,\n\tLPF_5_HZ = 6,\n\tLPF_2100_HZ_NOLPF = 7,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msg_end_type {\n\tMSG_END_STOP = 0,\n\tMSG_END_REPEAT_START = 1,\n\tMSG_END_CONTINUE = 2,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum msm8660_functions {\n\tmsm_mux_gpio = 0,\n\tmsm_mux_cam_mclk = 1,\n\tmsm_mux_dsub = 2,\n\tmsm_mux_ext_gps = 3,\n\tmsm_mux_gp_clk_0a = 4,\n\tmsm_mux_gp_clk_0b = 5,\n\tmsm_mux_gp_clk_1a = 6,\n\tmsm_mux_gp_clk_1b = 7,\n\tmsm_mux_gp_clk_2a = 8,\n\tmsm_mux_gp_clk_2b = 9,\n\tmsm_mux_gp_mn = 10,\n\tmsm_mux_gsbi1 = 11,\n\tmsm_mux_gsbi1_spi_cs1_n = 12,\n\tmsm_mux_gsbi1_spi_cs2a_n = 13,\n\tmsm_mux_gsbi1_spi_cs2b_n = 14,\n\tmsm_mux_gsbi1_spi_cs3_n = 15,\n\tmsm_mux_gsbi2 = 16,\n\tmsm_mux_gsbi2_spi_cs1_n = 17,\n\tmsm_mux_gsbi2_spi_cs2_n = 18,\n\tmsm_mux_gsbi2_spi_cs3_n = 19,\n\tmsm_mux_gsbi3 = 20,\n\tmsm_mux_gsbi3_spi_cs1_n = 21,\n\tmsm_mux_gsbi3_spi_cs2_n = 22,\n\tmsm_mux_gsbi3_spi_cs3_n = 23,\n\tmsm_mux_gsbi4 = 24,\n\tmsm_mux_gsbi5 = 25,\n\tmsm_mux_gsbi6 = 26,\n\tmsm_mux_gsbi7 = 27,\n\tmsm_mux_gsbi8 = 28,\n\tmsm_mux_gsbi9 = 29,\n\tmsm_mux_gsbi10 = 30,\n\tmsm_mux_gsbi11 = 31,\n\tmsm_mux_gsbi12 = 32,\n\tmsm_mux_hdmi = 33,\n\tmsm_mux_i2s = 34,\n\tmsm_mux_lcdc = 35,\n\tmsm_mux_mdp_vsync = 36,\n\tmsm_mux_mi2s = 37,\n\tmsm_mux_pcm = 38,\n\tmsm_mux_ps_hold = 39,\n\tmsm_mux_sdc1 = 40,\n\tmsm_mux_sdc2 = 41,\n\tmsm_mux_sdc5 = 42,\n\tmsm_mux_tsif1 = 43,\n\tmsm_mux_tsif2 = 44,\n\tmsm_mux_usb_fs1 = 45,\n\tmsm_mux_usb_fs1_oe_n = 46,\n\tmsm_mux_usb_fs2 = 47,\n\tmsm_mux_usb_fs2_oe_n = 48,\n\tmsm_mux_vfe = 49,\n\tmsm_mux_vsens_alarm = 50,\n\tmsm_mux_ebi2cs = 51,\n\tmsm_mux_ebi2 = 52,\n\tmsm_mux__ = 53,\n};\n\nenum msm8916_functions {\n\tmsm_mux_adsp_ext = 0,\n\tmsm_mux_alsp_int = 1,\n\tmsm_mux_atest_bbrx0 = 2,\n\tmsm_mux_atest_bbrx1 = 3,\n\tmsm_mux_atest_char = 4,\n\tmsm_mux_atest_char0 = 5,\n\tmsm_mux_atest_char1 = 6,\n\tmsm_mux_atest_char2 = 7,\n\tmsm_mux_atest_char3 = 8,\n\tmsm_mux_atest_combodac = 9,\n\tmsm_mux_atest_gpsadc0 = 10,\n\tmsm_mux_atest_gpsadc1 = 11,\n\tmsm_mux_atest_tsens = 12,\n\tmsm_mux_atest_wlan0 = 13,\n\tmsm_mux_atest_wlan1 = 14,\n\tmsm_mux_backlight_en = 15,\n\tmsm_mux_bimc_dte0 = 16,\n\tmsm_mux_bimc_dte1 = 17,\n\tmsm_mux_blsp_i2c1 = 18,\n\tmsm_mux_blsp_i2c2 = 19,\n\tmsm_mux_blsp_i2c3 = 20,\n\tmsm_mux_blsp_i2c4 = 21,\n\tmsm_mux_blsp_i2c5 = 22,\n\tmsm_mux_blsp_i2c6 = 23,\n\tmsm_mux_blsp_spi1 = 24,\n\tmsm_mux_blsp_spi1_cs1 = 25,\n\tmsm_mux_blsp_spi1_cs2 = 26,\n\tmsm_mux_blsp_spi1_cs3 = 27,\n\tmsm_mux_blsp_spi2 = 28,\n\tmsm_mux_blsp_spi2_cs1 = 29,\n\tmsm_mux_blsp_spi2_cs2 = 30,\n\tmsm_mux_blsp_spi2_cs3 = 31,\n\tmsm_mux_blsp_spi3 = 32,\n\tmsm_mux_blsp_spi3_cs1 = 33,\n\tmsm_mux_blsp_spi3_cs2 = 34,\n\tmsm_mux_blsp_spi3_cs3 = 35,\n\tmsm_mux_blsp_spi4 = 36,\n\tmsm_mux_blsp_spi5 = 37,\n\tmsm_mux_blsp_spi6 = 38,\n\tmsm_mux_blsp_uart1 = 39,\n\tmsm_mux_blsp_uart2 = 40,\n\tmsm_mux_blsp_uim1 = 41,\n\tmsm_mux_blsp_uim2 = 42,\n\tmsm_mux_cam1_rst = 43,\n\tmsm_mux_cam1_standby = 44,\n\tmsm_mux_cam_mclk0 = 45,\n\tmsm_mux_cam_mclk1 = 46,\n\tmsm_mux_cci_async = 47,\n\tmsm_mux_cci_i2c = 48,\n\tmsm_mux_cci_timer0 = 49,\n\tmsm_mux_cci_timer1 = 50,\n\tmsm_mux_cci_timer2 = 51,\n\tmsm_mux_cdc_pdm0 = 52,\n\tmsm_mux_codec_mad = 53,\n\tmsm_mux_dbg_out = 54,\n\tmsm_mux_display_5v = 55,\n\tmsm_mux_dmic0_clk = 56,\n\tmsm_mux_dmic0_data = 57,\n\tmsm_mux_dsi_rst = 58,\n\tmsm_mux_ebi0_wrcdc = 59,\n\tmsm_mux_euro_us = 60,\n\tmsm_mux_ext_lpass = 61,\n\tmsm_mux_flash_strobe = 62,\n\tmsm_mux_gcc_gp1_clk_a = 63,\n\tmsm_mux_gcc_gp1_clk_b = 64,\n\tmsm_mux_gcc_gp2_clk_a = 65,\n\tmsm_mux_gcc_gp2_clk_b = 66,\n\tmsm_mux_gcc_gp3_clk_a = 67,\n\tmsm_mux_gcc_gp3_clk_b = 68,\n\tmsm_mux_gpio___2 = 69,\n\tmsm_mux_gsm0_tx0 = 70,\n\tmsm_mux_gsm0_tx1 = 71,\n\tmsm_mux_gsm1_tx0 = 72,\n\tmsm_mux_gsm1_tx1 = 73,\n\tmsm_mux_gyro_accl = 74,\n\tmsm_mux_kpsns0 = 75,\n\tmsm_mux_kpsns1 = 76,\n\tmsm_mux_kpsns2 = 77,\n\tmsm_mux_ldo_en = 78,\n\tmsm_mux_ldo_update = 79,\n\tmsm_mux_mag_int = 80,\n\tmsm_mux_mdp_vsync___2 = 81,\n\tmsm_mux_modem_tsync = 82,\n\tmsm_mux_m_voc = 83,\n\tmsm_mux_nav_pps = 84,\n\tmsm_mux_nav_tsync = 85,\n\tmsm_mux_pa_indicator = 86,\n\tmsm_mux_pbs0 = 87,\n\tmsm_mux_pbs1 = 88,\n\tmsm_mux_pbs2 = 89,\n\tmsm_mux_pri_mi2s = 90,\n\tmsm_mux_pri_mi2s_ws = 91,\n\tmsm_mux_prng_rosc = 92,\n\tmsm_mux_pwr_crypto_enabled_a = 93,\n\tmsm_mux_pwr_crypto_enabled_b = 94,\n\tmsm_mux_pwr_modem_enabled_a = 95,\n\tmsm_mux_pwr_modem_enabled_b = 96,\n\tmsm_mux_pwr_nav_enabled_a = 97,\n\tmsm_mux_pwr_nav_enabled_b = 98,\n\tmsm_mux_qdss_ctitrig_in_a0 = 99,\n\tmsm_mux_qdss_ctitrig_in_a1 = 100,\n\tmsm_mux_qdss_ctitrig_in_b0 = 101,\n\tmsm_mux_qdss_ctitrig_in_b1 = 102,\n\tmsm_mux_qdss_ctitrig_out_a0 = 103,\n\tmsm_mux_qdss_ctitrig_out_a1 = 104,\n\tmsm_mux_qdss_ctitrig_out_b0 = 105,\n\tmsm_mux_qdss_ctitrig_out_b1 = 106,\n\tmsm_mux_qdss_traceclk_a = 107,\n\tmsm_mux_qdss_traceclk_b = 108,\n\tmsm_mux_qdss_tracectl_a = 109,\n\tmsm_mux_qdss_tracectl_b = 110,\n\tmsm_mux_qdss_tracedata_a = 111,\n\tmsm_mux_qdss_tracedata_b = 112,\n\tmsm_mux_reset_n = 113,\n\tmsm_mux_sd_card = 114,\n\tmsm_mux_sd_write = 115,\n\tmsm_mux_sec_mi2s = 116,\n\tmsm_mux_smb_int = 117,\n\tmsm_mux_ssbi_wtr0 = 118,\n\tmsm_mux_ssbi_wtr1 = 119,\n\tmsm_mux_uim1 = 120,\n\tmsm_mux_uim2 = 121,\n\tmsm_mux_uim3 = 122,\n\tmsm_mux_uim_batt = 123,\n\tmsm_mux_wcss_bt = 124,\n\tmsm_mux_wcss_fm = 125,\n\tmsm_mux_wcss_wlan = 126,\n\tmsm_mux_webcam1_rst = 127,\n\tmsm_mux_NA = 128,\n};\n\nenum msm8960_functions {\n\tmsm_mux_audio_pcm = 0,\n\tmsm_mux_bt = 1,\n\tmsm_mux_cam_mclk0___2 = 2,\n\tmsm_mux_cam_mclk1___2 = 3,\n\tmsm_mux_cam_mclk2 = 4,\n\tmsm_mux_codec_mic_i2s = 5,\n\tmsm_mux_codec_spkr_i2s = 6,\n\tmsm_mux_ext_gps___2 = 7,\n\tmsm_mux_fm = 8,\n\tmsm_mux_gps_blanking = 9,\n\tmsm_mux_gps_pps_in = 10,\n\tmsm_mux_gps_pps_out = 11,\n\tmsm_mux_gp_clk_0a___2 = 12,\n\tmsm_mux_gp_clk_0b___2 = 13,\n\tmsm_mux_gp_clk_1a___2 = 14,\n\tmsm_mux_gp_clk_1b___2 = 15,\n\tmsm_mux_gp_clk_2a___2 = 16,\n\tmsm_mux_gp_clk_2b___2 = 17,\n\tmsm_mux_gp_mn___2 = 18,\n\tmsm_mux_gp_pdm_0a = 19,\n\tmsm_mux_gp_pdm_0b = 20,\n\tmsm_mux_gp_pdm_1a = 21,\n\tmsm_mux_gp_pdm_1b = 22,\n\tmsm_mux_gp_pdm_2a = 23,\n\tmsm_mux_gp_pdm_2b = 24,\n\tmsm_mux_gpio___3 = 25,\n\tmsm_mux_gsbi1___2 = 26,\n\tmsm_mux_gsbi1_spi_cs1_n___2 = 27,\n\tmsm_mux_gsbi1_spi_cs2a_n___2 = 28,\n\tmsm_mux_gsbi1_spi_cs2b_n___2 = 29,\n\tmsm_mux_gsbi1_spi_cs3_n___2 = 30,\n\tmsm_mux_gsbi2___2 = 31,\n\tmsm_mux_gsbi2_spi_cs1_n___2 = 32,\n\tmsm_mux_gsbi2_spi_cs2_n___2 = 33,\n\tmsm_mux_gsbi2_spi_cs3_n___2 = 34,\n\tmsm_mux_gsbi3___2 = 35,\n\tmsm_mux_gsbi4___2 = 36,\n\tmsm_mux_gsbi4_3d_cam_i2c_l = 37,\n\tmsm_mux_gsbi4_3d_cam_i2c_r = 38,\n\tmsm_mux_gsbi5___2 = 39,\n\tmsm_mux_gsbi5_3d_cam_i2c_l = 40,\n\tmsm_mux_gsbi5_3d_cam_i2c_r = 41,\n\tmsm_mux_gsbi6___2 = 42,\n\tmsm_mux_gsbi7___2 = 43,\n\tmsm_mux_gsbi8___2 = 44,\n\tmsm_mux_gsbi9___2 = 45,\n\tmsm_mux_gsbi10___2 = 46,\n\tmsm_mux_gsbi11___2 = 47,\n\tmsm_mux_gsbi11_spi_cs1a_n = 48,\n\tmsm_mux_gsbi11_spi_cs1b_n = 49,\n\tmsm_mux_gsbi11_spi_cs2a_n = 50,\n\tmsm_mux_gsbi11_spi_cs2b_n = 51,\n\tmsm_mux_gsbi11_spi_cs3_n = 52,\n\tmsm_mux_gsbi12___2 = 53,\n\tmsm_mux_hdmi_cec = 54,\n\tmsm_mux_hdmi_ddc_clock = 55,\n\tmsm_mux_hdmi_ddc_data = 56,\n\tmsm_mux_hdmi_hot_plug_detect = 57,\n\tmsm_mux_hsic = 58,\n\tmsm_mux_mdp_vsync___3 = 59,\n\tmsm_mux_mi2s___2 = 60,\n\tmsm_mux_mic_i2s = 61,\n\tmsm_mux_pmb_clk = 62,\n\tmsm_mux_pmb_ext_ctrl = 63,\n\tmsm_mux_ps_hold___2 = 64,\n\tmsm_mux_rpm_wdog = 65,\n\tmsm_mux_sdc2___2 = 66,\n\tmsm_mux_sdc4 = 67,\n\tmsm_mux_sdc5___2 = 68,\n\tmsm_mux_slimbus1 = 69,\n\tmsm_mux_slimbus2 = 70,\n\tmsm_mux_spkr_i2s = 71,\n\tmsm_mux_ssbi1 = 72,\n\tmsm_mux_ssbi2 = 73,\n\tmsm_mux_ssbi_ext_gps = 74,\n\tmsm_mux_ssbi_pmic2 = 75,\n\tmsm_mux_ssbi_qpa1 = 76,\n\tmsm_mux_ssbi_ts = 77,\n\tmsm_mux_tsif1___2 = 78,\n\tmsm_mux_tsif2___2 = 79,\n\tmsm_mux_ts_eoc = 80,\n\tmsm_mux_usb_fs1___2 = 81,\n\tmsm_mux_usb_fs1_oe = 82,\n\tmsm_mux_usb_fs1_oe_n___2 = 83,\n\tmsm_mux_usb_fs2___2 = 84,\n\tmsm_mux_usb_fs2_oe = 85,\n\tmsm_mux_usb_fs2_oe_n___2 = 86,\n\tmsm_mux_vfe_camif_timer1_a = 87,\n\tmsm_mux_vfe_camif_timer1_b = 88,\n\tmsm_mux_vfe_camif_timer2 = 89,\n\tmsm_mux_vfe_camif_timer3_a = 90,\n\tmsm_mux_vfe_camif_timer3_b = 91,\n\tmsm_mux_vfe_camif_timer4_a = 92,\n\tmsm_mux_vfe_camif_timer4_b = 93,\n\tmsm_mux_vfe_camif_timer4_c = 94,\n\tmsm_mux_vfe_camif_timer5_a = 95,\n\tmsm_mux_vfe_camif_timer5_b = 96,\n\tmsm_mux_vfe_camif_timer6_a = 97,\n\tmsm_mux_vfe_camif_timer6_b = 98,\n\tmsm_mux_vfe_camif_timer6_c = 99,\n\tmsm_mux_vfe_camif_timer7_a = 100,\n\tmsm_mux_vfe_camif_timer7_b = 101,\n\tmsm_mux_vfe_camif_timer7_c = 102,\n\tmsm_mux_wlan = 103,\n\tmsm_mux_NA___2 = 104,\n};\n\nenum msm8x74_functions {\n\tmsm_mux_gpio___4 = 0,\n\tmsm_mux_cci_i2c0 = 1,\n\tmsm_mux_cci_i2c1 = 2,\n\tmsm_mux_blsp_i2c1___2 = 3,\n\tmsm_mux_blsp_i2c2___2 = 4,\n\tmsm_mux_blsp_i2c3___2 = 5,\n\tmsm_mux_blsp_i2c4___2 = 6,\n\tmsm_mux_blsp_i2c5___2 = 7,\n\tmsm_mux_blsp_i2c6___2 = 8,\n\tmsm_mux_blsp_i2c7 = 9,\n\tmsm_mux_blsp_i2c8 = 10,\n\tmsm_mux_blsp_i2c9 = 11,\n\tmsm_mux_blsp_i2c10 = 12,\n\tmsm_mux_blsp_i2c11 = 13,\n\tmsm_mux_blsp_i2c12 = 14,\n\tmsm_mux_blsp_spi1___2 = 15,\n\tmsm_mux_blsp_spi1_cs1___2 = 16,\n\tmsm_mux_blsp_spi1_cs2___2 = 17,\n\tmsm_mux_blsp_spi1_cs3___2 = 18,\n\tmsm_mux_blsp_spi2___2 = 19,\n\tmsm_mux_blsp_spi2_cs1___2 = 20,\n\tmsm_mux_blsp_spi2_cs2___2 = 21,\n\tmsm_mux_blsp_spi2_cs3___2 = 22,\n\tmsm_mux_blsp_spi3___2 = 23,\n\tmsm_mux_blsp_spi4___2 = 24,\n\tmsm_mux_blsp_spi5___2 = 25,\n\tmsm_mux_blsp_spi6___2 = 26,\n\tmsm_mux_blsp_spi7 = 27,\n\tmsm_mux_blsp_spi8 = 28,\n\tmsm_mux_blsp_spi9 = 29,\n\tmsm_mux_blsp_spi10 = 30,\n\tmsm_mux_blsp_spi10_cs1 = 31,\n\tmsm_mux_blsp_spi10_cs2 = 32,\n\tmsm_mux_blsp_spi10_cs3 = 33,\n\tmsm_mux_blsp_spi11 = 34,\n\tmsm_mux_blsp_spi12 = 35,\n\tmsm_mux_blsp_uart1___2 = 36,\n\tmsm_mux_blsp_uart2___2 = 37,\n\tmsm_mux_blsp_uart3 = 38,\n\tmsm_mux_blsp_uart4 = 39,\n\tmsm_mux_blsp_uart5 = 40,\n\tmsm_mux_blsp_uart6 = 41,\n\tmsm_mux_blsp_uart7 = 42,\n\tmsm_mux_blsp_uart8 = 43,\n\tmsm_mux_blsp_uart9 = 44,\n\tmsm_mux_blsp_uart10 = 45,\n\tmsm_mux_blsp_uart11 = 46,\n\tmsm_mux_blsp_uart12 = 47,\n\tmsm_mux_blsp_uim1___2 = 48,\n\tmsm_mux_blsp_uim2___2 = 49,\n\tmsm_mux_blsp_uim3 = 50,\n\tmsm_mux_blsp_uim4 = 51,\n\tmsm_mux_blsp_uim5 = 52,\n\tmsm_mux_blsp_uim6 = 53,\n\tmsm_mux_blsp_uim7 = 54,\n\tmsm_mux_blsp_uim8 = 55,\n\tmsm_mux_blsp_uim9 = 56,\n\tmsm_mux_blsp_uim10 = 57,\n\tmsm_mux_blsp_uim11 = 58,\n\tmsm_mux_blsp_uim12 = 59,\n\tmsm_mux_uim1___2 = 60,\n\tmsm_mux_uim2___2 = 61,\n\tmsm_mux_uim_batt_alarm = 62,\n\tmsm_mux_sdc3 = 63,\n\tmsm_mux_sdc4___2 = 64,\n\tmsm_mux_gcc_gp_clk1 = 65,\n\tmsm_mux_gcc_gp_clk2 = 66,\n\tmsm_mux_gcc_gp_clk3 = 67,\n\tmsm_mux_qua_mi2s = 68,\n\tmsm_mux_pri_mi2s___2 = 69,\n\tmsm_mux_spkr_mi2s = 70,\n\tmsm_mux_ter_mi2s = 71,\n\tmsm_mux_sec_mi2s___2 = 72,\n\tmsm_mux_hdmi_cec___2 = 73,\n\tmsm_mux_hdmi_ddc = 74,\n\tmsm_mux_hdmi_hpd = 75,\n\tmsm_mux_edp_hpd = 76,\n\tmsm_mux_mdp_vsync___4 = 77,\n\tmsm_mux_cam_mclk0___3 = 78,\n\tmsm_mux_cam_mclk1___3 = 79,\n\tmsm_mux_cam_mclk2___2 = 80,\n\tmsm_mux_cam_mclk3 = 81,\n\tmsm_mux_cci_timer0___2 = 82,\n\tmsm_mux_cci_timer1___2 = 83,\n\tmsm_mux_cci_timer2___2 = 84,\n\tmsm_mux_cci_timer3 = 85,\n\tmsm_mux_cci_timer4 = 86,\n\tmsm_mux_cci_async_in0 = 87,\n\tmsm_mux_cci_async_in1 = 88,\n\tmsm_mux_cci_async_in2 = 89,\n\tmsm_mux_gp_pdm0 = 90,\n\tmsm_mux_gp_pdm1 = 91,\n\tmsm_mux_gp_pdm2 = 92,\n\tmsm_mux_gp0_clk = 93,\n\tmsm_mux_gp1_clk = 94,\n\tmsm_mux_gp_mn___3 = 95,\n\tmsm_mux_tsif1___3 = 96,\n\tmsm_mux_tsif2___3 = 97,\n\tmsm_mux_hsic___2 = 98,\n\tmsm_mux_grfc = 99,\n\tmsm_mux_audio_ref_clk = 100,\n\tmsm_mux_bt___2 = 101,\n\tmsm_mux_fm___2 = 102,\n\tmsm_mux_wlan___2 = 103,\n\tmsm_mux_slimbus = 104,\n\tmsm_mux_hsic_ctl = 105,\n\tmsm_mux_NA___3 = 106,\n};\n\nenum mtd_file_modes {\n\tMTD_FILE_MODE_NORMAL = 0,\n\tMTD_FILE_MODE_OTP_FACTORY = 1,\n\tMTD_FILE_MODE_OTP_USER = 2,\n\tMTD_FILE_MODE_RAW = 3,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum mtk_cirq_regoffs_index {\n\tCIRQ_STA = 0,\n\tCIRQ_ACK = 1,\n\tCIRQ_MASK_SET = 2,\n\tCIRQ_MASK_CLR = 3,\n\tCIRQ_SENS_SET = 4,\n\tCIRQ_SENS_CLR = 5,\n\tCIRQ_POL_SET = 6,\n\tCIRQ_POL_CLR = 7,\n\tCIRQ_CONTROL = 8,\n};\n\nenum mtk_ddp_comp_id {\n\tDDP_COMPONENT_AAL0 = 0,\n\tDDP_COMPONENT_AAL1 = 1,\n\tDDP_COMPONENT_BLS = 2,\n\tDDP_COMPONENT_CCORR = 3,\n\tDDP_COMPONENT_COLOR0 = 4,\n\tDDP_COMPONENT_COLOR1 = 5,\n\tDDP_COMPONENT_DITHER0 = 6,\n\tDDP_COMPONENT_DITHER1 = 7,\n\tDDP_COMPONENT_DP_INTF0 = 8,\n\tDDP_COMPONENT_DP_INTF1 = 9,\n\tDDP_COMPONENT_DPI0 = 10,\n\tDDP_COMPONENT_DPI1 = 11,\n\tDDP_COMPONENT_DSC0 = 12,\n\tDDP_COMPONENT_DSC1 = 13,\n\tDDP_COMPONENT_DSI0 = 14,\n\tDDP_COMPONENT_DSI1 = 15,\n\tDDP_COMPONENT_DSI2 = 16,\n\tDDP_COMPONENT_DSI3 = 17,\n\tDDP_COMPONENT_ETHDR_MIXER = 18,\n\tDDP_COMPONENT_GAMMA = 19,\n\tDDP_COMPONENT_MDP_RDMA0 = 20,\n\tDDP_COMPONENT_MDP_RDMA1 = 21,\n\tDDP_COMPONENT_MDP_RDMA2 = 22,\n\tDDP_COMPONENT_MDP_RDMA3 = 23,\n\tDDP_COMPONENT_MDP_RDMA4 = 24,\n\tDDP_COMPONENT_MDP_RDMA5 = 25,\n\tDDP_COMPONENT_MDP_RDMA6 = 26,\n\tDDP_COMPONENT_MDP_RDMA7 = 27,\n\tDDP_COMPONENT_MERGE0 = 28,\n\tDDP_COMPONENT_MERGE1 = 29,\n\tDDP_COMPONENT_MERGE2 = 30,\n\tDDP_COMPONENT_MERGE3 = 31,\n\tDDP_COMPONENT_MERGE4 = 32,\n\tDDP_COMPONENT_MERGE5 = 33,\n\tDDP_COMPONENT_OD0 = 34,\n\tDDP_COMPONENT_OD1 = 35,\n\tDDP_COMPONENT_OVL0 = 36,\n\tDDP_COMPONENT_OVL_2L0 = 37,\n\tDDP_COMPONENT_OVL_2L1 = 38,\n\tDDP_COMPONENT_OVL_2L2 = 39,\n\tDDP_COMPONENT_OVL1 = 40,\n\tDDP_COMPONENT_PADDING0 = 41,\n\tDDP_COMPONENT_PADDING1 = 42,\n\tDDP_COMPONENT_PADDING2 = 43,\n\tDDP_COMPONENT_PADDING3 = 44,\n\tDDP_COMPONENT_PADDING4 = 45,\n\tDDP_COMPONENT_PADDING5 = 46,\n\tDDP_COMPONENT_PADDING6 = 47,\n\tDDP_COMPONENT_PADDING7 = 48,\n\tDDP_COMPONENT_POSTMASK0 = 49,\n\tDDP_COMPONENT_PWM0 = 50,\n\tDDP_COMPONENT_PWM1 = 51,\n\tDDP_COMPONENT_PWM2 = 52,\n\tDDP_COMPONENT_RDMA0 = 53,\n\tDDP_COMPONENT_RDMA1 = 54,\n\tDDP_COMPONENT_RDMA2 = 55,\n\tDDP_COMPONENT_RDMA4 = 56,\n\tDDP_COMPONENT_UFOE = 57,\n\tDDP_COMPONENT_WDMA0 = 58,\n\tDDP_COMPONENT_WDMA1 = 59,\n\tDDP_COMPONENT_ID_MAX = 60,\n};\n\nenum mtk_dpi_out_format_con {\n\tMTK_DPI_RGB888_SDR_CON = 0,\n\tMTK_DPI_RGB888_DDR_CON = 1,\n\tMTK_DPI_RGB565_SDR_CON = 2,\n\tMTK_DPI_RGB565_DDR_CON = 3,\n};\n\nenum mtk_mfg_ipi_cmd {\n\tCMD_INIT_SHARED_MEM = 0,\n\tCMD_GET_FREQ_BY_IDX = 1,\n\tCMD_GET_POWER_BY_IDX = 2,\n\tCMD_GET_OPPIDX_BY_FREQ = 3,\n\tCMD_GET_LEAKAGE_POWER = 4,\n\tCMD_SET_LIMIT = 5,\n\tCMD_POWER_CONTROL = 6,\n\tCMD_ACTIVE_SLEEP_CONTROL = 7,\n\tCMD_COMMIT = 8,\n\tCMD_DUAL_COMMIT = 9,\n\tCMD_PDCA_CONFIG = 10,\n\tCMD_UPDATE_DEBUG_OPP_INFO = 11,\n\tCMD_SWITCH_LIMIT = 12,\n\tCMD_FIX_TARGET_OPPIDX = 13,\n\tCMD_FIX_DUAL_TARGET_OPPIDX = 14,\n\tCMD_FIX_CUSTOM_FREQ_VOLT = 15,\n\tCMD_FIX_DUAL_CUSTOM_FREQ_VOLT = 16,\n\tCMD_SET_MFGSYS_CONFIG = 17,\n\tCMD_MSSV_COMMIT = 18,\n\tCMD_NUM = 19,\n};\n\nenum mtk_mutex_mod_index {\n\tMUTEX_MOD_IDX_MDP_RDMA0 = 0,\n\tMUTEX_MOD_IDX_MDP_RSZ0 = 1,\n\tMUTEX_MOD_IDX_MDP_RSZ1 = 2,\n\tMUTEX_MOD_IDX_MDP_TDSHP0 = 3,\n\tMUTEX_MOD_IDX_MDP_WROT0 = 4,\n\tMUTEX_MOD_IDX_MDP_WDMA = 5,\n\tMUTEX_MOD_IDX_MDP_AAL0 = 6,\n\tMUTEX_MOD_IDX_MDP_CCORR0 = 7,\n\tMUTEX_MOD_IDX_MDP_HDR0 = 8,\n\tMUTEX_MOD_IDX_MDP_COLOR0 = 9,\n\tMUTEX_MOD_IDX_MDP_RDMA1 = 10,\n\tMUTEX_MOD_IDX_MDP_RDMA2 = 11,\n\tMUTEX_MOD_IDX_MDP_RDMA3 = 12,\n\tMUTEX_MOD_IDX_MDP_STITCH0 = 13,\n\tMUTEX_MOD_IDX_MDP_FG0 = 14,\n\tMUTEX_MOD_IDX_MDP_FG1 = 15,\n\tMUTEX_MOD_IDX_MDP_FG2 = 16,\n\tMUTEX_MOD_IDX_MDP_FG3 = 17,\n\tMUTEX_MOD_IDX_MDP_HDR1 = 18,\n\tMUTEX_MOD_IDX_MDP_HDR2 = 19,\n\tMUTEX_MOD_IDX_MDP_HDR3 = 20,\n\tMUTEX_MOD_IDX_MDP_AAL1 = 21,\n\tMUTEX_MOD_IDX_MDP_AAL2 = 22,\n\tMUTEX_MOD_IDX_MDP_AAL3 = 23,\n\tMUTEX_MOD_IDX_MDP_RSZ2 = 24,\n\tMUTEX_MOD_IDX_MDP_RSZ3 = 25,\n\tMUTEX_MOD_IDX_MDP_MERGE2 = 26,\n\tMUTEX_MOD_IDX_MDP_MERGE3 = 27,\n\tMUTEX_MOD_IDX_MDP_TDSHP1 = 28,\n\tMUTEX_MOD_IDX_MDP_TDSHP2 = 29,\n\tMUTEX_MOD_IDX_MDP_TDSHP3 = 30,\n\tMUTEX_MOD_IDX_MDP_COLOR1 = 31,\n\tMUTEX_MOD_IDX_MDP_COLOR2 = 32,\n\tMUTEX_MOD_IDX_MDP_COLOR3 = 33,\n\tMUTEX_MOD_IDX_MDP_OVL0 = 34,\n\tMUTEX_MOD_IDX_MDP_OVL1 = 35,\n\tMUTEX_MOD_IDX_MDP_PAD0 = 36,\n\tMUTEX_MOD_IDX_MDP_PAD1 = 37,\n\tMUTEX_MOD_IDX_MDP_PAD2 = 38,\n\tMUTEX_MOD_IDX_MDP_PAD3 = 39,\n\tMUTEX_MOD_IDX_MDP_TCC0 = 40,\n\tMUTEX_MOD_IDX_MDP_TCC1 = 41,\n\tMUTEX_MOD_IDX_MDP_WROT1 = 42,\n\tMUTEX_MOD_IDX_MDP_WROT2 = 43,\n\tMUTEX_MOD_IDX_MDP_WROT3 = 44,\n\tMUTEX_MOD_IDX_MAX = 45,\n};\n\nenum mtk_mutex_sof_id {\n\tMUTEX_SOF_SINGLE_MODE = 0,\n\tMUTEX_SOF_DSI0 = 1,\n\tMUTEX_SOF_DSI1 = 2,\n\tMUTEX_SOF_DPI0 = 3,\n\tMUTEX_SOF_DPI1 = 4,\n\tMUTEX_SOF_DSI2 = 5,\n\tMUTEX_SOF_DSI3 = 6,\n\tMUTEX_SOF_DP_INTF0 = 7,\n\tMUTEX_SOF_DP_INTF1 = 8,\n\tDDP_MUTEX_SOF_MAX = 9,\n};\n\nenum mtk_mutex_sof_index {\n\tMUTEX_SOF_IDX_SINGLE_MODE = 0,\n\tMUTEX_SOF_IDX_MAX = 1,\n};\n\nenum mtk_reset_version {\n\tMTK_RST_SIMPLE = 0,\n\tMTK_RST_SET_CLR = 1,\n\tMTK_RST_MAX = 2,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum mux_first_reg {\n\tmux_f_mux = 0,\n\tmux_f_gpio = 1,\n\tmux_f_keep = 2,\n};\n\nenum mux_master_reg {\n\tmux_m_iop = 0,\n\tmux_m_gpio = 1,\n\tmux_m_keep = 2,\n};\n\nenum muxtype {\n\tpca954x_ismux = 0,\n\tpca954x_isswi = 1,\n};\n\nenum mv_xor_mode {\n\tXOR_MODE_IN_REG = 0,\n\tXOR_MODE_IN_DESC = 1,\n};\n\nenum mv_xor_type {\n\tXOR_ORION = 0,\n\tXOR_ARMADA_38X = 1,\n\tXOR_ARMADA_37XX = 2,\n};\n\nenum mvneta_bm_type {\n\tMVNETA_BM_FREE = 0,\n\tMVNETA_BM_LONG = 1,\n\tMVNETA_BM_SHORT = 2,\n};\n\nenum mvneta_tx_buf_type {\n\tMVNETA_TYPE_TSO = 0,\n\tMVNETA_TYPE_SKB = 1,\n\tMVNETA_TYPE_XDP_TX = 2,\n\tMVNETA_TYPE_XDP_NDO = 3,\n};\n\nenum mxc_cpu_pwr_mode {\n\tWAIT_CLOCKED = 0,\n\tWAIT_UNCLOCKED = 1,\n\tWAIT_UNCLOCKED_POWER_OFF = 2,\n\tSTOP_POWER_ON = 3,\n\tSTOP_POWER_OFF = 4,\n};\n\nenum mxs_dma_devtype {\n\tMXS_DMA_APBH = 0,\n\tMXS_DMA_APBX = 1,\n};\n\nenum mxs_dma_id {\n\tIMX23_DMA = 0,\n\tIMX28_DMA = 1,\n};\n\nenum nand_bbt_block_status {\n\tNAND_BBT_BLOCK_STATUS_UNKNOWN = 0,\n\tNAND_BBT_BLOCK_GOOD = 1,\n\tNAND_BBT_BLOCK_WORN = 2,\n\tNAND_BBT_BLOCK_RESERVED = 3,\n\tNAND_BBT_BLOCK_FACTORY_BAD = 4,\n\tNAND_BBT_BLOCK_NUM_STATUS = 5,\n};\n\nenum nand_ecc_algo {\n\tNAND_ECC_ALGO_UNKNOWN = 0,\n\tNAND_ECC_ALGO_HAMMING = 1,\n\tNAND_ECC_ALGO_BCH = 2,\n\tNAND_ECC_ALGO_RS = 3,\n};\n\nenum nand_ecc_engine_integration {\n\tNAND_ECC_ENGINE_INTEGRATION_INVALID = 0,\n\tNAND_ECC_ENGINE_INTEGRATION_PIPELINED = 1,\n\tNAND_ECC_ENGINE_INTEGRATION_EXTERNAL = 2,\n};\n\nenum nand_ecc_engine_type {\n\tNAND_ECC_ENGINE_TYPE_INVALID = 0,\n\tNAND_ECC_ENGINE_TYPE_NONE = 1,\n\tNAND_ECC_ENGINE_TYPE_SOFT = 2,\n\tNAND_ECC_ENGINE_TYPE_ON_HOST = 3,\n\tNAND_ECC_ENGINE_TYPE_ON_DIE = 4,\n};\n\nenum nand_ecc_legacy_mode {\n\tNAND_ECC_INVALID = 0,\n\tNAND_ECC_NONE = 1,\n\tNAND_ECC_SOFT = 2,\n\tNAND_ECC_SOFT_BCH = 3,\n\tNAND_ECC_HW = 4,\n\tNAND_ECC_HW_SYNDROME = 5,\n\tNAND_ECC_ON_DIE = 6,\n};\n\nenum nand_ecc_placement {\n\tNAND_ECC_PLACEMENT_UNKNOWN = 0,\n\tNAND_ECC_PLACEMENT_OOB = 1,\n\tNAND_ECC_PLACEMENT_INTERLEAVED = 2,\n};\n\nenum nand_interface_type {\n\tNAND_SDR_IFACE = 0,\n\tNAND_NVDDR_IFACE = 1,\n};\n\nenum nand_io {\n\tNAND_OMAP_PREFETCH_POLLED = 0,\n\tNAND_OMAP_POLLED = 1,\n\tNAND_OMAP_PREFETCH_DMA = 2,\n\tNAND_OMAP_PREFETCH_IRQ = 3,\n};\n\nenum nand_op_instr_type {\n\tNAND_OP_CMD_INSTR = 0,\n\tNAND_OP_ADDR_INSTR = 1,\n\tNAND_OP_DATA_IN_INSTR = 2,\n\tNAND_OP_DATA_OUT_INSTR = 3,\n\tNAND_OP_WAITRDY_INSTR = 4,\n};\n\nenum nand_page_io_req_type {\n\tNAND_PAGE_READ = 0,\n\tNAND_PAGE_WRITE = 1,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum netcp_addr_type {\n\tADDR_ANY = 0,\n\tADDR_DEV = 1,\n\tADDR_UCAST = 2,\n\tADDR_MCAST = 3,\n\tADDR_BCAST = 4,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_lag_hash {\n\tNETDEV_LAG_HASH_NONE = 0,\n\tNETDEV_LAG_HASH_L2 = 1,\n\tNETDEV_LAG_HASH_L34 = 2,\n\tNETDEV_LAG_HASH_L23 = 3,\n\tNETDEV_LAG_HASH_E23 = 4,\n\tNETDEV_LAG_HASH_E34 = 5,\n\tNETDEV_LAG_HASH_VLAN_SRCMAC = 6,\n\tNETDEV_LAG_HASH_UNKNOWN = 7,\n};\n\nenum netdev_lag_tx_type {\n\tNETDEV_LAG_TX_TYPE_UNKNOWN = 0,\n\tNETDEV_LAG_TX_TYPE_RANDOM = 1,\n\tNETDEV_LAG_TX_TYPE_BROADCAST = 2,\n\tNETDEV_LAG_TX_TYPE_ROUNDROBIN = 3,\n\tNETDEV_LAG_TX_TYPE_ACTIVEBACKUP = 4,\n\tNETDEV_LAG_TX_TYPE_HASH = 5,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netloc_type4 {\n\tNL4_NAME = 1,\n\tNL4_URL = 2,\n\tNL4_NETADDR = 3,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nfs3_createmode {\n\tNFS3_CREATE_UNCHECKED = 0,\n\tNFS3_CREATE_GUARDED = 1,\n\tNFS3_CREATE_EXCLUSIVE = 2,\n};\n\nenum nfs3_ftype {\n\tNF3NON = 0,\n\tNF3REG = 1,\n\tNF3DIR = 2,\n\tNF3BLK = 3,\n\tNF3CHR = 4,\n\tNF3LNK = 5,\n\tNF3SOCK = 6,\n\tNF3FIFO = 7,\n\tNF3BAD = 8,\n};\n\nenum nfs3_stable_how {\n\tNFS_UNSTABLE = 0,\n\tNFS_DATA_SYNC = 1,\n\tNFS_FILE_SYNC = 2,\n\tNFS_INVALID_STABLE_HOW = -1,\n};\n\nenum nfs4_acl_type {\n\tNFS4ACL_NONE = 0,\n\tNFS4ACL_ACL = 1,\n\tNFS4ACL_DACL = 2,\n\tNFS4ACL_SACL = 3,\n};\n\nenum nfs4_callback_procnum {\n\tCB_NULL = 0,\n\tCB_COMPOUND = 1,\n};\n\nenum nfs4_change_attr_type {\n\tNFS4_CHANGE_TYPE_IS_MONOTONIC_INCR = 0,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER = 1,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER_NOPNFS = 2,\n\tNFS4_CHANGE_TYPE_IS_TIME_METADATA = 3,\n\tNFS4_CHANGE_TYPE_IS_UNDEFINED = 4,\n};\n\nenum nfs4_client_state {\n\tNFS4CLNT_MANAGER_RUNNING = 0,\n\tNFS4CLNT_CHECK_LEASE = 1,\n\tNFS4CLNT_LEASE_EXPIRED = 2,\n\tNFS4CLNT_RECLAIM_REBOOT = 3,\n\tNFS4CLNT_RECLAIM_NOGRACE = 4,\n\tNFS4CLNT_DELEGRETURN = 5,\n\tNFS4CLNT_SESSION_RESET = 6,\n\tNFS4CLNT_LEASE_CONFIRM = 7,\n\tNFS4CLNT_SERVER_SCOPE_MISMATCH = 8,\n\tNFS4CLNT_PURGE_STATE = 9,\n\tNFS4CLNT_BIND_CONN_TO_SESSION = 10,\n\tNFS4CLNT_MOVED = 11,\n\tNFS4CLNT_LEASE_MOVED = 12,\n\tNFS4CLNT_DELEGATION_EXPIRED = 13,\n\tNFS4CLNT_RUN_MANAGER = 14,\n\tNFS4CLNT_MANAGER_AVAILABLE = 15,\n\tNFS4CLNT_RECALL_RUNNING = 16,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_READ = 17,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_RW = 18,\n\tNFS4CLNT_DELEGRETURN_DELAYED = 19,\n};\n\nenum nfs4_ff_op_type {\n\tNFS4_FF_OP_LAYOUTSTATS = 0,\n\tNFS4_FF_OP_LAYOUTRETURN = 1,\n};\n\nenum nfs4_open_delegation_type4 {\n\tNFS4_OPEN_DELEGATE_NONE = 0,\n\tNFS4_OPEN_DELEGATE_READ = 1,\n\tNFS4_OPEN_DELEGATE_WRITE = 2,\n\tNFS4_OPEN_DELEGATE_NONE_EXT = 3,\n\tNFS4_OPEN_DELEGATE_READ_ATTRS_DELEG = 4,\n\tNFS4_OPEN_DELEGATE_WRITE_ATTRS_DELEG = 5,\n};\n\nenum nfs4_session_state {\n\tNFS4_SESSION_INITING = 0,\n\tNFS4_SESSION_ESTABLISHED = 1,\n};\n\nenum nfs4_setxattr_options {\n\tSETXATTR4_EITHER = 0,\n\tSETXATTR4_CREATE = 1,\n\tSETXATTR4_REPLACE = 2,\n};\n\nenum nfs4_slot_tbl_state {\n\tNFS4_SLOT_TBL_DRAINING = 0,\n};\n\nenum nfs_cb_opnum4 {\n\tOP_CB_GETATTR = 3,\n\tOP_CB_RECALL = 4,\n\tOP_CB_LAYOUTRECALL = 5,\n\tOP_CB_NOTIFY = 6,\n\tOP_CB_PUSH_DELEG = 7,\n\tOP_CB_RECALL_ANY = 8,\n\tOP_CB_RECALLABLE_OBJ_AVAIL = 9,\n\tOP_CB_RECALL_SLOT = 10,\n\tOP_CB_SEQUENCE = 11,\n\tOP_CB_WANTS_CANCELLED = 12,\n\tOP_CB_NOTIFY_LOCK = 13,\n\tOP_CB_NOTIFY_DEVICEID = 14,\n\tOP_CB_OFFLOAD = 15,\n\tOP_CB_ILLEGAL = 10044,\n};\n\nenum nfs_ftype4 {\n\tNF4BAD = 0,\n\tNF4REG = 1,\n\tNF4DIR = 2,\n\tNF4BLK = 3,\n\tNF4CHR = 4,\n\tNF4LNK = 5,\n\tNF4SOCK = 6,\n\tNF4FIFO = 7,\n\tNF4ATTRDIR = 8,\n\tNF4NAMEDATTR = 9,\n};\n\nenum nfs_lock_status {\n\tNFS_LOCK_NOT_SET = 0,\n\tNFS_LOCK_LOCK = 1,\n\tNFS_LOCK_NOLOCK = 2,\n};\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nfs_param {\n\tOpt_ac = 0,\n\tOpt_acdirmax = 1,\n\tOpt_acdirmin = 2,\n\tOpt_acl___3 = 3,\n\tOpt_acregmax = 4,\n\tOpt_acregmin = 5,\n\tOpt_actimeo = 6,\n\tOpt_addr = 7,\n\tOpt_bg = 8,\n\tOpt_bsize = 9,\n\tOpt_clientaddr = 10,\n\tOpt_cto = 11,\n\tOpt_alignwrite = 12,\n\tOpt_fatal_neterrors = 13,\n\tOpt_fg = 14,\n\tOpt_fscache = 15,\n\tOpt_fscache_flag = 16,\n\tOpt_hard = 17,\n\tOpt_intr = 18,\n\tOpt_local_lock = 19,\n\tOpt_lock = 20,\n\tOpt_lookupcache = 21,\n\tOpt_migration = 22,\n\tOpt_minorversion = 23,\n\tOpt_mountaddr = 24,\n\tOpt_mounthost = 25,\n\tOpt_mountport = 26,\n\tOpt_mountproto = 27,\n\tOpt_mountvers = 28,\n\tOpt_namelen = 29,\n\tOpt_nconnect = 30,\n\tOpt_max_connect = 31,\n\tOpt_port = 32,\n\tOpt_posix = 33,\n\tOpt_proto = 34,\n\tOpt_rdirplus = 35,\n\tOpt_rdirplus_none = 36,\n\tOpt_rdirplus_force = 37,\n\tOpt_rdma = 38,\n\tOpt_resvport = 39,\n\tOpt_retrans = 40,\n\tOpt_retry = 41,\n\tOpt_rsize = 42,\n\tOpt_sec = 43,\n\tOpt_sharecache = 44,\n\tOpt_sloppy = 45,\n\tOpt_soft = 46,\n\tOpt_softerr = 47,\n\tOpt_softreval = 48,\n\tOpt_source___2 = 49,\n\tOpt_tcp = 50,\n\tOpt_timeo = 51,\n\tOpt_trunkdiscovery = 52,\n\tOpt_udp = 53,\n\tOpt_v = 54,\n\tOpt_vers = 55,\n\tOpt_wsize = 56,\n\tOpt_write = 57,\n\tOpt_xprtsec = 58,\n\tOpt_cert_serial = 59,\n\tOpt_privkey_serial = 60,\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nenum nfs_stat_bytecounters {\n\tNFSIOS_NORMALREADBYTES = 0,\n\tNFSIOS_NORMALWRITTENBYTES = 1,\n\tNFSIOS_DIRECTREADBYTES = 2,\n\tNFSIOS_DIRECTWRITTENBYTES = 3,\n\tNFSIOS_SERVERREADBYTES = 4,\n\tNFSIOS_SERVERWRITTENBYTES = 5,\n\tNFSIOS_READPAGES = 6,\n\tNFSIOS_WRITEPAGES = 7,\n\t__NFSIOS_BYTESMAX = 8,\n};\n\nenum nfs_stat_eventcounters {\n\tNFSIOS_INODEREVALIDATE = 0,\n\tNFSIOS_DENTRYREVALIDATE = 1,\n\tNFSIOS_DATAINVALIDATE = 2,\n\tNFSIOS_ATTRINVALIDATE = 3,\n\tNFSIOS_VFSOPEN = 4,\n\tNFSIOS_VFSLOOKUP = 5,\n\tNFSIOS_VFSACCESS = 6,\n\tNFSIOS_VFSUPDATEPAGE = 7,\n\tNFSIOS_VFSREADPAGE = 8,\n\tNFSIOS_VFSREADPAGES = 9,\n\tNFSIOS_VFSWRITEPAGE = 10,\n\tNFSIOS_VFSWRITEPAGES = 11,\n\tNFSIOS_VFSGETDENTS = 12,\n\tNFSIOS_VFSSETATTR = 13,\n\tNFSIOS_VFSFLUSH = 14,\n\tNFSIOS_VFSFSYNC = 15,\n\tNFSIOS_VFSLOCK = 16,\n\tNFSIOS_VFSRELEASE = 17,\n\tNFSIOS_CONGESTIONWAIT = 18,\n\tNFSIOS_SETATTRTRUNC = 19,\n\tNFSIOS_EXTENDWRITE = 20,\n\tNFSIOS_SILLYRENAME = 21,\n\tNFSIOS_SHORTREAD = 22,\n\tNFSIOS_SHORTWRITE = 23,\n\tNFSIOS_DELAY = 24,\n\tNFSIOS_PNFS_READ = 25,\n\tNFSIOS_PNFS_WRITE = 26,\n\t__NFSIOS_COUNTSMAX = 27,\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n\tNFS4ERR_NOXATTR = 10095,\n\tNFS4ERR_XATTR2BIG = 10096,\n\tNFS4ERR_FIRST_FREE = 10097,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum nmk_gpio_irq_type {\n\tNORMAL = 0,\n\tWAKE = 1,\n};\n\nenum nmk_gpio_pull {\n\tNMK_GPIO_PULL_NONE = 0,\n\tNMK_GPIO_PULL_UP = 1,\n\tNMK_GPIO_PULL_DOWN = 2,\n};\n\nenum nmk_gpio_slpm {\n\tNMK_GPIO_SLPM_INPUT = 0,\n\tNMK_GPIO_SLPM_WAKEUP_ENABLE = 0,\n\tNMK_GPIO_SLPM_NOCHANGE = 1,\n\tNMK_GPIO_SLPM_WAKEUP_DISABLE = 1,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_IOMMU_PAGES = 39,\n\tNR_SWAPCACHE = 40,\n\tPGDEMOTE_KSWAPD = 41,\n\tPGDEMOTE_DIRECT = 42,\n\tPGDEMOTE_KHUGEPAGED = 43,\n\tPGDEMOTE_PROACTIVE = 44,\n\tNR_BALLOON_PAGES = 45,\n\tNR_KERNEL_FILE_PAGES = 46,\n\tNR_VM_NODE_STAT_ITEMS = 47,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 3,\n\tN_MEMORY = 4,\n\tN_CPU = 5,\n\tN_GENERIC_INITIATOR = 6,\n\tNR_NODE_STATES = 7,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns2_led_modes {\n\tNS_V2_LED_OFF = 0,\n\tNS_V2_LED_ON = 1,\n\tNS_V2_LED_SATA = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum nvec_event_size {\n\tNVEC_2BYTES = 0,\n\tNVEC_3BYTES = 1,\n\tNVEC_VAR_SIZE = 2,\n};\n\nenum nvec_msg_category {\n\tNVEC_MSG_RX = 0,\n\tNVEC_MSG_TX = 1,\n};\n\nenum nvec_msg_type {\n\tNVEC_SYS = 1,\n\tNVEC_BAT = 2,\n\tNVEC_GPIO = 3,\n\tNVEC_SLEEP = 4,\n\tNVEC_KBD = 5,\n\tNVEC_PS2 = 6,\n\tNVEC_CNTL = 7,\n\tNVEC_OEM0 = 13,\n\tNVEC_KB_EVT = 128,\n\tNVEC_PS2_EVT = 129,\n};\n\nenum nvec_sleep_subcmds {\n\tGLOBAL_EVENTS = 0,\n\tAP_PWR_DOWN = 1,\n\tAP_SUSPEND = 2,\n};\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n\tNVMEM_TYPE_FRAM = 4,\n};\n\nenum oatc14_hdd_status {\n\tOATC14_HDD_STATUS_CABLE_OK = 0,\n\tOATC14_HDD_STATUS_OPEN = 1,\n\tOATC14_HDD_STATUS_SHORT = 2,\n\tOATC14_HDD_STATUS_NOT_DETECTABLE = 3,\n};\n\nenum of_gpio_flags {\n\tOF_GPIO_ACTIVE_LOW = 1,\n\tOF_GPIO_SINGLE_ENDED = 2,\n\tOF_GPIO_OPEN_DRAIN = 4,\n\tOF_GPIO_TRANSITORY = 8,\n\tOF_GPIO_PULL_UP = 16,\n\tOF_GPIO_PULL_DOWN = 32,\n\tOF_GPIO_PULL_DISABLE = 64,\n};\n\nenum of_reconfig_change {\n\tOF_RECONFIG_NO_CHANGE = 0,\n\tOF_RECONFIG_CHANGE_ADD = 1,\n\tOF_RECONFIG_CHANGE_REMOVE = 2,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum ohci_rh_state {\n\tOHCI_RH_HALTED = 0,\n\tOHCI_RH_SUSPENDED = 1,\n\tOHCI_RH_RUNNING = 2,\n};\n\nenum omap3_l3_code {\n\tOMAP_L3_CODE_NOERROR = 0,\n\tOMAP_L3_CODE_UNSUP_CMD = 1,\n\tOMAP_L3_CODE_ADDR_HOLE = 2,\n\tOMAP_L3_CODE_PROTECT_VIOLATION = 3,\n\tOMAP_L3_CODE_IN_BAND_ERR = 4,\n\tOMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,\n\tOMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,\n};\n\nenum omap3_l3_initiator_id {\n\tOMAP_L3_LCD = 29,\n\tOMAP_L3_SAD2D = 28,\n\tOMAP_L3_IA_MPU_SS_1 = 27,\n\tOMAP_L3_IA_MPU_SS_2 = 26,\n\tOMAP_L3_IA_MPU_SS_3 = 25,\n\tOMAP_L3_IA_MPU_SS_4 = 24,\n\tOMAP_L3_IA_MPU_SS_5 = 23,\n\tOMAP_L3_IA_IVA_SS_1 = 22,\n\tOMAP_L3_IA_IVA_SS_2 = 21,\n\tOMAP_L3_IA_IVA_SS_3 = 20,\n\tOMAP_L3_IA_IVA_SS_DMA_1 = 19,\n\tOMAP_L3_IA_IVA_SS_DMA_2 = 18,\n\tOMAP_L3_IA_IVA_SS_DMA_3 = 17,\n\tOMAP_L3_IA_IVA_SS_DMA_4 = 16,\n\tOMAP_L3_IA_IVA_SS_DMA_5 = 15,\n\tOMAP_L3_IA_IVA_SS_DMA_6 = 14,\n\tOMAP_L3_IA_SGX = 13,\n\tOMAP_L3_IA_CAM_1 = 12,\n\tOMAP_L3_IA_CAM_2 = 11,\n\tOMAP_L3_IA_CAM_3 = 10,\n\tOMAP_L3_IA_DAP = 9,\n\tOMAP_L3_SDMA_WR_1 = 8,\n\tOMAP_L3_SDMA_WR_2 = 7,\n\tOMAP_L3_SDMA_RD_1 = 6,\n\tOMAP_L3_SDMA_RD_2 = 5,\n\tOMAP_L3_SDMA_RD_3 = 4,\n\tOMAP_L3_SDMA_RD_4 = 3,\n\tOMAP_L3_USBOTG = 2,\n\tOMAP_L3_USBHOST = 1,\n};\n\nenum omap_control_phy_type {\n\tOMAP_CTRL_TYPE_OTGHS = 1,\n\tOMAP_CTRL_TYPE_USB2 = 2,\n\tOMAP_CTRL_TYPE_PIPE3 = 3,\n\tOMAP_CTRL_TYPE_PCIE = 4,\n\tOMAP_CTRL_TYPE_DRA7USB2 = 5,\n\tOMAP_CTRL_TYPE_AM437USB2 = 6,\n};\n\nenum omap_control_usb_mode {\n\tUSB_MODE_UNDEFINED = 0,\n\tUSB_MODE_HOST = 1,\n\tUSB_MODE_DEVICE = 2,\n\tUSB_MODE_DISCONNECT = 3,\n};\n\nenum omap_dwc3_vbus_id_status {\n\tOMAP_DWC3_ID_FLOAT = 0,\n\tOMAP_DWC3_ID_GROUND = 1,\n\tOMAP_DWC3_VBUS_OFF = 2,\n\tOMAP_DWC3_VBUS_VALID = 3,\n};\n\nenum omap_ecc {\n\tOMAP_ECC_HAM1_CODE_SW = 0,\n\tOMAP_ECC_HAM1_CODE_HW = 1,\n\tOMAP_ECC_BCH4_CODE_HW_DETECTION_SW = 2,\n\tOMAP_ECC_BCH4_CODE_HW = 3,\n\tOMAP_ECC_BCH8_CODE_HW_DETECTION_SW = 4,\n\tOMAP_ECC_BCH8_CODE_HW = 5,\n\tOMAP_ECC_BCH16_CODE_HW = 6,\n};\n\nenum omap_prm_domain_mode {\n\tOMAP_PRMD_OFF = 0,\n\tOMAP_PRMD_RETENTION = 1,\n\tOMAP_PRMD_ON_INACTIVE = 2,\n\tOMAP_PRMD_ON_ACTIVE = 3,\n};\n\nenum omap_reg_offsets {\n\tGCR = 0,\n\tGSCR = 1,\n\tGRST1 = 2,\n\tHW_ID = 3,\n\tPCH2_ID = 4,\n\tPCH0_ID = 5,\n\tPCH1_ID = 6,\n\tPCHG_ID = 7,\n\tPCHD_ID = 8,\n\tCAPS_0 = 9,\n\tCAPS_1 = 10,\n\tCAPS_2 = 11,\n\tCAPS_3 = 12,\n\tCAPS_4 = 13,\n\tPCH2_SR = 14,\n\tPCH0_SR = 15,\n\tPCH1_SR = 16,\n\tPCHD_SR = 17,\n\tREVISION = 18,\n\tIRQSTATUS_L0 = 19,\n\tIRQSTATUS_L1 = 20,\n\tIRQSTATUS_L2 = 21,\n\tIRQSTATUS_L3 = 22,\n\tIRQENABLE_L0 = 23,\n\tIRQENABLE_L1 = 24,\n\tIRQENABLE_L2 = 25,\n\tIRQENABLE_L3 = 26,\n\tSYSSTATUS = 27,\n\tOCP_SYSCONFIG = 28,\n\tCPC = 29,\n\tCCR2 = 30,\n\tLCH_CTRL = 31,\n\tCSDP = 32,\n\tCCR___2 = 33,\n\tCICR = 34,\n\tCSR = 35,\n\tCEN = 36,\n\tCFN = 37,\n\tCSFI = 38,\n\tCSEI = 39,\n\tCSAC = 40,\n\tCDAC = 41,\n\tCDEI = 42,\n\tCDFI = 43,\n\tCLNK_CTRL = 44,\n\tCSSA = 45,\n\tCDSA = 46,\n\tCOLOR = 47,\n\tCCEN = 48,\n\tCCFN = 49,\n\tCDP = 50,\n\tCNDP = 51,\n\tCCDN = 52,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum open_claim_type4 {\n\tNFS4_OPEN_CLAIM_NULL = 0,\n\tNFS4_OPEN_CLAIM_PREVIOUS = 1,\n\tNFS4_OPEN_CLAIM_DELEGATE_CUR = 2,\n\tNFS4_OPEN_CLAIM_DELEGATE_PREV = 3,\n\tNFS4_OPEN_CLAIM_FH = 4,\n\tNFS4_OPEN_CLAIM_DELEG_CUR_FH = 5,\n\tNFS4_OPEN_CLAIM_DELEG_PREV_FH = 6,\n};\n\nenum opentype4 {\n\tNFS4_OPEN_NOCREATE = 0,\n\tNFS4_OPEN_CREATE = 1,\n};\n\nenum operation_mode {\n\tDP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0,\n\tDP_AS_SDP_AVT_FIXED_VTOTAL = 1,\n\tDP_AS_SDP_FAVT_TRR_NOT_REACHED = 2,\n\tDP_AS_SDP_FAVT_TRR_REACHED = 3,\n};\n\nenum opp_table_access {\n\tOPP_TABLE_ACCESS_UNKNOWN = 0,\n\tOPP_TABLE_ACCESS_EXCLUSIVE = 1,\n\tOPP_TABLE_ACCESS_SHARED = 2,\n};\n\nenum orion_ehci_phy_ver {\n\tEHCI_PHY_ORION = 0,\n\tEHCI_PHY_DD = 1,\n\tEHCI_PHY_KW = 2,\n\tEHCI_PHY_NA = 3,\n};\n\nenum orion_mdio_bus_type {\n\tBUS_TYPE_SMI = 0,\n\tBUS_TYPE_XSMI = 1,\n};\n\nenum orion_spi_type {\n\tORION_SPI = 0,\n\tARMADA_SPI = 1,\n};\n\nenum ospi_mux_select_type {\n\tPM_OSPI_MUX_SEL_DMA = 0,\n\tPM_OSPI_MUX_SEL_LINEAR = 1,\n};\n\nenum otg_fsm_timer {\n\tA_WAIT_VRISE = 0,\n\tA_WAIT_VFALL = 1,\n\tA_WAIT_BCON = 2,\n\tA_AIDL_BDIS = 3,\n\tB_ASE0_BRST = 4,\n\tA_BIDL_ADIS = 5,\n\tB_AIDL_BDIS = 6,\n\tB_SE0_SRP = 7,\n\tB_SRP_FAIL = 8,\n\tA_WAIT_ENUM = 9,\n\tB_DATA_PLS = 10,\n\tB_SSEND_SRP = 11,\n\tNUM_OTG_FSM_TIMERS = 12,\n};\n\nenum owl_dma_id {\n\tS900_DMA = 0,\n\tS700_DMA = 1,\n};\n\nenum owl_dmadesc_offsets {\n\tOWL_DMADESC_NEXT_LLI = 0,\n\tOWL_DMADESC_SADDR = 1,\n\tOWL_DMADESC_DADDR = 2,\n\tOWL_DMADESC_FLEN = 3,\n\tOWL_DMADESC_SRC_STRIDE = 4,\n\tOWL_DMADESC_DST_STRIDE = 5,\n\tOWL_DMADESC_CTRLA = 6,\n\tOWL_DMADESC_CTRLB = 7,\n\tOWL_DMADESC_CONST_NUM = 8,\n\tOWL_DMADESC_SIZE = 9,\n};\n\nenum owl_pinconf_drv {\n\tOWL_PINCONF_DRV_2MA = 0,\n\tOWL_PINCONF_DRV_4MA = 1,\n\tOWL_PINCONF_DRV_8MA = 2,\n\tOWL_PINCONF_DRV_12MA = 3,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum packets_types {\n\tPACKET_AVCPQ = 1,\n\tPACKET_PTPQ = 2,\n\tPACKET_DCBCPQ = 3,\n\tPACKET_UPQ = 4,\n\tPACKET_MCBCQ = 5,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 4096,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\tPB_migrate_isolate = 4,\n\t__NR_PAGEBLOCK_BITS = 5,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\t__NR_PAGEFLAGS = 21,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum palmas_external_requestor_id {\n\tPALMAS_EXTERNAL_REQSTR_ID_REGEN1 = 0,\n\tPALMAS_EXTERNAL_REQSTR_ID_REGEN2 = 1,\n\tPALMAS_EXTERNAL_REQSTR_ID_SYSEN1 = 2,\n\tPALMAS_EXTERNAL_REQSTR_ID_SYSEN2 = 3,\n\tPALMAS_EXTERNAL_REQSTR_ID_CLK32KG = 4,\n\tPALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO = 5,\n\tPALMAS_EXTERNAL_REQSTR_ID_REGEN3 = 6,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS12 = 7,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS3 = 8,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS45 = 9,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS6 = 10,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS7 = 11,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS8 = 12,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS9 = 13,\n\tPALMAS_EXTERNAL_REQSTR_ID_SMPS10 = 14,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO1 = 15,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO2 = 16,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO3 = 17,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO4 = 18,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO5 = 19,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO6 = 20,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO7 = 21,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO8 = 22,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDO9 = 23,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDOLN = 24,\n\tPALMAS_EXTERNAL_REQSTR_ID_LDOUSB = 25,\n\tPALMAS_EXTERNAL_REQSTR_ID_MAX = 26,\n};\n\nenum palmas_irqs {\n\tPALMAS_CHARG_DET_N_VBUS_OVV_IRQ = 0,\n\tPALMAS_PWRON_IRQ = 1,\n\tPALMAS_LONG_PRESS_KEY_IRQ = 2,\n\tPALMAS_RPWRON_IRQ = 3,\n\tPALMAS_PWRDOWN_IRQ = 4,\n\tPALMAS_HOTDIE_IRQ = 5,\n\tPALMAS_VSYS_MON_IRQ = 6,\n\tPALMAS_VBAT_MON_IRQ = 7,\n\tPALMAS_RTC_ALARM_IRQ = 8,\n\tPALMAS_RTC_TIMER_IRQ = 9,\n\tPALMAS_WDT_IRQ = 10,\n\tPALMAS_BATREMOVAL_IRQ = 11,\n\tPALMAS_RESET_IN_IRQ = 12,\n\tPALMAS_FBI_BB_IRQ = 13,\n\tPALMAS_SHORT_IRQ = 14,\n\tPALMAS_VAC_ACOK_IRQ = 15,\n\tPALMAS_GPADC_AUTO_0_IRQ = 16,\n\tPALMAS_GPADC_AUTO_1_IRQ = 17,\n\tPALMAS_GPADC_EOC_SW_IRQ = 18,\n\tPALMAS_GPADC_EOC_RT_IRQ = 19,\n\tPALMAS_ID_OTG_IRQ = 20,\n\tPALMAS_ID_IRQ = 21,\n\tPALMAS_VBUS_OTG_IRQ = 22,\n\tPALMAS_VBUS_IRQ = 23,\n\tPALMAS_GPIO_0_IRQ = 24,\n\tPALMAS_GPIO_1_IRQ = 25,\n\tPALMAS_GPIO_2_IRQ = 26,\n\tPALMAS_GPIO_3_IRQ = 27,\n\tPALMAS_GPIO_4_IRQ = 28,\n\tPALMAS_GPIO_5_IRQ = 29,\n\tPALMAS_GPIO_6_IRQ = 30,\n\tPALMAS_GPIO_7_IRQ = 31,\n\tPALMAS_NUM_IRQ = 32,\n};\n\nenum palmas_pinmux {\n\tPALMAS_PINMUX_OPTION0 = 0,\n\tPALMAS_PINMUX_OPTION1 = 1,\n\tPALMAS_PINMUX_OPTION2 = 2,\n\tPALMAS_PINMUX_OPTION3 = 3,\n\tPALMAS_PINMUX_GPIO = 4,\n\tPALMAS_PINMUX_LED = 5,\n\tPALMAS_PINMUX_PWM = 6,\n\tPALMAS_PINMUX_REGEN = 7,\n\tPALMAS_PINMUX_SYSEN = 8,\n\tPALMAS_PINMUX_CLK32KGAUDIO = 9,\n\tPALMAS_PINMUX_ID = 10,\n\tPALMAS_PINMUX_VBUS_DET = 11,\n\tPALMAS_PINMUX_CHRG_DET = 12,\n\tPALMAS_PINMUX_VAC = 13,\n\tPALMAS_PINMUX_VACOK = 14,\n\tPALMAS_PINMUX_POWERGOOD = 15,\n\tPALMAS_PINMUX_USB_PSEL = 16,\n\tPALMAS_PINMUX_MSECURE = 17,\n\tPALMAS_PINMUX_PWRHOLD = 18,\n\tPALMAS_PINMUX_INT = 19,\n\tPALMAS_PINMUX_NRESWARM = 20,\n\tPALMAS_PINMUX_SIMRSTO = 21,\n\tPALMAS_PINMUX_SIMRSTI = 22,\n\tPALMAS_PINMUX_LOW_VBAT = 23,\n\tPALMAS_PINMUX_WIRELESS_CHRG1 = 24,\n\tPALMAS_PINMUX_RCM = 25,\n\tPALMAS_PINMUX_PWRDOWN = 26,\n\tPALMAS_PINMUX_GPADC_START = 27,\n\tPALMAS_PINMUX_RESET_IN = 28,\n\tPALMAS_PINMUX_NSLEEP = 29,\n\tPALMAS_PINMUX_ENABLE = 30,\n\tPALMAS_PINMUX_NA = 65535,\n};\n\nenum palmas_regulators {\n\tPALMAS_REG_SMPS12 = 0,\n\tPALMAS_REG_SMPS123 = 1,\n\tPALMAS_REG_SMPS3 = 2,\n\tPALMAS_REG_SMPS45 = 3,\n\tPALMAS_REG_SMPS457 = 4,\n\tPALMAS_REG_SMPS6 = 5,\n\tPALMAS_REG_SMPS7 = 6,\n\tPALMAS_REG_SMPS8 = 7,\n\tPALMAS_REG_SMPS9 = 8,\n\tPALMAS_REG_SMPS10_OUT2 = 9,\n\tPALMAS_REG_SMPS10_OUT1 = 10,\n\tPALMAS_REG_LDO1 = 11,\n\tPALMAS_REG_LDO2 = 12,\n\tPALMAS_REG_LDO3 = 13,\n\tPALMAS_REG_LDO4 = 14,\n\tPALMAS_REG_LDO5 = 15,\n\tPALMAS_REG_LDO6 = 16,\n\tPALMAS_REG_LDO7 = 17,\n\tPALMAS_REG_LDO8 = 18,\n\tPALMAS_REG_LDO9 = 19,\n\tPALMAS_REG_LDOLN = 20,\n\tPALMAS_REG_LDOUSB = 21,\n\tPALMAS_REG_REGEN1 = 22,\n\tPALMAS_REG_REGEN2 = 23,\n\tPALMAS_REG_REGEN3 = 24,\n\tPALMAS_REG_SYSEN1 = 25,\n\tPALMAS_REG_SYSEN2 = 26,\n\tPALMAS_NUM_REGS = 27,\n};\n\nenum palmas_usb_state {\n\tPALMAS_USB_STATE_DISCONNECT = 0,\n\tPALMAS_USB_STATE_VBUS = 1,\n\tPALMAS_USB_STATE_ID = 2,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nenum pb_isolate_mode {\n\tPB_ISOLATE_MODE_MEM_OFFLINE = 0,\n\tPB_ISOLATE_MODE_CMA_ALLOC = 1,\n\tPB_ISOLATE_MODE_OTHER = 2,\n};\n\nenum pca_type {\n\tmax_7356 = 0,\n\tmax_7357 = 1,\n\tmax_7358 = 2,\n\tmax_7367 = 3,\n\tmax_7368 = 4,\n\tmax_7369 = 5,\n\tpca_9540 = 6,\n\tpca_9542 = 7,\n\tpca_9543 = 8,\n\tpca_9544 = 9,\n\tpca_9545 = 10,\n\tpca_9546 = 11,\n\tpca_9547 = 12,\n\tpca_9548 = 13,\n\tpca_9846 = 14,\n\tpca_9847 = 15,\n\tpca_9848 = 16,\n\tpca_9849 = 17,\n};\n\nenum pce_status {\n\tPCE_STATUS_NONE = 0,\n\tPCE_STATUS_ACQUIRED = 1,\n\tPCE_STATUS_PREPARED = 2,\n\tPCE_STATUS_ENABLED = 3,\n\tPCE_STATUS_ERROR = 4,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_barno {\n\tNO_BAR = -1,\n\tBAR_0 = 0,\n\tBAR_1 = 1,\n\tBAR_2 = 2,\n\tBAR_3 = 3,\n\tBAR_4 = 4,\n\tBAR_5 = 5,\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_15625000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_oxsemi = 71,\n\tpbn_oxsemi_1_15625000 = 72,\n\tpbn_oxsemi_2_15625000 = 73,\n\tpbn_oxsemi_4_15625000 = 74,\n\tpbn_oxsemi_8_15625000 = 75,\n\tpbn_intel_i960 = 76,\n\tpbn_sgi_ioc3 = 77,\n\tpbn_computone_4 = 78,\n\tpbn_computone_6 = 79,\n\tpbn_computone_8 = 80,\n\tpbn_sbsxrsio = 81,\n\tpbn_pasemi_1682M = 82,\n\tpbn_ni8430_2 = 83,\n\tpbn_ni8430_4 = 84,\n\tpbn_ni8430_8 = 85,\n\tpbn_ni8430_16 = 86,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 87,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 90,\n\tpbn_ce4100_1_115200 = 91,\n\tpbn_omegapci = 92,\n\tpbn_NETMOS9900_2s_115200 = 93,\n\tpbn_brcm_trumanage = 94,\n\tpbn_fintek_4 = 95,\n\tpbn_fintek_8 = 96,\n\tpbn_fintek_12 = 97,\n\tpbn_fintek_F81504A = 98,\n\tpbn_fintek_F81508A = 99,\n\tpbn_fintek_F81512A = 100,\n\tpbn_wch382_2 = 101,\n\tpbn_wch384_4 = 102,\n\tpbn_wch384_8 = 103,\n\tpbn_sunix_pci_1s = 104,\n\tpbn_sunix_pci_2s = 105,\n\tpbn_sunix_pci_4s = 106,\n\tpbn_sunix_pci_8s = 107,\n\tpbn_sunix_pci_16s = 108,\n\tpbn_titan_1_4000000 = 109,\n\tpbn_titan_2_4000000 = 110,\n\tpbn_titan_4_4000000 = 111,\n\tpbn_titan_8_4000000 = 112,\n\tpbn_moxa_2 = 113,\n\tpbn_moxa_4 = 114,\n\tpbn_moxa_8 = 115,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_epc_bar_type {\n\tBAR_PROGRAMMABLE = 0,\n\tBAR_FIXED = 1,\n\tBAR_RESIZABLE = 2,\n\tBAR_RESERVED = 3,\n};\n\nenum pci_epc_interface_type {\n\tUNKNOWN_INTERFACE = -1,\n\tPRIMARY_INTERFACE = 0,\n\tSECONDARY_INTERFACE = 1,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_hotplug_event {\n\tPCI_HOTPLUG_LINK_UP = 0,\n\tPCI_HOTPLUG_LINK_DOWN = 1,\n\tPCI_HOTPLUG_CARD_PRESENT = 2,\n\tPCI_HOTPLUG_CARD_NOT_PRESENT = 3,\n};\n\nenum pci_interrupt_pin {\n\tPCI_INTERRUPT_UNKNOWN = 0,\n\tPCI_INTERRUPT_INTA = 1,\n\tPCI_INTERRUPT_INTB = 2,\n\tPCI_INTERRUPT_INTC = 3,\n\tPCI_INTERRUPT_INTD = 4,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcie_soc_base {\n\tGENERIC = 0,\n\tBCM2711 = 1,\n\tBCM4908 = 2,\n\tBCM7278 = 3,\n\tBCM7425 = 4,\n\tBCM7435 = 5,\n\tBCM7712 = 6,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum pd_types {\n\tPD_NORMAL = 0,\n\tPD_CPU = 1,\n\tPD_CONSOLE = 2,\n\tPD_DEBUG = 3,\n\tPD_MEMCTL = 4,\n};\n\nenum pegasus_registers {\n\tEthCtrl0 = 0,\n\tEthCtrl1 = 1,\n\tEthCtrl2 = 2,\n\tEthID = 16,\n\tReg1d = 29,\n\tEpromOffset = 32,\n\tEpromData = 33,\n\tEpromCtrl = 35,\n\tPhyAddr = 37,\n\tPhyData = 38,\n\tPhyCtrl = 40,\n\tUsbStst = 42,\n\tEthTxStat0 = 43,\n\tEthTxStat1 = 44,\n\tEthRxStat = 45,\n\tWakeupControl = 120,\n\tReg7b = 123,\n\tGpio0 = 126,\n\tGpio1 = 127,\n\tReg81 = 129,\n};\n\nenum pegasus_usb_ep {\n\tPEGASUS_USB_EP_CONTROL = 0,\n\tPEGASUS_USB_EP_BULK_IN = 1,\n\tPEGASUS_USB_EP_BULK_OUT = 2,\n\tPEGASUS_USB_EP_INT_IN = 3,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE = 262144,\n\tPERF_SAMPLE_BRANCH_COUNTERS = 524288,\n\tPERF_SAMPLE_BRANCH_MAX = 1048576,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 18446744073709551584ULL,\n\tPERF_CONTEXT_KERNEL = 18446744073709551488ULL,\n\tPERF_CONTEXT_USER = 18446744073709551104ULL,\n\tPERF_CONTEXT_USER_DEFERRED = 18446744073709550976ULL,\n\tPERF_CONTEXT_GUEST = 18446744073709549568ULL,\n\tPERF_CONTEXT_GUEST_KERNEL = 18446744073709549440ULL,\n\tPERF_CONTEXT_GUEST_USER = 18446744073709549056ULL,\n\tPERF_CONTEXT_MAX = 18446744073709547521ULL,\n};\n\nenum perf_event_arm_regs {\n\tPERF_REG_ARM_R0 = 0,\n\tPERF_REG_ARM_R1 = 1,\n\tPERF_REG_ARM_R2 = 2,\n\tPERF_REG_ARM_R3 = 3,\n\tPERF_REG_ARM_R4 = 4,\n\tPERF_REG_ARM_R5 = 5,\n\tPERF_REG_ARM_R6 = 6,\n\tPERF_REG_ARM_R7 = 7,\n\tPERF_REG_ARM_R8 = 8,\n\tPERF_REG_ARM_R9 = 9,\n\tPERF_REG_ARM_R10 = 10,\n\tPERF_REG_ARM_FP = 11,\n\tPERF_REG_ARM_IP = 12,\n\tPERF_REG_ARM_SP = 13,\n\tPERF_REG_ARM_LR = 14,\n\tPERF_REG_ARM_PC = 15,\n\tPERF_REG_ARM_MAX = 16,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_LOST = 16,\n\tPERF_FORMAT_MAX = 32,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_DATA_PAGE_SIZE = 4194304,\n\tPERF_SAMPLE_CODE_PAGE_SIZE = 8388608,\n\tPERF_SAMPLE_WEIGHT_STRUCT = 16777216,\n\tPERF_SAMPLE_MAX = 33554432,\n};\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = -5,\n\tPERF_EVENT_STATE_REVOKED = -4,\n\tPERF_EVENT_STATE_EXIT = -3,\n\tPERF_EVENT_STATE_ERROR = -2,\n\tPERF_EVENT_STATE_OFF = -1,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = -1,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_TEXT_POKE = 20,\n\tPERF_RECORD_AUX_OUTPUT_HW_ID = 21,\n\tPERF_RECORD_CALLCHAIN_DEFERRED = 22,\n\tPERF_RECORD_MAX = 23,\n};\n\nenum perf_hw_cache_id {\n\tPERF_COUNT_HW_CACHE_L1D = 0,\n\tPERF_COUNT_HW_CACHE_L1I = 1,\n\tPERF_COUNT_HW_CACHE_LL = 2,\n\tPERF_COUNT_HW_CACHE_DTLB = 3,\n\tPERF_COUNT_HW_CACHE_ITLB = 4,\n\tPERF_COUNT_HW_CACHE_BPU = 5,\n\tPERF_COUNT_HW_CACHE_NODE = 6,\n\tPERF_COUNT_HW_CACHE_MAX = 7,\n};\n\nenum perf_hw_cache_op_id {\n\tPERF_COUNT_HW_CACHE_OP_READ = 0,\n\tPERF_COUNT_HW_CACHE_OP_WRITE = 1,\n\tPERF_COUNT_HW_CACHE_OP_PREFETCH = 2,\n\tPERF_COUNT_HW_CACHE_OP_MAX = 3,\n};\n\nenum perf_hw_cache_op_result_id {\n\tPERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,\n\tPERF_COUNT_HW_CACHE_RESULT_MISS = 1,\n\tPERF_COUNT_HW_CACHE_RESULT_MAX = 2,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_pmu_scope {\n\tPERF_PMU_SCOPE_NONE = 0,\n\tPERF_PMU_SCOPE_CORE = 1,\n\tPERF_PMU_SCOPE_DIE = 2,\n\tPERF_PMU_SCOPE_CLUSTER = 3,\n\tPERF_PMU_SCOPE_PKG = 4,\n\tPERF_PMU_SCOPE_SYS_WIDE = 5,\n\tPERF_PMU_MAX_SCOPE = 6,\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum phy_led_modes {\n\tPHY_LED_ACTIVE_HIGH = 0,\n\tPHY_LED_ACTIVE_LOW = 1,\n\tPHY_LED_INACTIVE_HIGH_IMPEDANCE = 2,\n\t__PHY_LED_MODES_NUM = 3,\n};\n\nenum phy_media {\n\tPHY_MEDIA_DEFAULT = 0,\n\tPHY_MEDIA_SR = 1,\n\tPHY_MEDIA_DAC = 2,\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n\tPHY_MODE_HDMI = 20,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_port_parent {\n\tPHY_PORT_PHY = 0,\n};\n\nenum phy_reset_delays {\n\tPRE_DELAY = 0,\n\tPULSE = 1,\n\tPOST_DELAY = 2,\n\tDELAYS_NUM = 3,\n};\n\nenum phy_speed_mode {\n\tSPEED_MODE_GEN1 = 0,\n\tSPEED_MODE_GEN2 = 1,\n\tSPEED_MODE_GEN3 = 2,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_state_work {\n\tPHY_STATE_WORK_NONE = 0,\n\tPHY_STATE_WORK_ANEG = 1,\n\tPHY_STATE_WORK_SUSPEND = 2,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_ufs_state {\n\tPHY_UFS_HIBERN8_ENTER = 0,\n\tPHY_UFS_HIBERN8_EXIT = 1,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum phylink_op_type {\n\tPHYLINK_NETDEV = 0,\n\tPHYLINK_DEV = 1,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum pin_config_param {\n\tPIN_CONFIG_BIAS_BUS_HOLD = 0,\n\tPIN_CONFIG_BIAS_DISABLE = 1,\n\tPIN_CONFIG_BIAS_HIGH_IMPEDANCE = 2,\n\tPIN_CONFIG_BIAS_PULL_DOWN = 3,\n\tPIN_CONFIG_BIAS_PULL_PIN_DEFAULT = 4,\n\tPIN_CONFIG_BIAS_PULL_UP = 5,\n\tPIN_CONFIG_DRIVE_OPEN_DRAIN = 6,\n\tPIN_CONFIG_DRIVE_OPEN_SOURCE = 7,\n\tPIN_CONFIG_DRIVE_PUSH_PULL = 8,\n\tPIN_CONFIG_DRIVE_STRENGTH = 9,\n\tPIN_CONFIG_DRIVE_STRENGTH_UA = 10,\n\tPIN_CONFIG_INPUT_DEBOUNCE = 11,\n\tPIN_CONFIG_INPUT_ENABLE = 12,\n\tPIN_CONFIG_INPUT_SCHMITT = 13,\n\tPIN_CONFIG_INPUT_SCHMITT_ENABLE = 14,\n\tPIN_CONFIG_INPUT_SCHMITT_UV = 15,\n\tPIN_CONFIG_MODE_LOW_POWER = 16,\n\tPIN_CONFIG_MODE_PWM = 17,\n\tPIN_CONFIG_LEVEL = 18,\n\tPIN_CONFIG_OUTPUT_ENABLE = 19,\n\tPIN_CONFIG_OUTPUT_IMPEDANCE_OHMS = 20,\n\tPIN_CONFIG_PERSIST_STATE = 21,\n\tPIN_CONFIG_POWER_SOURCE = 22,\n\tPIN_CONFIG_SKEW_DELAY = 23,\n\tPIN_CONFIG_SKEW_DELAY_INPUT_PS = 24,\n\tPIN_CONFIG_SKEW_DELAY_OUTPUT_PS = 25,\n\tPIN_CONFIG_SLEEP_HARDWARE_STATE = 26,\n\tPIN_CONFIG_SLEW_RATE = 27,\n\tPIN_CONFIG_END = 127,\n\tPIN_CONFIG_MAX = 255,\n};\n\nenum pincfg_type {\n\tPINCFG_TYPE_FUNC = 0,\n\tPINCFG_TYPE_DAT = 1,\n\tPINCFG_TYPE_PUD = 2,\n\tPINCFG_TYPE_DRV = 3,\n\tPINCFG_TYPE_CON_PDN = 4,\n\tPINCFG_TYPE_PUD_PDN = 5,\n\tPINCFG_TYPE_NUM = 6,\n};\n\nenum pinctrl_map_type {\n\tPIN_MAP_TYPE_INVALID = 0,\n\tPIN_MAP_TYPE_DUMMY_STATE = 1,\n\tPIN_MAP_TYPE_MUX_GROUP = 2,\n\tPIN_MAP_TYPE_CONFIGS_PIN = 3,\n\tPIN_MAP_TYPE_CONFIGS_GROUP = 4,\n};\n\nenum pinmux_type {\n\tpinmux_type_fpmx = 0,\n\tpinmux_type_grp = 1,\n};\n\nenum pipe3_mode {\n\tPIPE3_MODE_PCIE = 1,\n\tPIPE3_MODE_SATA = 2,\n\tPIPE3_MODE_USBSS = 3,\n};\n\nenum pkcs7_actions {\n\tACT_pkcs7_check_content_type = 0,\n\tACT_pkcs7_extract_cert = 1,\n\tACT_pkcs7_note_OID = 2,\n\tACT_pkcs7_note_certificate_list = 3,\n\tACT_pkcs7_note_content = 4,\n\tACT_pkcs7_note_data = 5,\n\tACT_pkcs7_note_signed_info = 6,\n\tACT_pkcs7_note_signeddata_version = 7,\n\tACT_pkcs7_note_signerinfo_version = 8,\n\tACT_pkcs7_sig_note_authenticated_attr = 9,\n\tACT_pkcs7_sig_note_digest_algo = 10,\n\tACT_pkcs7_sig_note_issuer = 11,\n\tACT_pkcs7_sig_note_pkey_algo = 12,\n\tACT_pkcs7_sig_note_serial = 13,\n\tACT_pkcs7_sig_note_set_of_authattrs = 14,\n\tACT_pkcs7_sig_note_signature = 15,\n\tACT_pkcs7_sig_note_skid = 16,\n\tNR__pkcs7_actions = 17,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum pl011_rs485_tx_state {\n\tOFF___2 = 0,\n\tWAIT_AFTER_RTS___2 = 1,\n\tSEND___2 = 2,\n\tWAIT_AFTER_SEND___2 = 3,\n};\n\nenum pl330_byteswap {\n\tSWAP_NO = 0,\n\tSWAP_2 = 1,\n\tSWAP_4 = 2,\n\tSWAP_8 = 3,\n\tSWAP_16 = 4,\n};\n\nenum pl330_cachectrl {\n\tCCTRL0 = 0,\n\tCCTRL1 = 1,\n\tCCTRL2 = 2,\n\tCCTRL3 = 3,\n\tINVALID1 = 4,\n\tINVALID2 = 5,\n\tCCTRL6 = 6,\n\tCCTRL7 = 7,\n};\n\nenum pl330_cond {\n\tSINGLE = 0,\n\tBURST = 1,\n\tALWAYS = 2,\n};\n\nenum pl330_dmac_state {\n\tUNINIT = 0,\n\tINIT = 1,\n\tDYING = 2,\n};\n\nenum pl330_op_err {\n\tPL330_ERR_NONE = 0,\n\tPL330_ERR_ABORT = 1,\n\tPL330_ERR_FAIL = 2,\n};\n\nenum pll_component_id {\n\tPLL_COMPID_FRAC = 0,\n\tPLL_COMPID_DIV0 = 1,\n\tPLL_COMPID_DIV1 = 2,\n\tPLL_COMPID_MAX = 3,\n};\n\nenum pll_ctrl_bits {\n\tPLL_RESETB = 0,\n\tSSPLL_SUSPEND_EN = 1,\n\tPLL_SEQ_START = 2,\n\tPLL_LOCK = 3,\n};\n\nenum pll_ids {\n\tPLL_ID_CPU = 0,\n\tPLL_ID_SYS = 1,\n\tPLL_ID_DDR = 2,\n\tPLL_ID_IMG = 3,\n\tPLL_ID_BAUD = 4,\n\tPLL_ID_AUDIO = 5,\n\tPLL_ID_ETH = 6,\n\tPLL_ID_MAX = 7,\n};\n\nenum pll_ids___2 {\n\tPLL_ID_CPU___2 = 0,\n\tPLL_ID_SYS___2 = 1,\n\tPLL_ID_DDR___2 = 2,\n\tPLL_ID_GPU = 3,\n\tPLL_ID_BAUD___2 = 4,\n\tPLL_ID_AUDIO___2 = 5,\n\tPLL_ID_ETH___2 = 6,\n\tPLL_ID_LVDS = 7,\n\tPLL_ID_USB = 8,\n\tPLL_ID_MAX___2 = 9,\n};\n\nenum pll_type {\n\tPLL_TYPE_FRAC = 0,\n\tPLL_TYPE_DIV = 1,\n};\n\nenum pm_api_id {\n\tPM_API_FEATURES = 0,\n\tPM_GET_API_VERSION = 1,\n\tPM_GET_NODE_STATUS = 3,\n\tPM_REGISTER_NOTIFIER = 5,\n\tPM_FORCE_POWERDOWN = 8,\n\tPM_REQUEST_WAKEUP = 10,\n\tPM_SYSTEM_SHUTDOWN = 12,\n\tPM_REQUEST_NODE = 13,\n\tPM_RELEASE_NODE = 14,\n\tPM_SET_REQUIREMENT = 15,\n\tPM_RESET_ASSERT = 17,\n\tPM_RESET_GET_STATUS = 18,\n\tPM_MMIO_WRITE = 19,\n\tPM_MMIO_READ = 20,\n\tPM_PM_INIT_FINALIZE = 21,\n\tPM_FPGA_LOAD = 22,\n\tPM_FPGA_GET_STATUS = 23,\n\tPM_GET_CHIPID = 24,\n\tPM_SECURE_SHA = 26,\n\tPM_PINCTRL_REQUEST = 28,\n\tPM_PINCTRL_RELEASE = 29,\n\tPM_PINCTRL_SET_FUNCTION = 31,\n\tPM_PINCTRL_CONFIG_PARAM_GET = 32,\n\tPM_PINCTRL_CONFIG_PARAM_SET = 33,\n\tPM_IOCTL = 34,\n\tPM_QUERY_DATA = 35,\n\tPM_CLOCK_ENABLE = 36,\n\tPM_CLOCK_DISABLE = 37,\n\tPM_CLOCK_GETSTATE = 38,\n\tPM_CLOCK_SETDIVIDER = 39,\n\tPM_CLOCK_GETDIVIDER = 40,\n\tPM_CLOCK_SETPARENT = 43,\n\tPM_CLOCK_GETPARENT = 44,\n\tPM_FPGA_READ = 46,\n\tPM_SECURE_AES = 47,\n\tPM_EFUSE_ACCESS = 53,\n\tPM_FEATURE_CHECK = 63,\n};\n\nenum pm_gem_config_type {\n\tGEM_CONFIG_SGMII_MODE = 1,\n\tGEM_CONFIG_FIXED = 2,\n};\n\nenum pm_ioctl_id {\n\tIOCTL_GET_RPU_OPER_MODE = 0,\n\tIOCTL_SET_RPU_OPER_MODE = 1,\n\tIOCTL_RPU_BOOT_ADDR_CONFIG = 2,\n\tIOCTL_TCM_COMB_CONFIG = 3,\n\tIOCTL_SET_TAPDELAY_BYPASS = 4,\n\tIOCTL_SD_DLL_RESET = 6,\n\tIOCTL_SET_SD_TAPDELAY = 7,\n\tIOCTL_SET_PLL_FRAC_MODE = 8,\n\tIOCTL_GET_PLL_FRAC_MODE = 9,\n\tIOCTL_SET_PLL_FRAC_DATA = 10,\n\tIOCTL_GET_PLL_FRAC_DATA = 11,\n\tIOCTL_WRITE_GGS = 12,\n\tIOCTL_READ_GGS = 13,\n\tIOCTL_WRITE_PGGS = 14,\n\tIOCTL_READ_PGGS = 15,\n\tIOCTL_SET_BOOT_HEALTH_STATUS = 17,\n\tIOCTL_OSPI_MUX_SELECT = 21,\n\tIOCTL_REGISTER_SGI = 25,\n\tIOCTL_SET_FEATURE_CONFIG = 26,\n\tIOCTL_GET_FEATURE_CONFIG = 27,\n\tIOCTL_READ_REG = 28,\n\tIOCTL_MASK_WRITE_REG = 29,\n\tIOCTL_SET_SD_CONFIG = 30,\n\tIOCTL_SET_GEM_CONFIG = 31,\n\tIOCTL_GET_QOS = 34,\n};\n\nenum pm_node_id {\n\tNODE_SD_0 = 39,\n\tNODE_SD_1 = 40,\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = -1,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum pm_sd_config_type {\n\tSD_CONFIG_EMMC_SEL = 1,\n\tSD_CONFIG_BASECLK = 2,\n\tSD_CONFIG_8BIT = 3,\n\tSD_CONFIG_FIXED = 4,\n};\n\nenum pm_sleep_mode {\n\tPM_SLEEP_MODE_STBY = 0,\n\tPM_SLEEP_MODE_RET = 1,\n\tPM_SLEEP_MODE_SPC = 2,\n\tPM_SLEEP_MODE_PC = 3,\n\tPM_SLEEP_MODE_NR = 4,\n};\n\nenum pmic_arb_channel {\n\tPMIC_ARB_CHANNEL_RW = 0,\n\tPMIC_ARB_CHANNEL_OBS = 1,\n};\n\nenum pmic_arb_chnl_status {\n\tPMIC_ARB_STATUS_DONE = 1,\n\tPMIC_ARB_STATUS_FAILURE = 2,\n\tPMIC_ARB_STATUS_DENIED = 4,\n\tPMIC_ARB_STATUS_DROPPED = 8,\n};\n\nenum pmic_arb_cmd_op_code {\n\tPMIC_ARB_OP_EXT_WRITEL = 0,\n\tPMIC_ARB_OP_EXT_READL = 1,\n\tPMIC_ARB_OP_EXT_WRITE = 2,\n\tPMIC_ARB_OP_RESET = 3,\n\tPMIC_ARB_OP_SLEEP = 4,\n\tPMIC_ARB_OP_SHUTDOWN = 5,\n\tPMIC_ARB_OP_WAKEUP = 6,\n\tPMIC_ARB_OP_AUTHENTICATE = 7,\n\tPMIC_ARB_OP_MSTR_READ = 8,\n\tPMIC_ARB_OP_MSTR_WRITE = 9,\n\tPMIC_ARB_OP_EXT_READ = 13,\n\tPMIC_ARB_OP_WRITE = 14,\n\tPMIC_ARB_OP_READ = 15,\n\tPMIC_ARB_OP_ZERO_WRITE = 16,\n};\n\nenum pmic_gpio_func_index {\n\tPMIC_GPIO_FUNC_INDEX_NORMAL = 0,\n\tPMIC_GPIO_FUNC_INDEX_PAIRED = 1,\n\tPMIC_GPIO_FUNC_INDEX_FUNC1 = 2,\n\tPMIC_GPIO_FUNC_INDEX_FUNC2 = 3,\n\tPMIC_GPIO_FUNC_INDEX_FUNC3 = 4,\n\tPMIC_GPIO_FUNC_INDEX_FUNC4 = 5,\n\tPMIC_GPIO_FUNC_INDEX_DTEST1 = 6,\n\tPMIC_GPIO_FUNC_INDEX_DTEST2 = 7,\n\tPMIC_GPIO_FUNC_INDEX_DTEST3 = 8,\n\tPMIC_GPIO_FUNC_INDEX_DTEST4 = 9,\n};\n\nenum pmic_id {\n\tTPS65214 = 0,\n\tTPS65215 = 1,\n\tTPS65219 = 2,\n};\n\nenum pmsu_idle_prepare_flags {\n\tPMSU_PREPARE_NORMAL = 0,\n\tPMSU_PREPARE_DEEP_IDLE = 1,\n\tPMSU_PREPARE_SNOOP_DISABLE = 2,\n};\n\nenum pnfs_iomode {\n\tIOMODE_READ = 1,\n\tIOMODE_RW = 2,\n\tIOMODE_ANY = 3,\n};\n\nenum pnfs_layout_destroy_mode {\n\tPNFS_LAYOUT_INVALIDATE = 0,\n\tPNFS_LAYOUT_BULK_RETURN = 1,\n\tPNFS_LAYOUT_FILE_BULK_RETURN = 2,\n};\n\nenum pnfs_layoutreturn_type {\n\tRETURN_FILE = 1,\n\tRETURN_FSID = 2,\n\tRETURN_ALL = 3,\n};\n\nenum pnfs_layouttype {\n\tLAYOUT_NFSV4_1_FILES = 1,\n\tLAYOUT_OSD2_OBJECTS = 2,\n\tLAYOUT_BLOCK_VOLUME = 3,\n\tLAYOUT_FLEX_FILES = 4,\n\tLAYOUT_SCSI = 5,\n\tLAYOUT_TYPE_MAX = 6,\n};\n\nenum pnfs_notify_deviceid_type4 {\n\tNOTIFY_DEVICEID4_CHANGE = 2,\n\tNOTIFY_DEVICEID4_DELETE = 4,\n};\n\nenum pnfs_try_status {\n\tPNFS_ATTEMPTED = 0,\n\tPNFS_NOT_ATTEMPTED = 1,\n\tPNFS_TRY_AGAIN = 2,\n};\n\nenum pnfs_update_layout_reason {\n\tPNFS_UPDATE_LAYOUT_UNKNOWN = 0,\n\tPNFS_UPDATE_LAYOUT_NO_PNFS = 1,\n\tPNFS_UPDATE_LAYOUT_RD_ZEROLEN = 2,\n\tPNFS_UPDATE_LAYOUT_MDSTHRESH = 3,\n\tPNFS_UPDATE_LAYOUT_NOMEM = 4,\n\tPNFS_UPDATE_LAYOUT_BULK_RECALL = 5,\n\tPNFS_UPDATE_LAYOUT_IO_TEST_FAIL = 6,\n\tPNFS_UPDATE_LAYOUT_FOUND_CACHED = 7,\n\tPNFS_UPDATE_LAYOUT_RETURN = 8,\n\tPNFS_UPDATE_LAYOUT_RETRY = 9,\n\tPNFS_UPDATE_LAYOUT_BLOCKED = 10,\n\tPNFS_UPDATE_LAYOUT_INVALID_OPEN = 11,\n\tPNFS_UPDATE_LAYOUT_SEND_LAYOUTGET = 12,\n\tPNFS_UPDATE_LAYOUT_EXIT = 13,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port_pkey_state {\n\tIB_PORT_PKEY_NOT_VALID = 0,\n\tIB_PORT_PKEY_VALID = 1,\n\tIB_PORT_PKEY_LISTED = 2,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum power_event {\n\tpointer_reset = 2147483648,\n\tglobal_unicast = 512,\n\twake_up_rx_frame = 64,\n\tmagic_frame = 32,\n\twake_up_frame_en = 4,\n\tmagic_pkt_en = 2,\n\tpower_down = 1,\n};\n\nenum power_supply_charge_behaviour {\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO = 0,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE = 1,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE_AWAKE = 2,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE = 3,\n};\n\nenum power_supply_charge_type {\n\tPOWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_CHARGE_TYPE_NONE = 1,\n\tPOWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2,\n\tPOWER_SUPPLY_CHARGE_TYPE_FAST = 3,\n\tPOWER_SUPPLY_CHARGE_TYPE_STANDARD = 4,\n\tPOWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5,\n\tPOWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6,\n\tPOWER_SUPPLY_CHARGE_TYPE_LONGLIFE = 7,\n\tPOWER_SUPPLY_CHARGE_TYPE_BYPASS = 8,\n};\n\nenum power_supply_notifier_events {\n\tPSY_EVENT_PROP_CHANGED = 0,\n};\n\nenum power_supply_property {\n\tPOWER_SUPPLY_PROP_STATUS = 0,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPE = 1,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPES = 2,\n\tPOWER_SUPPLY_PROP_HEALTH = 3,\n\tPOWER_SUPPLY_PROP_PRESENT = 4,\n\tPOWER_SUPPLY_PROP_ONLINE = 5,\n\tPOWER_SUPPLY_PROP_AUTHENTIC = 6,\n\tPOWER_SUPPLY_PROP_TECHNOLOGY = 7,\n\tPOWER_SUPPLY_PROP_CYCLE_COUNT = 8,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX = 9,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN = 10,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN = 11,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN = 12,\n\tPOWER_SUPPLY_PROP_VOLTAGE_NOW = 13,\n\tPOWER_SUPPLY_PROP_VOLTAGE_AVG = 14,\n\tPOWER_SUPPLY_PROP_VOLTAGE_OCV = 15,\n\tPOWER_SUPPLY_PROP_VOLTAGE_BOOT = 16,\n\tPOWER_SUPPLY_PROP_CURRENT_MAX = 17,\n\tPOWER_SUPPLY_PROP_CURRENT_NOW = 18,\n\tPOWER_SUPPLY_PROP_CURRENT_AVG = 19,\n\tPOWER_SUPPLY_PROP_CURRENT_BOOT = 20,\n\tPOWER_SUPPLY_PROP_POWER_NOW = 21,\n\tPOWER_SUPPLY_PROP_POWER_AVG = 22,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL_DESIGN = 23,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN = 24,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL = 25,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY = 26,\n\tPOWER_SUPPLY_PROP_CHARGE_NOW = 27,\n\tPOWER_SUPPLY_PROP_CHARGE_AVG = 28,\n\tPOWER_SUPPLY_PROP_CHARGE_COUNTER = 29,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT = 30,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX = 31,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE = 32,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX = 33,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT = 34,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX = 35,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD = 36,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD = 37,\n\tPOWER_SUPPLY_PROP_CHARGE_BEHAVIOUR = 38,\n\tPOWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT = 39,\n\tPOWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT = 40,\n\tPOWER_SUPPLY_PROP_INPUT_POWER_LIMIT = 41,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL_DESIGN = 42,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN = 43,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL = 44,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY = 45,\n\tPOWER_SUPPLY_PROP_ENERGY_NOW = 46,\n\tPOWER_SUPPLY_PROP_ENERGY_AVG = 47,\n\tPOWER_SUPPLY_PROP_CAPACITY = 48,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MIN = 49,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MAX = 50,\n\tPOWER_SUPPLY_PROP_CAPACITY_ERROR_MARGIN = 51,\n\tPOWER_SUPPLY_PROP_CAPACITY_LEVEL = 52,\n\tPOWER_SUPPLY_PROP_TEMP = 53,\n\tPOWER_SUPPLY_PROP_TEMP_MAX = 54,\n\tPOWER_SUPPLY_PROP_TEMP_MIN = 55,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MIN = 56,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MAX = 57,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT = 58,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN = 59,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX = 60,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW = 61,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG = 62,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_NOW = 63,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_AVG = 64,\n\tPOWER_SUPPLY_PROP_TYPE = 65,\n\tPOWER_SUPPLY_PROP_USB_TYPE = 66,\n\tPOWER_SUPPLY_PROP_SCOPE = 67,\n\tPOWER_SUPPLY_PROP_PRECHARGE_CURRENT = 68,\n\tPOWER_SUPPLY_PROP_CHARGE_TERM_CURRENT = 69,\n\tPOWER_SUPPLY_PROP_CALIBRATE = 70,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_YEAR = 71,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_MONTH = 72,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_DAY = 73,\n\tPOWER_SUPPLY_PROP_INTERNAL_RESISTANCE = 74,\n\tPOWER_SUPPLY_PROP_STATE_OF_HEALTH = 75,\n\tPOWER_SUPPLY_PROP_MODEL_NAME = 76,\n\tPOWER_SUPPLY_PROP_MANUFACTURER = 77,\n\tPOWER_SUPPLY_PROP_SERIAL_NUMBER = 78,\n};\n\nenum power_supply_type {\n\tPOWER_SUPPLY_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_TYPE_BATTERY = 1,\n\tPOWER_SUPPLY_TYPE_UPS = 2,\n\tPOWER_SUPPLY_TYPE_MAINS = 3,\n\tPOWER_SUPPLY_TYPE_USB = 4,\n\tPOWER_SUPPLY_TYPE_USB_DCP = 5,\n\tPOWER_SUPPLY_TYPE_USB_CDP = 6,\n\tPOWER_SUPPLY_TYPE_USB_ACA = 7,\n\tPOWER_SUPPLY_TYPE_USB_TYPE_C = 8,\n\tPOWER_SUPPLY_TYPE_USB_PD = 9,\n\tPOWER_SUPPLY_TYPE_USB_PD_DRP = 10,\n\tPOWER_SUPPLY_TYPE_APPLE_BRICK_ID = 11,\n\tPOWER_SUPPLY_TYPE_WIRELESS = 12,\n};\n\nenum power_supply_usb_type {\n\tPOWER_SUPPLY_USB_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_USB_TYPE_SDP = 1,\n\tPOWER_SUPPLY_USB_TYPE_DCP = 2,\n\tPOWER_SUPPLY_USB_TYPE_CDP = 3,\n\tPOWER_SUPPLY_USB_TYPE_ACA = 4,\n\tPOWER_SUPPLY_USB_TYPE_C = 5,\n\tPOWER_SUPPLY_USB_TYPE_PD = 6,\n\tPOWER_SUPPLY_USB_TYPE_PD_DRP = 7,\n\tPOWER_SUPPLY_USB_TYPE_PD_PPS = 8,\n\tPOWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID = 9,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum prcm_gpiocr_altcx_index {\n\tPRCM_IDX_GPIOCR_ALTC1 = 0,\n\tPRCM_IDX_GPIOCR_ALTC2 = 1,\n\tPRCM_IDX_GPIOCR_ALTC3 = 2,\n\tPRCM_IDX_GPIOCR_ALTC4 = 3,\n\tPRCM_IDX_GPIOCR_ALTC_MAX = 4,\n};\n\nenum prcm_gpiocr_reg_index {\n\tPRCM_IDX_GPIOCR1 = 0,\n\tPRCM_IDX_GPIOCR2 = 1,\n\tPRCM_IDX_GPIOCR3 = 2,\n};\n\nenum prcmu_wakeup_index {\n\tPRCMU_WAKEUP_INDEX_RTC = 0,\n\tPRCMU_WAKEUP_INDEX_RTT0 = 1,\n\tPRCMU_WAKEUP_INDEX_RTT1 = 2,\n\tPRCMU_WAKEUP_INDEX_HSI0 = 3,\n\tPRCMU_WAKEUP_INDEX_HSI1 = 4,\n\tPRCMU_WAKEUP_INDEX_USB = 5,\n\tPRCMU_WAKEUP_INDEX_ABB = 6,\n\tPRCMU_WAKEUP_INDEX_ABB_FIFO = 7,\n\tPRCMU_WAKEUP_INDEX_ARM = 8,\n\tPRCMU_WAKEUP_INDEX_CD_IRQ = 9,\n\tNUM_PRCMU_WAKEUP_INDICES = 10,\n};\n\nenum prcmu_wdog_id {\n\tPRCMU_WDOG_ALL = 0,\n\tPRCMU_WDOG_CPU1 = 1,\n\tPRCMU_WDOG_CPU2 = 2,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_print_type {\n\tPROBE_PRINT_NORMAL = 0,\n\tPROBE_PRINT_RETURN = 1,\n\tPROBE_PRINT_EVENT = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum probes_arm_action {\n\tPROBES_PRELOAD_IMM = 0,\n\tPROBES_PRELOAD_REG = 1,\n\tPROBES_BRANCH_IMM = 2,\n\tPROBES_BRANCH_REG = 3,\n\tPROBES_MRS = 4,\n\tPROBES_CLZ = 5,\n\tPROBES_SATURATING_ARITHMETIC = 6,\n\tPROBES_MUL1 = 7,\n\tPROBES_MUL2 = 8,\n\tPROBES_SWP = 9,\n\tPROBES_LDRSTRD = 10,\n\tPROBES_LOAD = 11,\n\tPROBES_STORE = 12,\n\tPROBES_LOAD_EXTRA = 13,\n\tPROBES_STORE_EXTRA = 14,\n\tPROBES_MOV_IP_SP = 15,\n\tPROBES_DATA_PROCESSING_REG = 16,\n\tPROBES_DATA_PROCESSING_IMM = 17,\n\tPROBES_MOV_HALFWORD = 18,\n\tPROBES_SEV = 19,\n\tPROBES_WFE = 20,\n\tPROBES_SATURATE = 21,\n\tPROBES_REV = 22,\n\tPROBES_MMI = 23,\n\tPROBES_PACK = 24,\n\tPROBES_EXTEND = 25,\n\tPROBES_EXTEND_ADD = 26,\n\tPROBES_MUL_ADD_LONG = 27,\n\tPROBES_MUL_ADD = 28,\n\tPROBES_BITFIELD = 29,\n\tPROBES_BRANCH = 30,\n\tPROBES_LDMSTM = 31,\n\tNUM_PROBES_ARM_ACTIONS = 32,\n};\n\nenum probes_insn {\n\tINSN_REJECTED = 0,\n\tINSN_GOOD = 1,\n\tINSN_GOOD_NO_SLOT = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___7 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum ps2_disposition {\n\tPS2_PROCESS = 0,\n\tPS2_IGNORE = 1,\n\tPS2_ERROR = 2,\n};\n\nenum ps2_subcmds {\n\tSEND_COMMAND = 1,\n\tRECEIVE_N = 2,\n\tAUTO_RECEIVE_N = 3,\n\tCANCEL_AUTO_RECEIVE = 4,\n};\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nenum pstore_type_id {\n\tPSTORE_TYPE_DMESG = 0,\n\tPSTORE_TYPE_MCE = 1,\n\tPSTORE_TYPE_CONSOLE = 2,\n\tPSTORE_TYPE_FTRACE = 3,\n\tPSTORE_TYPE_PPC_RTAS = 4,\n\tPSTORE_TYPE_PPC_OF = 5,\n\tPSTORE_TYPE_PPC_COMMON = 6,\n\tPSTORE_TYPE_PMSG = 7,\n\tPSTORE_TYPE_PPC_OPAL = 8,\n\tPSTORE_TYPE_MAX = 9,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_EXTOFF = 2,\n\tPTP_CLOCK_PPS = 3,\n\tPTP_CLOCK_PPSUSR = 4,\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nenum ptrace_syscall_dir {\n\tPTRACE_SYSCALL_ENTER = 0,\n\tPTRACE_SYSCALL_EXIT = 1,\n};\n\nenum pud_index {\n\tPUD_PULL_DISABLE = 0,\n\tPUD_PULL_DOWN = 1,\n\tPUD_PULL_UP = 2,\n\tPUD_MAX = 3,\n};\n\nenum pwm_polarity {\n\tPWM_POLARITY_NORMAL = 0,\n\tPWM_POLARITY_INVERSED = 1,\n};\n\nenum pxa_gpio_type {\n\tPXA25X_GPIO = 0,\n\tPXA26X_GPIO = 1,\n\tPXA27X_GPIO = 2,\n\tPXA3XX_GPIO = 3,\n\tPXA93X_GPIO = 4,\n\tMMP_GPIO = 16,\n\tMMP2_GPIO = 17,\n\tPXA1928_GPIO = 18,\n};\n\nenum qcom_icc_type {\n\tQCOM_ICC_NOC = 0,\n\tQCOM_ICC_BIMC = 1,\n\tQCOM_ICC_QNOC = 2,\n};\n\nenum qcom_iommu_clk {\n\tCLK_IFACE = 0,\n\tCLK_BUS = 1,\n\tCLK_TBU = 2,\n\tCLK_NUM = 3,\n};\n\nenum qcom_scm_arg_types {\n\tQCOM_SCM_VAL = 0,\n\tQCOM_SCM_RO = 1,\n\tQCOM_SCM_RW = 2,\n\tQCOM_SCM_BUFVAL = 3,\n};\n\nenum qcom_scm_convention {\n\tSMC_CONVENTION_UNKNOWN = 0,\n\tSMC_CONVENTION_LEGACY = 1,\n\tSMC_CONVENTION_ARM_32 = 2,\n\tSMC_CONVENTION_ARM_64 = 3,\n};\n\nenum qcom_scm_ice_cipher {\n\tQCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,\n\tQCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,\n\tQCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,\n\tQCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,\n};\n\nenum qcom_scm_ocmem_client {\n\tQCOM_SCM_OCMEM_UNUSED_ID = 0,\n\tQCOM_SCM_OCMEM_GRAPHICS_ID = 1,\n\tQCOM_SCM_OCMEM_VIDEO_ID = 2,\n\tQCOM_SCM_OCMEM_LP_AUDIO_ID = 3,\n\tQCOM_SCM_OCMEM_SENSORS_ID = 4,\n\tQCOM_SCM_OCMEM_OTHER_OS_ID = 5,\n\tQCOM_SCM_OCMEM_DEBUG_ID = 6,\n};\n\nenum qcom_socinfo_feature_code {\n\tSOCINFO_FC_UNKNOWN = 0,\n\tSOCINFO_FC_AA = 1,\n\tSOCINFO_FC_AB = 2,\n\tSOCINFO_FC_AC = 3,\n\tSOCINFO_FC_AD = 4,\n\tSOCINFO_FC_AE = 5,\n\tSOCINFO_FC_AF = 6,\n\tSOCINFO_FC_AG = 7,\n\tSOCINFO_FC_AH = 8,\n};\n\nenum qcom_tzmem_policy {\n\tQCOM_TZMEM_POLICY_STATIC = 1,\n\tQCOM_TZMEM_POLICY_MULTIPLIER = 2,\n\tQCOM_TZMEM_POLICY_ON_DEMAND = 3,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum qmss_version {\n\tQMSS = 0,\n\tQMSS_66AK2G = 1,\n};\n\nenum qos_mode {\n\tNOC_QOS_MODE_INVALID = 0,\n\tNOC_QOS_MODE_FIXED = 1,\n\tNOC_QOS_MODE_BYPASS = 2,\n};\n\nenum qpnpint_regs {\n\tQPNPINT_REG_RT_STS = 16,\n\tQPNPINT_REG_SET_TYPE = 17,\n\tQPNPINT_REG_POLARITY_HIGH = 18,\n\tQPNPINT_REG_POLARITY_LOW = 19,\n\tQPNPINT_REG_LATCHED_CLR = 20,\n\tQPNPINT_REG_EN_SET = 21,\n\tQPNPINT_REG_EN_CLR = 22,\n\tQPNPINT_REG_LATCHED_STS = 24,\n};\n\nenum queue_mode {\n\tQUEUE_MODE_STRICT_PRIORITY = 0,\n\tQUEUE_MODE_STREAM_RESERVATION = 1,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum ramfs_param {\n\tOpt_mode___4 = 0,\n};\n\nenum ravb_reg {\n\tCCC = 0,\n\tDBAT = 4,\n\tDLR = 8,\n\tCSR___2 = 12,\n\tCDAR0 = 16,\n\tCDAR1 = 20,\n\tCDAR2 = 24,\n\tCDAR3 = 28,\n\tCDAR4 = 32,\n\tCDAR5 = 36,\n\tCDAR6 = 40,\n\tCDAR7 = 44,\n\tCDAR8 = 48,\n\tCDAR9 = 52,\n\tCDAR10 = 56,\n\tCDAR11 = 60,\n\tCDAR12 = 64,\n\tCDAR13 = 68,\n\tCDAR14 = 72,\n\tCDAR15 = 76,\n\tCDAR16 = 80,\n\tCDAR17 = 84,\n\tCDAR18 = 88,\n\tCDAR19 = 92,\n\tCDAR20 = 96,\n\tCDAR21 = 100,\n\tESR = 136,\n\tAPSR = 140,\n\tRCR = 144,\n\tRQC0 = 148,\n\tRQC1 = 152,\n\tRQC2 = 156,\n\tRQC3 = 160,\n\tRQC4 = 164,\n\tRPC = 176,\n\tRTC = 180,\n\tUFCW = 188,\n\tUFCS = 192,\n\tUFCV0 = 196,\n\tUFCV1 = 200,\n\tUFCV2 = 204,\n\tUFCV3 = 208,\n\tUFCV4 = 212,\n\tUFCD0 = 224,\n\tUFCD1 = 228,\n\tUFCD2 = 232,\n\tUFCD3 = 236,\n\tUFCD4 = 240,\n\tSFO = 252,\n\tSFP0 = 256,\n\tSFP1 = 260,\n\tSFP2 = 264,\n\tSFP3 = 268,\n\tSFP4 = 272,\n\tSFP5 = 276,\n\tSFP6 = 280,\n\tSFP7 = 284,\n\tSFP8 = 288,\n\tSFP9 = 292,\n\tSFP10 = 296,\n\tSFP11 = 300,\n\tSFP12 = 304,\n\tSFP13 = 308,\n\tSFP14 = 312,\n\tSFP15 = 316,\n\tSFP16 = 320,\n\tSFP17 = 324,\n\tSFP18 = 328,\n\tSFP19 = 332,\n\tSFP20 = 336,\n\tSFP21 = 340,\n\tSFP22 = 344,\n\tSFP23 = 348,\n\tSFP24 = 352,\n\tSFP25 = 356,\n\tSFP26 = 360,\n\tSFP27 = 364,\n\tSFP28 = 368,\n\tSFP29 = 372,\n\tSFP30 = 376,\n\tSFP31 = 380,\n\tSFM0 = 448,\n\tSFM1 = 452,\n\tTGC = 768,\n\tTCCR = 772,\n\tTSR = 776,\n\tTFA0 = 784,\n\tTFA1 = 788,\n\tTFA2 = 792,\n\tCIVR0 = 800,\n\tCIVR1 = 804,\n\tCDVR0 = 808,\n\tCDVR1 = 812,\n\tCUL0 = 816,\n\tCUL1 = 820,\n\tCLL0 = 824,\n\tCLL1 = 828,\n\tDIC = 848,\n\tDIS = 852,\n\tEIC = 856,\n\tEIS = 860,\n\tRIC0 = 864,\n\tRIS0 = 868,\n\tRIC1 = 872,\n\tRIS1 = 876,\n\tRIC2 = 880,\n\tRIS2 = 884,\n\tTIC = 888,\n\tTIS = 892,\n\tISS = 896,\n\tCIE = 900,\n\tGCCR = 912,\n\tGMTT = 916,\n\tGPTC = 920,\n\tGTI = 924,\n\tGTO0 = 928,\n\tGTO1 = 932,\n\tGTO2 = 936,\n\tGIC = 940,\n\tGIS = 944,\n\tGCPT = 948,\n\tGCT0 = 952,\n\tGCT1 = 956,\n\tGCT2 = 960,\n\tGIE = 972,\n\tGID = 976,\n\tDIL = 1088,\n\tRIE0 = 1120,\n\tRID0 = 1124,\n\tRIE2 = 1136,\n\tRID2 = 1140,\n\tTIE = 1144,\n\tTID = 1148,\n\tECMR___2 = 1280,\n\tRFLR___2 = 1288,\n\tECSR___2 = 1296,\n\tECSIPR___2 = 1304,\n\tPIR___2 = 1312,\n\tPSR___2 = 1320,\n\tPIPR___2 = 1324,\n\tCXR31 = 1328,\n\tCXR35 = 1344,\n\tMPR___2 = 1368,\n\tPFTCR___2 = 1372,\n\tPFRCR___2 = 1376,\n\tGECMR___2 = 1456,\n\tMAHR___2 = 1472,\n\tMALR___2 = 1480,\n\tTROCR___2 = 1792,\n\tCXR41 = 1800,\n\tCXR42 = 1808,\n\tCEFCR___2 = 1856,\n\tFRECR___2 = 1864,\n\tTSFRCR___2 = 1872,\n\tTLFRCR___2 = 1880,\n\tRFCR___2 = 1888,\n\tMAFCR___2 = 1912,\n\tCSR0 = 2048,\n\tCSR1 = 2052,\n\tCSR2 = 2056,\n};\n\nenum rc_driver_type {\n\tRC_DRIVER_SCANCODE = 0,\n\tRC_DRIVER_IR_RAW = 1,\n\tRC_DRIVER_IR_RAW_TX = 2,\n};\n\nenum rc_proto {\n\tRC_PROTO_UNKNOWN = 0,\n\tRC_PROTO_OTHER = 1,\n\tRC_PROTO_RC5 = 2,\n\tRC_PROTO_RC5X_20 = 3,\n\tRC_PROTO_RC5_SZ = 4,\n\tRC_PROTO_JVC = 5,\n\tRC_PROTO_SONY12 = 6,\n\tRC_PROTO_SONY15 = 7,\n\tRC_PROTO_SONY20 = 8,\n\tRC_PROTO_NEC = 9,\n\tRC_PROTO_NECX = 10,\n\tRC_PROTO_NEC32 = 11,\n\tRC_PROTO_SANYO = 12,\n\tRC_PROTO_MCIR2_KBD = 13,\n\tRC_PROTO_MCIR2_MSE = 14,\n\tRC_PROTO_RC6_0 = 15,\n\tRC_PROTO_RC6_6A_20 = 16,\n\tRC_PROTO_RC6_6A_24 = 17,\n\tRC_PROTO_RC6_6A_32 = 18,\n\tRC_PROTO_RC6_MCE = 19,\n\tRC_PROTO_SHARP = 20,\n\tRC_PROTO_XMP = 21,\n\tRC_PROTO_CEC = 22,\n\tRC_PROTO_IMON = 23,\n\tRC_PROTO_RCMM12 = 24,\n\tRC_PROTO_RCMM24 = 25,\n\tRC_PROTO_RCMM32 = 26,\n\tRC_PROTO_XBOX_DVD = 27,\n\tRC_PROTO_MAX = 27,\n};\n\nenum rcar_gen2_clk_types {\n\tCLK_TYPE_GEN2_MAIN = 5,\n\tCLK_TYPE_GEN2_PLL0 = 6,\n\tCLK_TYPE_GEN2_PLL1 = 7,\n\tCLK_TYPE_GEN2_PLL3 = 8,\n\tCLK_TYPE_GEN2_Z = 9,\n\tCLK_TYPE_GEN2_LB = 10,\n\tCLK_TYPE_GEN2_ADSP = 11,\n\tCLK_TYPE_GEN2_SDH = 12,\n\tCLK_TYPE_GEN2_SD0 = 13,\n\tCLK_TYPE_GEN2_SD1 = 14,\n\tCLK_TYPE_GEN2_QSPI = 15,\n\tCLK_TYPE_GEN2_RCAN = 16,\n};\n\nenum rcar_i2c_type {\n\tI2C_RCAR_GEN1 = 0,\n\tI2C_RCAR_GEN2 = 1,\n\tI2C_RCAR_GEN3 = 2,\n\tI2C_RCAR_GEN4 = 3,\n};\n\nenum rdma_ah_attr_type {\n\tRDMA_AH_ATTR_TYPE_UNDEFINED = 0,\n\tRDMA_AH_ATTR_TYPE_IB = 1,\n\tRDMA_AH_ATTR_TYPE_ROCE = 2,\n\tRDMA_AH_ATTR_TYPE_OPA = 3,\n};\n\nenum rdma_driver_id {\n\tRDMA_DRIVER_UNKNOWN = 0,\n\tRDMA_DRIVER_MLX5 = 1,\n\tRDMA_DRIVER_MLX4 = 2,\n\tRDMA_DRIVER_CXGB3 = 3,\n\tRDMA_DRIVER_CXGB4 = 4,\n\tRDMA_DRIVER_MTHCA = 5,\n\tRDMA_DRIVER_BNXT_RE = 6,\n\tRDMA_DRIVER_OCRDMA = 7,\n\tRDMA_DRIVER_NES = 8,\n\tRDMA_DRIVER_I40IW = 9,\n\tRDMA_DRIVER_IRDMA = 9,\n\tRDMA_DRIVER_VMW_PVRDMA = 10,\n\tRDMA_DRIVER_QEDR = 11,\n\tRDMA_DRIVER_HNS = 12,\n\tRDMA_DRIVER_USNIC = 13,\n\tRDMA_DRIVER_RXE = 14,\n\tRDMA_DRIVER_HFI1 = 15,\n\tRDMA_DRIVER_QIB = 16,\n\tRDMA_DRIVER_EFA = 17,\n\tRDMA_DRIVER_SIW = 18,\n\tRDMA_DRIVER_ERDMA = 19,\n\tRDMA_DRIVER_MANA = 20,\n\tRDMA_DRIVER_IONIC = 21,\n};\n\nenum rdma_link_layer {\n\tIB_LINK_LAYER_UNSPECIFIED = 0,\n\tIB_LINK_LAYER_INFINIBAND = 1,\n\tIB_LINK_LAYER_ETHERNET = 2,\n};\n\nenum rdma_netdev_t {\n\tRDMA_NETDEV_OPA_VNIC = 0,\n\tRDMA_NETDEV_IPOIB = 1,\n};\n\nenum rdma_nl_counter_mask {\n\tRDMA_COUNTER_MASK_QP_TYPE = 1,\n\tRDMA_COUNTER_MASK_PID = 2,\n};\n\nenum rdma_nl_counter_mode {\n\tRDMA_COUNTER_MODE_NONE = 0,\n\tRDMA_COUNTER_MODE_AUTO = 1,\n\tRDMA_COUNTER_MODE_MANUAL = 2,\n\tRDMA_COUNTER_MODE_MAX = 3,\n};\n\nenum rdma_nl_dev_type {\n\tRDMA_DEVICE_TYPE_SMI = 1,\n};\n\nenum rdma_nl_name_assign_type {\n\tRDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0,\n\tRDMA_NAME_ASSIGN_TYPE_USER = 1,\n};\n\nenum rdma_restrack_type {\n\tRDMA_RESTRACK_PD = 0,\n\tRDMA_RESTRACK_CQ = 1,\n\tRDMA_RESTRACK_QP = 2,\n\tRDMA_RESTRACK_CM_ID = 3,\n\tRDMA_RESTRACK_MR = 4,\n\tRDMA_RESTRACK_CTX = 5,\n\tRDMA_RESTRACK_COUNTER = 6,\n\tRDMA_RESTRACK_SRQ = 7,\n\tRDMA_RESTRACK_DMAH = 8,\n\tRDMA_RESTRACK_MAX = 9,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_FLAT = 2,\n\tREGCACHE_MAPLE = 3,\n\tREGCACHE_FLAT_S = 4,\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum regfield_ids {\n\tVER_MAJOR = 0,\n\tVER_MINOR = 1,\n\tVER_STEP = 2,\n\tTSENS_EN = 3,\n\tTSENS_SW_RST = 4,\n\tSENSOR_EN = 5,\n\tCODE_OR_TEMP = 6,\n\tMAIN_MEASURE_PERIOD = 7,\n\tTRDY = 8,\n\tINT_EN = 9,\n\tLAST_TEMP_0 = 10,\n\tLAST_TEMP_1 = 11,\n\tLAST_TEMP_2 = 12,\n\tLAST_TEMP_3 = 13,\n\tLAST_TEMP_4 = 14,\n\tLAST_TEMP_5 = 15,\n\tLAST_TEMP_6 = 16,\n\tLAST_TEMP_7 = 17,\n\tLAST_TEMP_8 = 18,\n\tLAST_TEMP_9 = 19,\n\tLAST_TEMP_10 = 20,\n\tLAST_TEMP_11 = 21,\n\tLAST_TEMP_12 = 22,\n\tLAST_TEMP_13 = 23,\n\tLAST_TEMP_14 = 24,\n\tLAST_TEMP_15 = 25,\n\tVALID_0 = 26,\n\tVALID_1 = 27,\n\tVALID_2 = 28,\n\tVALID_3 = 29,\n\tVALID_4 = 30,\n\tVALID_5 = 31,\n\tVALID_6 = 32,\n\tVALID_7 = 33,\n\tVALID_8 = 34,\n\tVALID_9 = 35,\n\tVALID_10 = 36,\n\tVALID_11 = 37,\n\tVALID_12 = 38,\n\tVALID_13 = 39,\n\tVALID_14 = 40,\n\tVALID_15 = 41,\n\tLOWER_STATUS_0 = 42,\n\tLOWER_STATUS_1 = 43,\n\tLOWER_STATUS_2 = 44,\n\tLOWER_STATUS_3 = 45,\n\tLOWER_STATUS_4 = 46,\n\tLOWER_STATUS_5 = 47,\n\tLOWER_STATUS_6 = 48,\n\tLOWER_STATUS_7 = 49,\n\tLOWER_STATUS_8 = 50,\n\tLOWER_STATUS_9 = 51,\n\tLOWER_STATUS_10 = 52,\n\tLOWER_STATUS_11 = 53,\n\tLOWER_STATUS_12 = 54,\n\tLOWER_STATUS_13 = 55,\n\tLOWER_STATUS_14 = 56,\n\tLOWER_STATUS_15 = 57,\n\tLOW_INT_STATUS_0 = 58,\n\tLOW_INT_STATUS_1 = 59,\n\tLOW_INT_STATUS_2 = 60,\n\tLOW_INT_STATUS_3 = 61,\n\tLOW_INT_STATUS_4 = 62,\n\tLOW_INT_STATUS_5 = 63,\n\tLOW_INT_STATUS_6 = 64,\n\tLOW_INT_STATUS_7 = 65,\n\tLOW_INT_STATUS_8 = 66,\n\tLOW_INT_STATUS_9 = 67,\n\tLOW_INT_STATUS_10 = 68,\n\tLOW_INT_STATUS_11 = 69,\n\tLOW_INT_STATUS_12 = 70,\n\tLOW_INT_STATUS_13 = 71,\n\tLOW_INT_STATUS_14 = 72,\n\tLOW_INT_STATUS_15 = 73,\n\tLOW_INT_CLEAR_0 = 74,\n\tLOW_INT_CLEAR_1 = 75,\n\tLOW_INT_CLEAR_2 = 76,\n\tLOW_INT_CLEAR_3 = 77,\n\tLOW_INT_CLEAR_4 = 78,\n\tLOW_INT_CLEAR_5 = 79,\n\tLOW_INT_CLEAR_6 = 80,\n\tLOW_INT_CLEAR_7 = 81,\n\tLOW_INT_CLEAR_8 = 82,\n\tLOW_INT_CLEAR_9 = 83,\n\tLOW_INT_CLEAR_10 = 84,\n\tLOW_INT_CLEAR_11 = 85,\n\tLOW_INT_CLEAR_12 = 86,\n\tLOW_INT_CLEAR_13 = 87,\n\tLOW_INT_CLEAR_14 = 88,\n\tLOW_INT_CLEAR_15 = 89,\n\tLOW_INT_MASK_0 = 90,\n\tLOW_INT_MASK_1 = 91,\n\tLOW_INT_MASK_2 = 92,\n\tLOW_INT_MASK_3 = 93,\n\tLOW_INT_MASK_4 = 94,\n\tLOW_INT_MASK_5 = 95,\n\tLOW_INT_MASK_6 = 96,\n\tLOW_INT_MASK_7 = 97,\n\tLOW_INT_MASK_8 = 98,\n\tLOW_INT_MASK_9 = 99,\n\tLOW_INT_MASK_10 = 100,\n\tLOW_INT_MASK_11 = 101,\n\tLOW_INT_MASK_12 = 102,\n\tLOW_INT_MASK_13 = 103,\n\tLOW_INT_MASK_14 = 104,\n\tLOW_INT_MASK_15 = 105,\n\tLOW_THRESH_0 = 106,\n\tLOW_THRESH_1 = 107,\n\tLOW_THRESH_2 = 108,\n\tLOW_THRESH_3 = 109,\n\tLOW_THRESH_4 = 110,\n\tLOW_THRESH_5 = 111,\n\tLOW_THRESH_6 = 112,\n\tLOW_THRESH_7 = 113,\n\tLOW_THRESH_8 = 114,\n\tLOW_THRESH_9 = 115,\n\tLOW_THRESH_10 = 116,\n\tLOW_THRESH_11 = 117,\n\tLOW_THRESH_12 = 118,\n\tLOW_THRESH_13 = 119,\n\tLOW_THRESH_14 = 120,\n\tLOW_THRESH_15 = 121,\n\tUPPER_STATUS_0 = 122,\n\tUPPER_STATUS_1 = 123,\n\tUPPER_STATUS_2 = 124,\n\tUPPER_STATUS_3 = 125,\n\tUPPER_STATUS_4 = 126,\n\tUPPER_STATUS_5 = 127,\n\tUPPER_STATUS_6 = 128,\n\tUPPER_STATUS_7 = 129,\n\tUPPER_STATUS_8 = 130,\n\tUPPER_STATUS_9 = 131,\n\tUPPER_STATUS_10 = 132,\n\tUPPER_STATUS_11 = 133,\n\tUPPER_STATUS_12 = 134,\n\tUPPER_STATUS_13 = 135,\n\tUPPER_STATUS_14 = 136,\n\tUPPER_STATUS_15 = 137,\n\tUP_INT_STATUS_0 = 138,\n\tUP_INT_STATUS_1 = 139,\n\tUP_INT_STATUS_2 = 140,\n\tUP_INT_STATUS_3 = 141,\n\tUP_INT_STATUS_4 = 142,\n\tUP_INT_STATUS_5 = 143,\n\tUP_INT_STATUS_6 = 144,\n\tUP_INT_STATUS_7 = 145,\n\tUP_INT_STATUS_8 = 146,\n\tUP_INT_STATUS_9 = 147,\n\tUP_INT_STATUS_10 = 148,\n\tUP_INT_STATUS_11 = 149,\n\tUP_INT_STATUS_12 = 150,\n\tUP_INT_STATUS_13 = 151,\n\tUP_INT_STATUS_14 = 152,\n\tUP_INT_STATUS_15 = 153,\n\tUP_INT_CLEAR_0 = 154,\n\tUP_INT_CLEAR_1 = 155,\n\tUP_INT_CLEAR_2 = 156,\n\tUP_INT_CLEAR_3 = 157,\n\tUP_INT_CLEAR_4 = 158,\n\tUP_INT_CLEAR_5 = 159,\n\tUP_INT_CLEAR_6 = 160,\n\tUP_INT_CLEAR_7 = 161,\n\tUP_INT_CLEAR_8 = 162,\n\tUP_INT_CLEAR_9 = 163,\n\tUP_INT_CLEAR_10 = 164,\n\tUP_INT_CLEAR_11 = 165,\n\tUP_INT_CLEAR_12 = 166,\n\tUP_INT_CLEAR_13 = 167,\n\tUP_INT_CLEAR_14 = 168,\n\tUP_INT_CLEAR_15 = 169,\n\tUP_INT_MASK_0 = 170,\n\tUP_INT_MASK_1 = 171,\n\tUP_INT_MASK_2 = 172,\n\tUP_INT_MASK_3 = 173,\n\tUP_INT_MASK_4 = 174,\n\tUP_INT_MASK_5 = 175,\n\tUP_INT_MASK_6 = 176,\n\tUP_INT_MASK_7 = 177,\n\tUP_INT_MASK_8 = 178,\n\tUP_INT_MASK_9 = 179,\n\tUP_INT_MASK_10 = 180,\n\tUP_INT_MASK_11 = 181,\n\tUP_INT_MASK_12 = 182,\n\tUP_INT_MASK_13 = 183,\n\tUP_INT_MASK_14 = 184,\n\tUP_INT_MASK_15 = 185,\n\tUP_THRESH_0 = 186,\n\tUP_THRESH_1 = 187,\n\tUP_THRESH_2 = 188,\n\tUP_THRESH_3 = 189,\n\tUP_THRESH_4 = 190,\n\tUP_THRESH_5 = 191,\n\tUP_THRESH_6 = 192,\n\tUP_THRESH_7 = 193,\n\tUP_THRESH_8 = 194,\n\tUP_THRESH_9 = 195,\n\tUP_THRESH_10 = 196,\n\tUP_THRESH_11 = 197,\n\tUP_THRESH_12 = 198,\n\tUP_THRESH_13 = 199,\n\tUP_THRESH_14 = 200,\n\tUP_THRESH_15 = 201,\n\tCRITICAL_STATUS_0 = 202,\n\tCRITICAL_STATUS_1 = 203,\n\tCRITICAL_STATUS_2 = 204,\n\tCRITICAL_STATUS_3 = 205,\n\tCRITICAL_STATUS_4 = 206,\n\tCRITICAL_STATUS_5 = 207,\n\tCRITICAL_STATUS_6 = 208,\n\tCRITICAL_STATUS_7 = 209,\n\tCRITICAL_STATUS_8 = 210,\n\tCRITICAL_STATUS_9 = 211,\n\tCRITICAL_STATUS_10 = 212,\n\tCRITICAL_STATUS_11 = 213,\n\tCRITICAL_STATUS_12 = 214,\n\tCRITICAL_STATUS_13 = 215,\n\tCRITICAL_STATUS_14 = 216,\n\tCRITICAL_STATUS_15 = 217,\n\tCRIT_INT_STATUS_0 = 218,\n\tCRIT_INT_STATUS_1 = 219,\n\tCRIT_INT_STATUS_2 = 220,\n\tCRIT_INT_STATUS_3 = 221,\n\tCRIT_INT_STATUS_4 = 222,\n\tCRIT_INT_STATUS_5 = 223,\n\tCRIT_INT_STATUS_6 = 224,\n\tCRIT_INT_STATUS_7 = 225,\n\tCRIT_INT_STATUS_8 = 226,\n\tCRIT_INT_STATUS_9 = 227,\n\tCRIT_INT_STATUS_10 = 228,\n\tCRIT_INT_STATUS_11 = 229,\n\tCRIT_INT_STATUS_12 = 230,\n\tCRIT_INT_STATUS_13 = 231,\n\tCRIT_INT_STATUS_14 = 232,\n\tCRIT_INT_STATUS_15 = 233,\n\tCRIT_INT_CLEAR_0 = 234,\n\tCRIT_INT_CLEAR_1 = 235,\n\tCRIT_INT_CLEAR_2 = 236,\n\tCRIT_INT_CLEAR_3 = 237,\n\tCRIT_INT_CLEAR_4 = 238,\n\tCRIT_INT_CLEAR_5 = 239,\n\tCRIT_INT_CLEAR_6 = 240,\n\tCRIT_INT_CLEAR_7 = 241,\n\tCRIT_INT_CLEAR_8 = 242,\n\tCRIT_INT_CLEAR_9 = 243,\n\tCRIT_INT_CLEAR_10 = 244,\n\tCRIT_INT_CLEAR_11 = 245,\n\tCRIT_INT_CLEAR_12 = 246,\n\tCRIT_INT_CLEAR_13 = 247,\n\tCRIT_INT_CLEAR_14 = 248,\n\tCRIT_INT_CLEAR_15 = 249,\n\tCRIT_INT_MASK_0 = 250,\n\tCRIT_INT_MASK_1 = 251,\n\tCRIT_INT_MASK_2 = 252,\n\tCRIT_INT_MASK_3 = 253,\n\tCRIT_INT_MASK_4 = 254,\n\tCRIT_INT_MASK_5 = 255,\n\tCRIT_INT_MASK_6 = 256,\n\tCRIT_INT_MASK_7 = 257,\n\tCRIT_INT_MASK_8 = 258,\n\tCRIT_INT_MASK_9 = 259,\n\tCRIT_INT_MASK_10 = 260,\n\tCRIT_INT_MASK_11 = 261,\n\tCRIT_INT_MASK_12 = 262,\n\tCRIT_INT_MASK_13 = 263,\n\tCRIT_INT_MASK_14 = 264,\n\tCRIT_INT_MASK_15 = 265,\n\tCRIT_THRESH_0 = 266,\n\tCRIT_THRESH_1 = 267,\n\tCRIT_THRESH_2 = 268,\n\tCRIT_THRESH_3 = 269,\n\tCRIT_THRESH_4 = 270,\n\tCRIT_THRESH_5 = 271,\n\tCRIT_THRESH_6 = 272,\n\tCRIT_THRESH_7 = 273,\n\tCRIT_THRESH_8 = 274,\n\tCRIT_THRESH_9 = 275,\n\tCRIT_THRESH_10 = 276,\n\tCRIT_THRESH_11 = 277,\n\tCRIT_THRESH_12 = 278,\n\tCRIT_THRESH_13 = 279,\n\tCRIT_THRESH_14 = 280,\n\tCRIT_THRESH_15 = 281,\n\tWDOG_BARK_STATUS = 282,\n\tWDOG_BARK_CLEAR = 283,\n\tWDOG_BARK_MASK = 284,\n\tWDOG_BARK_COUNT = 285,\n\tCC_MON_STATUS = 286,\n\tCC_MON_CLEAR = 287,\n\tCC_MON_MASK = 288,\n\tMIN_STATUS_0 = 289,\n\tMIN_STATUS_1 = 290,\n\tMIN_STATUS_2 = 291,\n\tMIN_STATUS_3 = 292,\n\tMIN_STATUS_4 = 293,\n\tMIN_STATUS_5 = 294,\n\tMIN_STATUS_6 = 295,\n\tMIN_STATUS_7 = 296,\n\tMIN_STATUS_8 = 297,\n\tMIN_STATUS_9 = 298,\n\tMIN_STATUS_10 = 299,\n\tMIN_STATUS_11 = 300,\n\tMIN_STATUS_12 = 301,\n\tMIN_STATUS_13 = 302,\n\tMIN_STATUS_14 = 303,\n\tMIN_STATUS_15 = 304,\n\tMAX_STATUS_0 = 305,\n\tMAX_STATUS_1 = 306,\n\tMAX_STATUS_2 = 307,\n\tMAX_STATUS_3 = 308,\n\tMAX_STATUS_4 = 309,\n\tMAX_STATUS_5 = 310,\n\tMAX_STATUS_6 = 311,\n\tMAX_STATUS_7 = 312,\n\tMAX_STATUS_8 = 313,\n\tMAX_STATUS_9 = 314,\n\tMAX_STATUS_10 = 315,\n\tMAX_STATUS_11 = 316,\n\tMAX_STATUS_12 = 317,\n\tMAX_STATUS_13 = 318,\n\tMAX_STATUS_14 = 319,\n\tMAX_STATUS_15 = 320,\n\tMAX_REGFIELDS___2 = 321,\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nenum regs {\n\tFP = 11,\n\tSP = 13,\n\tLR = 14,\n\tPC = 15,\n};\n\nenum regulator_active_discharge {\n\tREGULATOR_ACTIVE_DISCHARGE_DEFAULT = 0,\n\tREGULATOR_ACTIVE_DISCHARGE_DISABLE = 1,\n\tREGULATOR_ACTIVE_DISCHARGE_ENABLE = 2,\n};\n\nenum regulator_detection_severity {\n\tREGULATOR_SEVERITY_PROT = 0,\n\tREGULATOR_SEVERITY_ERR = 1,\n\tREGULATOR_SEVERITY_WARN = 2,\n};\n\nenum regulator_get_type {\n\tNORMAL_GET = 0,\n\tEXCLUSIVE_GET = 1,\n\tOPTIONAL_GET = 2,\n\tMAX_GET_TYPE = 3,\n};\n\nenum regulator_status {\n\tREGULATOR_STATUS_OFF = 0,\n\tREGULATOR_STATUS_ON = 1,\n\tREGULATOR_STATUS_ERROR = 2,\n\tREGULATOR_STATUS_FAST = 3,\n\tREGULATOR_STATUS_NORMAL = 4,\n\tREGULATOR_STATUS_IDLE = 5,\n\tREGULATOR_STATUS_STANDBY = 6,\n\tREGULATOR_STATUS_BYPASS = 7,\n\tREGULATOR_STATUS_UNDEFINED = 8,\n};\n\nenum regulator_type {\n\tREGULATOR_VOLTAGE = 0,\n\tREGULATOR_CURRENT = 1,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum renesas_sdhi_dma_cookie {\n\tCOOKIE_UNMAPPED___2 = 0,\n\tCOOKIE_PRE_MAPPED___2 = 1,\n\tCOOKIE_MAPPED___2 = 2,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum request_irq_err {\n\tREQ_IRQ_ERR_ALL = 0,\n\tREQ_IRQ_ERR_TX = 1,\n\tREQ_IRQ_ERR_RX = 2,\n\tREQ_IRQ_ERR_SFTY = 3,\n\tREQ_IRQ_ERR_SFTY_UE = 4,\n\tREQ_IRQ_ERR_SFTY_CE = 5,\n\tREQ_IRQ_ERR_WOL = 6,\n\tREQ_IRQ_ERR_MAC = 7,\n\tREQ_IRQ_ERR_NO = 8,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reset_control_flags {\n\tRESET_CONTROL_EXCLUSIVE = 4,\n\tRESET_CONTROL_EXCLUSIVE_DEASSERTED = 12,\n\tRESET_CONTROL_EXCLUSIVE_RELEASED = 0,\n\tRESET_CONTROL_SHARED = 1,\n\tRESET_CONTROL_SHARED_DEASSERTED = 9,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE = 6,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_DEASSERTED = 14,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_RELEASED = 2,\n\tRESET_CONTROL_OPTIONAL_SHARED = 3,\n\tRESET_CONTROL_OPTIONAL_SHARED_DEASSERTED = 11,\n};\n\nenum reset_type {\n\tRESET_TYPE_GENERAL = 0,\n\tRESET_TYPE_WAKEUP = 1,\n\tRESET_TYPE_WATCHDOG = 2,\n\tRESET_TYPE_SOFTWARE = 3,\n\tRESET_TYPE_USER = 4,\n\tRESET_TYPE_CPU_FAIL = 6,\n\tRESET_TYPE_XTAL_FAIL = 7,\n\tRESET_TYPE_ULP2 = 8,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum rfkill_hard_block_reasons {\n\tRFKILL_HARD_BLOCK_SIGNAL = 1,\n\tRFKILL_HARD_BLOCK_NOT_OWNER = 2,\n};\n\nenum rfkill_input_master_mode {\n\tRFKILL_INPUT_MASTER_UNLOCK = 0,\n\tRFKILL_INPUT_MASTER_RESTORE = 1,\n\tRFKILL_INPUT_MASTER_UNBLOCKALL = 2,\n\tNUM_RFKILL_INPUT_MASTER_MODES = 3,\n};\n\nenum rfkill_operation {\n\tRFKILL_OP_ADD = 0,\n\tRFKILL_OP_DEL = 1,\n\tRFKILL_OP_CHANGE = 2,\n\tRFKILL_OP_CHANGE_ALL = 3,\n};\n\nenum rfkill_sched_op {\n\tRFKILL_GLOBAL_OP_EPO = 0,\n\tRFKILL_GLOBAL_OP_RESTORE = 1,\n\tRFKILL_GLOBAL_OP_UNLOCK = 2,\n\tRFKILL_GLOBAL_OP_UNBLOCK = 3,\n};\n\nenum rfkill_type {\n\tRFKILL_TYPE_ALL = 0,\n\tRFKILL_TYPE_WLAN = 1,\n\tRFKILL_TYPE_BLUETOOTH = 2,\n\tRFKILL_TYPE_UWB = 3,\n\tRFKILL_TYPE_WIMAX = 4,\n\tRFKILL_TYPE_WWAN = 5,\n\tRFKILL_TYPE_GPS = 6,\n\tRFKILL_TYPE_FM = 7,\n\tRFKILL_TYPE_NFC = 8,\n\tNUM_RFKILL_TYPES = 9,\n};\n\nenum rfkill_user_states {\n\tRFKILL_USER_STATE_SOFT_BLOCKED = 0,\n\tRFKILL_USER_STATE_UNBLOCKED = 1,\n\tRFKILL_USER_STATE_HARD_BLOCKED = 2,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum riic_reg_list {\n\tRIIC_ICCR1 = 0,\n\tRIIC_ICCR2 = 1,\n\tRIIC_ICMR1 = 2,\n\tRIIC_ICMR3 = 3,\n\tRIIC_ICFER = 4,\n\tRIIC_ICSER = 5,\n\tRIIC_ICIER = 6,\n\tRIIC_ICSR2 = 7,\n\tRIIC_ICBRL = 8,\n\tRIIC_ICBRH = 9,\n\tRIIC_ICDRT = 10,\n\tRIIC_ICDRR = 11,\n\tRIIC_REG_END = 12,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum rk3036_plls {\n\tapll___5 = 0,\n\tdpll___2 = 1,\n\tgpll___2 = 2,\n};\n\nenum rk3128_plls {\n\tapll___6 = 0,\n\tdpll___3 = 1,\n\tcpll___4 = 2,\n\tgpll___3 = 3,\n};\n\nenum rk3188_plls {\n\tapll___7 = 0,\n\tcpll___5 = 1,\n\tdpll___4 = 2,\n\tgpll___4 = 3,\n};\n\nenum rk3228_plls {\n\tapll___8 = 0,\n\tdpll___5 = 1,\n\tcpll___6 = 2,\n\tgpll___5 = 3,\n};\n\nenum rk3288_plls {\n\tapll___9 = 0,\n\tdpll___6 = 1,\n\tcpll___7 = 2,\n\tgpll___6 = 3,\n\tnpll = 4,\n};\n\nenum rk3288_pwr_mode_con {\n\tPMU_PWR_MODE_EN = 0,\n\tPMU_CLK_CORE_SRC_GATE_EN = 1,\n\tPMU_GLOBAL_INT_DISABLE = 2,\n\tPMU_L2FLUSH_EN = 3,\n\tPMU_BUS_PD_EN = 4,\n\tPMU_A12_0_PD_EN = 5,\n\tPMU_SCU_EN = 6,\n\tPMU_PLL_PD_EN = 7,\n\tPMU_CHIP_PD_EN = 8,\n\tPMU_PWROFF_COMB = 9,\n\tPMU_ALIVE_USE_LF = 10,\n\tPMU_PMU_USE_LF = 11,\n\tPMU_OSC_24M_DIS = 12,\n\tPMU_INPUT_CLAMP_EN = 13,\n\tPMU_WAKEUP_RESET_EN = 14,\n\tPMU_SREF0_ENTER_EN = 15,\n\tPMU_SREF1_ENTER_EN = 16,\n\tPMU_DDR0IO_RET_EN = 17,\n\tPMU_DDR1IO_RET_EN = 18,\n\tPMU_DDR0_GATING_EN = 19,\n\tPMU_DDR1_GATING_EN = 20,\n\tPMU_DDR0IO_RET_DE_REQ = 21,\n\tPMU_DDR1IO_RET_DE_REQ = 22,\n};\n\nenum rk3288_pwr_mode_con1 {\n\tPMU_CLR_BUS = 0,\n\tPMU_CLR_CORE = 1,\n\tPMU_CLR_CPUP = 2,\n\tPMU_CLR_ALIVE = 3,\n\tPMU_CLR_DMA = 4,\n\tPMU_CLR_PERI = 5,\n\tPMU_CLR_GPU = 6,\n\tPMU_CLR_VIDEO = 7,\n\tPMU_CLR_HEVC = 8,\n\tPMU_CLR_VIO = 9,\n};\n\nenum rk3288_variant {\n\tRK3288_CRU = 0,\n\tRK3288W_CRU = 1,\n};\n\nenum rk3506_plls {\n\tgpll___7 = 0,\n\tv0pll = 1,\n\tv1pll = 2,\n};\n\nenum rk3x_i2c_state {\n\tSTATE_IDLE___4 = 0,\n\tSTATE_START = 1,\n\tSTATE_READ___2 = 2,\n\tSTATE_WRITE___2 = 3,\n\tSTATE_STOP = 4,\n};\n\nenum rk801_reg {\n\tRK801_ID_DCDC1 = 0,\n\tRK801_ID_DCDC2 = 1,\n\tRK801_ID_DCDC4 = 2,\n\tRK801_ID_DCDC3 = 3,\n\tRK801_ID_LDO1 = 4,\n\tRK801_ID_LDO2 = 5,\n\tRK801_ID_SWITCH = 6,\n\tRK801_ID_MAX = 7,\n};\n\nenum rk805_reg {\n\tRK805_ID_DCDC1 = 0,\n\tRK805_ID_DCDC2 = 1,\n\tRK805_ID_DCDC3 = 2,\n\tRK805_ID_DCDC4 = 3,\n\tRK805_ID_LDO1 = 4,\n\tRK805_ID_LDO2 = 5,\n\tRK805_ID_LDO3 = 6,\n};\n\nenum rk806_irqs {\n\tRK806_IRQ_PWRON_FALL = 0,\n\tRK806_IRQ_PWRON_RISE = 1,\n\tRK806_IRQ_PWRON = 2,\n\tRK806_IRQ_PWRON_LP = 3,\n\tRK806_IRQ_HOTDIE = 4,\n\tRK806_IRQ_VDC_RISE = 5,\n\tRK806_IRQ_VDC_FALL = 6,\n\tRK806_IRQ_VB_LO = 7,\n\tRK806_IRQ_REV0 = 8,\n\tRK806_IRQ_REV1 = 9,\n\tRK806_IRQ_REV2 = 10,\n\tRK806_IRQ_CRC_ERROR = 11,\n\tRK806_IRQ_SLP3_GPIO = 12,\n\tRK806_IRQ_SLP2_GPIO = 13,\n\tRK806_IRQ_SLP1_GPIO = 14,\n\tRK806_IRQ_WDT = 15,\n};\n\nenum rk806_reg_id {\n\tRK806_ID_DCDC1 = 0,\n\tRK806_ID_DCDC2 = 1,\n\tRK806_ID_DCDC3 = 2,\n\tRK806_ID_DCDC4 = 3,\n\tRK806_ID_DCDC5 = 4,\n\tRK806_ID_DCDC6 = 5,\n\tRK806_ID_DCDC7 = 6,\n\tRK806_ID_DCDC8 = 7,\n\tRK806_ID_DCDC9 = 8,\n\tRK806_ID_DCDC10 = 9,\n\tRK806_ID_NLDO1 = 10,\n\tRK806_ID_NLDO2 = 11,\n\tRK806_ID_NLDO3 = 12,\n\tRK806_ID_NLDO4 = 13,\n\tRK806_ID_NLDO5 = 14,\n\tRK806_ID_PLDO1 = 15,\n\tRK806_ID_PLDO2 = 16,\n\tRK806_ID_PLDO3 = 17,\n\tRK806_ID_PLDO4 = 18,\n\tRK806_ID_PLDO5 = 19,\n\tRK806_ID_PLDO6 = 20,\n\tRK806_ID_END = 21,\n};\n\nenum rk808_reg {\n\tRK808_ID_DCDC1 = 0,\n\tRK808_ID_DCDC2 = 1,\n\tRK808_ID_DCDC3 = 2,\n\tRK808_ID_DCDC4 = 3,\n\tRK808_ID_LDO1 = 4,\n\tRK808_ID_LDO2 = 5,\n\tRK808_ID_LDO3 = 6,\n\tRK808_ID_LDO4 = 7,\n\tRK808_ID_LDO5 = 8,\n\tRK808_ID_LDO6 = 9,\n\tRK808_ID_LDO7 = 10,\n\tRK808_ID_LDO8 = 11,\n\tRK808_ID_SWITCH1 = 12,\n\tRK808_ID_SWITCH2 = 13,\n};\n\nenum rk809_reg_id {\n\tRK809_ID_DCDC5 = 13,\n\tRK809_ID_SW1 = 14,\n\tRK809_ID_SW2 = 15,\n\tRK809_NUM_REGULATORS = 16,\n};\n\nenum rk816_irqs {\n\tRK816_IRQ_PWRON_FALL = 0,\n\tRK816_IRQ_PWRON_RISE = 1,\n\tRK816_IRQ_VB_LOW = 2,\n\tRK816_IRQ_PWRON = 3,\n\tRK816_IRQ_PWRON_LP = 4,\n\tRK816_IRQ_HOTDIE = 5,\n\tRK816_IRQ_RTC_ALARM = 6,\n\tRK816_IRQ_RTC_PERIOD = 7,\n\tRK816_IRQ_USB_OV = 8,\n\tRK816_IRQ_PLUG_IN = 9,\n\tRK816_IRQ_PLUG_OUT = 10,\n\tRK816_IRQ_CHG_OK = 11,\n\tRK816_IRQ_CHG_TE = 12,\n\tRK816_IRQ_CHG_TS = 13,\n\tRK816_IRQ_CHG_CVTLIM = 14,\n\tRK816_IRQ_DISCHG_ILIM = 15,\n};\n\nenum rk816_reg {\n\tRK816_ID_DCDC1 = 0,\n\tRK816_ID_DCDC2 = 1,\n\tRK816_ID_DCDC3 = 2,\n\tRK816_ID_DCDC4 = 3,\n\tRK816_ID_LDO1 = 4,\n\tRK816_ID_LDO2 = 5,\n\tRK816_ID_LDO3 = 6,\n\tRK816_ID_LDO4 = 7,\n\tRK816_ID_LDO5 = 8,\n\tRK816_ID_LDO6 = 9,\n\tRK816_ID_BOOST = 10,\n\tRK816_ID_OTG_SW = 11,\n};\n\nenum rk817_reg_id {\n\tRK817_ID_DCDC1 = 0,\n\tRK817_ID_DCDC2 = 1,\n\tRK817_ID_DCDC3 = 2,\n\tRK817_ID_DCDC4 = 3,\n\tRK817_ID_LDO1 = 4,\n\tRK817_ID_LDO2 = 5,\n\tRK817_ID_LDO3 = 6,\n\tRK817_ID_LDO4 = 7,\n\tRK817_ID_LDO5 = 8,\n\tRK817_ID_LDO6 = 9,\n\tRK817_ID_LDO7 = 10,\n\tRK817_ID_LDO8 = 11,\n\tRK817_ID_LDO9 = 12,\n\tRK817_ID_BOOST = 13,\n\tRK817_ID_BOOST_OTG_SW = 14,\n\tRK817_NUM_REGULATORS = 15,\n};\n\nenum rk818_reg {\n\tRK818_ID_DCDC1 = 0,\n\tRK818_ID_DCDC2 = 1,\n\tRK818_ID_DCDC3 = 2,\n\tRK818_ID_DCDC4 = 3,\n\tRK818_ID_BOOST = 4,\n\tRK818_ID_LDO1 = 5,\n\tRK818_ID_LDO2 = 6,\n\tRK818_ID_LDO3 = 7,\n\tRK818_ID_LDO4 = 8,\n\tRK818_ID_LDO5 = 9,\n\tRK818_ID_LDO6 = 10,\n\tRK818_ID_LDO7 = 11,\n\tRK818_ID_LDO8 = 12,\n\tRK818_ID_LDO9 = 13,\n\tRK818_ID_SWITCH = 14,\n\tRK818_ID_HDMI_SWITCH = 15,\n\tRK818_ID_OTG_SWITCH = 16,\n};\n\nenum rk_clocks_index {\n\tRK_ACLK_MAC = 0,\n\tRK_PCLK_MAC = 1,\n\tRK_MAC_CLK_TX = 2,\n\tRK_CLK_MAC_SPEED = 3,\n\tRK_MAC_CLK_RX = 4,\n\tRK_CLK_MAC_REF = 5,\n\tRK_CLK_MAC_REFOUT = 6,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rockchip_clk_branch_type {\n\tbranch_composite = 0,\n\tbranch_mux = 1,\n\tbranch_grf_mux = 2,\n\tbranch_divider = 3,\n\tbranch_fraction_divider = 4,\n\tbranch_gate = 5,\n\tbranch_grf_gate = 6,\n\tbranch_linked_gate = 7,\n\tbranch_mmc = 8,\n\tbranch_grf_mmc = 9,\n\tbranch_inverter = 10,\n\tbranch_factor = 11,\n\tbranch_ddrclk = 12,\n\tbranch_half_divider = 13,\n};\n\nenum rockchip_grf_type {\n\tgrf_type_sys = 0,\n\tgrf_type_pmu0 = 1,\n\tgrf_type_pmu1 = 2,\n\tgrf_type_ioc = 3,\n\tgrf_type_vo = 4,\n\tgrf_type_vpu = 5,\n};\n\nenum rockchip_mux_route_location {\n\tROCKCHIP_ROUTE_SAME = 0,\n\tROCKCHIP_ROUTE_PMU = 1,\n\tROCKCHIP_ROUTE_GRF = 2,\n};\n\nenum rockchip_pin_drv_type {\n\tDRV_TYPE_IO_DEFAULT = 0,\n\tDRV_TYPE_IO_1V8_OR_3V0 = 1,\n\tDRV_TYPE_IO_1V8_ONLY = 2,\n\tDRV_TYPE_IO_1V8_3V0_AUTO = 3,\n\tDRV_TYPE_IO_3V3_ONLY = 4,\n\tDRV_TYPE_IO_LEVEL_2_BIT = 5,\n\tDRV_TYPE_IO_LEVEL_8_BIT = 6,\n\tDRV_TYPE_MAX = 7,\n};\n\nenum rockchip_pin_pull_type {\n\tPULL_TYPE_IO_DEFAULT = 0,\n\tPULL_TYPE_IO_1V8_ONLY = 1,\n\tPULL_TYPE_MAX = 2,\n};\n\nenum rockchip_pinctrl_type {\n\tPX30 = 0,\n\tRV1108 = 1,\n\tRV1126 = 2,\n\tRK2928 = 3,\n\tRK3066B = 4,\n\tRK3128 = 5,\n\tRK3188 = 6,\n\tRK3288 = 7,\n\tRK3308 = 8,\n\tRK3328 = 9,\n\tRK3368 = 10,\n\tRK3399 = 11,\n\tRK3506 = 12,\n\tRK3528 = 13,\n\tRK3562 = 14,\n\tRK3568 = 15,\n\tRK3576 = 16,\n\tRK3588 = 17,\n};\n\nenum rockchip_pll_type {\n\tpll_rk3036 = 0,\n\tpll_rk3066 = 1,\n\tpll_rk3328 = 2,\n\tpll_rk3399 = 3,\n\tpll_rk3588 = 4,\n\tpll_rk3588_core = 5,\n\tpll_rk3588_ddr = 6,\n};\n\nenum romcode_read {\n\tINIT___2 = 0,\n\tFS_2_DS = 10,\n\tEND_DS = 11,\n\tDS_TO_FS = 12,\n\tEND_FS = 13,\n\tSWR = 14,\n\tEND_SWR = 15,\n};\n\nenum romcode_write {\n\tRDY_2_DS = 9,\n\tRDY_2_XP70_RST = 16,\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nenum rpc_accept_stat {\n\tRPC_SUCCESS = 0,\n\tRPC_PROG_UNAVAIL = 1,\n\tRPC_PROG_MISMATCH = 2,\n\tRPC_PROC_UNAVAIL = 3,\n\tRPC_GARBAGE_ARGS = 4,\n\tRPC_SYSTEM_ERR = 5,\n\tRPC_DROP_REPLY = 60000,\n};\n\nenum rpc_auth_flavors {\n\tRPC_AUTH_NULL = 0,\n\tRPC_AUTH_UNIX = 1,\n\tRPC_AUTH_SHORT = 2,\n\tRPC_AUTH_DES = 3,\n\tRPC_AUTH_KRB = 4,\n\tRPC_AUTH_GSS = 6,\n\tRPC_AUTH_TLS = 7,\n\tRPC_AUTH_MAXFLAVOR = 8,\n\tRPC_AUTH_GSS_KRB5 = 390003,\n\tRPC_AUTH_GSS_KRB5I = 390004,\n\tRPC_AUTH_GSS_KRB5P = 390005,\n\tRPC_AUTH_GSS_LKEY = 390006,\n\tRPC_AUTH_GSS_LKEYI = 390007,\n\tRPC_AUTH_GSS_LKEYP = 390008,\n\tRPC_AUTH_GSS_SPKM = 390009,\n\tRPC_AUTH_GSS_SPKMI = 390010,\n\tRPC_AUTH_GSS_SPKMP = 390011,\n};\n\nenum rpc_auth_stat {\n\tRPC_AUTH_OK = 0,\n\tRPC_AUTH_BADCRED = 1,\n\tRPC_AUTH_REJECTEDCRED = 2,\n\tRPC_AUTH_BADVERF = 3,\n\tRPC_AUTH_REJECTEDVERF = 4,\n\tRPC_AUTH_TOOWEAK = 5,\n\tRPC_AUTH_INVALIDRESP = 6,\n\tRPC_AUTH_FAILED = 7,\n\tRPCSEC_GSS_CREDPROBLEM = 13,\n\tRPCSEC_GSS_CTXPROBLEM = 14,\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum rpc_gss_proc {\n\tRPC_GSS_PROC_DATA = 0,\n\tRPC_GSS_PROC_INIT = 1,\n\tRPC_GSS_PROC_CONTINUE_INIT = 2,\n\tRPC_GSS_PROC_DESTROY = 3,\n};\n\nenum rpc_gss_svc {\n\tRPC_GSS_SVC_NONE = 1,\n\tRPC_GSS_SVC_INTEGRITY = 2,\n\tRPC_GSS_SVC_PRIVACY = 3,\n};\n\nenum rpc_msg_type {\n\tRPC_CALL = 0,\n\tRPC_REPLY = 1,\n};\n\nenum rpc_reject_stat {\n\tRPC_MISMATCH = 0,\n\tRPC_AUTH_ERROR = 1,\n};\n\nenum rpc_reply_stat {\n\tRPC_MSG_ACCEPTED = 0,\n\tRPC_MSG_DENIED = 1,\n};\n\nenum rpi_firmware_clk_id {\n\tRPI_FIRMWARE_EMMC_CLK_ID = 1,\n\tRPI_FIRMWARE_UART_CLK_ID = 2,\n\tRPI_FIRMWARE_ARM_CLK_ID = 3,\n\tRPI_FIRMWARE_CORE_CLK_ID = 4,\n\tRPI_FIRMWARE_V3D_CLK_ID = 5,\n\tRPI_FIRMWARE_H264_CLK_ID = 6,\n\tRPI_FIRMWARE_ISP_CLK_ID = 7,\n\tRPI_FIRMWARE_SDRAM_CLK_ID = 8,\n\tRPI_FIRMWARE_PIXEL_CLK_ID = 9,\n\tRPI_FIRMWARE_PWM_CLK_ID = 10,\n\tRPI_FIRMWARE_HEVC_CLK_ID = 11,\n\tRPI_FIRMWARE_EMMC2_CLK_ID = 12,\n\tRPI_FIRMWARE_M2MC_CLK_ID = 13,\n\tRPI_FIRMWARE_PIXEL_BVB_CLK_ID = 14,\n\tRPI_FIRMWARE_VEC_CLK_ID = 15,\n\tRPI_FIRMWARE_DISP_CLK_ID = 16,\n\tRPI_FIRMWARE_NUM_CLK_ID = 17,\n};\n\nenum rpi_firmware_property_status {\n\tRPI_FIRMWARE_STATUS_REQUEST = 0,\n\tRPI_FIRMWARE_STATUS_SUCCESS = 2147483648,\n\tRPI_FIRMWARE_STATUS_ERROR = 2147483649,\n};\n\nenum rpi_firmware_property_tag {\n\tRPI_FIRMWARE_PROPERTY_END = 0,\n\tRPI_FIRMWARE_GET_FIRMWARE_REVISION = 1,\n\tRPI_FIRMWARE_SET_CURSOR_INFO = 32784,\n\tRPI_FIRMWARE_SET_CURSOR_STATE = 32785,\n\tRPI_FIRMWARE_GET_BOARD_MODEL = 65537,\n\tRPI_FIRMWARE_GET_BOARD_REVISION = 65538,\n\tRPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 65539,\n\tRPI_FIRMWARE_GET_BOARD_SERIAL = 65540,\n\tRPI_FIRMWARE_GET_ARM_MEMORY = 65541,\n\tRPI_FIRMWARE_GET_VC_MEMORY = 65542,\n\tRPI_FIRMWARE_GET_CLOCKS = 65543,\n\tRPI_FIRMWARE_GET_POWER_STATE = 131073,\n\tRPI_FIRMWARE_GET_TIMING = 131074,\n\tRPI_FIRMWARE_SET_POWER_STATE = 163841,\n\tRPI_FIRMWARE_GET_CLOCK_STATE = 196609,\n\tRPI_FIRMWARE_GET_CLOCK_RATE = 196610,\n\tRPI_FIRMWARE_GET_VOLTAGE = 196611,\n\tRPI_FIRMWARE_GET_MAX_CLOCK_RATE = 196612,\n\tRPI_FIRMWARE_GET_MAX_VOLTAGE = 196613,\n\tRPI_FIRMWARE_GET_TEMPERATURE = 196614,\n\tRPI_FIRMWARE_GET_MIN_CLOCK_RATE = 196615,\n\tRPI_FIRMWARE_GET_MIN_VOLTAGE = 196616,\n\tRPI_FIRMWARE_GET_TURBO = 196617,\n\tRPI_FIRMWARE_GET_MAX_TEMPERATURE = 196618,\n\tRPI_FIRMWARE_GET_STC = 196619,\n\tRPI_FIRMWARE_ALLOCATE_MEMORY = 196620,\n\tRPI_FIRMWARE_LOCK_MEMORY = 196621,\n\tRPI_FIRMWARE_UNLOCK_MEMORY = 196622,\n\tRPI_FIRMWARE_RELEASE_MEMORY = 196623,\n\tRPI_FIRMWARE_EXECUTE_CODE = 196624,\n\tRPI_FIRMWARE_EXECUTE_QPU = 196625,\n\tRPI_FIRMWARE_SET_ENABLE_QPU = 196626,\n\tRPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 196628,\n\tRPI_FIRMWARE_GET_EDID_BLOCK = 196640,\n\tRPI_FIRMWARE_GET_CUSTOMER_OTP = 196641,\n\tRPI_FIRMWARE_GET_DOMAIN_STATE = 196656,\n\tRPI_FIRMWARE_GET_THROTTLED = 196678,\n\tRPI_FIRMWARE_GET_CLOCK_MEASURED = 196679,\n\tRPI_FIRMWARE_NOTIFY_REBOOT = 196680,\n\tRPI_FIRMWARE_SET_CLOCK_STATE = 229377,\n\tRPI_FIRMWARE_SET_CLOCK_RATE = 229378,\n\tRPI_FIRMWARE_SET_VOLTAGE = 229379,\n\tRPI_FIRMWARE_SET_TURBO = 229385,\n\tRPI_FIRMWARE_SET_CUSTOMER_OTP = 229409,\n\tRPI_FIRMWARE_SET_DOMAIN_STATE = 229424,\n\tRPI_FIRMWARE_GET_GPIO_STATE = 196673,\n\tRPI_FIRMWARE_SET_GPIO_STATE = 229441,\n\tRPI_FIRMWARE_SET_SDHOST_CLOCK = 229442,\n\tRPI_FIRMWARE_GET_GPIO_CONFIG = 196675,\n\tRPI_FIRMWARE_SET_GPIO_CONFIG = 229443,\n\tRPI_FIRMWARE_GET_PERIPH_REG = 196677,\n\tRPI_FIRMWARE_SET_PERIPH_REG = 229445,\n\tRPI_FIRMWARE_GET_POE_HAT_VAL = 196681,\n\tRPI_FIRMWARE_SET_POE_HAT_VAL = 196688,\n\tRPI_FIRMWARE_NOTIFY_XHCI_RESET = 196696,\n\tRPI_FIRMWARE_NOTIFY_DISPLAY_DONE = 196710,\n\tRPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 262145,\n\tRPI_FIRMWARE_FRAMEBUFFER_BLANK = 262146,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 262147,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 262148,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH = 262149,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER = 262150,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE = 262151,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PITCH = 262152,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 262153,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 262154,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 262155,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF = 262159,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF = 262160,\n\tRPI_FIRMWARE_FRAMEBUFFER_RELEASE = 294913,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 278531,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 278532,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH = 278533,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER = 278534,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE = 278535,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 278537,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 278538,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 278539,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC = 278542,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 294915,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 294916,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 294917,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER = 294918,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE = 294919,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 294921,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 294922,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 294923,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_TOUCHBUF = 294943,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF = 294944,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 294926,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT = 294927,\n\tRPI_FIRMWARE_VCHIQ_INIT = 294928,\n\tRPI_FIRMWARE_GET_COMMAND_LINE = 327681,\n\tRPI_FIRMWARE_GET_DMA_CHANNELS = 393217,\n};\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rpmb_type {\n\tRPMB_TYPE_EMMC = 0,\n\tRPMB_TYPE_UFS = 1,\n\tRPMB_TYPE_NVME = 2,\n};\n\nenum rproc_crash_type {\n\tRPROC_MMUFAULT = 0,\n\tRPROC_WATCHDOG = 1,\n\tRPROC_FATAL_ERROR = 2,\n};\n\nenum rproc_dump_mechanism {\n\tRPROC_COREDUMP_DISABLED = 0,\n\tRPROC_COREDUMP_ENABLED = 1,\n\tRPROC_COREDUMP_INLINE = 2,\n};\n\nenum rproc_features {\n\tRPROC_FEAT_ATTACH_ON_RECOVERY = 0,\n\tRPROC_MAX_FEATURES = 1,\n};\n\nenum rproc_state {\n\tRPROC_OFFLINE = 0,\n\tRPROC_SUSPENDED = 1,\n\tRPROC_RUNNING = 2,\n\tRPROC_CRASHED = 3,\n\tRPROC_DELETED = 4,\n\tRPROC_ATTACHED = 5,\n\tRPROC_DETACHED = 6,\n\tRPROC_LAST = 7,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rsaprivkey_actions {\n\tACT_rsa_get_d = 0,\n\tACT_rsa_get_dp = 1,\n\tACT_rsa_get_dq = 2,\n\tACT_rsa_get_e = 3,\n\tACT_rsa_get_n = 4,\n\tACT_rsa_get_p = 5,\n\tACT_rsa_get_q = 6,\n\tACT_rsa_get_qinv = 7,\n\tNR__rsaprivkey_actions = 8,\n};\n\nenum rsapubkey_actions {\n\tACT_rsa_get_e___2 = 0,\n\tACT_rsa_get_n___2 = 1,\n\tNR__rsapubkey_actions = 2,\n};\n\nenum rsc_handling_status {\n\tRSC_HANDLED = 0,\n\tRSC_IGNORED = 1,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rt6_nud_state {\n\tRT6_NUD_FAIL_HARD = -3,\n\tRT6_NUD_FAIL_PROBE = -2,\n\tRT6_NUD_FAIL_DO_RR = -1,\n\tRT6_NUD_SUCCEED = 1,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtc_control {\n\tDMA_CONTROL_RTC_64 = 0,\n\tDMA_CONTROL_RTC_32 = 8,\n\tDMA_CONTROL_RTC_96 = 16,\n\tDMA_CONTROL_RTC_128 = 24,\n};\n\nenum rtl8125_registers {\n\tLEDSEL0 = 24,\n\tINT_CFG0_8125 = 52,\n\tIntrMask_8125 = 56,\n\tIntrStatus_8125 = 60,\n\tINT_CFG1_8125 = 122,\n\tLEDSEL2 = 132,\n\tLEDSEL1 = 134,\n\tTxPoll_8125 = 144,\n\tLEDSEL3 = 150,\n\tMAC0_BKP = 6624,\n\tRSS_CTRL_8125 = 17664,\n\tQ_NUM_CTRL_8125 = 18432,\n\tEEE_TXIDLE_TIMER_8125 = 24648,\n};\n\nenum rtl8168_8101_registers {\n\tCSIDR = 100,\n\tCSIAR = 104,\n\tPMCH = 111,\n\tEPHYAR = 128,\n\tDLLPR = 208,\n\tDBG_REG = 209,\n\tTWSI = 210,\n\tMCU = 211,\n\tEFUSEAR = 220,\n\tMISC_1 = 242,\n};\n\nenum rtl8168_registers {\n\tLED_CTRL = 24,\n\tLED_FREQ = 26,\n\tEEE_LED = 27,\n\tERIDR = 112,\n\tERIAR = 116,\n\tEPHY_RXER_NUM = 124,\n\tOCPDR = 176,\n\tOCPAR = 180,\n\tGPHY_OCP = 184,\n\tRDSAR1 = 208,\n\tMISC = 240,\n\tCOMBO_LTR_EXTEND = 182,\n};\n\nenum rtl_dash_type {\n\tRTL_DASH_NONE = 0,\n\tRTL_DASH_DP = 1,\n\tRTL_DASH_EP = 2,\n\tRTL_DASH_25_BP = 3,\n};\n\nenum rtl_desc_bit {\n\tDescOwn = -2147483648,\n\tRingEnd = 1073741824,\n\tFirstFrag = 536870912,\n\tLastFrag = 268435456,\n};\n\nenum rtl_flag {\n\tRTL_FLAG_TASK_RESET_PENDING = 0,\n\tRTL_FLAG_TASK_TX_TIMEOUT = 1,\n\tRTL_FLAG_MAX = 2,\n};\n\nenum rtl_fw_opcode {\n\tPHY_READ = 0,\n\tPHY_DATA_OR = 1,\n\tPHY_DATA_AND = 2,\n\tPHY_BJMPN = 3,\n\tPHY_MDIO_CHG = 4,\n\tPHY_CLEAR_READCOUNT = 7,\n\tPHY_WRITE = 8,\n\tPHY_READCOUNT_EQ_SKIP = 9,\n\tPHY_COMP_EQ_SKIPN = 10,\n\tPHY_COMP_NEQ_SKIPN = 11,\n\tPHY_WRITE_PREVIOUS = 12,\n\tPHY_SKIPN = 13,\n\tPHY_DELAY_MS = 14,\n};\n\nenum rtl_register_content {\n\tSYSErr = 32768,\n\tPCSTimeout = 16384,\n\tSWInt = 256,\n\tTxDescUnavail = 128,\n\tRxFIFOOver = 64,\n\tLinkChg = 32,\n\tRxOverflow = 16,\n\tTxErr = 8,\n\tTxOK = 4,\n\tRxErr = 2,\n\tRxOK = 1,\n\tRxRWT = 4194304,\n\tRxRES = 2097152,\n\tRxRUNT = 1048576,\n\tRxCRC = 524288,\n\tStopReq = 128,\n\tCmdReset = 16,\n\tCmdRxEnb = 8,\n\tCmdTxEnb = 4,\n\tRxBufEmpty = 1,\n\tHPQ = 128,\n\tNPQ = 64,\n\tFSWInt = 1,\n\tCfg9346_Lock = 0,\n\tCfg9346_Unlock = 192,\n\tAcceptErr = 32,\n\tAcceptRunt = 16,\n\tAcceptBroadcast = 8,\n\tAcceptMulticast = 4,\n\tAcceptMyPhys = 2,\n\tAcceptAllPhys = 1,\n\tTxInterFrameGapShift = 24,\n\tTxDMAShift = 8,\n\tLEDS1 = 128,\n\tLEDS0 = 64,\n\tSpeed_down = 16,\n\tMEMMAP = 8,\n\tIOMAP = 4,\n\tVPD = 2,\n\tPMEnable = 1,\n\tClkReqEn = 128,\n\tMSIEnable = 32,\n\tPCI_Clock_66MHz = 1,\n\tPCI_Clock_33MHz = 0,\n\tMagicPacket = 32,\n\tLinkUp = 16,\n\tJumbo_En0 = 4,\n\tRdy_to_L23 = 2,\n\tBeacon_en = 1,\n\tJumbo_En1 = 2,\n\tBWF = 64,\n\tMWF = 32,\n\tUWF = 16,\n\tSpi_en = 8,\n\tLanWake = 2,\n\tPMEStatus = 1,\n\tASPM_en = 1,\n\tEnableBist = 32768,\n\tMac_dbgo_oe = 16384,\n\tEnAnaPLL = 16384,\n\tNormal_mode = 8192,\n\tForce_half_dup = 4096,\n\tForce_rxflow_en = 2048,\n\tForce_txflow_en = 1024,\n\tCxpl_dbg_sel = 512,\n\tASF = 256,\n\tPktCntrDisable = 128,\n\tMac_dbgo_sel = 28,\n\tRxVlan = 64,\n\tRxChkSum = 32,\n\tPCIDAC = 16,\n\tPCIMulRW = 8,\n\tTBI_Enable = 128,\n\tTxFlowCtrl = 64,\n\tRxFlowCtrl = 32,\n\t_1000bpsF = 16,\n\t_100bps = 8,\n\t_10bps = 4,\n\tLinkStatus = 2,\n\tFullDup = 1,\n\tCounterReset = 1,\n\tCounterDump = 8,\n\tMagicPacket_v2 = 65536,\n};\n\nenum rtl_registers {\n\tMAC0 = 0,\n\tMAC4 = 4,\n\tMAR0 = 8,\n\tCounterAddrLow = 16,\n\tCounterAddrHigh = 20,\n\tTxDescStartAddrLow = 32,\n\tTxDescStartAddrHigh = 36,\n\tTxHDescStartAddrLow = 40,\n\tTxHDescStartAddrHigh = 44,\n\tFLASH = 48,\n\tERSR = 54,\n\tChipCmd = 55,\n\tTxPoll = 56,\n\tIntrMask = 60,\n\tIntrStatus = 62,\n\tTxConfig = 64,\n\tTX_CONFIG_V2 = 24752,\n\tRxConfig = 68,\n\tCfg9346 = 80,\n\tConfig0 = 81,\n\tConfig1 = 82,\n\tConfig2 = 83,\n\tConfig3 = 84,\n\tConfig4 = 85,\n\tConfig5 = 86,\n\tPHYAR = 96,\n\tPHYstatus = 108,\n\tRxMaxSize = 218,\n\tCPlusCmd = 224,\n\tIntrMitigate = 226,\n\tRxDescAddrLow = 228,\n\tRxDescAddrHigh = 232,\n\tEarlyTxThres = 236,\n\tMaxTxPacketSize = 236,\n\tFuncEvent = 240,\n\tFuncEventMask = 244,\n\tFuncPresetState = 248,\n\tIBCR0 = 248,\n\tIBCR2 = 249,\n\tIBIMR0 = 250,\n\tIBISR0 = 251,\n\tFuncForceEvent = 252,\n\tALDPS_LTR = 57506,\n\tLTR_OBFF_LOCK = 57394,\n\tLTR_SNOOP = 57396,\n};\n\nenum rtl_rx_desc_bit {\n\tPID1 = 262144,\n\tPID0 = 131072,\n\tIPFail = 65536,\n\tUDPFail = 32768,\n\tTCPFail = 16384,\n\tRxVlanTag = 65536,\n};\n\nenum rtl_tx_desc_bit {\n\tTD_LSO = 134217728,\n\tTxVlanTag = 131072,\n};\n\nenum rtl_tx_desc_bit_0 {\n\tTD0_TCP_CS = 65536,\n\tTD0_UDP_CS = 131072,\n\tTD0_IP_CS = 262144,\n};\n\nenum rtl_tx_desc_bit_1 {\n\tTD1_GTSENV4 = 67108864,\n\tTD1_GTSENV6 = 33554432,\n\tTD1_IPv6_CS = 268435456,\n\tTD1_IPv4_CS = 536870912,\n\tTD1_TCP_CS = 1073741824,\n\tTD1_UDP_CS = -2147483648,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum rv1108_plls {\n\tapll___10 = 0,\n\tdpll___7 = 1,\n\tgpll___8 = 2,\n};\n\nenum rv1126_plls {\n\tapll___11 = 0,\n\tdpll___8 = 1,\n\tcpll___8 = 2,\n\thpll = 3,\n};\n\nenum rv1126_pmu_plls {\n\tgpll___9 = 0,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rx_frame_status {\n\tgood_frame = 0,\n\tdiscard_frame = 1,\n\tcsum_none = 2,\n\tllc_snap = 4,\n\tdma_own = 8,\n\trx_not_ls = 16,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum rx_offset {\n\tNO_RX_OFFSET = 0,\n\tRX_OFFSET_PLUS_5_MV = 1,\n\tRX_OFFSET_PLUS_10_MV = 2,\n\tRX_OFFSET_MINUS_5_MV = 3,\n\tRX_OFFSET_MAX = 4,\n};\n\nenum rz_clk_types {\n\tCLK_TYPE_RZA_MAIN = 5,\n\tCLK_TYPE_RZA_PLL = 6,\n};\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nenum s2mpa01_reg {\n\tS2MPA01_REG_ID = 0,\n\tS2MPA01_REG_INT1 = 1,\n\tS2MPA01_REG_INT2 = 2,\n\tS2MPA01_REG_INT3 = 3,\n\tS2MPA01_REG_INT1M = 4,\n\tS2MPA01_REG_INT2M = 5,\n\tS2MPA01_REG_INT3M = 6,\n\tS2MPA01_REG_ST1 = 7,\n\tS2MPA01_REG_ST2 = 8,\n\tS2MPA01_REG_PWRONSRC = 9,\n\tS2MPA01_REG_OFFSRC = 10,\n\tS2MPA01_REG_RTC_BUF = 11,\n\tS2MPA01_REG_CTRL1 = 12,\n\tS2MPA01_REG_ETC_TEST = 13,\n\tS2MPA01_REG_RSVD1 = 14,\n\tS2MPA01_REG_BU_CHG = 15,\n\tS2MPA01_REG_RAMP1 = 16,\n\tS2MPA01_REG_RAMP2 = 17,\n\tS2MPA01_REG_LDO_DSCH1 = 18,\n\tS2MPA01_REG_LDO_DSCH2 = 19,\n\tS2MPA01_REG_LDO_DSCH3 = 20,\n\tS2MPA01_REG_LDO_DSCH4 = 21,\n\tS2MPA01_REG_OTP_ADRL = 22,\n\tS2MPA01_REG_OTP_ADRH = 23,\n\tS2MPA01_REG_OTP_DATA = 24,\n\tS2MPA01_REG_MON1SEL = 25,\n\tS2MPA01_REG_MON2SEL = 26,\n\tS2MPA01_REG_LEE = 27,\n\tS2MPA01_REG_RSVD2 = 28,\n\tS2MPA01_REG_RSVD3 = 29,\n\tS2MPA01_REG_RSVD4 = 30,\n\tS2MPA01_REG_RSVD5 = 31,\n\tS2MPA01_REG_RSVD6 = 32,\n\tS2MPA01_REG_TOP_RSVD = 33,\n\tS2MPA01_REG_DVS_SEL = 34,\n\tS2MPA01_REG_DVS_PTR = 35,\n\tS2MPA01_REG_DVS_DATA = 36,\n\tS2MPA01_REG_RSVD_NO = 37,\n\tS2MPA01_REG_UVLO = 38,\n\tS2MPA01_REG_LEE_NO = 39,\n\tS2MPA01_REG_B1CTRL1 = 40,\n\tS2MPA01_REG_B1CTRL2 = 41,\n\tS2MPA01_REG_B2CTRL1 = 42,\n\tS2MPA01_REG_B2CTRL2 = 43,\n\tS2MPA01_REG_B3CTRL1 = 44,\n\tS2MPA01_REG_B3CTRL2 = 45,\n\tS2MPA01_REG_B4CTRL1 = 46,\n\tS2MPA01_REG_B4CTRL2 = 47,\n\tS2MPA01_REG_B5CTRL1 = 48,\n\tS2MPA01_REG_B5CTRL2 = 49,\n\tS2MPA01_REG_B5CTRL3 = 50,\n\tS2MPA01_REG_B5CTRL4 = 51,\n\tS2MPA01_REG_B5CTRL5 = 52,\n\tS2MPA01_REG_B5CTRL6 = 53,\n\tS2MPA01_REG_B6CTRL1 = 54,\n\tS2MPA01_REG_B6CTRL2 = 55,\n\tS2MPA01_REG_B7CTRL1 = 56,\n\tS2MPA01_REG_B7CTRL2 = 57,\n\tS2MPA01_REG_B8CTRL1 = 58,\n\tS2MPA01_REG_B8CTRL2 = 59,\n\tS2MPA01_REG_B9CTRL1 = 60,\n\tS2MPA01_REG_B9CTRL2 = 61,\n\tS2MPA01_REG_B10CTRL1 = 62,\n\tS2MPA01_REG_B10CTRL2 = 63,\n\tS2MPA01_REG_L1CTRL = 64,\n\tS2MPA01_REG_L2CTRL = 65,\n\tS2MPA01_REG_L3CTRL = 66,\n\tS2MPA01_REG_L4CTRL = 67,\n\tS2MPA01_REG_L5CTRL = 68,\n\tS2MPA01_REG_L6CTRL = 69,\n\tS2MPA01_REG_L7CTRL = 70,\n\tS2MPA01_REG_L8CTRL = 71,\n\tS2MPA01_REG_L9CTRL = 72,\n\tS2MPA01_REG_L10CTRL = 73,\n\tS2MPA01_REG_L11CTRL = 74,\n\tS2MPA01_REG_L12CTRL = 75,\n\tS2MPA01_REG_L13CTRL = 76,\n\tS2MPA01_REG_L14CTRL = 77,\n\tS2MPA01_REG_L15CTRL = 78,\n\tS2MPA01_REG_L16CTRL = 79,\n\tS2MPA01_REG_L17CTRL = 80,\n\tS2MPA01_REG_L18CTRL = 81,\n\tS2MPA01_REG_L19CTRL = 82,\n\tS2MPA01_REG_L20CTRL = 83,\n\tS2MPA01_REG_L21CTRL = 84,\n\tS2MPA01_REG_L22CTRL = 85,\n\tS2MPA01_REG_L23CTRL = 86,\n\tS2MPA01_REG_L24CTRL = 87,\n\tS2MPA01_REG_L25CTRL = 88,\n\tS2MPA01_REG_L26CTRL = 89,\n\tS2MPA01_REG_LDO_OVCB1 = 90,\n\tS2MPA01_REG_LDO_OVCB2 = 91,\n\tS2MPA01_REG_LDO_OVCB3 = 92,\n\tS2MPA01_REG_LDO_OVCB4 = 93,\n};\n\nenum s2mpg10_common_irq {\n\tS2MPG10_COMMON_IRQ_PMIC = 0,\n\tS2MPG10_COMMON_IRQ_UNUSED = 1,\n};\n\nenum s2mpg10_common_reg {\n\tS2MPG10_COMMON_CHIPID = 0,\n\tS2MPG10_COMMON_INT = 1,\n\tS2MPG10_COMMON_INT_MASK = 2,\n\tS2MPG10_COMMON_SPD_CTRL1 = 10,\n\tS2MPG10_COMMON_SPD_CTRL2 = 11,\n\tS2MPG10_COMMON_SPD_CTRL3 = 12,\n\tS2MPG10_COMMON_MON1SEL = 26,\n\tS2MPG10_COMMON_MON2SEL = 27,\n\tS2MPG10_COMMON_MONR = 28,\n\tS2MPG10_COMMON_DEBUG_CTRL1 = 29,\n\tS2MPG10_COMMON_DEBUG_CTRL2 = 30,\n\tS2MPG10_COMMON_DEBUG_CTRL3 = 31,\n\tS2MPG10_COMMON_DEBUG_CTRL4 = 32,\n\tS2MPG10_COMMON_DEBUG_CTRL5 = 33,\n\tS2MPG10_COMMON_DEBUG_CTRL6 = 34,\n\tS2MPG10_COMMON_DEBUG_CTRL7 = 35,\n\tS2MPG10_COMMON_DEBUG_CTRL8 = 36,\n\tS2MPG10_COMMON_TEST_MODE1 = 37,\n\tS2MPG10_COMMON_TEST_MODE2 = 38,\n\tS2MPG10_COMMON_SPD_DEBUG1 = 39,\n\tS2MPG10_COMMON_SPD_DEBUG2 = 40,\n\tS2MPG10_COMMON_SPD_DEBUG3 = 41,\n\tS2MPG10_COMMON_SPD_DEBUG4 = 42,\n};\n\nenum s2mpg10_irq {\n\tS2MPG10_IRQ_PWRONF = 0,\n\tS2MPG10_IRQ_PWRONR = 1,\n\tS2MPG10_IRQ_JIGONBF = 2,\n\tS2MPG10_IRQ_JIGONBR = 3,\n\tS2MPG10_IRQ_ACOKBF = 4,\n\tS2MPG10_IRQ_ACOKBR = 5,\n\tS2MPG10_IRQ_PWRON1S = 6,\n\tS2MPG10_IRQ_MRB = 7,\n\tS2MPG10_IRQ_RTC60S = 8,\n\tS2MPG10_IRQ_RTCA1 = 9,\n\tS2MPG10_IRQ_RTCA0 = 10,\n\tS2MPG10_IRQ_RTC1S = 11,\n\tS2MPG10_IRQ_WTSR_COLDRST = 12,\n\tS2MPG10_IRQ_WTSR = 13,\n\tS2MPG10_IRQ_WRST = 14,\n\tS2MPG10_IRQ_SMPL = 15,\n\tS2MPG10_IRQ_120C = 16,\n\tS2MPG10_IRQ_140C = 17,\n\tS2MPG10_IRQ_TSD = 18,\n\tS2MPG10_IRQ_PIF_TIMEOUT1 = 19,\n\tS2MPG10_IRQ_PIF_TIMEOUT2 = 20,\n\tS2MPG10_IRQ_SPD_PARITY_ERR = 21,\n\tS2MPG10_IRQ_SPD_ABNORMAL_STOP = 22,\n\tS2MPG10_IRQ_PMETER_OVERF = 23,\n\tS2MPG10_IRQ_OCP_B1M = 24,\n\tS2MPG10_IRQ_OCP_B2M = 25,\n\tS2MPG10_IRQ_OCP_B3M = 26,\n\tS2MPG10_IRQ_OCP_B4M = 27,\n\tS2MPG10_IRQ_OCP_B5M = 28,\n\tS2MPG10_IRQ_OCP_B6M = 29,\n\tS2MPG10_IRQ_OCP_B7M = 30,\n\tS2MPG10_IRQ_OCP_B8M = 31,\n\tS2MPG10_IRQ_OCP_B9M = 32,\n\tS2MPG10_IRQ_OCP_B10M = 33,\n\tS2MPG10_IRQ_WLWP_ACC = 34,\n\tS2MPG10_IRQ_SMPL_TIMEOUT = 35,\n\tS2MPG10_IRQ_WTSR_TIMEOUT = 36,\n\tS2MPG10_IRQ_SPD_SRP_PKT_RST = 37,\n\tS2MPG10_IRQ_PWR_WARN_CH0 = 38,\n\tS2MPG10_IRQ_PWR_WARN_CH1 = 39,\n\tS2MPG10_IRQ_PWR_WARN_CH2 = 40,\n\tS2MPG10_IRQ_PWR_WARN_CH3 = 41,\n\tS2MPG10_IRQ_PWR_WARN_CH4 = 42,\n\tS2MPG10_IRQ_PWR_WARN_CH5 = 43,\n\tS2MPG10_IRQ_PWR_WARN_CH6 = 44,\n\tS2MPG10_IRQ_PWR_WARN_CH7 = 45,\n\tS2MPG10_IRQ_NR = 46,\n};\n\nenum s2mpg10_pmic_reg {\n\tS2MPG10_PMIC_INT1 = 0,\n\tS2MPG10_PMIC_INT2 = 1,\n\tS2MPG10_PMIC_INT3 = 2,\n\tS2MPG10_PMIC_INT4 = 3,\n\tS2MPG10_PMIC_INT5 = 4,\n\tS2MPG10_PMIC_INT6 = 5,\n\tS2MPG10_PMIC_INT1M = 6,\n\tS2MPG10_PMIC_INT2M = 7,\n\tS2MPG10_PMIC_INT3M = 8,\n\tS2MPG10_PMIC_INT4M = 9,\n\tS2MPG10_PMIC_INT5M = 10,\n\tS2MPG10_PMIC_INT6M = 11,\n\tS2MPG10_PMIC_STATUS1 = 12,\n\tS2MPG10_PMIC_STATUS2 = 13,\n\tS2MPG10_PMIC_PWRONSRC = 14,\n\tS2MPG10_PMIC_OFFSRC = 15,\n\tS2MPG10_PMIC_BU_CHG = 16,\n\tS2MPG10_PMIC_RTCBUF = 17,\n\tS2MPG10_PMIC_COMMON_CTRL1 = 18,\n\tS2MPG10_PMIC_COMMON_CTRL2 = 19,\n\tS2MPG10_PMIC_COMMON_CTRL3 = 20,\n\tS2MPG10_PMIC_COMMON_CTRL4 = 21,\n\tS2MPG10_PMIC_SMPL_WARN_CTRL = 22,\n\tS2MPG10_PMIC_MIMICKING_CTRL = 23,\n\tS2MPG10_PMIC_B1M_CTRL = 24,\n\tS2MPG10_PMIC_B1M_OUT1 = 25,\n\tS2MPG10_PMIC_B1M_OUT2 = 26,\n\tS2MPG10_PMIC_B2M_CTRL = 27,\n\tS2MPG10_PMIC_B2M_OUT1 = 28,\n\tS2MPG10_PMIC_B2M_OUT2 = 29,\n\tS2MPG10_PMIC_B3M_CTRL = 30,\n\tS2MPG10_PMIC_B3M_OUT1 = 31,\n\tS2MPG10_PMIC_B3M_OUT2 = 32,\n\tS2MPG10_PMIC_B4M_CTRL = 33,\n\tS2MPG10_PMIC_B4M_OUT1 = 34,\n\tS2MPG10_PMIC_B4M_OUT2 = 35,\n\tS2MPG10_PMIC_B5M_CTRL = 36,\n\tS2MPG10_PMIC_B5M_OUT1 = 37,\n\tS2MPG10_PMIC_B5M_OUT2 = 38,\n\tS2MPG10_PMIC_B6M_CTRL = 39,\n\tS2MPG10_PMIC_B6M_OUT1 = 40,\n\tS2MPG10_PMIC_B6M_OUT2 = 41,\n\tS2MPG10_PMIC_B7M_CTRL = 42,\n\tS2MPG10_PMIC_B7M_OUT1 = 43,\n\tS2MPG10_PMIC_B7M_OUT2 = 44,\n\tS2MPG10_PMIC_B8M_CTRL = 45,\n\tS2MPG10_PMIC_B8M_OUT1 = 46,\n\tS2MPG10_PMIC_B8M_OUT2 = 47,\n\tS2MPG10_PMIC_B9M_CTRL = 48,\n\tS2MPG10_PMIC_B9M_OUT1 = 49,\n\tS2MPG10_PMIC_B9M_OUT2 = 50,\n\tS2MPG10_PMIC_B10M_CTRL = 51,\n\tS2MPG10_PMIC_B10M_OUT1 = 52,\n\tS2MPG10_PMIC_B10M_OUT2 = 53,\n\tS2MPG10_PMIC_BUCK1M_USONIC = 54,\n\tS2MPG10_PMIC_BUCK2M_USONIC = 55,\n\tS2MPG10_PMIC_BUCK3M_USONIC = 56,\n\tS2MPG10_PMIC_BUCK4M_USONIC = 57,\n\tS2MPG10_PMIC_BUCK5M_USONIC = 58,\n\tS2MPG10_PMIC_BUCK6M_USONIC = 59,\n\tS2MPG10_PMIC_BUCK7M_USONIC = 60,\n\tS2MPG10_PMIC_BUCK8M_USONIC = 61,\n\tS2MPG10_PMIC_BUCK9M_USONIC = 62,\n\tS2MPG10_PMIC_BUCK10M_USONIC = 63,\n\tS2MPG10_PMIC_L1M_CTRL = 64,\n\tS2MPG10_PMIC_L2M_CTRL = 65,\n\tS2MPG10_PMIC_L3M_CTRL = 66,\n\tS2MPG10_PMIC_L4M_CTRL = 67,\n\tS2MPG10_PMIC_L5M_CTRL = 68,\n\tS2MPG10_PMIC_L6M_CTRL = 69,\n\tS2MPG10_PMIC_L7M_CTRL = 70,\n\tS2MPG10_PMIC_L8M_CTRL = 71,\n\tS2MPG10_PMIC_L9M_CTRL = 72,\n\tS2MPG10_PMIC_L10M_CTRL = 73,\n\tS2MPG10_PMIC_L11M_CTRL1 = 74,\n\tS2MPG10_PMIC_L11M_CTRL2 = 75,\n\tS2MPG10_PMIC_L12M_CTRL1 = 76,\n\tS2MPG10_PMIC_L12M_CTRL2 = 77,\n\tS2MPG10_PMIC_L13M_CTRL1 = 78,\n\tS2MPG10_PMIC_L13M_CTRL2 = 79,\n\tS2MPG10_PMIC_L14M_CTRL = 80,\n\tS2MPG10_PMIC_L15M_CTRL1 = 81,\n\tS2MPG10_PMIC_L15M_CTRL2 = 82,\n\tS2MPG10_PMIC_L16M_CTRL = 83,\n\tS2MPG10_PMIC_L17M_CTRL = 84,\n\tS2MPG10_PMIC_L18M_CTRL = 85,\n\tS2MPG10_PMIC_L19M_CTRL = 86,\n\tS2MPG10_PMIC_L20M_CTRL = 87,\n\tS2MPG10_PMIC_L21M_CTRL = 88,\n\tS2MPG10_PMIC_L22M_CTRL = 89,\n\tS2MPG10_PMIC_L23M_CTRL = 90,\n\tS2MPG10_PMIC_L24M_CTRL = 91,\n\tS2MPG10_PMIC_L25M_CTRL = 92,\n\tS2MPG10_PMIC_L26M_CTRL = 93,\n\tS2MPG10_PMIC_L27M_CTRL = 94,\n\tS2MPG10_PMIC_L28M_CTRL = 95,\n\tS2MPG10_PMIC_L29M_CTRL = 96,\n\tS2MPG10_PMIC_L30M_CTRL = 97,\n\tS2MPG10_PMIC_L31M_CTRL = 98,\n\tS2MPG10_PMIC_LDO_CTRL1 = 99,\n\tS2MPG10_PMIC_LDO_CTRL2 = 100,\n\tS2MPG10_PMIC_LDO_DSCH1 = 101,\n\tS2MPG10_PMIC_LDO_DSCH2 = 102,\n\tS2MPG10_PMIC_LDO_DSCH3 = 103,\n\tS2MPG10_PMIC_LDO_DSCH4 = 104,\n\tS2MPG10_PMIC_LDO_BUCK7M_HLIMIT = 105,\n\tS2MPG10_PMIC_LDO_BUCK7M_LLIMIT = 106,\n\tS2MPG10_PMIC_LDO_LDO21M_HLIMIT = 107,\n\tS2MPG10_PMIC_LDO_LDO21M_LLIMIT = 108,\n\tS2MPG10_PMIC_LDO_LDO11M_HLIMIT = 109,\n\tS2MPG10_PMIC_DVS_RAMP1 = 110,\n\tS2MPG10_PMIC_DVS_RAMP2 = 111,\n\tS2MPG10_PMIC_DVS_RAMP3 = 112,\n\tS2MPG10_PMIC_DVS_RAMP4 = 113,\n\tS2MPG10_PMIC_DVS_RAMP5 = 114,\n\tS2MPG10_PMIC_DVS_RAMP6 = 115,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL1 = 116,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL2 = 117,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL3 = 118,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL4 = 119,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL5 = 120,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL6 = 121,\n\tS2MPG10_PMIC_OFF_CTRL1 = 122,\n\tS2MPG10_PMIC_OFF_CTRL2 = 123,\n\tS2MPG10_PMIC_OFF_CTRL3 = 124,\n\tS2MPG10_PMIC_OFF_CTRL4 = 125,\n\tS2MPG10_PMIC_SEQ_CTRL1 = 126,\n\tS2MPG10_PMIC_SEQ_CTRL2 = 127,\n\tS2MPG10_PMIC_SEQ_CTRL3 = 128,\n\tS2MPG10_PMIC_SEQ_CTRL4 = 129,\n\tS2MPG10_PMIC_SEQ_CTRL5 = 130,\n\tS2MPG10_PMIC_SEQ_CTRL6 = 131,\n\tS2MPG10_PMIC_SEQ_CTRL7 = 132,\n\tS2MPG10_PMIC_SEQ_CTRL8 = 133,\n\tS2MPG10_PMIC_SEQ_CTRL9 = 134,\n\tS2MPG10_PMIC_SEQ_CTRL10 = 135,\n\tS2MPG10_PMIC_SEQ_CTRL11 = 136,\n\tS2MPG10_PMIC_SEQ_CTRL12 = 137,\n\tS2MPG10_PMIC_SEQ_CTRL13 = 138,\n\tS2MPG10_PMIC_SEQ_CTRL14 = 139,\n\tS2MPG10_PMIC_SEQ_CTRL15 = 140,\n\tS2MPG10_PMIC_SEQ_CTRL16 = 141,\n\tS2MPG10_PMIC_SEQ_CTRL17 = 142,\n\tS2MPG10_PMIC_SEQ_CTRL18 = 143,\n\tS2MPG10_PMIC_SEQ_CTRL19 = 144,\n\tS2MPG10_PMIC_SEQ_CTRL20 = 145,\n\tS2MPG10_PMIC_SEQ_CTRL21 = 146,\n\tS2MPG10_PMIC_SEQ_CTRL22 = 147,\n\tS2MPG10_PMIC_SEQ_CTRL23 = 148,\n\tS2MPG10_PMIC_SEQ_CTRL24 = 149,\n\tS2MPG10_PMIC_SEQ_CTRL25 = 150,\n\tS2MPG10_PMIC_SEQ_CTRL26 = 151,\n\tS2MPG10_PMIC_SEQ_CTRL27 = 152,\n\tS2MPG10_PMIC_SEQ_CTRL28 = 153,\n\tS2MPG10_PMIC_SEQ_CTRL29 = 154,\n\tS2MPG10_PMIC_SEQ_CTRL30 = 155,\n\tS2MPG10_PMIC_SEQ_CTRL31 = 156,\n\tS2MPG10_PMIC_SEQ_CTRL32 = 157,\n\tS2MPG10_PMIC_SEQ_CTRL33 = 158,\n\tS2MPG10_PMIC_SEQ_CTRL34 = 159,\n\tS2MPG10_PMIC_SEQ_CTRL35 = 160,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL1 = 161,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL2 = 162,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL3 = 163,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL4 = 164,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL5 = 165,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL6 = 166,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL7 = 167,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL8 = 168,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL9 = 169,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL10 = 170,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL11 = 171,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL12 = 172,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL13 = 173,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL14 = 174,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL15 = 175,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL16 = 176,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL17 = 177,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL18 = 178,\n\tS2MPG10_PMIC_PCTRLSEL1 = 179,\n\tS2MPG10_PMIC_PCTRLSEL2 = 180,\n\tS2MPG10_PMIC_PCTRLSEL3 = 181,\n\tS2MPG10_PMIC_PCTRLSEL4 = 182,\n\tS2MPG10_PMIC_PCTRLSEL5 = 183,\n\tS2MPG10_PMIC_PCTRLSEL6 = 184,\n\tS2MPG10_PMIC_PCTRLSEL7 = 185,\n\tS2MPG10_PMIC_PCTRLSEL8 = 186,\n\tS2MPG10_PMIC_PCTRLSEL9 = 187,\n\tS2MPG10_PMIC_PCTRLSEL10 = 188,\n\tS2MPG10_PMIC_PCTRLSEL11 = 189,\n\tS2MPG10_PMIC_PCTRLSEL12 = 190,\n\tS2MPG10_PMIC_PCTRLSEL13 = 191,\n\tS2MPG10_PMIC_DCTRLSEL1 = 192,\n\tS2MPG10_PMIC_DCTRLSEL2 = 193,\n\tS2MPG10_PMIC_DCTRLSEL3 = 194,\n\tS2MPG10_PMIC_DCTRLSEL4 = 195,\n\tS2MPG10_PMIC_DCTRLSEL5 = 196,\n\tS2MPG10_PMIC_DCTRLSEL6 = 197,\n\tS2MPG10_PMIC_DCTRLSEL7 = 198,\n\tS2MPG10_PMIC_GPIO_CTRL1 = 199,\n\tS2MPG10_PMIC_GPIO_CTRL2 = 200,\n\tS2MPG10_PMIC_GPIO_CTRL3 = 201,\n\tS2MPG10_PMIC_GPIO_CTRL4 = 202,\n\tS2MPG10_PMIC_GPIO_CTRL5 = 203,\n\tS2MPG10_PMIC_GPIO_CTRL6 = 204,\n\tS2MPG10_PMIC_GPIO_CTRL7 = 205,\n\tS2MPG10_PMIC_B2M_OCP_WARN = 206,\n\tS2MPG10_PMIC_B2M_OCP_WARN_X = 207,\n\tS2MPG10_PMIC_B2M_OCP_WARN_Y = 208,\n\tS2MPG10_PMIC_B2M_OCP_WARN_Z = 209,\n\tS2MPG10_PMIC_B3M_OCP_WARN = 210,\n\tS2MPG10_PMIC_B3M_OCP_WARN_X = 211,\n\tS2MPG10_PMIC_B3M_OCP_WARN_Y = 212,\n\tS2MPG10_PMIC_B3M_OCP_WARN_Z = 213,\n\tS2MPG10_PMIC_B10M_OCP_WARN = 214,\n\tS2MPG10_PMIC_B10M_OCP_WARN_X = 215,\n\tS2MPG10_PMIC_B10M_OCP_WARN_Y = 216,\n\tS2MPG10_PMIC_B10M_OCP_WARN_Z = 217,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN = 218,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN_X = 219,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN_Y = 220,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN_Z = 221,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN = 222,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN_X = 223,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN_Y = 224,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN_Z = 225,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN = 226,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN_X = 227,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN_Y = 228,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN_Z = 229,\n\tS2MPG10_PMIC_BUCK_OCP_EN1 = 230,\n\tS2MPG10_PMIC_BUCK_OCP_EN2 = 231,\n\tS2MPG10_PMIC_BUCK_OCP_PD_EN1 = 232,\n\tS2MPG10_PMIC_BUCK_OCP_PD_EN2 = 233,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL1 = 234,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL2 = 235,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL3 = 236,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL4 = 237,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL5 = 238,\n\tS2MPG10_PMIC_PIF_CTRL = 239,\n\tS2MPG10_PMIC_BUCK_HR_MODE1 = 240,\n\tS2MPG10_PMIC_BUCK_HR_MODE2 = 241,\n\tS2MPG10_PMIC_FAULTOUT_CTRL = 242,\n\tS2MPG10_PMIC_LDO_SENSE1 = 243,\n\tS2MPG10_PMIC_LDO_SENSE2 = 244,\n\tS2MPG10_PMIC_LDO_SENSE3 = 245,\n\tS2MPG10_PMIC_LDO_SENSE4 = 246,\n};\n\nenum s2mpg10_regulators {\n\tS2MPG10_BUCK1 = 0,\n\tS2MPG10_BUCK2 = 1,\n\tS2MPG10_BUCK3 = 2,\n\tS2MPG10_BUCK4 = 3,\n\tS2MPG10_BUCK5 = 4,\n\tS2MPG10_BUCK6 = 5,\n\tS2MPG10_BUCK7 = 6,\n\tS2MPG10_BUCK8 = 7,\n\tS2MPG10_BUCK9 = 8,\n\tS2MPG10_BUCK10 = 9,\n\tS2MPG10_LDO1 = 10,\n\tS2MPG10_LDO2 = 11,\n\tS2MPG10_LDO3 = 12,\n\tS2MPG10_LDO4 = 13,\n\tS2MPG10_LDO5 = 14,\n\tS2MPG10_LDO6 = 15,\n\tS2MPG10_LDO7 = 16,\n\tS2MPG10_LDO8 = 17,\n\tS2MPG10_LDO9 = 18,\n\tS2MPG10_LDO10 = 19,\n\tS2MPG10_LDO11 = 20,\n\tS2MPG10_LDO12 = 21,\n\tS2MPG10_LDO13 = 22,\n\tS2MPG10_LDO14 = 23,\n\tS2MPG10_LDO15 = 24,\n\tS2MPG10_LDO16 = 25,\n\tS2MPG10_LDO17 = 26,\n\tS2MPG10_LDO18 = 27,\n\tS2MPG10_LDO19 = 28,\n\tS2MPG10_LDO20 = 29,\n\tS2MPG10_LDO21 = 30,\n\tS2MPG10_LDO22 = 31,\n\tS2MPG10_LDO23 = 32,\n\tS2MPG10_LDO24 = 33,\n\tS2MPG10_LDO25 = 34,\n\tS2MPG10_LDO26 = 35,\n\tS2MPG10_LDO27 = 36,\n\tS2MPG10_LDO28 = 37,\n\tS2MPG10_LDO29 = 38,\n\tS2MPG10_LDO30 = 39,\n\tS2MPG10_LDO31 = 40,\n\tS2MPG10_REGULATOR_MAX = 41,\n};\n\nenum s2mpg11_common_irq {\n\tS2MPG11_COMMON_IRQ_PMIC = 0,\n\tS2MPG11_COMMON_IRQ_UNUSED = 1,\n};\n\nenum s2mpg11_common_reg {\n\tS2MPG11_COMMON_CHIPID = 0,\n\tS2MPG11_COMMON_INT = 1,\n\tS2MPG11_COMMON_INT_MASK = 2,\n\tS2MPG11_COMMON_SPD_CTRL1 = 10,\n\tS2MPG11_COMMON_SPD_CTRL2 = 11,\n\tS2MPG11_COMMON_SPD_CTRL3 = 12,\n\tS2MPG11_COMMON_MON1SEL = 26,\n\tS2MPG11_COMMON_MON2SEL = 27,\n\tS2MPG11_COMMON_MONR = 28,\n\tS2MPG11_COMMON_DEBUG_CTRL1 = 29,\n\tS2MPG11_COMMON_DEBUG_CTRL2 = 30,\n\tS2MPG11_COMMON_DEBUG_CTRL3 = 31,\n\tS2MPG11_COMMON_DEBUG_CTRL4 = 32,\n\tS2MPG11_COMMON_DEBUG_CTRL5 = 33,\n\tS2MPG11_COMMON_DEBUG_CTRL6 = 34,\n\tS2MPG11_COMMON_TEST_MODE1 = 35,\n\tS2MPG11_COMMON_SPD_DEBUG1 = 36,\n\tS2MPG11_COMMON_SPD_DEBUG2 = 37,\n\tS2MPG11_COMMON_SPD_DEBUG3 = 38,\n\tS2MPG11_COMMON_SPD_DEBUG4 = 39,\n};\n\nenum s2mpg11_irq {\n\tS2MPG11_IRQ_PWRONF = 0,\n\tS2MPG11_IRQ_PWRONR = 1,\n\tS2MPG11_IRQ_PIF_TIMEOUT_MIF = 2,\n\tS2MPG11_IRQ_PIF_TIMEOUTS = 3,\n\tS2MPG11_IRQ_WTSR = 4,\n\tS2MPG11_IRQ_SPD_ABNORMAL_STOP = 5,\n\tS2MPG11_IRQ_SPD_PARITY_ERR = 6,\n\tS2MPG11_IRQ_140C = 7,\n\tS2MPG11_IRQ_120C = 8,\n\tS2MPG11_IRQ_TSD = 9,\n\tS2MPG11_IRQ_WRST = 10,\n\tS2MPG11_IRQ_NTC_CYCLE_DONE = 11,\n\tS2MPG11_IRQ_PMETER_OVERF = 12,\n\tS2MPG11_IRQ_OCP_B1S = 13,\n\tS2MPG11_IRQ_OCP_B2S = 14,\n\tS2MPG11_IRQ_OCP_B3S = 15,\n\tS2MPG11_IRQ_OCP_B4S = 16,\n\tS2MPG11_IRQ_OCP_B5S = 17,\n\tS2MPG11_IRQ_OCP_B6S = 18,\n\tS2MPG11_IRQ_OCP_B7S = 19,\n\tS2MPG11_IRQ_OCP_B8S = 20,\n\tS2MPG11_IRQ_OCP_B9S = 21,\n\tS2MPG11_IRQ_OCP_B10S = 22,\n\tS2MPG11_IRQ_OCP_BDS = 23,\n\tS2MPG11_IRQ_OCP_BAS = 24,\n\tS2MPG11_IRQ_OCP_BBS = 25,\n\tS2MPG11_IRQ_WLWP_ACC = 26,\n\tS2MPG11_IRQ_SPD_SRP_PKT_RST = 27,\n\tS2MPG11_IRQ_PWR_WARN_CH0 = 28,\n\tS2MPG11_IRQ_PWR_WARN_CH1 = 29,\n\tS2MPG11_IRQ_PWR_WARN_CH2 = 30,\n\tS2MPG11_IRQ_PWR_WARN_CH3 = 31,\n\tS2MPG11_IRQ_PWR_WARN_CH4 = 32,\n\tS2MPG11_IRQ_PWR_WARN_CH5 = 33,\n\tS2MPG11_IRQ_PWR_WARN_CH6 = 34,\n\tS2MPG11_IRQ_PWR_WARN_CH7 = 35,\n\tS2MPG11_IRQ_NTC_WARN_CH0 = 36,\n\tS2MPG11_IRQ_NTC_WARN_CH1 = 37,\n\tS2MPG11_IRQ_NTC_WARN_CH2 = 38,\n\tS2MPG11_IRQ_NTC_WARN_CH3 = 39,\n\tS2MPG11_IRQ_NTC_WARN_CH4 = 40,\n\tS2MPG11_IRQ_NTC_WARN_CH5 = 41,\n\tS2MPG11_IRQ_NTC_WARN_CH6 = 42,\n\tS2MPG11_IRQ_NTC_WARN_CH7 = 43,\n\tS2MPG11_IRQ_NR = 44,\n};\n\nenum s2mpg11_pmic_reg {\n\tS2MPG11_PMIC_INT1 = 0,\n\tS2MPG11_PMIC_INT2 = 1,\n\tS2MPG11_PMIC_INT3 = 2,\n\tS2MPG11_PMIC_INT4 = 3,\n\tS2MPG11_PMIC_INT5 = 4,\n\tS2MPG11_PMIC_INT6 = 5,\n\tS2MPG11_PMIC_INT1M = 6,\n\tS2MPG11_PMIC_INT2M = 7,\n\tS2MPG11_PMIC_INT3M = 8,\n\tS2MPG11_PMIC_INT4M = 9,\n\tS2MPG11_PMIC_INT5M = 10,\n\tS2MPG11_PMIC_INT6M = 11,\n\tS2MPG11_PMIC_STATUS1 = 12,\n\tS2MPG11_PMIC_OFFSRC = 13,\n\tS2MPG11_PMIC_COMMON_CTRL1 = 14,\n\tS2MPG11_PMIC_COMMON_CTRL2 = 15,\n\tS2MPG11_PMIC_COMMON_CTRL3 = 16,\n\tS2MPG11_PMIC_MIMICKING_CTRL = 17,\n\tS2MPG11_PMIC_B1S_CTRL = 18,\n\tS2MPG11_PMIC_B1S_OUT1 = 19,\n\tS2MPG11_PMIC_B1S_OUT2 = 20,\n\tS2MPG11_PMIC_B2S_CTRL = 21,\n\tS2MPG11_PMIC_B2S_OUT1 = 22,\n\tS2MPG11_PMIC_B2S_OUT2 = 23,\n\tS2MPG11_PMIC_B3S_CTRL = 24,\n\tS2MPG11_PMIC_B3S_OUT1 = 25,\n\tS2MPG11_PMIC_B3S_OUT2 = 26,\n\tS2MPG11_PMIC_B4S_CTRL = 27,\n\tS2MPG11_PMIC_B4S_OUT = 28,\n\tS2MPG11_PMIC_B5S_CTRL = 29,\n\tS2MPG11_PMIC_B5S_OUT = 30,\n\tS2MPG11_PMIC_B6S_CTRL = 31,\n\tS2MPG11_PMIC_B6S_OUT1 = 32,\n\tS2MPG11_PMIC_B6S_OUT2 = 33,\n\tS2MPG11_PMIC_B7S_CTRL = 34,\n\tS2MPG11_PMIC_B7S_OUT1 = 35,\n\tS2MPG11_PMIC_B7S_OUT2 = 36,\n\tS2MPG11_PMIC_B8S_CTRL = 37,\n\tS2MPG11_PMIC_B8S_OUT1 = 38,\n\tS2MPG11_PMIC_B8S_OUT2 = 39,\n\tS2MPG11_PMIC_B9S_CTRL = 40,\n\tS2MPG11_PMIC_B9S_OUT1 = 41,\n\tS2MPG11_PMIC_B9S_OUT2 = 42,\n\tS2MPG11_PMIC_B10S_CTRL = 43,\n\tS2MPG11_PMIC_B10S_OUT = 44,\n\tS2MPG11_PMIC_BUCKD_CTRL = 45,\n\tS2MPG11_PMIC_BUCKD_OUT = 46,\n\tS2MPG11_PMIC_BUCKA_CTRL = 47,\n\tS2MPG11_PMIC_BUCKA_OUT = 48,\n\tS2MPG11_PMIC_BB_CTRL = 49,\n\tS2MPG11_PMIC_BB_OUT1 = 50,\n\tS2MPG11_PMIC_BB_OUT2 = 51,\n\tS2MPG11_PMIC_BUCK1S_USONIC = 52,\n\tS2MPG11_PMIC_BUCK2S_USONIC = 53,\n\tS2MPG11_PMIC_BUCK3S_USONIC = 54,\n\tS2MPG11_PMIC_BUCK4S_USONIC = 55,\n\tS2MPG11_PMIC_BUCK5S_USONIC = 56,\n\tS2MPG11_PMIC_BUCK6S_USONIC = 57,\n\tS2MPG11_PMIC_BUCK7S_USONIC = 58,\n\tS2MPG11_PMIC_BUCK8S_USONIC = 59,\n\tS2MPG11_PMIC_BUCK9S_USONIC = 60,\n\tS2MPG11_PMIC_BUCK10S_USONIC = 61,\n\tS2MPG11_PMIC_BUCKD_USONIC = 62,\n\tS2MPG11_PMIC_BUCKA_USONIC = 63,\n\tS2MPG11_PMIC_BB_USONIC = 64,\n\tS2MPG11_PMIC_L1S_CTRL1 = 65,\n\tS2MPG11_PMIC_L1S_CTRL2 = 66,\n\tS2MPG11_PMIC_L2S_CTRL1 = 67,\n\tS2MPG11_PMIC_L2S_CTRL2 = 68,\n\tS2MPG11_PMIC_L3S_CTRL = 69,\n\tS2MPG11_PMIC_L4S_CTRL = 70,\n\tS2MPG11_PMIC_L5S_CTRL = 71,\n\tS2MPG11_PMIC_L6S_CTRL = 72,\n\tS2MPG11_PMIC_L7S_CTRL = 73,\n\tS2MPG11_PMIC_L8S_CTRL = 74,\n\tS2MPG11_PMIC_L9S_CTRL = 75,\n\tS2MPG11_PMIC_L10S_CTRL = 76,\n\tS2MPG11_PMIC_L11S_CTRL = 77,\n\tS2MPG11_PMIC_L12S_CTRL = 78,\n\tS2MPG11_PMIC_L13S_CTRL = 79,\n\tS2MPG11_PMIC_L14S_CTRL = 80,\n\tS2MPG11_PMIC_L15S_CTRL = 81,\n\tS2MPG11_PMIC_LDO_CTRL1 = 82,\n\tS2MPG11_PMIC_LDO_DSCH1 = 83,\n\tS2MPG11_PMIC_LDO_DSCH2 = 84,\n\tS2MPG11_PMIC_DVS_RAMP1 = 85,\n\tS2MPG11_PMIC_DVS_RAMP2 = 86,\n\tS2MPG11_PMIC_DVS_RAMP3 = 87,\n\tS2MPG11_PMIC_DVS_RAMP4 = 88,\n\tS2MPG11_PMIC_DVS_RAMP5 = 89,\n\tS2MPG11_PMIC_DVS_RAMP6 = 90,\n\tS2MPG11_PMIC_DVS_SYNC_CTRL1 = 92,\n\tS2MPG11_PMIC_DVS_SYNC_CTRL2 = 93,\n\tS2MPG11_PMIC_OFF_CTRL1 = 94,\n\tS2MPG11_PMIC_OFF_CTRL2 = 95,\n\tS2MPG11_PMIC_OFF_CTRL3 = 96,\n\tS2MPG11_PMIC_SEQ_CTRL1 = 97,\n\tS2MPG11_PMIC_SEQ_CTRL2 = 98,\n\tS2MPG11_PMIC_SEQ_CTRL3 = 99,\n\tS2MPG11_PMIC_SEQ_CTRL4 = 100,\n\tS2MPG11_PMIC_SEQ_CTRL5 = 101,\n\tS2MPG11_PMIC_SEQ_CTRL6 = 102,\n\tS2MPG11_PMIC_SEQ_CTRL7 = 103,\n\tS2MPG11_PMIC_SEQ_CTRL8 = 104,\n\tS2MPG11_PMIC_SEQ_CTRL9 = 105,\n\tS2MPG11_PMIC_SEQ_CTRL10 = 106,\n\tS2MPG11_PMIC_SEQ_CTRL11 = 107,\n\tS2MPG11_PMIC_SEQ_CTRL12 = 108,\n\tS2MPG11_PMIC_SEQ_CTRL13 = 109,\n\tS2MPG11_PMIC_SEQ_CTRL14 = 110,\n\tS2MPG11_PMIC_SEQ_CTRL15 = 111,\n\tS2MPG11_PMIC_SEQ_CTRL16 = 112,\n\tS2MPG11_PMIC_SEQ_CTRL17 = 113,\n\tS2MPG11_PMIC_SEQ_CTRL18 = 114,\n\tS2MPG11_PMIC_SEQ_CTRL19 = 115,\n\tS2MPG11_PMIC_SEQ_CTRL20 = 116,\n\tS2MPG11_PMIC_SEQ_CTRL21 = 117,\n\tS2MPG11_PMIC_SEQ_CTRL22 = 118,\n\tS2MPG11_PMIC_SEQ_CTRL23 = 119,\n\tS2MPG11_PMIC_SEQ_CTRL24 = 120,\n\tS2MPG11_PMIC_SEQ_CTRL25 = 121,\n\tS2MPG11_PMIC_SEQ_CTRL26 = 122,\n\tS2MPG11_PMIC_SEQ_CTRL27 = 123,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL1 = 124,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL2 = 125,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL3 = 126,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL4 = 127,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL5 = 128,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL6 = 129,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL7 = 130,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL8 = 131,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL9 = 132,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL10 = 133,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL11 = 134,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL12 = 135,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL13 = 136,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL14 = 137,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL15 = 138,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL16 = 139,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL17 = 140,\n\tS2MPG11_PMIC_PCTRLSEL1 = 141,\n\tS2MPG11_PMIC_PCTRLSEL2 = 142,\n\tS2MPG11_PMIC_PCTRLSEL3 = 143,\n\tS2MPG11_PMIC_PCTRLSEL4 = 144,\n\tS2MPG11_PMIC_PCTRLSEL5 = 145,\n\tS2MPG11_PMIC_PCTRLSEL6 = 146,\n\tS2MPG11_PMIC_DCTRLSEL1 = 147,\n\tS2MPG11_PMIC_DCTRLSEL2 = 148,\n\tS2MPG11_PMIC_DCTRLSEL3 = 149,\n\tS2MPG11_PMIC_DCTRLSEL4 = 150,\n\tS2MPG11_PMIC_DCTRLSEL5 = 151,\n\tS2MPG11_PMIC_GPIO_CTRL1 = 152,\n\tS2MPG11_PMIC_GPIO_CTRL2 = 153,\n\tS2MPG11_PMIC_GPIO_CTRL3 = 154,\n\tS2MPG11_PMIC_GPIO_CTRL4 = 155,\n\tS2MPG11_PMIC_GPIO_CTRL5 = 156,\n\tS2MPG11_PMIC_GPIO_CTRL6 = 157,\n\tS2MPG11_PMIC_GPIO_CTRL7 = 158,\n\tS2MPG11_PMIC_B2S_OCP_WARN = 159,\n\tS2MPG11_PMIC_B2S_OCP_WARN_X = 160,\n\tS2MPG11_PMIC_B2S_OCP_WARN_Y = 161,\n\tS2MPG11_PMIC_B2S_OCP_WARN_Z = 162,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN = 163,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN_X = 164,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y = 165,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z = 166,\n\tS2MPG11_PMIC_BUCK_OCP_EN1 = 167,\n\tS2MPG11_PMIC_BUCK_OCP_EN2 = 168,\n\tS2MPG11_PMIC_BUCK_OCP_PD_EN1 = 169,\n\tS2MPG11_PMIC_BUCK_OCP_PD_EN2 = 170,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL1 = 171,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL2 = 172,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL3 = 173,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL4 = 174,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL5 = 175,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL6 = 176,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL7 = 177,\n\tS2MPG11_PMIC_PIF_CTRL = 178,\n\tS2MPG11_PMIC_BUCK_HR_MODE1 = 179,\n\tS2MPG11_PMIC_BUCK_HR_MODE2 = 180,\n\tS2MPG11_PMIC_FAULTOUT_CTRL = 181,\n\tS2MPG11_PMIC_LDO_SENSE1 = 182,\n\tS2MPG11_PMIC_LDO_SENSE2 = 183,\n};\n\nenum s2mpg11_regulators {\n\tS2MPG11_BUCKBOOST = 0,\n\tS2MPG11_BUCK1 = 1,\n\tS2MPG11_BUCK2 = 2,\n\tS2MPG11_BUCK3 = 3,\n\tS2MPG11_BUCK4 = 4,\n\tS2MPG11_BUCK5 = 5,\n\tS2MPG11_BUCK6 = 6,\n\tS2MPG11_BUCK7 = 7,\n\tS2MPG11_BUCK8 = 8,\n\tS2MPG11_BUCK9 = 9,\n\tS2MPG11_BUCK10 = 10,\n\tS2MPG11_BUCKD = 11,\n\tS2MPG11_BUCKA = 12,\n\tS2MPG11_LDO1 = 13,\n\tS2MPG11_LDO2 = 14,\n\tS2MPG11_LDO3 = 15,\n\tS2MPG11_LDO4 = 16,\n\tS2MPG11_LDO5 = 17,\n\tS2MPG11_LDO6 = 18,\n\tS2MPG11_LDO7 = 19,\n\tS2MPG11_LDO8 = 20,\n\tS2MPG11_LDO9 = 21,\n\tS2MPG11_LDO10 = 22,\n\tS2MPG11_LDO11 = 23,\n\tS2MPG11_LDO12 = 24,\n\tS2MPG11_LDO13 = 25,\n\tS2MPG11_LDO14 = 26,\n\tS2MPG11_LDO15 = 27,\n\tS2MPG11_REGULATOR_MAX = 28,\n};\n\nenum s2mps11_irq {\n\tS2MPS11_IRQ_PWRONF = 0,\n\tS2MPS11_IRQ_PWRONR = 1,\n\tS2MPS11_IRQ_JIGONBF = 2,\n\tS2MPS11_IRQ_JIGONBR = 3,\n\tS2MPS11_IRQ_ACOKBF = 4,\n\tS2MPS11_IRQ_ACOKBR = 5,\n\tS2MPS11_IRQ_PWRON1S = 6,\n\tS2MPS11_IRQ_MRB = 7,\n\tS2MPS11_IRQ_RTC60S = 8,\n\tS2MPS11_IRQ_RTCA1 = 9,\n\tS2MPS11_IRQ_RTCA0 = 10,\n\tS2MPS11_IRQ_SMPL = 11,\n\tS2MPS11_IRQ_RTC1S = 12,\n\tS2MPS11_IRQ_WTSR = 13,\n\tS2MPS11_IRQ_INT120C = 14,\n\tS2MPS11_IRQ_INT140C = 15,\n\tS2MPS11_IRQ_NR = 16,\n};\n\nenum s2mps11_reg {\n\tS2MPS11_REG_ID = 0,\n\tS2MPS11_REG_INT1 = 1,\n\tS2MPS11_REG_INT2 = 2,\n\tS2MPS11_REG_INT3 = 3,\n\tS2MPS11_REG_INT1M = 4,\n\tS2MPS11_REG_INT2M = 5,\n\tS2MPS11_REG_INT3M = 6,\n\tS2MPS11_REG_ST1 = 7,\n\tS2MPS11_REG_ST2 = 8,\n\tS2MPS11_REG_OFFSRC = 9,\n\tS2MPS11_REG_PWRONSRC = 10,\n\tS2MPS11_REG_RTC_CTRL = 11,\n\tS2MPS11_REG_CTRL1 = 12,\n\tS2MPS11_REG_ETC_TEST = 13,\n\tS2MPS11_REG_RSVD3 = 14,\n\tS2MPS11_REG_BU_CHG = 15,\n\tS2MPS11_REG_RAMP = 16,\n\tS2MPS11_REG_RAMP_BUCK = 17,\n\tS2MPS11_REG_LDO1_8 = 18,\n\tS2MPS11_REG_LDO9_16 = 19,\n\tS2MPS11_REG_LDO17_24 = 20,\n\tS2MPS11_REG_LDO25_32 = 21,\n\tS2MPS11_REG_LDO33_38 = 22,\n\tS2MPS11_REG_LDO1_8_1 = 23,\n\tS2MPS11_REG_LDO9_16_1 = 24,\n\tS2MPS11_REG_LDO17_24_1 = 25,\n\tS2MPS11_REG_LDO25_32_1 = 26,\n\tS2MPS11_REG_LDO33_38_1 = 27,\n\tS2MPS11_REG_OTP_ADRL = 28,\n\tS2MPS11_REG_OTP_ADRH = 29,\n\tS2MPS11_REG_OTP_DATA = 30,\n\tS2MPS11_REG_MON1SEL = 31,\n\tS2MPS11_REG_MON2SEL = 32,\n\tS2MPS11_REG_LEE = 33,\n\tS2MPS11_REG_RSVD_NO = 34,\n\tS2MPS11_REG_UVLO = 35,\n\tS2MPS11_REG_LEE_NO = 36,\n\tS2MPS11_REG_B1CTRL1 = 37,\n\tS2MPS11_REG_B1CTRL2 = 38,\n\tS2MPS11_REG_B2CTRL1 = 39,\n\tS2MPS11_REG_B2CTRL2 = 40,\n\tS2MPS11_REG_B3CTRL1 = 41,\n\tS2MPS11_REG_B3CTRL2 = 42,\n\tS2MPS11_REG_B4CTRL1 = 43,\n\tS2MPS11_REG_B4CTRL2 = 44,\n\tS2MPS11_REG_B5CTRL1 = 45,\n\tS2MPS11_REG_BUCK5_SW = 46,\n\tS2MPS11_REG_B5CTRL2 = 47,\n\tS2MPS11_REG_B5CTRL3 = 48,\n\tS2MPS11_REG_B5CTRL4 = 49,\n\tS2MPS11_REG_B5CTRL5 = 50,\n\tS2MPS11_REG_B6CTRL1 = 51,\n\tS2MPS11_REG_B6CTRL2 = 52,\n\tS2MPS11_REG_B7CTRL1 = 53,\n\tS2MPS11_REG_B7CTRL2 = 54,\n\tS2MPS11_REG_B8CTRL1 = 55,\n\tS2MPS11_REG_B8CTRL2 = 56,\n\tS2MPS11_REG_B9CTRL1 = 57,\n\tS2MPS11_REG_B9CTRL2 = 58,\n\tS2MPS11_REG_B10CTRL1 = 59,\n\tS2MPS11_REG_B10CTRL2 = 60,\n\tS2MPS11_REG_L1CTRL = 61,\n\tS2MPS11_REG_L2CTRL = 62,\n\tS2MPS11_REG_L3CTRL = 63,\n\tS2MPS11_REG_L4CTRL = 64,\n\tS2MPS11_REG_L5CTRL = 65,\n\tS2MPS11_REG_L6CTRL = 66,\n\tS2MPS11_REG_L7CTRL = 67,\n\tS2MPS11_REG_L8CTRL = 68,\n\tS2MPS11_REG_L9CTRL = 69,\n\tS2MPS11_REG_L10CTRL = 70,\n\tS2MPS11_REG_L11CTRL = 71,\n\tS2MPS11_REG_L12CTRL = 72,\n\tS2MPS11_REG_L13CTRL = 73,\n\tS2MPS11_REG_L14CTRL = 74,\n\tS2MPS11_REG_L15CTRL = 75,\n\tS2MPS11_REG_L16CTRL = 76,\n\tS2MPS11_REG_L17CTRL = 77,\n\tS2MPS11_REG_L18CTRL = 78,\n\tS2MPS11_REG_L19CTRL = 79,\n\tS2MPS11_REG_L20CTRL = 80,\n\tS2MPS11_REG_L21CTRL = 81,\n\tS2MPS11_REG_L22CTRL = 82,\n\tS2MPS11_REG_L23CTRL = 83,\n\tS2MPS11_REG_L24CTRL = 84,\n\tS2MPS11_REG_L25CTRL = 85,\n\tS2MPS11_REG_L26CTRL = 86,\n\tS2MPS11_REG_L27CTRL = 87,\n\tS2MPS11_REG_L28CTRL = 88,\n\tS2MPS11_REG_L29CTRL = 89,\n\tS2MPS11_REG_L30CTRL = 90,\n\tS2MPS11_REG_L31CTRL = 91,\n\tS2MPS11_REG_L32CTRL = 92,\n\tS2MPS11_REG_L33CTRL = 93,\n\tS2MPS11_REG_L34CTRL = 94,\n\tS2MPS11_REG_L35CTRL = 95,\n\tS2MPS11_REG_L36CTRL = 96,\n\tS2MPS11_REG_L37CTRL = 97,\n\tS2MPS11_REG_L38CTRL = 98,\n};\n\nenum s2mps11_regulators {\n\tS2MPS11_LDO1 = 0,\n\tS2MPS11_LDO2 = 1,\n\tS2MPS11_LDO3 = 2,\n\tS2MPS11_LDO4 = 3,\n\tS2MPS11_LDO5 = 4,\n\tS2MPS11_LDO6 = 5,\n\tS2MPS11_LDO7 = 6,\n\tS2MPS11_LDO8 = 7,\n\tS2MPS11_LDO9 = 8,\n\tS2MPS11_LDO10 = 9,\n\tS2MPS11_LDO11 = 10,\n\tS2MPS11_LDO12 = 11,\n\tS2MPS11_LDO13 = 12,\n\tS2MPS11_LDO14 = 13,\n\tS2MPS11_LDO15 = 14,\n\tS2MPS11_LDO16 = 15,\n\tS2MPS11_LDO17 = 16,\n\tS2MPS11_LDO18 = 17,\n\tS2MPS11_LDO19 = 18,\n\tS2MPS11_LDO20 = 19,\n\tS2MPS11_LDO21 = 20,\n\tS2MPS11_LDO22 = 21,\n\tS2MPS11_LDO23 = 22,\n\tS2MPS11_LDO24 = 23,\n\tS2MPS11_LDO25 = 24,\n\tS2MPS11_LDO26 = 25,\n\tS2MPS11_LDO27 = 26,\n\tS2MPS11_LDO28 = 27,\n\tS2MPS11_LDO29 = 28,\n\tS2MPS11_LDO30 = 29,\n\tS2MPS11_LDO31 = 30,\n\tS2MPS11_LDO32 = 31,\n\tS2MPS11_LDO33 = 32,\n\tS2MPS11_LDO34 = 33,\n\tS2MPS11_LDO35 = 34,\n\tS2MPS11_LDO36 = 35,\n\tS2MPS11_LDO37 = 36,\n\tS2MPS11_LDO38 = 37,\n\tS2MPS11_BUCK1 = 38,\n\tS2MPS11_BUCK2 = 39,\n\tS2MPS11_BUCK3 = 40,\n\tS2MPS11_BUCK4 = 41,\n\tS2MPS11_BUCK5 = 42,\n\tS2MPS11_BUCK6 = 43,\n\tS2MPS11_BUCK7 = 44,\n\tS2MPS11_BUCK8 = 45,\n\tS2MPS11_BUCK9 = 46,\n\tS2MPS11_BUCK10 = 47,\n\tS2MPS11_REGULATOR_MAX = 48,\n};\n\nenum s2mps13_reg {\n\tS2MPS13_REG_ID = 0,\n\tS2MPS13_REG_INT1 = 1,\n\tS2MPS13_REG_INT2 = 2,\n\tS2MPS13_REG_INT3 = 3,\n\tS2MPS13_REG_INT1M = 4,\n\tS2MPS13_REG_INT2M = 5,\n\tS2MPS13_REG_INT3M = 6,\n\tS2MPS13_REG_ST1 = 7,\n\tS2MPS13_REG_ST2 = 8,\n\tS2MPS13_REG_PWRONSRC = 9,\n\tS2MPS13_REG_OFFSRC = 10,\n\tS2MPS13_REG_BU_CHG = 11,\n\tS2MPS13_REG_RTCCTRL = 12,\n\tS2MPS13_REG_CTRL1 = 13,\n\tS2MPS13_REG_CTRL2 = 14,\n\tS2MPS13_REG_RSVD1 = 15,\n\tS2MPS13_REG_RSVD2 = 16,\n\tS2MPS13_REG_RSVD3 = 17,\n\tS2MPS13_REG_RSVD4 = 18,\n\tS2MPS13_REG_RSVD5 = 19,\n\tS2MPS13_REG_RSVD6 = 20,\n\tS2MPS13_REG_CTRL3 = 21,\n\tS2MPS13_REG_RSVD7 = 22,\n\tS2MPS13_REG_RSVD8 = 23,\n\tS2MPS13_REG_WRSTBI = 24,\n\tS2MPS13_REG_B1CTRL = 25,\n\tS2MPS13_REG_B1OUT = 26,\n\tS2MPS13_REG_B2CTRL = 27,\n\tS2MPS13_REG_B2OUT = 28,\n\tS2MPS13_REG_B3CTRL = 29,\n\tS2MPS13_REG_B3OUT = 30,\n\tS2MPS13_REG_B4CTRL = 31,\n\tS2MPS13_REG_B4OUT = 32,\n\tS2MPS13_REG_B5CTRL = 33,\n\tS2MPS13_REG_B5OUT = 34,\n\tS2MPS13_REG_B6CTRL = 35,\n\tS2MPS13_REG_B6OUT = 36,\n\tS2MPS13_REG_B7CTRL = 37,\n\tS2MPS13_REG_B7SW = 38,\n\tS2MPS13_REG_B7OUT = 39,\n\tS2MPS13_REG_B8CTRL = 40,\n\tS2MPS13_REG_B8OUT = 41,\n\tS2MPS13_REG_B9CTRL = 42,\n\tS2MPS13_REG_B9OUT = 43,\n\tS2MPS13_REG_B10CTRL = 44,\n\tS2MPS13_REG_B10OUT = 45,\n\tS2MPS13_REG_BB1CTRL = 46,\n\tS2MPS13_REG_BB1OUT = 47,\n\tS2MPS13_REG_BUCK_RAMP1 = 48,\n\tS2MPS13_REG_BUCK_RAMP2 = 49,\n\tS2MPS13_REG_LDO_DVS1 = 50,\n\tS2MPS13_REG_LDO_DVS2 = 51,\n\tS2MPS13_REG_LDO_DVS3 = 52,\n\tS2MPS13_REG_B6OUT2 = 53,\n\tS2MPS13_REG_L1CTRL = 54,\n\tS2MPS13_REG_L2CTRL = 55,\n\tS2MPS13_REG_L3CTRL = 56,\n\tS2MPS13_REG_L4CTRL = 57,\n\tS2MPS13_REG_L5CTRL = 58,\n\tS2MPS13_REG_L6CTRL = 59,\n\tS2MPS13_REG_L7CTRL = 60,\n\tS2MPS13_REG_L8CTRL = 61,\n\tS2MPS13_REG_L9CTRL = 62,\n\tS2MPS13_REG_L10CTRL = 63,\n\tS2MPS13_REG_L11CTRL = 64,\n\tS2MPS13_REG_L12CTRL = 65,\n\tS2MPS13_REG_L13CTRL = 66,\n\tS2MPS13_REG_L14CTRL = 67,\n\tS2MPS13_REG_L15CTRL = 68,\n\tS2MPS13_REG_L16CTRL = 69,\n\tS2MPS13_REG_L17CTRL = 70,\n\tS2MPS13_REG_L18CTRL = 71,\n\tS2MPS13_REG_L19CTRL = 72,\n\tS2MPS13_REG_L20CTRL = 73,\n\tS2MPS13_REG_L21CTRL = 74,\n\tS2MPS13_REG_L22CTRL = 75,\n\tS2MPS13_REG_L23CTRL = 76,\n\tS2MPS13_REG_L24CTRL = 77,\n\tS2MPS13_REG_L25CTRL = 78,\n\tS2MPS13_REG_L26CTRL = 79,\n\tS2MPS13_REG_L27CTRL = 80,\n\tS2MPS13_REG_L28CTRL = 81,\n\tS2MPS13_REG_L29CTRL = 82,\n\tS2MPS13_REG_L30CTRL = 83,\n\tS2MPS13_REG_L31CTRL = 84,\n\tS2MPS13_REG_L32CTRL = 85,\n\tS2MPS13_REG_L33CTRL = 86,\n\tS2MPS13_REG_L34CTRL = 87,\n\tS2MPS13_REG_L35CTRL = 88,\n\tS2MPS13_REG_L36CTRL = 89,\n\tS2MPS13_REG_L37CTRL = 90,\n\tS2MPS13_REG_L38CTRL = 91,\n\tS2MPS13_REG_L39CTRL = 92,\n\tS2MPS13_REG_L40CTRL = 93,\n\tS2MPS13_REG_LDODSCH1 = 94,\n\tS2MPS13_REG_LDODSCH2 = 95,\n\tS2MPS13_REG_LDODSCH3 = 96,\n\tS2MPS13_REG_LDODSCH4 = 97,\n\tS2MPS13_REG_LDODSCH5 = 98,\n};\n\nenum s2mps13_regulators {\n\tS2MPS13_LDO1 = 0,\n\tS2MPS13_LDO2 = 1,\n\tS2MPS13_LDO3 = 2,\n\tS2MPS13_LDO4 = 3,\n\tS2MPS13_LDO5 = 4,\n\tS2MPS13_LDO6 = 5,\n\tS2MPS13_LDO7 = 6,\n\tS2MPS13_LDO8 = 7,\n\tS2MPS13_LDO9 = 8,\n\tS2MPS13_LDO10 = 9,\n\tS2MPS13_LDO11 = 10,\n\tS2MPS13_LDO12 = 11,\n\tS2MPS13_LDO13 = 12,\n\tS2MPS13_LDO14 = 13,\n\tS2MPS13_LDO15 = 14,\n\tS2MPS13_LDO16 = 15,\n\tS2MPS13_LDO17 = 16,\n\tS2MPS13_LDO18 = 17,\n\tS2MPS13_LDO19 = 18,\n\tS2MPS13_LDO20 = 19,\n\tS2MPS13_LDO21 = 20,\n\tS2MPS13_LDO22 = 21,\n\tS2MPS13_LDO23 = 22,\n\tS2MPS13_LDO24 = 23,\n\tS2MPS13_LDO25 = 24,\n\tS2MPS13_LDO26 = 25,\n\tS2MPS13_LDO27 = 26,\n\tS2MPS13_LDO28 = 27,\n\tS2MPS13_LDO29 = 28,\n\tS2MPS13_LDO30 = 29,\n\tS2MPS13_LDO31 = 30,\n\tS2MPS13_LDO32 = 31,\n\tS2MPS13_LDO33 = 32,\n\tS2MPS13_LDO34 = 33,\n\tS2MPS13_LDO35 = 34,\n\tS2MPS13_LDO36 = 35,\n\tS2MPS13_LDO37 = 36,\n\tS2MPS13_LDO38 = 37,\n\tS2MPS13_LDO39 = 38,\n\tS2MPS13_LDO40 = 39,\n\tS2MPS13_BUCK1 = 40,\n\tS2MPS13_BUCK2 = 41,\n\tS2MPS13_BUCK3 = 42,\n\tS2MPS13_BUCK4 = 43,\n\tS2MPS13_BUCK5 = 44,\n\tS2MPS13_BUCK6 = 45,\n\tS2MPS13_BUCK7 = 46,\n\tS2MPS13_BUCK8 = 47,\n\tS2MPS13_BUCK9 = 48,\n\tS2MPS13_BUCK10 = 49,\n\tS2MPS13_REGULATOR_MAX = 50,\n};\n\nenum s2mps14_irq {\n\tS2MPS14_IRQ_PWRONF = 0,\n\tS2MPS14_IRQ_PWRONR = 1,\n\tS2MPS14_IRQ_JIGONBF = 2,\n\tS2MPS14_IRQ_JIGONBR = 3,\n\tS2MPS14_IRQ_ACOKBF = 4,\n\tS2MPS14_IRQ_ACOKBR = 5,\n\tS2MPS14_IRQ_PWRON1S = 6,\n\tS2MPS14_IRQ_MRB = 7,\n\tS2MPS14_IRQ_RTC60S = 8,\n\tS2MPS14_IRQ_RTCA1 = 9,\n\tS2MPS14_IRQ_RTCA0 = 10,\n\tS2MPS14_IRQ_SMPL = 11,\n\tS2MPS14_IRQ_RTC1S = 12,\n\tS2MPS14_IRQ_WTSR = 13,\n\tS2MPS14_IRQ_INT120C = 14,\n\tS2MPS14_IRQ_INT140C = 15,\n\tS2MPS14_IRQ_TSD = 16,\n\tS2MPS14_IRQ_NR = 17,\n};\n\nenum s2mps14_reg {\n\tS2MPS14_REG_ID = 0,\n\tS2MPS14_REG_INT1 = 1,\n\tS2MPS14_REG_INT2 = 2,\n\tS2MPS14_REG_INT3 = 3,\n\tS2MPS14_REG_INT1M = 4,\n\tS2MPS14_REG_INT2M = 5,\n\tS2MPS14_REG_INT3M = 6,\n\tS2MPS14_REG_ST1 = 7,\n\tS2MPS14_REG_ST2 = 8,\n\tS2MPS14_REG_PWRONSRC = 9,\n\tS2MPS14_REG_OFFSRC = 10,\n\tS2MPS14_REG_BU_CHG = 11,\n\tS2MPS14_REG_RTCCTRL = 12,\n\tS2MPS14_REG_CTRL1 = 13,\n\tS2MPS14_REG_CTRL2 = 14,\n\tS2MPS14_REG_RSVD1 = 15,\n\tS2MPS14_REG_RSVD2 = 16,\n\tS2MPS14_REG_RSVD3 = 17,\n\tS2MPS14_REG_RSVD4 = 18,\n\tS2MPS14_REG_RSVD5 = 19,\n\tS2MPS14_REG_RSVD6 = 20,\n\tS2MPS14_REG_CTRL3 = 21,\n\tS2MPS14_REG_RSVD7 = 22,\n\tS2MPS14_REG_RSVD8 = 23,\n\tS2MPS14_REG_WRSTBI = 24,\n\tS2MPS14_REG_B1CTRL1 = 25,\n\tS2MPS14_REG_B1CTRL2 = 26,\n\tS2MPS14_REG_B2CTRL1 = 27,\n\tS2MPS14_REG_B2CTRL2 = 28,\n\tS2MPS14_REG_B3CTRL1 = 29,\n\tS2MPS14_REG_B3CTRL2 = 30,\n\tS2MPS14_REG_B4CTRL1 = 31,\n\tS2MPS14_REG_B4CTRL2 = 32,\n\tS2MPS14_REG_B5CTRL1 = 33,\n\tS2MPS14_REG_B5CTRL2 = 34,\n\tS2MPS14_REG_L1CTRL = 35,\n\tS2MPS14_REG_L2CTRL = 36,\n\tS2MPS14_REG_L3CTRL = 37,\n\tS2MPS14_REG_L4CTRL = 38,\n\tS2MPS14_REG_L5CTRL = 39,\n\tS2MPS14_REG_L6CTRL = 40,\n\tS2MPS14_REG_L7CTRL = 41,\n\tS2MPS14_REG_L8CTRL = 42,\n\tS2MPS14_REG_L9CTRL = 43,\n\tS2MPS14_REG_L10CTRL = 44,\n\tS2MPS14_REG_L11CTRL = 45,\n\tS2MPS14_REG_L12CTRL = 46,\n\tS2MPS14_REG_L13CTRL = 47,\n\tS2MPS14_REG_L14CTRL = 48,\n\tS2MPS14_REG_L15CTRL = 49,\n\tS2MPS14_REG_L16CTRL = 50,\n\tS2MPS14_REG_L17CTRL = 51,\n\tS2MPS14_REG_L18CTRL = 52,\n\tS2MPS14_REG_L19CTRL = 53,\n\tS2MPS14_REG_L20CTRL = 54,\n\tS2MPS14_REG_L21CTRL = 55,\n\tS2MPS14_REG_L22CTRL = 56,\n\tS2MPS14_REG_L23CTRL = 57,\n\tS2MPS14_REG_L24CTRL = 58,\n\tS2MPS14_REG_L25CTRL = 59,\n\tS2MPS14_REG_LDODSCH1 = 60,\n\tS2MPS14_REG_LDODSCH2 = 61,\n\tS2MPS14_REG_LDODSCH3 = 62,\n};\n\nenum s2mps14_regulators {\n\tS2MPS14_LDO1 = 0,\n\tS2MPS14_LDO2 = 1,\n\tS2MPS14_LDO3 = 2,\n\tS2MPS14_LDO4 = 3,\n\tS2MPS14_LDO5 = 4,\n\tS2MPS14_LDO6 = 5,\n\tS2MPS14_LDO7 = 6,\n\tS2MPS14_LDO8 = 7,\n\tS2MPS14_LDO9 = 8,\n\tS2MPS14_LDO10 = 9,\n\tS2MPS14_LDO11 = 10,\n\tS2MPS14_LDO12 = 11,\n\tS2MPS14_LDO13 = 12,\n\tS2MPS14_LDO14 = 13,\n\tS2MPS14_LDO15 = 14,\n\tS2MPS14_LDO16 = 15,\n\tS2MPS14_LDO17 = 16,\n\tS2MPS14_LDO18 = 17,\n\tS2MPS14_LDO19 = 18,\n\tS2MPS14_LDO20 = 19,\n\tS2MPS14_LDO21 = 20,\n\tS2MPS14_LDO22 = 21,\n\tS2MPS14_LDO23 = 22,\n\tS2MPS14_LDO24 = 23,\n\tS2MPS14_LDO25 = 24,\n\tS2MPS14_BUCK1 = 25,\n\tS2MPS14_BUCK2 = 26,\n\tS2MPS14_BUCK3 = 27,\n\tS2MPS14_BUCK4 = 28,\n\tS2MPS14_BUCK5 = 29,\n\tS2MPS14_REGULATOR_MAX = 30,\n};\n\nenum s2mps15_reg {\n\tS2MPS15_REG_ID = 0,\n\tS2MPS15_REG_INT1 = 1,\n\tS2MPS15_REG_INT2 = 2,\n\tS2MPS15_REG_INT3 = 3,\n\tS2MPS15_REG_INT1M = 4,\n\tS2MPS15_REG_INT2M = 5,\n\tS2MPS15_REG_INT3M = 6,\n\tS2MPS15_REG_ST1 = 7,\n\tS2MPS15_REG_ST2 = 8,\n\tS2MPS15_REG_PWRONSRC = 9,\n\tS2MPS15_REG_OFFSRC = 10,\n\tS2MPS15_REG_BU_CHG = 11,\n\tS2MPS15_REG_RTC_BUF = 12,\n\tS2MPS15_REG_CTRL1 = 13,\n\tS2MPS15_REG_CTRL2 = 14,\n\tS2MPS15_REG_RSVD1 = 15,\n\tS2MPS15_REG_RSVD2 = 16,\n\tS2MPS15_REG_RSVD3 = 17,\n\tS2MPS15_REG_RSVD4 = 18,\n\tS2MPS15_REG_RSVD5 = 19,\n\tS2MPS15_REG_RSVD6 = 20,\n\tS2MPS15_REG_CTRL3 = 21,\n\tS2MPS15_REG_RSVD7 = 22,\n\tS2MPS15_REG_RSVD8 = 23,\n\tS2MPS15_REG_RSVD9 = 24,\n\tS2MPS15_REG_B1CTRL1 = 25,\n\tS2MPS15_REG_B1CTRL2 = 26,\n\tS2MPS15_REG_B2CTRL1 = 27,\n\tS2MPS15_REG_B2CTRL2 = 28,\n\tS2MPS15_REG_B3CTRL1 = 29,\n\tS2MPS15_REG_B3CTRL2 = 30,\n\tS2MPS15_REG_B4CTRL1 = 31,\n\tS2MPS15_REG_B4CTRL2 = 32,\n\tS2MPS15_REG_B5CTRL1 = 33,\n\tS2MPS15_REG_B5CTRL2 = 34,\n\tS2MPS15_REG_B6CTRL1 = 35,\n\tS2MPS15_REG_B6CTRL2 = 36,\n\tS2MPS15_REG_B7CTRL1 = 37,\n\tS2MPS15_REG_B7CTRL2 = 38,\n\tS2MPS15_REG_B8CTRL1 = 39,\n\tS2MPS15_REG_B8CTRL2 = 40,\n\tS2MPS15_REG_B9CTRL1 = 41,\n\tS2MPS15_REG_B9CTRL2 = 42,\n\tS2MPS15_REG_B10CTRL1 = 43,\n\tS2MPS15_REG_B10CTRL2 = 44,\n\tS2MPS15_REG_BBCTRL1 = 45,\n\tS2MPS15_REG_BBCTRL2 = 46,\n\tS2MPS15_REG_BRAMP = 47,\n\tS2MPS15_REG_LDODVS1 = 48,\n\tS2MPS15_REG_LDODVS2 = 49,\n\tS2MPS15_REG_LDODVS3 = 50,\n\tS2MPS15_REG_LDODVS4 = 51,\n\tS2MPS15_REG_L1CTRL = 52,\n\tS2MPS15_REG_L2CTRL = 53,\n\tS2MPS15_REG_L3CTRL = 54,\n\tS2MPS15_REG_L4CTRL = 55,\n\tS2MPS15_REG_L5CTRL = 56,\n\tS2MPS15_REG_L6CTRL = 57,\n\tS2MPS15_REG_L7CTRL = 58,\n\tS2MPS15_REG_L8CTRL = 59,\n\tS2MPS15_REG_L9CTRL = 60,\n\tS2MPS15_REG_L10CTRL = 61,\n\tS2MPS15_REG_L11CTRL = 62,\n\tS2MPS15_REG_L12CTRL = 63,\n\tS2MPS15_REG_L13CTRL = 64,\n\tS2MPS15_REG_L14CTRL = 65,\n\tS2MPS15_REG_L15CTRL = 66,\n\tS2MPS15_REG_L16CTRL = 67,\n\tS2MPS15_REG_L17CTRL = 68,\n\tS2MPS15_REG_L18CTRL = 69,\n\tS2MPS15_REG_L19CTRL = 70,\n\tS2MPS15_REG_L20CTRL = 71,\n\tS2MPS15_REG_L21CTRL = 72,\n\tS2MPS15_REG_L22CTRL = 73,\n\tS2MPS15_REG_L23CTRL = 74,\n\tS2MPS15_REG_L24CTRL = 75,\n\tS2MPS15_REG_L25CTRL = 76,\n\tS2MPS15_REG_L26CTRL = 77,\n\tS2MPS15_REG_L27CTRL = 78,\n\tS2MPS15_REG_LDODSCH1 = 79,\n\tS2MPS15_REG_LDODSCH2 = 80,\n\tS2MPS15_REG_LDODSCH3 = 81,\n\tS2MPS15_REG_LDODSCH4 = 82,\n};\n\nenum s2mps15_regulators {\n\tS2MPS15_LDO1 = 0,\n\tS2MPS15_LDO2 = 1,\n\tS2MPS15_LDO3 = 2,\n\tS2MPS15_LDO4 = 3,\n\tS2MPS15_LDO5 = 4,\n\tS2MPS15_LDO6 = 5,\n\tS2MPS15_LDO7 = 6,\n\tS2MPS15_LDO8 = 7,\n\tS2MPS15_LDO9 = 8,\n\tS2MPS15_LDO10 = 9,\n\tS2MPS15_LDO11 = 10,\n\tS2MPS15_LDO12 = 11,\n\tS2MPS15_LDO13 = 12,\n\tS2MPS15_LDO14 = 13,\n\tS2MPS15_LDO15 = 14,\n\tS2MPS15_LDO16 = 15,\n\tS2MPS15_LDO17 = 16,\n\tS2MPS15_LDO18 = 17,\n\tS2MPS15_LDO19 = 18,\n\tS2MPS15_LDO20 = 19,\n\tS2MPS15_LDO21 = 20,\n\tS2MPS15_LDO22 = 21,\n\tS2MPS15_LDO23 = 22,\n\tS2MPS15_LDO24 = 23,\n\tS2MPS15_LDO25 = 24,\n\tS2MPS15_LDO26 = 25,\n\tS2MPS15_LDO27 = 26,\n\tS2MPS15_BUCK1 = 27,\n\tS2MPS15_BUCK2 = 28,\n\tS2MPS15_BUCK3 = 29,\n\tS2MPS15_BUCK4 = 30,\n\tS2MPS15_BUCK5 = 31,\n\tS2MPS15_BUCK6 = 32,\n\tS2MPS15_BUCK7 = 33,\n\tS2MPS15_BUCK8 = 34,\n\tS2MPS15_BUCK9 = 35,\n\tS2MPS15_BUCK10 = 36,\n\tS2MPS15_BUCK11 = 37,\n\tS2MPS15_REGULATOR_MAX = 38,\n};\n\nenum s2mpu02_irq {\n\tS2MPU02_IRQ_PWRONF = 0,\n\tS2MPU02_IRQ_PWRONR = 1,\n\tS2MPU02_IRQ_JIGONBF = 2,\n\tS2MPU02_IRQ_JIGONBR = 3,\n\tS2MPU02_IRQ_ACOKBF = 4,\n\tS2MPU02_IRQ_ACOKBR = 5,\n\tS2MPU02_IRQ_PWRON1S = 6,\n\tS2MPU02_IRQ_MRB = 7,\n\tS2MPU02_IRQ_RTC60S = 8,\n\tS2MPU02_IRQ_RTCA1 = 9,\n\tS2MPU02_IRQ_RTCA0 = 10,\n\tS2MPU02_IRQ_SMPL = 11,\n\tS2MPU02_IRQ_RTC1S = 12,\n\tS2MPU02_IRQ_WTSR = 13,\n\tS2MPU02_IRQ_INT120C = 14,\n\tS2MPU02_IRQ_INT140C = 15,\n\tS2MPU02_IRQ_TSD = 16,\n\tS2MPU02_IRQ_NR = 17,\n};\n\nenum s2mpu05_irq {\n\tS2MPU05_IRQ_PWRONF = 0,\n\tS2MPU05_IRQ_PWRONR = 1,\n\tS2MPU05_IRQ_JIGONBF = 2,\n\tS2MPU05_IRQ_JIGONBR = 3,\n\tS2MPU05_IRQ_ACOKF = 4,\n\tS2MPU05_IRQ_ACOKR = 5,\n\tS2MPU05_IRQ_PWRON1S = 6,\n\tS2MPU05_IRQ_MRB = 7,\n\tS2MPU05_IRQ_RTC60S = 8,\n\tS2MPU05_IRQ_RTCA1 = 9,\n\tS2MPU05_IRQ_RTCA0 = 10,\n\tS2MPU05_IRQ_SMPL = 11,\n\tS2MPU05_IRQ_RTC1S = 12,\n\tS2MPU05_IRQ_WTSR = 13,\n\tS2MPU05_IRQ_INT120C = 14,\n\tS2MPU05_IRQ_INT140C = 15,\n\tS2MPU05_IRQ_TSD = 16,\n\tS2MPU05_IRQ_NR = 17,\n};\n\nenum s3c24xx_i2c_state {\n\tSTATE_IDLE___5 = 0,\n\tSTATE_START___2 = 1,\n\tSTATE_READ___3 = 2,\n\tSTATE_WRITE___3 = 3,\n\tSTATE_STOP___2 = 4,\n};\n\nenum s3c24xx_port_type {\n\tTYPE_S3C6400 = 0,\n\tTYPE_APPLE_S5L = 1,\n};\n\nenum s500_pinconf_pull {\n\tOWL_PINCONF_PULL_DOWN = 0,\n\tOWL_PINCONF_PULL_UP = 1,\n};\n\nenum s500_pinmux_functions {\n\tS500_MUX_NOR = 0,\n\tS500_MUX_ETH_RMII = 1,\n\tS500_MUX_ETH_SMII = 2,\n\tS500_MUX_SPI0 = 3,\n\tS500_MUX_SPI1 = 4,\n\tS500_MUX_SPI2 = 5,\n\tS500_MUX_SPI3 = 6,\n\tS500_MUX_SENS0 = 7,\n\tS500_MUX_SENS1 = 8,\n\tS500_MUX_UART0 = 9,\n\tS500_MUX_UART1 = 10,\n\tS500_MUX_UART2 = 11,\n\tS500_MUX_UART3 = 12,\n\tS500_MUX_UART4 = 13,\n\tS500_MUX_UART5 = 14,\n\tS500_MUX_UART6 = 15,\n\tS500_MUX_I2S0 = 16,\n\tS500_MUX_I2S1 = 17,\n\tS500_MUX_PCM1 = 18,\n\tS500_MUX_PCM0 = 19,\n\tS500_MUX_KS = 20,\n\tS500_MUX_JTAG = 21,\n\tS500_MUX_PWM0 = 22,\n\tS500_MUX_PWM1 = 23,\n\tS500_MUX_PWM2 = 24,\n\tS500_MUX_PWM3 = 25,\n\tS500_MUX_PWM4 = 26,\n\tS500_MUX_PWM5 = 27,\n\tS500_MUX_P0 = 28,\n\tS500_MUX_SD0 = 29,\n\tS500_MUX_SD1 = 30,\n\tS500_MUX_SD2 = 31,\n\tS500_MUX_I2C0 = 32,\n\tS500_MUX_I2C1 = 33,\n\tS500_MUX_I2C3 = 34,\n\tS500_MUX_DSI = 35,\n\tS500_MUX_LVDS = 36,\n\tS500_MUX_USB30 = 37,\n\tS500_MUX_CLKO_25M = 38,\n\tS500_MUX_MIPI_CSI = 39,\n\tS500_MUX_NAND = 40,\n\tS500_MUX_SPDIF = 41,\n\tS500_MUX_TS = 42,\n\tS500_MUX_LCD0 = 43,\n\tS500_MUX_RESERVED = 44,\n};\n\nenum s5m8767_dvs_buck_ramp_values {\n\tS5M8767_DVS_BUCK_RAMP_5 = 4,\n\tS5M8767_DVS_BUCK_RAMP_10 = 9,\n\tS5M8767_DVS_BUCK_RAMP_12_5 = 11,\n\tS5M8767_DVS_BUCK_RAMP_25 = 13,\n\tS5M8767_DVS_BUCK_RAMP_50 = 14,\n\tS5M8767_DVS_BUCK_RAMP_100 = 15,\n};\n\nenum s5m8767_irq {\n\tS5M8767_IRQ_PWRR = 0,\n\tS5M8767_IRQ_PWRF = 1,\n\tS5M8767_IRQ_PWR1S = 2,\n\tS5M8767_IRQ_JIGR = 3,\n\tS5M8767_IRQ_JIGF = 4,\n\tS5M8767_IRQ_LOWBAT2 = 5,\n\tS5M8767_IRQ_LOWBAT1 = 6,\n\tS5M8767_IRQ_MRB = 7,\n\tS5M8767_IRQ_DVSOK2 = 8,\n\tS5M8767_IRQ_DVSOK3 = 9,\n\tS5M8767_IRQ_DVSOK4 = 10,\n\tS5M8767_IRQ_RTC60S = 11,\n\tS5M8767_IRQ_RTCA1 = 12,\n\tS5M8767_IRQ_RTCA2 = 13,\n\tS5M8767_IRQ_SMPL = 14,\n\tS5M8767_IRQ_RTC1S = 15,\n\tS5M8767_IRQ_WTSR = 16,\n\tS5M8767_IRQ_NR = 17,\n};\n\nenum s5m8767_reg {\n\tS5M8767_REG_ID = 0,\n\tS5M8767_REG_INT1 = 1,\n\tS5M8767_REG_INT2 = 2,\n\tS5M8767_REG_INT3 = 3,\n\tS5M8767_REG_INT1M = 4,\n\tS5M8767_REG_INT2M = 5,\n\tS5M8767_REG_INT3M = 6,\n\tS5M8767_REG_STATUS1 = 7,\n\tS5M8767_REG_STATUS2 = 8,\n\tS5M8767_REG_STATUS3 = 9,\n\tS5M8767_REG_CTRL1 = 10,\n\tS5M8767_REG_CTRL2 = 11,\n\tS5M8767_REG_LOWBAT1 = 12,\n\tS5M8767_REG_LOWBAT2 = 13,\n\tS5M8767_REG_BUCHG = 14,\n\tS5M8767_REG_DVSRAMP = 15,\n\tS5M8767_REG_DVSTIMER2 = 16,\n\tS5M8767_REG_DVSTIMER3 = 17,\n\tS5M8767_REG_DVSTIMER4 = 18,\n\tS5M8767_REG_LDO1 = 19,\n\tS5M8767_REG_LDO2 = 20,\n\tS5M8767_REG_LDO3 = 21,\n\tS5M8767_REG_LDO4 = 22,\n\tS5M8767_REG_LDO5 = 23,\n\tS5M8767_REG_LDO6 = 24,\n\tS5M8767_REG_LDO7 = 25,\n\tS5M8767_REG_LDO8 = 26,\n\tS5M8767_REG_LDO9 = 27,\n\tS5M8767_REG_LDO10 = 28,\n\tS5M8767_REG_LDO11 = 29,\n\tS5M8767_REG_LDO12 = 30,\n\tS5M8767_REG_LDO13 = 31,\n\tS5M8767_REG_LDO14 = 32,\n\tS5M8767_REG_LDO15 = 33,\n\tS5M8767_REG_LDO16 = 34,\n\tS5M8767_REG_LDO17 = 35,\n\tS5M8767_REG_LDO18 = 36,\n\tS5M8767_REG_LDO19 = 37,\n\tS5M8767_REG_LDO20 = 38,\n\tS5M8767_REG_LDO21 = 39,\n\tS5M8767_REG_LDO22 = 40,\n\tS5M8767_REG_LDO23 = 41,\n\tS5M8767_REG_LDO24 = 42,\n\tS5M8767_REG_LDO25 = 43,\n\tS5M8767_REG_LDO26 = 44,\n\tS5M8767_REG_LDO27 = 45,\n\tS5M8767_REG_LDO28 = 46,\n\tS5M8767_REG_UVLO = 49,\n\tS5M8767_REG_BUCK1CTRL1 = 50,\n\tS5M8767_REG_BUCK1CTRL2 = 51,\n\tS5M8767_REG_BUCK2CTRL = 52,\n\tS5M8767_REG_BUCK2DVS1 = 53,\n\tS5M8767_REG_BUCK2DVS2 = 54,\n\tS5M8767_REG_BUCK2DVS3 = 55,\n\tS5M8767_REG_BUCK2DVS4 = 56,\n\tS5M8767_REG_BUCK2DVS5 = 57,\n\tS5M8767_REG_BUCK2DVS6 = 58,\n\tS5M8767_REG_BUCK2DVS7 = 59,\n\tS5M8767_REG_BUCK2DVS8 = 60,\n\tS5M8767_REG_BUCK3CTRL = 61,\n\tS5M8767_REG_BUCK3DVS1 = 62,\n\tS5M8767_REG_BUCK3DVS2 = 63,\n\tS5M8767_REG_BUCK3DVS3 = 64,\n\tS5M8767_REG_BUCK3DVS4 = 65,\n\tS5M8767_REG_BUCK3DVS5 = 66,\n\tS5M8767_REG_BUCK3DVS6 = 67,\n\tS5M8767_REG_BUCK3DVS7 = 68,\n\tS5M8767_REG_BUCK3DVS8 = 69,\n\tS5M8767_REG_BUCK4CTRL = 70,\n\tS5M8767_REG_BUCK4DVS1 = 71,\n\tS5M8767_REG_BUCK4DVS2 = 72,\n\tS5M8767_REG_BUCK4DVS3 = 73,\n\tS5M8767_REG_BUCK4DVS4 = 74,\n\tS5M8767_REG_BUCK4DVS5 = 75,\n\tS5M8767_REG_BUCK4DVS6 = 76,\n\tS5M8767_REG_BUCK4DVS7 = 77,\n\tS5M8767_REG_BUCK4DVS8 = 78,\n\tS5M8767_REG_BUCK5CTRL1 = 79,\n\tS5M8767_REG_BUCK5CTRL2 = 80,\n\tS5M8767_REG_BUCK5CTRL3 = 81,\n\tS5M8767_REG_BUCK5CTRL4 = 82,\n\tS5M8767_REG_BUCK5CTRL5 = 83,\n\tS5M8767_REG_BUCK6CTRL1 = 84,\n\tS5M8767_REG_BUCK6CTRL2 = 85,\n\tS5M8767_REG_BUCK7CTRL1 = 86,\n\tS5M8767_REG_BUCK7CTRL2 = 87,\n\tS5M8767_REG_BUCK8CTRL1 = 88,\n\tS5M8767_REG_BUCK8CTRL2 = 89,\n\tS5M8767_REG_BUCK9CTRL1 = 90,\n\tS5M8767_REG_BUCK9CTRL2 = 91,\n\tS5M8767_REG_LDO1CTRL = 92,\n\tS5M8767_REG_LDO2_1CTRL = 93,\n\tS5M8767_REG_LDO2_2CTRL = 94,\n\tS5M8767_REG_LDO2_3CTRL = 95,\n\tS5M8767_REG_LDO2_4CTRL = 96,\n\tS5M8767_REG_LDO3CTRL = 97,\n\tS5M8767_REG_LDO4CTRL = 98,\n\tS5M8767_REG_LDO5CTRL = 99,\n\tS5M8767_REG_LDO6CTRL = 100,\n\tS5M8767_REG_LDO7CTRL = 101,\n\tS5M8767_REG_LDO8CTRL = 102,\n\tS5M8767_REG_LDO9CTRL = 103,\n\tS5M8767_REG_LDO10CTRL = 104,\n\tS5M8767_REG_LDO11CTRL = 105,\n\tS5M8767_REG_LDO12CTRL = 106,\n\tS5M8767_REG_LDO13CTRL = 107,\n\tS5M8767_REG_LDO14CTRL = 108,\n\tS5M8767_REG_LDO15CTRL = 109,\n\tS5M8767_REG_LDO16CTRL = 110,\n\tS5M8767_REG_LDO17CTRL = 111,\n\tS5M8767_REG_LDO18CTRL = 112,\n\tS5M8767_REG_LDO19CTRL = 113,\n\tS5M8767_REG_LDO20CTRL = 114,\n\tS5M8767_REG_LDO21CTRL = 115,\n\tS5M8767_REG_LDO22CTRL = 116,\n\tS5M8767_REG_LDO23CTRL = 117,\n\tS5M8767_REG_LDO24CTRL = 118,\n\tS5M8767_REG_LDO25CTRL = 119,\n\tS5M8767_REG_LDO26CTRL = 120,\n\tS5M8767_REG_LDO27CTRL = 121,\n\tS5M8767_REG_LDO28CTRL = 122,\n};\n\nenum s5m8767_regulators {\n\tS5M8767_LDO1 = 0,\n\tS5M8767_LDO2 = 1,\n\tS5M8767_LDO3 = 2,\n\tS5M8767_LDO4 = 3,\n\tS5M8767_LDO5 = 4,\n\tS5M8767_LDO6 = 5,\n\tS5M8767_LDO7 = 6,\n\tS5M8767_LDO8 = 7,\n\tS5M8767_LDO9 = 8,\n\tS5M8767_LDO10 = 9,\n\tS5M8767_LDO11 = 10,\n\tS5M8767_LDO12 = 11,\n\tS5M8767_LDO13 = 12,\n\tS5M8767_LDO14 = 13,\n\tS5M8767_LDO15 = 14,\n\tS5M8767_LDO16 = 15,\n\tS5M8767_LDO17 = 16,\n\tS5M8767_LDO18 = 17,\n\tS5M8767_LDO19 = 18,\n\tS5M8767_LDO20 = 19,\n\tS5M8767_LDO21 = 20,\n\tS5M8767_LDO22 = 21,\n\tS5M8767_LDO23 = 22,\n\tS5M8767_LDO24 = 23,\n\tS5M8767_LDO25 = 24,\n\tS5M8767_LDO26 = 25,\n\tS5M8767_LDO27 = 26,\n\tS5M8767_LDO28 = 27,\n\tS5M8767_BUCK1 = 28,\n\tS5M8767_BUCK2 = 29,\n\tS5M8767_BUCK3 = 30,\n\tS5M8767_BUCK4 = 31,\n\tS5M8767_BUCK5 = 32,\n\tS5M8767_BUCK6 = 33,\n\tS5M8767_BUCK7 = 34,\n\tS5M8767_BUCK8 = 35,\n\tS5M8767_BUCK9 = 36,\n\tS5M8767_AP_EN32KHZ = 37,\n\tS5M8767_CP_EN32KHZ = 38,\n\tS5M8767_REG_MAX = 39,\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum sama7d65_pck_parent_hw_id {\n\tPCK_PARENT_HW_MCK0 = 0,\n\tPCK_PARENT_HW_MCK1 = 1,\n\tPCK_PARENT_HW_MCK2 = 2,\n\tPCK_PARENT_HW_MCK3 = 3,\n\tPCK_PARENT_HW_MCK4 = 4,\n\tPCK_PARENT_HW_MCK5 = 5,\n\tPCK_PARENT_HW_MCK6 = 6,\n\tPCK_PARENT_HW_MCK7 = 7,\n\tPCK_PARENT_HW_MCK8 = 8,\n\tPCK_PARENT_HW_MCK9 = 9,\n\tPCK_PARENT_HW_MAX = 10,\n};\n\nenum sama7d65_pll_parent {\n\tSAMA7D65_PLL_PARENT_MAINCK = 0,\n\tSAMA7D65_PLL_PARENT_MAIN_XTAL = 1,\n\tSAMA7D65_PLL_PARENT_FRACCK = 2,\n};\n\nenum sama7g5_pck_parent_hw_id {\n\tPCK_PARENT_HW_MCK0___2 = 0,\n\tPCK_PARENT_HW_MCK1___2 = 1,\n\tPCK_PARENT_HW_MCK2___2 = 2,\n\tPCK_PARENT_HW_MCK3___2 = 3,\n\tPCK_PARENT_HW_MCK4___2 = 4,\n\tPCK_PARENT_HW_MAX___2 = 5,\n};\n\nenum sama7g5_pll_parent {\n\tSAMA7G5_PLL_PARENT_MAINCK = 0,\n\tSAMA7G5_PLL_PARENT_MAIN_XTAL = 1,\n\tSAMA7G5_PLL_PARENT_FRACCK = 2,\n};\n\nenum samsung_pll_type {\n\tpll_2126 = 0,\n\tpll_3000 = 1,\n\tpll_35xx = 2,\n\tpll_36xx = 3,\n\tpll_2550 = 4,\n\tpll_2650 = 5,\n\tpll_4500 = 6,\n\tpll_4502 = 7,\n\tpll_4508 = 8,\n\tpll_4600 = 9,\n\tpll_4650 = 10,\n\tpll_4650c = 11,\n\tpll_6552 = 12,\n\tpll_6552_s3c2416 = 13,\n\tpll_6553 = 14,\n\tpll_2550x = 15,\n\tpll_2550xx = 16,\n\tpll_2650x = 17,\n\tpll_2650xx = 18,\n\tpll_1417x = 19,\n\tpll_1418x = 20,\n\tpll_1450x = 21,\n\tpll_1451x = 22,\n\tpll_1452x = 23,\n\tpll_1460x = 24,\n\tpll_0818x = 25,\n\tpll_0822x = 26,\n\tpll_0831x = 27,\n\tpll_142xx = 28,\n\tpll_0516x = 29,\n\tpll_0517x = 30,\n\tpll_0518x = 31,\n\tpll_531x = 32,\n\tpll_1051x = 33,\n\tpll_1052x = 34,\n\tpll_0717x = 35,\n\tpll_0718x = 36,\n\tpll_0732x = 37,\n\tpll_4311 = 38,\n\tpll_1017x = 39,\n\tpll_1031x = 40,\n};\n\nenum sata_phy_ctrl_regs {\n\tPHY_CTRL_1 = 0,\n\tPHY_CTRL_1_RESET = 1,\n};\n\nenum sata_phy_regs {\n\tBLOCK0_REG_BANK = 0,\n\tBLOCK0_XGXSSTATUS = 129,\n\tBLOCK0_XGXSSTATUS_PLL_LOCK = 4096,\n\tBLOCK0_SPARE = 141,\n\tBLOCK0_SPARE_OOB_CLK_SEL_MASK = 3,\n\tBLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 1,\n\tBLOCK1_REG_BANK = 16,\n\tBLOCK1_TEST_TX = 131,\n\tBLOCK1_TEST_TX_AMP_SHIFT = 12,\n\tPLL_REG_BANK_0 = 80,\n\tPLL_REG_BANK_0_PLLCONTROL_0 = 129,\n\tPLLCONTROL_0_FREQ_DET_RESTART = 8192,\n\tPLLCONTROL_0_FREQ_MONITOR = 4096,\n\tPLLCONTROL_0_SEQ_START = 32768,\n\tPLL_CAP_CHARGE_TIME = 131,\n\tPLL_VCO_CAL_THRESH = 132,\n\tPLL_CAP_CONTROL = 133,\n\tPLL_FREQ_DET_TIME = 134,\n\tPLL_ACTRL2 = 139,\n\tPLL_ACTRL2_SELDIV_MASK = 31,\n\tPLL_ACTRL2_SELDIV_SHIFT = 9,\n\tPLL_ACTRL6 = 134,\n\tPLL1_REG_BANK = 96,\n\tPLL1_ACTRL2 = 130,\n\tPLL1_ACTRL3 = 131,\n\tPLL1_ACTRL4 = 132,\n\tPLL1_ACTRL5 = 133,\n\tPLL1_ACTRL6 = 134,\n\tPLL1_ACTRL7 = 135,\n\tPLL1_ACTRL8 = 136,\n\tTX_REG_BANK = 112,\n\tTX_ACTRL0 = 128,\n\tTX_ACTRL0_TXPOL_FLIP = 64,\n\tTX_ACTRL5 = 133,\n\tTX_ACTRL5_SSC_EN = 2048,\n\tAEQRX_REG_BANK_0 = 208,\n\tAEQ_CONTROL1 = 129,\n\tAEQ_CONTROL1_ENABLE = 4,\n\tAEQ_CONTROL1_FREEZE = 8,\n\tAEQ_FRC_EQ = 131,\n\tAEQ_FRC_EQ_FORCE = 1,\n\tAEQ_FRC_EQ_FORCE_VAL = 2,\n\tAEQ_RFZ_FRC_VAL = 256,\n\tAEQRX_REG_BANK_1 = 224,\n\tAEQRX_SLCAL0_CTRL0 = 130,\n\tAEQRX_SLCAL1_CTRL0 = 134,\n\tOOB_REG_BANK = 336,\n\tOOB1_REG_BANK = 352,\n\tOOB_CTRL1 = 128,\n\tOOB_CTRL1_BURST_MAX_MASK = 15,\n\tOOB_CTRL1_BURST_MAX_SHIFT = 12,\n\tOOB_CTRL1_BURST_MIN_MASK = 15,\n\tOOB_CTRL1_BURST_MIN_SHIFT = 8,\n\tOOB_CTRL1_WAKE_IDLE_MAX_MASK = 15,\n\tOOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,\n\tOOB_CTRL1_WAKE_IDLE_MIN_MASK = 15,\n\tOOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,\n\tOOB_CTRL2 = 129,\n\tOOB_CTRL2_SEL_ENA_SHIFT = 15,\n\tOOB_CTRL2_SEL_ENA_RC_SHIFT = 14,\n\tOOB_CTRL2_RESET_IDLE_MAX_MASK = 63,\n\tOOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,\n\tOOB_CTRL2_BURST_CNT_MASK = 3,\n\tOOB_CTRL2_BURST_CNT_SHIFT = 6,\n\tOOB_CTRL2_RESET_IDLE_MIN_MASK = 63,\n\tOOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,\n\tTXPMD_REG_BANK = 416,\n\tTXPMD_CONTROL1 = 129,\n\tTXPMD_CONTROL1_TX_SSC_EN_FRC = 1,\n\tTXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = 2,\n\tTXPMD_TX_FREQ_CTRL_CONTROL1 = 130,\n\tTXPMD_TX_FREQ_CTRL_CONTROL2 = 131,\n\tTXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 1023,\n\tTXPMD_TX_FREQ_CTRL_CONTROL3 = 132,\n\tTXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 1023,\n\tRXPMD_REG_BANK = 448,\n\tRXPMD_RX_CDR_CONTROL1 = 129,\n\tRXPMD_RX_PPM_VAL_MASK = 511,\n\tRXPMD_RXPMD_EN_FRC = 4096,\n\tRXPMD_RXPMD_EN_FRC_VAL = 8192,\n\tRXPMD_RX_CDR_CDR_PROP_BW = 130,\n\tRXPMD_G_CDR_PROP_BW_MASK = 7,\n\tRXPMD_G1_CDR_PROP_BW_SHIFT = 0,\n\tRXPMD_G2_CDR_PROP_BW_SHIFT = 3,\n\tRXPMD_G3_CDR_PROB_BW_SHIFT = 6,\n\tRXPMD_RX_CDR_CDR_ACQ_INTEG_BW = 131,\n\tRXPMD_G_CDR_ACQ_INT_BW_MASK = 7,\n\tRXPMD_G1_CDR_ACQ_INT_BW_SHIFT = 0,\n\tRXPMD_G2_CDR_ACQ_INT_BW_SHIFT = 3,\n\tRXPMD_G3_CDR_ACQ_INT_BW_SHIFT = 6,\n\tRXPMD_RX_CDR_CDR_LOCK_INTEG_BW = 132,\n\tRXPMD_G_CDR_LOCK_INT_BW_MASK = 7,\n\tRXPMD_G1_CDR_LOCK_INT_BW_SHIFT = 0,\n\tRXPMD_G2_CDR_LOCK_INT_BW_SHIFT = 3,\n\tRXPMD_G3_CDR_LOCK_INT_BW_SHIFT = 6,\n\tRXPMD_RX_FREQ_MON_CONTROL1 = 135,\n\tRXPMD_MON_CORRECT_EN = 256,\n\tRXPMD_MON_MARGIN_VAL_MASK = 255,\n};\n\nenum sata_rcar_type {\n\tRCAR_GEN1_SATA = 0,\n\tRCAR_GEN2_SATA = 1,\n\tRCAR_GEN3_SATA = 2,\n\tRCAR_R8A7790_ES1_SATA = 3,\n};\n\nenum sbs_capacity_mode {\n\tCAPACITY_MODE_AMPS = 0,\n\tCAPACITY_MODE_WATTS = 32768,\n};\n\nenum scale_freq_source {\n\tSCALE_FREQ_SOURCE_CPUFREQ = 0,\n\tSCALE_FREQ_SOURCE_ARCH = 1,\n\tSCALE_FREQ_SOURCE_CPPC = 2,\n\tSCALE_FREQ_SOURCE_VIRT = 3,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum scmi_bad_msg {\n\tMSG_UNEXPECTED = -1,\n\tMSG_INVALID = -2,\n\tMSG_UNKNOWN = -3,\n\tMSG_NOMEM = -4,\n\tMSG_MBOX_SPURIOUS = -5,\n};\n\nenum scmi_base_protocol_cmd {\n\tBASE_DISCOVER_VENDOR = 3,\n\tBASE_DISCOVER_SUB_VENDOR = 4,\n\tBASE_DISCOVER_IMPLEMENT_VERSION = 5,\n\tBASE_DISCOVER_LIST_PROTOCOLS = 6,\n\tBASE_DISCOVER_AGENT = 7,\n\tBASE_NOTIFY_ERRORS = 8,\n\tBASE_SET_DEVICE_PERMISSIONS = 9,\n\tBASE_SET_PROTOCOL_PERMISSIONS = 10,\n\tBASE_RESET_AGENT_CONFIGURATION = 11,\n};\n\nenum scmi_clk_feats {\n\tSCMI_CLK_ATOMIC_SUPPORTED = 0,\n\tSCMI_CLK_STATE_CTRL_SUPPORTED = 1,\n\tSCMI_CLK_RATE_CTRL_SUPPORTED = 2,\n\tSCMI_CLK_PARENT_CTRL_SUPPORTED = 3,\n\tSCMI_CLK_DUTY_CYCLE_SUPPORTED = 4,\n\tSCMI_CLK_FEATS_COUNT = 5,\n};\n\nenum scmi_clock_oem_config {\n\tSCMI_CLOCK_CFG_DUTY_CYCLE = 1,\n\tSCMI_CLOCK_CFG_PHASE = 2,\n\tSCMI_CLOCK_CFG_OEM_START = 128,\n\tSCMI_CLOCK_CFG_OEM_END = 255,\n};\n\nenum scmi_clock_protocol_cmd {\n\tCLOCK_ATTRIBUTES = 3,\n\tCLOCK_DESCRIBE_RATES = 4,\n\tCLOCK_RATE_SET = 5,\n\tCLOCK_RATE_GET = 6,\n\tCLOCK_CONFIG_SET = 7,\n\tCLOCK_NAME_GET = 8,\n\tCLOCK_RATE_NOTIFY = 9,\n\tCLOCK_RATE_CHANGE_REQUESTED_NOTIFY = 10,\n\tCLOCK_CONFIG_GET = 11,\n\tCLOCK_POSSIBLE_PARENTS_GET = 12,\n\tCLOCK_PARENT_SET = 13,\n\tCLOCK_PARENT_GET = 14,\n\tCLOCK_GET_PERMISSIONS = 15,\n};\n\nenum scmi_common_cmd {\n\tPROTOCOL_VERSION = 0,\n\tPROTOCOL_ATTRIBUTES = 1,\n\tPROTOCOL_MESSAGE_ATTRIBUTES = 2,\n\tNEGOTIATE_PROTOCOL_VERSION = 16,\n};\n\nenum scmi_error_codes {\n\tSCMI_SUCCESS = 0,\n\tSCMI_ERR_SUPPORT = -1,\n\tSCMI_ERR_PARAMS = -2,\n\tSCMI_ERR_ACCESS = -3,\n\tSCMI_ERR_ENTRY = -4,\n\tSCMI_ERR_RANGE = -5,\n\tSCMI_ERR_BUSY = -6,\n\tSCMI_ERR_COMMS = -7,\n\tSCMI_ERR_GENERIC = -8,\n\tSCMI_ERR_HARDWARE = -9,\n\tSCMI_ERR_PROTOCOL = -10,\n};\n\nenum scmi_imx_bbm_protocol_cmd {\n\tIMX_BBM_GPR_SET = 3,\n\tIMX_BBM_GPR_GET = 4,\n\tIMX_BBM_RTC_ATTRIBUTES = 5,\n\tIMX_BBM_RTC_TIME_SET = 6,\n\tIMX_BBM_RTC_TIME_GET = 7,\n\tIMX_BBM_RTC_ALARM_SET = 8,\n\tIMX_BBM_BUTTON_GET = 9,\n\tIMX_BBM_RTC_NOTIFY = 10,\n\tIMX_BBM_BUTTON_NOTIFY = 11,\n};\n\nenum scmi_imx_cpu_protocol_cmd {\n\tSCMI_IMX_CPU_ATTRIBUTES = 3,\n\tSCMI_IMX_CPU_START = 4,\n\tSCMI_IMX_CPU_STOP = 5,\n\tSCMI_IMX_CPU_RESET_VECTOR_SET = 6,\n\tSCMI_IMX_CPU_INFO_GET = 12,\n};\n\nenum scmi_imx_lmm_op {\n\tSCMI_IMX_LMM_BOOT = 0,\n\tSCMI_IMX_LMM_POWER_ON = 1,\n\tSCMI_IMX_LMM_SHUTDOWN = 2,\n};\n\nenum scmi_imx_lmm_protocol_cmd {\n\tSCMI_IMX_LMM_ATTRIBUTES = 3,\n\tSCMI_IMX_LMM_BOOT___2 = 4,\n\tSCMI_IMX_LMM_RESET = 5,\n\tSCMI_IMX_LMM_SHUTDOWN___2 = 6,\n\tSCMI_IMX_LMM_WAKE = 7,\n\tSCMI_IMX_LMM_SUSPEND = 8,\n\tSCMI_IMX_LMM_NOTIFY = 9,\n\tSCMI_IMX_LMM_RESET_REASON = 10,\n\tSCMI_IMX_LMM_POWER_ON___2 = 11,\n\tSCMI_IMX_LMM_RESET_VECTOR_SET = 12,\n};\n\nenum scmi_imx_lmm_state {\n\tLMM_STATE_LM_OFF = 0,\n\tLMM_STATE_LM_ON = 1,\n\tLMM_STATE_LM_SUSPEND = 2,\n\tLMM_STATE_LM_POWERED = 3,\n};\n\nenum scmi_imx_misc_protocol_cmd {\n\tSCMI_IMX_MISC_CTRL_SET = 3,\n\tSCMI_IMX_MISC_CTRL_GET = 4,\n\tSCMI_IMX_MISC_DISCOVER_BUILD_INFO = 6,\n\tSCMI_IMX_MISC_CTRL_NOTIFY = 8,\n\tSCMI_IMX_MISC_CFG_INFO_GET = 12,\n\tSCMI_IMX_MISC_SYSLOG_GET = 13,\n\tSCMI_IMX_MISC_BOARD_INFO = 14,\n};\n\nenum scmi_notification_events {\n\tSCMI_EVENT_POWER_STATE_CHANGED = 0,\n\tSCMI_EVENT_CLOCK_RATE_CHANGED = 0,\n\tSCMI_EVENT_CLOCK_RATE_CHANGE_REQUESTED = 1,\n\tSCMI_EVENT_PERFORMANCE_LIMITS_CHANGED = 0,\n\tSCMI_EVENT_PERFORMANCE_LEVEL_CHANGED = 1,\n\tSCMI_EVENT_SENSOR_TRIP_POINT_EVENT = 0,\n\tSCMI_EVENT_SENSOR_UPDATE = 1,\n\tSCMI_EVENT_RESET_ISSUED = 0,\n\tSCMI_EVENT_BASE_ERROR_EVENT = 0,\n\tSCMI_EVENT_SYSTEM_POWER_STATE_NOTIFIER = 0,\n\tSCMI_EVENT_POWERCAP_CAP_CHANGED = 0,\n\tSCMI_EVENT_POWERCAP_MEASUREMENTS_CHANGED = 1,\n};\n\nenum scmi_nxp_notification_events {\n\tSCMI_EVENT_IMX_BBM_RTC = 0,\n\tSCMI_EVENT_IMX_BBM_BUTTON = 1,\n\tSCMI_EVENT_IMX_MISC_CONTROL = 0,\n};\n\nenum scmi_optee_pta_cmd {\n\tPTA_SCMI_CMD_CAPABILITIES = 0,\n\tPTA_SCMI_CMD_PROCESS_SMT_CHANNEL = 1,\n\tPTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE = 2,\n\tPTA_SCMI_CMD_GET_CHANNEL = 3,\n\tPTA_SCMI_CMD_PROCESS_MSG_CHANNEL = 4,\n};\n\nenum scmi_performance_protocol_cmd {\n\tPERF_DOMAIN_ATTRIBUTES = 3,\n\tPERF_DESCRIBE_LEVELS = 4,\n\tPERF_LIMITS_SET = 5,\n\tPERF_LIMITS_GET = 6,\n\tPERF_LEVEL_SET = 7,\n\tPERF_LEVEL_GET = 8,\n\tPERF_NOTIFY_LIMITS = 9,\n\tPERF_NOTIFY_LEVEL = 10,\n\tPERF_DESCRIBE_FASTCHANNEL = 11,\n\tPERF_DOMAIN_NAME_GET = 12,\n};\n\nenum scmi_pinctrl_conf_type {\n\tSCMI_PIN_DEFAULT = 0,\n\tSCMI_PIN_BIAS_BUS_HOLD = 1,\n\tSCMI_PIN_BIAS_DISABLE = 2,\n\tSCMI_PIN_BIAS_HIGH_IMPEDANCE = 3,\n\tSCMI_PIN_BIAS_PULL_UP = 4,\n\tSCMI_PIN_BIAS_PULL_DEFAULT = 5,\n\tSCMI_PIN_BIAS_PULL_DOWN = 6,\n\tSCMI_PIN_DRIVE_OPEN_DRAIN = 7,\n\tSCMI_PIN_DRIVE_OPEN_SOURCE = 8,\n\tSCMI_PIN_DRIVE_PUSH_PULL = 9,\n\tSCMI_PIN_DRIVE_STRENGTH = 10,\n\tSCMI_PIN_INPUT_DEBOUNCE = 11,\n\tSCMI_PIN_INPUT_MODE = 12,\n\tSCMI_PIN_PULL_MODE = 13,\n\tSCMI_PIN_INPUT_VALUE = 14,\n\tSCMI_PIN_INPUT_SCHMITT = 15,\n\tSCMI_PIN_LOW_POWER_MODE = 16,\n\tSCMI_PIN_OUTPUT_MODE = 17,\n\tSCMI_PIN_OUTPUT_VALUE = 18,\n\tSCMI_PIN_POWER_SOURCE = 19,\n\tSCMI_PIN_SLEW_RATE = 20,\n\tSCMI_PIN_OEM_START = 192,\n\tSCMI_PIN_OEM_END = 255,\n};\n\nenum scmi_pinctrl_protocol_cmd {\n\tPINCTRL_ATTRIBUTES = 3,\n\tPINCTRL_LIST_ASSOCIATIONS = 4,\n\tPINCTRL_SETTINGS_GET = 5,\n\tPINCTRL_SETTINGS_CONFIGURE = 6,\n\tPINCTRL_REQUEST = 7,\n\tPINCTRL_RELEASE = 8,\n\tPINCTRL_NAME_GET = 9,\n\tPINCTRL_SET_PERMISSIONS = 10,\n};\n\nenum scmi_pinctrl_selector_type {\n\tPIN_TYPE = 0,\n\tGROUP_TYPE = 1,\n\tFUNCTION_TYPE = 2,\n};\n\nenum scmi_power_protocol_cmd {\n\tPOWER_DOMAIN_ATTRIBUTES = 3,\n\tPOWER_STATE_SET = 4,\n\tPOWER_STATE_GET = 5,\n\tPOWER_STATE_NOTIFY = 6,\n\tPOWER_DOMAIN_NAME_GET = 8,\n};\n\nenum scmi_power_scale {\n\tSCMI_POWER_BOGOWATTS = 0,\n\tSCMI_POWER_MILLIWATTS = 1,\n\tSCMI_POWER_MICROWATTS = 2,\n};\n\nenum scmi_powercap_protocol_cmd {\n\tPOWERCAP_DOMAIN_ATTRIBUTES = 3,\n\tPOWERCAP_CAP_GET = 4,\n\tPOWERCAP_CAP_SET = 5,\n\tPOWERCAP_PAI_GET = 6,\n\tPOWERCAP_PAI_SET = 7,\n\tPOWERCAP_DOMAIN_NAME_GET = 8,\n\tPOWERCAP_MEASUREMENTS_GET = 9,\n\tPOWERCAP_CAP_NOTIFY = 10,\n\tPOWERCAP_MEASUREMENTS_NOTIFY = 11,\n\tPOWERCAP_DESCRIBE_FASTCHANNEL = 12,\n};\n\nenum scmi_reset_protocol_cmd {\n\tRESET_DOMAIN_ATTRIBUTES = 3,\n\tRESET = 4,\n\tRESET_NOTIFY = 5,\n\tRESET_DOMAIN_NAME_GET = 6,\n};\n\nenum scmi_sensor_class {\n\tNONE = 0,\n\tUNSPEC = 1,\n\tTEMPERATURE_C = 2,\n\tTEMPERATURE_F = 3,\n\tTEMPERATURE_K = 4,\n\tVOLTAGE___2 = 5,\n\tCURRENT___2 = 6,\n\tPOWER = 7,\n\tENERGY = 8,\n\tCHARGE = 9,\n\tVOLTAMPERE = 10,\n\tNITS = 11,\n\tLUMENS = 12,\n\tLUX = 13,\n\tCANDELAS = 14,\n\tKPA = 15,\n\tPSI = 16,\n\tNEWTON = 17,\n\tCFM = 18,\n\tRPM = 19,\n\tHERTZ = 20,\n\tSECS = 21,\n\tMINS = 22,\n\tHOURS = 23,\n\tDAYS = 24,\n\tWEEKS = 25,\n\tMILS = 26,\n\tINCHES = 27,\n\tFEET = 28,\n\tCUBIC_INCHES = 29,\n\tCUBIC_FEET = 30,\n\tMETERS = 31,\n\tCUBIC_CM = 32,\n\tCUBIC_METERS = 33,\n\tLITERS = 34,\n\tFLUID_OUNCES = 35,\n\tRADIANS = 36,\n\tSTERADIANS = 37,\n\tREVOLUTIONS = 38,\n\tCYCLES = 39,\n\tGRAVITIES = 40,\n\tOUNCES = 41,\n\tPOUNDS = 42,\n\tFOOT_POUNDS = 43,\n\tOUNCE_INCHES = 44,\n\tGAUSS = 45,\n\tGILBERTS = 46,\n\tHENRIES = 47,\n\tFARADS = 48,\n\tOHMS = 49,\n\tSIEMENS = 50,\n\tMOLES = 51,\n\tBECQUERELS = 52,\n\tPPM = 53,\n\tDECIBELS = 54,\n\tDBA = 55,\n\tDBC = 56,\n\tGRAYS = 57,\n\tSIEVERTS = 58,\n\tCOLOR_TEMP_K = 59,\n\tBITS = 60,\n\tBYTES = 61,\n\tWORDS = 62,\n\tDWORDS = 63,\n\tQWORDS = 64,\n\tPERCENTAGE = 65,\n\tPASCALS = 66,\n\tCOUNTS = 67,\n\tGRAMS = 68,\n\tNEWTON_METERS = 69,\n\tHITS = 70,\n\tMISSES = 71,\n\tRETRIES = 72,\n\tOVERRUNS = 73,\n\tUNDERRUNS = 74,\n\tCOLLISIONS = 75,\n\tPACKETS = 76,\n\tMESSAGES = 77,\n\tCHARS = 78,\n\tERRORS = 79,\n\tCORRECTED_ERRS = 80,\n\tUNCORRECTABLE_ERRS = 81,\n\tSQ_MILS = 82,\n\tSQ_INCHES = 83,\n\tSQ_FEET = 84,\n\tSQ_CM = 85,\n\tSQ_METERS = 86,\n\tRADIANS_SEC = 87,\n\tBPM = 88,\n\tMETERS_SEC_SQUARED = 89,\n\tMETERS_SEC = 90,\n\tCUBIC_METERS_SEC = 91,\n\tMM_MERCURY = 92,\n\tRADIANS_SEC_SQUARED = 93,\n\tOEM_UNIT = 255,\n};\n\nenum scmi_sensor_protocol_cmd {\n\tSENSOR_DESCRIPTION_GET = 3,\n\tSENSOR_TRIP_POINT_NOTIFY = 4,\n\tSENSOR_TRIP_POINT_CONFIG = 5,\n\tSENSOR_READING_GET = 6,\n\tSENSOR_AXIS_DESCRIPTION_GET = 7,\n\tSENSOR_LIST_UPDATE_INTERVALS = 8,\n\tSENSOR_CONFIG_GET = 9,\n\tSENSOR_CONFIG_SET = 10,\n\tSENSOR_CONTINUOUS_UPDATE_NOTIFY = 11,\n\tSENSOR_NAME_GET = 12,\n\tSENSOR_AXIS_NAME_GET = 13,\n};\n\nenum scmi_std_protocol {\n\tSCMI_PROTOCOL_BASE = 16,\n\tSCMI_PROTOCOL_POWER = 17,\n\tSCMI_PROTOCOL_SYSTEM = 18,\n\tSCMI_PROTOCOL_PERF = 19,\n\tSCMI_PROTOCOL_CLOCK = 20,\n\tSCMI_PROTOCOL_SENSOR = 21,\n\tSCMI_PROTOCOL_RESET = 22,\n\tSCMI_PROTOCOL_VOLTAGE = 23,\n\tSCMI_PROTOCOL_POWERCAP = 24,\n\tSCMI_PROTOCOL_PINCTRL = 25,\n};\n\nenum scmi_system_events {\n\tSCMI_SYSTEM_SHUTDOWN = 0,\n\tSCMI_SYSTEM_COLDRESET = 1,\n\tSCMI_SYSTEM_WARMRESET = 2,\n\tSCMI_SYSTEM_POWERUP = 3,\n\tSCMI_SYSTEM_SUSPEND = 4,\n\tSCMI_SYSTEM_MAX = 5,\n};\n\nenum scmi_system_protocol_cmd {\n\tSYSTEM_POWER_STATE_NOTIFY = 5,\n};\n\nenum scmi_voltage_level_mode {\n\tSCMI_VOLTAGE_LEVEL_SET_AUTO = 0,\n\tSCMI_VOLTAGE_LEVEL_SET_SYNC = 1,\n};\n\nenum scmi_voltage_protocol_cmd {\n\tVOLTAGE_DOMAIN_ATTRIBUTES = 3,\n\tVOLTAGE_DESCRIBE_LEVELS = 4,\n\tVOLTAGE_CONFIG_SET = 5,\n\tVOLTAGE_CONFIG_GET = 6,\n\tVOLTAGE_LEVEL_SET = 7,\n\tVOLTAGE_LEVEL_GET = 8,\n\tVOLTAGE_DOMAIN_NAME_GET = 9,\n};\n\nenum scpsys_bus_prot_block {\n\tBUS_PROT_BLOCK_INFRA = 0,\n\tBUS_PROT_BLOCK_INFRA_NAO = 1,\n\tBUS_PROT_BLOCK_SMI = 2,\n\tBUS_PROT_BLOCK_SPM = 3,\n\tBUS_PROT_BLOCK_COUNT = 4,\n};\n\nenum scpsys_bus_prot_flags {\n\tBUS_PROT_REG_UPDATE = 2,\n\tBUS_PROT_IGNORE_CLR_ACK = 4,\n\tBUS_PROT_INVERTED = 8,\n};\n\nenum scpsys_mtcmos_type {\n\tSCPSYS_MTCMOS_TYPE_DIRECT_CTL = 0,\n\tSCPSYS_MTCMOS_TYPE_HW_VOTER = 1,\n\tSCPSYS_MTCMOS_TYPE_MAX = 2,\n};\n\nenum scpsys_rtff_type {\n\tSCPSYS_RTFF_NONE = 0,\n\tSCPSYS_RTFF_TYPE_GENERIC = 1,\n\tSCPSYS_RTFF_TYPE_PCIE_PHY = 2,\n\tSCPSYS_RTFF_TYPE_STOR_UFS = 3,\n\tSCPSYS_RTFF_TYPE_MAX = 4,\n};\n\nenum scrub_type {\n\tSCRUB_UNKNOWN = 0,\n\tSCRUB_NONE = 1,\n\tSCRUB_SW_PROG = 2,\n\tSCRUB_SW_SRC = 3,\n\tSCRUB_SW_PROG_SRC = 4,\n\tSCRUB_SW_TUNABLE = 5,\n\tSCRUB_HW_PROG = 6,\n\tSCRUB_HW_SRC = 7,\n\tSCRUB_HW_PROG_SRC = 8,\n\tSCRUB_HW_TUNABLE = 9,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 1000,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 3000,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_HAS_CGROUP_WEIGHT = 65536ULL,\n\tSCX_OPS_ALL_FLAGS = 65663ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1,\n\t__SCX_REENQ_FILTER_MASK = 65535,\n\t__SCX_REENQ_USER_MASK = 1,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum sd_uhs2_operation {\n\tUHS2_PHY_INIT = 0,\n\tUHS2_SET_CONFIG = 1,\n\tUHS2_ENABLE_INT = 2,\n\tUHS2_DISABLE_INT = 3,\n\tUHS2_ENABLE_CLK = 4,\n\tUHS2_DISABLE_CLK = 5,\n\tUHS2_CHECK_DORMANT = 6,\n\tUHS2_SET_IOS = 7,\n};\n\nenum sdhci_cookie {\n\tCOOKIE_UNMAPPED___3 = 0,\n\tCOOKIE_PRE_MAPPED___3 = 1,\n\tCOOKIE_MAPPED___3 = 2,\n};\n\nenum sdhci_reset_reason {\n\tSDHCI_RESET_FOR_INIT = 0,\n\tSDHCI_RESET_FOR_REQUEST_ERROR = 1,\n\tSDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY = 2,\n\tSDHCI_RESET_FOR_TUNING_ABORT = 3,\n\tSDHCI_RESET_FOR_CARD_REMOVED = 4,\n\tSDHCI_RESET_FOR_CQE_RECOVERY = 5,\n};\n\nenum sdma_peripheral_type {\n\tIMX_DMATYPE_SSI = 0,\n\tIMX_DMATYPE_SSI_SP = 1,\n\tIMX_DMATYPE_MMC = 2,\n\tIMX_DMATYPE_SDHC = 3,\n\tIMX_DMATYPE_UART = 4,\n\tIMX_DMATYPE_UART_SP = 5,\n\tIMX_DMATYPE_FIRI = 6,\n\tIMX_DMATYPE_CSPI = 7,\n\tIMX_DMATYPE_CSPI_SP = 8,\n\tIMX_DMATYPE_SIM = 9,\n\tIMX_DMATYPE_ATA = 10,\n\tIMX_DMATYPE_CCM = 11,\n\tIMX_DMATYPE_EXT = 12,\n\tIMX_DMATYPE_MSHC = 13,\n\tIMX_DMATYPE_MSHC_SP = 14,\n\tIMX_DMATYPE_DSP = 15,\n\tIMX_DMATYPE_MEMORY = 16,\n\tIMX_DMATYPE_FIFO_MEMORY = 17,\n\tIMX_DMATYPE_SPDIF = 18,\n\tIMX_DMATYPE_IPU_MEMORY = 19,\n\tIMX_DMATYPE_ASRC = 20,\n\tIMX_DMATYPE_ESAI = 21,\n\tIMX_DMATYPE_SSI_DUAL = 22,\n\tIMX_DMATYPE_ASRC_SP = 23,\n\tIMX_DMATYPE_SAI = 24,\n\tIMX_DMATYPE_MULTI_SAI = 25,\n\tIMX_DMATYPE_HDMI = 26,\n\tIMX_DMATYPE_I2C = 27,\n};\n\nenum sec_device_type {\n\tS5M8767X = 0,\n\tS2DOS05 = 1,\n\tS2MPA01 = 2,\n\tS2MPG10 = 3,\n\tS2MPG11 = 4,\n\tS2MPS11X = 5,\n\tS2MPS13X = 6,\n\tS2MPS14X = 7,\n\tS2MPS15X = 8,\n\tS2MPU02 = 9,\n\tS2MPU05 = 10,\n};\n\nenum security_clk {\n\tSECF_NONE = 0,\n\tSECF_LPTIM2 = 1,\n\tSECF_LPTIM3 = 2,\n\tSECF_VREF = 3,\n\tSECF_DCMIPP = 4,\n\tSECF_USBPHY = 5,\n\tSECF_TZC = 6,\n\tSECF_ETZPC = 7,\n\tSECF_IWDG1 = 8,\n\tSECF_BSEC = 9,\n\tSECF_STGENC = 10,\n\tSECF_STGENRO = 11,\n\tSECF_USART1 = 12,\n\tSECF_USART2 = 13,\n\tSECF_SPI4 = 14,\n\tSECF_SPI5 = 15,\n\tSECF_I2C3 = 16,\n\tSECF_I2C4 = 17,\n\tSECF_I2C5 = 18,\n\tSECF_TIM12 = 19,\n\tSECF_TIM13 = 20,\n\tSECF_TIM14 = 21,\n\tSECF_TIM15 = 22,\n\tSECF_TIM16 = 23,\n\tSECF_TIM17 = 24,\n\tSECF_DMA3 = 25,\n\tSECF_DMAMUX2 = 26,\n\tSECF_ADC1 = 27,\n\tSECF_ADC2 = 28,\n\tSECF_USBO = 29,\n\tSECF_TSC = 30,\n\tSECF_PKA = 31,\n\tSECF_SAES = 32,\n\tSECF_CRYP1 = 33,\n\tSECF_HASH1 = 34,\n\tSECF_RNG1 = 35,\n\tSECF_BKPSRAM = 36,\n\tSECF_MCE = 37,\n\tSECF_FMC = 38,\n\tSECF_QSPI = 39,\n\tSECF_SDMMC1 = 40,\n\tSECF_SDMMC2 = 41,\n\tSECF_ETH1CK = 42,\n\tSECF_ETH1TX = 43,\n\tSECF_ETH1RX = 44,\n\tSECF_ETH1MAC = 45,\n\tSECF_ETH1STP = 46,\n\tSECF_ETH2CK = 47,\n\tSECF_ETH2TX = 48,\n\tSECF_ETH2RX = 49,\n\tSECF_ETH2MAC = 50,\n\tSECF_ETH2STP = 51,\n\tSECF_MCO1 = 52,\n\tSECF_MCO2 = 53,\n};\n\nenum serdev_parity {\n\tSERDEV_PARITY_NONE = 0,\n\tSERDEV_PARITY_EVEN = 1,\n\tSERDEV_PARITY_ODD = 2,\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nenum set_event_iter_type {\n\tSET_EVENT_FILE = 0,\n\tSET_EVENT_MOD = 1,\n};\n\nenum sgmii_speed {\n\tSGMII_SPEED_10 = 0,\n\tSGMII_SPEED_100 = 1,\n\tSGMII_SPEED_1000 = 2,\n\tSGMII_SPEED_2500 = 2,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum sh_cmt_model {\n\tSH_CMT_16BIT = 0,\n\tSH_CMT_32BIT = 1,\n\tSH_CMT_48BIT = 2,\n\tSH_CMT0_RCAR_GEN2 = 3,\n\tSH_CMT1_RCAR_GEN2 = 4,\n};\n\nenum sh_mmcif_state {\n\tSTATE_IDLE___6 = 0,\n\tSTATE_REQUEST = 1,\n\tSTATE_IOS = 2,\n\tSTATE_TIMEOUT = 3,\n};\n\nenum sh_mmcif_wait_for {\n\tMMCIF_WAIT_FOR_REQUEST = 0,\n\tMMCIF_WAIT_FOR_CMD = 1,\n\tMMCIF_WAIT_FOR_MREAD = 2,\n\tMMCIF_WAIT_FOR_MWRITE = 3,\n\tMMCIF_WAIT_FOR_READ = 4,\n\tMMCIF_WAIT_FOR_WRITE = 5,\n\tMMCIF_WAIT_FOR_READ_END = 6,\n\tMMCIF_WAIT_FOR_WRITE_END = 7,\n\tMMCIF_WAIT_FOR_STOP = 8,\n};\n\nenum sh_mobile_i2c_op {\n\tOP_START = 0,\n\tOP_TX_FIRST = 1,\n\tOP_TX = 2,\n\tOP_TX_STOP = 3,\n\tOP_TX_TO_RX = 4,\n\tOP_RX = 5,\n\tOP_RX_STOP = 6,\n\tOP_RX_STOP_DATA = 7,\n};\n\nenum sh_tmu_model {\n\tSH_TMU = 0,\n\tSH_TMU_SH3 = 1,\n};\n\nenum shmem_param {\n\tOpt_gid___8 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___5 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes = 5,\n\tOpt_size = 6,\n\tOpt_uid___7 = 7,\n\tOpt_inode32 = 8,\n\tOpt_inode64 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota___2 = 11,\n\tOpt_usrquota___2 = 12,\n\tOpt_grpquota___2 = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_ext_id {\n\tSKB_EXT_SEC_PATH = 0,\n\tSKB_EXT_CAN = 1,\n\tSKB_EXT_NUM = 2,\n};\n\nenum skb_state {\n\tillegal = 0,\n\ttx_start = 1,\n\ttx_done = 2,\n\trx_start = 3,\n\trx_done = 4,\n\trx_cleanup = 5,\n\tunlink_start = 6,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN___2 = 0,\n\tPARTIAL = 1,\n\tUP___2 = 2,\n\tFULL = 3,\n};\n\nenum slewrate_bit {\n\tSLEWRATE_BIT_ENA = 0,\n\tSLEWRATE_BIT_DIS = 1,\n};\n\nenum smbios_attr_enum {\n\tSMBIOS_ATTR_NONE = 0,\n\tSMBIOS_ATTR_LABEL_SHOW = 1,\n\tSMBIOS_ATTR_INSTANCE_SHOW = 2,\n};\n\nenum smd_channel_state {\n\tSMD_CHANNEL_CLOSED = 0,\n\tSMD_CHANNEL_OPENING = 1,\n\tSMD_CHANNEL_OPENED = 2,\n\tSMD_CHANNEL_FLUSHING = 3,\n\tSMD_CHANNEL_CLOSING = 4,\n\tSMD_CHANNEL_RESET = 5,\n\tSMD_CHANNEL_RESET_OPENING = 6,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum snd_compr_direction {\n\tSND_COMPRESS_PLAYBACK = 0,\n\tSND_COMPRESS_CAPTURE = 1,\n\tSND_COMPRESS_ACCEL = 2,\n};\n\nenum snd_soc_bias_level {\n\tSND_SOC_BIAS_OFF = 0,\n\tSND_SOC_BIAS_STANDBY = 1,\n\tSND_SOC_BIAS_PREPARE = 2,\n\tSND_SOC_BIAS_ON = 3,\n};\n\nenum snd_soc_dapm_type {\n\tsnd_soc_dapm_input = 0,\n\tsnd_soc_dapm_output = 1,\n\tsnd_soc_dapm_mux = 2,\n\tsnd_soc_dapm_demux = 3,\n\tsnd_soc_dapm_mixer = 4,\n\tsnd_soc_dapm_mixer_named_ctl = 5,\n\tsnd_soc_dapm_pga = 6,\n\tsnd_soc_dapm_out_drv = 7,\n\tsnd_soc_dapm_adc = 8,\n\tsnd_soc_dapm_dac = 9,\n\tsnd_soc_dapm_micbias = 10,\n\tsnd_soc_dapm_mic = 11,\n\tsnd_soc_dapm_hp = 12,\n\tsnd_soc_dapm_spk = 13,\n\tsnd_soc_dapm_line = 14,\n\tsnd_soc_dapm_switch = 15,\n\tsnd_soc_dapm_vmid = 16,\n\tsnd_soc_dapm_pre = 17,\n\tsnd_soc_dapm_post = 18,\n\tsnd_soc_dapm_supply = 19,\n\tsnd_soc_dapm_pinctrl = 20,\n\tsnd_soc_dapm_regulator_supply = 21,\n\tsnd_soc_dapm_clock_supply = 22,\n\tsnd_soc_dapm_aif_in = 23,\n\tsnd_soc_dapm_aif_out = 24,\n\tsnd_soc_dapm_siggen = 25,\n\tsnd_soc_dapm_sink = 26,\n\tsnd_soc_dapm_dai_in = 27,\n\tsnd_soc_dapm_dai_out = 28,\n\tsnd_soc_dapm_dai_link = 29,\n\tsnd_soc_dapm_kcontrol = 30,\n\tsnd_soc_dapm_buffer = 31,\n\tsnd_soc_dapm_scheduler = 32,\n\tsnd_soc_dapm_effect = 33,\n\tsnd_soc_dapm_src = 34,\n\tsnd_soc_dapm_asrc = 35,\n\tsnd_soc_dapm_encoder = 36,\n\tsnd_soc_dapm_decoder = 37,\n\tSND_SOC_DAPM_TYPE_COUNT = 38,\n};\n\nenum snd_soc_dobj_type {\n\tSND_SOC_DOBJ_NONE = 0,\n\tSND_SOC_DOBJ_MIXER = 1,\n\tSND_SOC_DOBJ_BYTES = 2,\n\tSND_SOC_DOBJ_ENUM = 3,\n\tSND_SOC_DOBJ_GRAPH = 4,\n\tSND_SOC_DOBJ_WIDGET = 5,\n\tSND_SOC_DOBJ_DAI_LINK = 6,\n\tSND_SOC_DOBJ_PCM = 7,\n\tSND_SOC_DOBJ_CODEC_LINK = 8,\n\tSND_SOC_DOBJ_BACKEND_LINK = 9,\n};\n\nenum snd_soc_dpcm_state {\n\tSND_SOC_DPCM_STATE_NEW = 0,\n\tSND_SOC_DPCM_STATE_OPEN = 1,\n\tSND_SOC_DPCM_STATE_HW_PARAMS = 2,\n\tSND_SOC_DPCM_STATE_PREPARE = 3,\n\tSND_SOC_DPCM_STATE_START = 4,\n\tSND_SOC_DPCM_STATE_STOP = 5,\n\tSND_SOC_DPCM_STATE_PAUSED = 6,\n\tSND_SOC_DPCM_STATE_SUSPEND = 7,\n\tSND_SOC_DPCM_STATE_HW_FREE = 8,\n\tSND_SOC_DPCM_STATE_CLOSE = 9,\n};\n\nenum snd_soc_dpcm_trigger {\n\tSND_SOC_DPCM_TRIGGER_PRE = 0,\n\tSND_SOC_DPCM_TRIGGER_POST = 1,\n};\n\nenum snd_soc_dpcm_update {\n\tSND_SOC_DPCM_UPDATE_NO = 0,\n\tSND_SOC_DPCM_UPDATE_BE = 1,\n\tSND_SOC_DPCM_UPDATE_FE = 2,\n};\n\nenum snd_soc_pcm_subclass {\n\tSND_SOC_PCM_CLASS_PCM = 0,\n\tSND_SOC_PCM_CLASS_BE = 1,\n};\n\nenum snd_soc_trigger_order {\n\tSND_SOC_TRIGGER_ORDER_DEFAULT = 0,\n\tSND_SOC_TRIGGER_ORDER_LDC = 1,\n\tSND_SOC_TRIGGER_ORDER_MAX = 2,\n};\n\nenum snoop_when {\n\tSUBMIT = 0,\n\tCOMPLETE = 1,\n};\n\nenum soc_type {\n\tSOC_ARCH_EXYNOS3250 = 1,\n\tSOC_ARCH_EXYNOS4210 = 2,\n\tSOC_ARCH_EXYNOS4412 = 3,\n\tSOC_ARCH_EXYNOS5250 = 4,\n\tSOC_ARCH_EXYNOS5260 = 5,\n\tSOC_ARCH_EXYNOS5420 = 6,\n\tSOC_ARCH_EXYNOS5420_TRIMINFO = 7,\n\tSOC_ARCH_EXYNOS5433 = 8,\n\tSOC_ARCH_EXYNOS7 = 9,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum spear1310_miphy_mode {\n\tSATA = 0,\n\tPCIE = 1,\n};\n\nenum spear1340_miphy_mode {\n\tSATA___2 = 0,\n\tPCIE___2 = 1,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum spi_mem_data_dir {\n\tSPI_MEM_NO_DATA = 0,\n\tSPI_MEM_DATA_IN = 1,\n\tSPI_MEM_DATA_OUT = 2,\n};\n\nenum spi_nor_cmd_ext {\n\tSPI_NOR_EXT_NONE = 0,\n\tSPI_NOR_EXT_REPEAT = 1,\n\tSPI_NOR_EXT_INVERT = 2,\n\tSPI_NOR_EXT_HEX = 3,\n};\n\nenum spi_nor_option_flags {\n\tSNOR_F_HAS_SR_TB = 1,\n\tSNOR_F_NO_OP_CHIP_ERASE = 2,\n\tSNOR_F_BROKEN_RESET = 4,\n\tSNOR_F_4B_OPCODES = 8,\n\tSNOR_F_HAS_4BAIT = 16,\n\tSNOR_F_HAS_LOCK = 32,\n\tSNOR_F_HAS_16BIT_SR = 64,\n\tSNOR_F_NO_READ_CR = 128,\n\tSNOR_F_HAS_SR_TB_BIT6 = 256,\n\tSNOR_F_HAS_4BIT_BP = 512,\n\tSNOR_F_HAS_SR_BP3_BIT6 = 1024,\n\tSNOR_F_IO_MODE_EN_VOLATILE = 2048,\n\tSNOR_F_SOFT_RESET = 4096,\n\tSNOR_F_SWP_IS_VOLATILE = 8192,\n\tSNOR_F_RWW = 16384,\n\tSNOR_F_ECC = 32768,\n\tSNOR_F_NO_WP = 65536,\n\tSNOR_F_SWAP16 = 131072,\n};\n\nenum spi_nor_pp_command_index {\n\tSNOR_CMD_PP = 0,\n\tSNOR_CMD_PP_1_1_4 = 1,\n\tSNOR_CMD_PP_1_4_4 = 2,\n\tSNOR_CMD_PP_4_4_4 = 3,\n\tSNOR_CMD_PP_1_1_8 = 4,\n\tSNOR_CMD_PP_1_8_8 = 5,\n\tSNOR_CMD_PP_8_8_8 = 6,\n\tSNOR_CMD_PP_8_8_8_DTR = 7,\n\tSNOR_CMD_PP_MAX = 8,\n};\n\nenum spi_nor_protocol {\n\tSNOR_PROTO_1_1_1 = 65793,\n\tSNOR_PROTO_1_1_2 = 65794,\n\tSNOR_PROTO_1_1_4 = 65796,\n\tSNOR_PROTO_1_1_8 = 65800,\n\tSNOR_PROTO_1_2_2 = 66050,\n\tSNOR_PROTO_1_4_4 = 66564,\n\tSNOR_PROTO_1_8_8 = 67592,\n\tSNOR_PROTO_2_2_2 = 131586,\n\tSNOR_PROTO_4_4_4 = 263172,\n\tSNOR_PROTO_8_8_8 = 526344,\n\tSNOR_PROTO_1_1_1_DTR = 16843009,\n\tSNOR_PROTO_1_2_2_DTR = 16843266,\n\tSNOR_PROTO_1_4_4_DTR = 16843780,\n\tSNOR_PROTO_1_8_8_DTR = 16844808,\n\tSNOR_PROTO_8_8_8_DTR = 17303560,\n};\n\nenum spi_nor_read_command_index {\n\tSNOR_CMD_READ = 0,\n\tSNOR_CMD_READ_FAST = 1,\n\tSNOR_CMD_READ_1_1_1_DTR = 2,\n\tSNOR_CMD_READ_1_1_2 = 3,\n\tSNOR_CMD_READ_1_2_2 = 4,\n\tSNOR_CMD_READ_2_2_2 = 5,\n\tSNOR_CMD_READ_1_2_2_DTR = 6,\n\tSNOR_CMD_READ_1_1_4 = 7,\n\tSNOR_CMD_READ_1_4_4 = 8,\n\tSNOR_CMD_READ_4_4_4 = 9,\n\tSNOR_CMD_READ_1_4_4_DTR = 10,\n\tSNOR_CMD_READ_1_1_8 = 11,\n\tSNOR_CMD_READ_1_8_8 = 12,\n\tSNOR_CMD_READ_8_8_8 = 13,\n\tSNOR_CMD_READ_1_8_8_DTR = 14,\n\tSNOR_CMD_READ_8_8_8_DTR = 15,\n\tSNOR_CMD_READ_MAX = 16,\n};\n\nenum spm_reg {\n\tSPM_REG_CFG = 0,\n\tSPM_REG_SPM_CTL = 1,\n\tSPM_REG_DLY = 2,\n\tSPM_REG_PMIC_DLY = 3,\n\tSPM_REG_PMIC_DATA_0 = 4,\n\tSPM_REG_PMIC_DATA_1 = 5,\n\tSPM_REG_VCTL = 6,\n\tSPM_REG_SEQ_ENTRY = 7,\n\tSPM_REG_STS0 = 8,\n\tSPM_REG_STS1 = 9,\n\tSPM_REG_PMIC_STS = 10,\n\tSPM_REG_AVS_CTL = 11,\n\tSPM_REG_AVS_LIMIT = 12,\n\tSPM_REG_RST = 13,\n\tSPM_REG_NR = 14,\n};\n\nenum spmi_boost_byp_registers {\n\tSPMI_BOOST_BYP_REG_CURRENT_LIMIT = 75,\n};\n\nenum spmi_boost_registers {\n\tSPMI_BOOST_REG_CURRENT_LIMIT = 74,\n};\n\nenum spmi_common_control_register_index {\n\tSPMI_COMMON_IDX_VOLTAGE_RANGE = 0,\n\tSPMI_COMMON_IDX_VOLTAGE_SET = 1,\n\tSPMI_COMMON_IDX_MODE = 5,\n\tSPMI_COMMON_IDX_ENABLE = 6,\n};\n\nenum spmi_common_regulator_registers {\n\tSPMI_COMMON_REG_DIG_MAJOR_REV = 1,\n\tSPMI_COMMON_REG_TYPE = 4,\n\tSPMI_COMMON_REG_SUBTYPE = 5,\n\tSPMI_COMMON_REG_VOLTAGE_RANGE = 64,\n\tSPMI_COMMON_REG_VOLTAGE_SET = 65,\n\tSPMI_COMMON_REG_MODE = 69,\n\tSPMI_COMMON_REG_ENABLE = 70,\n\tSPMI_COMMON_REG_PULL_DOWN = 72,\n\tSPMI_COMMON_REG_SOFT_START = 76,\n\tSPMI_COMMON_REG_STEP_CTRL = 97,\n};\n\nenum spmi_ftsmps426_regulator_registers {\n\tSPMI_FTSMPS426_REG_VOLTAGE_LSB = 64,\n\tSPMI_FTSMPS426_REG_VOLTAGE_MSB = 65,\n\tSPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 104,\n\tSPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 105,\n};\n\nenum spmi_hfsmps_regulator_registers {\n\tSPMI_HFSMPS_REG_STEP_CTRL = 60,\n\tSPMI_HFSMPS_REG_PULL_DOWN = 160,\n};\n\nenum spmi_regulator_logical_type {\n\tSPMI_REGULATOR_LOGICAL_TYPE_SMPS = 0,\n\tSPMI_REGULATOR_LOGICAL_TYPE_LDO = 1,\n\tSPMI_REGULATOR_LOGICAL_TYPE_VS = 2,\n\tSPMI_REGULATOR_LOGICAL_TYPE_BOOST = 3,\n\tSPMI_REGULATOR_LOGICAL_TYPE_FTSMPS = 4,\n\tSPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP = 5,\n\tSPMI_REGULATOR_LOGICAL_TYPE_LN_LDO = 6,\n\tSPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS = 7,\n\tSPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS = 8,\n\tSPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO = 9,\n\tSPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426 = 10,\n\tSPMI_REGULATOR_LOGICAL_TYPE_HFS430 = 11,\n\tSPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3 = 12,\n\tSPMI_REGULATOR_LOGICAL_TYPE_LDO_510 = 13,\n\tSPMI_REGULATOR_LOGICAL_TYPE_HFSMPS = 14,\n};\n\nenum spmi_regulator_subtype {\n\tSPMI_REGULATOR_SUBTYPE_GP_CTL = 8,\n\tSPMI_REGULATOR_SUBTYPE_RF_CTL = 9,\n\tSPMI_REGULATOR_SUBTYPE_N50 = 1,\n\tSPMI_REGULATOR_SUBTYPE_N150 = 2,\n\tSPMI_REGULATOR_SUBTYPE_N300 = 3,\n\tSPMI_REGULATOR_SUBTYPE_N600 = 4,\n\tSPMI_REGULATOR_SUBTYPE_N1200 = 5,\n\tSPMI_REGULATOR_SUBTYPE_N600_ST = 6,\n\tSPMI_REGULATOR_SUBTYPE_N1200_ST = 7,\n\tSPMI_REGULATOR_SUBTYPE_N900_ST = 20,\n\tSPMI_REGULATOR_SUBTYPE_N300_ST = 21,\n\tSPMI_REGULATOR_SUBTYPE_P50 = 8,\n\tSPMI_REGULATOR_SUBTYPE_P150 = 9,\n\tSPMI_REGULATOR_SUBTYPE_P300 = 10,\n\tSPMI_REGULATOR_SUBTYPE_P600 = 11,\n\tSPMI_REGULATOR_SUBTYPE_P1200 = 12,\n\tSPMI_REGULATOR_SUBTYPE_LN = 16,\n\tSPMI_REGULATOR_SUBTYPE_LV_P50 = 40,\n\tSPMI_REGULATOR_SUBTYPE_LV_P150 = 41,\n\tSPMI_REGULATOR_SUBTYPE_LV_P300 = 42,\n\tSPMI_REGULATOR_SUBTYPE_LV_P600 = 43,\n\tSPMI_REGULATOR_SUBTYPE_LV_P1200 = 44,\n\tSPMI_REGULATOR_SUBTYPE_LV_P450 = 45,\n\tSPMI_REGULATOR_SUBTYPE_HT_N300_ST = 48,\n\tSPMI_REGULATOR_SUBTYPE_HT_N600_ST = 49,\n\tSPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 50,\n\tSPMI_REGULATOR_SUBTYPE_HT_LVP150 = 59,\n\tSPMI_REGULATOR_SUBTYPE_HT_LVP300 = 60,\n\tSPMI_REGULATOR_SUBTYPE_L660_N300_ST = 66,\n\tSPMI_REGULATOR_SUBTYPE_L660_N600_ST = 67,\n\tSPMI_REGULATOR_SUBTYPE_L660_P50 = 70,\n\tSPMI_REGULATOR_SUBTYPE_L660_P150 = 71,\n\tSPMI_REGULATOR_SUBTYPE_L660_P600 = 73,\n\tSPMI_REGULATOR_SUBTYPE_L660_LVP150 = 77,\n\tSPMI_REGULATOR_SUBTYPE_L660_LVP600 = 79,\n\tSPMI_REGULATOR_SUBTYPE_LV100 = 1,\n\tSPMI_REGULATOR_SUBTYPE_LV300 = 2,\n\tSPMI_REGULATOR_SUBTYPE_MV300 = 8,\n\tSPMI_REGULATOR_SUBTYPE_MV500 = 9,\n\tSPMI_REGULATOR_SUBTYPE_HDMI = 16,\n\tSPMI_REGULATOR_SUBTYPE_OTG = 17,\n\tSPMI_REGULATOR_SUBTYPE_5V_BOOST = 1,\n\tSPMI_REGULATOR_SUBTYPE_FTS_CTL = 8,\n\tSPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 9,\n\tSPMI_REGULATOR_SUBTYPE_FTS426_CTL = 10,\n\tSPMI_REGULATOR_SUBTYPE_BB_2A = 1,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 13,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 14,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 15,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 16,\n\tSPMI_REGULATOR_SUBTYPE_HFS430 = 10,\n\tSPMI_REGULATOR_SUBTYPE_HT_P150 = 53,\n\tSPMI_REGULATOR_SUBTYPE_HT_P600 = 61,\n\tSPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 10,\n\tSPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 11,\n\tSPMI_REGULATOR_SUBTYPE_LV_P150_510 = 113,\n\tSPMI_REGULATOR_SUBTYPE_LV_P300_510 = 114,\n\tSPMI_REGULATOR_SUBTYPE_LV_P600_510 = 115,\n\tSPMI_REGULATOR_SUBTYPE_N300_510 = 106,\n\tSPMI_REGULATOR_SUBTYPE_N600_510 = 107,\n\tSPMI_REGULATOR_SUBTYPE_N1200_510 = 108,\n\tSPMI_REGULATOR_SUBTYPE_MV_P50_510 = 122,\n\tSPMI_REGULATOR_SUBTYPE_MV_P150_510 = 123,\n\tSPMI_REGULATOR_SUBTYPE_MV_P600_510 = 125,\n};\n\nenum spmi_regulator_type {\n\tSPMI_REGULATOR_TYPE_BUCK = 3,\n\tSPMI_REGULATOR_TYPE_LDO = 4,\n\tSPMI_REGULATOR_TYPE_VS = 5,\n\tSPMI_REGULATOR_TYPE_BOOST = 27,\n\tSPMI_REGULATOR_TYPE_FTS = 28,\n\tSPMI_REGULATOR_TYPE_BOOST_BYP = 31,\n\tSPMI_REGULATOR_TYPE_ULT_LDO = 33,\n\tSPMI_REGULATOR_TYPE_ULT_BUCK = 34,\n};\n\nenum spmi_saw3_registers {\n\tSAW3_SECURE = 0,\n\tSAW3_ID = 4,\n\tSAW3_SPM_STS = 12,\n\tSAW3_AVS_STS = 16,\n\tSAW3_PMIC_STS = 20,\n\tSAW3_RST = 24,\n\tSAW3_VCTL = 28,\n\tSAW3_AVS_CTL = 32,\n\tSAW3_AVS_LIMIT = 36,\n\tSAW3_AVS_DLY = 40,\n\tSAW3_AVS_HYSTERESIS = 44,\n\tSAW3_SPM_STS2 = 56,\n\tSAW3_SPM_PMIC_DATA_3 = 76,\n\tSAW3_VERSION = 4048,\n};\n\nenum spmi_vs_registers {\n\tSPMI_VS_REG_OCP = 74,\n\tSPMI_VS_REG_SOFT_START = 76,\n};\n\nenum spmi_vs_soft_start_str {\n\tSPMI_VS_SOFT_START_STR_0P05_UA = 0,\n\tSPMI_VS_SOFT_START_STR_0P25_UA = 1,\n\tSPMI_VS_SOFT_START_STR_0P55_UA = 2,\n\tSPMI_VS_SOFT_START_STR_0P75_UA = 3,\n\tSPMI_VS_SOFT_START_STR_HW_DEFAULT = 4,\n};\n\nenum squashfs_param {\n\tOpt_errors___3 = 0,\n\tOpt_threads = 1,\n};\n\nenum squelch_level {\n\tSQLCH_NOMINAL = 0,\n\tSQLCH_PLUS_7_MV = 1,\n\tSQLCH_MINUS_5_MV = 2,\n\tSQLCH_PLUS_14_MV = 3,\n\tSQLCH_MAX = 4,\n};\n\nenum sr_instance {\n\tOMAP_SR_MPU = 0,\n\tOMAP_SR_CORE = 1,\n\tOMAP_SR_IVA = 2,\n\tOMAP_SR_NR = 3,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum ssbi_controller_type {\n\tMSM_SBI_CTRL_SSBI = 0,\n\tMSM_SBI_CTRL_SSBI2 = 1,\n\tMSM_SBI_CTRL_PMIC_ARBITER = 2,\n};\n\nenum ssp_clkdelay {\n\tSSP_FEEDBACK_CLK_DELAY_NONE = 0,\n\tSSP_FEEDBACK_CLK_DELAY_1T = 1,\n\tSSP_FEEDBACK_CLK_DELAY_2T = 2,\n\tSSP_FEEDBACK_CLK_DELAY_3T = 3,\n\tSSP_FEEDBACK_CLK_DELAY_4T = 4,\n\tSSP_FEEDBACK_CLK_DELAY_5T = 5,\n\tSSP_FEEDBACK_CLK_DELAY_6T = 6,\n\tSSP_FEEDBACK_CLK_DELAY_7T = 7,\n};\n\nenum ssp_data_size {\n\tSSP_DATA_BITS_4 = 3,\n\tSSP_DATA_BITS_5 = 4,\n\tSSP_DATA_BITS_6 = 5,\n\tSSP_DATA_BITS_7 = 6,\n\tSSP_DATA_BITS_8 = 7,\n\tSSP_DATA_BITS_9 = 8,\n\tSSP_DATA_BITS_10 = 9,\n\tSSP_DATA_BITS_11 = 10,\n\tSSP_DATA_BITS_12 = 11,\n\tSSP_DATA_BITS_13 = 12,\n\tSSP_DATA_BITS_14 = 13,\n\tSSP_DATA_BITS_15 = 14,\n\tSSP_DATA_BITS_16 = 15,\n\tSSP_DATA_BITS_17 = 16,\n\tSSP_DATA_BITS_18 = 17,\n\tSSP_DATA_BITS_19 = 18,\n\tSSP_DATA_BITS_20 = 19,\n\tSSP_DATA_BITS_21 = 20,\n\tSSP_DATA_BITS_22 = 21,\n\tSSP_DATA_BITS_23 = 22,\n\tSSP_DATA_BITS_24 = 23,\n\tSSP_DATA_BITS_25 = 24,\n\tSSP_DATA_BITS_26 = 25,\n\tSSP_DATA_BITS_27 = 26,\n\tSSP_DATA_BITS_28 = 27,\n\tSSP_DATA_BITS_29 = 28,\n\tSSP_DATA_BITS_30 = 29,\n\tSSP_DATA_BITS_31 = 30,\n\tSSP_DATA_BITS_32 = 31,\n};\n\nenum ssp_duplex {\n\tSSP_MICROWIRE_CHANNEL_FULL_DUPLEX = 0,\n\tSSP_MICROWIRE_CHANNEL_HALF_DUPLEX = 1,\n};\n\nenum ssp_hierarchy {\n\tSSP_MASTER = 0,\n\tSSP_SLAVE = 1,\n};\n\nenum ssp_interface {\n\tSSP_INTERFACE_MOTOROLA_SPI = 0,\n\tSSP_INTERFACE_TI_SYNC_SERIAL = 1,\n\tSSP_INTERFACE_NATIONAL_MICROWIRE = 2,\n\tSSP_INTERFACE_UNIDIRECTIONAL = 3,\n};\n\nenum ssp_loopback {\n\tLOOPBACK_DISABLED = 0,\n\tLOOPBACK_ENABLED = 1,\n};\n\nenum ssp_microwire_ctrl_len {\n\tSSP_BITS_4 = 3,\n\tSSP_BITS_5 = 4,\n\tSSP_BITS_6 = 5,\n\tSSP_BITS_7 = 6,\n\tSSP_BITS_8 = 7,\n\tSSP_BITS_9 = 8,\n\tSSP_BITS_10 = 9,\n\tSSP_BITS_11 = 10,\n\tSSP_BITS_12 = 11,\n\tSSP_BITS_13 = 12,\n\tSSP_BITS_14 = 13,\n\tSSP_BITS_15 = 14,\n\tSSP_BITS_16 = 15,\n\tSSP_BITS_17 = 16,\n\tSSP_BITS_18 = 17,\n\tSSP_BITS_19 = 18,\n\tSSP_BITS_20 = 19,\n\tSSP_BITS_21 = 20,\n\tSSP_BITS_22 = 21,\n\tSSP_BITS_23 = 22,\n\tSSP_BITS_24 = 23,\n\tSSP_BITS_25 = 24,\n\tSSP_BITS_26 = 25,\n\tSSP_BITS_27 = 26,\n\tSSP_BITS_28 = 27,\n\tSSP_BITS_29 = 28,\n\tSSP_BITS_30 = 29,\n\tSSP_BITS_31 = 30,\n\tSSP_BITS_32 = 31,\n};\n\nenum ssp_microwire_wait_state {\n\tSSP_MWIRE_WAIT_ZERO = 0,\n\tSSP_MWIRE_WAIT_ONE = 1,\n};\n\nenum ssp_mode {\n\tINTERRUPT_TRANSFER = 0,\n\tPOLLING_TRANSFER = 1,\n\tDMA_TRANSFER = 2,\n};\n\nenum ssp_reading {\n\tREADING_NULL = 0,\n\tREADING_U8 = 1,\n\tREADING_U16 = 2,\n\tREADING_U32 = 3,\n};\n\nenum ssp_rx_endian {\n\tSSP_RX_MSB = 0,\n\tSSP_RX_LSB = 1,\n};\n\nenum ssp_rx_level_trig {\n\tSSP_RX_1_OR_MORE_ELEM = 0,\n\tSSP_RX_4_OR_MORE_ELEM = 1,\n\tSSP_RX_8_OR_MORE_ELEM = 2,\n\tSSP_RX_16_OR_MORE_ELEM = 3,\n\tSSP_RX_32_OR_MORE_ELEM = 4,\n};\n\nenum ssp_spi_clk_phase {\n\tSSP_CLK_FIRST_EDGE = 0,\n\tSSP_CLK_SECOND_EDGE = 1,\n};\n\nenum ssp_spi_clk_pol {\n\tSSP_CLK_POL_IDLE_LOW = 0,\n\tSSP_CLK_POL_IDLE_HIGH = 1,\n};\n\nenum ssp_tx_endian {\n\tSSP_TX_MSB = 0,\n\tSSP_TX_LSB = 1,\n};\n\nenum ssp_tx_level_trig {\n\tSSP_TX_1_OR_MORE_EMPTY_LOC = 0,\n\tSSP_TX_4_OR_MORE_EMPTY_LOC = 1,\n\tSSP_TX_8_OR_MORE_EMPTY_LOC = 2,\n\tSSP_TX_16_OR_MORE_EMPTY_LOC = 3,\n\tSSP_TX_32_OR_MORE_EMPTY_LOC = 4,\n};\n\nenum ssp_writing {\n\tWRITING_NULL = 0,\n\tWRITING_U8 = 1,\n\tWRITING_U16 = 2,\n\tWRITING_U32 = 3,\n};\n\nenum st_i2c_mode {\n\tI2C_MODE_STANDARD = 0,\n\tI2C_MODE_FAST = 1,\n\tI2C_MODE_END = 2,\n};\n\nenum st_retime_style {\n\tst_retime_style_none = 0,\n\tst_retime_style_packed = 1,\n\tst_retime_style_dedicated = 2,\n};\n\nenum st_thermal_power_state {\n\tPOWER_OFF = 0,\n\tPOWER_ON = 1,\n};\n\nenum st_thermal_regfield_ids {\n\tINT_THRESH_HI = 0,\n\tTEMP_PWR = 0,\n\tDCORRECT = 1,\n\tOVERFLOW = 2,\n\tDATA = 3,\n\tINT_ENABLE = 4,\n\tMAX_REGFIELDS___3 = 5,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tOFF___3 = 0,\n\tON = 1,\n};\n\nenum state___2 {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum state_protect_how4 {\n\tSP4_NONE = 0,\n\tSP4_MACH_CRED = 1,\n\tSP4_SSV = 2,\n};\n\nenum stedma40_flow_ctrl {\n\tSTEDMA40_NO_FLOW_CTRL = 0,\n\tSTEDMA40_FLOW_CTRL = 1,\n};\n\nenum stedma40_mode {\n\tSTEDMA40_MODE_LOGICAL = 0,\n\tSTEDMA40_MODE_PHYSICAL = 1,\n\tSTEDMA40_MODE_OPERATION = 2,\n};\n\nenum stedma40_mode_opt {\n\tSTEDMA40_PCHAN_BASIC_MODE = 0,\n\tSTEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,\n\tSTEDMA40_PCHAN_MODULO_MODE = 1,\n\tSTEDMA40_PCHAN_DOUBLE_DST_MODE = 2,\n\tSTEDMA40_LCHAN_SRC_PHY_DST_LOG = 3,\n\tSTEDMA40_LCHAN_SRC_LOG_DST_PHY = 4,\n};\n\nenum sti_cpt_edge {\n\tCPT_EDGE_DISABLED = 0,\n\tCPT_EDGE_RISING = 1,\n\tCPT_EDGE_FALLING = 2,\n\tCPT_EDGE_BOTH = 3,\n};\n\nenum stm32_dma_burst_size {\n\tSTM32_DMA_BURST_SINGLE = 0,\n\tSTM32_DMA_BURST_INCR4 = 1,\n\tSTM32_DMA_BURST_INCR8 = 2,\n\tSTM32_DMA_BURST_INCR16 = 3,\n};\n\nenum stm32_dma_width {\n\tSTM32_DMA_BYTE = 0,\n\tSTM32_DMA_HALF_WORD = 1,\n\tSTM32_DMA_WORD = 2,\n};\n\nenum stm32_fmc2_ebi_bank {\n\tFMC2_EBI1 = 0,\n\tFMC2_EBI2 = 1,\n\tFMC2_EBI3 = 2,\n\tFMC2_EBI4 = 3,\n\tFMC2_NAND = 4,\n};\n\nenum stm32_fmc2_ebi_buswidth {\n\tFMC2_BUSWIDTH_8 = 8,\n\tFMC2_BUSWIDTH_16 = 16,\n};\n\nenum stm32_fmc2_ebi_cpsize {\n\tFMC2_CPSIZE_0 = 0,\n\tFMC2_CPSIZE_128 = 128,\n\tFMC2_CPSIZE_256 = 256,\n\tFMC2_CPSIZE_512 = 512,\n\tFMC2_CPSIZE_1024 = 1024,\n};\n\nenum stm32_fmc2_ebi_cscount {\n\tFMC2_CSCOUNT_0 = 0,\n\tFMC2_CSCOUNT_1 = 1,\n\tFMC2_CSCOUNT_64 = 64,\n\tFMC2_CSCOUNT_256 = 256,\n};\n\nenum stm32_fmc2_ebi_register_type {\n\tFMC2_REG_BCR = 1,\n\tFMC2_REG_BTR = 2,\n\tFMC2_REG_BWTR = 3,\n\tFMC2_REG_PCSCNTR = 4,\n\tFMC2_REG_CFGR = 5,\n};\n\nenum stm32_fmc2_ebi_transaction_type {\n\tFMC2_ASYNC_MODE_1_SRAM = 0,\n\tFMC2_ASYNC_MODE_1_PSRAM = 1,\n\tFMC2_ASYNC_MODE_A_SRAM = 2,\n\tFMC2_ASYNC_MODE_A_PSRAM = 3,\n\tFMC2_ASYNC_MODE_2_NOR = 4,\n\tFMC2_ASYNC_MODE_B_NOR = 5,\n\tFMC2_ASYNC_MODE_C_NOR = 6,\n\tFMC2_ASYNC_MODE_D_NOR = 7,\n\tFMC2_SYNC_READ_SYNC_WRITE_PSRAM = 8,\n\tFMC2_SYNC_READ_ASYNC_WRITE_PSRAM = 9,\n\tFMC2_SYNC_READ_SYNC_WRITE_NOR = 10,\n\tFMC2_SYNC_READ_ASYNC_WRITE_NOR = 11,\n};\n\nenum stm32_fmc2_ecc {\n\tFMC2_ECC_HAM = 1,\n\tFMC2_ECC_BCH4 = 4,\n\tFMC2_ECC_BCH8 = 8,\n};\n\nenum stm32_fmc2_irq_state {\n\tFMC2_IRQ_UNKNOWN = 0,\n\tFMC2_IRQ_BCH = 1,\n\tFMC2_IRQ_SEQ = 2,\n};\n\nenum stm32_mdma_inc_mode {\n\tSTM32_MDMA_FIXED = 0,\n\tSTM32_MDMA_INC = 2,\n\tSTM32_MDMA_DEC = 3,\n};\n\nenum stm32_mdma_trigger_mode {\n\tSTM32_MDMA_BUFFER = 0,\n\tSTM32_MDMA_BLOCK = 1,\n\tSTM32_MDMA_BLOCK_REP = 2,\n\tSTM32_MDMA_LINKED_LIST = 3,\n};\n\nenum stm32_rtc_pin_name {\n\tNONE___2 = 0,\n\tOUT1 = 1,\n\tOUT2 = 2,\n\tOUT2_RMP = 3,\n};\n\nenum stmfx_functions {\n\tSTMFX_FUNC_GPIO = 1,\n\tSTMFX_FUNC_ALTGPIO_LOW = 2,\n\tSTMFX_FUNC_ALTGPIO_HIGH = 4,\n\tSTMFX_FUNC_TS = 8,\n\tSTMFX_FUNC_IDD = 16,\n};\n\nenum stmfx_irqs {\n\tSTMFX_REG_IRQ_SRC_EN_GPIO = 0,\n\tSTMFX_REG_IRQ_SRC_EN_IDD = 1,\n\tSTMFX_REG_IRQ_SRC_EN_ERROR = 2,\n\tSTMFX_REG_IRQ_SRC_EN_TS_DET = 3,\n\tSTMFX_REG_IRQ_SRC_EN_TS_NE = 4,\n\tSTMFX_REG_IRQ_SRC_EN_TS_TH = 5,\n\tSTMFX_REG_IRQ_SRC_EN_TS_FULL = 6,\n\tSTMFX_REG_IRQ_SRC_EN_TS_OVF = 7,\n\tSTMFX_REG_IRQ_SRC_MAX = 8,\n};\n\nenum stmmac_dl_param_id {\n\tSTMMAC_DEVLINK_PARAM_ID_BASE = 21,\n\tSTMMAC_DEVLINK_PARAM_ID_TS_COARSE = 22,\n};\n\nenum stmmac_lpi_mode {\n\tSTMMAC_LPI_DISABLE = 0,\n\tSTMMAC_LPI_FORCED = 1,\n\tSTMMAC_LPI_TIMER = 2,\n};\n\nenum stmmac_rfs_type {\n\tSTMMAC_RFS_T_VLAN = 0,\n\tSTMMAC_RFS_T_LLDP = 1,\n\tSTMMAC_RFS_T_1588 = 2,\n\tSTMMAC_RFS_T_MAX = 3,\n};\n\nenum stmmac_state {\n\tSTMMAC_DOWN = 0,\n\tSTMMAC_RESET_REQUESTED = 1,\n\tSTMMAC_RESETING = 2,\n\tSTMMAC_SERVICE_SCHED = 3,\n};\n\nenum stmmac_txbuf_type {\n\tSTMMAC_TXBUF_T_SKB = 0,\n\tSTMMAC_TXBUF_T_XDP_TX = 1,\n\tSTMMAC_TXBUF_T_XDP_NDO = 2,\n\tSTMMAC_TXBUF_T_XSK_TX = 3,\n};\n\nenum stmpe_block {\n\tSTMPE_BLOCK_GPIO = 1,\n\tSTMPE_BLOCK_KEYPAD = 2,\n\tSTMPE_BLOCK_TOUCHSCREEN = 4,\n\tSTMPE_BLOCK_ADC = 8,\n\tSTMPE_BLOCK_PWM = 16,\n\tSTMPE_BLOCK_ROTATOR = 32,\n};\n\nenum stmpe_partnum {\n\tSTMPE610 = 0,\n\tSTMPE801 = 1,\n\tSTMPE811 = 2,\n\tSTMPE1600 = 3,\n\tSTMPE1601 = 4,\n\tSTMPE1801 = 5,\n\tSTMPE2401 = 6,\n\tSTMPE2403 = 7,\n\tSTMPE_NBR_PARTS = 8,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum stripetype4 {\n\tSTRIPE_SPARSE = 1,\n\tSTRIPE_DENSE = 2,\n};\n\nenum subpixel_order {\n\tSubPixelUnknown = 0,\n\tSubPixelHorizontalRGB = 1,\n\tSubPixelHorizontalBGR = 2,\n\tSubPixelVerticalRGB = 3,\n\tSubPixelVerticalBGR = 4,\n\tSubPixelNone = 5,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\nenum sunxi_desc_bias_voltage {\n\tBIAS_VOLTAGE_NONE = 0,\n\tBIAS_VOLTAGE_GRP_CONFIG = 1,\n\tBIAS_VOLTAGE_PIO_POW_MODE_SEL = 2,\n\tBIAS_VOLTAGE_PIO_POW_MODE_CTL = 3,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum suspend_stat_step {\n\tSUSPEND_WORKING = 0,\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nenum svc_auth_status {\n\tSVC_GARBAGE = 1,\n\tSVC_VALID = 2,\n\tSVC_NEGATIVE = 3,\n\tSVC_OK = 4,\n\tSVC_DROP = 5,\n\tSVC_CLOSE = 6,\n\tSVC_DENIED = 7,\n\tSVC_PENDING = 8,\n\tSVC_COMPLETE = 9,\n};\n\nenum sw_activity {\n\tOFF___4 = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum switch_power_state {\n\tDRM_SWITCH_POWER_ON = 0,\n\tDRM_SWITCH_POWER_OFF = 1,\n\tDRM_SWITCH_POWER_CHANGING = 2,\n\tDRM_SWITCH_POWER_DYNAMIC_OFF = 3,\n};\n\nenum switchdev_attr_id {\n\tSWITCHDEV_ATTR_ID_UNDEFINED = 0,\n\tSWITCHDEV_ATTR_ID_PORT_STP_STATE = 1,\n\tSWITCHDEV_ATTR_ID_PORT_MST_STATE = 2,\n\tSWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS = 3,\n\tSWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS = 4,\n\tSWITCHDEV_ATTR_ID_PORT_MROUTER = 5,\n\tSWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME = 6,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING = 7,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_PROTOCOL = 8,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED = 9,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MROUTER = 10,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MST = 11,\n\tSWITCHDEV_ATTR_ID_MRP_PORT_ROLE = 12,\n\tSWITCHDEV_ATTR_ID_VLAN_MSTI = 13,\n};\n\nenum switchdev_notifier_type {\n\tSWITCHDEV_FDB_ADD_TO_BRIDGE = 1,\n\tSWITCHDEV_FDB_DEL_TO_BRIDGE = 2,\n\tSWITCHDEV_FDB_ADD_TO_DEVICE = 3,\n\tSWITCHDEV_FDB_DEL_TO_DEVICE = 4,\n\tSWITCHDEV_FDB_OFFLOADED = 5,\n\tSWITCHDEV_FDB_FLUSH_TO_BRIDGE = 6,\n\tSWITCHDEV_PORT_OBJ_ADD = 7,\n\tSWITCHDEV_PORT_OBJ_DEL = 8,\n\tSWITCHDEV_PORT_ATTR_SET = 9,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_BRIDGE = 10,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_BRIDGE = 11,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_DEVICE = 12,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_DEVICE = 13,\n\tSWITCHDEV_VXLAN_FDB_OFFLOADED = 14,\n\tSWITCHDEV_BRPORT_OFFLOADED = 15,\n\tSWITCHDEV_BRPORT_UNOFFLOADED = 16,\n\tSWITCHDEV_BRPORT_REPLAY = 17,\n};\n\nenum switchdev_obj_id {\n\tSWITCHDEV_OBJ_ID_UNDEFINED = 0,\n\tSWITCHDEV_OBJ_ID_PORT_VLAN = 1,\n\tSWITCHDEV_OBJ_ID_PORT_MDB = 2,\n\tSWITCHDEV_OBJ_ID_HOST_MDB = 3,\n\tSWITCHDEV_OBJ_ID_MRP = 4,\n\tSWITCHDEV_OBJ_ID_RING_TEST_MRP = 5,\n\tSWITCHDEV_OBJ_ID_RING_ROLE_MRP = 6,\n\tSWITCHDEV_OBJ_ID_RING_STATE_MRP = 7,\n\tSWITCHDEV_OBJ_ID_IN_TEST_MRP = 8,\n\tSWITCHDEV_OBJ_ID_IN_ROLE_MRP = 9,\n\tSWITCHDEV_OBJ_ID_IN_STATE_MRP = 10,\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum sys_powerdown {\n\tSYS_AFTR = 0,\n\tSYS_LPA = 1,\n\tSYS_SLEEP = 2,\n\tNUM_SYS_POWERDOWN = 3,\n};\n\nenum sysc_clocks {\n\tSYSC_FCK = 0,\n\tSYSC_ICK = 1,\n\tSYSC_OPTFCK0 = 2,\n\tSYSC_OPTFCK1 = 3,\n\tSYSC_OPTFCK2 = 4,\n\tSYSC_OPTFCK3 = 5,\n\tSYSC_OPTFCK4 = 6,\n\tSYSC_OPTFCK5 = 7,\n\tSYSC_OPTFCK6 = 8,\n\tSYSC_OPTFCK7 = 9,\n\tSYSC_MAX_CLOCKS = 10,\n};\n\nenum sysc_registers {\n\tSYSC_REVISION = 0,\n\tSYSC_SYSCONFIG = 1,\n\tSYSC_SYSSTATUS = 2,\n\tSYSC_MAX_REGS = 3,\n};\n\nenum sysc_soc {\n\tSOC_UNKNOWN = 0,\n\tSOC_2420 = 1,\n\tSOC_2430 = 2,\n\tSOC_AM33 = 3,\n\tSOC_3430 = 4,\n\tSOC_AM35 = 5,\n\tSOC_3630 = 6,\n\tSOC_4430 = 7,\n\tSOC_4460 = 8,\n\tSOC_4470 = 9,\n\tSOC_5430 = 10,\n\tSOC_AM3 = 11,\n\tSOC_AM4 = 12,\n\tSOC_DRA7 = 13,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum ta_cmd {\n\tTA_CMD_BNXT_FASTBOOT = 0,\n\tTA_CMD_BNXT_COPY_COREDUMP = 3,\n};\n\nenum tap_delay_type {\n\tPM_TAPDELAY_INPUT = 0,\n\tPM_TAPDELAY_OUTPUT = 1,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_clsu32_command {\n\tTC_CLSU32_NEW_KNODE = 0,\n\tTC_CLSU32_REPLACE_KNODE = 1,\n\tTC_CLSU32_DELETE_KNODE = 2,\n\tTC_CLSU32_NEW_HNODE = 3,\n\tTC_CLSU32_REPLACE_HNODE = 4,\n\tTC_CLSU32_DELETE_HNODE = 5,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tc_taprio_qopt_cmd {\n\tTAPRIO_CMD_REPLACE = 0,\n\tTAPRIO_CMD_DESTROY = 1,\n\tTAPRIO_CMD_STATS = 2,\n\tTAPRIO_CMD_QUEUE_STATS = 3,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum tee_dma_heap_id {\n\tTEE_DMA_HEAP_SECURE_VIDEO_PLAY = 1,\n\tTEE_DMA_HEAP_TRUSTED_UI = 2,\n\tTEE_DMA_HEAP_SECURE_VIDEO_RECORD = 3,\n};\n\nenum tegra124_function {\n\tTEGRA124_FUNC_SNPS = 0,\n\tTEGRA124_FUNC_XUSB = 1,\n\tTEGRA124_FUNC_UART = 2,\n\tTEGRA124_FUNC_PCIE = 3,\n\tTEGRA124_FUNC_USB3 = 4,\n\tTEGRA124_FUNC_SATA = 5,\n\tTEGRA124_FUNC_RSVD = 6,\n};\n\nenum tegra_bo_sector_layout {\n\tTEGRA_BO_SECTOR_LAYOUT_TEGRA = 0,\n\tTEGRA_BO_SECTOR_LAYOUT_GPU = 1,\n};\n\nenum tegra_bo_tiling_mode {\n\tTEGRA_BO_TILING_MODE_PITCH = 0,\n\tTEGRA_BO_TILING_MODE_TILED = 1,\n\tTEGRA_BO_TILING_MODE_BLOCK = 2,\n};\n\nenum tegra_dfll_pmu_if {\n\tTEGRA_DFLL_PMU_I2C = 0,\n\tTEGRA_DFLL_PMU_PWM = 1,\n};\n\nenum tegra_dpaux_functions {\n\tDPAUX_PADCTL_FUNC_AUX = 0,\n\tDPAUX_PADCTL_FUNC_I2C = 1,\n\tDPAUX_PADCTL_FUNC_OFF = 2,\n};\n\nenum tegra_dsi_format {\n\tTEGRA_DSI_FORMAT_16P = 0,\n\tTEGRA_DSI_FORMAT_18NP = 1,\n\tTEGRA_DSI_FORMAT_18P = 2,\n\tTEGRA_DSI_FORMAT_24P = 3,\n};\n\nenum tegra_icc_client_type {\n\tTEGRA_ICC_NONE = 0,\n\tTEGRA_ICC_NISO = 1,\n\tTEGRA_ICC_ISO_DISPLAY = 2,\n\tTEGRA_ICC_ISO_VI = 3,\n\tTEGRA_ICC_ISO_AUDIO = 4,\n\tTEGRA_ICC_ISO_VIFAL = 5,\n};\n\nenum tegra_io_pad {\n\tTEGRA_IO_PAD_AUDIO = 0,\n\tTEGRA_IO_PAD_AUDIO_HV = 1,\n\tTEGRA_IO_PAD_BB = 2,\n\tTEGRA_IO_PAD_CAM = 3,\n\tTEGRA_IO_PAD_COMP = 4,\n\tTEGRA_IO_PAD_CONN = 5,\n\tTEGRA_IO_PAD_CSIA = 6,\n\tTEGRA_IO_PAD_CSIB = 7,\n\tTEGRA_IO_PAD_CSIC = 8,\n\tTEGRA_IO_PAD_CSID = 9,\n\tTEGRA_IO_PAD_CSIE = 10,\n\tTEGRA_IO_PAD_CSIF = 11,\n\tTEGRA_IO_PAD_CSIG = 12,\n\tTEGRA_IO_PAD_CSIH = 13,\n\tTEGRA_IO_PAD_DAP3 = 14,\n\tTEGRA_IO_PAD_DAP5 = 15,\n\tTEGRA_IO_PAD_DBG = 16,\n\tTEGRA_IO_PAD_DEBUG_NONAO = 17,\n\tTEGRA_IO_PAD_DMIC = 18,\n\tTEGRA_IO_PAD_DMIC_HV = 19,\n\tTEGRA_IO_PAD_DP = 20,\n\tTEGRA_IO_PAD_DSI = 21,\n\tTEGRA_IO_PAD_DSIB = 22,\n\tTEGRA_IO_PAD_DSIC = 23,\n\tTEGRA_IO_PAD_DSID = 24,\n\tTEGRA_IO_PAD_EDP = 25,\n\tTEGRA_IO_PAD_EMMC = 26,\n\tTEGRA_IO_PAD_EMMC2 = 27,\n\tTEGRA_IO_PAD_EQOS = 28,\n\tTEGRA_IO_PAD_GPIO = 29,\n\tTEGRA_IO_PAD_GP_PWM2 = 30,\n\tTEGRA_IO_PAD_GP_PWM3 = 31,\n\tTEGRA_IO_PAD_HDMI = 32,\n\tTEGRA_IO_PAD_HDMI_DP0 = 33,\n\tTEGRA_IO_PAD_HDMI_DP1 = 34,\n\tTEGRA_IO_PAD_HDMI_DP2 = 35,\n\tTEGRA_IO_PAD_HDMI_DP3 = 36,\n\tTEGRA_IO_PAD_HSIC = 37,\n\tTEGRA_IO_PAD_HV = 38,\n\tTEGRA_IO_PAD_LVDS = 39,\n\tTEGRA_IO_PAD_MIPI_BIAS = 40,\n\tTEGRA_IO_PAD_NAND = 41,\n\tTEGRA_IO_PAD_PEX_BIAS = 42,\n\tTEGRA_IO_PAD_PEX_CLK_BIAS = 43,\n\tTEGRA_IO_PAD_PEX_CLK1 = 44,\n\tTEGRA_IO_PAD_PEX_CLK2 = 45,\n\tTEGRA_IO_PAD_PEX_CLK3 = 46,\n\tTEGRA_IO_PAD_PEX_CLK_2_BIAS = 47,\n\tTEGRA_IO_PAD_PEX_CLK_2 = 48,\n\tTEGRA_IO_PAD_PEX_CNTRL = 49,\n\tTEGRA_IO_PAD_PEX_CTL2 = 50,\n\tTEGRA_IO_PAD_PEX_L0_RST = 51,\n\tTEGRA_IO_PAD_PEX_L1_RST = 52,\n\tTEGRA_IO_PAD_PEX_L5_RST = 53,\n\tTEGRA_IO_PAD_PWR_CTL = 54,\n\tTEGRA_IO_PAD_SDMMC1 = 55,\n\tTEGRA_IO_PAD_SDMMC1_HV = 56,\n\tTEGRA_IO_PAD_SDMMC2 = 57,\n\tTEGRA_IO_PAD_SDMMC2_HV = 58,\n\tTEGRA_IO_PAD_SDMMC3 = 59,\n\tTEGRA_IO_PAD_SDMMC3_HV = 60,\n\tTEGRA_IO_PAD_SDMMC4 = 61,\n\tTEGRA_IO_PAD_SOC_GPIO10 = 62,\n\tTEGRA_IO_PAD_SOC_GPIO12 = 63,\n\tTEGRA_IO_PAD_SOC_GPIO13 = 64,\n\tTEGRA_IO_PAD_SOC_GPIO53 = 65,\n\tTEGRA_IO_PAD_SPI = 66,\n\tTEGRA_IO_PAD_SPI_HV = 67,\n\tTEGRA_IO_PAD_SYS_DDC = 68,\n\tTEGRA_IO_PAD_UART = 69,\n\tTEGRA_IO_PAD_UART4 = 70,\n\tTEGRA_IO_PAD_UART5 = 71,\n\tTEGRA_IO_PAD_UFS = 72,\n\tTEGRA_IO_PAD_USB0 = 73,\n\tTEGRA_IO_PAD_USB1 = 74,\n\tTEGRA_IO_PAD_USB2 = 75,\n\tTEGRA_IO_PAD_USB3 = 76,\n\tTEGRA_IO_PAD_USB_BIAS = 77,\n\tTEGRA_IO_PAD_AO_HV = 78,\n};\n\nenum tegra_mux {\n\tTEGRA_MUX_AHB_CLK = 0,\n\tTEGRA_MUX_APB_CLK = 1,\n\tTEGRA_MUX_AUDIO_SYNC = 2,\n\tTEGRA_MUX_CRT = 3,\n\tTEGRA_MUX_DAP1 = 4,\n\tTEGRA_MUX_DAP2 = 5,\n\tTEGRA_MUX_DAP3 = 6,\n\tTEGRA_MUX_DAP4 = 7,\n\tTEGRA_MUX_DAP5 = 8,\n\tTEGRA_MUX_DISPLAYA = 9,\n\tTEGRA_MUX_DISPLAYB = 10,\n\tTEGRA_MUX_EMC_TEST0_DLL = 11,\n\tTEGRA_MUX_EMC_TEST1_DLL = 12,\n\tTEGRA_MUX_GMI = 13,\n\tTEGRA_MUX_GMI_INT = 14,\n\tTEGRA_MUX_HDMI = 15,\n\tTEGRA_MUX_I2CP = 16,\n\tTEGRA_MUX_I2C1 = 17,\n\tTEGRA_MUX_I2C2 = 18,\n\tTEGRA_MUX_I2C3 = 19,\n\tTEGRA_MUX_IDE = 20,\n\tTEGRA_MUX_IRDA = 21,\n\tTEGRA_MUX_KBC = 22,\n\tTEGRA_MUX_MIO = 23,\n\tTEGRA_MUX_MIPI_HS = 24,\n\tTEGRA_MUX_NAND = 25,\n\tTEGRA_MUX_OSC = 26,\n\tTEGRA_MUX_OWR = 27,\n\tTEGRA_MUX_PCIE = 28,\n\tTEGRA_MUX_PLLA_OUT = 29,\n\tTEGRA_MUX_PLLC_OUT1 = 30,\n\tTEGRA_MUX_PLLM_OUT1 = 31,\n\tTEGRA_MUX_PLLP_OUT2 = 32,\n\tTEGRA_MUX_PLLP_OUT3 = 33,\n\tTEGRA_MUX_PLLP_OUT4 = 34,\n\tTEGRA_MUX_PWM = 35,\n\tTEGRA_MUX_PWR_INTR = 36,\n\tTEGRA_MUX_PWR_ON = 37,\n\tTEGRA_MUX_RSVD1 = 38,\n\tTEGRA_MUX_RSVD2 = 39,\n\tTEGRA_MUX_RSVD3 = 40,\n\tTEGRA_MUX_RSVD4 = 41,\n\tTEGRA_MUX_RTCK = 42,\n\tTEGRA_MUX_SDIO1 = 43,\n\tTEGRA_MUX_SDIO2 = 44,\n\tTEGRA_MUX_SDIO3 = 45,\n\tTEGRA_MUX_SDIO4 = 46,\n\tTEGRA_MUX_SFLASH = 47,\n\tTEGRA_MUX_SPDIF = 48,\n\tTEGRA_MUX_SPI1 = 49,\n\tTEGRA_MUX_SPI2 = 50,\n\tTEGRA_MUX_SPI2_ALT = 51,\n\tTEGRA_MUX_SPI3 = 52,\n\tTEGRA_MUX_SPI4 = 53,\n\tTEGRA_MUX_TRACE = 54,\n\tTEGRA_MUX_TWC = 55,\n\tTEGRA_MUX_UARTA = 56,\n\tTEGRA_MUX_UARTB = 57,\n\tTEGRA_MUX_UARTC = 58,\n\tTEGRA_MUX_UARTD = 59,\n\tTEGRA_MUX_UARTE = 60,\n\tTEGRA_MUX_ULPI = 61,\n\tTEGRA_MUX_VI = 62,\n\tTEGRA_MUX_VI_SENSOR_CLK = 63,\n\tTEGRA_MUX_XIO = 64,\n};\n\nenum tegra_mux___2 {\n\tTEGRA_MUX_BLINK = 0,\n\tTEGRA_MUX_CCLA = 1,\n\tTEGRA_MUX_CEC = 2,\n\tTEGRA_MUX_CLDVFS = 3,\n\tTEGRA_MUX_CLK = 4,\n\tTEGRA_MUX_CLK12 = 5,\n\tTEGRA_MUX_CPU = 6,\n\tTEGRA_MUX_CSI = 7,\n\tTEGRA_MUX_DAP = 8,\n\tTEGRA_MUX_DAP1___2 = 9,\n\tTEGRA_MUX_DAP2___2 = 10,\n\tTEGRA_MUX_DEV3 = 11,\n\tTEGRA_MUX_DISPLAYA___2 = 12,\n\tTEGRA_MUX_DISPLAYA_ALT = 13,\n\tTEGRA_MUX_DISPLAYB___2 = 14,\n\tTEGRA_MUX_DP = 15,\n\tTEGRA_MUX_DSI_B = 16,\n\tTEGRA_MUX_DTV = 17,\n\tTEGRA_MUX_EXTPERIPH1 = 18,\n\tTEGRA_MUX_EXTPERIPH2 = 19,\n\tTEGRA_MUX_EXTPERIPH3 = 20,\n\tTEGRA_MUX_GMI___2 = 21,\n\tTEGRA_MUX_GMI_ALT = 22,\n\tTEGRA_MUX_HDA = 23,\n\tTEGRA_MUX_HSI = 24,\n\tTEGRA_MUX_I2C1___2 = 25,\n\tTEGRA_MUX_I2C2___2 = 26,\n\tTEGRA_MUX_I2C3___2 = 27,\n\tTEGRA_MUX_I2C4 = 28,\n\tTEGRA_MUX_I2CPWR = 29,\n\tTEGRA_MUX_I2S0 = 30,\n\tTEGRA_MUX_I2S1 = 31,\n\tTEGRA_MUX_I2S2 = 32,\n\tTEGRA_MUX_I2S3 = 33,\n\tTEGRA_MUX_I2S4 = 34,\n\tTEGRA_MUX_IRDA___2 = 35,\n\tTEGRA_MUX_KBC___2 = 36,\n\tTEGRA_MUX_OWR___2 = 37,\n\tTEGRA_MUX_PE = 38,\n\tTEGRA_MUX_PE0 = 39,\n\tTEGRA_MUX_PE1 = 40,\n\tTEGRA_MUX_PMI = 41,\n\tTEGRA_MUX_PWM0 = 42,\n\tTEGRA_MUX_PWM1 = 43,\n\tTEGRA_MUX_PWM2 = 44,\n\tTEGRA_MUX_PWM3 = 45,\n\tTEGRA_MUX_PWRON = 46,\n\tTEGRA_MUX_RESET_OUT_N = 47,\n\tTEGRA_MUX_RSVD1___2 = 48,\n\tTEGRA_MUX_RSVD2___2 = 49,\n\tTEGRA_MUX_RSVD3___2 = 50,\n\tTEGRA_MUX_RSVD4___2 = 51,\n\tTEGRA_MUX_RTCK___2 = 52,\n\tTEGRA_MUX_SATA = 53,\n\tTEGRA_MUX_SDMMC1 = 54,\n\tTEGRA_MUX_SDMMC2 = 55,\n\tTEGRA_MUX_SDMMC3 = 56,\n\tTEGRA_MUX_SDMMC4 = 57,\n\tTEGRA_MUX_SOC = 58,\n\tTEGRA_MUX_SPDIF___2 = 59,\n\tTEGRA_MUX_SPI1___2 = 60,\n\tTEGRA_MUX_SPI2___2 = 61,\n\tTEGRA_MUX_SPI3___2 = 62,\n\tTEGRA_MUX_SPI4___2 = 63,\n\tTEGRA_MUX_SPI5 = 64,\n\tTEGRA_MUX_SPI6 = 65,\n\tTEGRA_MUX_SYS = 66,\n\tTEGRA_MUX_TMDS = 67,\n\tTEGRA_MUX_TRACE___2 = 68,\n\tTEGRA_MUX_UARTA___2 = 69,\n\tTEGRA_MUX_UARTB___2 = 70,\n\tTEGRA_MUX_UARTC___2 = 71,\n\tTEGRA_MUX_UARTD___2 = 72,\n\tTEGRA_MUX_ULPI___2 = 73,\n\tTEGRA_MUX_USB = 74,\n\tTEGRA_MUX_VGP1 = 75,\n\tTEGRA_MUX_VGP2 = 76,\n\tTEGRA_MUX_VGP3 = 77,\n\tTEGRA_MUX_VGP4 = 78,\n\tTEGRA_MUX_VGP5 = 79,\n\tTEGRA_MUX_VGP6 = 80,\n\tTEGRA_MUX_VI___2 = 81,\n\tTEGRA_MUX_VI_ALT1 = 82,\n\tTEGRA_MUX_VI_ALT3 = 83,\n\tTEGRA_MUX_VIMCLK2 = 84,\n\tTEGRA_MUX_VIMCLK2_ALT = 85,\n};\n\nenum tegra_mux___3 {\n\tTEGRA_MUX_BLINK___2 = 0,\n\tTEGRA_MUX_CEC___2 = 1,\n\tTEGRA_MUX_CLK_12M_OUT = 2,\n\tTEGRA_MUX_CLK_32K_IN = 3,\n\tTEGRA_MUX_CORE_PWR_REQ = 4,\n\tTEGRA_MUX_CPU_PWR_REQ = 5,\n\tTEGRA_MUX_CRT___2 = 6,\n\tTEGRA_MUX_DAP___2 = 7,\n\tTEGRA_MUX_DDR = 8,\n\tTEGRA_MUX_DEV3___2 = 9,\n\tTEGRA_MUX_DISPLAYA___3 = 10,\n\tTEGRA_MUX_DISPLAYB___3 = 11,\n\tTEGRA_MUX_DTV___2 = 12,\n\tTEGRA_MUX_EXTPERIPH1___2 = 13,\n\tTEGRA_MUX_EXTPERIPH2___2 = 14,\n\tTEGRA_MUX_EXTPERIPH3___2 = 15,\n\tTEGRA_MUX_GMI___3 = 16,\n\tTEGRA_MUX_GMI_ALT___2 = 17,\n\tTEGRA_MUX_HDA___2 = 18,\n\tTEGRA_MUX_HDCP = 19,\n\tTEGRA_MUX_HDMI___2 = 20,\n\tTEGRA_MUX_HSI___2 = 21,\n\tTEGRA_MUX_I2C1___3 = 22,\n\tTEGRA_MUX_I2C2___3 = 23,\n\tTEGRA_MUX_I2C3___3 = 24,\n\tTEGRA_MUX_I2C4___2 = 25,\n\tTEGRA_MUX_I2CPWR___2 = 26,\n\tTEGRA_MUX_I2S0___2 = 27,\n\tTEGRA_MUX_I2S1___2 = 28,\n\tTEGRA_MUX_I2S2___2 = 29,\n\tTEGRA_MUX_I2S3___2 = 30,\n\tTEGRA_MUX_I2S4___2 = 31,\n\tTEGRA_MUX_INVALID = 32,\n\tTEGRA_MUX_KBC___3 = 33,\n\tTEGRA_MUX_MIO___2 = 34,\n\tTEGRA_MUX_NAND___2 = 35,\n\tTEGRA_MUX_NAND_ALT = 36,\n\tTEGRA_MUX_OWR___3 = 37,\n\tTEGRA_MUX_PCIE___2 = 38,\n\tTEGRA_MUX_PWM0___2 = 39,\n\tTEGRA_MUX_PWM1___2 = 40,\n\tTEGRA_MUX_PWM2___2 = 41,\n\tTEGRA_MUX_PWM3___2 = 42,\n\tTEGRA_MUX_PWR_INT_N = 43,\n\tTEGRA_MUX_RSVD1___3 = 44,\n\tTEGRA_MUX_RSVD2___3 = 45,\n\tTEGRA_MUX_RSVD3___3 = 46,\n\tTEGRA_MUX_RSVD4___3 = 47,\n\tTEGRA_MUX_RTCK___3 = 48,\n\tTEGRA_MUX_SATA___2 = 49,\n\tTEGRA_MUX_SDMMC1___2 = 50,\n\tTEGRA_MUX_SDMMC2___2 = 51,\n\tTEGRA_MUX_SDMMC3___2 = 52,\n\tTEGRA_MUX_SDMMC4___2 = 53,\n\tTEGRA_MUX_SPDIF___3 = 54,\n\tTEGRA_MUX_SPI1___3 = 55,\n\tTEGRA_MUX_SPI2___3 = 56,\n\tTEGRA_MUX_SPI2_ALT___2 = 57,\n\tTEGRA_MUX_SPI3___3 = 58,\n\tTEGRA_MUX_SPI4___3 = 59,\n\tTEGRA_MUX_SPI5___2 = 60,\n\tTEGRA_MUX_SPI6___2 = 61,\n\tTEGRA_MUX_SYSCLK = 62,\n\tTEGRA_MUX_TEST = 63,\n\tTEGRA_MUX_TRACE___3 = 64,\n\tTEGRA_MUX_UARTA___3 = 65,\n\tTEGRA_MUX_UARTB___3 = 66,\n\tTEGRA_MUX_UARTC___3 = 67,\n\tTEGRA_MUX_UARTD___3 = 68,\n\tTEGRA_MUX_UARTE___2 = 69,\n\tTEGRA_MUX_ULPI___3 = 70,\n\tTEGRA_MUX_VGP1___2 = 71,\n\tTEGRA_MUX_VGP2___2 = 72,\n\tTEGRA_MUX_VGP3___2 = 73,\n\tTEGRA_MUX_VGP4___2 = 74,\n\tTEGRA_MUX_VGP5___2 = 75,\n\tTEGRA_MUX_VGP6___2 = 76,\n\tTEGRA_MUX_VI___3 = 77,\n\tTEGRA_MUX_VI_ALT1___2 = 78,\n\tTEGRA_MUX_VI_ALT2 = 79,\n\tTEGRA_MUX_VI_ALT3___2 = 80,\n};\n\nenum tegra_mux___4 {\n\tTEGRA_MUX_BLINK___3 = 0,\n\tTEGRA_MUX_CEC___3 = 1,\n\tTEGRA_MUX_CLDVFS___2 = 2,\n\tTEGRA_MUX_CLK___2 = 3,\n\tTEGRA_MUX_CLK12___2 = 4,\n\tTEGRA_MUX_CPU___2 = 5,\n\tTEGRA_MUX_DAP___3 = 6,\n\tTEGRA_MUX_DAP1___3 = 7,\n\tTEGRA_MUX_DAP2___3 = 8,\n\tTEGRA_MUX_DEV3___3 = 9,\n\tTEGRA_MUX_DISPLAYA___4 = 10,\n\tTEGRA_MUX_DISPLAYA_ALT___2 = 11,\n\tTEGRA_MUX_DISPLAYB___4 = 12,\n\tTEGRA_MUX_DTV___3 = 13,\n\tTEGRA_MUX_EMC_DLL = 14,\n\tTEGRA_MUX_EXTPERIPH1___3 = 15,\n\tTEGRA_MUX_EXTPERIPH2___3 = 16,\n\tTEGRA_MUX_EXTPERIPH3___3 = 17,\n\tTEGRA_MUX_GMI___4 = 18,\n\tTEGRA_MUX_GMI_ALT___3 = 19,\n\tTEGRA_MUX_HDA___3 = 20,\n\tTEGRA_MUX_HSI___3 = 21,\n\tTEGRA_MUX_I2C1___4 = 22,\n\tTEGRA_MUX_I2C2___4 = 23,\n\tTEGRA_MUX_I2C3___4 = 24,\n\tTEGRA_MUX_I2C4___3 = 25,\n\tTEGRA_MUX_I2CPWR___3 = 26,\n\tTEGRA_MUX_I2S0___3 = 27,\n\tTEGRA_MUX_I2S1___3 = 28,\n\tTEGRA_MUX_I2S2___3 = 29,\n\tTEGRA_MUX_I2S3___3 = 30,\n\tTEGRA_MUX_I2S4___3 = 31,\n\tTEGRA_MUX_IRDA___3 = 32,\n\tTEGRA_MUX_KBC___4 = 33,\n\tTEGRA_MUX_NAND___3 = 34,\n\tTEGRA_MUX_NAND_ALT___2 = 35,\n\tTEGRA_MUX_OWR___4 = 36,\n\tTEGRA_MUX_PMI___2 = 37,\n\tTEGRA_MUX_PWM0___3 = 38,\n\tTEGRA_MUX_PWM1___3 = 39,\n\tTEGRA_MUX_PWM2___3 = 40,\n\tTEGRA_MUX_PWM3___3 = 41,\n\tTEGRA_MUX_PWRON___2 = 42,\n\tTEGRA_MUX_RESET_OUT_N___2 = 43,\n\tTEGRA_MUX_RSVD1___4 = 44,\n\tTEGRA_MUX_RSVD2___4 = 45,\n\tTEGRA_MUX_RSVD3___4 = 46,\n\tTEGRA_MUX_RSVD4___4 = 47,\n\tTEGRA_MUX_RTCK___4 = 48,\n\tTEGRA_MUX_SDMMC1___3 = 49,\n\tTEGRA_MUX_SDMMC2___3 = 50,\n\tTEGRA_MUX_SDMMC3___3 = 51,\n\tTEGRA_MUX_SDMMC4___3 = 52,\n\tTEGRA_MUX_SOC___2 = 53,\n\tTEGRA_MUX_SPDIF___4 = 54,\n\tTEGRA_MUX_SPI1___4 = 55,\n\tTEGRA_MUX_SPI2___4 = 56,\n\tTEGRA_MUX_SPI3___4 = 57,\n\tTEGRA_MUX_SPI4___4 = 58,\n\tTEGRA_MUX_SPI5___3 = 59,\n\tTEGRA_MUX_SPI6___3 = 60,\n\tTEGRA_MUX_SYSCLK___2 = 61,\n\tTEGRA_MUX_TRACE___4 = 62,\n\tTEGRA_MUX_UARTA___4 = 63,\n\tTEGRA_MUX_UARTB___4 = 64,\n\tTEGRA_MUX_UARTC___4 = 65,\n\tTEGRA_MUX_UARTD___4 = 66,\n\tTEGRA_MUX_ULPI___4 = 67,\n\tTEGRA_MUX_USB___2 = 68,\n\tTEGRA_MUX_VGP1___3 = 69,\n\tTEGRA_MUX_VGP2___3 = 70,\n\tTEGRA_MUX_VGP3___3 = 71,\n\tTEGRA_MUX_VGP4___3 = 72,\n\tTEGRA_MUX_VGP5___3 = 73,\n\tTEGRA_MUX_VGP6___3 = 74,\n\tTEGRA_MUX_VI___4 = 75,\n\tTEGRA_MUX_VI_ALT1___3 = 76,\n\tTEGRA_MUX_VI_ALT3___3 = 77,\n};\n\nenum tegra_pin_type {\n\tPIN_CFG_IGNORE = 0,\n\tPIN_CFG_COL = 1,\n\tPIN_CFG_ROW = 2,\n};\n\nenum tegra_pinconf_param {\n\tTEGRA_PINCONF_PARAM_PULL = 0,\n\tTEGRA_PINCONF_PARAM_TRISTATE = 1,\n\tTEGRA_PINCONF_PARAM_ENABLE_INPUT = 2,\n\tTEGRA_PINCONF_PARAM_OPEN_DRAIN = 3,\n\tTEGRA_PINCONF_PARAM_LOCK = 4,\n\tTEGRA_PINCONF_PARAM_IORESET = 5,\n\tTEGRA_PINCONF_PARAM_RCV_SEL = 6,\n\tTEGRA_PINCONF_PARAM_HIGH_SPEED_MODE = 7,\n\tTEGRA_PINCONF_PARAM_SCHMITT = 8,\n\tTEGRA_PINCONF_PARAM_LOW_POWER_MODE = 9,\n\tTEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH = 10,\n\tTEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH = 11,\n\tTEGRA_PINCONF_PARAM_SLEW_RATE_FALLING = 12,\n\tTEGRA_PINCONF_PARAM_SLEW_RATE_RISING = 13,\n\tTEGRA_PINCONF_PARAM_DRIVE_TYPE = 14,\n\tTEGRA_PINCONF_PARAM_GPIO_MODE = 15,\n};\n\nenum tegra_platform {\n\tTEGRA_PLATFORM_SILICON = 0,\n\tTEGRA_PLATFORM_QT = 1,\n\tTEGRA_PLATFORM_SYSTEM_FPGA = 2,\n\tTEGRA_PLATFORM_UNIT_FPGA = 3,\n\tTEGRA_PLATFORM_ASIM_QT = 4,\n\tTEGRA_PLATFORM_ASIM_LINSIM = 5,\n\tTEGRA_PLATFORM_DSIM_ASIM_LINSIM = 6,\n\tTEGRA_PLATFORM_VERIFICATION_SIMULATION = 7,\n\tTEGRA_PLATFORM_VDK = 8,\n\tTEGRA_PLATFORM_VSP = 9,\n\tTEGRA_PLATFORM_MAX = 10,\n};\n\nenum tegra_revision {\n\tTEGRA_REVISION_UNKNOWN = 0,\n\tTEGRA_REVISION_A01 = 1,\n\tTEGRA_REVISION_A02 = 2,\n\tTEGRA_REVISION_A03 = 3,\n\tTEGRA_REVISION_A03p = 4,\n\tTEGRA_REVISION_A04 = 5,\n\tTEGRA_REVISION_MAX = 6,\n};\n\nenum tegra_state {\n\tTEGRA_C1 = 0,\n\tTEGRA_C7 = 1,\n\tTEGRA_CC6 = 2,\n\tTEGRA_STATE_COUNT = 3,\n};\n\nenum tegra_super_gen {\n\tgen4 = 4,\n\tgen5 = 5,\n};\n\nenum tegra_suspend_mode {\n\tTEGRA_SUSPEND_NONE = 0,\n\tTEGRA_SUSPEND_LP2 = 1,\n\tTEGRA_SUSPEND_LP1 = 2,\n\tTEGRA_SUSPEND_LP0 = 3,\n\tTEGRA_MAX_SUSPEND_MODE = 4,\n\tTEGRA_SUSPEND_NOT_READY = 5,\n};\n\nenum tegra_xusb_padctl_param {\n\tTEGRA_XUSB_PADCTL_IDDQ = 0,\n};\n\nenum thermal_device_mode {\n\tTHERMAL_DEVICE_DISABLED = 0,\n\tTHERMAL_DEVICE_ENABLED = 1,\n};\n\nenum thermal_notify_event {\n\tTHERMAL_EVENT_UNSPECIFIED = 0,\n\tTHERMAL_EVENT_TEMP_SAMPLE = 1,\n\tTHERMAL_TRIP_VIOLATED = 2,\n\tTHERMAL_TRIP_CHANGED = 3,\n\tTHERMAL_DEVICE_DOWN = 4,\n\tTHERMAL_DEVICE_UP = 5,\n\tTHERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6,\n\tTHERMAL_TABLE_CHANGED = 7,\n\tTHERMAL_EVENT_KEEP_ALIVE = 8,\n\tTHERMAL_TZ_BIND_CDEV = 9,\n\tTHERMAL_TZ_UNBIND_CDEV = 10,\n\tTHERMAL_INSTANCE_WEIGHT_CHANGED = 11,\n\tTHERMAL_TZ_RESUME = 12,\n\tTHERMAL_TZ_ADD_THRESHOLD = 13,\n\tTHERMAL_TZ_DEL_THRESHOLD = 14,\n\tTHERMAL_TZ_FLUSH_THRESHOLDS = 15,\n};\n\nenum thermal_trend {\n\tTHERMAL_TREND_STABLE = 0,\n\tTHERMAL_TREND_RAISING = 1,\n\tTHERMAL_TREND_DROPPING = 2,\n};\n\nenum thermal_trip_type {\n\tTHERMAL_TRIP_ACTIVE = 0,\n\tTHERMAL_TRIP_PASSIVE = 1,\n\tTHERMAL_TRIP_HOT = 2,\n\tTHERMAL_TRIP_CRITICAL = 3,\n};\n\nenum ti_adpll_clocks {\n\tTI_ADPLL_DCO = 0,\n\tTI_ADPLL_DCO_GATE = 1,\n\tTI_ADPLL_N2 = 2,\n\tTI_ADPLL_M2 = 3,\n\tTI_ADPLL_M2_GATE = 4,\n\tTI_ADPLL_BYPASS = 5,\n\tTI_ADPLL_HIF = 6,\n\tTI_ADPLL_DIV2 = 7,\n\tTI_ADPLL_CLKOUT = 8,\n\tTI_ADPLL_CLKOUT2 = 9,\n\tTI_ADPLL_M3 = 10,\n};\n\nenum ti_adpll_inputs {\n\tTI_ADPLL_CLKINP = 0,\n\tTI_ADPLL_CLKINPULOW = 1,\n\tTI_ADPLL_CLKINPHIF = 2,\n};\n\nenum ti_adpll_lj_outputs {\n\tTI_ADPLL_LJ_CLKDCOLDO = 0,\n\tTI_ADPLL_LJ_CLKOUT = 1,\n\tTI_ADPLL_LJ_CLKOUTLDO = 2,\n};\n\nenum ti_adpll_s_outputs {\n\tTI_ADPLL_S_DCOCLKLDO = 0,\n\tTI_ADPLL_S_CLKOUT = 1,\n\tTI_ADPLL_S_CLKOUTX2 = 2,\n\tTI_ADPLL_S_CLKOUTHIF = 3,\n};\n\nenum ti_sysc_module_type {\n\tTI_SYSC_OMAP2 = 0,\n\tTI_SYSC_OMAP2_TIMER = 1,\n\tTI_SYSC_OMAP3_SHAM = 2,\n\tTI_SYSC_OMAP3_AES = 3,\n\tTI_SYSC_OMAP4 = 4,\n\tTI_SYSC_OMAP4_TIMER = 5,\n\tTI_SYSC_OMAP4_SIMPLE = 6,\n\tTI_SYSC_OMAP34XX_SR = 7,\n\tTI_SYSC_OMAP36XX_SR = 8,\n\tTI_SYSC_OMAP4_SR = 9,\n\tTI_SYSC_OMAP4_MCASP = 10,\n\tTI_SYSC_OMAP4_USB_HOST_FS = 11,\n\tTI_SYSC_DRA7_MCAN = 12,\n\tTI_SYSC_PRUSS = 13,\n};\n\nenum tick_broadcast_mode {\n\tTICK_BROADCAST_OFF = 0,\n\tTICK_BROADCAST_ON = 1,\n\tTICK_BROADCAST_FORCE = 2,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPERS_MAX = 1,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum tp_func_state {\n\tTP_FUNC_0 = 0,\n\tTP_FUNC_1 = 1,\n\tTP_FUNC_2 = 2,\n\tTP_FUNC_N = 3,\n};\n\nenum tp_mode {\n\tIAP_MODE = 1,\n\tMAIN_MODE = 2,\n};\n\nenum tp_transition_sync {\n\tTP_TRANSITION_SYNC_1_0_1 = 0,\n\tTP_TRANSITION_SYNC_N_2_1 = 1,\n\t_NR_TP_TRANSITION_SYNC = 2,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tph_mem_type {\n\tTPH_MEM_TYPE_VM = 0,\n\tTPH_MEM_TYPE_PM = 1,\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum tps65090_cells {\n\tPMIC = 0,\n\tCHARGER = 1,\n};\n\nenum tps65214_regulator_id {\n\tTPS65214_LDO_1 = 3,\n\tTPS65214_LDO_2 = 4,\n};\n\nenum tps65215_regulator_id {\n\tTPS65215_LDO_2 = 4,\n};\n\nenum tps65217_bl_fdim {\n\tTPS65217_BL_FDIM_100HZ = 0,\n\tTPS65217_BL_FDIM_200HZ = 1,\n\tTPS65217_BL_FDIM_500HZ = 2,\n\tTPS65217_BL_FDIM_1000HZ = 3,\n};\n\nenum tps65217_bl_isel {\n\tTPS65217_BL_ISET1 = 1,\n\tTPS65217_BL_ISET2 = 2,\n};\n\nenum tps65217_regulator_id {\n\tTPS65217_DCDC_1 = 0,\n\tTPS65217_DCDC_2 = 1,\n\tTPS65217_DCDC_3 = 2,\n\tTPS65217_LDO_1 = 3,\n\tTPS65217_LDO_2 = 4,\n\tTPS65217_LDO_3 = 5,\n\tTPS65217_LDO_4 = 6,\n};\n\nenum tps65218_irqs {\n\tTPS65218_PRGC_IRQ = 0,\n\tTPS65218_CC_AQC_IRQ = 1,\n\tTPS65218_HOT_IRQ = 2,\n\tTPS65218_PB_IRQ = 3,\n\tTPS65218_AC_IRQ = 4,\n\tTPS65218_VPRG_IRQ = 5,\n\tTPS65218_INVALID1_IRQ = 6,\n\tTPS65218_INVALID2_IRQ = 7,\n\tTPS65218_LS1_I_IRQ = 8,\n\tTPS65218_LS2_I_IRQ = 9,\n\tTPS65218_LS3_I_IRQ = 10,\n\tTPS65218_LS1_F_IRQ = 11,\n\tTPS65218_LS2_F_IRQ = 12,\n\tTPS65218_LS3_F_IRQ = 13,\n\tTPS65218_INVALID3_IRQ = 14,\n\tTPS65218_INVALID4_IRQ = 15,\n};\n\nenum tps65218_regulator_id {\n\tTPS65218_DCDC_1 = 0,\n\tTPS65218_DCDC_2 = 1,\n\tTPS65218_DCDC_3 = 2,\n\tTPS65218_DCDC_4 = 3,\n\tTPS65218_DCDC_5 = 4,\n\tTPS65218_DCDC_6 = 5,\n\tTPS65218_LDO_1 = 6,\n\tTPS65218_LS_2 = 7,\n\tTPS65218_LS_3 = 8,\n};\n\nenum tps65219_regulator_id {\n\tTPS65219_BUCK_1 = 0,\n\tTPS65219_BUCK_2 = 1,\n\tTPS65219_BUCK_3 = 2,\n\tTPS65219_LDO_1 = 3,\n\tTPS65219_LDO_2 = 4,\n\tTPS65219_LDO_3 = 5,\n\tTPS65219_LDO_4 = 6,\n};\n\nenum tps65917_external_requestor_id {\n\tTPS65917_EXTERNAL_REQSTR_ID_REGEN1 = 0,\n\tTPS65917_EXTERNAL_REQSTR_ID_REGEN2 = 1,\n\tTPS65917_EXTERNAL_REQSTR_ID_REGEN3 = 2,\n\tTPS65917_EXTERNAL_REQSTR_ID_SMPS1 = 3,\n\tTPS65917_EXTERNAL_REQSTR_ID_SMPS2 = 4,\n\tTPS65917_EXTERNAL_REQSTR_ID_SMPS3 = 5,\n\tTPS65917_EXTERNAL_REQSTR_ID_SMPS4 = 6,\n\tTPS65917_EXTERNAL_REQSTR_ID_SMPS5 = 7,\n\tTPS65917_EXTERNAL_REQSTR_ID_SMPS12 = 8,\n\tTPS65917_EXTERNAL_REQSTR_ID_LDO1 = 9,\n\tTPS65917_EXTERNAL_REQSTR_ID_LDO2 = 10,\n\tTPS65917_EXTERNAL_REQSTR_ID_LDO3 = 11,\n\tTPS65917_EXTERNAL_REQSTR_ID_LDO4 = 12,\n\tTPS65917_EXTERNAL_REQSTR_ID_LDO5 = 13,\n\tTPS65917_EXTERNAL_REQSTR_ID_MAX = 14,\n};\n\nenum tps65917_irqs {\n\tTPS65917_RESERVED1 = 0,\n\tTPS65917_PWRON_IRQ = 1,\n\tTPS65917_LONG_PRESS_KEY_IRQ = 2,\n\tTPS65917_RESERVED2 = 3,\n\tTPS65917_PWRDOWN_IRQ = 4,\n\tTPS65917_HOTDIE_IRQ = 5,\n\tTPS65917_VSYS_MON_IRQ = 6,\n\tTPS65917_RESERVED3 = 7,\n\tTPS65917_RESERVED4 = 8,\n\tTPS65917_OTP_ERROR_IRQ = 9,\n\tTPS65917_WDT_IRQ = 10,\n\tTPS65917_RESERVED5 = 11,\n\tTPS65917_RESET_IN_IRQ = 12,\n\tTPS65917_FSD_IRQ = 13,\n\tTPS65917_SHORT_IRQ = 14,\n\tTPS65917_RESERVED6 = 15,\n\tTPS65917_GPADC_AUTO_0_IRQ = 16,\n\tTPS65917_GPADC_AUTO_1_IRQ = 17,\n\tTPS65917_GPADC_EOC_SW_IRQ = 18,\n\tTPS65917_RESREVED6 = 19,\n\tTPS65917_RESERVED7 = 20,\n\tTPS65917_RESERVED8 = 21,\n\tTPS65917_RESERVED9 = 22,\n\tTPS65917_VBUS_IRQ = 23,\n\tTPS65917_GPIO_0_IRQ = 24,\n\tTPS65917_GPIO_1_IRQ = 25,\n\tTPS65917_GPIO_2_IRQ = 26,\n\tTPS65917_GPIO_3_IRQ = 27,\n\tTPS65917_GPIO_4_IRQ = 28,\n\tTPS65917_GPIO_5_IRQ = 29,\n\tTPS65917_GPIO_6_IRQ = 30,\n\tTPS65917_RESERVED10 = 31,\n\tTPS65917_NUM_IRQ = 32,\n};\n\nenum tps65917_regulators {\n\tTPS65917_REG_SMPS1 = 0,\n\tTPS65917_REG_SMPS2 = 1,\n\tTPS65917_REG_SMPS3 = 2,\n\tTPS65917_REG_SMPS4 = 3,\n\tTPS65917_REG_SMPS5 = 4,\n\tTPS65917_REG_SMPS12 = 5,\n\tTPS65917_REG_LDO1 = 6,\n\tTPS65917_REG_LDO2 = 7,\n\tTPS65917_REG_LDO3 = 8,\n\tTPS65917_REG_LDO4 = 9,\n\tTPS65917_REG_LDO5 = 10,\n\tTPS65917_REG_REGEN1 = 11,\n\tTPS65917_REG_REGEN2 = 12,\n\tTPS65917_REG_REGEN3 = 13,\n\tTPS65917_NUM_REGS = 14,\n};\n\nenum tpu_pin_state {\n\tTPU_PIN_INACTIVE = 0,\n\tTPU_PIN_PWM = 1,\n\tTPU_PIN_ACTIVE = 2,\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_NEED_RESCHED_LAZY = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n\tTRACE_FLAG_BH_OFF = 128,\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n\tTRACE_FILE_PAUSE = 8,\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_FIELDS_BIT = 8,\n\tTRACE_ITER_PRINTK_BIT = 9,\n\tTRACE_ITER_ANNOTATE_BIT = 10,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 11,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 12,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 13,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 14,\n\tTRACE_ITER_LATENCY_FMT_BIT = 15,\n\tTRACE_ITER_RECORD_CMD_BIT = 16,\n\tTRACE_ITER_RECORD_TGID_BIT = 17,\n\tTRACE_ITER_OVERWRITE_BIT = 18,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 19,\n\tTRACE_ITER_IRQ_INFO_BIT = 20,\n\tTRACE_ITER_MARKERS_BIT = 21,\n\tTRACE_ITER_EVENT_FORK_BIT = 22,\n\tTRACE_ITER_TRACE_PRINTK_BIT = 23,\n\tTRACE_ITER_COPY_MARKER_BIT = 24,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 25,\n\tTRACE_ITER_HASH_PTR_BIT = 26,\n\tTRACE_ITER_BITMASK_LIST_BIT = 27,\n\tTRACE_ITER_STACKTRACE_BIT = 28,\n\tTRACE_ITER_LAST_BIT = 29,\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_GRAPH_RETADDR_ENT = 12,\n\tTRACE_USER_STACK = 13,\n\tTRACE_BLK = 14,\n\tTRACE_BPUTS = 15,\n\tTRACE_HWLAT = 16,\n\tTRACE_OSNOISE = 17,\n\tTRACE_TIMERLAT = 18,\n\tTRACE_RAW_DATA = 19,\n\tTRACE_FUNC_REPEATS = 20,\n\t__TRACE_LAST_TYPE = 21,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum transact_state {\n\tTransactionUninitialized = 0,\n\tTransactionActive = 1,\n\tTransactionPrepared = 2,\n\tTransactionCommitted = 3,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum tsens_irq_type {\n\tLOWER = 0,\n\tUPPER = 1,\n\tCRITICAL = 2,\n};\n\nenum tsens_ver {\n\tVER_0 = 0,\n\tVER_0_1 = 1,\n\tVER_1_X = 2,\n\tVER_1_X_NO_RPM = 3,\n\tVER_2_X = 4,\n\tVER_2_X_NO_RPM = 5,\n};\n\nenum tshut_mode {\n\tTSHUT_MODE_CRU = 0,\n\tTSHUT_MODE_GPIO = 1,\n};\n\nenum tshut_polarity {\n\tTSHUT_LOW_ACTIVE = 0,\n\tTSHUT_HIGH_ACTIVE = 1,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum ttc_control {\n\tDMA_CONTROL_TTC_64 = 0,\n\tDMA_CONTROL_TTC_128 = 16384,\n\tDMA_CONTROL_TTC_192 = 32768,\n\tDMA_CONTROL_TTC_256 = 49152,\n\tDMA_CONTROL_TTC_40 = 65536,\n\tDMA_CONTROL_TTC_32 = 81920,\n\tDMA_CONTROL_TTC_24 = 98304,\n\tDMA_CONTROL_TTC_16 = 114688,\n};\n\nenum ttc_control___2 {\n\tDMA_CONTROL_TTC_DEFAULT = 0,\n\tDMA_CONTROL_TTC_64___2 = 16384,\n\tDMA_CONTROL_TTC_128___2 = 32768,\n\tDMA_CONTROL_TTC_256___2 = 49152,\n\tDMA_CONTROL_TTC_18 = 4194304,\n\tDMA_CONTROL_TTC_24___2 = 4210688,\n\tDMA_CONTROL_TTC_32___2 = 4227072,\n\tDMA_CONTROL_TTC_40___2 = 4243456,\n\tDMA_CONTROL_SE = 8,\n\tDMA_CONTROL_OSF = 4,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tunnel_encap_types {\n\tTUNNEL_ENCAP_NONE = 0,\n\tTUNNEL_ENCAP_FOU = 1,\n\tTUNNEL_ENCAP_GUE = 2,\n\tTUNNEL_ENCAP_MPLS = 3,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum twl4030_module_ids {\n\tTWL4030_MODULE_AUDIO_VOICE = 9,\n\tTWL4030_MODULE_GPIO = 10,\n\tTWL4030_MODULE_INTBR = 11,\n\tTWL4030_MODULE_TEST = 12,\n\tTWL4030_MODULE_KEYPAD = 13,\n\tTWL4030_MODULE_MADC = 14,\n\tTWL4030_MODULE_INTERRUPTS = 15,\n\tTWL4030_MODULE_PRECHARGE = 16,\n\tTWL4030_MODULE_BACKUP = 17,\n\tTWL4030_MODULE_INT = 18,\n\tTWL5031_MODULE_ACCESSORY = 19,\n\tTWL5031_MODULE_INTERRUPTS = 20,\n\tTWL4030_MODULE_LAST = 21,\n};\n\nenum twl6030_module_ids {\n\tTWL6030_MODULE_ID0 = 9,\n\tTWL6030_MODULE_ID1 = 10,\n\tTWL6030_MODULE_ID2 = 11,\n\tTWL6030_MODULE_GPADC = 12,\n\tTWL6030_MODULE_GASGAUGE = 13,\n\tTWL6032_MODULE_CHARGE = 14,\n\tTWL6030_MODULE_LAST = 15,\n};\n\nenum twl_class {\n\tTWL_4030 = 0,\n\tTWL_6030 = 1,\n};\n\nenum twl_module_ids {\n\tTWL_MODULE_USB = 0,\n\tTWL_MODULE_PIH = 1,\n\tTWL_MODULE_MAIN_CHARGE = 2,\n\tTWL_MODULE_PM_MASTER = 3,\n\tTWL_MODULE_PM_RECEIVER = 4,\n\tTWL_MODULE_RTC = 5,\n\tTWL_MODULE_PWM = 6,\n\tTWL_MODULE_LED = 7,\n\tTWL_MODULE_SECURED_REG = 8,\n\tTWL_MODULE_LAST = 9,\n};\n\nenum tx_frame_status {\n\ttx_done___2 = 0,\n\ttx_not_ls = 1,\n\ttx_err = 2,\n\ttx_dma_own = 4,\n\ttx_err_bump_tc = 8,\n};\n\nenum tx_queue_prio {\n\tTX_QUEUE_PRIO_HIGH = 0,\n\tTX_QUEUE_PRIO_LOW = 1,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum uart_iotype {\n\tUPIO_UNKNOWN = -1,\n\tUPIO_PORT = 0,\n\tUPIO_HUB6 = 1,\n\tUPIO_MEM = 2,\n\tUPIO_MEM32 = 3,\n\tUPIO_AU = 4,\n\tUPIO_TSI = 5,\n\tUPIO_MEM32BE = 6,\n\tUPIO_MEM16 = 7,\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_COUNTS = 10,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum ulp_cpu_pwr_mode {\n\tULP_PM_HSRUN = 0,\n\tULP_PM_RUN = 1,\n\tULP_PM_WAIT = 2,\n\tULP_PM_STOP = 3,\n\tULP_PM_VLPS = 4,\n\tULP_PM_VLLS = 5,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum uniphier_clk_type {\n\tUNIPHIER_CLK_TYPE_CPUGEAR = 0,\n\tUNIPHIER_CLK_TYPE_FIXED_FACTOR = 1,\n\tUNIPHIER_CLK_TYPE_FIXED_RATE = 2,\n\tUNIPHIER_CLK_TYPE_GATE = 3,\n\tUNIPHIER_CLK_TYPE_MUX = 4,\n};\n\nenum uniphier_pin_drv_type {\n\tUNIPHIER_PIN_DRV_1BIT = 0,\n\tUNIPHIER_PIN_DRV_2BIT = 1,\n\tUNIPHIER_PIN_DRV_3BIT = 2,\n\tUNIPHIER_PIN_DRV_FIXED4 = 3,\n\tUNIPHIER_PIN_DRV_FIXED5 = 4,\n\tUNIPHIER_PIN_DRV_FIXED8 = 5,\n\tUNIPHIER_PIN_DRV_NONE = 6,\n};\n\nenum uniphier_pin_pull_dir {\n\tUNIPHIER_PIN_PULL_UP = 0,\n\tUNIPHIER_PIN_PULL_DOWN = 1,\n\tUNIPHIER_PIN_PULL_UP_FIXED = 2,\n\tUNIPHIER_PIN_PULL_DOWN_FIXED = 3,\n\tUNIPHIER_PIN_PULL_NONE = 4,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_reason_code {\n\tURC_OK = 0,\n\tURC_CONTINUE_UNWIND = 8,\n\tURC_FAILURE = 9,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nenum usb3503_mode {\n\tUSB3503_MODE_UNKNOWN = 0,\n\tUSB3503_MODE_HUB = 1,\n\tUSB3503_MODE_STANDBY = 2,\n\tUSB3503_MODE_BYPASS = 3,\n};\n\nenum usb3_link_state {\n\tUSB3_LPM_U0 = 0,\n\tUSB3_LPM_U1 = 1,\n\tUSB3_LPM_U2 = 2,\n\tUSB3_LPM_U3 = 3,\n};\n\nenum usb_charger_state {\n\tUSB_CHARGER_DEFAULT = 0,\n\tUSB_CHARGER_PRESENT = 1,\n\tUSB_CHARGER_ABSENT = 2,\n};\n\nenum usb_charger_type {\n\tUNKNOWN_TYPE = 0,\n\tSDP_TYPE = 1,\n\tDCP_TYPE = 2,\n\tCDP_TYPE = 3,\n\tACA_TYPE = 4,\n};\n\nenum usb_dev_authorize_policy {\n\tUSB_DEVICE_AUTHORIZE_NONE = 0,\n\tUSB_DEVICE_AUTHORIZE_ALL = 1,\n\tUSB_DEVICE_AUTHORIZE_INTERNAL = 2,\n};\n\nenum usb_device_speed {\n\tUSB_SPEED_UNKNOWN = 0,\n\tUSB_SPEED_LOW = 1,\n\tUSB_SPEED_FULL = 2,\n\tUSB_SPEED_HIGH = 3,\n\tUSB_SPEED_WIRELESS = 4,\n\tUSB_SPEED_SUPER = 5,\n\tUSB_SPEED_SUPER_PLUS = 6,\n};\n\nenum usb_device_state {\n\tUSB_STATE_NOTATTACHED = 0,\n\tUSB_STATE_ATTACHED = 1,\n\tUSB_STATE_POWERED = 2,\n\tUSB_STATE_RECONNECTING = 3,\n\tUSB_STATE_UNAUTHENTICATED = 4,\n\tUSB_STATE_DEFAULT = 5,\n\tUSB_STATE_ADDRESS = 6,\n\tUSB_STATE_CONFIGURED = 7,\n\tUSB_STATE_SUSPENDED = 8,\n};\n\nenum usb_dr_mode {\n\tUSB_DR_MODE_UNKNOWN = 0,\n\tUSB_DR_MODE_HOST = 1,\n\tUSB_DR_MODE_PERIPHERAL = 2,\n\tUSB_DR_MODE_OTG = 3,\n};\n\nenum usb_interface_condition {\n\tUSB_INTERFACE_UNBOUND = 0,\n\tUSB_INTERFACE_BINDING = 1,\n\tUSB_INTERFACE_BOUND = 2,\n\tUSB_INTERFACE_UNBINDING = 3,\n};\n\nenum usb_led_event {\n\tUSB_LED_EVENT_HOST = 0,\n\tUSB_LED_EVENT_GADGET = 1,\n};\n\nenum usb_link_tunnel_mode {\n\tUSB_LINK_UNKNOWN = 0,\n\tUSB_LINK_NATIVE = 1,\n\tUSB_LINK_TUNNELED = 2,\n};\n\nenum usb_otg_state {\n\tOTG_STATE_UNDEFINED = 0,\n\tOTG_STATE_B_IDLE = 1,\n\tOTG_STATE_B_SRP_INIT = 2,\n\tOTG_STATE_B_PERIPHERAL = 3,\n\tOTG_STATE_B_WAIT_ACON = 4,\n\tOTG_STATE_B_HOST = 5,\n\tOTG_STATE_A_IDLE = 6,\n\tOTG_STATE_A_WAIT_VRISE = 7,\n\tOTG_STATE_A_WAIT_BCON = 8,\n\tOTG_STATE_A_HOST = 9,\n\tOTG_STATE_A_SUSPEND = 10,\n\tOTG_STATE_A_PERIPHERAL = 11,\n\tOTG_STATE_A_WAIT_VFALL = 12,\n\tOTG_STATE_A_VBUS_ERR = 13,\n};\n\nenum usb_phy_events {\n\tUSB_EVENT_NONE = 0,\n\tUSB_EVENT_VBUS = 1,\n\tUSB_EVENT_ID = 2,\n\tUSB_EVENT_CHARGER = 3,\n\tUSB_EVENT_ENUMERATED = 4,\n};\n\nenum usb_phy_interface {\n\tUSBPHY_INTERFACE_MODE_UNKNOWN = 0,\n\tUSBPHY_INTERFACE_MODE_UTMI = 1,\n\tUSBPHY_INTERFACE_MODE_UTMIW = 2,\n\tUSBPHY_INTERFACE_MODE_ULPI = 3,\n\tUSBPHY_INTERFACE_MODE_SERIAL = 4,\n\tUSBPHY_INTERFACE_MODE_HSIC = 5,\n};\n\nenum usb_phy_type {\n\tUSB_PHY_TYPE_UNDEFINED = 0,\n\tUSB_PHY_TYPE_USB2 = 1,\n\tUSB_PHY_TYPE_USB3 = 2,\n};\n\nenum usb_port_connect_type {\n\tUSB_PORT_CONNECT_TYPE_UNKNOWN = 0,\n\tUSB_PORT_CONNECT_TYPE_HOT_PLUG = 1,\n\tUSB_PORT_CONNECT_TYPE_HARD_WIRED = 2,\n\tUSB_PORT_NOT_USED = 3,\n};\n\nenum usb_role {\n\tUSB_ROLE_NONE = 0,\n\tUSB_ROLE_HOST = 1,\n\tUSB_ROLE_DEVICE = 2,\n};\n\nenum usb_ssp_rate {\n\tUSB_SSP_GEN_UNKNOWN = 0,\n\tUSB_SSP_GEN_2x1 = 1,\n\tUSB_SSP_GEN_1x2 = 2,\n\tUSB_SSP_GEN_2x2 = 3,\n};\n\nenum usb_wireless_status {\n\tUSB_WIRELESS_STATUS_NA = 0,\n\tUSB_WIRELESS_STATUS_DISCONNECTED = 1,\n\tUSB_WIRELESS_STATUS_CONNECTED = 2,\n};\n\nenum usbhs_omap_port_mode {\n\tOMAP_USBHS_PORT_MODE_UNUSED = 0,\n\tOMAP_EHCI_PORT_MODE_PHY = 1,\n\tOMAP_EHCI_PORT_MODE_TLL = 2,\n\tOMAP_EHCI_PORT_MODE_HSIC = 3,\n\tOMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0 = 4,\n\tOMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM = 5,\n\tOMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0 = 6,\n\tOMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM = 7,\n\tOMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0 = 8,\n\tOMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM = 9,\n\tOMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0 = 10,\n\tOMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM = 11,\n\tOMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0 = 12,\n\tOMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM = 13,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum ux500_musb_vbus_id_status {\n\tUX500_MUSB_NONE = 0,\n\tUX500_MUSB_VBUS = 1,\n\tUX500_MUSB_ID = 2,\n\tUX500_MUSB_CHARGER = 3,\n\tUX500_MUSB_ENUMERATED = 4,\n\tUX500_MUSB_RIDA = 5,\n\tUX500_MUSB_RIDB = 6,\n\tUX500_MUSB_RIDC = 7,\n\tUX500_MUSB_PREPARE = 8,\n\tUX500_MUSB_CLEAN = 9,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vcap_action_field {\n\tVCAP_AF_NO_VALUE = 0,\n\tVCAP_AF_ACL_ID = 1,\n\tVCAP_AF_CLS_VID_SEL = 2,\n\tVCAP_AF_CNT_ID = 3,\n\tVCAP_AF_COPY_PORT_NUM = 4,\n\tVCAP_AF_COPY_QUEUE_NUM = 5,\n\tVCAP_AF_CPU_COPY_ENA = 6,\n\tVCAP_AF_CPU_QU = 7,\n\tVCAP_AF_CPU_QUEUE_NUM = 8,\n\tVCAP_AF_CUSTOM_ACE_TYPE_ENA = 9,\n\tVCAP_AF_DEI_A_VAL = 10,\n\tVCAP_AF_DEI_B_VAL = 11,\n\tVCAP_AF_DEI_C_VAL = 12,\n\tVCAP_AF_DEI_ENA = 13,\n\tVCAP_AF_DEI_VAL = 14,\n\tVCAP_AF_DLR_SEL = 15,\n\tVCAP_AF_DP_ENA = 16,\n\tVCAP_AF_DP_VAL = 17,\n\tVCAP_AF_DSCP_ENA = 18,\n\tVCAP_AF_DSCP_SEL = 19,\n\tVCAP_AF_DSCP_VAL = 20,\n\tVCAP_AF_ES2_REW_CMD = 21,\n\tVCAP_AF_ESDX = 22,\n\tVCAP_AF_FWD_KILL_ENA = 23,\n\tVCAP_AF_FWD_MODE = 24,\n\tVCAP_AF_FWD_SEL = 25,\n\tVCAP_AF_HIT_ME_ONCE = 26,\n\tVCAP_AF_HOST_MATCH = 27,\n\tVCAP_AF_IGNORE_PIPELINE_CTRL = 28,\n\tVCAP_AF_INTR_ENA = 29,\n\tVCAP_AF_ISDX_ADD_REPLACE_SEL = 30,\n\tVCAP_AF_ISDX_ADD_VAL = 31,\n\tVCAP_AF_ISDX_ENA = 32,\n\tVCAP_AF_ISDX_REPLACE_ENA = 33,\n\tVCAP_AF_ISDX_VAL = 34,\n\tVCAP_AF_LOOP_ENA = 35,\n\tVCAP_AF_LRN_DIS = 36,\n\tVCAP_AF_MAP_IDX = 37,\n\tVCAP_AF_MAP_KEY = 38,\n\tVCAP_AF_MAP_LOOKUP_SEL = 39,\n\tVCAP_AF_MASK_MODE = 40,\n\tVCAP_AF_MATCH_ID = 41,\n\tVCAP_AF_MATCH_ID_MASK = 42,\n\tVCAP_AF_MIRROR_ENA = 43,\n\tVCAP_AF_MIRROR_PROBE = 44,\n\tVCAP_AF_MIRROR_PROBE_ID = 45,\n\tVCAP_AF_MRP_SEL = 46,\n\tVCAP_AF_NXT_IDX = 47,\n\tVCAP_AF_NXT_IDX_CTRL = 48,\n\tVCAP_AF_OAM_SEL = 49,\n\tVCAP_AF_PAG_OVERRIDE_MASK = 50,\n\tVCAP_AF_PAG_VAL = 51,\n\tVCAP_AF_PCP_A_VAL = 52,\n\tVCAP_AF_PCP_B_VAL = 53,\n\tVCAP_AF_PCP_C_VAL = 54,\n\tVCAP_AF_PCP_ENA = 55,\n\tVCAP_AF_PCP_VAL = 56,\n\tVCAP_AF_PIPELINE_ACT = 57,\n\tVCAP_AF_PIPELINE_FORCE_ENA = 58,\n\tVCAP_AF_PIPELINE_PT = 59,\n\tVCAP_AF_POLICE_ENA = 60,\n\tVCAP_AF_POLICE_IDX = 61,\n\tVCAP_AF_POLICE_REMARK = 62,\n\tVCAP_AF_POLICE_VCAP_ONLY = 63,\n\tVCAP_AF_POP_VAL = 64,\n\tVCAP_AF_PORT_MASK = 65,\n\tVCAP_AF_PUSH_CUSTOMER_TAG = 66,\n\tVCAP_AF_PUSH_INNER_TAG = 67,\n\tVCAP_AF_PUSH_OUTER_TAG = 68,\n\tVCAP_AF_QOS_ENA = 69,\n\tVCAP_AF_QOS_VAL = 70,\n\tVCAP_AF_REW_OP = 71,\n\tVCAP_AF_RT_DIS = 72,\n\tVCAP_AF_SFID_ENA = 73,\n\tVCAP_AF_SFID_VAL = 74,\n\tVCAP_AF_SGID_ENA = 75,\n\tVCAP_AF_SGID_VAL = 76,\n\tVCAP_AF_SWAP_MACS_ENA = 77,\n\tVCAP_AF_TAG_A_DEI_SEL = 78,\n\tVCAP_AF_TAG_A_PCP_SEL = 79,\n\tVCAP_AF_TAG_A_TPID_SEL = 80,\n\tVCAP_AF_TAG_A_VID_SEL = 81,\n\tVCAP_AF_TAG_B_DEI_SEL = 82,\n\tVCAP_AF_TAG_B_PCP_SEL = 83,\n\tVCAP_AF_TAG_B_TPID_SEL = 84,\n\tVCAP_AF_TAG_B_VID_SEL = 85,\n\tVCAP_AF_TAG_C_DEI_SEL = 86,\n\tVCAP_AF_TAG_C_PCP_SEL = 87,\n\tVCAP_AF_TAG_C_TPID_SEL = 88,\n\tVCAP_AF_TAG_C_VID_SEL = 89,\n\tVCAP_AF_TYPE = 90,\n\tVCAP_AF_UNTAG_VID_ENA = 91,\n\tVCAP_AF_VID_A_VAL = 92,\n\tVCAP_AF_VID_B_VAL = 93,\n\tVCAP_AF_VID_C_VAL = 94,\n\tVCAP_AF_VID_REPLACE_ENA = 95,\n\tVCAP_AF_VID_VAL = 96,\n\tVCAP_AF_VLAN_POP_CNT = 97,\n\tVCAP_AF_VLAN_POP_CNT_ENA = 98,\n};\n\nenum vcap_actionfield_set {\n\tVCAP_AFS_NO_VALUE = 0,\n\tVCAP_AFS_BASE_TYPE = 1,\n\tVCAP_AFS_CLASSIFICATION = 2,\n\tVCAP_AFS_CLASS_REDUCED = 3,\n\tVCAP_AFS_ES0 = 4,\n\tVCAP_AFS_FULL = 5,\n\tVCAP_AFS_S1 = 6,\n\tVCAP_AFS_SMAC_SIP = 7,\n\tVCAP_AFS_VID = 8,\n};\n\nenum vcap_arp_opcode {\n\tVCAP_ARP_OP_RESERVED = 0,\n\tVCAP_ARP_OP_REQUEST = 1,\n\tVCAP_ARP_OP_REPLY = 2,\n};\n\nenum vcap_bit {\n\tVCAP_BIT_ANY = 0,\n\tVCAP_BIT_0 = 1,\n\tVCAP_BIT_1 = 2,\n};\n\nenum vcap_command {\n\tVCAP_CMD_WRITE = 0,\n\tVCAP_CMD_READ = 1,\n\tVCAP_CMD_MOVE_DOWN = 2,\n\tVCAP_CMD_MOVE_UP = 3,\n\tVCAP_CMD_INITIALIZE = 4,\n};\n\nenum vcap_field_type {\n\tVCAP_FIELD_BIT = 0,\n\tVCAP_FIELD_U32 = 1,\n\tVCAP_FIELD_U48 = 2,\n\tVCAP_FIELD_U56 = 3,\n\tVCAP_FIELD_U64 = 4,\n\tVCAP_FIELD_U72 = 5,\n\tVCAP_FIELD_U112 = 6,\n\tVCAP_FIELD_U128 = 7,\n};\n\nenum vcap_is2_arp_opcode {\n\tVCAP_IS2_ARP_REQUEST = 0,\n\tVCAP_IS2_ARP_REPLY = 1,\n\tVCAP_IS2_RARP_REQUEST = 2,\n\tVCAP_IS2_RARP_REPLY = 3,\n};\n\nenum vcap_key_field {\n\tVCAP_KF_NO_VALUE = 0,\n\tVCAP_KF_8021BR_ECID_BASE = 1,\n\tVCAP_KF_8021BR_ECID_EXT = 2,\n\tVCAP_KF_8021BR_E_TAGGED = 3,\n\tVCAP_KF_8021BR_GRP = 4,\n\tVCAP_KF_8021BR_IGR_ECID_BASE = 5,\n\tVCAP_KF_8021BR_IGR_ECID_EXT = 6,\n\tVCAP_KF_8021CB_R_TAGGED_IS = 7,\n\tVCAP_KF_8021Q_DEI0 = 8,\n\tVCAP_KF_8021Q_DEI1 = 9,\n\tVCAP_KF_8021Q_DEI2 = 10,\n\tVCAP_KF_8021Q_DEI_CLS = 11,\n\tVCAP_KF_8021Q_PCP0 = 12,\n\tVCAP_KF_8021Q_PCP1 = 13,\n\tVCAP_KF_8021Q_PCP2 = 14,\n\tVCAP_KF_8021Q_PCP_CLS = 15,\n\tVCAP_KF_8021Q_TPID = 16,\n\tVCAP_KF_8021Q_TPID0 = 17,\n\tVCAP_KF_8021Q_TPID1 = 18,\n\tVCAP_KF_8021Q_TPID2 = 19,\n\tVCAP_KF_8021Q_VID0 = 20,\n\tVCAP_KF_8021Q_VID1 = 21,\n\tVCAP_KF_8021Q_VID2 = 22,\n\tVCAP_KF_8021Q_VID_CLS = 23,\n\tVCAP_KF_8021Q_VLAN_DBL_TAGGED_IS = 24,\n\tVCAP_KF_8021Q_VLAN_TAGGED_IS = 25,\n\tVCAP_KF_8021Q_VLAN_TAGS = 26,\n\tVCAP_KF_ACL_GRP_ID = 27,\n\tVCAP_KF_ARP_ADDR_SPACE_OK_IS = 28,\n\tVCAP_KF_ARP_LEN_OK_IS = 29,\n\tVCAP_KF_ARP_OPCODE = 30,\n\tVCAP_KF_ARP_OPCODE_UNKNOWN_IS = 31,\n\tVCAP_KF_ARP_PROTO_SPACE_OK_IS = 32,\n\tVCAP_KF_ARP_SENDER_MATCH_IS = 33,\n\tVCAP_KF_ARP_TGT_MATCH_IS = 34,\n\tVCAP_KF_COSID_CLS = 35,\n\tVCAP_KF_ES0_ISDX_KEY_ENA = 36,\n\tVCAP_KF_ETYPE = 37,\n\tVCAP_KF_ETYPE_LEN_IS = 38,\n\tVCAP_KF_HOST_MATCH = 39,\n\tVCAP_KF_IF_EGR_PORT_MASK = 40,\n\tVCAP_KF_IF_EGR_PORT_MASK_RNG = 41,\n\tVCAP_KF_IF_EGR_PORT_NO = 42,\n\tVCAP_KF_IF_IGR_PORT = 43,\n\tVCAP_KF_IF_IGR_PORT_MASK = 44,\n\tVCAP_KF_IF_IGR_PORT_MASK_L3 = 45,\n\tVCAP_KF_IF_IGR_PORT_MASK_RNG = 46,\n\tVCAP_KF_IF_IGR_PORT_MASK_SEL = 47,\n\tVCAP_KF_IF_IGR_PORT_SEL = 48,\n\tVCAP_KF_IP4_IS = 49,\n\tVCAP_KF_IP_MC_IS = 50,\n\tVCAP_KF_IP_PAYLOAD_5TUPLE = 51,\n\tVCAP_KF_IP_PAYLOAD_S1_IP6 = 52,\n\tVCAP_KF_IP_SNAP_IS = 53,\n\tVCAP_KF_ISDX_CLS = 54,\n\tVCAP_KF_ISDX_GT0_IS = 55,\n\tVCAP_KF_L2_BC_IS = 56,\n\tVCAP_KF_L2_DMAC = 57,\n\tVCAP_KF_L2_FRM_TYPE = 58,\n\tVCAP_KF_L2_FWD_IS = 59,\n\tVCAP_KF_L2_LLC = 60,\n\tVCAP_KF_L2_MAC = 61,\n\tVCAP_KF_L2_MC_IS = 62,\n\tVCAP_KF_L2_PAYLOAD0 = 63,\n\tVCAP_KF_L2_PAYLOAD1 = 64,\n\tVCAP_KF_L2_PAYLOAD2 = 65,\n\tVCAP_KF_L2_PAYLOAD_ETYPE = 66,\n\tVCAP_KF_L2_SMAC = 67,\n\tVCAP_KF_L2_SNAP = 68,\n\tVCAP_KF_L3_DIP_EQ_SIP_IS = 69,\n\tVCAP_KF_L3_DPL_CLS = 70,\n\tVCAP_KF_L3_DSCP = 71,\n\tVCAP_KF_L3_DST_IS = 72,\n\tVCAP_KF_L3_FRAGMENT = 73,\n\tVCAP_KF_L3_FRAGMENT_TYPE = 74,\n\tVCAP_KF_L3_FRAG_INVLD_L4_LEN = 75,\n\tVCAP_KF_L3_FRAG_OFS_GT0 = 76,\n\tVCAP_KF_L3_IP4_DIP = 77,\n\tVCAP_KF_L3_IP4_SIP = 78,\n\tVCAP_KF_L3_IP6_DIP = 79,\n\tVCAP_KF_L3_IP6_DIP_MSB = 80,\n\tVCAP_KF_L3_IP6_SIP = 81,\n\tVCAP_KF_L3_IP6_SIP_MSB = 82,\n\tVCAP_KF_L3_IP_PROTO = 83,\n\tVCAP_KF_L3_OPTIONS_IS = 84,\n\tVCAP_KF_L3_PAYLOAD = 85,\n\tVCAP_KF_L3_RT_IS = 86,\n\tVCAP_KF_L3_TOS = 87,\n\tVCAP_KF_L3_TTL_GT0 = 88,\n\tVCAP_KF_L4_1588_DOM = 89,\n\tVCAP_KF_L4_1588_VER = 90,\n\tVCAP_KF_L4_ACK = 91,\n\tVCAP_KF_L4_DPORT = 92,\n\tVCAP_KF_L4_FIN = 93,\n\tVCAP_KF_L4_PAYLOAD = 94,\n\tVCAP_KF_L4_PSH = 95,\n\tVCAP_KF_L4_RNG = 96,\n\tVCAP_KF_L4_RST = 97,\n\tVCAP_KF_L4_SEQUENCE_EQ0_IS = 98,\n\tVCAP_KF_L4_SPORT = 99,\n\tVCAP_KF_L4_SPORT_EQ_DPORT_IS = 100,\n\tVCAP_KF_L4_SYN = 101,\n\tVCAP_KF_L4_URG = 102,\n\tVCAP_KF_LOOKUP_FIRST_IS = 103,\n\tVCAP_KF_LOOKUP_GEN_IDX = 104,\n\tVCAP_KF_LOOKUP_GEN_IDX_SEL = 105,\n\tVCAP_KF_LOOKUP_INDEX = 106,\n\tVCAP_KF_LOOKUP_PAG = 107,\n\tVCAP_KF_MIRROR_PROBE = 108,\n\tVCAP_KF_OAM_CCM_CNTS_EQ0 = 109,\n\tVCAP_KF_OAM_DETECTED = 110,\n\tVCAP_KF_OAM_FLAGS = 111,\n\tVCAP_KF_OAM_MEL_FLAGS = 112,\n\tVCAP_KF_OAM_MEPID = 113,\n\tVCAP_KF_OAM_OPCODE = 114,\n\tVCAP_KF_OAM_VER = 115,\n\tVCAP_KF_OAM_Y1731_IS = 116,\n\tVCAP_KF_PDU_TYPE = 117,\n\tVCAP_KF_PROT_ACTIVE = 118,\n\tVCAP_KF_RTP_ID = 119,\n\tVCAP_KF_RT_FRMID = 120,\n\tVCAP_KF_RT_TYPE = 121,\n\tVCAP_KF_RT_VLAN_IDX = 122,\n\tVCAP_KF_TCP_IS = 123,\n\tVCAP_KF_TCP_UDP_IS = 124,\n\tVCAP_KF_TYPE = 125,\n};\n\nenum vcap_keyfield_set {\n\tVCAP_KFS_NO_VALUE = 0,\n\tVCAP_KFS_5TUPLE_IP4 = 1,\n\tVCAP_KFS_5TUPLE_IP6 = 2,\n\tVCAP_KFS_7TUPLE = 3,\n\tVCAP_KFS_ARP = 4,\n\tVCAP_KFS_DBL_VID = 5,\n\tVCAP_KFS_DMAC_VID = 6,\n\tVCAP_KFS_ETAG = 7,\n\tVCAP_KFS_IP4_OTHER = 8,\n\tVCAP_KFS_IP4_TCP_UDP = 9,\n\tVCAP_KFS_IP4_VID = 10,\n\tVCAP_KFS_IP6_OTHER = 11,\n\tVCAP_KFS_IP6_STD = 12,\n\tVCAP_KFS_IP6_TCP_UDP = 13,\n\tVCAP_KFS_IP6_VID = 14,\n\tVCAP_KFS_IP_7TUPLE = 15,\n\tVCAP_KFS_ISDX = 16,\n\tVCAP_KFS_LL_FULL = 17,\n\tVCAP_KFS_MAC_ETYPE = 18,\n\tVCAP_KFS_MAC_LLC = 19,\n\tVCAP_KFS_MAC_SNAP = 20,\n\tVCAP_KFS_NORMAL = 21,\n\tVCAP_KFS_NORMAL_5TUPLE_IP4 = 22,\n\tVCAP_KFS_NORMAL_7TUPLE = 23,\n\tVCAP_KFS_NORMAL_IP6 = 24,\n\tVCAP_KFS_OAM = 25,\n\tVCAP_KFS_PURE_5TUPLE_IP4 = 26,\n\tVCAP_KFS_RT = 27,\n\tVCAP_KFS_SMAC_SIP4 = 28,\n\tVCAP_KFS_SMAC_SIP6 = 29,\n\tVCAP_KFS_VID = 30,\n};\n\nenum vcap_rule_error {\n\tVCAP_ERR_NONE = 0,\n\tVCAP_ERR_NO_ADMIN = 1,\n\tVCAP_ERR_NO_NETDEV = 2,\n\tVCAP_ERR_NO_KEYSET_MATCH = 3,\n\tVCAP_ERR_NO_ACTIONSET_MATCH = 4,\n\tVCAP_ERR_NO_PORT_KEYSET_MATCH = 5,\n};\n\nenum vcap_rule_state {\n\tVCAP_RS_PERMANENT = 0,\n\tVCAP_RS_ENABLED = 1,\n\tVCAP_RS_DISABLED = 2,\n};\n\nenum vcap_selection {\n\tVCAP_SEL_ENTRY = 1,\n\tVCAP_SEL_ACTION = 2,\n\tVCAP_SEL_COUNTER = 4,\n\tVCAP_SEL_ALL = 255,\n};\n\nenum vcap_type {\n\tVCAP_TYPE_ES0 = 0,\n\tVCAP_TYPE_ES2 = 1,\n\tVCAP_TYPE_IS0 = 2,\n\tVCAP_TYPE_IS1 = 3,\n\tVCAP_TYPE_IS2 = 4,\n\tVCAP_TYPE_MAX = 5,\n};\n\nenum vcap_user {\n\tVCAP_USER_PTP = 0,\n\tVCAP_USER_MRP = 1,\n\tVCAP_USER_CFM = 2,\n\tVCAP_USER_VLAN = 3,\n\tVCAP_USER_QOS = 4,\n\tVCAP_USER_VCAP_UTIL = 5,\n\tVCAP_USER_TC = 6,\n\tVCAP_USER_TC_EXTRA = 7,\n\t__VCAP_USER_AFTER_LAST = 8,\n\tVCAP_USER_MAX = 7,\n};\n\nenum vco_freq_range {\n\tVCO_LOW = 700000000,\n\tVCO_MID = 1200000000,\n\tVCO_HIGH = 2200000000,\n\tVCO_HIGH_HIGH = 3100000000,\n\tVCO_MAX = 4000000000,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_ARCHTIMER = 1,\n\tVDSO_CLOCKMODE_MAX = 2,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum vexpress_reset_func {\n\tFUNC_RESET = 0,\n\tFUNC_SHUTDOWN = 1,\n\tFUNC_REBOOT = 2,\n};\n\nenum vf610_nfc_variant {\n\tNFC_VFC610 = 1,\n};\n\nenum vf610_pads {\n\tVF610_PAD_PTA6 = 0,\n\tVF610_PAD_PTA8 = 1,\n\tVF610_PAD_PTA9 = 2,\n\tVF610_PAD_PTA10 = 3,\n\tVF610_PAD_PTA11 = 4,\n\tVF610_PAD_PTA12 = 5,\n\tVF610_PAD_PTA16 = 6,\n\tVF610_PAD_PTA17 = 7,\n\tVF610_PAD_PTA18 = 8,\n\tVF610_PAD_PTA19 = 9,\n\tVF610_PAD_PTA20 = 10,\n\tVF610_PAD_PTA21 = 11,\n\tVF610_PAD_PTA22 = 12,\n\tVF610_PAD_PTA23 = 13,\n\tVF610_PAD_PTA24 = 14,\n\tVF610_PAD_PTA25 = 15,\n\tVF610_PAD_PTA26 = 16,\n\tVF610_PAD_PTA27 = 17,\n\tVF610_PAD_PTA28 = 18,\n\tVF610_PAD_PTA29 = 19,\n\tVF610_PAD_PTA30 = 20,\n\tVF610_PAD_PTA31 = 21,\n\tVF610_PAD_PTB0 = 22,\n\tVF610_PAD_PTB1 = 23,\n\tVF610_PAD_PTB2 = 24,\n\tVF610_PAD_PTB3 = 25,\n\tVF610_PAD_PTB4 = 26,\n\tVF610_PAD_PTB5 = 27,\n\tVF610_PAD_PTB6 = 28,\n\tVF610_PAD_PTB7 = 29,\n\tVF610_PAD_PTB8 = 30,\n\tVF610_PAD_PTB9 = 31,\n\tVF610_PAD_PTB10 = 32,\n\tVF610_PAD_PTB11 = 33,\n\tVF610_PAD_PTB12 = 34,\n\tVF610_PAD_PTB13 = 35,\n\tVF610_PAD_PTB14 = 36,\n\tVF610_PAD_PTB15 = 37,\n\tVF610_PAD_PTB16 = 38,\n\tVF610_PAD_PTB17 = 39,\n\tVF610_PAD_PTB18 = 40,\n\tVF610_PAD_PTB19 = 41,\n\tVF610_PAD_PTB20 = 42,\n\tVF610_PAD_PTB21 = 43,\n\tVF610_PAD_PTB22 = 44,\n\tVF610_PAD_PTC0 = 45,\n\tVF610_PAD_PTC1 = 46,\n\tVF610_PAD_PTC2 = 47,\n\tVF610_PAD_PTC3 = 48,\n\tVF610_PAD_PTC4 = 49,\n\tVF610_PAD_PTC5 = 50,\n\tVF610_PAD_PTC6 = 51,\n\tVF610_PAD_PTC7 = 52,\n\tVF610_PAD_PTC8 = 53,\n\tVF610_PAD_PTC9 = 54,\n\tVF610_PAD_PTC10 = 55,\n\tVF610_PAD_PTC11 = 56,\n\tVF610_PAD_PTC12 = 57,\n\tVF610_PAD_PTC13 = 58,\n\tVF610_PAD_PTC14 = 59,\n\tVF610_PAD_PTC15 = 60,\n\tVF610_PAD_PTC16 = 61,\n\tVF610_PAD_PTC17 = 62,\n\tVF610_PAD_PTD31 = 63,\n\tVF610_PAD_PTD30 = 64,\n\tVF610_PAD_PTD29 = 65,\n\tVF610_PAD_PTD28 = 66,\n\tVF610_PAD_PTD27 = 67,\n\tVF610_PAD_PTD26 = 68,\n\tVF610_PAD_PTD25 = 69,\n\tVF610_PAD_PTD24 = 70,\n\tVF610_PAD_PTD23 = 71,\n\tVF610_PAD_PTD22 = 72,\n\tVF610_PAD_PTD21 = 73,\n\tVF610_PAD_PTD20 = 74,\n\tVF610_PAD_PTD19 = 75,\n\tVF610_PAD_PTD18 = 76,\n\tVF610_PAD_PTD17 = 77,\n\tVF610_PAD_PTD16 = 78,\n\tVF610_PAD_PTD0 = 79,\n\tVF610_PAD_PTD1 = 80,\n\tVF610_PAD_PTD2 = 81,\n\tVF610_PAD_PTD3 = 82,\n\tVF610_PAD_PTD4 = 83,\n\tVF610_PAD_PTD5 = 84,\n\tVF610_PAD_PTD6 = 85,\n\tVF610_PAD_PTD7 = 86,\n\tVF610_PAD_PTD8 = 87,\n\tVF610_PAD_PTD9 = 88,\n\tVF610_PAD_PTD10 = 89,\n\tVF610_PAD_PTD11 = 90,\n\tVF610_PAD_PTD12 = 91,\n\tVF610_PAD_PTD13 = 92,\n\tVF610_PAD_PTB23 = 93,\n\tVF610_PAD_PTB24 = 94,\n\tVF610_PAD_PTB25 = 95,\n\tVF610_PAD_PTB26 = 96,\n\tVF610_PAD_PTB27 = 97,\n\tVF610_PAD_PTB28 = 98,\n\tVF610_PAD_PTC26 = 99,\n\tVF610_PAD_PTC27 = 100,\n\tVF610_PAD_PTC28 = 101,\n\tVF610_PAD_PTC29 = 102,\n\tVF610_PAD_PTC30 = 103,\n\tVF610_PAD_PTC31 = 104,\n\tVF610_PAD_PTE0 = 105,\n\tVF610_PAD_PTE1 = 106,\n\tVF610_PAD_PTE2 = 107,\n\tVF610_PAD_PTE3 = 108,\n\tVF610_PAD_PTE4 = 109,\n\tVF610_PAD_PTE5 = 110,\n\tVF610_PAD_PTE6 = 111,\n\tVF610_PAD_PTE7 = 112,\n\tVF610_PAD_PTE8 = 113,\n\tVF610_PAD_PTE9 = 114,\n\tVF610_PAD_PTE10 = 115,\n\tVF610_PAD_PTE11 = 116,\n\tVF610_PAD_PTE12 = 117,\n\tVF610_PAD_PTE13 = 118,\n\tVF610_PAD_PTE14 = 119,\n\tVF610_PAD_PTE15 = 120,\n\tVF610_PAD_PTE16 = 121,\n\tVF610_PAD_PTE17 = 122,\n\tVF610_PAD_PTE18 = 123,\n\tVF610_PAD_PTE19 = 124,\n\tVF610_PAD_PTE20 = 125,\n\tVF610_PAD_PTE21 = 126,\n\tVF610_PAD_PTE22 = 127,\n\tVF610_PAD_PTE23 = 128,\n\tVF610_PAD_PTE24 = 129,\n\tVF610_PAD_PTE25 = 130,\n\tVF610_PAD_PTE26 = 131,\n\tVF610_PAD_PTE27 = 132,\n\tVF610_PAD_PTE28 = 133,\n\tVF610_PAD_PTA7 = 134,\n};\n\nenum virtnet_xmit_type {\n\tVIRTNET_XMIT_TYPE_SKB = 0,\n\tVIRTNET_XMIT_TYPE_SKB_ORPHAN = 1,\n\tVIRTNET_XMIT_TYPE_XDP = 2,\n\tVIRTNET_XMIT_TYPE_XSK = 3,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_DMA = 4,\n\tPGALLOC_NORMAL = 5,\n\tPGALLOC_HIGH = 6,\n\tPGALLOC_MOVABLE = 7,\n\tALLOCSTALL_DMA = 8,\n\tALLOCSTALL_NORMAL = 9,\n\tALLOCSTALL_HIGH = 10,\n\tALLOCSTALL_MOVABLE = 11,\n\tPGSCAN_SKIP_DMA = 12,\n\tPGSCAN_SKIP_NORMAL = 13,\n\tPGSCAN_SKIP_HIGH = 14,\n\tPGSCAN_SKIP_MOVABLE = 15,\n\tPGFREE = 16,\n\tPGACTIVATE = 17,\n\tPGDEACTIVATE = 18,\n\tPGLAZYFREE = 19,\n\tPGFAULT = 20,\n\tPGMAJFAULT = 21,\n\tPGLAZYFREED = 22,\n\tPGREFILL = 23,\n\tPGREUSE = 24,\n\tPGSTEAL_KSWAPD = 25,\n\tPGSTEAL_DIRECT = 26,\n\tPGSTEAL_KHUGEPAGED = 27,\n\tPGSTEAL_PROACTIVE = 28,\n\tPGSCAN_KSWAPD = 29,\n\tPGSCAN_DIRECT = 30,\n\tPGSCAN_KHUGEPAGED = 31,\n\tPGSCAN_PROACTIVE = 32,\n\tPGSCAN_DIRECT_THROTTLE = 33,\n\tPGSCAN_ANON = 34,\n\tPGSCAN_FILE = 35,\n\tPGSTEAL_ANON = 36,\n\tPGSTEAL_FILE = 37,\n\tPGINODESTEAL = 38,\n\tSLABS_SCANNED = 39,\n\tKSWAPD_INODESTEAL = 40,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 41,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 42,\n\tPAGEOUTRUN = 43,\n\tPGROTATED = 44,\n\tDROP_PAGECACHE = 45,\n\tDROP_SLAB = 46,\n\tOOM_KILL = 47,\n\tPGMIGRATE_SUCCESS = 48,\n\tPGMIGRATE_FAIL = 49,\n\tTHP_MIGRATION_SUCCESS = 50,\n\tTHP_MIGRATION_FAIL = 51,\n\tTHP_MIGRATION_SPLIT = 52,\n\tCOMPACTMIGRATE_SCANNED = 53,\n\tCOMPACTFREE_SCANNED = 54,\n\tCOMPACTISOLATED = 55,\n\tCOMPACTSTALL = 56,\n\tCOMPACTFAIL = 57,\n\tCOMPACTSUCCESS = 58,\n\tKCOMPACTD_WAKE = 59,\n\tKCOMPACTD_MIGRATE_SCANNED = 60,\n\tKCOMPACTD_FREE_SCANNED = 61,\n\tCMA_ALLOC_SUCCESS = 62,\n\tCMA_ALLOC_FAIL = 63,\n\tUNEVICTABLE_PGCULLED = 64,\n\tUNEVICTABLE_PGSCANNED = 65,\n\tUNEVICTABLE_PGRESCUED = 66,\n\tUNEVICTABLE_PGMLOCKED = 67,\n\tUNEVICTABLE_PGMUNLOCKED = 68,\n\tUNEVICTABLE_PGCLEARED = 69,\n\tUNEVICTABLE_PGSTRANDED = 70,\n\tSWAP_RA = 71,\n\tSWAP_RA_HIT = 72,\n\tSWPIN_ZERO = 73,\n\tSWPOUT_ZERO = 74,\n\tNR_VM_EVENT_ITEMS = 75,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum voltage_change_dir {\n\tNO_CHANGE = 0,\n\tDOWN___3 = 1,\n\tUP___3 = 2,\n};\n\nenum vp_vq_vector_policy {\n\tVP_VQ_VECTOR_POLICY_EACH = 0,\n\tVP_VQ_VECTOR_POLICY_SHARED_SLOW = 1,\n\tVP_VQ_VECTOR_POLICY_SHARED = 2,\n};\n\nenum vq_layout {\n\tVQ_LAYOUT_SPLIT = 0,\n\tVQ_LAYOUT_PACKED = 1,\n\tVQ_LAYOUT_SPLIT_IN_ORDER = 2,\n\tVQ_LAYOUT_PACKED_IN_ORDER = 3,\n};\n\nenum wakeup_type {\n\tAT91_SHDW_WKMODE0_NONE = 0,\n\tAT91_SHDW_WKMODE0_HIGH = 1,\n\tAT91_SHDW_WKMODE0_LOW = 2,\n\tAT91_SHDW_WKMODE0_ANYLEVEL = 3,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum why_no_delegation4 {\n\tWND4_NOT_WANTED = 0,\n\tWND4_CONTENTION = 1,\n\tWND4_RESOURCE = 2,\n\tWND4_NOT_SUPP_FTYPE = 3,\n\tWND4_WRITE_DELEG_NOT_SUPP_FTYPE = 4,\n\tWND4_NOT_SUPP_UPGRADE = 5,\n\tWND4_NOT_SUPP_DOWNGRADE = 6,\n\tWND4_CANCELLED = 7,\n\tWND4_IS_DIR = 8,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 11,\n\tWORK_OFFQ_POOL_BITS = 11,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wp_types {\n\tESDHC_WP_NONE = 0,\n\tESDHC_WP_CONTROLLER = 1,\n\tESDHC_WP_GPIO = 2,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 30000,\n\tMAYDAY_INITIAL_TIMEOUT = 2,\n\tMAYDAY_INTERVAL = 10,\n\tCREATE_COOLDOWN = 100,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 16,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum x509_actions {\n\tACT_x509_extract_key_data = 0,\n\tACT_x509_extract_name_segment = 1,\n\tACT_x509_note_OID = 2,\n\tACT_x509_note_issuer = 3,\n\tACT_x509_note_not_after = 4,\n\tACT_x509_note_not_before = 5,\n\tACT_x509_note_params = 6,\n\tACT_x509_note_serial = 7,\n\tACT_x509_note_sig_algo = 8,\n\tACT_x509_note_signature = 9,\n\tACT_x509_note_subject = 10,\n\tACT_x509_note_tbs_certificate = 11,\n\tACT_x509_process_extension = 12,\n\tNR__x509_actions = 13,\n};\n\nenum x509_akid_actions {\n\tACT_x509_akid_note_kid = 0,\n\tACT_x509_akid_note_name = 1,\n\tACT_x509_akid_note_serial = 2,\n\tACT_x509_extract_name_segment___2 = 3,\n\tACT_x509_note_OID___2 = 4,\n\tNR__x509_akid_actions = 5,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xadc_external_mux_mode {\n\tXADC_EXTERNAL_MUX_NONE = 0,\n\tXADC_EXTERNAL_MUX_SINGLE = 1,\n\tXADC_EXTERNAL_MUX_DUAL = 2,\n};\n\nenum xadc_type {\n\tXADC_TYPE_S7 = 0,\n\tXADC_TYPE_US = 1,\n};\n\nenum xcan_ip_type {\n\tXAXI_CAN = 0,\n\tXZYNQ_CANPS = 1,\n\tXAXI_CANFD = 2,\n\tXAXI_CANFD_2_0 = 3,\n};\n\nenum xcan_reg {\n\tXCAN_SRR_OFFSET = 0,\n\tXCAN_MSR_OFFSET = 4,\n\tXCAN_BRPR_OFFSET = 8,\n\tXCAN_BTR_OFFSET = 12,\n\tXCAN_ECR_OFFSET = 16,\n\tXCAN_ESR_OFFSET = 20,\n\tXCAN_SR_OFFSET = 24,\n\tXCAN_ISR_OFFSET = 28,\n\tXCAN_IER_OFFSET = 32,\n\tXCAN_ICR_OFFSET = 36,\n\tXCAN_TXFIFO_OFFSET = 48,\n\tXCAN_RXFIFO_OFFSET = 80,\n\tXCAN_AFR_OFFSET = 96,\n\tXCAN_F_BRPR_OFFSET = 136,\n\tXCAN_F_BTR_OFFSET = 140,\n\tXCAN_TRR_OFFSET = 144,\n\tXCAN_ECC_CFG_OFFSET = 200,\n\tXCAN_TXTLFIFO_ECC_OFFSET = 204,\n\tXCAN_TXOLFIFO_ECC_OFFSET = 208,\n\tXCAN_RXFIFO_ECC_OFFSET = 212,\n\tXCAN_AFR_EXT_OFFSET = 224,\n\tXCAN_FSR_OFFSET = 232,\n\tXCAN_TXMSG_BASE_OFFSET = 256,\n\tXCAN_RXMSG_BASE_OFFSET = 4352,\n\tXCAN_RXMSG_2_BASE_OFFSET = 8448,\n\tXCAN_AFR_2_MASK_OFFSET = 2560,\n\tXCAN_AFR_2_ID_OFFSET = 2564,\n};\n\nenum xcan_stats_type {\n\tXCAN_ECC_RX_2_BIT_ERRORS = 0,\n\tXCAN_ECC_RX_1_BIT_ERRORS = 1,\n\tXCAN_ECC_TXOL_2_BIT_ERRORS = 2,\n\tXCAN_ECC_TXOL_1_BIT_ERRORS = 3,\n\tXCAN_ECC_TXTL_2_BIT_ERRORS = 4,\n\tXCAN_ECC_TXTL_1_BIT_ERRORS = 5,\n};\n\nenum xdma_ip_type {\n\tXDMA_TYPE_AXIDMA = 0,\n\tXDMA_TYPE_CDMA = 1,\n\tXDMA_TYPE_VDMA = 2,\n\tXDMA_TYPE_AXIMCDMA = 3,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xfer_buf_dir {\n\tTO_XFER_BUF = 0,\n\tFROM_XFER_BUF = 1,\n};\n\nenum xfrm_ae_ftype_t {\n\tXFRM_AE_UNSPEC = 0,\n\tXFRM_AE_RTHR = 1,\n\tXFRM_AE_RVAL = 2,\n\tXFRM_AE_LVAL = 4,\n\tXFRM_AE_ETHR = 8,\n\tXFRM_AE_CR = 16,\n\tXFRM_AE_CE = 32,\n\tXFRM_AE_CU = 64,\n\t__XFRM_AE_MAX = 65,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_nlgroups {\n\tXFRMNLGRP_NONE = 0,\n\tXFRMNLGRP_ACQUIRE = 1,\n\tXFRMNLGRP_EXPIRE = 2,\n\tXFRMNLGRP_SA = 3,\n\tXFRMNLGRP_POLICY = 4,\n\tXFRMNLGRP_AEVENTS = 5,\n\tXFRMNLGRP_REPORT = 6,\n\tXFRMNLGRP_MIGRATE = 7,\n\tXFRMNLGRP_MAPPING = 8,\n\t__XFRMNLGRP_MAX = 9,\n};\n\nenum xfrm_pol_inexact_candidate_type {\n\tXFRM_POL_CAND_BOTH = 0,\n\tXFRM_POL_CAND_SADDR = 1,\n\tXFRM_POL_CAND_DADDR = 2,\n\tXFRM_POL_CAND_ANY = 3,\n\tXFRM_POL_CAND_MAX = 4,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xfrm_sa_dir {\n\tXFRM_SA_DIR_IN = 1,\n\tXFRM_SA_DIR_OUT = 2,\n};\n\nenum xhci_cancelled_td_status {\n\tTD_DIRTY = 0,\n\tTD_HALTED = 1,\n\tTD_CLEARING_CACHE = 2,\n\tTD_CLEARING_CACHE_DEFERRED = 3,\n\tTD_CLEARED = 4,\n};\n\nenum xhci_ep_reset_type {\n\tEP_HARD_RESET = 0,\n\tEP_SOFT_RESET = 1,\n};\n\nenum xhci_overhead_type {\n\tLS_OVERHEAD_TYPE = 0,\n\tFS_OVERHEAD_TYPE = 1,\n\tHS_OVERHEAD_TYPE = 2,\n};\n\nenum xhci_ring_type {\n\tTYPE_CTRL = 0,\n\tTYPE_ISOC = 1,\n\tTYPE_BULK = 2,\n\tTYPE_INTR = 3,\n\tTYPE_STREAM = 4,\n\tTYPE_COMMAND = 5,\n\tTYPE_EVENT = 6,\n};\n\nenum xhci_setup_dev {\n\tSETUP_CONTEXT_ONLY = 0,\n\tSETUP_CONTEXT_ADDRESS = 1,\n};\n\nenum xhci_sideband_notify_type {\n\tXHCI_SIDEBAND_XFER_RING_FREE = 0,\n};\n\nenum xhci_sideband_type {\n\tXHCI_SIDEBAND_AUDIO = 0,\n\tXHCI_SIDEBAND_VENDOR = 1,\n};\n\nenum xiic_endian {\n\tLITTLE = 0,\n\tBIG = 1,\n};\n\nenum xilinx_i2c_state {\n\tSTATE_DONE = 0,\n\tSTATE_ERROR = 1,\n\tSTATE_START___3 = 2,\n};\n\nenum xprt_transports {\n\tXPRT_TRANSPORT_UDP = 17,\n\tXPRT_TRANSPORT_TCP = 6,\n\tXPRT_TRANSPORT_BC_TCP = -2147483642,\n\tXPRT_TRANSPORT_RDMA = 256,\n\tXPRT_TRANSPORT_BC_RDMA = -2147483392,\n\tXPRT_TRANSPORT_LOCAL = 257,\n\tXPRT_TRANSPORT_TCP_TLS = 258,\n};\n\nenum xprt_xid_rb_cmp {\n\tXID_RB_EQUAL = 0,\n\tXID_RB_LEFT = 1,\n\tXID_RB_RIGHT = 2,\n};\n\nenum xprtsec_policies {\n\tRPC_XPRTSEC_NONE = 0,\n\tRPC_XPRTSEC_TLS_ANON = 1,\n\tRPC_XPRTSEC_TLS_X509 = 2,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_FREE_CMA_PAGES = 9,\n\tNR_VM_ZONE_STAT_ITEMS = 10,\n};\n\nenum zone_type {\n\tZONE_DMA = 0,\n\tZONE_NORMAL = 1,\n\tZONE_HIGHMEM = 2,\n\tZONE_MOVABLE = 3,\n\t__MAX_NR_ZONES = 4,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\nenum zynq_clk {\n\tarmpll = 0,\n\tddrpll = 1,\n\tiopll = 2,\n\tcpu_6or4x = 3,\n\tcpu_3or2x = 4,\n\tcpu_2x = 5,\n\tcpu_1x = 6,\n\tddr2x = 7,\n\tddr3x = 8,\n\tdci = 9,\n\tlqspi = 10,\n\tsmc = 11,\n\tpcap = 12,\n\tgem0 = 13,\n\tgem1 = 14,\n\tfclk0 = 15,\n\tfclk1 = 16,\n\tfclk2 = 17,\n\tfclk3 = 18,\n\tcan0 = 19,\n\tcan1 = 20,\n\tsdio0 = 21,\n\tsdio1 = 22,\n\tuart0 = 23,\n\tuart1 = 24,\n\tspi0 = 25,\n\tspi1 = 26,\n\tdma = 27,\n\tusb0_aper = 28,\n\tusb1_aper = 29,\n\tgem0_aper = 30,\n\tgem1_aper = 31,\n\tsdio0_aper = 32,\n\tsdio1_aper = 33,\n\tspi0_aper = 34,\n\tspi1_aper = 35,\n\tcan0_aper = 36,\n\tcan1_aper = 37,\n\ti2c0_aper = 38,\n\ti2c1_aper = 39,\n\tuart0_aper = 40,\n\tuart1_aper = 41,\n\tgpio_aper = 42,\n\tlqspi_aper = 43,\n\tsmc_aper = 44,\n\tswdt = 45,\n\tdbg_trc = 46,\n\tdbg_apb = 47,\n\tclk_max = 48,\n};\n\nenum zynq_io_standards {\n\tzynq_iostd_min = 0,\n\tzynq_iostd_lvcmos18 = 1,\n\tzynq_iostd_lvcmos25 = 2,\n\tzynq_iostd_lvcmos33 = 3,\n\tzynq_iostd_hstl = 4,\n\tzynq_iostd_max = 5,\n};\n\nenum zynq_pinmux_functions {\n\tZYNQ_PMUX_can0 = 0,\n\tZYNQ_PMUX_can1 = 1,\n\tZYNQ_PMUX_ethernet0 = 2,\n\tZYNQ_PMUX_ethernet1 = 3,\n\tZYNQ_PMUX_gpio0 = 4,\n\tZYNQ_PMUX_i2c0 = 5,\n\tZYNQ_PMUX_i2c1 = 6,\n\tZYNQ_PMUX_mdio0 = 7,\n\tZYNQ_PMUX_mdio1 = 8,\n\tZYNQ_PMUX_qspi0 = 9,\n\tZYNQ_PMUX_qspi1 = 10,\n\tZYNQ_PMUX_qspi_fbclk = 11,\n\tZYNQ_PMUX_qspi_cs1 = 12,\n\tZYNQ_PMUX_spi0 = 13,\n\tZYNQ_PMUX_spi1 = 14,\n\tZYNQ_PMUX_spi0_ss = 15,\n\tZYNQ_PMUX_spi1_ss = 16,\n\tZYNQ_PMUX_sdio0 = 17,\n\tZYNQ_PMUX_sdio0_pc = 18,\n\tZYNQ_PMUX_sdio0_cd = 19,\n\tZYNQ_PMUX_sdio0_wp = 20,\n\tZYNQ_PMUX_sdio1 = 21,\n\tZYNQ_PMUX_sdio1_pc = 22,\n\tZYNQ_PMUX_sdio1_cd = 23,\n\tZYNQ_PMUX_sdio1_wp = 24,\n\tZYNQ_PMUX_smc0_nor = 25,\n\tZYNQ_PMUX_smc0_nor_cs1 = 26,\n\tZYNQ_PMUX_smc0_nor_addr25 = 27,\n\tZYNQ_PMUX_smc0_nand = 28,\n\tZYNQ_PMUX_ttc0 = 29,\n\tZYNQ_PMUX_ttc1 = 30,\n\tZYNQ_PMUX_uart0 = 31,\n\tZYNQ_PMUX_uart1 = 32,\n\tZYNQ_PMUX_usb0 = 33,\n\tZYNQ_PMUX_usb1 = 34,\n\tZYNQ_PMUX_swdt0 = 35,\n\tZYNQ_PMUX_MAX_FUNC = 36,\n};\n\ntypedef _Bool bool;\n\ntypedef char __pad_after_uframe[4];\n\ntypedef char __pad_before_uframe[0];\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_daddr_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_ptrdiff_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_ssize_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __s32;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef __s32 s32;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef s32 dma_cookie_t;\n\ntypedef int ext4_grpblk_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef int kprobe_opcode_t;\n\ntypedef int mpi_size_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef int snd_ctl_elem_iface_t;\n\ntypedef int snd_ctl_elem_type_t;\n\ntypedef int snd_pcm_access_t;\n\ntypedef int snd_pcm_format_t;\n\ntypedef int snd_pcm_state_t;\n\ntypedef int snd_pcm_subformat_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef int suspend_state_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef int vma_flag_t;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef long int mpi_limb_signed_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef long int snd_pcm_sframes_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 s64;\n\ntypedef s64 int64_t;\n\ntypedef int64_t S64;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef long long int qsize_t;\n\ntypedef __s64 time64_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef U64 ZSTD_VecMask;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef __u64 __virtio64;\n\ntypedef u64 arm_lpae_iopte;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 clientid4;\n\ntypedef u64 efi_physical_addr_t;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef __be64 fdt64_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef long long unsigned int llu;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 sci_t;\n\ntypedef u64 sector_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef u64 upf_t;\n\ntypedef uint64_t vli_type;\n\ntypedef long unsigned int mpi_limb_t;\n\ntypedef mpi_limb_t UWtype;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int cycles_t;\n\ntypedef long unsigned int efi_status_t;\n\ntypedef long unsigned int elf_greg_t;\n\ntypedef elf_greg_t elf_gregset_t[18];\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int kimage_entry_t;\n\ntypedef mpi_limb_t *mpi_ptr_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int old_sigset_t;\n\ntypedef long unsigned int perf_trace_t[2048];\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int snd_pcm_uframes_t;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int u_long;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulg;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short int mm_id_mapcount_t;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef short unsigned int ush;\n\ntypedef ush Pos;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef __u16 __hc16;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef short unsigned int __kernel_gid_t;\n\ntypedef short unsigned int __kernel_ipc_pid_t;\n\ntypedef short unsigned int __kernel_mode_t;\n\ntypedef short unsigned int __kernel_old_dev_t;\n\ntypedef __kernel_gid_t __kernel_old_gid_t;\n\ntypedef short unsigned int __kernel_uid_t;\n\ntypedef __kernel_uid_t __kernel_old_uid_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef u16 efi_char16_t;\n\ntypedef __kernel_gid16_t gid16_t;\n\ntypedef short unsigned int mm_id_t;\n\ntypedef __kernel_mode_t mode_t;\n\ntypedef __kernel_old_gid_t old_gid_t;\n\ntypedef __kernel_old_uid_t old_uid_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef short unsigned int pipe_index_t;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef u16 u_int16_t;\n\ntypedef short unsigned int u_short;\n\ntypedef u16 ucs2_char_t;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef u16 wchar_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef u8 dscp_t;\n\ntypedef __u8 dvd_challenge[10];\n\ntypedef __u8 dvd_key[5];\n\ntypedef u8 efi_bool_t;\n\ntypedef unsigned char *sk_buff_data_t;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef unsigned char uch;\n\ntypedef __u8 virtio_net_ctrl_ack;\n\ntypedef unsigned int __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef unsigned int __u32;\n\ntypedef __u32 u32;\n\ntypedef u32 CLST;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_CTable;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef size_t HUF_CElt;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef unsigned int IPos;\n\ntypedef unsigned int OM_uint32;\n\ntypedef unsigned int USItype;\n\ntypedef __u32 __be32;\n\ntypedef u32 __compat_uid32_t;\n\ntypedef __u32 __dw;\n\ntypedef __u32 __hc32;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __virtio32;\n\ntypedef __u32 __wsum;\n\ntypedef unsigned int acr_flags_t;\n\ntypedef unsigned int autofs_wqt_t;\n\ntypedef __le32 bitmap_ulong;\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef __u32 can_err_mask_t;\n\ntypedef __u32 canid_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef u32 depot_flags_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef u32 dma_addr_t;\n\ntypedef unsigned int drm_magic_t;\n\ntypedef u32 errseq_t;\n\ntypedef unsigned int ext4_group_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef __be32 fdt32_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef unsigned int ioasid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef unsigned int mmc_pm_flag_t;\n\ntypedef u32 nlink_t;\n\ntypedef u32 note_buf_t[45];\n\ntypedef u32 pci_bus_addr_t;\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef u32 pmdval_t;\n\ntypedef pmdval_t pgd_t[2];\n\ntypedef u32 pteval_t;\n\ntypedef pteval_t pgprot_t;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef u32 phys_addr_t;\n\ntypedef pmdval_t pmd_t;\n\ntypedef u32 probes_opcode_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef pteval_t pte_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u32 rpc_authflavor_t;\n\ntypedef __be32 rpc_fraghdr;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int speed_t;\n\ntypedef u32 sysmmu_iova_t;\n\ntypedef u32 sysmmu_pte_t;\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int tid_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef u32 uprobe_opcode_t;\n\ntypedef unsigned int upstat_t;\n\ntypedef u32 usb_port_location_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitPos;\n\tchar *startPtr;\n\tchar *ptr;\n\tchar *endPtr;\n} BIT_CStream_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tsize_t nbSequences;\n\tsize_t blockSize;\n\tsize_t litSize;\n} BlockSummary;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\ntypedef struct {\n\tsize_t estLitSize;\n\tsize_t estBlockSize;\n} EstimatedBlockSize;\n\ntypedef struct {\n\tunsigned int events[1024];\n\tsize_t nbEvents;\n} Fingerprint;\n\ntypedef struct {\n\tFingerprint pastEvents;\n\tFingerprint newEvents;\n} FPStats;\n\ntypedef struct {\n\tptrdiff_t value;\n\tconst void *stateTable;\n\tconst void *symbolTT;\n\tunsigned int stateLog;\n} FSE_CState_t;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tint deltaFindState;\n\tU32 deltaNbBits;\n} FSE_symbolCompressionTransform;\n\ntypedef struct {\n\tsize_t bitContainer[2];\n\tsize_t bitPos[2];\n\tBYTE *startPtr;\n\tBYTE *ptr;\n\tBYTE *endPtr;\n} HUF_CStream_t;\n\ntypedef struct {\n\tBYTE tableLog;\n\tBYTE maxSymbolValue;\n\tBYTE unused[2];\n} HUF_CTableHeader;\n\ntypedef struct {\n\tFSE_CTable CTable[59];\n\tU32 scratchBuffer[41];\n\tunsigned int count[13];\n\tS16 norm[13];\n} HUF_CompressWeightsWksp;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n\tlong: 32;\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\ntypedef struct {\n\tHUF_CompressWeightsWksp wksp;\n\tBYTE bitsToWeight[13];\n\tBYTE huffWeight[255];\n} HUF_WriteCTableWksp;\n\nstruct nodeElt_s {\n\tU32 count;\n\tU16 parent;\n\tBYTE byte;\n\tBYTE nbBits;\n};\n\ntypedef struct nodeElt_s nodeElt;\n\ntypedef nodeElt huffNodeTable[512];\n\ntypedef struct {\n\tU16 base;\n\tU16 curr;\n} rankPos;\n\ntypedef struct {\n\thuffNodeTable huffNodeTbl;\n\trankPos rankPosition[192];\n} HUF_buildCTable_wksp_tables;\n\ntypedef struct {\n\tunsigned int count[256];\n\tHUF_CElt CTable[257];\n\tunion {\n\t\tHUF_buildCTable_wksp_tables buildCTable_wksp;\n\t\tHUF_WriteCTableWksp writeCTable_wksp;\n\t\tU32 hist_wksp[1024];\n\t} wksps;\n} HUF_compress_tables_t;\n\nstruct buffer_head;\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\ntypedef struct {\n\tU32 offset;\n\tU32 litLength;\n\tU32 matchLength;\n} rawSeq;\n\ntypedef struct {\n\trawSeq *seq;\n\tsize_t pos;\n\tsize_t posInSequence;\n\tsize_t size;\n\tsize_t capacity;\n} RawSeqStore_t;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\ntypedef struct {\n\tunsigned int offset;\n\tunsigned int litLength;\n\tunsigned int matchLength;\n\tunsigned int rep;\n} ZSTD_Sequence;\n\ntypedef struct {\n\tint collectSequences;\n\tZSTD_Sequence *seqStart;\n\tsize_t seqIndex;\n\tsize_t maxSequences;\n} SeqCollector;\n\nstruct SeqDef_s;\n\ntypedef struct SeqDef_s SeqDef;\n\ntypedef struct {\n\tSeqDef *sequencesStart;\n\tSeqDef *sequences;\n\tBYTE *litStart;\n\tBYTE *lit;\n\tBYTE *llCode;\n\tBYTE *mlCode;\n\tBYTE *ofCode;\n\tsize_t maxNbSeq;\n\tsize_t maxNbLit;\n\tZSTD_longLengthType_e longLengthType;\n\tU32 longLengthPos;\n} SeqStore_t;\n\ntypedef struct {\n\tS16 norm[53];\n\tU32 wksp[285];\n} ZSTD_BuildCTableWksp;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n\tlong: 32;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tU32 litLength;\n\tU32 matchLength;\n} ZSTD_SequenceLength;\n\ntypedef struct {\n\tU32 idx;\n\tU32 posInSequence;\n\tsize_t posInSrc;\n} ZSTD_SequencePosition;\n\ntypedef struct {\n\tSymbolEncodingType_e hType;\n\tBYTE hufDesBuffer[128];\n\tsize_t hufDesSize;\n} ZSTD_hufCTablesMetadata_t;\n\ntypedef struct {\n\tSymbolEncodingType_e llType;\n\tSymbolEncodingType_e ofType;\n\tSymbolEncodingType_e mlType;\n\tBYTE fseTablesBuffer[133];\n\tsize_t fseTablesSize;\n\tsize_t lastCountSize;\n} ZSTD_fseCTablesMetadata_t;\n\ntypedef struct {\n\tZSTD_hufCTablesMetadata_t hufMetadata;\n\tZSTD_fseCTablesMetadata_t fseMetadata;\n} ZSTD_entropyCTablesMetadata_t;\n\ntypedef struct {\n\tSeqStore_t fullSeqStoreChunk;\n\tSeqStore_t firstHalfSeqStore;\n\tSeqStore_t secondHalfSeqStore;\n\tSeqStore_t currSeqStore;\n\tSeqStore_t nextSeqStore;\n\tU32 partitions[196];\n\tZSTD_entropyCTablesMetadata_t entropyMetadata;\n} ZSTD_blockSplitCtx;\n\ntypedef struct {\n\tHUF_CElt CTable[257];\n\tHUF_repeat repeatMode;\n} ZSTD_hufCTables_t;\n\ntypedef struct {\n\tFSE_CTable offcodeCTable[193];\n\tFSE_CTable matchlengthCTable[363];\n\tFSE_CTable litlengthCTable[329];\n\tFSE_repeat offcode_repeatMode;\n\tFSE_repeat matchlength_repeatMode;\n\tFSE_repeat litlength_repeatMode;\n} ZSTD_fseCTables_t;\n\ntypedef struct {\n\tZSTD_hufCTables_t huf;\n\tZSTD_fseCTables_t fse;\n} ZSTD_entropyCTables_t;\n\ntypedef struct {\n\tZSTD_entropyCTables_t entropy;\n\tU32 rep[3];\n} ZSTD_compressedBlockState_t;\n\ntypedef struct {\n\tconst BYTE *nextSrc;\n\tconst BYTE *base;\n\tconst BYTE *dictBase;\n\tU32 dictLimit;\n\tU32 lowLimit;\n\tU32 nbOverflowCorrections;\n} ZSTD_window_t;\n\ntypedef struct {\n\tU32 off;\n\tU32 len;\n} ZSTD_match_t;\n\ntypedef struct {\n\tint price;\n\tU32 off;\n\tU32 mlen;\n\tU32 litlen;\n\tU32 rep[3];\n} ZSTD_optimal_t;\n\ntypedef struct {\n\tunsigned int *litFreq;\n\tunsigned int *litLengthFreq;\n\tunsigned int *matchLengthFreq;\n\tunsigned int *offCodeFreq;\n\tZSTD_match_t *matchTable;\n\tZSTD_optimal_t *priceTable;\n\tU32 litSum;\n\tU32 litLengthSum;\n\tU32 matchLengthSum;\n\tU32 offCodeSum;\n\tU32 litSumBasePrice;\n\tU32 litLengthSumBasePrice;\n\tU32 matchLengthSumBasePrice;\n\tU32 offCodeSumBasePrice;\n\tZSTD_OptPrice_e priceType;\n\tconst ZSTD_entropyCTables_t *symbolCosts;\n\tZSTD_ParamSwitch_e literalCompressionMode;\n} optState_t;\n\ntypedef struct {\n\tunsigned int windowLog;\n\tunsigned int chainLog;\n\tunsigned int hashLog;\n\tunsigned int searchLog;\n\tunsigned int minMatch;\n\tunsigned int targetLength;\n\tZSTD_strategy strategy;\n} ZSTD_compressionParameters;\n\nstruct ZSTD_MatchState_t;\n\ntypedef struct ZSTD_MatchState_t ZSTD_MatchState_t;\n\nstruct ZSTD_MatchState_t {\n\tZSTD_window_t window;\n\tU32 loadedDictEnd;\n\tU32 nextToUpdate;\n\tU32 hashLog3;\n\tU32 rowHashLog;\n\tBYTE *tagTable;\n\tU32 hashCache[8];\n\tlong: 32;\n\tU64 hashSalt;\n\tU32 hashSaltEntropy;\n\tU32 *hashTable;\n\tU32 *hashTable3;\n\tU32 *chainTable;\n\tint forceNonContiguous;\n\tint dedicatedDictSearch;\n\toptState_t opt;\n\tconst ZSTD_MatchState_t *dictMatchState;\n\tZSTD_compressionParameters cParams;\n\tconst RawSeqStore_t *ldmSeqStore;\n\tint prefetchCDictTables;\n\tint lazySkipping;\n};\n\ntypedef struct {\n\tZSTD_compressedBlockState_t *prevCBlock;\n\tZSTD_compressedBlockState_t *nextCBlock;\n\tZSTD_MatchState_t matchState;\n} ZSTD_blockState_t;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef struct {\n\tU32 f1c;\n\tU32 f1d;\n\tU32 f7b;\n\tU32 f7c;\n} ZSTD_cpuid_t;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tvoid *workspace;\n\tvoid *workspaceEnd;\n\tvoid *objectEnd;\n\tvoid *tableEnd;\n\tvoid *tableValidEnd;\n\tvoid *allocStart;\n\tvoid *initOnceStart;\n\tBYTE allocFailed;\n\tint workspaceOversizedDuration;\n\tZSTD_cwksp_alloc_phase_e phase;\n\tZSTD_cwksp_static_alloc_e isStatic;\n} ZSTD_cwksp;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tint contentSizeFlag;\n\tint checksumFlag;\n\tint noDictIDFlag;\n} ZSTD_frameParameters;\n\ntypedef struct {\n\tlong long unsigned int ingested;\n\tlong long unsigned int consumed;\n\tlong long unsigned int produced;\n\tlong long unsigned int flushed;\n\tunsigned int currentJobID;\n\tunsigned int nbActiveWorkers;\n} ZSTD_frameProgression;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\nstruct ZSTD_CDict_s;\n\ntypedef struct ZSTD_CDict_s ZSTD_CDict;\n\ntypedef struct {\n\tvoid *dictBuffer;\n\tconst void *dict;\n\tsize_t dictSize;\n\tZSTD_dictContentType_e dictContentType;\n\tZSTD_CDict *cdict;\n} ZSTD_localDict;\n\ntypedef struct {\n\tRawSeqStore_t seqStore;\n\tU32 startPosInBlock;\n\tU32 endPosInBlock;\n\tU32 offset;\n} ZSTD_optLdm_t;\n\ntypedef struct {\n\tZSTD_compressionParameters cParams;\n\tZSTD_frameParameters fParams;\n} ZSTD_parameters;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tU32 LLtype;\n\tU32 Offtype;\n\tU32 MLtype;\n\tsize_t size;\n\tsize_t lastCountSize;\n\tint longOffsets;\n} ZSTD_symbolEncodingTypeStats_t;\n\ntypedef struct {\n\tlong unsigned int fds_bits[32];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\tu32 lock;\n} arch_rwlock_t;\n\nstruct __raw_tickets {\n\tu16 owner;\n\tu16 next;\n};\n\ntypedef struct {\n\tunion {\n\t\tu32 slock;\n\t\tstruct __raw_tickets tickets;\n\t};\n} arch_spinlock_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\ntypedef atomic_t atomic_long_t;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\ntypedef struct {\n\tint *lock;\n} class_disable_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\nstruct gpio_generic_chip;\n\ntypedef struct {\n\tstruct gpio_generic_chip *lock;\n\tlong unsigned int flags;\n} class_gpio_generic_lock_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ksimd_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_notrace_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\nstruct srcu_ctr;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tstruct srcu_ctr *scp;\n} class_srcu_fast_notrace_t;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\nstruct uart_port;\n\ntypedef struct {\n\tstruct uart_port *lock;\n\tlong unsigned int flags;\n} class_uart_port_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_write_lock_irqsave_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef struct {\n\t__be16 disc_information_length;\n\t__u8 disc_status: 2;\n\t__u8 border_status: 2;\n\t__u8 erasable: 1;\n\t__u8 reserved1: 3;\n\t__u8 n_first_track;\n\t__u8 n_sessions_lsb;\n\t__u8 first_track_lsb;\n\t__u8 last_track_lsb;\n\t__u8 mrw_status: 2;\n\t__u8 dbit: 1;\n\t__u8 reserved2: 2;\n\t__u8 uru: 1;\n\t__u8 dbc_v: 1;\n\t__u8 did_v: 1;\n\t__u8 disc_type;\n\t__u8 n_sessions_msb;\n\t__u8 first_track_msb;\n\t__u8 last_track_msb;\n\t__u32 disc_id;\n\t__u32 lead_in;\n\t__u32 lead_out;\n\t__u8 disc_bar_code[8];\n\t__u8 reserved3;\n\t__u8 n_opc;\n} disc_information;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\nstruct dvd_lu_send_agid {\n\t__u8 type;\n\tunsigned int agid: 2;\n};\n\nstruct dvd_host_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_send_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key key;\n};\n\nstruct dvd_lu_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_lu_send_title_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key title_key;\n\tint lba;\n\tunsigned int cpm: 1;\n\tunsigned int cp_sec: 1;\n\tunsigned int cgms: 2;\n};\n\nstruct dvd_lu_send_asf {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tunsigned int asf: 1;\n};\n\nstruct dvd_host_send_rpcstate {\n\t__u8 type;\n\t__u8 pdrc;\n};\n\nstruct dvd_lu_send_rpcstate {\n\t__u8 type: 2;\n\t__u8 vra: 3;\n\t__u8 ucca: 3;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_lu_send_agid lsa;\n\tstruct dvd_host_send_challenge hsc;\n\tstruct dvd_send_key lsk;\n\tstruct dvd_lu_send_challenge lsc;\n\tstruct dvd_send_key hsk;\n\tstruct dvd_lu_send_title_key lstk;\n\tstruct dvd_lu_send_asf lsasf;\n\tstruct dvd_host_send_rpcstate hrpcs;\n\tstruct dvd_lu_send_rpcstate lrpcs;\n} dvd_authinfo;\n\nstruct dvd_layer {\n\t__u8 book_version: 4;\n\t__u8 book_type: 4;\n\t__u8 min_rate: 4;\n\t__u8 disc_size: 4;\n\t__u8 layer_type: 4;\n\t__u8 track_path: 1;\n\t__u8 nlayers: 2;\n\tchar: 1;\n\t__u8 track_density: 4;\n\t__u8 linear_density: 4;\n\t__u8 bca: 1;\n\t__u32 start_sector;\n\t__u32 end_sector;\n\t__u32 end_sector_l0;\n};\n\nstruct dvd_physical {\n\t__u8 type;\n\t__u8 layer_num;\n\tstruct dvd_layer layer[4];\n};\n\nstruct dvd_copyright {\n\t__u8 type;\n\t__u8 layer_num;\n\t__u8 cpst;\n\t__u8 rmi;\n};\n\nstruct dvd_disckey {\n\t__u8 type;\n\tunsigned int agid: 2;\n\t__u8 value[2048];\n};\n\nstruct dvd_bca {\n\t__u8 type;\n\tint len;\n\t__u8 value[188];\n};\n\nstruct dvd_manufact {\n\t__u8 type;\n\t__u8 layer_num;\n\tint len;\n\t__u8 value[2048];\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_physical physical;\n\tstruct dvd_copyright copyright;\n\tstruct dvd_disckey disckey;\n\tstruct dvd_bca bca;\n\tstruct dvd_manufact manufact;\n} dvd_struct;\n\ntypedef struct {\n\tu64 length;\n\tu64 data;\n} efi_capsule_block_desc_t;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 headersize;\n\tu32 flags;\n\tu32 imagesize;\n} efi_capsule_header_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 table;\n} efi_config_table_32_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu64 table;\n} efi_config_table_64_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_guid_t guid;\n\t\tvoid *table;\n\t};\n\tefi_config_table_32_t mixed_mode;\n} efi_config_table_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tlong unsigned int *ptr;\n\tconst char name[16];\n} efi_config_table_type_t;\n\ntypedef struct {\n\tu32 type;\n\tu32 pad;\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu64 num_pages;\n\tu64 attribute;\n} efi_memory_desc_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 num_entries;\n\tu32 desc_size;\n\tu32 flags;\n\tefi_memory_desc_t entry[0];\n} efi_memory_attributes_table_t;\n\ntypedef struct {\n\tu16 version;\n\tu16 length;\n\tu32 runtime_services_supported;\n} efi_rt_properties_table_t;\n\ntypedef struct {\n\tu64 signature;\n\tu32 revision;\n\tu32 headersize;\n\tu32 crc32;\n\tu32 reserved;\n} efi_table_hdr_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 get_time;\n\tu32 set_time;\n\tu32 get_wakeup_time;\n\tu32 set_wakeup_time;\n\tu32 set_virtual_address_map;\n\tu32 convert_pointer;\n\tu32 get_variable;\n\tu32 get_next_variable;\n\tu32 set_variable;\n\tu32 get_next_high_mono_count;\n\tu32 reset_system;\n\tu32 update_capsule;\n\tu32 query_capsule_caps;\n\tu32 query_variable_info;\n} efi_runtime_services_32_t;\n\ntypedef struct {\n\tu16 year;\n\tu8 month;\n\tu8 day;\n\tu8 hour;\n\tu8 minute;\n\tu8 second;\n\tu8 pad1;\n\tu32 nanosecond;\n\ts16 timezone;\n\tu8 daylight;\n\tu8 pad2;\n} efi_time_t;\n\ntypedef struct {\n\tu32 resolution;\n\tu32 accuracy;\n\tu8 sets_to_zero;\n} efi_time_cap_t;\n\ntypedef efi_status_t efi_get_time_t(efi_time_t *, efi_time_cap_t *);\n\ntypedef efi_status_t efi_set_time_t(efi_time_t *);\n\ntypedef efi_status_t efi_get_wakeup_time_t(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\ntypedef efi_status_t efi_set_wakeup_time_t(efi_bool_t, efi_time_t *);\n\ntypedef efi_status_t efi_set_virtual_address_map_t(long unsigned int, long unsigned int, u32, efi_memory_desc_t *);\n\ntypedef efi_status_t efi_get_variable_t(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\ntypedef efi_status_t efi_get_next_variable_t(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\ntypedef efi_status_t efi_set_variable_t(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\ntypedef efi_status_t efi_get_next_high_mono_count_t(u32 *);\n\ntypedef void efi_reset_system_t(int, efi_status_t, long unsigned int, efi_char16_t *);\n\ntypedef efi_status_t efi_update_capsule_t(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\ntypedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\ntypedef efi_status_t efi_query_variable_info_t(u32, u64 *, u64 *, u64 *);\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tefi_get_time_t *get_time;\n\t\tefi_set_time_t *set_time;\n\t\tefi_get_wakeup_time_t *get_wakeup_time;\n\t\tefi_set_wakeup_time_t *set_wakeup_time;\n\t\tefi_set_virtual_address_map_t *set_virtual_address_map;\n\t\tvoid *convert_pointer;\n\t\tefi_get_variable_t *get_variable;\n\t\tefi_get_next_variable_t *get_next_variable;\n\t\tefi_set_variable_t *set_variable;\n\t\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\t\tefi_reset_system_t *reset_system;\n\t\tefi_update_capsule_t *update_capsule;\n\t\tefi_query_capsule_caps_t *query_capsule_caps;\n\t\tefi_query_variable_info_t *query_variable_info;\n\t};\n\tefi_runtime_services_32_t mixed_mode;\n} efi_runtime_services_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 fw_vendor;\n\tu32 fw_revision;\n\tu32 con_in_handle;\n\tu32 con_in;\n\tu32 con_out_handle;\n\tu32 con_out;\n\tu32 stderr_handle;\n\tu32 stderr;\n\tu32 runtime;\n\tu32 boottime;\n\tu32 nr_tables;\n\tu32 tables;\n} efi_system_table_32_t;\n\nunion efi_simple_text_input_protocol;\n\ntypedef union efi_simple_text_input_protocol efi_simple_text_input_protocol_t;\n\nunion efi_simple_text_output_protocol;\n\ntypedef union efi_simple_text_output_protocol efi_simple_text_output_protocol_t;\n\nunion efi_boot_services;\n\ntypedef union efi_boot_services efi_boot_services_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tlong unsigned int fw_vendor;\n\t\tu32 fw_revision;\n\t\tlong unsigned int con_in_handle;\n\t\tefi_simple_text_input_protocol_t *con_in;\n\t\tlong unsigned int con_out_handle;\n\t\tefi_simple_text_output_protocol_t *con_out;\n\t\tlong unsigned int stderr_handle;\n\t\tlong unsigned int stderr;\n\t\tefi_runtime_services_t *runtime;\n\t\tefi_boot_services_t *boottime;\n\t\tlong unsigned int nr_tables;\n\t\tlong unsigned int tables;\n\t};\n\tefi_system_table_32_t mixed_mode;\n} efi_system_table_t;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tunsigned int __softirq_pending;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n} irq_cpustat_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\tU32 offset;\n\tU32 checksum;\n} ldmEntry_t;\n\ntypedef struct {\n\tconst BYTE *split;\n\tU32 hash;\n\tU32 checksum;\n\tldmEntry_t *bucket;\n} ldmMatchCandidate_t;\n\ntypedef struct {\n\tZSTD_ParamSwitch_e enableLdm;\n\tU32 hashLog;\n\tU32 bucketSizeLog;\n\tU32 minMatchLength;\n\tU32 hashRateLog;\n\tU32 windowLog;\n} ldmParams_t;\n\ntypedef struct {\n\tU64 rolling;\n\tU64 stopMask;\n} ldmRollingHashState_t;\n\ntypedef struct {\n\tZSTD_window_t window;\n\tldmEntry_t *hashTable;\n\tU32 loadedDictEnd;\n\tBYTE *bucketOffsets;\n\tsize_t splitIndices[64];\n\tldmMatchCandidate_t matchCandidates[64];\n} ldmState_t;\n\ntypedef struct {\n\tatomic64_t a;\n} local64_t;\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef union {\n\tlong unsigned int x[1];\n} map_word;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\ntypedef struct {\n\tatomic64_t id;\n\tatomic_t vmalloc_seq;\n\tlong unsigned int sigpage;\n\tlong unsigned int vdso;\n\tlong: 32;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[2];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tchar data[8];\n} nfs4_verifier;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\ntypedef struct {\n\tpgd_t pgd;\n} p4d_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tp4d_t p4d;\n} pud_t;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\t__u16 report_key_length;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 ucca: 3;\n\t__u8 vra: 3;\n\t__u8 type_code: 2;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n\t__u8 reserved3;\n} rpc_state_t;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tU32 *splitLocations;\n\tsize_t idx;\n} seqStoreSplits;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[2];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\t__be16 track_information_length;\n\t__u8 track_lsb;\n\t__u8 session_lsb;\n\t__u8 reserved1;\n\t__u8 track_mode: 4;\n\t__u8 copy: 1;\n\t__u8 damage: 1;\n\t__u8 reserved2: 2;\n\t__u8 data_mode: 4;\n\t__u8 fp: 1;\n\t__u8 packet: 1;\n\t__u8 blank: 1;\n\t__u8 rt: 1;\n\t__u8 nwa_v: 1;\n\t__u8 lra_v: 1;\n\t__u8 reserved3: 6;\n\t__be32 track_start;\n\t__be32 next_writable;\n\t__be32 free_blocks;\n\t__be32 fixed_packet_size;\n\t__be32 track_size;\n\t__be32 last_rec_address;\n} track_information;\n\ntypedef struct {\n\tint data;\n\tint audio;\n\tint cdi;\n\tint xa;\n\tlong int error;\n} tracktype;\n\ntypedef struct {\n\tu64 v;\n} u64_stats_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_compressionParameters zstd_compression_parameters;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\ntypedef ZSTD_parameters zstd_parameters;\n\ntypedef ZSTD_Sequence zstd_sequence;\n\nstruct ACE_HEADER {\n\tu8 AceType;\n\tu8 AceFlags;\n\t__le16 AceSize;\n};\n\nstruct ACL {\n\tu8 AclRevision;\n\tu8 Sbz1;\n\t__le16 AclSize;\n\t__le16 AceCount;\n\t__le16 Sbz2;\n};\n\nstruct ATTR_RESIDENT {\n\t__le32 data_size;\n\t__le16 data_off;\n\tu8 flags;\n\tu8 res;\n};\n\nstruct ATTR_NONRESIDENT {\n\t__le64 svcn;\n\t__le64 evcn;\n\t__le16 run_off;\n\tu8 c_unit;\n\tu8 res1[5];\n\t__le64 alloc_size;\n\t__le64 data_size;\n\t__le64 valid_size;\n\t__le64 total_size;\n};\n\nstruct ATTRIB {\n\tenum ATTR_TYPE type;\n\t__le32 size;\n\tu8 non_res;\n\tu8 name_len;\n\t__le16 name_off;\n\t__le16 flags;\n\t__le16 id;\n\tunion {\n\t\tstruct ATTR_RESIDENT res;\n\t\tstruct ATTR_NONRESIDENT nres;\n\t};\n};\n\nstruct ATTR_DEF_ENTRY {\n\t__le16 name[64];\n\tenum ATTR_TYPE type;\n\t__le32 res;\n\tenum COLLATION_RULE rule;\n\t__le32 flags;\n\t__le64 min_sz;\n\t__le64 max_sz;\n};\n\nstruct MFT_REF {\n\t__le32 low;\n\t__le16 high;\n\t__le16 seq;\n};\n\nstruct NTFS_DUP_INFO {\n\t__le64 cr_time;\n\t__le64 m_time;\n\t__le64 c_time;\n\t__le64 a_time;\n\t__le64 alloc_size;\n\t__le64 data_size;\n\tenum FILE_ATTRIBUTE fa;\n\t__le32 extend_data;\n};\n\nstruct ATTR_FILE_NAME {\n\tstruct MFT_REF home;\n\tstruct NTFS_DUP_INFO dup;\n\tu8 name_len;\n\tu8 type;\n\t__le16 name[0];\n\tlong: 32;\n};\n\nstruct ATTR_LIST_ENTRY {\n\tenum ATTR_TYPE type;\n\t__le16 size;\n\tu8 name_len;\n\tu8 name_off;\n\t__le64 vcn;\n\tstruct MFT_REF ref;\n\t__le16 id;\n\t__le16 name[0];\n\tlong: 32;\n};\n\nstruct ATTR_NAME_ENTRY {\n\t__le16 off;\n\t__le16 name_bytes;\n\t__le16 name[0];\n};\n\nstruct ATTR_STD_INFO {\n\t__le64 cr_time;\n\t__le64 m_time;\n\t__le64 c_time;\n\t__le64 a_time;\n\tenum FILE_ATTRIBUTE fa;\n\t__le32 max_ver_num;\n\t__le32 ver_num;\n\t__le32 class_id;\n};\n\nstruct ATTR_STD_INFO5 {\n\t__le64 cr_time;\n\t__le64 m_time;\n\t__le64 c_time;\n\t__le64 a_time;\n\tenum FILE_ATTRIBUTE fa;\n\t__le32 max_ver_num;\n\t__le32 ver_num;\n\t__le32 class_id;\n\t__le32 owner_id;\n\t__le32 security_id;\n\t__le64 quota_charge;\n\t__le64 usn;\n};\n\nstruct BITMAP_RANGE {\n\t__le32 bitmap_off;\n\t__le32 bits;\n};\n\nstruct CLIENT_ID {\n\t__le16 seq_num;\n\t__le16 client_idx;\n};\n\nstruct CLIENT_REC {\n\t__le64 oldest_lsn;\n\t__le64 restart_lsn;\n\t__le16 prev_client;\n\t__le16 next_client;\n\t__le16 seq_num;\n\tu8 align[6];\n\t__le32 name_bytes;\n\t__le16 name[32];\n};\n\nstruct DIR_PAGE_ENTRY {\n\t__le32 next;\n\t__le32 target_attr;\n\t__le32 transfer_len;\n\t__le32 lcns_follow;\n\t__le64 vcn;\n\t__le64 oldest_lsn;\n\t__le64 page_lcns[0];\n};\n\nstruct DIR_PAGE_ENTRY_32 {\n\t__le32 next;\n\t__le32 target_attr;\n\t__le32 transfer_len;\n\t__le32 lcns_follow;\n\t__le32 reserved;\n\t__le32 vcn_low;\n\t__le32 vcn_hi;\n\t__le32 oldest_lsn_low;\n\t__le32 oldest_lsn_hi;\n\t__le32 page_lcns_low;\n\t__le32 page_lcns_hi;\n};\n\nstruct EA_FULL {\n\t__le32 size;\n\tu8 flags;\n\tu8 name_len;\n\t__le16 elength;\n\tu8 name[0];\n};\n\nstruct EA_INFO {\n\t__le16 size_pack;\n\t__le16 count;\n\t__le32 size;\n};\n\nstruct GUID {\n\t__le32 Data1;\n\t__le16 Data2;\n\t__le16 Data3;\n\tu8 Data4[8];\n};\n\nstruct NTFS_RECORD_HEADER {\n\tenum NTFS_SIGNATURE sign;\n\t__le16 fix_off;\n\t__le16 fix_num;\n\t__le64 lsn;\n};\n\nstruct INDEX_HDR {\n\t__le32 de_off;\n\t__le32 used;\n\t__le32 total;\n\t__le32 flags;\n};\n\nstruct INDEX_BUFFER {\n\tstruct NTFS_RECORD_HEADER rhdr;\n\t__le64 vbn;\n\tstruct INDEX_HDR ihdr;\n};\n\nstruct INDEX_NAMES {\n\tconst __le16 *name;\n\tu8 name_len;\n};\n\nstruct INDEX_ROOT {\n\tenum ATTR_TYPE type;\n\tenum COLLATION_RULE rule;\n\t__le32 index_block_size;\n\tu8 index_block_clst;\n\tu8 res[3];\n\tstruct INDEX_HDR ihdr;\n};\n\nstruct JS_DATA_TYPE {\n\t__s32 buttons;\n\t__s32 x;\n\t__s32 y;\n};\n\nstruct JS_DATA_SAVE_TYPE_32 {\n\t__s32 JS_TIMEOUT;\n\t__s32 BUSY;\n\t__s32 JS_EXPIRETIME;\n\t__s32 JS_TIMELIMIT;\n\tstruct JS_DATA_TYPE JS_SAVE;\n\tstruct JS_DATA_TYPE JS_CORR;\n};\n\nstruct LCN_RANGE {\n\t__le64 lcn;\n\t__le64 len;\n};\n\nstruct LFS_RECORD {\n\t__le16 next_record_off;\n\tu8 align[6];\n\t__le64 last_end_lsn;\n};\n\nstruct LFS_RECORD_HDR {\n\t__le64 this_lsn;\n\t__le64 client_prev_lsn;\n\t__le64 client_undo_next_lsn;\n\t__le32 client_data_len;\n\tstruct CLIENT_ID client;\n\t__le32 record_type;\n\t__le32 transact_id;\n\t__le16 flags;\n\tu8 align[6];\n};\n\nstruct LOG_REC_HDR {\n\t__le16 redo_op;\n\t__le16 undo_op;\n\t__le16 redo_off;\n\t__le16 redo_len;\n\t__le16 undo_off;\n\t__le16 undo_len;\n\t__le16 target_attr;\n\t__le16 lcns_follow;\n\t__le16 record_off;\n\t__le16 attr_off;\n\t__le16 cluster_off;\n\t__le16 reserved;\n\t__le64 target_vcn;\n\t__le64 page_lcns[0];\n};\n\nstruct MFT_REC {\n\tstruct NTFS_RECORD_HEADER rhdr;\n\t__le16 seq;\n\t__le16 hard_links;\n\t__le16 attr_off;\n\t__le16 flags;\n\t__le32 used;\n\t__le32 total;\n\tstruct MFT_REF parent_ref;\n\t__le16 next_attr_id;\n\t__le16 res;\n\t__le32 mft_record;\n\t__le16 fixups[0];\n};\n\nstruct NEW_ATTRIBUTE_SIZES {\n\t__le64 alloc_size;\n\t__le64 valid_size;\n\t__le64 data_size;\n\t__le64 total_size;\n};\n\nstruct NTFS_BOOT {\n\tu8 jump_code[3];\n\tu8 system_id[8];\n\tu8 bytes_per_sector[2];\n\tu8 sectors_per_clusters;\n\tu8 unused1[7];\n\tu8 media_type;\n\tu8 unused2[2];\n\t__le16 sct_per_track;\n\t__le16 heads;\n\t__le32 hidden_sectors;\n\tu8 unused3[4];\n\tu8 bios_drive_num;\n\tu8 unused4;\n\tu8 signature_ex;\n\tu8 unused5;\n\t__le64 sectors_per_volume;\n\t__le64 mft_clst;\n\t__le64 mft2_clst;\n\ts8 record_size;\n\tu8 unused6[3];\n\ts8 index_size;\n\tu8 unused7[3];\n\t__le64 serial_num;\n\t__le32 check_sum;\n\tu8 boot_code[426];\n\tu8 boot_magic[2];\n};\n\nstruct NTFS_DE {\n\tunion {\n\t\tstruct MFT_REF ref;\n\t\tstruct {\n\t\t\t__le16 data_off;\n\t\t\t__le16 data_size;\n\t\t\t__le32 res;\n\t\t} view;\n\t};\n\t__le16 size;\n\t__le16 key_size;\n\t__le16 flags;\n\t__le16 res;\n};\n\nstruct REPARSE_KEY {\n\t__le32 ReparseTag;\n\tstruct MFT_REF ref;\n};\n\nstruct NTFS_DE_R {\n\tstruct NTFS_DE de;\n\tstruct REPARSE_KEY key;\n\tu32 zero;\n};\n\nstruct SECURITY_KEY {\n\t__le32 hash;\n\t__le32 sec_id;\n};\n\nstruct SECURITY_HDR {\n\tstruct SECURITY_KEY key;\n\t__le64 off;\n\t__le32 size;\n};\n\nstruct NTFS_DE_SDH {\n\tstruct NTFS_DE de;\n\tstruct SECURITY_KEY key;\n\tstruct SECURITY_HDR sec_hdr;\n\t__le16 magic[2];\n};\n\nstruct NTFS_DE_SII {\n\tstruct NTFS_DE de;\n\t__le32 sec_id;\n\tstruct SECURITY_HDR sec_hdr;\n};\n\nstruct NTFS_RESTART {\n\t__le32 major_ver;\n\t__le32 minor_ver;\n\t__le64 check_point_start;\n\t__le64 open_attr_table_lsn;\n\t__le64 attr_names_lsn;\n\t__le64 dirty_pages_table_lsn;\n\t__le64 transact_table_lsn;\n\t__le32 open_attr_len;\n\t__le32 attr_names_len;\n\t__le32 dirty_pages_len;\n\t__le32 transact_table_len;\n};\n\nstruct OPEN_ATTR_ENRTY {\n\t__le32 next;\n\t__le32 bytes_per_index;\n\tenum ATTR_TYPE type;\n\tu8 is_dirty_pages;\n\tu8 is_attr_name;\n\tu8 name_len;\n\tu8 res;\n\tstruct MFT_REF ref;\n\t__le64 open_record_lsn;\n\tvoid *ptr;\n\tlong: 32;\n};\n\nstruct OPEN_ATTR_ENRTY_32 {\n\t__le32 next;\n\t__le32 ptr;\n\tstruct MFT_REF ref;\n\t__le64 open_record_lsn;\n\tu8 is_dirty_pages;\n\tu8 is_attr_name;\n\tu8 res1[2];\n\tenum ATTR_TYPE type;\n\tu8 name_len;\n\tu8 res2[3];\n\t__le32 AttributeName;\n\t__le32 bytes_per_index;\n\tlong: 32;\n};\n\nstruct ntfs_run;\n\nstruct runs_tree {\n\tstruct ntfs_run *runs;\n\tsize_t count;\n\tsize_t allocated;\n};\n\nstruct ntfs_inode;\n\nstruct OpenAttr {\n\tstruct ATTRIB *attr;\n\tstruct runs_tree *run1;\n\tstruct runs_tree run0;\n\tstruct ntfs_inode *ni;\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {\n\tseqcount_t seq;\n};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lock_class_key {};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong int privdata[0];\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct RECORD_PAGE_HDR {\n\tstruct NTFS_RECORD_HEADER rhdr;\n\t__le32 rflags;\n\t__le16 page_count;\n\t__le16 page_pos;\n\tstruct LFS_RECORD record_hdr;\n\t__le16 fixups[10];\n\t__le32 file_off;\n};\n\nstruct REPARSE_DATA_BUFFER {\n\t__le32 ReparseTag;\n\t__le16 ReparseDataLength;\n\t__le16 Reserved;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 SubstituteNameOffset;\n\t\t\t__le16 SubstituteNameLength;\n\t\t\t__le16 PrintNameOffset;\n\t\t\t__le16 PrintNameLength;\n\t\t\t__le16 PathBuffer[0];\n\t\t} MountPointReparseBuffer;\n\t\tstruct {\n\t\t\t__le16 SubstituteNameOffset;\n\t\t\t__le16 SubstituteNameLength;\n\t\t\t__le16 PrintNameOffset;\n\t\t\t__le16 PrintNameLength;\n\t\t\t__le32 Flags;\n\t\t\t__le16 PathBuffer[0];\n\t\t} SymbolicLinkReparseBuffer;\n\t\tstruct {\n\t\t\t__le32 WofVersion;\n\t\t\t__le32 WofProvider;\n\t\t\t__le32 ProviderVer;\n\t\t\t__le32 CompressionFormat;\n\t\t} CompressReparseBuffer;\n\t\tstruct {\n\t\t\tu8 DataBuffer[1];\n\t\t} GenericReparseBuffer;\n\t};\n};\n\nstruct REPARSE_POINT {\n\t__le32 ReparseTag;\n\t__le16 ReparseDataLength;\n\t__le16 Reserved;\n\tstruct GUID Guid;\n};\n\nstruct RESTART_AREA {\n\t__le64 current_lsn;\n\t__le16 log_clients;\n\t__le16 client_idx[2];\n\t__le16 flags;\n\t__le32 seq_num_bits;\n\t__le16 ra_len;\n\t__le16 client_off;\n\t__le64 l_size;\n\t__le32 last_lsn_data_len;\n\t__le16 rec_hdr_len;\n\t__le16 data_off;\n\t__le32 open_log_count;\n\t__le32 align[5];\n\tstruct CLIENT_REC clients[0];\n};\n\nstruct RESTART_HDR {\n\tstruct NTFS_RECORD_HEADER rhdr;\n\t__le32 sys_page_size;\n\t__le32 page_size;\n\t__le16 ra_off;\n\t__le16 minor_ver;\n\t__le16 major_ver;\n\t__le16 fixups[0];\n};\n\nstruct RESTART_TABLE {\n\t__le16 size;\n\t__le16 used;\n\t__le16 total;\n\t__le16 res[3];\n\t__le32 free_goal;\n\t__le32 first_free;\n\t__le32 last_free;\n};\n\nstruct RxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\nstruct SECURITY_DESCRIPTOR_RELATIVE {\n\tu8 Revision;\n\tu8 Sbz1;\n\t__le16 Control;\n\t__le32 Owner;\n\t__le32 Group;\n\t__le32 Sacl;\n\t__le32 Dacl;\n};\n\nstruct SID {\n\tu8 Revision;\n\tu8 SubAuthorityCount;\n\tu8 IdentifierAuthority[6];\n\t__le32 SubAuthority[0];\n};\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct lockdep_map {};\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tlong: 32;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n\tlong: 32;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool work_in_progress;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tbool smart_suspend: 1;\n\tbool must_resume: 1;\n\tbool may_skip_resume: 1;\n\tbool out_band_wakeup: 1;\n\tbool strict_midlayer: 1;\n\tstruct hrtimer suspend_timer;\n\tu64 timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tbool idle_notification: 1;\n\tbool request_pending: 1;\n\tbool deferred_resume: 1;\n\tbool needs_force_resume: 1;\n\tbool runtime_auto: 1;\n\tbool ignore_children: 1;\n\tbool no_callbacks: 1;\n\tbool irq_safe: 1;\n\tbool use_autosuspend: 1;\n\tbool timer_autosuspends: 1;\n\tbool memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tenum rpm_status last_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tlong: 32;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct dma_iommu_mapping;\n\nstruct dev_archdata {\n\tstruct dma_iommu_mapping *mapping;\n\tunsigned int dma_ops_setup: 1;\n};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct dev_pin_info;\n\nstruct dma_map_ops;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct dma_coherent_mem;\n\nstruct cma;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tlong: 32;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct dev_pin_info *pins;\n\tstruct dev_msi_info msi;\n\tconst struct dma_map_ops *dma_ops;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct dma_coherent_mem *dma_mem;\n\tstruct cma *cma_area;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_coherent: 1;\n\tbool dma_skip_sync: 1;\n\tlong: 32;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct SeqDef_s {\n\tU32 offBase;\n\tU16 litLength;\n\tU16 mlBase;\n};\n\nstruct TRANSACTION_ENTRY {\n\t__le32 next;\n\tu8 transact_state;\n\tu8 reserved[3];\n\t__le64 first_lsn;\n\t__le64 prev_lsn;\n\t__le64 undo_next_lsn;\n\t__le32 undo_records;\n\t__le32 undo_len;\n};\n\nstruct TxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\nstruct VOLUME_INFO {\n\t__le64 res1;\n\tu8 major_ver;\n\tu8 minor_ver;\n\t__le16 flags;\n\tlong: 32;\n};\n\ntypedef size_t (*ZSTD_sequenceProducer_F)(void *, ZSTD_Sequence *, size_t, const void *, size_t, const void *, size_t, int, size_t);\n\nstruct ZSTD_CCtx_params_s {\n\tZSTD_format_e format;\n\tZSTD_compressionParameters cParams;\n\tZSTD_frameParameters fParams;\n\tint compressionLevel;\n\tint forceWindow;\n\tsize_t targetCBlockSize;\n\tint srcSizeHint;\n\tZSTD_dictAttachPref_e attachDictPref;\n\tZSTD_ParamSwitch_e literalCompressionMode;\n\tint nbWorkers;\n\tsize_t jobSize;\n\tint overlapLog;\n\tint rsyncable;\n\tldmParams_t ldmParams;\n\tint enableDedicatedDictSearch;\n\tZSTD_bufferMode_e inBufferMode;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_SequenceFormat_e blockDelimiters;\n\tint validateSequences;\n\tZSTD_ParamSwitch_e postBlockSplitter;\n\tint preBlockSplitter_level;\n\tsize_t maxBlockSize;\n\tZSTD_ParamSwitch_e useRowMatchFinder;\n\tint deterministicRefPrefix;\n\tZSTD_customMem customMem;\n\tZSTD_ParamSwitch_e prefetchCDictTables;\n\tint enableMatchFinderFallback;\n\tvoid *extSeqProdState;\n\tZSTD_sequenceProducer_F extSeqProdFunc;\n\tZSTD_ParamSwitch_e searchForExternalRepcodes;\n};\n\ntypedef struct ZSTD_CCtx_params_s ZSTD_CCtx_params;\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n\tlong: 32;\n};\n\nstruct POOL_ctx_s;\n\ntypedef struct POOL_ctx_s ZSTD_threadPool;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\nstruct ZSTD_prefixDict_s {\n\tconst void *dict;\n\tsize_t dictSize;\n\tZSTD_dictContentType_e dictContentType;\n};\n\ntypedef struct ZSTD_prefixDict_s ZSTD_prefixDict;\n\nstruct ZSTD_CCtx_s {\n\tZSTD_compressionStage_e stage;\n\tint cParamsChanged;\n\tint bmi2;\n\tZSTD_CCtx_params requestedParams;\n\tZSTD_CCtx_params appliedParams;\n\tZSTD_CCtx_params simpleApiParams;\n\tU32 dictID;\n\tsize_t dictContentSize;\n\tZSTD_cwksp workspace;\n\tsize_t blockSizeMax;\n\tlong long unsigned int pledgedSrcSizePlusOne;\n\tlong long unsigned int consumedSrcSize;\n\tlong long unsigned int producedCSize;\n\tstruct xxh64_state xxhState;\n\tZSTD_customMem customMem;\n\tZSTD_threadPool *pool;\n\tsize_t staticSize;\n\tSeqCollector seqCollector;\n\tint isFirstBlock;\n\tint initialized;\n\tSeqStore_t seqStore;\n\tldmState_t ldmState;\n\trawSeq *ldmSequences;\n\tsize_t maxNbLdmSequences;\n\tRawSeqStore_t externSeqStore;\n\tZSTD_blockState_t blockState;\n\tvoid *tmpWorkspace;\n\tsize_t tmpWkspSize;\n\tZSTD_buffered_policy_e bufferedPolicy;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inToCompress;\n\tsize_t inBuffPos;\n\tsize_t inBuffTarget;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outBuffContentSize;\n\tsize_t outBuffFlushedSize;\n\tZSTD_cStreamStage streamStage;\n\tU32 frameEnded;\n\tZSTD_inBuffer expectedInBuffer;\n\tsize_t stableIn_notConsumed;\n\tsize_t expectedOutBufferSize;\n\tZSTD_localDict localDict;\n\tconst ZSTD_CDict *cdict;\n\tZSTD_prefixDict prefixDict;\n\tZSTD_blockSplitCtx blockSplitCtx;\n\tZSTD_Sequence *extSeqBuf;\n\tsize_t extSeqBufCapacity;\n};\n\ntypedef struct ZSTD_CCtx_s ZSTD_CCtx;\n\ntypedef ZSTD_CCtx ZSTD_CStream;\n\ntypedef ZSTD_CCtx zstd_cctx;\n\ntypedef ZSTD_CStream zstd_cstream;\n\nstruct ZSTD_CDict_s {\n\tconst void *dictContent;\n\tsize_t dictContentSize;\n\tZSTD_dictContentType_e dictContentType;\n\tU32 *entropyWorkspace;\n\tZSTD_cwksp workspace;\n\tlong: 32;\n\tZSTD_MatchState_t matchState;\n\tZSTD_compressedBlockState_t cBlockState;\n\tZSTD_customMem customMem;\n\tU32 dictID;\n\tint compressionLevel;\n\tZSTD_ParamSwitch_e useRowMatchFinder;\n\tlong: 32;\n};\n\ntypedef ZSTD_CDict zstd_cdict;\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct idr;\n\nstruct __class_idr {\n\tstruct idr *idr;\n\tint id;\n};\n\ntypedef struct __class_idr class_idr_alloc_t;\n\nstruct drm_colorop;\n\nstruct drm_colorop_state;\n\nstruct __drm_colorops_state {\n\tstruct drm_colorop *ptr;\n\tstruct drm_colorop_state *state;\n\tstruct drm_colorop_state *old_state;\n\tstruct drm_colorop_state *new_state;\n};\n\nstruct drm_connector;\n\nstruct drm_connector_state;\n\nstruct __drm_connnectors_state {\n\tstruct drm_connector *ptr;\n\tstruct drm_connector_state *state_to_destroy;\n\tstruct drm_connector_state *old_state;\n\tstruct drm_connector_state *new_state;\n\ts32 *out_fence_ptr;\n};\n\nstruct drm_crtc;\n\nstruct drm_crtc_state;\n\nstruct drm_crtc_commit;\n\nstruct __drm_crtcs_state {\n\tstruct drm_crtc *ptr;\n\tstruct drm_crtc_state *state_to_destroy;\n\tstruct drm_crtc_state *old_state;\n\tstruct drm_crtc_state *new_state;\n\tstruct drm_crtc_commit *commit;\n\ts32 *out_fence_ptr;\n\tu64 last_vblank_count;\n};\n\nstruct drm_plane;\n\nstruct drm_plane_state;\n\nstruct __drm_planes_state {\n\tstruct drm_plane *ptr;\n\tstruct drm_plane_state *state_to_destroy;\n\tstruct drm_plane_state *old_state;\n\tstruct drm_plane_state *new_state;\n};\n\nstruct drm_private_obj;\n\nstruct drm_private_state;\n\nstruct __drm_private_objs_state {\n\tstruct drm_private_obj *ptr;\n\tstruct drm_private_state *state_to_destroy;\n\tstruct drm_private_state *old_state;\n\tstruct drm_private_state *new_state;\n};\n\nstruct __extcon_info {\n\tunsigned int type;\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct __fat_dirent {\n\tlong int d_ino;\n\t__kernel_off_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[256];\n};\n\nstruct __fb_timings {\n\tu32 dclk;\n\tu32 hfreq;\n\tu32 vfreq;\n\tu32 hactive;\n\tu32 vactive;\n\tu32 hblank;\n\tu32 vblank;\n\tu32 htotal;\n\tu32 vtotal;\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct pmu;\n\nstruct cgroup;\n\nstruct __group_key {\n\tint cpu;\n\tstruct pmu *pmu;\n\tstruct cgroup *cgroup;\n};\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __ip6_tnl_parm {\n\tchar name[16];\n\tint link;\n\t__u8 proto;\n\t__u8 encap_limit;\n\t__u8 hop_limit;\n\tbool collect_md;\n\t__be32 flowinfo;\n\t__u32 flags;\n\tstruct in6_addr laddr;\n\tstruct in6_addr raddr;\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\t__u32 fwmark;\n\t__u32 index;\n\t__u8 erspan_ver;\n\t__u8 dir;\n\t__u16 hwid;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong: 32;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong: 32;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong: 32;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct net_device;\n\nstruct __rt6_probe_work {\n\tstruct work_struct work;\n\tstruct in6_addr target;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n};\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct dentry;\n\nstruct __track_dentry_update_args {\n\tstruct dentry *dentry;\n\tint op;\n};\n\nstruct __track_range_args {\n\text4_lblk_t start;\n\text4_lblk_t end;\n};\n\nstruct inode;\n\nstruct __uprobe_key {\n\tstruct inode *inode;\n\tlong: 32;\n\tloff_t offset;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct __va_list {\n\tvoid *__ap;\n};\n\ntypedef struct __va_list va_list;\n\nstruct _arg_GO {\n\tu8 chan;\n\tu32 addr;\n\tunsigned int ns;\n};\n\nstruct _arg_LPEND {\n\tenum pl330_cond cond;\n\tbool forever;\n\tunsigned int loop;\n\tu8 bjump;\n};\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nstruct _ccu_mult {\n\tlong unsigned int mult;\n\tlong unsigned int min;\n\tlong unsigned int max;\n};\n\nstruct _ccu_nk {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n};\n\nstruct _ccu_nkm {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n};\n\nstruct _ccu_nkmp {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n\tlong unsigned int p;\n\tlong unsigned int min_p;\n\tlong unsigned int max_p;\n};\n\nstruct _ccu_nm {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n};\n\nstruct _ddebug {\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n\tconst char *format;\n\tunsigned int lineno: 18;\n\tunsigned int class_id: 6;\n\tunsigned int flags: 8;\n\tlong: 32;\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _gpiochip_for_each_data {\n\tconst char **label;\n\tunsigned int *i;\n};\n\ntypedef struct _gpiochip_for_each_data class__gpiochip_for_each_data_t;\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n};\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct dma_pl330_desc;\n\nstruct _pl330_req {\n\tu32 mc_bus;\n\tvoid *mc_cpu;\n\tstruct dma_pl330_desc *desc;\n};\n\nstruct _pl330_tbd {\n\tbool reset_dmac;\n\tbool reset_mngr;\n\tu8 reset_chan;\n};\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct _xfer_spec {\n\tu32 ccr;\n\tstruct dma_pl330_desc *desc;\n};\n\nstruct ab8500 {\n\tstruct device *dev;\n\tstruct mutex lock;\n\tstruct mutex irq_lock;\n\tatomic_t transfer_ongoing;\n\tint irq;\n\tstruct irq_domain *domain;\n\tenum ab8500_version version;\n\tu8 chip_id;\n\tint (*write)(struct ab8500 *, u16, u8);\n\tint (*write_masked)(struct ab8500 *, u16, u8, u8);\n\tint (*read)(struct ab8500 *, u16);\n\tlong unsigned int tx_buf[4];\n\tlong unsigned int rx_buf[4];\n\tu8 *mask;\n\tu8 *oldmask;\n\tint mask_size;\n\tconst int *irq_reg_offset;\n\tint it_latchhier_num;\n};\n\nstruct ab8500_adc_cal_data {\n\ts64 gain;\n\ts64 offset;\n\tu16 otp_calib_hi;\n\tu16 otp_calib_lo;\n\tlong: 32;\n};\n\nstruct ab8500_ext_regulator_cfg {\n\tbool hwreq;\n};\n\nstruct regulator_config;\n\nstruct regulator_dev;\n\nstruct regulator_ops;\n\nstruct linear_range;\n\nstruct regulator_desc {\n\tconst char *name;\n\tconst char *supply_name;\n\tconst char *of_match;\n\tbool of_match_full_name;\n\tconst char *regulators_node;\n\tint (*of_parse_cb)(struct device_node *, const struct regulator_desc *, struct regulator_config *);\n\tint (*init_cb)(struct regulator_dev *, struct regulator_config *);\n\tint id;\n\tunsigned int continuous_voltage_range: 1;\n\tunsigned int n_voltages;\n\tunsigned int n_current_limits;\n\tconst struct regulator_ops *ops;\n\tint irq;\n\tenum regulator_type type;\n\tstruct module *owner;\n\tunsigned int min_uV;\n\tunsigned int uV_step;\n\tunsigned int linear_min_sel;\n\tint fixed_uV;\n\tunsigned int ramp_delay;\n\tint min_dropout_uV;\n\tconst struct linear_range *linear_ranges;\n\tconst unsigned int *linear_range_selectors_bitfield;\n\tint n_linear_ranges;\n\tconst unsigned int *volt_table;\n\tconst unsigned int *curr_table;\n\tunsigned int vsel_range_reg;\n\tunsigned int vsel_range_mask;\n\tbool range_applied_by_vsel;\n\tunsigned int vsel_reg;\n\tunsigned int vsel_mask;\n\tunsigned int vsel_step;\n\tunsigned int csel_reg;\n\tunsigned int csel_mask;\n\tunsigned int apply_reg;\n\tunsigned int apply_bit;\n\tunsigned int enable_reg;\n\tunsigned int enable_mask;\n\tunsigned int enable_val;\n\tunsigned int disable_val;\n\tbool enable_is_inverted;\n\tunsigned int bypass_reg;\n\tunsigned int bypass_mask;\n\tunsigned int bypass_val_on;\n\tunsigned int bypass_val_off;\n\tunsigned int active_discharge_on;\n\tunsigned int active_discharge_off;\n\tunsigned int active_discharge_mask;\n\tunsigned int active_discharge_reg;\n\tunsigned int soft_start_reg;\n\tunsigned int soft_start_mask;\n\tunsigned int soft_start_val_on;\n\tunsigned int pull_down_reg;\n\tunsigned int pull_down_mask;\n\tunsigned int pull_down_val_on;\n\tunsigned int ramp_reg;\n\tunsigned int ramp_mask;\n\tconst unsigned int *ramp_delay_table;\n\tunsigned int n_ramp_values;\n\tunsigned int enable_time;\n\tunsigned int off_on_delay;\n\tunsigned int poll_enabled_time;\n\tunsigned int (*of_map_mode)(unsigned int);\n};\n\nstruct ab8500_ext_regulator_info {\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct ab8500_ext_regulator_cfg *cfg;\n\tu8 update_bank;\n\tu8 update_reg;\n\tu8 update_mask;\n\tu8 update_val;\n\tu8 update_val_hp;\n\tu8 update_val_lp;\n\tu8 update_val_hw;\n};\n\nstruct ab8500_gpadc_chan_info;\n\nstruct regulator;\n\nstruct ab8500_gpadc {\n\tstruct device *dev;\n\tstruct ab8500 *ab8500;\n\tstruct ab8500_gpadc_chan_info *chans;\n\tunsigned int nchans;\n\tstruct completion complete;\n\tstruct regulator *vddadc;\n\tint irq_sw;\n\tint irq_hw;\n\tlong: 32;\n\tstruct ab8500_adc_cal_data cal_data[4];\n};\n\nstruct ab8500_gpadc_chan_info {\n\tconst char *name;\n\tu8 id;\n\tbool hardware_control;\n\tbool falling_edge;\n\tu8 avg_sample;\n\tu8 trig_timer;\n};\n\nstruct ab8500_reg_init {\n\tu8 bank;\n\tu8 addr;\n\tu8 mask;\n};\n\nstruct ab8500_shared_mode;\n\nstruct ab8500_regulator_info {\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct ab8500_shared_mode *shared_mode;\n\tint load_lp_uA;\n\tu8 update_bank;\n\tu8 update_reg;\n\tu8 update_mask;\n\tu8 update_val;\n\tu8 update_val_idle;\n\tu8 update_val_normal;\n\tu8 mode_bank;\n\tu8 mode_reg;\n\tu8 mode_mask;\n\tu8 mode_val_idle;\n\tu8 mode_val_normal;\n\tu8 voltage_bank;\n\tu8 voltage_reg;\n\tu8 voltage_mask;\n};\n\nstruct ab8500_shared_mode {\n\tstruct ab8500_regulator_info *shared_regulator;\n\tbool lp_mode_req;\n};\n\nstruct notifier_block;\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct usb_charger_current {\n\tunsigned int sdp_min;\n\tunsigned int sdp_max;\n\tunsigned int dcp_min;\n\tunsigned int dcp_max;\n\tunsigned int cdp_min;\n\tunsigned int cdp_max;\n\tunsigned int aca_min;\n\tunsigned int aca_max;\n};\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct usb_otg;\n\nstruct usb_phy_io_ops;\n\nstruct extcon_dev;\n\nstruct usb_phy {\n\tstruct device *dev;\n\tconst char *label;\n\tunsigned int flags;\n\tenum usb_phy_type type;\n\tenum usb_phy_events last_event;\n\tstruct usb_otg *otg;\n\tstruct device *io_dev;\n\tstruct usb_phy_io_ops *io_ops;\n\tvoid *io_priv;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *id_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct notifier_block type_nb;\n\tenum usb_charger_type chg_type;\n\tenum usb_charger_state chg_state;\n\tstruct usb_charger_current chg_cur;\n\tstruct work_struct chg_work;\n\tstruct atomic_notifier_head notifier;\n\tu16 port_status;\n\tu16 port_change;\n\tstruct list_head head;\n\tint (*init)(struct usb_phy *);\n\tvoid (*shutdown)(struct usb_phy *);\n\tint (*set_vbus)(struct usb_phy *, int);\n\tint (*set_power)(struct usb_phy *, unsigned int);\n\tint (*set_suspend)(struct usb_phy *, int);\n\tint (*set_wakeup)(struct usb_phy *, bool);\n\tint (*notify_connect)(struct usb_phy *, enum usb_device_speed);\n\tint (*notify_disconnect)(struct usb_phy *, enum usb_device_speed);\n\tenum usb_charger_type (*charger_detect)(struct usb_phy *);\n};\n\nstruct clk;\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct ab8500_usb {\n\tstruct usb_phy phy;\n\tstruct device *dev;\n\tstruct ab8500 *ab8500;\n\tunsigned int vbus_draw;\n\tstruct work_struct phy_dis_work;\n\tenum ab8500_usb_mode mode;\n\tstruct clk *sysclk;\n\tstruct regulator *v_ape;\n\tstruct regulator *v_musb;\n\tstruct regulator *v_ulpi;\n\tint saved_v_ulpi;\n\tint previous_link_status_state;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_sleep;\n\tbool enabled_charging_detection;\n\tunsigned int flags;\n};\n\nstruct abx500_ops {\n\tint (*get_chip_id)(struct device *);\n\tint (*get_register)(struct device *, u8, u8, u8 *);\n\tint (*set_register)(struct device *, u8, u8, u8);\n\tint (*get_register_page)(struct device *, u8, u8, u8 *, u8);\n\tint (*set_register_page)(struct device *, u8, u8, u8 *, u8);\n\tint (*mask_and_set_register)(struct device *, u8, u8, u8, u8);\n\tint (*event_registers_startup_state_get)(struct device *, u8 *);\n\tint (*startup_irq_enabled)(struct device *, unsigned int);\n\tvoid (*dump_all_banks)(struct device *);\n};\n\nstruct abx500_device_entry {\n\tstruct list_head list;\n\tstruct abx500_ops ops;\n\tstruct device *dev;\n};\n\nstruct abx500_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct abx500_gpio_irq_cluster {\n\tint start;\n\tint end;\n\tint to_irq;\n};\n\nstruct irq_fwspec;\n\nstruct irq_data;\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nstruct irq_chip;\n\nstruct gpio_chip;\n\nunion gpio_irq_fwspec;\n\nstruct gpio_irq_chip {\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *parent_domain;\n\tint (*child_to_parent_hwirq)(struct gpio_chip *, unsigned int, unsigned int, unsigned int *, unsigned int *);\n\tint (*populate_parent_alloc_arg)(struct gpio_chip *, union gpio_irq_fwspec *, unsigned int, unsigned int);\n\tunsigned int (*child_offset_to_irq)(struct gpio_chip *, unsigned int);\n\tstruct irq_domain_ops child_irq_domain_ops;\n\tirq_flow_handler_t handler;\n\tunsigned int default_type;\n\tstruct lock_class_key *lock_key;\n\tstruct lock_class_key *request_key;\n\tirq_flow_handler_t parent_handler;\n\tunion {\n\t\tvoid *parent_handler_data;\n\t\tvoid **parent_handler_data_array;\n\t};\n\tunsigned int num_parents;\n\tunsigned int *parents;\n\tunsigned int *map;\n\tbool threaded;\n\tbool per_parent_data;\n\tbool initialized;\n\tbool domain_is_allocated_externally;\n\tint (*init_hw)(struct gpio_chip *);\n\tvoid (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tlong unsigned int *valid_mask;\n\tunsigned int first;\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n};\n\nstruct gpio_device;\n\nstruct seq_file;\n\nstruct of_phandle_args;\n\nstruct gpio_chip {\n\tconst char *label;\n\tstruct gpio_device *gpiodev;\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tstruct module *owner;\n\tint (*request)(struct gpio_chip *, unsigned int);\n\tvoid (*free)(struct gpio_chip *, unsigned int);\n\tint (*get_direction)(struct gpio_chip *, unsigned int);\n\tint (*direction_input)(struct gpio_chip *, unsigned int);\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tint (*get)(struct gpio_chip *, unsigned int);\n\tint (*get_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n\tint (*set_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set_config)(struct gpio_chip *, unsigned int, long unsigned int);\n\tint (*to_irq)(struct gpio_chip *, unsigned int);\n\tvoid (*dbg_show)(struct seq_file *, struct gpio_chip *);\n\tint (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tint (*add_pin_ranges)(struct gpio_chip *);\n\tint (*en_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint (*dis_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint base;\n\tu16 ngpio;\n\tu16 offset;\n\tconst char * const *names;\n\tbool can_sleep;\n\tstruct gpio_irq_chip irq;\n\tunsigned int of_gpio_n_cells;\n\tbool (*of_node_instance_match)(struct gpio_chip *, unsigned int);\n\tint (*of_xlate)(struct gpio_chip *, const struct of_phandle_args *, u32 *);\n};\n\nstruct pinctrl_dev;\n\nstruct abx500_pinctrl_soc_data;\n\nstruct abx500_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctldev;\n\tstruct abx500_pinctrl_soc_data *soc;\n\tstruct gpio_chip chip;\n\tstruct ab8500 *parent;\n\tstruct abx500_gpio_irq_cluster *irq_cluster;\n\tint irq_cluster_size;\n};\n\nstruct abx500_pinrange;\n\nstruct pinctrl_pin_desc;\n\nstruct abx500_pingroup;\n\nstruct alternate_functions;\n\nstruct abx500_pinctrl_soc_data {\n\tconst struct abx500_pinrange *gpio_ranges;\n\tunsigned int gpio_num_ranges;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct abx500_function *functions;\n\tunsigned int nfunctions;\n\tconst struct abx500_pingroup *groups;\n\tunsigned int ngroups;\n\tstruct alternate_functions *alternate_functions;\n\tstruct abx500_gpio_irq_cluster *gpio_irq_cluster;\n\tunsigned int ngpio_irq_cluster;\n\tint irq_gpio_rising_offset;\n\tint irq_gpio_falling_offset;\n\tint irq_gpio_factor;\n};\n\nstruct abx500_pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tconst unsigned int npins;\n\tint altsetting;\n};\n\nstruct abx500_pinrange {\n\tunsigned int offset;\n\tunsigned int npins;\n\tint altfunc;\n};\n\nstruct clk_core;\n\nstruct clk_init_data;\n\nstruct clk_hw {\n\tstruct clk_core *core;\n\tstruct clk *clk;\n\tconst struct clk_init_data *init;\n};\n\nstruct regmap;\n\nstruct ac100_clkout {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu8 offset;\n};\n\nstruct ac100_dev {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n};\n\nstruct rtc_device;\n\nstruct clk_hw_onecell_data;\n\nstruct ac100_rtc_dev {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tint irq;\n\tlong unsigned int alarm;\n\tstruct clk_hw *rtc_32k_clk;\n\tstruct ac100_clkout clks[3];\n\tstruct clk_hw_onecell_data *clk_data;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct ac6_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct reg_sequence;\n\nstruct acc_desc {\n\tunsigned int enable_reg;\n\tu32 enable_mask;\n\tstruct reg_sequence *config;\n\tstruct reg_sequence *settings;\n\tint num_regs_per_fuse;\n};\n\nstruct drm_dp_nak_reply {\n\tguid_t guid;\n\tu8 reason;\n\tu8 nak_data;\n};\n\nstruct drm_dp_link_addr_reply_port {\n\tbool input_port;\n\tu8 peer_device_type;\n\tu8 port_number;\n\tbool mcs;\n\tbool ddps;\n\tbool legacy_device_plug_status;\n\tu8 dpcd_revision;\n\tguid_t peer_guid;\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n};\n\nstruct drm_dp_link_address_ack_reply {\n\tguid_t guid;\n\tu8 nports;\n\tstruct drm_dp_link_addr_reply_port ports[16];\n};\n\nstruct drm_dp_port_number_rep {\n\tu8 port_number;\n};\n\nstruct drm_dp_enum_path_resources_ack_reply {\n\tu8 port_number;\n\tbool fec_capable;\n\tu16 full_payload_bw_number;\n\tu16 avail_payload_bw_number;\n};\n\nstruct drm_dp_allocate_payload_ack_reply {\n\tu8 port_number;\n\tu8 vcpi;\n\tu16 allocated_pbn;\n};\n\nstruct drm_dp_query_payload_ack_reply {\n\tu8 port_number;\n\tu16 allocated_pbn;\n};\n\nstruct drm_dp_remote_dpcd_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_dpcd_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_remote_dpcd_write_nak_reply {\n\tu8 port_number;\n\tu8 reason;\n\tu8 bytes_written_before_failure;\n};\n\nstruct drm_dp_remote_i2c_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_i2c_read_nak_reply {\n\tu8 port_number;\n\tu8 nak_reason;\n\tu8 i2c_nak_transaction;\n};\n\nstruct drm_dp_remote_i2c_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_query_stream_enc_status_ack_reply {\n\tu8 stream_id;\n\tbool reply_signed;\n\tbool unauthorizable_device_present;\n\tbool legacy_device_present;\n\tbool query_capable_device_present;\n\tbool hdcp_1x_device_present;\n\tbool hdcp_2x_device_present;\n\tbool auth_completed;\n\tbool encryption_enabled;\n\tbool repeater_present;\n\tu8 state;\n};\n\nunion ack_replies {\n\tstruct drm_dp_nak_reply nak;\n\tstruct drm_dp_link_address_ack_reply link_addr;\n\tstruct drm_dp_port_number_rep port_number;\n\tstruct drm_dp_enum_path_resources_ack_reply path_resources;\n\tstruct drm_dp_allocate_payload_ack_reply allocate_payload;\n\tstruct drm_dp_query_payload_ack_reply query_payload;\n\tstruct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack;\n\tstruct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack;\n\tstruct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack;\n\tstruct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack;\n\tstruct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack;\n\tstruct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;\n\tstruct drm_dp_query_stream_enc_status_ack_reply enc_status;\n};\n\nstruct drm_dp_connection_status_notify {\n\tguid_t guid;\n\tu8 port_number;\n\tbool legacy_device_plug_status;\n\tbool displayport_device_plug_status;\n\tbool message_capability_status;\n\tbool input_port;\n\tu8 peer_device_type;\n};\n\nstruct drm_dp_port_number_req {\n\tu8 port_number;\n};\n\nstruct drm_dp_resource_status_notify {\n\tu8 port_number;\n\tguid_t guid;\n\tu16 available_pbn;\n};\n\nstruct drm_dp_query_payload {\n\tu8 port_number;\n\tu8 vcpi;\n};\n\nstruct drm_dp_allocate_payload {\n\tu8 port_number;\n\tu8 number_sdp_streams;\n\tu8 vcpi;\n\tu16 pbn;\n\tu8 sdp_stream_sink[16];\n};\n\nstruct drm_dp_remote_dpcd_read {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n};\n\nstruct drm_dp_remote_dpcd_write {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_remote_i2c_read_tx {\n\tu8 i2c_dev_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n\tu8 no_stop_bit;\n\tu8 i2c_transaction_delay;\n};\n\nstruct drm_dp_remote_i2c_read {\n\tu8 num_transactions;\n\tu8 port_number;\n\tstruct drm_dp_remote_i2c_read_tx transactions[4];\n\tu8 read_i2c_device_id;\n\tu8 num_bytes_read;\n};\n\nstruct drm_dp_remote_i2c_write {\n\tu8 port_number;\n\tu8 write_i2c_device_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_query_stream_enc_status {\n\tu8 stream_id;\n\tu8 client_id[7];\n\tu8 stream_event;\n\tbool valid_stream_event;\n\tu8 stream_behavior;\n\tu8 valid_stream_behavior;\n};\n\nunion ack_req {\n\tstruct drm_dp_connection_status_notify conn_stat;\n\tstruct drm_dp_port_number_req port_num;\n\tstruct drm_dp_resource_status_notify resource_stat;\n\tstruct drm_dp_query_payload query_payload;\n\tstruct drm_dp_allocate_payload allocate_payload;\n\tstruct drm_dp_remote_dpcd_read dpcd_read;\n\tstruct drm_dp_remote_dpcd_write dpcd_write;\n\tstruct drm_dp_remote_i2c_read i2c_read;\n\tstruct drm_dp_remote_i2c_write i2c_write;\n\tstruct drm_dp_query_stream_enc_status enc_status;\n};\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct comp_alg_common {\n\tstruct crypto_alg base;\n};\n\nstruct acomp_req;\n\nstruct crypto_acomp;\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\ntypedef void (*crypto_completion_t)(void *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n\tunsigned int dma_length;\n};\n\nstruct acomp_req_chain {\n\tcrypto_completion_t compl;\n\tvoid *data;\n\tstruct scatterlist ssg;\n\tstruct scatterlist dsg;\n\tunion {\n\t\tconst u8 *src;\n\t\tstruct folio *sfolio;\n\t};\n\tunion {\n\t\tu8 *dst;\n\t\tstruct folio *dfolio;\n\t};\n\tu32 flags;\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tunion {\n\t\tstruct scatterlist *dst;\n\t\tu8 *dvirt;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct acomp_req_chain chain;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nunion crypto_no_such_thing;\n\nstruct scatter_walk {\n\tunion {\n\t\tvoid * const addr;\n\t\tunion crypto_no_such_thing *__addr;\n\t};\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct acomp_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tint flags;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct acpi_gpio_params;\n\nstruct acpi_gpio_mapping {\n\tconst char *name;\n\tconst struct acpi_gpio_params *data;\n\tunsigned int size;\n\tunsigned int quirks;\n};\n\nstruct acpi_gpio_params {\n\tunsigned int crs_entry_index;\n\tshort unsigned int line_index;\n\tbool active_low;\n};\n\nstruct act8865 {\n\tstruct regmap *regmap;\n\tint off_reg;\n\tint off_mask;\n};\n\nstruct act8865_regulator_data;\n\nstruct act8865_platform_data {\n\tint num_regulators;\n\tstruct act8865_regulator_data *regulators;\n};\n\nstruct regulator_init_data;\n\nstruct act8865_regulator_data {\n\tint id;\n\tconst char *name;\n\tstruct regulator_init_data *init_data;\n\tstruct device_node *of_node;\n};\n\nstruct power_supply;\n\nunion power_supply_propval;\n\nstruct power_supply_desc {\n\tconst char *name;\n\tenum power_supply_type type;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tu32 usb_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, enum power_supply_property);\n\tvoid (*external_power_changed)(struct power_supply *);\n\tbool no_thermal;\n\tint use_for_apm;\n};\n\nstruct gpio_desc;\n\nstruct act8945a_charger {\n\tstruct power_supply *psy;\n\tstruct power_supply_desc desc;\n\tstruct regmap *regmap;\n\tstruct work_struct work;\n\tbool init_done;\n\tstruct gpio_desc *lbo_gpio;\n\tstruct gpio_desc *chglev_gpio;\n};\n\nstruct act8945a_pmic {\n\tstruct regmap *regmap;\n\tu32 op_mode[7];\n};\n\nstruct action_cache {\n\tlong unsigned int allow_native[15];\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct ad_dpot_bus_ops;\n\nstruct ad_dpot_bus_data {\n\tvoid *client;\n\tconst struct ad_dpot_bus_ops *bops;\n};\n\nstruct ad_dpot_bus_ops {\n\tint (*read_d8)(void *);\n\tint (*read_r8d8)(void *, u8);\n\tint (*read_r8d16)(void *, u8);\n\tint (*write_d8)(void *, u8);\n\tint (*write_r8d8)(void *, u8, u8);\n\tint (*write_r8d16)(void *, u8, u16);\n};\n\nstruct addr_sync_ctx {\n\tstruct net_device *ndev;\n\tconst u8 *addr;\n\tint consumed;\n\tint flush;\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct file;\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct audit_ntp_data {};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n\tlong: 32;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n\tlong: 32;\n};\n\nstruct crypto_aead;\n\nstruct aead_request;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct aemif_cs_timings {\n\tu32 ta;\n\tu32 rhold;\n\tu32 rstrobe;\n\tu32 rsetup;\n\tu32 whold;\n\tu32 wstrobe;\n\tu32 wsetup;\n};\n\nstruct aemif_cs_data {\n\tstruct aemif_cs_timings timings;\n\tu8 cs;\n\tu8 enable_ss;\n\tu8 enable_ew;\n\tu8 asize;\n};\n\nstruct aemif_device {\n\tvoid *base;\n\tstruct clk *clk;\n\tlong unsigned int clk_rate;\n\tu8 num_cs;\n\tint cs_offset;\n\tstruct aemif_cs_data cs_data[4];\n\tstruct mutex config_cs_lock;\n};\n\nstruct cpumask;\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request;\n\nstruct crypto_ahash;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*export_core)(struct ahash_request *, void *);\n\tint (*import_core)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_ahash *);\n\tvoid (*exit_tfm)(struct crypto_ahash *);\n\tint (*clone_tfm)(struct crypto_ahash *, struct crypto_ahash *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct hash_alg_common halg;\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tu8 *result;\n\tstruct scatterlist sg_head[2];\n\tcrypto_completion_t saved_complete;\n\tvoid *saved_data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\nstruct ata_link;\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct clk_bulk_data;\n\nstruct reset_control;\n\nstruct phy;\n\nstruct ata_port;\n\nstruct ata_host;\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 mask_port_map;\n\tu32 mask_port_ext;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 saved_port_cap[32];\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tunsigned int n_clks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int f_rsts;\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[15];\n\tchar *irq_desc;\n};\n\nstruct ccsr_ahci;\n\nstruct ahci_qoriq_priv {\n\tstruct ccsr_ahci *reg_base;\n\tenum ahci_qoriq_type type;\n\tvoid *ecc_addr;\n\tbool is_dmacoherent;\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nstruct aic_chip_data {\n\tu32 ext_irqs;\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tlong: 32;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n\tlong: 32;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct eventfd_ctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct gpd_dev_ops {\n\tint (*start)(struct device *);\n\tint (*stop)(struct device *);\n};\n\nstruct dev_power_governor;\n\nstruct genpd_governor_data;\n\nstruct opp_table;\n\nstruct genpd_power_state;\n\nstruct genpd_lock_ops;\n\nstruct generic_pm_domain {\n\tstruct device dev;\n\tstruct dev_pm_domain domain;\n\tstruct list_head gpd_list_node;\n\tstruct list_head parent_links;\n\tstruct list_head child_links;\n\tstruct list_head dev_list;\n\tstruct dev_power_governor *gov;\n\tstruct genpd_governor_data *gd;\n\tstruct work_struct power_off_work;\n\tstruct fwnode_handle *provider;\n\tbool has_provider;\n\tconst char *name;\n\tatomic_t sd_count;\n\tenum gpd_status status;\n\tunsigned int device_count;\n\tunsigned int device_id;\n\tunsigned int suspended_count;\n\tunsigned int prepared_count;\n\tunsigned int performance_state;\n\tcpumask_var_t cpus;\n\tbool synced_poweroff;\n\tbool stay_on;\n\tenum genpd_sync_state sync_state;\n\tint (*power_off)(struct generic_pm_domain *);\n\tint (*power_on)(struct generic_pm_domain *);\n\tstruct raw_notifier_head power_notifiers;\n\tstruct opp_table *opp_table;\n\tint (*set_performance_state)(struct generic_pm_domain *, unsigned int);\n\tstruct gpd_dev_ops dev_ops;\n\tint (*set_hwmode_dev)(struct generic_pm_domain *, struct device *, bool);\n\tbool (*get_hwmode_dev)(struct generic_pm_domain *, struct device *);\n\tint (*attach_dev)(struct generic_pm_domain *, struct device *);\n\tvoid (*detach_dev)(struct generic_pm_domain *, struct device *);\n\tunsigned int flags;\n\tstruct genpd_power_state *states;\n\tvoid (*free_states)(struct genpd_power_state *, unsigned int);\n\tunsigned int state_count;\n\tunsigned int state_idx;\n\tu64 on_time;\n\tu64 accounting_time;\n\tconst struct genpd_lock_ops *lock_ops;\n\tunion {\n\t\tstruct mutex mlock;\n\t\tstruct {\n\t\t\tspinlock_t slock;\n\t\t\tlong unsigned int lock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_slock;\n\t\t\tlong unsigned int raw_lock_flags;\n\t\t};\n\t};\n};\n\nstruct airoha_cpu_pmdomain_priv {\n\tstruct clk_hw hw;\n\tlong: 32;\n\tstruct generic_pm_domain pd;\n};\n\nstruct dev_pm_domain_list;\n\nstruct platform_device;\n\nstruct airoha_cpufreq_priv {\n\tint opp_token;\n\tstruct dev_pm_domain_list *pd_list;\n\tstruct platform_device *cpufreq_dt;\n};\n\nstruct gpio_generic_chip {\n\tstruct gpio_chip gc;\n\tlong unsigned int (*read_reg)(void *);\n\tvoid (*write_reg)(void *, long unsigned int);\n\tbool be_bits;\n\tvoid *reg_dat;\n\tvoid *reg_set;\n\tvoid *reg_clr;\n\tvoid *reg_dir_out;\n\tvoid *reg_dir_in;\n\tbool dir_unreadable;\n\tbool pinctrl;\n\tint bits;\n\traw_spinlock_t lock;\n\tlong unsigned int sdata;\n\tlong unsigned int sdir;\n};\n\nstruct airoha_gpio_ctrl {\n\tstruct gpio_generic_chip gen_gc;\n\tvoid *data;\n\tvoid *dir[2];\n\tvoid *output;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct airoha_trng {\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tstruct completion rng_op_done;\n};\n\nstruct iio_mount_matrix {\n\tconst char *rotation[9];\n};\n\nstruct i2c_client;\n\nstruct ak_def;\n\nstruct ak8975_data {\n\tstruct i2c_client *client;\n\tconst struct ak_def *def;\n\tstruct mutex lock;\n\tu8 asa[3];\n\tlong int raw_to_gauss[3];\n\tstruct gpio_desc *eoc_gpiod;\n\tstruct gpio_desc *reset_gpiod;\n\tint eoc_irq;\n\twait_queue_head_t data_ready_queue;\n\tlong unsigned int flags;\n\tu8 cntl_cache;\n\tstruct iio_mount_matrix orientation;\n\tstruct regulator *vdd;\n\tstruct regulator *vid;\n\tstruct {\n\t\ts16 channels[3];\n\t\t__s64 ts;\n\t} scan;\n};\n\nstruct ak_def {\n\tenum asahi_compass_chipset type;\n\tlong int (*raw_to_gauss)(u16);\n\tu16 range;\n\tu8 ctrl_regs[5];\n\tu8 ctrl_masks[4];\n\tu8 ctrl_modes[4];\n\tu8 data_regs[3];\n};\n\nstruct akcipher_request;\n\nstruct crypto_akcipher;\n\nstruct akcipher_alg {\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct al_cpu_resume_regs_per_cpu {\n\tuint32_t flags;\n\tuint32_t resume_addr;\n};\n\nstruct al_cpu_resume_regs {\n\tuint32_t watermark;\n\tuint32_t flags;\n\tstruct al_cpu_resume_regs_per_cpu per_cpu[0];\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct alarm_regs {\n\tu32 tmr_alarm1_h;\n\tu32 tmr_alarm1_l;\n\tu32 tmr_alarm2_h;\n\tu32 tmr_alarm2_l;\n};\n\nstruct ale_control_info {\n\tconst char *name;\n\tint offset;\n\tint port_offset;\n\tint shift;\n\tint port_shift;\n\tint bits;\n};\n\nstruct ale_entry_fld {\n\tu8 start_bit;\n\tu8 num_bits;\n\tu8 flags;\n};\n\nstruct alert_data {\n\tshort unsigned int addr;\n\tenum i2c_alert_protocol type;\n\tunsigned int data;\n};\n\nstruct alias_prop {\n\tstruct list_head link;\n\tconst char *alias;\n\tstruct device_node *np;\n\tint id;\n\tchar stem[0];\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n\tlong: 32;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n\tlong: 32;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alpha_pll_config {\n\tu32 l;\n\tu32 cal_l;\n\tu32 alpha;\n\tu32 alpha_hi;\n\tu32 config_ctl_val;\n\tu32 config_ctl_hi_val;\n\tu32 config_ctl_hi1_val;\n\tu32 config_ctl_hi2_val;\n\tu32 user_ctl_val;\n\tu32 user_ctl_hi_val;\n\tu32 user_ctl_hi1_val;\n\tu32 test_ctl_val;\n\tu32 test_ctl_mask;\n\tu32 test_ctl_hi_val;\n\tu32 test_ctl_hi_mask;\n\tu32 test_ctl_hi1_val;\n\tu32 test_ctl_hi2_val;\n\tu32 test_ctl_hi3_val;\n\tu32 main_output_mask;\n\tu32 aux_output_mask;\n\tu32 aux2_output_mask;\n\tu32 early_output_mask;\n\tu32 alpha_en_mask;\n\tu32 alpha_mode_mask;\n\tu32 pre_div_val;\n\tu32 pre_div_mask;\n\tu32 post_div_val;\n\tu32 post_div_mask;\n\tu32 vco_val;\n\tu32 vco_mask;\n\tu32 status_val;\n\tu32 status_mask;\n\tu32 lock_det;\n};\n\nstruct alpine_msix_data {\n\tspinlock_t msi_map_lock;\n\tphys_addr_t addr;\n\tu32 spi_first;\n\tu32 num_spis;\n\tlong unsigned int *msi_map;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct psmouse;\n\nstruct input_dev;\n\nstruct alps_nibble_commands;\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct als_data {\n\tstruct mutex mutex;\n};\n\nstruct alternate_functions {\n\tunsigned int pin_number;\n\ts8 gpiosel_bit;\n\ts8 alt_bit1;\n\ts8 alt_bit2;\n\tu8 alta_val;\n\tu8 altb_val;\n\tu8 altc_val;\n};\n\nstruct am33xx_pm_sram_addr;\n\nstruct am33xx_pm_platform_data {\n\tint (*init)(int (*)(u32));\n\tint (*deinit)(void);\n\tint (*soc_suspend)(unsigned int, int (*)(long unsigned int), long unsigned int);\n\tint (*cpu_suspend)(int (*)(long unsigned int), long unsigned int);\n\tvoid (*begin_suspend)(void);\n\tvoid (*finish_suspend)(void);\n\tstruct am33xx_pm_sram_addr * (*get_sram_addrs)(void);\n\tvoid (*save_context)(void);\n\tvoid (*restore_context)(void);\n\tint (*check_off_mode_enable)(void);\n};\n\nstruct am33xx_pm_sram_addr {\n\tvoid (*do_wfi)(void);\n\tlong unsigned int *do_wfi_sz;\n\tlong unsigned int *resume_offset;\n\tlong unsigned int *emif_sram_table;\n\tlong unsigned int *ro_sram_data;\n\tlong unsigned int resume_address;\n};\n\nstruct amba_cs_uci_id {\n\tunsigned int devarch;\n\tunsigned int devarch_mask;\n\tunsigned int devtype;\n\tvoid *data;\n};\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct amba_device {\n\tstruct device dev;\n\tstruct resource res;\n\tstruct clk *pclk;\n\tstruct device_dma_parameters dma_parms;\n\tunsigned int periphid;\n\tstruct mutex periphid_lock;\n\tunsigned int cid;\n\tstruct amba_cs_uci_id uci;\n\tunsigned int irq[9];\n\tconst char *driver_override;\n\tlong: 32;\n};\n\nstruct of_device_id;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct amba_id;\n\nstruct amba_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct amba_device *, const struct amba_id *);\n\tvoid (*remove)(struct amba_device *);\n\tvoid (*shutdown)(struct amba_device *);\n\tconst struct amba_id *id_table;\n\tbool driver_managed_dma;\n};\n\nstruct amba_id {\n\tunsigned int id;\n\tunsigned int mask;\n\tvoid *data;\n};\n\nstruct serio;\n\nstruct amba_kmi_port {\n\tstruct serio *io;\n\tstruct clk *clk;\n\tvoid *base;\n\tunsigned int irq;\n\tunsigned int divisor;\n\tunsigned int open;\n};\n\nstruct dma_chan;\n\nstruct amba_pl011_data {\n\tbool (*dma_filter)(struct dma_chan *, void *);\n\tvoid *dma_rx_param;\n\tvoid *dma_tx_param;\n\tbool dma_rx_poll_enable;\n\tunsigned int dma_rx_poll_rate;\n\tunsigned int dma_rx_poll_timeout;\n\tvoid (*init)(void);\n\tvoid (*exit)(void);\n};\n\nstruct aml_rtc_config {\n\tbool gray_stored;\n};\n\nstruct aml_rtc_data {\n\tstruct regmap *map;\n\tstruct rtc_device *rtc_dev;\n\tint irq;\n\tstruct clk *rtc_clk;\n\tstruct clk *sys_clk;\n\tint rtc_enabled;\n\tconst struct aml_rtc_config *config;\n};\n\nstruct amlogic_thermal_data;\n\nstruct thermal_zone_device;\n\nstruct amlogic_thermal {\n\tstruct platform_device *pdev;\n\tconst struct amlogic_thermal_data *data;\n\tstruct regmap *regmap;\n\tstruct regmap *sec_ao_map;\n\tstruct clk *clk;\n\tstruct thermal_zone_device *tzd;\n\tu32 trim_info;\n};\n\nstruct amlogic_thermal_soc_calib_data;\n\nstruct regmap_config;\n\nstruct amlogic_thermal_data {\n\tint u_efuse_off;\n\tconst struct amlogic_thermal_soc_calib_data *calibration_parameters;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct amlogic_thermal_soc_calib_data {\n\tint A;\n\tint B;\n\tint m;\n\tint n;\n};\n\nstruct amx3_idle_state {\n\tint wfi_flags;\n};\n\nstruct analog_param_field {\n\tunsigned int even;\n\tunsigned int odd;\n};\n\nstruct analog_param_range {\n\tunsigned int min;\n\tunsigned int typ;\n\tunsigned int max;\n};\n\nstruct analog_parameters {\n\tunsigned int num_lines;\n\tunsigned int line_duration_ns;\n\tstruct analog_param_range hact_ns;\n\tstruct analog_param_range hfp_ns;\n\tstruct analog_param_range hslen_ns;\n\tstruct analog_param_range hbp_ns;\n\tstruct analog_param_range hblk_ns;\n\tunsigned int bt601_hfp;\n\tstruct analog_param_field vfp_lines;\n\tstruct analog_param_field vslen_lines;\n\tstruct analog_param_field vbp_lines;\n};\n\nstruct anatop_regulator {\n\tu32 delay_reg;\n\tint delay_bit_shift;\n\tint delay_bit_width;\n\tstruct regulator_desc rdesc;\n\tbool bypass;\n\tint sel;\n};\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct device_attribute;\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct vm_area_struct;\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct aperture_range {\n\tstruct device *dev;\n\tresource_size_t base;\n\tresource_size_t size;\n\tstruct list_head lh;\n\tvoid (*detach)(struct device *);\n};\n\nstruct api_context {\n\tstruct completion done;\n\tint status;\n};\n\nstruct apid_data {\n\tu16 ppid;\n\tu8 write_ee;\n\tu8 irq_ee;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct arch_elf_state {};\n\nstruct arch_hw_breakpoint_ctrl {\n\tu32 __reserved: 9;\n\tu32 mismatch: 1;\n\tshort: 6;\n\tchar: 3;\n\tu32 len: 8;\n\tu32 type: 2;\n\tu32 privilege: 2;\n\tu32 enabled: 1;\n};\n\nstruct arch_hw_breakpoint {\n\tu32 address;\n\tu32 trigger;\n\tstruct arch_hw_breakpoint_ctrl step_ctrl;\n\tstruct arch_hw_breakpoint_ctrl ctrl;\n};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct arch_msi_msg_addr_hi {\n\tu32 address_hi;\n};\n\ntypedef struct arch_msi_msg_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct arch_msi_msg_addr_lo {\n\tu32 address_lo;\n};\n\ntypedef struct arch_msi_msg_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct arch_msi_msg_data {\n\tu32 data;\n};\n\ntypedef struct arch_msi_msg_data arch_msi_msg_data_t;\n\nstruct arch_probes_insn;\n\nstruct pt_regs;\n\ntypedef void probes_insn_handler_t(probes_opcode_t, struct arch_probes_insn *, struct pt_regs *);\n\ntypedef long unsigned int probes_check_cc(long unsigned int);\n\ntypedef void probes_insn_singlestep_t(probes_opcode_t, struct arch_probes_insn *, struct pt_regs *);\n\ntypedef void probes_insn_fn_t(void);\n\nstruct arch_probes_insn {\n\tprobes_opcode_t *insn;\n\tprobes_insn_handler_t *insn_handler;\n\tprobes_check_cc *insn_check_cc;\n\tprobes_insn_singlestep_t *insn_singlestep;\n\tprobes_insn_fn_t *insn_fn;\n\tint stack_space;\n\tlong unsigned int register_usage_flags;\n\tbool kprobe_direct_exec;\n};\n\nstruct arch_specific_insn {\n\tint dummy;\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tlong: 32;\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tlong: 32;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct module *owner;\n};\n\nstruct arch_timer_mem;\n\nstruct arch_timer {\n\tstruct clock_event_device evt;\n\tstruct clocksource cs;\n\tstruct arch_timer_mem *gt_block;\n\tvoid *base;\n\tenum arch_timer_access access;\n\tu32 rate;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cyclecounter;\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tlong: 32;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct arch_timer_kvm_info {\n\tstruct timecounter timecounter;\n\tint virtual_irq;\n\tint physical_irq;\n};\n\nstruct arch_timer_mem_frame {\n\tbool valid;\n\tphys_addr_t cntbase;\n\tsize_t size;\n\tint phys_irq;\n\tint virt_irq;\n};\n\nstruct arch_timer_mem {\n\tphys_addr_t cntctlbase;\n\tsize_t size;\n\tstruct arch_timer_mem_frame frame[8];\n};\n\nstruct arch_uprobe_task;\n\nstruct arch_uprobe {\n\tu8 insn[4];\n\tlong unsigned int ixol[2];\n\tuprobe_opcode_t bpinsn;\n\tbool simulate;\n\tu32 pcreg;\n\tvoid (*prehandler)(struct arch_uprobe *, struct arch_uprobe_task *, struct pt_regs *);\n\tvoid (*posthandler)(struct arch_uprobe *, struct arch_uprobe_task *, struct pt_regs *);\n\tstruct arch_probes_insn asi;\n};\n\nstruct arch_uprobe_task {\n\tu32 backup;\n\tlong unsigned int saved_trap_no;\n};\n\nstruct arch_vdso_time_data {};\n\nstruct arg_dev_net_ip {\n\tstruct net *net;\n\tstruct in6_addr *addr;\n};\n\nstruct arg_netdev_event {\n\tconst struct net_device *dev;\n\tunion {\n\t\tunsigned char nh_flags;\n\t\tlong unsigned int event;\n\t};\n};\n\nstruct args_askumount {\n\t__u32 may_umount;\n};\n\nstruct args_expire {\n\t__u32 how;\n};\n\nstruct args_fail {\n\t__u32 token;\n\t__s32 status;\n};\n\nstruct args_in {\n\t__u32 type;\n};\n\nstruct args_out {\n\t__u32 devid;\n\t__u32 magic;\n};\n\nstruct args_ismountpoint {\n\tunion {\n\t\tstruct args_in in;\n\t\tstruct args_out out;\n\t};\n};\n\nstruct args_openmount {\n\t__u32 devid;\n};\n\nstruct args_protosubver {\n\t__u32 sub_version;\n};\n\nstruct args_protover {\n\t__u32 version;\n};\n\nstruct args_ready {\n\t__u32 token;\n};\n\nstruct args_requester {\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct args_setpipefd {\n\t__s32 pipefd;\n};\n\nstruct args_timeout {\n\t__u64 timeout;\n};\n\nstruct arm_cpuidle_irq_context {};\n\nstruct arm_delay_ops {\n\tvoid (*delay)(long unsigned int);\n\tvoid (*const_udelay)(long unsigned int);\n\tvoid (*udelay)(long unsigned int);\n\tlong unsigned int ticks_per_jiffy;\n};\n\nstruct arm_dma_alloc_args {\n\tstruct device *dev;\n\tsize_t size;\n\tgfp_t gfp;\n\tpgprot_t prot;\n\tconst void *caller;\n\tbool want_vaddr;\n\tint coherent_flag;\n};\n\nstruct page;\n\nstruct arm_dma_free_args;\n\nstruct arm_dma_allocator {\n\tvoid * (*alloc)(struct arm_dma_alloc_args *, struct page **);\n\tvoid (*free)(struct arm_dma_free_args *);\n};\n\nstruct arm_dma_buffer {\n\tstruct list_head list;\n\tvoid *virt;\n\tstruct arm_dma_allocator *allocator;\n};\n\nstruct arm_dma_free_args {\n\tstruct device *dev;\n\tsize_t size;\n\tvoid *cpu_addr;\n\tstruct page *page;\n\tbool want_vaddr;\n};\n\nstruct iommu_flush_ops;\n\nstruct io_pgtable_cfg {\n\tlong unsigned int quirks;\n\tlong unsigned int pgsize_bitmap;\n\tunsigned int ias;\n\tunsigned int oas;\n\tbool coherent_walk;\n\tconst struct iommu_flush_ops *tlb;\n\tstruct device *iommu_dev;\n\tvoid * (*alloc)(void *, size_t, gfp_t);\n\tvoid (*free)(void *, void *, size_t);\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 ttbr;\n\t\t\tstruct {\n\t\t\t\tu32 ips: 3;\n\t\t\t\tu32 tg: 2;\n\t\t\t\tu32 sh: 2;\n\t\t\t\tu32 orgn: 2;\n\t\t\t\tu32 irgn: 2;\n\t\t\t\tu32 tsz: 6;\n\t\t\t} tcr;\n\t\t\tlong: 32;\n\t\t\tu64 mair;\n\t\t} arm_lpae_s1_cfg;\n\t\tstruct {\n\t\t\tu64 vttbr;\n\t\t\tstruct {\n\t\t\t\tu32 ps: 3;\n\t\t\t\tu32 tg: 2;\n\t\t\t\tu32 sh: 2;\n\t\t\t\tu32 orgn: 2;\n\t\t\t\tu32 irgn: 2;\n\t\t\t\tu32 sl: 2;\n\t\t\t\tu32 tsz: 6;\n\t\t\t} vtcr;\n\t\t\tlong: 32;\n\t\t} arm_lpae_s2_cfg;\n\t\tstruct {\n\t\t\tu32 ttbr;\n\t\t\tu32 tcr;\n\t\t\tu32 nmrr;\n\t\t\tu32 prrr;\n\t\t} arm_v7s_cfg;\n\t\tstruct {\n\t\t\tu64 transtab;\n\t\t\tu64 memattr;\n\t\t} arm_mali_lpae_cfg;\n\t\tstruct {\n\t\t\tu64 ttbr[4];\n\t\t\tu32 n_ttbrs;\n\t\t\tu32 n_levels;\n\t\t} apple_dart_cfg;\n\t\tstruct {\n\t\t\tint nid;\n\t\t} amd;\n\t};\n};\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_dirty_bitmap;\n\nstruct io_pgtable_ops {\n\tint (*map_pages)(struct io_pgtable_ops *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct io_pgtable_ops *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tphys_addr_t (*iova_to_phys)(struct io_pgtable_ops *, long unsigned int);\n\tint (*pgtable_walk)(struct io_pgtable_ops *, long unsigned int, void *);\n\tint (*read_and_clear_dirty)(struct io_pgtable_ops *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct io_pgtable {\n\tenum io_pgtable_fmt fmt;\n\tvoid *cookie;\n\tstruct io_pgtable_cfg cfg;\n\tstruct io_pgtable_ops ops;\n\tlong: 32;\n};\n\nstruct arm_lpae_io_pgtable {\n\tstruct io_pgtable iop;\n\tint pgd_bits;\n\tint start_level;\n\tint bits_per_level;\n\tvoid *pgd;\n};\n\nstruct arm_lpae_io_pgtable_walk_data {\n\tu64 ptes[4];\n};\n\nstruct perf_cpu_pmu_context;\n\nstruct perf_event;\n\nstruct mm_struct;\n\nstruct perf_event_pmu_context;\n\nstruct kmem_cache;\n\nstruct perf_output_handle;\n\nstruct pmu {\n\tstruct list_head entry;\n\tspinlock_t events_lock;\n\tstruct list_head events;\n\tstruct module *module;\n\tstruct device *dev;\n\tstruct device *parent;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tunsigned int scope;\n\tstruct perf_cpu_pmu_context **cpu_pmu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tstruct kmem_cache *task_ctx_cache;\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tbool (*filter)(struct pmu *, int);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct pmu_hw_events;\n\nstruct hw_perf_event;\n\nstruct perf_event_attr;\n\nstruct arm_pmu {\n\tstruct pmu pmu;\n\tcpumask_t supported_cpus;\n\tchar *name;\n\tirqreturn_t (*handle_irq)(struct arm_pmu *);\n\tvoid (*enable)(struct perf_event *);\n\tvoid (*disable)(struct perf_event *);\n\tint (*get_event_idx)(struct pmu_hw_events *, struct perf_event *);\n\tvoid (*clear_event_idx)(struct pmu_hw_events *, struct perf_event *);\n\tint (*set_event_filter)(struct hw_perf_event *, struct perf_event_attr *);\n\tu64 (*read_counter)(struct perf_event *);\n\tvoid (*write_counter)(struct perf_event *, u64);\n\tvoid (*start)(struct arm_pmu *);\n\tvoid (*stop)(struct arm_pmu *);\n\tvoid (*reset)(void *);\n\tint (*map_event)(struct perf_event *);\n\tint (*map_pmuv3_event)(unsigned int);\n\tlong unsigned int cntr_mask[1];\n\tbool secure_access;\n\tstruct platform_device *plat_device;\n\tstruct pmu_hw_events *hw_events;\n\tstruct hlist_node node;\n\tstruct notifier_block cpu_pm_nb;\n\tconst struct attribute_group *attr_groups[5];\n\tint pmuver;\n\tbool has_smt;\n\tu64 reg_pmmir;\n\tu64 reg_brbidr;\n\tlong unsigned int pmceid_bitmap[2];\n\tlong unsigned int pmceid_ext_bitmap[2];\n\tlong unsigned int acpi_cpuid;\n\tlong: 32;\n};\n\nstruct arm_smccc_args {\n\tlong unsigned int args[8];\n};\n\nstruct arm_smccc_quirk {\n\tint id;\n\tunion {\n\t\tlong unsigned int a6;\n\t} state;\n};\n\nstruct arm_smccc_res {\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n\tlong unsigned int a3;\n};\n\nstruct armada375_cluster_phy {\n\tstruct phy *phy;\n\tvoid *reg;\n\tbool use_usb3;\n\tint phy_provided;\n};\n\nstruct armada_thermal_priv;\n\nstruct armada_drvdata {\n\tenum drvtype type;\n\tunion {\n\t\tstruct armada_thermal_priv *priv;\n\t\tstruct thermal_zone_device *tz;\n\t} data;\n};\n\nstruct armada_thermal_data {\n\tvoid (*init)(struct platform_device *, struct armada_thermal_priv *);\n\tlong: 32;\n\ts64 coef_b;\n\ts64 coef_m;\n\tu32 coef_div;\n\tbool inverted;\n\tbool signed_sample;\n\tunsigned int temp_shift;\n\tunsigned int temp_mask;\n\tunsigned int thresh_shift;\n\tunsigned int hyst_shift;\n\tunsigned int hyst_mask;\n\tu32 is_valid_bit;\n\tunsigned int syscon_control0_off;\n\tunsigned int syscon_control1_off;\n\tunsigned int syscon_status_off;\n\tunsigned int dfx_irq_cause_off;\n\tunsigned int dfx_irq_mask_off;\n\tunsigned int dfx_overheat_irq;\n\tunsigned int dfx_server_irq_mask_off;\n\tunsigned int dfx_server_irq_en;\n\tunsigned int cpu_nr;\n\tlong: 32;\n};\n\nstruct armada_thermal_priv {\n\tstruct device *dev;\n\tstruct regmap *syscon;\n\tchar zone_name[20];\n\tstruct mutex update_lock;\n\tstruct armada_thermal_data *data;\n\tstruct thermal_zone_device *overheat_sensor;\n\tint interrupt_source;\n\tint current_channel;\n\tlong int current_threshold;\n\tlong int current_hysteresis;\n};\n\nstruct armada_thermal_sensor {\n\tstruct armada_thermal_priv *priv;\n\tint id;\n};\n\nstruct armctrl_ic {\n\tvoid *base;\n\tvoid *pending[3];\n\tvoid *enable[3];\n\tvoid *disable[3];\n\tstruct irq_domain *domain;\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct trace_array;\n\nstruct trace_buffer;\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tlong: 32;\n\tu64 time_start;\n\tint cpu;\n\tlong: 32;\n};\n\nstruct clk_onecell_data {\n\tstruct clk **clks;\n\tunsigned int clk_num;\n};\n\nstruct artpec6_clkctrl_drvdata {\n\tstruct clk *clk_table[20];\n\tvoid *syscon_base;\n\tstruct clk_onecell_data clk_data;\n\tspinlock_t i2scfg_lock;\n};\n\nstruct as3711 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n};\n\nstruct backlight_device;\n\nstruct as3711_bl_data {\n\tbool powered;\n\tenum as3711_bl_type type;\n\tint brightness;\n\tstruct backlight_device *bl;\n};\n\nstruct as3711_bl_pdata {\n\tbool su1_fb;\n\tint su1_max_uA;\n\tbool su2_fb;\n\tint su2_max_uA;\n\tenum as3711_su2_feedback su2_feedback;\n\tenum as3711_su2_fbprot su2_fbprot;\n\tbool su2_auto_curr1;\n\tbool su2_auto_curr2;\n\tbool su2_auto_curr3;\n};\n\nstruct as3711_bl_supply {\n\tstruct as3711_bl_data su1;\n\tstruct as3711_bl_data su2;\n\tconst struct as3711_bl_pdata *pdata;\n\tstruct as3711 *as3711;\n};\n\nstruct as3711_regulator_pdata {\n\tstruct regulator_init_data *init_data[12];\n};\n\nstruct as3711_platform_data {\n\tstruct as3711_regulator_pdata regulator;\n\tstruct as3711_bl_pdata backlight;\n};\n\nstruct regmap_irq_chip_data;\n\nstruct as3722 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tint chip_irq;\n\tlong unsigned int irq_flags;\n\tbool en_intern_int_pullup;\n\tbool en_intern_i2c_pullup;\n\tbool en_ac_ok_pwr_on;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct as3722_gpio_pin_control {\n\tunsigned int mode_prop;\n\tint io_function;\n};\n\nstruct as3722_pin_function;\n\nstruct as3722_pingroup;\n\nstruct as3722_pctrl_info {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct as3722 *as3722;\n\tstruct gpio_chip gpio_chip;\n\tint pins_current_opt[8];\n\tconst struct as3722_pin_function *functions;\n\tunsigned int num_functions;\n\tconst struct as3722_pingroup *pin_groups;\n\tint num_pin_groups;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int num_pins;\n\tstruct as3722_gpio_pin_control gpio_control[8];\n};\n\nstruct as3722_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n\tint mux_option;\n};\n\nstruct as3722_pingroup {\n\tconst char *name;\n\tconst unsigned int pins[1];\n\tunsigned int npins;\n};\n\nstruct as3722_poweroff {\n\tstruct device *dev;\n\tstruct as3722 *as3722;\n};\n\nstruct as3722_register_mapping {\n\tu8 regulator_id;\n\tconst char *name;\n\tconst char *sname;\n\tu8 vsel_reg;\n\tu8 vsel_mask;\n\tint n_voltages;\n\tu32 enable_reg;\n\tu8 enable_mask;\n\tu32 control_reg;\n\tu8 mode_mask;\n\tu32 sleep_ctrl_reg;\n\tu8 sleep_ctrl_mask;\n};\n\nstruct as3722_regulator_config_data {\n\tstruct regulator_init_data *reg_init;\n\tbool enable_tracking;\n\tint ext_control;\n};\n\nstruct as3722_regulators {\n\tstruct device *dev;\n\tstruct as3722 *as3722;\n\tstruct regulator_desc desc[18];\n\tstruct as3722_regulator_config_data reg_config_data[18];\n};\n\nstruct as3722_rtc {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tstruct as3722 *as3722;\n\tint alarm_irq;\n\tbool irq_enable;\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\tunion {\n\t\t__u32 padding[5];\n\t\tstruct {\n\t\t\t__u8 addr_recv;\n\t\t\t__u8 addr_dest;\n\t\t\t__u8 padding0[2];\n\t\t\t__u32 padding1[4];\n\t\t};\n\t};\n};\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct ktermios;\n\nstruct uart_state;\n\nstruct console;\n\nstruct uart_ops;\n\nstruct serial_port_device;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int ctrl_id;\n\tunsigned int port_id;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char quirks;\n\tenum uart_iotype iotype;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tlong: 32;\n\tupf_t flags;\n\tupstat_t status;\n\tbool hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int frame_time;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tstruct serial_port_device *port_dev;\n\tlong unsigned int sysrq;\n\tu8 sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tunsigned char console_reinit;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct serial_rs485 rs485_supported;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct gpio_desc *rs485_rx_during_tx_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nstruct asc_port {\n\tstruct uart_port port;\n\tstruct gpio_desc *rts;\n\tstruct clk *clk;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *states[2];\n\tunsigned int hw_flow_control: 1;\n\tunsigned int force_m1: 1;\n};\n\nstruct asix_rx_fixup_info {\n\tstruct sk_buff *ax_skb;\n\tu32 header;\n\tu16 remaining;\n\tbool split_head;\n};\n\nstruct phylink_link_state;\n\nstruct phylink_config {\n\tstruct device *dev;\n\tenum phylink_op_type type;\n\tbool poll_fixed_state;\n\tbool mac_managed_pm;\n\tbool mac_requires_rxc;\n\tbool default_an_inband;\n\tbool eee_rx_clk_stop_enable;\n\tvoid (*get_fixed_state)(struct phylink_config *, struct phylink_link_state *);\n\tlong unsigned int supported_interfaces[2];\n\tlong unsigned int lpi_interfaces[2];\n\tlong unsigned int mac_capabilities;\n\tlong unsigned int lpi_capabilities;\n\tu32 lpi_timer_default;\n\tbool eee_enabled_default;\n\tbool wol_phy_legacy;\n\tbool wol_phy_speed_ctrl;\n\tu32 wol_mac_support;\n};\n\nstruct usbnet;\n\nstruct mii_bus;\n\nstruct phy_device;\n\nstruct phylink;\n\nstruct asix_common_private {\n\tvoid (*resume)(struct usbnet *);\n\tvoid (*suspend)(struct usbnet *);\n\tint (*reset)(struct usbnet *, int);\n\tu16 presvd_phy_advertise;\n\tu16 presvd_phy_bmcr;\n\tstruct asix_rx_fixup_info rx_fixup_info;\n\tstruct mii_bus *mdio;\n\tstruct phy_device *phydev;\n\tstruct phy_device *phydev_int;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tu16 phy_addr;\n\tbool embd_phy;\n\tu8 chipcode;\n};\n\nstruct asix_data {\n\tu8 multi_filter[8];\n\tu8 mac_addr[6];\n\tu8 phymode;\n\tu8 ledmode;\n\tu8 res;\n};\n\ntypedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t);\n\nstruct asn1_decoder {\n\tconst unsigned char *machine;\n\tsize_t machlen;\n\tconst asn1_action_t *actions;\n};\n\nstruct aspeed_clk_gate {\n\tstruct clk_hw hw;\n\tstruct regmap *map;\n\tu8 clock_idx;\n\ts8 reset_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_div_table;\n\nstruct aspeed_clk_soc_data {\n\tconst struct clk_div_table *div_table;\n\tconst struct clk_div_table *eclk_div_table;\n\tconst struct clk_div_table *mac_div_table;\n\tstruct clk_hw * (*calc_pll)(const char *, u32);\n};\n\nstruct aspeed_gate_data {\n\tu8 clock_idx;\n\ts8 reset_idx;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n};\n\nstruct aspeed_i2c_ic {\n\tvoid *base;\n\tint parent_irq;\n\tstruct irq_domain *irq_domain;\n};\n\nstruct aspeed_intc_ic {\n\tvoid *base;\n\traw_spinlock_t gic_lock;\n\traw_spinlock_t intc_lock;\n\tstruct irq_domain *irq_domain;\n};\n\nstruct aspeed_pin_config {\n\tenum pin_config_param param;\n\tunsigned int pins[2];\n\tunsigned int reg;\n\tu32 mask;\n};\n\nstruct aspeed_pin_config_map {\n\tenum pin_config_param param;\n\ts32 arg;\n\tu32 val;\n\tu32 mask;\n};\n\nstruct aspeed_sig_expr;\n\nstruct aspeed_pin_desc {\n\tconst char *name;\n\tconst struct aspeed_sig_expr ***prios;\n};\n\nstruct aspeed_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct aspeed_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tconst unsigned int npins;\n};\n\nstruct aspeed_pinmux_ops;\n\nstruct aspeed_pinmux_data {\n\tstruct device *dev;\n\tstruct regmap *maps[3];\n\tconst struct aspeed_pinmux_ops *ops;\n\tconst struct aspeed_pin_group *groups;\n\tconst unsigned int ngroups;\n\tconst struct aspeed_pin_function *functions;\n\tconst unsigned int nfunctions;\n};\n\nstruct aspeed_pinctrl_data {\n\tstruct regmap *scu;\n\tconst struct pinctrl_pin_desc *pins;\n\tconst unsigned int npins;\n\tconst struct aspeed_pin_config *configs;\n\tconst unsigned int nconfigs;\n\tstruct aspeed_pinmux_data pinmux;\n\tconst struct aspeed_pin_config_map *confmaps;\n\tconst unsigned int nconfmaps;\n};\n\nstruct aspeed_pinmux_ops {\n\tint (*eval)(struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool);\n\tint (*set)(struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool);\n};\n\nstruct reset_control_ops;\n\nstruct reset_controller_dev {\n\tconst struct reset_control_ops *ops;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct list_head reset_control_head;\n\tstruct device *dev;\n\tstruct device_node *of_node;\n\tconst struct of_phandle_args *of_args;\n\tint of_reset_n_cells;\n\tint (*of_xlate)(struct reset_controller_dev *, const struct of_phandle_args *);\n\tunsigned int nr_resets;\n};\n\nstruct aspeed_reset {\n\tstruct regmap *map;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct aspeed_scu_ic {\n\tlong unsigned int irq_enable;\n\tlong unsigned int irq_shift;\n\tunsigned int num_irqs;\n\tvoid *base;\n\tstruct irq_domain *irq_domain;\n\tlong unsigned int ier;\n\tlong unsigned int isr;\n};\n\nstruct aspeed_scu_ic_variant {\n\tconst char *compatible;\n\tlong unsigned int irq_enable;\n\tlong unsigned int irq_shift;\n\tunsigned int num_irqs;\n\tlong unsigned int ier;\n\tlong unsigned int isr;\n};\n\nstruct aspeed_sgpio_pdata;\n\nstruct aspeed_sgpio {\n\tstruct gpio_chip chip;\n\tstruct device *dev;\n\tstruct clk *pclk;\n\traw_spinlock_t lock;\n\tvoid *base;\n\tint irq;\n\tconst struct aspeed_sgpio_pdata *pdata;\n};\n\nstruct aspeed_sgpio_bank {\n\tu16 val_regs;\n\tu16 rdata_reg;\n\tu16 irq_regs;\n\tu16 tolerance_regs;\n};\n\nstruct aspeed_sgpio_llops {\n\tvoid (*reg_bit_set)(struct aspeed_sgpio *, unsigned int, const enum aspeed_sgpio_reg, bool);\n\tbool (*reg_bit_get)(struct aspeed_sgpio *, unsigned int, const enum aspeed_sgpio_reg);\n\tint (*reg_bank_get)(struct aspeed_sgpio *, unsigned int, const enum aspeed_sgpio_reg);\n};\n\nstruct aspeed_sgpio_pdata {\n\tconst u32 pin_mask;\n\tconst struct aspeed_sgpio_llops *llops;\n\tconst u32 cfg_offset;\n};\n\nstruct aspeed_sig_desc {\n\tunsigned int ip;\n\tunsigned int reg;\n\tu32 mask;\n\tu32 enable;\n\tu32 disable;\n};\n\nstruct aspeed_sig_expr {\n\tconst char *signal;\n\tconst char *function;\n\tint ndescs;\n\tconst struct aspeed_sig_desc *descs;\n};\n\nstruct aspeed_uart_routing {\n\tstruct regmap *map;\n\tconst struct attribute_group *attr_grp;\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct aspeed_uart_routing_selector {\n\tstruct device_attribute dev_attr;\n\tuint8_t reg;\n\tuint8_t mask;\n\tuint8_t shift;\n\tconst char * const options[0];\n};\n\nstruct aspeed_vic {\n\tvoid *base;\n\tu32 edge_sources[2];\n\tstruct irq_domain *dom;\n};\n\nstruct watchdog_info;\n\nstruct watchdog_ops;\n\nstruct watchdog_governor;\n\nstruct watchdog_core_data;\n\nstruct watchdog_device {\n\tint id;\n\tstruct device *parent;\n\tconst struct attribute_group **groups;\n\tconst struct watchdog_info *info;\n\tconst struct watchdog_ops *ops;\n\tconst struct watchdog_governor *gov;\n\tunsigned int bootstatus;\n\tunsigned int timeout;\n\tunsigned int pretimeout;\n\tunsigned int min_timeout;\n\tunsigned int max_timeout;\n\tunsigned int min_hw_heartbeat_ms;\n\tunsigned int max_hw_heartbeat_ms;\n\tstruct notifier_block reboot_nb;\n\tstruct notifier_block restart_nb;\n\tstruct notifier_block pm_nb;\n\tvoid *driver_data;\n\tstruct watchdog_core_data *wd_data;\n\tlong unsigned int status;\n\tstruct list_head deferred;\n};\n\nstruct aspeed_wdt_config;\n\nstruct aspeed_wdt {\n\tstruct watchdog_device wdd;\n\tvoid *base;\n\tu32 ctrl;\n\tconst struct aspeed_wdt_config *cfg;\n};\n\nstruct aspeed_wdt_scu {\n\tconst char *compatible;\n\tu32 reset_status_reg;\n\tu32 wdt_reset_mask;\n\tu32 wdt_reset_mask_shift;\n};\n\nstruct aspeed_wdt_config {\n\tu32 ext_pulse_width_mask;\n\tu32 irq_shift;\n\tu32 irq_mask;\n\tstruct aspeed_wdt_scu scu;\n\tu32 num_reset_masks;\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct asv_limit_entry {\n\tunsigned int hpm;\n\tunsigned int ids;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct asymmetric_key_id {\n\tshort unsigned int len;\n\tunsigned char data[0];\n};\n\nstruct asymmetric_key_ids {\n\tvoid *id[3];\n};\n\nstruct key_preparsed_payload;\n\nstruct asymmetric_key_parser {\n\tstruct list_head link;\n\tstruct module *owner;\n\tconst char *name;\n\tint (*parse)(struct key_preparsed_payload *);\n};\n\nstruct key;\n\nstruct kernel_pkey_params;\n\nstruct kernel_pkey_query;\n\nstruct public_key_signature;\n\nstruct asymmetric_key_subtype {\n\tstruct module *owner;\n\tconst char *name;\n\tshort unsigned int name_len;\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tvoid (*destroy)(void *, void *);\n\tint (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*verify_signature)(const struct key *, const struct public_key_signature *);\n};\n\nstruct usb_dev_state;\n\nstruct pid;\n\nstruct urb;\n\nstruct usb_memory;\n\nstruct async {\n\tstruct list_head asynclist;\n\tstruct usb_dev_state *ps;\n\tstruct pid *pid;\n\tconst struct cred *cred;\n\tunsigned int signr;\n\tunsigned int ifnum;\n\tvoid *userbuffer;\n\tvoid *userurb;\n\tsigval_t userurb_sigval;\n\tstruct urb *urb;\n\tstruct usb_memory *usbm;\n\tunsigned int mem_usage;\n\tint status;\n\tu8 bulk_addr;\n\tu8 bulk_status;\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n\tlong: 32;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct at24_chip_data {\n\tu32 byte_len;\n\tu8 flags;\n\tu8 bank_addr_shift;\n\tvoid (*read_post)(unsigned int, char *, size_t);\n};\n\nstruct nvmem_device;\n\nstruct at24_data {\n\tstruct mutex lock;\n\tunsigned int write_max;\n\tunsigned int num_addresses;\n\tunsigned int offset_adj;\n\tu32 byte_len;\n\tu16 page_size;\n\tu8 flags;\n\tstruct nvmem_device *nvmem;\n\tstruct regulator *vcc_reg;\n\tvoid (*read_post)(unsigned int, char *, size_t);\n\tu8 bank_addr_shift;\n\tstruct regmap *client_regmaps[0];\n};\n\nstruct at803x_context {\n\tu16 bmcr;\n\tu16 advertise;\n\tu16 control1000;\n\tu16 int_enable;\n\tu16 smart_speed;\n\tu16 led_control;\n};\n\nstruct at803x_priv {\n\tint flags;\n\tu16 clk_25m_reg;\n\tu16 clk_25m_mask;\n\tu8 smarteee_lpi_tw_1g;\n\tu8 smarteee_lpi_tw_100m;\n\tbool is_fiber;\n\tbool is_1000basex;\n\tstruct regulator_dev *vddio_rdev;\n\tstruct regulator_dev *vddh_rdev;\n};\n\nstruct at803x_ss_mask {\n\tu16 speed_mask;\n\tu8 speed_shift;\n};\n\nstruct at91_clk_pms {\n\tlong unsigned int rate;\n\tlong unsigned int parent_rate;\n\tunsigned int status;\n\tunsigned int parent;\n};\n\nstruct pinctrl_gpio_range {\n\tstruct list_head node;\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int base;\n\tunsigned int pin_base;\n\tunsigned int npins;\n\tconst unsigned int *pins;\n\tstruct gpio_chip *gc;\n};\n\nstruct at91_pinctrl_mux_ops;\n\nstruct at91_gpio_chip {\n\tstruct gpio_chip chip;\n\tstruct pinctrl_gpio_range range;\n\tstruct at91_gpio_chip *next;\n\tint pioc_hwirq;\n\tint pioc_virq;\n\tvoid *regbase;\n\tstruct clk *clock;\n\tconst struct at91_pinctrl_mux_ops *ops;\n\tu32 wakeups;\n\tu32 backups;\n\tu32 id;\n};\n\nstruct at91_pmx_pin;\n\nstruct at91_pin_group {\n\tconst char *name;\n\tstruct at91_pmx_pin *pins_conf;\n\tunsigned int *pins;\n\tunsigned int npins;\n};\n\nstruct at91_pmx_func;\n\nstruct at91_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tint nactive_banks;\n\tuint32_t *mux_mask;\n\tint nmux;\n\tstruct at91_pmx_func *functions;\n\tint nfunctions;\n\tstruct at91_pin_group *groups;\n\tint ngroups;\n\tconst struct at91_pinctrl_mux_ops *ops;\n};\n\nstruct at91_pinctrl_mux_ops {\n\tenum at91_mux (*get_periph)(void *, unsigned int);\n\tvoid (*mux_A_periph)(void *, unsigned int);\n\tvoid (*mux_B_periph)(void *, unsigned int);\n\tvoid (*mux_C_periph)(void *, unsigned int);\n\tvoid (*mux_D_periph)(void *, unsigned int);\n\tbool (*get_deglitch)(void *, unsigned int);\n\tvoid (*set_deglitch)(void *, unsigned int, bool);\n\tbool (*get_debounce)(void *, unsigned int, u32 *);\n\tvoid (*set_debounce)(void *, unsigned int, bool, u32);\n\tbool (*get_pulldown)(void *, unsigned int);\n\tvoid (*set_pulldown)(void *, unsigned int, bool);\n\tbool (*get_schmitt_trig)(void *, unsigned int);\n\tvoid (*disable_schmitt_trig)(void *, unsigned int);\n\tunsigned int (*get_drivestrength)(void *, unsigned int);\n\tvoid (*set_drivestrength)(void *, unsigned int, u32);\n\tunsigned int (*get_slewrate)(void *, unsigned int);\n\tvoid (*set_slewrate)(void *, unsigned int, u32);\n\tint (*irq_type)(struct irq_data *, unsigned int);\n};\n\nstruct at91_pm_bu {\n\tint suspended;\n\tlong unsigned int reserved;\n\tphys_addr_t canary;\n\tphys_addr_t resume;\n\tlong unsigned int ddr_phy_calibration[9];\n};\n\nstruct at91_pm_data {\n\tvoid *pmc;\n\tvoid *ramc[2];\n\tvoid *ramc_phy;\n\tlong unsigned int uhp_udp_mask;\n\tunsigned int memctrl;\n\tunsigned int mode;\n\tvoid *shdwc;\n\tvoid *sfrbu;\n\tunsigned int standby_mode;\n\tunsigned int suspend_mode;\n\tunsigned int pmc_mckr_offset;\n\tunsigned int pmc_version;\n\tunsigned int pmc_mcks;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct at91_pm_quirk_eth {\n\tstruct device *dev;\n\tstruct device_node *np;\n\tstruct clk_bulk_data clks[2];\n\tu32 modes;\n\tu32 dns_modes;\n};\n\nstruct at91_pm_quirks {\n\tstruct at91_pm_quirk_eth eth[2];\n};\n\nstruct at91_pm_sfrbu_regs {\n\tstruct {\n\t\tu32 key;\n\t\tu32 ctrl;\n\t\tu32 state;\n\t\tu32 softsw;\n\t} pswbu;\n};\n\nstruct at91_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct at91_pmx_pin {\n\tuint32_t bank;\n\tuint32_t pin;\n\tenum at91_mux mux;\n\tlong unsigned int conf;\n};\n\nstruct at91_reset_data;\n\nstruct at91_reset {\n\tvoid *rstc_base;\n\tvoid *ramc_base[2];\n\tvoid *dev_base;\n\tstruct clk *sclk;\n\tconst struct at91_reset_data *data;\n\tstruct reset_controller_dev rcdev;\n\tspinlock_t lock;\n\tstruct notifier_block nb;\n\tu32 args;\n\tu32 ramc_lpr;\n};\n\nstruct at91_reset_data {\n\tu32 reset_args;\n\tu32 n_device_reset;\n\tu8 device_reset_min_id;\n\tu8 device_reset_max_id;\n};\n\nstruct at91_soc {\n\tu32 cidr_match;\n\tu32 cidr_mask;\n\tu32 version_mask;\n\tu32 exid_match;\n\tconst char *name;\n\tconst char *family;\n};\n\nstruct at91_soc_pm {\n\tint (*config_shdwc_ws)(void *, u32 *, u32 *);\n\tint (*config_pmc_ws)(void *, u32, u32);\n\tconst struct of_device_id *ws_ids;\n\tstruct at91_pm_bu *bu;\n\tstruct at91_pm_quirks quirks;\n\tstruct at91_pm_data data;\n\tstruct at91_pm_sfrbu_regs sfrbu_regs;\n\tvoid *memcs;\n};\n\nstruct at91_usbh_data {\n\tstruct gpio_desc *vbus_pin[3];\n\tstruct gpio_desc *overcurrent_pin[3];\n\tu8 ports;\n\tu8 overcurrent_supported;\n\tu8 overcurrent_status[3];\n\tu8 overcurrent_changed[3];\n};\n\nstruct at91rm9200_clk_usb {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 divisors[4];\n};\n\nstruct at91sam9x5_clk_smd {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n};\n\nstruct at91sam9x5_clk_usb {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct at91_clk_pms pms;\n\tu32 usbs_mask;\n\tu8 num_parents;\n};\n\nstruct at91wdt {\n\tstruct watchdog_device wdd;\n\tvoid *base;\n\tlong unsigned int next_heartbeat;\n\tstruct timer_list timer;\n\tu32 mr;\n\tu32 mr_mask;\n\tlong unsigned int heartbeat;\n\tbool nowayout;\n\tunsigned int irq;\n\tstruct clk *sclk;\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nstruct dmaengine_result;\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dmaengine_unmap_data;\n\nstruct dma_descriptor_metadata_ops;\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n\tstruct dma_async_tx_descriptor *next;\n\tstruct dma_async_tx_descriptor *parent;\n\tspinlock_t lock;\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\nstruct virt_dma_desc {\n\tstruct dma_async_tx_descriptor tx;\n\tstruct dmaengine_result tx_result;\n\tstruct list_head node;\n};\n\nstruct at_lli;\n\nstruct atdma_sg {\n\tunsigned int len;\n\tstruct at_lli *lli;\n\tdma_addr_t lli_phys;\n};\n\nstruct at_dma_chan;\n\nstruct at_desc {\n\tstruct virt_dma_desc vd;\n\tstruct at_dma_chan *atchan;\n\tsize_t total_len;\n\tunsigned int sglen;\n\tsize_t boundary;\n\tsize_t dst_hole;\n\tsize_t src_hole;\n\tbool memset_buffer;\n\tdma_addr_t memset_paddr;\n\tint *memset_vaddr;\n\tstruct atdma_sg sg[0];\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan *, void *);\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct dma_vec;\n\nstruct dma_interleaved_template;\n\nstruct dma_slave_caps;\n\nstruct dma_slave_config;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan *);\n\tint (*device_router_config)(struct dma_chan *);\n\tvoid (*device_free_chan_resources)(struct dma_chan *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_peripheral_dma_vec)(struct dma_chan *, const struct dma_vec *, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan *, struct dma_interleaved_template *, long unsigned int);\n\tvoid (*device_caps)(struct dma_chan *, struct dma_slave_caps *);\n\tint (*device_config)(struct dma_chan *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan *);\n\tint (*device_resume)(struct dma_chan *);\n\tint (*device_terminate_all)(struct dma_chan *);\n\tvoid (*device_synchronize)(struct dma_chan *);\n\tenum dma_status (*device_tx_status)(struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct dma_chan_dev;\n\nstruct dma_chan_percpu;\n\nstruct dma_router;\n\nstruct dma_chan {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct virt_dma_chan {\n\tstruct dma_chan chan;\n\tstruct tasklet_struct task;\n\tvoid (*desc_free)(struct virt_dma_desc *);\n\tspinlock_t lock;\n\tstruct list_head desc_allocated;\n\tstruct list_head desc_submitted;\n\tstruct list_head desc_issued;\n\tstruct list_head desc_completed;\n\tstruct list_head desc_terminated;\n\tstruct virt_dma_desc *cyclic;\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n};\n\nstruct at_dma;\n\nstruct at_dma_chan {\n\tstruct virt_dma_chan vc;\n\tstruct at_dma *atdma;\n\tvoid *ch_regs;\n\tu8 mask;\n\tu8 per_if;\n\tu8 mem_if;\n\tlong unsigned int status;\n\tu32 save_cfg;\n\tu32 save_dscr;\n\tstruct dma_slave_config dma_sconfig;\n\tstruct at_desc *desc;\n};\n\nstruct dma_pool;\n\nstruct at_dma {\n\tstruct dma_device dma_device;\n\tvoid *regs;\n\tstruct clk *clk;\n\tu32 save_imr;\n\tu8 all_chan_mask;\n\tstruct dma_pool *lli_pool;\n\tstruct dma_pool *memset_pool;\n\tstruct at_dma_chan chan[0];\n};\n\nstruct at_dma_platform_data {\n\tunsigned int nr_channels;\n\tdma_cap_mask_t cap_mask;\n};\n\nstruct at_dma_slave {\n\tstruct device *dma_dev;\n\tu32 cfg;\n};\n\nstruct at_lli {\n\tu32 saddr;\n\tu32 daddr;\n\tu32 ctrla;\n\tu32 ctrlb;\n\tu32 dscr;\n};\n\nstruct at_xdmac_chan {\n\tstruct dma_chan chan;\n\tvoid *ch_regs;\n\tu32 mask;\n\tu32 cfg;\n\tu8 perid;\n\tu8 perif;\n\tu8 memif;\n\tu32 save_cc;\n\tu32 save_cim;\n\tu32 save_cnda;\n\tu32 save_cndc;\n\tu32 irq_status;\n\tlong unsigned int status;\n\tstruct tasklet_struct tasklet;\n\tstruct dma_slave_config sconfig;\n\tspinlock_t lock;\n\tstruct list_head xfers_list;\n\tstruct list_head free_descs_list;\n};\n\nstruct at_xdmac_layout;\n\nstruct at_xdmac {\n\tstruct dma_device dma;\n\tvoid *regs;\n\tstruct device *dev;\n\tint irq;\n\tstruct clk *clk;\n\tu32 save_gim;\n\tu32 save_gs;\n\tstruct dma_pool *at_xdmac_desc_pool;\n\tconst struct at_xdmac_layout *layout;\n\tstruct at_xdmac_chan chan[0];\n};\n\nstruct at_xdmac_lld {\n\tu32 mbr_nda;\n\tu32 mbr_ubc;\n\tu32 mbr_sa;\n\tu32 mbr_da;\n\tu32 mbr_cfg;\n\tu32 mbr_bc;\n\tu32 mbr_ds;\n\tu32 mbr_sus;\n\tu32 mbr_dus;\n};\n\nstruct at_xdmac_desc {\n\tstruct at_xdmac_lld lld;\n\tenum dma_transfer_direction direction;\n\tstruct dma_async_tx_descriptor tx_dma_desc;\n\tstruct list_head desc_node;\n\tbool active_xfer;\n\tunsigned int xfer_size;\n\tstruct list_head descs_list;\n\tstruct list_head xfer_node;\n\tlong: 32;\n};\n\nstruct at_xdmac_layout {\n\tu8 grs;\n\tu8 gws;\n\tu8 grws;\n\tu8 grwr;\n\tu8 gswr;\n\tu8 gsws;\n\tu8 gswf;\n\tu8 chan_cc_reg_base;\n\tbool sdif;\n\tbool axi_config;\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nstruct ata_cdl {\n\tu8 desc_log_buf[512];\n\tu8 ncq_sense_log_buf[1024];\n};\n\nstruct ata_cpr {\n\tu8 num;\n\tu8 num_storage_elements;\n\tlong: 32;\n\tu64 start_lba;\n\tu64 num_lbas;\n};\n\nstruct ata_cpr_log {\n\tu8 nr_cpr;\n\tlong: 32;\n\tstruct ata_cpr cpr[0];\n};\n\nstruct ata_dev_quirk_value {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 val;\n};\n\nstruct ata_dev_quirks_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 quirks;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tlong: 32;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tu64 quirks;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tlong: 32;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 gp_log_dir[512];\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tstruct ata_cpr_log *cpr_log;\n\tstruct ata_cdl *cdl;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tu8 sector_buf[512];\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst unsigned int *timeouts;\n};\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[16];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tlong: 32;\n\tu64 value;\n\tu8 cbl;\n\tu8 spd_limit;\n\tunsigned int xfer_mask;\n\tu64 quirk_on;\n\tu64 quirk_off;\n\tunsigned int pflags_on;\n\tu16 lflags_on;\n\tu16 lflags_off;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tunion {\n\t\tu8 error;\n\t\tu8 feature;\n\t};\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tunion {\n\t\tu8 status;\n\t\tu8 command;\n\t};\n\tu32 auxiliary;\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct scsi_cmnd;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tlong: 32;\n\tu64 qc_active;\n\tint nr_active_links;\n\tstruct work_struct deferred_qc_work;\n\tstruct ata_queued_cmd *deferred_qc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tlong: 32;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct delayed_work scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tunsigned int fastdrain_cnt;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nstruct ata_reset_operations {\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tvoid (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tvoid (*qc_ncq_fill_rtf)(struct ata_port *, u64);\n\tint (*cable_detect)(struct ata_port *);\n\tunsigned int (*mode_filter)(struct ata_device *, unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, __le16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tstruct ata_reset_operations reset;\n\tstruct ata_reset_operations pmp_reset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ps2dev;\n\ntypedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int);\n\ntypedef void (*ps2_receive_handler_t)(struct ps2dev *, u8);\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n\tps2_pre_receive_handler_t pre_receive_handler;\n\tps2_receive_handler_t receive_handler;\n};\n\nstruct vivaldi_data {\n\tu32 function_row_physmap[24];\n\tunsigned int num_function_row_keys;\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[16];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tstruct vivaldi_data vdata;\n};\n\nstruct atmel_dma_buffer {\n\tunsigned char *buf;\n\tdma_addr_t dma_addr;\n\tunsigned int dma_size;\n\tunsigned int ofs;\n};\n\nstruct atmel_hsmc_reg_layout;\n\nstruct atmel_ebi_caps;\n\nstruct atmel_ebi {\n\tstruct clk *clk;\n\tstruct regmap *regmap;\n\tstruct {\n\t\tstruct regmap *regmap;\n\t\tstruct clk *clk;\n\t\tconst struct atmel_hsmc_reg_layout *layout;\n\t} smc;\n\tstruct device *dev;\n\tconst struct atmel_ebi_caps *caps;\n\tstruct list_head devs;\n};\n\nstruct atmel_ebi_dev;\n\nstruct atmel_ebi_dev_config;\n\nstruct atmel_ebi_caps {\n\tunsigned int available_cs;\n\tunsigned int ebi_csa_offs;\n\tconst char *regmap_name;\n\tvoid (*get_config)(struct atmel_ebi_dev *, struct atmel_ebi_dev_config *);\n\tint (*xlate_config)(struct atmel_ebi_dev *, struct device_node *, struct atmel_ebi_dev_config *);\n\tvoid (*apply_config)(struct atmel_ebi_dev *, struct atmel_ebi_dev_config *);\n};\n\nstruct atmel_smc_cs_conf {\n\tu32 setup;\n\tu32 pulse;\n\tu32 cycle;\n\tu32 timings;\n\tu32 mode;\n};\n\nstruct atmel_ebi_dev_config {\n\tint cs;\n\tstruct atmel_smc_cs_conf smcconf;\n};\n\nstruct atmel_ebi_dev {\n\tstruct list_head node;\n\tstruct atmel_ebi *ebi;\n\tu32 mode;\n\tint numcs;\n\tstruct atmel_ebi_dev_config configs[0];\n};\n\nstruct atmel_ehci_priv {\n\tstruct clk *iclk;\n\tstruct clk *uclk;\n\tbool clocked;\n};\n\nstruct atmel_flexcom {\n\tvoid *base;\n\tu32 opmode;\n\tstruct clk *clk;\n};\n\nstruct atmel_group {\n\tconst char *name;\n\tu32 pin;\n};\n\nstruct nand_controller_ops;\n\nstruct nand_controller {\n\tstruct mutex lock;\n\tconst struct nand_controller_ops *ops;\n\tstruct {\n\t\tunsigned int data_only_read: 1;\n\t\tunsigned int cont_read: 1;\n\t} supported_op;\n\tbool controller_wp;\n};\n\nstruct atmel_nand_controller_caps;\n\nstruct atmel_pmecc;\n\nstruct atmel_nand_controller {\n\tstruct nand_controller base;\n\tconst struct atmel_nand_controller_caps *caps;\n\tstruct device *dev;\n\tstruct regmap *smc;\n\tstruct dma_chan *dmac;\n\tstruct atmel_pmecc *pmecc;\n\tstruct list_head chips;\n\tstruct clk *mck;\n};\n\nstruct atmel_nfc_op {\n\tu8 cs;\n\tu8 ncmds;\n\tu8 cmds[2];\n\tu8 naddrs;\n\tu8 addrs[5];\n\tenum atmel_nfc_data_xfer data;\n\tu32 wait;\n\tu32 errors;\n};\n\nstruct gen_pool;\n\nstruct atmel_hsmc_nand_controller {\n\tstruct atmel_nand_controller base;\n\tstruct {\n\t\tstruct gen_pool *pool;\n\t\tvoid *virt;\n\t\tdma_addr_t dma;\n\t} sram;\n\tconst struct atmel_hsmc_reg_layout *hsmc_layout;\n\tstruct regmap *io;\n\tstruct atmel_nfc_op op;\n\tstruct completion complete;\n\tu32 cfg;\n\tint irq;\n\tstruct clk *clk;\n};\n\nstruct atmel_hsmc_reg_layout {\n\tunsigned int timing_regs_offset;\n};\n\nstruct atmel_mci_dma {\n\tstruct dma_chan *chan;\n\tstruct dma_async_tx_descriptor *data_desc;\n};\n\nstruct mci_slot_pdata {\n\tunsigned int bus_width;\n\tstruct gpio_desc *detect_pin;\n\tstruct gpio_desc *wp_pin;\n\tbool non_removable;\n};\n\nstruct atmel_mci_caps {\n\tbool has_dma_conf_reg;\n\tbool has_pdc;\n\tbool has_cfg_reg;\n\tbool has_cstor_reg;\n\tbool has_highspeed;\n\tbool has_rwproof;\n\tbool has_odd_clk_div;\n\tbool has_bad_data_ordering;\n\tbool need_reset_after_xfer;\n\tbool need_blksz_mul_4;\n\tbool need_notbusy_for_read_ops;\n};\n\nstruct atmel_mci_slot;\n\nstruct mmc_request;\n\nstruct mmc_command;\n\nstruct mmc_data;\n\nstruct atmel_mci {\n\tspinlock_t lock;\n\tvoid *regs;\n\tstruct scatterlist *sg;\n\tunsigned int sg_len;\n\tunsigned int pio_offset;\n\tunsigned int *buffer;\n\tunsigned int buf_size;\n\tdma_addr_t buf_phys_addr;\n\tstruct atmel_mci_slot *cur_slot;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tunsigned int data_size;\n\tstruct atmel_mci_dma dma;\n\tstruct dma_chan *data_chan;\n\tstruct dma_slave_config dma_conf;\n\tu32 cmd_status;\n\tu32 data_status;\n\tu32 stop_cmdr;\n\tstruct work_struct bh_work;\n\tlong unsigned int pending_events;\n\tlong unsigned int completed_events;\n\tenum atmel_mci_state state;\n\tstruct list_head queue;\n\tbool need_clock_update;\n\tbool need_reset;\n\tstruct timer_list timer;\n\tu32 mode_reg;\n\tu32 cfg_reg;\n\tlong unsigned int bus_hz;\n\tlong unsigned int mapbase;\n\tstruct clk *mck;\n\tstruct device *dev;\n\tstruct mci_slot_pdata pdata[2];\n\tstruct atmel_mci_slot *slot[2];\n\tstruct atmel_mci_caps caps;\n\tu32 (*prepare_data)(struct atmel_mci *, struct mmc_data *);\n\tvoid (*submit_data)(struct atmel_mci *, struct mmc_data *);\n\tvoid (*stop_transfer)(struct atmel_mci *);\n};\n\nstruct mmc_host;\n\nstruct atmel_mci_slot {\n\tstruct mmc_host *mmc;\n\tstruct atmel_mci *host;\n\tu32 sdc_reg;\n\tu32 sdio_irq;\n\tstruct mmc_request *mrq;\n\tstruct list_head queue_node;\n\tunsigned int clock;\n\tlong unsigned int flags;\n\tstruct gpio_desc *detect_pin;\n\tstruct gpio_desc *wp_pin;\n\tstruct timer_list detect_timer;\n};\n\nstruct mtd_ecc_stats {\n\t__u32 corrected;\n\t__u32 failed;\n\t__u32 badblocks;\n\t__u32 bbtblocks;\n};\n\nstruct mtd_debug_info {\n\tstruct dentry *dfs_dir;\n};\n\nstruct mtd_part {\n\tstruct list_head node;\n\tu64 offset;\n\tu64 size;\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct mtd_master {\n\tstruct mutex partitions_lock;\n\tstruct mutex chrdev_lock;\n\tunsigned int suspended: 1;\n};\n\nstruct mtd_ooblayout_ops;\n\nstruct mtd_pairing_scheme;\n\nstruct mtd_erase_region_info;\n\nstruct erase_info;\n\nstruct mtd_oob_ops;\n\nstruct otp_info;\n\nstruct kvec;\n\nstruct mtd_info {\n\tu_char type;\n\tuint32_t flags;\n\tuint64_t size;\n\tuint32_t erasesize;\n\tuint32_t writesize;\n\tuint32_t writebufsize;\n\tuint32_t oobsize;\n\tuint32_t oobavail;\n\tunsigned int erasesize_shift;\n\tunsigned int writesize_shift;\n\tunsigned int erasesize_mask;\n\tunsigned int writesize_mask;\n\tunsigned int bitflip_threshold;\n\tconst char *name;\n\tint index;\n\tconst struct mtd_ooblayout_ops *ooblayout;\n\tconst struct mtd_pairing_scheme *pairing;\n\tunsigned int ecc_step_size;\n\tunsigned int ecc_strength;\n\tint numeraseregions;\n\tstruct mtd_erase_region_info *eraseregions;\n\tint (*_erase)(struct mtd_info *, struct erase_info *);\n\tint (*_point)(struct mtd_info *, loff_t, size_t, size_t *, void **, resource_size_t *);\n\tint (*_unpoint)(struct mtd_info *, loff_t, size_t);\n\tint (*_read)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_panic_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_read_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_write_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_get_fact_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_fact_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_get_user_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_lock_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_erase_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_writev)(struct mtd_info *, const struct kvec *, long unsigned int, loff_t, size_t *);\n\tvoid (*_sync)(struct mtd_info *);\n\tint (*_lock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_unlock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_is_locked)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_block_isreserved)(struct mtd_info *, loff_t);\n\tint (*_block_isbad)(struct mtd_info *, loff_t);\n\tint (*_block_markbad)(struct mtd_info *, loff_t);\n\tint (*_max_bad_blocks)(struct mtd_info *, loff_t, size_t);\n\tint (*_suspend)(struct mtd_info *);\n\tvoid (*_resume)(struct mtd_info *);\n\tvoid (*_reboot)(struct mtd_info *);\n\tint (*_get_device)(struct mtd_info *);\n\tvoid (*_put_device)(struct mtd_info *);\n\tbool oops_panic_write;\n\tstruct notifier_block reboot_notifier;\n\tstruct mtd_ecc_stats ecc_stats;\n\tint subpage_sft;\n\tvoid *priv;\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct kref refcnt;\n\tstruct mtd_debug_info dbg;\n\tstruct nvmem_device *nvmem;\n\tstruct nvmem_device *otp_user_nvmem;\n\tstruct nvmem_device *otp_factory_nvmem;\n\tstruct mtd_info *parent;\n\tstruct list_head partitions;\n\tstruct mtd_part part;\n\tstruct mtd_master master;\n\tlong: 32;\n};\n\nstruct nand_memory_organization {\n\tunsigned int bits_per_cell;\n\tunsigned int pagesize;\n\tunsigned int oobsize;\n\tunsigned int pages_per_eraseblock;\n\tunsigned int eraseblocks_per_lun;\n\tunsigned int max_bad_eraseblocks_per_lun;\n\tunsigned int planes_per_lun;\n\tunsigned int luns_per_target;\n\tunsigned int ntargets;\n};\n\nstruct nand_ecc_props {\n\tenum nand_ecc_engine_type engine_type;\n\tenum nand_ecc_placement placement;\n\tenum nand_ecc_algo algo;\n\tunsigned int strength;\n\tunsigned int step_size;\n\tunsigned int flags;\n};\n\nstruct nand_ecc_context {\n\tstruct nand_ecc_props conf;\n\tunsigned int nsteps;\n\tunsigned int total;\n\tvoid *priv;\n};\n\nstruct nand_ecc_engine;\n\nstruct nand_ecc {\n\tstruct nand_ecc_props defaults;\n\tstruct nand_ecc_props requirements;\n\tstruct nand_ecc_props user_conf;\n\tstruct nand_ecc_context ctx;\n\tstruct nand_ecc_engine *ondie_engine;\n\tstruct nand_ecc_engine *engine;\n};\n\nstruct nand_row_converter {\n\tunsigned int lun_addr_shift;\n\tunsigned int eraseblock_addr_shift;\n};\n\nstruct nand_bbt {\n\tlong unsigned int *cache;\n};\n\nstruct nand_ops;\n\nstruct nand_device {\n\tstruct mtd_info mtd;\n\tstruct nand_memory_organization memorg;\n\tstruct nand_ecc ecc;\n\tstruct nand_row_converter rowconv;\n\tstruct nand_bbt bbt;\n\tconst struct nand_ops *ops;\n};\n\nstruct nand_id {\n\tu8 data[8];\n\tint len;\n};\n\nstruct onfi_params;\n\nstruct nand_parameters {\n\tconst char *model;\n\tbool supports_set_get_features;\n\tbool supports_read_cache;\n\tlong unsigned int set_feature_list[8];\n\tlong unsigned int get_feature_list[8];\n\tstruct onfi_params *onfi;\n};\n\nstruct nand_manufacturer_desc;\n\nstruct nand_manufacturer {\n\tconst struct nand_manufacturer_desc *desc;\n\tvoid *priv;\n};\n\nstruct nand_chip;\n\nstruct nand_interface_config;\n\nstruct nand_chip_ops {\n\tint (*suspend)(struct nand_chip *);\n\tvoid (*resume)(struct nand_chip *);\n\tint (*lock_area)(struct nand_chip *, loff_t, uint64_t);\n\tint (*unlock_area)(struct nand_chip *, loff_t, uint64_t);\n\tint (*setup_read_retry)(struct nand_chip *, int);\n\tint (*choose_interface_config)(struct nand_chip *, struct nand_interface_config *);\n};\n\nstruct nand_legacy {\n\tvoid *IO_ADDR_R;\n\tvoid *IO_ADDR_W;\n\tvoid (*select_chip)(struct nand_chip *, int);\n\tu8 (*read_byte)(struct nand_chip *);\n\tvoid (*write_byte)(struct nand_chip *, u8);\n\tvoid (*write_buf)(struct nand_chip *, const u8 *, int);\n\tvoid (*read_buf)(struct nand_chip *, u8 *, int);\n\tvoid (*cmd_ctrl)(struct nand_chip *, int, unsigned int);\n\tvoid (*cmdfunc)(struct nand_chip *, unsigned int, int, int);\n\tint (*dev_ready)(struct nand_chip *);\n\tint (*waitfunc)(struct nand_chip *);\n\tint (*block_bad)(struct nand_chip *, loff_t);\n\tint (*block_markbad)(struct nand_chip *, loff_t);\n\tint (*set_features)(struct nand_chip *, int, u8 *);\n\tint (*get_features)(struct nand_chip *, int, u8 *);\n\tint chip_delay;\n\tstruct nand_controller dummy_controller;\n};\n\nstruct nand_ecc_ctrl {\n\tenum nand_ecc_engine_type engine_type;\n\tenum nand_ecc_placement placement;\n\tenum nand_ecc_algo algo;\n\tint steps;\n\tint size;\n\tint bytes;\n\tint total;\n\tint strength;\n\tint prepad;\n\tint postpad;\n\tunsigned int options;\n\tu8 *calc_buf;\n\tu8 *code_buf;\n\tvoid (*hwctl)(struct nand_chip *, int);\n\tint (*calculate)(struct nand_chip *, const uint8_t *, uint8_t *);\n\tint (*correct)(struct nand_chip *, uint8_t *, uint8_t *, uint8_t *);\n\tint (*read_page_raw)(struct nand_chip *, uint8_t *, int, int);\n\tint (*write_page_raw)(struct nand_chip *, const uint8_t *, int, int);\n\tint (*read_page)(struct nand_chip *, uint8_t *, int, int);\n\tint (*read_subpage)(struct nand_chip *, uint32_t, uint32_t, uint8_t *, int);\n\tint (*write_subpage)(struct nand_chip *, uint32_t, uint32_t, const uint8_t *, int, int);\n\tint (*write_page)(struct nand_chip *, const uint8_t *, int, int);\n\tint (*write_oob_raw)(struct nand_chip *, int);\n\tint (*read_oob_raw)(struct nand_chip *, int);\n\tint (*read_oob)(struct nand_chip *, int);\n\tint (*write_oob)(struct nand_chip *, int);\n};\n\nstruct nand_bbt_descr;\n\nstruct nand_secure_region;\n\nstruct nand_chip {\n\tstruct nand_device base;\n\tstruct nand_id id;\n\tstruct nand_parameters parameters;\n\tstruct nand_manufacturer manufacturer;\n\tstruct nand_chip_ops ops;\n\tstruct nand_legacy legacy;\n\tunsigned int options;\n\tconst struct nand_interface_config *current_interface_config;\n\tstruct nand_interface_config *best_interface_config;\n\tunsigned int bbt_erase_shift;\n\tunsigned int bbt_options;\n\tunsigned int badblockpos;\n\tunsigned int badblockbits;\n\tstruct nand_bbt_descr *bbt_td;\n\tstruct nand_bbt_descr *bbt_md;\n\tstruct nand_bbt_descr *badblock_pattern;\n\tu8 *bbt;\n\tunsigned int page_shift;\n\tunsigned int phys_erase_shift;\n\tunsigned int chip_shift;\n\tunsigned int pagemask;\n\tunsigned int subpagesize;\n\tu8 *data_buf;\n\tu8 *oob_poi;\n\tstruct {\n\t\tunsigned int bitflips;\n\t\tint page;\n\t} pagecache;\n\tlong unsigned int buf_align;\n\tstruct mutex lock;\n\tunsigned int suspended: 1;\n\twait_queue_head_t resume_wq;\n\tint cur_cs;\n\tint read_retries;\n\tstruct nand_secure_region *secure_regions;\n\tu8 nr_secure_regions;\n\tstruct {\n\t\tbool ongoing;\n\t\tunsigned int first_page;\n\t\tunsigned int pause_page;\n\t\tunsigned int last_page;\n\t} cont_read;\n\tstruct nand_controller *controller;\n\tstruct nand_ecc_ctrl ecc;\n\tvoid *priv;\n};\n\nstruct atmel_nand_rb {\n\tenum atmel_nand_rb_type type;\n\tunion {\n\t\tstruct gpio_desc *gpio;\n\t\tint id;\n\t};\n};\n\nstruct atmel_nand_cs {\n\tint id;\n\tstruct atmel_nand_rb rb;\n\tstruct gpio_desc *csgpio;\n\tstruct {\n\t\tvoid *virt;\n\t\tdma_addr_t dma;\n\t} io;\n\tstruct atmel_smc_cs_conf smcconf;\n};\n\nstruct atmel_pmecc_user;\n\nstruct atmel_nand {\n\tstruct list_head node;\n\tstruct device *dev;\n\tlong: 32;\n\tstruct nand_chip base;\n\tstruct atmel_nand_cs *activecs;\n\tstruct atmel_pmecc_user *pmecc;\n\tstruct gpio_desc *cdgpio;\n\tint numcs;\n\tstruct atmel_nand_cs cs[0];\n};\n\nstruct atmel_nand_controller_ops;\n\nstruct atmel_nand_controller_caps {\n\tbool has_dma;\n\tbool legacy_of_bindings;\n\tu32 ale_offs;\n\tu32 cle_offs;\n\tconst char *ebi_csa_regmap_name;\n\tconst struct atmel_nand_controller_ops *ops;\n};\n\nstruct nand_operation;\n\nstruct atmel_nand_controller_ops {\n\tint (*probe)(struct platform_device *, const struct atmel_nand_controller_caps *);\n\tint (*remove)(struct atmel_nand_controller *);\n\tvoid (*nand_init)(struct atmel_nand_controller *, struct atmel_nand *);\n\tint (*ecc_init)(struct nand_chip *);\n\tint (*setup_interface)(struct atmel_nand *, int, const struct nand_interface_config *);\n\tint (*exec_op)(struct atmel_nand *, const struct nand_operation *, bool);\n};\n\nstruct atmel_pin {\n\tunsigned int pin_id;\n\tunsigned int mux;\n\tunsigned int ioset;\n\tunsigned int bank;\n\tunsigned int line;\n\tconst char *device;\n};\n\nstruct atmel_pioctrl {\n\tvoid *reg_base;\n\tstruct clk *clk;\n\tunsigned int nbanks;\n\tstruct pinctrl_dev *pinctrl_dev;\n\tstruct atmel_group *groups;\n\tconst char * const *group_names;\n\tstruct atmel_pin **pins;\n\tunsigned int npins;\n\tstruct gpio_chip *gpio_chip;\n\tstruct irq_domain *irq_domain;\n\tint *irqs;\n\tunsigned int *pm_wakeup_sources;\n\tstruct {\n\t\tu32 imr;\n\t\tu32 odsr;\n\t\tu32 cfgr[32];\n\t} *pm_suspend_backup;\n\tstruct device *dev;\n\tstruct device_node *node;\n\tunsigned int slew_rate_support;\n};\n\nstruct atmel_pioctrl_data {\n\tunsigned int nbanks;\n\tunsigned int last_bank_count;\n\tunsigned int slew_rate_support;\n};\n\nstruct atmel_pmecc_caps;\n\nstruct atmel_pmecc {\n\tstruct device *dev;\n\tconst struct atmel_pmecc_caps *caps;\n\tstruct {\n\t\tvoid *base;\n\t\tvoid *errloc;\n\t} regs;\n\tstruct mutex lock;\n};\n\nstruct atmel_pmecc_caps {\n\tconst int *strengths;\n\tint nstrengths;\n\tint el_offset;\n\tbool correct_erased_chunks;\n\tbool clk_ctrl;\n};\n\nstruct atmel_pmecc_gf_tables {\n\tu16 *alpha_to;\n\tu16 *index_of;\n};\n\nstruct atmel_pmecc_user_conf_cache {\n\tu32 cfg;\n\tu32 sarea;\n\tu32 saddr;\n\tu32 eaddr;\n};\n\nstruct atmel_pmecc_user {\n\tstruct atmel_pmecc_user_conf_cache cache;\n\tstruct atmel_pmecc *pmecc;\n\tconst struct atmel_pmecc_gf_tables *gf_tables;\n\tint eccbytes;\n\ts16 *partial_syn;\n\ts16 *si;\n\ts16 *lmu;\n\ts16 *smu;\n\ts32 *mu;\n\ts32 *dmu;\n\ts32 *delta;\n\tu32 isr;\n};\n\nstruct atmel_pmecc_user_req {\n\tint pagesize;\n\tint oobsize;\n\tstruct {\n\t\tint strength;\n\t\tint bytes;\n\t\tint sectorsize;\n\t\tint nsectors;\n\t\tint ooboffset;\n\t} ecc;\n};\n\nstruct atmel_smc_nand_ebi_csa_cfg;\n\nstruct atmel_smc_nand_controller {\n\tstruct atmel_nand_controller base;\n\tstruct regmap *ebi_csa_regmap;\n\tstruct atmel_smc_nand_ebi_csa_cfg *ebi_csa;\n};\n\nstruct atmel_smc_nand_ebi_csa_cfg {\n\tu32 offs;\n\tu32 nfd0_on_d16;\n};\n\nstruct atmel_smc_timing_xlate {\n\tconst char *name;\n\tint (*converter)(struct atmel_smc_cs_conf *, unsigned int, unsigned int);\n\tunsigned int shift;\n};\n\nstruct atmel_tcb_config;\n\nstruct atmel_tc {\n\tstruct platform_device *pdev;\n\tvoid *regs;\n\tint id;\n\tconst struct atmel_tcb_config *tcb_config;\n\tint irq[3];\n\tstruct clk *clk[3];\n\tstruct clk *slow_clk;\n\tstruct list_head node;\n\tbool allocated;\n};\n\nstruct atmel_tcb_config {\n\tsize_t counter_width;\n\tbool has_gclk;\n\tbool has_qdec;\n};\n\nstruct atmel_trng {\n\tstruct clk *clk;\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tbool has_half_rate;\n};\n\nstruct atmel_trng_data {\n\tbool has_half_rate;\n};\n\nstruct atmel_uart_char {\n\tu16 status;\n\tu16 ch;\n};\n\nstruct circ_buf {\n\tchar *buf;\n\tint head;\n\tint tail;\n};\n\nstruct mctrl_gpios;\n\nstruct atmel_uart_port {\n\tstruct uart_port uart;\n\tstruct clk *clk;\n\tstruct clk *gclk;\n\tint may_wakeup;\n\tu32 backup_imr;\n\tint break_active;\n\tbool use_dma_rx;\n\tbool use_pdc_rx;\n\tshort int pdc_rx_idx;\n\tstruct atmel_dma_buffer pdc_rx[2];\n\tbool use_dma_tx;\n\tbool use_pdc_tx;\n\tstruct atmel_dma_buffer pdc_tx;\n\tspinlock_t lock_tx;\n\tspinlock_t lock_rx;\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n\tstruct dma_async_tx_descriptor *desc_tx;\n\tstruct dma_async_tx_descriptor *desc_rx;\n\tdma_cookie_t cookie_tx;\n\tdma_cookie_t cookie_rx;\n\tdma_addr_t tx_phys;\n\tdma_addr_t rx_phys;\n\tstruct tasklet_struct tasklet_rx;\n\tstruct tasklet_struct tasklet_tx;\n\tatomic_t tasklet_shutdown;\n\tunsigned int irq_status_prev;\n\tunsigned int tx_len;\n\tstruct circ_buf rx_ring;\n\tstruct mctrl_gpios *gpios;\n\tu32 backup_mode;\n\tu32 backup_brgr;\n\tunsigned int tx_done_mask;\n\tu32 fifo_size;\n\tu32 rts_high;\n\tu32 rts_low;\n\tbool ms_irq_enabled;\n\tu32 rtor;\n\tbool is_usart;\n\tbool has_frac_baudrate;\n\tbool has_hw_timer;\n\tstruct timer_list uart_timer;\n\tbool tx_stopped;\n\tbool suspended;\n\tunsigned int pending;\n\tunsigned int pending_status;\n\tspinlock_t lock_suspended;\n\tbool hd_start_rx;\n\tunsigned int fidi_min;\n\tunsigned int fidi_max;\n\tstruct {\n\t\tu32 cr;\n\t\tu32 mr;\n\t\tu32 imr;\n\t\tu32 brgr;\n\t\tu32 rtor;\n\t\tu32 ttgr;\n\t\tu32 fmr;\n\t\tu32 fimr;\n\t} cache;\n\tint (*prepare_rx)(struct uart_port *);\n\tint (*prepare_tx)(struct uart_port *);\n\tvoid (*schedule_rx)(struct uart_port *);\n\tvoid (*schedule_tx)(struct uart_port *);\n\tvoid (*release_rx)(struct uart_port *);\n\tvoid (*release_tx)(struct uart_port *);\n\tlong: 32;\n};\n\nstruct bin_attribute;\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct auth_cred {\n\tconst struct cred *cred;\n\tconst char *principal;\n};\n\nstruct auth_ops;\n\nstruct auth_domain {\n\tstruct kref ref;\n\tstruct hlist_node hash;\n\tchar *name;\n\tstruct auth_ops *flavour;\n\tstruct callback_head callback_head;\n};\n\nstruct svc_rqst;\n\nstruct auth_ops {\n\tchar *name;\n\tstruct module *owner;\n\tint flavour;\n\tenum svc_auth_status (*accept)(struct svc_rqst *);\n\tint (*release)(struct svc_rqst *);\n\tvoid (*domain_release)(struct auth_domain *);\n\tenum svc_auth_status (*set_client)(struct svc_rqst *);\n\trpc_authflavor_t (*pseudoflavor)(struct svc_rqst *);\n};\n\nstruct auto_mode_param {\n\tint qp_type;\n};\n\nstruct autofs_dev_ioctl {\n\t__u32 ver_major;\n\t__u32 ver_minor;\n\t__u32 size;\n\t__s32 ioctlfd;\n\tunion {\n\t\tstruct args_protover protover;\n\t\tstruct args_protosubver protosubver;\n\t\tstruct args_openmount openmount;\n\t\tstruct args_ready ready;\n\t\tstruct args_fail fail;\n\t\tstruct args_setpipefd setpipefd;\n\t\tstruct args_timeout timeout;\n\t\tstruct args_requester requester;\n\t\tstruct args_expire expire;\n\t\tstruct args_askumount askumount;\n\t\tstruct args_ismountpoint ismountpoint;\n\t};\n\tchar path[0];\n};\n\nstruct autofs_fs_context {\n\tkuid_t uid;\n\tkgid_t gid;\n\tint pgrp;\n\tbool pgrp_set;\n};\n\nstruct autofs_sb_info;\n\nstruct autofs_info {\n\tstruct dentry *dentry;\n\tint flags;\n\tstruct completion expire_complete;\n\tstruct list_head active;\n\tstruct list_head expiring;\n\tstruct autofs_sb_info *sbi;\n\tlong unsigned int exp_timeout;\n\tlong unsigned int last_used;\n\tint count;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_packet_hdr {\n\tint proto_version;\n\tint type;\n};\n\nstruct autofs_packet_expire {\n\tstruct autofs_packet_hdr hdr;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_expire_multi {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_missing {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nunion autofs_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_packet_missing missing;\n\tstruct autofs_packet_expire expire;\n\tstruct autofs_packet_expire_multi expire_multi;\n};\n\nstruct super_block;\n\nstruct autofs_wait_queue;\n\nstruct autofs_sb_info {\n\tu32 magic;\n\tint pipefd;\n\tstruct file *pipe;\n\tstruct pid *oz_pgrp;\n\tu64 mnt_ns_id;\n\tint version;\n\tint sub_version;\n\tint min_proto;\n\tint max_proto;\n\tunsigned int flags;\n\tlong unsigned int exp_timeout;\n\tunsigned int type;\n\tstruct super_block *sb;\n\tstruct mutex wq_mutex;\n\tstruct mutex pipe_mutex;\n\tspinlock_t fs_lock;\n\tstruct autofs_wait_queue *queues;\n\tspinlock_t lookup_lock;\n\tstruct list_head active_list;\n\tstruct list_head expiring_list;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct autofs_v5_packet {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\t__u32 dev;\n\t__u64 ino;\n\t__u32 uid;\n\t__u32 gid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 len;\n\tchar name[256];\n\tlong: 32;\n};\n\ntypedef struct autofs_v5_packet autofs_packet_expire_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_expire_indirect_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_indirect_t;\n\nunion autofs_v5_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_v5_packet v5_packet;\n\tautofs_packet_missing_indirect_t missing_indirect;\n\tautofs_packet_expire_indirect_t expire_indirect;\n\tautofs_packet_missing_direct_t missing_direct;\n\tautofs_packet_expire_direct_t expire_direct;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n\tlong: 32;\n};\n\nstruct autofs_wait_queue {\n\twait_queue_head_t queue;\n\tstruct autofs_wait_queue *next;\n\tautofs_wqt_t wait_queue_token;\n\tlong: 32;\n\tstruct qstr name;\n\tu32 offset;\n\tu32 dev;\n\tu64 ino;\n\tkuid_t uid;\n\tkgid_t gid;\n\tpid_t pid;\n\tpid_t tgid;\n\tint status;\n\tunsigned int wait_ctr;\n};\n\nstruct aux_clk_masks {\n\tu32 eq_sel_mask;\n\tu32 eq_sel_shift;\n\tu32 eq1_mask;\n\tu32 eq2_mask;\n\tu32 xscale_sel_mask;\n\tu32 xscale_sel_shift;\n\tu32 yscale_sel_mask;\n\tu32 yscale_sel_shift;\n\tu32 enable_bit;\n};\n\nstruct aux_rate_tbl {\n\tu16 xscale;\n\tu16 yscale;\n\tu8 eq;\n};\n\nstruct user_vfp {\n\tlong long unsigned int fpregs[32];\n\tlong unsigned int fpscr;\n\tlong: 32;\n};\n\nstruct user_vfp_exc {\n\tlong unsigned int fpexc;\n\tlong unsigned int fpinst;\n\tlong unsigned int fpinst2;\n};\n\nstruct vfp_sigframe {\n\tlong unsigned int magic;\n\tlong unsigned int size;\n\tstruct user_vfp ufp;\n\tstruct user_vfp_exc ufp_exc;\n\tlong: 32;\n};\n\nstruct aux_sigframe {\n\tstruct vfp_sigframe vfp;\n\tlong unsigned int end_magic;\n\tlong: 32;\n};\n\nstruct auxiliary_device {\n\tstruct device dev;\n\tconst char *name;\n\tu32 id;\n\tstruct {\n\t\tstruct xarray irqs;\n\t\tstruct mutex lock;\n\t\tbool irq_dir_exists;\n\t} sysfs;\n\tlong: 32;\n};\n\nstruct auxiliary_device_id {\n\tchar name[40];\n\tkernel_ulong_t driver_data;\n};\n\nstruct auxiliary_driver {\n\tint (*probe)(struct auxiliary_device *, const struct auxiliary_device_id *);\n\tvoid (*remove)(struct auxiliary_device *);\n\tvoid (*shutdown)(struct auxiliary_device *);\n\tint (*suspend)(struct auxiliary_device *, pm_message_t);\n\tint (*resume)(struct auxiliary_device *);\n\tconst char *name;\n\tstruct device_driver driver;\n\tconst struct auxiliary_device_id *id_table;\n};\n\nstruct auxiliary_irq_info {\n\tstruct device_attribute sysfs_attr;\n\tchar name[11];\n};\n\nstruct ave_desc {\n\tstruct sk_buff *skbs;\n\tdma_addr_t skbs_dma;\n\tsize_t skbs_dmalen;\n};\n\nstruct ave_desc_info {\n\tu32 ndesc;\n\tu32 daddr;\n\tu32 proc_idx;\n\tu32 done_idx;\n\tstruct ave_desc *desc;\n};\n\nstruct ave_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64 packets;\n\tu64 bytes;\n\tu64 errors;\n\tu64 dropped;\n\tu64 collisions;\n\tu64 fifo_errors;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct napi_config;\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n\tlong: 32;\n};\n\nstruct ave_soc_data;\n\nstruct ave_private {\n\tvoid *base;\n\tint irq;\n\tint phy_id;\n\tunsigned int desc_size;\n\tu32 msg_enable;\n\tint nclks;\n\tstruct clk *clk[4];\n\tint nrsts;\n\tstruct reset_control *rst[2];\n\tphy_interface_t phy_mode;\n\tstruct phy_device *phydev;\n\tstruct mii_bus *mdio;\n\tstruct regmap *regmap;\n\tunsigned int pinmode_mask;\n\tunsigned int pinmode_val;\n\tu32 wolopts;\n\tstruct ave_stats stats_rx;\n\tstruct ave_stats stats_tx;\n\tstruct net_device *ndev;\n\tlong: 32;\n\tstruct napi_struct napi_rx;\n\tstruct napi_struct napi_tx;\n\tstruct ave_desc_info rx;\n\tstruct ave_desc_info tx;\n\tint pause_auto;\n\tint pause_rx;\n\tint pause_tx;\n\tconst struct ave_soc_data *data;\n};\n\nstruct ave_soc_data {\n\tbool is_desc_64bit;\n\tconst char *clock_names[4];\n\tconst char *reset_names[2];\n\tint (*get_pinmode)(struct ave_private *, phy_interface_t, u32);\n};\n\nstruct ax88172_int_data {\n\t__le16 res1;\n\tu8 link;\n\t__le16 res2;\n\tu8 status;\n\t__le16 res3;\n} __attribute__((packed));\n\nstruct ax88172a_private {\n\tstruct mii_bus *mdio;\n\tstruct phy_device *phydev;\n\tchar phy_name[64];\n\tu8 phy_addr;\n\tu16 oldmode;\n\tint use_embdphy;\n\tstruct asix_rx_fixup_info rx_fixup_info;\n};\n\nstruct ax88179_data {\n\tu8 eee_enabled;\n\tu8 eee_active;\n\tu16 rxctl;\n\tu8 in_pm;\n\tu32 wol_supported;\n\tu32 wolopts;\n\tu8 disconnecting;\n};\n\nstruct ax88179_int_data {\n\t__le32 intdata1;\n\t__le32 intdata2;\n};\n\nstruct mfd_cell;\n\nstruct regmap_irq_chip;\n\nstruct axp20x_dev {\n\tstruct device *dev;\n\tint irq;\n\tlong unsigned int irq_flags;\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip_data *regmap_irqc;\n\tenum axp20x_variants variant;\n\tint nr_cells;\n\tconst struct mfd_cell *cells;\n\tconst struct regmap_config *regmap_cfg;\n\tconst struct regmap_irq_chip *regmap_irq_chip;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\tlong: 32;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n\tlong: 32;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct backing_dev_info;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tlong: 32;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tlong: 32;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n\tlong: 32;\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tlong: 32;\n\tloff_t prev_pos;\n};\n\nstruct file_operations;\n\nstruct fown_struct;\n\nstruct hlist_head;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tlong: 32;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n\tlong: 32;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backlight_properties {\n\tint brightness;\n\tint max_brightness;\n\tint power;\n\tenum backlight_type type;\n\tunsigned int state;\n\tenum backlight_scale scale;\n};\n\nstruct backlight_ops;\n\nstruct backlight_device {\n\tstruct backlight_properties props;\n\tstruct mutex update_lock;\n\tstruct mutex ops_lock;\n\tconst struct backlight_ops *ops;\n\tstruct list_head entry;\n\tlong: 32;\n\tstruct device dev;\n\tint use_count;\n\tlong: 32;\n};\n\nstruct backlight_ops {\n\tunsigned int options;\n\tint (*update_status)(struct backlight_device *);\n\tint (*get_brightness)(struct backlight_device *);\n\tbool (*controls_device)(struct backlight_device *, struct device *);\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n\tlong: 32;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct bam_desc_hw {\n\t__le32 addr;\n\t__le16 size;\n\t__le16 flags;\n};\n\nstruct bam_async_desc {\n\tstruct virt_dma_desc vd;\n\tu32 num_desc;\n\tu32 xfer_len;\n\tu16 flags;\n\tstruct bam_desc_hw *curr_desc;\n\tstruct list_head desc_node;\n\tenum dma_transfer_direction dir;\n\tsize_t length;\n\tstruct bam_desc_hw desc[0];\n};\n\nstruct bam_device;\n\nstruct bam_chan {\n\tstruct virt_dma_chan vc;\n\tstruct bam_device *bdev;\n\tu32 id;\n\tstruct dma_slave_config slave;\n\tstruct bam_desc_hw *fifo_virt;\n\tdma_addr_t fifo_phys;\n\tshort unsigned int head;\n\tshort unsigned int tail;\n\tunsigned int initialized;\n\tunsigned int paused;\n\tunsigned int reconfigure;\n\tstruct list_head desc_list;\n\tstruct list_head node;\n};\n\nstruct reg_offset_data;\n\nstruct bam_device {\n\tvoid *regs;\n\tstruct device *dev;\n\tstruct dma_device common;\n\tstruct bam_chan *channels;\n\tu32 num_channels;\n\tu32 num_ees;\n\tu32 ee;\n\tbool controlled_remotely;\n\tbool powered_remotely;\n\tu32 active_channels;\n\tconst struct reg_offset_data *layout;\n\tstruct clk *bamclk;\n\tint irq;\n\tstruct tasklet_struct task;\n};\n\nstruct bat_response {\n\tu8 event_type;\n\tu8 length;\n\tu8 sub_type;\n\tu8 status;\n\tunion {\n\t\tchar plc[30];\n\t\tu16 plu;\n\t\ts16 pls;\n\t};\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct local_lock {};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct mdiobb_ops;\n\nstruct mdiobb_ctrl {\n\tconst struct mdiobb_ops *ops;\n\tunsigned int override_op_c22;\n\tu8 op_c22_read;\n\tu8 op_c22_write;\n};\n\nstruct bb_info {\n\tvoid (*set_gate)(void *);\n\tstruct mdiobb_ctrl ctrl;\n\tvoid *addr;\n};\n\nstruct gf_poly;\n\nstruct bch_control {\n\tunsigned int m;\n\tunsigned int n;\n\tunsigned int t;\n\tunsigned int ecc_bits;\n\tunsigned int ecc_bytes;\n\tuint16_t *a_pow_tab;\n\tuint16_t *a_log_tab;\n\tuint32_t *mod8_tab;\n\tuint32_t *ecc_buf;\n\tuint32_t *ecc_buf2;\n\tunsigned int *xi_tab;\n\tunsigned int *syn;\n\tint *cache;\n\tstruct gf_poly *elp;\n\tstruct gf_poly *poly_2t[4];\n\tbool swap_bits;\n};\n\nstruct bch_geometry {\n\tunsigned int gf_len;\n\tunsigned int ecc_strength;\n\tunsigned int page_size;\n\tunsigned int metadata_size;\n\tunsigned int ecc0_chunk_size;\n\tunsigned int eccn_chunk_size;\n\tunsigned int ecc_chunk_count;\n\tunsigned int payload_size;\n\tunsigned int auxiliary_size;\n\tunsigned int auxiliary_status_offset;\n\tunsigned int block_mark_byte_offset;\n\tunsigned int block_mark_bit_offset;\n\tunsigned int ecc_for_meta;\n};\n\nstruct bcm281xx_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tconst unsigned int ngroups;\n};\n\nstruct bcm281xx_pinctrl_info;\n\nstruct bcm281xx_pinctrl_data {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tstruct regmap *regmap;\n\tconst struct bcm281xx_pinctrl_info *info;\n};\n\nstruct bcm281xx_pinctrl_info {\n\tenum bcm281xx_pinctrl_type device_type;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct bcm281xx_pin_function *functions;\n\tunsigned int nfunctions;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct bcm2835_dma_cb;\n\nstruct bcm2835_cb_entry {\n\tstruct bcm2835_dma_cb *cb;\n\tdma_addr_t paddr;\n};\n\nstruct bcm2835_desc;\n\nstruct bcm2835_chan {\n\tstruct virt_dma_chan vc;\n\tstruct dma_slave_config cfg;\n\tunsigned int dreq;\n\tint ch;\n\tstruct bcm2835_desc *desc;\n\tstruct dma_pool *cb_pool;\n\tvoid *chan_base;\n\tint irq_number;\n\tunsigned int irq_flags;\n\tbool is_lite_channel;\n};\n\nstruct bcm2835_cprman;\n\nstruct bcm2835_clk_desc {\n\tstruct clk_hw * (*clk_register)(struct bcm2835_cprman *, const void *);\n\tunsigned int supported;\n\tconst void *data;\n};\n\nstruct bcm2835_clock_data;\n\nstruct bcm2835_clock {\n\tstruct clk_hw hw;\n\tstruct bcm2835_cprman *cprman;\n\tconst struct bcm2835_clock_data *data;\n};\n\nstruct bcm2835_clock_data {\n\tconst char *name;\n\tconst char * const *parents;\n\tint num_mux_parents;\n\tunsigned int set_rate_parent;\n\tu32 ctl_reg;\n\tu32 div_reg;\n\tu32 int_bits;\n\tu32 frac_bits;\n\tu32 flags;\n\tbool is_vpu_clock;\n\tbool is_mash_clock;\n\tbool low_jitter;\n\tu32 tcnt_mux;\n\tbool round_up;\n};\n\nstruct clk_hw_onecell_data {\n\tunsigned int num;\n\tstruct clk_hw *hws[0];\n};\n\nstruct bcm2835_cprman {\n\tstruct device *dev;\n\tvoid *regs;\n\tspinlock_t regs_lock;\n\tunsigned int soc;\n\tconst char *real_parent_names[7];\n\tstruct clk_hw_onecell_data onecell;\n};\n\nstruct bcm2835_desc {\n\tstruct bcm2835_chan *c;\n\tstruct virt_dma_desc vd;\n\tenum dma_transfer_direction dir;\n\tunsigned int frames;\n\tsize_t size;\n\tbool cyclic;\n\tstruct bcm2835_cb_entry cb_list[0];\n};\n\nstruct bcm2835_dma_cb {\n\tuint32_t info;\n\tuint32_t src;\n\tuint32_t dst;\n\tuint32_t length;\n\tuint32_t stride;\n\tuint32_t next;\n\tuint32_t pad[2];\n};\n\nstruct bcm2835_dmadev {\n\tstruct dma_device ddev;\n\tvoid *base;\n\tdma_addr_t zero_page;\n};\n\nstruct bcm2835_gate_data {\n\tconst char *name;\n\tconst char *parent;\n\tu32 ctl_reg;\n};\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct bcm2835_host {\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tvoid *ioaddr;\n\tu32 phys_addr;\n\tstruct clk *clk;\n\tstruct platform_device *pdev;\n\tunsigned int clock;\n\tunsigned int max_clk;\n\tstruct work_struct dma_work;\n\tstruct delayed_work timeout_work;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int blocks;\n\tint irq;\n\tu32 ns_per_fifo_word;\n\tu32 hcfg;\n\tu32 cdiv;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tbool data_complete: 1;\n\tbool use_busy: 1;\n\tbool use_sbc: 1;\n\tbool irq_block;\n\tbool irq_busy;\n\tbool irq_data;\n\tstruct dma_chan *dma_chan_rxtx;\n\tstruct dma_chan *dma_chan;\n\tstruct dma_slave_config dma_cfg_rx;\n\tstruct dma_slave_config dma_cfg_tx;\n\tstruct dma_async_tx_descriptor *dma_desc;\n\tu32 dma_dir;\n\tu32 drain_words;\n\tstruct page *drain_page;\n\tu32 drain_offset;\n\tbool use_dma;\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tlong: 32;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n\tstruct regulator *bus_regulator;\n\tstruct dentry *debugfs;\n\tlong unsigned int addrs_in_instantiation[4];\n};\n\nstruct i2c_msg;\n\nstruct bcm2835_i2c_dev {\n\tstruct device *dev;\n\tvoid *regs;\n\tint irq;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tstruct completion completion;\n\tstruct i2c_msg *curr_msg;\n\tstruct clk *bus_clk;\n\tint num_msgs;\n\tu32 msg_err;\n\tu8 *msg_buf;\n\tsize_t msg_buf_remaining;\n};\n\nstruct mbox_chan_ops;\n\nstruct mbox_chan;\n\nstruct fwnode_reference_args;\n\nstruct mbox_controller {\n\tstruct device *dev;\n\tconst struct mbox_chan_ops *ops;\n\tstruct mbox_chan *chans;\n\tint num_chans;\n\tbool txdone_irq;\n\tbool txdone_poll;\n\tunsigned int txpoll_period;\n\tstruct mbox_chan * (*fw_xlate)(struct mbox_controller *, const struct fwnode_reference_args *);\n\tstruct mbox_chan * (*of_xlate)(struct mbox_controller *, const struct of_phandle_args *);\n\tstruct hrtimer poll_hrt;\n\tspinlock_t poll_hrt_lock;\n\tstruct list_head node;\n\tlong: 32;\n};\n\nstruct bcm2835_mbox {\n\tvoid *regs;\n\tspinlock_t lock;\n\tstruct mbox_controller controller;\n};\n\nstruct pinctrl_ops;\n\nstruct pinmux_ops;\n\nstruct pinconf_ops;\n\nstruct pinconf_generic_params;\n\nstruct pin_config_item;\n\nstruct pinctrl_desc {\n\tconst char *name;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct pinctrl_ops *pctlops;\n\tconst struct pinmux_ops *pmxops;\n\tconst struct pinconf_ops *confops;\n\tstruct module *owner;\n\tunsigned int num_custom_params;\n\tconst struct pinconf_generic_params *custom_params;\n\tconst struct pin_config_item *custom_conf_items;\n\tbool link_consumers;\n};\n\nstruct bcm2835_pinctrl {\n\tstruct device *dev;\n\tvoid *base;\n\tint *wake_irq;\n\tlong unsigned int enabled_irq_map[2];\n\tunsigned int irq_type[58];\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct pinctrl_gpio_range gpio_range;\n\traw_spinlock_t irq_lock[2];\n\tspinlock_t fsel_lock;\n};\n\nstruct bcm2835_pll_data;\n\nstruct bcm2835_pll {\n\tstruct clk_hw hw;\n\tstruct bcm2835_cprman *cprman;\n\tconst struct bcm2835_pll_data *data;\n};\n\nstruct bcm2835_pll_ana_bits {\n\tu32 mask0;\n\tu32 set0;\n\tu32 mask1;\n\tu32 set1;\n\tu32 mask3;\n\tu32 set3;\n\tu32 fb_prediv_mask;\n};\n\nstruct bcm2835_pll_data {\n\tconst char *name;\n\tu32 cm_ctrl_reg;\n\tu32 a2w_ctrl_reg;\n\tu32 frac_reg;\n\tu32 ana_reg_base;\n\tu32 reference_enable_mask;\n\tu32 lock_mask;\n\tu32 flags;\n\tconst struct bcm2835_pll_ana_bits *ana;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int max_fb_rate;\n};\n\nstruct clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu16 flags;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct bcm2835_pll_divider_data;\n\nstruct bcm2835_pll_divider {\n\tstruct clk_divider div;\n\tstruct bcm2835_cprman *cprman;\n\tconst struct bcm2835_pll_divider_data *data;\n};\n\nstruct bcm2835_pll_divider_data {\n\tconst char *name;\n\tconst char *source_pll;\n\tu32 cm_reg;\n\tu32 a2w_reg;\n\tu32 load_mask;\n\tu32 hold_mask;\n\tu32 fixed_divider;\n\tu32 flags;\n};\n\nstruct bcm2835_pm {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *asb;\n\tvoid *rpivid_asb;\n};\n\ntypedef struct generic_pm_domain * (*genpd_xlate_t)(const struct of_phandle_args *, void *);\n\nstruct genpd_onecell_data {\n\tstruct generic_pm_domain **domains;\n\tunsigned int num_domains;\n\tgenpd_xlate_t xlate;\n};\n\nstruct bcm2835_power;\n\nstruct bcm2835_power_domain {\n\tstruct generic_pm_domain base;\n\tstruct bcm2835_power *power;\n\tu32 domain;\n\tstruct clk *clk;\n\tlong: 32;\n};\n\nstruct bcm2835_power {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *asb;\n\tvoid *rpivid_asb;\n\tstruct genpd_onecell_data pd_xlate;\n\tlong: 32;\n\tstruct bcm2835_power_domain domains[13];\n\tstruct reset_controller_dev reset;\n};\n\nstruct bcm2835_pwm {\n\tvoid *base;\n\tstruct clk *clk;\n\tlong unsigned int rate;\n};\n\nstruct bcm2835_rng_of_data {\n\tbool mask_interrupts;\n};\n\nstruct bcm2835_rng_priv {\n\tstruct hwrng rng;\n\tvoid *base;\n\tbool mask_interrupts;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n};\n\nstruct spi_transfer;\n\nstruct spi_controller;\n\nstruct bcm2835_spidev;\n\nstruct bcm2835_spi {\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct gpio_desc *cs_gpio;\n\tlong unsigned int clk_hz;\n\tint irq;\n\tstruct spi_transfer *tfr;\n\tstruct spi_controller *ctlr;\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tint tx_len;\n\tint rx_len;\n\tint tx_prologue;\n\tint rx_prologue;\n\tunsigned int tx_spillover;\n\tstruct dentry *debugfs_dir;\n\tlong: 32;\n\tu64 count_transfer_polling;\n\tu64 count_transfer_irq;\n\tu64 count_transfer_irq_after_polling;\n\tu64 count_transfer_dma;\n\tstruct bcm2835_spidev *target;\n\tunsigned int tx_dma_active;\n\tunsigned int rx_dma_active;\n\tstruct dma_async_tx_descriptor *fill_tx_desc;\n\tdma_addr_t fill_tx_addr;\n\tlong: 32;\n};\n\nstruct bcm2835_spidev {\n\tu32 prepare_cs;\n\tstruct dma_async_tx_descriptor *clear_rx_desc;\n\tdma_addr_t clear_rx_addr;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu32 clear_rx_cs;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bcm2835_timer {\n\tvoid *control;\n\tvoid *compare;\n\tint match_mask;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device evt;\n};\n\nstruct bcm2835_wdt {\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct bcm2835aux_data {\n\tstruct clk *clk;\n\tint line;\n\tu32 cntl;\n};\n\nstruct bcm2835aux_spi {\n\tvoid *regs;\n\tstruct clk *clk;\n\tint irq;\n\tu32 cntl[2];\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tint tx_len;\n\tint rx_len;\n\tint pending;\n\tu64 count_transfer_polling;\n\tu64 count_transfer_irq;\n\tu64 count_transfer_irq_after_poll;\n\tstruct dentry *debugfs_dir;\n\tlong: 32;\n};\n\nstruct bcm2836_arm_irqchip_intc {\n\tstruct irq_domain *domain;\n\tvoid *base;\n};\n\nstruct bcm47xx_wdt {\n\tu32 (*timer_set)(struct bcm47xx_wdt *, u32);\n\tu32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);\n\tu32 max_timer_ms;\n\tvoid *driver_data;\n\tstruct watchdog_device wdd;\n\tstruct timer_list soft_timer;\n\tatomic_t soft_ticks;\n};\n\nstruct bcm4908_enet_dma_ring_bd;\n\nstruct bcm4908_enet_dma_ring_slot;\n\nstruct bcm4908_enet_dma_ring {\n\tint is_tx;\n\tint read_idx;\n\tint write_idx;\n\tint length;\n\tu16 cfg_block;\n\tu16 st_ram_block;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tunion {\n\t\tvoid *cpu_addr;\n\t\tstruct bcm4908_enet_dma_ring_bd *buf_desc;\n\t};\n\tdma_addr_t dma_addr;\n\tstruct bcm4908_enet_dma_ring_slot *slots;\n\tlong: 32;\n};\n\nstruct bcm4908_enet {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tvoid *base;\n\tint irq_tx;\n\tstruct bcm4908_enet_dma_ring tx_ring;\n\tstruct bcm4908_enet_dma_ring rx_ring;\n};\n\nstruct bcm4908_enet_dma_ring_bd {\n\t__le32 ctl;\n\t__le32 addr;\n};\n\nstruct bcm4908_enet_dma_ring_slot {\n\tunion {\n\t\tvoid *buf;\n\t\tstruct sk_buff *skb;\n\t};\n\tunsigned int len;\n\tdma_addr_t dma_addr;\n};\n\nstruct bcm4908_pinctrl {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct mutex mutex;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_desc pctldesc;\n};\n\nstruct bcm4908_pinctrl_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tconst unsigned int num_groups;\n};\n\nstruct bcm4908_pinctrl_pin_setup;\n\nstruct bcm4908_pinctrl_grp {\n\tconst char *name;\n\tconst struct bcm4908_pinctrl_pin_setup *pins;\n\tconst unsigned int num_pins;\n};\n\nstruct bcm4908_pinctrl_pin_setup {\n\tunsigned int number;\n\tunsigned int function;\n};\n\nstruct bcm53573_ilp {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n};\n\nstruct bcm54616s_phy_priv {\n\tbool mode_1000bx_en;\n};\n\nstruct bcm_ptp_private;\n\nstruct bcm54xx_phy_priv {\n\tu64 *stats;\n\tstruct bcm_ptp_private *ptp;\n\tint wake_irq;\n\tbool wake_irq_enabled;\n\tbool brr_mode;\n};\n\nstruct bcm590xx {\n\tstruct device *dev;\n\tstruct i2c_client *i2c_pri;\n\tstruct i2c_client *i2c_sec;\n\tstruct regmap *regmap_pri;\n\tstruct regmap *regmap_sec;\n\tu8 pmu_id;\n\tu8 rev_digital;\n\tu8 rev_analog;\n};\n\nstruct bcm590xx_reg_data;\n\nstruct bcm590xx_reg {\n\tstruct bcm590xx *mfd;\n\tunsigned int n_regulators;\n\tconst struct bcm590xx_reg_data *regs;\n};\n\nstruct bcm590xx_reg_data {\n\tenum bcm590xx_reg_type type;\n\tenum bcm590xx_regmap_type regmap;\n\tconst struct regulator_desc desc;\n};\n\nstruct led_pattern;\n\nstruct led_trigger;\n\nstruct led_hw_trigger_type;\n\nstruct led_classdev {\n\tconst char *name;\n\tunsigned int brightness;\n\tunsigned int max_brightness;\n\tunsigned int color;\n\tint flags;\n\tlong unsigned int work_flags;\n\tvoid (*brightness_set)(struct led_classdev *, enum led_brightness);\n\tint (*brightness_set_blocking)(struct led_classdev *, enum led_brightness);\n\tenum led_brightness (*brightness_get)(struct led_classdev *);\n\tint (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *);\n\tint (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int);\n\tint (*pattern_clear)(struct led_classdev *);\n\tstruct device *dev;\n\tconst struct attribute_group **groups;\n\tstruct list_head node;\n\tconst char *default_trigger;\n\tlong unsigned int blink_delay_on;\n\tlong unsigned int blink_delay_off;\n\tstruct timer_list blink_timer;\n\tint blink_brightness;\n\tint new_blink_brightness;\n\tvoid (*flash_resume)(struct led_classdev *);\n\tstruct workqueue_struct *wq;\n\tstruct work_struct set_brightness_work;\n\tint delayed_set_value;\n\tlong unsigned int delayed_delay_on;\n\tlong unsigned int delayed_delay_off;\n\tstruct rw_semaphore trigger_lock;\n\tstruct led_trigger *trigger;\n\tstruct list_head trig_list;\n\tvoid *trigger_data;\n\tbool activated;\n\tstruct led_hw_trigger_type *trigger_type;\n\tconst char *hw_control_trigger;\n\tint (*hw_control_is_supported)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_set)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_get)(struct led_classdev *, long unsigned int *);\n\tstruct device * (*hw_control_get_device)(struct led_classdev *);\n\tstruct mutex led_access;\n};\n\nstruct bcm63138_leds;\n\nstruct bcm63138_led {\n\tstruct bcm63138_leds *leds;\n\tstruct led_classdev cdev;\n\tu32 pin;\n\tbool active_low;\n};\n\nstruct bcm63138_leds {\n\tstruct device *dev;\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct bcm7038_l1_cpu;\n\nstruct bcm7038_l1_chip {\n\traw_spinlock_t lock;\n\tunsigned int n_words;\n\tstruct irq_domain *domain;\n\tstruct bcm7038_l1_cpu *cpus[16];\n\tstruct list_head list;\n\tu32 wake_mask[8];\n\tu32 irq_fwd_mask[8];\n\tu8 affinity[256];\n};\n\nstruct bcm7038_l1_cpu {\n\tvoid *map_base;\n\tu32 mask_cache[0];\n};\n\nstruct bcm7120_l2_intc_data;\n\nstruct bcm7120_l1_intc_data {\n\tstruct bcm7120_l2_intc_data *b;\n\tu32 irq_map_mask[4];\n};\n\nstruct bcm7120_l2_intc_data {\n\tunsigned int n_words;\n\tvoid *map_base[8];\n\tvoid *pair_base[4];\n\tint en_offset[4];\n\tint stat_offset[4];\n\tstruct irq_domain *domain;\n\tbool can_wake;\n\tu32 irq_fwd_mask[4];\n\tstruct bcm7120_l1_intc_data *l1_data;\n\tint num_parent_irqs;\n\tconst __be32 *map_mask_prop;\n};\n\nstruct bcm74110_mbox_chan;\n\nstruct bcm74110_mbox {\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tint tx_chan;\n\tint rx_chan;\n\tint rx_irq;\n\tstruct list_head rx_svc_init_list;\n\tspinlock_t rx_svc_list_lock;\n\tstruct mbox_controller controller;\n\tstruct bcm74110_mbox_chan *mbox_chan;\n\tlong: 32;\n};\n\nstruct bcm74110_mbox_chan {\n\tstruct bcm74110_mbox *mbox;\n\tbool en;\n\tint slot;\n\tint type;\n};\n\nstruct bcm74110_mbox_msg {\n\tstruct list_head list_entry;\n\tu32 msg;\n};\n\nstruct bcm74110_priv {\n\tvoid *base;\n};\n\nstruct bcm_clk_div {\n\tunion {\n\t\tstruct {\n\t\t\tu32 offset;\n\t\t\tu32 shift;\n\t\t\tu32 width;\n\t\t\tu32 frac_width;\n\t\t\tu64 scaled_div;\n\t\t} s;\n\t\tu32 fixed;\n\t} u;\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct bcm_clk_gate {\n\tu32 offset;\n\tu32 status_bit;\n\tu32 en_bit;\n\tu32 hw_sw_sel_bit;\n\tu32 flags;\n};\n\nstruct bcm_clk_hyst {\n\tu32 offset;\n\tu32 en_bit;\n\tu32 val_bit;\n};\n\nstruct bcm_clk_policy {\n\tu32 offset;\n\tu32 bit;\n};\n\nstruct bcm_clk_sel {\n\tu32 offset;\n\tu32 shift;\n\tu32 width;\n\tu32 parent_count;\n\tu32 *parent_sel;\n\tu8 clk_index;\n};\n\nstruct bcm_clk_trig {\n\tu32 offset;\n\tu32 bit;\n\tu32 flags;\n};\n\nstruct bcm_iproc_i2c_dev {\n\tstruct device *device;\n\tenum bcm_iproc_i2c_type type;\n\tint irq;\n\tvoid *base;\n\tvoid *idm_base;\n\tu32 ape_addr_mask;\n\tspinlock_t idm_lock;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tunsigned int bus_speed;\n\tstruct completion done;\n\tint xfer_is_done;\n\tstruct i2c_msg *msg;\n\tstruct i2c_client *slave;\n\tunsigned int tx_bytes;\n\tunsigned int rx_bytes;\n\tunsigned int thld_bytes;\n\tbool slave_rx_only;\n\tbool rx_start_rcvd;\n\tbool slave_read_complete;\n\tu32 tx_underrun;\n\tu32 slave_int_mask;\n\tstruct tasklet_struct slave_rx_tasklet;\n};\n\nstruct bcm_qspi_soc_intc {\n\tvoid (*bcm_qspi_int_ack)(struct bcm_qspi_soc_intc *, int);\n\tvoid (*bcm_qspi_int_set)(struct bcm_qspi_soc_intc *, int, bool);\n\tu32 (*bcm_qspi_get_int_status)(struct bcm_qspi_soc_intc *);\n};\n\nstruct bcm_iproc_intc {\n\tstruct bcm_qspi_soc_intc soc_intc;\n\tstruct platform_device *pdev;\n\tvoid *int_reg;\n\tvoid *int_status_reg;\n\tspinlock_t soclock;\n\tbool big_endian;\n};\n\nstruct bcm_kona_gpio_bank;\n\nstruct bcm_kona_gpio {\n\tvoid *reg_base;\n\tint num_bank;\n\traw_spinlock_t lock;\n\tstruct gpio_chip gpio_chip;\n\tstruct irq_domain *irq_domain;\n\tstruct bcm_kona_gpio_bank *banks;\n};\n\nstruct bcm_kona_gpio_bank {\n\tint id;\n\tint irq;\n\tu8 gpio_unlock_count[32];\n\tstruct bcm_kona_gpio *kona_gpio;\n};\n\nstruct bus_speed_cfg;\n\nstruct hs_bus_speed_cfg;\n\nstruct bcm_kona_i2c_dev {\n\tstruct device *device;\n\tvoid *base;\n\tint irq;\n\tstruct clk *external_clk;\n\tstruct i2c_adapter adapter;\n\tstruct completion done;\n\tconst struct bus_speed_cfg *std_cfg;\n\tconst struct hs_bus_speed_cfg *hs_cfg;\n};\n\nstruct bcm_kona_smc_data {\n\tunsigned int service_id;\n\tunsigned int arg0;\n\tunsigned int arg1;\n\tunsigned int arg2;\n\tunsigned int arg3;\n\tunsigned int result;\n};\n\nstruct bcm_kona_wdt {\n\tvoid *base;\n\tint resolution;\n\tspinlock_t lock;\n};\n\nstruct bcm_kp {\n\tvoid *base;\n\tint irq;\n\tstruct clk *clk;\n\tstruct input_dev *input_dev;\n\tlong unsigned int last_state[2];\n\tunsigned int n_rows;\n\tunsigned int n_cols;\n\tu32 kpcr;\n\tu32 kpior;\n\tu32 kpemr;\n\tu32 imr0_val;\n\tu32 imr1_val;\n};\n\nstruct bcm_lvm_en {\n\tu32 offset;\n\tu32 bit;\n};\n\nstruct bcm_timeval {\n\tlong int tv_sec;\n\tlong int tv_usec;\n};\n\nstruct can_frame {\n\tcanid_t can_id;\n\tunion {\n\t\t__u8 len;\n\t\t__u8 can_dlc;\n\t};\n\t__u8 __pad;\n\t__u8 __res0;\n\t__u8 len8_dlc;\n\t__u8 data[8];\n};\n\nstruct bcm_msg_head {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 count;\n\tstruct bcm_timeval ival1;\n\tstruct bcm_timeval ival2;\n\tcanid_t can_id;\n\t__u32 nframes;\n\tlong: 32;\n\tstruct can_frame frames[0];\n};\n\nstruct canfd_frame {\n\tcanid_t can_id;\n\t__u8 len;\n\t__u8 flags;\n\t__u8 __res0;\n\t__u8 __res1;\n\t__u8 data[64];\n};\n\nstruct sock;\n\nstruct bcm_op {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tint ifindex;\n\tcanid_t can_id;\n\tu32 flags;\n\tlong unsigned int frames_abs;\n\tlong unsigned int frames_filtered;\n\tstruct bcm_timeval ival1;\n\tstruct bcm_timeval ival2;\n\tlong: 32;\n\tstruct hrtimer timer;\n\tstruct hrtimer thrtimer;\n\tktime_t rx_stamp;\n\tktime_t kt_ival1;\n\tktime_t kt_ival2;\n\tktime_t kt_lastmsg;\n\tint rx_ifindex;\n\tint cfsiz;\n\tu32 count;\n\tu32 nframes;\n\tu32 currframe;\n\tvoid *frames;\n\tvoid *last_frames;\n\tlong: 32;\n\tstruct canfd_frame sframe;\n\tstruct canfd_frame last_sframe;\n\tstruct sock *sk;\n\tstruct net_device *rx_reg_dev;\n\tspinlock_t bcm_tx_lock;\n\tlong: 32;\n};\n\nstruct bcm_phy_hw_stat {\n\tconst char *string;\n\tint devad;\n\tu16 reg;\n\tu8 shift;\n\tu8 bits;\n};\n\nstruct bcm_plat_data {\n\tconst struct gpio_chip *gpio_chip;\n\tconst struct pinctrl_desc *pctl_desc;\n\tconst struct pinctrl_gpio_range *gpio_range;\n};\n\nstruct bcm_pmb {\n\tstruct device *dev;\n\tvoid *base;\n\tspinlock_t lock;\n\tbool little_endian;\n\tstruct genpd_onecell_data genpd_onecell_data;\n};\n\nstruct bcm_pmb_pd_data {\n\tconst char * const name;\n\tint id;\n\tu8 bus;\n\tu8 device;\n};\n\nstruct bcm_pmb_pm_domain {\n\tstruct bcm_pmb *pmb;\n\tconst struct bcm_pmb_pd_data *data;\n\tstruct generic_pm_domain genpd;\n};\n\nstruct bcm_policy_ctl {\n\tu32 offset;\n\tu32 go_bit;\n\tu32 atl_bit;\n\tu32 ac_bit;\n};\n\nstruct bcm_qspi_parms {\n\tu32 speed_hz;\n\tu8 mode;\n\tu8 bits_per_word;\n};\n\nstruct qspi_trans {\n\tstruct spi_transfer *trans;\n\tint byte;\n\tbool mspi_last_trans;\n};\n\nstruct bcm_xfer_mode {\n\tbool flex_mode;\n\tunsigned int width;\n\tunsigned int addrlen;\n\tunsigned int hp;\n};\n\nstruct spi_mem_op;\n\nstruct bcm_qspi_dev_id;\n\nstruct bcm_qspi {\n\tstruct platform_device *pdev;\n\tstruct spi_controller *host;\n\tstruct clk *clk;\n\tu32 base_clk;\n\tu32 max_speed_hz;\n\tvoid *base[3];\n\tstruct bcm_qspi_soc_intc *soc_intc;\n\tstruct bcm_qspi_parms last_parms;\n\tstruct qspi_trans trans_pos;\n\tint curr_cs;\n\tint bspi_maj_rev;\n\tint bspi_min_rev;\n\tint bspi_enabled;\n\tconst struct spi_mem_op *bspi_rf_op;\n\tu32 bspi_rf_op_idx;\n\tu32 bspi_rf_op_len;\n\tu32 bspi_rf_op_status;\n\tstruct bcm_xfer_mode xfer_mode;\n\tu32 s3_strap_override_ctrl;\n\tbool bspi_mode;\n\tbool big_endian;\n\tint num_irqs;\n\tstruct bcm_qspi_dev_id *dev_ids;\n\tstruct completion mspi_done;\n\tstruct completion bspi_done;\n\tu8 mspi_maj_rev;\n\tu8 mspi_min_rev;\n\tbool mspi_spcr3_sysclk;\n};\n\nstruct bcm_qspi_data {\n\tbool has_mspi_rev;\n\tbool has_spcr3_sysclk;\n};\n\nstruct bcm_qspi_irq;\n\nstruct bcm_qspi_dev_id {\n\tconst struct bcm_qspi_irq *irqp;\n\tvoid *dev;\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct bcm_qspi_irq {\n\tconst char *irq_name;\n\tconst irq_handler_t irq_handler;\n\tint irq_source;\n\tu32 mask;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n\tlong: 32;\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u16 offset;\n\t__u16 size;\n};\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n};\n\nstruct sock_cgroup_data {};\n\nstruct dst_entry;\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct socket;\n\nstruct xfrm_policy;\n\nstruct sock_reuseport;\n\nstruct bpf_local_storage;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\tstruct xfrm_policy *sk_policy[2];\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tlong: 32;\n\tnetdev_features_t sk_route_caps;\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tktime_t sk_stamp;\n\tseqlock_t sk_stamp_seq;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n};\n\nstruct proc_dir_entry;\n\nstruct bcm_sock {\n\tstruct sock sk;\n\tint bound;\n\tint ifindex;\n\tstruct list_head notifier;\n\tstruct list_head rx_ops;\n\tstruct list_head tx_ops;\n\tlong unsigned int dropped_usr_msgs;\n\tstruct proc_dir_entry *bcm_proc_read;\n\tchar procname[32];\n};\n\nstruct bcm_usb_phy_cfg {\n\tuint32_t type;\n\tuint32_t version;\n\tvoid *regs;\n\tstruct phy *phy;\n\tconst u8 *offset;\n};\n\nstruct bcma_boardinfo {\n\tu16 vendor;\n\tu16 type;\n};\n\nstruct bcma_chipinfo {\n\tu16 id;\n\tu8 rev;\n\tu8 pkg;\n};\n\nstruct bcma_device;\n\nstruct bcma_chipcommon_pmu {\n\tstruct bcma_device *core;\n\tu8 rev;\n\tu32 crystalfreq;\n};\n\nstruct bcma_sflash {\n\tbool present;\n\tu32 blocksize;\n\tu16 numblocks;\n\tu32 size;\n};\n\nstruct bcma_drv_cc {\n\tstruct bcma_device *core;\n\tu32 status;\n\tu32 capabilities;\n\tu32 capabilities_ext;\n\tu8 setup_done: 1;\n\tu8 early_setup_done: 1;\n\tu16 fast_pwrup_delay;\n\tstruct bcma_chipcommon_pmu pmu;\n\tstruct bcma_sflash sflash;\n\tu32 ticks_per_ms;\n\tstruct platform_device *watchdog;\n\tspinlock_t gpio_lock;\n\tstruct gpio_chip gpio;\n};\n\nstruct bcma_drv_cc_b {\n\tstruct bcma_device *core;\n\tu8 setup_done: 1;\n\tvoid *mii;\n};\n\nstruct bcma_drv_pci {\n\tstruct bcma_device *core;\n\tu8 early_setup_done: 1;\n\tu8 setup_done: 1;\n\tu8 hostmode: 1;\n};\n\nstruct bcma_drv_pcie2 {\n\tstruct bcma_device *core;\n\tu16 reqsize;\n};\n\nstruct bcma_drv_mips {\n\tstruct bcma_device *core;\n\tu8 setup_done: 1;\n\tu8 early_setup_done: 1;\n};\n\nstruct bcma_drv_gmac_cmn {\n\tstruct bcma_device *core;\n\tstruct mutex phy_mutex;\n};\n\nstruct ssb_sprom_core_pwr_info {\n\tu8 itssi_2g;\n\tu8 itssi_5g;\n\tu8 maxpwr_2g;\n\tu8 maxpwr_5gl;\n\tu8 maxpwr_5g;\n\tu8 maxpwr_5gh;\n\tu16 pa_2g[4];\n\tu16 pa_5gl[4];\n\tu16 pa_5g[4];\n\tu16 pa_5gh[4];\n};\n\nstruct ssb_sprom {\n\tu8 revision;\n\tshort: 0;\n\tu8 il0mac[6];\n\tu8 et0mac[6];\n\tu8 et1mac[6];\n\tu8 et2mac[6];\n\tu8 et0phyaddr;\n\tu8 et1phyaddr;\n\tu8 et2phyaddr;\n\tu8 et0mdcport;\n\tu8 et1mdcport;\n\tu8 et2mdcport;\n\tu16 dev_id;\n\tu16 board_rev;\n\tu16 board_num;\n\tu16 board_type;\n\tu8 country_code;\n\tchar alpha2[2];\n\tu8 leddc_on_time;\n\tu8 leddc_off_time;\n\tu8 ant_available_a;\n\tu8 ant_available_bg;\n\tu16 pa0b0;\n\tu16 pa0b1;\n\tu16 pa0b2;\n\tu16 pa1b0;\n\tu16 pa1b1;\n\tu16 pa1b2;\n\tu16 pa1lob0;\n\tu16 pa1lob1;\n\tu16 pa1lob2;\n\tu16 pa1hib0;\n\tu16 pa1hib1;\n\tu16 pa1hib2;\n\tu8 gpio0;\n\tu8 gpio1;\n\tu8 gpio2;\n\tu8 gpio3;\n\tu8 maxpwr_bg;\n\tu8 maxpwr_al;\n\tu8 maxpwr_a;\n\tu8 maxpwr_ah;\n\tu8 itssi_a;\n\tu8 itssi_bg;\n\tu8 tri2g;\n\tu8 tri5gl;\n\tu8 tri5g;\n\tu8 tri5gh;\n\tu8 txpid2g[4];\n\tu8 txpid5gl[4];\n\tu8 txpid5g[4];\n\tu8 txpid5gh[4];\n\ts8 rxpo2g;\n\ts8 rxpo5g;\n\tu8 rssisav2g;\n\tu8 rssismc2g;\n\tu8 rssismf2g;\n\tu8 bxa2g;\n\tu8 rssisav5g;\n\tu8 rssismc5g;\n\tu8 rssismf5g;\n\tu8 bxa5g;\n\tu16 cck2gpo;\n\tu32 ofdm2gpo;\n\tu32 ofdm5glpo;\n\tu32 ofdm5gpo;\n\tu32 ofdm5ghpo;\n\tu32 boardflags;\n\tu32 boardflags2;\n\tu32 boardflags3;\n\tu16 boardflags_lo;\n\tu16 boardflags_hi;\n\tu16 boardflags2_lo;\n\tu16 boardflags2_hi;\n\tstruct ssb_sprom_core_pwr_info core_pwr_info[4];\n\tstruct {\n\t\ts8 a0;\n\t\ts8 a1;\n\t\ts8 a2;\n\t\ts8 a3;\n\t} antenna_gain;\n\tstruct {\n\t\tstruct {\n\t\t\tu8 tssipos;\n\t\t\tu8 extpa_gain;\n\t\t\tu8 pdet_range;\n\t\t\tu8 tr_iso;\n\t\t\tu8 antswlut;\n\t\t} ghz2;\n\t\tstruct {\n\t\t\tu8 tssipos;\n\t\t\tu8 extpa_gain;\n\t\t\tu8 pdet_range;\n\t\t\tu8 tr_iso;\n\t\t\tu8 antswlut;\n\t\t} ghz5;\n\t} fem;\n\tu16 mcs2gpo[8];\n\tu16 mcs5gpo[8];\n\tu16 mcs5glpo[8];\n\tu16 mcs5ghpo[8];\n\tu8 opo;\n\tu8 rxgainerr2ga[3];\n\tu8 rxgainerr5gla[3];\n\tu8 rxgainerr5gma[3];\n\tu8 rxgainerr5gha[3];\n\tu8 rxgainerr5gua[3];\n\tu8 noiselvl2ga[3];\n\tu8 noiselvl5gla[3];\n\tu8 noiselvl5gma[3];\n\tu8 noiselvl5gha[3];\n\tu8 noiselvl5gua[3];\n\tu8 regrev;\n\tu8 txchain;\n\tu8 rxchain;\n\tu8 antswitch;\n\tu16 cddpo;\n\tu16 stbcpo;\n\tu16 bw40po;\n\tu16 bwduppo;\n\tu8 tempthresh;\n\tu8 tempoffset;\n\tu16 rawtempsense;\n\tu8 measpower;\n\tu8 tempsense_slope;\n\tu8 tempcorrx;\n\tu8 tempsense_option;\n\tu8 freqoffset_corr;\n\tu8 iqcal_swp_dis;\n\tu8 hw_iqcal_en;\n\tu8 elna2g;\n\tu8 elna5g;\n\tu8 phycal_tempdelta;\n\tu8 temps_period;\n\tu8 temps_hysteresis;\n\tu8 measpower1;\n\tu8 measpower2;\n\tu8 pcieingress_war;\n\tu16 cckbw202gpo;\n\tu16 cckbw20ul2gpo;\n\tu32 legofdmbw202gpo;\n\tu32 legofdmbw20ul2gpo;\n\tu32 legofdmbw205glpo;\n\tu32 legofdmbw20ul5glpo;\n\tu32 legofdmbw205gmpo;\n\tu32 legofdmbw20ul5gmpo;\n\tu32 legofdmbw205ghpo;\n\tu32 legofdmbw20ul5ghpo;\n\tu32 mcsbw202gpo;\n\tu32 mcsbw20ul2gpo;\n\tu32 mcsbw402gpo;\n\tu32 mcsbw205glpo;\n\tu32 mcsbw20ul5glpo;\n\tu32 mcsbw405glpo;\n\tu32 mcsbw205gmpo;\n\tu32 mcsbw20ul5gmpo;\n\tu32 mcsbw405gmpo;\n\tu32 mcsbw205ghpo;\n\tu32 mcsbw20ul5ghpo;\n\tu32 mcsbw405ghpo;\n\tu16 mcs32po;\n\tu16 legofdm40duppo;\n\tu8 sar2g;\n\tu8 sar5g;\n};\n\nstruct bcma_host_ops;\n\nstruct pci_dev;\n\nstruct bcma_bus {\n\tstruct device *dev;\n\tvoid *mmio;\n\tconst struct bcma_host_ops *ops;\n\tenum bcma_hosttype hosttype;\n\tbool host_is_pcie2;\n\tstruct pci_dev *host_pci;\n\tstruct bcma_chipinfo chipinfo;\n\tstruct bcma_boardinfo boardinfo;\n\tstruct bcma_device *mapped_core;\n\tstruct list_head cores;\n\tu8 nr_cores;\n\tu8 num;\n\tstruct bcma_drv_cc drv_cc;\n\tstruct bcma_drv_cc_b drv_cc_b;\n\tstruct bcma_drv_pci drv_pci[2];\n\tstruct bcma_drv_pcie2 drv_pcie2;\n\tstruct bcma_drv_mips drv_mips;\n\tstruct bcma_drv_gmac_cmn drv_gmac_cmn;\n\tstruct ssb_sprom sprom;\n};\n\nstruct bcma_device_id {\n\t__u16 manuf;\n\t__u16 id;\n\t__u8 rev;\n\t__u8 class;\n};\n\nstruct bcma_device {\n\tstruct bcma_bus *bus;\n\tstruct bcma_device_id id;\n\tlong: 32;\n\tstruct device dev;\n\tstruct device *dma_dev;\n\tunsigned int irq;\n\tbool dev_registered;\n\tu8 core_index;\n\tu8 core_unit;\n\tu32 addr;\n\tu32 addr_s[8];\n\tu32 wrap;\n\tvoid *io_addr;\n\tvoid *io_wrap;\n\tvoid *drvdata;\n\tstruct list_head list;\n};\n\nstruct bcma_device_id_name {\n\tu16 id;\n\tconst char *name;\n};\n\nstruct bcma_driver {\n\tconst char *name;\n\tconst struct bcma_device_id *id_table;\n\tint (*probe)(struct bcma_device *);\n\tvoid (*remove)(struct bcma_device *);\n\tint (*suspend)(struct bcma_device *);\n\tint (*resume)(struct bcma_device *);\n\tvoid (*shutdown)(struct bcma_device *);\n\tstruct device_driver drv;\n};\n\nstruct bcma_host_ops {\n\tu8 (*read8)(struct bcma_device *, u16);\n\tu16 (*read16)(struct bcma_device *, u16);\n\tu32 (*read32)(struct bcma_device *, u16);\n\tvoid (*write8)(struct bcma_device *, u16, u8);\n\tvoid (*write16)(struct bcma_device *, u16, u16);\n\tvoid (*write32)(struct bcma_device *, u16, u32);\n\tu32 (*aread32)(struct bcma_device *, u16);\n\tvoid (*awrite32)(struct bcma_device *, u16, u32);\n};\n\nstruct bcma_sflash_tbl_e {\n\tchar *name;\n\tu32 id;\n\tu32 blocksize;\n\tu16 numblocks;\n};\n\nstruct bcma_soc {\n\tstruct bcma_bus bus;\n\tstruct device *dev;\n};\n\nstruct bcmasp_desc {\n\tu64 buf;\n\tu32 size;\n\tu32 flags;\n};\n\nstruct bcmasp_res {\n\tvoid *umac;\n\tvoid *umac2fb;\n\tvoid *rgmii;\n\tvoid *tx_spb_ctrl;\n\tvoid *tx_spb_top;\n\tvoid *tx_epkt_core;\n\tvoid *tx_pause_ctrl;\n};\n\nstruct bcmasp_intf_stats64 {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_errors;\n\tu64_stats_t rx_dropped;\n\tu64_stats_t rx_crc_errs;\n\tu64_stats_t rx_sym_errs;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct bcmasp_mib_counters {\n\tu32 edpkt_ts;\n\tu32 edpkt_rx_pkt_cnt;\n\tu32 edpkt_hdr_ext_cnt;\n\tu32 edpkt_hdr_out_cnt;\n\tu32 umac_frm_cnt;\n\tu32 fb_frm_cnt;\n\tu32 fb_rx_fifo_depth;\n\tu32 fb_out_frm_cnt;\n\tu32 fb_filt_out_frm_cnt;\n\tu32 alloc_rx_skb_failed;\n\tu32 tx_dma_failed;\n\tu32 mc_filters_full_cnt;\n\tu32 uc_filters_full_cnt;\n\tu32 filters_combine_cnt;\n\tu32 promisc_filters_cnt;\n\tu32 tx_realloc_offload_failed;\n\tu32 tx_timeout_cnt;\n};\n\nstruct bcmasp_priv;\n\nstruct bcmasp_tx_cb;\n\nstruct bcmasp_intf {\n\tstruct list_head list;\n\tstruct net_device *ndev;\n\tstruct bcmasp_priv *parent;\n\tint channel;\n\tint port;\n\tint index;\n\tlong: 32;\n\tstruct napi_struct tx_napi;\n\tvoid *tx_spb_dma;\n\tint tx_spb_index;\n\tint tx_spb_clean_index;\n\tstruct bcmasp_desc *tx_spb_cpu;\n\tdma_addr_t tx_spb_dma_addr;\n\tdma_addr_t tx_spb_dma_valid;\n\tdma_addr_t tx_spb_dma_read;\n\tstruct bcmasp_tx_cb *tx_cbs;\n\tvoid *rx_edpkt_cfg;\n\tvoid *rx_edpkt_dma;\n\tint rx_edpkt_index;\n\tint rx_buf_order;\n\tstruct bcmasp_desc *rx_edpkt_cpu;\n\tdma_addr_t rx_edpkt_dma_addr;\n\tdma_addr_t rx_edpkt_dma_read;\n\tdma_addr_t rx_edpkt_dma_valid;\n\tvoid *rx_ring_cpu;\n\tdma_addr_t rx_ring_dma;\n\tdma_addr_t rx_ring_dma_valid;\n\tlong: 32;\n\tstruct napi_struct rx_napi;\n\tstruct bcmasp_res res;\n\tunsigned int crc_fwd;\n\tstruct device_node *phy_dn;\n\tstruct device_node *ndev_dn;\n\tphy_interface_t phy_interface;\n\tbool internal_phy;\n\tint old_pause;\n\tint old_link;\n\tint old_duplex;\n\tu32 msg_enable;\n\tstruct bcmasp_intf_stats64 stats64;\n\tstruct bcmasp_mib_counters mib;\n\tu32 wolopts;\n\tu8 sopass[6];\n};\n\nstruct bcmasp_mda_filter {\n\tint port;\n\tbool en;\n\tu8 addr[6];\n\tu8 mask[6];\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\tlong: 32;\n\t__u64 ring_cookie;\n\t__u32 location;\n\tlong: 32;\n};\n\nstruct bcmasp_net_filter {\n\tstruct ethtool_rx_flow_spec fs;\n\tbool claimed;\n\tbool wake_filter;\n\tint port;\n\tint ch;\n\tunsigned int hw_index;\n};\n\nstruct bcmasp_pkt_offload {\n\t__be32 nop;\n\t__be32 header;\n\t__be32 header2;\n\t__be32 epkt;\n\t__be32 end;\n};\n\nstruct bcmasp_plat_data {\n\tvoid (*core_clock_select)(struct bcmasp_priv *, bool);\n\tvoid (*eee_fixup)(struct bcmasp_intf *, bool);\n\tunsigned int num_mda_filters;\n\tunsigned int num_net_filters;\n\tunsigned int tx_chan_offset;\n\tunsigned int rx_ctrl_offset;\n};\n\nstruct bcmasp_priv {\n\tstruct platform_device *pdev;\n\tstruct clk *clk;\n\tint irq;\n\tu32 irq_mask;\n\tstruct mutex wol_lock;\n\tint wol_irq;\n\tlong unsigned int wol_irq_enabled_mask;\n\tvoid (*core_clock_select)(struct bcmasp_priv *, bool);\n\tvoid (*eee_fixup)(struct bcmasp_intf *, bool);\n\tunsigned int num_mda_filters;\n\tunsigned int num_net_filters;\n\tunsigned int tx_chan_offset;\n\tunsigned int rx_ctrl_offset;\n\tvoid *base;\n\tstruct list_head intfs;\n\tstruct bcmasp_mda_filter *mda_filters;\n\tspinlock_t mda_lock;\n\tspinlock_t clk_lock;\n\tstruct bcmasp_net_filter *net_filters;\n\tstruct mutex net_lock;\n};\n\nstruct bcmasp_stats {\n\tchar stat_string[32];\n\tenum bcmasp_stat_type type;\n\tu32 reg_offset;\n};\n\nstruct bcmasp_tx_cb {\n\tstruct sk_buff *skb;\n\tunsigned int bytes_sent;\n\tbool last;\n\tdma_addr_t dma_addr;\n\t__u32 dma_len;\n};\n\nstruct brcmnand_io_ops;\n\nstruct brcmnand_soc {\n\tbool (*ctlrdy_ack)(struct brcmnand_soc *);\n\tvoid (*ctlrdy_set_enabled)(struct brcmnand_soc *, bool);\n\tvoid (*prepare_data_bus)(struct brcmnand_soc *, bool, bool);\n\tvoid (*read_data_bus)(struct brcmnand_soc *, void *, u32 *, int);\n\tconst struct brcmnand_io_ops *ops;\n};\n\nstruct bcmbca_nand_soc {\n\tstruct brcmnand_soc soc;\n\tvoid *base;\n};\n\nstruct bd_table;\n\nstruct bd_list {\n\tstruct bd_table **bd_table_array;\n\tint num_tabs;\n\tint max_bdi;\n\tint eqp_bdi;\n\tint hwd_bdi;\n\tint num_bds_table;\n};\n\nstruct bdc_bd;\n\nstruct bd_table {\n\tstruct bdc_bd *start_bd;\n\tdma_addr_t dma;\n};\n\nstruct bdc_req;\n\nstruct bd_transfer {\n\tstruct bdc_req *req;\n\tint start_bdi;\n\tint next_hwd_bdi;\n\tint num_bds;\n};\n\nstruct usb_udc;\n\nstruct usb_gadget_ops;\n\nstruct usb_ep;\n\nstruct usb_otg_caps;\n\nstruct usb_gadget {\n\tstruct work_struct work;\n\tstruct usb_udc *udc;\n\tconst struct usb_gadget_ops *ops;\n\tstruct usb_ep *ep0;\n\tstruct list_head ep_list;\n\tenum usb_device_speed speed;\n\tenum usb_device_speed max_speed;\n\tenum usb_ssp_rate ssp_rate;\n\tenum usb_ssp_rate max_ssp_rate;\n\tenum usb_device_state state;\n\tspinlock_t state_lock;\n\tbool teardown;\n\tconst char *name;\n\tlong: 32;\n\tstruct device dev;\n\tunsigned int isoch_delay;\n\tunsigned int out_epnum;\n\tunsigned int in_epnum;\n\tunsigned int mA;\n\tstruct usb_otg_caps *otg_caps;\n\tunsigned int sg_supported: 1;\n\tunsigned int is_otg: 1;\n\tunsigned int is_a_peripheral: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int a_hnp_support: 1;\n\tunsigned int a_alt_hnp_support: 1;\n\tunsigned int hnp_polling_support: 1;\n\tunsigned int host_request_flag: 1;\n\tunsigned int quirk_ep_out_aligned_size: 1;\n\tunsigned int quirk_altset_not_supp: 1;\n\tunsigned int quirk_stall_not_supp: 1;\n\tunsigned int quirk_zlp_not_supp: 1;\n\tunsigned int quirk_avoids_skb_reserve: 1;\n\tunsigned int is_selfpowered: 1;\n\tunsigned int deactivated: 1;\n\tunsigned int connected: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int wakeup_capable: 1;\n\tunsigned int wakeup_armed: 1;\n\tint irq;\n\tint id_number;\n};\n\nstruct bdc_scratchpad {\n\tdma_addr_t sp_dma;\n\tvoid *buff;\n\tu32 size;\n};\n\nstruct bdc_sr;\n\nstruct srr {\n\tstruct bdc_sr *sr_bds;\n\tu16 eqp_index;\n\tu16 dqp_index;\n\tdma_addr_t dma_addr;\n};\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_request {\n\tstruct usb_ep *ep;\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tstruct scatterlist *sg;\n\tunsigned int num_sgs;\n\tunsigned int num_mapped_sgs;\n\tunsigned int stream_id: 16;\n\tunsigned int is_last: 1;\n\tunsigned int no_interrupt: 1;\n\tunsigned int zero: 1;\n\tunsigned int short_not_ok: 1;\n\tunsigned int dma_mapped: 1;\n\tunsigned int sg_was_mapped: 1;\n\tvoid (*complete)(struct usb_ep *, struct usb_request *);\n\tvoid *context;\n\tstruct list_head list;\n\tunsigned int frame_number;\n\tint status;\n\tunsigned int actual;\n};\n\nstruct bdc_ep;\n\nstruct bdc_req {\n\tstruct usb_request usb_req;\n\tstruct list_head queue;\n\tstruct bdc_ep *ep;\n\tstruct bd_transfer bd_xfr;\n\tint epnum;\n};\n\nstruct usb_gadget_driver;\n\nstruct bdc {\n\tstruct usb_gadget gadget;\n\tstruct usb_gadget_driver *gadget_driver;\n\tstruct device *dev;\n\tspinlock_t lock;\n\tstruct phy **phys;\n\tint num_phys;\n\tunsigned int num_eps;\n\tstruct bdc_ep **bdc_ep_array;\n\tvoid *regs;\n\tstruct bdc_scratchpad scratchpad;\n\tu32 sp_buff_size;\n\tstruct srr srr;\n\tstruct usb_ctrlrequest setup_pkt;\n\tstruct bdc_req ep0_req;\n\tstruct bdc_req status_req;\n\tenum bdc_ep0_state ep0_state;\n\tbool delayed_status;\n\tbool zlp_needed;\n\tbool reinit;\n\tbool pullup;\n\tu32 devstatus;\n\tint irq;\n\tvoid *mem;\n\tu32 dev_addr;\n\tstruct dma_pool *bd_table_pool;\n\tu8 test_mode;\n\tvoid (*sr_handler[2])(struct bdc *, struct bdc_sr *);\n\tvoid (*sr_xsf_ep0[3])(struct bdc *, struct bdc_sr *);\n\tunsigned char ep0_response_buff[6];\n\tstruct delayed_work func_wake_notify;\n\tstruct clk *clk;\n};\n\nstruct bdc_bd {\n\t__le32 offset[4];\n};\n\nstruct usb_ep_caps {\n\tunsigned int type_control: 1;\n\tunsigned int type_iso: 1;\n\tunsigned int type_bulk: 1;\n\tunsigned int type_int: 1;\n\tunsigned int dir_in: 1;\n\tunsigned int dir_out: 1;\n};\n\nstruct usb_ep_ops;\n\nstruct usb_endpoint_descriptor;\n\nstruct usb_ss_ep_comp_descriptor;\n\nstruct usb_ep {\n\tvoid *driver_data;\n\tconst char *name;\n\tconst struct usb_ep_ops *ops;\n\tconst struct usb_endpoint_descriptor *desc;\n\tconst struct usb_ss_ep_comp_descriptor *comp_desc;\n\tstruct list_head ep_list;\n\tstruct usb_ep_caps caps;\n\tbool claimed;\n\tbool enabled;\n\tunsigned int mult: 2;\n\tunsigned int maxburst: 5;\n\tu8 address;\n\tu16 maxpacket;\n\tu16 maxpacket_limit;\n\tu16 max_streams;\n};\n\nstruct bdc_ep {\n\tstruct usb_ep usb_ep;\n\tstruct list_head queue;\n\tstruct bdc *bdc;\n\tu8 ep_type;\n\tu8 dir;\n\tu8 ep_num;\n\tconst struct usb_ss_ep_comp_descriptor *comp_desc;\n\tconst struct usb_endpoint_descriptor *desc;\n\tunsigned int flags;\n\tchar name[20];\n\tstruct bd_list bd_list;\n\tbool ignore_next_sr;\n};\n\nstruct bdc_sr {\n\t__le32 offset[4];\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tlong: 32;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct fsnotify_mark_connector;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tseqcount_t i_size_seqcount;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n\tlong: 32;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct berlin2_avpll_channel {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu8 flags;\n\tu8 index;\n};\n\nstruct berlin2_avpll_vco {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu8 flags;\n};\n\nstruct berlin2_div_map {\n\tu16 pll_select_offs;\n\tu16 pll_switch_offs;\n\tu16 div_select_offs;\n\tu16 div_switch_offs;\n\tu16 div3_switch_offs;\n\tu16 gate_offs;\n\tu8 pll_select_shift;\n\tu8 pll_switch_shift;\n\tu8 div_select_shift;\n\tu8 div_switch_shift;\n\tu8 div3_switch_shift;\n\tu8 gate_shift;\n};\n\nstruct berlin2_div {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct berlin2_div_map map;\n\tspinlock_t *lock;\n};\n\nstruct berlin2_div_data {\n\tconst char *name;\n\tconst u8 *parent_ids;\n\tint num_parents;\n\tlong unsigned int flags;\n\tstruct berlin2_div_map map;\n\tu8 div_flags;\n};\n\nstruct berlin2_gate_data {\n\tconst char *name;\n\tconst char *parent_name;\n\tu8 bit_idx;\n\tlong unsigned int flags;\n};\n\nstruct berlin2_pll_map {\n\tconst u8 vcodiv[16];\n\tu8 mult;\n\tu8 fbdiv_shift;\n\tu8 rfdiv_shift;\n\tu8 divsel_shift;\n};\n\nstruct berlin2_pll {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct berlin2_pll_map map;\n};\n\nstruct berlin_desc_function {\n\tconst char *name;\n\tu8 muxval;\n};\n\nstruct berlin_desc_group {\n\tconst char *name;\n\tu8 offset;\n\tu8 bit_width;\n\tu8 lsb;\n\tstruct berlin_desc_function *functions;\n};\n\nstruct berlin_pinctrl_desc;\n\nstruct pinfunction;\n\nstruct berlin_pinctrl {\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tconst struct berlin_pinctrl_desc *desc;\n\tstruct pinfunction *functions;\n\tunsigned int nfunctions;\n\tstruct pinctrl_dev *pctrl_dev;\n};\n\nstruct berlin_pinctrl_desc {\n\tconst struct berlin_desc_group *groups;\n\tunsigned int ngroups;\n};\n\nstruct bfq_sched_data;\n\nstruct bfq_queue;\n\nstruct bfq_entity {\n\tstruct rb_node rb_node;\n\tbool on_st_or_in_serv;\n\tu64 start;\n\tu64 finish;\n\tstruct rb_root *tree;\n\tlong: 32;\n\tu64 min_start;\n\tint service;\n\tint budget;\n\tint allocated;\n\tint dev_weight;\n\tint weight;\n\tint new_weight;\n\tint orig_weight;\n\tstruct bfq_entity *parent;\n\tstruct bfq_sched_data *my_sched_data;\n\tstruct bfq_sched_data *sched_data;\n\tint prio_changed;\n\tstruct bfq_queue *last_bfqq_created;\n};\n\nstruct bfq_ttime {\n\tu64 last_end_request;\n\tu64 ttime_total;\n\tlong unsigned int ttime_samples;\n\tlong: 32;\n\tu64 ttime_mean;\n};\n\nstruct bfq_data;\n\nstruct request;\n\nstruct bfq_weight_counter;\n\nstruct bfq_io_cq;\n\nstruct bfq_queue {\n\tint ref;\n\tint stable_ref;\n\tstruct bfq_data *bfqd;\n\tshort unsigned int ioprio;\n\tshort unsigned int ioprio_class;\n\tshort unsigned int new_ioprio;\n\tshort unsigned int new_ioprio_class;\n\tlong: 32;\n\tu64 last_serv_time_ns;\n\tunsigned int inject_limit;\n\tlong unsigned int decrease_time_jif;\n\tstruct bfq_queue *new_bfqq;\n\tstruct rb_node pos_node;\n\tstruct rb_root *pos_root;\n\tstruct rb_root sort_list;\n\tstruct request *next_rq;\n\tint queued[2];\n\tint meta_pending;\n\tstruct list_head fifo;\n\tstruct bfq_entity entity;\n\tstruct bfq_weight_counter *weight_counter;\n\tint max_budget;\n\tlong unsigned int budget_timeout;\n\tint dispatched;\n\tlong unsigned int flags;\n\tstruct list_head bfqq_list;\n\tlong: 32;\n\tstruct bfq_ttime ttime;\n\tu64 io_start_time;\n\tu64 tot_idle_time;\n\tu32 seek_history;\n\tstruct hlist_node burst_list_node;\n\tlong: 32;\n\tsector_t last_request_pos;\n\tunsigned int requests_within_timer;\n\tpid_t pid;\n\tstruct bfq_io_cq *bic;\n\tlong unsigned int wr_cur_max_time;\n\tlong unsigned int soft_rt_next_start;\n\tlong unsigned int last_wr_start_finish;\n\tunsigned int wr_coeff;\n\tlong unsigned int last_idle_bklogged;\n\tlong unsigned int service_from_backlogged;\n\tlong unsigned int service_from_wr;\n\tlong unsigned int wr_start_at_switch_to_srt;\n\tlong unsigned int split_time;\n\tlong unsigned int first_IO_time;\n\tlong unsigned int creation_time;\n\tstruct bfq_queue *waker_bfqq;\n\tstruct bfq_queue *tentative_waker_bfqq;\n\tunsigned int num_waker_detections;\n\tlong: 32;\n\tu64 waker_detection_started;\n\tstruct hlist_node woken_list_node;\n\tstruct hlist_head woken_list;\n\tunsigned int actuator_idx;\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tlong: 32;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct bfq_group;\n\nstruct bfq_data {\n\tstruct request_queue *queue;\n\tstruct list_head dispatch;\n\tstruct bfq_group *root_group;\n\tstruct rb_root_cached queue_weights_tree;\n\tunsigned int busy_queues[3];\n\tint wr_busy_queues;\n\tint queued;\n\tint tot_rq_in_driver;\n\tint rq_in_driver[8];\n\tbool nonrot_with_queueing;\n\tint max_rq_in_driver;\n\tint hw_tag_samples;\n\tint hw_tag;\n\tint budgets_assigned;\n\tlong: 32;\n\tstruct hrtimer idle_slice_timer;\n\tstruct bfq_queue *in_service_queue;\n\tlong: 32;\n\tsector_t last_position;\n\tsector_t in_serv_last_pos;\n\tu64 last_completion;\n\tstruct bfq_queue *last_completed_rq_bfqq;\n\tstruct bfq_queue *last_bfqq_created;\n\tu64 last_empty_occupied_ns;\n\tbool wait_dispatch;\n\tstruct request *waited_rq;\n\tbool rqs_injected;\n\tlong: 32;\n\tu64 first_dispatch;\n\tu64 last_dispatch;\n\tktime_t last_budget_start;\n\tktime_t last_idling_start;\n\tlong unsigned int last_idling_start_jiffies;\n\tint peak_rate_samples;\n\tu32 sequential_samples;\n\tlong: 32;\n\tu64 tot_sectors_dispatched;\n\tu32 last_rq_max_size;\n\tlong: 32;\n\tu64 delta_from_first;\n\tu32 peak_rate;\n\tint bfq_max_budget;\n\tstruct list_head active_list[8];\n\tstruct list_head idle_list;\n\tu64 bfq_fifo_expire[2];\n\tunsigned int bfq_back_penalty;\n\tunsigned int bfq_back_max;\n\tu32 bfq_slice_idle;\n\tint bfq_user_max_budget;\n\tunsigned int bfq_timeout;\n\tbool strict_guarantees;\n\tlong unsigned int last_ins_in_burst;\n\tlong unsigned int bfq_burst_interval;\n\tint burst_size;\n\tstruct bfq_entity *burst_parent_entity;\n\tlong unsigned int bfq_large_burst_thresh;\n\tbool large_burst;\n\tstruct hlist_head burst_list;\n\tbool low_latency;\n\tunsigned int bfq_wr_coeff;\n\tunsigned int bfq_wr_rt_max_time;\n\tunsigned int bfq_wr_min_idle_time;\n\tlong unsigned int bfq_wr_min_inter_arr_async;\n\tunsigned int bfq_wr_max_softrt_rate;\n\tlong: 32;\n\tu64 rate_dur_prod;\n\tstruct bfq_queue oom_bfqq;\n\tspinlock_t lock;\n\tstruct bfq_io_cq *bio_bic;\n\tstruct bfq_queue *bio_bfqq;\n\tunsigned int async_depths[4];\n\tunsigned int num_actuators;\n\tsector_t sector[8];\n\tsector_t nr_sectors[8];\n\tstruct blk_independent_access_range ia_ranges[8];\n\tunsigned int actuator_load_threshold;\n\tlong: 32;\n};\n\nstruct bfq_service_tree {\n\tstruct rb_root active;\n\tstruct rb_root idle;\n\tstruct bfq_entity *first_idle;\n\tstruct bfq_entity *last_idle;\n\tu64 vtime;\n\tlong unsigned int wsum;\n\tlong: 32;\n};\n\nstruct bfq_sched_data {\n\tstruct bfq_entity *in_service_entity;\n\tstruct bfq_entity *next_in_service;\n\tstruct bfq_service_tree service_tree[3];\n\tlong unsigned int bfq_class_idle_last_service;\n\tlong: 32;\n};\n\nstruct bfq_group {\n\tstruct bfq_entity entity;\n\tstruct bfq_sched_data sched_data;\n\tstruct bfq_queue *async_bfqq[128];\n\tstruct bfq_queue *async_idle_bfqq[8];\n\tstruct rb_root rq_pos_tree;\n\tlong: 32;\n};\n\nstruct io_context;\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct bfq_iocq_bfqq_data {\n\tbool saved_has_short_ttime;\n\tbool saved_IO_bound;\n\tbool saved_in_large_burst;\n\tbool was_in_burst_list;\n\tunsigned int saved_weight;\n\tu64 saved_io_start_time;\n\tu64 saved_tot_idle_time;\n\tlong unsigned int saved_wr_coeff;\n\tlong unsigned int saved_last_wr_start_finish;\n\tlong unsigned int saved_service_from_wr;\n\tlong unsigned int saved_wr_start_at_switch_to_srt;\n\tstruct bfq_ttime saved_ttime;\n\tunsigned int saved_wr_cur_max_time;\n\tunsigned int saved_inject_limit;\n\tlong unsigned int saved_decrease_time_jif;\n\tlong: 32;\n\tu64 saved_last_serv_time_ns;\n\tstruct bfq_queue *stable_merge_bfqq;\n\tbool stably_merged;\n};\n\nstruct bfq_io_cq {\n\tstruct io_cq icq;\n\tstruct bfq_queue *bfqq[16];\n\tint ioprio;\n\tstruct bfq_iocq_bfqq_data bfqq_data[8];\n\tunsigned int requests;\n\tlong: 32;\n};\n\nstruct bfq_weight_counter {\n\tunsigned int weight;\n\tunsigned int num_active;\n\tstruct rb_node weights_node;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bgmac_slot_info {\n\tunion {\n\t\tstruct sk_buff *skb;\n\t\tvoid *buf;\n\t};\n\tdma_addr_t dma_addr;\n};\n\nstruct bgmac_dma_desc;\n\nstruct bgmac_dma_ring {\n\tu32 start;\n\tu32 end;\n\tstruct bgmac_dma_desc *cpu_base;\n\tdma_addr_t dma_base;\n\tu32 index_base;\n\tu16 mmio_base;\n\tbool unaligned;\n\tstruct bgmac_slot_info slots[512];\n};\n\nstruct bgmac {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *base;\n\t\t\tvoid *idm_base;\n\t\t\tvoid *nicpm_base;\n\t\t} plat;\n\t\tstruct {\n\t\t\tstruct bcma_device *core;\n\t\t\tstruct bcma_device *cmn;\n\t\t} bcma;\n\t};\n\tstruct device *dev;\n\tstruct device *dma_dev;\n\tu32 feature_flags;\n\tstruct net_device *net_dev;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tstruct mii_bus *mii_bus;\n\tstruct bgmac_dma_ring tx_ring[4];\n\tstruct bgmac_dma_ring rx_ring[1];\n\tbool stats_grabbed;\n\tu32 mib_tx_regs[43];\n\tu32 mib_rx_regs[31];\n\tint irq;\n\tu32 int_mask;\n\tbool in_init;\n\tint mac_speed;\n\tint mac_duplex;\n\tu8 phyaddr;\n\tbool has_robosw;\n\tbool loopback;\n\tu32 (*read)(struct bgmac *, u16);\n\tvoid (*write)(struct bgmac *, u16, u32);\n\tu32 (*idm_read)(struct bgmac *, u16);\n\tvoid (*idm_write)(struct bgmac *, u16, u32);\n\tbool (*clk_enabled)(struct bgmac *);\n\tvoid (*clk_enable)(struct bgmac *, u32);\n\tvoid (*cco_ctl_maskset)(struct bgmac *, u32, u32, u32);\n\tu32 (*get_bus_clock)(struct bgmac *);\n\tvoid (*cmn_maskset32)(struct bgmac *, u16, u32, u32);\n\tint (*phy_connect)(struct bgmac *);\n};\n\nstruct bgmac_dma_desc {\n\t__le32 ctl0;\n\t__le32 ctl1;\n\t__le32 addr_low;\n\t__le32 addr_high;\n};\n\nstruct bgmac_rx_header {\n\t__le16 len;\n\t__le16 flags;\n\t__le16 pad[12];\n};\n\nstruct bgmac_stat {\n\tu8 size;\n\tu32 offset;\n\tconst char *name;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n};\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tlong: 32;\n\tu64 bc_dun[4];\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tlong: 32;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct fsverity_info;\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct fsverity_info *vi;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bl_dev_msg {\n\tint32_t status;\n\tuint32_t major;\n\tuint32_t minor;\n};\n\nstruct bl_trig_notifier {\n\tstruct led_classdev *led;\n\tint brightness;\n\tint old_status;\n\tunsigned int invert;\n\tstruct list_head entry;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tlong: 32;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tlong: 32;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bio bio;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n\tlong: 32;\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[64];\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct mft_inode;\n\nstruct bmp_buf {\n\tstruct ATTRIB *b;\n\tstruct mft_inode *mi;\n\tstruct buffer_head *bh;\n\tulong *buf;\n\tsize_t bit;\n\tu32 nbits;\n\tu64 new_valid;\n};\n\nstruct software_node;\n\nstruct spi_board_info {\n\tchar modalias[32];\n\tconst void *platform_data;\n\tconst struct software_node *swnode;\n\tvoid *controller_data;\n\tint irq;\n\tu32 max_speed_hz;\n\tu16 bus_num;\n\tu16 chip_select;\n\tu32 mode;\n};\n\nstruct boardinfo {\n\tstruct list_head list;\n\tstruct spi_board_info board_info;\n};\n\nstruct boot_rom_geometry {\n\tunsigned int stride_size_in_pages;\n\tunsigned int search_area_stride_exponent;\n};\n\nstruct boot_triggers {\n\tconst char *event;\n\tchar *trigger;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct bp_slots_histogram {\n\tatomic_t *count;\n};\n\nstruct bp_cpuinfo {\n\tunsigned int cpu_pinned;\n\tstruct bp_slots_histogram tsk_pinned;\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tlong: 32;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tlong: 32;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tlong: 32;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n\tlong: 32;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct bpf_prog;\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n\tlong: 32;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tlong: 32;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n\tlong: 32;\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\tlong: 32;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t\tlong: 32;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\tlong: 32;\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\tlong: 32;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t\tlong: 32;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t\tlong: 32;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\tlong: 32;\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t\tlong: 32;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 32;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n\tlong: 32;\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\tlong: 32;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\traw_spinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n\tlong: 32;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n\tlong: 32;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct skb_ext;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\t__u8 active_extensions;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tstruct skb_ext *extensions;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_rxq_info;\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t\tu64 frame_sz_flags_init;\n\t};\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tlong: 32;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\nstruct pt_regs {\n\tlong unsigned int uregs[18];\n};\n\ntypedef struct pt_regs bpf_user_pt_regs_t;\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_sample_data;\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tlong: 32;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n\tlong: 32;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tlong: 32;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tlong: 32;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n\tlong: 32;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n\tlong: 32;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n\tlong: 32;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tlong: 32;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t\tlong: 32;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tlong: 32;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n\tlong: 32;\n};\n\nstruct bpf_cgroup_storage;\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tlong: 32;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n\tlong: 32;\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n\tlong: 32;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tlong: 32;\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n\tlong: 32;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n\tlong: 32;\n};\n\nstruct obj_cgroup;\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tlong: 32;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 32;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 32;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tlong: 32;\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n\tlong: 32;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct dma_buf;\n\nstruct bpf_iter__dmabuf {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct dma_buf *dmabuf;\n\t};\n};\n\nstruct fib6_info;\n\nstruct bpf_iter__ipv6_route {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct fib6_info *rt;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tlong: 32;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n\tlong: 32;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 32;\n\tint bucket;\n\tlong: 32;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n\tlong: 32;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct cgroup_subsys_state;\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n\tlong: 32;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n\tlong: 32;\n};\n\nstruct bpf_iter_dmabuf {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_dmabuf_kern {\n\tstruct dma_buf *dmabuf;\n\tlong: 32;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n\tlong: 32;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tlong: 32;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 32;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tlong: 32;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n\tlong: 32;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n\tlong: 32;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tlong: 32;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t\tlong: 32;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tlong: 32;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\tlong: 32;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\tlong: 32;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t\tlong: 32;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t\tlong: 32;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tlong: 32;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\tlong: 32;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\tlong: 32;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n\tlong: 32;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tlong: 32;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n\tlong: 32;\n};\n\nstruct rqspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tu32 locked;\n\t};\n};\n\ntypedef struct rqspinlock rqspinlock_t;\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tlong: 32;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tlong: 32;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tlong: 32;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n\tlong: 32;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tlong: 32;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tlong: 32;\n\tatomic64_t revision;\n\tu32 count;\n\tlong: 32;\n};\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n\tlong: 32;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tlong: 32;\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_perf_link {\n\tstruct bpf_link link;\n\tstruct file *perf_file;\n\tlong: 32;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_arena;\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n\tlong: 32;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct tracepoint;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tlong: 32;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tlong: 32;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tlong: 32;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\trqspinlock_t spinlock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_t busy;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int consumer_pos;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n\tlong: 32;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n\tlong: 32;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct bpf_session_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tbool is_return;\n\tvoid *data;\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tlong: 32;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nstruct stack_map_bucket;\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n\tlong: 32;\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bpf_dummy_ops data;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n\tlong: 32;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_ext_ops data;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tlong: 32;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tlong: 32;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tlong: 32;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n\tlong: 32;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tlong: 32;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n\tlong: 32;\n};\n\nunion perf_sample_weight {\n\t__u64 full;\n\tstruct {\n\t\t__u32 var1_dw;\n\t\t__u16 var2_w;\n\t\t__u16 var3_w;\n\t};\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_op: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_blk: 3;\n\t\t__u64 mem_hops: 3;\n\t\t__u64 mem_region: 5;\n\t\t__u64 mem_rsvd: 13;\n\t};\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n\tlong: 32;\n};\n\nstruct perf_callchain_entry;\n\nstruct perf_raw_record;\n\nstruct perf_branch_stack;\n\nstruct perf_sample_data {\n\tu64 sample_flags;\n\tu64 period;\n\tu64 dyn_size;\n\tu64 type;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tu64 ip;\n\tstruct perf_callchain_entry *callchain;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 *br_stack_cntr;\n\tunion perf_sample_weight weight;\n\tunion perf_mem_data_src data_src;\n\tu64 txn;\n\tstruct perf_regs regs_user;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 stream_id;\n\tu64 cgroup;\n\tu64 addr;\n\tu64 phys_addr;\n\tu64 data_page_size;\n\tu64 code_page_size;\n\tu64 aux_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[38];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n\tlong: 32;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *, __u64 *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *, __u64 *);\n\tbool (*filter)(struct uprobe_consumer *, struct mm_struct *);\n\tstruct list_head cons_node;\n\tlong: 32;\n\t__u64 id;\n};\n\nstruct bpf_uprobe_multi_link;\n\nstruct uprobe;\n\nstruct bpf_uprobe {\n\tstruct bpf_uprobe_multi_link *link;\n\tlong: 32;\n\tloff_t offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong: 32;\n\tu64 cookie;\n\tstruct uprobe *uprobe;\n\tlong: 32;\n\tstruct uprobe_consumer consumer;\n\tbool session;\n\tlong: 32;\n};\n\nstruct bpf_uprobe_multi_link {\n\tstruct path path;\n\tstruct bpf_link link;\n\tu32 cnt;\n\tstruct bpf_uprobe *uprobes;\n\tstruct task_struct *task;\n\tlong: 32;\n};\n\nstruct bpf_uprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tlong unsigned int entry_ip;\n\tstruct bpf_uprobe *uprobe;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tlong: 32;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tlong: 32;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n\tlong: 32;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpf_xfrm_state {\n\t__u32 reqid;\n\t__u32 spi;\n\t__u16 family;\n\t__u16 ext;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n};\n\nstruct bpf_xfrm_state_opts {\n\ts32 error;\n\ts32 netns_id;\n\tu32 mark;\n\txfrm_address_t daddr;\n\t__be32 spi;\n\tu8 proto;\n\tu16 family;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct brcm_ahci_priv {\n\tstruct device *dev;\n\tvoid *top_ctrl;\n\tu32 port_mask;\n\tu32 quirks;\n\tenum brcm_ahci_version version;\n\tstruct reset_control *rcdev_rescal;\n\tstruct reset_control *rcdev_ahci;\n};\n\nstruct brcm_msi {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct device_node *np;\n\tstruct irq_domain *inner_domain;\n\tstruct mutex lock;\n\tlong: 32;\n\tu64 target_addr;\n\tint irq;\n\tlong unsigned int used[1];\n\tbool legacy;\n\tint legacy_shift;\n\tint nr;\n\tvoid *intr_base;\n};\n\nstruct brcm_nand_dma_desc {\n\tu32 next_desc;\n\tu32 next_desc_ext;\n\tu32 cmd_irq;\n\tu32 dram_addr;\n\tu32 dram_addr_ext;\n\tu32 tfr_len;\n\tu32 total_len;\n\tu32 flash_addr;\n\tu32 flash_addr_ext;\n\tu32 cs;\n\tu32 pad2[5];\n\tu32 status_valid;\n};\n\nstruct subdev_regulators;\n\nstruct pcie_cfg_data;\n\nstruct brcm_pcie {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct device_node *np;\n\tbool ssc;\n\tint gen;\n\tu64 msi_target_addr;\n\tstruct brcm_msi *msi;\n\tstruct reset_control *rescal;\n\tstruct reset_control *perst_reset;\n\tstruct reset_control *bridge_reset;\n\tstruct reset_control *swinit_reset;\n\tint num_memc;\n\tu64 memc_size[3];\n\tu32 hw_rev;\n\tstruct subdev_regulators *sr;\n\tbool ep_wakeup_capable;\n\tconst struct pcie_cfg_data *cfg;\n\tbool bridge_in_reset;\n\tstruct notifier_block die_notifier;\n\tstruct notifier_block panic_notifier;\n\tspinlock_t bridge_lock;\n};\n\nstruct brcm_rescal_reset {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct brcm_sata_phy;\n\nstruct brcm_sata_port {\n\tint portnum;\n\tstruct phy *phy;\n\tstruct brcm_sata_phy *phy_priv;\n\tbool ssc_en;\n\tenum brcm_sata_phy_rxaeq_mode rxaeq_mode;\n\tu32 rxaeq_val;\n\tu32 tx_amplitude_val;\n};\n\nstruct brcm_sata_phy {\n\tstruct device *dev;\n\tvoid *phy_base;\n\tvoid *ctrl_base;\n\tenum brcm_sata_phy_version version;\n\tstruct brcm_sata_port phys[2];\n};\n\nstruct brcmnand_cfg {\n\tu64 device_size;\n\tunsigned int block_size;\n\tunsigned int page_size;\n\tunsigned int spare_area_size;\n\tunsigned int device_width;\n\tunsigned int col_adr_bytes;\n\tunsigned int blk_adr_bytes;\n\tunsigned int ful_adr_bytes;\n\tunsigned int sector_size_1k;\n\tunsigned int ecc_level;\n\tu32 acc_control;\n\tu32 config;\n\tu32 config_ext;\n\tu32 timing_1;\n\tu32 timing_2;\n};\n\nstruct brcmnand_host;\n\nstruct brcmnand_controller {\n\tstruct device *dev;\n\tstruct nand_controller controller;\n\tvoid *nand_base;\n\tvoid *nand_fc;\n\tvoid *flash_dma_base;\n\tint irq;\n\tunsigned int dma_irq;\n\tint nand_version;\n\tstruct brcmnand_soc *soc;\n\tstruct clk *clk;\n\tint cmd_pending;\n\tbool dma_pending;\n\tbool edu_pending;\n\tstruct completion done;\n\tstruct completion dma_done;\n\tstruct completion edu_done;\n\tstruct list_head host_list;\n\tint (*check_instr)(struct nand_chip *, const struct nand_operation *);\n\tint (*exec_instr)(struct nand_chip *, const struct nand_operation *);\n\tconst u16 *edu_offsets;\n\tvoid *edu_base;\n\tint edu_irq;\n\tint edu_count;\n\tlong: 32;\n\tu64 edu_dram_addr;\n\tu32 edu_ext_addr;\n\tu32 edu_cmd;\n\tu32 edu_config;\n\tint sas;\n\tint sector_size_1k;\n\tu8 *oob;\n\tconst u16 *flash_dma_offsets;\n\tstruct brcm_nand_dma_desc *dma_desc;\n\tdma_addr_t dma_pa;\n\tint (*dma_trans)(struct brcmnand_host *, u64, u32 *, u8 *, u32, u8);\n\tu8 flash_cache[512];\n\tconst u16 *reg_offsets;\n\tunsigned int reg_spacing;\n\tconst u8 *cs_offsets;\n\tconst u8 *cs0_offsets;\n\tunsigned int max_block_size;\n\tconst unsigned int *block_sizes;\n\tunsigned int max_page_size;\n\tconst unsigned int *page_sizes;\n\tunsigned int page_size_shift;\n\tunsigned int max_oob;\n\tu32 ecc_level_shift;\n\tu32 features;\n\tu32 nand_cs_nand_select;\n\tu32 nand_cs_nand_xor;\n\tu32 corr_stat_threshold;\n\tu32 flash_dma_mode;\n\tu32 flash_edu_mode;\n\tbool pio_poll_mode;\n};\n\nstruct brcmnand_host {\n\tstruct list_head node;\n\tstruct nand_chip chip;\n\tstruct platform_device *pdev;\n\tint cs;\n\tstruct brcmnand_cfg hwcfg;\n\tstruct brcmnand_controller *ctrl;\n\tlong: 32;\n};\n\nstruct brcmnand_io_ops {\n\tu32 (*read_reg)(struct brcmnand_soc *, u32);\n\tvoid (*write_reg)(struct brcmnand_soc *, u32, u32);\n};\n\nstruct brcmnand_platform_data {\n\tint chip_select;\n\tconst char * const *part_probe_types;\n\tunsigned int ecc_stepsize;\n\tunsigned int ecc_strength;\n};\n\nstruct dpfe_api;\n\nstruct brcmstb_dpfe_priv {\n\tvoid *regs;\n\tvoid *dmem;\n\tvoid *imem;\n\tstruct device *dev;\n\tconst struct dpfe_api *dpfe_api;\n\tstruct mutex lock;\n};\n\nstruct brcmstb_gisb_arb_device {\n\tvoid *base;\n\tconst int *gisb_offsets;\n\tbool big_endian;\n\tstruct mutex lock;\n\tstruct list_head next;\n\tu32 valid_mask;\n\tconst char *master_names[32];\n\tu32 saved_timeout;\n};\n\nstruct brcmstb_gpio_priv;\n\nstruct brcmstb_gpio_bank {\n\tstruct list_head node;\n\tint id;\n\tstruct gpio_generic_chip chip;\n\tstruct brcmstb_gpio_priv *parent_priv;\n\tu32 width;\n\tu32 wake_active;\n\tu32 saved_regs[7];\n};\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct brcmstb_gpio_priv {\n\tstruct list_head bank_list;\n\tvoid *reg_base;\n\tstruct platform_device *pdev;\n\tstruct irq_domain *irq_domain;\n\tstruct irq_chip irq_chip;\n\tint parent_irq;\n\tint num_gpios;\n\tint parent_wake_irq;\n};\n\nstruct bsc_regs;\n\nstruct brcmstb_i2c_dev {\n\tstruct device *device;\n\tvoid *base;\n\tint irq;\n\tstruct bsc_regs *bsc_regmap;\n\tstruct i2c_adapter adapter;\n\tstruct completion done;\n\tu32 clk_freq_hz;\n\tint data_regsz;\n\tbool atomic;\n\tlong: 32;\n};\n\nstruct brcmstb_intc_init_params {\n\tirq_flow_handler_t handler;\n\tint cpu_status;\n\tint cpu_clear;\n\tint cpu_mask_status;\n\tint cpu_mask_set;\n\tint cpu_mask_clear;\n};\n\nstruct irq_chip_generic;\n\nstruct brcmstb_l2_intc_data {\n\tstruct irq_domain *domain;\n\tstruct irq_chip_generic *gc;\n\tint status_offset;\n\tint mask_offset;\n\tbool can_wake;\n\tu32 saved_mask;\n};\n\nstruct sdhci_host;\n\nstruct mmc_ios;\n\nstruct sdhci_ops;\n\nstruct brcmstb_match_priv {\n\tvoid (*cfginit)(struct sdhci_host *);\n\tvoid (*hs400es)(struct mmc_host *, struct mmc_ios *);\n\tvoid (*save_restore_regs)(struct mmc_host *, int);\n\tstruct sdhci_ops *ops;\n\tconst unsigned int flags;\n};\n\nstruct brcmstb_memc {\n\tstruct device *dev;\n\tvoid *ddr_ctrl;\n\tunsigned int timeout_cycles;\n\tu32 frequency;\n\tu32 srpd_offset;\n};\n\nstruct brcmstb_memc_data {\n\tu32 srpd_offset;\n};\n\nstruct brcmstb_reset {\n\tvoid *base;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct brcmstb_waketmr {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tvoid *base;\n\tunsigned int wake_irq;\n\tunsigned int alarm_irq;\n\tstruct notifier_block reboot_notifier;\n\tstruct clk *clk;\n\tu32 rate;\n\tlong unsigned int rtc_alarm;\n\tbool alarm_en;\n\tbool alarm_expired;\n};\n\nstruct uart_8250_port;\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_tx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan *rxchan;\n\tstruct dma_chan *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct brcmuart_priv {\n\tint line;\n\tstruct clk *baud_mux_clk;\n\tlong unsigned int default_mux_rate;\n\tu32 real_rates[4];\n\tconst u32 *rate_table;\n\tktime_t char_wait;\n\tstruct uart_port *up;\n\tlong: 32;\n\tstruct hrtimer hrt;\n\tbool shutdown;\n\tbool dma_enabled;\n\tstruct uart_8250_dma dma;\n\tvoid *regs[5];\n\tdma_addr_t rx_addr;\n\tvoid *rx_bufs;\n\tsize_t rx_size;\n\tint rx_next_buf;\n\tdma_addr_t tx_addr;\n\tvoid *tx_buf;\n\tsize_t tx_size;\n\tbool tx_running;\n\tbool rx_running;\n\tstruct dentry *debugfs_dir;\n\tu64 dma_rx_partial_buf;\n\tu64 dma_rx_full_buf;\n\tu32 rx_bad_timeout_late_char;\n\tu32 rx_bad_timeout_no_char;\n\tu32 rx_missing_close_timeout;\n\tu32 rx_err;\n\tu32 rx_timeout;\n\tu32 rx_abort;\n\tu32 saved_mctrl;\n\tlong: 32;\n};\n\nstruct brd_device {\n\tint brd_number;\n\tstruct gendisk *brd_disk;\n\tstruct list_head brd_list;\n\tstruct xarray brd_pages;\n\tlong: 32;\n\tu64 brd_nr_pages;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct broken_edid {\n\tu8 manufacturer[4];\n\tu32 model;\n\tu32 fix;\n};\n\nstruct bsc_clk_param {\n\tu32 hz;\n\tu32 scl_mask;\n\tu32 div_mask;\n};\n\nstruct bsc_regs {\n\tu32 chip_address;\n\tu32 data_in[8];\n\tu32 cnt_reg;\n\tu32 ctl_reg;\n\tu32 iic_enable;\n\tu32 data_out[8];\n\tu32 ctlhi_reg;\n\tu32 scl_param;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tlong: 32;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n\tlong: 32;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[60];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_ptr {\n\tvoid *ptr;\n\t__u32 type_id;\n\t__u32 flags;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, va_list);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nunion ubifs_key {\n\tuint8_t u8[8];\n\tuint32_t u32[2];\n\tuint64_t u64[1];\n\t__le32 j32[2];\n};\n\nstruct ubifs_znode;\n\nstruct ubifs_zbranch {\n\tunion ubifs_key key;\n\tunion {\n\t\tstruct ubifs_znode *znode;\n\t\tvoid *leaf;\n\t};\n\tint lnum;\n\tint offs;\n\tint len;\n\tu8 hash[0];\n};\n\nstruct bu_info {\n\tunion ubifs_key key;\n\tstruct ubifs_zbranch zbranch[32];\n\tvoid *buf;\n\tint buf_len;\n\tint gc_seq;\n\tint cnt;\n\tint blk_cnt;\n\tint eof;\n};\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct ubifs_bud;\n\nstruct bud_entry {\n\tstruct list_head list;\n\tstruct ubifs_bud *bud;\n\tlong: 32;\n\tlong long unsigned int sqnum;\n\tint free;\n\tint dirty;\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\nstruct bufdesc {\n\t__le16 cbd_datlen;\n\t__le16 cbd_sc;\n\t__le32 cbd_bufaddr;\n};\n\nstruct bufdesc_ex {\n\tstruct bufdesc desc;\n\t__le32 cbd_esc;\n\t__le32 cbd_prot;\n\t__le32 cbd_bdu;\n\t__le32 ts;\n\t__le16 res0[4];\n};\n\nstruct bufdesc_prop {\n\tint qid;\n\tstruct bufdesc *base;\n\tstruct bufdesc *last;\n\tstruct bufdesc *cur;\n\tvoid *reg_desc_active;\n\tdma_addr_t dma;\n\tshort unsigned int ring_size;\n\tunsigned char dsize;\n\tunsigned char dsize_log2;\n};\n\nstruct buffer {\n\tsize_t size;\n\tchar data[0];\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n\tlong: 32;\n};\n\nstruct buffer_data_read_page {\n\tunsigned int order;\n\tstruct buffer_data_page *data;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tlong: 32;\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tunsigned int order;\n\tu32 id: 30;\n\tu32 range: 1;\n\tstruct buffer_data_page *page;\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct host1x_syncpt;\n\nstruct host1x_client;\n\nstruct buffer_timeout {\n\tstruct delayed_work wq;\n\tbool initialized;\n\tstruct host1x_syncpt *syncpt;\n\tu32 syncpt_val;\n\tktime_t start_ktime;\n\tstruct host1x_client *client;\n\tlong: 32;\n};\n\nstruct bug_entry {\n\tlong unsigned int bug_addr;\n\tconst char *file;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct bulk_cb_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 DataTransferLength;\n\t__u8 Flags;\n\t__u8 Lun;\n\t__u8 Length;\n\t__u8 CDB[16];\n};\n\nstruct bulk_cs_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 Residue;\n\t__u8 Status;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_speed_cfg {\n\tuint8_t time_m;\n\tuint8_t time_n;\n\tuint8_t prescale;\n\tuint8_t time_p;\n\tuint8_t no_div;\n\tuint8_t time_div;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct cache_head;\n\nstruct cache_deferred_req {\n\tstruct hlist_node hash;\n\tstruct list_head recent;\n\tstruct cache_head *item;\n\tvoid *owner;\n\tvoid (*revisit)(struct cache_deferred_req *, int);\n};\n\nstruct cache_detail {\n\tstruct module *owner;\n\tint hash_size;\n\tstruct hlist_head *hash_table;\n\tspinlock_t hash_lock;\n\tchar *name;\n\tvoid (*cache_put)(struct kref *);\n\tint (*cache_upcall)(struct cache_detail *, struct cache_head *);\n\tvoid (*cache_request)(struct cache_detail *, struct cache_head *, char **, int *);\n\tint (*cache_parse)(struct cache_detail *, char *, int);\n\tint (*cache_show)(struct seq_file *, struct cache_detail *, struct cache_head *);\n\tvoid (*warn_no_listener)(struct cache_detail *, int);\n\tstruct cache_head * (*alloc)(void);\n\tvoid (*flush)(void);\n\tint (*match)(struct cache_head *, struct cache_head *);\n\tvoid (*init)(struct cache_head *, struct cache_head *);\n\tvoid (*update)(struct cache_head *, struct cache_head *);\n\ttime64_t flush_time;\n\tstruct list_head others;\n\ttime64_t nextcheck;\n\tint entries;\n\tstruct list_head queue;\n\tatomic_t writers;\n\ttime64_t last_close;\n\ttime64_t last_warn;\n\tunion {\n\t\tstruct proc_dir_entry *procfs;\n\t\tstruct dentry *pipefs;\n\t};\n\tstruct net *net;\n};\n\nstruct cache_head {\n\tstruct hlist_node cache_list;\n\ttime64_t expiry_time;\n\ttime64_t last_refresh;\n\tstruct kref ref;\n\tlong unsigned int flags;\n};\n\nstruct cache_queue {\n\tstruct list_head list;\n\tint reader;\n};\n\nstruct cache_reader {\n\tstruct cache_queue q;\n\tint offset;\n};\n\nstruct cache_req {\n\tstruct cache_deferred_req * (*defer)(struct cache_req *);\n\tlong unsigned int thread_wait;\n};\n\nstruct cache_request {\n\tstruct cache_queue q;\n\tstruct cache_head *item;\n\tchar *buf;\n\tint len;\n\tint readers;\n};\n\nstruct cache_type_info {\n\tconst char *size_prop;\n\tconst char *line_size_props[2];\n\tconst char *nr_sets_prop;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachepolicy {\n\tconst char policy[16];\n\tunsigned int cr_mask;\n\tpmdval_t pmd;\n\tpteval_t pte;\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct cb_process_state;\n\nstruct xdr_stream;\n\nstruct callback_op {\n\t__be32 (*process_op)(void *, void *, struct cb_process_state *);\n\t__be32 (*decode_args)(struct svc_rqst *, struct xdr_stream *, void *);\n\t__be32 (*encode_res)(struct svc_rqst *, struct xdr_stream *, const void *);\n\tlong int res_maxsize;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nstruct can_berr_counter {\n\t__u16 txerr;\n\t__u16 rxerr;\n};\n\nstruct can_bittiming {\n\t__u32 bitrate;\n\t__u32 sample_point;\n\t__u32 tq;\n\t__u32 prop_seg;\n\t__u32 phase_seg1;\n\t__u32 phase_seg2;\n\t__u32 sjw;\n\t__u32 brp;\n};\n\nstruct can_bittiming_const {\n\tchar name[16];\n\t__u32 tseg1_min;\n\t__u32 tseg1_max;\n\t__u32 tseg2_min;\n\t__u32 tseg2_max;\n\t__u32 sjw_max;\n\t__u32 brp_min;\n\t__u32 brp_max;\n\t__u32 brp_inc;\n};\n\nstruct can_filter {\n\tcanid_t can_id;\n\tcanid_t can_mask;\n};\n\nstruct can_can_gw {\n\tstruct can_filter filter;\n\tint src_idx;\n\tint dst_idx;\n};\n\nstruct can_clock {\n\t__u32 freq;\n};\n\nstruct can_ctrlmode {\n\t__u32 mask;\n\t__u32 flags;\n};\n\nstruct can_dev_rcv_lists {\n\tstruct hlist_head rx[4];\n\tstruct hlist_head rx_sff[2048];\n\tstruct hlist_head rx_eff[1024];\n\tint entries;\n};\n\nstruct can_device_stats {\n\t__u32 bus_error;\n\t__u32 error_warning;\n\t__u32 error_passive;\n\t__u32 bus_off;\n\t__u32 arbitration_lost;\n\t__u32 restarts;\n};\n\nstruct j1939_priv;\n\nstruct can_ml_priv {\n\tstruct can_dev_rcv_lists dev_rcv_lists;\n\tstruct j1939_priv *j1939_priv;\n\tu32 can_cap;\n};\n\nstruct can_pkg_stats {\n\tlong unsigned int jiffies_init;\n\tatomic_long_t rx_frames;\n\tatomic_long_t tx_frames;\n\tatomic_long_t matches;\n\tlong unsigned int total_rx_rate;\n\tlong unsigned int total_tx_rate;\n\tlong unsigned int total_rx_match_ratio;\n\tlong unsigned int current_rx_rate;\n\tlong unsigned int current_tx_rate;\n\tlong unsigned int current_rx_match_ratio;\n\tlong unsigned int max_rx_rate;\n\tlong unsigned int max_tx_rate;\n\tlong unsigned int max_rx_match_ratio;\n\tatomic_long_t rx_frames_delta;\n\tatomic_long_t tx_frames_delta;\n\tatomic_long_t matches_delta;\n};\n\nstruct can_tdc {\n\tu32 tdcv;\n\tu32 tdco;\n\tu32 tdcf;\n};\n\nstruct can_pwm {\n\tu32 pwms;\n\tu32 pwml;\n\tu32 pwmo;\n};\n\nstruct can_tdc_const;\n\nstruct can_pwm_const;\n\nstruct data_bittiming_params {\n\tconst struct can_bittiming_const *data_bittiming_const;\n\tstruct can_bittiming data_bittiming;\n\tconst struct can_tdc_const *tdc_const;\n\tconst struct can_pwm_const *pwm_const;\n\tunion {\n\t\tstruct can_tdc tdc;\n\t\tstruct can_pwm pwm;\n\t};\n\tconst u32 *data_bitrate_const;\n\tunsigned int data_bitrate_const_cnt;\n\tint (*do_set_data_bittiming)(struct net_device *);\n\tint (*do_get_auto_tdcv)(const struct net_device *, u32 *);\n};\n\nstruct can_priv {\n\tstruct net_device *dev;\n\tstruct can_device_stats can_stats;\n\tconst struct can_bittiming_const *bittiming_const;\n\tstruct can_bittiming bittiming;\n\tstruct data_bittiming_params fd;\n\tstruct data_bittiming_params xl;\n\tunsigned int bitrate_const_cnt;\n\tconst u32 *bitrate_const;\n\tu32 bitrate_max;\n\tstruct can_clock clock;\n\tunsigned int termination_const_cnt;\n\tconst u16 *termination_const;\n\tu16 termination;\n\tstruct gpio_desc *termination_gpio;\n\tu16 termination_gpio_ohms[2];\n\tunsigned int echo_skb_max;\n\tstruct sk_buff **echo_skb;\n\tenum can_state state;\n\tu32 ctrlmode;\n\tu32 ctrlmode_supported;\n\tint restart_ms;\n\tstruct delayed_work restart_work;\n\tint (*do_set_bittiming)(struct net_device *);\n\tint (*do_set_mode)(struct net_device *, enum can_mode);\n\tint (*do_set_termination)(struct net_device *, u16);\n\tint (*do_get_state)(const struct net_device *, enum can_state *);\n\tint (*do_get_berr_counter)(const struct net_device *, struct can_berr_counter *);\n};\n\nstruct proto_ops;\n\nstruct can_proto {\n\tint type;\n\tint protocol;\n\tconst struct proto_ops *ops;\n\tstruct proto *prot;\n};\n\nstruct can_pwm_const {\n\tu32 pwms_min;\n\tu32 pwms_max;\n\tu32 pwml_min;\n\tu32 pwml_max;\n\tu32 pwmo_min;\n\tu32 pwmo_max;\n};\n\nstruct can_raw_vcid_options {\n\t__u8 flags;\n\t__u8 tx_vcid;\n\t__u8 rx_vcid;\n\t__u8 rx_vcid_mask;\n};\n\nstruct can_rcv_lists_stats {\n\tlong unsigned int stats_reset;\n\tlong unsigned int user_reset;\n\tlong unsigned int rcv_entries;\n\tlong unsigned int rcv_entries_max;\n};\n\nstruct can_rx_offload {\n\tstruct net_device *dev;\n\tstruct sk_buff * (*mailbox_read)(struct can_rx_offload *, unsigned int, u32 *, bool);\n\tstruct sk_buff_head skb_queue;\n\tstruct sk_buff_head skb_irq_queue;\n\tu32 skb_queue_len_max;\n\tunsigned int mb_first;\n\tunsigned int mb_last;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tbool inc;\n\tlong: 32;\n};\n\nstruct can_rx_offload_cb {\n\tu32 timestamp;\n};\n\nstruct can_skb_ext {\n\tint can_iif;\n\tu16 can_framelen;\n\tu8 can_gw_hops;\n\tu8 can_ext_flags;\n};\n\nstruct can_tdc_const {\n\tu32 tdcv_min;\n\tu32 tdcv_max;\n\tu32 tdco_min;\n\tu32 tdco_max;\n\tu32 tdcf_min;\n\tu32 tdcf_max;\n};\n\nstruct canxl_frame {\n\tcanid_t prio;\n\t__u8 flags;\n\t__u8 sdt;\n\t__u16 len;\n\t__u32 af;\n\t__u8 data[2048];\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct cb_compound_hdr_arg {\n\tunsigned int taglen;\n\tconst char *tag;\n\tunsigned int minorversion;\n\tunsigned int cb_ident;\n\tunsigned int nops;\n};\n\nstruct cb_compound_hdr_res {\n\t__be32 *status;\n\tunsigned int taglen;\n\tconst char *tag;\n\t__be32 *nops;\n};\n\nstruct cb_devicenotifyitem;\n\nstruct cb_devicenotifyargs {\n\tuint32_t ndevs;\n\tstruct cb_devicenotifyitem *devs;\n};\n\nstruct nfs4_deviceid {\n\tchar data[16];\n};\n\nstruct cb_devicenotifyitem {\n\tuint32_t cbd_notify_type;\n\tuint32_t cbd_layout_type;\n\tstruct nfs4_deviceid cbd_dev_id;\n\tuint32_t cbd_immediate;\n};\n\nstruct nfs_fh {\n\tshort unsigned int size;\n\tunsigned char data[128];\n};\n\nstruct cb_getattrargs {\n\tstruct nfs_fh fh;\n\tuint32_t bitmap[3];\n};\n\nstruct cb_getattrres {\n\t__be32 status;\n\tuint32_t bitmap[3];\n\tuint64_t size;\n\tuint64_t change_attr;\n\tstruct timespec64 atime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 mtime;\n};\n\nstruct pnfs_layout_range {\n\tu32 iomode;\n\tlong: 32;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct nfs4_stateid_struct {\n\tunion {\n\t\tchar data[16];\n\t\tstruct {\n\t\t\t__be32 seqid;\n\t\t\tchar other[12];\n\t\t};\n\t};\n\tenum {\n\t\tNFS4_INVALID_STATEID_TYPE = 0,\n\t\tNFS4_SPECIAL_STATEID_TYPE = 1,\n\t\tNFS4_OPEN_STATEID_TYPE = 2,\n\t\tNFS4_LOCK_STATEID_TYPE = 3,\n\t\tNFS4_DELEGATION_STATEID_TYPE = 4,\n\t\tNFS4_LAYOUT_STATEID_TYPE = 5,\n\t\tNFS4_PNFS_DS_STATEID_TYPE = 6,\n\t\tNFS4_REVOKED_STATEID_TYPE = 7,\n\t\tNFS4_FREED_STATEID_TYPE = 8,\n\t} type;\n};\n\ntypedef struct nfs4_stateid_struct nfs4_stateid;\n\nstruct nfs_fsid {\n\tuint64_t major;\n\tuint64_t minor;\n};\n\nstruct cb_layoutrecallargs {\n\tuint32_t cbl_recall_type;\n\tuint32_t cbl_layout_type;\n\tuint32_t cbl_layoutchanged;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct nfs_fh cbl_fh;\n\t\t\tlong: 32;\n\t\t\tstruct pnfs_layout_range cbl_range;\n\t\t\tnfs4_stateid cbl_stateid;\n\t\t\tlong: 32;\n\t\t};\n\t\tstruct nfs_fsid cbl_fsid;\n\t};\n};\n\nstruct nfs_lowner {\n\t__u64 clientid;\n\t__u64 id;\n\tdev_t s_dev;\n\tlong: 32;\n};\n\nstruct cb_notify_lock_args {\n\tstruct nfs_fh cbnl_fh;\n\tlong: 32;\n\tstruct nfs_lowner cbnl_owner;\n\tbool cbnl_valid;\n\tlong: 32;\n};\n\nstruct nfs_write_verifier {\n\tchar data[8];\n};\n\nstruct nfs_writeverf {\n\tstruct nfs_write_verifier verifier;\n\tenum nfs3_stable_how committed;\n};\n\nstruct cb_offloadargs {\n\tstruct nfs_fh coa_fh;\n\tnfs4_stateid coa_stateid;\n\tuint32_t error;\n\tlong: 32;\n\tuint64_t wr_count;\n\tstruct nfs_writeverf wr_writeverf;\n\tlong: 32;\n};\n\nstruct nfs_client;\n\nstruct nfs4_slot;\n\nstruct cb_process_state {\n\tstruct nfs_client *clp;\n\tstruct nfs4_slot *slot;\n\tstruct net *net;\n\tu32 minorversion;\n\t__be32 drc_status;\n\tunsigned int referring_calls;\n};\n\nstruct cb_recallanyargs {\n\tuint32_t craa_objs_to_keep;\n\tuint32_t craa_type_mask;\n};\n\nstruct cb_recallargs {\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tuint32_t truncate;\n};\n\nstruct cb_recallslotargs {\n\tuint32_t crsa_target_highest_slotid;\n};\n\nstruct nfs4_sessionid {\n\tunsigned char data[16];\n};\n\nstruct referring_call_list;\n\nstruct cb_sequenceargs {\n\tstruct sockaddr *csa_addr;\n\tstruct nfs4_sessionid csa_sessionid;\n\tuint32_t csa_sequenceid;\n\tuint32_t csa_slotid;\n\tuint32_t csa_highestslotid;\n\tuint32_t csa_cachethis;\n\tuint32_t csa_nrclists;\n\tstruct referring_call_list *csa_rclists;\n};\n\nstruct cb_sequenceres {\n\t__be32 csr_status;\n\tstruct nfs4_sessionid csr_sessionid;\n\tuint32_t csr_sequenceid;\n\tuint32_t csr_slotid;\n\tuint32_t csr_highestslotid;\n\tuint32_t csr_target_highestslotid;\n};\n\nstruct cci_ace_port {\n\tvoid *base;\n\tlong unsigned int phys;\n\tenum cci_ace_port_type type;\n\tstruct device_node *dn;\n};\n\nstruct cci_nb_ports {\n\tunsigned int nb_ace;\n\tunsigned int nb_ace_lite;\n};\n\nstruct ccs_modesel_head {\n\t__u8 _r1;\n\t__u8 medium;\n\t__u8 _r2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_blocks_hi;\n\t__u8 number_blocks_med;\n\t__u8 number_blocks_lo;\n\t__u8 _r3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct ccsr_guts {\n\tu32 porpllsr;\n\tu32 porbmsr;\n\tu32 porimpscr;\n\tu32 pordevsr;\n\tu32 pordbgmsr;\n\tu32 pordevsr2;\n\tu8 res018[8];\n\tu32 porcir;\n\tu8 res024[12];\n\tu32 gpiocr;\n\tu8 res034[12];\n\tu32 gpoutdr;\n\tu8 res044[12];\n\tu32 gpindr;\n\tu8 res054[12];\n\tu32 pmuxcr;\n\tu32 pmuxcr2;\n\tu32 dmuxcr;\n\tu8 res06c[4];\n\tu32 devdisr;\n\tu32 devdisr2;\n\tu8 res078[4];\n\tu32 pmjcr;\n\tu32 powmgtcsr;\n\tu32 pmrccr;\n\tu32 pmpdccr;\n\tu32 pmcdr;\n\tu32 mcpsumr;\n\tu32 rstrscr;\n\tu32 ectrstcr;\n\tu32 autorstsr;\n\tu32 pvr;\n\tu32 svr;\n\tu8 res0a8[8];\n\tu32 rstcr;\n\tu8 res0b4[12];\n\tu32 iovselsr;\n\tu8 res0c4[60];\n\tu32 rcwsr[16];\n\tu8 res140[228];\n\tu32 iodelay1;\n\tu32 iodelay2;\n\tu8 res22c[984];\n\tu32 pamubypenr;\n\tu8 res608[504];\n\tu32 clkdvdr;\n\tu8 res804[252];\n\tu32 ircr;\n\tu8 res904[4];\n\tu32 dmacr;\n\tu8 res90c[8];\n\tu32 elbccr;\n\tu8 res918[520];\n\tu32 ddr1clkdr;\n\tu32 ddr2clkdr;\n\tu32 ddrclkdr;\n\tu8 resb2c[724];\n\tu32 clkocr;\n\tu8 rese04[12];\n\tu32 ddrdllcr;\n\tu8 rese14[12];\n\tu32 lbcdllcr;\n\tu32 cpfor;\n\tu8 rese28[220];\n\tu32 srds1cr0;\n\tu32 srds1cr1;\n\tu8 resf0c[32];\n\tu32 itcr;\n\tu8 resf30[16];\n\tu32 srds2cr0;\n\tu32 srds2cr1;\n};\n\nstruct ccu_common {\n\tvoid *base;\n\tu16 reg;\n\tu16 lock_reg;\n\tu32 prediv;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int features;\n\tspinlock_t *lock;\n\tstruct clk_hw hw;\n};\n\nstruct ccu_policy {\n\tstruct bcm_lvm_en enable;\n\tstruct bcm_policy_ctl control;\n};\n\nstruct clk_ops;\n\nstruct clk_parent_data;\n\nstruct clk_init_data {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tconst char * const *parent_names;\n\tconst struct clk_parent_data *parent_data;\n\tconst struct clk_hw **parent_hws;\n\tu8 num_parents;\n\tlong unsigned int flags;\n};\n\nstruct ccu_data;\n\nstruct peri_clk_data;\n\nstruct kona_clk {\n\tstruct clk_hw hw;\n\tstruct clk_init_data init_data;\n\tstruct ccu_data *ccu;\n\tenum bcm_clk_type type;\n\tunion {\n\t\tvoid *data;\n\t\tstruct peri_clk_data *peri;\n\t} u;\n};\n\nstruct ccu_data {\n\tvoid *base;\n\tspinlock_t lock;\n\tbool write_enabled;\n\tstruct ccu_policy policy;\n\tstruct device_node *node;\n\tsize_t clk_num;\n\tconst char *name;\n\tu32 range;\n\tstruct kona_clk kona_clks[0];\n};\n\nstruct ccu_div_internal {\n\tu8 shift;\n\tu8 width;\n\tu32 max;\n\tu32 offset;\n\tu32 flags;\n\tstruct clk_div_table *table;\n};\n\nstruct ccu_mux_fixed_prediv;\n\nstruct ccu_mux_var_prediv;\n\nstruct ccu_mux_internal {\n\tu8 shift;\n\tu8 width;\n\tconst u8 *table;\n\tconst struct ccu_mux_fixed_prediv *fixed_predivs;\n\tu8 n_predivs;\n\tconst struct ccu_mux_var_prediv *var_predivs;\n\tu8 n_var_predivs;\n};\n\nstruct ccu_div {\n\tu32 enable;\n\tstruct ccu_div_internal div;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common common;\n\tunsigned int fixed_post_div;\n};\n\nstruct ccu_frac_internal {\n\tu32 enable;\n\tu32 select;\n\tlong unsigned int rates[2];\n};\n\nstruct ccu_gate {\n\tu32 enable;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mp {\n\tu32 enable;\n\tstruct ccu_div_internal m;\n\tstruct ccu_div_internal p;\n\tstruct ccu_mux_internal mux;\n\tunsigned int fixed_post_div;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mult_internal {\n\tu8 offset;\n\tu8 shift;\n\tu8 width;\n\tu8 min;\n\tu8 max;\n};\n\nstruct ccu_mult {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_frac_internal frac;\n\tstruct ccu_mult_internal mult;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mux {\n\tu32 enable;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mux_fixed_prediv {\n\tu8 index;\n\tu16 div;\n};\n\nstruct ccu_mux_nb {\n\tstruct notifier_block clk_nb;\n\tstruct ccu_common *common;\n\tstruct ccu_mux_internal *cm;\n\tu32 delay_us;\n\tu8 bypass_index;\n\tu8 original_index;\n};\n\nstruct ccu_mux_var_prediv {\n\tu8 index;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct ccu_nk {\n\tu16 reg;\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tunsigned int fixed_post_div;\n\tstruct ccu_common common;\n};\n\nstruct ccu_nkm {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tstruct ccu_div_internal m;\n\tstruct ccu_mux_internal mux;\n\tunsigned int fixed_post_div;\n\tlong unsigned int max_m_n_ratio;\n\tlong unsigned int min_parent_m_ratio;\n\tstruct ccu_common common;\n};\n\nstruct ccu_nkmp {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tstruct ccu_div_internal m;\n\tstruct ccu_div_internal p;\n\tunsigned int fixed_post_div;\n\tunsigned int max_rate;\n\tstruct ccu_common common;\n};\n\nstruct ccu_sdm_setting;\n\nstruct ccu_sdm_internal {\n\tstruct ccu_sdm_setting *table;\n\tu32 table_size;\n\tu32 enable;\n\tu32 tuning_enable;\n\tu16 tuning_reg;\n};\n\nstruct ccu_nm {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_div_internal m;\n\tstruct ccu_frac_internal frac;\n\tstruct ccu_sdm_internal sdm;\n\tunsigned int fixed_post_div;\n\tunsigned int min_rate;\n\tunsigned int max_rate;\n\tstruct ccu_common common;\n};\n\nstruct ccu_phase {\n\tu8 shift;\n\tu8 width;\n\tstruct ccu_common common;\n};\n\nstruct ccu_pll_nb {\n\tstruct notifier_block clk_nb;\n\tstruct ccu_common *common;\n\tu32 enable;\n\tu32 lock;\n};\n\nstruct ccu_reset_map;\n\nstruct ccu_reset {\n\tvoid *base;\n\tconst struct ccu_reset_map *reset_map;\n\tspinlock_t *lock;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct ccu_reset_map {\n\tu16 reg;\n\tu32 bit;\n};\n\nstruct ccu_sdm_setting {\n\tlong unsigned int rate;\n\tu32 pattern;\n\tu32 m;\n\tu32 n;\n};\n\nstruct usb_cdc_ncm_ntb_parameters {\n\t__le16 wLength;\n\t__le16 bmNtbFormatsSupported;\n\t__le32 dwNtbInMaxSize;\n\t__le16 wNdpInDivisor;\n\t__le16 wNdpInPayloadRemainder;\n\t__le16 wNdpInAlignment;\n\t__le16 wPadding1;\n\t__le32 dwNtbOutMaxSize;\n\t__le16 wNdpOutDivisor;\n\t__le16 wNdpOutPayloadRemainder;\n\t__le16 wNdpOutAlignment;\n\t__le16 wNtbOutMaxDatagrams;\n};\n\nstruct usb_cdc_ncm_desc;\n\nstruct usb_cdc_mbim_desc;\n\nstruct usb_cdc_mbim_extended_desc;\n\nstruct usb_cdc_ether_desc;\n\nstruct usb_interface;\n\nstruct usb_cdc_ncm_ndp16;\n\nstruct usb_cdc_ncm_ndp32;\n\nstruct cdc_ncm_ctx {\n\tstruct usb_cdc_ncm_ntb_parameters ncm_parm;\n\tlong: 32;\n\tstruct hrtimer tx_timer;\n\tstruct tasklet_struct bh;\n\tstruct usbnet *dev;\n\tconst struct usb_cdc_ncm_desc *func_desc;\n\tconst struct usb_cdc_mbim_desc *mbim_desc;\n\tconst struct usb_cdc_mbim_extended_desc *mbim_extended_desc;\n\tconst struct usb_cdc_ether_desc *ether_desc;\n\tstruct usb_interface *control;\n\tstruct usb_interface *data;\n\tstruct sk_buff *tx_curr_skb;\n\tstruct sk_buff *tx_rem_skb;\n\t__le32 tx_rem_sign;\n\tspinlock_t mtx;\n\tatomic_t stop;\n\tint drvflags;\n\tu32 timer_interval;\n\tu32 max_ndp_size;\n\tu8 is_ndp16;\n\tu8 filtering_supported;\n\tunion {\n\t\tstruct usb_cdc_ncm_ndp16 *delayed_ndp16;\n\t\tstruct usb_cdc_ncm_ndp32 *delayed_ndp32;\n\t};\n\tu32 tx_timer_pending;\n\tu32 tx_curr_frame_num;\n\tu32 rx_max;\n\tu32 tx_max;\n\tu32 tx_curr_size;\n\tu32 tx_low_mem_max_cnt;\n\tu32 tx_low_mem_val;\n\tu32 max_datagram_size;\n\tu16 tx_max_datagrams;\n\tu16 tx_remainder;\n\tu16 tx_modulus;\n\tu16 tx_ndp_modulus;\n\tu16 tx_seq;\n\tu16 rx_seq;\n\tu16 min_tx_pkt;\n\tu32 tx_curr_frame_payload;\n\tu32 tx_reason_ntb_full;\n\tu32 tx_reason_ndp_full;\n\tu32 tx_reason_timeout;\n\tu32 tx_reason_max_datagram;\n\tu64 tx_overhead;\n\tu64 tx_ntbs;\n\tu64 rx_overhead;\n\tu64 rx_ntbs;\n};\n\nstruct cdc_ncm_stats {\n\tchar stat_string[32];\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct usb_cdc_header_desc;\n\nstruct usb_cdc_union_desc;\n\nstruct cdc_state {\n\tstruct usb_cdc_header_desc *header;\n\tstruct usb_cdc_union_desc *u;\n\tstruct usb_cdc_ether_desc *ether;\n\tstruct usb_interface *control;\n\tstruct usb_interface *data;\n};\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_gpio;\n};\n\nstruct cdns_i2c {\n\tstruct device *dev;\n\tvoid *membase;\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *p_msg;\n\tint err_status;\n\tstruct completion xfer_done;\n\tunsigned char *p_send_buf;\n\tunsigned char *p_recv_buf;\n\tunsigned int send_count;\n\tunsigned int recv_count;\n\tunsigned int curr_recv_count;\n\tlong unsigned int input_clk;\n\tunsigned int i2c_clk;\n\tunsigned int bus_hold_flag;\n\tstruct clk *clk;\n\tstruct notifier_block clk_rate_change_nb;\n\tstruct reset_control *reset;\n\tu32 quirks;\n\tu32 ctrl_reg;\n\tstruct i2c_bus_recovery_info rinfo;\n\tu16 ctrl_reg_diva_divb;\n\tstruct i2c_client *slave;\n\tenum cdns_i2c_mode dev_mode;\n\tenum cdns_i2c_slave_state slave_state;\n\tu32 fifo_depth;\n\tunsigned int transfer_size;\n\tbool atomic;\n\tint err_status_atomic;\n};\n\nstruct cdns_platform_data {\n\tu32 quirks;\n};\n\nstruct cdns_spi {\n\tvoid *regs;\n\tstruct clk *ref_clk;\n\tstruct clk *pclk;\n\tunsigned int clk_rate;\n\tu32 speed_hz;\n\tconst void *txbuf;\n\tvoid *rxbuf;\n\tint tx_bytes;\n\tint rx_bytes;\n\tu8 n_bytes;\n\tu8 dev_busy;\n\tu32 is_decoded_cs;\n\tunsigned int tx_fifo_depth;\n\tstruct reset_control *rstc;\n};\n\nstruct cdns_uart {\n\tstruct uart_port *port;\n\tstruct clk *uartclk;\n\tstruct clk *pclk;\n\tunsigned int baud;\n\tstruct notifier_block clk_rate_change_nb;\n\tu32 quirks;\n\tbool cts_override;\n\tstruct gpio_desc *gpiod_rts;\n\tbool rs485_tx_started;\n\tlong: 32;\n\tstruct hrtimer tx_timer;\n\tstruct reset_control *rstc;\n\tlong: 32;\n};\n\nstruct cdrom_msf0 {\n\t__u8 minute;\n\t__u8 second;\n\t__u8 frame;\n};\n\nunion cdrom_addr {\n\tstruct cdrom_msf0 msf;\n\tint lba;\n};\n\nstruct cdrom_blk {\n\tunsigned int from;\n\tshort unsigned int len;\n};\n\nstruct cdrom_mechstat_header {\n\t__u8 curslot: 5;\n\t__u8 changer_state: 2;\n\t__u8 fault: 1;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 mech_state: 3;\n\t__u8 curlba[3];\n\t__u8 nslots;\n\t__u16 slot_tablelen;\n};\n\nstruct cdrom_slot {\n\t__u8 change: 1;\n\t__u8 reserved1: 6;\n\t__u8 disc_present: 1;\n\t__u8 reserved2[3];\n};\n\nstruct cdrom_changer_info {\n\tstruct cdrom_mechstat_header hdr;\n\tstruct cdrom_slot slots[256];\n};\n\nstruct cdrom_device_ops;\n\nstruct cdrom_device_info {\n\tconst struct cdrom_device_ops *ops;\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tvoid *handle;\n\tint mask;\n\tint speed;\n\tint capacity;\n\tunsigned int options: 30;\n\tunsigned int mc_flags: 2;\n\tunsigned int vfs_events;\n\tunsigned int ioctl_events;\n\tint use_count;\n\tchar name[20];\n\t__u8 sanyo_slot: 2;\n\t__u8 keeplocked: 1;\n\t__u8 reserved: 5;\n\tint cdda_method;\n\t__u8 last_sense;\n\t__u8 media_written;\n\tshort unsigned int mmc3_profile;\n\tint mrw_mode_page;\n\tbool opened_for_data;\n\t__s64 last_media_change_ms;\n};\n\nstruct cdrom_multisession;\n\nstruct cdrom_mcn;\n\nstruct packet_command;\n\nstruct cdrom_device_ops {\n\tint (*open)(struct cdrom_device_info *, int);\n\tvoid (*release)(struct cdrom_device_info *);\n\tint (*drive_status)(struct cdrom_device_info *, int);\n\tunsigned int (*check_events)(struct cdrom_device_info *, unsigned int, int);\n\tint (*tray_move)(struct cdrom_device_info *, int);\n\tint (*lock_door)(struct cdrom_device_info *, int);\n\tint (*select_speed)(struct cdrom_device_info *, long unsigned int);\n\tint (*get_last_session)(struct cdrom_device_info *, struct cdrom_multisession *);\n\tint (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);\n\tint (*reset)(struct cdrom_device_info *);\n\tint (*audio_ioctl)(struct cdrom_device_info *, unsigned int, void *);\n\tint (*generic_packet)(struct cdrom_device_info *, struct packet_command *);\n\tint (*read_cdda_bpc)(struct cdrom_device_info *, void *, u32, u32, u8 *);\n\tconst int capability;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct cdrom_mcn {\n\t__u8 medium_catalog_number[14];\n};\n\nstruct cdrom_msf {\n\t__u8 cdmsf_min0;\n\t__u8 cdmsf_sec0;\n\t__u8 cdmsf_frame0;\n\t__u8 cdmsf_min1;\n\t__u8 cdmsf_sec1;\n\t__u8 cdmsf_frame1;\n};\n\nstruct cdrom_multisession {\n\tunion cdrom_addr addr;\n\t__u8 xa_flag;\n\t__u8 addr_format;\n};\n\nstruct cdrom_read_audio {\n\tunion cdrom_addr addr;\n\t__u8 addr_format;\n\tint nframes;\n\t__u8 *buf;\n};\n\nstruct cdrom_subchnl {\n\t__u8 cdsc_format;\n\t__u8 cdsc_audiostatus;\n\t__u8 cdsc_adr: 4;\n\t__u8 cdsc_ctrl: 4;\n\t__u8 cdsc_trk;\n\t__u8 cdsc_ind;\n\tunion cdrom_addr cdsc_absaddr;\n\tunion cdrom_addr cdsc_reladdr;\n};\n\nstruct cdrom_sysctl_settings {\n\tchar info[1000];\n\tint autoclose;\n\tint autoeject;\n\tint debug;\n\tint lock;\n\tint check;\n};\n\nstruct cdrom_ti {\n\t__u8 cdti_trk0;\n\t__u8 cdti_ind0;\n\t__u8 cdti_trk1;\n\t__u8 cdti_ind1;\n};\n\nstruct cdrom_timed_media_change_info {\n\t__s64 last_media_change;\n\t__u64 media_flags;\n};\n\nstruct cdrom_tocentry {\n\t__u8 cdte_track;\n\t__u8 cdte_adr: 4;\n\t__u8 cdte_ctrl: 4;\n\t__u8 cdte_format;\n\tunion cdrom_addr cdte_addr;\n\t__u8 cdte_datamode;\n};\n\nstruct cdrom_tochdr {\n\t__u8 cdth_trk0;\n\t__u8 cdth_trk1;\n};\n\nstruct cdrom_volctrl {\n\t__u8 channel0;\n\t__u8 channel1;\n\t__u8 channel2;\n\t__u8 channel3;\n};\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct cea_db {\n\tu8 tag_length;\n\tu8 data[0];\n};\n\nstruct drm_edid;\n\nstruct drm_edid_iter {\n\tconst struct drm_edid *drm_edid;\n\tint index;\n};\n\nstruct displayid_iter {\n\tconst struct drm_edid *drm_edid;\n\tconst u8 *section;\n\tint length;\n\tint idx;\n\tint ext_index;\n\tu8 version;\n\tu8 primary_use;\n\tu8 quirks;\n};\n\nstruct cea_db_iter {\n\tstruct drm_edid_iter edid_iter;\n\tstruct displayid_iter displayid_iter;\n\tconst u8 *collection;\n\tint index;\n\tint end;\n};\n\nstruct cea_sad {\n\tu8 format;\n\tu8 channels;\n\tu8 freq;\n\tu8 byte2;\n};\n\nstruct cec_adapter;\n\nstruct cec_msg;\n\nstruct cec_adap_ops {\n\tint (*adap_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_all_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_pin_enable)(struct cec_adapter *, bool);\n\tint (*adap_log_addr)(struct cec_adapter *, u8);\n\tvoid (*adap_unconfigured)(struct cec_adapter *);\n\tint (*adap_transmit)(struct cec_adapter *, u8, u32, struct cec_msg *);\n\tvoid (*adap_nb_transmit_canceled)(struct cec_adapter *, const struct cec_msg *);\n\tvoid (*adap_status)(struct cec_adapter *, struct seq_file *);\n\tvoid (*adap_free)(struct cec_adapter *);\n\tint (*error_inj_show)(struct cec_adapter *, struct seq_file *);\n\tbool (*error_inj_parse_line)(struct cec_adapter *, char *);\n\tvoid (*configured)(struct cec_adapter *);\n\tint (*received)(struct cec_adapter *, struct cec_msg *);\n};\n\nstruct cec_devnode {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tint minor;\n\tstruct mutex lock;\n\tbool registered;\n\tbool unregistered;\n\tstruct mutex lock_fhs;\n\tstruct list_head fhs;\n\tlong: 32;\n};\n\nstruct cec_log_addrs {\n\t__u8 log_addr[4];\n\t__u16 log_addr_mask;\n\t__u8 cec_version;\n\t__u8 num_log_addrs;\n\t__u32 vendor_id;\n\t__u32 flags;\n\tchar osd_name[15];\n\t__u8 primary_device_type[4];\n\t__u8 log_addr_type[4];\n\t__u8 all_device_types[4];\n\t__u8 features[48];\n};\n\nstruct cec_drm_connector_info {\n\t__u32 card_no;\n\t__u32 connector_id;\n};\n\nstruct cec_connector_info {\n\t__u32 type;\n\tunion {\n\t\tstruct cec_drm_connector_info drm;\n\t\t__u32 raw[16];\n\t};\n};\n\nstruct rc_dev;\n\nstruct cec_data;\n\nstruct cec_fh;\n\nstruct cec_notifier;\n\nstruct cec_adapter {\n\tstruct module *owner;\n\tchar name[32];\n\tlong: 32;\n\tstruct cec_devnode devnode;\n\tstruct mutex lock;\n\tstruct rc_dev *rc;\n\tstruct list_head transmit_queue;\n\tunsigned int transmit_queue_sz;\n\tstruct list_head wait_queue;\n\tstruct cec_data *transmitting;\n\tbool transmit_in_progress;\n\tbool transmit_in_progress_aborted;\n\tunsigned int xfer_timeout_ms;\n\tstruct task_struct *kthread_config;\n\tstruct completion config_completion;\n\tstruct task_struct *kthread;\n\twait_queue_head_t kthread_waitq;\n\tconst struct cec_adap_ops *ops;\n\tvoid *priv;\n\tu32 capabilities;\n\tu8 available_log_addrs;\n\tu16 phys_addr;\n\tbool needs_hpd;\n\tbool is_enabled;\n\tbool is_claiming_log_addrs;\n\tbool is_configuring;\n\tbool must_reconfigure;\n\tbool is_configured;\n\tbool cec_pin_is_high;\n\tbool adap_controls_phys_addr;\n\tu8 last_initiator;\n\tu32 monitor_all_cnt;\n\tu32 monitor_pin_cnt;\n\tu32 follower_cnt;\n\tstruct cec_fh *cec_follower;\n\tstruct cec_fh *cec_initiator;\n\tbool passthrough;\n\tstruct cec_log_addrs log_addrs;\n\tstruct cec_connector_info conn_info;\n\tu32 tx_timeout_cnt;\n\tu32 tx_low_drive_cnt;\n\tu32 tx_error_cnt;\n\tu32 tx_arb_lost_cnt;\n\tu32 tx_low_drive_log_cnt;\n\tu32 tx_error_log_cnt;\n\tstruct cec_notifier *notifier;\n\tstruct dentry *cec_dir;\n\tu32 sequence;\n\tchar input_phys[40];\n\tlong: 32;\n};\n\nstruct cec_caps {\n\tchar driver[32];\n\tchar name[32];\n\t__u32 available_log_addrs;\n\t__u32 capabilities;\n\t__u32 version;\n};\n\nstruct cec_msg {\n\t__u64 tx_ts;\n\t__u64 rx_ts;\n\t__u32 len;\n\t__u32 timeout;\n\t__u32 sequence;\n\t__u32 flags;\n\t__u8 msg[16];\n\t__u8 reply;\n\t__u8 rx_status;\n\t__u8 tx_status;\n\t__u8 tx_arb_lost_cnt;\n\t__u8 tx_nack_cnt;\n\t__u8 tx_low_drive_cnt;\n\t__u8 tx_error_cnt;\n};\n\nstruct cec_data {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tlong: 32;\n\tstruct cec_msg msg;\n\tu8 match_len;\n\tu8 match_reply[5];\n\tstruct cec_fh *fh;\n\tstruct delayed_work work;\n\tstruct completion c;\n\tu8 attempts;\n\tbool blocking;\n\tbool completed;\n\tlong: 32;\n};\n\nstruct cec_event_state_change {\n\t__u16 phys_addr;\n\t__u16 log_addr_mask;\n\t__u16 have_conn_info;\n};\n\nstruct cec_event_lost_msgs {\n\t__u32 lost_msgs;\n};\n\nstruct cec_event {\n\t__u64 ts;\n\t__u32 event;\n\t__u32 flags;\n\tunion {\n\t\tstruct cec_event_state_change state_change;\n\t\tstruct cec_event_lost_msgs lost_msgs;\n\t\t__u32 raw[16];\n\t};\n};\n\nstruct cec_event_entry {\n\tstruct list_head list;\n\tstruct cec_event ev;\n};\n\nstruct cec_fh {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tu8 mode_initiator;\n\tu8 mode_follower;\n\twait_queue_head_t wait;\n\tstruct mutex lock;\n\tstruct list_head events[8];\n\tu16 queued_events[8];\n\tunsigned int total_queued_events;\n\tlong: 32;\n\tstruct cec_event_entry core_events[2];\n\tstruct list_head msgs;\n\tunsigned int queued_msgs;\n\tlong: 32;\n};\n\nstruct cec_msg_entry {\n\tstruct list_head list;\n\tstruct cec_msg msg;\n};\n\nstruct cec_notifier {\n\tstruct mutex lock;\n\tstruct list_head head;\n\tstruct kref kref;\n\tstruct device *hdmi_dev;\n\tstruct cec_connector_info conn_info;\n\tconst char *port_name;\n\tstruct cec_adapter *cec_adap;\n\tu16 phys_addr;\n};\n\nstruct cgw_csum_xor {\n\t__s8 from_idx;\n\t__s8 to_idx;\n\t__s8 result_idx;\n\t__u8 init_xor_val;\n};\n\nstruct cgw_csum_crc8 {\n\t__s8 from_idx;\n\t__s8 to_idx;\n\t__s8 result_idx;\n\t__u8 init_crc_val;\n\t__u8 final_xor_val;\n\t__u8 crctab[256];\n\t__u8 profile;\n\t__u8 profile_data[20];\n};\n\nstruct cf_mod {\n\tstruct {\n\t\tstruct canfd_frame and;\n\t\tstruct canfd_frame or;\n\t\tstruct canfd_frame xor;\n\t\tstruct canfd_frame set;\n\t} modframe;\n\tstruct {\n\t\tu8 and;\n\t\tu8 or;\n\t\tu8 xor;\n\t\tu8 set;\n\t} modtype;\n\tvoid (*modfunc[16])(struct canfd_frame *, struct cf_mod *);\n\tstruct {\n\t\tstruct cgw_csum_xor xor;\n\t\tstruct cgw_csum_crc8 crc8;\n\t} csum;\n\tstruct {\n\t\tvoid (*xor)(struct canfd_frame *, struct cgw_csum_xor *);\n\t\tvoid (*crc8)(struct canfd_frame *, struct cgw_csum_crc8 *);\n\t} csumfunc;\n\tu32 uid;\n};\n\nstruct cfg_param {\n\tconst char *property;\n\tenum tegra_pinconf_param param;\n};\n\nstruct cfi_private;\n\nstruct cfi_early_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct cfi_private *);\n};\n\nstruct cfi_extquery {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n};\n\nstruct cfi_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct mtd_info *);\n};\n\nstruct cfi_ident {\n\tuint8_t qry[3];\n\tuint16_t P_ID;\n\tuint16_t P_ADR;\n\tuint16_t A_ID;\n\tuint16_t A_ADR;\n\tuint8_t VccMin;\n\tuint8_t VccMax;\n\tuint8_t VppMin;\n\tuint8_t VppMax;\n\tuint8_t WordWriteTimeoutTyp;\n\tuint8_t BufWriteTimeoutTyp;\n\tuint8_t BlockEraseTimeoutTyp;\n\tuint8_t ChipEraseTimeoutTyp;\n\tuint8_t WordWriteTimeoutMax;\n\tuint8_t BufWriteTimeoutMax;\n\tuint8_t BlockEraseTimeoutMax;\n\tuint8_t ChipEraseTimeoutMax;\n\tuint8_t DevSize;\n\tuint16_t InterfaceDesc;\n\tuint16_t MaxBufWriteSize;\n\tuint8_t NumEraseRegions;\n\tuint32_t EraseRegionInfo[0];\n} __attribute__((packed));\n\nstruct cfi_intelext_blockinfo {\n\tuint16_t NumIdentBlocks;\n\tuint16_t BlockSize;\n\tuint16_t MinBlockEraseCycles;\n\tuint8_t BitsPerCell;\n\tuint8_t BlockCap;\n};\n\nstruct cfi_intelext_otpinfo {\n\tuint32_t ProtRegAddr;\n\tuint16_t FactGroups;\n\tuint8_t FactProtRegSize;\n\tuint16_t UserGroups;\n\tuint8_t UserProtRegSize;\n} __attribute__((packed));\n\nstruct cfi_intelext_programming_regioninfo {\n\tuint8_t ProgRegShift;\n\tuint8_t Reserved1;\n\tuint8_t ControlValid;\n\tuint8_t Reserved2;\n\tuint8_t ControlInvalid;\n\tuint8_t Reserved3;\n};\n\nstruct cfi_intelext_regioninfo {\n\tuint16_t NumIdentPartitions;\n\tuint8_t NumOpAllowed;\n\tuint8_t NumOpAllowedSimProgMode;\n\tuint8_t NumOpAllowedSimEraMode;\n\tuint8_t NumBlockTypes;\n\tstruct cfi_intelext_blockinfo BlockTypes[1];\n};\n\nstruct cfi_pri_atmel {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n\tuint8_t Features;\n\tuint8_t BottomBoot;\n\tuint8_t BurstMode;\n\tuint8_t PageMode;\n};\n\nstruct cfi_pri_intelext {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n\tuint32_t FeatureSupport;\n\tuint8_t SuspendCmdSupport;\n\tuint16_t BlkStatusRegMask;\n\tuint8_t VccOptimal;\n\tuint8_t VppOptimal;\n\tuint8_t NumProtectionFields;\n\tuint16_t ProtRegAddr;\n\tuint8_t FactProtRegSize;\n\tuint8_t UserProtRegSize;\n\tuint8_t extra[0];\n} __attribute__((packed));\n\nstruct flchip {\n\tlong unsigned int start;\n\tint ref_point_counter;\n\tflstate_t state;\n\tflstate_t oldstate;\n\tunsigned int write_suspended: 1;\n\tunsigned int erase_suspended: 1;\n\tlong unsigned int in_progress_block_addr;\n\tlong unsigned int in_progress_block_mask;\n\tstruct mutex mutex;\n\twait_queue_head_t wq;\n\tint word_write_time;\n\tint buffer_write_time;\n\tint erase_time;\n\tint word_write_time_max;\n\tint buffer_write_time_max;\n\tint erase_time_max;\n\tvoid *priv;\n};\n\nstruct map_info;\n\nstruct cfi_private {\n\tuint16_t cmdset;\n\tvoid *cmdset_priv;\n\tint interleave;\n\tint device_type;\n\tint cfi_mode;\n\tint addr_unlock1;\n\tint addr_unlock2;\n\tstruct mtd_info * (*cmdset_setup)(struct map_info *);\n\tstruct cfi_ident *cfiq;\n\tint mfr;\n\tint id;\n\tint numchips;\n\tmap_word sector_erase_cmd;\n\tlong unsigned int chipshift;\n\tconst char *im_name;\n\tlong unsigned int quirks;\n\tstruct flchip chips[0];\n};\n\nstruct cfs_bandwidth {\n\traw_spinlock_t lock;\n\tlong: 32;\n\tktime_t period;\n\tu64 quota;\n\tu64 runtime;\n\tu64 burst;\n\tu64 runtime_snap;\n\ts64 hierarchical_quota;\n\tu8 idle;\n\tu8 period_active;\n\tu8 slack_started;\n\tlong: 32;\n\tstruct hrtimer period_timer;\n\tstruct hrtimer slack_timer;\n\tstruct list_head throttled_cfs_rq;\n\tint nr_periods;\n\tint nr_throttled;\n\tint nr_burst;\n\tlong: 32;\n\tu64 throttled_time;\n\tu64 burst_time;\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sched_entity;\n\nstruct task_group;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tstruct sched_avg avg;\n\tu64 last_update_time_copy;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tint runtime_enabled;\n\ts64 runtime_remaining;\n\tu64 throttled_pelt_idle;\n\tu64 throttled_pelt_idle_copy;\n\tu64 throttled_clock;\n\tu64 throttled_clock_pelt;\n\tu64 throttled_clock_pelt_time;\n\tu64 throttled_clock_self;\n\tu64 throttled_clock_self_time;\n\tbool throttled: 1;\n\tbool pelt_clock_throttled: 1;\n\tint throttle_count;\n\tstruct list_head throttled_list;\n\tstruct list_head throttled_csd_list;\n\tstruct list_head throttled_limbo_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cfs_schedulable_data {\n\tstruct task_group *tg;\n\tlong: 32;\n\tu64 period;\n\tu64 quota;\n};\n\nstruct cgroup_subsys;\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tlong: 32;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n\tlong: 32;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 ntime;\n};\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n\tlong: 32;\n};\n\nstruct cgroup_bpf {};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[0];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[2];\n\tint nr_dying_subsys[2];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[2];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tlong: 32;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n\tlong: 32;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tlong: 32;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct cgw_fdframe_mod {\n\tstruct canfd_frame cf;\n\t__u8 modtype;\n} __attribute__((packed));\n\nstruct cgw_frame_mod {\n\tstruct can_frame cf;\n\t__u8 modtype;\n} __attribute__((packed));\n\nstruct cgw_job {\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n\tu32 handled_frames;\n\tu32 dropped_frames;\n\tu32 deleted_frames;\n\tstruct cf_mod *cf_mod;\n\tunion {\n\t\tstruct net_device *dev;\n\t} src;\n\tunion {\n\t\tstruct net_device *dev;\n\t} dst;\n\tunion {\n\t\tstruct can_can_gw ccgw;\n\t};\n\tu8 gwtype;\n\tu8 limit_hops;\n\tu16 flags;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct ubifs_ino_node;\n\nstruct check_info {\n\tlong unsigned int last_ino;\n\tlong unsigned int tot_inos;\n\tlong unsigned int missing;\n\tlong: 32;\n\tlong long unsigned int leaf_cnt;\n\tstruct ubifs_ino_node *node;\n\tstruct rb_root root;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct check_orphan {\n\tstruct rb_node rb;\n\tino_t inum;\n};\n\nstruct chip_data {\n\tenum power_supply_property psp;\n\tu8 addr;\n\tint min_value;\n\tint max_value;\n};\n\nstruct chip_data___2 {\n\tu32 cr0;\n\tu16 cr1;\n\tu16 dmacr;\n\tu16 cpsr;\n\tu8 n_bytes;\n\tbool enable_dma;\n\tenum ssp_reading read;\n\tenum ssp_writing write;\n\tint xfer_type;\n};\n\nstruct rtc_class_ops;\n\nstruct ds1307;\n\nstruct chip_desc {\n\tunsigned int alarm: 1;\n\tu16 nvram_offset;\n\tu16 nvram_size;\n\tu8 offset;\n\tu8 century_reg;\n\tu8 century_enable_bit;\n\tu8 century_bit;\n\tu8 bbsqi_bit;\n\tirq_handler_t irq_handler;\n\tconst struct rtc_class_ops *rtc_ops;\n\tu16 trickle_charger_reg;\n\tu8 (*do_trickle_setup)(struct ds1307 *, u32, bool);\n\tbool requires_trickle_resistor;\n\tbool charge_default;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct chip_desc___2 {\n\tu8 nchans;\n\tu8 enable;\n\tu8 has_irq;\n\tenum muxtype muxtype;\n\tstruct i2c_device_identity id;\n};\n\nstruct chip_probe {\n\tchar *name;\n\tint (*probe_chip)(struct map_info *, __u32, long unsigned int *, struct cfi_private *);\n};\n\nstruct tsadc_table;\n\nstruct chip_tsadc_table {\n\tconst struct tsadc_table *id;\n\tunsigned int length;\n\tu32 data_mask;\n\tenum adc_sort_mode mode;\n};\n\nstruct i2c_of_probe_cfg;\n\nstruct i2c_of_probe_simple_opts;\n\nstruct chromeos_i2c_probe_data {\n\tconst struct i2c_of_probe_cfg *cfg;\n\tconst struct i2c_of_probe_simple_opts *opts;\n};\n\nstruct hw_bank {\n\tunsigned int lpm;\n\tresource_size_t phys;\n\tvoid *abs;\n\tvoid *cap;\n\tvoid *op;\n\tsize_t size;\n\tvoid *regmap[39];\n};\n\nstruct usb_bus;\n\nstruct usb_otg {\n\tu8 default_a;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_bus *host;\n\tstruct usb_gadget *gadget;\n\tenum usb_otg_state state;\n\tint (*set_host)(struct usb_otg *, struct usb_bus *);\n\tint (*set_peripheral)(struct usb_otg *, struct usb_gadget *);\n\tint (*set_vbus)(struct usb_otg *, bool);\n\tint (*start_srp)(struct usb_otg *);\n\tint (*start_hnp)(struct usb_otg *);\n};\n\nstruct otg_fsm_ops;\n\nstruct otg_fsm {\n\tint id;\n\tint adp_change;\n\tint power_up;\n\tint a_srp_det;\n\tint a_vbus_vld;\n\tint b_conn;\n\tint a_bus_resume;\n\tint a_bus_suspend;\n\tint a_conn;\n\tint b_se0_srp;\n\tint b_ssend_srp;\n\tint b_sess_vld;\n\tint test_device;\n\tint a_bus_drop;\n\tint a_bus_req;\n\tint b_bus_req;\n\tint a_sess_vld;\n\tint b_bus_resume;\n\tint b_bus_suspend;\n\tint drv_vbus;\n\tint loc_conn;\n\tint loc_sof;\n\tint adp_prb;\n\tint adp_sns;\n\tint data_pulse;\n\tint a_set_b_hnp_en;\n\tint b_srp_done;\n\tint b_hnp_enable;\n\tint a_clr_err;\n\tint a_bus_drop_inf;\n\tint a_bus_req_inf;\n\tint a_clr_err_inf;\n\tint b_bus_req_inf;\n\tint a_suspend_req_inf;\n\tint a_wait_vrise_tmout;\n\tint a_wait_vfall_tmout;\n\tint a_wait_bcon_tmout;\n\tint a_aidl_bdis_tmout;\n\tint b_ase0_brst_tmout;\n\tint a_bidl_adis_tmout;\n\tstruct otg_fsm_ops *ops;\n\tstruct usb_otg *otg;\n\tint protocol;\n\tstruct mutex lock;\n\tu8 *host_req_flag;\n\tstruct delayed_work hnp_polling_work;\n\tbool hnp_work_inited;\n\tbool state_changed;\n};\n\nstruct ci_hw_qh;\n\nstruct ci_hdrc;\n\nstruct td_node;\n\nstruct ci_hw_ep {\n\tstruct usb_ep ep;\n\tu8 dir;\n\tu8 num;\n\tu8 type;\n\tchar name[16];\n\tstruct {\n\t\tstruct list_head queue;\n\t\tstruct ci_hw_qh *ptr;\n\t\tdma_addr_t dma;\n\t} qh;\n\tint wedge;\n\tstruct ci_hdrc *ci;\n\tspinlock_t *lock;\n\tstruct dma_pool *td_pool;\n\tstruct td_node *pending_td;\n};\n\nstruct ulpi_ops {\n\tint (*read)(struct device *, u8);\n\tint (*write)(struct device *, u8, u8);\n};\n\nstruct ci_role_driver;\n\nstruct usb_role_switch;\n\nstruct ci_hdrc_platform_data;\n\nstruct ulpi;\n\nstruct usb_hcd;\n\nstruct ci_hdrc {\n\tstruct device *dev;\n\tspinlock_t lock;\n\tstruct hw_bank hw_bank;\n\tint irq;\n\tstruct ci_role_driver *roles[2];\n\tenum ci_role role;\n\tbool is_otg;\n\tstruct usb_otg otg;\n\tstruct otg_fsm fsm;\n\tstruct hrtimer otg_fsm_hrtimer;\n\tktime_t hr_timeouts[12];\n\tunsigned int enabled_otg_timer_bits;\n\tenum otg_fsm_timer next_otg_timer;\n\tstruct usb_role_switch *role_switch;\n\tstruct work_struct work;\n\tstruct work_struct power_lost_work;\n\tstruct workqueue_struct *wq;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *td_pool;\n\tstruct usb_gadget gadget;\n\tstruct usb_gadget_driver *driver;\n\tenum usb_device_state resume_state;\n\tunsigned int hw_ep_max;\n\tstruct ci_hw_ep ci_hw_ep[32];\n\tu32 ep0_dir;\n\tstruct ci_hw_ep *ep0out;\n\tstruct ci_hw_ep *ep0in;\n\tstruct usb_request *status;\n\tbool setaddr;\n\tu8 address;\n\tu8 remote_wakeup;\n\tu8 suspended;\n\tu8 test_mode;\n\tstruct ci_hdrc_platform_data *platdata;\n\tint vbus_active;\n\tstruct ulpi *ulpi;\n\tstruct ulpi_ops ulpi_ops;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_hcd *hcd;\n\tbool id_event;\n\tbool b_sess_valid_event;\n\tbool imx28_write_fix;\n\tbool has_portsc_pec_bug;\n\tbool has_short_pkt_limit;\n\tbool supports_runtime_pm;\n\tbool in_lpm;\n\tbool wakeup_int;\n\tenum ci_revision rev;\n\tstruct mutex mutex;\n\tlong: 32;\n};\n\nstruct ci_hdrc_cable {\n\tbool connected;\n\tbool changed;\n\tbool enabled;\n\tstruct extcon_dev *edev;\n\tstruct ci_hdrc *ci;\n\tstruct notifier_block nb;\n};\n\nstruct ci_hdrc_dma_aligned_buffer {\n\tvoid *original_buffer;\n\tu8 data[0];\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints;\n\nstruct pm_qos_request {\n\tstruct plist_node node;\n\tstruct pm_qos_constraints *qos;\n};\n\nstruct imx_usbmisc_data;\n\nstruct ci_hdrc_imx_platform_flag;\n\nstruct ci_hdrc_imx_data {\n\tstruct usb_phy *phy;\n\tstruct platform_device *ci_pdev;\n\tstruct clk *clk;\n\tstruct clk *clk_wakeup;\n\tstruct imx_usbmisc_data *usbmisc_data;\n\tint wakeup_irq;\n\tbool supports_runtime_pm;\n\tbool override_phy_control;\n\tbool in_lpm;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pinctrl_hsic_active;\n\tstruct regulator *hsic_pad_regulator;\n\tbool need_three_clks;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_per;\n\tstruct pm_qos_request pm_qos_req;\n\tconst struct ci_hdrc_imx_platform_flag *plat_data;\n};\n\nstruct ci_hdrc_imx_platform_flag {\n\tunsigned int flags;\n};\n\nstruct usb_otg_caps {\n\tu16 otg_rev;\n\tbool hnp_support;\n\tbool srp_support;\n\tbool adp_support;\n};\n\nstruct ci_hdrc_platform_data {\n\tconst char *name;\n\tuintptr_t capoffset;\n\tunsigned int power_budget;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tenum usb_phy_interface phy_mode;\n\tlong unsigned int flags;\n\tenum usb_dr_mode dr_mode;\n\tint (*notify_event)(struct ci_hdrc *, unsigned int);\n\tstruct regulator *reg_vbus;\n\tstruct usb_otg_caps ci_otg_caps;\n\tbool tpl_support;\n\tu32 itc_setting;\n\tu32 ahb_burst_config;\n\tu32 tx_burst_size;\n\tu32 rx_burst_size;\n\tstruct ci_hdrc_cable vbus_extcon;\n\tstruct ci_hdrc_cable id_extcon;\n\tu32 phy_clkgate_delay_us;\n\tstruct pinctrl *pctl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_host;\n\tstruct pinctrl_state *pins_device;\n\tint (*hub_control)(struct ci_hdrc *, u16, u16, u16, char *, u16, bool *, long unsigned int *);\n\tvoid (*enter_lpm)(struct ci_hdrc *, bool);\n};\n\nstruct ci_hdrc_msm {\n\tstruct platform_device *ci;\n\tstruct clk *core_clk;\n\tstruct clk *iface_clk;\n\tstruct clk *fs_clk;\n\tstruct ci_hdrc_platform_data pdata;\n\tstruct reset_controller_dev rcdev;\n\tbool secondary_phy;\n\tbool hsic;\n\tvoid *base;\n};\n\nstruct ci_hdrc_pci {\n\tstruct platform_device *ci;\n\tstruct platform_device *phy;\n};\n\nstruct ci_hdrc_usb2_priv {\n\tstruct platform_device *ci_pdev;\n\tstruct clk *clk;\n};\n\nstruct ci_hw_td {\n\t__le32 next;\n\t__le32 token;\n\t__le32 page[5];\n};\n\nstruct ci_hw_qh {\n\t__le32 cap;\n\t__le32 curr;\n\tstruct ci_hw_td td;\n\t__le32 RESERVED;\n\tstruct usb_ctrlrequest setup;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct ci_hw_req {\n\tstruct usb_request req;\n\tstruct list_head queue;\n\tstruct list_head tds;\n\tstruct sg_table sgt;\n};\n\nstruct ci_role_driver {\n\tint (*start)(struct ci_hdrc *);\n\tvoid (*stop)(struct ci_hdrc *);\n\tvoid (*suspend)(struct ci_hdrc *);\n\tvoid (*resume)(struct ci_hdrc *, bool);\n\tirqreturn_t (*irq)(struct ci_hdrc *);\n\tconst char *name;\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct mmc_card;\n\nstruct sdio_func;\n\ntypedef int tpl_parse_t(struct mmc_card *, struct sdio_func *, const unsigned char *, unsigned int);\n\nstruct cis_tpl {\n\tunsigned char code;\n\tunsigned char min_size;\n\ttpl_parse_t *parse;\n};\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_info {\n\tint class;\n\tchar *class_name;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct clk {\n\tstruct clk_core *core;\n\tstruct device *dev;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tunsigned int exclusive_count;\n\tstruct hlist_node clks_node;\n};\n\nstruct clk_regmap {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int enable_reg;\n\tunsigned int enable_mask;\n\tbool enable_is_inverted;\n};\n\nstruct pll_vco;\n\nstruct clk_alpha_pll {\n\tu32 offset;\n\tconst u8 *regs;\n\tconst struct alpha_pll_config *config;\n\tconst struct pll_vco *vco_table;\n\tsize_t num_vco;\n\tu8 flags;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_alpha_pll_postdiv {\n\tu32 offset;\n\tu8 width;\n\tconst u8 *regs;\n\tstruct clk_regmap clkr;\n\tint post_div_shift;\n\tconst struct clk_div_table *post_div_table;\n\tsize_t num_post_div;\n};\n\nstruct clk_apbc {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tunsigned int delay;\n\tunsigned int flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_apmu {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu32 rst_mask;\n\tu32 enable_mask;\n\tspinlock_t *lock;\n};\n\nstruct clk_audio_frac {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 fracr;\n\tu8 nd;\n};\n\nstruct clk_audio_pad {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu8 qdaudio;\n\tu8 div;\n};\n\nstruct clk_audio_pmc {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu8 qdpmc;\n};\n\nstruct clk_aux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tconst struct aux_clk_masks *masks;\n\tstruct aux_rate_tbl *rtbl;\n\tu8 rtbl_cnt;\n\tspinlock_t *lock;\n};\n\nstruct clk_bcm2835_i2c {\n\tstruct clk_hw hw;\n\tstruct bcm2835_i2c_dev *i2c_dev;\n};\n\nstruct clk_branch {\n\tu32 hwcg_reg;\n\tu32 halt_reg;\n\tu8 hwcg_bit;\n\tu8 halt_bit;\n\tu8 halt_check;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_bulk_devres {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct clk_busy_divider {\n\tstruct clk_divider div;\n\tconst struct clk_ops *div_ops;\n\tvoid *reg;\n\tu8 shift;\n};\n\nstruct clk_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tconst u32 *table;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_busy_mux {\n\tstruct clk_mux mux;\n\tconst struct clk_ops *mux_ops;\n\tvoid *reg;\n\tu8 shift;\n};\n\nstruct clk_rate_request;\n\nstruct clk_duty;\n\nstruct clk_ops {\n\tint (*prepare)(struct clk_hw *);\n\tvoid (*unprepare)(struct clk_hw *);\n\tint (*is_prepared)(struct clk_hw *);\n\tvoid (*unprepare_unused)(struct clk_hw *);\n\tint (*enable)(struct clk_hw *);\n\tvoid (*disable)(struct clk_hw *);\n\tint (*is_enabled)(struct clk_hw *);\n\tvoid (*disable_unused)(struct clk_hw *);\n\tint (*save_context)(struct clk_hw *);\n\tvoid (*restore_context)(struct clk_hw *);\n\tlong unsigned int (*recalc_rate)(struct clk_hw *, long unsigned int);\n\tlong int (*round_rate)(struct clk_hw *, long unsigned int, long unsigned int *);\n\tint (*determine_rate)(struct clk_hw *, struct clk_rate_request *);\n\tint (*set_parent)(struct clk_hw *, u8);\n\tu8 (*get_parent)(struct clk_hw *);\n\tint (*set_rate)(struct clk_hw *, long unsigned int, long unsigned int);\n\tint (*set_rate_and_parent)(struct clk_hw *, long unsigned int, long unsigned int, u8);\n\tlong unsigned int (*recalc_accuracy)(struct clk_hw *, long unsigned int);\n\tint (*get_phase)(struct clk_hw *);\n\tint (*set_phase)(struct clk_hw *, int);\n\tint (*get_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*set_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*init)(struct clk_hw *);\n\tvoid (*terminate)(struct clk_hw *);\n\tvoid (*debug_init)(struct clk_hw *, struct dentry *);\n};\n\nstruct clk_composite {\n\tstruct clk_hw hw;\n\tstruct clk_ops ops;\n\tstruct clk_hw *mux_hw;\n\tstruct clk_hw *rate_hw;\n\tstruct clk_hw *gate_hw;\n\tconst struct clk_ops *mux_ops;\n\tconst struct clk_ops *rate_ops;\n\tconst struct clk_ops *gate_ops;\n};\n\nstruct clk_duty {\n\tunsigned int num;\n\tunsigned int den;\n};\n\nstruct clk_parent_map;\n\nstruct clk_core {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tstruct clk_hw *hw;\n\tstruct module *owner;\n\tstruct device *dev;\n\tstruct hlist_node rpm_node;\n\tstruct device_node *of_node;\n\tstruct clk_core *parent;\n\tstruct clk_parent_map *parents;\n\tu8 num_parents;\n\tu8 new_parent_index;\n\tlong unsigned int rate;\n\tlong unsigned int req_rate;\n\tlong unsigned int new_rate;\n\tstruct clk_core *new_parent;\n\tstruct clk_core *new_child;\n\tlong unsigned int flags;\n\tbool orphan;\n\tbool rpm_enabled;\n\tunsigned int enable_count;\n\tunsigned int prepare_count;\n\tunsigned int protect_count;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int accuracy;\n\tint phase;\n\tstruct clk_duty duty;\n\tstruct hlist_head children;\n\tstruct hlist_node child_node;\n\tstruct hlist_node hashtable_node;\n\tstruct hlist_head clks;\n\tunsigned int notifier_count;\n\tstruct dentry *dentry;\n\tstruct hlist_node debug_node;\n\tstruct kref ref;\n};\n\nstruct clk_corediv_desc;\n\nstruct clk_corediv_soc_desc;\n\nstruct clk_corediv {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tconst struct clk_corediv_desc *desc;\n\tconst struct clk_corediv_soc_desc *soc_desc;\n\tspinlock_t lock;\n};\n\nstruct clk_corediv_desc {\n\tunsigned int mask;\n\tunsigned int offset;\n\tunsigned int fieldbit;\n};\n\nstruct clk_corediv_soc_desc {\n\tconst struct clk_corediv_desc *descs;\n\tunsigned int ndescs;\n\tconst struct clk_ops ops;\n\tu32 ratio_reload;\n\tu32 enable_bit_offset;\n\tu32 ratio_offset;\n};\n\nstruct clk_cpu {\n\tstruct clk_hw hw;\n\tstruct clk *div;\n\tstruct clk *mux;\n\tstruct clk *pll;\n\tstruct clk *step;\n};\n\nstruct clk_device {\n\tstruct clk_hw hw;\n\tvoid *div_reg;\n\tunsigned int div_mask;\n\tvoid *en_reg;\n\tint en_bit;\n\tspinlock_t *lock;\n};\n\nstruct clk_div_table {\n\tunsigned int val;\n\tunsigned int div;\n};\n\nstruct clk_divider_gate {\n\tstruct clk_divider divider;\n\tu32 cached_val;\n};\n\nstruct reset_simple_data {\n\tspinlock_t lock;\n\tvoid *membase;\n\tstruct reset_controller_dev rcdev;\n\tbool active_low;\n\tbool status_active_low;\n\tunsigned int reset_us;\n};\n\nstruct clk_dvp {\n\tstruct clk_hw_onecell_data *data;\n\tstruct reset_simple_data reset;\n};\n\nstruct mn {\n\tu8 mnctr_en_bit;\n\tu8 mnctr_reset_bit;\n\tu8 mnctr_mode_shift;\n\tu8 n_val_shift;\n\tu8 m_val_shift;\n\tu8 width;\n\tbool reset_in_cc;\n};\n\nstruct pre_div {\n\tu8 pre_div_shift;\n\tu8 pre_div_width;\n};\n\nstruct parent_map;\n\nstruct src_sel {\n\tu8 src_sel_shift;\n\tconst struct parent_map *parent_map;\n};\n\nstruct freq_tbl;\n\nstruct clk_dyn_rcg {\n\tu32 ns_reg[2];\n\tu32 md_reg[2];\n\tu32 bank_reg;\n\tu8 mux_sel_bit;\n\tstruct mn mn[2];\n\tstruct pre_div p[2];\n\tstruct src_sel s[2];\n\tconst struct freq_tbl *freq_tbl;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_factor_table {\n\tunsigned int val;\n\tunsigned int mul;\n\tunsigned int div;\n};\n\nstruct clk_factors_config;\n\nstruct factors_request;\n\nstruct clk_gate;\n\nstruct clk_factors {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tconst struct clk_factors_config *config;\n\tvoid (*get_factors)(struct factors_request *);\n\tvoid (*recalc)(struct factors_request *);\n\tspinlock_t *lock;\n\tstruct clk_mux *mux;\n\tstruct clk_gate *gate;\n};\n\nstruct clk_factors_config {\n\tu8 nshift;\n\tu8 nwidth;\n\tu8 kshift;\n\tu8 kwidth;\n\tu8 mshift;\n\tu8 mwidth;\n\tu8 pshift;\n\tu8 pwidth;\n\tu8 n_start;\n};\n\nstruct clk_fixed_factor {\n\tstruct clk_hw hw;\n\tunsigned int mult;\n\tunsigned int div;\n\tlong unsigned int acc;\n\tunsigned int flags;\n};\n\nstruct clk_fixed_rate {\n\tstruct clk_hw hw;\n\tlong unsigned int fixed_rate;\n\tlong unsigned int fixed_accuracy;\n\tlong unsigned int flags;\n};\n\nstruct clk_fixup_div {\n\tstruct clk_divider divider;\n\tconst struct clk_ops *ops;\n\tvoid (*fixup)(u32 *);\n};\n\nstruct clk_fixup_mux {\n\tstruct clk_mux mux;\n\tconst struct clk_ops *ops;\n\tvoid (*fixup)(u32 *);\n};\n\nstruct frac_rate_tbl;\n\nstruct clk_frac {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tstruct frac_rate_tbl *rtbl;\n\tu8 rtbl_cnt;\n\tspinlock_t *lock;\n};\n\nstruct clk_frac_pll {\n\tstruct clk_hw hw;\n\tvoid *base;\n};\n\nstruct imx_fracn_gppll_rate_table;\n\nstruct clk_fracn_gppll {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tconst struct imx_fracn_gppll_rate_table *rate_table;\n\tint rate_count;\n\tu32 flags;\n};\n\nstruct clk_fractional_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 mshift;\n\tu8 mwidth;\n\tu8 nshift;\n\tu8 nwidth;\n\tu8 flags;\n\tvoid (*approximation)(struct clk_hw *, long unsigned int, long unsigned int *, long unsigned int *, long unsigned int *);\n\tspinlock_t *lock;\n};\n\nstruct clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_gate2 {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tu8 cgr_val;\n\tu8 cgr_mask;\n\tu8 flags;\n\tspinlock_t *lock;\n\tunsigned int *share_count;\n};\n\nstruct clk_gate_exclusive {\n\tstruct clk_gate gate;\n\tu32 exclusive_mask;\n};\n\nstruct clk_gate_soc_desc {\n\tconst char *name;\n\tint bit_idx;\n};\n\nstruct clk_gpio {\n\tstruct clk_hw hw;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct clk_gated_fixed {\n\tstruct clk_gpio clk_gpio;\n\tstruct regulator *supply;\n\tlong unsigned int rate;\n};\n\nstruct clk_gating_ctrl {\n\tspinlock_t *lock;\n\tstruct clk **gates;\n\tint num_gates;\n\tvoid *base;\n\tu32 saved_reg;\n};\n\nstruct clk_gating_soc_desc {\n\tconst char *name;\n\tconst char *parent;\n\tint bit_idx;\n\tlong unsigned int flags;\n};\n\nstruct clk_range {\n\tlong unsigned int min;\n\tlong unsigned int max;\n};\n\nstruct clk_pcr_layout;\n\nstruct clk_generated {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct clk_range range;\n\tspinlock_t *lock;\n\tu32 *mux_table;\n\tu32 id;\n\tu32 gckdiv;\n\tconst struct clk_pcr_layout *layout;\n\tstruct at91_clk_pms pms;\n\tu8 parent_id;\n\tint chg_pid;\n};\n\nstruct gpt_rate_tbl;\n\nstruct clk_gpt {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tstruct gpt_rate_tbl *rtbl;\n\tu8 rtbl_cnt;\n\tspinlock_t *lock;\n};\n\nstruct hfpll_data;\n\nstruct clk_hfpll {\n\tconst struct hfpll_data *d;\n\tint init_done;\n\tstruct clk_regmap clkr;\n\tspinlock_t lock;\n};\n\nstruct clk_hisi_phase {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu32 *phase_degrees;\n\tu32 *phase_regvals;\n\tu8 phase_num;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_omap_reg {\n\tvoid *ptr;\n\tu16 offset;\n\tu8 bit;\n\tu8 index;\n\tu8 flags;\n};\n\nstruct dpll_data;\n\nstruct clockdomain;\n\nstruct clk_hw_omap_ops;\n\nstruct clk_hw_omap {\n\tstruct clk_hw hw;\n\tstruct list_head node;\n\tlong unsigned int fixed_rate;\n\tu8 fixed_div;\n\tstruct clk_omap_reg enable_reg;\n\tu8 enable_bit;\n\tlong unsigned int flags;\n\tstruct clk_omap_reg clksel_reg;\n\tstruct dpll_data *dpll_data;\n\tconst char *clkdm_name;\n\tstruct clockdomain *clkdm;\n\tconst struct clk_hw_omap_ops *ops;\n\tu32 context;\n\tint autoidle_count;\n};\n\nstruct component_clk;\n\nstruct clk_hw_omap_comp {\n\tstruct clk_hw hw;\n\tstruct device_node *comp_nodes[3];\n\tstruct component_clk *comp_clks[3];\n};\n\nstruct clk_hw_omap_ops {\n\tvoid (*find_idlest)(struct clk_hw_omap *, struct clk_omap_reg *, u8 *, u8 *);\n\tvoid (*find_companion)(struct clk_hw_omap *, struct clk_omap_reg *, u8 *);\n\tvoid (*allow_idle)(struct clk_hw_omap *);\n\tvoid (*deny_idle)(struct clk_hw_omap *);\n};\n\nstruct clk_i2s_mux {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu8 bus_id;\n};\n\nstruct icst_params;\n\nstruct clk_icst {\n\tstruct clk_hw hw;\n\tstruct regmap *map;\n\tu32 vcoreg_off;\n\tu32 lockreg_off;\n\tstruct icst_params *params;\n\tlong unsigned int rate;\n\tenum icst_control_type ctype;\n};\n\nstruct clk_icst_desc {\n\tconst struct icst_params *params;\n\tu32 vco_offset;\n\tu32 lock_offset;\n};\n\ntypedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);\n\nstruct clk_init_item {\n\tstruct device_node *node;\n\tvoid *user;\n\tti_of_clk_init_cb_t func;\n\tstruct list_head link;\n};\n\nstruct clk_iomap {\n\tstruct regmap *regmap;\n\tvoid *mem;\n};\n\nstruct clk_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct clk *clk;\n\tstruct clk_hw *clk_hw;\n};\n\nstruct clk_lookup_alloc {\n\tstruct clk_lookup cl;\n\tchar dev_id[24];\n\tchar con_id[16];\n};\n\nstruct clk_main_osc {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct at91_clk_pms pms;\n};\n\nstruct clk_main_rc_osc {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tlong unsigned int frequency;\n\tlong unsigned int accuracy;\n\tstruct at91_clk_pms pms;\n};\n\nstruct clk_master_layout;\n\nstruct clk_master_characteristics;\n\nstruct clk_master {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tspinlock_t *lock;\n\tconst struct clk_master_layout *layout;\n\tconst struct clk_master_characteristics *characteristics;\n\tstruct at91_clk_pms pms;\n\tu32 *mux_table;\n\tu32 mckr;\n\tint chg_pid;\n\tu8 id;\n\tu8 parent;\n\tu8 div;\n\tu32 safe_div;\n};\n\nstruct clk_master_characteristics {\n\tstruct clk_range output;\n\tu32 divisors[5];\n\tu8 have_div3_pres;\n};\n\nstruct clk_master_layout {\n\tu32 offset;\n\tu32 mask;\n\tu8 pres_shift;\n};\n\nstruct clk_mem_branch {\n\tu32 mem_enable_reg;\n\tu32 mem_ack_reg;\n\tu32 mem_enable_ack_mask;\n\tu32 mem_enable_mask;\n\tbool mem_enable_invert;\n\tstruct clk_branch branch;\n};\n\nstruct clk_mgt {\n\tu32 offset;\n\tu32 pllsw;\n\tint branch;\n\tbool clk38div;\n};\n\nstruct clk_mmc {\n\tstruct clk_hw hw;\n\tu32 id;\n\tvoid *clken_reg;\n\tu32 clken_bit;\n\tvoid *div_reg;\n\tu32 div_off;\n\tu32 div_bits;\n\tvoid *drv_reg;\n\tu32 drv_off;\n\tu32 drv_bits;\n\tvoid *sam_reg;\n\tu32 sam_off;\n\tu32 sam_bits;\n};\n\nstruct clk_multiplier {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct srcu_node;\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[2];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct clk_notifier {\n\tstruct clk *clk;\n\tstruct srcu_notifier_head notifier_head;\n\tstruct list_head node;\n};\n\nstruct clk_notifier_data {\n\tstruct clk *clk;\n\tlong unsigned int old_rate;\n\tlong unsigned int new_rate;\n};\n\nstruct clk_notifier_devres {\n\tstruct clk *clk;\n\tstruct notifier_block *nb;\n};\n\nstruct clk_omap_divider {\n\tstruct clk_hw hw;\n\tstruct clk_omap_reg reg;\n\tu8 shift;\n\tu8 flags;\n\ts8 latch;\n\tu16 min;\n\tu16 max;\n\tu16 mask;\n\tconst struct clk_div_table *table;\n\tu32 context;\n};\n\nstruct clk_omap_mux {\n\tstruct clk_hw hw;\n\tstruct clk_omap_reg reg;\n\tu32 *table;\n\tu32 mask;\n\tu8 shift;\n\ts8 latch;\n\tu8 flags;\n\tu8 saved_parent;\n};\n\nstruct clk_parent_data {\n\tconst struct clk_hw *hw;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_parent_map {\n\tconst struct clk_hw *hw;\n\tstruct clk_core *core;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_pcr_layout {\n\tu32 offset;\n\tu32 cmd;\n\tu32 div_mask;\n\tu32 gckcss_mask;\n\tu32 pid_mask;\n};\n\nstruct clk_peripheral {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 id;\n};\n\nstruct clk_pfd {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 idx;\n};\n\nstruct clk_pfdv2 {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 gate_bit;\n\tu8 vld_bit;\n\tu8 frac_off;\n};\n\nstruct clk_pix_rdi {\n\tu32 s_reg;\n\tu32 s_mask;\n\tu32 s2_reg;\n\tu32 s2_mask;\n\tstruct clk_regmap clkr;\n};\n\nstruct pll_freq_tbl;\n\nstruct clk_pll {\n\tu32 l_reg;\n\tu32 m_reg;\n\tu32 n_reg;\n\tu32 config_reg;\n\tu32 mode_reg;\n\tu32 status_reg;\n\tu8 status_bit;\n\tu8 post_div_width;\n\tu8 post_div_shift;\n\tconst struct pll_freq_tbl *freq_tbl;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_pll_data;\n\nstruct clk_pll___2 {\n\tstruct clk_hw hw;\n\tstruct clk_pll_data *pll_data;\n};\n\nstruct clk_pll_layout;\n\nstruct clk_pll_characteristics;\n\nstruct clk_pll___3 {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu8 id;\n\tu8 div;\n\tu8 range;\n\tu16 mul;\n\tconst struct clk_pll_layout *layout;\n\tconst struct clk_pll_characteristics *characteristics;\n\tstruct at91_clk_pms pms;\n};\n\nstruct clk_vco;\n\nstruct clk_pll___4 {\n\tstruct clk_hw hw;\n\tstruct clk_vco *vco;\n\tconst char *parent[1];\n\tspinlock_t *lock;\n};\n\nstruct clk_pll___5 {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tspinlock_t *lock;\n\tint type;\n};\n\nstruct imx_pll14xx_rate_table;\n\nstruct clk_pll14xx {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tenum imx_pll14xx_type type;\n\tconst struct imx_pll14xx_rate_table *rate_table;\n\tint rate_count;\n};\n\nstruct clk_pll_characteristics {\n\tstruct clk_range input;\n\tint num_output;\n\tconst struct clk_range *output;\n\tconst struct clk_range *core_output;\n\tu16 *icpll;\n\tu8 *out;\n\tu8 upll: 1;\n\tu32 acr;\n};\n\nstruct clk_pll_data {\n\tbool has_pllctrl;\n\tu32 phy_pllm;\n\tu32 phy_pll_ctl0;\n\tvoid *pllm;\n\tvoid *pllod;\n\tvoid *pll_ctl0;\n\tu32 pllm_lower_mask;\n\tu32 pllm_upper_mask;\n\tu32 pllm_upper_shift;\n\tu32 plld_mask;\n\tu32 clkod_mask;\n\tu32 clkod_shift;\n\tu32 postdiv;\n};\n\nstruct clk_pll_layout {\n\tu32 pllr_mask;\n\tu32 mul_mask;\n\tu32 frac_mask;\n\tu32 div_mask;\n\tu32 endiv_mask;\n\tu8 mul_shift;\n\tu8 frac_shift;\n\tu8 div_shift;\n\tu8 endiv_shift;\n\tu8 div2;\n};\n\nstruct clk_pll_table {\n\tunsigned int val;\n\tlong unsigned int rate;\n};\n\nstruct clk_plldiv {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n};\n\nstruct clk_pllv1 {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tenum imx_pllv1_type type;\n};\n\nstruct clk_pllv2 {\n\tstruct clk_hw hw;\n\tvoid *base;\n};\n\nstruct clk_pllv3 {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu32 power_bit;\n\tbool powerup_set;\n\tu32 div_mask;\n\tu32 div_shift;\n\tlong unsigned int ref_clock;\n\tu32 num_offset;\n\tu32 denom_offset;\n};\n\nstruct clk_pllv3_vf610_mf {\n\tu32 mfi;\n\tu32 mfn;\n\tu32 mfd;\n};\n\nstruct clk_pllv4 {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu32 cfg_offset;\n\tu32 num_offset;\n\tu32 denom_offset;\n\tbool use_mult_range;\n};\n\nstruct clk_prcc {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu32 cg_sel;\n\tint is_enabled;\n};\n\nstruct clk_prcmu {\n\tstruct clk_hw hw;\n\tu8 cg_sel;\n\tint opp_requested;\n};\n\nstruct clk_prcmu_clkout {\n\tstruct clk_hw hw;\n\tu8 clkout_id;\n\tu8 source;\n\tu8 divider;\n};\n\nstruct clk_programmable_layout;\n\nstruct clk_programmable {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 *mux_table;\n\tu8 id;\n\tconst struct clk_programmable_layout *layout;\n\tstruct at91_clk_pms pms;\n};\n\nstruct clk_programmable_layout {\n\tu8 pres_mask;\n\tu8 pres_shift;\n\tu8 css_mask;\n\tu8 have_slck_mck;\n\tu8 is_pres_direct;\n};\n\nstruct clk_psc_data;\n\nstruct clk_psc {\n\tstruct clk_hw hw;\n\tstruct clk_psc_data *psc_data;\n\tspinlock_t *lock;\n};\n\nstruct clk_psc_data {\n\tvoid *control_base;\n\tvoid *domain_base;\n\tu32 domain_id;\n};\n\nstruct clk_rate_request {\n\tstruct clk_core *core;\n\tlong unsigned int rate;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int best_parent_rate;\n\tstruct clk_hw *best_parent_hw;\n};\n\nstruct clk_rcg {\n\tu32 ns_reg;\n\tu32 md_reg;\n\tstruct mn mn;\n\tstruct pre_div p;\n\tstruct src_sel s;\n\tconst struct freq_tbl *freq_tbl;\n\tstruct clk_regmap clkr;\n};\n\nstruct freq_multi_tbl;\n\nstruct clk_rcg2 {\n\tu32 cmd_rcgr;\n\tu8 mnd_width;\n\tu8 hid_width;\n\tu8 safe_src_index;\n\tconst struct parent_map *parent_map;\n\tunion {\n\t\tconst struct freq_tbl *freq_tbl;\n\t\tconst struct freq_multi_tbl *freq_multi_tbl;\n\t};\n\tstruct clk_regmap clkr;\n\tu8 cfg_off;\n\tu32 parked_cfg;\n\tbool hw_clk_ctrl;\n};\n\nstruct clk_rcg2_gfx3d {\n\tu8 div;\n\tstruct clk_rcg2 rcg;\n\tstruct clk_hw **hws;\n};\n\nstruct clk_rcg_dfs_data {\n\tstruct clk_rcg2 *rcg;\n\tstruct clk_init_data *init;\n};\n\nstruct clk_regmap___2 {\n\tstruct clk_hw hw;\n\tstruct regmap *map;\n\tvoid *data;\n};\n\nstruct clk_regmap_div {\n\tu32 reg;\n\tu32 shift;\n\tu32 width;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_regmap_div_data {\n\tunsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tconst struct clk_div_table *table;\n};\n\nstruct clk_regmap_gate_data {\n\tunsigned int offset;\n\tu8 bit_idx;\n\tu8 flags;\n};\n\nstruct clk_regmap_mux {\n\tu32 reg;\n\tu32 shift;\n\tu32 width;\n\tconst struct parent_map *parent_map;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_regmap_mux_data {\n\tunsigned int offset;\n\tu32 *table;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n};\n\nstruct clk_regmap_mux_div {\n\tu32 reg_offset;\n\tu32 hid_width;\n\tu32 hid_shift;\n\tu32 src_width;\n\tu32 src_shift;\n\tu32 div;\n\tu32 src;\n\tconst u32 *parent_map;\n\tstruct clk_regmap clkr;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_nb;\n};\n\nstruct clk_regmap_phy_mux {\n\tu32 reg;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_rk3506_inits {\n\tvoid (*inits)(struct device_node *);\n};\n\nstruct clk_rm9200_main {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n};\n\nstruct qcom_rpm;\n\nstruct rpm_cc;\n\nstruct clk_rpm {\n\tconst int rpm_clk_id;\n\tconst int xo_offset;\n\tconst bool active_only;\n\tlong unsigned int rate;\n\tbool enabled;\n\tbool branch;\n\tstruct clk_rpm *peer;\n\tstruct clk_hw hw;\n\tstruct qcom_rpm *rpm;\n\tstruct rpm_cc *rpm_cc;\n};\n\nstruct clk_rv1126_inits {\n\tvoid (*inits)(struct device_node *);\n};\n\nstruct clk_sam9260_slow {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n};\n\nstruct clk_sam9x5_main {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct at91_clk_pms pms;\n\tu8 parent;\n};\n\nstruct clk_sam9x5_peripheral {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct clk_range range;\n\tspinlock_t *lock;\n\tu32 id;\n\tu32 div;\n\tconst struct clk_pcr_layout *layout;\n\tstruct at91_clk_pms pms;\n\tbool auto_div;\n\tint chg_pid;\n};\n\nstruct clk_slow_bits;\n\nstruct clk_sam9x5_slow {\n\tstruct clk_hw hw;\n\tvoid *sckcr;\n\tconst struct clk_slow_bits *bits;\n\tu8 parent;\n};\n\nstruct clk_sama5d4_h32mx {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n};\n\nstruct clk_sama5d4_slow_osc {\n\tstruct clk_hw hw;\n\tvoid *sckcr;\n\tconst struct clk_slow_bits *bits;\n\tlong unsigned int startup_usec;\n\tbool prepared;\n};\n\nstruct clk_slow_bits {\n\tu32 cr_rcen;\n\tu32 cr_osc32en;\n\tu32 cr_osc32byp;\n\tu32 cr_oscsel;\n};\n\nstruct clk_slow_osc {\n\tstruct clk_hw hw;\n\tvoid *sckcr;\n\tconst struct clk_slow_bits *bits;\n\tlong unsigned int startup_usec;\n};\n\nstruct clk_slow_rc_osc {\n\tstruct clk_hw hw;\n\tvoid *sckcr;\n\tconst struct clk_slow_bits *bits;\n\tlong unsigned int frequency;\n\tlong unsigned int accuracy;\n\tlong unsigned int startup_usec;\n};\n\nstruct clk_smd_rpm {\n\tconst int rpm_res_type;\n\tconst int rpm_key;\n\tconst int rpm_clk_id;\n\tconst bool active_only;\n\tbool enabled;\n\tbool branch;\n\tstruct clk_smd_rpm *peer;\n\tstruct clk_hw hw;\n\tlong unsigned int rate;\n};\n\nstruct clk_smd_rpm_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct clk_sp810;\n\nstruct clk_sp810_timerclken {\n\tstruct clk_hw hw;\n\tstruct clk *clk;\n\tstruct clk_sp810 *sp810;\n\tint channel;\n};\n\nstruct clk_sp810 {\n\tstruct device_node *node;\n\tvoid *base;\n\tspinlock_t lock;\n\tstruct clk_sp810_timerclken timerclken[4];\n};\n\nstruct clk_spc {\n\tstruct clk_hw hw;\n\tint cluster;\n};\n\nstruct clk_sscg_pll_setup {\n\tint divr1;\n\tint divf1;\n\tint divr2;\n\tint divf2;\n\tint divq;\n\tint bypass;\n\tuint64_t vco1;\n\tuint64_t vco2;\n\tuint64_t fout;\n\tuint64_t ref;\n\tuint64_t ref_div1;\n\tuint64_t ref_div2;\n\tuint64_t fout_request;\n\tint fout_error;\n\tlong: 32;\n};\n\nstruct clk_sscg_pll {\n\tstruct clk_hw hw;\n\tconst struct clk_ops ops;\n\tvoid *base;\n\tlong: 32;\n\tstruct clk_sscg_pll_setup setup;\n\tu8 parent;\n\tu8 bypass1;\n\tu8 bypass2;\n\tlong: 32;\n};\n\nstruct stm32_gate_cfg;\n\nstruct stm32_mux_cfg;\n\nstruct stm32_div_cfg;\n\nstruct clk_stm32_clock_data {\n\tu16 *gate_cpt;\n\tconst struct stm32_gate_cfg *gates;\n\tconst struct stm32_mux_cfg *muxes;\n\tconst struct stm32_div_cfg *dividers;\n\tstruct clk_hw * (*is_multi_mux)(struct clk_hw *);\n};\n\nstruct clk_stm32_composite {\n\tu16 gate_id;\n\tu16 mux_id;\n\tu16 div_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct clk_stm32_div {\n\tu16 div_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct clk_stm32_gate {\n\tu16 gate_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct clk_stm32_mux {\n\tu16 mux_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct stm32_reset_cfg;\n\nstruct clk_stm32_reset_data {\n\tconst struct reset_control_ops *ops;\n\tconst struct stm32_reset_cfg **reset_lines;\n\tunsigned int nr_lines;\n\tu32 clear_offset;\n};\n\nstruct clk_stm32_securiy {\n\tu32 offset;\n\tu8 bit_idx;\n\tlong unsigned int scmi_id;\n};\n\nstruct clk_sysctrl {\n\tstruct clk_hw hw;\n\tstruct device *dev;\n\tu8 parent_index;\n\tu16 reg_sel[4];\n\tu8 reg_mask[4];\n\tu8 reg_bits[4];\n\tlong unsigned int rate;\n\tlong unsigned int enable_delay_us;\n};\n\nstruct clk_system {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct at91_clk_pms pms;\n\tu8 id;\n};\n\nstruct clk_ti_autoidle {\n\tstruct clk_omap_reg reg;\n\tu8 shift;\n\tu8 flags;\n\tconst char *name;\n\tstruct list_head node;\n};\n\nstruct clk_utmi {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap_pmc;\n\tstruct regmap *regmap_sfr;\n\tstruct at91_clk_pms pms;\n};\n\nstruct pll_rate_tbl;\n\nstruct clk_vco {\n\tstruct clk_hw hw;\n\tvoid *mode_reg;\n\tvoid *cfg_reg;\n\tstruct pll_rate_tbl *rtbl;\n\tu8 rtbl_cnt;\n\tspinlock_t *lock;\n};\n\nstruct clkctrl_provider {\n\tint num_addrs;\n\tu32 *addr;\n\tu32 *size;\n\tstruct device_node *node;\n\tstruct list_head link;\n};\n\nstruct clkdm_autodep {\n\tunion {\n\t\tconst char *name;\n\t\tstruct clockdomain *ptr;\n\t} clkdm;\n};\n\nstruct clkdm_dep {\n\tconst char *clkdm_name;\n\tstruct clockdomain *clkdm;\n\ts16 wkdep_usecount;\n\ts16 sleepdep_usecount;\n};\n\nstruct clkdm_ops {\n\tint (*clkdm_add_wkdep)(struct clockdomain *, struct clockdomain *);\n\tint (*clkdm_del_wkdep)(struct clockdomain *, struct clockdomain *);\n\tint (*clkdm_read_wkdep)(struct clockdomain *, struct clockdomain *);\n\tint (*clkdm_clear_all_wkdeps)(struct clockdomain *);\n\tint (*clkdm_add_sleepdep)(struct clockdomain *, struct clockdomain *);\n\tint (*clkdm_del_sleepdep)(struct clockdomain *, struct clockdomain *);\n\tint (*clkdm_read_sleepdep)(struct clockdomain *, struct clockdomain *);\n\tint (*clkdm_clear_all_sleepdeps)(struct clockdomain *);\n\tint (*clkdm_sleep)(struct clockdomain *);\n\tint (*clkdm_wakeup)(struct clockdomain *);\n\tvoid (*clkdm_allow_idle)(struct clockdomain *);\n\tvoid (*clkdm_deny_idle)(struct clockdomain *);\n\tint (*clkdm_clk_enable)(struct clockdomain *);\n\tint (*clkdm_clk_disable)(struct clockdomain *);\n\tint (*clkdm_save_context)(struct clockdomain *);\n\tint (*clkdm_restore_context)(struct clockdomain *);\n};\n\nstruct clkgate_separated {\n\tstruct clk_hw hw;\n\tvoid *enable;\n\tu8 bit_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clkgen_clk_out {\n\tconst char *name;\n\tlong unsigned int flags;\n};\n\nstruct clkgen_data {\n\tlong unsigned int flags;\n\tbool mode;\n\tconst struct clkgen_clk_out *outputs;\n\tconst unsigned int outputs_nb;\n};\n\nstruct clkgen_field {\n\tunsigned int offset;\n\tunsigned int mask;\n\tunsigned int shift;\n};\n\nstruct clkgen_mux_data {\n\tu32 offset;\n\tu8 shift;\n\tu8 width;\n\tspinlock_t *lock;\n\tlong unsigned int clk_flags;\n\tu8 mux_flags;\n};\n\nstruct clkgen_pll_data;\n\nstruct clkgen_pll {\n\tstruct clk_hw hw;\n\tstruct clkgen_pll_data *data;\n\tvoid *regs_base;\n\tspinlock_t *lock;\n\tu32 ndiv;\n\tu32 idf;\n\tu32 cp;\n};\n\nstruct clkgen_pll_data {\n\tstruct clkgen_field pdn_status;\n\tstruct clkgen_field pdn_ctrl;\n\tstruct clkgen_field locked_status;\n\tstruct clkgen_field mdiv;\n\tstruct clkgen_field ndiv;\n\tstruct clkgen_field pdiv;\n\tstruct clkgen_field idf;\n\tstruct clkgen_field ldf;\n\tstruct clkgen_field cp;\n\tunsigned int num_odfs;\n\tstruct clkgen_field odf[4];\n\tstruct clkgen_field odf_gate[4];\n\tbool switch2pll_en;\n\tstruct clkgen_field switch2pll;\n\tspinlock_t *lock;\n\tconst struct clk_ops *ops;\n};\n\nstruct clkgen_pll_data_clks {\n\tstruct clkgen_pll_data *data;\n\tconst struct clkgen_clk_out *outputs;\n};\n\nstruct stm_fs;\n\nstruct clkgen_quadfs_data {\n\tbool reset_present;\n\tbool bwfilter_present;\n\tbool lockstatus_present;\n\tbool powerup_polarity;\n\tbool standby_polarity;\n\tbool nsdiv_present;\n\tbool nrst_present;\n\tstruct clkgen_field ndiv;\n\tstruct clkgen_field ref_bw;\n\tstruct clkgen_field nreset;\n\tstruct clkgen_field npda;\n\tstruct clkgen_field lock_status;\n\tstruct clkgen_field nrst[4];\n\tstruct clkgen_field nsb[4];\n\tstruct clkgen_field en[4];\n\tstruct clkgen_field mdiv[4];\n\tstruct clkgen_field pe[4];\n\tstruct clkgen_field sdiv[4];\n\tstruct clkgen_field nsdiv[4];\n\tconst struct clk_ops *pll_ops;\n\tint (*get_params)(long unsigned int, long unsigned int, struct stm_fs *);\n\tint (*get_rate)(long unsigned int, const struct stm_fs *, long unsigned int *);\n};\n\nstruct clkgen_quadfs_data_clks {\n\tstruct clkgen_quadfs_data *data;\n\tconst struct clkgen_clk_out *outputs;\n};\n\nstruct stm32_rcc_match_data;\n\nstruct clock_config {\n\tlong unsigned int id;\n\tint sec_id;\n\tvoid *clock_cfg;\n\tstruct clk_hw * (*func)(struct device *, const struct stm32_rcc_match_data *, void *, spinlock_t *, const struct clock_config *);\n};\n\nstruct clock_config___2 {\n\tu32 id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst char * const *parent_names;\n\tconst struct clk_parent_data *parent_data;\n\tint num_parents;\n\tlong unsigned int flags;\n\tvoid *cfg;\n\tstruct clk_hw * (*func)(struct device *, struct clk_hw_onecell_data *, void *, spinlock_t *, const struct clock_config___2 *);\n};\n\nstruct clock_read_data {\n\tu64 epoch_ns;\n\tu64 epoch_cyc;\n\tu64 sched_clock_mask;\n\tu64 (*read_sched_clock)(void);\n\tu32 mult;\n\tu32 shift;\n\tlong: 32;\n};\n\nstruct clock_data {\n\tseqcount_latch_t seq;\n\tlong: 32;\n\tstruct clock_read_data read_data[2];\n\tktime_t wrap_kt;\n\tlong unsigned int rate;\n\tu64 (*actual_read_sched_clock)(void);\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct scmi_clock_info;\n\nstruct scmi_protocol_handle;\n\nstruct clock_info {\n\tint num_clocks;\n\tint max_async_req;\n\tbool notify_rate_changed_cmd;\n\tbool notify_rate_change_requested_cmd;\n\tatomic_t cur_async_req;\n\tstruct scmi_clock_info *clk;\n\tint (*clock_config_set)(const struct scmi_protocol_handle *, u32, enum clk_state, enum scmi_clock_oem_config, u32, bool);\n\tint (*clock_config_get)(const struct scmi_protocol_handle *, u32, enum scmi_clock_oem_config, u32 *, bool *, u32 *, bool);\n};\n\nstruct clock_provider {\n\tvoid (*clk_init_cb)(struct device_node *);\n\tstruct device_node *np;\n\tstruct list_head node;\n};\n\nstruct powerdomain;\n\nstruct clockdomain {\n\tconst char *name;\n\tunion {\n\t\tconst char *name;\n\t\tstruct powerdomain *ptr;\n\t} pwrdm;\n\tconst u16 clktrctrl_mask;\n\tconst u8 flags;\n\tu8 _flags;\n\tconst u8 dep_bit;\n\tconst u8 prcm_partition;\n\tconst u16 cm_inst;\n\tconst u16 clkdm_offs;\n\tstruct clkdm_dep *wkdep_srcs;\n\tstruct clkdm_dep *sleepdep_srcs;\n\tint usecount;\n\tint forcewake_count;\n\tstruct list_head node;\n\tu32 context;\n};\n\nstruct clockgen_muxinfo;\n\nstruct clockgen;\n\nstruct clockgen_chipinfo {\n\tconst char *compat;\n\tconst char *guts_compat;\n\tconst struct clockgen_muxinfo *cmux_groups[2];\n\tconst struct clockgen_muxinfo *hwaccel[5];\n\tvoid (*init_periph)(struct clockgen *);\n\tint cmux_to_group[9];\n\tu32 pll_mask;\n\tu32 flags;\n};\n\nstruct clockgen_pll_div {\n\tstruct clk *clk;\n\tchar name[32];\n};\n\nstruct clockgen_pll {\n\tstruct clockgen_pll_div div[32];\n};\n\nstruct clockgen {\n\tstruct device_node *node;\n\tvoid *regs;\n\tstruct clockgen_chipinfo info;\n\tstruct clk *sysclk;\n\tstruct clk *coreclk;\n\tstruct clockgen_pll pll[6];\n\tstruct clk *cmux[8];\n\tstruct clk *hwaccel[5];\n\tstruct clk *fman[2];\n\tstruct ccsr_guts *guts;\n};\n\nstruct clockgen_sourceinfo {\n\tu32 flags;\n\tint pll;\n\tint div;\n};\n\nstruct clockgen_muxinfo {\n\tstruct clockgen_sourceinfo clksel[16];\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clocksource_mmio {\n\tvoid *reg;\n\tlong: 32;\n\tstruct clocksource clksrc;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct cm_ll_data {\n\tint (*split_idlest_reg)(struct clk_omap_reg *, s16 *, u8 *);\n\tint (*wait_module_ready)(u8, s16, u16, u8);\n\tint (*wait_module_idle)(u8, s16, u16, u8);\n\tvoid (*module_enable)(u8, u8, u16, u16);\n\tvoid (*module_disable)(u8, u16, u16);\n\tu32 (*xlate_clkctrl)(u8, u16, u16);\n};\n\nstruct cma_memrange {\n\tlong unsigned int base_pfn;\n\tlong unsigned int count;\n\tunion {\n\t\tlong unsigned int early_pfn;\n\t\tlong unsigned int *bitmap;\n\t};\n};\n\nstruct cma {\n\tlong unsigned int count;\n\tlong unsigned int available_count;\n\tunsigned int order_per_bit;\n\tspinlock_t lock;\n\tstruct mutex alloc_mutex;\n\tchar name[64];\n\tint nranges;\n\tstruct cma_memrange ranges[8];\n\tlong unsigned int flags;\n\tint nid;\n};\n\nstruct cma_init_memrange {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tstruct list_head list;\n};\n\nstruct mtd_partition;\n\nstruct cmdline_mtd_partition {\n\tstruct cmdline_mtd_partition *next;\n\tchar *mtd_id;\n\tint num_parts;\n\tstruct mtd_partition *parts;\n};\n\nstruct cmdline_subpart;\n\nstruct cmdline_parts {\n\tchar name[32];\n\tunsigned int nr_subparts;\n\tstruct cmdline_subpart *subpart;\n\tstruct cmdline_parts *next_parts;\n};\n\nstruct cmdline_subpart {\n\tchar name[32];\n\tsector_t from;\n\tsector_t size;\n\tint flags;\n\tstruct cmdline_subpart *next_subpart;\n};\n\nstruct cmdq_pkt;\n\nstruct cmdq_client_reg {\n\tu8 subsys;\n\tphys_addr_t pa_base;\n\tu16 offset;\n\tu16 size;\n\tint (*pkt_write)(struct cmdq_pkt *, u8, u32, u16, u32);\n\tint (*pkt_write_mask)(struct cmdq_pkt *, u8, u32, u16, u32, u32);\n};\n\nstruct cmdq_mbox_priv {\n\tu8 shift_pa;\n\tdma_addr_t mminfra_offset;\n};\n\nstruct cmdq_pkt {\n\tvoid *va_base;\n\tdma_addr_t pa_base;\n\tsize_t cmd_buf_size;\n\tsize_t buf_size;\n\tstruct cmdq_mbox_priv priv;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct combiner_chip_data {\n\tunsigned int hwirq_offset;\n\tunsigned int irq_mask;\n\tvoid *base;\n\tunsigned int parent_irq;\n\tu32 pm_save;\n};\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n\tlong: 32;\n};\n\nstruct comp_opts {\n\tint dict_size;\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[12];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_nfs_string {\n\tcompat_uint_t len;\n\tcompat_uptr_t data;\n};\n\nstruct compat_nfs4_mount_data_v1 {\n\tcompat_int_t version;\n\tcompat_int_t flags;\n\tcompat_int_t rsize;\n\tcompat_int_t wsize;\n\tcompat_int_t timeo;\n\tcompat_int_t retrans;\n\tcompat_int_t acregmin;\n\tcompat_int_t acregmax;\n\tcompat_int_t acdirmin;\n\tcompat_int_t acdirmax;\n\tstruct compat_nfs_string client_addr;\n\tstruct compat_nfs_string mnt_path;\n\tstruct compat_nfs_string hostname;\n\tcompat_uint_t host_addrlen;\n\tcompat_uptr_t host_addr;\n\tcompat_int_t proto;\n\tcompat_int_t auth_flavourlen;\n\tcompat_uptr_t auth_flavours;\n};\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_clk {\n\tint num_parents;\n\tconst char **parent_names;\n\tstruct device_node *node;\n\tint type;\n\tstruct clk_hw *hw;\n\tstruct list_head link;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\nstruct compound_hdr {\n\tint32_t status;\n\tuint32_t nops;\n\t__be32 *nops_p;\n\tuint32_t taglen;\n\tchar *tag;\n\tuint32_t replen;\n\tu32 minorversion;\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct config_group;\n\nstruct config_item_type;\n\nstruct config_item {\n\tchar *ci_name;\n\tchar ci_namebuf[20];\n\tstruct kref ci_kref;\n\tstruct list_head ci_entry;\n\tstruct config_item *ci_parent;\n\tstruct config_group *ci_group;\n\tconst struct config_item_type *ci_type;\n\tstruct dentry *ci_dentry;\n};\n\nstruct configfs_subsystem;\n\nstruct config_group {\n\tstruct config_item cg_item;\n\tstruct list_head cg_children;\n\tstruct configfs_subsystem *cg_subsys;\n\tstruct list_head default_groups;\n\tstruct list_head group_entry;\n};\n\nstruct configfs_item_operations;\n\nstruct configfs_group_operations;\n\nstruct configfs_attribute;\n\nstruct configfs_bin_attribute;\n\nstruct config_item_type {\n\tstruct module *ct_owner;\n\tconst struct configfs_item_operations *ct_item_ops;\n\tconst struct configfs_group_operations *ct_group_ops;\n\tstruct configfs_attribute **ct_attrs;\n\tstruct configfs_bin_attribute **ct_bin_attrs;\n};\n\nstruct deflate_state;\n\ntypedef struct deflate_state deflate_state;\n\ntypedef block_state (*compress_func)(deflate_state *, int);\n\nstruct config_s {\n\tush good_length;\n\tush max_lazy;\n\tush nice_length;\n\tush max_chain;\n\tcompress_func func;\n};\n\ntypedef struct config_s config;\n\nstruct configfs_attribute {\n\tconst char *ca_name;\n\tstruct module *ca_owner;\n\tumode_t ca_mode;\n\tssize_t (*show)(struct config_item *, char *);\n\tssize_t (*store)(struct config_item *, const char *, size_t);\n};\n\nstruct configfs_bin_attribute {\n\tstruct configfs_attribute cb_attr;\n\tvoid *cb_private;\n\tsize_t cb_max_size;\n\tssize_t (*read)(struct config_item *, void *, size_t);\n\tssize_t (*write)(struct config_item *, const void *, size_t);\n};\n\nstruct configfs_buffer {\n\tsize_t count;\n\tlong: 32;\n\tloff_t pos;\n\tchar *page;\n\tconst struct configfs_item_operations *ops;\n\tstruct mutex mutex;\n\tint needs_read_fill;\n\tbool read_in_progress;\n\tbool write_in_progress;\n\tchar *bin_buffer;\n\tint bin_buffer_size;\n\tint cb_max_size;\n\tstruct config_item *item;\n\tstruct module *owner;\n\tunion {\n\t\tstruct configfs_attribute *attr;\n\t\tstruct configfs_bin_attribute *bin_attr;\n\t};\n\tlong: 32;\n};\n\nstruct iattr;\n\nstruct configfs_fragment;\n\nstruct configfs_dirent {\n\tatomic_t s_count;\n\tint s_dependent_count;\n\tstruct list_head s_sibling;\n\tstruct list_head s_children;\n\tint s_links;\n\tvoid *s_element;\n\tint s_type;\n\tumode_t s_mode;\n\tstruct dentry *s_dentry;\n\tstruct iattr *s_iattr;\n\tstruct configfs_fragment *s_frag;\n};\n\nstruct configfs_fragment {\n\tatomic_t frag_count;\n\tstruct rw_semaphore frag_sem;\n\tbool frag_dead;\n};\n\nstruct configfs_group_operations {\n\tstruct config_item * (*make_item)(struct config_group *, const char *);\n\tstruct config_group * (*make_group)(struct config_group *, const char *);\n\tvoid (*disconnect_notify)(struct config_group *, struct config_item *);\n\tvoid (*drop_item)(struct config_group *, struct config_item *);\n\tbool (*is_visible)(struct config_item *, struct configfs_attribute *, int);\n\tbool (*is_bin_visible)(struct config_item *, struct configfs_bin_attribute *, int);\n};\n\nstruct configfs_item_operations {\n\tvoid (*release)(struct config_item *);\n\tint (*allow_link)(struct config_item *, struct config_item *);\n\tvoid (*drop_link)(struct config_item *, struct config_item *);\n};\n\nstruct configfs_subsystem {\n\tstruct config_group su_group;\n\tstruct mutex su_mutex;\n};\n\nstruct connect_timeout_data {\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tlong: 32;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tlong: 32;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct;\n\nstruct console___2 {\n\tstruct list_head list;\n\tstruct hvc_struct *hvc;\n\tstruct winsize ws;\n\tu32 vtermno;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n\tlong: 32;\n};\n\nstruct context_tracking {\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct virtio_net_ctrl_hdr {\n\t__u8 class;\n\t__u8 cmd;\n};\n\nstruct control_buf {\n\tstruct virtio_net_ctrl_hdr hdr;\n\tvirtio_net_ctrl_ack status;\n};\n\nstruct control_init_data {\n\tint index;\n\tvoid *mem;\n\ts16 offset;\n};\n\nstruct cooling_spec {\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tunsigned int weight;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coreclk_ratio {\n\tint id;\n\tconst char *name;\n};\n\nstruct coreclk_soc_desc {\n\tu32 (*get_tclk_freq)(void *);\n\tu32 (*get_cpu_freq)(void *);\n\tvoid (*get_clk_ratio)(void *, int, int *, int *);\n\tu32 (*get_refclk_freq)(void *);\n\tbool (*is_sscg_enabled)(void *);\n\tu32 (*fix_sscg_deviation)(u32);\n\tconst struct coreclk_ratio *ratios;\n\tint num_ratios;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tlong: 32;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct fuse_corner;\n\nstruct corner {\n\tint min_uV;\n\tint max_uV;\n\tint uV;\n\tint last_uV;\n\tint quot_adjust;\n\tu32 save_ctl;\n\tu32 save_irq;\n\tlong unsigned int freq;\n\tstruct fuse_corner *fuse_corner;\n};\n\nstruct corner_data {\n\tunsigned int fuse_corner;\n\tlong unsigned int freq;\n};\n\nstruct regulator_coupler;\n\nstruct coupling_desc {\n\tstruct regulator_dev **coupled_rdevs;\n\tstruct regulator_coupler *coupler;\n\tint n_resolved;\n\tint n_coupled;\n};\n\nstruct spi_device;\n\nstruct regmap_irq;\n\nstruct cpcap_ddata {\n\tstruct spi_device *spi;\n\tstruct regmap_irq *irqs;\n\tstruct regmap_irq_chip_data *irqdata[3];\n\tconst struct regmap_config *regmap_conf;\n\tstruct regmap *regmap;\n};\n\nstruct cpcap_regulator;\n\nstruct cpcap_ddata___2 {\n\tstruct regmap *reg;\n\tstruct device *dev;\n\tconst struct cpcap_regulator *soc;\n};\n\nstruct cpcap_regulator {\n\tstruct regulator_desc rdesc;\n\tconst u16 assign_reg;\n\tconst u16 assign_mask;\n};\n\ntypedef void (*cpdma_handler_fn)(void *, int, int);\n\nstruct cpdma_chan_stats {\n\tu32 head_enqueue;\n\tu32 tail_enqueue;\n\tu32 pad_enqueue;\n\tu32 misqueued;\n\tu32 desc_alloc_fail;\n\tu32 pad_alloc_fail;\n\tu32 runt_receive_buff;\n\tu32 runt_transmit_buff;\n\tu32 empty_dequeue;\n\tu32 busy_dequeue;\n\tu32 good_dequeue;\n\tu32 requeue;\n\tu32 teardown_dequeue;\n};\n\nstruct cpdma_desc;\n\nstruct cpdma_ctlr;\n\nstruct cpdma_chan {\n\tstruct cpdma_desc *head;\n\tstruct cpdma_desc *tail;\n\tvoid *hdp;\n\tvoid *cp;\n\tvoid *rxfree;\n\tenum cpdma_state state;\n\tstruct cpdma_ctlr *ctlr;\n\tint chan_num;\n\tspinlock_t lock;\n\tint count;\n\tu32 desc_num;\n\tu32 mask;\n\tcpdma_handler_fn handler;\n\tenum dma_data_direction dir;\n\tstruct cpdma_chan_stats stats;\n\tint int_set;\n\tint int_clear;\n\tint td;\n\tint weight;\n\tu32 rate_factor;\n\tu32 rate;\n};\n\nstruct cpdma_control_info {\n\tu32 reg;\n\tu32 shift;\n\tu32 mask;\n\tint access;\n};\n\nstruct cpdma_params {\n\tstruct device *dev;\n\tvoid *dmaregs;\n\tvoid *txhdp;\n\tvoid *rxhdp;\n\tvoid *txcp;\n\tvoid *rxcp;\n\tvoid *rxthresh;\n\tvoid *rxfree;\n\tint num_chan;\n\tbool has_soft_reset;\n\tint min_packet_size;\n\tdma_addr_t desc_mem_phys;\n\tdma_addr_t desc_hw_addr;\n\tint desc_mem_size;\n\tint desc_align;\n\tu32 bus_freq_mhz;\n\tu32 descs_pool_size;\n\tbool has_ext_regs;\n};\n\nstruct cpdma_desc_pool;\n\nstruct cpdma_ctlr {\n\tenum cpdma_state state;\n\tstruct cpdma_params params;\n\tstruct device *dev;\n\tstruct cpdma_desc_pool *pool;\n\tspinlock_t lock;\n\tstruct cpdma_chan *channels[64];\n\tint chan_num;\n\tint num_rx_desc;\n\tint num_tx_desc;\n};\n\nstruct cpdma_desc {\n\tu32 hw_next;\n\tu32 hw_buffer;\n\tu32 hw_len;\n\tu32 hw_mode;\n\tvoid *sw_token;\n\tu32 sw_buffer;\n\tu32 sw_len;\n};\n\nstruct cpdma_desc_pool {\n\tphys_addr_t phys;\n\tdma_addr_t hw_addr;\n\tvoid *iomap;\n\tvoid *cpumap;\n\tint desc_size;\n\tint mem_size;\n\tint num_desc;\n\tstruct device *dev;\n\tstruct gen_pool *gen_pool;\n};\n\nstruct cper_arm_ctx_info {\n\tu16 version;\n\tu16 type;\n\tu32 size;\n};\n\nstruct cper_arm_err_info {\n\tu8 version;\n\tu8 length;\n\tu16 validation_bits;\n\tu8 type;\n\tu16 multiple_error;\n\tu8 flags;\n\tu64 error_info;\n\tu64 virt_fault_addr;\n\tu64 physical_fault_addr;\n} __attribute__((packed));\n\nstruct cper_sec_proc_arm {\n\tu32 validation_bits;\n\tu16 err_info_num;\n\tu16 context_info_num;\n\tu32 section_length;\n\tu8 affinity_level;\n\tu8 reserved[3];\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n};\n\nstruct cpg_clk_config {\n\tunsigned int z_mult;\n\tunsigned int z_div;\n\tunsigned int zs_and_s_div;\n\tunsigned int s1_div;\n\tunsigned int p_div;\n\tunsigned int b_and_out_div;\n};\n\nstruct cpg_core_clk {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int type;\n\tunsigned int parent;\n\tunsigned int div;\n\tunsigned int mult;\n\tunsigned int offset;\n\tunion {\n\t\tconst char * const *parent_names;\n\t\tconst struct clk_div_table *dtable;\n\t};\n\tu32 conf;\n\tu16 flag;\n\tu8 mux_flags;\n\tu8 num_parents;\n};\n\nstruct cpg_mssr_clk_domain {\n\tstruct generic_pm_domain genpd;\n\tunsigned int num_core_pm_clks;\n\tunsigned int core_pm_clks[0];\n\tlong: 32;\n};\n\nstruct mssr_mod_clk;\n\nstruct cpg_mssr_pub;\n\nstruct cpg_mssr_info {\n\tconst struct cpg_core_clk *early_core_clks;\n\tunsigned int num_early_core_clks;\n\tconst struct mssr_mod_clk *early_mod_clks;\n\tunsigned int num_early_mod_clks;\n\tconst struct cpg_core_clk *core_clks;\n\tunsigned int num_core_clks;\n\tunsigned int last_dt_core_clk;\n\tunsigned int num_total_core_clks;\n\tenum clk_reg_layout reg_layout;\n\tconst struct mssr_mod_clk *mod_clks;\n\tunsigned int num_mod_clks;\n\tunsigned int num_hw_mod_clks;\n\tconst unsigned int *crit_mod_clks;\n\tunsigned int num_crit_mod_clks;\n\tconst unsigned int *core_pm_clks;\n\tunsigned int num_core_pm_clks;\n\tint (*init)(struct device *);\n\tstruct clk * (*cpg_clk_register)(struct device *, const struct cpg_core_clk *, const struct cpg_mssr_info *, struct cpg_mssr_pub *);\n};\n\nstruct cpg_mssr_pub {\n\tvoid *base0;\n\tvoid *base1;\n\tstruct raw_notifier_head notifiers;\n\tspinlock_t rmw_lock;\n\tstruct clk **clks;\n};\n\nstruct cpg_mssr_priv {\n\tstruct cpg_mssr_pub pub;\n\tstruct reset_controller_dev rcdev;\n\tstruct device *dev;\n\tenum clk_reg_layout reg_layout;\n\tstruct device_node *np;\n\tunsigned int num_core_clks;\n\tunsigned int num_mod_clks;\n\tunsigned int last_dt_core_clk;\n\tconst u16 *status_regs;\n\tconst u16 *control_regs;\n\tconst u16 *reset_regs;\n\tconst u16 *reset_clear_regs;\n\tstruct {\n\t\tu32 mask;\n\t\tu32 val;\n\t} smstpcr_saved[30];\n\tunsigned int *reserved_ids;\n\tunsigned int num_reserved_ids;\n\tstruct clk *clks[0];\n};\n\nstruct cpg_z_clk {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tvoid *kick_reg;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cpr_desc;\n\nstruct cpr_acc_desc {\n\tconst struct cpr_desc *cpr_desc;\n\tconst struct acc_desc *acc_desc;\n};\n\nstruct fuse_corner_data;\n\nstruct cpr_fuses {\n\tint init_voltage_step;\n\tint init_voltage_width;\n\tstruct fuse_corner_data *fuse_corner_data;\n};\n\nstruct cpr_desc {\n\tunsigned int num_fuse_corners;\n\tint min_diff_quot;\n\tint *step_quot;\n\tunsigned int timer_delay_us;\n\tunsigned int timer_cons_up;\n\tunsigned int timer_cons_down;\n\tunsigned int up_threshold;\n\tunsigned int down_threshold;\n\tunsigned int idle_clocks;\n\tunsigned int gcnt_us;\n\tunsigned int vdd_apc_step_up_limit;\n\tunsigned int vdd_apc_step_down_limit;\n\tunsigned int clamp_timer_interval;\n\tstruct cpr_fuses cpr_fuses;\n\tbool reduce_to_fuse_uV;\n\tbool reduce_to_corner_uV;\n};\n\nstruct cpr_fuse;\n\nstruct cpr_drv {\n\tunsigned int num_corners;\n\tunsigned int ref_clk_khz;\n\tstruct generic_pm_domain pd;\n\tstruct device *dev;\n\tstruct device *attached_cpu_dev;\n\tstruct mutex lock;\n\tvoid *base;\n\tstruct corner *corner;\n\tstruct regulator *vdd_apc;\n\tstruct clk *cpu_clk;\n\tstruct regmap *tcsr;\n\tbool loop_disabled;\n\tu32 gcnt;\n\tlong unsigned int flags;\n\tstruct fuse_corner *fuse_corners;\n\tstruct corner *corners;\n\tconst struct cpr_desc *desc;\n\tconst struct acc_desc *acc_desc;\n\tconst struct cpr_fuse *cpr_fuses;\n\tstruct dentry *debugfs;\n\tlong: 32;\n};\n\nstruct cpr_fuse {\n\tchar *ring_osc;\n\tchar *init_voltage;\n\tchar *quotient;\n\tchar *quotient_offset;\n};\n\nstruct cprman_plat_data {\n\tunsigned int soc;\n};\n\nstruct reg_field;\n\nstruct cpsw_ale_params {\n\tstruct device *dev;\n\tvoid *ale_regs;\n\tlong unsigned int ale_ageout;\n\tlong unsigned int ale_entries;\n\tlong unsigned int num_policers;\n\tlong unsigned int ale_ports;\n\tbool nu_switch_ale;\n\tconst struct reg_field *reg_fields;\n\tint num_fields;\n\tconst char *dev_id;\n\tlong unsigned int bus_freq;\n};\n\nstruct regmap_field;\n\nstruct cpsw_ale {\n\tstruct cpsw_ale_params params;\n\tstruct timer_list timer;\n\tstruct regmap *regmap;\n\tstruct regmap_field *fields[45];\n\tlong unsigned int ageout;\n\tu32 version;\n\tu32 features;\n\tu32 port_mask_bits;\n\tu32 port_num_bits;\n\tu32 vlan_field_bits;\n\tlong unsigned int *p0_untag_vid_mask;\n\tconst struct ale_entry_fld *vlan_entry_tbl;\n};\n\nstruct cpsw_ale_dev_id {\n\tconst char *dev_id;\n\tu32 features;\n\tu32 tbl_entries;\n\tconst struct reg_field *reg_fields;\n\tint num_fields;\n\tbool nu_switch_ale;\n\tconst struct ale_entry_fld *vlan_entry_tbl;\n};\n\nstruct cpsw_ale_ratelimit {\n\tlong unsigned int cookie;\n\tlong: 32;\n\tu64 rate_packet_ps;\n};\n\nstruct cpsw_slave_data;\n\nstruct cpsw_platform_data {\n\tstruct cpsw_slave_data *slave_data;\n\tu32 ss_reg_ofs;\n\tu32 channels;\n\tu32 slaves;\n\tu32 active_slave;\n\tu32 bd_ram_size;\n\tu32 mac_control;\n\tu16 default_vlan;\n\tbool dual_emac;\n};\n\nstruct cpsw_vector {\n\tstruct cpdma_chan *ch;\n\tint budget;\n};\n\nstruct cpsw_ss_regs;\n\nstruct cpsw_wr_regs;\n\nstruct cpsw_host_regs;\n\nstruct cpsw_slave;\n\nstruct cpts;\n\nstruct devlink;\n\nstruct page_pool;\n\nstruct cpsw_common {\n\tstruct device *dev;\n\tstruct cpsw_platform_data data;\n\tlong: 32;\n\tstruct napi_struct napi_rx;\n\tstruct napi_struct napi_tx;\n\tstruct cpsw_ss_regs *regs;\n\tstruct cpsw_wr_regs *wr_regs;\n\tu8 *hw_stats;\n\tstruct cpsw_host_regs *host_port_regs;\n\tu32 version;\n\tu32 coal_intvl;\n\tu32 bus_freq_mhz;\n\tint rx_packet_max;\n\tint descs_pool_size;\n\tstruct cpsw_slave *slaves;\n\tstruct cpdma_ctlr *dma;\n\tstruct cpsw_vector txv[8];\n\tstruct cpsw_vector rxv[8];\n\tstruct cpsw_ale *ale;\n\tbool quirk_irq;\n\tbool rx_irq_disabled;\n\tbool tx_irq_disabled;\n\tu32 irqs_table[2];\n\tint misc_irq;\n\tstruct cpts *cpts;\n\tstruct devlink *devlink;\n\tint rx_ch_num;\n\tint tx_ch_num;\n\tint speed;\n\tint usage_count;\n\tstruct page_pool *page_pool[8];\n\tu8 br_members;\n\tstruct net_device *hw_bridge_dev;\n\tbool ale_bypass;\n\tu8 base_mac[6];\n};\n\nstruct cpsw_cpts {\n\tu32 idver;\n\tu32 control;\n\tu32 rftclk_sel;\n\tu32 ts_push;\n\tu32 ts_load_val;\n\tu32 ts_load_en;\n\tu32 res2[2];\n\tu32 intstat_raw;\n\tu32 intstat_masked;\n\tu32 int_enable;\n\tu32 res3;\n\tu32 event_pop;\n\tu32 event_low;\n\tu32 event_high;\n};\n\nstruct cpsw_devlink {\n\tstruct cpsw_common *cpsw;\n};\n\nstruct cpsw_host_regs {\n\tu32 max_blks;\n\tu32 blk_cnt;\n\tu32 tx_in_ctl;\n\tu32 port_vlan;\n\tu32 tx_pri_map;\n\tu32 cpdma_tx_pri_map;\n\tu32 cpdma_rx_chan_map;\n};\n\nstruct cpsw_hw_stats {\n\tu32 rxgoodframes;\n\tu32 rxbroadcastframes;\n\tu32 rxmulticastframes;\n\tu32 rxpauseframes;\n\tu32 rxcrcerrors;\n\tu32 rxaligncodeerrors;\n\tu32 rxoversizedframes;\n\tu32 rxjabberframes;\n\tu32 rxundersizedframes;\n\tu32 rxfragments;\n\tu32 __pad_0[2];\n\tu32 rxoctets;\n\tu32 txgoodframes;\n\tu32 txbroadcastframes;\n\tu32 txmulticastframes;\n\tu32 txpauseframes;\n\tu32 txdeferredframes;\n\tu32 txcollisionframes;\n\tu32 txsinglecollframes;\n\tu32 txmultcollframes;\n\tu32 txexcessivecollisions;\n\tu32 txlatecollisions;\n\tu32 txunderrun;\n\tu32 txcarriersenseerrors;\n\tu32 txoctets;\n\tu32 octetframes64;\n\tu32 octetframes65t127;\n\tu32 octetframes128t255;\n\tu32 octetframes256t511;\n\tu32 octetframes512t1023;\n\tu32 octetframes1024tup;\n\tu32 netoctets;\n\tu32 rxsofoverruns;\n\tu32 rxmofoverruns;\n\tu32 rxdmaoverruns;\n};\n\nstruct cpsw_meta_xdp {\n\tstruct net_device *ndev;\n\tint ch;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct cpsw_priv {\n\tstruct net_device *ndev;\n\tstruct device *dev;\n\tu32 msg_enable;\n\tu8 mac_addr[6];\n\tbool rx_pause;\n\tbool tx_pause;\n\tbool mqprio_hw;\n\tint fifo_bw[4];\n\tint shp_cfg_speed;\n\tint tx_ts_enabled;\n\tint rx_ts_enabled;\n\tstruct bpf_prog *xdp_prog;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xdp_rxq[8];\n\tstruct xdp_attachment_info xdpi;\n\tu32 emac_port;\n\tstruct cpsw_common *cpsw;\n\tint offload_fwd_mark;\n\tu32 tx_packet_min;\n\tstruct cpsw_ale_ratelimit ale_bc_ratelimit;\n\tstruct cpsw_ale_ratelimit ale_mc_ratelimit;\n\tstruct work_struct rx_mode_work;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct cpsw_sl {\n\tstruct device *dev;\n\tvoid *sl_base;\n\tconst u16 *regs;\n\tu32 control_features;\n\tu32 idle_mask;\n};\n\nstruct cpsw_sl_dev_id {\n\tconst char *device_id;\n\tconst u16 *regs;\n\tconst u32 control_features;\n\tconst u32 regs_offset;\n\tconst u32 idle_mask;\n};\n\nstruct cpsw_slave {\n\tvoid *regs;\n\tint slave_num;\n\tu32 mac_control;\n\tstruct cpsw_slave_data *data;\n\tstruct phy_device *phy;\n\tstruct net_device *ndev;\n\tu32 port_vlan;\n\tstruct cpsw_sl *mac_sl;\n};\n\nstruct cpsw_slave_data {\n\tstruct device_node *slave_node;\n\tstruct device_node *phy_node;\n\tchar phy_id[61];\n\tphy_interface_t phy_if;\n\tu8 mac_addr[6];\n\tu16 dual_emac_res_vlan;\n\tstruct phy *ifphy;\n\tbool disabled;\n};\n\nstruct cpsw_ss_regs {\n\tu32 id_ver;\n\tu32 control;\n\tu32 soft_reset;\n\tu32 stat_port_en;\n\tu32 ptype;\n\tu32 soft_idle;\n\tu32 thru_rate;\n\tu32 gap_thresh;\n\tu32 tx_start_wds;\n\tu32 flow_control;\n\tu32 vlan_ltype;\n\tu32 ts_ltype;\n\tu32 dlr_ltype;\n};\n\nstruct cpsw_stats {\n\tchar stat_string[32];\n\tint type;\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct switchdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n\tconst void *ctx;\n};\n\nstruct switchdev_notifier_fdb_info {\n\tstruct switchdev_notifier_info info;\n\tconst unsigned char *addr;\n\tu16 vid;\n\tu8 added_by_user: 1;\n\tu8 is_local: 1;\n\tu8 locked: 1;\n\tu8 offloaded: 1;\n};\n\nstruct cpsw_switchdev_event_work {\n\tstruct work_struct work;\n\tstruct switchdev_notifier_fdb_info fdb_info;\n\tstruct cpsw_priv *priv;\n\tlong unsigned int event;\n};\n\nstruct cpsw_wr_regs {\n\tu32 id_ver;\n\tu32 soft_reset;\n\tu32 control;\n\tu32 int_control;\n\tu32 rx_thresh_en;\n\tu32 rx_en;\n\tu32 tx_en;\n\tu32 misc_en;\n\tu32 mem_allign1[8];\n\tu32 rx_thresh_stat;\n\tu32 rx_stat;\n\tu32 tx_stat;\n\tu32 misc_stat;\n\tu32 mem_allign2[8];\n\tu32 rx_imax;\n\tu32 tx_imax;\n};\n\nstruct ptp_pin_desc;\n\nstruct ptp_system_timestamp;\n\nstruct system_device_crosststamp;\n\nstruct ptp_clock_request;\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[32];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint n_per_lp;\n\tint pps;\n\tunsigned int supported_perout_flags;\n\tunsigned int supported_extts_flags;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\ts32 (*getmaxphase)(struct ptp_clock_info *);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*getcycles64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n\tint (*perout_loopback)(struct ptp_clock_info *, unsigned int, int);\n};\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tlong: 32;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct cpts_event {\n\tstruct list_head list;\n\tlong unsigned int tmo;\n\tu32 high;\n\tu32 low;\n\tlong: 32;\n\tu64 timestamp;\n};\n\nstruct ptp_clock;\n\nstruct cpts {\n\tstruct device *dev;\n\tstruct cpsw_cpts *reg;\n\tint tx_enable;\n\tint rx_enable;\n\tstruct ptp_clock_info info;\n\tstruct ptp_clock *clock;\n\tspinlock_t lock;\n\tu32 cc_mult;\n\tlong: 32;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tint phc_index;\n\tstruct clk *refclk;\n\tstruct list_head events;\n\tstruct list_head pool;\n\tstruct cpts_event pool_data[32];\n\tlong unsigned int ov_check_period;\n\tstruct sk_buff_head txq;\n\tlong: 32;\n\tu64 cur_timestamp;\n\tu32 mult_new;\n\tstruct mutex ptp_clk_mutex;\n\tbool irq_poll;\n\tstruct completion ts_push_complete;\n\tu32 hw_ts_enable;\n};\n\nstruct cpts_skb_cb_data {\n\tu32 skb_mtype_seqid;\n\tlong unsigned int tmo;\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cache_fns {\n\tvoid (*flush_icache_all)(void);\n\tvoid (*flush_kern_all)(void);\n\tvoid (*flush_kern_louis)(void);\n\tvoid (*flush_user_all)(void);\n\tvoid (*flush_user_range)(long unsigned int, long unsigned int, unsigned int);\n\tvoid (*coherent_kern_range)(long unsigned int, long unsigned int);\n\tint (*coherent_user_range)(long unsigned int, long unsigned int);\n\tvoid (*flush_kern_dcache_area)(void *, size_t);\n\tvoid (*dma_map_area)(const void *, size_t, int);\n\tvoid (*dma_unmap_area)(const void *, size_t, int);\n\tvoid (*dma_flush_range)(const void *, const void *);\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct cpu_clk {\n\tstruct clk_hw hw;\n\tint cpu;\n\tconst char *clk_name;\n\tconst char *parent_name;\n\tvoid *reg_base;\n\tvoid *pmu_dfs;\n};\n\nstruct cpu_clk_suspend_context {\n\tu32 pllx_misc;\n\tu32 pllx_base;\n\tu32 cpu_burst;\n\tu32 clk_csite_src;\n\tu32 cclk_divider;\n};\n\nstruct cpu_clk_suspend_context___2 {\n\tu32 clk_csite_src;\n\tu32 cclkg_burst;\n\tu32 cclkg_divider;\n};\n\nstruct cpu_context_save {\n\t__u32 r4;\n\t__u32 r5;\n\t__u32 r6;\n\t__u32 r7;\n\t__u32 r8;\n\t__u32 r9;\n\t__u32 sl;\n\t__u32 fp;\n\t__u32 sp;\n\t__u32 pc;\n\t__u32 extra[2];\n};\n\nstruct cpufreq_frequency_table;\n\nstruct cpu_data {\n\tstruct clk **pclk;\n\tstruct cpufreq_frequency_table *table;\n};\n\nstruct update_util_data {\n\tvoid (*func)(struct update_util_data *, u64, unsigned int);\n};\n\nstruct policy_dbs_info;\n\nstruct cpu_dbs_info {\n\tu64 prev_cpu_idle;\n\tu64 prev_update_time;\n\tu64 prev_cpu_nice;\n\tunsigned int prev_load;\n\tstruct update_util_data update_util;\n\tstruct policy_dbs_info *policy_dbs;\n\tlong: 32;\n};\n\nstruct cpu_efficiency {\n\tconst char *compatible;\n\tlong unsigned int efficiency;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_lpi_count {\n\tatomic_t managed;\n\tatomic_t unmanaged;\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_pm_ops {\n\tint (*finish_suspend)(long unsigned int);\n\tvoid (*resume)(void);\n\tvoid (*scu_prepare)(unsigned int, unsigned int);\n\tvoid (*hotplug_restart)(void);\n};\n\nstruct cpu_port {\n\tu64 mpidr;\n\tu32 port;\n\tlong: 32;\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_str {\n\tu8 len;\n\tu8 unused;\n\tu16 name[0];\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_tlb_fns {\n\tvoid (*flush_user_range)(long unsigned int, long unsigned int, struct vm_area_struct *);\n\tvoid (*flush_kern_range)(long unsigned int, long unsigned int);\n\tlong unsigned int tlb_flags;\n};\n\nstruct cpu_topology {\n\tint thread_id;\n\tint core_id;\n\tint cluster_id;\n\tint package_id;\n\tcpumask_t thread_sibling;\n\tcpumask_t core_sibling;\n\tcpumask_t cluster_sibling;\n\tcpumask_t llc_sibling;\n};\n\nstruct cpu_user_fns {\n\tvoid (*cpu_clear_user_highpage)(struct page *, long unsigned int);\n\tvoid (*cpu_copy_user_highpage)(struct page *, struct page *, long unsigned int, struct vm_area_struct *);\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct thermal_cooling_device;\n\nstruct thermal_cooling_device_ops {\n\tint (*get_max_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*get_cur_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*set_cur_state)(struct thermal_cooling_device *, long unsigned int);\n\tint (*get_requested_power)(struct thermal_cooling_device *, u32 *);\n\tint (*state2power)(struct thermal_cooling_device *, long unsigned int, u32 *);\n\tint (*power2state)(struct thermal_cooling_device *, u32, long unsigned int *);\n};\n\nstruct freq_constraints;\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct em_perf_domain;\n\nstruct cpufreq_policy;\n\nstruct cpufreq_cooling_device {\n\tu32 last_load;\n\tunsigned int cpufreq_state;\n\tunsigned int max_level;\n\tstruct em_perf_domain *em;\n\tstruct cpufreq_policy *policy;\n\tstruct thermal_cooling_device_ops cooling_ops;\n\tstruct freq_qos_request qos_req;\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_policy_data;\n\nstruct freq_attr;\n\nstruct cpufreq_driver {\n\tchar name[16];\n\tu16 flags;\n\tvoid *driver_data;\n\tint (*init)(struct cpufreq_policy *);\n\tint (*verify)(struct cpufreq_policy_data *);\n\tint (*setpolicy)(struct cpufreq_policy *);\n\tint (*target)(struct cpufreq_policy *, unsigned int, unsigned int);\n\tint (*target_index)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*fast_switch)(struct cpufreq_policy *, unsigned int);\n\tvoid (*adjust_perf)(unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get)(unsigned int);\n\tvoid (*update_limits)(struct cpufreq_policy *);\n\tint (*bios_limit)(int, unsigned int *);\n\tint (*online)(struct cpufreq_policy *);\n\tint (*offline)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n\tvoid (*ready)(struct cpufreq_policy *);\n\tstruct freq_attr **attr;\n\tbool boost_enabled;\n\tint (*set_boost)(struct cpufreq_policy *, int);\n\tvoid (*register_em)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_dt_platform_data {\n\tbool have_governor_per_policy;\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_freqs {\n\tstruct cpufreq_policy *policy;\n\tunsigned int old;\n\tunsigned int new;\n\tu8 flags;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tstruct list_head governor_list;\n\tstruct module *owner;\n\tu8 flags;\n};\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_read_t;\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_write_t;\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct cpufreq_stats;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tbool strict_target;\n\tbool efficiencies_available;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tbool boost_enabled;\n\tbool boost_supported;\n\tunsigned int cached_target_freq;\n\tunsigned int cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpufreq_policy_data {\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tstruct cpufreq_frequency_table *freq_table;\n\tunsigned int cpu;\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct cpufreq_stats {\n\tunsigned int total_trans;\n\tlong: 32;\n\tlong long unsigned int last_time;\n\tunsigned int max_state;\n\tunsigned int state_num;\n\tunsigned int last_index;\n\tu64 *time_in_state;\n\tunsigned int *freq_table;\n\tunsigned int *trans_table;\n\tunsigned int reset_pending;\n\tlong: 32;\n\tlong long unsigned int reset_time;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nstruct cpuidle_device;\n\nstruct cpuidle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_device *, char *);\n\tssize_t (*store)(struct cpuidle_device *, const char *, size_t);\n};\n\nstruct cpuidle_coupled {\n\tcpumask_t coupled_cpus;\n\tint requested_state[16];\n\tatomic_t ready_waiting_counts;\n\tatomic_t abort_barrier;\n\tint online_count;\n\tint refcnt;\n\tint prevent;\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tlong: 32;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n\tcpumask_t coupled_cpus;\n\tstruct cpuidle_coupled *coupled;\n};\n\nstruct cpuidle_device_kobj {\n\tstruct cpuidle_device *dev;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tlong: 32;\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tlong: 32;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct cpuidle_driver_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_driver *, char *);\n\tssize_t (*store)(struct cpuidle_driver *, const char *, size_t);\n};\n\nstruct cpuidle_driver_kobj {\n\tstruct cpuidle_driver *drv;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_exynos_data {\n\tint (*cpu0_enter_aftr)(void);\n\tint (*cpu1_powerdown)(void);\n\tvoid (*pre_enter_aftr)(void);\n\tvoid (*post_enter_aftr)(void);\n};\n\nstruct cpuidle_governor {\n\tchar name[16];\n\tstruct list_head governor_list;\n\tunsigned int rating;\n\tint (*enable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tvoid (*disable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tint (*select)(struct cpuidle_driver *, struct cpuidle_device *, bool *);\n\tvoid (*reflect)(struct cpuidle_device *, int);\n};\n\nstruct cpuidle_ops {\n\tint (*suspend)(long unsigned int);\n\tint (*init)(struct device_node *, int);\n};\n\nstruct spm_driver_data;\n\nstruct cpuidle_qcom_spm_data {\n\tstruct cpuidle_driver cpuidle_driver;\n\tstruct spm_driver_data *spm;\n\tlong: 32;\n};\n\nstruct cpuidle_state_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_state *, struct cpuidle_state_usage *, char *);\n\tssize_t (*store)(struct cpuidle_state *, struct cpuidle_state_usage *, const char *, size_t);\n};\n\nstruct cpuidle_state_kobj {\n\tstruct cpuidle_state *state;\n\tstruct cpuidle_state_usage *state_usage;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n\tstruct cpuidle_device *device;\n};\n\nstruct cpuinfo_arm {\n\tu32 cpuid;\n\tunsigned int loops_per_jiffy;\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tlong: 32;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct cqhci_host_ops;\n\nstruct cqhci_slot;\n\nstruct cqhci_host {\n\tconst struct cqhci_host_ops *ops;\n\tvoid *mmio;\n\tstruct mmc_host *mmc;\n\tspinlock_t lock;\n\tunsigned int rca;\n\tbool dma64;\n\tint num_slots;\n\tint qcnt;\n\tu32 dcmd_slot;\n\tu32 caps;\n\tu32 quirks;\n\tbool enabled;\n\tbool halted;\n\tbool init_done;\n\tbool activated;\n\tbool waiting_for_idle;\n\tbool recovery_halt;\n\tsize_t desc_size;\n\tsize_t data_size;\n\tu8 *desc_base;\n\tu8 slot_sz;\n\tu8 task_desc_len;\n\tu8 link_desc_len;\n\tu8 *trans_desc_base;\n\tu8 trans_desc_len;\n\tdma_addr_t desc_dma_base;\n\tdma_addr_t trans_desc_dma_base;\n\tstruct completion halt_comp;\n\twait_queue_head_t wait_queue;\n\tstruct cqhci_slot *slot;\n};\n\nstruct cqhci_host_ops {\n\tvoid (*dumpregs)(struct mmc_host *);\n\tvoid (*write_l)(struct cqhci_host *, u32, int);\n\tu32 (*read_l)(struct cqhci_host *, int);\n\tvoid (*enable)(struct mmc_host *);\n\tvoid (*disable)(struct mmc_host *, bool);\n\tvoid (*update_dcmd_desc)(struct mmc_host *, struct mmc_request *, u64 *);\n\tvoid (*pre_enable)(struct mmc_host *);\n\tvoid (*post_disable)(struct mmc_host *);\n\tvoid (*set_tran_desc)(struct cqhci_host *, u8 **, dma_addr_t, int, bool, bool);\n};\n\nstruct cqhci_slot {\n\tstruct mmc_request *mrq;\n\tunsigned int flags;\n};\n\nstruct cqspi_flash_pdata;\n\nstruct cqspi_st;\n\nstruct cqspi_driver_platdata {\n\tu32 hwcaps_mask;\n\tu16 quirks;\n\tint (*indirect_read_dma)(struct cqspi_flash_pdata *, u_char *, loff_t, size_t);\n\tu32 (*get_dma_status)(struct cqspi_st *);\n};\n\nstruct cqspi_flash_pdata {\n\tstruct cqspi_st *cqspi;\n\tu32 clk_rate;\n\tu32 read_delay;\n\tu32 tshsl_ns;\n\tu32 tsd2d_ns;\n\tu32 tchsh_ns;\n\tu32 tslch_ns;\n\tu8 cs;\n};\n\nstruct cqspi_st {\n\tstruct platform_device *pdev;\n\tstruct spi_controller *host;\n\tstruct clk_bulk_data clks[3];\n\tunsigned int sclk;\n\tvoid *iobase;\n\tvoid *ahb_base;\n\tresource_size_t ahb_size;\n\tstruct completion transfer_complete;\n\tstruct dma_chan *rx_chan;\n\tstruct completion rx_dma_complete;\n\tdma_addr_t mmap_phys_base;\n\tint current_cs;\n\tlong unsigned int master_ref_clk_hz;\n\tbool is_decoded_cs;\n\tu32 fifo_depth;\n\tu32 fifo_width;\n\tu32 num_chipselect;\n\tbool rclk_en;\n\tu32 trigger_address;\n\tu32 wr_delay;\n\tbool use_direct_mode;\n\tbool use_direct_mode_wr;\n\tstruct cqspi_flash_pdata f_pdata[4];\n\tbool use_dma_read;\n\tu32 pd_dev_id;\n\tbool wr_completion;\n\tbool slow_sram;\n\tbool apb_ahb_hazard;\n\tbool is_jh7110;\n\tbool is_rzn1;\n\tbool disable_stig_mode;\n\trefcount_t refcount;\n\trefcount_t inflight_ops;\n\tconst struct cqspi_driver_platdata *ddata;\n};\n\nstruct cr_regs {\n\tu32 cam;\n\tu32 ram;\n};\n\nstruct cramfs_info {\n\t__u32 crc;\n\t__u32 edition;\n\t__u32 blocks;\n\t__u32 files;\n};\n\nstruct cramfs_inode {\n\t__u32 mode: 16;\n\t__u32 uid: 16;\n\t__u32 size: 24;\n\t__u32 gid: 8;\n\t__u32 namelen: 6;\n\t__u32 offset: 26;\n};\n\nstruct cramfs_super {\n\t__u32 magic;\n\t__u32 size;\n\t__u32 flags;\n\t__u32 future;\n\t__u8 signature[16];\n\tstruct cramfs_info fsid;\n\t__u8 name[16];\n\tstruct cramfs_inode root;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct crash_mem {\n\tunsigned int max_nr_ranges;\n\tunsigned int nr_ranges;\n\tstruct range ranges[0];\n};\n\nstruct crci_config {\n\tu32 num_rows;\n\tconst u32 (*array)[12];\n};\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n\tlong: 32;\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct crossbar_device {\n\traw_spinlock_t lock;\n\tuint int_max;\n\tuint safe_map;\n\tuint max_crossbar_sources;\n\tuint *irq_map;\n\tvoid *crossbar_base;\n\tint *register_offsets;\n\tvoid (*write)(int, int);\n};\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_acomp_stream {\n\tspinlock_t lock;\n\tvoid *ctx;\n};\n\nstruct crypto_acomp_streams {\n\tvoid * (*alloc_ctx)(void);\n\tvoid (*free_ctx)(void *);\n\tstruct crypto_acomp_stream *streams;\n\tstruct work_struct stream_work;\n\tcpumask_t stream_want;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_ahash {\n\tbool using_shash;\n\tunsigned int statesize;\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_akcipher {\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_akcipher_sync_data {\n\tstruct crypto_akcipher *tfm;\n\tconst void *src;\n\tvoid *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct akcipher_request *req;\n\tstruct crypto_wait cwait;\n\tstruct scatterlist sg;\n\tu8 *buf;\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_hash_walk {\n\tconst char *data;\n\tunsigned int offset;\n\tunsigned int flags;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n};\n\nstruct crypto_kpp {\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_kpp_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n\tbool test_started;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct crypto_lskcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_lskcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct crypto_report_acomp {\n\tchar type[64];\n};\n\nstruct crypto_report_aead {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int maxauthsize;\n\tunsigned int ivsize;\n};\n\nstruct crypto_report_akcipher {\n\tchar type[64];\n};\n\nstruct crypto_report_blkcipher {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n};\n\nstruct crypto_report_comp {\n\tchar type[64];\n};\n\nstruct crypto_report_hash {\n\tchar type[64];\n\tunsigned int blocksize;\n\tunsigned int digestsize;\n};\n\nstruct crypto_report_kpp {\n\tchar type[64];\n};\n\nstruct crypto_report_rng {\n\tchar type[64];\n\tunsigned int seedsize;\n};\n\nstruct crypto_report_sig {\n\tchar type[64];\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sig {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sig_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sync_aead {\n\tstruct crypto_aead base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct hlist_head dead;\n\tstruct module *module;\n\tstruct work_struct free_work;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tvoid (*destroy)(struct crypto_alg *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n\tunsigned int algsize;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_alg data;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct cs_data {\n\tu32 enable_mask;\n\tu16 slow_cfg;\n\tu16 fast_cfg;\n};\n\nstruct mem_ctl_info;\n\nstruct rank_info;\n\nstruct csrow_info {\n\tstruct device dev;\n\tlong unsigned int first_page;\n\tlong unsigned int last_page;\n\tlong unsigned int page_mask;\n\tint csrow_idx;\n\tu32 ue_count;\n\tu32 ce_count;\n\tstruct mem_ctl_info *mci;\n\tu32 nr_channels;\n\tstruct rank_info **channels;\n\tlong: 32;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[2];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[2];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ct_data_s {\n\tunion {\n\t\tush freq;\n\t\tush code;\n\t} fc;\n\tunion {\n\t\tush dad;\n\t\tush len;\n\t} dl;\n};\n\ntypedef struct ct_data_s ct_data;\n\nstruct ctl_table;\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct edac_device_ctl_info;\n\nstruct ctl_info_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctrl_regs {\n\tu32 tmr_ctrl;\n\tu32 tmr_tevent;\n\tu32 tmr_temask;\n\tu32 tmr_pevent;\n\tu32 tmr_pemask;\n\tu32 tmr_stat;\n\tu32 tmr_cnt_h;\n\tu32 tmr_cnt_l;\n\tu32 tmr_add;\n\tu32 tmr_acc;\n\tu32 tmr_prsc;\n\tu8 res1[4];\n\tu32 tmroff_h;\n\tu32 tmroff_l;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct cvb_coefficients {\n\tint c0;\n\tint c1;\n\tint c2;\n};\n\nstruct cvb_cpu_dfll_data {\n\tu32 tune0_low;\n\tu32 tune0_high;\n\tu32 tune1;\n\tunsigned int tune_high_min_millivolts;\n};\n\nstruct cvb_table_freq_entry {\n\tlong unsigned int freq;\n\tstruct cvb_coefficients coefficients;\n};\n\nstruct cvb_table {\n\tint speedo_id;\n\tint process_id;\n\tint min_millivolts;\n\tint max_millivolts;\n\tint speedo_scale;\n\tint voltage_scale;\n\tstruct cvb_table_freq_entry entries[40];\n\tstruct cvb_cpu_dfll_data cpu_dfll_data;\n};\n\nstruct cvt_timing {\n\tu8 code[3];\n};\n\nstruct cygnus_gpio_mux {\n\tint is_supported;\n\tunsigned int offset;\n\tunsigned int shift;\n};\n\nstruct cygnus_mux {\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int alt;\n};\n\nstruct cygnus_mux_log {\n\tstruct cygnus_mux mux;\n\tbool is_configured;\n};\n\nstruct cygnus_pcie_phy_core;\n\nstruct cygnus_pcie_phy {\n\tstruct cygnus_pcie_phy_core *core;\n\tenum cygnus_pcie_phy_id id;\n\tstruct phy *phy;\n};\n\nstruct cygnus_pcie_phy_core {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct mutex lock;\n\tstruct cygnus_pcie_phy phys[2];\n};\n\nstruct cygnus_pin {\n\tunsigned int pin;\n\tchar *name;\n\tstruct cygnus_gpio_mux gpio_mux;\n};\n\nstruct cygnus_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct cygnus_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int num_pins;\n\tstruct cygnus_mux mux;\n};\n\nstruct cygnus_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct device *dev;\n\tvoid *base0;\n\tvoid *base1;\n\tconst struct cygnus_pin_group *groups;\n\tunsigned int num_groups;\n\tconst struct cygnus_pin_function *functions;\n\tunsigned int num_functions;\n\tstruct cygnus_mux_log *mux_log;\n\tspinlock_t lock;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct d40_desc;\n\nstruct d40_lcla_pool {\n\tvoid *base;\n\tdma_addr_t dma_addr;\n\tvoid *base_unaligned;\n\tint pages;\n\tspinlock_t lock;\n\tstruct d40_desc **alloc_map;\n};\n\nstruct d40_interrupt_lookup;\n\nstruct d40_reg_val;\n\nstruct d40_gen_dmac {\n\tu32 *backup;\n\tu32 backup_size;\n\tu32 realtime_en;\n\tu32 realtime_clear;\n\tu32 high_prio_en;\n\tu32 high_prio_clear;\n\tu32 interrupt_en;\n\tu32 interrupt_clear;\n\tstruct d40_interrupt_lookup *il;\n\tu32 il_size;\n\tstruct d40_reg_val *init_reg;\n\tu32 init_reg_size;\n};\n\nstruct d40_chan;\n\nstruct stedma40_platform_data;\n\nstruct d40_phy_res;\n\nstruct d40_base {\n\tspinlock_t interrupt_lock;\n\tspinlock_t execmd_lock;\n\tstruct device *dev;\n\tvoid *virtbase;\n\tu8 rev: 4;\n\tstruct clk *clk;\n\tint irq;\n\tint num_memcpy_chans;\n\tint num_phy_chans;\n\tint num_log_chans;\n\tstruct dma_device dma_both;\n\tstruct dma_device dma_slave;\n\tstruct dma_device dma_memcpy;\n\tstruct d40_chan *phy_chans;\n\tstruct d40_chan *log_chans;\n\tstruct d40_chan **lookup_log_chans;\n\tstruct d40_chan **lookup_phy_chans;\n\tstruct stedma40_platform_data *plat_data;\n\tstruct regulator *lcpa_regulator;\n\tstruct d40_phy_res *phy_res;\n\tstruct d40_lcla_pool lcla_pool;\n\tvoid *lcpa_base;\n\tdma_addr_t phy_lcpa;\n\tresource_size_t lcpa_size;\n\tstruct kmem_cache *desc_slab;\n\tu32 reg_val_backup[6];\n\tu32 reg_val_backup_v4[20];\n\tu32 *reg_val_backup_chan;\n\tu32 *regs_interrupt;\n\tu16 gcc_pwr_off_mask;\n\tstruct d40_gen_dmac gen_dmac;\n};\n\nstruct stedma40_half_channel_info {\n\tbool big_endian;\n\tenum dma_slave_buswidth data_width;\n\tint psize;\n\tenum stedma40_flow_ctrl flow_ctrl;\n};\n\nstruct stedma40_chan_cfg {\n\tenum dma_transfer_direction dir;\n\tbool high_priority;\n\tbool realtime;\n\tenum stedma40_mode mode;\n\tenum stedma40_mode_opt mode_opt;\n\tint dev_type;\n\tstruct stedma40_half_channel_info src_info;\n\tstruct stedma40_half_channel_info dst_info;\n\tbool use_fixed_channel;\n\tint phy_channel;\n};\n\nstruct d40_def_lcsp {\n\tu32 lcsp3;\n\tu32 lcsp1;\n};\n\nstruct d40_log_lli_full;\n\nstruct d40_chan {\n\tspinlock_t lock;\n\tint log_num;\n\tint pending_tx;\n\tbool busy;\n\tstruct d40_phy_res *phy_chan;\n\tstruct dma_chan chan;\n\tstruct tasklet_struct tasklet;\n\tstruct list_head client;\n\tstruct list_head pending_queue;\n\tstruct list_head active;\n\tstruct list_head done;\n\tstruct list_head queue;\n\tstruct list_head prepare_queue;\n\tstruct stedma40_chan_cfg dma_cfg;\n\tstruct dma_slave_config slave_config;\n\tbool configured;\n\tstruct d40_base *base;\n\tu32 src_def_cfg;\n\tu32 dst_def_cfg;\n\tstruct d40_def_lcsp log_def;\n\tstruct d40_log_lli_full *lcpa;\n\tdma_addr_t runtime_addr;\n\tenum dma_transfer_direction runtime_direction;\n};\n\nstruct d40_phy_lli;\n\nstruct d40_phy_lli_bidir {\n\tstruct d40_phy_lli *src;\n\tstruct d40_phy_lli *dst;\n};\n\nstruct d40_log_lli;\n\nstruct d40_log_lli_bidir {\n\tstruct d40_log_lli *src;\n\tstruct d40_log_lli *dst;\n};\n\nstruct d40_lli_pool {\n\tvoid *base;\n\tint size;\n\tdma_addr_t dma_addr;\n\tu8 pre_alloc_lli[48];\n};\n\nstruct d40_desc {\n\tstruct d40_phy_lli_bidir lli_phy;\n\tstruct d40_log_lli_bidir lli_log;\n\tstruct d40_lli_pool lli_pool;\n\tint lli_len;\n\tint lli_current;\n\tint lcla_alloc;\n\tstruct dma_async_tx_descriptor txd;\n\tstruct list_head node;\n\tbool is_in_client_list;\n\tbool cyclic;\n};\n\nstruct d40_interrupt_lookup {\n\tu32 src;\n\tu32 clr;\n\tbool is_error;\n\tint offset;\n};\n\nstruct d40_log_lli {\n\tu32 lcsp02;\n\tu32 lcsp13;\n};\n\nstruct d40_log_lli_full {\n\tu32 lcsp0;\n\tu32 lcsp1;\n\tu32 lcsp2;\n\tu32 lcsp3;\n};\n\nstruct d40_phy_lli {\n\tu32 reg_cfg;\n\tu32 reg_elt;\n\tu32 reg_ptr;\n\tu32 reg_lnk;\n};\n\nstruct d40_phy_res {\n\tspinlock_t lock;\n\tbool reserved;\n\tint num;\n\tu32 allocated_src;\n\tu32 allocated_dst;\n\tbool use_soft_lli;\n};\n\nstruct d40_reg_val {\n\tunsigned int reg;\n\tunsigned int val;\n};\n\nstruct da9052 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct mutex auxadc_lock;\n\tstruct completion done;\n\tint irq_base;\n\tstruct regmap_irq_chip_data *irq_data;\n\tu8 chip_id;\n\tint chip_irq;\n\tint fault_log;\n\tint (*fix_io)(struct da9052 *, unsigned char);\n};\n\nstruct led_platform_data;\n\nstruct da9052_pdata {\n\tstruct led_platform_data *pled;\n\tint (*init)(struct da9052 *);\n\tint irq_base;\n\tint gpio_base;\n\tint use_for_apm;\n\tstruct regulator_init_data *regulators[14];\n};\n\nstruct da9210 {\n\tstruct regulator_dev *rdev;\n\tstruct regmap *regmap;\n};\n\nstruct regulator_state {\n\tint uV;\n\tint min_uV;\n\tint max_uV;\n\tunsigned int mode;\n\tint enabled;\n\tbool changeable;\n};\n\nstruct notification_limit {\n\tint prot;\n\tint err;\n\tint warn;\n};\n\nstruct regulation_constraints {\n\tconst char *name;\n\tint min_uV;\n\tint max_uV;\n\tint uV_offset;\n\tint min_uA;\n\tint max_uA;\n\tint ilim_uA;\n\tint pw_budget_mW;\n\tint system_load;\n\tu32 *max_spread;\n\tint max_uV_step;\n\tunsigned int valid_modes_mask;\n\tunsigned int valid_ops_mask;\n\tint input_uV;\n\tstruct regulator_state state_disk;\n\tstruct regulator_state state_mem;\n\tstruct regulator_state state_standby;\n\tstruct notification_limit over_curr_limits;\n\tstruct notification_limit over_voltage_limits;\n\tstruct notification_limit under_voltage_limits;\n\tstruct notification_limit temp_limits;\n\tsuspend_state_t initial_state;\n\tunsigned int initial_mode;\n\tunsigned int ramp_delay;\n\tunsigned int settling_time;\n\tunsigned int settling_time_up;\n\tunsigned int settling_time_down;\n\tunsigned int enable_time;\n\tunsigned int uv_less_critical_window_ms;\n\tunsigned int active_discharge;\n\tunsigned int always_on: 1;\n\tunsigned int boot_on: 1;\n\tunsigned int apply_uV: 1;\n\tunsigned int ramp_disable: 1;\n\tunsigned int soft_start: 1;\n\tunsigned int pull_down: 1;\n\tunsigned int system_critical: 1;\n\tunsigned int over_current_protection: 1;\n\tunsigned int over_current_detection: 1;\n\tunsigned int over_voltage_detection: 1;\n\tunsigned int under_voltage_detection: 1;\n\tunsigned int over_temp_detection: 1;\n};\n\nstruct regulator_consumer_supply;\n\nstruct regulator_init_data {\n\tconst char *supply_regulator;\n\tstruct regulation_constraints constraints;\n\tint num_consumer_supplies;\n\tstruct regulator_consumer_supply *consumer_supplies;\n\tvoid *driver_data;\n};\n\nstruct da9210_pdata {\n\tstruct regulator_init_data da9210_constraints;\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct davinci_gpio_regs {\n\tu32 dir;\n\tu32 out_data;\n\tu32 set_data;\n\tu32 clr_data;\n\tu32 in_data;\n\tu32 set_rising;\n\tu32 clr_rising;\n\tu32 set_falling;\n\tu32 clr_falling;\n\tu32 intstat;\n};\n\nstruct davinci_gpio_controller {\n\tstruct gpio_chip chip;\n\tstruct irq_domain *irq_domain;\n\tspinlock_t lock;\n\tvoid *regs[5];\n\tint gpio_unbanked;\n\tint irqs[32];\n\tstruct davinci_gpio_regs context[5];\n\tu32 binten_context;\n};\n\nstruct davinci_gpio_irq_data {\n\tvoid *regs;\n\tstruct davinci_gpio_controller *chip;\n\tint bank_num;\n};\n\nstruct davinci_i2c_dev {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct completion cmd_complete;\n\tstruct clk *clk;\n\tint cmd_err;\n\tu8 *buf;\n\tsize_t buf_len;\n\tint irq;\n\tint stop;\n\tu8 terminate;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tstruct notifier_block freq_transition;\n\tunsigned int bus_freq;\n\tbool has_pfunc;\n\tlong: 32;\n};\n\nstruct mdio_platform_data {\n\tlong unsigned int bus_freq;\n};\n\nstruct davinci_mdio_regs;\n\nstruct davinci_mdio_data {\n\tstruct mdio_platform_data pdata;\n\tstruct mdiobb_ctrl bb_ctrl;\n\tstruct davinci_mdio_regs *regs;\n\tstruct clk *clk;\n\tstruct device *dev;\n\tstruct mii_bus *bus;\n\tbool active_in_suspend;\n\tlong unsigned int access_time;\n\tbool skip_scan;\n\tu32 clk_div;\n\tbool manual_mode;\n};\n\nstruct davinci_mdio_of_param {\n\tint autosuspend_delay_ms;\n\tbool manual_mode;\n};\n\nstruct davinci_mdio_regs {\n\tu32 version;\n\tu32 control;\n\tu32 alive;\n\tu32 link;\n\tu32 linkintraw;\n\tu32 linkintmasked;\n\tu32 __reserved_0[2];\n\tu32 userintraw;\n\tu32 userintmasked;\n\tu32 userintmaskset;\n\tu32 userintmaskclr;\n\tu32 manualif;\n\tu32 poll;\n\tu32 __reserved_1[18];\n\tstruct {\n\t\tu32 access;\n\t\tu32 physel;\n\t} user[0];\n};\n\nstruct davinci_nand_info {\n\tstruct nand_controller controller;\n\tstruct nand_chip chip;\n\tstruct platform_device *pdev;\n\tbool is_readmode;\n\tvoid *base;\n\tvoid *vaddr;\n\tvoid *current_cs;\n\tuint32_t mask_chipsel;\n\tuint32_t mask_ale;\n\tuint32_t mask_cle;\n\tuint32_t core_chipsel;\n\tstruct clk *clk;\n\tstruct aemif_device *aemif;\n\tlong: 32;\n};\n\nstruct davinci_nand_pdata {\n\tuint32_t mask_ale;\n\tuint32_t mask_cle;\n\tuint32_t core_chipsel;\n\tuint32_t mask_chipsel;\n\tstruct mtd_partition *parts;\n\tunsigned int nr_parts;\n\tenum nand_ecc_engine_type engine_type;\n\tenum nand_ecc_placement ecc_placement;\n\tu8 ecc_bits;\n\tunsigned int options;\n\tunsigned int bbt_options;\n\tstruct nand_bbt_descr *bbt_td;\n\tstruct nand_bbt_descr *bbt_md;\n};\n\ntypedef u32 (*spi_bb_txrx_word_fn)(struct spi_device *, unsigned int, u32, u8, unsigned int);\n\nstruct spi_bitbang {\n\tstruct mutex lock;\n\tu8 busy;\n\tu8 use_dma;\n\tu16 flags;\n\tstruct spi_controller *ctlr;\n\tint (*setup_transfer)(struct spi_device *, struct spi_transfer *);\n\tvoid (*chipselect)(struct spi_device *, int);\n\tvoid (*set_mosi_idle)(struct spi_device *);\n\tint (*txrx_bufs)(struct spi_device *, struct spi_transfer *);\n\tspi_bb_txrx_word_fn txrx_word[4];\n\tint (*set_line_direction)(struct spi_device *, bool);\n};\n\nstruct davinci_spi_platform_data {\n\tu8 version;\n\tu8 num_chipselect;\n\tu8 intr_line;\n\tu8 prescaler_limit;\n\tbool cshold_bug;\n\tenum dma_event_q dma_event_q;\n};\n\nstruct davinci_spi {\n\tstruct spi_bitbang bitbang;\n\tstruct clk *clk;\n\tu8 version;\n\tresource_size_t pbase;\n\tvoid *base;\n\tu32 irq;\n\tstruct completion done;\n\tconst void *tx;\n\tvoid *rx;\n\tint rcount;\n\tint wcount;\n\tstruct dma_chan *dma_rx;\n\tstruct dma_chan *dma_tx;\n\tstruct davinci_spi_platform_data pdata;\n\tvoid (*get_rx)(u32, struct davinci_spi *);\n\tu32 (*get_tx)(struct davinci_spi *);\n\tu8 *bytes_per_word;\n\tu8 prescaler_limit;\n};\n\nstruct davinci_spi_config {\n\tu8 wdelay;\n\tu8 odd_parity;\n\tu8 parity_enable;\n\tu8 io_type;\n\tu8 timer_disable;\n\tu8 c2tdelay;\n\tu8 t2cdelay;\n\tu8 t2edelay;\n\tu8 c2edelay;\n};\n\nstruct davinci_spi_of_data {\n\tu8 version;\n\tu8 prescaler_limit;\n};\n\nstruct dax_device;\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct db8500_thermal_zone {\n\tstruct thermal_zone_device *tz;\n\tstruct device *dev;\n\tlong unsigned int interpolated_temp;\n\tunsigned int cur_index;\n};\n\nstruct xhci_dbc;\n\nstruct dbc_driver {\n\tint (*configure)(struct xhci_dbc *);\n\tvoid (*disconnect)(struct xhci_dbc *);\n};\n\nstruct xhci_ring;\n\nstruct dbc_ep {\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tstruct xhci_ring *ring;\n\tunsigned int direction: 1;\n\tunsigned int halted: 1;\n};\n\nstruct dbc_regs {\n\t__le32 capability;\n\t__le32 doorbell;\n\t__le32 ersts;\n\t__le32 __reserved_0;\n\t__le64 erstba;\n\t__le64 erdp;\n\t__le32 control;\n\t__le32 status;\n\t__le32 portsc;\n\t__le32 __reserved_1;\n\t__le64 dccp;\n\t__le32 devinfo1;\n\t__le32 devinfo2;\n};\n\nunion xhci_trb;\n\nstruct dbc_request {\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tvoid (*complete)(struct xhci_dbc *, struct dbc_request *);\n\tstruct list_head list_pool;\n\tint status;\n\tunsigned int actual;\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tdma_addr_t trb_dma;\n\tunion xhci_trb *trb;\n\tunsigned int direction: 1;\n};\n\nstruct dbc_str {\n\tchar manufacturer[127];\n\tchar product[127];\n\tchar serial[127];\n};\n\nstruct dbc_str_descs {\n\tchar string0[254];\n\tchar manufacturer[254];\n\tchar product[254];\n\tchar serial[254];\n};\n\nstruct gov_attr_set {\n\tstruct kobject kobj;\n\tstruct list_head policy_list;\n\tstruct mutex update_lock;\n\tint usage_count;\n};\n\nstruct dbs_governor;\n\nstruct dbs_data {\n\tstruct gov_attr_set attr_set;\n\tstruct dbs_governor *gov;\n\tvoid *tuners;\n\tunsigned int ignore_nice_load;\n\tunsigned int sampling_rate;\n\tunsigned int sampling_down_factor;\n\tunsigned int up_threshold;\n\tunsigned int io_is_busy;\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct dbs_governor {\n\tstruct cpufreq_governor gov;\n\tstruct kobj_type kobj_type;\n\tstruct dbs_data *gdbs_data;\n\tunsigned int (*gov_dbs_update)(struct cpufreq_policy *);\n\tstruct policy_dbs_info * (*alloc)(void);\n\tvoid (*free)(struct policy_dbs_info *);\n\tint (*init)(struct dbs_data *);\n\tvoid (*exit)(struct dbs_data *);\n\tvoid (*start)(struct cpufreq_policy *);\n};\n\nstruct dbx500_asic_id {\n\tu16 partnumber;\n\tu8 revision;\n\tu8 process;\n};\n\nstruct dbx500_regulator_info {\n\tstruct regulator_desc desc;\n\tbool is_enabled;\n\tu16 epod_id;\n\tbool is_ramret;\n\tbool exclude_from_power_state;\n};\n\nstruct dc_pinmap {\n\tvoid *regs;\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc *desc;\n\tconst char *pin_names[144];\n\tstruct gpio_chip chip;\n\tspinlock_t lock;\n};\n\nstruct dc_wdt {\n\tvoid *base;\n\tstruct clk *clk;\n\tspinlock_t lock;\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct ddebug_class_map {\n\tstruct list_head link;\n\tstruct module *mod;\n\tconst char *mod_name;\n\tconst char **class_names;\n\tconst int length;\n\tconst int base;\n\tenum class_map_type map_type;\n};\n\nstruct ddrc_reg_config {\n\tu32 type_offset;\n\tu32 type_mask;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct ohci_hcd;\n\nstruct debug_buffer {\n\tssize_t (*fill_func)(struct debug_buffer *);\n\tstruct ohci_hcd *ohci;\n\tstruct mutex mutex;\n\tsize_t count;\n\tchar *page;\n};\n\nstruct debug_info {\n\tstruct perf_event *hbp[32];\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\nstruct debugfs_info {\n\tstruct dentry *debug_dir;\n\tvoid *rasdes_info;\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct decode_header;\n\ntypedef enum probes_insn probes_custom_decode_t(probes_opcode_t, struct arch_probes_insn *, const struct decode_header *);\n\nunion decode_action {\n\tprobes_insn_handler_t *handler;\n\tprobes_custom_decode_t *decoder;\n};\n\ntypedef enum probes_insn probes_check_t(probes_opcode_t, struct arch_probes_insn *, const struct decode_header *);\n\nstruct decode_checker {\n\tprobes_check_t *checker;\n};\n\nunion decode_item {\n\tu32 bits;\n\tconst union decode_item *table;\n\tint action;\n};\n\nstruct decode_header {\n\tunion decode_item type_regs;\n\tunion decode_item mask;\n\tunion decode_item value;\n};\n\nstruct decode_custom {\n\tstruct decode_header header;\n\tunion decode_item decoder;\n};\n\nstruct decode_emulate {\n\tstruct decode_header header;\n\tunion decode_item handler;\n};\n\nstruct decode_simulate {\n\tstruct decode_header header;\n\tunion decode_item handler;\n};\n\nstruct decode_table {\n\tstruct decode_header header;\n\tunion decode_item table;\n};\n\nstruct skcipher_request;\n\nstruct decryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tstruct scatterlist frags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct z_stream_s;\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct static_tree_desc_s;\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\nstruct tree_desc_s {\n\tct_data *dyn_tree;\n\tint max_code;\n\tstatic_tree_desc *stat_desc;\n};\n\nstruct deflate_state {\n\tz_streamp strm;\n\tint status;\n\tByte *pending_buf;\n\tulg pending_buf_size;\n\tByte *pending_out;\n\tint pending;\n\tint noheader;\n\tByte data_type;\n\tByte method;\n\tint last_flush;\n\tuInt w_size;\n\tuInt w_bits;\n\tuInt w_mask;\n\tByte *window;\n\tulg window_size;\n\tPos *prev;\n\tPos *head;\n\tuInt ins_h;\n\tuInt hash_size;\n\tuInt hash_bits;\n\tuInt hash_mask;\n\tuInt hash_shift;\n\tlong int block_start;\n\tuInt match_length;\n\tIPos prev_match;\n\tint match_available;\n\tuInt strstart;\n\tuInt match_start;\n\tuInt lookahead;\n\tuInt prev_length;\n\tuInt max_chain_length;\n\tuInt max_lazy_match;\n\tint level;\n\tint strategy;\n\tuInt good_match;\n\tint nice_match;\n\tstruct ct_data_s dyn_ltree[573];\n\tstruct ct_data_s dyn_dtree[61];\n\tstruct ct_data_s bl_tree[39];\n\tstruct tree_desc_s l_desc;\n\tstruct tree_desc_s d_desc;\n\tstruct tree_desc_s bl_desc;\n\tush bl_count[16];\n\tint heap[573];\n\tint heap_len;\n\tint heap_max;\n\tuch depth[573];\n\tuch *l_buf;\n\tuInt lit_bufsize;\n\tuInt last_lit;\n\tush *d_buf;\n\tulg opt_len;\n\tulg static_len;\n\tulg compressed_len;\n\tuInt matches;\n\tint last_eob_len;\n\tush bi_buf;\n\tint bi_valid;\n};\n\nstruct internal_state;\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\nstruct deflate_stream {\n\tstruct z_stream_s stream;\n\tu8 workspace[0];\n};\n\nstruct deflate_workspace {\n\tdeflate_state deflate_memory;\n\tByte *window_memory;\n\tPos *prev_memory;\n\tPos *head_memory;\n\tchar *overlay_memory;\n};\n\ntypedef struct deflate_workspace deflate_workspace;\n\nstruct delay_timer {\n\tlong unsigned int (*read_current_timer)(void);\n\tlong unsigned int freq;\n};\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct filename;\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct denali_chip_sel {\n\tint bank;\n\tu32 hwhr2_and_we_2_re;\n\tu32 tcwaw_and_addr_2_data;\n\tu32 re_2_we;\n\tu32 acc_clks;\n\tu32 rdwr_en_lo_cnt;\n\tu32 rdwr_en_hi_cnt;\n\tu32 cs_setup_cnt;\n\tu32 re_2_re;\n};\n\nstruct denali_chip {\n\tstruct nand_chip chip;\n\tstruct list_head node;\n\tunsigned int nsels;\n\tstruct denali_chip_sel sels[0];\n\tlong: 32;\n};\n\nstruct nand_ecc_caps;\n\nstruct denali_controller {\n\tstruct nand_controller controller;\n\tstruct device *dev;\n\tstruct list_head chips;\n\tlong unsigned int clk_rate;\n\tlong unsigned int clk_x_rate;\n\tvoid *reg;\n\tvoid *host;\n\tstruct completion complete;\n\tint irq;\n\tu32 irq_mask;\n\tu32 irq_status;\n\tspinlock_t irq_lock;\n\tbool dma_avail;\n\tint devs_per_cs;\n\tint oob_skip_bytes;\n\tint active_bank;\n\tint nbanks;\n\tunsigned int revision;\n\tunsigned int caps;\n\tconst struct nand_ecc_caps *ecc_caps;\n\tu32 (*host_read)(struct denali_controller *, u32);\n\tvoid (*host_write)(struct denali_controller *, u32, u32);\n\tvoid (*setup_dma)(struct denali_controller *, dma_addr_t, int, bool);\n};\n\nstruct denali_dt {\n\tstruct denali_controller controller;\n\tstruct clk *clk;\n\tstruct clk *clk_x;\n\tstruct clk *clk_ecc;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_reg;\n};\n\nstruct denali_dt_data {\n\tunsigned int revision;\n\tunsigned int caps;\n\tunsigned int oob_skip_bytes;\n\tconst struct nand_ecc_caps *ecc_caps;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nunion shortname_store {\n\tunsigned char string[36];\n\tlong unsigned int words[9];\n};\n\nstruct lockref {\n\tunion {\n\t\t__u64 lock_count;\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tlong: 32;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n\tlong: 32;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_info_args {\n\tint parent_ino;\n\tint dname_len;\n\tint ino;\n\tint inode_len;\n\tchar *dname;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 32;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct detailed_data_monitor_range {\n\tu8 min_vfreq;\n\tu8 max_vfreq;\n\tu8 min_hfreq_khz;\n\tu8 max_hfreq_khz;\n\tu8 pixel_clock_mhz;\n\tu8 flags;\n\tunion {\n\t\tstruct {\n\t\t\tu8 reserved;\n\t\t\tu8 hfreq_start_khz;\n\t\t\tu8 c;\n\t\t\t__le16 m;\n\t\t\tu8 k;\n\t\t\tu8 j;\n\t\t} __attribute__((packed)) gtf2;\n\t\tstruct {\n\t\t\tu8 version;\n\t\t\tu8 data1;\n\t\t\tu8 data2;\n\t\t\tu8 supported_aspects;\n\t\t\tu8 flags;\n\t\t\tu8 supported_scalings;\n\t\t\tu8 preferred_refresh;\n\t\t} cvt;\n\t} formula;\n};\n\nstruct detailed_data_string {\n\tu8 str[13];\n};\n\nstruct detailed_data_wpindex {\n\tu8 white_yx_lo;\n\tu8 white_x_hi;\n\tu8 white_y_hi;\n\tu8 gamma;\n};\n\nstruct detailed_mode_closure {\n\tstruct drm_connector *connector;\n\tconst struct drm_edid *drm_edid;\n\tbool preferred;\n\tint modes;\n};\n\nstruct std_timing {\n\tu8 hsize;\n\tu8 vfreq_aspect;\n};\n\nstruct detailed_non_pixel {\n\tu8 pad1;\n\tu8 type;\n\tu8 pad2;\n\tunion {\n\t\tstruct detailed_data_string str;\n\t\tstruct detailed_data_monitor_range range;\n\t\tstruct detailed_data_wpindex color;\n\t\tstruct std_timing timings[6];\n\t\tstruct cvt_timing cvt[4];\n\t} data;\n};\n\nstruct detailed_pixel_timing {\n\tu8 hactive_lo;\n\tu8 hblank_lo;\n\tu8 hactive_hblank_hi;\n\tu8 vactive_lo;\n\tu8 vblank_lo;\n\tu8 vactive_vblank_hi;\n\tu8 hsync_offset_lo;\n\tu8 hsync_pulse_width_lo;\n\tu8 vsync_offset_pulse_width_lo;\n\tu8 hsync_vsync_offset_pulse_width_hi;\n\tu8 width_mm_lo;\n\tu8 height_mm_lo;\n\tu8 width_height_mm_hi;\n\tu8 hborder;\n\tu8 vborder;\n\tu8 misc;\n};\n\nstruct detailed_timing {\n\t__le16 pixel_clock;\n\tunion {\n\t\tstruct detailed_pixel_timing pixel_data;\n\t\tstruct detailed_non_pixel other_data;\n\t} data;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct iommu_device;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n\tu32 max_pasids;\n\tu32 attach_deferred: 1;\n\tu32 pci_32bit_workaround: 1;\n\tu32 require_direct: 1;\n\tu32 shadow_on_flush: 1;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct dev_pin_info {\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *default_state;\n\tstruct pinctrl_state *init_state;\n\tstruct pinctrl_state *sleep_state;\n\tstruct pinctrl_state *idle_state;\n};\n\nstruct dev_pm_domain_attach_data {\n\tconst char * const *pd_names;\n\tconst u32 num_pd_names;\n\tconst u32 pd_flags;\n};\n\nstruct device_link;\n\nstruct dev_pm_domain_list {\n\tstruct device **pd_devs;\n\tstruct device_link **pd_links;\n\tu32 *opp_tokens;\n\tu32 num_pds;\n};\n\nstruct dev_pm_opp_supply;\n\nstruct dev_pm_opp_icc_bw;\n\nstruct dev_pm_opp {\n\tstruct list_head node;\n\tstruct kref kref;\n\tbool available;\n\tbool dynamic;\n\tbool turbo;\n\tbool suspend;\n\tbool removed;\n\tlong unsigned int *rates;\n\tunsigned int level;\n\tstruct dev_pm_opp_supply *supplies;\n\tstruct dev_pm_opp_icc_bw *bandwidth;\n\tlong unsigned int clock_latency_ns;\n\tstruct dev_pm_opp **required_opps;\n\tstruct opp_table *opp_table;\n\tstruct device_node *np;\n\tstruct dentry *dentry;\n\tconst char *of_name;\n};\n\ntypedef int (*config_clks_t)(struct device *, struct opp_table *, struct dev_pm_opp *, void *, bool);\n\ntypedef int (*config_regulators_t)(struct device *, struct dev_pm_opp *, struct dev_pm_opp *, struct regulator **, unsigned int);\n\nstruct dev_pm_opp_config {\n\tconst char * const *clk_names;\n\tconfig_clks_t config_clks;\n\tconst char *prop_name;\n\tconfig_regulators_t config_regulators;\n\tconst unsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char * const *regulator_names;\n\tstruct device *required_dev;\n\tunsigned int required_dev_index;\n};\n\nstruct dev_pm_opp_data {\n\tbool turbo;\n\tunsigned int level;\n\tlong unsigned int freq;\n\tlong unsigned int u_volt;\n};\n\nstruct dev_pm_opp_icc_bw {\n\tu32 avg;\n\tu32 peak;\n};\n\nstruct dev_pm_opp_key {\n\tlong unsigned int freq;\n\tunsigned int level;\n\tu32 bw;\n};\n\nstruct dev_pm_opp_supply {\n\tlong unsigned int u_volt;\n\tlong unsigned int u_volt_min;\n\tlong unsigned int u_volt_max;\n\tlong unsigned int u_amp;\n\tlong unsigned int u_watt;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_power_governor {\n\tbool (*system_power_down_ok)(struct dev_pm_domain *);\n\tbool (*power_down_ok)(struct dev_pm_domain *);\n\tbool (*suspend_ok)(struct device *);\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\nstruct devbus {\n\tstruct device *dev;\n\tvoid *base;\n\tlong unsigned int tick_ps;\n};\n\nstruct devbus_read_params {\n\tu32 bus_width;\n\tu32 badr_skew;\n\tu32 turn_off;\n\tu32 acc_first;\n\tu32 acc_next;\n\tu32 rd_setup;\n\tu32 rd_hold;\n};\n\nstruct devbus_write_params {\n\tu32 sync_enable;\n\tu32 wr_high;\n\tu32 wr_low;\n\tu32 ale_wr;\n};\n\nstruct devcd_entry {\n\tstruct device devcd_dev;\n\tvoid *data;\n\tsize_t datalen;\n\tstruct mutex mutex;\n\tbool init_completed;\n\tbool deleted;\n\tstruct module *owner;\n\tssize_t (*read)(char *, loff_t, size_t, void *, size_t);\n\tvoid (*free)(void *);\n\tstruct delayed_work del_wk;\n\tstruct device *failing_dev;\n\tlong: 32;\n};\n\nstruct devfreq_dev_status {\n\tlong unsigned int total_time;\n\tlong unsigned int busy_time;\n\tlong unsigned int current_frequency;\n\tvoid *private_data;\n};\n\nstruct devfreq_stats {\n\tunsigned int total_trans;\n\tunsigned int *trans_table;\n\tu64 *time_in_state;\n\tlong: 32;\n\tu64 last_update;\n};\n\nstruct devfreq_dev_profile;\n\nstruct devfreq_governor;\n\nstruct devfreq {\n\tstruct list_head node;\n\tstruct mutex lock;\n\tlong: 32;\n\tstruct device dev;\n\tstruct devfreq_dev_profile *profile;\n\tconst struct devfreq_governor *governor;\n\tstruct opp_table *opp_table;\n\tstruct notifier_block nb;\n\tstruct delayed_work work;\n\tlong unsigned int *freq_table;\n\tunsigned int max_state;\n\tlong unsigned int previous_freq;\n\tstruct devfreq_dev_status last_status;\n\tvoid *data;\n\tvoid *governor_data;\n\tstruct dev_pm_qos_request user_min_freq_req;\n\tstruct dev_pm_qos_request user_max_freq_req;\n\tlong unsigned int scaling_min_freq;\n\tlong unsigned int scaling_max_freq;\n\tbool stop_polling;\n\tlong unsigned int suspend_freq;\n\tlong unsigned int resume_freq;\n\tatomic_t suspend_count;\n\tstruct devfreq_stats stats;\n\tstruct srcu_notifier_head transition_notifier_list;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct devfreq_cooling_power;\n\nstruct devfreq_cooling_device {\n\tstruct thermal_cooling_device *cdev;\n\tstruct thermal_cooling_device_ops cooling_ops;\n\tstruct devfreq *devfreq;\n\tlong unsigned int cooling_state;\n\tu32 *freq_table;\n\tsize_t max_state;\n\tstruct devfreq_cooling_power *power_ops;\n\tu32 res_util;\n\tint capped_state;\n\tstruct dev_pm_qos_request req_max_freq;\n\tstruct em_perf_domain *em_pd;\n};\n\nstruct devfreq_cooling_power {\n\tint (*get_real_power)(struct devfreq *, u32 *, long unsigned int, long unsigned int);\n};\n\nstruct devfreq_dev_profile {\n\tlong unsigned int initial_freq;\n\tunsigned int polling_ms;\n\tenum devfreq_timer timer;\n\tint (*target)(struct device *, long unsigned int *, u32);\n\tint (*get_dev_status)(struct device *, struct devfreq_dev_status *);\n\tint (*get_cur_freq)(struct device *, long unsigned int *);\n\tvoid (*exit)(struct device *);\n\tlong unsigned int *freq_table;\n\tunsigned int max_state;\n\tbool is_cooling_device;\n\tconst struct attribute_group **dev_groups;\n};\n\nstruct devfreq_event_data {\n\tlong unsigned int load_count;\n\tlong unsigned int total_count;\n};\n\nstruct devfreq_event_ops;\n\nstruct devfreq_event_desc {\n\tconst char *name;\n\tu32 event_type;\n\tvoid *driver_data;\n\tconst struct devfreq_event_ops *ops;\n};\n\nstruct devfreq_event_dev {\n\tstruct list_head node;\n\tstruct device dev;\n\tstruct mutex lock;\n\tu32 enable_count;\n\tconst struct devfreq_event_desc *desc;\n\tlong: 32;\n};\n\nstruct devfreq_event_ops {\n\tint (*enable)(struct devfreq_event_dev *);\n\tint (*disable)(struct devfreq_event_dev *);\n\tint (*reset)(struct devfreq_event_dev *);\n\tint (*set_event)(struct devfreq_event_dev *);\n\tint (*get_event)(struct devfreq_event_dev *, struct devfreq_event_data *);\n};\n\nstruct devfreq_freqs {\n\tlong unsigned int old;\n\tlong unsigned int new;\n};\n\nstruct devfreq_governor {\n\tstruct list_head node;\n\tconst char name[16];\n\tconst u64 attrs;\n\tconst u64 flags;\n\tint (*get_target_freq)(struct devfreq *, long unsigned int *);\n\tint (*event_handler)(struct devfreq *, unsigned int, void *);\n};\n\nstruct devfreq_notifier_devres {\n\tstruct devfreq *devfreq;\n\tstruct notifier_block *nb;\n\tunsigned int list;\n};\n\nstruct devfreq_passive_data {\n\tstruct devfreq *parent;\n\tint (*get_target_freq)(struct devfreq *, long unsigned int *);\n\tenum devfreq_parent_dev_type parent_type;\n\tstruct devfreq *this;\n\tstruct notifier_block nb;\n\tstruct list_head cpu_data_list;\n};\n\nstruct devfreq_simple_ondemand_data {\n\tunsigned int upthreshold;\n\tunsigned int downdifferential;\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_pm_runtime_active_auto_t;\n\ntypedef class_pm_runtime_active_auto_t class_pm_runtime_active_auto_try_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\ntypedef struct device *class_pm_runtime_noresume_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n\tlong: 32;\n};\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tstruct kobject kobj;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n};\n\nstruct devlink_dev_stats {\n\tu32 reload_stats[6];\n\tu32 remote_reload_stats[6];\n};\n\nstruct devlink_dpipe_headers;\n\nstruct devlink_ops;\n\nstruct devlink_rel;\n\nstruct devlink {\n\tu32 index;\n\tstruct xarray ports;\n\tstruct list_head rate_list;\n\tstruct list_head sb_list;\n\tstruct list_head dpipe_table_list;\n\tstruct list_head resource_list;\n\tstruct xarray params;\n\tstruct list_head region_list;\n\tstruct list_head reporter_list;\n\tstruct devlink_dpipe_headers *dpipe_headers;\n\tstruct list_head trap_list;\n\tstruct list_head trap_group_list;\n\tstruct list_head trap_policer_list;\n\tstruct list_head linecard_list;\n\tconst struct devlink_ops *ops;\n\tstruct xarray snapshot_ids;\n\tstruct devlink_dev_stats stats;\n\tstruct device *dev;\n\tpossible_net_t _net;\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tu8 reload_failed: 1;\n\trefcount_t refcount;\n\tstruct rcu_work rwork;\n\tstruct devlink_rel *rel;\n\tstruct xarray nested_rels;\n\tchar priv[0];\n};\n\nstruct devlink_dpipe_header;\n\nstruct devlink_dpipe_action {\n\tenum devlink_dpipe_action_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct genl_info;\n\nstruct devlink_dpipe_dump_ctx {\n\tstruct genl_info *info;\n\tenum devlink_command cmd;\n\tstruct sk_buff *skb;\n\tstruct nlattr *nest;\n\tvoid *hdr;\n};\n\nstruct devlink_dpipe_value;\n\nstruct devlink_dpipe_entry {\n\tu64 index;\n\tstruct devlink_dpipe_value *match_values;\n\tunsigned int match_values_count;\n\tstruct devlink_dpipe_value *action_values;\n\tunsigned int action_values_count;\n\tu64 counter;\n\tbool counter_valid;\n\tlong: 32;\n};\n\nstruct devlink_dpipe_field {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int bitwidth;\n\tenum devlink_dpipe_field_mapping_type mapping_type;\n};\n\nstruct devlink_dpipe_header {\n\tconst char *name;\n\tunsigned int id;\n\tstruct devlink_dpipe_field *fields;\n\tunsigned int fields_count;\n\tbool global;\n};\n\nstruct devlink_dpipe_headers {\n\tstruct devlink_dpipe_header **headers;\n\tunsigned int headers_count;\n};\n\nstruct devlink_dpipe_match {\n\tenum devlink_dpipe_match_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct devlink_dpipe_table_ops;\n\nstruct devlink_dpipe_table {\n\tvoid *priv;\n\tstruct list_head list;\n\tconst char *name;\n\tbool counters_enabled;\n\tbool counter_control_extern;\n\tbool resource_valid;\n\tlong: 32;\n\tu64 resource_id;\n\tu64 resource_units;\n\tconst struct devlink_dpipe_table_ops *table_ops;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct devlink_dpipe_table_ops {\n\tint (*actions_dump)(void *, struct sk_buff *);\n\tint (*matches_dump)(void *, struct sk_buff *);\n\tint (*entries_dump)(void *, bool, struct devlink_dpipe_dump_ctx *);\n\tint (*counters_set_update)(void *, bool);\n\tu64 (*size_get)(void *);\n};\n\nstruct devlink_dpipe_value {\n\tunion {\n\t\tstruct devlink_dpipe_action *action;\n\t\tstruct devlink_dpipe_match *match;\n\t};\n\tunsigned int mapping_value;\n\tbool mapping_valid;\n\tunsigned int value_size;\n\tvoid *value;\n\tvoid *mask;\n};\n\nstruct devlink_flash_component_lookup_ctx {\n\tconst char *lookup_name;\n\tbool lookup_name_found;\n};\n\nstruct devlink_flash_notify {\n\tconst char *status_msg;\n\tconst char *component;\n\tlong unsigned int done;\n\tlong unsigned int total;\n\tlong unsigned int timeout;\n};\n\nstruct firmware;\n\nstruct devlink_flash_update_params {\n\tconst struct firmware *fw;\n\tconst char *component;\n\tu32 overwrite_mask;\n};\n\nstruct devlink_fmsg {\n\tstruct list_head item_list;\n\tint err;\n\tbool putting_binary;\n};\n\nstruct devlink_fmsg_item {\n\tstruct list_head list;\n\tint attrtype;\n\tu8 nla_type;\n\tu16 len;\n\tint value[0];\n};\n\nstruct devlink_health_reporter_ops;\n\nstruct devlink_port;\n\nstruct devlink_health_reporter {\n\tstruct list_head list;\n\tvoid *priv;\n\tconst struct devlink_health_reporter_ops *ops;\n\tstruct devlink *devlink;\n\tstruct devlink_port *devlink_port;\n\tstruct devlink_fmsg *dump_fmsg;\n\tlong: 32;\n\tu64 graceful_period;\n\tu64 burst_period;\n\tbool auto_recover;\n\tbool auto_dump;\n\tu8 health_state;\n\tlong: 32;\n\tu64 dump_ts;\n\tu64 dump_real_ts;\n\tu64 error_count;\n\tu64 recovery_count;\n\tu64 last_recovery_ts;\n};\n\nstruct devlink_health_reporter_ops {\n\tchar *name;\n\tint (*recover)(struct devlink_health_reporter *, void *, struct netlink_ext_ack *);\n\tint (*dump)(struct devlink_health_reporter *, struct devlink_fmsg *, void *, struct netlink_ext_ack *);\n\tint (*diagnose)(struct devlink_health_reporter *, struct devlink_fmsg *, struct netlink_ext_ack *);\n\tint (*test)(struct devlink_health_reporter *, struct netlink_ext_ack *);\n\tlong: 32;\n\tu64 default_graceful_period;\n\tu64 default_burst_period;\n};\n\nstruct devlink_info_req {\n\tstruct sk_buff *msg;\n\tvoid (*version_cb)(const char *, enum devlink_info_version_type, void *);\n\tvoid *version_cb_priv;\n};\n\nstruct devlink_linecard_ops;\n\nstruct devlink_linecard_type;\n\nstruct devlink_linecard {\n\tstruct list_head list;\n\tstruct devlink *devlink;\n\tunsigned int index;\n\tconst struct devlink_linecard_ops *ops;\n\tvoid *priv;\n\tenum devlink_linecard_state state;\n\tstruct mutex state_lock;\n\tconst char *type;\n\tstruct devlink_linecard_type *types;\n\tunsigned int types_count;\n\tu32 rel_index;\n};\n\nstruct devlink_linecard_ops {\n\tint (*provision)(struct devlink_linecard *, void *, const char *, const void *, struct netlink_ext_ack *);\n\tint (*unprovision)(struct devlink_linecard *, void *, struct netlink_ext_ack *);\n\tbool (*same_provision)(struct devlink_linecard *, void *, const char *, const void *);\n\tunsigned int (*types_count)(struct devlink_linecard *, void *);\n\tvoid (*types_get)(struct devlink_linecard *, void *, unsigned int, const char **, const void **);\n};\n\nstruct devlink_linecard_type {\n\tconst char *type;\n\tconst void *priv;\n};\n\nstruct devlink_nl_dump_state {\n\tlong unsigned int instance;\n\tint idx;\n\tunion {\n\t\tstruct {\n\t\t\tu64 start_offset;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dump_ts;\n\t\t};\n\t};\n};\n\nstruct devlink_obj_desc;\n\nstruct devlink_nl_sock_priv {\n\tstruct devlink_obj_desc *flt;\n\tspinlock_t flt_lock;\n};\n\nstruct devlink_obj_desc {\n\tstruct callback_head rcu;\n\tconst char *bus_name;\n\tconst char *dev_name;\n\tunsigned int port_index;\n\tbool port_index_valid;\n\tlong int data[0];\n};\n\nstruct devlink_sb_pool_info;\n\nstruct devlink_trap;\n\nstruct devlink_trap_group;\n\nstruct devlink_trap_policer;\n\nstruct devlink_port_new_attrs;\n\nstruct devlink_rate;\n\nstruct devlink_ops {\n\tu32 supported_flash_update_params;\n\tlong unsigned int reload_actions;\n\tlong unsigned int reload_limits;\n\tint (*reload_down)(struct devlink *, bool, enum devlink_reload_action, enum devlink_reload_limit, struct netlink_ext_ack *);\n\tint (*reload_up)(struct devlink *, enum devlink_reload_action, enum devlink_reload_limit, u32 *, struct netlink_ext_ack *);\n\tint (*sb_pool_get)(struct devlink *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*sb_pool_set)(struct devlink *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*sb_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *);\n\tint (*sb_port_pool_set)(struct devlink_port *, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_tc_pool_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*sb_tc_pool_bind_set)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_occ_snapshot)(struct devlink *, unsigned int);\n\tint (*sb_occ_max_clear)(struct devlink *, unsigned int);\n\tint (*sb_occ_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *, u32 *);\n\tint (*sb_occ_tc_port_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*eswitch_mode_get)(struct devlink *, u16 *);\n\tint (*eswitch_mode_set)(struct devlink *, u16, struct netlink_ext_ack *);\n\tint (*eswitch_inline_mode_get)(struct devlink *, u8 *);\n\tint (*eswitch_inline_mode_set)(struct devlink *, u8, struct netlink_ext_ack *);\n\tint (*eswitch_encap_mode_get)(struct devlink *, enum devlink_eswitch_encap_mode *);\n\tint (*eswitch_encap_mode_set)(struct devlink *, enum devlink_eswitch_encap_mode, struct netlink_ext_ack *);\n\tint (*info_get)(struct devlink *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*flash_update)(struct devlink *, struct devlink_flash_update_params *, struct netlink_ext_ack *);\n\tint (*trap_init)(struct devlink *, const struct devlink_trap *, void *);\n\tvoid (*trap_fini)(struct devlink *, const struct devlink_trap *, void *);\n\tint (*trap_action_set)(struct devlink *, const struct devlink_trap *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_group_init)(struct devlink *, const struct devlink_trap_group *);\n\tint (*trap_group_set)(struct devlink *, const struct devlink_trap_group *, const struct devlink_trap_policer *, struct netlink_ext_ack *);\n\tint (*trap_group_action_set)(struct devlink *, const struct devlink_trap_group *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_drop_counter_get)(struct devlink *, const struct devlink_trap *, u64 *);\n\tint (*trap_policer_init)(struct devlink *, const struct devlink_trap_policer *);\n\tvoid (*trap_policer_fini)(struct devlink *, const struct devlink_trap_policer *);\n\tint (*trap_policer_set)(struct devlink *, const struct devlink_trap_policer *, u64, u64, struct netlink_ext_ack *);\n\tint (*trap_policer_counter_get)(struct devlink *, const struct devlink_trap_policer *, u64 *);\n\tint (*port_new)(struct devlink *, const struct devlink_port_new_attrs *, struct netlink_ext_ack *, struct devlink_port **);\n\tint (*rate_leaf_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_new)(struct devlink_rate *, void **, struct netlink_ext_ack *);\n\tint (*rate_node_del)(struct devlink_rate *, void *, struct netlink_ext_ack *);\n\tint (*rate_leaf_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tint (*rate_node_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tbool (*selftest_check)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n\tenum devlink_selftest_status (*selftest_run)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n};\n\nstruct devlink_param_gset_ctx;\n\nunion devlink_param_value;\n\nstruct devlink_param {\n\tu32 id;\n\tconst char *name;\n\tbool generic;\n\tenum devlink_param_type type;\n\tlong unsigned int supported_cmodes;\n\tint (*get)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*set)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*validate)(struct devlink *, u32, union devlink_param_value, struct netlink_ext_ack *);\n\tint (*get_default)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*reset_default)(struct devlink *, u32, enum devlink_param_cmode, struct netlink_ext_ack *);\n};\n\nunion devlink_param_value {\n\tu8 vu8;\n\tu16 vu16;\n\tu32 vu32;\n\tu64 vu64;\n\tchar vstr[32];\n\tbool vbool;\n};\n\nstruct devlink_param_gset_ctx {\n\tunion devlink_param_value val;\n\tenum devlink_param_cmode cmode;\n\tlong: 32;\n};\n\nstruct devlink_param_item {\n\tstruct list_head list;\n\tconst struct devlink_param *param;\n\tlong: 32;\n\tunion devlink_param_value driverinit_value;\n\tbool driverinit_value_valid;\n\tlong: 32;\n\tunion devlink_param_value driverinit_value_new;\n\tbool driverinit_value_new_valid;\n\tlong: 32;\n\tunion devlink_param_value driverinit_default;\n};\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_port_ops;\n\nstruct ib_device;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct devlink_port_new_attrs {\n\tenum devlink_port_flavour flavour;\n\tunsigned int port_index;\n\tu32 controller;\n\tu32 sfnum;\n\tu16 pfnum;\n\tu8 port_index_valid: 1;\n\tu8 controller_valid: 1;\n\tu8 sfnum_valid: 1;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_port_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tlong: 32;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n\tlong: 32;\n};\n\nstruct devlink_region_ops;\n\nstruct devlink_region {\n\tstruct devlink *devlink;\n\tstruct devlink_port *port;\n\tstruct list_head list;\n\tunion {\n\t\tconst struct devlink_region_ops *ops;\n\t\tconst struct devlink_port_region_ops *port_ops;\n\t};\n\tstruct mutex snapshot_lock;\n\tstruct list_head snapshot_list;\n\tu32 max_snapshots;\n\tu32 cur_snapshots;\n\tu64 size;\n};\n\nstruct devlink_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\ntypedef void devlink_rel_notify_cb_t(struct devlink *, u32);\n\ntypedef void devlink_rel_cleanup_cb_t(struct devlink *, u32, u32);\n\nstruct devlink_rel {\n\tu32 index;\n\trefcount_t refcount;\n\tu32 devlink_index;\n\tstruct {\n\t\tu32 devlink_index;\n\t\tu32 obj_index;\n\t\tdevlink_rel_notify_cb_t *notify_cb;\n\t\tdevlink_rel_cleanup_cb_t *cleanup_cb;\n\t\tstruct delayed_work notify_work;\n\t} nested_in;\n};\n\nstruct devlink_reload_combination {\n\tenum devlink_reload_action action;\n\tenum devlink_reload_limit limit;\n};\n\nstruct devlink_resource_size_params {\n\tu64 size_min;\n\tu64 size_max;\n\tu64 size_granularity;\n\tenum devlink_resource_unit unit;\n\tlong: 32;\n};\n\ntypedef u64 devlink_resource_occ_get_t(void *);\n\nstruct devlink_resource {\n\tconst char *name;\n\tlong: 32;\n\tu64 id;\n\tu64 size;\n\tu64 size_new;\n\tbool size_valid;\n\tstruct devlink_resource *parent;\n\tstruct devlink_resource_size_params size_params;\n\tstruct list_head list;\n\tstruct list_head resource_list;\n\tdevlink_resource_occ_get_t *occ_get;\n\tvoid *occ_get_priv;\n};\n\nstruct devlink_sb {\n\tstruct list_head list;\n\tunsigned int index;\n\tu32 size;\n\tu16 ingress_pools_count;\n\tu16 egress_pools_count;\n\tu16 ingress_tc_count;\n\tu16 egress_tc_count;\n};\n\nstruct devlink_sb_pool_info {\n\tenum devlink_sb_pool_type pool_type;\n\tu32 size;\n\tenum devlink_sb_threshold_type threshold_type;\n\tu32 cell_size;\n};\n\nstruct devlink_snapshot {\n\tstruct list_head list;\n\tstruct devlink_region *region;\n\tu8 *data;\n\tu32 id;\n};\n\nstruct devlink_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct devlink_trap {\n\tenum devlink_trap_type type;\n\tenum devlink_trap_action init_action;\n\tbool generic;\n\tu16 id;\n\tconst char *name;\n\tu16 init_group_id;\n\tu32 metadata_cap;\n};\n\nstruct devlink_trap_group {\n\tconst char *name;\n\tu16 id;\n\tbool generic;\n\tu32 init_policer_id;\n};\n\nstruct devlink_trap_policer_item;\n\nstruct devlink_trap_group_item {\n\tconst struct devlink_trap_group *group;\n\tstruct devlink_trap_policer_item *policer_item;\n\tstruct list_head list;\n\tstruct devlink_stats *stats;\n};\n\nstruct devlink_trap_item {\n\tconst struct devlink_trap *trap;\n\tstruct devlink_trap_group_item *group_item;\n\tstruct list_head list;\n\tenum devlink_trap_action action;\n\tstruct devlink_stats *stats;\n\tvoid *priv;\n};\n\nstruct flow_action_cookie;\n\nstruct devlink_trap_metadata {\n\tconst char *trap_name;\n\tconst char *trap_group_name;\n\tstruct net_device *input_dev;\n\tnetdevice_tracker dev_tracker;\n\tconst struct flow_action_cookie *fa_cookie;\n\tenum devlink_trap_type trap_type;\n};\n\nstruct devlink_trap_policer {\n\tu32 id;\n\tlong: 32;\n\tu64 init_rate;\n\tu64 init_burst;\n\tu64 max_rate;\n\tu64 min_rate;\n\tu64 max_burst;\n\tu64 min_burst;\n};\n\nstruct devlink_trap_policer_item {\n\tconst struct devlink_trap_policer *policer;\n\tlong: 32;\n\tu64 rate;\n\tu64 burst;\n\tstruct list_head list;\n};\n\nstruct devm_clk_state {\n\tstruct clk *clk;\n\tvoid (*exit)(struct clk *);\n};\n\nstruct of_regulator_match;\n\nstruct devm_of_regulator_matches {\n\tstruct of_regulator_match *matches;\n\tunsigned int num_matches;\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nunion dfixed {\n\tu32 full;\n};\n\ntypedef union dfixed fixed20_12;\n\nstruct dfll_fcpu_data {\n\tconst long unsigned int *cpu_max_freq_table;\n\tunsigned int cpu_max_freq_table_size;\n\tconst struct cvb_table *cpu_cvb_tables;\n\tunsigned int cpu_cvb_tables_size;\n};\n\nstruct dfll_rate_req {\n\tlong unsigned int rate;\n\tlong unsigned int dvco_target_rate;\n\tint lut_index;\n\tu8 mult_bits;\n\tu8 scale_bits;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct digicolor_port {\n\tstruct uart_port port;\n\tstruct delayed_work rx_poll_work;\n\tlong: 32;\n};\n\nstruct digicolor_timer {\n\tstruct clock_event_device ce;\n\tvoid *base;\n\tu32 ticks_per_jiffy;\n\tint timer_id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n\tlong: 32;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\nstruct dimm_info {\n\tstruct device dev;\n\tchar label[32];\n\tunsigned int location[3];\n\tstruct mem_ctl_info *mci;\n\tunsigned int idx;\n\tu32 grain;\n\tenum dev_type dtype;\n\tenum mem_type mtype;\n\tenum edac_type edac_mode;\n\tu32 nr_pages;\n\tunsigned int csrow;\n\tunsigned int cschannel;\n\tu16 smbios_handle;\n\tu32 ce_count;\n\tu32 ue_count;\n\tlong: 32;\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\nstruct dio {\n\tint flags;\n\tblk_opf_t opf;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tbool is_pinned;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tlong: 32;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tlong: 32;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n\tlong: 32;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tlong: 32;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tlong: 32;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n\tlong: 32;\n\tu64 cookie;\n\tbool initialized;\n\tlong: 32;\n};\n\nstruct dirty_throttle_control {\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct disk_comp_opts {\n\t__le32 dictionary_size;\n\t__le32 flags;\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n\tlong: 32;\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct timing_entry {\n\tu32 min;\n\tu32 typ;\n\tu32 max;\n};\n\nstruct display_timing {\n\tstruct timing_entry pixelclock;\n\tstruct timing_entry hactive;\n\tstruct timing_entry hfront_porch;\n\tstruct timing_entry hback_porch;\n\tstruct timing_entry hsync_len;\n\tstruct timing_entry vactive;\n\tstruct timing_entry vfront_porch;\n\tstruct timing_entry vback_porch;\n\tstruct timing_entry vsync_len;\n\tenum display_flags flags;\n};\n\nstruct display_timings {\n\tunsigned int num_timings;\n\tunsigned int native_mode;\n\tstruct display_timing **timings;\n};\n\nstruct displayid_block {\n\tu8 tag;\n\tu8 rev;\n\tu8 num_bytes;\n};\n\nstruct displayid_detailed_timings_1 {\n\tu8 pixel_clock[3];\n\tu8 flags;\n\t__le16 hactive;\n\t__le16 hblank;\n\t__le16 hsync;\n\t__le16 hsw;\n\t__le16 vactive;\n\t__le16 vblank;\n\t__le16 vsync;\n\t__le16 vsw;\n};\n\nstruct displayid_detailed_timing_block {\n\tstruct displayid_block base;\n\tstruct displayid_detailed_timings_1 timings[0];\n} __attribute__((packed));\n\nstruct displayid_formula_timings_9 {\n\tu8 flags;\n\t__le16 hactive;\n\t__le16 vactive;\n\tu8 vrefresh;\n} __attribute__((packed));\n\nstruct displayid_formula_timing_block {\n\tstruct displayid_block base;\n\tstruct displayid_formula_timings_9 timings[0];\n};\n\nstruct displayid_header {\n\tu8 rev;\n\tu8 bytes;\n\tu8 prod_id;\n\tu8 ext_count;\n};\n\nstruct drm_edid_ident {\n\tu32 panel_id;\n\tconst char *name;\n};\n\nstruct displayid_quirk {\n\tconst struct drm_edid_ident ident;\n\tu8 quirks;\n};\n\nstruct displayid_tiled_block {\n\tstruct displayid_block base;\n\tu8 tile_cap;\n\tu8 topo[3];\n\tu8 tile_size[4];\n\tu8 tile_pixel_bezel[5];\n\tu8 topology_id[8];\n};\n\nstruct displayid_vesa_vendor_specific_block {\n\tstruct displayid_block base;\n\tu8 oui[3];\n\tu8 data_structure_type;\n\tu8 mso;\n};\n\nstruct div4_clk {\n\tconst char *name;\n\tconst char *parent;\n\tunsigned int reg;\n\tunsigned int shift;\n};\n\nstruct div4_clk___2 {\n\tconst char *name;\n\tunsigned int reg;\n\tunsigned int shift;\n};\n\nstruct div6_clock {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tunsigned int div;\n\tu32 src_mask;\n\tstruct notifier_block nb;\n\tu8 parents[0];\n};\n\nstruct div_cfg {\n\tu32 reg_off;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tconst struct clk_div_table *table;\n};\n\nstruct div_data {\n\tu8 shift;\n\tu8 pow;\n\tu8 width;\n\tconst struct clk_div_table *table;\n};\n\nstruct div_nmp {\n\tu8 divn_shift;\n\tu8 divn_width;\n\tu8 divm_shift;\n\tu8 divm_width;\n\tu8 divp_shift;\n\tu8 divp_width;\n\tu8 override_divn_shift;\n\tu8 override_divm_shift;\n\tu8 override_divp_shift;\n};\n\nstruct factors_data;\n\nstruct divs_data {\n\tconst struct factors_data *factors;\n\tint ndivs;\n\tstruct {\n\t\tu8 self;\n\t\tu8 fixed;\n\t\tstruct clk_div_table *table;\n\t\tu8 shift;\n\t\tu8 pow;\n\t\tu8 gate;\n\t\tbool critical;\n\t} div[4];\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tlong: 32;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tlong: 32;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tlong: 32;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_resv;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct dma_iova_state;\n\nstruct dma_buf_dma {\n\tstruct sg_table sgt;\n\tstruct dma_iova_state *state;\n\tsize_t size;\n};\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct dma_buf_export_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_import_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_buf_sg_table_wrapper {\n\tstruct sg_table *original;\n\tstruct sg_table wrapper;\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan *chan;\n\tlong: 32;\n\tstruct device device;\n\tint dev_id;\n\tbool chan_dma_dev;\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_chan_tbl_ent {\n\tstruct dma_chan *chan;\n};\n\nstruct dma_coherent_mem {\n\tvoid *virt_base;\n\tdma_addr_t device_base;\n\tlong unsigned int pfn_base;\n\tint size;\n\tlong unsigned int *bitmap;\n\tspinlock_t spinlock;\n\tbool use_dev_dma_pfn_offset;\n};\n\nstruct dma_contig_early_reserve {\n\tphys_addr_t base;\n\tlong unsigned int size;\n};\n\nstruct dma_desc {\n\t__le32 des0;\n\t__le32 des1;\n\t__le32 des2;\n\t__le32 des3;\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_edesc {\n\t__le32 des4;\n\t__le32 des5;\n\t__le32 des6;\n\t__le32 des7;\n\tstruct dma_desc basic;\n};\n\nstruct dma_extended_desc {\n\tstruct dma_desc basic;\n\t__le32 des4;\n\t__le32 des5;\n\t__le32 des6;\n\t__le32 des7;\n};\n\nstruct dma_features {\n\tunsigned int mbps_10_100;\n\tunsigned int mbps_1000;\n\tunsigned int half_duplex;\n\tunsigned int hash_filter;\n\tunsigned int multi_addr;\n\tunsigned int pcs;\n\tunsigned int sma_mdio;\n\tunsigned int pmt_remote_wake_up;\n\tunsigned int pmt_magic_frame;\n\tunsigned int rmon;\n\tunsigned int time_stamp;\n\tunsigned int atime_stamp;\n\tunsigned int eee;\n\tunsigned int av;\n\tunsigned int hash_tb_sz;\n\tunsigned int tsoen;\n\tunsigned int tx_coe;\n\tunsigned int rx_coe;\n\tunsigned int rx_coe_type1;\n\tunsigned int rx_coe_type2;\n\tunsigned int rxfifo_over_2048;\n\tunsigned int number_rx_channel;\n\tunsigned int number_tx_channel;\n\tunsigned int number_rx_queues;\n\tunsigned int number_tx_queues;\n\tunsigned int pps_out_num;\n\tunsigned int numtc;\n\tunsigned int dcben;\n\tunsigned int advthword;\n\tunsigned int ptoen;\n\tunsigned int osten;\n\tunsigned int pfcen;\n\tunsigned int enh_desc;\n\tunsigned int tx_fifo_size;\n\tunsigned int rx_fifo_size;\n\tunsigned int asp;\n\tunsigned int frpsel;\n\tunsigned int frpbs;\n\tunsigned int frpes;\n\tunsigned int addr64;\n\tunsigned int host_dma_width;\n\tunsigned int rssen;\n\tunsigned int vlhash;\n\tunsigned int sphen;\n\tunsigned int vlins;\n\tunsigned int dvlan;\n\tunsigned int l3l4fnum;\n\tunsigned int arpoffsel;\n\tunsigned int pou_ost_en;\n\tunsigned int ttsfd;\n\tunsigned int cbtisel;\n\tunsigned int frppipe_num;\n\tunsigned int nrvf_num;\n\tunsigned int estwid;\n\tunsigned int estdep;\n\tunsigned int estsel;\n\tunsigned int fpesel;\n\tunsigned int tbssel;\n\tunsigned int tbs_ch_num;\n\tunsigned int sgfsel;\n\tunsigned int aux_snapshot_n;\n\tunsigned int tssrc;\n\tunsigned int edma;\n\tunsigned int ediffc;\n\tunsigned int vxn;\n\tunsigned int dbgmem;\n\tunsigned int pcsel;\n\tu8 actphyif;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n\tlong: 32;\n};\n\nstruct dma_fence_array;\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n\tstruct dma_fence_array_cb callbacks[0];\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tstruct dma_fence *prev;\n\tlong: 32;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tunion {\n\t\tstruct dma_fence_cb cb;\n\t\tstruct irq_work work;\n\t};\n\tspinlock_t lock;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_fence_unwrap {\n\tstruct dma_fence *chain;\n\tstruct dma_fence *array;\n\tunsigned int index;\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nstruct iommu_domain;\n\nstruct dma_iommu_mapping {\n\tstruct iommu_domain *domain;\n\tlong unsigned int **bitmaps;\n\tunsigned int nr_bitmaps;\n\tunsigned int extensions;\n\tsize_t bitmap_size;\n\tsize_t bits;\n\tdma_addr_t base;\n\tspinlock_t lock;\n\tstruct kref kref;\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tlong: 32;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct pl330_dmac;\n\nstruct pl330_thread;\n\nstruct dma_pl330_chan {\n\tstruct tasklet_struct task;\n\tstruct dma_chan chan;\n\tstruct list_head submitted_list;\n\tstruct list_head work_list;\n\tstruct list_head completed_list;\n\tstruct pl330_dmac *dmac;\n\tspinlock_t lock;\n\tstruct pl330_thread *thread;\n\tint burst_sz;\n\tint burst_len;\n\tphys_addr_t fifo_addr;\n\tdma_addr_t fifo_dma;\n\tenum dma_data_direction dir;\n\tstruct dma_slave_config slave_config;\n\tbool cyclic;\n\tbool active;\n};\n\nstruct pl330_xfer {\n\tu32 src_addr;\n\tu32 dst_addr;\n\tu32 bytes;\n};\n\nstruct pl330_config;\n\nstruct pl330_reqcfg {\n\tunsigned int dst_inc: 1;\n\tunsigned int src_inc: 1;\n\tbool nonsecure;\n\tbool privileged;\n\tbool insnaccess;\n\tunsigned int brst_len: 5;\n\tunsigned int brst_size: 3;\n\tenum pl330_cachectrl dcctl;\n\tenum pl330_cachectrl scctl;\n\tenum pl330_byteswap swap;\n\tstruct pl330_config *pcfg;\n};\n\nstruct dma_pl330_desc {\n\tstruct list_head node;\n\tstruct dma_async_tx_descriptor txd;\n\tstruct pl330_xfer px;\n\tstruct pl330_reqcfg rqcfg;\n\tenum desc_status status;\n\tint bytes_requested;\n\tbool last;\n\tstruct dma_pl330_chan *pchan;\n\tenum dma_transfer_direction rqtype;\n\tunsigned int peri: 5;\n\tstruct list_head rqd;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct ww_acquire_ctx;\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tstruct dma_resv_list *fences;\n};\n\nstruct dma_resv_iter {\n\tstruct dma_resv *obj;\n\tenum dma_resv_usage usage;\n\tstruct dma_fence *fence;\n\tenum dma_resv_usage fence_usage;\n\tunsigned int index;\n\tstruct dma_resv_list *fences;\n\tunsigned int num_fences;\n\tbool is_restarted;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 num_fences;\n\tu32 max_fences;\n\tstruct dma_fence *table[0];\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_vec {\n\tdma_addr_t addr;\n\tsize_t len;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct net_devmem_dmabuf_binding;\n\nstruct dmabuf_genpool_chunk_owner {\n\tstruct net_iov_area area;\n\tstruct net_devmem_dmabuf_binding *binding;\n\tdma_addr_t base_dma_addr;\n};\n\nstruct dmabuf_iter_priv {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmaengine_desc_callback {\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n};\n\nstruct dmaengine_unmap_data {\n\tu16 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dmaengine_unmap_pool {\n\tstruct kmem_cache *cache;\n\tconst char *name;\n\tmempool_t *pool;\n\tsize_t size;\n};\n\nstruct dmi_device {\n\tstruct list_head list;\n\tint type;\n\tconst char *name;\n\tvoid *device_data;\n};\n\nstruct dmi_dev_onboard {\n\tstruct dmi_device dev;\n\tint instance;\n\tint segment;\n\tint bus;\n\tint devfn;\n};\n\nstruct dmi_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint field;\n};\n\nstruct dmi_header {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n};\n\nstruct dmi_memdev_info {\n\tconst char *device;\n\tconst char *bank;\n\tu64 size;\n\tu16 handle;\n\tu8 type;\n\tlong: 32;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct fb_videomode;\n\nstruct dmt_videomode {\n\tu32 dmt_id;\n\tu32 std_2byte_code;\n\tu32 cvt_3byte_code;\n\tconst struct fb_videomode *mode;\n};\n\nstruct omap_dm_timer {};\n\nstruct timer_regs {\n\tu32 ocp_cfg;\n\tu32 tidr;\n\tu32 tier;\n\tu32 twer;\n\tu32 tclr;\n\tu32 tcrr;\n\tu32 tldr;\n\tu32 ttrg;\n\tu32 twps;\n\tu32 tmar;\n\tu32 tcar1;\n\tu32 tsicr;\n\tu32 tcar2;\n\tu32 tpir;\n\tu32 tnir;\n\tu32 tcvr;\n\tu32 tocr;\n\tu32 towr;\n};\n\nstruct dmtimer {\n\tstruct omap_dm_timer cookie;\n\tint id;\n\tint irq;\n\tstruct clk *fclk;\n\tvoid *io_base;\n\tint irq_stat;\n\tint irq_ena;\n\tint irq_dis;\n\tvoid *pend;\n\tvoid *func_base;\n\tatomic_t enabled;\n\tunsigned int reserved: 1;\n\tunsigned int posted: 1;\n\tunsigned int omap1: 1;\n\tstruct timer_regs context;\n\tint revision;\n\tu32 capability;\n\tu32 errata;\n\tstruct platform_device *pdev;\n\tstruct list_head node;\n\tstruct notifier_block nb;\n\tstruct notifier_block fclk_nb;\n\tlong unsigned int fclk_rate;\n};\n\nstruct dmtimer_systimer {\n\tvoid *base;\n\tu8 sysc;\n\tu8 irq_stat;\n\tu8 irq_ena;\n\tu8 pend;\n\tu8 load;\n\tu8 counter;\n\tu8 ctrl;\n\tu8 wakeup;\n\tu8 ifctrl;\n\tstruct clk *fck;\n\tstruct clk *ick;\n\tlong unsigned int rate;\n};\n\nstruct dmtimer_clockevent {\n\tstruct clock_event_device dev;\n\tstruct dmtimer_systimer t;\n\tu32 period;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct dmtimer_clocksource {\n\tstruct clocksource dev;\n\tstruct dmtimer_systimer t;\n\tunsigned int loadval;\n};\n\nstruct omap_dm_timer_ops;\n\nstruct dmtimer_platform_data {\n\tint (*set_timer_src)(struct platform_device *, int);\n\tu32 timer_capability;\n\tu32 timer_errata;\n\tint (*get_context_loss_count)(struct device *);\n\tconst struct omap_dm_timer_ops *timer_ops;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct done_ref {\n\tstruct rb_node rb;\n\tint lnum;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct dove_clk {\n\tconst char *name;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tspinlock_t *lock;\n\tu8 div_bit_start;\n\tu8 div_bit_end;\n\tu8 div_bit_load;\n\tu8 div_bit_size;\n\tu32 *divider_table;\n};\n\nstruct dove_pmu_domain_initdata {\n\tu32 pwr_mask;\n\tu32 rst_mask;\n\tu32 iso_mask;\n\tconst char *name;\n};\n\nstruct dove_pmu_initdata {\n\tvoid *pmc_base;\n\tvoid *pmu_base;\n\tint irq;\n\tint irq_domain_start;\n\tconst struct dove_pmu_domain_initdata *domains;\n};\n\nstruct dp83867_private {\n\tu32 rx_id_delay;\n\tu32 tx_id_delay;\n\tu32 tx_fifo_depth;\n\tu32 rx_fifo_depth;\n\tint io_impedance;\n\tint port_mirroring;\n\tbool rxctrl_strap_quirk;\n\tbool set_clk_output;\n\tu32 clk_output_sel;\n\tbool sgmii_ref_clk_en;\n};\n\nstruct drm_edp_backlight_info {\n\tu8 pwmgen_bit_count;\n\tu8 pwm_freq_pre_divider;\n\tu32 max;\n\tbool lsb_reg_used: 1;\n\tbool aux_enable: 1;\n\tbool aux_set: 1;\n\tbool luminance_set: 1;\n};\n\nstruct drm_dp_aux;\n\nstruct dp_aux_backlight {\n\tstruct backlight_device *base;\n\tstruct drm_dp_aux *aux;\n\tstruct drm_edp_backlight_info info;\n\tbool enabled;\n};\n\nstruct dp_aux_ep_device {\n\tstruct device dev;\n\tstruct drm_dp_aux *aux;\n\tlong: 32;\n};\n\nstruct dp_aux_ep_device_with_data {\n\tstruct dp_aux_ep_device aux_ep;\n\tint (*done_probing)(struct drm_dp_aux *);\n\tlong: 32;\n};\n\nstruct dp_aux_ep_driver {\n\tint (*probe)(struct dp_aux_ep_device *);\n\tvoid (*remove)(struct dp_aux_ep_device *);\n\tvoid (*shutdown)(struct dp_aux_ep_device *);\n\tstruct device_driver driver;\n};\n\nstruct dp_sdp_header {\n\tu8 HB0;\n\tu8 HB1;\n\tu8 HB2;\n\tu8 HB3;\n};\n\nstruct dp_sdp {\n\tstruct dp_sdp_header sdp_header;\n\tu8 db[32];\n};\n\nstruct dpcd_quirk {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tbool is_branch;\n\tu32 quirks;\n};\n\nstruct dpfe_api {\n\tint version;\n\tconst char *fw_name;\n\tconst struct attribute_group **sysfs_attrs;\n\tu32 command[48];\n};\n\nstruct dpfe_firmware_header {\n\tu32 magic;\n\tu32 sequence;\n\tu32 version;\n\tu32 imem_size;\n\tu32 dmem_size;\n};\n\nstruct dpll_data {\n\tstruct clk_omap_reg mult_div1_reg;\n\tu32 mult_mask;\n\tu32 div1_mask;\n\tstruct clk_hw *clk_bypass;\n\tstruct clk_hw *clk_ref;\n\tstruct clk_omap_reg control_reg;\n\tu32 enable_mask;\n\tlong unsigned int last_rounded_rate;\n\tu16 last_rounded_m;\n\tu8 last_rounded_m4xen;\n\tu8 last_rounded_lpmode;\n\tu16 max_multiplier;\n\tu8 last_rounded_n;\n\tu8 min_divider;\n\tu16 max_divider;\n\tlong unsigned int max_rate;\n\tu8 modes;\n\tstruct clk_omap_reg autoidle_reg;\n\tstruct clk_omap_reg idlest_reg;\n\tu32 autoidle_mask;\n\tu32 freqsel_mask;\n\tu32 idlest_mask;\n\tu32 dco_mask;\n\tu32 sddiv_mask;\n\tu32 dcc_mask;\n\tlong unsigned int dcc_rate;\n\tu32 lpmode_mask;\n\tu32 m4xen_mask;\n\tu8 auto_recal_bit;\n\tu8 recal_en_bit;\n\tu8 recal_st_bit;\n\tstruct clk_omap_reg ssc_deltam_reg;\n\tstruct clk_omap_reg ssc_modfreq_reg;\n\tu32 ssc_deltam_int_mask;\n\tu32 ssc_deltam_frac_mask;\n\tu32 ssc_modfreq_mant_mask;\n\tu32 ssc_modfreq_exp_mask;\n\tu32 ssc_enable_mask;\n\tu32 ssc_downspread_mask;\n\tu32 ssc_modfreq;\n\tu32 ssc_deltam;\n\tbool ssc_downspread;\n\tu8 flags;\n};\n\nstruct dpot_data {\n\tstruct ad_dpot_bus_data bdata;\n\tstruct mutex update_lock;\n\tunsigned int rdac_mask;\n\tunsigned int max_pos;\n\tlong unsigned int devid;\n\tunsigned int uid;\n\tunsigned int feat;\n\tunsigned int wipers;\n\tu16 rdac_cache[6];\n\tlong unsigned int otp_en_mask[1];\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tlong: 32;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct dra7_atl_desc;\n\nstruct dra7_atl_clock_info {\n\tstruct device *dev;\n\tvoid *iobase;\n\tstruct dra7_atl_desc *cdesc;\n};\n\nstruct dra7_atl_desc {\n\tstruct clk *clk;\n\tstruct clk_hw hw;\n\tstruct dra7_atl_clock_info *cinfo;\n\tint id;\n\tbool probed;\n\tbool valid;\n\tbool enabled;\n\tu32 bws;\n\tu32 aws;\n\tu32 divider;\n};\n\nstruct dw_pcie;\n\nstruct dra7xx_pcie {\n\tstruct dw_pcie *pci;\n\tvoid *base;\n\tint phy_count;\n\tstruct phy **phy;\n\tstruct irq_domain *irq_domain;\n\tstruct clk *clk;\n\tenum dw_pcie_device_mode mode;\n};\n\nstruct dra7xx_pcie_of_data {\n\tenum dw_pcie_device_mode mode;\n\tu32 b1co_mode_sel_mask;\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct driver_info {\n\tchar *description;\n\tint flags;\n\tint (*bind)(struct usbnet *, struct usb_interface *);\n\tvoid (*unbind)(struct usbnet *, struct usb_interface *);\n\tint (*reset)(struct usbnet *);\n\tint (*stop)(struct usbnet *);\n\tint (*check_connect)(struct usbnet *);\n\tint (*manage_power)(struct usbnet *, int);\n\tvoid (*status)(struct usbnet *, struct urb *);\n\tint (*link_reset)(struct usbnet *);\n\tint (*rx_fixup)(struct usbnet *, struct sk_buff *);\n\tstruct sk_buff * (*tx_fixup)(struct usbnet *, struct sk_buff *, gfp_t);\n\tvoid (*recover)(struct usbnet *);\n\tint (*early_init)(struct usbnet *);\n\tvoid (*indication)(struct usbnet *, void *, int);\n\tvoid (*set_rx_mode)(struct usbnet *);\n\tint in;\n\tint out;\n\tlong unsigned int data;\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drm_object_properties;\n\nstruct drm_mode_object {\n\tuint32_t id;\n\tuint32_t type;\n\tstruct drm_object_properties *properties;\n\tstruct kref refcount;\n\tvoid (*free_cb)(struct kref *);\n};\n\nstruct drm_device;\n\nstruct drm_format_info;\n\nstruct drm_framebuffer_funcs;\n\nstruct drm_gem_object;\n\nstruct drm_framebuffer {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar comm[16];\n\tconst struct drm_format_info *format;\n\tconst struct drm_framebuffer_funcs *funcs;\n\tunsigned int pitches[4];\n\tunsigned int offsets[4];\n\tuint64_t modifier;\n\tunsigned int width;\n\tunsigned int height;\n\tint flags;\n\tunsigned int internal_flags;\n\tstruct list_head filp_head;\n\tstruct drm_gem_object *obj[4];\n};\n\nstruct drm_afbc_framebuffer {\n\tstruct drm_framebuffer base;\n\tu32 block_width;\n\tu32 block_height;\n\tu32 aligned_width;\n\tu32 aligned_height;\n\tu32 offset;\n\tu32 afbc_size;\n};\n\nstruct drm_rect {\n\tint x1;\n\tint y1;\n\tint x2;\n\tint y2;\n};\n\nstruct drm_atomic_helper_damage_iter {\n\tstruct drm_rect plane_src;\n\tconst struct drm_rect *clips;\n\tuint32_t num_clips;\n\tuint32_t curr_clip;\n\tbool full_update;\n};\n\nstruct drm_modeset_acquire_ctx;\n\nstruct drm_atomic_state {\n\tstruct kref ref;\n\tstruct drm_device *dev;\n\tbool allow_modeset: 1;\n\tbool legacy_cursor_update: 1;\n\tbool async_update: 1;\n\tbool duplicated: 1;\n\tbool checked: 1;\n\tbool plane_color_pipeline: 1;\n\tstruct __drm_colorops_state *colorops;\n\tstruct __drm_planes_state *planes;\n\tstruct __drm_crtcs_state *crtcs;\n\tint num_connector;\n\tstruct __drm_connnectors_state *connectors;\n\tint num_private_objs;\n\tstruct __drm_private_objs_state *private_objs;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct drm_crtc_commit *fake_commit;\n\tstruct work_struct commit_work;\n};\n\nstruct drm_auth {\n\tdrm_magic_t magic;\n};\n\nstruct drm_modeset_lock {\n\tstruct ww_mutex mutex;\n\tstruct list_head head;\n};\n\nstruct drm_private_state_funcs;\n\nstruct drm_private_obj {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_modeset_lock lock;\n\tstruct drm_private_state *state;\n\tconst struct drm_private_state_funcs *funcs;\n};\n\nstruct drm_encoder;\n\nstruct drm_bridge_timings;\n\nstruct drm_bridge_funcs;\n\nstruct drm_bridge {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tstruct drm_encoder *encoder;\n\tstruct list_head chain_node;\n\tstruct device_node *of_node;\n\tstruct list_head list;\n\tconst struct drm_bridge_timings *timings;\n\tconst struct drm_bridge_funcs *funcs;\n\tvoid *container;\n\tstruct kref refcount;\n\tbool unplugged;\n\tvoid *driver_private;\n\tenum drm_bridge_ops ops;\n\tint type;\n\tbool interlace_allowed;\n\tbool ycbcr_420_allowed;\n\tbool pre_enable_prev_first;\n\tbool support_hdcp;\n\tstruct i2c_adapter *ddc;\n\tconst char *vendor;\n\tconst char *product;\n\tunsigned int supported_formats;\n\tunsigned int max_bpc;\n\tstruct device *hdmi_cec_dev;\n\tstruct device *hdmi_audio_dev;\n\tint hdmi_audio_max_i2s_playback_channels;\n\tlong: 32;\n\tu64 hdmi_audio_i2s_formats;\n\tunsigned int hdmi_audio_spdif_playback: 1;\n\tint hdmi_audio_dai_port;\n\tconst char *hdmi_cec_adapter_name;\n\tu8 hdmi_cec_available_las;\n\tstruct mutex hpd_mutex;\n\tvoid (*hpd_cb)(void *, enum drm_connector_status);\n\tvoid *hpd_data;\n\tstruct drm_bridge *next_bridge;\n};\n\nstruct drm_scrambling {\n\tbool supported;\n\tbool low_rates;\n};\n\nstruct drm_scdc {\n\tbool supported;\n\tbool read_request;\n\tstruct drm_scrambling scrambling;\n};\n\nstruct drm_hdmi_dsc_cap {\n\tbool v_1p2;\n\tbool native_420;\n\tbool all_bpp;\n\tu8 bpc_supported;\n\tu8 max_slices;\n\tint clk_per_slice;\n\tu8 max_lanes;\n\tu8 max_frl_rate_per_lane;\n\tu8 total_chunk_kbytes;\n};\n\nstruct drm_hdmi_info {\n\tstruct drm_scdc scdc;\n\tlong unsigned int y420_vdb_modes[8];\n\tlong unsigned int y420_cmdb_modes[8];\n\tu8 y420_dc_modes;\n\tu8 max_frl_rate_per_lane;\n\tu8 max_lanes;\n\tstruct drm_hdmi_dsc_cap dsc_cap;\n};\n\nstruct hdr_static_metadata {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\t__u16 max_cll;\n\t__u16 max_fall;\n\t__u16 min_cll;\n};\n\nstruct hdr_sink_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_static_metadata hdmi_type1;\n\t};\n};\n\nstruct drm_monitor_range_info {\n\tu16 min_vfreq;\n\tu16 max_vfreq;\n};\n\nstruct drm_luminance_range_info {\n\tu32 min_luminance;\n\tu32 max_luminance;\n};\n\nstruct drm_display_info {\n\tunsigned int width_mm;\n\tunsigned int height_mm;\n\tunsigned int bpc;\n\tenum subpixel_order subpixel_order;\n\tint panel_orientation;\n\tu32 color_formats;\n\tconst u32 *bus_formats;\n\tunsigned int num_bus_formats;\n\tu32 bus_flags;\n\tint max_tmds_clock;\n\tbool dvi_dual;\n\tbool is_hdmi;\n\tbool has_audio;\n\tbool has_hdmi_infoframe;\n\tbool rgb_quant_range_selectable;\n\tu8 edid_hdmi_rgb444_dc_modes;\n\tu8 edid_hdmi_ycbcr444_dc_modes;\n\tu8 cea_rev;\n\tstruct drm_hdmi_info hdmi;\n\tstruct hdr_sink_metadata hdr_sink_metadata;\n\tbool non_desktop;\n\tstruct drm_monitor_range_info monitor_range;\n\tstruct drm_luminance_range_info luminance_range;\n\tu8 mso_stream_count;\n\tu8 mso_pixel_overlap;\n\tu32 max_dsc_bpp;\n\tu8 *vics;\n\tint vics_len;\n\tu32 quirks;\n\tu16 source_physical_address;\n};\n\nstruct drm_property;\n\nstruct drm_object_properties {\n\tint count;\n\tstruct drm_property *properties[64];\n\tlong: 32;\n\tuint64_t values[64];\n};\n\nstruct drm_privacy_screen;\n\nstruct drm_connector_tv_margins {\n\tunsigned int bottom;\n\tunsigned int left;\n\tunsigned int right;\n\tunsigned int top;\n};\n\nstruct drm_cmdline_mode {\n\tchar name[32];\n\tbool specified;\n\tbool refresh_specified;\n\tbool bpp_specified;\n\tunsigned int pixel_clock;\n\tint xres;\n\tint yres;\n\tint bpp;\n\tint refresh;\n\tbool rb;\n\tbool interlace;\n\tbool cvt;\n\tbool margins;\n\tenum drm_connector_force force;\n\tunsigned int rotation_reflection;\n\tenum drm_panel_orientation panel_orientation;\n\tstruct drm_connector_tv_margins tv_margins;\n\tenum drm_connector_tv_mode tv_mode;\n\tbool tv_mode_specified;\n};\n\nstruct hdmi_any_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n};\n\nstruct hdmi_avi_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tbool itc;\n\tunsigned char pixel_repeat;\n\tenum hdmi_colorspace colorspace;\n\tenum hdmi_scan_mode scan_mode;\n\tenum hdmi_colorimetry colorimetry;\n\tenum hdmi_picture_aspect picture_aspect;\n\tenum hdmi_active_aspect active_aspect;\n\tenum hdmi_extended_colorimetry extended_colorimetry;\n\tenum hdmi_quantization_range quantization_range;\n\tenum hdmi_nups nups;\n\tunsigned char video_code;\n\tenum hdmi_ycc_quantization_range ycc_quantization_range;\n\tenum hdmi_content_type content_type;\n\tshort unsigned int top_bar;\n\tshort unsigned int bottom_bar;\n\tshort unsigned int left_bar;\n\tshort unsigned int right_bar;\n};\n\nstruct hdmi_spd_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tchar vendor[8];\n\tchar product[16];\n\tenum hdmi_spd_sdi sdi;\n};\n\nstruct hdmi_vendor_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned int oui;\n\tu8 vic;\n\tenum hdmi_3d_structure s3d_struct;\n\tunsigned int s3d_ext_data;\n};\n\nunion hdmi_vendor_any_infoframe {\n\tstruct {\n\t\tenum hdmi_infoframe_type type;\n\t\tunsigned char version;\n\t\tunsigned char length;\n\t\tunsigned int oui;\n\t} any;\n\tstruct hdmi_vendor_infoframe hdmi;\n};\n\nstruct hdmi_audio_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned char channels;\n\tenum hdmi_audio_coding_type coding_type;\n\tenum hdmi_audio_sample_size sample_size;\n\tenum hdmi_audio_sample_frequency sample_frequency;\n\tenum hdmi_audio_coding_type_ext coding_type_ext;\n\tunsigned char channel_allocation;\n\tunsigned char level_shift_value;\n\tbool downmix_inhibit;\n};\n\nstruct hdmi_drm_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_eotf eotf;\n\tenum hdmi_metadata_type metadata_type;\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} white_point;\n\tu16 max_display_mastering_luminance;\n\tu16 min_display_mastering_luminance;\n\tu16 max_cll;\n\tu16 max_fall;\n};\n\nunion hdmi_infoframe {\n\tstruct hdmi_any_infoframe any;\n\tstruct hdmi_avi_infoframe avi;\n\tstruct hdmi_spd_infoframe spd;\n\tunion hdmi_vendor_any_infoframe vendor;\n\tstruct hdmi_audio_infoframe audio;\n\tstruct hdmi_drm_infoframe drm;\n};\n\nstruct drm_connector_hdmi_infoframe {\n\tunion hdmi_infoframe data;\n\tbool set;\n};\n\nstruct drm_connector_hdmi_funcs;\n\nstruct drm_connector_hdmi {\n\tunsigned char vendor[8];\n\tunsigned char product[16];\n\tlong unsigned int supported_formats;\n\tconst struct drm_connector_hdmi_funcs *funcs;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct drm_connector_hdmi_infoframe audio;\n\t} infoframes;\n};\n\nstruct drm_connector_hdmi_audio_funcs;\n\nstruct drm_connector_hdmi_audio {\n\tconst struct drm_connector_hdmi_audio_funcs *funcs;\n\tstruct platform_device *codec_pdev;\n\tstruct mutex lock;\n\tvoid (*plugged_cb)(struct device *, bool);\n\tstruct device *plugged_cb_dev;\n\tbool last_state;\n\tint dai_port;\n};\n\nstruct drm_connector_cec_funcs;\n\nstruct drm_connector_cec {\n\tstruct mutex mutex;\n\tconst struct drm_connector_cec_funcs *funcs;\n\tvoid *data;\n};\n\nstruct drm_connector_funcs;\n\nstruct drm_property_blob;\n\nstruct drm_connector_helper_funcs;\n\nstruct drm_tile_group;\n\nstruct drm_connector {\n\tstruct drm_device *dev;\n\tstruct device *kdev;\n\tstruct device_attribute *attr;\n\tstruct fwnode_handle *fwnode;\n\tstruct list_head head;\n\tstruct list_head global_connector_list_entry;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tstruct mutex mutex;\n\tunsigned int index;\n\tint connector_type;\n\tint connector_type_id;\n\tbool interlace_allowed;\n\tbool doublescan_allowed;\n\tbool stereo_allowed;\n\tbool ycbcr_420_allowed;\n\tenum drm_connector_registration_state registration_state;\n\tstruct list_head modes;\n\tenum drm_connector_status status;\n\tstruct list_head probed_modes;\n\tstruct drm_display_info display_info;\n\tconst struct drm_connector_funcs *funcs;\n\tstruct drm_property_blob *edid_blob_ptr;\n\tstruct drm_object_properties properties;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *vrr_capable_property;\n\tstruct drm_property *colorspace_property;\n\tstruct drm_property_blob *path_blob_ptr;\n\tunsigned int max_bpc;\n\tstruct drm_property *max_bpc_property;\n\tstruct drm_privacy_screen *privacy_screen;\n\tstruct notifier_block privacy_screen_notifier;\n\tstruct drm_property *privacy_screen_sw_state_property;\n\tstruct drm_property *privacy_screen_hw_state_property;\n\tstruct drm_property *broadcast_rgb_property;\n\tuint8_t polled;\n\tint dpms;\n\tconst struct drm_connector_helper_funcs *helper_private;\n\tstruct drm_cmdline_mode cmdline_mode;\n\tenum drm_connector_force force;\n\tconst struct drm_edid *edid_override;\n\tstruct mutex edid_override_mutex;\n\tlong: 32;\n\tu64 epoch_counter;\n\tu32 possible_encoders;\n\tstruct drm_encoder *encoder;\n\tuint8_t eld[128];\n\tstruct mutex eld_mutex;\n\tbool latency_present[2];\n\tint video_latency[2];\n\tint audio_latency[2];\n\tstruct i2c_adapter *ddc;\n\tint null_edid_counter;\n\tunsigned int bad_edid_counter;\n\tbool edid_corrupt;\n\tu8 real_edid_checksum;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_connector_state *state;\n\tstruct drm_property_blob *tile_blob_ptr;\n\tbool has_tile;\n\tstruct drm_tile_group *tile_group;\n\tbool tile_is_single_monitor;\n\tuint8_t num_h_tile;\n\tuint8_t num_v_tile;\n\tuint8_t tile_h_loc;\n\tuint8_t tile_v_loc;\n\tuint16_t tile_h_size;\n\tuint16_t tile_v_size;\n\tstruct llist_node free_node;\n\tstruct drm_connector_hdmi hdmi;\n\tstruct drm_connector_hdmi_audio hdmi_audio;\n\tstruct drm_connector_cec cec;\n};\n\nstruct drm_connector_infoframe_funcs {\n\tint (*clear_infoframe)(struct drm_connector *);\n\tint (*write_infoframe)(struct drm_connector *, const u8 *, size_t);\n};\n\nstruct drm_display_mode;\n\nstruct drm_connector_hdmi_funcs {\n\tenum drm_mode_status (*tmds_char_rate_valid)(const struct drm_connector *, const struct drm_display_mode *, long long unsigned int);\n\tconst struct drm_edid * (*read_edid)(struct drm_connector *);\n\tstruct drm_connector_infoframe_funcs avi;\n\tstruct drm_connector_infoframe_funcs hdmi;\n\tstruct drm_connector_infoframe_funcs audio;\n\tstruct drm_connector_infoframe_funcs hdr_drm;\n\tstruct drm_connector_infoframe_funcs spd;\n};\n\nstruct drm_bridge_connector {\n\tstruct drm_connector base;\n\tstruct drm_encoder *encoder;\n\tstruct drm_bridge *bridge_edid;\n\tstruct drm_bridge *bridge_hpd;\n\tstruct drm_bridge *bridge_detect;\n\tstruct drm_bridge *bridge_modes;\n\tstruct drm_bridge *bridge_hdmi;\n\tstruct drm_bridge *bridge_hdmi_audio;\n\tstruct drm_bridge *bridge_dp_audio;\n\tstruct drm_bridge *bridge_hdmi_cec;\n\tstruct drm_connector_hdmi_funcs hdmi_funcs;\n\tlong: 32;\n};\n\nstruct drm_bridge_state;\n\nstruct hdmi_codec_daifmt;\n\nstruct hdmi_codec_params;\n\nstruct drm_bridge_funcs {\n\tint (*attach)(struct drm_bridge *, struct drm_encoder *, enum drm_bridge_attach_flags);\n\tvoid (*destroy)(struct drm_bridge *);\n\tvoid (*detach)(struct drm_bridge *);\n\tenum drm_mode_status (*mode_valid)(struct drm_bridge *, const struct drm_display_info *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_bridge *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*disable)(struct drm_bridge *);\n\tvoid (*post_disable)(struct drm_bridge *);\n\tvoid (*mode_set)(struct drm_bridge *, const struct drm_display_mode *, const struct drm_display_mode *);\n\tvoid (*pre_enable)(struct drm_bridge *);\n\tvoid (*enable)(struct drm_bridge *);\n\tvoid (*atomic_pre_enable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_post_disable)(struct drm_bridge *, struct drm_atomic_state *);\n\tstruct drm_bridge_state * (*atomic_duplicate_state)(struct drm_bridge *);\n\tvoid (*atomic_destroy_state)(struct drm_bridge *, struct drm_bridge_state *);\n\tu32 * (*atomic_get_output_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, unsigned int *);\n\tu32 * (*atomic_get_input_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, u32, unsigned int *);\n\tint (*atomic_check)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *);\n\tstruct drm_bridge_state * (*atomic_reset)(struct drm_bridge *);\n\tenum drm_connector_status (*detect)(struct drm_bridge *, struct drm_connector *);\n\tint (*get_modes)(struct drm_bridge *, struct drm_connector *);\n\tconst struct drm_edid * (*edid_read)(struct drm_bridge *, struct drm_connector *);\n\tvoid (*hpd_notify)(struct drm_bridge *, struct drm_connector *, enum drm_connector_status);\n\tvoid (*hpd_enable)(struct drm_bridge *);\n\tvoid (*hpd_disable)(struct drm_bridge *);\n\tenum drm_mode_status (*hdmi_tmds_char_rate_valid)(const struct drm_bridge *, const struct drm_display_mode *, long long unsigned int);\n\tint (*hdmi_clear_avi_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_avi_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_hdmi_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_hdmi_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_hdr_drm_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_hdr_drm_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_spd_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_spd_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_audio_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_audio_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_audio_startup)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_audio_prepare)(struct drm_bridge *, struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*hdmi_audio_shutdown)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_audio_mute_stream)(struct drm_bridge *, struct drm_connector *, bool, int);\n\tint (*hdmi_cec_init)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_cec_enable)(struct drm_bridge *, bool);\n\tint (*hdmi_cec_log_addr)(struct drm_bridge *, u8);\n\tint (*hdmi_cec_transmit)(struct drm_bridge *, u8, u32, struct cec_msg *);\n\tint (*dp_audio_startup)(struct drm_bridge *, struct drm_connector *);\n\tint (*dp_audio_prepare)(struct drm_bridge *, struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*dp_audio_shutdown)(struct drm_bridge *, struct drm_connector *);\n\tint (*dp_audio_mute_stream)(struct drm_bridge *, struct drm_connector *, bool, int);\n\tvoid (*debugfs_init)(struct drm_bridge *, struct dentry *);\n};\n\nstruct drm_private_state {\n\tstruct drm_atomic_state *state;\n\tstruct drm_private_obj *obj;\n};\n\nstruct drm_bus_cfg {\n\tu32 format;\n\tu32 flags;\n};\n\nstruct drm_bridge_state {\n\tstruct drm_private_state base;\n\tstruct drm_bridge *bridge;\n\tstruct drm_bus_cfg input_bus_cfg;\n\tstruct drm_bus_cfg output_bus_cfg;\n};\n\nstruct drm_bridge_timings {\n\tu32 input_bus_flags;\n\tu32 setup_time_ps;\n\tu32 hold_time_ps;\n\tbool dual_link;\n};\n\nstruct drm_client {\n\tint idx;\n\tint auth;\n\tlong unsigned int pid;\n\tlong unsigned int uid;\n\tlong unsigned int magic;\n\tlong unsigned int iocs;\n};\n\nstruct drm_client_dev;\n\nstruct drm_client_buffer {\n\tstruct drm_client_dev *client;\n\tstruct drm_gem_object *gem;\n\tstruct iosys_map map;\n\tstruct drm_framebuffer *fb;\n};\n\nstruct drm_client_funcs;\n\nstruct drm_file;\n\nstruct drm_mode_set;\n\nstruct drm_client_dev {\n\tstruct drm_device *dev;\n\tconst char *name;\n\tstruct list_head list;\n\tconst struct drm_client_funcs *funcs;\n\tstruct drm_file *file;\n\tstruct mutex modeset_mutex;\n\tstruct drm_mode_set *modesets;\n\tbool suspended;\n\tbool hotplug_pending;\n\tbool hotplug_failed;\n};\n\nstruct drm_client_funcs {\n\tstruct module *owner;\n\tvoid (*free)(struct drm_client_dev *);\n\tvoid (*unregister)(struct drm_client_dev *);\n\tint (*restore)(struct drm_client_dev *, bool);\n\tint (*hotplug)(struct drm_client_dev *);\n\tint (*suspend)(struct drm_client_dev *);\n\tint (*resume)(struct drm_client_dev *);\n};\n\nstruct drm_client_offset {\n\tint x;\n\tint y;\n};\n\nstruct drm_clip_rect {\n\tshort unsigned int x1;\n\tshort unsigned int y1;\n\tshort unsigned int x2;\n\tshort unsigned int y2;\n};\n\nstruct drm_color_lut {\n\t__u16 red;\n\t__u16 green;\n\t__u16 blue;\n\t__u16 reserved;\n};\n\nstruct drm_color_lut32 {\n\t__u32 red;\n\t__u32 green;\n\t__u32 blue;\n\t__u32 reserved;\n};\n\nstruct drm_colorop {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tunsigned int index;\n\tstruct drm_mode_object base;\n\tstruct drm_plane *plane;\n\tstruct drm_colorop_state *state;\n\tlong: 32;\n\tstruct drm_object_properties properties;\n\tenum drm_colorop_type type;\n\tstruct drm_colorop *next;\n\tstruct drm_property *type_property;\n\tstruct drm_property *bypass_property;\n\tuint32_t size;\n\tenum drm_colorop_lut1d_interpolation_type lut1d_interpolation;\n\tenum drm_colorop_lut3d_interpolation_type lut3d_interpolation;\n\tstruct drm_property *lut1d_interpolation_property;\n\tstruct drm_property *curve_1d_type_property;\n\tstruct drm_property *multiplier_property;\n\tstruct drm_property *size_property;\n\tstruct drm_property *lut3d_interpolation_property;\n\tstruct drm_property *data_property;\n\tstruct drm_property *next_property;\n};\n\nstruct drm_colorop_state {\n\tstruct drm_colorop *colorop;\n\tbool bypass;\n\tenum drm_colorop_curve_1d_type curve_1d_type;\n\tlong: 32;\n\tuint64_t multiplier;\n\tstruct drm_property_blob *data;\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_conn_prop_enum_list {\n\tint type;\n\tconst char *name;\n\tstruct ida ida;\n};\n\nstruct drm_connector_cec_funcs {\n\tvoid (*phys_addr_invalidate)(struct drm_connector *);\n\tvoid (*phys_addr_set)(struct drm_connector *, u16);\n};\n\nstruct drm_printer;\n\nstruct drm_connector_funcs {\n\tint (*dpms)(struct drm_connector *, int);\n\tvoid (*reset)(struct drm_connector *);\n\tenum drm_connector_status (*detect)(struct drm_connector *, bool);\n\tvoid (*force)(struct drm_connector *);\n\tint (*fill_modes)(struct drm_connector *, uint32_t, uint32_t);\n\tint (*set_property)(struct drm_connector *, struct drm_property *, uint64_t);\n\tint (*late_register)(struct drm_connector *);\n\tvoid (*early_unregister)(struct drm_connector *);\n\tvoid (*destroy)(struct drm_connector *);\n\tstruct drm_connector_state * (*atomic_duplicate_state)(struct drm_connector *);\n\tvoid (*atomic_destroy_state)(struct drm_connector *, struct drm_connector_state *);\n\tint (*atomic_set_property)(struct drm_connector *, struct drm_connector_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_connector *, const struct drm_connector_state *, struct drm_property *, uint64_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_connector_state *);\n\tvoid (*oob_hotplug_event)(struct drm_connector *, enum drm_connector_status);\n\tvoid (*debugfs_init)(struct drm_connector *, struct dentry *);\n};\n\nstruct drm_connector_hdmi_audio_funcs {\n\tint (*startup)(struct drm_connector *);\n\tint (*prepare)(struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*shutdown)(struct drm_connector *);\n\tint (*mute_stream)(struct drm_connector *, bool, int);\n};\n\nstruct drm_connector_hdmi_cec_funcs;\n\nstruct drm_connector_hdmi_cec_data {\n\tstruct cec_adapter *adapter;\n\tconst struct drm_connector_hdmi_cec_funcs *funcs;\n};\n\nstruct drm_connector_hdmi_cec_funcs {\n\tint (*init)(struct drm_connector *);\n\tvoid (*uninit)(struct drm_connector *);\n\tint (*enable)(struct drm_connector *, bool);\n\tint (*log_addr)(struct drm_connector *, u8);\n\tint (*transmit)(struct drm_connector *, u8, u32, struct cec_msg *);\n};\n\nstruct drm_connector_hdmi_state {\n\tenum drm_hdmi_broadcast_rgb broadcast_rgb;\n\tstruct {\n\t\tstruct drm_connector_hdmi_infoframe avi;\n\t\tstruct drm_connector_hdmi_infoframe hdr_drm;\n\t\tstruct drm_connector_hdmi_infoframe spd;\n\t\tstruct drm_connector_hdmi_infoframe hdmi;\n\t} infoframes;\n\tbool is_limited_range;\n\tunsigned int output_bpc;\n\tenum hdmi_colorspace output_format;\n\tlong long unsigned int tmds_char_rate;\n};\n\nstruct drm_writeback_connector;\n\nstruct drm_writeback_job;\n\nstruct drm_connector_helper_funcs {\n\tint (*get_modes)(struct drm_connector *);\n\tint (*detect_ctx)(struct drm_connector *, struct drm_modeset_acquire_ctx *, bool);\n\tenum drm_mode_status (*mode_valid)(struct drm_connector *, const struct drm_display_mode *);\n\tint (*mode_valid_ctx)(struct drm_connector *, const struct drm_display_mode *, struct drm_modeset_acquire_ctx *, enum drm_mode_status *);\n\tstruct drm_encoder * (*best_encoder)(struct drm_connector *);\n\tstruct drm_encoder * (*atomic_best_encoder)(struct drm_connector *, struct drm_atomic_state *);\n\tint (*atomic_check)(struct drm_connector *, struct drm_atomic_state *);\n\tvoid (*atomic_commit)(struct drm_connector *, struct drm_atomic_state *);\n\tint (*prepare_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n\tvoid (*cleanup_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n\tvoid (*enable_hpd)(struct drm_connector *);\n\tvoid (*disable_hpd)(struct drm_connector *);\n};\n\nstruct drm_connector_list_iter {\n\tstruct drm_device *dev;\n\tstruct drm_connector *conn;\n};\n\nstruct drm_tv_connector_state {\n\tenum drm_mode_subconnector select_subconnector;\n\tenum drm_mode_subconnector subconnector;\n\tstruct drm_connector_tv_margins margins;\n\tunsigned int legacy_mode;\n\tunsigned int mode;\n\tunsigned int brightness;\n\tunsigned int contrast;\n\tunsigned int flicker_reduction;\n\tunsigned int overscan;\n\tunsigned int saturation;\n\tunsigned int hue;\n};\n\nstruct drm_connector_state {\n\tstruct drm_connector *connector;\n\tstruct drm_crtc *crtc;\n\tstruct drm_encoder *best_encoder;\n\tenum drm_link_status link_status;\n\tstruct drm_atomic_state *state;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_tv_connector_state tv;\n\tbool self_refresh_aware;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n\tunsigned int content_type;\n\tunsigned int hdcp_content_type;\n\tunsigned int scaling_mode;\n\tunsigned int content_protection;\n\tenum drm_colorspace colorspace;\n\tstruct drm_writeback_job *writeback_job;\n\tu8 max_requested_bpc;\n\tu8 max_bpc;\n\tenum drm_privacy_screen_status privacy_screen_sw_state;\n\tstruct drm_property_blob *hdr_output_metadata;\n\tlong: 32;\n\tstruct drm_connector_hdmi_state hdmi;\n};\n\nstruct drm_display_mode {\n\tint clock;\n\tu16 hdisplay;\n\tu16 hsync_start;\n\tu16 hsync_end;\n\tu16 htotal;\n\tu16 hskew;\n\tu16 vdisplay;\n\tu16 vsync_start;\n\tu16 vsync_end;\n\tu16 vtotal;\n\tu16 vscan;\n\tu32 flags;\n\tint crtc_clock;\n\tu16 crtc_hdisplay;\n\tu16 crtc_hblank_start;\n\tu16 crtc_hblank_end;\n\tu16 crtc_hsync_start;\n\tu16 crtc_hsync_end;\n\tu16 crtc_htotal;\n\tu16 crtc_hskew;\n\tu16 crtc_vdisplay;\n\tu16 crtc_vblank_start;\n\tu16 crtc_vblank_end;\n\tu16 crtc_vsync_start;\n\tu16 crtc_vsync_end;\n\tu16 crtc_vtotal;\n\tu16 width_mm;\n\tu16 height_mm;\n\tu8 type;\n\tbool expose_to_userspace;\n\tstruct list_head head;\n\tchar name[32];\n\tenum drm_mode_status status;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n};\n\nstruct drm_crtc_crc_entry;\n\nstruct drm_crtc_crc {\n\tspinlock_t lock;\n\tconst char *source;\n\tbool opened;\n\tbool overflow;\n\tstruct drm_crtc_crc_entry *entries;\n\tint head;\n\tint tail;\n\tsize_t values_cnt;\n\twait_queue_head_t wq;\n};\n\nstruct drm_crtc_funcs;\n\nstruct drm_crtc_helper_funcs;\n\nstruct drm_self_refresh_data;\n\nstruct drm_crtc {\n\tstruct drm_device *dev;\n\tstruct device_node *port;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tstruct drm_plane *primary;\n\tstruct drm_plane *cursor;\n\tunsigned int index;\n\tint cursor_x;\n\tint cursor_y;\n\tbool enabled;\n\tstruct drm_display_mode mode;\n\tstruct drm_display_mode hwmode;\n\tint x;\n\tint y;\n\tconst struct drm_crtc_funcs *funcs;\n\tuint32_t gamma_size;\n\tuint16_t *gamma_store;\n\tconst struct drm_crtc_helper_funcs *helper_private;\n\tstruct drm_object_properties properties;\n\tstruct drm_property *scaling_filter_property;\n\tstruct drm_property *sharpness_strength_property;\n\tstruct drm_crtc_state *state;\n\tstruct list_head commit_list;\n\tspinlock_t commit_lock;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_crtc_crc crc;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n\tstruct drm_self_refresh_data *self_refresh_data;\n\tlong: 32;\n};\n\nstruct drm_pending_vblank_event;\n\nstruct drm_crtc_commit {\n\tstruct drm_crtc *crtc;\n\tstruct kref ref;\n\tstruct completion flip_done;\n\tstruct completion hw_done;\n\tstruct completion cleanup_done;\n\tstruct list_head commit_entry;\n\tstruct drm_pending_vblank_event *event;\n\tbool abort_completion;\n};\n\nstruct drm_crtc_crc_entry {\n\tbool has_frame_counter;\n\tuint32_t frame;\n\tuint32_t crcs[10];\n};\n\nstruct drm_crtc_funcs {\n\tvoid (*reset)(struct drm_crtc *);\n\tint (*cursor_set)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t);\n\tint (*cursor_set2)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t, int32_t, int32_t);\n\tint (*cursor_move)(struct drm_crtc *, int, int);\n\tint (*gamma_set)(struct drm_crtc *, u16 *, u16 *, u16 *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_crtc *);\n\tint (*set_config)(struct drm_mode_set *, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip_target)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*set_property)(struct drm_crtc *, struct drm_property *, uint64_t);\n\tstruct drm_crtc_state * (*atomic_duplicate_state)(struct drm_crtc *);\n\tvoid (*atomic_destroy_state)(struct drm_crtc *, struct drm_crtc_state *);\n\tint (*atomic_set_property)(struct drm_crtc *, struct drm_crtc_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_crtc *, const struct drm_crtc_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_crtc *);\n\tvoid (*early_unregister)(struct drm_crtc *);\n\tint (*set_crc_source)(struct drm_crtc *, const char *);\n\tint (*verify_crc_source)(struct drm_crtc *, const char *, size_t *);\n\tconst char * const * (*get_crc_sources)(struct drm_crtc *, size_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_crtc_state *);\n\tu32 (*get_vblank_counter)(struct drm_crtc *);\n\tint (*enable_vblank)(struct drm_crtc *);\n\tvoid (*disable_vblank)(struct drm_crtc *);\n\tbool (*get_vblank_timestamp)(struct drm_crtc *, int *, ktime_t *, bool);\n};\n\nstruct drm_crtc_get_sequence {\n\t__u32 crtc_id;\n\t__u32 active;\n\t__u64 sequence;\n\t__s64 sequence_ns;\n};\n\nstruct drm_crtc_helper_funcs {\n\tvoid (*dpms)(struct drm_crtc *, int);\n\tvoid (*prepare)(struct drm_crtc *);\n\tvoid (*commit)(struct drm_crtc *);\n\tenum drm_mode_status (*mode_valid)(struct drm_crtc *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_crtc *, const struct drm_display_mode *, struct drm_display_mode *);\n\tint (*mode_set)(struct drm_crtc *, struct drm_display_mode *, struct drm_display_mode *, int, int, struct drm_framebuffer *);\n\tvoid (*mode_set_nofb)(struct drm_crtc *);\n\tint (*mode_set_base)(struct drm_crtc *, int, int, struct drm_framebuffer *);\n\tvoid (*disable)(struct drm_crtc *);\n\tint (*atomic_check)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_begin)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_flush)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_crtc *, struct drm_atomic_state *);\n\tbool (*get_scanout_position)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n\tbool (*handle_vblank_timeout)(struct drm_crtc *);\n};\n\nstruct drm_crtc_queue_sequence {\n\t__u32 crtc_id;\n\t__u32 flags;\n\t__u64 sequence;\n\t__u64 user_data;\n};\n\nstruct drm_crtc_state {\n\tstruct drm_crtc *crtc;\n\tbool enable;\n\tbool active;\n\tbool planes_changed: 1;\n\tbool mode_changed: 1;\n\tbool active_changed: 1;\n\tbool connectors_changed: 1;\n\tbool zpos_changed: 1;\n\tbool color_mgmt_changed: 1;\n\tbool no_vblank;\n\tu32 plane_mask;\n\tu32 connector_mask;\n\tu32 encoder_mask;\n\tstruct drm_display_mode adjusted_mode;\n\tstruct drm_display_mode mode;\n\tstruct drm_property_blob *mode_blob;\n\tstruct drm_property_blob *degamma_lut;\n\tstruct drm_property_blob *ctm;\n\tstruct drm_property_blob *gamma_lut;\n\tu32 target_vblank;\n\tbool async_flip;\n\tbool vrr_enabled;\n\tbool self_refresh_active;\n\tenum drm_scaling_filter scaling_filter;\n\tu8 sharpness_strength;\n\tstruct drm_pending_vblank_event *event;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_debugfs_info {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n\tu32 driver_features;\n\tvoid *data;\n};\n\nstruct drm_debugfs_entry {\n\tstruct drm_device *dev;\n\tstruct drm_debugfs_info file;\n\tstruct list_head list;\n};\n\nstruct drm_mode_config_funcs;\n\nstruct drm_mode_config_helper_funcs;\n\nstruct drm_mode_config {\n\tstruct mutex mutex;\n\tstruct drm_modeset_lock connection_mutex;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct mutex idr_mutex;\n\tstruct idr object_idr;\n\tstruct idr tile_idr;\n\tstruct mutex fb_lock;\n\tint num_fb;\n\tstruct list_head fb_list;\n\tspinlock_t connector_list_lock;\n\tint num_connector;\n\tstruct ida connector_ida;\n\tstruct list_head connector_list;\n\tstruct llist_head connector_free_list;\n\tstruct work_struct connector_free_work;\n\tint num_encoder;\n\tstruct list_head encoder_list;\n\tint num_total_plane;\n\tstruct list_head plane_list;\n\tstruct raw_spinlock panic_lock;\n\tint num_colorop;\n\tstruct list_head colorop_list;\n\tint num_crtc;\n\tstruct list_head crtc_list;\n\tstruct list_head property_list;\n\tstruct list_head privobj_list;\n\tunsigned int min_width;\n\tunsigned int min_height;\n\tunsigned int max_width;\n\tunsigned int max_height;\n\tconst struct drm_mode_config_funcs *funcs;\n\tbool poll_enabled;\n\tbool poll_running;\n\tbool delayed_event;\n\tstruct delayed_work output_poll_work;\n\tstruct mutex blob_lock;\n\tstruct list_head property_blob_list;\n\tstruct drm_property *edid_property;\n\tstruct drm_property *dpms_property;\n\tstruct drm_property *path_property;\n\tstruct drm_property *tile_property;\n\tstruct drm_property *link_status_property;\n\tstruct drm_property *plane_type_property;\n\tstruct drm_property *prop_src_x;\n\tstruct drm_property *prop_src_y;\n\tstruct drm_property *prop_src_w;\n\tstruct drm_property *prop_src_h;\n\tstruct drm_property *prop_crtc_x;\n\tstruct drm_property *prop_crtc_y;\n\tstruct drm_property *prop_crtc_w;\n\tstruct drm_property *prop_crtc_h;\n\tstruct drm_property *prop_fb_id;\n\tstruct drm_property *prop_in_fence_fd;\n\tstruct drm_property *prop_out_fence_ptr;\n\tstruct drm_property *prop_crtc_id;\n\tstruct drm_property *prop_fb_damage_clips;\n\tstruct drm_property *prop_active;\n\tstruct drm_property *prop_mode_id;\n\tstruct drm_property *prop_vrr_enabled;\n\tstruct drm_property *dvi_i_subconnector_property;\n\tstruct drm_property *dvi_i_select_subconnector_property;\n\tstruct drm_property *dp_subconnector_property;\n\tstruct drm_property *tv_subconnector_property;\n\tstruct drm_property *tv_select_subconnector_property;\n\tstruct drm_property *legacy_tv_mode_property;\n\tstruct drm_property *tv_mode_property;\n\tstruct drm_property *tv_left_margin_property;\n\tstruct drm_property *tv_right_margin_property;\n\tstruct drm_property *tv_top_margin_property;\n\tstruct drm_property *tv_bottom_margin_property;\n\tstruct drm_property *tv_brightness_property;\n\tstruct drm_property *tv_contrast_property;\n\tstruct drm_property *tv_flicker_reduction_property;\n\tstruct drm_property *tv_overscan_property;\n\tstruct drm_property *tv_saturation_property;\n\tstruct drm_property *tv_hue_property;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *aspect_ratio_property;\n\tstruct drm_property *content_type_property;\n\tstruct drm_property *degamma_lut_property;\n\tstruct drm_property *degamma_lut_size_property;\n\tstruct drm_property *ctm_property;\n\tstruct drm_property *gamma_lut_property;\n\tstruct drm_property *gamma_lut_size_property;\n\tstruct drm_property *suggested_x_property;\n\tstruct drm_property *suggested_y_property;\n\tstruct drm_property *non_desktop_property;\n\tstruct drm_property *panel_orientation_property;\n\tstruct drm_property *writeback_fb_id_property;\n\tstruct drm_property *writeback_pixel_formats_property;\n\tstruct drm_property *writeback_out_fence_ptr_property;\n\tstruct drm_property *hdr_output_metadata_property;\n\tstruct drm_property *content_protection_property;\n\tstruct drm_property *hdcp_content_type_property;\n\tuint32_t preferred_depth;\n\tuint32_t prefer_shadow;\n\tbool quirk_addfb_prefer_xbgr_30bpp;\n\tbool quirk_addfb_prefer_host_byte_order;\n\tbool async_page_flip;\n\tbool fb_modifiers_not_supported;\n\tbool normalize_zpos;\n\tstruct drm_property *modifiers_property;\n\tstruct drm_property *async_modifiers_property;\n\tstruct drm_property *size_hints_property;\n\tuint32_t cursor_width;\n\tuint32_t cursor_height;\n\tstruct drm_atomic_state *suspend_state;\n\tconst struct drm_mode_config_helper_funcs *helper_private;\n};\n\nstruct drm_vram_mm;\n\nstruct drm_driver;\n\nstruct drm_minor;\n\nstruct drm_master;\n\nstruct drm_vblank_crtc;\n\nstruct drm_vma_offset_manager;\n\nstruct drm_fb_helper;\n\nstruct drm_device {\n\tint if_version;\n\tstruct kref ref;\n\tstruct device *dev;\n\tstruct device *dma_dev;\n\tstruct {\n\t\tstruct list_head resources;\n\t\tvoid *final_kfree;\n\t\tspinlock_t lock;\n\t} managed;\n\tconst struct drm_driver *driver;\n\tvoid *dev_private;\n\tstruct drm_minor *primary;\n\tstruct drm_minor *render;\n\tstruct drm_minor *accel;\n\tbool registered;\n\tstruct drm_master *master;\n\tu32 driver_features;\n\tbool unplugged;\n\tstruct inode *anon_inode;\n\tchar *unique;\n\tstruct mutex master_mutex;\n\tatomic_t open_count;\n\tstruct mutex filelist_mutex;\n\tstruct list_head filelist;\n\tstruct list_head filelist_internal;\n\tstruct mutex clientlist_mutex;\n\tstruct list_head clientlist;\n\tstruct list_head client_sysrq_list;\n\tbool vblank_disable_immediate;\n\tstruct drm_vblank_crtc *vblank;\n\tspinlock_t vblank_time_lock;\n\tspinlock_t vbl_lock;\n\tu32 max_vblank_count;\n\tstruct list_head vblank_event_list;\n\tspinlock_t event_lock;\n\tunsigned int num_crtcs;\n\tstruct drm_mode_config mode_config;\n\tstruct mutex object_name_lock;\n\tstruct idr object_name_idr;\n\tstruct drm_vma_offset_manager *vma_offset_manager;\n\tstruct drm_vram_mm *vram_mm;\n\tenum switch_power_state switch_power_state;\n\tstruct drm_fb_helper *fb_helper;\n\tstruct dentry *debugfs_root;\n};\n\nstruct drm_dmi_panel_orientation_data {\n\tint width;\n\tint height;\n\tconst char * const *bios_dates;\n\tint orientation;\n};\n\nstruct drm_dp_as_sdp {\n\tunsigned char sdp_type;\n\tunsigned char revision;\n\tunsigned char length;\n\tint vtotal;\n\tint target_rr;\n\tint duration_incr_ms;\n\tint duration_decr_ms;\n\tbool target_rr_divider;\n\tenum operation_mode mode;\n};\n\nstruct drm_dp_aux_cec {\n\tstruct mutex lock;\n\tstruct cec_adapter *adap;\n\tstruct drm_connector *connector;\n\tstruct delayed_work unregister_work;\n};\n\nstruct drm_dp_aux_msg;\n\nstruct drm_dp_aux {\n\tconst char *name;\n\tlong: 32;\n\tstruct i2c_adapter ddc;\n\tstruct device *dev;\n\tstruct drm_device *drm_dev;\n\tstruct drm_crtc *crtc;\n\tstruct mutex hw_mutex;\n\tstruct work_struct crc_work;\n\tu8 crc_count;\n\tssize_t (*transfer)(struct drm_dp_aux *, struct drm_dp_aux_msg *);\n\tint (*wait_hpd_asserted)(struct drm_dp_aux *, long unsigned int);\n\tunsigned int i2c_nack_count;\n\tunsigned int i2c_defer_count;\n\tstruct drm_dp_aux_cec cec;\n\tbool is_remote;\n\tbool powered_down;\n\tbool no_zero_sized;\n\tbool dpcd_probe_disabled;\n};\n\nstruct drm_dp_aux_msg {\n\tunsigned int address;\n\tu8 request;\n\tu8 reply;\n\tvoid *buffer;\n\tsize_t size;\n};\n\nstruct drm_dp_dpcd_ident {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tu8 hw_rev;\n\tu8 sw_major_rev;\n\tu8 sw_minor_rev;\n};\n\nstruct drm_dp_desc {\n\tstruct drm_dp_dpcd_ident ident;\n\tu32 quirks;\n};\n\nstruct drm_dp_link_caps {\n\tbool enhanced_framing;\n\tbool tps3_supported;\n\tbool fast_training;\n\tbool channel_coding;\n\tbool alternate_scrambler_reset;\n};\n\nstruct drm_dp_link_train_set {\n\tunsigned int voltage_swing[4];\n\tunsigned int pre_emphasis[4];\n\tunsigned int post_cursor[4];\n};\n\nstruct drm_dp_link_train {\n\tstruct drm_dp_link_train_set request;\n\tstruct drm_dp_link_train_set adjust;\n\tunsigned int pattern;\n\tbool clock_recovered;\n\tbool channel_equalized;\n};\n\nstruct drm_dp_link_ops;\n\nstruct drm_dp_link {\n\tunsigned char revision;\n\tunsigned int max_rate;\n\tunsigned int max_lanes;\n\tstruct drm_dp_link_caps caps;\n\tstruct {\n\t\tunsigned int cr;\n\t\tunsigned int ce;\n\t} aux_rd_interval;\n\tunsigned char edp;\n\tunsigned int rate;\n\tunsigned int lanes;\n\tlong unsigned int rates[8];\n\tunsigned int num_rates;\n\tconst struct drm_dp_link_ops *ops;\n\tstruct drm_dp_aux *aux;\n\tstruct drm_dp_link_train train;\n};\n\nstruct drm_dp_link_ops {\n\tint (*apply_training)(struct drm_dp_link *);\n\tint (*configure)(struct drm_dp_link *);\n};\n\nstruct drm_dp_mst_port;\n\nstruct drm_dp_mst_atomic_payload {\n\tstruct drm_dp_mst_port *port;\n\ts8 vc_start_slot;\n\tu8 vcpi;\n\tint time_slots;\n\tint pbn;\n\tbool delete: 1;\n\tbool dsc_enabled: 1;\n\tenum drm_dp_mst_payload_allocation payload_allocation_status;\n\tstruct list_head next;\n};\n\nstruct drm_dp_mst_topology_mgr;\n\nstruct drm_dp_mst_branch {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tstruct list_head destroy_next;\n\tu8 rad[8];\n\tu8 lct;\n\tint num_ports;\n\tstruct list_head ports;\n\tstruct drm_dp_mst_port *port_parent;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tbool link_address_sent;\n\tguid_t guid;\n};\n\nstruct drm_dp_mst_port {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tu8 port_num;\n\tbool input;\n\tbool mcs;\n\tbool ddps;\n\tu8 pdt;\n\tbool ldps;\n\tu8 dpcd_rev;\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n\tuint16_t full_pbn;\n\tstruct list_head next;\n\tstruct drm_dp_mst_branch *mstb;\n\tstruct drm_dp_aux aux;\n\tstruct drm_dp_aux *passthrough_aux;\n\tstruct drm_dp_mst_branch *parent;\n\tstruct drm_connector *connector;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tconst struct drm_edid *cached_edid;\n\tbool fec_capable;\n};\n\nstruct drm_dp_mst_topology_cbs {\n\tstruct drm_connector * (*add_connector)(struct drm_dp_mst_topology_mgr *, struct drm_dp_mst_port *, const char *);\n\tvoid (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *);\n};\n\nstruct drm_dp_sideband_msg_hdr {\n\tu8 lct;\n\tu8 lcr;\n\tu8 rad[8];\n\tbool broadcast;\n\tbool path_msg;\n\tu8 msg_len;\n\tbool somt;\n\tbool eomt;\n\tbool seqno;\n};\n\nstruct drm_dp_sideband_msg_rx {\n\tu8 chunk[48];\n\tu8 msg[256];\n\tu8 curchunk_len;\n\tu8 curchunk_idx;\n\tu8 curchunk_hdrlen;\n\tu8 curlen;\n\tbool have_somt;\n\tbool have_eomt;\n\tstruct drm_dp_sideband_msg_hdr initial_hdr;\n};\n\nstruct drm_dp_mst_topology_mgr {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tconst struct drm_dp_mst_topology_cbs *cbs;\n\tint max_dpcd_transaction_bytes;\n\tstruct drm_dp_aux *aux;\n\tint max_payloads;\n\tint conn_base_id;\n\tstruct drm_dp_sideband_msg_rx up_req_recv;\n\tstruct drm_dp_sideband_msg_rx down_rep_recv;\n\tstruct mutex lock;\n\tstruct mutex probe_lock;\n\tbool mst_state: 1;\n\tbool payload_id_table_cleared: 1;\n\tbool reset_rx_state: 1;\n\tu8 payload_count;\n\tu8 next_start_slot;\n\tstruct drm_dp_mst_branch *mst_primary;\n\tu8 dpcd[15];\n\tu8 sink_count;\n\tconst struct drm_private_state_funcs *funcs;\n\tstruct mutex qlock;\n\tstruct list_head tx_msg_downq;\n\twait_queue_head_t tx_waitq;\n\tstruct work_struct work;\n\tstruct work_struct tx_work;\n\tstruct list_head destroy_port_list;\n\tstruct list_head destroy_branch_device_list;\n\tstruct mutex delayed_destroy_lock;\n\tstruct workqueue_struct *delayed_destroy_wq;\n\tstruct work_struct delayed_destroy_work;\n\tstruct list_head up_req_list;\n\tstruct mutex up_req_lock;\n\tstruct work_struct up_req_work;\n};\n\nstruct drm_dp_mst_topology_state {\n\tstruct drm_private_state base;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tu32 pending_crtc_mask;\n\tstruct drm_crtc_commit **commit_deps;\n\tsize_t num_commit_deps;\n\tu32 payload_mask;\n\tstruct list_head payloads;\n\tu8 total_avail_slots;\n\tu8 start_slot;\n\tfixed20_12 pbn_div;\n};\n\nstruct drm_dp_sideband_msg_req_body {\n\tu8 req_type;\n\tunion ack_req u;\n};\n\nstruct drm_dp_pending_up_req {\n\tstruct drm_dp_sideband_msg_hdr hdr;\n\tstruct drm_dp_sideband_msg_req_body msg;\n\tstruct list_head next;\n};\n\nstruct drm_dp_phy_test_params {\n\tint link_rate;\n\tu8 num_lanes;\n\tu8 phy_pattern;\n\tu8 hbr2_reset[2];\n\tu8 custom80[10];\n\tbool enhanced_frame_cap;\n};\n\nstruct drm_dp_sideband_msg_reply_body {\n\tu8 reply_type;\n\tu8 req_type;\n\tunion ack_replies u;\n};\n\nstruct drm_dp_sideband_msg_tx {\n\tu8 msg[256];\n\tu8 chunk[48];\n\tu8 cur_offset;\n\tu8 cur_len;\n\tstruct drm_dp_mst_branch *dst;\n\tstruct list_head next;\n\tint seqno;\n\tint state;\n\tbool path_msg;\n\tstruct drm_dp_sideband_msg_reply_body reply;\n};\n\nstruct drm_dp_vsc_sdp {\n\tunsigned char sdp_type;\n\tunsigned char revision;\n\tunsigned char length;\n\tenum dp_pixelformat pixelformat;\n\tenum dp_colorimetry colorimetry;\n\tint bpc;\n\tenum dp_dynamic_range dynamic_range;\n\tenum dp_content_type content_type;\n};\n\nstruct drm_mode_create_dumb;\n\nstruct drm_fb_helper_surface_size;\n\nstruct drm_ioctl_desc;\n\nstruct drm_driver {\n\tint (*load)(struct drm_device *, long unsigned int);\n\tint (*open)(struct drm_device *, struct drm_file *);\n\tvoid (*postclose)(struct drm_device *, struct drm_file *);\n\tvoid (*unload)(struct drm_device *);\n\tvoid (*release)(struct drm_device *);\n\tvoid (*master_set)(struct drm_device *, struct drm_file *, bool);\n\tvoid (*master_drop)(struct drm_device *, struct drm_file *);\n\tvoid (*debugfs_init)(struct drm_minor *);\n\tstruct drm_gem_object * (*gem_create_object)(struct drm_device *, size_t);\n\tint (*prime_handle_to_fd)(struct drm_device *, struct drm_file *, uint32_t, uint32_t, int *);\n\tint (*prime_fd_to_handle)(struct drm_device *, struct drm_file *, int, uint32_t *);\n\tstruct drm_gem_object * (*gem_prime_import)(struct drm_device *, struct dma_buf *);\n\tstruct drm_gem_object * (*gem_prime_import_sg_table)(struct drm_device *, struct dma_buf_attachment *, struct sg_table *);\n\tint (*dumb_create)(struct drm_file *, struct drm_device *, struct drm_mode_create_dumb *);\n\tint (*dumb_map_offset)(struct drm_file *, struct drm_device *, uint32_t, uint64_t *);\n\tint (*fbdev_probe)(struct drm_fb_helper *, struct drm_fb_helper_surface_size *);\n\tvoid (*show_fdinfo)(struct drm_printer *, struct drm_file *);\n\tint major;\n\tint minor;\n\tint patchlevel;\n\tchar *name;\n\tchar *desc;\n\tu32 driver_features;\n\tconst struct drm_ioctl_desc *ioctls;\n\tint num_ioctls;\n\tconst struct file_operations *fops;\n};\n\nstruct drm_dsc_rc_range_parameters {\n\tu8 range_min_qp;\n\tu8 range_max_qp;\n\tu8 range_bpg_offset;\n};\n\nstruct drm_dsc_config {\n\tu8 line_buf_depth;\n\tu8 bits_per_component;\n\tbool convert_rgb;\n\tu8 slice_count;\n\tu16 slice_width;\n\tu16 slice_height;\n\tbool simple_422;\n\tu16 pic_width;\n\tu16 pic_height;\n\tu8 rc_tgt_offset_high;\n\tu8 rc_tgt_offset_low;\n\tu16 bits_per_pixel;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_quant_incr_limit0;\n\tu16 initial_xmit_delay;\n\tu16 initial_dec_delay;\n\tbool block_pred_enable;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu16 rc_buf_thresh[14];\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n\tu16 rc_model_size;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 initial_scale_value;\n\tu16 scale_decrement_interval;\n\tu16 scale_increment_interval;\n\tu16 nfl_bpg_offset;\n\tu16 slice_bpg_offset;\n\tu16 final_offset;\n\tbool vbr_enable;\n\tu8 mux_word_size;\n\tu16 slice_chunk_size;\n\tu16 rc_bits;\n\tu8 dsc_version_minor;\n\tu8 dsc_version_major;\n\tbool native_422;\n\tbool native_420;\n\tu8 second_line_bpg_offset;\n\tu16 nsl_bpg_offset;\n\tu16 second_line_offset_adj;\n};\n\nstruct drm_dsc_picture_parameter_set {\n\tu8 dsc_version;\n\tu8 pps_identifier;\n\tu8 pps_reserved;\n\tu8 pps_3;\n\tu8 pps_4;\n\tu8 bits_per_pixel_low;\n\t__be16 pic_height;\n\t__be16 pic_width;\n\t__be16 slice_height;\n\t__be16 slice_width;\n\t__be16 chunk_size;\n\tu8 initial_xmit_delay_high;\n\tu8 initial_xmit_delay_low;\n\t__be16 initial_dec_delay;\n\tu8 pps20_reserved;\n\tu8 initial_scale_value;\n\t__be16 scale_increment_interval;\n\tu8 scale_decrement_interval_high;\n\tu8 scale_decrement_interval_low;\n\tu8 pps26_reserved;\n\tu8 first_line_bpg_offset;\n\t__be16 nfl_bpg_offset;\n\t__be16 slice_bpg_offset;\n\t__be16 initial_offset;\n\t__be16 final_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\t__be16 rc_model_size;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_tgt_offset;\n\tu8 rc_buf_thresh[14];\n\t__be16 rc_range_parameters[15];\n\tu8 native_422_420;\n\tu8 second_line_bpg_offset;\n\t__be16 nsl_bpg_offset;\n\t__be16 second_line_offset_adj;\n\tu32 pps_long_94_reserved;\n\tu32 pps_long_98_reserved;\n\tu32 pps_long_102_reserved;\n\tu32 pps_long_106_reserved;\n\tu32 pps_long_110_reserved;\n\tu32 pps_long_114_reserved;\n\tu32 pps_long_118_reserved;\n\tu32 pps_long_122_reserved;\n\t__be16 pps_short_126_reserved;\n} __attribute__((packed));\n\nstruct edid;\n\nstruct drm_edid {\n\tsize_t size;\n\tconst struct edid *edid;\n};\n\nstruct drm_edid_match_closure {\n\tconst struct drm_edid_ident *ident;\n\tbool matched;\n};\n\nstruct drm_edid_product_id {\n\t__be16 manufacturer_name;\n\t__le16 product_code;\n\t__le32 serial_number;\n\tu8 week_of_manufacture;\n\tu8 year_of_manufacture;\n} __attribute__((packed));\n\nstruct drm_encoder_funcs;\n\nstruct drm_encoder_helper_funcs;\n\nstruct drm_encoder {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tint encoder_type;\n\tunsigned int index;\n\tuint32_t possible_crtcs;\n\tuint32_t possible_clones;\n\tstruct drm_crtc *crtc;\n\tstruct list_head bridge_chain;\n\tconst struct drm_encoder_funcs *funcs;\n\tconst struct drm_encoder_helper_funcs *helper_private;\n\tstruct dentry *debugfs_entry;\n};\n\nstruct drm_encoder_funcs {\n\tvoid (*reset)(struct drm_encoder *);\n\tvoid (*destroy)(struct drm_encoder *);\n\tint (*late_register)(struct drm_encoder *);\n\tvoid (*early_unregister)(struct drm_encoder *);\n\tvoid (*debugfs_init)(struct drm_encoder *, struct dentry *);\n};\n\nstruct drm_encoder_helper_funcs {\n\tvoid (*dpms)(struct drm_encoder *, int);\n\tenum drm_mode_status (*mode_valid)(struct drm_encoder *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_encoder *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*prepare)(struct drm_encoder *);\n\tvoid (*commit)(struct drm_encoder *);\n\tvoid (*mode_set)(struct drm_encoder *, struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*atomic_mode_set)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n\tenum drm_connector_status (*detect)(struct drm_encoder *, struct drm_connector *);\n\tvoid (*atomic_disable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*disable)(struct drm_encoder *);\n\tvoid (*enable)(struct drm_encoder *);\n\tint (*atomic_check)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n};\n\nstruct drm_event {\n\t__u32 type;\n\t__u32 length;\n};\n\nstruct drm_event_crtc_sequence {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__s64 time_ns;\n\t__u64 sequence;\n};\n\nstruct drm_event_vblank {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__u32 tv_sec;\n\t__u32 tv_usec;\n\t__u32 sequence;\n\t__u32 crtc_id;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n};\n\nstruct drm_exec {\n\tu32 flags;\n\tstruct ww_acquire_ctx ticket;\n\tunsigned int num_objects;\n\tunsigned int max_objects;\n\tstruct drm_gem_object **objects;\n\tstruct drm_gem_object *contended;\n\tstruct drm_gem_object *prelocked;\n};\n\nstruct fb_info;\n\nstruct fb_deferred_io {\n\tlong unsigned int delay;\n\tbool sort_pagereflist;\n\tint open_count;\n\tstruct mutex lock;\n\tstruct list_head pagereflist;\n\tstruct address_space *mapping;\n\tstruct page * (*get_page)(struct fb_info *, long unsigned int);\n\tvoid (*deferred_io)(struct fb_info *, struct list_head *);\n};\n\nstruct drm_fb_helper_funcs;\n\nstruct drm_fb_helper {\n\tstruct drm_client_dev client;\n\tstruct drm_client_buffer *buffer;\n\tstruct drm_framebuffer *fb;\n\tstruct drm_device *dev;\n\tconst struct drm_fb_helper_funcs *funcs;\n\tstruct fb_info *info;\n\tu32 pseudo_palette[17];\n\tstruct drm_clip_rect damage_clip;\n\tspinlock_t damage_lock;\n\tstruct work_struct damage_work;\n\tstruct work_struct resume_work;\n\tstruct mutex lock;\n\tbool delayed_hotplug;\n\tbool deferred_setup;\n\tint preferred_bpp;\n\tstruct fb_deferred_io fbdefio;\n};\n\nstruct drm_fb_helper_funcs {\n\tint (*fb_dirty)(struct drm_fb_helper *, struct drm_clip_rect *);\n\tvoid (*fb_restore)(struct drm_fb_helper *);\n\tvoid (*fb_set_suspend)(struct drm_fb_helper *, bool);\n};\n\nstruct drm_fb_helper_surface_size {\n\tu32 fb_width;\n\tu32 fb_height;\n\tu32 surface_width;\n\tu32 surface_height;\n\tu32 surface_bpp;\n\tu32 surface_depth;\n};\n\nstruct drm_prime_file_private {\n\tstruct mutex lock;\n\tstruct rb_root dmabufs;\n\tstruct rb_root handles;\n};\n\nstruct drm_file {\n\tbool authenticated;\n\tbool stereo_allowed;\n\tbool universal_planes;\n\tbool atomic;\n\tbool aspect_ratio_allowed;\n\tbool writeback_connectors;\n\tbool plane_color_pipeline;\n\tbool was_master;\n\tbool is_master;\n\tbool supports_virtualized_cursor_plane;\n\tstruct drm_master *master;\n\tspinlock_t master_lookup_lock;\n\tstruct pid *pid;\n\tu64 client_id;\n\tdrm_magic_t magic;\n\tstruct list_head lhead;\n\tstruct drm_minor *minor;\n\tstruct idr object_idr;\n\tspinlock_t table_lock;\n\tstruct xarray syncobj_xa;\n\tstruct file *filp;\n\tvoid *driver_priv;\n\tstruct list_head fbs;\n\tstruct mutex fbs_lock;\n\tstruct list_head blobs;\n\twait_queue_head_t event_wait;\n\tstruct list_head pending_event_list;\n\tstruct list_head event_list;\n\tint event_space;\n\tstruct mutex event_read_lock;\n\tstruct drm_prime_file_private prime;\n\tconst char *client_name;\n\tstruct mutex client_name_lock;\n\tstruct dentry *debugfs_client;\n\tlong: 32;\n};\n\nstruct drm_flip_task {\n\tstruct list_head node;\n\tvoid *data;\n};\n\nstruct drm_flip_work;\n\ntypedef void (*drm_flip_func_t)(struct drm_flip_work *, void *);\n\nstruct drm_flip_work {\n\tconst char *name;\n\tdrm_flip_func_t func;\n\tstruct work_struct worker;\n\tstruct list_head queued;\n\tstruct list_head commited;\n\tspinlock_t lock;\n};\n\nstruct drm_format_conv_state {\n\tstruct {\n\t\tvoid *mem;\n\t\tsize_t size;\n\t\tbool preallocated;\n\t} tmp;\n};\n\nstruct drm_format_info {\n\tu32 format;\n\tu8 depth;\n\tu8 num_planes;\n\tunion {\n\t\tu8 cpp[4];\n\t\tu8 char_per_block[4];\n\t};\n\tu8 block_w[4];\n\tu8 block_h[4];\n\tu8 hsub;\n\tu8 vsub;\n\tbool has_alpha;\n\tbool is_yuv;\n\tbool is_color_indexed;\n};\n\nstruct drm_format_modifier {\n\t__u64 formats;\n\t__u32 offset;\n\t__u32 pad;\n\t__u64 modifier;\n};\n\nstruct drm_format_modifier_blob {\n\t__u32 version;\n\t__u32 flags;\n\t__u32 count_formats;\n\t__u32 formats_offset;\n\t__u32 count_modifiers;\n\t__u32 modifiers_offset;\n};\n\nstruct drm_framebuffer_funcs {\n\tvoid (*destroy)(struct drm_framebuffer *);\n\tint (*create_handle)(struct drm_framebuffer *, struct drm_file *, unsigned int *);\n\tint (*dirty)(struct drm_framebuffer *, struct drm_file *, unsigned int, unsigned int, struct drm_clip_rect *, unsigned int);\n};\n\nstruct drm_gem_change_handle {\n\t__u32 handle;\n\t__u32 new_handle;\n};\n\nstruct drm_gem_close {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_gem_flink {\n\t__u32 handle;\n\t__u32 name;\n};\n\nstruct drm_gem_lru {\n\tstruct mutex *lock;\n\tlong int count;\n\tstruct list_head list;\n};\n\nstruct drm_mm;\n\nstruct drm_mm_node {\n\tlong unsigned int color;\n\tlong: 32;\n\tu64 start;\n\tu64 size;\n\tstruct drm_mm *mm;\n\tstruct list_head node_list;\n\tstruct list_head hole_stack;\n\tstruct rb_node rb;\n\tstruct rb_node rb_hole_size;\n\tstruct rb_node rb_hole_addr;\n\tu64 __subtree_last;\n\tu64 hole_size;\n\tu64 subtree_max_hole;\n\tlong unsigned int flags;\n\tlong: 32;\n};\n\nstruct drm_vma_offset_node {\n\trwlock_t vm_lock;\n\tlong: 32;\n\tstruct drm_mm_node vm_node;\n\tstruct rb_root vm_files;\n\tvoid *driver_private;\n};\n\nstruct drm_gem_object_funcs;\n\nstruct drm_gem_object {\n\tstruct kref refcount;\n\tunsigned int handle_count;\n\tstruct drm_device *dev;\n\tstruct file *filp;\n\tstruct drm_vma_offset_node vma_node;\n\tsize_t size;\n\tint name;\n\tstruct dma_buf *dma_buf;\n\tstruct dma_buf_attachment *import_attach;\n\tstruct dma_resv *resv;\n\tstruct dma_resv _resv;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct mutex lock;\n\t} gpuva;\n\tconst struct drm_gem_object_funcs *funcs;\n\tstruct list_head lru_node;\n\tstruct drm_gem_lru *lru;\n\tlong: 32;\n};\n\nstruct vm_operations_struct;\n\nstruct drm_gem_object_funcs {\n\tvoid (*free)(struct drm_gem_object *);\n\tint (*open)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*close)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*print_info)(struct drm_printer *, unsigned int, const struct drm_gem_object *);\n\tstruct dma_buf * (*export)(struct drm_gem_object *, int);\n\tint (*pin)(struct drm_gem_object *);\n\tvoid (*unpin)(struct drm_gem_object *);\n\tstruct sg_table * (*get_sg_table)(struct drm_gem_object *);\n\tint (*vmap)(struct drm_gem_object *, struct iosys_map *);\n\tvoid (*vunmap)(struct drm_gem_object *, struct iosys_map *);\n\tint (*mmap)(struct drm_gem_object *, struct vm_area_struct *);\n\tint (*evict)(struct drm_gem_object *);\n\tenum drm_gem_object_status (*status)(struct drm_gem_object *);\n\tsize_t (*rss)(struct drm_gem_object *);\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct drm_gem_open {\n\t__u32 name;\n\t__u32 handle;\n\t__u64 size;\n};\n\nstruct drm_get_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_gpuvm;\n\nstruct drm_gpuvm_bo;\n\nstruct drm_gpuva {\n\tstruct drm_gpuvm *vm;\n\tstruct drm_gpuvm_bo *vm_bo;\n\tenum drm_gpuva_flags flags;\n\tlong: 32;\n\tstruct {\n\t\tu64 addr;\n\t\tu64 range;\n\t} va;\n\tstruct {\n\t\tu64 offset;\n\t\tstruct drm_gem_object *obj;\n\t\tstruct list_head entry;\n\t\tlong: 32;\n\t} gem;\n\tstruct {\n\t\tstruct rb_node node;\n\t\tstruct list_head entry;\n\t\tlong: 32;\n\t\tu64 __subtree_last;\n\t} rb;\n};\n\nstruct drm_gpuva_op_map {\n\tstruct {\n\t\tu64 addr;\n\t\tu64 range;\n\t} va;\n\tstruct {\n\t\tu64 offset;\n\t\tstruct drm_gem_object *obj;\n\t\tlong: 32;\n\t} gem;\n};\n\nstruct drm_gpuva_op_unmap;\n\nstruct drm_gpuva_op_remap {\n\tstruct drm_gpuva_op_map *prev;\n\tstruct drm_gpuva_op_map *next;\n\tstruct drm_gpuva_op_unmap *unmap;\n};\n\nstruct drm_gpuva_op_unmap {\n\tstruct drm_gpuva *va;\n\tbool keep;\n};\n\nstruct drm_gpuva_op_prefetch {\n\tstruct drm_gpuva *va;\n};\n\nstruct drm_gpuva_op {\n\tstruct list_head entry;\n\tenum drm_gpuva_op_type op;\n\tlong: 32;\n\tunion {\n\t\tstruct drm_gpuva_op_map map;\n\t\tstruct drm_gpuva_op_remap remap;\n\t\tstruct drm_gpuva_op_unmap unmap;\n\t\tstruct drm_gpuva_op_prefetch prefetch;\n\t};\n};\n\nstruct drm_gpuvm_ops;\n\nstruct drm_gpuvm {\n\tconst char *name;\n\tenum drm_gpuvm_flags flags;\n\tstruct drm_device *drm;\n\tlong: 32;\n\tu64 mm_start;\n\tu64 mm_range;\n\tstruct {\n\t\tstruct rb_root_cached tree;\n\t\tstruct list_head list;\n\t} rb;\n\tstruct kref kref;\n\tlong: 32;\n\tstruct drm_gpuva kernel_alloc_node;\n\tconst struct drm_gpuvm_ops *ops;\n\tstruct drm_gem_object *r_obj;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct list_head *local_list;\n\t\tspinlock_t lock;\n\t} extobj;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct list_head *local_list;\n\t\tspinlock_t lock;\n\t} evict;\n\tstruct llist_head bo_defer;\n\tlong: 32;\n};\n\nstruct drm_gpuvm_bo {\n\tstruct drm_gpuvm *vm;\n\tstruct drm_gem_object *obj;\n\tbool evicted;\n\tstruct kref kref;\n\tstruct {\n\t\tstruct list_head gpuva;\n\t\tstruct {\n\t\t\tstruct list_head gem;\n\t\t\tstruct list_head extobj;\n\t\t\tstruct list_head evict;\n\t\t\tstruct llist_node bo_defer;\n\t\t} entry;\n\t} list;\n};\n\nstruct drm_gpuvm_ops {\n\tvoid (*vm_free)(struct drm_gpuvm *);\n\tstruct drm_gpuva_op * (*op_alloc)(void);\n\tvoid (*op_free)(struct drm_gpuva_op *);\n\tstruct drm_gpuvm_bo * (*vm_bo_alloc)(void);\n\tvoid (*vm_bo_free)(struct drm_gpuvm_bo *);\n\tint (*vm_bo_validate)(struct drm_gpuvm_bo *, struct drm_exec *);\n\tint (*sm_step_map)(struct drm_gpuva_op *, void *);\n\tint (*sm_step_remap)(struct drm_gpuva_op *, void *);\n\tint (*sm_step_unmap)(struct drm_gpuva_op *, void *);\n};\n\nstruct drm_hdmi_acr_n_cts_entry {\n\tunsigned int n;\n\tunsigned int cts;\n};\n\nstruct drm_hdmi_acr_data {\n\tlong unsigned int tmds_clock_khz;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_32k;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_44k1;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_48k;\n};\n\nstruct drm_info_list {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n\tu32 driver_features;\n\tvoid *data;\n};\n\nstruct drm_info_node {\n\tstruct drm_minor *minor;\n\tconst struct drm_info_list *info_ent;\n\tstruct list_head list;\n\tstruct dentry *dent;\n};\n\ntypedef int drm_ioctl_t(struct drm_device *, void *, struct drm_file *);\n\nstruct drm_ioctl_desc {\n\tunsigned int cmd;\n\tenum drm_ioctl_flags flags;\n\tdrm_ioctl_t *func;\n\tconst char *name;\n};\n\nstruct drm_master {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tchar *unique;\n\tint unique_len;\n\tstruct idr magic_map;\n\tvoid *driver_priv;\n\tstruct drm_master *lessor;\n\tint lessee_id;\n\tstruct list_head lessee_list;\n\tstruct list_head lessees;\n\tstruct idr leases;\n\tstruct idr lessee_idr;\n};\n\nstruct drm_memory_stats {\n\tu64 shared;\n\tu64 private;\n\tu64 resident;\n\tu64 purgeable;\n\tu64 active;\n};\n\nstruct drm_minor {\n\tint index;\n\tint type;\n\tstruct device *kdev;\n\tstruct drm_device *dev;\n\tstruct dentry *debugfs_symlink;\n\tstruct dentry *debugfs_root;\n};\n\nstruct drm_mm {\n\tvoid (*color_adjust)(const struct drm_mm_node *, long unsigned int, u64 *, u64 *);\n\tstruct list_head hole_stack;\n\tlong: 32;\n\tstruct drm_mm_node head_node;\n\tstruct rb_root_cached interval_tree;\n\tstruct rb_root_cached holes_size;\n\tstruct rb_root holes_addr;\n\tlong unsigned int scan_active;\n};\n\nstruct drm_mm_scan {\n\tstruct drm_mm *mm;\n\tlong: 32;\n\tu64 size;\n\tu64 alignment;\n\tu64 remainder_mask;\n\tu64 range_start;\n\tu64 range_end;\n\tu64 hit_start;\n\tu64 hit_end;\n\tlong unsigned int color;\n\tenum drm_mm_insert_mode mode;\n};\n\nstruct drm_mode_atomic {\n\t__u32 flags;\n\t__u32 count_objs;\n\t__u64 objs_ptr;\n\t__u64 count_props_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u64 reserved;\n\t__u64 user_data;\n};\n\nstruct drm_mode_card_res {\n\t__u64 fb_id_ptr;\n\t__u64 crtc_id_ptr;\n\t__u64 connector_id_ptr;\n\t__u64 encoder_id_ptr;\n\t__u32 count_fbs;\n\t__u32 count_crtcs;\n\t__u32 count_connectors;\n\t__u32 count_encoders;\n\t__u32 min_width;\n\t__u32 max_width;\n\t__u32 min_height;\n\t__u32 max_height;\n};\n\nstruct drm_mode_closefb {\n\t__u32 fb_id;\n\t__u32 pad;\n};\n\nstruct drm_mode_fb_cmd2;\n\nstruct drm_mode_config_funcs {\n\tstruct drm_framebuffer * (*fb_create)(struct drm_device *, struct drm_file *, const struct drm_format_info *, const struct drm_mode_fb_cmd2 *);\n\tconst struct drm_format_info * (*get_format_info)(u32, u64);\n\tenum drm_mode_status (*mode_valid)(struct drm_device *, const struct drm_display_mode *);\n\tint (*atomic_check)(struct drm_device *, struct drm_atomic_state *);\n\tint (*atomic_commit)(struct drm_device *, struct drm_atomic_state *, bool);\n\tstruct drm_atomic_state * (*atomic_state_alloc)(struct drm_device *);\n\tvoid (*atomic_state_clear)(struct drm_atomic_state *);\n\tvoid (*atomic_state_free)(struct drm_atomic_state *);\n};\n\nstruct drm_mode_config_helper_funcs {\n\tvoid (*atomic_commit_tail)(struct drm_atomic_state *);\n\tint (*atomic_commit_setup)(struct drm_atomic_state *);\n};\n\nstruct drm_mode_connector_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 connector_id;\n};\n\nstruct drm_mode_create_blob {\n\t__u64 data;\n\t__u32 length;\n\t__u32 blob_id;\n};\n\nstruct drm_mode_create_dumb {\n\t__u32 height;\n\t__u32 width;\n\t__u32 bpp;\n\t__u32 flags;\n\t__u32 handle;\n\t__u32 pitch;\n\t__u64 size;\n};\n\nstruct drm_mode_create_lease {\n\t__u64 object_ids;\n\t__u32 object_count;\n\t__u32 flags;\n\t__u32 lessee_id;\n\t__u32 fd;\n};\n\nstruct drm_mode_modeinfo {\n\t__u32 clock;\n\t__u16 hdisplay;\n\t__u16 hsync_start;\n\t__u16 hsync_end;\n\t__u16 htotal;\n\t__u16 hskew;\n\t__u16 vdisplay;\n\t__u16 vsync_start;\n\t__u16 vsync_end;\n\t__u16 vtotal;\n\t__u16 vscan;\n\t__u32 vrefresh;\n\t__u32 flags;\n\t__u32 type;\n\tchar name[32];\n};\n\nstruct drm_mode_crtc {\n\t__u64 set_connectors_ptr;\n\t__u32 count_connectors;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 x;\n\t__u32 y;\n\t__u32 gamma_size;\n\t__u32 mode_valid;\n\tstruct drm_mode_modeinfo mode;\n};\n\nstruct drm_mode_crtc_lut {\n\t__u32 crtc_id;\n\t__u32 gamma_size;\n\t__u64 red;\n\t__u64 green;\n\t__u64 blue;\n};\n\nstruct drm_mode_crtc_page_flip_target {\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 sequence;\n\t__u64 user_data;\n};\n\nstruct drm_mode_cursor {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n};\n\nstruct drm_mode_cursor2 {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n\t__s32 hot_x;\n\t__s32 hot_y;\n};\n\nstruct drm_mode_destroy_blob {\n\t__u32 blob_id;\n};\n\nstruct drm_mode_destroy_dumb {\n\t__u32 handle;\n};\n\nstruct drm_mode_fb_cmd {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pitch;\n\t__u32 bpp;\n\t__u32 depth;\n\t__u32 handle;\n};\n\nstruct drm_mode_fb_cmd2 {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pixel_format;\n\t__u32 flags;\n\t__u32 handles[4];\n\t__u32 pitches[4];\n\t__u32 offsets[4];\n\tlong: 32;\n\t__u64 modifier[4];\n};\n\nstruct drm_mode_fb_dirty_cmd {\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 color;\n\t__u32 num_clips;\n\t__u64 clips_ptr;\n};\n\nstruct drm_mode_get_blob {\n\t__u32 blob_id;\n\t__u32 length;\n\t__u64 data;\n};\n\nstruct drm_mode_get_connector {\n\t__u64 encoders_ptr;\n\t__u64 modes_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_modes;\n\t__u32 count_props;\n\t__u32 count_encoders;\n\t__u32 encoder_id;\n\t__u32 connector_id;\n\t__u32 connector_type;\n\t__u32 connector_type_id;\n\t__u32 connection;\n\t__u32 mm_width;\n\t__u32 mm_height;\n\t__u32 subpixel;\n\t__u32 pad;\n};\n\nstruct drm_mode_get_encoder {\n\t__u32 encoder_id;\n\t__u32 encoder_type;\n\t__u32 crtc_id;\n\t__u32 possible_crtcs;\n\t__u32 possible_clones;\n};\n\nstruct drm_mode_get_lease {\n\t__u32 count_objects;\n\t__u32 pad;\n\t__u64 objects_ptr;\n};\n\nstruct drm_mode_get_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 possible_crtcs;\n\t__u32 gamma_size;\n\t__u32 count_format_types;\n\t__u64 format_type_ptr;\n};\n\nstruct drm_mode_get_plane_res {\n\t__u64 plane_id_ptr;\n\t__u32 count_planes;\n\tlong: 32;\n};\n\nstruct drm_mode_get_property {\n\t__u64 values_ptr;\n\t__u64 enum_blob_ptr;\n\t__u32 prop_id;\n\t__u32 flags;\n\tchar name[32];\n\t__u32 count_values;\n\t__u32 count_enum_blobs;\n};\n\nstruct drm_mode_list_lessees {\n\t__u32 count_lessees;\n\t__u32 pad;\n\t__u64 lessees_ptr;\n};\n\nstruct drm_mode_map_dumb {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n};\n\nstruct drm_mode_obj_get_properties {\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_props;\n\t__u32 obj_id;\n\t__u32 obj_type;\n\tlong: 32;\n};\n\nstruct drm_mode_obj_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 obj_id;\n\t__u32 obj_type;\n\tlong: 32;\n};\n\nstruct drm_mode_property_enum {\n\t__u64 value;\n\tchar name[32];\n};\n\nstruct drm_mode_rect {\n\t__s32 x1;\n\t__s32 y1;\n\t__s32 x2;\n\t__s32 y2;\n};\n\nstruct drm_mode_revoke_lease {\n\t__u32 lessee_id;\n};\n\nstruct drm_mode_rmfb_work {\n\tstruct work_struct work;\n\tstruct list_head fbs;\n};\n\nstruct drm_mode_set {\n\tstruct drm_framebuffer *fb;\n\tstruct drm_crtc *crtc;\n\tstruct drm_display_mode *mode;\n\tuint32_t x;\n\tuint32_t y;\n\tstruct drm_connector **connectors;\n\tsize_t num_connectors;\n};\n\nstruct drm_mode_set_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__s32 crtc_x;\n\t__s32 crtc_y;\n\t__u32 crtc_w;\n\t__u32 crtc_h;\n\t__u32 src_x;\n\t__u32 src_y;\n\t__u32 src_h;\n\t__u32 src_w;\n};\n\nstruct drm_modeset_acquire_ctx {\n\tstruct ww_acquire_ctx ww_ctx;\n\tstruct drm_modeset_lock *contended;\n\tdepot_stack_handle_t stack_depot;\n\tstruct list_head locked;\n\tbool trylock_only;\n\tbool interruptible;\n};\n\nstruct drm_named_mode {\n\tconst char *name;\n\tunsigned int pixel_clock_khz;\n\tunsigned int xres;\n\tunsigned int yres;\n\tunsigned int flags;\n\tunsigned int tv_mode;\n};\n\nstruct sync_file;\n\nstruct drm_out_fence_state {\n\ts32 *out_fence_ptr;\n\tstruct sync_file *sync_file;\n\tint fd;\n};\n\nstruct drm_panel_funcs;\n\nstruct drm_panel {\n\tstruct device *dev;\n\tstruct backlight_device *backlight;\n\tconst struct drm_panel_funcs *funcs;\n\tint connector_type;\n\tstruct list_head list;\n\tstruct list_head followers;\n\tstruct mutex follower_lock;\n\tbool prepare_prev_first;\n\tbool prepared;\n\tbool enabled;\n\tvoid *container;\n\tstruct kref refcount;\n};\n\nstruct drm_panel_follower_funcs;\n\nstruct drm_panel_follower {\n\tconst struct drm_panel_follower_funcs *funcs;\n\tstruct list_head list;\n\tstruct drm_panel *panel;\n};\n\nstruct drm_panel_follower_funcs {\n\tint (*panel_prepared)(struct drm_panel_follower *);\n\tint (*panel_unpreparing)(struct drm_panel_follower *);\n\tint (*panel_enabled)(struct drm_panel_follower *);\n\tint (*panel_disabling)(struct drm_panel_follower *);\n};\n\nstruct drm_panel_funcs {\n\tint (*prepare)(struct drm_panel *);\n\tint (*enable)(struct drm_panel *);\n\tint (*disable)(struct drm_panel *);\n\tint (*unprepare)(struct drm_panel *);\n\tint (*get_modes)(struct drm_panel *, struct drm_connector *);\n\tenum drm_panel_orientation (*get_orientation)(struct drm_panel *);\n\tint (*get_timings)(struct drm_panel *, unsigned int, struct display_timing *);\n\tvoid (*debugfs_init)(struct drm_panel *, struct dentry *);\n};\n\nstruct drm_pending_event {\n\tstruct completion *completion;\n\tvoid (*completion_release)(struct completion *);\n\tstruct drm_event *event;\n\tstruct dma_fence *fence;\n\tstruct drm_file *file_priv;\n\tstruct list_head link;\n\tstruct list_head pending_link;\n};\n\nstruct drm_pending_vblank_event {\n\tstruct drm_pending_event base;\n\tunsigned int pipe;\n\tu64 sequence;\n\tunion {\n\t\tstruct drm_event base;\n\t\tstruct drm_event_vblank vbl;\n\t\tstruct drm_event_crtc_sequence seq;\n\t} event;\n};\n\nstruct kmsg_dump_detail;\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct drm_plane_funcs;\n\nstruct drm_plane_helper_funcs;\n\nstruct drm_plane {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tuint32_t possible_crtcs;\n\tuint32_t *format_types;\n\tunsigned int format_count;\n\tbool format_default;\n\tuint64_t *modifiers;\n\tunsigned int modifier_count;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct drm_framebuffer *old_fb;\n\tconst struct drm_plane_funcs *funcs;\n\tlong: 32;\n\tstruct drm_object_properties properties;\n\tenum drm_plane_type type;\n\tunsigned int index;\n\tconst struct drm_plane_helper_funcs *helper_private;\n\tstruct drm_plane_state *state;\n\tstruct drm_property *alpha_property;\n\tstruct drm_property *zpos_property;\n\tstruct drm_property *rotation_property;\n\tstruct drm_property *blend_mode_property;\n\tstruct drm_property *color_encoding_property;\n\tstruct drm_property *color_range_property;\n\tstruct drm_property *color_pipeline_property;\n\tstruct drm_property *scaling_filter_property;\n\tstruct drm_property *hotspot_x_property;\n\tstruct drm_property *hotspot_y_property;\n\tstruct kmsg_dumper kmsg_panic;\n\tlong: 32;\n};\n\nstruct drm_plane_funcs {\n\tint (*update_plane)(struct drm_plane *, struct drm_crtc *, struct drm_framebuffer *, int, int, unsigned int, unsigned int, uint32_t, uint32_t, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*disable_plane)(struct drm_plane *, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_plane *);\n\tvoid (*reset)(struct drm_plane *);\n\tint (*set_property)(struct drm_plane *, struct drm_property *, uint64_t);\n\tstruct drm_plane_state * (*atomic_duplicate_state)(struct drm_plane *);\n\tvoid (*atomic_destroy_state)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_set_property)(struct drm_plane *, struct drm_plane_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_plane *, const struct drm_plane_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_plane *);\n\tvoid (*early_unregister)(struct drm_plane *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_plane_state *);\n\tbool (*format_mod_supported)(struct drm_plane *, uint32_t, uint64_t);\n\tbool (*format_mod_supported_async)(struct drm_plane *, u32, u64);\n};\n\nstruct drm_scanout_buffer;\n\nstruct drm_plane_helper_funcs {\n\tint (*prepare_fb)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_plane *, struct drm_plane_state *);\n\tint (*begin_fb_access)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*end_fb_access)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_check)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_update)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_plane *, struct drm_atomic_state *);\n\tint (*atomic_async_check)(struct drm_plane *, struct drm_atomic_state *, bool);\n\tvoid (*atomic_async_update)(struct drm_plane *, struct drm_atomic_state *);\n\tint (*get_scanout_buffer)(struct drm_plane *, struct drm_scanout_buffer *);\n\tvoid (*panic_flush)(struct drm_plane *);\n};\n\nstruct drm_plane_size_hint {\n\t__u16 width;\n\t__u16 height;\n};\n\nstruct drm_plane_state {\n\tstruct drm_plane *plane;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *fence;\n\tint32_t crtc_x;\n\tint32_t crtc_y;\n\tuint32_t crtc_w;\n\tuint32_t crtc_h;\n\tuint32_t src_x;\n\tuint32_t src_y;\n\tuint32_t src_h;\n\tuint32_t src_w;\n\tint32_t hotspot_x;\n\tint32_t hotspot_y;\n\tu16 alpha;\n\tuint16_t pixel_blend_mode;\n\tunsigned int rotation;\n\tunsigned int zpos;\n\tunsigned int normalized_zpos;\n\tenum drm_color_encoding color_encoding;\n\tenum drm_color_range color_range;\n\tstruct drm_property_blob *fb_damage_clips;\n\tbool ignore_damage_clips;\n\tstruct drm_rect src;\n\tstruct drm_rect dst;\n\tbool visible;\n\tenum drm_scaling_filter scaling_filter;\n\tstruct drm_colorop *color_pipeline;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n\tbool color_mgmt_changed: 1;\n};\n\nstruct drm_prime_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct drm_prime_member {\n\tstruct dma_buf *dma_buf;\n\tuint32_t handle;\n\tstruct rb_node dmabuf_rb;\n\tstruct rb_node handle_rb;\n};\n\nstruct drm_print_iterator {\n\tvoid *data;\n\tssize_t start;\n\tssize_t remain;\n\tssize_t offset;\n};\n\nstruct va_format;\n\nstruct drm_printer {\n\tvoid (*printfn)(struct drm_printer *, struct va_format *);\n\tvoid (*puts)(struct drm_printer *, const char *);\n\tvoid *arg;\n\tconst void *origin;\n\tconst char *prefix;\n\tstruct {\n\t\tunsigned int series;\n\t\tunsigned int counter;\n\t} line;\n\tenum drm_debug_category category;\n};\n\nstruct drm_private_state_funcs {\n\tstruct drm_private_state * (*atomic_duplicate_state)(struct drm_private_obj *);\n\tvoid (*atomic_destroy_state)(struct drm_private_obj *, struct drm_private_state *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_private_state *);\n};\n\nstruct drm_prop_enum_list {\n\tint type;\n\tconst char *name;\n};\n\nstruct drm_property {\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tuint32_t flags;\n\tchar name[32];\n\tuint32_t num_values;\n\tuint64_t *values;\n\tstruct drm_device *dev;\n\tstruct list_head enum_list;\n};\n\nstruct drm_property_blob {\n\tstruct drm_mode_object base;\n\tstruct drm_device *dev;\n\tstruct list_head head_global;\n\tstruct list_head head_file;\n\tsize_t length;\n\tvoid *data;\n};\n\nstruct drm_property_enum {\n\tuint64_t value;\n\tstruct list_head head;\n\tchar name[32];\n};\n\nstruct drm_scanout_buffer {\n\tconst struct drm_format_info *format;\n\tstruct iosys_map map[4];\n\tstruct page **pages;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int pitch[4];\n\tvoid (*set_pixel)(struct drm_scanout_buffer *, unsigned int, unsigned int, u32);\n\tvoid *private;\n};\n\nstruct ewma_psr_time {\n\tlong unsigned int internal;\n};\n\nstruct drm_self_refresh_data {\n\tstruct drm_crtc *crtc;\n\tstruct delayed_work entry_work;\n\tstruct mutex avg_mutex;\n\tstruct ewma_psr_time entry_avg_ms;\n\tstruct ewma_psr_time exit_avg_ms;\n};\n\nstruct drm_set_client_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_set_client_name {\n\t__u64 name_len;\n\t__u64 name;\n};\n\nstruct drm_set_version {\n\tint drm_di_major;\n\tint drm_di_minor;\n\tint drm_dd_major;\n\tint drm_dd_minor;\n};\n\nstruct drm_shadow_plane_state {\n\tstruct drm_plane_state base;\n\tstruct drm_format_conv_state fmtcnv_state;\n\tstruct iosys_map map[4];\n\tstruct iosys_map data[4];\n};\n\nstruct drm_simple_display_pipe_funcs;\n\nstruct drm_simple_display_pipe {\n\tstruct drm_crtc crtc;\n\tstruct drm_plane plane;\n\tstruct drm_encoder encoder;\n\tstruct drm_connector *connector;\n\tconst struct drm_simple_display_pipe_funcs *funcs;\n\tlong: 32;\n};\n\nstruct drm_simple_display_pipe_funcs {\n\tenum drm_mode_status (*mode_valid)(struct drm_simple_display_pipe *, const struct drm_display_mode *);\n\tvoid (*enable)(struct drm_simple_display_pipe *, struct drm_crtc_state *, struct drm_plane_state *);\n\tvoid (*disable)(struct drm_simple_display_pipe *);\n\tint (*check)(struct drm_simple_display_pipe *, struct drm_plane_state *, struct drm_crtc_state *);\n\tvoid (*update)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*prepare_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*begin_fb_access)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tvoid (*end_fb_access)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*enable_vblank)(struct drm_simple_display_pipe *);\n\tvoid (*disable_vblank)(struct drm_simple_display_pipe *);\n\tvoid (*reset_crtc)(struct drm_simple_display_pipe *);\n\tstruct drm_crtc_state * (*duplicate_crtc_state)(struct drm_simple_display_pipe *);\n\tvoid (*destroy_crtc_state)(struct drm_simple_display_pipe *, struct drm_crtc_state *);\n\tvoid (*reset_plane)(struct drm_simple_display_pipe *);\n\tstruct drm_plane_state * (*duplicate_plane_state)(struct drm_simple_display_pipe *);\n\tvoid (*destroy_plane_state)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n};\n\nstruct drm_stats {\n\tlong unsigned int count;\n\tstruct {\n\t\tlong unsigned int value;\n\t\tenum drm_stat_type type;\n\t} data[15];\n};\n\nstruct drm_syncobj {\n\tstruct kref refcount;\n\tstruct dma_fence *fence;\n\tstruct list_head cb_list;\n\tstruct list_head ev_fd_list;\n\tspinlock_t lock;\n\tstruct file *file;\n};\n\nstruct drm_syncobj_array {\n\t__u64 handles;\n\t__u32 count_handles;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_create {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_syncobj_destroy {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_eventfd {\n\t__u32 handle;\n\t__u32 flags;\n\t__u64 point;\n\t__s32 fd;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n\t__u32 pad;\n\t__u64 point;\n};\n\nstruct drm_syncobj_timeline_array {\n\t__u64 handles;\n\t__u64 points;\n\t__u32 count_handles;\n\t__u32 flags;\n};\n\nstruct drm_syncobj_timeline_wait {\n\t__u64 handles;\n\t__u64 points;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n\t__u64 deadline_nsec;\n};\n\nstruct drm_syncobj_transfer {\n\t__u32 src_handle;\n\t__u32 dst_handle;\n\t__u64 src_point;\n\t__u64 dst_point;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_wait {\n\t__u64 handles;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n\t__u64 deadline_nsec;\n};\n\nstruct drm_tegra_channel_close {\n\t__u32 context;\n\t__u32 padding;\n};\n\nstruct drm_tegra_channel_map {\n\t__u32 context;\n\t__u32 handle;\n\t__u32 flags;\n\t__u32 mapping;\n};\n\nstruct drm_tegra_channel_open {\n\t__u32 host1x_class;\n\t__u32 flags;\n\t__u32 context;\n\t__u32 version;\n\t__u32 capabilities;\n\t__u32 padding;\n};\n\nstruct drm_tegra_submit_syncpt {\n\t__u32 id;\n\t__u32 flags;\n\t__u32 increments;\n\t__u32 value;\n};\n\nstruct drm_tegra_channel_submit {\n\t__u32 context;\n\t__u32 num_bufs;\n\t__u32 num_cmds;\n\t__u32 gather_data_words;\n\t__u64 bufs_ptr;\n\t__u64 cmds_ptr;\n\t__u64 gather_data_ptr;\n\t__u32 syncobj_in;\n\t__u32 syncobj_out;\n\tstruct drm_tegra_submit_syncpt syncpt;\n};\n\nstruct drm_tegra_channel_unmap {\n\t__u32 context;\n\t__u32 mapping;\n};\n\nstruct drm_tegra_cmdbuf {\n\t__u32 handle;\n\t__u32 offset;\n\t__u32 words;\n\t__u32 pad;\n};\n\nstruct drm_tegra_reloc {\n\tstruct {\n\t\t__u32 handle;\n\t\t__u32 offset;\n\t} cmdbuf;\n\tstruct {\n\t\t__u32 handle;\n\t\t__u32 offset;\n\t} target;\n\t__u32 shift;\n\t__u32 pad;\n};\n\nstruct drm_tegra_submit {\n\t__u64 context;\n\t__u32 num_syncpts;\n\t__u32 num_cmdbufs;\n\t__u32 num_relocs;\n\t__u32 num_waitchks;\n\t__u32 waitchk_mask;\n\t__u32 timeout;\n\t__u64 syncpts;\n\t__u64 cmdbufs;\n\t__u64 relocs;\n\t__u64 waitchks;\n\t__u32 fence;\n\t__u32 reserved[5];\n};\n\nstruct drm_tegra_submit_buf {\n\t__u32 mapping;\n\t__u32 flags;\n\tstruct {\n\t\t__u64 target_offset;\n\t\t__u32 gather_offset_words;\n\t\t__u32 shift;\n\t} reloc;\n};\n\nstruct drm_tegra_submit_cmd_gather_uptr {\n\t__u32 words;\n\t__u32 reserved[3];\n};\n\nstruct drm_tegra_submit_cmd_wait_syncpt {\n\t__u32 id;\n\t__u32 value;\n\t__u32 reserved[2];\n};\n\nstruct drm_tegra_submit_cmd {\n\t__u32 type;\n\t__u32 flags;\n\tunion {\n\t\tstruct drm_tegra_submit_cmd_gather_uptr gather_uptr;\n\t\tstruct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;\n\t\t__u32 reserved[4];\n\t};\n};\n\nstruct drm_tegra_syncpoint_allocate {\n\t__u32 id;\n\t__u32 padding;\n};\n\nstruct drm_tegra_syncpoint_wait {\n\t__s64 timeout_ns;\n\t__u32 id;\n\t__u32 threshold;\n\t__u32 value;\n\t__u32 padding;\n};\n\nstruct drm_tegra_syncpt {\n\t__u32 id;\n\t__u32 incrs;\n};\n\nstruct drm_tile_group {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tint id;\n\tu8 group_data[8];\n};\n\nstruct drm_unique {\n\t__kernel_size_t unique_len;\n\tchar *unique;\n};\n\nstruct drm_vblank_crtc_config {\n\tint offdelay_ms;\n\tbool disable_immediate;\n};\n\nstruct drm_vblank_crtc_timer {\n\tstruct hrtimer timer;\n\tspinlock_t interval_lock;\n\tlong: 32;\n\tktime_t interval;\n\tstruct drm_crtc *crtc;\n\tlong: 32;\n};\n\nstruct kthread_worker;\n\nstruct drm_vblank_crtc {\n\tstruct drm_device *dev;\n\twait_queue_head_t queue;\n\tstruct timer_list disable_timer;\n\tseqlock_t seqlock;\n\tlong: 32;\n\tatomic64_t count;\n\tktime_t time;\n\tatomic_t refcount;\n\tu32 last;\n\tu32 max_vblank_count;\n\tunsigned int inmodeset;\n\tunsigned int pipe;\n\tint framedur_ns;\n\tint linedur_ns;\n\tstruct drm_display_mode hwmode;\n\tstruct drm_vblank_crtc_config config;\n\tbool enabled;\n\tstruct kthread_worker *worker;\n\tstruct list_head pending_work;\n\twait_queue_head_t work_wait_queue;\n\tstruct drm_vblank_crtc_timer vblank_timer;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nstruct drm_vblank_work {\n\tstruct kthread_work base;\n\tstruct drm_vblank_crtc *vblank;\n\tu64 count;\n\tint cancelling;\n\tstruct list_head node;\n\tlong: 32;\n};\n\nstruct drm_version {\n\tint version_major;\n\tint version_minor;\n\tint version_patchlevel;\n\t__kernel_size_t name_len;\n\tchar *name;\n\t__kernel_size_t date_len;\n\tchar *date;\n\t__kernel_size_t desc_len;\n\tchar *desc;\n};\n\nstruct drm_vma_offset_file {\n\tstruct rb_node vm_rb;\n\tstruct drm_file *vm_tag;\n\tlong unsigned int vm_count;\n};\n\nstruct drm_vma_offset_manager {\n\trwlock_t vm_lock;\n\tlong: 32;\n\tstruct drm_mm vm_addr_space_mm;\n};\n\nstruct drm_wait_vblank_request {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong unsigned int signal;\n};\n\nstruct drm_wait_vblank_reply {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong int tval_sec;\n\tlong int tval_usec;\n};\n\nunion drm_wait_vblank {\n\tstruct drm_wait_vblank_request request;\n\tstruct drm_wait_vblank_reply reply;\n};\n\nstruct drm_wedge_task_info {\n\tpid_t pid;\n\tchar comm[16];\n};\n\nstruct drm_writeback_connector {\n\tstruct drm_connector base;\n\tstruct drm_encoder encoder;\n\tstruct drm_property_blob *pixel_formats_blob_ptr;\n\tspinlock_t job_lock;\n\tstruct list_head job_queue;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n};\n\nstruct drm_writeback_job {\n\tstruct drm_writeback_connector *connector;\n\tbool prepared;\n\tstruct work_struct cleanup_work;\n\tstruct list_head list_entry;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *out_fence;\n\tvoid *priv;\n};\n\ntypedef void (*drmres_release_t)(struct drm_device *, void *);\n\nstruct drmres_node {\n\tstruct list_head entry;\n\tdrmres_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct drmres {\n\tstruct drmres_node node;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu8 data[0];\n};\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct pci_driver;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct ds1307 {\n\tenum ds_type type;\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tconst char *name;\n\tstruct rtc_device *rtc;\n\tstruct clk_hw clks[2];\n};\n\nstruct ds1307_platform_data {\n\tu8 trickle_charger_setup;\n};\n\nstruct dsa_bridge {\n\tstruct net_device *dev;\n\tunsigned int num;\n\tbool tx_fwd_offload;\n\trefcount_t refcount;\n};\n\nstruct dsa_chip_data {\n\tstruct device *host_dev;\n\tint sw_addr;\n\tstruct device *netdev[12];\n\tint eeprom_len;\n\tstruct device_node *of_node;\n\tchar *port_names[12];\n\tstruct device_node *port_dn[12];\n\ts8 rtable[4];\n};\n\nstruct dsa_lag {\n\tstruct net_device *dev;\n\tunsigned int id;\n\tstruct mutex fdb_lock;\n\tstruct list_head fdbs;\n\trefcount_t refcount;\n};\n\nstruct dsa_port;\n\nstruct dsa_db {\n\tenum dsa_db_type type;\n\tunion {\n\t\tconst struct dsa_port *dp;\n\t\tstruct dsa_lag lag;\n\t\tstruct dsa_bridge bridge;\n\t};\n};\n\nstruct dsa_switch;\n\nstruct dsa_device_ops {\n\tstruct sk_buff * (*xmit)(struct sk_buff *, struct net_device *);\n\tstruct sk_buff * (*rcv)(struct sk_buff *, struct net_device *);\n\tvoid (*flow_dissect)(const struct sk_buff *, __be16 *, int *);\n\tint (*connect)(struct dsa_switch *);\n\tvoid (*disconnect)(struct dsa_switch *);\n\tunsigned int needed_headroom;\n\tunsigned int needed_tailroom;\n\tconst char *name;\n\tenum dsa_tag_protocol proto;\n\tbool promisc_on_conduit;\n};\n\nstruct dsa_mall_mirror_tc_entry {\n\tu8 to_local_port;\n\tbool ingress;\n};\n\nstruct dsa_platform_data {\n\tstruct device *netdev;\n\tstruct net_device *of_netdev;\n\tint nr_chips;\n\tstruct dsa_chip_data *chip;\n};\n\nstruct dsa_switch_tree;\n\nstruct ethtool_ops;\n\nstruct dsa_port {\n\tunion {\n\t\tstruct net_device *conduit;\n\t\tstruct net_device *user;\n\t};\n\tconst struct dsa_device_ops *tag_ops;\n\tstruct dsa_switch_tree *dst;\n\tstruct sk_buff * (*rcv)(struct sk_buff *, struct net_device *);\n\tstruct dsa_switch *ds;\n\tunsigned int index;\n\tenum {\n\t\tDSA_PORT_TYPE_UNUSED = 0,\n\t\tDSA_PORT_TYPE_CPU = 1,\n\t\tDSA_PORT_TYPE_DSA = 2,\n\t\tDSA_PORT_TYPE_USER = 3,\n\t} type;\n\tconst char *name;\n\tstruct dsa_port *cpu_dp;\n\tu8 mac[6];\n\tu8 stp_state;\n\tu8 vlan_filtering: 1;\n\tu8 learning: 1;\n\tu8 lag_tx_enabled: 1;\n\tu8 conduit_admin_up: 1;\n\tu8 conduit_oper_up: 1;\n\tu8 cpu_port_in_lag: 1;\n\tu8 setup: 1;\n\tstruct device_node *dn;\n\tunsigned int ageing_time;\n\tstruct dsa_bridge *bridge;\n\tstruct devlink_port devlink_port;\n\tstruct phylink *pl;\n\tstruct phylink_config pl_config;\n\tnetdevice_tracker conduit_tracker;\n\tstruct dsa_lag *lag;\n\tstruct net_device *hsr_dev;\n\tstruct list_head list;\n\tconst struct ethtool_ops *orig_ethtool_ops;\n\tstruct mutex addr_lists_lock;\n\tstruct list_head fdbs;\n\tstruct list_head mdbs;\n\tstruct mutex vlans_lock;\n\tunion {\n\t\tstruct list_head vlans;\n\t\tstruct list_head user_vlans;\n\t};\n};\n\nstruct kernel_hwtstamp_config;\n\nstruct dsa_stubs {\n\tint (*conduit_hwtstamp_validate)(struct net_device *, const struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct dsa_8021q_context;\n\nstruct dsa_switch_ops;\n\nstruct phylink_mac_ops;\n\nstruct dsa_switch {\n\tstruct device *dev;\n\tstruct dsa_switch_tree *dst;\n\tunsigned int index;\n\tu32 setup: 1;\n\tu32 vlan_filtering_is_global: 1;\n\tu32 needs_standalone_vlan_filtering: 1;\n\tu32 configure_vlan_while_not_filtering: 1;\n\tu32 untag_bridge_pvid: 1;\n\tu32 untag_vlan_aware_bridge_pvid: 1;\n\tu32 assisted_learning_on_cpu_port: 1;\n\tu32 vlan_filtering: 1;\n\tu32 mtu_enforcement_ingress: 1;\n\tu32 fdb_isolation: 1;\n\tu32 dscp_prio_mapping_is_global: 1;\n\tstruct notifier_block nb;\n\tvoid *priv;\n\tvoid *tagger_data;\n\tstruct dsa_chip_data *cd;\n\tconst struct dsa_switch_ops *ops;\n\tconst struct phylink_mac_ops *phylink_mac_ops;\n\tu32 phys_mii_mask;\n\tstruct mii_bus *user_mii_bus;\n\tunsigned int ageing_time_min;\n\tunsigned int ageing_time_max;\n\tstruct dsa_8021q_context *tag_8021q_ctx;\n\tstruct devlink *devlink;\n\tunsigned int num_tx_queues;\n\tunsigned int num_lag_ids;\n\tunsigned int max_num_bridges;\n\tunsigned int num_ports;\n};\n\ntypedef int dsa_fdb_dump_cb_t(const unsigned char *, u16, bool, void *);\n\nstruct ethtool_eth_phy_stats;\n\nstruct ethtool_eth_mac_stats;\n\nstruct ethtool_eth_ctrl_stats;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ts_stats;\n\nstruct rtnl_link_stats64;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_test;\n\nstruct ethtool_wolinfo;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_mm_state;\n\nstruct ethtool_mm_cfg;\n\nstruct ethtool_mm_stats;\n\nstruct ethtool_keee;\n\nstruct ethtool_eeprom;\n\nstruct ethtool_regs;\n\nstruct netdev_notifier_changeupper_info;\n\nstruct switchdev_mst_state;\n\nstruct switchdev_brport_flags;\n\nstruct switchdev_obj_port_vlan;\n\nstruct switchdev_vlan_msti;\n\nstruct switchdev_obj_port_mdb;\n\nstruct ethtool_rxnfc;\n\nstruct flow_cls_offload;\n\nstruct flow_action_police;\n\nstruct netdev_lag_upper_info;\n\nstruct switchdev_obj_mrp;\n\nstruct switchdev_obj_ring_role_mrp;\n\nstruct dsa_switch_ops {\n\tenum dsa_tag_protocol (*get_tag_protocol)(struct dsa_switch *, int, enum dsa_tag_protocol);\n\tint (*change_tag_protocol)(struct dsa_switch *, enum dsa_tag_protocol);\n\tint (*connect_tag_protocol)(struct dsa_switch *, enum dsa_tag_protocol);\n\tint (*port_change_conduit)(struct dsa_switch *, int, struct net_device *, struct netlink_ext_ack *);\n\tint (*setup)(struct dsa_switch *);\n\tvoid (*teardown)(struct dsa_switch *);\n\tint (*port_setup)(struct dsa_switch *, int);\n\tvoid (*port_teardown)(struct dsa_switch *, int);\n\tu32 (*get_phy_flags)(struct dsa_switch *, int);\n\tint (*phy_read)(struct dsa_switch *, int, int);\n\tint (*phy_write)(struct dsa_switch *, int, int, u16);\n\tvoid (*phylink_get_caps)(struct dsa_switch *, int, struct phylink_config *);\n\tvoid (*phylink_fixed_state)(struct dsa_switch *, int, struct phylink_link_state *);\n\tvoid (*get_strings)(struct dsa_switch *, int, u32, uint8_t *);\n\tvoid (*get_ethtool_stats)(struct dsa_switch *, int, uint64_t *);\n\tint (*get_sset_count)(struct dsa_switch *, int, int);\n\tvoid (*get_ethtool_phy_stats)(struct dsa_switch *, int, uint64_t *);\n\tvoid (*get_eth_phy_stats)(struct dsa_switch *, int, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct dsa_switch *, int, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct dsa_switch *, int, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct dsa_switch *, int, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tvoid (*get_ts_stats)(struct dsa_switch *, int, struct ethtool_ts_stats *);\n\tvoid (*get_stats64)(struct dsa_switch *, int, struct rtnl_link_stats64 *);\n\tvoid (*get_pause_stats)(struct dsa_switch *, int, struct ethtool_pause_stats *);\n\tvoid (*self_test)(struct dsa_switch *, int, struct ethtool_test *, u64 *);\n\tvoid (*get_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *);\n\tint (*get_ts_info)(struct dsa_switch *, int, struct kernel_ethtool_ts_info *);\n\tint (*get_mm)(struct dsa_switch *, int, struct ethtool_mm_state *);\n\tint (*set_mm)(struct dsa_switch *, int, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct dsa_switch *, int, struct ethtool_mm_stats *);\n\tint (*port_get_default_prio)(struct dsa_switch *, int);\n\tint (*port_set_default_prio)(struct dsa_switch *, int, u8);\n\tint (*port_get_dscp_prio)(struct dsa_switch *, int, u8);\n\tint (*port_add_dscp_prio)(struct dsa_switch *, int, u8, u8);\n\tint (*port_del_dscp_prio)(struct dsa_switch *, int, u8, u8);\n\tint (*port_set_apptrust)(struct dsa_switch *, int, const u8 *, int);\n\tint (*port_get_apptrust)(struct dsa_switch *, int, u8 *, int *);\n\tint (*suspend)(struct dsa_switch *);\n\tint (*resume)(struct dsa_switch *);\n\tint (*port_enable)(struct dsa_switch *, int, struct phy_device *);\n\tvoid (*port_disable)(struct dsa_switch *, int);\n\tint (*port_set_mac_address)(struct dsa_switch *, int, const unsigned char *);\n\tstruct dsa_port * (*preferred_default_local_cpu_port)(struct dsa_switch *);\n\tbool (*support_eee)(struct dsa_switch *, int);\n\tint (*set_mac_eee)(struct dsa_switch *, int, struct ethtool_keee *);\n\tint (*get_eeprom_len)(struct dsa_switch *);\n\tint (*get_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *);\n\tint (*get_regs_len)(struct dsa_switch *, int);\n\tvoid (*get_regs)(struct dsa_switch *, int, struct ethtool_regs *, void *);\n\tint (*port_prechangeupper)(struct dsa_switch *, int, struct netdev_notifier_changeupper_info *);\n\tint (*set_ageing_time)(struct dsa_switch *, unsigned int);\n\tint (*port_bridge_join)(struct dsa_switch *, int, struct dsa_bridge, bool *, struct netlink_ext_ack *);\n\tvoid (*port_bridge_leave)(struct dsa_switch *, int, struct dsa_bridge);\n\tvoid (*port_stp_state_set)(struct dsa_switch *, int, u8);\n\tint (*port_mst_state_set)(struct dsa_switch *, int, const struct switchdev_mst_state *);\n\tvoid (*port_fast_age)(struct dsa_switch *, int);\n\tint (*port_vlan_fast_age)(struct dsa_switch *, int, u16);\n\tint (*port_pre_bridge_flags)(struct dsa_switch *, int, struct switchdev_brport_flags, struct netlink_ext_ack *);\n\tint (*port_bridge_flags)(struct dsa_switch *, int, struct switchdev_brport_flags, struct netlink_ext_ack *);\n\tvoid (*port_set_host_flood)(struct dsa_switch *, int, bool, bool);\n\tint (*port_vlan_filtering)(struct dsa_switch *, int, bool, struct netlink_ext_ack *);\n\tint (*port_vlan_add)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *, struct netlink_ext_ack *);\n\tint (*port_vlan_del)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *);\n\tint (*vlan_msti_set)(struct dsa_switch *, struct dsa_bridge, const struct switchdev_vlan_msti *);\n\tint (*port_fdb_add)(struct dsa_switch *, int, const unsigned char *, u16, struct dsa_db);\n\tint (*port_fdb_del)(struct dsa_switch *, int, const unsigned char *, u16, struct dsa_db);\n\tint (*port_fdb_dump)(struct dsa_switch *, int, dsa_fdb_dump_cb_t *, void *);\n\tint (*lag_fdb_add)(struct dsa_switch *, struct dsa_lag, const unsigned char *, u16, struct dsa_db);\n\tint (*lag_fdb_del)(struct dsa_switch *, struct dsa_lag, const unsigned char *, u16, struct dsa_db);\n\tint (*port_mdb_add)(struct dsa_switch *, int, const struct switchdev_obj_port_mdb *, struct dsa_db);\n\tint (*port_mdb_del)(struct dsa_switch *, int, const struct switchdev_obj_port_mdb *, struct dsa_db);\n\tint (*get_rxnfc)(struct dsa_switch *, int, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct dsa_switch *, int, struct ethtool_rxnfc *);\n\tint (*cls_flower_add)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*cls_flower_del)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*cls_flower_stats)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*port_mirror_add)(struct dsa_switch *, int, struct dsa_mall_mirror_tc_entry *, bool, struct netlink_ext_ack *);\n\tvoid (*port_mirror_del)(struct dsa_switch *, int, struct dsa_mall_mirror_tc_entry *);\n\tint (*port_policer_add)(struct dsa_switch *, int, const struct flow_action_police *);\n\tvoid (*port_policer_del)(struct dsa_switch *, int);\n\tint (*port_setup_tc)(struct dsa_switch *, int, enum tc_setup_type, void *);\n\tint (*crosschip_bridge_join)(struct dsa_switch *, int, int, int, struct dsa_bridge, struct netlink_ext_ack *);\n\tvoid (*crosschip_bridge_leave)(struct dsa_switch *, int, int, int, struct dsa_bridge);\n\tint (*crosschip_lag_change)(struct dsa_switch *, int, int);\n\tint (*crosschip_lag_join)(struct dsa_switch *, int, int, struct dsa_lag, struct netdev_lag_upper_info *, struct netlink_ext_ack *);\n\tint (*crosschip_lag_leave)(struct dsa_switch *, int, int, struct dsa_lag);\n\tint (*port_hwtstamp_get)(struct dsa_switch *, int, struct kernel_hwtstamp_config *);\n\tint (*port_hwtstamp_set)(struct dsa_switch *, int, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*port_txtstamp)(struct dsa_switch *, int, struct sk_buff *);\n\tbool (*port_rxtstamp)(struct dsa_switch *, int, struct sk_buff *, unsigned int);\n\tint (*devlink_param_get)(struct dsa_switch *, u32, struct devlink_param_gset_ctx *);\n\tint (*devlink_param_set)(struct dsa_switch *, u32, struct devlink_param_gset_ctx *);\n\tint (*devlink_info_get)(struct dsa_switch *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*devlink_sb_pool_get)(struct dsa_switch *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*devlink_sb_pool_set)(struct dsa_switch *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*devlink_sb_port_pool_get)(struct dsa_switch *, int, unsigned int, u16, u32 *);\n\tint (*devlink_sb_port_pool_set)(struct dsa_switch *, int, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*devlink_sb_tc_pool_bind_get)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*devlink_sb_tc_pool_bind_set)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*devlink_sb_occ_snapshot)(struct dsa_switch *, unsigned int);\n\tint (*devlink_sb_occ_max_clear)(struct dsa_switch *, unsigned int);\n\tint (*devlink_sb_occ_port_pool_get)(struct dsa_switch *, int, unsigned int, u16, u32 *, u32 *);\n\tint (*devlink_sb_occ_tc_port_bind_get)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*port_change_mtu)(struct dsa_switch *, int, int);\n\tint (*port_max_mtu)(struct dsa_switch *, int);\n\tint (*port_lag_change)(struct dsa_switch *, int);\n\tint (*port_lag_join)(struct dsa_switch *, int, struct dsa_lag, struct netdev_lag_upper_info *, struct netlink_ext_ack *);\n\tint (*port_lag_leave)(struct dsa_switch *, int, struct dsa_lag);\n\tint (*port_hsr_join)(struct dsa_switch *, int, struct net_device *, struct netlink_ext_ack *);\n\tint (*port_hsr_leave)(struct dsa_switch *, int, struct net_device *);\n\tint (*port_mrp_add)(struct dsa_switch *, int, const struct switchdev_obj_mrp *);\n\tint (*port_mrp_del)(struct dsa_switch *, int, const struct switchdev_obj_mrp *);\n\tint (*port_mrp_add_ring_role)(struct dsa_switch *, int, const struct switchdev_obj_ring_role_mrp *);\n\tint (*port_mrp_del_ring_role)(struct dsa_switch *, int, const struct switchdev_obj_ring_role_mrp *);\n\tint (*tag_8021q_vlan_add)(struct dsa_switch *, int, u16, u16);\n\tint (*tag_8021q_vlan_del)(struct dsa_switch *, int, u16);\n\tvoid (*conduit_state_change)(struct dsa_switch *, const struct net_device *, bool);\n};\n\nstruct dsa_switch_tree {\n\tstruct list_head list;\n\tstruct list_head ports;\n\tstruct raw_notifier_head nh;\n\tunsigned int index;\n\tstruct kref refcount;\n\tstruct dsa_lag **lags;\n\tconst struct dsa_device_ops *tag_ops;\n\tenum dsa_tag_protocol default_proto;\n\tbool setup;\n\tstruct dsa_platform_data *pd;\n\tstruct list_head rtable;\n\tunsigned int lags_len;\n\tunsigned int last_switch;\n};\n\nstruct dsiclk {\n\tu32 divsel_mask;\n\tu32 divsel_shift;\n\tu32 divsel;\n};\n\nstruct dsiescclk {\n\tu32 en;\n\tu32 div_mask;\n\tu32 div_shift;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tlocal_lock_t bh_lock;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct dst_ops;\n\nstruct xfrm_state;\n\nstruct lwtunnel_state;\n\nstruct uncached_list;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tstruct xfrm_state *xfrm;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tstruct lwtunnel_state *lwtstate;\n\trcuref_t __rcuref;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct dw8250_port_data {\n\tint line;\n\tstruct uart_8250_dma dma;\n\tu32 cpr_value;\n\tu8 dlf_size;\n\tbool hw_rs485_support;\n};\n\nstruct dw8250_platform_data;\n\nstruct dw8250_data {\n\tstruct dw8250_port_data data;\n\tconst struct dw8250_platform_data *pdata;\n\tu32 msr_mask_on;\n\tu32 msr_mask_off;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_notifier;\n\tstruct work_struct clk_work;\n\tstruct reset_control *rst;\n\tunsigned int skip_autocfg: 1;\n\tunsigned int uart_16550_compatible: 1;\n};\n\nstruct dw8250_platform_data {\n\tu8 usr_reg;\n\tu32 cpr_value;\n\tunsigned int quirks;\n};\n\nstruct dw_apb_timer {\n\tvoid *base;\n\tlong unsigned int freq;\n\tint irq;\n};\n\nstruct dw_apb_clock_event_device {\n\tstruct clock_event_device ced;\n\tstruct dw_apb_timer timer;\n\tvoid (*eoi)(struct dw_apb_timer *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct dw_apb_clocksource {\n\tstruct dw_apb_timer timer;\n\tlong: 32;\n\tstruct clocksource cs;\n};\n\nstruct dw_lli {\n\t__le32 sar;\n\t__le32 dar;\n\t__le32 llp;\n\t__le32 ctllo;\n\t__le32 ctlhi;\n\t__le32 sstat;\n\t__le32 dstat;\n};\n\nstruct dw_desc {\n\tstruct dw_lli lli;\n\tstruct list_head desc_node;\n\tstruct list_head tx_list;\n\tstruct dma_async_tx_descriptor txd;\n\tsize_t len;\n\tsize_t total_len;\n\tu32 residue;\n};\n\nstruct dw_dma_chan;\n\nstruct dw_dma_platform_data;\n\nstruct dw_dma {\n\tstruct dma_device dma;\n\tchar name[20];\n\tvoid *regs;\n\tstruct dma_pool *desc_pool;\n\tstruct tasklet_struct tasklet;\n\tstruct dw_dma_chan *chan;\n\tu8 all_chan_mask;\n\tu8 in_use;\n\tvoid (*initialize_chan)(struct dw_dma_chan *);\n\tvoid (*suspend_chan)(struct dw_dma_chan *, bool);\n\tvoid (*resume_chan)(struct dw_dma_chan *, bool);\n\tu32 (*prepare_ctllo)(struct dw_dma_chan *);\n\tu32 (*bytes2block)(struct dw_dma_chan *, size_t, unsigned int, size_t *);\n\tsize_t (*block2bytes)(struct dw_dma_chan *, u32, u32);\n\tvoid (*set_device_name)(struct dw_dma *, int);\n\tvoid (*disable)(struct dw_dma *);\n\tvoid (*enable)(struct dw_dma *);\n\tstruct dw_dma_platform_data *pdata;\n};\n\nstruct dw_dma_slave {\n\tstruct device *dma_dev;\n\tu8 src_id;\n\tu8 dst_id;\n\tu8 m_master;\n\tu8 p_master;\n\tu8 channels;\n\tbool hs_polarity;\n};\n\nstruct dw_dma_chan {\n\tstruct dma_chan chan;\n\tvoid *ch_regs;\n\tu8 mask;\n\tu8 priority;\n\tenum dma_transfer_direction direction;\n\tstruct list_head *tx_node_active;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tstruct list_head active_list;\n\tstruct list_head queue;\n\tunsigned int descs_allocated;\n\tunsigned int block_size;\n\tbool nollp;\n\tu32 max_burst;\n\tstruct dw_dma_slave dws;\n\tstruct dma_slave_config dma_sconfig;\n};\n\nstruct dw_dma_chan_regs {\n\tu32 SAR;\n\tu32 __pad_SAR;\n\tu32 DAR;\n\tu32 __pad_DAR;\n\tu32 LLP;\n\tu32 __pad_LLP;\n\tu32 CTL_LO;\n\tu32 CTL_HI;\n\tu32 SSTAT;\n\tu32 __pad_SSTAT;\n\tu32 DSTAT;\n\tu32 __pad_DSTAT;\n\tu32 SSTATAR;\n\tu32 __pad_SSTATAR;\n\tu32 DSTATAR;\n\tu32 __pad_DSTATAR;\n\tu32 CFG_LO;\n\tu32 CFG_HI;\n\tu32 SGR;\n\tu32 __pad_SGR;\n\tu32 DSR;\n\tu32 __pad_DSR;\n};\n\nstruct dw_dma_chip {\n\tstruct device *dev;\n\tint id;\n\tint irq;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct dw_dma *dw;\n\tconst struct dw_dma_platform_data *pdata;\n};\n\nstruct dw_dma_chip_pdata {\n\tconst struct dw_dma_platform_data *pdata;\n\tint (*probe)(struct dw_dma_chip *);\n\tint (*remove)(struct dw_dma_chip *);\n\tstruct dw_dma_chip *chip;\n\tu8 m_master;\n\tu8 p_master;\n};\n\nstruct dw_dma_irq_regs {\n\tu32 XFER;\n\tu32 __pad_XFER;\n\tu32 BLOCK;\n\tu32 __pad_BLOCK;\n\tu32 SRC_TRAN;\n\tu32 __pad_SRC_TRAN;\n\tu32 DST_TRAN;\n\tu32 __pad_DST_TRAN;\n\tu32 ERROR;\n\tu32 __pad_ERROR;\n};\n\nstruct dw_dma_platform_data {\n\tu32 nr_masters;\n\tu32 nr_channels;\n\tu32 chan_allocation_order;\n\tu32 chan_priority;\n\tu32 block_size;\n\tu32 data_width[4];\n\tu32 multi_block[8];\n\tu32 max_burst[8];\n\tu32 protctl;\n\tu32 quirks;\n};\n\nstruct dw_dma_regs {\n\tstruct dw_dma_chan_regs CHAN[8];\n\tstruct dw_dma_irq_regs RAW;\n\tstruct dw_dma_irq_regs STATUS;\n\tstruct dw_dma_irq_regs MASK;\n\tstruct dw_dma_irq_regs CLEAR;\n\tu32 STATUS_INT;\n\tu32 __pad_STATUS_INT;\n\tu32 REQ_SRC;\n\tu32 __pad_REQ_SRC;\n\tu32 REQ_DST;\n\tu32 __pad_REQ_DST;\n\tu32 SGL_REQ_SRC;\n\tu32 __pad_SGL_REQ_SRC;\n\tu32 SGL_REQ_DST;\n\tu32 __pad_SGL_REQ_DST;\n\tu32 LAST_SRC;\n\tu32 __pad_LAST_SRC;\n\tu32 LAST_DST;\n\tu32 __pad_LAST_DST;\n\tu32 CFG;\n\tu32 __pad_CFG;\n\tu32 CH_EN;\n\tu32 __pad_CH_EN;\n\tu32 ID;\n\tu32 __pad_ID;\n\tu32 TEST;\n\tu32 __pad_TEST;\n\tu32 CLASS_PRIORITY0;\n\tu32 __pad_CLASS_PRIORITY0;\n\tu32 CLASS_PRIORITY1;\n\tu32 __pad_CLASS_PRIORITY1;\n\tu32 __reserved;\n\tu32 DWC_PARAMS[8];\n\tu32 MULTI_BLK_TYPE;\n\tu32 MAX_BLK_SIZE;\n\tu32 DW_PARAMS;\n\tu32 COMP_TYPE;\n\tu32 COMP_VERSION;\n\tu32 FIFO_PARTITION0;\n\tu32 __pad_FIFO_PARTITION0;\n\tu32 FIFO_PARTITION1;\n\tu32 __pad_FIFO_PARTITION1;\n\tu32 SAI_ERR;\n\tu32 __pad_SAI_ERR;\n\tu32 GLOBAL_CFG;\n\tu32 __pad_GLOBAL_CFG;\n};\n\nstruct dw_edma_region {\n\tu64 paddr;\n\tunion {\n\t\tvoid *mem;\n\t\tvoid *io;\n\t} vaddr;\n\tsize_t sz;\n};\n\nstruct dw_edma;\n\nstruct dw_edma_plat_ops;\n\nstruct dw_edma_chip {\n\tstruct device *dev;\n\tint nr_irqs;\n\tconst struct dw_edma_plat_ops *ops;\n\tu32 flags;\n\tvoid *reg_base;\n\tu16 ll_wr_cnt;\n\tu16 ll_rd_cnt;\n\tstruct dw_edma_region ll_region_wr[8];\n\tstruct dw_edma_region ll_region_rd[8];\n\tstruct dw_edma_region dt_region_wr[8];\n\tstruct dw_edma_region dt_region_rd[8];\n\tenum dw_edma_map_format mf;\n\tstruct dw_edma *dw;\n};\n\nstruct dw_edma_plat_ops {\n\tint (*irq_vector)(struct device *, unsigned int);\n\tu64 (*pci_address)(struct device *, phys_addr_t);\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct dw_i2c_dev {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct regmap *sysmap;\n\tvoid *base;\n\tvoid *ext;\n\tstruct completion cmd_complete;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct reset_control *rst;\n\tstruct i2c_client *slave;\n\tu32 (*get_clk_rate_khz)(struct dw_i2c_dev *);\n\tint cmd_err;\n\tstruct i2c_msg *msgs;\n\tint msgs_num;\n\tint msg_write_idx;\n\tu32 tx_buf_len;\n\tu8 *tx_buf;\n\tint msg_read_idx;\n\tu32 rx_buf_len;\n\tu8 *rx_buf;\n\tint msg_err;\n\tunsigned int status;\n\tunsigned int abort_source;\n\tunsigned int sw_mask;\n\tint irq;\n\tu32 flags;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tu32 functionality;\n\tu32 master_cfg;\n\tu32 slave_cfg;\n\tunsigned int tx_fifo_depth;\n\tunsigned int rx_fifo_depth;\n\tint rx_outstanding;\n\tstruct i2c_timings timings;\n\tu32 sda_hold_time;\n\tu16 ss_hcnt;\n\tu16 ss_lcnt;\n\tu16 fs_hcnt;\n\tu16 fs_lcnt;\n\tu16 fp_hcnt;\n\tu16 fp_lcnt;\n\tu16 hs_hcnt;\n\tu16 hs_lcnt;\n\tint (*acquire_lock)(void);\n\tvoid (*release_lock)(void);\n\tint semaphore_idx;\n\tbool shared_with_punit;\n\tint (*set_sda_hold_time)(struct dw_i2c_dev *);\n\tint mode;\n\tstruct i2c_bus_recovery_info rinfo;\n\tu32 bus_capacitance_pF;\n\tbool clk_freq_optimized;\n\tbool emptyfifo_hold_master;\n};\n\nstruct uhs2_command;\n\nstruct mmc_command {\n\tu32 opcode;\n\tu32 arg;\n\tu32 resp[4];\n\tunsigned int flags;\n\tunsigned int retries;\n\tint error;\n\tunsigned int busy_timeout;\n\tstruct mmc_data *data;\n\tstruct mmc_request *mrq;\n\tstruct uhs2_command *uhs2_cmd;\n\tbool has_ext_addr;\n\tu8 ext_addr;\n};\n\nstruct dw_mci_dma_ops;\n\nstruct dw_mci_dma_slave;\n\nstruct dw_mci_board;\n\nstruct dw_mci_drv_data;\n\nstruct dw_mci_slot;\n\nstruct dw_mci {\n\tspinlock_t lock;\n\tspinlock_t irq_lock;\n\tvoid *regs;\n\tvoid *fifo_reg;\n\tu32 data_addr_override;\n\tbool wm_aligned;\n\tstruct scatterlist *sg;\n\tstruct sg_mapping_iter sg_miter;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command stop_abort;\n\tunsigned int prev_blksz;\n\tunsigned char timing;\n\tint use_dma;\n\tint using_dma;\n\tint dma_64bit_address;\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tconst struct dw_mci_dma_ops *dma_ops;\n\tunsigned int ring_size;\n\tstruct dw_mci_dma_slave *dms;\n\tresource_size_t phy_regs;\n\tu32 cmd_status;\n\tu32 data_status;\n\tu32 stop_cmdr;\n\tu32 dir_status;\n\tstruct work_struct bh_work;\n\tlong unsigned int pending_events;\n\tlong unsigned int completed_events;\n\tenum dw_mci_state state;\n\tstruct list_head queue;\n\tu32 bus_hz;\n\tu32 current_speed;\n\tu32 minimum_speed;\n\tu32 fifoth_val;\n\tu16 verid;\n\tstruct device *dev;\n\tstruct dw_mci_board *pdata;\n\tconst struct dw_mci_drv_data *drv_data;\n\tvoid *priv;\n\tstruct clk *biu_clk;\n\tstruct clk *ciu_clk;\n\tstruct dw_mci_slot *slot;\n\tint fifo_depth;\n\tint data_shift;\n\tu8 part_buf_start;\n\tu8 part_buf_count;\n\tunion {\n\t\tu16 part_buf16;\n\t\tu32 part_buf32;\n\t\tu64 part_buf;\n\t};\n\tvoid (*push_data)(struct dw_mci *, void *, int);\n\tvoid (*pull_data)(struct dw_mci *, void *, int);\n\tu32 quirks;\n\tbool vqmmc_enabled;\n\tlong unsigned int irq_flags;\n\tint irq;\n\tint sdio_id0;\n\tstruct timer_list cmd11_timer;\n\tstruct timer_list cto_timer;\n\tstruct timer_list dto_timer;\n};\n\nstruct dma_pdata;\n\nstruct dw_mci_board {\n\tunsigned int bus_hz;\n\tu32 caps;\n\tu32 caps2;\n\tu32 pm_caps;\n\tunsigned int fifo_depth;\n\tu32 detect_delay_ms;\n\tstruct reset_control *rstc;\n\tstruct dw_mci_dma_ops *dma_ops;\n\tstruct dma_pdata *data;\n};\n\nstruct dw_mci_dma_ops {\n\tint (*init)(struct dw_mci *);\n\tint (*start)(struct dw_mci *, unsigned int);\n\tvoid (*complete)(void *);\n\tvoid (*stop)(struct dw_mci *);\n\tvoid (*cleanup)(struct dw_mci *);\n\tvoid (*exit)(struct dw_mci *);\n};\n\nstruct dw_mci_dma_slave {\n\tstruct dma_chan *ch;\n\tenum dma_transfer_direction direction;\n};\n\nstruct dw_mci_drv_data {\n\tlong unsigned int *caps;\n\tu32 num_caps;\n\tu32 common_caps;\n\tint (*init)(struct dw_mci *);\n\tvoid (*set_ios)(struct dw_mci *, struct mmc_ios *);\n\tint (*parse_dt)(struct dw_mci *);\n\tint (*execute_tuning)(struct dw_mci_slot *, u32);\n\tint (*prepare_hs400_tuning)(struct dw_mci *, struct mmc_ios *);\n\tint (*switch_voltage)(struct mmc_host *, struct mmc_ios *);\n\tvoid (*set_data_timeout)(struct dw_mci *, unsigned int);\n\tu32 (*get_drto_clks)(struct dw_mci *);\n\tvoid (*hw_reset)(struct dw_mci *);\n};\n\nstruct dw_mci_exynos_compatible {\n\tchar *compatible;\n\tenum dw_mci_exynos_type ctrl_type;\n};\n\nstruct dw_mci_exynos_priv_data {\n\tenum dw_mci_exynos_type ctrl_type;\n\tu8 ciu_div;\n\tu32 sdr_timing;\n\tu32 ddr_timing;\n\tu32 hs400_timing;\n\tu32 tuned_sample;\n\tu32 cur_speed;\n\tu32 dqs_delay;\n\tu32 saved_dqs_en;\n\tu32 saved_strobe_ctrl;\n};\n\nstruct dw_mci_rockchip_priv_data {\n\tstruct clk *drv_clk;\n\tstruct clk *sample_clk;\n\tint default_sample_phase;\n\tint num_phases;\n\tbool internal_phase;\n\tint sample_phase;\n\tint drv_phase;\n};\n\nstruct dw_mci_slot {\n\tstruct mmc_host *mmc;\n\tstruct dw_mci *host;\n\tu32 ctype;\n\tstruct mmc_request *mrq;\n\tstruct list_head queue_node;\n\tunsigned int clock;\n\tunsigned int __clk_old;\n\tlong unsigned int flags;\n\tint id;\n\tint sdio_id;\n};\n\nstruct pci_eq_presets {\n\tu16 eq_presets_8gts[16];\n\tu8 eq_presets_Ngts[48];\n};\n\nstruct dw_pcie_host_ops;\n\nstruct pci_host_bridge;\n\nstruct pci_config_window;\n\nstruct dw_pcie_rp {\n\tbool use_imsi_rx: 1;\n\tbool cfg0_io_shared: 1;\n\tlong: 32;\n\tu64 cfg0_base;\n\tvoid *va_cfg0_base;\n\tu32 cfg0_size;\n\tresource_size_t io_base;\n\tphys_addr_t io_bus_addr;\n\tu32 io_size;\n\tint irq;\n\tconst struct dw_pcie_host_ops *ops;\n\tint msi_irq[8];\n\tstruct irq_domain *irq_domain;\n\tdma_addr_t msi_data;\n\tstruct irq_chip *msi_irq_chip;\n\tu32 num_vectors;\n\tu32 irq_mask[8];\n\tstruct pci_host_bridge *bridge;\n\traw_spinlock_t lock;\n\tlong unsigned int msi_irq_in_use[8];\n\tbool use_atu_msg;\n\tint msg_atu_index;\n\tstruct resource *msg_res;\n\tstruct pci_eq_presets presets;\n\tstruct pci_config_window *cfg;\n\tbool ecam_enabled;\n\tbool native_ecam;\n\tbool skip_l23_ready;\n};\n\nstruct pci_epc;\n\nstruct dw_pcie_ep_ops;\n\nstruct dw_pcie_ep {\n\tstruct pci_epc *epc;\n\tstruct list_head func_list;\n\tconst struct dw_pcie_ep_ops *ops;\n\tphys_addr_t phys_base;\n\tsize_t addr_size;\n\tsize_t page_size;\n\tphys_addr_t *outbound_addr;\n\tlong unsigned int *ib_window_map;\n\tlong unsigned int *ob_window_map;\n\tvoid *msi_mem;\n\tphys_addr_t msi_mem_phys;\n\tbool msi_iatu_mapped;\n\tlong: 32;\n\tu64 msi_msg_addr;\n\tsize_t msi_map_size;\n\tlong: 32;\n};\n\nstruct reset_control_bulk_data {\n\tconst char *id;\n\tstruct reset_control *rstc;\n};\n\nstruct dw_pcie_ops;\n\nstruct pci_ptm_debugfs;\n\nstruct dw_pcie {\n\tstruct device *dev;\n\tvoid *dbi_base;\n\tresource_size_t dbi_phys_addr;\n\tvoid *dbi_base2;\n\tvoid *atu_base;\n\tvoid *elbi_base;\n\tresource_size_t atu_phys_addr;\n\tsize_t atu_size;\n\tresource_size_t parent_bus_offset;\n\tu32 num_ib_windows;\n\tu32 num_ob_windows;\n\tu32 region_align;\n\tu64 region_limit;\n\tstruct dw_pcie_rp pp;\n\tstruct dw_pcie_ep ep;\n\tconst struct dw_pcie_ops *ops;\n\tu32 version;\n\tu32 type;\n\tlong unsigned int caps;\n\tint num_lanes;\n\tint max_link_speed;\n\tu8 n_fts[2];\n\tlong: 32;\n\tstruct dw_edma_chip edma;\n\tbool l1ss_support;\n\tstruct clk_bulk_data app_clks[3];\n\tstruct clk_bulk_data core_clks[4];\n\tstruct reset_control_bulk_data app_rsts[3];\n\tstruct reset_control_bulk_data core_rsts[7];\n\tstruct gpio_desc *pe_rst;\n\tbool suspended;\n\tstruct debugfs_info *debugfs;\n\tenum dw_pcie_device_mode mode;\n\tu16 ptm_vsec_offset;\n\tstruct pci_ptm_debugfs *ptm_debugfs;\n\tbool use_parent_dt_ranges;\n};\n\nstruct pci_epf_bar;\n\nstruct dw_pcie_ep_func {\n\tstruct list_head list;\n\tu8 func_no;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 bar_to_atu[6];\n\tstruct pci_epf_bar *epf_bar[6];\n\tu32 *ib_atu_indexes[6];\n\tunsigned int num_ib_atu_indexes[6];\n};\n\nstruct pci_epc_features;\n\nstruct dw_pcie_ep_ops {\n\tvoid (*pre_init)(struct dw_pcie_ep *);\n\tvoid (*init)(struct dw_pcie_ep *);\n\tint (*raise_irq)(struct dw_pcie_ep *, u8, unsigned int, u16);\n\tconst struct pci_epc_features * (*get_features)(struct dw_pcie_ep *);\n\tunsigned int (*get_dbi_offset)(struct dw_pcie_ep *, u8);\n\tunsigned int (*get_dbi2_offset)(struct dw_pcie_ep *, u8);\n};\n\nstruct dw_pcie_host_ops {\n\tint (*init)(struct dw_pcie_rp *);\n\tvoid (*deinit)(struct dw_pcie_rp *);\n\tvoid (*post_init)(struct dw_pcie_rp *);\n\tint (*msi_init)(struct dw_pcie_rp *);\n\tvoid (*pme_turn_off)(struct dw_pcie_rp *);\n};\n\nstruct dw_pcie_ob_atu_cfg {\n\tint index;\n\tint type;\n\tu8 func_no;\n\tu8 code;\n\tu8 routing;\n\tu32 ctrl2;\n\tu64 parent_bus_addr;\n\tu64 pci_addr;\n\tu64 size;\n};\n\nstruct dw_pcie_ops {\n\tu64 (*cpu_addr_fixup)(struct dw_pcie *, u64);\n\tu32 (*read_dbi)(struct dw_pcie *, void *, u32, size_t);\n\tvoid (*write_dbi)(struct dw_pcie *, void *, u32, size_t, u32);\n\tvoid (*write_dbi2)(struct dw_pcie *, void *, u32, size_t, u32);\n\tbool (*link_up)(struct dw_pcie *);\n\tenum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *);\n\tint (*start_link)(struct dw_pcie *);\n\tvoid (*stop_link)(struct dw_pcie *);\n};\n\nstruct dw_wdt_timeout {\n\tu32 top_val;\n\tunsigned int sec;\n\tunsigned int msec;\n};\n\nstruct dw_wdt {\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tlong unsigned int rate;\n\tenum dw_wdt_rmod rmod;\n\tstruct dw_wdt_timeout timeouts[16];\n\tstruct watchdog_device wdd;\n\tstruct reset_control *rst;\n\tu32 control;\n\tu32 timeout;\n\tstruct dentry *dbgfs_dir;\n};\n\nstruct dw_xpcs_info {\n\tu32 pcs;\n\tu32 pma;\n};\n\nstruct phylink_pcs_ops;\n\nstruct phylink_pcs {\n\tlong unsigned int supported_interfaces[2];\n\tconst struct phylink_pcs_ops *ops;\n\tstruct phylink *phylink;\n\tbool poll;\n\tbool rxc_always_on;\n};\n\nstruct dw_xpcs_desc;\n\nstruct mdio_device;\n\nstruct dw_xpcs {\n\tstruct dw_xpcs_info info;\n\tconst struct dw_xpcs_desc *desc;\n\tstruct mdio_device *mdiodev;\n\tstruct clk_bulk_data clks[2];\n\tstruct phylink_pcs pcs;\n\tphy_interface_t interface;\n\tbool need_reset;\n\tu8 eee_mult_fact;\n};\n\nstruct dw_xpcs_compat {\n\tphy_interface_t interface;\n\tconst int *supported;\n\tint an_mode;\n\tint (*pma_config)(struct dw_xpcs *);\n};\n\nstruct dw_xpcs_desc {\n\tu32 id;\n\tu32 mask;\n\tconst struct dw_xpcs_compat *compat;\n};\n\nstruct dw_xpcs_plat {\n\tstruct platform_device *pdev;\n\tstruct mii_bus *bus;\n\tbool reg_indir;\n\tint reg_width;\n\tvoid *reg_base;\n\tstruct clk *cclk;\n};\n\nstruct dwapb_context {\n\tu32 data;\n\tu32 dir;\n\tu32 ext;\n\tu32 int_en;\n\tu32 int_mask;\n\tu32 int_type;\n\tu32 int_pol;\n\tu32 int_deb;\n\tu32 wake_en;\n};\n\nstruct dwapb_gpio_port;\n\nstruct dwapb_gpio {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct dwapb_gpio_port *ports;\n\tunsigned int nr_ports;\n\tunsigned int flags;\n\tstruct reset_control *rst;\n\tstruct clk_bulk_data clks[2];\n};\n\nstruct dwapb_gpio_port_irqchip;\n\nstruct dwapb_gpio_port {\n\tstruct gpio_generic_chip chip;\n\tstruct dwapb_gpio_port_irqchip *pirq;\n\tstruct dwapb_gpio *gpio;\n\tstruct dwapb_context *ctx;\n\tunsigned int idx;\n};\n\nstruct dwapb_gpio_port_irqchip {\n\tunsigned int nr_irqs;\n\tunsigned int irq[32];\n};\n\nstruct dwapb_port_property;\n\nstruct dwapb_platform_data {\n\tstruct dwapb_port_property *properties;\n\tunsigned int nports;\n};\n\nstruct dwapb_port_property {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int idx;\n\tunsigned int ngpio;\n\tunsigned int gpio_base;\n\tint irq[32];\n};\n\nstruct dwc2_core_params {\n\tstruct usb_otg_caps otg_caps;\n\tu8 phy_type;\n\tu8 speed;\n\tu8 phy_utmi_width;\n\tbool eusb2_disc;\n\tbool phy_ulpi_ddr;\n\tbool phy_ulpi_ext_vbus;\n\tbool enable_dynamic_fifo;\n\tbool en_multiple_tx_fifo;\n\tbool i2c_enable;\n\tbool acg_enable;\n\tbool ulpi_fs_ls;\n\tbool ts_dline;\n\tbool reload_ctl;\n\tbool uframe_sched;\n\tbool external_id_pin_ctl;\n\tint power_down;\n\tbool no_clock_gating;\n\tbool lpm;\n\tbool lpm_clock_gating;\n\tbool besl;\n\tbool hird_threshold_en;\n\tbool service_interval;\n\tu8 hird_threshold;\n\tbool activate_stm_fs_transceiver;\n\tbool activate_stm_id_vb_detection;\n\tbool activate_ingenic_overcurrent_detection;\n\tbool ipg_isoc_en;\n\tu16 max_packet_count;\n\tu32 max_transfer_size;\n\tu32 ahbcfg;\n\tu32 ref_clk_per;\n\tu16 sof_cnt_wkup_alert;\n\tbool host_dma;\n\tbool dma_desc_enable;\n\tbool dma_desc_fs_enable;\n\tbool host_support_fs_ls_low_power;\n\tbool host_ls_low_power_phy_clk;\n\tbool oc_disable;\n\tu8 host_channels;\n\tu16 host_rx_fifo_size;\n\tu16 host_nperio_tx_fifo_size;\n\tu16 host_perio_tx_fifo_size;\n\tbool g_dma;\n\tbool g_dma_desc;\n\tu32 g_rx_fifo_size;\n\tu32 g_np_tx_fifo_size;\n\tu32 g_tx_fifo_size[16];\n\tbool change_speed_quirk;\n};\n\nstruct dwc2_dma_desc {\n\tu32 status;\n\tu32 buf;\n};\n\nstruct dwc2_dregs_backup {\n\tu32 dcfg;\n\tu32 dctl;\n\tu32 daintmsk;\n\tu32 diepmsk;\n\tu32 doepmsk;\n\tu32 diepctl[16];\n\tu32 dieptsiz[16];\n\tu32 diepdma[16];\n\tu32 doepctl[16];\n\tu32 doeptsiz[16];\n\tu32 doepdma[16];\n\tu32 dtxfsiz[16];\n\tbool valid;\n};\n\nstruct dwc2_gregs_backup {\n\tu32 gintsts;\n\tu32 gotgctl;\n\tu32 gintmsk;\n\tu32 gahbcfg;\n\tu32 gusbcfg;\n\tu32 grxfsiz;\n\tu32 gnptxfsiz;\n\tu32 gi2cctl;\n\tu32 glpmcfg;\n\tu32 pcgcctl;\n\tu32 pcgcctl1;\n\tu32 gdfifocfg;\n\tu32 gpwrdn;\n\tbool valid;\n};\n\nunion dwc2_hcd_internal_flags {\n\tu32 d32;\n\tstruct {\n\t\tunsigned int port_connect_status_change: 1;\n\t\tunsigned int port_connect_status: 1;\n\t\tunsigned int port_reset_change: 1;\n\t\tunsigned int port_enable_change: 1;\n\t\tunsigned int port_suspend_change: 1;\n\t\tunsigned int port_over_current_change: 1;\n\t\tunsigned int port_l1_change: 1;\n\t\tunsigned int reserved: 25;\n\t} b;\n};\n\nstruct dwc2_hcd_iso_packet_desc {\n\tu32 offset;\n\tu32 length;\n\tu32 actual_length;\n\tu32 status;\n};\n\nstruct dwc2_hcd_pipe_info {\n\tu8 dev_addr;\n\tu8 ep_num;\n\tu8 pipe_type;\n\tu8 pipe_dir;\n\tu16 maxp;\n\tu16 maxp_mult;\n};\n\nstruct dwc2_qtd;\n\nstruct dwc2_hcd_urb {\n\tvoid *priv;\n\tstruct dwc2_qtd *qtd;\n\tvoid *buf;\n\tdma_addr_t dma;\n\tvoid *setup_packet;\n\tdma_addr_t setup_dma;\n\tu32 length;\n\tu32 actual_length;\n\tu32 status;\n\tu32 error_count;\n\tu32 packet_count;\n\tu32 flags;\n\tu16 interval;\n\tstruct dwc2_hcd_pipe_info pipe_info;\n\tstruct dwc2_hcd_iso_packet_desc iso_descs[0];\n};\n\nstruct dwc2_qh;\n\nstruct dwc2_host_chan {\n\tu8 hc_num;\n\tunsigned int dev_addr: 7;\n\tunsigned int ep_num: 4;\n\tunsigned int ep_is_in: 1;\n\tunsigned int speed: 4;\n\tunsigned int ep_type: 2;\n\tlong: 6;\n\tunsigned int max_packet: 11;\n\tunsigned int data_pid_start: 2;\n\tunsigned int multi_count: 2;\n\tu8 *xfer_buf;\n\tdma_addr_t xfer_dma;\n\tdma_addr_t align_buf;\n\tu32 xfer_len;\n\tu32 xfer_count;\n\tu16 start_pkt_count;\n\tu8 xfer_started;\n\tu8 do_ping;\n\tu8 error_state;\n\tu8 halt_on_queue;\n\tu8 halt_pending;\n\tu8 do_split;\n\tu8 complete_split;\n\tu8 hub_addr;\n\tu8 hub_port;\n\tu8 xact_pos;\n\tu8 requests;\n\tu8 schinfo;\n\tu16 ntd;\n\tenum dwc2_halt_status halt_status;\n\tu32 hcint;\n\tstruct dwc2_qh *qh;\n\tstruct list_head hc_list_entry;\n\tdma_addr_t desc_list_addr;\n\tu32 desc_list_sz;\n\tstruct list_head split_order_list_entry;\n};\n\nstruct dwc2_hregs_backup {\n\tu32 hcfg;\n\tu32 hflbaddr;\n\tu32 haintmsk;\n\tu32 hcchar[16];\n\tu32 hcsplt[16];\n\tu32 hcintmsk[16];\n\tu32 hctsiz[16];\n\tu32 hcidma[16];\n\tu32 hcidmab[16];\n\tu32 hprt0;\n\tu32 hfir;\n\tu32 hptxfsiz;\n\tbool valid;\n};\n\nstruct dwc2_hs_transfer_time {\n\tu32 start_schedule_us;\n\tu16 duration_us;\n};\n\nstruct dwc2_hw_params {\n\tunsigned int op_mode: 3;\n\tunsigned int arch: 2;\n\tunsigned int dma_desc_enable: 1;\n\tunsigned int enable_dynamic_fifo: 1;\n\tunsigned int en_multiple_tx_fifo: 1;\n\tunsigned int rx_fifo_size: 16;\n\tlong: 8;\n\tunsigned int host_nperio_tx_fifo_size: 16;\n\tunsigned int dev_nperio_tx_fifo_size: 16;\n\tunsigned int host_perio_tx_fifo_size: 16;\n\tunsigned int nperio_tx_q_depth: 3;\n\tunsigned int host_perio_tx_q_depth: 3;\n\tunsigned int dev_token_q_depth: 5;\n\tlong: 5;\n\tunsigned int max_transfer_size: 26;\n\tlong: 6;\n\tunsigned int max_packet_count: 11;\n\tunsigned int host_channels: 5;\n\tunsigned int hs_phy_type: 2;\n\tunsigned int fs_phy_type: 2;\n\tunsigned int i2c_enable: 1;\n\tunsigned int acg_enable: 1;\n\tunsigned int num_dev_ep: 4;\n\tunsigned int num_dev_in_eps: 4;\n\tlong: 2;\n\tunsigned int num_dev_perio_in_ep: 4;\n\tunsigned int total_fifo_size: 16;\n\tunsigned int power_optimized: 1;\n\tunsigned int hibernation: 1;\n\tunsigned int utmi_phy_data_width: 2;\n\tunsigned int lpm_mode: 1;\n\tunsigned int ipg_isoc_en: 1;\n\tunsigned int service_interval_mode: 1;\n\tu32 snpsid;\n\tu32 dev_ep_dirs;\n\tu32 g_tx_fifo_size[16];\n};\n\nstruct regulator_bulk_data {\n\tconst char *supply;\n\tstruct regulator *consumer;\n\tint init_load_uA;\n\tint ret;\n};\n\nstruct dwc2_hsotg_plat;\n\nstruct dwc2_hsotg_ep;\n\nstruct dwc2_hsotg {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct dwc2_hw_params hw_params;\n\tstruct dwc2_core_params params;\n\tenum usb_otg_state op_state;\n\tenum usb_dr_mode dr_mode;\n\tstruct usb_role_switch *role_sw;\n\tenum usb_dr_mode role_sw_default_mode;\n\tunsigned int hcd_enabled: 1;\n\tunsigned int gadget_enabled: 1;\n\tunsigned int ll_hw_enabled: 1;\n\tunsigned int hibernated: 1;\n\tunsigned int in_ppd: 1;\n\tbool bus_suspended;\n\tunsigned int reset_phy_on_wake: 1;\n\tunsigned int need_phy_for_wake: 1;\n\tunsigned int phy_off_for_suspend: 1;\n\tu16 frame_number;\n\tstruct phy *phy;\n\tstruct usb_phy *uphy;\n\tstruct dwc2_hsotg_plat *plat;\n\tstruct regulator_bulk_data supplies[2];\n\tstruct regulator *vbus_supply;\n\tstruct regulator *usb33d;\n\tspinlock_t lock;\n\tvoid *priv;\n\tint irq;\n\tstruct clk *clk;\n\tstruct clk *utmi_clk;\n\tstruct reset_control *reset;\n\tstruct reset_control *reset_ecc;\n\tunsigned int queuing_high_bandwidth: 1;\n\tunsigned int srp_success: 1;\n\tstruct workqueue_struct *wq_otg;\n\tstruct work_struct wf_otg;\n\tstruct timer_list wkp_timer;\n\tenum dwc2_lx_state lx_state;\n\tstruct dwc2_gregs_backup gr_backup;\n\tstruct dwc2_dregs_backup dr_backup;\n\tstruct dwc2_hregs_backup hr_backup;\n\tstruct dentry *debug_root;\n\tstruct debugfs_regset32 *regset;\n\tbool needs_byte_swap;\n\tunion dwc2_hcd_internal_flags flags;\n\tstruct list_head non_periodic_sched_inactive;\n\tstruct list_head non_periodic_sched_waiting;\n\tstruct list_head non_periodic_sched_active;\n\tstruct list_head *non_periodic_qh_ptr;\n\tstruct list_head periodic_sched_inactive;\n\tstruct list_head periodic_sched_ready;\n\tstruct list_head periodic_sched_assigned;\n\tstruct list_head periodic_sched_queued;\n\tstruct list_head split_order;\n\tu16 periodic_usecs;\n\tlong unsigned int hs_periodic_bitmap[25];\n\tu16 periodic_qh_count;\n\tbool new_connection;\n\tu16 last_frame_num;\n\tstruct list_head free_hc_list;\n\tint periodic_channels;\n\tint non_periodic_channels;\n\tint available_host_channels;\n\tstruct dwc2_host_chan *hc_ptr_array[16];\n\tu8 *status_buf;\n\tdma_addr_t status_buf_dma;\n\tstruct delayed_work start_work;\n\tstruct delayed_work reset_work;\n\tstruct work_struct phy_reset_work;\n\tu8 otg_port;\n\tu32 *frame_list;\n\tdma_addr_t frame_list_dma;\n\tu32 frame_list_sz;\n\tstruct kmem_cache *desc_gen_cache;\n\tstruct kmem_cache *desc_hsisoc_cache;\n\tstruct kmem_cache *unaligned_cache;\n\tstruct usb_gadget_driver *driver;\n\tint fifo_mem;\n\tunsigned int dedicated_fifos: 1;\n\tunsigned char num_of_eps;\n\tu32 fifo_map;\n\tstruct usb_request *ep0_reply;\n\tstruct usb_request *ctrl_req;\n\tvoid *ep0_buff;\n\tvoid *ctrl_buff;\n\tenum dwc2_ep0_state ep0_state;\n\tunsigned int delayed_status: 1;\n\tu8 test_mode;\n\tdma_addr_t setup_desc_dma[2];\n\tstruct dwc2_dma_desc *setup_desc[2];\n\tdma_addr_t ctrl_in_desc_dma;\n\tstruct dwc2_dma_desc *ctrl_in_desc;\n\tdma_addr_t ctrl_out_desc_dma;\n\tstruct dwc2_dma_desc *ctrl_out_desc;\n\tstruct usb_gadget gadget;\n\tunsigned int enabled: 1;\n\tunsigned int connected: 1;\n\tunsigned int remote_wakeup_allowed: 1;\n\tstruct dwc2_hsotg_ep *eps_in[16];\n\tstruct dwc2_hsotg_ep *eps_out[16];\n\tlong: 32;\n};\n\nstruct dwc2_hsotg_req;\n\nstruct dwc2_hsotg_ep {\n\tstruct usb_ep ep;\n\tstruct list_head queue;\n\tstruct dwc2_hsotg *parent;\n\tstruct dwc2_hsotg_req *req;\n\tstruct dentry *debugfs;\n\tlong unsigned int total_data;\n\tunsigned int size_loaded;\n\tunsigned int last_load;\n\tunsigned int fifo_load;\n\tshort unsigned int fifo_size;\n\tshort unsigned int fifo_index;\n\tunsigned char dir_in;\n\tunsigned char map_dir;\n\tunsigned char index;\n\tunsigned char mc;\n\tu16 interval;\n\tunsigned int halted: 1;\n\tunsigned int periodic: 1;\n\tunsigned int isochronous: 1;\n\tunsigned int send_zlp: 1;\n\tunsigned int wedged: 1;\n\tunsigned int target_frame;\n\tbool frame_overrun;\n\tdma_addr_t desc_list_dma;\n\tstruct dwc2_dma_desc *desc_list;\n\tu8 desc_count;\n\tunsigned int next_desc;\n\tunsigned int compl_desc;\n\tchar name[10];\n};\n\nstruct dwc2_hsotg_plat {\n\tenum dwc2_hsotg_dmamode dma;\n\tunsigned int is_osc: 1;\n\tint phy_type;\n\tint (*phy_init)(struct platform_device *, int);\n\tint (*phy_exit)(struct platform_device *, int);\n};\n\nstruct dwc2_hsotg_req {\n\tstruct usb_request req;\n\tstruct list_head queue;\n\tvoid *saved_req_buf;\n};\n\nstruct dwc2_tt;\n\nstruct dwc2_qh {\n\tstruct dwc2_hsotg *hsotg;\n\tu8 ep_type;\n\tu8 ep_is_in;\n\tu16 maxp;\n\tu16 maxp_mult;\n\tu8 dev_speed;\n\tu8 data_toggle;\n\tu8 ping_state;\n\tu8 do_split;\n\tu8 td_first;\n\tu8 td_last;\n\tu16 host_us;\n\tu16 device_us;\n\tu16 host_interval;\n\tu16 device_interval;\n\tu16 next_active_frame;\n\tu16 start_active_frame;\n\ts16 num_hs_transfers;\n\tstruct dwc2_hs_transfer_time hs_transfers[8];\n\tu32 ls_start_schedule_slice;\n\tu16 ntd;\n\tu8 *dw_align_buf;\n\tdma_addr_t dw_align_buf_dma;\n\tstruct list_head qtd_list;\n\tstruct dwc2_host_chan *channel;\n\tstruct list_head qh_list_entry;\n\tstruct dwc2_dma_desc *desc_list;\n\tdma_addr_t desc_list_dma;\n\tu32 desc_list_sz;\n\tu32 *n_bytes;\n\tstruct timer_list unreserve_timer;\n\tstruct hrtimer wait_timer;\n\tstruct dwc2_tt *dwc_tt;\n\tint ttport;\n\tunsigned int tt_buffer_dirty: 1;\n\tunsigned int unreserve_pending: 1;\n\tunsigned int schedule_low_speed: 1;\n\tunsigned int want_wait: 1;\n\tunsigned int wait_timer_cancel: 1;\n\tlong: 32;\n};\n\nstruct dwc2_qtd {\n\tenum dwc2_control_phase control_phase;\n\tu8 in_process;\n\tu8 data_toggle;\n\tu8 complete_split;\n\tu8 isoc_split_pos;\n\tu16 isoc_frame_index;\n\tu16 isoc_split_offset;\n\tu16 isoc_td_last;\n\tu16 isoc_td_first;\n\tu32 ssplit_out_xfer_count;\n\tu8 error_count;\n\tu8 n_desc;\n\tu16 isoc_frame_index_last;\n\tu16 num_naks;\n\tstruct dwc2_hcd_urb *urb;\n\tstruct dwc2_qh *qh;\n\tstruct list_head qtd_list_entry;\n};\n\nstruct usb_tt;\n\nstruct dwc2_tt {\n\tint refcount;\n\tstruct usb_tt *usb_tt;\n\tlong unsigned int periodic_bitmaps[0];\n};\n\nstruct dwc3_ep;\n\nstruct dwc3_trb;\n\nstruct dwc3_request {\n\tstruct usb_request request;\n\tstruct list_head list;\n\tstruct dwc3_ep *dep;\n\tstruct scatterlist *start_sg;\n\tunsigned int num_pending_sgs;\n\tunsigned int remaining;\n\tunsigned int status;\n\tu8 epnum;\n\tstruct dwc3_trb *trb;\n\tdma_addr_t trb_dma;\n\tunsigned int num_trbs;\n\tunsigned int direction: 1;\n\tunsigned int mapped: 1;\n};\n\nstruct dwc3_hwparams {\n\tu32 hwparams0;\n\tu32 hwparams1;\n\tu32 hwparams2;\n\tu32 hwparams3;\n\tu32 hwparams4;\n\tu32 hwparams5;\n\tu32 hwparams6;\n\tu32 hwparams7;\n\tu32 hwparams8;\n\tu32 hwparams9;\n};\n\nstruct dwc3_event_buffer;\n\nstruct dwc3_glue_ops;\n\nstruct dwc3 {\n\tstruct work_struct drd_work;\n\tstruct dwc3_trb *ep0_trb;\n\tvoid *bounce;\n\tu8 *setup_buf;\n\tdma_addr_t ep0_trb_addr;\n\tdma_addr_t bounce_addr;\n\tstruct dwc3_request ep0_usb_req;\n\tstruct completion ep0_in_setup;\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tstruct device *dev;\n\tstruct device *sysdev;\n\tstruct platform_device *xhci;\n\tstruct resource xhci_resources[2];\n\tstruct dwc3_event_buffer *ev_buf;\n\tstruct dwc3_ep *eps[32];\n\tstruct usb_gadget *gadget;\n\tstruct usb_gadget_driver *gadget_driver;\n\tconst struct dwc3_glue_ops *glue_ops;\n\tstruct clk *bus_clk;\n\tstruct clk *ref_clk;\n\tstruct clk *susp_clk;\n\tstruct clk *utmi_clk;\n\tstruct clk *pipe_clk;\n\tstruct reset_control *reset;\n\tstruct usb_phy *usb2_phy;\n\tstruct usb_phy *usb3_phy;\n\tstruct phy *usb2_generic_phy[15];\n\tstruct phy *usb3_generic_phy[4];\n\tu8 num_usb2_ports;\n\tu8 num_usb3_ports;\n\tbool phys_ready;\n\tstruct ulpi *ulpi;\n\tbool ulpi_ready;\n\tvoid *regs;\n\tsize_t regs_size;\n\tenum usb_dr_mode dr_mode;\n\tu32 current_dr_role;\n\tu32 desired_dr_role;\n\tstruct extcon_dev *edev;\n\tstruct notifier_block edev_nb;\n\tenum usb_phy_interface hsphy_mode;\n\tstruct usb_role_switch *role_sw;\n\tenum usb_dr_mode role_switch_default_mode;\n\tstruct power_supply *usb_psy;\n\tstruct work_struct vbus_draw_work;\n\tunsigned int current_limit;\n\tu32 fladj;\n\tu32 ref_clk_per;\n\tu32 irq_gadget;\n\tu32 otg_irq;\n\tu32 current_otg_role;\n\tu32 desired_otg_role;\n\tbool otg_restart_host;\n\tu32 u1u2;\n\tu32 maximum_speed;\n\tu32 gadget_max_speed;\n\tenum usb_ssp_rate max_ssp_rate;\n\tenum usb_ssp_rate gadget_ssp_rate;\n\tu32 ip;\n\tu32 revision;\n\tu32 version_type;\n\tenum dwc3_ep0_next ep0_next_event;\n\tenum dwc3_ep0_state ep0state;\n\tenum dwc3_link_state link_state;\n\tu16 u2sel;\n\tu16 u2pel;\n\tu8 u1sel;\n\tu8 u1pel;\n\tu8 speed;\n\tu8 num_eps;\n\tstruct dwc3_hwparams hwparams;\n\tstruct debugfs_regset32 *regset;\n\tu32 dbg_lsp_select;\n\tu8 test_mode;\n\tu8 test_mode_nr;\n\tu8 lpm_nyet_threshold;\n\tu8 hird_threshold;\n\tu8 rx_thr_num_pkt;\n\tu8 rx_max_burst;\n\tu8 tx_thr_num_pkt;\n\tu8 tx_max_burst;\n\tu8 rx_thr_num_pkt_prd;\n\tu8 rx_max_burst_prd;\n\tu8 tx_thr_num_pkt_prd;\n\tu8 tx_max_burst_prd;\n\tu8 tx_fifo_resize_max_num;\n\tu8 clear_stall_protocol;\n\tu16 num_hc_interrupters;\n\tconst char *hsphy_interface;\n\tunsigned int connected: 1;\n\tunsigned int softconnect: 1;\n\tunsigned int delayed_status: 1;\n\tunsigned int ep0_bounced: 1;\n\tunsigned int ep0_expect_in: 1;\n\tunsigned int sysdev_is_parent: 1;\n\tunsigned int has_lpm_erratum: 1;\n\tunsigned int is_utmi_l1_suspend: 1;\n\tunsigned int is_fpga: 1;\n\tunsigned int pending_events: 1;\n\tunsigned int do_fifo_resize: 1;\n\tunsigned int pullups_connected: 1;\n\tunsigned int setup_packet_pending: 1;\n\tunsigned int three_stage_setup: 1;\n\tunsigned int dis_start_transfer_quirk: 1;\n\tunsigned int usb3_lpm_capable: 1;\n\tunsigned int usb2_lpm_disable: 1;\n\tunsigned int usb2_gadget_lpm_disable: 1;\n\tunsigned int disable_scramble_quirk: 1;\n\tunsigned int u2exit_lfps_quirk: 1;\n\tunsigned int u2ss_inp3_quirk: 1;\n\tunsigned int req_p1p2p3_quirk: 1;\n\tunsigned int del_p1p2p3_quirk: 1;\n\tunsigned int del_phy_power_chg_quirk: 1;\n\tunsigned int lfps_filter_quirk: 1;\n\tunsigned int rx_detect_poll_quirk: 1;\n\tunsigned int dis_u3_susphy_quirk: 1;\n\tunsigned int dis_u2_susphy_quirk: 1;\n\tunsigned int dis_enblslpm_quirk: 1;\n\tunsigned int dis_u1_entry_quirk: 1;\n\tunsigned int dis_u2_entry_quirk: 1;\n\tunsigned int dis_rxdet_inp3_quirk: 1;\n\tunsigned int dis_u2_freeclk_exists_quirk: 1;\n\tunsigned int dis_del_phy_power_chg_quirk: 1;\n\tunsigned int dis_tx_ipgap_linecheck_quirk: 1;\n\tunsigned int resume_hs_terminations: 1;\n\tunsigned int ulpi_ext_vbus_drv: 1;\n\tunsigned int parkmode_disable_ss_quirk: 1;\n\tunsigned int parkmode_disable_hs_quirk: 1;\n\tunsigned int gfladj_refclk_lpm_sel: 1;\n\tunsigned int tx_de_emphasis_quirk: 1;\n\tunsigned int tx_de_emphasis: 2;\n\tunsigned int dis_metastability_quirk: 1;\n\tunsigned int dis_split_quirk: 1;\n\tunsigned int async_callbacks: 1;\n\tunsigned int sys_wakeup: 1;\n\tunsigned int wakeup_configured: 1;\n\tunsigned int suspended: 1;\n\tunsigned int susphy_state: 1;\n\tu16 imod_interval;\n\tint max_cfg_eps;\n\tint last_fifo_depth;\n\tint num_ep_resized;\n\tstruct dentry *debug_root;\n\tu32 gsbuscfg0_reqinfo;\n\tu32 wakeup_pending_funcs;\n};\n\nstruct dwc3_ep {\n\tstruct usb_ep endpoint;\n\tstruct delayed_work nostream_work;\n\tstruct list_head cancelled_list;\n\tstruct list_head pending_list;\n\tstruct list_head started_list;\n\tstruct dwc3_trb *trb_pool;\n\tdma_addr_t trb_pool_dma;\n\tstruct dwc3 *dwc;\n\tu32 saved_state;\n\tunsigned int flags;\n\tu8 trb_enqueue;\n\tu8 trb_dequeue;\n\tu8 number;\n\tu8 type;\n\tu8 resource_index;\n\tu32 frame_number;\n\tu32 interval;\n\tchar name[20];\n\tunsigned int direction: 1;\n\tunsigned int stream_capable: 1;\n\tu8 combo_num;\n\tint start_cmd_status;\n};\n\nstruct dwc3_ep_file_map {\n\tconst char name[25];\n\tconst struct file_operations * const fops;\n};\n\nstruct dwc3_event_type {\n\tu32 is_devspec: 1;\n\tu32 type: 7;\n\tu32 reserved8_31: 24;\n};\n\nstruct dwc3_event_depevt {\n\tu32 one_bit: 1;\n\tu32 endpoint_number: 5;\n\tu32 endpoint_event: 4;\n\tu32 reserved11_10: 2;\n\tu32 status: 4;\n\tu32 parameters: 16;\n};\n\nstruct dwc3_event_devt {\n\tu32 one_bit: 1;\n\tu32 device_event: 7;\n\tu32 type: 4;\n\tu32 reserved15_12: 4;\n\tu32 event_info: 9;\n\tu32 reserved31_25: 7;\n};\n\nstruct dwc3_event_gevt {\n\tu32 one_bit: 1;\n\tu32 device_event: 7;\n\tu32 phy_port_number: 4;\n\tu32 reserved31_12: 20;\n};\n\nunion dwc3_event {\n\tu32 raw;\n\tstruct dwc3_event_type type;\n\tstruct dwc3_event_depevt depevt;\n\tstruct dwc3_event_devt devt;\n\tstruct dwc3_event_gevt gevt;\n};\n\nstruct dwc3_event_buffer {\n\tvoid *buf;\n\tvoid *cache;\n\tunsigned int length;\n\tunsigned int lpos;\n\tunsigned int count;\n\tunsigned int flags;\n\tdma_addr_t dma;\n\tstruct dwc3 *dwc;\n};\n\nstruct dwc3_exynos {\n\tstruct device *dev;\n\tconst char **clk_names;\n\tstruct clk *clks[4];\n\tint num_clks;\n\tint suspend_clk_idx;\n\tstruct regulator *vdd33;\n\tstruct regulator *vdd10;\n};\n\nstruct dwc3_exynos_driverdata {\n\tconst char *clk_names[4];\n\tint num_clks;\n\tint suspend_clk_idx;\n};\n\nstruct dwc3_gadget_ep_cmd_params {\n\tu32 param2;\n\tu32 param1;\n\tu32 param0;\n};\n\nstruct dwc3_generic {\n\tstruct device *dev;\n\tstruct dwc3 dwc;\n\tstruct clk_bulk_data *clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n};\n\nstruct dwc3_properties {\n\tu32 gsbuscfg0_reqinfo;\n};\n\nstruct dwc3_generic_config {\n\tint (*init)(struct dwc3_generic *);\n\tstruct dwc3_properties properties;\n};\n\nstruct dwc3_glue_ops {\n\tvoid (*pre_set_role)(struct dwc3 *, enum usb_role);\n\tvoid (*pre_run_stop)(struct dwc3 *, bool);\n};\n\nstruct dwc3_haps {\n\tstruct platform_device *dwc3;\n\tstruct pci_dev *pci;\n};\n\nstruct dwc3_keystone {\n\tstruct device *dev;\n\tvoid *usbss;\n\tstruct phy *usb3_phy;\n};\n\ntypedef int (*usb_role_switch_set_t)(struct usb_role_switch *, enum usb_role);\n\ntypedef enum usb_role (*usb_role_switch_get_t)(struct usb_role_switch *);\n\nstruct usb_role_switch_desc {\n\tstruct fwnode_handle *fwnode;\n\tstruct device *usb2_port;\n\tstruct device *usb3_port;\n\tstruct device *udc;\n\tusb_role_switch_set_t set;\n\tusb_role_switch_get_t get;\n\tbool allow_userspace_control;\n\tvoid *driver_data;\n\tconst char *name;\n};\n\nstruct dwc3_meson_g12a_drvdata;\n\nstruct dwc3_meson_g12a {\n\tstruct device *dev;\n\tstruct regmap *u2p_regmap[3];\n\tstruct regmap *usb_glue_regmap;\n\tstruct reset_control *reset;\n\tstruct phy *phys[3];\n\tenum usb_dr_mode otg_mode;\n\tenum phy_mode otg_phy_mode;\n\tunsigned int usb2_ports;\n\tunsigned int usb3_ports;\n\tstruct regulator *vbus;\n\tstruct usb_role_switch_desc switch_desc;\n\tstruct usb_role_switch *role_switch;\n\tconst struct dwc3_meson_g12a_drvdata *drvdata;\n};\n\nstruct dwc3_meson_g12a_drvdata {\n\tbool otg_phy_host_port_disable;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tconst char * const *phy_names;\n\tint num_phys;\n\tint (*setup_regmaps)(struct dwc3_meson_g12a *, void *);\n\tint (*usb2_init_phy)(struct dwc3_meson_g12a *, int, enum phy_mode);\n\tint (*set_phy_mode)(struct dwc3_meson_g12a *, int, enum phy_mode);\n\tint (*usb_init)(struct dwc3_meson_g12a *);\n\tint (*usb_post_init)(struct dwc3_meson_g12a *);\n};\n\nstruct dwc3_of_simple {\n\tstruct device *dev;\n\tstruct clk_bulk_data *clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n\tbool need_reset;\n};\n\nstruct dwc3_omap {\n\tstruct device *dev;\n\tint irq;\n\tvoid *base;\n\tu32 utmi_otg_ctrl;\n\tu32 utmi_otg_offset;\n\tu32 irqmisc_offset;\n\tu32 irq_eoi_offset;\n\tu32 debug_offset;\n\tu32 irq0_offset;\n\tstruct extcon_dev *edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct regulator *vbus_reg;\n};\n\nstruct dwc3_probe_data {\n\tstruct dwc3 *dwc;\n\tstruct resource *res;\n\tbool ignore_clocks_and_resets;\n\tbool skip_core_init_mode;\n\tstruct dwc3_properties properties;\n};\n\nstruct dwc3_qcom_port {\n\tint qusb2_phy_irq;\n\tint dp_hs_phy_irq;\n\tint dm_hs_phy_irq;\n\tint ss_phy_irq;\n\tenum usb_device_speed usb2_speed;\n};\n\nstruct icc_path;\n\nstruct dwc3_qcom {\n\tstruct device *dev;\n\tvoid *qscratch_base;\n\tstruct dwc3 dwc;\n\tstruct clk_bulk_data *clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n\tstruct dwc3_qcom_port ports[4];\n\tu8 num_ports;\n\tenum usb_dr_mode mode;\n\tbool is_suspended;\n\tbool pm_suspended;\n\tstruct icc_path *icc_path_ddr;\n\tstruct icc_path *icc_path_apps;\n\tenum usb_role current_role;\n};\n\nstruct dwc3_qcom___2 {\n\tstruct device *dev;\n\tvoid *qscratch_base;\n\tstruct platform_device *dwc3;\n\tstruct clk **clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n\tstruct dwc3_qcom_port ports[4];\n\tu8 num_ports;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *host_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block host_nb;\n\tenum usb_dr_mode mode;\n\tbool is_suspended;\n\tbool pm_suspended;\n\tstruct icc_path *icc_path_ddr;\n\tstruct icc_path *icc_path_apps;\n};\n\nstruct dwc3_trb {\n\tu32 bpl;\n\tu32 bph;\n\tu32 size;\n\tu32 ctrl;\n};\n\nstruct plat_stmmacenet_data;\n\nstruct stmmac_resources;\n\nstruct dwc_eth_dwmac_data {\n\tint (*probe)(struct platform_device *, struct plat_stmmacenet_data *, struct stmmac_resources *);\n\tvoid (*remove)(struct platform_device *);\n\tconst char *stmmac_clk_name;\n};\n\nstruct dwc_pcie_vsec_id {\n\tu16 vendor_id;\n\tu16 vsec_id;\n\tu8 vsec_rev;\n};\n\nstruct dwmac4_addrs {\n\tu32 dma_chan;\n\tu32 dma_chan_offset;\n\tu32 mtl_chan;\n\tu32 mtl_chan_offset;\n\tu32 mtl_ets_ctrl;\n\tu32 mtl_ets_ctrl_offset;\n\tu32 mtl_txq_weight;\n\tu32 mtl_txq_weight_offset;\n\tu32 mtl_send_slp_cred;\n\tu32 mtl_send_slp_cred_offset;\n\tu32 mtl_high_cred;\n\tu32 mtl_high_cred_offset;\n\tu32 mtl_low_cred;\n\tu32 mtl_low_cred_offset;\n};\n\nstruct dwmac5_error_desc;\n\nstruct dwmac5_error {\n\tconst struct dwmac5_error_desc *desc;\n};\n\nstruct dwmac5_error_desc {\n\tbool valid;\n\tconst char *desc;\n\tconst char *detailed_desc;\n};\n\nstruct dwxgmac3_error_desc;\n\nstruct dwxgmac3_error {\n\tconst struct dwxgmac3_error_desc *desc;\n};\n\nstruct dwxgmac3_error_desc {\n\tbool valid;\n\tconst char *desc;\n\tconst char *detailed_desc;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct dyn_event_operations;\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(const char *);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct e1000_hw;\n\nstruct e1000_mac_operations {\n\ts32 (*id_led_init)(struct e1000_hw *);\n\ts32 (*blink_led)(struct e1000_hw *);\n\tbool (*check_mng_mode)(struct e1000_hw *);\n\ts32 (*check_for_link)(struct e1000_hw *);\n\ts32 (*cleanup_led)(struct e1000_hw *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw *);\n\tvoid (*clear_vfta)(struct e1000_hw *);\n\ts32 (*get_bus_info)(struct e1000_hw *);\n\tvoid (*set_lan_id)(struct e1000_hw *);\n\ts32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw *);\n\ts32 (*led_off)(struct e1000_hw *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw *);\n\ts32 (*init_hw)(struct e1000_hw *);\n\ts32 (*setup_link)(struct e1000_hw *);\n\ts32 (*setup_physical_interface)(struct e1000_hw *);\n\ts32 (*setup_led)(struct e1000_hw *);\n\tvoid (*write_vfta)(struct e1000_hw *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw *);\n\tint (*rar_set)(struct e1000_hw *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw *);\n\tu32 (*rar_get_count)(struct e1000_hw *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type type;\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tenum e1000_serdes_link_state serdes_link_state;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tu16 refresh_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_phy_operations {\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*cfg_on_link_up)(struct e1000_hw *);\n\ts32 (*check_polarity)(struct e1000_hw *);\n\ts32 (*check_reset_block)(struct e1000_hw *);\n\ts32 (*commit)(struct e1000_hw *);\n\ts32 (*force_speed_duplex)(struct e1000_hw *);\n\ts32 (*get_cfg_done)(struct e1000_hw *);\n\ts32 (*get_cable_length)(struct e1000_hw *);\n\ts32 (*get_info)(struct e1000_hw *);\n\ts32 (*set_page)(struct e1000_hw *, u16);\n\ts32 (*read_reg)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\ts32 (*reset)(struct e1000_hw *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*write_reg)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw *);\n\tvoid (*power_down)(struct e1000_hw *);\n};\n\nstruct e1000_phy_info {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tu32 retry_count;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n\tbool retry_enabled;\n};\n\nstruct e1000_nvm_operations {\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*read)(struct e1000_hw *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\tvoid (*reload)(struct e1000_hw *);\n\ts32 (*update)(struct e1000_hw *);\n\ts32 (*valid_led_default)(struct e1000_hw *, u16 *);\n\ts32 (*validate)(struct e1000_hw *);\n\ts32 (*write)(struct e1000_hw *, u16, u16, u16 *);\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type___2 type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_width width;\n\tu16 func;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\nstruct e1000_dev_spec_82571 {\n\tbool laa_is_present;\n\tu32 smb_counter;\n};\n\nstruct e1000_dev_spec_80003es2lan {\n\tbool mdic_wa_enable;\n};\n\nstruct e1000_shadow_ram {\n\tu16 value;\n\tbool modified;\n};\n\nstruct e1000_dev_spec_ich8lan {\n\tbool kmrn_lock_loss_workaround_enabled;\n\tstruct e1000_shadow_ram shadow_ram[2048];\n\tbool nvm_k1_enabled;\n\tbool eee_disable;\n\tu16 eee_lp_ability;\n\tenum e1000_ulp_state ulp_state;\n};\n\nstruct e1000_adapter;\n\nstruct e1000_hw {\n\tstruct e1000_adapter *adapter;\n\tvoid *hw_addr;\n\tvoid *flash_address;\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82571 e82571;\n\t\tstruct e1000_dev_spec_80003es2lan e80003es2lan;\n\t\tstruct e1000_dev_spec_ich8lan ich8lan;\n\t} dev_spec;\n};\n\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_phy_regs {\n\tu16 bmcr;\n\tu16 bmsr;\n\tu16 advertise;\n\tu16 lpa;\n\tu16 expansion;\n\tu16 ctrl1000;\n\tu16 stat1000;\n\tu16 estatus;\n};\n\nstruct e1000_buffer;\n\nstruct e1000_ring {\n\tstruct e1000_adapter *adapter;\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\tvoid *head;\n\tvoid *tail;\n\tstruct e1000_buffer *buffer_info;\n\tchar name[21];\n\tu32 ims_val;\n\tu32 itr_val;\n\tvoid *itr_register;\n\tint set_itr;\n\tstruct sk_buff *rx_skb_top;\n};\n\nstruct ifreq;\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct e1000_info;\n\nstruct msix_entry;\n\nstruct e1000_adapter {\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tstruct timer_list blink_timer;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tconst struct e1000_info *ei;\n\tlong unsigned int active_vlans[128];\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu16 mng_vlan_id;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu16 eeprom_vers;\n\tlong unsigned int state;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tstruct e1000_ring *tx_ring;\n\tu32 tx_fifo_limit;\n\tstruct napi_struct napi;\n\tunsigned int uncorr_errors;\n\tunsigned int corr_errors;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tbool detect_tx_hung;\n\tbool tx_hang_recheck;\n\tu8 tx_timeout_factor;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tlong: 32;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 gotc;\n\tlong: 32;\n\tu64 gotc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu32 tx_dma_failed;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tbool (*clean_rx)(struct e1000_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_ring *, int, gfp_t);\n\tstruct e1000_ring *rx_ring;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tlong: 32;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu64 rx_hdr_split;\n\tu32 gorc;\n\tlong: 32;\n\tu64 gorc_old;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_dma_failed;\n\tu32 rx_hwtstamp_cleared;\n\tunsigned int rx_ps_pages;\n\tu16 rx_ps_bsize0;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw hw;\n\tspinlock_t stats64_lock;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_phy_info phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tstruct e1000_phy_regs phy_regs;\n\tstruct e1000_ring test_tx_ring;\n\tstruct e1000_ring test_rx_ring;\n\tu32 test_icr;\n\tu32 msg_enable;\n\tunsigned int num_vectors;\n\tstruct msix_entry *msix_entries;\n\tint int_mode;\n\tu32 eiac_mask;\n\tu32 eeprom_wol;\n\tu32 wol;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\tbool fc_autoneg;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tstruct work_struct downshift_task;\n\tstruct work_struct update_phy_task;\n\tstruct work_struct print_hang_task;\n\tint phy_hang_count;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tstruct kernel_hwtstamp_config hwtstamp_config;\n\tstruct delayed_work systim_overflow_work;\n\tstruct sk_buff *tx_hwtstamp_skb;\n\tlong unsigned int tx_hwtstamp_start;\n\tstruct work_struct tx_hwtstamp_work;\n\tspinlock_t systim_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct pm_qos_request pm_qos_req;\n\tlong int ptp_delta;\n\tu16 eee_advert;\n\tlong: 32;\n};\n\nunion e1000_adv_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr;\n\t\t__le64 hdr_addr;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\t__le16 pkt_info;\n\t\t\t\t__le16 hdr_info;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nstruct e1000_adv_tx_context_desc {\n\t__le32 vlan_macip_lens;\n\t__le32 seqnum_seed;\n\t__le32 type_tucmd_mlhl;\n\t__le32 mss_l4len_idx;\n};\n\nunion e1000_adv_tx_desc {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le32 cmd_type_len;\n\t\t__le32 olinfo_status;\n\t} read;\n\tstruct {\n\t\t__le64 rsvd;\n\t\t__le32 nxtseq_seed;\n\t\t__le32 status;\n\t} wb;\n};\n\nstruct e1000_ps_page;\n\nstruct e1000_buffer {\n\tdma_addr_t dma;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int time_stamp;\n\t\t\tu16 length;\n\t\t\tu16 next_to_watch;\n\t\t\tunsigned int segs;\n\t\t\tunsigned int bytecount;\n\t\t\tu16 mapped_as_page;\n\t\t};\n\t\tstruct {\n\t\t\tstruct e1000_ps_page *ps_pages;\n\t\t\tstruct page *page;\n\t\t};\n\t};\n};\n\nstruct e1000_bus_info___2 {\n\tenum e1000_bus_type type;\n\tenum e1000_bus_speed speed;\n\tenum e1000_bus_width width;\n\tu32 snoop;\n\tu16 func;\n\tu16 pci_cmd_word;\n};\n\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss;\n\t\t\tu8 ipcso;\n\t\t\t__le16 ipcse;\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss;\n\t\t\tu8 tucso;\n\t\t\t__le16 tucse;\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 hdr_len;\n\t\t\t__le16 mss;\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\nstruct e1000_sfp_flags {\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e10_base_bx10: 1;\n\tu8 e10_base_px: 1;\n};\n\nstruct e1000_dev_spec_82575 {\n\tbool sgmii_active;\n\tbool global_device_reset;\n\tbool eee_disable;\n\tbool clear_semaphore_once;\n\tstruct e1000_sfp_flags eth_flags;\n\tbool module_plugged;\n\tu8 media_port;\n\tbool media_changed;\n\tbool mas_capable;\n};\n\nstruct e1000_fc_info___2 {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_fw_version {\n\tu32 etrack_id;\n\tu16 eep_major;\n\tu16 eep_minor;\n\tu16 eep_build;\n\tu8 invm_major;\n\tu8 invm_minor;\n\tu8 invm_img_type;\n\tbool or_valid;\n\tu16 or_major;\n\tu16 or_build;\n\tu16 or_patch;\n};\n\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\nstruct e1000_hw___2;\n\nstruct e1000_mac_operations___2 {\n\ts32 (*check_for_link)(struct e1000_hw___2 *);\n\ts32 (*reset_hw)(struct e1000_hw___2 *);\n\ts32 (*init_hw)(struct e1000_hw___2 *);\n\tbool (*check_mng_mode)(struct e1000_hw___2 *);\n\ts32 (*setup_physical_interface)(struct e1000_hw___2 *);\n\tvoid (*rar_set)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw___2 *);\n\ts32 (*get_speed_and_duplex)(struct e1000_hw___2 *, u16 *, u16 *);\n\ts32 (*acquire_swfw_sync)(struct e1000_hw___2 *, u16);\n\tvoid (*release_swfw_sync)(struct e1000_hw___2 *, u16);\n\ts32 (*get_thermal_sensor_data)(struct e1000_hw___2 *);\n\ts32 (*init_thermal_sensor_thresh)(struct e1000_hw___2 *);\n\tvoid (*write_vfta)(struct e1000_hw___2 *, u32, u32);\n};\n\nstruct e1000_thermal_diode_data {\n\tu8 location;\n\tu8 temp;\n\tu8 caution_thresh;\n\tu8 max_op_thresh;\n};\n\nstruct e1000_thermal_sensor_data {\n\tstruct e1000_thermal_diode_data sensor[3];\n};\n\nstruct e1000_mac_info___2 {\n\tstruct e1000_mac_operations___2 ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type___2 type;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 txcw;\n\tu16 mta_reg_count;\n\tu16 uta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool arc_subsystem_valid;\n\tbool asf_firmware_present;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool disable_hw_init_bits;\n\tbool get_link_status;\n\tbool ifs_params_forced;\n\tbool in_ifs_mode;\n\tbool report_tx_early;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tstruct e1000_thermal_sensor_data thermal_sensor_data;\n};\n\nstruct e1000_phy_operations___2 {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*check_polarity)(struct e1000_hw___2 *);\n\ts32 (*check_reset_block)(struct e1000_hw___2 *);\n\ts32 (*force_speed_duplex)(struct e1000_hw___2 *);\n\ts32 (*get_cfg_done)(struct e1000_hw___2 *);\n\ts32 (*get_cable_length)(struct e1000_hw___2 *);\n\ts32 (*get_phy_info)(struct e1000_hw___2 *);\n\ts32 (*read_reg)(struct e1000_hw___2 *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\ts32 (*reset)(struct e1000_hw___2 *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*write_reg)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*read_i2c_byte)(struct e1000_hw___2 *, u8, u8, u8 *);\n\ts32 (*write_i2c_byte)(struct e1000_hw___2 *, u8, u8, u8);\n};\n\nstruct e1000_phy_info___2 {\n\tstruct e1000_phy_operations___2 ops;\n\tenum e1000_phy_type___2 type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu16 pair_length[4];\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool reset_disable;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n};\n\nstruct e1000_nvm_operations___2 {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*read)(struct e1000_hw___2 *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\ts32 (*write)(struct e1000_hw___2 *, u16, u16, u16 *);\n\ts32 (*update)(struct e1000_hw___2 *);\n\ts32 (*validate)(struct e1000_hw___2 *);\n\ts32 (*valid_led_default)(struct e1000_hw___2 *, u16 *);\n};\n\nstruct e1000_nvm_info___2 {\n\tstruct e1000_nvm_operations___2 ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_mbx_operations {\n\ts32 (*init_params)(struct e1000_hw___2 *);\n\ts32 (*read)(struct e1000_hw___2 *, u32 *, u16, u16, bool);\n\ts32 (*write)(struct e1000_hw___2 *, u32 *, u16, u16);\n\ts32 (*read_posted)(struct e1000_hw___2 *, u32 *, u16, u16);\n\ts32 (*write_posted)(struct e1000_hw___2 *, u32 *, u16, u16);\n\ts32 (*check_for_msg)(struct e1000_hw___2 *, u16);\n\ts32 (*check_for_ack)(struct e1000_hw___2 *, u16);\n\ts32 (*check_for_rst)(struct e1000_hw___2 *, u16);\n\ts32 (*unlock)(struct e1000_hw___2 *, u16);\n};\n\nstruct e1000_mbx_stats {\n\tu32 msgs_tx;\n\tu32 msgs_rx;\n\tu32 acks;\n\tu32 reqs;\n\tu32 rsts;\n};\n\nstruct e1000_mbx_info {\n\tstruct e1000_mbx_operations ops;\n\tstruct e1000_mbx_stats stats;\n\tu32 timeout;\n\tu32 usec_delay;\n\tu16 size;\n};\n\nstruct e1000_hw___2 {\n\tvoid *back;\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tlong unsigned int io_base;\n\tstruct e1000_mac_info___2 mac;\n\tstruct e1000_fc_info___2 fc;\n\tstruct e1000_phy_info___2 phy;\n\tstruct e1000_nvm_info___2 nvm;\n\tstruct e1000_bus_info___2 bus;\n\tstruct e1000_mbx_info mbx;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82575 _82575;\n\t} dev_spec;\n\tu16 device_id;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_device_id;\n\tu16 vendor_id;\n\tu8 revision_id;\n};\n\nstruct e1000_hw_stats___2 {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n\tu64 cbtmpc;\n\tu64 htdpmc;\n\tu64 cbrdpc;\n\tu64 cbrmpc;\n\tu64 rpthc;\n\tu64 hgptc;\n\tu64 htcbdpc;\n\tu64 hgorc;\n\tu64 hgotc;\n\tu64 lenerrs;\n\tu64 scvpc;\n\tu64 hrmpc;\n\tu64 doosync;\n\tu64 o2bgptc;\n\tu64 o2bspc;\n\tu64 b2ospc;\n\tu64 b2ogprc;\n};\n\nstruct e1000_info___2 {\n\ts32 (*get_invariants)(struct e1000_hw___2 *);\n\tstruct e1000_mac_operations___2 *mac_ops;\n\tconst struct e1000_phy_operations___2 *phy_ops;\n\tstruct e1000_nvm_operations___2 *nvm_ops;\n};\n\nstruct e1000_info {\n\tenum e1000_mac_type mac;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\ts32 (*get_variants)(struct e1000_adapter *);\n\tconst struct e1000_mac_operations *mac_ops;\n\tconst struct e1000_phy_operations *phy_ops;\n\tconst struct e1000_nvm_operations *nvm_ops;\n};\n\nstruct e1000_opt_list {\n\tint i;\n\tchar *str;\n};\n\nstruct e1000_option {\n\tenum {\n\t\tenable_option = 0,\n\t\trange_option = 1,\n\t\tlist_option = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tstruct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_ps_page {\n\tstruct page *page;\n\tlong: 32;\n\tu64 dma;\n};\n\nstruct e1000_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t__le64 buffer_addr[4];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length0;\n\t\t\t__le16 vlan;\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t__le16 length[3];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb;\n};\n\nstruct e1000_stats {\n\tchar stat_string[32];\n\tint type;\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct e1000_tx_desc {\n\t__le64 buffer_addr;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length;\n\t\t\tu8 cso;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 css;\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\nstruct rb_node_key {\n\tstruct rb_node node;\n\tsize_t key;\n};\n\nstruct e_node {\n\tstruct rb_node_key start;\n\tstruct rb_node_key count;\n};\n\nstruct usb_device;\n\nstruct each_dev_arg {\n\tvoid *data;\n\tint (*fn)(struct usb_device *, void *);\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tlong: 32;\n\tstruct uart_port port;\n\tchar options[32];\n\tunsigned int baud;\n\tlong: 32;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nstruct ebi2_xmem_prop {\n\tconst char *prop;\n\tu32 max;\n\tbool slowreg;\n\tu16 shift;\n};\n\nstruct ecx_plat_data {\n\tu32 n_ports;\n\tu32 pre_clocks;\n\tu32 post_clocks;\n\tstruct gpio_desc *sgpio_gpiod[3];\n\tu32 sgpio_pattern;\n\tu32 port_to_sgpio[8];\n};\n\nstruct td;\n\nstruct ed {\n\t__hc32 hwINFO;\n\t__hc32 hwTailP;\n\t__hc32 hwHeadP;\n\t__hc32 hwNextED;\n\tdma_addr_t dma;\n\tstruct td *dummy;\n\tstruct ed *ed_next;\n\tstruct ed *ed_prev;\n\tstruct list_head td_list;\n\tstruct list_head in_use_list;\n\tu8 state;\n\tu8 type;\n\tu8 branch;\n\tu16 interval;\n\tu16 load;\n\tu16 last_iso;\n\tu16 tick;\n\tunsigned int takeback_wdh_cnt;\n\tstruct td *pending_td;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct edac_scrub_ops;\n\nstruct edac_ecs_ops;\n\nstruct edac_mem_repair_ops;\n\nstruct edac_dev_data {\n\tunion {\n\t\tconst struct edac_scrub_ops *scrub_ops;\n\t\tconst struct edac_ecs_ops *ecs_ops;\n\t\tconst struct edac_mem_repair_ops *mem_repair_ops;\n\t};\n\tu8 instance;\n\tvoid *private;\n};\n\nstruct edac_dev_feat_ctx {\n\tstruct device dev;\n\tvoid *private;\n\tstruct edac_dev_data *scrub;\n\tstruct edac_dev_data ecs;\n\tstruct edac_dev_data *mem_repair;\n};\n\nstruct edac_ecs_ex_info {\n\tu16 num_media_frus;\n};\n\nstruct edac_dev_feature {\n\tenum edac_dev_feat ft_type;\n\tu8 instance;\n\tunion {\n\t\tconst struct edac_scrub_ops *scrub_ops;\n\t\tconst struct edac_ecs_ops *ecs_ops;\n\t\tconst struct edac_mem_repair_ops *mem_repair_ops;\n\t};\n\tvoid *ctx;\n\tstruct edac_ecs_ex_info ecs_info;\n};\n\nstruct edac_dev_sysfs_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct edac_dev_sysfs_block_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n};\n\nstruct edac_device_counter {\n\tu32 ue_count;\n\tu32 ce_count;\n};\n\nstruct edac_device_instance;\n\nstruct edac_device_block {\n\tstruct edac_device_instance *instance;\n\tchar name[32];\n\tstruct edac_device_counter counters;\n\tint nr_attribs;\n\tstruct edac_dev_sysfs_block_attribute *block_attributes;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_ctl_info {\n\tstruct list_head link;\n\tstruct module *owner;\n\tint dev_idx;\n\tint log_ue;\n\tint log_ce;\n\tint panic_on_ue;\n\tunsigned int poll_msec;\n\tlong unsigned int delay;\n\tstruct edac_dev_sysfs_attribute *sysfs_attributes;\n\tconst struct bus_type *edac_subsys;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_device_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tchar name[32];\n\tu32 nr_instances;\n\tstruct edac_device_instance *instances;\n\tstruct edac_device_block *blocks;\n\tstruct edac_device_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_instance {\n\tstruct edac_device_ctl_info *ctl;\n\tchar name[35];\n\tstruct edac_device_counter counters;\n\tu32 nr_blocks;\n\tstruct edac_device_block *blocks;\n\tstruct kobject kobj;\n};\n\nstruct edac_ecs_ops {\n\tint (*get_log_entry_type)(struct device *, void *, int, u32 *);\n\tint (*set_log_entry_type)(struct device *, void *, int, u32);\n\tint (*get_mode)(struct device *, void *, int, u32 *);\n\tint (*set_mode)(struct device *, void *, int, u32);\n\tint (*reset)(struct device *, void *, int, u32);\n\tint (*get_threshold)(struct device *, void *, int, u32 *);\n\tint (*set_threshold)(struct device *, void *, int, u32);\n};\n\nstruct edac_mc_layer {\n\tenum edac_mc_layer_type type;\n\tunsigned int size;\n\tbool is_virt_csrow;\n};\n\nstruct edac_mem_repair_ops {\n\tint (*get_repair_type)(struct device *, void *, const char **);\n\tint (*get_persist_mode)(struct device *, void *, bool *);\n\tint (*set_persist_mode)(struct device *, void *, bool);\n\tint (*get_repair_safe_when_in_use)(struct device *, void *, bool *);\n\tint (*get_hpa)(struct device *, void *, u64 *);\n\tint (*set_hpa)(struct device *, void *, u64);\n\tint (*get_min_hpa)(struct device *, void *, u64 *);\n\tint (*get_max_hpa)(struct device *, void *, u64 *);\n\tint (*get_dpa)(struct device *, void *, u64 *);\n\tint (*set_dpa)(struct device *, void *, u64);\n\tint (*get_min_dpa)(struct device *, void *, u64 *);\n\tint (*get_max_dpa)(struct device *, void *, u64 *);\n\tint (*get_nibble_mask)(struct device *, void *, u32 *);\n\tint (*set_nibble_mask)(struct device *, void *, u32);\n\tint (*get_bank_group)(struct device *, void *, u32 *);\n\tint (*set_bank_group)(struct device *, void *, u32);\n\tint (*get_bank)(struct device *, void *, u32 *);\n\tint (*set_bank)(struct device *, void *, u32);\n\tint (*get_rank)(struct device *, void *, u32 *);\n\tint (*set_rank)(struct device *, void *, u32);\n\tint (*get_row)(struct device *, void *, u32 *);\n\tint (*set_row)(struct device *, void *, u32);\n\tint (*get_column)(struct device *, void *, u32 *);\n\tint (*set_column)(struct device *, void *, u32);\n\tint (*get_channel)(struct device *, void *, u32 *);\n\tint (*set_channel)(struct device *, void *, u32);\n\tint (*get_sub_channel)(struct device *, void *, u32 *);\n\tint (*set_sub_channel)(struct device *, void *, u32);\n\tint (*do_repair)(struct device *, void *, u32);\n};\n\nstruct edac_pci_counter {\n\tatomic_t pe_count;\n\tatomic_t npe_count;\n};\n\nstruct edac_pci_ctl_info {\n\tstruct list_head link;\n\tint pci_idx;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_pci_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tchar name[32];\n\tstruct edac_pci_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_pci_dev_attribute {\n\tstruct attribute attr;\n\tvoid *value;\n\tssize_t (*show)(void *, char *);\n\tssize_t (*store)(void *, const char *, size_t);\n};\n\nstruct edac_pci_gen_data {\n\tint edac_idx;\n};\n\nstruct edac_raw_error_desc {\n\tchar location[256];\n\tchar label[296];\n\tlong int grain;\n\tu16 error_count;\n\tenum hw_event_mc_err_type type;\n\tint top_layer;\n\tint mid_layer;\n\tint low_layer;\n\tlong unsigned int page_frame_number;\n\tlong unsigned int offset_in_page;\n\tlong unsigned int syndrome;\n\tconst char *msg;\n\tconst char *other_detail;\n};\n\nstruct edac_scrub_ops {\n\tint (*read_addr)(struct device *, void *, u64 *);\n\tint (*read_size)(struct device *, void *, u64 *);\n\tint (*write_addr)(struct device *, void *, u64);\n\tint (*write_size)(struct device *, void *, u64);\n\tint (*get_enabled_bg)(struct device *, void *, bool *);\n\tint (*set_enabled_bg)(struct device *, void *, bool);\n\tint (*get_min_cycle)(struct device *, void *, u32 *);\n\tint (*get_max_cycle)(struct device *, void *, u32 *);\n\tint (*get_cycle_duration)(struct device *, void *, u32 *);\n\tint (*set_cycle_duration)(struct device *, void *, u32);\n};\n\nstruct est_timings {\n\tu8 t1;\n\tu8 t2;\n\tu8 mfg_rsvd;\n};\n\nstruct edid {\n\tu8 header[8];\n\tunion {\n\t\tstruct drm_edid_product_id product_id;\n\t\tstruct {\n\t\t\tu8 mfg_id[2];\n\t\t\tu8 prod_code[2];\n\t\t\tu32 serial;\n\t\t\tu8 mfg_week;\n\t\t\tu8 mfg_year;\n\t\t} __attribute__((packed));\n\t};\n\tu8 version;\n\tu8 revision;\n\tu8 input;\n\tu8 width_cm;\n\tu8 height_cm;\n\tu8 gamma;\n\tu8 features;\n\tu8 red_green_lo;\n\tu8 blue_white_lo;\n\tu8 red_x;\n\tu8 red_y;\n\tu8 green_x;\n\tu8 green_y;\n\tu8 blue_x;\n\tu8 blue_y;\n\tu8 white_x;\n\tu8 white_y;\n\tstruct est_timings established_timings;\n\tstruct std_timing standard_timings[8];\n\tstruct detailed_timing detailed_timings[4];\n\tu8 extensions;\n\tu8 checksum;\n};\n\nstruct edid_quirk {\n\tconst struct drm_edid_ident ident;\n\tu32 quirks;\n};\n\nstruct edma_soc_info;\n\nstruct edma_chan;\n\nstruct edma_tc;\n\nstruct edma_cc {\n\tstruct device *dev;\n\tstruct edma_soc_info *info;\n\tvoid *base;\n\tint id;\n\tbool legacy_mode;\n\tunsigned int num_channels;\n\tunsigned int num_qchannels;\n\tunsigned int num_region;\n\tunsigned int num_slots;\n\tunsigned int num_tc;\n\tbool chmap_exist;\n\tenum dma_event_q default_queue;\n\tunsigned int ccint;\n\tunsigned int ccerrint;\n\tlong unsigned int *slot_inuse;\n\tlong unsigned int *channels_mask;\n\tstruct dma_device dma_slave;\n\tstruct dma_device *dma_memcpy;\n\tstruct edma_chan *slave_chans;\n\tstruct edma_tc *tc_list;\n\tint dummy_slot;\n};\n\nstruct edma_desc;\n\nstruct edma_chan {\n\tstruct virt_dma_chan vchan;\n\tstruct list_head node;\n\tstruct edma_desc *edesc;\n\tstruct edma_cc *ecc;\n\tstruct edma_tc *tc;\n\tint ch_num;\n\tbool alloced;\n\tbool hw_triggered;\n\tint slot[20];\n\tint missed;\n\tstruct dma_slave_config cfg;\n};\n\nstruct edmacc_param {\n\tu32 opt;\n\tu32 src;\n\tu32 a_b_cnt;\n\tu32 dst;\n\tu32 src_dst_bidx;\n\tu32 link_bcntrld;\n\tu32 src_dst_cidx;\n\tu32 ccnt;\n};\n\nstruct edma_pset {\n\tu32 len;\n\tdma_addr_t addr;\n\tstruct edmacc_param param;\n};\n\nstruct edma_desc {\n\tstruct virt_dma_desc vdesc;\n\tstruct list_head node;\n\tenum dma_transfer_direction direction;\n\tint cyclic;\n\tbool polled;\n\tint absync;\n\tint pset_nr;\n\tstruct edma_chan *echan;\n\tint processed;\n\tint processed_stat;\n\tu32 sg_len;\n\tu32 residue;\n\tu32 residue_stat;\n\tstruct edma_pset pset[0];\n};\n\nstruct edma_regs {\n\tvoid *cr;\n\tvoid *es;\n\tvoid *erqh;\n\tvoid *erql;\n\tvoid *eeih;\n\tvoid *eeil;\n\tvoid *seei;\n\tvoid *ceei;\n\tvoid *serq;\n\tvoid *cerq;\n\tvoid *cint;\n\tvoid *cerr;\n\tvoid *ssrt;\n\tvoid *cdne;\n\tvoid *inth;\n\tvoid *intl;\n\tvoid *errh;\n\tvoid *errl;\n};\n\nstruct edma_rsv_info {\n\tconst s16 (*rsv_chans)[2];\n\tconst s16 (*rsv_slots)[2];\n};\n\nstruct edma_soc_info {\n\tenum dma_event_q default_queue;\n\tstruct edma_rsv_info *rsv;\n\ts32 *memcpy_channels;\n\ts8 (*queue_priority_mapping)[2];\n\tconst s16 (*xbar_chans)[2];\n\tconst struct dma_slave_map *slave_map;\n\tint slavecnt;\n};\n\nstruct edma_tc {\n\tu16 id;\n};\n\nstruct panel_delay;\n\nstruct edp_panel_entry {\n\tconst struct drm_edid_ident ident;\n\tconst struct panel_delay *delay;\n\tconst struct drm_display_mode *override_edid_mode;\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[4];\n\tlong unsigned int advertised[4];\n\tlong unsigned int lp_advertised[4];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct eeprom_93cx6 {\n\tvoid *data;\n\tvoid (*register_read)(struct eeprom_93cx6 *);\n\tvoid (*register_write)(struct eeprom_93cx6 *);\n\tint width;\n\tunsigned int quirks;\n\tchar drive_data;\n\tchar reg_data_in;\n\tchar reg_data_out;\n\tchar reg_data_clock;\n\tchar reg_chip_select;\n};\n\nstruct eeprom_data {\n\tstruct bin_attribute bin;\n\tspinlock_t buffer_lock;\n\tu16 buffer_idx;\n\tu16 address_mask;\n\tu8 num_address_bytes;\n\tu8 idx_write_cnt;\n\tbool read_only;\n\tu8 buffer[0];\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\nstruct efi_memory_map {\n\tphys_addr_t phys_map;\n\tvoid *map;\n\tvoid *map_end;\n\tint nr_map;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nstruct efi {\n\tconst efi_runtime_services_t *runtime;\n\tunsigned int runtime_version;\n\tunsigned int runtime_supported_mask;\n\tlong unsigned int acpi;\n\tlong unsigned int acpi20;\n\tlong unsigned int smbios;\n\tlong unsigned int smbios3;\n\tlong unsigned int esrt;\n\tlong unsigned int tpm_log;\n\tlong unsigned int tpm_final_log;\n\tlong unsigned int ovmf_debug_log;\n\tlong unsigned int mokvar_table;\n\tlong unsigned int coco_secret;\n\tlong unsigned int unaccepted;\n\tefi_get_time_t *get_time;\n\tefi_set_time_t *set_time;\n\tefi_get_wakeup_time_t *get_wakeup_time;\n\tefi_set_wakeup_time_t *set_wakeup_time;\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_info_t *query_variable_info;\n\tefi_query_variable_info_t *query_variable_info_nonblocking;\n\tefi_update_capsule_t *update_capsule;\n\tefi_query_capsule_caps_t *query_capsule_caps;\n\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\tefi_reset_system_t *reset_system;\n\tstruct efi_memory_map memmap;\n\tlong unsigned int flags;\n};\n\nstruct efi_arm_entry_state {\n\tu32 cpsr_before_ebs;\n\tu32 sctlr_before_ebs;\n\tu32 cpsr_after_ebs;\n\tu32 sctlr_after_ebs;\n};\n\nstruct efi_memory_map_data {\n\tphys_addr_t phys_map;\n\tlong unsigned int size;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nunion efi_rts_args {\n\tstruct {\n\t\tefi_time_t *time;\n\t\tefi_time_cap_t *capabilities;\n\t} GET_TIME;\n\tstruct {\n\t\tefi_time_t *time;\n\t} SET_TIME;\n\tstruct {\n\t\tefi_bool_t *enabled;\n\t\tefi_bool_t *pending;\n\t\tefi_time_t *time;\n\t} GET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_bool_t enable;\n\t\tefi_time_t *time;\n\t} SET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 *attr;\n\t\tlong unsigned int *data_size;\n\t\tvoid *data;\n\t} GET_VARIABLE;\n\tstruct {\n\t\tlong unsigned int *name_size;\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t} GET_NEXT_VARIABLE;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 attr;\n\t\tlong unsigned int data_size;\n\t\tvoid *data;\n\t} SET_VARIABLE;\n\tstruct {\n\t\tu32 attr;\n\t\tu64 *storage_space;\n\t\tu64 *remaining_space;\n\t\tu64 *max_variable_size;\n\t} QUERY_VARIABLE_INFO;\n\tstruct {\n\t\tu32 *high_count;\n\t} GET_NEXT_HIGH_MONO_COUNT;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tlong unsigned int sg_list;\n\t} UPDATE_CAPSULE;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tu64 *max_size;\n\t\tint *reset_type;\n\t} QUERY_CAPSULE_CAPS;\n\tstruct {\n\t\tefi_status_t (*acpi_prm_handler)(u64, void *);\n\t\tlong: 32;\n\t\tu64 param_buffer_addr;\n\t\tvoid *context;\n\t\tlong: 32;\n\t} ACPI_PRM_HANDLER;\n};\n\nstruct efi_runtime_work {\n\tunion efi_rts_args *args;\n\tefi_status_t status;\n\tstruct work_struct work;\n\tenum efi_rts_ids efi_rts_id;\n\tstruct completion efi_rts_comp;\n\tconst void *caller;\n};\n\nstruct efi_system_resource_entry_v1 {\n\tefi_guid_t fw_class;\n\tu32 fw_type;\n\tu32 fw_version;\n\tu32 lowest_supported_fw_version;\n\tu32 capsule_flags;\n\tu32 last_attempt_version;\n\tu32 last_attempt_status;\n};\n\nstruct efi_system_resource_table {\n\tu32 fw_resource_count;\n\tu32 fw_resource_count_max;\n\tu64 fw_resource_version;\n\tu8 entries[0];\n};\n\nstruct efi_tcg2_final_events_table {\n\tu64 version;\n\tu64 nr_events;\n\tu8 events[0];\n};\n\nstruct efi_unaccepted_memory {\n\tu32 version;\n\tu32 unit_size;\n\tu64 phys_base;\n\tu64 size;\n\tlong unsigned int bitmap[0];\n};\n\nstruct efifb_dmi_info {\n\tchar *optname;\n\tlong unsigned int base;\n\tint stride;\n\tint width;\n\tint height;\n\tint flags;\n};\n\nstruct efifb_mode_fixup {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int linelength;\n};\n\nstruct efifb_par {\n\tu32 pseudo_palette[16];\n\tresource_size_t base;\n\tresource_size_t size;\n};\n\ntypedef efi_status_t efi_query_variable_store_t(u32, long unsigned int, bool);\n\nstruct efivar_operations {\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_store_t *query_variable_store;\n\tefi_query_variable_info_t *query_variable_info;\n};\n\nstruct efivars {\n\tstruct kset *kset;\n\tconst struct efivar_operations *ops;\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_ci_priv {\n\tstruct regulator *reg_vbus;\n\tbool enabled;\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct ehci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\nstruct ehci_qh;\n\nstruct ehci_itd;\n\nstruct ehci_sitd;\n\nstruct ehci_fstn;\n\nunion ehci_shadow {\n\tstruct ehci_qh *qh;\n\tstruct ehci_itd *itd;\n\tstruct ehci_sitd *sitd;\n\tstruct ehci_fstn *fstn;\n\t__le32 *hw_next;\n\tvoid *ptr;\n};\n\nstruct ehci_fstn {\n\t__le32 hw_next;\n\t__le32 hw_prev;\n\tdma_addr_t fstn_dma;\n\tunion ehci_shadow fstn_next;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_regs;\n\nstruct ehci_hcd {\n\tenum ehci_hrtimer_event next_hrtimer_event;\n\tunsigned int enabled_hrtimer_events;\n\tktime_t hr_timeouts[12];\n\tstruct hrtimer hrtimer;\n\tint PSS_poll_count;\n\tint ASS_poll_count;\n\tint died_poll_count;\n\tstruct ehci_caps *caps;\n\tstruct ehci_regs *regs;\n\tstruct ehci_dbg_port *debug;\n\t__u32 hcs_params;\n\tspinlock_t lock;\n\tenum ehci_rh_state rh_state;\n\tbool scanning: 1;\n\tbool need_rescan: 1;\n\tbool intr_unlinking: 1;\n\tbool iaa_in_progress: 1;\n\tbool async_unlinking: 1;\n\tbool shutdown: 1;\n\tstruct ehci_qh *qh_scan_next;\n\tstruct ehci_qh *async;\n\tstruct ehci_qh *dummy;\n\tstruct list_head async_unlink;\n\tstruct list_head async_idle;\n\tunsigned int async_unlink_cycle;\n\tunsigned int async_count;\n\t__le32 old_current;\n\t__le32 old_token;\n\tunsigned int periodic_size;\n\t__le32 *periodic;\n\tdma_addr_t periodic_dma;\n\tstruct list_head intr_qh_list;\n\tunsigned int i_thresh;\n\tunion ehci_shadow *pshadow;\n\tstruct list_head intr_unlink_wait;\n\tstruct list_head intr_unlink;\n\tunsigned int intr_unlink_wait_cycle;\n\tunsigned int intr_unlink_cycle;\n\tunsigned int now_frame;\n\tunsigned int last_iso_frame;\n\tunsigned int intr_count;\n\tunsigned int isoc_count;\n\tunsigned int periodic_count;\n\tunsigned int uframe_periodic_max;\n\tstruct list_head cached_itd_list;\n\tstruct ehci_itd *last_itd_to_free;\n\tstruct list_head cached_sitd_list;\n\tstruct ehci_sitd *last_sitd_to_free;\n\tlong unsigned int reset_done[15];\n\tlong unsigned int bus_suspended;\n\tlong unsigned int companion_ports;\n\tlong unsigned int owned_ports;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int suspended_ports;\n\tlong unsigned int resuming_ports;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *qtd_pool;\n\tstruct dma_pool *itd_pool;\n\tstruct dma_pool *sitd_pool;\n\tunsigned int random_frame;\n\tlong unsigned int next_statechange;\n\tlong: 32;\n\tktime_t last_periodic_enable;\n\tu32 command;\n\tunsigned int no_selective_suspend: 1;\n\tunsigned int has_fsl_port_bug: 1;\n\tunsigned int has_fsl_hs_errata: 1;\n\tunsigned int has_fsl_susp_errata: 1;\n\tunsigned int has_ci_pec_bug: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_capbase: 1;\n\tunsigned int has_amcc_usb23: 1;\n\tunsigned int need_io_watchdog: 1;\n\tunsigned int amd_pll_fix: 1;\n\tunsigned int use_dummy_qh: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int frame_index_bug: 1;\n\tunsigned int need_oc_pp_cycle: 1;\n\tunsigned int imx28_write_fix: 1;\n\tunsigned int spurious_oc: 1;\n\tunsigned int is_aspeed: 1;\n\tunsigned int zx_wakeup_clear_needed: 1;\n\t__le32 *ohci_hcctrl_reg;\n\tunsigned int has_hostpc: 1;\n\tunsigned int has_tdi_phy_lpm: 1;\n\tunsigned int has_ppcd: 1;\n\tu8 sbrn;\n\tu8 bandwidth[64];\n\tu8 tt_budget[64];\n\tstruct list_head tt_list;\n\tlong unsigned int priv[0];\n};\n\nstruct ehci_hcd_omap_platform_data {\n\tenum usbhs_omap_port_mode port_mode[3];\n\tint reset_gpio_port[3];\n\tstruct regulator *regulator[3];\n\tunsigned int phy_reset: 1;\n};\n\nstruct ehci_iso_packet {\n\tu64 bufp;\n\t__le32 transaction;\n\tu8 cross;\n\tu32 buf1;\n\tlong: 32;\n};\n\nstruct ehci_iso_sched {\n\tstruct list_head td_list;\n\tunsigned int span;\n\tunsigned int first_packet;\n\tstruct ehci_iso_packet packet[0];\n};\n\nstruct usb_host_endpoint;\n\nstruct ehci_per_sched {\n\tstruct usb_device *udev;\n\tstruct usb_host_endpoint *ep;\n\tstruct list_head ps_list;\n\tu16 tt_usecs;\n\tu16 cs_mask;\n\tu16 period;\n\tu16 phase;\n\tu8 bw_phase;\n\tu8 phase_uf;\n\tu8 usecs;\n\tu8 c_usecs;\n\tu8 bw_uperiod;\n\tu8 bw_period;\n};\n\nstruct ehci_qh_hw;\n\nstruct ehci_iso_stream {\n\tstruct ehci_qh_hw *hw;\n\tu8 bEndpointAddress;\n\tu8 highspeed;\n\tstruct list_head td_list;\n\tstruct list_head free_list;\n\tstruct ehci_per_sched ps;\n\tunsigned int next_uframe;\n\t__le32 splits;\n\tu16 uperiod;\n\tu16 maxp;\n\tunsigned int bandwidth;\n\t__le32 buf0;\n\t__le32 buf1;\n\t__le32 buf2;\n\t__le32 address;\n};\n\nstruct ehci_itd {\n\t__le32 hw_next;\n\t__le32 hw_transaction[8];\n\t__le32 hw_bufp[7];\n\t__le32 hw_bufp_hi[7];\n\tdma_addr_t itd_dma;\n\tunion ehci_shadow itd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head itd_list;\n\tunsigned int frame;\n\tunsigned int pg;\n\tunsigned int index[8];\n\tlong: 32;\n};\n\nstruct ehci_platform_priv {\n\tstruct clk *clks[4];\n\tstruct reset_control *rsts;\n\tbool reset_on_resume;\n\tbool quirk_poll;\n\tstruct timer_list poll_timer;\n\tstruct delayed_work poll_work;\n};\n\nstruct ehci_qtd;\n\nstruct ehci_qh {\n\tstruct ehci_qh_hw *hw;\n\tdma_addr_t qh_dma;\n\tunion ehci_shadow qh_next;\n\tstruct list_head qtd_list;\n\tstruct list_head intr_node;\n\tstruct ehci_qtd *dummy;\n\tstruct list_head unlink_node;\n\tstruct ehci_per_sched ps;\n\tunsigned int unlink_cycle;\n\tu8 qh_state;\n\tu8 xacterrs;\n\tu8 unlink_reason;\n\tu8 gap_uf;\n\tunsigned int is_out: 1;\n\tunsigned int clearing_tt: 1;\n\tunsigned int dequeue_during_giveback: 1;\n\tunsigned int should_be_inactive: 1;\n};\n\nstruct ehci_qh_hw {\n\t__le32 hw_next;\n\t__le32 hw_info1;\n\t__le32 hw_info2;\n\t__le32 hw_current;\n\t__le32 hw_qtd_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_qtd {\n\t__le32 hw_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tdma_addr_t qtd_dma;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tunion {\n\t\tu32 port_status[15];\n\t\tstruct {\n\t\t\tu32 reserved3[9];\n\t\t\tu32 usbmode;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved4;\n\t\t\tu32 hostpc[15];\n\t\t};\n\t\tu32 brcm_insnreg[4];\n\t};\n\tu32 reserved5[2];\n\tu32 usbmode_ex;\n};\n\nstruct ehci_sitd {\n\t__le32 hw_next;\n\t__le32 hw_fullspeed_ep;\n\t__le32 hw_uframe;\n\t__le32 hw_results;\n\t__le32 hw_buf[2];\n\t__le32 hw_backpointer;\n\t__le32 hw_buf_hi[2];\n\tdma_addr_t sitd_dma;\n\tunion ehci_shadow sitd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head sitd_list;\n\tunsigned int frame;\n\tunsigned int index;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ehci_tt {\n\tu16 bandwidth[8];\n\tstruct list_head tt_list;\n\tstruct list_head ps_list;\n\tstruct usb_tt *usb_tt;\n\tint tt_port;\n};\n\nstruct elan_transport_ops;\n\nstruct elan_tp_data {\n\tstruct i2c_client *client;\n\tstruct input_dev *input;\n\tstruct input_dev *tp_input;\n\tstruct regulator *vcc;\n\tconst struct elan_transport_ops *ops;\n\tstruct completion fw_completion;\n\tbool in_fw_update;\n\tstruct mutex sysfs_mutex;\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tunsigned int width_x;\n\tunsigned int width_y;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tu8 pattern;\n\tu16 product_id;\n\tu8 fw_version;\n\tu8 sm_version;\n\tu8 iap_version;\n\tu16 fw_checksum;\n\tunsigned int report_features;\n\tunsigned int report_len;\n\tint pressure_adjustment;\n\tu8 mode;\n\tu16 ic_type;\n\tu16 fw_validpage_count;\n\tu16 fw_page_size;\n\tu32 fw_signature_address;\n\tu8 min_baseline;\n\tu8 max_baseline;\n\tbool baseline_ready;\n\tu8 clickpad;\n\tbool middle_button;\n\tu32 quirks;\n};\n\nstruct elan_transport_ops {\n\tint (*initialize)(struct i2c_client *);\n\tint (*sleep_control)(struct i2c_client *, bool);\n\tint (*power_control)(struct i2c_client *, bool);\n\tint (*set_mode)(struct i2c_client *, u8);\n\tint (*calibrate)(struct i2c_client *);\n\tint (*calibrate_result)(struct i2c_client *, u8 *);\n\tint (*get_baseline_data)(struct i2c_client *, bool, u8 *);\n\tint (*get_version)(struct i2c_client *, u8, bool, u8 *);\n\tint (*get_sm_version)(struct i2c_client *, u8, u16 *, u8 *, u8 *);\n\tint (*get_checksum)(struct i2c_client *, bool, u16 *);\n\tint (*get_product_id)(struct i2c_client *, u16 *);\n\tint (*get_max)(struct i2c_client *, unsigned int *, unsigned int *);\n\tint (*get_resolution)(struct i2c_client *, u8 *, u8 *);\n\tint (*get_num_traces)(struct i2c_client *, unsigned int *, unsigned int *);\n\tint (*iap_get_mode)(struct i2c_client *, enum tp_mode *);\n\tint (*iap_reset)(struct i2c_client *);\n\tint (*prepare_fw_update)(struct i2c_client *, u16, u8, u16);\n\tint (*write_fw_block)(struct i2c_client *, u16, const u8 *, u16, int);\n\tint (*finish_fw_update)(struct i2c_client *, struct completion *);\n\tint (*get_report_features)(struct i2c_client *, u8, unsigned int *, unsigned int *);\n\tint (*get_report)(struct i2c_client *, u8 *, unsigned int);\n\tint (*get_pressure_adjustment)(struct i2c_client *, int *);\n\tint (*get_pattern)(struct i2c_client *, u8 *);\n};\n\nstruct elantech_attr_data {\n\tsize_t field_offset;\n\tunsigned char reg;\n};\n\nstruct finger_pos {\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct elantech_device_info {\n\tunsigned char capabilities[3];\n\tunsigned char samples[3];\n\tunsigned char debug;\n\tunsigned char hw_version;\n\tunsigned char pattern;\n\tunsigned int fw_version;\n\tunsigned int ic_version;\n\tunsigned int product_id;\n\tunsigned int x_min;\n\tunsigned int y_min;\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tunsigned int x_traces;\n\tunsigned int y_traces;\n\tunsigned int width;\n\tunsigned int bus;\n\tbool paritycheck;\n\tbool jumpy_cursor;\n\tbool reports_pressure;\n\tbool crc_enabled;\n\tbool set_hw_resolution;\n\tbool has_trackpoint;\n\tbool has_middle_button;\n\tint (*send_cmd)(struct psmouse *, unsigned char, unsigned char *);\n};\n\nstruct elantech_data {\n\tstruct input_dev *tp_dev;\n\tchar tp_phys[32];\n\tunsigned char reg_07;\n\tunsigned char reg_10;\n\tunsigned char reg_11;\n\tunsigned char reg_20;\n\tunsigned char reg_21;\n\tunsigned char reg_22;\n\tunsigned char reg_23;\n\tunsigned char reg_24;\n\tunsigned char reg_25;\n\tunsigned char reg_26;\n\tunsigned int single_finger_reports;\n\tunsigned int y_max;\n\tunsigned int width;\n\tstruct finger_pos mt[5];\n\tunsigned char parity[256];\n\tstruct elantech_device_info info;\n\tvoid (*original_set_rate)(struct psmouse *, unsigned int);\n};\n\nstruct elevator_queue;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf32_rel {\n\tElf32_Addr r_offset;\n\tElf32_Word r_info;\n};\n\ntypedef struct elf32_rel Elf32_Rel;\n\nstruct elf32_shdr {\n\tElf32_Word sh_name;\n\tElf32_Word sh_type;\n\tElf32_Word sh_flags;\n\tElf32_Addr sh_addr;\n\tElf32_Off sh_offset;\n\tElf32_Word sh_size;\n\tElf32_Word sh_link;\n\tElf32_Word sh_info;\n\tElf32_Word sh_addralign;\n\tElf32_Word sh_entsize;\n};\n\ntypedef struct elf32_shdr Elf32_Shdr;\n\nstruct elf32_sym {\n\tElf32_Word st_name;\n\tElf32_Addr st_value;\n\tElf32_Word st_size;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf32_Half st_shndx;\n};\n\ntypedef struct elf32_sym Elf32_Sym;\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elfinfo {\n\tElf32_Ehdr *hdr;\n\tElf32_Sym *dynsym;\n\tlong unsigned int dynsymsize;\n\tchar *dynstr;\n};\n\nstruct elm_errorvec {\n\tbool error_reported;\n\tbool error_uncorrectable;\n\tint error_count;\n\tint error_loc[16];\n};\n\nstruct elm_registers {\n\tu32 elm_irqenable;\n\tu32 elm_sysconfig;\n\tu32 elm_location_config;\n\tu32 elm_page_ctrl;\n\tu32 elm_syndrome_fragment_6[8];\n\tu32 elm_syndrome_fragment_5[8];\n\tu32 elm_syndrome_fragment_4[8];\n\tu32 elm_syndrome_fragment_3[8];\n\tu32 elm_syndrome_fragment_2[8];\n\tu32 elm_syndrome_fragment_1[8];\n\tu32 elm_syndrome_fragment_0[8];\n};\n\nstruct elm_info {\n\tstruct device *dev;\n\tvoid *elm_base;\n\tstruct completion elm_completion;\n\tstruct list_head list;\n\tenum bch_ecc bch_type;\n\tstruct elm_registers elm_regs;\n\tint ecc_steps;\n\tint ecc_syndrome_size;\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_data_callback {};\n\nstruct em_gio_priv {\n\tvoid *base0;\n\tvoid *base1;\n\tspinlock_t sense_lock;\n\tstruct platform_device *pdev;\n\tstruct gpio_chip gpio_chip;\n\tstruct irq_chip irq_chip;\n\tstruct irq_domain *irq_domain;\n};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct em_sti_priv {\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct platform_device *pdev;\n\tunsigned int active[2];\n\tlong unsigned int rate;\n\traw_spinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device ced;\n\tstruct clocksource cs;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct emac_board_info {\n\tstruct clk *clk;\n\tstruct device *dev;\n\tstruct platform_device *pdev;\n\tspinlock_t lock;\n\tvoid *membase;\n\tu32 msg_enable;\n\tstruct net_device *ndev;\n\tu16 tx_fifo_stat;\n\tint emacrx_completed_flag;\n\tstruct device_node *phy_node;\n\tunsigned int link;\n\tunsigned int speed;\n\tunsigned int duplex;\n\tphy_interface_t phy_interface;\n\tstruct dma_chan *rx_chan;\n\tphys_addr_t emac_rx_fifo;\n};\n\nstruct emac_dma_req {\n\tstruct emac_board_info *db;\n\tstruct dma_async_tx_descriptor *desc;\n\tstruct sk_buff *skb;\n\tdma_addr_t rxbuf;\n\tint count;\n};\n\nstruct emac_platform_data {\n\tchar mac_addr[6];\n\tu32 ctrl_reg_offset;\n\tu32 ctrl_mod_reg_offset;\n\tu32 ctrl_ram_offset;\n\tu32 hw_ram_addr;\n\tu32 ctrl_ram_size;\n\tconst char *phy_id;\n\tu8 rmii_en;\n\tu8 version;\n\tbool no_bd_ram;\n\tvoid (*interrupt_enable)(void);\n\tvoid (*interrupt_disable)(void);\n};\n\nstruct emac_variant {\n\tconst struct reg_field *syscon_field;\n\tbool soc_has_internal_phy;\n\tbool support_mii;\n\tbool support_rmii;\n\tbool support_rgmii;\n\tu8 rx_delay_max;\n\tu8 tx_delay_max;\n};\n\nstruct emc_rate_request {\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n};\n\nstruct emc_timing {\n\tlong unsigned int rate;\n\tlong unsigned int parent_rate;\n\tu8 parent_index;\n\tstruct clk *parent;\n\tu32 ram_code;\n};\n\nstruct emc_timing___2 {\n\tlong unsigned int rate;\n\tu32 data[46];\n};\n\nstruct emc_timing___3 {\n\tlong unsigned int rate;\n\tu32 emc_burst_data[143];\n\tu32 emc_auto_cal_config;\n\tu32 emc_auto_cal_config2;\n\tu32 emc_auto_cal_config3;\n\tu32 emc_auto_cal_interval;\n\tu32 emc_bgbias_ctl0;\n\tu32 emc_cfg;\n\tu32 emc_cfg_2;\n\tu32 emc_ctt_term_ctrl;\n\tu32 emc_mode_1;\n\tu32 emc_mode_2;\n\tu32 emc_mode_4;\n\tu32 emc_mode_reset;\n\tu32 emc_mrs_wait_cnt;\n\tu32 emc_sel_dpd_ctrl;\n\tu32 emc_xm2dqspadctrl2;\n\tu32 emc_zcal_cnt_long;\n\tu32 emc_zcal_interval;\n};\n\nstruct emc_timing___4 {\n\tlong unsigned int rate;\n\tu32 data[89];\n\tu32 emc_auto_cal_interval;\n\tu32 emc_mode_1;\n\tu32 emc_mode_2;\n\tu32 emc_mode_reset;\n\tu32 emc_zcal_cnt_long;\n\tbool emc_cfg_periodic_qrst;\n\tbool emc_cfg_dyn_self_ref;\n};\n\nstruct en_clk_desc {\n\tint id;\n\tconst char *name;\n\tu32 base_reg;\n\tu8 base_bits;\n\tu8 base_shift;\n\tunion {\n\t\tconst unsigned int *base_values;\n\t\tunsigned int base_value;\n\t};\n\tsize_t n_base_values;\n\tu16 div_reg;\n\tu8 div_bits;\n\tu8 div_shift;\n\tu16 div_val0;\n\tu8 div_step;\n\tu8 div_offset;\n};\n\nstruct en_clk_gate {\n\tvoid *base;\n\tstruct clk_hw hw;\n};\n\nstruct en_clk_soc_data {\n\tu32 num_clocks;\n\tconst struct clk_ops pcie_ops;\n\tint (*hw_init)(struct platform_device *, struct clk_hw_onecell_data *);\n};\n\nstruct en_rst_data {\n\tconst u16 *bank_ofs;\n\tconst u16 *idx_map;\n\tvoid *base;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct trace_event_file;\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nstruct xdr_buf;\n\nstruct encryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tint pos;\n\tstruct xdr_buf *outbuf;\n\tstruct page **pages;\n\tstruct scatterlist infrags[4];\n\tstruct scatterlist outfrags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\nstruct ep_device {\n\tstruct usb_endpoint_descriptor *desc;\n\tstruct usb_device *udev;\n\tstruct device dev;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct ephy_info {\n\tunsigned int offset;\n\tu16 mask;\n\tu16 bits;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n};\n\nstruct epoll_event {\n\t__poll_t events;\n\tlong: 32;\n\t__u64 data;\n};\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct trace_eprobe;\n\nstruct eprobe_data {\n\tstruct trace_event_file *file;\n\tstruct trace_eprobe *ep;\n};\n\nstruct eprobe_trace_entry_head {\n\tstruct trace_entry ent;\n};\n\nstruct erase_info {\n\tuint64_t addr;\n\tuint64_t len;\n\tuint64_t fail_addr;\n};\n\nstruct erase_info_user {\n\t__u32 start;\n\t__u32 length;\n};\n\nstruct erase_info_user64 {\n\t__u64 start;\n\t__u64 length;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu16 pos;\n\tu64 ts;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct esdhc_clk_fixup {\n\tconst unsigned int sd_dflt_max_clk;\n\tconst unsigned int max_clk[11];\n};\n\nstruct esdhc_platform_data {\n\tenum wp_types wp_type;\n\tenum cd_types___2 cd_type;\n\tint max_bus_width;\n\tunsigned int delay_line;\n\tunsigned int tuning_step;\n\tunsigned int tuning_start_tap;\n\tunsigned int strobe_dll_delay_target;\n\tunsigned int saved_tuning_delay_cell;\n\tunsigned int saved_auto_tuning_window;\n};\n\nstruct esdhc_soc_data {\n\tu32 flags;\n\tu32 quirks;\n};\n\nstruct esre_entry;\n\nstruct esre_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct esre_entry *, char *);\n};\n\nstruct esre_entry {\n\tunion {\n\t\tstruct efi_system_resource_entry_v1 *esre1;\n\t} esre;\n\tstruct kobject kobj;\n\tstruct list_head list;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethqos_emac_por;\n\nstruct ethqos_emac_driver_data {\n\tconst struct ethqos_emac_por *por;\n\tunsigned int num_por;\n\tbool rgmii_config_loopback_en;\n\tbool has_emac_ge_3;\n\tconst char *link_clk_name;\n\tu32 dma_addr_width;\n\tstruct dwmac4_addrs dwmac4_addrs;\n\tbool needs_sgmii_loopback;\n};\n\nstruct ethqos_emac_por {\n\tunsigned int offset;\n\tunsigned int value;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n\tlong: 32;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_flow_spec_container {\n\tstruct ethtool_rx_flow_spec fs;\n\tstruct list_head list;\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[4];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[4];\n\t\tlong unsigned int advertising[4];\n\t\tlong unsigned int lp_advertising[4];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct ethtool_tunable;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n\tlong: 32;\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rx_fs_item {\n\tstruct ethtool_rx_flow_spec fs;\n\tstruct list_head list;\n};\n\nstruct ethtool_rx_fs_list {\n\tstruct list_head list;\n\tunsigned int count;\n};\n\nstruct ethtool_rx_list {\n\tstruct list_head list;\n\tunsigned int count;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n\tlong: 32;\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct etts_regs {\n\tu32 tmr_etts1_h;\n\tu32 tmr_etts1_l;\n\tu32 tmr_etts2_h;\n\tu32 tmr_etts2_l;\n};\n\nstruct input_handler;\n\nstruct input_value;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct fasync_struct;\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct event_trigger_data;\n\nstruct ring_buffer_event;\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*parse)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*trigger)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tbool (*count_func)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_data *);\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\nstruct perf_cpu_context;\n\nstruct perf_event_context;\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nstruct event_header {\n\t__be16 data_len;\n\t__u8 notification_class: 3;\n\t__u8 reserved1: 4;\n\t__u8 nea: 1;\n\t__u8 supp_event_class;\n};\n\nstruct its_vm;\n\nstruct its_vlpi_map;\n\nstruct event_lpi_map {\n\tlong unsigned int *lpi_map;\n\tu16 *col_map;\n\tirq_hw_number_t lpi_base;\n\tint nr_lpis;\n\traw_spinlock_t vlpi_lock;\n\tstruct its_vm *vm;\n\tstruct its_vlpi_map *vlpi_maps;\n\tint nr_vlpis;\n};\n\nstruct event_mod_load {\n\tstruct list_head list;\n\tchar *module;\n\tchar *match;\n\tchar *system;\n\tchar *event;\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tint flags;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n\tstruct llist_node llist;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventfs_attr {\n\tint mode;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\ntypedef int (*eventfs_callback)(const char *, umode_t *, void **, const struct file_operations **);\n\ntypedef void (*eventfs_release)(const char *, void *);\n\nstruct eventfs_entry {\n\tconst char *name;\n\teventfs_callback callback;\n\teventfs_release release;\n};\n\nstruct eventfs_inode {\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head children;\n\tconst struct eventfs_entry *entries;\n\tconst char *name;\n\tstruct eventfs_attr *entry_attrs;\n\tvoid *data;\n\tstruct eventfs_attr attr;\n\tstruct kref kref;\n\tunsigned int is_freed: 1;\n\tunsigned int is_events: 1;\n\tunsigned int nr_entries: 30;\n\tunsigned int ino;\n};\n\nstruct eventfs_root_inode {\n\tstruct eventfs_inode ei;\n\tstruct dentry *events_dir;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n};\n\nstruct kfifo {\n\tunion {\n\t\tstruct __kfifo kfifo;\n\t\tunsigned char *type;\n\t\tconst unsigned char *const_type;\n\t\tchar (*rectype)[0];\n\t\tvoid *ptr;\n\t\tconst void *ptr_const;\n\t};\n\tunsigned char buf[0];\n};\n\nstruct events_queue {\n\tsize_t sz;\n\tstruct kfifo kfifo;\n\tstruct work_struct notify_work;\n\tstruct workqueue_struct *wq;\n};\n\nstruct ewma_pkt_len {\n\tlong unsigned int internal;\n};\n\nstruct exar8250_board;\n\nstruct exar8250 {\n\tunsigned int nr;\n\tunsigned int osc_freq;\n\tstruct exar8250_board *board;\n\tstruct eeprom_93cx6 eeprom;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tconst struct serial_rs485 *rs485_supported;\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n\tvoid (*unregister_gpio)(struct uart_8250_port *);\n};\n\nstruct exception_table_entry {\n\tlong unsigned int insn;\n\tlong unsigned int fixup;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_buddy;\n\nstruct ext4_prealloc_space;\n\nstruct ext4_locality_group;\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\text4_grpblk_t ac_orig_goal_len;\n\text4_group_t ac_prefetch_grp;\n\tunsigned int ac_prefetch_ios;\n\tunsigned int ac_prefetch_nr;\n\tint ac_first_err;\n\t__u32 ac_flags;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_cX_found[5];\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct ext4_buddy *ac_e4b;\n\tstruct folio *ac_bitmap_folio;\n\tstruct folio *ac_buddy_folio;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\tlong: 32;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n\tlong: 32;\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_group_info;\n\nstruct ext4_buddy {\n\tstruct folio *bd_buddy_folio;\n\tvoid *bd_buddy;\n\tstruct folio *bd_bitmap_folio;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_hash {\n\t__le32 hash;\n\t__le32 minor_hash;\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\nstruct ext4_err_translation {\n\tint code;\n\tint errno;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tlong: 32;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct extent_status;\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_extent;\n\nstruct ext4_extent_idx;\n\nstruct ext4_extent_header;\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n\tlong: 32;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_fc_add_range {\n\t__le32 fc_ino;\n\t__u8 fc_ex[12];\n};\n\nstruct ext4_fc_alloc_region {\n\text4_lblk_t lblk;\n\tlong: 32;\n\text4_fsblk_t pblk;\n\tint ino;\n\tint len;\n};\n\nstruct ext4_fc_del_range {\n\t__le32 fc_ino;\n\t__le32 fc_lblk;\n\t__le32 fc_len;\n};\n\nstruct ext4_fc_dentry_info {\n\t__le32 fc_parent_ino;\n\t__le32 fc_ino;\n\t__u8 fc_dname[0];\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n\tlong: 32;\n};\n\nstruct ext4_fc_dentry_update {\n\tint fcd_op;\n\tint fcd_parent;\n\tint fcd_ino;\n\tlong: 32;\n\tstruct name_snapshot fcd_name;\n\tstruct list_head fcd_list;\n\tstruct list_head fcd_dilist;\n};\n\nstruct ext4_fc_head {\n\t__le32 fc_features;\n\t__le32 fc_tid;\n};\n\nstruct ext4_fc_inode {\n\t__le32 fc_ino;\n\t__u8 fc_raw_inode[0];\n};\n\nstruct ext4_fc_replay_state {\n\tint fc_replay_num_tags;\n\tint fc_replay_expected_off;\n\tint fc_current_pass;\n\tint fc_cur_tag;\n\tint fc_crc;\n\tstruct ext4_fc_alloc_region *fc_regions;\n\tint fc_regions_size;\n\tint fc_regions_used;\n\tint fc_regions_valid;\n\tint *fc_modified_inodes;\n\tint fc_modified_inodes_used;\n\tint fc_modified_inodes_size;\n};\n\nstruct ext4_fc_stats {\n\tunsigned int fc_ineligible_reason_count[13];\n\tlong unsigned int fc_num_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_failed_commits;\n\tlong unsigned int fc_skipped_commits;\n\tlong unsigned int fc_numblks;\n\tu64 s_fc_avg_commit_time;\n};\n\nstruct ext4_fc_tail {\n\t__le32 fc_tid;\n\t__le32 fc_crc;\n};\n\nstruct ext4_fc_tl {\n\t__le16 fc_tag;\n\t__le16 fc_len;\n};\n\nstruct ext4_fc_tl_mem {\n\tu16 fc_tag;\n\tu16 fc_len;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nstruct fscrypt_dummy_policy {};\n\nstruct ext4_fs_context {\n\tchar *s_qf_names[3];\n\tstruct fscrypt_dummy_policy dummy_enc_policy;\n\tint s_jquota_fmt;\n\tshort unsigned int qname_spec;\n\tlong unsigned int vals_s_flags;\n\tlong unsigned int mask_s_flags;\n\tlong unsigned int journal_devnum;\n\tlong unsigned int s_commit_interval;\n\tlong unsigned int s_stripe;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_want_extra_isize;\n\tunsigned int s_li_wait_mult;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int journal_ioprio;\n\tunsigned int vals_s_mount_opt;\n\tunsigned int mask_s_mount_opt;\n\tunsigned int vals_s_mount_opt2;\n\tunsigned int mask_s_mount_opt2;\n\tunsigned int opt_flags;\n\tunsigned int spec;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong: 32;\n\text4_fsblk_t s_sb_block;\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\nstruct ext4_getfsmap_info;\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\tlong: 32;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n\tlong: 32;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\tint bb_avg_fragment_size_order;\n\text4_grpblk_t bb_largest_free_order;\n\text4_group_t bb_group;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct jbd2_inode;\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_state_flags;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tunion {\n\t\tstruct list_head i_orphan;\n\t\tunsigned int i_orphan_idx;\n\t};\n\tstruct list_head i_fc_dilist;\n\tstruct list_head i_fc_list;\n\text4_lblk_t i_fc_lblk_start;\n\text4_lblk_t i_fc_lblk_len;\n\tspinlock_t i_raw_lock;\n\twait_queue_head_t i_fc_wait;\n\tspinlock_t i_fc_lock;\n\tlong: 32;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tlong: 32;\n\tstruct timespec64 i_crtime;\n\tatomic_t i_prealloc_active;\n\tunsigned int i_reserved_data_blocks;\n\tstruct rb_root i_prealloc_node;\n\trwlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\tu64 i_es_seq;\n\text4_group_t i_last_alloc_group;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tspinlock_t i_block_reservation_lock;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\trefcount_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n\tlong: 32;\n};\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tlong: 32;\n\tsector_t io_next_block;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct ext4_journal_trigger {\n\tstruct jbd2_buffer_trigger_type tr_triggers;\n\tstruct super_block *sb;\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tenum ext4_li_mode lr_mode;\n\text4_group_t lr_first_not_zeroed;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n\tlong: 32;\n\tu64 m_seq;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n};\n\nstruct ext4_new_group_data;\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t resize_bg;\n\text4_group_t count;\n};\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\tlong: 32;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n\tlong: 32;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\tlong: 32;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct ext4_orphan_block {\n\tatomic_t ob_free_entries;\n\tstruct buffer_head *ob_bh;\n};\n\nstruct ext4_orphan_block_tail {\n\t__le32 ob_magic;\n\t__le32 ob_checksum;\n};\n\nstruct ext4_orphan_info {\n\tint of_blocks;\n\t__u32 of_csum_seed;\n\tstruct ext4_orphan_block *of_binfo;\n};\n\nstruct ext4_prealloc_space {\n\tunion {\n\t\tstruct rb_node inode_node;\n\t\tstruct list_head lg_list;\n\t} pa_node;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tunion {\n\t\trwlock_t *inode_lock;\n\t\tspinlock_t *lg_lock;\n\t} pa_node_lock;\n\tstruct inode *pa_inode;\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct ext4_super_block;\n\nstruct journal_s;\n\nstruct ext4_system_blocks;\n\nstruct flex_groups;\n\nstruct shrinker;\n\nstruct mb_cache;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tlong: 32;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tlong unsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\tunsigned int s_def_mount_opt2;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tlong: 32;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct percpu_counter s_sra_exceeded_retry_limit;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct buffer_head *s_mmp_bh;\n\tstruct journal_s *s_journal;\n\tlong unsigned int s_ext4_flags;\n\tstruct mutex s_orphan_lock;\n\tstruct list_head s_orphan;\n\tstruct ext4_orphan_info s_orphan_info;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct file *s_journal_bdev_file;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *s_system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tatomic_t s_mb_free_pending;\n\tstruct list_head s_freed_data_list[2];\n\tstruct list_head s_discard_list;\n\tstruct work_struct s_discard_work;\n\tatomic_t s_retry_alloc_pending;\n\tstruct xarray *s_mb_avg_fragment_size;\n\tstruct xarray *s_mb_largest_free_orders;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_max_linear_groups;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int s_mb_prefetch;\n\tunsigned int s_mb_prefetch_limit;\n\tunsigned int s_mb_best_avail_max_trim_order;\n\tunsigned int s_sb_update_sec;\n\tunsigned int s_sb_update_kb;\n\text4_group_t *s_mb_last_groups;\n\tunsigned int s_mb_nr_global_goals;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_cX_ex_scanned[5];\n\tatomic_t s_bal_groups_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_stream_goals;\n\tatomic_t s_bal_len_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tatomic64_t s_bal_cX_groups_considered[5];\n\tatomic64_t s_bal_cX_hits[5];\n\tatomic64_t s_bal_cX_failed[5];\n\tatomic_t s_mb_buddies_generated;\n\tlong: 32;\n\tatomic64_t s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tlong unsigned int s_err_report_sec;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tlong unsigned int s_last_trim_minblks;\n\tu16 s_min_folio_order;\n\tu16 s_max_folio_order;\n\t__u32 s_csum_seed;\n\tstruct shrinker *s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tlong: 32;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache *s_ea_block_cache;\n\tstruct mb_cache *s_ea_inode_cache;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t s_es_lock;\n\tstruct ext4_journal_trigger s_journal_triggers[1];\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tatomic_t s_warning_count;\n\tatomic_t s_msg_count;\n\tstruct fscrypt_dummy_policy s_dummy_enc_policy;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tlong: 32;\n\tu64 s_dax_part_off;\n\terrseq_t s_bdev_wb_err;\n\tspinlock_t s_bdev_wb_lock;\n\tspinlock_t s_error_lock;\n\tint s_add_error_count;\n\tint s_first_error_code;\n\t__u32 s_first_error_line;\n\t__u32 s_first_error_ino;\n\tlong: 32;\n\t__u64 s_first_error_block;\n\tconst char *s_first_error_func;\n\tlong: 32;\n\ttime64_t s_first_error_time;\n\tint s_last_error_code;\n\t__u32 s_last_error_line;\n\t__u32 s_last_error_ino;\n\tlong: 32;\n\t__u64 s_last_error_block;\n\tconst char *s_last_error_func;\n\tlong: 32;\n\ttime64_t s_last_error_time;\n\tstruct work_struct s_sb_upd_work;\n\tunsigned int s_awu_min;\n\tunsigned int s_awu_max;\n\tatomic_t s_fc_subtid;\n\tstruct list_head s_fc_q[2];\n\tstruct list_head s_fc_dentry_q[2];\n\tunsigned int s_fc_bytes;\n\tstruct mutex s_fc_lock;\n\tstruct buffer_head *s_fc_bh;\n\tstruct ext4_fc_stats s_fc_stats;\n\ttid_t s_fc_ineligible_tid;\n\tstruct ext4_fc_replay_state s_fc_replay_state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_orphan_file_inum;\n\t__le16 s_def_resuid_hi;\n\t__le16 s_def_resgid_hi;\n\t__le32 s_reserved[93];\n\t__le32 s_checksum;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\tlong: 32;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n\tu32 ino;\n};\n\nstruct ext4_tune_sb_params {\n\t__u32 set_flags;\n\t__u32 checkinterval;\n\t__u16 errors_behavior;\n\t__u16 mnt_count;\n\t__u16 max_mnt_count;\n\t__u16 raid_stride;\n\t__u64 last_check_time;\n\t__u64 reserved_blocks;\n\t__u64 blocks_count;\n\t__u32 default_mnt_opts;\n\t__u32 reserved_uid;\n\t__u32 reserved_gid;\n\t__u32 raid_stripe_width;\n\t__u16 encoding;\n\t__u16 encoding_flags;\n\t__u8 def_hash_alg;\n\t__u8 pad_1;\n\t__u16 pad_2;\n\t__u32 feature_compat;\n\t__u32 feature_incompat;\n\t__u32 feature_ro_compat;\n\t__u32 set_feature_compat_mask;\n\t__u32 set_feature_incompat_mask;\n\t__u32 set_feature_ro_compat_mask;\n\t__u32 clear_feature_compat_mask;\n\t__u32 clear_feature_incompat_mask;\n\t__u32 clear_feature_ro_compat_mask;\n\t__u8 mount_opts[64];\n\t__u8 pad[68];\n};\n\nstruct ext4_xattr_entry;\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tlong: 32;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tlong: 32;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n\tlong: 32;\n};\n\nunion extcon_property_value {\n\tint intval;\n};\n\nstruct extcon_cable {\n\tstruct extcon_dev *edev;\n\tint cable_index;\n\tstruct attribute_group attr_g;\n\tstruct device_attribute attr_name;\n\tstruct device_attribute attr_state;\n\tstruct attribute *attrs[3];\n\tunion extcon_property_value usb_propval[3];\n\tunion extcon_property_value chg_propval[1];\n\tunion extcon_property_value jack_propval[1];\n\tunion extcon_property_value disp_propval[2];\n\tlong unsigned int usb_bits[1];\n\tlong unsigned int chg_bits[1];\n\tlong unsigned int jack_bits[1];\n\tlong unsigned int disp_bits[1];\n};\n\nstruct extcon_dev {\n\tconst char *name;\n\tconst unsigned int *supported_cable;\n\tconst u32 *mutually_exclusive;\n\tlong: 32;\n\tstruct device dev;\n\tunsigned int id;\n\tstruct raw_notifier_head nh_all;\n\tstruct raw_notifier_head *nh;\n\tstruct list_head entry;\n\tint max_supported;\n\tspinlock_t lock;\n\tu32 state;\n\tstruct device_type extcon_dev_type;\n\tstruct extcon_cable *cables;\n\tstruct attribute_group attr_g_muex;\n\tstruct attribute **attrs_muex;\n\tstruct device_attribute *d_attrs_muex;\n\tlong: 32;\n};\n\nstruct extcon_dev_notifier_devres {\n\tstruct extcon_dev *edev;\n\tunsigned int id;\n\tstruct notifier_block *nb;\n};\n\nstruct extcon_specific_cable_nb {\n\tstruct notifier_block *user_nb;\n\tint cable_index;\n\tstruct extcon_dev *edev;\n\tlong unsigned int previous_value;\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\tlong: 32;\n\text4_fsblk_t es_pblk;\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct exynos_hsi2c_variant;\n\nstruct exynos5_i2c {\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *msg;\n\tstruct completion msg_complete;\n\tunsigned int msg_ptr;\n\tunsigned int irq;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct device *dev;\n\tint state;\n\tspinlock_t lock;\n\tint trans_done;\n\tunsigned int atomic;\n\tunsigned int op_clock;\n\tconst struct exynos_hsi2c_variant *variant;\n\tlong: 32;\n};\n\nstruct samsung_div_clock;\n\nstruct samsung_gate_clock;\n\nstruct exynos5_subcmu_reg_dump;\n\nstruct exynos5_subcmu_info {\n\tconst struct samsung_div_clock *div_clks;\n\tunsigned int nr_div_clks;\n\tconst struct samsung_gate_clock *gate_clks;\n\tunsigned int nr_gate_clks;\n\tstruct exynos5_subcmu_reg_dump *suspend_regs;\n\tunsigned int nr_suspend_regs;\n\tconst char *pd_name;\n};\n\nstruct exynos5_subcmu_reg_dump {\n\tu32 offset;\n\tu32 value;\n\tu32 mask;\n\tu32 save;\n};\n\nstruct exynos_asv_table {\n\tunsigned int num_rows;\n\tunsigned int num_cols;\n\tu32 *buf;\n};\n\nstruct exynos_asv;\n\nstruct exynos_asv_subsys {\n\tstruct exynos_asv *asv;\n\tconst char *cpu_dt_compat;\n\tint id;\n\tstruct exynos_asv_table table;\n\tunsigned int base_volt;\n\tunsigned int offset_volt_h;\n\tunsigned int offset_volt_l;\n};\n\nstruct exynos_asv {\n\tstruct device *dev;\n\tstruct regmap *chipid_regmap;\n\tstruct exynos_asv_subsys subsys[2];\n\tint (*opp_get_voltage)(const struct exynos_asv_subsys *, int, unsigned int);\n\tunsigned int group;\n\tunsigned int table;\n\tbool use_sg;\n\tint of_bin;\n};\n\nstruct exynos_audss_clk_drvdata {\n\tunsigned int has_adma_clk: 1;\n\tunsigned int has_mst_clk: 1;\n\tunsigned int enable_epll: 1;\n\tunsigned int num_clks;\n};\n\nstruct exynos_chipid_info {\n\tu32 product_id;\n\tu32 revision;\n};\n\nstruct exynos_chipid_variant {\n\tunsigned int main_rev_reg;\n\tunsigned int sub_rev_reg;\n\tunsigned int main_rev_shift;\n\tunsigned int sub_rev_shift;\n\tbool efuse;\n};\n\nstruct exynos_clkout {\n\tstruct clk_gate gate;\n\tstruct clk_mux mux;\n\tspinlock_t slock;\n\tvoid *reg;\n\tstruct device_node *np;\n\tu32 pmu_debug_save;\n\tstruct clk_hw_onecell_data data;\n};\n\nstruct exynos_clkout_variant {\n\tu32 mux_mask;\n};\n\nstruct exynos_cpuclk_cfg_data;\n\nstruct exynos_cpuclk_chip;\n\nstruct exynos_cpuclk {\n\tstruct clk_hw hw;\n\tconst struct clk_hw *alt_parent;\n\tvoid *base;\n\tspinlock_t *lock;\n\tconst struct exynos_cpuclk_cfg_data *cfg;\n\tconst long unsigned int num_cfgs;\n\tstruct notifier_block clk_nb;\n\tlong unsigned int flags;\n\tconst struct exynos_cpuclk_chip *chip;\n};\n\nstruct exynos_cpuclk_cfg_data {\n\tlong unsigned int prate;\n\tlong unsigned int div0;\n\tlong unsigned int div1;\n};\n\ntypedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *, struct exynos_cpuclk *);\n\nstruct exynos_cpuclk_regs;\n\nstruct exynos_cpuclk_chip {\n\tconst struct exynos_cpuclk_regs *regs;\n\texynos_rate_change_fn_t pre_rate_cb;\n\texynos_rate_change_fn_t post_rate_cb;\n};\n\nstruct exynos_cpuclk_regs {\n\tu32 mux_sel;\n\tu32 mux_stat;\n\tu32 div_cpu0;\n\tu32 div_cpu1;\n\tu32 div_stat_cpu0;\n\tu32 div_stat_cpu1;\n\tu32 mux;\n\tu32 divs[4];\n};\n\nstruct exynos_eint_gpio_save {\n\tu32 eint_con;\n\tu32 eint_fltcon0;\n\tu32 eint_fltcon1;\n\tu32 eint_mask;\n};\n\nstruct exynos_hsi2c_variant {\n\tunsigned int fifo_depth;\n\tenum i2c_type_exynos hw;\n};\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommu_dma_cookie;\n\nstruct iommu_dma_msi_cookie;\n\nstruct iommufd_hw_pagetable;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_ops;\n\nstruct iommu_dirty_ops;\n\nstruct iommu_ops;\n\nstruct iopf_group;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct exynos_iommu_domain {\n\tstruct list_head clients;\n\tsysmmu_pte_t *pgtable;\n\tshort int *lv2entcnt;\n\tspinlock_t lock;\n\tspinlock_t pgtablelock;\n\tstruct iommu_domain domain;\n};\n\nstruct exynos_iommu_owner {\n\tstruct list_head controllers;\n\tstruct iommu_domain *domain;\n\tstruct mutex rpm_lock;\n};\n\nstruct samsung_pinctrl_drv_data;\n\nstruct exynos_irq_chip {\n\tstruct irq_chip chip;\n\tu32 eint_con;\n\tu32 eint_mask;\n\tu32 eint_pend;\n\tu32 eint_num_wakeup_reg;\n\tu32 eint_wake_mask_reg;\n\tvoid (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *, struct exynos_irq_chip *);\n};\n\nstruct samsung_pin_bank;\n\nstruct exynos_muxed_weint_data {\n\tunsigned int nr_banks;\n\tstruct samsung_pin_bank *banks[0];\n};\n\nstruct exynos_wkup_irq;\n\nstruct syscore_ops;\n\nstruct exynos_pm_data {\n\tconst struct exynos_wkup_irq *wkup_irq;\n\tunsigned int wake_disable_mask;\n\tvoid (*pm_prepare)(void);\n\tvoid (*pm_resume_prepare)(void);\n\tint (*cpu_suspend)(long unsigned int);\n\tconst struct syscore_ops *syscore_ops;\n};\n\nstruct exynos_pm_domain {\n\tvoid *base;\n\tlong: 32;\n\tstruct generic_pm_domain pd;\n\tu32 local_pwr_cfg;\n\tlong: 32;\n};\n\nstruct exynos_pm_domain_config {\n\tu32 local_pwr_cfg;\n};\n\nstruct exynos_pm_state {\n\tint cpu_state;\n\tunsigned int pmu_spare3;\n\tvoid *sysram_base;\n\tphys_addr_t sysram_phys;\n\tbool secure_firmware;\n};\n\nstruct exynos_pmu_conf {\n\tunsigned int offset;\n\tu8 val[3];\n};\n\nstruct exynos_pmu_data;\n\nstruct exynos_pmu_context {\n\tstruct device *dev;\n\tconst struct exynos_pmu_data *pmu_data;\n\tstruct regmap *pmureg;\n\tstruct regmap *pmuintrgen;\n\traw_spinlock_t cpupm_lock;\n\tlong unsigned int *in_cpuhp;\n\tbool sys_insuspend;\n\tbool sys_inreboot;\n};\n\nstruct regmap_access_table;\n\nstruct exynos_pmu_data {\n\tconst struct exynos_pmu_conf *pmu_config;\n\tconst struct exynos_pmu_conf *pmu_config_extra;\n\tbool pmu_secure;\n\tbool pmu_cpuhp;\n\tvoid (*pmu_init)(void);\n\tvoid (*powerdown_conf)(enum sys_powerdown);\n\tvoid (*powerdown_conf_extra)(enum sys_powerdown);\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *wr_table;\n};\n\nstruct exynos_soc_id {\n\tconst char *name;\n\tunsigned int id;\n};\n\nstruct exynos_srom_reg_dump;\n\nstruct exynos_srom {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tstruct exynos_srom_reg_dump *reg_offset;\n};\n\nstruct exynos_srom_reg_dump {\n\tu32 offset;\n\tu32 value;\n};\n\nstruct exynos_tmu_data {\n\tvoid *base;\n\tvoid *base_second;\n\tint irq;\n\tenum soc_type soc;\n\tstruct mutex lock;\n\tstruct clk *clk;\n\tstruct clk *clk_sec;\n\tstruct clk *sclk;\n\tu32 cal_type;\n\tu32 efuse_value;\n\tu32 min_efuse_value;\n\tu32 max_efuse_value;\n\tu16 temp_error1;\n\tu16 temp_error2;\n\tu8 gain;\n\tu8 reference_voltage;\n\tstruct thermal_zone_device *tzd;\n\tbool enabled;\n\tvoid (*tmu_set_low_temp)(struct exynos_tmu_data *, u8);\n\tvoid (*tmu_set_high_temp)(struct exynos_tmu_data *, u8);\n\tvoid (*tmu_set_crit_temp)(struct exynos_tmu_data *, u8);\n\tvoid (*tmu_disable_low)(struct exynos_tmu_data *);\n\tvoid (*tmu_disable_high)(struct exynos_tmu_data *);\n\tvoid (*tmu_initialize)(struct platform_device *);\n\tvoid (*tmu_control)(struct platform_device *, bool);\n\tint (*tmu_read)(struct exynos_tmu_data *);\n\tvoid (*tmu_set_emulation)(struct exynos_tmu_data *, int);\n\tvoid (*tmu_clear_irqs)(struct exynos_tmu_data *);\n};\n\nstruct exynos_trng_dev {\n\tstruct device *dev;\n\tvoid *mem;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct hwrng rng;\n\tlong unsigned int flags;\n};\n\nstruct exynos_weint_data {\n\tunsigned int irq;\n\tstruct samsung_pin_bank *bank;\n};\n\nstruct exynos_wkup_irq {\n\tunsigned int hwirq;\n\tu32 mask;\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct factors_data {\n\tint enable;\n\tint mux;\n\tint muxmask;\n\tconst struct clk_factors_config *table;\n\tvoid (*getter)(struct factors_request *);\n\tvoid (*recalc)(struct factors_request *);\n\tconst char *name;\n};\n\nstruct factors_request {\n\tlong unsigned int rate;\n\tlong unsigned int parent_rate;\n\tu8 parent_index;\n\tu8 n;\n\tu8 k;\n\tu8 m;\n\tu8 p;\n};\n\nstruct failover_ops;\n\nstruct failover {\n\tstruct list_head list;\n\tstruct net_device *failover_dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct failover_ops *ops;\n};\n\nstruct failover_ops {\n\tint (*slave_pre_register)(struct net_device *, struct net_device *);\n\tint (*slave_register)(struct net_device *, struct net_device *);\n\tint (*slave_pre_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_link_change)(struct net_device *, struct net_device *);\n\tint (*slave_name_change)(struct net_device *, struct net_device *);\n\trx_handler_result_t (*slave_handle_frame)(struct sk_buff **);\n};\n\nstruct falcon_firmware_section {\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct falcon_firmware {\n\tconst struct firmware *firmware;\n\tdma_addr_t iova;\n\tdma_addr_t phys;\n\tvoid *virt;\n\tsize_t size;\n\tstruct falcon_firmware_section bin_data;\n\tstruct falcon_firmware_section data;\n\tstruct falcon_firmware_section code;\n};\n\nstruct falcon {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct falcon_firmware firmware;\n};\n\nstruct falcon_fw_bin_header_v1 {\n\tu32 magic;\n\tu32 version;\n\tu32 size;\n\tu32 os_header_offset;\n\tu32 os_data_offset;\n\tu32 os_size;\n};\n\nstruct falcon_fw_os_header_v1 {\n\tu32 code_offset;\n\tu32 code_size;\n\tu32 data_offset;\n\tu32 data_size;\n};\n\nstruct fan53555_device_info {\n\tenum fan53555_vendor vendor;\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct regulator_init_data *regulator;\n\tint chip_id;\n\tint chip_rev;\n\tunsigned int vol_reg;\n\tunsigned int sleep_reg;\n\tunsigned int en_reg;\n\tunsigned int sleep_en_reg;\n\tunsigned int vsel_min;\n\tunsigned int vsel_step;\n\tunsigned int vsel_count;\n\tunsigned int mode_reg;\n\tunsigned int mode_mask;\n\tunsigned int sleep_vol_cache;\n\tunsigned int slew_reg;\n\tunsigned int slew_mask;\n\tconst unsigned int *ramp_delay_table;\n\tunsigned int n_ramp_values;\n\tunsigned int enable_time;\n\tunsigned int slew_rate;\n};\n\nstruct fan53555_platform_data {\n\tstruct regulator_init_data *regulator;\n\tunsigned int slew_rate;\n\tunsigned int sleep_vsel_id;\n};\n\nstruct fanout_args {\n\t__u16 id;\n\t__u16 type_flags;\n\t__u32 max_num_members;\n};\n\nstruct fapll_data {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tconst char *name;\n\tstruct clk *clk_ref;\n\tstruct clk *clk_bypass;\n\tstruct clk_onecell_data outputs;\n\tbool bypass_bit_inverted;\n};\n\nstruct fapll_synth {\n\tstruct clk_hw hw;\n\tstruct fapll_data *fd;\n\tint index;\n\tvoid *freq;\n\tvoid *div;\n\tconst char *name;\n\tstruct clk *clk_pll;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_bios_param_block {\n\tu16 fat_sector_size;\n\tu8 fat_sec_per_clus;\n\tu16 fat_reserved;\n\tu8 fat_fats;\n\tu16 fat_dir_entries;\n\tu16 fat_sectors;\n\tu16 fat_fat_length;\n\tu32 fat_total_sect;\n\tu8 fat16_state;\n\tu32 fat16_vol_id;\n\tu32 fat32_length;\n\tu32 fat32_root_cluster;\n\tu16 fat32_info_sector;\n\tu8 fat32_state;\n\tu32 fat32_vol_id;\n};\n\nstruct fat_boot_fsinfo {\n\t__le32 signature1;\n\t__le32 reserved1[120];\n\t__le32 signature2;\n\t__le32 free_clusters;\n\t__le32 next_cluster;\n\t__le32 reserved2[4];\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fat_cache {\n\tstruct list_head cache_list;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_cache_id {\n\tunsigned int id;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_entry {\n\tint entry;\n\tunion {\n\t\tu8 *ent12_p[2];\n\t\t__le16 *ent16_p;\n\t\t__le32 *ent32_p;\n\t} u;\n\tint nr_bhs;\n\tstruct buffer_head *bhs[2];\n\tstruct inode *fat_inode;\n};\n\nstruct fat_fid {\n\tu32 i_gen;\n\tu32 i_pos_low;\n\tu16 i_pos_hi;\n\tu16 parent_i_pos_hi;\n\tu32 parent_i_pos_low;\n\tu32 parent_i_gen;\n};\n\nstruct fat_floppy_defaults {\n\tunsigned int nr_sectors;\n\tunsigned int sec_per_clus;\n\tunsigned int dir_entries;\n\tunsigned int media;\n\tunsigned int fat_length;\n};\n\nstruct fat_ioctl_filldir_callback {\n\tstruct dir_context ctx;\n\tvoid *dirent;\n\tint result;\n\tconst char *longname;\n\tint long_len;\n\tconst char *shortname;\n\tint short_len;\n};\n\nstruct fat_mount_options {\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tshort unsigned int fs_fmask;\n\tshort unsigned int fs_dmask;\n\tshort unsigned int codepage;\n\tint time_offset;\n\tchar *iocharset;\n\tshort unsigned int shortname;\n\tunsigned char name_check;\n\tunsigned char errors;\n\tunsigned char nfs;\n\tshort unsigned int allow_utime;\n\tunsigned int quiet: 1;\n\tunsigned int showexec: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int dotsOK: 1;\n\tunsigned int isvfat: 1;\n\tunsigned int utf8: 1;\n\tunsigned int unicode_xlate: 1;\n\tunsigned int numtail: 1;\n\tunsigned int flush: 1;\n\tunsigned int nocase: 1;\n\tunsigned int usefree: 1;\n\tunsigned int tz_set: 1;\n\tunsigned int rodir: 1;\n\tunsigned int discard: 1;\n\tunsigned int dos1xfloppy: 1;\n\tunsigned int debug: 1;\n};\n\nstruct msdos_dir_entry;\n\nstruct fat_slot_info {\n\tloff_t i_pos;\n\tloff_t slot_off;\n\tint nr_slots;\n\tstruct msdos_dir_entry *de;\n\tstruct buffer_head *bh;\n\tlong: 32;\n};\n\nstruct fatent_operations {\n\tvoid (*ent_blocknr)(struct super_block *, int, int *, sector_t *);\n\tvoid (*ent_set_ptr)(struct fat_entry *, int);\n\tint (*ent_bread)(struct super_block *, struct fat_entry *, int, sector_t);\n\tint (*ent_get)(struct fat_entry *);\n\tvoid (*ent_put)(struct fat_entry *, int);\n\tint (*ent_next)(struct fat_entry *);\n};\n\nstruct fatent_ra {\n\tsector_t cur;\n\tsector_t limit;\n\tunsigned int ra_blocks;\n\tlong: 32;\n\tsector_t ra_advance;\n\tsector_t ra_next;\n\tsector_t ra_limit;\n};\n\nstruct fault_attr {};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_address {\n\tvoid *address;\n\tint bits;\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_bitmap4x_iter {\n\tconst u8 *data;\n\tu32 fgxcolor;\n\tu32 bgcolor;\n\tint width;\n\tint i;\n\tconst u32 *expand;\n\tint bpp;\n\tbool top;\n};\n\nstruct fb_bitmap_iter {\n\tconst u8 *data;\n\tlong unsigned int colors[2];\n\tint width;\n\tint i;\n};\n\nstruct fb_blit_caps {\n\tlong unsigned int x[2];\n\tlong unsigned int y[4];\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_reverse {\n\tbool byte;\n\tbool pixel;\n};\n\nstruct fb_color_iter {\n\tconst u8 *data;\n\tconst u32 *palette;\n\tstruct fb_reverse reverse;\n\tint shift;\n\tint width;\n\tint i;\n};\n\nstruct fb_con2fbmap {\n\t__u32 console;\n\t__u32 framebuffer;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\nstruct fb_deferred_io_pageref {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tstruct list_head list;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tlong unsigned int blit_x[2];\n\tlong unsigned int blit_y[4];\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct lcd_device;\n\nstruct fb_ops;\n\nstruct fbcon_par;\n\nstruct fb_info {\n\trefcount_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tint blank;\n\tstruct lcd_device *lcd_dev;\n\tstruct delayed_work deferred_work;\n\tlong unsigned int npagerefs;\n\tstruct fb_deferred_io_pageref *pagerefs;\n\tstruct fb_deferred_io *fbdefio;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tstruct device *dev;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tstruct fbcon_par *fbcon_par;\n\tvoid *par;\n\tbool skip_vt_switch;\n\tbool skip_panic;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n};\n\nstruct fb_pattern {\n\tlong unsigned int pixels;\n\tint left;\n\tint right;\n\tstruct fb_reverse reverse;\n};\n\nstruct fbcon_bitops {\n\tvoid (*bmove)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*clear)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*putcs)(struct vc_data *, struct fb_info *, const short unsigned int *, int, int, int, int, int);\n\tvoid (*clear_margins)(struct vc_data *, struct fb_info *, int, int);\n\tvoid (*cursor)(struct vc_data *, struct fb_info *, bool, int, int);\n\tint (*update_start)(struct fb_info *);\n\tint (*rotate_font)(struct fb_info *, struct vc_data *);\n};\n\nstruct fbcon_display {\n\tconst u_char *fontdata;\n\tint userfont;\n\tshort int yscroll;\n\tint vrows;\n\tint cursor_shape;\n\tint con_rotate;\n\tu32 xres_virtual;\n\tu32 yres_virtual;\n\tu32 height;\n\tu32 width;\n\tu32 bits_per_pixel;\n\tu32 grayscale;\n\tu32 nonstd;\n\tu32 accel_flags;\n\tu32 rotate;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tconst struct fb_videomode *mode;\n};\n\nstruct fbcon_par {\n\tstruct fb_var_screeninfo var;\n\tstruct delayed_work cursor_work;\n\tstruct fb_cursor cursor_state;\n\tstruct fbcon_display *p;\n\tstruct fb_info *info;\n\tint currcon;\n\tint cur_blink_jiffies;\n\tint cursor_flash;\n\tint cursor_reset;\n\tint blank_state;\n\tint graphics;\n\tbool initialized;\n\tint rotate;\n\tint cur_rotate;\n\tchar *cursor_data;\n\tu8 *fontbuffer;\n\tu8 *fontdata;\n\tu8 *cursor_src;\n\tu32 cursor_size;\n\tu32 fd_size;\n\tconst struct fbcon_bitops *bitops;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdma;\n\nstruct fdma_ops {\n\tint (*dataptr_cb)(struct fdma *, int, int, u64 *);\n\tint (*nextptr_cb)(struct fdma *, int, u64 *);\n};\n\nstruct fdma_dcb;\n\nstruct fdma {\n\tvoid *priv;\n\tstruct fdma_dcb *dcbs;\n\tstruct fdma_dcb *last_dcb;\n\tdma_addr_t dma;\n\tint size;\n\tint db_index;\n\tint dcb_index;\n\tu32 n_dcbs;\n\tu32 n_dbs;\n\tu32 db_size;\n\tu32 channel_id;\n\tstruct fdma_ops ops;\n};\n\nstruct fdma_db {\n\tu64 dataptr;\n\tu64 status;\n};\n\nstruct fdma_dcb {\n\tu64 nextptr;\n\tu64 info;\n\tstruct fdma_db db[15];\n};\n\nstruct fdt_errtabent {\n\tconst char *str;\n};\n\nstruct fdt_header {\n\tfdt32_t magic;\n\tfdt32_t totalsize;\n\tfdt32_t off_dt_struct;\n\tfdt32_t off_dt_strings;\n\tfdt32_t off_mem_rsvmap;\n\tfdt32_t version;\n\tfdt32_t last_comp_version;\n\tfdt32_t boot_cpuid_phys;\n\tfdt32_t size_dt_strings;\n\tfdt32_t size_dt_struct;\n};\n\nstruct fdt_node_header {\n\tfdt32_t tag;\n\tchar name[0];\n};\n\nstruct fdt_property {\n\tfdt32_t tag;\n\tfdt32_t len;\n\tfdt32_t nameoff;\n\tchar data[0];\n};\n\nstruct fdt_reserve_entry {\n\tfdt64_t address;\n\tfdt64_t size;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_devinfo {\n\tu32 quirks;\n};\n\nstruct fec_dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n};\n\nunion fec_rx_buffer {\n\tvoid *buf_p;\n\tstruct page *page;\n\tstruct xdp_buff *xdp;\n};\n\nstruct xsk_buff_pool;\n\nstruct fec_enet_priv_rx_q {\n\tstruct bufdesc_prop bd;\n\tunion fec_rx_buffer rx_buf[256];\n\tstruct xsk_buff_pool *xsk_pool;\n\tstruct page_pool *page_pool;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xdp_rxq;\n\tu32 stats[7];\n\tu8 id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct fec_tx_buffer {\n\tvoid *buf_p;\n\tenum fec_txbuf_type type;\n};\n\nstruct fec_enet_priv_tx_q {\n\tstruct bufdesc_prop bd;\n\tunsigned char *tx_bounce[1024];\n\tstruct fec_tx_buffer tx_buf[1024];\n\tstruct xsk_buff_pool *xsk_pool;\n\tshort unsigned int tx_stop_threshold;\n\tshort unsigned int tx_wake_threshold;\n\tstruct bufdesc *dirty_tx;\n\tchar *tso_hdrs;\n\tdma_addr_t tso_hdrs_dma;\n};\n\nstruct fec_stop_mode_gpr {\n\tstruct regmap *gpr;\n\tu8 reg;\n\tu8 bit;\n};\n\nstruct imx_sc_ipc;\n\nstruct fec_enet_private {\n\tvoid *hwp;\n\tstruct net_device *netdev;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_ref;\n\tstruct clk *clk_enet_out;\n\tstruct clk *clk_ptp;\n\tstruct clk *clk_2x_txclk;\n\tbool ptp_clk_on;\n\tstruct mutex ptp_clk_mutex;\n\tunsigned int num_tx_queues;\n\tunsigned int num_rx_queues;\n\tstruct fec_enet_priv_tx_q *tx_queue[3];\n\tstruct fec_enet_priv_rx_q *rx_queue[3];\n\tunsigned int total_tx_ring_size;\n\tunsigned int total_rx_ring_size;\n\tunsigned int max_buf_size;\n\tunsigned int pagepool_order;\n\tunsigned int rx_frame_size;\n\tstruct platform_device *pdev;\n\tint dev_id;\n\tstruct mii_bus *mii_bus;\n\tuint phy_speed;\n\tphy_interface_t phy_interface;\n\tstruct device_node *phy_node;\n\tbool rgmii_txc_dly;\n\tbool rgmii_rxc_dly;\n\tbool rpm_active;\n\tint link;\n\tint full_duplex;\n\tint speed;\n\tint irq[3];\n\tbool bufdesc_ex;\n\tint pause_flag;\n\tint wol_flag;\n\tint wake_irq;\n\tu32 quirks;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tint csum_flags;\n\tstruct work_struct tx_timeout_work;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_caps;\n\tspinlock_t tmreg_lock;\n\tlong: 32;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tu32 cycle_speed;\n\tint hwts_rx_en;\n\tint hwts_tx_en;\n\tstruct delayed_work time_keep;\n\tstruct regulator *reg_phy;\n\tstruct fec_stop_mode_gpr stop_gpr;\n\tstruct pm_qos_request pm_qos_req;\n\tunsigned int tx_align;\n\tunsigned int rx_shift;\n\tunsigned int rx_pkts_itr;\n\tunsigned int rx_time_itr;\n\tunsigned int tx_pkts_itr;\n\tunsigned int tx_time_itr;\n\tunsigned int itr_clk_rate;\n\tunsigned int clk_ref_rate;\n\tunsigned int ptp_inc;\n\tint pps_channel;\n\tunsigned int reload_period;\n\tint pps_enable;\n\tunsigned int next_counter;\n\tbool perout_enable;\n\tlong: 32;\n\tstruct hrtimer perout_timer;\n\tu64 perout_stime;\n\tstruct imx_sc_ipc *ipc_handle;\n\tstruct bpf_prog *xdp_prog;\n\tstruct {\n\t\tint pps_enable;\n\t\tlong: 32;\n\t\tu64 ns_sys;\n\t\tu64 ns_phc;\n\t\tu32 at_corr;\n\t\tu8 at_inc_corr;\n\t} ptp_saved_state;\n\tu64 ethtool_stats[0];\n};\n\nstruct fec_platform_data {\n\tphy_interface_t phy;\n\tunsigned char mac[6];\n\tvoid (*sleep_mode_enable)(int);\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n\tlong: 32;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[4];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tlong: 32;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct fec_stat {\n\tchar name[32];\n\tu16 offset;\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct trace_seq;\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tbool is_signed;\n\tbool is_string;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[4];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct ffa_device;\n\nstruct ffa_cpu_ops {\n\tint (*run)(struct ffa_device *, u16);\n};\n\nstruct ffa_ops;\n\nstruct ffa_device {\n\tu32 id;\n\tu32 properties;\n\tint vm_id;\n\tbool mode_32bit;\n\tuuid_t uuid;\n\tstruct device dev;\n\tconst struct ffa_ops *ops;\n\tlong: 32;\n};\n\nstruct ffa_device_id {\n\tuuid_t uuid;\n};\n\nstruct ffa_driver {\n\tconst char *name;\n\tint (*probe)(struct ffa_device *);\n\tvoid (*remove)(struct ffa_device *);\n\tconst struct ffa_device_id *id_table;\n\tstruct device_driver driver;\n};\n\nstruct ffa_partition_info;\n\nstruct ffa_info_ops {\n\tu32 (*api_version_get)(void);\n\tint (*partition_info_get)(const char *, struct ffa_partition_info *);\n};\n\nstruct ffa_mem_ops_args;\n\nstruct ffa_mem_ops {\n\tint (*memory_reclaim)(u64, u32);\n\tint (*memory_share)(struct ffa_mem_ops_args *);\n\tint (*memory_lend)(struct ffa_mem_ops_args *);\n};\n\nstruct ffa_mem_region_attributes;\n\nstruct ffa_mem_ops_args {\n\tbool use_txbuf;\n\tu32 nattrs;\n\tu32 flags;\n\tlong: 32;\n\tu64 tag;\n\tu64 g_handle;\n\tstruct scatterlist *sg;\n\tstruct ffa_mem_region_attributes *attrs;\n};\n\nstruct ffa_mem_region_attributes {\n\tu16 receiver;\n\tu8 attrs;\n\tu8 flag;\n\tu32 composite_off;\n\tu8 impdef_val[16];\n\tu64 reserved;\n};\n\nstruct ffa_send_direct_data;\n\nstruct ffa_send_direct_data2;\n\nstruct ffa_msg_ops {\n\tvoid (*mode_32bit_set)(struct ffa_device *);\n\tint (*sync_send_receive)(struct ffa_device *, struct ffa_send_direct_data *);\n\tint (*indirect_send)(struct ffa_device *, void *, size_t);\n\tint (*sync_send_receive2)(struct ffa_device *, struct ffa_send_direct_data2 *);\n};\n\ntypedef void (*ffa_sched_recv_cb)(u16, bool, void *);\n\ntypedef void (*ffa_notifier_cb)(int, void *);\n\ntypedef void (*ffa_fwk_notifier_cb)(int, void *, void *);\n\nstruct ffa_notifier_ops {\n\tint (*sched_recv_cb_register)(struct ffa_device *, ffa_sched_recv_cb, void *);\n\tint (*sched_recv_cb_unregister)(struct ffa_device *);\n\tint (*notify_request)(struct ffa_device *, bool, ffa_notifier_cb, void *, int);\n\tint (*notify_relinquish)(struct ffa_device *, int);\n\tint (*fwk_notify_request)(struct ffa_device *, ffa_fwk_notifier_cb, void *, int);\n\tint (*fwk_notify_relinquish)(struct ffa_device *, int);\n\tint (*notify_send)(struct ffa_device *, int, bool, u16);\n};\n\nstruct ffa_ops {\n\tconst struct ffa_info_ops *info_ops;\n\tconst struct ffa_msg_ops *msg_ops;\n\tconst struct ffa_mem_ops *mem_ops;\n\tconst struct ffa_cpu_ops *cpu_ops;\n\tconst struct ffa_notifier_ops *notifier_ops;\n};\n\nstruct ffa_partition_info {\n\tu16 id;\n\tu16 exec_ctxt;\n\tu32 properties;\n\tuuid_t uuid;\n};\n\nstruct ffa_send_direct_data {\n\tlong unsigned int data0;\n\tlong unsigned int data1;\n\tlong unsigned int data2;\n\tlong unsigned int data3;\n\tlong unsigned int data4;\n};\n\nstruct ffa_send_direct_data2 {\n\tlong unsigned int data[14];\n};\n\nstruct mtk_fh;\n\nstruct fh_operation {\n\tint (*hopping)(struct mtk_fh *, unsigned int, unsigned int);\n\tint (*ssc_enable)(struct mtk_fh *, u32);\n};\n\nstruct fh_pll_data {\n\tint pll_id;\n\tint fh_id;\n\tint fh_ver;\n\tu32 fhx_offset;\n\tu32 dds_mask;\n\tu32 slope0_value;\n\tu32 slope1_value;\n\tu32 sfstrx_en;\n\tu32 frddsx_en;\n\tu32 fhctlx_en;\n\tu32 tgl_org;\n\tu32 dvfs_tri;\n\tu32 pcwchg;\n\tu32 dt_val;\n\tu32 df_val;\n\tu32 updnlmt_shft;\n\tu32 msk_frddsx_dys;\n\tu32 msk_frddsx_dts;\n};\n\nstruct fh_pll_regs {\n\tvoid *reg_hp_en;\n\tvoid *reg_clk_con;\n\tvoid *reg_rst_con;\n\tvoid *reg_slope0;\n\tvoid *reg_slope1;\n\tvoid *reg_cfg;\n\tvoid *reg_updnlmt;\n\tvoid *reg_dds;\n\tvoid *reg_dvfs;\n\tvoid *reg_mon;\n};\n\nstruct fh_pll_state {\n\tvoid *base;\n\tu32 fh_enable;\n\tu32 ssc_rate;\n};\n\nstruct fhctl_offset {\n\tu32 offset_hp_en;\n\tu32 offset_clk_con;\n\tu32 offset_rst_con;\n\tu32 offset_slope0;\n\tu32 offset_slope1;\n\tu32 offset_cfg;\n\tu32 offset_updnlmt;\n\tu32 offset_dds;\n\tu32 offset_dvfs;\n\tu32 offset_mon;\n};\n\nstruct fib6_node;\n\nstruct fib6_walker {\n\tstruct list_head lh;\n\tstruct fib6_node *root;\n\tstruct fib6_node *node;\n\tstruct fib6_info *leaf;\n\tenum fib6_walk_state state;\n\tunsigned int skip;\n\tunsigned int count;\n\tunsigned int skip_in_node;\n\tint (*func)(struct fib6_walker *);\n\tvoid *args;\n};\n\nstruct fib6_cleaner {\n\tstruct fib6_walker w;\n\tstruct net *net;\n\tint (*func)(struct fib6_info *, void *);\n\tint sernum;\n\tvoid *arg;\n\tbool skip_notify;\n};\n\nstruct nlmsghdr;\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct fib6_dump_arg {\n\tstruct net *net;\n\tstruct notifier_block *nb;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib6_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib6_info *rt;\n\tunsigned int nsiblings;\n};\n\nstruct fib6_gc_args {\n\tint timeout;\n\tint more;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tlong unsigned int last_probe;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_nh_age_excptn_arg {\n\tstruct fib6_gc_args *gc_args;\n\tlong unsigned int now;\n};\n\nstruct fib6_nh_del_cached_rt_arg {\n\tstruct fib6_config *cfg;\n\tstruct fib6_info *f6i;\n};\n\nstruct fib6_nh_dm_arg {\n\tstruct net *net;\n\tconst struct in6_addr *saddr;\n\tint oif;\n\tint flags;\n\tstruct fib6_nh *nh;\n};\n\nstruct rt6_rtnl_dump_arg;\n\nstruct fib6_nh_exception_dump_walker {\n\tstruct rt6_rtnl_dump_arg *dump;\n\tstruct fib6_info *rt;\n\tunsigned int flags;\n\tunsigned int skip;\n\tunsigned int count;\n};\n\nstruct fib6_nh_excptn_arg {\n\tstruct rt6_info *rt;\n\tint plen;\n};\n\nstruct fib6_nh_frl_arg {\n\tu32 flags;\n\tint oif;\n\tint strict;\n\tint *mpri;\n\tbool *do_rr;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_match_arg {\n\tconst struct net_device *dev;\n\tconst struct in6_addr *gw;\n\tstruct fib6_nh *match;\n};\n\nstruct fib6_result;\n\nstruct flowi6;\n\nstruct fib6_nh_rd_arg {\n\tstruct fib6_result *res;\n\tstruct flowi6 *fl6;\n\tconst struct in6_addr *gw;\n\tstruct rt6_info **ret;\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct fib_kuid_range {\n\tkuid_t start;\n\tkuid_t end;\n};\n\nstruct fib_rule_port_range {\n\t__u16 start;\n\t__u16 end;\n};\n\nstruct fib_rule {\n\tstruct list_head list;\n\tint iifindex;\n\tint oifindex;\n\tu32 mark;\n\tu32 mark_mask;\n\tu32 flags;\n\tu32 table;\n\tu8 action;\n\tu8 l3mdev;\n\tu8 proto;\n\tu8 ip_proto;\n\tu32 target;\n\t__be64 tun_id;\n\tstruct fib_rule *ctarget;\n\tstruct net *fr_net;\n\trefcount_t refcnt;\n\tu32 pref;\n\tint suppress_ifgroup;\n\tint suppress_prefixlen;\n\tchar iifname[16];\n\tchar oifname[16];\n\tstruct fib_kuid_range uid_range;\n\tstruct fib_rule_port_range sport_range;\n\tstruct fib_rule_port_range dport_range;\n\tu16 sport_mask;\n\tu16 dport_mask;\n\tu8 iif_is_l3_master;\n\tu8 oif_is_l3_master;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_rule {\n\tstruct fib_rule common;\n\tstruct rt6key src;\n\tstruct rt6key dst;\n\t__be32 flowlabel;\n\t__be32 flowlabel_mask;\n\tdscp_t dscp;\n\tdscp_t dscp_mask;\n\tu8 dscp_full: 1;\n\tlong: 32;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_lookup_arg {\n\tvoid *lookup_ptr;\n\tconst void *lookup_data;\n\tvoid *result;\n\tstruct fib_rule *rule;\n\tu32 table;\n\tint flags;\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tlong: 32;\n\tloff_t pos;\n\tt_key key;\n\tlong: 32;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_rule_hdr {\n\t__u8 family;\n\t__u8 dst_len;\n\t__u8 src_len;\n\t__u8 tos;\n\t__u8 table;\n\t__u8 res1;\n\t__u8 res2;\n\t__u8 action;\n\t__u32 flags;\n};\n\nstruct fib_rule_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_rule *rule;\n};\n\nstruct fib_rule_uid_range {\n\t__u32 start;\n\t__u32 end;\n};\n\nstruct flowi;\n\nstruct fib_rules_ops {\n\tint family;\n\tstruct list_head list;\n\tint rule_size;\n\tint addr_size;\n\tint unresolved_rules;\n\tint nr_goto_rules;\n\tunsigned int fib_rules_seq;\n\tint (*action)(struct fib_rule *, struct flowi *, int, struct fib_lookup_arg *);\n\tbool (*suppress)(struct fib_rule *, int, struct fib_lookup_arg *);\n\tint (*match)(struct fib_rule *, struct flowi *, int);\n\tint (*configure)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*delete)(struct fib_rule *);\n\tint (*compare)(struct fib_rule *, struct fib_rule_hdr *, struct nlattr **);\n\tint (*fill)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *);\n\tsize_t (*nlmsg_payload)(struct fib_rule *);\n\tvoid (*flush_cache)(struct fib_rules_ops *);\n\tint nlgroup;\n\tstruct list_head rules_list;\n\tstruct module *owner;\n\tstruct net *fro_net;\n\tstruct callback_head rcu;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct io_uring_cmd;\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct file_range {\n\tconst struct path *path;\n\tlong: 32;\n\tloff_t pos;\n\tsize_t count;\n\tlong: 32;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[180];\n};\n\nstruct gfar_filer_entry {\n\tu32 ctrl;\n\tu32 prop;\n};\n\nstruct filer_table {\n\tu32 index;\n\tstruct gfar_filer_entry fe[530];\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[32];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct filter_head {\n\tstruct list_head list;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rcu_work rwork;\n\t};\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\nstruct regex;\n\nstruct ftrace_event_field;\n\nstruct filter_pred {\n\tstruct regex *regex;\n\tstruct cpumask *mask;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tu64 val;\n\tu64 val2;\n\tenum filter_pred_fn fn_num;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nstruct find_interface_arg {\n\tint minor;\n\tstruct device_driver *drv;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct fiper_regs {\n\tu32 tmr_fiper1;\n\tu32 tmr_fiper2;\n\tu32 tmr_fiper3;\n};\n\nstruct fiq_handler {\n\tstruct fiq_handler *next;\n\tconst char *name;\n\tint (*fiq_op)(void *, int);\n\tvoid *dev_id;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct firmware_ops {\n\tint (*prepare_idle)(long unsigned int);\n\tint (*do_idle)(long unsigned int);\n\tint (*set_cpu_boot_addr)(int, long unsigned int);\n\tint (*get_cpu_boot_addr)(int, long unsigned int *);\n\tint (*cpu_boot)(int);\n\tint (*l2x0_init)(void);\n\tint (*suspend)(void);\n\tint (*resume)(void);\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\nstruct fixed_dev_type {\n\tbool has_enable_clock;\n\tbool has_performance_state;\n};\n\nstruct fixed_factor_cfg {\n\tunsigned int mult;\n\tunsigned int div;\n};\n\nstruct fixed_partitions_quirks {\n\tint (*post_parse)(struct mtd_info *, struct mtd_partition *, int);\n};\n\nstruct fixed_phy_status {\n\tint speed;\n\tint duplex;\n\tbool link: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n};\n\nstruct fixed_phy {\n\tstruct phy_device *phydev;\n\tstruct fixed_phy_status status;\n\tint (*link_update)(struct net_device *, struct fixed_phy_status *);\n};\n\nstruct fixed_voltage_config {\n\tconst char *supply_name;\n\tconst char *input_supply;\n\tint microvolts;\n\tunsigned int startup_delay;\n\tunsigned int off_on_delay;\n\tunsigned int enabled_at_boot: 1;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct omap_device;\n\nstruct pdev_archdata {\n\tstruct omap_device *od;\n};\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tlong: 32;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n\tlong: 32;\n};\n\nstruct fixed_regulator_data {\n\tstruct fixed_voltage_config cfg;\n\tstruct regulator_init_data init_data;\n\tlong: 32;\n\tstruct platform_device pdev;\n};\n\nstruct fixed_voltage_data {\n\tstruct regulator_desc desc;\n\tstruct regulator_dev *dev;\n\tstruct clk *enable_clock;\n\tunsigned int enable_counter;\n\tint performance_state;\n};\n\nstruct flash_device {\n\tchar *name;\n\tu8 erase_cmd;\n\tu32 device_id;\n\tu32 pagesize;\n\tlong unsigned int sectorsize;\n\tlong unsigned int size_in_bytes;\n};\n\nstruct spi_nor_id;\n\nstruct spi_nor_otp_organization;\n\nstruct spi_nor_fixups;\n\nstruct flash_info {\n\tchar *name;\n\tconst struct spi_nor_id *id;\n\tsize_t size;\n\tunsigned int sector_size;\n\tu16 page_size;\n\tu8 n_banks;\n\tu8 addr_nbytes;\n\tu16 flags;\n\tu8 no_sfdp_flags;\n\tu8 fixup_flags;\n\tu8 mfr_flags;\n\tconst struct spi_nor_otp_organization *otp;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct flash_platform_data {\n\tchar *name;\n\tstruct mtd_partition *parts;\n\tunsigned int nr_parts;\n\tchar *type;\n};\n\nstruct flchip_shared {\n\tstruct mutex lock;\n\tstruct flchip *writing;\n\tstruct flchip *erasing;\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct flexgen {\n\tstruct clk_hw hw;\n\tstruct clk_mux mux;\n\tstruct clk_gate pgate;\n\tstruct clk_divider pdiv;\n\tstruct clk_gate fgate;\n\tstruct clk_divider fdiv;\n\tstruct clk_gate sync;\n\tbool control_mode;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\tlong: 32;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n\tlong: 32;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct psample_group;\n\nstruct flow_action_police {\n\tu32 burst;\n\tlong: 32;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n\tlong: 32;\n};\n\nstruct nf_flowtable;\n\nstruct action_gate_entry;\n\nstruct ip_tunnel_info;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tlong: 32;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tlong: 32;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tlong: 32;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n\tlong: 32;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tlong: 32;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_cls_common_offload {\n\tu32 chain_index;\n\t__be16 protocol;\n\tu32 prio;\n\tbool skip_sw;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct flow_cls_offload {\n\tstruct flow_cls_common_offload common;\n\tenum flow_cls_command command;\n\tbool use_act_stats;\n\tlong unsigned int cookie;\n\tstruct flow_rule *rule;\n\tlong: 32;\n\tstruct flow_stats stats;\n\tu32 classid;\n\tlong: 32;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 32;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tlong: 32;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tlong: 32;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n\tlong: 32;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n\tlong: 32;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t\tatomic_t _entire_mapcount;\n\t\t\tatomic_t _pincount;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct mem_cgroup;\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct font_data {\n\tunsigned int extra[4];\n\tconst unsigned char data[0];\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tconst void *data;\n\tint pref;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fp_hard_struct {\n\tunsigned int save[35];\n};\n\nstruct fp_soft_struct {\n\tunsigned int save[35];\n};\n\nunion fp_state {\n\tstruct fp_hard_struct hard;\n\tstruct fp_soft_struct soft;\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct rhashtable rhashtable;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct frac_entry {\n\tint num;\n\tint den;\n};\n\nstruct frac_rate_tbl {\n\tu32 div;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct frag_queue {\n\tstruct inet_frag_queue q;\n\tint iif;\n\t__u16 nhoffset;\n\tu8 ecn;\n};\n\nstruct frags_info {\n\t__le32 addr;\n\t__le32 size;\n};\n\nstruct frame_tail {\n\tstruct frame_tail *fp;\n\tlong unsigned int sp;\n\tlong unsigned int lr;\n};\n\nstruct free_area {\n\tstruct list_head free_list[6];\n\tlong unsigned int nr_free;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct freq_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpufreq_policy *, char *);\n\tssize_t (*store)(struct cpufreq_policy *, const char *, size_t);\n};\n\nstruct freq_conf {\n\tu8 src;\n\tu8 pre_div;\n\tu16 m;\n\tu16 n;\n};\n\nstruct freq_multi_tbl {\n\tlong unsigned int freq;\n\tsize_t num_confs;\n\tconst struct freq_conf *confs;\n};\n\nstruct freq_tbl {\n\tlong unsigned int freq;\n\tu8 src;\n\tu8 pre_div;\n\tu16 m;\n\tu16 n;\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tlong: 32;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fsck_data {\n\tstruct rb_root inodes;\n};\n\nstruct fsck_inode {\n\tstruct rb_node rb;\n\tino_t inum;\n\tumode_t mode;\n\tunsigned int nlink;\n\tunsigned int xattr_cnt;\n\tint references;\n\tint calc_cnt;\n\tlong: 32;\n\tlong long int size;\n\tunsigned int xattr_sz;\n\tlong: 32;\n\tlong long int calc_sz;\n\tlong long int calc_xcnt;\n\tlong long int calc_xsz;\n\tunsigned int xattr_nms;\n\tlong: 32;\n\tlong long int calc_xnms;\n};\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_nokey_name;\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsl_edma_hw_tcd {\n\t__le32 saddr;\n\t__le16 soff;\n\t__le16 attr;\n\t__le32 nbytes;\n\t__le32 slast;\n\t__le32 daddr;\n\t__le16 doff;\n\t__le16 citer;\n\t__le32 dlast_sga;\n\t__le16 csr;\n\t__le16 biter;\n};\n\nstruct fsl_edma_hw_tcd64 {\n\t__le64 saddr;\n\t__le16 soff;\n\t__le16 attr;\n\t__le32 nbytes;\n\t__le64 slast;\n\t__le64 daddr;\n\t__le64 dlast_sga;\n\t__le16 doff;\n\t__le16 citer;\n\t__le16 csr;\n\t__le16 biter;\n};\n\nstruct fsl_edma3_ch_reg {\n\t__le32 ch_csr;\n\t__le32 ch_es;\n\t__le32 ch_int;\n\t__le32 ch_sbr;\n\t__le32 ch_pri;\n\t__le32 ch_mux;\n\t__le32 ch_mattr;\n\t__le32 ch_reserved;\n\tunion {\n\t\tstruct fsl_edma_hw_tcd tcd;\n\t\tstruct fsl_edma_hw_tcd64 tcd64;\n\t};\n};\n\nstruct fsl_edma_engine;\n\nstruct fsl_edma_desc;\n\nstruct fsl_edma_chan {\n\tstruct virt_dma_chan vchan;\n\tenum dma_status status;\n\tenum fsl_edma_pm_state pm_state;\n\tstruct fsl_edma_engine *edma;\n\tstruct fsl_edma_desc *edesc;\n\tstruct dma_slave_config cfg;\n\tu32 attr;\n\tbool is_sw;\n\tstruct dma_pool *tcd_pool;\n\tdma_addr_t dma_dev_addr;\n\tu32 dma_dev_size;\n\tenum dma_data_direction dma_dir;\n\tchar chan_name[32];\n\tchar errirq_name[36];\n\tvoid *tcd;\n\tvoid *mux_addr;\n\tu32 real_count;\n\tstruct work_struct issue_worker;\n\tstruct platform_device *pdev;\n\tstruct device *pd_dev;\n\tstruct device_link *pd_dev_link;\n\tu32 srcid;\n\tstruct clk *clk;\n\tint priority;\n\tint hw_chanid;\n\tint txirq;\n\tint errirq;\n\tirqreturn_t (*irq_handler)(int, void *);\n\tirqreturn_t (*errirq_handler)(int, void *);\n\tbool is_rxchan;\n\tbool is_remote;\n\tbool is_multi_fifo;\n};\n\nstruct fsl_edma_sw_tcd {\n\tdma_addr_t ptcd;\n\tvoid *vtcd;\n};\n\nstruct fsl_edma_desc {\n\tstruct virt_dma_desc vdesc;\n\tstruct fsl_edma_chan *echan;\n\tbool iscyclic;\n\tenum dma_transfer_direction dirn;\n\tunsigned int n_tcds;\n\tstruct fsl_edma_sw_tcd tcd[0];\n};\n\nstruct fsl_edma_drvdata {\n\tu32 dmamuxs;\n\tu32 chreg_off;\n\tu32 chreg_space_sz;\n\tu32 flags;\n\tu32 mux_off;\n\tu32 mux_skip;\n\tint (*setup_irq)(struct platform_device *, struct fsl_edma_engine *);\n};\n\nstruct fsl_edma_engine {\n\tstruct dma_device dma_dev;\n\tvoid *membase;\n\tvoid *muxbase[2];\n\tstruct clk *muxclk[2];\n\tstruct clk *dmaclk;\n\tstruct mutex fsl_edma_mutex;\n\tconst struct fsl_edma_drvdata *drvdata;\n\tu32 n_chans;\n\tint txirq;\n\tint txirq_16_31;\n\tint errirq;\n\tbool big_endian;\n\tstruct edma_regs regs;\n\tu64 chan_masked;\n\tstruct fsl_edma_chan chans[0];\n};\n\nstruct fsl_gpio_soc_data {\n\tbool have_paddr;\n\tbool have_dual_base;\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_io;\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu32 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n\tconst char *driver_override;\n};\n\nstruct fsl_mc_resource_pool;\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tunsigned int virq;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\traw_spinlock_t spinlock;\n\t};\n};\n\nstruct fsl_mc_pdata {\n\tchar *name;\n\tint edac_idx;\n\tvoid *mc_vbase;\n\tvoid *inject_vbase;\n\tint irq;\n\tu32 orig_ddr_err_disable;\n\tu32 orig_ddr_err_sbe;\n\tbool little_endian;\n\tlong unsigned int flag;\n};\n\nstruct fsl_mmdc_devtype_data {\n\tunsigned int flags;\n};\n\nstruct fsl_pq_mdio_data {\n\tunsigned int mii_offset;\n\tuint32_t * (*get_tbipa)(void *);\n\tvoid (*ucc_configure)(phys_addr_t, phys_addr_t);\n};\n\nstruct fsl_pq_mii;\n\nstruct fsl_pq_mdio_priv {\n\tvoid *map;\n\tstruct fsl_pq_mii *regs;\n};\n\nstruct fsl_pq_mii {\n\tu32 miimcfg;\n\tu32 miimcom;\n\tu32 miimadd;\n\tu32 miimcon;\n\tu32 miimstat;\n\tu32 miimind;\n};\n\nstruct fsl_soc_data {\n\tconst char *sfp_compat;\n\tu32 uid_offset;\n};\n\nstruct fsl_soc_die_attr {\n\tchar *die;\n\tu32 svr;\n\tu32 mask;\n};\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tlong: 32;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fsr_info {\n\tint (*fn)(long unsigned int, unsigned int, struct pt_regs *);\n\tint sig;\n\tint code;\n\tconst char *name;\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct fsuuid {\n\t__u32 fsu_len;\n\t__u32 fsu_flags;\n\t__u8 fsu_uuid[0];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8172];\n};\n\nstruct tracer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tchar *fmt;\n\tunsigned int fmt_size;\n\tatomic_t wait_index;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool closed;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n\tlong: 32;\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int spare_size;\n\tunsigned int read;\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int args[0];\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tunsigned int is_signed: 1;\n\tunsigned int needs_test: 1;\n\tint len;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct func_repeats_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu16 count;\n\tu16 top_delta_ts;\n\tu32 bottom_delta_ts;\n};\n\nstruct function_desc {\n\tconst struct pinfunction *func;\n\tvoid *data;\n};\n\nstruct fuse_corner {\n\tint min_uV;\n\tint max_uV;\n\tint uV;\n\tint quot;\n\tint step_quot;\n\tconst struct reg_sequence *accs;\n\tint num_accs;\n\tlong unsigned int max_freq;\n\tu8 ring_osc_idx;\n};\n\nstruct fuse_corner_data {\n\tint ref_uV;\n\tint max_uV;\n\tint min_uV;\n\tint max_volt_scale;\n\tint max_quot_scale;\n\tint quot_offset;\n\tint quot_scale;\n\tint quot_adjust;\n\tint quot_offset_scale;\n\tint quot_offset_adjust;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t\tlong: 32;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tlong: 32;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_info {\n\tu32 magic;\n\tchar version[32];\n\t__le32 fw_start;\n\t__le32 fw_len;\n\tu8 chksum;\n} __attribute__((packed));\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tsize_t offset;\n\tu32 opt_flags;\n\tconst char *fw_name;\n};\n\nstruct fw_rsc_carveout {\n\tu32 da;\n\tu32 pa;\n\tu32 len;\n\tu32 flags;\n\tu32 reserved;\n\tu8 name[32];\n};\n\nstruct fw_rsc_devmem {\n\tu32 da;\n\tu32 pa;\n\tu32 len;\n\tu32 flags;\n\tu32 reserved;\n\tu8 name[32];\n};\n\nstruct fw_rsc_hdr {\n\tu32 type;\n\tu8 data[0];\n};\n\nstruct fw_rsc_trace {\n\tu32 da;\n\tu32 len;\n\tu32 reserved;\n\tu8 name[32];\n};\n\nstruct fw_rsc_vdev_vring {\n\tu32 da;\n\tu32 align;\n\tu32 num;\n\tu32 notifyid;\n\tu32 pa;\n};\n\nstruct fw_rsc_vdev {\n\tu32 id;\n\tu32 notifyid;\n\tu32 dfeatures;\n\tu32 gfeatures;\n\tu32 config_len;\n\tu8 status;\n\tu8 num_of_vrings;\n\tu8 reserved[2];\n\tstruct fw_rsc_vdev_vring vring[0];\n};\n\nstruct fwh_xxlock_thunk {\n\tenum fwh_lock_state val;\n\tflstate_t state;\n};\n\nunion fwnet_hwaddr {\n\tu8 u[16];\n\tstruct {\n\t\t__be64 uniq_id;\n\t\tu8 max_rec;\n\t\tu8 sspd;\n\t\tu8 fifo[6];\n\t} uc;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct gate_cfg {\n\tu32 reg_off;\n\tu8 bit_idx;\n\tu8 gate_flags;\n};\n\nstruct gates_data {\n\tlong unsigned int mask[1];\n};\n\nstruct host1x_bo_ops;\n\nstruct host1x_bo {\n\tconst struct host1x_bo_ops *ops;\n\tstruct list_head mappings;\n\tspinlock_t lock;\n};\n\nstruct gather_bo {\n\tstruct host1x_bo base;\n\tstruct kref ref;\n\tstruct device *dev;\n\tu32 *gather_data;\n\tdma_addr_t gather_data_dma;\n\tsize_t gather_data_words;\n};\n\nstruct gbe_emac_regs_ofs {\n\tu16 mac_control;\n\tu16 soft_reset;\n\tu16 rx_maxlen;\n};\n\nstruct gbe_host_port_regs_ofs {\n\tu16 port_vlan;\n\tu16 tx_pri_map;\n\tu16 rx_maxlen;\n};\n\nstruct gbe_hw_stats {\n\tu32 rx_good_frames;\n\tu32 rx_broadcast_frames;\n\tu32 rx_multicast_frames;\n\tu32 rx_pause_frames;\n\tu32 rx_crc_errors;\n\tu32 rx_align_code_errors;\n\tu32 rx_oversized_frames;\n\tu32 rx_jabber_frames;\n\tu32 rx_undersized_frames;\n\tu32 rx_fragments;\n\tu32 __pad_0[2];\n\tu32 rx_bytes;\n\tu32 tx_good_frames;\n\tu32 tx_broadcast_frames;\n\tu32 tx_multicast_frames;\n\tu32 tx_pause_frames;\n\tu32 tx_deferred_frames;\n\tu32 tx_collision_frames;\n\tu32 tx_single_coll_frames;\n\tu32 tx_mult_coll_frames;\n\tu32 tx_excessive_collisions;\n\tu32 tx_late_collisions;\n\tu32 tx_underrun;\n\tu32 tx_carrier_sense_errors;\n\tu32 tx_bytes;\n\tu32 tx_64byte_frames;\n\tu32 tx_65_to_127byte_frames;\n\tu32 tx_128_to_255byte_frames;\n\tu32 tx_256_to_511byte_frames;\n\tu32 tx_512_to_1023byte_frames;\n\tu32 tx_1024byte_frames;\n\tu32 net_bytes;\n\tu32 rx_sof_overruns;\n\tu32 rx_mof_overruns;\n\tu32 rx_dma_overruns;\n};\n\nstruct netcp_device;\n\nstruct netcp_tx_pipe {\n\tstruct netcp_device *netcp_device;\n\tvoid *dma_queue;\n\tunsigned int dma_queue_id;\n\tu8 switch_to_port;\n\tu8 flags;\n\tvoid *dma_channel;\n\tconst char *dma_chan_name;\n};\n\nstruct gbe_priv;\n\nstruct gbe_slave;\n\nstruct gbe_intf {\n\tstruct net_device *ndev;\n\tstruct device *dev;\n\tstruct gbe_priv *gbe_dev;\n\tstruct netcp_tx_pipe tx_pipe;\n\tstruct gbe_slave *slave;\n\tstruct list_head gbe_intf_list;\n\tlong unsigned int active_vlans[128];\n};\n\nstruct gbe_phy_init_data_fix {\n\tu16 addr;\n\tu16 value;\n};\n\nstruct gbe_port_regs_ofs {\n\tu16 port_vlan;\n\tu16 tx_pri_map;\n\tu16 rx_pri_map;\n\tu16 sa_lo;\n\tu16 sa_hi;\n\tu16 ts_ctl;\n\tu16 ts_seq_ltype;\n\tu16 ts_vlan;\n\tu16 ts_ctl_ltype2;\n\tu16 ts_ctl2;\n\tu16 rx_maxlen;\n};\n\nstruct gbe_ss_regs_ofs {\n\tu16 id_ver;\n\tu16 control;\n\tu16 rgmii_status;\n};\n\nstruct gbe_switch_regs_ofs {\n\tu16 id_ver;\n\tu16 control;\n\tu16 soft_reset;\n\tu16 emcontrol;\n\tu16 stat_port_en;\n\tu16 ptype;\n\tu16 flow_control;\n};\n\nstruct netcp_ethtool_stat;\n\nstruct gbe_priv {\n\tstruct device *dev;\n\tstruct netcp_device *netcp_device;\n\tstruct timer_list timer;\n\tu32 num_slaves;\n\tu32 ale_ports;\n\tbool enable_ale;\n\tu8 max_num_slaves;\n\tu8 max_num_ports;\n\tu8 num_stats_mods;\n\tstruct netcp_tx_pipe tx_pipe;\n\tint host_port;\n\tu32 rx_packet_max;\n\tu32 ss_version;\n\tu32 stats_en_mask;\n\tvoid *ss_regs;\n\tvoid *switch_regs;\n\tvoid *host_port_regs;\n\tvoid *ale_reg;\n\tvoid *cpts_reg;\n\tvoid *sgmii_port_regs;\n\tvoid *sgmii_port34_regs;\n\tvoid *xgbe_serdes_regs;\n\tvoid *hw_stats_regs[9];\n\tstruct gbe_ss_regs_ofs ss_regs_ofs;\n\tstruct gbe_switch_regs_ofs switch_regs_ofs;\n\tstruct gbe_host_port_regs_ofs host_port_regs_ofs;\n\tstruct cpsw_ale *ale;\n\tunsigned int tx_queue_id;\n\tconst char *dma_chan_name;\n\tstruct list_head gbe_intf_head;\n\tstruct list_head secondary_slaves;\n\tstruct net_device *dummy_ndev;\n\tu64 *hw_stats;\n\tu32 *hw_stats_prev;\n\tconst struct netcp_ethtool_stat *et_stats;\n\tint num_et_stats;\n\tspinlock_t hw_stats_lock;\n\tint cpts_registered;\n\tstruct cpts *cpts;\n\tint rx_ts_enabled;\n\tint tx_ts_enabled;\n};\n\nstruct ts_ctl {\n\tint uni;\n\tu8 dst_port_map;\n\tu8 maddr_map;\n\tu8 ts_mcast_type;\n};\n\nstruct gbe_slave {\n\tvoid *port_regs;\n\tvoid *emac_regs;\n\tstruct gbe_port_regs_ofs port_regs_ofs;\n\tstruct gbe_emac_regs_ofs emac_regs_ofs;\n\tint slave_num;\n\tint port_num;\n\tatomic_t link_state;\n\tbool open;\n\tstruct phy_device *phy;\n\tu32 link_interface;\n\tu32 mac_control;\n\tu8 phy_port_t;\n\tstruct device_node *node;\n\tstruct device_node *phy_node;\n\tstruct ts_ctl ts_ctl;\n\tstruct list_head slave_list;\n};\n\nstruct gbenu_hw_stats {\n\tu32 rx_good_frames;\n\tu32 rx_broadcast_frames;\n\tu32 rx_multicast_frames;\n\tu32 rx_pause_frames;\n\tu32 rx_crc_errors;\n\tu32 rx_align_code_errors;\n\tu32 rx_oversized_frames;\n\tu32 rx_jabber_frames;\n\tu32 rx_undersized_frames;\n\tu32 rx_fragments;\n\tu32 ale_drop;\n\tu32 ale_overrun_drop;\n\tu32 rx_bytes;\n\tu32 tx_good_frames;\n\tu32 tx_broadcast_frames;\n\tu32 tx_multicast_frames;\n\tu32 tx_pause_frames;\n\tu32 tx_deferred_frames;\n\tu32 tx_collision_frames;\n\tu32 tx_single_coll_frames;\n\tu32 tx_mult_coll_frames;\n\tu32 tx_excessive_collisions;\n\tu32 tx_late_collisions;\n\tu32 rx_ipg_error;\n\tu32 tx_carrier_sense_errors;\n\tu32 tx_bytes;\n\tu32 tx_64B_frames;\n\tu32 tx_65_to_127B_frames;\n\tu32 tx_128_to_255B_frames;\n\tu32 tx_256_to_511B_frames;\n\tu32 tx_512_to_1023B_frames;\n\tu32 tx_1024B_frames;\n\tu32 net_bytes;\n\tu32 rx_bottom_fifo_drop;\n\tu32 rx_port_mask_drop;\n\tu32 rx_top_fifo_drop;\n\tu32 ale_rate_limit_drop;\n\tu32 ale_vid_ingress_drop;\n\tu32 ale_da_eq_sa_drop;\n\tu32 __rsvd_0[3];\n\tu32 ale_unknown_ucast;\n\tu32 ale_unknown_ucast_bytes;\n\tu32 ale_unknown_mcast;\n\tu32 ale_unknown_mcast_bytes;\n\tu32 ale_unknown_bcast;\n\tu32 ale_unknown_bcast_bytes;\n\tu32 ale_pol_match;\n\tu32 ale_pol_match_red;\n\tu32 ale_pol_match_yellow;\n\tu32 __rsvd_1[44];\n\tu32 tx_mem_protect_err;\n\tu32 tx_pri0;\n\tu32 tx_pri1;\n\tu32 tx_pri2;\n\tu32 tx_pri3;\n\tu32 tx_pri4;\n\tu32 tx_pri5;\n\tu32 tx_pri6;\n\tu32 tx_pri7;\n\tu32 tx_pri0_bcnt;\n\tu32 tx_pri1_bcnt;\n\tu32 tx_pri2_bcnt;\n\tu32 tx_pri3_bcnt;\n\tu32 tx_pri4_bcnt;\n\tu32 tx_pri5_bcnt;\n\tu32 tx_pri6_bcnt;\n\tu32 tx_pri7_bcnt;\n\tu32 tx_pri0_drop;\n\tu32 tx_pri1_drop;\n\tu32 tx_pri2_drop;\n\tu32 tx_pri3_drop;\n\tu32 tx_pri4_drop;\n\tu32 tx_pri5_drop;\n\tu32 tx_pri6_drop;\n\tu32 tx_pri7_drop;\n\tu32 tx_pri0_drop_bcnt;\n\tu32 tx_pri1_drop_bcnt;\n\tu32 tx_pri2_drop_bcnt;\n\tu32 tx_pri3_drop_bcnt;\n\tu32 tx_pri4_drop_bcnt;\n\tu32 tx_pri5_drop_bcnt;\n\tu32 tx_pri6_drop_bcnt;\n\tu32 tx_pri7_drop_bcnt;\n};\n\nstruct gcry_mpi;\n\ntypedef struct gcry_mpi *MPI;\n\nstruct gcry_mpi {\n\tint alloced;\n\tint nlimbs;\n\tint nbits;\n\tint sign;\n\tunsigned int flags;\n\tmpi_limb_t *d;\n};\n\nstruct gdsc {\n\tstruct generic_pm_domain pd;\n\tstruct generic_pm_domain *parent;\n\tstruct regmap *regmap;\n\tunsigned int gdscr;\n\tunsigned int collapse_ctrl;\n\tunsigned int collapse_mask;\n\tunsigned int gds_hw_ctrl;\n\tunsigned int clamp_io_ctrl;\n\tunsigned int *cxcs;\n\tunsigned int cxc_count;\n\tunsigned int en_rest_wait_val;\n\tunsigned int en_few_wait_val;\n\tunsigned int clk_dis_wait_val;\n\tconst u8 pwrsts;\n\tconst u16 flags;\n\tstruct reset_controller_dev *rcdev;\n\tunsigned int *resets;\n\tunsigned int reset_count;\n\tconst char *supply;\n\tstruct regulator *rsupply;\n};\n\nstruct gdsc_desc {\n\tstruct device *dev;\n\tstruct gdsc **scs;\n\tsize_t num;\n\tstruct dev_pm_domain_list *pd_list;\n};\n\nstruct gem_statistic {\n\tchar stat_string[32];\n\tint offset;\n\tu32 stat_bits;\n};\n\nstruct gem_stats {\n\tu64 tx_octets;\n\tu64 tx_frames;\n\tu64 tx_broadcast_frames;\n\tu64 tx_multicast_frames;\n\tu64 tx_pause_frames;\n\tu64 tx_64_byte_frames;\n\tu64 tx_65_127_byte_frames;\n\tu64 tx_128_255_byte_frames;\n\tu64 tx_256_511_byte_frames;\n\tu64 tx_512_1023_byte_frames;\n\tu64 tx_1024_1518_byte_frames;\n\tu64 tx_greater_than_1518_byte_frames;\n\tu64 tx_underrun;\n\tu64 tx_single_collision_frames;\n\tu64 tx_multiple_collision_frames;\n\tu64 tx_excessive_collisions;\n\tu64 tx_late_collisions;\n\tu64 tx_deferred_frames;\n\tu64 tx_carrier_sense_errors;\n\tu64 rx_octets;\n\tu64 rx_frames;\n\tu64 rx_broadcast_frames;\n\tu64 rx_multicast_frames;\n\tu64 rx_pause_frames;\n\tu64 rx_64_byte_frames;\n\tu64 rx_65_127_byte_frames;\n\tu64 rx_128_255_byte_frames;\n\tu64 rx_256_511_byte_frames;\n\tu64 rx_512_1023_byte_frames;\n\tu64 rx_1024_1518_byte_frames;\n\tu64 rx_greater_than_1518_byte_frames;\n\tu64 rx_undersized_frames;\n\tu64 rx_oversize_frames;\n\tu64 rx_jabbers;\n\tu64 rx_frame_check_sequence_errors;\n\tu64 rx_length_field_frame_errors;\n\tu64 rx_symbol_errors;\n\tu64 rx_alignment_errors;\n\tu64 rx_resource_errors;\n\tu64 rx_overruns;\n\tu64 rx_ip_header_checksum_errors;\n\tu64 rx_tcp_checksum_errors;\n\tu64 rx_udp_checksum_errors;\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tstruct cdrom_device_info *cdi;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tlong: 32;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n\tlong: 32;\n};\n\nstruct pm_domain_data {\n\tstruct list_head list_node;\n\tstruct device *dev;\n};\n\nstruct gpd_timing_data;\n\nstruct generic_pm_domain_data {\n\tstruct pm_domain_data base;\n\tstruct gpd_timing_data *td;\n\tstruct notifier_block nb;\n\tstruct notifier_block *power_nb;\n\tint cpu;\n\tunsigned int performance_state;\n\tunsigned int default_pstate;\n\tunsigned int rpm_pstate;\n\tunsigned int opp_token;\n\tbool hw_mode;\n\tbool rpm_always_on;\n\tvoid *data;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct netlink_callback;\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpd_governor_data {\n\ts64 max_off_time_ns;\n\tbool max_off_time_changed;\n\tlong: 32;\n\tktime_t next_wakeup;\n\tktime_t next_hrtimer;\n\tktime_t last_enter;\n\tbool reflect_residency;\n\tbool cached_power_down_ok;\n\tbool cached_power_down_state_idx;\n\tlong: 32;\n};\n\nstruct genpd_lock_ops {\n\tvoid (*lock)(struct generic_pm_domain *);\n\tvoid (*lock_nested)(struct generic_pm_domain *, int);\n\tint (*lock_interruptible)(struct generic_pm_domain *);\n\tvoid (*unlock)(struct generic_pm_domain *);\n};\n\nstruct genpd_power_state {\n\tconst char *name;\n\tlong: 32;\n\ts64 power_off_latency_ns;\n\ts64 power_on_latency_ns;\n\ts64 residency_ns;\n\tu64 usage;\n\tu64 rejected;\n\tu64 above;\n\tu64 below;\n\tstruct fwnode_handle *fwnode;\n\tlong: 32;\n\tu64 idle_time;\n\tvoid *data;\n\tlong: 32;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[128];\n\t\tu8 data[512];\n\t};\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n\tlong: 32;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tlong: 32;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n\tlong: 32;\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct gf_poly {\n\tunsigned int deg;\n\tunsigned int c[0];\n};\n\nstruct gf_poly_deg1 {\n\tstruct gf_poly poly;\n\tunsigned int c[2];\n};\n\nstruct rmon_mib {\n\tu32 tr64;\n\tu32 tr127;\n\tu32 tr255;\n\tu32 tr511;\n\tu32 tr1k;\n\tu32 trmax;\n\tu32 trmgv;\n\tu32 rbyt;\n\tu32 rpkt;\n\tu32 rfcs;\n\tu32 rmca;\n\tu32 rbca;\n\tu32 rxcf;\n\tu32 rxpf;\n\tu32 rxuo;\n\tu32 raln;\n\tu32 rflr;\n\tu32 rcde;\n\tu32 rcse;\n\tu32 rund;\n\tu32 rovr;\n\tu32 rfrg;\n\tu32 rjbr;\n\tu32 rdrp;\n\tu32 tbyt;\n\tu32 tpkt;\n\tu32 tmca;\n\tu32 tbca;\n\tu32 txpf;\n\tu32 tdfr;\n\tu32 tedf;\n\tu32 tscl;\n\tu32 tmcl;\n\tu32 tlcl;\n\tu32 txcl;\n\tu32 tncl;\n\tu8 res1[4];\n\tu32 tdrp;\n\tu32 tjbr;\n\tu32 tfcs;\n\tu32 txcf;\n\tu32 tovr;\n\tu32 tund;\n\tu32 tfrg;\n\tu32 car1;\n\tu32 car2;\n\tu32 cam1;\n\tu32 cam2;\n};\n\nstruct gfar {\n\tu32 tsec_id;\n\tu32 tsec_id2;\n\tu8 res1[8];\n\tu32 ievent;\n\tu32 imask;\n\tu32 edis;\n\tu32 emapg;\n\tu32 ecntrl;\n\tu32 minflr;\n\tu32 ptv;\n\tu32 dmactrl;\n\tu32 tbipa;\n\tu8 res2[28];\n\tu32 fifo_rx_pause;\n\tu32 fifo_rx_pause_shutoff;\n\tu32 fifo_rx_alarm;\n\tu32 fifo_rx_alarm_shutoff;\n\tu8 res3[44];\n\tu32 fifo_tx_thr;\n\tu8 res4[8];\n\tu32 fifo_tx_starve;\n\tu32 fifo_tx_starve_shutoff;\n\tu8 res5[96];\n\tu32 tctrl;\n\tu32 tstat;\n\tu32 dfvlan;\n\tu32 tbdlen;\n\tu32 txic;\n\tu32 tqueue;\n\tu8 res7[40];\n\tu32 tr03wt;\n\tu32 tr47wt;\n\tu8 res8[52];\n\tu32 tbdbph;\n\tu8 res9a[4];\n\tu32 tbptr0;\n\tu8 res9b[4];\n\tu32 tbptr1;\n\tu8 res9c[4];\n\tu32 tbptr2;\n\tu8 res9d[4];\n\tu32 tbptr3;\n\tu8 res9e[4];\n\tu32 tbptr4;\n\tu8 res9f[4];\n\tu32 tbptr5;\n\tu8 res9g[4];\n\tu32 tbptr6;\n\tu8 res9h[4];\n\tu32 tbptr7;\n\tu8 res9[64];\n\tu32 tbaseh;\n\tu32 tbase0;\n\tu8 res10a[4];\n\tu32 tbase1;\n\tu8 res10b[4];\n\tu32 tbase2;\n\tu8 res10c[4];\n\tu32 tbase3;\n\tu8 res10d[4];\n\tu32 tbase4;\n\tu8 res10e[4];\n\tu32 tbase5;\n\tu8 res10f[4];\n\tu32 tbase6;\n\tu8 res10g[4];\n\tu32 tbase7;\n\tu8 res10[192];\n\tu32 rctrl;\n\tu32 rstat;\n\tu8 res12[8];\n\tu32 rxic;\n\tu32 rqueue;\n\tu32 rir0;\n\tu32 rir1;\n\tu32 rir2;\n\tu32 rir3;\n\tu8 res13[8];\n\tu32 rbifx;\n\tu32 rqfar;\n\tu32 rqfcr;\n\tu32 rqfpr;\n\tu32 mrblr;\n\tu8 res14[56];\n\tu32 rbdbph;\n\tu8 res15a[4];\n\tu32 rbptr0;\n\tu8 res15b[4];\n\tu32 rbptr1;\n\tu8 res15c[4];\n\tu32 rbptr2;\n\tu8 res15d[4];\n\tu32 rbptr3;\n\tu8 res15e[4];\n\tu32 rbptr4;\n\tu8 res15f[4];\n\tu32 rbptr5;\n\tu8 res15g[4];\n\tu32 rbptr6;\n\tu8 res15h[4];\n\tu32 rbptr7;\n\tu8 res16[64];\n\tu32 rbaseh;\n\tu32 rbase0;\n\tu8 res17a[4];\n\tu32 rbase1;\n\tu8 res17b[4];\n\tu32 rbase2;\n\tu8 res17c[4];\n\tu32 rbase3;\n\tu8 res17d[4];\n\tu32 rbase4;\n\tu8 res17e[4];\n\tu32 rbase5;\n\tu8 res17f[4];\n\tu32 rbase6;\n\tu8 res17g[4];\n\tu32 rbase7;\n\tu8 res17[192];\n\tu32 maccfg1;\n\tu32 maccfg2;\n\tu32 ipgifg;\n\tu32 hafdup;\n\tu32 maxfrm;\n\tu8 res18[12];\n\tu8 gfar_mii_regs[24];\n\tu32 ifctrl;\n\tu32 ifstat;\n\tu32 macstnaddr1;\n\tu32 macstnaddr2;\n\tu32 mac01addr1;\n\tu32 mac01addr2;\n\tu32 mac02addr1;\n\tu32 mac02addr2;\n\tu32 mac03addr1;\n\tu32 mac03addr2;\n\tu32 mac04addr1;\n\tu32 mac04addr2;\n\tu32 mac05addr1;\n\tu32 mac05addr2;\n\tu32 mac06addr1;\n\tu32 mac06addr2;\n\tu32 mac07addr1;\n\tu32 mac07addr2;\n\tu32 mac08addr1;\n\tu32 mac08addr2;\n\tu32 mac09addr1;\n\tu32 mac09addr2;\n\tu32 mac10addr1;\n\tu32 mac10addr2;\n\tu32 mac11addr1;\n\tu32 mac11addr2;\n\tu32 mac12addr1;\n\tu32 mac12addr2;\n\tu32 mac13addr1;\n\tu32 mac13addr2;\n\tu32 mac14addr1;\n\tu32 mac14addr2;\n\tu32 mac15addr1;\n\tu32 mac15addr2;\n\tu8 res20[192];\n\tstruct rmon_mib rmon;\n\tu32 rrej;\n\tu8 res21[188];\n\tu32 igaddr0;\n\tu32 igaddr1;\n\tu32 igaddr2;\n\tu32 igaddr3;\n\tu32 igaddr4;\n\tu32 igaddr5;\n\tu32 igaddr6;\n\tu32 igaddr7;\n\tu8 res22[96];\n\tu32 gaddr0;\n\tu32 gaddr1;\n\tu32 gaddr2;\n\tu32 gaddr3;\n\tu32 gaddr4;\n\tu32 gaddr5;\n\tu32 gaddr6;\n\tu32 gaddr7;\n\tu8 res23a[352];\n\tu32 fifocfg;\n\tu8 res23b[252];\n\tu8 res23c[248];\n\tu32 attr;\n\tu32 attreli;\n\tu32 rqprm0;\n\tu32 rqprm1;\n\tu32 rqprm2;\n\tu32 rqprm3;\n\tu32 rqprm4;\n\tu32 rqprm5;\n\tu32 rqprm6;\n\tu32 rqprm7;\n\tu8 res24[36];\n\tu32 rfbptr0;\n\tu8 res24a[4];\n\tu32 rfbptr1;\n\tu8 res24b[4];\n\tu32 rfbptr2;\n\tu8 res24c[4];\n\tu32 rfbptr3;\n\tu8 res24d[4];\n\tu32 rfbptr4;\n\tu8 res24e[4];\n\tu32 rfbptr5;\n\tu8 res24f[4];\n\tu32 rfbptr6;\n\tu8 res24g[4];\n\tu32 rfbptr7;\n\tu8 res24h[4];\n\tu8 res24x[556];\n\tu32 isrg0;\n\tu32 isrg1;\n\tu32 isrg2;\n\tu32 isrg3;\n\tu8 res25[16];\n\tu32 rxic0;\n\tu32 rxic1;\n\tu32 rxic2;\n\tu32 rxic3;\n\tu32 rxic4;\n\tu32 rxic5;\n\tu32 rxic6;\n\tu32 rxic7;\n\tu8 res26[32];\n\tu32 txic0;\n\tu32 txic1;\n\tu32 txic2;\n\tu32 txic3;\n\tu32 txic4;\n\tu32 txic5;\n\tu32 txic6;\n\tu32 txic7;\n\tu8 res27[208];\n};\n\nstruct gfar_extra_stats {\n\tatomic64_t rx_alloc_err;\n\tatomic64_t rx_large;\n\tatomic64_t rx_short;\n\tatomic64_t rx_nonoctet;\n\tatomic64_t rx_crcerr;\n\tatomic64_t rx_overrun;\n\tatomic64_t rx_bsy;\n\tatomic64_t rx_babr;\n\tatomic64_t rx_trunc;\n\tatomic64_t eberr;\n\tatomic64_t tx_babt;\n\tatomic64_t tx_underrun;\n\tatomic64_t tx_timeout;\n};\n\nstruct gfar_irqinfo {\n\tunsigned int irq;\n\tchar name[22];\n};\n\nstruct gfar_priv_tx_q;\n\nstruct gfar_priv_rx_q;\n\nstruct gfar_private;\n\nstruct gfar_priv_grp {\n\tspinlock_t grplock;\n\tlong: 32;\n\tstruct napi_struct napi_rx;\n\tstruct napi_struct napi_tx;\n\tstruct gfar *regs;\n\tstruct gfar_priv_tx_q *tx_queue;\n\tstruct gfar_priv_rx_q *rx_queue;\n\tunsigned int tstat;\n\tunsigned int rstat;\n\tstruct gfar_private *priv;\n\tlong unsigned int num_tx_queues;\n\tlong unsigned int tx_bit_map;\n\tlong unsigned int num_rx_queues;\n\tlong unsigned int rx_bit_map;\n\tstruct gfar_irqinfo *irqinfo[3];\n\tlong: 32;\n};\n\nstruct rx_q_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_dropped;\n};\n\nstruct gfar_rx_buff;\n\nstruct rxbd8;\n\nstruct gfar_priv_rx_q {\n\tstruct gfar_rx_buff *rx_buff;\n\tstruct rxbd8 *rx_bd_base;\n\tstruct net_device *ndev;\n\tstruct device *dev;\n\tu16 rx_ring_size;\n\tu16 qindex;\n\tstruct gfar_priv_grp *grp;\n\tu16 next_to_clean;\n\tu16 next_to_use;\n\tu16 next_to_alloc;\n\tstruct sk_buff *skb;\n\tlong: 32;\n\tstruct rx_q_stats stats;\n\tu32 *rfbptr;\n\tunsigned char rxcoalescing;\n\tlong unsigned int rxic;\n\tdma_addr_t rx_bd_dma_base;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct tx_q_stats {\n\tu64 tx_packets;\n\tu64 tx_bytes;\n};\n\nstruct txbd8;\n\nstruct gfar_priv_tx_q {\n\tspinlock_t txlock;\n\tstruct txbd8 *tx_bd_base;\n\tstruct txbd8 *cur_tx;\n\tunsigned int num_txbdfree;\n\tshort unsigned int skb_curtx;\n\tshort unsigned int tx_ring_size;\n\tlong: 32;\n\tstruct tx_q_stats stats;\n\tstruct gfar_priv_grp *grp;\n\tstruct net_device *dev;\n\tstruct sk_buff **tx_skbuff;\n\tstruct txbd8 *dirty_tx;\n\tshort unsigned int skb_dirtytx;\n\tshort unsigned int qindex;\n\tunsigned int txcoalescing;\n\tlong unsigned int txic;\n\tdma_addr_t tx_bd_dma_base;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rmon_overflow {\n\tspinlock_t lock;\n\tu32 imask;\n\tu64 rdrp;\n};\n\nstruct gfar_private {\n\tstruct device *dev;\n\tstruct net_device *ndev;\n\tenum gfar_errata errata;\n\tu16 uses_rxfcb;\n\tu16 padding;\n\tu32 device_flags;\n\tint hwts_rx_en;\n\tint hwts_tx_en;\n\tstruct gfar_priv_tx_q *tx_queue[8];\n\tstruct gfar_priv_rx_q *rx_queue[8];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct gfar_priv_grp gfargrp[2];\n\tlong unsigned int state;\n\tshort unsigned int mode;\n\tunsigned int num_tx_queues;\n\tunsigned int num_rx_queues;\n\tunsigned int num_grps;\n\tint tx_actual_en;\n\tstruct gfar_extra_stats extra_stats;\n\tstruct rmon_overflow rmon_overflow;\n\tphy_interface_t interface;\n\tstruct device_node *phy_node;\n\tstruct device_node *tbi_node;\n\tstruct mii_bus *mii_bus;\n\tint oldspeed;\n\tint oldduplex;\n\tint oldlink;\n\tuint32_t msg_enable;\n\tstruct work_struct reset_task;\n\tstruct platform_device *ofdev;\n\tunsigned char extended_hash: 1;\n\tunsigned char bd_stash_en: 1;\n\tunsigned char rx_filer_enable: 1;\n\tunsigned char prio_sched_en: 1;\n\tunsigned char pause_aneg_en: 1;\n\tunsigned char tx_pause_en: 1;\n\tunsigned char rx_pause_en: 1;\n\tunsigned int total_tx_ring_size;\n\tunsigned int total_rx_ring_size;\n\tu32 rqueue;\n\tu32 tqueue;\n\tunsigned int rx_stash_size;\n\tunsigned int rx_stash_index;\n\tu32 cur_filer_idx;\n\tstruct ethtool_rx_list rx_list;\n\tstruct mutex rx_queue_access;\n\tu32 *hash_regs[16];\n\tint hash_width;\n\tu16 wol_opts;\n\tu16 wol_supported;\n\tunsigned int ftp_rqfpr[256];\n\tunsigned int ftp_rqfcr[256];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct gfar_rx_buff {\n\tdma_addr_t dma;\n\tstruct page *page;\n\tunsigned int page_offset;\n};\n\nstruct gianfar_skb_cb {\n\tunsigned int bytes_sent;\n};\n\nunion gic_base {\n\tvoid *common_base;\n\tvoid **percpu_base;\n};\n\nstruct rdists {\n\tstruct {\n\t\traw_spinlock_t rd_lock;\n\t\tvoid *rd_base;\n\t\tstruct page *pend_page;\n\t\tphys_addr_t phys_base;\n\t\tu64 flags;\n\t\tcpumask_t *vpe_table_mask;\n\t\tvoid *vpe_l1_base;\n\t} *rdist;\n\tphys_addr_t prop_table_pa;\n\tvoid *prop_table_va;\n\tlong: 32;\n\tu64 flags;\n\tu32 gicd_typer;\n\tu32 gicd_typer2;\n\tint cpuhp_memreserve_state;\n\tbool has_vlpis;\n\tbool has_rvpeid;\n\tbool has_direct_lpi;\n\tbool has_vpend_valid_dirty;\n};\n\nstruct redist_region;\n\nstruct partition_affinity;\n\nstruct gic_chip_data {\n\tstruct fwnode_handle *fwnode;\n\tphys_addr_t dist_phys_base;\n\tvoid *dist_base;\n\tstruct redist_region *redist_regions;\n\tstruct rdists rdists;\n\tstruct irq_domain *domain;\n\tlong: 32;\n\tu64 redist_stride;\n\tu32 nr_redist_regions;\n\tlong: 32;\n\tu64 flags;\n\tbool has_rss;\n\tunsigned int ppi_nr;\n\tstruct partition_affinity *parts;\n\tunsigned int nr_parts;\n};\n\nstruct gic_chip_data___2 {\n\tunion gic_base dist_base;\n\tunion gic_base cpu_base;\n\tvoid *raw_dist_base;\n\tvoid *raw_cpu_base;\n\tu32 percpu_offset;\n\tu32 saved_spi_enable[32];\n\tu32 saved_spi_active[32];\n\tu32 saved_spi_conf[64];\n\tu32 saved_spi_target[255];\n\tu32 *saved_ppi_enable;\n\tu32 *saved_ppi_active;\n\tu32 *saved_ppi_conf;\n\tstruct irq_domain *domain;\n\tunsigned int gic_irqs;\n};\n\nstruct gic_kvm_info {\n\tenum gic_type type;\n\tstruct resource vcpu;\n\tvoid *gicc_base;\n\tunsigned int maint_irq;\n\tbool no_maint_irq_mask;\n\tstruct resource vctrl;\n\tbool has_v4;\n\tbool has_v4_1;\n\tbool no_hw_deactivation;\n};\n\nstruct gic_quirk {\n\tconst char *desc;\n\tconst char *compatible;\n\tconst char *property;\n\tbool (*init)(void *);\n\tu32 iidr;\n\tu32 mask;\n};\n\nstruct giveback_urb_bh {\n\tbool running;\n\tbool high_prio;\n\tspinlock_t lock;\n\tstruct list_head head;\n\tstruct work_struct bh;\n\tstruct usb_host_endpoint *completing_ep;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n\tlong: 32;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n\tlong: 32;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct governor_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gov_attr_set *, char *);\n\tssize_t (*store)(struct gov_attr_set *, const char *, size_t);\n};\n\nstruct gpcv2_irqchip_data {\n\tstruct raw_spinlock rlock;\n\tvoid *gpc_base;\n\tu32 wakeup_sources[4];\n\tu32 saved_irq_mask[4];\n\tu32 cpu2wakeup;\n};\n\nstruct gpd_link {\n\tstruct generic_pm_domain *parent;\n\tstruct list_head parent_node;\n\tstruct generic_pm_domain *child;\n\tstruct list_head child_node;\n\tunsigned int performance_state;\n\tunsigned int prev_performance_state;\n};\n\nstruct gpd_timing_data {\n\ts64 suspend_latency_ns;\n\ts64 resume_latency_ns;\n\ts64 effective_constraint_ns;\n\tktime_t next_wakeup;\n\tbool constraint_changed;\n\tbool cached_suspend_ok;\n\tlong: 32;\n};\n\nstruct gpio_array {\n\tstruct gpio_desc **desc;\n\tunsigned int size;\n\tstruct gpio_device *gdev;\n\tlong unsigned int *get_mask;\n\tlong unsigned int *set_mask;\n\tlong unsigned int invert_mask[0];\n};\n\nstruct gpio_backlight {\n\tstruct device *dev;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct gpio_backlight_platform_data {\n\tstruct device *dev;\n};\n\nstruct gpio_regs {\n\tu32 sysconfig;\n\tu32 irqenable1;\n\tu32 irqenable2;\n\tu32 wake_en;\n\tu32 ctrl;\n\tu32 oe;\n\tu32 leveldetect0;\n\tu32 leveldetect1;\n\tu32 risingdetect;\n\tu32 fallingdetect;\n\tu32 dataout;\n\tu32 debounce;\n\tu32 debounce_en;\n};\n\nstruct omap_gpio_reg_offs;\n\nstruct gpio_bank {\n\tvoid *base;\n\tconst struct omap_gpio_reg_offs *regs;\n\tstruct device *dev;\n\tint irq;\n\tu32 non_wakeup_gpios;\n\tu32 enabled_non_wakeup_gpios;\n\tstruct gpio_regs context;\n\tu32 saved_datain;\n\tu32 level_mask;\n\tu32 toggle_mask;\n\traw_spinlock_t lock;\n\traw_spinlock_t wa_lock;\n\tstruct gpio_chip chip;\n\tstruct clk *dbck;\n\tstruct notifier_block nb;\n\tunsigned int is_suspended: 1;\n\tunsigned int needs_resume: 1;\n\tu32 mod_usage;\n\tu32 irq_usage;\n\tu32 dbck_enable_mask;\n\tbool dbck_enabled;\n\tbool is_mpuio;\n\tbool dbck_flag;\n\tbool loses_context;\n\tbool context_valid;\n\tint stride;\n\tu32 width;\n\tint context_loss_count;\n\tvoid (*set_dataout)(struct gpio_bank *, unsigned int, int);\n\tint (*get_context_loss_count)(struct device *);\n};\n\nstruct gpio_keys_button;\n\nstruct gpio_button_data {\n\tconst struct gpio_keys_button *button;\n\tstruct input_dev *input;\n\tstruct gpio_desc *gpiod;\n\tshort unsigned int *code;\n\tstruct hrtimer release_timer;\n\tunsigned int release_delay;\n\tstruct delayed_work work;\n\tstruct hrtimer debounce_timer;\n\tunsigned int software_debounce;\n\tunsigned int irq;\n\tunsigned int wakeirq;\n\tunsigned int wakeup_trigger_type;\n\tspinlock_t lock;\n\tbool disabled;\n\tbool key_pressed;\n\tbool suspended;\n\tbool debounce_use_hrtimer;\n};\n\nstruct gpio_v2_line_attribute {\n\t__u32 id;\n\t__u32 padding;\n\tunion {\n\t\t__u64 flags;\n\t\t__u64 values;\n\t\t__u32 debounce_period_us;\n\t};\n};\n\nstruct gpio_v2_line_info {\n\tchar name[32];\n\tchar consumer[32];\n\t__u32 offset;\n\t__u32 num_attrs;\n\t__u64 flags;\n\tstruct gpio_v2_line_attribute attrs[10];\n\t__u32 padding[4];\n};\n\nstruct gpio_v2_line_info_changed {\n\tstruct gpio_v2_line_info info;\n\t__u64 timestamp_ns;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct gpio_chardev_data {\n\tstruct gpio_device *gdev;\n\twait_queue_head_t wait;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_info_changed *type;\n\t\t\tconst struct gpio_v2_line_info_changed *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_info_changed *ptr;\n\t\t\tconst struct gpio_v2_line_info_changed *ptr_const;\n\t\t};\n\t\tlong: 32;\n\t\tstruct gpio_v2_line_info_changed buf[32];\n\t} events;\n\tstruct notifier_block lineinfo_changed_nb;\n\tstruct notifier_block device_unregistered_nb;\n\tlong unsigned int *watched_lines;\n\tatomic_t watch_abi_version;\n\tstruct file *fp;\n\tlong: 32;\n};\n\nstruct gpio_chip_guard {\n\tstruct gpio_device *gdev;\n\tstruct gpio_chip *gc;\n\tint idx;\n};\n\ntypedef struct gpio_chip_guard class_gpio_chip_guard_t;\n\nstruct gpio_desc_label;\n\nstruct gpio_desc {\n\tstruct gpio_device *gdev;\n\tlong unsigned int flags;\n\tstruct gpio_desc_label *label;\n\tconst char *name;\n\tstruct device_node *hog;\n\tunsigned int debounce_period_us;\n};\n\nstruct gpio_desc_label {\n\tstruct callback_head rh;\n\tchar str[0];\n};\n\nstruct gpio_descs {\n\tstruct gpio_array *info;\n\tunsigned int ndescs;\n\tstruct gpio_desc *desc[0];\n};\n\nstruct gpio_device {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tstruct module *owner;\n\tstruct gpio_chip *chip;\n\tstruct gpio_desc *descs;\n\tlong unsigned int *valid_mask;\n\tstruct srcu_struct desc_srcu;\n\tunsigned int base;\n\tu16 ngpio;\n\tbool can_sleep;\n\tconst char *label;\n\tvoid *data;\n\tstruct list_head list;\n\tstruct raw_notifier_head line_state_notifier;\n\trwlock_t line_state_lock;\n\tstruct workqueue_struct *line_state_wq;\n\tstruct blocking_notifier_head device_notifier;\n\tstruct srcu_struct srcu;\n\tstruct list_head pin_ranges;\n};\n\nstruct gpio_generic_chip_config {\n\tstruct device *dev;\n\tlong unsigned int sz;\n\tvoid *dat;\n\tvoid *set;\n\tvoid *clr;\n\tvoid *dirout;\n\tvoid *dirin;\n\tlong unsigned int flags;\n};\n\nstruct gpio_get_config {\n\tu32 gpio;\n\tu32 direction;\n\tu32 polarity;\n\tu32 term_en;\n\tu32 term_pull_up;\n};\n\nstruct gpio_get_set_state {\n\tu32 gpio;\n\tu32 state;\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct msi_desc;\n\nstruct msi_alloc_info {\n\tstruct msi_desc *desc;\n\tirq_hw_number_t hwirq;\n\tlong unsigned int flags;\n\tunion {\n\t\tlong unsigned int ul;\n\t\tvoid *ptr;\n\t} scratchpad[2];\n};\n\ntypedef struct msi_alloc_info msi_alloc_info_t;\n\nunion gpio_irq_fwspec {\n\tstruct irq_fwspec fwspec;\n\tmsi_alloc_info_t msiinfo;\n};\n\nstruct gpio_keys_button {\n\tunsigned int code;\n\tint gpio;\n\tint active_low;\n\tconst char *desc;\n\tunsigned int type;\n\tint wakeup;\n\tint wakeup_event_action;\n\tint debounce_interval;\n\tbool can_disable;\n\tint value;\n\tunsigned int irq;\n\tunsigned int wakeirq;\n};\n\nstruct gpio_keys_platform_data;\n\nstruct gpio_keys_drvdata {\n\tconst struct gpio_keys_platform_data *pdata;\n\tstruct input_dev *input;\n\tstruct mutex disable_lock;\n\tshort unsigned int *keymap;\n\tstruct gpio_button_data data[0];\n};\n\nstruct gpio_keys_platform_data {\n\tconst struct gpio_keys_button *buttons;\n\tint nbuttons;\n\tunsigned int poll_interval;\n\tunsigned int rep: 1;\n\tint (*enable)(struct device *);\n\tvoid (*disable)(struct device *);\n\tconst char *name;\n};\n\nstruct gpio_led {\n\tconst char *name;\n\tconst char *default_trigger;\n\tunsigned int gpio;\n\tunsigned int active_low: 1;\n\tunsigned int retain_state_suspended: 1;\n\tunsigned int panic_indicator: 1;\n\tunsigned int default_state: 2;\n\tunsigned int retain_state_shutdown: 1;\n\tstruct gpio_desc *gpiod;\n};\n\ntypedef int (*gpio_blink_set_t)(struct gpio_desc *, int, long unsigned int *, long unsigned int *);\n\nstruct gpio_led_data {\n\tstruct led_classdev cdev;\n\tstruct gpio_desc *gpiod;\n\tu8 can_sleep;\n\tu8 blinking;\n\tgpio_blink_set_t platform_gpio_blink_set;\n};\n\nstruct gpio_led_platform_data {\n\tint num_leds;\n\tconst struct gpio_led *leds;\n\tgpio_blink_set_t gpio_blink_set;\n};\n\nstruct gpio_leds_priv {\n\tint num_leds;\n\tstruct gpio_led_data leds[0];\n};\n\nstruct gpio_pin_range {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_gpio_range range;\n};\n\nstruct gpio_poweroff {\n\tstruct gpio_desc *reset_gpio;\n\tu32 timeout_ms;\n\tu32 active_delay_ms;\n\tu32 inactive_delay_ms;\n};\n\nstruct gpio_rcar_bank_info {\n\tu32 iointsel;\n\tu32 inoutsel;\n\tu32 outdt;\n\tu32 posneg;\n\tu32 edglevel;\n\tu32 bothedge;\n\tu32 intmsk;\n};\n\nstruct gpio_rcar_info {\n\tbool has_outdtsel;\n\tbool has_both_edge_trigger;\n\tbool has_always_in;\n\tbool has_inen;\n};\n\nstruct gpio_rcar_priv {\n\tvoid *base;\n\traw_spinlock_t lock;\n\tstruct device *dev;\n\tstruct gpio_chip gpio_chip;\n\tunsigned int irq_parent;\n\tatomic_t wakeup_path;\n\tstruct gpio_rcar_info info;\n\tstruct gpio_rcar_bank_info bank_info;\n};\n\nstruct gpio_regs___2 {\n\tu32 datamsw[6];\n\tu32 datalsw[6];\n\tu32 dirm[6];\n\tu32 outen[6];\n\tu32 int_en[6];\n\tu32 int_dis[6];\n\tu32 int_type[6];\n\tu32 int_polarity[6];\n\tu32 int_any[6];\n};\n\nstruct gpio_regulator_state;\n\nstruct gpio_regulator_config {\n\tconst char *supply_name;\n\tconst char *input_supply;\n\tunsigned int enabled_at_boot: 1;\n\tunsigned int startup_delay;\n\tenum gpiod_flags *gflags;\n\tint ngpios;\n\tstruct gpio_regulator_state *states;\n\tint nr_states;\n\tenum regulator_type type;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct gpio_regulator_data {\n\tstruct regulator_desc desc;\n\tstruct gpio_desc **gpiods;\n\tint nr_gpios;\n\tstruct gpio_regulator_state *states;\n\tint nr_states;\n\tint state;\n};\n\nstruct gpio_regulator_state {\n\tint value;\n\tint gpios;\n};\n\nstruct gpio_restart {\n\tstruct gpio_desc *reset_gpio;\n\tu32 active_delay_ms;\n\tu32 inactive_delay_ms;\n\tu32 wait_delay_ms;\n};\n\nstruct gpio_set_config {\n\tu32 gpio;\n\tu32 direction;\n\tu32 polarity;\n\tu32 term_en;\n\tu32 term_pull_up;\n\tu32 state;\n};\n\nstruct gpio_trig_data {\n\tstruct led_classdev *led;\n\tunsigned int desired_brightness;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct gpio_twl4030_priv {\n\tstruct gpio_chip gpio_chip;\n\tstruct mutex mutex;\n\tint irq_base;\n\tunsigned int usage_count;\n\tunsigned int direction;\n\tunsigned int out_state;\n};\n\nstruct gpio_v2_line_config_attribute {\n\tstruct gpio_v2_line_attribute attr;\n\t__u64 mask;\n};\n\nstruct gpio_v2_line_config {\n\t__u64 flags;\n\t__u32 num_attrs;\n\t__u32 padding[5];\n\tstruct gpio_v2_line_config_attribute attrs[10];\n};\n\nstruct gpio_v2_line_event {\n\t__u64 timestamp_ns;\n\t__u32 id;\n\t__u32 offset;\n\t__u32 seqno;\n\t__u32 line_seqno;\n\t__u32 padding[6];\n};\n\nstruct gpio_v2_line_request {\n\t__u32 offsets[64];\n\tchar consumer[32];\n\tstruct gpio_v2_line_config config;\n\t__u32 num_lines;\n\t__u32 event_buffer_size;\n\t__u32 padding[5];\n\t__s32 fd;\n};\n\nstruct gpio_v2_line_values {\n\t__u64 bits;\n\t__u64 mask;\n};\n\nstruct gpiochip_info {\n\tchar name[32];\n\tchar label[32];\n\t__u32 lines;\n};\n\nstruct gpiod_hog {\n\tstruct list_head list;\n\tconst char *chip_label;\n\tu16 chip_hwnum;\n\tconst char *line_name;\n\tlong unsigned int lflags;\n\tint dflags;\n};\n\nstruct gpiod_lookup {\n\tconst char *key;\n\tu16 chip_hwnum;\n\tconst char *con_id;\n\tunsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct gpiod_lookup_table {\n\tstruct list_head list;\n\tconst char *dev_id;\n\tstruct gpiod_lookup table[0];\n};\n\nstruct gpioevent_data {\n\t__u64 timestamp;\n\t__u32 id;\n\tlong: 32;\n};\n\nstruct gpioevent_request {\n\t__u32 lineoffset;\n\t__u32 handleflags;\n\t__u32 eventflags;\n\tchar consumer_label[32];\n\tint fd;\n};\n\nstruct gpiohandle_config {\n\t__u32 flags;\n\t__u8 default_values[64];\n\t__u32 padding[4];\n};\n\nstruct gpiohandle_data {\n\t__u8 values[64];\n};\n\nstruct gpiohandle_request {\n\t__u32 lineoffsets[64];\n\t__u32 flags;\n\t__u8 default_values[64];\n\tchar consumer_label[32];\n\t__u32 lines;\n\tint fd;\n};\n\nstruct gpiolib_seq_priv {\n\tbool newline;\n\tint idx;\n};\n\nstruct gpioline_info {\n\t__u32 line_offset;\n\t__u32 flags;\n\tchar name[32];\n\tchar consumer[32];\n};\n\nstruct gpioline_info_changed {\n\tstruct gpioline_info info;\n\t__u64 timestamp;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct i2c_mux_gpio_platform_data {\n\tint parent;\n\tint base_nr;\n\tconst unsigned int *values;\n\tint n_values;\n\tunsigned int idle;\n\tu32 settle_time;\n};\n\nstruct gpiomux {\n\tstruct i2c_mux_gpio_platform_data data;\n\tint ngpios;\n\tstruct gpio_desc **gpios;\n};\n\nstruct gpmc_bool_timings {\n\tbool cycle2cyclediffcsen;\n\tbool cycle2cyclesamecsen;\n\tbool we_extra_delay;\n\tbool oe_extra_delay;\n\tbool adv_extra_delay;\n\tbool cs_extra_delay;\n\tbool time_para_granularity;\n};\n\nstruct gpmc_cs_config {\n\tu32 config1;\n\tu32 config2;\n\tu32 config3;\n\tu32 config4;\n\tu32 config5;\n\tu32 config6;\n\tu32 config7;\n\tint is_valid;\n};\n\nstruct gpmc_cs_data {\n\tconst char *name;\n\tu32 flags;\n\tstruct resource mem;\n};\n\nstruct omap3_gpmc_regs {\n\tu32 sysconfig;\n\tu32 irqenable;\n\tu32 timeout_ctrl;\n\tu32 config;\n\tu32 prefetch_config1;\n\tu32 prefetch_config2;\n\tu32 prefetch_control;\n\tstruct gpmc_cs_config cs_context[8];\n};\n\nstruct gpmc_waitpin;\n\nstruct gpmc_device {\n\tstruct device *dev;\n\tint irq;\n\tstruct irq_chip irq_chip;\n\tstruct gpio_chip gpio_chip;\n\tstruct notifier_block nb;\n\tstruct omap3_gpmc_regs context;\n\tstruct gpmc_waitpin *waitpins;\n\tint nirqs;\n\tunsigned int is_suspended: 1;\n\tstruct resource *data;\n};\n\nstruct gpmc_device_timings {\n\tu32 t_ceasu;\n\tu32 t_avdasu;\n\tu32 t_avdp_r;\n\tu32 t_avdp_w;\n\tu32 t_aavdh;\n\tu32 t_oeasu;\n\tu32 t_aa;\n\tu32 t_iaa;\n\tu32 t_oe;\n\tu32 t_ce;\n\tu32 t_rd_cycle;\n\tu32 t_cez_r;\n\tu32 t_cez_w;\n\tu32 t_oez;\n\tu32 t_weasu;\n\tu32 t_wpl;\n\tu32 t_wph;\n\tu32 t_wr_cycle;\n\tu32 clk;\n\tu32 t_bacc;\n\tu32 t_ces;\n\tu32 t_avds;\n\tu32 t_avdh;\n\tu32 t_ach;\n\tu32 t_rdyo;\n\tu32 t_ce_rdyz;\n\tu32 t_ce_avd;\n\tu8 cyc_aavdh_oe;\n\tu8 cyc_aavdh_we;\n\tu8 cyc_oe;\n\tu8 cyc_wpl;\n\tu32 cyc_iaa;\n\tbool ce_xdelay;\n\tbool avd_xdelay;\n\tbool oe_xdelay;\n\tbool we_xdelay;\n};\n\nstruct gpmc_nand_ops {\n\tbool (*nand_writebuffer_empty)(void);\n};\n\nstruct gpmc_nand_regs {\n\tvoid *gpmc_nand_command;\n\tvoid *gpmc_nand_address;\n\tvoid *gpmc_nand_data;\n\tvoid *gpmc_prefetch_config1;\n\tvoid *gpmc_prefetch_config2;\n\tvoid *gpmc_prefetch_control;\n\tvoid *gpmc_prefetch_status;\n\tvoid *gpmc_ecc_config;\n\tvoid *gpmc_ecc_control;\n\tvoid *gpmc_ecc_size_config;\n\tvoid *gpmc_ecc1_result;\n\tvoid *gpmc_bch_result0[8];\n\tvoid *gpmc_bch_result1[8];\n\tvoid *gpmc_bch_result2[8];\n\tvoid *gpmc_bch_result3[8];\n\tvoid *gpmc_bch_result4[8];\n\tvoid *gpmc_bch_result5[8];\n\tvoid *gpmc_bch_result6[8];\n};\n\nstruct gpmc_onenand_info {\n\tbool sync_read;\n\tbool sync_write;\n\tint burst_len;\n};\n\nstruct gpmc_settings {\n\tbool burst_wrap;\n\tbool burst_read;\n\tbool burst_write;\n\tbool device_nand;\n\tbool sync_read;\n\tbool sync_write;\n\tbool wait_on_read;\n\tbool wait_on_write;\n\tu32 burst_len;\n\tu32 device_width;\n\tu32 mux_add_data;\n\tu32 wait_pin;\n\tu32 wait_pin_polarity;\n};\n\nstruct gpmc_timings {\n\tu32 sync_clk;\n\tu32 cs_on;\n\tu32 cs_rd_off;\n\tu32 cs_wr_off;\n\tu32 adv_on;\n\tu32 adv_rd_off;\n\tu32 adv_wr_off;\n\tu32 adv_aad_mux_on;\n\tu32 adv_aad_mux_rd_off;\n\tu32 adv_aad_mux_wr_off;\n\tu32 we_on;\n\tu32 we_off;\n\tu32 oe_on;\n\tu32 oe_off;\n\tu32 oe_aad_mux_on;\n\tu32 oe_aad_mux_off;\n\tu32 page_burst_access;\n\tu32 access;\n\tu32 rd_cycle;\n\tu32 wr_cycle;\n\tu32 bus_turnaround;\n\tu32 cycle2cycle_delay;\n\tu32 wait_monitoring;\n\tu32 clk_activation;\n\tu32 wr_access;\n\tu32 wr_data_mux_bus;\n\tstruct gpmc_bool_timings bool_timings;\n};\n\nstruct gpmc_waitpin {\n\tu32 pin;\n\tu32 polarity;\n\tstruct gpio_desc *desc;\n};\n\nstruct gpmi_devdata {\n\tenum gpmi_type type;\n\tint bch_max_ecc_strength;\n\tint max_chain_delay;\n\tconst char * const *clks;\n\tconst int clks_count;\n\tbool support_edo_timing;\n};\n\nstruct resources {\n\tvoid *gpmi_regs;\n\tvoid *bch_regs;\n\tunsigned int dma_low_channel;\n\tunsigned int dma_high_channel;\n\tstruct clk *clock[5];\n};\n\nstruct gpmi_nfc_hardware_timing {\n\tbool must_apply_timings;\n\tlong unsigned int clk_rate;\n\tu32 timing0;\n\tu32 timing1;\n\tu32 ctrl1n;\n};\n\nstruct gpmi_transfer {\n\tu8 cmdbuf[8];\n\tstruct scatterlist sgl;\n\tenum dma_data_direction direction;\n};\n\nstruct gpmi_nand_data {\n\tconst struct gpmi_devdata *devdata;\n\tstruct device *dev;\n\tstruct platform_device *pdev;\n\tstruct resources resources;\n\tstruct gpmi_nfc_hardware_timing hw;\n\tstruct bch_geometry bch_geometry;\n\tstruct completion bch_done;\n\tbool swap_block_mark;\n\tstruct boot_rom_geometry rom_geometry;\n\tstruct nand_controller base;\n\tlong: 32;\n\tstruct nand_chip nand;\n\tstruct gpmi_transfer transfers[8];\n\tint ntransfers;\n\tbool bch;\n\tuint32_t bch_flashlayout0;\n\tuint32_t bch_flashlayout1;\n\tchar *data_buffer_dma;\n\tvoid *auxiliary_virt;\n\tdma_addr_t auxiliary_phys;\n\tvoid *raw_buffer;\n\tstruct dma_chan *dma_chans[8];\n\tstruct completion dma_done;\n};\n\nstruct gpt_rate_tbl {\n\tu16 mscale;\n\tu16 nscale;\n};\n\nstruct host1x_bo_cache {\n\tstruct list_head mappings;\n\tstruct mutex lock;\n};\n\nstruct host1x_client_ops;\n\nstruct host1x_channel;\n\nstruct host1x_client {\n\tstruct list_head list;\n\tstruct device *host;\n\tstruct device *dev;\n\tstruct iommu_group *group;\n\tconst struct host1x_client_ops *ops;\n\tenum host1x_class class;\n\tstruct host1x_channel *channel;\n\tstruct host1x_syncpt **syncpts;\n\tunsigned int num_syncpts;\n\tstruct host1x_client *parent;\n\tunsigned int usecount;\n\tstruct mutex lock;\n\tstruct host1x_bo_cache cache;\n};\n\nstruct tegra_drm;\n\nstruct tegra_drm_client_ops;\n\nstruct tegra_drm_client {\n\tstruct host1x_client base;\n\tstruct list_head list;\n\tstruct tegra_drm *drm;\n\tstruct host1x_channel *shared_channel;\n\tunsigned int version;\n\tconst struct tegra_drm_client_ops *ops;\n};\n\nstruct gr2d_soc;\n\nstruct gr2d {\n\tstruct tegra_drm_client client;\n\tstruct host1x_channel *channel;\n\tstruct clk *clk;\n\tstruct reset_control_bulk_data resets[2];\n\tunsigned int nresets;\n\tconst struct gr2d_soc *soc;\n\tlong unsigned int addr_regs[3];\n};\n\nstruct gr2d_soc {\n\tunsigned int version;\n};\n\nstruct gr3d_soc;\n\nstruct gr3d {\n\tstruct tegra_drm_client client;\n\tstruct host1x_channel *channel;\n\tconst struct gr3d_soc *soc;\n\tstruct clk_bulk_data *clocks;\n\tunsigned int nclocks;\n\tstruct reset_control_bulk_data resets[4];\n\tunsigned int nresets;\n\tstruct dev_pm_domain_list *pd_list;\n\tlong unsigned int addr_regs[117];\n};\n\nstruct gr3d_soc {\n\tunsigned int version;\n\tunsigned int num_clocks;\n\tunsigned int num_resets;\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n};\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tsize_t npins;\n};\n\nstruct group_desc {\n\tstruct pingroup grp;\n\tvoid *data;\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct grp2fp_map {\n\tu16 f_idx;\n\tu16 g_idx;\n};\n\nstruct gsbi_info {\n\tstruct clk *hclk;\n\tu32 mode;\n\tu32 crci;\n\tstruct regmap *tcsr;\n};\n\nstruct rpc_clnt;\n\nstruct rpc_pipe_ops;\n\nstruct gss_alloc_pdo {\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tconst struct rpc_pipe_ops *upcall_ops;\n};\n\nstruct rpcsec_gss_oid {\n\tunsigned int len;\n\tu8 data[32];\n};\n\nstruct gss_api_ops;\n\nstruct pf_desc;\n\nstruct gss_api_mech {\n\tstruct list_head gm_list;\n\tstruct module *gm_owner;\n\tstruct rpcsec_gss_oid gm_oid;\n\tchar *gm_name;\n\tconst struct gss_api_ops *gm_ops;\n\tint gm_pf_num;\n\tstruct pf_desc *gm_pfs;\n\tconst char *gm_upcall_enctypes;\n};\n\nstruct gss_ctx;\n\nstruct xdr_netobj;\n\nstruct gss_api_ops {\n\tint (*gss_import_sec_context)(const void *, size_t, struct gss_ctx *, time64_t *, gfp_t);\n\tu32 (*gss_get_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_verify_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_wrap)(struct gss_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*gss_unwrap)(struct gss_ctx *, int, int, struct xdr_buf *);\n\tvoid (*gss_delete_sec_context)(void *);\n};\n\nstruct rpc_authops;\n\nstruct rpc_cred_cache;\n\nstruct rpc_auth {\n\tunsigned int au_cslack;\n\tunsigned int au_rslack;\n\tunsigned int au_verfsize;\n\tunsigned int au_ralign;\n\tlong unsigned int au_flags;\n\tconst struct rpc_authops *au_ops;\n\trpc_authflavor_t au_flavor;\n\trefcount_t au_count;\n\tstruct rpc_cred_cache *au_credcache;\n};\n\nstruct gss_pipe;\n\nstruct gss_auth {\n\tstruct kref kref;\n\tstruct hlist_node hash;\n\tstruct rpc_auth rpc_auth;\n\tstruct gss_api_mech *mech;\n\tenum rpc_gss_svc service;\n\tstruct rpc_clnt *client;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct gss_pipe *gss_pipe[2];\n\tconst char *target_name;\n};\n\nstruct xdr_netobj {\n\tunsigned int len;\n\tu8 *data;\n};\n\nstruct gss_cl_ctx {\n\trefcount_t count;\n\tenum rpc_gss_proc gc_proc;\n\tu32 gc_seq;\n\tu32 gc_seq_xmit;\n\tspinlock_t gc_seq_lock;\n\tstruct gss_ctx *gc_gss_ctx;\n\tstruct xdr_netobj gc_wire_ctx;\n\tstruct xdr_netobj gc_acceptor;\n\tu32 gc_win;\n\tlong unsigned int gc_expiry;\n\tstruct callback_head gc_rcu;\n};\n\nstruct rpc_credops;\n\nstruct rpc_cred {\n\tstruct hlist_node cr_hash;\n\tstruct list_head cr_lru;\n\tstruct callback_head cr_rcu;\n\tstruct rpc_auth *cr_auth;\n\tconst struct rpc_credops *cr_ops;\n\tlong unsigned int cr_expire;\n\tlong unsigned int cr_flags;\n\trefcount_t cr_count;\n\tconst struct cred *cr_cred;\n};\n\nstruct gss_upcall_msg;\n\nstruct gss_cred {\n\tstruct rpc_cred gc_base;\n\tenum rpc_gss_svc gc_service;\n\tstruct gss_cl_ctx *gc_ctx;\n\tstruct gss_upcall_msg *gc_upcall;\n\tconst char *gc_principal;\n\tlong unsigned int gc_upcall_timestamp;\n};\n\nstruct gss_ctx {\n\tstruct gss_api_mech *mech_type;\n\tvoid *internal_ctx_id;\n\tunsigned int slack;\n\tunsigned int align;\n};\n\nstruct gss_domain {\n\tstruct auth_domain h;\n\tu32 pseudoflavor;\n};\n\nstruct krb5_ctx;\n\nstruct gss_krb5_enctype {\n\tconst u32 etype;\n\tconst u32 ctype;\n\tconst char *name;\n\tconst char *encrypt_name;\n\tconst char *aux_cipher;\n\tconst char *cksum_name;\n\tconst u16 signalg;\n\tconst u16 sealalg;\n\tconst u32 cksumlength;\n\tconst u32 keyed_cksum;\n\tconst u32 keybytes;\n\tconst u32 keylength;\n\tconst u32 Kc_length;\n\tconst u32 Ke_length;\n\tconst u32 Ki_length;\n\tint (*derive_key)(const struct gss_krb5_enctype *, const struct xdr_netobj *, struct xdr_netobj *, const struct xdr_netobj *, gfp_t);\n\tu32 (*encrypt)(struct krb5_ctx *, u32, struct xdr_buf *, struct page **);\n\tu32 (*decrypt)(struct krb5_ctx *, u32, u32, struct xdr_buf *, u32 *, u32 *);\n\tu32 (*get_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*verify_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*wrap)(struct krb5_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*unwrap)(struct krb5_ctx *, int, int, struct xdr_buf *, unsigned int *, unsigned int *);\n};\n\nstruct rpc_pipe_dir_object_ops;\n\nstruct rpc_pipe_dir_object {\n\tstruct list_head pdo_head;\n\tconst struct rpc_pipe_dir_object_ops *pdo_ops;\n\tvoid *pdo_data;\n};\n\nstruct rpc_pipe;\n\nstruct gss_pipe {\n\tstruct rpc_pipe_dir_object pdo;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tstruct kref kref;\n};\n\nstruct rpc_gss_wire_cred {\n\tu32 gc_v;\n\tu32 gc_proc;\n\tu32 gc_seq;\n\tu32 gc_svc;\n\tstruct xdr_netobj gc_ctx;\n};\n\nstruct rsc;\n\nstruct gss_svc_data {\n\tstruct rpc_gss_wire_cred clcred;\n\tu32 gsd_databody_offset;\n\tstruct rsc *rsci;\n\t__be32 gsd_seq_num;\n\tu8 gsd_scratch[40];\n};\n\nstruct gss_svc_seq_data {\n\tu32 sd_max;\n\tlong unsigned int sd_win[4];\n\tspinlock_t sd_lock;\n};\n\nstruct rpc_pipe_msg {\n\tstruct list_head list;\n\tvoid *data;\n\tsize_t len;\n\tsize_t copied;\n\tint errno;\n};\n\nstruct rpc_timer {\n\tstruct list_head list;\n\tlong unsigned int expires;\n\tstruct delayed_work dwork;\n};\n\nstruct rpc_wait_queue {\n\tspinlock_t lock;\n\tstruct list_head tasks[4];\n\tunsigned char maxpriority;\n\tunsigned char priority;\n\tunsigned char nr;\n\tunsigned int qlen;\n\tstruct rpc_timer timer_list;\n\tconst char *name;\n};\n\nstruct gss_upcall_msg {\n\trefcount_t count;\n\tkuid_t uid;\n\tconst char *service_name;\n\tstruct rpc_pipe_msg msg;\n\tstruct list_head list;\n\tstruct gss_auth *auth;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_wait_queue rpc_waitqueue;\n\twait_queue_head_t waitqueue;\n\tstruct gss_cl_ctx *ctx;\n\tchar databuf[256];\n};\n\nstruct gssp_in_token {\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n};\n\nstruct svc_cred {\n\tkuid_t cr_uid;\n\tkgid_t cr_gid;\n\tstruct group_info *cr_group_info;\n\tu32 cr_flavor;\n\tchar *cr_raw_principal;\n\tchar *cr_principal;\n\tchar *cr_targ_princ;\n\tstruct gss_api_mech *cr_gss_mech;\n};\n\nstruct gssp_upcall_data {\n\tstruct xdr_netobj in_handle;\n\tstruct gssp_in_token in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tstruct rpcsec_gss_oid mech_oid;\n\tstruct svc_cred creds;\n\tint found_creds;\n\tint major_status;\n\tint minor_status;\n};\n\ntypedef struct xdr_netobj utf8string;\n\ntypedef struct xdr_netobj gssx_buffer;\n\nstruct gssx_option;\n\nstruct gssx_option_array {\n\tu32 count;\n\tstruct gssx_option *data;\n};\n\nstruct gssx_call_ctx {\n\tutf8string locale;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx;\n\nstruct gssx_cred;\n\nstruct gssx_cb;\n\nstruct gssx_arg_accept_sec_context {\n\tstruct gssx_call_ctx call_ctx;\n\tstruct gssx_ctx *context_handle;\n\tstruct gssx_cred *cred_handle;\n\tstruct gssp_in_token input_token;\n\tstruct gssx_cb *input_cb;\n\tu32 ret_deleg_cred;\n\tstruct gssx_option_array options;\n\tstruct page **pages;\n\tunsigned int npages;\n};\n\nstruct gssx_cb {\n\tu64 initiator_addrtype;\n\tgssx_buffer initiator_address;\n\tu64 acceptor_addrtype;\n\tgssx_buffer acceptor_address;\n\tgssx_buffer application_data;\n};\n\nstruct gssx_name {\n\tgssx_buffer display_name;\n};\n\ntypedef struct gssx_name gssx_name;\n\nstruct gssx_cred_element;\n\nstruct gssx_cred_element_array {\n\tu32 count;\n\tstruct gssx_cred_element *data;\n};\n\nstruct gssx_cred {\n\tgssx_name desired_name;\n\tstruct gssx_cred_element_array elements;\n\tgssx_buffer cred_handle_reference;\n\tu32 needs_release;\n};\n\ntypedef struct xdr_netobj gssx_OID;\n\nstruct gssx_cred_element {\n\tgssx_name MN;\n\tgssx_OID mech;\n\tu32 cred_usage;\n\tlong: 32;\n\tu64 initiator_time_rec;\n\tu64 acceptor_time_rec;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx {\n\tgssx_buffer exported_context_token;\n\tgssx_buffer state;\n\tu32 need_release;\n\tgssx_OID mech;\n\tgssx_name src_name;\n\tgssx_name targ_name;\n\tlong: 32;\n\tu64 lifetime;\n\tu64 ctx_flags;\n\tu32 locally_initiated;\n\tu32 open;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_name_attr {\n\tgssx_buffer attr;\n\tgssx_buffer value;\n\tstruct gssx_option_array extensions;\n};\n\nstruct gssx_name_attr_array {\n\tu32 count;\n\tstruct gssx_name_attr *data;\n};\n\nstruct gssx_option {\n\tgssx_buffer option;\n\tgssx_buffer value;\n};\n\nstruct gssx_status {\n\tu64 major_status;\n\tgssx_OID mech;\n\tu64 minor_status;\n\tutf8string major_status_string;\n\tutf8string minor_status_string;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_res_accept_sec_context {\n\tstruct gssx_status status;\n\tstruct gssx_ctx *context_handle;\n\tgssx_buffer *output_token;\n\tstruct gssx_option_array options;\n};\n\nstruct gt_prescaler_config {\n\tconst char *compatible;\n\tlong unsigned int prescaler;\n};\n\nstruct gxp_timer {\n\tvoid *counter;\n\tvoid *control;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device evt;\n};\n\nstruct gxp_wdt {\n\tvoid *base;\n\tstruct watchdog_device wdd;\n};\n\nunion handle_parts {\n\tdepot_stack_handle_t handle;\n\tstruct {\n\t\tu32 pool_index_plus_1: 17;\n\t\tu32 offset: 10;\n\t\tu32 extra: 5;\n\t};\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct handshake_net {\n\tspinlock_t hn_lock;\n\tint hn_pending;\n\tint hn_pending_max;\n\tstruct list_head hn_requests;\n\tlong unsigned int hn_flags;\n};\n\nstruct handshake_req;\n\nstruct handshake_proto {\n\tint hp_handler_class;\n\tsize_t hp_privsize;\n\tlong unsigned int hp_flags;\n\tint (*hp_accept)(struct handshake_req *, struct genl_info *, int);\n\tvoid (*hp_done)(struct handshake_req *, unsigned int, struct genl_info *);\n\tvoid (*hp_destroy)(struct handshake_req *);\n};\n\nstruct handshake_req {\n\tstruct list_head hr_list;\n\tstruct rhash_head hr_rhash;\n\tlong unsigned int hr_flags;\n\tconst struct handshake_proto *hr_proto;\n\tstruct sock *hr_sk;\n\tvoid (*hr_odestruct)(struct sock *);\n\tchar hr_priv[0];\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hash_prefix {\n\tconst char *name;\n\tconst u8 *data;\n\tsize_t size;\n};\n\nstruct hb_clk {\n\tstruct clk_hw hw;\n\tvoid *reg;\n};\n\nstruct hb_l2_drvdata {\n\tvoid *base;\n\tint sb_irq;\n\tint db_irq;\n};\n\nstruct hb_mc_drvdata {\n\tvoid *mc_err_base;\n\tvoid *mc_int_base;\n};\n\nstruct hb_mc_settings {\n\tint err_offset;\n\tint int_offset;\n};\n\nstruct hc_driver {\n\tconst char *description;\n\tconst char *product_desc;\n\tsize_t hcd_priv_size;\n\tirqreturn_t (*irq)(struct usb_hcd *);\n\tint flags;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*pci_suspend)(struct usb_hcd *, bool);\n\tint (*pci_resume)(struct usb_hcd *, pm_message_t);\n\tint (*pci_poweroff_late)(struct usb_hcd *, bool);\n\tvoid (*stop)(struct usb_hcd *);\n\tvoid (*shutdown)(struct usb_hcd *);\n\tint (*get_frame_number)(struct usb_hcd *);\n\tint (*urb_enqueue)(struct usb_hcd *, struct urb *, gfp_t);\n\tint (*urb_dequeue)(struct usb_hcd *, struct urb *, int);\n\tint (*map_urb_for_dma)(struct usb_hcd *, struct urb *, gfp_t);\n\tvoid (*unmap_urb_for_dma)(struct usb_hcd *, struct urb *);\n\tvoid (*endpoint_disable)(struct usb_hcd *, struct usb_host_endpoint *);\n\tvoid (*endpoint_reset)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*hub_status_data)(struct usb_hcd *, char *);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n\tint (*bus_suspend)(struct usb_hcd *);\n\tint (*bus_resume)(struct usb_hcd *);\n\tint (*start_port_reset)(struct usb_hcd *, unsigned int);\n\tlong unsigned int (*get_resuming_ports)(struct usb_hcd *);\n\tvoid (*relinquish_port)(struct usb_hcd *, int);\n\tint (*port_handed_over)(struct usb_hcd *, int);\n\tvoid (*clear_tt_buffer_complete)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*alloc_dev)(struct usb_hcd *, struct usb_device *);\n\tvoid (*free_dev)(struct usb_hcd *, struct usb_device *);\n\tint (*alloc_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, unsigned int, gfp_t);\n\tint (*free_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, gfp_t);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*address_device)(struct usb_hcd *, struct usb_device *, unsigned int);\n\tint (*enable_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*reset_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_device)(struct usb_hcd *, struct usb_device *);\n\tint (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);\n\tint (*enable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*disable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*find_raw_port_number)(struct usb_hcd *, int);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n\tint (*submit_single_step_set_feature)(struct usb_hcd *, struct urb *, int);\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hdmi_codec_daifmt {\n\tenum {\n\t\tHDMI_I2S = 0,\n\t\tHDMI_RIGHT_J = 1,\n\t\tHDMI_LEFT_J = 2,\n\t\tHDMI_DSP_A = 3,\n\t\tHDMI_DSP_B = 4,\n\t\tHDMI_AC97 = 5,\n\t\tHDMI_SPDIF = 6,\n\t} fmt;\n\tunsigned int bit_clk_inv: 1;\n\tunsigned int frame_clk_inv: 1;\n\tunsigned int bit_clk_provider: 1;\n\tunsigned int frame_clk_provider: 1;\n\tsnd_pcm_format_t bit_fmt;\n};\n\ntypedef void (*hdmi_codec_plugged_cb)(struct device *, bool);\n\nstruct snd_soc_component;\n\nstruct hdmi_codec_ops {\n\tint (*audio_startup)(struct device *, void *);\n\tint (*hw_params)(struct device *, void *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tint (*prepare)(struct device *, void *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*audio_shutdown)(struct device *, void *);\n\tint (*mute_stream)(struct device *, void *, bool, int);\n\tint (*get_eld)(struct device *, void *, uint8_t *, size_t);\n\tint (*get_dai_id)(struct snd_soc_component *, struct device_node *, void *);\n\tint (*hook_plugged_cb)(struct device *, void *, hdmi_codec_plugged_cb, struct device *);\n};\n\nstruct snd_aes_iec958 {\n\tunsigned char status[24];\n\tunsigned char subcode[147];\n\tunsigned char pad;\n\tunsigned char dig_subframe[4];\n};\n\nstruct hdmi_codec_params {\n\tstruct hdmi_audio_infoframe cea;\n\tstruct snd_aes_iec958 iec;\n\tint sample_rate;\n\tint sample_width;\n\tint channels;\n};\n\nstruct hdmi_codec_pdata {\n\tconst struct hdmi_codec_ops *ops;\n\tlong: 32;\n\tu64 i2s_formats;\n\tuint i2s: 1;\n\tuint no_i2s_playback: 1;\n\tuint no_i2s_capture: 1;\n\tuint spdif: 1;\n\tuint no_spdif_playback: 1;\n\tuint no_spdif_capture: 1;\n\tuint no_capture_mute: 1;\n\tint max_i2s_channels;\n\tvoid *data;\n\tlong: 32;\n};\n\nstruct hdr_metadata_infoframe {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} white_point;\n\t__u16 max_display_mastering_luminance;\n\t__u16 min_display_mastering_luminance;\n\t__u16 max_cll;\n\t__u16 max_fall;\n};\n\nstruct hdr_output_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_metadata_infoframe hdmi_metadata_type1;\n\t};\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct heartbeat_trig_data {\n\tstruct led_classdev *led_cdev;\n\tunsigned int phase;\n\tunsigned int period;\n\tstruct timer_list timer;\n\tunsigned int invert;\n};\n\nstruct hfpll_data {\n\tu32 mode_reg;\n\tu32 l_reg;\n\tu32 m_reg;\n\tu32 n_reg;\n\tu32 user_reg;\n\tu32 droop_reg;\n\tu32 config_reg;\n\tu32 status_reg;\n\tu8 lock_bit;\n\tu32 l_val;\n\tu32 droop_val;\n\tu32 config_val;\n\tu32 user_val;\n\tu32 user_vco_mask;\n\tlong unsigned int low_vco_max_rate;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[24];\n};\n\nstruct hisi_clock_data;\n\nstruct hisi_reset_controller;\n\nstruct hi3519_crg_data {\n\tstruct hisi_clock_data *clk_data;\n\tstruct hisi_reset_controller *rstc;\n};\n\nstruct hi3559av100_clk_pll {\n\tstruct clk_hw hw;\n\tu32 id;\n\tvoid *ctrl_reg1;\n\tu8 frac_shift;\n\tu8 frac_width;\n\tu8 postdiv1_shift;\n\tu8 postdiv1_width;\n\tu8 postdiv2_shift;\n\tu8 postdiv2_width;\n\tvoid *ctrl_reg2;\n\tu8 fbdiv_shift;\n\tu8 fbdiv_width;\n\tu8 refdiv_shift;\n\tu8 refdiv_width;\n};\n\nstruct hi3559av100_pll_clock {\n\tu32 id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst u32 ctrl_reg1;\n\tconst u8 frac_shift;\n\tconst u8 frac_width;\n\tconst u8 postdiv1_shift;\n\tconst u8 postdiv1_width;\n\tconst u8 postdiv2_shift;\n\tconst u8 postdiv2_width;\n\tconst u32 ctrl_reg2;\n\tconst u8 fbdiv_shift;\n\tconst u8 fbdiv_width;\n\tconst u8 refdiv_shift;\n\tconst u8 refdiv_width;\n};\n\nstruct hi3660_chan_info {\n\tunsigned int dst_irq;\n\tunsigned int ack_irq;\n};\n\nstruct mbox_client;\n\nstruct mbox_chan {\n\tstruct mbox_controller *mbox;\n\tunsigned int txdone_method;\n\tstruct mbox_client *cl;\n\tstruct completion tx_complete;\n\tvoid *active_req;\n\tunsigned int msg_count;\n\tunsigned int msg_free;\n\tvoid *msg_data[20];\n\tspinlock_t lock;\n\tvoid *con_priv;\n};\n\nstruct hi3660_mbox {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct mbox_chan chan[32];\n\tstruct hi3660_chan_info mchan[32];\n\tstruct mbox_controller controller;\n};\n\nstruct hi3660_reset_controller {\n\tstruct reset_controller_dev rst;\n\tstruct regmap *map;\n};\n\nstruct hi3660_stub_clk {\n\tunsigned int id;\n\tstruct clk_hw hw;\n\tunsigned int cmd;\n\tunsigned int msg[8];\n\tunsigned int rate;\n};\n\nstruct mbox_client {\n\tstruct device *dev;\n\tbool tx_block;\n\tlong unsigned int tx_tout;\n\tbool knows_txdone;\n\tvoid (*rx_callback)(struct mbox_client *, void *);\n\tvoid (*tx_prepare)(struct mbox_client *, void *);\n\tvoid (*tx_done)(struct mbox_client *, void *, int);\n};\n\nstruct hi3660_stub_clk_chan {\n\tstruct mbox_client cl;\n\tstruct mbox_chan *mbox;\n};\n\nstruct hi6220_clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu32 mask;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct hi6220_divider_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu32 mask_bit;\n\tconst char *alias;\n};\n\nstruct hi6220_mbox_chan;\n\nstruct hi6220_mbox {\n\tstruct device *dev;\n\tint irq;\n\tbool tx_irq_mode;\n\tvoid *ipc;\n\tvoid *base;\n\tunsigned int chan_num;\n\tstruct hi6220_mbox_chan *mchan;\n\tvoid *irq_map_chan[32];\n\tstruct mbox_chan *chan;\n\tstruct mbox_controller controller;\n};\n\nstruct hi6220_mbox_chan {\n\tunsigned int dir;\n\tunsigned int dst_irq;\n\tunsigned int ack_irq;\n\tunsigned int slot;\n\tstruct hi6220_mbox *parent;\n};\n\nstruct hi6220_mbox_msg {\n\tunsigned char type;\n\tunsigned char cmd;\n\tunsigned char obj;\n\tunsigned char src;\n\tunsigned char para[4];\n};\n\nunion hi6220_mbox_data {\n\tunsigned int data[8];\n\tstruct hi6220_mbox_msg msg;\n};\n\nstruct hi6220_reset_data {\n\tstruct reset_controller_dev rc_dev;\n\tstruct regmap *regmap;\n};\n\nstruct hi6220_stub_clk {\n\tu32 id;\n\tstruct device *dev;\n\tstruct clk_hw hw;\n\tstruct regmap *dfs_map;\n\tstruct mbox_client cl;\n\tstruct mbox_chan *mbox;\n};\n\nstruct hid_class_descriptor {\n\t__u8 bDescriptorType;\n\t__le16 wDescriptorLength;\n} __attribute__((packed));\n\nstruct hid_collection {\n\tint parent_idx;\n\tunsigned int type;\n\tunsigned int usage;\n\tunsigned int level;\n};\n\nstruct hid_report;\n\nstruct hid_control_fifo {\n\tunsigned char dir;\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_device;\n\nstruct hid_debug_list {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tchar *type;\n\t\t\tconst char *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tchar *ptr;\n\t\t\tconst char *ptr_const;\n\t\t};\n\t\tchar buf[0];\n\t} hid_debug_fifo;\n\tstruct fasync_struct *fasync;\n\tstruct hid_device *hdev;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct hid_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdHID;\n\t__u8 bCountryCode;\n\t__u8 bNumDescriptors;\n\tstruct hid_class_descriptor rpt_desc;\n\tstruct hid_class_descriptor opt_descs[0];\n} __attribute__((packed));\n\nstruct hid_report_enum {\n\tunsigned int numbered;\n\tstruct list_head report_list;\n\tstruct hid_report *report_id_hash[256];\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct hid_driver;\n\nstruct hid_ll_driver;\n\nstruct hid_field;\n\nstruct hid_usage;\n\nstruct hid_device {\n\tconst __u8 *dev_rdesc;\n\tconst __u8 *bpf_rdesc;\n\tconst __u8 *rdesc;\n\tunsigned int dev_rsize;\n\tunsigned int bpf_rsize;\n\tunsigned int rsize;\n\tunsigned int collection_size;\n\tstruct hid_collection *collection;\n\tunsigned int maxcollection;\n\tunsigned int maxapplication;\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\t__u32 version;\n\tenum hid_type type;\n\tunsigned int country;\n\tstruct hid_report_enum report_enum[3];\n\tstruct work_struct led_work;\n\tstruct semaphore driver_input_lock;\n\tlong: 32;\n\tstruct device dev;\n\tstruct hid_driver *driver;\n\tvoid *devres_group_id;\n\tconst struct hid_ll_driver *ll_driver;\n\tstruct mutex ll_open_lock;\n\tunsigned int ll_open_count;\n\tlong unsigned int status;\n\tunsigned int claimed;\n\tunsigned int quirks;\n\tunsigned int initial_quirks;\n\tbool io_started;\n\tstruct list_head inputs;\n\tvoid *hiddev;\n\tvoid *hidraw;\n\tchar name[128];\n\tchar phys[64];\n\tchar uniq[64];\n\tvoid *driver_data;\n\tint (*ff_init)(struct hid_device *);\n\tint (*hiddev_connect)(struct hid_device *, unsigned int);\n\tvoid (*hiddev_disconnect)(struct hid_device *);\n\tvoid (*hiddev_hid_event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*hiddev_report_event)(struct hid_device *, struct hid_report *);\n\tshort unsigned int debug;\n\tstruct dentry *debug_dir;\n\tstruct dentry *debug_rdesc;\n\tstruct dentry *debug_events;\n\tstruct list_head debug_list;\n\tspinlock_t debug_list_lock;\n\twait_queue_head_t debug_wait;\n\tstruct kref ref;\n\tunsigned int id;\n};\n\nstruct hid_device_id {\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hid_report_id;\n\nstruct hid_usage_id;\n\nstruct hid_input;\n\nstruct hid_driver {\n\tconst char *name;\n\tconst struct hid_device_id *id_table;\n\tstruct list_head dyn_list;\n\tspinlock_t dyn_lock;\n\tbool (*match)(struct hid_device *, bool);\n\tint (*probe)(struct hid_device *, const struct hid_device_id *);\n\tvoid (*remove)(struct hid_device *);\n\tconst struct hid_report_id *report_table;\n\tint (*raw_event)(struct hid_device *, struct hid_report *, u8 *, int);\n\tconst struct hid_usage_id *usage_table;\n\tint (*event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*report)(struct hid_device *, struct hid_report *);\n\tconst __u8 * (*report_fixup)(struct hid_device *, __u8 *, unsigned int *);\n\tint (*input_mapping)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_mapped)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_configured)(struct hid_device *, struct hid_input *);\n\tvoid (*feature_mapping)(struct hid_device *, struct hid_field *, struct hid_usage *);\n\tint (*suspend)(struct hid_device *, pm_message_t);\n\tint (*resume)(struct hid_device *);\n\tint (*reset_resume)(struct hid_device *);\n\tvoid (*on_hid_hw_open)(struct hid_device *);\n\tvoid (*on_hid_hw_close)(struct hid_device *);\n\tstruct device_driver driver;\n};\n\nstruct hid_dynid {\n\tstruct list_head list;\n\tstruct hid_device_id id;\n};\n\nstruct hid_field {\n\tunsigned int physical;\n\tunsigned int logical;\n\tunsigned int application;\n\tstruct hid_usage *usage;\n\tunsigned int maxusage;\n\tunsigned int flags;\n\tunsigned int report_offset;\n\tunsigned int report_size;\n\tunsigned int report_count;\n\tunsigned int report_type;\n\t__s32 *value;\n\t__s32 *new_value;\n\t__s32 *usages_priorities;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tbool ignored;\n\tstruct hid_report *report;\n\tunsigned int index;\n\tstruct hid_input *hidinput;\n\t__u16 dpad;\n\tunsigned int slot_idx;\n};\n\nstruct hid_field_entry {\n\tstruct list_head list;\n\tstruct hid_field *field;\n\tunsigned int index;\n\t__s32 priority;\n};\n\nstruct hid_global {\n\tunsigned int usage_page;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tunsigned int report_id;\n\tunsigned int report_size;\n\tunsigned int report_count;\n};\n\nstruct hid_input {\n\tstruct list_head list;\n\tstruct hid_report *report;\n\tstruct input_dev *input;\n\tconst char *name;\n\tstruct list_head reports;\n\tunsigned int application;\n\tbool registered;\n};\n\nstruct hid_item {\n\tunsigned int format;\n\t__u8 size;\n\t__u8 type;\n\t__u8 tag;\n\tunion {\n\t\t__u8 u8;\n\t\t__s8 s8;\n\t\t__u16 u16;\n\t\t__s16 s16;\n\t\t__u32 u32;\n\t\t__s32 s32;\n\t\tconst __u8 *longdata;\n\t} data;\n};\n\nstruct hid_ll_driver {\n\tint (*start)(struct hid_device *);\n\tvoid (*stop)(struct hid_device *);\n\tint (*open)(struct hid_device *);\n\tvoid (*close)(struct hid_device *);\n\tint (*power)(struct hid_device *, int);\n\tint (*parse)(struct hid_device *);\n\tvoid (*request)(struct hid_device *, struct hid_report *, int);\n\tint (*wait)(struct hid_device *);\n\tint (*raw_request)(struct hid_device *, unsigned char, __u8 *, size_t, unsigned char, int);\n\tint (*output_report)(struct hid_device *, __u8 *, size_t);\n\tint (*idle)(struct hid_device *, int, int, int);\n\tbool (*may_wakeup)(struct hid_device *);\n\tunsigned int max_buffer_size;\n};\n\nstruct hid_local {\n\tunsigned int usage[12288];\n\tu8 usage_size[12288];\n\tunsigned int collection_index[12288];\n\tunsigned int usage_index;\n\tunsigned int usage_minimum;\n\tunsigned int delimiter_depth;\n\tunsigned int delimiter_branch;\n};\n\nstruct hid_output_fifo {\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_parser {\n\tstruct hid_global global;\n\tstruct hid_global global_stack[4];\n\tunsigned int global_stack_ptr;\n\tstruct hid_local local;\n\tunsigned int *collection_stack;\n\tunsigned int collection_stack_ptr;\n\tunsigned int collection_stack_size;\n\tstruct hid_device *device;\n\tunsigned int scan_flags;\n};\n\nstruct hid_report {\n\tstruct list_head list;\n\tstruct list_head hidinput_list;\n\tstruct list_head field_entry_list;\n\tunsigned int id;\n\tenum hid_report_type type;\n\tunsigned int application;\n\tstruct hid_field *field[256];\n\tstruct hid_field_entry *field_entries;\n\tunsigned int maxfield;\n\tunsigned int size;\n\tstruct hid_device *device;\n\tbool tool_active;\n\tunsigned int tool;\n};\n\nstruct hid_report_id {\n\t__u32 report_type;\n};\n\nstruct hid_usage {\n\tunsigned int hid;\n\tunsigned int collection_index;\n\tunsigned int usage_index;\n\t__s8 resolution_multiplier;\n\t__s8 wheel_factor;\n\t__u16 code;\n\t__u8 type;\n\t__s16 hat_min;\n\t__s16 hat_max;\n\t__s16 hat_dir;\n\t__s16 wheel_accumulated;\n};\n\nstruct hid_usage_entry {\n\tunsigned int page;\n\tunsigned int usage;\n\tconst char *description;\n};\n\nstruct hid_usage_id {\n\t__u32 usage_hid;\n\t__u32 usage_type;\n\t__u32 usage_code;\n};\n\nstruct hiddev {\n\tint minor;\n\tint exist;\n\tint open;\n\tstruct mutex existancelock;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tbool initialized;\n};\n\nstruct hidraw {\n\tunsigned int minor;\n\tint exist;\n\tint open;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct device *dev;\n\tspinlock_t list_lock;\n\tstruct list_head list;\n};\n\nstruct hip04_irq_data {\n\tvoid *dist_base;\n\tvoid *cpu_base;\n\tstruct irq_domain *domain;\n\tunsigned int nr_irqs;\n};\n\nstruct hisi_clock_data {\n\tstruct clk_onecell_data clk_data;\n\tvoid *base;\n};\n\nstruct hisi_crg_funcs;\n\nstruct hisi_crg_dev {\n\tstruct hisi_clock_data *clk_data;\n\tstruct hisi_reset_controller *rstc;\n\tconst struct hisi_crg_funcs *funcs;\n};\n\nstruct hisi_crg_funcs {\n\tstruct hisi_clock_data * (*register_clks)(struct platform_device *);\n\tvoid (*unregister_clks)(struct platform_device *);\n};\n\nstruct hisi_divider_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tstruct clk_div_table *table;\n\tconst char *alias;\n};\n\nstruct hisi_fixed_factor_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int mult;\n\tlong unsigned int div;\n\tlong unsigned int flags;\n};\n\nstruct hisi_fixed_rate_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int fixed_rate;\n};\n\nstruct hisi_gate_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 bit_idx;\n\tu8 gate_flags;\n\tconst char *alias;\n};\n\nstruct hisi_mmc_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tu32 clken_reg;\n\tu32 clken_bit;\n\tu32 div_reg;\n\tu32 div_off;\n\tu32 div_bits;\n\tu32 drv_reg;\n\tu32 drv_off;\n\tu32 drv_bits;\n\tu32 sam_reg;\n\tu32 sam_off;\n\tu32 sam_bits;\n};\n\nstruct hisi_mux_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 mux_flags;\n\tconst u32 *table;\n\tconst char *alias;\n};\n\nstruct hisi_phase_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_names;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu32 *phase_degrees;\n\tu32 *phase_regvals;\n\tu8 phase_num;\n};\n\nstruct hisi_reset_controller {\n\tspinlock_t lock;\n\tvoid *membase;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct hisi_rng {\n\tvoid *base;\n\tstruct hwrng rng;\n};\n\nstruct hisi_thermal_ops;\n\nstruct hisi_thermal_sensor;\n\nstruct hisi_thermal_data {\n\tconst struct hisi_thermal_ops *ops;\n\tstruct hisi_thermal_sensor *sensor;\n\tstruct platform_device *pdev;\n\tstruct clk *clk;\n\tvoid *regs;\n\tint nr_sensors;\n};\n\nstruct hisi_thermal_ops {\n\tint (*get_temp)(struct hisi_thermal_sensor *);\n\tint (*enable_sensor)(struct hisi_thermal_sensor *);\n\tint (*disable_sensor)(struct hisi_thermal_sensor *);\n\tint (*irq_handler)(struct hisi_thermal_sensor *);\n\tint (*probe)(struct hisi_thermal_data *);\n};\n\nstruct hisi_thermal_sensor {\n\tstruct hisi_thermal_data *data;\n\tstruct thermal_zone_device *tzd;\n\tconst char *irq_name;\n\tuint32_t id;\n\tuint32_t thres_temp;\n};\n\nstruct histb_rng_priv {\n\tstruct hwrng rng;\n\tvoid *base;\n};\n\nstruct hix5hd2_clk_complex {\n\tstruct clk_hw hw;\n\tu32 id;\n\tvoid *ctrl_reg;\n\tu32 ctrl_clk_mask;\n\tu32 ctrl_rst_mask;\n\tvoid *phy_reg;\n\tu32 phy_clk_mask;\n\tu32 phy_rst_mask;\n};\n\nstruct hix5hd2_complex_clock {\n\tconst char *name;\n\tconst char *parent_name;\n\tu32 id;\n\tu32 ctrl_reg;\n\tu32 ctrl_clk_mask;\n\tu32 ctrl_rst_mask;\n\tu32 phy_reg;\n\tu32 phy_clk_mask;\n\tu32 phy_rst_mask;\n\tenum hix5hd2_clk_type type;\n};\n\nstruct hix5hd2_desc {\n\t__le32 buff_addr;\n\t__le32 cmd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct hix5hd2_desc_sw {\n\tstruct hix5hd2_desc *desc;\n\tdma_addr_t phys_addr;\n\tunsigned int count;\n\tunsigned int size;\n};\n\nstruct hix5hd2_priv {\n\tvoid *base;\n\tstruct regmap *peri_ctrl;\n};\n\nstruct sg_desc;\n\nstruct hix5hd2_sg_desc_ring {\n\tstruct sg_desc *desc;\n\tdma_addr_t phys_addr;\n};\n\nstruct hix5hd2_priv___2 {\n\tstruct hix5hd2_desc_sw pool[4];\n\tstruct hix5hd2_sg_desc_ring tx_ring;\n\tvoid *base;\n\tvoid *ctrl_base;\n\tstruct sk_buff *tx_skb[1024];\n\tstruct sk_buff *rx_skb[1024];\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct device_node *phy_node;\n\tphy_interface_t phy_mode;\n\tlong unsigned int hw_cap;\n\tunsigned int speed;\n\tunsigned int duplex;\n\tstruct clk *mac_core_clk;\n\tstruct clk *mac_ifc_clk;\n\tstruct reset_control *mac_core_rst;\n\tstruct reset_control *mac_ifc_rst;\n\tstruct reset_control *phy_rst;\n\tu32 phy_reset_delays[3];\n\tstruct mii_bus *bus;\n\tstruct napi_struct napi;\n\tstruct work_struct tx_timeout_task;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct sha1_block_state {\n\tu32 h[5];\n};\n\nstruct sha1_ctx {\n\tstruct sha1_block_state state;\n\tlong: 32;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_sha1_ctx {\n\tstruct sha1_ctx sha_ctx;\n\tstruct sha1_block_state ostate;\n\tlong: 32;\n};\n\nstruct hmac_sha1_key {\n\tstruct sha1_block_state istate;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct iova {\n\tstruct rb_node node;\n\tlong unsigned int pfn_hi;\n\tlong unsigned int pfn_lo;\n};\n\nstruct iova_rcache;\n\nstruct iova_domain {\n\tspinlock_t iova_rbtree_lock;\n\tstruct rb_root rbroot;\n\tstruct rb_node *cached_node;\n\tstruct rb_node *cached32_node;\n\tlong unsigned int granule;\n\tlong unsigned int start_pfn;\n\tlong unsigned int dma_32bit_pfn;\n\tlong unsigned int max32_alloc_size;\n\tstruct iova anchor;\n\tstruct iova_rcache *rcaches;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct host1x_channel_list {\n\tstruct host1x_channel *channels;\n\tstruct mutex lock;\n\tlong unsigned int *allocated_channels;\n};\n\nstruct host1x_memory_context;\n\nstruct host1x_memory_context_list {\n\tstruct mutex lock;\n\tstruct host1x_memory_context *devs;\n\tunsigned int len;\n};\n\nstruct host1x_info;\n\nstruct host1x_syncpt_base;\n\nstruct host1x_syncpt_ops;\n\nstruct host1x_intr_ops;\n\nstruct host1x_channel_ops;\n\nstruct host1x_cdma_ops;\n\nstruct host1x_pushbuffer_ops;\n\nstruct host1x_debug_ops;\n\nstruct host1x {\n\tconst struct host1x_info *info;\n\tvoid *regs;\n\tvoid *hv_regs;\n\tvoid *common_regs;\n\tint syncpt_irqs[8];\n\tint num_syncpt_irqs;\n\tstruct host1x_syncpt *syncpt;\n\tstruct host1x_syncpt_base *bases;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct reset_control_bulk_data resets[2];\n\tunsigned int nresets;\n\tstruct iommu_group *group;\n\tstruct iommu_domain *domain;\n\tstruct iova_domain iova;\n\tdma_addr_t iova_end;\n\tstruct mutex intr_mutex;\n\tconst struct host1x_syncpt_ops *syncpt_op;\n\tconst struct host1x_intr_ops *intr_op;\n\tconst struct host1x_channel_ops *channel_op;\n\tconst struct host1x_cdma_ops *cdma_op;\n\tconst struct host1x_pushbuffer_ops *cdma_pb_op;\n\tconst struct host1x_debug_ops *debug_op;\n\tstruct host1x_syncpt *nop_sp;\n\tstruct mutex syncpt_mutex;\n\tstruct host1x_channel_list channel_list;\n\tstruct host1x_memory_context_list context_list;\n\tstruct dentry *debugfs;\n\tstruct mutex devices_lock;\n\tstruct list_head devices;\n\tstruct list_head list;\n\tstruct device_dma_parameters dma_parms;\n\tstruct host1x_bo_cache cache;\n};\n\nstruct host1x_bo_mapping {\n\tstruct kref ref;\n\tstruct dma_buf_attachment *attach;\n\tenum dma_data_direction direction;\n\tstruct list_head list;\n\tstruct host1x_bo *bo;\n\tstruct sg_table *sgt;\n\tunsigned int chunks;\n\tstruct device *dev;\n\tdma_addr_t phys;\n\tsize_t size;\n\tstruct host1x_bo_cache *cache;\n\tstruct list_head entry;\n};\n\nstruct host1x_bo_ops {\n\tstruct host1x_bo * (*get)(struct host1x_bo *);\n\tvoid (*put)(struct host1x_bo *);\n\tstruct host1x_bo_mapping * (*pin)(struct device *, struct host1x_bo *, enum dma_data_direction);\n\tvoid (*unpin)(struct host1x_bo_mapping *);\n\tvoid * (*mmap)(struct host1x_bo *);\n\tvoid (*munmap)(struct host1x_bo *, void *);\n};\n\nstruct push_buffer {\n\tvoid *mapped;\n\tdma_addr_t dma;\n\tdma_addr_t phys;\n\tu32 fence;\n\tu32 pos;\n\tu32 size;\n\tu32 alloc_size;\n};\n\nstruct host1x_cdma {\n\tstruct mutex lock;\n\tstruct completion complete;\n\tenum cdma_event event;\n\tunsigned int slots_used;\n\tunsigned int slots_free;\n\tunsigned int first_get;\n\tunsigned int last_pos;\n\tstruct push_buffer push_buffer;\n\tstruct list_head sync_queue;\n\tlong: 32;\n\tstruct buffer_timeout timeout;\n\tbool running;\n\tbool torndown;\n\tstruct work_struct update_work;\n\tlong: 32;\n};\n\nstruct host1x_cdma_ops {\n\tvoid (*start)(struct host1x_cdma *);\n\tvoid (*stop)(struct host1x_cdma *);\n\tvoid (*flush)(struct host1x_cdma *);\n\tint (*timeout_init)(struct host1x_cdma *);\n\tvoid (*timeout_destroy)(struct host1x_cdma *);\n\tvoid (*freeze)(struct host1x_cdma *);\n\tvoid (*resume)(struct host1x_cdma *, u32);\n\tvoid (*timeout_cpu_incr)(struct host1x_cdma *, u32, u32, u32, u32);\n};\n\nstruct host1x_channel {\n\tstruct kref refcount;\n\tunsigned int id;\n\tstruct mutex submitlock;\n\tvoid *regs;\n\tstruct host1x_client *client;\n\tstruct device *dev;\n\tstruct host1x_cdma cdma;\n};\n\nstruct host1x_job;\n\nstruct host1x_channel_ops {\n\tint (*init)(struct host1x_channel *, struct host1x *, unsigned int);\n\tint (*submit)(struct host1x_job *);\n};\n\nstruct host1x_client_ops {\n\tint (*early_init)(struct host1x_client *);\n\tint (*init)(struct host1x_client *);\n\tint (*exit)(struct host1x_client *);\n\tint (*late_exit)(struct host1x_client *);\n\tint (*suspend)(struct host1x_client *);\n\tint (*resume)(struct host1x_client *);\n};\n\nstruct output;\n\nstruct host1x_debug_ops {\n\tvoid (*debug_init)(struct dentry *);\n\tvoid (*show_channel_cdma)(struct host1x *, struct host1x_channel *, struct output *);\n\tvoid (*show_channel_fifo)(struct host1x *, struct host1x_channel *, struct output *);\n\tvoid (*show_mlocks)(struct host1x *, struct output *);\n};\n\nstruct host1x_driver;\n\nstruct host1x_device {\n\tstruct host1x_driver *driver;\n\tstruct list_head list;\n\tlong: 32;\n\tstruct device dev;\n\tstruct mutex subdevs_lock;\n\tstruct list_head subdevs;\n\tstruct list_head active;\n\tstruct mutex clients_lock;\n\tstruct list_head clients;\n\tbool registered;\n\tstruct device_dma_parameters dma_parms;\n};\n\nstruct host1x_driver {\n\tstruct device_driver driver;\n\tconst struct of_device_id *subdevs;\n\tstruct list_head list;\n\tint (*probe)(struct host1x_device *);\n\tvoid (*remove)(struct host1x_device *);\n\tvoid (*shutdown)(struct host1x_device *);\n};\n\nstruct host1x_fence_list {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct host1x_reloc;\n\nstruct host1x_firewall {\n\tstruct host1x_job *job;\n\tstruct device *dev;\n\tunsigned int num_relocs;\n\tstruct host1x_reloc *reloc;\n\tstruct host1x_bo *cmdbuf;\n\tunsigned int offset;\n\tu32 words;\n\tu32 class;\n\tu32 reg;\n\tu32 mask;\n\tu32 count;\n};\n\nstruct host1x_table_desc {\n\tunsigned int base;\n\tunsigned int count;\n};\n\nstruct host1x_sid_entry;\n\nstruct host1x_info {\n\tunsigned int nb_channels;\n\tunsigned int nb_pts;\n\tunsigned int nb_bases;\n\tunsigned int nb_mlocks;\n\tint (*init)(struct host1x *);\n\tunsigned int sync_offset;\n\tu64 dma_mask;\n\tbool has_wide_gather;\n\tbool has_hypervisor;\n\tbool has_common;\n\tunsigned int num_sid_entries;\n\tconst struct host1x_sid_entry *sid_table;\n\tstruct host1x_table_desc streamid_vm_table;\n\tstruct host1x_table_desc classid_vm_table;\n\tstruct host1x_table_desc mmio_vm_table;\n\tbool reserve_vblank_syncpts;\n\tbool skip_reset_assert;\n};\n\nstruct host1x_intr_irq_data {\n\tstruct host1x *host;\n\tu32 offset;\n};\n\nstruct host1x_intr_ops {\n\tint (*init_host_sync)(struct host1x *, u32);\n\tvoid (*set_syncpt_threshold)(struct host1x *, unsigned int, u32);\n\tvoid (*enable_syncpt_intr)(struct host1x *, unsigned int);\n\tvoid (*disable_syncpt_intr)(struct host1x *, unsigned int);\n\tvoid (*disable_all_syncpt_intrs)(struct host1x *);\n\tint (*free_syncpt_irq)(struct host1x *);\n\tirqreturn_t (*isr)(int, void *);\n};\n\nstruct host1x_job_cmd;\n\nstruct host1x_job_unpin_data;\n\nstruct host1x_job {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct host1x_channel *channel;\n\tstruct host1x_client *client;\n\tstruct host1x_job_cmd *cmds;\n\tunsigned int num_cmds;\n\tstruct host1x_reloc *relocs;\n\tunsigned int num_relocs;\n\tstruct host1x_job_unpin_data *unpins;\n\tunsigned int num_unpins;\n\tdma_addr_t *addr_phys;\n\tdma_addr_t *gather_addr_phys;\n\tdma_addr_t *reloc_addr_phys;\n\tstruct host1x_syncpt *syncpt;\n\tu32 syncpt_incrs;\n\tu32 syncpt_end;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tunsigned int timeout;\n\tbool cancelled;\n\tunsigned int first_get;\n\tunsigned int num_slots;\n\tsize_t gather_copy_size;\n\tdma_addr_t gather_copy;\n\tu8 *gather_copy_mapped;\n\tint (*is_addr_reg)(struct device *, u32, u32);\n\tint (*is_valid_class)(u32);\n\tu32 class;\n\tbool serialize;\n\tbool syncpt_recovery;\n\tvoid (*release)(struct host1x_job *);\n\tvoid *user_data;\n\tbool enable_firewall;\n\tstruct host1x_memory_context *memory_context;\n\tu32 engine_fallback_streamid;\n\tu32 engine_streamid_offset;\n};\n\nstruct host1x_job_gather {\n\tunsigned int words;\n\tdma_addr_t base;\n\tstruct host1x_bo *bo;\n\tunsigned int offset;\n\tbool handled;\n};\n\nstruct host1x_job_wait {\n\tu32 id;\n\tu32 threshold;\n\tu32 next_class;\n\tbool relative;\n};\n\nstruct host1x_job_cmd {\n\tbool is_wait;\n\tunion {\n\t\tstruct host1x_job_gather gather;\n\t\tstruct host1x_job_wait wait;\n\t};\n};\n\nstruct host1x_job_unpin_data {\n\tstruct host1x_bo_mapping *map;\n};\n\nstruct host1x_memory_context {\n\tstruct host1x *host;\n\trefcount_t ref;\n\tstruct pid *owner;\n\tstruct device_dma_parameters dma_parms;\n\tstruct device dev;\n\tu64 dma_mask;\n\tu32 stream_id;\n\tlong: 32;\n};\n\nstruct host1x_pushbuffer_ops {\n\tvoid (*init)(struct push_buffer *);\n};\n\nstruct host1x_reloc {\n\tstruct {\n\t\tstruct host1x_bo *bo;\n\t\tlong unsigned int offset;\n\t} cmdbuf;\n\tstruct {\n\t\tstruct host1x_bo *bo;\n\t\tlong unsigned int offset;\n\t} target;\n\tlong unsigned int shift;\n\tlong unsigned int flags;\n};\n\nstruct host1x_sid_entry {\n\tunsigned int base;\n\tunsigned int offset;\n\tunsigned int limit;\n};\n\nstruct host1x_subdev {\n\tstruct host1x_client *client;\n\tstruct device_node *np;\n\tstruct list_head list;\n};\n\nstruct host1x_syncpt {\n\tstruct kref ref;\n\tunsigned int id;\n\tatomic_t min_val;\n\tatomic_t max_val;\n\tu32 base_val;\n\tconst char *name;\n\tbool client_managed;\n\tstruct host1x *host;\n\tstruct host1x_syncpt_base *base;\n\tstruct host1x_fence_list fences;\n\tbool locked;\n};\n\nstruct host1x_syncpt_base {\n\tunsigned int id;\n\tbool requested;\n};\n\nstruct host1x_syncpt_fence {\n\tstruct dma_fence base;\n\tatomic_t signaling;\n\tstruct host1x_syncpt *sp;\n\tu32 threshold;\n\tbool timeout;\n\tstruct delayed_work timeout_work;\n\tstruct list_head list;\n\tlong: 32;\n};\n\nstruct host1x_syncpt_ops {\n\tvoid (*restore)(struct host1x_syncpt *);\n\tvoid (*restore_wait_base)(struct host1x_syncpt *);\n\tvoid (*load_wait_base)(struct host1x_syncpt *);\n\tu32 (*load)(struct host1x_syncpt *);\n\tint (*cpu_incr)(struct host1x_syncpt *);\n\tvoid (*assign_to_channel)(struct host1x_syncpt *, struct host1x_channel *);\n\tvoid (*enable_protection)(struct host1x *);\n};\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct hprobe {\n\tenum hprobe_state state;\n\tint srcu_idx;\n\tstruct uprobe *uprobe;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tlong: 32;\n\tktime_t offset;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tlong: 32;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tlong: 32;\n\tstruct hrtimer_clock_base clock_base[8];\n\tcall_single_data_t csd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n\tlong: 32;\n};\n\nstruct hs_bus_speed_cfg {\n\tuint8_t hs_hold;\n\tuint8_t hs_high_phase;\n\tuint8_t hs_setup;\n\tuint8_t prescale;\n\tuint8_t time_p;\n\tuint8_t no_div;\n\tuint8_t time_div;\n};\n\nstruct hspi_priv {\n\tvoid *addr;\n\tstruct spi_controller *ctlr;\n\tstruct device *dev;\n\tstruct clk *clk;\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tchar key[0];\n};\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct pci_ops;\n\nstruct pci_sys_data;\n\nstruct hw_pci {\n\tstruct pci_ops *ops;\n\tint nr_controllers;\n\tvoid **private_data;\n\tint (*setup)(int, struct pci_sys_data *);\n\tint (*scan)(int, struct pci_host_bridge *);\n\tvoid (*preinit)(void);\n\tvoid (*postinit)(void);\n\tu8 (*swizzle)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n\tlong: 32;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 config1;\n\t\t\tu64 last_tag;\n\t\t\tu64 dyn_constraint;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tu64 aux_config;\n\t\t\tunsigned int aux_paused;\n\t\t\tlong: 32;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tstruct arch_hw_breakpoint info;\n\t\t\tstruct rhlist_head bp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tlong: 32;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tunion {\n\t\tstruct {\n\t\t\tu64 last_period;\n\t\t\tlocal64_t period_left;\n\t\t};\n\t\tstruct {\n\t\t\tu64 saved_metric;\n\t\t\tu64 saved_slots;\n\t\t};\n\t};\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hw_prober_entry {\n\tconst char *compatible;\n\tint (*prober)(struct device *, const void *);\n\tconst void *data;\n};\n\nstruct hwbm_pool {\n\tint size;\n\tint frag_size;\n\tint buf_num;\n\tint (*construct)(struct hwbm_pool *, void *);\n\tstruct mutex buf_lock;\n\tvoid *priv;\n};\n\nstruct hwerr_info {\n\tatomic_t count;\n\tlong: 32;\n\ttime64_t timestamp;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n\tlong: 32;\n};\n\nstruct hwmon_attr {\n\tstruct device_attribute dev_attr;\n\tstruct e1000_hw___2 *hw;\n\tstruct e1000_thermal_diode_data *sensor;\n\tchar name[12];\n};\n\nstruct hwmon_buff {\n\tstruct attribute_group group;\n\tconst struct attribute_group *groups[2];\n\tstruct attribute *attrs[13];\n\tstruct hwmon_attr hwmon_list[12];\n\tunsigned int n_hwmon;\n};\n\nstruct hwmon_channel_info {\n\tenum hwmon_sensor_types type;\n\tconst u32 *config;\n};\n\nstruct hwmon_ops;\n\nstruct hwmon_chip_info {\n\tconst struct hwmon_ops *ops;\n\tconst struct hwmon_channel_info * const *info;\n};\n\nstruct hwmon_device {\n\tconst char *name;\n\tconst char *label;\n\tstruct device dev;\n\tconst struct hwmon_chip_info *chip;\n\tstruct mutex lock;\n\tstruct list_head tzdata;\n\tstruct attribute_group group;\n\tconst struct attribute_group **groups;\n\tlong: 32;\n};\n\nstruct hwmon_device_attribute {\n\tstruct device_attribute dev_attr;\n\tconst struct hwmon_ops *ops;\n\tenum hwmon_sensor_types type;\n\tu32 attr;\n\tint index;\n\tchar name[32];\n};\n\nstruct hwmon_ops {\n\tumode_t visible;\n\tumode_t (*is_visible)(const void *, enum hwmon_sensor_types, u32, int);\n\tint (*read)(struct device *, enum hwmon_sensor_types, u32, int, long int *);\n\tint (*read_string)(struct device *, enum hwmon_sensor_types, u32, int, const char **);\n\tint (*write)(struct device *, enum hwmon_sensor_types, u32, int, long int);\n};\n\nstruct hwmon_thermal_data {\n\tstruct list_head node;\n\tstruct device *dev;\n\tint index;\n\tstruct thermal_zone_device *tzd;\n};\n\nstruct hwmon_type_attr_list {\n\tconst u32 *attrs;\n\tsize_t n_attrs;\n};\n\nstruct hwspinlock_device;\n\nstruct hwspinlock {\n\tstruct hwspinlock_device *bank;\n\tspinlock_t lock;\n\tvoid *priv;\n};\n\nstruct hwspinlock_ops;\n\nstruct hwspinlock_device {\n\tstruct device *dev;\n\tconst struct hwspinlock_ops *ops;\n\tint base_id;\n\tint num_locks;\n\tstruct hwspinlock lock[0];\n};\n\nstruct hwspinlock_ops {\n\tint (*trylock)(struct hwspinlock *);\n\tvoid (*unlock)(struct hwspinlock *);\n\tint (*bust)(struct hwspinlock *, unsigned int);\n\tvoid (*relax)(struct hwspinlock *);\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct hynix_read_retry;\n\nstruct hynix_nand {\n\tconst struct hynix_read_retry *read_retry;\n};\n\nstruct hynix_read_retry {\n\tint nregs;\n\tconst u8 *regs;\n\tu8 values[0];\n};\n\nstruct hynix_read_retry_otp {\n\tint nregs;\n\tconst u8 *regs;\n\tconst u8 *values;\n\tint page;\n\tint size;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n\tlong: 32;\n};\n\nstruct i2c_algo_bit_data {\n\tvoid *data;\n\tvoid (*setsda)(void *, int);\n\tvoid (*setscl)(void *, int);\n\tint (*getsda)(void *);\n\tint (*getscl)(void *);\n\tint (*pre_xfer)(struct i2c_adapter *);\n\tvoid (*post_xfer)(struct i2c_adapter *);\n\tint udelay;\n\tint timeout;\n\tbool can_do_atomic;\n};\n\nunion i2c_smbus_data;\n\nstruct i2c_algorithm {\n\tunion {\n\t\tint (*xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tunion {\n\t\tint (*xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n\tunion {\n\t\tint (*reg_target)(struct i2c_client *);\n\t\tint (*reg_slave)(struct i2c_client *);\n\t};\n\tunion {\n\t\tint (*unreg_target)(struct i2c_client *);\n\t\tint (*unreg_slave)(struct i2c_client *);\n\t};\n};\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\ntypedef int (*i2c_slave_cb_t)(struct i2c_client *, enum i2c_slave_event, u8 *);\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tlong: 32;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n\ti2c_slave_cb_t slave_cb;\n\tvoid *devres_group_id;\n\tstruct dentry *debugfs;\n\tlong: 32;\n};\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct of_changeset {\n\tstruct list_head entries;\n};\n\nstruct i2c_demux_pinctrl_chan {\n\tstruct device_node *parent_np;\n\tstruct i2c_adapter *parent_adap;\n\tstruct of_changeset chgset;\n};\n\nstruct i2c_demux_pinctrl_priv {\n\tint cur_chan;\n\tint num_chan;\n\tstruct device *dev;\n\tconst char *bus_name;\n\tstruct i2c_adapter cur_adap;\n\tstruct i2c_algorithm algo;\n\tstruct i2c_demux_pinctrl_chan chan[0];\n\tlong: 32;\n};\n\nstruct i2c_dev {\n\tstruct list_head list;\n\tstruct i2c_adapter *adap;\n\tlong: 32;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tlong: 32;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *);\n\tvoid (*remove)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tu32 flags;\n};\n\nstruct i2c_dw_semaphore_callbacks {\n\tint (*probe)(struct dw_i2c_dev *);\n};\n\nstruct i2c_init_data {\n\tu8 loadbits;\n\tu8 load;\n\tu8 hsscll_38_4;\n\tu8 hsscll_26;\n\tu8 hsscll_19_2;\n\tu8 hsscll_16_8;\n\tu8 hsscll_12;\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nstruct i2c_mux_core {\n\tstruct i2c_adapter *parent;\n\tstruct device *dev;\n\tunsigned int mux_locked: 1;\n\tunsigned int arbitrator: 1;\n\tunsigned int gate: 1;\n\tvoid *priv;\n\tint (*select)(struct i2c_mux_core *, u32);\n\tint (*deselect)(struct i2c_mux_core *, u32);\n\tint num_adapters;\n\tint max_adapters;\n\tstruct i2c_adapter *adapter[0];\n};\n\nstruct i2c_mux_pinctrl {\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *states[0];\n};\n\nstruct i2c_mux_priv {\n\tstruct i2c_adapter adap;\n\tstruct i2c_algorithm algo;\n\tstruct i2c_mux_core *muxc;\n\tu32 chan_id;\n\tlong: 32;\n};\n\nstruct i2c_nmk_client {\n\tshort unsigned int slave_adr;\n\tlong unsigned int count;\n\tunsigned char *buffer;\n\tlong unsigned int xfer_bytes;\n\tenum i2c_operation operation;\n};\n\nstruct i2c_of_probe_ops;\n\nstruct i2c_of_probe_cfg {\n\tconst struct i2c_of_probe_ops *ops;\n\tconst char *type;\n};\n\nstruct i2c_of_probe_ops {\n\tint (*enable)(struct device *, struct device_node *, void *);\n\tvoid (*cleanup_early)(struct device *, void *);\n\tvoid (*cleanup)(struct device *, void *);\n};\n\nstruct i2c_of_probe_simple_ctx {\n\tconst struct i2c_of_probe_simple_opts *opts;\n\tstruct regulator *supply;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct i2c_of_probe_simple_opts {\n\tconst char *res_node_compatible;\n\tconst char *supply_name;\n\tconst char *gpio_name;\n\tunsigned int post_power_on_delay_ms;\n\tunsigned int post_gpio_config_delay_ms;\n\tbool gpio_assert_to_enable;\n};\n\nstruct i2c_rdwr_ioctl_data {\n\tstruct i2c_msg *msgs;\n\t__u32 nmsgs;\n};\n\nstruct i2c_slave_host_notify_status {\n\tu8 index;\n\tu8 addr;\n};\n\nstruct i2c_smbus_alert {\n\tstruct work_struct alert;\n\tstruct i2c_client *ara;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct i2c_smbus_ioctl_data {\n\t__u8 read_write;\n\t__u8 command;\n\t__u32 size;\n\tunion i2c_smbus_data *data;\n};\n\nstruct i2c_spec_values {\n\tlong unsigned int min_hold_start_ns;\n\tlong unsigned int min_low_ns;\n\tlong unsigned int min_high_ns;\n\tlong unsigned int min_setup_start_ns;\n\tlong unsigned int max_data_hold_ns;\n\tlong unsigned int min_data_setup_ns;\n\tlong unsigned int min_setup_stop_ns;\n\tlong unsigned int min_hold_buffer_ns;\n};\n\nstruct i2c_vendor_data {\n\tbool has_mtdws;\n\tu32 fifodepth;\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n\tlong: 32;\n};\n\nstruct ib_pd;\n\nstruct ib_uobject;\n\nstruct ib_gid_attr;\n\nstruct ib_ah {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tconst struct ib_gid_attr *sgid_attr;\n\tenum rdma_ah_attr_type type;\n};\n\nstruct ib_ah_attr {\n\tu16 dlid;\n\tu8 src_path_bits;\n};\n\nstruct ib_core_device {\n\tstruct device dev;\n\tpossible_net_t rdma_net;\n\tstruct kobject *ports_kobj;\n\tstruct list_head port_list;\n\tstruct ib_device *owner;\n\tlong: 32;\n};\n\nstruct ib_counters {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_counters_read_attr {\n\tu64 *counters_buff;\n\tu32 ncounters;\n\tu32 flags;\n};\n\nstruct ib_ucq_object;\n\nstruct ib_cq;\n\ntypedef void (*ib_comp_handler)(struct ib_cq *, void *);\n\nstruct irq_poll;\n\ntypedef int irq_poll_fn(struct irq_poll *, int);\n\nstruct irq_poll {\n\tstruct list_head list;\n\tlong unsigned int state;\n\tint weight;\n\tirq_poll_fn *poll;\n};\n\nstruct rdma_restrack_entry {\n\tbool valid;\n\tu8 no_track: 1;\n\tstruct kref kref;\n\tstruct completion comp;\n\tstruct task_struct *task;\n\tconst char *kern_name;\n\tenum rdma_restrack_type type;\n\tbool user;\n\tu32 id;\n};\n\nstruct ib_event;\n\nstruct ib_wc;\n\nstruct ib_cq {\n\tstruct ib_device *device;\n\tstruct ib_ucq_object *uobject;\n\tib_comp_handler comp_handler;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *cq_context;\n\tint cqe;\n\tunsigned int cqe_used;\n\tatomic_t usecnt;\n\tenum ib_poll_context poll_ctx;\n\tstruct ib_wc *wc;\n\tstruct list_head pool_entry;\n\tunion {\n\t\tstruct irq_poll iop;\n\t\tstruct work_struct work;\n\t};\n\tstruct workqueue_struct *comp_wq;\n\tstruct dim *dim;\n\tlong: 32;\n\tktime_t timestamp;\n\tu8 interrupt: 1;\n\tu8 shared: 1;\n\tunsigned int comp_vector;\n\tstruct rdma_restrack_entry res;\n\tlong: 32;\n};\n\nstruct ib_cq_caps {\n\tu16 max_cq_moderation_count;\n\tu16 max_cq_moderation_period;\n};\n\nstruct ib_cq_init_attr {\n\tunsigned int cqe;\n\tu32 comp_vector;\n\tu32 flags;\n};\n\nstruct ib_cqe {\n\tvoid (*done)(struct ib_cq *, struct ib_wc *);\n};\n\nstruct ib_mad;\n\nstruct uverbs_attr_bundle;\n\nstruct ib_umem;\n\nstruct rdma_cm_id;\n\nstruct iw_cm_id;\n\nstruct iw_cm_conn_param;\n\nstruct ib_uverbs_file;\n\nstruct ib_qp;\n\nstruct ib_send_wr;\n\nstruct ib_recv_wr;\n\nstruct ib_srq;\n\nstruct ib_grh;\n\nstruct ib_device_attr;\n\nstruct ib_udata;\n\nstruct ib_device_modify;\n\nstruct ib_port_attr;\n\nstruct ib_port_modify;\n\nstruct ib_port_immutable;\n\nstruct rdma_netdev_alloc_params;\n\nunion ib_gid;\n\nstruct ib_ucontext;\n\nstruct rdma_user_mmap_entry;\n\nstruct phys_vec;\n\nstruct rdma_ah_init_attr;\n\nstruct rdma_ah_attr;\n\nstruct ib_srq_init_attr;\n\nstruct ib_srq_attr;\n\nstruct ib_qp_init_attr;\n\nstruct ib_qp_attr;\n\nstruct ib_mr;\n\nstruct ib_dmah;\n\nstruct ib_sge;\n\nstruct ib_mr_status;\n\nstruct ib_mw;\n\nstruct ib_xrcd;\n\nstruct ib_flow;\n\nstruct ib_flow_attr;\n\nstruct ib_flow_action;\n\nstruct ifla_vf_info;\n\nstruct ifla_vf_stats;\n\nstruct ifla_vf_guid;\n\nstruct ib_wq;\n\nstruct ib_wq_init_attr;\n\nstruct ib_wq_attr;\n\nstruct ib_rwq_ind_table;\n\nstruct ib_rwq_ind_table_init_attr;\n\nstruct ib_dm;\n\nstruct ib_dm_alloc_attr;\n\nstruct ib_dm_mr_attr;\n\nstruct rdma_hw_stats;\n\nstruct rdma_counter;\n\nstruct ib_device_ops {\n\tstruct module *owner;\n\tenum rdma_driver_id driver_id;\n\tu32 uverbs_abi_ver;\n\tunsigned int uverbs_no_driver_id_binding: 1;\n\tconst struct attribute_group *device_group;\n\tconst struct attribute_group **port_groups;\n\tint (*post_send)(struct ib_qp *, const struct ib_send_wr *, const struct ib_send_wr **);\n\tint (*post_recv)(struct ib_qp *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tvoid (*drain_rq)(struct ib_qp *);\n\tvoid (*drain_sq)(struct ib_qp *);\n\tint (*poll_cq)(struct ib_cq *, int, struct ib_wc *);\n\tint (*peek_cq)(struct ib_cq *, int);\n\tint (*req_notify_cq)(struct ib_cq *, enum ib_cq_notify_flags);\n\tint (*post_srq_recv)(struct ib_srq *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tint (*process_mad)(struct ib_device *, int, u32, const struct ib_wc *, const struct ib_grh *, const struct ib_mad *, struct ib_mad *, size_t *, u16 *);\n\tint (*query_device)(struct ib_device *, struct ib_device_attr *, struct ib_udata *);\n\tint (*modify_device)(struct ib_device *, int, struct ib_device_modify *);\n\tvoid (*get_dev_fw_str)(struct ib_device *, char *);\n\tconst struct cpumask * (*get_vector_affinity)(struct ib_device *, int);\n\tint (*query_port)(struct ib_device *, u32, struct ib_port_attr *);\n\tint (*query_port_speed)(struct ib_device *, u32, u64 *);\n\tint (*modify_port)(struct ib_device *, u32, int, struct ib_port_modify *);\n\tint (*get_port_immutable)(struct ib_device *, u32, struct ib_port_immutable *);\n\tenum rdma_link_layer (*get_link_layer)(struct ib_device *, u32);\n\tstruct net_device * (*get_netdev)(struct ib_device *, u32);\n\tstruct net_device * (*alloc_rdma_netdev)(struct ib_device *, u32, enum rdma_netdev_t, const char *, unsigned char, void (*)(struct net_device *));\n\tint (*rdma_netdev_get_params)(struct ib_device *, u32, enum rdma_netdev_t, struct rdma_netdev_alloc_params *);\n\tint (*query_gid)(struct ib_device *, u32, int, union ib_gid *);\n\tint (*add_gid)(const struct ib_gid_attr *, void **);\n\tint (*del_gid)(const struct ib_gid_attr *, void **);\n\tint (*query_pkey)(struct ib_device *, u32, u16, u16 *);\n\tint (*alloc_ucontext)(struct ib_ucontext *, struct ib_udata *);\n\tvoid (*dealloc_ucontext)(struct ib_ucontext *);\n\tint (*mmap)(struct ib_ucontext *, struct vm_area_struct *);\n\tvoid (*mmap_free)(struct rdma_user_mmap_entry *);\n\tint (*mmap_get_pfns)(struct rdma_user_mmap_entry *, struct phys_vec *, struct p2pdma_provider **);\n\tstruct rdma_user_mmap_entry * (*pgoff_to_mmap_entry)(struct ib_ucontext *, off_t);\n\tvoid (*disassociate_ucontext)(struct ib_ucontext *);\n\tint (*alloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*dealloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*create_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*create_user_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*modify_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*query_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*destroy_ah)(struct ib_ah *, u32);\n\tint (*create_srq)(struct ib_srq *, struct ib_srq_init_attr *, struct ib_udata *);\n\tint (*modify_srq)(struct ib_srq *, struct ib_srq_attr *, enum ib_srq_attr_mask, struct ib_udata *);\n\tint (*query_srq)(struct ib_srq *, struct ib_srq_attr *);\n\tint (*destroy_srq)(struct ib_srq *, struct ib_udata *);\n\tint (*create_qp)(struct ib_qp *, struct ib_qp_init_attr *, struct ib_udata *);\n\tint (*modify_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);\n\tint (*query_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_qp_init_attr *);\n\tint (*destroy_qp)(struct ib_qp *, struct ib_udata *);\n\tint (*create_cq)(struct ib_cq *, const struct ib_cq_init_attr *, struct uverbs_attr_bundle *);\n\tint (*create_cq_umem)(struct ib_cq *, const struct ib_cq_init_attr *, struct ib_umem *, struct uverbs_attr_bundle *);\n\tint (*modify_cq)(struct ib_cq *, u16, u16);\n\tint (*destroy_cq)(struct ib_cq *, struct ib_udata *);\n\tint (*resize_cq)(struct ib_cq *, int, struct ib_udata *);\n\tint (*pre_destroy_cq)(struct ib_cq *);\n\tvoid (*post_destroy_cq)(struct ib_cq *);\n\tstruct ib_mr * (*get_dma_mr)(struct ib_pd *, int);\n\tstruct ib_mr * (*reg_user_mr)(struct ib_pd *, u64, u64, u64, int, struct ib_dmah *, struct ib_udata *);\n\tstruct ib_mr * (*reg_user_mr_dmabuf)(struct ib_pd *, u64, u64, u64, int, int, struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*rereg_user_mr)(struct ib_mr *, int, u64, u64, u64, int, struct ib_pd *, struct ib_udata *);\n\tint (*dereg_mr)(struct ib_mr *, struct ib_udata *);\n\tstruct ib_mr * (*alloc_mr)(struct ib_pd *, enum ib_mr_type, u32);\n\tstruct ib_mr * (*alloc_mr_integrity)(struct ib_pd *, u32, u32);\n\tint (*advise_mr)(struct ib_pd *, enum ib_uverbs_advise_mr_advice, u32, struct ib_sge *, u32, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg)(struct ib_mr *, struct scatterlist *, int, unsigned int *);\n\tint (*check_mr_status)(struct ib_mr *, u32, struct ib_mr_status *);\n\tint (*alloc_mw)(struct ib_mw *, struct ib_udata *);\n\tint (*dealloc_mw)(struct ib_mw *);\n\tint (*attach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*detach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*alloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tint (*dealloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tstruct ib_flow * (*create_flow)(struct ib_qp *, struct ib_flow_attr *, struct ib_udata *);\n\tint (*destroy_flow)(struct ib_flow *);\n\tint (*destroy_flow_action)(struct ib_flow_action *);\n\tint (*set_vf_link_state)(struct ib_device *, int, u32, int);\n\tint (*get_vf_config)(struct ib_device *, int, u32, struct ifla_vf_info *);\n\tint (*get_vf_stats)(struct ib_device *, int, u32, struct ifla_vf_stats *);\n\tint (*get_vf_guid)(struct ib_device *, int, u32, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*set_vf_guid)(struct ib_device *, int, u32, u64, int);\n\tstruct ib_wq * (*create_wq)(struct ib_pd *, struct ib_wq_init_attr *, struct ib_udata *);\n\tint (*destroy_wq)(struct ib_wq *, struct ib_udata *);\n\tint (*modify_wq)(struct ib_wq *, struct ib_wq_attr *, u32, struct ib_udata *);\n\tint (*create_rwq_ind_table)(struct ib_rwq_ind_table *, struct ib_rwq_ind_table_init_attr *, struct ib_udata *);\n\tint (*destroy_rwq_ind_table)(struct ib_rwq_ind_table *);\n\tstruct ib_dm * (*alloc_dm)(struct ib_device *, struct ib_ucontext *, struct ib_dm_alloc_attr *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dm)(struct ib_dm *, struct uverbs_attr_bundle *);\n\tint (*alloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*reg_dm_mr)(struct ib_pd *, struct ib_dm *, struct ib_dm_mr_attr *, struct uverbs_attr_bundle *);\n\tint (*create_counters)(struct ib_counters *, struct uverbs_attr_bundle *);\n\tint (*destroy_counters)(struct ib_counters *);\n\tint (*read_counters)(struct ib_counters *, struct ib_counters_read_attr *, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg_pi)(struct ib_mr *, struct scatterlist *, int, unsigned int *, struct scatterlist *, int, unsigned int *);\n\tstruct rdma_hw_stats * (*alloc_hw_device_stats)(struct ib_device *);\n\tstruct rdma_hw_stats * (*alloc_hw_port_stats)(struct ib_device *, u32);\n\tint (*get_hw_stats)(struct ib_device *, struct rdma_hw_stats *, u32, int);\n\tint (*modify_hw_stat)(struct ib_device *, u32, unsigned int, bool);\n\tint (*fill_res_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_mr_entry_raw)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_cq_entry)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_cq_entry_raw)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_qp_entry)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_qp_entry_raw)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_cm_id_entry)(struct sk_buff *, struct rdma_cm_id *);\n\tint (*fill_res_srq_entry)(struct sk_buff *, struct ib_srq *);\n\tint (*fill_res_srq_entry_raw)(struct sk_buff *, struct ib_srq *);\n\tint (*enable_driver)(struct ib_device *);\n\tvoid (*dealloc_driver)(struct ib_device *);\n\tvoid (*iw_add_ref)(struct ib_qp *);\n\tvoid (*iw_rem_ref)(struct ib_qp *);\n\tstruct ib_qp * (*iw_get_qp)(struct ib_device *, int);\n\tint (*iw_connect)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_accept)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_reject)(struct iw_cm_id *, const void *, u8);\n\tint (*iw_create_listen)(struct iw_cm_id *, int);\n\tint (*iw_destroy_listen)(struct iw_cm_id *);\n\tint (*counter_bind_qp)(struct rdma_counter *, struct ib_qp *, u32);\n\tint (*counter_unbind_qp)(struct ib_qp *, u32);\n\tint (*counter_dealloc)(struct rdma_counter *);\n\tstruct rdma_hw_stats * (*counter_alloc_stats)(struct rdma_counter *);\n\tint (*counter_update_stats)(struct rdma_counter *);\n\tvoid (*counter_init)(struct rdma_counter *);\n\tint (*fill_stat_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*query_ucontext)(struct ib_ucontext *, struct uverbs_attr_bundle *);\n\tint (*get_numa_node)(struct ib_device *);\n\tstruct ib_device * (*add_sub_dev)(struct ib_device *, enum rdma_nl_dev_type, const char *);\n\tvoid (*del_sub_dev)(struct ib_device *);\n\tvoid (*ufile_hw_cleanup)(struct ib_uverbs_file *);\n\tvoid (*report_port_event)(struct ib_device *, struct net_device *, long unsigned int);\n\tsize_t size_ib_ah;\n\tsize_t size_ib_counters;\n\tsize_t size_ib_cq;\n\tsize_t size_ib_dmah;\n\tsize_t size_ib_mw;\n\tsize_t size_ib_pd;\n\tsize_t size_ib_qp;\n\tsize_t size_ib_rwq_ind_table;\n\tsize_t size_ib_srq;\n\tsize_t size_ib_ucontext;\n\tsize_t size_ib_xrcd;\n\tsize_t size_rdma_counter;\n};\n\nstruct ib_odp_caps {\n\tuint64_t general_caps;\n\tstruct {\n\t\tuint32_t rc_odp_caps;\n\t\tuint32_t uc_odp_caps;\n\t\tuint32_t ud_odp_caps;\n\t\tuint32_t xrc_odp_caps;\n\t} per_transport_caps;\n};\n\nstruct ib_rss_caps {\n\tu32 supported_qpts;\n\tu32 max_rwq_indirection_tables;\n\tu32 max_rwq_indirection_table_size;\n};\n\nstruct ib_tm_caps {\n\tu32 max_rndv_hdr_size;\n\tu32 max_num_tags;\n\tu32 flags;\n\tu32 max_ops;\n\tu32 max_sge;\n};\n\nstruct ib_device_attr {\n\tu64 fw_ver;\n\t__be64 sys_image_guid;\n\tu64 max_mr_size;\n\tu64 page_size_cap;\n\tu32 vendor_id;\n\tu32 vendor_part_id;\n\tu32 hw_ver;\n\tint max_qp;\n\tint max_qp_wr;\n\tlong: 32;\n\tu64 device_cap_flags;\n\tu64 kernel_cap_flags;\n\tint max_send_sge;\n\tint max_recv_sge;\n\tint max_sge_rd;\n\tint max_cq;\n\tint max_cqe;\n\tint max_mr;\n\tint max_pd;\n\tint max_qp_rd_atom;\n\tint max_ee_rd_atom;\n\tint max_res_rd_atom;\n\tint max_qp_init_rd_atom;\n\tint max_ee_init_rd_atom;\n\tenum ib_atomic_cap atomic_cap;\n\tenum ib_atomic_cap masked_atomic_cap;\n\tint max_ee;\n\tint max_rdd;\n\tint max_mw;\n\tint max_raw_ipv6_qp;\n\tint max_raw_ethy_qp;\n\tint max_mcast_grp;\n\tint max_mcast_qp_attach;\n\tint max_total_mcast_qp_attach;\n\tint max_ah;\n\tint max_srq;\n\tint max_srq_wr;\n\tint max_srq_sge;\n\tunsigned int max_fast_reg_page_list_len;\n\tunsigned int max_pi_fast_reg_page_list_len;\n\tu16 max_pkeys;\n\tu8 local_ca_ack_delay;\n\tint sig_prot_cap;\n\tint sig_guard_cap;\n\tlong: 32;\n\tstruct ib_odp_caps odp_caps;\n\tuint64_t timestamp_mask;\n\tuint64_t hca_core_clock;\n\tstruct ib_rss_caps rss_caps;\n\tu32 max_wq_type_rq;\n\tu32 raw_packet_caps;\n\tstruct ib_tm_caps tm_caps;\n\tstruct ib_cq_caps cq_caps;\n\tlong: 32;\n\tu64 max_dm_size;\n\tu32 max_sgl_rd;\n\tlong: 32;\n};\n\nstruct hw_stats_device_data;\n\nstruct rdma_restrack_root;\n\nstruct uapi_definition;\n\nstruct ib_port_data;\n\nstruct rdma_link_ops;\n\nstruct ib_device {\n\tstruct device *dma_device;\n\tstruct ib_device_ops ops;\n\tchar name[64];\n\tstruct callback_head callback_head;\n\tstruct list_head event_handler_list;\n\tstruct rw_semaphore event_handler_rwsem;\n\tspinlock_t qp_open_list_lock;\n\tstruct rw_semaphore client_data_rwsem;\n\tstruct xarray client_data;\n\tstruct mutex unregistration_lock;\n\trwlock_t cache_lock;\n\tstruct ib_port_data *port_data;\n\tint num_comp_vectors;\n\tlong: 32;\n\tunion {\n\t\tstruct device dev;\n\t\tstruct ib_core_device coredev;\n\t};\n\tconst struct attribute_group *groups[4];\n\tu8 hw_stats_attr_index;\n\tlong: 32;\n\tu64 uverbs_cmd_mask;\n\tchar node_desc[64];\n\t__be64 node_guid;\n\tu32 local_dma_lkey;\n\tu16 is_switch: 1;\n\tu16 kverbs_provider: 1;\n\tu16 use_cq_dim: 1;\n\tu8 node_type;\n\tu32 phys_port_cnt;\n\tlong: 32;\n\tstruct ib_device_attr attrs;\n\tstruct hw_stats_device_data *hw_stats_data;\n\tu32 index;\n\tspinlock_t cq_pools_lock;\n\tstruct list_head cq_pools[3];\n\tstruct rdma_restrack_root *res;\n\tconst struct uapi_definition *driver_def;\n\trefcount_t refcount;\n\tstruct completion unreg_completion;\n\tstruct work_struct unregistration_work;\n\tconst struct rdma_link_ops *link_ops;\n\tstruct mutex compat_devs_mutex;\n\tstruct xarray compat_devs;\n\tchar iw_ifname[16];\n\tu32 iw_driver_flags;\n\tu32 lag_flags;\n\tstruct mutex subdev_lock;\n\tstruct list_head subdev_list_head;\n\tenum rdma_nl_dev_type type;\n\tstruct ib_device *parent;\n\tstruct list_head subdev_list;\n\tenum rdma_nl_name_assign_type name_assign_type;\n\tlong: 32;\n};\n\nstruct ib_device_modify {\n\tu64 sys_image_guid;\n\tchar node_desc[64];\n};\n\nstruct ib_dm {\n\tstruct ib_device *device;\n\tu32 length;\n\tu32 flags;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_dm_alloc_attr {\n\tu64 length;\n\tu32 alignment;\n\tu32 flags;\n};\n\nstruct ib_dm_mr_attr {\n\tu64 length;\n\tu64 offset;\n\tu32 access_flags;\n\tlong: 32;\n};\n\nstruct ib_dmah {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tstruct rdma_restrack_entry res;\n\tu32 cpu_id;\n\tenum tph_mem_type mem_type;\n\tatomic_t usecnt;\n\tu8 ph;\n\tu8 valid_fields;\n};\n\nstruct ib_event {\n\tstruct ib_device *device;\n\tunion {\n\t\tstruct ib_cq *cq;\n\t\tstruct ib_qp *qp;\n\t\tstruct ib_srq *srq;\n\t\tstruct ib_wq *wq;\n\t\tu32 port_num;\n\t} element;\n\tenum ib_event_type event;\n};\n\nstruct ib_flow {\n\tstruct ib_qp *qp;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n};\n\nstruct ib_flow_action {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tenum ib_flow_action_type type;\n\tatomic_t usecnt;\n};\n\nstruct ib_flow_eth_filter {\n\tu8 dst_mac[6];\n\tu8 src_mac[6];\n\t__be16 ether_type;\n\t__be16 vlan_tag;\n};\n\nstruct ib_flow_spec_eth {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_eth_filter val;\n\tstruct ib_flow_eth_filter mask;\n};\n\nstruct ib_flow_ib_filter {\n\t__be16 dlid;\n\t__u8 sl;\n};\n\nstruct ib_flow_spec_ib {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ib_filter val;\n\tstruct ib_flow_ib_filter mask;\n};\n\nstruct ib_flow_ipv4_filter {\n\t__be32 src_ip;\n\t__be32 dst_ip;\n\tu8 proto;\n\tu8 tos;\n\tu8 ttl;\n\tu8 flags;\n};\n\nstruct ib_flow_spec_ipv4 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv4_filter val;\n\tstruct ib_flow_ipv4_filter mask;\n};\n\nstruct ib_flow_tcp_udp_filter {\n\t__be16 dst_port;\n\t__be16 src_port;\n};\n\nstruct ib_flow_spec_tcp_udp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tcp_udp_filter val;\n\tstruct ib_flow_tcp_udp_filter mask;\n};\n\nstruct ib_flow_ipv6_filter {\n\tu8 src_ip[16];\n\tu8 dst_ip[16];\n\t__be32 flow_label;\n\tu8 next_hdr;\n\tu8 traffic_class;\n\tu8 hop_limit;\n} __attribute__((packed));\n\nstruct ib_flow_spec_ipv6 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv6_filter val;\n\tstruct ib_flow_ipv6_filter mask;\n};\n\nstruct ib_flow_tunnel_filter {\n\t__be32 tunnel_id;\n};\n\nstruct ib_flow_spec_tunnel {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tunnel_filter val;\n\tstruct ib_flow_tunnel_filter mask;\n};\n\nstruct ib_flow_esp_filter {\n\t__be32 spi;\n\t__be32 seq;\n};\n\nstruct ib_flow_spec_esp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_esp_filter val;\n\tstruct ib_flow_esp_filter mask;\n};\n\nstruct ib_flow_gre_filter {\n\t__be16 c_ks_res0_ver;\n\t__be16 protocol;\n\t__be32 key;\n};\n\nstruct ib_flow_spec_gre {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_gre_filter val;\n\tstruct ib_flow_gre_filter mask;\n};\n\nstruct ib_flow_mpls_filter {\n\t__be32 tag;\n};\n\nstruct ib_flow_spec_mpls {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_mpls_filter val;\n\tstruct ib_flow_mpls_filter mask;\n};\n\nstruct ib_flow_spec_action_tag {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tu32 tag_id;\n};\n\nstruct ib_flow_spec_action_drop {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n};\n\nstruct ib_flow_spec_action_handle {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_flow_action *act;\n};\n\nstruct ib_flow_spec_action_count {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_counters *counters;\n};\n\nunion ib_flow_spec {\n\tstruct {\n\t\tu32 type;\n\t\tu16 size;\n\t};\n\tstruct ib_flow_spec_eth eth;\n\tstruct ib_flow_spec_ib ib;\n\tstruct ib_flow_spec_ipv4 ipv4;\n\tstruct ib_flow_spec_tcp_udp tcp_udp;\n\tstruct ib_flow_spec_ipv6 ipv6;\n\tstruct ib_flow_spec_tunnel tunnel;\n\tstruct ib_flow_spec_esp esp;\n\tstruct ib_flow_spec_gre gre;\n\tstruct ib_flow_spec_mpls mpls;\n\tstruct ib_flow_spec_action_tag flow_tag;\n\tstruct ib_flow_spec_action_drop drop;\n\tstruct ib_flow_spec_action_handle action;\n\tstruct ib_flow_spec_action_count flow_count;\n};\n\nstruct ib_flow_attr {\n\tenum ib_flow_attr_type type;\n\tu16 size;\n\tu16 priority;\n\tu32 flags;\n\tu8 num_of_specs;\n\tu32 port;\n\tunion ib_flow_spec flows[0];\n};\n\nunion ib_gid {\n\tu8 raw[16];\n\tstruct {\n\t\t__be64 subnet_prefix;\n\t\t__be64 interface_id;\n\t} global;\n};\n\nstruct ib_gid_attr {\n\tstruct net_device *ndev;\n\tstruct ib_device *device;\n\tunion ib_gid gid;\n\tenum ib_gid_type gid_type;\n\tu16 index;\n\tu32 port_num;\n\tlong: 32;\n};\n\nstruct ib_global_route {\n\tconst struct ib_gid_attr *sgid_attr;\n\tlong: 32;\n\tunion ib_gid dgid;\n\tu32 flow_label;\n\tu8 sgid_index;\n\tu8 hop_limit;\n\tu8 traffic_class;\n};\n\nstruct ib_grh {\n\t__be32 version_tclass_flow;\n\t__be16 paylen;\n\tu8 next_hdr;\n\tu8 hop_limit;\n\tunion ib_gid sgid;\n\tunion ib_gid dgid;\n};\n\nstruct ib_sig_attrs;\n\nstruct ib_mr {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tu32 lkey;\n\tu32 rkey;\n\tu64 iova;\n\tu64 length;\n\tunsigned int page_size;\n\tenum ib_mr_type type;\n\tbool need_inval;\n\tunion {\n\t\tstruct ib_uobject *uobject;\n\t\tstruct list_head qp_entry;\n\t};\n\tstruct ib_dm *dm;\n\tstruct ib_sig_attrs *sig_attrs;\n\tstruct ib_dmah *dmah;\n\tstruct rdma_restrack_entry res;\n\tlong: 32;\n};\n\nstruct ib_sig_err {\n\tenum ib_sig_err_type err_type;\n\tu32 expected;\n\tu32 actual;\n\tlong: 32;\n\tu64 sig_err_offset;\n\tu32 key;\n\tlong: 32;\n};\n\nstruct ib_mr_status {\n\tu32 fail_status;\n\tlong: 32;\n\tstruct ib_sig_err sig_err;\n};\n\nstruct ib_mw {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tu32 rkey;\n\tenum ib_mw_type type;\n};\n\nstruct ib_pd {\n\tu32 local_dma_lkey;\n\tu32 flags;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 unsafe_global_rkey;\n\tstruct ib_mr *__internal_mr;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_port_attr {\n\tu64 subnet_prefix;\n\tenum ib_port_state state;\n\tenum ib_mtu max_mtu;\n\tenum ib_mtu active_mtu;\n\tu32 phys_mtu;\n\tint gid_tbl_len;\n\tunsigned int ip_gids: 1;\n\tu32 port_cap_flags;\n\tu32 max_msg_sz;\n\tu32 bad_pkey_cntr;\n\tu32 qkey_viol_cntr;\n\tu16 pkey_tbl_len;\n\tu32 sm_lid;\n\tu32 lid;\n\tu8 lmc;\n\tu8 max_vl_num;\n\tu8 sm_sl;\n\tu8 subnet_timeout;\n\tu8 init_type_reply;\n\tu8 active_width;\n\tu16 active_speed;\n\tu8 phys_state;\n\tu16 port_cap_flags2;\n};\n\nstruct ib_pkey_cache;\n\nstruct ib_gid_table;\n\nstruct ib_port_cache {\n\tu64 subnet_prefix;\n\tstruct ib_pkey_cache *pkey;\n\tstruct ib_gid_table *gid;\n\tu8 lmc;\n\tenum ib_port_state port_state;\n\tenum ib_port_state last_port_state;\n\tlong: 32;\n};\n\nstruct ib_port_immutable {\n\tint pkey_tbl_len;\n\tint gid_tbl_len;\n\tu32 core_cap_flags;\n\tu32 max_mad_size;\n};\n\nstruct rdma_counter_mode {\n\tenum rdma_nl_counter_mode mode;\n\tenum rdma_nl_counter_mask mask;\n\tstruct auto_mode_param param;\n\tbool bind_opcnt;\n};\n\nstruct rdma_port_counter {\n\tstruct rdma_counter_mode mode;\n\tstruct rdma_hw_stats *hstats;\n\tunsigned int num_counters;\n\tstruct mutex lock;\n};\n\nstruct ib_port;\n\nstruct ib_port_data {\n\tstruct ib_device *ib_dev;\n\tstruct ib_port_immutable immutable;\n\tspinlock_t pkey_list_lock;\n\tspinlock_t netdev_lock;\n\tstruct list_head pkey_list;\n\tlong: 32;\n\tstruct ib_port_cache cache;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\tstruct hlist_node ndev_hash_link;\n\tstruct rdma_port_counter port_counter;\n\tstruct ib_port *sysfs;\n\tlong: 32;\n};\n\nstruct ib_port_modify {\n\tu32 set_port_cap_mask;\n\tu32 clr_port_cap_mask;\n\tu8 init_type;\n};\n\nstruct ib_qp_security;\n\nstruct ib_port_pkey {\n\tenum port_pkey_state state;\n\tu16 pkey_index;\n\tu32 port_num;\n\tstruct list_head qp_list;\n\tstruct list_head to_error_list;\n\tstruct ib_qp_security *sec;\n};\n\nstruct ib_ports_pkeys {\n\tstruct ib_port_pkey main;\n\tstruct ib_port_pkey alt;\n};\n\nstruct ib_uqp_object;\n\nstruct ib_qp {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tspinlock_t mr_lock;\n\tint mrs_used;\n\tstruct list_head rdma_mrs;\n\tstruct list_head sig_mrs;\n\tstruct ib_srq *srq;\n\tstruct completion srq_completion;\n\tstruct ib_xrcd *xrcd;\n\tstruct list_head xrcd_list;\n\tatomic_t usecnt;\n\tstruct list_head open_list;\n\tstruct ib_qp *real_qp;\n\tstruct ib_uqp_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid (*registered_event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tconst struct ib_gid_attr *av_sgid_attr;\n\tconst struct ib_gid_attr *alt_path_sgid_attr;\n\tu32 qp_num;\n\tu32 max_write_sge;\n\tu32 max_read_sge;\n\tenum ib_qp_type qp_type;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tstruct ib_qp_security *qp_sec;\n\tu32 port;\n\tbool integrity_en;\n\tstruct rdma_restrack_entry res;\n\tstruct rdma_counter *counter;\n};\n\nstruct ib_qp_cap {\n\tu32 max_send_wr;\n\tu32 max_recv_wr;\n\tu32 max_send_sge;\n\tu32 max_recv_sge;\n\tu32 max_inline_data;\n\tu32 max_rdma_ctxs;\n};\n\nstruct roce_ah_attr {\n\tu8 dmac[6];\n};\n\nstruct opa_ah_attr {\n\tu32 dlid;\n\tu8 src_path_bits;\n\tbool make_grd;\n};\n\nstruct rdma_ah_attr {\n\tstruct ib_global_route grh;\n\tu8 sl;\n\tu8 static_rate;\n\tu32 port_num;\n\tu8 ah_flags;\n\tenum rdma_ah_attr_type type;\n\tunion {\n\t\tstruct ib_ah_attr ib;\n\t\tstruct roce_ah_attr roce;\n\t\tstruct opa_ah_attr opa;\n\t};\n};\n\nstruct ib_qp_attr {\n\tenum ib_qp_state qp_state;\n\tenum ib_qp_state cur_qp_state;\n\tenum ib_mtu path_mtu;\n\tenum ib_mig_state path_mig_state;\n\tu32 qkey;\n\tu32 rq_psn;\n\tu32 sq_psn;\n\tu32 dest_qp_num;\n\tint qp_access_flags;\n\tstruct ib_qp_cap cap;\n\tlong: 32;\n\tstruct rdma_ah_attr ah_attr;\n\tstruct rdma_ah_attr alt_ah_attr;\n\tu16 pkey_index;\n\tu16 alt_pkey_index;\n\tu8 en_sqd_async_notify;\n\tu8 sq_draining;\n\tu8 max_rd_atomic;\n\tu8 max_dest_rd_atomic;\n\tu8 min_rnr_timer;\n\tu32 port_num;\n\tu8 timeout;\n\tu8 retry_cnt;\n\tu8 rnr_retry;\n\tu32 alt_port_num;\n\tu8 alt_timeout;\n\tu32 rate_limit;\n\tstruct net_device *xmit_slave;\n\tlong: 32;\n};\n\nstruct ib_qp_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tstruct ib_srq *srq;\n\tstruct ib_xrcd *xrcd;\n\tstruct ib_qp_cap cap;\n\tenum ib_sig_type sq_sig_type;\n\tenum ib_qp_type qp_type;\n\tu32 create_flags;\n\tu32 port_num;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tu32 source_qpn;\n};\n\nstruct ib_qp_security {\n\tstruct ib_qp *qp;\n\tstruct ib_device *dev;\n\tstruct mutex mutex;\n\tstruct ib_ports_pkeys *ports_pkeys;\n\tstruct list_head shared_qp_list;\n\tvoid *security;\n\tbool destroying;\n\tatomic_t error_list_count;\n\tstruct completion error_complete;\n\tint error_comps_pending;\n};\n\nstruct ib_rdmacg_object {};\n\nstruct ib_recv_wr {\n\tstruct ib_recv_wr *next;\n\tlong: 32;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n};\n\nstruct ib_rwq_ind_table {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 ind_tbl_num;\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_rwq_ind_table_init_attr {\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_send_wr {\n\tstruct ib_send_wr *next;\n\tlong: 32;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n\tenum ib_wr_opcode opcode;\n\tint send_flags;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tlong: 32;\n};\n\nstruct ib_sge {\n\tu64 addr;\n\tu32 length;\n\tu32 lkey;\n};\n\nstruct ib_t10_dif_domain {\n\tenum ib_t10_dif_bg_type bg_type;\n\tu16 pi_interval;\n\tu16 bg;\n\tu16 app_tag;\n\tu32 ref_tag;\n\tbool ref_remap;\n\tbool app_escape;\n\tbool ref_escape;\n\tu16 apptag_check_mask;\n};\n\nstruct ib_sig_domain {\n\tenum ib_signature_type sig_type;\n\tunion {\n\t\tstruct ib_t10_dif_domain dif;\n\t} sig;\n};\n\nstruct ib_sig_attrs {\n\tu8 check_mask;\n\tstruct ib_sig_domain mem;\n\tstruct ib_sig_domain wire;\n\tint meta_length;\n};\n\nstruct ib_usrq_object;\n\nstruct ib_srq {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_usrq_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tenum ib_srq_type srq_type;\n\tatomic_t usecnt;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t\tu32 srq_num;\n\t\t\t} xrc;\n\t\t};\n\t} ext;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_srq_attr {\n\tu32 max_wr;\n\tu32 max_sge;\n\tu32 srq_limit;\n};\n\nstruct ib_srq_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tstruct ib_srq_attr attr;\n\tenum ib_srq_type srq_type;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t} xrc;\n\t\t\tstruct {\n\t\t\t\tu32 max_num_tags;\n\t\t\t} tag_matching;\n\t\t};\n\t} ext;\n};\n\nstruct ib_ucontext {\n\tstruct ib_device *device;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_rdmacg_object cg_obj;\n\tu64 enabled_caps;\n\tstruct rdma_restrack_entry res;\n\tstruct xarray mmap_xa;\n};\n\nstruct ib_udata {\n\tconst void *inbuf;\n\tvoid *outbuf;\n\tsize_t inlen;\n\tsize_t outlen;\n};\n\nstruct uverbs_api_object;\n\nstruct ib_uobject {\n\tu64 user_handle;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_ucontext *context;\n\tvoid *object;\n\tstruct list_head list;\n\tstruct ib_rdmacg_object cg_obj;\n\tint id;\n\tstruct kref ref;\n\tatomic_t usecnt;\n\tstruct callback_head rcu;\n\tconst struct uverbs_api_object *uapi_object;\n\tlong: 32;\n};\n\nstruct ib_wc {\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tenum ib_wc_status status;\n\tenum ib_wc_opcode opcode;\n\tu32 vendor_err;\n\tu32 byte_len;\n\tstruct ib_qp *qp;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tu32 src_qp;\n\tu32 slid;\n\tint wc_flags;\n\tu16 pkey_index;\n\tu8 sl;\n\tu8 dlid_path_bits;\n\tu32 port_num;\n\tu8 smac[6];\n\tu16 vlan_id;\n\tu8 network_hdr_type;\n};\n\nstruct ib_uwq_object;\n\nstruct ib_wq {\n\tstruct ib_device *device;\n\tstruct ib_uwq_object *uobject;\n\tvoid *wq_context;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tstruct ib_pd *pd;\n\tstruct ib_cq *cq;\n\tu32 wq_num;\n\tenum ib_wq_state state;\n\tenum ib_wq_type wq_type;\n\tatomic_t usecnt;\n};\n\nstruct ib_wq_attr {\n\tenum ib_wq_state wq_state;\n\tenum ib_wq_state curr_wq_state;\n\tu32 flags;\n\tu32 flags_mask;\n};\n\nstruct ib_wq_init_attr {\n\tvoid *wq_context;\n\tenum ib_wq_type wq_type;\n\tu32 max_wr;\n\tu32 max_sge;\n\tstruct ib_cq *cq;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tu32 create_flags;\n};\n\nstruct ib_xrcd {\n\tstruct ib_device *device;\n\tatomic_t usecnt;\n\tstruct inode *inode;\n\tstruct rw_semaphore tgt_qps_rwsem;\n\tstruct xarray tgt_qps;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct icc_bulk_data {\n\tstruct icc_path *path;\n\tconst char *name;\n\tu32 avg_bw;\n\tu32 peak_bw;\n};\n\nstruct icc_bulk_devres {\n\tstruct icc_bulk_data *paths;\n\tint num_paths;\n};\n\nstruct icc_clk_data {\n\tstruct clk *clk;\n\tconst char *name;\n\tunsigned int master_id;\n\tunsigned int slave_id;\n};\n\nstruct icc_clk_node {\n\tstruct clk *clk;\n\tbool enabled;\n};\n\nstruct icc_node;\n\nstruct icc_node_data;\n\nstruct icc_provider {\n\tstruct list_head provider_list;\n\tstruct list_head nodes;\n\tint (*set)(struct icc_node *, struct icc_node *);\n\tint (*aggregate)(struct icc_node *, u32, u32, u32, u32 *, u32 *);\n\tvoid (*pre_aggregate)(struct icc_node *);\n\tint (*get_bw)(struct icc_node *, u32 *, u32 *);\n\tstruct icc_node * (*xlate)(const struct of_phandle_args *, void *);\n\tstruct icc_node_data * (*xlate_extended)(const struct of_phandle_args *, void *);\n\tstruct device *dev;\n\tint users;\n\tbool inter_set;\n\tvoid *data;\n};\n\nstruct icc_clk_provider {\n\tstruct icc_provider provider;\n\tint num_clocks;\n\tstruct icc_clk_node clocks[0];\n};\n\nstruct icc_node {\n\tint id;\n\tconst char *name;\n\tstruct icc_node **links;\n\tsize_t num_links;\n\tstruct icc_provider *provider;\n\tstruct list_head node_list;\n\tstruct list_head search_list;\n\tstruct icc_node *reverse;\n\tu8 is_traversed: 1;\n\tstruct hlist_head req_list;\n\tu32 avg_bw;\n\tu32 peak_bw;\n\tu32 init_avg;\n\tu32 init_peak;\n\tvoid *data;\n};\n\nstruct icc_node_data {\n\tstruct icc_node *node;\n\tu32 tag;\n};\n\nstruct icc_onecell_data {\n\tunsigned int num_nodes;\n\tstruct icc_node *nodes[0];\n};\n\nstruct icc_req {\n\tstruct hlist_node req_node;\n\tstruct icc_node *node;\n\tstruct device *dev;\n\tbool enabled;\n\tu32 tag;\n\tu32 avg_bw;\n\tu32 peak_bw;\n};\n\nstruct icc_path {\n\tconst char *name;\n\tsize_t num_nodes;\n\tstruct icc_req reqs[0];\n};\n\nstruct icc_rpm_smd_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct ich8_pr {\n\tu32 base: 13;\n\tu32 reserved1: 2;\n\tu32 rpe: 1;\n\tu32 limit: 13;\n\tu32 reserved2: 2;\n\tu32 wpe: 1;\n};\n\nunion ich8_flash_protected_range {\n\tstruct ich8_pr range;\n\tu32 regval;\n};\n\nstruct ich8_hsflctl {\n\tu16 flcgo: 1;\n\tu16 flcycle: 2;\n\tu16 reserved: 5;\n\tu16 fldbcount: 2;\n\tu16 flockdn: 6;\n};\n\nstruct ich8_hsfsts {\n\tu16 flcdone: 1;\n\tu16 flcerr: 1;\n\tu16 dael: 1;\n\tu16 berasesz: 2;\n\tu16 flcinprog: 1;\n\tu16 reserved1: 2;\n\tu16 reserved2: 6;\n\tu16 fldesvalid: 1;\n\tu16 flockdn: 1;\n};\n\nunion ich8_hws_flash_ctrl {\n\tstruct ich8_hsflctl hsf_ctrl;\n\tu16 regval;\n};\n\nunion ich8_hws_flash_status {\n\tstruct ich8_hsfsts hsf_status;\n\tu16 regval;\n};\n\nstruct icmp6_err {\n\tint err;\n\tint fatal;\n};\n\nstruct icmp6_ext_iio_addr6_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\tstruct in6_addr addr6;\n};\n\nstruct icmp6_filter {\n\t__u32 data[8];\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 reserved1: 4;\n\t__u8 version: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[7];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6_msg {\n\tstruct sk_buff *skb;\n\tint offset;\n\tuint8_t type;\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct ics932s401_data {\n\tstruct attribute_group attrs;\n\tstruct mutex lock;\n\tchar sensors_valid;\n\tlong unsigned int sensors_last_updated;\n\tu8 regs[21];\n};\n\nstruct icst_params {\n\tlong unsigned int ref;\n\tlong unsigned int vco_max;\n\tlong unsigned int vco_min;\n\tshort unsigned int vd_min;\n\tshort unsigned int vd_max;\n\tunsigned char rd_min;\n\tunsigned char rd_max;\n\tconst unsigned char *s2div;\n\tconst unsigned char *idx2s;\n};\n\nstruct icst_vco {\n\tshort unsigned int v;\n\tunsigned char r;\n\tunsigned char s;\n};\n\nstruct icu_chip_data {\n\tint nr_irqs;\n\tunsigned int virq_base;\n\tunsigned int cascade_irq;\n\tvoid *reg_status;\n\tvoid *reg_mask;\n\tunsigned int conf_enable;\n\tunsigned int conf_disable;\n\tunsigned int conf_mask;\n\tunsigned int conf2_mask;\n\tunsigned int clr_mfp_irq_base;\n\tunsigned int clr_mfp_hwirq;\n\tstruct irq_domain *domain;\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[32];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_statedata {\n\tu32 cpu_state;\n\tu32 mpu_logic_state;\n\tu32 mpu_state;\n\tu32 mpu_state_vote;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n\tlong: 32;\n};\n\nstruct idmac_desc {\n\t__le32 des0;\n\t__le32 des1;\n\t__le32 des2;\n\t__le32 des3;\n};\n\nstruct idmac_desc_64addr {\n\tu32 des0;\n\tu32 des1;\n\tu32 des2;\n\tu32 des3;\n\tu32 des4;\n\tu32 des5;\n\tu32 des6;\n\tu32 des7;\n};\n\nstruct idmap_legacy_upcalldata;\n\nstruct idmap {\n\tstruct rpc_pipe_dir_object idmap_pdo;\n\tstruct rpc_pipe *idmap_pipe;\n\tstruct idmap_legacy_upcalldata *idmap_upcall_data;\n\tstruct mutex idmap_mutex;\n\tstruct user_namespace *user_ns;\n};\n\nstruct idmap_msg {\n\t__u8 im_type;\n\t__u8 im_conv;\n\tchar im_name[128];\n\t__u32 im_id;\n\t__u8 im_status;\n};\n\nstruct idmap_legacy_upcalldata {\n\tstruct rpc_pipe_msg pipe_msg;\n\tstruct idmap_msg idmap_msg;\n\tstruct key *authkey;\n\tstruct idmap *idmap;\n};\n\nstruct ubifs_ch {\n\t__le32 magic;\n\t__le32 crc;\n\t__le64 sqnum;\n\t__le32 len;\n\t__u8 node_type;\n\t__u8 group_type;\n\t__u8 padding[2];\n};\n\nstruct ubifs_idx_node {\n\tstruct ubifs_ch ch;\n\t__le16 child_cnt;\n\t__le16 level;\n\t__u8 branches[0];\n};\n\nstruct idx_node {\n\tstruct list_head list;\n\tint iip;\n\tlong: 32;\n\tunion ubifs_key upper_key;\n\tstruct ubifs_idx_node idx;\n\tlong: 32;\n};\n\nstruct if6_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tint offset;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa6_config {\n\tconst struct in6_addr *pfx;\n\tunsigned int plen;\n\tu8 ifa_proto;\n\tconst struct in6_addr *peer_pfx;\n\tu32 rt_priority;\n\tu32 ifa_flags;\n\tu32 preferred_lft;\n\tu32 valid_lft;\n\tu16 scope;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifaddrlblmsg {\n\t__u8 ifal_family;\n\t__u8 __ifal_reserved;\n\t__u8 ifal_prefixlen;\n\t__u8 ifal_flags;\n\t__u32 ifal_index;\n\t__u32 ifal_seq;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_cacheinfo {\n\t__u32 max_reasm_len;\n\t__u32 tstamp;\n\t__u32 reachable_time;\n\t__u32 retrans_time;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\tlong: 32;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct inet6_dev;\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct igb_tx_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 restart_queue;\n\tu64 restart_queue2;\n};\n\nstruct igb_rx_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 drops;\n\tu64 csum_err;\n\tu64 alloc_failed;\n};\n\nstruct igb_q_vector;\n\nstruct igb_tx_buffer;\n\nstruct igb_rx_buffer;\n\nstruct igb_ring {\n\tstruct igb_q_vector *q_vector;\n\tstruct net_device *netdev;\n\tstruct bpf_prog *xdp_prog;\n\tstruct device *dev;\n\tunion {\n\t\tstruct igb_tx_buffer *tx_buffer_info;\n\t\tstruct igb_rx_buffer *rx_buffer_info;\n\t\tstruct xdp_buff **rx_buffer_info_zc;\n\t};\n\tvoid *desc;\n\tlong unsigned int flags;\n\tvoid *tail;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tu16 count;\n\tu8 queue_index;\n\tu8 reg_idx;\n\tbool launchtime_enable;\n\tbool cbs_enable;\n\ts32 idleslope;\n\ts32 sendslope;\n\ts32 hicredit;\n\ts32 locredit;\n\tu16 next_to_clean;\n\tu16 next_to_use;\n\tu16 next_to_alloc;\n\tunion {\n\t\tstruct {\n\t\t\tstruct igb_tx_queue_stats tx_stats;\n\t\t\tstruct u64_stats_sync tx_syncp;\n\t\t\tstruct u64_stats_sync tx_syncp2;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *skb;\n\t\t\tlong: 32;\n\t\t\tstruct igb_rx_queue_stats rx_stats;\n\t\t\tstruct u64_stats_sync rx_syncp;\n\t\t\tlong: 32;\n\t\t};\n\t};\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct vf_mac_filter {\n\tstruct list_head l;\n\tint vf;\n\tbool free;\n\tu8 vf_mac[6];\n};\n\nstruct vf_data_storage;\n\nstruct igb_mac_addr;\n\nstruct igb_adapter {\n\tlong unsigned int active_vlans[128];\n\tstruct net_device *netdev;\n\tstruct bpf_prog *xdp_prog;\n\tlong unsigned int state;\n\tunsigned int flags;\n\tunsigned int num_q_vectors;\n\tstruct msix_entry msix_entries[10];\n\tu32 rx_itr_setting;\n\tu32 tx_itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tu16 tx_work_limit;\n\tu32 tx_timeout_count;\n\tint num_tx_queues;\n\tstruct igb_ring *tx_ring[16];\n\tint num_rx_queues;\n\tstruct igb_ring *rx_ring[16];\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tu16 mng_vlan_id;\n\tu32 bd_number;\n\tu32 wol;\n\tu32 en_mng_pt;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu8 *io_addr;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tbool fc_autoneg;\n\tu8 tx_timeout_factor;\n\tstruct timer_list blink_timer;\n\tlong unsigned int led_status;\n\tstruct pci_dev *pdev;\n\tspinlock_t stats64_lock;\n\tlong: 32;\n\tstruct rtnl_link_stats64 stats64;\n\tstruct e1000_hw___2 hw;\n\tstruct e1000_hw_stats___2 stats;\n\tstruct e1000_phy_info___2 phy_info;\n\tu32 test_icr;\n\tlong: 32;\n\tstruct igb_ring test_tx_ring;\n\tstruct igb_ring test_rx_ring;\n\tint msg_enable;\n\tstruct igb_q_vector *q_vector[8];\n\tu32 eims_enable_mask;\n\tu32 eims_other;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tunsigned int vfs_allocated_count;\n\tstruct vf_data_storage *vf_data;\n\tint vf_rate_link_speed;\n\tu32 rss_queues;\n\tu32 wvbr;\n\tu32 *shadow_vfta;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_caps;\n\tstruct delayed_work ptp_overflow_work;\n\tstruct work_struct ptp_tx_work;\n\tstruct sk_buff *ptp_tx_skb;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tlong unsigned int ptp_tx_start;\n\tlong unsigned int last_rx_ptp_check;\n\tlong unsigned int last_rx_timestamp;\n\tunsigned int ptp_flags;\n\tspinlock_t tmreg_lock;\n\tlong: 32;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tu32 rx_hwtstamp_cleared;\n\tbool pps_sys_wrap_on;\n\tstruct ptp_pin_desc sdp_config[4];\n\tstruct {\n\t\tstruct timespec64 start;\n\t\tstruct timespec64 period;\n\t} perout[2];\n\tchar fw_version[48];\n\tstruct hwmon_buff *igb_hwmon_buff;\n\tbool ets;\n\tstruct i2c_algo_bit_data i2c_algo;\n\tstruct i2c_adapter i2c_adap;\n\tstruct i2c_client *i2c_client;\n\tu32 rss_indir_tbl_init;\n\tu8 rss_indir_tbl[128];\n\tlong unsigned int link_check_timeout;\n\tint copper_tries;\n\tstruct e1000_info___2 ei;\n\tu16 eee_advert;\n\tstruct hlist_head nfc_filter_list;\n\tstruct hlist_head cls_flower_list;\n\tunsigned int nfc_filter_count;\n\tspinlock_t nfc_lock;\n\tbool etype_bitmap[3];\n\tstruct igb_mac_addr *mac_table;\n\tstruct vf_mac_filter vf_macs;\n\tstruct vf_mac_filter *vf_mac_list;\n\tspinlock_t vfs_lock;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct igb_mac_addr {\n\tu8 addr[6];\n\tu8 queue;\n\tu8 state;\n};\n\nstruct igb_nfc_input {\n\tu8 match_flags;\n\t__be16 etype;\n\t__be16 vlan_tci;\n\tu8 src_addr[6];\n\tu8 dst_addr[6];\n};\n\nstruct igb_nfc_filter {\n\tstruct hlist_node nfc_node;\n\tstruct igb_nfc_input filter;\n\tlong unsigned int cookie;\n\tu16 etype_reg_index;\n\tu16 sw_idx;\n\tu16 action;\n};\n\nstruct igb_ring_container {\n\tstruct igb_ring *ring;\n\tunsigned int total_bytes;\n\tunsigned int total_packets;\n\tu16 work_limit;\n\tu8 count;\n\tu8 itr;\n};\n\nstruct igb_q_vector {\n\tstruct igb_adapter *adapter;\n\tint cpu;\n\tu32 eims_value;\n\tu16 itr_val;\n\tu8 set_itr;\n\tvoid *itr_register;\n\tstruct igb_ring_container rx;\n\tstruct igb_ring_container tx;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tstruct callback_head rcu;\n\tchar name[25];\n\tlong: 32;\n\tstruct igb_ring ring[0];\n};\n\nstruct igb_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nstruct igb_reg_test {\n\tu16 reg;\n\tu16 reg_offset;\n\tu16 array_len;\n\tu16 test_type;\n\tu32 mask;\n\tu32 write;\n};\n\nstruct igb_rx_buffer {\n\tdma_addr_t dma;\n\tstruct page *page;\n\t__u16 page_offset;\n\t__u16 pagecnt_bias;\n};\n\nstruct igb_stats {\n\tchar stat_string[32];\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct xdp_frame;\n\nstruct igb_tx_buffer {\n\tunion e1000_adv_tx_desc *next_to_watch;\n\tlong unsigned int time_stamp;\n\tenum igb_tx_buf_type type;\n\tunion {\n\t\tstruct sk_buff *skb;\n\t\tstruct xdp_frame *xdpf;\n\t};\n\tunsigned int bytecount;\n\tu16 gso_segs;\n\t__be16 protocol;\n\tdma_addr_t dma;\n\t__u32 len;\n\tu32 tx_flags;\n};\n\nstruct igmp6_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct igmp6_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *im;\n};\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct ignore_entry {\n\tu16 vid;\n\tu16 pid;\n\tu16 bcdmin;\n\tu16 bcdmax;\n};\n\nstruct iio_buffer_access_funcs;\n\nstruct iio_dev_attr;\n\nstruct iio_buffer {\n\tunsigned int length;\n\tlong unsigned int flags;\n\tsize_t bytes_per_datum;\n\tenum iio_buffer_direction direction;\n\tconst struct iio_buffer_access_funcs *access;\n\tlong int *scan_mask;\n\tstruct list_head demux_list;\n\twait_queue_head_t pollq;\n\tunsigned int watermark;\n\tbool scan_timestamp;\n\tstruct list_head buffer_attr_list;\n\tstruct attribute_group buffer_group;\n\tconst struct iio_dev_attr **attrs;\n\tvoid *demux_bounce;\n\tstruct list_head attached_entry;\n\tstruct list_head buffer_list;\n\tstruct kref ref;\n\tstruct list_head dmabufs;\n\tstruct mutex dmabufs_mutex;\n};\n\nstruct iio_dma_buffer_block;\n\nstruct iio_dev;\n\nstruct iio_buffer_access_funcs {\n\tint (*store_to)(struct iio_buffer *, const void *);\n\tint (*read)(struct iio_buffer *, size_t, char *);\n\tsize_t (*data_available)(struct iio_buffer *);\n\tint (*remove_from)(struct iio_buffer *, void *);\n\tint (*write)(struct iio_buffer *, size_t, const char *);\n\tsize_t (*space_available)(struct iio_buffer *);\n\tint (*request_update)(struct iio_buffer *);\n\tint (*set_bytes_per_datum)(struct iio_buffer *, size_t);\n\tint (*set_length)(struct iio_buffer *, unsigned int);\n\tint (*enable)(struct iio_buffer *, struct iio_dev *);\n\tint (*disable)(struct iio_buffer *, struct iio_dev *);\n\tvoid (*release)(struct iio_buffer *);\n\tstruct iio_dma_buffer_block * (*attach_dmabuf)(struct iio_buffer *, struct dma_buf_attachment *);\n\tvoid (*detach_dmabuf)(struct iio_buffer *, struct iio_dma_buffer_block *);\n\tint (*enqueue_dmabuf)(struct iio_buffer *, struct iio_dma_buffer_block *, struct dma_fence *, struct sg_table *, size_t, bool);\n\tstruct device * (*get_dma_dev)(struct iio_buffer *);\n\tvoid (*lock_queue)(struct iio_buffer *);\n\tvoid (*unlock_queue)(struct iio_buffer *);\n\tunsigned int modes;\n\tunsigned int flags;\n};\n\nstruct iio_buffer_setup_ops {\n\tint (*preenable)(struct iio_dev *);\n\tint (*postenable)(struct iio_dev *);\n\tint (*predisable)(struct iio_dev *);\n\tint (*postdisable)(struct iio_dev *);\n\tbool (*validate_scan_mask)(struct iio_dev *, const long unsigned int *);\n};\n\nstruct iio_scan_type {\n\tchar sign;\n\tu8 realbits;\n\tu8 storagebits;\n\tu8 shift;\n\tu8 repeat;\n\tenum iio_endian endianness;\n};\n\nstruct iio_event_spec;\n\nstruct iio_chan_spec_ext_info;\n\nstruct iio_chan_spec {\n\tenum iio_chan_type type;\n\tint channel;\n\tint channel2;\n\tlong unsigned int address;\n\tint scan_index;\n\tunion {\n\t\tstruct iio_scan_type scan_type;\n\t\tstruct {\n\t\t\tconst struct iio_scan_type *ext_scan_type;\n\t\t\tunsigned int num_ext_scan_type;\n\t\t};\n\t};\n\tlong unsigned int info_mask_separate;\n\tlong unsigned int info_mask_separate_available;\n\tlong unsigned int info_mask_shared_by_type;\n\tlong unsigned int info_mask_shared_by_type_available;\n\tlong unsigned int info_mask_shared_by_dir;\n\tlong unsigned int info_mask_shared_by_dir_available;\n\tlong unsigned int info_mask_shared_by_all;\n\tlong unsigned int info_mask_shared_by_all_available;\n\tconst struct iio_event_spec *event_spec;\n\tunsigned int num_event_specs;\n\tconst struct iio_chan_spec_ext_info *ext_info;\n\tconst char *extend_name;\n\tconst char *datasheet_name;\n\tunsigned int modified: 1;\n\tunsigned int indexed: 1;\n\tunsigned int output: 1;\n\tunsigned int differential: 1;\n\tunsigned int has_ext_scan_type: 1;\n};\n\nstruct iio_chan_spec_ext_info {\n\tconst char *name;\n\tenum iio_shared_by shared;\n\tssize_t (*read)(struct iio_dev *, uintptr_t, const struct iio_chan_spec *, char *);\n\tssize_t (*write)(struct iio_dev *, uintptr_t, const struct iio_chan_spec *, const char *, size_t);\n\tuintptr_t private;\n};\n\nstruct iio_channel {\n\tstruct iio_dev *indio_dev;\n\tconst struct iio_chan_spec *channel;\n\tvoid *data;\n};\n\nstruct iio_const_attr {\n\tconst char *string;\n\tstruct device_attribute dev_attr;\n};\n\nstruct iio_demux_table {\n\tunsigned int from;\n\tunsigned int to;\n\tunsigned int length;\n\tstruct list_head l;\n};\n\nstruct iio_trigger;\n\nstruct iio_poll_func;\n\nstruct iio_info;\n\nstruct iio_dev {\n\tint modes;\n\tlong: 32;\n\tstruct device dev;\n\tstruct iio_buffer *buffer;\n\tint scan_bytes;\n\tconst long unsigned int *available_scan_masks;\n\tunsigned int masklength;\n\tconst long unsigned int *active_scan_mask;\n\tbool scan_timestamp;\n\tstruct iio_trigger *trig;\n\tstruct iio_poll_func *pollfunc;\n\tstruct iio_poll_func *pollfunc_event;\n\tconst struct iio_chan_spec *channels;\n\tint num_channels;\n\tconst char *name;\n\tconst char *label;\n\tconst struct iio_info *info;\n\tconst struct iio_buffer_setup_ops *setup_ops;\n\tvoid *priv;\n};\n\nstruct iio_dev_attr {\n\tstruct device_attribute dev_attr;\n\tu64 address;\n\tstruct list_head l;\n\tconst struct iio_chan_spec *c;\n\tstruct iio_buffer *buffer;\n};\n\nstruct iio_dev_buffer_pair {\n\tstruct iio_dev *indio_dev;\n\tstruct iio_buffer *buffer;\n};\n\nstruct iio_event_interface;\n\nstruct iio_ioctl_handler;\n\nstruct iio_dev_opaque {\n\tstruct iio_dev indio_dev;\n\tint currentmode;\n\tint id;\n\tstruct module *driver_module;\n\tstruct mutex mlock;\n\tstruct lock_class_key mlock_key;\n\tstruct mutex info_exist_lock;\n\tstruct lock_class_key info_exist_key;\n\tbool trig_readonly;\n\tstruct iio_event_interface *event_interface;\n\tstruct iio_buffer **attached_buffers;\n\tunsigned int attached_buffers_cnt;\n\tstruct iio_ioctl_handler *buffer_ioctl_handler;\n\tstruct list_head buffer_list;\n\tstruct list_head channel_attr_list;\n\tstruct attribute_group chan_attr_group;\n\tstruct list_head ioctl_handlers;\n\tconst struct attribute_group **groups;\n\tint groupcounter;\n\tstruct attribute_group legacy_scan_el_group;\n\tstruct attribute_group legacy_buffer_group;\n\tvoid *bounce_buffer;\n\tsize_t bounce_buffer_size;\n\tunsigned int scan_index_timestamp;\n\tclockid_t clock_id;\n\tstruct cdev chrdev;\n\tlong unsigned int flags;\n\tstruct dentry *debugfs_dentry;\n\tunsigned int cached_reg_addr;\n\tchar read_buf[20];\n\tunsigned int read_buf_len;\n};\n\nstruct iio_device_config {\n\tunsigned int mode;\n\tunsigned int watermark;\n\tconst long unsigned int *scan_mask;\n\tunsigned int scan_bytes;\n\tbool scan_timestamp;\n};\n\nstruct iio_dmabuf_priv;\n\nstruct iio_dma_fence {\n\tstruct dma_fence base;\n\tstruct iio_dmabuf_priv *priv;\n\tstruct work_struct work;\n\tlong: 32;\n};\n\nstruct iio_dmabuf {\n\t__u32 fd;\n\t__u32 flags;\n\t__u64 bytes_used;\n};\n\nstruct iio_dmabuf_priv {\n\tstruct list_head entry;\n\tstruct kref ref;\n\tstruct iio_buffer *buffer;\n\tstruct iio_dma_buffer_block *block;\n\tlong: 32;\n\tu64 context;\n\tspinlock_t lock;\n\tstruct dma_buf_attachment *attach;\n\tstruct sg_table *sgt;\n\tenum dma_data_direction dir;\n\tatomic_t seqno;\n\tlong: 32;\n};\n\nstruct iio_enum {\n\tconst char * const *items;\n\tunsigned int num_items;\n\tint (*set)(struct iio_dev *, const struct iio_chan_spec *, unsigned int);\n\tint (*get)(struct iio_dev *, const struct iio_chan_spec *);\n};\n\nstruct iio_event_data {\n\t__u64 id;\n\t__s64 timestamp;\n};\n\nstruct iio_ioctl_handler {\n\tstruct list_head entry;\n\tlong int (*ioctl)(struct iio_dev *, struct file *, unsigned int, long unsigned int);\n};\n\nstruct iio_event_interface {\n\twait_queue_head_t wait;\n\tlong: 32;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct iio_event_data *type;\n\t\t\tconst struct iio_event_data *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct iio_event_data *ptr;\n\t\t\tconst struct iio_event_data *ptr_const;\n\t\t};\n\t\tlong: 32;\n\t\tstruct iio_event_data buf[16];\n\t} det_events;\n\tstruct list_head dev_attr_list;\n\tlong unsigned int flags;\n\tstruct attribute_group group;\n\tstruct mutex read_lock;\n\tstruct iio_ioctl_handler ioctl_handler;\n\tlong: 32;\n};\n\nstruct iio_event_spec {\n\tenum iio_event_type type;\n\tenum iio_event_direction dir;\n\tlong unsigned int mask_separate;\n\tlong unsigned int mask_shared_by_type;\n\tlong unsigned int mask_shared_by_dir;\n\tlong unsigned int mask_shared_by_all;\n};\n\nstruct iio_sw_trigger_type;\n\nstruct iio_sw_trigger {\n\tstruct iio_trigger *trigger;\n\tstruct iio_sw_trigger_type *trigger_type;\n\tstruct config_group group;\n};\n\nstruct iio_hrtimer_info {\n\tstruct iio_sw_trigger swt;\n\tstruct hrtimer timer;\n\tint sampling_frequency[2];\n\tktime_t period;\n};\n\nstruct iio_hwmon_state {\n\tstruct iio_channel *channels;\n\tint num_channels;\n\tstruct attribute_group attr_group;\n\tconst struct attribute_group *groups[2];\n\tstruct attribute **attrs;\n};\n\nstruct iio_info {\n\tconst struct attribute_group *event_attrs;\n\tconst struct attribute_group *attrs;\n\tint (*read_raw)(struct iio_dev *, const struct iio_chan_spec *, int *, int *, long int);\n\tint (*read_raw_multi)(struct iio_dev *, const struct iio_chan_spec *, int, int *, int *, long int);\n\tint (*read_avail)(struct iio_dev *, const struct iio_chan_spec *, const int **, int *, int *, long int);\n\tint (*write_raw)(struct iio_dev *, const struct iio_chan_spec *, int, int, long int);\n\tint (*read_label)(struct iio_dev *, const struct iio_chan_spec *, char *);\n\tint (*write_raw_get_fmt)(struct iio_dev *, const struct iio_chan_spec *, long int);\n\tint (*read_event_config)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction);\n\tint (*write_event_config)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, bool);\n\tint (*read_event_value)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, enum iio_event_info, int *, int *);\n\tint (*write_event_value)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, enum iio_event_info, int, int);\n\tint (*read_event_label)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, char *);\n\tint (*validate_trigger)(struct iio_dev *, struct iio_trigger *);\n\tint (*get_current_scan_type)(const struct iio_dev *, const struct iio_chan_spec *);\n\tint (*update_scan_mode)(struct iio_dev *, const long unsigned int *);\n\tint (*debugfs_reg_access)(struct iio_dev *, unsigned int, unsigned int, unsigned int *);\n\tint (*fwnode_xlate)(struct iio_dev *, const struct fwnode_reference_args *);\n\tint (*hwfifo_set_watermark)(struct iio_dev *, unsigned int);\n\tint (*hwfifo_flush_to_buffer)(struct iio_dev *, unsigned int);\n};\n\nstruct iio_kfifo {\n\tstruct iio_buffer buffer;\n\tstruct kfifo kf;\n\tstruct mutex user_lock;\n\tint update_needed;\n};\n\nstruct iio_map {\n\tconst char *adc_channel_label;\n\tconst char *consumer_dev_name;\n\tconst char *consumer_channel;\n\tvoid *consumer_data;\n};\n\nstruct iio_map_internal {\n\tstruct iio_dev *indio_dev;\n\tconst struct iio_map *map;\n\tstruct list_head l;\n};\n\nstruct iio_poll_func {\n\tstruct iio_dev *indio_dev;\n\tirqreturn_t (*h)(int, void *);\n\tirqreturn_t (*thread)(int, void *);\n\tint type;\n\tchar *name;\n\tint irq;\n\ts64 timestamp;\n};\n\nstruct iio_subirq {\n\tbool enabled;\n};\n\nstruct iio_sw_trigger_ops {\n\tstruct iio_sw_trigger * (*probe)(const char *);\n\tint (*remove)(struct iio_sw_trigger *);\n};\n\nstruct iio_sw_trigger_type {\n\tconst char *name;\n\tstruct module *owner;\n\tconst struct iio_sw_trigger_ops *ops;\n\tstruct list_head list;\n\tstruct config_group *group;\n};\n\nstruct iio_trigger_ops;\n\nstruct iio_trigger {\n\tconst struct iio_trigger_ops *ops;\n\tstruct module *owner;\n\tint id;\n\tconst char *name;\n\tstruct device dev;\n\tstruct list_head list;\n\tstruct list_head alloc_list;\n\tatomic_t use_count;\n\tstruct irq_chip subirq_chip;\n\tint subirq_base;\n\tstruct iio_subirq subirqs[2];\n\tlong unsigned int pool[1];\n\tstruct mutex pool_lock;\n\tbool attached_own_device;\n\tstruct work_struct reenable_work;\n\tlong: 32;\n};\n\nstruct iio_trigger_ops {\n\tint (*set_trigger_state)(struct iio_trigger *, bool);\n\tvoid (*reenable)(struct iio_trigger *);\n\tint (*validate_device)(struct iio_trigger *, struct iio_dev *);\n};\n\nstruct imx2_wdt_data {\n\tbool wdw_supported;\n};\n\nstruct imx2_wdt_device {\n\tstruct clk *clk;\n\tstruct regmap *regmap;\n\tstruct watchdog_device wdog;\n\tconst struct imx2_wdt_data *data;\n\tbool ext_reset;\n\tbool clk_is_on;\n\tbool no_ping;\n\tbool sleep_wait;\n};\n\nstruct imx5_suspend_io_state {\n\tu32 offset;\n\tu32 clear;\n\tu32 set;\n\tu32 saved_value;\n};\n\nstruct imx5_cpu_suspend_info {\n\tvoid *m4if_base;\n\tvoid *iomuxc_base;\n\tu32 io_count;\n\tstruct imx5_suspend_io_state io_state[20];\n\tlong: 32;\n};\n\nstruct imx5_pm_data {\n\tphys_addr_t ccm_addr;\n\tphys_addr_t cortex_addr;\n\tphys_addr_t gpc_addr;\n\tphys_addr_t m4if_addr;\n\tphys_addr_t iomuxc_addr;\n\tvoid (*suspend_asm)(void *);\n\tconst u32 *suspend_asm_sz;\n\tconst struct imx5_suspend_io_state *suspend_io_config;\n\tint suspend_io_count;\n};\n\nstruct imx6_pm_base {\n\tphys_addr_t pbase;\n\tvoid *vbase;\n};\n\nstruct imx6_cpu_pm_info {\n\tphys_addr_t pbase;\n\tphys_addr_t resume_addr;\n\tu32 ddr_type;\n\tu32 pm_info_size;\n\tstruct imx6_pm_base mmdc_base;\n\tstruct imx6_pm_base src_base;\n\tstruct imx6_pm_base iomuxc_base;\n\tstruct imx6_pm_base ccm_base;\n\tstruct imx6_pm_base gpc_base;\n\tstruct imx6_pm_base l2_base;\n\tu32 mmdc_io_num;\n\tu32 mmdc_io_val[66];\n\tlong: 32;\n};\n\nstruct imx6_pm_socdata {\n\tu32 ddr_type;\n\tconst char *mmdc_compat;\n\tconst char *src_compat;\n\tconst char *iomuxc_compat;\n\tconst char *gpc_compat;\n\tconst char *pl310_compat;\n\tconst u32 mmdc_io_num;\n\tconst u32 *mmdc_io_offset;\n};\n\nstruct imx7_src_signal;\n\nstruct imx7_src {\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *regmap;\n\tconst struct imx7_src_signal *signals;\n};\n\nstruct imx7_src_signal {\n\tunsigned int offset;\n\tunsigned int bit;\n};\n\nstruct reset_control_ops {\n\tint (*reset)(struct reset_controller_dev *, long unsigned int);\n\tint (*assert)(struct reset_controller_dev *, long unsigned int);\n\tint (*deassert)(struct reset_controller_dev *, long unsigned int);\n\tint (*status)(struct reset_controller_dev *, long unsigned int);\n};\n\nstruct imx7_src_variant {\n\tconst struct imx7_src_signal *signals;\n\tunsigned int signals_num;\n\tstruct reset_control_ops ops;\n};\n\nstruct imx93_clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu32 bit_idx;\n\tu32 val;\n\tu32 mask;\n\tspinlock_t *lock;\n\tunsigned int *share_count;\n};\n\nstruct imx_ahci_priv {\n\tstruct platform_device *ahci_pdev;\n\tenum ahci_imx_type type;\n\tstruct clk *sata_clk;\n\tstruct clk *sata_ref_clk;\n\tstruct clk *ahb_clk;\n\tstruct regmap *gpr;\n\tstruct phy *sata_phy;\n\tstruct phy *cali_phy0;\n\tstruct phy *cali_phy1;\n\tbool no_device;\n\tbool first_time;\n\tu32 phy_params;\n\tu32 imped_ratio;\n};\n\nstruct imx_clk_gpr {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 mask;\n\tu32 reg;\n\tconst u32 *mux_table;\n};\n\nstruct imx_dma_2d_config {\n\tu16 xsr;\n\tu16 ysr;\n\tu16 wsr;\n\tint count;\n};\n\nstruct imx_dma_data {\n\tint dma_request;\n\tint dma_request2;\n\tenum sdma_peripheral_type peripheral_type;\n\tint priority;\n};\n\nstruct stmmac_priv;\n\nstruct imx_priv_data;\n\nstruct imx_dwmac_ops {\n\tu32 addr_width;\n\tu32 flags;\n\tbool mac_rgmii_txclk_auto_adj;\n\tint (*fix_soc_reset)(struct stmmac_priv *);\n\tint (*set_intf_mode)(struct imx_priv_data *, u8);\n\tvoid (*fix_mac_speed)(void *, int, unsigned int);\n};\n\nstruct imx_fracn_gppll_clk {\n\tconst struct imx_fracn_gppll_rate_table *rate_table;\n\tint rate_count;\n\tint flags;\n};\n\nstruct imx_fracn_gppll_rate_table {\n\tunsigned int rate;\n\tunsigned int mfi;\n\tunsigned int mfn;\n\tunsigned int mfd;\n\tunsigned int rdiv;\n\tunsigned int odiv;\n};\n\nstruct imx_gpc_dt_data {\n\tint num_domains;\n\tbool err009619_present;\n\tbool err006287_present;\n};\n\nstruct imx_timer;\n\nstruct imx_gpt_data {\n\tint reg_tstat;\n\tint reg_tcn;\n\tint reg_tcmp;\n\tvoid (*gpt_setup_tctl)(struct imx_timer *);\n\tvoid (*gpt_irq_enable)(struct imx_timer *);\n\tvoid (*gpt_irq_disable)(struct imx_timer *);\n\tvoid (*gpt_irq_acknowledge)(struct imx_timer *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n};\n\nstruct imx_i2c_clk_pair {\n\tu16 div;\n\tu16 val;\n};\n\nstruct imx_i2c_dma {\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n\tstruct dma_chan *chan_using;\n\tstruct completion cmd_complete;\n\tdma_addr_t dma_buf;\n\tunsigned int dma_len;\n\tenum dma_transfer_direction dma_transfer_dir;\n\tenum dma_data_direction dma_data_dir;\n};\n\nstruct imx_i2c_hwdata {\n\tenum imx_i2c_type devtype;\n\tunsigned int regshift;\n\tstruct imx_i2c_clk_pair *clk_div;\n\tunsigned int ndivs;\n\tunsigned int i2sr_clr_opcode;\n\tunsigned int i2cr_ien_opcode;\n\tbool has_err007805;\n};\n\nstruct imx_i2c_struct {\n\tstruct i2c_adapter adapter;\n\tstruct clk *clk;\n\tstruct notifier_block clk_change_nb;\n\tvoid *base;\n\twait_queue_head_t queue;\n\tlong unsigned int i2csr;\n\tunsigned int disable_delay;\n\tint stopped;\n\tunsigned int ifdr;\n\tunsigned int cur_clk;\n\tunsigned int bitrate;\n\tconst struct imx_i2c_hwdata *hwdata;\n\tstruct i2c_bus_recovery_info rinfo;\n\tstruct imx_i2c_dma *dma;\n\tstruct i2c_client *slave;\n\tenum i2c_slave_event last_slave_event;\n\tstruct i2c_msg *msg;\n\tunsigned int msg_buf_idx;\n\tint isr_result;\n\tbool is_lastmsg;\n\tenum imx_i2c_state state;\n\tbool multi_master;\n\tspinlock_t slave_lock;\n\tstruct hrtimer slave_timer;\n};\n\nstruct imx_pgc_regs;\n\nstruct imx_pgc_domain {\n\tstruct generic_pm_domain genpd;\n\tstruct regmap *regmap;\n\tconst struct imx_pgc_regs *regs;\n\tstruct regulator *regulator;\n\tstruct reset_control *reset;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tlong unsigned int pgc;\n\tconst struct {\n\t\tu32 pxx;\n\t\tu32 map;\n\t\tu32 hskreq;\n\t\tu32 hskack;\n\t} bits;\n\tconst int voltage;\n\tconst bool keep_clocks;\n\tstruct device *dev;\n\tunsigned int pgc_sw_pup_reg;\n\tunsigned int pgc_sw_pdn_reg;\n};\n\nstruct imx_pgc_domain_data {\n\tconst struct imx_pgc_domain *domains;\n\tsize_t domains_num;\n\tconst struct regmap_access_table *reg_access_table;\n\tconst struct imx_pgc_regs *pgc_regs;\n};\n\nstruct imx_pgc_regs {\n\tu16 map;\n\tu16 pup;\n\tu16 pdn;\n\tu16 hsk;\n};\n\nstruct imx_pin_mmio {\n\tunsigned int mux_mode;\n\tu16 input_reg;\n\tunsigned int input_val;\n\tlong unsigned int config;\n};\n\nstruct imx_pin_scu {\n\tunsigned int mux_mode;\n\tlong unsigned int config;\n};\n\nstruct imx_pin {\n\tunsigned int pin;\n\tunion {\n\t\tstruct imx_pin_mmio mmio;\n\t\tstruct imx_pin_scu scu;\n\t} conf;\n};\n\nstruct imx_pin_reg {\n\ts16 mux_reg;\n\ts16 conf_reg;\n};\n\nstruct imx_pinctrl_soc_info;\n\nstruct imx_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tvoid *base;\n\tvoid *input_sel_base;\n\tconst struct imx_pinctrl_soc_info *info;\n\tstruct imx_pin_reg *pin_regs;\n\tunsigned int group_index;\n\tstruct mutex mutex;\n};\n\nstruct imx_pinctrl_soc_info {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tunsigned int flags;\n\tconst char *gpr_compatible;\n\tunsigned int mux_mask;\n\tu8 mux_shift;\n\tint (*gpio_set_direction)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int, bool);\n\tint (*imx_pinconf_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*imx_pinconf_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tvoid (*imx_pinctrl_parse_pin)(struct imx_pinctrl *, unsigned int *, struct imx_pin *, const __be32 **);\n};\n\nstruct imx_pll14xx_clk {\n\tenum imx_pll14xx_type type;\n\tconst struct imx_pll14xx_rate_table *rate_table;\n\tint rate_count;\n\tint flags;\n};\n\nstruct imx_pll14xx_rate_table {\n\tunsigned int rate;\n\tunsigned int pdiv;\n\tunsigned int mdiv;\n\tunsigned int sdiv;\n\tunsigned int kdiv;\n};\n\nstruct imx_pm_domain {\n\tstruct generic_pm_domain base;\n\tstruct regmap *regmap;\n\tstruct regulator *supply;\n\tstruct clk *clk[7];\n\tint num_clks;\n\tunsigned int reg_offs;\n\tsigned char cntr_pdn_bit;\n\tunsigned int ipg_rate_mhz;\n\tlong: 32;\n};\n\nstruct imx_uart_data;\n\nstruct imx_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tunsigned int old_status;\n\tunsigned int have_rtscts: 1;\n\tunsigned int have_rtsgpio: 1;\n\tunsigned int dte_mode: 1;\n\tunsigned int inverted_tx: 1;\n\tunsigned int inverted_rx: 1;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_per;\n\tconst struct imx_uart_data *devdata;\n\tstruct mctrl_gpios *gpios;\n\tint idle_counter;\n\tunsigned int dma_is_enabled: 1;\n\tunsigned int dma_is_rxing: 1;\n\tunsigned int dma_is_txing: 1;\n\tstruct dma_chan *dma_chan_rx;\n\tstruct dma_chan *dma_chan_tx;\n\tstruct scatterlist rx_sgl;\n\tstruct scatterlist tx_sgl[2];\n\tvoid *rx_buf;\n\tstruct circ_buf rx_ring;\n\tunsigned int rx_buf_size;\n\tunsigned int rx_period_length;\n\tunsigned int rx_periods;\n\tdma_cookie_t rx_cookie;\n\tunsigned int tx_bytes;\n\tunsigned int dma_tx_nents;\n\tunsigned int saved_reg[10];\n\tbool context_saved;\n\tbool last_putchar_was_newline;\n\tenum imx_tx_state tx_state;\n\tstruct hrtimer trigger_start_tx;\n\tstruct hrtimer trigger_stop_tx;\n\tunsigned int rxtl;\n\tlong: 32;\n};\n\nstruct imx_port_ucrs {\n\tunsigned int ucr1;\n\tunsigned int ucr2;\n\tunsigned int ucr3;\n};\n\nstruct imx_priv_data {\n\tstruct device *dev;\n\tstruct clk *clk_tx;\n\tstruct clk *clk_mem;\n\tstruct regmap *intf_regmap;\n\tu32 intf_reg_off;\n\tbool rmii_refclk_ext;\n\tvoid *base_addr;\n\tconst struct imx_dwmac_ops *ops;\n\tstruct plat_stmmacenet_data *plat_dat;\n};\n\nstruct imx_rngc {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct completion rng_op_done;\n\tu32 err_reg;\n};\n\nstruct thermal_soc_data;\n\nstruct imx_thermal_data {\n\tstruct device *dev;\n\tstruct cpufreq_policy *policy;\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_cooling_device *cdev;\n\tstruct regmap *tempmon;\n\tu32 c1;\n\tu32 c2;\n\tint temp_max;\n\tint alarm_temp;\n\tint last_temp;\n\tbool irq_enabled;\n\tint irq;\n\tstruct clk *thermal_clk;\n\tconst struct thermal_soc_data *socdata;\n\tconst char *temp_grade;\n};\n\nstruct imx_timer {\n\tenum imx_gpt_type type;\n\tvoid *base;\n\tint irq;\n\tstruct clk *clk_per;\n\tstruct clk *clk_ipg;\n\tconst struct imx_gpt_data *gpt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device ced;\n};\n\nstruct imx_uart_data {\n\tunsigned int uts_reg;\n\tenum imx_uart_type devtype;\n};\n\nstruct usbmisc_ops;\n\nstruct imx_usbmisc {\n\tvoid *base;\n\tvoid *blkctl;\n\tspinlock_t lock;\n\tconst struct usbmisc_ops *ops;\n};\n\nstruct imx_usbmisc_data {\n\tstruct device *dev;\n\tint index;\n\tunsigned int disable_oc: 1;\n\tunsigned int oc_pol_active_low: 1;\n\tunsigned int oc_pol_configured: 1;\n\tunsigned int pwr_pol: 1;\n\tunsigned int evdo: 1;\n\tunsigned int ulpi: 1;\n\tunsigned int hsic: 1;\n\tunsigned int ext_id: 1;\n\tunsigned int ext_vbus: 1;\n\tstruct usb_phy *usb_phy;\n\tenum usb_dr_mode available_role;\n\tint emp_curr_control;\n\tint dc_vol_level_adjust;\n\tint rise_fall_time_adjust;\n};\n\nstruct imxdma_engine;\n\nstruct imxdma_channel {\n\tint hw_chaining;\n\tstruct timer_list watchdog;\n\tstruct imxdma_engine *imxdma;\n\tunsigned int channel;\n\tstruct tasklet_struct dma_tasklet;\n\tstruct list_head ld_free;\n\tstruct list_head ld_queue;\n\tstruct list_head ld_active;\n\tint descs_allocated;\n\tenum dma_slave_buswidth word_size;\n\tdma_addr_t per_address;\n\tu32 watermark_level;\n\tstruct dma_chan chan;\n\tstruct dma_async_tx_descriptor desc;\n\tenum dma_status status;\n\tint dma_request;\n\tstruct scatterlist *sg_list;\n\tu32 ccr_from_device;\n\tu32 ccr_to_device;\n\tbool enabled_2d;\n\tint slot_2d;\n\tunsigned int irq;\n\tstruct dma_slave_config config;\n};\n\nstruct imxdma_desc {\n\tstruct list_head node;\n\tstruct dma_async_tx_descriptor desc;\n\tenum dma_status status;\n\tdma_addr_t src;\n\tdma_addr_t dest;\n\tsize_t len;\n\tenum dma_transfer_direction direction;\n\tenum imxdma_prep_type type;\n\tunsigned int config_port;\n\tunsigned int config_mem;\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned int w;\n\tstruct scatterlist *sg;\n\tunsigned int sgcount;\n};\n\nstruct imxdma_engine {\n\tstruct device *dev;\n\tstruct dma_device dma_device;\n\tvoid *base;\n\tstruct clk *dma_ahb;\n\tstruct clk *dma_ipg;\n\tspinlock_t lock;\n\tstruct imx_dma_2d_config slots_2d[2];\n\tstruct imxdma_channel channel[16];\n\tenum imx_dma_type devtype;\n\tunsigned int irq;\n\tunsigned int irq_err;\n};\n\nstruct imxdma_filter_data {\n\tstruct imxdma_engine *imxdma;\n\tint request;\n};\n\nstruct imxi2c_platform_data {\n\tu32 bitrate;\n};\n\nstruct in6_flowlabel_req {\n\tstruct in6_addr flr_dst;\n\t__be32 flr_label;\n\t__u8 flr_action;\n\t__u8 flr_share;\n\t__u16 flr_flags;\n\t__u16 flr_expires;\n\t__u16 flr_linger;\n\t__u32 __flr_pad;\n};\n\nstruct in6_ifreq {\n\tstruct in6_addr ifr6_addr;\n\t__u32 ifr6_prefixlen;\n\tint ifr6_ifindex;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\t__u32 rtmsg_type;\n\t__u16 rtmsg_dst_len;\n\t__u16 rtmsg_src_len;\n\t__u32 rtmsg_metric;\n\tlong unsigned int rtmsg_info;\n\t__u32 rtmsg_flags;\n\tint rtmsg_ifindex;\n};\n\nstruct in6_validator_info {\n\tstruct in6_addr i6vi_addr;\n\tstruct inet6_dev *i6vi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[2];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct inbound_win {\n\tu64 size;\n\tu64 pci_offset;\n\tu64 cpu_addr;\n};\n\nstruct ntfs_buffers {\n\tstruct buffer_head *bh[8];\n\tu32 bytes;\n\tu32 nbufs;\n\tu32 off;\n};\n\nstruct indx_node {\n\tstruct ntfs_buffers nb;\n\tstruct INDEX_BUFFER *index;\n};\n\nstruct ipv6_txoptions;\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n\tu8 dontfrag: 1;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_ra_rtr_pref;\n\t__s32 rtr_probe_interval;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 optimistic_dad;\n\t__s32 use_optimistic;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n\tenum addr_type_t type;\n\tbool force_rt_scope_universe;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\tlong: 32;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_skb_parm;\n\nstruct inet6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 dsthao;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tshort unsigned int addr_type;\n\tstruct in6_addr v6_rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n\tlong: 32;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n\tstruct inet6_cork base6;\n};\n\nstruct ipv6_pinfo;\n\nstruct ipv6_fl_socklist;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_diag_bc_op {\n\tunsigned char code;\n\tunsigned char yes;\n\tshort unsigned int no;\n};\n\nstruct inet_diag_dump_data {\n\tstruct nlattr *req_nlas[4];\n\tstruct bpf_sk_storage_diag *bpf_stg_diag;\n\tbool mark_needed;\n\tbool userlocks_needed;\n};\n\nstruct inet_diag_entry {\n\tconst __be32 *saddr;\n\tconst __be32 *daddr;\n\tu16 sport;\n\tu16 dport;\n\tu16 family;\n\tu16 userlocks;\n\tu32 ifindex;\n\tu32 mark;\n};\n\nstruct inet_diag_req_v2;\n\nstruct inet_diag_msg;\n\nstruct inet_diag_handler {\n\tstruct module *owner;\n\tvoid (*dump)(struct sk_buff *, struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tint (*dump_one)(struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tvoid (*idiag_get_info)(struct sock *, struct inet_diag_msg *, void *);\n\tint (*idiag_get_aux)(struct sock *, bool, struct sk_buff *);\n\tint (*destroy)(struct sk_buff *, const struct inet_diag_req_v2 *);\n\t__u16 idiag_type;\n\t__u16 idiag_info_size;\n};\n\nstruct inet_diag_hostcond {\n\t__u8 family;\n\t__u8 prefix_len;\n\tint port;\n\t__be32 addr[0];\n};\n\nstruct inet_diag_markcond {\n\t__u32 mark;\n\t__u32 mask;\n};\n\nstruct inet_diag_meminfo {\n\t__u32 idiag_rmem;\n\t__u32 idiag_wmem;\n\t__u32 idiag_fmem;\n\t__u32 idiag_tmem;\n};\n\nstruct inet_diag_sockid {\n\t__be16 idiag_sport;\n\t__be16 idiag_dport;\n\t__be32 idiag_src[4];\n\t__be32 idiag_dst[4];\n\t__u32 idiag_if;\n\t__u32 idiag_cookie[2];\n};\n\nstruct inet_diag_msg {\n\t__u8 idiag_family;\n\t__u8 idiag_state;\n\t__u8 idiag_timer;\n\t__u8 idiag_retrans;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_expires;\n\t__u32 idiag_rqueue;\n\t__u32 idiag_wqueue;\n\t__u32 idiag_uid;\n\t__u32 idiag_inode;\n};\n\nstruct inet_diag_req {\n\t__u8 idiag_family;\n\t__u8 idiag_src_len;\n\t__u8 idiag_dst_len;\n\t__u8 idiag_ext;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_states;\n\t__u32 idiag_dbs;\n};\n\nstruct inet_diag_req_v2 {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u8 idiag_ext;\n\t__u8 pad;\n\t__u32 idiag_states;\n\tstruct inet_diag_sockid id;\n};\n\nstruct inet_diag_sockopt {\n\t__u8 recverr: 1;\n\t__u8 is_icsk: 1;\n\t__u8 freebind: 1;\n\t__u8 hdrincl: 1;\n\t__u8 mc_loop: 1;\n\t__u8 transparent: 1;\n\t__u8 mc_all: 1;\n\t__u8 nodefrag: 1;\n\t__u8 bind_address_no_port: 1;\n\t__u8 recverr_rfc4884: 1;\n\t__u8 defer_connect: 1;\n\t__u8 unused: 5;\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n\tlong: 32;\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\nstruct init_data {\n\tunsigned int dmem_len;\n\tunsigned int imem_len;\n\tunsigned int chksum;\n\tbool is_big_endian;\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[24];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[2];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[4];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[24];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n\tlong: 32;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[24];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[2];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[4];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_led {\n\tstruct led_classdev cdev;\n\tstruct input_handle *handle;\n\tunsigned int code;\n};\n\nstruct input_leds {\n\tstruct input_handle handle;\n\tunsigned int num_leds;\n\tstruct input_led leds[0];\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nstruct instance_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_instance *, char *);\n\tssize_t (*store)(struct edac_device_instance *, const char *, size_t);\n};\n\nstruct instance_attribute___2 {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_pci_ctl_info *, char *);\n\tssize_t (*store)(struct edac_pci_ctl_info *, const char *, size_t);\n};\n\nstruct intc_irqpin_config {\n\tint irlm_bit;\n};\n\nstruct intc_irqpin_iomem {\n\tvoid *iomem;\n\tlong unsigned int (*read)(void *);\n\tvoid (*write)(void *, long unsigned int);\n\tint width;\n};\n\nstruct intc_irqpin_priv;\n\nstruct intc_irqpin_irq {\n\tint hw_irq;\n\tint requested_irq;\n\tint domain_irq;\n\tstruct intc_irqpin_priv *p;\n};\n\nstruct intc_irqpin_priv {\n\tstruct intc_irqpin_iomem iomem[6];\n\tstruct intc_irqpin_irq irq[8];\n\tunsigned int sense_bitfield_width;\n\tstruct platform_device *pdev;\n\tstruct irq_chip irq_chip;\n\tstruct irq_domain *irq_domain;\n\tatomic_t wakeup_path;\n\tunsigned int shared_irqs: 1;\n\tu8 shared_irq_mask;\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tlong: 32;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct intmux_irqchip_data {\n\tu32 saved_reg;\n\tint chanidx;\n\tint irq;\n\tstruct irq_domain *domain;\n};\n\nstruct intmux_data {\n\traw_spinlock_t lock;\n\tvoid *regs;\n\tstruct clk *ipg_clk;\n\tint channum;\n\tstruct intmux_irqchip_data irqchip_data[0];\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tlong: 32;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n\tlong: 32;\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tlong: 32;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tlong: 32;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n\tlong: 32;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tlong: 32;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n\tspinlock_t lock;\n\tstruct xarray icq_tree;\n\tstruct io_cq *icq_hint;\n\tstruct hlist_head icq_list;\n\tstruct work_struct release_work;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tlong: 32;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n\tlong: 32;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tlong: 32;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n\tlong: 32;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tlong: 32;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tlong: 32;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tlong: 32;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tlong: 32;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n\tlong: 32;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n\tlong: 32;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pgtable_init_fns {\n\tstruct io_pgtable * (*alloc)(struct io_pgtable_cfg *, void *);\n\tvoid (*free)(struct io_pgtable *);\n\tu32 caps;\n};\n\nstruct io_pgtable_walk_data {\n\tstruct io_pgtable *iop;\n\tvoid *data;\n\tint (*visit)(struct io_pgtable_walk_data *, int, arm_lpae_iopte *, size_t);\n\tlong unsigned int flags;\n\tu64 addr;\n\tconst u64 end;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tlong: 32;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\tlong: 32;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[2];\n\tlong unsigned int sqe_op[3];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tlong: 32;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tlong: 32;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n\tlong: 32;\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tlong: 32;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tlong: 32;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n\tlong: 32;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tlong: 32;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n\tlong: 32;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tlong: 32;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tlong: 32;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tlong: 32;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tlong: 32;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tlong: 32;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[32];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ioam6_hdr {\n\t__u8 opt_type;\n\t__u8 opt_len;\n\tchar: 8;\n\t__u8 type;\n};\n\nstruct ioam6_schema;\n\nstruct ioam6_namespace {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_schema *schema;\n\t__be16 id;\n\t__be32 data;\n\t__be64 data_wide;\n};\n\nstruct ioam6_pernet_data {\n\tstruct mutex lock;\n\tstruct rhashtable namespaces;\n\tstruct rhashtable schemas;\n};\n\nstruct ioam6_schema {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_namespace *ns;\n\tu32 id;\n\tint len;\n\t__be32 hdr;\n\tu8 data[0];\n};\n\nstruct ioam6_trace_hdr {\n\t__be16 namespace_id;\n\tchar: 2;\n\t__u8 overflow: 1;\n\t__u8 nodelen: 5;\n\t__u8 remlen: 7;\n\tunion {\n\t\t__be32 type_be32;\n\t\tstruct {\n\t\t\t__u32 bit7: 1;\n\t\t\t__u32 bit6: 1;\n\t\t\t__u32 bit5: 1;\n\t\t\t__u32 bit4: 1;\n\t\t\t__u32 bit3: 1;\n\t\t\t__u32 bit2: 1;\n\t\t\t__u32 bit1: 1;\n\t\t\t__u32 bit0: 1;\n\t\t\t__u32 bit15: 1;\n\t\t\t__u32 bit14: 1;\n\t\t\t__u32 bit13: 1;\n\t\t\t__u32 bit12: 1;\n\t\t\t__u32 bit11: 1;\n\t\t\t__u32 bit10: 1;\n\t\t\t__u32 bit9: 1;\n\t\t\t__u32 bit8: 1;\n\t\t\t__u32 bit23: 1;\n\t\t\t__u32 bit22: 1;\n\t\t\t__u32 bit21: 1;\n\t\t\t__u32 bit20: 1;\n\t\t\t__u32 bit19: 1;\n\t\t\t__u32 bit18: 1;\n\t\t\t__u32 bit17: 1;\n\t\t\t__u32 bit16: 1;\n\t\t} type;\n\t};\n\t__u8 data[0];\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tlong: 32;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n\tlong: 32;\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tstruct bio io_bio;\n\tlong: 32;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tlong: 32;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tlong: 32;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n\tlong: 32;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n\tlong: 32;\n};\n\nstruct iommu_attach_handle {\n\tstruct iommu_domain *domain;\n};\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n\tstruct iommu_group *singleton_group;\n\tu32 max_pasids;\n\tbool ready;\n};\n\nstruct iova_bitmap;\n\nstruct iommu_dirty_bitmap {\n\tstruct iova_bitmap *bitmap;\n\tstruct iommu_iotlb_gather *gather;\n};\n\nstruct iommu_dirty_ops {\n\tint (*set_dirty_tracking)(struct iommu_domain *, bool);\n\tint (*read_and_clear_dirty)(struct iommu_domain *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct iommu_user_data_array;\n\nstruct iommu_domain_ops {\n\tint (*attach_dev)(struct iommu_domain *, struct device *, struct iommu_domain *);\n\tint (*set_dev_pasid)(struct iommu_domain *, struct device *, ioasid_t, struct iommu_domain *);\n\tint (*map_pages)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct iommu_domain *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tint (*iotlb_sync_map)(struct iommu_domain *, long unsigned int, size_t);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tint (*cache_invalidate_user)(struct iommu_domain *, struct iommu_user_data_array *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tbool (*enforce_cache_coherency)(struct iommu_domain *);\n\tint (*set_pgtable_quirks)(struct iommu_domain *, long unsigned int);\n\tvoid (*free)(struct iommu_domain *);\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tlong: 32;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iopf_queue;\n\nstruct iommu_fault_param {\n\tstruct mutex lock;\n\trefcount_t users;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n\tstruct iopf_queue *queue;\n\tstruct list_head queue_list;\n\tstruct list_head partial;\n\tstruct list_head faults;\n};\n\nstruct iommu_flush_ops {\n\tvoid (*tlb_flush_all)(void *);\n\tvoid (*tlb_flush_walk)(long unsigned int, size_t, size_t, void *);\n\tvoid (*tlb_add_page)(struct iommu_iotlb_gather *, long unsigned int, size_t, void *);\n};\n\nstruct iommu_fwspec {\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct xarray pasid_array;\n\tstruct mutex mutex;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *blocking_domain;\n\tstruct iommu_domain *resetting_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n\tunsigned int owner_cnt;\n\tvoid *owner;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct iommu_pages_list {\n\tstruct list_head pages;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n\tstruct iommu_pages_list freelist;\n\tbool queued;\n};\n\nstruct iommu_user_data;\n\nstruct iopf_fault;\n\nstruct iommu_page_response;\n\nstruct iommufd_viommu;\n\nstruct iommu_ops {\n\tbool (*capable)(struct device *, enum iommu_cap);\n\tvoid * (*hw_info)(struct device *, u32 *, enum iommu_hw_info_type *);\n\tstruct iommu_domain * (*domain_alloc_identity)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_paging_flags)(struct device *, u32, const struct iommu_user_data *);\n\tstruct iommu_domain * (*domain_alloc_paging)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_sva)(struct device *, struct mm_struct *);\n\tstruct iommu_domain * (*domain_alloc_nested)(struct device *, struct iommu_domain *, u32, const struct iommu_user_data *);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tint (*of_xlate)(struct device *, const struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct device *);\n\tvoid (*page_response)(struct device *, struct iopf_fault *, struct iommu_page_response *);\n\tint (*def_domain_type)(struct device *);\n\tsize_t (*get_viommu_size)(struct device *, enum iommu_viommu_type);\n\tint (*viommu_init)(struct iommufd_viommu *, struct iommu_domain *, const struct iommu_user_data *);\n\tconst struct iommu_domain_ops *default_domain_ops;\n\tstruct module *owner;\n\tstruct iommu_domain *identity_domain;\n\tstruct iommu_domain *blocked_domain;\n\tstruct iommu_domain *release_domain;\n\tstruct iommu_domain *default_domain;\n\tu8 user_pasid_table: 1;\n};\n\nstruct iommu_page_response {\n\tu32 pasid;\n\tu32 grpid;\n\tu32 code;\n};\n\nstruct iommu_platform_data {\n\tconst char *reset_name;\n\tint (*assert_reset)(struct platform_device *, const char *);\n\tint (*deassert_reset)(struct platform_device *, const char *);\n\tint (*device_enable)(struct platform_device *);\n\tint (*device_idle)(struct platform_device *);\n\tint (*set_pwrdm_constraint)(struct platform_device *, bool, u8 *);\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n\tvoid (*free)(struct device *, struct iommu_resv_region *);\n};\n\nstruct iommu_user_data {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t len;\n};\n\nstruct iommu_user_data_array {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t entry_len;\n\tu32 entry_num;\n};\n\nstruct iommufd_object {\n\trefcount_t wait_cnt;\n\trefcount_t users;\n\tenum iommufd_object_type type;\n\tunsigned int id;\n};\n\nstruct iommufd_access;\n\nstruct iommufd_hw_queue {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_access *access;\n\tu64 base_addr;\n\tsize_t length;\n\tenum iommu_hw_queue_type type;\n\tvoid (*destroy)(struct iommufd_hw_queue *);\n\tlong: 32;\n};\n\nstruct iommufd_device;\n\nstruct iommufd_vdevice {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_device *idev;\n\tu64 virt_id;\n\tvoid (*destroy)(struct iommufd_vdevice *);\n\tlong: 32;\n};\n\nstruct iommufd_ctx;\n\nstruct iommufd_hwpt_paging;\n\nstruct iommufd_viommu_ops;\n\nstruct iommufd_viommu {\n\tstruct iommufd_object obj;\n\tstruct iommufd_ctx *ictx;\n\tstruct iommu_device *iommu_dev;\n\tstruct iommufd_hwpt_paging *hwpt;\n\tconst struct iommufd_viommu_ops *ops;\n\tstruct xarray vdevs;\n\tstruct list_head veventqs;\n\tstruct rw_semaphore veventqs_rwsem;\n\tenum iommu_viommu_type type;\n};\n\nstruct iommufd_viommu_ops {\n\tvoid (*destroy)(struct iommufd_viommu *);\n\tstruct iommu_domain * (*alloc_domain_nested)(struct iommufd_viommu *, u32, const struct iommu_user_data *);\n\tint (*cache_invalidate)(struct iommufd_viommu *, struct iommu_user_data_array *);\n\tconst size_t vdevice_size;\n\tint (*vdevice_init)(struct iommufd_vdevice *);\n\tsize_t (*get_hw_queue_size)(struct iommufd_viommu *, enum iommu_hw_queue_type);\n\tint (*hw_queue_init_phys)(struct iommufd_hw_queue *, u32, phys_addr_t);\n};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct iopf_queue {\n\tstruct workqueue_struct *wq;\n\tstruct list_head devices;\n\tstruct mutex lock;\n};\n\nstruct ioptdesc {\n\tlong unsigned int __page_flags;\n\tstruct list_head iopt_freelist_elm;\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tu8 incoherent;\n\t\tlong unsigned int __index;\n\t};\n\tvoid *_private;\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n};\n\nstruct iotlb_entry {\n\tu32 da;\n\tu32 pa;\n\tu32 pgsz;\n\tu32 prsvd;\n\tu32 valid;\n\tu32 endian;\n\tu32 elsz;\n\tu32 mixed;\n};\n\nstruct iotlb_lock {\n\tshort int base;\n\tshort int vict;\n};\n\nstruct iova_magazine;\n\nstruct iova_cpu_rcache {\n\tspinlock_t lock;\n\tstruct iova_magazine *loaded;\n\tstruct iova_magazine *prev;\n};\n\nstruct iova_magazine {\n\tunion {\n\t\tlong unsigned int size;\n\t\tstruct iova_magazine *next;\n\t};\n\tlong unsigned int pfns[127];\n};\n\nstruct iova_rcache {\n\tspinlock_t lock;\n\tunsigned int depot_size;\n\tstruct iova_magazine *depot;\n\tstruct iova_cpu_rcache *cpu_rcaches;\n\tstruct iova_domain *iovad;\n\tstruct delayed_work work;\n};\n\nstruct iova_to_phys_data {\n\tarm_lpae_iopte pte;\n\tint lvl;\n\tlong: 32;\n};\n\nstruct ip101a_g_phy_priv {\n\tenum ip101gr_sel_intr32 sel_intr32;\n\tlong: 32;\n\tu64 stats[2];\n};\n\nstruct ip101g_hw_stat {\n\tconst char *name;\n\tint page;\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct ip6_frag_state {\n\tu8 *prevhdr;\n\tunsigned int hlen;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\tint hroom;\n\tint troom;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ipv6hdr;\n\nstruct ip6_fraglist_iter {\n\tstruct ipv6hdr *tmp_hdr;\n\tstruct sk_buff *frag;\n\tint offset;\n\tunsigned int hlen;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct ip6_mtuinfo {\n\tstruct sockaddr_in6 ip6m_addr;\n\t__u32 ip6m_mtu;\n};\n\nstruct ip6_ra_chain {\n\tstruct ip6_ra_chain *next;\n\tstruct sock *sk;\n\tint sel;\n\tvoid (*destructor)(struct sock *);\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip6_tnl {\n\tstruct ip6_tnl *next;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tstruct __ip6_tnl_parm parms;\n\tstruct flowi fl;\n\tstruct dst_cache dst_cache;\n\tstruct gro_cells gro_cells;\n\tint err_count;\n\tlong unsigned int err_time;\n\t__u32 i_seqno;\n\tatomic_t o_seqno;\n\tint hlen;\n\tint tun_hlen;\n\tint encap_hlen;\n\tstruct ip_tunnel_encap encap;\n\tint mlink;\n\tlong: 32;\n};\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip6addrlbl_entry {\n\tstruct in6_addr prefix;\n\tint prefixlen;\n\tint ifindex;\n\tint addrtype;\n\tu32 label;\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n};\n\nstruct ip6addrlbl_init_table {\n\tconst struct in6_addr *prefix;\n\tint prefixlen;\n\tu32 label;\n};\n\nstruct ip6fl_iter_state {\n\tstruct seq_net_private p;\n\tstruct pid_namespace *pid_ns;\n\tint bucket;\n};\n\nstruct ip6rd_flowi {\n\tstruct flowi6 fl6;\n\tstruct in6_addr gateway;\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_beet_phdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 padlen;\n\t__u8 reserved;\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct unix_domain;\n\nstruct ip_map {\n\tstruct cache_head h;\n\tchar m_class[8];\n\tstruct in6_addr m_addr;\n\tstruct unix_domain *m_client;\n\tstruct callback_head m_rcu;\n\tlong: 32;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl_entry;\n\nstruct ip_tunnel {\n\tstruct ip_tunnel *next;\n\tstruct hlist_node hash_node;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tlong unsigned int err_time;\n\tint err_count;\n\tu32 i_seqno;\n\tatomic_t o_seqno;\n\tint tun_hlen;\n\tu32 index;\n\tu8 erspan_ver;\n\tu8 dir;\n\tu16 hwid;\n\tstruct dst_cache dst_cache;\n\tstruct ip_tunnel_parm_kern parms;\n\tint mlink;\n\tint encap_hlen;\n\tint hlen;\n\tstruct ip_tunnel_encap encap;\n\tstruct ip_tunnel_prl_entry *prl;\n\tunsigned int prl_count;\n\tunsigned int ip_tnl_net_id;\n\tstruct gro_cells gro_cells;\n\t__u32 fwmark;\n\tbool collect_md;\n\tbool ignore_df;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n\tlong: 32;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 32;\n\tu8 options[0];\n};\n\nstruct rtnl_link_ops;\n\nstruct ip_tunnel_net {\n\tstruct net_device *fb_tunnel_dev;\n\tstruct rtnl_link_ops *rtnl_link_ops;\n\tstruct hlist_head tunnels[128];\n\tstruct ip_tunnel *collect_md_tun;\n\tint type;\n};\n\nstruct ip_tunnel_parm {\n\tchar name[16];\n\tint link;\n\t__be16 i_flags;\n\t__be16 o_flags;\n\t__be32 i_key;\n\t__be32 o_key;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl {\n\t__be32 addr;\n\t__u16 flags;\n\t__u16 __reserved;\n\t__u32 datalen;\n\t__u32 __reserved2;\n};\n\nstruct ip_tunnel_prl_entry {\n\tstruct ip_tunnel_prl_entry *next;\n\t__be32 addr;\n\tu16 flags;\n\tstruct callback_head callback_head;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned char __pad1[2];\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\t__kernel_ulong_t __unused1;\n\t__kernel_ulong_t __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tstruct rhashtable key_ht;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tlong: 32;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n\tlong: 32;\n};\n\nstruct ipcm6_cookie {\n\tstruct sockcm_cookie sockc;\n\t__s16 hlimit;\n\t__s16 tclass;\n\t__u16 gso_size;\n\t__s8 dontfrag;\n\tstruct ipv6_txoptions *opt;\n\tlong: 32;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n\tlong: 32;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipq5018_priv {\n\tstruct reset_control *rst;\n\tbool set_short_cable_dac;\n};\n\nstruct ipq806x_gmac {\n\tstruct platform_device *pdev;\n\tstruct regmap *nss_common;\n\tstruct regmap *qsgmii_csr;\n\tuint32_t id;\n\tstruct clk *core_clk;\n\tphy_interface_t phy_mode;\n};\n\nstruct iproc_adc_priv {\n\tstruct regmap *regmap;\n\tstruct clk *adc_clk;\n\tstruct mutex mutex;\n\tint irqno;\n\tint chan_val;\n\tint chan_id;\n\tstruct completion completion;\n};\n\nstruct iproc_arm_pll {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tlong unsigned int rate;\n};\n\nstruct iproc_asiu_clk;\n\nstruct iproc_asiu {\n\tvoid *div_base;\n\tvoid *gate_base;\n\tstruct clk_hw_onecell_data *clk_data;\n\tstruct iproc_asiu_clk *clks;\n};\n\nstruct iproc_asiu_div {\n\tunsigned int offset;\n\tunsigned int en_shift;\n\tunsigned int high_shift;\n\tunsigned int high_width;\n\tunsigned int low_shift;\n\tunsigned int low_width;\n};\n\nstruct iproc_asiu_gate {\n\tunsigned int offset;\n\tunsigned int en_shift;\n};\n\nstruct iproc_asiu_clk {\n\tstruct clk_hw hw;\n\tconst char *name;\n\tstruct iproc_asiu *asiu;\n\tlong unsigned int rate;\n\tstruct iproc_asiu_div div;\n\tstruct iproc_asiu_gate gate;\n};\n\nstruct iproc_pll;\n\nstruct iproc_clk_ctrl;\n\nstruct iproc_clk {\n\tstruct clk_hw hw;\n\tstruct iproc_pll *pll;\n\tconst struct iproc_clk_ctrl *ctrl;\n};\n\nstruct iproc_clk_enable_ctrl {\n\tunsigned int offset;\n\tunsigned int enable_shift;\n\tunsigned int hold_shift;\n\tunsigned int bypass_shift;\n};\n\nstruct iproc_clk_reg_op {\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int width;\n};\n\nstruct iproc_clk_ctrl {\n\tunsigned int channel;\n\tlong unsigned int flags;\n\tstruct iproc_clk_enable_ctrl enable;\n\tstruct iproc_clk_reg_op mdiv;\n};\n\nstruct iproc_gpio {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *io_ctrl;\n\tenum iproc_pinconf_ctrl_type io_ctrl_type;\n\traw_spinlock_t lock;\n\tstruct gpio_chip gc;\n\tunsigned int num_banks;\n\tbool pinmux_is_supported;\n\tenum pin_config_param *pinconf_disable;\n\tunsigned int nr_pinconf_disable;\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc pctldesc;\n};\n\nstruct iproc_gpio_chip {\n\tstruct gpio_generic_chip gen_gc;\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *intr;\n};\n\nstruct iproc_mdio_priv {\n\tstruct mii_bus *mii_bus;\n\tvoid *base;\n};\n\nstruct iproc_mdiomux_desc {\n\tvoid *mux_handle;\n\tvoid *base;\n\tstruct device *dev;\n\tstruct mii_bus *mii_bus;\n\tstruct clk *core_clk;\n};\n\nstruct iproc_pcie;\n\nstruct iproc_msi_grp;\n\nstruct iproc_msi {\n\tstruct iproc_pcie *pcie;\n\tconst u16 (*reg_offsets)[8];\n\tstruct iproc_msi_grp *grps;\n\tint nr_irqs;\n\tint nr_cpus;\n\tbool has_inten_reg;\n\tlong unsigned int *bitmap;\n\tstruct mutex bitmap_lock;\n\tunsigned int nr_msi_vecs;\n\tstruct irq_domain *inner_domain;\n\tunsigned int nr_eq_region;\n\tunsigned int nr_msi_region;\n\tvoid *eq_cpu;\n\tdma_addr_t eq_dma;\n\tphys_addr_t msi_addr;\n};\n\nstruct iproc_msi_grp {\n\tstruct iproc_msi *msi;\n\tint gic_irq;\n\tunsigned int eq;\n};\n\nstruct iproc_nand_soc {\n\tstruct brcmnand_soc soc;\n\tvoid *idm_base;\n\tvoid *ext_base;\n\tspinlock_t idm_lock;\n};\n\nstruct iproc_pcie_ob {\n\tresource_size_t axi_offset;\n\tunsigned int nr_windows;\n};\n\nstruct iproc_pcie_ib {\n\tunsigned int nr_regions;\n};\n\nstruct iproc_pcie_ob_map;\n\nstruct iproc_pcie_ib_map;\n\nstruct iproc_pcie {\n\tstruct device *dev;\n\tenum iproc_pcie_type type;\n\tu16 *reg_offsets;\n\tvoid *base;\n\tphys_addr_t base_addr;\n\tstruct resource mem;\n\tstruct phy *phy;\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tbool ep_is_internal;\n\tbool iproc_cfg_read;\n\tbool rej_unconfig_pf;\n\tbool has_apb_err_disable;\n\tbool fix_paxc_cap;\n\tbool need_ob_cfg;\n\tstruct iproc_pcie_ob ob;\n\tconst struct iproc_pcie_ob_map *ob_map;\n\tbool need_ib_cfg;\n\tstruct iproc_pcie_ib ib;\n\tconst struct iproc_pcie_ib_map *ib_map;\n\tbool need_msi_steer;\n\tstruct iproc_msi *msi;\n};\n\nstruct iproc_pcie_ib_map {\n\tenum iproc_pcie_ib_map_type type;\n\tunsigned int size_unit;\n\tresource_size_t region_sizes[9];\n\tunsigned int nr_sizes;\n\tunsigned int nr_windows;\n\tu16 imap_addr_offset;\n\tu16 imap_window_offset;\n};\n\nstruct iproc_pcie_ob_map {\n\tresource_size_t window_sizes[4];\n\tunsigned int nr_sizes;\n};\n\nstruct iproc_pll_ctrl;\n\nstruct iproc_pll_vco_param;\n\nstruct iproc_pll {\n\tvoid *status_base;\n\tvoid *control_base;\n\tvoid *pwr_base;\n\tvoid *asiu_base;\n\tconst struct iproc_pll_ctrl *ctrl;\n\tconst struct iproc_pll_vco_param *vco_param;\n\tunsigned int num_vco_entries;\n};\n\nstruct iproc_pll_aon_pwr_ctrl {\n\tunsigned int offset;\n\tunsigned int pwr_width;\n\tunsigned int pwr_shift;\n\tunsigned int iso_shift;\n};\n\nstruct iproc_pll_reset_ctrl {\n\tunsigned int offset;\n\tunsigned int reset_shift;\n\tunsigned int p_reset_shift;\n};\n\nstruct iproc_pll_dig_filter_ctrl {\n\tunsigned int offset;\n\tunsigned int ki_shift;\n\tunsigned int ki_width;\n\tunsigned int kp_shift;\n\tunsigned int kp_width;\n\tunsigned int ka_shift;\n\tunsigned int ka_width;\n};\n\nstruct iproc_pll_sw_ctrl {\n\tunsigned int offset;\n\tunsigned int shift;\n};\n\nstruct iproc_pll_vco_ctrl {\n\tunsigned int u_offset;\n\tunsigned int l_offset;\n};\n\nstruct iproc_pll_ctrl {\n\tlong unsigned int flags;\n\tstruct iproc_pll_aon_pwr_ctrl aon;\n\tstruct iproc_asiu_gate asiu;\n\tstruct iproc_pll_reset_ctrl reset;\n\tstruct iproc_pll_dig_filter_ctrl dig_filter;\n\tstruct iproc_pll_sw_ctrl sw_ctrl;\n\tstruct iproc_clk_reg_op ndiv_int;\n\tstruct iproc_clk_reg_op ndiv_frac;\n\tstruct iproc_clk_reg_op pdiv;\n\tstruct iproc_pll_vco_ctrl vco_ctrl;\n\tstruct iproc_clk_reg_op status;\n\tstruct iproc_clk_reg_op macro_mode;\n};\n\nstruct iproc_pll_vco_param {\n\tlong unsigned int rate;\n\tunsigned int ndiv_int;\n\tunsigned int ndiv_frac;\n\tunsigned int pdiv;\n};\n\nstruct iproc_pwmc {\n\tvoid *base;\n\tstruct clk *clk;\n};\n\nstruct iproc_rng200_dev {\n\tstruct hwrng rng;\n\tvoid *base;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_destopt_hao {\n\t__u8 type;\n\t__u8 length;\n\tstruct in6_addr addr;\n} __attribute__((packed));\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mreq {\n\tstruct in6_addr ipv6mr_multiaddr;\n\tint ipv6mr_ifindex;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_params {\n\t__s32 disable_ipv6;\n\t__s32 autoconf;\n};\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib6_walker w;\n\tloff_t skip;\n\tstruct fib6_table *tbl;\n\tint sernum;\n};\n\nstruct ipv6_rpl_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u32 cmpre: 4;\n\t__u32 cmpri: 4;\n\t__u32 reserved: 4;\n\t__u32 pad: 4;\n\t__u32 reserved1: 16;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_addr;\n\t\t\tstruct in6_addr addr[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\t__u8 data[0];\n\t\t};\n\t} segments;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct ipv6_saddr_dst {\n\tconst struct in6_addr *addr;\n\tint ifindex;\n\tint scope;\n\tint label;\n\tunsigned int prefs;\n};\n\nstruct ipv6_saddr_score {\n\tint rule;\n\tint addr_type;\n\tstruct inet6_ifaddr *ifa;\n\tlong unsigned int scorebits[1];\n\tint scopedist;\n\tint matchlen;\n};\n\nstruct ipv6_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u8 first_segment;\n\t__u8 flags;\n\t__u16 tag;\n\tstruct in6_addr segments[0];\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tvoid (*xfrm6_local_rxpmtu)(struct sk_buff *, u32);\n\tint (*xfrm6_udp_encap_rcv)(struct sock *, struct sk_buff *);\n\tstruct sk_buff * (*xfrm6_gro_udp_encap_rcv)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*xfrm6_rcv_encap)(struct sk_buff *, int, __be32, int);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n\tcpumask_var_t effective_affinity;\n\tunsigned int ipi_offset;\n};\n\nstruct meson_gpio_irq_controller;\n\nstruct irq_ctl_ops {\n\tvoid (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *, unsigned int, long unsigned int);\n\tvoid (*gpio_irq_init)(struct meson_gpio_irq_controller *);\n\tint (*gpio_irq_set_type)(struct meson_gpio_irq_controller *, unsigned int, u32 *);\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct hlist_node resend_node;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_generic_chip_devres {\n\tstruct irq_chip_generic *gc;\n\tu32 msk;\n\tunsigned int clr;\n\tunsigned int set;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_info {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct irqc_priv;\n\nstruct irqc_irq {\n\tint hw_irq;\n\tint requested_irq;\n\tstruct irqc_priv *p;\n};\n\nstruct irqc_priv {\n\tvoid *iomem;\n\tvoid *cpu_int_base;\n\tstruct irqc_irq irq[32];\n\tunsigned int number_of_irqs;\n\tstruct device *dev;\n\tstruct irq_chip_generic *gc;\n\tstruct irq_domain *irq_domain;\n\tatomic_t wakeup_path;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct irqsteer_data {\n\tvoid *regs;\n\tstruct clk *ipg_clk;\n\tint irq[15];\n\tint irq_count;\n\traw_spinlock_t lock;\n\tint reg_num;\n\tint channel;\n\tstruct irq_domain *domain;\n\tu32 *saved_reg;\n\tstruct device *dev;\n};\n\nstruct isl29003_data {\n\tstruct i2c_client *client;\n\tstruct mutex lock;\n\tu8 reg_cache[4];\n\tu8 power_state_before_suspend;\n};\n\nstruct isl29018_scale {\n\tunsigned int scale;\n\tunsigned int uscale;\n};\n\nstruct isl29018_chip {\n\tstruct regmap *regmap;\n\tstruct mutex lock;\n\tint type;\n\tunsigned int calibscale;\n\tunsigned int ucalibscale;\n\tunsigned int int_time;\n\tstruct isl29018_scale scale;\n\tint prox_scheme;\n\tbool suspended;\n\tstruct regulator *vcc_reg;\n};\n\nstruct isl29018_chip_info {\n\tconst struct iio_chan_spec *channels;\n\tint num_channels;\n\tconst struct iio_info *indio_info;\n\tconst struct regmap_config *regmap_cfg;\n};\n\nstruct isl29028_chip {\n\tstruct mutex lock;\n\tstruct regmap *regmap;\n\tint prox_sampling_int;\n\tint prox_sampling_frac;\n\tbool enable_prox;\n\tint lux_scale;\n\tenum isl29028_als_ir_mode als_ir_mode;\n};\n\nstruct isl29028_prox_data {\n\tint sampling_int;\n\tint sampling_fract;\n\tint sleep_time;\n};\n\nstruct isp1301 {\n\tstruct usb_phy phy;\n\tstruct mutex mutex;\n\tstruct i2c_client *client;\n};\n\nstruct isp1760_memory_chunk {\n\tunsigned int start;\n\tunsigned int size;\n\tunsigned int free;\n};\n\nstruct isp1760_memory_layout;\n\nstruct isp1760_slotinfo;\n\nstruct isp1760_hcd {\n\tstruct usb_hcd *hcd;\n\tvoid *base;\n\tstruct regmap *regs;\n\tstruct regmap_field *fields[78];\n\tbool is_isp1763;\n\tconst struct isp1760_memory_layout *memory_layout;\n\tspinlock_t lock;\n\tstruct isp1760_slotinfo *atl_slots;\n\tint atl_done_map;\n\tstruct isp1760_slotinfo *int_slots;\n\tint int_done_map;\n\tstruct isp1760_memory_chunk memory_pool[56];\n\tstruct list_head qh_list[3];\n\tunsigned int periodic_size;\n\tunsigned int i_thresh;\n\tlong unsigned int reset_done;\n\tlong unsigned int next_statechange;\n};\n\nstruct isp1760_udc;\n\nstruct isp1760_ep {\n\tstruct isp1760_udc *udc;\n\tstruct usb_ep ep;\n\tstruct list_head queue;\n\tunsigned int addr;\n\tunsigned int maxpacket;\n\tchar name[7];\n\tconst struct usb_endpoint_descriptor *desc;\n\tbool rx_pending;\n\tbool halted;\n\tbool wedged;\n};\n\nstruct isp1760_device;\n\nstruct isp1760_udc {\n\tstruct isp1760_device *isp;\n\tint irq;\n\tchar *irqname;\n\tstruct regmap *regs;\n\tstruct regmap_field *fields[40];\n\tstruct usb_gadget_driver *driver;\n\tlong: 32;\n\tstruct usb_gadget gadget;\n\tspinlock_t lock;\n\tstruct timer_list vbus_timer;\n\tstruct isp1760_ep ep[15];\n\tenum isp1760_ctrl_state ep0_state;\n\tu8 ep0_dir;\n\tu16 ep0_length;\n\tbool connected;\n\tbool is_isp1763;\n\tunsigned int devstatus;\n};\n\nstruct isp1760_device {\n\tstruct device *dev;\n\tunsigned int devflags;\n\tstruct gpio_desc *rst_gpio;\n\tstruct isp1760_hcd hcd;\n\tlong: 32;\n\tstruct isp1760_udc udc;\n};\n\nstruct isp1760_memory_layout {\n\tunsigned int blocks[3];\n\tunsigned int blocks_size[3];\n\tunsigned int slot_num;\n\tunsigned int payload_blocks;\n\tunsigned int payload_area_size;\n};\n\nstruct isp1760_qh {\n\tstruct list_head qh_list;\n\tstruct list_head qtd_list;\n\tu32 toggle;\n\tu32 ping;\n\tint slot;\n\tint tt_buffer_dirty;\n};\n\nstruct isp1760_qtd {\n\tu8 packet_type;\n\tvoid *data_buffer;\n\tu32 payload_addr;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n\tsize_t actual_length;\n\tu32 status;\n};\n\nstruct isp1760_request {\n\tstruct usb_request req;\n\tstruct list_head queue;\n\tstruct isp1760_ep *ep;\n\tunsigned int packet_size;\n};\n\nstruct isp1760_slotinfo {\n\tstruct isp1760_qh *qh;\n\tstruct isp1760_qtd *qtd;\n\tlong unsigned int timestamp;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct its_baser {\n\tvoid *base;\n\tlong: 32;\n\tu64 val;\n\tu32 order;\n\tu32 psz;\n};\n\nstruct its_cmd_block {\n\tunion {\n\t\tu64 raw_cmd[4];\n\t\t__le64 raw_cmd_le[4];\n\t};\n};\n\nstruct its_device;\n\nstruct its_collection;\n\nstruct its_vpe;\n\nstruct its_cmd_desc {\n\tunion {\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_inv_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_clear_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_int_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tint valid;\n\t\t} its_mapd_cmd;\n\t\tstruct {\n\t\t\tstruct its_collection *col;\n\t\t\tint valid;\n\t\t} its_mapc_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 phys_id;\n\t\t\tu32 event_id;\n\t\t} its_mapti_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tstruct its_collection *col;\n\t\t\tu32 event_id;\n\t\t} its_movi_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_discard_cmd;\n\t\tstruct {\n\t\t\tstruct its_collection *col;\n\t\t} its_invall_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t} its_vinvall_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_collection *col;\n\t\t\tbool valid;\n\t\t} its_vmapp_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_device *dev;\n\t\t\tu32 virt_id;\n\t\t\tu32 event_id;\n\t\t\tbool db_enabled;\n\t\t} its_vmapti_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t\tbool db_enabled;\n\t\t} its_vmovi_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_collection *col;\n\t\t\tu16 seq_num;\n\t\t\tu16 its_list;\n\t\t} its_vmovp_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t} its_invdb_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tu8 sgi;\n\t\t\tu8 priority;\n\t\t\tbool enable;\n\t\t\tbool group;\n\t\t\tbool clear;\n\t\t} its_vsgi_cmd;\n\t};\n};\n\nstruct its_cmd_info {\n\tenum its_vcpu_info_cmd_type cmd_type;\n\tunion {\n\t\tstruct its_vlpi_map *map;\n\t\tu8 config;\n\t\tbool req_db;\n\t\tstruct {\n\t\t\tbool g0en;\n\t\t\tbool g1en;\n\t\t};\n\t\tstruct {\n\t\t\tu8 priority;\n\t\t\tbool group;\n\t\t};\n\t};\n};\n\nstruct its_collection {\n\tu64 target_address;\n\tu16 col_id;\n\tlong: 32;\n};\n\nstruct its_node;\n\nstruct its_device {\n\tstruct list_head entry;\n\tstruct its_node *its;\n\tstruct event_lpi_map event_map;\n\tvoid *itt;\n\tu32 itt_sz;\n\tu32 nr_ites;\n\tu32 device_id;\n\tbool shared;\n};\n\nstruct its_node {\n\traw_spinlock_t lock;\n\tstruct mutex dev_alloc_lock;\n\tstruct list_head entry;\n\tvoid *base;\n\tvoid *sgir_base;\n\tphys_addr_t phys_base;\n\tstruct its_cmd_block *cmd_base;\n\tstruct its_cmd_block *cmd_write;\n\tlong: 32;\n\tstruct its_baser tables[8];\n\tstruct its_collection *collections;\n\tstruct fwnode_handle *fwnode_handle;\n\tu64 (*get_msi_base)(struct its_device *);\n\tlong: 32;\n\tu64 typer;\n\tu64 cbaser_save;\n\tu32 ctlr_save;\n\tu32 mpidr;\n\tstruct list_head its_device_list;\n\tu64 flags;\n\tlong unsigned int list_nr;\n\tint numa_node;\n\tunsigned int msi_domain_flags;\n\tu32 pre_its_base;\n\tint vlpi_redist_offset;\n\tlong: 32;\n};\n\nstruct its_vlpi_map {\n\tstruct its_vm *vm;\n\tstruct its_vpe *vpe;\n\tu32 vintid;\n\tu8 properties;\n\tbool db_enabled;\n};\n\nstruct its_vm {\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *domain;\n\tstruct page *vprop_page;\n\tstruct its_vpe **vpes;\n\tint nr_vpes;\n\tirq_hw_number_t db_lpi_base;\n\tlong unsigned int *db_bitmap;\n\tint nr_db_lpis;\n\traw_spinlock_t vmapp_lock;\n\tu32 vlpi_count[16];\n};\n\nstruct its_vpe {\n\tstruct page *vpt_page;\n\tstruct its_vm *its_vm;\n\tatomic_t vlpi_count;\n\tint irq;\n\tirq_hw_number_t vpe_db_lpi;\n\tbool resident;\n\tbool ready;\n\tunion {\n\t\tstruct {\n\t\t\tint vpe_proxy_event;\n\t\t\tbool idai;\n\t\t};\n\t\tstruct {\n\t\t\tstruct fwnode_handle *fwnode;\n\t\t\tstruct irq_domain *sgi_domain;\n\t\t\tstruct {\n\t\t\t\tu8 priority;\n\t\t\t\tbool enabled;\n\t\t\t\tbool group;\n\t\t\t} sgi_config[16];\n\t\t};\n\t};\n\tatomic_t vmapp_count;\n\traw_spinlock_t vpe_lock;\n\tu16 col_idx;\n\tu16 vpe_id;\n\tbool pending_last;\n};\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_s journal_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong: 32;\n\tlong long unsigned int blocknr;\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct transaction_stats_s;\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct jedec_ecc_info {\n\tu8 ecc_bits;\n\tu8 codeword_size;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 reserved[2];\n};\n\nstruct jit_ctx {\n\tconst struct bpf_prog *prog;\n\tunsigned int idx;\n\tunsigned int prologue_bytes;\n\tunsigned int epilogue_offset;\n\tunsigned int cpu_architecture;\n\tu32 flags;\n\tu32 *offsets;\n\tu32 *target;\n\tu32 stack_size;\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\twait_queue_head_t j_fc_wait;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tstruct shrinker *j_shrinker;\n\tlong: 32;\n\tstruct percpu_counter j_checkpoint_jh_count;\n\ttransaction_t *j_shrink_transaction;\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tlong unsigned int j_fc_first;\n\tlong unsigned int j_fc_off;\n\tlong unsigned int j_fc_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong: 32;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\terrseq_t j_fs_dev_wb_err;\n\tunsigned int j_total_len;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tint j_transaction_overhead_buffers;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tstruct buffer_head **j_fc_wbuf;\n\tint j_wbufsize;\n\tint j_fc_wbufsize;\n\tpid_t j_last_sync_writer;\n\tlong: 32;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tint (*j_submit_inode_data_buffers)(struct jbd2_inode *);\n\tint (*j_finish_inode_data_buffers)(struct jbd2_inode *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\t__u32 j_csum_seed;\n\tstruct lock_class_key jbd2_trans_commit_key;\n\tvoid (*j_fc_cleanup_callback)(struct journal_s *, int, tid_t);\n\tint (*j_fc_replay_callback)(struct journal_s *, struct buffer_head *, enum passtype, int, tid_t);\n\tint (*j_bmap)(struct journal_s *, sector_t *);\n};\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__be32 s_num_fc_blks;\n\t__be32 s_head;\n\t__u32 s_padding[40];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nstruct js_corr {\n\t__s32 coef[8];\n\t__s16 prec;\n\t__u16 type;\n};\n\nstruct joydev {\n\tint open;\n\tstruct input_handle handle;\n\twait_queue_head_t wait;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n\tstruct js_corr corr[64];\n\tstruct JS_DATA_SAVE_TYPE_32 glue;\n\tint nabs;\n\tint nkey;\n\t__u16 keymap[512];\n\t__u16 keypam[512];\n\t__u8 absmap[64];\n\t__u8 abspam[64];\n\t__s16 abs[64];\n};\n\nstruct js_event {\n\t__u32 time;\n\t__s16 value;\n\t__u8 type;\n\t__u8 number;\n};\n\nstruct joydev_client {\n\tstruct js_event buffer[64];\n\tint head;\n\tint tail;\n\tint startup;\n\tspinlock_t buffer_lock;\n\tstruct fasync_struct *fasync;\n\tstruct joydev *joydev;\n\tstruct list_head node;\n};\n\nstruct k3_mdio_soc_data {\n\tbool manual_mode;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\tlong: 32;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\ntypedef void __restorefn_t(void);\n\ntypedef __restorefn_t *__sigrestore_t;\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[60];\n\tint exported;\n\tint show_value;\n};\n\nstruct karatsuba_ctx {\n\tstruct karatsuba_ctx *next;\n\tmpi_ptr_t tspace;\n\tmpi_size_t tspace_size;\n\tmpi_ptr_t tp;\n\tmpi_size_t tp_size;\n};\n\nstruct led_trigger {\n\tconst char *name;\n\tint (*activate)(struct led_classdev *);\n\tvoid (*deactivate)(struct led_classdev *);\n\tenum led_brightness brightness;\n\tstruct led_hw_trigger_type *trigger_type;\n\tspinlock_t leddev_list_lock;\n\tstruct list_head led_cdevs;\n\tstruct list_head next_trig;\n\tconst struct attribute_group **groups;\n};\n\nstruct kbd_led_trigger {\n\tstruct led_trigger trigger;\n\tunsigned int mask;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tlong: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcmp_epoll_slot {\n\t__u32 efd;\n\t__u32 tfd;\n\t__u32 toff;\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 32;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[10];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tlong unsigned int value;\n\tconst char *name;\n\tconst char *namespace;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n\tlong: 32;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[256];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct kexec_link_entry {\n\tconst char *target;\n\tconst char *name;\n};\n\nstruct kexec_load_limit {\n\tstruct mutex mutex;\n\tint limit;\n};\n\nstruct kexec_relocate_data {\n\tlong unsigned int kexec_start_address;\n\tlong unsigned int kexec_indirection_page;\n\tlong unsigned int kexec_mach_type;\n\tlong unsigned int kexec_r2;\n};\n\nstruct kexec_segment {\n\tunion {\n\t\tvoid *buf;\n\t\tvoid *kbuf;\n\t};\n\tsize_t bufsz;\n\tlong unsigned int mem;\n\tsize_t memsz;\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[2];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tlong: 32;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\tlong: 32;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\tlong: 32;\n\ttime64_t now;\n};\n\nstruct keystone_irq_device {\n\tstruct device *dev;\n\tstruct irq_chip chip;\n\tu32 mask;\n\tint irq;\n\tstruct irq_domain *irqd;\n\tstruct regmap *devctrl_regs;\n\tu32 devctrl_offset;\n\traw_spinlock_t wa_lock;\n};\n\nstruct keystone_pcie {\n\tstruct dw_pcie *pci;\n\tu32 device_id;\n\tint intx_host_irqs[4];\n\tint msi_host_irq;\n\tint num_lanes;\n\tu32 num_viewport;\n\tstruct phy **phy;\n\tstruct device_link **link;\n\tstruct device_node *msi_intc_np;\n\tstruct irq_domain *intx_irq_domain;\n\tstruct device_node *np;\n\tvoid *va_app_base;\n\tstruct resource app;\n\tbool is_am6;\n};\n\nstruct keystone_timer {\n\tvoid *base;\n\tlong unsigned int hz_period;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device event_dev;\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tlong: 32;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct kimage_arch {\n\tu32 kernel_r2;\n};\n\nstruct kimage {\n\tkimage_entry_t head;\n\tkimage_entry_t *entry;\n\tkimage_entry_t *last_entry;\n\tlong unsigned int start;\n\tstruct page *control_code_page;\n\tstruct page *swap_page;\n\tvoid *vmcoreinfo_data_copy;\n\tlong unsigned int nr_segments;\n\tstruct kexec_segment segment[16];\n\tstruct page *segment_cma[16];\n\tstruct list_head control_pages;\n\tstruct list_head dest_pages;\n\tstruct list_head unusable_pages;\n\tlong unsigned int control_page;\n\tunsigned int type: 1;\n\tunsigned int preserve_context: 1;\n\tunsigned int file_mode: 1;\n\tunsigned int no_cma: 1;\n\tstruct kimage_arch arch;\n\tstruct {\n\t\tstruct kexec_segment *scratch;\n\t\tphys_addr_t fdt;\n\t} kho;\n\tvoid *elf_headers;\n\tlong unsigned int elf_headers_sz;\n\tlong unsigned int elf_load_addr;\n\tlong unsigned int dm_crypt_keys_addr;\n\tlong unsigned int dm_crypt_keys_sz;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tlong: 32;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct km_event {\n\tunion {\n\t\tu32 hard;\n\t\tu32 proto;\n\t\tu32 byid;\n\t\tu32 aevent;\n\t\tu32 type;\n\t} data;\n\tu32 seq;\n\tu32 portid;\n\tu32 event;\n\tstruct net *net;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[3];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {\n\tint idx;\n\tpte_t pteval[16];\n};\n\ntypedef struct kmem_cache *kmem_buckets[14];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tstruct kmem_cache_node *node[1];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct knav_acc_channel {\n\tu32 channel;\n\tu32 list_index;\n\tu32 open_mask;\n\tu32 *list_cpu[2];\n\tdma_addr_t list_dma[2];\n\tchar name[32];\n\tatomic_t retrigger_count;\n};\n\nstruct knav_pdsp_info;\n\nstruct knav_acc_info {\n\tu32 pdsp_id;\n\tu32 start_channel;\n\tu32 list_entries;\n\tu32 pacing_mode;\n\tu32 timer_count;\n\tint mem_size;\n\tint list_size;\n\tstruct knav_pdsp_info *pdsp;\n};\n\nstruct knav_link_ram_block {\n\tdma_addr_t dma;\n\tvoid *virt;\n\tsize_t size;\n};\n\nstruct knav_device {\n\tstruct device *dev;\n\tunsigned int base_id;\n\tunsigned int num_queues;\n\tunsigned int num_queues_in_use;\n\tunsigned int inst_shift;\n\tstruct knav_link_ram_block link_rams[2];\n\tvoid *instances;\n\tstruct list_head regions;\n\tstruct list_head queue_ranges;\n\tstruct list_head pools;\n\tstruct list_head pdsps;\n\tstruct list_head qmgrs;\n\tenum qmss_version version;\n};\n\nstruct knav_dma_tx_cfg {\n\tbool filt_einfo;\n\tbool filt_pswords;\n\tenum knav_dma_tx_priority priority;\n};\n\nstruct knav_dma_rx_cfg {\n\tbool einfo_present;\n\tbool psinfo_present;\n\tenum knav_dma_rx_err_mode err_mode;\n\tenum knav_dma_desc_type desc_type;\n\tbool psinfo_at_sop;\n\tunsigned int sop_offset;\n\tunsigned int dst_q;\n\tenum knav_dma_rx_thresholds thresh;\n\tunsigned int fdq[4];\n\tunsigned int sz_thresh0;\n\tunsigned int sz_thresh1;\n\tunsigned int sz_thresh2;\n};\n\nstruct knav_dma_cfg {\n\tenum dma_transfer_direction direction;\n\tunion {\n\t\tstruct knav_dma_tx_cfg tx;\n\t\tstruct knav_dma_rx_cfg rx;\n\t} u;\n};\n\nstruct knav_dma_device;\n\nstruct reg_chan;\n\nstruct reg_tx_sched;\n\nstruct reg_rx_flow;\n\nstruct knav_dma_chan {\n\tenum dma_transfer_direction direction;\n\tstruct knav_dma_device *dma;\n\tatomic_t ref_count;\n\tstruct reg_chan *reg_chan;\n\tstruct reg_tx_sched *reg_tx_sched;\n\tstruct reg_rx_flow *reg_rx_flow;\n\tunsigned int channel;\n\tunsigned int flow;\n\tstruct knav_dma_cfg cfg;\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct knav_dma_desc {\n\t__le32 desc_info;\n\t__le32 tag_info;\n\t__le32 packet_info;\n\t__le32 buff_len;\n\t__le32 buff;\n\t__le32 next_desc;\n\t__le32 orig_len;\n\t__le32 orig_buff;\n\t__le32 epib[4];\n\t__le32 psdata[16];\n\tu32 sw_data[4];\n};\n\nstruct reg_global;\n\nstruct knav_dma_device {\n\tbool loopback;\n\tbool enable_all;\n\tunsigned int tx_priority;\n\tunsigned int rx_priority;\n\tunsigned int rx_timeout;\n\tunsigned int logical_queue_managers;\n\tunsigned int qm_base_address[4];\n\tstruct reg_global *reg_global;\n\tstruct reg_chan *reg_tx_chan;\n\tstruct reg_rx_flow *reg_rx_flow;\n\tstruct reg_chan *reg_rx_chan;\n\tstruct reg_tx_sched *reg_tx_sched;\n\tunsigned int max_rx_chan;\n\tunsigned int max_tx_chan;\n\tunsigned int max_rx_flow;\n\tchar name[32];\n\tatomic_t ref_count;\n\tstruct list_head list;\n\tstruct list_head chan_list;\n\tspinlock_t lock;\n};\n\nstruct knav_dma_pool_device {\n\tstruct device *dev;\n\tstruct list_head list;\n};\n\nstruct knav_irq_info {\n\tint irq;\n\tstruct cpumask *cpu_mask;\n};\n\nstruct knav_reg_pdsp_regs;\n\nstruct knav_reg_acc_command;\n\nstruct knav_pdsp_info {\n\tconst char *name;\n\tstruct knav_reg_pdsp_regs *regs;\n\tunion {\n\t\tvoid *command;\n\t\tstruct knav_reg_acc_command *acc_command;\n\t\tu32 *qos_command;\n\t};\n\tvoid *intd;\n\tu32 *iram;\n\tu32 id;\n\tstruct list_head list;\n\tbool loaded;\n\tbool started;\n};\n\nstruct knav_region;\n\nstruct knav_queue;\n\nstruct knav_pool {\n\tstruct device *dev;\n\tstruct knav_region *region;\n\tstruct knav_queue *queue;\n\tstruct knav_device *kdev;\n\tint region_offset;\n\tint num_desc;\n\tint desc_size;\n\tint region_id;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct list_head region_inst;\n};\n\nstruct knav_reg_config;\n\nstruct knav_reg_region;\n\nstruct knav_reg_queue;\n\nstruct knav_qmgr_info {\n\tunsigned int start_queue;\n\tunsigned int num_queues;\n\tstruct knav_reg_config *reg_config;\n\tstruct knav_reg_region *reg_region;\n\tstruct knav_reg_queue *reg_push;\n\tstruct knav_reg_queue *reg_pop;\n\tstruct knav_reg_queue *reg_peek;\n\tvoid *reg_status;\n\tstruct list_head list;\n};\n\ntypedef void (*knav_queue_notify_fn)(void *);\n\nstruct knav_queue_inst;\n\nstruct knav_queue_stats;\n\nstruct knav_queue {\n\tstruct knav_reg_queue *reg_push;\n\tstruct knav_reg_queue *reg_pop;\n\tstruct knav_reg_queue *reg_peek;\n\tstruct knav_queue_inst *inst;\n\tstruct knav_queue_stats *stats;\n\tknav_queue_notify_fn notifier_fn;\n\tvoid *notifier_fn_arg;\n\tatomic_t notifier_enabled;\n\tstruct callback_head rcu;\n\tunsigned int flags;\n\tstruct list_head list;\n};\n\nstruct knav_range_info;\n\nstruct knav_queue_inst {\n\tu32 *descs;\n\tatomic_t desc_head;\n\tatomic_t desc_tail;\n\tatomic_t desc_count;\n\tstruct knav_acc_channel *acc;\n\tstruct knav_device *kdev;\n\tstruct knav_range_info *range;\n\tstruct knav_qmgr_info *qmgr;\n\tu32 id;\n\tint irq_num;\n\tint notify_needed;\n\tatomic_t num_notifiers;\n\tstruct list_head handles;\n\tconst char *name;\n\tconst char *irq_name;\n};\n\nstruct knav_queue_notify_config {\n\tknav_queue_notify_fn fn;\n\tvoid *fn_arg;\n};\n\nstruct knav_queue_stats {\n\tunsigned int pushes;\n\tunsigned int pops;\n\tunsigned int push_errors;\n\tunsigned int pop_errors;\n\tunsigned int notifies;\n};\n\nstruct knav_range_ops;\n\nstruct knav_range_info {\n\tconst char *name;\n\tstruct knav_device *kdev;\n\tunsigned int queue_base;\n\tunsigned int num_queues;\n\tvoid *queue_base_inst;\n\tunsigned int flags;\n\tstruct list_head list;\n\tconst struct knav_range_ops *ops;\n\tstruct knav_acc_info acc_info;\n\tstruct knav_acc_channel *acc;\n\tunsigned int num_irqs;\n\tstruct knav_irq_info irqs[64];\n};\n\nstruct knav_range_ops {\n\tint (*init_range)(struct knav_range_info *);\n\tint (*free_range)(struct knav_range_info *);\n\tint (*init_queue)(struct knav_range_info *, struct knav_queue_inst *);\n\tint (*open_queue)(struct knav_range_info *, struct knav_queue_inst *, unsigned int);\n\tint (*close_queue)(struct knav_range_info *, struct knav_queue_inst *);\n\tint (*set_notify)(struct knav_range_info *, struct knav_queue_inst *, bool);\n};\n\nstruct knav_reg_acc_command {\n\tu32 command;\n\tu32 queue_mask;\n\tu32 list_dma;\n\tu32 queue_num;\n\tu32 timer_config;\n};\n\nstruct knav_reg_config {\n\tu32 revision;\n\tu32 __pad1;\n\tu32 divert;\n\tu32 link_ram_base0;\n\tu32 link_ram_size0;\n\tu32 link_ram_base1;\n\tu32 __pad2[2];\n\tu32 starvation[0];\n};\n\nstruct knav_reg_pdsp_regs {\n\tu32 control;\n\tu32 status;\n\tu32 cycle_count;\n\tu32 stall_count;\n};\n\nstruct knav_reg_queue {\n\tu32 entry_count;\n\tu32 byte_count;\n\tu32 packet_size;\n\tu32 ptr_size_thresh;\n};\n\nstruct knav_reg_region {\n\tu32 base;\n\tu32 start_index;\n\tu32 size_count;\n\tu32 __pad;\n};\n\nstruct knav_region {\n\tdma_addr_t dma_start;\n\tdma_addr_t dma_end;\n\tvoid *virt_start;\n\tvoid *virt_end;\n\tunsigned int desc_size;\n\tunsigned int used_desc;\n\tunsigned int id;\n\tunsigned int num_desc;\n\tunsigned int link_index;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct list_head pools;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct kona_bcm_timers {\n\tint tmr_irq;\n\tvoid *tmr_regs;\n};\n\nstruct kona_pwmc {\n\tvoid *base;\n\tstruct clk *clk;\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kpp_request;\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct kpp_instance {\n\tvoid (*free)(struct kpp_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct kpp_alg alg;\n\t};\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct kprobe;\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct krb5_ctx {\n\tint initiate;\n\tu32 enctype;\n\tu32 flags;\n\tconst struct gss_krb5_enctype *gk5e;\n\tstruct crypto_sync_skcipher *enc;\n\tstruct crypto_sync_skcipher *seq;\n\tstruct crypto_sync_skcipher *acceptor_enc;\n\tstruct crypto_sync_skcipher *initiator_enc;\n\tstruct crypto_sync_skcipher *acceptor_enc_aux;\n\tstruct crypto_sync_skcipher *initiator_enc_aux;\n\tstruct crypto_ahash *acceptor_sign;\n\tstruct crypto_ahash *initiator_sign;\n\tstruct crypto_ahash *initiator_integ;\n\tstruct crypto_ahash *acceptor_integ;\n\tu8 Ksess[32];\n\tu8 cksum[32];\n\tatomic_t seq_send;\n\tlong: 32;\n\tatomic64_t seq_send64;\n\ttime64_t endtime;\n\tstruct xdr_netobj mech_used;\n};\n\nunion ks8851_tx_hdr {\n\tu8 txb[6];\n\t__le16 txw[3];\n};\n\nstruct mii_if_info {\n\tint phy_id;\n\tint advertising;\n\tint phy_id_mask;\n\tint reg_num_mask;\n\tunsigned int full_duplex: 1;\n\tunsigned int force_media: 1;\n\tunsigned int supports_gmii: 1;\n\tstruct net_device *dev;\n\tint (*mdio_read)(struct net_device *, int, int);\n\tvoid (*mdio_write)(struct net_device *, int, int, int);\n};\n\nstruct ks8851_rxctrl {\n\tu16 mchash[4];\n\tu16 rxcr1;\n\tu16 rxcr2;\n};\n\nstruct ks8851_net {\n\tstruct net_device *netdev;\n\tspinlock_t statelock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion ks8851_tx_hdr txh;\n\tu8 rxd[8];\n\tu8 txd[8];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu32 msg_enable;\n\tu16 tx_space;\n\tu8 fid;\n\tu16 rc_ier;\n\tu16 rc_rxqcr;\n\tu16 rc_ccr;\n\tstruct mii_if_info mii;\n\tstruct ks8851_rxctrl rxctrl;\n\tstruct work_struct rxctrl_work;\n\tstruct sk_buff_head txq;\n\tunsigned int queued_len;\n\tstruct eeprom_93cx6 eeprom;\n\tstruct regulator *vdd_reg;\n\tstruct regulator *vdd_io;\n\tstruct gpio_desc *gpio;\n\tstruct mii_bus *mii_bus;\n\tvoid (*lock)(struct ks8851_net *, long unsigned int *);\n\tvoid (*unlock)(struct ks8851_net *, long unsigned int *);\n\tunsigned int (*rdreg16)(struct ks8851_net *, unsigned int);\n\tvoid (*wrreg16)(struct ks8851_net *, unsigned int, unsigned int);\n\tvoid (*rdfifo)(struct ks8851_net *, u8 *, unsigned int);\n\tvoid (*wrfifo)(struct ks8851_net *, struct sk_buff *, bool);\n\tnetdev_tx_t (*start_xmit)(struct sk_buff *, struct net_device *);\n\tvoid (*flush_tx_work)(struct ks8851_net *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct spi_offload;\n\nstruct spi_message {\n\tstruct list_head transfers;\n\tstruct spi_device *spi;\n\tbool pre_optimized;\n\tbool optimized;\n\tbool prepared;\n\tint status;\n\tvoid (*complete)(void *);\n\tvoid *context;\n\tunsigned int frame_length;\n\tunsigned int actual_length;\n\tstruct list_head queue;\n\tvoid *state;\n\tvoid *opt_state;\n\tstruct spi_offload *offload;\n\tstruct list_head resources;\n};\n\nstruct spi_delay {\n\tu16 value;\n\tu8 unit;\n};\n\nstruct spi_transfer {\n\tconst void *tx_buf;\n\tvoid *rx_buf;\n\tunsigned int len;\n\tu16 error;\n\tbool tx_sg_mapped;\n\tbool rx_sg_mapped;\n\tstruct sg_table tx_sg;\n\tstruct sg_table rx_sg;\n\tdma_addr_t tx_dma;\n\tdma_addr_t rx_dma;\n\tunsigned int dummy_data: 1;\n\tunsigned int cs_off: 1;\n\tunsigned int cs_change: 1;\n\tunsigned int tx_nbits: 4;\n\tunsigned int rx_nbits: 4;\n\tunsigned int multi_lane_mode: 2;\n\tunsigned int timestamped: 1;\n\tbool dtr_mode;\n\tu8 bits_per_word;\n\tstruct spi_delay delay;\n\tstruct spi_delay cs_change_delay;\n\tstruct spi_delay word_delay;\n\tu32 speed_hz;\n\tu32 effective_speed_hz;\n\tunsigned int offload_flags;\n\tunsigned int ptp_sts_word_pre;\n\tunsigned int ptp_sts_word_post;\n\tstruct ptp_system_timestamp *ptp_sts;\n\tstruct list_head transfer_list;\n};\n\nstruct ks8851_net_spi {\n\tstruct ks8851_net ks8851;\n\tstruct mutex lock;\n\tstruct work_struct tx_work;\n\tstruct spi_device *spidev;\n\tstruct spi_message spi_msg1;\n\tstruct spi_message spi_msg2;\n\tstruct spi_transfer spi_xfer1;\n\tstruct spi_transfer spi_xfer2[2];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ks_pcie_of_data {\n\tenum dw_pcie_device_mode mode;\n\tconst struct dw_pcie_host_ops *host_ops;\n\tconst struct dw_pcie_ep_ops *ep_ops;\n\tu32 version;\n};\n\nstruct trng_regs;\n\nstruct ks_sa_rng {\n\tstruct hwrng rng;\n\tstruct clk *clk;\n\tstruct regmap *regmap_cfg;\n\tstruct trng_regs *reg_rng;\n\tu64 ready_ts;\n\tunsigned int refill_delay_ns;\n\tlong: 32;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n\tlong: 32;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n\tlong: 32;\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tlong: 32;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n\tlong: 32;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ksz9477_errata_write {\n\tu8 dev_addr;\n\tu8 reg_addr;\n\tu16 val;\n};\n\nstruct kszphy_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct kszphy_phy_stats {\n\tu64 rx_err_pkt_cnt;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct kszphy_ptp_priv {\n\tstruct mii_timestamper mii_ts;\n\tstruct phy_device *phydev;\n\tstruct sk_buff_head tx_queue;\n\tstruct sk_buff_head rx_queue;\n\tstruct list_head rx_ts_list;\n\tspinlock_t rx_ts_lock;\n\tint hwts_tx_type;\n\tenum hwtstamp_rx_filters rx_filter;\n\tint layer;\n\tint version;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct mutex ptp_lock;\n\tstruct ptp_pin_desc *pin_config;\n\ts64 seconds;\n\tspinlock_t seconds_lock;\n\tlong: 32;\n};\n\nstruct kszphy_type;\n\nstruct kszphy_priv {\n\tstruct kszphy_ptp_priv ptp_priv;\n\tconst struct kszphy_type *type;\n\tstruct clk *clk;\n\tint led_mode;\n\tu16 vct_ctrl1000;\n\tbool rmii_ref_clk_sel;\n\tbool rmii_ref_clk_sel_val;\n\tbool clk_enable;\n\tbool is_ptp_available;\n\tlong: 32;\n\tu64 stats[2];\n\tstruct kszphy_phy_stats phy_stats;\n};\n\nstruct kszphy_type {\n\tu32 led_mode_reg;\n\tu16 interrupt_level_mask;\n\tu16 cable_diag_reg;\n\tlong unsigned int pair_mask;\n\tu16 disable_dll_tx_bit;\n\tu16 disable_dll_rx_bit;\n\tu16 disable_dll_mask;\n\tbool has_broadcast_disable;\n\tbool has_nand_tree_disable;\n\tbool has_rmii_ref_clk_sel;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kvm_ptp_clock {\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info caps;\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nstruct l2x0_regs;\n\nstruct outer_cache_fns {\n\tvoid (*inv_range)(long unsigned int, long unsigned int);\n\tvoid (*clean_range)(long unsigned int, long unsigned int);\n\tvoid (*flush_range)(long unsigned int, long unsigned int);\n\tvoid (*flush_all)(void);\n\tvoid (*disable)(void);\n\tvoid (*sync)(void);\n\tvoid (*resume)(void);\n\tvoid (*write_sec)(long unsigned int, unsigned int);\n\tvoid (*configure)(const struct l2x0_regs *);\n};\n\nstruct l2c_init_data {\n\tconst char *type;\n\tunsigned int way_size_0;\n\tunsigned int num_lock;\n\tvoid (*of_parse)(const struct device_node *, u32 *, u32 *);\n\tvoid (*enable)(void *, unsigned int);\n\tvoid (*fixup)(void *, u32, struct outer_cache_fns *);\n\tvoid (*save)(void *);\n\tvoid (*configure)(void *);\n\tvoid (*unlock)(void *, unsigned int);\n\tstruct outer_cache_fns outer_cache;\n};\n\nstruct l2x0_regs {\n\tlong unsigned int phy_base;\n\tlong unsigned int aux_ctrl;\n\tlong unsigned int tag_latency;\n\tlong unsigned int data_latency;\n\tlong unsigned int filter_start;\n\tlong unsigned int filter_end;\n\tlong unsigned int prefetch_ctrl;\n\tlong unsigned int pwr_ctrl;\n\tlong unsigned int ctrl;\n\tlong unsigned int aux2_ctrl;\n};\n\nstruct l3_target_data;\n\nstruct l3_flagmux_data {\n\tu32 offset;\n\tstruct l3_target_data *l3_targ;\n\tu8 num_targ_data;\n\tu32 mask_app_bits;\n\tu32 mask_dbg_bits;\n};\n\nstruct l3_masters_data {\n\tu32 id;\n\tchar *name;\n};\n\nstruct l3_target_data {\n\tu32 offset;\n\tchar *name;\n};\n\nstruct lan8814_ptp_rx_ts {\n\tstruct list_head list;\n\tu32 seconds;\n\tu32 nsec;\n\tu16 seq_id;\n};\n\nstruct lan8814_shared_priv {\n\tstruct phy_device *phydev;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct ptp_pin_desc *pin_config;\n\tstruct mutex shared_lock;\n};\n\nstruct lan8842_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_errors;\n};\n\nstruct lan8842_priv {\n\tstruct lan8842_phy_stats phy_stats;\n\tstruct kszphy_ptp_priv ptp_priv;\n\tu16 rev;\n\tlong: 32;\n};\n\nstruct lan966x_gck {\n\tstruct clk_hw hw;\n\tvoid *reg;\n};\n\nstruct lan966x_match_data {\n\tchar *name;\n\tconst char * const *clk_name;\n\tconst struct clk_gate_soc_desc *clk_gate_desc;\n\tu8 num_generic_clks;\n\tu8 num_total_clks;\n};\n\nstruct lanphy_reg_data {\n\tint page;\n\tu16 addr;\n\tu16 val;\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tlong: 32;\n\tu64 val[2];\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct lcb {\n\tstruct LFS_RECORD_HDR *lrh;\n\tstruct LOG_REC_HDR *log_rec;\n\tu32 ctx_mode;\n\tstruct CLIENT_ID client;\n\tbool alloc;\n};\n\nstruct lcd_properties {\n\tint max_contrast;\n};\n\nstruct lcd_ops;\n\nstruct lcd_device {\n\tstruct lcd_properties props;\n\tstruct mutex ops_lock;\n\tconst struct lcd_ops *ops;\n\tstruct mutex update_lock;\n\tstruct list_head entry;\n\tstruct device dev;\n};\n\nstruct lcd_ops {\n\tint (*get_power)(struct lcd_device *);\n\tint (*set_power)(struct lcd_device *, int);\n\tint (*get_contrast)(struct lcd_device *);\n\tint (*set_contrast)(struct lcd_device *, int);\n\tint (*set_mode)(struct lcd_device *, u32, u32);\n\tbool (*controls_device)(struct lcd_device *, struct device *);\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct le_str {\n\tu8 len;\n\tu8 unused;\n\t__le16 name[0];\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct mc_subled;\n\nstruct led_classdev_mc {\n\tstruct led_classdev led_cdev;\n\tunsigned int num_colors;\n\tstruct mc_subled *subled_info;\n};\n\nstruct led_hw_trigger_type {\n\tint dummy;\n};\n\nstruct led_init_data {\n\tstruct fwnode_handle *fwnode;\n\tconst char *default_label;\n\tconst char *devicename;\n\tbool devname_mandatory;\n};\n\nstruct led_lookup_data {\n\tstruct list_head list;\n\tconst char *provider;\n\tconst char *dev_id;\n\tconst char *con_id;\n};\n\nstruct led_pattern {\n\tu32 delta_t;\n\tint brightness;\n};\n\nstruct led_properties {\n\tu32 color;\n\tbool color_present;\n\tconst char *function;\n\tu32 func_enum;\n\tbool func_enum_present;\n\tconst char *label;\n};\n\nstruct led_pwm {\n\tconst char *name;\n\tu8 active_low;\n\tu8 default_state;\n\tunsigned int max_brightness;\n};\n\nstruct pwm_state {\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tbool usage_power;\n};\n\nstruct pwm_device;\n\nstruct led_pwm_data {\n\tstruct gpio_desc *enable_gpio;\n\tstruct led_classdev cdev;\n\tstruct pwm_device *pwm;\n\tlong: 32;\n\tstruct pwm_state pwmstate;\n\tunsigned int active_low;\n\tlong: 32;\n};\n\nstruct led_pwm_priv {\n\tint num_leds;\n\tlong: 32;\n\tstruct led_pwm_data leds[0];\n};\n\nstruct led_trigger_cpu {\n\tbool is_active;\n\tchar name[8];\n\tstruct led_trigger *_trig;\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linereq;\n\nstruct line {\n\tstruct gpio_desc *desc;\n\tstruct linereq *req;\n\tunsigned int irq;\n\tlong: 32;\n\tu64 edflags;\n\tu64 timestamp_ns;\n\tu32 req_seqno;\n\tu32 line_seqno;\n\tstruct delayed_work work;\n\tunsigned int sw_debounced;\n\tunsigned int level;\n\tlong: 32;\n};\n\nstruct linear_range {\n\tunsigned int min;\n\tunsigned int min_sel;\n\tunsigned int max_sel;\n\tunsigned int step;\n};\n\nstruct lineevent_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *desc;\n\tu32 eflags;\n\tint irq;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tlong: 32;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpioevent_data *type;\n\t\t\tconst struct gpioevent_data *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpioevent_data *ptr;\n\t\t\tconst struct gpioevent_data *ptr_const;\n\t\t};\n\t\tlong: 32;\n\t\tstruct gpioevent_data buf[16];\n\t} events;\n\tu64 timestamp;\n};\n\nstruct linehandle_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *descs[64];\n\tu32 num_descs;\n};\n\nstruct lineinfo_changed_ctx {\n\tstruct work_struct work;\n\tstruct gpio_v2_line_info_changed chg;\n\tstruct gpio_device *gdev;\n\tstruct gpio_chardev_data *cdev;\n};\n\nstruct linereq {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tu32 num_lines;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tu32 event_buffer_size;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_event *type;\n\t\t\tconst struct gpio_v2_line_event *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_event *ptr;\n\t\t\tconst struct gpio_v2_line_event *ptr_const;\n\t\t};\n\t\tlong: 32;\n\t\tstruct gpio_v2_line_event buf[0];\n\t} events;\n\tatomic_t seqno;\n\tstruct mutex config_mutex;\n\tstruct line lines[0];\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_capabilities {\n\tint speed;\n\tunsigned int duplex;\n\tlong unsigned int linkmodes[4];\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n\tlong: 32;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n\tlong: 32;\n};\n\nstruct linux_efi_initrd {\n\tlong unsigned int base;\n\tlong unsigned int size;\n};\n\nstruct linux_efi_memreserve {\n\tint size;\n\tatomic_t count;\n\tphys_addr_t next;\n\tstruct {\n\t\tphys_addr_t base;\n\t\tphys_addr_t size;\n\t} entry[0];\n};\n\nstruct linux_efi_random_seed {\n\tu32 size;\n\tu8 bits[0];\n};\n\nstruct linux_efi_tpm_eventlog {\n\tu32 size;\n\tu32 final_events_preboot_size;\n\tu8 version;\n\tu8 log[0];\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct lm90_data {\n\tstruct i2c_client *client;\n\tstruct device *hwmon_dev;\n\tu32 chip_config[2];\n\tu32 channel_config[4];\n\tconst char *channel_label[3];\n\tstruct hwmon_channel_info chip_info;\n\tstruct hwmon_channel_info temp_info;\n\tconst struct hwmon_channel_info *info[3];\n\tstruct hwmon_chip_info chip;\n\tstruct delayed_work alert_work;\n\tstruct work_struct report_work;\n\tbool valid;\n\tbool alarms_valid;\n\tlong unsigned int last_updated;\n\tlong unsigned int alarms_updated;\n\tint kind;\n\tu32 flags;\n\tunsigned int update_interval;\n\tu8 config;\n\tu8 config_orig;\n\tu8 convrate_orig;\n\tu8 resolution;\n\tu16 alert_alarms;\n\tu8 max_convrate;\n\tu8 reg_status2;\n\tu8 reg_local_ext;\n\tu8 reg_remote_ext;\n\tu8 faultqueue_mask;\n\tu8 faultqueue_depth;\n\tu16 temp[17];\n\tu8 temp_hyst;\n\tu8 conalert;\n\tu16 reported_alarms;\n\tu16 current_alarms;\n\tu16 alarms;\n};\n\nstruct lm90_params {\n\tu32 flags;\n\tu16 alert_alarms;\n\tu8 max_convrate;\n\tu8 resolution;\n\tu8 reg_status2;\n\tu8 reg_local_ext;\n\tu8 faultqueue_mask;\n\tu8 faultqueue_depth;\n};\n\nstruct lm95245_data {\n\tstruct regmap *regmap;\n\tint interval;\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf32_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf32_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct location;\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n\tlong: 32;\n\tloff_t idx;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct location {\n\tdepot_stack_handle_t handle;\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong unsigned int waste;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[1];\n\tnodemask_t nodes;\n};\n\nstruct lock_manager {\n\tstruct list_head list;\n\tbool block_opens;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct lockd_net {\n\tunsigned int nlmsvc_users;\n\tlong unsigned int next_gc;\n\tlong unsigned int nrhosts;\n\tu32 gracetime;\n\tu16 tcp_port;\n\tu16 udp_port;\n\tstruct delayed_work grace_period_end;\n\tstruct lock_manager lockd_manager;\n\tstruct list_head nsm_handles;\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tlong: 32;\n\tloff_t li_pos;\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct lookup_args {\n\tint offset;\n\tconst struct in6_addr *addr;\n};\n\nstruct loop_cmd {\n\tstruct list_head list_entry;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tlong: 32;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct cgroup_subsys_state *memcg_css;\n\tlong: 32;\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nstruct loop_device {\n\tint lo_number;\n\tlong: 32;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tchar lo_file_name[64];\n\tstruct file *lo_backing_file;\n\tunsigned int lo_min_dio_size;\n\tstruct block_device *lo_device;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tspinlock_t lo_work_lock;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rootcg_work;\n\tstruct list_head rootcg_cmd_list;\n\tstruct list_head idle_worker_list;\n\tstruct rb_root worker_tree;\n\tstruct timer_list timer;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n\tstruct mutex lo_mutex;\n\tbool idr_visible;\n\tlong: 32;\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_worker {\n\tstruct rb_node rb_node;\n\tstruct work_struct work;\n\tstruct list_head cmd_list;\n\tstruct list_head idle_list;\n\tstruct loop_device *lo;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tlong unsigned int last_ran_at;\n};\n\nunion lower_chunk {\n\tunion lower_chunk *next;\n\tlong unsigned int data[512];\n};\n\nstruct lp872x_platform_data;\n\nstruct lp872x {\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tenum lp872x_id chipid;\n\tstruct lp872x_platform_data *pdata;\n\tint num_regulators;\n\tenum gpiod_flags dvs_pin;\n};\n\nstruct lp872x_dvs {\n\tstruct gpio_desc *gpio;\n\tenum lp872x_dvs_sel vsel;\n\tenum gpiod_flags init_state;\n};\n\nstruct lp872x_regulator_data {\n\tenum lp872x_regulator_id id;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct lp872x_platform_data {\n\tu8 general_config;\n\tbool update_config;\n\tstruct lp872x_regulator_data regulator_data[9];\n\tstruct lp872x_dvs *dvs;\n\tstruct gpio_desc *enable_gpio;\n};\n\nstruct lpddr2_addressing {\n\tu32 num_banks;\n\tu32 tREFI_ns;\n\tu32 tRFCab_ps;\n};\n\nunion lpddr2_basic_config4 {\n\tu32 value;\n\tstruct {\n\t\tunsigned int arch_type: 2;\n\t\tunsigned int density: 4;\n\t\tunsigned int io_width: 2;\n\t} __attribute__((packed));\n};\n\nstruct lpddr2_info {\n\tint arch_type;\n\tint density;\n\tint io_width;\n\tint manufacturer_id;\n\tint revision_id1;\n\tint revision_id2;\n};\n\nstruct lpddr2_min_tck {\n\tu32 tRPab;\n\tu32 tRCD;\n\tu32 tWR;\n\tu32 tRASmin;\n\tu32 tRRD;\n\tu32 tWTR;\n\tu32 tXP;\n\tu32 tRTP;\n\tu32 tCKE;\n\tu32 tCKESR;\n\tu32 tFAW;\n};\n\nstruct lpddr2_timings {\n\tu32 max_freq;\n\tu32 min_freq;\n\tu32 tRPab;\n\tu32 tRCD;\n\tu32 tWR;\n\tu32 tRAS_min;\n\tu32 tRRD;\n\tu32 tWTR;\n\tu32 tXP;\n\tu32 tRTP;\n\tu32 tCKESR;\n\tu32 tDQSCK_max;\n\tu32 tDQSCK_max_derated;\n\tu32 tFAW;\n\tu32 tZQCS;\n\tu32 tZQCL;\n\tu32 tZQinit;\n\tu32 tRAS_max_ns;\n};\n\nstruct lpddr3_min_tck {\n\tu32 tRFC;\n\tu32 tRRD;\n\tu32 tRPab;\n\tu32 tRPpb;\n\tu32 tRCD;\n\tu32 tRC;\n\tu32 tRAS;\n\tu32 tWTR;\n\tu32 tWR;\n\tu32 tRTP;\n\tu32 tW2W_C2C;\n\tu32 tR2R_C2C;\n\tu32 tWL;\n\tu32 tDQSCK;\n\tu32 tRL;\n\tu32 tFAW;\n\tu32 tXSR;\n\tu32 tXP;\n\tu32 tCKE;\n\tu32 tCKESR;\n\tu32 tMRD;\n};\n\nstruct lpddr3_timings {\n\tu32 max_freq;\n\tu32 min_freq;\n\tu32 tRFC;\n\tu32 tRRD;\n\tu32 tRPab;\n\tu32 tRPpb;\n\tu32 tRCD;\n\tu32 tRC;\n\tu32 tRAS;\n\tu32 tWTR;\n\tu32 tWR;\n\tu32 tRTP;\n\tu32 tW2W_C2C;\n\tu32 tR2R_C2C;\n\tu32 tWL;\n\tu32 tDQSCK;\n\tu32 tRL;\n\tu32 tFAW;\n\tu32 tXSR;\n\tu32 tXP;\n\tu32 tCKE;\n\tu32 tCKESR;\n\tu32 tMRD;\n};\n\nstruct lpi_range {\n\tstruct list_head entry;\n\tu32 base_id;\n\tu32 span;\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n\tlong: 32;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct ubifs_nnode;\n\nstruct ubifs_pnode;\n\nstruct ubifs_cnode;\n\nstruct ubifs_nbranch {\n\tint lnum;\n\tint offs;\n\tunion {\n\t\tstruct ubifs_nnode *nnode;\n\t\tstruct ubifs_pnode *pnode;\n\t\tstruct ubifs_cnode *cnode;\n\t};\n};\n\nstruct ubifs_nnode {\n\tstruct ubifs_nnode *parent;\n\tstruct ubifs_cnode *cnext;\n\tlong unsigned int flags;\n\tint iip;\n\tint level;\n\tint num;\n\tstruct ubifs_nbranch nbranch[4];\n};\n\nstruct ubifs_lprops {\n\tint free;\n\tint dirty;\n\tint flags;\n\tint lnum;\n\tunion {\n\t\tstruct list_head list;\n\t\tint hpos;\n\t};\n};\n\nstruct ubifs_pnode {\n\tstruct ubifs_nnode *parent;\n\tstruct ubifs_cnode *cnext;\n\tlong unsigned int flags;\n\tint iip;\n\tint level;\n\tint num;\n\tstruct ubifs_lprops lprops[4];\n};\n\nstruct ubifs_cnode {\n\tstruct ubifs_nnode *parent;\n\tstruct ubifs_cnode *cnext;\n\tlong unsigned int flags;\n\tint iip;\n\tint level;\n\tint num;\n};\n\nstruct lpt_scan_node {\n\tunion {\n\t\tstruct ubifs_nnode nnode;\n\t\tstruct ubifs_pnode pnode;\n\t\tstruct ubifs_cnode cnode;\n\t};\n\tint in_tree;\n\tunion {\n\t\tstruct ubifs_nnode *nnode;\n\t\tstruct ubifs_pnode *pnode;\n\t\tstruct ubifs_cnode *cnode;\n\t} ptr;\n};\n\nstruct lpuart_port {\n\tstruct uart_port port;\n\tenum lpuart_type devtype;\n\tstruct clk *ipg_clk;\n\tstruct clk *baud_clk;\n\tunsigned int txfifo_size;\n\tunsigned int rxfifo_size;\n\tu8 rx_watermark;\n\tbool lpuart_dma_tx_use;\n\tbool lpuart_dma_rx_use;\n\tstruct dma_chan *dma_tx_chan;\n\tstruct dma_chan *dma_rx_chan;\n\tstruct dma_async_tx_descriptor *dma_tx_desc;\n\tstruct dma_async_tx_descriptor *dma_rx_desc;\n\tdma_cookie_t dma_tx_cookie;\n\tdma_cookie_t dma_rx_cookie;\n\tunsigned int dma_tx_bytes;\n\tunsigned int dma_rx_bytes;\n\tbool dma_tx_in_progress;\n\tunsigned int dma_rx_timeout;\n\tstruct timer_list lpuart_timer;\n\tstruct scatterlist rx_sgl;\n\tstruct scatterlist tx_sgl[2];\n\tstruct circ_buf rx_ring;\n\tint rx_dma_rng_buf_len;\n\tint last_residue;\n\tunsigned int dma_tx_nents;\n\twait_queue_head_t dma_wait;\n\tbool is_cs7;\n\tbool dma_idle_int;\n};\n\nstruct lpuart_soc_data {\n\tenum lpuart_type devtype;\n\tchar iotype;\n\tu8 reg_off;\n\tu8 rx_watermark;\n};\n\nstruct zswap_lruvec_state {};\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct ls_extirq_data {\n\tvoid *intpcr;\n\traw_spinlock_t lock;\n\tbool big_endian;\n\tbool is_ls1021a_or_ls1043a;\n\tu32 nirq;\n\tstruct irq_fwspec map[12];\n};\n\nstruct ls_pcie_drvdata;\n\nstruct ls_pcie {\n\tstruct dw_pcie *pci;\n\tconst struct ls_pcie_drvdata *drvdata;\n\tvoid *pf_lut_base;\n\tstruct regmap *scfg;\n\tint index;\n\tbool big_endian;\n};\n\nstruct ls_pcie_drvdata {\n\tconst u32 pf_lut_off;\n\tconst struct dw_pcie_host_ops *ops;\n\tint (*exit_from_l2)(struct dw_pcie_rp *);\n\tbool scfg_support;\n\tbool pm_support;\n};\n\nstruct ls_scfg_msi_cfg;\n\nstruct ls_scfg_msir;\n\nstruct ls_scfg_msi {\n\tspinlock_t lock;\n\tstruct platform_device *pdev;\n\tstruct irq_domain *parent;\n\tvoid *regs;\n\tphys_addr_t msiir_addr;\n\tstruct ls_scfg_msi_cfg *cfg;\n\tu32 msir_num;\n\tstruct ls_scfg_msir *msir;\n\tu32 irqs_num;\n\tlong unsigned int *used;\n};\n\nstruct ls_scfg_msi_cfg {\n\tu32 ibs_shift;\n\tu32 msir_irqs;\n\tu32 msir_base;\n};\n\nstruct ls_scfg_msir {\n\tstruct ls_scfg_msi *msi_data;\n\tunsigned int index;\n\tunsigned int gic_irq;\n\tunsigned int bit_start;\n\tunsigned int bit_end;\n\tunsigned int srs;\n\tvoid *reg;\n};\n\nstruct skcipher_alg_common {\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int statesize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct lskcipher_alg {\n\tint (*setkey)(struct crypto_lskcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*decrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*init)(struct crypto_lskcipher *);\n\tvoid (*exit)(struct crypto_lskcipher *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct skcipher_alg_common co;\n};\n\nstruct lskcipher_instance {\n\tvoid (*free)(struct lskcipher_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct lskcipher_alg alg;\n\t};\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwq_node {\n\tstruct llist_node node;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lynx_pcs {\n\tstruct phylink_pcs pcs;\n\tstruct mdio_device *mdio;\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct lznt_hash {\n\tconst u8 *p1;\n\tconst u8 *p2;\n};\n\nstruct lznt {\n\tconst u8 *unc;\n\tconst u8 *unc_end;\n\tconst u8 *best_match;\n\tsize_t max_len;\n\tbool std;\n\tstruct lznt_hash hash[4096];\n};\n\nstruct m10v_clk_div_factors {\n\tconst char *name;\n\tconst char *parent_name;\n\tu32 offset;\n\tu8 shift;\n\tu8 width;\n\tconst struct clk_div_table *table;\n\tlong unsigned int div_flags;\n\tint onecell_idx;\n};\n\nstruct m10v_clk_div_fixed_data {\n\tconst char *name;\n\tconst char *parent_name;\n\tu8 div;\n\tu8 mult;\n\tint onecell_idx;\n};\n\nstruct m10v_clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n\tvoid *write_valid_reg;\n};\n\nstruct m10v_clk_mux_factors {\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tu32 offset;\n\tu8 shift;\n\tu8 mask;\n\tu32 *table;\n\tlong unsigned int mux_flags;\n\tint onecell_idx;\n};\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct mii_regs {\n\tunsigned int addr;\n\tunsigned int data;\n\tunsigned int addr_shift;\n\tunsigned int reg_shift;\n\tunsigned int addr_mask;\n\tunsigned int reg_mask;\n\tunsigned int clk_csr_shift;\n\tunsigned int clk_csr_mask;\n};\n\nstruct mac_link {\n\tu32 caps;\n\tu32 speed_mask;\n\tu32 speed10;\n\tu32 speed100;\n\tu32 speed1000;\n\tu32 speed2500;\n\tu32 duplex;\n\tstruct {\n\t\tu32 speed2500;\n\t\tu32 speed5000;\n\t\tu32 speed10000;\n\t} xgmii;\n\tstruct {\n\t\tu32 speed25000;\n\t\tu32 speed40000;\n\t\tu32 speed50000;\n\t\tu32 speed100000;\n\t} xlgmii;\n};\n\nstruct stmmac_ops;\n\nstruct stmmac_desc_ops;\n\nstruct stmmac_dma_ops;\n\nstruct stmmac_mode_ops;\n\nstruct stmmac_hwtimestamp;\n\nstruct stmmac_tc_ops;\n\nstruct stmmac_mmc_ops;\n\nstruct stmmac_est_ops;\n\nstruct stmmac_vlan_ops;\n\nstruct mac_device_info {\n\tconst struct stmmac_ops *mac;\n\tconst struct stmmac_desc_ops *desc;\n\tconst struct stmmac_dma_ops *dma;\n\tconst struct stmmac_mode_ops *mode;\n\tconst struct stmmac_hwtimestamp *ptp;\n\tconst struct stmmac_tc_ops *tc;\n\tconst struct stmmac_mmc_ops *mmc;\n\tconst struct stmmac_est_ops *est;\n\tconst struct stmmac_vlan_ops *vlan;\n\tstruct dw_xpcs *xpcs;\n\tstruct phylink_pcs *phylink_pcs;\n\tstruct mii_regs mii;\n\tstruct mac_link link;\n\tvoid *pcsr;\n\tunsigned int multicast_filter_bins;\n\tunsigned int unicast_filter_entries;\n\tunsigned int mcast_bits_log2;\n\tunsigned int rx_csum;\n\tunsigned int pcs;\n\tunsigned int xlgmac;\n\tunsigned int num_vlan;\n\tu32 vlan_filter[32];\n\tbool vlan_fail_q_en;\n\tu8 vlan_fail_q;\n\tbool hw_vlan_en;\n\tbool reverse_sgmii_enable;\n\tspinlock_t irq_ctrl_lock;\n};\n\nstruct queue_stats {\n\tunion {\n\t\tlong unsigned int first;\n\t\tlong unsigned int rx_packets;\n\t};\n\tlong unsigned int rx_bytes;\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_packets;\n\tlong unsigned int tx_bytes;\n\tlong unsigned int tx_dropped;\n};\n\nstruct macb;\n\nstruct macb_dma_desc;\n\nstruct macb_tx_skb;\n\nstruct macb_queue {\n\tstruct macb *bp;\n\tint irq;\n\tunsigned int ISR;\n\tunsigned int IER;\n\tunsigned int IDR;\n\tunsigned int IMR;\n\tunsigned int TBQP;\n\tunsigned int RBQS;\n\tunsigned int RBQP;\n\tunsigned int ENST_START_TIME;\n\tunsigned int ENST_ON_TIME;\n\tunsigned int ENST_OFF_TIME;\n\tspinlock_t tx_ptr_lock;\n\tunsigned int tx_head;\n\tunsigned int tx_tail;\n\tstruct macb_dma_desc *tx_ring;\n\tstruct macb_tx_skb *tx_skb;\n\tdma_addr_t tx_ring_dma;\n\tstruct work_struct tx_error_task;\n\tbool txubr_pending;\n\tlong: 32;\n\tstruct napi_struct napi_tx;\n\tdma_addr_t rx_ring_dma;\n\tdma_addr_t rx_buffers_dma;\n\tunsigned int rx_tail;\n\tunsigned int rx_prepared_head;\n\tstruct macb_dma_desc *rx_ring;\n\tstruct sk_buff **rx_skbuff;\n\tvoid *rx_buffers;\n\tlong: 32;\n\tstruct napi_struct napi_rx;\n\tstruct queue_stats stats;\n};\n\nstruct macb_stats {\n\tu64 rx_pause_frames;\n\tu64 tx_ok;\n\tu64 tx_single_cols;\n\tu64 tx_multiple_cols;\n\tu64 rx_ok;\n\tu64 rx_fcs_errors;\n\tu64 rx_align_errors;\n\tu64 tx_deferred;\n\tu64 tx_late_cols;\n\tu64 tx_excessive_cols;\n\tu64 tx_underruns;\n\tu64 tx_carrier_errors;\n\tu64 rx_resource_errors;\n\tu64 rx_overruns;\n\tu64 rx_symbol_errors;\n\tu64 rx_oversize_pkts;\n\tu64 rx_jabbers;\n\tu64 rx_undersize_pkts;\n\tu64 sqe_test_errors;\n\tu64 rx_length_mismatch;\n\tu64 tx_pause_frames;\n};\n\nstruct macb_or_gem_ops {\n\tint (*mog_alloc_rx_buffers)(struct macb *);\n\tvoid (*mog_free_rx_buffers)(struct macb *);\n\tvoid (*mog_init_rings)(struct macb *);\n\tint (*mog_rx)(struct macb_queue *, struct napi_struct *, int);\n};\n\nstruct macb_tx_skb {\n\tstruct sk_buff *skb;\n\tdma_addr_t mapping;\n\tsize_t size;\n\tbool mapped_as_page;\n};\n\nstruct tsu_incr {\n\tu32 sub_ns;\n\tu32 ns;\n};\n\nstruct macb_pm_data {\n\tu32 scrt2;\n\tu32 usrio;\n};\n\nstruct macb_ptp_info;\n\nstruct macb_usrio_config;\n\nstruct macb {\n\tvoid *regs;\n\tbool native_io;\n\tu32 (*macb_reg_readl)(struct macb *, int);\n\tvoid (*macb_reg_writel)(struct macb *, int, u32);\n\tstruct macb_dma_desc *rx_ring_tieoff;\n\tdma_addr_t rx_ring_tieoff_dma;\n\tsize_t rx_buffer_size;\n\tunsigned int rx_ring_size;\n\tunsigned int tx_ring_size;\n\tunsigned int num_queues;\n\tstruct macb_queue queues[8];\n\tspinlock_t lock;\n\tstruct platform_device *pdev;\n\tstruct clk *pclk;\n\tstruct clk *hclk;\n\tstruct clk *tx_clk;\n\tstruct clk *rx_clk;\n\tstruct clk *tsu_clk;\n\tstruct net_device *dev;\n\tspinlock_t stats_lock;\n\tlong: 32;\n\tunion {\n\t\tstruct macb_stats macb;\n\t\tstruct gem_stats gem;\n\t} hw_stats;\n\tstruct macb_or_gem_ops macbgem_ops;\n\tstruct mii_bus *mii_bus;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tstruct phylink_pcs phylink_usx_pcs;\n\tstruct phylink_pcs phylink_sgmii_pcs;\n\tu32 caps;\n\tunsigned int dma_burst_length;\n\tphy_interface_t phy_interface;\n\tstruct macb_tx_skb rm9200_txq[2];\n\tunsigned int max_tx_length;\n\tu64 ethtool_stats[91];\n\tunsigned int rx_frm_len_mask;\n\tunsigned int jumbo_max_len;\n\tu32 wol;\n\tu32 wolopts;\n\tu32 rx_watermark;\n\tstruct macb_ptp_info *ptp_info;\n\tstruct phy *phy;\n\tspinlock_t tsu_clk_lock;\n\tunsigned int tsu_rate;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct tsu_incr tsu_incr;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tstruct ethtool_rx_fs_list rx_fs_list;\n\tspinlock_t rx_fs_lock;\n\tunsigned int max_tuples;\n\tstruct work_struct hresp_err_bh_work;\n\tint rx_bd_rd_prefetch;\n\tint tx_bd_rd_prefetch;\n\tu32 rx_intr_mask;\n\tstruct macb_pm_data pm_data;\n\tconst struct macb_usrio_config *usrio;\n};\n\nstruct macb_config {\n\tu32 caps;\n\tunsigned int dma_burst_length;\n\tint (*clk_init)(struct platform_device *, struct clk **, struct clk **, struct clk **, struct clk **, struct clk **);\n\tint (*init)(struct platform_device *);\n\tunsigned int max_tx_length;\n\tint jumbo_max_len;\n\tconst struct macb_usrio_config *usrio;\n};\n\nstruct macb_dma_desc {\n\tu32 addr;\n\tu32 ctrl;\n};\n\nstruct macb_dma_desc_64 {\n\tu32 addrh;\n\tu32 resvd;\n};\n\nstruct macb_dma_desc_ptp {\n\tu32 ts_1;\n\tu32 ts_2;\n};\n\nstruct macb_platform_data {\n\tstruct clk *pclk;\n\tstruct clk *hclk;\n};\n\nstruct macb_ptp_info {\n\tvoid (*ptp_init)(struct net_device *);\n\tvoid (*ptp_remove)(struct net_device *);\n\ts32 (*get_ptp_max_adj)(void);\n\tunsigned int (*get_tsu_rate)(struct macb *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tint (*get_hwtst)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*set_hwtst)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct macb_queue_enst_config {\n\tu32 start_time_mask;\n\tu32 on_time_bytes;\n\tu32 off_time_bytes;\n\tu8 queue_id;\n};\n\nstruct macb_usrio_config {\n\tu32 mii;\n\tu32 rmii;\n\tu32 rgmii;\n\tu32 refclk;\n\tu32 hdfctlen;\n};\n\nstruct smp_operations;\n\nstruct tag;\n\nstruct machine_desc {\n\tunsigned int nr;\n\tconst char *name;\n\tlong unsigned int atag_offset;\n\tconst char * const *dt_compat;\n\tunsigned int nr_irqs;\n\tphys_addr_t dma_zone_size;\n\tunsigned int video_start;\n\tunsigned int video_end;\n\tunsigned char reserve_lp0: 1;\n\tunsigned char reserve_lp1: 1;\n\tunsigned char reserve_lp2: 1;\n\tenum reboot_mode reboot_mode;\n\tunsigned int l2c_aux_val;\n\tunsigned int l2c_aux_mask;\n\tvoid (*l2c_write_sec)(long unsigned int, unsigned int);\n\tconst struct smp_operations *smp;\n\tbool (*smp_init)(void);\n\tvoid (*fixup)(struct tag *, char **);\n\tvoid (*dt_fixup)(void);\n\tlong long int (*pv_fixup)(void);\n\tvoid (*reserve)(void);\n\tvoid (*map_io)(void);\n\tvoid (*init_early)(void);\n\tvoid (*init_irq)(void);\n\tvoid (*init_time)(void);\n\tvoid (*init_machine)(void);\n\tvoid (*init_late)(void);\n\tvoid (*restart)(enum reboot_mode, const char *);\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct mafield {\n\tconst char *prefix;\n\tint field;\n};\n\nstruct map_desc {\n\tlong unsigned int virtual;\n\tlong unsigned int pfn;\n\tlong unsigned int length;\n\tunsigned int type;\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct mtd_chip_driver;\n\nstruct map_info {\n\tconst char *name;\n\tlong unsigned int size;\n\tresource_size_t phys;\n\tvoid *virt;\n\tvoid *cached;\n\tint swap;\n\tint bankwidth;\n\tvoid (*inval_cache)(struct map_info *, long unsigned int, ssize_t);\n\tvoid (*set_vpp)(struct map_info *, int);\n\tlong unsigned int pfow_base;\n\tlong unsigned int map_priv_1;\n\tlong unsigned int map_priv_2;\n\tstruct device_node *device_node;\n\tvoid *fldrv_priv;\n\tstruct mtd_chip_driver *fldrv;\n};\n\nstruct map_info___2 {\n\tstruct map_info___2 *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[20];\n\tvoid *slot[21];\n\tlong unsigned int gap[21];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[65];\n\tunion {\n\t\tstruct maple_enode *slot[66];\n\t\tstruct {\n\t\t\tlong unsigned int padding[43];\n\t\t\tlong unsigned int gap[43];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[31];\n\tunion {\n\t\tvoid *slot[32];\n\t\tstruct {\n\t\t\tvoid *pad[31];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[63];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct marvell_hw_ecc_layout {\n\tint writesize;\n\tint chunk;\n\tint strength;\n\tint nchunks;\n\tint full_chunk_cnt;\n\tint data_bytes;\n\tint spare_bytes;\n\tint ecc_bytes;\n\tint last_data_bytes;\n\tint last_spare_bytes;\n\tint last_ecc_bytes;\n};\n\nstruct marvell_hw_stat {\n\tconst char *string;\n\tu8 page;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct marvell_hw_stat_simple {\n\tconst char *string;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct marvell_hwmon_ops {\n\tint (*config)(struct phy_device *);\n\tint (*get_temp)(struct phy_device *, long int *);\n\tint (*get_temp_critical)(struct phy_device *, long int *);\n\tint (*set_temp_critical)(struct phy_device *, long int);\n\tint (*get_temp_alarm)(struct phy_device *, long int *);\n};\n\nstruct marvell_led_rules {\n\tint mode;\n\tlong unsigned int rules;\n};\n\nstruct marvell_nand_chip_sel {\n\tunsigned int cs;\n\tu32 ndcb0_csel;\n\tunsigned int rb;\n};\n\nstruct marvell_nand_chip {\n\tstruct nand_chip chip;\n\tstruct list_head node;\n\tconst struct marvell_hw_ecc_layout *layout;\n\tu32 ndcr;\n\tu32 ndtr0;\n\tu32 ndtr1;\n\tint addr_cyc;\n\tint selected_die;\n\tunsigned int nsels;\n\tstruct marvell_nand_chip_sel sels[0];\n\tlong: 32;\n};\n\nstruct marvell_nfc_caps;\n\nstruct marvell_nfc {\n\tstruct nand_controller controller;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct clk *core_clk;\n\tstruct clk *reg_clk;\n\tstruct completion complete;\n\tlong unsigned int assigned_cs;\n\tstruct list_head chips;\n\tstruct nand_chip *selected_chip;\n\tconst struct marvell_nfc_caps *caps;\n\tbool use_dma;\n\tstruct dma_chan *dma_chan;\n\tu8 *dma_buf;\n};\n\nstruct marvell_nfc_caps {\n\tunsigned int max_cs_nb;\n\tunsigned int max_rb_nb;\n\tbool need_system_controller;\n\tbool legacy_of_bindings;\n\tbool is_nfcv2;\n\tbool use_dma;\n\tunsigned int max_mode_number;\n};\n\nstruct nand_op_instr;\n\nstruct marvell_nfc_op {\n\tu32 ndcb[4];\n\tunsigned int cle_ale_delay_ns;\n\tunsigned int rdy_timeout_ms;\n\tunsigned int rdy_delay_ns;\n\tunsigned int data_delay_ns;\n\tunsigned int data_instr_idx;\n\tconst struct nand_op_instr *data_instr;\n};\n\nstruct marvell_nfc_timings {\n\tunsigned int tRP;\n\tunsigned int tRH;\n\tunsigned int tWP;\n\tunsigned int tWH;\n\tunsigned int tCS;\n\tunsigned int tCH;\n\tunsigned int tADL;\n\tunsigned int tAR;\n\tunsigned int tWHR;\n\tunsigned int tRHW;\n\tunsigned int tR;\n};\n\nstruct marvell_priv {\n\tu64 stats[3];\n\tchar *hwmon_name;\n\tstruct device *hwmon_dev;\n\tbool cable_test_tdr;\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n\tu8 vct_phase;\n\tlong: 32;\n};\n\nstruct tee_ioctl_version_data;\n\nstruct match_dev_data {\n\tstruct tee_ioctl_version_data *vers;\n\tconst void *data;\n\tint (*match)(struct tee_ioctl_version_data *, const void *);\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct matrix_keymap_data {\n\tconst uint32_t *keymap;\n\tunsigned int keymap_size;\n};\n\nstruct max14577 {\n\tstruct device *dev;\n\tstruct i2c_client *i2c;\n\tstruct i2c_client *i2c_pmic;\n\tenum maxim_device_type dev_type;\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_pmic;\n\tstruct regmap_irq_chip_data *irq_data;\n\tstruct regmap_irq_chip_data *irq_data_pmic;\n\tint irq;\n};\n\nstruct max14577_regulator_platform_data;\n\nstruct max14577_platform_data {\n\tint irq_base;\n\tint gpio_pogo_vbatt_en;\n\tint gpio_pogo_vbus_en;\n\tint (*set_gpio_pogo_vbatt_en)(int);\n\tint (*set_gpio_pogo_vbus_en)(int);\n\tint (*set_gpio_pogo_cb)(int);\n\tstruct max14577_regulator_platform_data *regulators;\n};\n\nstruct max14577_regulator_platform_data {\n\tint id;\n\tstruct regulator_init_data *initdata;\n\tstruct device_node *of_node;\n};\n\nstruct max77686_clk_init_data;\n\nstruct max77686_clk_driver_data {\n\tenum max77686_chip_name chip;\n\tstruct max77686_clk_init_data *max_clk_data;\n\tsize_t num_clks;\n};\n\nstruct max77686_hw_clk_info;\n\nstruct max77686_clk_init_data {\n\tstruct regmap *regmap;\n\tstruct clk_hw hw;\n\tstruct clk_init_data clk_idata;\n\tconst struct max77686_hw_clk_info *clk_info;\n};\n\nstruct max77686_data {\n\tstruct device *dev;\n\tlong unsigned int gpio_enabled[2];\n\tunsigned int opmode[35];\n};\n\nstruct max77686_dev {\n\tstruct device *dev;\n\tstruct i2c_client *i2c;\n\tlong unsigned int type;\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip_data *irq_data;\n\tint irq;\n\tstruct mutex irqlock;\n\tint irq_masks_cur[3];\n\tint irq_masks_cache[3];\n};\n\nstruct max77686_hw_clk_info {\n\tconst char *name;\n\tu32 clk_reg;\n\tu32 clk_enable_mask;\n\tu32 flags;\n};\n\nstruct max77686_rtc_driver_data {\n\tlong unsigned int delay;\n\tu8 mask;\n\tconst unsigned int *map;\n\tbool alarm_enable_reg;\n\tint rtc_i2c_addr;\n\tbool rtc_irq_from_platform;\n\tint alarm_pending_status_reg;\n\tconst struct regmap_irq_chip *rtc_irq_chip;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct max77686_rtc_info {\n\tstruct device *dev;\n\tstruct rtc_device *rtc_dev;\n\tstruct mutex lock;\n\tstruct regmap *regmap;\n\tstruct regmap *rtc_regmap;\n\tconst struct max77686_rtc_driver_data *drv_data;\n\tstruct regmap_irq_chip_data *rtc_irq_data;\n\tint rtc_irq;\n\tint virq;\n};\n\nstruct max77802_regulator_prv {\n\tunsigned int opmode[42];\n};\n\nstruct max8907 {\n\tstruct device *dev;\n\tstruct mutex irq_lock;\n\tstruct i2c_client *i2c_gen;\n\tstruct i2c_client *i2c_rtc;\n\tstruct regmap *regmap_gen;\n\tstruct regmap *regmap_rtc;\n\tstruct regmap_irq_chip_data *irqc_chg;\n\tstruct regmap_irq_chip_data *irqc_on_off;\n\tstruct regmap_irq_chip_data *irqc_rtc;\n};\n\nstruct max8907_platform_data {\n\tstruct regulator_init_data *init_data[29];\n\tbool pm_off;\n};\n\nstruct max8907_regulator {\n\tstruct regulator_desc desc[29];\n};\n\nstruct max8907_rtc {\n\tstruct max8907 *max8907;\n\tstruct regmap *regmap;\n\tstruct rtc_device *rtc_dev;\n\tint irq;\n};\n\nstruct regulator_ops {\n\tint (*list_voltage)(struct regulator_dev *, unsigned int);\n\tint (*set_voltage)(struct regulator_dev *, int, int, unsigned int *);\n\tint (*map_voltage)(struct regulator_dev *, int, int);\n\tint (*set_voltage_sel)(struct regulator_dev *, unsigned int);\n\tint (*get_voltage)(struct regulator_dev *);\n\tint (*get_voltage_sel)(struct regulator_dev *);\n\tint (*set_current_limit)(struct regulator_dev *, int, int);\n\tint (*get_current_limit)(struct regulator_dev *);\n\tint (*set_input_current_limit)(struct regulator_dev *, int);\n\tint (*set_over_current_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_over_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_under_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_thermal_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_active_discharge)(struct regulator_dev *, bool);\n\tint (*enable)(struct regulator_dev *);\n\tint (*disable)(struct regulator_dev *);\n\tint (*is_enabled)(struct regulator_dev *);\n\tint (*set_mode)(struct regulator_dev *, unsigned int);\n\tunsigned int (*get_mode)(struct regulator_dev *);\n\tint (*get_error_flags)(struct regulator_dev *, unsigned int *);\n\tint (*enable_time)(struct regulator_dev *);\n\tint (*set_ramp_delay)(struct regulator_dev *, int);\n\tint (*set_voltage_time)(struct regulator_dev *, int, int);\n\tint (*set_voltage_time_sel)(struct regulator_dev *, unsigned int, unsigned int);\n\tint (*set_soft_start)(struct regulator_dev *);\n\tint (*get_status)(struct regulator_dev *);\n\tunsigned int (*get_optimum_mode)(struct regulator_dev *, int, int, int);\n\tint (*set_load)(struct regulator_dev *, int);\n\tint (*set_bypass)(struct regulator_dev *, bool);\n\tint (*get_bypass)(struct regulator_dev *, bool *);\n\tint (*set_suspend_voltage)(struct regulator_dev *, int);\n\tint (*set_suspend_enable)(struct regulator_dev *);\n\tint (*set_suspend_disable)(struct regulator_dev *);\n\tint (*set_suspend_mode)(struct regulator_dev *, unsigned int);\n\tint (*resume)(struct regulator_dev *);\n\tint (*set_pull_down)(struct regulator_dev *);\n};\n\nstruct max8973_chip {\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct regmap *regmap;\n\tbool enable_external_control;\n\tstruct gpio_desc *dvs_gpiod;\n\tint lru_index[2];\n\tint curr_vout_val[2];\n\tint curr_vout_reg;\n\tint curr_gpio_val;\n\tstruct regulator_ops ops;\n\tenum device_id id;\n\tint junction_temp_warning;\n\tint irq;\n\tstruct thermal_zone_device *tz_device;\n};\n\nstruct max8973_regulator_platform_data {\n\tstruct regulator_init_data *reg_init_data;\n\tlong unsigned int control_flags;\n\tlong unsigned int junction_temp_warning;\n\tbool enable_ext_control;\n\tunsigned int dvs_def_state: 1;\n};\n\nstruct max8997_platform_data;\n\nstruct max8997_dev {\n\tstruct device *dev;\n\tstruct max8997_platform_data *pdata;\n\tstruct i2c_client *i2c;\n\tstruct i2c_client *rtc;\n\tstruct i2c_client *haptic;\n\tstruct i2c_client *muic;\n\tstruct mutex iolock;\n\tlong unsigned int type;\n\tstruct platform_device *battery;\n\tint irq;\n\tint ono;\n\tstruct irq_domain *irq_domain;\n\tstruct mutex irqlock;\n\tint irq_masks_cur[11];\n\tint irq_masks_cache[11];\n\tu8 reg_dump[187];\n\tbool gpio_status[12];\n};\n\nstruct max8997_haptic_platform_data {\n\tunsigned int pwm_period;\n\tenum max8997_haptic_motor_type type;\n\tenum max8997_haptic_pulse_mode mode;\n\tenum max8997_haptic_pwm_divisor pwm_divisor;\n\tunsigned int internal_mode_pattern;\n\tunsigned int pattern_cycle;\n\tunsigned int pattern_signal_period;\n};\n\nstruct max8997_irq_data {\n\tint mask;\n\tenum max8997_irq_source group;\n};\n\nstruct max8997_led_platform_data {\n\tenum max8997_led_mode mode[2];\n\tu8 brightness[2];\n};\n\nstruct max8997_muic_reg_data;\n\nstruct max8997_muic_platform_data {\n\tstruct max8997_muic_reg_data *init_data;\n\tint num_init_data;\n\tint detcable_delay_ms;\n\tint path_usb;\n\tint path_uart;\n};\n\nstruct max8997_muic_reg_data {\n\tu8 addr;\n\tu8 data;\n};\n\nstruct max8997_regulator_data;\n\nstruct max8997_platform_data {\n\tint ono;\n\tstruct max8997_regulator_data *regulators;\n\tint num_regulators;\n\tbool ignore_gpiodvs_side_effect;\n\tint buck125_default_idx;\n\tunsigned int buck1_voltage[8];\n\tbool buck1_gpiodvs;\n\tunsigned int buck2_voltage[8];\n\tbool buck2_gpiodvs;\n\tunsigned int buck5_voltage[8];\n\tbool buck5_gpiodvs;\n\tint eoc_mA;\n\tint timeout;\n\tstruct max8997_muic_platform_data *muic_pdata;\n\tstruct max8997_haptic_platform_data *haptic_pdata;\n\tstruct max8997_led_platform_data *led_pdata;\n};\n\nstruct max8997_regulator_data {\n\tint id;\n\tstruct regulator_init_data *initdata;\n\tstruct device_node *reg_node;\n};\n\nstruct max8998_platform_data;\n\nstruct max8998_dev {\n\tstruct device *dev;\n\tstruct max8998_platform_data *pdata;\n\tstruct i2c_client *i2c;\n\tstruct i2c_client *rtc;\n\tstruct mutex iolock;\n\tstruct mutex irqlock;\n\tunsigned int irq_base;\n\tstruct irq_domain *irq_domain;\n\tint irq;\n\tint ono;\n\tu8 irq_masks_cur[4];\n\tu8 irq_masks_cache[4];\n\tlong unsigned int type;\n\tbool wakeup;\n};\n\nstruct max8998_irq_data {\n\tint reg;\n\tint mask;\n};\n\nstruct max8998_regulator_data;\n\nstruct max8998_platform_data {\n\tstruct max8998_regulator_data *regulators;\n\tint num_regulators;\n\tunsigned int irq_base;\n\tint ono;\n\tbool buck_voltage_lock;\n\tint buck1_voltage[4];\n\tint buck2_voltage[2];\n\tint buck1_default_idx;\n\tint buck2_default_idx;\n\tbool wakeup;\n\tbool rtc_delay;\n\tint eoc;\n\tint restart;\n\tint timeout;\n};\n\nstruct max8998_reg_dump {\n\tu8 addr;\n\tu8 val;\n};\n\nstruct max8998_regulator_data {\n\tint id;\n\tstruct regulator_init_data *initdata;\n\tstruct device_node *reg_node;\n};\n\nstruct maxim_charger_current {\n\tunsigned int min;\n\tunsigned int high_start;\n\tunsigned int high_step;\n\tunsigned int max;\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker *c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tlong unsigned int e_flags;\n\tlong: 32;\n\tu64 e_value;\n};\n\nstruct mbi_range {\n\tu32 spi_start;\n\tu32 nr_spis;\n\tlong unsigned int *bm;\n};\n\nstruct mbox_chan_ops {\n\tint (*send_data)(struct mbox_chan *, void *);\n\tint (*flush)(struct mbox_chan *, long unsigned int);\n\tint (*startup)(struct mbox_chan *);\n\tvoid (*shutdown)(struct mbox_chan *);\n\tbool (*last_tx_done)(struct mbox_chan *);\n\tbool (*peek_data)(struct mbox_chan *);\n};\n\nstruct mbus_dram_window {\n\tu8 cs_index;\n\tu8 mbus_attr;\n\tlong: 32;\n\tu64 base;\n\tu64 size;\n};\n\nstruct mbus_dram_target_info {\n\tu8 mbus_dram_target_id;\n\tint num_cs;\n\tstruct mbus_dram_window cs[4];\n};\n\nstruct mc_subled {\n\tunsigned int color_index;\n\tunsigned int brightness;\n\tunsigned int intensity;\n\tunsigned int channel;\n};\n\nstruct mchp_pit64b_timer {\n\tvoid *base;\n\tstruct clk *pclk;\n\tstruct clk *gclk;\n\tu32 mode;\n};\n\nstruct mchp_pit64b_clkevt {\n\tstruct mchp_pit64b_timer timer;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device clkevt;\n};\n\nstruct mchp_pit64b_clksrc {\n\tstruct mchp_pit64b_timer timer;\n\tstruct clocksource clksrc;\n};\n\nstruct reset_props;\n\nstruct mchp_reset_context {\n\tstruct regmap *cpu_ctrl;\n\tstruct regmap *gcb_ctrl;\n\tstruct reset_controller_dev rcdev;\n\tconst struct reset_props *props;\n};\n\nstruct mcp251x_priv {\n\tstruct can_priv can;\n\tstruct net_device *net;\n\tstruct spi_device *spi;\n\tenum mcp251x_model model;\n\tstruct mutex mcp_lock;\n\tu8 *spi_tx_buf;\n\tu8 *spi_rx_buf;\n\tstruct sk_buff *tx_skb;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct tx_work;\n\tstruct work_struct restart_work;\n\tint force_quit;\n\tint after_suspend;\n\tint restart_tx;\n\tbool tx_busy;\n\tstruct regulator *power;\n\tstruct regulator *transceiver;\n\tstruct clk *clk;\n\tstruct gpio_chip gpio;\n\tu8 reg_bfpctrl;\n};\n\nstruct mcpm_platform_ops {\n\tint (*cpu_powerup)(unsigned int, unsigned int);\n\tint (*cluster_powerup)(unsigned int);\n\tvoid (*cpu_suspend_prepare)(unsigned int, unsigned int);\n\tvoid (*cpu_powerdown_prepare)(unsigned int, unsigned int);\n\tvoid (*cluster_powerdown_prepare)(unsigned int);\n\tvoid (*cpu_cache_disable)(void);\n\tvoid (*cluster_cache_disable)(void);\n\tvoid (*cpu_is_up)(unsigned int, unsigned int);\n\tvoid (*cluster_is_up)(unsigned int);\n\tint (*wait_for_powerdown)(unsigned int, unsigned int);\n};\n\nstruct mcpm_sync_struct {\n\tstruct {\n\t\ts8 cpu;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t} cpus[4];\n\ts8 cluster;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\ts8 inbound;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mct_clock_event_device {\n\tstruct clock_event_device evt;\n\tlong unsigned int base;\n\tchar name[11];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mctrl_gpios {\n\tstruct uart_port *port;\n\tstruct gpio_desc *gpio[6];\n\tint irq[6];\n\tunsigned int mctrl_prev;\n\tbool mctrl_on;\n};\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n\tlong: 32;\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n\tvoid (*shutdown)(struct mdio_device *);\n};\n\nstruct mdio_mux_parent_bus;\n\nstruct mdio_mux_child_bus {\n\tstruct mii_bus *mii_bus;\n\tstruct mdio_mux_parent_bus *parent;\n\tstruct mdio_mux_child_bus *next;\n\tint bus_number;\n};\n\nstruct mdio_mux_parent_bus {\n\tstruct mii_bus *mii_bus;\n\tint current_child;\n\tint parent_id;\n\tvoid *switch_data;\n\tint (*switch_fn)(int, int, void *);\n\tstruct mdio_mux_child_bus *children;\n};\n\nstruct mdio_regmap_config {\n\tstruct device *parent;\n\tstruct regmap *regmap;\n\tchar name[61];\n\tu8 valid_addr;\n\tbool autoscan;\n};\n\nstruct mdio_regmap_priv {\n\tstruct regmap *regmap;\n\tu8 valid_addr;\n};\n\nstruct mdiobb_ops {\n\tstruct module *owner;\n\tvoid (*set_mdc)(struct mdiobb_ctrl *, int);\n\tvoid (*set_mdio_dir)(struct mdiobb_ctrl *, int);\n\tvoid (*set_mdio_data)(struct mdiobb_ctrl *, int);\n\tint (*get_mdio_data)(struct mdiobb_ctrl *);\n};\n\nstruct mdiobus_devres {\n\tstruct mii_bus *mii;\n};\n\nstruct media_event_desc {\n\t__u8 media_event_code: 4;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 media_present: 1;\n\t__u8 reserved2: 6;\n\t__u8 start_slot;\n\t__u8 end_slot;\n};\n\nstruct regulator_coupler {\n\tstruct list_head list;\n\tint (*attach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*detach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*balance_voltage)(struct regulator_coupler *, struct regulator_dev *, suspend_state_t);\n};\n\nstruct mediatek_regulator_coupler {\n\tstruct regulator_coupler coupler;\n\tstruct regulator_dev *vsram_rdev;\n};\n\nstruct pglist_data;\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct mcidev_sysfs_attribute;\n\nstruct mem_ctl_info {\n\tstruct device dev;\n\tconst struct bus_type *bus;\n\tstruct list_head link;\n\tstruct module *owner;\n\tlong unsigned int mtype_cap;\n\tlong unsigned int edac_ctl_cap;\n\tlong unsigned int edac_cap;\n\tlong unsigned int scrub_cap;\n\tenum scrub_type scrub_mode;\n\tint (*set_sdram_scrub_rate)(struct mem_ctl_info *, u32);\n\tint (*get_sdram_scrub_rate)(struct mem_ctl_info *);\n\tvoid (*edac_check)(struct mem_ctl_info *);\n\tlong unsigned int (*ctl_page_to_phys)(struct mem_ctl_info *, long unsigned int);\n\tint mc_idx;\n\tstruct csrow_info **csrows;\n\tunsigned int nr_csrows;\n\tunsigned int num_cschannel;\n\tunsigned int n_layers;\n\tstruct edac_mc_layer *layers;\n\tbool csbased;\n\tunsigned int tot_dimms;\n\tstruct dimm_info **dimms;\n\tstruct device *pdev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tu32 ce_noinfo_count;\n\tu32 ue_noinfo_count;\n\tu32 ue_mc;\n\tu32 ce_mc;\n\tstruct completion complete;\n\tconst struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;\n\tstruct delayed_work work;\n\tstruct edac_raw_error_desc error_desc;\n\tint op_state;\n\tstruct dentry *debugfs;\n\tu8 fake_inject_layer[3];\n\tbool fake_inject_ue;\n\tu16 fake_inject_count;\n\tlong: 32;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tlong: 32;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n\tlong: 32;\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tlong: 32;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct mem_type___2 {\n\tpteval_t prot_pte;\n\tpteval_t prot_pte_s2;\n\tpmdval_t prot_l1;\n\tpmdval_t prot_sect;\n\tunsigned int domain;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct mempolicy {};\n\nstruct menu_device {\n\tint needs_update;\n\tint tick_wakeup;\n\tu64 next_timer_ns;\n\tunsigned int bucket;\n\tunsigned int correction_factor[6];\n\tunsigned int intervals[8];\n\tint interval_ptr;\n};\n\nstruct merge_sched_data {\n\tint can_add_hw;\n\tenum event_type_t event_type;\n};\n\nstruct meson8_pmx_data {\n\tbool is_gpio;\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct meson8b_clk_reset {\n\tstruct reset_controller_dev reset;\n\tstruct regmap *regmap;\n};\n\nstruct meson8b_clk_reset_line {\n\tu32 reg;\n\tu8 bit_idx;\n\tbool active_low;\n};\n\nstruct meson8b_dwmac_data;\n\nstruct meson8b_dwmac {\n\tstruct device *dev;\n\tvoid *regs;\n\tconst struct meson8b_dwmac_data *data;\n\tphy_interface_t phy_mode;\n\tstruct clk *rgmii_tx_clk;\n\tu32 tx_delay_ns;\n\tu32 rx_delay_ps;\n\tstruct clk *timing_adj_clk;\n};\n\nstruct meson8b_dwmac_clk_configs {\n\tstruct clk_mux m250_mux;\n\tstruct clk_divider m250_div;\n\tstruct clk_fixed_factor fixed_div2;\n\tstruct clk_gate rgmii_tx_en;\n};\n\nstruct meson8b_dwmac_data {\n\tint (*set_phy_mode)(struct meson8b_dwmac *);\n\tbool has_prg_eth1_rgmii_rx_delay;\n};\n\nstruct meson8b_nb_data {\n\tstruct notifier_block nb;\n\tstruct clk_hw *cpu_clk;\n};\n\nstruct meson_reg_desc {\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct meson_bank {\n\tconst char *name;\n\tunsigned int first;\n\tunsigned int last;\n\tint irq_first;\n\tint irq_last;\n\tstruct meson_reg_desc regs[6];\n};\n\nstruct meson_clk_hw_data {\n\tstruct clk_hw **hws;\n\tunsigned int num;\n};\n\nstruct parm {\n\tu16 reg_off;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct meson_clk_mpll_data {\n\tstruct parm sdm;\n\tstruct parm sdm_en;\n\tstruct parm n2;\n\tstruct parm ssen;\n\tstruct parm misc;\n\tconst struct reg_sequence *init_regs;\n\tunsigned int init_count;\n\tu8 flags;\n};\n\nstruct pll_params_table;\n\nstruct pll_mult_range;\n\nstruct meson_clk_pll_data {\n\tstruct parm en;\n\tstruct parm m;\n\tstruct parm n;\n\tstruct parm frac;\n\tstruct parm l;\n\tstruct parm rst;\n\tstruct parm current_en;\n\tstruct parm l_detect;\n\tconst struct reg_sequence *init_regs;\n\tunsigned int init_count;\n\tconst struct pll_params_table *table;\n\tconst struct pll_mult_range *range;\n\tunsigned int frac_max;\n\tu8 flags;\n};\n\nstruct meson_clkc_data {\n\tconst struct reg_sequence *init_regs;\n\tunsigned int init_count;\n\tstruct meson_clk_hw_data hw_clks;\n};\n\nstruct meson_dwmac {\n\tstruct device *dev;\n\tvoid *reg;\n};\n\nstruct meson_ee_pwrc_domain;\n\nstruct meson_ee_pwrc {\n\tstruct regmap *regmap_ao;\n\tstruct regmap *regmap_hhi;\n\tstruct meson_ee_pwrc_domain *domains;\n\tstruct genpd_onecell_data xlate;\n};\n\nstruct meson_ee_pwrc_top_domain;\n\nstruct meson_ee_pwrc_mem_domain;\n\nstruct meson_ee_pwrc_domain_desc {\n\tchar *name;\n\tunsigned int reset_names_count;\n\tunsigned int clk_names_count;\n\tconst struct meson_ee_pwrc_top_domain *top_pd;\n\tunsigned int mem_pd_count;\n\tconst struct meson_ee_pwrc_mem_domain *mem_pd;\n\tbool (*is_powered_off)(struct meson_ee_pwrc_domain *);\n};\n\nstruct meson_ee_pwrc_domain {\n\tstruct generic_pm_domain base;\n\tbool enabled;\n\tstruct meson_ee_pwrc *pwrc;\n\tstruct meson_ee_pwrc_domain_desc desc;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct reset_control *rstc;\n\tint num_rstc;\n\tlong: 32;\n};\n\nstruct meson_ee_pwrc_domain_data {\n\tunsigned int count;\n\tconst struct meson_ee_pwrc_domain_desc *domains;\n};\n\nstruct meson_ee_pwrc_mem_domain {\n\tunsigned int reg;\n\tunsigned int mask;\n};\n\nstruct meson_ee_pwrc_top_domain {\n\tunsigned int sleep_reg;\n\tunsigned int sleep_mask;\n\tunsigned int iso_reg;\n\tunsigned int iso_mask;\n};\n\nstruct meson_gpio_irq_params;\n\nstruct meson_gpio_irq_controller {\n\tconst struct meson_gpio_irq_params *params;\n\tvoid *base;\n\tu32 channel_irqs[64];\n\tlong unsigned int channel_map[2];\n\traw_spinlock_t lock;\n};\n\nstruct meson_gpio_irq_params {\n\tunsigned int nr_hwirq;\n\tunsigned int nr_channels;\n\tbool support_edge_both;\n\tunsigned int edge_both_offset;\n\tunsigned int edge_single_offset;\n\tunsigned int edge_pol_reg;\n\tunsigned int pol_low_offset;\n\tunsigned int pin_sel_mask;\n\tstruct irq_ctl_ops ops;\n};\n\nstruct meson_i2c_data;\n\nstruct meson_i2c {\n\tstruct i2c_adapter adap;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct i2c_msg *msg;\n\tint state;\n\tbool last;\n\tint count;\n\tint pos;\n\tint error;\n\tspinlock_t lock;\n\tstruct completion done;\n\tu32 tokens[2];\n\tint num_tokens;\n\tconst struct meson_i2c_data *data;\n};\n\nstruct meson_i2c_data {\n\tvoid (*set_clk_div)(struct meson_i2c *, unsigned int);\n};\n\nstruct meson_msr_id;\n\nstruct msr_reg_offset;\n\nstruct meson_msr_data {\n\tstruct meson_msr_id *msr_table;\n\tunsigned int msr_count;\n\tconst struct msr_reg_offset *reg;\n};\n\nstruct meson_msr {\n\tstruct regmap *regmap;\n\tstruct meson_msr_data data;\n};\n\nstruct meson_msr_id {\n\tstruct meson_msr *priv;\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct meson_mx_mmc_host {\n\tstruct device *controller_dev;\n\tstruct clk *cfg_div_clk;\n\tstruct regmap *regmap;\n\tint irq;\n\tspinlock_t irq_lock;\n\tstruct timer_list cmd_timeout;\n\tunsigned int slot_id;\n\tstruct mmc_host *mmc;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tint error;\n};\n\nstruct meson_mx_mmc_host_clkc {\n\tstruct clk_divider cfg_div;\n\tstruct clk_fixed_factor fixed_div2;\n};\n\nstruct meson_mx_sdhc_clkc {\n\tstruct clk_mux src_sel;\n\tstruct clk_divider div;\n\tstruct clk_gate mod_clk_en;\n\tstruct clk_gate tx_clk_en;\n\tstruct clk_gate rx_clk_en;\n\tstruct clk_gate sd_clk_en;\n};\n\nstruct meson_mx_sdhc_data {\n\tvoid (*init_hw)(struct mmc_host *);\n\tvoid (*set_pdma)(struct mmc_host *);\n\tvoid (*wait_before_send)(struct mmc_host *);\n\tbool hardware_flush_all_cmds;\n};\n\nstruct meson_mx_sdhc_host {\n\tstruct mmc_host *mmc;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tint error;\n\tstruct regmap *regmap;\n\tstruct clk *pclk;\n\tstruct clk *sd_clk;\n\tstruct clk_bulk_data bulk_clks[4];\n\tbool bulk_clks_enabled;\n\tconst struct meson_mx_sdhc_data *platform;\n};\n\nstruct meson_pinctrl_data;\n\nstruct meson_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pcdev;\n\tstruct pinctrl_desc desc;\n\tstruct meson_pinctrl_data *data;\n\tstruct regmap *reg_mux;\n\tstruct regmap *reg_pullen;\n\tstruct regmap *reg_pull;\n\tstruct regmap *reg_gpio;\n\tstruct regmap *reg_ds;\n\tstruct gpio_chip chip;\n\tstruct fwnode_handle *fwnode;\n};\n\nstruct meson_pmx_group;\n\nstruct meson_pmx_func;\n\nstruct meson_pinctrl_data {\n\tconst char *name;\n\tconst struct pinctrl_pin_desc *pins;\n\tconst struct meson_pmx_group *groups;\n\tconst struct meson_pmx_func *funcs;\n\tunsigned int num_pins;\n\tunsigned int num_groups;\n\tunsigned int num_funcs;\n\tconst struct meson_bank *banks;\n\tunsigned int num_banks;\n\tconst struct pinmux_ops *pmx_ops;\n\tconst void *pmx_data;\n\tint (*parse_dt)(struct meson_pinctrl *);\n};\n\nstruct meson_pmx_func {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct meson_pmx_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int num_pins;\n\tconst void *data;\n};\n\nstruct meson_reset_param;\n\nstruct meson_reset {\n\tconst struct meson_reset_param *param;\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *map;\n};\n\nstruct meson_reset_param {\n\tconst struct reset_control_ops *reset_ops;\n\tunsigned int reset_num;\n\tunsigned int reset_offset;\n\tunsigned int level_offset;\n\tbool level_low_reset;\n};\n\nstruct meson_rng_data {\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n};\n\nstruct meson_rng_priv {\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n};\n\nstruct uart_driver;\n\nstruct meson_uart_data {\n\tstruct uart_driver *uart_driver;\n\tbool has_xtal_div2;\n};\n\nstruct meson_wdt_data {\n\tunsigned int enable;\n\tunsigned int terminal_count_mask;\n\tunsigned int count_unit;\n};\n\nstruct meson_wdt_dev {\n\tstruct watchdog_device wdt_dev;\n\tvoid *wdt_base;\n\tconst struct meson_wdt_data *data;\n};\n\nstruct meta_entry {\n\tu64 data_block;\n\tunsigned int index_block;\n\tshort unsigned int offset;\n\tshort unsigned int pad;\n};\n\nstruct meta_index {\n\tunsigned int inode_number;\n\tunsigned int offset;\n\tshort unsigned int entries;\n\tshort unsigned int skip;\n\tshort unsigned int locked;\n\tshort unsigned int pad;\n\tstruct meta_entry meta_entry[127];\n};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tlong: 32;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mext_data {\n\tstruct inode *orig_inode;\n\tstruct inode *donor_inode;\n\tstruct ext4_map_blocks orig_map;\n\text4_lblk_t donor_lblk;\n\tlong: 32;\n};\n\nstruct mfd_cell_acpi_match;\n\nstruct mfd_cell {\n\tconst char *name;\n\tint id;\n\tint level;\n\tint (*suspend)(struct platform_device *);\n\tint (*resume)(struct platform_device *);\n\tconst void *platform_data;\n\tsize_t pdata_size;\n\tconst struct mfd_cell_acpi_match *acpi_match;\n\tconst struct software_node *swnode;\n\tconst char *of_compatible;\n\tu64 of_reg;\n\tbool use_of_reg;\n\tint num_resources;\n\tconst struct resource *resources;\n\tbool ignore_resource_conflicts;\n\tbool pm_runtime_no_callbacks;\n\tint num_parent_supplies;\n\tconst char * const *parent_supplies;\n};\n\nstruct mfd_cell_acpi_match {\n\tconst char *pnpid;\n\tlong: 32;\n\tconst long long unsigned int adr;\n};\n\nstruct mfd_of_node_entry {\n\tstruct list_head list;\n\tstruct device *dev;\n\tstruct device_node *np;\n};\n\nstruct mfp_addr_map {\n\tunsigned int start;\n\tunsigned int end;\n\tlong unsigned int offset;\n};\n\nstruct mfp_pin {\n\tlong unsigned int config;\n\tlong unsigned int mfpr_off;\n\tlong unsigned int mfpr_run;\n\tlong unsigned int mfpr_lpm;\n};\n\nstruct ntfs_sb_info;\n\nstruct mft_inode {\n\tstruct rb_node node;\n\tstruct ntfs_sb_info *sbi;\n\tstruct MFT_REC *mrec;\n\tstruct ntfs_buffers nb;\n\tCLST rno;\n\tbool dirty;\n};\n\nstruct mib_counters {\n\tu64 good_octets_received;\n\tu32 bad_octets_received;\n\tu32 internal_mac_transmit_err;\n\tu32 good_frames_received;\n\tu32 bad_frames_received;\n\tu32 broadcast_frames_received;\n\tu32 multicast_frames_received;\n\tu32 frames_64_octets;\n\tu32 frames_65_to_127_octets;\n\tu32 frames_128_to_255_octets;\n\tu32 frames_256_to_511_octets;\n\tu32 frames_512_to_1023_octets;\n\tu32 frames_1024_to_max_octets;\n\tu64 good_octets_sent;\n\tu32 good_frames_sent;\n\tu32 excessive_collision;\n\tu32 multicast_frames_sent;\n\tu32 broadcast_frames_sent;\n\tu32 unrec_mac_control_received;\n\tu32 fc_sent;\n\tu32 good_fc_received;\n\tu32 bad_fc_received;\n\tu32 undersize_received;\n\tu32 fragments_received;\n\tu32 oversize_received;\n\tu32 jabber_received;\n\tu32 mac_receive_error;\n\tu32 bad_crc_event;\n\tu32 collision;\n\tu32 late_collision;\n\tu32 rx_discard;\n\tu32 rx_overrun;\n};\n\nstruct micron_on_die_ecc {\n\tbool forced;\n\tbool enabled;\n\tvoid *rawbuf;\n};\n\nstruct micron_nand {\n\tstruct micron_on_die_ecc ecc;\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\tlong: 32;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct phy_package_shared;\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tlong: 32;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n\tstruct phy_package_shared *shared[32];\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct miic_phy_link_cfg {\n\tu32 mask;\n\tu32 val;\n};\n\nstruct miic_of_data;\n\nstruct miic {\n\tvoid *base;\n\tstruct device *dev;\n\tspinlock_t lock;\n\tstruct reset_control_bulk_data rsts[2];\n\tconst struct miic_of_data *of_data;\n\tstruct miic_phy_link_cfg link_cfg;\n};\n\nstruct modctrl_match;\n\nstruct miic_of_data {\n\tstruct modctrl_match *match_table;\n\tu8 match_table_count;\n\tu8 conf_conv_count;\n\tconst char * const *conf_to_string;\n\tu8 conf_to_string_count;\n\tconst char * const *index_to_string;\n\tu8 index_to_string_count;\n\tu8 miic_port_start;\n\tu8 miic_port_max;\n\tu8 sw_mode_mask;\n\tconst char * const *reset_ids;\n\tu8 reset_count;\n\tbool init_unlock_lock_regs;\n\tvoid (*miic_write)(struct miic *, int, u32);\n\tenum miic_type type;\n};\n\nstruct miic_port {\n\tstruct miic *miic;\n\tstruct phylink_pcs pcs;\n\tint port;\n\tphy_interface_t interface;\n};\n\nstruct min_heap_callbacks {\n\tbool (*less)(const void *, const void *, void *);\n\tvoid (*swp)(void *, void *, void *);\n};\n\nstruct min_heap_char {\n\tsize_t nr;\n\tsize_t size;\n\tchar *data;\n\tchar preallocated[0];\n};\n\ntypedef struct min_heap_char min_heap_char;\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nstruct tcf_proto;\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minimode {\n\tshort int w;\n\tshort int h;\n\tshort int r;\n\tshort int rb;\n};\n\nstruct minix_super_block {\n\t__u16 s_ninodes;\n\t__u16 s_nzones;\n\t__u16 s_imap_blocks;\n\t__u16 s_zmap_blocks;\n\t__u16 s_firstdatazone;\n\t__u16 s_log_zone_size;\n\t__u32 s_max_size;\n\t__u16 s_magic;\n\t__u16 s_state;\n\t__u32 s_zones;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct miphy28lp_phy;\n\nstruct miphy28lp_dev {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct mutex miphy_mutex;\n\tstruct miphy28lp_phy **phys;\n\tint nphys;\n};\n\nstruct miphy28lp_phy {\n\tstruct phy *phy;\n\tstruct miphy28lp_dev *phydev;\n\tvoid *base;\n\tvoid *pipebase;\n\tbool osc_force_ext;\n\tbool osc_rdy;\n\tbool px_rx_pol_inv;\n\tbool ssc;\n\tbool tx_impedance;\n\tstruct reset_control *miphy_rst;\n\tu32 sata_gen;\n\tu32 syscfg_reg[4];\n\tu8 type;\n};\n\nstruct miphy28lp_pll_gen {\n\tint bank;\n\tint speed;\n\tint bias_boost_1;\n\tint bias_boost_2;\n\tint tx_ctrl_1;\n\tint tx_ctrl_2;\n\tint tx_ctrl_3;\n\tint rx_k_gain;\n\tint rx_vga_gain;\n\tint rx_equ_gain_1;\n\tint rx_equ_gain_2;\n\tint rx_equ_gain_3;\n\tint rx_buff_ctrl;\n};\n\nstruct mipi_dphy_timing {\n\tunsigned int clkmiss;\n\tunsigned int clkpost;\n\tunsigned int clkpre;\n\tunsigned int clkprepare;\n\tunsigned int clksettle;\n\tunsigned int clktermen;\n\tunsigned int clktrail;\n\tunsigned int clkzero;\n\tunsigned int dtermen;\n\tunsigned int eot;\n\tunsigned int hsexit;\n\tunsigned int hsprepare;\n\tunsigned int hszero;\n\tunsigned int hssettle;\n\tunsigned int hsskip;\n\tunsigned int hstrail;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int taget;\n\tunsigned int tago;\n\tunsigned int tasure;\n\tunsigned int wakeup;\n};\n\nstruct mipi_dsi_host;\n\nstruct mipi_dsi_device {\n\tstruct mipi_dsi_host *host;\n\tlong: 32;\n\tstruct device dev;\n\tbool attached;\n\tchar name[20];\n\tunsigned int channel;\n\tunsigned int lanes;\n\tenum mipi_dsi_pixel_format format;\n\tlong unsigned int mode_flags;\n\tlong unsigned int hs_rate;\n\tlong unsigned int lp_rate;\n\tstruct drm_dsc_config *dsc;\n\tlong: 32;\n};\n\nstruct mipi_dsi_device_info {\n\tchar type[20];\n\tu32 channel;\n\tstruct device_node *node;\n};\n\nstruct mipi_dsi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct mipi_dsi_device *);\n\tvoid (*remove)(struct mipi_dsi_device *);\n\tvoid (*shutdown)(struct mipi_dsi_device *);\n};\n\nstruct mipi_dsi_host_ops;\n\nstruct mipi_dsi_host {\n\tstruct device *dev;\n\tconst struct mipi_dsi_host_ops *ops;\n\tstruct list_head list;\n};\n\nstruct mipi_dsi_msg;\n\nstruct mipi_dsi_host_ops {\n\tint (*attach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tint (*detach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tssize_t (*transfer)(struct mipi_dsi_host *, const struct mipi_dsi_msg *);\n};\n\nstruct mipi_dsi_msg {\n\tu8 channel;\n\tu8 type;\n\tu16 flags;\n\tsize_t tx_len;\n\tconst void *tx_buf;\n\tsize_t rx_len;\n\tvoid *rx_buf;\n};\n\nstruct mipi_dsi_multi_context {\n\tstruct mipi_dsi_device *dsi;\n\tint accum_err;\n};\n\nstruct mipi_dsi_packet {\n\tsize_t size;\n\tu8 header[4];\n\tsize_t payload_length;\n\tconst u8 *payload;\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct mld2_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\tstruct in6_addr grec_mca;\n\tstruct in6_addr grec_src[0];\n};\n\nstruct mld2_query {\n\tstruct icmp6hdr mld2q_hdr;\n\tstruct in6_addr mld2q_mca;\n\t__u8 mld2q_qrv: 3;\n\t__u8 mld2q_suppress: 1;\n\t__u8 mld2q_resv2: 4;\n\t__u8 mld2q_qqic;\n\t__be16 mld2q_nsrcs;\n\tstruct in6_addr mld2q_srcs[0];\n};\n\nstruct mld2_report {\n\tstruct icmp6hdr mld2r_hdr;\n\tstruct mld2_grec mld2r_grec[0];\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tlong: 32;\n\tstruct ethtool_mm_stats stats;\n};\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n};\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct rcuwait vma_writer_wait;\n\t\tseqcount_t mm_lock_seq;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tlong: 32;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[46];\n\t\tlong: 32;\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tlong: 32;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tatomic_t tlb_flush_pending;\n\t\tstruct uprobes_state uprobes_state;\n\t\tstruct work_struct async_put_work;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t\tlong: 32;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct mmap_arg_struct {\n\tlong unsigned int addr;\n\tlong unsigned int len;\n\tlong unsigned int prot;\n\tlong unsigned int flags;\n\tlong unsigned int fd;\n\tlong unsigned int offset;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mmc_blk_busy_data {\n\tstruct mmc_card *card;\n\tu32 status;\n};\n\nstruct mmc_ctx {\n\tstruct task_struct *task;\n};\n\nstruct mmc_blk_data;\n\nstruct mmc_queue {\n\tstruct mmc_card *card;\n\tstruct mmc_ctx ctx;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct mmc_blk_data *blkdata;\n\tstruct request_queue *queue;\n\tspinlock_t lock;\n\tint in_flight[3];\n\tunsigned int cqe_busy;\n\tbool busy;\n\tbool recovery_needed;\n\tbool in_recovery;\n\tbool rw_wait;\n\tbool waiting;\n\tstruct work_struct recovery_work;\n\twait_queue_head_t wait;\n\tstruct request *recovery_req;\n\tstruct request *complete_req;\n\tstruct mutex complete_lock;\n\tstruct work_struct complete_work;\n};\n\nstruct mmc_blk_data {\n\tstruct device *parent;\n\tstruct gendisk *disk;\n\tstruct mmc_queue queue;\n\tstruct list_head part;\n\tstruct list_head rpmbs;\n\tunsigned int flags;\n\tstruct kref kref;\n\tunsigned int read_only;\n\tunsigned int part_type;\n\tunsigned int reset_done;\n\tunsigned int part_curr;\n\tint area_type;\n\tstruct dentry *status_dentry;\n\tstruct dentry *ext_csd_dentry;\n};\n\nstruct mmc_ioc_cmd {\n\tint write_flag;\n\tint is_acmd;\n\t__u32 opcode;\n\t__u32 arg;\n\t__u32 response[4];\n\tunsigned int flags;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int postsleep_min_us;\n\tunsigned int postsleep_max_us;\n\tunsigned int data_timeout_ns;\n\tunsigned int cmd_timeout_ms;\n\t__u32 __pad;\n\t__u64 data_ptr;\n};\n\nstruct mmc_rpmb_data;\n\nstruct mmc_blk_ioc_data {\n\tstruct mmc_ioc_cmd ic;\n\tunsigned char *buf;\n\tlong: 32;\n\tu64 buf_bytes;\n\tunsigned int flags;\n\tstruct mmc_rpmb_data *rpmb;\n};\n\nstruct uhs2_command {\n\tu16 header;\n\tu16 arg;\n\t__be32 payload[2];\n\tu8 payload_len;\n\tu8 packet_len;\n\tu8 tmode_half_duplex;\n\tu8 uhs2_resp[20];\n\tu8 uhs2_resp_len;\n};\n\nstruct mmc_request {\n\tstruct mmc_command *sbc;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command *stop;\n\tstruct completion completion;\n\tstruct completion cmd_completion;\n\tvoid (*done)(struct mmc_request *);\n\tvoid (*recovery_notifier)(struct mmc_request *);\n\tstruct mmc_host *host;\n\tbool cap_cmd_during_tfr;\n\tint tag;\n\tstruct uhs2_command uhs2_cmd;\n};\n\nstruct mmc_data {\n\tunsigned int timeout_ns;\n\tunsigned int timeout_clks;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int blk_addr;\n\tint error;\n\tunsigned int flags;\n\tunsigned int bytes_xfered;\n\tstruct mmc_command *stop;\n\tstruct mmc_request *mrq;\n\tunsigned int sg_len;\n\tint sg_count;\n\tstruct scatterlist *sg;\n\ts32 host_cookie;\n};\n\nstruct mmc_blk_request {\n\tstruct mmc_request mrq;\n\tstruct mmc_command sbc;\n\tstruct mmc_command cmd;\n\tstruct mmc_command stop;\n\tstruct mmc_data data;\n};\n\nstruct mmc_bus_ops {\n\tvoid (*remove)(struct mmc_host *);\n\tvoid (*detect)(struct mmc_host *);\n\tint (*pre_suspend)(struct mmc_host *);\n\tint (*suspend)(struct mmc_host *);\n\tint (*resume)(struct mmc_host *);\n\tint (*runtime_suspend)(struct mmc_host *);\n\tint (*runtime_resume)(struct mmc_host *);\n\tint (*alive)(struct mmc_host *);\n\tint (*shutdown)(struct mmc_host *);\n\tint (*hw_reset)(struct mmc_host *);\n\tint (*sw_reset)(struct mmc_host *);\n\tbool (*cache_enabled)(struct mmc_host *);\n\tint (*flush_cache)(struct mmc_host *);\n\tint (*handle_undervoltage)(struct mmc_host *);\n};\n\nstruct mmc_busy_data {\n\tstruct mmc_card *card;\n\tbool retry_crc_err;\n\tenum mmc_busy_cmd busy_cmd;\n};\n\nstruct mmc_cid {\n\tunsigned int manfid;\n\tchar prod_name[8];\n\tunsigned char prv;\n\tunsigned int serial;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char hwrev;\n\tunsigned char fwrev;\n\tunsigned char month;\n};\n\nstruct mmc_csd {\n\tunsigned char structure;\n\tunsigned char mmca_vsn;\n\tshort unsigned int cmdclass;\n\tshort unsigned int taac_clks;\n\tunsigned int taac_ns;\n\tunsigned int c_size;\n\tunsigned int r2w_factor;\n\tunsigned int max_dtr;\n\tunsigned int erase_size;\n\tunsigned int wp_grp_size;\n\tunsigned int read_blkbits;\n\tunsigned int write_blkbits;\n\tsector_t capacity;\n\tunsigned int read_partial: 1;\n\tunsigned int read_misalign: 1;\n\tunsigned int write_partial: 1;\n\tunsigned int write_misalign: 1;\n\tunsigned int dsr_imp: 1;\n\tlong: 32;\n};\n\nstruct mmc_ext_csd {\n\tu8 rev;\n\tu8 erase_group_def;\n\tu8 sec_feature_support;\n\tu8 rel_sectors;\n\tu8 rel_param;\n\tbool enhanced_rpmb_supported;\n\tu8 part_config;\n\tu8 cache_ctrl;\n\tu8 rst_n_function;\n\tunsigned int part_time;\n\tunsigned int sa_timeout;\n\tunsigned int generic_cmd6_time;\n\tunsigned int power_off_longtime;\n\tu8 power_off_notification;\n\tunsigned int hs_max_dtr;\n\tunsigned int hs200_max_dtr;\n\tunsigned int sectors;\n\tunsigned int hc_erase_size;\n\tunsigned int hc_erase_timeout;\n\tunsigned int sec_trim_mult;\n\tunsigned int sec_erase_mult;\n\tunsigned int trim_timeout;\n\tbool partition_setting_completed;\n\tlong: 32;\n\tlong long unsigned int enhanced_area_offset;\n\tunsigned int enhanced_area_size;\n\tunsigned int cache_size;\n\tbool hpi_en;\n\tbool hpi;\n\tunsigned int hpi_cmd;\n\tbool bkops;\n\tbool man_bkops_en;\n\tbool auto_bkops_en;\n\tunsigned int data_sector_size;\n\tunsigned int data_tag_unit_size;\n\tunsigned int boot_ro_lock;\n\tbool boot_ro_lockable;\n\tbool ffu_capable;\n\tbool cmdq_en;\n\tbool cmdq_support;\n\tunsigned int cmdq_depth;\n\tu8 fwrev[8];\n\tu8 raw_exception_status;\n\tu8 raw_partition_support;\n\tu8 raw_rpmb_size_mult;\n\tu8 raw_erased_mem_count;\n\tu8 strobe_support;\n\tu8 raw_ext_csd_structure;\n\tu8 raw_card_type;\n\tu8 raw_driver_strength;\n\tu8 out_of_int_time;\n\tu8 raw_pwr_cl_52_195;\n\tu8 raw_pwr_cl_26_195;\n\tu8 raw_pwr_cl_52_360;\n\tu8 raw_pwr_cl_26_360;\n\tu8 raw_s_a_timeout;\n\tu8 raw_hc_erase_gap_size;\n\tu8 raw_erase_timeout_mult;\n\tu8 raw_hc_erase_grp_size;\n\tu8 raw_boot_mult;\n\tu8 raw_sec_trim_mult;\n\tu8 raw_sec_erase_mult;\n\tu8 raw_sec_feature_support;\n\tu8 raw_trim_mult;\n\tu8 raw_pwr_cl_200_195;\n\tu8 raw_pwr_cl_200_360;\n\tu8 raw_pwr_cl_ddr_52_195;\n\tu8 raw_pwr_cl_ddr_52_360;\n\tu8 raw_pwr_cl_ddr_200_360;\n\tu8 raw_bkops_status;\n\tu8 raw_sectors[4];\n\tu8 pre_eol_info;\n\tu8 device_life_time_est_typ_a;\n\tu8 device_life_time_est_typ_b;\n\tunsigned int feature_support;\n};\n\nstruct sd_scr {\n\tunsigned char sda_vsn;\n\tunsigned char sda_spec3;\n\tunsigned char sda_spec4;\n\tunsigned char sda_specx;\n\tunsigned char bus_widths;\n\tunsigned char cmds;\n};\n\nstruct sd_ssr {\n\tunsigned int au;\n\tunsigned int erase_timeout;\n\tunsigned int erase_offset;\n};\n\nstruct sd_switch_caps {\n\tunsigned int hs_max_dtr;\n\tunsigned int uhs_max_dtr;\n\tunsigned int sd3_bus_mode;\n\tunsigned int sd3_drv_type;\n\tunsigned int sd3_curr_limit;\n};\n\nstruct sd_ext_reg {\n\tu8 fno;\n\tu8 page;\n\tu16 offset;\n\tu8 rev;\n\tu8 feature_enabled;\n\tu8 feature_support;\n};\n\nstruct sd_uhs2_config {\n\tu32 node_id;\n\tu32 n_fcu;\n\tu32 maxblk_len;\n\tu8 n_lanes;\n\tu8 dadr_len;\n\tu8 app_type;\n\tu8 phy_minor_rev;\n\tu8 phy_major_rev;\n\tu8 can_hibernate;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_minor_rev;\n\tu8 link_major_rev;\n\tu8 dev_type;\n\tu8 n_data_gap;\n\tu32 n_fcu_set;\n\tu32 maxblk_len_set;\n\tu8 n_lanes_set;\n\tu8 speed_range_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct sdio_cccr {\n\tunsigned int sdio_vsn;\n\tunsigned int sd_vsn;\n\tunsigned int multi_block: 1;\n\tunsigned int low_speed: 1;\n\tunsigned int wide_bus: 1;\n\tunsigned int high_power: 1;\n\tunsigned int high_speed: 1;\n\tunsigned int disable_cd: 1;\n\tunsigned int enable_async_irq: 1;\n};\n\nstruct sdio_cis {\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int blksize;\n\tunsigned int max_dtr;\n};\n\nstruct mmc_part {\n\tu64 size;\n\tunsigned int part_cfg;\n\tchar name[20];\n\tbool force_ro;\n\tunsigned int area_type;\n};\n\nstruct sdio_func_tuple;\n\nstruct mmc_card {\n\tstruct mmc_host *host;\n\tlong: 32;\n\tstruct device dev;\n\tu32 ocr;\n\tunsigned int rca;\n\tunsigned int type;\n\tunsigned int state;\n\tunsigned int quirks;\n\tunsigned int quirk_max_rate;\n\tbool written_flag;\n\tbool reenable_cmdq;\n\tunsigned int erase_size;\n\tunsigned int erase_shift;\n\tunsigned int pref_erase;\n\tunsigned int eg_boundary;\n\tunsigned int erase_arg;\n\tu8 erased_byte;\n\tunsigned int wp_grp_size;\n\tu32 raw_cid[4];\n\tu32 raw_csd[4];\n\tu32 raw_scr[2];\n\tu32 raw_ssr[16];\n\tstruct mmc_cid cid;\n\tlong: 32;\n\tstruct mmc_csd csd;\n\tstruct mmc_ext_csd ext_csd;\n\tstruct sd_scr scr;\n\tstruct sd_ssr ssr;\n\tstruct sd_switch_caps sw_caps;\n\tstruct sd_ext_reg ext_power;\n\tstruct sd_ext_reg ext_perf;\n\tstruct sd_uhs2_config uhs2_config;\n\tunsigned int sdio_funcs;\n\tatomic_t sdio_funcs_probed;\n\tstruct sdio_cccr cccr;\n\tstruct sdio_cis cis;\n\tstruct sdio_func *sdio_func[7];\n\tstruct sdio_func *sdio_single_irq;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n\tunsigned int sd_bus_speed;\n\tunsigned int mmc_avail_type;\n\tunsigned int drive_strength;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_part part[7];\n\tunsigned int nr_parts;\n\tstruct workqueue_struct *complete_wq;\n};\n\nstruct mmc_clk_phase {\n\tbool valid;\n\tu16 in_deg;\n\tu16 out_deg;\n};\n\nstruct mmc_clk_phase_map {\n\tstruct mmc_clk_phase phase[11];\n};\n\nstruct mmc_cqe_ops {\n\tint (*cqe_enable)(struct mmc_host *, struct mmc_card *);\n\tvoid (*cqe_disable)(struct mmc_host *);\n\tint (*cqe_request)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_post_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_off)(struct mmc_host *);\n\tint (*cqe_wait_for_idle)(struct mmc_host *);\n\tbool (*cqe_timeout)(struct mmc_host *, struct mmc_request *, bool *);\n\tvoid (*cqe_recovery_start)(struct mmc_host *);\n\tvoid (*cqe_recovery_finish)(struct mmc_host *);\n};\n\nstruct mmc_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct mmc_card *);\n\tvoid (*remove)(struct mmc_card *);\n\tvoid (*shutdown)(struct mmc_card *);\n};\n\nstruct mmc_fixup {\n\tconst char *name;\n\tlong: 32;\n\tu64 rev_start;\n\tu64 rev_end;\n\tunsigned int manfid;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char month;\n\tu16 cis_vendor;\n\tu16 cis_device;\n\tunsigned int ext_csd_rev;\n\tconst char *of_compatible;\n\tvoid (*vendor_fixup)(struct mmc_card *, int);\n\tint data;\n};\n\nstruct mmc_gpio {\n\tstruct gpio_desc *ro_gpio;\n\tstruct gpio_desc *cd_gpio;\n\tirq_handler_t cd_gpio_isr;\n\tchar *ro_label;\n\tchar *cd_label;\n\tu32 cd_debounce_delay_ms;\n\tint cd_irq;\n};\n\nstruct sd_uhs2_caps {\n\tu32 dap;\n\tu32 gap;\n\tu32 group_desc;\n\tu32 maxblk_len;\n\tu32 n_fcu;\n\tu8 n_lanes;\n\tu8 addr64;\n\tu8 card_type;\n\tu8 phy_rev;\n\tu8 speed_range;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_rev;\n\tu8 host_type;\n\tu8 n_data_gap;\n\tu32 maxblk_len_set;\n\tu32 n_fcu_set;\n\tu8 n_lanes_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct mmc_ios {\n\tunsigned int clock;\n\tshort unsigned int vdd;\n\tunsigned int power_delay_ms;\n\tunsigned char bus_mode;\n\tunsigned char chip_select;\n\tunsigned char power_mode;\n\tunsigned char bus_width;\n\tunsigned char timing;\n\tunsigned char signal_voltage;\n\tunsigned char vqmmc2_voltage;\n\tunsigned char drv_type;\n\tbool enhanced_strobe;\n};\n\nstruct mmc_slot {\n\tint cd_irq;\n\tbool cd_wake_enabled;\n\tvoid *handler_priv;\n};\n\nstruct mmc_supply {\n\tstruct regulator *vmmc;\n\tstruct regulator *vqmmc;\n\tstruct regulator *vqmmc2;\n\tstruct notifier_block vmmc_nb;\n\tstruct work_struct uv_work;\n};\n\nstruct mmc_host_ops;\n\nstruct mmc_pwrseq;\n\nstruct mmc_host {\n\tstruct device *parent;\n\tlong: 32;\n\tstruct device class_dev;\n\tint index;\n\tconst struct mmc_host_ops *ops;\n\tstruct mmc_pwrseq *pwrseq;\n\tunsigned int f_min;\n\tunsigned int f_max;\n\tunsigned int f_init;\n\tu32 ocr_avail;\n\tu32 ocr_avail_sdio;\n\tu32 ocr_avail_sd;\n\tu32 ocr_avail_mmc;\n\tstruct wakeup_source *ws;\n\tu32 max_current_330;\n\tu32 max_current_300;\n\tu32 max_current_180;\n\tu32 caps;\n\tu32 caps2;\n\tbool uhs2_sd_tran;\n\tbool uhs2_app_cmd;\n\tstruct sd_uhs2_caps uhs2_caps;\n\tint fixed_drv_type;\n\tmmc_pm_flag_t pm_caps;\n\tunsigned int max_seg_size;\n\tshort unsigned int max_segs;\n\tshort unsigned int unused;\n\tunsigned int max_req_size;\n\tunsigned int max_blk_size;\n\tunsigned int max_blk_count;\n\tunsigned int max_busy_timeout;\n\tspinlock_t lock;\n\tstruct mmc_ios ios;\n\tbool claimed;\n\tunsigned int use_spi_crc: 1;\n\tunsigned int doing_init_tune: 1;\n\tunsigned int doing_retune: 1;\n\tunsigned int retune_crc_disable: 1;\n\tunsigned int can_dma_map_merge: 1;\n\tunsigned int vqmmc_enabled: 1;\n\tunsigned int undervoltage: 1;\n\tint rescan_disable;\n\tint rescan_entered;\n\tbool can_retune;\n\tbool retune_now;\n\tbool retune_paused;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct timer_list retune_timer;\n\tbool trigger_card_event;\n\tstruct mmc_card *card;\n\twait_queue_head_t wq;\n\tstruct mmc_ctx *claimer;\n\tint claim_cnt;\n\tstruct mmc_ctx default_ctx;\n\tstruct delayed_work detect;\n\tint detect_change;\n\tstruct mmc_slot slot;\n\tconst struct mmc_bus_ops *bus_ops;\n\tunsigned int sdio_irqs;\n\tstruct task_struct *sdio_irq_thread;\n\tstruct work_struct sdio_irq_work;\n\tbool sdio_irq_pending;\n\tatomic_t sdio_irq_thread_abort;\n\tmmc_pm_flag_t pm_flags;\n\tstruct led_trigger *led;\n\tbool regulator_enabled;\n\tstruct mmc_supply supply;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_request *ongoing_mrq;\n\tunsigned int actual_clock;\n\tunsigned int slotno;\n\tint dsr_req;\n\tu32 dsr;\n\tconst struct mmc_cqe_ops *cqe_ops;\n\tvoid *cqe_private;\n\tint cqe_qdepth;\n\tbool cqe_enabled;\n\tbool cqe_on;\n\tbool hsq_enabled;\n\tint hsq_depth;\n\tu32 err_stats[15];\n\tu32 max_sd_hs_hz;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct mmc_host_ops {\n\tvoid (*post_req)(struct mmc_host *, struct mmc_request *, int);\n\tvoid (*pre_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*request)(struct mmc_host *, struct mmc_request *);\n\tint (*request_atomic)(struct mmc_host *, struct mmc_request *);\n\tvoid (*set_ios)(struct mmc_host *, struct mmc_ios *);\n\tint (*get_ro)(struct mmc_host *);\n\tint (*get_cd)(struct mmc_host *);\n\tvoid (*enable_sdio_irq)(struct mmc_host *, int);\n\tvoid (*ack_sdio_irq)(struct mmc_host *);\n\tvoid (*init_card)(struct mmc_host *, struct mmc_card *);\n\tint (*start_signal_voltage_switch)(struct mmc_host *, struct mmc_ios *);\n\tint (*card_busy)(struct mmc_host *);\n\tint (*execute_tuning)(struct mmc_host *, u32);\n\tint (*prepare_hs400_tuning)(struct mmc_host *, struct mmc_ios *);\n\tint (*execute_hs400_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*prepare_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*execute_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*hs400_prepare_ddr)(struct mmc_host *);\n\tvoid (*hs400_downgrade)(struct mmc_host *);\n\tvoid (*hs400_complete)(struct mmc_host *);\n\tvoid (*hs400_enhanced_strobe)(struct mmc_host *, struct mmc_ios *);\n\tint (*select_drive_strength)(struct mmc_card *, unsigned int, int, int, int *);\n\tvoid (*card_hw_reset)(struct mmc_host *);\n\tvoid (*card_event)(struct mmc_host *);\n\tint (*multi_io_quirk)(struct mmc_card *, unsigned int, int);\n\tint (*init_sd_express)(struct mmc_host *, struct mmc_ios *);\n\tint (*uhs2_control)(struct mmc_host *, enum sd_uhs2_operation);\n};\n\nstruct mmc_ioc_multi_cmd {\n\t__u64 num_of_cmds;\n\tstruct mmc_ioc_cmd cmds[0];\n};\n\nstruct mmc_omap_slot;\n\nstruct omap_mmc_platform_data;\n\nstruct mmc_omap_host {\n\tint initialized;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_host *mmc;\n\tstruct device *dev;\n\tunsigned char id;\n\tstruct clk *iclk;\n\tstruct clk *fclk;\n\tstruct dma_chan *dma_rx;\n\tu32 dma_rx_burst;\n\tstruct dma_chan *dma_tx;\n\tu32 dma_tx_burst;\n\tvoid *virt_base;\n\tunsigned int phys_base;\n\tint irq;\n\tunsigned char bus_mode;\n\tunsigned int reg_shift;\n\tstruct gpio_desc *slot_switch;\n\tstruct work_struct cmd_abort_work;\n\tunsigned int abort: 1;\n\tstruct timer_list cmd_abort_timer;\n\tstruct work_struct slot_release_work;\n\tstruct mmc_omap_slot *next_slot;\n\tstruct work_struct send_stop_work;\n\tstruct mmc_data *stop_data;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int sg_len;\n\tu32 total_bytes_left;\n\tunsigned int features;\n\tunsigned int brs_received: 1;\n\tunsigned int dma_done: 1;\n\tunsigned int dma_in_use: 1;\n\tspinlock_t dma_lock;\n\tstruct mmc_omap_slot *slots[2];\n\tstruct mmc_omap_slot *current_slot;\n\tspinlock_t slot_lock;\n\twait_queue_head_t slot_wq;\n\tint nr_slots;\n\tstruct timer_list clk_timer;\n\tspinlock_t clk_lock;\n\tunsigned int fclk_enabled: 1;\n\tstruct workqueue_struct *mmc_omap_wq;\n\tstruct omap_mmc_platform_data *pdata;\n};\n\nstruct omap_mmc_slot_data;\n\nstruct mmc_omap_slot {\n\tint id;\n\tunsigned int vdd;\n\tu16 saved_con;\n\tu16 bus_mode;\n\tu16 power_mode;\n\tunsigned int fclk_freq;\n\tstruct work_struct cover_bh_work;\n\tstruct timer_list cover_timer;\n\tunsigned int cover_open;\n\tstruct mmc_request *mrq;\n\tstruct mmc_omap_host *host;\n\tstruct mmc_host *mmc;\n\tstruct gpio_desc *vsd;\n\tstruct gpio_desc *vio;\n\tstruct gpio_desc *cover;\n\tstruct omap_mmc_slot_data *pdata;\n};\n\nstruct mmc_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct mmc_phase {\n\tstruct clk_hw hw;\n\tu8 offset;\n\tvoid *reg;\n\tspinlock_t *lock;\n};\n\nstruct mmc_pwrseq_ops;\n\nstruct mmc_pwrseq {\n\tconst struct mmc_pwrseq_ops *ops;\n\tstruct device *dev;\n\tstruct list_head pwrseq_node;\n\tstruct module *owner;\n};\n\nstruct mmc_pwrseq_emmc {\n\tstruct mmc_pwrseq pwrseq;\n\tstruct notifier_block reset_nb;\n\tstruct gpio_desc *reset_gpio;\n};\n\nstruct mmc_pwrseq_ops {\n\tvoid (*pre_power_on)(struct mmc_host *);\n\tvoid (*post_power_on)(struct mmc_host *);\n\tvoid (*power_off)(struct mmc_host *);\n\tvoid (*reset)(struct mmc_host *);\n};\n\nstruct mmc_pwrseq_simple {\n\tstruct mmc_pwrseq pwrseq;\n\tbool clk_enabled;\n\tu32 post_power_on_delay_ms;\n\tu32 power_off_delay_us;\n\tstruct clk *ext_clk;\n\tstruct gpio_descs *reset_gpios;\n\tstruct reset_control *reset_ctrl;\n};\n\nstruct mmc_queue_req {\n\tstruct mmc_blk_request brq;\n\tstruct scatterlist *sg;\n\tenum mmc_drv_op drv_op;\n\tint drv_op_result;\n\tvoid *drv_op_data;\n\tunsigned int ioc_count;\n\tint retries;\n};\n\nstruct rpmb_dev;\n\nstruct mmc_rpmb_data {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tunsigned int part_index;\n\tstruct mmc_blk_data *md;\n\tstruct rpmb_dev *rdev;\n\tstruct list_head node;\n\tlong: 32;\n};\n\nstruct mmci_dmae_next {\n\tstruct dma_async_tx_descriptor *desc;\n\tstruct dma_chan *chan;\n};\n\nstruct mmci_dmae_priv {\n\tstruct dma_chan *cur;\n\tstruct dma_chan *rx_channel;\n\tstruct dma_chan *tx_channel;\n\tstruct dma_async_tx_descriptor *desc_current;\n\tstruct mmci_dmae_next next_data;\n};\n\nstruct mmci_platform_data;\n\nstruct mmci_host_ops;\n\nstruct variant_data;\n\nstruct mmci_host {\n\tphys_addr_t phybase;\n\tvoid *base;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_command stop_abort;\n\tstruct mmc_data *data;\n\tstruct mmc_host *mmc;\n\tstruct clk *clk;\n\tu8 singleirq: 1;\n\tstruct reset_control *rst;\n\tspinlock_t lock;\n\tunsigned int mclk;\n\tunsigned int clock_cache;\n\tunsigned int cclk;\n\tu32 pwr_reg;\n\tu32 pwr_reg_add;\n\tu32 clk_reg;\n\tu32 clk_reg_add;\n\tu32 datactrl_reg;\n\tenum mmci_busy_state busy_state;\n\tu32 busy_status;\n\tu32 mask1_reg;\n\tu8 vqmmc_enabled: 1;\n\tstruct mmci_platform_data *plat;\n\tstruct mmc_host_ops *mmc_ops;\n\tstruct mmci_host_ops *ops;\n\tstruct variant_data *variant;\n\tvoid *variant_priv;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_opendrain;\n\tu8 hw_designer;\n\tu8 hw_revision: 4;\n\tstruct timer_list timer;\n\tunsigned int oldstat;\n\tu32 irq_action;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int size;\n\tint (*get_rx_fifocnt)(struct mmci_host *, u32, int);\n\tu8 use_dma: 1;\n\tu8 dma_in_progress: 1;\n\tvoid *dma_priv;\n\ts32 next_cookie;\n\tstruct delayed_work ux500_busy_timeout_work;\n};\n\nstruct mmci_host_ops {\n\tint (*validate_data)(struct mmci_host *, struct mmc_data *);\n\tint (*prep_data)(struct mmci_host *, struct mmc_data *, bool);\n\tvoid (*unprep_data)(struct mmci_host *, struct mmc_data *, int);\n\tu32 (*get_datactrl_cfg)(struct mmci_host *);\n\tvoid (*get_next_data)(struct mmci_host *, struct mmc_data *);\n\tint (*dma_setup)(struct mmci_host *);\n\tvoid (*dma_release)(struct mmci_host *);\n\tint (*dma_start)(struct mmci_host *, unsigned int *);\n\tvoid (*dma_finalize)(struct mmci_host *, struct mmc_data *);\n\tvoid (*dma_error)(struct mmci_host *);\n\tvoid (*set_clkreg)(struct mmci_host *, unsigned int);\n\tvoid (*set_pwrreg)(struct mmci_host *, unsigned int);\n\tbool (*busy_complete)(struct mmci_host *, struct mmc_command *, u32, u32);\n\tvoid (*pre_sig_volt_switch)(struct mmci_host *);\n\tint (*post_sig_volt_switch)(struct mmci_host *, struct mmc_ios *);\n};\n\nstruct mmci_platform_data {\n\tunsigned int ocr_mask;\n\tunsigned int (*status)(struct device *);\n};\n\nstruct mmdc_pmu {\n\tstruct pmu pmu;\n\tvoid *mmdc_base;\n\tcpumask_t cpu;\n\tlong: 32;\n\tstruct hrtimer hrtimer;\n\tunsigned int active_events;\n\tint id;\n\tstruct device *dev;\n\tstruct perf_event *mmdc_events[6];\n\tstruct hlist_node node;\n\tconst struct fsl_mmdc_devtype_data *devtype_data;\n\tstruct clk *mmdc_ipg_clk;\n\tlong: 32;\n};\n\nstruct mmp_clk_unit {\n\tunsigned int nr_clks;\n\tstruct clk **clk_table;\n\tstruct clk_onecell_data clk_data;\n};\n\nstruct mmp2_clk_unit {\n\tstruct mmp_clk_unit unit;\n\tenum mmp2_clk_model model;\n\tstruct genpd_onecell_data pd_data;\n\tstruct generic_pm_domain *pm_domains[3];\n\tvoid *mpmu_base;\n\tvoid *apmu_base;\n\tvoid *apbc_base;\n};\n\nstruct mmp_clk_factor_masks;\n\nstruct u32_fract;\n\nstruct mmp_clk_factor {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct mmp_clk_factor_masks *masks;\n\tstruct u32_fract *ftbl;\n\tunsigned int ftbl_cnt;\n\tspinlock_t *lock;\n};\n\nstruct mmp_clk_factor_masks {\n\tunsigned int factor;\n\tunsigned int num_mask;\n\tunsigned int den_mask;\n\tunsigned int num_shift;\n\tunsigned int den_shift;\n\tunsigned int enable_mask;\n};\n\nstruct mmp_clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu32 mask;\n\tu32 val_enable;\n\tu32 val_disable;\n\tunsigned int flags;\n\tspinlock_t *lock;\n};\n\nstruct mmp_clk_mix_reg_info {\n\tvoid *reg_clk_ctrl;\n\tvoid *reg_clk_sel;\n\tu8 width_div;\n\tu8 shift_div;\n\tu8 width_mux;\n\tu8 shift_mux;\n\tu8 bit_fc;\n};\n\nstruct mmp_clk_mix_clk_table;\n\nstruct mmp_clk_mix {\n\tstruct clk_hw hw;\n\tstruct mmp_clk_mix_reg_info reg_info;\n\tstruct mmp_clk_mix_clk_table *table;\n\tu32 *mux_table;\n\tstruct clk_div_table *div_table;\n\tunsigned int table_size;\n\tu8 div_flags;\n\tu8 mux_flags;\n\tunsigned int type;\n\tspinlock_t *lock;\n};\n\nstruct mmp_clk_mix_clk_table {\n\tlong unsigned int rate;\n\tu8 parent_index;\n\tunsigned int divisor;\n\tunsigned int valid;\n};\n\nstruct mmp_clk_mix_config {\n\tstruct mmp_clk_mix_reg_info reg_info;\n\tstruct mmp_clk_mix_clk_table *table;\n\tunsigned int table_size;\n\tu32 *mux_table;\n\tstruct clk_div_table *div_table;\n\tu8 div_flags;\n\tu8 mux_flags;\n};\n\nstruct mmp_clk_pll {\n\tstruct clk_hw hw;\n\tlong unsigned int default_rate;\n\tvoid *enable_reg;\n\tu32 enable;\n\tvoid *reg;\n\tu8 shift;\n\tlong unsigned int input_rate;\n\tvoid *postdiv_reg;\n\tu8 postdiv_shift;\n};\n\nstruct mmp_clk_reset_cell {\n\tunsigned int clk_id;\n\tvoid *reg;\n\tu32 bits;\n\tunsigned int flags;\n\tspinlock_t *lock;\n};\n\nstruct mmp_clk_reset_unit {\n\tstruct reset_controller_dev rcdev;\n\tstruct mmp_clk_reset_cell *cells;\n};\n\nstruct mmp_intc_conf {\n\tunsigned int conf_enable;\n\tunsigned int conf_disable;\n\tunsigned int conf_mask;\n\tunsigned int conf2_mask;\n};\n\nstruct mmp_param_div_clk {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tspinlock_t *lock;\n};\n\nstruct mmp_param_fixed_factor_clk {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int mult;\n\tlong unsigned int div;\n\tlong unsigned int flags;\n};\n\nstruct mmp_param_fixed_rate_clk {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int fixed_rate;\n};\n\nstruct mmp_param_gate_clk {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu32 mask;\n\tu32 val_enable;\n\tu32 val_disable;\n\tunsigned int gate_flags;\n\tspinlock_t *lock;\n};\n\nstruct mmp_param_general_gate_clk {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 bit_idx;\n\tu8 gate_flags;\n\tspinlock_t *lock;\n};\n\nstruct mmp_param_mux_clk {\n\tunsigned int id;\n\tchar *name;\n\tconst char * const *parent_name;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 mux_flags;\n\tspinlock_t *lock;\n};\n\nstruct mmp_param_pll_clk {\n\tunsigned int id;\n\tchar *name;\n\tlong unsigned int default_rate;\n\tlong unsigned int enable_offset;\n\tu32 enable;\n\tlong unsigned int offset;\n\tu8 shift;\n\tlong unsigned int input_rate;\n\tlong unsigned int postdiv_offset;\n\tlong unsigned int postdiv_shift;\n};\n\nstruct mmp_pm_domain {\n\tstruct generic_pm_domain genpd;\n\tvoid *reg;\n\tspinlock_t *lock;\n\tu32 power_on;\n\tu32 reset;\n\tu32 clock_enable;\n\tunsigned int flags;\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct encoded_page;\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct encoded_page *encoded_pages[0];\n};\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n};\n\nstruct mmu_notifier_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tlong: 32;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct plt_entries;\n\nstruct mod_plt_sec {\n\tstruct elf32_shdr *plt;\n\tstruct plt_entries *plt_ent;\n\tint plt_count;\n};\n\nstruct unwind_table;\n\nstruct mod_arch_specific {\n\tstruct list_head unwind_list;\n\tstruct unwind_table *init_table;\n\tstruct mod_plt_sec core;\n\tstruct mod_plt_sec init;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf32_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct modctrl_match {\n\tu32 mode_cfg;\n\tu8 conv[6];\n};\n\nstruct mode_info {\n\tconst char *mode;\n\tu32 magic;\n\tstruct list_head list;\n};\n\nstruct mode_page_header {\n\t__be16 mode_data_length;\n\t__u8 medium_type;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 reserved3;\n\t__be16 desc_length;\n};\n\nstruct modesel_head {\n\t__u8 reserved1;\n\t__u8 medium;\n\t__u8 reserved2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_of_blocks_hi;\n\t__u8 number_of_blocks_med;\n\t__u8 number_of_blocks_lo;\n\t__u8 reserved3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n\tstruct mod_tree_node mtn;\n};\n\ntypedef struct tracepoint * const tracepoint_ptr_t;\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_event_call;\n\nstruct trace_eval_map;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[60];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_string {\n\tstruct list_head next;\n\tstruct module *module;\n\tchar *str;\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n\tlong: 32;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct mountres {\n\tint errno;\n\tstruct nfs_fh *fh;\n\tunsigned int *auth_count;\n\trpc_authflavor_t *auth_flavors;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tunsigned int can_map: 1;\n\tlong: 32;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tloff_t end_pos;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n\tunsigned int journalled_more_data: 1;\n\tlong: 32;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tlong: 32;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n\tlong: 32;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpc8xxx_gpio_chip {\n\tstruct gpio_generic_chip chip;\n\tvoid *regs;\n\traw_spinlock_t lock;\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tstruct irq_domain *irq;\n\tint irqn;\n};\n\nstruct mpc8xxx_gpio_devtype {\n\tint (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);\n\tint (*gpio_get)(struct gpio_chip *, unsigned int);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n};\n\nstruct mpfs_ccc_data {\n\tvoid **pll_base;\n\tstruct device *dev;\n\tstruct clk_hw_onecell_data hw_data;\n};\n\nstruct mpfs_ccc_out_hw_clock {\n\tstruct clk_divider divider;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n};\n\nstruct mpfs_ccc_pll_hw_clock {\n\tvoid *base;\n\tconst char *name;\n\tconst struct clk_parent_data *parents;\n\tunsigned int id;\n\tu32 reg_offset;\n\tu32 shift;\n\tu32 width;\n\tu32 flags;\n\tstruct clk_hw hw;\n\tstruct clk_init_data init;\n};\n\nstruct mpfs_cfg_clock {\n\tstruct regmap *map;\n\tconst struct clk_div_table *table;\n\tu8 map_offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n};\n\nstruct mpfs_cfg_hw_clock {\n\tstruct clk_hw hw;\n\tstruct mpfs_cfg_clock cfg;\n\tunsigned int id;\n};\n\nstruct mpfs_clock_data {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tvoid *base;\n\tvoid *msspll_base;\n\tstruct clk_hw_onecell_data hw_data;\n};\n\nstruct mpfs_msspll_hw_clock {\n\tvoid *base;\n\tstruct clk_hw hw;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n\tu32 shift;\n\tu32 width;\n\tu32 flags;\n};\n\nstruct mpfs_msspll_out_hw_clock {\n\tvoid *base;\n\tstruct clk_divider output;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n};\n\nstruct mpfs_periph_clock {\n\tstruct regmap *map;\n\tu8 map_offset;\n\tu8 shift;\n};\n\nstruct mpfs_periph_hw_clock {\n\tstruct clk_hw hw;\n\tstruct mpfs_periph_clock periph;\n\tunsigned int id;\n};\n\nstruct mpfs_reset {\n\tstruct regmap *regmap;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct mpic {\n\tvoid *base;\n\tvoid *per_cpu;\n\tint parent_irq;\n\tstruct irq_domain *domain;\n\tstruct irq_domain *ipi_domain;\n\tstruct irq_domain *msi_inner_domain;\n\tlong unsigned int msi_used[1];\n\tstruct mutex msi_lock;\n\tphys_addr_t msi_doorbell_addr;\n\tu32 msi_doorbell_mask;\n\tunsigned int msi_doorbell_start;\n\tunsigned int msi_doorbell_size;\n\tu32 doorbell_mask;\n};\n\nstruct mpidr_hash {\n\tu32 mask;\n\tu32 shift_aff[3];\n\tu32 bits;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mptcp_out_options {};\n\nstruct mptcp_sock {};\n\nstruct mpu3050 {\n\tstruct device *dev;\n\tstruct iio_mount_matrix orientation;\n\tstruct regmap *map;\n\tstruct mutex lock;\n\tint irq;\n\tstruct regulator_bulk_data regs[2];\n\tenum mpu3050_fullscale fullscale;\n\tenum mpu3050_lpf lpf;\n\tu8 divisor;\n\ts16 calibration[3];\n\tstruct iio_trigger *trig;\n\tbool hw_irq_trigger;\n\tbool irq_actl;\n\tbool irq_latch;\n\tbool irq_opendrain;\n\tbool pending_fifo_footer;\n\ts64 hw_timestamp;\n\tstruct i2c_mux_core *i2cmux;\n\tlong: 32;\n};\n\nstruct mpu_rgn {\n\tunion {\n\t\tu32 drbar;\n\t\tu32 prbar;\n\t};\n\tunion {\n\t\tu32 drsr;\n\t\tu32 prlar;\n\t};\n\tunion {\n\t\tu32 dracr;\n\t\tu32 unused;\n\t};\n};\n\nstruct mpu_rgn_info {\n\tunsigned int used;\n\tstruct mpu_rgn rgns[16];\n};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct mrw_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u8 write: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n\t__u8 reserved4;\n\t__u8 reserved5;\n};\n\nstruct msdos_dir_entry {\n\t__u8 name[11];\n\t__u8 attr;\n\t__u8 lcase;\n\t__u8 ctime_cs;\n\t__le16 ctime;\n\t__le16 cdate;\n\t__le16 adate;\n\t__le16 starthi;\n\t__le16 time;\n\t__le16 date;\n\t__le16 start;\n\t__le32 size;\n};\n\nstruct msdos_dir_slot {\n\t__u8 id;\n\t__u8 name0_4[10];\n\t__u8 attr;\n\t__u8 reserved;\n\t__u8 alias_checksum;\n\t__u8 name5_10[12];\n\t__le16 start;\n\t__u8 name11_12[4];\n};\n\nstruct msdos_inode_info {\n\tspinlock_t cache_lru_lock;\n\tstruct list_head cache_lru;\n\tint nr_caches;\n\tunsigned int cache_valid_id;\n\tlong: 32;\n\tloff_t mmu_private;\n\tint i_start;\n\tint i_logstart;\n\tint i_attrs;\n\tlong: 32;\n\tloff_t i_pos;\n\tstruct hlist_node i_fat_hash;\n\tstruct hlist_node i_dir_hash;\n\tstruct rw_semaphore truncate_lock;\n\tstruct timespec64 i_crtime;\n\tstruct inode vfs_inode;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct nls_table;\n\nstruct msdos_sb_info {\n\tshort unsigned int sec_per_clus;\n\tshort unsigned int cluster_bits;\n\tunsigned int cluster_size;\n\tunsigned char fats;\n\tunsigned char fat_bits;\n\tshort unsigned int fat_start;\n\tlong unsigned int fat_length;\n\tlong unsigned int dir_start;\n\tshort unsigned int dir_entries;\n\tlong unsigned int data_start;\n\tlong unsigned int max_cluster;\n\tlong unsigned int root_cluster;\n\tlong unsigned int fsinfo_sector;\n\tstruct mutex fat_lock;\n\tstruct mutex nfs_build_inode_lock;\n\tstruct mutex s_lock;\n\tunsigned int prev_free;\n\tunsigned int free_clusters;\n\tunsigned int free_clus_valid;\n\tstruct fat_mount_options options;\n\tstruct nls_table *nls_disk;\n\tstruct nls_table *nls_io;\n\tconst void *dir_ops;\n\tint dir_per_block;\n\tint dir_per_block_bits;\n\tunsigned int vol_id;\n\tint fatent_shift;\n\tconst struct fatent_operations *fatent_ops;\n\tstruct inode *fat_inode;\n\tstruct inode *fsinfo_inode;\n\tstruct ratelimit_state ratelimit;\n\tspinlock_t inode_hash_lock;\n\tstruct hlist_head inode_hashtable[256];\n\tspinlock_t dir_hash_lock;\n\tstruct hlist_head dir_hashtable[256];\n\tunsigned int dirty;\n\tstruct callback_head rcu;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n\tlong: 32;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong: 32;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n\tlong: 32;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tlong: 32;\n\tu64 iommu_msi_iova: 58;\n\tu64 iommu_msi_shift: 6;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msm_baud_map {\n\tu16 divisor;\n\tu8 code;\n\tu8 rxstale;\n};\n\nstruct msm_dma {\n\tstruct dma_chan *chan;\n\tenum dma_data_direction dir;\n\tunion {\n\t\tstruct {\n\t\t\tdma_addr_t phys;\n\t\t\tunsigned char *virt;\n\t\t\tunsigned int count;\n\t\t} rx;\n\t\tstruct scatterlist tx_sg;\n\t};\n\tdma_cookie_t cookie;\n\tu32 enable_bit;\n\tstruct dma_async_tx_descriptor *desc;\n};\n\nstruct msm_gpio_wakeirq_map {\n\tunsigned int gpio;\n\tunsigned int wakeirq;\n};\n\nstruct msm_pinctrl_soc_data;\n\nstruct msm_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctrl;\n\tstruct gpio_chip chip;\n\tstruct pinctrl_desc desc;\n\tint irq;\n\tbool intr_target_use_scm;\n\traw_spinlock_t lock;\n\tlong unsigned int dual_edge_irqs[10];\n\tlong unsigned int enabled_irqs[10];\n\tlong unsigned int skip_wake_irqs[10];\n\tlong unsigned int disabled_for_mux[10];\n\tlong unsigned int ever_gpio[10];\n\tconst struct msm_pinctrl_soc_data *soc;\n\tvoid *regs[4];\n\tu32 phys_base[4];\n};\n\nstruct msm_pingroup;\n\nstruct msm_pinctrl_soc_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct pinfunction *functions;\n\tunsigned int nfunctions;\n\tconst struct msm_pingroup *groups;\n\tunsigned int ngroups;\n\tunsigned int ngpios;\n\tbool pull_no_keeper;\n\tconst char * const *tiles;\n\tunsigned int ntiles;\n\tconst int *reserved_gpios;\n\tconst struct msm_gpio_wakeirq_map *wakeirq_map;\n\tunsigned int nwakeirq_map;\n\tbool wakeirq_dual_edge_errata;\n\tunsigned int gpio_func;\n\tunsigned int egpio_func;\n};\n\nstruct msm_pingroup {\n\tstruct pingroup grp;\n\tunsigned int *funcs;\n\tunsigned int nfuncs;\n\tu32 ctl_reg;\n\tu32 io_reg;\n\tu32 intr_cfg_reg;\n\tu32 intr_status_reg;\n\tu32 intr_target_reg;\n\tunsigned int tile: 2;\n\tunsigned int mux_bit: 5;\n\tunsigned int pull_bit: 5;\n\tunsigned int drv_bit: 5;\n\tunsigned int i2c_pull_bit: 5;\n\tunsigned int od_bit: 5;\n\tunsigned int egpio_enable: 5;\n\tunsigned int egpio_present: 5;\n\tunsigned int oe_bit: 5;\n\tunsigned int in_bit: 5;\n\tunsigned int out_bit: 5;\n\tunsigned int intr_enable_bit: 5;\n\tunsigned int intr_status_bit: 5;\n\tunsigned int intr_ack_high: 1;\n\tlong: 1;\n\tunsigned int intr_wakeup_present_bit: 5;\n\tunsigned int intr_wakeup_enable_bit: 5;\n\tunsigned int intr_target_bit: 5;\n\tunsigned int intr_target_width: 5;\n\tunsigned int intr_target_kpss_val: 5;\n\tunsigned int intr_raw_status_bit: 5;\n\tlong: 2;\n\tunsigned int intr_polarity_bit: 5;\n\tunsigned int intr_detection_bit: 5;\n\tunsigned int intr_detection_width: 5;\n};\n\nstruct msm_port {\n\tstruct uart_port uart;\n\tchar name[16];\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tunsigned int imr;\n\tint is_uartdm;\n\tunsigned int old_snap_state;\n\tbool break_detected;\n\tstruct msm_dma tx_dma;\n\tstruct msm_dma rx_dma;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong unsigned int msg_stime;\n\tlong unsigned int msg_stime_high;\n\tlong unsigned int msg_rtime;\n\tlong unsigned int msg_rtime_high;\n\tlong unsigned int msg_ctime;\n\tlong unsigned int msg_ctime_high;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct msr_reg_offset {\n\tunsigned int duty_val;\n\tunsigned int freq_ctrl;\n\tunsigned int duty_ctrl;\n\tunsigned int freq_val;\n};\n\nstruct mssr_mod_clk {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int parent;\n};\n\nstruct mst_intc_chip_data {\n\traw_spinlock_t lock;\n\tunsigned int irq_start;\n\tunsigned int nr_irqs;\n\tvoid *base;\n\tbool no_eoi;\n\tstruct list_head entry;\n\tu16 saved_polarity_conf[4];\n};\n\nstruct mstp_clock {\n\tstruct clk_hw hw;\n\tu32 index;\n\tstruct cpg_mssr_priv *priv;\n};\n\nstruct mstp_clock_group;\n\nstruct mstp_clock___2 {\n\tstruct clk_hw hw;\n\tu32 bit_index;\n\tstruct mstp_clock_group *group;\n};\n\nstruct mstp_clock_group {\n\tstruct clk_onecell_data data;\n\tvoid *smstpcr;\n\tvoid *mstpsr;\n\tspinlock_t lock;\n\tbool width_8bit;\n\tstruct clk *clks[0];\n};\n\nstruct mtd_blktrans_ops;\n\nstruct mtd_blktrans_dev {\n\tstruct mtd_blktrans_ops *tr;\n\tstruct list_head list;\n\tstruct mtd_info *mtd;\n\tstruct mutex lock;\n\tint devnum;\n\tbool bg_stop;\n\tlong unsigned int size;\n\tint readonly;\n\tint open;\n\tstruct kref ref;\n\tstruct gendisk *disk;\n\tstruct attribute_group *disk_attributes;\n\tstruct request_queue *rq;\n\tstruct list_head rq_list;\n\tstruct blk_mq_tag_set *tag_set;\n\tspinlock_t queue_lock;\n\tvoid *priv;\n\tbool writable;\n};\n\nstruct mtd_blktrans_ops {\n\tchar *name;\n\tint major;\n\tint part_bits;\n\tint blksize;\n\tint blkshift;\n\tint (*readsect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*writesect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*discard)(struct mtd_blktrans_dev *, long unsigned int, unsigned int);\n\tvoid (*background)(struct mtd_blktrans_dev *);\n\tint (*getgeo)(struct mtd_blktrans_dev *, struct hd_geometry *);\n\tint (*flush)(struct mtd_blktrans_dev *);\n\tint (*open)(struct mtd_blktrans_dev *);\n\tvoid (*release)(struct mtd_blktrans_dev *);\n\tvoid (*add_mtd)(struct mtd_blktrans_ops *, struct mtd_info *);\n\tvoid (*remove_dev)(struct mtd_blktrans_dev *);\n\tstruct list_head devs;\n\tstruct list_head list;\n\tstruct module *owner;\n};\n\nstruct mtd_chip_driver {\n\tstruct mtd_info * (*probe)(struct map_info *);\n\tvoid (*destroy)(struct mtd_info *);\n\tstruct module *module;\n\tchar *name;\n\tstruct list_head list;\n};\n\nstruct mtd_concat {\n\tstruct mtd_info mtd;\n\tint num_subdev;\n\tstruct mtd_info **subdev;\n};\n\nstruct mtd_dev_param {\n\tchar name[64];\n\tint ubi_num;\n\tint vid_hdr_offs;\n\tint max_beb_per1024;\n\tint enable_fm;\n\tint need_resv_pool;\n};\n\nstruct mtd_erase_region_info {\n\tuint64_t offset;\n\tuint32_t erasesize;\n\tuint32_t numblocks;\n\tlong unsigned int *lockmap;\n\tlong: 32;\n};\n\nstruct mtd_file_info {\n\tstruct mtd_info *mtd;\n\tenum mtd_file_modes mode;\n};\n\nstruct mtd_info_user {\n\t__u8 type;\n\t__u32 flags;\n\t__u32 size;\n\t__u32 erasesize;\n\t__u32 writesize;\n\t__u32 oobsize;\n\t__u64 padding;\n};\n\nstruct mtd_notifier {\n\tvoid (*add)(struct mtd_info *);\n\tvoid (*remove)(struct mtd_info *);\n\tstruct list_head list;\n};\n\nstruct mtd_oob_buf {\n\t__u32 start;\n\t__u32 length;\n\tunsigned char *ptr;\n};\n\nstruct mtd_oob_buf64 {\n\t__u64 start;\n\t__u32 pad;\n\t__u32 length;\n\t__u64 usr_ptr;\n};\n\nstruct mtd_req_stats;\n\nstruct mtd_oob_ops {\n\tunsigned int mode;\n\tsize_t len;\n\tsize_t retlen;\n\tsize_t ooblen;\n\tsize_t oobretlen;\n\tuint32_t ooboffs;\n\tuint8_t *datbuf;\n\tuint8_t *oobbuf;\n\tstruct mtd_req_stats *stats;\n};\n\nstruct mtd_oob_region {\n\tu32 offset;\n\tu32 length;\n};\n\nstruct mtd_ooblayout_ops {\n\tint (*ecc)(struct mtd_info *, int, struct mtd_oob_region *);\n\tint (*free)(struct mtd_info *, int, struct mtd_oob_region *);\n};\n\nstruct mtd_pairing_info {\n\tint pair;\n\tint group;\n};\n\nstruct mtd_pairing_scheme {\n\tint ngroups;\n\tint (*get_info)(struct mtd_info *, int, struct mtd_pairing_info *);\n\tint (*get_wunit)(struct mtd_info *, const struct mtd_pairing_info *);\n};\n\nstruct mtd_part_parser_data;\n\nstruct mtd_part_parser {\n\tstruct list_head list;\n\tstruct module *owner;\n\tconst char *name;\n\tconst struct of_device_id *of_match_table;\n\tint (*parse_fn)(struct mtd_info *, const struct mtd_partition **, struct mtd_part_parser_data *);\n\tvoid (*cleanup)(const struct mtd_partition *, int);\n};\n\nstruct mtd_part_parser_data {\n\tlong unsigned int origin;\n};\n\nstruct mtd_partition {\n\tconst char *name;\n\tconst char * const *types;\n\tuint64_t size;\n\tuint64_t offset;\n\tuint32_t mask_flags;\n\tuint32_t add_flags;\n\tstruct device_node *of_node;\n\tlong: 32;\n};\n\nstruct mtd_partitions {\n\tconst struct mtd_partition *parts;\n\tint nr_parts;\n\tconst struct mtd_part_parser *parser;\n};\n\nstruct mtd_read_req_ecc_stats {\n\t__u32 uncorrectable_errors;\n\t__u32 corrected_bitflips;\n\t__u32 max_bitflips;\n};\n\nstruct mtd_read_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n\tstruct mtd_read_req_ecc_stats ecc_stats;\n\tlong: 32;\n};\n\nstruct mtd_req_stats {\n\tunsigned int uncorrectable_errors;\n\tunsigned int corrected_bitflips;\n\tunsigned int max_bitflips;\n};\n\nstruct mtd_write_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n};\n\nstruct mtdblk_dev {\n\tstruct mtd_blktrans_dev mbd;\n\tint count;\n\tstruct mutex cache_mutex;\n\tunsigned char *cache_data;\n\tlong unsigned int cache_offset;\n\tunsigned int cache_size;\n\tenum {\n\t\tSTATE_EMPTY = 0,\n\t\tSTATE_CLEAN = 1,\n\t\tSTATE_DIRTY = 2,\n\t} cache_state;\n};\n\nstruct mtk8250_data {\n\tint line;\n\tunsigned int rx_pos;\n\tunsigned int clk_count;\n\tstruct clk *uart_clk;\n\tstruct clk *bus_clk;\n\tstruct uart_8250_dma *dma;\n\tenum dma_rx_status rx_status;\n\tint rx_wakeup_irq;\n};\n\nstruct mtk_cirq_chip_data {\n\tvoid *base;\n\tunsigned int ext_irq_start;\n\tunsigned int ext_irq_end;\n\tconst u32 *offsets;\n\tstruct irq_domain *domain;\n};\n\nstruct mtk_clk_cpumux {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 reg;\n\tu32 mask;\n\tu8 shift;\n};\n\nstruct mtk_gate;\n\nstruct mtk_composite;\n\nstruct mtk_clk_divider;\n\nstruct mtk_fixed_clk;\n\nstruct mtk_fixed_factor;\n\nstruct mtk_mux;\n\nstruct mtk_clk_rst_desc;\n\nstruct mtk_clk_desc {\n\tconst struct mtk_gate *clks;\n\tsize_t num_clks;\n\tconst struct mtk_composite *composite_clks;\n\tsize_t num_composite_clks;\n\tconst struct mtk_clk_divider *divider_clks;\n\tsize_t num_divider_clks;\n\tconst struct mtk_fixed_clk *fixed_clks;\n\tsize_t num_fixed_clks;\n\tconst struct mtk_fixed_factor *factor_clks;\n\tsize_t num_factor_clks;\n\tconst struct mtk_mux *mux_clks;\n\tsize_t num_mux_clks;\n\tconst struct mtk_clk_rst_desc *rst_desc;\n\tspinlock_t *clk_lock;\n\tbool shared_io;\n\tint (*clk_notifier_func)(struct device *, struct clk *);\n\tunsigned int mfg_clk_idx;\n\tbool need_runtime_pm;\n};\n\nstruct mtk_clk_divider {\n\tint id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tu32 div_reg;\n\tunsigned char div_shift;\n\tunsigned char div_width;\n\tunsigned char clk_divider_flags;\n\tconst struct clk_div_table *clk_div_table;\n};\n\nstruct mtk_clk_gate {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_hwv;\n\tconst struct mtk_gate *gate;\n};\n\nstruct mtk_clk_mux {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_hwv;\n\tconst struct mtk_mux *data;\n\tspinlock_t *lock;\n\tbool reparent;\n};\n\nstruct mtk_pll_data;\n\nstruct mtk_clk_pll {\n\tstruct device *dev;\n\tstruct clk_hw hw;\n\tvoid *base_addr;\n\tvoid *pd_addr;\n\tvoid *pwr_addr;\n\tvoid *tuner_addr;\n\tvoid *tuner_en_addr;\n\tvoid *pcw_addr;\n\tvoid *pcw_chg_addr;\n\tvoid *en_addr;\n\tvoid *en_set_addr;\n\tvoid *en_clr_addr;\n\tvoid *fenc_addr;\n\tconst struct mtk_pll_data *data;\n};\n\nstruct mtk_clk_rst_data {\n\tstruct regmap *regmap;\n\tstruct reset_controller_dev rcdev;\n\tconst struct mtk_clk_rst_desc *desc;\n};\n\nstruct mtk_clk_rst_desc {\n\tenum mtk_reset_version version;\n\tu16 *rst_bank_ofs;\n\tu32 rst_bank_nr;\n\tu16 *rst_idx_map;\n\tu32 rst_idx_map_nr;\n};\n\nstruct mtk_composite {\n\tint id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tconst char *parent;\n\tunsigned int flags;\n\tuint32_t mux_reg;\n\tuint32_t divider_reg;\n\tuint32_t gate_reg;\n\tsigned char mux_shift;\n\tsigned char mux_width;\n\tsigned char gate_shift;\n\tsigned char divider_shift;\n\tsigned char divider_width;\n\tu8 mux_flags;\n\tsigned char num_parents;\n};\n\nstruct mtk_desc_eint {\n\tunsigned char eintmux;\n\tunsigned char eintnum;\n};\n\nstruct mtk_desc_function {\n\tconst char *name;\n\tunsigned char muxval;\n};\n\nstruct pinctrl_pin_desc {\n\tunsigned int number;\n\tconst char *name;\n\tvoid *drv_data;\n};\n\nstruct mtk_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tconst struct mtk_desc_eint eint;\n\tconst struct mtk_desc_function *functions;\n};\n\nstruct mtk_drive_desc {\n\tu8 min;\n\tu8 max;\n\tu8 step;\n\tu8 scal;\n};\n\nstruct mtk_drv_group_desc {\n\tunsigned char min_drv;\n\tunsigned char max_drv;\n\tunsigned char low_bit;\n\tunsigned char high_bit;\n\tunsigned char step;\n};\n\nstruct mtk_eint_hw;\n\nstruct mtk_eint_regs;\n\nstruct mtk_eint_pin;\n\nstruct mtk_eint_xt;\n\nstruct mtk_eint {\n\tstruct device *dev;\n\tvoid **base;\n\tint nbase;\n\tu16 *base_pin_num;\n\tstruct irq_domain *domain;\n\tint irq;\n\tint *dual_edge;\n\tu16 **pin_list;\n\tu32 **wake_mask;\n\tu32 **cur_mask;\n\tconst struct mtk_eint_hw *hw;\n\tconst struct mtk_eint_regs *regs;\n\tstruct mtk_eint_pin *pins;\n\tu16 num_db_time;\n\tvoid *pctl;\n\tconst struct mtk_eint_xt *gpio_xlate;\n};\n\nstruct mtk_eint_desc {\n\tu16 eint_m;\n\tu16 eint_n;\n};\n\nstruct mtk_eint_hw {\n\tu8 port_mask;\n\tu8 ports;\n\tunsigned int ap_num;\n\tunsigned int db_cnt;\n\tconst unsigned int *db_time;\n};\n\nstruct mtk_eint_pin {\n\tu16 number;\n\tu8 instance;\n\tu8 index;\n\tbool debounce;\n\tbool dual_edge;\n};\n\nstruct mtk_eint_regs {\n\tunsigned int stat;\n\tunsigned int ack;\n\tunsigned int mask;\n\tunsigned int mask_set;\n\tunsigned int mask_clr;\n\tunsigned int sens;\n\tunsigned int sens_set;\n\tunsigned int sens_clr;\n\tunsigned int soft;\n\tunsigned int soft_set;\n\tunsigned int soft_clr;\n\tunsigned int pol;\n\tunsigned int pol_set;\n\tunsigned int pol_clr;\n\tunsigned int dom_en;\n\tunsigned int dbnc_ctrl;\n\tunsigned int dbnc_set;\n\tunsigned int dbnc_clr;\n};\n\nstruct mtk_eint_xt {\n\tint (*get_gpio_n)(void *, long unsigned int, unsigned int *, struct gpio_chip **);\n\tint (*get_gpio_state)(void *, long unsigned int);\n\tint (*set_gpio_as_eint)(void *, long unsigned int);\n};\n\nstruct mtk_pllfh_data;\n\nstruct mtk_fh {\n\tstruct mtk_clk_pll clk_pll;\n\tstruct fh_pll_regs regs;\n\tstruct mtk_pllfh_data *pllfh_data;\n\tconst struct fh_operation *ops;\n\tspinlock_t *lock;\n};\n\nstruct mtk_fixed_clk {\n\tint id;\n\tconst char *name;\n\tconst char *parent;\n\tlong unsigned int rate;\n};\n\nstruct mtk_fixed_factor {\n\tint id;\n\tconst char *name;\n\tconst char *parent_name;\n\tint mult;\n\tint div;\n\tlong unsigned int flags;\n};\n\nstruct mtk_func_desc {\n\tconst char *name;\n\tu8 muxval;\n};\n\nstruct mtk_gate_regs;\n\nstruct mtk_gate {\n\tint id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst struct mtk_gate_regs *regs;\n\tconst struct mtk_gate_regs *hwv_regs;\n\tint shift;\n\tconst struct clk_ops *ops;\n\tlong unsigned int flags;\n};\n\nstruct mtk_gate_regs {\n\tu32 sta_ofs;\n\tu32 clr_ofs;\n\tu32 set_ofs;\n};\n\nstruct mtk_gpueb_mbox_chan;\n\nstruct mtk_gpueb_mbox_variant;\n\nstruct mtk_gpueb_mbox {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tvoid *mbox_mmio;\n\tvoid *mbox_ctl;\n\tstruct mbox_controller mbox;\n\tstruct mtk_gpueb_mbox_chan *ch;\n\tint irq;\n\tconst struct mtk_gpueb_mbox_variant *v;\n\tlong: 32;\n};\n\nstruct mtk_gpueb_mbox_chan_desc;\n\nstruct mtk_gpueb_mbox_chan {\n\tstruct mtk_gpueb_mbox *ebm;\n\tchar *full_name;\n\tu8 num;\n\tatomic_t rx_status;\n\tconst struct mtk_gpueb_mbox_chan_desc *c;\n};\n\nstruct mtk_gpueb_mbox_chan_desc {\n\tconst char *name;\n\tconst u8 num;\n\tconst u16 tx_offset;\n\tconst u8 tx_len;\n\tconst u16 rx_offset;\n\tconst u8 rx_len;\n};\n\nstruct mtk_gpueb_mbox_variant {\n\tconst u8 num_channels;\n\tconst struct mtk_gpueb_mbox_chan_desc channels[0];\n};\n\nstruct mtk_mfg_mbox;\n\nstruct mtk_mfg_variant;\n\nstruct mtk_mfg {\n\tstruct generic_pm_domain pd;\n\tstruct platform_device *pdev;\n\tstruct clk *clk_eb;\n\tstruct clk_bulk_data *gpu_clks;\n\tstruct clk_hw clk_core_hw;\n\tstruct clk_hw clk_stack_hw;\n\tstruct regulator_bulk_data *gpu_regs;\n\tvoid *rpc;\n\tvoid *gpr;\n\tvoid *shared_mem;\n\tphys_addr_t shared_mem_phys;\n\tunsigned int shared_mem_size;\n\tu16 ghpm_en_reg;\n\tu32 ipi_magic;\n\tshort unsigned int num_gpu_opps;\n\tshort unsigned int num_stack_opps;\n\tstruct dev_pm_opp_data *gpu_opps;\n\tstruct dev_pm_opp_data *stack_opps;\n\tstruct mtk_mfg_mbox *gf_mbox;\n\tstruct mtk_mfg_mbox *slp_mbox;\n\tconst struct mtk_mfg_variant *variant;\n\tlong: 32;\n};\n\nstruct mtk_mfg_ipi_msg {\n\t__le32 magic;\n\t__le32 cmd;\n\t__le32 target;\n\t__le32 reserved;\n\tunion {\n\t\ts32 oppidx;\n\t\ts32 return_value;\n\t\t__le32 freq;\n\t\t__le32 volt;\n\t\t__le32 power;\n\t\t__le32 power_state;\n\t\t__le32 mode;\n\t\t__le32 value;\n\t\tstruct {\n\t\t\t__le64 base;\n\t\t\t__le32 size;\n\t\t\tlong: 32;\n\t\t} shared_mem;\n\t\tstruct {\n\t\t\t__le32 freq;\n\t\t\t__le32 volt;\n\t\t} custom;\n\t\tstruct {\n\t\t\t__le32 limiter;\n\t\t\ts32 ceiling_info;\n\t\t\ts32 floor_info;\n\t\t} set_limit;\n\t\tstruct {\n\t\t\t__le32 target;\n\t\t\t__le32 val;\n\t\t} mfg_cfg;\n\t\tstruct {\n\t\t\t__le32 target;\n\t\t\t__le32 val;\n\t\t} mssv;\n\t\tstruct {\n\t\t\ts32 gpu_oppidx;\n\t\t\ts32 stack_oppidx;\n\t\t} dual_commit;\n\t\tstruct {\n\t\t\t__le32 fgpu;\n\t\t\t__le32 vgpu;\n\t\t\t__le32 fstack;\n\t\t\t__le32 vstack;\n\t\t} dual_custom;\n\t} u;\n};\n\nstruct mtk_mfg_ipi_sleep_msg {\n\t__le32 event;\n\t__le32 state;\n\t__le32 magic;\n};\n\nstruct mtk_mfg_mbox {\n\tstruct mbox_client cl;\n\tstruct completion rx_done;\n\tstruct mtk_mfg *mfg;\n\tstruct mbox_chan *ch;\n\tvoid *rx_data;\n};\n\nstruct mtk_mfg_opp_entry {\n\t__le32 freq_khz;\n\t__le32 voltage_core;\n\t__le32 voltage_sram;\n\t__le32 posdiv;\n\t__le32 voltage_margin;\n\t__le32 power_mw;\n};\n\nstruct mtk_mfg_variant {\n\tconst char * const *clk_names;\n\tunsigned int num_clks;\n\tconst char * const *regulator_names;\n\tunsigned int num_regulators;\n\tunsigned int turbo_below;\n\tint (*init)(struct mtk_mfg *);\n};\n\nstruct mtk_mmsys_driver_data;\n\nstruct mtk_mmsys {\n\tvoid *regs;\n\tconst struct mtk_mmsys_driver_data *data;\n\tstruct platform_device *clks_pdev;\n\tstruct platform_device *drm_pdev;\n\tspinlock_t lock;\n\tstruct reset_controller_dev rcdev;\n\tstruct cmdq_client_reg cmdq_base;\n};\n\nstruct mtk_mmsys_routes;\n\nstruct mtk_mmsys_driver_data {\n\tconst char *clk_driver;\n\tconst struct mtk_mmsys_routes *routes;\n\tconst unsigned int num_routes;\n\tconst u16 sw0_rst_offset;\n\tconst u8 *rst_tb;\n\tconst u32 num_resets;\n\tconst bool is_vppsys;\n\tconst u8 vsync_len;\n};\n\nstruct mtk_mmsys_routes {\n\tu32 from_comp;\n\tu32 to_comp;\n\tu32 addr;\n\tu32 mask;\n\tu32 val;\n};\n\nstruct mtk_mutex {\n\tu8 id;\n\tbool claimed;\n};\n\nstruct mtk_mutex_data;\n\nstruct mtk_mutex_ctx {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tvoid *regs;\n\tstruct mtk_mutex mutex[10];\n\tconst struct mtk_mutex_data *data;\n\tphys_addr_t addr;\n\tstruct cmdq_client_reg cmdq_reg;\n};\n\nstruct mtk_mutex_data {\n\tconst u8 *mutex_mod;\n\tconst u8 *mutex_table_mod;\n\tconst u16 *mutex_sof;\n\tconst u16 mutex_mod_reg;\n\tconst u16 mutex_mod1_reg;\n\tconst u16 mutex_sof_reg;\n\tconst bool no_clk;\n};\n\nstruct mtk_mux {\n\tint id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tconst u8 *parent_index;\n\tunsigned int flags;\n\tu32 mux_ofs;\n\tu32 set_ofs;\n\tu32 clr_ofs;\n\tu32 upd_ofs;\n\tu32 hwv_set_ofs;\n\tu32 hwv_clr_ofs;\n\tu32 hwv_sta_ofs;\n\tu32 fenc_sta_mon_ofs;\n\tu8 mux_shift;\n\tu8 mux_width;\n\tu8 gate_shift;\n\ts8 upd_shift;\n\tu8 fenc_shift;\n\tconst struct clk_ops *ops;\n\tsigned char num_parents;\n};\n\nstruct mtk_mux_nb {\n\tstruct notifier_block nb;\n\tconst struct clk_ops *ops;\n\tu8 bypass_index;\n\tu8 original_index;\n};\n\nstruct mtk_pin_desc {\n\tunsigned int number;\n\tconst char *name;\n\tstruct mtk_eint_desc eint;\n\tu8 drv_n;\n\tstruct mtk_func_desc *funcs;\n};\n\nstruct mtk_pin_drv_grp {\n\tshort unsigned int pin;\n\tshort unsigned int offset;\n\tunsigned char bit;\n\tunsigned char grp;\n};\n\nstruct mtk_pin_field {\n\tu8 index;\n\tu32 offset;\n\tu32 mask;\n\tu8 bitpos;\n\tu8 next;\n};\n\nstruct mtk_pin_field_calc {\n\tu16 s_pin;\n\tu16 e_pin;\n\tu8 i_base;\n\tu32 s_addr;\n\tu8 x_addrs;\n\tu8 s_bit;\n\tu8 x_bits;\n\tu8 sz_reg;\n\tu8 fixed;\n};\n\nstruct mtk_pin_ies_smt_set {\n\tshort unsigned int start;\n\tshort unsigned int end;\n\tshort unsigned int offset;\n\tunsigned char bit;\n};\n\nstruct mtk_pin_reg_calc {\n\tconst struct mtk_pin_field_calc *range;\n\tunsigned int nranges;\n};\n\nstruct mtk_pin_rsel {\n\tu16 s_pin;\n\tu16 e_pin;\n\tu16 rsel_index;\n\tu32 up_rsel;\n\tu32 down_rsel;\n};\n\nstruct mtk_pinctrl;\n\nstruct mtk_pin_soc {\n\tconst struct mtk_pin_reg_calc *reg_cal;\n\tconst struct mtk_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct group_desc *grps;\n\tunsigned int ngrps;\n\tconst struct pinfunction *funcs;\n\tunsigned int nfuncs;\n\tconst struct mtk_eint_regs *eint_regs;\n\tconst struct mtk_eint_hw *eint_hw;\n\tstruct mtk_eint_pin *eint_pin;\n\tu8 gpio_m;\n\tbool ies_present;\n\tconst char * const *base_names;\n\tunsigned int nbase_names;\n\tconst unsigned int *pull_type;\n\tconst struct mtk_pin_rsel *pin_rsel;\n\tunsigned int npin_rsel;\n\tint (*bias_disable_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *);\n\tint (*bias_disable_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, int *);\n\tint (*bias_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool);\n\tint (*bias_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool, int *);\n\tint (*bias_set_combo)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32, u32);\n\tint (*bias_get_combo)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32 *, u32 *);\n\tint (*drive_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32);\n\tint (*drive_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, int *);\n\tint (*adv_pull_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool, u32);\n\tint (*adv_pull_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool, u32 *);\n\tint (*adv_drive_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32);\n\tint (*adv_drive_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32 *);\n\tvoid *driver_data;\n};\n\nstruct mtk_pin_spec_pupd_set_samereg {\n\tshort unsigned int pin;\n\tshort unsigned int offset;\n\tunsigned char pupd_bit;\n\tunsigned char r1_bit;\n\tunsigned char r0_bit;\n};\n\nstruct mtk_pinctrl_group;\n\nstruct mtk_pinctrl_devdata;\n\nstruct mtk_pinctrl___2 {\n\tstruct regmap *regmap1;\n\tstruct regmap *regmap2;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct device *dev;\n\tstruct gpio_chip *chip;\n\tstruct mtk_pinctrl_group *groups;\n\tunsigned int ngroups;\n\tconst char **grp_names;\n\tstruct pinctrl_dev *pctl_dev;\n\tconst struct mtk_pinctrl_devdata *devdata;\n\tstruct mtk_eint *eint;\n};\n\nstruct mtk_pinctrl {\n\tstruct pinctrl_dev *pctrl;\n\tvoid **base;\n\tu8 nbase;\n\tstruct device *dev;\n\tstruct gpio_chip chip;\n\tconst struct mtk_pin_soc *soc;\n\tstruct mtk_eint *eint;\n\tstruct mtk_pinctrl_group *groups;\n\tconst char **grp_names;\n\tspinlock_t lock;\n\tbool rsel_si_unit;\n};\n\nstruct mtk_pinctrl_devdata {\n\tconst struct mtk_desc_pin *pins;\n\tunsigned int npins;\n\tconst struct mtk_drv_group_desc *grp_desc;\n\tunsigned int n_grp_cls;\n\tconst struct mtk_pin_drv_grp *pin_drv_grp;\n\tunsigned int n_pin_drv_grps;\n\tconst struct mtk_pin_ies_smt_set *spec_ies;\n\tunsigned int n_spec_ies;\n\tconst struct mtk_pin_spec_pupd_set_samereg *spec_pupd;\n\tunsigned int n_spec_pupd;\n\tconst struct mtk_pin_ies_smt_set *spec_smt;\n\tunsigned int n_spec_smt;\n\tint (*spec_pull_set)(struct regmap *, const struct mtk_pinctrl_devdata *, unsigned int, bool, unsigned int);\n\tint (*spec_ies_smt_set)(struct regmap *, const struct mtk_pinctrl_devdata *, unsigned int, int, enum pin_config_param);\n\tvoid (*spec_pinmux_set)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*spec_dir_set)(unsigned int *, unsigned int);\n\tint (*mt8365_set_clr_mode)(struct regmap *, unsigned int, unsigned int, unsigned int, bool, bool);\n\tunsigned int dir_offset;\n\tunsigned int ies_offset;\n\tunsigned int smt_offset;\n\tunsigned int pullen_offset;\n\tunsigned int pullsel_offset;\n\tunsigned int dout_offset;\n\tunsigned int din_offset;\n\tunsigned int pinmux_offset;\n\tshort unsigned int type1_start;\n\tshort unsigned int type1_end;\n\tunsigned char port_shf;\n\tunsigned char port_mask;\n\tunsigned char port_align;\n\tstruct mtk_eint_hw eint_hw;\n\tstruct mtk_eint_regs *eint_regs;\n\tunsigned int mode_mask;\n\tunsigned int mode_per_reg;\n\tunsigned int mode_shf;\n};\n\nstruct mtk_pinctrl_group {\n\tconst char *name;\n\tlong unsigned int config;\n\tunsigned int pin;\n};\n\nstruct mtk_pll_div_table;\n\nstruct mtk_pll_data {\n\tint id;\n\tconst char *name;\n\tu32 reg;\n\tu32 pwr_reg;\n\tu32 en_mask;\n\tu32 fenc_sta_ofs;\n\tu32 pd_reg;\n\tu32 tuner_reg;\n\tu32 tuner_en_reg;\n\tu8 tuner_en_bit;\n\tint pd_shift;\n\tunsigned int flags;\n\tconst struct clk_ops *ops;\n\tu32 rst_bar_mask;\n\tlong unsigned int fmin;\n\tlong unsigned int fmax;\n\tint pcwbits;\n\tint pcwibits;\n\tu32 pcw_reg;\n\tint pcw_shift;\n\tu32 pcw_chg_reg;\n\tconst struct mtk_pll_div_table *div_table;\n\tconst char *parent_name;\n\tu32 en_reg;\n\tu32 en_set_reg;\n\tu32 en_clr_reg;\n\tu8 pll_en_bit;\n\tu8 pcw_chg_bit;\n\tu8 fenc_sta_bit;\n};\n\nstruct mtk_pll_div_table {\n\tu32 div;\n\tlong unsigned int freq;\n};\n\nstruct mtk_pllfh_data {\n\tstruct fh_pll_state state;\n\tconst struct fh_pll_data data;\n};\n\nstruct mtk_ref2usb_tx {\n\tstruct clk_hw hw;\n\tvoid *base_addr;\n};\n\nstruct mtk_rng {\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct hwrng rng;\n\tstruct device *dev;\n};\n\nstruct mtk_smp_boot_info {\n\tlong unsigned int smp_base;\n\tunsigned int jump_reg;\n\tunsigned int core_keys[7];\n\tunsigned int core_regs[7];\n};\n\nstruct mtk_spec_pinmux_set {\n\tshort unsigned int pin;\n\tshort unsigned int offset;\n\tunsigned char bit;\n};\n\nstruct mtk_spec_pull_set {\n\tunsigned char pin;\n\tunsigned char pupd_bit;\n\tshort unsigned int pupd_offset;\n\tshort unsigned int r0_offset;\n\tshort unsigned int r1_offset;\n\tunsigned char r0_bit;\n\tunsigned char r1_bit;\n};\n\nstruct mtk_sysirq_chip_data {\n\traw_spinlock_t lock;\n\tu32 nr_intpol_bases;\n\tvoid **intpol_bases;\n\tu32 *intpol_words;\n\tu8 *intpol_idx;\n\tu16 *which_word;\n};\n\nstruct mtk_wdt_data {\n\tint toprgu_sw_rst_num;\n\tbool has_swsysrst_en;\n};\n\nstruct mtk_wdt_dev {\n\tstruct watchdog_device wdt_dev;\n\tvoid *wdt_base;\n\tspinlock_t lock;\n\tstruct reset_controller_dev rcdev;\n\tbool disable_wdt_extrst;\n\tbool reset_by_toprgu;\n\tbool has_swsysrst_en;\n};\n\nstruct multi_mux {\n\tstruct clk_hw *hw1;\n\tstruct clk_hw *hw2;\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\nstruct mux_cfg {\n\tu32 reg_off;\n\tu8 shift;\n\tu8 width;\n\tu8 mux_flags;\n\tu32 *table;\n};\n\nstruct mux_chip;\n\nstruct mux_control {\n\tstruct semaphore lock;\n\tstruct mux_chip *chip;\n\tint cached_state;\n\tunsigned int states;\n\tint idle_state;\n\tktime_t last_change;\n};\n\nstruct mux_control_ops;\n\nstruct mux_chip {\n\tunsigned int controllers;\n\tlong: 32;\n\tstruct device dev;\n\tint id;\n\tconst struct mux_control_ops *ops;\n\tstruct mux_control mux[0];\n};\n\nstruct mux_control_ops {\n\tint (*set)(struct mux_control *, int);\n};\n\nstruct mux_data {\n\tu8 shift;\n};\n\nstruct mux_hwclock {\n\tstruct clk_hw hw;\n\tstruct clockgen *cg;\n\tconst struct clockgen_muxinfo *info;\n\tu32 *reg;\n\tu8 parent_to_clksel[16];\n\ts8 clksel_to_parent[16];\n\tint num_parents;\n};\n\nstruct mux_state {\n\tstruct mux_control *mux;\n\tunsigned int state;\n};\n\nstruct mv643xx_eth_platform_data {\n\tstruct platform_device *shared;\n\tint port_number;\n\tint phy_addr;\n\tstruct device_node *phy_node;\n\tu8 mac_addr[6];\n\tint speed;\n\tint duplex;\n\tphy_interface_t interface;\n\tint rx_queue_count;\n\tint tx_queue_count;\n\tint rx_queue_size;\n\tint tx_queue_size;\n\tlong unsigned int rx_sram_addr;\n\tint rx_sram_size;\n\tlong unsigned int tx_sram_addr;\n\tint tx_sram_size;\n};\n\nstruct rx_desc;\n\nstruct rx_queue {\n\tint index;\n\tint rx_ring_size;\n\tint rx_desc_count;\n\tint rx_curr_desc;\n\tint rx_used_desc;\n\tstruct rx_desc *rx_desc_area;\n\tdma_addr_t rx_desc_dma;\n\tint rx_desc_area_size;\n\tstruct sk_buff **rx_skb;\n};\n\nstruct tx_desc;\n\nstruct tx_queue {\n\tint index;\n\tint tx_ring_size;\n\tint tx_desc_count;\n\tint tx_curr_desc;\n\tint tx_used_desc;\n\tint tx_stop_threshold;\n\tint tx_wake_threshold;\n\tchar *tso_hdrs;\n\tdma_addr_t tso_hdrs_dma;\n\tstruct tx_desc *tx_desc_area;\n\tchar *tx_desc_mapping;\n\tdma_addr_t tx_desc_dma;\n\tint tx_desc_area_size;\n\tstruct sk_buff_head tx_skb;\n\tlong unsigned int tx_packets;\n\tlong unsigned int tx_bytes;\n\tlong unsigned int tx_dropped;\n};\n\nstruct mv643xx_eth_shared_private;\n\nstruct mv643xx_eth_private {\n\tstruct mv643xx_eth_shared_private *shared;\n\tvoid *base;\n\tint port_num;\n\tstruct net_device *dev;\n\tstruct timer_list mib_counters_timer;\n\tspinlock_t mib_counters_lock;\n\tstruct mib_counters mib_counters;\n\tstruct work_struct tx_timeout_task;\n\tstruct napi_struct napi;\n\tu32 int_mask;\n\tu8 oom;\n\tu8 work_link;\n\tu8 work_tx;\n\tu8 work_tx_end;\n\tu8 work_rx;\n\tu8 work_rx_refill;\n\tint skb_size;\n\tint rx_ring_size;\n\tlong unsigned int rx_desc_sram_addr;\n\tint rx_desc_sram_size;\n\tint rxq_count;\n\tstruct timer_list rx_oom;\n\tstruct rx_queue rxq[8];\n\tint tx_ring_size;\n\tlong unsigned int tx_desc_sram_addr;\n\tint tx_desc_sram_size;\n\tint txq_count;\n\tstruct tx_queue txq[8];\n\tstruct clk *clk;\n\tunsigned int t_clk;\n\tlong: 32;\n};\n\nstruct mv643xx_eth_shared_platform_data {\n\tstruct mbus_dram_target_info *dram;\n\tint tx_csum_limit;\n};\n\nstruct mv643xx_eth_shared_private {\n\tvoid *base;\n\tu32 win_protect;\n\tint extended_rx_coal_limit;\n\tint tx_bw_control;\n\tint tx_csum_limit;\n\tstruct clk *clk;\n};\n\nstruct mv643xx_eth_stats {\n\tchar stat_string[32];\n\tint sizeof_stat;\n\tint netdev_off;\n\tint mp_off;\n};\n\nstruct mv64xxx_i2c_regs {\n\tu8 addr;\n\tu8 ext_addr;\n\tu8 data;\n\tu8 control;\n\tu8 status;\n\tu8 clock;\n\tu8 soft_reset;\n};\n\nstruct mv64xxx_i2c_data {\n\tstruct i2c_msg *msgs;\n\tint num_msgs;\n\tint irq;\n\tu32 state;\n\tu32 action;\n\tu32 aborting;\n\tu32 cntl_bits;\n\tvoid *reg_base;\n\tstruct mv64xxx_i2c_regs reg_offsets;\n\tu32 addr1;\n\tu32 addr2;\n\tu32 bytes_left;\n\tu32 byte_posn;\n\tu32 send_stop;\n\tu32 block;\n\tint rc;\n\tu32 freq_m;\n\tu32 freq_n;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\twait_queue_head_t waitq;\n\tspinlock_t lock;\n\tstruct i2c_msg *msg;\n\tstruct i2c_adapter adapter;\n\tbool offload_enabled;\n\tbool errata_delay;\n\tstruct reset_control *rstc;\n\tbool irq_clear_inverted;\n\tbool clk_n_base_0;\n\tstruct i2c_bus_recovery_info rinfo;\n\tbool atomic;\n\tlong: 32;\n};\n\nstruct mv64xxx_i2c_pdata {\n\tu32 freq_m;\n\tu32 freq_n;\n\tu32 timeout;\n};\n\nstruct mv_cached_regs {\n\tu32 fiscfg;\n\tu32 ltmode;\n\tu32 haltcond;\n\tu32 unknown_rsvd;\n};\n\nstruct mv_crpb {\n\t__le16 id;\n\t__le16 flags;\n\t__le32 tmstmp;\n};\n\nstruct mv_crqb {\n\t__le32 sg_addr;\n\t__le32 sg_addr_hi;\n\t__le16 ctrl_flags;\n\t__le16 ata_cmd[11];\n};\n\nstruct mv_crqb_iie {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 flags;\n\t__le32 len;\n\t__le32 ata_cmd[4];\n};\n\nstruct mv_port_signal {\n\tu32 amps;\n\tu32 pre;\n};\n\nstruct mv_hw_ops;\n\nstruct mv_host_priv {\n\tu32 hp_flags;\n\tunsigned int board_idx;\n\tu32 main_irq_mask;\n\tstruct mv_port_signal signal[8];\n\tconst struct mv_hw_ops *ops;\n\tint n_ports;\n\tvoid *base;\n\tvoid *main_irq_cause_addr;\n\tvoid *main_irq_mask_addr;\n\tu32 irq_cause_offset;\n\tu32 irq_mask_offset;\n\tu32 unmask_all_irqs;\n\tstruct clk *clk;\n\tstruct clk **port_clks;\n\tstruct phy **port_phys;\n\tstruct dma_pool *crqb_pool;\n\tstruct dma_pool *crpb_pool;\n\tstruct dma_pool *sg_tbl_pool;\n};\n\nstruct mv_hw_ops {\n\tvoid (*phy_errata)(struct mv_host_priv *, void *, unsigned int);\n\tvoid (*enable_leds)(struct mv_host_priv *, void *);\n\tvoid (*read_preamp)(struct mv_host_priv *, int, void *);\n\tint (*reset_hc)(struct ata_host *, void *, unsigned int);\n\tvoid (*reset_flash)(struct mv_host_priv *, void *);\n\tvoid (*reset_bus)(struct ata_host *, void *);\n};\n\nstruct mv_sg;\n\nstruct mv_port_priv {\n\tstruct mv_crqb *crqb;\n\tdma_addr_t crqb_dma;\n\tstruct mv_crpb *crpb;\n\tdma_addr_t crpb_dma;\n\tstruct mv_sg *sg_tbl[32];\n\tdma_addr_t sg_tbl_dma[32];\n\tunsigned int req_idx;\n\tunsigned int resp_idx;\n\tu32 pp_flags;\n\tstruct mv_cached_regs cached;\n\tunsigned int delayed_eh_pmp_map;\n};\n\nstruct mv_sata_platform_data {\n\tint n_ports;\n};\n\nstruct mv_sg {\n\t__le32 addr;\n\t__le32 flags_size;\n\t__le32 addr_hi;\n\t__le32 reserved;\n};\n\nstruct mv_xor_device;\n\nstruct mv_xor_chan {\n\tint pending;\n\tspinlock_t lock;\n\tvoid *mmr_base;\n\tvoid *mmr_high_base;\n\tunsigned int idx;\n\tint irq;\n\tstruct list_head chain;\n\tstruct list_head free_slots;\n\tstruct list_head allocated_slots;\n\tstruct list_head completed_slots;\n\tdma_addr_t dma_desc_pool;\n\tvoid *dma_desc_pool_virt;\n\tsize_t pool_size;\n\tstruct dma_device dmadev;\n\tstruct dma_chan dmachan;\n\tint slots_allocated;\n\tstruct tasklet_struct irq_tasklet;\n\tint op_in_desc;\n\tchar dummy_src[128];\n\tchar dummy_dst[128];\n\tdma_addr_t dummy_src_addr;\n\tdma_addr_t dummy_dst_addr;\n\tu32 saved_config_reg;\n\tu32 saved_int_mask_reg;\n\tstruct mv_xor_device *xordev;\n};\n\nstruct mv_xor_channel_data {\n\tdma_cap_mask_t cap_mask;\n};\n\nstruct mv_xor_desc {\n\tu32 status;\n\tu32 crc32_result;\n\tu32 desc_command;\n\tu32 phy_next_desc;\n\tu32 byte_count;\n\tu32 phy_dest_addr;\n\tu32 phy_src_addr[8];\n\tu32 reserved0;\n\tu32 reserved1;\n};\n\nstruct mv_xor_desc_slot {\n\tstruct list_head node;\n\tstruct list_head sg_tx_list;\n\tenum dma_transaction_type type;\n\tvoid *hw_desc;\n\tu16 idx;\n\tstruct dma_async_tx_descriptor async_tx;\n};\n\nstruct mv_xor_device {\n\tvoid *xor_base;\n\tvoid *xor_high_base;\n\tstruct clk *clk;\n\tstruct mv_xor_chan *channels[2];\n\tint xor_type;\n\tu32 win_start[8];\n\tu32 win_end[8];\n};\n\nstruct mv_xor_platform_data {\n\tstruct mv_xor_channel_data *channels;\n};\n\nstruct mvebu_a3700_comphy_conf {\n\tunsigned int lane;\n\tenum phy_mode mode;\n\tint submode;\n};\n\nstruct mvebu_a3700_comphy_priv;\n\nstruct mvebu_a3700_comphy_lane {\n\tstruct mvebu_a3700_comphy_priv *priv;\n\tstruct device *dev;\n\tunsigned int id;\n\tenum phy_mode mode;\n\tint submode;\n\tbool invert_tx;\n\tbool invert_rx;\n};\n\nstruct mvebu_a3700_comphy_priv {\n\tvoid *comphy_regs;\n\tvoid *lane0_phy_regs;\n\tvoid *lane1_phy_regs;\n\tvoid *lane2_phy_indirect;\n\tspinlock_t lock;\n\tbool xtal_is_40m;\n};\n\nstruct mvebu_a3700_utmi_caps;\n\nstruct mvebu_a3700_utmi {\n\tvoid *regs;\n\tstruct regmap *usb_misc;\n\tconst struct mvebu_a3700_utmi_caps *caps;\n\tstruct phy *phy;\n};\n\nstruct phy_ops;\n\nstruct mvebu_a3700_utmi_caps {\n\tint usb32;\n\tconst struct phy_ops *ops;\n};\n\nstruct mvebu_pwm;\n\nstruct mvebu_gpio_chip {\n\tstruct gpio_chip chip;\n\tstruct regmap *regs;\n\tu32 offset;\n\tstruct regmap *percpu_regs;\n\tint irqbase;\n\tstruct irq_domain *domain;\n\tint soc_variant;\n\tstruct clk *clk;\n\tstruct mvebu_pwm *mvpwm;\n\tu32 out_reg;\n\tu32 io_conf_reg;\n\tu32 blink_en_reg;\n\tu32 in_pol_reg;\n\tu32 edge_mask_regs[4];\n\tu32 level_mask_regs[4];\n};\n\nstruct mvebu_mbus_state;\n\nstruct mvebu_mbus_soc_data {\n\tunsigned int num_wins;\n\tbool has_mbus_bridge;\n\tunsigned int (*win_cfg_offset)(const int);\n\tunsigned int (*win_remap_offset)(const int);\n\tvoid (*setup_cpu_target)(struct mvebu_mbus_state *);\n\tint (*save_cpu_target)(struct mvebu_mbus_state *, u32 *);\n\tint (*show_cpu_target)(struct mvebu_mbus_state *, struct seq_file *, void *);\n};\n\nstruct mvebu_mbus_win_data {\n\tu32 ctrl;\n\tu32 base;\n\tu32 remap_lo;\n\tu32 remap_hi;\n};\n\nstruct mvebu_mbus_state {\n\tvoid *mbuswins_base;\n\tvoid *sdramwins_base;\n\tvoid *mbusbridge_base;\n\tphys_addr_t sdramwins_phys_base;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_sdram;\n\tstruct dentry *debugfs_devs;\n\tstruct resource pcie_mem_aperture;\n\tstruct resource pcie_io_aperture;\n\tconst struct mvebu_mbus_soc_data *soc;\n\tint hw_io_coherency;\n\tu32 mbus_bridge_ctrl;\n\tu32 mbus_bridge_base;\n\tstruct mvebu_mbus_win_data wins[20];\n};\n\nstruct mvebu_mpp_ctrl_data;\n\nstruct mvebu_mpp_ctrl {\n\tconst char *name;\n\tu8 pid;\n\tu8 npins;\n\tunsigned int *pins;\n\tint (*mpp_get)(struct mvebu_mpp_ctrl_data *, unsigned int, long unsigned int *);\n\tint (*mpp_set)(struct mvebu_mpp_ctrl_data *, unsigned int, long unsigned int);\n\tint (*mpp_gpio_req)(struct mvebu_mpp_ctrl_data *, unsigned int);\n\tint (*mpp_gpio_dir)(struct mvebu_mpp_ctrl_data *, unsigned int, bool);\n};\n\nstruct mvebu_mpp_ctrl_data {\n\tunion {\n\t\tvoid *base;\n\t\tstruct {\n\t\t\tstruct regmap *map;\n\t\t\tu32 offset;\n\t\t} regmap;\n\t};\n};\n\nstruct mvebu_mpp_ctrl_setting {\n\tu8 val;\n\tconst char *name;\n\tconst char *subname;\n\tu8 variant;\n\tu8 flags;\n};\n\nstruct mvebu_mpp_mode {\n\tu8 pid;\n\tstruct mvebu_mpp_ctrl_setting *settings;\n};\n\nstruct mvebu_pcie_port;\n\nstruct mvebu_pcie {\n\tstruct platform_device *pdev;\n\tstruct mvebu_pcie_port *ports;\n\tstruct resource io;\n\tstruct resource realio;\n\tstruct resource mem;\n\tint nports;\n};\n\nstruct pci_bridge_emul_conf {\n\t__le16 vendor;\n\t__le16 device;\n\t__le16 command;\n\t__le16 status;\n\t__le32 class_revision;\n\tu8 cache_line_size;\n\tu8 latency_timer;\n\tu8 header_type;\n\tu8 bist;\n\t__le32 bar[2];\n\tu8 primary_bus;\n\tu8 secondary_bus;\n\tu8 subordinate_bus;\n\tu8 secondary_latency_timer;\n\tu8 iobase;\n\tu8 iolimit;\n\t__le16 secondary_status;\n\t__le16 membase;\n\t__le16 memlimit;\n\t__le16 pref_mem_base;\n\t__le16 pref_mem_limit;\n\t__le32 prefbaseupper;\n\t__le32 preflimitupper;\n\t__le16 iobaseupper;\n\t__le16 iolimitupper;\n\tu8 capabilities_pointer;\n\tu8 reserve[3];\n\t__le32 romaddr;\n\tu8 intline;\n\tu8 intpin;\n\t__le16 bridgectrl;\n};\n\nstruct pci_bridge_emul_pcie_conf {\n\tu8 cap_id;\n\tu8 next;\n\t__le16 cap;\n\t__le32 devcap;\n\t__le16 devctl;\n\t__le16 devsta;\n\t__le32 lnkcap;\n\t__le16 lnkctl;\n\t__le16 lnksta;\n\t__le32 slotcap;\n\t__le16 slotctl;\n\t__le16 slotsta;\n\t__le16 rootctl;\n\t__le16 rootcap;\n\t__le32 rootsta;\n\t__le32 devcap2;\n\t__le16 devctl2;\n\t__le16 devsta2;\n\t__le32 lnkcap2;\n\t__le16 lnkctl2;\n\t__le16 lnksta2;\n\t__le32 slotcap2;\n\t__le16 slotctl2;\n\t__le16 slotsta2;\n};\n\nstruct pci_bridge_emul_ops;\n\nstruct pci_bridge_reg_behavior;\n\nstruct pci_bridge_emul {\n\tstruct pci_bridge_emul_conf conf;\n\tstruct pci_bridge_emul_pcie_conf pcie_conf;\n\tconst struct pci_bridge_emul_ops *ops;\n\tstruct pci_bridge_reg_behavior *pci_regs_behavior;\n\tstruct pci_bridge_reg_behavior *pcie_cap_regs_behavior;\n\tvoid *data;\n\tu8 pcie_start;\n\tu8 ssid_start;\n\tbool has_pcie;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_id;\n};\n\nstruct mvebu_pcie_window {\n\tphys_addr_t base;\n\tphys_addr_t remap;\n\tsize_t size;\n};\n\nstruct mvebu_pcie_port {\n\tchar *name;\n\tvoid *base;\n\tu32 port;\n\tu32 lane;\n\tbool is_x4;\n\tint devfn;\n\tunsigned int mem_target;\n\tunsigned int mem_attr;\n\tunsigned int io_target;\n\tunsigned int io_attr;\n\tstruct clk *clk;\n\tstruct gpio_desc *reset_gpio;\n\tchar *reset_name;\n\tstruct pci_bridge_emul bridge;\n\tstruct device_node *dn;\n\tstruct mvebu_pcie *pcie;\n\tstruct mvebu_pcie_window memwin;\n\tstruct mvebu_pcie_window iowin;\n\tu32 saved_pcie_stat;\n\tstruct resource regs;\n\tu8 slot_power_limit_value;\n\tu8 slot_power_limit_scale;\n\tstruct irq_domain *intx_irq_domain;\n\traw_spinlock_t irq_lock;\n\tint intx_irq;\n};\n\nstruct mvebu_pinctrl_group;\n\nstruct mvebu_pinctrl_function;\n\nstruct mvebu_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_desc desc;\n\tstruct mvebu_pinctrl_group *groups;\n\tunsigned int num_groups;\n\tstruct mvebu_pinctrl_function *functions;\n\tunsigned int num_functions;\n\tu8 variant;\n};\n\nstruct mvebu_pinctrl_function {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int num_groups;\n};\n\nstruct mvebu_pinctrl_group {\n\tconst char *name;\n\tconst struct mvebu_mpp_ctrl *ctrl;\n\tstruct mvebu_mpp_ctrl_data *data;\n\tstruct mvebu_mpp_ctrl_setting *settings;\n\tunsigned int num_settings;\n\tunsigned int gid;\n\tunsigned int *pins;\n\tunsigned int npins;\n};\n\nstruct mvebu_pinctrl_soc_info {\n\tu8 variant;\n\tconst struct mvebu_mpp_ctrl *controls;\n\tstruct mvebu_mpp_ctrl_data *control_data;\n\tint ncontrols;\n\tstruct mvebu_mpp_mode *modes;\n\tint nmodes;\n\tstruct pinctrl_gpio_range *gpioranges;\n\tint ngpioranges;\n};\n\nstruct mvebu_pwm {\n\tstruct regmap *regs;\n\tu32 offset;\n\tlong unsigned int clk_rate;\n\tstruct gpio_desc *gpiod;\n\tspinlock_t lock;\n\tstruct mvebu_gpio_chip *mvchip;\n\tu32 blink_select;\n\tu32 blink_on_duration;\n\tu32 blink_off_duration;\n};\n\nstruct mvebu_system_controller {\n\tu32 rstoutn_mask_offset;\n\tu32 system_soft_reset_offset;\n\tu32 rstoutn_mask_reset_out_en;\n\tu32 system_soft_reset;\n\tu32 resume_boot_addr;\n\tu32 dev_id;\n\tu32 rev_id;\n};\n\nstruct mvneta_bm_pool;\n\nstruct mvneta_bm {\n\tvoid *reg_base;\n\tstruct clk *clk;\n\tstruct platform_device *pdev;\n\tstruct gen_pool *bppi_pool;\n\tvoid *bppi_virt_addr;\n\tdma_addr_t bppi_phys_addr;\n\tstruct mvneta_bm_pool *bm_pools;\n};\n\nstruct mvneta_bm_pool {\n\tstruct hwbm_pool hwbm_pool;\n\tu8 id;\n\tenum mvneta_bm_type type;\n\tint pkt_size;\n\tu32 buf_size;\n\tu32 *virt_addr;\n\tdma_addr_t phys_addr;\n\tu8 port_map;\n\tstruct mvneta_bm *priv;\n};\n\nstruct mvneta_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 xdp_redirect;\n\tu64 xdp_pass;\n\tu64 xdp_drop;\n\tu64 xdp_xmit;\n\tu64 xdp_xmit_err;\n\tu64 xdp_tx;\n\tu64 xdp_tx_err;\n};\n\nstruct mvneta_ethtool_stats {\n\tstruct mvneta_stats ps;\n\tu64 skb_alloc_error;\n\tu64 refill_error;\n};\n\nstruct mvneta_port;\n\nstruct mvneta_pcpu_port {\n\tstruct mvneta_port *pp;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tu32 cause_rx_tx;\n\tlong: 32;\n};\n\nstruct mvneta_pcpu_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tstruct mvneta_ethtool_stats es;\n\tu64 rx_dropped;\n\tu64 rx_errors;\n};\n\nstruct mvneta_rx_queue;\n\nstruct mvneta_tx_queue;\n\nstruct mvneta_port {\n\tu8 id;\n\tstruct mvneta_pcpu_port *ports;\n\tstruct mvneta_pcpu_stats *stats;\n\tlong unsigned int state;\n\tint pkt_size;\n\tvoid *base;\n\tstruct mvneta_rx_queue *rxqs;\n\tstruct mvneta_tx_queue *txqs;\n\tstruct net_device *dev;\n\tstruct hlist_node node_online;\n\tstruct hlist_node node_dead;\n\tint rxq_def;\n\tspinlock_t lock;\n\tbool is_stopped;\n\tu32 cause_rx_tx;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tstruct clk *clk;\n\tstruct clk *clk_bus;\n\tu8 mcast_count[256];\n\tu16 tx_ring_size;\n\tu16 rx_ring_size;\n\tphy_interface_t phy_interface;\n\tstruct device_node *dn;\n\tunsigned int tx_csum_limit;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tstruct phylink_pcs phylink_pcs;\n\tstruct phy *comphy;\n\tstruct mvneta_bm *bm_priv;\n\tstruct mvneta_bm_pool *pool_long;\n\tstruct mvneta_bm_pool *pool_short;\n\tint bm_win_id;\n\tu64 ethtool_stats[42];\n\tu32 indir[1];\n\tbool neta_armada3700;\n\tbool neta_ac5;\n\tu16 rx_offset_correction;\n\tconst struct mbus_dram_target_info *dram_target_info;\n\tlong: 32;\n};\n\nstruct mvneta_rx_desc {\n\tu32 status;\n\tu16 reserved1;\n\tu16 data_size;\n\tu32 buf_phys_addr;\n\tu32 reserved2;\n\tu32 buf_cookie;\n\tu16 reserved3;\n\tu16 reserved4;\n\tu32 reserved5;\n\tu32 reserved6;\n};\n\nstruct mvneta_rx_queue {\n\tu8 id;\n\tint size;\n\tu32 pkts_coal;\n\tu32 time_coal;\n\tstruct page_pool *page_pool;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xdp_rxq;\n\tvoid **buf_virt_addr;\n\tstruct mvneta_rx_desc *descs;\n\tdma_addr_t descs_phys;\n\tint last_desc;\n\tint next_desc_to_proc;\n\tint first_to_refill;\n\tu32 refill_num;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct mvneta_statistic {\n\tshort unsigned int offset;\n\tshort unsigned int type;\n\tconst char name[32];\n};\n\nstruct mvneta_tx_buf {\n\tenum mvneta_tx_buf_type type;\n\tunion {\n\t\tstruct xdp_frame *xdpf;\n\t\tstruct sk_buff *skb;\n\t};\n};\n\nstruct mvneta_tx_desc {\n\tu32 command;\n\tu16 reserved1;\n\tu16 data_size;\n\tu32 buf_phys_addr;\n\tu32 reserved2;\n\tu32 reserved3[4];\n};\n\nstruct mvneta_tx_queue {\n\tu8 id;\n\tint size;\n\tint count;\n\tint pending;\n\tint tx_stop_threshold;\n\tint tx_wake_threshold;\n\tstruct mvneta_tx_buf *buf;\n\tint txq_put_index;\n\tint txq_get_index;\n\tu32 done_pkts_coal;\n\tstruct mvneta_tx_desc *descs;\n\tdma_addr_t descs_phys;\n\tint last_desc;\n\tint next_desc_to_proc;\n\tchar *tso_hdrs[32];\n\tdma_addr_t tso_hdrs_phys[32];\n\tcpumask_t affinity_mask;\n};\n\nstruct mvsd_host {\n\tvoid *base;\n\tstruct mmc_request *mrq;\n\tspinlock_t lock;\n\tunsigned int xfer_mode;\n\tunsigned int intr_en;\n\tunsigned int ctrl;\n\tunsigned int pio_size;\n\tvoid *pio_ptr;\n\tunsigned int sg_frags;\n\tunsigned int ns_per_clk;\n\tunsigned int clock;\n\tunsigned int base_clock;\n\tstruct timer_list timer;\n\tstruct mmc_host *mmc;\n\tstruct device *dev;\n\tstruct clk *clk;\n};\n\nstruct mxc_extra_irq {\n\tint (*set_irq_fiq)(unsigned int, unsigned int);\n};\n\nstruct mxc_gpio_hwdata {\n\tunsigned int dr_reg;\n\tunsigned int gdir_reg;\n\tunsigned int psr_reg;\n\tunsigned int icr1_reg;\n\tunsigned int icr2_reg;\n\tunsigned int imr_reg;\n\tunsigned int isr_reg;\n\tint edge_sel_reg;\n\tunsigned int low_level;\n\tunsigned int high_level;\n\tunsigned int rise_edge;\n\tunsigned int fall_edge;\n};\n\nstruct mxc_gpio_reg_saved {\n\tu32 icr1;\n\tu32 icr2;\n\tu32 imr;\n\tu32 gdir;\n\tu32 edge_sel;\n\tu32 dr;\n};\n\nstruct mxc_gpio_port {\n\tstruct list_head node;\n\tvoid *base;\n\tstruct clk *clk;\n\tint irq;\n\tint irq_high;\n\tvoid (*mx_irq_handler)(struct irq_desc *);\n\tstruct irq_domain *domain;\n\tstruct gpio_generic_chip gen_gc;\n\tstruct device *dev;\n\tu32 both_edges;\n\tstruct mxc_gpio_reg_saved gpio_saved_reg;\n\tbool power_off;\n\tu32 wakeup_pads;\n\tbool is_pad_wakeup;\n\tu32 pad_type[32];\n\tconst struct mxc_gpio_hwdata *hwdata;\n};\n\nstruct mxs_dma_ccw {\n\tu32 next;\n\tu16 bits;\n\tu16 xfer_bytes;\n\tu32 bufaddr;\n\tu32 pio_words[16];\n};\n\nstruct mxs_dma_engine;\n\nstruct mxs_dma_chan {\n\tstruct mxs_dma_engine *mxs_dma;\n\tstruct dma_chan chan;\n\tstruct dma_async_tx_descriptor desc;\n\tstruct tasklet_struct tasklet;\n\tunsigned int chan_irq;\n\tstruct mxs_dma_ccw *ccw;\n\tdma_addr_t ccw_phys;\n\tint desc_count;\n\tenum dma_status status;\n\tunsigned int flags;\n\tbool reset;\n};\n\nstruct mxs_dma_engine {\n\tenum mxs_dma_id dev_id;\n\tenum mxs_dma_devtype type;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct dma_device dma_device;\n\tstruct mxs_dma_chan mxs_chans[16];\n\tstruct platform_device *pdev;\n\tunsigned int nr_channels;\n};\n\nstruct mxs_dma_filter_param {\n\tunsigned int chan_id;\n};\n\nstruct mxs_dma_type {\n\tenum mxs_dma_id id;\n\tenum mxs_dma_devtype type;\n};\n\nstruct mxs_phy_data;\n\nstruct mxs_phy {\n\tstruct usb_phy phy;\n\tstruct clk *clk;\n\tconst struct mxs_phy_data *data;\n\tstruct regmap *regmap_anatop;\n\tstruct regmap *regmap_sim;\n\tint port_id;\n\tu32 tx_reg_set;\n\tu32 tx_reg_mask;\n\tstruct regulator *phy_3p0;\n};\n\nstruct mxs_phy_data {\n\tunsigned int flags;\n};\n\nstruct my_u0 {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u1 {\n\t__le64 a;\n\t__le64 b;\n\t__le64 c;\n\t__le64 d;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[8];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[128];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct nand_bbt_descr {\n\tint options;\n\tint pages[8];\n\tint offs;\n\tint veroffs;\n\tuint8_t version[8];\n\tint len;\n\tint maxblocks;\n\tint reserved_block_code;\n\tuint8_t *pattern;\n};\n\nstruct nand_controller_ops {\n\tint (*attach_chip)(struct nand_chip *);\n\tvoid (*detach_chip)(struct nand_chip *);\n\tint (*exec_op)(struct nand_chip *, const struct nand_operation *, bool);\n\tint (*setup_interface)(struct nand_chip *, int, const struct nand_interface_config *);\n};\n\nstruct nand_ecc_step_info;\n\nstruct nand_ecc_caps {\n\tconst struct nand_ecc_step_info *stepinfos;\n\tint nstepinfos;\n\tint (*calc_ecc_bytes)(int, int);\n};\n\nstruct nand_ecc_engine_ops;\n\nstruct nand_ecc_engine {\n\tstruct device *dev;\n\tstruct list_head node;\n\tconst struct nand_ecc_engine_ops *ops;\n\tenum nand_ecc_engine_integration integration;\n\tvoid *priv;\n};\n\nstruct nand_page_io_req;\n\nstruct nand_ecc_engine_ops {\n\tint (*init_ctx)(struct nand_device *);\n\tvoid (*cleanup_ctx)(struct nand_device *);\n\tint (*prepare_io_req)(struct nand_device *, struct nand_page_io_req *);\n\tint (*finish_io_req)(struct nand_device *, struct nand_page_io_req *);\n};\n\nstruct nand_pos {\n\tunsigned int target;\n\tunsigned int lun;\n\tunsigned int plane;\n\tunsigned int eraseblock;\n\tunsigned int page;\n};\n\nstruct nand_page_io_req {\n\tenum nand_page_io_req_type type;\n\tstruct nand_pos pos;\n\tunsigned int dataoffs;\n\tunsigned int datalen;\n\tunion {\n\t\tconst void *out;\n\t\tvoid *in;\n\t} databuf;\n\tunsigned int ooboffs;\n\tunsigned int ooblen;\n\tunion {\n\t\tconst void *out;\n\t\tvoid *in;\n\t} oobbuf;\n\tint mode;\n\tbool continuous;\n};\n\nstruct nand_ecc_req_tweak_ctx {\n\tstruct nand_page_io_req orig_req;\n\tstruct nand_device *nand;\n\tunsigned int page_buffer_size;\n\tunsigned int oob_buffer_size;\n\tvoid *spare_databuf;\n\tvoid *spare_oobbuf;\n\tbool bounce_data;\n\tbool bounce_oob;\n};\n\nstruct nand_ecc_step_info {\n\tint stepsize;\n\tconst int *strengths;\n\tint nstrengths;\n};\n\nstruct nand_ecc_sw_hamming_conf {\n\tstruct nand_ecc_req_tweak_ctx req_ctx;\n\tunsigned int code_size;\n\tu8 *calc_buf;\n\tu8 *code_buf;\n\tunsigned int sm_order;\n};\n\nstruct nand_oobfree {\n\t__u32 offset;\n\t__u32 length;\n};\n\nstruct nand_ecclayout_user {\n\t__u32 eccbytes;\n\t__u32 eccpos[64];\n\t__u32 oobavail;\n\tstruct nand_oobfree oobfree[8];\n};\n\nstruct nand_flash_dev {\n\tchar *name;\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t mfr_id;\n\t\t\tuint8_t dev_id;\n\t\t};\n\t\tuint8_t id[8];\n\t};\n\tunsigned int pagesize;\n\tunsigned int chipsize;\n\tunsigned int erasesize;\n\tunsigned int options;\n\tuint16_t id_len;\n\tuint16_t oobsize;\n\tstruct {\n\t\tuint16_t strength_ds;\n\t\tuint16_t step_ds;\n\t} ecc;\n};\n\nstruct nand_sdr_timings {\n\tu64 tBERS_max;\n\tu32 tCCS_min;\n\tlong: 32;\n\tu64 tPROG_max;\n\tu64 tR_max;\n\tu32 tALH_min;\n\tu32 tADL_min;\n\tu32 tALS_min;\n\tu32 tAR_min;\n\tu32 tCEA_max;\n\tu32 tCEH_min;\n\tu32 tCH_min;\n\tu32 tCHZ_max;\n\tu32 tCLH_min;\n\tu32 tCLR_min;\n\tu32 tCLS_min;\n\tu32 tCOH_min;\n\tu32 tCS_min;\n\tu32 tDH_min;\n\tu32 tDS_min;\n\tu32 tFEAT_max;\n\tu32 tIR_min;\n\tu32 tITC_max;\n\tu32 tRC_min;\n\tu32 tREA_max;\n\tu32 tREH_min;\n\tu32 tRHOH_min;\n\tu32 tRHW_min;\n\tu32 tRHZ_max;\n\tu32 tRLOH_min;\n\tu32 tRP_min;\n\tu32 tRR_min;\n\tlong: 32;\n\tu64 tRST_max;\n\tu32 tWB_max;\n\tu32 tWC_min;\n\tu32 tWH_min;\n\tu32 tWHR_min;\n\tu32 tWP_min;\n\tu32 tWW_min;\n};\n\nstruct nand_nvddr_timings {\n\tu64 tBERS_max;\n\tu32 tCCS_min;\n\tlong: 32;\n\tu64 tPROG_max;\n\tu64 tR_max;\n\tu32 tAC_min;\n\tu32 tAC_max;\n\tu32 tADL_min;\n\tu32 tCAD_min;\n\tu32 tCAH_min;\n\tu32 tCALH_min;\n\tu32 tCALS_min;\n\tu32 tCAS_min;\n\tu32 tCEH_min;\n\tu32 tCH_min;\n\tu32 tCK_min;\n\tu32 tCS_min;\n\tu32 tDH_min;\n\tu32 tDQSCK_min;\n\tu32 tDQSCK_max;\n\tu32 tDQSD_min;\n\tu32 tDQSD_max;\n\tu32 tDQSHZ_max;\n\tu32 tDQSQ_max;\n\tu32 tDS_min;\n\tu32 tDSC_min;\n\tu32 tFEAT_max;\n\tu32 tITC_max;\n\tu32 tQHS_max;\n\tu32 tRHW_min;\n\tu32 tRR_min;\n\tu32 tRST_max;\n\tu32 tWB_max;\n\tu32 tWHR_min;\n\tu32 tWRCK_min;\n\tu32 tWW_min;\n\tlong: 32;\n};\n\nstruct nand_timings {\n\tunsigned int mode;\n\tlong: 32;\n\tunion {\n\t\tstruct nand_sdr_timings sdr;\n\t\tstruct nand_nvddr_timings nvddr;\n\t};\n};\n\nstruct nand_interface_config {\n\tenum nand_interface_type type;\n\tlong: 32;\n\tstruct nand_timings timings;\n};\n\nstruct nand_jedec_params {\n\tu8 sig[4];\n\t__le16 revision;\n\t__le16 features;\n\tu8 opt_cmd[3];\n\t__le16 sec_cmd;\n\tu8 num_of_param_pages;\n\tu8 reserved0[18];\n\tchar manufacturer[12];\n\tchar model[20];\n\tu8 jedec_id[6];\n\tu8 reserved1[10];\n\t__le32 byte_per_page;\n\t__le16 spare_bytes_per_page;\n\tu8 reserved2[6];\n\t__le32 pages_per_block;\n\t__le32 blocks_per_lun;\n\tu8 lun_count;\n\tu8 addr_cycles;\n\tu8 bits_per_cell;\n\tu8 programs_per_page;\n\tu8 multi_plane_addr;\n\tu8 multi_plane_op_attr;\n\tu8 reserved3[38];\n\t__le16 async_sdr_speed_grade;\n\t__le16 toggle_ddr_speed_grade;\n\t__le16 sync_ddr_speed_grade;\n\tu8 async_sdr_features;\n\tu8 toggle_ddr_features;\n\tu8 sync_ddr_features;\n\t__le16 t_prog;\n\t__le16 t_bers;\n\t__le16 t_r;\n\t__le16 t_r_multi_plane;\n\t__le16 t_ccs;\n\t__le16 io_pin_capacitance_typ;\n\t__le16 input_pin_capacitance_typ;\n\t__le16 clk_pin_capacitance_typ;\n\tu8 driver_strength_support;\n\t__le16 t_adl;\n\tu8 reserved4[36];\n\tu8 guaranteed_good_blocks;\n\t__le16 guaranteed_block_endurance;\n\tstruct jedec_ecc_info ecc_info[4];\n\tu8 reserved5[29];\n\tu8 reserved6[148];\n\t__le16 vendor_rev_num;\n\tu8 reserved7[88];\n\t__le16 crc;\n} __attribute__((packed));\n\nstruct nand_manufacturer_ops;\n\nstruct nand_manufacturer_desc {\n\tint id;\n\tchar *name;\n\tconst struct nand_manufacturer_ops *ops;\n};\n\nstruct nand_onfi_params;\n\nstruct nand_manufacturer_ops {\n\tvoid (*detect)(struct nand_chip *);\n\tint (*init)(struct nand_chip *);\n\tvoid (*cleanup)(struct nand_chip *);\n\tvoid (*fixup_onfi_param_page)(struct nand_chip *, struct nand_onfi_params *);\n};\n\nstruct nand_onfi_params {\n\tu8 sig[4];\n\t__le16 revision;\n\t__le16 features;\n\t__le16 opt_cmd;\n\tu8 reserved0[2];\n\t__le16 ext_param_page_length;\n\tu8 num_of_param_pages;\n\tu8 reserved1[17];\n\tchar manufacturer[12];\n\tchar model[20];\n\tu8 jedec_id;\n\t__le16 date_code;\n\tu8 reserved2[13];\n\t__le32 byte_per_page;\n\t__le16 spare_bytes_per_page;\n\t__le32 data_bytes_per_ppage;\n\t__le16 spare_bytes_per_ppage;\n\t__le32 pages_per_block;\n\t__le32 blocks_per_lun;\n\tu8 lun_count;\n\tu8 addr_cycles;\n\tu8 bits_per_cell;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 guaranteed_good_blocks;\n\t__le16 guaranteed_block_endurance;\n\tu8 programs_per_page;\n\tu8 ppage_attr;\n\tu8 ecc_bits;\n\tu8 interleaved_bits;\n\tu8 interleaved_ops;\n\tu8 reserved3[13];\n\tu8 io_pin_capacitance_max;\n\t__le16 sdr_timing_modes;\n\t__le16 program_cache_timing_mode;\n\t__le16 t_prog;\n\t__le16 t_bers;\n\t__le16 t_r;\n\t__le16 t_ccs;\n\tu8 nvddr_timing_modes;\n\tu8 nvddr2_timing_modes;\n\tu8 nvddr_nvddr2_features;\n\t__le16 clk_pin_capacitance_typ;\n\t__le16 io_pin_capacitance_typ;\n\t__le16 input_pin_capacitance_typ;\n\tu8 input_pin_capacitance_max;\n\tu8 driver_strength_support;\n\t__le16 t_int_r;\n\t__le16 t_adl;\n\tu8 reserved4[8];\n\t__le16 vendor_revision;\n\tu8 vendor[88];\n\t__le16 crc;\n} __attribute__((packed));\n\nstruct nand_onfi_vendor_macronix {\n\tu8 reserved;\n\tu8 reliability_func;\n};\n\nstruct nand_onfi_vendor_micron {\n\tu8 two_plane_read;\n\tu8 read_cache;\n\tu8 read_unique_id;\n\tu8 dq_imped;\n\tu8 dq_imped_num_settings;\n\tu8 dq_imped_feat_addr;\n\tu8 rb_pulldown_strength;\n\tu8 rb_pulldown_strength_feat_addr;\n\tu8 rb_pulldown_strength_num_settings;\n\tu8 otp_mode;\n\tu8 otp_page_start;\n\tu8 otp_data_prot_addr;\n\tu8 otp_num_pages;\n\tu8 otp_feat_addr;\n\tu8 read_retry_options;\n\tu8 reserved[72];\n\tu8 param_revision;\n};\n\nstruct nand_oobinfo {\n\t__u32 useecc;\n\t__u32 eccbytes;\n\t__u32 oobfree[16];\n\t__u32 eccpos[32];\n};\n\nstruct nand_op_addr_instr {\n\tunsigned int naddrs;\n\tconst u8 *addrs;\n};\n\nstruct nand_op_cmd_instr {\n\tu8 opcode;\n};\n\nstruct nand_op_data_instr {\n\tunsigned int len;\n\tunion {\n\t\tvoid *in;\n\t\tconst void *out;\n\t} buf;\n\tbool force_8bit;\n};\n\nstruct nand_op_waitrdy_instr {\n\tunsigned int timeout_ms;\n};\n\nstruct nand_op_instr {\n\tenum nand_op_instr_type type;\n\tunion {\n\t\tstruct nand_op_cmd_instr cmd;\n\t\tstruct nand_op_addr_instr addr;\n\t\tstruct nand_op_data_instr data;\n\t\tstruct nand_op_waitrdy_instr waitrdy;\n\t} ctx;\n\tunsigned int delay_ns;\n};\n\nstruct nand_op_parser_pattern;\n\nstruct nand_op_parser {\n\tconst struct nand_op_parser_pattern *patterns;\n\tunsigned int npatterns;\n};\n\nstruct nand_op_parser_addr_constraints {\n\tunsigned int maxcycles;\n};\n\nstruct nand_subop {\n\tunsigned int cs;\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n\tunsigned int first_instr_start_off;\n\tunsigned int last_instr_end_off;\n};\n\nstruct nand_op_parser_ctx {\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n\tstruct nand_subop subop;\n};\n\nstruct nand_op_parser_data_constraints {\n\tunsigned int maxlen;\n};\n\nstruct nand_op_parser_pattern_elem;\n\nstruct nand_op_parser_pattern {\n\tconst struct nand_op_parser_pattern_elem *elems;\n\tunsigned int nelems;\n\tint (*exec)(struct nand_chip *, const struct nand_subop *);\n};\n\nstruct nand_op_parser_pattern_elem {\n\tenum nand_op_instr_type type;\n\tbool optional;\n\tunion {\n\t\tstruct nand_op_parser_addr_constraints addr;\n\t\tstruct nand_op_parser_data_constraints data;\n\t} ctx;\n};\n\nstruct nand_operation {\n\tunsigned int cs;\n\tbool deassert_wp;\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n};\n\nstruct nand_ops {\n\tint (*erase)(struct nand_device *, const struct nand_pos *);\n\tint (*markbad)(struct nand_device *, const struct nand_pos *);\n\tbool (*isbad)(struct nand_device *, const struct nand_pos *);\n};\n\nstruct nand_secure_region {\n\tu64 offset;\n\tu64 size;\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u16 offset;\n\t__u16 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct nat_keepalive {\n\tstruct net *net;\n\tu16 family;\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\t__u32 smark;\n};\n\nstruct nat_keepalive_work_ctx {\n\ttime64_t next_run;\n\ttime64_t now;\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n\tlong: 32;\n};\n\nstruct nc_header {\n\t__le16 hdr_len;\n\t__le16 packet_len;\n\t__le16 packet_id;\n};\n\nstruct nc_trailer {\n\t__le16 packet_id;\n};\n\nstruct nd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\t__u8 opt[0];\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct nduseroptmsg {\n\tunsigned char nduseropt_family;\n\tunsigned char nduseropt_pad1;\n\tshort unsigned int nduseropt_opts_len;\n\tint nduseropt_ifindex;\n\t__u8 nduseropt_icmp_type;\n\t__u8 nduseropt_icmp_code;\n\tshort unsigned int nduseropt_pad2;\n\tunsigned int nduseropt_pad3;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct ref_tracker_dir {};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct udp_mib *udplite_statistics;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 32;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tu32 multipath_hash_fields;\n\tu8 multipath_hash_policy;\n\t__u8 __cacheline_group_begin__sysctl_ipv6_flowlabel[0];\n\tu8 flowlabel_consistency;\n\tu8 auto_flowlabels;\n\tu8 flowlabel_state_ranges;\n\t__u8 __cacheline_group_end__sysctl_ipv6_flowlabel[0];\n\tu8 icmpv6_echo_ignore_all;\n\tu8 icmpv6_echo_ignore_multicast;\n\tu8 icmpv6_echo_ignore_anycast;\n\tint icmpv6_time;\n\tlong unsigned int icmpv6_ratemask[8];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tu8 anycast_src_echo_reply;\n\tu8 bindv6only;\n\tu8 ip_nonlocal_bind;\n\tu8 fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tu32 ioam6_id;\n\tu64 ioam6_id_wide;\n\tu8 skip_notify_on_dev_down;\n\tu8 fib_notify_on_flag_change;\n\tu8 icmpv6_error_anycast_as_unicast;\n\tu8 icmpv6_errors_extension_mask;\n\tlong: 32;\n};\n\nstruct rt6_statistics;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct dst_ops ip6_dst_ops;\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tspinlock_t fib_table_hash_lock;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tatomic_t ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned char flowlabel_has_excl;\n\tbool fib6_has_custom_rules;\n\tunsigned int fib6_rules_require_fldissect;\n\tstruct rt6_info *ip6_prohibit_entry;\n\tstruct rt6_info *ip6_blk_hole_entry;\n\tstruct fib6_table *fib6_local_tbl;\n\tstruct fib_rules_ops *fib6_rules_ops;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct hlist_head *inet6_addr_lst;\n\tspinlock_t addrconf_hash_lock;\n\tstruct delayed_work addr_chk_work;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tstruct ioam6_pernet_data *ioam6_data;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct xfrm_policy_hash {\n\tstruct hlist_head *table;\n\tunsigned int hmask;\n\tu8 dbits4;\n\tu8 sbits4;\n\tu8 dbits6;\n\tu8 sbits6;\n};\n\nstruct xfrm_policy_hthresh {\n\tstruct work_struct work;\n\tseqlock_t lock;\n\tu8 lbits4;\n\tu8 rbits4;\n\tu8 lbits6;\n\tu8 rbits6;\n};\n\nstruct netns_xfrm {\n\tstruct list_head state_all;\n\tstruct hlist_head *state_bydst;\n\tstruct hlist_head *state_bysrc;\n\tstruct hlist_head *state_byspi;\n\tstruct hlist_head *state_byseq;\n\tstruct hlist_head *state_cache_input;\n\tunsigned int state_hmask;\n\tunsigned int state_num;\n\tstruct work_struct state_hash_work;\n\tstruct list_head policy_all;\n\tstruct hlist_head *policy_byidx;\n\tunsigned int policy_idx_hmask;\n\tunsigned int idx_generator;\n\tstruct xfrm_policy_hash policy_bydst[3];\n\tunsigned int policy_count[6];\n\tstruct work_struct policy_hash_work;\n\tstruct xfrm_policy_hthresh policy_hthresh;\n\tstruct list_head inexact_bins;\n\tstruct sock *nlsk;\n\tstruct sock *nlsk_stash;\n\tu32 sysctl_aevent_etime;\n\tu32 sysctl_aevent_rseqth;\n\tint sysctl_larval_drop;\n\tu32 sysctl_acq_expires;\n\tu8 policy_default[3];\n\tstruct ctl_table_header *sysctl_hdr;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct dst_ops xfrm4_dst_ops;\n\tstruct dst_ops xfrm6_dst_ops;\n\tspinlock_t xfrm_state_lock;\n\tseqcount_spinlock_t xfrm_state_hash_generation;\n\tseqcount_spinlock_t xfrm_policy_hash_generation;\n\tspinlock_t xfrm_policy_lock;\n\tstruct mutex xfrm_cfg_mutex;\n\tstruct delayed_work nat_keepalive_work;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netns_can {\n\tstruct proc_dir_entry *proc_dir;\n\tstruct proc_dir_entry *pde_stats;\n\tstruct proc_dir_entry *pde_reset_stats;\n\tstruct proc_dir_entry *pde_rcvlist_all;\n\tstruct proc_dir_entry *pde_rcvlist_fil;\n\tstruct proc_dir_entry *pde_rcvlist_inv;\n\tstruct proc_dir_entry *pde_rcvlist_sff;\n\tstruct proc_dir_entry *pde_rcvlist_eff;\n\tstruct proc_dir_entry *pde_rcvlist_err;\n\tstruct proc_dir_entry *bcmproc_dir;\n\tstruct can_dev_rcv_lists *rx_alldev_list;\n\tspinlock_t rcvlists_lock;\n\tstruct timer_list stattimer;\n\tstruct can_pkg_stats *pkg_stats;\n\tstruct can_rcv_lists_stats *rcv_lists_stats;\n\tstruct hlist_head cgw_list;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct netns_xfrm xfrm;\n\tu64 net_cookie;\n\tstruct netns_can can;\n\tstruct sock *crypto_nlsk;\n\tstruct sock *diag_nlsk;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct wireless_dev;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_sw_netstats;\n\nstruct pcpu_dstats;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct xdp_dev_bulk_queue;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct phy_link_topology;\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tlong: 32;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tlong: 32;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tstruct dsa_port *dsa_ptr;\n\tstruct wireless_dev *ieee80211_ptr;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tlong: 32;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct netdev_bpf;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct net_failover_info {\n\tstruct net_device *primary_dev;\n\tstruct net_device *standby_dev;\n\tstruct rtnl_link_stats64 primary_stats;\n\tstruct rtnl_link_stats64 standby_stats;\n\tstruct rtnl_link_stats64 failover_stats;\n\tspinlock_t stats_lock;\n\tlong: 32;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct inet6_protocol tcpv6_protocol;\n\tstruct inet6_protocol udpv6_protocol;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_local {\n\tstruct net_device *ndev;\n\tbool tx_ping_pong;\n\tbool rx_ping_pong;\n\tu32 next_tx_buf_to_use;\n\tu32 next_rx_buf_to_use;\n\tvoid *base_addr;\n\tspinlock_t reset_lock;\n\tstruct sk_buff *deferred_skb;\n\tstruct phy_device *phy_dev;\n\tstruct device_node *phy_node;\n\tstruct mii_bus *mii_bus;\n\tint last_link;\n};\n\nstruct net_packet_attrs {\n\tconst unsigned char *src;\n\tconst unsigned char *dst;\n\tu32 ip_src;\n\tu32 ip_dst;\n\tbool tcp;\n\tu16 sport;\n\tu16 dport;\n\tint timeout;\n\tint size;\n\tint max_size;\n\tu8 id;\n\tu16 queue_mapping;\n\tbool bad_csum;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct net_test {\n\tchar name[32];\n\tint (*fn)(struct net_device *);\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct net_test_priv {\n\tstruct net_packet_attrs *packet;\n\tstruct packet_type pt;\n\tstruct completion comp;\n\tint double_vlan;\n\tint vlan_id;\n\tint ok;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netcp_intf;\n\nstruct netcp_addr {\n\tstruct netcp_intf *netcp;\n\tunsigned char addr[6];\n\tenum netcp_addr_type type;\n\tunsigned int flags;\n\tstruct list_head node;\n};\n\nstruct netcp_device {\n\tstruct list_head device_list;\n\tstruct list_head interface_head;\n\tstruct list_head modpriv_head;\n\tstruct device *device;\n};\n\nstruct netcp_ethtool_stat {\n\tchar desc[32];\n\tint type;\n\tu32 size;\n\tint offset;\n};\n\nstruct netcp_packet;\n\ntypedef int netcp_hook_rtn(int, void *, struct netcp_packet *);\n\nstruct netcp_hook_list {\n\tstruct list_head list;\n\tnetcp_hook_rtn *hook_rtn;\n\tvoid *hook_data;\n\tint order;\n};\n\nstruct netcp_module;\n\nstruct netcp_inst_modpriv {\n\tstruct netcp_device *netcp_device;\n\tstruct netcp_module *netcp_module;\n\tstruct list_head inst_list;\n\tvoid *module_priv;\n};\n\nstruct netcp_stats {\n\tstruct u64_stats_sync syncp_rx;\n\tlong: 32;\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu32 rx_errors;\n\tu32 rx_dropped;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct u64_stats_sync syncp_tx;\n\tlong: 32;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu32 tx_errors;\n\tu32 tx_dropped;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netcp_intf {\n\tstruct device *dev;\n\tstruct device *ndev_dev;\n\tstruct net_device *ndev;\n\tbool big_endian;\n\tunsigned int tx_compl_qid;\n\tvoid *tx_pool;\n\tstruct list_head txhook_list_head;\n\tunsigned int tx_pause_threshold;\n\tvoid *tx_compl_q;\n\tunsigned int tx_resume_threshold;\n\tvoid *rx_queue;\n\tvoid *rx_pool;\n\tstruct list_head rxhook_list_head;\n\tunsigned int rx_queue_id;\n\tvoid *rx_fdq[4];\n\tstruct napi_struct rx_napi;\n\tstruct napi_struct tx_napi;\n\tu32 hw_cap;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct netcp_stats stats;\n\tvoid *rx_channel;\n\tconst char *dma_chan_name;\n\tu32 rx_pool_size;\n\tu32 rx_pool_region_id;\n\tu32 tx_pool_size;\n\tu32 tx_pool_region_id;\n\tstruct list_head module_head;\n\tstruct list_head interface_list;\n\tstruct list_head addr_list;\n\tbool netdev_registered;\n\tbool primary_module_attached;\n\tspinlock_t lock;\n\tstruct netcp_device *netcp_device;\n\tstruct device_node *node_interface;\n\tu32 msg_enable;\n\tu32 rx_queue_depths[4];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netcp_intf_modpriv {\n\tstruct netcp_intf *netcp_priv;\n\tstruct netcp_module *netcp_module;\n\tstruct list_head intf_list;\n\tvoid *module_priv;\n};\n\nstruct netcp_module {\n\tconst char *name;\n\tstruct module *owner;\n\tbool primary;\n\tint (*probe)(struct netcp_device *, struct device *, struct device_node *, void **);\n\tint (*remove)(struct netcp_device *, void *);\n\tint (*attach)(void *, struct net_device *, struct device_node *, void **);\n\tint (*release)(void *);\n\tint (*open)(void *, struct net_device *);\n\tint (*close)(void *, struct net_device *);\n\tint (*add_addr)(void *, struct netcp_addr *);\n\tint (*del_addr)(void *, struct netcp_addr *);\n\tint (*add_vid)(void *, int);\n\tint (*del_vid)(void *, int);\n\tint (*ioctl)(void *, struct ifreq *, int);\n\tint (*set_rx_mode)(void *, bool);\n\tint (*hwtstamp_get)(void *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(void *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tstruct list_head module_list;\n\tstruct list_head interface_list;\n};\n\nstruct netcp_packet {\n\tstruct sk_buff *skb;\n\t__le32 *epib;\n\tu32 *psdata;\n\tu32 eflags;\n\tunsigned int psdata_len;\n\tstruct netcp_intf *netcp;\n\tstruct netcp_tx_pipe *tx_pipe;\n\tbool rxtstamp_complete;\n\tvoid *ts_context;\n\tvoid (*txtstamp)(void *, struct sk_buff *);\n};\n\nstruct netcp_tx_cb {\n\tvoid *ts_context;\n\tvoid (*txtstamp)(void *, struct sk_buff *);\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_lag_lower_state_info {\n\tu8 link_up: 1;\n\tu8 tx_enabled: 1;\n};\n\nstruct netdev_lag_upper_info {\n\tenum netdev_lag_tx_type tx_type;\n\tenum netdev_lag_hash hash_type;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n\tlong: 32;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n};\n\nstruct netevent_redirect {\n\tstruct dst_entry *old;\n\tstruct dst_entry *new;\n\tstruct neighbour *neigh;\n\tconst void *daddr;\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netsfhdr {\n\t__be32 version;\n\t__be64 magic;\n\tu8 id;\n} __attribute__((packed));\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nfs2_fh {\n\tchar data[32];\n};\n\nstruct nfs3_accessargs {\n\tstruct nfs_fh *fh;\n\t__u32 access;\n};\n\nstruct nfs_fattr;\n\nstruct nfs3_accessres {\n\tstruct nfs_fattr *fattr;\n\t__u32 access;\n};\n\nstruct nfs3_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n\tenum nfs3_createmode createmode;\n\t__be32 verifier[2];\n};\n\nstruct rpc_procinfo;\n\nstruct rpc_message {\n\tconst struct rpc_procinfo *rpc_proc;\n\tvoid *rpc_argp;\n\tvoid *rpc_resp;\n\tconst struct cred *rpc_cred;\n};\n\nstruct nfs3_mkdirargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_mknodargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tenum nfs3_ftype type;\n\tstruct iattr *sattr;\n\tdev_t rdev;\n};\n\nstruct nfs3_diropres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs4_string;\n\nstruct nfs4_threshold;\n\nstruct nfs4_label;\n\nstruct nfs_fattr {\n\t__u64 valid;\n\tumode_t mode;\n\t__u32 nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tlong: 32;\n\t__u64 size;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 blocksize;\n\t\t\t__u32 blocks;\n\t\t} nfs2;\n\t\tstruct {\n\t\t\t__u64 used;\n\t\t} nfs3;\n\t} du;\n\tstruct nfs_fsid fsid;\n\t__u64 fileid;\n\t__u64 mounted_on_fileid;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\t__u64 change_attr;\n\t__u64 pre_change_attr;\n\t__u64 pre_size;\n\tstruct timespec64 pre_mtime;\n\tstruct timespec64 pre_ctime;\n\tlong unsigned int time_start;\n\tlong unsigned int gencount;\n\tstruct nfs4_string *owner_name;\n\tstruct nfs4_string *group_name;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs3_createdata {\n\tstruct rpc_message msg;\n\tunion {\n\t\tstruct nfs3_createargs create;\n\t\tstruct nfs3_mkdirargs mkdir;\n\t\tstruct nfs3_symlinkargs symlink;\n\t\tstruct nfs3_mknodargs mknod;\n\t} arg;\n\tstruct nfs3_diropres res;\n\tstruct nfs_fh fh;\n\tlong: 32;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_fattr dir_attr;\n};\n\nstruct nfs3_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs3_fh {\n\tshort unsigned int size;\n\tunsigned char data[64];\n};\n\nstruct nfs3_getaclargs {\n\tstruct nfs_fh *fh;\n\tint mask;\n\tstruct page **pages;\n};\n\nstruct nfs3_getaclres {\n\tstruct nfs_fattr *fattr;\n\tint mask;\n\tunsigned int acl_access_count;\n\tunsigned int acl_default_count;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n};\n\nstruct nfs3_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs3_linkres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_readdirargs {\n\tstruct nfs_fh *fh;\n\tlong: 32;\n\t__u64 cookie;\n\t__be32 verf[2];\n\tbool plus;\n\tunsigned int count;\n\tstruct page **pages;\n\tlong: 32;\n};\n\nstruct nfs3_readdirres {\n\tstruct nfs_fattr *dir_attr;\n\t__be32 *verf;\n\tbool plus;\n};\n\nstruct nfs3_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs3_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n\tunsigned int guard;\n\tlong: 32;\n\tstruct timespec64 guardtime;\n};\n\nstruct nfs3_setaclargs {\n\tstruct inode *inode;\n\tint mask;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n\tsize_t len;\n\tunsigned int npages;\n\tstruct page **pages;\n};\n\nstruct nfs41_bind_conn_to_session_args {\n\tstruct nfs_client *client;\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n\tint retries;\n};\n\nstruct nfs41_bind_conn_to_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n};\n\nstruct nfs4_channel_attrs {\n\tu32 max_rqst_sz;\n\tu32 max_resp_sz;\n\tu32 max_resp_sz_cached;\n\tu32 max_ops;\n\tu32 max_reqs;\n};\n\nstruct nfs41_create_session_args {\n\tstruct nfs_client *client;\n\tlong: 32;\n\tu64 clientid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tuint32_t cb_program;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tlong: 32;\n};\n\nstruct nfs41_create_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs4_op_map {\n\tunion {\n\t\tlong unsigned int longs[3];\n\t\tu32 words[3];\n\t} u;\n};\n\nstruct nfs41_state_protection {\n\tu32 how;\n\tstruct nfs4_op_map enforce;\n\tstruct nfs4_op_map allow;\n};\n\nstruct nfs41_exchange_id_args {\n\tstruct nfs_client *client;\n\tnfs4_verifier verifier;\n\tu32 flags;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_server_owner;\n\nstruct nfs41_server_scope;\n\nstruct nfs41_impl_id;\n\nstruct nfs41_exchange_id_res {\n\tu64 clientid;\n\tu32 seqid;\n\tu32 flags;\n\tstruct nfs41_server_owner *server_owner;\n\tstruct nfs41_server_scope *server_scope;\n\tstruct nfs41_impl_id *impl_id;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_exchange_id_data {\n\tstruct nfs41_exchange_id_res res;\n\tstruct nfs41_exchange_id_args args;\n\tlong: 32;\n};\n\nstruct nfs4_sequence_args {\n\tstruct nfs4_slot *sa_slot;\n\tu8 sa_cache_this: 1;\n\tu8 sa_privileged: 1;\n};\n\nstruct nfs41_free_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_sequence_slot_ops;\n\nstruct nfs4_sequence_res {\n\tconst struct nfs4_sequence_slot_ops *sr_slot_ops;\n\tstruct nfs4_slot *sr_slot;\n\tlong unsigned int sr_timestamp;\n\tint sr_status;\n\tu32 sr_status_flags;\n\tu32 sr_highest_slotid;\n\tu32 sr_target_highest_slotid;\n};\n\nstruct nfs41_free_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfstime4 {\n\tint64_t seconds;\n\tuint32_t nseconds;\n\tlong: 32;\n};\n\nstruct nfs41_impl_id {\n\tchar domain[1025];\n\tchar name[1025];\n\tlong: 32;\n\tstruct nfstime4 date;\n};\n\nstruct nfs41_reclaim_complete_args {\n\tstruct nfs4_sequence_args seq_args;\n\tunsigned char one_fs: 1;\n};\n\nstruct nfs41_reclaim_complete_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs41_secinfo_no_name_args {\n\tstruct nfs4_sequence_args seq_args;\n\tint style;\n};\n\nstruct nfs41_server_owner {\n\tuint64_t minor_id;\n\tuint32_t major_id_sz;\n\tchar major_id[1024];\n\tlong: 32;\n};\n\nstruct nfs41_server_scope {\n\tuint32_t server_scope_sz;\n\tchar server_scope[1024];\n};\n\nstruct nfs41_test_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs41_test_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfs42_clone_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid src_stateid;\n\tnfs4_stateid dst_stateid;\n\t__u64 src_offset;\n\t__u64 dst_offset;\n\t__u64 count;\n\tconst u32 *dst_bitmask;\n\tlong: 32;\n};\n\nstruct nfs_server;\n\nstruct nfs42_clone_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int rpc_status;\n\tstruct nfs_fattr *dst_fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nl4_server;\n\nstruct nfs42_copy_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tnfs4_stateid src_stateid;\n\tu64 src_pos;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid dst_stateid;\n\tu64 dst_pos;\n\tu64 count;\n\tbool sync;\n\tstruct nl4_server *cp_src;\n};\n\nstruct nfs42_netaddr {\n\tchar netid[5];\n\tchar addr[58];\n\tu32 netid_len;\n\tu32 addr_len;\n};\n\nstruct nl4_server {\n\tenum netloc_type4 nl4_type;\n\tunion {\n\t\tstruct {\n\t\t\tint nl4_str_sz;\n\t\t\tchar nl4_str[1025];\n\t\t};\n\t\tstruct nfs42_netaddr nl4_addr;\n\t} u;\n};\n\nstruct nfs42_copy_notify_args {\n\tstruct nfs4_sequence_args cna_seq_args;\n\tstruct nfs_fh *cna_src_fh;\n\tnfs4_stateid cna_src_stateid;\n\tstruct nl4_server cna_dst;\n};\n\nstruct nfs42_copy_notify_res {\n\tstruct nfs4_sequence_res cnr_seq_res;\n\tlong: 32;\n\tstruct nfstime4 cnr_lease_time;\n\tnfs4_stateid cnr_stateid;\n\tstruct nl4_server cnr_src;\n};\n\nstruct nfs42_write_res {\n\tnfs4_stateid stateid;\n\tlong: 32;\n\tu64 count;\n\tstruct nfs_writeverf verifier;\n\tlong: 32;\n};\n\nstruct nfs_commitres {\n\tstruct nfs4_sequence_res seq_res;\n\t__u32 op_status;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_writeverf *verf;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs42_copy_res {\n\tstruct nfs4_sequence_res seq_res;\n\tlong: 32;\n\tstruct nfs42_write_res write_res;\n\tbool consecutive;\n\tbool synchronous;\n\tstruct nfs_commitres commit_res;\n};\n\nstruct nfs42_device_error {\n\tstruct nfs4_deviceid dev_id;\n\tint status;\n\tenum nfs_opnum4 opnum;\n};\n\nstruct nfs42_falloc_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *falloc_fh;\n\tnfs4_stateid falloc_stateid;\n\tu64 falloc_offset;\n\tu64 falloc_length;\n\tconst u32 *falloc_bitmask;\n\tlong: 32;\n};\n\nstruct nfs42_falloc_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tstruct nfs_fattr *falloc_fattr;\n\tconst struct nfs_server *falloc_server;\n};\n\nstruct nfs42_getxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_getxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tsize_t xattr_len;\n};\n\nstruct nfs42_layout_error {\n\t__u64 offset;\n\t__u64 length;\n\tnfs4_stateid stateid;\n\tstruct nfs42_device_error errors[1];\n\tlong: 32;\n};\n\nstruct nfs42_layouterror_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct inode *inode;\n\tunsigned int num_errors;\n\tstruct nfs42_layout_error errors[5];\n};\n\nstruct nfs42_layouterror_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int num_errors;\n\tint rpc_status;\n};\n\nstruct pnfs_layout_segment;\n\nstruct nfs42_layouterror_data {\n\tstruct nfs42_layouterror_args args;\n\tstruct nfs42_layouterror_res res;\n\tstruct inode *inode;\n\tstruct pnfs_layout_segment *lseg;\n\tlong: 32;\n};\n\nstruct nfs42_layoutstat_devinfo;\n\nstruct nfs42_layoutstat_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tint num_dev;\n\tstruct nfs42_layoutstat_devinfo *devinfo;\n};\n\nstruct nfs42_layoutstat_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint num_dev;\n\tint rpc_status;\n};\n\nstruct nfs42_layoutstat_data {\n\tstruct inode *inode;\n\tstruct nfs42_layoutstat_args args;\n\tstruct nfs42_layoutstat_res res;\n};\n\nstruct nfs4_xdr_opaque_ops;\n\nstruct nfs4_xdr_opaque_data {\n\tconst struct nfs4_xdr_opaque_ops *ops;\n\tvoid *data;\n};\n\nstruct nfs42_layoutstat_devinfo {\n\tstruct nfs4_deviceid dev_id;\n\t__u64 offset;\n\t__u64 length;\n\t__u64 read_count;\n\t__u64 read_bytes;\n\t__u64 write_count;\n\t__u64 write_bytes;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data ld_private;\n\tlong: 32;\n};\n\nstruct nfs42_listxattrsargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tu32 count;\n\tu64 cookie;\n\tstruct page **xattr_pages;\n\tlong: 32;\n};\n\nstruct nfs42_listxattrsres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct folio *scratch;\n\tvoid *xattr_buf;\n\tsize_t xattr_len;\n\tu64 cookie;\n\tbool eof;\n\tsize_t copied;\n};\n\nstruct nfs42_offload_status_args {\n\tstruct nfs4_sequence_args osa_seq_args;\n\tstruct nfs_fh *osa_src_fh;\n\tnfs4_stateid osa_stateid;\n};\n\nstruct nfs42_offload_status_res {\n\tstruct nfs4_sequence_res osr_seq_res;\n\tlong: 32;\n\tu64 osr_count;\n\tint complete_count;\n\tu32 osr_complete;\n};\n\nstruct nfs42_offload_data {\n\tstruct nfs_server *seq_server;\n\tstruct nfs42_offload_status_args args;\n\tlong: 32;\n\tstruct nfs42_offload_status_res res;\n};\n\nstruct nfs42_removexattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n};\n\nstruct nfs4_change_info {\n\tu32 atomic;\n\tlong: 32;\n\tu64 before;\n\tu64 after;\n};\n\nstruct nfs42_removexattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs42_seek_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *sa_fh;\n\tnfs4_stateid sa_stateid;\n\tu64 sa_offset;\n\tu32 sa_what;\n\tlong: 32;\n};\n\nstruct nfs42_seek_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tu32 sr_eof;\n\tlong: 32;\n\tu64 sr_offset;\n};\n\nstruct nfs42_setxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tconst char *xattr_name;\n\tu32 xattr_flags;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_setxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs4_accessargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tu32 access;\n};\n\nstruct nfs4_accessres {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tu32 supported;\n\tu32 access;\n};\n\nstruct nfs4_add_xprt_data {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct nfs4_cached_acl {\n\tenum nfs4_acl_type type;\n\tint cached;\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct nfs4_call_sync_data {\n\tconst struct nfs_server *seq_server;\n\tstruct nfs4_sequence_args *seq_args;\n\tstruct nfs4_sequence_res *seq_res;\n};\n\nstruct nfs_seqid;\n\nstruct nfs4_layoutreturn_args;\n\nstruct nfs_closeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n\tfmode_t fmode;\n\tu32 share_access;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs4_layoutreturn_res;\n\nstruct nfs_closeres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct pnfs_layout_hdr;\n\nstruct nfs4_layoutreturn_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_layout_hdr *layout;\n\tstruct inode *inode;\n\tstruct pnfs_layout_range range;\n\tnfs4_stateid stateid;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data *ld_private;\n\tlong: 32;\n};\n\nstruct nfs4_layoutreturn_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 lrs_present;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_state;\n\nstruct nfs4_closedata {\n\tstruct inode *inode;\n\tstruct nfs4_state *state;\n\tstruct nfs_closeargs arg;\n\tstruct nfs_closeres res;\n\tlong: 32;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t\tlong: 32;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_copy_state {\n\tstruct list_head copies;\n\tstruct list_head src_copies;\n\tnfs4_stateid stateid;\n\tstruct completion completion;\n\tlong: 32;\n\tuint64_t count;\n\tstruct nfs_writeverf verf;\n\tint error;\n\tint flags;\n\tstruct nfs4_state *parent_src_state;\n\tstruct nfs4_state *parent_dst_state;\n\tlong: 32;\n};\n\nstruct nfs4_create_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tu32 ftype;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page **pages;\n\t\t\tunsigned int len;\n\t\t} symlink;\n\t\tstruct {\n\t\t\tu32 specdata1;\n\t\t\tu32 specdata2;\n\t\t} device;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst struct iattr *attrs;\n\tconst struct nfs_fh *dir_fh;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n};\n\nstruct nfs4_create_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info dir_cinfo;\n};\n\nstruct nfs4_createdata {\n\tstruct rpc_message msg;\n\tstruct nfs4_create_arg arg;\n\tstruct nfs4_create_res res;\n\tstruct nfs_fh fh;\n\tlong: 32;\n\tstruct nfs_fattr fattr;\n};\n\nstruct nfs4_delegattr {\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tbool atime_set;\n\tbool mtime_set;\n\tlong: 32;\n};\n\nstruct nfs4_delegreturnargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fhandle;\n\tconst nfs4_stateid *stateid;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n\tstruct nfs4_delegattr *sattr_args;\n};\n\nstruct nfs4_delegreturnres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n\tbool sattr_res;\n\tint sattr_ret;\n};\n\nstruct nfs4_delegreturndata {\n\tstruct nfs4_delegreturnargs args;\n\tstruct nfs4_delegreturnres res;\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tlong: 32;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t\tlong: 32;\n\t} lr;\n\tstruct nfs4_delegattr sattr;\n\tstruct nfs_fattr fattr;\n\tint rpc_status;\n\tstruct inode *inode;\n};\n\nstruct pnfs_layoutdriver_type;\n\nstruct nfs4_deviceid_node {\n\tstruct hlist_node node;\n\tstruct hlist_node tmpnode;\n\tconst struct pnfs_layoutdriver_type *ld;\n\tconst struct nfs_client *nfs_client;\n\tlong unsigned int flags;\n\tlong unsigned int timestamp_unavailable;\n\tstruct nfs4_deviceid deviceid;\n\tstruct callback_head rcu;\n\tatomic_t ref;\n};\n\nstruct nfs4_ds_server {\n\tstruct list_head list;\n\tstruct rpc_clnt *rpc_clnt;\n};\n\nstruct nfs4_exception {\n\tstruct nfs4_state *state;\n\tstruct inode *inode;\n\tnfs4_stateid *stateid;\n\tlong int timeout;\n\tshort unsigned int retrans;\n\tunsigned char task_is_privileged: 1;\n\tunsigned char delay: 1;\n\tunsigned char recovering: 1;\n\tunsigned char retry: 1;\n\tbool interruptible;\n};\n\nstruct nfs4_ff_busy_timer {\n\tktime_t start_time;\n\tatomic_t n_ops;\n\tlong: 32;\n};\n\nstruct nfs4_ff_ds_version {\n\tu32 version;\n\tu32 minor_version;\n\tu32 rsize;\n\tu32 wsize;\n\tbool tightly_coupled;\n};\n\nstruct nfs4_ff_io_stat {\n\t__u64 ops_requested;\n\t__u64 bytes_requested;\n\t__u64 ops_completed;\n\t__u64 bytes_completed;\n\t__u64 bytes_not_delivered;\n\tktime_t total_busy_time;\n\tktime_t aggregate_completion_time;\n};\n\nstruct nfs4_pnfs_ds;\n\nstruct nfs4_ff_layout_ds {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 ds_versions_cnt;\n\tstruct nfs4_ff_ds_version *ds_versions;\n\tstruct nfs4_pnfs_ds *ds;\n};\n\nstruct nfs4_ff_layout_ds_err {\n\tstruct list_head list;\n\tu64 offset;\n\tu64 length;\n\tint status;\n\tenum nfs_opnum4 opnum;\n\tnfs4_stateid stateid;\n\tstruct nfs4_deviceid deviceid;\n\tlong: 32;\n};\n\nstruct nfsd_file;\n\nstruct nfs_file_localio {\n\tstruct nfsd_file *ro_file;\n\tstruct nfsd_file *rw_file;\n\tstruct list_head list;\n\tvoid *nfs_uuid;\n};\n\nstruct nfs4_ff_layoutstat {\n\tstruct nfs4_ff_io_stat io_stat;\n\tstruct nfs4_ff_busy_timer busy_timer;\n};\n\nstruct nfs4_ff_layout_mirror;\n\nstruct nfs4_ff_layout_ds_stripe {\n\tstruct nfs4_ff_layout_mirror *mirror;\n\tstruct nfs4_deviceid devid;\n\tu32 efficiency;\n\tstruct nfs4_ff_layout_ds *mirror_ds;\n\tu32 fh_versions_cnt;\n\tstruct nfs_fh *fh_versions;\n\tnfs4_stateid stateid;\n\tconst struct cred *ro_cred;\n\tconst struct cred *rw_cred;\n\tstruct nfs_file_localio nfl;\n\tlong: 32;\n\tstruct nfs4_ff_layoutstat read_stat;\n\tstruct nfs4_ff_layoutstat write_stat;\n\tktime_t start_time;\n};\n\nstruct nfs4_ff_layout_mirror {\n\tstruct pnfs_layout_hdr *layout;\n\tstruct list_head mirrors;\n\tu32 dss_count;\n\tstruct nfs4_ff_layout_ds_stripe *dss;\n\trefcount_t ref;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu32 report_interval;\n};\n\nstruct pnfs_layout_segment {\n\tstruct list_head pls_list;\n\tstruct list_head pls_lc_list;\n\tstruct list_head pls_commits;\n\tstruct pnfs_layout_range pls_range;\n\trefcount_t pls_refcount;\n\tu32 pls_seq;\n\tlong unsigned int pls_flags;\n\tstruct pnfs_layout_hdr *pls_layout;\n};\n\nstruct nfs4_ff_layout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu64 stripe_unit;\n\tu32 flags;\n\tu32 mirror_array_cnt;\n\tstruct nfs4_ff_layout_mirror *mirror_array[0];\n};\n\nstruct nfs4_file_layout_dsaddr {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 stripe_count;\n\tu8 *stripe_indices;\n\tu32 ds_num;\n\tstruct nfs4_pnfs_ds *ds_list[0];\n};\n\nstruct pnfs_layout_hdr {\n\trefcount_t plh_refcount;\n\tatomic_t plh_outstanding;\n\tstruct list_head plh_layouts;\n\tstruct list_head plh_bulk_destroy;\n\tstruct list_head plh_segs;\n\tstruct list_head plh_return_segs;\n\tlong unsigned int plh_block_lgets;\n\tlong unsigned int plh_retry_timestamp;\n\tlong unsigned int plh_flags;\n\tnfs4_stateid plh_stateid;\n\tu32 plh_barrier;\n\tu32 plh_return_seq;\n\tenum pnfs_iomode plh_return_iomode;\n\tlong: 32;\n\tloff_t plh_lwb;\n\tconst struct cred *plh_lc_cred;\n\tstruct inode *plh_inode;\n\tstruct callback_head plh_rcu;\n};\n\nstruct pnfs_commit_ops;\n\nstruct pnfs_ds_commit_info {\n\tstruct list_head commits;\n\tunsigned int nwritten;\n\tunsigned int ncommitting;\n\tconst struct pnfs_commit_ops *ops;\n};\n\nstruct nfs4_filelayout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tlong: 32;\n};\n\nstruct nfs4_filelayout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu32 stripe_type;\n\tu32 commit_through_mds;\n\tu32 stripe_unit;\n\tu32 first_stripe_index;\n\tu64 pattern_offset;\n\tstruct nfs4_deviceid deviceid;\n\tstruct nfs4_file_layout_dsaddr *dsaddr;\n\tunsigned int num_fh;\n\tstruct nfs_fh **fh_array;\n\tlong: 32;\n};\n\nstruct nfs4_flexfile_layout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tstruct list_head mirrors;\n\tstruct list_head error_list;\n\tlong: 32;\n\tktime_t last_report_time;\n};\n\nstruct nfs4_flexfile_layoutreturn_args {\n\tstruct list_head errors;\n\tstruct nfs42_layoutstat_devinfo devinfo[4];\n\tunsigned int num_errors;\n\tunsigned int num_dev;\n\tstruct page *pages[1];\n\tlong: 32;\n};\n\nstruct nfs4_string {\n\tunsigned int len;\n\tchar *data;\n};\n\nstruct nfs4_pathname {\n\tunsigned int ncomponents;\n\tstruct nfs4_string components[512];\n};\n\nstruct nfs4_fs_location {\n\tunsigned int nservers;\n\tstruct nfs4_string servers[10];\n\tstruct nfs4_pathname rootpath;\n};\n\nstruct nfs4_fs_locations {\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tstruct nfs4_pathname fs_path;\n\tint nlocations;\n\tstruct nfs4_fs_location locations[10];\n};\n\nstruct nfs4_fs_locations_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct nfs_fh *fh;\n\tconst struct qstr *name;\n\tstruct page *page;\n\tconst u32 *bitmask;\n\tlong: 32;\n\tclientid4 clientid;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n\tlong: 32;\n};\n\nstruct nfs4_fs_locations_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_fs_locations *fs_locations;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tlong: 32;\n\tclientid4 clientid;\n\tunsigned char renew: 1;\n\tlong: 32;\n};\n\nstruct nfs4_fsid_present_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fh *fh;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsinfo;\n\nstruct nfs4_fsinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsinfo *fsinfo;\n};\n\nstruct nfs4_gdd_res {\n\tu32 status;\n\tnfs4_stateid deleg;\n};\n\nstruct nfs4_get_lease_time_args {\n\tstruct nfs4_sequence_args la_seq_args;\n};\n\nstruct nfs4_get_lease_time_res;\n\nstruct nfs4_get_lease_time_data {\n\tstruct nfs4_get_lease_time_args *args;\n\tstruct nfs4_get_lease_time_res *res;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_get_lease_time_res {\n\tstruct nfs4_sequence_res lr_seq_res;\n\tstruct nfs_fsinfo *lr_fsinfo;\n};\n\nstruct nfs4_getattr_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tbool get_dir_deleg;\n};\n\nstruct nfs4_getattr_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_gdd_res *gdd_res;\n};\n\nstruct pnfs_device;\n\nstruct nfs4_getdeviceinfo_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_device *pdev;\n\t__u32 notify_types;\n};\n\nstruct nfs4_getdeviceinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct pnfs_device *pdev;\n\t__u32 notification;\n};\n\nstruct nfs4_label {\n\tuint32_t lfs;\n\tuint32_t pi;\n\tu32 lsmid;\n\tu32 len;\n\tchar *label;\n};\n\nstruct nfs4_layoutcommit_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n\tlong: 32;\n\t__u64 lastbytewritten;\n\tstruct inode *inode;\n\tconst u32 *bitmask;\n\tsize_t layoutupdate_len;\n\tstruct page *layoutupdate_page;\n\tstruct page **layoutupdate_pages;\n\t__be32 *start_p;\n};\n\nstruct rpc_wait {\n\tstruct list_head list;\n\tstruct list_head links;\n\tstruct list_head timer_list;\n};\n\nstruct rpc_call_ops;\n\nstruct rpc_xprt;\n\nstruct rpc_rqst;\n\nstruct rpc_task {\n\tatomic_t tk_count;\n\tint tk_status;\n\tstruct list_head tk_task;\n\tvoid (*tk_callback)(struct rpc_task *);\n\tvoid (*tk_action)(struct rpc_task *);\n\tlong unsigned int tk_timeout;\n\tlong unsigned int tk_runstate;\n\tstruct rpc_wait_queue *tk_waitqueue;\n\tunion {\n\t\tstruct work_struct tk_work;\n\t\tstruct rpc_wait tk_wait;\n\t} u;\n\tstruct rpc_message tk_msg;\n\tvoid *tk_calldata;\n\tconst struct rpc_call_ops *tk_ops;\n\tstruct rpc_clnt *tk_client;\n\tstruct rpc_xprt *tk_xprt;\n\tstruct rpc_cred *tk_op_cred;\n\tstruct rpc_rqst *tk_rqstp;\n\tstruct workqueue_struct *tk_workqueue;\n\tktime_t tk_start;\n\tpid_t tk_owner;\n\tint tk_rpc_status;\n\tshort unsigned int tk_flags;\n\tshort unsigned int tk_timeouts;\n\tshort unsigned int tk_pid;\n\tunsigned char tk_priority: 2;\n\tunsigned char tk_garb_retry: 2;\n\tunsigned char tk_cred_retry: 2;\n};\n\nstruct nfs4_layoutcommit_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tint status;\n};\n\nstruct nfs4_layoutcommit_data {\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct list_head lseg_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tstruct nfs4_layoutcommit_args args;\n\tstruct nfs4_layoutcommit_res res;\n};\n\nstruct nfs4_layoutdriver_data {\n\tstruct page **pages;\n\t__u32 pglen;\n\t__u32 len;\n};\n\nstruct nfs_open_context;\n\nstruct nfs4_layoutget_args {\n\tstruct nfs4_sequence_args seq_args;\n\t__u32 type;\n\tlong: 32;\n\tstruct pnfs_layout_range range;\n\t__u64 minlength;\n\t__u32 maxcount;\n\tstruct inode *inode;\n\tstruct nfs_open_context *ctx;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data layout;\n\tlong: 32;\n};\n\nstruct nfs4_layoutget_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint status;\n\t__u32 return_on_close;\n\tlong: 32;\n\tstruct pnfs_layout_range range;\n\t__u32 type;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data *layoutp;\n\tlong: 32;\n};\n\nstruct nfs4_layoutget {\n\tstruct nfs4_layoutget_args args;\n\tstruct nfs4_layoutget_res res;\n\tconst struct cred *cred;\n\tstruct pnfs_layout_hdr *lo;\n\tgfp_t gfp_flags;\n\tlong: 32;\n};\n\nstruct nfs4_layoutreturn {\n\tstruct nfs4_layoutreturn_args args;\n\tstruct nfs4_layoutreturn_res res;\n\tconst struct cred *cred;\n\tstruct nfs_client *clp;\n\tstruct inode *inode;\n\tint rpc_status;\n\tstruct nfs4_xdr_opaque_data ld_private;\n\tlong: 32;\n};\n\nstruct nfs4_link_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_link_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *dir_attr;\n\tlong: 32;\n};\n\nstruct nfs_seqid_counter {\n\tktime_t create_time;\n\tu64 owner_id;\n\tint flags;\n\tu32 counter;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct rpc_wait_queue wait;\n\tlong: 32;\n};\n\nstruct nfs4_lock_state {\n\tstruct list_head ls_locks;\n\tstruct nfs4_state *ls_state;\n\tlong unsigned int ls_flags;\n\tstruct nfs_seqid_counter ls_seqid;\n\tnfs4_stateid ls_stateid;\n\trefcount_t ls_count;\n\tfl_owner_t ls_owner;\n\tlong: 32;\n};\n\nstruct nfs4_lock_waiter {\n\tstruct inode *inode;\n\tlong: 32;\n\tstruct nfs_lowner owner;\n\twait_queue_entry_t wait;\n\tlong: 32;\n};\n\nstruct nfs_lock_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *lock_seqid;\n\tnfs4_stateid lock_stateid;\n\tstruct nfs_seqid *open_seqid;\n\tnfs4_stateid open_stateid;\n\tstruct nfs_lowner lock_owner;\n\tunsigned char block: 1;\n\tunsigned char reclaim: 1;\n\tunsigned char new_lock: 1;\n\tunsigned char new_lock_owner: 1;\n\tlong: 32;\n};\n\nstruct nfs_lock_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *lock_seqid;\n\tstruct nfs_seqid *open_seqid;\n};\n\nstruct nfs4_lockdata {\n\tstruct nfs_lock_args arg;\n\tstruct nfs_lock_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct file_lock fl;\n\tlong unsigned int timestamp;\n\tint rpc_status;\n\tint cancelled;\n\tstruct nfs_server *server;\n};\n\nstruct nfs4_lookup_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookup_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_lookup_root_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_mig_recovery_ops {\n\tint (*get_locations)(struct nfs_server *, struct nfs_fh *, struct nfs4_fs_locations *, struct page *, const struct cred *);\n\tint (*fsid_present)(struct inode *, const struct cred *);\n};\n\nstruct nfs4_state_recovery_ops;\n\nstruct nfs4_state_maintenance_ops;\n\nstruct nfs4_minor_version_ops {\n\tu32 minor_version;\n\tunsigned int init_caps;\n\tint (*init_client)(struct nfs_client *);\n\tvoid (*shutdown_client)(struct nfs_client *);\n\tbool (*match_stateid)(const nfs4_stateid *, const nfs4_stateid *);\n\tint (*find_root_sec)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *);\n\tvoid (*free_lock_state)(struct nfs_server *, struct nfs4_lock_state *);\n\tint (*test_and_free_expired)(struct nfs_server *, nfs4_stateid *, const struct cred *);\n\tstruct nfs_seqid * (*alloc_seqid)(struct nfs_seqid_counter *, gfp_t);\n\tvoid (*session_trunk)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tconst struct rpc_call_ops *call_sync_ops;\n\tconst struct nfs4_sequence_slot_ops *sequence_slot_ops;\n\tconst struct nfs4_state_recovery_ops *reboot_recovery_ops;\n\tconst struct nfs4_state_recovery_ops *nograce_recovery_ops;\n\tconst struct nfs4_state_maintenance_ops *state_renewal_ops;\n\tconst struct nfs4_mig_recovery_ops *mig_recovery_ops;\n};\n\nstruct nfs_string {\n\tunsigned int len;\n\tconst char *data;\n};\n\nstruct nfs4_mount_data {\n\tint version;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct nfs_string client_addr;\n\tstruct nfs_string mnt_path;\n\tstruct nfs_string hostname;\n\tunsigned int host_addrlen;\n\tstruct sockaddr *host_addr;\n\tint proto;\n\tint auth_flavourlen;\n\tint *auth_flavours;\n};\n\nstruct nfs4_open_caps {\n\tu32 oa_share_access[1];\n\tu32 oa_share_deny[1];\n\tu32 oa_share_access_want[1];\n\tu32 oa_open_claim[1];\n\tu32 oa_createmode[1];\n};\n\nstruct nfs4_open_createattrs {\n\tstruct nfs4_label *label;\n\tstruct iattr *sattr;\n\tconst __u32 verf[2];\n};\n\nstruct nfs4_open_delegation {\n\t__u32 open_delegation_type;\n\tunion {\n\t\tstruct {\n\t\t\tfmode_t type;\n\t\t\t__u32 do_recall;\n\t\t\tnfs4_stateid stateid;\n\t\t\tlong unsigned int pagemod_limit;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 why_no_delegation;\n\t\t\t__u32 will_notify;\n\t\t};\n\t};\n};\n\nstruct stateowner_id {\n\t__u64 create_time;\n\t__u64 uniquifier;\n};\n\nstruct nfs_openargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct nfs_seqid *seqid;\n\tint open_flags;\n\tfmode_t fmode;\n\tu32 share_access;\n\tu32 access;\n\t__u64 clientid;\n\tstruct stateowner_id id;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iattr *attrs;\n\t\t\tnfs4_verifier verifier;\n\t\t};\n\t\tnfs4_stateid delegation;\n\t\t__u32 delegation_type;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst u32 *open_bitmap;\n\tenum open_claim_type4 claim;\n\tenum createmode4 createmode;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n\tstruct nfs4_layoutget_args *lg_args;\n};\n\nstruct nfs_openres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fh fh;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n\t__u32 rflags;\n\tstruct nfs_fattr *f_attr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\t__u32 attrset[3];\n\tstruct nfs4_string *owner;\n\tstruct nfs4_string *group_owner;\n\tstruct nfs4_open_delegation delegation;\n\t__u32 access_request;\n\t__u32 access_supported;\n\t__u32 access_result;\n\tstruct nfs4_layoutget_res *lg_res;\n};\n\nstruct nfs_open_confirmargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tnfs4_stateid *stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_open_confirmres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs4_state_owner;\n\nstruct nfs4_opendata {\n\tstruct kref kref;\n\tlong: 32;\n\tstruct nfs_openargs o_arg;\n\tstruct nfs_openres o_res;\n\tstruct nfs_open_confirmargs c_arg;\n\tstruct nfs_open_confirmres c_res;\n\tstruct nfs4_string owner_name;\n\tstruct nfs4_string group_name;\n\tstruct nfs4_label *a_label;\n\tlong: 32;\n\tstruct nfs_fattr f_attr;\n\tstruct dentry *dir;\n\tstruct dentry *dentry;\n\tstruct nfs4_state_owner *owner;\n\tstruct nfs4_state *state;\n\tstruct iattr attrs;\n\tstruct nfs4_layoutget *lgp;\n\tlong unsigned int timestamp;\n\tbool rpc_done;\n\tbool file_created;\n\tbool is_recover;\n\tbool cancelled;\n\tint rpc_status;\n};\n\nstruct nfs4_pathconf_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_pathconf;\n\nstruct nfs4_pathconf_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_pathconf *pathconf;\n};\n\nstruct nfs4_pnfs_ds {\n\tstruct list_head ds_node;\n\tchar *ds_remotestr;\n\tstruct list_head ds_addrs;\n\tconst struct net *ds_net;\n\tstruct nfs_client *ds_clp;\n\trefcount_t ds_count;\n\tlong unsigned int ds_state;\n};\n\nstruct nfs4_pnfs_ds_addr {\n\tstruct __kernel_sockaddr_storage da_addr;\n\tsize_t da_addrlen;\n\tstruct list_head da_node;\n\tchar *da_remotestr;\n\tconst char *da_netid;\n\tint da_transport;\n};\n\nstruct nfs4_readdir_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tlong: 32;\n\tu64 cookie;\n\tnfs4_verifier verifier;\n\tu32 count;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tconst u32 *bitmask;\n\tbool plus;\n\tlong: 32;\n};\n\nstruct nfs4_readdir_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_verifier verifier;\n\tunsigned int pgbase;\n};\n\nstruct nfs4_readlink {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs4_readlink_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_reclaim_complete_data {\n\tstruct nfs_client *clp;\n\tstruct nfs41_reclaim_complete_args arg;\n\tstruct nfs41_reclaim_complete_res res;\n};\n\nstruct rpcsec_gss_info {\n\tstruct rpcsec_gss_oid oid;\n\tu32 qop;\n\tu32 service;\n};\n\nstruct nfs4_secinfo4 {\n\tu32 flavor;\n\tstruct rpcsec_gss_info flavor_info;\n};\n\nstruct nfs4_secinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n};\n\nstruct nfs4_secinfo_flavors {\n\tunsigned int num_flavors;\n\tstruct nfs4_secinfo4 flavors[0];\n};\n\nstruct nfs4_secinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_secinfo_flavors *flavors;\n};\n\nstruct nfs4_sequence_data {\n\tstruct nfs_client *clp;\n\tstruct nfs4_sequence_args args;\n\tstruct nfs4_sequence_res res;\n};\n\nstruct nfs4_sequence_slot_ops {\n\tint (*process)(struct rpc_task *, struct nfs4_sequence_res *);\n\tint (*done)(struct rpc_task *, struct nfs4_sequence_res *);\n\tvoid (*free_slot)(struct nfs4_sequence_res *);\n};\n\nstruct nfs4_server_caps_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fhandle;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_server_caps_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 attr_bitmask[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 has_links;\n\tu32 has_symlinks;\n\tu32 fh_expire_type;\n\tu32 case_insensitive;\n\tu32 case_preserving;\n\tstruct nfs4_open_caps open_caps;\n};\n\nstruct nfs4_session;\n\nstruct nfs4_slot_table {\n\tstruct nfs4_session *session;\n\tstruct nfs4_slot *slots;\n\tlong unsigned int used_slots[32];\n\tspinlock_t slot_tbl_lock;\n\tstruct rpc_wait_queue slot_tbl_waitq;\n\twait_queue_head_t slot_waitq;\n\tu32 max_slots;\n\tu32 max_slotid;\n\tu32 highest_used_slotid;\n\tu32 target_highest_slotid;\n\tu32 server_highest_slotid;\n\ts32 d_target_highest_slotid;\n\ts32 d2_target_highest_slotid;\n\tlong unsigned int generation;\n\tstruct completion complete;\n\tlong unsigned int slot_tbl_state;\n};\n\nstruct nfs4_session {\n\tstruct nfs4_sessionid sess_id;\n\tu32 flags;\n\tlong unsigned int session_state;\n\tu32 hash_alg;\n\tu32 ssv_len;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_slot_table fc_slot_table;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tstruct nfs4_slot_table bc_slot_table;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_setclientid {\n\tconst nfs4_verifier *sc_verifier;\n\tu32 sc_prog;\n\tunsigned int sc_netid_len;\n\tchar sc_netid[6];\n\tunsigned int sc_uaddr_len;\n\tchar sc_uaddr[58];\n\tstruct nfs_client *sc_clnt;\n\tstruct rpc_cred *sc_cred;\n};\n\nstruct nfs4_setclientid_res {\n\tu64 clientid;\n\tnfs4_verifier confirm;\n};\n\nstruct nfs4_slot {\n\tstruct nfs4_slot_table *table;\n\tstruct nfs4_slot *next;\n\tlong unsigned int generation;\n\tu32 slot_nr;\n\tu32 seq_nr;\n\tu32 seq_nr_last_acked;\n\tu32 seq_nr_highest_sent;\n\tunsigned int privileged: 1;\n\tunsigned int seq_done: 1;\n};\n\nstruct nfs4_ssc_client_ops {\n\tstruct file * (*sco_open)(struct vfsmount *, struct nfs_fh *, nfs4_stateid *);\n\tvoid (*sco_close)(struct file *);\n};\n\nstruct nfs4_state {\n\tstruct list_head open_states;\n\tstruct list_head inode_states;\n\tstruct list_head lock_states;\n\tstruct nfs4_state_owner *owner;\n\tstruct inode *inode;\n\tlong unsigned int flags;\n\tspinlock_t state_lock;\n\tseqlock_t seqlock;\n\tnfs4_stateid stateid;\n\tnfs4_stateid open_stateid;\n\tunsigned int n_rdonly;\n\tunsigned int n_wronly;\n\tunsigned int n_rdwr;\n\tfmode_t state;\n\trefcount_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs4_state_maintenance_ops {\n\tint (*sched_state_renewal)(struct nfs_client *, const struct cred *, unsigned int);\n\tconst struct cred * (*get_state_renewal_cred)(struct nfs_client *);\n\tint (*renew_lease)(struct nfs_client *, const struct cred *);\n};\n\nstruct nfs4_state_owner {\n\tstruct nfs_server *so_server;\n\tstruct list_head so_lru;\n\tlong unsigned int so_expires;\n\tstruct rb_node so_server_node;\n\tconst struct cred *so_cred;\n\tspinlock_t so_lock;\n\tatomic_t so_count;\n\tlong unsigned int so_flags;\n\tstruct list_head so_states;\n\tlong: 32;\n\tstruct nfs_seqid_counter so_seqid;\n\tstruct mutex so_delegreturn_mutex;\n\tlong: 32;\n};\n\nstruct nfs4_state_recovery_ops {\n\tint owner_flag_bit;\n\tint state_flag_bit;\n\tint (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);\n\tint (*recover_lock)(struct nfs4_state *, struct file_lock *);\n\tint (*establish_clid)(struct nfs_client *, const struct cred *);\n\tint (*reclaim_complete)(struct nfs_client *, const struct cred *);\n\tint (*detect_trunking)(struct nfs_client *, struct nfs_client **, const struct cred *);\n};\n\nstruct nfs4_statfs_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsstat;\n\nstruct nfs4_statfs_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsstat *fsstat;\n};\n\nstruct nfs4_threshold {\n\t__u32 bm;\n\t__u32 l_type;\n\t__u64 rd_sz;\n\t__u64 wr_sz;\n\t__u64 rd_io_sz;\n\t__u64 wr_io_sz;\n};\n\nstruct nfs_locku_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *seqid;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs_locku_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_lock_context;\n\nstruct nfs4_unlockdata {\n\tstruct nfs_locku_args arg;\n\tstruct nfs_locku_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct file_lock fl;\n\tstruct nfs_server *server;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tlong: 32;\n};\n\nstruct nfs4_xattr_cache;\n\nstruct nfs4_xattr_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n\tstruct nfs4_xattr_cache *cache;\n\tbool draining;\n};\n\nstruct nfs4_xattr_entry;\n\nstruct nfs4_xattr_cache {\n\tstruct kref ref;\n\tstruct nfs4_xattr_bucket buckets[64];\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tatomic_long_t nent;\n\tspinlock_t listxattr_lock;\n\tstruct inode *inode;\n\tstruct nfs4_xattr_entry *listxattr;\n};\n\nstruct nfs4_xattr_entry {\n\tstruct kref ref;\n\tstruct hlist_node hnode;\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tchar *xattr_name;\n\tvoid *xattr_value;\n\tsize_t xattr_size;\n\tstruct nfs4_xattr_bucket *bucket;\n\tuint32_t flags;\n};\n\nstruct nfs4_xdr_opaque_ops {\n\tvoid (*encode)(struct xdr_stream *, const void *, const struct nfs4_xdr_opaque_data *);\n\tvoid (*free)(struct nfs4_xdr_opaque_data *);\n};\n\nstruct nfs_access_entry {\n\tstruct rb_node rb_node;\n\tstruct list_head lru;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tstruct group_info *group_info;\n\tu64 timestamp;\n\t__u32 mask;\n\tstruct callback_head callback_head;\n\tlong: 32;\n};\n\nstruct nfs_auth_info {\n\tunsigned int flavor_len;\n\trpc_authflavor_t flavors[12];\n};\n\nstruct nfs_cache_array_entry {\n\tu64 cookie;\n\tu64 ino;\n\tconst char *name;\n\tunsigned int name_len;\n\tunsigned char d_type;\n\tlong: 32;\n};\n\nstruct nfs_cache_array {\n\tu64 change_attr;\n\tu64 last_cookie;\n\tunsigned int size;\n\tunsigned char folio_full: 1;\n\tunsigned char folio_is_eof: 1;\n\tunsigned char cookies_are_ordered: 1;\n\tstruct nfs_cache_array_entry array[0];\n};\n\nstruct svc_serv;\n\nstruct nfs_callback_data {\n\tunsigned int users;\n\tstruct svc_serv *serv;\n};\n\nstruct xprtsec_parms {\n\tenum xprtsec_policies policy;\n\tkey_serial_t cert_serial;\n\tkey_serial_t privkey_serial;\n};\n\nstruct nfs_rpc_ops;\n\nstruct nfs_subversion;\n\nstruct nfs_client {\n\trefcount_t cl_count;\n\tatomic_t cl_mds_count;\n\tint cl_cons_state;\n\tlong unsigned int cl_res_state;\n\tlong unsigned int cl_flags;\n\tstruct __kernel_sockaddr_storage cl_addr;\n\tsize_t cl_addrlen;\n\tchar *cl_hostname;\n\tchar *cl_acceptor;\n\tstruct list_head cl_share_link;\n\tstruct list_head cl_superblocks;\n\tstruct rpc_clnt *cl_rpcclient;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tint cl_proto;\n\tstruct nfs_subversion *cl_nfs_mod;\n\tu32 cl_minorversion;\n\tunsigned int cl_nconnect;\n\tunsigned int cl_max_connect;\n\tconst char *cl_principal;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct list_head cl_ds_clients;\n\tlong: 32;\n\tu64 cl_clientid;\n\tnfs4_verifier cl_confirm;\n\tlong unsigned int cl_state;\n\tspinlock_t cl_lock;\n\tlong unsigned int cl_lease_time;\n\tlong unsigned int cl_last_renewal;\n\tstruct delayed_work cl_renewd;\n\tstruct rpc_wait_queue cl_rpcwaitq;\n\tstruct idmap *cl_idmap;\n\tconst char *cl_owner_id;\n\tu32 cl_cb_ident;\n\tconst struct nfs4_minor_version_ops *cl_mvops;\n\tlong unsigned int cl_mig_gen;\n\tstruct nfs4_slot_table *cl_slot_tbl;\n\tu32 cl_seqid;\n\tu32 cl_exchange_flags;\n\tstruct nfs4_session *cl_session;\n\tbool cl_preserve_clid;\n\tstruct nfs41_server_owner *cl_serverowner;\n\tstruct nfs41_server_scope *cl_serverscope;\n\tstruct nfs41_impl_id *cl_implid;\n\tlong unsigned int cl_sp4_flags;\n\twait_queue_head_t cl_lock_waitq;\n\tchar cl_ipaddr[48];\n\tstruct net *cl_net;\n\tnetns_tracker cl_ns_tracker;\n\tstruct list_head pending_cb_stateids;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct rpc_timeout;\n\nstruct nfs_client_initdata {\n\tlong unsigned int init_flags;\n\tconst char *hostname;\n\tconst struct __kernel_sockaddr_storage *addr;\n\tconst char *nodename;\n\tconst char *ip_addr;\n\tsize_t addrlen;\n\tstruct nfs_subversion *nfs_mod;\n\tint proto;\n\tu32 minorversion;\n\tunsigned int nconnect;\n\tunsigned int max_connect;\n\tstruct net *net;\n\tconst struct rpc_timeout *timeparms;\n\tconst struct cred *cred;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct nfs_clone_mount {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_commit_data;\n\nstruct nfs_commit_info;\n\nstruct nfs_page;\n\nstruct nfs_commit_completion_ops {\n\tvoid (*completion)(struct nfs_commit_data *);\n\tvoid (*resched_write)(struct nfs_commit_info *, struct nfs_page *);\n};\n\nstruct nfs_commitargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tlong: 32;\n\t__u64 offset;\n\t__u32 count;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_direct_req;\n\nstruct nfs_commit_data {\n\tstruct rpc_task task;\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_writeverf verf;\n\tstruct list_head pages;\n\tstruct list_head list;\n\tstruct nfs_direct_req *dreq;\n\tstruct nfs_commitargs args;\n\tstruct nfs_commitres res;\n\tstruct nfs_open_context *context;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_index;\n\tlong: 32;\n\tloff_t lwb;\n\tconst struct rpc_call_ops *mds_ops;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n\tint (*commit_done_cb)(struct rpc_task *, struct nfs_commit_data *);\n\tlong unsigned int flags;\n};\n\nstruct nfs_mds_commit_info;\n\nstruct nfs_commit_info {\n\tstruct inode *inode;\n\tstruct nfs_mds_commit_info *mds;\n\tstruct pnfs_ds_commit_info *ds;\n\tstruct nfs_direct_req *dreq;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n};\n\nstruct nfs_delegation {\n\tstruct hlist_node hash;\n\tstruct list_head super_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tfmode_t type;\n\tlong unsigned int pagemod_limit;\n\tlong: 32;\n\t__u64 change_attr;\n\tlong unsigned int test_gen;\n\tlong unsigned int flags;\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_mds_commit_info {\n\tatomic_t rpcs_out;\n\tatomic_long_t ncommit;\n\tstruct list_head list;\n};\n\nstruct nfs_direct_req {\n\tstruct kref kref;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct kiocb *iocb;\n\tstruct inode *inode;\n\tatomic_t io_count;\n\tspinlock_t lock;\n\tlong: 32;\n\tloff_t io_start;\n\tssize_t count;\n\tssize_t max_count;\n\tssize_t error;\n\tstruct completion completion;\n\tstruct nfs_mds_commit_info mds_cinfo;\n\tstruct pnfs_ds_commit_info ds_cinfo;\n\tstruct work_struct work;\n\tint flags;\n\tlong: 32;\n};\n\nstruct nfs_entry {\n\t__u64 ino;\n\t__u64 cookie;\n\tconst char *name;\n\tunsigned int len;\n\tint eof;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tunsigned char d_type;\n\tstruct nfs_server *server;\n\tlong: 32;\n};\n\nstruct nfs_find_desc {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_free_stateid_data {\n\tstruct nfs_server *server;\n\tstruct nfs41_free_stateid_args args;\n\tstruct nfs41_free_stateid_res res;\n};\n\nstruct nfs_fs_context {\n\tbool internal;\n\tbool skip_reconfig_option_check;\n\tbool need_mount;\n\tbool sloppy;\n\tunsigned int flags;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tunsigned int timeo;\n\tunsigned int retrans;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namlen;\n\tunsigned int options;\n\tunsigned int bsize;\n\tstruct nfs_auth_info auth_info;\n\trpc_authflavor_t selected_flavor;\n\tstruct xprtsec_parms xprtsec;\n\tchar *client_address;\n\tunsigned int version;\n\tunsigned int minorversion;\n\tchar *fscache_uniq;\n\tshort unsigned int protofamily;\n\tshort unsigned int mountfamily;\n\tbool has_sec_mnt_opts;\n\tint lock_status;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tu32 version;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t} mount_server;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tchar *export_path;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t\tshort unsigned int nconnect;\n\t\tshort unsigned int max_connect;\n\t\tshort unsigned int export_path_len;\n\t} nfs_server;\n\tstruct nfs_fh *mntfh;\n\tstruct nfs_server *server;\n\tstruct nfs_subversion *nfs_mod;\n\tstruct nfs_clone_mount clone_data;\n};\n\nstruct nfs_fsinfo {\n\tstruct nfs_fattr *fattr;\n\t__u32 rtmax;\n\t__u32 rtpref;\n\t__u32 rtmult;\n\t__u32 wtmax;\n\t__u32 wtpref;\n\t__u32 wtmult;\n\t__u32 dtpref;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\t__u32 lease_time;\n\t__u32 nlayouttypes;\n\t__u32 layouttype[8];\n\t__u32 blksize;\n\t__u32 clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\t__u32 xattr_support;\n};\n\nstruct nfs_fsstat {\n\tstruct nfs_fattr *fattr;\n\tlong: 32;\n\t__u64 tbytes;\n\t__u64 fbytes;\n\t__u64 abytes;\n\t__u64 tfiles;\n\t__u64 ffiles;\n\t__u64 afiles;\n};\n\nstruct nfs_getaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_getaclres {\n\tstruct nfs4_sequence_res seq_res;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tsize_t acl_data_offset;\n\tint acl_flags;\n\tstruct folio *acl_scratch;\n};\n\nstruct nfs_inode {\n\t__u64 fileid;\n\tstruct nfs_fh fh;\n\tlong unsigned int flags;\n\tlong unsigned int cache_validity;\n\tlong: 32;\n\tstruct timespec64 btime;\n\tlong unsigned int read_cache_jiffies;\n\tlong unsigned int attrtimeo;\n\tlong unsigned int attrtimeo_timestamp;\n\tlong unsigned int attr_gencount;\n\tstruct rb_root access_cache;\n\tstruct list_head access_cache_entry_lru;\n\tstruct list_head access_cache_inode_lru;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int cache_change_attribute;\n\t\t\t__be32 cookieverf[2];\n\t\t\tstruct rw_semaphore rmdir_sem;\n\t\t};\n\t\tstruct {\n\t\t\tatomic_long_t nrequests;\n\t\t\tatomic_long_t redirtied_pages;\n\t\t\tstruct nfs_mds_commit_info commit_info;\n\t\t\tstruct mutex commit_mutex;\n\t\t};\n\t};\n\tstruct list_head open_files;\n\tstruct {\n\t\tint cnt;\n\t\tlong: 32;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 end;\n\t\t} gap[16];\n\t} *ooo;\n\tstruct nfs4_cached_acl *nfs4_acl;\n\tstruct list_head open_states;\n\tstruct nfs_delegation *delegation;\n\tstruct rw_semaphore rwsem;\n\tstruct pnfs_layout_hdr *layout;\n\t__u64 write_io;\n\t__u64 read_io;\n\tstruct nfs4_xattr_cache *xattr_cache;\n\tlong: 32;\n\tunion {\n\t\tstruct inode vfs_inode;\n\t};\n};\n\nstruct nfs_io_completion {\n\tvoid (*complete)(void *);\n\tvoid *data;\n\tstruct kref refcount;\n};\n\nstruct nfs_iostats {\n\tlong long unsigned int bytes[8];\n\tlong unsigned int events[27];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct nfs_lock_context {\n\trefcount_t count;\n\tstruct list_head list;\n\tstruct nfs_open_context *open_context;\n\tfl_owner_t lockowner;\n\tatomic_t io_count;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_lockt_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_lockt_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct file_lock *denied;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct nfs_mount_data {\n\tint version;\n\tint fd;\n\tstruct nfs2_fh old_root;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct sockaddr_in addr;\n\tchar hostname[256];\n\tint namlen;\n\tunsigned int bsize;\n\tstruct nfs3_fh root;\n\tint pseudoflavor;\n\tchar context[257];\n};\n\nstruct nfs_mount_request {\n\tstruct __kernel_sockaddr_storage *sap;\n\tsize_t salen;\n\tchar *hostname;\n\tchar *dirpath;\n\tu32 version;\n\tshort unsigned int protocol;\n\tstruct nfs_fh *fh;\n\tint noresvport;\n\tunsigned int *auth_flav_len;\n\trpc_authflavor_t *auth_flavs;\n\tstruct net *net;\n};\n\nstruct rpc_program;\n\nstruct rpc_stat {\n\tconst struct rpc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int netreconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcretrans;\n\tunsigned int rpcauthrefresh;\n\tunsigned int rpcgarbage;\n};\n\nstruct nfs_netns_client;\n\nstruct nfs_net {\n\tstruct cache_detail *nfs_dns_resolve;\n\tstruct rpc_pipe *bl_device_pipe;\n\tstruct bl_dev_msg bl_mount_reply;\n\twait_queue_head_t bl_wq;\n\tstruct mutex bl_mutex;\n\tstruct list_head nfs_client_list;\n\tstruct list_head nfs_volume_list;\n\tstruct idr cb_ident_idr;\n\tshort unsigned int nfs_callback_tcpport;\n\tshort unsigned int nfs_callback_tcpport6;\n\tint cb_users[3];\n\tstruct list_head nfs4_data_server_cache;\n\tspinlock_t nfs4_data_server_lock;\n\tstruct nfs_netns_client *nfs_client;\n\tspinlock_t nfs_client_lock;\n\tlong: 32;\n\tktime_t boot_time;\n\tstruct rpc_stat rpcstats;\n\tstruct proc_dir_entry *proc_nfsfs;\n\tlong: 32;\n};\n\nstruct nfs_netns_client {\n\tstruct kobject kobject;\n\tstruct kobject nfs_net_kobj;\n\tstruct net *net;\n\tconst char *identifier;\n};\n\nstruct nfs_open_context {\n\tstruct nfs_lock_context lock_context;\n\tfl_owner_t flock_owner;\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\tstruct rpc_cred *ll_cred;\n\tstruct nfs4_state *state;\n\tfmode_t mode;\n\tint error;\n\tlong unsigned int flags;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tstruct nfs_file_localio nfl;\n};\n\nstruct nfs_open_dir_context {\n\tstruct list_head list;\n\tatomic_t cache_hits;\n\tatomic_t cache_misses;\n\tlong unsigned int attr_gencount;\n\t__be32 verf[2];\n\tlong: 32;\n\t__u64 dir_cookie;\n\t__u64 last_cookie;\n\tlong unsigned int page_index;\n\tunsigned int dtsize;\n\tbool force_clear;\n\tbool eof;\n\tstruct callback_head callback_head;\n\tlong: 32;\n};\n\nstruct nfs_page {\n\tstruct list_head wb_list;\n\tunion {\n\t\tstruct page *wb_page;\n\t\tstruct folio *wb_folio;\n\t};\n\tstruct nfs_lock_context *wb_lock_context;\n\tlong unsigned int wb_index;\n\tunsigned int wb_offset;\n\tunsigned int wb_pgbase;\n\tunsigned int wb_bytes;\n\tstruct kref wb_kref;\n\tlong unsigned int wb_flags;\n\tstruct nfs_write_verifier wb_verf;\n\tstruct nfs_page *wb_this_page;\n\tstruct nfs_page *wb_head;\n\tshort unsigned int wb_nio;\n};\n\nstruct nfs_page_array {\n\tstruct page **pagevec;\n\tunsigned int npages;\n\tstruct page *page_array[8];\n};\n\nstruct nfs_page_iter_page {\n\tconst struct nfs_page *req;\n\tsize_t count;\n};\n\nstruct nfs_pgio_mirror {\n\tstruct list_head pg_list;\n\tlong unsigned int pg_bytes_written;\n\tsize_t pg_count;\n\tsize_t pg_bsize;\n\tunsigned int pg_base;\n\tunsigned char pg_recoalesce: 1;\n};\n\nstruct nfs_pageio_ops;\n\nstruct nfs_rw_ops;\n\nstruct nfs_pgio_completion_ops;\n\nstruct nfs_pageio_descriptor {\n\tstruct inode *pg_inode;\n\tconst struct nfs_pageio_ops *pg_ops;\n\tconst struct nfs_rw_ops *pg_rw_ops;\n\tint pg_ioflags;\n\tint pg_error;\n\tconst struct rpc_call_ops *pg_rpc_callops;\n\tconst struct nfs_pgio_completion_ops *pg_completion_ops;\n\tstruct pnfs_layout_segment *pg_lseg;\n\tstruct nfs_io_completion *pg_io_completion;\n\tstruct nfs_direct_req *pg_dreq;\n\tunsigned int pg_bsize;\n\tu32 pg_mirror_count;\n\tstruct nfs_pgio_mirror *pg_mirrors;\n\tstruct nfs_pgio_mirror pg_mirrors_static[1];\n\tstruct nfs_pgio_mirror *pg_mirrors_dynamic;\n\tu32 pg_mirror_idx;\n\tshort unsigned int pg_maxretrans;\n\tunsigned char pg_moreio: 1;\n};\n\nstruct nfs_pageio_ops {\n\tvoid (*pg_init)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tsize_t (*pg_test)(struct nfs_pageio_descriptor *, struct nfs_page *, struct nfs_page *);\n\tint (*pg_doio)(struct nfs_pageio_descriptor *);\n\tunsigned int (*pg_get_mirror_count)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tvoid (*pg_cleanup)(struct nfs_pageio_descriptor *);\n\tstruct nfs_pgio_mirror * (*pg_get_mirror)(struct nfs_pageio_descriptor *, u32);\n\tu32 (*pg_set_mirror)(struct nfs_pageio_descriptor *, u32);\n};\n\nstruct nfs_pathconf {\n\tstruct nfs_fattr *fattr;\n\t__u32 max_link;\n\t__u32 max_namelen;\n};\n\nstruct nfs_pgio_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct nfs_open_context *context;\n\tstruct nfs_lock_context *lock_context;\n\tnfs4_stateid stateid;\n\t__u64 offset;\n\t__u32 count;\n\tunsigned int pgbase;\n\tstruct page **pages;\n\tunion {\n\t\tunsigned int replen;\n\t\tstruct {\n\t\t\tconst u32 *bitmask;\n\t\t\tu32 bitmask_store[3];\n\t\t\tenum nfs3_stable_how stable;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header;\n\nstruct nfs_pgio_completion_ops {\n\tvoid (*error_cleanup)(struct list_head *, int);\n\tvoid (*init_hdr)(struct nfs_pgio_header *);\n\tvoid (*completion)(struct nfs_pgio_header *);\n\tvoid (*reschedule_io)(struct nfs_pgio_header *);\n};\n\nstruct nfs_pgio_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\t__u64 count;\n\t__u32 op_status;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int replen;\n\t\t\tint eof;\n\t\t\tvoid *scratch;\n\t\t};\n\t\tstruct {\n\t\t\tstruct nfs_writeverf *verf;\n\t\t\tconst struct nfs_server *server;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header {\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct list_head pages;\n\tstruct nfs_page *req;\n\tstruct nfs_writeverf verf;\n\tfmode_t rw_mode;\n\tstruct pnfs_layout_segment *lseg;\n\tloff_t io_start;\n\tconst struct rpc_call_ops *mds_ops;\n\tvoid (*release)(struct nfs_pgio_header *);\n\tconst struct nfs_pgio_completion_ops *completion_ops;\n\tconst struct nfs_rw_ops *rw_ops;\n\tstruct nfs_io_completion *io_completion;\n\tstruct nfs_direct_req *dreq;\n\tshort unsigned int retrans;\n\tint pnfs_error;\n\tint error;\n\tunsigned int good_bytes;\n\tlong unsigned int flags;\n\tlong: 32;\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_pgio_args args;\n\tstruct nfs_pgio_res res;\n\tlong unsigned int timestamp;\n\tint (*pgio_done_cb)(struct rpc_task *, struct nfs_pgio_header *);\n\t__u64 mds_offset;\n\tstruct nfs_page_array page_array;\n\tstruct nfs_client *ds_clp;\n\tu32 ds_commit_idx;\n\tu32 pgio_mirror_idx;\n\tlong: 32;\n};\n\nstruct nfs_readdir_arg {\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\t__be32 *verf;\n\tlong: 32;\n\tu64 cookie;\n\tstruct page **pages;\n\tunsigned int page_len;\n\tbool plus;\n\tlong: 32;\n};\n\nstruct nfs_readdir_descriptor {\n\tstruct file *file;\n\tstruct folio *folio;\n\tstruct dir_context *ctx;\n\tlong unsigned int folio_index;\n\tlong unsigned int folio_index_max;\n\tlong: 32;\n\tu64 dir_cookie;\n\tu64 last_cookie;\n\tloff_t current_index;\n\t__be32 verf[2];\n\tlong unsigned int dir_verifier;\n\tlong unsigned int timestamp;\n\tlong unsigned int gencount;\n\tlong unsigned int attr_gencount;\n\tunsigned int cache_entry_index;\n\tunsigned int buffer_fills;\n\tunsigned int dtsize;\n\tbool clear_cache;\n\tbool plus;\n\tbool eob;\n\tbool eof;\n};\n\nstruct nfs_readdir_res {\n\t__be32 *verf;\n};\n\nstruct nfs_referral_count {\n\tstruct list_head list;\n\tconst struct task_struct *task;\n\tunsigned int referral_count;\n};\n\nstruct nfs_removeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tlong: 32;\n\tstruct qstr name;\n};\n\nstruct nfs_removeres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs_fattr *dir_attr;\n\tlong: 32;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs_renameargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *old_dir;\n\tconst struct nfs_fh *new_dir;\n\tconst struct qstr *old_name;\n\tconst struct qstr *new_name;\n};\n\nstruct nfs_renameres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs4_change_info old_cinfo;\n\tstruct nfs_fattr *old_fattr;\n\tlong: 32;\n\tstruct nfs4_change_info new_cinfo;\n\tstruct nfs_fattr *new_fattr;\n\tlong: 32;\n};\n\nstruct nfs_renamedata {\n\tstruct nfs_renameargs args;\n\tstruct nfs_renameres res;\n\tstruct rpc_task task;\n\tconst struct cred *cred;\n\tstruct inode *old_dir;\n\tstruct dentry *old_dentry;\n\tlong: 32;\n\tstruct nfs_fattr old_fattr;\n\tstruct inode *new_dir;\n\tstruct dentry *new_dentry;\n\tstruct nfs_fattr new_fattr;\n\tvoid (*complete)(struct rpc_task *, struct nfs_renamedata *);\n\tlong int timeout;\n\tbool cancelled;\n\tlong: 32;\n};\n\nstruct nlmclnt_operations;\n\nstruct nfs_unlinkdata;\n\nstruct nfs_rpc_ops {\n\tu32 version;\n\tconst struct dentry_operations *dentry_ops;\n\tconst struct inode_operations *dir_inode_ops;\n\tconst struct inode_operations *file_inode_ops;\n\tconst struct file_operations *file_ops;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tint (*getroot)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*submount)(struct fs_context *, struct nfs_server *);\n\tint (*try_get_tree)(struct fs_context *);\n\tint (*getattr)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, struct inode *);\n\tint (*setattr)(struct dentry *, struct nfs_fattr *, struct iattr *);\n\tint (*lookup)(struct inode *, struct dentry *, const struct qstr *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*lookupp)(struct inode *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*access)(struct inode *, struct nfs_access_entry *, const struct cred *);\n\tint (*readlink)(struct inode *, struct page *, unsigned int, unsigned int);\n\tint (*create)(struct inode *, struct dentry *, struct iattr *, int);\n\tint (*remove)(struct inode *, struct dentry *);\n\tvoid (*unlink_setup)(struct rpc_message *, struct dentry *, struct inode *);\n\tvoid (*unlink_rpc_prepare)(struct rpc_task *, struct nfs_unlinkdata *);\n\tint (*unlink_done)(struct rpc_task *, struct inode *);\n\tvoid (*rename_setup)(struct rpc_message *, struct dentry *, struct dentry *, struct inode *);\n\tvoid (*rename_rpc_prepare)(struct rpc_task *, struct nfs_renamedata *);\n\tint (*rename_done)(struct rpc_task *, struct inode *, struct inode *);\n\tint (*link)(struct inode *, struct inode *, const struct qstr *);\n\tint (*symlink)(struct inode *, struct dentry *, struct folio *, unsigned int, struct iattr *);\n\tstruct dentry * (*mkdir)(struct inode *, struct dentry *, struct iattr *);\n\tint (*rmdir)(struct inode *, const struct qstr *);\n\tint (*readdir)(struct nfs_readdir_arg *, struct nfs_readdir_res *);\n\tint (*mknod)(struct inode *, struct dentry *, struct iattr *, dev_t);\n\tint (*statfs)(struct nfs_server *, struct nfs_fh *, struct nfs_fsstat *);\n\tint (*fsinfo)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*pathconf)(struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *);\n\tint (*set_capabilities)(struct nfs_server *, struct nfs_fh *);\n\tint (*decode_dirent)(struct xdr_stream *, struct nfs_entry *, bool);\n\tint (*pgio_rpc_prepare)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*read_setup)(struct nfs_pgio_header *, struct rpc_message *);\n\tint (*read_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*write_setup)(struct nfs_pgio_header *, struct rpc_message *, struct rpc_clnt **);\n\tint (*write_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*commit_setup)(struct nfs_commit_data *, struct rpc_message *, struct rpc_clnt **);\n\tvoid (*commit_rpc_prepare)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*commit_done)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tint (*lock_check_bounds)(const struct file_lock *);\n\tvoid (*clear_acl_cache)(struct inode *);\n\tvoid (*close_context)(struct nfs_open_context *, int);\n\tstruct inode * (*open_context)(struct inode *, struct nfs_open_context *, int, struct iattr *, int *);\n\tint (*have_delegation)(struct inode *, fmode_t, int);\n\tvoid (*return_delegation)(struct inode *);\n\tstruct nfs_client * (*alloc_client)(const struct nfs_client_initdata *);\n\tstruct nfs_client * (*init_client)(struct nfs_client *, const struct nfs_client_initdata *);\n\tvoid (*free_client)(struct nfs_client *);\n\tstruct nfs_server * (*create_server)(struct fs_context *);\n\tstruct nfs_server * (*clone_server)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, rpc_authflavor_t);\n\tint (*discover_trunking)(struct nfs_server *, struct nfs_fh *);\n\tvoid (*enable_swap)(struct inode *);\n\tvoid (*disable_swap)(struct inode *);\n};\n\nstruct rpc_task_setup;\n\nstruct nfs_rw_ops {\n\tstruct nfs_pgio_header * (*rw_alloc_header)(void);\n\tvoid (*rw_free_header)(struct nfs_pgio_header *);\n\tint (*rw_done)(struct rpc_task *, struct nfs_pgio_header *, struct inode *);\n\tvoid (*rw_result)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*rw_initiate)(struct nfs_pgio_header *, struct rpc_message *, const struct nfs_rpc_ops *, struct rpc_task_setup *, int);\n};\n\nstruct nfs_seqid {\n\tstruct nfs_seqid_counter *sequence;\n\tstruct list_head list;\n\tstruct rpc_task *task;\n};\n\nstruct nlm_host;\n\nstruct nfs_server {\n\tstruct nfs_client *nfs_client;\n\tstruct list_head client_link;\n\tstruct list_head master_link;\n\tstruct rpc_clnt *client;\n\tstruct rpc_clnt *client_acl;\n\tstruct nlm_host *nlm_host;\n\tstruct nfs_iostats *io_stats;\n\twait_queue_head_t write_congestion_wait;\n\tatomic_long_t writeback;\n\tunsigned int write_congested;\n\tunsigned int flags;\n\tunsigned int automount_inherit;\n\tunsigned int caps;\n\tlong: 32;\n\t__u64 fattr_valid;\n\tunsigned int rsize;\n\tunsigned int rpages;\n\tunsigned int wsize;\n\tunsigned int wtmult;\n\tunsigned int dtsize;\n\tshort unsigned int port;\n\tunsigned int bsize;\n\tunsigned int gxasize;\n\tunsigned int sxasize;\n\tunsigned int lxasize;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namelen;\n\tunsigned int options;\n\tunsigned int clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\tstruct nfs_fsid fsid;\n\tint s_sysfs_id;\n\tlong: 32;\n\t__u64 maxfilesize;\n\tlong unsigned int mount_time;\n\tstruct super_block *super;\n\tdev_t s_dev;\n\tstruct nfs_auth_info auth_info;\n\tu32 fh_expire_type;\n\tu32 pnfs_blksize;\n\tu32 attr_bitmask[3];\n\tu32 attr_bitmask_nl[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 cache_consistency_bitmask[3];\n\tu32 acl_bitmask;\n\tstruct pnfs_layoutdriver_type *pnfs_curr_ld;\n\tstruct rpc_wait_queue roc_rpcwaitq;\n\tstruct rb_root state_owners;\n\tlong: 32;\n\tatomic64_t owner_ctr;\n\tstruct list_head state_owners_lru;\n\tstruct list_head layouts;\n\tstruct list_head delegations;\n\tspinlock_t delegations_lock;\n\tstruct list_head delegations_return;\n\tstruct list_head delegations_lru;\n\tstruct list_head delegations_delayed;\n\tatomic_long_t nr_active_delegations;\n\tunsigned int delegation_hash_mask;\n\tstruct hlist_head *delegation_hash_table;\n\tstruct list_head ss_copies;\n\tstruct list_head ss_src_copies;\n\tlong unsigned int delegation_flags;\n\tlong unsigned int delegation_gen;\n\tlong unsigned int mig_gen;\n\tlong unsigned int mig_status;\n\tvoid (*destroy)(struct nfs_server *);\n\tatomic_t active;\n\tstruct __kernel_sockaddr_storage mountd_address;\n\tsize_t mountd_addrlen;\n\tu32 mountd_version;\n\tshort unsigned int mountd_port;\n\tshort unsigned int mountd_protocol;\n\tstruct rpc_wait_queue uoc_rpcwaitq;\n\tunsigned int read_hdrsize;\n\tconst struct cred *cred;\n\tbool has_sec_mnt_opts;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct nfs_setaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_setaclres {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs_setattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct iattr *iap;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n};\n\nstruct nfs_setattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs_ssc_client_ops {\n\tvoid (*sco_sb_deactive)(struct super_block *);\n};\n\nstruct nfs_ssc_client_ops_tbl {\n\tconst struct nfs4_ssc_client_ops *ssc_nfs4_ops;\n\tconst struct nfs_ssc_client_ops *ssc_nfs_ops;\n};\n\nstruct rpc_version;\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct nfs_subversion {\n\tstruct module *owner;\n\tstruct file_system_type *nfs_fs;\n\tconst struct rpc_version *rpc_vers;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tconst struct super_operations *sops;\n\tconst struct xattr_handler * const *xattr;\n};\n\nstruct nfs_unlinkdata {\n\tstruct nfs_removeargs args;\n\tstruct nfs_removeres res;\n\tstruct dentry *dentry;\n\twait_queue_head_t wq;\n\tconst struct cred *cred;\n\tlong: 32;\n\tstruct nfs_fattr dir_attr;\n\tlong int timeout;\n\tlong: 32;\n};\n\nstruct xdr_array2_desc;\n\ntypedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *, void *);\n\nstruct xdr_array2_desc {\n\tunsigned int elem_size;\n\tunsigned int array_len;\n\tunsigned int array_maxlen;\n\txdr_xcode_elem_t xcode;\n};\n\nstruct nfsacl_decode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n};\n\nstruct nfsacl_encode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n\tint typeflag;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct nfsacl_simple_acl {\n\tstruct posix_acl_hdr acl;\n\tstruct posix_acl_entry ace[4];\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tlong: 32;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tlong: 32;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tlong: 32;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlm_cookie {\n\tunsigned char data[32];\n\tunsigned int len;\n};\n\nstruct nlm_lock {\n\tchar *caller;\n\tunsigned int len;\n\tstruct nfs_fh fh;\n\tstruct xdr_netobj oh;\n\tu32 svid;\n\tu64 lock_start;\n\tu64 lock_len;\n\tstruct file_lock fl;\n};\n\nstruct nlm_args {\n\tstruct nlm_cookie cookie;\n\tlong: 32;\n\tstruct nlm_lock lock;\n\tu32 block;\n\tu32 reclaim;\n\tu32 state;\n\tu32 monitor;\n\tu32 fsm_access;\n\tu32 fsm_mode;\n};\n\nstruct nlm_rqst;\n\nstruct nlm_file;\n\nstruct nlm_block {\n\tstruct kref b_count;\n\tstruct list_head b_list;\n\tstruct list_head b_flist;\n\tstruct nlm_rqst *b_call;\n\tstruct svc_serv *b_daemon;\n\tstruct nlm_host *b_host;\n\tlong unsigned int b_when;\n\tunsigned int b_id;\n\tunsigned char b_granted;\n\tstruct nlm_file *b_file;\n\tstruct cache_req *b_cache_req;\n\tstruct cache_deferred_req *b_deferred_req;\n\tunsigned int b_flags;\n};\n\nstruct nlm_share;\n\nstruct nlm_file {\n\tstruct hlist_node f_list;\n\tstruct nfs_fh f_handle;\n\tstruct file *f_file[2];\n\tstruct nlm_share *f_shares;\n\tstruct list_head f_blocks;\n\tunsigned int f_locks;\n\tunsigned int f_count;\n\tstruct mutex f_mutex;\n};\n\nstruct nsm_handle;\n\nstruct nlm_host {\n\tstruct hlist_node h_hash;\n\tstruct __kernel_sockaddr_storage h_addr;\n\tsize_t h_addrlen;\n\tstruct __kernel_sockaddr_storage h_srcaddr;\n\tsize_t h_srcaddrlen;\n\tstruct rpc_clnt *h_rpcclnt;\n\tchar *h_name;\n\tu32 h_version;\n\tshort unsigned int h_proto;\n\tshort unsigned int h_reclaiming: 1;\n\tshort unsigned int h_server: 1;\n\tshort unsigned int h_noresvport: 1;\n\tshort unsigned int h_inuse: 1;\n\twait_queue_head_t h_gracewait;\n\tstruct rw_semaphore h_rwsem;\n\tu32 h_state;\n\tu32 h_nsmstate;\n\tu32 h_pidcount;\n\trefcount_t h_count;\n\tstruct mutex h_mutex;\n\tlong unsigned int h_nextrebind;\n\tlong unsigned int h_expires;\n\tstruct list_head h_lockowners;\n\tspinlock_t h_lock;\n\tstruct list_head h_granted;\n\tstruct list_head h_reclaim;\n\tstruct nsm_handle *h_nsmhandle;\n\tchar *h_addrbuf;\n\tstruct net *net;\n\tconst struct cred *h_cred;\n\tchar nodename[65];\n\tconst struct nlmclnt_operations *h_nlmclnt_ops;\n};\n\nstruct nlm_lockowner {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct nlm_host *host;\n\tfl_owner_t owner;\n\tuint32_t pid;\n};\n\nstruct nlm_lookup_host_info {\n\tconst int server;\n\tconst struct sockaddr *sap;\n\tconst size_t salen;\n\tconst short unsigned int protocol;\n\tconst u32 version;\n\tconst char *hostname;\n\tconst size_t hostname_len;\n\tconst int noresvport;\n\tstruct net *net;\n\tconst struct cred *cred;\n};\n\nstruct nsm_private {\n\tunsigned char data[16];\n};\n\nstruct nlm_reboot {\n\tchar *mon;\n\tunsigned int len;\n\tu32 state;\n\tstruct nsm_private priv;\n};\n\nstruct nlm_res {\n\tstruct nlm_cookie cookie;\n\t__be32 status;\n\tstruct nlm_lock lock;\n};\n\nstruct nlm_rqst {\n\trefcount_t a_count;\n\tunsigned int a_flags;\n\tstruct nlm_host *a_host;\n\tlong: 32;\n\tstruct nlm_args a_args;\n\tstruct nlm_res a_res;\n\tstruct nlm_block *a_block;\n\tunsigned int a_retries;\n\tu8 a_owner[74];\n\tvoid *a_callback_data;\n};\n\nstruct nlm_share {\n\tstruct nlm_share *s_next;\n\tstruct nlm_host *s_host;\n\tstruct nlm_file *s_file;\n\tstruct xdr_netobj s_owner;\n\tu32 s_access;\n\tu32 s_mode;\n};\n\nstruct nlm_wait {\n\tstruct list_head b_list;\n\twait_queue_head_t b_wait;\n\tstruct nlm_host *b_host;\n\tstruct file_lock *b_lock;\n\t__be32 b_status;\n};\n\nstruct nlmclnt_initdata {\n\tconst char *hostname;\n\tconst struct sockaddr *address;\n\tsize_t addrlen;\n\tshort unsigned int protocol;\n\tu32 nfs_version;\n\tint noresvport;\n\tstruct net *net;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tconst struct cred *cred;\n};\n\nstruct nlmclnt_operations {\n\tvoid (*nlmclnt_alloc_call)(void *);\n\tbool (*nlmclnt_unlock_prepare)(struct rpc_task *, void *);\n\tvoid (*nlmclnt_release_call)(void *);\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nlmsvc_binding {\n\t__be32 (*fopen)(struct svc_rqst *, struct nfs_fh *, struct file **, int);\n\tvoid (*fclose)(struct file *);\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\nstruct nmk_cfg_param {\n\tconst char *property;\n\tlong unsigned int config;\n\tconst long unsigned int *choice;\n\tint size;\n};\n\nstruct nmk_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct nmk_gpio_chip {\n\tstruct gpio_chip chip;\n\tvoid *addr;\n\tstruct clk *clk;\n\tunsigned int bank;\n\tvoid (*set_ioforce)(bool);\n\tspinlock_t lock;\n\tbool sleepmode;\n\tbool is_mobileye_soc;\n\tu32 edge_rising;\n\tu32 edge_falling;\n\tu32 real_wake;\n\tu32 rwimsc;\n\tu32 fwimsc;\n\tu32 rimsc;\n\tu32 fimsc;\n\tu32 pull_up;\n\tu32 lowemi;\n};\n\nstruct nmk_i2c_dev {\n\tstruct i2c_vendor_data *vendor;\n\tstruct amba_device *adev;\n\tstruct i2c_adapter adap;\n\tint irq;\n\tvoid *virtbase;\n\tstruct clk *clk;\n\tstruct i2c_nmk_client cli;\n\tu32 clk_freq;\n\tunsigned char tft;\n\tunsigned char rft;\n\tu32 timeout_usecs;\n\tenum i2c_freq_mode sm;\n\tint stop;\n\tstruct wait_queue_head xfer_wq;\n\tbool xfer_done;\n\tint result;\n\tbool has_32b_bus;\n\tlong: 32;\n};\n\nstruct nmk_pinctrl_soc_data;\n\nstruct nmk_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tconst struct nmk_pinctrl_soc_data *soc;\n\tvoid *prcm_base;\n};\n\nstruct nmk_pingroup;\n\nstruct prcm_gpiocr_altcx_pin_desc;\n\nstruct nmk_pinctrl_soc_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct nmk_function *functions;\n\tunsigned int nfunctions;\n\tconst struct nmk_pingroup *groups;\n\tunsigned int ngroups;\n\tconst struct prcm_gpiocr_altcx_pin_desc *altcx_pins;\n\tunsigned int npins_altcx;\n\tconst u16 *prcm_gpiocr_registers;\n};\n\nstruct nmk_pingroup {\n\tstruct pingroup grp;\n\tint altsetting;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct notif_entry {\n\tstruct list_head link;\n\tstruct completion c;\n\tu_int key;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct npcm_udc_data {\n\tstruct platform_device *ci;\n\tstruct clk *core_clk;\n\tstruct ci_hdrc_platform_data pdata;\n};\n\nstruct ns2_led_modval;\n\nstruct ns2_led {\n\tstruct led_classdev cdev;\n\tstruct gpio_desc *cmd;\n\tstruct gpio_desc *slow;\n\tbool can_sleep;\n\tunsigned char sata;\n\trwlock_t rw_lock;\n\tint num_modes;\n\tstruct ns2_led_modval *modval;\n};\n\nstruct ns2_led_modval {\n\tu32 mode;\n\tu32 cmd_level;\n\tu32 slow_level;\n};\n\nstruct ns2_phy_driver;\n\nstruct ns2_phy_data {\n\tstruct ns2_phy_driver *driver;\n\tstruct phy *phy;\n\tint new_state;\n};\n\nstruct ns2_phy_driver {\n\tvoid *icfgdrd_regs;\n\tvoid *idmdrd_rst_ctrl;\n\tvoid *crmu_usb2_ctrl;\n\tvoid *usb2h_strap_reg;\n\tstruct ns2_phy_data *data;\n\tstruct extcon_dev *edev;\n\tstruct gpio_desc *vbus_gpiod;\n\tstruct gpio_desc *id_gpiod;\n\tint id_irq;\n\tint vbus_irq;\n\tlong unsigned int debounce_jiffies;\n\tstruct delayed_work wq_extcon;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct ns_pinctrl {\n\tstruct device *dev;\n\tunsigned int chipset_flag;\n\tstruct pinctrl_dev *pctldev;\n\tvoid *base;\n\tstruct pinctrl_desc pctldesc;\n};\n\nstruct ns_pinctrl_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tconst unsigned int num_groups;\n\tunsigned int chipsets;\n};\n\nstruct ns_pinctrl_group {\n\tconst char *name;\n\tunsigned int *pins;\n\tconst unsigned int num_pins;\n\tunsigned int chipsets;\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct nsm_args {\n\tstruct nsm_private *priv;\n\tu32 prog;\n\tu32 vers;\n\tu32 proc;\n\tchar *mon_name;\n\tconst char *nodename;\n};\n\nstruct nsm_handle {\n\tstruct list_head sm_link;\n\trefcount_t sm_count;\n\tchar *sm_mon_name;\n\tchar *sm_name;\n\tstruct __kernel_sockaddr_storage sm_addr;\n\tsize_t sm_addrlen;\n\tunsigned int sm_monitored: 1;\n\tunsigned int sm_sticky: 1;\n\tstruct nsm_private sm_priv;\n\tchar sm_addrbuf[51];\n};\n\nstruct nsm_res {\n\tu32 status;\n\tu32 state;\n};\n\nstruct nsp_gpio {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *io_ctrl;\n\tstruct gpio_chip gc;\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc pctldesc;\n\traw_spinlock_t lock;\n};\n\nstruct nsp_mux {\n\tunsigned int base;\n\tunsigned int shift;\n\tunsigned int mask;\n\tunsigned int alt;\n};\n\nstruct nsp_mux_log {\n\tstruct nsp_mux mux;\n\tbool is_configured;\n};\n\nstruct nsp_pin {\n\tunsigned int pin;\n\tchar *name;\n\tunsigned int gpio_select;\n};\n\nstruct nsp_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tconst unsigned int num_groups;\n};\n\nstruct nsp_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tconst unsigned int num_pins;\n\tconst struct nsp_mux mux;\n};\n\nstruct nsp_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct device *dev;\n\tvoid *base0;\n\tvoid *base1;\n\tvoid *base2;\n\tconst struct nsp_pin_group *groups;\n\tunsigned int num_groups;\n\tconst struct nsp_pin_function *functions;\n\tunsigned int num_functions;\n\tstruct nsp_mux_log *mux_log;\n\tspinlock_t lock;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n};\n\nstruct ntfs_fnd {\n\tint level;\n\tstruct indx_node *nodes[20];\n\tstruct NTFS_DE *de[20];\n\tstruct NTFS_DE *root_de;\n};\n\ntypedef int (*NTFS_CMP_FUNC)(const void *, size_t, const void *, size_t, const void *);\n\nstruct ntfs_index {\n\tstruct runs_tree bitmap_run;\n\tstruct runs_tree alloc_run;\n\tstruct rw_semaphore run_lock;\n\tsize_t version;\n\tNTFS_CMP_FUNC cmp;\n\tu8 index_bits;\n\tu8 idx2vbn_bits;\n\tu8 vbn2vbo_bits;\n\tu8 type;\n};\n\nstruct ntfs_inode {\n\tstruct mft_inode mi;\n\tu64 i_valid;\n\tstruct timespec64 i_crtime;\n\tstruct mutex ni_lock;\n\tenum FILE_ATTRIBUTE std_fa;\n\t__le32 std_security_id;\n\tstruct rb_root mi_tree;\n\tu8 mi_loaded;\n\tu8 ni_bad;\n\tunion {\n\t\tstruct ntfs_index dir;\n\t\tstruct {\n\t\t\tstruct rw_semaphore run_lock;\n\t\t\tstruct runs_tree run;\n\t\t\tstruct runs_tree run_da;\n\t\t} file;\n\t};\n\tstruct {\n\t\tstruct runs_tree run;\n\t\tstruct ATTR_LIST_ENTRY *le;\n\t\tsize_t size;\n\t\tbool dirty;\n\t} attr_list;\n\tsize_t ni_flags;\n\tlong: 32;\n\tstruct inode vfs_inode;\n};\n\nstruct restart_info {\n\tu64 last_lsn;\n\tstruct RESTART_HDR *r_page;\n\tu32 vbo;\n\tbool chkdsk_was_run;\n\tbool valid_page;\n\tbool initialized;\n\tbool restart;\n\tlong: 32;\n};\n\nstruct ntfs_log {\n\tstruct ntfs_inode *ni;\n\tu32 l_size;\n\tu32 orig_file_size;\n\tu32 sys_page_size;\n\tu32 sys_page_mask;\n\tu32 page_size;\n\tu32 page_mask;\n\tu8 page_bits;\n\tstruct RECORD_PAGE_HDR *one_page_buf;\n\tstruct RESTART_TABLE *open_attr_tbl;\n\tu32 transaction_id;\n\tu32 clst_per_page;\n\tu32 first_page;\n\tu32 next_page;\n\tu32 ra_off;\n\tu32 data_off;\n\tu32 restart_size;\n\tu32 data_size;\n\tu16 record_header_len;\n\tlong: 32;\n\tu64 seq_num;\n\tu32 seq_num_bits;\n\tu32 file_data_bits;\n\tu32 seq_num_mask;\n\tstruct RESTART_AREA *ra;\n\tu32 ra_size;\n\tbool init_ra;\n\tbool set_dirty;\n\tu64 oldest_lsn;\n\tu32 oldest_lsn_off;\n\tlong: 32;\n\tu64 last_lsn;\n\tu32 total_avail;\n\tu32 total_avail_pages;\n\tu32 total_undo_commit;\n\tu32 max_current_avail;\n\tu32 current_avail;\n\tu32 reserved;\n\tshort int major_ver;\n\tshort int minor_ver;\n\tu32 l_flags;\n\tu32 current_openlog_count;\n\tstruct CLIENT_ID client_id;\n\tu32 client_undo_commit;\n\tlong: 32;\n\tstruct restart_info rst_info;\n\tstruct restart_info rst_info2;\n\tstruct file_ra_state read_ahead;\n};\n\nstruct ntfs_mount_options {\n\tchar *nls_name;\n\tstruct nls_table *nls;\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tu16 fs_fmask_inv;\n\tu16 fs_dmask_inv;\n\tunsigned int fmask: 1;\n\tunsigned int dmask: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int discard: 1;\n\tunsigned int sparse: 1;\n\tunsigned int showmeta: 1;\n\tunsigned int nohidden: 1;\n\tunsigned int hide_dot_files: 1;\n\tunsigned int windows_names: 1;\n\tunsigned int force: 1;\n\tunsigned int prealloc: 1;\n\tunsigned int nocase: 1;\n\tunsigned int delalloc: 1;\n};\n\nstruct ntfs_run {\n\tCLST vcn;\n\tCLST len;\n\tCLST lcn;\n};\n\nstruct wnd_bitmap {\n\tstruct super_block *sb;\n\tstruct rw_semaphore rw_lock;\n\tstruct runs_tree run;\n\tsize_t nbits;\n\tsize_t total_zeroes;\n\tu16 *free_bits;\n\tsize_t nwnd;\n\tu32 bits_last;\n\tstruct rb_root start_tree;\n\tstruct rb_root count_tree;\n\tsize_t count;\n\tint uptodated;\n\tsize_t extent_min;\n\tsize_t extent_max;\n\tsize_t zone_bit;\n\tsize_t zone_end;\n\tbool inited;\n};\n\nstruct ntfs_sb_info {\n\tstruct super_block *sb;\n\tu32 discard_granularity;\n\tu64 discard_granularity_mask_inv;\n\tu32 bdev_blocksize;\n\tu32 cluster_size;\n\tu32 cluster_mask;\n\tlong: 32;\n\tu64 cluster_mask_inv;\n\tu32 block_mask;\n\tu32 blocks_per_cluster;\n\tu32 record_size;\n\tu32 index_size;\n\tu8 cluster_bits;\n\tu8 record_bits;\n\tlong: 32;\n\tu64 maxbytes;\n\tu64 maxbytes_sparse;\n\tlong unsigned int flags;\n\tCLST zone_max;\n\tCLST bad_clusters;\n\tu16 max_bytes_per_attr;\n\tu16 attr_size_tr;\n\tCLST objid_no;\n\tCLST quota_no;\n\tCLST reparse_no;\n\tCLST usn_jrnl_no;\n\tstruct ATTR_DEF_ENTRY *def_table;\n\tu32 def_entries;\n\tu32 ea_max_size;\n\tstruct MFT_REC *new_rec;\n\tu16 *upcase;\n\tlong: 32;\n\tstruct {\n\t\tu64 lbo;\n\t\tu64 lbo2;\n\t\tstruct ntfs_inode *ni;\n\t\tstruct wnd_bitmap bitmap;\n\t\tulong reserved_bitmap;\n\t\tsize_t next_free;\n\t\tsize_t used;\n\t\tu32 recs_mirr;\n\t\tu8 next_reserved;\n\t\tu8 reserved_bitmap_inited;\n\t} mft;\n\tstruct {\n\t\tstruct wnd_bitmap bitmap;\n\t\tCLST next_free_lcn;\n\t\tatomic_t da;\n\t} used;\n\tstruct {\n\t\tu64 size;\n\t\tu64 blocks;\n\t\tu64 ser_num;\n\t\tstruct ntfs_inode *ni;\n\t\t__le16 flags;\n\t\tu8 major_ver;\n\t\tu8 minor_ver;\n\t\tchar label[256];\n\t\tbool real_dirty;\n\t\tlong: 32;\n\t} volume;\n\tstruct {\n\t\tstruct ntfs_index index_sii;\n\t\tstruct ntfs_index index_sdh;\n\t\tstruct ntfs_inode *ni;\n\t\tu32 next_id;\n\t\tu64 next_off;\n\t\t__le32 def_security_id;\n\t\tlong: 32;\n\t} security;\n\tstruct {\n\t\tstruct ntfs_index index_r;\n\t\tstruct ntfs_inode *ni;\n\t\tu64 max_size;\n\t} reparse;\n\tstruct {\n\t\tstruct ntfs_index index_o;\n\t\tstruct ntfs_inode *ni;\n\t} objid;\n\tstruct {\n\t\tstruct mutex mtx_lznt;\n\t\tstruct lznt *lznt;\n\t} compress;\n\tstruct ntfs_mount_options *options;\n\tstruct ratelimit_state msg_ratelimit;\n\tstruct proc_dir_entry *procdir;\n\tlong: 32;\n};\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tlong: 32;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\tlong: 32;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\tlong: 32;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_t drops1;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct tegra_drm_riscv_descriptor {\n\tu32 manifest_offset;\n\tu32 code_offset;\n\tu32 code_size;\n\tu32 data_offset;\n\tu32 data_size;\n};\n\nstruct tegra_drm_riscv {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct tegra_drm_riscv_descriptor bl_desc;\n\tstruct tegra_drm_riscv_descriptor os_desc;\n};\n\nstruct nvdec_config;\n\nstruct nvdec {\n\tstruct falcon falcon;\n\tvoid *regs;\n\tstruct tegra_drm_client client;\n\tstruct host1x_channel *channel;\n\tstruct device *dev;\n\tstruct clk_bulk_data clks[3];\n\tunsigned int num_clks;\n\tstruct reset_control *reset;\n\tconst struct nvdec_config *config;\n\tstruct tegra_drm_riscv riscv;\n\tphys_addr_t carveout_base;\n};\n\nstruct nvdec_config {\n\tconst char *firmware;\n\tunsigned int version;\n\tbool supports_sid;\n\tbool has_riscv;\n\tbool has_extra_clocks;\n};\n\nstruct nvec_msg {\n\tstruct list_head node;\n\tunsigned char data[34];\n\tshort unsigned int size;\n\tshort unsigned int pos;\n\tatomic_t used;\n};\n\nstruct nvec_chip {\n\tstruct device *dev;\n\tstruct gpio_desc *gpiod;\n\tint irq;\n\tu32 i2c_addr;\n\tvoid *base;\n\tstruct clk *i2c_clk;\n\tstruct reset_control *rst;\n\tstruct atomic_notifier_head notifier_list;\n\tstruct list_head rx_data;\n\tstruct list_head tx_data;\n\tstruct notifier_block nvec_status_notifier;\n\tstruct work_struct rx_work;\n\tstruct work_struct tx_work;\n\tstruct workqueue_struct *wq;\n\tstruct nvec_msg msg_pool[64];\n\tstruct nvec_msg *rx;\n\tstruct nvec_msg *tx;\n\tstruct nvec_msg tx_scratch;\n\tstruct completion ec_transfer;\n\tspinlock_t tx_lock;\n\tspinlock_t rx_lock;\n\tstruct mutex sync_write_mutex;\n\tstruct completion sync_write;\n\tu16 sync_write_pending;\n\tstruct nvec_msg *last_sync_msg;\n\tint state;\n};\n\nstruct nvec_keys {\n\tstruct input_dev *input;\n\tstruct notifier_block notifier;\n\tstruct nvec_chip *nvec;\n\tbool caps_lock;\n};\n\nstruct nvec_led {\n\tstruct led_classdev cdev;\n\tstruct nvec_chip *nvec;\n};\n\nstruct nvec_power {\n\tstruct notifier_block notifier;\n\tstruct delayed_work poller;\n\tstruct nvec_chip *nvec;\n\tint on;\n\tint bat_present;\n\tint bat_status;\n\tint bat_voltage_now;\n\tint bat_current_now;\n\tint bat_current_avg;\n\tint time_remain;\n\tint charge_full_design;\n\tint charge_last_full;\n\tint critical_capacity;\n\tint capacity_remain;\n\tint bat_temperature;\n\tint bat_cap;\n\tint bat_type_enum;\n\tchar bat_manu[30];\n\tchar bat_model[30];\n\tchar bat_type[30];\n};\n\nstruct nvec_ps2 {\n\tstruct serio *ser_dev;\n\tstruct notifier_block notifier;\n\tstruct nvec_chip *nvec;\n};\n\nstruct nvjpg_config;\n\nstruct nvjpg {\n\tstruct falcon falcon;\n\tvoid *regs;\n\tstruct tegra_drm_client client;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tconst struct nvjpg_config *config;\n};\n\nstruct nvjpg_config {\n\tconst char *firmware;\n\tunsigned int version;\n};\n\nstruct nvmem_cell_entry;\n\nstruct nvmem_cell {\n\tstruct nvmem_cell_entry *entry;\n\tconst char *id;\n\tint index;\n};\n\ntypedef int (*nvmem_cell_post_process_t)(void *, const char *, int, unsigned int, void *, size_t);\n\nstruct nvmem_cell_entry {\n\tconst char *name;\n\tint offset;\n\tsize_t raw_len;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n\tstruct device_node *np;\n\tstruct nvmem_device *nvmem;\n\tstruct list_head node;\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tsize_t raw_len;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n\tstruct device_node *np;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n};\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nstruct nvmem_keepout;\n\nstruct nvmem_layout;\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tbool add_legacy_fixed_of_cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool ignore_wp;\n\tstruct nvmem_layout *layout;\n\tstruct device_node *of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device {\n\tstruct module *owner;\n\tlong: 32;\n\tstruct device dev;\n\tstruct list_head node;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tstruct nvmem_layout *layout;\n\tvoid *priv;\n\tbool sysfs_cells_populated;\n\tlong: 32;\n};\n\nstruct nvmem_keepout {\n\tunsigned int start;\n\tunsigned int end;\n\tunsigned char value;\n};\n\nstruct nvmem_layout {\n\tstruct device dev;\n\tstruct nvmem_device *nvmem;\n\tint (*add_cells)(struct nvmem_layout *);\n};\n\nstruct nvmem_layout_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct nvmem_layout *);\n\tvoid (*remove)(struct nvmem_layout *);\n};\n\nstruct nvram_header {\n\tu32 magic;\n\tu32 len;\n\tu32 crc_ver_init;\n\tu32 config_refresh;\n\tu32 config_ncdl;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct ocelot_irq_work {\n\tstruct work_struct irq_work;\n\tstruct irq_desc *irq_desc;\n};\n\nstruct ocelot_pincfg_data {\n\tu8 pd_bit;\n\tu8 pu_bit;\n\tu8 drive_bits;\n\tu8 schmitt_bit;\n};\n\nstruct ocelot_match_data {\n\tstruct pinctrl_desc desc;\n\tstruct ocelot_pincfg_data pincfg_data;\n\tunsigned int n_alt_modes;\n};\n\nstruct ocelot_pin_caps {\n\tunsigned int pin;\n\tunsigned char functions[4];\n\tunsigned char a_functions[4];\n};\n\nstruct ocelot_pmx_func {\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct ocelot_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct gpio_chip gpio_chip;\n\tstruct regmap *map;\n\tstruct regmap *pincfg;\n\tstruct pinctrl_desc *desc;\n\tconst struct ocelot_pincfg_data *pincfg_data;\n\tstruct ocelot_pmx_func func[144];\n\tu8 stride;\n\tu8 altm_stride;\n\tstruct workqueue_struct *wq;\n};\n\nstruct ocotp_ctrl_reg {\n\tu32 bm_addr;\n\tu32 bm_busy;\n\tu32 bm_error;\n\tu32 bm_rel_shadows;\n};\n\nstruct ocotp_priv;\n\nstruct ocotp_params {\n\tunsigned int nregs;\n\tunsigned int bank_address_words;\n\tvoid (*set_timing)(struct ocotp_priv *);\n\tstruct ocotp_ctrl_reg ctrl;\n};\n\nstruct ocotp_priv {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tvoid *base;\n\tconst struct ocotp_params *params;\n\tstruct nvmem_config *config;\n};\n\nstruct od_dbs_tuners {\n\tunsigned int powersave_bias;\n};\n\nstruct od_ops {\n\tunsigned int (*powersave_bias_target)(struct cpufreq_policy *, unsigned int, unsigned int);\n};\n\nstruct policy_dbs_info {\n\tstruct cpufreq_policy *policy;\n\tstruct mutex update_mutex;\n\tu64 last_sample_time;\n\ts64 sample_delay_ns;\n\tatomic_t work_count;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\tstruct dbs_data *dbs_data;\n\tstruct list_head list;\n\tunsigned int rate_mult;\n\tunsigned int idle_periods;\n\tbool is_shared;\n\tbool work_in_progress;\n\tlong: 32;\n};\n\nstruct od_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int freq_lo;\n\tunsigned int freq_lo_delay_us;\n\tunsigned int freq_hi_delay_us;\n\tunsigned int sample_type: 1;\n};\n\nstruct of_bus {\n\tvoid (*count_cells)(const void *, int, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n};\n\nstruct of_bus___2 {\n\tconst char *name;\n\tconst char *addresses;\n\tint (*match)(struct device_node *);\n\tvoid (*count_cells)(struct device_node *, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n\tint flag_cells;\n\tunsigned int (*get_flags)(const __be32 *);\n};\n\nstruct of_changeset_entry {\n\tstruct list_head node;\n\tlong unsigned int action;\n\tstruct device_node *np;\n\tstruct property *prop;\n\tstruct property *old_prop;\n};\n\nstruct of_clk_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n\tstruct clk * (*get)(struct of_phandle_args *, void *);\n\tstruct clk_hw * (*get_hw)(struct of_phandle_args *, void *);\n\tvoid *data;\n};\n\nstruct of_cpu_method {\n\tconst char *method;\n\tconst struct smp_operations *ops;\n};\n\nstruct of_cpuidle_method {\n\tconst char *method;\n\tconst struct cpuidle_ops *ops;\n};\n\nstruct of_dev_auxdata {\n\tchar *compatible;\n\tresource_size_t phys_addr;\n\tchar *name;\n\tvoid *platform_data;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_dma {\n\tstruct list_head of_dma_controllers;\n\tstruct device_node *of_node;\n\tstruct dma_chan * (*of_dma_xlate)(struct of_phandle_args *, struct of_dma *);\n\tvoid * (*of_dma_route_allocate)(struct of_phandle_args *, struct of_dma *);\n\tstruct dma_router *dma_router;\n\tvoid *of_dma_data;\n};\n\nstruct of_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct of_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct device_node *local_node;\n};\n\nstruct of_genpd_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n\tgenpd_xlate_t xlate;\n\tvoid *data;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct of_imap_item {\n\tstruct of_phandle_args parent_args;\n\tu32 child_imap_count;\n\tu32 child_imap[16];\n};\n\nstruct of_imap_parser {\n\tstruct device_node *node;\n\tconst __be32 *imap;\n\tconst __be32 *imap_end;\n\tu32 parent_offset;\n};\n\ntypedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *);\n\nstruct of_intc_desc {\n\tstruct list_head list;\n\tof_irq_init_cb_t irq_init_cb;\n\tstruct device_node *dev;\n\tstruct device_node *interrupt_parent;\n};\n\nstruct of_pci_iommu_alias_info {\n\tstruct device *dev;\n\tstruct device_node *np;\n};\n\nstruct of_pci_range {\n\tunion {\n\t\tu64 pci_addr;\n\t\tu64 bus_addr;\n\t};\n\tu64 cpu_addr;\n\tu64 parent_bus_addr;\n\tu64 size;\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct of_pci_range_parser {\n\tstruct device_node *node;\n\tconst struct of_bus___2 *bus;\n\tconst __be32 *range;\n\tconst __be32 *end;\n\tint na;\n\tint ns;\n\tint pna;\n\tbool dma;\n};\n\nstruct of_phandle_iterator {\n\tconst char *cells_name;\n\tint cell_count;\n\tconst struct device_node *parent;\n\tconst __be32 *list_end;\n\tconst __be32 *phandle_end;\n\tconst __be32 *cur;\n\tuint32_t cur_count;\n\tphandle phandle;\n\tstruct device_node *node;\n};\n\nstruct of_reconfig_data {\n\tstruct device_node *dn;\n\tstruct property *prop;\n\tstruct property *old_prop;\n};\n\nstruct of_regulator_match {\n\tconst char *name;\n\tvoid *driver_data;\n\tstruct regulator_init_data *init_data;\n\tstruct device_node *of_node;\n\tconst struct regulator_desc *desc;\n};\n\nstruct of_rename_gpio {\n\tconst char *con_id;\n\tconst char *legacy_id;\n\tconst char *compatible;\n};\n\nstruct of_serial_info {\n\tstruct clk *clk;\n\tstruct clk *bus_clk;\n\tstruct reset_control *rst;\n\tint type;\n\tint line;\n\tstruct notifier_block clk_notifier;\n};\n\nstruct of_timer_base {\n\tvoid *base;\n\tconst char *name;\n\tint index;\n};\n\nstruct of_timer_clk {\n\tstruct clk *clk;\n\tconst char *name;\n\tint index;\n\tlong unsigned int rate;\n\tlong unsigned int period;\n};\n\nstruct of_timer_irq {\n\tint irq;\n\tint index;\n\tconst char *name;\n\tlong unsigned int flags;\n\tirq_handler_t handler;\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nunion offset_union {\n\tlong unsigned int un;\n\tlong int sn;\n};\n\nstruct ohci_at91_priv {\n\tstruct clk *iclk;\n\tstruct clk *fclk;\n\tstruct clk *hclk;\n\tbool clocked;\n\tbool wakeup;\n\tstruct regmap *sfr_regmap;\n\tu32 suspend_smc_id;\n};\n\nstruct ohci_driver_overrides {\n\tconst char *product_desc;\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n};\n\nstruct ohci_hcca {\n\t__hc32 int_table[32];\n\t__hc32 frame_no;\n\t__hc32 done_head;\n\tu8 reserved_for_hc[116];\n\tu8 what[4];\n};\n\nstruct ohci_regs;\n\nstruct ohci_hcd {\n\tspinlock_t lock;\n\tstruct ohci_regs *regs;\n\tstruct ohci_hcca *hcca;\n\tdma_addr_t hcca_dma;\n\tstruct ed *ed_rm_list;\n\tstruct ed *ed_bulktail;\n\tstruct ed *ed_controltail;\n\tstruct ed *periodic[32];\n\tvoid (*start_hnp)(struct ohci_hcd *);\n\tstruct dma_pool *td_cache;\n\tstruct dma_pool *ed_cache;\n\tstruct td *td_hash[64];\n\tstruct td *dl_start;\n\tstruct td *dl_end;\n\tstruct list_head pending;\n\tstruct list_head eds_in_use;\n\tenum ohci_rh_state rh_state;\n\tint num_ports;\n\tint load[32];\n\tu32 hc_control;\n\tlong unsigned int next_statechange;\n\tu32 fminterval;\n\tunsigned int autostop: 1;\n\tunsigned int working: 1;\n\tunsigned int restart_work: 1;\n\tlong unsigned int flags;\n\tunsigned int prev_frame_no;\n\tunsigned int wdh_cnt;\n\tunsigned int prev_wdh_cnt;\n\tu32 prev_donehead;\n\tstruct timer_list io_watchdog;\n\tstruct work_struct nec_work;\n\tstruct dentry *debug_dir;\n\tlong: 32;\n\tlong unsigned int priv[0];\n};\n\nstruct ohci_hcd_omap_platform_data {\n\tenum usbhs_omap_port_mode port_mode[3];\n\tunsigned int es2_compatibility: 1;\n};\n\nstruct ohci_platform_priv {\n\tstruct clk *clks[4];\n\tstruct reset_control *resets;\n};\n\nstruct ohci_roothub_regs {\n\t__hc32 a;\n\t__hc32 b;\n\t__hc32 status;\n\t__hc32 portstatus[15];\n};\n\nstruct ohci_regs {\n\t__hc32 revision;\n\t__hc32 control;\n\t__hc32 cmdstatus;\n\t__hc32 intrstatus;\n\t__hc32 intrenable;\n\t__hc32 intrdisable;\n\t__hc32 hcca;\n\t__hc32 ed_periodcurrent;\n\t__hc32 ed_controlhead;\n\t__hc32 ed_controlcurrent;\n\t__hc32 ed_bulkhead;\n\t__hc32 ed_bulkcurrent;\n\t__hc32 donehead;\n\t__hc32 fminterval;\n\t__hc32 fmremaining;\n\t__hc32 fmnumber;\n\t__hc32 periodicstart;\n\t__hc32 lsthresh;\n\tstruct ohci_roothub_regs roothub;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tlong: 32;\n};\n\nstruct old_sigaction {\n\t__sighandler_t sa_handler;\n\told_sigset_t sa_mask;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct old_timex32 {\n\tu32 modes;\n\ts32 offset;\n\ts32 freq;\n\ts32 maxerror;\n\ts32 esterror;\n\ts32 status;\n\ts32 constant;\n\ts32 precision;\n\ts32 tolerance;\n\tstruct old_timeval32 time;\n\ts32 tick;\n\ts32 ppsfreq;\n\ts32 jitter;\n\ts32 shift;\n\ts32 stabil;\n\ts32 jitcnt;\n\ts32 calcnt;\n\ts32 errcnt;\n\ts32 stbcnt;\n\ts32 tai;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct old_utimbuf32 {\n\told_time32_t actime;\n\told_time32_t modtime;\n};\n\nstruct omap2_mcspi_regs {\n\tu32 modulctrl;\n\tu32 wakeupenable;\n\tstruct list_head cs;\n};\n\nstruct omap2_mcspi_dma;\n\nstruct omap2_mcspi {\n\tstruct completion txdone;\n\tstruct spi_controller *ctlr;\n\tvoid *base;\n\tlong unsigned int phys;\n\tstruct omap2_mcspi_dma *dma_channels;\n\tstruct device *dev;\n\tstruct omap2_mcspi_regs ctx;\n\tstruct clk *ref_clk;\n\tint fifo_depth;\n\tbool target_aborted;\n\tunsigned int pin_dir: 1;\n\tsize_t max_xfer_len;\n\tu32 ref_clk_hz;\n\tbool use_multi_mode;\n\tbool last_msg_kept_cs;\n};\n\nstruct omap2_mcspi_cs {\n\tvoid *base;\n\tlong unsigned int phys;\n\tint word_len;\n\tu16 mode;\n\tstruct list_head node;\n\tu32 chconf0;\n\tu32 chctrl0;\n};\n\nstruct omap2_mcspi_device_config {\n\tunsigned int turbo_mode: 1;\n};\n\nstruct omap2_mcspi_dma {\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tstruct completion dma_tx_completion;\n\tstruct completion dma_rx_completion;\n\tchar dma_rx_ch_name[14];\n\tchar dma_tx_ch_name[14];\n};\n\nstruct omap2_mcspi_platform_config {\n\tshort unsigned int num_cs;\n\tunsigned int regs_offset;\n\tunsigned int pin_dir: 1;\n\tsize_t max_xfer_len;\n};\n\nstruct omap2_oscillator {\n\tu32 startup_time;\n\tu32 shutdown_time;\n};\n\nstruct omap2_sms_regs {\n\tu32 sms_sysconfig;\n};\n\nstruct omap3_cm_regs {\n\tu32 iva2_cm_clksel1;\n\tu32 iva2_cm_clksel2;\n\tu32 cm_sysconfig;\n\tu32 sgx_cm_clksel;\n\tu32 dss_cm_clksel;\n\tu32 cam_cm_clksel;\n\tu32 per_cm_clksel;\n\tu32 emu_cm_clksel;\n\tu32 emu_cm_clkstctrl;\n\tu32 pll_cm_autoidle;\n\tu32 pll_cm_autoidle2;\n\tu32 pll_cm_clksel4;\n\tu32 pll_cm_clksel5;\n\tu32 pll_cm_clken2;\n\tu32 cm_polctrl;\n\tu32 iva2_cm_fclken;\n\tu32 iva2_cm_clken_pll;\n\tu32 core_cm_fclken1;\n\tu32 core_cm_fclken3;\n\tu32 sgx_cm_fclken;\n\tu32 wkup_cm_fclken;\n\tu32 dss_cm_fclken;\n\tu32 cam_cm_fclken;\n\tu32 per_cm_fclken;\n\tu32 usbhost_cm_fclken;\n\tu32 core_cm_iclken1;\n\tu32 core_cm_iclken2;\n\tu32 core_cm_iclken3;\n\tu32 sgx_cm_iclken;\n\tu32 wkup_cm_iclken;\n\tu32 dss_cm_iclken;\n\tu32 cam_cm_iclken;\n\tu32 per_cm_iclken;\n\tu32 usbhost_cm_iclken;\n\tu32 iva2_cm_autoidle2;\n\tu32 mpu_cm_autoidle2;\n\tu32 iva2_cm_clkstctrl;\n\tu32 mpu_cm_clkstctrl;\n\tu32 core_cm_clkstctrl;\n\tu32 sgx_cm_clkstctrl;\n\tu32 dss_cm_clkstctrl;\n\tu32 cam_cm_clkstctrl;\n\tu32 per_cm_clkstctrl;\n\tu32 neon_cm_clkstctrl;\n\tu32 usbhost_cm_clkstctrl;\n\tu32 core_cm_autoidle1;\n\tu32 core_cm_autoidle2;\n\tu32 core_cm_autoidle3;\n\tu32 wkup_cm_autoidle;\n\tu32 dss_cm_autoidle;\n\tu32 cam_cm_autoidle;\n\tu32 per_cm_autoidle;\n\tu32 usbhost_cm_autoidle;\n\tu32 sgx_cm_sleepdep;\n\tu32 dss_cm_sleepdep;\n\tu32 cam_cm_sleepdep;\n\tu32 per_cm_sleepdep;\n\tu32 usbhost_cm_sleepdep;\n\tu32 cm_clkout_ctrl;\n};\n\nstruct omap3_control_regs {\n\tu32 sysconfig;\n\tu32 devconf0;\n\tu32 mem_dftrw0;\n\tu32 mem_dftrw1;\n\tu32 msuspendmux_0;\n\tu32 msuspendmux_1;\n\tu32 msuspendmux_2;\n\tu32 msuspendmux_3;\n\tu32 msuspendmux_4;\n\tu32 msuspendmux_5;\n\tu32 sec_ctrl;\n\tu32 devconf1;\n\tu32 csirxfe;\n\tu32 iva2_bootaddr;\n\tu32 iva2_bootmod;\n\tu32 wkup_ctrl;\n\tu32 debobs_0;\n\tu32 debobs_1;\n\tu32 debobs_2;\n\tu32 debobs_3;\n\tu32 debobs_4;\n\tu32 debobs_5;\n\tu32 debobs_6;\n\tu32 debobs_7;\n\tu32 debobs_8;\n\tu32 prog_io0;\n\tu32 prog_io1;\n\tu32 dss_dpll_spreading;\n\tu32 core_dpll_spreading;\n\tu32 per_dpll_spreading;\n\tu32 usbhost_dpll_spreading;\n\tu32 pbias_lite;\n\tu32 temp_sensor;\n\tu32 sramldo4;\n\tu32 sramldo5;\n\tu32 csi;\n\tu32 padconf_sys_nirq;\n};\n\nstruct omap3_dpll5_settings {\n\tunsigned int rate;\n\tunsigned int m;\n\tunsigned int n;\n};\n\nstruct omap3_idle_statedata {\n\tu8 mpu_state;\n\tu8 core_state;\n\tu8 per_min_state;\n\tu8 flags;\n};\n\nstruct omap3_l3 {\n\tstruct device *dev;\n\tstruct clk *ick;\n\tvoid *rt;\n\tint debug_irq;\n\tint app_irq;\n\tunsigned int inband: 1;\n};\n\nstruct omap3_scratchpad {\n\tu32 boot_config_ptr;\n\tu32 public_restore_ptr;\n\tu32 secure_ram_restore_ptr;\n\tu32 sdrc_module_semaphore;\n\tu32 prcm_block_offset;\n\tu32 sdrc_block_offset;\n};\n\nstruct omap3_scratchpad_prcm_block {\n\tu32 prm_contents[2];\n\tu32 cm_contents[11];\n\tu32 prcm_block_size;\n};\n\nstruct omap3_scratchpad_sdrc_block {\n\tu16 sysconfig;\n\tu16 cs_cfg;\n\tu16 sharing;\n\tu16 err_type;\n\tu32 dll_a_ctrl;\n\tu32 dll_b_ctrl;\n\tu32 power;\n\tu32 cs_0;\n\tu32 mcfg_0;\n\tu16 mr_0;\n\tu16 emr_1_0;\n\tu16 emr_2_0;\n\tu16 emr_3_0;\n\tu32 actim_ctrla_0;\n\tu32 actim_ctrlb_0;\n\tu32 rfr_ctrl_0;\n\tu32 cs_1;\n\tu32 mcfg_1;\n\tu16 mr_1;\n\tu16 emr_1_1;\n\tu16 emr_2_1;\n\tu16 emr_3_1;\n\tu32 actim_ctrla_1;\n\tu32 actim_ctrlb_1;\n\tu32 rfr_ctrl_1;\n\tu16 dcdl_1_ctrl;\n\tu16 dcdl_2_ctrl;\n\tu32 flags;\n\tu32 block_size;\n};\n\nstruct omap3_vc_timings {\n\tu32 voltsetup1;\n\tu32 voltsetup2;\n};\n\nstruct voltagedomain;\n\nstruct omap3_vc {\n\tstruct voltagedomain *vd;\n\tu32 voltctrl;\n\tu32 voltsetup1;\n\tu32 voltsetup2;\n\tstruct omap3_vc_timings timings[2];\n};\n\nstruct omap3_vp {\n\tu32 tranxdone_status;\n};\n\nstruct omap4_cpu_pm_info {\n\tstruct powerdomain *pwrdm;\n\tvoid *scu_sar_addr;\n\tvoid *wkup_sar_addr;\n\tvoid *l2x0_sar_addr;\n};\n\nunion omap4_timeout {\n\tu32 cycles;\n\tktime_t start;\n};\n\nstruct omap4_vp {\n\tu32 irqstatus_mpu;\n\tu32 tranxdone_status;\n};\n\nstruct omap8250_dma_params {\n\tu32 rx_size;\n\tu8 rx_trigger;\n\tu8 tx_trigger;\n};\n\nstruct omap8250_platdata {\n\tstruct omap8250_dma_params *dma_params;\n\tu8 habit;\n};\n\nstruct omap8250_priv {\n\tvoid *membase;\n\tint line;\n\tu8 habit;\n\tu8 mdr1;\n\tu8 mdr3;\n\tu8 efr;\n\tu8 scr;\n\tu8 wer;\n\tu8 xon;\n\tu8 xoff;\n\tu8 delayed_restore;\n\tu16 quot;\n\tu8 tx_trigger;\n\tu8 rx_trigger;\n\tatomic_t active;\n\tbool is_suspending;\n\tint wakeirq;\n\tu32 latency;\n\tu32 calc_latency;\n\tstruct pm_qos_request pm_qos_request;\n\tstruct work_struct qos_work;\n\tstruct uart_8250_dma omap8250_dma;\n\tspinlock_t rx_dma_lock;\n\tbool rx_dma_broken;\n\tbool throttled;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pinctrl_wakeup;\n};\n\nstruct omap_dma_reg;\n\nstruct omap_desc;\n\nstruct omap_chan {\n\tstruct virt_dma_chan vc;\n\tvoid *channel_base;\n\tconst struct omap_dma_reg *reg_map;\n\tuint32_t ccr;\n\tstruct dma_slave_config cfg;\n\tunsigned int dma_sig;\n\tbool cyclic;\n\tbool paused;\n\tbool running;\n\tint dma_ch;\n\tstruct omap_desc *desc;\n\tunsigned int sgidx;\n};\n\nstruct omap_clkctrl_bit_data {\n\tu8 bit;\n\tu8 type;\n\tconst char * const *parents;\n\tconst void *data;\n};\n\nstruct omap_clkctrl_clk {\n\tstruct clk_hw *clk;\n\tu16 reg_offset;\n\tint bit_offset;\n\tstruct list_head node;\n};\n\nstruct omap_clkctrl_reg_data;\n\nstruct omap_clkctrl_data {\n\tu32 addr;\n\tconst struct omap_clkctrl_reg_data *regs;\n};\n\nstruct omap_clkctrl_div_data {\n\tconst int *dividers;\n\tint max_div;\n\tu32 flags;\n};\n\nstruct omap_clkctrl_provider {\n\tvoid *base;\n\tstruct list_head clocks;\n\tchar *clkdm_name;\n};\n\nstruct omap_clkctrl_reg_data {\n\tu16 offset;\n\tconst struct omap_clkctrl_bit_data *bit_data;\n\tu16 flags;\n\tconst char *parent;\n\tconst char *clkdm_name;\n};\n\nstruct omap_control_phy {\n\tstruct device *dev;\n\tu32 *otghs_control;\n\tu32 *power;\n\tu32 *power_aux;\n\tu32 *pcie_pcs;\n\tstruct clk *sys_clk;\n\tenum omap_control_phy_type type;\n};\n\nstruct omap_type2_desc;\n\nstruct omap_sg {\n\tdma_addr_t addr;\n\tuint32_t en;\n\tuint32_t fn;\n\tint32_t fi;\n\tint16_t ei;\n\tstruct omap_type2_desc *t2_desc;\n\tdma_addr_t t2_desc_paddr;\n};\n\nstruct omap_desc {\n\tstruct virt_dma_desc vd;\n\tbool using_ll;\n\tenum dma_transfer_direction dir;\n\tdma_addr_t dev_addr;\n\tbool polled;\n\tint32_t fi;\n\tint16_t ei;\n\tuint8_t es;\n\tuint32_t ccr;\n\tuint16_t clnk_ctrl;\n\tuint16_t cicr;\n\tuint32_t csdp;\n\tunsigned int sglen;\n\tstruct omap_sg sg[0];\n};\n\nstruct omap_hwmod;\n\nstruct omap_device {\n\tstruct platform_device *pdev;\n\tstruct omap_hwmod **hwmods;\n\tlong unsigned int _driver_status;\n\tu8 hwmods_cnt;\n\tu8 _state;\n\tu8 flags;\n};\n\nstruct omap_die_id {\n\tu32 id_0;\n\tu32 id_1;\n\tu32 id_2;\n\tu32 id_3;\n};\n\nstruct omap_dm_timer_ops {\n\tstruct omap_dm_timer * (*request_by_node)(struct device_node *);\n\tstruct omap_dm_timer * (*request_specific)(int);\n\tstruct omap_dm_timer * (*request)(void);\n\tint (*free)(struct omap_dm_timer *);\n\tvoid (*enable)(struct omap_dm_timer *);\n\tvoid (*disable)(struct omap_dm_timer *);\n\tint (*get_irq)(struct omap_dm_timer *);\n\tint (*set_int_enable)(struct omap_dm_timer *, unsigned int);\n\tint (*set_int_disable)(struct omap_dm_timer *, u32);\n\tstruct clk * (*get_fclk)(struct omap_dm_timer *);\n\tint (*start)(struct omap_dm_timer *);\n\tint (*stop)(struct omap_dm_timer *);\n\tint (*set_source)(struct omap_dm_timer *, int);\n\tint (*set_load)(struct omap_dm_timer *, unsigned int);\n\tint (*set_match)(struct omap_dm_timer *, int, unsigned int);\n\tint (*set_pwm)(struct omap_dm_timer *, int, int, int, int);\n\tint (*get_pwm_status)(struct omap_dm_timer *);\n\tint (*set_cap)(struct omap_dm_timer *, int, bool);\n\tint (*get_cap_status)(struct omap_dm_timer *);\n\tint (*set_prescaler)(struct omap_dm_timer *, int);\n\tunsigned int (*read_counter)(struct omap_dm_timer *);\n\tunsigned int (*read_cap)(struct omap_dm_timer *, bool);\n\tint (*write_counter)(struct omap_dm_timer *, unsigned int);\n\tunsigned int (*read_status)(struct omap_dm_timer *);\n\tint (*write_status)(struct omap_dm_timer *, unsigned int);\n};\n\nstruct omap_dma_config {\n\tint lch_end;\n\tunsigned int rw_priority: 1;\n\tunsigned int needs_busy_check: 1;\n\tunsigned int may_lose_context: 1;\n\tunsigned int needs_lch_clear: 1;\n};\n\nstruct omap_dma_context {\n\tu32 irqenable_l0;\n\tu32 irqenable_l1;\n\tu32 ocp_sysconfig;\n\tu32 gcr;\n};\n\nstruct omap_dma_dev_attr {\n\tu32 dev_caps;\n\tu16 lch_count;\n\tu16 chan_count;\n};\n\nstruct omap_dma_reg {\n\tu16 offset;\n\tu8 stride;\n\tu8 type;\n};\n\nstruct omap_system_dma_plat_info;\n\nstruct omap_dmadev {\n\tstruct dma_device ddev;\n\tspinlock_t lock;\n\tvoid *base;\n\tconst struct omap_dma_reg *reg_map;\n\tstruct omap_system_dma_plat_info *plat;\n\tconst struct omap_dma_config *cfg;\n\tstruct notifier_block nb;\n\tstruct omap_dma_context context;\n\tint lch_count;\n\tlong unsigned int lch_bitmap[1];\n\tstruct mutex lch_lock;\n\tbool legacy;\n\tbool ll123_supported;\n\tstruct dma_pool *desc_pool;\n\tunsigned int dma_requests;\n\tspinlock_t irq_lock;\n\tuint32_t irq_enable_mask;\n\tstruct omap_chan **lch_map;\n};\n\nstruct omap_domain_base {\n\tu32 pa;\n\tvoid *va;\n\ts16 offset;\n};\n\nstruct omap_dss_dispc_dev_attr {\n\tu8 manager_count;\n\tbool has_framedonetv_irq;\n};\n\nstruct omap_gpio_platform_data {\n\tint bank_type;\n\tint bank_width;\n\tint bank_stride;\n\tbool dbck_flag;\n\tbool loses_context;\n\tbool is_mpuio;\n\tu32 non_wakeup_gpios;\n\tconst struct omap_gpio_reg_offs *regs;\n\tint (*get_context_loss_count)(struct device *);\n};\n\nstruct omap_gpio_reg_offs {\n\tu16 revision;\n\tu16 sysconfig;\n\tu16 direction;\n\tu16 datain;\n\tu16 dataout;\n\tu16 set_dataout;\n\tu16 clr_dataout;\n\tu16 irqstatus;\n\tu16 irqstatus2;\n\tu16 irqstatus_raw0;\n\tu16 irqstatus_raw1;\n\tu16 irqenable;\n\tu16 irqenable2;\n\tu16 set_irqenable;\n\tu16 clr_irqenable;\n\tu16 debounce;\n\tu16 debounce_en;\n\tu16 ctrl;\n\tu16 wkup_en;\n\tu16 leveldetect0;\n\tu16 leveldetect1;\n\tu16 risingdetect;\n\tu16 fallingdetect;\n\tu16 irqctrl;\n\tu16 edgectrl1;\n\tu16 edgectrl2;\n\tu16 pinctrl;\n\tbool irqenable_inv;\n};\n\nstruct omap_hcd {\n\tstruct usb_phy *phy[3];\n\tint nports;\n};\n\nstruct omap_hsmmc_dev_attr {\n\tu8 flags;\n};\n\nstruct omap_hsmmc_next {\n\tunsigned int dma_len;\n\ts32 cookie;\n};\n\nstruct omap_hsmmc_platform_data;\n\nstruct omap_hsmmc_host {\n\tstruct device *dev;\n\tstruct mmc_host *mmc;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct clk *fclk;\n\tstruct clk *dbclk;\n\tstruct regulator *pbias;\n\tbool pbias_enabled;\n\tvoid *base;\n\tbool vqmmc_enabled;\n\tresource_size_t mapbase;\n\tspinlock_t irq_lock;\n\tunsigned int dma_len;\n\tunsigned int dma_sg_idx;\n\tunsigned char bus_mode;\n\tunsigned char power_mode;\n\tint suspended;\n\tu32 con;\n\tu32 hctl;\n\tu32 sysctl;\n\tu32 capa;\n\tint irq;\n\tint wake_irq;\n\tint use_dma;\n\tint dma_ch;\n\tstruct dma_chan *tx_chan;\n\tstruct dma_chan *rx_chan;\n\tint response_busy;\n\tint context_loss;\n\tint reqs_blocked;\n\tint req_in_progress;\n\tlong unsigned int clk_rate;\n\tunsigned int flags;\n\tstruct omap_hsmmc_next next_data;\n\tstruct omap_hsmmc_platform_data *pdata;\n};\n\nstruct omap_hsmmc_platform_data {\n\tstruct device *dev;\n\tunsigned int max_freq;\n\tu8 controller_flags;\n\tu16 reg_offset;\n\tu32 caps;\n\tu32 pm_caps;\n\tunsigned int nonremovable: 1;\n\tunsigned int no_regulator_off_init: 1;\n\tunsigned int features;\n\tchar *version;\n\tconst char *name;\n\tu32 ocr_mask;\n};\n\nstruct omap_hwmod_omap2_prcm {\n\ts16 module_offs;\n\tu8 idlest_reg_id;\n\tu8 idlest_idle_bit;\n};\n\nstruct omap_hwmod_omap4_prcm {\n\tu16 clkctrl_offs;\n\tu16 rstctrl_offs;\n\tu16 rstst_offs;\n\tu16 context_offs;\n\tu32 lostcontext_mask;\n\tu8 submodule_wkdep_bit;\n\tu8 modulemode;\n\tu8 flags;\n\tint context_lost_counter;\n};\n\nstruct omap_hwmod_class;\n\nstruct omap_hwmod_rst_info;\n\nstruct omap_hwmod_opt_clk;\n\nstruct omap_hwmod_ocp_if;\n\nstruct omap_hwmod {\n\tconst char *name;\n\tstruct omap_hwmod_class *class;\n\tstruct omap_device *od;\n\tstruct omap_hwmod_rst_info *rst_lines;\n\tunion {\n\t\tstruct omap_hwmod_omap2_prcm omap2;\n\t\tstruct omap_hwmod_omap4_prcm omap4;\n\t} prcm;\n\tconst char *main_clk;\n\tstruct clk *_clk;\n\tstruct omap_hwmod_opt_clk *opt_clks;\n\tconst char *clkdm_name;\n\tstruct clockdomain *clkdm;\n\tstruct list_head slave_ports;\n\tvoid *dev_attr;\n\tu32 _sysc_cache;\n\tvoid *_mpu_rt_va;\n\tspinlock_t _lock;\n\tstruct lock_class_key hwmod_key;\n\tstruct list_head node;\n\tstruct omap_hwmod_ocp_if *_mpu_port;\n\tu32 flags;\n\tu8 mpu_rt_idx;\n\tu8 response_lat;\n\tu8 rst_lines_cnt;\n\tu8 opt_clks_cnt;\n\tu8 slaves_cnt;\n\tu8 hwmods_cnt;\n\tu8 _int_flags;\n\tu8 _state;\n\tu8 _postsetup_state;\n\tstruct omap_hwmod *parent_hwmod;\n};\n\nstruct omap_hwmod_class_sysconfig;\n\nstruct omap_hwmod_class {\n\tconst char *name;\n\tstruct omap_hwmod_class_sysconfig *sysc;\n\tint (*pre_shutdown)(struct omap_hwmod *);\n\tint (*reset)(struct omap_hwmod *);\n\tvoid (*lock)(struct omap_hwmod *);\n\tvoid (*unlock)(struct omap_hwmod *);\n};\n\nstruct sysc_regbits;\n\nstruct omap_hwmod_class_sysconfig {\n\ts32 rev_offs;\n\ts32 sysc_offs;\n\ts32 syss_offs;\n\tu16 sysc_flags;\n\tstruct sysc_regbits *sysc_fields;\n\tu8 srst_udelay;\n\tu8 idlemodes;\n};\n\nstruct omap_hwmod_addr_space;\n\nstruct omap_hwmod_omap2_firewall {\n\tu8 l3_perm_bit;\n\tu8 l4_fw_region;\n\tu8 l4_prot_group;\n\tu8 flags;\n};\n\nstruct omap_hwmod_ocp_if {\n\tstruct omap_hwmod *master;\n\tstruct omap_hwmod *slave;\n\tstruct omap_hwmod_addr_space *addr;\n\tconst char *clk;\n\tstruct clk *_clk;\n\tstruct list_head node;\n\tunion {\n\t\tstruct omap_hwmod_omap2_firewall omap2;\n\t} fw;\n\tu8 width;\n\tu8 user;\n\tu8 flags;\n\tu8 _int_flags;\n};\n\nstruct omap_hwmod_opt_clk {\n\tconst char *role;\n\tconst char *clk;\n\tstruct clk *_clk;\n};\n\nstruct omap_hwmod_reset {\n\tconst char *match;\n\tint len;\n\tint (*reset)(struct omap_hwmod *);\n};\n\nstruct omap_hwmod_rst_info {\n\tconst char *name;\n\tu8 rst_shift;\n\tu8 st_shift;\n};\n\nstruct omap_hwmod_soc_ops {\n\tvoid (*enable_module)(struct omap_hwmod *);\n\tint (*disable_module)(struct omap_hwmod *);\n\tint (*wait_target_ready)(struct omap_hwmod *);\n\tint (*assert_hardreset)(struct omap_hwmod *, struct omap_hwmod_rst_info *);\n\tint (*deassert_hardreset)(struct omap_hwmod *, struct omap_hwmod_rst_info *);\n\tint (*is_hardreset_asserted)(struct omap_hwmod *, struct omap_hwmod_rst_info *);\n\tint (*init_clkdm)(struct omap_hwmod *);\n\tvoid (*update_context_lost)(struct omap_hwmod *);\n\tint (*get_context_lost)(struct omap_hwmod *);\n\tint (*disable_direct_prcm)(struct omap_hwmod *);\n\tu32 (*xlate_clkctrl)(struct omap_hwmod *);\n};\n\nstruct omap_i2c_bus_platform_data {\n\tu32 clkrate;\n\tu32 rev;\n\tu32 flags;\n\tvoid (*set_mpu_wkup_lat)(struct device *, long int);\n};\n\nstruct omap_i2c_dev {\n\tstruct device *dev;\n\tvoid *base;\n\tint irq;\n\tint reg_shift;\n\tstruct completion cmd_complete;\n\tstruct resource *ioarea;\n\tu32 latency;\n\tvoid (*set_mpu_wkup_lat)(struct device *, long int);\n\tu32 speed;\n\tu32 flags;\n\tu16 scheme;\n\tu16 cmd_err;\n\tu8 *buf;\n\tu8 *regs;\n\tsize_t buf_len;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tu8 threshold;\n\tu8 fifo_size;\n\tu32 rev;\n\tunsigned int b_hw: 1;\n\tunsigned int bb_valid: 1;\n\tunsigned int receiver: 1;\n\tu16 iestate;\n\tu16 pscstate;\n\tu16 scllstate;\n\tu16 sclhstate;\n\tu16 syscstate;\n\tu16 westate;\n\tu16 errata;\n\tstruct mux_state *mux_state;\n\tlong: 32;\n};\n\nstruct omap_id {\n\tu16 hawkeye;\n\tu8 dev;\n\tu32 type;\n};\n\nstruct omap_intc_regs {\n\tu32 sysconfig;\n\tu32 protection;\n\tu32 idle;\n\tu32 threshold;\n\tu32 ilr[128];\n\tu32 mir[4];\n};\n\nstruct omap_iommu {\n\tconst char *name;\n\tvoid *regbase;\n\tstruct regmap *syscfg;\n\tstruct device *dev;\n\tstruct iommu_domain *domain;\n\tstruct dentry *debug_dir;\n\tspinlock_t iommu_lock;\n\tu32 *iopgd;\n\tspinlock_t page_table_lock;\n\tdma_addr_t pd_dma;\n\tint nr_tlb_entries;\n\tvoid *ctx;\n\tstruct cr_regs *cr_ctx;\n\tu32 num_cr_ctx;\n\tint has_bus_err_back;\n\tu32 id;\n\tstruct iommu_device iommu;\n\tbool has_iommu_driver;\n\tu8 pwrst;\n};\n\nstruct omap_iommu_arch_data {\n\tstruct omap_iommu *iommu_dev;\n};\n\nstruct omap_iommu_device {\n\tu32 *pgtable;\n\tstruct omap_iommu *iommu_dev;\n};\n\nstruct omap_iommu_domain {\n\tu32 num_iommus;\n\tstruct omap_iommu_device *iommus;\n\tstruct device *dev;\n\tspinlock_t lock;\n\tstruct iommu_domain domain;\n};\n\nstruct omap_l3 {\n\tstruct device *dev;\n\tvoid *l3_base[3];\n\tstruct l3_flagmux_data **l3_flagmux;\n\tint num_modules;\n\tstruct l3_masters_data *l3_masters;\n\tint num_masters;\n\tu32 mst_addr_mask;\n\tint debug_irq;\n\tint app_irq;\n};\n\nstruct omap_mbox_fifo {\n\tlong unsigned int msg;\n\tlong unsigned int fifo_stat;\n\tlong unsigned int msg_stat;\n\tlong unsigned int irqenable;\n\tlong unsigned int irqstatus;\n\tlong unsigned int irqdisable;\n\tu32 intr_bit;\n};\n\nstruct omap_mbox_device;\n\nstruct omap_mbox {\n\tconst char *name;\n\tint irq;\n\tstruct omap_mbox_device *parent;\n\tstruct omap_mbox_fifo tx_fifo;\n\tstruct omap_mbox_fifo rx_fifo;\n\tu32 intr_type;\n\tstruct mbox_chan *chan;\n\tbool send_no_irq;\n};\n\nstruct omap_mbox_match_data;\n\nstruct omap_mbox_device {\n\tstruct device *dev;\n\tstruct mutex cfg_lock;\n\tvoid *mbox_base;\n\tu32 *irq_ctx;\n\tu32 num_users;\n\tu32 num_fifos;\n\tu32 intr_type;\n\tconst struct omap_mbox_match_data *mbox_data;\n};\n\nstruct omap_mbox_match_data {\n\tu32 intr_type;\n\tbool is_exclusive;\n};\n\nstruct omap_mmc_of_data {\n\tu32 reg_offset;\n\tu8 controller_flags;\n};\n\nstruct omap_mmc_slot_data {\n\tu8 wires;\n\tu32 caps;\n\tu32 pm_caps;\n\tunsigned int nomux: 1;\n\tunsigned int cover: 1;\n\tunsigned int internal_clock: 1;\n\tunsigned int nonremovable: 1;\n\tunsigned int power_saving: 1;\n\tunsigned int no_off: 1;\n\tunsigned int no_regulator_off_init: 1;\n\tunsigned int vcc_aux_disable_is_sleep: 1;\n\tunsigned int features;\n\tint switch_pin;\n\tint gpio_wp;\n\tint (*set_bus_mode)(struct device *, int, int);\n\tint (*set_power)(struct device *, int, int, int);\n\tint (*get_ro)(struct device *, int);\n\tvoid (*remux)(struct device *, int, int);\n\tvoid (*before_set_reg)(struct device *, int, int, int);\n\tvoid (*after_set_reg)(struct device *, int, int, int);\n\tvoid (*init_card)(struct mmc_card *);\n\tint (*get_cover_state)(struct device *, int);\n\tconst char *name;\n\tu32 ocr_mask;\n\tint (*card_detect)(struct device *, int);\n\tunsigned int ban_openended: 1;\n};\n\nstruct omap_mmc_platform_data {\n\tstruct device *dev;\n\tunsigned int nr_slots: 2;\n\tunsigned int max_freq;\n\tint (*init)(struct device *);\n\tvoid (*cleanup)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*get_context_loss_count)(struct device *);\n\tu8 controller_flags;\n\tu16 reg_offset;\n\tstruct omap_mmc_slot_data slots[2];\n};\n\nstruct omap_nand_info {\n\tstruct nand_chip nand;\n\tstruct platform_device *pdev;\n\tint gpmc_cs;\n\tbool dev_ready;\n\tenum nand_io xfer_type;\n\tenum omap_ecc ecc_opt;\n\tstruct device_node *elm_of_node;\n\tlong unsigned int phys_base;\n\tstruct completion comp;\n\tstruct dma_chan *dma;\n\tint gpmc_irq_fifo;\n\tint gpmc_irq_count;\n\tenum {\n\t\tOMAP_NAND_IO_READ = 0,\n\t\tOMAP_NAND_IO_WRITE = 1,\n\t} iomode;\n\tu_char *buf;\n\tint buf_len;\n\tvoid *fifo;\n\tstruct gpmc_nand_regs reg;\n\tstruct gpmc_nand_ops *ops;\n\tbool flash_bbt;\n\tstruct device *elm_dev;\n\tstruct gpio_desc *ready_gpiod;\n\tunsigned int neccpg;\n\tunsigned int nsteps_per_eccpg;\n\tunsigned int eccpg_size;\n\tunsigned int eccpg_bytes;\n\tvoid (*data_in)(struct nand_chip *, void *, unsigned int, bool);\n\tvoid (*data_out)(struct nand_chip *, const void *, unsigned int, bool);\n\tlong: 32;\n};\n\nstruct omap_prcm_init_data {\n\tint index;\n\tvoid *mem;\n\tu32 phys;\n\ts16 offset;\n\tu16 flags;\n\ts32 device_inst_offset;\n\tint (*init)(const struct omap_prcm_init_data *);\n\tstruct device_node *np;\n};\n\nstruct omap_prcm_irq {\n\tconst char *name;\n\tunsigned int offset;\n\tbool priority;\n};\n\nstruct omap_prcm_irq_setup {\n\tu16 ack;\n\tu16 mask;\n\tu16 pm_ctrl;\n\tu8 nr_regs;\n\tu8 nr_irqs;\n\tconst struct omap_prcm_irq *irqs;\n\tint irq;\n\tvoid (*read_pending_irqs)(long unsigned int *);\n\tvoid (*ocp_barrier)(void);\n\tvoid (*save_and_clear_irqen)(u32 *);\n\tvoid (*restore_irqen)(u32 *);\n\tvoid (*reconfigure_io_chain)(void);\n\tu32 *saved_mask;\n\tu32 *priority_mask;\n\tint base_irq;\n\tbool suspended;\n\tbool suspend_save_flag;\n};\n\nstruct omap_prm_data;\n\nstruct omap_prm_domain;\n\nstruct omap_prm {\n\tconst struct omap_prm_data *data;\n\tvoid *base;\n\tstruct omap_prm_domain *prmd;\n};\n\nstruct omap_prm_domain_map;\n\nstruct omap_rst_map;\n\nstruct omap_prm_data {\n\tu32 base;\n\tconst char *name;\n\tconst char *clkdm_name;\n\tu16 pwrstctrl;\n\tu16 pwrstst;\n\tconst struct omap_prm_domain_map *dmap;\n\tu16 rstctrl;\n\tu16 rstst;\n\tconst struct omap_rst_map *rstmap;\n\tu8 flags;\n};\n\nstruct omap_prm_domain {\n\tstruct device *dev;\n\tstruct omap_prm *prm;\n\tstruct generic_pm_domain pd;\n\tu16 pwrstctrl;\n\tu16 pwrstst;\n\tconst struct omap_prm_domain_map *cap;\n\tu32 pwrstctrl_saved;\n\tunsigned int uses_pm_clk: 1;\n};\n\nstruct omap_prm_domain_map {\n\tunsigned int usable_modes;\n\tlong unsigned int statechange: 1;\n\tlong unsigned int logicretstate: 1;\n};\n\nstruct omap_prm_irq_context {\n\tlong unsigned int irq_enable;\n\tlong unsigned int pm_ctrl;\n};\n\nstruct omap_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tstruct omap_prm *prm;\n\tu32 mask;\n\tspinlock_t lock;\n\tstruct clockdomain *clkdm;\n\tstruct device *dev;\n};\n\nstruct omap_rng_pdata;\n\nstruct omap_rng_dev {\n\tvoid *base;\n\tstruct device *dev;\n\tconst struct omap_rng_pdata *pdata;\n\tstruct hwrng rng;\n\tstruct clk *clk;\n\tstruct clk *clk_reg;\n};\n\nstruct omap_rng_pdata {\n\tu16 *regs;\n\tu32 data_size;\n\tu32 (*data_present)(struct omap_rng_dev *);\n\tint (*init)(struct omap_rng_dev *);\n\tvoid (*cleanup)(struct omap_rng_dev *);\n};\n\nstruct omap_rom_rng {\n\tstruct clk *clk;\n\tstruct device *dev;\n\tstruct hwrng ops;\n\tu32 (*rom_rng_call)(u32, u32, u32);\n};\n\nstruct omap_rst_map {\n\ts8 rst;\n\ts8 st;\n};\n\nstruct omap_sdrc_params {\n\tlong unsigned int rate;\n\tu32 actim_ctrla;\n\tu32 actim_ctrlb;\n\tu32 rfr_ctrl;\n\tu32 mr;\n};\n\nstruct omap_smartreflex_dev_attr {\n\tconst char *sensor_voltdm_name;\n};\n\nstruct omap_smp_config {\n\tlong unsigned int cpu1_rstctrl_pa;\n\tvoid *cpu1_rstctrl_va;\n\tvoid *scu_base;\n\tvoid *wakeupgen_base;\n\tvoid *startup_addr;\n};\n\nstruct omap_sr_nvalue_table;\n\nstruct omap_sr_data {\n\tconst char *name;\n\tint ip_type;\n\tu32 senp_mod;\n\tu32 senn_mod;\n\tu32 err_weight;\n\tu32 err_maxlimit;\n\tu32 accum_data;\n\tu32 senn_avgweight;\n\tu32 senp_avgweight;\n\tint nvalue_count;\n\tstruct omap_sr_nvalue_table *nvalue_table;\n\tstruct voltagedomain *voltdm;\n};\n\nstruct omap_sr_nvalue_table {\n\tu32 efuse_offs;\n\tu32 nvalue;\n\tu32 errminlimit;\n\tlong unsigned int volt_nominal;\n};\n\nstruct omap_system_dma_plat_info {\n\tconst struct omap_dma_reg *reg_map;\n\tunsigned int channel_stride;\n\tstruct omap_dma_dev_attr *dma_attr;\n\tu32 errata;\n\tvoid (*show_dma_caps)(void);\n\tvoid (*clear_lch_regs)(int);\n\tvoid (*clear_dma)(int);\n\tvoid (*dma_write)(u32, int, int);\n\tu32 (*dma_read)(int, int);\n\tconst struct dma_slave_map *slave_map;\n\tint slavecnt;\n};\n\nstruct omap_type2_desc {\n\tuint32_t next_desc;\n\tuint32_t en;\n\tuint32_t addr;\n\tuint16_t fn;\n\tuint16_t cicr;\n\tint16_t cdei;\n\tint16_t csei;\n\tint32_t cdfi;\n\tint32_t csfi;\n};\n\nstruct phy_companion;\n\nstruct omap_usb {\n\tstruct usb_phy phy;\n\tstruct phy_companion *comparator;\n\tvoid *pll_ctrl_base;\n\tvoid *phy_base;\n\tstruct device *dev;\n\tstruct device *control_dev;\n\tstruct clk *wkupclk;\n\tstruct clk *optclk;\n\tu8 flags;\n\tstruct regmap *syscon_phy_power;\n\tunsigned int power_reg;\n\tu32 mask;\n\tu32 power_on;\n\tu32 power_off;\n};\n\nstruct omap_vc_common;\n\nstruct omap_vc_channel {\n\tu16 i2c_slave_addr;\n\tu16 volt_reg_addr;\n\tu16 cmd_reg_addr;\n\tu8 cfg_channel;\n\tbool i2c_high_speed;\n\tconst struct omap_vc_common *common;\n\tu32 smps_sa_mask;\n\tu32 smps_volra_mask;\n\tu32 smps_cmdra_mask;\n\tu8 cmdval_reg;\n\tu8 smps_sa_reg;\n\tu8 smps_volra_reg;\n\tu8 smps_cmdra_reg;\n\tu8 cfg_channel_reg;\n\tu8 cfg_channel_sa_shift;\n\tu8 flags;\n};\n\nstruct omap_vc_channel_cfg {\n\tu8 sa;\n\tu8 rav;\n\tu8 rac;\n\tu8 racen;\n\tu8 cmd;\n};\n\nstruct omap_vc_common {\n\tu32 cmd_on_mask;\n\tu32 valid;\n\tu8 bypass_val_reg;\n\tu8 data_shift;\n\tu8 slaveaddr_shift;\n\tu8 regaddr_shift;\n\tu8 cmd_on_shift;\n\tu8 cmd_onlp_shift;\n\tu8 cmd_ret_shift;\n\tu8 cmd_off_shift;\n\tu8 i2c_cfg_reg;\n\tu8 i2c_cfg_clear_mask;\n\tu8 i2c_cfg_hsen_mask;\n\tu8 i2c_mcode_mask;\n};\n\nstruct omap_vc_param {\n\tu32 on;\n\tu32 onlp;\n\tu32 ret;\n\tu32 off;\n};\n\nstruct omap_vfsm_instance {\n\tu32 voltsetup_mask;\n\tu8 voltsetup_reg;\n\tu8 voltsetup_off_reg;\n};\n\nstruct omap_volt_data {\n\tu32 volt_nominal;\n\tu32 sr_efuse_offs;\n\tu8 sr_errminlimit;\n\tu8 vp_errgain;\n};\n\nstruct omap_voltdm_pmic {\n\tint slew_rate;\n\tint step_size;\n\tu16 i2c_slave_addr;\n\tu16 volt_reg_addr;\n\tu16 cmd_reg_addr;\n\tu8 vp_erroroffset;\n\tu8 vp_vstepmin;\n\tu8 vp_vstepmax;\n\tu32 vddmin;\n\tu32 vddmax;\n\tu8 vp_timeout_us;\n\tbool i2c_high_speed;\n\tu32 i2c_pad_load;\n\tu8 i2c_mcode;\n\tlong unsigned int (*vsel_to_uv)(const u8);\n\tu8 (*uv_to_vsel)(long unsigned int);\n};\n\nstruct omap_vp_ops;\n\nstruct omap_vp_common {\n\tu32 vpconfig_erroroffset_mask;\n\tu32 vpconfig_errorgain_mask;\n\tu32 vpconfig_initvoltage_mask;\n\tu8 vpconfig_timeouten;\n\tu8 vpconfig_initvdd;\n\tu8 vpconfig_forceupdate;\n\tu8 vpconfig_vpenable;\n\tu8 vstepmin_stepmin_shift;\n\tu8 vstepmin_smpswaittimemin_shift;\n\tu8 vstepmax_stepmax_shift;\n\tu8 vstepmax_smpswaittimemax_shift;\n\tu8 vlimitto_vddmin_shift;\n\tu8 vlimitto_vddmax_shift;\n\tu8 vlimitto_timeout_shift;\n\tu8 vpvoltage_mask;\n\tconst struct omap_vp_ops *ops;\n};\n\nstruct omap_vp_instance {\n\tconst struct omap_vp_common *common;\n\tu8 vpconfig;\n\tu8 vstepmin;\n\tu8 vstepmax;\n\tu8 vlimitto;\n\tu8 vstatus;\n\tu8 voltage;\n\tu8 id;\n\tbool enabled;\n};\n\nstruct omap_vp_ops {\n\tu32 (*check_txdone)(u8);\n\tvoid (*clear_txdone)(u8);\n};\n\nstruct omap_vp_param {\n\tu32 vddmax;\n\tu32 vddmin;\n};\n\nstruct omap_wakeupgen_ops {\n\tvoid (*save_context)(void);\n\tvoid (*restore_context)(void);\n};\n\nstruct onboard_dev_pdata {\n\tlong unsigned int reset_us;\n\tlong unsigned int power_on_delay_us;\n\tunsigned int num_supplies;\n\tconst char * const supply_names[2];\n\tbool is_hub;\n};\n\nstruct static_key_true;\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct oneshot_trig_data {\n\tunsigned int invert;\n};\n\nstruct onfi_ext_ecc_info {\n\tu8 ecc_bits;\n\tu8 codeword_size;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 reserved[2];\n};\n\nstruct onfi_ext_section {\n\tu8 type;\n\tu8 length;\n};\n\nstruct onfi_ext_param_page {\n\t__le16 crc;\n\tu8 sig[4];\n\tu8 reserved0[10];\n\tstruct onfi_ext_section sections[8];\n};\n\nstruct onfi_params {\n\tint version;\n\tu16 tPROG;\n\tu16 tBERS;\n\tu16 tR;\n\tu16 tCCS;\n\tbool fast_tCAD;\n\tu16 sdr_timing_modes;\n\tu16 nvddr_timing_modes;\n\tu16 vendor_revision;\n\tu8 vendor[88];\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct op {\n\tu32 (* const fn)(int, int, int, u32);\n\tu32 flags;\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct opp_config_data {\n\tstruct opp_table *opp_table;\n\tunsigned int flags;\n\tunsigned int required_dev_index;\n};\n\nstruct opp_device {\n\tstruct list_head node;\n\tconst struct device *dev;\n\tstruct dentry *dentry;\n};\n\nstruct opp_table {\n\tstruct list_head node;\n\tstruct list_head lazy;\n\tstruct blocking_notifier_head head;\n\tstruct list_head dev_list;\n\tstruct list_head opp_list;\n\tstruct kref kref;\n\tstruct mutex lock;\n\tstruct device_node *np;\n\tlong unsigned int clock_latency_ns_max;\n\tunsigned int voltage_tolerance_v1;\n\tunsigned int parsed_static_opps;\n\tenum opp_table_access shared_opp;\n\tlong unsigned int current_rate_single_clk;\n\tstruct dev_pm_opp *current_opp;\n\tstruct dev_pm_opp *suspend_opp;\n\tstruct opp_table **required_opp_tables;\n\tstruct device **required_devs;\n\tunsigned int required_opp_count;\n\tunsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char *prop_name;\n\tconfig_clks_t config_clks;\n\tstruct clk **clks;\n\tstruct clk *clk;\n\tint clk_count;\n\tconfig_regulators_t config_regulators;\n\tstruct regulator **regulators;\n\tint regulator_count;\n\tstruct icc_path **paths;\n\tunsigned int path_count;\n\tbool enabled;\n\tbool is_genpd;\n\tstruct dentry *dentry;\n\tchar dentry_name[255];\n};\n\ntypedef void optee_invoke_fn(long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, struct arm_smccc_res *);\n\nstruct optee_pcpu;\n\nstruct optee_smc {\n\toptee_invoke_fn *invoke_fn;\n\tvoid *memremaped_shm;\n\tu32 sec_caps;\n\tunsigned int notif_irq;\n\tstruct optee_pcpu *optee_pcpu;\n\tstruct workqueue_struct *notif_pcpu_wq;\n\tstruct work_struct notif_pcpu_work;\n\tunsigned int notif_cpuhp_state;\n};\n\nstruct optee_ffa {\n\tstruct ffa_device *ffa_dev;\n\tu32 bottom_half_value;\n\tstruct mutex mutex;\n\tstruct rhashtable global_ids;\n\tstruct workqueue_struct *notif_wq;\n\tstruct work_struct notif_work;\n};\n\nstruct optee_shm_arg_cache {\n\tu32 flags;\n\tstruct mutex mutex;\n\tstruct list_head shm_args;\n};\n\nstruct optee_call_queue {\n\tstruct mutex mutex;\n\tstruct list_head waiters;\n\tint total_thread_count;\n\tint free_thread_count;\n\tint sys_thread_req_count;\n};\n\nstruct optee_notif {\n\tu_int max_key;\n\tspinlock_t lock;\n\tstruct list_head db;\n\tu_long *bitmap;\n};\n\nstruct tee_context;\n\nstruct optee_supp {\n\tstruct mutex mutex;\n\tstruct tee_context *ctx;\n\tint req_id;\n\tstruct list_head reqs;\n\tstruct idr idr;\n\tstruct completion reqs_c;\n};\n\nstruct optee_revision {\n\tu32 os_major;\n\tu32 os_minor;\n\tu64 os_build_id;\n};\n\nstruct tee_device;\n\nstruct optee_ops;\n\nstruct tee_shm_pool;\n\nstruct optee {\n\tstruct tee_device *supp_teedev;\n\tstruct tee_device *teedev;\n\tconst struct optee_ops *ops;\n\tstruct tee_context *ctx;\n\tunion {\n\t\tstruct optee_smc smc;\n\t\tstruct optee_ffa ffa;\n\t};\n\tstruct optee_shm_arg_cache shm_arg_cache;\n\tstruct optee_call_queue call_queue;\n\tstruct optee_notif notif;\n\tstruct optee_supp supp;\n\tstruct tee_shm_pool *pool;\n\tstruct mutex rpmb_dev_mutex;\n\tstruct rpmb_dev *rpmb_dev;\n\tstruct notifier_block rpmb_intf;\n\tunsigned int rpc_param_count;\n\tbool scan_bus_done;\n\tbool rpmb_scan_bus_done;\n\tbool in_kernel_rpmb_routing;\n\tstruct work_struct scan_bus_work;\n\tstruct work_struct rpmb_scan_bus_work;\n\tlong: 32;\n\tstruct optee_revision revision;\n};\n\nstruct optee_call_ctx {\n\tvoid *pages_list;\n\tsize_t num_entries;\n};\n\nstruct optee_call_waiter {\n\tstruct list_head list_node;\n\tstruct completion c;\n\tbool sys_thread;\n};\n\nstruct optee_context_data {\n\tstruct mutex mutex;\n\tstruct list_head sess_list;\n};\n\nstruct optee_msg_param_tmem {\n\tu64 buf_ptr;\n\tu64 size;\n\tu64 shm_ref;\n};\n\nstruct optee_msg_param_rmem {\n\tu64 offs;\n\tu64 size;\n\tu64 shm_ref;\n};\n\nstruct optee_msg_param_fmem {\n\tu32 offs_low;\n\tu16 offs_high;\n\tu16 internal_offs;\n\tu64 size;\n\tu64 global_id;\n};\n\nstruct optee_msg_param_value {\n\tu64 a;\n\tu64 b;\n\tu64 c;\n};\n\nstruct optee_msg_param {\n\tu64 attr;\n\tunion {\n\t\tstruct optee_msg_param_tmem tmem;\n\t\tstruct optee_msg_param_rmem rmem;\n\t\tstruct optee_msg_param_fmem fmem;\n\t\tstruct optee_msg_param_value value;\n\t\tu8 octets[24];\n\t} u;\n};\n\nstruct optee_msg_arg {\n\tu32 cmd;\n\tu32 func;\n\tu32 session;\n\tu32 cancel_id;\n\tu32 pad;\n\tu32 ret;\n\tu32 ret_origin;\n\tu32 num_params;\n\tstruct optee_msg_param params[0];\n};\n\nstruct tee_shm;\n\nstruct tee_param;\n\nstruct optee_ops {\n\tint (*do_call_with_arg)(struct tee_context *, struct tee_shm *, u_int, bool);\n\tint (*to_msg_param)(struct optee *, struct optee_msg_param *, size_t, const struct tee_param *);\n\tint (*from_msg_param)(struct optee *, struct tee_param *, size_t, const struct optee_msg_param *);\n\tint (*lend_protmem)(struct optee *, struct tee_shm *, u32 *, unsigned int, u32);\n\tint (*reclaim_protmem)(struct optee *, struct tee_shm *);\n};\n\nstruct optee_pcpu {\n\tstruct optee *optee;\n};\n\nstruct tee_protmem_pool_ops;\n\nstruct tee_protmem_pool {\n\tconst struct tee_protmem_pool_ops *ops;\n};\n\nstruct optee_protmem_dyn_pool {\n\tstruct tee_protmem_pool pool;\n\tstruct gen_pool *gen_pool;\n\tstruct optee *optee;\n\tsize_t page_count;\n\tu32 *mem_attrs;\n\tu_int mem_attr_count;\n\trefcount_t refcount;\n\tu32 use_case;\n\tstruct tee_shm *protmem;\n\tstruct mutex mutex;\n};\n\nstruct optee_rng_private {\n\tstruct device *dev;\n\tstruct tee_context *ctx;\n\tu32 session_id;\n\tu32 data_rate;\n\tstruct tee_shm *entropy_shm_pool;\n\tstruct hwrng optee_rng;\n};\n\nstruct optee_rpc_param {\n\tu32 a0;\n\tu32 a1;\n\tu32 a2;\n\tu32 a3;\n\tu32 a4;\n\tu32 a5;\n\tu32 a6;\n\tu32 a7;\n};\n\nstruct optee_session {\n\tstruct list_head list_node;\n\tu32 session_id;\n\tbool use_sys_thread;\n};\n\nstruct optee_shm_arg_entry {\n\tstruct list_head list_node;\n\tstruct tee_shm *shm;\n\tlong unsigned int map[1];\n};\n\nstruct optee_smc_call_get_os_revision_result {\n\tlong unsigned int major;\n\tlong unsigned int minor;\n\tlong unsigned int build_id;\n\tlong unsigned int reserved1;\n};\n\nstruct optee_smc_calls_revision_result {\n\tlong unsigned int major;\n\tlong unsigned int minor;\n\tlong unsigned int reserved0;\n\tlong unsigned int reserved1;\n};\n\nstruct optee_smc_disable_shm_cache_result {\n\tlong unsigned int status;\n\tlong unsigned int shm_upper32;\n\tlong unsigned int shm_lower32;\n\tlong unsigned int reserved0;\n};\n\nstruct optee_smc_exchange_capabilities_result {\n\tlong unsigned int status;\n\tlong unsigned int capabilities;\n\tlong unsigned int max_notif_value;\n\tlong unsigned int data;\n};\n\nstruct optee_smc_get_shm_config_result {\n\tlong unsigned int status;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int settings;\n};\n\nstruct optee_supp_req {\n\tstruct list_head link;\n\tbool in_queue;\n\tu32 func;\n\tu32 ret;\n\tsize_t num_params;\n\tstruct tee_param *param;\n\tstruct completion c;\n};\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct orion_direct_acc {\n\tvoid *vaddr;\n\tu32 size;\n};\n\nstruct orion_child_options {\n\tstruct orion_direct_acc direct_access;\n};\n\nstruct orion_ehci_data {\n\tenum orion_ehci_phy_ver phy_version;\n};\n\nstruct orion_ehci_hcd {\n\tstruct clk *clk;\n\tstruct phy *phy;\n};\n\nstruct orion_mdio_dev {\n\tvoid *regs;\n\tstruct clk *clk[4];\n\tint err_interrupt;\n\twait_queue_head_t smi_busy_wait;\n};\n\nstruct orion_mdio_ops {\n\tint (*is_done)(struct orion_mdio_dev *);\n};\n\nstruct orion_spi_dev;\n\nstruct orion_spi {\n\tstruct spi_controller *host;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *axi_clk;\n\tconst struct orion_spi_dev *devdata;\n\tstruct device *dev;\n\tstruct orion_child_options child[8];\n};\n\nstruct orion_spi_dev {\n\tenum orion_spi_type typ;\n\tlong unsigned int max_hz;\n\tunsigned int min_divisor;\n\tunsigned int max_divisor;\n\tu32 prescale_mask;\n\tbool is_errata_50mhz_ac;\n};\n\nstruct orion_watchdog_data;\n\nstruct orion_watchdog {\n\tstruct watchdog_device wdt;\n\tvoid *reg;\n\tvoid *rstout;\n\tvoid *rstout_mask;\n\tlong unsigned int clk_rate;\n\tstruct clk *clk;\n\tconst struct orion_watchdog_data *data;\n};\n\nstruct orion_watchdog_data {\n\tint wdt_counter_offset;\n\tint wdt_enable_bit;\n\tint rstout_enable_bit;\n\tint rstout_mask_bit;\n\tint (*clock_init)(struct platform_device *, struct orion_watchdog *);\n\tint (*enabled)(struct orion_watchdog *);\n\tint (*start)(struct watchdog_device *);\n\tint (*stop)(struct watchdog_device *);\n};\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\nstruct osnoise_entry {\n\tstruct trace_entry ent;\n\tu64 noise;\n\tu64 runtime;\n\tu64 max_sample;\n\tunsigned int hw_count;\n\tunsigned int nmi_count;\n\tunsigned int irq_count;\n\tunsigned int softirq_count;\n\tunsigned int thread_count;\n\tlong: 32;\n};\n\nstruct otg_fsm_ops {\n\tvoid (*chrg_vbus)(struct otg_fsm *, int);\n\tvoid (*drv_vbus)(struct otg_fsm *, int);\n\tvoid (*loc_conn)(struct otg_fsm *, int);\n\tvoid (*loc_sof)(struct otg_fsm *, int);\n\tvoid (*start_pulse)(struct otg_fsm *);\n\tvoid (*start_adp_prb)(struct otg_fsm *);\n\tvoid (*start_adp_sns)(struct otg_fsm *);\n\tvoid (*add_timer)(struct otg_fsm *, enum otg_fsm_timer);\n\tvoid (*del_timer)(struct otg_fsm *, enum otg_fsm_timer);\n\tint (*start_host)(struct otg_fsm *, int);\n\tint (*start_gadget)(struct otg_fsm *, int);\n};\n\nstruct otp_info {\n\t__u32 start;\n\t__u32 length;\n\t__u32 locked;\n};\n\nstruct otpc_map {\n\tu32 otpc_row_size;\n\tu16 data_r_offset[4];\n\tu16 data_w_offset[4];\n};\n\nstruct otpc_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tconst struct otpc_map *map;\n\tstruct nvmem_config *config;\n};\n\nstruct output {\n\tvoid (*fn)(void *, const char *, size_t, bool);\n\tvoid *ctx;\n\tchar buf[256];\n};\n\nstruct owl_clk_common {\n\tstruct regmap *regmap;\n\tstruct clk_hw hw;\n};\n\nstruct owl_reset_map;\n\nstruct owl_clk_desc {\n\tstruct owl_clk_common **clks;\n\tlong unsigned int num_clks;\n\tstruct clk_hw_onecell_data *hw_clks;\n\tconst struct owl_reset_map *resets;\n\tlong unsigned int num_resets;\n\tstruct regmap *regmap;\n};\n\nstruct owl_mux_hw {\n\tu32 reg;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct owl_gate_hw {\n\tu32 reg;\n\tu8 bit_idx;\n\tu8 gate_flags;\n};\n\nstruct owl_divider_hw {\n\tu32 reg;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tstruct clk_div_table *table;\n};\n\nstruct owl_factor_hw {\n\tu32 reg;\n\tu8 shift;\n\tu8 width;\n\tu8 fct_flags;\n\tstruct clk_factor_table *table;\n};\n\nunion owl_rate {\n\tstruct owl_divider_hw div_hw;\n\tstruct owl_factor_hw factor_hw;\n\tstruct clk_fixed_factor fix_fact_hw;\n};\n\nstruct owl_composite {\n\tstruct owl_mux_hw mux_hw;\n\tstruct owl_gate_hw gate_hw;\n\tunion owl_rate rate;\n\tconst struct clk_ops *fix_fact_ops;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_divider {\n\tstruct owl_divider_hw div_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_dma_pchan;\n\nstruct owl_dma_vchan;\n\nstruct owl_dma {\n\tstruct dma_device dma;\n\tvoid *base;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tstruct dma_pool *lli_pool;\n\tint irq;\n\tunsigned int nr_pchans;\n\tstruct owl_dma_pchan *pchans;\n\tunsigned int nr_vchans;\n\tstruct owl_dma_vchan *vchans;\n\tenum owl_dma_id devid;\n};\n\nstruct owl_dma_lli {\n\tu32 hw[9];\n\tdma_addr_t phys;\n\tstruct list_head node;\n};\n\nstruct owl_dma_pchan {\n\tu32 id;\n\tvoid *base;\n\tstruct owl_dma_vchan *vchan;\n};\n\nstruct owl_dma_txd {\n\tstruct virt_dma_desc vd;\n\tstruct list_head lli_list;\n\tbool cyclic;\n};\n\nstruct owl_dma_vchan {\n\tstruct virt_dma_chan vc;\n\tstruct owl_dma_pchan *pchan;\n\tstruct owl_dma_txd *txd;\n\tstruct dma_slave_config cfg;\n\tu8 drq;\n};\n\nstruct owl_factor {\n\tstruct owl_factor_hw factor_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_gate {\n\tstruct owl_gate_hw gate_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_gpio_port {\n\tunsigned int offset;\n\tunsigned int pins;\n\tunsigned int outen;\n\tunsigned int inen;\n\tunsigned int dat;\n\tunsigned int intc_ctl;\n\tunsigned int intc_pd;\n\tunsigned int intc_msk;\n\tunsigned int intc_type;\n\tu8 shared_ctl_offset;\n};\n\nstruct owl_i2c_dev {\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *msg;\n\tstruct completion msg_complete;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tvoid *base;\n\tlong unsigned int clk_rate;\n\tu32 bus_freq;\n\tu32 msg_ptr;\n\tint err;\n};\n\nstruct owl_mmc_host {\n\tstruct device *dev;\n\tstruct reset_control *reset;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct completion sdc_complete;\n\tspinlock_t lock;\n\tint irq;\n\tu32 clock;\n\tbool ddr_50;\n\tenum dma_data_direction dma_dir;\n\tstruct dma_chan *dma;\n\tstruct dma_async_tx_descriptor *desc;\n\tstruct dma_slave_config dma_cfg;\n\tstruct completion dma_complete;\n\tstruct mmc_host *mmc;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n};\n\nstruct owl_mux {\n\tstruct owl_mux_hw mux_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_pullctl;\n\nstruct owl_st;\n\nstruct owl_padinfo {\n\tint pad;\n\tstruct owl_pullctl *pullctl;\n\tstruct owl_st *st;\n};\n\nstruct owl_pinctrl_soc_data;\n\nstruct owl_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctrldev;\n\tstruct gpio_chip chip;\n\traw_spinlock_t lock;\n\tstruct clk *clk;\n\tconst struct owl_pinctrl_soc_data *soc;\n\tvoid *base;\n\tunsigned int num_irq;\n\tunsigned int *irq;\n};\n\nstruct owl_pinmux_func;\n\nstruct owl_pingroup;\n\nstruct owl_pinctrl_soc_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct owl_pinmux_func *functions;\n\tunsigned int nfunctions;\n\tconst struct owl_pingroup *groups;\n\tunsigned int ngroups;\n\tconst struct owl_padinfo *padinfo;\n\tunsigned int ngpios;\n\tconst struct owl_gpio_port *ports;\n\tunsigned int nports;\n\tint (*padctl_val2arg)(const struct owl_padinfo *, unsigned int, u32 *);\n\tint (*padctl_arg2val)(const struct owl_padinfo *, unsigned int, u32 *);\n};\n\nstruct owl_pingroup {\n\tconst char *name;\n\tunsigned int *pads;\n\tunsigned int npads;\n\tunsigned int *funcs;\n\tunsigned int nfuncs;\n\tint mfpctl_reg;\n\tunsigned int mfpctl_shift;\n\tunsigned int mfpctl_width;\n\tint drv_reg;\n\tunsigned int drv_shift;\n\tunsigned int drv_width;\n\tint sr_reg;\n\tunsigned int sr_shift;\n\tunsigned int sr_width;\n};\n\nstruct owl_pinmux_func {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct owl_pll_hw {\n\tu32 reg;\n\tu32 bfreq;\n\tu8 bit_idx;\n\tu8 shift;\n\tu8 width;\n\tu8 min_mul;\n\tu8 max_mul;\n\tu8 delay;\n\tconst struct clk_pll_table *table;\n};\n\nstruct owl_pll {\n\tstruct owl_pll_hw pll_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_pullctl {\n\tint reg;\n\tunsigned int shift;\n\tunsigned int width;\n};\n\nstruct owl_reset {\n\tstruct reset_controller_dev rcdev;\n\tconst struct owl_reset_map *reset_map;\n\tstruct regmap *regmap;\n};\n\nstruct owl_reset_map {\n\tu32 reg;\n\tu32 bit;\n};\n\nstruct owl_sirq_params;\n\nstruct owl_sirq_chip_data {\n\tconst struct owl_sirq_params *params;\n\tvoid *base;\n\traw_spinlock_t lock;\n\tu32 ext_irqs[3];\n};\n\nstruct owl_sirq_params {\n\tbool reg_shared;\n\tu16 reg_offset[3];\n};\n\nstruct owl_st {\n\tint reg;\n\tunsigned int shift;\n\tunsigned int width;\n};\n\nstruct owl_uart_info {\n\tunsigned int tx_fifosize;\n};\n\nstruct owl_uart_port {\n\tstruct uart_port port;\n\tstruct clk *clk;\n\tlong: 32;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tlong: 32;\n\tu64 bus_offset;\n};\n\nstruct p2wi {\n\tstruct i2c_adapter adapter;\n\tstruct completion complete;\n\tunsigned int status;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct reset_control *rstc;\n\tint target_addr;\n\tlong: 32;\n};\n\nstruct scsi_sense_hdr;\n\nstruct packet_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct scsi_sense_hdr *sshdr;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tlong: 32;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu32 history[16];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct packet_type prot_hook;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_t tp_drops;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef struct page *pgtable_t;\n\nstruct page_address_map {\n\tstruct page *page;\n\tvoid *virtual;\n\tstruct list_head list;\n};\n\nstruct page_address_slot {\n\tstruct list_head lh;\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct page_change_data {\n\tpgprot_t set_mask;\n\tpgprot_t clear_mask;\n};\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct page_pool_alloc_stats {\n\tu64 fast;\n\tu64 slow;\n\tu64 slow_high_order;\n\tu64 empty;\n\tu64 refill;\n\tu64 waive;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool_recycle_stats;\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tbool system: 1;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 32;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tstruct page_pool_alloc_stats alloc_stats;\n\tu32 xdp_mem_id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct pp_alloc_cache alloc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tstruct page_pool_recycle_stats *recycle_stats;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tlong: 32;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t\tlong: 32;\n\t} user;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_pool_recycle_stats {\n\tu64 cached;\n\tu64 cache_full;\n\tu64 ring;\n\tu64 ring_full;\n\tu64 released_refcnt;\n};\n\nstruct page_pool_stats {\n\tstruct page_pool_alloc_stats alloc_stats;\n\tstruct page_pool_recycle_stats recycle_stats;\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n\tlong: 32;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct palmas_gpadc;\n\nstruct palmas_pmic_driver_data;\n\nstruct palmas_pmic;\n\nstruct palmas_resource;\n\nstruct palmas_usb;\n\nstruct palmas {\n\tstruct device *dev;\n\tstruct i2c_client *i2c_clients[3];\n\tstruct regmap *regmap[3];\n\tint id;\n\tunsigned int features;\n\tint irq;\n\tu32 irq_mask;\n\tstruct mutex irq_lock;\n\tstruct regmap_irq_chip_data *irq_data;\n\tstruct palmas_pmic_driver_data *pmic_ddata;\n\tstruct palmas_pmic *pmic;\n\tstruct palmas_gpadc *gpadc;\n\tstruct palmas_resource *resource;\n\tstruct palmas_usb *usb;\n\tu8 gpio_muxed;\n\tu8 led_muxed;\n\tu8 pwm_muxed;\n};\n\nstruct palmas_clk_platform_data {\n\tint clk32kg_mode_sleep;\n\tint clk32kgaudio_mode_sleep;\n};\n\nstruct palmas_device_data {\n\tint ngpio;\n};\n\nstruct palmas_driver_data {\n\tunsigned int features;\n\tconst struct regmap_irq_chip *irq_chip;\n};\n\nstruct palmas_gpadc_platform_data {\n\tint ch3_current;\n\tint ch0_current;\n\tbool extended_delay;\n\tint bat_removal;\n\tint start_polarity;\n\tint auto_conversion_period_ms;\n};\n\nstruct palmas_gpio {\n\tstruct gpio_chip gpio_chip;\n\tstruct palmas *palmas;\n};\n\nstruct palmas_pin_function;\n\nstruct palmas_pingroup;\n\nstruct palmas_pctrl_chip_info {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct palmas *palmas;\n\tint pins_current_opt[26];\n\tconst struct palmas_pin_function *functions;\n\tunsigned int num_functions;\n\tconst struct palmas_pingroup *pin_groups;\n\tint num_pin_groups;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int num_pins;\n};\n\nstruct palmas_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct palmas_pins_pullup_dn_info;\n\nstruct palmas_pins_od_info;\n\nstruct palmas_pin_info {\n\tenum palmas_pinmux mux_opt;\n\tconst struct palmas_pins_pullup_dn_info *pud_info;\n\tconst struct palmas_pins_od_info *od_info;\n};\n\nstruct palmas_pinctrl_data {\n\tconst struct palmas_pingroup *pin_groups;\n\tint num_pin_groups;\n};\n\nstruct palmas_pingroup {\n\tconst char *name;\n\tconst unsigned int pins[1];\n\tunsigned int npins;\n\tunsigned int mux_reg_base;\n\tunsigned int mux_reg_add;\n\tunsigned int mux_reg_mask;\n\tunsigned int mux_bit_shift;\n\tconst struct palmas_pin_info *opt[4];\n};\n\nstruct palmas_pins_od_info {\n\tint od_reg_base;\n\tint od_reg_add;\n\tint od_mask;\n\tint od_enable;\n\tint od_disable;\n};\n\nstruct palmas_pins_pullup_dn_info {\n\tint pullup_dn_reg_base;\n\tint pullup_dn_reg_add;\n\tint pullup_dn_mask;\n\tint normal_val;\n\tint pull_up_val;\n\tint pull_dn_val;\n};\n\nstruct palmas_pmic_platform_data;\n\nstruct palmas_usb_platform_data;\n\nstruct palmas_resource_platform_data;\n\nstruct palmas_platform_data {\n\tint irq_flags;\n\tint gpio_base;\n\tu8 power_ctrl;\n\tint mux_from_pdata;\n\tu8 pad1;\n\tu8 pad2;\n\tbool pm_off;\n\tstruct palmas_pmic_platform_data *pmic_pdata;\n\tstruct palmas_gpadc_platform_data *gpadc_pdata;\n\tstruct palmas_usb_platform_data *usb_pdata;\n\tstruct palmas_resource_platform_data *resource_pdata;\n\tstruct palmas_clk_platform_data *clk_pdata;\n};\n\nstruct palmas_pmic {\n\tstruct palmas *palmas;\n\tstruct device *dev;\n\tstruct regulator_desc desc[27];\n\tstruct mutex mutex;\n\tint smps123;\n\tint smps457;\n\tint smps12;\n\tint range[10];\n\tunsigned int ramp_delay[10];\n\tunsigned int current_reg_mode[10];\n};\n\nstruct palmas_regs_info;\n\nstruct palmas_sleep_requestor_info;\n\nstruct palmas_pmic_driver_data {\n\tint smps_start;\n\tint smps_end;\n\tint ldo_begin;\n\tint ldo_end;\n\tint max_reg;\n\tbool has_regen3;\n\tstruct palmas_regs_info *palmas_regs_info;\n\tstruct of_regulator_match *palmas_matches;\n\tstruct palmas_sleep_requestor_info *sleep_req_info;\n\tint (*smps_register)(struct palmas_pmic *, struct palmas_pmic_driver_data *, struct palmas_pmic_platform_data *, const char *, struct regulator_config);\n\tint (*ldo_register)(struct palmas_pmic *, struct palmas_pmic_driver_data *, struct palmas_pmic_platform_data *, const char *, struct regulator_config);\n};\n\nstruct palmas_reg_init;\n\nstruct palmas_pmic_platform_data {\n\tstruct regulator_init_data *reg_data[27];\n\tstruct palmas_reg_init *reg_init[27];\n\tint ldo6_vibrator;\n\tbool enable_ldo8_tracking;\n};\n\nstruct palmas_reg_init {\n\tint warm_reset;\n\tint roof_floor;\n\tint mode_sleep;\n\tu8 vsel;\n};\n\nstruct palmas_regs_info {\n\tconst char *name;\n\tconst char *sname;\n\tu8 vsel_addr;\n\tu8 ctrl_addr;\n\tu8 tstep_addr;\n\tint sleep_id;\n};\n\nstruct palmas_resource {\n\tstruct palmas *palmas;\n\tstruct device *dev;\n};\n\nstruct palmas_resource_platform_data {\n\tint regen1_mode_sleep;\n\tint regen2_mode_sleep;\n\tint sysen1_mode_sleep;\n\tint sysen2_mode_sleep;\n\tu8 nsleep_res;\n\tu8 nsleep_smps;\n\tu8 nsleep_ldo1;\n\tu8 nsleep_ldo2;\n\tu8 enable1_res;\n\tu8 enable1_smps;\n\tu8 enable1_ldo1;\n\tu8 enable1_ldo2;\n\tu8 enable2_res;\n\tu8 enable2_smps;\n\tu8 enable2_ldo1;\n\tu8 enable2_ldo2;\n};\n\nstruct palmas_rtc {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tunsigned int irq;\n};\n\nstruct palmas_sleep_requestor_info {\n\tint id;\n\tint reg_offset;\n\tint bit_pos;\n};\n\nstruct palmas_usb {\n\tstruct palmas *palmas;\n\tstruct device *dev;\n\tstruct extcon_dev *edev;\n\tint id_otg_irq;\n\tint id_irq;\n\tint vbus_otg_irq;\n\tint vbus_irq;\n\tint gpio_id_irq;\n\tint gpio_vbus_irq;\n\tstruct gpio_desc *id_gpiod;\n\tstruct gpio_desc *vbus_gpiod;\n\tlong unsigned int sw_debounce_jiffies;\n\tstruct delayed_work wq_detectid;\n\tenum palmas_usb_state linkstat;\n\tint wakeup;\n\tbool enable_vbus_detection;\n\tbool enable_id_detection;\n\tbool enable_gpio_id_detection;\n\tbool enable_gpio_vbus_detection;\n};\n\nstruct palmas_usb_platform_data {\n\tint wakeup;\n};\n\nstruct panel_bridge {\n\tstruct drm_bridge bridge;\n\tstruct drm_connector connector;\n\tstruct drm_panel *panel;\n\tu32 connector_type;\n};\n\nstruct panel_delay {\n\tunsigned int hpd_reliable;\n\tunsigned int hpd_absent;\n\tunsigned int powered_on_to_enable;\n\tunsigned int prepare_to_enable;\n\tunsigned int enable;\n\tunsigned int disable;\n\tunsigned int unprepare;\n};\n\nstruct panel_desc {\n\tconst struct drm_display_mode *modes;\n\tunsigned int num_modes;\n\tconst struct display_timing *timings;\n\tunsigned int num_timings;\n\tunsigned int bpc;\n\tstruct {\n\t\tunsigned int width;\n\t\tunsigned int height;\n\t} size;\n\tstruct {\n\t\tunsigned int prepare;\n\t\tunsigned int enable;\n\t\tunsigned int disable;\n\t\tunsigned int unprepare;\n\t} delay;\n\tu32 bus_format;\n\tu32 bus_flags;\n\tint connector_type;\n};\n\nstruct panel_desc___2 {\n\tconst struct drm_display_mode *modes;\n\tunsigned int num_modes;\n\tconst struct display_timing *timings;\n\tunsigned int num_timings;\n\tunsigned int bpc;\n\tstruct {\n\t\tunsigned int width;\n\t\tunsigned int height;\n\t} size;\n\tstruct panel_delay delay;\n};\n\nstruct panel_desc_dsi {\n\tstruct panel_desc desc;\n\tlong unsigned int flags;\n\tenum mipi_dsi_pixel_format format;\n\tunsigned int lanes;\n};\n\nstruct panel_edp {\n\tstruct drm_panel base;\n\tbool no_hpd;\n\tlong: 32;\n\tktime_t prepared_time;\n\tktime_t powered_on_time;\n\tktime_t unprepared_time;\n\tconst struct panel_desc___2 *desc;\n\tstruct regulator *supply;\n\tstruct i2c_adapter *ddc;\n\tstruct drm_dp_aux *aux;\n\tstruct gpio_desc *enable_gpio;\n\tstruct gpio_desc *hpd_gpio;\n\tconst struct edp_panel_entry *detected_panel;\n\tconst struct drm_edid *drm_edid;\n\tstruct drm_display_mode override_mode;\n\tenum drm_panel_orientation orientation;\n\tlong: 32;\n};\n\nstruct panel_simple {\n\tstruct drm_panel base;\n\tktime_t unprepared_time;\n\tconst struct panel_desc *desc;\n\tstruct regulator *supply;\n\tstruct i2c_adapter *ddc;\n\tstruct gpio_desc *enable_gpio;\n\tconst struct drm_edid *drm_edid;\n\tstruct drm_display_mode override_mode;\n\tenum drm_panel_orientation orientation;\n};\n\nstruct parent_map {\n\tu8 src;\n\tu8 cfg;\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t\tlong: 32;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct partition_affinity {\n\tcpumask_t mask;\n\tstruct fwnode_handle *partition_id;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tlong: 32;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct pbias_of_data {\n\tunsigned int offset;\n};\n\nstruct pbias_reg_info {\n\tu32 enable;\n\tu32 enable_mask;\n\tu32 disable_val;\n\tu32 vmode;\n\tunsigned int enable_time;\n\tchar *name;\n\tconst unsigned int *pbias_volt_table;\n\tint n_voltages;\n};\n\nstruct pca953x_reg_config;\n\nstruct pca953x_chip {\n\tunsigned int gpio_start;\n\tstruct mutex i2c_lock;\n\tstruct regmap *regmap;\n\tstruct mutex irq_lock;\n\tlong unsigned int irq_mask[2];\n\tlong unsigned int irq_stat[2];\n\tlong unsigned int irq_trig_raise[2];\n\tlong unsigned int irq_trig_fall[2];\n\tlong unsigned int irq_trig_level_high[2];\n\tlong unsigned int irq_trig_level_low[2];\n\tatomic_t wakeup_path;\n\tstruct i2c_client *client;\n\tstruct gpio_chip gpio_chip;\n\tlong unsigned int driver_data;\n\tstruct regulator *regulator;\n\tconst struct pca953x_reg_config *regs;\n\tu8 (*recalc_addr)(struct pca953x_chip *, int, int);\n\tbool (*check_reg)(struct pca953x_chip *, unsigned int, u32);\n};\n\nstruct pca953x_platform_data {\n\tunsigned int gpio_base;\n\tint irq_base;\n};\n\nstruct pca953x_reg_config {\n\tint direction;\n\tint output;\n\tint input;\n\tint invert;\n};\n\nstruct pca954x {\n\tconst struct chip_desc___2 *chip;\n\tu8 last_chan;\n\ts32 idle_state;\n\tstruct i2c_client *client;\n\tstruct irq_domain *irq;\n\tunsigned int irq_mask;\n\traw_spinlock_t lock;\n\tstruct regulator *supply;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_cont;\n};\n\nstruct pcf857x {\n\tstruct gpio_chip chip;\n\tstruct i2c_client *client;\n\tstruct mutex lock;\n\tunsigned int out;\n\tunsigned int status;\n\tunsigned int irq_enabled;\n\tint (*write)(struct i2c_client *, unsigned int);\n\tint (*read)(struct i2c_client *);\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nstruct pci_bridge_emul_ops {\n\tpci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *, int, u32 *);\n\tpci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *, int, u32 *);\n\tpci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *, int, u32 *);\n\tvoid (*write_base)(struct pci_bridge_emul *, int, u32, u32, u32);\n\tvoid (*write_pcie)(struct pci_bridge_emul *, int, u32, u32, u32);\n\tvoid (*write_ext)(struct pci_bridge_emul *, int, u32, u32, u32);\n};\n\nstruct pci_bridge_reg_behavior {\n\tu32 ro;\n\tu32 rw;\n\tu32 w1c;\n};\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tint domain_nr;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tlong: 32;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n\tlong: 32;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_ecam_ops;\n\nstruct pci_config_window {\n\tstruct resource res;\n\tstruct resource busr;\n\tunsigned int bus_shift;\n\tvoid *priv;\n\tconst struct pci_ecam_ops *ops;\n\tunion {\n\t\tvoid *win;\n\t\tvoid **winp;\n\t};\n\tstruct device *parent;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct rcec_ea;\n\nstruct pcie_link_state;\n\nstruct pcie_bwctrl_data;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tstruct rcec_ea *rcec_ea;\n\tstruct pci_dev *rcec;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tstruct pcie_link_state *link_state;\n\tunsigned int aspm_l0s_support: 1;\n\tunsigned int aspm_l1_support: 1;\n\tunsigned int ltr_path: 1;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tlong: 32;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[11];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[11];\n\tstruct bin_attribute *res_attr_wc[11];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n\tlong: 32;\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_ecam_ops {\n\tunsigned int bus_shift;\n\tstruct pci_ops pci_ops;\n\tint (*init)(struct pci_config_window *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n};\n\nstruct pci_epc_ops;\n\nstruct pci_epc_mem;\n\nstruct pci_epc {\n\tstruct device dev;\n\tstruct list_head pci_epf;\n\tstruct mutex list_lock;\n\tconst struct pci_epc_ops *ops;\n\tstruct pci_epc_mem **windows;\n\tstruct pci_epc_mem *mem;\n\tunsigned int num_windows;\n\tu8 max_functions;\n\tu8 *max_vfs;\n\tstruct config_group *group;\n\tstruct mutex lock;\n\tlong unsigned int function_num_map;\n\tint domain_nr;\n\tbool init_complete;\n};\n\nstruct pci_epc_bar_desc {\n\tenum pci_epc_bar_type type;\n\tlong: 32;\n\tu64 fixed_size;\n\tbool only_64bit;\n\tlong: 32;\n};\n\nstruct pci_epf;\n\nstruct pci_epc_event_ops {\n\tint (*epc_init)(struct pci_epf *);\n\tvoid (*epc_deinit)(struct pci_epf *);\n\tint (*link_up)(struct pci_epf *);\n\tint (*link_down)(struct pci_epf *);\n\tint (*bus_master_enable)(struct pci_epf *);\n};\n\nstruct pci_epc_features {\n\tunsigned int linkup_notifier: 1;\n\tunsigned int dynamic_inbound_mapping: 1;\n\tunsigned int subrange_mapping: 1;\n\tunsigned int msi_capable: 1;\n\tunsigned int msix_capable: 1;\n\tunsigned int intx_capable: 1;\n\tlong: 32;\n\tstruct pci_epc_bar_desc bar[6];\n\tsize_t align;\n\tlong: 32;\n};\n\nstruct pci_epc_group {\n\tstruct config_group group;\n\tstruct pci_epc *epc;\n\tbool start;\n};\n\nstruct pci_epc_map {\n\tu64 pci_addr;\n\tsize_t pci_size;\n\tlong: 32;\n\tu64 map_pci_addr;\n\tsize_t map_size;\n\tphys_addr_t phys_base;\n\tphys_addr_t phys_addr;\n\tvoid *virt_base;\n\tvoid *virt_addr;\n\tlong: 32;\n};\n\nstruct pci_epc_mem_window {\n\tphys_addr_t phys_base;\n\tsize_t size;\n\tsize_t page_size;\n};\n\nstruct pci_epc_mem {\n\tstruct pci_epc_mem_window window;\n\tlong unsigned int *bitmap;\n\tint pages;\n\tstruct mutex lock;\n};\n\nstruct pci_epf_header;\n\nstruct pci_epc_ops {\n\tint (*write_header)(struct pci_epc *, u8, u8, struct pci_epf_header *);\n\tint (*set_bar)(struct pci_epc *, u8, u8, struct pci_epf_bar *);\n\tvoid (*clear_bar)(struct pci_epc *, u8, u8, struct pci_epf_bar *);\n\tu64 (*align_addr)(struct pci_epc *, u64, size_t *, size_t *);\n\tint (*map_addr)(struct pci_epc *, u8, u8, phys_addr_t, u64, size_t);\n\tvoid (*unmap_addr)(struct pci_epc *, u8, u8, phys_addr_t);\n\tint (*set_msi)(struct pci_epc *, u8, u8, u8);\n\tint (*get_msi)(struct pci_epc *, u8, u8);\n\tint (*set_msix)(struct pci_epc *, u8, u8, u16, enum pci_barno, u32);\n\tint (*get_msix)(struct pci_epc *, u8, u8);\n\tint (*raise_irq)(struct pci_epc *, u8, u8, unsigned int, u16);\n\tint (*map_msi_irq)(struct pci_epc *, u8, u8, phys_addr_t, u8, u32, u32 *, u32 *);\n\tint (*start)(struct pci_epc *);\n\tvoid (*stop)(struct pci_epc *);\n\tconst struct pci_epc_features * (*get_features)(struct pci_epc *, u8, u8);\n\tstruct module *owner;\n};\n\nstruct pci_epf_bar_submap;\n\nstruct pci_epf_bar {\n\tdma_addr_t phys_addr;\n\tvoid *addr;\n\tsize_t size;\n\tsize_t mem_size;\n\tenum pci_barno barno;\n\tint flags;\n\tunsigned int num_submap;\n\tstruct pci_epf_bar_submap *submap;\n};\n\nstruct pci_epf_driver;\n\nstruct pci_epf_device_id;\n\nstruct pci_epf_doorbell_msg;\n\nstruct pci_epf {\n\tstruct device dev;\n\tconst char *name;\n\tstruct pci_epf_header *header;\n\tstruct pci_epf_bar bar[6];\n\tu8 msi_interrupts;\n\tu16 msix_interrupts;\n\tu8 func_no;\n\tu8 vfunc_no;\n\tstruct pci_epc *epc;\n\tstruct pci_epf *epf_pf;\n\tstruct pci_epf_driver *driver;\n\tconst struct pci_epf_device_id *id;\n\tstruct list_head list;\n\tstruct mutex lock;\n\tstruct pci_epc *sec_epc;\n\tstruct list_head sec_epc_list;\n\tstruct pci_epf_bar sec_epc_bar[6];\n\tu8 sec_epc_func_no;\n\tstruct config_group *group;\n\tunsigned int is_bound;\n\tunsigned int is_vf;\n\tlong unsigned int vfunction_num_map;\n\tstruct list_head pci_vepf;\n\tconst struct pci_epc_event_ops *event_ops;\n\tstruct pci_epf_doorbell_msg *db_msg;\n\tu16 num_db;\n};\n\nstruct pci_epf_bar_submap {\n\tdma_addr_t phys_addr;\n\tsize_t size;\n};\n\nstruct pci_epf_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pci_epf_doorbell_msg {\n\tstruct msi_msg msg;\n\tint virq;\n};\n\nstruct pci_epf_ops;\n\nstruct pci_epf_driver {\n\tint (*probe)(struct pci_epf *, const struct pci_epf_device_id *);\n\tvoid (*remove)(struct pci_epf *);\n\tstruct device_driver driver;\n\tconst struct pci_epf_ops *ops;\n\tstruct module *owner;\n\tstruct list_head epf_group;\n\tconst struct pci_epf_device_id *id_table;\n};\n\nstruct pci_epf_group {\n\tstruct config_group group;\n\tstruct config_group primary_epc_group;\n\tstruct config_group secondary_epc_group;\n\tstruct pci_epf *epf;\n\tint index;\n};\n\nstruct pci_epf_header {\n\tu16 vendorid;\n\tu16 deviceid;\n\tu8 revid;\n\tu8 progif_code;\n\tu8 subclass_code;\n\tu8 baseclass_code;\n\tu8 cache_line_size;\n\tu16 subsys_vendor_id;\n\tu16 subsys_id;\n\tenum pci_interrupt_pin interrupt_pin;\n};\n\nstruct pci_epf_msix_tbl {\n\tu64 msg_addr;\n\tu32 msg_data;\n\tu32 vector_ctrl;\n};\n\nstruct pci_epf_ops {\n\tint (*bind)(struct pci_epf *);\n\tvoid (*unbind)(struct pci_epf *);\n\tstruct config_group * (*add_cfs)(struct pci_epf *, struct config_group *);\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_filp_private {\n\tenum pci_mmap_state mmap_state;\n\tint write_combine;\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tvoid (*hook)(struct pci_dev *);\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pcie_ptm_ops;\n\nstruct pci_ptm_debugfs {\n\tstruct dentry *debugfs;\n\tconst struct pcie_ptm_ops *ops;\n\tstruct mutex lock;\n\tvoid *pdata;\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct serial_private;\n\nstruct pciserial_board;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pci_sys_data {\n\tstruct list_head node;\n\tint busnr;\n\tlong: 32;\n\tu64 mem_offset;\n\tlong unsigned int io_offset;\n\tstruct pci_bus *bus;\n\tstruct list_head resources;\n\tstruct resource io_res;\n\tchar io_res_name[12];\n\tu8 (*swizzle)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid *private_data;\n};\n\nstruct pcie_bwctrl_data {\n\tstruct mutex set_speed_mutex;\n\tstruct thermal_cooling_device *cdev;\n};\n\nstruct pcie_cfg_data {\n\tconst int *offsets;\n\tconst enum pcie_soc_base soc_base;\n\tconst bool has_phy;\n\tconst u32 quirks;\n\tu8 num_inbound_wins;\n\tint (*perst_set)(struct brcm_pcie *, u32);\n\tint (*bridge_sw_init_set)(struct brcm_pcie *, u32);\n\tint (*post_setup)(struct brcm_pcie *);\n\tbool has_err_report;\n};\n\nstruct pcie_device {\n\tint irq;\n\tstruct pci_dev *port;\n\tu32 service;\n\tvoid *priv_data;\n\tstruct device device;\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tlong: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n};\n\nstruct pcie_pme_service_data {\n\tspinlock_t lock;\n\tstruct pcie_device *srv;\n\tstruct work_struct work;\n\tbool noirq;\n};\n\nstruct pcie_port_service_driver {\n\tconst char *name;\n\tint (*probe)(struct pcie_device *);\n\tvoid (*remove)(struct pcie_device *);\n\tint (*suspend)(struct pcie_device *);\n\tint (*resume_noirq)(struct pcie_device *);\n\tint (*resume)(struct pcie_device *);\n\tint (*runtime_suspend)(struct pcie_device *);\n\tint (*runtime_resume)(struct pcie_device *);\n\tint (*slot_reset)(struct pcie_device *);\n\tint port_type;\n\tu32 service;\n\tstruct device_driver driver;\n};\n\nstruct pcie_ptm_ops {\n\tint (*check_capability)(void *);\n\tint (*context_update_write)(void *, u8);\n\tint (*context_update_read)(void *, u8 *);\n\tint (*context_valid_write)(void *, bool);\n\tint (*context_valid_read)(void *, bool *);\n\tint (*local_clock_read)(void *, u64 *);\n\tint (*master_clock_read)(void *, u64 *);\n\tint (*t1_read)(void *, u64 *);\n\tint (*t2_read)(void *, u64 *);\n\tint (*t3_read)(void *, u64 *);\n\tint (*t4_read)(void *, u64 *);\n\tbool (*context_update_visible)(void *);\n\tbool (*context_valid_visible)(void *);\n\tbool (*local_clock_visible)(void *);\n\tbool (*master_clock_visible)(void *);\n\tbool (*t1_visible)(void *);\n\tbool (*t2_visible)(void *);\n\tbool (*t3_visible)(void *);\n\tbool (*t4_visible)(void *);\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[11];\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tlong: 32;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pcs_conf_type {\n\tconst char *name;\n\tenum pin_config_param param;\n};\n\nstruct pcs_conf_vals {\n\tenum pin_config_param param;\n\tunsigned int val;\n\tunsigned int enable;\n\tunsigned int disable;\n\tunsigned int mask;\n};\n\nstruct pcs_data {\n\tstruct pinctrl_pin_desc *pa;\n\tint cur;\n};\n\nstruct pcs_soc_data {\n\tunsigned int flags;\n\tint irq;\n\tunsigned int irq_enable_mask;\n\tunsigned int irq_status_mask;\n\tvoid (*rearm)(void);\n};\n\nstruct pcs_device {\n\tstruct resource *res;\n\tvoid *base;\n\tvoid *saved_vals;\n\tunsigned int size;\n\tstruct device *dev;\n\tstruct device_node *np;\n\tstruct pinctrl_dev *pctl;\n\tunsigned int flags;\n\tstruct property *missing_nr_pinctrl_cells;\n\tstruct pcs_soc_data socdata;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int width;\n\tunsigned int fmask;\n\tunsigned int fshift;\n\tunsigned int foff;\n\tunsigned int fmax;\n\tbool bits_per_mux;\n\tunsigned int bits_per_pin;\n\tstruct pcs_data pins;\n\tstruct list_head gpiofuncs;\n\tstruct list_head irqs;\n\tstruct irq_chip chip;\n\tstruct irq_domain *domain;\n\tstruct pinctrl_desc desc;\n\tunsigned int (*read)(void *);\n\tvoid (*write)(unsigned int, void *);\n};\n\nstruct pcs_func_vals {\n\tvoid *reg;\n\tunsigned int val;\n\tunsigned int mask;\n};\n\nstruct pcs_function {\n\tconst char *name;\n\tstruct pcs_func_vals *vals;\n\tunsigned int nvals;\n\tstruct pcs_conf_vals *conf;\n\tint nconfs;\n\tstruct list_head node;\n};\n\nstruct pcs_gpiofunc_range {\n\tunsigned int offset;\n\tunsigned int npins;\n\tunsigned int gpiofunc;\n\tstruct list_head node;\n};\n\nstruct pcs_interrupt {\n\tvoid *reg;\n\tirq_hw_number_t hwirq;\n\tunsigned int irq;\n\tstruct list_head node;\n};\n\nstruct pcs_pdata {\n\tint irq;\n\tvoid (*rearm)(void);\n};\n\nstruct pdata_init {\n\tconst char *compatible;\n\tvoid (*fn)(void);\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pdev_list_entry {\n\tstruct platform_device *pdev;\n\tstruct list_head node;\n};\n\nstruct pdiv_map {\n\tu8 pdiv;\n\tu8 hw_val;\n};\n\nstruct pegasus {\n\tstruct usb_device *usb;\n\tstruct usb_interface *intf;\n\tstruct net_device *net;\n\tstruct mii_if_info mii;\n\tunsigned int flags;\n\tunsigned int features;\n\tu32 msg_enable;\n\tu32 wolopts;\n\tint dev_index;\n\tint intr_interval;\n\tstruct tasklet_struct rx_tl;\n\tstruct delayed_work carrier_check;\n\tstruct urb *rx_urb;\n\tstruct urb *tx_urb;\n\tstruct urb *intr_urb;\n\tstruct sk_buff *rx_skb;\n\tint chip;\n\tunsigned char intr_buff[8];\n\t__u8 tx_buff[1536];\n\t__u8 eth_regs[4];\n\t__u8 phy;\n\t__u8 gpio_res;\n};\n\ntypedef struct pegasus pegasus_t;\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[47];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tshort int free_count;\n\tstruct list_head lists[12];\n\tlong: 32;\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[10];\n\ts8 stat_threshold;\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\nstruct percpu_free_defer {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\ntypedef struct percpu_rw_semaphore *class_percpu_read_t;\n\ntypedef struct percpu_rw_semaphore *class_percpu_write_t;\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[1];\n\tlong unsigned int offset[1];\n\tlocal_lock_t lock;\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu64 hw_id;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___3 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 spec: 2;\n\t__u64 new_type: 4;\n\t__u64 priv: 3;\n\t__u64 reserved: 31;\n};\n\nstruct perf_branch_stack {\n\tu64 nr;\n\tu64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct perf_event_mmap_page;\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tstruct work_struct work;\n\tint page_order;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\trefcount_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tstruct mutex aux_mutex;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\trefcount_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tint aux_in_pause_resume;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct unwind_stacktrace;\n\nstruct perf_callchain_deferred_event {\n\tstruct unwind_stacktrace *trace;\n\tlong: 32;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 cookie;\n\t\tu64 nr;\n\t\tu64 ips[0];\n\t} event;\n};\n\nstruct perf_callchain_entry {\n\tu64 nr;\n\tu64 ip[0];\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tlong: 32;\n\tu64 index;\n};\n\nstruct perf_time_ctx {\n\tu64 time;\n\tu64 stamp;\n\tu64 offset;\n};\n\nstruct perf_event_context {\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head pmu_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tint nr_events;\n\tint nr_user;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tstruct perf_event_context *parent_ctx;\n\tlong: 32;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tstruct callback_head callback_head;\n\tlocal_t nr_no_switch_fast;\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint online;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_event_pmu_context {\n\tstruct pmu *pmu;\n\tstruct perf_event_context *ctx;\n\tstruct list_head pmu_ctx_entry;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tunsigned int embedded: 1;\n\tunsigned int nr_events;\n\tunsigned int nr_cgroups;\n\tunsigned int nr_freq;\n\tatomic_t refcount;\n\tstruct callback_head callback_head;\n\tint rotate_necessary;\n};\n\nstruct perf_cpu_pmu_context {\n\tstruct perf_event_pmu_context epc;\n\tstruct perf_event_pmu_context *task_epc;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint active_oncpu;\n\tint exclusive;\n\tint pmu_disable_count;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n\tlong: 32;\n};\n\nstruct perf_ctx_data {\n\tstruct callback_head callback_head;\n\trefcount_t refcount;\n\tint global;\n\tstruct kmem_cache *ctx_cache;\n\tvoid *data;\n};\n\nstruct scmi_perf_domain_info {\n\tchar name[64];\n\tbool set_perf;\n};\n\nstruct scmi_opp {\n\tu32 perf;\n\tu32 power;\n\tu32 trans_latency_us;\n\tu32 indicative_freq;\n\tu32 level_index;\n\tstruct hlist_node hash;\n};\n\nstruct scmi_fc_info;\n\nstruct perf_dom_info {\n\tu32 id;\n\tbool set_limits;\n\tbool perf_limit_notify;\n\tbool perf_level_notify;\n\tbool perf_fastchannels;\n\tbool level_indexing_mode;\n\tu32 opp_count;\n\tu32 rate_limit_us;\n\tu32 sustained_freq_khz;\n\tu32 sustained_perf_level;\n\tlong unsigned int mult_factor;\n\tstruct scmi_perf_domain_info info;\n\tstruct scmi_opp opp[64];\n\tstruct scmi_fc_info *fc_info;\n\tstruct xarray opps_by_idx;\n\tstruct xarray opps_by_lvl;\n\tstruct hlist_head opps_by_freq[64];\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 text_poke: 1;\n\t__u64 build_id: 1;\n\t__u64 inherit_thread: 1;\n\t__u64 remove_on_exec: 1;\n\t__u64 sigtrap: 1;\n\t__u64 defer_callchain: 1;\n\t__u64 defer_output: 1;\n\t__u64 __reserved_1: 24;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\tunion {\n\t\t__u32 aux_action;\n\t\tstruct {\n\t\t\t__u32 aux_start_paused: 1;\n\t\t\t__u32 aux_pause: 1;\n\t\t\t__u32 aux_resume: 1;\n\t\t\t__u32 __reserved_3: 29;\n\t\t};\n\t};\n\t__u64 sig_data;\n\t__u64 config3;\n\t__u64 config4;\n};\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tlong: 32;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tunsigned int group_generation;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlong: 32;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tstruct perf_event_pmu_context *pmu_ctx;\n\tatomic_long_t refcount;\n\tlong: 32;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\trefcount_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tunsigned int pending_wakeup;\n\tunsigned int pending_kill;\n\tunsigned int pending_disable;\n\tlong unsigned int pending_addr;\n\tstruct irq_work pending_irq;\n\tstruct irq_work pending_disable_irq;\n\tstruct callback_head pending_task;\n\tunsigned int pending_work;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tlong: 32;\n\tu64 id;\n\tatomic64_t lost_samples;\n\tu64 (*clock)(void);\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tstruct bpf_prog *prog;\n\tu64 bpf_cookie;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tstruct list_head sb_list;\n\tstruct list_head pmu_list;\n\tu32 orig_type;\n\tlong: 32;\n};\n\nstruct perf_event_min_heap {\n\tsize_t nr;\n\tsize_t size;\n\tstruct perf_event **data;\n\tstruct perf_event *preallocated[0];\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_user_time_short: 1;\n\t\t\t__u64 cap_____res: 58;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u32 __reserved_1;\n\t__u64 time_cycles;\n\t__u64 time_mask;\n\t__u8 __reserved[928];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tlong: 32;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tu8 build_id[20];\n\tu32 build_id_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tlong: 32;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tunion {\n\t\tu64 flags;\n\t\tu64 aux_flags;\n\t\tstruct {\n\t\t\tu64 skip_read: 1;\n\t\t\tlong: 32;\n\t\t};\n\t};\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n\tlong: 32;\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n};\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_text_poke_event {\n\tconst void *old_bytes;\n\tconst void *new_bytes;\n\tsize_t pad;\n\tu16 old_len;\n\tu16 new_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t} event_id;\n};\n\nstruct peri_clk_data {\n\tstruct bcm_clk_policy policy;\n\tstruct bcm_clk_gate gate;\n\tstruct bcm_clk_hyst hyst;\n\tstruct bcm_clk_trig pre_trig;\n\tlong: 32;\n\tstruct bcm_clk_div pre_div;\n\tstruct bcm_clk_trig trig;\n\tlong: 32;\n\tstruct bcm_clk_div div;\n\tstruct bcm_clk_sel sel;\n\tconst char *clocks[0];\n};\n\nstruct pericom8250 {\n\tvoid *virt;\n\tunsigned int nr;\n\tint line[0];\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct persistent_ram_buffer {\n\tuint32_t sig;\n\tatomic_t start;\n\tatomic_t size;\n\tuint8_t data[0];\n};\n\nstruct persistent_ram_ecc_info {\n\tint block_size;\n\tint ecc_size;\n\tint symsize;\n\tint poly;\n\tuint16_t *par;\n};\n\nstruct rs_control;\n\nstruct persistent_ram_zone {\n\tphys_addr_t paddr;\n\tsize_t size;\n\tvoid *vaddr;\n\tchar *label;\n\tenum pstore_type_id type;\n\tu32 flags;\n\traw_spinlock_t buffer_lock;\n\tstruct persistent_ram_buffer *buffer;\n\tsize_t buffer_size;\n\tchar *par_buffer;\n\tchar *par_header;\n\tstruct rs_control *rs_decoder;\n\tint corrected_bytes;\n\tint bad_blocks;\n\tstruct persistent_ram_ecc_info ecc_info;\n\tchar *old_log;\n\tsize_t old_log_size;\n};\n\nstruct pf_desc {\n\tu32 pseudoflavor;\n\tu32 qop;\n\tu32 service;\n\tchar *name;\n\tchar *auth_domain_name;\n\tstruct auth_domain *domain;\n\tbool datatouch;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[4];\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int *pageblock_flags;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tlong unsigned int cma_pages;\n\tconst char *name;\n\tlong unsigned int nr_isolate_pageblock;\n\tint initialized;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[12];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 32;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[10];\n\tatomic_long_t vm_numa_event[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[5];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[4];\n\tstruct zonelist node_zonelists[1];\n\tint nr_zones;\n\tstruct page *node_mem_map;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tstruct cacheline_padding _pad1_;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[47];\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tu32 max_link_rate;\n\tenum phy_mode mode;\n};\n\nstruct phy {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tstruct lock_class_key lockdep_key;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n\tstruct dentry *debugfs;\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nstruct phy_axg_mipi_pcie_analog_priv {\n\tstruct phy *phy;\n\tstruct regmap *regmap;\n\tbool dsi_configured;\n\tbool dsi_enabled;\n\tbool powered;\n\tstruct phy_configure_opts_mipi_dphy config;\n};\n\nstruct phy_axg_pcie_priv {\n\tstruct phy *phy;\n\tstruct phy *analog;\n\tstruct regmap *regmap;\n\tstruct reset_control *reset;\n};\n\nstruct phy_berlin_desc {\n\tstruct phy *phy;\n\tu32 power_bit;\n\tunsigned int index;\n};\n\nstruct phy_berlin_priv {\n\tvoid *base;\n\tspinlock_t lock;\n\tstruct clk *clk;\n\tstruct phy_berlin_desc **phys;\n\tunsigned int nphys;\n\tu32 phy_base;\n};\n\nstruct phy_berlin_usb_priv {\n\tvoid *base;\n\tstruct reset_control *rst_ctrl;\n\tu32 pll_divider;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phy_companion {\n\tint (*set_vbus)(struct phy_companion *, bool);\n\tint (*start_srp)(struct phy_companion *);\n};\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_lvds {\n\tunsigned int bits_per_lane_and_dclk_cycle;\n\tlong unsigned int differential_clk_rate;\n\tunsigned int lanes;\n\tbool is_slave;\n};\n\nstruct phy_configure_opts_hdmi {\n\tunsigned int bpc;\n\tlong: 32;\n\tunion {\n\t\tlong long unsigned int tmds_char_rate;\n\t\tstruct {\n\t\t\tu8 rate_per_lane;\n\t\t\tu8 lanes;\n\t\t} frl;\n\t};\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n\tstruct phy_configure_opts_lvds lvds;\n\tstruct phy_configure_opts_hdmi hdmi;\n};\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[2];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[4];\n\tlong unsigned int advertising[4];\n\tlong unsigned int lp_advertising[4];\n\tlong unsigned int adv_old[4];\n\tlong unsigned int supported_eee[4];\n\tlong unsigned int advertising_eee[4];\n\tlong unsigned int eee_disabled_modes[4];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[2];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct phy_package_shared *shared;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct phy_devm {\n\tstruct usb_phy *phy;\n\tstruct notifier_block *nb;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct phy_g12a_mipi_dphy_analog_priv {\n\tstruct phy *phy;\n\tstruct regmap *regmap;\n\tstruct phy_configure_opts_mipi_dphy config;\n};\n\nstruct phy_g12a_usb3_pcie_priv {\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_cr;\n\tstruct clk *clk_ref;\n\tstruct reset_control *reset;\n\tstruct phy *phy;\n\tunsigned int mode;\n};\n\nstruct phy_gmii_sel_priv;\n\nstruct phy_gmii_sel_phy_priv {\n\tstruct phy_gmii_sel_priv *priv;\n\tu32 id;\n\tstruct phy *if_phy;\n\tint rmii_clock_external;\n\tint phy_if_mode;\n\tstruct regmap_field *fields[4];\n};\n\nstruct phy_gmii_sel_soc_data;\n\nstruct phy_provider;\n\nstruct phy_gmii_sel_priv {\n\tstruct device *dev;\n\tconst struct phy_gmii_sel_soc_data *soc_data;\n\tstruct regmap *regmap;\n\tstruct phy_provider *phy_provider;\n\tstruct phy_gmii_sel_phy_priv *if_phys;\n\tu32 num_ports;\n\tu32 reg_offset;\n\tu32 qsgmii_main_ports;\n\tbool no_offset;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct phy_gmii_sel_soc_data {\n\tu32 num_ports;\n\tu32 features;\n\tconst struct reg_field (*regfields)[4];\n\tbool use_of_data;\n\tu64 extra_modes;\n\tu32 num_qsgmii_main_ports;\n\tlong: 32;\n};\n\nstruct phy_lane_info {\n\tvoid *phy_base;\n\tu8 lane_mapping;\n\tu8 phy_devs;\n\tu8 tx_atten;\n};\n\nstruct phy_led {\n\tstruct list_head list;\n\tstruct phy_device *phydev;\n\tstruct led_classdev led_cdev;\n\tu8 index;\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nstruct phy_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct phy *phy;\n};\n\nstruct phy_meson8b_usb2_match_data {\n\tbool host_enable_aca;\n};\n\nstruct phy_meson8b_usb2_priv {\n\tstruct regmap *regmap;\n\tenum usb_dr_mode dr_mode;\n\tstruct clk *clk_usb_general;\n\tstruct clk *clk_usb;\n\tstruct reset_control *reset;\n\tconst struct phy_meson8b_usb2_match_data *match;\n};\n\nstruct phy_meson_axg_mipi_dphy_priv {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tstruct phy *analog;\n\tstruct phy_configure_opts_mipi_dphy config;\n};\n\nstruct phy_meson_g12a_usb2_priv {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tint soc_id;\n};\n\nstruct phy_meson_gxl_usb2_priv {\n\tstruct regmap *regmap;\n\tenum phy_mode mode;\n\tint is_enabled;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n};\n\nunion phy_notify {\n\tenum phy_ufs_state ufs_state;\n};\n\nstruct phy_ops {\n\tint (*init)(struct phy *);\n\tint (*exit)(struct phy *);\n\tint (*power_on)(struct phy *);\n\tint (*power_off)(struct phy *);\n\tint (*set_mode)(struct phy *, enum phy_mode, int);\n\tint (*set_media)(struct phy *, enum phy_media);\n\tint (*set_speed)(struct phy *, int);\n\tint (*configure)(struct phy *, union phy_configure_opts *);\n\tint (*validate)(struct phy *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy *);\n\tint (*calibrate)(struct phy *);\n\tint (*connect)(struct phy *, int);\n\tint (*disconnect)(struct phy *, int);\n\tint (*notify_phystate)(struct phy *, union phy_notify);\n\tvoid (*release)(struct phy *);\n\tstruct module *owner;\n};\n\nstruct phy_package_shared {\n\tu8 base_addr;\n\tstruct device_node *np;\n\trefcount_t refcnt;\n\tlong unsigned int flags;\n\tsize_t priv_size;\n\tvoid *priv;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_port_ops;\n\nstruct phy_port {\n\tstruct list_head head;\n\tenum phy_port_parent parent_type;\n\tunion {\n\t\tstruct phy_device *phy;\n\t};\n\tconst struct phy_port_ops *ops;\n\tint pairs;\n\tlong unsigned int mediums;\n\tlong unsigned int supported[4];\n\tlong unsigned int interfaces[2];\n\tunsigned int not_described: 1;\n\tunsigned int active: 1;\n\tunsigned int is_mii: 1;\n\tunsigned int is_sfp: 1;\n};\n\nstruct phy_port_ops {\n\tvoid (*link_up)(struct phy_port *);\n\tvoid (*link_down)(struct phy_port *);\n\tint (*configure_mii)(struct phy_port *, bool, phy_interface_t);\n};\n\nstruct phy_provider {\n\tstruct device *dev;\n\tstruct device_node *children;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct phy * (*of_xlate)(struct device *, const struct of_phandle_args *);\n};\n\nstruct phy_reg {\n\tu16 reg;\n\tu16 val;\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phylib_stubs {\n\tint (*hwtstamp_get)(struct phy_device *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct phy_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_ext_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n};\n\nstruct phylink_link_state {\n\tlong unsigned int advertising[4];\n\tlong unsigned int lp_advertising[4];\n\tphy_interface_t interface;\n\tint speed;\n\tint duplex;\n\tint pause;\n\tint rate_matching;\n\tunsigned int link: 1;\n\tunsigned int an_complete: 1;\n};\n\nstruct phylink {\n\tstruct net_device *netdev;\n\tconst struct phylink_mac_ops *mac_ops;\n\tstruct phylink_config *config;\n\tstruct phylink_pcs *pcs;\n\tstruct device *dev;\n\tunsigned int old_link_state: 1;\n\tlong unsigned int phylink_disable_state;\n\tstruct phy_device *phydev;\n\tphy_interface_t link_interface;\n\tu8 cfg_link_an_mode;\n\tu8 req_link_an_mode;\n\tu8 act_link_an_mode;\n\tu8 link_port;\n\tlong unsigned int supported[4];\n\tlong unsigned int supported_lpi[4];\n\tstruct phylink_link_state link_config;\n\tphy_interface_t cur_interface;\n\tstruct gpio_desc *link_gpio;\n\tunsigned int link_irq;\n\tstruct timer_list link_poll;\n\tstruct mutex state_mutex;\n\tstruct mutex phydev_mutex;\n\tstruct phylink_link_state phy_state;\n\tunsigned int phy_ib_mode;\n\tstruct work_struct resolve;\n\tunsigned int pcs_neg_mode;\n\tunsigned int pcs_state;\n\tbool link_failed;\n\tbool suspend_link_up;\n\tbool force_major_config;\n\tbool major_config_failed;\n\tbool mac_supports_eee_ops;\n\tbool mac_supports_eee;\n\tbool phy_enable_tx_lpi;\n\tbool mac_enable_tx_lpi;\n\tbool mac_tx_clk_stop;\n\tu32 mac_tx_lpi_timer;\n\tu8 mac_rx_clk_stop_blocked;\n\tstruct sfp_bus *sfp_bus;\n\tbool sfp_may_have_phy;\n\tlong unsigned int sfp_interfaces[2];\n\tlong unsigned int sfp_support[4];\n\tu8 sfp_port;\n\tstruct eee_config eee_cfg;\n\tu32 wolopts_mac;\n\tu8 wol_sopass[6];\n};\n\nstruct phylink_mac_ops {\n\tlong unsigned int (*mac_get_caps)(struct phylink_config *, phy_interface_t);\n\tstruct phylink_pcs * (*mac_select_pcs)(struct phylink_config *, phy_interface_t);\n\tint (*mac_prepare)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_config)(struct phylink_config *, unsigned int, const struct phylink_link_state *);\n\tint (*mac_finish)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_down)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_up)(struct phylink_config *, struct phy_device *, unsigned int, phy_interface_t, int, int, bool, bool);\n\tvoid (*mac_disable_tx_lpi)(struct phylink_config *);\n\tint (*mac_enable_tx_lpi)(struct phylink_config *, u32, bool);\n\tint (*mac_wol_set)(struct phylink_config *, u32, const u8 *);\n};\n\nstruct phylink_pcs_ops {\n\tint (*pcs_validate)(struct phylink_pcs *, long unsigned int *, const struct phylink_link_state *);\n\tunsigned int (*pcs_inband_caps)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_enable)(struct phylink_pcs *);\n\tvoid (*pcs_disable)(struct phylink_pcs *);\n\tvoid (*pcs_pre_config)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_post_config)(struct phylink_pcs *, phy_interface_t);\n\tvoid (*pcs_get_state)(struct phylink_pcs *, unsigned int, struct phylink_link_state *);\n\tint (*pcs_config)(struct phylink_pcs *, unsigned int, phy_interface_t, const long unsigned int *, bool);\n\tvoid (*pcs_an_restart)(struct phylink_pcs *);\n\tvoid (*pcs_link_up)(struct phylink_pcs *, unsigned int, phy_interface_t, int, int);\n\tvoid (*pcs_disable_eee)(struct phylink_pcs *);\n\tvoid (*pcs_enable_eee)(struct phylink_pcs *);\n\tint (*pcs_pre_init)(struct phylink_pcs *);\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct physmap_flash_data {\n\tunsigned int width;\n\tint (*init)(struct platform_device *);\n\tvoid (*exit)(struct platform_device *);\n\tvoid (*set_vpp)(struct platform_device *, int);\n\tunsigned int nr_parts;\n\tunsigned int pfow_base;\n\tchar *probe_type;\n\tstruct mtd_partition *parts;\n\tconst char * const *part_probe_types;\n};\n\nstruct physmap_flash_info {\n\tunsigned int nmaps;\n\tstruct mtd_info **mtds;\n\tstruct mtd_info *cmtd;\n\tstruct map_info *maps;\n\tspinlock_t vpp_lock;\n\tint vpp_refcnt;\n\tconst char *probe_type;\n\tconst char * const *part_types;\n\tunsigned int nparts;\n\tconst struct mtd_partition *parts;\n\tstruct gpio_descs *gpios;\n\tunsigned int gpio_values;\n\tunsigned int win_order;\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tlong: 32;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t\tlong: 32;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t\tlong: 32;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pin_config {\n\tconst char *property;\n\tenum pincfg_type param;\n};\n\nstruct pin_config_item {\n\tconst enum pin_config_param param;\n\tconst char * const display;\n\tconst char * const format;\n\tbool has_arg;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinctrl_setting_mux;\n\nstruct pin_desc {\n\tstruct pinctrl_dev *pctldev;\n\tconst char *name;\n\tbool dynamic_name;\n\tvoid *drv_data;\n\tunsigned int mux_usecount;\n\tconst char *mux_owner;\n\tconst struct pinctrl_setting_mux *mux_setting;\n\tconst char *gpio_owner;\n\tstruct mutex mux_lock;\n};\n\nstruct pinconf_generic_params {\n\tconst char * const property;\n\tenum pin_config_param param;\n\tu32 default_value;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinconf_ops {\n\tbool is_generic;\n\tint (*pin_config_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tint (*pin_config_group_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_group_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tvoid (*pin_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_group_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, long unsigned int);\n};\n\nstruct pinctrl {\n\tstruct list_head node;\n\tstruct device *dev;\n\tstruct list_head states;\n\tstruct pinctrl_state *state;\n\tstruct list_head dt_maps;\n\tstruct kref users;\n};\n\nstruct pinctrl_dev {\n\tstruct list_head node;\n\tconst struct pinctrl_desc *desc;\n\tstruct xarray pin_desc_tree;\n\tstruct xarray pin_group_tree;\n\tunsigned int num_groups;\n\tstruct xarray pin_function_tree;\n\tunsigned int num_functions;\n\tstruct list_head gpio_ranges;\n\tstruct device *dev;\n\tstruct module *owner;\n\tvoid *driver_data;\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *hog_default;\n\tstruct pinctrl_state *hog_sleep;\n\tstruct mutex mutex;\n\tstruct dentry *device_root;\n};\n\nstruct pinctrl_map;\n\nstruct pinctrl_dt_map {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_map *map;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_map_mux {\n\tconst char *group;\n\tconst char *function;\n};\n\nstruct pinctrl_map_configs {\n\tconst char *group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_map {\n\tconst char *dev_name;\n\tconst char *name;\n\tenum pinctrl_map_type type;\n\tconst char *ctrl_dev_name;\n\tunion {\n\t\tstruct pinctrl_map_mux mux;\n\t\tstruct pinctrl_map_configs configs;\n\t} data;\n};\n\nstruct pinctrl_maps {\n\tstruct list_head node;\n\tconst struct pinctrl_map *maps;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_ops {\n\tint (*get_groups_count)(struct pinctrl_dev *);\n\tconst char * (*get_group_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_group_pins)(struct pinctrl_dev *, unsigned int, const unsigned int **, unsigned int *);\n\tvoid (*pin_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tint (*dt_node_to_map)(struct pinctrl_dev *, struct device_node *, struct pinctrl_map **, unsigned int *);\n\tvoid (*dt_free_map)(struct pinctrl_dev *, struct pinctrl_map *, unsigned int);\n};\n\nstruct pinctrl_setting_mux {\n\tunsigned int group;\n\tunsigned int func;\n};\n\nstruct pinctrl_setting_configs {\n\tunsigned int group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_setting {\n\tstruct list_head node;\n\tenum pinctrl_map_type type;\n\tstruct pinctrl_dev *pctldev;\n\tconst char *dev_name;\n\tunion {\n\t\tstruct pinctrl_setting_mux mux;\n\t\tstruct pinctrl_setting_configs configs;\n\t} data;\n};\n\nstruct pinctrl_state {\n\tstruct list_head node;\n\tconst char *name;\n\tstruct list_head settings;\n};\n\nstruct pinfunction {\n\tconst char *name;\n\tconst char * const *groups;\n\tsize_t ngroups;\n\tlong unsigned int flags;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinmux_bias_reg {\n\tu32 puen;\n\tu32 pud;\n\tconst u16 pins[32];\n};\n\nstruct pinmux_cfg_reg {\n\tu32 reg;\n\tu8 reg_width;\n\tu8 field_width;\n\tconst u16 *enum_ids;\n\tconst s8 *var_field_width;\n};\n\nstruct pinmux_data_reg {\n\tu32 reg;\n\tu8 reg_width;\n\tconst u16 *enum_ids;\n};\n\nstruct pinmux_drive_reg_field {\n\tu16 pin;\n\tu8 offset;\n\tu8 size;\n};\n\nstruct pinmux_drive_reg {\n\tu32 reg;\n\tconst struct pinmux_drive_reg_field fields[10];\n};\n\nstruct pinmux_ioctrl_reg {\n\tu32 reg;\n};\n\nstruct pinmux_irq {\n\tconst short int *gpios;\n};\n\nstruct pinmux_ops {\n\tint (*request)(struct pinctrl_dev *, unsigned int);\n\tint (*free)(struct pinctrl_dev *, unsigned int);\n\tint (*get_functions_count)(struct pinctrl_dev *);\n\tconst char * (*get_function_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_function_groups)(struct pinctrl_dev *, unsigned int, const char * const **, unsigned int *);\n\tbool (*function_is_gpio)(struct pinctrl_dev *, unsigned int);\n\tint (*set_mux)(struct pinctrl_dev *, unsigned int, unsigned int);\n\tint (*gpio_request_enable)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tvoid (*gpio_disable_free)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tint (*gpio_set_direction)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int, bool);\n\tbool strict;\n};\n\nstruct pinmux_range {\n\tu16 begin;\n\tu16 end;\n\tu16 force;\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe3_settings {\n\tu8 ana_interface;\n\tu8 ana_losd;\n\tu8 dig_fastlock;\n\tu8 dig_lbw;\n\tu8 dig_stepcnt;\n\tu8 dig_stl;\n\tu8 dig_thr;\n\tu8 dig_thr_mode;\n\tu8 dig_2ndo_sdm_mode;\n\tu8 dig_hs_rate;\n\tu8 dig_ovrd_hs_rate;\n\tu8 dll_trim_sel;\n\tu8 dll_phint_rate;\n\tu8 eq_lev;\n\tu8 eq_ftc;\n\tu8 eq_ctl;\n\tu8 eq_ovrd_lev;\n\tu8 eq_ovrd_ftc;\n};\n\nstruct pipe3_dpll_map;\n\nstruct pipe3_data {\n\tenum pipe3_mode mode;\n\tstruct pipe3_dpll_map *dpll_map;\n\tstruct pipe3_settings settings;\n};\n\nstruct pipe3_dpll_params {\n\tu16 m;\n\tu8 n;\n\tu8 freq: 3;\n\tu8 sd;\n\tu32 mf;\n};\n\nstruct pipe3_dpll_map {\n\tlong unsigned int rate;\n\tstruct pipe3_dpll_params params;\n};\n\nstruct pipe_buffer;\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct pipe_wait {\n\tstruct trace_iterator *iter;\n\tint wait_index;\n};\n\nstruct pit_data {\n\tstruct clock_event_device clkevt;\n\tstruct clocksource clksrc;\n\tvoid *base;\n\tu32 cycle;\n\tu32 cnt;\n\tunsigned int irq;\n\tstruct clk *mck;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct pixel_format {\n\tunsigned char bits_per_pixel;\n\tbool indexed;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} alpha;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} red;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} green;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} blue;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char offset;\n\t\t\tunsigned char length;\n\t\t} index;\n\t};\n};\n\nstruct pkcs1pad_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct pkcs1pad_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n};\n\nstruct pkcs1pad_request {\n\tstruct scatterlist in_sg[2];\n\tstruct scatterlist out_sg[1];\n\tuint8_t *in_buf;\n\tuint8_t *out_buf;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct akcipher_request child_req;\n};\n\nstruct x509_certificate;\n\nstruct pkcs7_signed_info;\n\nstruct pkcs7_message {\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate *crl;\n\tstruct pkcs7_signed_info *signed_infos;\n\tu8 version;\n\tbool have_authattrs;\n\tenum OID data_type;\n\tsize_t data_len;\n\tsize_t data_hdrlen;\n\tconst void *data;\n};\n\nstruct pkcs7_parse_context {\n\tstruct pkcs7_message *msg;\n\tstruct pkcs7_signed_info *sinfo;\n\tstruct pkcs7_signed_info **ppsinfo;\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate **ppcerts;\n\tlong unsigned int data;\n\tenum OID last_oid;\n\tunsigned int x509_index;\n\tunsigned int sinfo_index;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_skid;\n\tunsigned int raw_skid_size;\n\tbool expect_skid;\n};\n\nstruct pkcs7_signed_info {\n\tstruct pkcs7_signed_info *next;\n\tstruct x509_certificate *signer;\n\tunsigned int index;\n\tbool unsupported_crypto;\n\tbool blacklisted;\n\tconst void *msgdigest;\n\tunsigned int msgdigest_len;\n\tunsigned int authattrs_len;\n\tconst void *authattrs;\n\tlong unsigned int aa_set;\n\tlong: 32;\n\ttime64_t signing_time;\n\tstruct public_key_signature *sig;\n\tlong: 32;\n};\n\nstruct pl011_dmabuf {\n\tdma_addr_t dma;\n\tsize_t len;\n\tchar *buf;\n};\n\nstruct pl011_dmarx_data {\n\tstruct dma_chan *chan;\n\tstruct completion complete;\n\tbool use_buf_b;\n\tstruct pl011_dmabuf dbuf_a;\n\tstruct pl011_dmabuf dbuf_b;\n\tdma_cookie_t cookie;\n\tbool running;\n\tstruct timer_list timer;\n\tunsigned int last_residue;\n\tlong unsigned int last_jiffies;\n\tbool auto_poll_rate;\n\tunsigned int poll_rate;\n\tunsigned int poll_timeout;\n};\n\nstruct pl011_dmatx_data {\n\tstruct dma_chan *chan;\n\tdma_addr_t dma;\n\tsize_t len;\n\tchar *buf;\n\tbool queued;\n};\n\nstruct vendor_data;\n\nstruct pl022_ssp_controller;\n\nstruct pl022 {\n\tstruct amba_device *adev;\n\tstruct vendor_data *vendor;\n\tresource_size_t phybase;\n\tvoid *virtbase;\n\tstruct clk *clk;\n\tstruct spi_controller *host;\n\tstruct pl022_ssp_controller *host_info;\n\tstruct spi_transfer *cur_transfer;\n\tstruct chip_data___2 *cur_chip;\n\tvoid *tx;\n\tvoid *tx_end;\n\tvoid *rx;\n\tvoid *rx_end;\n\tenum ssp_reading read;\n\tenum ssp_writing write;\n\tu32 exp_fifo_level;\n\tenum ssp_rx_level_trig rx_lev_trig;\n\tenum ssp_tx_level_trig tx_lev_trig;\n\tstruct dma_chan *dma_rx_channel;\n\tstruct dma_chan *dma_tx_channel;\n\tstruct sg_table sgt_rx;\n\tstruct sg_table sgt_tx;\n\tchar *dummypage;\n\tbool dma_running;\n\tint cur_cs;\n};\n\nstruct ssp_clock_params {\n\tu8 cpsdvsr;\n\tu8 scr;\n};\n\nstruct pl022_config_chip {\n\tenum ssp_interface iface;\n\tenum ssp_hierarchy hierarchy;\n\tbool slave_tx_disable;\n\tstruct ssp_clock_params clk_freq;\n\tenum ssp_mode com_mode;\n\tenum ssp_rx_level_trig rx_lev_trig;\n\tenum ssp_tx_level_trig tx_lev_trig;\n\tenum ssp_microwire_ctrl_len ctrl_len;\n\tenum ssp_microwire_wait_state wait_state;\n\tenum ssp_duplex duplex;\n\tenum ssp_clkdelay clkdelay;\n};\n\nstruct pl022_ssp_controller {\n\tu16 bus_id;\n\tu8 enable_dma: 1;\n\tdma_filter_fn dma_filter;\n\tvoid *dma_rx_param;\n\tvoid *dma_tx_param;\n\tint autosuspend_delay;\n\tbool rt;\n};\n\nstruct pl031_vendor_data;\n\nstruct pl031_local {\n\tstruct pl031_vendor_data *vendor;\n\tstruct rtc_device *rtc;\n\tvoid *base;\n};\n\nstruct rtc_time;\n\nstruct rtc_wkalrm;\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct pl031_vendor_data {\n\tstruct rtc_class_ops ops;\n\tbool clockwatch;\n\tbool st_weekday;\n\tlong unsigned int irqflags;\n\tlong: 32;\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n};\n\nstruct pl061_context_save_regs {\n\tu8 gpio_data;\n\tu8 gpio_dir;\n\tu8 gpio_is;\n\tu8 gpio_ibe;\n\tu8 gpio_iev;\n\tu8 gpio_ie;\n};\n\nstruct pl061 {\n\traw_spinlock_t lock;\n\tvoid *base;\n\tstruct gpio_chip gc;\n\tint parent_irq;\n\tstruct pl061_context_save_regs csave_regs;\n};\n\nstruct pl330_config {\n\tu32 periph_id;\n\tunsigned int mode;\n\tunsigned int data_bus_width: 10;\n\tunsigned int data_buf_dep: 11;\n\tunsigned int num_chan: 4;\n\tunsigned int num_peri: 6;\n\tu32 peri_ns;\n\tunsigned int num_events: 6;\n\tu32 irq_ns;\n};\n\nstruct pl330_dmac {\n\tstruct dma_device ddma;\n\tstruct list_head desc_pool;\n\tspinlock_t pool_lock;\n\tunsigned int mcbufsz;\n\tvoid *base;\n\tstruct pl330_config pcfg;\n\tspinlock_t lock;\n\tint events[32];\n\tdma_addr_t mcode_bus;\n\tvoid *mcode_cpu;\n\tstruct pl330_thread *channels;\n\tstruct pl330_thread *manager;\n\tstruct tasklet_struct tasks;\n\tstruct _pl330_tbd dmac_tbd;\n\tenum pl330_dmac_state state;\n\tstruct list_head req_done;\n\tunsigned int num_peripherals;\n\tstruct dma_pl330_chan *peripherals;\n\tint quirks;\n\tstruct reset_control *rstc;\n\tstruct reset_control *rstc_ocp;\n};\n\nstruct pl330_of_quirks {\n\tchar *quirk;\n\tint id;\n};\n\nstruct pl330_thread {\n\tu8 id;\n\tint ev;\n\tbool free;\n\tstruct pl330_dmac *dmac;\n\tstruct _pl330_req req[2];\n\tunsigned int lstenq;\n\tint req_running;\n};\n\nstruct pl353_smc_data {\n\tstruct clk *memclk;\n\tstruct clk *aclk;\n};\n\nstruct pl35x_nand {\n\tstruct list_head node;\n\tstruct nand_chip chip;\n\tunsigned int cs;\n\tunsigned int addr_cycles;\n\tu32 ecc_cfg;\n\tu32 timings;\n};\n\nstruct pl35x_nand_timings {\n\tunsigned int t_rc: 4;\n\tunsigned int t_wc: 4;\n\tunsigned int t_rea: 3;\n\tunsigned int t_wp: 3;\n\tunsigned int t_clr: 3;\n\tunsigned int t_ar: 3;\n\tunsigned int t_rr: 4;\n\tunsigned int rsvd: 8;\n};\n\nstruct pl35x_nandc {\n\tstruct device *dev;\n\tvoid *conf_regs;\n\tvoid *io_regs;\n\tstruct nand_controller controller;\n\tstruct list_head chips;\n\tstruct nand_chip *selected_chip;\n\tlong unsigned int assigned_cs;\n\tu8 *ecc_buf;\n};\n\nstruct plat_sci_port_ops;\n\nstruct plat_sci_port {\n\tunsigned int type;\n\tlong: 32;\n\tupf_t flags;\n\tunsigned int sampling_rate;\n\tunsigned int scscr;\n\tunsigned char regtype;\n\tstruct plat_sci_port_ops *ops;\n};\n\nstruct plat_sci_port_ops {\n\tvoid (*init_pins)(struct uart_port *, unsigned int);\n};\n\nstruct plat_sci_reg {\n\tu8 offset;\n\tu8 size;\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tunsigned int uartclk;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tunsigned int type;\n\tupf_t flags;\n\tu16 bugs;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tlong: 32;\n};\n\nstruct stmmac_rxq_cfg {\n\tu8 mode_to_use;\n\tu32 chan;\n\tu8 pkt_route;\n\tbool use_prio;\n\tu32 prio;\n};\n\nstruct stmmac_txq_cfg {\n\tu32 weight;\n\tbool coe_unsupported;\n\tu8 mode_to_use;\n\tu32 send_slope;\n\tu32 idle_slope;\n\tu32 high_credit;\n\tu32 low_credit;\n\tbool use_prio;\n\tu32 prio;\n\tint tbs_en;\n};\n\nstruct stmmac_mdio_bus_data;\n\nstruct stmmac_dma_cfg;\n\nstruct stmmac_safety_feature_cfg;\n\nstruct system_counterval_t;\n\nstruct stmmac_axi;\n\nstruct plat_stmmacenet_data {\n\tenum dwmac_core_type core_type;\n\tint bus_id;\n\tint phy_addr;\n\tphy_interface_t phy_interface;\n\tstruct stmmac_mdio_bus_data *mdio_bus_data;\n\tstruct device_node *phy_node;\n\tstruct fwnode_handle *port_node;\n\tstruct device_node *mdio_node;\n\tstruct stmmac_dma_cfg *dma_cfg;\n\tstruct stmmac_safety_feature_cfg *safety_feat_cfg;\n\tint clk_csr;\n\tint enh_desc;\n\tint tx_coe;\n\tint rx_coe;\n\tint bugged_jumbo;\n\tint pmt;\n\tint force_sf_dma_mode;\n\tint force_thresh_dma_mode;\n\tint riwt_off;\n\tint max_speed;\n\tint maxmtu;\n\tint multicast_filter_bins;\n\tint unicast_filter_entries;\n\tint tx_fifo_size;\n\tint rx_fifo_size;\n\tu32 host_dma_width;\n\tu32 rx_queues_to_use;\n\tu32 tx_queues_to_use;\n\tu8 rx_sched_algorithm;\n\tu8 tx_sched_algorithm;\n\tstruct stmmac_rxq_cfg rx_queues_cfg[8];\n\tstruct stmmac_txq_cfg tx_queues_cfg[8];\n\tvoid (*get_interfaces)(struct stmmac_priv *, void *, long unsigned int *);\n\tint (*set_phy_intf_sel)(void *, u8);\n\tint (*set_clk_tx_rate)(void *, struct clk *, phy_interface_t, int);\n\tvoid (*fix_mac_speed)(void *, int, unsigned int);\n\tint (*fix_soc_reset)(struct stmmac_priv *);\n\tint (*serdes_powerup)(struct net_device *, void *);\n\tvoid (*serdes_powerdown)(struct net_device *, void *);\n\tint (*mac_finish)(struct net_device *, void *, unsigned int, phy_interface_t);\n\tvoid (*ptp_clk_freq_config)(struct stmmac_priv *);\n\tint (*init)(struct device *, void *);\n\tvoid (*exit)(struct device *, void *);\n\tint (*suspend)(struct device *, void *);\n\tint (*resume)(struct device *, void *);\n\tint (*mac_setup)(void *, struct mac_device_info *);\n\tint (*clks_config)(void *, bool);\n\tint (*crosststamp)(ktime_t *, struct system_counterval_t *, void *);\n\tvoid (*dump_debug_regs)(void *);\n\tint (*pcs_init)(struct stmmac_priv *);\n\tvoid (*pcs_exit)(struct stmmac_priv *);\n\tstruct phylink_pcs * (*select_pcs)(struct stmmac_priv *, phy_interface_t);\n\tvoid *bsp_priv;\n\tstruct clk *stmmac_clk;\n\tstruct clk *pclk;\n\tstruct clk *clk_ptp_ref;\n\tstruct clk *clk_tx_i;\n\tlong unsigned int clk_ptp_rate;\n\tlong unsigned int clk_ref_rate;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tunsigned int mult_fact_100ns;\n\ts32 ptp_max_adj;\n\tu32 cdc_error_adj;\n\tstruct reset_control *stmmac_rst;\n\tstruct reset_control *stmmac_ahb_rst;\n\tstruct stmmac_axi *axi;\n\tint rss_en;\n\tint mac_port_sel_speed;\n\tu8 vlan_fail_q;\n\tstruct pci_dev *pdev;\n\tint int_snapshot_num;\n\tint msi_mac_vec;\n\tint msi_wol_vec;\n\tint msi_sfty_ce_vec;\n\tint msi_sfty_ue_vec;\n\tint msi_rx_base_vec;\n\tint msi_tx_base_vec;\n\tconst struct dwmac4_addrs *dwmac4_addrs;\n\tunsigned int flags;\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct property_entry;\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tlong: 32;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n\tlong: 32;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct platform_pwm_backlight_data {\n\tunsigned int max_brightness;\n\tunsigned int dft_brightness;\n\tunsigned int lth_brightness;\n\tunsigned int pwm_period_ns;\n\tunsigned int *levels;\n\tunsigned int post_pwm_on_delay;\n\tunsigned int pwm_off_delay;\n\tint (*init)(struct device *);\n\tint (*notify)(struct device *, int);\n\tvoid (*notify_after)(struct device *, int);\n\tvoid (*exit)(struct device *);\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)(void);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tvoid (*check)(void);\n\tbool (*wake)(void);\n\tvoid (*restore_early)(void);\n\tvoid (*restore)(void);\n\tvoid (*end)(void);\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)(void);\n\tvoid (*finish)(void);\n\tbool (*suspend_again)(void);\n\tvoid (*end)(void);\n\tvoid (*recover)(void);\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct plgpio_regs {\n\tu32 enb;\n\tu32 wdata;\n\tu32 dir;\n\tu32 rdata;\n\tu32 ie;\n\tu32 mis;\n\tu32 eit;\n};\n\nstruct plgpio {\n\tspinlock_t lock;\n\tstruct regmap *regmap;\n\tstruct clk *clk;\n\tstruct gpio_chip chip;\n\tint (*p2o)(int);\n\tint (*o2p)(int);\n\tu32 p2o_regs;\n\tstruct plgpio_regs regs;\n\tstruct plgpio_regs *csave_regs;\n};\n\nstruct pll_config {\n\tu16 l;\n\tu32 m;\n\tu32 n;\n\tu32 vco_val;\n\tu32 vco_mask;\n\tu32 pre_div_val;\n\tu32 pre_div_mask;\n\tu32 post_div_val;\n\tu32 post_div_mask;\n\tu32 mn_ena_mask;\n\tu32 main_output_mask;\n\tu32 aux_output_mask;\n};\n\nstruct pll_freq_tbl {\n\tlong unsigned int freq;\n\tu16 l;\n\tu16 m;\n\tu16 n;\n\tu32 ibits;\n};\n\nstruct pll_mult_range {\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct pll_out_data {\n\tchar *div_name;\n\tchar *pll_out_name;\n\tu32 offset;\n\tint clk_id;\n\tu8 div_shift;\n\tu8 div_flags;\n\tu8 rst_shift;\n\tspinlock_t *lock;\n};\n\nstruct pll_params {\n\tu8 ndiv;\n\tu16 frac;\n};\n\nstruct pll_params_table {\n\tunsigned int m;\n\tunsigned int n;\n};\n\nstruct pll_rate_tbl {\n\tu8 mode;\n\tu16 m;\n\tu8 n;\n\tu8 p;\n};\n\nstruct pll_ratio {\n\tint clk_ref;\n\tint calset_1;\n\tint calset_2;\n\tint calset_3;\n\tint calset_4;\n\tint cal_ctrl;\n};\n\nstruct pll_vco {\n\tlong unsigned int min_freq;\n\tlong unsigned int max_freq;\n\tu32 val;\n};\n\nstruct plt_entries {\n\tu32 ldr[16];\n\tu32 lit[16];\n};\n\nstruct pltfm_imx_data {\n\tu32 scratchpad;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_100mhz;\n\tstruct pinctrl_state *pins_200mhz;\n\tconst struct esdhc_soc_data *socdata;\n\tstruct esdhc_platform_data boarddata;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_per;\n\tunsigned int actual_clock;\n\tunsigned int init_card_type;\n\tenum {\n\t\tNO_CMD_PENDING = 0,\n\t\tMULTIBLK_IN_PROCESS = 1,\n\t\tWAIT_FOR_INT = 2,\n\t} multiblock_status;\n\tu32 is_ddr;\n\tstruct pm_qos_request pm_qos_req;\n};\n\nstruct pm8941_data {\n\tunsigned int pull_up_bit;\n\tunsigned int status_bit;\n\tbool supports_ps_hold_poff_config;\n\tbool supports_debounce_config;\n\tbool has_pon_pbs;\n\tbool wakeup_source_default;\n\tconst char *name;\n\tconst char *phys;\n};\n\nstruct pm8941_pwrkey {\n\tstruct device *dev;\n\tint irq;\n\tu32 baseaddr;\n\tu32 pon_pbs_baseaddr;\n\tstruct regmap *regmap;\n\tstruct input_dev *input;\n\tunsigned int revision;\n\tunsigned int subtype;\n\tstruct notifier_block reboot_notifier;\n\tu32 code;\n\tu32 sw_debounce_time_us;\n\tlong: 32;\n\tktime_t sw_debounce_end_time;\n\tbool last_status;\n\tconst struct pm8941_data *data;\n};\n\nstruct pm8xxx_gpio {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct pinctrl_dev *pctrl;\n\tstruct gpio_chip chip;\n\tstruct pinctrl_desc desc;\n\tunsigned int npins;\n};\n\nstruct pm8xxx_mpp {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct pinctrl_dev *pctrl;\n\tstruct gpio_chip chip;\n\tstruct pinctrl_desc desc;\n\tunsigned int npins;\n};\n\nstruct pm8xxx_pin_data {\n\tunsigned int reg;\n\tu8 power_source;\n\tu8 mode;\n\tbool open_drain;\n\tbool output_value;\n\tu8 bias;\n\tu8 pull_up_strength;\n\tu8 output_strength;\n\tbool disable;\n\tu8 function;\n\tbool inverted;\n};\n\nstruct pm8xxx_pin_data___2 {\n\tunsigned int reg;\n\tu8 mode;\n\tbool input;\n\tbool output;\n\tbool high_z;\n\tbool paired;\n\tbool output_value;\n\tu8 power_source;\n\tu8 dtest;\n\tu8 amux;\n\tu8 aout_level;\n\tu8 drive_strength;\n\tunsigned int pullup;\n};\n\nstruct pm_clk_notifier_block {\n\tstruct notifier_block nb;\n\tstruct dev_pm_domain *pm_domain;\n\tchar *con_ids[0];\n};\n\nstruct pm_clock_entry {\n\tstruct list_head node;\n\tchar *con_id;\n\tstruct clk *clk;\n\tenum pce_status status;\n\tbool enabled_when_prepared;\n};\n\nstruct pm_irq_data;\n\nstruct pm_irq_chip {\n\tstruct regmap *regmap;\n\tspinlock_t pm_irq_lock;\n\tstruct irq_domain *irqdomain;\n\tunsigned int num_blocks;\n\tunsigned int num_masters;\n\tconst struct pm_irq_data *pm_irq_data;\n\tu8 config[0];\n};\n\nstruct pm_irq_data {\n\tint num_irqs;\n\tstruct irq_chip *irq_chip;\n\tirq_handler_t irq_handler;\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n\tunsigned int clock_op_might_sleep;\n\tstruct mutex clock_mutex;\n\tstruct list_head clock_list;\n\tstruct pm_domain_data *domain_data;\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct tegra_pmc;\n\nstruct pmc_clk {\n\tstruct clk_hw hw;\n\tstruct tegra_pmc *pmc;\n\tlong unsigned int offs;\n\tu32 mux_shift;\n\tu32 force_en_shift;\n};\n\nstruct pmc_clk_gate {\n\tstruct clk_hw hw;\n\tstruct tegra_pmc *pmc;\n\tlong unsigned int offs;\n\tu32 shift;\n};\n\nstruct pmc_clk_init_data {\n\tchar *name;\n\tconst char * const *parents;\n\tint num_parents;\n\tint clk_id;\n\tu8 mux_shift;\n\tu8 force_en_shift;\n};\n\nstruct pmc_data {\n\tunsigned int ncore;\n\tstruct clk_hw **chws;\n\tunsigned int nsystem;\n\tstruct clk_hw **shws;\n\tunsigned int nperiph;\n\tstruct clk_hw **phws;\n\tunsigned int ngck;\n\tstruct clk_hw **ghws;\n\tunsigned int npck;\n\tstruct clk_hw **pchws;\n\tstruct clk_hw *hwtable[0];\n};\n\nstruct pmc_info {\n\tlong unsigned int uhp_udp_mask;\n\tlong unsigned int mckr;\n\tlong unsigned int version;\n\tlong unsigned int mcks;\n};\n\nstruct pmc_reg_config {\n\tu8 mckr;\n};\n\nstruct spmi_pmic_arb_bus;\n\nstruct spmi_controller;\n\nstruct pmic_arb_ver_ops {\n\tconst char *ver_str;\n\tint (*get_core_resources)(struct platform_device *, void *);\n\tint (*get_bus_resources)(struct platform_device *, struct device_node *, struct spmi_pmic_arb_bus *);\n\tint (*init_apid)(struct spmi_pmic_arb_bus *, int);\n\tint (*ppid_to_apid)(struct spmi_pmic_arb_bus *, u16);\n\tint (*offset)(struct spmi_pmic_arb_bus *, u8, u16, enum pmic_arb_channel);\n\tu32 (*fmt_cmd)(u8, u8, u16, u8);\n\tint (*non_data_cmd)(struct spmi_controller *, u8, u8);\n\tvoid * (*owner_acc_status)(struct spmi_pmic_arb_bus *, u8, u16);\n\tvoid * (*acc_enable)(struct spmi_pmic_arb_bus *, u16);\n\tvoid * (*irq_status)(struct spmi_pmic_arb_bus *, u16);\n\tvoid * (*irq_clear)(struct spmi_pmic_arb_bus *, u16);\n\tu32 (*apid_map_offset)(u16);\n\tvoid * (*apid_owner)(struct spmi_pmic_arb_bus *, u16);\n};\n\nstruct pmic_gpio_pad {\n\tu16 base;\n\tbool is_enabled;\n\tbool out_value;\n\tbool have_buffer;\n\tbool output_enabled;\n\tbool input_enabled;\n\tbool analog_pass;\n\tbool lv_mv_type;\n\tunsigned int num_sources;\n\tunsigned int power_source;\n\tunsigned int buffer_type;\n\tunsigned int pullup;\n\tunsigned int strength;\n\tunsigned int function;\n\tunsigned int atest;\n\tunsigned int dtest_buffer;\n};\n\nstruct pmic_gpio_state {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct pinctrl_dev *ctrl;\n\tstruct gpio_chip chip;\n\tu8 usid;\n\tu8 pid_base;\n};\n\nstruct pmic_mpp_pad {\n\tu16 base;\n\tbool is_enabled;\n\tbool out_value;\n\tbool output_enabled;\n\tbool input_enabled;\n\tbool paired;\n\tbool has_pullup;\n\tunsigned int num_sources;\n\tunsigned int power_source;\n\tunsigned int amux_input;\n\tunsigned int aout_level;\n\tunsigned int pullup;\n\tunsigned int function;\n\tunsigned int drive_strength;\n\tunsigned int dtest;\n};\n\nstruct pmic_mpp_state {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct pinctrl_dev *ctrl;\n\tstruct gpio_chip chip;\n};\n\nstruct pmu_data {\n\tspinlock_t lock;\n\tstruct device_node *of_node;\n\tvoid *pmc_base;\n\tvoid *pmu_base;\n\tstruct irq_chip_generic *irq_gc;\n\tstruct irq_domain *irq_domain;\n\tstruct reset_controller_dev reset;\n};\n\nstruct pmu_domain {\n\tstruct pmu_data *pmu;\n\tu32 pwr_mask;\n\tu32 rst_mask;\n\tu32 iso_mask;\n\tstruct generic_pm_domain base;\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pmu_hw_events {\n\tstruct perf_event *events[32];\n\tlong unsigned int used_mask[1];\n\tstruct arm_pmu *percpu_pmu;\n\tint irq;\n\tstruct perf_branch_stack *branch_stack;\n\tunsigned int branch_users;\n};\n\nstruct pmu_irq_ops {\n\tvoid (*enable_pmuirq)(unsigned int);\n\tvoid (*disable_pmuirq)(unsigned int);\n\tvoid (*free_pmuirq)(unsigned int, int, void *);\n};\n\ntypedef int (*armpmu_init_fn)(struct arm_pmu *);\n\nstruct pmu_probe_info {\n\tunsigned int cpuid;\n\tunsigned int mask;\n\tarmpmu_init_fn init;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct pnfs_commit_bucket {\n\tstruct list_head written;\n\tstruct list_head committing;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_writeverf direct_verf;\n};\n\nstruct pnfs_commit_array {\n\tstruct list_head cinfo_list;\n\tstruct list_head lseg_list;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tunsigned int nbuckets;\n\tstruct pnfs_commit_bucket buckets[0];\n};\n\nstruct pnfs_commit_ops {\n\tvoid (*setup_ds_info)(struct pnfs_ds_commit_info *, struct pnfs_layout_segment *);\n\tvoid (*release_ds_info)(struct pnfs_ds_commit_info *, struct inode *);\n\tint (*commit_pagelist)(struct inode *, struct list_head *, int, struct nfs_commit_info *);\n\tvoid (*mark_request_commit)(struct nfs_page *, struct pnfs_layout_segment *, struct nfs_commit_info *, u32);\n\tvoid (*clear_request_commit)(struct nfs_page *, struct nfs_commit_info *);\n\tint (*scan_commit_lists)(struct nfs_commit_info *, int);\n\tvoid (*recover_commit_reqs)(struct list_head *, struct nfs_commit_info *);\n};\n\nstruct pnfs_device {\n\tstruct nfs4_deviceid dev_id;\n\tunsigned int layout_type;\n\tunsigned int mincount;\n\tunsigned int maxcount;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tunsigned char nocache: 1;\n};\n\nstruct pnfs_layoutdriver_type {\n\tstruct list_head pnfs_tblid;\n\tconst u32 id;\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int flags;\n\tunsigned int max_layoutget_response;\n\tint (*set_layoutdriver)(struct nfs_server *, const struct nfs_fh *);\n\tint (*clear_layoutdriver)(struct nfs_server *);\n\tstruct pnfs_layout_hdr * (*alloc_layout_hdr)(struct inode *, gfp_t);\n\tvoid (*free_layout_hdr)(struct pnfs_layout_hdr *);\n\tstruct pnfs_layout_segment * (*alloc_lseg)(struct pnfs_layout_hdr *, struct nfs4_layoutget_res *, gfp_t);\n\tvoid (*free_lseg)(struct pnfs_layout_segment *);\n\tvoid (*add_lseg)(struct pnfs_layout_hdr *, struct pnfs_layout_segment *, struct list_head *);\n\tvoid (*return_range)(struct pnfs_layout_hdr *, struct pnfs_layout_range *);\n\tconst struct nfs_pageio_ops *pg_read_ops;\n\tconst struct nfs_pageio_ops *pg_write_ops;\n\tstruct pnfs_ds_commit_info * (*get_ds_info)(struct inode *);\n\tint (*sync)(struct inode *, bool);\n\tenum pnfs_try_status (*read_pagelist)(struct nfs_pgio_header *);\n\tenum pnfs_try_status (*write_pagelist)(struct nfs_pgio_header *, int);\n\tvoid (*free_deviceid_node)(struct nfs4_deviceid_node *);\n\tstruct nfs4_deviceid_node * (*alloc_deviceid_node)(struct nfs_server *, struct pnfs_device *, gfp_t);\n\tint (*prepare_layoutreturn)(struct nfs4_layoutreturn_args *);\n\tvoid (*cleanup_layoutcommit)(struct nfs4_layoutcommit_data *);\n\tint (*prepare_layoutcommit)(struct nfs4_layoutcommit_args *);\n\tint (*prepare_layoutstats)(struct nfs42_layoutstat_args *);\n\tvoid (*cancel_io)(struct pnfs_layout_segment *);\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n\tlong: 32;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_device_id;\n\nstruct pnp_dev;\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_link;\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[18];\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tlong: 32;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct port_stats {\n\tlong unsigned int bytes_sent;\n\tlong unsigned int bytes_received;\n\tlong unsigned int bytes_discarded;\n};\n\nstruct ports_device;\n\nstruct port_buffer;\n\nstruct virtqueue;\n\nstruct port {\n\tstruct list_head list;\n\tstruct ports_device *portdev;\n\tstruct port_buffer *inbuf;\n\tspinlock_t inbuf_lock;\n\tspinlock_t outvq_lock;\n\tstruct virtqueue *in_vq;\n\tstruct virtqueue *out_vq;\n\tstruct dentry *debugfs_file;\n\tstruct port_stats stats;\n\tstruct console___2 cons;\n\tstruct cdev *cdev;\n\tstruct device *dev;\n\tstruct kref kref;\n\twait_queue_head_t waitqueue;\n\tchar *name;\n\tstruct fasync_struct *async_queue;\n\tu32 id;\n\tbool outvq_full;\n\tbool host_connected;\n\tbool guest_connected;\n};\n\nstruct port_buffer {\n\tchar *buf;\n\tsize_t size;\n\tsize_t len;\n\tsize_t offset;\n\tdma_addr_t dma;\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int sgpages;\n\tstruct scatterlist sg[0];\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct portdrv_service_data {\n\tstruct pcie_port_service_driver *drv;\n\tstruct device *dev;\n\tu32 service;\n};\n\nstruct virtio_console_control {\n\t__virtio32 id;\n\t__virtio16 event;\n\t__virtio16 value;\n};\n\nstruct virtio_device;\n\nstruct ports_device {\n\tstruct list_head list;\n\tstruct work_struct control_work;\n\tstruct work_struct config_work;\n\tstruct list_head ports;\n\tspinlock_t ports_lock;\n\tspinlock_t c_ivq_lock;\n\tspinlock_t c_ovq_lock;\n\tu32 max_nr_ports;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *c_ivq;\n\tstruct virtqueue *c_ovq;\n\tstruct virtio_console_control cpkt;\n\tstruct virtqueue **in_vqs;\n\tstruct virtqueue **out_vqs;\n\tint chr_major;\n};\n\nstruct ports_driver_data {\n\tstruct dentry *debugfs_dir;\n\tstruct list_head portdevs;\n\tstruct list_head consoles;\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct power_dom_info {\n\tbool state_set_sync;\n\tbool state_set_async;\n\tbool state_set_notify;\n\tchar name[64];\n};\n\nstruct power_state {\n\tstruct powerdomain *pwrdm;\n\tu32 next_state;\n\tu32 saved_state;\n\tstruct list_head node;\n};\n\nstruct power_state___2 {\n\tstruct powerdomain *pwrdm;\n\tu32 next_state;\n\tu32 next_logic_state;\n\tu32 saved_state;\n\tu32 saved_logic_state;\n\tstruct list_head node;\n};\n\nstruct power_supply_battery_info;\n\nstruct power_supply {\n\tconst struct power_supply_desc *desc;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tchar **supplied_from;\n\tsize_t num_supplies;\n\tvoid *drv_data;\n\tstruct device dev;\n\tstruct work_struct changed_work;\n\tstruct delayed_work deferred_register_work;\n\tspinlock_t changed_lock;\n\tbool changed;\n\tbool update_groups;\n\tbool initialized;\n\tbool removing;\n\tatomic_t use_cnt;\n\tstruct power_supply_battery_info *battery_info;\n\tstruct rw_semaphore extensions_sem;\n\tstruct list_head extensions;\n\tstruct thermal_zone_device *tzd;\n\tstruct thermal_cooling_device *tcd;\n\tstruct led_trigger *trig;\n\tstruct led_trigger *charging_trig;\n\tstruct led_trigger *full_trig;\n\tstruct led_trigger *charging_blink_full_solid_trig;\n\tstruct led_trigger *charging_orange_full_green_trig;\n};\n\nstruct power_supply_attr {\n\tconst char *prop_name;\n\tchar attr_name[31];\n\tstruct device_attribute dev_attr;\n\tconst char * const *text_values;\n\tint text_values_len;\n};\n\nstruct power_supply_maintenance_charge_table;\n\nstruct power_supply_battery_ocv_table;\n\nstruct power_supply_resistance_temp_table;\n\nstruct power_supply_vbat_ri_table;\n\nstruct power_supply_battery_info {\n\tunsigned int technology;\n\tint energy_full_design_uwh;\n\tint charge_full_design_uah;\n\tint voltage_min_design_uv;\n\tint voltage_max_design_uv;\n\tint tricklecharge_current_ua;\n\tint precharge_current_ua;\n\tint precharge_voltage_max_uv;\n\tint charge_term_current_ua;\n\tint charge_restart_voltage_uv;\n\tint overvoltage_limit_uv;\n\tint constant_charge_current_max_ua;\n\tint constant_charge_voltage_max_uv;\n\tconst struct power_supply_maintenance_charge_table *maintenance_charge;\n\tint maintenance_charge_size;\n\tint alert_low_temp_charge_current_ua;\n\tint alert_low_temp_charge_voltage_uv;\n\tint alert_high_temp_charge_current_ua;\n\tint alert_high_temp_charge_voltage_uv;\n\tint factory_internal_resistance_uohm;\n\tint factory_internal_resistance_charging_uohm;\n\tint ocv_temp[20];\n\tint temp_ambient_alert_min;\n\tint temp_ambient_alert_max;\n\tint temp_alert_min;\n\tint temp_alert_max;\n\tint temp_min;\n\tint temp_max;\n\tconst struct power_supply_battery_ocv_table *ocv_table[20];\n\tint ocv_table_size[20];\n\tconst struct power_supply_resistance_temp_table *resist_table;\n\tint resist_table_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_discharging;\n\tint vbat2ri_discharging_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_charging;\n\tint vbat2ri_charging_size;\n\tint bti_resistance_ohm;\n\tint bti_resistance_tolerance;\n};\n\nstruct power_supply_battery_ocv_table {\n\tint ocv;\n\tint capacity;\n};\n\nstruct power_supply_config {\n\tstruct fwnode_handle *fwnode;\n\tvoid *drv_data;\n\tconst struct attribute_group **attr_grp;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tbool no_wakeup_source;\n};\n\nstruct power_supply_ext {\n\tconst char * const name;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property);\n};\n\nstruct power_supply_ext_registration {\n\tstruct list_head list_head;\n\tconst struct power_supply_ext *ext;\n\tstruct device *dev;\n\tvoid *data;\n};\n\nstruct power_supply_hwmon {\n\tstruct power_supply *psy;\n\tlong unsigned int *props;\n};\n\nstruct power_supply_led_trigger {\n\tstruct led_trigger trig;\n\tstruct power_supply *psy;\n};\n\nstruct power_supply_maintenance_charge_table {\n\tint charge_current_max_ua;\n\tint charge_voltage_max_uv;\n\tint charge_safety_timer_minutes;\n};\n\nunion power_supply_propval {\n\tint intval;\n\tconst char *strval;\n};\n\nstruct power_supply_resistance_temp_table {\n\tint temp;\n\tint resistance;\n};\n\nstruct power_supply_vbat_ri_table {\n\tint vbat_uv;\n\tint ri_uohm;\n};\n\nstruct scmi_powercap_state;\n\nstruct scmi_powercap_info;\n\nstruct powercap_info {\n\tint num_domains;\n\tbool notify_cap_cmd;\n\tbool notify_measurements_cmd;\n\tstruct scmi_powercap_state *states;\n\tstruct scmi_powercap_info *powercaps;\n};\n\nstruct powerdomain {\n\tconst char *name;\n\tunion {\n\t\tconst char *name;\n\t\tstruct voltagedomain *ptr;\n\t} voltdm;\n\tconst s16 prcm_offs;\n\tconst u8 pwrsts;\n\tconst u8 pwrsts_logic_ret;\n\tconst u8 flags;\n\tconst u8 banks;\n\tconst u8 pwrsts_mem_ret[5];\n\tconst u8 pwrsts_mem_on[5];\n\tconst u8 prcm_partition;\n\tstruct clockdomain *pwrdm_clkdms[11];\n\tstruct list_head node;\n\tstruct list_head voltdm_node;\n\tint state;\n\tunsigned int state_counter[4];\n\tunsigned int ret_logic_off_counter;\n\tunsigned int ret_mem_off_counter[5];\n\tspinlock_t _lock;\n\tlong unsigned int _lock_flags;\n\tconst u8 pwrstctrl_offs;\n\tconst u8 pwrstst_offs;\n\tconst u32 logicretstate_mask;\n\tconst u32 mem_on_mask[5];\n\tconst u32 mem_ret_mask[5];\n\tconst u32 mem_pwrst_mask[5];\n\tconst u32 mem_retst_mask[5];\n\tu32 context;\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pps_bind_args {\n\tint tsformat;\n\tint edge;\n\tint consumer;\n};\n\nstruct pps_device;\n\nstruct pps_source_info {\n\tchar name[32];\n\tchar path[32];\n\tint mode;\n\tvoid (*echo)(struct pps_device *, int, void *);\n\tstruct module *owner;\n\tstruct device *dev;\n};\n\nstruct pps_ktime {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kparams {\n\tint api_version;\n\tint mode;\n\tstruct pps_ktime assert_off_tu;\n\tstruct pps_ktime clear_off_tu;\n};\n\nstruct pps_device {\n\tstruct pps_source_info info;\n\tstruct pps_kparams params;\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tunsigned int last_ev;\n\tunsigned int last_fetched_ev;\n\twait_queue_head_t queue;\n\tunsigned int id;\n\tconst void *lookup_cookie;\n\tstruct device dev;\n\tstruct fasync_struct *async_queue;\n\tspinlock_t lock;\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct pps_kinfo {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tlong: 32;\n};\n\nstruct pps_fdata {\n\tstruct pps_kinfo info;\n\tstruct pps_ktime timeout;\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prcm_data {\n\tint nsubdevs;\n\tconst struct mfd_cell *subdevs;\n};\n\nstruct prcm_gpiocr_altcx {\n\tbool used: 1;\n\tu8 reg_index: 2;\n\tu8 control_bit: 5;\n};\n\nstruct prcm_gpiocr_altcx_pin_desc {\n\tshort unsigned int pin;\n\tstruct prcm_gpiocr_altcx altcx[4];\n};\n\nstruct prcmu_auto_pm_config {\n\tu8 sia_auto_pm_enable;\n\tu8 sia_power_on;\n\tu8 sia_policy;\n\tu8 sva_auto_pm_enable;\n\tu8 sva_power_on;\n\tu8 sva_policy;\n};\n\nstruct prcmu_fw_version {\n\tu32 project;\n\tu8 api_version;\n\tu8 func_version;\n\tu8 errata;\n\tchar project_name[20];\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n\tlong: 32;\n};\n\nstruct pre_voltage_change_data {\n\tlong unsigned int old_uV;\n\tlong unsigned int min_uV;\n\tlong unsigned int max_uV;\n};\n\nstruct prefix_cacheinfo {\n\t__u32 preferred_time;\n\t__u32 valid_time;\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\tunion {\n\t\t__u8 flags;\n\t\tstruct {\n\t\t\t__u8 reserved: 4;\n\t\t\t__u8 preferpd: 1;\n\t\t\t__u8 routeraddr: 1;\n\t\t\t__u8 autoconf: 1;\n\t\t\t__u8 onlink: 1;\n\t\t};\n\t};\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct prefixmsg {\n\tunsigned char prefix_family;\n\tunsigned char prefix_pad1;\n\tshort unsigned int prefix_pad2;\n\tint prefix_ifindex;\n\tunsigned char prefix_type;\n\tunsigned char prefix_len;\n\tunsigned char prefix_flags;\n\tunsigned char prefix_pad3;\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tlong: 32;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct priv {\n\tstruct clk *clk;\n\tvoid *base;\n};\n\nstruct private_data {\n\tstruct list_head node;\n\tcpumask_var_t cpus;\n\tstruct device *cpu_dev;\n\tstruct cpufreq_frequency_table *freq_table;\n\tbool have_static_opps;\n\tint opp_token;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\nstruct prm_ll_data {\n\tu32 (*read_reset_sources)(void);\n\tbool (*was_any_context_lost_old)(u8, s16, u16);\n\tvoid (*clear_context_loss_flags_old)(u8, s16, u16);\n\tint (*late_init)(void);\n\tint (*assert_hardreset)(u8, u8, s16, u16);\n\tint (*deassert_hardreset)(u8, u8, u8, s16, u16, u16);\n\tint (*is_hardreset_asserted)(u8, u8, s16, u16);\n\tvoid (*reset_system)(void);\n\tint (*clear_mod_irqs)(s16, u8, u32);\n\tu32 (*vp_check_txdone)(u8);\n\tvoid (*vp_clear_txdone)(u8);\n};\n\nstruct prm_reset_src_map {\n\ts8 reg_shift;\n\ts8 std_shift;\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct probe_entry_arg {\n\tstruct fetch_insn *code;\n\tunsigned int size;\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n\tlong: 32;\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct processor;\n\nstruct proc_info_list {\n\tunsigned int cpu_val;\n\tunsigned int cpu_mask;\n\tlong unsigned int __cpu_mm_mmu_flags;\n\tlong unsigned int __cpu_io_mmu_flags;\n\tlong unsigned int __cpu_flush;\n\tconst char *arch_name;\n\tconst char *elf_name;\n\tunsigned int elf_hwcap;\n\tconst char *cpu_name;\n\tstruct processor *proc;\n\tstruct cpu_tlb_fns *tlb;\n\tstruct cpu_user_fns *user;\n\tstruct cpu_cache_fns *cache;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tlong: 32;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n\tbool mmap_locked;\n\tstruct vm_area_struct *locked_vma;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tlong: 32;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_nfs_info {\n\tint flag;\n\tconst char *str;\n\tconst char *nostr;\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tlong: 32;\n\tstruct timespec64 val;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct processor {\n\tvoid (*_data_abort)(long unsigned int);\n\tlong unsigned int (*_prefetch_abort)(long unsigned int);\n\tvoid (*_proc_init)(void);\n\tvoid (*check_bugs)(void);\n\tvoid (*_proc_fin)(void);\n\tvoid (*reset)(long unsigned int, bool);\n\tint (*_do_idle)(void);\n\tvoid (*dcache_clean_area)(void *, int);\n\tvoid (*switch_mm)(phys_addr_t, struct mm_struct *);\n\tvoid (*set_pte_ext)(pte_t *, pte_t, unsigned int);\n\tunsigned int suspend_size;\n\tvoid (*do_suspend)(void *);\n\tvoid (*do_resume)(void *);\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n\tlong unsigned int _flags;\n\tstruct bin_attribute attr;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[2];\n\t\t} value;\n\t};\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n\tlong: 32;\n};\n\nstruct psci_0_1_function_ids {\n\tu32 cpu_suspend;\n\tu32 cpu_on;\n\tu32 cpu_off;\n\tu32 migrate;\n};\n\nstruct psci_cpuidle_data {\n\tu32 *psci_states;\n\tstruct device *dev;\n};\n\nstruct psci_cpuidle_domain_state {\n\tstruct generic_pm_domain *pd;\n\tunsigned int state_idx;\n\tu32 state;\n};\n\nstruct psci_operations {\n\tu32 (*get_version)(void);\n\tint (*cpu_suspend)(u32, long unsigned int);\n\tint (*cpu_off)(u32);\n\tint (*cpu_on)(long unsigned int, long unsigned int);\n\tint (*migrate)(long unsigned int);\n\tint (*affinity_info)(long unsigned int, long unsigned int);\n\tint (*migrate_info_type)(void);\n};\n\nstruct psci_pd_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psi_group {};\n\nstruct psmouse_protocol;\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct pstore_context {\n\tunsigned int kmsg_bytes;\n};\n\nstruct pstore_ftrace_record {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu64 ts;\n};\n\nstruct pstore_ftrace_seq_data {\n\tconst void *ptr;\n\tsize_t off;\n\tsize_t size;\n};\n\nstruct pstore_record;\n\nstruct pstore_info {\n\tstruct module *owner;\n\tconst char *name;\n\traw_spinlock_t buf_lock;\n\tchar *buf;\n\tsize_t bufsize;\n\tstruct mutex read_mutex;\n\tint flags;\n\tint max_reason;\n\tvoid *data;\n\tint (*open)(struct pstore_info *);\n\tint (*close)(struct pstore_info *);\n\tssize_t (*read)(struct pstore_record *);\n\tint (*write)(struct pstore_record *);\n\tint (*write_user)(struct pstore_record *, const char *);\n\tint (*erase)(struct pstore_record *);\n};\n\nstruct pstore_private {\n\tstruct list_head list;\n\tstruct dentry *dentry;\n\tstruct pstore_record *record;\n\tsize_t total_size;\n};\n\nstruct pstore_record {\n\tstruct pstore_info *psi;\n\tenum pstore_type_id type;\n\tu64 id;\n\tstruct timespec64 time;\n\tchar *buf;\n\tssize_t size;\n\tssize_t ecc_notice_size;\n\tvoid *priv;\n\tint count;\n\tenum kmsg_dump_reason reason;\n\tunsigned int part;\n\tbool compressed;\n};\n\nstruct psy_am_i_supplied_data {\n\tstruct power_supply *psy;\n\tunsigned int count;\n};\n\nstruct psy_for_each_psy_cb_data {\n\tint (*fn)(struct power_supply *, void *);\n\tvoid *data;\n};\n\nstruct psy_get_supplier_prop_data {\n\tstruct power_supply *psy;\n\tenum power_supply_property psp;\n\tunion power_supply_propval *val;\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\nstruct ptd {\n\t__dw dw0;\n\t__dw dw1;\n\t__dw dw2;\n\t__dw dw3;\n\t__dw dw4;\n\t__dw dw5;\n\t__dw dw6;\n\t__dw dw7;\n};\n\nstruct ptd_le32 {\n\t__le32 dw0;\n\t__le32 dw1;\n\t__le32 dw2;\n\t__le32 dw3;\n\t__le32 dw4;\n\t__le32 dw5;\n\t__le32 dw6;\n\t__le32 dw7;\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n};\n\nstruct ptp_clock {\n\tstruct posix_clock clock;\n\tlong: 32;\n\tstruct device dev;\n\tstruct ptp_clock_info *info;\n\tdev_t devid;\n\tint index;\n\tstruct pps_device *pps_source;\n\tlong int dialed_frequency;\n\tstruct list_head tsevqs;\n\tspinlock_t tsevqs_lock;\n\tstruct mutex pincfg_mux;\n\twait_queue_head_t tsev_wq;\n\tint defunct;\n\tstruct device_attribute *pin_dev_attr;\n\tstruct attribute **pin_attr;\n\tstruct attribute_group pin_attr_group;\n\tconst struct attribute_group *pin_attr_groups[2];\n\tstruct kthread_worker *kworker;\n\tstruct kthread_delayed_work aux_work;\n\tunsigned int max_vclocks;\n\tunsigned int n_vclocks;\n\tint *vclock_index;\n\tstruct mutex n_vclocks_mux;\n\tbool is_virtual_clock;\n\tbool has_cycles;\n\tstruct dentry *debugfs_root;\n};\n\nstruct ptp_clock_caps {\n\tint max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint pps;\n\tint n_pins;\n\tint cross_timestamping;\n\tint adjust_phase;\n\tint max_phase_adj;\n\tint rsv[11];\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\ts64 offset;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_perout_request {\n\tunion {\n\t\tstruct ptp_clock_time start;\n\t\tstruct ptp_clock_time phase;\n\t};\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunion {\n\t\tstruct ptp_clock_time on;\n\t\tunsigned int rsv[4];\n\t};\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tlong: 32;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_dte {\n\tvoid *regs;\n\tstruct ptp_clock *ptp_clk;\n\tstruct ptp_clock_info caps;\n\tstruct device *dev;\n\tu32 ts_ovf_last;\n\tu32 ts_wrap_cnt;\n\tspinlock_t lock;\n\tu32 reg_val[4];\n};\n\nstruct ptp_extts_event {\n\tstruct ptp_clock_time t;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptp_qoriq_registers {\n\tstruct ctrl_regs *ctrl_regs;\n\tstruct alarm_regs *alarm_regs;\n\tstruct fiper_regs *fiper_regs;\n\tstruct etts_regs *etts_regs;\n};\n\nstruct ptp_qoriq {\n\tvoid *base;\n\tstruct ptp_qoriq_registers regs;\n\tspinlock_t lock;\n\tstruct ptp_clock *clock;\n\tstruct ptp_clock_info caps;\n\tstruct resource *rsrc;\n\tstruct device *dev;\n\tbool extts_fifo_support;\n\tbool fiper3_support;\n\tbool etsec;\n\tint irq;\n\tint phc_index;\n\tu32 tclk_period;\n\tu32 tmr_prsc;\n\tu32 tmr_add;\n\tu32 cksel;\n\tu32 tmr_fiper1;\n\tu32 tmr_fiper2;\n\tu32 tmr_fiper3;\n\tu32 (*read)(unsigned int *);\n\tvoid (*write)(unsigned int *, u32);\n};\n\nstruct ptp_sys_offset {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[51];\n};\n\nstruct ptp_sys_offset_extended {\n\tunsigned int n_samples;\n\t__kernel_clockid_t clockid;\n\tunsigned int rsv[2];\n\tstruct ptp_clock_time ts[75];\n};\n\nstruct ptp_sys_offset_precise {\n\tstruct ptp_clock_time device;\n\tstruct ptp_clock_time sys_realtime;\n\tstruct ptp_clock_time sys_monoraw;\n\tunsigned int rsv[4];\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n\tclockid_t clockid;\n\tlong: 32;\n};\n\nstruct ptp_vclock {\n\tstruct ptp_clock *pclock;\n\tstruct ptp_clock_info info;\n\tstruct ptp_clock *clock;\n\tstruct hlist_node vclock_hash_node;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct mutex lock;\n\tlong: 32;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t\tlong: 32;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct public_key {\n\tvoid *key;\n\tu32 keylen;\n\tenum OID algo;\n\tvoid *params;\n\tu32 paramlen;\n\tbool key_is_private;\n\tconst char *id_type;\n\tconst char *pkey_algo;\n\tlong unsigned int key_eflags;\n};\n\nstruct public_key_signature {\n\tstruct asymmetric_key_id *auth_ids[3];\n\tu8 *s;\n\tu8 *m;\n\tu32 s_size;\n\tu32 m_size;\n\tbool m_free;\n\tbool algo_takes_data;\n\tconst char *pkey_algo;\n\tconst char *hash_algo;\n\tconst char *encoding;\n};\n\nstruct pwm_args {\n\tu64 period;\n\tenum pwm_polarity polarity;\n\tlong: 32;\n};\n\nstruct pwm_bl_data {\n\tstruct pwm_device *pwm;\n\tstruct device *dev;\n\tunsigned int lth_brightness;\n\tunsigned int *levels;\n\tbool enabled;\n\tstruct regulator *power_supply;\n\tstruct gpio_desc *enable_gpio;\n\tunsigned int scale;\n\tunsigned int post_pwm_on_delay;\n\tunsigned int pwm_off_delay;\n\tint (*notify)(struct device *, int);\n\tvoid (*notify_after)(struct device *, int);\n\tvoid (*exit)(struct device *);\n};\n\nstruct pwm_capture {\n\tunsigned int period;\n\tunsigned int duty_cycle;\n};\n\nstruct pwm_chip;\n\nstruct pwm_cdev_data {\n\tstruct pwm_chip *chip;\n\tstruct pwm_device *pwm[0];\n};\n\ntypedef struct pwm_chip *class_pwmchip_t;\n\nstruct pwm_device {\n\tconst char *label;\n\tlong unsigned int flags;\n\tunsigned int hwpwm;\n\tstruct pwm_chip *chip;\n\tstruct pwm_args args;\n\tstruct pwm_state state;\n\tstruct pwm_state last;\n};\n\nstruct pwm_ops;\n\nstruct pwm_chip {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tconst struct pwm_ops *ops;\n\tstruct module *owner;\n\tunsigned int id;\n\tunsigned int npwm;\n\tstruct pwm_device * (*of_xlate)(struct pwm_chip *, const struct of_phandle_args *);\n\tbool atomic;\n\tstruct gpio_chip gpio;\n\tbool uses_pwmchip_alloc;\n\tbool operational;\n\tunion {\n\t\tstruct mutex nonatomic_lock;\n\t\tspinlock_t atomic_lock;\n\t};\n\tlong: 32;\n\tstruct pwm_device pwms[0];\n};\n\nstruct pwm_continuous_reg_data {\n\tunsigned int min_uV_dutycycle;\n\tunsigned int max_uV_dutycycle;\n\tunsigned int dutycycle_unit;\n};\n\nstruct pwm_export {\n\tstruct device pwm_dev;\n\tstruct pwm_device *pwm;\n\tstruct mutex lock;\n\tstruct pwm_state suspend;\n};\n\nstruct pwm_lookup {\n\tstruct list_head list;\n\tconst char *provider;\n\tunsigned int index;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tunsigned int period;\n\tenum pwm_polarity polarity;\n\tconst char *module;\n};\n\nstruct pwm_waveform;\n\nstruct pwm_ops {\n\tint (*request)(struct pwm_chip *, struct pwm_device *);\n\tvoid (*free)(struct pwm_chip *, struct pwm_device *);\n\tint (*capture)(struct pwm_chip *, struct pwm_device *, struct pwm_capture *, long unsigned int);\n\tsize_t sizeof_wfhw;\n\tint (*round_waveform_tohw)(struct pwm_chip *, struct pwm_device *, const struct pwm_waveform *, void *);\n\tint (*round_waveform_fromhw)(struct pwm_chip *, struct pwm_device *, const void *, struct pwm_waveform *);\n\tint (*read_waveform)(struct pwm_chip *, struct pwm_device *, void *);\n\tint (*write_waveform)(struct pwm_chip *, struct pwm_device *, const void *);\n\tint (*apply)(struct pwm_chip *, struct pwm_device *, const struct pwm_state *);\n\tint (*get_state)(struct pwm_chip *, struct pwm_device *, struct pwm_state *);\n};\n\nstruct pwm_voltages;\n\nstruct pwm_regulator_data {\n\tstruct pwm_device *pwm;\n\tstruct pwm_voltages *duty_cycle_table;\n\tstruct pwm_continuous_reg_data continuous;\n\tstruct regulator_desc desc;\n\tint state;\n\tstruct gpio_desc *enb_gpio;\n};\n\nstruct pwm_voltages {\n\tunsigned int uV;\n\tunsigned int dutycycle;\n};\n\nstruct pwm_waveform {\n\tu64 period_length_ns;\n\tu64 duty_length_ns;\n\tu64 duty_offset_ns;\n};\n\nstruct pwmchip_waveform {\n\t__u32 hwpwm;\n\t__u32 __pad;\n\t__u64 period_length_ns;\n\t__u64 duty_length_ns;\n\t__u64 duty_offset_ns;\n};\n\nstruct pwrdm_link {\n\tstruct device *dev;\n\tstruct powerdomain *pwrdm;\n\tstruct list_head node;\n};\n\nstruct pwrdm_ops {\n\tint (*pwrdm_set_next_pwrst)(struct powerdomain *, u8);\n\tint (*pwrdm_read_next_pwrst)(struct powerdomain *);\n\tint (*pwrdm_read_pwrst)(struct powerdomain *);\n\tint (*pwrdm_read_prev_pwrst)(struct powerdomain *);\n\tint (*pwrdm_set_logic_retst)(struct powerdomain *, u8);\n\tint (*pwrdm_set_mem_onst)(struct powerdomain *, u8, u8);\n\tint (*pwrdm_set_mem_retst)(struct powerdomain *, u8, u8);\n\tint (*pwrdm_read_logic_pwrst)(struct powerdomain *);\n\tint (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *);\n\tint (*pwrdm_read_logic_retst)(struct powerdomain *);\n\tint (*pwrdm_read_mem_pwrst)(struct powerdomain *, u8);\n\tint (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *, u8);\n\tint (*pwrdm_read_mem_retst)(struct powerdomain *, u8);\n\tint (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *);\n\tint (*pwrdm_enable_hdwr_sar)(struct powerdomain *);\n\tint (*pwrdm_disable_hdwr_sar)(struct powerdomain *);\n\tint (*pwrdm_set_lowpwrstchange)(struct powerdomain *);\n\tint (*pwrdm_wait_transition)(struct powerdomain *);\n\tint (*pwrdm_has_voltdm)(void);\n\tvoid (*pwrdm_save_context)(struct powerdomain *);\n\tvoid (*pwrdm_restore_context)(struct powerdomain *);\n};\n\nstruct pxa1928_clk_unit {\n\tstruct mmp_clk_unit unit;\n\tvoid *mpmu_base;\n\tvoid *apmu_base;\n\tvoid *apbc_base;\n\tvoid *apbcp_base;\n};\n\nstruct pxa3xx_nand_platform_data {\n\tbool keep_config;\n\tbool flash_bbt;\n\tint ecc_strength;\n\tint ecc_step_size;\n\tconst struct mtd_partition *parts;\n\tunsigned int nr_parts;\n};\n\nstruct pxa_gpio_bank {\n\tvoid *regbase;\n\tlong unsigned int irq_mask;\n\tlong unsigned int irq_edge_rise;\n\tlong unsigned int irq_edge_fall;\n\tlong unsigned int saved_gplr;\n\tlong unsigned int saved_gpdr;\n\tlong unsigned int saved_grer;\n\tlong unsigned int saved_gfer;\n};\n\nstruct pxa_gpio_chip {\n\tstruct device *dev;\n\tstruct gpio_chip chip;\n\tstruct pxa_gpio_bank *banks;\n\tstruct irq_domain *irqdomain;\n\tint irq0;\n\tint irq1;\n\tint (*set_wake)(unsigned int, unsigned int);\n};\n\nstruct pxa_gpio_id {\n\tenum pxa_gpio_type type;\n\tint gpio_nums;\n};\n\nstruct pxa_gpio_platform_data {\n\tint irq_base;\n\tint (*gpio_set_wake)(unsigned int, unsigned int);\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tlong: 32;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n\tlong: 32;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong: 32;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tlong: 32;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qcom_adm_peripheral_config {\n\tu32 crci;\n\tu32 mux;\n};\n\nstruct qcom_apcs_ipc {\n\tstruct mbox_controller mbox;\n\tstruct mbox_chan mbox_chans[32];\n\tstruct regmap *regmap;\n\tlong unsigned int offset;\n\tstruct platform_device *clk;\n\tlong: 32;\n};\n\nstruct qcom_apcs_ipc_data {\n\tint offset;\n\tchar *clk_name;\n};\n\nstruct qcom_reset_map;\n\nstruct qcom_reset_controller {\n\tconst struct qcom_reset_map *reset_map;\n\tstruct regmap *regmap;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct qcom_cc {\n\tstruct qcom_reset_controller reset;\n\tstruct clk_regmap **rclks;\n\tsize_t num_rclks;\n\tstruct dev_pm_domain_list *pd_list;\n};\n\nstruct qcom_icc_hws_data;\n\nstruct qcom_cc_driver_data;\n\nstruct qcom_cc_desc {\n\tconst struct regmap_config *config;\n\tstruct clk_regmap **clks;\n\tsize_t num_clks;\n\tconst struct qcom_reset_map *resets;\n\tsize_t num_resets;\n\tstruct gdsc **gdscs;\n\tsize_t num_gdscs;\n\tstruct clk_hw **clk_hws;\n\tsize_t num_clk_hws;\n\tconst struct qcom_icc_hws_data *icc_hws;\n\tsize_t num_icc_hws;\n\tunsigned int icc_first_node_id;\n\tbool use_rpm;\n\tstruct qcom_cc_driver_data *driver_data;\n};\n\nstruct qcom_cc_driver_data {\n\tstruct clk_alpha_pll **alpha_plls;\n\tsize_t num_alpha_plls;\n\tu32 *clk_cbcrs;\n\tsize_t num_clk_cbcrs;\n\tconst struct clk_rcg_dfs_data *dfs_rcgs;\n\tsize_t num_dfs_rcgs;\n\tvoid (*clk_regs_configure)(struct device *, struct regmap *);\n};\n\nstruct qcom_cpufreq_drv_cpu {\n\tint opp_token;\n\tstruct dev_pm_domain_list *pd_list;\n};\n\nstruct qcom_cpufreq_match_data;\n\nstruct qcom_cpufreq_drv {\n\tu32 versions;\n\tconst struct qcom_cpufreq_match_data *data;\n\tstruct qcom_cpufreq_drv_cpu cpus[0];\n};\n\nstruct qcom_cpufreq_match_data {\n\tint (*get_version)(struct device *, struct nvmem_cell *, char **, struct qcom_cpufreq_drv *);\n\tconst char **pd_names;\n\tunsigned int num_pd_names;\n};\n\nstruct qcom_ethqos {\n\tstruct platform_device *pdev;\n\tvoid *rgmii_base;\n\tint (*configure_func)(struct qcom_ethqos *, int);\n\tunsigned int link_clk_rate;\n\tstruct clk *link_clk;\n\tstruct phy *serdes_phy;\n\tint serdes_speed;\n\tphy_interface_t phy_mode;\n\tconst struct ethqos_emac_por *por;\n\tunsigned int num_por;\n\tbool rgmii_config_loopback_en;\n\tbool has_emac_ge_3;\n\tbool needs_sgmii_loopback;\n};\n\nstruct qcom_hwspinlock_of_data {\n\tu32 offset;\n\tu32 stride;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct qcom_icc_node;\n\nstruct rpm_clk_resource;\n\nstruct qcom_icc_desc {\n\tstruct qcom_icc_node * const *nodes;\n\tsize_t num_nodes;\n\tconst struct rpm_clk_resource *bus_clk_desc;\n\tconst char * const *intf_clocks;\n\tsize_t num_intf_clocks;\n\tbool keep_alive;\n\tenum qcom_icc_type type;\n\tconst struct regmap_config *regmap_cfg;\n\tunsigned int qos_offset;\n\tu16 ab_coeff;\n\tu16 ib_coeff;\n};\n\nstruct qcom_icc_hws_data {\n\tint master_id;\n\tint slave_id;\n\tint clk_id;\n};\n\nstruct qcom_icc_qos {\n\tu32 areq_prio;\n\tu32 prio_level;\n\tbool limit_commands;\n\tbool ap_owned;\n\tint qos_mode;\n\tint qos_port;\n\tbool urg_fwd_en;\n};\n\nstruct qcom_icc_node {\n\tunsigned char *name;\n\tu16 id;\n\tconst u16 *links;\n\tu16 num_links;\n\tu16 channels;\n\tu16 buswidth;\n\tconst struct rpm_clk_resource *bus_clk_desc;\n\tu64 sum_avg[2];\n\tu64 max_peak[2];\n\tint mas_rpm_id;\n\tint slv_rpm_id;\n\tstruct qcom_icc_qos qos;\n\tu16 ab_coeff;\n\tu16 ib_coeff;\n\tu32 bus_clk_rate[2];\n\tlong: 32;\n};\n\nstruct qcom_icc_provider {\n\tstruct icc_provider provider;\n\tint num_intf_clks;\n\tenum qcom_icc_type type;\n\tstruct regmap *regmap;\n\tunsigned int qos_offset;\n\tu16 ab_coeff;\n\tu16 ib_coeff;\n\tu32 bus_clk_rate[2];\n\tconst struct rpm_clk_resource *bus_clk_desc;\n\tstruct clk *bus_clk;\n\tstruct clk_bulk_data *intf_clks;\n\tbool keep_alive;\n\tbool is_on;\n};\n\nstruct qcom_iommu_ctx {\n\tstruct device *dev;\n\tvoid *base;\n\tbool secure_init;\n\tbool secured_ctx;\n\tu8 asid;\n\tstruct iommu_domain *domain;\n};\n\nstruct qcom_iommu_dev {\n\tstruct iommu_device iommu;\n\tstruct device *dev;\n\tstruct clk_bulk_data clks[3];\n\tvoid *local_base;\n\tu32 sec_id;\n\tu8 max_asid;\n\tstruct qcom_iommu_ctx *ctxs[0];\n};\n\nstruct qcom_iommu_domain {\n\tstruct io_pgtable_ops *pgtbl_ops;\n\tspinlock_t pgtbl_lock;\n\tstruct mutex init_mutex;\n\tstruct iommu_domain domain;\n\tstruct qcom_iommu_dev *iommu;\n\tstruct iommu_fwspec *fwspec;\n};\n\nstruct qcom_ipcc_chan_info;\n\nstruct qcom_ipcc {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct irq_domain *irq_domain;\n\tstruct mbox_chan *chans;\n\tstruct qcom_ipcc_chan_info *mchan;\n\tlong: 32;\n\tstruct mbox_controller mbox;\n\tint num_chans;\n\tint irq;\n};\n\nstruct qcom_ipcc_chan_info {\n\tu16 client_id;\n\tu16 signal_id;\n};\n\nstruct qcom_phy_hw_stats {\n\tu64 rx_pkts;\n\tu64 rx_err_pkts;\n\tu64 tx_pkts;\n\tu64 tx_err_pkts;\n};\n\nstruct reboot_mode_driver {\n\tstruct device *dev;\n\tstruct list_head head;\n\tint (*write)(struct reboot_mode_driver *, unsigned int);\n\tstruct notifier_block reboot_notifier;\n};\n\nstruct qcom_pon {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tu32 baseaddr;\n\tstruct reboot_mode_driver reboot_mode;\n\tlong int reason_shift;\n};\n\nstruct qcom_reset_map {\n\tunsigned int reg;\n\tu8 bit;\n\tu16 udelay;\n\tu32 bitmask;\n};\n\nstruct qcom_rpm_data;\n\nstruct qcom_rpm {\n\tstruct device *dev;\n\tstruct regmap *ipc_regmap;\n\tunsigned int ipc_offset;\n\tunsigned int ipc_bit;\n\tstruct clk *ramclk;\n\tstruct completion ack;\n\tstruct mutex lock;\n\tvoid *status_regs;\n\tvoid *ctrl_regs;\n\tvoid *req_regs;\n\tu32 ack_status;\n\tconst struct qcom_rpm_data *data;\n};\n\nstruct qcom_rpm_resource;\n\nstruct qcom_rpm_data {\n\tu32 version;\n\tconst struct qcom_rpm_resource *resource_table;\n\tunsigned int n_resources;\n\tunsigned int req_ctx_off;\n\tunsigned int req_sel_off;\n\tunsigned int ack_ctx_off;\n\tunsigned int ack_sel_off;\n\tunsigned int req_sel_size;\n\tunsigned int ack_sel_size;\n};\n\nstruct qcom_rpm_header {\n\t__le32 service_type;\n\t__le32 length;\n};\n\nstruct qcom_rpm_message {\n\t__le32 msg_type;\n\t__le32 length;\n\tunion {\n\t\t__le32 msg_id;\n\t\tstruct {\n\t\t\tstruct {} __empty_message;\n\t\t\tu8 message[0];\n\t\t};\n\t};\n};\n\nstruct rpm_reg_parts;\n\nstruct qcom_rpm_reg {\n\tstruct qcom_rpm *rpm;\n\tstruct mutex lock;\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tconst struct rpm_reg_parts *parts;\n\tint resource;\n\tu32 val[2];\n\tint uV;\n\tint is_enabled;\n\tbool supports_force_mode_auto;\n\tbool supports_force_mode_bypass;\n};\n\nstruct qcom_rpm_reg___2 {\n\tstruct device *dev;\n\tu32 type;\n\tu32 id;\n\tstruct regulator_desc desc;\n\tint is_enabled;\n\tint uV;\n\tu32 load;\n\tunsigned int enabled_updated: 1;\n\tunsigned int uv_updated: 1;\n\tunsigned int load_updated: 1;\n};\n\nstruct qcom_rpm_request {\n\t__le32 msg_id;\n\t__le32 flags;\n\t__le32 type;\n\t__le32 id;\n\t__le32 data_len;\n};\n\nstruct qcom_rpm_resource {\n\tunsigned int target_id;\n\tunsigned int status_id;\n\tunsigned int select_id;\n\tunsigned int size;\n};\n\nstruct qcom_tzmem_pool;\n\nstruct qcom_scm {\n\tstruct device *dev;\n\tstruct clk *core_clk;\n\tstruct clk *iface_clk;\n\tstruct clk *bus_clk;\n\tstruct icc_path *path;\n\tstruct completion *waitq_comps;\n\tstruct reset_controller_dev reset;\n\tstruct mutex scm_bw_lock;\n\tint scm_vote_count;\n\tu64 dload_mode_addr;\n\tstruct qcom_tzmem_pool *mempool;\n\tunsigned int wq_cnt;\n};\n\nstruct qcom_scm_current_perm_info {\n\t__le32 vmid;\n\t__le32 perm;\n\t__le64 ctx;\n\t__le32 ctx_size;\n\t__le32 unused;\n};\n\nstruct qcom_scm_desc {\n\tu32 svc;\n\tu32 cmd;\n\tu32 arginfo;\n\tlong: 32;\n\tu64 args[10];\n\tu32 owner;\n\tlong: 32;\n};\n\nstruct qcom_scm_hdcp_req {\n\tu32 addr;\n\tu32 val;\n};\n\nstruct qcom_scm_mem_map_info {\n\t__le64 mem_addr;\n\t__le64 mem_size;\n};\n\nstruct qcom_scm_pas_context {\n\tstruct device *dev;\n\tu32 pas_id;\n\tphys_addr_t mem_phys;\n\tsize_t mem_size;\n\tvoid *ptr;\n\tdma_addr_t phys;\n\tssize_t size;\n\tbool use_tzmem;\n};\n\nstruct qcom_scm_res {\n\tu64 result[3];\n};\n\nstruct qcom_scm_vmperm {\n\tint vmid;\n\tint perm;\n};\n\nstruct qcom_smd_alloc_entry {\n\tu8 name[20];\n\t__le32 cid;\n\t__le32 flags;\n\t__le32 ref_count;\n};\n\nstruct qcom_smd_edge;\n\nstruct qcom_smd_endpoint;\n\nstruct smd_channel_info_pair;\n\nstruct smd_channel_info_word_pair;\n\nstruct qcom_smd_channel {\n\tstruct qcom_smd_edge *edge;\n\tstruct qcom_smd_endpoint *qsept;\n\tbool registered;\n\tchar *name;\n\tenum smd_channel_state state;\n\tenum smd_channel_state remote_state;\n\twait_queue_head_t state_change_event;\n\tstruct smd_channel_info_pair *info;\n\tstruct smd_channel_info_word_pair *info_word;\n\tspinlock_t tx_lock;\n\twait_queue_head_t fblockread_event;\n\tvoid *tx_fifo;\n\tvoid *rx_fifo;\n\tint fifo_size;\n\tvoid *bounce_buffer;\n\tspinlock_t recv_lock;\n\tint pkt_size;\n\tvoid *drvdata;\n\tstruct list_head list;\n};\n\nstruct rpmsg_device_id {\n\tchar name[32];\n\tkernel_ulong_t driver_data;\n};\n\nstruct rpmsg_endpoint;\n\nstruct rpmsg_device_ops;\n\nstruct rpmsg_device {\n\tstruct device dev;\n\tstruct rpmsg_device_id id;\n\tconst char *driver_override;\n\tu32 src;\n\tu32 dst;\n\tstruct rpmsg_endpoint *ept;\n\tbool announce;\n\tbool little_endian;\n\tconst struct rpmsg_device_ops *ops;\n\tlong: 32;\n};\n\nstruct qcom_smd_device {\n\tstruct rpmsg_device rpdev;\n\tstruct qcom_smd_edge *edge;\n\tlong: 32;\n};\n\nstruct qcom_smd_edge {\n\tstruct device dev;\n\tconst char *name;\n\tstruct device_node *of_node;\n\tunsigned int edge_id;\n\tunsigned int remote_pid;\n\tint irq;\n\tstruct regmap *ipc_regmap;\n\tint ipc_offset;\n\tint ipc_bit;\n\tstruct mbox_client mbox_client;\n\tstruct mbox_chan *mbox_chan;\n\tstruct list_head channels;\n\tspinlock_t channels_lock;\n\tlong unsigned int allocated[4];\n\tunsigned int smem_available;\n\twait_queue_head_t new_channel_event;\n\tstruct work_struct scan_work;\n\tstruct work_struct state_work;\n\tlong: 32;\n};\n\ntypedef int (*rpmsg_rx_cb_t)(struct rpmsg_device *, void *, int, void *, u32);\n\ntypedef int (*rpmsg_flowcontrol_cb_t)(struct rpmsg_device *, void *, bool);\n\nstruct rpmsg_endpoint_ops;\n\nstruct rpmsg_endpoint {\n\tstruct rpmsg_device *rpdev;\n\tstruct kref refcount;\n\trpmsg_rx_cb_t cb;\n\trpmsg_flowcontrol_cb_t flow_cb;\n\tstruct mutex cb_lock;\n\tu32 addr;\n\tvoid *priv;\n\tconst struct rpmsg_endpoint_ops *ops;\n};\n\nstruct qcom_smd_endpoint {\n\tstruct rpmsg_endpoint ept;\n\tstruct qcom_smd_channel *qsch;\n};\n\nstruct qcom_smd_rpm {\n\tstruct rpmsg_endpoint *rpm_channel;\n\tstruct device *dev;\n\tstruct completion ack;\n\tstruct mutex lock;\n\tint ack_status;\n};\n\nstruct smem_partition {\n\tvoid *virt_base;\n\tphys_addr_t phys_base;\n\tsize_t cacheline;\n\tsize_t size;\n};\n\nstruct smem_region {\n\tphys_addr_t aux_base;\n\tvoid *virt_base;\n\tsize_t size;\n};\n\nstruct smem_ptable;\n\nstruct qcom_smem {\n\tstruct device *dev;\n\tstruct hwspinlock *hwlock;\n\tu32 item_count;\n\tstruct platform_device *socinfo;\n\tstruct smem_ptable *ptable;\n\tstruct smem_partition global_partition;\n\tstruct smem_partition partitions[25];\n\tunsigned int num_regions;\n\tstruct smem_region regions[0];\n};\n\nstruct qcom_smem_state_ops {\n\tint (*update_bits)(void *, u32, u32);\n};\n\nstruct qcom_smem_state {\n\tstruct kref refcount;\n\tbool orphan;\n\tstruct list_head list;\n\tstruct device_node *of_node;\n\tvoid *priv;\n\tstruct qcom_smem_state_ops ops;\n};\n\nstruct smp2p_smem_item;\n\nstruct qcom_smp2p {\n\tstruct device *dev;\n\tstruct smp2p_smem_item *in;\n\tstruct smp2p_smem_item *out;\n\tunsigned int smem_items[2];\n\tunsigned int valid_entries;\n\tbool ssr_ack_enabled;\n\tbool ssr_ack;\n\tbool negotiation_done;\n\tunsigned int local_pid;\n\tunsigned int remote_pid;\n\tstruct regmap *ipc_regmap;\n\tint ipc_offset;\n\tint ipc_bit;\n\tstruct mbox_client mbox_client;\n\tstruct mbox_chan *mbox_chan;\n\tstruct list_head inbound;\n\tstruct list_head outbound;\n};\n\nstruct smsm_entry;\n\nstruct smsm_host;\n\nstruct qcom_smsm {\n\tstruct device *dev;\n\tu32 local_host;\n\tu32 num_hosts;\n\tu32 num_entries;\n\tu32 *local_state;\n\tu32 *subscription;\n\tstruct qcom_smem_state *state;\n\tspinlock_t lock;\n\tstruct smsm_entry *entries;\n\tstruct smsm_host *hosts;\n\tstruct mbox_client mbox_client;\n};\n\nstruct qcom_spmi_pmic {\n\tunsigned int type;\n\tunsigned int subtype;\n\tunsigned int major;\n\tunsigned int minor;\n\tunsigned int rev2;\n\tunsigned int fab_id;\n\tconst char *name;\n};\n\nstruct qcom_spmi_dev {\n\tint num_usids;\n\tstruct qcom_spmi_pmic pmic;\n};\n\nstruct qcom_tzmem_area {\n\tstruct list_head list;\n\tvoid *vaddr;\n\tdma_addr_t paddr;\n\tsize_t size;\n\tvoid *priv;\n};\n\nstruct qcom_tzmem_chunk {\n\tsize_t size;\n\tstruct qcom_tzmem_pool *owner;\n};\n\nstruct qcom_tzmem_pool {\n\tstruct gen_pool *genpool;\n\tstruct list_head areas;\n\tenum qcom_tzmem_policy policy;\n\tsize_t increment;\n\tsize_t max_size;\n\tspinlock_t lock;\n};\n\nstruct qcom_tzmem_pool_config {\n\tsize_t initial_size;\n\tenum qcom_tzmem_policy policy;\n\tsize_t increment;\n\tsize_t max_size;\n};\n\nstruct ulpi_seq;\n\nstruct qcom_usb_hs_phy {\n\tstruct ulpi *ulpi;\n\tstruct phy *phy;\n\tstruct clk *ref_clk;\n\tstruct clk *sleep_clk;\n\tstruct regulator *v1p8;\n\tstruct regulator *v3p3;\n\tstruct reset_control *reset;\n\tstruct ulpi_seq *init_seq;\n\tstruct extcon_dev *vbus_edev;\n\tstruct notifier_block vbus_notify;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct qfprom_soc_data;\n\nstruct qfprom_priv {\n\tvoid *qfpraw;\n\tvoid *qfpconf;\n\tvoid *qfpcorrected;\n\tvoid *qfpsecurity;\n\tstruct device *dev;\n\tstruct clk *secclk;\n\tstruct regulator *vcc;\n\tconst struct qfprom_soc_data *soc_data;\n};\n\nstruct qfprom_soc_compatible_data {\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n};\n\nstruct qfprom_soc_data {\n\tu32 accel_value;\n\tu32 qfprom_blow_timer_value;\n\tu32 qfprom_blow_set_freq;\n\tint qfprom_blow_uV;\n};\n\nstruct qfprom_touched_values {\n\tlong unsigned int clk_rate;\n\tu32 accel_val;\n\tu32 timer_val;\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quirk_entry {\n\tu16 vid;\n\tu16 pid;\n\tu32 flags;\n};\n\nstruct quirks_list_struct {\n\tstruct hid_device_id hid_bl_item;\n\tstruct list_head node;\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n\tlong: 32;\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct qup_i2c_tag {\n\tu8 *start;\n\tdma_addr_t addr;\n};\n\nstruct qup_i2c_bam {\n\tstruct qup_i2c_tag tag;\n\tstruct dma_chan *dma;\n\tstruct scatterlist *sg;\n\tunsigned int sg_cnt;\n};\n\nstruct qup_i2c_block {\n\tint count;\n\tint pos;\n\tint tx_tag_len;\n\tint rx_tag_len;\n\tint data_len;\n\tint cur_blk_len;\n\tint total_tx_len;\n\tint total_rx_len;\n\tint tx_fifo_data_pos;\n\tint tx_fifo_free;\n\tint rx_fifo_data_pos;\n\tint fifo_available;\n\tu32 tx_fifo_data;\n\tu32 rx_fifo_data;\n\tu8 *cur_data;\n\tu8 *cur_tx_tags;\n\tbool tx_tags_sent;\n\tbool send_last_word;\n\tbool rx_tags_fetched;\n\tbool rx_bytes_read;\n\tbool is_tx_blk_mode;\n\tbool is_rx_blk_mode;\n\tu8 tags[6];\n};\n\nstruct qup_i2c_dev {\n\tstruct device *dev;\n\tvoid *base;\n\tint irq;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct icc_path *icc_path;\n\tstruct i2c_adapter adap;\n\tint clk_ctl;\n\tint out_fifo_sz;\n\tint in_fifo_sz;\n\tint out_blk_sz;\n\tint in_blk_sz;\n\tint blk_xfer_limit;\n\tlong unsigned int one_byte_t;\n\tlong unsigned int xfer_timeout;\n\tstruct qup_i2c_block blk;\n\tstruct i2c_msg *msg;\n\tint pos;\n\tu32 bus_err;\n\tu32 qup_err;\n\tbool is_last;\n\tbool is_smbus_read;\n\tu32 config_run;\n\tu32 src_clk_freq;\n\tu32 cur_bw_clk_freq;\n\tbool is_dma;\n\tbool use_dma;\n\tunsigned int max_xfer_sg_len;\n\tunsigned int tag_buf_pos;\n\tunsigned int blk_mode_threshold;\n\tstruct dma_pool *dpool;\n\tstruct qup_i2c_tag start_tag;\n\tstruct qup_i2c_bam brx;\n\tstruct qup_i2c_bam btx;\n\tstruct completion xfer;\n\tvoid (*write_tx_fifo)(struct qup_i2c_dev *);\n\tvoid (*read_rx_fifo)(struct qup_i2c_dev *);\n\tvoid (*write_rx_tags)(struct qup_i2c_dev *);\n\tlong: 32;\n};\n\nstruct r8a73a4_cpg {\n\tstruct clk_onecell_data data;\n\tspinlock_t lock;\n};\n\nstruct r8a7740_cpg {\n\tstruct clk_onecell_data data;\n\tspinlock_t lock;\n};\n\nstruct r8a7740_portcr_group {\n\tunsigned int end_pin;\n\tunsigned int offset;\n};\n\nstruct regbit {\n\tu16 bit: 5;\n\tu16 reg: 11;\n};\n\nstruct r9a06g032_priv;\n\nstruct r9a06g032_clk_bitsel {\n\tstruct clk_hw hw;\n\tstruct r9a06g032_priv *clocks;\n\tu16 index;\n\tstruct regbit selector;\n};\n\nstruct r9a06g032_clk_div {\n\tstruct clk_hw hw;\n\tstruct r9a06g032_priv *clocks;\n\tu16 index;\n\tu16 reg;\n\tu16 min;\n\tu16 max;\n\tu8 table_size;\n\tu16 table[8];\n};\n\nstruct r9a06g032_gate {\n\tstruct regbit gate;\n\tstruct regbit reset;\n\tstruct regbit ready;\n\tstruct regbit midle;\n};\n\nstruct r9a06g032_clk_dualgate {\n\tstruct clk_hw hw;\n\tstruct r9a06g032_priv *clocks;\n\tu16 index;\n\tstruct regbit selector;\n\tstruct r9a06g032_gate gate[2];\n};\n\nstruct r9a06g032_clk_gate {\n\tstruct clk_hw hw;\n\tstruct r9a06g032_priv *clocks;\n\tu16 index;\n\tstruct r9a06g032_gate gate;\n};\n\nstruct r9a06g032_clkdesc {\n\tconst char *name;\n\tuint32_t managed: 1;\n\tenum gate_type type: 3;\n\tuint32_t index: 8;\n\tuint32_t source: 8;\n\tunion {\n\t\tstruct r9a06g032_gate gate;\n\t\tstruct {\n\t\t\tunsigned int min: 10;\n\t\t\tunsigned int max: 10;\n\t\t\tunsigned int reg: 10;\n\t\t\tu16 table[4];\n\t\t} div;\n\t\tstruct {\n\t\t\tu16 div;\n\t\t\tu16 mul;\n\t\t} ffc;\n\t\tstruct {\n\t\t\tuint16_t group: 1;\n\t\t\tstruct regbit sel;\n\t\t\tstruct regbit g1;\n\t\t\tstruct regbit r1;\n\t\t\tstruct regbit g2;\n\t\t\tstruct regbit r2;\n\t\t} dual;\n\t};\n};\n\nstruct r9a06g032_priv {\n\tstruct clk_onecell_data data;\n\tspinlock_t lock;\n\tvoid *reg;\n};\n\nstruct ra_msg {\n\tstruct icmp6hdr icmph;\n\t__be32 reachable_time;\n\t__be32 retrans_timer;\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct rail_alignment {\n\tint offset_uv;\n\tint step_uv;\n};\n\nstruct ramc_info {\n\tvoid (*idle)(void);\n\tunsigned int memctrl;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct ramoops_context {\n\tstruct persistent_ram_zone **dprzs;\n\tstruct persistent_ram_zone *cprz;\n\tstruct persistent_ram_zone **fprzs;\n\tstruct persistent_ram_zone *mprz;\n\tphys_addr_t phys_addr;\n\tlong unsigned int size;\n\tunsigned int memtype;\n\tsize_t record_size;\n\tsize_t console_size;\n\tsize_t ftrace_size;\n\tsize_t pmsg_size;\n\tu32 flags;\n\tstruct persistent_ram_ecc_info ecc_info;\n\tunsigned int max_dump_cnt;\n\tunsigned int dump_write_cnt;\n\tunsigned int dump_read_cnt;\n\tunsigned int console_read_cnt;\n\tunsigned int max_ftrace_cnt;\n\tunsigned int ftrace_read_cnt;\n\tunsigned int pmsg_read_cnt;\n\tstruct pstore_info pstore;\n};\n\nstruct ramoops_platform_data {\n\tlong unsigned int mem_size;\n\tphys_addr_t mem_address;\n\tunsigned int mem_type;\n\tlong unsigned int record_size;\n\tlong unsigned int console_size;\n\tlong unsigned int ftrace_size;\n\tlong unsigned int pmsg_size;\n\tint max_reason;\n\tu32 flags;\n\tstruct persistent_ram_ecc_info ecc_info;\n};\n\nstruct range_t {\n\tint start;\n\tint end;\n};\n\nstruct rank_info {\n\tint chan_idx;\n\tstruct csrow_info *csrow;\n\tstruct dimm_info *dimm;\n\tu32 ce_count;\n};\n\nstruct rpi_firmware;\n\nstruct raspberrypi_clk {\n\tstruct device *dev;\n\tstruct rpi_firmware *firmware;\n\tstruct platform_device *cpufreq;\n};\n\nstruct raspberrypi_clk_variant;\n\nstruct raspberrypi_clk_data {\n\tstruct clk_hw hw;\n\tunsigned int id;\n\tstruct raspberrypi_clk_variant *variant;\n\tstruct raspberrypi_clk *rpi;\n};\n\nstruct raspberrypi_clk_variant {\n\tbool export;\n\tchar *clkdev;\n\tlong unsigned int min_rate;\n\tbool minimize;\n\tbool maximize;\n\tu32 flags;\n};\n\nstruct raspberrypi_firmware_prop {\n\t__le32 id;\n\t__le32 val;\n\t__le32 disable_turbo;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n\tlong: 32;\n};\n\nstruct ravb_desc {\n\t__le16 ds;\n\tu8 cc;\n\tu8 die_dt;\n\t__le32 dptr;\n};\n\nstruct ravb_ex_rx_desc {\n\t__le16 ds_cc;\n\tu8 msc;\n\tu8 die_dt;\n\t__le32 dptr;\n\t__le32 ts_n;\n\t__le32 ts_sl;\n\t__le16 ts_sh;\n\t__le16 res;\n};\n\nstruct ravb_hw_info {\n\tint (*receive)(struct net_device *, int, int);\n\tvoid (*set_rate)(struct net_device *);\n\tint (*set_feature)(struct net_device *, netdev_features_t);\n\tint (*dmac_init)(struct net_device *);\n\tvoid (*emac_init)(struct net_device *);\n\tconst char (*gstrings_stats)[32];\n\tsize_t gstrings_size;\n\tlong: 32;\n\tnetdev_features_t net_hw_features;\n\tnetdev_features_t net_features;\n\tnetdev_features_t vlan_features;\n\tint stats_len;\n\tu32 tccr_mask;\n\tu32 tx_max_frame_size;\n\tu32 rx_max_frame_size;\n\tu32 rx_buffer_size;\n\tu32 rx_desc_size;\n\tu32 dbat_entry_num;\n\tunsigned int aligned_tx: 1;\n\tunsigned int coalesce_irqs: 1;\n\tunsigned int internal_delay: 1;\n\tunsigned int tx_counters: 1;\n\tunsigned int carrier_counters: 1;\n\tunsigned int multi_irqs: 1;\n\tunsigned int irq_en_dis: 1;\n\tunsigned int err_mgmt_irqs: 1;\n\tunsigned int gptp: 1;\n\tunsigned int ccc_gac: 1;\n\tunsigned int gptp_ref_clk: 1;\n\tunsigned int nc_queues: 1;\n\tunsigned int magic_pkt: 1;\n\tunsigned int half_duplex: 1;\n};\n\nstruct ravb_ptp_perout {\n\tu32 target;\n\tu32 period;\n};\n\nstruct ravb_ptp {\n\tstruct ptp_clock *clock;\n\tstruct ptp_clock_info info;\n\tu32 default_addend;\n\tu32 current_addend;\n\tint extts[1];\n\tstruct ravb_ptp_perout perout[1];\n};\n\nstruct ravb_rx_desc;\n\nstruct ravb_tx_desc;\n\nstruct ravb_rx_buffer;\n\nstruct ravb_private {\n\tstruct net_device *ndev;\n\tstruct platform_device *pdev;\n\tvoid *addr;\n\tstruct clk *clk;\n\tstruct clk *refclk;\n\tstruct clk *gptp_clk;\n\tstruct mdiobb_ctrl mdiobb;\n\tu32 num_rx_ring[2];\n\tu32 num_tx_ring[2];\n\tu32 desc_bat_size;\n\tdma_addr_t desc_bat_dma;\n\tstruct ravb_desc *desc_bat;\n\tdma_addr_t rx_desc_dma[2];\n\tdma_addr_t tx_desc_dma[2];\n\tunion {\n\t\tstruct ravb_rx_desc *desc;\n\t\tstruct ravb_ex_rx_desc *ex_desc;\n\t\tvoid *raw;\n\t} rx_ring[2];\n\tstruct ravb_tx_desc *tx_ring[2];\n\tvoid *tx_align[2];\n\tstruct sk_buff *rx_1st_skb;\n\tstruct page_pool *rx_pool[2];\n\tstruct ravb_rx_buffer *rx_buffers[2];\n\tstruct sk_buff **tx_skb[2];\n\tu32 rx_over_errors;\n\tu32 rx_fifo_errors;\n\tstruct net_device_stats stats[2];\n\tenum hwtstamp_tx_types tstamp_tx_ctrl;\n\tenum hwtstamp_rx_filters tstamp_rx_ctrl;\n\tstruct list_head ts_skb_list;\n\tu32 ts_skb_tag;\n\tstruct ravb_ptp ptp;\n\tspinlock_t lock;\n\tu32 cur_rx[2];\n\tu32 dirty_rx[2];\n\tu32 cur_tx[2];\n\tu32 dirty_tx[2];\n\tlong: 32;\n\tstruct napi_struct napi[2];\n\tstruct work_struct work;\n\tstruct mii_bus *mii_bus;\n\tint link;\n\tphy_interface_t phy_interface;\n\tint msg_enable;\n\tint speed;\n\tint emac_irq;\n\tunsigned int no_avb_link: 1;\n\tunsigned int avb_link_active_low: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int rxcidm: 1;\n\tunsigned int txcidm: 1;\n\tunsigned int rgmii_override: 1;\n\tunsigned int num_tx_desc;\n\tint duplex;\n\tconst struct ravb_hw_info *info;\n\tstruct reset_control *rstc;\n\tu32 gti_tiv;\n};\n\nstruct ravb_rx_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n};\n\nstruct ravb_rx_desc {\n\t__le16 ds_cc;\n\tu8 msc;\n\tu8 die_dt;\n\t__le32 dptr;\n};\n\nstruct ravb_tstamp_skb {\n\tstruct list_head list;\n\tstruct sk_buff *skb;\n\tu16 tag;\n};\n\nstruct ravb_tx_desc {\n\t__le16 ds_tagl;\n\tu8 tagh_tsr;\n\tu8 die_dt;\n\t__le32 dptr;\n};\n\nstruct raw6_frag_vec {\n\tstruct msghdr *msg;\n\tint hlen;\n\tchar c[4];\n};\n\nstruct raw6_sock {\n\tstruct inet_sock inet;\n\t__u32 checksum;\n\t__u32 offset;\n\tstruct icmp6_filter filter;\n\t__u32 ip6mr_table;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct numa_drop_counters drop_counters;\n\tstruct ipv6_pinfo inet6;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tlong: 32;\n\tlong: 32;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct uniqframe;\n\nstruct raw_sock___2 {\n\tstruct sock sk;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head notifier;\n\tint ifindex;\n\tunsigned int bound: 1;\n\tunsigned int loopback: 1;\n\tunsigned int recv_own_msgs: 1;\n\tunsigned int fd_frames: 1;\n\tunsigned int xl_frames: 1;\n\tunsigned int join_filters: 1;\n\tstruct can_raw_vcid_options raw_vcid_opts;\n\tcanid_t tx_vcid_shifted;\n\tcanid_t rx_vcid_shifted;\n\tcanid_t rx_vcid_mask_shifted;\n\tcan_err_mask_t err_mask;\n\tint count;\n\tstruct can_filter dfilter;\n\tstruct can_filter *filter;\n\tstruct uniqframe *uniq;\n\tlong: 32;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tu64 before;\n\tu64 after;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n\tlong: 32;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tatomic_t seq;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rb_time_struct {\n\tlocal64_t time;\n};\n\ntypedef struct rb_time_struct rb_time_t;\n\nstruct rb_wait_data {\n\tstruct rb_irq_work *irq_work;\n\tint seq;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct rc_map_table;\n\nstruct rc_map {\n\tstruct rc_map_table *scan;\n\tunsigned int size;\n\tunsigned int len;\n\tunsigned int alloc;\n\tenum rc_proto rc_proto;\n\tconst char *name;\n\tspinlock_t lock;\n};\n\nstruct ir_raw_event_ctrl;\n\nstruct rc_scancode_filter {\n\tu32 data;\n\tu32 mask;\n};\n\nstruct rc_dev {\n\tstruct device dev;\n\tbool managed_alloc;\n\tbool registered;\n\tbool idle;\n\tbool encode_wakeup;\n\tunsigned int minor;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst char *device_name;\n\tconst char *input_phys;\n\tstruct input_id input_id;\n\tconst char *driver_name;\n\tconst char *map_name;\n\tstruct rc_map rc_map;\n\tstruct mutex lock;\n\tstruct ir_raw_event_ctrl *raw;\n\tstruct input_dev *input_dev;\n\tenum rc_driver_type driver_type;\n\tu32 users;\n\tlong: 32;\n\tu64 allowed_protocols;\n\tu64 enabled_protocols;\n\tu64 allowed_wakeup_protocols;\n\tenum rc_proto wakeup_protocol;\n\tstruct rc_scancode_filter scancode_filter;\n\tstruct rc_scancode_filter scancode_wakeup_filter;\n\tu32 scancode_mask;\n\tvoid *priv;\n\tspinlock_t keylock;\n\tbool keypressed;\n\tu8 last_toggle;\n\tu32 last_keycode;\n\tenum rc_proto last_protocol;\n\tlong: 32;\n\tu64 last_scancode;\n\tlong unsigned int keyup_jiffies;\n\tstruct timer_list timer_keyup;\n\tstruct timer_list timer_repeat;\n\tu32 timeout;\n\tu32 min_timeout;\n\tu32 max_timeout;\n\tu32 rx_resolution;\n\tint (*change_protocol)(struct rc_dev *, u64 *);\n\tint (*open)(struct rc_dev *);\n\tvoid (*close)(struct rc_dev *);\n\tint (*s_tx_mask)(struct rc_dev *, u32);\n\tint (*s_tx_carrier)(struct rc_dev *, u32);\n\tint (*s_tx_duty_cycle)(struct rc_dev *, u32);\n\tint (*s_rx_carrier_range)(struct rc_dev *, u32, u32);\n\tint (*tx_ir)(struct rc_dev *, unsigned int *, unsigned int);\n\tvoid (*s_idle)(struct rc_dev *, bool);\n\tint (*s_wideband_receiver)(struct rc_dev *, int);\n\tint (*s_carrier_report)(struct rc_dev *, int);\n\tint (*s_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_wakeup_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_timeout)(struct rc_dev *, unsigned int);\n\tlong: 32;\n};\n\nstruct rc_map_table {\n\tu64 scancode;\n\tu32 keycode;\n\tlong: 32;\n};\n\nstruct rc_parameters {\n\tu16 initial_xmit_delay;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n};\n\nstruct rc_parameters_data {\n\tu8 bpp;\n\tu8 bpc;\n\tstruct rc_parameters params;\n};\n\nstruct rcar_dmac_chan;\n\nstruct rcar_dmac {\n\tstruct dma_device engine;\n\tstruct device *dev;\n\tvoid *dmac_base;\n\tvoid *chan_base;\n\tunsigned int n_channels;\n\tstruct rcar_dmac_chan *channels;\n\tu32 channels_mask;\n\tlong unsigned int modules[8];\n};\n\nstruct rcar_dmac_chan_slave {\n\tphys_addr_t slave_addr;\n\tunsigned int xfer_size;\n};\n\nstruct rcar_dmac_chan_map {\n\tdma_addr_t addr;\n\tenum dma_data_direction dir;\n\tstruct rcar_dmac_chan_slave slave;\n};\n\nstruct rcar_dmac_desc;\n\nstruct rcar_dmac_chan {\n\tstruct dma_chan chan;\n\tvoid *iomem;\n\tunsigned int index;\n\tint irq;\n\tstruct rcar_dmac_chan_slave src;\n\tstruct rcar_dmac_chan_slave dst;\n\tstruct rcar_dmac_chan_map map;\n\tint mid_rid;\n\tspinlock_t lock;\n\tstruct {\n\t\tstruct list_head free;\n\t\tstruct list_head pending;\n\t\tstruct list_head active;\n\t\tstruct list_head done;\n\t\tstruct list_head wait;\n\t\tstruct rcar_dmac_desc *running;\n\t\tstruct list_head chunks_free;\n\t\tstruct list_head pages;\n\t} desc;\n};\n\nstruct rcar_dmac_xfer_chunk;\n\nstruct rcar_dmac_hw_desc;\n\nstruct rcar_dmac_desc {\n\tstruct dma_async_tx_descriptor async_tx;\n\tenum dma_transfer_direction direction;\n\tunsigned int xfer_shift;\n\tu32 chcr;\n\tstruct list_head node;\n\tstruct list_head chunks;\n\tstruct rcar_dmac_xfer_chunk *running;\n\tunsigned int nchunks;\n\tstruct {\n\t\tbool use;\n\t\tstruct rcar_dmac_hw_desc *mem;\n\t\tdma_addr_t dma;\n\t\tsize_t size;\n\t} hwdescs;\n\tunsigned int size;\n\tbool cyclic;\n};\n\nstruct rcar_dmac_xfer_chunk {\n\tstruct list_head node;\n\tdma_addr_t src_addr;\n\tdma_addr_t dst_addr;\n\tu32 size;\n};\n\nstruct rcar_dmac_desc_page {\n\tstruct list_head node;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_descs;\n\t\t\tstruct rcar_dmac_desc descs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_chunks;\n\t\t\tstruct rcar_dmac_xfer_chunk chunks[0];\n\t\t};\n\t};\n};\n\nstruct rcar_dmac_hw_desc {\n\tu32 sar;\n\tu32 dar;\n\tu32 tcr;\n\tu32 reserved;\n};\n\nstruct rcar_dmac_of_data {\n\tu32 chan_offset_base;\n\tu32 chan_offset_stride;\n};\n\nstruct rcar_gen2_cpg_pll_config {\n\tu8 extal_div;\n\tu8 pll1_mult;\n\tu8 pll3_mult;\n\tu8 pll0_mult;\n};\n\nstruct rcar_i2c_priv {\n\tu32 flags;\n\tvoid *io;\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *msg;\n\tint msgs_left;\n\tstruct clk *clk;\n\twait_queue_head_t wait;\n\tint pos;\n\tu32 icccr;\n\tu16 schd;\n\tu16 scld;\n\tu8 smd;\n\tu8 recovery_icmcr;\n\tenum rcar_i2c_type devtype;\n\tstruct i2c_client *slave;\n\tstruct resource *res;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tstruct scatterlist sg;\n\tenum dma_data_direction dma_direction;\n\tstruct reset_control *rstc;\n\tint irq;\n\tstruct i2c_client *host_notify_client;\n\tu8 slave_flags;\n\tlong: 32;\n};\n\nstruct rcar_msi {\n\tlong unsigned int used[1];\n\tstruct irq_domain *domain;\n\tstruct mutex map_lock;\n\traw_spinlock_t mask_lock;\n\tint irq1;\n\tint irq2;\n};\n\nstruct rcar_pci {\n\tstruct device *dev;\n\tvoid *reg;\n\tstruct resource mem_res;\n\tstruct resource *cfg_res;\n\tint irq;\n};\n\nstruct rcar_pcie {\n\tstruct device *dev;\n\tvoid *base;\n};\n\nstruct rcar_pcie_host {\n\tstruct rcar_pcie pcie;\n\tstruct phy *phy;\n\tstruct clk *bus_clk;\n\tstruct rcar_msi msi;\n\tint (*phy_init_fn)(struct rcar_pcie_host *);\n};\n\nstruct rcar_pm_domains {\n\tstruct genpd_onecell_data onecell_data;\n\tstruct generic_pm_domain *domains[33];\n};\n\nstruct rcar_sysc_area {\n\tconst char *name;\n\tu16 chan_offs;\n\tu8 chan_bit;\n\tu8 isr_bit;\n\ts8 parent;\n\tu8 flags;\n};\n\nstruct rcar_sysc_info {\n\tint (*init)(void);\n\tconst struct rcar_sysc_area *areas;\n\tunsigned int num_areas;\n\tu32 extmask_offs;\n\tu32 extmask_val;\n};\n\nstruct rcar_sysc_pd {\n\tstruct generic_pm_domain genpd;\n\tu16 chan_offs;\n\tu8 chan_bit;\n\tu8 isr_bit;\n\tunsigned int flags;\n\tchar name[0];\n};\n\nstruct rcar_thermal_chip {\n\tunsigned int use_of_thermal: 1;\n\tunsigned int has_filonoff: 1;\n\tunsigned int irq_per_ch: 1;\n\tunsigned int needs_suspend_resume: 1;\n\tunsigned int nirqs;\n\tunsigned int ctemp_bands;\n};\n\nstruct rcar_thermal_common {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rcar_thermal_priv {\n\tvoid *base;\n\tstruct rcar_thermal_common *common;\n\tstruct thermal_zone_device *zone;\n\tconst struct rcar_thermal_chip *chip;\n\tstruct delayed_work work;\n\tstruct mutex lock;\n\tstruct list_head list;\n\tint id;\n};\n\nstruct rcec_ea {\n\tu8 nextbusn;\n\tu8 lastbusn;\n\tu32 bitmap;\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tlong: 32;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong: 32;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n\tlong: 32;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\traw_spinlock_t fqslock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[1];\n\tstruct rcu_node *level[2];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\tstruct in6_addr dest;\n\t__u8 opt[0];\n};\n\nstruct rdma_ah_init_attr {\n\tstruct rdma_ah_attr *ah_attr;\n\tu32 flags;\n\tstruct net_device *xmit_slave;\n};\n\nstruct rdma_counter {\n\tstruct rdma_restrack_entry res;\n\tstruct ib_device *device;\n\tuint32_t id;\n\tstruct kref kref;\n\tstruct rdma_counter_mode mode;\n\tstruct mutex lock;\n\tstruct rdma_hw_stats *stats;\n\tu32 port;\n};\n\nstruct rdma_stat_desc;\n\nstruct rdma_hw_stats {\n\tstruct mutex lock;\n\tlong unsigned int timestamp;\n\tlong unsigned int lifespan;\n\tconst struct rdma_stat_desc *descs;\n\tlong unsigned int *is_disabled;\n\tint num_counters;\n\tu64 value[0];\n};\n\nstruct rdma_link_ops {\n\tstruct list_head list;\n\tconst char *type;\n\tint (*newlink)(const char *, struct net_device *);\n};\n\nstruct rdma_netdev_alloc_params {\n\tsize_t sizeof_priv;\n\tunsigned int txqs;\n\tunsigned int rxqs;\n\tvoid *param;\n\tint (*initialize_rdma_netdev)(struct ib_device *, u32, struct net_device *, void *);\n};\n\nstruct rdma_stat_desc {\n\tconst char *name;\n\tunsigned int flags;\n\tconst void *priv;\n};\n\nstruct rdma_user_mmap_entry {\n\tstruct kref ref;\n\tstruct ib_ucontext *ucontext;\n\tlong unsigned int start_pgoff;\n\tsize_t npages;\n\tbool driver_removed;\n\tstruct mutex dmabufs_lock;\n\tstruct list_head dmabufs;\n};\n\nstruct read_plus_segment {\n\tenum data_content4 type;\n\tlong: 32;\n\tuint64_t offset;\n\tunion {\n\t\tstruct {\n\t\t\tuint64_t length;\n\t\t} hole;\n\t\tstruct {\n\t\t\tuint32_t length;\n\t\t\tunsigned int from;\n\t\t} data;\n\t};\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct reboot_mode_bits {\n\tu32 offset;\n\tu32 mask;\n\tu32 value;\n\tbool valid;\n};\n\nstruct reboot_data {\n\tstruct reboot_mode_bits mode_bits[4];\n\tstruct reboot_mode_bits catchall;\n};\n\nstruct virtnet_rq_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t drops;\n\tu64_stats_t xdp_packets;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_redirects;\n\tu64_stats_t xdp_drops;\n\tu64_stats_t kicks;\n};\n\nstruct virtnet_interrupt_coalesce {\n\tu32 max_packets;\n\tu32 max_usecs;\n};\n\nstruct virtnet_rq_dma;\n\nstruct receive_queue {\n\tstruct virtqueue *vq;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tlong: 32;\n\tstruct virtnet_rq_stats stats;\n\tu16 calls;\n\tbool dim_enabled;\n\tstruct mutex dim_lock;\n\tstruct dim dim;\n\tu32 packets_in_napi;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct page *pages;\n\tstruct ewma_pkt_len mrg_avg_pkt_len;\n\tstruct page_frag alloc_frag;\n\tstruct scatterlist sg[19];\n\tunsigned int min_buf_len;\n\tchar name[16];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct virtnet_rq_dma *last_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xsk_rxq_info;\n\tstruct xdp_buff **xsk_buffs;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct receiver {\n\tstruct hlist_node list;\n\tcanid_t can_id;\n\tcanid_t mask;\n\tlong unsigned int matches;\n\tvoid (*func)(struct sk_buff *, void *);\n\tvoid *data;\n\tchar *ident;\n\tstruct sock *sk;\n\tstruct callback_head rcu;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tlong unsigned int head_block;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\nstruct redist_region {\n\tvoid *redist_base;\n\tphys_addr_t phys_base;\n\tbool single_redist;\n};\n\nstruct referring_call {\n\tuint32_t rc_sequenceid;\n\tuint32_t rc_slotid;\n};\n\nstruct referring_call_list {\n\tstruct nfs4_sessionid rcl_sessionid;\n\tuint32_t rcl_nrefcalls;\n\tstruct referring_call *rcl_refcalls;\n};\n\nstruct reg_chan {\n\tu32 control;\n\tu32 mode;\n\tu32 __rsvd[6];\n};\n\nstruct shdwc_reg_config {\n\tu8 wkup_pin_input;\n\tu8 mr_rtcwk_shift;\n\tu8 mr_rttwk_shift;\n\tu8 sr_rtcwk_shift;\n\tu8 sr_rttwk_shift;\n};\n\nstruct reg_config {\n\tstruct shdwc_reg_config shdwc;\n\tstruct pmc_reg_config pmc;\n\tstruct ddrc_reg_config ddrc;\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_entry {\n\tlong unsigned int offset;\n\tlong unsigned int value;\n};\n\nstruct reg_global {\n\tu32 revision;\n\tu32 perf_control;\n\tu32 emulation_control;\n\tu32 priority_control;\n\tu32 qm_base_address[4];\n};\n\nstruct reg_offset_data {\n\tu32 base_offset;\n\tunsigned int pipe_mult;\n\tunsigned int evnt_mult;\n\tunsigned int ee_mult;\n};\n\nstruct reg_value;\n\nstruct reg_property {\n\tconst char *name;\n\tconst struct reg_value *values;\n\tsize_t num_values;\n\tu32 def_value;\n\tu32 set_value;\n};\n\nstruct reg_rx_flow {\n\tu32 control;\n\tu32 tags;\n\tu32 tag_sel;\n\tu32 fdq_sel[2];\n\tu32 thresh[3];\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nstruct reg_tx_sched {\n\tu32 prio;\n};\n\nstruct reg_value {\n\tu32 of_value;\n\tu32 reg_value;\n};\n\nstruct regcache_flat_data {\n\tlong unsigned int *valid;\n\tunsigned int data[0];\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tint (*populate)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regcache_rbtree_node;\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong unsigned int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\nstruct region_info_user {\n\t__u32 offset;\n\t__u32 erasesize;\n\t__u32 numblocks;\n\t__u32 regionindex;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\ts8 reg_shift;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct regmap_bus;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_spinlock;\n\t\t\tlong unsigned int raw_spinlock_flags;\n\t\t};\n\t};\n\tstruct lock_class_key *lock_key;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tunsigned int reg_base;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool async;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool max_register_is_set;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tbool defer_caching;\n\tbool force_write_field;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool can_sleep;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regmap_range;\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\nstruct regmap_async_spi {\n\tstruct regmap_async core;\n\tstruct spi_message m;\n\tstruct spi_transfer t[2];\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_noinc_write)(void *, unsigned int, const void *, size_t);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_noinc_read)(void *, unsigned int, void *, size_t);\n\ntypedef void (*regmap_hw_free_context)(void *);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)(void);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tbool free_on_exit;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_noinc_write reg_noinc_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_reg_noinc_read reg_noinc_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint reg_shift;\n\tunsigned int reg_base;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tbool can_sleep;\n\tbool fast_io;\n\tbool io_port;\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tunsigned int max_register;\n\tbool max_register_is_0;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool use_relaxed_mmio;\n\tbool can_multi_write;\n\tbool use_hwlock;\n\tbool use_raw_spinlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tstruct list_head link;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_irq_type {\n\tunsigned int type_reg_offset;\n\tunsigned int type_reg_mask;\n\tunsigned int type_rising_val;\n\tunsigned int type_falling_val;\n\tunsigned int type_level_low_val;\n\tunsigned int type_level_high_val;\n\tunsigned int types_supported;\n};\n\nstruct regmap_irq {\n\tunsigned int reg_offset;\n\tunsigned int mask;\n\tstruct regmap_irq_type type;\n};\n\nstruct regmap_irq_sub_irq_map;\n\nstruct regmap_irq_chip {\n\tconst char *name;\n\tconst char *domain_suffix;\n\tunsigned int main_status;\n\tunsigned int num_main_status_bits;\n\tconst struct regmap_irq_sub_irq_map *sub_reg_offsets;\n\tint num_main_regs;\n\tunsigned int status_base;\n\tunsigned int mask_base;\n\tunsigned int unmask_base;\n\tunsigned int ack_base;\n\tunsigned int wake_base;\n\tconst unsigned int *config_base;\n\tunsigned int irq_reg_stride;\n\tunsigned int init_ack_masked: 1;\n\tunsigned int mask_unmask_non_inverted: 1;\n\tunsigned int use_ack: 1;\n\tunsigned int ack_invert: 1;\n\tunsigned int clear_ack: 1;\n\tunsigned int status_invert: 1;\n\tunsigned int status_is_level: 1;\n\tunsigned int wake_invert: 1;\n\tunsigned int type_in_mask: 1;\n\tunsigned int clear_on_unmask: 1;\n\tunsigned int runtime_pm: 1;\n\tunsigned int no_status: 1;\n\tint num_regs;\n\tconst struct regmap_irq *irqs;\n\tint num_irqs;\n\tint num_config_bases;\n\tint num_config_regs;\n\tint (*handle_pre_irq)(void *);\n\tint (*handle_post_irq)(void *);\n\tint (*handle_mask_sync)(int, unsigned int, unsigned int, void *);\n\tint (*set_type_config)(unsigned int **, unsigned int, const struct regmap_irq *, int, void *);\n\tunsigned int (*get_irq_reg)(struct regmap_irq_chip_data *, unsigned int, int);\n\tvoid *irq_drv_data;\n};\n\nstruct regmap_irq_chip_data {\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tstruct irq_chip irq_chip;\n\tstruct regmap *map;\n\tconst struct regmap_irq_chip *chip;\n\tint irq_base;\n\tstruct irq_domain *domain;\n\tint irq;\n\tint wake_count;\n\tvoid *status_reg_buf;\n\tunsigned int *main_status_buf;\n\tunsigned int *status_buf;\n\tunsigned int *prev_status_buf;\n\tunsigned int *mask_buf;\n\tunsigned int *mask_buf_def;\n\tunsigned int *wake_buf;\n\tunsigned int *type_buf;\n\tunsigned int *type_buf_def;\n\tunsigned int **config_buf;\n\tunsigned int irq_reg_stride;\n\tunsigned int (*get_irq_reg)(struct regmap_irq_chip_data *, unsigned int, int);\n\tunsigned int clear_status: 1;\n};\n\nstruct regmap_irq_sub_irq_map {\n\tunsigned int num_regs;\n\tunsigned int *offset;\n};\n\nstruct regmap_mmio_context {\n\tvoid *regs;\n\tunsigned int val_bytes;\n\tbool big_endian;\n\tbool attached_clk;\n\tstruct clk *clk;\n\tvoid (*reg_write)(struct regmap_mmio_context *, unsigned int, unsigned int);\n\tunsigned int (*reg_read)(struct regmap_mmio_context *, unsigned int);\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regulator_voltage {\n\tint min_uV;\n\tint max_uV;\n};\n\nstruct regulator {\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int always_on: 1;\n\tunsigned int bypass: 1;\n\tunsigned int device_link: 1;\n\tint uA_load;\n\tunsigned int enable_count;\n\tunsigned int deferred_disables;\n\tstruct regulator_voltage voltage[5];\n\tconst char *supply_name;\n\tstruct device_attribute dev_attr;\n\tstruct regulator_dev *rdev;\n\tstruct dentry *debugfs;\n};\n\nstruct regulator_bulk_devres {\n\tstruct regulator_bulk_data *consumers;\n\tint num_consumers;\n};\n\nstruct regulator_config {\n\tstruct device *dev;\n\tconst struct regulator_init_data *init_data;\n\tvoid *driver_data;\n\tstruct device_node *of_node;\n\tstruct regmap *regmap;\n\tstruct gpio_desc *ena_gpiod;\n};\n\nstruct regulator_consumer_supply {\n\tconst char *dev_name;\n\tconst char *supply;\n};\n\nstruct regulator_enable_gpio;\n\nstruct regulator_dev {\n\tconst struct regulator_desc *desc;\n\tint exclusive;\n\tu32 use_count;\n\tu32 open_count;\n\tu32 bypass_count;\n\tstruct list_head list;\n\tstruct list_head consumer_list;\n\tstruct coupling_desc coupling_desc;\n\tstruct blocking_notifier_head notifier;\n\tstruct ww_mutex mutex;\n\tstruct task_struct *mutex_owner;\n\tint ref_cnt;\n\tstruct module *owner;\n\tlong: 32;\n\tstruct device dev;\n\tstruct device bdev;\n\tstruct regulation_constraints *constraints;\n\tstruct regulator *supply;\n\tconst char *supply_name;\n\tstruct regmap *regmap;\n\tstruct delayed_work disable_work;\n\tvoid *reg_data;\n\tstruct dentry *debugfs;\n\tstruct regulator_enable_gpio *ena_pin;\n\tunsigned int ena_gpio_state: 1;\n\tunsigned int constraints_pending: 1;\n\tunsigned int is_switch: 1;\n\tlong: 32;\n\tktime_t last_off;\n\tint cached_err;\n\tbool use_cached_err;\n\tspinlock_t err_lock;\n\tint pw_requested_mW;\n\tstruct notifier_block supply_fwd_nb;\n\tlong: 32;\n};\n\nstruct regulator_enable_gpio {\n\tstruct list_head list;\n\tstruct gpio_desc *gpiod;\n\tu32 enable_count;\n\tu32 request_count;\n};\n\nstruct regulator_err_state {\n\tstruct regulator_dev *rdev;\n\tlong unsigned int notifs;\n\tlong unsigned int errors;\n\tint possible_errs;\n};\n\nstruct regulator_event_work {\n\tstruct work_struct work;\n\tstruct regulator_dev *rdev;\n\tlong unsigned int event;\n};\n\nstruct regulator_irq_data {\n\tstruct regulator_err_state *states;\n\tint num_states;\n\tvoid *data;\n\tlong int opaque;\n};\n\nstruct regulator_irq_desc {\n\tconst char *name;\n\tint fatal_cnt;\n\tint reread_ms;\n\tint irq_off_ms;\n\tbool skip_off;\n\tbool high_prio;\n\tvoid *data;\n\tint (*die)(struct regulator_irq_data *);\n\tint (*map_event)(int, struct regulator_irq_data *, long unsigned int *);\n\tint (*renable)(struct regulator_irq_data *);\n};\n\nstruct regulator_irq {\n\tstruct regulator_irq_data rdata;\n\tstruct regulator_irq_desc desc;\n\tint irq;\n\tint retry_cnt;\n\tstruct delayed_work isr_work;\n};\n\nstruct regulator_map {\n\tstruct list_head list;\n\tconst char *dev_name;\n\tconst char *supply;\n\tstruct regulator_dev *regulator;\n};\n\nstruct regulator_notifier_match {\n\tstruct regulator *regulator;\n\tstruct notifier_block *nb;\n};\n\nstruct regulator_quirk {\n\tstruct list_head list;\n\tconst struct of_device_id *id;\n\tstruct device_node *np;\n\tstruct of_phandle_args irq_args;\n\tstruct i2c_msg i2c_msg;\n\tbool shared;\n};\n\nstruct regulator_supply_alias {\n\tstruct list_head list;\n\tstruct device *src_dev;\n\tconst char *src_supply;\n\tstruct device *alias_dev;\n\tconst char *alias_supply;\n};\n\nstruct regulator_supply_alias_match {\n\tstruct device *dev;\n\tconst char *id;\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct renesas_family {\n\tconst char name[16];\n\tu32 reg;\n};\n\nstruct renesas_gbeth_of_data;\n\nstruct renesas_gbeth {\n\tconst struct renesas_gbeth_of_data *of_data;\n\tstruct plat_stmmacenet_data *plat_dat;\n\tstruct reset_control *rstc;\n\tstruct device *dev;\n};\n\nstruct renesas_gbeth_of_data {\n\tconst char * const *clks;\n\tu8 num_clks;\n\tu32 stmmac_flags;\n\tbool handle_reset;\n\tbool set_clk_tx_rate;\n\tbool has_pcs;\n};\n\nstruct renesas_id {\n\tunsigned int offset;\n\tu32 mask;\n};\n\nstruct tmio_mmc_data {\n\tvoid *chan_priv_tx;\n\tvoid *chan_priv_rx;\n\tunsigned int hclk;\n\tlong unsigned int capabilities;\n\tlong unsigned int capabilities2;\n\tlong unsigned int flags;\n\tu32 ocr_mask;\n\tdma_addr_t dma_rx_offset;\n\tunsigned int max_blk_count;\n\tshort unsigned int max_segs;\n};\n\nstruct tmio_mmc_host;\n\nstruct renesas_sdhi_dma {\n\tlong unsigned int end_flags;\n\tenum dma_slave_buswidth dma_buswidth;\n\tdma_filter_fn filter;\n\tvoid (*enable)(struct tmio_mmc_host *, bool);\n\tstruct completion dma_dataend;\n\tstruct work_struct dma_complete;\n};\n\nstruct renesas_sdhi_quirks;\n\nstruct renesas_sdhi {\n\tstruct clk *clk;\n\tstruct clk *clkh;\n\tstruct clk *clk_cd;\n\tstruct tmio_mmc_data mmc_data;\n\tstruct renesas_sdhi_dma dma_priv;\n\tconst struct renesas_sdhi_quirks *quirks;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_uhs;\n\tvoid *scc_ctl;\n\tu32 scc_tappos;\n\tu32 scc_tappos_hs400;\n\tconst u8 *adjust_hs400_calib_table;\n\tbool needs_adjust_hs400;\n\tbool card_is_sdio;\n\tlong unsigned int taps[1];\n\tlong unsigned int smpcmp[1];\n\tunsigned int tap_num;\n\tunsigned int tap_set;\n\tstruct reset_control *rstc;\n\tstruct tmio_mmc_host *host;\n\tstruct regulator_dev *rdev;\n};\n\nstruct renesas_sdhi_scc;\n\nstruct renesas_sdhi_of_data {\n\tlong unsigned int tmio_flags;\n\tu32 tmio_ocr_mask;\n\tlong unsigned int capabilities;\n\tlong unsigned int capabilities2;\n\tenum dma_slave_buswidth dma_buswidth;\n\tdma_addr_t dma_rx_offset;\n\tunsigned int bus_shift;\n\tint scc_offset;\n\tstruct renesas_sdhi_scc *taps;\n\tint taps_num;\n\tunsigned int max_blk_count;\n\tshort unsigned int max_segs;\n\tlong unsigned int sdhi_flags;\n};\n\nstruct renesas_sdhi_of_data_with_quirks {\n\tconst struct renesas_sdhi_of_data *of_data;\n\tconst struct renesas_sdhi_quirks *quirks;\n};\n\nstruct renesas_sdhi_quirks {\n\tbool hs400_disabled;\n\tbool hs400_4taps;\n\tbool fixed_addr_mode;\n\tbool dma_one_rx_only;\n\tbool manual_tap_correction;\n\tbool old_info1_layout;\n\tu32 hs400_bad_taps;\n\tconst u8 (*hs400_calib_table)[32];\n};\n\nstruct renesas_sdhi_scc {\n\tlong unsigned int clk_rate;\n\tu32 tap;\n\tu32 tap_hs400_4tap;\n};\n\nstruct renesas_soc {\n\tconst struct renesas_family *family;\n\tu32 id;\n};\n\nstruct repcodes_s {\n\tU32 rep[3];\n};\n\ntypedef struct repcodes_s Repcodes_t;\n\nstruct replay_entry {\n\tint lnum;\n\tint offs;\n\tint len;\n\tu8 hash[0];\n\tunsigned int deletion: 1;\n\tlong long unsigned int sqnum;\n\tstruct list_head list;\n\tunion ubifs_key key;\n\tunion {\n\t\tstruct fscrypt_name nm;\n\t\tstruct {\n\t\t\tloff_t old_size;\n\t\t\tloff_t new_size;\n\t\t};\n\t};\n};\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tlong: 32;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tlong: 32;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tlong: 32;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct request_member {\n\tint word;\n\tunsigned int mask;\n\tint shift;\n};\n\nstruct rq_qos;\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tstruct device *dev;\n\tenum rpm_status rpm_status;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\nstruct reserved_mem_ops;\n\nstruct reserved_mem {\n\tconst char *name;\n\tlong unsigned int fdt_node;\n\tconst struct reserved_mem_ops *ops;\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tvoid *priv;\n};\n\nstruct reserved_mem_ops {\n\tint (*device_init)(struct reserved_mem *, struct device *);\n\tvoid (*device_release)(struct reserved_mem *, struct device *);\n};\n\nstruct reset_control {\n\tstruct reset_controller_dev *rcdev;\n\tstruct list_head list;\n\tunsigned int id;\n\tstruct kref refcnt;\n\tbool acquired;\n\tbool shared;\n\tbool array;\n\tatomic_t deassert_count;\n\tatomic_t triggered_count;\n};\n\nstruct reset_control_array {\n\tstruct reset_control base;\n\tunsigned int num_rstcs;\n\tstruct reset_control *rstc[0];\n};\n\nstruct reset_control_bulk_devres {\n\tint num_rstcs;\n\tstruct reset_control_bulk_data *rstcs;\n};\n\nstruct reset_data {\n\tvoid *reg;\n\tspinlock_t *lock;\n\tstruct reset_controller_dev rcdev;\n\tu8 offset;\n};\n\nstruct reset_dom_info {\n\tbool async_reset;\n\tbool reset_notify;\n\tu32 latency_us;\n\tchar name[64];\n};\n\nstruct reset_props {\n\tu32 protect_reg;\n\tu32 protect_bit;\n\tu32 reset_reg;\n\tu32 reset_bit;\n};\n\nstruct reset_reg_mask {\n\tu32 rst_src_en_mask;\n\tu32 sw_mstr_rst_mask;\n};\n\nstruct reset_simple_devdata {\n\tu32 reg_offset;\n\tu32 nr_resets;\n\tbool active_low;\n\tbool status_active_low;\n};\n\nstruct reset_syscfg {\n\tstruct regmap *regmap;\n\tunsigned int offset_rst;\n\tunsigned int mask_rst;\n\tunsigned int offset_rst_msk;\n\tunsigned int mask_rst_msk;\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct resource_table {\n\tu32 ver;\n\tu32 num;\n\tu32 reserved[2];\n\tu32 offset[0];\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t\tlong: 32;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tlong: 32;\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tlong: 32;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct return_consumer {\n\t__u64 cookie;\n\t__u64 id;\n};\n\nstruct return_instance {\n\tstruct hprobe hprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tint cons_cnt;\n\tstruct return_instance *next;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tstruct return_consumer consumer;\n\tstruct return_consumer *extra_consumers;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct rfkill_ops;\n\nstruct rfkill {\n\tspinlock_t lock;\n\tenum rfkill_type type;\n\tlong unsigned int state;\n\tlong unsigned int hard_block_reasons;\n\tu32 idx;\n\tbool registered;\n\tbool persistent;\n\tbool polling_paused;\n\tbool suspended;\n\tbool need_sync;\n\tconst struct rfkill_ops *ops;\n\tvoid *data;\n\tstruct led_trigger led_trigger;\n\tconst char *ledtrigname;\n\tlong: 32;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct delayed_work poll_work;\n\tstruct work_struct uevent_work;\n\tstruct work_struct sync_work;\n\tchar name[0];\n\tlong: 32;\n};\n\nstruct rfkill_data {\n\tstruct list_head list;\n\tstruct list_head events;\n\tstruct mutex mtx;\n\twait_queue_head_t read_wait;\n\tbool input_handler;\n\tu8 max_size;\n};\n\nstruct rfkill_event_ext {\n\t__u32 idx;\n\t__u8 type;\n\t__u8 op;\n\t__u8 soft;\n\t__u8 hard;\n\t__u8 hard_block_reasons;\n} __attribute__((packed));\n\nstruct rfkill_gpio_data {\n\tconst char *name;\n\tenum rfkill_type type;\n\tstruct gpio_desc *reset_gpio;\n\tstruct gpio_desc *shutdown_gpio;\n\tstruct rfkill *rfkill_dev;\n\tstruct clk *clk;\n\tbool clk_enabled;\n};\n\nstruct rfkill_int_event {\n\tstruct list_head list;\n\tstruct rfkill_event_ext ev;\n};\n\nstruct rfkill_ops {\n\tvoid (*poll)(struct rfkill *, void *);\n\tvoid (*query)(struct rfkill *, void *);\n\tint (*set_block)(void *, bool);\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct stm32_rifsc_resources_names;\n\nstruct rifsc_dbg_private {\n\tconst struct stm32_rifsc_resources_names *res_names;\n\tvoid *mmio;\n\tunsigned int nb_risup;\n\tunsigned int nb_rimu;\n\tunsigned int nb_risal;\n};\n\nstruct rifsc_rimu_debug_data {\n\tchar m_name[11];\n\tu8 m_cid;\n\tbool cidsel;\n\tbool m_sec;\n\tbool m_priv;\n};\n\nstruct rifsc_risup_debug_data {\n\tchar dev_name[15];\n\tu8 dev_cid;\n\tu8 dev_sem_cids;\n\tu8 dev_id;\n\tbool dev_cid_filt_en;\n\tbool dev_sem_en;\n\tbool dev_priv;\n\tbool dev_sec;\n};\n\nstruct rifsc_subreg_debug_data {\n\tbool sr_sec;\n\tbool sr_priv;\n\tu8 sr_cid;\n\tbool sr_rlock;\n\tbool sr_enable;\n\tu16 sr_start;\n\tu16 sr_length;\n};\n\nstruct riic_of_data;\n\nstruct riic_dev {\n\tvoid *base;\n\tu8 *buf;\n\tstruct i2c_msg *msg;\n\tint bytes_left;\n\tint err;\n\tint is_last;\n\tconst struct riic_of_data *info;\n\tstruct completion msg_done;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tstruct clk *clk;\n\tstruct reset_control *rstc;\n\tstruct i2c_timings i2c_t;\n};\n\nstruct riic_irq_desc {\n\tint res_num;\n\tirq_handler_t isr;\n\tchar *name;\n};\n\nstruct riic_of_data {\n\tconst u8 *regs;\n\tconst struct riic_irq_desc *irqs;\n\tu8 num_irqs;\n\tbool fast_mode_plus;\n};\n\nstruct ring_buffer_cpu_meta {\n\tlong unsigned int first_buffer;\n\tlong unsigned int head_buffer;\n\tlong unsigned int commit_buffer;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tint buffers[0];\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tlong unsigned int cache_pages_removed;\n\tlong: 32;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tsize_t event_size;\n\tint missed_events;\n\tlong: 32;\n};\n\nstruct ring_buffer_meta {\n\tint magic;\n\tint struct_sizes;\n\tlong unsigned int total_size;\n\tlong unsigned int buffers_offset;\n};\n\nstruct trace_buffer_meta;\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tlong unsigned int cnt;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_lost;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\trb_time_t write_stamp;\n\trb_time_t before_stamp;\n\tu64 event_stamp[5];\n\tu64 read_stamp;\n\tlong unsigned int pages_removed;\n\tunsigned int mapped;\n\tunsigned int user_mapped;\n\tstruct mutex mapping_lock;\n\tlong unsigned int *subbuf_ids;\n\tstruct trace_buffer_meta *meta_page;\n\tstruct ring_buffer_cpu_meta *ring_meta;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct ring_info {\n\tstruct sk_buff *skb;\n\tu32 len;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rk3x_i2c_soc_data;\n\nstruct rk3x_i2c {\n\tstruct i2c_adapter adap;\n\tstruct device *dev;\n\tconst struct rk3x_i2c_soc_data *soc_data;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_rate_nb;\n\tint irq;\n\tstruct i2c_timings t;\n\tspinlock_t lock;\n\twait_queue_head_t wait;\n\tbool busy;\n\tstruct i2c_msg *msg;\n\tu8 addr;\n\tunsigned int mode;\n\tbool is_last_msg;\n\tenum rk3x_i2c_state state;\n\tunsigned int processed;\n\tint error;\n\tlong: 32;\n};\n\nstruct rk3x_i2c_calced_timings {\n\tlong unsigned int div_low;\n\tlong unsigned int div_high;\n\tunsigned int tuning;\n};\n\nstruct rk3x_i2c_soc_data {\n\tint grf_offset;\n\tint (*calc_timings)(long unsigned int, struct i2c_timings *, struct rk3x_i2c_calced_timings *);\n};\n\nstruct rk808 {\n\tstruct device *dev;\n\tstruct regmap_irq_chip_data *irq_data;\n\tstruct regmap *regmap;\n\tlong int variant;\n\tconst struct regmap_config *regmap_cfg;\n\tconst struct regmap_irq_chip *regmap_irq_chip;\n};\n\nstruct rk808_reg_data {\n\tint addr;\n\tint mask;\n\tint value;\n};\n\nstruct rk808_regulator_data {\n\tstruct gpio_desc *dvs_gpio[2];\n};\n\nstruct rk8xx_i2c_platform_data {\n\tconst struct regmap_config *regmap_cfg;\n\tint variant;\n};\n\nstruct rk8xx_register_bit {\n\tu8 reg;\n\tu8 bit;\n};\n\nstruct rk_timer {\n\tvoid *base;\n\tvoid *ctrl;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tu32 freq;\n\tint irq;\n};\n\nstruct rk_clkevt {\n\tstruct clock_event_device ce;\n\tstruct rk_timer timer;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rk_clock_fields {\n\tu16 io_clksel_cru_mask;\n\tu16 io_clksel_io_mask;\n\tu16 gmii_clk_sel_mask;\n\tu16 rmii_clk_sel_mask;\n\tu16 rmii_gate_en_mask;\n\tu16 rmii_mode_mask;\n\tu16 mac_speed_mask;\n};\n\nstruct rk_priv_data;\n\nstruct rk_gmac_ops {\n\tint (*init)(struct rk_priv_data *);\n\tvoid (*set_to_rgmii)(struct rk_priv_data *, int, int);\n\tvoid (*set_to_rmii)(struct rk_priv_data *);\n\tint (*set_speed)(struct rk_priv_data *, phy_interface_t, int);\n\tvoid (*integrated_phy_powerup)(struct rk_priv_data *);\n\tvoid (*integrated_phy_powerdown)(struct rk_priv_data *);\n\tu16 gmac_grf_reg;\n\tu16 gmac_phy_intf_sel_mask;\n\tu16 gmac_rmii_mode_mask;\n\tu16 clock_grf_reg;\n\tstruct rk_clock_fields clock;\n\tbool gmac_grf_reg_in_php;\n\tbool clock_grf_reg_in_php;\n\tbool supports_rgmii;\n\tbool supports_rmii;\n\tbool php_grf_required;\n\tbool regs_valid;\n\tu32 regs[0];\n};\n\nstruct rk_iommu {\n\tstruct device *dev;\n\tvoid **bases;\n\tint num_mmu;\n\tint num_irq;\n\tstruct clk_bulk_data *clocks;\n\tint num_clocks;\n\tbool reset_disabled;\n\tstruct iommu_device iommu;\n\tstruct list_head node;\n\tstruct iommu_domain *domain;\n};\n\nstruct rk_iommu_domain {\n\tstruct list_head iommus;\n\tu32 *dt;\n\tdma_addr_t dt_dma;\n\tspinlock_t iommus_lock;\n\tspinlock_t dt_lock;\n\tstruct device *dma_dev;\n\tstruct iommu_domain domain;\n};\n\nstruct rk_iommu_ops {\n\tphys_addr_t (*pt_address)(u32);\n\tu32 (*mk_dtentries)(dma_addr_t);\n\tu32 (*mk_ptentries)(phys_addr_t, int);\n\tlong: 32;\n\tu64 dma_bit_mask;\n\tgfp_t gfp_flags;\n\tlong: 32;\n};\n\nstruct rk_iommudata {\n\tstruct device_link *link;\n\tstruct rk_iommu *iommu;\n};\n\nstruct rk_priv_data {\n\tstruct device *dev;\n\tphy_interface_t phy_iface;\n\tint id;\n\tstruct regulator *regulator;\n\tconst struct rk_gmac_ops *ops;\n\tbool clk_enabled;\n\tbool clock_input;\n\tbool integrated_phy;\n\tbool supports_rgmii;\n\tbool supports_rmii;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct clk *clk_phy;\n\tstruct reset_control *phy_reset;\n\tint tx_delay;\n\tint rx_delay;\n\tstruct regmap *grf;\n\tstruct regmap *php_grf;\n\tu16 gmac_grf_reg;\n\tu16 gmac_phy_intf_sel_mask;\n\tu16 gmac_rmii_mode_mask;\n\tu16 clock_grf_reg;\n\tstruct rk_clock_fields clock;\n};\n\nstruct rk_rng_soc_data;\n\nstruct rk_rng {\n\tstruct hwrng rng;\n\tvoid *base;\n\tint clk_num;\n\tstruct clk_bulk_data *clk_bulks;\n\tconst struct rk_rng_soc_data *soc_data;\n\tstruct device *dev;\n};\n\nstruct rk_rng_soc_data {\n\tint (*rk_rng_init)(struct hwrng *);\n\tint (*rk_rng_read)(struct hwrng *, void *, size_t, bool);\n\tvoid (*rk_rng_cleanup)(struct hwrng *);\n\tshort unsigned int quality;\n\tbool reset_optional;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rmem_assigned_device {\n\tstruct device *dev;\n\tstruct reserved_mem *rmem;\n\tstruct list_head list;\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_gpio_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_gpio_data gpio_data;\n};\n\nstruct rmobile_pm_domain {\n\tstruct generic_pm_domain genpd;\n\tstruct dev_power_governor *gov;\n\tint (*suspend)(void);\n\tvoid *base;\n\tunsigned int bit_shift;\n};\n\nstruct rn5t618 {\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tlong int variant;\n\tint irq;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct rn5t618_wdt {\n\tstruct watchdog_device wdt_dev;\n\tstruct rn5t618 *rn5t618;\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct rockchip_aux_grf {\n\tstruct regmap *grf;\n\tenum rockchip_grf_type type;\n\tstruct hlist_node node;\n};\n\nstruct rockchip_clk_branch {\n\tunsigned int id;\n\tenum rockchip_clk_branch_type branch_type;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tint muxdiv_offset;\n\tu8 mux_shift;\n\tu8 mux_width;\n\tu8 mux_flags;\n\tu32 *mux_table;\n\tint div_offset;\n\tu8 div_shift;\n\tu8 div_width;\n\tu8 div_flags;\n\tstruct clk_div_table *div_table;\n\tint gate_offset;\n\tu8 gate_shift;\n\tu8 gate_flags;\n\tunsigned int linked_clk_id;\n\tenum rockchip_grf_type grf_type;\n\tstruct rockchip_clk_branch *child;\n};\n\nstruct rockchip_clk_frac {\n\tstruct notifier_block clk_nb;\n\tstruct clk_fractional_divider div;\n\tstruct clk_gate gate;\n\tstruct clk_mux mux;\n\tconst struct clk_ops *mux_ops;\n\tint mux_frac_idx;\n\tbool rate_change_remuxed;\n\tint rate_change_idx;\n};\n\nstruct rockchip_pll_rate_table;\n\nstruct rockchip_clk_provider;\n\nstruct rockchip_clk_pll {\n\tstruct clk_hw hw;\n\tstruct clk_mux pll_mux;\n\tconst struct clk_ops *pll_mux_ops;\n\tstruct notifier_block clk_nb;\n\tvoid *reg_base;\n\tint lock_offset;\n\tunsigned int lock_shift;\n\tenum rockchip_pll_type type;\n\tu8 flags;\n\tconst struct rockchip_pll_rate_table *rate_table;\n\tunsigned int rate_count;\n\tspinlock_t *lock;\n\tstruct rockchip_clk_provider *ctx;\n};\n\nstruct rockchip_clk_provider {\n\tvoid *reg_base;\n\tstruct clk_onecell_data clk_data;\n\tstruct device_node *cru_node;\n\tstruct regmap *grf;\n\tstruct hlist_head aux_grf_table[4];\n\tspinlock_t lock;\n};\n\nstruct rockchip_cpuclk_rate_table;\n\nstruct rockchip_cpuclk_reg_data;\n\nstruct rockchip_cpuclk {\n\tstruct clk_hw hw;\n\tstruct clk *alt_parent;\n\tvoid *reg_base;\n\tstruct notifier_block clk_nb;\n\tunsigned int rate_count;\n\tstruct rockchip_cpuclk_rate_table *rate_table;\n\tconst struct rockchip_cpuclk_reg_data *reg_data;\n\tspinlock_t *lock;\n};\n\nstruct rockchip_cpuclk_clksel {\n\tint reg;\n\tu32 val;\n};\n\nstruct rockchip_cpuclk_rate_table {\n\tlong unsigned int prate;\n\tstruct rockchip_cpuclk_clksel divs[6];\n\tstruct rockchip_cpuclk_clksel pre_muxs[6];\n\tstruct rockchip_cpuclk_clksel post_muxs[6];\n};\n\nstruct rockchip_cpuclk_reg_data {\n\tint core_reg[4];\n\tu8 div_core_shift[4];\n\tu32 div_core_mask[4];\n\tint num_cores;\n\tint mux_core_reg;\n\tu8 mux_core_alt;\n\tu8 mux_core_main;\n\tu8 mux_core_shift;\n\tu32 mux_core_mask;\n};\n\nstruct rockchip_ddrclk {\n\tstruct clk_hw hw;\n\tvoid *reg_base;\n\tint mux_offset;\n\tint mux_shift;\n\tint mux_width;\n\tint div_shift;\n\tint div_width;\n\tint ddr_flag;\n\tspinlock_t *lock;\n};\n\nstruct rockchip_domain_info {\n\tconst char *name;\n\tint pwr_mask;\n\tint status_mask;\n\tint req_mask;\n\tint idle_mask;\n\tint ack_mask;\n\tbool active_wakeup;\n\tbool need_regulator;\n\tint pwr_w_mask;\n\tint req_w_mask;\n\tint clk_ungate_mask;\n\tint mem_status_mask;\n\tint repair_status_mask;\n\tu32 pwr_offset;\n\tu32 mem_offset;\n\tu32 req_offset;\n};\n\nstruct rockchip_drv {\n\tenum rockchip_pin_drv_type drv_type;\n\tint offset;\n};\n\nstruct rockchip_gate_grf {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int reg;\n\tunsigned int shift;\n\tu8 flags;\n};\n\nstruct rockchip_gate_link_platdata {\n\tstruct rockchip_clk_provider *ctx;\n\tstruct rockchip_clk_branch *clkbr;\n};\n\nstruct rockchip_gpio_regs {\n\tu32 port_dr;\n\tu32 port_ddr;\n\tu32 int_en;\n\tu32 int_mask;\n\tu32 int_type;\n\tu32 int_polarity;\n\tu32 int_bothedge;\n\tu32 int_status;\n\tu32 int_rawstatus;\n\tu32 debounce;\n\tu32 dbclk_div_en;\n\tu32 dbclk_div_con;\n\tu32 port_eoi;\n\tu32 ext_port;\n\tu32 version_id;\n};\n\nstruct rockchip_grf_value;\n\nstruct rockchip_grf_info {\n\tconst struct rockchip_grf_value *values;\n\tint num_values;\n};\n\nstruct rockchip_grf_value {\n\tconst char *desc;\n\tu32 reg;\n\tu32 val;\n};\n\nstruct rockchip_inv_clock {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tint shift;\n\tint flags;\n\tspinlock_t *lock;\n};\n\nstruct rockchip_iodomain;\n\nstruct rockchip_iodomain_supply {\n\tstruct rockchip_iodomain *iod;\n\tstruct regulator *reg;\n\tstruct notifier_block nb;\n\tint idx;\n};\n\nstruct rockchip_iodomain_soc_data;\n\nstruct rockchip_iodomain {\n\tstruct device *dev;\n\tstruct regmap *grf;\n\tconst struct rockchip_iodomain_soc_data *soc_data;\n\tstruct rockchip_iodomain_supply supplies[16];\n\tint (*write)(struct rockchip_iodomain_supply *, int);\n};\n\nstruct rockchip_iodomain_soc_data {\n\tint grf_offset;\n\tconst char *supply_names[16];\n\tvoid (*init)(struct rockchip_iodomain *);\n\tint (*write)(struct rockchip_iodomain_supply *, int);\n};\n\nstruct rockchip_iomux {\n\tint type;\n\tint offset;\n};\n\nstruct rockchip_mmc_clock {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tstruct regmap *grf;\n\tint grf_reg;\n\tint shift;\n\tint cached_phase;\n\tstruct notifier_block clk_rate_change_nb;\n};\n\nstruct rockchip_mux_recalced_data {\n\tu8 num;\n\tu8 pin;\n\tu32 reg;\n\tu8 bit;\n\tu8 mask;\n};\n\nstruct rockchip_mux_route_data {\n\tu8 bank_num;\n\tu8 pin;\n\tu8 func;\n\tenum rockchip_mux_route_location route_location;\n\tu32 route_offset;\n\tu32 route_val;\n};\n\nstruct rockchip_muxgrf_clock {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 reg;\n\tu32 shift;\n\tu32 width;\n\tint flags;\n};\n\nstruct rockchip_pinctrl;\n\nstruct rockchip_pin_bank {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tstruct regmap *regmap_pull;\n\tstruct clk *clk;\n\tstruct clk *db_clk;\n\tint irq;\n\tu32 saved_masks;\n\tu32 pin_base;\n\tu8 nr_pins;\n\tchar *name;\n\tu8 bank_num;\n\tstruct rockchip_iomux iomux[4];\n\tstruct rockchip_drv drv[4];\n\tenum rockchip_pin_pull_type pull_type[4];\n\tbool valid;\n\tstruct device_node *of_node;\n\tstruct rockchip_pinctrl *drvdata;\n\tstruct irq_domain *domain;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range grange;\n\traw_spinlock_t slock;\n\tconst struct rockchip_gpio_regs *gpio_regs;\n\tu32 gpio_type;\n\tu32 toggle_edge_mode;\n\tu32 recalced_mask;\n\tu32 route_mask;\n\tstruct list_head deferred_pins;\n\tstruct mutex deferred_lock;\n};\n\nstruct rockchip_pin_config {\n\tunsigned int func;\n\tlong unsigned int *configs;\n\tunsigned int nconfigs;\n};\n\nstruct rockchip_pin_ctrl {\n\tstruct rockchip_pin_bank *pin_banks;\n\tu32 nr_banks;\n\tu32 nr_pins;\n\tchar *label;\n\tenum rockchip_pinctrl_type type;\n\tint grf_mux_offset;\n\tint pmu_mux_offset;\n\tint grf_drv_offset;\n\tint pmu_drv_offset;\n\tstruct rockchip_mux_recalced_data *iomux_recalced;\n\tu32 niomux_recalced;\n\tstruct rockchip_mux_route_data *iomux_routes;\n\tu32 niomux_routes;\n\tint (*pull_calc_reg)(struct rockchip_pin_bank *, int, struct regmap **, int *, u8 *);\n\tint (*drv_calc_reg)(struct rockchip_pin_bank *, int, struct regmap **, int *, u8 *);\n\tint (*schmitt_calc_reg)(struct rockchip_pin_bank *, int, struct regmap **, int *, u8 *);\n};\n\nstruct rockchip_pin_deferred {\n\tstruct list_head head;\n\tunsigned int pin;\n\tenum pin_config_param param;\n\tu32 arg;\n};\n\nstruct rockchip_pin_group {\n\tconst char *name;\n\tunsigned int npins;\n\tunsigned int *pins;\n\tstruct rockchip_pin_config *data;\n};\n\nstruct rockchip_pmx_func;\n\nstruct rockchip_pinctrl {\n\tstruct regmap *regmap_base;\n\tint reg_size;\n\tstruct regmap *regmap_pull;\n\tstruct regmap *regmap_pmu;\n\tstruct regmap *regmap_ioc1;\n\tstruct device *dev;\n\tstruct rockchip_pin_ctrl *ctrl;\n\tstruct pinctrl_desc pctl;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct rockchip_pin_group *groups;\n\tunsigned int ngroups;\n\tstruct rockchip_pmx_func *functions;\n\tunsigned int nfunctions;\n};\n\nstruct rockchip_pll_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tint con_offset;\n\tint mode_offset;\n\tint mode_shift;\n\tint lock_shift;\n\tenum rockchip_pll_type type;\n\tu8 pll_flags;\n\tstruct rockchip_pll_rate_table *rate_table;\n};\n\nstruct rockchip_pll_rate_table {\n\tlong unsigned int rate;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int nr;\n\t\t\tunsigned int nf;\n\t\t\tunsigned int no;\n\t\t\tunsigned int nb;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int fbdiv;\n\t\t\tunsigned int postdiv1;\n\t\t\tunsigned int refdiv;\n\t\t\tunsigned int postdiv2;\n\t\t\tunsigned int dsmpd;\n\t\t\tunsigned int frac;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int m;\n\t\t\tunsigned int p;\n\t\t\tunsigned int s;\n\t\t\tunsigned int k;\n\t\t};\n\t};\n};\n\nstruct rockchip_pm_data {\n\tconst struct platform_suspend_ops *ops;\n\tint (*init)(struct device_node *);\n};\n\nstruct rockchip_pmu;\n\nstruct rockchip_pm_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct rockchip_domain_info *info;\n\tstruct rockchip_pmu *pmu;\n\tint num_qos;\n\tstruct regmap **qos_regmap;\n\tu32 *qos_save_regs[5];\n\tint num_clks;\n\tstruct clk_bulk_data *clks;\n\tstruct device_node *node;\n\tstruct regulator *supply;\n\tlong: 32;\n};\n\nstruct rockchip_pmu_info;\n\nstruct rockchip_pmu {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tconst struct rockchip_pmu_info *info;\n\tstruct mutex mutex;\n\tstruct genpd_onecell_data genpd_data;\n\tstruct generic_pm_domain *domains[0];\n};\n\nstruct rockchip_pmu_info {\n\tu32 pwr_offset;\n\tu32 status_offset;\n\tu32 req_offset;\n\tu32 idle_offset;\n\tu32 ack_offset;\n\tu32 mem_pwr_offset;\n\tu32 chain_status_offset;\n\tu32 mem_status_offset;\n\tu32 repair_status_offset;\n\tu32 clk_ungate_offset;\n\tu32 core_pwrcnt_offset;\n\tu32 gpu_pwrcnt_offset;\n\tunsigned int core_power_transition_time;\n\tunsigned int gpu_power_transition_time;\n\tint num_domains;\n\tconst struct rockchip_domain_info *domain_info;\n};\n\nstruct rockchip_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tu8 ngroups;\n};\n\nstruct rockchip_softrst {\n\tstruct reset_controller_dev rcdev;\n\tconst int *lut;\n\tvoid *reg_base;\n\tint num_regs;\n\tint num_per_reg;\n\tu8 flags;\n\tspinlock_t lock;\n};\n\nstruct rockchip_tsadc_chip;\n\nstruct rockchip_thermal_sensor;\n\nstruct rockchip_thermal_data {\n\tconst struct rockchip_tsadc_chip *chip;\n\tstruct platform_device *pdev;\n\tstruct reset_control *reset;\n\tstruct rockchip_thermal_sensor *sensors;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct regmap *grf;\n\tvoid *regs;\n\tint trim_base;\n\tint trim_base_frac;\n\tint trim;\n\tint tshut_temp;\n\tint trim_temp;\n\tenum tshut_mode tshut_mode;\n\tenum tshut_polarity tshut_polarity;\n};\n\nstruct rockchip_thermal_sensor {\n\tstruct rockchip_thermal_data *thermal;\n\tstruct thermal_zone_device *tzd;\n\tstruct device_node *of_node;\n\tint id;\n\tint trim_temp;\n};\n\nstruct rockchip_tsadc_chip {\n\tint chn_offset;\n\tint chn_num;\n\tint trim_slope;\n\tint tshut_temp;\n\tenum tshut_mode tshut_mode;\n\tenum tshut_polarity tshut_polarity;\n\tbool grf_required;\n\tvoid (*initialize)(struct regmap *, void *, enum tshut_polarity);\n\tvoid (*irq_ack)(void *);\n\tvoid (*control)(void *, bool);\n\tint (*get_temp)(const struct chip_tsadc_table *, int, void *, int *);\n\tint (*set_alarm_temp)(const struct chip_tsadc_table *, int, void *, int);\n\tint (*set_tshut_temp)(const struct chip_tsadc_table *, int, void *, int);\n\tvoid (*set_tshut_mode)(int, void *, enum tshut_mode);\n\tint (*get_trim_code)(const struct chip_tsadc_table *, int, int, int);\n\tstruct chip_tsadc_table table;\n};\n\nstruct rockchip_usb_phy_base;\n\nstruct rockchip_usb_phy {\n\tstruct rockchip_usb_phy_base *base;\n\tstruct device_node *np;\n\tunsigned int reg_offset;\n\tstruct clk *clk;\n\tstruct clk *clk480m;\n\tstruct clk_hw clk480m_hw;\n\tstruct phy *phy;\n\tbool uart_enabled;\n\tstruct reset_control *reset;\n\tstruct regulator *vbus;\n};\n\nstruct rockchip_usb_phy_pdata;\n\nstruct rockchip_usb_phy_base {\n\tstruct device *dev;\n\tstruct regmap *reg_base;\n\tconst struct rockchip_usb_phy_pdata *pdata;\n};\n\nstruct rockchip_usb_phys;\n\nstruct rockchip_usb_phy_pdata {\n\tstruct rockchip_usb_phys *phys;\n\tint (*init_usb_uart)(struct regmap *, const struct rockchip_usb_phy_pdata *);\n\tint usb_uart_phy;\n};\n\nstruct rockchip_usb_phys {\n\tint reg;\n\tconst char *pll_name;\n};\n\nstruct romfs_super_block {\n\t__be32 word0;\n\t__be32 word1;\n\t__be32 size;\n\t__be32 checksum;\n\tchar name[0];\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tlong: 32;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tlong: 32;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct rpc_add_xprt_test {\n\tvoid (*add_xprt_test)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tvoid *data;\n};\n\nstruct rpc_auth_create_args {\n\trpc_authflavor_t pseudoflavor;\n\tconst char *target_name;\n};\n\nstruct rpc_authops {\n\tstruct module *owner;\n\trpc_authflavor_t au_flavor;\n\tchar *au_name;\n\tstruct rpc_auth * (*create)(const struct rpc_auth_create_args *, struct rpc_clnt *);\n\tvoid (*destroy)(struct rpc_auth *);\n\tint (*hash_cred)(struct auth_cred *, unsigned int);\n\tstruct rpc_cred * (*lookup_cred)(struct rpc_auth *, struct auth_cred *, int);\n\tstruct rpc_cred * (*crcreate)(struct rpc_auth *, struct auth_cred *, int, gfp_t);\n\trpc_authflavor_t (*info2flavor)(struct rpcsec_gss_info *);\n\tint (*flavor2info)(rpc_authflavor_t, struct rpcsec_gss_info *);\n\tint (*key_timeout)(struct rpc_auth *, struct rpc_cred *);\n\tint (*ping)(struct rpc_clnt *);\n};\n\nstruct rpc_bind_conn_calldata {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct rpc_buffer {\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct rpc_call_ops {\n\tvoid (*rpc_call_prepare)(struct rpc_task *, void *);\n\tvoid (*rpc_call_done)(struct rpc_task *, void *);\n\tvoid (*rpc_count_stats)(struct rpc_task *, void *);\n\tvoid (*rpc_release)(void *);\n};\n\nstruct rpc_xprt_switch;\n\nstruct rpc_cb_add_xprt_calldata {\n\tstruct rpc_xprt_switch *xps;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_pipe_dir_head {\n\tstruct list_head pdh_entries;\n\tstruct dentry *pdh_dentry;\n};\n\nstruct rpc_rtt {\n\tlong unsigned int timeo;\n\tlong unsigned int srtt[5];\n\tlong unsigned int sdrtt[5];\n\tint ntimeouts[5];\n};\n\nstruct rpc_timeout {\n\tlong unsigned int to_initval;\n\tlong unsigned int to_maxval;\n\tlong unsigned int to_increment;\n\tunsigned int to_retries;\n\tunsigned char to_exponential;\n};\n\nstruct rpc_xprt_iter_ops;\n\nstruct rpc_xprt_iter {\n\tstruct rpc_xprt_switch *xpi_xpswitch;\n\tstruct rpc_xprt *xpi_cursor;\n\tconst struct rpc_xprt_iter_ops *xpi_ops;\n};\n\nstruct rpc_iostats;\n\nstruct rpc_sysfs_client;\n\nstruct rpc_clnt {\n\trefcount_t cl_count;\n\tunsigned int cl_clid;\n\tstruct list_head cl_clients;\n\tstruct list_head cl_tasks;\n\tatomic_t cl_pid;\n\tspinlock_t cl_lock;\n\tstruct rpc_xprt *cl_xprt;\n\tconst struct rpc_procinfo *cl_procinfo;\n\tu32 cl_prog;\n\tu32 cl_vers;\n\tu32 cl_maxproc;\n\tstruct rpc_auth *cl_auth;\n\tstruct rpc_stat *cl_stats;\n\tstruct rpc_iostats *cl_metrics;\n\tunsigned int cl_softrtry: 1;\n\tunsigned int cl_softerr: 1;\n\tunsigned int cl_discrtry: 1;\n\tunsigned int cl_noretranstimeo: 1;\n\tunsigned int cl_autobind: 1;\n\tunsigned int cl_chatty: 1;\n\tunsigned int cl_shutdown: 1;\n\tunsigned int cl_netunreach_fatal: 1;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct rpc_rtt *cl_rtt;\n\tconst struct rpc_timeout *cl_timeout;\n\tatomic_t cl_swapper;\n\tint cl_nodelen;\n\tchar cl_nodename[65];\n\tstruct rpc_pipe_dir_head cl_pipedir_objects;\n\tstruct rpc_clnt *cl_parent;\n\tstruct rpc_rtt cl_rtt_default;\n\tstruct rpc_timeout cl_timeout_default;\n\tconst struct rpc_program *cl_program;\n\tconst char *cl_principal;\n\tstruct rpc_sysfs_client *cl_sysfs;\n\tunion {\n\t\tstruct rpc_xprt_iter cl_xpi;\n\t\tstruct work_struct cl_work;\n\t};\n\tconst struct cred *cl_cred;\n\tunsigned int cl_max_connect;\n\tstruct super_block *pipefs_sb;\n\tatomic_t cl_task_count;\n};\n\nstruct svc_xprt;\n\nstruct rpc_create_args {\n\tstruct net *net;\n\tint protocol;\n\tstruct sockaddr *address;\n\tsize_t addrsize;\n\tstruct sockaddr *saddress;\n\tconst struct rpc_timeout *timeout;\n\tconst char *servername;\n\tconst char *nodename;\n\tconst struct rpc_program *program;\n\tstruct rpc_stat *stats;\n\tu32 prognumber;\n\tu32 version;\n\trpc_authflavor_t authflavor;\n\tu32 nconnect;\n\tlong unsigned int flags;\n\tchar *client_name;\n\tstruct svc_xprt *bc_xprt;\n\tconst struct cred *cred;\n\tunsigned int max_connect;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct rpc_cred_cache {\n\tstruct hlist_head *hashtable;\n\tunsigned int hashbits;\n\tspinlock_t lock;\n};\n\nstruct rpc_credops {\n\tconst char *cr_name;\n\tint (*cr_init)(struct rpc_auth *, struct rpc_cred *);\n\tvoid (*crdestroy)(struct rpc_cred *);\n\tint (*crmatch)(struct auth_cred *, struct rpc_cred *, int);\n\tint (*crmarshal)(struct rpc_task *, struct xdr_stream *);\n\tint (*crrefresh)(struct rpc_task *);\n\tint (*crvalidate)(struct rpc_task *, struct xdr_stream *);\n\tint (*crwrap_req)(struct rpc_task *, struct xdr_stream *);\n\tint (*crunwrap_resp)(struct rpc_task *, struct xdr_stream *);\n\tint (*crkey_timeout)(struct rpc_cred *);\n\tchar * (*crstringify_acceptor)(struct rpc_cred *);\n\tbool (*crneed_reencode)(struct rpc_task *);\n};\n\nstruct rpc_filelist {\n\tconst char *name;\n\tconst struct file_operations *i_fop;\n\tumode_t mode;\n};\n\nstruct rpc_inode {\n\tstruct inode vfs_inode;\n\tvoid *private;\n\tstruct rpc_pipe *pipe;\n\twait_queue_head_t waitq;\n\tlong: 32;\n};\n\nstruct rpc_iostats {\n\tspinlock_t om_lock;\n\tlong unsigned int om_ops;\n\tlong unsigned int om_ntrans;\n\tlong unsigned int om_timeouts;\n\tlong long unsigned int om_bytes_sent;\n\tlong long unsigned int om_bytes_recv;\n\tktime_t om_queue;\n\tktime_t om_rtt;\n\tktime_t om_execute;\n\tlong unsigned int om_error_status;\n\tlong: 32;\n};\n\nstruct rpc_pipe {\n\tstruct list_head pipe;\n\tstruct list_head in_upcall;\n\tstruct list_head in_downcall;\n\tint pipelen;\n\tint nreaders;\n\tint nwriters;\n\tint flags;\n\tstruct delayed_work queue_timeout;\n\tconst struct rpc_pipe_ops *ops;\n\tspinlock_t lock;\n\tstruct dentry *dentry;\n};\n\nstruct rpc_pipe_dir_object_ops {\n\tint (*create)(struct dentry *, struct rpc_pipe_dir_object *);\n\tvoid (*destroy)(struct dentry *, struct rpc_pipe_dir_object *);\n};\n\nstruct rpc_pipe_ops {\n\tssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char *, size_t);\n\tssize_t (*downcall)(struct file *, const char *, size_t);\n\tvoid (*release_pipe)(struct inode *);\n\tint (*open_pipe)(struct inode *);\n\tvoid (*destroy_msg)(struct rpc_pipe_msg *);\n};\n\ntypedef void (*kxdreproc_t)(struct rpc_rqst *, struct xdr_stream *, const void *);\n\ntypedef int (*kxdrdproc_t)(struct rpc_rqst *, struct xdr_stream *, void *);\n\nstruct rpc_procinfo {\n\tu32 p_proc;\n\tkxdreproc_t p_encode;\n\tkxdrdproc_t p_decode;\n\tunsigned int p_arglen;\n\tunsigned int p_replen;\n\tunsigned int p_timer;\n\tu32 p_statidx;\n\tconst char *p_name;\n};\n\nstruct rpc_program {\n\tconst char *name;\n\tu32 number;\n\tunsigned int nrvers;\n\tconst struct rpc_version **version;\n\tstruct rpc_stat *stats;\n\tconst char *pipe_dir_name;\n};\n\nstruct xdr_buf {\n\tstruct kvec head[1];\n\tstruct kvec tail[1];\n\tstruct bio_vec *bvec;\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int flags;\n\tunsigned int buflen;\n\tunsigned int len;\n};\n\nstruct rpc_rqst {\n\tstruct rpc_xprt *rq_xprt;\n\tstruct xdr_buf rq_snd_buf;\n\tstruct xdr_buf rq_rcv_buf;\n\tstruct rpc_task *rq_task;\n\tstruct rpc_cred *rq_cred;\n\t__be32 rq_xid;\n\tint rq_cong;\n\tu32 rq_seqnos[3];\n\tunsigned int rq_seqno_count;\n\tint rq_enc_pages_num;\n\tstruct page **rq_enc_pages;\n\tvoid (*rq_release_snd_buf)(struct rpc_rqst *);\n\tunion {\n\t\tstruct list_head rq_list;\n\t\tstruct rb_node rq_recv;\n\t};\n\tstruct list_head rq_xmit;\n\tstruct list_head rq_xmit2;\n\tvoid *rq_buffer;\n\tsize_t rq_callsize;\n\tvoid *rq_rbuffer;\n\tsize_t rq_rcvsize;\n\tsize_t rq_xmit_bytes_sent;\n\tsize_t rq_reply_bytes_recvd;\n\tstruct xdr_buf rq_private_buf;\n\tlong unsigned int rq_majortimeo;\n\tlong unsigned int rq_minortimeo;\n\tlong unsigned int rq_timeout;\n\tlong: 32;\n\tktime_t rq_rtt;\n\tunsigned int rq_retries;\n\tunsigned int rq_connect_cookie;\n\tatomic_t rq_pin;\n\tu32 rq_bytes_sent;\n\tktime_t rq_xtime;\n\tint rq_ntrans;\n\tstruct lwq_node rq_bc_list;\n\tlong unsigned int rq_bc_pa_state;\n\tstruct list_head rq_bc_pa_list;\n\tlong: 32;\n};\n\nstruct rpc_sysfs_client {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_clnt *clnt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt {\n\tstruct kobject kobject;\n\tstruct rpc_xprt *xprt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt_switch {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_xprt_switch *xprt_switch;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_task_setup {\n\tstruct rpc_task *task;\n\tstruct rpc_clnt *rpc_client;\n\tstruct rpc_xprt *rpc_xprt;\n\tstruct rpc_cred *rpc_op_cred;\n\tconst struct rpc_message *rpc_message;\n\tconst struct rpc_call_ops *callback_ops;\n\tvoid *callback_data;\n\tstruct workqueue_struct *workqueue;\n\tshort unsigned int flags;\n\tsigned char priority;\n};\n\nstruct rpc_version {\n\tu32 number;\n\tunsigned int nrprocs;\n\tconst struct rpc_procinfo *procs;\n\tunsigned int *counts;\n};\n\nstruct rpc_xprt_ops;\n\nstruct xprt_class;\n\nstruct rpc_xprt {\n\tstruct kref kref;\n\tconst struct rpc_xprt_ops *ops;\n\tunsigned int id;\n\tconst struct rpc_timeout *timeout;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tint prot;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tsize_t max_payload;\n\tstruct rpc_wait_queue binding;\n\tstruct rpc_wait_queue sending;\n\tstruct rpc_wait_queue pending;\n\tstruct rpc_wait_queue backlog;\n\tstruct list_head free;\n\tunsigned int max_reqs;\n\tunsigned int min_reqs;\n\tunsigned int num_reqs;\n\tlong unsigned int state;\n\tunsigned char resvport: 1;\n\tunsigned char reuseport: 1;\n\tatomic_t swapper;\n\tunsigned int bind_index;\n\tstruct list_head xprt_switch;\n\tlong unsigned int bind_timeout;\n\tlong unsigned int reestablish_timeout;\n\tstruct xprtsec_parms xprtsec;\n\tunsigned int connect_cookie;\n\tstruct work_struct task_cleanup;\n\tstruct timer_list timer;\n\tlong unsigned int last_used;\n\tlong unsigned int idle_timeout;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int max_reconnect_timeout;\n\tatomic_long_t queuelen;\n\tspinlock_t transport_lock;\n\tspinlock_t reserve_lock;\n\tspinlock_t queue_lock;\n\tu32 xid;\n\tstruct rpc_task *snd_task;\n\tstruct list_head xmit_queue;\n\tatomic_long_t xmit_queuelen;\n\tstruct svc_xprt *bc_xprt;\n\tstruct svc_serv *bc_serv;\n\tunsigned int bc_alloc_max;\n\tunsigned int bc_alloc_count;\n\tatomic_t bc_slot_count;\n\tspinlock_t bc_pa_lock;\n\tstruct list_head bc_pa_list;\n\tstruct rb_root recv_queue;\n\tlong: 32;\n\tstruct {\n\t\tlong unsigned int bind_count;\n\t\tlong unsigned int connect_count;\n\t\tlong unsigned int connect_start;\n\t\tlong unsigned int connect_time;\n\t\tlong unsigned int sends;\n\t\tlong unsigned int recvs;\n\t\tlong unsigned int bad_xids;\n\t\tlong unsigned int max_slots;\n\t\tlong long unsigned int req_u;\n\t\tlong long unsigned int bklog_u;\n\t\tlong long unsigned int sending_u;\n\t\tlong long unsigned int pending_u;\n\t} stat;\n\tstruct net *xprt_net;\n\tnetns_tracker ns_tracker;\n\tconst char *servername;\n\tconst char *address_strings[6];\n\tstruct callback_head rcu;\n\tconst struct xprt_class *xprt_class;\n\tstruct rpc_sysfs_xprt *xprt_sysfs;\n\tbool main;\n\tlong: 32;\n};\n\nstruct rpc_xprt_iter_ops {\n\tvoid (*xpi_rewind)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_xprt)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_next)(struct rpc_xprt_iter *);\n};\n\nstruct rpc_xprt_ops {\n\tvoid (*set_buffer_size)(struct rpc_xprt *, size_t, size_t);\n\tint (*reserve_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*alloc_slot)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*free_slot)(struct rpc_xprt *, struct rpc_rqst *);\n\tvoid (*rpcbind)(struct rpc_task *);\n\tvoid (*set_port)(struct rpc_xprt *, short unsigned int);\n\tvoid (*connect)(struct rpc_xprt *, struct rpc_task *);\n\tint (*get_srcaddr)(struct rpc_xprt *, char *, size_t);\n\tshort unsigned int (*get_srcport)(struct rpc_xprt *);\n\tint (*buf_alloc)(struct rpc_task *);\n\tvoid (*buf_free)(struct rpc_task *);\n\tint (*prepare_request)(struct rpc_rqst *, struct xdr_buf *);\n\tint (*send_request)(struct rpc_rqst *);\n\tvoid (*abort_send_request)(struct rpc_rqst *);\n\tvoid (*wait_for_reply_request)(struct rpc_task *);\n\tvoid (*timer)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_request)(struct rpc_task *);\n\tvoid (*close)(struct rpc_xprt *);\n\tvoid (*destroy)(struct rpc_xprt *);\n\tvoid (*set_connect_timeout)(struct rpc_xprt *, long unsigned int, long unsigned int);\n\tvoid (*print_stats)(struct rpc_xprt *, struct seq_file *);\n\tint (*enable_swap)(struct rpc_xprt *);\n\tvoid (*disable_swap)(struct rpc_xprt *);\n\tvoid (*inject_disconnect)(struct rpc_xprt *);\n\tint (*bc_setup)(struct rpc_xprt *, unsigned int);\n\tsize_t (*bc_maxpayload)(struct rpc_xprt *);\n\tunsigned int (*bc_num_slots)(struct rpc_xprt *);\n\tvoid (*bc_free_rqst)(struct rpc_rqst *);\n\tvoid (*bc_destroy)(struct rpc_xprt *, unsigned int);\n};\n\nstruct rpc_xprt_switch {\n\tspinlock_t xps_lock;\n\tstruct kref xps_kref;\n\tunsigned int xps_id;\n\tunsigned int xps_nxprts;\n\tunsigned int xps_nactive;\n\tunsigned int xps_nunique_destaddr_xprts;\n\tatomic_long_t xps_queuelen;\n\tstruct list_head xps_xprt_list;\n\tstruct net *xps_net;\n\tconst struct rpc_xprt_iter_ops *xps_iter_ops;\n\tstruct rpc_sysfs_xprt_switch *xps_sysfs;\n\tstruct callback_head xps_rcu;\n};\n\nstruct rpcb_info {\n\tu32 rpc_vers;\n\tconst struct rpc_procinfo *rpc_proc;\n};\n\nstruct rpcbind_args {\n\tstruct rpc_xprt *r_xprt;\n\tu32 r_prog;\n\tu32 r_vers;\n\tu32 r_prot;\n\tshort unsigned int r_port;\n\tconst char *r_netid;\n\tconst char *r_addr;\n\tconst char *r_owner;\n\tint r_status;\n};\n\nstruct rpi_exp_gpio {\n\tstruct gpio_chip gc;\n\tstruct rpi_firmware *fw;\n};\n\nstruct rpi_firmware {\n\tstruct mbox_client cl;\n\tstruct mbox_chan *chan;\n\tstruct completion c;\n\tu32 enabled;\n\tstruct kref consumers;\n};\n\nstruct rpi_firmware_clk_rate_request {\n\t__le32 id;\n\t__le32 rate;\n};\n\nstruct rpi_firmware_get_clocks_response {\n\tu32 parent;\n\tu32 id;\n};\n\nstruct rpi_firmware_property_tag_header {\n\tu32 tag;\n\tu32 buf_size;\n\tu32 req_resp_size;\n};\n\nstruct rpi_power_domain {\n\tu32 domain;\n\tbool enabled;\n\tbool old_interface;\n\tstruct generic_pm_domain base;\n\tstruct rpi_firmware *fw;\n\tlong: 32;\n};\n\nstruct rpi_power_domain_packet {\n\tu32 domain;\n\tu32 state;\n};\n\nstruct rpi_power_domains {\n\tbool has_new_interface;\n\tstruct genpd_onecell_data xlate;\n\tstruct rpi_firmware *fw;\n\tlong: 32;\n\tstruct rpi_power_domain domains[23];\n};\n\nstruct rpi_reset {\n\tstruct reset_controller_dev rcdev;\n\tstruct rpi_firmware *fw;\n};\n\nstruct rpm_cc {\n\tstruct clk_rpm **clks;\n\tsize_t num_clks;\n\tu32 xo_buffer_value;\n\tstruct mutex xo_lock;\n};\n\nstruct rpm_clk_desc {\n\tstruct clk_rpm **clks;\n\tsize_t num_clks;\n};\n\nstruct rpm_clk_resource {\n\tu32 resource_type;\n\tu32 clock_id;\n\tbool branch;\n};\n\nstruct rpm_reg_parts {\n\tstruct request_member mV;\n\tstruct request_member uV;\n\tstruct request_member ip;\n\tstruct request_member pd;\n\tstruct request_member ia;\n\tstruct request_member fm;\n\tstruct request_member pm;\n\tstruct request_member pc;\n\tstruct request_member pf;\n\tstruct request_member enable_state;\n\tstruct request_member comp_mode;\n\tstruct request_member freq;\n\tstruct request_member freq_clk_src;\n\tstruct request_member hpm;\n\tint request_len;\n};\n\nstruct rpm_regulator_data {\n\tconst char *name;\n\tint resource;\n\tconst struct qcom_rpm_reg *template;\n\tconst char *supply;\n};\n\nstruct rpm_regulator_data___2 {\n\tconst char *name;\n\tu32 type;\n\tu32 id;\n\tconst struct regulator_desc *desc;\n\tconst char *supply;\n};\n\nstruct rpm_regulator_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct rpm_smd_clk_desc {\n\tstruct clk_smd_rpm **clks;\n\tsize_t num_clks;\n\tconst struct clk_smd_rpm ** const icc_clks;\n\tsize_t num_icc_clks;\n\tbool scaling_before_handover;\n};\n\nstruct rpmb_descr {\n\tenum rpmb_type type;\n\tint (*route_frames)(struct device *, u8 *, unsigned int, u8 *, unsigned int);\n\tu8 *dev_id;\n\tsize_t dev_id_len;\n\tu16 reliable_wr_count;\n\tu16 capacity;\n};\n\nstruct rpmb_dev {\n\tstruct device dev;\n\tint id;\n\tstruct list_head list_node;\n\tstruct rpmb_descr descr;\n};\n\nstruct rpmb_frame {\n\tu8 stuff[196];\n\tu8 key_mac[32];\n\tu8 data[256];\n\tu8 nonce[16];\n\t__be32 write_counter;\n\t__be16 addr;\n\t__be16 block_count;\n\t__be16 result;\n\t__be16 req_resp;\n};\n\nstruct rpmpd {\n\tstruct generic_pm_domain pd;\n\tstruct generic_pm_domain *parent;\n\tstruct rpmpd *peer;\n\tconst bool active_only;\n\tunsigned int corner;\n\tbool enabled;\n\tconst int res_type;\n\tconst int res_id;\n\tunsigned int max_state;\n\t__le32 key;\n\tbool state_synced;\n};\n\nstruct rpmpd_desc {\n\tstruct rpmpd **rpmpds;\n\tsize_t num_pds;\n\tunsigned int max_state;\n};\n\nstruct rpmpd_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct rpmsg_channel_info {\n\tchar name[32];\n\tu32 src;\n\tu32 dst;\n};\n\nstruct rpmsg_device_ops {\n\tstruct rpmsg_device * (*create_channel)(struct rpmsg_device *, struct rpmsg_channel_info *);\n\tint (*release_channel)(struct rpmsg_device *, struct rpmsg_channel_info *);\n\tstruct rpmsg_endpoint * (*create_ept)(struct rpmsg_device *, rpmsg_rx_cb_t, void *, struct rpmsg_channel_info);\n\tint (*announce_create)(struct rpmsg_device *);\n\tint (*announce_destroy)(struct rpmsg_device *);\n};\n\nstruct rpmsg_driver {\n\tstruct device_driver drv;\n\tconst struct rpmsg_device_id *id_table;\n\tint (*probe)(struct rpmsg_device *);\n\tvoid (*remove)(struct rpmsg_device *);\n\tint (*callback)(struct rpmsg_device *, void *, int, void *, u32);\n\tint (*flowcontrol)(struct rpmsg_device *, void *, bool);\n};\n\nstruct rpmsg_endpoint_ops {\n\tvoid (*destroy_ept)(struct rpmsg_endpoint *);\n\tint (*send)(struct rpmsg_endpoint *, void *, int);\n\tint (*sendto)(struct rpmsg_endpoint *, void *, int, u32);\n\tint (*trysend)(struct rpmsg_endpoint *, void *, int);\n\tint (*trysendto)(struct rpmsg_endpoint *, void *, int, u32);\n\t__poll_t (*poll)(struct rpmsg_endpoint *, struct file *, poll_table *);\n\tint (*set_flow_control)(struct rpmsg_endpoint *, bool, u32);\n\tssize_t (*get_mtu)(struct rpmsg_endpoint *);\n};\n\nstruct rproc_ops;\n\nstruct rproc {\n\tstruct list_head node;\n\tstruct iommu_domain *domain;\n\tconst char *name;\n\tconst char *firmware;\n\tvoid *priv;\n\tstruct rproc_ops *ops;\n\tlong: 32;\n\tstruct device dev;\n\tatomic_t power;\n\tunsigned int state;\n\tenum rproc_dump_mechanism dump_conf;\n\tstruct mutex lock;\n\tstruct dentry *dbg_dir;\n\tstruct list_head traces;\n\tint num_traces;\n\tstruct list_head carveouts;\n\tstruct list_head mappings;\n\tu64 bootaddr;\n\tstruct list_head rvdevs;\n\tstruct list_head subdevs;\n\tstruct idr notifyids;\n\tint index;\n\tstruct work_struct crash_handler;\n\tunsigned int crash_cnt;\n\tbool recovery_disabled;\n\tint max_notifyid;\n\tstruct resource_table *table_ptr;\n\tstruct resource_table *clean_table;\n\tstruct resource_table *cached_table;\n\tsize_t table_sz;\n\tbool has_iommu;\n\tbool auto_boot;\n\tbool sysfs_read_only;\n\tstruct list_head dump_segments;\n\tint nb_vdev;\n\tu8 elf_class;\n\tu16 elf_machine;\n\tstruct cdev cdev;\n\tbool cdev_put_on_release;\n\tlong unsigned int features[1];\n\tlong: 32;\n};\n\nstruct rproc_coredump_state {\n\tstruct rproc *rproc;\n\tvoid *header;\n\tstruct completion dump_done;\n};\n\nstruct rproc_mem_entry {\n\tvoid *va;\n\tbool is_iomem;\n\tdma_addr_t dma;\n\tsize_t len;\n\tu32 da;\n\tvoid *priv;\n\tchar name[32];\n\tstruct list_head node;\n\tu32 rsc_offset;\n\tu32 flags;\n\tu32 of_resm_idx;\n\tint (*alloc)(struct rproc *, struct rproc_mem_entry *);\n\tint (*release)(struct rproc *, struct rproc_mem_entry *);\n};\n\nstruct rproc_debug_trace {\n\tstruct rproc *rproc;\n\tstruct dentry *tfile;\n\tstruct list_head node;\n\tstruct rproc_mem_entry trace_mem;\n};\n\nstruct rproc_dump_segment {\n\tstruct list_head node;\n\tdma_addr_t da;\n\tsize_t size;\n\tvoid *priv;\n\tvoid (*dump)(struct rproc *, struct rproc_dump_segment *, void *, size_t, size_t);\n\tloff_t offset;\n};\n\nstruct rproc_ops {\n\tint (*prepare)(struct rproc *);\n\tint (*unprepare)(struct rproc *);\n\tint (*start)(struct rproc *);\n\tint (*stop)(struct rproc *);\n\tint (*attach)(struct rproc *);\n\tint (*detach)(struct rproc *);\n\tvoid (*kick)(struct rproc *, int);\n\tvoid * (*da_to_va)(struct rproc *, u64, size_t, bool *);\n\tint (*parse_fw)(struct rproc *, const struct firmware *);\n\tint (*handle_rsc)(struct rproc *, u32, void *, int, int);\n\tstruct resource_table * (*find_loaded_rsc_table)(struct rproc *, const struct firmware *);\n\tstruct resource_table * (*get_loaded_rsc_table)(struct rproc *, size_t *);\n\tint (*load)(struct rproc *, const struct firmware *);\n\tint (*sanity_check)(struct rproc *, const struct firmware *);\n\tu64 (*get_boot_addr)(struct rproc *, const struct firmware *);\n\tlong unsigned int (*panic)(struct rproc *);\n\tvoid (*coredump)(struct rproc *);\n};\n\nstruct rproc_subdev {\n\tstruct list_head node;\n\tint (*prepare)(struct rproc_subdev *);\n\tint (*start)(struct rproc_subdev *);\n\tvoid (*stop)(struct rproc_subdev *, bool);\n\tvoid (*unprepare)(struct rproc_subdev *);\n};\n\nstruct rproc_vdev;\n\nstruct rproc_vring {\n\tvoid *va;\n\tint num;\n\tu32 da;\n\tu32 align;\n\tint notifyid;\n\tstruct rproc_vdev *rvdev;\n\tstruct virtqueue *vq;\n};\n\nstruct rproc_vdev {\n\tstruct rproc_subdev subdev;\n\tstruct platform_device *pdev;\n\tunsigned int id;\n\tstruct list_head node;\n\tstruct rproc *rproc;\n\tstruct rproc_vring vring[2];\n\tu32 rsc_offset;\n\tu32 index;\n};\n\nstruct rproc_vdev_data {\n\tu32 rsc_offset;\n\tunsigned int id;\n\tu32 index;\n\tstruct fw_rsc_vdev *rsc;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[4];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tlong: 32;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tlong: 32;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n\tlong: 32;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tlong: 32;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n\tlong: 32;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tlong: 32;\n\tcall_single_data_t nohz_csd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tlong: 32;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 clock_pelt_idle_copy;\n\tu64 clock_idle_copy;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tstruct sched_avg avg_hw;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tktime_t hrtick_time;\n\tstruct cpuidle_state *idle_state;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tcpumask_var_t scratch_mask;\n\tcall_single_data_t cfsb_csd;\n\tstruct list_head cfsb_csd_list;\n\tatomic_t nr_iowait;\n\tlong: 32;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\nstruct rq_wait;\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n\tlong: 32;\n};\n\nstruct rs_codec {\n\tint mm;\n\tint nn;\n\tuint16_t *alpha_to;\n\tuint16_t *index_of;\n\tuint16_t *genpoly;\n\tint nroots;\n\tint fcr;\n\tint prim;\n\tint iprim;\n\tint gfpoly;\n\tint (*gffunc)(int);\n\tint users;\n\tstruct list_head list;\n};\n\nstruct rs_control {\n\tstruct rs_codec *codec;\n\tuint16_t buffers[0];\n};\n\nstruct rs_msg {\n\tstruct icmp6hdr icmph;\n\t__u8 opt[0];\n};\n\nstruct rsa_key {\n\tconst u8 *n;\n\tconst u8 *e;\n\tconst u8 *d;\n\tconst u8 *p;\n\tconst u8 *q;\n\tconst u8 *dp;\n\tconst u8 *dq;\n\tconst u8 *qinv;\n\tsize_t n_sz;\n\tsize_t e_sz;\n\tsize_t d_sz;\n\tsize_t p_sz;\n\tsize_t q_sz;\n\tsize_t dp_sz;\n\tsize_t dq_sz;\n\tsize_t qinv_sz;\n};\n\nstruct rsa_mpi_key {\n\tMPI n;\n\tMPI e;\n\tMPI d;\n\tMPI p;\n\tMPI q;\n\tMPI dp;\n\tMPI dq;\n\tMPI qinv;\n};\n\nstruct rsassa_pkcs1_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct rsassa_pkcs1_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n\tconst struct hash_prefix *hash_prefix;\n};\n\nstruct rsc {\n\tstruct cache_head h;\n\tstruct xdr_netobj handle;\n\tstruct svc_cred cred;\n\tstruct gss_svc_seq_data seqdata;\n\tstruct gss_ctx *mechctx;\n\tstruct callback_head callback_head;\n\tlong: 32;\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tlong: 32;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rsi {\n\tstruct cache_head h;\n\tstruct xdr_netobj in_handle;\n\tstruct xdr_netobj in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tint major_status;\n\tint minor_status;\n\tstruct callback_head callback_head;\n};\n\nstruct spi_ops;\n\nstruct rspi_data {\n\tvoid *addr;\n\tu32 speed_hz;\n\tstruct spi_controller *ctlr;\n\tstruct platform_device *pdev;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tstruct clk *clk;\n\tu16 spcmd;\n\tu8 spsr;\n\tu8 sppcr;\n\tint rx_irq;\n\tint tx_irq;\n\tconst struct spi_ops *ops;\n\tunsigned int dma_callbacked: 1;\n\tunsigned int byte_access: 1;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rst_config {\n\tunsigned int modemr;\n\tint (*configure)(void *);\n\tint (*set_rproc_boot_addr)(u64);\n};\n\nstruct rsvd_count {\n\tint ndelayed;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct rt0_hdr {\n\tstruct ipv6_rt_hdr rt_hdr;\n\t__u32 reserved;\n\tstruct in6_addr addr[0];\n};\n\nstruct rt6_exception {\n\tstruct hlist_node hlist;\n\tstruct rt6_info *rt6i;\n\tlong unsigned int stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct rt6_mtu_change_arg {\n\tstruct net_device *dev;\n\tunsigned int mtu;\n\tstruct fib6_info *f6i;\n};\n\nstruct rt6_nh {\n\tstruct fib6_info *fib6_info;\n\tstruct fib6_config r_cfg;\n\tstruct list_head list;\n};\n\nstruct rt6_rtnl_dump_arg {\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct net *net;\n\tstruct fib_dump_filter filter;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\t__kernel_size_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct sigcontext {\n\tlong unsigned int trap_no;\n\tlong unsigned int error_code;\n\tlong unsigned int oldmask;\n\tlong unsigned int arm_r0;\n\tlong unsigned int arm_r1;\n\tlong unsigned int arm_r2;\n\tlong unsigned int arm_r3;\n\tlong unsigned int arm_r4;\n\tlong unsigned int arm_r5;\n\tlong unsigned int arm_r6;\n\tlong unsigned int arm_r7;\n\tlong unsigned int arm_r8;\n\tlong unsigned int arm_r9;\n\tlong unsigned int arm_r10;\n\tlong unsigned int arm_fp;\n\tlong unsigned int arm_ip;\n\tlong unsigned int arm_sp;\n\tlong unsigned int arm_lr;\n\tlong unsigned int arm_pc;\n\tlong unsigned int arm_cpsr;\n\tlong unsigned int fault_address;\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tstruct sigcontext uc_mcontext;\n\tsigset_t uc_sigmask;\n\tint __unused[30];\n\tlong unsigned int uc_regspace[128];\n};\n\nstruct sigframe {\n\tstruct ucontext uc;\n\tlong unsigned int retcode[4];\n};\n\nstruct rt_sigframe {\n\tstruct siginfo info;\n\tstruct sigframe sig;\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n\tlong: 32;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\tlong: 32;\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n\tlong: 32;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtc_plat_data {\n\tstruct rtc_device *rtc;\n\tvoid *ioaddr;\n\tint irq;\n\tstruct clk *clk;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtcanmsg {\n\t__u8 can_family;\n\t__u8 gwtype;\n\t__u16 flags;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtl8169_counters {\n\t__le64 tx_packets;\n\t__le64 rx_packets;\n\t__le64 tx_errors;\n\t__le32 rx_errors;\n\t__le16 rx_missed;\n\t__le16 align_errors;\n\t__le32 tx_one_collision;\n\t__le32 tx_multi_collision;\n\t__le64 rx_unicast;\n\t__le64 rx_broadcast;\n\t__le32 rx_multicast;\n\t__le16 tx_aborted;\n\t__le16 tx_underrun;\n\t__le64 tx_octets;\n\t__le64 rx_octets;\n\t__le64 rx_multicast64;\n\t__le64 tx_unicast64;\n\t__le64 tx_broadcast64;\n\t__le64 tx_multicast64;\n\t__le32 tx_pause_on;\n\t__le32 tx_pause_off;\n\t__le32 tx_pause_all;\n\t__le32 tx_deferred;\n\t__le32 tx_late_collision;\n\t__le32 tx_all_collision;\n\t__le32 tx_aborted32;\n\t__le32 align_errors32;\n\t__le32 rx_frame_too_long;\n\t__le32 rx_runt;\n\t__le32 rx_pause_on;\n\t__le32 rx_pause_off;\n\t__le32 rx_pause_all;\n\t__le32 rx_unknown_opcode;\n\t__le32 rx_mac_error;\n\t__le32 tx_underrun32;\n\t__le32 rx_mac_missed;\n\t__le32 rx_tcam_dropped;\n\t__le32 tdu;\n\t__le32 rdu;\n};\n\nstruct rtl8169_tc_offsets {\n\tbool inited;\n\tlong: 32;\n\t__le64 tx_errors;\n\t__le32 tx_multi_collision;\n\t__le16 tx_aborted;\n\t__le16 rx_missed;\n};\n\nstruct r8169_led_classdev;\n\nstruct rtl_fw;\n\nstruct rtl8169_private {\n\tvoid *mmio_addr;\n\tstruct pci_dev *pci_dev;\n\tstruct net_device *dev;\n\tstruct phy_device *phydev;\n\tstruct napi_struct napi;\n\tenum mac_version mac_version;\n\tenum rtl_dash_type dash_type;\n\tu32 cur_rx;\n\tu32 cur_tx;\n\tu32 dirty_tx;\n\tstruct TxDesc *TxDescArray;\n\tstruct RxDesc *RxDescArray;\n\tdma_addr_t TxPhyAddr;\n\tdma_addr_t RxPhyAddr;\n\tstruct page *Rx_databuff[256];\n\tstruct ring_info tx_skb[256];\n\tu16 cp_cmd;\n\tu16 tx_lpi_timer;\n\tu32 irq_mask;\n\tint irq;\n\tstruct clk *clk;\n\tstruct {\n\t\tlong unsigned int flags[1];\n\t\tstruct work_struct work;\n\t} wk;\n\traw_spinlock_t mac_ocp_lock;\n\tstruct mutex led_lock;\n\tunsigned int supports_gmii: 1;\n\tunsigned int aspm_manageable: 1;\n\tunsigned int dash_enabled: 1;\n\tbool sfp_mode: 1;\n\tdma_addr_t counters_phys_addr;\n\tstruct rtl8169_counters *counters;\n\tlong: 32;\n\tstruct rtl8169_tc_offsets tc_offset;\n\tu32 saved_wolopts;\n\tconst char *fw_name;\n\tstruct rtl_fw *rtl_fw;\n\tstruct r8169_led_classdev *leds;\n\tu32 ocp_base;\n\tlong: 32;\n};\n\nstruct rtl821x_priv {\n\tbool enable_aldps;\n\tbool disable_clk_out;\n\tstruct clk *clk;\n\tu16 iner;\n};\n\nstruct rtl_chip_info {\n\tu32 mask;\n\tu32 val;\n\tenum mac_version mac_version;\n\tconst char *name;\n\tconst char *fw_name;\n};\n\nstruct rtl_coalesce_info {\n\tu32 speed;\n\tu32 scale_nsecs[4];\n};\n\nstruct rtl_cond {\n\tbool (*check)(struct rtl8169_private *);\n\tconst char *msg;\n};\n\ntypedef void (*rtl_fw_write_t)(struct rtl8169_private *, int, int);\n\ntypedef int (*rtl_fw_read_t)(struct rtl8169_private *, int);\n\nstruct rtl_fw_phy_action {\n\t__le32 *code;\n\tsize_t size;\n};\n\nstruct rtl_fw {\n\trtl_fw_write_t phy_write;\n\trtl_fw_read_t phy_read;\n\trtl_fw_write_t mac_mcu_write;\n\trtl_fw_read_t mac_mcu_read;\n\tconst struct firmware *fw;\n\tconst char *fw_name;\n\tstruct device *dev;\n\tchar version[32];\n\tstruct rtl_fw_phy_action phy_action;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n\tlong: 32;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rwrt_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u32 last_lba;\n\t__u32 block_size;\n\t__u16 blocking;\n\t__u8 page_present: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx_desc {\n\tu32 cmd_sts;\n\tu16 buf_size;\n\tu16 byte_cnt;\n\tu32 buf_ptr;\n\tu32 next_desc_ptr;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct rxbd8 {\n\tunion {\n\t\tstruct {\n\t\t\t__be16 status;\n\t\t\t__be16 length;\n\t\t};\n\t\t__be32 lstatus;\n\t};\n\t__be32 bufPtr;\n};\n\nstruct rxfcb {\n\t__be16 flags;\n\tu8 rq;\n\tu8 pro;\n\tu16 reserved;\n\t__be16 vlctl;\n};\n\nstruct rza1_irqc_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct irq_chip chip;\n\tstruct irq_domain *irq_domain;\n\tstruct of_phandle_args map[8];\n};\n\nstruct rza2_pinctrl_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct pinctrl_pin_desc *pins;\n\tstruct pinctrl_desc desc;\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_gpio_range gpio_range;\n\tint npins;\n\tstruct mutex mutex;\n};\n\nstruct rzn1_pin_group {\n\tconst char *name;\n\tconst char *func;\n\tunsigned int npins;\n\tunsigned int *pins;\n\tu8 *pin_ids;\n};\n\nstruct rzn1_pinctrl_regs;\n\nstruct rzn1_pmx_func;\n\nstruct rzn1_pinctrl {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct pinctrl_dev *pctl;\n\tstruct rzn1_pinctrl_regs *lev1;\n\tstruct rzn1_pinctrl_regs *lev2;\n\tu32 lev1_protect_phys;\n\tu32 lev2_protect_phys;\n\tint mdio_func[2];\n\tstruct rzn1_pin_group *groups;\n\tunsigned int ngroups;\n\tstruct rzn1_pmx_func *functions;\n\tunsigned int nfunctions;\n};\n\nstruct rzn1_pinctrl_regs {\n\tu32 conf[170];\n\tu32 pad0[86];\n\tu32 status_protect;\n\tu32 l2_mdio[2];\n};\n\nstruct rzn1_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int num_groups;\n};\n\nstruct s2mpg10_regulator_desc {\n\tstruct regulator_desc desc;\n\tunsigned int enable_ramp_rate;\n\tunsigned int pctrlsel_reg;\n\tunsigned int pctrlsel_mask;\n\tunsigned int pctrlsel_val;\n};\n\nstruct s2mps11_info {\n\tint ramp_delay2;\n\tint ramp_delay34;\n\tint ramp_delay5;\n\tint ramp_delay16;\n\tint ramp_delay7810;\n\tint ramp_delay9;\n\tenum sec_device_type dev_type;\n\tlong unsigned int suspend_state[2];\n};\n\nstruct s3_save {\n\tu32 command;\n\tu32 dev_nt;\n\tu64 dcbaa_ptr;\n\tu32 config_reg;\n\tlong: 32;\n};\n\nstruct s3c2410_platform_i2c {\n\tint bus_num;\n\tunsigned int flags;\n\tunsigned int slave_addr;\n\tlong unsigned int frequency;\n\tunsigned int sda_delay;\n\tvoid (*cfg_gpio)(struct platform_device *);\n};\n\nstruct s3c2410_uartcfg {\n\tunsigned char hwport;\n\tunsigned char unused;\n\tshort unsigned int flags;\n\tlong: 32;\n\tupf_t uart_flags;\n\tunsigned int clk_sel;\n\tunsigned int has_fracval;\n\tlong unsigned int ucon;\n\tlong unsigned int ulcon;\n\tlong unsigned int ufcon;\n\tlong: 32;\n};\n\nstruct s3c24xx_i2c {\n\twait_queue_head_t wait;\n\tkernel_ulong_t quirks;\n\tstruct i2c_msg *msg;\n\tunsigned int msg_num;\n\tunsigned int msg_idx;\n\tunsigned int msg_ptr;\n\tunsigned int tx_setup;\n\tunsigned int irq;\n\tenum s3c24xx_i2c_state state;\n\tlong unsigned int clkrate;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct device *dev;\n\tlong: 32;\n\tstruct i2c_adapter adap;\n\tstruct s3c2410_platform_i2c *pdata;\n\tstruct gpio_desc *gpios[2];\n\tstruct pinctrl *pctrl;\n\tstruct regmap *sysreg;\n\tunsigned int sys_i2c_cfg;\n};\n\nstruct s3c24xx_uart_info {\n\tconst char *name;\n\tenum s3c24xx_port_type type;\n\tunsigned int port_type;\n\tunsigned int fifosize;\n\tu32 rx_fifomask;\n\tu32 rx_fifoshift;\n\tu32 rx_fifofull;\n\tu32 tx_fifomask;\n\tu32 tx_fifoshift;\n\tu32 tx_fifofull;\n\tu32 clksel_mask;\n\tu32 clksel_shift;\n\tu32 ucon_mask;\n\tu8 def_clk_sel;\n\tu8 num_clks;\n\tu8 iotype;\n\tbool has_divslot;\n};\n\nstruct s3c24xx_serial_drv_data {\n\tconst struct s3c24xx_uart_info info;\n\tconst struct s3c2410_uartcfg def_cfg;\n\tconst unsigned int fifosize[4];\n};\n\nstruct s3c24xx_uart_dma {\n\tunsigned int rx_chan_id;\n\tunsigned int tx_chan_id;\n\tstruct dma_slave_config rx_conf;\n\tstruct dma_slave_config tx_conf;\n\tstruct dma_chan *rx_chan;\n\tstruct dma_chan *tx_chan;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tchar *rx_buf;\n\tdma_addr_t tx_transfer_addr;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tstruct dma_async_tx_descriptor *tx_desc;\n\tstruct dma_async_tx_descriptor *rx_desc;\n\tint tx_bytes_requested;\n\tint rx_bytes_requested;\n};\n\nstruct s3c24xx_uart_port {\n\tunsigned char rx_enabled;\n\tunsigned char tx_enabled;\n\tunsigned int pm_level;\n\tlong unsigned int baudclk_rate;\n\tunsigned int min_dma_size;\n\tunsigned int rx_irq;\n\tunsigned int tx_irq;\n\tunsigned int tx_in_progress;\n\tunsigned int tx_mode;\n\tunsigned int rx_mode;\n\tconst struct s3c24xx_uart_info *info;\n\tstruct clk *clk;\n\tstruct clk *baudclk;\n\tstruct uart_port port;\n\tconst struct s3c24xx_serial_drv_data *drv_data;\n\tconst struct s3c2410_uartcfg *cfg;\n\tstruct s3c24xx_uart_dma *dma;\n\tlong: 32;\n};\n\nstruct s3c_sdhci_platdata {\n\tunsigned int max_width;\n\tunsigned int host_caps;\n\tunsigned int host_caps2;\n\tunsigned int pm_caps;\n\tenum cd_types cd_type;\n\tint ext_cd_gpio;\n\tbool ext_cd_gpio_invert;\n\tint (*ext_cd_init)(void (*)(struct platform_device *, int));\n\tint (*ext_cd_cleanup)(void (*)(struct platform_device *, int));\n\tvoid (*cfg_gpio)(struct platform_device *, int);\n};\n\nstruct sec_pmic_dev;\n\nstruct sec_opmode_data;\n\nstruct s5m8767_info {\n\tstruct device *dev;\n\tstruct sec_pmic_dev *iodev;\n\tint num_regulators;\n\tstruct sec_opmode_data *opmode;\n\tint ramp_delay;\n\tbool buck2_ramp;\n\tbool buck3_ramp;\n\tbool buck4_ramp;\n\tbool buck2_gpiodvs;\n\tbool buck3_gpiodvs;\n\tbool buck4_gpiodvs;\n\tu8 buck2_vol[8];\n\tu8 buck3_vol[8];\n\tu8 buck4_vol[8];\n\tstruct gpio_desc *buck_gpios[3];\n\tstruct gpio_desc *buck_ds[3];\n\tint buck_gpioindex;\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct sam9x60_pll_core {\n\tstruct regmap *regmap;\n\tspinlock_t *lock;\n\tconst struct clk_pll_characteristics *characteristics;\n\tconst struct clk_pll_layout *layout;\n\tstruct clk_hw hw;\n\tu8 id;\n};\n\nstruct sam9x60_div {\n\tstruct sam9x60_pll_core core;\n\tstruct at91_clk_pms pms;\n\tu8 div;\n\tu8 safe_div;\n};\n\nstruct sam9x60_frac {\n\tstruct sam9x60_pll_core core;\n\tstruct at91_clk_pms pms;\n\tu32 frac;\n\tu16 mul;\n};\n\nstruct sama5d4_wdt {\n\tstruct watchdog_device wdd;\n\tvoid *reg_base;\n\tu32 mr;\n\tu32 ir;\n\tlong unsigned int last_ping;\n\tbool need_irq;\n\tbool sam9x60_support;\n};\n\nstruct sama7d65_pll {\n\tconst char *n;\n\tconst struct clk_pll_layout *l;\n\tconst struct clk_pll_characteristics *c;\n\tstruct clk_hw *hw;\n\tlong unsigned int f;\n\tenum sama7d65_pll_parent p;\n\tu8 t;\n\tu8 eid;\n\tu8 safe_div;\n};\n\nstruct sama7g5_pll {\n\tconst char *n;\n\tconst struct clk_pll_layout *l;\n\tconst struct clk_pll_characteristics *c;\n\tstruct clk_hw *hw;\n\tlong unsigned int f;\n\tenum sama7g5_pll_parent p;\n\tu8 t;\n\tu8 eid;\n\tu8 safe_div;\n};\n\nstruct samsung_pll_rate_table;\n\nstruct samsung_clk_pll {\n\tstruct clk_hw hw;\n\tvoid *lock_reg;\n\tvoid *con_reg;\n\tshort unsigned int enable_offs;\n\tshort unsigned int lock_offs;\n\tenum samsung_pll_type type;\n\tunsigned int rate_count;\n\tconst struct samsung_pll_rate_table *rate_table;\n};\n\nstruct samsung_clk_provider {\n\tvoid *reg_base;\n\tstruct device *dev;\n\tstruct regmap *sysreg;\n\tspinlock_t lock;\n\tbool auto_clock_gate;\n\tu32 gate_dbg_offset;\n\tu32 option_offset;\n\tu32 drcg_offset;\n\tu32 memclk_offset;\n\tstruct clk_hw_onecell_data clk_data;\n};\n\nstruct samsung_clk_reg_dump {\n\tu32 offset;\n\tu32 value;\n};\n\nstruct samsung_clock_alias {\n\tunsigned int id;\n\tconst char *dev_name;\n\tconst char *alias;\n};\n\nstruct samsung_clock_reg_cache {\n\tstruct list_head node;\n\tvoid *reg_base;\n\tstruct regmap *sysreg;\n\tstruct samsung_clk_reg_dump *rdump;\n\tunsigned int rd_num;\n\tconst struct samsung_clk_reg_dump *rsuspend;\n\tunsigned int rsuspend_num;\n};\n\nstruct samsung_pll_clock;\n\nstruct samsung_mux_clock;\n\nstruct samsung_fixed_rate_clock;\n\nstruct samsung_fixed_factor_clock;\n\nstruct samsung_cpu_clock;\n\nstruct samsung_cmu_info {\n\tconst struct samsung_pll_clock *pll_clks;\n\tunsigned int nr_pll_clks;\n\tconst struct samsung_mux_clock *mux_clks;\n\tunsigned int nr_mux_clks;\n\tconst struct samsung_div_clock *div_clks;\n\tunsigned int nr_div_clks;\n\tconst struct samsung_gate_clock *gate_clks;\n\tunsigned int nr_gate_clks;\n\tconst struct samsung_fixed_rate_clock *fixed_clks;\n\tunsigned int nr_fixed_clks;\n\tconst struct samsung_fixed_factor_clock *fixed_factor_clks;\n\tunsigned int nr_fixed_factor_clks;\n\tunsigned int nr_clk_ids;\n\tconst struct samsung_cpu_clock *cpu_clks;\n\tunsigned int nr_cpu_clks;\n\tconst long unsigned int *clk_regs;\n\tunsigned int nr_clk_regs;\n\tconst struct samsung_clk_reg_dump *suspend_regs;\n\tunsigned int nr_suspend_regs;\n\tconst char *clk_name;\n\tconst long unsigned int *sysreg_clk_regs;\n\tunsigned int nr_sysreg_clk_regs;\n\tbool manual_plls;\n\tbool auto_clock_gate;\n\tu32 gate_dbg_offset;\n\tu32 option_offset;\n\tu32 drcg_offset;\n\tu32 memclk_offset;\n};\n\nstruct samsung_cpu_clock {\n\tunsigned int id;\n\tconst char *name;\n\tunsigned int parent_id;\n\tunsigned int alt_parent_id;\n\tlong unsigned int flags;\n\tint offset;\n\tenum exynos_cpuclk_layout reg_layout;\n\tconst struct exynos_cpuclk_cfg_data *cfg;\n};\n\nstruct samsung_div_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tstruct clk_div_table *table;\n};\n\nstruct samsung_early_console_data {\n\tu32 txfull_mask;\n\tu32 rxfifo_mask;\n};\n\nstruct samsung_fixed_factor_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int mult;\n\tlong unsigned int div;\n\tlong unsigned int flags;\n};\n\nstruct samsung_fixed_rate_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int fixed_rate;\n};\n\nstruct samsung_gate_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 bit_idx;\n\tu8 gate_flags;\n};\n\nstruct samsung_mux_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 mux_flags;\n};\n\nstruct samsung_pin_bank_type;\n\nstruct samsung_pin_bank {\n\tconst struct samsung_pin_bank_type *type;\n\tvoid *pctl_base;\n\tu32 pctl_offset;\n\tu8 nr_pins;\n\tvoid *eint_base;\n\tu8 eint_func;\n\tenum eint_type eint_type;\n\tu32 eint_mask;\n\tu32 eint_offset;\n\tu32 eint_num;\n\tu32 eint_con_offset;\n\tu32 eint_mask_offset;\n\tu32 eint_pend_offset;\n\tu32 eint_fltcon_offset;\n\tconst char *name;\n\tu32 id;\n\tu32 pin_base;\n\tvoid *soc_priv;\n\tstruct fwnode_handle *fwnode;\n\tstruct samsung_pinctrl_drv_data *drvdata;\n\tstruct irq_domain *irq_domain;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range grange;\n\tstruct exynos_irq_chip *irq_chip;\n\traw_spinlock_t slock;\n\tu32 pm_save[7];\n};\n\nstruct samsung_pin_bank_data {\n\tconst struct samsung_pin_bank_type *type;\n\tu32 pctl_offset;\n\tu8 pctl_res_idx;\n\tu8 nr_pins;\n\tu8 eint_func;\n\tenum eint_type eint_type;\n\tu32 eint_mask;\n\tu32 eint_offset;\n\tu32 eint_num;\n\tu32 eint_con_offset;\n\tu32 eint_mask_offset;\n\tu32 eint_pend_offset;\n\tu32 eint_fltcon_offset;\n\tconst char *name;\n};\n\nstruct samsung_pin_bank_type {\n\tu8 fld_width[6];\n\tu8 reg_offset[6];\n};\n\nstruct samsung_retention_data;\n\nstruct samsung_pin_ctrl {\n\tconst struct samsung_pin_bank_data *pin_banks;\n\tunsigned int nr_banks;\n\tunsigned int nr_ext_resources;\n\tconst struct samsung_retention_data *retention_data;\n\tint (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);\n\tint (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);\n\tvoid (*pud_value_init)(struct samsung_pinctrl_drv_data *);\n\tvoid (*suspend)(struct samsung_pin_bank *);\n\tvoid (*resume)(struct samsung_pin_bank *);\n};\n\nstruct samsung_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tu8 num_pins;\n\tu8 func;\n};\n\nstruct samsung_pmx_func;\n\nstruct samsung_retention_ctrl;\n\nstruct samsung_pinctrl_drv_data {\n\tstruct list_head node;\n\tvoid *virt_base;\n\tstruct device *dev;\n\tint irq;\n\tstruct clk *pclk;\n\tstruct pinctrl_desc pctl;\n\tstruct pinctrl_dev *pctl_dev;\n\tconst struct samsung_pin_group *pin_groups;\n\tunsigned int nr_groups;\n\tconst struct samsung_pmx_func *pmx_functions;\n\tunsigned int nr_functions;\n\tstruct samsung_pin_bank *pin_banks;\n\tunsigned int nr_banks;\n\tunsigned int nr_pins;\n\tunsigned int pud_val[3];\n\tstruct samsung_retention_ctrl *retention_ctrl;\n\tvoid (*suspend)(struct samsung_pin_bank *);\n\tvoid (*resume)(struct samsung_pin_bank *);\n};\n\nstruct samsung_pinctrl_of_match_data {\n\tconst struct samsung_pin_ctrl *ctrl;\n\tunsigned int num_ctrl;\n};\n\nstruct samsung_pll_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tint con_offset;\n\tint lock_offset;\n\tenum samsung_pll_type type;\n\tconst struct samsung_pll_rate_table *rate_table;\n};\n\nstruct samsung_pll_rate_table {\n\tunsigned int rate;\n\tunsigned int pdiv;\n\tunsigned int mdiv;\n\tunsigned int sdiv;\n\tunsigned int kdiv;\n\tunsigned int afc;\n\tunsigned int mfr;\n\tunsigned int mrr;\n\tunsigned int vsel;\n};\n\nstruct samsung_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tu8 num_groups;\n\tu32 val;\n};\n\nstruct samsung_pwm_variant {\n\tu8 bits;\n\tu8 div_base;\n\tu8 tclk_mask;\n\tu8 output_mask;\n\tbool has_tint_cstat;\n};\n\nstruct samsung_pwm_clocksource {\n\tvoid *base;\n\tconst void *source_reg;\n\tunsigned int irq[5];\n\tstruct samsung_pwm_variant variant;\n\tstruct clk *timerclk;\n\tunsigned int event_id;\n\tunsigned int source_id;\n\tunsigned int tcnt_max;\n\tunsigned int tscaler_div;\n\tunsigned int tdiv;\n\tlong unsigned int clock_count_per_tick;\n};\n\nstruct samsung_retention_ctrl {\n\tconst u32 *regs;\n\tint nr_regs;\n\tu32 value;\n\tatomic_t *refcnt;\n\tvoid *priv;\n\tvoid (*enable)(struct samsung_pinctrl_drv_data *);\n\tvoid (*disable)(struct samsung_pinctrl_drv_data *);\n};\n\nstruct samsung_retention_data {\n\tconst u32 *regs;\n\tint nr_regs;\n\tu32 value;\n\tatomic_t *refcnt;\n\tstruct samsung_retention_ctrl * (*init)(struct samsung_pinctrl_drv_data *, const struct samsung_retention_data *);\n};\n\nstruct sata_pad_calibration {\n\tu8 gen1_tx_amp;\n\tu8 gen1_tx_peak;\n\tu8 gen2_tx_amp;\n\tu8 gen2_tx_peak;\n};\n\nstruct sata_rcar_priv {\n\tvoid *base;\n\tu32 sataint_mask;\n\tenum sata_rcar_type type;\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar saved_cmdlines[0];\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sbs_info {\n\tstruct i2c_client *client;\n\tstruct power_supply *power_supply;\n\tbool is_present;\n\tstruct gpio_desc *gpio_detect;\n\tbool charger_broadcasts;\n\tint last_state;\n\tint poll_time;\n\tu32 i2c_retry_count;\n\tu32 poll_retry_count;\n\tstruct delayed_work work;\n\tstruct mutex mode_lock;\n\tu32 flags;\n\tint technology;\n\tchar strings[99];\n};\n\nstruct sbs_platform_data {\n\tu32 i2c_retry_count;\n\tu32 poll_retry_count;\n};\n\nstruct scale_freq_data {\n\tenum scale_freq_source source;\n\tvoid (*set_freq_scale)(void);\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct scan_data {\n\tint min_space;\n\tint pick_free;\n\tint lnum;\n\tint exclude_index;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tlong: 32;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tlong: 32;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_avg avg;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tlong: 32;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_info {};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct sched_statistics {};\n\nstruct sci_clk_provider;\n\nstruct sci_clk {\n\tstruct clk_hw hw;\n\tu16 dev_id;\n\tu32 clk_id;\n\tu32 num_parents;\n\tstruct sci_clk_provider *provider;\n\tu8 flags;\n\tstruct list_head node;\n\tlong unsigned int cached_req;\n\tlong unsigned int cached_res;\n};\n\nstruct ti_sci_handle;\n\nstruct ti_sci_clk_ops;\n\nstruct sci_clk_provider {\n\tconst struct ti_sci_handle *sci;\n\tconst struct ti_sci_clk_ops *ops;\n\tstruct device *dev;\n\tstruct sci_clk **clocks;\n\tint num_clocks;\n};\n\nstruct sci_common_regs {\n\tunsigned int status;\n\tunsigned int control;\n};\n\nstruct sci_irq_desc {\n\tconst char *desc;\n\tirq_handler_t handler;\n};\n\nstruct sci_port_params;\n\nstruct sci_port_ops;\n\nstruct sci_of_data {\n\tconst struct sci_port_params *params;\n\tconst struct uart_ops *uart_ops;\n\tconst struct sci_port_ops *ops;\n\tshort unsigned int regtype;\n\tshort unsigned int type;\n};\n\nstruct sci_suspend_regs;\n\nstruct sci_port {\n\tstruct uart_port port;\n\tconst struct sci_port_params *params;\n\tconst struct plat_sci_port *cfg;\n\tunsigned int sampling_rate_mask;\n\tresource_size_t reg_size;\n\tstruct mctrl_gpios *gpios;\n\tstruct clk *clks[7];\n\tlong unsigned int clk_rates[7];\n\tint irqs[6];\n\tchar *irqstr[6];\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n\tstruct reset_control *rstc;\n\tstruct sci_suspend_regs *suspend_regs;\n\tstruct dma_chan *chan_tx_saved;\n\tstruct dma_chan *chan_rx_saved;\n\tdma_cookie_t cookie_tx;\n\tdma_cookie_t cookie_rx[2];\n\tdma_cookie_t active_rx;\n\tdma_addr_t tx_dma_addr;\n\tunsigned int tx_dma_len;\n\tstruct scatterlist sg_rx[2];\n\tvoid *rx_buf[2];\n\tsize_t buf_len_rx;\n\tstruct work_struct work_tx;\n\tstruct hrtimer rx_timer;\n\tunsigned int rx_timeout;\n\tunsigned int rx_frame;\n\tint rx_trigger;\n\tstruct timer_list rx_fifo_timer;\n\tint rx_fifo_timeout;\n\tu16 hscif_tot;\n\tu8 type;\n\tu8 regtype;\n\tconst struct sci_port_ops *ops;\n\tbool has_rtscts;\n\tbool autorts;\n\tbool tx_occurred;\n};\n\nstruct sci_port_ops {\n\tu32 (*read_reg)(struct uart_port *, int);\n\tvoid (*write_reg)(struct uart_port *, int, int);\n\tvoid (*clear_SCxSR)(struct uart_port *, unsigned int);\n\tvoid (*transmit_chars)(struct uart_port *);\n\tvoid (*receive_chars)(struct uart_port *);\n\tvoid (*poll_put_char)(struct uart_port *, unsigned char);\n\tint (*set_rtrg)(struct uart_port *, int);\n\tint (*rtrg_enabled)(struct uart_port *);\n\tvoid (*shutdown_complete)(struct uart_port *);\n\tvoid (*prepare_console_write)(struct uart_port *, u32);\n\tvoid (*finish_console_write)(struct uart_port *, u32);\n\tvoid (*console_save)(struct uart_port *);\n\tvoid (*console_restore)(struct uart_port *);\n\tsize_t (*suspend_regs_size)(void);\n};\n\nstruct sci_port_params_bits;\n\nstruct sci_port_params {\n\tconst struct plat_sci_reg regs[20];\n\tconst struct sci_common_regs *common_regs;\n\tconst struct sci_port_params_bits *param_bits;\n\tunsigned int fifosize;\n\tunsigned int overrun_reg;\n\tunsigned int overrun_mask;\n\tunsigned int sampling_rate_mask;\n\tunsigned int error_mask;\n\tunsigned int error_clear;\n};\n\nstruct sci_port_params_bits {\n\tunsigned int rxtx_enable;\n\tunsigned int te_clear;\n\tunsigned int poll_sent_bits;\n};\n\nstruct sci_suspend_regs {\n\tu16 scdl;\n\tu16 sccks;\n\tu16 scsmr;\n\tu16 scscr;\n\tu16 scfcr;\n\tu16 scsptr;\n\tu16 hssrr;\n\tu16 scpcr;\n\tu16 scpdr;\n\tu8 scbrr;\n\tu8 semr;\n};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_legacy_command {\n\t__le32 len;\n\t__le32 buf_offset;\n\t__le32 resp_hdr_offset;\n\t__le32 id;\n\t__le32 buf[0];\n};\n\nstruct scm_legacy_response {\n\t__le32 len;\n\t__le32 buf_offset;\n\t__le32 is_complete;\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scmi_sensor_info;\n\nstruct scmi_apriv {\n\tbool any_axes_support_extended_names;\n\tstruct scmi_sensor_info *s;\n};\n\nstruct scmi_msg_resp_attrs {\n\t__le32 min_range_low;\n\t__le32 min_range_high;\n\t__le32 max_range_low;\n\t__le32 max_range_high;\n};\n\nstruct scmi_axis_descriptor {\n\t__le32 id;\n\t__le32 attributes_low;\n\t__le32 attributes_high;\n\tu8 name[16];\n\t__le32 resolution;\n\tstruct scmi_msg_resp_attrs attrs;\n};\n\nstruct scmi_base_error_notify_payld {\n\t__le32 agent_id;\n\t__le32 error_status;\n\t__le64 msg_reports[1024];\n};\n\nstruct scmi_base_error_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tbool fatal;\n\tunsigned int cmd_count;\n\tlong: 32;\n\tlong long unsigned int reports[0];\n};\n\nstruct scmi_handle;\n\nstruct scmi_chan_info {\n\tint id;\n\tstruct device *dev;\n\tbool is_p2a;\n\tunsigned int rx_timeout_ms;\n\tunsigned int max_msg_size;\n\tstruct scmi_handle *handle;\n\tbool no_completion_irq;\n\tvoid *transport_info;\n};\n\nstruct scmi_clk {\n\tu32 id;\n\tstruct device *dev;\n\tstruct clk_hw hw;\n\tconst struct scmi_clock_info *info;\n\tconst struct scmi_protocol_handle *ph;\n\tstruct clk_parent_data *parent_data;\n};\n\nstruct scmi_clk_ipriv {\n\tstruct device *dev;\n\tu32 clk_id;\n\tstruct scmi_clock_info *clk;\n};\n\nstruct scmi_clk_proto_ops {\n\tint (*count_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_clock_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*rate_get)(const struct scmi_protocol_handle *, u32, u64 *);\n\tint (*rate_set)(const struct scmi_protocol_handle *, u32, u64);\n\tint (*enable)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*disable)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*state_get)(const struct scmi_protocol_handle *, u32, bool *, bool);\n\tint (*config_oem_get)(const struct scmi_protocol_handle *, u32, enum scmi_clock_oem_config, u32 *, u32 *, bool);\n\tint (*config_oem_set)(const struct scmi_protocol_handle *, u32, enum scmi_clock_oem_config, u32, bool);\n\tint (*parent_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*parent_set)(const struct scmi_protocol_handle *, u32, u32);\n};\n\nstruct scmi_clock_info {\n\tchar name[64];\n\tunsigned int enable_latency;\n\tbool rate_discrete;\n\tbool rate_changed_notifications;\n\tbool rate_change_requested_notifications;\n\tbool state_ctrl_forbidden;\n\tbool rate_ctrl_forbidden;\n\tbool parent_ctrl_forbidden;\n\tbool extended_config;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tint num_rates;\n\t\t\tlong: 32;\n\t\t\tu64 rates[16];\n\t\t} list;\n\t\tstruct {\n\t\t\tu64 min_rate;\n\t\t\tu64 max_rate;\n\t\t\tu64 step_size;\n\t\t} range;\n\t};\n\tint num_parents;\n\tu32 *parents;\n};\n\nstruct scmi_clock_rate_notif_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int clock_id;\n\tlong long unsigned int rate;\n};\n\nstruct scmi_clock_rate_notify_payld {\n\t__le32 agent_id;\n\t__le32 clock_id;\n\t__le32 rate_low;\n\t__le32 rate_high;\n};\n\nstruct scmi_clock_set_rate {\n\t__le32 flags;\n\t__le32 id;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_data {\n\tint domain_id;\n\tint nr_opp;\n\tstruct device *cpu_dev;\n\tcpumask_var_t opp_shared_cpus;\n\tstruct notifier_block limit_notify_nb;\n\tstruct freq_qos_request limits_freq_req;\n};\n\nstruct scmi_debug_info {\n\tstruct dentry *top_dentry;\n\tconst char *name;\n\tconst char *type;\n\tbool is_atomic;\n\tatomic_t counters[15];\n};\n\nstruct scmi_transport_ops;\n\nstruct scmi_desc {\n\tconst struct scmi_transport_ops *ops;\n\tint max_rx_timeout_ms;\n\tint max_msg;\n\tint max_msg_size;\n\tunsigned int atomic_threshold;\n\tconst bool force_polling;\n\tconst bool sync_cmds_completed_on_ret;\n\tconst bool atomic_enabled;\n};\n\nstruct scmi_device {\n\tu32 id;\n\tu8 protocol_id;\n\tconst char *name;\n\tlong: 32;\n\tstruct device dev;\n\tstruct scmi_handle *handle;\n\tlong: 32;\n};\n\nstruct scmi_device_id {\n\tu8 protocol_id;\n\tconst char *name;\n};\n\nstruct scmi_driver {\n\tconst char *name;\n\tint (*probe)(struct scmi_device *);\n\tvoid (*remove)(struct scmi_device *);\n\tconst struct scmi_device_id *id_table;\n\tstruct device_driver driver;\n};\n\nstruct scmi_event {\n\tu8 id;\n\tsize_t max_payld_sz;\n\tsize_t max_report_sz;\n};\n\nstruct scmi_registered_event;\n\nstruct scmi_event_handler {\n\tu32 key;\n\trefcount_t users;\n\tstruct scmi_registered_event *r_evt;\n\tstruct blocking_notifier_head chain;\n\tstruct hlist_node hash;\n\tbool enabled;\n};\n\nstruct scmi_event_header {\n\tktime_t timestamp;\n\tsize_t payld_sz;\n\tunsigned char evt_id;\n\tunsigned char payld[0];\n};\n\nstruct scmi_event_ops {\n\tbool (*is_notify_supported)(const struct scmi_protocol_handle *, u8, u32);\n\tint (*get_num_sources)(const struct scmi_protocol_handle *);\n\tint (*set_notify_enabled)(const struct scmi_protocol_handle *, u8, u32, bool);\n\tvoid * (*fill_custom_report)(const struct scmi_protocol_handle *, u8, ktime_t, const void *, size_t, void *, u32 *);\n};\n\nstruct scmi_fc_db_info {\n\tint width;\n\tlong: 32;\n\tu64 set;\n\tu64 mask;\n\tvoid *addr;\n\tlong: 32;\n};\n\nstruct scmi_fc_info {\n\tvoid *set_addr;\n\tvoid *get_addr;\n\tstruct scmi_fc_db_info *set_db;\n\tu32 rate_limit;\n};\n\nstruct scmi_function_info {\n\tchar name[64];\n\tbool present;\n\tu32 *groups;\n\tu32 nr_groups;\n};\n\nstruct scmi_group_info {\n\tchar name[64];\n\tbool present;\n\tu32 *group_pins;\n\tu32 nr_pins;\n};\n\nstruct scmi_revision_info;\n\nstruct scmi_notify_ops;\n\nstruct scmi_handle {\n\tstruct device *dev;\n\tstruct scmi_revision_info *version;\n\tint (*devm_protocol_acquire)(struct scmi_device *, u8);\n\tconst void * (*devm_protocol_get)(struct scmi_device *, u8, struct scmi_protocol_handle **);\n\tvoid (*devm_protocol_put)(struct scmi_device *, u8);\n\tbool (*is_transport_atomic)(const struct scmi_handle *, unsigned int *);\n\tconst struct scmi_notify_ops *notify_ops;\n};\n\nstruct scmi_imx_bbm_proto_ops;\n\nstruct scmi_imx_bbm {\n\tstruct scmi_protocol_handle *ph;\n\tconst struct scmi_imx_bbm_proto_ops *ops;\n\tstruct notifier_block nb;\n\tint keycode;\n\tint keystate;\n\tbool suspended;\n\tstruct delayed_work check_work;\n\tstruct input_dev *input;\n};\n\nstruct scmi_imx_bbm___2 {\n\tconst struct scmi_imx_bbm_proto_ops *ops;\n\tstruct rtc_device *rtc_dev;\n\tstruct scmi_protocol_handle *ph;\n\tstruct notifier_block nb;\n};\n\nstruct scmi_imx_bbm_alarm_time {\n\t__le32 id;\n\t__le32 flags;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_imx_bbm_get_time {\n\t__le32 id;\n\t__le32 flags;\n};\n\nstruct scmi_imx_bbm_info {\n\tint nr_rtc;\n\tint nr_gpr;\n};\n\nstruct scmi_imx_bbm_notif_report {\n\tbool is_rtc;\n\tbool is_button;\n\tlong: 32;\n\tktime_t timestamp;\n\tunsigned int rtc_id;\n\tunsigned int rtc_evt;\n};\n\nstruct scmi_imx_bbm_notify_payld {\n\t__le32 flags;\n};\n\nstruct scmi_imx_bbm_proto_ops {\n\tint (*rtc_time_set)(const struct scmi_protocol_handle *, u32, uint64_t);\n\tint (*rtc_time_get)(const struct scmi_protocol_handle *, u32, u64 *);\n\tint (*rtc_alarm_set)(const struct scmi_protocol_handle *, u32, bool, u64);\n\tint (*button_get)(const struct scmi_protocol_handle *, u32 *);\n};\n\nstruct scmi_imx_bbm_set_time {\n\t__le32 id;\n\t__le32 flags;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_imx_cpu_info {\n\tu32 nr_cpu;\n};\n\nstruct scmi_imx_cpu_info_get_out {\n\t__le32 runmode;\n\t__le32 sleepmode;\n\t__le32 resetvectorlow;\n\t__le32 resetvectorhigh;\n};\n\nstruct scmi_imx_cpu_proto_ops {\n\tint (*cpu_reset_vector_set)(const struct scmi_protocol_handle *, u32, u64, bool, bool, bool);\n\tint (*cpu_start)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*cpu_started)(const struct scmi_protocol_handle *, u32, bool *);\n};\n\nstruct scmi_imx_cpu_reset_vector_set_in {\n\t__le32 cpuid;\n\t__le32 flags;\n\t__le32 resetvectorlow;\n\t__le32 resetvectorhigh;\n};\n\nstruct scmi_imx_lmm_info {\n\tu32 lmid;\n\tenum scmi_imx_lmm_state state;\n\tu32 errstatus;\n\tu8 name[16];\n};\n\nstruct scmi_imx_lmm_priv {\n\tu32 nr_lmm;\n};\n\nstruct scmi_imx_lmm_proto_ops {\n\tint (*lmm_power_boot)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*lmm_info)(const struct scmi_protocol_handle *, u32, struct scmi_imx_lmm_info *);\n\tint (*lmm_reset_vector_set)(const struct scmi_protocol_handle *, u32, u32, u32, u64);\n\tint (*lmm_shutdown)(const struct scmi_protocol_handle *, u32, u32);\n};\n\nstruct scmi_imx_lmm_reset_vector_set_in {\n\t__le32 lmid;\n\t__le32 cpuid;\n\t__le32 flags;\n\t__le32 resetvectorlow;\n\t__le32 resetvectorhigh;\n};\n\nstruct scmi_imx_lmm_shutdown_in {\n\t__le32 lmid;\n\t__le32 flags;\n};\n\nstruct scmi_imx_misc_board_info_out {\n\t__le32 attributes;\n\tu8 brdname[16];\n};\n\nstruct scmi_imx_misc_buildinfo_out {\n\t__le32 buildnum;\n\t__le32 buildcommit;\n\tu8 builddate[16];\n\tu8 buildtime[16];\n};\n\nstruct scmi_imx_misc_cfg_info_out {\n\t__le32 msel;\n\tu8 cfgname[16];\n};\n\nstruct scmi_imx_misc_ctrl_get_out {\n\t__le32 num;\n\t__le32 val[0];\n};\n\nstruct scmi_imx_misc_ctrl_notify_in {\n\t__le32 ctrl_id;\n\t__le32 flags;\n};\n\nstruct scmi_imx_misc_ctrl_notify_payld {\n\t__le32 ctrl_id;\n\t__le32 flags;\n};\n\nstruct scmi_imx_misc_ctrl_notify_report {\n\tktime_t timestamp;\n\tunsigned int ctrl_id;\n\tunsigned int flags;\n};\n\nstruct scmi_imx_misc_ctrl_set_in {\n\t__le32 id;\n\t__le32 num;\n\t__le32 value[0];\n};\n\nstruct scmi_imx_misc_info {\n\tu32 nr_dev_ctrl;\n\tu32 nr_brd_ctrl;\n\tu32 nr_reason;\n};\n\nstruct scmi_imx_misc_proto_ops {\n\tint (*misc_ctrl_set)(const struct scmi_protocol_handle *, u32, u32, u32 *);\n\tint (*misc_ctrl_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n\tint (*misc_ctrl_req_notify)(const struct scmi_protocol_handle *, u32, u32, u32);\n\tint (*misc_syslog)(const struct scmi_protocol_handle *, u16 *, void *);\n};\n\nstruct scmi_imx_misc_syslog_in {\n\t__le32 flags;\n\t__le32 index;\n};\n\nstruct scmi_imx_misc_syslog_ipriv {\n\tu32 *array;\n\tu16 *size;\n};\n\nstruct scmi_imx_misc_syslog_out {\n\t__le32 numlogflags;\n\t__le32 syslog[0];\n};\n\nstruct scmi_revision_info {\n\tu16 major_ver;\n\tu16 minor_ver;\n\tu8 num_protocols;\n\tu8 num_agents;\n\tu32 impl_ver;\n\tchar vendor_id[16];\n\tchar sub_vendor_id[16];\n};\n\nstruct scmi_xfers_info {\n\tlong unsigned int *xfer_alloc_table;\n\tspinlock_t xfer_lock;\n\tint max_msg;\n\tstruct hlist_head free_xfers;\n\tstruct hlist_head pending_xfers[512];\n};\n\nstruct scmi_info {\n\tint id;\n\tstruct device *dev;\n\tconst struct scmi_desc *desc;\n\tstruct scmi_revision_info version;\n\tstruct scmi_handle handle;\n\tstruct scmi_xfers_info tx_minfo;\n\tstruct scmi_xfers_info rx_minfo;\n\tstruct idr tx_idr;\n\tstruct idr rx_idr;\n\tstruct idr protocols;\n\tstruct mutex protocols_mtx;\n\tu8 *protocols_imp;\n\tstruct idr active_protocols;\n\tvoid *notify_priv;\n\tstruct list_head node;\n\tint users;\n\tstruct notifier_block bus_nb;\n\tstruct notifier_block dev_req_nb;\n\tstruct mutex devreq_mtx;\n\tstruct scmi_debug_info *dbg;\n\tvoid *raw;\n};\n\nstruct scmi_iterator_state {\n\tunsigned int desc_index;\n\tunsigned int num_returned;\n\tunsigned int num_remaining;\n\tunsigned int max_resources;\n\tunsigned int loop_idx;\n\tsize_t rx_len;\n\tvoid *priv;\n};\n\nstruct scmi_xfer;\n\nstruct scmi_iterator_ops;\n\nstruct scmi_iterator {\n\tvoid *msg;\n\tvoid *resp;\n\tstruct scmi_xfer *t;\n\tconst struct scmi_protocol_handle *ph;\n\tstruct scmi_iterator_ops *ops;\n\tstruct scmi_iterator_state state;\n\tvoid *priv;\n};\n\nstruct scmi_iterator_ops {\n\tvoid (*prepare_message)(void *, unsigned int, const void *);\n\tint (*update_state)(struct scmi_iterator_state *, const void *, void *);\n\tint (*process_response)(const struct scmi_protocol_handle *, const void *, struct scmi_iterator_state *, void *);\n};\n\nstruct scmi_shared_mem;\n\nstruct scmi_shmem_io_ops;\n\nstruct scmi_mailbox {\n\tstruct mbox_client cl;\n\tstruct mbox_chan *chan;\n\tstruct mbox_chan *chan_receiver;\n\tstruct mbox_chan *chan_platform_receiver;\n\tstruct scmi_chan_info *cinfo;\n\tstruct scmi_shared_mem *shmem;\n\tstruct mutex chan_lock;\n\tstruct scmi_shmem_io_ops *io_ops;\n};\n\nstruct scmi_msg_payld;\n\nstruct scmi_message_operations {\n\tsize_t (*response_size)(struct scmi_xfer *);\n\tsize_t (*command_size)(struct scmi_xfer *);\n\tvoid (*tx_prepare)(struct scmi_msg_payld *, struct scmi_xfer *);\n\tu32 (*read_header)(struct scmi_msg_payld *);\n\tvoid (*fetch_response)(struct scmi_msg_payld *, size_t, struct scmi_xfer *);\n\tvoid (*fetch_notification)(struct scmi_msg_payld *, size_t, size_t, struct scmi_xfer *);\n};\n\nstruct scmi_msg {\n\tvoid *buf;\n\tsize_t len;\n};\n\nstruct scmi_msg_base_error_notify {\n\t__le32 event_control;\n};\n\nstruct scmi_msg_clock_config_get {\n\t__le32 id;\n\t__le32 flags;\n};\n\nstruct scmi_msg_clock_config_set {\n\t__le32 id;\n\t__le32 attributes;\n};\n\nstruct scmi_msg_clock_config_set_v2 {\n\t__le32 id;\n\t__le32 attributes;\n\t__le32 oem_config_val;\n};\n\nstruct scmi_msg_clock_describe_rates {\n\t__le32 id;\n\t__le32 rate_index;\n};\n\nstruct scmi_msg_clock_possible_parents {\n\t__le32 id;\n\t__le32 skip_parents;\n};\n\nstruct scmi_msg_clock_rate_notify {\n\t__le32 clk_id;\n\t__le32 notify_enable;\n};\n\nstruct scmi_msg_clock_set_parent {\n\t__le32 id;\n\t__le32 parent_id;\n};\n\nstruct scmi_msg_cmd_config_set {\n\t__le32 domain_id;\n\t__le32 config;\n};\n\nstruct scmi_msg_cmd_describe_levels {\n\t__le32 domain_id;\n\t__le32 level_index;\n};\n\nstruct scmi_msg_cmd_level_set {\n\t__le32 domain_id;\n\t__le32 flags;\n\t__le32 voltage_level;\n};\n\nstruct scmi_msg_get_fc_info {\n\t__le32 domain;\n\t__le32 message_id;\n};\n\nstruct scmi_msg_hdr {\n\tu8 id;\n\tu8 protocol_id;\n\tu8 type;\n\tu16 seq;\n\tu32 status;\n\tbool poll_completion;\n};\n\nstruct scmi_msg_imx_bbm_button_notify {\n\t__le32 flags;\n};\n\nstruct scmi_msg_imx_bbm_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_imx_bbm_rtc_notify {\n\t__le32 rtc_id;\n\t__le32 flags;\n};\n\nstruct scmi_msg_imx_cpu_attributes_out {\n\t__le32 attributes;\n\tu8 name[16];\n};\n\nstruct scmi_msg_imx_cpu_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_imx_lmm_attributes_out {\n\t__le32 lmid;\n\t__le32 attributes;\n\t__le32 state;\n\t__le32 errstatus;\n\tu8 name[16];\n};\n\nstruct scmi_msg_imx_lmm_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_imx_misc_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_payld {\n\t__le32 msg_header;\n\t__le32 msg_payload[0];\n};\n\nstruct scmi_msg_perf_describe_levels {\n\t__le32 domain;\n\t__le32 level_index;\n};\n\nstruct scmi_msg_pinctrl_attributes {\n\t__le32 identifier;\n\t__le32 flags;\n};\n\nstruct scmi_msg_pinctrl_list_assoc {\n\t__le32 identifier;\n\t__le32 flags;\n\t__le32 index;\n};\n\nstruct scmi_msg_pinctrl_protocol_attributes {\n\t__le32 attributes_low;\n\t__le32 attributes_high;\n};\n\nstruct scmi_msg_powercap_notify_cap {\n\t__le32 domain;\n\t__le32 notify_enable;\n};\n\nstruct scmi_msg_powercap_notify_thresh {\n\t__le32 domain;\n\t__le32 notify_enable;\n\t__le32 power_thresh_low;\n\t__le32 power_thresh_high;\n};\n\nstruct scmi_msg_powercap_set_cap_or_pai {\n\t__le32 domain;\n\t__le32 flags;\n\t__le32 value;\n};\n\nstruct scmi_msg_request {\n\t__le32 identifier;\n\t__le32 flags;\n};\n\nstruct scmi_msg_reset_domain_reset {\n\t__le32 domain_id;\n\t__le32 flags;\n\t__le32 reset_state;\n};\n\nstruct scmi_msg_reset_notify {\n\t__le32 id;\n\t__le32 event_control;\n};\n\nstruct scmi_msg_resp_base_attributes {\n\tu8 num_protocols;\n\tu8 num_agents;\n\t__le16 reserved;\n};\n\nstruct scmi_msg_resp_base_discover_agent {\n\t__le32 agent_id;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_clock_attributes {\n\t__le32 attributes;\n\tu8 name[16];\n\t__le32 clock_enable_latency;\n};\n\nstruct scmi_msg_resp_clock_config_get {\n\t__le32 attributes;\n\t__le32 config;\n\t__le32 oem_config_val;\n};\n\nstruct scmi_msg_resp_clock_describe_rates {\n\t__le32 num_rates_flags;\n\tstruct {\n\t\t__le32 value_low;\n\t\t__le32 value_high;\n\t} rate[0];\n};\n\nstruct scmi_msg_resp_clock_possible_parents {\n\t__le32 num_parent_flags;\n\t__le32 possible_parents[0];\n};\n\nstruct scmi_msg_resp_clock_protocol_attributes {\n\t__le16 num_clocks;\n\tu8 max_async_req;\n\tu8 reserved;\n};\n\nstruct scmi_msg_resp_desc_fc {\n\t__le32 attr;\n\t__le32 rate_limit;\n\t__le32 chan_addr_low;\n\t__le32 chan_addr_high;\n\t__le32 chan_size;\n\t__le32 db_addr_low;\n\t__le32 db_addr_high;\n\t__le32 db_set_lmask;\n\t__le32 db_set_hmask;\n\t__le32 db_preserve_lmask;\n\t__le32 db_preserve_hmask;\n};\n\nstruct scmi_msg_resp_describe_levels {\n\t__le32 flags;\n\t__le32 voltage[0];\n};\n\nstruct scmi_msg_resp_domain_attributes {\n\t__le32 attr;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_domain_name_get {\n\t__le32 flags;\n\tu8 name[64];\n};\n\nstruct scmi_msg_resp_perf_attributes {\n\t__le16 num_domains;\n\t__le16 flags;\n\t__le32 stats_addr_low;\n\t__le32 stats_addr_high;\n\t__le32 stats_size;\n};\n\nstruct scmi_msg_resp_perf_describe_levels {\n\t__le16 num_returned;\n\t__le16 num_remaining;\n\tstruct {\n\t\t__le32 perf_val;\n\t\t__le32 power;\n\t\t__le16 transition_latency_us;\n\t\t__le16 reserved;\n\t} opp[0];\n};\n\nstruct scmi_msg_resp_perf_describe_levels_v4 {\n\t__le16 num_returned;\n\t__le16 num_remaining;\n\tstruct {\n\t\t__le32 perf_val;\n\t\t__le32 power;\n\t\t__le16 transition_latency_us;\n\t\t__le16 reserved;\n\t\t__le32 indicative_freq;\n\t\t__le32 level_index;\n\t} opp[0];\n};\n\nstruct scmi_msg_resp_perf_domain_attributes {\n\t__le32 flags;\n\t__le32 rate_limit_us;\n\t__le32 sustained_freq_khz;\n\t__le32 sustained_perf_level;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_power_attributes {\n\t__le16 num_domains;\n\t__le16 reserved;\n\t__le32 stats_addr_low;\n\t__le32 stats_addr_high;\n\t__le32 stats_size;\n};\n\nstruct scmi_msg_resp_power_domain_attributes {\n\t__le32 flags;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_powercap_cap_set_complete {\n\t__le32 domain;\n\t__le32 power_cap;\n};\n\nstruct scmi_msg_resp_powercap_domain_attributes {\n\t__le32 attributes;\n\tu8 name[16];\n\t__le32 min_pai;\n\t__le32 max_pai;\n\t__le32 pai_step;\n\t__le32 min_power_cap;\n\t__le32 max_power_cap;\n\t__le32 power_cap_step;\n\t__le32 sustainable_power;\n\t__le32 accuracy;\n\t__le32 parent_id;\n};\n\nstruct scmi_msg_resp_powercap_meas_get {\n\t__le32 power;\n\t__le32 pai;\n};\n\nstruct scmi_msg_resp_reset_domain_attributes {\n\t__le32 attributes;\n\t__le32 latency;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_sensor_attributes {\n\t__le16 num_sensors;\n\tu8 max_requests;\n\tu8 reserved;\n\t__le32 reg_addr_low;\n\t__le32 reg_addr_high;\n\t__le32 reg_size;\n};\n\nstruct scmi_msg_resp_sensor_axis_description {\n\t__le32 num_axis_flags;\n\tstruct scmi_axis_descriptor desc[0];\n};\n\nstruct scmi_sensor_axis_name_descriptor {\n\t__le32 axis_id;\n\tu8 name[64];\n};\n\nstruct scmi_msg_resp_sensor_axis_names_description {\n\t__le32 num_axis_flags;\n\tstruct scmi_sensor_axis_name_descriptor desc[0];\n};\n\nstruct scmi_sensor_descriptor {\n\t__le32 id;\n\t__le32 attributes_low;\n\t__le32 attributes_high;\n\tu8 name[16];\n\t__le32 power;\n\t__le32 resolution;\n\tstruct scmi_msg_resp_attrs scalar_attrs;\n};\n\nstruct scmi_msg_resp_sensor_description {\n\t__le16 num_returned;\n\t__le16 num_remaining;\n\tstruct scmi_sensor_descriptor desc[0];\n};\n\nstruct scmi_msg_resp_sensor_list_update_intervals {\n\t__le32 num_intervals_flags;\n\t__le32 intervals[0];\n};\n\nstruct scmi_msg_resp_set_rate_complete {\n\t__le32 id;\n\t__le32 rate_low;\n\t__le32 rate_high;\n};\n\nstruct scmi_msg_sensor_axis_description_get {\n\t__le32 id;\n\t__le32 axis_desc_index;\n};\n\nstruct scmi_msg_sensor_config_set {\n\t__le32 id;\n\t__le32 sensor_config;\n};\n\nstruct scmi_msg_sensor_description {\n\t__le32 desc_index;\n};\n\nstruct scmi_msg_sensor_list_update_intervals {\n\t__le32 id;\n\t__le32 index;\n};\n\nstruct scmi_msg_sensor_reading_get {\n\t__le32 id;\n\t__le32 flags;\n};\n\nstruct scmi_msg_sensor_request_notify {\n\t__le32 id;\n\t__le32 event_control;\n};\n\nstruct scmi_msg_set_sensor_trip_point {\n\t__le32 id;\n\t__le32 event_control;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_msg_settings_conf {\n\t__le32 identifier;\n\t__le32 function_id;\n\t__le32 attributes;\n\t__le32 configs[0];\n};\n\nstruct scmi_msg_settings_get {\n\t__le32 identifier;\n\t__le32 attributes;\n};\n\nstruct scmi_notifier_devres {\n\tconst struct scmi_handle *handle;\n\tu8 proto_id;\n\tu8 evt_id;\n\tu32 __src_id;\n\tu32 *src_id;\n\tstruct notifier_block *nb;\n};\n\nstruct scmi_registered_events_desc;\n\nstruct scmi_notify_instance {\n\tvoid *gid;\n\tstruct scmi_handle *handle;\n\tstruct work_struct init_work;\n\tstruct workqueue_struct *notify_wq;\n\tstruct mutex pending_mtx;\n\tstruct scmi_registered_events_desc **registered_protocols;\n\tstruct hlist_head pending_events_handlers[16];\n};\n\nstruct scmi_notify_ops {\n\tint (*devm_event_notifier_register)(struct scmi_device *, u8, u8, const u32 *, struct notifier_block *);\n\tint (*devm_event_notifier_unregister)(struct scmi_device *, struct notifier_block *);\n\tint (*event_notifier_register)(const struct scmi_handle *, u8, u8, const u32 *, struct notifier_block *);\n\tint (*event_notifier_unregister)(const struct scmi_handle *, u8, u8, const u32 *, struct notifier_block *);\n};\n\nstruct scmi_optee_agent {\n\tstruct device *dev;\n\tstruct tee_context *tee_ctx;\n\tu32 caps;\n\tstruct mutex mu;\n\tstruct list_head channel_list;\n};\n\nstruct scmi_optee_channel {\n\tu32 channel_id;\n\tu32 tee_session;\n\tu32 caps;\n\tu32 rx_len;\n\tstruct mutex mu;\n\tstruct scmi_chan_info *cinfo;\n\tunion {\n\t\tstruct scmi_shared_mem *shmem;\n\t\tstruct scmi_msg_payld *msg;\n\t} req;\n\tstruct scmi_shmem_io_ops *io_ops;\n\tstruct tee_shm *tee_shm;\n\tstruct list_head link;\n};\n\nstruct scmi_perf_proto_ops;\n\nstruct scmi_perf_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct scmi_perf_proto_ops *perf_ops;\n\tconst struct scmi_protocol_handle *ph;\n\tconst struct scmi_perf_domain_info *info;\n\tu32 domain_id;\n};\n\nstruct scmi_perf_get_limits {\n\t__le32 max_level;\n\t__le32 min_level;\n};\n\nstruct scmi_perf_info {\n\tu16 num_domains;\n\tenum scmi_power_scale power_scale;\n\tu64 stats_addr;\n\tu32 stats_size;\n\tbool notify_lvl_cmd;\n\tbool notify_lim_cmd;\n\tstruct perf_dom_info *dom_info;\n\tlong: 32;\n};\n\nstruct scmi_perf_level_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 performance_level;\n};\n\nstruct scmi_perf_level_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int performance_level;\n\tlong unsigned int performance_level_freq;\n};\n\nstruct scmi_perf_limits_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 range_max;\n\t__le32 range_min;\n};\n\nstruct scmi_perf_limits_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int range_max;\n\tunsigned int range_min;\n\tlong unsigned int range_max_freq;\n\tlong unsigned int range_min_freq;\n};\n\nstruct scmi_perf_notify_level_or_limits {\n\t__le32 domain;\n\t__le32 notify_enable;\n};\n\nstruct scmi_perf_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_perf_domain_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*limits_set)(const struct scmi_protocol_handle *, u32, u32, u32);\n\tint (*limits_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n\tint (*level_set)(const struct scmi_protocol_handle *, u32, u32, bool);\n\tint (*level_get)(const struct scmi_protocol_handle *, u32, u32 *, bool);\n\tint (*transition_latency_get)(const struct scmi_protocol_handle *, u32);\n\tint (*rate_limit_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*device_opps_add)(const struct scmi_protocol_handle *, struct device *, u32);\n\tint (*freq_set)(const struct scmi_protocol_handle *, u32, long unsigned int, bool);\n\tint (*freq_get)(const struct scmi_protocol_handle *, u32, long unsigned int *, bool);\n\tint (*est_power_get)(const struct scmi_protocol_handle *, u32, long unsigned int *, long unsigned int *);\n\tbool (*fast_switch_possible)(const struct scmi_protocol_handle *, u32);\n\tint (*fast_switch_rate_limit)(const struct scmi_protocol_handle *, u32, u32 *);\n\tenum scmi_power_scale (*power_scale_get)(const struct scmi_protocol_handle *);\n};\n\nstruct scmi_perf_set_level {\n\t__le32 domain;\n\t__le32 level;\n};\n\nstruct scmi_perf_set_limits {\n\t__le32 domain;\n\t__le32 max_level;\n\t__le32 min_level;\n};\n\nstruct scmi_pin_info {\n\tchar name[64];\n\tbool present;\n};\n\nstruct scmi_pinctrl_info {\n\tint nr_groups;\n\tint nr_functions;\n\tint nr_pins;\n\tstruct scmi_group_info *groups;\n\tstruct scmi_function_info *functions;\n\tstruct scmi_pin_info *pins;\n};\n\nstruct scmi_pinctrl_ipriv {\n\tu32 selector;\n\tenum scmi_pinctrl_selector_type type;\n\tu32 *array;\n};\n\nstruct scmi_pinctrl_proto_ops {\n\tint (*count_get)(const struct scmi_protocol_handle *, enum scmi_pinctrl_selector_type);\n\tint (*name_get)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, const char **);\n\tint (*group_pins_get)(const struct scmi_protocol_handle *, u32, const unsigned int **, unsigned int *);\n\tint (*function_groups_get)(const struct scmi_protocol_handle *, u32, unsigned int *, const unsigned int **);\n\tint (*mux_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*settings_get_one)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, enum scmi_pinctrl_conf_type, u32 *);\n\tint (*settings_get_all)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, unsigned int *, enum scmi_pinctrl_conf_type *, u32 *);\n\tint (*settings_conf)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, unsigned int, enum scmi_pinctrl_conf_type *, u32 *);\n\tint (*pin_request)(const struct scmi_protocol_handle *, u32);\n\tint (*pin_free)(const struct scmi_protocol_handle *, u32);\n};\n\nstruct scmi_pm_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct scmi_protocol_handle *ph;\n\tconst char *name;\n\tu32 domain;\n\tlong: 32;\n};\n\nstruct scmi_power_info {\n\tbool notify_state_change_cmd;\n\tint num_domains;\n\tu64 stats_addr;\n\tu32 stats_size;\n\tstruct power_dom_info *dom_info;\n};\n\nstruct scmi_power_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst char * (*name_get)(const struct scmi_protocol_handle *, u32);\n\tint (*state_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*state_get)(const struct scmi_protocol_handle *, u32, u32 *);\n};\n\nstruct scmi_power_set_state {\n\t__le32 flags;\n\t__le32 domain;\n\t__le32 state;\n};\n\nstruct scmi_power_state_changed_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int power_state;\n\tlong: 32;\n};\n\nstruct scmi_power_state_notify {\n\t__le32 domain;\n\t__le32 notify_enable;\n};\n\nstruct scmi_power_state_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 power_state;\n};\n\nstruct scmi_powercap_cap_changed_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 power_cap;\n\t__le32 pai;\n};\n\nstruct scmi_powercap_cap_changed_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int power_cap;\n\tunsigned int pai;\n};\n\nstruct scmi_powercap_info {\n\tunsigned int id;\n\tbool notify_powercap_cap_change;\n\tbool notify_powercap_measurement_change;\n\tbool async_powercap_cap_set;\n\tbool powercap_cap_config;\n\tbool powercap_monitoring;\n\tbool powercap_pai_config;\n\tbool powercap_scale_mw;\n\tbool powercap_scale_uw;\n\tbool fastchannels;\n\tchar name[64];\n\tunsigned int min_pai;\n\tunsigned int max_pai;\n\tunsigned int pai_step;\n\tunsigned int min_power_cap;\n\tunsigned int max_power_cap;\n\tunsigned int power_cap_step;\n\tunsigned int sustainable_power;\n\tunsigned int accuracy;\n\tunsigned int parent_id;\n\tstruct scmi_fc_info *fc_info;\n};\n\nstruct scmi_powercap_meas_changed_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 power;\n};\n\nstruct scmi_powercap_meas_changed_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int power;\n\tlong: 32;\n};\n\nstruct scmi_powercap_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_powercap_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*cap_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*cap_set)(const struct scmi_protocol_handle *, u32, u32, bool);\n\tint (*cap_enable_set)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*cap_enable_get)(const struct scmi_protocol_handle *, u32, bool *);\n\tint (*pai_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*pai_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*measurements_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n\tint (*measurements_threshold_set)(const struct scmi_protocol_handle *, u32, u32, u32);\n\tint (*measurements_threshold_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n};\n\nstruct scmi_powercap_state {\n\tbool enabled;\n\tu32 last_pcap;\n\tbool meas_notif_enabled;\n\tlong: 32;\n\tu64 thresholds;\n};\n\nstruct scmi_proto_helpers_ops {\n\tint (*extended_name_get)(const struct scmi_protocol_handle *, u8, u32, u32 *, char *, size_t);\n\tvoid * (*iter_response_init)(const struct scmi_protocol_handle *, struct scmi_iterator_ops *, unsigned int, u8, size_t, void *);\n\tint (*iter_response_run)(void *);\n\tint (*protocol_msg_check)(const struct scmi_protocol_handle *, u32, u32 *);\n\tvoid (*fastchannel_init)(const struct scmi_protocol_handle *, u8, u32, u32, u32, void **, struct scmi_fc_db_info **, u32 *);\n\tvoid (*fastchannel_db_ring)(struct scmi_fc_db_info *);\n\tint (*get_max_msg_size)(const struct scmi_protocol_handle *);\n};\n\ntypedef int (*scmi_prot_init_ph_fn_t)(const struct scmi_protocol_handle *);\n\nstruct scmi_protocol_events;\n\nstruct scmi_protocol {\n\tconst u8 id;\n\tstruct module *owner;\n\tconst scmi_prot_init_ph_fn_t instance_init;\n\tconst scmi_prot_init_ph_fn_t instance_deinit;\n\tconst void *ops;\n\tconst struct scmi_protocol_events *events;\n\tunsigned int supported_version;\n\tchar *vendor_id;\n\tchar *sub_vendor_id;\n\tu32 impl_ver;\n};\n\nstruct scmi_protocol_devres {\n\tconst struct scmi_handle *handle;\n\tu8 protocol_id;\n};\n\nstruct scmi_protocol_events {\n\tsize_t queue_sz;\n\tconst struct scmi_event_ops *ops;\n\tconst struct scmi_event *evts;\n\tunsigned int num_events;\n\tunsigned int num_sources;\n};\n\nstruct scmi_xfer_ops;\n\nstruct scmi_protocol_handle {\n\tstruct device *dev;\n\tunsigned int version;\n\tconst struct scmi_xfer_ops *xops;\n\tconst struct scmi_proto_helpers_ops *hops;\n\tint (*set_priv)(const struct scmi_protocol_handle *, void *);\n\tvoid * (*get_priv)(const struct scmi_protocol_handle *);\n};\n\nstruct scmi_protocol_instance {\n\tconst struct scmi_handle *handle;\n\tconst struct scmi_protocol *proto;\n\tvoid *gid;\n\trefcount_t users;\n\tvoid *priv;\n\tunsigned int version;\n\tunsigned int negotiated_version;\n\tstruct scmi_protocol_handle ph;\n};\n\nstruct scmi_range_attrs {\n\tlong long int min_range;\n\tlong long int max_range;\n};\n\nstruct scmi_registered_event {\n\tstruct scmi_registered_events_desc *proto;\n\tconst struct scmi_event *evt;\n\tvoid *report;\n\tu32 num_sources;\n\tbool not_supported_by_platform;\n\trefcount_t *sources;\n\tstruct mutex sources_mtx;\n};\n\nstruct scmi_registered_events_desc {\n\tu8 id;\n\tconst struct scmi_event_ops *ops;\n\tstruct events_queue equeue;\n\tstruct scmi_notify_instance *ni;\n\tstruct scmi_event_header *eh;\n\tsize_t eh_sz;\n\tvoid *in_flight;\n\tint num_events;\n\tstruct scmi_registered_event **registered_events;\n\tstruct mutex registered_mtx;\n\tconst struct scmi_protocol_handle *ph;\n\tstruct hlist_head registered_events_handlers[64];\n};\n\nstruct scmi_regulator {\n\tu32 id;\n\tstruct scmi_device *sdev;\n\tstruct scmi_protocol_handle *ph;\n\tstruct regulator_dev *rdev;\n\tstruct device_node *of_node;\n\tstruct regulator_desc desc;\n\tstruct regulator_config conf;\n};\n\nstruct scmi_regulator_info {\n\tint num_doms;\n\tstruct scmi_regulator **sregv;\n};\n\nstruct scmi_requested_dev {\n\tconst struct scmi_device_id *id_table;\n\tstruct list_head node;\n};\n\nstruct scmi_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tconst struct scmi_protocol_handle *ph;\n};\n\nstruct scmi_reset_info {\n\tint num_domains;\n\tbool notify_reset_cmd;\n\tstruct reset_dom_info *dom_info;\n};\n\nstruct scmi_reset_issued_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 reset_state;\n};\n\nstruct scmi_reset_issued_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int reset_state;\n\tlong: 32;\n};\n\nstruct scmi_reset_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst char * (*name_get)(const struct scmi_protocol_handle *, u32);\n\tint (*latency_get)(const struct scmi_protocol_handle *, u32);\n\tint (*reset)(const struct scmi_protocol_handle *, u32);\n\tint (*assert)(const struct scmi_protocol_handle *, u32);\n\tint (*deassert)(const struct scmi_protocol_handle *, u32);\n};\n\nstruct scmi_resp_pinctrl_attributes {\n\t__le32 attributes;\n\tu8 name[16];\n};\n\nstruct scmi_resp_pinctrl_list_assoc {\n\t__le32 flags;\n\t__le16 array[0];\n};\n\nstruct scmi_resp_sensor_reading_complete {\n\t__le32 id;\n\t__le32 readings_low;\n\t__le32 readings_high;\n};\n\nstruct scmi_sensor_reading_resp {\n\t__le32 sensor_value_low;\n\t__le32 sensor_value_high;\n\t__le32 timestamp_low;\n\t__le32 timestamp_high;\n};\n\nstruct scmi_resp_sensor_reading_complete_v3 {\n\t__le32 id;\n\tstruct scmi_sensor_reading_resp readings[0];\n};\n\nstruct scmi_resp_settings_get {\n\t__le32 function_selected;\n\t__le32 num_configs;\n\t__le32 configs[0];\n};\n\nstruct scmi_resp_voltage_level_set_complete {\n\t__le32 domain_id;\n\t__le32 voltage_level;\n};\n\nstruct scmi_sens_ipriv {\n\tvoid *priv;\n\tstruct device *dev;\n};\n\nstruct scmi_sensor_axis_info {\n\tunsigned int id;\n\tunsigned int type;\n\tint scale;\n\tchar name[64];\n\tbool extended_attrs;\n\tunsigned int resolution;\n\tint exponent;\n\tstruct scmi_range_attrs attrs;\n};\n\nstruct scmi_sensor_intervals_info {\n\tbool segmented;\n\tunsigned int count;\n\tunsigned int *desc;\n\tunsigned int prealloc_pool[16];\n};\n\nstruct scmi_sensor_info {\n\tunsigned int id;\n\tunsigned int type;\n\tint scale;\n\tunsigned int num_trip_points;\n\tbool async;\n\tbool update;\n\tbool timestamped;\n\tint tstamp_scale;\n\tunsigned int num_axis;\n\tstruct scmi_sensor_axis_info *axis;\n\tstruct scmi_sensor_intervals_info intervals;\n\tunsigned int sensor_config;\n\tchar name[64];\n\tbool extended_scalar_attrs;\n\tunsigned int sensor_power;\n\tunsigned int resolution;\n\tint exponent;\n\tstruct scmi_range_attrs scalar_attrs;\n};\n\nstruct scmi_sensor_reading;\n\nstruct scmi_sensor_proto_ops {\n\tint (*count_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_sensor_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*trip_point_config)(const struct scmi_protocol_handle *, u32, u8, u64);\n\tint (*reading_get)(const struct scmi_protocol_handle *, u32, u64 *);\n\tint (*reading_get_timestamped)(const struct scmi_protocol_handle *, u32, u8, struct scmi_sensor_reading *);\n\tint (*config_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*config_set)(const struct scmi_protocol_handle *, u32, u32);\n};\n\nstruct scmi_sensor_reading {\n\tlong long int value;\n\tlong long unsigned int timestamp;\n};\n\nstruct scmi_sensor_trip_notify_payld {\n\t__le32 agent_id;\n\t__le32 sensor_id;\n\t__le32 trip_point_desc;\n};\n\nstruct scmi_sensor_trip_point_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int sensor_id;\n\tunsigned int trip_point_desc;\n\tlong: 32;\n};\n\nstruct scmi_sensor_update_notify_payld {\n\t__le32 agent_id;\n\t__le32 sensor_id;\n\tstruct scmi_sensor_reading_resp readings[0];\n};\n\nstruct scmi_sensor_update_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int sensor_id;\n\tunsigned int readings_count;\n\tlong: 32;\n\tstruct scmi_sensor_reading readings[0];\n};\n\nstruct scmi_sensors {\n\tconst struct scmi_protocol_handle *ph;\n\tconst struct scmi_sensor_info **info[11];\n};\n\nstruct scmi_settings_get_ipriv {\n\tu32 selector;\n\tenum scmi_pinctrl_selector_type type;\n\tbool get_all;\n\tunsigned int *nr_configs;\n\tenum scmi_pinctrl_conf_type *config_types;\n\tu32 *config_values;\n};\n\nstruct scmi_shared_mem {\n\t__le32 reserved;\n\t__le32 channel_status;\n\t__le32 reserved1[2];\n\t__le32 flags;\n\t__le32 length;\n\t__le32 msg_header;\n\tu8 msg_payload[0];\n};\n\ntypedef void (*shmem_copy_toio_t)(void *, const void *, size_t);\n\ntypedef void (*shmem_copy_fromio_t)(void *, const void *, size_t);\n\nstruct scmi_shared_mem_operations {\n\tvoid (*tx_prepare)(struct scmi_shared_mem *, struct scmi_xfer *, struct scmi_chan_info *, shmem_copy_toio_t);\n\tu32 (*read_header)(struct scmi_shared_mem *);\n\tvoid (*fetch_response)(struct scmi_shared_mem *, struct scmi_xfer *, shmem_copy_fromio_t);\n\tvoid (*fetch_notification)(struct scmi_shared_mem *, size_t, struct scmi_xfer *, shmem_copy_fromio_t);\n\tvoid (*clear_channel)(struct scmi_shared_mem *);\n\tbool (*poll_done)(struct scmi_shared_mem *, struct scmi_xfer *);\n\tbool (*channel_free)(struct scmi_shared_mem *);\n\tbool (*channel_intr_enabled)(struct scmi_shared_mem *);\n\tvoid * (*setup_iomap)(struct scmi_chan_info *, struct device *, bool, struct resource *, struct scmi_shmem_io_ops **);\n};\n\nstruct scmi_shmem_io_ops {\n\tshmem_copy_fromio_t fromio;\n\tshmem_copy_toio_t toio;\n};\n\nstruct scmi_smc {\n\tint irq;\n\tstruct scmi_chan_info *cinfo;\n\tstruct scmi_shared_mem *shmem;\n\tstruct scmi_shmem_io_ops *io_ops;\n\tstruct mutex shmem_lock;\n\tatomic_t inflight;\n\tlong unsigned int func_id;\n\tlong unsigned int param_page;\n\tlong unsigned int param_offset;\n\tlong unsigned int cap_id;\n};\n\nstruct scmi_system_info {\n\tbool graceful_timeout_supported;\n\tbool power_state_notify_cmd;\n};\n\nstruct scmi_system_power_state_notifier_payld {\n\t__le32 agent_id;\n\t__le32 flags;\n\t__le32 system_state;\n\t__le32 timeout;\n};\n\nstruct scmi_system_power_state_notifier_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int flags;\n\tunsigned int system_state;\n\tunsigned int timeout;\n};\n\nstruct scmi_system_power_state_notify {\n\t__le32 notify_enable;\n};\n\nstruct scmi_thermal_sensor {\n\tconst struct scmi_protocol_handle *ph;\n\tconst struct scmi_sensor_info *info;\n};\n\nstruct scmi_transport_core_operations;\n\nstruct scmi_transport {\n\tstruct device *supplier;\n\tstruct scmi_desc desc;\n\tstruct scmi_transport_core_operations **core_ops;\n};\n\nstruct scmi_transport_core_operations {\n\tvoid (*bad_message_trace)(struct scmi_chan_info *, u32, enum scmi_bad_msg);\n\tvoid (*rx_callback)(struct scmi_chan_info *, u32, void *);\n\tconst struct scmi_shared_mem_operations *shmem;\n\tconst struct scmi_message_operations *msg;\n};\n\nstruct scmi_transport_ops {\n\tbool (*chan_available)(struct device_node *, int);\n\tint (*chan_setup)(struct scmi_chan_info *, struct device *, bool);\n\tint (*chan_free)(int, void *, void *);\n\tunsigned int (*get_max_msg)(struct scmi_chan_info *);\n\tint (*send_message)(struct scmi_chan_info *, struct scmi_xfer *);\n\tvoid (*mark_txdone)(struct scmi_chan_info *, int, struct scmi_xfer *);\n\tvoid (*fetch_response)(struct scmi_chan_info *, struct scmi_xfer *);\n\tvoid (*fetch_notification)(struct scmi_chan_info *, size_t, struct scmi_xfer *);\n\tvoid (*clear_channel)(struct scmi_chan_info *);\n\tbool (*poll_done)(struct scmi_chan_info *, struct scmi_xfer *);\n};\n\nstruct scmi_voltage_info;\n\nstruct scmi_volt_ipriv {\n\tstruct device *dev;\n\tstruct scmi_voltage_info *v;\n};\n\nstruct scmi_voltage_info {\n\tunsigned int id;\n\tbool segmented;\n\tbool negative_volts_allowed;\n\tbool async_level_set;\n\tchar name[64];\n\tunsigned int num_levels;\n\tint *levels_uv;\n};\n\nstruct scmi_voltage_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_voltage_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*config_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*config_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*level_set)(const struct scmi_protocol_handle *, u32, enum scmi_voltage_level_mode, s32);\n\tint (*level_get)(const struct scmi_protocol_handle *, u32, s32 *);\n};\n\nstruct scmi_xfer {\n\tint transfer_id;\n\tstruct scmi_msg_hdr hdr;\n\tstruct scmi_msg tx;\n\tstruct scmi_msg rx;\n\tstruct completion done;\n\tstruct completion *async_done;\n\tbool pending;\n\tstruct hlist_node node;\n\trefcount_t users;\n\tatomic_t busy;\n\tint state;\n\tint flags;\n\tspinlock_t lock;\n\tvoid *priv;\n};\n\nstruct scmi_xfer_ops {\n\tint (*xfer_get_init)(const struct scmi_protocol_handle *, u8, size_t, size_t, struct scmi_xfer **);\n\tvoid (*reset_rx_to_maxsz)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n\tint (*do_xfer)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n\tint (*do_xfer_with_response)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n\tvoid (*xfer_put)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n};\n\nstruct scomp_alg {\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_acomp_streams streams;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tunion {\n\t\tvoid *src;\n\t\tlong unsigned int saddr;\n\t};\n};\n\nstruct scp_ctrl_reg {\n\tint pwr_sta_offs;\n\tint pwr_sta2nd_offs;\n};\n\nstruct scp_domain;\n\nstruct scp {\n\tstruct scp_domain *domains;\n\tstruct genpd_onecell_data pd_data;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct regmap *infracfg;\n\tstruct scp_ctrl_reg ctrl_reg;\n\tbool bus_prot_reg_update;\n};\n\nstruct scp_domain_data;\n\nstruct scp_domain {\n\tstruct generic_pm_domain genpd;\n\tstruct scp *scp;\n\tstruct clk *clk[3];\n\tconst struct scp_domain_data *data;\n\tstruct regulator *supply;\n};\n\nstruct scp_domain_data {\n\tconst char *name;\n\tu32 sta_mask;\n\tint ctl_offs;\n\tu32 sram_pdn_bits;\n\tu32 sram_pdn_ack_bits;\n\tu32 bus_prot_mask;\n\tenum clk_id___2 clk_id[3];\n\tu8 caps;\n};\n\nstruct scp_subdomain;\n\nstruct scp_soc_data {\n\tconst struct scp_domain_data *domains;\n\tint num_domains;\n\tconst struct scp_subdomain *subdomains;\n\tint num_subdomains;\n\tconst struct scp_ctrl_reg regs;\n\tbool bus_prot_reg_update;\n};\n\nstruct scp_subdomain {\n\tint origin;\n\tint subdomain;\n};\n\nstruct scpsys_soc_data;\n\nstruct scpsys {\n\tstruct device *dev;\n\tstruct regmap *base;\n\tconst struct scpsys_soc_data *soc_data;\n\tu8 bus_prot_index[4];\n\tstruct regmap **bus_prot;\n\tstruct genpd_onecell_data pd_data;\n\tstruct generic_pm_domain *domains[0];\n};\n\nstruct scpsys_bus_prot_data {\n\tu8 bus_prot_block;\n\tu8 bus_prot_sta_block;\n\tu32 bus_prot_set_clr_mask;\n\tu32 bus_prot_set;\n\tu32 bus_prot_clr;\n\tu32 bus_prot_sta_mask;\n\tu32 bus_prot_sta;\n\tu8 flags;\n};\n\nstruct scpsys_domain_data;\n\nstruct scpsys_hwv_domain_data;\n\nstruct scpsys_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct scpsys_domain_data *data;\n\tconst struct scpsys_hwv_domain_data *hwv_data;\n\tstruct scpsys *scpsys;\n\tint num_clks;\n\tstruct clk_bulk_data *clks;\n\tint num_subsys_clks;\n\tstruct clk_bulk_data *subsys_clks;\n\tstruct regulator *supply;\n};\n\nstruct scpsys_domain_data {\n\tconst char *name;\n\tu32 sta_mask;\n\tu32 sta2nd_mask;\n\tint ctl_offs;\n\tu32 sram_pdn_bits;\n\tu32 sram_pdn_ack_bits;\n\tint ext_buck_iso_offs;\n\tu32 ext_buck_iso_mask;\n\tu16 caps;\n\tenum scpsys_rtff_type rtff_type;\n\tconst struct scpsys_bus_prot_data bp_cfg[7];\n\tint pwr_sta_offs;\n\tint pwr_sta2nd_offs;\n};\n\nstruct scpsys_hwv_domain_data {\n\tconst char *name;\n\tu16 set;\n\tu16 clr;\n\tu16 done;\n\tu16 en;\n\tu16 set_sta;\n\tu16 clr_sta;\n\tu8 setclr_bit;\n\tu8 sta_bit;\n\tu16 caps;\n};\n\nstruct scpsys_soc_data {\n\tconst struct scpsys_domain_data *domains_data;\n\tint num_domains;\n\tconst struct scpsys_hwv_domain_data *hwv_domains_data;\n\tint num_hwv_domains;\n\tenum scpsys_bus_prot_block *bus_prot_blocks;\n\tint num_bus_prot_blocks;\n\tenum scpsys_mtcmos_type type;\n};\n\nstruct screen_info {\n\t__u8 orig_x;\n\t__u8 orig_y;\n\t__u16 ext_mem_k;\n\t__u16 orig_video_page;\n\t__u8 orig_video_mode;\n\t__u8 orig_video_cols;\n\t__u8 flags;\n\t__u8 unused2;\n\t__u16 orig_video_ega_bx;\n\t__u16 unused3;\n\t__u8 orig_video_lines;\n\t__u8 orig_video_isVGA;\n\t__u16 orig_video_points;\n\t__u16 lfb_width;\n\t__u16 lfb_height;\n\t__u16 lfb_depth;\n\t__u32 lfb_base;\n\t__u32 lfb_size;\n\t__u16 cl_magic;\n\t__u16 cl_offset;\n\t__u16 lfb_linelength;\n\t__u8 red_size;\n\t__u8 red_pos;\n\t__u8 green_size;\n\t__u8 green_pos;\n\t__u8 blue_size;\n\t__u8 blue_pos;\n\t__u8 rsvd_size;\n\t__u8 rsvd_pos;\n\t__u16 vesapm_seg;\n\t__u16 vesapm_off;\n\t__u16 pages;\n\t__u16 vesa_attributes;\n\t__u32 capabilities;\n\t__u32 ext_lfb_base;\n\t__u8 _reserved[2];\n} __attribute__((packed));\n\nstruct scsi_cd {\n\tunsigned int capacity;\n\tstruct scsi_device *device;\n\tunsigned int vendor;\n\tlong unsigned int ms_offset;\n\tunsigned int writeable: 1;\n\tunsigned int use: 1;\n\tunsigned int xa_flag: 1;\n\tunsigned int readcd_known: 1;\n\tunsigned int readcd_cdda: 1;\n\tunsigned int media_present: 1;\n\tint tur_mismatch;\n\tbool tur_changed: 1;\n\tbool get_event_changed: 1;\n\tbool ignore_get_event: 1;\n\tlong: 32;\n\tstruct cdrom_device_info cdi;\n\tstruct mutex lock;\n\tstruct gendisk *disk;\n};\n\ntypedef struct scsi_cd Scsi_CD;\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n\tlong: 32;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tlong: 32;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tlong: 32;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n\tlong: 32;\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tlong: 32;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tlong: 32;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tlong: 32;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 ic_enable: 1;\n\tu8 cs_enble: 1;\n\tu8 st_enble: 1;\n\tu8 reserved1: 3;\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved2[3];\n\tu8 lbm_descriptor_type: 4;\n\tu8 rlbsr: 2;\n\tu8 reserved3: 1;\n\tu8 acdlu: 1;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_proc_entry {\n\tstruct list_head entry;\n\tconst struct scsi_host_template *sht;\n\tstruct proc_dir_entry *proc_dir;\n\tunsigned int present;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 reserved1: 7;\n\tu8 perm: 1;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 rel_lifetime: 6;\n\tu8 reserved3: 2;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tlong: 32;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n\tlong: 32;\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tlong: 32;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tlong: 32;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tlong: 32;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tlong: 32;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\tlong: 32;\n\ts64 exit_code;\n\tconst char *reason;\n\tlong: 32;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tlong: 32;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\tlong: 32;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n\tlong: 32;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[2];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work error_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tlong: 32;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tlong: 32;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n\tlong: 32;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n\tlong: 32;\n};\n\nstruct sd_app_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct sd_busy_data {\n\tstruct mmc_card *card;\n\tu8 *reg_buf;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct sd_uhs2_wait_active_state_data {\n\tstruct mmc_host *host;\n\tstruct mmc_command *cmd;\n};\n\nstruct sdhci_adma2_64_desc {\n\t__le16 cmd;\n\t__le16 len;\n\t__le32 addr_lo;\n\t__le32 addr_hi;\n};\n\nstruct sdhci_arasan_clk_data {\n\tstruct clk_hw sdcardclk_hw;\n\tstruct clk *sdcardclk;\n\tstruct clk_hw sampleclk_hw;\n\tstruct clk *sampleclk;\n\tint clk_phase_in[11];\n\tint clk_phase_out[11];\n\tvoid (*set_clk_delays)(struct sdhci_host *);\n\tvoid *clk_of_data;\n};\n\nstruct sdhci_arasan_clk_ops {\n\tconst struct clk_ops *sdcardclk_ops;\n\tconst struct clk_ops *sampleclk_ops;\n};\n\nstruct sdhci_arasan_soc_ctl_map;\n\nstruct sdhci_arasan_data {\n\tstruct sdhci_host *host;\n\tstruct clk *clk_ahb;\n\tstruct phy *phy;\n\tbool is_phy_on;\n\tbool internal_phy_reg;\n\tbool has_cqe;\n\tstruct sdhci_arasan_clk_data clk_data;\n\tconst struct sdhci_arasan_clk_ops *clk_ops;\n\tstruct regmap *soc_ctl_base;\n\tconst struct sdhci_arasan_soc_ctl_map *soc_ctl_map;\n\tunsigned int quirks;\n};\n\nstruct sdhci_pltfm_data;\n\nstruct sdhci_arasan_of_data {\n\tconst struct sdhci_arasan_soc_ctl_map *soc_ctl_map;\n\tconst struct sdhci_pltfm_data *pdata;\n\tconst struct sdhci_arasan_clk_ops *clk_ops;\n\tu32 quirks;\n};\n\nstruct sdhci_arasan_soc_ctl_field {\n\tu32 reg;\n\tu16 width;\n\ts16 shift;\n};\n\nstruct sdhci_arasan_soc_ctl_map {\n\tstruct sdhci_arasan_soc_ctl_field baseclkfreq;\n\tstruct sdhci_arasan_soc_ctl_field clockmultiplier;\n\tstruct sdhci_arasan_soc_ctl_field support64b;\n\tbool hiword_update;\n};\n\nstruct sdhci_at91_soc_data;\n\nstruct sdhci_at91_priv {\n\tconst struct sdhci_at91_soc_data *soc_data;\n\tstruct clk *hclock;\n\tstruct clk *gck;\n\tstruct clk *mainck;\n\tbool restore_needed;\n\tbool cal_always_on;\n};\n\nstruct sdhci_at91_soc_data {\n\tconst struct sdhci_pltfm_data *pdata;\n\tbool baseclk_is_generated_internally;\n\tunsigned int divider_for_baseclk;\n};\n\nstruct sdhci_bcm_kona_dev {\n\tstruct mutex write_lock;\n};\n\nstruct sdhci_brcmstb_saved_regs {\n\tu32 sd_pin_sel;\n\tu32 phy_sw_mode0_rxctrl;\n\tu32 max_50mhz_mode;\n\tu32 boot_main_ctl;\n};\n\nstruct sdhci_brcmstb_priv {\n\tvoid *cfg_regs;\n\tvoid *boot_regs;\n\tstruct sdhci_brcmstb_saved_regs saved_regs;\n\tunsigned int flags;\n\tstruct clk *base_clk;\n\tu32 base_freq_hz;\n\tconst struct brcmstb_match_priv *match_priv;\n};\n\nstruct sdhci_esdhc {\n\tu8 vendor_ver;\n\tu8 spec_ver;\n\tbool quirk_incorrect_hostver;\n\tbool quirk_limited_clk_division;\n\tbool quirk_unreliable_pulse_detection;\n\tbool quirk_tuning_erratum_type1;\n\tbool quirk_tuning_erratum_type2;\n\tbool quirk_ignore_data_inhibit;\n\tbool quirk_delay_before_data_reset;\n\tbool quirk_trans_complete_erratum;\n\tbool in_sw_tuning;\n\tunsigned int peripheral_clock;\n\tconst struct esdhc_clk_fixup *clk_fixup;\n\tu32 div_ratio;\n};\n\nstruct sdhci_host {\n\tconst char *hw_name;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tint irq;\n\tvoid *ioaddr;\n\tphys_addr_t mapbase;\n\tchar *bounce_buffer;\n\tdma_addr_t bounce_addr;\n\tunsigned int bounce_buffer_size;\n\tconst struct sdhci_ops *ops;\n\tstruct mmc_host *mmc;\n\tstruct mmc_host_ops mmc_host_ops;\n\tu64 dma_mask;\n\tstruct led_classdev led;\n\tchar led_name[32];\n\tspinlock_t lock;\n\tint flags;\n\tunsigned int version;\n\tunsigned int max_clk;\n\tunsigned int timeout_clk;\n\tu8 max_timeout_count;\n\tunsigned int clk_mul;\n\tunsigned int clock;\n\tu8 pwr;\n\tu8 drv_type;\n\tbool reinit_uhs;\n\tbool runtime_suspended;\n\tbool bus_on;\n\tbool preset_enabled;\n\tbool pending_reset;\n\tbool irq_wake_enabled;\n\tbool v4_mode;\n\tbool use_external_dma;\n\tbool always_defer_done;\n\tstruct mmc_request *mrqs_done[2];\n\tstruct mmc_command *cmd;\n\tstruct mmc_command *data_cmd;\n\tstruct mmc_command *deferred_cmd;\n\tstruct mmc_data *data;\n\tunsigned int data_early: 1;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int blocks;\n\tint sg_count;\n\tint max_adma;\n\tvoid *adma_table;\n\tvoid *align_buffer;\n\tsize_t adma_table_sz;\n\tsize_t align_buffer_sz;\n\tdma_addr_t adma_addr;\n\tdma_addr_t align_addr;\n\tunsigned int desc_sz;\n\tunsigned int alloc_desc_sz;\n\tstruct workqueue_struct *complete_wq;\n\tstruct work_struct complete_work;\n\tstruct timer_list timer;\n\tstruct timer_list data_timer;\n\tvoid (*complete_work_fn)(struct work_struct *);\n\tirqreturn_t (*thread_irq_fn)(int, void *);\n\tstruct dma_chan *rx_chan;\n\tstruct dma_chan *tx_chan;\n\tu32 caps;\n\tu32 caps1;\n\tbool read_caps;\n\tbool sdhci_core_to_disable_vqmmc;\n\tunsigned int ocr_avail_sdio;\n\tunsigned int ocr_avail_sd;\n\tunsigned int ocr_avail_mmc;\n\tu32 ocr_mask;\n\tunsigned int timing;\n\tu32 thread_isr;\n\tu32 ier;\n\tbool cqe_on;\n\tu32 cqe_ier;\n\tu32 cqe_err_ier;\n\twait_queue_head_t buf_ready_int;\n\tunsigned int tuning_done;\n\tunsigned int tuning_count;\n\tunsigned int tuning_mode;\n\tunsigned int tuning_err;\n\tint tuning_delay;\n\tint tuning_loop_count;\n\tu32 sdma_boundary;\n\tu32 adma_table_cnt;\n\tu64 data_timeout;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct sdhci_iproc_data {\n\tconst struct sdhci_pltfm_data *pdata;\n\tu32 caps;\n\tu32 caps1;\n\tu32 mmc_caps;\n\tbool missing_caps;\n};\n\nstruct sdhci_iproc_host {\n\tconst struct sdhci_iproc_data *data;\n\tu32 shadow_cmd;\n\tu32 shadow_blk;\n\tbool is_cmd_shadowed;\n\tbool is_blk_shadowed;\n};\n\nstruct sdhci_msm_variant_ops;\n\nstruct sdhci_msm_offset;\n\nstruct sdhci_msm_host {\n\tstruct platform_device *pdev;\n\tvoid *core_mem;\n\tint pwr_irq;\n\tstruct clk *bus_clk;\n\tstruct clk *xo_clk;\n\tstruct clk_bulk_data bulk_clks[4];\n\tlong unsigned int clk_rate;\n\tstruct mmc_host *mmc;\n\tbool use_14lpp_dll_reset;\n\tbool tuning_done;\n\tbool calibration_done;\n\tu8 saved_tuning_phase;\n\tbool use_cdclp533;\n\tu32 curr_pwr_state;\n\tu32 curr_io_level;\n\twait_queue_head_t pwr_irq_wait;\n\tbool pwr_irq_flag;\n\tu32 caps_0;\n\tbool mci_removed;\n\tbool restore_dll_config;\n\tconst struct sdhci_msm_variant_ops *var_ops;\n\tconst struct sdhci_msm_offset *offset;\n\tbool use_cdr;\n\tu32 transfer_mode;\n\tbool updated_ddr_cfg;\n\tbool uses_tassadar_dll;\n\tu32 dll_config;\n\tu32 ddr_config;\n\tbool vqmmc_enabled;\n};\n\nstruct sdhci_msm_offset {\n\tu32 core_hc_mode;\n\tu32 core_mci_data_cnt;\n\tu32 core_mci_status;\n\tu32 core_mci_fifo_cnt;\n\tu32 core_mci_version;\n\tu32 core_generics;\n\tu32 core_testbus_config;\n\tu32 core_testbus_sel2_bit;\n\tu32 core_testbus_ena;\n\tu32 core_testbus_sel2;\n\tu32 core_pwrctl_status;\n\tu32 core_pwrctl_mask;\n\tu32 core_pwrctl_clear;\n\tu32 core_pwrctl_ctl;\n\tu32 core_sdcc_debug_reg;\n\tu32 core_dll_config;\n\tu32 core_dll_status;\n\tu32 core_vendor_spec;\n\tu32 core_vendor_spec_adma_err_addr0;\n\tu32 core_vendor_spec_adma_err_addr1;\n\tu32 core_vendor_spec_func2;\n\tu32 core_vendor_spec_capabilities0;\n\tu32 core_ddr_200_cfg;\n\tu32 core_vendor_spec3;\n\tu32 core_dll_config_2;\n\tu32 core_dll_config_3;\n\tu32 core_ddr_config_old;\n\tu32 core_ddr_config;\n\tu32 core_dll_usr_ctl;\n};\n\nstruct sdhci_msm_variant_info {\n\tbool mci_removed;\n\tbool restore_dll_config;\n\tconst struct sdhci_msm_variant_ops *var_ops;\n\tconst struct sdhci_msm_offset *offset;\n};\n\nstruct sdhci_msm_variant_ops {\n\tu32 (*msm_readl_relaxed)(struct sdhci_host *, u32);\n\tvoid (*msm_writel_relaxed)(u32, struct sdhci_host *, u32);\n};\n\nstruct sdhci_omap_data {\n\tint omap_offset;\n\tu32 offset;\n\tu8 flags;\n};\n\nstruct sdhci_omap_host {\n\tchar *version;\n\tvoid *base;\n\tstruct device *dev;\n\tstruct regulator *pbias;\n\tbool pbias_enabled;\n\tstruct sdhci_host *host;\n\tu8 bus_mode;\n\tu8 power_mode;\n\tu8 timing;\n\tu8 flags;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state **pinctrl_state;\n\tint wakeirq;\n\tbool is_tuning;\n\tint omap_offset;\n\tu32 con;\n\tu32 hctl;\n\tu32 sysctl;\n\tu32 capa;\n\tu32 ie;\n\tu32 ise;\n};\n\nstruct sdhci_ops {\n\tu32 (*read_l)(struct sdhci_host *, int);\n\tu16 (*read_w)(struct sdhci_host *, int);\n\tu8 (*read_b)(struct sdhci_host *, int);\n\tvoid (*write_l)(struct sdhci_host *, u32, int);\n\tvoid (*write_w)(struct sdhci_host *, u16, int);\n\tvoid (*write_b)(struct sdhci_host *, u8, int);\n\tvoid (*set_clock)(struct sdhci_host *, unsigned int);\n\tvoid (*set_power)(struct sdhci_host *, unsigned char, short unsigned int);\n\tu32 (*irq)(struct sdhci_host *, u32);\n\tint (*set_dma_mask)(struct sdhci_host *);\n\tint (*enable_dma)(struct sdhci_host *);\n\tunsigned int (*get_max_clock)(struct sdhci_host *);\n\tunsigned int (*get_min_clock)(struct sdhci_host *);\n\tunsigned int (*get_timeout_clock)(struct sdhci_host *);\n\tunsigned int (*get_max_timeout_count)(struct sdhci_host *);\n\tvoid (*set_timeout)(struct sdhci_host *, struct mmc_command *);\n\tvoid (*set_bus_width)(struct sdhci_host *, int);\n\tvoid (*platform_send_init_74_clocks)(struct sdhci_host *, u8);\n\tunsigned int (*get_ro)(struct sdhci_host *);\n\tvoid (*reset)(struct sdhci_host *, u8);\n\tint (*platform_execute_tuning)(struct sdhci_host *, u32);\n\tvoid (*set_uhs_signaling)(struct sdhci_host *, unsigned int);\n\tvoid (*hw_reset)(struct sdhci_host *);\n\tvoid (*adma_workaround)(struct sdhci_host *, u32);\n\tvoid (*card_event)(struct sdhci_host *);\n\tvoid (*voltage_switch)(struct sdhci_host *);\n\tvoid (*adma_write_desc)(struct sdhci_host *, void **, dma_addr_t, int, unsigned int);\n\tvoid (*copy_to_bounce_buffer)(struct sdhci_host *, struct mmc_data *, unsigned int);\n\tvoid (*request_done)(struct sdhci_host *, struct mmc_request *);\n\tvoid (*dump_vendor_regs)(struct sdhci_host *);\n\tvoid (*dump_uhs2_regs)(struct sdhci_host *);\n\tvoid (*uhs2_pre_detect_init)(struct sdhci_host *);\n};\n\nstruct sdhci_pltfm_data {\n\tconst struct sdhci_ops *ops;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n};\n\nstruct sdhci_pltfm_host {\n\tstruct clk *clk;\n\tunsigned int clock;\n\tu16 xfer_mode_shadow;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong unsigned int private[0];\n};\n\nstruct sdhci_pxa {\n\tstruct clk *clk_core;\n\tstruct clk *clk_io;\n\tu8 power_mode;\n\tvoid *sdio3_conf_reg;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_uhs;\n};\n\nstruct sdhci_pxa_platdata {\n\tunsigned int flags;\n\tunsigned int clk_delay_cycles;\n\tunsigned int clk_delay_sel;\n\tbool clk_delay_enable;\n\tunsigned int max_speed;\n\tu32 host_caps;\n\tu32 host_caps2;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tunsigned int pm_caps;\n};\n\nstruct sdhci_s3c {\n\tstruct sdhci_host *host;\n\tstruct platform_device *pdev;\n\tstruct resource *ioarea;\n\tstruct s3c_sdhci_platdata *pdata;\n\tint cur_clk;\n\tint ext_cd_irq;\n\tstruct clk *clk_io;\n\tstruct clk *clk_bus[4];\n\tlong unsigned int clk_rates[4];\n\tbool no_divider;\n};\n\nstruct sdhci_s3c_drv_data {\n\tunsigned int sdhci_quirks;\n\tbool no_divider;\n\tconst struct sdhci_ops *ops;\n};\n\nstruct sdhci_tegra_autocal_offsets {\n\tu32 pull_up_3v3;\n\tu32 pull_down_3v3;\n\tu32 pull_up_3v3_timeout;\n\tu32 pull_down_3v3_timeout;\n\tu32 pull_up_1v8;\n\tu32 pull_down_1v8;\n\tu32 pull_up_1v8_timeout;\n\tu32 pull_down_1v8_timeout;\n\tu32 pull_up_sdr104;\n\tu32 pull_down_sdr104;\n\tu32 pull_up_hs400;\n\tu32 pull_down_hs400;\n};\n\nstruct sdhci_tegra_soc_data;\n\nstruct sdhci_tegra {\n\tconst struct sdhci_tegra_soc_data *soc_data;\n\tstruct gpio_desc *power_gpio;\n\tstruct clk *tmclk;\n\tbool ddr_signaling;\n\tbool pad_calib_required;\n\tbool pad_control_available;\n\tstruct reset_control *rst;\n\tstruct pinctrl *pinctrl_sdmmc;\n\tstruct pinctrl_state *pinctrl_state_3v3;\n\tstruct pinctrl_state *pinctrl_state_1v8;\n\tstruct pinctrl_state *pinctrl_state_3v3_drv;\n\tstruct pinctrl_state *pinctrl_state_1v8_drv;\n\tstruct sdhci_tegra_autocal_offsets autocal_offsets;\n\tktime_t last_calib;\n\tu32 default_tap;\n\tu32 default_trim;\n\tu32 dqs_trim;\n\tbool enable_hwcq;\n\tlong unsigned int curr_clk_rate;\n\tu8 tuned_tap_delay;\n\tu32 stream_id;\n\tlong: 32;\n};\n\nstruct sdhci_tegra_soc_data {\n\tconst struct sdhci_pltfm_data *pdata;\n\tlong: 32;\n\tu64 dma_mask;\n\tu32 nvquirks;\n\tu8 min_tap_delay;\n\tu8 max_tap_delay;\n};\n\nstruct sdio_device_id {\n\t__u8 class;\n\t__u16 vendor;\n\t__u16 device;\n\tkernel_ulong_t driver_data;\n};\n\nstruct sdio_driver {\n\tchar *name;\n\tconst struct sdio_device_id *id_table;\n\tint (*probe)(struct sdio_func *, const struct sdio_device_id *);\n\tvoid (*remove)(struct sdio_func *);\n\tvoid (*shutdown)(struct sdio_func *);\n\tstruct device_driver drv;\n};\n\ntypedef void sdio_irq_handler_t(struct sdio_func *);\n\nstruct sdio_func {\n\tstruct mmc_card *card;\n\tlong: 32;\n\tstruct device dev;\n\tsdio_irq_handler_t *irq_handler;\n\tunsigned int num;\n\tunsigned char class;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tunsigned int max_blksize;\n\tunsigned int cur_blksize;\n\tunsigned int enable_timeout;\n\tunsigned int state;\n\tu8 *tmpbuf;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n\tlong: 32;\n};\n\nstruct sdio_func_tuple {\n\tstruct sdio_func_tuple *next;\n\tunsigned char code;\n\tunsigned char size;\n\tunsigned char data[0];\n};\n\nstruct sdma_mode_count {\n\tu32 count: 16;\n\tu32 status: 8;\n\tu32 command: 8;\n};\n\nstruct sdma_buffer_descriptor {\n\tstruct sdma_mode_count mode;\n\tu32 buffer_addr;\n\tu32 ext_buffer_addr;\n};\n\nstruct sdma_desc;\n\nstruct sdma_engine;\n\nstruct sdma_channel {\n\tstruct virt_dma_chan vc;\n\tstruct sdma_desc *desc;\n\tstruct sdma_engine *sdma;\n\tunsigned int channel;\n\tenum dma_transfer_direction direction;\n\tstruct dma_slave_config slave_config;\n\tenum sdma_peripheral_type peripheral_type;\n\tunsigned int event_id0;\n\tunsigned int event_id1;\n\tenum dma_slave_buswidth word_size;\n\tunsigned int pc_from_device;\n\tunsigned int pc_to_device;\n\tunsigned int device_to_device;\n\tunsigned int pc_to_pc;\n\tlong unsigned int flags;\n\tdma_addr_t per_address;\n\tdma_addr_t per_address2;\n\tlong unsigned int event_mask[2];\n\tlong unsigned int watermark_level;\n\tu32 shp_addr;\n\tu32 per_addr;\n\tenum dma_status status;\n\tstruct imx_dma_data data;\n\tstruct work_struct terminate_worker;\n\tstruct list_head terminated;\n\tbool is_ram_script;\n\tunsigned int n_fifos_src;\n\tunsigned int n_fifos_dst;\n\tunsigned int stride_fifos_src;\n\tunsigned int stride_fifos_dst;\n\tunsigned int words_per_fifo;\n\tbool sw_done;\n};\n\nstruct sdma_channel_control {\n\tu32 current_bd_ptr;\n\tu32 base_bd_ptr;\n\tu32 unused[2];\n};\n\nstruct sdma_state_registers {\n\tu32 pc: 14;\n\tu32 unused1: 1;\n\tu32 t: 1;\n\tu32 rpc: 14;\n\tu32 unused0: 1;\n\tu32 sf: 1;\n\tu32 spc: 14;\n\tu32 unused2: 1;\n\tu32 df: 1;\n\tu32 epc: 14;\n\tu32 lm: 2;\n};\n\nstruct sdma_context_data {\n\tstruct sdma_state_registers channel_state;\n\tu32 gReg[8];\n\tu32 mda;\n\tu32 msa;\n\tu32 ms;\n\tu32 md;\n\tu32 pda;\n\tu32 psa;\n\tu32 ps;\n\tu32 pd;\n\tu32 ca;\n\tu32 cs;\n\tu32 dda;\n\tu32 dsa;\n\tu32 ds;\n\tu32 dd;\n\tu32 scratch0;\n\tu32 scratch1;\n\tu32 scratch2;\n\tu32 scratch3;\n\tu32 scratch4;\n\tu32 scratch5;\n\tu32 scratch6;\n\tu32 scratch7;\n};\n\nstruct sdma_desc {\n\tstruct virt_dma_desc vd;\n\tunsigned int num_bd;\n\tdma_addr_t bd_phys;\n\tunsigned int buf_tail;\n\tunsigned int buf_ptail;\n\tunsigned int period_len;\n\tunsigned int chn_real_count;\n\tunsigned int chn_count;\n\tstruct sdma_channel *sdmac;\n\tstruct sdma_buffer_descriptor *bd;\n};\n\nstruct sdma_script_start_addrs;\n\nstruct sdma_driver_data {\n\tint chnenbl0;\n\tint num_events;\n\tstruct sdma_script_start_addrs *script_addrs;\n\tbool check_ratio;\n\tbool ecspi_fixed;\n};\n\nstruct sdma_engine {\n\tstruct device *dev;\n\tstruct sdma_channel channel[32];\n\tstruct sdma_channel_control *channel_control;\n\tvoid *regs;\n\tstruct sdma_context_data *context;\n\tdma_addr_t context_phys;\n\tstruct dma_device dma_device;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_ahb;\n\tspinlock_t channel_0_lock;\n\tu32 script_number;\n\tstruct sdma_script_start_addrs *script_addrs;\n\tconst struct sdma_driver_data *drvdata;\n\tu32 spba_start_addr;\n\tu32 spba_end_addr;\n\tunsigned int irq;\n\tdma_addr_t bd0_phys;\n\tstruct sdma_buffer_descriptor *bd0;\n\tbool clk_ratio;\n\tbool fw_loaded;\n\tstruct gen_pool *iram_pool;\n};\n\nstruct sdma_firmware_header {\n\tu32 magic;\n\tu32 version_major;\n\tu32 version_minor;\n\tu32 script_addrs_start;\n\tu32 num_script_addrs;\n\tu32 ram_code_start;\n\tu32 ram_code_size;\n};\n\nstruct sdma_peripheral_config {\n\tint n_fifos_src;\n\tint n_fifos_dst;\n\tint stride_fifos_src;\n\tint stride_fifos_dst;\n\tint words_per_fifo;\n\tbool sw_done;\n};\n\nstruct sdma_script_start_addrs {\n\ts32 ap_2_ap_addr;\n\ts32 ap_2_bp_addr;\n\ts32 ap_2_ap_fixed_addr;\n\ts32 bp_2_ap_addr;\n\ts32 loopback_on_dsp_side_addr;\n\ts32 mcu_interrupt_only_addr;\n\ts32 firi_2_per_addr;\n\ts32 firi_2_mcu_addr;\n\ts32 per_2_firi_addr;\n\ts32 mcu_2_firi_addr;\n\ts32 uart_2_per_addr;\n\ts32 uart_2_mcu_addr;\n\ts32 per_2_app_addr;\n\ts32 mcu_2_app_addr;\n\ts32 per_2_per_addr;\n\ts32 uartsh_2_per_addr;\n\ts32 uartsh_2_mcu_addr;\n\ts32 per_2_shp_addr;\n\ts32 mcu_2_shp_addr;\n\ts32 ata_2_mcu_addr;\n\ts32 mcu_2_ata_addr;\n\ts32 app_2_per_addr;\n\ts32 app_2_mcu_addr;\n\ts32 shp_2_per_addr;\n\ts32 shp_2_mcu_addr;\n\ts32 mshc_2_mcu_addr;\n\ts32 mcu_2_mshc_addr;\n\ts32 spdif_2_mcu_addr;\n\ts32 mcu_2_spdif_addr;\n\ts32 asrc_2_mcu_addr;\n\ts32 ext_mem_2_ipu_addr;\n\ts32 descrambler_addr;\n\ts32 dptc_dvfs_addr;\n\ts32 utra_addr;\n\ts32 ram_code_start_addr;\n\tunion {\n\t\ts32 v1_end;\n\t\ts32 mcu_2_ssish_addr;\n\t};\n\ts32 ssish_2_mcu_addr;\n\ts32 hdmi_dma_addr;\n\tunion {\n\t\ts32 v2_end;\n\t\ts32 zcanfd_2_mcu_addr;\n\t};\n\ts32 zqspi_2_mcu_addr;\n\ts32 mcu_2_ecspi_addr;\n\ts32 mcu_2_sai_addr;\n\ts32 sai_2_mcu_addr;\n\ts32 uart_2_mcu_rom_addr;\n\ts32 uartsh_2_mcu_rom_addr;\n\ts32 i2c_2_mcu_addr;\n\ts32 mcu_2_i2c_addr;\n\tunion {\n\t\ts32 v3_end;\n\t\ts32 mcu_2_zqspi_addr;\n\t};\n\ts32 v4_end[0];\n};\n\nstruct sdmmc_tuning_ops;\n\nstruct sdmmc_dlyb {\n\tvoid *base;\n\tu32 unit;\n\tu32 max;\n\tstruct sdmmc_tuning_ops *ops;\n};\n\nstruct sdmmc_idma {\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tdma_addr_t bounce_dma_addr;\n\tvoid *bounce_buf;\n\tbool use_bounce_buffer;\n};\n\nstruct sdmmc_lli_desc {\n\tu32 idmalar;\n\tu32 idmabase;\n\tu32 idmasize;\n};\n\nstruct sdmmc_tuning_ops {\n\tint (*dlyb_enable)(struct sdmmc_dlyb *);\n\tvoid (*set_input_ck)(struct sdmmc_dlyb *);\n\tint (*tuning_prepare)(struct mmci_host *);\n\tint (*set_cfg)(struct sdmmc_dlyb *, int, int, bool);\n};\n\nstruct sec_opmode_data {\n\tint id;\n\tunsigned int mode;\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct sec_regulator_data;\n\nstruct sec_platform_data {\n\tstruct sec_regulator_data *regulators;\n\tstruct sec_opmode_data *opmode;\n\tint num_regulators;\n\tint buck_gpios[3];\n\tint buck_ds[3];\n\tunsigned int buck2_voltage[8];\n\tbool buck2_gpiodvs;\n\tunsigned int buck3_voltage[8];\n\tbool buck3_gpiodvs;\n\tunsigned int buck4_voltage[8];\n\tbool buck4_gpiodvs;\n\tint buck_default_idx;\n\tint buck_ramp_delay;\n\tbool buck2_ramp_enable;\n\tbool buck3_ramp_enable;\n\tbool buck4_ramp_enable;\n\tint buck2_init;\n\tint buck3_init;\n\tint buck4_init;\n\tbool manual_poweroff;\n\tbool disable_wrstbi;\n};\n\nstruct sec_pmic_dev {\n\tstruct device *dev;\n\tstruct sec_platform_data *pdata;\n\tstruct regmap *regmap_pmic;\n\tstruct i2c_client *i2c;\n\tint device_type;\n\tint irq;\n};\n\nstruct sec_pmic_i2c_platform_data {\n\tconst struct regmap_config *regmap_cfg;\n\tint device_type;\n};\n\nstruct sec_regulator_data {\n\tint id;\n\tstruct regulator_init_data *initdata;\n\tstruct device_node *reg_node;\n\tstruct gpio_desc *ext_control_gpiod;\n};\n\nstruct sec_voltage_desc {\n\tint max;\n\tint min;\n\tint step;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tlong: 32;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n\tlong: 32;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct secondary_data {\n\tunion {\n\t\tstruct mpu_rgn_info *mpu_rgn_info;\n\t\tu64 pgdir;\n\t};\n\tlong unsigned int swapper_pg_dir;\n\tvoid *stack;\n\tstruct task_struct *task;\n\tlong: 32;\n};\n\nstruct section_perm {\n\tconst char *name;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tpmdval_t mask;\n\tpmdval_t prot;\n\tpmdval_t clear;\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nstruct sel_arg_struct {\n\tlong unsigned int n;\n\tfd_set *inp;\n\tfd_set *outp;\n\tfd_set *exp;\n\tstruct __kernel_old_timeval *tvp;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tlong: 32;\n\ttime64_t sem_otime;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sembuf;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\tlong unsigned int sem_otime;\n\tlong unsigned int sem_otime_high;\n\tlong unsigned int sem_ctime;\n\tlong unsigned int sem_ctime_high;\n\tlong unsigned int sem_nsems;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct virtnet_sq_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_tx_drops;\n\tu64_stats_t kicks;\n\tu64_stats_t tx_timeouts;\n\tu64_stats_t stop;\n\tu64_stats_t wake;\n};\n\nstruct send_queue {\n\tstruct virtqueue *vq;\n\tstruct scatterlist sg[19];\n\tchar name[16];\n\tstruct virtnet_sq_stats stats;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct napi_struct napi;\n\tbool reset;\n\tstruct xsk_buff_pool *xsk_pool;\n\tdma_addr_t xsk_hdr_dma_addr;\n\tlong: 32;\n};\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n\tbool has_siginfo;\n\tstruct kernel_siginfo info;\n};\n\nstruct sensor_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint index;\n};\n\nstruct sensors_info {\n\tbool notify_trip_point_cmd;\n\tbool notify_continuos_update_cmd;\n\tint num_sensors;\n\tint max_requests;\n\tlong: 32;\n\tu64 reg_addr;\n\tu32 reg_size;\n\tstruct scmi_sensor_info *sensors;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct seqcount_rwlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_rwlock seqcount_rwlock_t;\n\nstruct serdes_cfg {\n\tu32 ofs;\n\tu32 val;\n\tu32 mask;\n};\n\nstruct serdev_device;\n\nstruct serdev_controller_ops;\n\nstruct serdev_controller {\n\tstruct device dev;\n\tstruct device *host;\n\tunsigned int nr;\n\tstruct serdev_device *serdev;\n\tconst struct serdev_controller_ops *ops;\n};\n\nstruct serdev_controller_ops {\n\tssize_t (*write_buf)(struct serdev_controller *, const u8 *, size_t);\n\tvoid (*write_flush)(struct serdev_controller *);\n\tint (*open)(struct serdev_controller *);\n\tvoid (*close)(struct serdev_controller *);\n\tvoid (*set_flow_control)(struct serdev_controller *, bool);\n\tint (*set_parity)(struct serdev_controller *, enum serdev_parity);\n\tunsigned int (*set_baudrate)(struct serdev_controller *, unsigned int);\n\tvoid (*wait_until_sent)(struct serdev_controller *, long int);\n\tint (*get_tiocm)(struct serdev_controller *);\n\tint (*set_tiocm)(struct serdev_controller *, unsigned int, unsigned int);\n\tint (*break_ctl)(struct serdev_controller *, unsigned int);\n};\n\nstruct serdev_device_ops;\n\nstruct serdev_device {\n\tstruct device dev;\n\tint nr;\n\tstruct serdev_controller *ctrl;\n\tconst struct serdev_device_ops *ops;\n\tstruct completion write_comp;\n\tstruct mutex write_lock;\n};\n\nstruct serdev_device_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct serdev_device *);\n\tvoid (*remove)(struct serdev_device *);\n\tvoid (*shutdown)(struct serdev_device *);\n};\n\nstruct serdev_device_ops {\n\tsize_t (*receive_buf)(struct serdev_device *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct serdev_device *);\n};\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct serial8250_em_priv {\n\tint line;\n};\n\nstruct serial_ctrl_device {\n\tstruct device dev;\n\tstruct ida port_ida;\n\tlong: 32;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_port_device {\n\tstruct device dev;\n\tstruct uart_port *port;\n\tunsigned int tx_enabled: 1;\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\ntypedef struct serio *class_serio_pause_rx_t;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tlong: 32;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n\tlong: 32;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nstruct serport {\n\tstruct tty_port *port;\n\tstruct tty_struct *tty;\n\tstruct tty_driver *tty_drv;\n\tint tty_idx;\n\tlong unsigned int flags;\n};\n\nstruct serport___2 {\n\tstruct tty_struct *tty;\n\twait_queue_head_t wait;\n\tstruct serio *serio;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_config_request {\n\tstruct usb_device *udev;\n\tint config;\n\tstruct work_struct work;\n\tstruct list_head node;\n};\n\nstruct set_event_iter {\n\tenum set_event_iter_type type;\n\tunion {\n\t\tstruct trace_event_file *file;\n\t\tstruct event_mod_load *event_mod;\n\t};\n};\n\nstruct sfdp {\n\tsize_t num_dwords;\n\tu32 *dwords;\n};\n\nstruct sfdp_4bait {\n\tu32 hwcaps;\n\tu32 supported_bit;\n};\n\nstruct sfdp_bfpt {\n\tu32 dwords[20];\n};\n\nstruct sfdp_bfpt_erase {\n\tu32 dword;\n\tu32 shift;\n};\n\nstruct sfdp_bfpt_read {\n\tu32 hwcaps;\n\tu32 supported_dword;\n\tu32 supported_bit;\n\tu32 settings_dword;\n\tu32 settings_shift;\n\tenum spi_nor_protocol proto;\n};\n\nstruct sfdp_parameter_header {\n\tu8 id_lsb;\n\tu8 minor;\n\tu8 major;\n\tu8 length;\n\tu8 parameter_table_pointer[3];\n\tu8 id_msb;\n};\n\nstruct sfdp_header {\n\tu32 signature;\n\tu8 minor;\n\tu8 major;\n\tu8 nph;\n\tu8 unused;\n\tstruct sfdp_parameter_header bfpt_header;\n};\n\nstruct sfp;\n\nstruct sfp_module_caps {\n\tlong unsigned int interfaces[2];\n\tlong unsigned int link_modes[4];\n\tbool may_have_phy;\n\tu8 port;\n};\n\nstruct sfp_socket_ops;\n\nstruct sfp_upstream_ops;\n\nstruct sfp_bus {\n\tstruct kref kref;\n\tstruct list_head node;\n\tconst struct fwnode_handle *fwnode;\n\tconst struct sfp_socket_ops *socket_ops;\n\tstruct device *sfp_dev;\n\tstruct sfp *sfp;\n\tconst struct sfp_upstream_ops *upstream_ops;\n\tvoid *upstream;\n\tstruct phy_device *phydev;\n\tbool registered;\n\tbool started;\n\tstruct sfp_module_caps caps;\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_quirk {\n\tconst char *vendor;\n\tconst char *part;\n\tvoid (*support)(const struct sfp_eeprom_id *, struct sfp_module_caps *);\n\tvoid (*fixup)(struct sfp *);\n};\n\nstruct sfp_socket_ops {\n\tvoid (*attach)(struct sfp *);\n\tvoid (*detach)(struct sfp *);\n\tvoid (*start)(struct sfp *);\n\tvoid (*stop)(struct sfp *);\n\tvoid (*set_signal_rate)(struct sfp *, unsigned int);\n\tint (*module_info)(struct sfp *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct sfp *, struct ethtool_eeprom *, u8 *);\n\tint (*module_eeprom_by_page)(struct sfp *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *, struct phy_device *);\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_desc {\n\t__le32 total_len;\n\t__le32 resvd0;\n\t__le32 linear_addr;\n\t__le32 linear_len;\n\tstruct frags_info frags[18];\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_list {\n\tunsigned int n;\n\tunsigned int size;\n\tsize_t len;\n\tstruct scatterlist *sg;\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sg_splitter {\n\tstruct scatterlist *in_sg0;\n\tint nents;\n\toff_t skip_sg0;\n\tunsigned int length_last_sg;\n\tstruct scatterlist *out_sg;\n};\n\nstruct sgpio_priv;\n\nstruct sgpio_bank {\n\tstruct sgpio_priv *priv;\n\tbool is_input;\n\tstruct gpio_chip gpio;\n\tstruct pinctrl_desc pctl_desc;\n};\n\nstruct sgpio_port_addr {\n\tu8 port;\n\tu8 bit;\n};\n\nstruct sgpio_properties;\n\nstruct sgpio_priv {\n\tstruct device *dev;\n\tstruct sgpio_bank in;\n\tstruct sgpio_bank out;\n\tu32 bitcount;\n\tu32 ports;\n\tu32 clock;\n\tstruct regmap *regs;\n\tconst struct sgpio_properties *properties;\n\tspinlock_t lock;\n\tstruct mutex poll_lock;\n};\n\nstruct sgpio_properties {\n\tint arch;\n\tint flags;\n\tu8 regoff[10];\n};\n\nstruct sh73a0_cpg {\n\tstruct clk_onecell_data data;\n\tspinlock_t lock;\n};\n\nstruct sh_cmt_device;\n\nstruct sh_cmt_channel {\n\tstruct sh_cmt_device *cmt;\n\tunsigned int index;\n\tunsigned int hwidx;\n\tvoid *iostart;\n\tvoid *ioctrl;\n\tunsigned int timer_bit;\n\tlong unsigned int flags;\n\tu32 match_value;\n\tu32 next_match_value;\n\tu32 max_match_value;\n\traw_spinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device ced;\n\tstruct clocksource cs;\n\tu64 total_cycles;\n\tbool cs_enabled;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct sh_cmt_info;\n\nstruct sh_cmt_device {\n\tstruct platform_device *pdev;\n\tconst struct sh_cmt_info *info;\n\tvoid *mapbase;\n\tstruct clk *clk;\n\tlong unsigned int rate;\n\tunsigned int reg_delay;\n\traw_spinlock_t lock;\n\tstruct sh_cmt_channel *channels;\n\tunsigned int num_channels;\n\tunsigned int hw_channels;\n\tbool has_clockevent;\n\tbool has_clocksource;\n};\n\nstruct sh_cmt_info {\n\tenum sh_cmt_model model;\n\tunsigned int channels_mask;\n\tlong unsigned int width;\n\tu32 overflow_bit;\n\tu32 clear_bits;\n\tu32 (*read_control)(void *, long unsigned int);\n\tvoid (*write_control)(void *, long unsigned int, u32);\n\tu32 (*read_count)(void *, long unsigned int);\n\tvoid (*write_count)(void *, long unsigned int, u32);\n};\n\nstruct sh_eth_cpu_data {\n\tint (*soft_reset)(struct net_device *);\n\tvoid (*chip_reset)(struct net_device *);\n\tvoid (*set_duplex)(struct net_device *);\n\tvoid (*set_rate)(struct net_device *);\n\tint register_type;\n\tu32 edtrr_trns;\n\tu32 eesipr_value;\n\tu32 ecsr_value;\n\tu32 ecsipr_value;\n\tu32 fdr_value;\n\tu32 fcftr_value;\n\tu32 tx_check;\n\tu32 eesr_err_check;\n\tu32 trscer_err_mask;\n\tlong unsigned int irq_flags;\n\tunsigned int no_psr: 1;\n\tunsigned int apr: 1;\n\tunsigned int mpr: 1;\n\tunsigned int tpauser: 1;\n\tunsigned int gecmr: 1;\n\tunsigned int bculr: 1;\n\tunsigned int tsu: 1;\n\tunsigned int hw_swap: 1;\n\tunsigned int nbst: 1;\n\tunsigned int rpadir: 1;\n\tunsigned int no_trimd: 1;\n\tunsigned int no_ade: 1;\n\tunsigned int no_xdfar: 1;\n\tunsigned int xdfar_rw: 1;\n\tunsigned int csmr: 1;\n\tunsigned int rx_csum: 1;\n\tunsigned int select_mii: 1;\n\tunsigned int rmiimode: 1;\n\tunsigned int rtrate: 1;\n\tunsigned int magic: 1;\n\tunsigned int no_tx_cntrs: 1;\n\tunsigned int cexcr: 1;\n\tunsigned int dual_port: 1;\n};\n\nstruct sh_eth_plat_data {\n\tint phy;\n\tint phy_irq;\n\tphy_interface_t phy_interface;\n\tvoid (*set_mdio_gate)(void *);\n\tunsigned char mac_addr[6];\n\tunsigned int no_ether_link: 1;\n\tunsigned int ether_link_active_low: 1;\n};\n\nstruct sh_eth_rxdesc;\n\nstruct sh_eth_txdesc;\n\nstruct sh_eth_private {\n\tstruct platform_device *pdev;\n\tstruct sh_eth_cpu_data *cd;\n\tconst u16 *reg_offset;\n\tvoid *addr;\n\tvoid *tsu_addr;\n\tstruct clk *clk;\n\tu32 num_rx_ring;\n\tu32 num_tx_ring;\n\tdma_addr_t rx_desc_dma;\n\tdma_addr_t tx_desc_dma;\n\tstruct sh_eth_rxdesc *rx_ring;\n\tstruct sh_eth_txdesc *tx_ring;\n\tstruct sk_buff **rx_skbuff;\n\tstruct sk_buff **tx_skbuff;\n\tspinlock_t lock;\n\tu32 cur_rx;\n\tu32 dirty_rx;\n\tu32 cur_tx;\n\tu32 dirty_tx;\n\tu32 rx_buf_sz;\n\tstruct napi_struct napi;\n\tbool irq_enabled;\n\tu32 phy_id;\n\tstruct mii_bus *mii_bus;\n\tint link;\n\tphy_interface_t phy_interface;\n\tint msg_enable;\n\tint speed;\n\tint duplex;\n\tint port;\n\tint vlan_num_ids;\n\tunsigned int no_ether_link: 1;\n\tunsigned int ether_link_active_low: 1;\n\tunsigned int is_opened: 1;\n\tunsigned int wol_enabled: 1;\n\tlong: 32;\n};\n\nstruct sh_eth_rxdesc {\n\tu32 status;\n\tu32 len;\n\tu32 addr;\n\tu32 pad0;\n};\n\nstruct sh_eth_txdesc {\n\tu32 status;\n\tu32 len;\n\tu32 addr;\n\tu32 pad0;\n};\n\nstruct sh_mmcif_host {\n\tstruct mmc_host *mmc;\n\tstruct mmc_request *mrq;\n\tstruct platform_device *pd;\n\tstruct clk *clk;\n\tint bus_width;\n\tunsigned char timing;\n\tbool sd_error;\n\tbool dying;\n\tlong int timeout;\n\tvoid *addr;\n\tspinlock_t lock;\n\tenum sh_mmcif_state state;\n\tenum sh_mmcif_wait_for wait_for;\n\tstruct delayed_work timeout_work;\n\tsize_t blocksize;\n\tstruct sg_mapping_iter sg_miter;\n\tbool power;\n\tbool ccs_enable;\n\tbool clk_ctrl2_enable;\n\tstruct mutex thread_lock;\n\tu32 clkdiv_map;\n\tstruct dma_chan *chan_rx;\n\tstruct dma_chan *chan_tx;\n\tstruct completion dma_complete;\n\tbool dma_active;\n};\n\nstruct sh_mmcif_plat_data {\n\tunsigned int slave_id_tx;\n\tunsigned int slave_id_rx;\n\tu8 sup_pclk;\n\tlong unsigned int caps;\n\tu32 ocr;\n};\n\nstruct sh_mobile_i2c_data;\n\nstruct sh_mobile_dt_config {\n\tint clks_per_count;\n\tint (*setup)(struct sh_mobile_i2c_data *);\n};\n\nstruct sh_mobile_i2c_data {\n\tstruct device *dev;\n\tvoid *reg;\n\tstruct i2c_adapter adap;\n\tlong unsigned int bus_speed;\n\tunsigned int clks_per_count;\n\tstruct clk *clk;\n\tu_int8_t icic;\n\tu_int8_t flags;\n\tu_int16_t iccl;\n\tu_int16_t icch;\n\tspinlock_t lock;\n\twait_queue_head_t wait;\n\tstruct i2c_msg *msg;\n\tint pos;\n\tint sr;\n\tbool send_stop;\n\tbool stop_after_dma;\n\tbool atomic_xfer;\n\tstruct resource *res;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tstruct scatterlist sg;\n\tenum dma_data_direction dma_direction;\n\tu8 *dma_buf;\n\tlong: 32;\n};\n\nstruct sh_mtu2_device;\n\nstruct sh_mtu2_channel {\n\tstruct sh_mtu2_device *mtu;\n\tunsigned int index;\n\tvoid *base;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device ced;\n};\n\nstruct sh_mtu2_device {\n\tstruct platform_device *pdev;\n\tvoid *mapbase;\n\tstruct clk *clk;\n\traw_spinlock_t lock;\n\tstruct sh_mtu2_channel *channels;\n\tunsigned int num_channels;\n\tbool has_clockevent;\n};\n\nstruct sh_pfc_soc_info;\n\nstruct sh_pfc_window;\n\nstruct sh_pfc_pin_range;\n\nstruct sh_pfc_chip;\n\nstruct sh_pfc {\n\tstruct device *dev;\n\tconst struct sh_pfc_soc_info *info;\n\tspinlock_t lock;\n\tunsigned int num_windows;\n\tstruct sh_pfc_window *windows;\n\tunsigned int num_irqs;\n\tunsigned int *irqs;\n\tstruct sh_pfc_pin_range *ranges;\n\tunsigned int nr_ranges;\n\tunsigned int nr_gpio_pins;\n\tstruct sh_pfc_chip *gpio;\n\tu32 *saved_regs;\n};\n\nstruct sh_pfc_gpio_data_reg;\n\nstruct sh_pfc_gpio_pin;\n\nstruct sh_pfc_chip {\n\tstruct sh_pfc *pfc;\n\tstruct gpio_chip gpio_chip;\n\tstruct sh_pfc_window *mem;\n\tstruct sh_pfc_gpio_data_reg *regs;\n\tstruct sh_pfc_gpio_pin *pins;\n};\n\nstruct sh_pfc_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int nr_groups;\n};\n\nstruct sh_pfc_gpio_data_reg {\n\tconst struct pinmux_data_reg *info;\n\tu32 shadow;\n};\n\nstruct sh_pfc_gpio_pin {\n\tu8 dbit;\n\tu8 dreg;\n};\n\nstruct sh_pfc_pin {\n\tconst char *name;\n\tunsigned int configs;\n\tu16 pin;\n\tu16 enum_id;\n};\n\nstruct sh_pfc_pin_config {\n\tu16 gpio_enabled: 1;\n\tu16 mux_mark: 15;\n};\n\nstruct sh_pfc_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tconst unsigned int *mux;\n\tunsigned int nr_pins;\n};\n\nstruct sh_pfc_pin_range {\n\tu16 start;\n\tu16 end;\n};\n\nstruct sh_pfc_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct sh_pfc *pfc;\n\tstruct pinctrl_pin_desc *pins;\n\tstruct sh_pfc_pin_config *configs;\n};\n\nstruct sh_pfc_soc_operations;\n\nstruct sh_pfc_soc_info {\n\tconst char *name;\n\tconst struct sh_pfc_soc_operations *ops;\n\tstruct pinmux_range input;\n\tstruct pinmux_range output;\n\tconst struct pinmux_irq *gpio_irq;\n\tunsigned int gpio_irq_size;\n\tstruct pinmux_range function;\n\tconst struct sh_pfc_pin *pins;\n\tunsigned int nr_pins;\n\tconst struct sh_pfc_pin_group *groups;\n\tunsigned int nr_groups;\n\tconst struct sh_pfc_function *functions;\n\tunsigned int nr_functions;\n\tconst struct pinmux_cfg_reg *cfg_regs;\n\tconst struct pinmux_drive_reg *drive_regs;\n\tconst struct pinmux_bias_reg *bias_regs;\n\tconst struct pinmux_ioctrl_reg *ioctrl_regs;\n\tconst struct pinmux_data_reg *data_regs;\n\tconst u16 *pinmux_data;\n\tunsigned int pinmux_data_size;\n\tu32 unlock_reg;\n};\n\nstruct sh_pfc_soc_operations {\n\tint (*init)(struct sh_pfc *);\n\tunsigned int (*get_bias)(struct sh_pfc *, unsigned int);\n\tvoid (*set_bias)(struct sh_pfc *, unsigned int, unsigned int);\n\tint (*pin_to_pocctrl)(unsigned int, u32 *);\n\tint (*pin_to_portcr)(unsigned int);\n};\n\nstruct sh_pfc_window {\n\tphys_addr_t phys;\n\tvoid *virt;\n\tlong unsigned int size;\n};\n\nstruct sh_timer_config {\n\tunsigned int channels_mask;\n};\n\nstruct sh_tmu_device;\n\nstruct sh_tmu_channel {\n\tstruct sh_tmu_device *tmu;\n\tunsigned int index;\n\tvoid *base;\n\tint irq;\n\tlong unsigned int periodic;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device ced;\n\tstruct clocksource cs;\n\tbool cs_enabled;\n\tunsigned int enable_count;\n};\n\nstruct sh_tmu_device {\n\tstruct platform_device *pdev;\n\tvoid *mapbase;\n\tstruct clk *clk;\n\tlong unsigned int rate;\n\tenum sh_tmu_model model;\n\traw_spinlock_t lock;\n\tstruct sh_tmu_channel *channels;\n\tunsigned int num_channels;\n\tbool has_clockevent;\n\tbool has_clocksource;\n};\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct shared_policy {};\n\nstruct shash_desc;\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*export_core)(struct shash_desc *, void *);\n\tint (*import_core)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tint (*clone_tfm)(struct crypto_shash *, struct crypto_shash *);\n\tunsigned int descsize;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int digestsize;\n\t\t\tunsigned int statesize;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct hash_alg_common halg;\n\t};\n};\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct shdwc {\n\tstruct clk *sclk;\n\tvoid *shdwc_base;\n\tvoid *mpddrc_base;\n};\n\nstruct shdwc___2 {\n\tconst struct reg_config *rcfg;\n\tstruct clk *sclk;\n\tvoid *shdwc_base;\n\tvoid *mpddrc_base;\n\tvoid *pmc_base;\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tlong: 32;\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tlong: 32;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tlong: 32;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tlong: 32;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\t__kernel_size_t shm_segsz;\n\tlong unsigned int shm_atime;\n\tlong unsigned int shm_atime_high;\n\tlong unsigned int shm_dtime;\n\tlong unsigned int shm_dtime_high;\n\tlong unsigned int shm_ctime;\n\tlong unsigned int shm_ctime_high;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\tlong: 32;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct shortname_info {\n\tunsigned char lower: 1;\n\tunsigned char upper: 1;\n\tunsigned char valid: 1;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct sifive_fu540_macb_mgmt {\n\tvoid *reg;\n\tlong unsigned int rate;\n\tstruct clk_hw hw;\n};\n\nstruct sig_alg {\n\tint (*sign)(struct crypto_sig *, const void *, unsigned int, void *, unsigned int);\n\tint (*verify)(struct crypto_sig *, const void *, unsigned int, const void *, unsigned int);\n\tint (*set_pub_key)(struct crypto_sig *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_sig *, const void *, unsigned int);\n\tunsigned int (*key_size)(struct crypto_sig *);\n\tunsigned int (*digest_size)(struct crypto_sig *);\n\tunsigned int (*max_size)(struct crypto_sig *);\n\tint (*init)(struct crypto_sig *);\n\tvoid (*exit)(struct crypto_sig *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct crypto_alg base;\n};\n\nstruct sig_instance {\n\tvoid (*free)(struct sig_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t};\n\t\tstruct sig_alg alg;\n\t};\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[13];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {};\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tlong: 32;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tseqlock_t stats_lock;\n\tlong: 32;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct sih_irq_data {\n\tu8 isr_offset;\n\tu8 imr_offset;\n};\n\nstruct sih {\n\tchar name[8];\n\tu8 module;\n\tu8 control_offset;\n\tbool set_cor;\n\tu8 bits;\n\tu8 bytes_ixr;\n\tu8 edr_offset;\n\tu8 bytes_edr;\n\tu8 irq_lines;\n\tstruct sih_irq_data mask[2];\n};\n\nstruct sih_agent {\n\tint irq_base;\n\tconst struct sih *sih;\n\tu32 imr;\n\tbool imr_change_pending;\n\tu32 edge_change;\n\tstruct mutex irq_lock;\n\tchar *irq_name;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_pm_bus {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct simplefb_format {\n\tconst char *name;\n\tu32 bits_per_pixel;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tu32 fourcc;\n};\n\nstruct simplefb_par {\n\tu32 palette[16];\n\tresource_size_t base;\n\tresource_size_t size;\n\tstruct resource *mem;\n\tbool clks_enabled;\n\tunsigned int clk_count;\n\tstruct clk **clks;\n\tunsigned int num_genpds;\n\tstruct device **genpds;\n\tstruct device_link **genpd_links;\n\tbool regulators_enabled;\n\tu32 regulator_count;\n\tstruct regulator **regulators;\n};\n\nstruct simplefb_params {\n\tu32 width;\n\tu32 height;\n\tu32 stride;\n\tstruct simplefb_format *format;\n\tstruct resource memory;\n};\n\nstruct simplefb_platform_data {\n\tu32 width;\n\tu32 height;\n\tu32 stride;\n\tconst char *format;\n};\n\nstruct sit_net {\n\tstruct ip_tunnel *tunnels_r_l[16];\n\tstruct ip_tunnel *tunnels_r[16];\n\tstruct ip_tunnel *tunnels_l[16];\n\tstruct ip_tunnel *tunnels_wc[1];\n\tstruct ip_tunnel **tunnels[4];\n\tstruct net_device *fb_tunnel_dev;\n};\n\nstruct size_entry {\n\tstruct rb_node rb;\n\tino_t inum;\n\tloff_t i_size;\n\tloff_t d_size;\n\tint exists;\n\tstruct inode *inode;\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n\tlong: 32;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_data {\n\tstruct urb *urb;\n\tstruct usbnet *dev;\n\tenum skb_state state;\n\tlong int length;\n\tlong unsigned int packets;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct skb_ext {\n\trefcount_t refcnt;\n\tu8 offset[2];\n\tu8 chunks;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tlong: 32;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*export)(struct skcipher_request *, void *);\n\tint (*import)(struct skcipher_request *, const void *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int walksize;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int min_keysize;\n\t\t\tunsigned int max_keysize;\n\t\t\tunsigned int ivsize;\n\t\t\tunsigned int chunksize;\n\t\t\tunsigned int statesize;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tlong: 32;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct skcipher_alg_common co;\n\t};\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tchar head[128];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tvoid *__ctx[0];\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int nbytes;\n\tunsigned int total;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct sleep_save_sp {\n\tu32 *save_ptr_stash;\n\tu32 save_ptr_stash_phys;\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct smd_channel_info {\n\t__le32 state;\n\tu8 fDSR;\n\tu8 fCTS;\n\tu8 fCD;\n\tu8 fRI;\n\tu8 fHEAD;\n\tu8 fTAIL;\n\tu8 fSTATE;\n\tu8 fBLOCKREADINTR;\n\t__le32 tail;\n\t__le32 head;\n};\n\nstruct smd_channel_info_pair {\n\tstruct smd_channel_info tx;\n\tstruct smd_channel_info rx;\n};\n\nstruct smd_channel_info_word {\n\t__le32 state;\n\t__le32 fDSR;\n\t__le32 fCTS;\n\t__le32 fCD;\n\t__le32 fRI;\n\t__le32 fHEAD;\n\t__le32 fTAIL;\n\t__le32 fSTATE;\n\t__le32 fBLOCKREADINTR;\n\t__le32 tail;\n\t__le32 head;\n};\n\nstruct smd_channel_info_word_pair {\n\tstruct smd_channel_info_word tx;\n\tstruct smd_channel_info_word rx;\n};\n\nstruct smem_global_entry {\n\t__le32 allocated;\n\t__le32 offset;\n\t__le32 size;\n\t__le32 aux_base;\n};\n\nstruct smem_proc_comm {\n\t__le32 command;\n\t__le32 status;\n\t__le32 params[2];\n};\n\nstruct smem_header {\n\tstruct smem_proc_comm proc_comm[4];\n\t__le32 version[32];\n\t__le32 initialized;\n\t__le32 free_offset;\n\t__le32 available;\n\t__le32 reserved;\n\tstruct smem_global_entry toc[512];\n};\n\nstruct smem_info {\n\tu8 magic[4];\n\t__le32 size;\n\t__le32 base_addr;\n\t__le32 reserved;\n\t__le16 num_items;\n};\n\nstruct smem_partition_header {\n\tu8 magic[4];\n\t__le16 host0;\n\t__le16 host1;\n\t__le32 size;\n\t__le32 offset_free_uncached;\n\t__le32 offset_free_cached;\n\t__le32 reserved[3];\n};\n\nstruct smem_private_entry {\n\tu16 canary;\n\t__le16 item;\n\t__le32 size;\n\t__le16 padding_data;\n\t__le16 padding_hdr;\n\t__le32 reserved;\n};\n\nstruct smem_ptable_entry {\n\t__le32 offset;\n\t__le32 size;\n\t__le32 flags;\n\t__le16 host0;\n\t__le16 host1;\n\t__le32 cacheline;\n\t__le32 reserved[7];\n};\n\nstruct smem_ptable {\n\tu8 magic[4];\n\t__le32 version;\n\t__le32 num_entries;\n\t__le32 reserved[5];\n\tstruct smem_ptable_entry entry[0];\n};\n\nstruct smp2p_entry {\n\tstruct list_head node;\n\tstruct qcom_smp2p *smp2p;\n\tconst char *name;\n\tu32 *value;\n\tu32 last_value;\n\tstruct irq_domain *domain;\n\tlong unsigned int irq_enabled[1];\n\tlong unsigned int irq_rising[1];\n\tlong unsigned int irq_falling[1];\n\tstruct qcom_smem_state *state;\n\tspinlock_t lock;\n};\n\nstruct smp2p_smem_item {\n\tu32 magic;\n\tu8 version;\n\tunsigned int features: 24;\n\tu16 local_pid;\n\tu16 remote_pid;\n\tu16 total_entries;\n\tu16 valid_entries;\n\tu32 flags;\n\tstruct {\n\t\tu8 name[16];\n\t\tu32 value;\n\t} entries[16];\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smp_operations {\n\tvoid (*smp_init_cpus)(void);\n\tvoid (*smp_prepare_cpus)(unsigned int);\n\tvoid (*smp_secondary_init)(unsigned int);\n\tint (*smp_boot_secondary)(unsigned int, struct task_struct *);\n\tint (*cpu_kill)(unsigned int);\n\tvoid (*cpu_die)(unsigned int);\n\tbool (*cpu_can_disable)(unsigned int);\n\tint (*cpu_disable)(unsigned int);\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct smsc75xx_priv {\n\tstruct usbnet *dev;\n\tu32 rfe_ctl;\n\tu32 wolopts;\n\tu32 multicast_hash_table[16];\n\tstruct mutex dataport_mutex;\n\tspinlock_t rfe_ctl_lock;\n\tstruct work_struct set_multicast;\n\tu8 suspend_flags;\n};\n\nstruct smsc911x_platform_config {\n\tunsigned int irq_polarity;\n\tunsigned int irq_type;\n\tunsigned int flags;\n\tunsigned int shift;\n\tphy_interface_t phy_interface;\n\tunsigned char mac[6];\n};\n\nstruct smsc911x_ops;\n\nstruct smsc911x_data {\n\tvoid *ioaddr;\n\tunsigned int idrev;\n\tunsigned int generation;\n\tstruct smsc911x_platform_config config;\n\tspinlock_t mac_lock;\n\tspinlock_t dev_lock;\n\tstruct mii_bus *mii_bus;\n\tunsigned int using_extphy;\n\tint last_duplex;\n\tint last_carrier;\n\tu32 msg_enable;\n\tunsigned int gpio_setting;\n\tunsigned int gpio_orig_setting;\n\tstruct net_device *dev;\n\tstruct napi_struct napi;\n\tunsigned int software_irq_signal;\n\tchar loopback_tx_pkt[64];\n\tchar loopback_rx_pkt[64];\n\tunsigned int resetcount;\n\tunsigned int multicast_update_pending;\n\tunsigned int set_bits_mask;\n\tunsigned int clear_bits_mask;\n\tunsigned int hashhi;\n\tunsigned int hashlo;\n\tconst struct smsc911x_ops *ops;\n\tstruct regulator_bulk_data supplies[2];\n\tstruct gpio_desc *reset_gpiod;\n\tstruct clk *clk;\n};\n\nstruct smsc911x_ops {\n\tu32 (*reg_read)(struct smsc911x_data *, u32);\n\tvoid (*reg_write)(struct smsc911x_data *, u32, u32);\n\tvoid (*rx_readfifo)(struct smsc911x_data *, unsigned int *, unsigned int);\n\tvoid (*tx_writefifo)(struct smsc911x_data *, unsigned int *, unsigned int);\n};\n\nstruct smsc95xx_priv {\n\tu32 mac_cr;\n\tu32 hash_hi;\n\tu32 hash_lo;\n\tu32 wolopts;\n\tbool pause_rx;\n\tbool pause_tx;\n\tbool pause_autoneg;\n\tspinlock_t mac_cr_lock;\n\tu8 features;\n\tu8 suspend_flags;\n\tbool is_internal_phy;\n\tstruct irq_chip irqchip;\n\tstruct irq_domain *irqdomain;\n\tstruct fwnode_handle *irqfwnode;\n\tstruct mii_bus *mdiobus;\n\tstruct phy_device *phydev;\n\tstruct task_struct *pm_task;\n};\n\nstruct smsc_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct smsc_phy_priv {\n\tunsigned int edpd_enable: 1;\n\tunsigned int edpd_mode_set_by_user: 1;\n\tunsigned int edpd_max_wait_ms;\n\tbool wol_arp;\n};\n\nstruct smsm_entry {\n\tstruct qcom_smsm *smsm;\n\tstruct irq_domain *domain;\n\tlong unsigned int irq_enabled[1];\n\tlong unsigned int irq_rising[1];\n\tlong unsigned int irq_falling[1];\n\tlong unsigned int last_value;\n\tu32 *remote_state;\n\tu32 *subscription;\n};\n\nstruct smsm_host {\n\tstruct regmap *ipc_regmap;\n\tint ipc_offset;\n\tint ipc_bit;\n\tstruct mbox_chan *mbox_chan;\n};\n\nstruct snd_shutdown_f_ops;\n\nstruct snd_info_entry;\n\nstruct snd_card {\n\tint number;\n\tchar id[16];\n\tchar driver[16];\n\tchar shortname[32];\n\tchar longname[80];\n\tchar irq_descr[32];\n\tchar mixername[80];\n\tchar components[128];\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_card *);\n\tstruct list_head devices;\n\tstruct device *ctl_dev;\n\tunsigned int last_numid;\n\tstruct rw_semaphore controls_rwsem;\n\trwlock_t controls_rwlock;\n\tint controls_count;\n\tsize_t user_ctl_alloc_size;\n\tstruct list_head controls;\n\tstruct list_head ctl_files;\n\tstruct xarray ctl_numids;\n\tstruct xarray ctl_hash;\n\tbool ctl_hash_collision;\n\tstruct snd_info_entry *proc_root;\n\tstruct proc_dir_entry *proc_root_link;\n\tstruct list_head files_list;\n\tstruct snd_shutdown_f_ops *s_f_ops;\n\tspinlock_t files_lock;\n\tint shutdown;\n\tstruct completion *release_completion;\n\tstruct device *dev;\n\tlong: 32;\n\tstruct device card_dev;\n\tconst struct attribute_group *dev_groups[4];\n\tbool registered;\n\tbool managed;\n\tbool releasing;\n\tint sync_irq;\n\twait_queue_head_t remove_sleep;\n\tsize_t total_pcm_alloc_bytes;\n\tstruct mutex memory_mutex;\n\tunsigned int power_state;\n\tatomic_t power_ref;\n\twait_queue_head_t power_sleep;\n\twait_queue_head_t power_ref_sleep;\n\tlong: 32;\n};\n\nstruct snd_enc_wma {\n\t__u32 super_block_align;\n};\n\nstruct snd_enc_vorbis {\n\t__s32 quality;\n\t__u32 managed;\n\t__u32 max_bit_rate;\n\t__u32 min_bit_rate;\n\t__u32 downmix;\n};\n\nstruct snd_enc_real {\n\t__u32 quant_bits;\n\t__u32 start_region;\n\t__u32 num_regions;\n};\n\nstruct snd_enc_flac {\n\t__u32 num;\n\t__u32 gain;\n};\n\nstruct snd_enc_generic {\n\t__u32 bw;\n\t__s32 reserved[15];\n};\n\nstruct snd_dec_flac {\n\t__u16 sample_size;\n\t__u16 min_blk_size;\n\t__u16 max_blk_size;\n\t__u16 min_frame_size;\n\t__u16 max_frame_size;\n\t__u16 reserved;\n};\n\nstruct snd_dec_wma {\n\t__u32 encoder_option;\n\t__u32 adv_encoder_option;\n\t__u32 adv_encoder_option2;\n\t__u32 reserved;\n};\n\nstruct snd_dec_alac {\n\t__u32 frame_length;\n\t__u8 compatible_version;\n\t__u8 pb;\n\t__u8 mb;\n\t__u8 kb;\n\t__u32 max_run;\n\t__u32 max_frame_bytes;\n};\n\nstruct snd_dec_ape {\n\t__u16 compatible_version;\n\t__u16 compression_level;\n\t__u32 format_flags;\n\t__u32 blocks_per_frame;\n\t__u32 final_frame_blocks;\n\t__u32 total_frames;\n\t__u32 seek_table_present;\n};\n\nstruct snd_dec_opus_ch_map {\n\t__u8 stream_count;\n\t__u8 coupled_count;\n\t__u8 channel_map[8];\n};\n\nstruct snd_dec_opus {\n\t__u8 version;\n\t__u8 num_channels;\n\t__u16 pre_skip;\n\t__u32 sample_rate;\n\t__u16 output_gain;\n\t__u8 mapping_family;\n\tstruct snd_dec_opus_ch_map chan_map;\n};\n\nunion snd_codec_options {\n\tstruct snd_enc_wma wma;\n\tstruct snd_enc_vorbis vorbis;\n\tstruct snd_enc_real real;\n\tstruct snd_enc_flac flac;\n\tstruct snd_enc_generic generic;\n\tstruct snd_dec_flac flac_d;\n\tstruct snd_dec_wma wma_d;\n\tstruct snd_dec_alac alac_d;\n\tstruct snd_dec_ape ape_d;\n\tstruct snd_dec_opus opus_d;\n\tstruct {\n\t\t__u32 out_sample_rate;\n\t} src_d;\n};\n\nstruct snd_codec {\n\t__u32 id;\n\t__u32 ch_in;\n\t__u32 ch_out;\n\t__u32 sample_rate;\n\t__u32 bit_rate;\n\t__u32 rate_control;\n\t__u32 profile;\n\t__u32 level;\n\t__u32 ch_mode;\n\t__u32 format;\n\t__u32 align;\n\tunion snd_codec_options options;\n\t__u32 pcm_format;\n\t__u32 reserved[2];\n};\n\nstruct snd_codec_desc_src {\n\t__u32 out_sample_rate_min;\n\t__u32 out_sample_rate_max;\n};\n\nstruct snd_codec_desc {\n\t__u32 max_ch;\n\t__u32 sample_rates[32];\n\t__u32 num_sample_rates;\n\t__u32 bit_rate[32];\n\t__u32 num_bitrates;\n\t__u32 rate_control;\n\t__u32 profiles;\n\t__u32 modes;\n\t__u32 formats;\n\t__u32 min_buffer;\n\t__u32 pcm_formats;\n\tunion {\n\t\t__u32 u_space[6];\n\t\tstruct snd_codec_desc_src src;\n\t};\n\t__u32 reserved[8];\n};\n\nstruct snd_compr_ops;\n\nstruct snd_compr {\n\tconst char *name;\n\tstruct device *dev;\n\tstruct snd_compr_ops *ops;\n\tvoid *private_data;\n\tstruct snd_card *card;\n\tunsigned int direction;\n\tstruct mutex lock;\n\tint device;\n\tbool use_pause_in_draining;\n\tchar id[64];\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_info_entry *proc_info_entry;\n};\n\nstruct snd_compr_caps {\n\t__u32 num_codecs;\n\t__u32 direction;\n\t__u32 min_fragment_size;\n\t__u32 max_fragment_size;\n\t__u32 min_fragments;\n\t__u32 max_fragments;\n\t__u32 codecs[32];\n\t__u32 reserved[11];\n};\n\nstruct snd_compr_codec_caps {\n\t__u32 codec;\n\t__u32 num_descriptors;\n\tstruct snd_codec_desc descriptor[32];\n};\n\nstruct snd_compr_metadata {\n\t__u32 key;\n\t__u32 value[8];\n};\n\nstruct snd_compr_stream;\n\nstruct snd_compr_params;\n\nstruct snd_compr_tstamp64;\n\nstruct snd_compr_ops {\n\tint (*open)(struct snd_compr_stream *);\n\tint (*free)(struct snd_compr_stream *);\n\tint (*set_params)(struct snd_compr_stream *, struct snd_compr_params *);\n\tint (*get_params)(struct snd_compr_stream *, struct snd_codec *);\n\tint (*set_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*get_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*trigger)(struct snd_compr_stream *, int);\n\tint (*pointer)(struct snd_compr_stream *, struct snd_compr_tstamp64 *);\n\tint (*copy)(struct snd_compr_stream *, char *, size_t);\n\tint (*mmap)(struct snd_compr_stream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_compr_stream *, size_t);\n\tint (*get_caps)(struct snd_compr_stream *, struct snd_compr_caps *);\n\tint (*get_codec_caps)(struct snd_compr_stream *, struct snd_compr_codec_caps *);\n};\n\nstruct snd_compressed_buffer {\n\t__u32 fragment_size;\n\t__u32 fragments;\n};\n\nstruct snd_compr_params {\n\tstruct snd_compressed_buffer buffer;\n\tstruct snd_codec codec;\n\t__u8 no_wake_mode;\n};\n\nstruct snd_dma_buffer;\n\nstruct snd_compr_runtime {\n\tsnd_pcm_state_t state;\n\tstruct snd_compr_ops *ops;\n\tvoid *buffer;\n\tlong: 32;\n\tu64 buffer_size;\n\tu32 fragment_size;\n\tu32 fragments;\n\tu64 total_bytes_available;\n\tu64 total_bytes_transferred;\n\twait_queue_head_t sleep;\n\tvoid *private_data;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n};\n\nstruct snd_dma_device {\n\tint type;\n\tenum dma_data_direction dir;\n\tbool need_sync;\n\tstruct device *dev;\n};\n\nstruct snd_dma_buffer {\n\tstruct snd_dma_device dev;\n\tunsigned char *area;\n\tdma_addr_t addr;\n\tsize_t bytes;\n\tvoid *private_data;\n};\n\nstruct snd_compr_stream {\n\tconst char *name;\n\tstruct snd_compr_ops *ops;\n\tstruct snd_compr_runtime *runtime;\n\tstruct snd_compr *device;\n\tstruct delayed_work error_work;\n\tenum snd_compr_direction direction;\n\tbool metadata_set;\n\tbool next_track;\n\tbool partial_drain;\n\tbool pause_in_draining;\n\tvoid *private_data;\n\tstruct snd_dma_buffer dma_buffer;\n};\n\nstruct snd_compr_tstamp64 {\n\t__u32 byte_offset;\n\t__u64 copied_total;\n\t__u64 pcm_frames;\n\t__u64 pcm_io_frames;\n\t__u32 sampling_rate;\n};\n\nstruct snd_compress_ops {\n\tint (*open)(struct snd_soc_component *, struct snd_compr_stream *);\n\tint (*free)(struct snd_soc_component *, struct snd_compr_stream *);\n\tint (*set_params)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_params *);\n\tint (*get_params)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_codec *);\n\tint (*set_metadata)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*get_metadata)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*trigger)(struct snd_soc_component *, struct snd_compr_stream *, int);\n\tint (*pointer)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_tstamp64 *);\n\tint (*copy)(struct snd_soc_component *, struct snd_compr_stream *, char *, size_t);\n\tint (*mmap)(struct snd_soc_component *, struct snd_compr_stream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_soc_component *, struct snd_compr_stream *, size_t);\n\tint (*get_caps)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_caps *);\n\tint (*get_codec_caps)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_codec_caps *);\n};\n\nstruct snd_ctl_elem_id {\n\tunsigned int numid;\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tunsigned char name[44];\n\tunsigned int index;\n};\n\nstruct snd_ctl_elem_info {\n\tstruct snd_ctl_elem_id id;\n\tsnd_ctl_elem_type_t type;\n\tunsigned int access;\n\tunsigned int count;\n\t__kernel_pid_t owner;\n\tunion {\n\t\tstruct {\n\t\t\tlong int min;\n\t\t\tlong int max;\n\t\t\tlong int step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tlong long int min;\n\t\t\tlong long int max;\n\t\t\tlong long int step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tunsigned int items;\n\t\t\tunsigned int item;\n\t\t\tchar name[64];\n\t\t\t__u64 names_ptr;\n\t\t\tunsigned int names_length;\n\t\t\tlong: 32;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_value {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect: 1;\n\tlong: 32;\n\tunion {\n\t\tunion {\n\t\t\tlong int value[128];\n\t\t\tlong int *value_ptr;\n\t\t} integer;\n\t\tunion {\n\t\t\tlong long int value[64];\n\t\t\tlong long int *value_ptr;\n\t\t} integer64;\n\t\tunion {\n\t\t\tunsigned int item[128];\n\t\t\tunsigned int *item_ptr;\n\t\t} enumerated;\n\t\tunion {\n\t\t\tunsigned char data[512];\n\t\t\tunsigned char *data_ptr;\n\t\t} bytes;\n\t\tstruct snd_aes_iec958 iec958;\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_fasync;\n\nstruct snd_ctl_file {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tstruct pid *pid;\n\tint preferred_subdevice[2];\n\twait_queue_head_t change_sleep;\n\tspinlock_t read_lock;\n\tstruct snd_fasync *fasync;\n\tint subscribed;\n\tstruct list_head events;\n};\n\nstruct snd_info_buffer {\n\tchar *buffer;\n\tunsigned int curr;\n\tunsigned int size;\n\tunsigned int len;\n\tint stop;\n\tint error;\n};\n\nstruct snd_info_entry_text {\n\tvoid (*read)(struct snd_info_entry *, struct snd_info_buffer *);\n\tvoid (*write)(struct snd_info_entry *, struct snd_info_buffer *);\n};\n\nstruct snd_info_entry_ops;\n\nstruct snd_info_entry {\n\tconst char *name;\n\tumode_t mode;\n\tlong int size;\n\tshort unsigned int content;\n\tunion {\n\t\tstruct snd_info_entry_text text;\n\t\tconst struct snd_info_entry_ops *ops;\n\t} c;\n\tstruct snd_info_entry *parent;\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_info_entry *);\n\tstruct proc_dir_entry *p;\n\tstruct mutex access;\n\tstruct list_head children;\n\tstruct list_head list;\n};\n\nstruct snd_info_entry_ops {\n\tint (*open)(struct snd_info_entry *, short unsigned int, void **);\n\tint (*release)(struct snd_info_entry *, short unsigned int, void *);\n\tssize_t (*read)(struct snd_info_entry *, void *, struct file *, char *, size_t, loff_t);\n\tssize_t (*write)(struct snd_info_entry *, void *, struct file *, const char *, size_t, loff_t);\n\tloff_t (*llseek)(struct snd_info_entry *, void *, struct file *, loff_t, int);\n\t__poll_t (*poll)(struct snd_info_entry *, void *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_info_entry *, void *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_info_entry *, void *, struct inode *, struct file *, struct vm_area_struct *);\n};\n\nstruct snd_interval {\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int openmin: 1;\n\tunsigned int openmax: 1;\n\tunsigned int integer: 1;\n\tunsigned int empty: 1;\n};\n\nstruct snd_kcontrol;\n\ntypedef int snd_kcontrol_info_t(struct snd_kcontrol *, struct snd_ctl_elem_info *);\n\ntypedef int snd_kcontrol_get_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_put_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_tlv_rw_t(struct snd_kcontrol *, int, unsigned int, unsigned int *);\n\nstruct snd_kcontrol_volatile {\n\tstruct snd_ctl_file *owner;\n\tunsigned int access;\n};\n\nstruct snd_kcontrol {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_kcontrol *);\n\tstruct snd_kcontrol_volatile vd[0];\n};\n\nstruct snd_kcontrol_new {\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tconst char *name;\n\tunsigned int index;\n\tunsigned int access;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n};\n\nstruct snd_mask {\n\t__u32 bits[8];\n};\n\nstruct snd_pcm;\n\nstruct snd_pcm_substream;\n\nstruct snd_pcm_str {\n\tint stream;\n\tstruct snd_pcm *pcm;\n\tunsigned int substream_count;\n\tunsigned int substream_opened;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_kcontrol *chmap_kctl;\n\tstruct device *dev;\n};\n\nstruct snd_pcm {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tunsigned int info_flags;\n\tshort unsigned int dev_class;\n\tshort unsigned int dev_subclass;\n\tchar id[64];\n\tchar name[80];\n\tstruct snd_pcm_str streams[2];\n\tstruct mutex open_mutex;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm *);\n\tbool internal;\n\tbool nonatomic;\n\tbool no_device_suspend;\n};\n\nstruct snd_pcm_audio_tstamp_config {\n\tu32 type_requested: 4;\n\tu32 report_delay: 1;\n};\n\nstruct snd_pcm_audio_tstamp_report {\n\tu32 valid: 1;\n\tu32 actual_type: 4;\n\tu32 accuracy_report: 1;\n\tu32 accuracy;\n};\n\nstruct snd_pcm_group {\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head substreams;\n\trefcount_t refs;\n};\n\nstruct snd_pcm_hardware {\n\tunsigned int info;\n\tlong: 32;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int rates;\n\tunsigned int rate_min;\n\tunsigned int rate_max;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\tsize_t buffer_bytes_max;\n\tsize_t period_bytes_min;\n\tsize_t period_bytes_max;\n\tunsigned int periods_min;\n\tunsigned int periods_max;\n\tsize_t fifo_size;\n};\n\nstruct snd_pcm_hw_rule;\n\nstruct snd_pcm_hw_constraints {\n\tstruct snd_mask masks[3];\n\tstruct snd_interval intervals[12];\n\tunsigned int rules_num;\n\tunsigned int rules_all;\n\tstruct snd_pcm_hw_rule *rules;\n};\n\nstruct snd_pcm_hw_params {\n\tunsigned int flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tunsigned int rmask;\n\tunsigned int cmask;\n\tunsigned int info;\n\tunsigned int msbits;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tsnd_pcm_uframes_t fifo_size;\n\tunsigned char sync[16];\n\tunsigned char reserved[48];\n};\n\ntypedef int (*snd_pcm_hw_rule_func_t)(struct snd_pcm_hw_params *, struct snd_pcm_hw_rule *);\n\nstruct snd_pcm_hw_rule {\n\tunsigned int cond;\n\tint var;\n\tint deps[5];\n\tsnd_pcm_hw_rule_func_t func;\n\tvoid *private;\n};\n\nstruct snd_pcm_mmap_control {\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t appl_ptr;\n\t__pad_before_uframe __pad2;\n\t__pad_before_uframe __pad3;\n\tsnd_pcm_uframes_t avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct snd_pcm_mmap_status {\n\tsnd_pcm_state_t state;\n\t__u32 pad1;\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t hw_ptr;\n\t__pad_after_uframe __pad2;\n\tstruct __kernel_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 pad3;\n\tstruct __kernel_timespec audio_tstamp;\n};\n\nstruct snd_pcm_ops {\n\tint (*open)(struct snd_pcm_substream *);\n\tint (*close)(struct snd_pcm_substream *);\n\tint (*ioctl)(struct snd_pcm_substream *, unsigned int, void *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_pcm_substream *, int);\n\tint (*sync_stop)(struct snd_pcm_substream *);\n\tsnd_pcm_uframes_t (*pointer)(struct snd_pcm_substream *);\n\tint (*get_time_info)(struct snd_pcm_substream *, struct timespec64 *, struct timespec64 *, struct snd_pcm_audio_tstamp_config *, struct snd_pcm_audio_tstamp_report *);\n\tint (*fill_silence)(struct snd_pcm_substream *, int, long unsigned int, long unsigned int);\n\tint (*copy)(struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\tstruct page * (*page)(struct snd_pcm_substream *, long unsigned int);\n\tint (*mmap)(struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_pcm_substream *);\n};\n\nstruct snd_pcm_runtime {\n\tsnd_pcm_state_t state;\n\tsnd_pcm_state_t suspended_state;\n\tstruct snd_pcm_substream *trigger_master;\n\tlong: 32;\n\tstruct timespec64 trigger_tstamp;\n\tbool trigger_tstamp_latched;\n\tint overrange;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t hw_ptr_base;\n\tsnd_pcm_uframes_t hw_ptr_interrupt;\n\tlong unsigned int hw_ptr_jiffies;\n\tlong unsigned int hw_ptr_buffer_jiffies;\n\tsnd_pcm_sframes_t delay;\n\tu64 hw_ptr_wrap;\n\tsnd_pcm_access_t access;\n\tsnd_pcm_format_t format;\n\tsnd_pcm_subformat_t subformat;\n\tunsigned int rate;\n\tunsigned int channels;\n\tsnd_pcm_uframes_t period_size;\n\tunsigned int periods;\n\tsnd_pcm_uframes_t buffer_size;\n\tsnd_pcm_uframes_t min_align;\n\tsize_t byte_align;\n\tunsigned int frame_bits;\n\tunsigned int sample_bits;\n\tunsigned int info;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tunsigned int no_period_wakeup: 1;\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tsnd_pcm_uframes_t silence_start;\n\tsnd_pcm_uframes_t silence_filled;\n\tbool std_sync_id;\n\tstruct snd_pcm_mmap_status *status;\n\tstruct snd_pcm_mmap_control *control;\n\tsnd_pcm_uframes_t twake;\n\twait_queue_head_t sleep;\n\twait_queue_head_t tsleep;\n\tstruct snd_fasync *fasync;\n\tbool stop_operating;\n\tstruct mutex buffer_mutex;\n\tatomic_t buffer_accessing;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm_runtime *);\n\tlong: 32;\n\tstruct snd_pcm_hardware hw;\n\tstruct snd_pcm_hw_constraints hw_constraints;\n\tunsigned int timer_resolution;\n\tint tstamp_type;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n\tunsigned int buffer_changed: 1;\n\tstruct snd_pcm_audio_tstamp_config audio_tstamp_config;\n\tstruct snd_pcm_audio_tstamp_report audio_tstamp_report;\n\tlong: 32;\n\tstruct timespec64 driver_tstamp;\n};\n\nstruct snd_timer;\n\nstruct snd_pcm_substream {\n\tstruct snd_pcm *pcm;\n\tstruct snd_pcm_str *pstr;\n\tvoid *private_data;\n\tint number;\n\tchar name[32];\n\tint stream;\n\tstruct pm_qos_request latency_pm_qos_req;\n\tsize_t buffer_bytes_max;\n\tstruct snd_dma_buffer dma_buffer;\n\tsize_t dma_max;\n\tconst struct snd_pcm_ops *ops;\n\tstruct snd_pcm_runtime *runtime;\n\tstruct snd_timer *timer;\n\tunsigned int timer_running: 1;\n\tlong int wait_time;\n\tstruct snd_pcm_substream *next;\n\tstruct list_head link_list;\n\tstruct snd_pcm_group self_group;\n\tstruct snd_pcm_group *group;\n\tint ref_count;\n\tatomic_t mmap_count;\n\tunsigned int f_flags;\n\tvoid (*pcm_release)(struct snd_pcm_substream *);\n\tstruct pid *pid;\n\tstruct snd_info_entry *proc_root;\n\tunsigned int hw_opened: 1;\n\tunsigned int managed_buffer_alloc: 1;\n};\n\nstruct snd_soc_dai_link_component {\n\tconst char *name;\n\tstruct device_node *of_node;\n\tconst char *dai_name;\n\tconst struct of_phandle_args *dai_args;\n\tunsigned int ext_fmt;\n};\n\nstruct snd_soc_aux_dev {\n\tstruct snd_soc_dai_link_component dlc;\n\tint (*init)(struct snd_soc_component *);\n};\n\nstruct snd_soc_dapm_context;\n\nstruct snd_soc_dapm_stats {\n\tint power_checks;\n\tint path_checks;\n\tint neighbour_checks;\n};\n\nstruct snd_soc_dai_link;\n\nstruct snd_soc_codec_conf;\n\nstruct snd_soc_dapm_widget;\n\nstruct snd_soc_dapm_route;\n\nstruct snd_soc_card {\n\tconst char *name;\n\tconst char *long_name;\n\tconst char *driver_name;\n\tconst char *components;\n\tchar dmi_longname[80];\n\tshort unsigned int pci_subsystem_vendor;\n\tshort unsigned int pci_subsystem_device;\n\tbool pci_subsystem_set;\n\tchar topology_shortname[32];\n\tstruct device *dev;\n\tstruct snd_card *snd_card;\n\tstruct module *owner;\n\tstruct mutex mutex;\n\tstruct mutex dapm_mutex;\n\tstruct mutex pcm_mutex;\n\tenum snd_soc_pcm_subclass pcm_subclass;\n\tint (*probe)(struct snd_soc_card *);\n\tint (*late_probe)(struct snd_soc_card *);\n\tvoid (*fixup_controls)(struct snd_soc_card *);\n\tint (*remove)(struct snd_soc_card *);\n\tint (*suspend_pre)(struct snd_soc_card *);\n\tint (*suspend_post)(struct snd_soc_card *);\n\tint (*resume_pre)(struct snd_soc_card *);\n\tint (*resume_post)(struct snd_soc_card *);\n\tint (*set_bias_level)(struct snd_soc_card *, struct snd_soc_dapm_context *, enum snd_soc_bias_level);\n\tint (*set_bias_level_post)(struct snd_soc_card *, struct snd_soc_dapm_context *, enum snd_soc_bias_level);\n\tint (*add_dai_link)(struct snd_soc_card *, struct snd_soc_dai_link *);\n\tvoid (*remove_dai_link)(struct snd_soc_card *, struct snd_soc_dai_link *);\n\tlong int pmdown_time;\n\tstruct snd_soc_dai_link *dai_link;\n\tint num_links;\n\tstruct list_head rtd_list;\n\tint num_rtd;\n\tstruct snd_soc_codec_conf *codec_conf;\n\tint num_configs;\n\tstruct snd_soc_aux_dev *aux_dev;\n\tint num_aux_devs;\n\tstruct list_head aux_comp_list;\n\tconst struct snd_kcontrol_new *controls;\n\tint num_controls;\n\tconst struct snd_soc_dapm_widget *dapm_widgets;\n\tint num_dapm_widgets;\n\tconst struct snd_soc_dapm_route *dapm_routes;\n\tint num_dapm_routes;\n\tconst struct snd_soc_dapm_widget *of_dapm_widgets;\n\tint num_of_dapm_widgets;\n\tconst struct snd_soc_dapm_route *of_dapm_routes;\n\tint num_of_dapm_routes;\n\tstruct list_head component_dev_list;\n\tstruct list_head list;\n\tstruct list_head widgets;\n\tstruct list_head paths;\n\tstruct list_head dapm_list;\n\tstruct list_head dapm_dirty;\n\tstruct list_head dobj_list;\n\tstruct snd_soc_dapm_context *dapm;\n\tstruct snd_soc_dapm_stats dapm_stats;\n\tstruct dentry *debugfs_card_root;\n\tstruct work_struct deferred_resume_work;\n\tu32 pop_time;\n\tunsigned int instantiated: 1;\n\tunsigned int topology_shortname_created: 1;\n\tunsigned int fully_routed: 1;\n\tunsigned int probed: 1;\n\tunsigned int component_chaining: 1;\n\tstruct device *devres_dev;\n\tvoid *drvdata;\n};\n\nstruct snd_soc_dai;\n\nstruct snd_soc_cdai_ops {\n\tint (*startup)(struct snd_compr_stream *, struct snd_soc_dai *);\n\tint (*shutdown)(struct snd_compr_stream *, struct snd_soc_dai *);\n\tint (*set_params)(struct snd_compr_stream *, struct snd_compr_params *, struct snd_soc_dai *);\n\tint (*get_params)(struct snd_compr_stream *, struct snd_codec *, struct snd_soc_dai *);\n\tint (*set_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *, struct snd_soc_dai *);\n\tint (*get_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *, struct snd_soc_dai *);\n\tint (*trigger)(struct snd_compr_stream *, int, struct snd_soc_dai *);\n\tint (*pointer)(struct snd_compr_stream *, struct snd_compr_tstamp64 *, struct snd_soc_dai *);\n\tint (*ack)(struct snd_compr_stream *, size_t, struct snd_soc_dai *);\n};\n\nstruct snd_soc_codec_conf {\n\tstruct snd_soc_dai_link_component dlc;\n\tconst char *name_prefix;\n};\n\nstruct snd_soc_component_driver;\n\nstruct snd_soc_component {\n\tconst char *name;\n\tconst char *name_prefix;\n\tstruct device *dev;\n\tstruct snd_soc_card *card;\n\tunsigned int active;\n\tunsigned int suspended: 1;\n\tstruct list_head list;\n\tstruct list_head card_aux_list;\n\tstruct list_head card_list;\n\tconst struct snd_soc_component_driver *driver;\n\tstruct list_head dai_list;\n\tint num_dai;\n\tstruct regmap *regmap;\n\tint val_bytes;\n\tstruct mutex io_mutex;\n\tstruct list_head dobj_list;\n\tstruct snd_soc_dapm_context *dapm;\n\tint (*init)(struct snd_soc_component *);\n\tvoid *mark_module;\n\tstruct snd_pcm_substream *mark_open;\n\tstruct snd_pcm_substream *mark_hw_params;\n\tstruct snd_pcm_substream *mark_trigger;\n\tstruct snd_compr_stream *mark_compr_open;\n\tvoid *mark_pm;\n\tstruct dentry *debugfs_root;\n\tconst char *debugfs_prefix;\n};\n\nstruct snd_soc_pcm_runtime;\n\nstruct snd_soc_jack;\n\nstruct snd_soc_component_driver {\n\tconst char *name;\n\tconst struct snd_kcontrol_new *controls;\n\tunsigned int num_controls;\n\tconst struct snd_soc_dapm_widget *dapm_widgets;\n\tunsigned int num_dapm_widgets;\n\tconst struct snd_soc_dapm_route *dapm_routes;\n\tunsigned int num_dapm_routes;\n\tint (*probe)(struct snd_soc_component *);\n\tvoid (*remove)(struct snd_soc_component *);\n\tint (*suspend)(struct snd_soc_component *);\n\tint (*resume)(struct snd_soc_component *);\n\tunsigned int (*read)(struct snd_soc_component *, unsigned int);\n\tint (*write)(struct snd_soc_component *, unsigned int, unsigned int);\n\tint (*pcm_construct)(struct snd_soc_component *, struct snd_soc_pcm_runtime *);\n\tvoid (*pcm_destruct)(struct snd_soc_component *, struct snd_pcm *);\n\tint (*set_sysclk)(struct snd_soc_component *, int, int, unsigned int, int);\n\tint (*set_pll)(struct snd_soc_component *, int, int, unsigned int, unsigned int);\n\tint (*set_jack)(struct snd_soc_component *, struct snd_soc_jack *, void *);\n\tint (*get_jack_type)(struct snd_soc_component *);\n\tint (*of_xlate_dai_name)(struct snd_soc_component *, const struct of_phandle_args *, const char **);\n\tint (*of_xlate_dai_id)(struct snd_soc_component *, struct device_node *);\n\tvoid (*seq_notifier)(struct snd_soc_component *, enum snd_soc_dapm_type, int);\n\tint (*stream_event)(struct snd_soc_component *, int);\n\tint (*set_bias_level)(struct snd_soc_component *, enum snd_soc_bias_level);\n\tint (*open)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*close)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*ioctl)(struct snd_soc_component *, struct snd_pcm_substream *, unsigned int, void *);\n\tint (*hw_params)(struct snd_soc_component *, struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_soc_component *, struct snd_pcm_substream *, int);\n\tint (*sync_stop)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tsnd_pcm_uframes_t (*pointer)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*get_time_info)(struct snd_soc_component *, struct snd_pcm_substream *, struct timespec64 *, struct timespec64 *, struct snd_pcm_audio_tstamp_config *, struct snd_pcm_audio_tstamp_report *);\n\tint (*copy)(struct snd_soc_component *, struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\tstruct page * (*page)(struct snd_soc_component *, struct snd_pcm_substream *, long unsigned int);\n\tint (*mmap)(struct snd_soc_component *, struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tsnd_pcm_sframes_t (*delay)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tconst struct snd_compress_ops *compress_ops;\n\tint probe_order;\n\tint remove_order;\n\tenum snd_soc_trigger_order trigger_start;\n\tenum snd_soc_trigger_order trigger_stop;\n\tunsigned int module_get_upon_open: 1;\n\tunsigned int idle_bias_on: 1;\n\tunsigned int suspend_bias_off: 1;\n\tunsigned int use_pmdown_time: 1;\n\tunsigned int endianness: 1;\n\tunsigned int legacy_dai_naming: 1;\n\tconst char *ignore_machine;\n\tconst char *topology_name_prefix;\n\tint (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *, struct snd_pcm_hw_params *);\n\tbool use_dai_pcm_id;\n\tint be_pcm_base;\n\tconst char *debugfs_prefix;\n};\n\nstruct snd_soc_compr_ops {\n\tint (*startup)(struct snd_compr_stream *);\n\tvoid (*shutdown)(struct snd_compr_stream *);\n\tint (*set_params)(struct snd_compr_stream *);\n};\n\nstruct snd_soc_dai_stream {\n\tstruct snd_soc_dapm_widget *widget;\n\tunsigned int active;\n\tunsigned int tdm_mask;\n\tvoid *dma_data;\n};\n\nstruct snd_soc_dai_driver;\n\nstruct snd_soc_dai {\n\tconst char *name;\n\tint id;\n\tstruct device *dev;\n\tstruct snd_soc_dai_driver *driver;\n\tstruct snd_soc_dai_stream stream[2];\n\tunsigned int symmetric_rate;\n\tunsigned int symmetric_channels;\n\tunsigned int symmetric_sample_bits;\n\tstruct snd_soc_component *component;\n\tstruct list_head list;\n\tstruct snd_pcm_substream *mark_startup;\n\tstruct snd_pcm_substream *mark_hw_params;\n\tstruct snd_pcm_substream *mark_trigger;\n\tstruct snd_compr_stream *mark_compr_startup;\n\tunsigned int probed: 1;\n\tvoid *priv;\n};\n\nstruct snd_soc_dobj_control {\n\tstruct snd_kcontrol *kcontrol;\n\tchar **dtexts;\n\tlong unsigned int *dvalues;\n};\n\nstruct snd_soc_dobj_widget {\n\tunsigned int *kcontrol_type;\n};\n\nstruct snd_soc_dobj {\n\tenum snd_soc_dobj_type type;\n\tunsigned int index;\n\tstruct list_head list;\n\tint (*unload)(struct snd_soc_component *, struct snd_soc_dobj *);\n\tunion {\n\t\tstruct snd_soc_dobj_control control;\n\t\tstruct snd_soc_dobj_widget widget;\n\t};\n\tvoid *private;\n};\n\nstruct snd_soc_pcm_stream {\n\tconst char *stream_name;\n\tlong: 32;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int rates;\n\tunsigned int rate_min;\n\tunsigned int rate_max;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\tunsigned int sig_bits;\n\tlong: 32;\n};\n\nstruct snd_soc_dai_ops;\n\nstruct snd_soc_dai_driver {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int base;\n\tstruct snd_soc_dobj dobj;\n\tconst struct of_phandle_args *dai_args;\n\tconst struct snd_soc_dai_ops *ops;\n\tconst struct snd_soc_cdai_ops *cops;\n\tlong: 32;\n\tstruct snd_soc_pcm_stream capture;\n\tstruct snd_soc_pcm_stream playback;\n\tunsigned int symmetric_rate: 1;\n\tunsigned int symmetric_channels: 1;\n\tunsigned int symmetric_sample_bits: 1;\n\tlong: 32;\n};\n\nstruct snd_soc_dai_link_ch_map;\n\nstruct snd_soc_ops;\n\nstruct snd_soc_dai_link {\n\tconst char *name;\n\tconst char *stream_name;\n\tstruct snd_soc_dai_link_component *cpus;\n\tunsigned int num_cpus;\n\tstruct snd_soc_dai_link_component *codecs;\n\tunsigned int num_codecs;\n\tstruct snd_soc_dai_link_ch_map *ch_maps;\n\tstruct snd_soc_dai_link_component *platforms;\n\tunsigned int num_platforms;\n\tint id;\n\tconst struct snd_soc_pcm_stream *c2c_params;\n\tunsigned int num_c2c_params;\n\tunsigned int dai_fmt;\n\tenum snd_soc_dpcm_trigger trigger[2];\n\tint (*init)(struct snd_soc_pcm_runtime *);\n\tvoid (*exit)(struct snd_soc_pcm_runtime *);\n\tint (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *, struct snd_pcm_hw_params *);\n\tconst struct snd_soc_ops *ops;\n\tconst struct snd_soc_compr_ops *compr_ops;\n\tenum snd_soc_trigger_order trigger_start;\n\tenum snd_soc_trigger_order trigger_stop;\n\tunsigned int nonatomic: 1;\n\tunsigned int playback_only: 1;\n\tunsigned int capture_only: 1;\n\tunsigned int ignore_suspend: 1;\n\tunsigned int symmetric_rate: 1;\n\tunsigned int symmetric_channels: 1;\n\tunsigned int symmetric_sample_bits: 1;\n\tunsigned int no_pcm: 1;\n\tunsigned int dynamic: 1;\n\tunsigned int dpcm_merged_format: 1;\n\tunsigned int dpcm_merged_chan: 1;\n\tunsigned int dpcm_merged_rate: 1;\n\tunsigned int ignore_pmdown_time: 1;\n\tunsigned int ignore: 1;\n};\n\nstruct snd_soc_dai_link_ch_map {\n\tunsigned int cpu;\n\tunsigned int codec;\n\tunsigned int ch_mask;\n};\n\nstruct snd_soc_dai_ops {\n\tint (*probe)(struct snd_soc_dai *);\n\tint (*remove)(struct snd_soc_dai *);\n\tint (*compress_new)(struct snd_soc_pcm_runtime *);\n\tint (*pcm_new)(struct snd_soc_pcm_runtime *, struct snd_soc_dai *);\n\tint (*set_sysclk)(struct snd_soc_dai *, int, unsigned int, int);\n\tint (*set_pll)(struct snd_soc_dai *, int, int, unsigned int, unsigned int);\n\tint (*set_clkdiv)(struct snd_soc_dai *, int, int);\n\tint (*set_bclk_ratio)(struct snd_soc_dai *, unsigned int);\n\tint (*set_fmt)(struct snd_soc_dai *, unsigned int);\n\tint (*xlate_tdm_slot_mask)(unsigned int, unsigned int *, unsigned int *);\n\tint (*set_tdm_slot)(struct snd_soc_dai *, unsigned int, unsigned int, int, int);\n\tint (*set_channel_map)(struct snd_soc_dai *, unsigned int, const unsigned int *, unsigned int, const unsigned int *);\n\tint (*get_channel_map)(const struct snd_soc_dai *, unsigned int *, unsigned int *, unsigned int *, unsigned int *);\n\tint (*set_tristate)(struct snd_soc_dai *, int);\n\tint (*set_stream)(struct snd_soc_dai *, void *, int);\n\tvoid * (*get_stream)(struct snd_soc_dai *, int);\n\tint (*mute_stream)(struct snd_soc_dai *, int, int);\n\tint (*startup)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tvoid (*shutdown)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *, struct snd_soc_dai *);\n\tint (*hw_free)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tint (*prepare)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tint (*trigger)(struct snd_pcm_substream *, int, struct snd_soc_dai *);\n\tsnd_pcm_sframes_t (*delay)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tconst u64 *auto_selectable_formats;\n\tint num_auto_selectable_formats;\n\tint probe_order;\n\tint remove_order;\n\tunsigned int no_capture_mute: 1;\n\tunsigned int mute_unmute_on_trigger: 1;\n};\n\nstruct snd_soc_dapm_route {\n\tconst char *sink;\n\tconst char *control;\n\tconst char *source;\n\tint (*connected)(struct snd_soc_dapm_widget *, struct snd_soc_dapm_widget *);\n\tstruct snd_soc_dobj dobj;\n};\n\nstruct snd_soc_dapm_widget {\n\tenum snd_soc_dapm_type id;\n\tconst char *name;\n\tconst char *sname;\n\tstruct list_head list;\n\tstruct snd_soc_dapm_context *dapm;\n\tvoid *priv;\n\tstruct regulator *regulator;\n\tstruct pinctrl *pinctrl;\n\tint reg;\n\tunsigned char shift;\n\tunsigned int mask;\n\tunsigned int on_val;\n\tunsigned int off_val;\n\tunsigned char power: 1;\n\tunsigned char active: 1;\n\tunsigned char connected: 1;\n\tunsigned char new: 1;\n\tunsigned char force: 1;\n\tunsigned char ignore_suspend: 1;\n\tunsigned char new_power: 1;\n\tunsigned char power_checked: 1;\n\tunsigned char is_supply: 1;\n\tunsigned char is_ep: 2;\n\tunsigned char no_wname_in_kcontrol_name: 1;\n\tint subseq;\n\tint (*power_check)(struct snd_soc_dapm_widget *);\n\tshort unsigned int event_flags;\n\tint (*event)(struct snd_soc_dapm_widget *, struct snd_kcontrol *, int);\n\tint num_kcontrols;\n\tconst struct snd_kcontrol_new *kcontrol_news;\n\tstruct snd_kcontrol **kcontrols;\n\tstruct snd_soc_dobj dobj;\n\tstruct list_head edges[2];\n\tstruct list_head work_list;\n\tstruct list_head power_list;\n\tstruct list_head dirty;\n\tint endpoints[2];\n\tstruct clk *clk;\n\tint channel;\n};\n\nstruct snd_soc_dpcm_runtime {\n\tstruct list_head be_clients;\n\tstruct list_head fe_clients;\n\tint users;\n\tstruct snd_pcm_hw_params hw_params;\n\tenum snd_soc_dpcm_update runtime_update;\n\tenum snd_soc_dpcm_state state;\n\tint trigger_pending;\n\tint be_start;\n\tint be_pause;\n\tbool fe_pause;\n};\n\nstruct snd_jack;\n\nstruct snd_soc_jack {\n\tstruct mutex mutex;\n\tstruct snd_jack *jack;\n\tstruct snd_soc_card *card;\n\tstruct list_head pins;\n\tint status;\n\tstruct blocking_notifier_head notifier;\n\tstruct list_head jack_zones;\n};\n\nstruct snd_soc_ops {\n\tint (*startup)(struct snd_pcm_substream *);\n\tvoid (*shutdown)(struct snd_pcm_substream *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_pcm_substream *, int);\n};\n\nstruct snd_soc_pcm_runtime {\n\tstruct device *dev;\n\tstruct snd_soc_card *card;\n\tstruct snd_soc_dai_link *dai_link;\n\tstruct snd_pcm_ops ops;\n\tunsigned int c2c_params_select;\n\tstruct snd_soc_dpcm_runtime dpcm[2];\n\tstruct snd_soc_dapm_widget *c2c_widget[2];\n\tlong int pmdown_time;\n\tstruct snd_pcm *pcm;\n\tstruct snd_compr *compr;\n\tstruct snd_soc_dai **dais;\n\tstruct delayed_work delayed_work;\n\tvoid (*close_delayed_work_func)(struct snd_soc_pcm_runtime *);\n\tstruct dentry *debugfs_dpcm_root;\n\tunsigned int id;\n\tstruct list_head list;\n\tstruct snd_pcm_substream *mark_startup;\n\tstruct snd_pcm_substream *mark_hw_params;\n\tstruct snd_pcm_substream *mark_trigger;\n\tstruct snd_compr_stream *mark_compr_startup;\n\tunsigned int pop_wait: 1;\n\tunsigned int fe_compr: 1;\n\tunsigned int initialized: 1;\n\tint num_components;\n\tstruct snd_soc_component *components[0];\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct soc_device_attribute;\n\nstruct soc_device {\n\tstruct device dev;\n\tstruct soc_device_attribute *attr;\n\tint soc_dev_num;\n};\n\nstruct soc_device_attribute {\n\tconst char *machine;\n\tconst char *family;\n\tconst char *revision;\n\tconst char *serial_number;\n\tconst char *soc_id;\n\tconst void *data;\n\tconst struct attribute_group *custom_attr_group;\n};\n\nstruct socfpga_dwmac_ops;\n\nstruct socfpga_dwmac {\n\tu32 reg_offset;\n\tu32 reg_shift;\n\tstruct device *dev;\n\tstruct plat_stmmacenet_data *plat_dat;\n\tstruct regmap *sys_mgr_base_addr;\n\tstruct reset_control *stmmac_rst;\n\tstruct reset_control *stmmac_ocp_rst;\n\tvoid *splitter_base;\n\tvoid *tse_pcs_base;\n\tvoid *sgmii_adapter_base;\n\tbool f2h_ptp_ref_clk;\n\tconst struct socfpga_dwmac_ops *ops;\n};\n\nstruct socfpga_dwmac_ops {\n\tint (*set_phy_mode)(struct socfpga_dwmac *);\n\tvoid (*setup_plat_dat)(struct socfpga_dwmac *);\n};\n\nstruct socfpga_gate_clk {\n\tstruct clk_gate hw;\n\tchar *parent_name;\n\tu32 fixed_div;\n\tvoid *div_reg;\n\tvoid *bypass_reg;\n\tstruct regmap *sys_mgr_base_addr;\n\tu32 width;\n\tu32 shift;\n\tu32 bypass_shift;\n};\n\nstruct socfpga_periph_clk {\n\tstruct clk_gate hw;\n\tchar *parent_name;\n\tu32 fixed_div;\n\tvoid *div_reg;\n\tvoid *bypass_reg;\n\tu32 width;\n\tu32 shift;\n\tu32 bypass_shift;\n};\n\nstruct socfpga_pll {\n\tstruct clk_gate hw;\n};\n\nstruct socinfo {\n\t__le32 fmt;\n\t__le32 id;\n\t__le32 ver;\n\tchar build_id[32];\n\t__le32 raw_id;\n\t__le32 raw_ver;\n\t__le32 hw_plat;\n\t__le32 plat_ver;\n\t__le32 accessory_chip;\n\t__le32 hw_plat_subtype;\n\t__le32 pmic_model;\n\t__le32 pmic_die_rev;\n\t__le32 pmic_model_1;\n\t__le32 pmic_die_rev_1;\n\t__le32 pmic_model_2;\n\t__le32 pmic_die_rev_2;\n\t__le32 foundry_id;\n\t__le32 serial_num;\n\t__le32 num_pmics;\n\t__le32 pmic_array_offset;\n\t__le32 chip_family;\n\t__le32 raw_device_family;\n\t__le32 raw_device_num;\n\t__le32 nproduct_id;\n\tchar chip_id[32];\n\t__le32 num_clusters;\n\t__le32 ncluster_array_offset;\n\t__le32 num_subset_parts;\n\t__le32 nsubset_parts_array_offset;\n\t__le32 nmodem_supported;\n\t__le32 feature_code;\n\t__le32 pcode;\n\t__le32 npartnamemap_offset;\n\t__le32 nnum_partname_mapping;\n\t__le32 oem_variant;\n\t__le32 num_kvps;\n\t__le32 kvps_offset;\n\t__le32 num_func_clusters;\n\t__le32 boot_cluster;\n\t__le32 boot_core;\n\t__le32 raw_package_type;\n\t__le32 reserve1[4];\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sock_xprt {\n\tstruct rpc_xprt xprt;\n\tstruct socket *sock;\n\tstruct sock *inet;\n\tstruct file *file;\n\tstruct {\n\t\tstruct {\n\t\t\t__be32 fraghdr;\n\t\t\t__be32 xid;\n\t\t\t__be32 calldir;\n\t\t};\n\t\tu32 offset;\n\t\tu32 len;\n\t\tlong unsigned int copied;\n\t} recv;\n\tstruct {\n\t\tu32 offset;\n\t} xmit;\n\tlong unsigned int sock_state;\n\tstruct delayed_work connect_worker;\n\tstruct work_struct error_worker;\n\tstruct work_struct recv_worker;\n\tstruct mutex recv_mutex;\n\tstruct completion handshake_done;\n\tstruct __kernel_sockaddr_storage srcaddr;\n\tshort unsigned int srcport;\n\tint xprt_err;\n\tstruct rpc_clnt *clnt;\n\tsize_t rcvsize;\n\tsize_t sndsize;\n\tstruct rpc_timeout tcp_timeout;\n\tvoid (*old_data_ready)(struct sock *);\n\tvoid (*old_state_change)(struct sock *);\n\tvoid (*old_write_space)(struct sock *);\n\tvoid (*old_error_report)(struct sock *);\n\tlong: 32;\n};\n\nstruct sockaddr_can {\n\t__kernel_sa_family_t can_family;\n\tint can_ifindex;\n\tunion {\n\t\tstruct {\n\t\t\tcanid_t rx_id;\n\t\t\tcanid_t tx_id;\n\t\t} tp;\n\t\tstruct {\n\t\t\t__u64 name;\n\t\t\t__u32 pgn;\n\t\t\t__u8 addr;\n\t\t} j1939;\n\t} can_addr;\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\tlong: 32;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tunsigned int input_queue_head;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tcall_single_data_t defer_csd;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tlong: 32;\n\tu64 args[16];\n};\n\nstruct sp804_clkevt {\n\tvoid *base;\n\tvoid *load;\n\tvoid *load_h;\n\tvoid *value;\n\tvoid *value_h;\n\tvoid *ctrl;\n\tvoid *intclr;\n\tvoid *ris;\n\tvoid *mis;\n\tvoid *bgload;\n\tvoid *bgload_h;\n\tlong unsigned int reload;\n\tint width;\n};\n\nstruct sp804_timer {\n\tint load;\n\tint load_h;\n\tint value;\n\tint value_h;\n\tint ctrl;\n\tint intclr;\n\tint ris;\n\tint mis;\n\tint bgload;\n\tint bgload_h;\n\tint timer_base[2];\n\tint width;\n};\n\nstruct sp805_wdt {\n\tstruct watchdog_device wdd;\n\tspinlock_t lock;\n\tvoid *base;\n\tstruct clk *clk;\n\tu64 rate;\n\tstruct amba_device *adev;\n\tunsigned int load_val;\n};\n\nstruct sp_clk_gate_info {\n\tu16 reg;\n\tu16 ext_parent;\n};\n\nstruct sp_intctl {\n\tvoid *g0;\n\tvoid *g1;\n\tstruct irq_domain *domain;\n\traw_spinlock_t lock;\n\tlong unsigned int states[1];\n};\n\nstruct sp_pll {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tspinlock_t lock;\n\tint div_shift;\n\tint div_width;\n\tint pd_bit;\n\tint bp_bit;\n\tlong unsigned int brate;\n\tu32 p[7];\n};\n\nstruct sp_reset {\n\tstruct reset_controller_dev rcdev;\n\tstruct notifier_block notifier;\n\tvoid *base;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\tlong: 32;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct spansion_nor_params {\n\tu8 clsr;\n};\n\nstruct spear1310_miphy_priv {\n\tu32 id;\n\tenum spear1310_miphy_mode mode;\n\tstruct regmap *misc;\n\tstruct phy *phy;\n};\n\nstruct spear1340_miphy_priv {\n\tenum spear1340_miphy_mode mode;\n\tstruct regmap *misc;\n\tstruct phy *phy;\n};\n\nstruct spear_ehci {\n\tstruct clk *clk;\n};\n\nstruct spear_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct spear_muxreg;\n\nstruct spear_gpio_pingroup {\n\tconst unsigned int *pins;\n\tunsigned int npins;\n\tstruct spear_muxreg *muxregs;\n\tu8 nmuxregs;\n};\n\nstruct spear_kbd {\n\tstruct input_dev *input;\n\tvoid *io_base;\n\tstruct clk *clk;\n\tunsigned int irq;\n\tu32 mode;\n\tu32 suspended_rate;\n\tu32 mode_ctl_reg;\n\tshort unsigned int last_key;\n\tshort unsigned int keycodes[256];\n\tbool irq_wake_enabled;\n};\n\nstruct spear_modemux {\n\tu16 modes;\n\tu8 nmuxregs;\n\tstruct spear_muxreg *muxregs;\n};\n\nstruct spear_muxreg {\n\tu16 reg;\n\tu32 mask;\n\tu32 val;\n};\n\nstruct spear_ohci {\n\tstruct clk *clk;\n};\n\nstruct spear_pingroup;\n\nstruct spear_pmx;\n\nstruct spear_pmx_mode;\n\nstruct spear_pinctrl_machdata {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tstruct spear_function **functions;\n\tunsigned int nfunctions;\n\tstruct spear_pingroup **groups;\n\tunsigned int ngroups;\n\tstruct spear_gpio_pingroup *gpio_pingroups;\n\tvoid (*gpio_request_endisable)(struct spear_pmx *, int, bool);\n\tunsigned int ngpio_pingroups;\n\tbool modes_supported;\n\tu16 mode;\n\tstruct spear_pmx_mode **pmx_modes;\n\tunsigned int npmx_modes;\n};\n\nstruct spear_pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int npins;\n\tstruct spear_modemux *modemuxs;\n\tunsigned int nmodemuxs;\n};\n\nstruct spear_pmx {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct spear_pinctrl_machdata *machdata;\n\tstruct regmap *regmap;\n};\n\nstruct spear_pmx_mode {\n\tconst char * const name;\n\tu16 mode;\n\tu16 reg;\n\tu16 mask;\n\tu32 val;\n};\n\nstruct spear_rtc_config {\n\tstruct rtc_device *rtc;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tvoid *ioaddr;\n\tunsigned int irq_wake;\n};\n\nstruct spear_sdhci {\n\tstruct clk *clk;\n};\n\nstruct spear_snor_flash;\n\nstruct spear_smi {\n\tstruct clk *clk;\n\tu32 status;\n\tlong unsigned int clk_rate;\n\tstruct mutex lock;\n\tvoid *io_base;\n\tstruct platform_device *pdev;\n\twait_queue_head_t cmd_complete;\n\tu32 num_flashes;\n\tstruct spear_snor_flash *flash[4];\n};\n\nstruct spear_smi_flash_info {\n\tchar *name;\n\tlong unsigned int mem_base;\n\tlong unsigned int size;\n\tstruct mtd_partition *partitions;\n\tint nr_partitions;\n\tu8 fast_mode;\n};\n\nstruct spear_smi_plat_data {\n\tlong unsigned int clk_rate;\n\tint num_flashes;\n\tstruct spear_smi_flash_info *board_flash_info;\n\tstruct device_node *np[4];\n};\n\nstruct spear_snor_flash {\n\tu32 bank;\n\tu32 dev_id;\n\tstruct mutex lock;\n\tlong: 32;\n\tstruct mtd_info mtd;\n\tu32 num_parts;\n\tstruct mtd_partition *parts;\n\tu32 page_size;\n\tvoid *base_addr;\n\tu8 erase_cmd;\n\tu8 fast_mode;\n\tlong: 32;\n};\n\nstruct spear_spics {\n\tvoid *base;\n\tu32 perip_cfg;\n\tu32 sw_enable_bit;\n\tu32 cs_value_bit;\n\tu32 cs_enable_mask;\n\tu32 cs_enable_shift;\n\tlong unsigned int use_count;\n\tint last_off;\n\tstruct gpio_chip chip;\n};\n\nstruct special_pd {\n\tstruct device_node *pd;\n\tenum pd_types type;\n};\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n\tlong: 32;\n};\n\ntypedef unsigned int (*spi_bb_txrx_bufs_fn)(struct spi_device *, spi_bb_txrx_word_fn, unsigned int, struct spi_transfer *, unsigned int);\n\nstruct spi_bitbang_cs {\n\tunsigned int nsecs;\n\tspi_bb_txrx_word_fn txrx_word;\n\tspi_bb_txrx_bufs_fn txrx_bufs;\n};\n\nstruct spi_controller_mem_ops;\n\nstruct spi_controller_mem_caps;\n\nstruct spi_offload_config;\n\nstruct spi_statistics;\n\nstruct spi_controller {\n\tstruct device dev;\n\tstruct list_head list;\n\ts16 bus_num;\n\tu16 num_chipselect;\n\tu16 num_data_lanes;\n\tu16 dma_alignment;\n\tu32 mode_bits;\n\tu32 buswidth_override_bits;\n\tu32 bits_per_word_mask;\n\tu32 min_speed_hz;\n\tu32 max_speed_hz;\n\tu16 flags;\n\tbool devm_allocated;\n\tunion {\n\t\tbool slave;\n\t\tbool target;\n\t};\n\tsize_t (*max_transfer_size)(struct spi_device *);\n\tsize_t (*max_message_size)(struct spi_device *);\n\tstruct mutex io_mutex;\n\tstruct mutex add_lock;\n\tspinlock_t bus_lock_spinlock;\n\tstruct mutex bus_lock_mutex;\n\tbool bus_lock_flag;\n\tint (*setup)(struct spi_device *);\n\tint (*set_cs_timing)(struct spi_device *);\n\tint (*transfer)(struct spi_device *, struct spi_message *);\n\tvoid (*cleanup)(struct spi_device *);\n\tbool (*can_dma)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tstruct device *dma_map_dev;\n\tstruct device *cur_rx_dma_dev;\n\tstruct device *cur_tx_dma_dev;\n\tbool queued;\n\tstruct kthread_worker *kworker;\n\tstruct kthread_work pump_messages;\n\tspinlock_t queue_lock;\n\tstruct list_head queue;\n\tstruct spi_message *cur_msg;\n\tstruct completion cur_msg_completion;\n\tbool cur_msg_incomplete;\n\tbool cur_msg_need_completion;\n\tbool busy;\n\tbool running;\n\tbool rt;\n\tbool auto_runtime_pm;\n\tbool fallback;\n\tbool last_cs_mode_high;\n\ts8 last_cs[4];\n\tu32 last_cs_index_mask: 4;\n\tstruct completion xfer_completion;\n\tsize_t max_dma_len;\n\tint (*optimize_message)(struct spi_message *);\n\tint (*unoptimize_message)(struct spi_message *);\n\tint (*prepare_transfer_hardware)(struct spi_controller *);\n\tint (*transfer_one_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_transfer_hardware)(struct spi_controller *);\n\tint (*prepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*target_abort)(struct spi_controller *);\n\tvoid (*set_cs)(struct spi_device *, bool);\n\tint (*transfer_one)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tvoid (*handle_err)(struct spi_controller *, struct spi_message *);\n\tconst struct spi_controller_mem_ops *mem_ops;\n\tconst struct spi_controller_mem_caps *mem_caps;\n\tbool dtr_caps;\n\tstruct spi_offload * (*get_offload)(struct spi_device *, const struct spi_offload_config *);\n\tvoid (*put_offload)(struct spi_offload *);\n\tstruct gpio_desc **cs_gpiods;\n\tbool use_gpio_descriptors;\n\ts8 unused_native_cs;\n\ts8 max_native_cs;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tvoid *dummy_rx;\n\tvoid *dummy_tx;\n\tint (*fw_translate_cs)(struct spi_controller *, unsigned int);\n\tbool ptp_sts_supported;\n\tlong unsigned int irq_flags;\n\tbool queue_empty;\n\tbool must_async;\n\tbool defer_optimize_message;\n};\n\nstruct spi_controller_mem_caps {\n\tbool dtr;\n\tbool ecc;\n\tbool swap16;\n\tbool per_op_freq;\n};\n\nstruct spi_mem;\n\nstruct spi_mem_dirmap_desc;\n\nstruct spi_controller_mem_ops {\n\tint (*adjust_op_size)(struct spi_mem *, struct spi_mem_op *);\n\tbool (*supports_op)(struct spi_mem *, const struct spi_mem_op *);\n\tint (*exec_op)(struct spi_mem *, const struct spi_mem_op *);\n\tconst char * (*get_name)(struct spi_mem *);\n\tint (*dirmap_create)(struct spi_mem_dirmap_desc *);\n\tvoid (*dirmap_destroy)(struct spi_mem_dirmap_desc *);\n\tssize_t (*dirmap_read)(struct spi_mem_dirmap_desc *, u64, size_t, void *);\n\tssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *, u64, size_t, const void *);\n\tint (*poll_status)(struct spi_mem *, const struct spi_mem_op *, u16, u16, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct spi_device {\n\tstruct device dev;\n\tstruct spi_controller *controller;\n\tu32 max_speed_hz;\n\tu8 bits_per_word;\n\tbool rt;\n\tu32 mode;\n\tint irq;\n\tvoid *controller_state;\n\tvoid *controller_data;\n\tchar modalias[32];\n\tconst char *driver_override;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct spi_delay word_delay;\n\tstruct spi_delay cs_setup;\n\tstruct spi_delay cs_hold;\n\tstruct spi_delay cs_inactive;\n\tu8 chip_select[4];\n\tu8 num_chipselect;\n\tu32 cs_index_mask: 4;\n\tstruct gpio_desc *cs_gpiod[4];\n\tu8 tx_lane_map[8];\n\tu8 num_tx_lanes;\n\tu8 rx_lane_map[8];\n\tu8 num_rx_lanes;\n};\n\nstruct spi_device_id {\n\tchar name[32];\n\tkernel_ulong_t driver_data;\n};\n\nstruct spi_driver {\n\tconst struct spi_device_id *id_table;\n\tint (*probe)(struct spi_device *);\n\tvoid (*remove)(struct spi_device *);\n\tvoid (*shutdown)(struct spi_device *);\n\tstruct device_driver driver;\n};\n\nstruct spi_ioc_transfer {\n\t__u64 tx_buf;\n\t__u64 rx_buf;\n\t__u32 len;\n\t__u32 speed_hz;\n\t__u16 delay_usecs;\n\t__u8 bits_per_word;\n\t__u8 cs_change;\n\t__u8 tx_nbits;\n\t__u8 rx_nbits;\n\t__u8 word_delay_usecs;\n\t__u8 pad;\n};\n\nstruct spi_mem {\n\tstruct spi_device *spi;\n\tvoid *drvpriv;\n\tconst char *name;\n};\n\nstruct spi_mem_op {\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tu16 opcode;\n\t} cmd;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tlong: 32;\n\t\tu64 val;\n\t} addr;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t} dummy;\n\tstruct {\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 ecc: 1;\n\t\tu8 swap16: 1;\n\t\tu8 __pad: 5;\n\t\tenum spi_mem_data_dir dir;\n\t\tunsigned int nbytes;\n\t\tunion {\n\t\t\tvoid *in;\n\t\t\tconst void *out;\n\t\t} buf;\n\t} data;\n\tunsigned int max_freq;\n};\n\nstruct spi_mem_dirmap_info {\n\tstruct spi_mem_op op_tmpl;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct spi_mem_dirmap_desc {\n\tstruct spi_mem *mem;\n\tlong: 32;\n\tstruct spi_mem_dirmap_info info;\n\tunsigned int nodirmap;\n\tvoid *priv;\n};\n\nstruct spi_mem_driver {\n\tstruct spi_driver spidrv;\n\tint (*probe)(struct spi_mem *);\n\tint (*remove)(struct spi_mem *);\n\tvoid (*shutdown)(struct spi_mem *);\n};\n\nstruct spi_nor_rww {\n\twait_queue_head_t wait;\n\tbool ongoing_io;\n\tbool ongoing_rd;\n\tbool ongoing_pe;\n\tunsigned int used_banks;\n};\n\nstruct spi_nor_manufacturer;\n\nstruct spi_nor_controller_ops;\n\nstruct spi_nor_flash_parameter;\n\nstruct spi_nor {\n\tstruct mtd_info mtd;\n\tstruct mutex lock;\n\tstruct spi_nor_rww rww;\n\tstruct device *dev;\n\tstruct spi_mem *spimem;\n\tu8 *bouncebuf;\n\tsize_t bouncebuf_size;\n\tu8 *id;\n\tconst struct flash_info *info;\n\tconst struct spi_nor_manufacturer *manufacturer;\n\tu8 addr_nbytes;\n\tu8 erase_opcode;\n\tu8 read_opcode;\n\tu8 read_dummy;\n\tu8 program_opcode;\n\tenum spi_nor_protocol read_proto;\n\tenum spi_nor_protocol write_proto;\n\tenum spi_nor_protocol reg_proto;\n\tbool sst_write_second;\n\tu32 flags;\n\tenum spi_nor_cmd_ext cmd_ext_type;\n\tstruct sfdp *sfdp;\n\tstruct dentry *debugfs_root;\n\tconst struct spi_nor_controller_ops *controller_ops;\n\tstruct spi_nor_flash_parameter *params;\n\tstruct {\n\t\tstruct spi_mem_dirmap_desc *rdesc;\n\t\tstruct spi_mem_dirmap_desc *wdesc;\n\t} dirmap;\n\tvoid *priv;\n};\n\nstruct spi_nor_controller_ops {\n\tint (*prepare)(struct spi_nor *);\n\tvoid (*unprepare)(struct spi_nor *);\n\tint (*read_reg)(struct spi_nor *, u8, u8 *, size_t);\n\tint (*write_reg)(struct spi_nor *, u8, const u8 *, size_t);\n\tssize_t (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tssize_t (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*erase)(struct spi_nor *, loff_t);\n};\n\nstruct spi_nor_erase_command {\n\tstruct list_head list;\n\tu32 count;\n\tu32 size;\n\tu8 opcode;\n};\n\nstruct spi_nor_erase_region {\n\tu64 offset;\n\tu64 size;\n\tu8 erase_mask;\n\tbool overlaid;\n\tlong: 32;\n};\n\nstruct spi_nor_erase_type {\n\tu32 size;\n\tu32 size_shift;\n\tu32 size_mask;\n\tu8 opcode;\n\tu8 idx;\n};\n\nstruct spi_nor_erase_map {\n\tstruct spi_nor_erase_region *regions;\n\tlong: 32;\n\tstruct spi_nor_erase_region uniform_region;\n\tstruct spi_nor_erase_type erase_type[4];\n\tunsigned int n_regions;\n\tlong: 32;\n};\n\nstruct spi_nor_fixups {\n\tvoid (*default_init)(struct spi_nor *);\n\tint (*post_bfpt)(struct spi_nor *, const struct sfdp_parameter_header *, const struct sfdp_bfpt *);\n\tvoid (*smpt_read_dummy)(const struct spi_nor *, u8 *);\n\tvoid (*smpt_map_id)(const struct spi_nor *, u8 *);\n\tint (*post_sfdp)(struct spi_nor *);\n\tint (*late_init)(struct spi_nor *);\n};\n\nstruct spi_nor_hwcaps {\n\tu32 mask;\n};\n\nstruct spi_nor_read_command {\n\tu8 num_mode_clocks;\n\tu8 num_wait_states;\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_pp_command {\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_otp_ops;\n\nstruct spi_nor_otp {\n\tconst struct spi_nor_otp_organization *org;\n\tconst struct spi_nor_otp_ops *ops;\n};\n\nstruct spi_nor_locking_ops;\n\nstruct spi_nor_flash_parameter {\n\tu64 bank_size;\n\tu64 size;\n\tu32 writesize;\n\tu32 page_size;\n\tu8 addr_nbytes;\n\tu8 addr_mode_nbytes;\n\tu8 rdsr_dummy;\n\tu8 rdsr_addr_nbytes;\n\tu8 n_banks;\n\tu8 n_dice;\n\tu8 die_erase_opcode;\n\tu32 *vreg_offset;\n\tstruct spi_nor_hwcaps hwcaps;\n\tstruct spi_nor_read_command reads[16];\n\tstruct spi_nor_pp_command page_programs[8];\n\tstruct spi_nor_erase_map erase_map;\n\tstruct spi_nor_otp otp;\n\tint (*set_octal_dtr)(struct spi_nor *, bool);\n\tint (*quad_enable)(struct spi_nor *);\n\tint (*set_4byte_addr_mode)(struct spi_nor *, bool);\n\tint (*ready)(struct spi_nor *);\n\tconst struct spi_nor_locking_ops *locking_ops;\n\tvoid *priv;\n};\n\nstruct spi_nor_id {\n\tconst u8 *bytes;\n\tu8 len;\n};\n\nstruct spi_nor_locking_ops {\n\tint (*lock)(struct spi_nor *, loff_t, u64);\n\tint (*unlock)(struct spi_nor *, loff_t, u64);\n\tint (*is_locked)(struct spi_nor *, loff_t, u64);\n};\n\nstruct spi_nor_manufacturer {\n\tconst char *name;\n\tconst struct flash_info *parts;\n\tunsigned int nparts;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct spi_nor_otp_ops {\n\tint (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tint (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*lock)(struct spi_nor *, unsigned int);\n\tint (*erase)(struct spi_nor *, loff_t);\n\tint (*is_locked)(struct spi_nor *, unsigned int);\n};\n\nstruct spi_nor_otp_organization {\n\tsize_t len;\n\tlong: 32;\n\tloff_t base;\n\tloff_t offset;\n\tunsigned int n_regions;\n\tlong: 32;\n};\n\nstruct spi_offload_ops;\n\nstruct spi_offload {\n\tstruct device *provider_dev;\n\tvoid *priv;\n\tconst struct spi_offload_ops *ops;\n\tu32 xfer_flags;\n};\n\nstruct spi_offload_config {\n\tu32 capability_flags;\n};\n\nstruct spi_offload_ops {\n\tint (*trigger_enable)(struct spi_offload *);\n\tvoid (*trigger_disable)(struct spi_offload *);\n\tstruct dma_chan * (*tx_stream_request_dma_chan)(struct spi_offload *);\n\tstruct dma_chan * (*rx_stream_request_dma_chan)(struct spi_offload *);\n};\n\nstruct spi_ops {\n\tint (*set_config_register)(struct rspi_data *, int);\n\tint (*transfer_one)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tu16 extra_mode_bits;\n\tu16 min_div;\n\tu16 max_div;\n\tu16 flags;\n\tu16 fifo_size;\n\tu8 num_hw_ss;\n};\n\nstruct spi_replaced_transfers;\n\ntypedef void (*spi_replaced_release_t)(struct spi_controller *, struct spi_message *, struct spi_replaced_transfers *);\n\nstruct spi_replaced_transfers {\n\tspi_replaced_release_t release;\n\tvoid *extradata;\n\tstruct list_head replaced_transfers;\n\tstruct list_head *replaced_after;\n\tsize_t inserted;\n\tstruct spi_transfer inserted_transfers[0];\n};\n\ntypedef void (*spi_res_release_t)(struct spi_controller *, struct spi_message *, void *);\n\nstruct spi_res {\n\tstruct list_head entry;\n\tspi_res_release_t release;\n\tlong: 32;\n\tlong long unsigned int data[0];\n};\n\nstruct spi_statistics {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t messages;\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t timedout;\n\tu64_stats_t spi_sync;\n\tu64_stats_t spi_sync_immediate;\n\tu64_stats_t spi_async;\n\tu64_stats_t bytes;\n\tu64_stats_t bytes_rx;\n\tu64_stats_t bytes_tx;\n\tu64_stats_t transfer_bytes_histo[17];\n\tu64_stats_t transfers_split_maxsize;\n};\n\nstruct spidev_data {\n\tdev_t devt;\n\tstruct mutex spi_lock;\n\tstruct spi_device *spi;\n\tstruct list_head device_entry;\n\tunsigned int users;\n\tu8 *tx_buffer;\n\tu8 *rx_buffer;\n\tu32 speed_hz;\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tlong: 32;\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n\tlong: 32;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct spm_reg_data;\n\nstruct spm_driver_data {\n\tvoid *reg_base;\n\tconst struct spm_reg_data *reg_data;\n\tstruct device *dev;\n\tunsigned int volt_sel;\n\tint reg_cpu;\n};\n\nstruct spm_reg_data {\n\tconst u16 *reg_offset;\n\tu32 spm_cfg;\n\tu32 spm_dly;\n\tu32 pmic_dly;\n\tu32 pmic_data[2];\n\tu32 avs_ctl;\n\tu32 avs_limit;\n\tu8 seq[64];\n\tu8 start_index[4];\n\tsmp_call_func_t set_vdd;\n\tstruct linear_range *range;\n\tunsigned int ramp_delay;\n\tunsigned int init_uV;\n};\n\nstruct spmi_controller {\n\tstruct device dev;\n\tunsigned int nr;\n\tint (*cmd)(struct spmi_controller *, u8, u8);\n\tint (*read_cmd)(struct spmi_controller *, u8, u8, u16, u8 *, size_t);\n\tint (*write_cmd)(struct spmi_controller *, u8, u8, u16, const u8 *, size_t);\n};\n\nstruct spmi_device {\n\tstruct device dev;\n\tstruct spmi_controller *ctrl;\n\tu8 usid;\n};\n\nstruct spmi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct spmi_device *);\n\tvoid (*remove)(struct spmi_device *);\n\tvoid (*shutdown)(struct spmi_device *);\n};\n\nstruct spmi_pmic_arb {\n\tvoid *rd_base;\n\tvoid *wr_base;\n\tvoid *core;\n\tresource_size_t core_size;\n\tvoid *apid_map;\n\tu8 channel;\n\tu8 ee;\n\tconst struct pmic_arb_ver_ops *ver_ops;\n\tint max_periphs;\n\tstruct spmi_pmic_arb_bus *buses[4];\n\tint buses_available;\n};\n\nstruct spmi_pmic_arb_bus {\n\tstruct spmi_pmic_arb *pmic_arb;\n\tstruct irq_domain *domain;\n\tvoid *intr;\n\tvoid *cnfg;\n\tvoid *apid_owner;\n\tstruct spmi_controller *spmic;\n\traw_spinlock_t lock;\n\tu16 base_apid;\n\tint apid_count;\n\tu32 *mapping_table;\n\tlong unsigned int mapping_table_valid[16];\n\tu16 *ppid_to_apid;\n\tu16 last_apid;\n\tstruct apid_data *apid_data;\n\tu16 min_apid;\n\tu16 max_apid;\n\tint irq;\n\tu8 id;\n};\n\nstruct spmi_pmic_arb_qpnpint_type {\n\tu8 type;\n\tu8 polarity_high;\n\tu8 polarity_low;\n};\n\nstruct spmi_voltage_set_points;\n\nstruct spmi_regulator {\n\tstruct regulator_desc desc;\n\tstruct device *dev;\n\tstruct delayed_work ocp_work;\n\tstruct regmap *regmap;\n\tstruct spmi_voltage_set_points *set_points;\n\tenum spmi_regulator_logical_type logical_type;\n\tint ocp_irq;\n\tint ocp_count;\n\tint ocp_max_retries;\n\tint ocp_retry_delay_ms;\n\tint hpm_min_load;\n\tint slew_rate;\n\tktime_t vs_enable_time;\n\tu16 base;\n\tstruct list_head node;\n\tlong: 32;\n};\n\nstruct spmi_regulator_data {\n\tconst char *name;\n\tu16 base;\n\tconst char *supply;\n\tconst char *ocp;\n\tu16 force_type;\n};\n\nstruct spmi_regulator_init_data {\n\tunsigned int pin_ctrl_enable;\n\tunsigned int pin_ctrl_hpm;\n\tenum spmi_vs_soft_start_str vs_soft_start_strength;\n};\n\nstruct spmi_regulator_mapping {\n\tenum spmi_regulator_type type;\n\tenum spmi_regulator_subtype subtype;\n\tenum spmi_regulator_logical_type logical_type;\n\tu32 revision_min;\n\tu32 revision_max;\n\tconst struct regulator_ops *ops;\n\tstruct spmi_voltage_set_points *set_points;\n\tint hpm_min_load;\n};\n\nstruct spmi_voltage_range {\n\tint min_uV;\n\tint max_uV;\n\tint step_uV;\n\tint set_point_min_uV;\n\tint set_point_max_uV;\n\tunsigned int n_voltages;\n\tu8 range_sel;\n};\n\nstruct spmi_voltage_set_points {\n\tconst struct spmi_voltage_range *range;\n\tint count;\n\tunsigned int n_voltages;\n};\n\nstruct sppctl_grp;\n\nstruct sppctl_func {\n\tconst char * const name;\n\tconst enum pinmux_type type;\n\tconst u8 roff;\n\tconst u8 boff;\n\tconst u8 blen;\n\tconst struct sppctl_grp * const grps;\n\tconst unsigned int gnum;\n};\n\nstruct sppctl_gpio_chip {\n\tvoid *gpioxt_base;\n\tvoid *first_base;\n\tstruct gpio_chip chip;\n\tspinlock_t lock;\n};\n\nstruct sppctl_grp {\n\tconst char * const name;\n\tconst u8 gval;\n\tconst unsigned int * const pins;\n\tconst unsigned int pnum;\n};\n\nstruct sppctl_pdata {\n\tvoid *moon2_base;\n\tvoid *gpioxt_base;\n\tvoid *first_base;\n\tvoid *moon1_base;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct pinctrl_gpio_range pctl_grange;\n\tstruct sppctl_gpio_chip *spp_gchip;\n\tconst char **unq_grps;\n\tsize_t unq_grps_sz;\n\tstruct grp2fp_map *g2fp_maps;\n};\n\nstruct squashfs_base_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n};\n\nstruct squashfs_cache_entry;\n\nstruct squashfs_cache {\n\tchar *name;\n\tint entries;\n\tint curr_blk;\n\tint next_blk;\n\tint num_waiters;\n\tint unused;\n\tint block_size;\n\tint pages;\n\tspinlock_t lock;\n\twait_queue_head_t wait_queue;\n\tstruct squashfs_cache_entry *entry;\n};\n\nstruct squashfs_page_actor;\n\nstruct squashfs_cache_entry {\n\tu64 block;\n\tint length;\n\tint refcount;\n\tu64 next_index;\n\tint pending;\n\tint error;\n\tint num_waiters;\n\twait_queue_head_t wait_queue;\n\tstruct squashfs_cache *cache;\n\tvoid **data;\n\tstruct squashfs_page_actor *actor;\n\tlong: 32;\n};\n\nstruct squashfs_sb_info;\n\nstruct squashfs_decompressor {\n\tvoid * (*init)(struct squashfs_sb_info *, void *);\n\tvoid * (*comp_opts)(struct squashfs_sb_info *, void *, int);\n\tvoid (*free)(void *);\n\tint (*decompress)(struct squashfs_sb_info *, void *, struct bio *, int, int, struct squashfs_page_actor *);\n\tint id;\n\tchar *name;\n\tint alloc_buffer;\n\tint supported;\n};\n\nstruct squashfs_decompressor_thread_ops {\n\tvoid * (*create)(struct squashfs_sb_info *, void *);\n\tvoid (*destroy)(struct squashfs_sb_info *);\n\tint (*decompress)(struct squashfs_sb_info *, struct bio *, int, int, struct squashfs_page_actor *);\n\tint (*max_decompressors)(void);\n};\n\nstruct squashfs_dev_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 rdev;\n};\n\nstruct squashfs_dir_entry {\n\t__le16 offset;\n\t__le16 inode_number;\n\t__le16 type;\n\t__le16 size;\n\tchar name[0];\n};\n\nstruct squashfs_dir_header {\n\t__le32 count;\n\t__le32 start_block;\n\t__le32 inode_number;\n};\n\nstruct squashfs_dir_index {\n\t__le32 index;\n\t__le32 start_block;\n\t__le32 size;\n\tunsigned char name[0];\n};\n\nstruct squashfs_dir_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 start_block;\n\t__le32 nlink;\n\t__le16 file_size;\n\t__le16 offset;\n\t__le32 parent_inode;\n};\n\nstruct squashfs_fragment_entry {\n\t__le64 start_block;\n\t__le32 size;\n\tunsigned int unused;\n};\n\nstruct squashfs_ldev_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 rdev;\n\t__le32 xattr;\n};\n\nstruct squashfs_symlink_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 symlink_size;\n\tchar symlink[0];\n};\n\nstruct squashfs_reg_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 start_block;\n\t__le32 fragment;\n\t__le32 offset;\n\t__le32 file_size;\n\t__le16 block_list[0];\n};\n\nstruct squashfs_lreg_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le64 start_block;\n\t__le64 file_size;\n\t__le64 sparse;\n\t__le32 nlink;\n\t__le32 fragment;\n\t__le32 offset;\n\t__le32 xattr;\n\t__le16 block_list[0];\n};\n\nstruct squashfs_ldir_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 file_size;\n\t__le32 start_block;\n\t__le32 parent_inode;\n\t__le16 i_count;\n\t__le16 offset;\n\t__le32 xattr;\n\tstruct squashfs_dir_index index[0];\n};\n\nstruct squashfs_ipc_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n};\n\nstruct squashfs_lipc_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 xattr;\n};\n\nunion squashfs_inode {\n\tstruct squashfs_base_inode base;\n\tstruct squashfs_dev_inode dev;\n\tstruct squashfs_ldev_inode ldev;\n\tstruct squashfs_symlink_inode symlink;\n\tstruct squashfs_reg_inode reg;\n\tstruct squashfs_lreg_inode lreg;\n\tstruct squashfs_dir_inode dir;\n\tstruct squashfs_ldir_inode ldir;\n\tstruct squashfs_ipc_inode ipc;\n\tstruct squashfs_lipc_inode lipc;\n};\n\nstruct squashfs_inode_info {\n\tu64 start;\n\tint offset;\n\tlong: 32;\n\tu64 xattr;\n\tunsigned int xattr_size;\n\tint xattr_count;\n\tint parent;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tu64 fragment_block;\n\t\t\tint fragment_size;\n\t\t\tint fragment_offset;\n\t\t\tu64 block_list_start;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dir_idx_start;\n\t\t\tint dir_idx_offset;\n\t\t\tint dir_idx_cnt;\n\t\t};\n\t};\n\tstruct inode vfs_inode;\n};\n\nstruct squashfs_lzo {\n\tvoid *input;\n\tvoid *output;\n};\n\nstruct squashfs_mount_opts {\n\tenum Opt_errors errors;\n\tconst struct squashfs_decompressor_thread_ops *thread_ops;\n\tint thread_num;\n};\n\nstruct squashfs_page_actor {\n\tunion {\n\t\tvoid **buffer;\n\t\tstruct page **page;\n\t};\n\tvoid *pageaddr;\n\tvoid *tmp_buffer;\n\tvoid * (*squashfs_first_page)(struct squashfs_page_actor *);\n\tvoid * (*squashfs_next_page)(struct squashfs_page_actor *);\n\tvoid (*squashfs_finish_page)(struct squashfs_page_actor *);\n\tstruct page *last_page;\n\tint pages;\n\tint length;\n\tint next_page;\n\tint alloc_buffer;\n\tint returned_pages;\n\tlong unsigned int next_index;\n};\n\nstruct squashfs_sb_info {\n\tconst struct squashfs_decompressor *decompressor;\n\tint devblksize;\n\tint devblksize_log2;\n\tstruct squashfs_cache *block_cache;\n\tstruct squashfs_cache *fragment_cache;\n\tstruct squashfs_cache *read_page;\n\tstruct address_space *cache_mapping;\n\tint next_meta_index;\n\t__le64 *id_table;\n\t__le64 *fragment_index;\n\t__le64 *xattr_id_table;\n\tstruct mutex meta_index_mutex;\n\tstruct meta_index *meta_index;\n\tvoid *stream;\n\t__le64 *inode_lookup_table;\n\tlong: 32;\n\tu64 inode_table;\n\tu64 directory_table;\n\tu64 xattr_table;\n\tunsigned int block_size;\n\tshort unsigned int block_log;\n\tlong long int bytes_used;\n\tunsigned int inodes;\n\tunsigned int fragments;\n\tunsigned int xattr_ids;\n\tunsigned int ids;\n\tbool panic_on_errors;\n\tconst struct squashfs_decompressor_thread_ops *thread_ops;\n\tint max_thread_num;\n\tlong: 32;\n};\n\nstruct squashfs_stream {\n\tvoid *stream;\n\tstruct mutex mutex;\n};\n\nstruct squashfs_super_block {\n\t__le32 s_magic;\n\t__le32 inodes;\n\t__le32 mkfs_time;\n\t__le32 block_size;\n\t__le32 fragments;\n\t__le16 compression;\n\t__le16 block_log;\n\t__le16 flags;\n\t__le16 no_ids;\n\t__le16 s_major;\n\t__le16 s_minor;\n\t__le64 root_inode;\n\t__le64 bytes_used;\n\t__le64 id_table_start;\n\t__le64 xattr_id_table_start;\n\t__le64 inode_table_start;\n\t__le64 directory_table_start;\n\t__le64 fragment_table_start;\n\t__le64 lookup_table_start;\n};\n\nstruct squashfs_xattr_id_table {\n\t__le64 xattr_table_start;\n\t__le32 xattr_ids;\n\t__le32 unused;\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec;\n\nstruct squashfs_xz {\n\tstruct xz_dec *state;\n\tstruct xz_buf buf;\n};\n\nstruct sr6_tlv {\n\t__u8 type;\n\t__u8 len;\n\t__u8 data[0];\n};\n\nstruct sr_pcie_phy_core;\n\nstruct sr_pcie_phy {\n\tstruct sr_pcie_phy_core *core;\n\tunsigned int index;\n\tstruct phy *phy;\n};\n\nstruct sr_pcie_phy_core {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct regmap *cdru;\n\tstruct regmap *mhb;\n\tu32 pipemux;\n\tstruct sr_pcie_phy phys[9];\n};\n\nstruct sr_thermal;\n\nstruct sr_tmon {\n\tunsigned int crit_temp;\n\tunsigned int tmon_id;\n\tstruct sr_thermal *priv;\n};\n\nstruct sr_thermal {\n\tvoid *regs;\n\tunsigned int max_crit_temp;\n\tstruct sr_tmon tmon[6];\n};\n\nstruct sram_config {\n\tint (*init)(void);\n\tbool map_only_reserved;\n};\n\nstruct sram_partition;\n\nstruct sram_dev {\n\tconst struct sram_config *config;\n\tstruct device *dev;\n\tvoid *virt_base;\n\tbool no_memory_wc;\n\tstruct gen_pool *pool;\n\tstruct sram_partition *partition;\n\tu32 partitions;\n};\n\nstruct sram_partition {\n\tvoid *base;\n\tstruct gen_pool *pool;\n\tstruct bin_attribute battr;\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct sram_reserve {\n\tstruct list_head list;\n\tu32 start;\n\tu32 size;\n\tstruct resource res;\n\tbool export;\n\tbool pool;\n\tbool protect_exec;\n\tconst char *label;\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct ssbi {\n\tvoid *base;\n\tspinlock_t lock;\n\tenum ssbi_controller_type controller_type;\n\tint (*read)(struct ssbi *, u16, u8 *, int);\n\tint (*write)(struct ssbi *, u16, const u8 *, int);\n};\n\nstruct st_ahci_drv_data {\n\tstruct reset_control *pwr;\n\tstruct reset_control *sw_rst;\n\tstruct reset_control *pwr_rst;\n};\n\nstruct st_clk_quadfs_fsynth {\n\tstruct clk_hw hw;\n\tvoid *regs_base;\n\tspinlock_t *lock;\n\tstruct clkgen_quadfs_data *data;\n\tu32 chan;\n\tu32 md;\n\tu32 pe;\n\tu32 sdiv;\n\tu32 nsdiv;\n};\n\nstruct st_clk_quadfs_pll {\n\tstruct clk_hw hw;\n\tvoid *regs_base;\n\tspinlock_t *lock;\n\tstruct clkgen_quadfs_data *data;\n\tu32 ndiv;\n};\n\nstruct st_clksrc_ddata {\n\tstruct clk *clk;\n\tvoid *base;\n};\n\nstruct st_dwc3 {\n\tstruct device *dev;\n\tvoid *glue_base;\n\tstruct regmap *regmap;\n\tint syscfg_reg_off;\n\tenum usb_dr_mode dr_mode;\n\tstruct reset_control *rstc_pwrdn;\n\tstruct reset_control *rstc_rst;\n};\n\nstruct st_ehci_platform_priv {\n\tstruct clk *clks[3];\n\tstruct clk *clk48;\n\tstruct reset_control *rst;\n\tstruct reset_control *pwr;\n\tstruct phy *phy;\n};\n\nstruct st_retime_packed {\n\tstruct regmap_field *clk1notclk0;\n\tstruct regmap_field *delay_0;\n\tstruct regmap_field *delay_1;\n\tstruct regmap_field *invertclk;\n\tstruct regmap_field *retime;\n\tstruct regmap_field *clknotdata;\n\tstruct regmap_field *double_edge;\n};\n\nstruct st_retime_dedicated {\n\tstruct regmap_field *rt[8];\n};\n\nstruct st_pio_control {\n\tu32 rt_pin_mask;\n\tstruct regmap_field *alt;\n\tstruct regmap_field *oe;\n\tstruct regmap_field *pu;\n\tstruct regmap_field *od;\n\tunion {\n\t\tstruct st_retime_packed rt_p;\n\t\tstruct st_retime_dedicated rt_d;\n\t} rt;\n};\n\nstruct st_gpio_bank {\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range range;\n\tvoid *base;\n\tstruct st_pio_control pc;\n\tlong unsigned int irq_edge_conf;\n\tspinlock_t lock;\n};\n\nstruct st_i2c_client {\n\tu8 addr;\n\tu32 count;\n\tu32 xfered;\n\tu8 *buf;\n\tint result;\n\tbool stop;\n};\n\nstruct st_i2c_dev {\n\tstruct i2c_adapter adap;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct completion complete;\n\tint irq;\n\tstruct clk *clk;\n\tint mode;\n\tu32 scl_min_width_us;\n\tu32 sda_min_width_us;\n\tstruct st_i2c_client client;\n\tbool busy;\n};\n\nstruct st_i2c_timings {\n\tu32 rate;\n\tu32 rep_start_hold;\n\tu32 rep_start_setup;\n\tu32 start_hold;\n\tu32 data_setup_time;\n\tu32 stop_setup_time;\n\tu32 bus_free_time;\n\tu32 sda_pulse_min_limit;\n};\n\nstruct st_irq_syscfg {\n\tstruct regmap *regmap;\n\tunsigned int syscfg;\n\tunsigned int config;\n\tbool ext_inverted;\n};\n\nstruct st_keyscan {\n\tvoid *base;\n\tint irq;\n\tstruct clk *clk;\n\tstruct input_dev *input_dev;\n\tlong unsigned int last_state;\n\tunsigned int n_rows;\n\tunsigned int n_cols;\n\tunsigned int debounce_us;\n};\n\nstruct st_mmc_platform_data {\n\tstruct reset_control *rstc;\n\tstruct clk *icnclk;\n\tvoid *top_ioaddr;\n};\n\nstruct st_ohci_platform_priv {\n\tstruct clk *clks[3];\n\tstruct clk *clk48;\n\tstruct reset_control *rst;\n\tstruct reset_control *pwr;\n\tstruct phy *phy;\n};\n\nstruct st_pctl_data {\n\tconst enum st_retime_style rt_style;\n\tconst unsigned int *input_delays;\n\tconst int ninput_delays;\n\tconst unsigned int *output_delays;\n\tconst int noutput_delays;\n\tconst int alt;\n\tconst int oe;\n\tconst int pu;\n\tconst int od;\n\tconst int rt;\n};\n\nstruct st_pinconf;\n\nstruct st_pctl_group {\n\tconst char *name;\n\tunsigned int *pins;\n\tunsigned int npins;\n\tstruct st_pinconf *pin_conf;\n};\n\nstruct st_pinconf {\n\tint pin;\n\tconst char *name;\n\tlong unsigned int config;\n\tint altfunc;\n};\n\nstruct st_pmx_func;\n\nstruct st_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct st_gpio_bank *banks;\n\tint nbanks;\n\tstruct st_pmx_func *functions;\n\tint nfunctions;\n\tstruct st_pctl_group *groups;\n\tint ngroups;\n\tstruct regmap *regmap;\n\tconst struct st_pctl_data *data;\n\tvoid *irqmux_base;\n};\n\nstruct st_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct st_rng_data {\n\tvoid *base;\n\tstruct hwrng ops;\n};\n\nstruct st_rtc {\n\tstruct rtc_device *rtc_dev;\n\tstruct rtc_wkalrm alarm;\n\tstruct clk *clk;\n\tlong unsigned int clkrate;\n\tvoid *ioaddr;\n\tbool irq_enabled: 1;\n\tspinlock_t lock;\n\tshort int irq;\n};\n\nstruct st_thermal_sensor_ops;\n\nstruct st_thermal_compat_data {\n\tchar *sys_compat;\n\tconst struct reg_field *reg_fields;\n\tconst struct st_thermal_sensor_ops *ops;\n\tunsigned int calibration_val;\n\tint temp_adjust_val;\n\tint crit_temp;\n};\n\nstruct st_thermal_sensor {\n\tstruct device *dev;\n\tstruct thermal_zone_device *thermal_dev;\n\tconst struct st_thermal_sensor_ops *ops;\n\tconst struct st_thermal_compat_data *cdata;\n\tstruct clk *clk;\n\tstruct regmap *regmap;\n\tstruct regmap_field *pwr;\n\tstruct regmap_field *dcorrect;\n\tstruct regmap_field *overflow;\n\tstruct regmap_field *temp_data;\n\tstruct regmap_field *int_thresh_hi;\n\tstruct regmap_field *int_enable;\n\tint irq;\n\tvoid *mmio_base;\n};\n\nstruct st_thermal_sensor_ops {\n\tint (*power_ctrl)(struct st_thermal_sensor *, enum st_thermal_power_state);\n\tint (*alloc_regfields)(struct st_thermal_sensor *);\n\tint (*regmap_init)(struct st_thermal_sensor *);\n\tint (*register_enable_irq)(struct st_thermal_sensor *);\n\tint (*enable_irq)(struct st_thermal_sensor *);\n};\n\nstruct st_wdog_syscfg;\n\nstruct st_wdog {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tconst struct st_wdog_syscfg *syscfg;\n\tstruct clk *clk;\n\tlong unsigned int clkrate;\n\tbool warm_reset;\n};\n\nstruct st_wdog_syscfg {\n\tunsigned int reset_type_reg;\n\tunsigned int reset_type_mask;\n\tunsigned int enable_reg;\n\tunsigned int enable_mask;\n};\n\nstruct stack {\n\tu32 irq[4];\n\tu32 abt[4];\n\tu32 und[4];\n\tu32 fiq[4];\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[0];\n};\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tlong: 32;\n\tu64 data[0];\n};\n\nstruct stack_record {\n\tstruct list_head hash_list;\n\tu32 hash;\n\tu32 size;\n\tunion handle_parts handle;\n\trefcount_t count;\n\tunion {\n\t\tlong unsigned int entries[64];\n\t\tstruct {\n\t\t\tstruct list_head free_list;\n\t\t\tlong unsigned int rcu_state;\n\t\t};\n\t};\n};\n\nstruct stackframe {\n\tlong unsigned int fp;\n\tlong unsigned int sp;\n\tlong unsigned int lr;\n\tlong unsigned int pc;\n\tlong unsigned int *lr_addr;\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\tlong unsigned int st_dev;\n\tlong unsigned int st_ino;\n\tshort unsigned int st_mode;\n\tshort unsigned int st_nlink;\n\tshort unsigned int st_uid;\n\tshort unsigned int st_gid;\n\tlong unsigned int st_rdev;\n\tlong unsigned int st_size;\n\tlong unsigned int st_blksize;\n\tlong unsigned int st_blocks;\n\tlong unsigned int st_atime;\n\tlong unsigned int st_atime_nsec;\n\tlong unsigned int st_mtime;\n\tlong unsigned int st_mtime_nsec;\n\tlong unsigned int st_ctime;\n\tlong unsigned int st_ctime_nsec;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct stat64 {\n\tlong long unsigned int st_dev;\n\tunsigned char __pad0[4];\n\tlong unsigned int __st_ino;\n\tunsigned int st_mode;\n\tunsigned int st_nlink;\n\tlong unsigned int st_uid;\n\tlong unsigned int st_gid;\n\tlong long unsigned int st_rdev;\n\tunsigned char __pad3[4];\n\tlong: 32;\n\tlong long int st_size;\n\tlong unsigned int st_blksize;\n\tlong: 32;\n\tlong long unsigned int st_blocks;\n\tlong unsigned int st_atime;\n\tlong unsigned int st_atime_nsec;\n\tlong unsigned int st_mtime;\n\tlong unsigned int st_mtime_nsec;\n\tlong unsigned int st_ctime;\n\tlong unsigned int st_ctime_nsec;\n\tlong long unsigned int st_ino;\n};\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct tracer_stat;\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct statfs {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u32 f_blocks;\n\t__u32 f_bfree;\n\t__u32 f_bavail;\n\t__u32 f_files;\n\t__u32 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_frsize;\n\t__u32 f_flags;\n\t__u32 f_spare[4];\n};\n\nstruct statfs64 {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_frsize;\n\t__u32 f_flags;\n\t__u32 f_spare[4];\n};\n\nstruct static_call_key {\n\tvoid *func;\n};\n\nstruct static_dep_map {\n\tconst char *from;\n\tconst char *to;\n};\n\nstruct static_key {\n\tatomic_t enabled;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct static_tree_desc_s {\n\tconst ct_data *static_tree;\n\tconst int *extra_bits;\n\tint extra_base;\n\tint elems;\n\tint max_length;\n};\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct static_vm {\n\tstruct vm_struct vm;\n\tstruct list_head list;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong: 32;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n\tlong: 32;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct stedma40_platform_data {\n\tint disabled_channels[32];\n\tint *soft_lli_chans;\n\tint num_of_soft_lli_chans;\n\tbool use_esram_lcla;\n\tint num_of_memcpy_chans;\n\tint num_of_phy_chans;\n};\n\nstruct stereo_mandatory_mode {\n\tint width;\n\tint height;\n\tint vrefresh;\n\tunsigned int flags;\n};\n\nstruct sti_cpt_ddata {\n\tu32 snapshot[3];\n\tunsigned int index;\n\tstruct mutex lock;\n\twait_queue_head_t wait;\n};\n\nstruct sti_dwmac {\n\tphy_interface_t interface;\n\tbool ext_phyclk;\n\tu32 tx_retime_src;\n\tstruct clk *clk;\n\tu32 ctrl_reg;\n\tint clk_sel_reg;\n\tstruct regmap *regmap;\n\tbool gmac_en;\n\tint speed;\n\tvoid (*fix_retime_src)(void *, int, unsigned int);\n};\n\nstruct sti_dwmac_of_data {\n\tvoid (*fix_retime_src)(void *, int, unsigned int);\n};\n\nstruct sti_pwm_chip {\n\tstruct device *dev;\n\tstruct clk *pwm_clk;\n\tstruct clk *cpt_clk;\n\tstruct regmap *regmap;\n\tunsigned int pwm_num_devs;\n\tunsigned int cpt_num_devs;\n\tunsigned int max_pwm_cnt;\n\tunsigned int max_prescale;\n\tstruct sti_cpt_ddata *ddata;\n\tstruct regmap_field *prescale_low;\n\tstruct regmap_field *prescale_high;\n\tstruct regmap_field *pwm_out_en;\n\tstruct regmap_field *pwm_cpt_en;\n\tstruct regmap_field *pwm_cpt_int_en;\n\tstruct regmap_field *pwm_cpt_int_stat;\n\tstruct pwm_device *cur;\n\tlong unsigned int configured;\n\tunsigned int en_count;\n\tvoid *mmio;\n};\n\nstruct stih407_usb2_picophy {\n\tstruct phy *phy;\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tstruct reset_control *rstc;\n\tstruct reset_control *rstport;\n\tint ctrl;\n\tint param;\n};\n\nstruct stm32_cktim_cfg {\n\tu32 offset_apbdiv;\n\tu32 offset_timpre;\n};\n\nstruct stm32_mgate;\n\nstruct stm32_clk_mgate {\n\tstruct clk_gate gate;\n\tstruct stm32_mgate *mgate;\n\tu32 mask;\n};\n\nstruct stm32_mmux;\n\nstruct stm32_clk_mmux {\n\tstruct clk_mux mux;\n\tstruct stm32_mmux *mmux;\n};\n\nstruct stm32_gate_cfg___2;\n\nstruct stm32_div_cfg___2;\n\nstruct stm32_mux_cfg___2;\n\nstruct stm32_composite_cfg {\n\tconst struct stm32_gate_cfg___2 *gate;\n\tconst struct stm32_div_cfg___2 *div;\n\tconst struct stm32_mux_cfg___2 *mux;\n};\n\nstruct stm32_desc_function {\n\tconst char *name;\n\tconst unsigned char num;\n};\n\nstruct stm32_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tconst struct stm32_desc_function functions[19];\n\tconst unsigned int pkg;\n};\n\nstruct stm32_div_cfg {\n\tu16 offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tu8 ready;\n\tconst struct clk_div_table *table;\n};\n\nstruct stm32_div_cfg___2 {\n\tstruct div_cfg *div;\n\tconst struct clk_ops *ops;\n};\n\nstruct stm32_dma_cfg {\n\tu32 channel_id;\n\tu32 request_line;\n\tu32 stream_config;\n\tu32 features;\n};\n\nstruct stm32_dma_chan_reg {\n\tu32 dma_lisr;\n\tu32 dma_hisr;\n\tu32 dma_lifcr;\n\tu32 dma_hifcr;\n\tu32 dma_scr;\n\tu32 dma_sndtr;\n\tu32 dma_spar;\n\tu32 dma_sm0ar;\n\tu32 dma_sm1ar;\n\tu32 dma_sfcr;\n};\n\nstruct stm32_dma_mdma_config {\n\tu32 stream_id;\n\tu32 ifcr;\n\tu32 tcf;\n};\n\nstruct stm32_dma_desc;\n\nstruct stm32_dma_chan {\n\tstruct virt_dma_chan vchan;\n\tbool config_init;\n\tbool busy;\n\tu32 id;\n\tu32 irq;\n\tstruct stm32_dma_desc *desc;\n\tu32 next_sg;\n\tstruct dma_slave_config dma_sconfig;\n\tstruct stm32_dma_chan_reg chan_reg;\n\tu32 threshold;\n\tu32 mem_burst;\n\tu32 mem_width;\n\tenum dma_status status;\n\tbool trig_mdma;\n\tstruct stm32_dma_mdma_config mdma_config;\n};\n\nstruct stm32_dma_sg_req {\n\tu32 len;\n\tstruct stm32_dma_chan_reg chan_reg;\n};\n\nstruct stm32_dma_desc {\n\tstruct virt_dma_desc vdesc;\n\tbool cyclic;\n\tu32 num_sgs;\n\tstruct stm32_dma_sg_req sg_req[0];\n};\n\nstruct stm32_dma_device {\n\tstruct dma_device ddev;\n\tvoid *base;\n\tstruct clk *clk;\n\tbool mem2mem;\n\tstruct stm32_dma_chan chan[8];\n};\n\nstruct stm32_dmamux {\n\tu32 master;\n\tu32 request;\n\tu32 chan_id;\n};\n\nstruct stm32_dmamux_data {\n\tstruct dma_router dmarouter;\n\tstruct clk *clk;\n\tvoid *iomem;\n\tu32 dma_requests;\n\tu32 dmamux_requests;\n\tspinlock_t lock;\n\tlong unsigned int dma_inuse[1];\n\tu32 ccr[32];\n\tu32 dma_reqs[0];\n};\n\nstruct stm32_ops;\n\nstruct stm32_dwmac {\n\tstruct clk *clk_tx;\n\tstruct clk *clk_rx;\n\tstruct clk *clk_eth_ck;\n\tstruct clk *clk_ethstp;\n\tstruct clk *syscfg_clk;\n\tint ext_phyclk;\n\tint enable_eth_ck;\n\tint eth_clk_sel_reg;\n\tint eth_ref_clk_sel_reg;\n\tint irq_pwr_wakeup;\n\tu32 mode_reg;\n\tu32 mode_mask;\n\tstruct regmap *regmap;\n\tu32 speed;\n\tconst struct stm32_ops *ops;\n\tstruct device *dev;\n};\n\nstruct stm32_firewall_controller;\n\nstruct stm32_firewall {\n\tstruct stm32_firewall_controller *firewall_ctrl;\n\tu32 extra_args[5];\n\tconst char *entry;\n\tsize_t extra_args_size;\n\tu32 firewall_id;\n};\n\nstruct stm32_firewall_controller {\n\tconst char *name;\n\tstruct device *dev;\n\tvoid *mmio;\n\tstruct list_head entry;\n\tunsigned int type;\n\tunsigned int max_entries;\n\tint (*grant_access)(struct stm32_firewall_controller *, u32);\n\tvoid (*release_access)(struct stm32_firewall_controller *, u32);\n\tint (*grant_memory_range_access)(struct stm32_firewall_controller *, phys_addr_t, size_t);\n};\n\nstruct stm32_fmc2_ebi_data;\n\nstruct stm32_fmc2_ebi {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct regmap *regmap;\n\tconst struct stm32_fmc2_ebi_data *data;\n\tu8 bank_assigned;\n\tu8 sem_taken;\n\tbool access_granted;\n\tu32 bcr[4];\n\tu32 btr[4];\n\tu32 bwtr[4];\n\tu32 pcscntr;\n\tu32 cfgr;\n};\n\nstruct stm32_fmc2_prop;\n\nstruct stm32_fmc2_ebi_data {\n\tconst struct stm32_fmc2_prop *child_props;\n\tunsigned int nb_child_props;\n\tu32 fmc2_enable_reg;\n\tu32 fmc2_enable_bit;\n\tint (*nwait_used_by_ctrls)(struct stm32_fmc2_ebi *);\n\tvoid (*set_setup)(struct stm32_fmc2_ebi *);\n\tint (*save_setup)(struct stm32_fmc2_ebi *);\n\tint (*check_rif)(struct stm32_fmc2_ebi *, u32);\n\tvoid (*put_sems)(struct stm32_fmc2_ebi *);\n\tvoid (*get_sems)(struct stm32_fmc2_ebi *);\n};\n\nstruct stm32_fmc2_timings {\n\tu8 tclr;\n\tu8 tar;\n\tu8 thiz;\n\tu8 twait;\n\tu8 thold_mem;\n\tu8 tset_mem;\n\tu8 thold_att;\n\tu8 tset_att;\n};\n\nstruct stm32_fmc2_nand {\n\tstruct nand_chip chip;\n\tstruct gpio_desc *wp_gpio;\n\tstruct stm32_fmc2_timings timings;\n\tint ncs;\n\tint cs_used[4];\n};\n\nstruct stm32_fmc2_nfc_data;\n\nstruct stm32_fmc2_nfc {\n\tstruct nand_controller base;\n\tstruct stm32_fmc2_nand nand;\n\tstruct device *dev;\n\tstruct device *cdev;\n\tstruct regmap *regmap;\n\tvoid *data_base[4];\n\tvoid *cmd_base[4];\n\tvoid *addr_base[4];\n\tphys_addr_t io_phys_addr;\n\tphys_addr_t data_phys_addr[4];\n\tstruct clk *clk;\n\tu8 irq_state;\n\tconst struct stm32_fmc2_nfc_data *data;\n\tstruct dma_chan *dma_tx_ch;\n\tstruct dma_chan *dma_rx_ch;\n\tstruct dma_chan *dma_ecc_ch;\n\tstruct sg_table dma_data_sg;\n\tstruct sg_table dma_ecc_sg;\n\tu8 *ecc_buf;\n\tdma_addr_t dma_ecc_addr;\n\tint dma_ecc_len;\n\tu32 tx_dma_max_burst;\n\tu32 rx_dma_max_burst;\n\tstruct completion complete;\n\tstruct completion dma_data_complete;\n\tstruct completion dma_ecc_complete;\n\tu8 cs_assigned;\n\tint cs_sel;\n\tlong: 32;\n};\n\nstruct stm32_fmc2_nfc_data {\n\tint max_ncs;\n\tint (*set_cdev)(struct stm32_fmc2_nfc *);\n};\n\nstruct stm32_fmc2_prop {\n\tconst char *name;\n\tbool bprop;\n\tbool mprop;\n\tint reg_type;\n\tu32 reg_mask;\n\tu32 reset_val;\n\tint (*check)(struct stm32_fmc2_ebi *, const struct stm32_fmc2_prop *, int);\n\tu32 (*calculate)(struct stm32_fmc2_ebi *, int, u32);\n\tint (*set)(struct stm32_fmc2_ebi *, const struct stm32_fmc2_prop *, int, u32);\n};\n\nstruct stm32_gate_cfg___2 {\n\tstruct gate_cfg *gate;\n\tstruct stm32_mgate *mgate;\n\tconst struct clk_ops *ops;\n};\n\nstruct stm32_gate_cfg {\n\tu16 offset;\n\tu8 bit_idx;\n\tu8 set_clr;\n};\n\nstruct stm32_pin_backup {\n\tunsigned int alt: 4;\n\tunsigned int mode: 2;\n\tunsigned int bias: 2;\n\tunsigned int speed: 2;\n\tunsigned int drive: 1;\n\tunsigned int value: 1;\n\tunsigned int advcfg: 4;\n\tunsigned int skew_delay: 4;\n};\n\nstruct stm32_gpio_bank {\n\tvoid *base;\n\tstruct reset_control *rstc;\n\tspinlock_t lock;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range range;\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *domain;\n\tu32 bank_nr;\n\tu32 bank_ioport_nr;\n\tstruct stm32_pin_backup pin_backup[16];\n\tu8 irq_type[16];\n\tbool secure_control;\n\tbool io_sync_control;\n\tbool rif_control;\n};\n\nstruct stm32_hdp {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct gpio_generic_chip gpio_chip;\n\tu32 mux_conf;\n\tu32 gposet_conf;\n\tconst char * const *func_name;\n};\n\nstruct stm32_i2c_dma {\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n\tstruct dma_chan *chan_using;\n\tdma_addr_t dma_buf;\n\tunsigned int dma_len;\n\tenum dma_transfer_direction dma_transfer_dir;\n\tenum dma_data_direction dma_data_dir;\n\tstruct completion dma_complete;\n};\n\nstruct stm32_iwdg_data;\n\nstruct stm32_iwdg {\n\tstruct watchdog_device wdd;\n\tconst struct stm32_iwdg_data *data;\n\tvoid *regs;\n\tstruct clk *clk_lsi;\n\tstruct clk *clk_pclk;\n\tunsigned int rate;\n};\n\nstruct stm32_iwdg_data {\n\tbool has_pclk;\n\tbool has_early_wakeup;\n\tu32 max_prescaler;\n};\n\nstruct stm32_mdma_chan_config {\n\tu32 request;\n\tu32 priority_level;\n\tu32 transfer_config;\n\tu32 mask_addr;\n\tu32 mask_data;\n\tbool m2m_hw;\n};\n\nstruct stm32_mdma_desc;\n\nstruct stm32_mdma_chan {\n\tstruct virt_dma_chan vchan;\n\tstruct dma_pool *desc_pool;\n\tu32 id;\n\tstruct stm32_mdma_desc *desc;\n\tu32 curr_hwdesc;\n\tstruct dma_slave_config dma_config;\n\tstruct stm32_mdma_chan_config chan_config;\n\tbool busy;\n\tu32 mem_burst;\n\tu32 mem_width;\n};\n\nstruct stm32_mdma_hwdesc;\n\nstruct stm32_mdma_desc_node {\n\tstruct stm32_mdma_hwdesc *hwdesc;\n\tdma_addr_t hwdesc_phys;\n};\n\nstruct stm32_mdma_desc {\n\tstruct virt_dma_desc vdesc;\n\tu32 ccr;\n\tbool cyclic;\n\tu32 count;\n\tstruct stm32_mdma_desc_node node[0];\n};\n\nstruct stm32_mdma_device {\n\tstruct dma_device ddev;\n\tvoid *base;\n\tstruct clk *clk;\n\tint irq;\n\tu32 nr_channels;\n\tu32 nr_requests;\n\tu32 nr_ahb_addr_masks;\n\tu32 chan_reserved;\n\tstruct stm32_mdma_chan chan[32];\n\tu32 ahb_addr_masks[0];\n};\n\nstruct stm32_mdma_dma_config {\n\tu32 request;\n\tu32 cmar;\n\tu32 cmdr;\n};\n\nstruct stm32_mdma_hwdesc {\n\tu32 ctcr;\n\tu32 cbndtr;\n\tu32 csar;\n\tu32 cdar;\n\tu32 cbrur;\n\tu32 clar;\n\tu32 ctbr;\n\tu32 dummy;\n\tu32 cmar;\n\tu32 cmdr;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stm32_mgate {\n\tu8 nbr_clk;\n\tu32 flag;\n};\n\nstruct stm32_mmux {\n\tu8 nbr_clk;\n\tstruct clk_hw *hws[2];\n};\n\nstruct stm32_mux_cfg___2 {\n\tstruct mux_cfg *mux;\n\tstruct stm32_mmux *mmux;\n\tconst struct clk_ops *ops;\n};\n\nstruct stm32_mux_cfg {\n\tu16 offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tu32 *table;\n\tu8 ready;\n};\n\nstruct stm32_ops {\n\tint (*set_mode)(struct plat_stmmacenet_data *);\n\tint (*suspend)(struct stm32_dwmac *);\n\tvoid (*resume)(struct stm32_dwmac *);\n\tint (*parse_data)(struct stm32_dwmac *, struct device *);\n\tbool clk_rx_enable_in_suspend;\n\tbool is_mp13;\n\tbool is_mp2;\n\tu32 syscfg_clr_off;\n};\n\nstruct stm32_pinctrl_group;\n\nstruct stm32_pinctrl_match_data;\n\nstruct stm32_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct stm32_pinctrl_group *groups;\n\tunsigned int ngroups;\n\tconst char **grp_names;\n\tstruct stm32_gpio_bank *banks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int nbanks;\n\tconst struct stm32_pinctrl_match_data *match_data;\n\tstruct irq_domain *domain;\n\tstruct regmap *regmap;\n\tstruct regmap_field *irqmux[16];\n\tstruct hwspinlock *hwlock;\n\tstruct stm32_desc_pin *pins;\n\tu32 npins;\n\tu32 pkg;\n\tu16 irqmux_map;\n\tspinlock_t irqmux_lock;\n};\n\nstruct stm32_pinctrl_group {\n\tconst char *name;\n\tlong unsigned int config;\n\tunsigned int pin;\n};\n\nstruct stm32_pinctrl_match_data {\n\tconst struct stm32_desc_pin *pins;\n\tconst unsigned int npins;\n\tbool secure_control;\n\tbool io_sync_control;\n\tbool rif_control;\n};\n\nstruct stm32_pll_cfg {\n\tu32 offset;\n\tu32 muxoff;\n};\n\nstruct stm32_pll_obj {\n\tspinlock_t *lock;\n\tvoid *reg;\n\tstruct clk_hw hw;\n\tstruct clk_mux mux;\n};\n\nstruct stm32_usart_info;\n\nstruct stm32_port {\n\tstruct uart_port port;\n\tstruct clk *clk;\n\tconst struct stm32_usart_info *info;\n\tstruct dma_chan *rx_ch;\n\tdma_addr_t rx_dma_buf;\n\tunsigned char *rx_buf;\n\tstruct dma_chan *tx_ch;\n\tdma_addr_t tx_dma_buf;\n\tunsigned char *tx_buf;\n\tu32 cr1_irq;\n\tu32 cr3_irq;\n\tint last_res;\n\tbool tx_dma_busy;\n\tbool rx_dma_busy;\n\tbool throttled;\n\tbool hw_flow_control;\n\tbool swap;\n\tbool fifoen;\n\tint rxftcfg;\n\tint txftcfg;\n\tbool wakeup_src;\n\tint rdr_mask;\n\tstruct mctrl_gpios *gpios;\n\tstruct dma_tx_state rx_dma_state;\n};\n\nstruct stm32_pwr_reg {\n\tvoid *base;\n\tu32 ready_mask;\n};\n\nstruct stm32_qspi_flash {\n\tu32 cs;\n\tu32 presc;\n};\n\nstruct stm32_qspi {\n\tstruct device *dev;\n\tstruct spi_controller *ctrl;\n\tphys_addr_t phys_base;\n\tvoid *io_base;\n\tvoid *mm_base;\n\tresource_size_t mm_size;\n\tstruct clk *clk;\n\tu32 clk_rate;\n\tstruct stm32_qspi_flash flash[2];\n\tstruct completion match_completion;\n\tu32 fmode;\n\tstruct dma_chan *dma_chtx;\n\tstruct dma_chan *dma_chrx;\n\tstruct completion dma_completion;\n\tu32 cr_reg;\n\tu32 dcr_reg;\n\tlong unsigned int status_timeout;\n\tstruct mutex lock;\n};\n\nstruct stm32_rcc_match_data {\n\tstruct clk_hw_onecell_data *hw_clks;\n\tunsigned int num_clocks;\n\tconst struct clock_config *tab_clocks;\n\tunsigned int maxbinding;\n\tstruct clk_stm32_clock_data *clock_data;\n\tstruct clk_stm32_reset_data *reset_data;\n\tint (*check_security)(struct device_node *, void *, const struct clock_config *);\n\tint (*multi_mux)(void *, const struct clock_config *);\n};\n\nstruct stm32_rcc_match_data___2 {\n\tconst struct clock_config___2 *cfg;\n\tunsigned int num;\n\tunsigned int maxbinding;\n\tstruct clk_stm32_reset_data *reset_data;\n\tbool (*check_security)(const struct clock_config___2 *);\n};\n\nstruct stm32_reset_cfg {\n\tu16 offset;\n\tu8 bit_idx;\n\tbool set_clr;\n};\n\nstruct stm32_reset_data {\n\tspinlock_t lock;\n\tstruct reset_controller_dev rcdev;\n\tvoid *membase;\n\tu32 clear_offset;\n\tconst struct stm32_reset_cfg **reset_lines;\n};\n\nstruct stm32_rifsc_resources_names {\n\tconst char **device_names;\n\tconst char **initiator_names;\n};\n\nstruct stm32_rng_config {\n\tu32 cr;\n\tu32 nscr;\n\tu32 htcr;\n};\n\nstruct stm32_rng_data {\n\tuint max_clock_rate;\n\tuint nb_clock;\n\tu32 cr;\n\tu32 nscr;\n\tu32 htcr;\n\tbool has_cond_reset;\n};\n\nstruct stm32_rng_private {\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk_bulk_data *clk_bulk;\n\tstruct reset_control *rst;\n\tstruct stm32_rng_config pm_conf;\n\tconst struct stm32_rng_data *data;\n\tbool ced;\n\tbool lock_conf;\n};\n\nstruct stm32_rtc_data;\n\nstruct stm32_rtc {\n\tstruct rtc_device *rtc_dev;\n\tvoid *base;\n\tstruct regmap *dbp;\n\tunsigned int dbp_reg;\n\tunsigned int dbp_mask;\n\tstruct clk *pclk;\n\tstruct clk *rtc_ck;\n\tconst struct stm32_rtc_data *data;\n\tint irq_alarm;\n\tstruct clk *clk_lsco;\n};\n\nstruct stm32_rtc_registers {\n\tu16 tr;\n\tu16 dr;\n\tu16 cr;\n\tu16 isr;\n\tu16 prer;\n\tu16 alrmar;\n\tu16 wpr;\n\tu16 sr;\n\tu16 scr;\n\tu16 cfgr;\n\tu16 verr;\n};\n\nstruct stm32_rtc_events {\n\tu32 alra;\n};\n\nstruct stm32_rtc_data {\n\tconst struct stm32_rtc_registers regs;\n\tconst struct stm32_rtc_events events;\n\tvoid (*clear_events)(struct stm32_rtc *, unsigned int);\n\tbool has_pclk;\n\tbool need_dbp;\n\tbool need_accuracy;\n\tbool rif_protected;\n\tbool has_lsco;\n\tbool has_alarm_out;\n};\n\nstruct stm32_rtc_pinmux_func {\n\tconst char *name;\n\tconst char * const *groups;\n\tconst unsigned int num_groups;\n\tint (*action)(struct pinctrl_dev *, unsigned int);\n};\n\nstruct stm32_rtc_rif_resource {\n\tunsigned int num;\n\tu32 bit;\n};\n\nstruct stm32_timer_private {\n\tint bits;\n};\n\nstruct stm32_usart_config {\n\tu8 uart_enable_bit;\n\tbool has_7bits_data;\n\tbool has_swap;\n\tbool has_wakeup;\n\tbool has_fifo;\n};\n\nstruct stm32_usart_offsets {\n\tu16 cr1;\n\tu16 cr2;\n\tu16 cr3;\n\tu16 brr;\n\tu16 gtpr;\n\tu16 rtor;\n\tu16 rqr;\n\tu16 isr;\n\tu16 icr;\n\tu16 rdr;\n\tu16 tdr;\n\tu16 presc;\n\tu16 hwcfgr1;\n};\n\nstruct stm32_usart_info {\n\tstruct stm32_usart_offsets ofs;\n\tstruct stm32_usart_config cfg;\n};\n\nstruct stm32_usart_thresh_ratio {\n\tint mul;\n\tint div;\n};\n\nstruct stm32_usbphyc_phy;\n\nstruct stm32_usbphyc {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tstruct stm32_usbphyc_phy **phys;\n\tint nphys;\n\tstruct regulator *vdda1v1;\n\tstruct regulator *vdda1v8;\n\tatomic_t n_pll_cons;\n\tstruct clk_hw clk48_hw;\n\tint switch_setup;\n};\n\nstruct stm32_usbphyc_phy {\n\tstruct phy *phy;\n\tstruct stm32_usbphyc *usbphyc;\n\tstruct regulator *vbus;\n\tu32 index;\n\tbool active;\n\tu32 tune;\n};\n\nstruct stm32f7_i2c_alert {\n\tstruct i2c_smbus_alert_setup setup;\n\tstruct i2c_client *ara;\n};\n\nstruct stm32f7_i2c_msg {\n\tu16 addr;\n\tu32 count;\n\tu8 *buf;\n\tint result;\n\tbool stop;\n\tbool smbus;\n\tint size;\n\tchar read_write;\n\tlong: 0;\n\tu8 smbus_buf[35];\n};\n\nstruct stm32f7_i2c_setup {\n\tu32 speed_freq;\n\tu32 clock_src;\n\tu32 rise_time;\n\tu32 fall_time;\n\tu32 fmp_clr_offset;\n\tbool single_it_line;\n\tbool fmp_cr1_bit;\n};\n\nstruct stm32f7_i2c_timings {\n\tstruct list_head node;\n\tu8 presc;\n\tu8 scldel;\n\tu8 sdadel;\n\tu8 sclh;\n\tu8 scll;\n};\n\nstruct stm32f7_i2c_regs {\n\tu32 cr1;\n\tu32 cr2;\n\tu32 oar1;\n\tu32 oar2;\n\tu32 tmgr;\n};\n\nstruct stm32f7_i2c_dev {\n\tstruct i2c_adapter adap;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct completion complete;\n\tstruct clk *clk;\n\tunsigned int bus_rate;\n\tstruct i2c_msg *msg;\n\tunsigned int msg_num;\n\tunsigned int msg_id;\n\tstruct stm32f7_i2c_msg f7_msg;\n\tstruct stm32f7_i2c_setup setup;\n\tstruct stm32f7_i2c_timings timing;\n\tstruct i2c_client *slave[3];\n\tstruct i2c_client *slave_running;\n\tstruct stm32f7_i2c_regs backup_regs;\n\tu32 slave_dir;\n\tbool master_mode;\n\tstruct stm32_i2c_dma *dma;\n\tbool use_dma;\n\tstruct regmap *regmap;\n\tu32 fmp_sreg;\n\tu32 fmp_creg;\n\tu32 fmp_mask;\n\tbool wakeup_src;\n\tbool smbus_mode;\n\tstruct i2c_client *host_notify_client;\n\tbool analog_filter;\n\tu32 dnf_dt;\n\tu32 dnf;\n\tstruct stm32f7_i2c_alert *alert;\n\tbool atomic;\n\tlong: 32;\n};\n\nstruct stm32f7_i2c_spec {\n\tu32 rate;\n\tu32 fall_max;\n\tu32 rise_max;\n\tu32 hddat_min;\n\tu32 vddat_max;\n\tu32 sudat_min;\n\tu32 l_min;\n\tu32 h_min;\n};\n\nstruct stm32mp_exti_bank {\n\tu32 imr_ofst;\n\tu32 rtsr_ofst;\n\tu32 ftsr_ofst;\n\tu32 swier_ofst;\n\tu32 rpr_ofst;\n\tu32 fpr_ofst;\n\tu32 trg_ofst;\n\tu32 seccfgr_ofst;\n};\n\nstruct stm32mp_exti_host_data;\n\nstruct stm32mp_exti_chip_data {\n\tstruct stm32mp_exti_host_data *host_data;\n\tconst struct stm32mp_exti_bank *reg_bank;\n\tstruct raw_spinlock rlock;\n\tu32 wake_active;\n\tu32 mask_cache;\n\tu32 rtsr_cache;\n\tu32 ftsr_cache;\n\tu32 event_reserved;\n};\n\nstruct stm32mp_exti_drv_data {\n\tconst struct stm32mp_exti_bank **exti_banks;\n\tconst u8 *desc_irqs;\n\tu32 bank_nr;\n};\n\nstruct stm32mp_exti_host_data {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct stm32mp_exti_chip_data *chips_data;\n\tconst struct stm32mp_exti_drv_data *drv_data;\n\tstruct hwspinlock *hwlock;\n\tbool dt_has_irqs_desc;\n};\n\nstruct stm_fs {\n\tlong unsigned int ndiv;\n\tlong unsigned int mdiv;\n\tlong unsigned int pe;\n\tlong unsigned int sdiv;\n\tlong unsigned int nsdiv;\n};\n\nstruct stm_pll {\n\tlong unsigned int mdiv;\n\tlong unsigned int ndiv;\n\tlong unsigned int pdiv;\n\tlong unsigned int odf;\n\tlong unsigned int idf;\n\tlong unsigned int ldf;\n\tlong unsigned int cp;\n};\n\nstruct stm_thermal_sensor {\n\tstruct device *dev;\n\tstruct thermal_zone_device *th_dev;\n\tenum thermal_device_mode mode;\n\tstruct clk *clk;\n\tunsigned int low_temp_enabled;\n\tunsigned int high_temp_enabled;\n\tint irq;\n\tvoid *base;\n\tint t0;\n\tint fmt0;\n\tint ramp_coeff;\n};\n\nstruct stmfx {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct regulator *vdd;\n\tint irq;\n\tstruct irq_domain *irq_domain;\n\tstruct mutex lock;\n\tu8 irq_src;\n\tu8 bkp_sysctrl;\n\tu8 bkp_irqoutpin;\n};\n\nstruct stmfx_pinctrl {\n\tstruct device *dev;\n\tstruct stmfx *stmfx;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct gpio_chip gpio_chip;\n\tstruct mutex lock;\n\tlong unsigned int gpio_valid_mask;\n\tu8 irq_gpi_src[3];\n\tu8 irq_gpi_type[3];\n\tu8 irq_gpi_evt[3];\n\tu8 irq_toggle_edge[3];\n\tu8 bkp_gpio_state[3];\n\tu8 bkp_gpio_dir[3];\n\tu8 bkp_gpio_type[3];\n\tu8 bkp_gpio_pupd[3];\n};\n\nstruct stmmac_axi {\n\tbool axi_lpi_en;\n\tbool axi_xit_frm;\n\tu32 axi_wr_osr_lmt;\n\tu32 axi_rd_osr_lmt;\n\tbool axi_kbbe;\n\tu32 axi_blen_regval;\n\tbool axi_fb;\n\tbool axi_mb;\n\tbool axi_rb;\n};\n\nstruct stmmac_channel {\n\tstruct napi_struct rx_napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct napi_struct tx_napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct napi_struct rxtx_napi;\n\tstruct stmmac_priv *priv_data;\n\tspinlock_t lock;\n\tu32 index;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_counters {\n\tunsigned int mmc_tx_octetcount_gb;\n\tunsigned int mmc_tx_framecount_gb;\n\tunsigned int mmc_tx_broadcastframe_g;\n\tunsigned int mmc_tx_multicastframe_g;\n\tunsigned int mmc_tx_64_octets_gb;\n\tunsigned int mmc_tx_65_to_127_octets_gb;\n\tunsigned int mmc_tx_128_to_255_octets_gb;\n\tunsigned int mmc_tx_256_to_511_octets_gb;\n\tunsigned int mmc_tx_512_to_1023_octets_gb;\n\tunsigned int mmc_tx_1024_to_max_octets_gb;\n\tunsigned int mmc_tx_unicast_gb;\n\tunsigned int mmc_tx_multicast_gb;\n\tunsigned int mmc_tx_broadcast_gb;\n\tunsigned int mmc_tx_underflow_error;\n\tunsigned int mmc_tx_singlecol_g;\n\tunsigned int mmc_tx_multicol_g;\n\tunsigned int mmc_tx_deferred;\n\tunsigned int mmc_tx_latecol;\n\tunsigned int mmc_tx_exesscol;\n\tunsigned int mmc_tx_carrier_error;\n\tunsigned int mmc_tx_octetcount_g;\n\tunsigned int mmc_tx_framecount_g;\n\tunsigned int mmc_tx_excessdef;\n\tunsigned int mmc_tx_pause_frame;\n\tunsigned int mmc_tx_vlan_frame_g;\n\tunsigned int mmc_tx_oversize_g;\n\tunsigned int mmc_tx_lpi_usec;\n\tunsigned int mmc_tx_lpi_tran;\n\tunsigned int mmc_rx_framecount_gb;\n\tunsigned int mmc_rx_octetcount_gb;\n\tunsigned int mmc_rx_octetcount_g;\n\tunsigned int mmc_rx_broadcastframe_g;\n\tunsigned int mmc_rx_multicastframe_g;\n\tunsigned int mmc_rx_crc_error;\n\tunsigned int mmc_rx_align_error;\n\tunsigned int mmc_rx_run_error;\n\tunsigned int mmc_rx_jabber_error;\n\tunsigned int mmc_rx_undersize_g;\n\tunsigned int mmc_rx_oversize_g;\n\tunsigned int mmc_rx_64_octets_gb;\n\tunsigned int mmc_rx_65_to_127_octets_gb;\n\tunsigned int mmc_rx_128_to_255_octets_gb;\n\tunsigned int mmc_rx_256_to_511_octets_gb;\n\tunsigned int mmc_rx_512_to_1023_octets_gb;\n\tunsigned int mmc_rx_1024_to_max_octets_gb;\n\tunsigned int mmc_rx_unicast_g;\n\tunsigned int mmc_rx_length_error;\n\tunsigned int mmc_rx_autofrangetype;\n\tunsigned int mmc_rx_pause_frames;\n\tunsigned int mmc_rx_fifo_overflow;\n\tunsigned int mmc_rx_vlan_frames_gb;\n\tunsigned int mmc_rx_watchdog_error;\n\tunsigned int mmc_rx_error;\n\tunsigned int mmc_rx_lpi_usec;\n\tunsigned int mmc_rx_lpi_tran;\n\tunsigned int mmc_rx_discard_frames_gb;\n\tunsigned int mmc_rx_discard_octets_gb;\n\tunsigned int mmc_rx_align_err_frames;\n\tunsigned int mmc_rx_ipv4_gd;\n\tunsigned int mmc_rx_ipv4_hderr;\n\tunsigned int mmc_rx_ipv4_nopay;\n\tunsigned int mmc_rx_ipv4_frag;\n\tunsigned int mmc_rx_ipv4_udsbl;\n\tunsigned int mmc_rx_ipv4_gd_octets;\n\tunsigned int mmc_rx_ipv4_hderr_octets;\n\tunsigned int mmc_rx_ipv4_nopay_octets;\n\tunsigned int mmc_rx_ipv4_frag_octets;\n\tunsigned int mmc_rx_ipv4_udsbl_octets;\n\tunsigned int mmc_rx_ipv6_gd_octets;\n\tunsigned int mmc_rx_ipv6_hderr_octets;\n\tunsigned int mmc_rx_ipv6_nopay_octets;\n\tunsigned int mmc_rx_ipv6_gd;\n\tunsigned int mmc_rx_ipv6_hderr;\n\tunsigned int mmc_rx_ipv6_nopay;\n\tunsigned int mmc_rx_udp_gd;\n\tunsigned int mmc_rx_udp_err;\n\tunsigned int mmc_rx_tcp_gd;\n\tunsigned int mmc_rx_tcp_err;\n\tunsigned int mmc_rx_icmp_gd;\n\tunsigned int mmc_rx_icmp_err;\n\tunsigned int mmc_rx_udp_gd_octets;\n\tunsigned int mmc_rx_udp_err_octets;\n\tunsigned int mmc_rx_tcp_gd_octets;\n\tunsigned int mmc_rx_tcp_err_octets;\n\tunsigned int mmc_rx_icmp_gd_octets;\n\tunsigned int mmc_rx_icmp_err_octets;\n\tunsigned int mmc_sgf_pass_fragment_cntr;\n\tunsigned int mmc_sgf_fail_fragment_cntr;\n\tunsigned int mmc_tx_fpe_fragment_cntr;\n\tunsigned int mmc_tx_hold_req_cntr;\n\tunsigned int mmc_tx_gate_overrun_cntr;\n\tunsigned int mmc_rx_packet_assembly_err_cntr;\n\tunsigned int mmc_rx_packet_smd_err_cntr;\n\tunsigned int mmc_rx_packet_assembly_ok_cntr;\n\tunsigned int mmc_rx_fpe_fragment_cntr;\n};\n\nstruct stmmac_extra_stats;\n\nstruct stmmac_desc_ops {\n\tvoid (*init_rx_desc)(struct dma_desc *, int, int, int, int);\n\tvoid (*init_tx_desc)(struct dma_desc *, int, int);\n\tvoid (*prepare_tx_desc)(struct dma_desc *, int, int, bool, int, bool, bool, unsigned int);\n\tvoid (*prepare_tso_tx_desc)(struct dma_desc *, int, int, int, bool, bool, unsigned int, unsigned int);\n\tvoid (*set_tx_owner)(struct dma_desc *);\n\tint (*get_tx_owner)(struct dma_desc *);\n\tvoid (*release_tx_desc)(struct dma_desc *, int);\n\tvoid (*set_tx_ic)(struct dma_desc *);\n\tint (*get_tx_ls)(struct dma_desc *);\n\tu16 (*get_rx_vlan_tci)(struct dma_desc *);\n\tbool (*get_rx_vlan_valid)(struct dma_desc *);\n\tint (*tx_status)(struct stmmac_extra_stats *, struct dma_desc *, void *);\n\tint (*get_tx_len)(struct dma_desc *);\n\tvoid (*set_rx_owner)(struct dma_desc *, int);\n\tint (*get_rx_frame_len)(struct dma_desc *, int);\n\tint (*rx_status)(struct stmmac_extra_stats *, struct dma_desc *);\n\tvoid (*rx_extended_status)(struct stmmac_extra_stats *, struct dma_extended_desc *);\n\tvoid (*enable_tx_timestamp)(struct dma_desc *);\n\tint (*get_tx_timestamp_status)(struct dma_desc *);\n\tvoid (*get_timestamp)(void *, u32, u64 *);\n\tint (*get_rx_timestamp_status)(void *, void *, u32);\n\tvoid (*display_ring)(void *, unsigned int, bool, dma_addr_t, unsigned int);\n\tvoid (*set_mss)(struct dma_desc *, unsigned int);\n\tvoid (*set_addr)(struct dma_desc *, dma_addr_t);\n\tvoid (*clear)(struct dma_desc *);\n\tint (*get_rx_hash)(struct dma_desc *, u32 *, enum pkt_hash_types *);\n\tvoid (*get_rx_header_len)(struct dma_desc *, unsigned int *);\n\tvoid (*set_sec_addr)(struct dma_desc *, dma_addr_t, bool);\n\tvoid (*set_sarc)(struct dma_desc *, u32);\n\tvoid (*set_vlan_tag)(struct dma_desc *, u16, u16, u32);\n\tvoid (*set_vlan)(struct dma_desc *, u32);\n\tvoid (*set_tbs)(struct dma_edesc *, u32, u32);\n};\n\nstruct stmmac_devlink_priv {\n\tstruct stmmac_priv *stmmac_priv;\n};\n\nstruct stmmac_dma_cfg {\n\tint pbl;\n\tint txpbl;\n\tint rxpbl;\n\tbool pblx8;\n\tint fixed_burst;\n\tint mixed_burst;\n\tbool aal;\n\tbool eame;\n\tbool multi_msi_en;\n\tbool dche;\n\tbool atds;\n};\n\nstruct stmmac_rx_buffer;\n\nstruct stmmac_rx_queue {\n\tu32 rx_count_frames;\n\tu32 queue_index;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct xsk_buff_pool *xsk_pool;\n\tstruct page_pool *page_pool;\n\tstruct stmmac_rx_buffer *buf_pool;\n\tstruct stmmac_priv *priv_data;\n\tstruct dma_extended_desc *dma_erx;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct dma_desc *dma_rx;\n\tunsigned int cur_rx;\n\tunsigned int dirty_rx;\n\tunsigned int buf_alloc_num;\n\tunsigned int napi_skb_frag_size;\n\tdma_addr_t dma_rx_phy;\n\tu32 rx_tail_addr;\n\tunsigned int state_saved;\n\tstruct {\n\t\tstruct sk_buff *skb;\n\t\tunsigned int len;\n\t\tunsigned int error;\n\t} state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_tx_info;\n\nstruct stmmac_tx_queue {\n\tu32 tx_count_frames;\n\tint tbs;\n\tstruct hrtimer txtimer;\n\tu32 queue_index;\n\tstruct stmmac_priv *priv_data;\n\tstruct dma_extended_desc *dma_etx;\n\tstruct dma_edesc *dma_entx;\n\tstruct dma_desc *dma_tx;\n\tunion {\n\t\tstruct sk_buff **tx_skbuff;\n\t\tstruct xdp_frame **xdpf;\n\t};\n\tstruct stmmac_tx_info *tx_skbuff_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tu32 xsk_frames_done;\n\tunsigned int cur_tx;\n\tunsigned int dirty_tx;\n\tdma_addr_t dma_tx_phy;\n\tdma_addr_t tx_tail_addr;\n\tu32 mss;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_dma_conf {\n\tunsigned int dma_buf_sz;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_rx_queue rx_queue[8];\n\tunsigned int dma_rx_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_tx_queue tx_queue[8];\n\tunsigned int dma_tx_size;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_dma_ops {\n\tint (*reset)(void *);\n\tvoid (*init)(void *, struct stmmac_dma_cfg *);\n\tvoid (*init_chan)(struct stmmac_priv *, void *, struct stmmac_dma_cfg *, u32);\n\tvoid (*init_rx_chan)(struct stmmac_priv *, void *, struct stmmac_dma_cfg *, dma_addr_t, u32);\n\tvoid (*init_tx_chan)(struct stmmac_priv *, void *, struct stmmac_dma_cfg *, dma_addr_t, u32);\n\tvoid (*axi)(void *, struct stmmac_axi *);\n\tvoid (*dump_regs)(struct stmmac_priv *, void *, u32 *);\n\tvoid (*dma_rx_mode)(struct stmmac_priv *, void *, int, u32, int, u8);\n\tvoid (*dma_tx_mode)(struct stmmac_priv *, void *, int, u32, int, u8);\n\tvoid (*dma_diagnostic_fr)(struct stmmac_extra_stats *, void *);\n\tvoid (*enable_dma_transmission)(void *, u32);\n\tvoid (*enable_dma_reception)(void *, u32);\n\tvoid (*enable_dma_irq)(struct stmmac_priv *, void *, u32, bool, bool);\n\tvoid (*disable_dma_irq)(struct stmmac_priv *, void *, u32, bool, bool);\n\tvoid (*start_tx)(struct stmmac_priv *, void *, u32);\n\tvoid (*stop_tx)(struct stmmac_priv *, void *, u32);\n\tvoid (*start_rx)(struct stmmac_priv *, void *, u32);\n\tvoid (*stop_rx)(struct stmmac_priv *, void *, u32);\n\tint (*dma_interrupt)(struct stmmac_priv *, void *, struct stmmac_extra_stats *, u32, u32);\n\tint (*get_hw_feature)(void *, struct dma_features *);\n\tvoid (*rx_watchdog)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_tx_ring_len)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_rx_ring_len)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_rx_tail_ptr)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*set_tx_tail_ptr)(struct stmmac_priv *, void *, u32, u32);\n\tvoid (*enable_tso)(struct stmmac_priv *, void *, bool, u32);\n\tvoid (*qmode)(struct stmmac_priv *, void *, u32, u8);\n\tvoid (*set_bfsize)(struct stmmac_priv *, void *, int, u32);\n\tvoid (*enable_sph)(struct stmmac_priv *, void *, bool, u32);\n\tint (*enable_tbs)(struct stmmac_priv *, void *, bool, u32);\n};\n\nstruct stmmac_est {\n\tint enable;\n\tu32 btr_reserve[2];\n\tu32 btr_offset[2];\n\tu32 btr[2];\n\tu32 ctr[2];\n\tu32 ter;\n\tu32 gcl_unaligned[1024];\n\tu32 gcl[1024];\n\tu32 gcl_size;\n\tu32 max_sdu[8];\n};\n\nstruct stmmac_est_ops {\n\tint (*configure)(struct stmmac_priv *, struct stmmac_est *, unsigned int);\n\tvoid (*irq_status)(struct stmmac_priv *, struct net_device *, struct stmmac_extra_stats *, u32);\n};\n\nstruct stmmac_q_tx_stats {\n\tu64_stats_t tx_bytes;\n\tu64_stats_t tx_set_ic_bit;\n\tu64_stats_t tx_tso_frames;\n\tu64_stats_t tx_tso_nfrags;\n};\n\nstruct stmmac_napi_tx_stats {\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_pkt_n;\n\tu64_stats_t poll;\n\tu64_stats_t tx_clean;\n\tu64_stats_t tx_set_ic_bit;\n};\n\nstruct stmmac_txq_stats {\n\tstruct u64_stats_sync q_syncp;\n\tlong: 32;\n\tstruct stmmac_q_tx_stats q;\n\tstruct u64_stats_sync napi_syncp;\n\tlong: 32;\n\tstruct stmmac_napi_tx_stats napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_napi_rx_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_pkt_n;\n\tu64_stats_t poll;\n};\n\nstruct stmmac_rxq_stats {\n\tstruct u64_stats_sync napi_syncp;\n\tlong: 32;\n\tstruct stmmac_napi_rx_stats napi;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_pcpu_stats;\n\nstruct stmmac_extra_stats {\n\tlong unsigned int tx_underflow;\n\tlong unsigned int tx_carrier;\n\tlong unsigned int tx_losscarrier;\n\tlong unsigned int vlan_tag;\n\tlong unsigned int tx_deferred;\n\tlong unsigned int tx_vlan;\n\tlong unsigned int tx_jabber;\n\tlong unsigned int tx_frame_flushed;\n\tlong unsigned int tx_payload_error;\n\tlong unsigned int tx_ip_header_error;\n\tlong unsigned int tx_collision;\n\tlong unsigned int rx_desc;\n\tlong unsigned int sa_filter_fail;\n\tlong unsigned int overflow_error;\n\tlong unsigned int ipc_csum_error;\n\tlong unsigned int rx_collision;\n\tlong unsigned int rx_crc_errors;\n\tlong unsigned int dribbling_bit;\n\tlong unsigned int rx_length;\n\tlong unsigned int rx_mii;\n\tlong unsigned int rx_multicast;\n\tlong unsigned int rx_gmac_overflow;\n\tlong unsigned int rx_watchdog;\n\tlong unsigned int da_rx_filter_fail;\n\tlong unsigned int sa_rx_filter_fail;\n\tlong unsigned int rx_missed_cntr;\n\tlong unsigned int rx_overflow_cntr;\n\tlong unsigned int rx_vlan;\n\tlong unsigned int rx_split_hdr_pkt_n;\n\tlong unsigned int tx_undeflow_irq;\n\tlong unsigned int tx_process_stopped_irq;\n\tlong unsigned int tx_jabber_irq;\n\tlong unsigned int rx_overflow_irq;\n\tlong unsigned int rx_buf_unav_irq;\n\tlong unsigned int rx_process_stopped_irq;\n\tlong unsigned int rx_watchdog_irq;\n\tlong unsigned int tx_early_irq;\n\tlong unsigned int fatal_bus_error_irq;\n\tlong unsigned int rx_early_irq;\n\tlong unsigned int threshold;\n\tlong unsigned int irq_receive_pmt_irq_n;\n\tlong unsigned int mmc_tx_irq_n;\n\tlong unsigned int mmc_rx_irq_n;\n\tlong unsigned int mmc_rx_csum_offload_irq_n;\n\tlong unsigned int irq_tx_path_in_lpi_mode_n;\n\tlong unsigned int irq_tx_path_exit_lpi_mode_n;\n\tlong unsigned int irq_rx_path_in_lpi_mode_n;\n\tlong unsigned int irq_rx_path_exit_lpi_mode_n;\n\tlong unsigned int phy_eee_wakeup_error_n;\n\tlong unsigned int ip_hdr_err;\n\tlong unsigned int ip_payload_err;\n\tlong unsigned int ip_csum_bypassed;\n\tlong unsigned int ipv4_pkt_rcvd;\n\tlong unsigned int ipv6_pkt_rcvd;\n\tlong unsigned int no_ptp_rx_msg_type_ext;\n\tlong unsigned int ptp_rx_msg_type_sync;\n\tlong unsigned int ptp_rx_msg_type_follow_up;\n\tlong unsigned int ptp_rx_msg_type_delay_req;\n\tlong unsigned int ptp_rx_msg_type_delay_resp;\n\tlong unsigned int ptp_rx_msg_type_pdelay_req;\n\tlong unsigned int ptp_rx_msg_type_pdelay_resp;\n\tlong unsigned int ptp_rx_msg_type_pdelay_follow_up;\n\tlong unsigned int ptp_rx_msg_type_announce;\n\tlong unsigned int ptp_rx_msg_type_management;\n\tlong unsigned int ptp_rx_msg_pkt_reserved_type;\n\tlong unsigned int ptp_frame_type;\n\tlong unsigned int ptp_ver;\n\tlong unsigned int timestamp_dropped;\n\tlong unsigned int av_pkt_rcvd;\n\tlong unsigned int av_tagged_pkt_rcvd;\n\tlong unsigned int vlan_tag_priority_val;\n\tlong unsigned int l3_filter_match;\n\tlong unsigned int l4_filter_match;\n\tlong unsigned int l3_l4_filter_no_match;\n\tlong unsigned int irq_pcs_ane_n;\n\tlong unsigned int irq_pcs_link_n;\n\tlong unsigned int irq_rgmii_n;\n\tlong unsigned int mtl_tx_status_fifo_full;\n\tlong unsigned int mtl_tx_fifo_not_empty;\n\tlong unsigned int mmtl_fifo_ctrl;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_write;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_wait;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_read;\n\tlong unsigned int mtl_tx_fifo_read_ctrl_idle;\n\tlong unsigned int mac_tx_in_pause;\n\tlong unsigned int mac_tx_frame_ctrl_xfer;\n\tlong unsigned int mac_tx_frame_ctrl_idle;\n\tlong unsigned int mac_tx_frame_ctrl_wait;\n\tlong unsigned int mac_tx_frame_ctrl_pause;\n\tlong unsigned int mac_gmii_tx_proto_engine;\n\tlong unsigned int mtl_rx_fifo_fill_level_full;\n\tlong unsigned int mtl_rx_fifo_fill_above_thresh;\n\tlong unsigned int mtl_rx_fifo_fill_below_thresh;\n\tlong unsigned int mtl_rx_fifo_fill_level_empty;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_flush;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_read_data;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_status;\n\tlong unsigned int mtl_rx_fifo_read_ctrl_idle;\n\tlong unsigned int mtl_rx_fifo_ctrl_active;\n\tlong unsigned int mac_rx_frame_ctrl_fifo;\n\tlong unsigned int mac_gmii_rx_proto_engine;\n\tlong unsigned int mtl_est_cgce;\n\tlong unsigned int mtl_est_hlbs;\n\tlong unsigned int mtl_est_hlbf;\n\tlong unsigned int mtl_est_btre;\n\tlong unsigned int mtl_est_btrlm;\n\tlong unsigned int max_sdu_txq_drop[8];\n\tlong unsigned int mtl_est_txq_hlbf[8];\n\tlong unsigned int mtl_est_txq_hlbs[8];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_txq_stats txq_stats[8];\n\tstruct stmmac_rxq_stats rxq_stats[8];\n\tstruct stmmac_pcpu_stats *pcpu_stats;\n\tlong unsigned int rx_dropped;\n\tlong unsigned int rx_errors;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int tx_errors;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_flow_entry {\n\tlong unsigned int cookie;\n\tlong unsigned int action;\n\tu8 ip_proto;\n\tint in_use;\n\tint idx;\n\tint is_l4;\n};\n\nstruct stmmac_fpe_reg;\n\nstruct stmmac_fpe_cfg {\n\tstruct ethtool_mmsv mmsv;\n\tconst struct stmmac_fpe_reg *reg;\n\tu32 fpe_csr;\n};\n\nstruct stmmac_fpe_reg {\n\tconst u32 mac_fpe_reg;\n\tconst u32 mtl_fpe_reg;\n\tconst u32 rxq_ctrl1_reg;\n\tconst u32 fprq_mask;\n\tconst u32 int_en_reg;\n\tconst u32 int_en_bit;\n};\n\nstruct stmmac_regs_off {\n\tconst struct stmmac_fpe_reg *fpe_reg;\n\tu32 ptp_off;\n\tu32 mmc_off;\n\tu32 est_off;\n};\n\nstruct stmmac_hwif_entry {\n\tenum dwmac_core_type core_type;\n\tu32 min_id;\n\tu32 dev_id;\n\tconst struct stmmac_regs_off regs;\n\tconst void *desc;\n\tconst void *dma;\n\tconst void *mac;\n\tconst void *hwtimestamp;\n\tconst void *ptp;\n\tconst void *mode;\n\tconst void *tc;\n\tconst void *mmc;\n\tconst void *est;\n\tconst void *vlan;\n\tint (*setup)(struct stmmac_priv *);\n\tint (*quirks)(struct stmmac_priv *);\n};\n\nstruct stmmac_hwtimestamp {\n\tvoid (*config_hw_tstamping)(void *, u32);\n\tvoid (*config_sub_second_increment)(void *, u32, int, u32 *);\n\tint (*init_systime)(void *, u32, u32);\n\tint (*config_addend)(void *, u32);\n\tint (*adjust_systime)(void *, u32, u32, int, int);\n\tvoid (*get_systime)(void *, u64 *);\n\tvoid (*get_ptptime)(void *, u64 *);\n\tvoid (*timestamp_interrupt)(struct stmmac_priv *);\n\tvoid (*hwtstamp_correct_latency)(struct stmmac_priv *);\n};\n\nstruct stmmac_mdio_bus_data {\n\tunsigned int phy_mask;\n\tunsigned int pcs_mask;\n\tunsigned int default_an_inband;\n\tint *irqs;\n\tint probed_phy_irq;\n\tbool needs_reset;\n};\n\nstruct stmmac_metadata_request {\n\tstruct stmmac_priv *priv;\n\tstruct dma_desc *tx_desc;\n\tbool *set_ic;\n\tstruct dma_edesc *edesc;\n\tint tbs;\n};\n\nstruct stmmac_mmc_ops {\n\tvoid (*ctrl)(void *, unsigned int);\n\tvoid (*intr_all_mask)(void *);\n\tvoid (*read)(void *, struct stmmac_counters *);\n};\n\nstruct stmmac_mode_ops {\n\tvoid (*init)(void *, dma_addr_t, unsigned int, unsigned int);\n\tbool (*is_jumbo_frm)(unsigned int, bool);\n\tint (*jumbo_frm)(struct stmmac_tx_queue *, struct sk_buff *, int);\n\tint (*set_16kib_bfsize)(int);\n\tvoid (*init_desc3)(struct dma_desc *);\n\tvoid (*refill_desc3)(struct stmmac_rx_queue *, struct dma_desc *);\n\tvoid (*clean_desc3)(struct stmmac_tx_queue *, struct dma_desc *);\n};\n\nstruct stmmac_safety_stats;\n\nstruct stmmac_tc_entry;\n\nstruct stmmac_pps_cfg;\n\nstruct stmmac_rss;\n\nstruct stmmac_ops {\n\tint (*pcs_init)(struct stmmac_priv *);\n\tvoid (*core_init)(struct mac_device_info *, struct net_device *);\n\tvoid (*update_caps)(struct stmmac_priv *);\n\tvoid (*irq_modify)(struct mac_device_info *, u32, u32);\n\tvoid (*set_mac)(void *, bool);\n\tint (*rx_ipc)(struct mac_device_info *);\n\tvoid (*rx_queue_enable)(struct mac_device_info *, u8, u32);\n\tvoid (*rx_queue_prio)(struct mac_device_info *, u32, u32);\n\tvoid (*tx_queue_prio)(struct mac_device_info *, u32, u32);\n\tvoid (*rx_queue_routing)(struct mac_device_info *, u8, u32);\n\tvoid (*prog_mtl_rx_algorithms)(struct mac_device_info *, u32);\n\tvoid (*prog_mtl_tx_algorithms)(struct mac_device_info *, u32);\n\tvoid (*set_mtl_tx_queue_weight)(struct stmmac_priv *, struct mac_device_info *, u32, u32);\n\tvoid (*map_mtl_to_dma)(struct mac_device_info *, u32, u32);\n\tvoid (*config_cbs)(struct stmmac_priv *, struct mac_device_info *, u32, u32, u32, u32, u32);\n\tvoid (*dump_regs)(struct mac_device_info *, u32 *);\n\tint (*host_irq_status)(struct stmmac_priv *, struct stmmac_extra_stats *);\n\tint (*host_mtl_irq_status)(struct stmmac_priv *, struct mac_device_info *, u32);\n\tvoid (*set_filter)(struct mac_device_info *, struct net_device *);\n\tvoid (*flow_ctrl)(struct mac_device_info *, unsigned int, unsigned int, unsigned int, u32);\n\tvoid (*pmt)(struct mac_device_info *, long unsigned int);\n\tvoid (*set_umac_addr)(struct mac_device_info *, const unsigned char *, unsigned int);\n\tvoid (*get_umac_addr)(struct mac_device_info *, unsigned char *, unsigned int);\n\tint (*set_lpi_mode)(struct mac_device_info *, enum stmmac_lpi_mode, bool, u32);\n\tvoid (*set_eee_timer)(struct mac_device_info *, int, int);\n\tvoid (*set_eee_pls)(struct mac_device_info *, int);\n\tvoid (*debug)(struct stmmac_priv *, void *, struct stmmac_extra_stats *, u32, u32);\n\tvoid (*pcs_ctrl_ane)(struct stmmac_priv *, bool, bool);\n\tint (*safety_feat_config)(void *, unsigned int, struct stmmac_safety_feature_cfg *);\n\tint (*safety_feat_irq_status)(struct net_device *, void *, unsigned int, struct stmmac_safety_stats *);\n\tint (*safety_feat_dump)(struct stmmac_safety_stats *, int, long unsigned int *, const char **);\n\tint (*rxp_config)(void *, struct stmmac_tc_entry *, unsigned int);\n\tint (*flex_pps_config)(void *, int, struct stmmac_pps_cfg *, bool, u32, u32);\n\tvoid (*set_mac_loopback)(void *, bool);\n\tint (*rss_configure)(struct mac_device_info *, struct stmmac_rss *, u32);\n\tint (*get_mac_tx_timestamp)(struct mac_device_info *, u64 *);\n\tvoid (*sarc_configure)(void *, int);\n\tint (*config_l3_filter)(struct mac_device_info *, u32, bool, bool, bool, bool, u32);\n\tint (*config_l4_filter)(struct mac_device_info *, u32, bool, bool, bool, bool, u32);\n\tvoid (*set_arp_offload)(struct mac_device_info *, bool, u32);\n\tint (*fpe_map_preemption_class)(struct net_device *, struct netlink_ext_ack *, u32);\n};\n\nstruct stmmac_pcpu_stats {\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t rx_normal_irq_n[8];\n\tu64_stats_t tx_normal_irq_n[8];\n};\n\nstruct stmmac_pcs {\n\tstruct stmmac_priv *priv;\n\tvoid *base;\n\tu32 int_mask;\n\tstruct phylink_pcs pcs;\n};\n\nstruct stmmac_pps_cfg {\n\tbool available;\n\tlong: 32;\n\tstruct timespec64 start;\n\tstruct timespec64 period;\n};\n\nstruct stmmac_safety_stats {\n\tlong unsigned int mac_errors[32];\n\tlong unsigned int mtl_errors[32];\n\tlong unsigned int dma_errors[32];\n\tlong unsigned int dma_dpp_errors[32];\n};\n\nstruct stmmac_rss {\n\tint enable;\n\tu8 key[40];\n\tu32 table[256];\n};\n\nstruct stmmac_rfs_entry;\n\nstruct stmmac_priv {\n\tu32 tx_coal_frames[8];\n\tu32 tx_coal_timer[8];\n\tu32 rx_coal_frames[8];\n\tint hwts_tx_en;\n\tbool tx_path_in_lpi_mode;\n\tbool tso;\n\tbool sph_active;\n\tbool sph_capable;\n\tu32 sarc_type;\n\tu32 rx_riwt[8];\n\tint hwts_rx_en;\n\tbool tsfupdt_coarse;\n\tvoid *ioaddr;\n\tstruct net_device *dev;\n\tstruct device *device;\n\tstruct mac_device_info *hw;\n\tint (*hwif_quirks)(struct stmmac_priv *);\n\tstruct mutex lock;\n\tlong: 32;\n\tstruct stmmac_dma_conf dma_conf;\n\tstruct stmmac_channel channel[8];\n\tunsigned int pause_time;\n\tstruct mii_bus *mii;\n\tstruct stmmac_pcs *integrated_pcs;\n\tstruct phylink_config phylink_config;\n\tstruct phylink *phylink;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct stmmac_extra_stats xstats;\n\tstruct stmmac_safety_stats sstats;\n\tstruct plat_stmmacenet_data *plat;\n\tstruct mutex est_lock;\n\tstruct stmmac_est *est;\n\tstruct dma_features dma_cap;\n\tstruct stmmac_counters mmc;\n\tint hw_cap_support;\n\tint synopsys_id;\n\tu32 msg_enable;\n\tint wolopts;\n\tint wol_irq;\n\tu32 gmii_address_bus_config;\n\tstruct timer_list eee_ctrl_timer;\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_clk_stop;\n\tbool eee_enabled;\n\tbool eee_active;\n\tbool eee_sw_timer_en;\n\tbool legacy_serdes_is_powered;\n\tunsigned int mode;\n\tunsigned int chain_mode;\n\tint extend_desc;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_ops;\n\tunsigned int default_addend;\n\tu32 sub_second_inc;\n\tu32 systime_flags;\n\tu32 adv_ts;\n\tint use_riwt;\n\tint irq_wake;\n\trwlock_t ptp_lock;\n\tstruct mutex aux_ts_lock;\n\twait_queue_head_t tstamp_busy_wait;\n\tvoid *mmcaddr;\n\tvoid *ptpaddr;\n\tvoid *estaddr;\n\tlong unsigned int active_vlans[128];\n\tunsigned int num_double_vlans;\n\tint sfty_irq;\n\tint sfty_ce_irq;\n\tint sfty_ue_irq;\n\tint rx_irq[8];\n\tint tx_irq[8];\n\tchar int_name_mac[25];\n\tchar int_name_wol[25];\n\tchar int_name_lpi[25];\n\tchar int_name_sfty[26];\n\tchar int_name_sfty_ce[26];\n\tchar int_name_sfty_ue[26];\n\tchar int_name_rx_irq[240];\n\tchar int_name_tx_irq[272];\n\tstruct dentry *dbgfs_dir;\n\tlong unsigned int state;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct service_task;\n\tstruct stmmac_fpe_cfg fpe_cfg;\n\tunsigned int tc_entries_max;\n\tunsigned int tc_off_max;\n\tstruct stmmac_tc_entry *tc_entries;\n\tunsigned int flow_entries_max;\n\tstruct stmmac_flow_entry *flow_entries;\n\tunsigned int rfs_entries_max[3];\n\tunsigned int rfs_entries_cnt[3];\n\tunsigned int rfs_entries_total;\n\tstruct stmmac_rfs_entry *rfs_entries;\n\tstruct stmmac_pps_cfg pps[4];\n\tstruct stmmac_rss rss;\n\tlong unsigned int *af_xdp_zc_qps;\n\tstruct bpf_prog *xdp_prog;\n\tstruct devlink *devlink;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct stmmac_resources {\n\tvoid *addr;\n\tu8 mac[6];\n\tint wol_irq;\n\tint irq;\n\tint sfty_irq;\n\tint sfty_ce_irq;\n\tint sfty_ue_irq;\n\tint rx_irq[8];\n\tint tx_irq[8];\n};\n\nstruct stmmac_rfs_entry {\n\tlong unsigned int cookie;\n\tu16 etype;\n\tint in_use;\n\tint type;\n\tint tc;\n};\n\nstruct stmmac_rx_buffer {\n\tunion {\n\t\tstruct {\n\t\t\tstruct page *page;\n\t\t\tdma_addr_t addr;\n\t\t\t__u32 page_offset;\n\t\t};\n\t\tstruct xdp_buff *xdp;\n\t};\n\tstruct page *sec_page;\n\tdma_addr_t sec_addr;\n};\n\nstruct stmmac_rx_routing {\n\tu32 reg_mask;\n\tu32 reg_shift;\n};\n\nstruct stmmac_safety_feature_cfg {\n\tu32 tsoee;\n\tu32 mrxpee;\n\tu32 mestee;\n\tu32 mrxee;\n\tu32 mtxee;\n\tu32 epsi;\n\tu32 edpp;\n\tu32 prtyen;\n\tu32 tmouten;\n};\n\nstruct stmmac_stats {\n\tchar stat_string[32];\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct stmmac_tc_entry {\n\tbool in_use;\n\tbool in_hw;\n\tbool is_last;\n\tbool is_frag;\n\tvoid *frag_ptr;\n\tunsigned int table_pos;\n\tu32 handle;\n\tu32 prio;\n\tstruct {\n\t\tu32 match_data;\n\t\tu32 match_en;\n\t\tu8 af: 1;\n\t\tu8 rf: 1;\n\t\tu8 im: 1;\n\t\tu8 nc: 1;\n\t\tu8 res1: 4;\n\t\tu8 frame_offset;\n\t\tu8 ok_index;\n\t\tu8 dma_ch_no;\n\t\tu32 res2;\n\t} val;\n};\n\nstruct tc_cls_u32_offload;\n\nstruct tc_cbs_qopt_offload;\n\nstruct tc_taprio_qopt_offload;\n\nstruct tc_etf_qopt_offload;\n\nstruct tc_query_caps_base;\n\nstruct tc_mqprio_qopt_offload;\n\nstruct stmmac_tc_ops {\n\tint (*init)(struct stmmac_priv *);\n\tint (*setup_cls_u32)(struct stmmac_priv *, struct tc_cls_u32_offload *);\n\tint (*setup_cbs)(struct stmmac_priv *, struct tc_cbs_qopt_offload *);\n\tint (*setup_cls)(struct stmmac_priv *, struct flow_cls_offload *);\n\tint (*setup_taprio)(struct stmmac_priv *, struct tc_taprio_qopt_offload *);\n\tint (*setup_etf)(struct stmmac_priv *, struct tc_etf_qopt_offload *);\n\tint (*query_caps)(struct stmmac_priv *, struct tc_query_caps_base *);\n\tint (*setup_mqprio)(struct stmmac_priv *, struct tc_mqprio_qopt_offload *);\n};\n\nstruct stmmac_tx_info {\n\tdma_addr_t buf;\n\tbool map_as_page;\n\tunsigned int len;\n\tbool last_segment;\n\tbool is_jumbo;\n\tenum stmmac_txbuf_type buf_type;\n\tstruct xsk_tx_metadata_compl xsk_meta;\n};\n\nstruct stmmac_version {\n\tu8 snpsver;\n\tu8 dev_id;\n};\n\nstruct stmmac_vlan_ops {\n\tvoid (*update_vlan_hash)(struct mac_device_info *, u32, u16, bool);\n\tvoid (*enable_vlan)(struct mac_device_info *, u32);\n\tvoid (*rx_hw_vlan)(struct mac_device_info *, struct dma_desc *, struct sk_buff *);\n\tvoid (*set_hw_vlan_mode)(struct mac_device_info *);\n\tint (*add_hw_vlan_rx_fltr)(struct net_device *, struct mac_device_info *, __be16, u16);\n\tint (*del_hw_vlan_rx_fltr)(struct net_device *, struct mac_device_info *, __be16, u16);\n\tvoid (*restore_hw_vlan_rx_fltr)(struct net_device *, struct mac_device_info *);\n};\n\nstruct stmmac_xdp_buff {\n\tstruct xdp_buff xdp;\n\tstruct stmmac_priv *priv;\n\tstruct dma_desc *desc;\n\tstruct dma_desc *ndesc;\n\tlong: 32;\n};\n\nstruct stmmac_xsk_tx_complete {\n\tstruct stmmac_priv *priv;\n\tstruct dma_desc *desc;\n};\n\nstruct stmpe_client_info;\n\nstruct stmpe_variant_info;\n\nstruct stmpe_platform_data;\n\nstruct stmpe {\n\tstruct regulator *vcc;\n\tstruct regulator *vio;\n\tstruct mutex lock;\n\tstruct mutex irq_lock;\n\tstruct device *dev;\n\tstruct irq_domain *domain;\n\tvoid *client;\n\tstruct stmpe_client_info *ci;\n\tenum stmpe_partnum partnum;\n\tstruct stmpe_variant_info *variant;\n\tconst u8 *regs;\n\tint irq;\n\tint num_gpios;\n\tu8 ier[2];\n\tu8 oldier[2];\n\tstruct stmpe_platform_data *pdata;\n\tu8 sample_time;\n\tu8 mod_12b;\n\tu8 ref_sel;\n\tu8 adc_freq;\n};\n\nstruct stmpe_client_info {\n\tvoid *data;\n\tint irq;\n\tvoid *client;\n\tstruct device *dev;\n\tint (*read_byte)(struct stmpe *, u8);\n\tint (*write_byte)(struct stmpe *, u8, u8);\n\tint (*read_block)(struct stmpe *, u8, u8, u8 *);\n\tint (*write_block)(struct stmpe *, u8, u8, const u8 *);\n\tvoid (*init)(struct stmpe *);\n};\n\nstruct stmpe_gpio {\n\tstruct gpio_chip chip;\n\tstruct stmpe *stmpe;\n\tstruct mutex irq_lock;\n\tu32 norequest_mask;\n\tu8 regs[9];\n\tu8 oldregs[9];\n};\n\nstruct stmpe_platform_data {\n\tint id;\n\tunsigned int blocks;\n\tunsigned int irq_trigger;\n\tbool autosleep;\n\tint autosleep_timeout;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct stmpe_touch {\n\tstruct stmpe *stmpe;\n\tstruct input_dev *idev;\n\tstruct delayed_work work;\n\tstruct device *dev;\n\tstruct touchscreen_properties prop;\n\tu8 ave_ctrl;\n\tu8 touch_det_delay;\n\tu8 settling;\n\tu8 fraction_z;\n\tu8 i_drive;\n};\n\nstruct stmpe_variant_block {\n\tconst struct mfd_cell *cell;\n\tint irq;\n\tenum stmpe_block block;\n};\n\nstruct stmpe_variant_info {\n\tconst char *name;\n\tu16 id_val;\n\tu16 id_mask;\n\tint num_gpios;\n\tint af_bits;\n\tconst u8 *regs;\n\tstruct stmpe_variant_block *blocks;\n\tint num_blocks;\n\tint num_irqs;\n\tint (*enable)(struct stmpe *, unsigned int, bool);\n\tint (*get_altfunc)(struct stmpe *, enum stmpe_block);\n\tint (*enable_autosleep)(struct stmpe *, int);\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct stpmic1 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tint irq;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct stpmic1_onkey {\n\tstruct input_dev *input_dev;\n\tint irq_falling;\n\tint irq_rising;\n};\n\nstruct stpmic1_regulator_cfg {\n\tstruct regulator_desc desc;\n\tu8 mask_reset_reg;\n\tu8 mask_reset_mask;\n\tu8 icc_reg;\n\tu8 icc_mask;\n};\n\nstruct stpmic1_wdt {\n\tstruct stpmic1 *pmic;\n\tstruct watchdog_device wdtdev;\n};\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct subdev_regulators {\n\tunsigned int num_supplies;\n\tstruct regulator_bulk_data supplies[0];\n};\n\nstruct submit_info {\n\tstruct cpdma_chan *chan;\n\tint directed;\n\tvoid *token;\n\tvoid *data_virt;\n\tdma_addr_t data_dma;\n\tint len;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\nstruct sugov_policy;\n\nstruct sugov_cpu {\n\tstruct update_util_data update_util;\n\tstruct sugov_policy *sg_policy;\n\tunsigned int cpu;\n\tbool iowait_boost_pending;\n\tunsigned int iowait_boost;\n\tlong: 32;\n\tu64 last_update;\n\tlong unsigned int util;\n\tlong unsigned int bw_min;\n\tlong unsigned int saved_idle_calls;\n\tlong: 32;\n};\n\nstruct sugov_tunables;\n\nstruct sugov_policy {\n\tstruct cpufreq_policy *policy;\n\tstruct sugov_tunables *tunables;\n\tstruct list_head tunables_hook;\n\traw_spinlock_t update_lock;\n\tlong: 32;\n\tu64 last_freq_update_time;\n\ts64 freq_update_delay_ns;\n\tunsigned int next_freq;\n\tunsigned int cached_raw_freq;\n\tstruct irq_work irq_work;\n\tstruct kthread_work work;\n\tstruct mutex work_lock;\n\tstruct kthread_worker worker;\n\tstruct task_struct *thread;\n\tbool work_in_progress;\n\tbool limits_changed;\n\tbool need_freq_update;\n};\n\nstruct sugov_tunables {\n\tstruct gov_attr_set attr_set;\n\tunsigned int rate_limit_us;\n};\n\nstruct summary_data {\n\tstruct seq_file *s;\n\tstruct regulator_dev *parent;\n\tint level;\n};\n\nstruct summary_lock_data {\n\tstruct ww_acquire_ctx *ww_ctx;\n\tstruct regulator_dev **new_contended_rdev;\n\tstruct regulator_dev **old_contended_rdev;\n};\n\nstruct sun20i_ppu_desc {\n\tconst char * const *names;\n\tunsigned int num_domains;\n};\n\nstruct sun20i_ppu_pd {\n\tstruct generic_pm_domain genpd;\n\tvoid *base;\n\tlong: 32;\n};\n\nstruct sun20i_regulator_data {\n\tconst struct regulator_desc *descs;\n\tunsigned int ndescs;\n};\n\nstruct sun4i_a10_display_clk_data {\n\tbool has_div;\n\tu8 num_rst;\n\tu8 parents;\n\tu8 offset_en;\n\tu8 offset_div;\n\tu8 offset_mux;\n\tu8 offset_rst;\n\tu8 width_div;\n\tu8 width_mux;\n\tu32 flags;\n};\n\nstruct sun4i_dma_config {\n\tu32 ndma_nr_max_channels;\n\tu32 ndma_nr_max_vchans;\n\tu32 ddma_nr_max_channels;\n\tu32 ddma_nr_max_vchans;\n\tu32 dma_nr_max_channels;\n\tvoid (*set_dst_data_width)(u32 *, s8);\n\tvoid (*set_src_data_width)(u32 *, s8);\n\tint (*convert_burst)(u32);\n\tu8 ndma_drq_sdram;\n\tu8 ddma_drq_sdram;\n\tu8 max_burst;\n\tbool has_reset;\n};\n\nstruct sun4i_dma_contract {\n\tstruct virt_dma_desc vd;\n\tstruct list_head demands;\n\tstruct list_head completed_demands;\n\tbool is_cyclic: 1;\n\tbool use_half_int: 1;\n};\n\nstruct sun4i_dma_pchan;\n\nstruct sun4i_dma_vchan;\n\nstruct sun4i_dma_dev {\n\tlong unsigned int *pchans_used;\n\tstruct dma_device slave;\n\tstruct sun4i_dma_pchan *pchans;\n\tstruct sun4i_dma_vchan *vchans;\n\tvoid *base;\n\tstruct clk *clk;\n\tint irq;\n\tspinlock_t lock;\n\tconst struct sun4i_dma_config *cfg;\n\tstruct reset_control *rst;\n};\n\nstruct sun4i_dma_pchan {\n\tvoid *base;\n\tstruct sun4i_dma_vchan *vchan;\n\tint is_dedicated;\n};\n\nstruct sun4i_dma_promise {\n\tu32 cfg;\n\tu32 para;\n\tdma_addr_t src;\n\tdma_addr_t dst;\n\tsize_t len;\n\tstruct list_head list;\n};\n\nstruct sun4i_dma_vchan {\n\tstruct virt_dma_chan vc;\n\tstruct dma_slave_config cfg;\n\tstruct sun4i_dma_pchan *pchan;\n\tstruct sun4i_dma_promise *processing;\n\tstruct sun4i_dma_contract *contract;\n\tu8 endpoint;\n\tint is_dedicated;\n};\n\nstruct sun4i_irq_chip_data {\n\tvoid *irq_base;\n\tstruct irq_domain *irq_domain;\n\tu32 enable_reg_offset;\n\tu32 mask_reg_offset;\n};\n\nstruct sun4i_mdio_data {\n\tvoid *membase;\n\tstruct regulator *regulator;\n};\n\nstruct sun4i_pwm_data;\n\nstruct sun4i_pwm_chip {\n\tstruct clk *bus_clk;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tvoid *base;\n\tconst struct sun4i_pwm_data *data;\n};\n\nstruct sun4i_pwm_data {\n\tbool has_prescaler_bypass;\n\tbool has_direct_mod_clk_output;\n\tunsigned int npwm;\n};\n\nstruct sun4i_spi {\n\tstruct spi_controller *host;\n\tvoid *base_addr;\n\tstruct clk *hclk;\n\tstruct clk *mclk;\n\tstruct completion done;\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tint len;\n};\n\nstruct sun4i_ts_data {\n\tstruct device *dev;\n\tstruct input_dev *input;\n\tvoid *base;\n\tunsigned int irq;\n\tbool ignore_fifo_data;\n\tint temp_data;\n\tint temp_offset;\n\tint temp_step;\n};\n\nstruct sun4i_usb_phy {\n\tstruct phy *phy;\n\tvoid *pmu;\n\tstruct regulator *vbus;\n\tstruct reset_control *reset;\n\tstruct clk *clk;\n\tstruct clk *clk2;\n\tbool regulator_on;\n\tint index;\n};\n\nstruct sun4i_usb_phy_cfg {\n\tint hsic_index;\n\tu32 disc_thresh;\n\tu32 hci_phy_ctl_clear;\n\tu8 phyctl_offset;\n\tbool dedicated_clocks;\n\tbool phy0_dual_route;\n\tbool needs_phy2_siddq;\n\tbool siddq_in_base;\n\tbool poll_vbusen;\n\tint missing_phys;\n};\n\nstruct sun4i_usb_phy_data {\n\tvoid *base;\n\tconst struct sun4i_usb_phy_cfg *cfg;\n\tenum usb_dr_mode dr_mode;\n\tspinlock_t reg_lock;\n\tint num_phys;\n\tstruct sun4i_usb_phy phys[4];\n\tstruct extcon_dev *extcon;\n\tbool phy0_init;\n\tstruct gpio_desc *id_det_gpio;\n\tstruct gpio_desc *vbus_det_gpio;\n\tstruct power_supply *vbus_power_supply;\n\tstruct notifier_block vbus_power_nb;\n\tbool vbus_power_nb_registered;\n\tbool force_session_end;\n\tint id_det_irq;\n\tint vbus_det_irq;\n\tint id_det;\n\tint vbus_det;\n\tstruct delayed_work detect;\n};\n\nstruct sun4ican_priv {\n\tstruct can_priv can;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tspinlock_t cmdreg_lock;\n\tint acp_offset;\n};\n\nstruct sun4ican_quirks {\n\tbool has_reset;\n\tint acp_offset;\n};\n\nstruct sun5i_timer {\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct notifier_block clk_rate_cb;\n\tu32 ticks_per_jiffy;\n\tstruct clocksource clksrc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device clkevt;\n};\n\nstruct sun6i_dma_lli;\n\nstruct sun6i_desc {\n\tstruct virt_dma_desc vd;\n\tdma_addr_t p_lli;\n\tstruct sun6i_dma_lli *v_lli;\n};\n\nstruct sun6i_dma_dev;\n\nstruct sun6i_dma_config {\n\tu32 nr_max_channels;\n\tu32 nr_max_requests;\n\tu32 nr_max_vchans;\n\tvoid (*clock_autogate_enable)(struct sun6i_dma_dev *);\n\tvoid (*set_burst_length)(u32 *, s8, s8);\n\tvoid (*set_drq)(u32 *, s8, s8);\n\tvoid (*set_mode)(u32 *, s8, s8);\n\tu32 src_burst_lengths;\n\tu32 dst_burst_lengths;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tbool has_high_addr;\n\tbool has_mbus_clk;\n};\n\nstruct sun6i_pchan;\n\nstruct sun6i_vchan;\n\nstruct sun6i_dma_dev {\n\tstruct dma_device slave;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *clk_mbus;\n\tint irq;\n\tspinlock_t lock;\n\tstruct reset_control *rstc;\n\tstruct tasklet_struct task;\n\tatomic_t tasklet_shutdown;\n\tstruct list_head pending;\n\tstruct dma_pool *pool;\n\tstruct sun6i_pchan *pchans;\n\tstruct sun6i_vchan *vchans;\n\tconst struct sun6i_dma_config *cfg;\n\tu32 num_pchans;\n\tu32 num_vchans;\n\tu32 max_request;\n};\n\nstruct sun6i_dma_lli {\n\tu32 cfg;\n\tu32 src;\n\tu32 dst;\n\tu32 len;\n\tu32 para;\n\tu32 p_lli_next;\n\tstruct sun6i_dma_lli *v_lli_next;\n};\n\nstruct sun6i_msgbox {\n\tstruct mbox_controller controller;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tvoid *regs;\n\tlong: 32;\n};\n\nstruct sun6i_pchan {\n\tu32 idx;\n\tvoid *base;\n\tstruct sun6i_vchan *vchan;\n\tstruct sun6i_desc *desc;\n\tstruct sun6i_desc *done;\n};\n\nstruct sun6i_r_intc_variant {\n\tu32 first_mux_irq;\n\tu32 nr_mux_irqs;\n\tu32 mux_valid[4];\n};\n\nstruct sun6i_rtc_clk_data {\n\tlong unsigned int rc_osc_rate;\n\tunsigned int fixed_prescaler: 16;\n\tunsigned int has_prescaler: 1;\n\tunsigned int has_out_clk: 1;\n\tunsigned int has_losc_en: 1;\n\tunsigned int has_auto_swt: 1;\n};\n\nstruct sun6i_rtc_dev {\n\tstruct rtc_device *rtc;\n\tconst struct sun6i_rtc_clk_data *data;\n\tvoid *base;\n\tint irq;\n\ttime64_t alarm;\n\tlong unsigned int flags;\n\tstruct clk_hw hw;\n\tstruct clk_hw *int_osc;\n\tstruct clk *losc;\n\tstruct clk *ext_losc;\n\tspinlock_t lock;\n};\n\nstruct sun6i_rtc_match_data {\n\tbool have_ext_osc32k: 1;\n\tbool have_iosc_calibration: 1;\n\tbool rtc_32k_single_parent: 1;\n\tconst struct clk_parent_data *osc32k_fanout_parents;\n\tu8 osc32k_fanout_nparents;\n};\n\nstruct sun6i_spi_cfg;\n\nstruct sun6i_spi {\n\tstruct spi_controller *host;\n\tvoid *base_addr;\n\tdma_addr_t dma_addr_rx;\n\tdma_addr_t dma_addr_tx;\n\tstruct clk *hclk;\n\tstruct clk *mclk;\n\tstruct reset_control *rstc;\n\tstruct completion done;\n\tstruct completion dma_rx_done;\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tint len;\n\tconst struct sun6i_spi_cfg *cfg;\n};\n\nstruct sun6i_spi_cfg {\n\tlong unsigned int fifo_depth;\n\tbool has_clk_ctl;\n\tu32 mode_bits;\n};\n\nstruct sun6i_vchan {\n\tstruct virt_dma_chan vc;\n\tstruct list_head node;\n\tstruct dma_slave_config cfg;\n\tstruct sun6i_pchan *phy;\n\tu8 port;\n\tu8 irq_type;\n\tbool cyclic;\n};\n\nstruct sun9i_a80_cpus_clk {\n\tstruct clk_hw hw;\n\tvoid *reg;\n};\n\nstruct sun9i_mmc_clk_data {\n\tspinlock_t lock;\n\tvoid *membase;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tstruct clk_onecell_data clk_data;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct sun9i_usb_phy {\n\tstruct phy *phy;\n\tvoid *pmu;\n\tstruct reset_control *reset;\n\tstruct clk *clk;\n\tstruct clk *hsic_clk;\n\tenum usb_phy_interface type;\n};\n\nstruct sunplus_uart_port {\n\tstruct uart_port port;\n\tstruct clk *clk;\n\tstruct reset_control *rstc;\n};\n\nstruct sunrpc_net {\n\tstruct proc_dir_entry *proc_net_rpc;\n\tstruct cache_detail *ip_map_cache;\n\tstruct cache_detail *unix_gid_cache;\n\tstruct cache_detail *rsc_cache;\n\tstruct cache_detail *rsi_cache;\n\tstruct super_block *pipefs_sb;\n\tstruct rpc_pipe *gssd_dummy;\n\tstruct mutex pipefs_sb_lock;\n\tstruct list_head all_clients;\n\tspinlock_t rpc_client_lock;\n\tstruct rpc_clnt *rpcb_local_clnt;\n\tstruct rpc_clnt *rpcb_local_clnt4;\n\tspinlock_t rpcb_clnt_lock;\n\tunsigned int rpcb_users;\n\tunsigned int rpcb_is_af_local: 1;\n\tstruct mutex gssp_lock;\n\tstruct rpc_clnt *gssp_clnt;\n\tint use_gss_proxy;\n\tint pipe_version;\n\tatomic_t pipe_users;\n\tstruct proc_dir_entry *use_gssp_proc;\n\tstruct proc_dir_entry *gss_krb5_enctypes;\n};\n\nstruct sunxi_ccu_desc;\n\nstruct sunxi_ccu {\n\tconst struct sunxi_ccu_desc *desc;\n\tspinlock_t lock;\n\tstruct ccu_reset reset;\n};\n\nstruct sunxi_ccu_desc {\n\tstruct ccu_common **ccu_clks;\n\tlong unsigned int num_ccu_clks;\n\tstruct clk_hw_onecell_data *hw_clks;\n\tconst struct ccu_reset_map *resets;\n\tlong unsigned int num_resets;\n};\n\nstruct sunxi_desc_function {\n\tlong unsigned int variant;\n\tconst char *name;\n\tu8 muxval;\n\tu8 irqbank;\n\tu8 irqnum;\n};\n\nstruct sunxi_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tlong unsigned int variant;\n\tstruct sunxi_desc_function *functions;\n};\n\nstruct sunxi_idma_des {\n\t__le32 config;\n\t__le32 buf_size;\n\t__le32 buf_addr_ptr1;\n\t__le32 buf_addr_ptr2;\n};\n\nstruct sunxi_mc_smp_nodes;\n\nstruct sunxi_mc_smp_data {\n\tconst char *enable_method;\n\tint (*get_smp_nodes)(struct sunxi_mc_smp_nodes *);\n\tbool is_a83t;\n};\n\nstruct sunxi_mc_smp_nodes {\n\tstruct device_node *prcm_node;\n\tstruct device_node *cpucfg_node;\n\tstruct device_node *sram_node;\n\tstruct device_node *r_cpucfg_node;\n};\n\nstruct sunxi_mmc_clk_delay;\n\nstruct sunxi_mmc_cfg {\n\tu32 idma_des_size_bits;\n\tu32 idma_des_shift;\n\tconst struct sunxi_mmc_clk_delay *clk_delays;\n\tbool can_calibrate;\n\tbool mask_data0;\n\tbool needs_new_timings;\n\tbool ccu_has_timings_switch;\n};\n\nstruct sunxi_mmc_clk_delay {\n\tu32 output;\n\tu32 sample;\n};\n\nstruct sunxi_mmc_host {\n\tstruct device *dev;\n\tstruct mmc_host *mmc;\n\tstruct reset_control *reset;\n\tconst struct sunxi_mmc_cfg *cfg;\n\tvoid *reg_base;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_mmc;\n\tstruct clk *clk_sample;\n\tstruct clk *clk_output;\n\tspinlock_t lock;\n\tint irq;\n\tu32 int_sum;\n\tu32 sdio_imask;\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tbool wait_dma;\n\tstruct mmc_request *mrq;\n\tstruct mmc_request *manual_stop_mrq;\n\tint ferror;\n\tbool vqmmc_enabled;\n\tbool use_new_timings;\n};\n\nstruct sunxi_pck600;\n\nstruct sunxi_pck600_pd {\n\tstruct generic_pm_domain genpd;\n\tstruct sunxi_pck600 *pck;\n\tvoid *base;\n};\n\nstruct sunxi_pck600 {\n\tstruct device *dev;\n\tstruct genpd_onecell_data genpd_data;\n\tstruct sunxi_pck600_pd pds[0];\n};\n\nstruct sunxi_pck600_desc {\n\tconst char * const *pd_names;\n\tunsigned int num_domains;\n\tu32 logic_power_switch0_delay_offset;\n\tu32 logic_power_switch1_delay_offset;\n\tu32 off2on_delay_offset;\n\tu32 device_ctrl0_delay;\n\tu32 device_ctrl1_delay;\n\tu32 logic_power_switch0_delay;\n\tu32 logic_power_switch1_delay;\n\tu32 off2on_delay;\n};\n\nstruct sunxi_pinctrl_regulator {\n\tstruct regulator *regulator;\n\trefcount_t refcount;\n};\n\nstruct sunxi_pinctrl_desc;\n\nstruct sunxi_pinctrl_function;\n\nstruct sunxi_pinctrl_group;\n\nstruct sunxi_pinctrl {\n\tvoid *membase;\n\tstruct gpio_chip *chip;\n\tconst struct sunxi_pinctrl_desc *desc;\n\tstruct device *dev;\n\tstruct sunxi_pinctrl_regulator regulators[11];\n\tstruct irq_domain *domain;\n\tstruct sunxi_pinctrl_function *functions;\n\tunsigned int nfunctions;\n\tstruct sunxi_pinctrl_group *groups;\n\tunsigned int ngroups;\n\tint *irq;\n\tunsigned int *irq_array;\n\traw_spinlock_t lock;\n\tstruct pinctrl_dev *pctl_dev;\n\tlong unsigned int variant;\n\tu32 bank_mem_size;\n\tu32 pull_regs_offset;\n\tu32 dlevel_field_width;\n\tu32 pow_mod_sel_offset;\n};\n\nstruct sunxi_pinctrl_desc {\n\tconst struct sunxi_desc_pin *pins;\n\tint npins;\n\tunsigned int pin_base;\n\tunsigned int irq_banks;\n\tconst unsigned int *irq_bank_map;\n\tbool irq_read_needs_mux;\n\tbool disable_strict_mode;\n\tenum sunxi_desc_bias_voltage io_bias_cfg_variant;\n};\n\nstruct sunxi_pinctrl_function {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct sunxi_pinctrl_group {\n\tconst char *name;\n\tunsigned int pin;\n};\n\nstruct sunxi_priv_data {\n\tphy_interface_t interface;\n\tint clk_enabled;\n\tstruct clk *tx_clk;\n\tstruct regulator *regulator;\n};\n\nstruct sunxi_priv_data___2 {\n\tstruct clk *ephy_clk;\n\tstruct regulator *regulator;\n\tstruct reset_control *rst_ephy;\n\tconst struct emac_variant *variant;\n\tstruct regmap_field *regmap_field;\n\tbool internal_phy_powered;\n\tbool use_internal_phy;\n\tvoid *mux_handle;\n};\n\nstruct sunxi_rsb {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct reset_control *rstc;\n\tstruct completion complete;\n\tstruct mutex lock;\n\tunsigned int status;\n\tu32 clk_freq;\n};\n\nstruct sunxi_rsb_addr_map {\n\tu16 hwaddr;\n\tu8 rtaddr;\n};\n\nstruct sunxi_rsb_device;\n\nstruct sunxi_rsb_ctx {\n\tstruct sunxi_rsb_device *rdev;\n\tint size;\n};\n\nstruct sunxi_rsb_device {\n\tstruct device dev;\n\tstruct sunxi_rsb *rsb;\n\tint irq;\n\tu8 rtaddr;\n\tu16 hwaddr;\n\tlong: 32;\n};\n\nstruct sunxi_rsb_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct sunxi_rsb_device *);\n\tvoid (*remove)(struct sunxi_rsb_device *);\n};\n\nstruct sunxi_rtc_data_year {\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int mask;\n\tunsigned char leap_shift;\n};\n\nstruct sunxi_rtc_dev {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tconst struct sunxi_rtc_data_year *data_year;\n\tvoid *base;\n\tint irq;\n};\n\nstruct sunxi_sc_nmi_data {\n\tstruct {\n\t\tu32 ctrl;\n\t\tu32 pend;\n\t\tu32 enable;\n\t} reg_offs;\n\tu32 enable_val;\n};\n\nstruct sunxi_sid {\n\tvoid *base;\n\tu32 value_offset;\n};\n\nstruct sunxi_sid_cfg {\n\tu32 value_offset;\n\tu32 size;\n\tbool need_register_readout;\n};\n\nstruct sunxi_sram_func;\n\nstruct sunxi_sram_data {\n\tchar *name;\n\tu8 reg;\n\tu8 offset;\n\tu8 width;\n\tstruct sunxi_sram_func *func;\n};\n\nstruct sunxi_sram_desc {\n\tstruct sunxi_sram_data data;\n\tbool claimed;\n};\n\nstruct sunxi_sram_func {\n\tchar *func;\n\tu8 val;\n\tu32 reg_val;\n};\n\nstruct sunxi_sramc_variant {\n\tint num_emac_clocks;\n\tbool has_ldo_ctrl;\n\tbool has_ths_offset;\n};\n\nstruct sunxi_wdt_reg;\n\nstruct sunxi_wdt_dev {\n\tstruct watchdog_device wdt_dev;\n\tvoid *wdt_base;\n\tconst struct sunxi_wdt_reg *wdt_regs;\n};\n\nstruct sunxi_wdt_reg {\n\tu8 wdt_ctrl;\n\tu8 wdt_cfg;\n\tu8 wdt_mode;\n\tu8 wdt_timeout_shift;\n\tu8 wdt_reset_mask;\n\tu8 wdt_reset_val;\n\tu32 wdt_key_val;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tlong: 32;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tconst struct xattr_handler * const *s_xattr;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tlong: 32;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\tlong: 32;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct supplier_bindings {\n\tstruct device_node * (*parse_prop)(struct device_node *, const char *, int);\n\tstruct device_node * (*get_con_dev)(struct device_node *);\n\tbool optional;\n\tu8 fwlink_flags;\n};\n\nstruct suspend_stats {\n\tunsigned int step_failures[8];\n\tunsigned int success;\n\tunsigned int fail;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tlong: 32;\n\tu64 last_hw_sleep;\n\tu64 total_hw_sleep;\n\tu64 max_hw_sleep;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nstruct svc_deferred_req {\n\tu32 prot;\n\tstruct svc_xprt *xprt;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tstruct __kernel_sockaddr_storage daddr;\n\tsize_t daddrlen;\n\tvoid *xprt_ctxt;\n\tstruct cache_deferred_req handle;\n\tint argslen;\n\t__be32 args[0];\n};\n\nstruct svc_info {\n\tstruct svc_serv *serv;\n\tstruct mutex *mutex;\n};\n\nstruct svc_pool {\n\tunsigned int sp_id;\n\tunsigned int sp_nrthreads;\n\tunsigned int sp_nrthrmin;\n\tunsigned int sp_nrthrmax;\n\tstruct lwq sp_xprts;\n\tstruct list_head sp_all_threads;\n\tstruct llist_head sp_idle_threads;\n\tstruct percpu_counter sp_messages_arrived;\n\tstruct percpu_counter sp_sockets_queued;\n\tstruct percpu_counter sp_threads_woken;\n\tlong unsigned int sp_flags;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct svc_pool_map {\n\tint count;\n\tint mode;\n\tunsigned int npools;\n\tunsigned int *pool_to;\n\tunsigned int *to_pool;\n};\n\nstruct svc_procedure {\n\t__be32 (*pc_func)(struct svc_rqst *);\n\tbool (*pc_decode)(struct svc_rqst *, struct xdr_stream *);\n\tbool (*pc_encode)(struct svc_rqst *, struct xdr_stream *);\n\tvoid (*pc_release)(struct svc_rqst *);\n\tunsigned int pc_argsize;\n\tunsigned int pc_argzero;\n\tunsigned int pc_ressize;\n\tunsigned int pc_cachetype;\n\tunsigned int pc_xdrressize;\n\tconst char *pc_name;\n};\n\nstruct svc_process_info {\n\tunion {\n\t\tint (*dispatch)(struct svc_rqst *);\n\t\tstruct {\n\t\t\tunsigned int lovers;\n\t\t\tunsigned int hivers;\n\t\t} mismatch;\n\t};\n};\n\nstruct svc_version;\n\nstruct svc_program {\n\tu32 pg_prog;\n\tunsigned int pg_lovers;\n\tunsigned int pg_hivers;\n\tunsigned int pg_nvers;\n\tconst struct svc_version **pg_vers;\n\tchar *pg_name;\n\tchar *pg_class;\n\tenum svc_auth_status (*pg_authenticate)(struct svc_rqst *);\n\t__be32 (*pg_init_request)(struct svc_rqst *, const struct svc_program *, struct svc_process_info *);\n\tint (*pg_rpcbind_set)(struct net *, const struct svc_program *, u32, int, short unsigned int, short unsigned int);\n};\n\nstruct svc_pt_regs {\n\tstruct pt_regs regs;\n\tu32 dacr;\n\tu32 ttbcr;\n};\n\nstruct xdr_stream {\n\t__be32 *p;\n\tstruct xdr_buf *buf;\n\t__be32 *end;\n\tstruct kvec *iov;\n\tstruct kvec scratch;\n\tstruct page **page_ptr;\n\tvoid *page_kaddr;\n\tunsigned int nwords;\n\tstruct rpc_rqst *rqst;\n};\n\nstruct svc_rqst {\n\tstruct list_head rq_all;\n\tstruct llist_node rq_idle;\n\tstruct callback_head rq_rcu_head;\n\tstruct svc_xprt *rq_xprt;\n\tstruct __kernel_sockaddr_storage rq_addr;\n\tsize_t rq_addrlen;\n\tstruct __kernel_sockaddr_storage rq_daddr;\n\tsize_t rq_daddrlen;\n\tstruct svc_serv *rq_server;\n\tstruct svc_pool *rq_pool;\n\tconst struct svc_procedure *rq_procinfo;\n\tstruct auth_ops *rq_authop;\n\tstruct svc_cred rq_cred;\n\tvoid *rq_xprt_ctxt;\n\tstruct svc_deferred_req *rq_deferred;\n\tstruct xdr_buf rq_arg;\n\tstruct xdr_stream rq_arg_stream;\n\tstruct xdr_stream rq_res_stream;\n\tstruct folio *rq_scratch_folio;\n\tstruct xdr_buf rq_res;\n\tlong unsigned int rq_maxpages;\n\tstruct page **rq_pages;\n\tstruct page **rq_respages;\n\tstruct page **rq_next_page;\n\tstruct page **rq_page_end;\n\tstruct folio_batch rq_fbatch;\n\tstruct bio_vec *rq_bvec;\n\t__be32 rq_xid;\n\tu32 rq_prog;\n\tu32 rq_vers;\n\tu32 rq_proc;\n\tu32 rq_prot;\n\tint rq_cachetype;\n\tlong unsigned int rq_flags;\n\tktime_t rq_qtime;\n\tvoid *rq_argp;\n\tvoid *rq_resp;\n\t__be32 *rq_accept_statp;\n\tvoid *rq_auth_data;\n\t__be32 rq_auth_stat;\n\tint rq_auth_slack;\n\tint rq_reserved;\n\tlong: 32;\n\tktime_t rq_stime;\n\tstruct cache_req rq_chandle;\n\tstruct auth_domain *rq_client;\n\tstruct auth_domain *rq_gssclient;\n\tstruct task_struct *rq_task;\n\tstruct net *rq_bc_net;\n\tint rq_err;\n\tlong unsigned int bc_to_initval;\n\tunsigned int bc_to_retries;\n\tunsigned int rq_status_counter;\n\tvoid **rq_lease_breaker;\n\tlong: 32;\n};\n\nstruct svc_stat;\n\nstruct svc_serv {\n\tstruct svc_program *sv_programs;\n\tstruct svc_stat *sv_stats;\n\tspinlock_t sv_lock;\n\tunsigned int sv_nprogs;\n\tunsigned int sv_nrthreads;\n\tunsigned int sv_max_payload;\n\tunsigned int sv_max_mesg;\n\tunsigned int sv_xdrsize;\n\tstruct list_head sv_permsocks;\n\tstruct list_head sv_tempsocks;\n\tint sv_tmpcnt;\n\tstruct timer_list sv_temptimer;\n\tchar *sv_name;\n\tunsigned int sv_nrpools;\n\tbool sv_is_pooled;\n\tstruct svc_pool *sv_pools;\n\tint (*sv_threadfn)(void *);\n\tstruct lwq sv_cb_list;\n\tbool sv_bc_enabled;\n};\n\nstruct svc_xprt_class;\n\nstruct svc_xprt_ops;\n\nstruct svc_xprt {\n\tstruct svc_xprt_class *xpt_class;\n\tconst struct svc_xprt_ops *xpt_ops;\n\tstruct kref xpt_ref;\n\tlong: 32;\n\tktime_t xpt_qtime;\n\tstruct list_head xpt_list;\n\tstruct lwq_node xpt_ready;\n\tlong unsigned int xpt_flags;\n\tstruct svc_serv *xpt_server;\n\tatomic_t xpt_reserved;\n\tatomic_t xpt_nr_rqsts;\n\tstruct mutex xpt_mutex;\n\tspinlock_t xpt_lock;\n\tvoid *xpt_auth_cache;\n\tstruct list_head xpt_deferred;\n\tstruct __kernel_sockaddr_storage xpt_local;\n\tsize_t xpt_locallen;\n\tstruct __kernel_sockaddr_storage xpt_remote;\n\tsize_t xpt_remotelen;\n\tchar xpt_remotebuf[58];\n\tstruct list_head xpt_users;\n\tstruct net *xpt_net;\n\tnetns_tracker ns_tracker;\n\tconst struct cred *xpt_cred;\n\tstruct rpc_xprt *xpt_bc_xprt;\n\tstruct rpc_xprt_switch *xpt_bc_xps;\n\tlong: 32;\n};\n\nstruct svc_sock {\n\tstruct svc_xprt sk_xprt;\n\tstruct socket *sk_sock;\n\tstruct sock *sk_sk;\n\tvoid (*sk_ostate)(struct sock *);\n\tvoid (*sk_odata)(struct sock *);\n\tvoid (*sk_owspace)(struct sock *);\n\tstruct bio_vec *sk_bvec;\n\t__be32 sk_marker;\n\tu32 sk_tcplen;\n\tu32 sk_datalen;\n\tstruct page_frag_cache sk_frag_cache;\n\tstruct completion sk_handshake_done;\n\tlong unsigned int sk_maxpages;\n\tstruct page *sk_pages[0];\n};\n\nstruct svc_stat {\n\tstruct svc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcbadfmt;\n\tunsigned int rpcbadauth;\n\tunsigned int rpcbadclnt;\n};\n\nstruct svc_version {\n\tu32 vs_vers;\n\tu32 vs_nproc;\n\tconst struct svc_procedure *vs_proc;\n\tlong unsigned int *vs_count;\n\tu32 vs_xdrsize;\n\tbool vs_hidden;\n\tbool vs_rpcb_optnl;\n\tbool vs_need_cong_ctrl;\n\tint (*vs_dispatch)(struct svc_rqst *);\n};\n\nstruct svc_xprt_class {\n\tconst char *xcl_name;\n\tstruct module *xcl_owner;\n\tconst struct svc_xprt_ops *xcl_ops;\n\tstruct list_head xcl_list;\n\tu32 xcl_max_payload;\n\tint xcl_ident;\n};\n\nstruct svc_xprt_ops {\n\tstruct svc_xprt * (*xpo_create)(struct svc_serv *, struct net *, struct sockaddr *, int, int);\n\tstruct svc_xprt * (*xpo_accept)(struct svc_xprt *);\n\tint (*xpo_has_wspace)(struct svc_xprt *);\n\tint (*xpo_recvfrom)(struct svc_rqst *);\n\tint (*xpo_sendto)(struct svc_rqst *);\n\tint (*xpo_result_payload)(struct svc_rqst *, unsigned int, unsigned int);\n\tvoid (*xpo_release_ctxt)(struct svc_xprt *, void *);\n\tvoid (*xpo_detach)(struct svc_xprt *);\n\tvoid (*xpo_free)(struct svc_xprt *);\n\tvoid (*xpo_kill_temp_xprt)(struct svc_xprt *);\n\tvoid (*xpo_handshake)(struct svc_xprt *);\n};\n\nstruct svc_xpt_user {\n\tstruct list_head list;\n\tvoid (*callback)(struct svc_xpt_user *);\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tlong: 32;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[1];\n\tstruct list_head frag_clusters[1];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[1];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[256];\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n};\n\nstruct switchdev_mst_state {\n\tu16 msti;\n\tu8 state;\n};\n\nstruct switchdev_brport_flags {\n\tlong unsigned int val;\n\tlong unsigned int mask;\n};\n\nstruct switchdev_vlan_msti {\n\tu16 vid;\n\tu16 msti;\n};\n\nstruct switchdev_attr {\n\tstruct net_device *orig_dev;\n\tenum switchdev_attr_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n\tunion {\n\t\tu8 stp_state;\n\t\tstruct switchdev_mst_state mst_state;\n\t\tstruct switchdev_brport_flags brport_flags;\n\t\tbool mrouter;\n\t\tclock_t ageing_time;\n\t\tbool vlan_filtering;\n\t\tu16 vlan_protocol;\n\t\tbool mst;\n\t\tbool mc_disabled;\n\t\tu8 mrp_port_role;\n\t\tstruct switchdev_vlan_msti vlan_msti;\n\t} u;\n};\n\nstruct switchdev_brport {\n\tstruct net_device *dev;\n\tconst void *ctx;\n\tstruct notifier_block *atomic_nb;\n\tstruct notifier_block *blocking_nb;\n\tbool tx_fwd_offload;\n};\n\ntypedef void switchdev_deferred_func_t(struct net_device *, const void *);\n\nstruct switchdev_deferred_item {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tswitchdev_deferred_func_t *func;\n\tlong unsigned int data[0];\n};\n\nstruct switchdev_nested_priv {\n\tbool (*check_cb)(const struct net_device *);\n\tbool (*foreign_dev_check_cb)(const struct net_device *, const struct net_device *);\n\tconst struct net_device *dev;\n\tstruct net_device *lower_dev;\n};\n\nstruct switchdev_notifier_brport_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_brport brport;\n};\n\nstruct switchdev_notifier_port_attr_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_attr *attr;\n\tbool handled;\n};\n\nstruct switchdev_obj;\n\nstruct switchdev_notifier_port_obj_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_obj *obj;\n\tbool handled;\n};\n\nstruct switchdev_obj {\n\tstruct list_head list;\n\tstruct net_device *orig_dev;\n\tenum switchdev_obj_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n};\n\nstruct switchdev_obj_mrp {\n\tstruct switchdev_obj obj;\n\tstruct net_device *p_port;\n\tstruct net_device *s_port;\n\tu32 ring_id;\n\tu16 prio;\n};\n\nstruct switchdev_obj_port_mdb {\n\tstruct switchdev_obj obj;\n\tunsigned char addr[6];\n\tu16 vid;\n};\n\nstruct switchdev_obj_port_vlan {\n\tstruct switchdev_obj obj;\n\tu16 flags;\n\tu16 vid;\n\tbool changed;\n};\n\nstruct switchdev_obj_ring_role_mrp {\n\tstruct switchdev_obj obj;\n\tu8 ring_role;\n\tu32 ring_id;\n\tu8 sw_backup;\n};\n\nstruct swmii_regs {\n\tu16 bmsr;\n\tu16 lpa;\n\tu16 lpagb;\n\tu16 estat;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct swoc_info {\n\t__u8 rev;\n\t__u8 reserved[8];\n\t__u16 LinuxSKU;\n\t__u16 LinuxVer;\n\t__u8 reserved2[47];\n} __attribute__((packed));\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tbool pt_port_open;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct sync_fence_info {\n\tchar obj_name[32];\n\tchar driver_name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u64 timestamp_ns;\n};\n\nstruct sync_file {\n\tstruct file *file;\n\tchar user_name[32];\n\tstruct list_head sync_file_list;\n\twait_queue_head_t wq;\n\tlong unsigned int flags;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct sync_file_info {\n\tchar name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u32 num_fences;\n\t__u32 pad;\n\t__u64 sync_fence_info;\n};\n\nstruct sync_merge_data {\n\tchar name[32];\n\t__s32 fd2;\n\t__s32 fence;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct sync_set_deadline {\n\t__u64 deadline_ns;\n\t__u64 pad;\n};\n\nstruct sync_struct {\n\tstruct mcpm_sync_struct clusters[4];\n};\n\nstruct syncobj_eventfd_entry {\n\tstruct list_head node;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tstruct drm_syncobj *syncobj;\n\tstruct eventfd_ctx *ev_fd_ctx;\n\tu64 point;\n\tu32 flags;\n\tlong: 32;\n};\n\nstruct syncobj_wait_entry {\n\tstruct list_head node;\n\tstruct task_struct *task;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tlong: 32;\n\tu64 point;\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct sysc_config {\n\tu32 sysc_val;\n\tu32 syss_mask;\n\tu8 midlemodes;\n\tu8 sidlemodes;\n\tu8 srst_udelay;\n\tu32 quirks;\n};\n\nstruct ti_sysc_cookie {\n\tvoid *data;\n\tvoid *clkdm;\n};\n\nstruct ti_sysc_module_data;\n\nstruct sysc_capabilities;\n\nstruct sysc {\n\tstruct device *dev;\n\tlong: 32;\n\tu64 module_pa;\n\tu32 module_size;\n\tvoid *module_va;\n\tint offsets[3];\n\tstruct ti_sysc_module_data *mdata;\n\tstruct clk **clocks;\n\tconst char **clock_roles;\n\tint nr_clocks;\n\tstruct reset_control *rsts;\n\tconst char *legacy_mode;\n\tconst struct sysc_capabilities *cap;\n\tstruct sysc_config cfg;\n\tstruct ti_sysc_cookie cookie;\n\tconst char *name;\n\tu32 revision;\n\tu32 sysconfig;\n\tunsigned int reserved: 1;\n\tunsigned int enabled: 1;\n\tunsigned int needs_resume: 1;\n\tunsigned int child_needs_resume: 1;\n\tstruct delayed_work idle_work;\n\tvoid (*pre_reset_quirk)(struct sysc *);\n\tvoid (*post_reset_quirk)(struct sysc *);\n\tvoid (*reset_done_quirk)(struct sysc *);\n\tvoid (*module_enable_quirk)(struct sysc *);\n\tvoid (*module_disable_quirk)(struct sysc *);\n\tvoid (*module_unlock_quirk)(struct sysc *);\n\tvoid (*module_lock_quirk)(struct sysc *);\n};\n\nstruct sysc_address {\n\tlong unsigned int base;\n\tstruct list_head node;\n};\n\nstruct sysc_capabilities {\n\tconst enum ti_sysc_module_type type;\n\tconst u32 sysc_mask;\n\tconst struct sysc_regbits *regbits;\n\tconst u32 mod_quirks;\n};\n\nstruct sysc_dts_quirk {\n\tconst char *name;\n\tu32 mask;\n};\n\nstruct sysc_module {\n\tstruct sysc *ddata;\n\tstruct list_head node;\n};\n\nstruct sysc_regbits {\n\ts8 midle_shift;\n\ts8 clkact_shift;\n\ts8 sidle_shift;\n\ts8 enwkup_shift;\n\ts8 srst_shift;\n\ts8 autoidle_shift;\n\ts8 dmadisable_shift;\n\ts8 emufree_shift;\n};\n\nstruct sysc_revision_quirk {\n\tconst char *name;\n\tu32 base;\n\tint rev_offset;\n\tint sysc_offset;\n\tint syss_offset;\n\tu32 revision;\n\tu32 revision_mask;\n\tu32 quirks;\n};\n\nstruct sysc_soc_info {\n\tlong unsigned int general_purpose: 1;\n\tenum sysc_soc soc;\n\tstruct mutex list_lock;\n\tstruct list_head disabled_modules;\n\tstruct list_head restored_modules;\n\tstruct notifier_block nb;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_user_dispatch {};\n\nstruct syscfg_reset_channel {\n\tstruct regmap_field *reset;\n\tstruct regmap_field *ack;\n};\n\nstruct syscfg_reset_channel_data {\n\tconst char *compatible;\n\tstruct reg_field reset;\n\tstruct reg_field ack;\n};\n\nstruct syscfg_reset_controller {\n\tstruct reset_controller_dev rst;\n\tbool active_low;\n\tstruct syscfg_reset_channel *channels;\n};\n\nstruct syscfg_reset_controller_data {\n\tbool wait_for_ack;\n\tbool active_low;\n\tint nr_channels;\n\tconst struct syscfg_reset_channel_data *channels;\n};\n\nstruct syscon {\n\tstruct device_node *np;\n\tstruct regmap *regmap;\n\tstruct reset_control *reset;\n\tstruct list_head list;\n};\n\nstruct syscon_gpio_data {\n\tunsigned int flags;\n\tunsigned int bit_count;\n\tunsigned int dat_bit_offset;\n\tunsigned int dir_bit_offset;\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n};\n\nstruct syscon_gpio_priv {\n\tstruct gpio_chip chip;\n\tstruct regmap *syscon;\n\tconst struct syscon_gpio_data *data;\n\tu32 dreg_offset;\n\tu32 dir_reg_offset;\n};\n\nstruct syscon_poweroff_data {\n\tstruct regmap *map;\n\tu32 offset;\n\tu32 value;\n\tu32 mask;\n};\n\nstruct syscon_reboot_context {\n\tstruct regmap *map;\n\tconst struct reboot_data *rd;\n\tstruct reboot_mode_bits catchall;\n\tstruct notifier_block restart_handler;\n};\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysfb_display_info {\n\tstruct screen_info screen;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[8];\n};\n\nstruct sysmmu_variant;\n\nstruct sysmmu_drvdata {\n\tstruct device *sysmmu;\n\tstruct device *master;\n\tstruct device_link *link;\n\tvoid *sfrbase;\n\tstruct clk *clk;\n\tstruct clk *aclk;\n\tstruct clk *pclk;\n\tstruct clk *clk_master;\n\tspinlock_t lock;\n\tbool active;\n\tstruct exynos_iommu_domain *domain;\n\tstruct list_head domain_node;\n\tstruct list_head owner_node;\n\tphys_addr_t pgtable;\n\tunsigned int version;\n\tstruct iommu_device iommu;\n\tconst struct sysmmu_variant *variant;\n\tbool has_vcr;\n};\n\nstruct sysmmu_fault {\n\tsysmmu_iova_t addr;\n\tconst char *name;\n\tunsigned int type;\n};\n\nstruct sysmmu_v1_fault_info {\n\tshort unsigned int addr_reg;\n\tconst char *name;\n\tunsigned int type;\n};\n\nstruct sysmmu_variant {\n\tu32 pt_base;\n\tu32 flush_all;\n\tu32 flush_entry;\n\tu32 flush_range;\n\tu32 flush_start;\n\tu32 flush_end;\n\tu32 int_status;\n\tu32 int_clear;\n\tu32 fault_va;\n\tu32 fault_info;\n\tint (*get_fault_info)(struct sysmmu_drvdata *, unsigned int, struct sysmmu_fault *);\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[24];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tunsigned int shift;\n\tunsigned int shift_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[24];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tlong: 32;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct tag_header {\n\t__u32 size;\n\t__u32 tag;\n};\n\nstruct tag_core {\n\t__u32 flags;\n\t__u32 pagesize;\n\t__u32 rootdev;\n};\n\nstruct tag_mem32 {\n\t__u32 size;\n\t__u32 start;\n};\n\nstruct tag_videotext {\n\t__u8 x;\n\t__u8 y;\n\t__u16 video_page;\n\t__u8 video_mode;\n\t__u8 video_cols;\n\t__u16 video_ega_bx;\n\t__u8 video_lines;\n\t__u8 video_isvga;\n\t__u16 video_points;\n};\n\nstruct tag_ramdisk {\n\t__u32 flags;\n\t__u32 size;\n\t__u32 start;\n};\n\nstruct tag_initrd {\n\t__u32 start;\n\t__u32 size;\n};\n\nstruct tag_serialnr {\n\t__u32 low;\n\t__u32 high;\n};\n\nstruct tag_revision {\n\t__u32 rev;\n};\n\nstruct tag_videolfb {\n\t__u16 lfb_width;\n\t__u16 lfb_height;\n\t__u16 lfb_depth;\n\t__u16 lfb_linelength;\n\t__u32 lfb_base;\n\t__u32 lfb_size;\n\t__u8 red_size;\n\t__u8 red_pos;\n\t__u8 green_size;\n\t__u8 green_pos;\n\t__u8 blue_size;\n\t__u8 blue_pos;\n\t__u8 rsvd_size;\n\t__u8 rsvd_pos;\n};\n\nstruct tag_cmdline {\n\tchar cmdline[1];\n};\n\nstruct tag_acorn {\n\t__u32 memc_control_reg;\n\t__u32 vram_pages;\n\t__u8 sounddefault;\n\t__u8 adfsdrives;\n};\n\nstruct tag_memclk {\n\t__u32 fmemclk;\n};\n\nstruct tag {\n\tstruct tag_header hdr;\n\tunion {\n\t\tstruct tag_core core;\n\t\tstruct tag_mem32 mem;\n\t\tstruct tag_videotext videotext;\n\t\tstruct tag_ramdisk ramdisk;\n\t\tstruct tag_initrd initrd;\n\t\tstruct tag_serialnr serialnr;\n\t\tstruct tag_revision revision;\n\t\tstruct tag_videolfb videolfb;\n\t\tstruct tag_cmdline cmdline;\n\t\tstruct tag_acorn acorn;\n\t\tstruct tag_memclk memclk;\n\t} u;\n};\n\nstruct tagtable {\n\t__u32 tag;\n\tint (*parse)(const struct tag *);\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tatomic_long_t load_avg;\n\tlong: 32;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tlong: 32;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct vfp_hard_struct {\n\t__u64 fpregs[32];\n\t__u32 fpexc;\n\t__u32 fpscr;\n\t__u32 fpinst;\n\t__u32 fpinst2;\n\t__u32 cpu;\n\tlong: 32;\n};\n\nunion vfp_state {\n\tstruct vfp_hard_struct hard;\n};\n\nstruct thread_info {\n\tlong unsigned int flags;\n\tint preempt_count;\n\t__u32 cpu;\n\t__u32 cpu_domain;\n\tstruct cpu_context_save cpu_context;\n\t__u32 abi_syscall;\n\tlong unsigned int tp_value[2];\n\tlong: 32;\n\tunion fp_state fpstate;\n\tlong: 32;\n\tunion vfp_state vfpstate;\n\tlong unsigned int thumbee_state;\n\tlong: 32;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {};\n\nstruct thread_struct {\n\tlong unsigned int address;\n\tlong unsigned int trap_no;\n\tlong unsigned int error_code;\n\tstruct debug_info debug;\n};\n\nstruct uprobe_task;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tlong: 32;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tlong: 32;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct task_group *sched_task_group;\n\tstruct callback_head sched_throttle_work;\n\tstruct list_head throttle_node;\n\tbool throttled;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sched_statistics stats;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int brk_randomized: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tlong: 32;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tlong: 32;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tu8 perf_recursion[4];\n\tstruct perf_event_context *perf_event_ctxp;\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct perf_ctx_data *perf_ctx_data;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tlong unsigned int trace_recursion;\n\tstruct uprobe_task *utask;\n\tstruct kmap_ctrl kmap_ctrl;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\tstruct vm_struct *stack_vm_area;\n\trefcount_t stack_refcount;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tstruct thread_struct thread;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tlong: 32;\n\tstruct tcf_t tcfa_tm;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_cbs_qopt_offload {\n\tu8 enable;\n\ts32 queue;\n\ts32 hicredit;\n\ts32 locredit;\n\ts32 idleslope;\n\ts32 sendslope;\n};\n\nstruct tc_clkevt_device {\n\tstruct clock_event_device clkevt;\n\tstruct clk *clk;\n\tu32 rate;\n\tvoid *regs;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct tc_cls_u32_hnode {\n\tu32 handle;\n\tu32 prio;\n\tunsigned int divisor;\n};\n\nstruct tcf_exts;\n\nstruct tc_u32_sel;\n\nstruct tc_cls_u32_knode {\n\tstruct tcf_exts *exts;\n\tstruct tcf_result *res;\n\tstruct tc_u32_sel *sel;\n\tu32 handle;\n\tu32 val;\n\tu32 mask;\n\tu32 link_handle;\n\tu8 fshift;\n};\n\nstruct tc_cls_u32_offload {\n\tstruct flow_cls_common_offload common;\n\tenum tc_clsu32_command command;\n\tunion {\n\t\tstruct tc_cls_u32_knode knode;\n\t\tstruct tc_cls_u32_hnode hnode;\n\t};\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_etf_qopt_offload {\n\tu8 enable;\n\ts32 queue;\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_mqprio_caps {\n\tbool validate_queue_counts: 1;\n};\n\nstruct tc_mqprio_qopt {\n\t__u8 num_tc;\n\t__u8 prio_tc_map[16];\n\t__u8 hw;\n\t__u16 count[16];\n\t__u16 offset[16];\n};\n\nstruct tc_mqprio_qopt_offload {\n\tstruct tc_mqprio_qopt qopt;\n\tstruct netlink_ext_ack *extack;\n\tu16 mode;\n\tu16 shaper;\n\tu32 flags;\n\tu64 min_rate[16];\n\tu64 max_rate[16];\n\tlong unsigned int preemptible_tcs;\n\tlong: 32;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tc_taprio_caps {\n\tbool supports_queue_max_sdu: 1;\n\tbool gate_mask_per_txq: 1;\n\tbool broken_mqprio: 1;\n};\n\nstruct tc_taprio_qopt_stats {\n\tu64 window_drops;\n\tu64 tx_overruns;\n};\n\nstruct tc_taprio_qopt_queue_stats {\n\tint queue;\n\tlong: 32;\n\tstruct tc_taprio_qopt_stats stats;\n};\n\nstruct tc_taprio_sched_entry {\n\tu8 command;\n\tu32 gate_mask;\n\tu32 interval;\n};\n\nstruct tc_taprio_qopt_offload {\n\tenum tc_taprio_qopt_cmd cmd;\n\tlong: 32;\n\tunion {\n\t\tstruct tc_taprio_qopt_stats stats;\n\t\tstruct tc_taprio_qopt_queue_stats queue_stats;\n\t\tstruct {\n\t\t\tstruct tc_mqprio_qopt_offload mqprio;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t\tlong: 32;\n\t\t\tktime_t base_time;\n\t\t\tu64 cycle_time;\n\t\t\tu64 cycle_time_extension;\n\t\t\tu32 max_sdu[16];\n\t\t\tsize_t num_entries;\n\t\t\tstruct tc_taprio_sched_entry entries[0];\n\t\t\tlong: 32;\n\t\t};\n\t};\n};\n\nstruct tc_u32_key {\n\t__be32 mask;\n\t__be32 val;\n\tint off;\n\tint offmask;\n};\n\nstruct tc_u32_sel_hdr {\n\tunsigned char flags;\n\tunsigned char offshift;\n\tunsigned char nkeys;\n\t__be16 offmask;\n\t__u16 off;\n\tshort int offoff;\n\tshort int hoff;\n\t__be32 hmask;\n};\n\nstruct tc_u32_sel {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char flags;\n\t\t\tunsigned char offshift;\n\t\t\tunsigned char nkeys;\n\t\t\t__be16 offmask;\n\t\t\t__u16 off;\n\t\t\tshort int offoff;\n\t\t\tshort int hoff;\n\t\t\t__be32 hmask;\n\t\t};\n\t\tstruct tc_u32_sel_hdr hdr;\n\t};\n\tstruct tc_u32_key keys[0];\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_exts {\n\tint action;\n\tint police;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_walker;\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcon_ch1_clk {\n\tstruct clk_hw hw;\n\tspinlock_t lock;\n\tvoid *reg;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tlong: 32;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tlong: 32;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tlong: 32;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n\tlong: 32;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tlong: 32;\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tlong: 32;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t};\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 ae: 1;\n\t__u16 res1: 3;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tlong: 32;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n\tlong: 32;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tlong: 32;\n};\n\nstruct td {\n\t__hc32 hwINFO;\n\t__hc32 hwCBP;\n\t__hc32 hwNextTD;\n\t__hc32 hwBE;\n\t__hc16 hwPSW[2];\n\t__u8 index;\n\tstruct ed *ed;\n\tstruct td *td_hash;\n\tstruct td *next_dl_td;\n\tstruct urb *urb;\n\tdma_addr_t td_dma;\n\tdma_addr_t data_dma;\n\tstruct list_head td_list;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct td_node {\n\tstruct list_head td;\n\tdma_addr_t dma;\n\tstruct ci_hw_td *ptr;\n\tint td_remaining_size;\n};\n\nstruct tee_bnxt_fw_private {\n\tstruct device *dev;\n\tstruct tee_context *ctx;\n\tu32 session_id;\n\tstruct tee_shm *fw_shm_pool;\n};\n\nstruct tee_client_device_id {\n\tuuid_t uuid;\n};\n\nstruct tee_client_device {\n\tstruct tee_client_device_id id;\n\tstruct device dev;\n};\n\nstruct tee_client_driver {\n\tint (*probe)(struct tee_client_device *);\n\tvoid (*remove)(struct tee_client_device *);\n\tvoid (*shutdown)(struct tee_client_device *);\n\tconst struct tee_client_device_id *id_table;\n\tstruct device_driver driver;\n};\n\nstruct tee_context {\n\tstruct tee_device *teedev;\n\tvoid *data;\n\tstruct kref refcount;\n\tbool releasing;\n\tbool supp_nowait;\n\tbool cap_memref_null;\n};\n\nstruct tee_driver_ops;\n\nstruct tee_desc {\n\tconst char *name;\n\tconst struct tee_driver_ops *ops;\n\tstruct module *owner;\n\tu32 flags;\n};\n\nstruct tee_device {\n\tchar name[32];\n\tconst struct tee_desc *desc;\n\tint id;\n\tunsigned int flags;\n\tlong: 32;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tsize_t num_users;\n\tstruct completion c_no_users;\n\tstruct mutex mutex;\n\tstruct idr idr;\n\tstruct tee_shm_pool *pool;\n\tlong: 32;\n};\n\nstruct tee_ioctl_open_session_arg;\n\nstruct tee_ioctl_invoke_arg;\n\nstruct tee_ioctl_object_invoke_arg;\n\nstruct tee_driver_ops {\n\tvoid (*get_version)(struct tee_device *, struct tee_ioctl_version_data *);\n\tint (*get_tee_revision)(struct tee_device *, char *, size_t);\n\tint (*open)(struct tee_context *);\n\tvoid (*close_context)(struct tee_context *);\n\tvoid (*release)(struct tee_context *);\n\tint (*open_session)(struct tee_context *, struct tee_ioctl_open_session_arg *, struct tee_param *);\n\tint (*close_session)(struct tee_context *, u32);\n\tint (*system_session)(struct tee_context *, u32);\n\tint (*invoke_func)(struct tee_context *, struct tee_ioctl_invoke_arg *, struct tee_param *);\n\tint (*object_invoke_func)(struct tee_context *, struct tee_ioctl_object_invoke_arg *, struct tee_param *);\n\tint (*cancel_req)(struct tee_context *, u32, u32);\n\tint (*supp_recv)(struct tee_context *, u32 *, u32 *, struct tee_param *);\n\tint (*supp_send)(struct tee_context *, u32, u32, struct tee_param *);\n\tint (*shm_register)(struct tee_context *, struct tee_shm *, struct page **, size_t, long unsigned int);\n\tint (*shm_unregister)(struct tee_context *, struct tee_shm *);\n};\n\nstruct tee_ioctl_param {\n\t__u64 attr;\n\t__u64 a;\n\t__u64 b;\n\t__u64 c;\n};\n\nstruct tee_iocl_supp_recv_arg {\n\t__u32 func;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_iocl_supp_send_arg {\n\t__u32 ret;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_buf_data {\n\t__u64 buf_ptr;\n\t__u64 buf_len;\n};\n\nstruct tee_ioctl_cancel_arg {\n\t__u32 cancel_id;\n\t__u32 session;\n};\n\nstruct tee_ioctl_close_session_arg {\n\t__u32 session;\n};\n\nstruct tee_ioctl_invoke_arg {\n\t__u32 func;\n\t__u32 session;\n\t__u32 cancel_id;\n\t__u32 ret;\n\t__u32 ret_origin;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_object_invoke_arg {\n\t__u64 id;\n\t__u32 op;\n\t__u32 ret;\n\t__u32 num_params;\n\tlong: 32;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_open_session_arg {\n\t__u8 uuid[16];\n\t__u8 clnt_uuid[16];\n\t__u32 clnt_login;\n\t__u32 cancel_id;\n\t__u32 session;\n\t__u32 ret;\n\t__u32 ret_origin;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_shm_alloc_data {\n\t__u64 size;\n\t__u32 flags;\n\t__s32 id;\n};\n\nstruct tee_ioctl_shm_register_data {\n\t__u64 addr;\n\t__u64 length;\n\t__u32 flags;\n\t__s32 id;\n};\n\nstruct tee_ioctl_shm_register_fd_data {\n\t__s64 fd;\n\t__u64 size;\n\t__u32 flags;\n\t__s32 id;\n};\n\nstruct tee_ioctl_version_data {\n\t__u32 impl_id;\n\t__u32 impl_caps;\n\t__u32 gen_caps;\n};\n\nstruct tee_param_memref {\n\tsize_t shm_offs;\n\tsize_t size;\n\tstruct tee_shm *shm;\n};\n\nstruct tee_param_objref {\n\tu64 id;\n\tu64 flags;\n};\n\nstruct tee_param_ubuf {\n\tvoid *uaddr;\n\tsize_t size;\n};\n\nstruct tee_param_value {\n\tu64 a;\n\tu64 b;\n\tu64 c;\n};\n\nstruct tee_param {\n\tu64 attr;\n\tunion {\n\t\tstruct tee_param_memref memref;\n\t\tstruct tee_param_objref objref;\n\t\tstruct tee_param_ubuf ubuf;\n\t\tstruct tee_param_value value;\n\t} u;\n};\n\nstruct tee_protmem_pool_ops {\n\tint (*alloc)(struct tee_protmem_pool *, struct sg_table *, size_t, size_t *);\n\tvoid (*free)(struct tee_protmem_pool *, struct sg_table *);\n\tint (*update_shm)(struct tee_protmem_pool *, struct sg_table *, size_t, struct tee_shm *, struct tee_shm **);\n\tvoid (*destroy_pool)(struct tee_protmem_pool *);\n};\n\nstruct tee_protmem_static_pool {\n\tstruct tee_protmem_pool pool;\n\tstruct gen_pool *gen_pool;\n\tphys_addr_t pa_base;\n};\n\nstruct tee_shm {\n\tstruct tee_context *ctx;\n\tphys_addr_t paddr;\n\tvoid *kaddr;\n\tsize_t size;\n\tunsigned int offset;\n\tstruct page **pages;\n\tsize_t num_pages;\n\trefcount_t refcount;\n\tu32 flags;\n\tint id;\n\tu64 sec_world_id;\n};\n\nstruct tee_shm_dmabuf_ref {\n\tstruct tee_shm shm;\n\tsize_t offset;\n\tstruct dma_buf *dmabuf;\n\tstruct tee_shm *parent_shm;\n\tlong: 32;\n};\n\nstruct tee_shm_pool_ops;\n\nstruct tee_shm_pool {\n\tconst struct tee_shm_pool_ops *ops;\n\tvoid *private_data;\n};\n\nstruct tee_shm_pool_ops {\n\tint (*alloc)(struct tee_shm_pool *, struct tee_shm *, size_t, size_t);\n\tvoid (*free)(struct tee_shm_pool *, struct tee_shm *);\n\tvoid (*destroy_pool)(struct tee_shm_pool *);\n};\n\nstruct tegra124_cpufreq_priv {\n\tstruct clk *cpu_clk;\n\tstruct clk *pllp_clk;\n\tstruct clk *pllx_clk;\n\tstruct clk *dfll_clk;\n\tstruct platform_device *cpufreq_dt_pdev;\n};\n\nstruct tegra124_xusb_fuse_calibration {\n\tu32 hs_curr_level[3];\n\tu32 hs_iref_cap;\n\tu32 hs_term_range_adj;\n\tu32 hs_squelch_level;\n};\n\nstruct tegra_xusb_padctl_soc;\n\nstruct tegra_xusb_pad;\n\nstruct tegra_xusb_padctl {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct mutex lock;\n\tstruct reset_control *rst;\n\tconst struct tegra_xusb_padctl_soc *soc;\n\tstruct tegra_xusb_pad *pcie;\n\tstruct tegra_xusb_pad *sata;\n\tstruct tegra_xusb_pad *ulpi;\n\tstruct tegra_xusb_pad *usb2;\n\tstruct tegra_xusb_pad *hsic;\n\tstruct list_head ports;\n\tstruct list_head lanes;\n\tstruct list_head pads;\n\tunsigned int enable;\n\tstruct clk *clk;\n\tstruct regulator_bulk_data *supplies;\n};\n\nstruct tegra124_xusb_padctl {\n\tstruct tegra_xusb_padctl base;\n\tstruct tegra124_xusb_fuse_calibration fuse;\n};\n\nstruct tegra20_mc_client_stat {\n\tunsigned int events;\n\tunsigned int arb_high_prio;\n\tunsigned int arb_timeout;\n\tunsigned int arb_bandwidth;\n\tunsigned int rd_wr_change;\n\tunsigned int successive;\n\tunsigned int page_miss;\n\tunsigned int auto_precharge;\n\tunsigned int arb_bank_aa;\n\tunsigned int arb_bank_bb;\n};\n\nstruct tegra20_mc_stat_gather {\n\tunsigned int pri_filter;\n\tunsigned int pri_event;\n\tunsigned int result;\n\tunsigned int client;\n\tunsigned int event;\n\tbool client_enb;\n};\n\nstruct tegra_mc;\n\nstruct tegra20_mc_stat {\n\tstruct tegra20_mc_stat_gather gather0;\n\tstruct tegra20_mc_stat_gather gather1;\n\tunsigned int sample_time_usec;\n\tconst struct tegra_mc *mc;\n};\n\nstruct tegra_ahb {\n\tvoid *regs;\n\tstruct device *dev;\n\tu32 ctx[0];\n};\n\nstruct tegra_ahci_ops {\n\tint (*init)(struct ahci_host_priv *);\n};\n\nstruct tegra_ahci_soc;\n\nstruct tegra_ahci_priv {\n\tstruct platform_device *pdev;\n\tvoid *sata_regs;\n\tvoid *sata_aux_regs;\n\tstruct reset_control *sata_rst;\n\tstruct reset_control *sata_oob_rst;\n\tstruct reset_control *sata_cold_rst;\n\tstruct clk *sata_clk;\n\tstruct regulator_bulk_data *supplies;\n\tconst struct tegra_ahci_soc *soc;\n};\n\nstruct tegra_ahci_regs {\n\tunsigned int nvoob_comma_cnt_mask;\n\tunsigned int nvoob_comma_cnt_val;\n};\n\nstruct tegra_ahci_soc {\n\tconst char * const *supply_names;\n\tu32 num_supplies;\n\tbool supports_devslp;\n\tbool has_sata_oob_rst;\n\tconst struct tegra_ahci_ops *ops;\n\tconst struct tegra_ahci_regs *regs;\n};\n\nstruct tegra_audio2x_clk_initdata {\n\tchar *parent;\n\tchar *gate_name;\n\tchar *name_2x;\n\tchar *div_name;\n\tint clk_id;\n\tint clk_num;\n\tu8 div_offset;\n};\n\nstruct tegra_clk_pll_params;\n\nstruct tegra_audio_clk_info {\n\tchar *name;\n\tstruct tegra_clk_pll_params *pll_params;\n\tint clk_id;\n\tchar *parent;\n};\n\nstruct tegra_audio_clk_initdata {\n\tchar *gate_name;\n\tchar *mux_name;\n\tu32 offset;\n\tint gate_clk_id;\n\tint mux_clk_id;\n};\n\nstruct tegra_baud_tolerance {\n\tu32 lower_range_baud;\n\tu32 upper_range_baud;\n\ts32 tolerance;\n};\n\nstruct tegra_bo_tiling {\n\tenum tegra_bo_tiling_mode mode;\n\tlong unsigned int value;\n\tenum tegra_bo_sector_layout sector_layout;\n};\n\nstruct tegra_bo {\n\tstruct drm_gem_object gem;\n\tstruct host1x_bo base;\n\tlong unsigned int flags;\n\tstruct sg_table *sgt;\n\tdma_addr_t iova;\n\tvoid *vaddr;\n\tstruct dma_buf *dma_buf;\n\tstruct drm_mm_node *mm;\n\tlong unsigned int num_pages;\n\tstruct page **pages;\n\tsize_t size;\n\tstruct tegra_bo_tiling tiling;\n};\n\nstruct tegra_clk {\n\tint dt_id;\n\tbool present;\n};\n\nstruct tegra_clk_device {\n\tstruct notifier_block clk_nb;\n\tstruct device *dev;\n\tstruct clk_hw *hw;\n\tstruct mutex lock;\n};\n\nstruct tegra_clk_duplicate {\n\tint clk_id;\n\tstruct clk_lookup lookup;\n};\n\ntypedef long int tegra20_clk_emc_round_cb(long unsigned int, long unsigned int, long unsigned int, void *);\n\nstruct tegra_clk_emc {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tbool mc_same_freq;\n\tbool want_low_jitter;\n\ttegra20_clk_emc_round_cb *round_cb;\n\tvoid *cb_arg;\n};\n\nstruct tegra_emc;\n\ntypedef int tegra124_emc_prepare_timing_change_cb(struct tegra_emc *, long unsigned int);\n\ntypedef void tegra124_emc_complete_timing_change_cb(struct tegra_emc *, long unsigned int);\n\nstruct tegra_clk_emc___2 {\n\tstruct clk_hw hw;\n\tvoid *clk_regs;\n\tstruct clk *prev_parent;\n\tbool changing_timing;\n\tstruct device_node *emc_node;\n\tstruct tegra_emc *emc;\n\tint num_timings;\n\tstruct emc_timing *timings;\n\tspinlock_t *lock;\n\ttegra124_emc_prepare_timing_change_cb *prepare_timing_change;\n\ttegra124_emc_complete_timing_change_cb *complete_timing_change;\n};\n\nstruct tegra_clk_frac_div {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 flags;\n\tu8 shift;\n\tu8 width;\n\tu8 frac_width;\n\tspinlock_t *lock;\n};\n\nstruct tegra_clk_init_table {\n\tunsigned int clk_id;\n\tunsigned int parent_id;\n\tlong unsigned int rate;\n\tint state;\n};\n\nstruct tegra_clk_periph_regs;\n\nstruct tegra_clk_periph_gate {\n\tu32 magic;\n\tstruct clk_hw hw;\n\tvoid *clk_base;\n\tu8 flags;\n\tint clk_num;\n\tint *enable_refcnt;\n\tconst struct tegra_clk_periph_regs *regs;\n};\n\nstruct tegra_clk_periph {\n\tu32 magic;\n\tstruct clk_hw hw;\n\tstruct clk_mux mux;\n\tstruct tegra_clk_frac_div divider;\n\tstruct tegra_clk_periph_gate gate;\n\tconst struct clk_ops *mux_ops;\n\tconst struct clk_ops *div_ops;\n\tconst struct clk_ops *gate_ops;\n};\n\nstruct tegra_clk_periph_fixed {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tconst struct tegra_clk_periph_regs *regs;\n\tunsigned int mul;\n\tunsigned int div;\n\tunsigned int num;\n};\n\nstruct tegra_clk_periph_regs {\n\tu32 enb_reg;\n\tu32 enb_set_reg;\n\tu32 enb_clr_reg;\n\tu32 rst_reg;\n\tu32 rst_set_reg;\n\tu32 rst_clr_reg;\n};\n\nstruct tegra_clk_pll {\n\tstruct clk_hw hw;\n\tvoid *clk_base;\n\tvoid *pmc;\n\tspinlock_t *lock;\n\tstruct tegra_clk_pll_params *params;\n};\n\nstruct tegra_clk_pll_freq_table {\n\tlong unsigned int input_rate;\n\tlong unsigned int output_rate;\n\tu32 n;\n\tu32 m;\n\tu8 p;\n\tu8 cpcon;\n\tu16 sdm_data;\n};\n\nstruct tegra_clk_pll_out {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 enb_bit_idx;\n\tu8 rst_bit_idx;\n\tspinlock_t *lock;\n\tu8 flags;\n};\n\nstruct tegra_clk_pll_params {\n\tlong unsigned int input_min;\n\tlong unsigned int input_max;\n\tlong unsigned int cf_min;\n\tlong unsigned int cf_max;\n\tlong unsigned int vco_min;\n\tlong unsigned int vco_max;\n\tu32 base_reg;\n\tu32 misc_reg;\n\tu32 lock_reg;\n\tu32 lock_mask;\n\tu32 lock_enable_bit_idx;\n\tu32 iddq_reg;\n\tu32 iddq_bit_idx;\n\tu32 reset_reg;\n\tu32 reset_bit_idx;\n\tu32 sdm_din_reg;\n\tu32 sdm_din_mask;\n\tu32 sdm_ctrl_reg;\n\tu32 sdm_ctrl_en_mask;\n\tu32 ssc_ctrl_reg;\n\tu32 ssc_ctrl_en_mask;\n\tu32 aux_reg;\n\tu32 dyn_ramp_reg;\n\tu32 ext_misc_reg[6];\n\tu32 pmc_divnm_reg;\n\tu32 pmc_divp_reg;\n\tu32 flags;\n\tint stepa_shift;\n\tint stepb_shift;\n\tint lock_delay;\n\tint max_p;\n\tbool defaults_set;\n\tconst struct pdiv_map *pdiv_tohw;\n\tstruct div_nmp *div_nmp;\n\tstruct tegra_clk_pll_freq_table *freq_table;\n\tlong unsigned int fixed_rate;\n\tu16 mdiv_default;\n\tu32 (*round_p_to_pdiv)(u32, u32 *);\n\tvoid (*set_gain)(struct tegra_clk_pll_freq_table *);\n\tint (*calc_rate)(struct clk_hw *, struct tegra_clk_pll_freq_table *, long unsigned int, long unsigned int);\n\tlong unsigned int (*adjust_vco)(struct tegra_clk_pll_params *, long unsigned int);\n\tvoid (*set_defaults)(struct tegra_clk_pll *);\n\tint (*dyn_ramp)(struct tegra_clk_pll *, struct tegra_clk_pll_freq_table *);\n\tint (*pre_rate_change)(void);\n\tvoid (*post_rate_change)(void);\n};\n\nstruct tegra_sor;\n\nstruct tegra_clk_sor_pad {\n\tstruct clk_hw hw;\n\tstruct tegra_sor *sor;\n};\n\nstruct tegra_clk_super_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tstruct tegra_clk_frac_div frac_div;\n\tconst struct clk_ops *div_ops;\n\tu8 width;\n\tu8 flags;\n\tu8 div2_index;\n\tu8 pllx_index;\n\tspinlock_t *lock;\n};\n\nstruct tegra_clk_sync_source {\n\tstruct clk_hw hw;\n\tlong unsigned int rate;\n\tlong unsigned int max_rate;\n};\n\nstruct tegra_core_opp_params {\n\tbool init_state;\n};\n\nstruct tegra_cpu_car_ops {\n\tvoid (*wait_for_reset)(u32);\n\tvoid (*put_in_reset)(u32);\n\tvoid (*out_of_reset)(u32);\n\tvoid (*enable_clock)(u32);\n\tvoid (*disable_clock)(u32);\n\tbool (*rail_off_ready)(void);\n\tvoid (*suspend)(void);\n\tvoid (*resume)(void);\n};\n\nstruct tegra_dc_stats {\n\tlong unsigned int frames;\n\tlong unsigned int vblank;\n\tlong unsigned int underflow;\n\tlong unsigned int overflow;\n\tlong unsigned int frames_total;\n\tlong unsigned int vblank_total;\n\tlong unsigned int underflow_total;\n\tlong unsigned int overflow_total;\n};\n\nstruct tegra_output;\n\nstruct tegra_dc_soc_info;\n\nstruct tegra_dc {\n\tstruct host1x_client client;\n\tstruct host1x_syncpt *syncpt;\n\tstruct device *dev;\n\tstruct drm_crtc base;\n\tunsigned int powergate;\n\tint pipe;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tvoid *regs;\n\tint irq;\n\tstruct tegra_output *rgb;\n\tstruct tegra_dc_stats stats;\n\tstruct list_head list;\n\tstruct drm_info_list *debugfs_files;\n\tconst struct tegra_dc_soc_info *soc;\n\tbool has_opp_table;\n};\n\nstruct tegra_windowgroup_soc;\n\nstruct tegra_dc_soc_info {\n\tbool supports_background_color;\n\tbool supports_interlacing;\n\tbool supports_cursor;\n\tbool supports_block_linear;\n\tbool supports_sector_layout;\n\tbool has_legacy_blending;\n\tunsigned int pitch_align;\n\tbool has_powergate;\n\tbool coupled_pm;\n\tbool has_nvdisplay;\n\tconst struct tegra_windowgroup_soc *wgrps;\n\tunsigned int num_wgrps;\n\tconst u32 *primary_formats;\n\tunsigned int num_primary_formats;\n\tconst u32 *overlay_formats;\n\tunsigned int num_overlay_formats;\n\tconst u64 *modifiers;\n\tbool has_win_a_without_filters;\n\tbool has_win_b_vfilter_mem_client;\n\tbool has_win_c_without_vert_filter;\n\tbool plane_tiled_memory_bandwidth_x2;\n\tbool has_pll_d2_out0;\n};\n\nstruct tegra_dc_state {\n\tstruct drm_crtc_state base;\n\tstruct clk *clk;\n\tlong unsigned int pclk;\n\tunsigned int div;\n\tu32 planes;\n};\n\nstruct tegra_dc_window {\n\tstruct {\n\t\tunsigned int x;\n\t\tunsigned int y;\n\t\tunsigned int w;\n\t\tunsigned int h;\n\t} src;\n\tstruct {\n\t\tunsigned int x;\n\t\tunsigned int y;\n\t\tunsigned int w;\n\t\tunsigned int h;\n\t} dst;\n\tunsigned int bits_per_pixel;\n\tunsigned int stride[2];\n\tlong unsigned int base[3];\n\tunsigned int zpos;\n\tbool reflect_x;\n\tbool reflect_y;\n\tstruct tegra_bo_tiling tiling;\n\tu32 format;\n\tu32 swap;\n};\n\nstruct tegra_devclk {\n\tint dt_id;\n\tchar *dev_id;\n\tchar *con_id;\n};\n\nstruct tegra_dfll_soc_data;\n\nstruct tegra_dfll {\n\tstruct device *dev;\n\tstruct tegra_dfll_soc_data *soc;\n\tvoid *base;\n\tvoid *i2c_base;\n\tvoid *i2c_controller_base;\n\tvoid *lut_base;\n\tstruct regulator *vdd_reg;\n\tstruct clk *soc_clk;\n\tstruct clk *ref_clk;\n\tstruct clk *i2c_clk;\n\tstruct clk *dfll_clk;\n\tstruct reset_control *dfll_rst;\n\tstruct reset_control *dvco_rst;\n\tlong unsigned int ref_rate;\n\tlong unsigned int i2c_clk_rate;\n\tlong unsigned int dvco_rate_min;\n\tenum dfll_ctrl_mode mode;\n\tenum dfll_tune_range tune_range;\n\tstruct dentry *debugfs_dir;\n\tstruct clk_hw dfll_clk_hw;\n\tconst char *output_clock_name;\n\tstruct dfll_rate_req last_req;\n\tlong unsigned int last_unrounded_rate;\n\tu32 droop_ctrl;\n\tu32 sample_rate;\n\tu32 force_mode;\n\tu32 cf;\n\tu32 ci;\n\tu32 cg;\n\tbool cg_scale;\n\tu32 i2c_fs_rate;\n\tu32 i2c_reg;\n\tu32 i2c_slave_addr;\n\tunsigned int lut[33];\n\tlong unsigned int lut_uv[33];\n\tint lut_size;\n\tu8 lut_bottom;\n\tu8 lut_min;\n\tu8 lut_max;\n\tu8 lut_safe;\n\tenum tegra_dfll_pmu_if pmu_if;\n\tlong unsigned int pwm_rate;\n\tstruct pinctrl *pwm_pin;\n\tstruct pinctrl_state *pwm_enable_state;\n\tstruct pinctrl_state *pwm_disable_state;\n\tu32 reg_init_uV;\n};\n\nstruct tegra_dfll_soc_data {\n\tstruct device *dev;\n\tlong unsigned int max_freq;\n\tconst struct cvb_table *cvb;\n\tstruct rail_alignment alignment;\n\tvoid (*init_clock_trimmers)(void);\n\tvoid (*set_clock_trimmers_high)(void);\n\tvoid (*set_clock_trimmers_low)(void);\n};\n\nstruct tegra_display_hub_soc;\n\nstruct tegra_windowgroup;\n\nstruct tegra_display_hub {\n\tstruct drm_private_obj base;\n\tstruct host1x_client client;\n\tstruct clk *clk_disp;\n\tstruct clk *clk_dsc;\n\tstruct clk *clk_hub;\n\tstruct reset_control *rst;\n\tunsigned int num_heads;\n\tstruct clk **clk_heads;\n\tconst struct tegra_display_hub_soc *soc;\n\tstruct tegra_windowgroup *wgrps;\n};\n\nstruct tegra_display_hub_soc {\n\tunsigned int num_wgrps;\n\tbool supports_dsc;\n};\n\nstruct tegra_display_hub_state {\n\tstruct drm_private_state base;\n\tstruct tegra_dc *dc;\n\tlong unsigned int rate;\n\tstruct clk *clk;\n};\n\nstruct tegra_dma_channel;\n\ntypedef void (*dma_isr_handler)(struct tegra_dma_channel *, bool);\n\nstruct tegra_dma_channel_regs {\n\tu32 csr;\n\tu32 ahb_ptr;\n\tu32 apb_ptr;\n\tu32 ahb_seq;\n\tu32 apb_seq;\n\tu32 wcount;\n};\n\nstruct tegra_dma;\n\nstruct tegra_dma_channel {\n\tstruct dma_chan dma_chan;\n\tchar name[12];\n\tbool config_init;\n\tunsigned int id;\n\tvoid *chan_addr;\n\tspinlock_t lock;\n\tbool busy;\n\tstruct tegra_dma *tdma;\n\tbool cyclic;\n\tstruct list_head free_sg_req;\n\tstruct list_head pending_sg_req;\n\tstruct list_head free_dma_desc;\n\tstruct list_head cb_desc;\n\tdma_isr_handler isr_handler;\n\tstruct tasklet_struct tasklet;\n\tunsigned int slave_id;\n\tstruct dma_slave_config dma_sconfig;\n\tstruct tegra_dma_channel_regs channel_reg;\n\tstruct wait_queue_head wq;\n};\n\nstruct tegra_dma_chip_data;\n\nstruct tegra_dma {\n\tstruct dma_device dma_dev;\n\tstruct device *dev;\n\tstruct clk *dma_clk;\n\tstruct reset_control *rst;\n\tspinlock_t global_lock;\n\tvoid *base_addr;\n\tconst struct tegra_dma_chip_data *chip_data;\n\tu32 global_pause_count;\n\tstruct tegra_dma_channel channels[0];\n};\n\nstruct tegra_dma_chip_data {\n\tunsigned int nr_channels;\n\tunsigned int channel_reg_size;\n\tunsigned int max_dma_count;\n\tbool support_channel_pause;\n\tbool support_separate_wcount_reg;\n};\n\nstruct tegra_dma_desc {\n\tstruct dma_async_tx_descriptor txd;\n\tunsigned int bytes_requested;\n\tunsigned int bytes_transferred;\n\tenum dma_status dma_status;\n\tstruct list_head node;\n\tstruct list_head tx_list;\n\tstruct list_head cb_node;\n\tunsigned int cb_count;\n};\n\nstruct tegra_dma_sg_req {\n\tstruct tegra_dma_channel_regs ch_regs;\n\tunsigned int req_len;\n\tbool configured;\n\tbool last_sg;\n\tstruct list_head node;\n\tstruct tegra_dma_desc *dma_desc;\n\tunsigned int words_xferred;\n};\n\nstruct tegra_dpaux_soc;\n\nstruct tegra_dpaux {\n\tstruct drm_dp_aux aux;\n\tstruct device *dev;\n\tconst struct tegra_dpaux_soc *soc;\n\tvoid *regs;\n\tint irq;\n\tstruct tegra_output *output;\n\tstruct reset_control *rst;\n\tstruct clk *clk_parent;\n\tstruct clk *clk;\n\tstruct regulator *vdd;\n\tstruct completion complete;\n\tstruct work_struct work;\n\tstruct list_head list;\n\tstruct pinctrl_dev *pinctrl;\n\tstruct pinctrl_desc desc;\n\tlong: 32;\n};\n\nstruct tegra_dpaux_soc {\n\tunsigned int cmh;\n\tunsigned int drvz;\n\tunsigned int drvi;\n};\n\nstruct tegra_drm {\n\tstruct drm_device *drm;\n\tstruct iommu_domain *domain;\n\tbool use_explicit_iommu;\n\tstruct mutex mm_lock;\n\tstruct drm_mm mm;\n\tstruct {\n\t\tstruct iova_domain domain;\n\t\tlong unsigned int shift;\n\t\tlong unsigned int limit;\n\t} carveout;\n\tstruct mutex clients_lock;\n\tstruct list_head clients;\n\tunsigned int hmask;\n\tunsigned int vmask;\n\tunsigned int pitch_align;\n\tunsigned int num_crtcs;\n\tstruct tegra_display_hub *hub;\n};\n\nstruct tegra_drm_context;\n\nstruct tegra_drm_client_ops {\n\tint (*open_channel)(struct tegra_drm_client *, struct tegra_drm_context *);\n\tvoid (*close_channel)(struct tegra_drm_context *);\n\tint (*is_addr_reg)(struct device *, u32, u32);\n\tint (*is_valid_class)(u32);\n\tint (*submit)(struct tegra_drm_context *, struct drm_tegra_submit *, struct drm_device *, struct drm_file *);\n\tint (*get_streamid_offset)(struct tegra_drm_client *, u32 *);\n\tint (*can_use_memory_ctx)(struct tegra_drm_client *, bool *);\n};\n\nstruct tegra_drm_context {\n\tstruct tegra_drm_client *client;\n\tstruct host1x_channel *channel;\n\tunsigned int id;\n\tstruct xarray mappings;\n\tstruct host1x_memory_context *memory_context;\n};\n\nstruct tegra_drm_file {\n\tstruct idr legacy_contexts;\n\tstruct mutex lock;\n\tstruct xarray contexts;\n\tstruct xarray syncpoints;\n};\n\nstruct tegra_drm_submit_data;\n\nstruct tegra_drm_firewall {\n\tstruct tegra_drm_submit_data *submit;\n\tstruct tegra_drm_client *client;\n\tu32 *data;\n\tu32 pos;\n\tu32 end;\n\tu32 class;\n};\n\nstruct tegra_drm_mapping {\n\tstruct kref ref;\n\tstruct host1x_bo_mapping *map;\n\tstruct host1x_bo *bo;\n\tdma_addr_t iova;\n\tdma_addr_t iova_end;\n};\n\nstruct tegra_drm_used_mapping;\n\nstruct tegra_drm_submit_data {\n\tstruct tegra_drm_used_mapping *used_mappings;\n\tu32 num_used_mappings;\n};\n\nstruct tegra_drm_used_mapping {\n\tstruct tegra_drm_mapping *mapping;\n\tu32 flags;\n};\n\nstruct tegra_output {\n\tstruct device_node *of_node;\n\tstruct device *dev;\n\tstruct drm_bridge *bridge;\n\tstruct drm_panel *panel;\n\tstruct i2c_adapter *ddc;\n\tconst struct drm_edid *drm_edid;\n\tstruct cec_notifier *cec;\n\tunsigned int hpd_irq;\n\tstruct gpio_desc *hpd_gpio;\n\tstruct drm_encoder encoder;\n\tstruct drm_connector connector;\n};\n\nstruct tegra_mipi_device;\n\nstruct tegra_dsi {\n\tstruct host1x_client client;\n\tstruct tegra_output output;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct reset_control *rst;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_lp;\n\tstruct clk *clk;\n\tstruct drm_info_list *debugfs_files;\n\tlong unsigned int flags;\n\tenum mipi_dsi_pixel_format format;\n\tunsigned int lanes;\n\tstruct tegra_mipi_device *mipi;\n\tstruct mipi_dsi_host host;\n\tstruct regulator *vdd;\n\tunsigned int video_fifo_depth;\n\tunsigned int host_fifo_depth;\n\tstruct tegra_dsi *master;\n\tstruct tegra_dsi *slave;\n};\n\nstruct tegra_dsi_state {\n\tstruct drm_connector_state base;\n\tstruct mipi_dphy_timing timing;\n\tlong unsigned int period;\n\tunsigned int vrefresh;\n\tunsigned int lanes;\n\tlong unsigned int pclk;\n\tlong unsigned int bclk;\n\tenum tegra_dsi_format format;\n\tunsigned int mul;\n\tunsigned int div;\n};\n\nstruct tegra_emc {\n\tstruct device *dev;\n\tstruct tegra_mc *mc;\n\tstruct icc_provider provider;\n\tstruct notifier_block clk_nb;\n\tstruct clk *clk;\n\tvoid *regs;\n\tunsigned int irq;\n\tbool bad_state;\n\tstruct emc_timing___4 *new_timing;\n\tstruct emc_timing___4 *timings;\n\tunsigned int num_timings;\n\tu32 mc_override;\n\tu32 emc_cfg;\n\tu32 emc_mode_1;\n\tu32 emc_mode_2;\n\tu32 emc_mode_reset;\n\tbool vref_cal_toggle: 1;\n\tbool zcal_long: 1;\n\tbool dll_on: 1;\n\tstruct {\n\t\tstruct dentry *root;\n\t\tlong unsigned int min_rate;\n\t\tlong unsigned int max_rate;\n\t} debugfs;\n\tstruct emc_rate_request requested_rate[2];\n\tstruct mutex rate_lock;\n\tbool mrr_error;\n};\n\nstruct tegra_emc___2 {\n\tstruct device *dev;\n\tstruct tegra_mc *mc;\n\tstruct icc_provider provider;\n\tstruct notifier_block clk_nb;\n\tstruct clk *clk;\n\tvoid *regs;\n\tunsigned int dram_bus_width;\n\tstruct emc_timing___2 *timings;\n\tunsigned int num_timings;\n\tstruct {\n\t\tstruct dentry *root;\n\t\tlong unsigned int min_rate;\n\t\tlong unsigned int max_rate;\n\t} debugfs;\n\tstruct emc_rate_request requested_rate[3];\n\tstruct mutex rate_lock;\n\tstruct devfreq_simple_ondemand_data ondemand_data;\n\tunion lpddr2_basic_config4 basic_conf4;\n\tunsigned int manufacturer_id;\n\tunsigned int revision_id1;\n\tunsigned int revision_id2;\n\tbool mrr_error;\n};\n\nstruct tegra_emc___3 {\n\tstruct device *dev;\n\tstruct tegra_mc *mc;\n\tvoid *regs;\n\tstruct clk *clk;\n\tenum emc_dram_type___2 dram_type;\n\tunsigned int dram_bus_width;\n\tunsigned int dram_num;\n\tstruct emc_timing___3 last_timing;\n\tstruct emc_timing___3 *timings;\n\tunsigned int num_timings;\n\tstruct {\n\t\tstruct dentry *root;\n\t\tlong unsigned int min_rate;\n\t\tlong unsigned int max_rate;\n\t} debugfs;\n\tstruct icc_provider provider;\n\tstruct emc_rate_request requested_rate[2];\n\tstruct mutex rate_lock;\n};\n\nstruct tegra_eqos {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct reset_control *rst;\n\tstruct gpio_desc *reset;\n};\n\nstruct tegra_function {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct tegra_fuse_soc;\n\nstruct tegra_fuse {\n\tstruct device *dev;\n\tvoid *base;\n\tphys_addr_t phys;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tu32 (*read_early)(struct tegra_fuse *, unsigned int);\n\tu32 (*read)(struct tegra_fuse *, unsigned int);\n\tconst struct tegra_fuse_soc *soc;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct completion wait;\n\t\tstruct dma_chan *chan;\n\t\tstruct dma_slave_config config;\n\t\tdma_addr_t phys;\n\t\tu32 *virt;\n\t} apbdma;\n\tstruct nvmem_device *nvmem;\n\tstruct nvmem_cell_lookup *lookups;\n};\n\nstruct tegra_fuse_info {\n\tu32 (*read)(struct tegra_fuse *, unsigned int);\n\tunsigned int size;\n\tunsigned int spare;\n};\n\nstruct tegra_sku_info;\n\nstruct tegra_fuse_soc {\n\tvoid (*init)(struct tegra_fuse *);\n\tvoid (*speedo_init)(struct tegra_sku_info *);\n\tint (*probe)(struct tegra_fuse *);\n\tconst struct tegra_fuse_info *info;\n\tconst struct nvmem_cell_lookup *lookups;\n\tunsigned int num_lookups;\n\tconst struct nvmem_cell_info *cells;\n\tunsigned int num_cells;\n\tconst struct nvmem_keepout *keepouts;\n\tunsigned int num_keepouts;\n\tconst struct attribute_group *soc_attr_group;\n\tbool clk_suspend_on;\n};\n\nstruct tegra_gpio_bank {\n\tunsigned int bank;\n\traw_spinlock_t lvl_lock[4];\n\tspinlock_t dbc_lock[4];\n\tu32 cnf[4];\n\tu32 out[4];\n\tu32 oe[4];\n\tu32 int_enb[4];\n\tu32 int_lvl[4];\n\tu32 wake_enb[4];\n\tu32 dbc_enb[4];\n\tu32 dbc_cnt[4];\n};\n\nstruct tegra_gpio_soc_config;\n\nstruct tegra_gpio_info {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct tegra_gpio_bank *bank_info;\n\tconst struct tegra_gpio_soc_config *soc;\n\tstruct gpio_chip gc;\n\tu32 bank_count;\n\tunsigned int *irqs;\n};\n\nstruct tegra_gpio_soc_config {\n\tbool debounce_supported;\n\tu32 bank_stride;\n\tu32 upper_offset;\n};\n\nstruct tegra_hda_format {\n\tunsigned int sample_rate;\n\tunsigned int channels;\n\tunsigned int bits;\n\tbool pcm;\n};\n\nstruct tegra_hdmi_config;\n\nstruct tegra_hdmi {\n\tstruct host1x_client client;\n\tstruct tegra_output output;\n\tstruct device *dev;\n\tstruct regulator *hdmi;\n\tstruct regulator *pll;\n\tstruct regulator *vdd;\n\tvoid *regs;\n\tunsigned int irq;\n\tstruct clk *clk_parent;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tconst struct tegra_hdmi_config *config;\n\tunsigned int audio_source;\n\tstruct tegra_hda_format format;\n\tunsigned int pixel_clock;\n\tbool stereo;\n\tbool dvi;\n\tstruct drm_info_list *debugfs_files;\n\tstruct platform_device *audio_pdev;\n\tstruct mutex audio_lock;\n};\n\nstruct tegra_hdmi_audio_config {\n\tunsigned int n;\n\tunsigned int cts;\n\tunsigned int aval;\n};\n\nstruct tmds_config;\n\nstruct tegra_hdmi_config {\n\tconst struct tmds_config *tmds;\n\tunsigned int num_tmds;\n\tlong unsigned int fuse_override_offset;\n\tu32 fuse_override_value;\n\tbool has_sor_io_peak_current;\n\tbool has_hda;\n\tbool has_hbr;\n};\n\nstruct tegra_i2c_hw_feature;\n\nstruct tegra_i2c_dev {\n\tstruct device *dev;\n\tlong: 32;\n\tstruct i2c_adapter adapter;\n\tconst struct tegra_i2c_hw_feature *hw;\n\tunsigned int cont_id;\n\tunsigned int irq;\n\tphys_addr_t base_phys;\n\tvoid *base;\n\tstruct clk_bulk_data clocks[2];\n\tunsigned int nclocks;\n\tstruct clk *div_clk;\n\tstruct i2c_timings timings;\n\tstruct completion msg_complete;\n\tsize_t msg_buf_remaining;\n\tunsigned int msg_len;\n\tint msg_err;\n\tu8 *msg_buf;\n\tstruct completion dma_complete;\n\tstruct dma_chan *dma_chan;\n\tunsigned int dma_buf_size;\n\tstruct device *dma_dev;\n\tdma_addr_t dma_phys;\n\tvoid *dma_buf;\n\tbool multimaster_mode;\n\tbool atomic_mode;\n\tbool dma_mode;\n\tbool msg_read;\n\tbool is_dvc;\n\tbool is_vi;\n};\n\nstruct tegra_i2c_hw_feature {\n\tbool has_continue_xfer_support;\n\tbool has_per_pkt_xfer_complete_irq;\n\tbool has_config_load_reg;\n\tu32 clk_divisor_hs_mode;\n\tu32 clk_divisor_std_mode;\n\tu32 clk_divisor_fast_mode;\n\tu32 clk_divisor_fast_plus_mode;\n\tbool has_multi_master_mode;\n\tbool has_slcg_override_reg;\n\tbool has_mst_fifo;\n\tbool has_mst_reset;\n\tconst struct i2c_adapter_quirks *quirks;\n\tbool supports_bus_clear;\n\tbool has_apb_dma;\n\tu32 tlow_std_mode;\n\tu32 thigh_std_mode;\n\tu32 tlow_fast_mode;\n\tu32 thigh_fast_mode;\n\tu32 tlow_fastplus_mode;\n\tu32 thigh_fastplus_mode;\n\tu32 tlow_hs_mode;\n\tu32 thigh_hs_mode;\n\tu32 setup_hold_time_std_mode;\n\tu32 setup_hold_time_fast_mode;\n\tu32 setup_hold_time_fastplus_mode;\n\tu32 setup_hold_time_hs_mode;\n\tbool has_interface_timing_reg;\n\tbool enable_hs_mode_support;\n\tbool has_mutex;\n};\n\nstruct tegra_ictlr_info {\n\tvoid *base[6];\n\tu32 cop_ier[6];\n\tu32 cop_iep[6];\n\tu32 cpu_ier[6];\n\tu32 cpu_iep[6];\n\tu32 ictlr_wake_mask[6];\n};\n\nstruct tegra_ictlr_soc {\n\tunsigned int num_ictlrs;\n};\n\nstruct tegra_io_pad_soc {\n\tenum tegra_io_pad id;\n\tunsigned int dpd;\n\tunsigned int request;\n\tunsigned int status;\n\tunsigned int voltage;\n\tconst char *name;\n};\n\nstruct tegra_kbc_pin_cfg {\n\tenum tegra_pin_type type;\n\tunsigned char num;\n};\n\nstruct tegra_kbc_hw_support;\n\nstruct tegra_kbc {\n\tstruct device *dev;\n\tunsigned int debounce_cnt;\n\tunsigned int repeat_cnt;\n\tstruct tegra_kbc_pin_cfg pin_cfg[24];\n\tconst struct matrix_keymap_data *keymap_data;\n\tbool wakeup;\n\tvoid *mmio;\n\tstruct input_dev *idev;\n\tint irq;\n\tspinlock_t lock;\n\tunsigned int repoll_dly;\n\tlong unsigned int cp_dly_jiffies;\n\tunsigned int cp_to_wkup_dly;\n\tbool use_fn_map;\n\tbool use_ghost_filter;\n\tbool keypress_caused_wake;\n\tshort unsigned int keycode[256];\n\tshort unsigned int current_keys[8];\n\tunsigned int num_pressed_keys;\n\tu32 wakeup_key;\n\tstruct timer_list timer;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tconst struct tegra_kbc_hw_support *hw_support;\n\tint max_keys;\n\tint num_rows_and_columns;\n};\n\nstruct tegra_kbc_hw_support {\n\tint max_rows;\n\tint max_columns;\n};\n\nstruct tegra_lp1_iram {\n\tvoid *start_addr;\n\tvoid *end_addr;\n};\n\nstruct tegra_bpmp;\n\nstruct tegra_smmu;\n\nstruct tegra_mc_soc;\n\nstruct tegra_mc_timing;\n\nstruct tegra_mc {\n\tstruct tegra_bpmp *bpmp;\n\tstruct device *dev;\n\tstruct tegra_smmu *smmu;\n\tvoid *regs;\n\tvoid *bcast_ch_regs;\n\tvoid **ch_regs;\n\tstruct clk *clk;\n\tint irq;\n\tconst struct tegra_mc_soc *soc;\n\tlong unsigned int tick;\n\tstruct tegra_mc_timing *timings;\n\tunsigned int num_timings;\n\tunsigned int num_channels;\n\tbool bwmgr_mrq_supported;\n\tstruct reset_controller_dev reset;\n\tstruct icc_provider provider;\n\tspinlock_t lock;\n\tstruct {\n\t\tstruct dentry *root;\n\t} debugfs;\n};\n\nstruct tegra_mc_client {\n\tunsigned int id;\n\tunsigned int bpmp_id;\n\tenum tegra_icc_client_type type;\n\tconst char *name;\n\tunion {\n\t\tunsigned int swgroup;\n\t\tunsigned int sid;\n\t};\n\tunsigned int fifo_size;\n\tstruct {\n\t\tstruct {\n\t\t\tunsigned int reg;\n\t\t\tunsigned int bit;\n\t\t} smmu;\n\t\tstruct {\n\t\t\tunsigned int reg;\n\t\t\tunsigned int shift;\n\t\t\tunsigned int mask;\n\t\t\tunsigned int def;\n\t\t} la;\n\t\tstruct {\n\t\t\tunsigned int override;\n\t\t\tunsigned int security;\n\t\t} sid;\n\t} regs;\n};\n\nstruct tegra_mc_icc_ops {\n\tint (*set)(struct icc_node *, struct icc_node *);\n\tint (*aggregate)(struct icc_node *, u32, u32, u32, u32 *, u32 *);\n\tstruct icc_node * (*xlate)(const struct of_phandle_args *, void *);\n\tstruct icc_node_data * (*xlate_extended)(const struct of_phandle_args *, void *);\n\tint (*get_bw)(struct icc_node *, u32 *, u32 *);\n};\n\nstruct tegra_mc_ops {\n\tint (*probe)(struct tegra_mc *);\n\tvoid (*remove)(struct tegra_mc *);\n\tint (*resume)(struct tegra_mc *);\n\tirqreturn_t (*handle_irq)(int, void *);\n\tint (*probe_device)(struct tegra_mc *, struct device *);\n};\n\nstruct tegra_mc_reset {\n\tconst char *name;\n\tlong unsigned int id;\n\tunsigned int control;\n\tunsigned int status;\n\tunsigned int reset;\n\tunsigned int bit;\n};\n\nstruct tegra_mc_reset_ops {\n\tint (*hotreset_assert)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*hotreset_deassert)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*block_dma)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tbool (*dma_idling)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*unblock_dma)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*reset_status)(struct tegra_mc *, const struct tegra_mc_reset *);\n};\n\nstruct tegra_smmu_soc;\n\nstruct tegra_mc_soc {\n\tconst struct tegra_mc_client *clients;\n\tunsigned int num_clients;\n\tconst long unsigned int *emem_regs;\n\tunsigned int num_emem_regs;\n\tunsigned int num_address_bits;\n\tunsigned int atom_size;\n\tunsigned int num_carveouts;\n\tu16 client_id_mask;\n\tu8 num_channels;\n\tconst struct tegra_smmu_soc *smmu;\n\tu32 intmask;\n\tu32 ch_intmask;\n\tu32 global_intstatus_channel_shift;\n\tbool has_addr_hi_reg;\n\tconst struct tegra_mc_reset_ops *reset_ops;\n\tconst struct tegra_mc_reset *resets;\n\tunsigned int num_resets;\n\tconst struct tegra_mc_icc_ops *icc_ops;\n\tconst struct tegra_mc_ops *ops;\n};\n\nstruct tegra_mc_timing {\n\tlong unsigned int rate;\n\tu32 *emem_data;\n};\n\nstruct tegra_mipi_soc;\n\nstruct tegra_mipi {\n\tconst struct tegra_mipi_soc *soc;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct mutex lock;\n\tstruct clk *clk;\n\tlong unsigned int usage_count;\n};\n\nstruct tegra_mipi_device {\n\tstruct platform_device *pdev;\n\tstruct tegra_mipi *mipi;\n\tstruct device *device;\n\tlong unsigned int pads;\n};\n\nstruct tegra_mipi_pad {\n\tlong unsigned int data;\n\tlong unsigned int clk;\n};\n\nstruct tegra_mipi_soc {\n\tbool has_clk_lane;\n\tconst struct tegra_mipi_pad *pads;\n\tunsigned int num_pads;\n\tbool clock_enable_override;\n\tbool needs_vclamp_ref;\n\tu8 pad_drive_down_ref;\n\tu8 pad_drive_up_ref;\n\tu8 pad_vclamp_level;\n\tu8 pad_vauxp_level;\n\tu8 hspdos;\n\tu8 hspuos;\n\tu8 termos;\n\tu8 hsclkpdos;\n\tu8 hsclkpuos;\n};\n\nstruct tegra_msi {\n\tlong unsigned int used[8];\n\tstruct irq_domain *domain;\n\tstruct mutex map_lock;\n\traw_spinlock_t mask_lock;\n\tvoid *virt;\n\tdma_addr_t phys;\n\tint irq;\n};\n\nstruct tegra_pcie_soc;\n\nstruct tegra_pcie {\n\tstruct device *dev;\n\tvoid *pads;\n\tvoid *afi;\n\tvoid *cfg;\n\tint irq;\n\tstruct resource cs;\n\tstruct clk *pex_clk;\n\tstruct clk *afi_clk;\n\tstruct clk *pll_e;\n\tstruct clk *cml_clk;\n\tstruct reset_control *pex_rst;\n\tstruct reset_control *afi_rst;\n\tstruct reset_control *pcie_xrst;\n\tbool legacy_phy;\n\tstruct phy *phy;\n\tstruct tegra_msi msi;\n\tstruct list_head ports;\n\tu32 xbar_config;\n\tstruct regulator_bulk_data *supplies;\n\tunsigned int num_supplies;\n\tconst struct tegra_pcie_soc *soc;\n\tstruct dentry *debugfs;\n};\n\nstruct tegra_pcie_port {\n\tstruct tegra_pcie *pcie;\n\tstruct device_node *np;\n\tstruct list_head list;\n\tstruct resource regs;\n\tvoid *base;\n\tunsigned int index;\n\tunsigned int lanes;\n\tstruct phy **phys;\n\tstruct gpio_desc *reset_gpio;\n};\n\nstruct tegra_pcie_port_soc {\n\tstruct {\n\t\tu8 turnoff_bit;\n\t\tu8 ack_bit;\n\t} pme;\n};\n\nstruct tegra_pcie_soc {\n\tunsigned int num_ports;\n\tconst struct tegra_pcie_port_soc *ports;\n\tunsigned int msi_base_shift;\n\tlong unsigned int afi_pex2_ctrl;\n\tu32 pads_pll_ctl;\n\tu32 tx_ref_sel;\n\tu32 pads_refclk_cfg0;\n\tu32 pads_refclk_cfg1;\n\tu32 update_fc_threshold;\n\tbool has_pex_clkreq_en;\n\tbool has_pex_bias_ctrl;\n\tbool has_intr_prsnt_sense;\n\tbool has_cml_clk;\n\tbool has_gen2;\n\tbool force_pca_enable;\n\tbool program_uphy;\n\tbool update_clamp_threshold;\n\tbool program_deskew_time;\n\tbool update_fc_timer;\n\tbool has_cache_bars;\n\tstruct {\n\t\tstruct {\n\t\t\tu32 rp_ectl_2_r1;\n\t\t\tu32 rp_ectl_4_r1;\n\t\t\tu32 rp_ectl_5_r1;\n\t\t\tu32 rp_ectl_6_r1;\n\t\t\tu32 rp_ectl_2_r2;\n\t\t\tu32 rp_ectl_4_r2;\n\t\t\tu32 rp_ectl_5_r2;\n\t\t\tu32 rp_ectl_6_r2;\n\t\t} regs;\n\t\tbool enable;\n\t} ectl;\n};\n\nstruct tegra_pd {\n\tu32 val[1024];\n};\n\nstruct tegra_periph_init_data {\n\tconst char *name;\n\tint clk_id;\n\tunion {\n\t\tconst char * const *parent_names;\n\t\tconst char *parent_name;\n\t} p;\n\tint num_parents;\n\tstruct tegra_clk_periph periph;\n\tu32 offset;\n\tconst char *con_id;\n\tconst char *dev_id;\n\tlong unsigned int flags;\n};\n\nstruct tegra_phy_soc_config {\n\tbool utmi_pll_config_in_car_module;\n\tbool has_hostpc;\n\tbool requires_usbmode_setup;\n\tbool requires_extra_tuning_parameters;\n\tbool requires_pmc_ao_power_up;\n\tu32 uhsic_registers_offset;\n\tu32 uhsic_tx_rtune;\n\tu32 uhsic_pts_value;\n\tu32 portsc1_offset;\n};\n\nstruct tegra_pingroup;\n\nstruct tegra_pinctrl_soc_data {\n\tunsigned int ngpios;\n\tconst char *gpio_compatible;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst char * const *functions;\n\tunsigned int nfunctions;\n\tconst struct tegra_pingroup *groups;\n\tunsigned int ngroups;\n\tbool hsm_in_mux;\n\tbool schmitt_in_mux;\n\tbool drvtype_in_mux;\n\tbool sfsel_in_mux;\n};\n\nstruct tegra_pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tu8 npins;\n\tu8 funcs[4];\n\ts32 mux_reg;\n\ts32 pupd_reg;\n\ts32 tri_reg;\n\ts32 drv_reg;\n\tu32 mux_bank: 2;\n\tu32 pupd_bank: 2;\n\tu32 tri_bank: 2;\n\tu32 drv_bank: 2;\n\ts32 mux_bit: 6;\n\ts32 pupd_bit: 6;\n\ts32 tri_bit: 6;\n\ts32 einput_bit: 6;\n\ts32 odrain_bit: 6;\n\ts32 lock_bit: 6;\n\ts32 ioreset_bit: 6;\n\ts32 rcv_sel_bit: 6;\n\ts32 hsm_bit: 6;\n\tlong: 2;\n\ts32 sfsel_bit: 6;\n\ts32 schmitt_bit: 6;\n\ts32 lpmd_bit: 6;\n\ts32 drvdn_bit: 6;\n\ts32 drvup_bit: 6;\n\tlong: 2;\n\ts32 slwr_bit: 6;\n\ts32 slwf_bit: 6;\n\ts32 lpdr_bit: 6;\n\ts32 drvtype_bit: 6;\n\ts32 drvdn_width: 6;\n\tlong: 2;\n\ts32 drvup_width: 6;\n\ts32 slwr_width: 6;\n\ts32 slwf_width: 6;\n\tu32 parked_bitmask;\n};\n\nstruct tegra_pingroup_config {\n\tbool is_sfsel;\n};\n\nstruct tegra_plane {\n\tstruct drm_plane base;\n\tstruct tegra_dc *dc;\n\tunsigned int offset;\n\tunsigned int index;\n\tstruct icc_path *icc_mem;\n\tstruct icc_path *icc_mem_vfilter;\n\tlong: 32;\n};\n\nstruct tegra_plane_legacy_blending_state {\n\tbool alpha;\n\tbool top;\n};\n\nstruct tegra_plane_state {\n\tstruct drm_plane_state base;\n\tstruct host1x_bo_mapping *map[3];\n\tdma_addr_t iova[3];\n\tstruct tegra_bo_tiling tiling;\n\tu32 format;\n\tu32 swap;\n\tbool reflect_x;\n\tbool reflect_y;\n\tstruct tegra_plane_legacy_blending_state blending[2];\n\tbool opaque;\n\tu32 total_peak_memory_bandwidth;\n\tu32 peak_memory_bandwidth;\n\tu32 avg_memory_bandwidth;\n};\n\nstruct tegra_pmc_soc;\n\nstruct tegra_pmc {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *wake;\n\tvoid *aotag;\n\tvoid *scratch;\n\tstruct clk *clk;\n\tconst struct tegra_pmc_soc *soc;\n\tbool tz_only;\n\tlong unsigned int rate;\n\tenum tegra_suspend_mode suspend_mode;\n\tu32 cpu_good_time;\n\tu32 cpu_off_time;\n\tu32 core_osc_time;\n\tu32 core_pmu_time;\n\tu32 core_off_time;\n\tbool corereq_high;\n\tbool sysclkreq_high;\n\tbool combined_req;\n\tbool cpu_pwr_good_en;\n\tu32 lp0_vec_phys;\n\tu32 lp0_vec_size;\n\tlong unsigned int powergates_available[1];\n\tstruct mutex powergates_lock;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct irq_domain *domain;\n\tstruct irq_chip irq;\n\tstruct notifier_block clk_nb;\n\tbool core_domain_state_synced;\n\tlong unsigned int *wake_type_level_map;\n\tlong unsigned int *wake_type_dual_edge_map;\n\tlong unsigned int *wake_sw_status_map;\n\tlong unsigned int *wake_cntrl_level_map;\n\tstruct notifier_block reboot_notifier;\n\tstruct syscore syscore;\n\tstruct irq_work wake_work;\n\tu32 *wake_status;\n};\n\nstruct tegra_pmc_core_pd {\n\tstruct generic_pm_domain genpd;\n\tstruct tegra_pmc *pmc;\n\tlong: 32;\n};\n\nstruct tegra_pmc_regs {\n\tunsigned int scratch0;\n\tunsigned int rst_status;\n\tunsigned int rst_source_shift;\n\tunsigned int rst_source_mask;\n\tunsigned int rst_level_shift;\n\tunsigned int rst_level_mask;\n};\n\nstruct tegra_wake_event;\n\nstruct tegra_pmc_soc {\n\tunsigned int num_powergates;\n\tconst char * const *powergates;\n\tunsigned int num_cpu_powergates;\n\tconst u8 *cpu_powergates;\n\tbool has_tsense_reset;\n\tbool has_gpu_clamps;\n\tbool needs_mbist_war;\n\tbool has_impl_33v_pwr;\n\tbool maybe_tz_only;\n\tconst struct tegra_io_pad_soc *io_pads;\n\tunsigned int num_io_pads;\n\tconst struct pinctrl_pin_desc *pin_descs;\n\tunsigned int num_pin_descs;\n\tconst struct tegra_pmc_regs *regs;\n\tvoid (*init)(struct tegra_pmc *);\n\tvoid (*setup_irq_polarity)(struct tegra_pmc *, struct device_node *, bool);\n\tvoid (*set_wake_filters)(struct tegra_pmc *);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*powergate_set)(struct tegra_pmc *, unsigned int, bool);\n\tconst char * const *reset_sources;\n\tunsigned int num_reset_sources;\n\tconst char * const *reset_levels;\n\tunsigned int num_reset_levels;\n\tconst struct tegra_wake_event *wake_events;\n\tunsigned int num_wake_events;\n\tunsigned int max_wake_events;\n\tunsigned int max_wake_vectors;\n\tconst struct pmc_clk_init_data *pmc_clks_data;\n\tunsigned int num_pmc_clks;\n\tbool has_blink_output;\n\tbool has_usb_sleepwalk;\n\tbool supports_core_domain;\n\tbool has_single_mmio_aperture;\n};\n\nstruct tegra_pmx {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tconst struct tegra_pinctrl_soc_data *soc;\n\tstruct tegra_function *functions;\n\tconst char **group_pins;\n\tstruct pinctrl_gpio_range gpio_range;\n\tstruct pinctrl_desc desc;\n\tint nbanks;\n\tvoid **regs;\n\tu32 *backup_regs;\n\tstruct tegra_pingroup_config *pingroup_configs;\n};\n\nstruct tegra_powergate {\n\tstruct generic_pm_domain genpd;\n\tstruct tegra_pmc *pmc;\n\tunsigned int id;\n\tstruct clk **clks;\n\tunsigned int num_clks;\n\tlong unsigned int *clk_rates;\n\tstruct reset_control *reset;\n};\n\nstruct tegra_pt {\n\tu32 val[1024];\n};\n\nstruct tegra_pwm_soc;\n\nstruct tegra_pwm_chip {\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tlong unsigned int clk_rate;\n\tlong unsigned int min_period_ns;\n\tvoid *regs;\n\tconst struct tegra_pwm_soc *soc;\n};\n\nstruct tegra_pwm_soc {\n\tunsigned int num_channels;\n\tlong unsigned int max_frequency;\n};\n\nstruct tegra_regulator_coupler {\n\tstruct regulator_coupler coupler;\n\tstruct regulator_dev *core_rdev;\n\tstruct regulator_dev *cpu_rdev;\n\tstruct regulator_dev *rtc_rdev;\n\tstruct notifier_block reboot_notifier;\n\tstruct notifier_block suspend_notifier;\n\tint core_min_uV;\n\tint cpu_min_uV;\n\tbool sys_reboot_mode_req;\n\tbool sys_reboot_mode;\n\tbool sys_suspend_mode_req;\n\tbool sys_suspend_mode;\n};\n\nstruct tegra_regulator_coupler___2 {\n\tstruct regulator_coupler coupler;\n\tstruct regulator_dev *core_rdev;\n\tstruct regulator_dev *cpu_rdev;\n\tstruct notifier_block reboot_notifier;\n\tstruct notifier_block suspend_notifier;\n\tint core_min_uV;\n\tint cpu_min_uV;\n\tbool sys_reboot_mode_req;\n\tbool sys_reboot_mode;\n\tbool sys_suspend_mode_req;\n\tbool sys_suspend_mode;\n};\n\nstruct tegra_rgb {\n\tstruct tegra_output output;\n\tstruct tegra_dc *dc;\n\tstruct clk *pll_d_out0;\n\tstruct clk *pll_d2_out0;\n\tstruct clk *clk_parent;\n\tstruct clk *clk;\n\tlong: 32;\n};\n\nstruct tegra_rtc_info {\n\tstruct platform_device *pdev;\n\tstruct rtc_device *rtc;\n\tvoid *base;\n\tstruct clk *clk;\n\tint irq;\n\tspinlock_t lock;\n};\n\nstruct tegra_sdmmc_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tspinlock_t *lock;\n\tconst struct clk_ops *gate_ops;\n\tstruct tegra_clk_periph_gate gate;\n\tu8 div_flags;\n};\n\nstruct tegra_sflash_data {\n\tstruct device *dev;\n\tstruct spi_controller *host;\n\tspinlock_t lock;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tvoid *base;\n\tunsigned int irq;\n\tu32 cur_speed;\n\tstruct spi_device *cur_spi;\n\tunsigned int cur_pos;\n\tunsigned int cur_len;\n\tunsigned int bytes_per_word;\n\tunsigned int cur_direction;\n\tunsigned int curr_xfer_words;\n\tunsigned int cur_rx_pos;\n\tunsigned int cur_tx_pos;\n\tu32 tx_status;\n\tu32 rx_status;\n\tu32 status_reg;\n\tu32 def_command_reg;\n\tu32 command_reg;\n\tu32 dma_control_reg;\n\tstruct completion xfer_completion;\n\tstruct spi_transfer *curr_xfer;\n};\n\nstruct tegra_shared_plane {\n\tstruct tegra_plane base;\n\tstruct tegra_windowgroup *wgrp;\n\tlong: 32;\n};\n\nstruct tegra_sku_info {\n\tint sku_id;\n\tint cpu_process_id;\n\tint cpu_speedo_id;\n\tint cpu_speedo_value;\n\tint cpu_iddq_value;\n\tint soc_process_id;\n\tint soc_speedo_id;\n\tint soc_speedo_value;\n\tint gpu_process_id;\n\tint gpu_speedo_id;\n\tint gpu_speedo_value;\n\tenum tegra_revision revision;\n\tenum tegra_platform platform;\n};\n\nstruct tegra_slink_chip_data {\n\tbool cs_hold_time;\n};\n\nstruct tegra_slink_data {\n\tstruct device *dev;\n\tstruct spi_controller *host;\n\tconst struct tegra_slink_chip_data *chip_data;\n\tspinlock_t lock;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tvoid *base;\n\tphys_addr_t phys;\n\tunsigned int irq;\n\tu32 cur_speed;\n\tstruct spi_device *cur_spi;\n\tunsigned int cur_pos;\n\tunsigned int cur_len;\n\tunsigned int words_per_32bit;\n\tunsigned int bytes_per_word;\n\tunsigned int curr_dma_words;\n\tunsigned int cur_direction;\n\tunsigned int cur_rx_pos;\n\tunsigned int cur_tx_pos;\n\tunsigned int dma_buf_size;\n\tunsigned int max_buf_size;\n\tbool is_curr_dma_xfer;\n\tstruct completion rx_dma_complete;\n\tstruct completion tx_dma_complete;\n\tu32 tx_status;\n\tu32 rx_status;\n\tu32 status_reg;\n\tbool is_packed;\n\tu32 packed_size;\n\tu32 command_reg;\n\tu32 command2_reg;\n\tu32 dma_control_reg;\n\tu32 def_command_reg;\n\tu32 def_command2_reg;\n\tstruct completion xfer_completion;\n\tstruct spi_transfer *curr_xfer;\n\tstruct dma_chan *rx_dma_chan;\n\tu32 *rx_dma_buf;\n\tdma_addr_t rx_dma_phys;\n\tstruct dma_async_tx_descriptor *rx_dma_desc;\n\tstruct dma_chan *tx_dma_chan;\n\tu32 *tx_dma_buf;\n\tdma_addr_t tx_dma_phys;\n\tstruct dma_async_tx_descriptor *tx_dma_desc;\n};\n\nstruct tegra_smmu {\n\tvoid *regs;\n\tstruct device *dev;\n\tstruct tegra_mc *mc;\n\tconst struct tegra_smmu_soc *soc;\n\tstruct list_head groups;\n\tlong unsigned int pfn_mask;\n\tlong unsigned int tlb_mask;\n\tlong unsigned int *asids;\n\tstruct mutex lock;\n\tstruct list_head list;\n\tstruct dentry *debugfs;\n\tstruct iommu_device iommu;\n};\n\nstruct tegra_smmu_as {\n\tstruct iommu_domain domain;\n\tstruct tegra_smmu *smmu;\n\tunsigned int use_count;\n\tspinlock_t lock;\n\tu32 *count;\n\tstruct tegra_pt **pts;\n\tstruct tegra_pd *pd;\n\tdma_addr_t pd_dma;\n\tunsigned int id;\n\tu32 attr;\n};\n\nstruct tegra_smmu_group_soc;\n\nstruct tegra_smmu_group {\n\tstruct list_head list;\n\tstruct tegra_smmu *smmu;\n\tconst struct tegra_smmu_group_soc *soc;\n\tstruct iommu_group *group;\n\tunsigned int swgroup;\n};\n\nstruct tegra_smmu_group_soc {\n\tconst char *name;\n\tconst unsigned int *swgroups;\n\tunsigned int num_swgroups;\n};\n\nstruct tegra_smmu_swgroup;\n\nstruct tegra_smmu_soc {\n\tconst struct tegra_mc_client *clients;\n\tunsigned int num_clients;\n\tconst struct tegra_smmu_swgroup *swgroups;\n\tunsigned int num_swgroups;\n\tconst struct tegra_smmu_group_soc *groups;\n\tunsigned int num_groups;\n\tbool supports_round_robin_arbitration;\n\tbool supports_request_limit;\n\tunsigned int num_tlb_lines;\n\tunsigned int num_asids;\n};\n\nstruct tegra_smmu_swgroup {\n\tconst char *name;\n\tunsigned int swgroup;\n\tunsigned int reg;\n};\n\nstruct tegra_sor_soc;\n\nstruct tegra_sor_ops;\n\nstruct tegra_sor_hdmi_settings;\n\nstruct tegra_sor {\n\tstruct host1x_client client;\n\tstruct tegra_output output;\n\tstruct device *dev;\n\tconst struct tegra_sor_soc *soc;\n\tvoid *regs;\n\tunsigned int index;\n\tunsigned int irq;\n\tstruct reset_control *rst;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_safe;\n\tstruct clk *clk_out;\n\tstruct clk *clk_pad;\n\tstruct clk *clk_dp;\n\tstruct clk *clk;\n\tu8 xbar_cfg[5];\n\tstruct drm_dp_link link;\n\tstruct drm_dp_aux *aux;\n\tstruct drm_info_list *debugfs_files;\n\tconst struct tegra_sor_ops *ops;\n\tenum tegra_io_pad pad;\n\tstruct tegra_sor_hdmi_settings *settings;\n\tunsigned int num_settings;\n\tstruct regulator *avdd_io_supply;\n\tstruct regulator *vdd_pll_supply;\n\tstruct regulator *hdmi_supply;\n\tstruct delayed_work scdc;\n\tbool scdc_enabled;\n\tstruct tegra_hda_format format;\n};\n\nstruct tegra_sor_config {\n\tu32 bits_per_pixel;\n\tu32 active_polarity;\n\tu32 active_count;\n\tu32 tu_size;\n\tu32 active_frac;\n\tu32 watermark;\n\tu32 hblank_symbols;\n\tu32 vblank_symbols;\n};\n\nstruct tegra_sor_hdmi_settings {\n\tlong unsigned int frequency;\n\tu8 vcocap;\n\tu8 filter;\n\tu8 ichpmp;\n\tu8 loadadj;\n\tu8 tmds_termadj;\n\tu8 tx_pu_value;\n\tu8 bg_temp_coef;\n\tu8 bg_vref_level;\n\tu8 avdd10_level;\n\tu8 avdd14_level;\n\tu8 sparepll;\n\tu8 drive_current[4];\n\tu8 preemphasis[4];\n};\n\nstruct tegra_sor_ops {\n\tconst char *name;\n\tint (*probe)(struct tegra_sor *);\n\tvoid (*audio_enable)(struct tegra_sor *);\n\tvoid (*audio_disable)(struct tegra_sor *);\n};\n\nstruct tegra_sor_params {\n\tunsigned int num_clocks;\n\tlong: 32;\n\tu64 ratio;\n\tu64 precision;\n\tunsigned int active_polarity;\n\tunsigned int active_count;\n\tunsigned int active_frac;\n\tunsigned int tu_size;\n\tunsigned int error;\n\tlong: 32;\n};\n\nstruct tegra_sor_regs {\n\tunsigned int head_state0;\n\tunsigned int head_state1;\n\tunsigned int head_state2;\n\tunsigned int head_state3;\n\tunsigned int head_state4;\n\tunsigned int head_state5;\n\tunsigned int pll0;\n\tunsigned int pll1;\n\tunsigned int pll2;\n\tunsigned int pll3;\n\tunsigned int dp_padctl0;\n\tunsigned int dp_padctl2;\n};\n\nstruct tegra_sor_soc {\n\tbool supports_lvds;\n\tbool supports_hdmi;\n\tbool supports_dp;\n\tbool supports_audio;\n\tbool supports_hdcp;\n\tconst struct tegra_sor_regs *regs;\n\tbool has_nvdisplay;\n\tconst struct tegra_sor_hdmi_settings *settings;\n\tunsigned int num_settings;\n\tconst u8 *xbar_cfg;\n\tconst u8 *lane_map;\n\tconst u8 (*voltage_swing)[16];\n\tconst u8 (*pre_emphasis)[16];\n\tconst u8 (*post_cursor)[16];\n\tconst u8 (*tx_pu)[16];\n};\n\nstruct tegra_sor_state {\n\tstruct drm_connector_state base;\n\tunsigned int link_speed;\n\tlong unsigned int pclk;\n\tunsigned int bpc;\n\tlong: 32;\n};\n\nstruct tegra_spi_client_data {\n\tint tx_clk_tap_delay;\n\tint rx_clk_tap_delay;\n};\n\nstruct tegra_spi_soc_data;\n\nstruct tegra_spi_data {\n\tstruct device *dev;\n\tstruct spi_controller *host;\n\tspinlock_t lock;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tvoid *base;\n\tphys_addr_t phys;\n\tunsigned int irq;\n\tu32 cur_speed;\n\tstruct spi_device *cur_spi;\n\tstruct spi_device *cs_control;\n\tunsigned int cur_pos;\n\tunsigned int words_per_32bit;\n\tunsigned int bytes_per_word;\n\tunsigned int curr_dma_words;\n\tunsigned int cur_direction;\n\tunsigned int cur_rx_pos;\n\tunsigned int cur_tx_pos;\n\tunsigned int dma_buf_size;\n\tunsigned int max_buf_size;\n\tbool is_curr_dma_xfer;\n\tbool use_hw_based_cs;\n\tstruct completion rx_dma_complete;\n\tstruct completion tx_dma_complete;\n\tu32 tx_status;\n\tu32 rx_status;\n\tu32 status_reg;\n\tbool is_packed;\n\tu32 command1_reg;\n\tu32 dma_control_reg;\n\tu32 def_command1_reg;\n\tu32 def_command2_reg;\n\tu32 spi_cs_timing1;\n\tu32 spi_cs_timing2;\n\tu8 last_used_cs;\n\tstruct completion xfer_completion;\n\tstruct spi_transfer *curr_xfer;\n\tstruct dma_chan *rx_dma_chan;\n\tu32 *rx_dma_buf;\n\tdma_addr_t rx_dma_phys;\n\tstruct dma_async_tx_descriptor *rx_dma_desc;\n\tstruct dma_chan *tx_dma_chan;\n\tu32 *tx_dma_buf;\n\tdma_addr_t tx_dma_phys;\n\tstruct dma_async_tx_descriptor *tx_dma_desc;\n\tconst struct tegra_spi_soc_data *soc_data;\n};\n\nstruct tegra_spi_soc_data {\n\tbool has_intr_mask_reg;\n};\n\nstruct tegra_super_gen_info {\n\tenum tegra_super_gen gen;\n\tconst char **sclk_parents;\n\tconst char **cclk_g_parents;\n\tconst char **cclk_lp_parents;\n\tint num_sclk_parents;\n\tint num_cclk_g_parents;\n\tint num_cclk_lp_parents;\n};\n\nstruct tegra_sync_source_initdata {\n\tchar *name;\n\tlong unsigned int rate;\n\tlong unsigned int max_rate;\n\tint clk_id;\n};\n\nstruct tegra_uart {\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tint line;\n};\n\nstruct tegra_uart_chip_data {\n\tbool tx_fifo_full_status;\n\tbool allow_txfifo_reset_fifo_mode;\n\tbool support_clk_src_div;\n\tbool fifo_mode_enable_status;\n\tint uart_max_port;\n\tint max_dma_burst_bytes;\n\tint error_tolerance_low_range;\n\tint error_tolerance_high_range;\n};\n\nstruct tegra_uart_port {\n\tstruct uart_port uport;\n\tconst struct tegra_uart_chip_data *cdata;\n\tstruct clk *uart_clk;\n\tstruct reset_control *rst;\n\tunsigned int current_baud;\n\tlong unsigned int fcr_shadow;\n\tlong unsigned int mcr_shadow;\n\tlong unsigned int lcr_shadow;\n\tlong unsigned int ier_shadow;\n\tbool rts_active;\n\tint tx_in_progress;\n\tunsigned int tx_bytes;\n\tbool enable_modem_interrupt;\n\tbool rx_timeout;\n\tint rx_in_progress;\n\tint symb_bit;\n\tstruct dma_chan *rx_dma_chan;\n\tstruct dma_chan *tx_dma_chan;\n\tdma_addr_t rx_dma_buf_phys;\n\tdma_addr_t tx_dma_buf_phys;\n\tunsigned char *rx_dma_buf_virt;\n\tunsigned char *tx_dma_buf_virt;\n\tstruct dma_async_tx_descriptor *tx_dma_desc;\n\tstruct dma_async_tx_descriptor *rx_dma_desc;\n\tdma_cookie_t tx_cookie;\n\tdma_cookie_t rx_cookie;\n\tunsigned int tx_bytes_requested;\n\tunsigned int rx_bytes_requested;\n\tstruct tegra_baud_tolerance *baud_tolerance;\n\tint n_adjustable_baud_rates;\n\tint required_rate;\n\tint configured_rate;\n\tbool use_rx_pio;\n\tbool use_tx_pio;\n\tbool rx_dma_active;\n\tlong: 32;\n};\n\nstruct tegra_usb_soc_info;\n\nstruct tegra_usb {\n\tstruct ci_hdrc_platform_data data;\n\tstruct platform_device *dev;\n\tconst struct tegra_usb_soc_info *soc;\n\tstruct usb_phy *phy;\n\tstruct clk *clk;\n\tbool needs_double_reset;\n};\n\nstruct tegra_xtal_freq;\n\nstruct tegra_usb_phy {\n\tint irq;\n\tint instance;\n\tconst struct tegra_xtal_freq *freq;\n\tvoid *regs;\n\tvoid *pad_regs;\n\tstruct clk *clk;\n\tstruct clk *pll_u;\n\tstruct clk *pad_clk;\n\tstruct regulator *vbus;\n\tstruct regmap *pmc_regmap;\n\tenum usb_dr_mode mode;\n\tvoid *config;\n\tconst struct tegra_phy_soc_config *soc_config;\n\tstruct usb_phy *ulpi;\n\tstruct usb_phy u_phy;\n\tbool is_legacy_phy;\n\tenum usb_phy_interface phy_type;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *pad_rst;\n\tbool wakeup_enabled;\n\tbool pad_wakeup;\n\tbool powered_on;\n};\n\nstruct tegra_usb_soc_info {\n\tlong unsigned int flags;\n\tunsigned int txfifothresh;\n\tenum usb_dr_mode dr_mode;\n};\n\nstruct tegra_utmip_config {\n\tu8 hssync_start_delay;\n\tu8 elastic_limit;\n\tu8 idle_wait_delay;\n\tu8 term_range_adj;\n\tbool xcvr_setup_use_fuses;\n\tu8 xcvr_setup;\n\tu8 xcvr_lsfslew;\n\tu8 xcvr_lsrslew;\n\tu8 xcvr_hsslew;\n\tu8 hssquelch_level;\n\tu8 hsdiscon_level;\n};\n\nstruct tegra_wake_event {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int irq;\n\tstruct {\n\t\tunsigned int instance;\n\t\tunsigned int pin;\n\t} gpio;\n};\n\nstruct tegra_windowgroup {\n\tunsigned int usecount;\n\tstruct mutex lock;\n\tunsigned int index;\n\tstruct host1x_client *parent;\n\tstruct reset_control *rst;\n};\n\nstruct tegra_windowgroup_soc {\n\tunsigned int index;\n\tunsigned int dc;\n\tconst unsigned int *windows;\n\tunsigned int num_windows;\n};\n\nstruct tegra_xtal_freq {\n\tunsigned int freq;\n\tu8 enable_delay;\n\tu8 stable_count;\n\tu8 active_delay;\n\tu8 utmi_xtal_freq_count;\n\tu16 hsic_xtal_freq_count;\n\tu16 debounce;\n};\n\nstruct tegra_xusb_lane_soc;\n\nstruct tegra_xusb_lane {\n\tconst struct tegra_xusb_lane_soc *soc;\n\tstruct tegra_xusb_pad *pad;\n\tstruct device_node *np;\n\tstruct list_head list;\n\tunsigned int function;\n\tunsigned int index;\n};\n\nstruct tegra_xusb_hsic_lane {\n\tstruct tegra_xusb_lane base;\n\tu32 strobe_trim;\n\tu32 rx_strobe_trim;\n\tu32 rx_data_trim;\n\tu32 tx_rtune_n;\n\tu32 tx_rtune_p;\n\tu32 tx_rslew_n;\n\tu32 tx_rslew_p;\n\tbool auto_term;\n};\n\nstruct tegra_xusb_pad_soc;\n\nstruct tegra_xusb_lane_ops;\n\nstruct tegra_xusb_pad {\n\tconst struct tegra_xusb_pad_soc *soc;\n\tstruct tegra_xusb_padctl *padctl;\n\tstruct phy_provider *provider;\n\tstruct phy **lanes;\n\tstruct device dev;\n\tconst struct tegra_xusb_lane_ops *ops;\n\tstruct list_head list;\n\tlong: 32;\n};\n\nstruct tegra_xusb_hsic_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct regulator *supply;\n\tstruct clk *clk;\n};\n\nstruct tegra_xusb_port_ops;\n\nstruct tegra_xusb_port {\n\tstruct tegra_xusb_padctl *padctl;\n\tstruct tegra_xusb_lane *lane;\n\tunsigned int index;\n\tstruct list_head list;\n\tlong: 32;\n\tstruct device dev;\n\tstruct usb_role_switch *usb_role_sw;\n\tstruct work_struct usb_phy_work;\n\tstruct usb_phy usb_phy;\n\tconst struct tegra_xusb_port_ops *ops;\n};\n\nstruct tegra_xusb_hsic_port {\n\tstruct tegra_xusb_port base;\n};\n\nstruct tegra_xusb_lane_map {\n\tunsigned int port;\n\tconst char *type;\n\tunsigned int index;\n\tconst char *func;\n};\n\nstruct tegra_xusb_lane_ops {\n\tstruct tegra_xusb_lane * (*probe)(struct tegra_xusb_pad *, struct device_node *, unsigned int);\n\tvoid (*remove)(struct tegra_xusb_lane *);\n\tvoid (*iddq_enable)(struct tegra_xusb_lane *);\n\tvoid (*iddq_disable)(struct tegra_xusb_lane *);\n\tint (*enable_phy_sleepwalk)(struct tegra_xusb_lane *, enum usb_device_speed);\n\tint (*disable_phy_sleepwalk)(struct tegra_xusb_lane *);\n\tint (*enable_phy_wake)(struct tegra_xusb_lane *);\n\tint (*disable_phy_wake)(struct tegra_xusb_lane *);\n\tbool (*remote_wake_detected)(struct tegra_xusb_lane *);\n};\n\nstruct tegra_xusb_lane_soc {\n\tconst char *name;\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int mask;\n\tconst char * const *funcs;\n\tunsigned int num_funcs;\n\tstruct {\n\t\tunsigned int misc_ctl2;\n\t} regs;\n};\n\nstruct tegra_xusb_pad_ops {\n\tstruct tegra_xusb_pad * (*probe)(struct tegra_xusb_padctl *, const struct tegra_xusb_pad_soc *, struct device_node *);\n\tvoid (*remove)(struct tegra_xusb_pad *);\n};\n\nstruct tegra_xusb_pad_soc {\n\tconst char *name;\n\tconst struct tegra_xusb_lane_soc *lanes;\n\tunsigned int num_lanes;\n\tconst struct tegra_xusb_pad_ops *ops;\n};\n\nstruct tegra_xusb_padctl_soc___2;\n\nstruct tegra_xusb_padctl___2 {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct mutex lock;\n\tstruct reset_control *rst;\n\tconst struct tegra_xusb_padctl_soc___2 *soc;\n\tstruct pinctrl_dev *pinctrl;\n\tstruct pinctrl_desc desc;\n\tstruct phy_provider *provider;\n\tstruct phy *phys[2];\n\tunsigned int enable;\n};\n\nstruct tegra_xusb_padctl_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct tegra_xusb_padctl_lane {\n\tconst char *name;\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int mask;\n\tunsigned int iddq;\n\tconst unsigned int *funcs;\n\tunsigned int num_funcs;\n};\n\nstruct tegra_xusb_padctl_ops {\n\tstruct tegra_xusb_padctl * (*probe)(struct device *, const struct tegra_xusb_padctl_soc *);\n\tvoid (*remove)(struct tegra_xusb_padctl *);\n\tint (*suspend_noirq)(struct tegra_xusb_padctl *);\n\tint (*resume_noirq)(struct tegra_xusb_padctl *);\n\tint (*usb3_save_context)(struct tegra_xusb_padctl *, unsigned int);\n\tint (*hsic_set_idle)(struct tegra_xusb_padctl *, unsigned int, bool);\n\tint (*usb3_set_lfps_detect)(struct tegra_xusb_padctl *, unsigned int, bool);\n\tint (*vbus_override)(struct tegra_xusb_padctl *, bool);\n\tint (*utmi_port_reset)(struct phy *);\n\tvoid (*utmi_pad_power_on)(struct phy *);\n\tvoid (*utmi_pad_power_down)(struct phy *);\n};\n\nstruct tegra_xusb_padctl_property {\n\tconst char *name;\n\tenum tegra_xusb_padctl_param param;\n};\n\nstruct tegra_xusb_padctl_soc {\n\tconst struct tegra_xusb_pad_soc * const *pads;\n\tunsigned int num_pads;\n\tstruct {\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} usb2;\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} ulpi;\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} hsic;\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} usb3;\n\t} ports;\n\tconst struct tegra_xusb_padctl_ops *ops;\n\tconst char * const *supply_names;\n\tunsigned int num_supplies;\n\tbool supports_gen2;\n\tbool need_fake_usb3_port;\n\tbool poll_trk_completed;\n\tbool trk_hw_mode;\n\tbool trk_update_on_idle;\n\tbool supports_lp_cfg_en;\n};\n\nstruct tegra_xusb_padctl_soc___2 {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int num_pins;\n\tconst struct tegra_xusb_padctl_function *functions;\n\tunsigned int num_functions;\n\tconst struct tegra_xusb_padctl_lane *lanes;\n\tunsigned int num_lanes;\n};\n\nstruct tegra_xusb_pcie_lane {\n\tstruct tegra_xusb_lane base;\n};\n\nstruct tegra_xusb_pcie_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct reset_control *rst;\n\tstruct clk *pll;\n\tbool enable;\n\tlong: 32;\n};\n\nstruct tegra_xusb_port_ops {\n\tvoid (*release)(struct tegra_xusb_port *);\n\tvoid (*remove)(struct tegra_xusb_port *);\n\tint (*enable)(struct tegra_xusb_port *);\n\tvoid (*disable)(struct tegra_xusb_port *);\n\tstruct tegra_xusb_lane * (*map)(struct tegra_xusb_port *);\n};\n\nstruct tegra_xusb_sata_lane {\n\tstruct tegra_xusb_lane base;\n};\n\nstruct tegra_xusb_sata_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct reset_control *rst;\n\tstruct clk *pll;\n\tbool enable;\n\tlong: 32;\n};\n\nstruct tegra_xusb_ulpi_lane {\n\tstruct tegra_xusb_lane base;\n};\n\nstruct tegra_xusb_ulpi_pad {\n\tstruct tegra_xusb_pad base;\n};\n\nstruct tegra_xusb_ulpi_port {\n\tstruct tegra_xusb_port base;\n\tstruct regulator *supply;\n\tbool internal;\n};\n\nstruct tegra_xusb_usb2_lane {\n\tstruct tegra_xusb_lane base;\n\tu32 hs_curr_level_offset;\n};\n\nstruct tegra_xusb_usb2_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct clk *clk;\n\tunsigned int enable;\n\tstruct mutex lock;\n\tlong: 32;\n};\n\nstruct tegra_xusb_usb2_port {\n\tstruct tegra_xusb_port base;\n\tstruct regulator *supply;\n\tenum usb_dr_mode mode;\n\tbool internal;\n\tint usb3_port_fake;\n};\n\nstruct tegra_xusb_usb3_port {\n\tstruct tegra_xusb_port base;\n\tbool context_saved;\n\tunsigned int port;\n\tbool internal;\n\tbool disable_gen2;\n\tu32 tap1;\n\tu32 amp;\n\tu32 ctle_z;\n\tu32 ctle_g;\n\tlong: 32;\n};\n\nstruct temp_sensor_data {\n\tu32 tshut_hot;\n\tu32 tshut_cold;\n\tu32 t_hot;\n\tu32 t_cold;\n\tu32 min_freq;\n\tu32 max_freq;\n};\n\nstruct temp_sensor_registers {\n\tu32 temp_sensor_ctrl;\n\tu32 bgap_tempsoff_mask;\n\tu32 bgap_soc_mask;\n\tu32 bgap_eocz_mask;\n\tu32 bgap_dtemp_mask;\n\tu32 bgap_mask_ctrl;\n\tu32 mask_hot_mask;\n\tu32 mask_cold_mask;\n\tu32 mask_counter_delay_mask;\n\tu32 mask_freeze_mask;\n\tu32 bgap_mode_ctrl;\n\tu32 mode_ctrl_mask;\n\tu32 bgap_counter;\n\tu32 counter_mask;\n\tu32 bgap_threshold;\n\tu32 threshold_thot_mask;\n\tu32 threshold_tcold_mask;\n\tu32 tshut_threshold;\n\tu32 tshut_hot_mask;\n\tu32 tshut_cold_mask;\n\tu32 bgap_status;\n\tu32 status_hot_mask;\n\tu32 status_cold_mask;\n\tu32 ctrl_dtemp_1;\n\tu32 ctrl_dtemp_2;\n\tu32 bgap_efuse;\n};\n\nstruct temp_sensor_regval {\n\tu32 bg_mode_ctrl;\n\tu32 bg_ctrl;\n\tu32 bg_counter;\n\tu32 bg_threshold;\n\tu32 tshut_threshold;\n\tvoid *data;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[8];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct thermal_attr {\n\tstruct device_attribute attr;\n\tchar name[20];\n};\n\ntypedef struct thermal_cooling_device *class_cooling_dev_t;\n\nstruct thermal_cooling_device {\n\tint id;\n\tconst char *type;\n\tlong unsigned int max_state;\n\tlong: 32;\n\tstruct device device;\n\tstruct device_node *np;\n\tvoid *devdata;\n\tvoid *stats;\n\tconst struct thermal_cooling_device_ops *ops;\n\tbool updated;\n\tstruct mutex lock;\n\tstruct list_head thermal_instances;\n\tstruct list_head node;\n};\n\nstruct thermal_trip;\n\nstruct thermal_governor {\n\tconst char *name;\n\tint (*bind_to_tz)(struct thermal_zone_device *);\n\tvoid (*unbind_from_tz)(struct thermal_zone_device *);\n\tvoid (*trip_crossed)(struct thermal_zone_device *, const struct thermal_trip *, bool);\n\tvoid (*manage)(struct thermal_zone_device *);\n\tvoid (*update_tz)(struct thermal_zone_device *, enum thermal_notify_event);\n\tstruct list_head governor_list;\n};\n\nstruct thermal_hwmon_attr {\n\tstruct device_attribute attr;\n\tchar name[16];\n};\n\nstruct thermal_hwmon_device {\n\tchar type[20];\n\tstruct device *device;\n\tint count;\n\tstruct list_head tz_list;\n\tstruct list_head node;\n};\n\nstruct thermal_hwmon_temp {\n\tstruct list_head hwmon_node;\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_hwmon_attr temp_input;\n\tstruct thermal_hwmon_attr temp_crit;\n};\n\nstruct thermal_instance {\n\tint id;\n\tchar name[20];\n\tstruct thermal_cooling_device *cdev;\n\tconst struct thermal_trip *trip;\n\tbool initialized;\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tlong unsigned int target;\n\tchar attr_name[20];\n\tstruct device_attribute attr;\n\tchar weight_attr_name[20];\n\tstruct device_attribute weight_attr;\n\tstruct list_head trip_node;\n\tstruct list_head cdev_node;\n\tunsigned int weight;\n\tbool upper_no_limit;\n};\n\nstruct thermal_soc_data {\n\tu32 version;\n\tu32 sensor_ctrl;\n\tu32 power_down_mask;\n\tu32 measure_temp_mask;\n\tu32 measure_freq_ctrl;\n\tu32 measure_freq_mask;\n\tu32 measure_freq_shift;\n\tu32 temp_data;\n\tu32 temp_value_mask;\n\tu32 temp_value_shift;\n\tu32 temp_valid_mask;\n\tu32 panic_alarm_ctrl;\n\tu32 panic_alarm_mask;\n\tu32 panic_alarm_shift;\n\tu32 high_alarm_ctrl;\n\tu32 high_alarm_mask;\n\tu32 high_alarm_shift;\n\tu32 low_alarm_ctrl;\n\tu32 low_alarm_mask;\n\tu32 low_alarm_shift;\n};\n\nstruct thermal_trip {\n\tint temperature;\n\tint hysteresis;\n\tenum thermal_trip_type type;\n\tu8 flags;\n\tvoid *priv;\n};\n\nstruct thermal_trip_attrs {\n\tstruct thermal_attr type;\n\tstruct thermal_attr temp;\n\tstruct thermal_attr hyst;\n};\n\nstruct thermal_trip_desc {\n\tstruct thermal_trip trip;\n\tstruct thermal_trip_attrs trip_attrs;\n\tstruct list_head list_node;\n\tstruct list_head thermal_instances;\n\tint threshold;\n};\n\ntypedef struct thermal_zone_device *class_thermal_zone_reverse_t;\n\ntypedef struct thermal_zone_device *class_thermal_zone_t;\n\nstruct thermal_zone_device_ops {\n\tbool (*should_bind)(struct thermal_zone_device *, const struct thermal_trip *, struct thermal_cooling_device *, struct cooling_spec *);\n\tint (*get_temp)(struct thermal_zone_device *, int *);\n\tint (*set_trips)(struct thermal_zone_device *, int, int);\n\tint (*change_mode)(struct thermal_zone_device *, enum thermal_device_mode);\n\tint (*set_trip_temp)(struct thermal_zone_device *, const struct thermal_trip *, int);\n\tint (*get_crit_temp)(struct thermal_zone_device *, int *);\n\tint (*set_emul_temp)(struct thermal_zone_device *, int);\n\tint (*get_trend)(struct thermal_zone_device *, const struct thermal_trip *, enum thermal_trend *);\n\tvoid (*hot)(struct thermal_zone_device *);\n\tvoid (*critical)(struct thermal_zone_device *);\n};\n\nstruct thermal_zone_params;\n\nstruct thermal_zone_device {\n\tint id;\n\tchar type[20];\n\tstruct device device;\n\tstruct completion removal;\n\tstruct completion resume;\n\tstruct attribute_group trips_attribute_group;\n\tstruct list_head trips_high;\n\tstruct list_head trips_reached;\n\tstruct list_head trips_invalid;\n\tenum thermal_device_mode mode;\n\tvoid *devdata;\n\tint num_trips;\n\tlong unsigned int passive_delay_jiffies;\n\tlong unsigned int polling_delay_jiffies;\n\tlong unsigned int recheck_delay_jiffies;\n\tint temperature;\n\tint last_temperature;\n\tint emul_temperature;\n\tint passive;\n\tint prev_low_trip;\n\tint prev_high_trip;\n\tstruct thermal_zone_device_ops ops;\n\tstruct thermal_zone_params *tzp;\n\tstruct thermal_governor *governor;\n\tvoid *governor_data;\n\tstruct ida ida;\n\tstruct mutex lock;\n\tstruct list_head node;\n\tstruct delayed_work poll_queue;\n\tenum thermal_notify_event notify_event;\n\tu8 state;\n\tstruct list_head user_thresholds;\n\tstruct thermal_trip_desc trips[0];\n};\n\nstruct thermal_zone_params {\n\tconst char *governor_name;\n\tbool no_hwmon;\n\tu32 sustainable_power;\n\ts32 k_po;\n\ts32 k_pu;\n\ts32 k_i;\n\ts32 k_d;\n\ts32 integral_cutoff;\n\tint slope;\n\tint offset;\n};\n\nstruct thread_deferred_req {\n\tstruct cache_deferred_req handle;\n\tstruct completion completion;\n};\n\nstruct ti_32k {\n\tvoid *base;\n\tvoid *counter;\n\tstruct clocksource cs;\n};\n\nstruct ti_abb_reg;\n\nstruct ti_abb_info;\n\nstruct ti_abb {\n\tstruct regulator_desc rdesc;\n\tstruct clk *clk;\n\tvoid *base;\n\tvoid *setup_reg;\n\tvoid *control_reg;\n\tvoid *int_base;\n\tvoid *efuse_base;\n\tvoid *ldo_base;\n\tconst struct ti_abb_reg *regs;\n\tu32 txdone_mask;\n\tu32 ldovbb_override_mask;\n\tu32 ldovbb_vset_mask;\n\tstruct ti_abb_info *info;\n\tint current_info_idx;\n\tu32 settling_time;\n};\n\nstruct ti_abb_info {\n\tu32 opp_sel;\n\tu32 vset;\n};\n\nstruct ti_abb_reg {\n\tu32 setup_off;\n\tu32 control_off;\n\tu32 sr2_wtcnt_value_mask;\n\tu32 fbb_sel_mask;\n\tu32 rbb_sel_mask;\n\tu32 sr2_en_mask;\n\tu32 opp_change_mask;\n\tu32 opp_sel_mask;\n};\n\nstruct ti_adpll_data;\n\nstruct ti_adpll_clkout_data {\n\tstruct ti_adpll_data *adpll;\n\tstruct clk_gate gate;\n\tstruct clk_hw hw;\n};\n\nstruct ti_adpll_clock {\n\tstruct clk *clk;\n\tstruct clk_lookup *cl;\n\tvoid (*unregister)(struct clk *);\n};\n\nstruct ti_adpll_dco_data {\n\tstruct clk_hw hw;\n};\n\nstruct ti_adpll_platform_data;\n\nstruct ti_adpll_data {\n\tstruct device *dev;\n\tconst struct ti_adpll_platform_data *c;\n\tstruct device_node *np;\n\tlong unsigned int pa;\n\tvoid *iobase;\n\tvoid *regs;\n\tspinlock_t lock;\n\tconst char *parent_names[3];\n\tstruct clk *parent_clocks[3];\n\tstruct ti_adpll_clock *clocks;\n\tstruct clk_onecell_data outputs;\n\tstruct ti_adpll_dco_data dco;\n};\n\nstruct ti_adpll_platform_data {\n\tconst bool is_type_s;\n\tconst int nr_max_inputs;\n\tconst int nr_max_outputs;\n\tconst int output_index;\n};\n\nstruct ti_am335x_xbar_data {\n\tvoid *iomem;\n\tstruct dma_router dmarouter;\n\tu32 xbar_events;\n\tu32 dma_requests;\n};\n\nstruct ti_am335x_xbar_map {\n\tu16 dma_line;\n\tu8 mux_val;\n};\n\nstruct ti_bandgap_data;\n\nstruct ti_bandgap {\n\tstruct device *dev;\n\tvoid *base;\n\tconst struct ti_bandgap_data *conf;\n\tstruct temp_sensor_regval *regval;\n\tstruct clk *fclock;\n\tstruct clk *div_clk;\n\tspinlock_t lock;\n\tint irq;\n\tstruct gpio_desc *tshut_gpiod;\n\tu32 clk_rate;\n\tstruct notifier_block nb;\n\tunsigned int is_suspended: 1;\n};\n\nstruct ti_temp_sensor {\n\tstruct temp_sensor_data *ts_data;\n\tstruct temp_sensor_registers *registers;\n\tchar *domain;\n\tconst int slope_pcb;\n\tconst int constant_pcb;\n\tint (*register_cooling)(struct ti_bandgap *, int);\n\tint (*unregister_cooling)(struct ti_bandgap *, int);\n};\n\nstruct ti_bandgap_data {\n\tunsigned int features;\n\tconst int *conv_table;\n\tu32 adc_start_val;\n\tu32 adc_end_val;\n\tchar *fclock_name;\n\tchar *div_ck_name;\n\tint sensor_count;\n\tint (*report_temperature)(struct ti_bandgap *, int);\n\tint (*expose_sensor)(struct ti_bandgap *, int, char *);\n\tint (*remove_sensor)(struct ti_bandgap *, int);\n\tstruct ti_temp_sensor sensors[0];\n};\n\nstruct ti_clk_features {\n\tu32 flags;\n\tlong int fint_min;\n\tlong int fint_max;\n\tlong int fint_band1_max;\n\tlong int fint_band2_min;\n\tu8 dpll_bypass_vals;\n\tu8 cm_idlest_val;\n};\n\nstruct ti_clk_ll_ops {\n\tu32 (*clk_readl)(const struct clk_omap_reg *);\n\tvoid (*clk_writel)(u32, const struct clk_omap_reg *);\n\tvoid (*clk_rmw)(u32, u32, const struct clk_omap_reg *);\n\tint (*clkdm_clk_enable)(struct clockdomain *, struct clk *);\n\tint (*clkdm_clk_disable)(struct clockdomain *, struct clk *);\n\tstruct clockdomain * (*clkdm_lookup)(const char *);\n\tint (*cm_wait_module_ready)(u8, s16, u16, u8);\n\tint (*cm_split_idlest_reg)(struct clk_omap_reg *, s16 *, u8 *);\n};\n\nstruct ti_clk_mux {\n\tu8 bit_shift;\n\tint num_parents;\n\tu16 reg;\n\tu8 module;\n\tconst char * const *parents;\n\tu16 flags;\n};\n\nstruct ti_cpufreq_soc_data;\n\nstruct ti_cpufreq_data {\n\tstruct device *cpu_dev;\n\tstruct device_node *opp_node;\n\tstruct regmap *syscon;\n\tconst struct ti_cpufreq_soc_data *soc_data;\n};\n\nstruct ti_cpufreq_soc_data {\n\tconst char * const *reg_names;\n\tlong unsigned int (*efuse_xlate)(struct ti_cpufreq_data *, long unsigned int);\n\tlong unsigned int efuse_fallback;\n\tlong unsigned int efuse_offset;\n\tlong unsigned int efuse_mask;\n\tlong unsigned int efuse_shift;\n\tlong unsigned int rev_offset;\n\tbool multi_regulator;\n\tu8 quirks;\n};\n\nstruct ti_dra7_xbar_data {\n\tvoid *iomem;\n\tstruct dma_router dmarouter;\n\tstruct mutex mutex;\n\tlong unsigned int *dma_inuse;\n\tu16 safe_val;\n\tu32 xbar_requests;\n\tu32 dma_requests;\n\tu32 dma_offset;\n};\n\nstruct ti_dra7_xbar_map {\n\tu16 xbar_in;\n\tint xbar_out;\n};\n\nstruct ti_dt_clk {\n\tstruct clk_lookup lk;\n\tchar *node_name;\n};\n\nstruct ti_iodelay_cfg {\n\tu16 offset;\n\tu16 a_delay;\n\tu16 g_delay;\n};\n\nstruct ti_iodelay_reg_values {\n\tu16 coarse_ref_count;\n\tu16 coarse_delay_count;\n\tu16 fine_ref_count;\n\tu16 fine_delay_count;\n\tu16 ref_clk_period;\n\tu32 cdpe;\n\tu32 fdpe;\n};\n\nstruct ti_iodelay_reg_data;\n\nstruct ti_iodelay_device {\n\tstruct device *dev;\n\tlong unsigned int phys_base;\n\tvoid *reg_base;\n\tstruct regmap *regmap;\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc desc;\n\tstruct pinctrl_pin_desc *pa;\n\tconst struct ti_iodelay_reg_data *reg_data;\n\tstruct ti_iodelay_reg_values reg_init_conf_values;\n};\n\nstruct ti_iodelay_pingroup {\n\tstruct ti_iodelay_cfg *cfg;\n\tint ncfg;\n\tlong unsigned int config;\n};\n\nstruct ti_iodelay_reg_data {\n\tu32 signature_mask;\n\tu32 signature_value;\n\tu32 lock_mask;\n\tu32 lock_val;\n\tu32 unlock_val;\n\tu32 binary_data_coarse_mask;\n\tu32 binary_data_fine_mask;\n\tu32 reg_refclk_offset;\n\tu32 refclk_period_mask;\n\tu32 reg_coarse_offset;\n\tu32 coarse_delay_count_mask;\n\tu32 coarse_ref_count_mask;\n\tu32 reg_fine_offset;\n\tu32 fine_delay_count_mask;\n\tu32 fine_ref_count_mask;\n\tu32 reg_global_lock_offset;\n\tu32 global_lock_mask;\n\tu32 global_unlock_val;\n\tu32 global_lock_val;\n\tu32 reg_start_offset;\n\tu32 reg_nr_per_pin;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct ti_msgmgr_valid_queue_desc;\n\nstruct ti_msgmgr_desc {\n\tu8 queue_count;\n\tu8 max_message_size;\n\tu8 max_messages;\n\tu8 data_first_reg;\n\tu8 data_last_reg;\n\tu32 status_cnt_mask;\n\tu32 status_err_mask;\n\tbool tx_polled;\n\tint tx_poll_timeout_ms;\n\tconst struct ti_msgmgr_valid_queue_desc *valid_queues;\n\tconst char *data_region_name;\n\tconst char *status_region_name;\n\tconst char *ctrl_region_name;\n\tint num_valid_queues;\n\tbool is_sproxy;\n};\n\nstruct ti_queue_inst;\n\nstruct ti_msgmgr_inst {\n\tstruct device *dev;\n\tconst struct ti_msgmgr_desc *desc;\n\tvoid *queue_proxy_region;\n\tvoid *queue_state_debug_region;\n\tvoid *queue_ctrl_region;\n\tu8 num_valid_queues;\n\tstruct ti_queue_inst *qinsts;\n\tlong: 32;\n\tstruct mbox_controller mbox;\n\tstruct mbox_chan *chans;\n\tlong: 32;\n};\n\nstruct ti_msgmgr_message {\n\tsize_t len;\n\tu8 *buf;\n\tstruct mbox_chan *chan_rx;\n\tint timeout_rx_ms;\n};\n\nstruct ti_msgmgr_valid_queue_desc {\n\tu8 queue_id;\n\tu8 proxy_id;\n\tbool is_tx;\n};\n\nstruct ti_opp_supply_optimum_voltage_table;\n\nstruct ti_opp_supply_data {\n\tstruct ti_opp_supply_optimum_voltage_table *vdd_table;\n\tu32 num_vdd_table;\n\tu32 vdd_absolute_max_voltage_uv;\n\tstruct dev_pm_opp_supply old_supplies[2];\n\tstruct dev_pm_opp_supply new_supplies[2];\n};\n\nstruct ti_opp_supply_of_data {\n\tconst u8 flags;\n\tconst u32 efuse_voltage_mask;\n\tconst bool efuse_voltage_uv;\n};\n\nstruct ti_opp_supply_optimum_voltage_table {\n\tunsigned int reference_uv;\n\tunsigned int optimized_uv;\n};\n\nstruct ti_pipe3 {\n\tvoid *pll_ctrl_base;\n\tvoid *phy_rx;\n\tvoid *phy_tx;\n\tstruct device *dev;\n\tstruct device *control_dev;\n\tstruct clk *wkupclk;\n\tstruct clk *sys_clk;\n\tstruct clk *refclk;\n\tstruct clk *div_clk;\n\tstruct pipe3_dpll_map *dpll_map;\n\tstruct regmap *phy_power_syscon;\n\tstruct regmap *pcs_syscon;\n\tstruct regmap *dpll_reset_syscon;\n\tunsigned int dpll_reset_reg;\n\tunsigned int power_reg;\n\tunsigned int pcie_pcs_reg;\n\tbool sata_refclk_enabled;\n\tenum pipe3_mode mode;\n\tstruct pipe3_settings settings;\n};\n\nstruct ti_prm_platform_data {\n\tvoid (*clkdm_deny_idle)(struct clockdomain *);\n\tvoid (*clkdm_allow_idle)(struct clockdomain *);\n\tstruct clockdomain * (*clkdm_lookup)(const char *);\n};\n\nstruct ti_queue_inst {\n\tchar name[30];\n\tu8 queue_id;\n\tu8 proxy_id;\n\tint irq;\n\tbool is_tx;\n\tvoid *queue_buff_start;\n\tvoid *queue_buff_end;\n\tvoid *queue_state;\n\tvoid *queue_ctrl;\n\tstruct mbox_chan *chan;\n\tu32 *rx_buff;\n\tbool polled_rx_mode;\n};\n\nstruct ti_sci_clk_ops {\n\tint (*get_clock)(const struct ti_sci_handle *, u32, u32, bool, bool, bool);\n\tint (*idle_clock)(const struct ti_sci_handle *, u32, u32);\n\tint (*put_clock)(const struct ti_sci_handle *, u32, u32);\n\tint (*is_auto)(const struct ti_sci_handle *, u32, u32, bool *);\n\tint (*is_on)(const struct ti_sci_handle *, u32, u32, bool *, bool *);\n\tint (*is_off)(const struct ti_sci_handle *, u32, u32, bool *, bool *);\n\tint (*set_parent)(const struct ti_sci_handle *, u32, u32, u32);\n\tint (*get_parent)(const struct ti_sci_handle *, u32, u32, u32 *);\n\tint (*get_num_parents)(const struct ti_sci_handle *, u32, u32, u32 *);\n\tint (*get_best_match_freq)(const struct ti_sci_handle *, u32, u32, u64, u64, u64, u64 *);\n\tint (*set_freq)(const struct ti_sci_handle *, u32, u32, u64, u64, u64);\n\tint (*get_freq)(const struct ti_sci_handle *, u32, u32, u64 *);\n};\n\nstruct ti_sci_core_ops {\n\tint (*reboot_device)(const struct ti_sci_handle *);\n};\n\nstruct ti_sci_desc {\n\tu8 default_host_id;\n\tint max_rx_timeout_ms;\n\tint max_msgs;\n\tint max_msg_size;\n};\n\nstruct ti_sci_dev_ops {\n\tint (*get_device)(const struct ti_sci_handle *, u32);\n\tint (*get_device_exclusive)(const struct ti_sci_handle *, u32);\n\tint (*idle_device)(const struct ti_sci_handle *, u32);\n\tint (*idle_device_exclusive)(const struct ti_sci_handle *, u32);\n\tint (*put_device)(const struct ti_sci_handle *, u32);\n\tint (*is_valid)(const struct ti_sci_handle *, u32);\n\tint (*get_context_loss_count)(const struct ti_sci_handle *, u32, u32 *);\n\tint (*is_idle)(const struct ti_sci_handle *, u32, bool *);\n\tint (*is_stop)(const struct ti_sci_handle *, u32, bool *, bool *);\n\tint (*is_on)(const struct ti_sci_handle *, u32, bool *, bool *);\n\tint (*is_transitioning)(const struct ti_sci_handle *, u32, bool *);\n\tint (*set_device_resets)(const struct ti_sci_handle *, u32, u32);\n\tint (*get_device_resets)(const struct ti_sci_handle *, u32, u32 *);\n};\n\nstruct ti_sci_genpd_provider {\n\tconst struct ti_sci_handle *ti_sci;\n\tstruct device *dev;\n\tstruct list_head pd_list;\n\tstruct genpd_onecell_data data;\n};\n\nstruct ti_sci_version_info {\n\tu8 abi_major;\n\tu8 abi_minor;\n\tu16 firmware_revision;\n\tchar firmware_description[32];\n};\n\nstruct ti_sci_pm_ops {\n\tint (*lpm_wake_reason)(const struct ti_sci_handle *, u32 *, u64 *, u8 *, u8 *);\n\tint (*set_device_constraint)(const struct ti_sci_handle *, u32, u8);\n\tint (*set_latency_constraint)(const struct ti_sci_handle *, u16, u8);\n};\n\nstruct ti_sci_resource_desc;\n\nstruct ti_sci_rm_core_ops {\n\tint (*get_range)(const struct ti_sci_handle *, u32, u8, struct ti_sci_resource_desc *);\n\tint (*get_range_from_shost)(const struct ti_sci_handle *, u32, u8, u8, struct ti_sci_resource_desc *);\n};\n\nstruct ti_sci_rm_irq_ops {\n\tint (*set_irq)(const struct ti_sci_handle *, u16, u16, u16, u16);\n\tint (*set_event_map)(const struct ti_sci_handle *, u16, u16, u16, u16, u16, u8);\n\tint (*free_irq)(const struct ti_sci_handle *, u16, u16, u16, u16);\n\tint (*free_event_map)(const struct ti_sci_handle *, u16, u16, u16, u16, u16, u8);\n};\n\nstruct ti_sci_msg_rm_ring_cfg;\n\nstruct ti_sci_rm_ringacc_ops {\n\tint (*set_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_ring_cfg *);\n};\n\nstruct ti_sci_rm_psil_ops {\n\tint (*pair)(const struct ti_sci_handle *, u32, u32, u32);\n\tint (*unpair)(const struct ti_sci_handle *, u32, u32, u32);\n};\n\nstruct ti_sci_msg_rm_udmap_tx_ch_cfg;\n\nstruct ti_sci_msg_rm_udmap_rx_ch_cfg;\n\nstruct ti_sci_msg_rm_udmap_flow_cfg;\n\nstruct ti_sci_rm_udmap_ops {\n\tint (*tx_ch_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_udmap_tx_ch_cfg *);\n\tint (*rx_ch_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_udmap_rx_ch_cfg *);\n\tint (*rx_flow_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_udmap_flow_cfg *);\n};\n\nstruct ti_sci_proc_ops {\n\tint (*request)(const struct ti_sci_handle *, u8);\n\tint (*release)(const struct ti_sci_handle *, u8);\n\tint (*handover)(const struct ti_sci_handle *, u8, u8);\n\tint (*set_config)(const struct ti_sci_handle *, u8, u64, u32, u32);\n\tint (*set_control)(const struct ti_sci_handle *, u8, u32, u32);\n\tint (*get_status)(const struct ti_sci_handle *, u8, u64 *, u32 *, u32 *, u32 *);\n};\n\nstruct ti_sci_ops {\n\tstruct ti_sci_core_ops core_ops;\n\tstruct ti_sci_dev_ops dev_ops;\n\tstruct ti_sci_clk_ops clk_ops;\n\tstruct ti_sci_pm_ops pm_ops;\n\tstruct ti_sci_rm_core_ops rm_core_ops;\n\tstruct ti_sci_rm_irq_ops rm_irq_ops;\n\tstruct ti_sci_rm_ringacc_ops rm_ring_ops;\n\tstruct ti_sci_rm_psil_ops rm_psil_ops;\n\tstruct ti_sci_rm_udmap_ops rm_udmap_ops;\n\tstruct ti_sci_proc_ops proc_ops;\n};\n\nstruct ti_sci_handle {\n\tstruct ti_sci_version_info version;\n\tstruct ti_sci_ops ops;\n};\n\nstruct ti_sci_xfer;\n\nstruct ti_sci_xfers_info {\n\tstruct semaphore sem_xfer_count;\n\tstruct ti_sci_xfer *xfer_block;\n\tlong unsigned int *xfer_alloc_table;\n\tspinlock_t xfer_lock;\n};\n\nstruct ti_sci_info {\n\tstruct device *dev;\n\tconst struct ti_sci_desc *desc;\n\tstruct dentry *d;\n\tvoid *debug_region;\n\tchar *debug_buffer;\n\tsize_t debug_region_size;\n\tstruct ti_sci_handle handle;\n\tstruct mbox_client cl;\n\tstruct mbox_chan *chan_tx;\n\tstruct mbox_chan *chan_rx;\n\tstruct ti_sci_xfers_info minfo;\n\tstruct list_head node;\n\tu8 host_id;\n\tlong: 32;\n\tu64 fw_caps;\n\tint users;\n\tlong: 32;\n};\n\nstruct ti_sci_msg_hdr {\n\tu16 type;\n\tu8 host;\n\tu8 seq;\n\tu32 flags;\n};\n\nstruct ti_sci_msg_psil_pair {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 nav_id;\n\tu32 src_thread;\n\tu32 dst_thread;\n};\n\nstruct ti_sci_msg_psil_unpair {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 nav_id;\n\tu32 src_thread;\n\tu32 dst_thread;\n};\n\nstruct ti_sci_msg_req_get_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_clock_num_parents {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_clock_parent {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_clock_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_device_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n};\n\nstruct ti_sci_msg_req_get_resource_range {\n\tstruct ti_sci_msg_hdr hdr;\n\tu16 type;\n\tu8 subtype;\n\tu8 secondary_host;\n};\n\nstruct ti_sci_msg_req_get_status {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_lpm_set_device_constraint {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n\tu8 state;\n\tu32 rsvd[2];\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_lpm_set_latency_constraint {\n\tstruct ti_sci_msg_hdr hdr;\n\tu16 latency;\n\tu8 state;\n\tu32 rsvd;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_manage_irq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 src_id;\n\tu16 src_index;\n\tu16 dst_id;\n\tu16 dst_host_irq;\n\tu16 ia_id;\n\tu16 vint;\n\tu16 global_event;\n\tu8 vint_status_bit;\n\tu8 secondary_host;\n};\n\nstruct ti_sci_msg_req_prepare_sleep {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 mode;\n\tu32 ctx_lo;\n\tu32 ctx_hi;\n\tu32 debug_flags;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_proc_handover {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu8 host_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_proc_release {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_proc_request {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_query_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu64 min_freq_hz;\n\tu64 target_freq_hz;\n\tu64 max_freq_hz;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_reboot {\n\tstruct ti_sci_msg_hdr hdr;\n};\n\nstruct ti_sci_msg_req_set_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu64 min_freq_hz;\n\tu64 target_freq_hz;\n\tu64 max_freq_hz;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_clock_parent {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu8 parent_id;\n\tu32 clk_id_32;\n\tu32 parent_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_clock_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu8 request_state;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_config {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu32 bootvector_low;\n\tu32 bootvector_high;\n\tu32 config_flags_set;\n\tu32 config_flags_clear;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_ctrl {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu32 control_flags_set;\n\tu32 control_flags_clear;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_device_resets {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n\tu32 resets;\n};\n\nstruct ti_sci_msg_req_set_device_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n\tu32 reserved;\n\tu8 state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_io_isolation {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu64 freq_hz;\n};\n\nstruct ti_sci_msg_resp_get_clock_num_parents {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 num_parents;\n\tu32 num_parents_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_clock_parent {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 parent_id;\n\tu32 parent_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_clock_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 programmed_state;\n\tu8 current_state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_device_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 context_loss_count;\n\tu32 resets;\n\tu8 programmed_state;\n\tu8 current_state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_resource_range {\n\tstruct ti_sci_msg_hdr hdr;\n\tu16 range_start;\n\tu16 range_num;\n\tu16 range_start_sec;\n\tu16 range_num_sec;\n};\n\nstruct ti_sci_msg_resp_get_status {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu32 bootvector_low;\n\tu32 bootvector_high;\n\tu32 config_flags;\n\tu32 control_flags;\n\tu32 status_flags;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_lpm_wake_reason {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 wake_source;\n\tu64 wake_timestamp;\n\tu8 wake_pin;\n\tu8 mode;\n\tu32 rsvd[2];\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_query_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu64 freq_hz;\n};\n\nstruct ti_sci_msg_resp_query_fw_caps {\n\tstruct ti_sci_msg_hdr hdr;\n\tu64 fw_caps;\n};\n\nstruct ti_sci_msg_resp_version {\n\tstruct ti_sci_msg_hdr hdr;\n\tchar firmware_description[32];\n\tu16 firmware_revision;\n\tu8 abi_major;\n\tu8 abi_minor;\n};\n\nstruct ti_sci_msg_rm_ring_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu32 addr_lo;\n\tu32 addr_hi;\n\tu32 count;\n\tu8 mode;\n\tu8 size;\n\tu8 order_id;\n\tu16 virtid;\n\tu8 asel;\n};\n\nstruct ti_sci_msg_rm_ring_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu32 addr_lo;\n\tu32 addr_hi;\n\tu32 count;\n\tu8 mode;\n\tu8 size;\n\tu8 order_id;\n\tu16 virtid;\n\tu8 asel;\n} __attribute__((packed));\n\nstruct ti_sci_msg_rm_udmap_flow_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 flow_index;\n\tu8 rx_einfo_present;\n\tu8 rx_psinfo_present;\n\tu8 rx_error_handling;\n\tu8 rx_desc_type;\n\tu16 rx_sop_offset;\n\tu16 rx_dest_qnum;\n\tu8 rx_src_tag_hi;\n\tu8 rx_src_tag_lo;\n\tu8 rx_dest_tag_hi;\n\tu8 rx_dest_tag_lo;\n\tu8 rx_src_tag_hi_sel;\n\tu8 rx_src_tag_lo_sel;\n\tu8 rx_dest_tag_hi_sel;\n\tu8 rx_dest_tag_lo_sel;\n\tu16 rx_fdq0_sz0_qnum;\n\tu16 rx_fdq1_qnum;\n\tu16 rx_fdq2_qnum;\n\tu16 rx_fdq3_qnum;\n\tu8 rx_ps_location;\n};\n\nstruct ti_sci_msg_rm_udmap_flow_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 flow_index;\n\tu8 rx_einfo_present;\n\tu8 rx_psinfo_present;\n\tu8 rx_error_handling;\n\tu8 rx_desc_type;\n\tu16 rx_sop_offset;\n\tu16 rx_dest_qnum;\n\tu8 rx_src_tag_hi;\n\tu8 rx_src_tag_lo;\n\tu8 rx_dest_tag_hi;\n\tu8 rx_dest_tag_lo;\n\tu8 rx_src_tag_hi_sel;\n\tu8 rx_src_tag_lo_sel;\n\tu8 rx_dest_tag_hi_sel;\n\tu8 rx_dest_tag_lo_sel;\n\tu16 rx_fdq0_sz0_qnum;\n\tu16 rx_fdq1_qnum;\n\tu16 rx_fdq2_qnum;\n\tu16 rx_fdq3_qnum;\n\tu8 rx_ps_location;\n} __attribute__((packed));\n\nstruct ti_sci_msg_rm_udmap_rx_ch_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu16 rx_fetch_size;\n\tu16 rxcq_qnum;\n\tu8 rx_priority;\n\tu8 rx_qos;\n\tu8 rx_orderid;\n\tu8 rx_sched_priority;\n\tu16 flowid_start;\n\tu16 flowid_cnt;\n\tu8 rx_pause_on_err;\n\tu8 rx_atype;\n\tu8 rx_chan_type;\n\tu8 rx_ignore_short;\n\tu8 rx_ignore_long;\n\tu8 rx_burst_size;\n};\n\nstruct ti_sci_msg_rm_udmap_rx_ch_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu16 rx_fetch_size;\n\tu16 rxcq_qnum;\n\tu8 rx_priority;\n\tu8 rx_qos;\n\tu8 rx_orderid;\n\tu8 rx_sched_priority;\n\tu16 flowid_start;\n\tu16 flowid_cnt;\n\tu8 rx_pause_on_err;\n\tu8 rx_atype;\n\tu8 rx_chan_type;\n\tu8 rx_ignore_short;\n\tu8 rx_ignore_long;\n\tu8 rx_burst_size;\n} __attribute__((packed));\n\nstruct ti_sci_msg_rm_udmap_tx_ch_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu8 tx_pause_on_err;\n\tu8 tx_filt_einfo;\n\tu8 tx_filt_pswords;\n\tu8 tx_atype;\n\tu8 tx_chan_type;\n\tu8 tx_supr_tdpkt;\n\tu16 tx_fetch_size;\n\tu8 tx_credit_count;\n\tu16 txcq_qnum;\n\tu8 tx_priority;\n\tu8 tx_qos;\n\tu8 tx_orderid;\n\tu16 fdepth;\n\tu8 tx_sched_priority;\n\tu8 tx_burst_size;\n\tu8 tx_tdtype;\n\tu8 extended_ch_type;\n};\n\nstruct ti_sci_msg_rm_udmap_tx_ch_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu8 tx_pause_on_err;\n\tu8 tx_filt_einfo;\n\tu8 tx_filt_pswords;\n\tu8 tx_atype;\n\tu8 tx_chan_type;\n\tu8 tx_supr_tdpkt;\n\tu16 tx_fetch_size;\n\tu8 tx_credit_count;\n\tu16 txcq_qnum;\n\tu8 tx_priority;\n\tu8 tx_qos;\n\tu8 tx_orderid;\n\tu16 fdepth;\n\tu8 tx_sched_priority;\n\tu8 tx_burst_size;\n\tu8 tx_tdtype;\n\tu8 extended_ch_type;\n} __attribute__((packed));\n\nstruct ti_sci_pm_domain {\n\tint idx;\n\tu8 exclusive;\n\tstruct generic_pm_domain pd;\n\tstruct list_head node;\n\tstruct ti_sci_genpd_provider *parent;\n\tlong: 32;\n};\n\nstruct ti_sci_resource {\n\tu16 sets;\n\traw_spinlock_t lock;\n\tstruct ti_sci_resource_desc *desc;\n};\n\nstruct ti_sci_resource_desc {\n\tu16 start;\n\tu16 num;\n\tu16 start_sec;\n\tu16 num_sec;\n\tlong unsigned int *res_map;\n};\n\nstruct ti_sci_xfer {\n\tstruct ti_msgmgr_message tx_message;\n\tu8 rx_len;\n\tu8 *xfer_buf;\n\tstruct completion done;\n};\n\nstruct ti_sysc_module_data {\n\tconst char *name;\n\tlong: 32;\n\tu64 module_pa;\n\tu32 module_size;\n\tint *offsets;\n\tint nr_offsets;\n\tconst struct sysc_capabilities *cap;\n\tstruct sysc_config *cfg;\n\tlong: 32;\n};\n\nstruct ti_sysc_platform_data {\n\tstruct of_dev_auxdata *auxdata;\n\tbool (*soc_type_gp)(void);\n\tint (*init_clockdomain)(struct device *, struct clk *, struct clk *, struct ti_sysc_cookie *);\n\tvoid (*clkdm_deny_idle)(struct device *, const struct ti_sysc_cookie *);\n\tvoid (*clkdm_allow_idle)(struct device *, const struct ti_sysc_cookie *);\n\tint (*init_module)(struct device *, const struct ti_sysc_module_data *, struct ti_sysc_cookie *);\n\tint (*enable_module)(struct device *, const struct ti_sysc_cookie *);\n\tint (*idle_module)(struct device *, const struct ti_sysc_cookie *);\n\tint (*shutdown_module)(struct device *, const struct ti_sysc_cookie *);\n};\n\nstruct ti_syscon_gate_clk_data {\n\tchar *name;\n\tu32 offset;\n\tu32 bit_idx;\n};\n\nstruct ti_syscon_gate_clk_priv {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 reg;\n\tu32 idx;\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tlong: 32;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tlong: 32;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tlong: 32;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tlong: 32;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tlong: 32;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[16];\n\tstruct hlist_head vectors[512];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct timer_cker {\n\tspinlock_t *lock;\n\tvoid *apbdiv;\n\tvoid *timpre;\n\tstruct clk_hw hw;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_of {\n\tunsigned int flags;\n\tstruct device_node *np;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device clkevt;\n\tstruct of_timer_base of_base;\n\tstruct of_timer_irq of_irq;\n\tstruct of_timer_clk of_clk;\n\tvoid *private_data;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tlong: 32;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timerlat_entry {\n\tstruct trace_entry ent;\n\tunsigned int seqnum;\n\tint context;\n\tu64 timer_latency;\n};\n\nstruct timestamp_event_queue {\n\tstruct ptp_extts_event buf[128];\n\tint head;\n\tint tail;\n\tspinlock_t lock;\n\tstruct list_head qlist;\n\tlong unsigned int *mask;\n\tstruct dentry *debugfs_instance;\n\tstruct debugfs_u32_array dfs_bitmap;\n\tlong: 32;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct timing {\n\tu8 u1sel;\n\tu8 u1pel;\n\t__le16 u2sel;\n\t__le16 u2pel;\n};\n\nstruct timing_regs {\n\tunsigned int tsusta;\n\tunsigned int tsusto;\n\tunsigned int thdsta;\n\tunsigned int tsudat;\n\tunsigned int tbuf;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tlong: 32;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n\tlong: 32;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tlong: 32;\n\tstruct tk_read_base base[2];\n};\n\nstruct tlb_args {\n\tstruct vm_area_struct *ta_vma;\n\tlong unsigned int ta_start;\n\tlong unsigned int ta_end;\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\ntypedef void (*tls_done_func_t)(void *, int, key_serial_t);\n\nstruct tls_handshake_args {\n\tstruct socket *ta_sock;\n\ttls_done_func_t ta_done;\n\tvoid *ta_data;\n\tconst char *ta_peername;\n\tunsigned int ta_timeout_ms;\n\tkey_serial_t ta_keyring;\n\tkey_serial_t ta_my_cert;\n\tkey_serial_t ta_my_privkey;\n\tunsigned int ta_num_peerids;\n\tkey_serial_t ta_my_peerids[5];\n};\n\nstruct tls_handshake_req {\n\tvoid (*th_consumer_done)(void *, int, key_serial_t);\n\tvoid *th_consumer_data;\n\tint th_type;\n\tunsigned int th_timeout_ms;\n\tint th_auth_mode;\n\tconst char *th_peername;\n\tkey_serial_t th_keyring;\n\tkey_serial_t th_certificate;\n\tkey_serial_t th_privkey;\n\tunsigned int th_num_peerids;\n\tkey_serial_t th_peerid[5];\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmds_config {\n\tunsigned int pclk;\n\tu32 pll0;\n\tu32 pll1;\n\tu32 pe_current;\n\tu32 drive_current;\n\tu32 peak_current;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n\tlong: 32;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tlong: 32;\n\tu64 now;\n\tbool check;\n\tlong: 32;\n};\n\nstruct tmio_mmc_dma_ops {\n\tvoid (*start)(struct tmio_mmc_host *, struct mmc_data *);\n\tvoid (*enable)(struct tmio_mmc_host *, bool);\n\tvoid (*request)(struct tmio_mmc_host *, struct tmio_mmc_data *);\n\tvoid (*release)(struct tmio_mmc_host *);\n\tvoid (*abort)(struct tmio_mmc_host *);\n\tvoid (*dataend)(struct tmio_mmc_host *);\n\tvoid (*end)(struct tmio_mmc_host *);\n\tbool (*dma_irq)(struct tmio_mmc_host *);\n};\n\nstruct tmio_mmc_host {\n\tvoid *ctl;\n\tstruct mmc_command *cmd;\n\tstruct mmc_request *mrq;\n\tstruct mmc_data *data;\n\tstruct mmc_host *mmc;\n\tstruct mmc_host_ops ops;\n\tstruct scatterlist *sg_ptr;\n\tstruct scatterlist *sg_orig;\n\tunsigned int sg_len;\n\tunsigned int sg_off;\n\tunsigned int bus_shift;\n\tstruct platform_device *pdev;\n\tstruct tmio_mmc_data *pdata;\n\tbool dma_on;\n\tstruct dma_chan *chan_rx;\n\tstruct dma_chan *chan_tx;\n\tstruct work_struct dma_issue;\n\tstruct scatterlist bounce_sg;\n\tu8 *bounce_buf;\n\tstruct delayed_work delayed_reset_work;\n\tstruct work_struct done;\n\tu32 sdcard_irq_mask;\n\tu32 sdio_irq_mask;\n\tunsigned int clk_cache;\n\tu32 sdcard_irq_setbit_mask;\n\tu32 sdcard_irq_mask_all;\n\tspinlock_t lock;\n\tlong unsigned int last_req_ts;\n\tstruct mutex ios_lock;\n\tbool native_hotplug;\n\tbool sdio_irq_enabled;\n\tint (*clk_enable)(struct tmio_mmc_host *);\n\tvoid (*set_clock)(struct tmio_mmc_host *, unsigned int);\n\tvoid (*clk_disable)(struct tmio_mmc_host *);\n\tint (*multi_io_quirk)(struct mmc_card *, unsigned int, int);\n\tint (*write16_hook)(struct tmio_mmc_host *, int);\n\tvoid (*reset)(struct tmio_mmc_host *, bool);\n\tbool (*check_retune)(struct tmio_mmc_host *, struct mmc_request *);\n\tvoid (*fixup_request)(struct tmio_mmc_host *, struct mmc_request *);\n\tunsigned int (*get_timeout_cycles)(struct tmio_mmc_host *);\n\tvoid (*sdio_irq)(struct tmio_mmc_host *);\n\tconst struct tmio_mmc_dma_ops *dma_ops;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnl_ptk_info {\n\tlong unsigned int flags[1];\n\t__be16 proto;\n\t__be32 key;\n\t__be32 seq;\n\tint hdr_len;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nstruct tp_transition_snapshot {\n\tlong unsigned int rcu;\n\tlong unsigned int srcu_gp;\n\tbool ongoing;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct tps51632_chip {\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct regulator_dev *rdev;\n\tstruct regmap *regmap;\n};\n\nstruct tps51632_regulator_platform_data {\n\tstruct regulator_init_data *reg_init_data;\n\tbool enable_pwm_dvfs;\n\tbool dvfs_step_20mV;\n\tint max_voltage_uV;\n\tint base_voltage_uV;\n};\n\nstruct tps62360_chip {\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct regulator_dev *rdev;\n\tstruct regmap *regmap;\n\tstruct gpio_desc *vsel0_gpio;\n\tstruct gpio_desc *vsel1_gpio;\n\tu8 voltage_reg_mask;\n\tbool en_internal_pulldn;\n\tbool en_discharge;\n\tbool valid_gpios;\n\tint lru_index[4];\n\tint curr_vset_vsel[4];\n\tint curr_vset_id;\n};\n\nstruct tps62360_regulator_platform_data {\n\tstruct regulator_init_data *reg_init_data;\n\tbool en_discharge;\n\tbool en_internal_pulldn;\n\tint vsel0_def_state;\n\tint vsel1_def_state;\n};\n\nstruct tps65090 {\n\tstruct device *dev;\n\tstruct regmap *rmap;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct tps65090_platform_data;\n\nstruct tps65090_charger {\n\tstruct device *dev;\n\tint ac_online;\n\tint prev_ac_online;\n\tint irq;\n\tstruct task_struct *poll_task;\n\tbool passive_mode;\n\tstruct power_supply *ac;\n\tstruct tps65090_platform_data *pdata;\n};\n\nstruct tps65090_regulator_plat_data;\n\nstruct tps65090_platform_data {\n\tint irq_base;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tint enable_low_current_chrg;\n\tstruct tps65090_regulator_plat_data *reg_pdata[12];\n};\n\nstruct tps65090_regulator {\n\tstruct device *dev;\n\tstruct regulator_desc *desc;\n\tstruct regulator_dev *rdev;\n\tbool overcurrent_wait_valid;\n\tint overcurrent_wait;\n};\n\nstruct tps65090_regulator_plat_data {\n\tstruct regulator_init_data *reg_init_data;\n\tbool enable_ext_control;\n\tstruct gpio_desc *gpiod;\n\tbool overcurrent_wait_valid;\n\tint overcurrent_wait;\n};\n\nstruct tps65217_board;\n\nstruct tps65217 {\n\tstruct device *dev;\n\tstruct tps65217_board *pdata;\n\tstruct regulator_desc desc[7];\n\tstruct regmap *regmap;\n\tu8 *strobes;\n\tstruct irq_domain *irq_domain;\n\tstruct mutex irq_lock;\n\tu8 irq_mask;\n\tint irq;\n};\n\nstruct tps65217_bl_pdata {\n\tenum tps65217_bl_isel isel;\n\tenum tps65217_bl_fdim fdim;\n\tint dft_brightness;\n};\n\nstruct tps65217_board {\n\tstruct regulator_init_data *tps65217_init_data[7];\n\tstruct device_node *of_node[7];\n\tstruct tps65217_bl_pdata *bl_pdata;\n};\n\nstruct tps65218 {\n\tstruct device *dev;\n\tunsigned int id;\n\tu8 rev;\n\tstruct mutex tps_lock;\n\tint irq;\n\tu32 irq_mask;\n\tstruct regmap_irq_chip_data *irq_data;\n\tstruct regulator_desc desc[9];\n\tstruct regmap *regmap;\n\tu8 *strobes;\n};\n\nstruct tps65219 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct tps65219_chip_data {\n\tconst struct regmap_irq_chip *irq_chip;\n\tconst struct mfd_cell *cells;\n\tint n_cells;\n};\n\nstruct tps65219_regulator_irq_type;\n\nstruct tps65219_chip_data___2 {\n\tsize_t rdesc_size;\n\tsize_t common_rdesc_size;\n\tsize_t dev_irq_size;\n\tsize_t common_irq_size;\n\tconst struct regulator_desc *rdesc;\n\tconst struct regulator_desc *common_rdesc;\n\tstruct tps65219_regulator_irq_type *irq_types;\n\tstruct tps65219_regulator_irq_type *common_irq_types;\n};\n\nstruct tps65219_gpio {\n\tint (*change_dir)(struct gpio_chip *, unsigned int, unsigned int);\n\tstruct gpio_chip gpio_chip;\n\tstruct tps65219 *tps;\n};\n\nstruct tps65219_regulator_irq_data {\n\tstruct device *dev;\n\tstruct tps65219_regulator_irq_type *type;\n\tstruct regulator_dev *rdev;\n};\n\nstruct tps65219_regulator_irq_type {\n\tconst char *irq_name;\n\tconst char *regulator_name;\n\tconst char *event_name;\n\tlong unsigned int event;\n};\n\nstruct tps6586x {\n\tstruct device *dev;\n\tstruct i2c_client *client;\n\tstruct regmap *regmap;\n\tint version;\n\tint irq;\n\tstruct irq_chip irq_chip;\n\tstruct mutex irq_lock;\n\tint irq_base;\n\tu32 irq_en;\n\tu8 mask_reg[5];\n\tstruct irq_domain *irq_domain;\n};\n\nstruct tps6586x_gpio {\n\tstruct gpio_chip gpio_chip;\n\tstruct device *parent;\n};\n\nstruct tps6586x_irq_data {\n\tu8 mask_reg;\n\tu8 mask_mask;\n};\n\nstruct tps6586x_subdev_info;\n\nstruct tps6586x_platform_data {\n\tint num_subdevs;\n\tstruct tps6586x_subdev_info *subdevs;\n\tint gpio_base;\n\tint irq_base;\n\tbool pm_off;\n\tstruct regulator_init_data *reg_init_data[15];\n};\n\nstruct tps6586x_regulator {\n\tstruct regulator_desc desc;\n\tint enable_bit[2];\n\tint enable_reg[2];\n};\n\nstruct tps6586x_rtc {\n\tstruct device *dev;\n\tstruct rtc_device *rtc;\n\tint irq;\n\tbool irq_en;\n};\n\nstruct tps6586x_settings {\n\tint slew_rate;\n};\n\nstruct tps6586x_subdev_info {\n\tint id;\n\tconst char *name;\n\tvoid *platform_data;\n\tstruct device_node *of_node;\n};\n\nstruct tps65910_board;\n\nstruct tps65910 {\n\tstruct device *dev;\n\tstruct i2c_client *i2c_client;\n\tstruct regmap *regmap;\n\tlong unsigned int id;\n\tstruct tps65910_board *of_plat_data;\n\tint chip_irq;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct tps65910_sleep_keepon_data {\n\tunsigned int therm_keepon: 1;\n\tunsigned int clkout32k_keepon: 1;\n\tunsigned int i2chs_keepon: 1;\n};\n\nstruct tps65910_board {\n\tint gpio_base;\n\tint irq;\n\tint irq_base;\n\tint vmbch_threshold;\n\tint vmbch2_threshold;\n\tbool en_ck32k_xtal;\n\tbool en_dev_slp;\n\tbool pm_off;\n\tstruct tps65910_sleep_keepon_data slp_keepon;\n\tbool en_gpio_sleep[9];\n\tlong unsigned int regulator_ext_sleep_control[14];\n\tstruct regulator_init_data *tps65910_pmic_init_data[14];\n};\n\nstruct tps65910_gpio {\n\tstruct gpio_chip gpio_chip;\n\tstruct tps65910 *tps65910;\n};\n\nstruct tps65910_platform_data {\n\tint irq;\n\tint irq_base;\n};\n\nstruct tps_info;\n\nstruct tps65910_reg {\n\tstruct regulator_desc *desc;\n\tstruct tps65910 *mfd;\n\tstruct regulator_dev **rdev;\n\tstruct tps_info **info;\n\tint num_regulators;\n\tint mode;\n\tint (*get_ctrl_reg)(int);\n\tunsigned int *ext_sleep_control;\n\tunsigned int board_ext_control[14];\n};\n\nstruct tps65910_rtc {\n\tstruct rtc_device *rtc;\n\tint irq;\n};\n\nstruct tps_info {\n\tconst char *name;\n\tconst char *vin_name;\n\tu8 n_voltages;\n\tconst unsigned int *voltage_table;\n\tint enable_time_us;\n};\n\nstruct tpu_device;\n\nstruct tpu_pwm_device {\n\tbool timer_on;\n\tstruct tpu_device *tpu;\n\tunsigned int channel;\n\tenum pwm_polarity polarity;\n\tunsigned int prescaler;\n\tu16 period;\n\tu16 duty;\n};\n\nstruct tpu_device {\n\tstruct platform_device *pdev;\n\tspinlock_t lock;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct tpu_pwm_device tpd[4];\n};\n\nstruct trace_module_delta;\n\nstruct trace_pid_list;\n\nstruct tracer_flags;\n\nstruct trace_options;\n\nstruct trace_func_repeats;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tlong: 32;\n\tstruct array_buffer array_buffer;\n\tunsigned int mapped;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_size;\n\tchar *range_name;\n\tlong int text_delta;\n\tstruct trace_module_delta *module_delta;\n\tvoid *scratch;\n\tint scratch_size;\n\tint buffer_disabled;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tstruct tracer_flags *current_trace_flags;\n\tu64 trace_flags;\n\tunsigned char trace_flags_index[64];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tconst char *system_names;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct eventfs_inode *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct list_head marker_list;\n\tstruct list_head tracers;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tcpumask_var_t pipe_cpumask;\n\tint ref;\n\tint trace_ref;\n\tstruct list_head mod_events;\n\tint no_filter_buffering_ref;\n\tunsigned int syscall_buf_sz;\n\tstruct list_head hist_vars;\n\tstruct trace_func_repeats *last_func_repeats;\n\tbool ring_buffer_expanded;\n\tlong: 32;\n};\n\nstruct trace_array_cpu {\n\tlocal_t disabled;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tbool ignore_pid;\n\tlong: 32;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\ntypedef struct trace_buffer *class_ring_buffer_nest_t;\n\nstruct trace_buffer {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tatomic_t resizing;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)(void);\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_end;\n\tstruct ring_buffer_meta *meta;\n\tunsigned int subbuf_size;\n\tunsigned int subbuf_order;\n\tunsigned int max_data_size;\n};\n\nstruct trace_buffer_meta {\n\t__u32 meta_page_size;\n\t__u32 meta_struct_len;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tstruct {\n\t\t__u64 lost_events;\n\t\t__u32 id;\n\t\t__u32 read;\n\t} reader;\n\t__u64 flags;\n\t__u64 entries;\n\t__u64 overrun;\n\t__u64 read;\n\t__u64 Reserved1;\n\t__u64 Reserved2;\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct trace_probe_event;\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_entry_arg *entry_arg;\n\tstruct probe_arg args[0];\n};\n\nstruct trace_eprobe {\n\tconst char *event_system;\n\tconst char *event_name;\n\tchar *filter_str;\n\tstruct trace_event_call *event;\n\tstruct dyn_event devent;\n\tstruct trace_probe tp;\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tunsigned int trace_ctx;\n\tstruct pt_regs *regs;\n};\n\nstruct trace_event_class;\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tconst char *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tunion {\n\t\tvoid *module;\n\t\tatomic_t refcnt;\n\t};\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct trace_event_fields;\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_event_data_offsets_alarm_class {};\n\nstruct trace_event_data_offsets_alarmtimer_suspend {};\n\nstruct trace_event_data_offsets_alloc_vmap_area {};\n\nstruct trace_event_data_offsets_arm_event {\n\tu32 pei_buf;\n\tconst void *pei_buf_ptr_;\n\tu32 ctx_buf;\n\tconst void *ctx_buf_ptr_;\n\tu32 oem_buf;\n\tconst void *oem_buf_ptr_;\n};\n\nstruct trace_event_data_offsets_ata_bmdma_status {};\n\nstruct trace_event_data_offsets_ata_eh_action_template {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy_qc {};\n\nstruct trace_event_data_offsets_ata_exec_command_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_begin_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_end_template {};\n\nstruct trace_event_data_offsets_ata_port_eh_begin_template {};\n\nstruct trace_event_data_offsets_ata_qc_complete_template {};\n\nstruct trace_event_data_offsets_ata_qc_issue_template {};\n\nstruct trace_event_data_offsets_ata_sff_hsm_template {};\n\nstruct trace_event_data_offsets_ata_sff_template {};\n\nstruct trace_event_data_offsets_ata_tf_load {};\n\nstruct trace_event_data_offsets_ata_transfer_data_template {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_bl_ext_tree_prepare_commit {};\n\nstruct trace_event_data_offsets_blkdev_zone_mgmt {};\n\nstruct trace_event_data_offsets_block_bio {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_completion {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_zwplug {};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\nstruct trace_event_data_offsets_bpf_trace_printk {\n\tu32 bpf_string;\n\tconst void *bpf_string_ptr_;\n};\n\nstruct trace_event_data_offsets_bpf_trigger_tp {};\n\nstruct trace_event_data_offsets_bpf_xdp_link_attach_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cap_capable {};\n\nstruct trace_event_data_offsets_cdev_update {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tconst void *dst_path_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_rstat {};\n\nstruct trace_event_data_offsets_ci_log {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_ci_log_trb {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_duty_cycle {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_parent {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 pname;\n\tconst void *pname_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_phase {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate_range {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate_request {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 pname;\n\tconst void *pname_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_busy_retry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_finish {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_start {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_release {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_compact_retry {};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_contention_begin {};\n\nstruct trace_event_data_offsets_contention_end {};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_cpu_idle_miss {};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_csd_function {};\n\nstruct trace_event_data_offsets_csd_queue_cpu {};\n\nstruct trace_event_data_offsets_ctime {};\n\nstruct trace_event_data_offsets_ctime_ns_xchg {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_devfreq_frequency {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devfreq_monitor {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_end {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_start {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 parent;\n\tconst void *parent_ptr_;\n\tu32 pm_ops;\n\tconst void *pm_ops_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_recover_aborted {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_reporter_state_update {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwerr {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwmsg {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_trap_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 trap_name;\n\tconst void *trap_name_ptr_;\n\tu32 trap_group_name;\n\tconst void *trap_group_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devres {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_attach_dev {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_fd {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence_unsignaled {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg_err {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_single {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 addrs;\n\tconst void *addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dql_stall_detected {};\n\nstruct trace_event_data_offsets_drm_vblank_event {};\n\nstruct trace_event_data_offsets_drm_vblank_event_delivered {};\n\nstruct trace_event_data_offsets_drm_vblank_event_queued {};\n\nstruct trace_event_data_offsets_dwc3_log_ctrl {};\n\nstruct trace_event_data_offsets_dwc3_log_ep {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dwc3_log_event {};\n\nstruct trace_event_data_offsets_dwc3_log_gadget_ep_cmd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dwc3_log_generic_cmd {};\n\nstruct trace_event_data_offsets_dwc3_log_io {};\n\nstruct trace_event_data_offsets_dwc3_log_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dwc3_log_set_prtcap {};\n\nstruct trace_event_data_offsets_dwc3_log_trb {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_e1000e_trace_mac_register {};\n\nstruct trace_event_data_offsets_edma_log_io {};\n\nstruct trace_event_data_offsets_edma_log_tcd {};\n\nstruct trace_event_data_offsets_error_report_template {};\n\nstruct trace_event_data_offsets_exit_mmap {};\n\nstruct trace_event_data_offsets_ext4__bitmap_load {};\n\nstruct trace_event_data_offsets_ext4__es_extent {};\n\nstruct trace_event_data_offsets_ext4__es_shrink_enter {};\n\nstruct trace_event_data_offsets_ext4__fallocate_mode {};\n\nstruct trace_event_data_offsets_ext4__folio_op {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_enter {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_exit {};\n\nstruct trace_event_data_offsets_ext4__mb_new_pa {};\n\nstruct trace_event_data_offsets_ext4__mballoc {};\n\nstruct trace_event_data_offsets_ext4__trim {};\n\nstruct trace_event_data_offsets_ext4__truncate {};\n\nstruct trace_event_data_offsets_ext4__write_begin {};\n\nstruct trace_event_data_offsets_ext4__write_end {};\n\nstruct trace_event_data_offsets_ext4_alloc_da_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_inode {};\n\nstruct trace_event_data_offsets_ext4_begin_ordered_truncate {};\n\nstruct trace_event_data_offsets_ext4_collapse_range {};\n\nstruct trace_event_data_offsets_ext4_da_release_space {};\n\nstruct trace_event_data_offsets_ext4_da_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_update_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_end {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_start {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages_extent {};\n\nstruct trace_event_data_offsets_ext4_discard_blocks {};\n\nstruct trace_event_data_offsets_ext4_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_drop_inode {};\n\nstruct trace_event_data_offsets_ext4_error {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_enter {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_exit {};\n\nstruct trace_event_data_offsets_ext4_es_insert_delayed_extent {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_es_remove_extent {};\n\nstruct trace_event_data_offsets_ext4_es_shrink {};\n\nstruct trace_event_data_offsets_ext4_es_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_ext4_evict_inode {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_enter {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_fastpath {};\n\nstruct trace_event_data_offsets_ext4_ext_handle_unwritten_extents {};\n\nstruct trace_event_data_offsets_ext4_ext_load_extent {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space_done {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_idx {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_leaf {};\n\nstruct trace_event_data_offsets_ext4_ext_show_extent {};\n\nstruct trace_event_data_offsets_ext4_fallocate_exit {};\n\nstruct trace_event_data_offsets_ext4_fc_cleanup {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_start {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_stop {};\n\nstruct trace_event_data_offsets_ext4_fc_replay {};\n\nstruct trace_event_data_offsets_ext4_fc_replay_scan {};\n\nstruct trace_event_data_offsets_ext4_fc_stats {};\n\nstruct trace_event_data_offsets_ext4_fc_track_dentry {};\n\nstruct trace_event_data_offsets_ext4_fc_track_inode {};\n\nstruct trace_event_data_offsets_ext4_fc_track_range {};\n\nstruct trace_event_data_offsets_ext4_forget {};\n\nstruct trace_event_data_offsets_ext4_free_blocks {};\n\nstruct trace_event_data_offsets_ext4_free_inode {};\n\nstruct trace_event_data_offsets_ext4_fsmap_class {};\n\nstruct trace_event_data_offsets_ext4_get_implied_cluster_alloc_exit {};\n\nstruct trace_event_data_offsets_ext4_getfsmap_class {};\n\nstruct trace_event_data_offsets_ext4_insert_range {};\n\nstruct trace_event_data_offsets_ext4_invalidate_folio_op {};\n\nstruct trace_event_data_offsets_ext4_journal_start_inode {};\n\nstruct trace_event_data_offsets_ext4_journal_start_reserved {};\n\nstruct trace_event_data_offsets_ext4_journal_start_sb {};\n\nstruct trace_event_data_offsets_ext4_lazy_itable_init {};\n\nstruct trace_event_data_offsets_ext4_load_inode {};\n\nstruct trace_event_data_offsets_ext4_mark_inode_dirty {};\n\nstruct trace_event_data_offsets_ext4_mb_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_mb_release_group_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_inode_pa {};\n\nstruct trace_event_data_offsets_ext4_mballoc_alloc {};\n\nstruct trace_event_data_offsets_ext4_mballoc_prealloc {};\n\nstruct trace_event_data_offsets_ext4_move_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_move_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_nfs_commit_metadata {};\n\nstruct trace_event_data_offsets_ext4_other_inode_update_time {};\n\nstruct trace_event_data_offsets_ext4_prefetch_bitmaps {};\n\nstruct trace_event_data_offsets_ext4_read_block_bitmap_load {};\n\nstruct trace_event_data_offsets_ext4_remove_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_inode {};\n\nstruct trace_event_data_offsets_ext4_shutdown {};\n\nstruct trace_event_data_offsets_ext4_sync_file_enter {};\n\nstruct trace_event_data_offsets_ext4_sync_file_exit {};\n\nstruct trace_event_data_offsets_ext4_sync_fs {};\n\nstruct trace_event_data_offsets_ext4_unlink_enter {};\n\nstruct trace_event_data_offsets_ext4_unlink_exit {};\n\nstruct trace_event_data_offsets_ext4_update_sb {};\n\nstruct trace_event_data_offsets_ext4_writepages {};\n\nstruct trace_event_data_offsets_ext4_writepages_result {};\n\nstruct trace_event_data_offsets_ff_layout_commit_error {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_fib6_table_lookup {};\n\nstruct trace_event_data_offsets_fib_table_lookup {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_fill_mg_cmtime {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_fl_getdevinfo {\n\tu32 mds_addr;\n\tconst void *mds_addr_ptr_;\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_free_vmap_area_noflush {};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_gpio_direction {};\n\nstruct trace_event_data_offsets_gpio_value {};\n\nstruct trace_event_data_offsets_gpu_mem_total {};\n\nstruct trace_event_data_offsets_guest_halt_poll_ns {};\n\nstruct trace_event_data_offsets_handshake_alert_class {};\n\nstruct trace_event_data_offsets_handshake_complete {};\n\nstruct trace_event_data_offsets_handshake_error_class {};\n\nstruct trace_event_data_offsets_handshake_event_class {};\n\nstruct trace_event_data_offsets_handshake_fd_class {};\n\nstruct trace_event_data_offsets_host1x {};\n\nstruct trace_event_data_offsets_host1x_cdma_push {};\n\nstruct trace_event_data_offsets_host1x_cdma_push_gather {\n\tu32 cmdbuf;\n\tconst void *cmdbuf_ptr_;\n};\n\nstruct trace_event_data_offsets_host1x_cdma_push_wide {};\n\nstruct trace_event_data_offsets_host1x_channel_submit {};\n\nstruct trace_event_data_offsets_host1x_channel_submit_complete {};\n\nstruct trace_event_data_offsets_host1x_channel_submitted {};\n\nstruct trace_event_data_offsets_host1x_syncpt_load_min {};\n\nstruct trace_event_data_offsets_host1x_syncpt_wait_check {};\n\nstruct trace_event_data_offsets_host1x_wait_cdma {};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_setup {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hw_pressure_update {};\n\nstruct trace_event_data_offsets_hwmon_attr_class {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_show_string {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_read {};\n\nstruct trace_event_data_offsets_i2c_reply {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_result {};\n\nstruct trace_event_data_offsets_i2c_slave {};\n\nstruct trace_event_data_offsets_i2c_write {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_icc_set_bw {\n\tu32 path_name;\n\tconst void *path_name_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 node_name;\n\tconst void *node_name_ptr_;\n};\n\nstruct trace_event_data_offsets_icc_set_bw_end {\n\tu32 path_name;\n\tconst void *path_name_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_icmp_send {};\n\nstruct trace_event_data_offsets_inet_sk_error_report {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n\tconst void *level_ptr_;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_cqe_overflow {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_defer {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_fail_link {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_local_work_run {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_req_failed {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_short_write {};\n\nstruct trace_event_data_offsets_io_uring_submit_req {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_add {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_work_run {};\n\nstruct trace_event_data_offsets_iomap_add_to_ioend {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_dio_complete {};\n\nstruct trace_event_data_offsets_iomap_dio_rw_begin {};\n\nstruct trace_event_data_offsets_iomap_iter {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_handler {};\n\nstruct trace_event_data_offsets_ipi_raise {\n\tu32 target_cpus;\n\tconst void *target_cpus_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_send_cpu {};\n\nstruct trace_event_data_offsets_ipi_send_cpumask {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint_stats {};\n\nstruct trace_event_data_offsets_jbd2_commit {};\n\nstruct trace_event_data_offsets_jbd2_end_commit {};\n\nstruct trace_event_data_offsets_jbd2_handle_extend {};\n\nstruct trace_event_data_offsets_jbd2_handle_start_class {};\n\nstruct trace_event_data_offsets_jbd2_handle_stats {};\n\nstruct trace_event_data_offsets_jbd2_journal_shrink {};\n\nstruct trace_event_data_offsets_jbd2_lock_buffer_stall {};\n\nstruct trace_event_data_offsets_jbd2_run_stats {};\n\nstruct trace_event_data_offsets_jbd2_shrink_checkpoint_list {};\n\nstruct trace_event_data_offsets_jbd2_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_jbd2_submit_inode_data {};\n\nstruct trace_event_data_offsets_jbd2_update_log_tail {};\n\nstruct trace_event_data_offsets_jbd2_write_superblock {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\nstruct trace_event_data_offsets_kfree {};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_kmalloc {};\n\nstruct trace_event_data_offsets_kmem_cache_alloc {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kmem_cache_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_ma_op {};\n\nstruct trace_event_data_offsets_ma_read {};\n\nstruct trace_event_data_offsets_ma_write {};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_mark_victim {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_mc_event {\n\tu32 msg;\n\tconst void *msg_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n\tu32 driver_detail;\n\tconst void *driver_detail_ptr_;\n};\n\nstruct trace_event_data_offsets_mdio_access {};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_migration_pte {};\n\nstruct trace_event_data_offsets_mm_calculate_totalreserve_pages {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_filemap_fault {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache_range {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\nstruct trace_event_data_offsets_mm_migrate_pages_start {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_lowmem_reserve {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 upper_name;\n\tconst void *upper_name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_wmarks {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_clear_hopeless {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_reclaim_fail {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\nstruct trace_event_data_offsets_mm_vmscan_reclaim_pages {};\n\nstruct trace_event_data_offsets_mm_vmscan_throttled {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_write_folio {};\n\nstruct trace_event_data_offsets_mmap_lock {};\n\nstruct trace_event_data_offsets_mmap_lock_acquire_returned {};\n\nstruct trace_event_data_offsets_mmc_request_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mmc_request_start {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_netlink_extack {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_cached_open {};\n\nstruct trace_event_data_offsets_nfs4_cb_error_class {};\n\nstruct trace_event_data_offsets_nfs4_cb_offload {};\n\nstruct trace_event_data_offsets_nfs4_cb_seqid_err {};\n\nstruct trace_event_data_offsets_nfs4_cb_sequence {};\n\nstruct trace_event_data_offsets_nfs4_clientid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_clone {};\n\nstruct trace_event_data_offsets_nfs4_close {};\n\nstruct trace_event_data_offsets_nfs4_commit_event {};\n\nstruct trace_event_data_offsets_nfs4_copy {};\n\nstruct trace_event_data_offsets_nfs4_copy_notify {};\n\nstruct trace_event_data_offsets_nfs4_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_delegreturn_exit {};\n\nstruct trace_event_data_offsets_nfs4_deviceid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_deviceid_status {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_flexfiles_io_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_getattr_event {};\n\nstruct trace_event_data_offsets_nfs4_idmap_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_event {};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_layoutget {};\n\nstruct trace_event_data_offsets_nfs4_llseek {};\n\nstruct trace_event_data_offsets_nfs4_lock_event {};\n\nstruct trace_event_data_offsets_nfs4_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_lookupp {};\n\nstruct trace_event_data_offsets_nfs4_match_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_offload_class {};\n\nstruct trace_event_data_offsets_nfs4_open_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_read_event {};\n\nstruct trace_event_data_offsets_nfs4_rename {\n\tu32 oldname;\n\tconst void *oldname_ptr_;\n\tu32 newname;\n\tconst void *newname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_sequence_done {};\n\nstruct trace_event_data_offsets_nfs4_set_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_set_lock {};\n\nstruct trace_event_data_offsets_nfs4_setup_sequence {};\n\nstruct trace_event_data_offsets_nfs4_sparse_event {};\n\nstruct trace_event_data_offsets_nfs4_state_lock_reclaim {};\n\nstruct trace_event_data_offsets_nfs4_state_mgr {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_state_mgr_failed {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n\tu32 section;\n\tconst void *section_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_test_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_trunked_exchange_id {\n\tu32 main_addr;\n\tconst void *main_addr_ptr_;\n\tu32 trunk_addr;\n\tconst void *trunk_addr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_write_event {};\n\nstruct trace_event_data_offsets_nfs4_xattr_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_xdr_bad_operation {};\n\nstruct trace_event_data_offsets_nfs4_xdr_event {};\n\nstruct trace_event_data_offsets_nfs_access_exit {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead_done {};\n\nstruct trace_event_data_offsets_nfs_atomic_open_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_atomic_open_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_commit_done {};\n\nstruct trace_event_data_offsets_nfs_create_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_create_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_direct_req_class {};\n\nstruct trace_event_data_offsets_nfs_directory_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_directory_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_fh_to_dentry {};\n\nstruct trace_event_data_offsets_nfs_folio_event {};\n\nstruct trace_event_data_offsets_nfs_folio_event_done {};\n\nstruct trace_event_data_offsets_nfs_initiate_commit {};\n\nstruct trace_event_data_offsets_nfs_initiate_read {};\n\nstruct trace_event_data_offsets_nfs_initiate_write {};\n\nstruct trace_event_data_offsets_nfs_inode_event {};\n\nstruct trace_event_data_offsets_nfs_inode_event_done {};\n\nstruct trace_event_data_offsets_nfs_inode_range_event {};\n\nstruct trace_event_data_offsets_nfs_kiocb_event {};\n\nstruct trace_event_data_offsets_nfs_link_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_link_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_local_open_fh {};\n\nstruct trace_event_data_offsets_nfs_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_lookup_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_assign {\n\tu32 option;\n\tconst void *option_ptr_;\n\tu32 value;\n\tconst void *value_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_option {\n\tu32 option;\n\tconst void *option_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_path {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_page_class {};\n\nstruct trace_event_data_offsets_nfs_page_error_class {};\n\nstruct trace_event_data_offsets_nfs_pgio_error {};\n\nstruct trace_event_data_offsets_nfs_readdir_event {};\n\nstruct trace_event_data_offsets_nfs_readpage_done {};\n\nstruct trace_event_data_offsets_nfs_readpage_short {};\n\nstruct trace_event_data_offsets_nfs_rename_event {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_rename_event_done {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_sillyrename_unlink {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_update_size_class {};\n\nstruct trace_event_data_offsets_nfs_writeback_done {};\n\nstruct trace_event_data_offsets_nfs_xdr_event {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_nlmclnt_lock_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_non_standard_event {\n\tu32 fru_text;\n\tconst void *fru_text_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_notifier_info {};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_optee_invoke_fn_begin {};\n\nstruct trace_event_data_offsets_optee_invoke_fn_end {};\n\nstruct trace_event_data_offsets_page_cache_ra_op {};\n\nstruct trace_event_data_offsets_page_cache_ra_order {};\n\nstruct trace_event_data_offsets_page_cache_ra_unbounded {};\n\nstruct trace_event_data_offsets_page_pool_release {};\n\nstruct trace_event_data_offsets_page_pool_state_hold {};\n\nstruct trace_event_data_offsets_page_pool_state_release {};\n\nstruct trace_event_data_offsets_page_pool_update_nid {};\n\nstruct trace_event_data_offsets_pci_hp_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n\tu32 slot;\n\tconst void *slot_ptr_;\n};\n\nstruct trace_event_data_offsets_pcie_link_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_pmap_register {};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_err_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_ds_connect {\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_layout_event {};\n\nstruct trace_event_data_offsets_pnfs_update_layout {};\n\nstruct trace_event_data_offsets_power_domain {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_psci_domain_idle {};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_purge_vmap_area_lazy {};\n\nstruct trace_event_data_offsets_pwm {};\n\nstruct trace_event_data_offsets_pwm_read_waveform {};\n\nstruct trace_event_data_offsets_pwm_round_waveform_fromhw {};\n\nstruct trace_event_data_offsets_pwm_round_waveform_tohw {};\n\nstruct trace_event_data_offsets_pwm_write_waveform {};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_enqueue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kvfree_callback {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_segcb_stats {};\n\nstruct trace_event_data_offsets_rcu_sr_normal {};\n\nstruct trace_event_data_offsets_rcu_stall_warning {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_watching {};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_regcache_drop_region {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regcache_sync {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 status;\n\tconst void *status_ptr_;\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_register_access {};\n\nstruct trace_event_data_offsets_register_class {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_async {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bool {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bulk {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_reg {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_basic {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_range {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_value {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_buf_alloc {};\n\nstruct trace_event_data_offsets_rpc_call_rpcerror {};\n\nstruct trace_event_data_offsets_rpc_clnt_class {};\n\nstruct trace_event_data_offsets_rpc_clnt_clone_err {};\n\nstruct trace_event_data_offsets_rpc_clnt_new {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_clnt_new_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_failure {};\n\nstruct trace_event_data_offsets_rpc_reply_event {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_request {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_socket_nospace {};\n\nstruct trace_event_data_offsets_rpc_stats_latency {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_queued {\n\tu32 q_name;\n\tconst void *q_name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_running {};\n\nstruct trace_event_data_offsets_rpc_task_status {};\n\nstruct trace_event_data_offsets_rpc_tls_class {\n\tu32 servername;\n\tconst void *servername_ptr_;\n\tu32 progname;\n\tconst void *progname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_alignment {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_rpc_xdr_overflow {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_lifetime_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_getport {\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_register {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_setport {};\n\nstruct trace_event_data_offsets_rpcb_unregister {\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_bad_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_context {\n\tu32 acceptor;\n\tconst void *acceptor_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_createauth {};\n\nstruct trace_event_data_offsets_rpcgss_ctx_class {\n\tu32 principal;\n\tconst void *principal_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_gssapi_event {};\n\nstruct trace_event_data_offsets_rpcgss_import_ctx {};\n\nstruct trace_event_data_offsets_rpcgss_need_reencode {};\n\nstruct trace_event_data_offsets_rpcgss_oid_to_mech {\n\tu32 oid;\n\tconst void *oid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_svc_accept_upcall {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_authenticate {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_gssapi_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_bad {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_class {};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_low {};\n\nstruct trace_event_data_offsets_rpcgss_svc_unwrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_wrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_unwrap_failed {};\n\nstruct trace_event_data_offsets_rpcgss_upcall_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_upcall_result {};\n\nstruct trace_event_data_offsets_rpcgss_update_slack {};\n\nstruct trace_event_data_offsets_rpm_internal {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_return_int {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_status {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\nstruct trace_event_data_offsets_rtc_alarm_irq_enable {};\n\nstruct trace_event_data_offsets_rtc_irq_set_freq {};\n\nstruct trace_event_data_offsets_rtc_irq_set_state {};\n\nstruct trace_event_data_offsets_rtc_offset_class {};\n\nstruct trace_event_data_offsets_rtc_time_alarm_class {};\n\nstruct trace_event_data_offsets_rtc_timer_class {};\n\nstruct trace_event_data_offsets_sched_ext_bypass_lb {};\n\nstruct trace_event_data_offsets_sched_ext_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_ext_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_end {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_start {};\n\nstruct trace_event_data_offsets_sched_kthread_work_queue_work {};\n\nstruct trace_event_data_offsets_sched_migrate_task {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_pi_setprio {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_prepare_exec {\n\tu32 interp;\n\tconst void *interp_ptr_;\n\tu32 filename;\n\tconst void *filename_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exit {};\n\nstruct trace_event_data_offsets_sched_process_fork {\n\tu32 parent_comm;\n\tconst void *parent_comm_ptr_;\n\tu32 child_comm;\n\tconst void *child_comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_wait {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_stat_runtime {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_scmi_fc_call {};\n\nstruct trace_event_data_offsets_scmi_msg_dump {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_scmi_rx_done {};\n\nstruct trace_event_data_offsets_scmi_xfer_begin {};\n\nstruct trace_event_data_offsets_scmi_xfer_end {};\n\nstruct trace_event_data_offsets_scmi_xfer_response_wait {};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_sk_data_ready {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_smbus_read {};\n\nstruct trace_event_data_offsets_smbus_reply {};\n\nstruct trace_event_data_offsets_smbus_result {};\n\nstruct trace_event_data_offsets_smbus_write {};\n\nstruct trace_event_data_offsets_smp2p_negotiate {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_smp2p_notify_in {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 client_name;\n\tconst void *client_name_ptr_;\n};\n\nstruct trace_event_data_offsets_smp2p_ssr_ack {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_smp2p_update_bits {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 client_name;\n\tconst void *client_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_sock_msg_length {};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_softirq {};\n\nstruct trace_event_data_offsets_spi_controller {};\n\nstruct trace_event_data_offsets_spi_mem_start_op {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 op;\n\tconst void *op_ptr_;\n\tu32 data;\n\tconst void *data_ptr_;\n};\n\nstruct trace_event_data_offsets_spi_mem_stop_op {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 data;\n\tconst void *data_ptr_;\n};\n\nstruct trace_event_data_offsets_spi_message {};\n\nstruct trace_event_data_offsets_spi_message_done {};\n\nstruct trace_event_data_offsets_spi_set_cs {};\n\nstruct trace_event_data_offsets_spi_setup {};\n\nstruct trace_event_data_offsets_spi_transfer {\n\tu32 rx_buf;\n\tconst void *rx_buf_ptr_;\n\tu32 tx_buf;\n\tconst void *tx_buf_ptr_;\n};\n\nstruct trace_event_data_offsets_spmi_cmd {};\n\nstruct trace_event_data_offsets_spmi_read_begin {};\n\nstruct trace_event_data_offsets_spmi_read_end {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_spmi_write_begin {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_spmi_write_end {};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_svc_alloc_arg_err {};\n\nstruct trace_event_data_offsets_svc_authenticate {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_deferred_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_pool_thread_event {};\n\nstruct trace_event_data_offsets_svc_process {\n\tu32 service;\n\tconst void *service_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_replace_page_err {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_status {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_stats_latency {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_unregister {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_svc_xdr_msg_class {};\n\nstruct trace_event_data_offsets_svc_xprt_accept {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_create_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_dequeue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_enqueue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_accept_class {\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_lifetime_class {};\n\nstruct trace_event_data_offsets_svcsock_marker {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_recv_short {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_state {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_prctl_unknown {};\n\nstruct trace_event_data_offsets_task_rename {};\n\nstruct trace_event_data_offsets_tasklet {};\n\nstruct trace_event_data_offsets_tcp_ao_event {};\n\nstruct trace_event_data_offsets_tcp_cong_state_set {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_event_skb {};\n\nstruct trace_event_data_offsets_tcp_hash_event {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\nstruct trace_event_data_offsets_tcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_tcp_retransmit_skb {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_send_reset {};\n\nstruct trace_event_data_offsets_tcp_sendmsg_locked {};\n\nstruct trace_event_data_offsets_tegra_dma_complete_cb {\n\tu32 chan;\n\tconst void *chan_ptr_;\n};\n\nstruct trace_event_data_offsets_tegra_dma_isr {\n\tu32 chan;\n\tconst void *chan_ptr_;\n};\n\nstruct trace_event_data_offsets_tegra_dma_tx_status {\n\tu32 chan;\n\tconst void *chan_ptr_;\n};\n\nstruct trace_event_data_offsets_test_pages_isolated {};\n\nstruct trace_event_data_offsets_thermal_power_cpu_get_power_simple {};\n\nstruct trace_event_data_offsets_thermal_power_cpu_limit {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_power_devfreq_get_power {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_power_devfreq_limit {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_temperature {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_zone_trip {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_tick_stop {};\n\nstruct trace_event_data_offsets_timer_base_idle {};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_tls_contenttype {};\n\nstruct trace_event_data_offsets_tmigr_connect_child_parent {};\n\nstruct trace_event_data_offsets_tmigr_connect_cpu_parent {};\n\nstruct trace_event_data_offsets_tmigr_cpugroup {};\n\nstruct trace_event_data_offsets_tmigr_group_and_cpu {};\n\nstruct trace_event_data_offsets_tmigr_group_set {};\n\nstruct trace_event_data_offsets_tmigr_handle_remote {};\n\nstruct trace_event_data_offsets_tmigr_idle {};\n\nstruct trace_event_data_offsets_tmigr_update_events {};\n\nstruct trace_event_data_offsets_udc_log_ep {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_udc_log_gadget {};\n\nstruct trace_event_data_offsets_udc_log_req {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_usb_core_log_usb_device {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_watchdog_set_timeout {};\n\nstruct trace_event_data_offsets_watchdog_template {};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_queue_work {\n\tu32 workqueue;\n\tconst void *workqueue_ptr_;\n};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_folio_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_data_offsets_xhci_dbc_log_request {};\n\nstruct trace_event_data_offsets_xhci_log_ctrl_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_doorbell {};\n\nstruct trace_event_data_offsets_xhci_log_ep_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_free_virt_dev {};\n\nstruct trace_event_data_offsets_xhci_log_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_portsc {};\n\nstruct trace_event_data_offsets_xhci_log_ring {};\n\nstruct trace_event_data_offsets_xhci_log_slot_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_stream_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_trb {};\n\nstruct trace_event_data_offsets_xhci_log_urb {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_virt_dev {};\n\nstruct trace_event_data_offsets_xprt_cong_event {};\n\nstruct trace_event_data_offsets_xprt_ping {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_reserve {};\n\nstruct trace_event_data_offsets_xprt_retransmit {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_transmit {};\n\nstruct trace_event_data_offsets_xprt_writelock_event {};\n\nstruct trace_event_data_offsets_xs_data_ready {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_socket_event {};\n\nstruct trace_event_data_offsets_xs_socket_event_done {};\n\nstruct trace_event_data_offsets_xs_stream_read_data {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_stream_read_request {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst unsigned int is_signed: 1;\n\t\t\tunsigned int needs_test: 1;\n\t\t\tconst int filter_type;\n\t\t\tconst int len;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct eventfs_inode *ei;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\trefcount_t ref;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarmtimer_suspend {\n\tstruct trace_entry ent;\n\ts64 expires;\n\tunsigned char alarm_type;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_alloc_vmap_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int vstart;\n\tlong unsigned int vend;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_arm_event {\n\tstruct trace_entry ent;\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n\tu8 affinity;\n\tu32 pei_len;\n\tu32 __data_loc_pei_buf;\n\tu32 ctx_len;\n\tu32 __data_loc_ctx_buf;\n\tu32 oem_len;\n\tu32 __data_loc_oem_buf;\n\tu8 sev;\n\tint cpu;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ata_bmdma_status {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char host_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_action_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy_qc {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_exec_command_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char feature;\n\tunsigned char hob_nsect;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tlong unsigned int deadline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_end_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tint rc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_port_eh_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_complete_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char status;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char error;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_issue_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tunsigned char proto;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_hsm_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int protocol;\n\tunsigned int hsm_state;\n\tunsigned char dev_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char hsm_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_tf_load {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_transfer_data_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int flags;\n\tunsigned int offset;\n\tunsigned int bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int wb_setpoint;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bl_ext_tree_prepare_commit {\n\tstruct trace_entry ent;\n\tint ret;\n\tsize_t count;\n\tu64 lwb;\n\tbool not_all_ranges;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_blkdev_zone_mgmt {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tsector_t nr_sectors;\n\tchar rwbs[10];\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_block_bio {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[10];\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[10];\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_completion {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_zwplug {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int zno;\n\tsector_t sector;\n\tunsigned int nr_sectors;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trace_printk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bpf_string;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trigger_tp {\n\tstruct trace_entry ent;\n\tint nonce;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_xdp_link_attach_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_event {\n\tstruct trace_entry ent;\n\tconst struct cache_head *h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cap_capable {\n\tstruct trace_entry ent;\n\tconst struct cred *cred;\n\tstruct user_namespace *target_ns;\n\tconst struct user_namespace *capable_ns;\n\tint cap;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cdev_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int target;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_level;\n\tu64 dst_id;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu32 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_rstat {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tint cpu;\n\tbool contended;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ci_log {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ci_log_trb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tstruct td_node *td;\n\tstruct usb_request *req;\n\tdma_addr_t dma;\n\ts32 td_remaining_size;\n\tu32 next;\n\tu32 token;\n\tu32 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_duty_cycle {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int num;\n\tunsigned int den;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_parent {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_pname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_phase {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint phase;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int rate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate_range {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_pname;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int prate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_busy_retry {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_finish {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tint errorno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int request_count;\n\tlong unsigned int available_count;\n\tlong unsigned int total_count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_release {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_begin {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_end {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_idle_miss {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool below;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_function {\n\tstruct trace_entry ent;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_queue_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\tu32 ctime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime_ns_xchg {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tu32 gen;\n\tu32 old;\n\tu32 new;\n\tu32 cur;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devfreq_frequency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tlong unsigned int freq;\n\tlong unsigned int prev_freq;\n\tlong unsigned int busy_time;\n\tlong unsigned int total_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devfreq_monitor {\n\tstruct trace_entry ent;\n\tlong unsigned int freq;\n\tlong unsigned int busy_time;\n\tlong unsigned int total_time;\n\tunsigned int polling_ms;\n\tu32 __data_loc_dev_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_parent;\n\tu32 __data_loc_pm_ops;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_recover_aborted {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tbool health_state;\n\tlong: 32;\n\tu64 time_since_last_recover;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_reporter_state_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu8 new_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwerr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tint err;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwmsg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tbool incoming;\n\tlong unsigned int type;\n\tu32 __data_loc_buf;\n\tsize_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_trap_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_trap_name;\n\tu32 __data_loc_trap_group_name;\n\tchar input_dev_name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devres {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tstruct device *dev;\n\tconst char *op;\n\tvoid *node;\n\tu32 __data_loc_name;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tgfp_t flags;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tgfp_t flags;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_attach_dev {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tstruct dma_buf_attachment *attach;\n\tbool is_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_fd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence_unsignaled {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_dma_free_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tlong: 32;\n\tu64 phys_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tint full_nents;\n\tint full_ents;\n\tbool truncated;\n\tu32 __data_loc_phys_addrs;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tint err;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_single {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tlong: 32;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tlong: 32;\n\tu64 addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_dma_unmap_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_addrs;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dql_stall_detected {\n\tstruct trace_entry ent;\n\tshort unsigned int thrs;\n\tunsigned int len;\n\tlong unsigned int last_reap;\n\tlong unsigned int hist_head;\n\tlong unsigned int now;\n\tlong unsigned int hist[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event {\n\tstruct trace_entry ent;\n\tint crtc;\n\tunsigned int seq;\n\tktime_t time;\n\tbool high_prec;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_drm_vblank_event_delivered {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event_queued {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_ctrl {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_ep {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tunsigned int maxpacket;\n\tunsigned int maxpacket_limit;\n\tunsigned int max_streams;\n\tunsigned int maxburst;\n\tunsigned int flags;\n\tunsigned int direction;\n\tu8 trb_enqueue;\n\tu8 trb_dequeue;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_event {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 event;\n\tu32 ep0state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_gadget_ep_cmd {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tunsigned int cmd;\n\tu32 param0;\n\tu32 param1;\n\tu32 param2;\n\tint cmd_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_generic_cmd {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tunsigned int cmd;\n\tu32 param;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_io {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tvoid *base;\n\tu32 offset;\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_request {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tstruct dwc3_request *req;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tint zero;\n\tint short_not_ok;\n\tint no_interrupt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_set_prtcap {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_trb {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tstruct dwc3_trb *trb;\n\tu32 bpl;\n\tu32 bph;\n\tu32 size;\n\tu32 ctrl;\n\tu32 type;\n\tu32 enqueue;\n\tu32 dequeue;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_e1000e_trace_mac_register {\n\tstruct trace_entry ent;\n\tuint32_t reg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_edma_log_io {\n\tstruct trace_entry ent;\n\tstruct fsl_edma_engine *edma;\n\tvoid *addr;\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_edma_log_tcd {\n\tstruct trace_entry ent;\n\tu64 saddr;\n\tu16 soff;\n\tu16 attr;\n\tu32 nbytes;\n\tu64 slast;\n\tu64 daddr;\n\tu16 doff;\n\tu16 citer;\n\tlong: 32;\n\tu64 dlast_sga;\n\tu16 csr;\n\tu16 biter;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_error_report_template {\n\tstruct trace_entry ent;\n\tenum error_detector error_detector;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exit_mmap {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tstruct maple_tree *mt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tlong: 32;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_shrink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_to_scan;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__fallocate_mode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tint mode;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4__folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int flags;\n\tlong: 32;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int mflags;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mb_new_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 pa_pstart;\n\t__u64 pa_lstart;\n\t__u32 pa_len;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4__mballoc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__trim {\n\tstruct trace_entry ent;\n\tint dev_major;\n\tint dev_minor;\n\t__u32 group;\n\tint start;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4__write_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int copied;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_alloc_da_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int data_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_allocate_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_begin_ordered_truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_collapse_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_release_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint freed_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_da_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint reserve_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_da_update_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint used_blocks;\n\tint reserved_data_blocks;\n\tint quota_claim;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 lblk;\n\t__u32 len;\n\t__u32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\t__u64 blk;\n\t__u64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_drop_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint drop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tconst char *function;\n\tunsigned int line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_es_insert_delayed_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tbool lclu_allocated;\n\tbool end_allocated;\n\tlong: 32;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tint found;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_remove_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t lblk;\n\tloff_t len;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tlong long unsigned int scan_time;\n\tint nr_skipped;\n\tint retried;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_evict_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_fastpath {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\text4_lblk_t i_lblk;\n\tunsigned int i_len;\n\text4_fsblk_t i_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_handle_unwritten_extents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tunsigned int allocated;\n\text4_fsblk_t newblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_load_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_ext_remove_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tlong: 32;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tshort unsigned int eh_entries;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_ext_rm_idx {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_leaf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t ee_lblk;\n\text4_fsblk_t ee_pblk;\n\tshort int ee_len;\n\tlong: 32;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_show_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tshort unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fallocate_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int blocks;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_cleanup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint j_fc_off;\n\tint full;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_stop {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nblks;\n\tint reason;\n\tint num_fc;\n\tint num_fc_ineligible;\n\tint nblks_agg;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint tag;\n\tint ino;\n\tint priv1;\n\tint priv2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint error;\n\tint off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int fc_ineligible_rc[13];\n\tlong unsigned int fc_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_numblks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_dentry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tlong int start;\n\tlong int end;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_forget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tint is_metadata;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tlong unsigned int count;\n\tint flags;\n\t__u16 mode;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_free_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u64 blocks;\n\t__u16 mode;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_fsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu32 agno;\n\tlong: 32;\n\tu64 bno;\n\tu64 len;\n\tu64 owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_implied_cluster_alloc_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\text4_lblk_t lblk;\n\tlong: 32;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu64 block;\n\tu64 len;\n\tu64 owner;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_insert_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_invalidate_folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tsize_t offset;\n\tsize_t length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_inode {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_reserved {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_lazy_itable_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_load_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mark_inode_dirty {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint needed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_group_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\t__u64 pa_pstart;\n\t__u32 pa_len;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_mb_release_inode_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\t__u32 count;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_mballoc_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 goal_logical;\n\tint goal_start;\n\t__u32 goal_group;\n\tint goal_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\t__u16 found;\n\t__u16 groups;\n\t__u16 buddy;\n\t__u16 flags;\n\t__u16 tail;\n\t__u8 cr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_prealloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tunsigned int orig_flags;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int m_len;\n\tu64 move_len;\n\tint move_type;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_nfs_commit_metadata {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_other_inode_update_time {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t orig_ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_prefetch_bitmaps {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\t__u32 next;\n\t__u32 ios;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_read_block_bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tbool prefetch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_remove_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\text4_fsblk_t ee_pblk;\n\text4_lblk_t ee_lblk;\n\tshort unsigned int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_request_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tint datasync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tlong: 32;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_update_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\text4_fsblk_t fsblk;\n\tunsigned int flags;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_writepages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_ext4_writepages_result {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tint pages_written;\n\tlong int pages_skipped;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ff_layout_commit_error {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib6_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu32 flowlabel;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[16];\n\t__u8 dst[16];\n\tu16 sport;\n\tu16 dport;\n\tu8 proto;\n\tu8 rt_type;\n\tchar name[16];\n\t__u8 gw[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tchar name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lease *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tlong unsigned int break_time;\n\tlong unsigned int downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int pid;\n\tunsigned int flags;\n\tunsigned char type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fill_mg_cmtime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\ttime64_t mtime_s;\n\tu32 ctime_ns;\n\tu32 mtime_ns;\n\tu32 gen;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fl_getdevinfo {\n\tstruct trace_entry ent;\n\tu32 __data_loc_mds_addr;\n\tunsigned char deviceid[16];\n\tu32 __data_loc_ds_ips;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_free_vmap_area_noflush {\n\tstruct trace_entry ent;\n\tlong unsigned int va_start;\n\tlong unsigned int nr_lazy;\n\tlong unsigned int nr_lazy_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpio_direction {\n\tstruct trace_entry ent;\n\tunsigned int gpio;\n\tint in;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpio_value {\n\tstruct trace_entry ent;\n\tunsigned int gpio;\n\tint get;\n\tint value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpu_mem_total {\n\tstruct trace_entry ent;\n\tuint32_t gpu_id;\n\tuint32_t pid;\n\tuint64_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_guest_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_alert_class {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int level;\n\tlong unsigned int description;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_complete {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint status;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_error_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint err;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_event_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_fd_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint fd;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_cdma_push {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tu32 op1;\n\tu32 op2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_cdma_push_gather {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tstruct host1x_bo *bo;\n\tu32 words;\n\tu32 offset;\n\tbool cmdbuf;\n\tu32 __data_loc_cmdbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_cdma_push_wide {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tu32 op1;\n\tu32 op2;\n\tu32 op3;\n\tu32 op4;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_channel_submit {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tu32 cmdbufs;\n\tu32 relocs;\n\tu32 syncpt_id;\n\tu32 syncpt_incrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_channel_submit_complete {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tint count;\n\tu32 thresh;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_channel_submitted {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tu32 syncpt_base;\n\tu32 syncpt_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_syncpt_load_min {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_syncpt_wait_check {\n\tstruct trace_entry ent;\n\tstruct host1x_bo *bo;\n\tu32 offset;\n\tu32 syncpt_id;\n\tu32 thresh;\n\tu32 min;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_host1x_wait_cdma {\n\tstruct trace_entry ent;\n\tconst char *name;\n\tu32 eventid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tlong: 32;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_hrtimer_setup {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_hw_pressure_update {\n\tstruct trace_entry ent;\n\tlong unsigned int hw_pressure;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_class {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tlong long int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_show_string {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tu32 __data_loc_label;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 nr_msgs;\n\t__s16 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_slave {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\tint ret;\n\t__u16 addr;\n\t__u16 len;\n\tenum i2c_slave_event event;\n\t__u8 buf[1];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icc_set_bw {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path_name;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_node_name;\n\tu32 avg_bw;\n\tu32 peak_bw;\n\tu32 node_avg_bw;\n\tu32 node_peak_bw;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icc_set_bw_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path_name;\n\tu32 __data_loc_dev;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icmp_send {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint type;\n\tint code;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u16 sport;\n\t__u16 dport;\n\tshort unsigned int ulen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sk_error_report {\n\tstruct trace_entry ent;\n\tint error;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\ntypedef int (*initcall_t)(void);\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint res;\n\tunsigned int cflags;\n\tu64 extra1;\n\tu64 extra2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqe_overflow {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong: 32;\n\tlong long unsigned int user_data;\n\ts32 res;\n\tu32 cflags;\n\tvoid *ocqe;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tu8 opcode;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tvoid *link;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint fd;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_local_work_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint count;\n\tunsigned int loops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tint events;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tu8 opcode;\n\tlong: 32;\n\tlong long unsigned int flags;\n\tstruct io_wq_work *work;\n\tbool hashed;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_req_failed {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tu8 flags;\n\tu8 ioprio;\n\tlong: 32;\n\tu64 off;\n\tu64 addr;\n\tu32 len;\n\tu32 op_flags;\n\tu16 buf_index;\n\tu16 personality;\n\tu32 file_index;\n\tu64 pad1;\n\tu64 addr3;\n\tint error;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_short_write {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong: 32;\n\tu64 fpos;\n\tu64 wanted;\n\tu64 got;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_req {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tlong: 32;\n\tlong long unsigned int flags;\n\tbool sq_thread;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_io_uring_task_work_run {\n\tstruct trace_entry ent;\n\tvoid *tctx;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_add_to_ioend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 ino;\n\tu64 pos;\n\tu64 dirty_len;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tint ki_flags;\n\tbool aio;\n\tint error;\n\tssize_t ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_rw_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tsize_t count;\n\tsize_t done_before;\n\tint ki_flags;\n\tunsigned int dio_flags;\n\tbool aio;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_iomap_iter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 ino;\n\tloff_t pos;\n\tu64 length;\n\tint status;\n\tunsigned int flags;\n\tconst void *ops;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 ino;\n\tloff_t size;\n\tloff_t offset;\n\tu64 length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_handler {\n\tstruct trace_entry ent;\n\tconst char *reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_raise {\n\tstruct trace_entry ent;\n\tu32 __data_loc_target_cpus;\n\tconst char *reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpumask {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong: 32;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int chp_time;\n\t__u32 forced_to_close;\n\t__u32 written;\n\t__u32 dropped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_end_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\ttid_t head;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_extend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint buffer_credits;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_start_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint interval;\n\tint sync;\n\tint requested_blocks;\n\tint dirtied_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_journal_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_lock_buffer_stall {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int stall_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_run_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int wait;\n\tlong unsigned int request_delay;\n\tlong unsigned int running;\n\tlong unsigned int locked;\n\tlong unsigned int flushing;\n\tlong unsigned int logging;\n\t__u32 handle_count;\n\t__u32 blocks;\n\t__u32 blocks_logged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_checkpoint_list {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t first_tid;\n\ttid_t tid;\n\ttid_t last_tid;\n\tlong unsigned int nr_freed;\n\ttid_t next_tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_shrunk;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_submit_inode_data {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_update_log_tail {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tail_sequence;\n\ttid_t first_tid;\n\tlong unsigned int block_nr;\n\tlong unsigned int freed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_write_superblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tblk_opf_t write_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tvoid *rx_sk;\n\tshort unsigned int protocol;\n\tenum skb_drop_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmalloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tbool accounted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_op {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_read {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_write {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tlong unsigned int piv;\n\tvoid *val;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tu32 __data_loc_comm;\n\tlong unsigned int total_vm;\n\tlong unsigned int anon_rss;\n\tlong unsigned int file_rss;\n\tlong unsigned int shmem_rss;\n\tuid_t uid;\n\tlong unsigned int pgtables;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mc_event {\n\tstruct trace_entry ent;\n\tunsigned int error_type;\n\tu32 __data_loc_msg;\n\tu32 __data_loc_label;\n\tu16 error_count;\n\tu8 mc_index;\n\ts8 top_layer;\n\ts8 middle_layer;\n\ts8 lower_layer;\n\tlong int address;\n\tu8 grain_bits;\n\tlong int syndrome;\n\tu32 __data_loc_driver_detail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mdio_access {\n\tstruct trace_entry ent;\n\tchar busid[61];\n\tchar read;\n\tu8 addr;\n\tu16 val;\n\tunsigned int regnum;\n\tchar __data[0];\n};\n\nstruct xdp_mem_allocator;\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pte {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_calculate_totalreserve_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int totalreserve_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tunsigned char order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache_range {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int last_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tenum lru_list lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tlong unsigned int thp_succeeded;\n\tlong unsigned int thp_failed;\n\tlong unsigned int thp_split;\n\tlong unsigned int large_folio_split;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages_start {\n\tstruct trace_entry ent;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tint percpu_refill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tlong unsigned int gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_lowmem_reserve {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tu32 __data_loc_upper_name;\n\tlong int lowmem_reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_wmarks {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tlong unsigned int watermark_min;\n\tlong unsigned int watermark_low;\n\tlong unsigned int watermark_high;\n\tlong unsigned int watermark_promo;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tlong unsigned int gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_clear_hopeless {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_reclaim_fail {\n\tstruct trace_entry ent;\n\tint nid;\n\tint failures;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_reclaim_pages {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_throttled {\n\tstruct trace_entry ent;\n\tint nid;\n\tint usec_timeout;\n\tint usec_delayed;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_write_folio {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong: 32;\n\tu64 memcg_id;\n\tbool write;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_mmap_lock_acquire_returned {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong: 32;\n\tu64 memcg_id;\n\tbool write;\n\tbool success;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_mmc_request_done {\n\tstruct trace_entry ent;\n\tu32 cmd_opcode;\n\tint cmd_err;\n\tu32 cmd_resp[4];\n\tunsigned int cmd_retries;\n\tu32 stop_opcode;\n\tint stop_err;\n\tu32 stop_resp[4];\n\tunsigned int stop_retries;\n\tu32 sbc_opcode;\n\tint sbc_err;\n\tu32 sbc_resp[4];\n\tunsigned int sbc_retries;\n\tunsigned int bytes_xfered;\n\tint data_err;\n\tint tag;\n\tunsigned int can_retune;\n\tunsigned int doing_retune;\n\tunsigned int retune_now;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct mmc_request *mrq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmc_request_start {\n\tstruct trace_entry ent;\n\tu32 cmd_opcode;\n\tu32 cmd_arg;\n\tunsigned int cmd_flags;\n\tunsigned int cmd_retries;\n\tu32 stop_opcode;\n\tu32 stop_arg;\n\tunsigned int stop_flags;\n\tunsigned int stop_retries;\n\tu32 sbc_opcode;\n\tu32 sbc_arg;\n\tunsigned int sbc_flags;\n\tunsigned int sbc_retries;\n\tunsigned int blocks;\n\tunsigned int blk_addr;\n\tunsigned int blksz;\n\tunsigned int data_flags;\n\tint tag;\n\tunsigned int can_retune;\n\tunsigned int doing_retune;\n\tunsigned int retune_now;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct mmc_request *mrq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tlong: 32;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tlong: 32;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tlong: 32;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netlink_extack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cached_open {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_cb_error_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 cbident;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_offload {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tloff_t cb_count;\n\tint cb_how;\n\tint cb_stateid_seq;\n\tu32 cb_stateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_cb_seqid_err {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clientid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clone {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 src_fhandle;\n\tu32 src_fileid;\n\tu32 dst_fhandle;\n\tu32 dst_fileid;\n\tdev_t src_dev;\n\tdev_t dst_dev;\n\tlong: 32;\n\tloff_t src_offset;\n\tloff_t dst_offset;\n\tint src_stateid_seq;\n\tu32 src_stateid_hash;\n\tint dst_stateid_seq;\n\tu32 dst_stateid_hash;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_close {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_commit_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tlong: 32;\n\tloff_t offset;\n\tu32 count;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_copy {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 src_fhandle;\n\tu32 src_fileid;\n\tu32 dst_fhandle;\n\tu32 dst_fileid;\n\tdev_t src_dev;\n\tdev_t dst_dev;\n\tint src_stateid_seq;\n\tu32 src_stateid_hash;\n\tint dst_stateid_seq;\n\tu32 dst_stateid_hash;\n\tlong: 32;\n\tloff_t src_offset;\n\tloff_t dst_offset;\n\tbool sync;\n\tlong: 32;\n\tloff_t len;\n\tint res_stateid_seq;\n\tu32 res_stateid_hash;\n\tloff_t res_count;\n\tbool res_sync;\n\tbool res_cons;\n\tbool intra;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_copy_notify {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tu32 fileid;\n\tdev_t dev;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint res_stateid_seq;\n\tu32 res_stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegation_event {\n\tstruct trace_entry ent;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegreturn_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_status {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint status;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_flexfiles_io_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_getattr_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int valid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_idmap_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 id;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong: 32;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong: 32;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_layoutget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 iomode;\n\tlong: 32;\n\tu64 offset;\n\tu64 count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_llseek {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tu32 fileid;\n\tdev_t dev;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tloff_t offset_s;\n\tu32 what;\n\tlong: 32;\n\tloff_t offset_r;\n\tu32 eof;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_lock_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tlong: 32;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookup_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_lookupp {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 ino;\n\tlong unsigned int error;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_match_stateid_event {\n\tstruct trace_entry ent;\n\tint s1_seq;\n\tint s2_seq;\n\tu32 s1_hash;\n\tu32 s2_hash;\n\tint s1_type;\n\tint s2_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_offload_class {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_open_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong: 32;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint openstateid_seq;\n\tu32 openstateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_read_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 olddir;\n\tu32 __data_loc_oldname;\n\tlong: 32;\n\tu64 newdir;\n\tu32 __data_loc_newname;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_sequence_done {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int target_highest_slotid;\n\tlong unsigned int status_flags;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_delegation_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_set_lock {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tlong: 32;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint lockstateid_seq;\n\tu32 lockstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_setup_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_used_slotid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_sparse_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong: 32;\n\tloff_t offset;\n\tloff_t len;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_lock_reclaim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int state_flags;\n\tlong unsigned int lock_flags;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr_failed {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tu32 __data_loc_section;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_test_stateid_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong: 32;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_trunked_exchange_id {\n\tstruct trace_entry ent;\n\tu32 __data_loc_main_addr;\n\tu32 __data_loc_trunk_addr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_write_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_xattr_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong: 32;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs4_xdr_bad_operation {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tu32 expected;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_access_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tunsigned int mask;\n\tunsigned int permitted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_aop_readahead_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tlong: 32;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_atomic_open_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tlong: 32;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_atomic_open_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_commit_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_create_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tlong: 32;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_direct_req_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 fileid;\n\tu32 fhandle;\n\tlong: 32;\n\tloff_t offset;\n\tssize_t count;\n\tssize_t error;\n\tint flags;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_directory_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_directory_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_fh_to_dentry {\n\tstruct trace_entry ent;\n\tint error;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong: 32;\n\tu64 fileid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_folio_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tlong: 32;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_initiate_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_initiate_read {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_initiate_write {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tlong unsigned int stable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_inode_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_range_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t range_start;\n\tloff_t range_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_kiocb_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_link_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_local_open_fh {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_lookup_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tlong: 32;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_mount_assign {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tu32 __data_loc_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_option {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_path {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tconst struct nfs_page *req;\n\tlong: 32;\n\tloff_t offset;\n\tunsigned int count;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tunsigned int count;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_pgio_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tloff_t pos;\n\tint error;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_readdir_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tchar verifier[8];\n\tu64 cookie;\n\tlong unsigned int index;\n\tunsigned int dtsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_short {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 old_dir;\n\tu64 new_dir;\n\tu32 __data_loc_old_name;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 old_dir;\n\tu32 __data_loc_old_name;\n\tlong: 32;\n\tu64 new_dir;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_sillyrename_unlink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_nfs_update_size_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t cur_size;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_writeback_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tlong unsigned int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nlmclnt_lock_event {\n\tstruct trace_entry ent;\n\tu32 oh;\n\tu32 svid;\n\tu32 fh;\n\tlong unsigned int status;\n\tu64 start;\n\tu64 len;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_non_standard_event {\n\tstruct trace_entry ent;\n\tchar sec_type[16];\n\tchar fru_id[16];\n\tu32 __data_loc_fru_text;\n\tu8 sev;\n\tu32 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_notifier_info {\n\tstruct trace_entry ent;\n\tvoid *cb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_optee_invoke_fn_begin {\n\tstruct trace_entry ent;\n\tvoid *param;\n\tu32 args[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_optee_invoke_fn_end {\n\tstruct trace_entry ent;\n\tvoid *param;\n\tlong unsigned int rets[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_op {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n\tlong unsigned int req_count;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_page_cache_ra_order {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_unbounded {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int nr_to_read;\n\tlong unsigned int lookahead_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\ts32 inflight;\n\tu32 hold;\n\tu32 release;\n\tu64 cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_hold {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 hold;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 release;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_update_nid {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tint pool_nid;\n\tint new_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pci_hp_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tu32 __data_loc_slot;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pcie_link_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tunsigned int type;\n\tunsigned int reason;\n\tunsigned int cur_bus_speed;\n\tunsigned int max_bus_speed;\n\tunsigned int width;\n\tunsigned int flit_mode;\n\tunsigned int link_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pmap_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_err_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tlong unsigned int status;\n\tu32 __data_loc_device;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_pnfs_ds_connect {\n\tstruct trace_entry ent;\n\tu32 __data_loc_ds_ips;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_layout_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 fileid;\n\tu32 fhandle;\n\tlong: 32;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_update_layout {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong: 32;\n\tu64 fileid;\n\tu32 fhandle;\n\tlong: 32;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tenum pnfs_update_layout_reason reason;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_power_domain {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong: 32;\n\tu64 state;\n\tu64 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_psci_domain_idle {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool s2idle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_purge_vmap_area_lazy {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int npurged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tint err;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_pwm_read_waveform {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tvoid *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_round_waveform_fromhw {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tconst void *wfhw;\n\tlong: 32;\n\tu64 wf_period_length_ns;\n\tu64 wf_duty_length_ns;\n\tu64 wf_duty_offset_ns;\n\tint err;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_pwm_round_waveform_tohw {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tu64 wf_period_length_ns;\n\tu64 wf_duty_length_ns;\n\tu64 wf_duty_offset_ns;\n\tvoid *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_write_waveform {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tconst void *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_enqueue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kvfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_segcb_stats {\n\tstruct trace_entry ent;\n\tconst char *ctx;\n\tlong unsigned int gp_seq[4];\n\tlong int seglen[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_sr_normal {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tconst char *srevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_stall_warning {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_watching {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint counter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_drop_region {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int from;\n\tunsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_sync {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_status;\n\tu32 __data_loc_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_register_access {\n\tstruct trace_entry ent;\n\tstruct device *dev;\n\tunsigned int offset;\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_register_class {\n\tstruct trace_entry ent;\n\tu32 version;\n\tlong unsigned int family;\n\tshort unsigned int protocol;\n\tshort unsigned int port;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_async {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_block {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bool {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bulk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tu32 __data_loc_buf;\n\tint val_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_reg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_basic {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_range {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint min;\n\tint max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_value {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_buf_alloc {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tsize_t callsize;\n\tsize_t recvsize;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_call_rpcerror {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint tk_status;\n\tint rpc_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_class {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_clone_err {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tlong unsigned int xprtsec;\n\tlong unsigned int flags;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new_err {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_failure {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_reply_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 __data_loc_progname;\n\tu32 version;\n\tu32 __data_loc_procname;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_request {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tbool async;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_socket_nospace {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int total;\n\tunsigned int remaining;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_stats_latency {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tlong unsigned int backlog;\n\tlong unsigned int rtt;\n\tlong unsigned int execute;\n\tu32 xprt_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_queued {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tlong unsigned int timeout;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tu32 __data_loc_q_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_running {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *action;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_tls_class {\n\tstruct trace_entry ent;\n\tlong unsigned int requested_policy;\n\tu32 version;\n\tu32 __data_loc_servername;\n\tu32 __data_loc_progname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_alignment {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t offset;\n\tunsigned int copied;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_overflow {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t requested;\n\tconst void *end;\n\tconst void *p;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_lifetime_class {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_getport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int bind_version;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_setport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tshort unsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_unregister {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_bad_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 expected;\n\tu32 received;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_context {\n\tstruct trace_entry ent;\n\tlong unsigned int expiry;\n\tlong unsigned int now;\n\tunsigned int timeout;\n\tu32 window_size;\n\tint len;\n\tu32 __data_loc_acceptor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_createauth {\n\tstruct trace_entry ent;\n\tunsigned int flavor;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_ctx_class {\n\tstruct trace_entry ent;\n\tconst void *cred;\n\tlong unsigned int service;\n\tu32 __data_loc_principal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_gssapi_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 maj_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_import_ctx {\n\tstruct trace_entry ent;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_need_reencode {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seq_xmit;\n\tu32 seqno;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_oid_to_mech {\n\tstruct trace_entry ent;\n\tu32 __data_loc_oid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_accept_upcall {\n\tstruct trace_entry ent;\n\tu32 minor_status;\n\tlong unsigned int major_status;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 seqno;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_gssapi_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 maj_stat;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_bad {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_low {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_unwrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_wrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_unwrap_failed {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_result {\n\tstruct trace_entry ent;\n\tu32 uid;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_update_slack {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tconst void *auth;\n\tunsigned int rslack;\n\tunsigned int ralign;\n\tunsigned int verfsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_internal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flags;\n\tint usage_count;\n\tint disable_depth;\n\tint runtime_auto;\n\tint request_pending;\n\tint irq_safe;\n\tint child_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_return_int {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int ip;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\ts32 node_id;\n\ts32 mm_cid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_alarm_irq_enable {\n\tstruct trace_entry ent;\n\tunsigned int enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_freq {\n\tstruct trace_entry ent;\n\tint freq;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_state {\n\tstruct trace_entry ent;\n\tint enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_offset_class {\n\tstruct trace_entry ent;\n\tlong int offset;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_time_alarm_class {\n\tstruct trace_entry ent;\n\ttime64_t secs;\n\tint err;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_rtc_timer_class {\n\tstruct trace_entry ent;\n\tstruct rtc_timer *timer;\n\tlong: 32;\n\tktime_t expires;\n\tktime_t period;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_bypass_lb {\n\tstruct trace_entry ent;\n\t__u32 node;\n\t__u32 nr_cpus;\n\t__u32 nr_tasks;\n\t__u32 nr_balanced;\n\t__u32 before_min;\n\t__u32 before_max;\n\t__u32 after_min;\n\t__u32 after_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_dump {\n\tstruct trace_entry ent;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong: 32;\n\t__s64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *worker;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_prepare_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_interp;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exit {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tbool group_dead;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tu32 __data_loc_parent_comm;\n\tpid_t parent_pid;\n\tu32 __data_loc_child_comm;\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 runtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_fc_call {\n\tstruct trace_entry ent;\n\tu8 protocol_id;\n\tu8 msg_id;\n\tu32 res_id;\n\tu32 val1;\n\tu32 val2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_msg_dump {\n\tstruct trace_entry ent;\n\tint id;\n\tu8 channel_id;\n\tu8 protocol_id;\n\tu8 msg_id;\n\tchar tag[6];\n\tu16 seq;\n\tint status;\n\tsize_t len;\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_rx_done {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tu8 msg_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_xfer_begin {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tbool poll;\n\tint inflight;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_xfer_end {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tint status;\n\tint inflight;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_xfer_response_wait {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tu32 timeout;\n\tbool poll;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sk_data_ready {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 family;\n\t__u16 protocol;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 flags;\n\t__u16 addr;\n\t__u8 command;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 read_write;\n\t__u8 command;\n\t__s16 res;\n\t__u32 protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_negotiate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 out_features;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_notify_in {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_client_name;\n\tlong unsigned int status;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_ssr_ack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_update_bits {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_client_name;\n\tu32 orig;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int sysctl_mem[3];\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_msg_length {\n\tstruct trace_entry ent;\n\tvoid *sk;\n\t__u16 family;\n\t__u16 protocol;\n\tint ret;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_controller {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_mem_start_op {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_op;\n\tu32 __data_loc_data;\n\tu32 data_len;\n\tu32 max_freq;\n\tu8 cmd_buswidth;\n\tbool cmd_dtr;\n\tu8 addr_buswidth;\n\tbool addr_dtr;\n\tu8 dummy_nbytes;\n\tu8 data_buswidth;\n\tbool data_dtr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_mem_stop_op {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_data;\n\tu32 data_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_message {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_message *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_message_done {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_message *msg;\n\tunsigned int frame;\n\tunsigned int actual;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_set_cs {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tlong unsigned int mode;\n\tbool enable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_setup {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tlong unsigned int mode;\n\tunsigned int bits_per_word;\n\tunsigned int max_speed_hz;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_transfer {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_transfer *xfer;\n\tint len;\n\tu32 __data_loc_rx_buf;\n\tu32 __data_loc_tx_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_cmd {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_read_begin {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_read_end {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tint ret;\n\tu8 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_write_begin {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tu8 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_write_end {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_alloc_arg_err {\n\tstruct trace_entry ent;\n\tunsigned int requested;\n\tunsigned int allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int svc_status;\n\tlong unsigned int auth_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_deferred_event {\n\tstruct trace_entry ent;\n\tconst void *dr;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_pool_thread_event {\n\tstruct trace_entry ent;\n\tunsigned int pool_id;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_process {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 vers;\n\tu32 proc;\n\tu32 __data_loc_service;\n\tu32 __data_loc_procedure;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_replace_page_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tconst void *begin;\n\tconst void *respages;\n\tconst void *nextpage;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tint status;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_stats_latency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int execute;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_unregister {\n\tstruct trace_entry ent;\n\tu32 version;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_msg_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_accept {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_service;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_create_err {\n\tstruct trace_entry ent;\n\tlong int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_dequeue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tlong unsigned int wakeup;\n\tlong unsigned int qtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_enqueue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_accept_class {\n\tstruct trace_entry ent;\n\tlong int status;\n\tu32 __data_loc_service;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_class {\n\tstruct trace_entry ent;\n\tssize_t result;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_lifetime_class {\n\tstruct trace_entry ent;\n\tunsigned int netns_ino;\n\tconst void *svsk;\n\tconst void *sk;\n\tlong unsigned int type;\n\tlong unsigned int family;\n\tlong unsigned int state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_marker {\n\tstruct trace_entry ent;\n\tunsigned int length;\n\tbool last;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_recv_short {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_state {\n\tstruct trace_entry ent;\n\tlong unsigned int socket_state;\n\tlong unsigned int sock_state;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tlong: 32;\n\tu64 clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_task_prctl_unknown {\n\tstruct trace_entry ent;\n\tint option;\n\tlong unsigned int arg2;\n\tlong unsigned int arg3;\n\tlong unsigned int arg4;\n\tlong unsigned int arg5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tasklet {\n\tstruct trace_entry ent;\n\tvoid *tasklet;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_ao_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\t__u8 keyid;\n\t__u8 rnext;\n\t__u8 maclen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_cong_state_set {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u8 cong_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tlong: 32;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_hash_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\tlong: 32;\n\t__u64 sock_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_ssthresh;\n\t__u32 window_clamp;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\tlong: 32;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_send_reset {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\tenum sk_rst_reason reason;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_sendmsg_locked {\n\tstruct trace_entry ent;\n\tconst void *skb_addr;\n\tint skb_len;\n\tint msg_left;\n\tint size_goal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tegra_dma_complete_cb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_chan;\n\tint count;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tegra_dma_isr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_chan;\n\tint irq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tegra_dma_tx_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_chan;\n\tdma_cookie_t cookie;\n\t__u32 residue;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_test_pages_isolated {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int fin_pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_cpu_get_power_simple {\n\tstruct trace_entry ent;\n\tint cpu;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_cpu_limit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tunsigned int freq;\n\tlong unsigned int cdev_state;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_devfreq_get_power {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int freq;\n\tu32 busy_time;\n\tu32 total_time;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_devfreq_limit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tunsigned int freq;\n\tlong unsigned int cdev_state;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_temperature {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint temp_prev;\n\tint temp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_zone_trip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint trip;\n\tenum thermal_trip_type trip_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_base_idle {\n\tstruct trace_entry ent;\n\tbool is_idle;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int bucket_expiry;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tls_contenttype {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_child_parent {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_cpu_parent {\n\tstruct trace_entry ent;\n\tvoid *parent;\n\tunsigned int cpu;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_cpugroup {\n\tstruct trace_entry ent;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_and_cpu {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tu32 childmask;\n\tu8 active;\n\tu8 migrator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_set {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_handle_remote {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_idle {\n\tstruct trace_entry ent;\n\tu64 nextevt;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_update_events {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *group;\n\tu64 nextevt;\n\tu64 group_next_expiry;\n\tu64 child_evt_expiry;\n\tunsigned int group_lvl;\n\tunsigned int child_evtcpu;\n\tu8 child_active;\n\tu8 group_active;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_udc_log_ep {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int maxpacket;\n\tunsigned int maxpacket_limit;\n\tunsigned int max_streams;\n\tunsigned int mult;\n\tunsigned int maxburst;\n\tu8 address;\n\tbool claimed;\n\tbool enabled;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udc_log_gadget {\n\tstruct trace_entry ent;\n\tenum usb_device_speed speed;\n\tenum usb_device_speed max_speed;\n\tenum usb_device_state state;\n\tunsigned int mA;\n\tunsigned int sg_supported;\n\tunsigned int is_otg;\n\tunsigned int is_a_peripheral;\n\tunsigned int b_hnp_enable;\n\tunsigned int a_hnp_support;\n\tunsigned int hnp_polling_support;\n\tunsigned int host_request_flag;\n\tunsigned int quirk_ep_out_aligned_size;\n\tunsigned int quirk_altset_not_supp;\n\tunsigned int quirk_stall_not_supp;\n\tunsigned int quirk_zlp_not_supp;\n\tunsigned int is_selfpowered;\n\tunsigned int deactivated;\n\tunsigned int connected;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udc_log_req {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int length;\n\tunsigned int actual;\n\tunsigned int num_sgs;\n\tunsigned int num_mapped_sgs;\n\tunsigned int stream_id;\n\tunsigned int no_interrupt;\n\tunsigned int zero;\n\tunsigned int short_not_ok;\n\tint status;\n\tint ret;\n\tstruct usb_request *req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_usb_core_log_usb_device {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum usb_device_speed speed;\n\tenum usb_device_state state;\n\tshort unsigned int bus_mA;\n\tunsigned int authorized;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong: 32;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_set_timeout {\n\tstruct trace_entry ent;\n\tint id;\n\tunsigned int timeout;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_template {\n\tstruct trace_entry ent;\n\tint id;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tu32 __data_loc_workqueue;\n\tint req_cpu;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_folio_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tunsigned int xdp_pass;\n\tunsigned int xdp_drop;\n\tunsigned int xdp_redirect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_dbc_log_request {\n\tstruct trace_entry ent;\n\tstruct dbc_request *req;\n\tbool dir;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctrl_ctx {\n\tstruct trace_entry ent;\n\tu32 drop;\n\tu32 add;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctx {\n\tstruct trace_entry ent;\n\tint ctx_64;\n\tunsigned int ctx_type;\n\tdma_addr_t ctx_dma;\n\tu8 *ctx_va;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_doorbell {\n\tstruct trace_entry ent;\n\tu32 slot;\n\tu32 doorbell;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ep_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu64 deq;\n\tu32 tx_info;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_xhci_log_free_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong: 32;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint slot_id;\n\tu16 current_mel;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_portsc {\n\tstruct trace_entry ent;\n\tu32 busnum;\n\tu32 portnum;\n\tu32 portsc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ring {\n\tstruct trace_entry ent;\n\tu32 type;\n\tvoid *ring;\n\tdma_addr_t enq;\n\tdma_addr_t deq;\n\tunsigned int num_segs;\n\tunsigned int stream_id;\n\tunsigned int cycle_state;\n\tunsigned int bounce_buf_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_slot_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu32 tt_info;\n\tu32 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_stream_ctx {\n\tstruct trace_entry ent;\n\tunsigned int stream_id;\n\tlong: 32;\n\tu64 stream_ring;\n\tdma_addr_t ctx_array_dma;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_xhci_log_trb {\n\tstruct trace_entry ent;\n\tdma_addr_t dma;\n\tu32 type;\n\tu32 field0;\n\tu32 field1;\n\tu32 field2;\n\tu32 field3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_urb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tvoid *urb;\n\tunsigned int pipe;\n\tunsigned int stream;\n\tint status;\n\tunsigned int flags;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tint length;\n\tint actual;\n\tint epnum;\n\tint dir_in;\n\tint type;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong: 32;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint devnum;\n\tint state;\n\tint speed;\n\tu8 portnum;\n\tu8 level;\n\tint slot_id;\n\tchar __data[0];\n\tlong: 32;\n};\n\nstruct trace_event_raw_xprt_cong_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tbool wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_ping {\n\tstruct trace_entry ent;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_reserve {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_retransmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint ntrans;\n\tint version;\n\tlong unsigned int timeout;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_transmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_writelock_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_data_ready {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event {\n\tstruct trace_entry ent;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event_done {\n\tstruct trace_entry ent;\n\tint error;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong: 32;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_data {\n\tstruct trace_entry ent;\n\tssize_t err;\n\tsize_t total;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tu32 xid;\n\tlong unsigned int copied;\n\tunsigned int reclen;\n\tunsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n\tint flags;\n};\n\nstruct trace_func_repeats {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int count;\n\tlong: 32;\n\tu64 ts_last_call;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n\tlong: 32;\n};\n\nstruct trace_min_max_param {\n\tstruct mutex *lock;\n\tu64 *val;\n\tu64 *min;\n\tu64 *max;\n};\n\nstruct trace_mod_entry {\n\tlong unsigned int mod_addr;\n\tchar mod_name[60];\n};\n\nstruct trace_module_delta {\n\tstruct callback_head rcu;\n\tlong int delta[0];\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tbool fail;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nunion upper_chunk;\n\nstruct trace_pid_list {\n\tseqcount_raw_spinlock_t seqcount;\n\traw_spinlock_t lock;\n\tstruct irq_work refill_irqwork;\n\tunion upper_chunk *upper[256];\n\tunion upper_chunk *upper_list;\n\tunion lower_chunk *lower_list;\n\tint free_upper_chunks;\n\tint free_lower_chunks;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_print_flags_u64 {\n\tlong long unsigned int mask;\n\tconst char *name;\n\tlong: 32;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nstruct trace_scratch {\n\tunsigned int clock_id;\n\tlong unsigned int text_addr;\n\tlong unsigned int nr_entries;\n\tstruct trace_mod_entry entries[0];\n};\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct eventfs_inode *ei;\n\tint ref_count;\n\tint nr_events;\n};\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tlong: 32;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tchar *filename;\n\tstruct uprobe *uprobe;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int *nhits;\n\tstruct trace_probe tp;\n\tlong: 32;\n};\n\nstruct trace_user_buf {\n\tchar *buf;\n};\n\nstruct trace_user_buf_info {\n\tstruct trace_user_buf *tbuf;\n\tsize_t size;\n\tint ref;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct tracefs_inode {\n\tstruct inode vfs_inode;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tvoid *private;\n};\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct traceprobe_parse_context {\n\tstruct trace_event_call *event;\n\tconst char *funcname;\n\tconst struct btf_type *proto;\n\tconst struct btf_param *params;\n\ts32 nr_params;\n\tstruct btf *btf;\n\tconst struct btf_type *last_type;\n\tu32 last_bitoffs;\n\tu32 last_bitsize;\n\tstruct trace_probe *tp;\n\tunsigned int flags;\n\tint offset;\n};\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u64, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tstruct tracer_flags *default_flags;\n\tint enabled;\n\tbool print_max;\n\tbool allow_instances;\n\tbool noboot;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct tracers {\n\tstruct list_head list;\n\tstruct tracer *tracer;\n\tstruct tracer_flags *flags;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar *cmd;\n\tlong: 32;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tdepot_stack_handle_t handle;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n};\n\nstruct transient_trig_data {\n\tint activate;\n\tint state;\n\tint restore_state;\n\tlong unsigned int duration;\n\tstruct timer_list timer;\n\tstruct led_classdev *led_cdev;\n};\n\ntypedef struct tree_desc_s tree_desc;\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct uniphier_tm_dev;\n\nstruct trip_walk_data {\n\tstruct uniphier_tm_dev *tdev;\n\tint crit_temp;\n\tint index;\n};\n\nstruct trng_regs {\n\tu32 output_l;\n\tu32 output_h;\n\tu32 status;\n\tu32 intmask;\n\tu32 intack;\n\tu32 control;\n\tu32 config;\n};\n\nstruct trusted_foundations_platform_data {\n\tunsigned int version_major;\n\tunsigned int version_minor;\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsadc_table {\n\tu32 code;\n\tint temp;\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsens_context {\n\tint threshold;\n\tint control;\n};\n\nstruct tsens_features {\n\tunsigned int ver_major;\n\tunsigned int crit_int: 1;\n\tunsigned int combo_int: 1;\n\tunsigned int adc: 1;\n\tunsigned int srot_split: 1;\n\tunsigned int has_watchdog: 1;\n\tunsigned int max_sensors;\n\tint trip_min_temp;\n\tint trip_max_temp;\n};\n\nstruct tsens_irq_data {\n\tu32 up_viol;\n\tint up_thresh;\n\tu32 up_irq_mask;\n\tu32 up_irq_clear;\n\tu32 low_viol;\n\tint low_thresh;\n\tu32 low_irq_mask;\n\tu32 low_irq_clear;\n\tu32 crit_viol;\n\tu32 crit_thresh;\n\tu32 crit_irq_mask;\n\tu32 crit_irq_clear;\n};\n\nstruct tsens_single_value {\n\tu8 idx;\n\tu8 shift;\n\tu8 blob;\n};\n\nstruct tsens_legacy_calibration_format {\n\tunsigned int base_len;\n\tunsigned int base_shift;\n\tunsigned int sp_len;\n\tstruct tsens_single_value mode;\n\tstruct tsens_single_value invalid;\n\tstruct tsens_single_value base[2];\n\tstruct tsens_single_value sp[0];\n};\n\nstruct tsens_priv;\n\nstruct tsens_sensor;\n\nstruct tsens_ops {\n\tint (*init)(struct tsens_priv *);\n\tint (*calibrate)(struct tsens_priv *);\n\tint (*get_temp)(const struct tsens_sensor *, int *);\n\tint (*enable)(struct tsens_priv *, int);\n\tvoid (*disable)(struct tsens_priv *);\n\tint (*suspend)(struct tsens_priv *);\n\tint (*resume)(struct tsens_priv *);\n};\n\nstruct tsens_plat_data {\n\tconst u32 num_sensors;\n\tconst struct tsens_ops *ops;\n\tunsigned int *hw_ids;\n\tstruct tsens_features *feat;\n\tconst struct reg_field *fields;\n};\n\nstruct tsens_sensor {\n\tstruct tsens_priv *priv;\n\tstruct thermal_zone_device *tzd;\n\tint offset;\n\tunsigned int hw_id;\n\tint slope;\n\tu32 status;\n\tint p1_calib_offset;\n\tint p2_calib_offset;\n};\n\nstruct tsens_priv {\n\tstruct device *dev;\n\tu32 num_sensors;\n\tstruct regmap *tm_map;\n\tstruct regmap *srot_map;\n\tu32 tm_offset;\n\tspinlock_t ul_lock;\n\tstruct regmap_field *rf[321];\n\tstruct tsens_context ctx;\n\tstruct tsens_features *feat;\n\tconst struct reg_field *fields;\n\tconst struct tsens_ops *ops;\n\tstruct dentry *debug_root;\n\tstruct dentry *debug;\n\tstruct tsens_sensor sensor[0];\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tlong: 32;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct ttc_timer {\n\tvoid *base_addr;\n\tlong unsigned int freq;\n\tstruct clk *clk;\n\tstruct notifier_block clk_rate_change_nb;\n};\n\nstruct ttc_timer_clockevent {\n\tstruct ttc_timer ttc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct clock_event_device ce;\n};\n\nstruct ttc_timer_clocksource {\n\tu32 scale_clk_ctrl_reg_old;\n\tu32 scale_clk_ctrl_reg_new;\n\tstruct ttc_timer ttc;\n\tstruct clocksource cs;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct twl4030_gpio_platform_data {\n\tbool use_leds;\n\tu8 mmc_cd;\n\tu32 debounce;\n\tu32 pullups;\n\tu32 pulldowns;\n};\n\nstruct twl4030_ins {\n\tu16 pmb_message;\n\tu8 delay;\n};\n\nstruct twl4030_script;\n\nstruct twl4030_resconfig;\n\nstruct twl4030_power_data {\n\tstruct twl4030_script **scripts;\n\tunsigned int num;\n\tstruct twl4030_resconfig *resource_config;\n\tstruct twl4030_resconfig *board_config;\n\tbool use_poweroff;\n\tbool ac_charger_quirk;\n};\n\nstruct twl4030_resconfig {\n\tu8 resource;\n\tu8 devgroup;\n\tu8 type;\n\tu8 type2;\n\tu8 remap_off;\n\tu8 remap_sleep;\n};\n\nstruct twl4030_script {\n\tstruct twl4030_ins *script;\n\tunsigned int size;\n\tu8 flags;\n};\n\nstruct twl6030_irq {\n\tunsigned int irq_base;\n\tint twl_irq;\n\tbool irq_wake_enabled;\n\tatomic_t wakeirqs;\n\tstruct notifier_block pm_nb;\n\tstruct irq_chip irq_chip;\n\tstruct irq_domain *irq_domain;\n\tconst int *irq_mapping_tbl;\n};\n\nstruct twl_client {\n\tstruct i2c_client *client;\n\tstruct regmap *regmap;\n};\n\nstruct twl_mapping {\n\tunsigned char sid;\n\tunsigned char base;\n};\n\nstruct twl_private {\n\tbool ready;\n\tu32 twl_idcode;\n\tunsigned int twl_id;\n\tstruct twl_mapping *twl_map;\n\tstruct twl_client *twl_modules;\n};\n\nstruct twl_rtc {\n\tstruct device *dev;\n\tstruct rtc_device *rtc;\n\tu8 *reg_map;\n\tunsigned char rtc_irq_bits;\n\tbool wake_enabled;\n\tunsigned char irqstat;\n\tenum twl_class class;\n};\n\nstruct twlreg_info {\n\tu8 base;\n\tu8 id;\n\tu8 flags;\n\tstruct regulator_desc desc;\n\tlong unsigned int features;\n\tvoid *data;\n};\n\nstruct twlreg_info___2 {\n\tu8 base;\n\tu8 id;\n\tu8 table_len;\n\tconst u16 *table;\n\tu8 remap;\n\tstruct regulator_desc desc;\n\tlong unsigned int features;\n\tvoid *data;\n};\n\nstruct tx_desc {\n\tu32 cmd_sts;\n\tu16 l4i_chk;\n\tu16 byte_cnt;\n\tu32 buf_ptr;\n\tu32 next_desc_ptr;\n};\n\nstruct txbd8 {\n\tunion {\n\t\tstruct {\n\t\t\t__be16 status;\n\t\t\t__be16 length;\n\t\t};\n\t\t__be32 lstatus;\n\t};\n\t__be32 bufPtr;\n};\n\nstruct txfcb {\n\tu8 flags;\n\tu8 ptp;\n\tu8 l4os;\n\tu8 l3os;\n\t__be16 phcs;\n\t__be16 vlctl;\n};\n\nstruct typec_connector {\n\tvoid (*attach)(struct typec_connector *, struct device *);\n\tvoid (*deattach)(struct typec_connector *, struct device *);\n};\n\nstruct u32_fract {\n\t__u32 numerator;\n\t__u32 denominator;\n};\n\nstruct u8500_prcc_reset {\n\tstruct reset_controller_dev rcdev;\n\tu32 phy_base[5];\n\tvoid *base[5];\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n\tlong: 32;\n};\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n\tvoid (*setup_timer)(struct uart_8250_port *);\n};\n\ntypedef struct uart_8250_port *class_serial8250_rpm_t;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tu16 bugs;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tu16 lsr_saved_flags;\n\tu16 lsr_save_mask;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *, bool);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *, bool);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct vendor_data___2;\n\nstruct uart_amba_port {\n\tstruct uart_port port;\n\tconst u16 *reg_offset;\n\tstruct clk *clk;\n\tconst struct vendor_data___2 *vendor;\n\tunsigned int im;\n\tunsigned int old_status;\n\tunsigned int fifosize;\n\tunsigned int fixed_baud;\n\tchar type[12];\n\tktime_t rs485_tx_drain_interval;\n\tenum pl011_rs485_tx_state rs485_tx_state;\n\tlong: 32;\n\tstruct hrtimer trigger_start_tx;\n\tstruct hrtimer trigger_stop_tx;\n\tbool console_line_ended;\n\tunsigned int dmacr;\n\tbool using_tx_dma;\n\tbool using_rx_dma;\n\tstruct pl011_dmarx_data dmarx;\n\tstruct pl011_dmatx_data dmatx;\n\tbool dma_probed;\n\tlong: 32;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*start_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\ntypedef struct uart_port *class_uart_port_lock_irq_t;\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct ubi_ainf_peb {\n\tint ec;\n\tint pnum;\n\tint vol_id;\n\tint lnum;\n\tunsigned int scrub: 1;\n\tunsigned int copy_flag: 1;\n\tlong: 32;\n\tlong long unsigned int sqnum;\n\tunion {\n\t\tstruct rb_node rb;\n\t\tstruct list_head list;\n\t} u;\n\tlong: 32;\n};\n\nstruct ubi_ainf_volume {\n\tint vol_id;\n\tint highest_lnum;\n\tint leb_count;\n\tint vol_type;\n\tint used_ebs;\n\tint last_data_size;\n\tint data_pad;\n\tint compat;\n\tstruct rb_node rb;\n\tstruct rb_root root;\n};\n\nstruct ubi_ec_hdr;\n\nstruct ubi_vid_io_buf;\n\nstruct ubi_attach_info {\n\tstruct rb_root volumes;\n\tstruct list_head corr;\n\tstruct list_head free;\n\tstruct list_head erase;\n\tstruct list_head alien;\n\tstruct list_head fastmap;\n\tint corr_peb_count;\n\tint empty_peb_count;\n\tint alien_peb_count;\n\tint bad_peb_count;\n\tint maybe_bad_peb_count;\n\tint vols_found;\n\tint highest_vol_id;\n\tint is_empty;\n\tint force_full_scan;\n\tint min_ec;\n\tint max_ec;\n\tlong long unsigned int max_sqnum;\n\tint mean_ec;\n\tlong: 32;\n\tuint64_t ec_sum;\n\tint ec_count;\n\tstruct kmem_cache *aeb_slab_cache;\n\tstruct ubi_ec_hdr *ech;\n\tstruct ubi_vid_io_buf *vidb;\n};\n\nstruct ubi_attach_req {\n\t__s32 ubi_num;\n\t__s32 mtd_num;\n\t__s32 vid_hdr_offset;\n\t__s16 max_beb_per1024;\n\t__s8 disable_fm;\n\t__s8 need_resv_pool;\n\t__s8 padding[8];\n};\n\nstruct ubi_debug_info {\n\tunsigned int chk_gen: 1;\n\tunsigned int chk_io: 1;\n\tunsigned int chk_fastmap: 1;\n\tunsigned int disable_bgt: 1;\n\tunsigned int emulate_bitflips: 1;\n\tunsigned int emulate_io_failures: 1;\n\tunsigned int emulate_power_cut: 2;\n\tunsigned int power_cut_counter;\n\tunsigned int power_cut_min;\n\tunsigned int power_cut_max;\n\tunsigned int emulate_failures;\n\tchar dfs_dir_name[6];\n\tstruct dentry *dfs_dir;\n\tstruct dentry *dfs_chk_gen;\n\tstruct dentry *dfs_chk_io;\n\tstruct dentry *dfs_chk_fastmap;\n\tstruct dentry *dfs_disable_bgt;\n\tstruct dentry *dfs_emulate_bitflips;\n\tstruct dentry *dfs_emulate_io_failures;\n\tstruct dentry *dfs_emulate_power_cut;\n\tstruct dentry *dfs_power_cut_min;\n\tstruct dentry *dfs_power_cut_max;\n\tstruct dentry *dfs_emulate_failures;\n};\n\nstruct ubi_fm_pool {\n\tint pebs[256];\n\tint used;\n\tint size;\n\tint max_size;\n};\n\nstruct ubi_volume;\n\nstruct ubi_vtbl_record;\n\nstruct ubi_fastmap_layout;\n\nstruct ubi_wl_entry;\n\nstruct ubi_device {\n\tstruct cdev cdev;\n\tlong: 32;\n\tstruct device dev;\n\tint ubi_num;\n\tchar ubi_name[9];\n\tint vol_count;\n\tstruct ubi_volume *volumes[129];\n\tspinlock_t volumes_lock;\n\tint ref_count;\n\tint image_seq;\n\tbool is_dead;\n\tint rsvd_pebs;\n\tint avail_pebs;\n\tint beb_rsvd_pebs;\n\tint beb_rsvd_level;\n\tint bad_peb_limit;\n\tint autoresize_vol_id;\n\tint vtbl_slots;\n\tint vtbl_size;\n\tstruct ubi_vtbl_record *vtbl;\n\tstruct mutex device_mutex;\n\tint max_ec;\n\tint mean_ec;\n\tlong long unsigned int global_sqnum;\n\tspinlock_t ltree_lock;\n\tstruct rb_root ltree;\n\tstruct mutex alc_mutex;\n\tint fm_disabled;\n\tstruct ubi_fastmap_layout *fm;\n\tstruct ubi_fm_pool fm_pool;\n\tstruct ubi_fm_pool fm_wl_pool;\n\tstruct rw_semaphore fm_eba_sem;\n\tstruct rw_semaphore fm_protect;\n\tvoid *fm_buf;\n\tsize_t fm_size;\n\tstruct work_struct fm_work;\n\tint fm_work_scheduled;\n\tint fast_attach;\n\tstruct ubi_wl_entry *fm_anchor;\n\tint fm_do_produce_anchor;\n\tint fm_pool_rsv_cnt;\n\tstruct rb_root used;\n\tstruct rb_root erroneous;\n\tstruct rb_root free;\n\tint free_count;\n\tstruct rb_root scrub;\n\tstruct list_head pq[10];\n\tint pq_head;\n\tspinlock_t wl_lock;\n\tstruct mutex move_mutex;\n\tstruct rw_semaphore work_sem;\n\tint wl_scheduled;\n\tstruct ubi_wl_entry **lookuptbl;\n\tstruct ubi_wl_entry *move_from;\n\tstruct ubi_wl_entry *move_to;\n\tint move_to_put;\n\tstruct list_head works;\n\tint works_count;\n\tstruct task_struct *bgt_thread;\n\tint thread_enabled;\n\tchar bgt_name[13];\n\tlong long int flash_size;\n\tint peb_count;\n\tint peb_size;\n\tint bad_peb_count;\n\tint good_peb_count;\n\tint corr_peb_count;\n\tint erroneous_peb_count;\n\tint max_erroneous;\n\tint min_io_size;\n\tint hdrs_min_io_size;\n\tint ro_mode;\n\tint leb_size;\n\tint leb_start;\n\tint ec_hdr_alsize;\n\tint vid_hdr_alsize;\n\tint vid_hdr_offset;\n\tint vid_hdr_aloffset;\n\tint vid_hdr_shift;\n\tunsigned int bad_allowed: 1;\n\tunsigned int nor_flash: 1;\n\tint max_write_size;\n\tstruct mtd_info *mtd;\n\tvoid *peb_buf;\n\tstruct mutex buf_mutex;\n\tstruct mutex ckvol_mutex;\n\tstruct ubi_debug_info dbg;\n\tlong: 32;\n};\n\nstruct ubi_device_info {\n\tint ubi_num;\n\tint leb_size;\n\tint leb_start;\n\tint min_io_size;\n\tint max_write_size;\n\tint ro_mode;\n\tdev_t cdev;\n};\n\nstruct ubi_eba_entry {\n\tint pnum;\n};\n\nstruct ubi_eba_leb_desc {\n\tint lnum;\n\tint pnum;\n};\n\nstruct ubi_eba_table {\n\tstruct ubi_eba_entry *entries;\n};\n\nstruct ubi_ec_hdr {\n\t__be32 magic;\n\t__u8 version;\n\t__u8 padding1[3];\n\t__be64 ec;\n\t__be32 vid_hdr_offset;\n\t__be32 data_offset;\n\t__be32 image_seq;\n\t__u8 padding2[32];\n\t__be32 hdr_crc;\n};\n\nstruct ubi_ecinfo_req {\n\t__s32 start;\n\t__s32 length;\n\t__s32 read_length;\n\t__s8 padding[16];\n\t__s32 erase_counters[0];\n};\n\nstruct ubi_fastmap_layout {\n\tstruct ubi_wl_entry *e[32];\n\tint to_be_tortured[32];\n\tint used_blocks;\n\tint max_pool_size;\n\tint max_wl_pool_size;\n};\n\nstruct ubi_leb_change_req {\n\t__s32 lnum;\n\t__s32 bytes;\n\t__s8 dtype;\n\t__s8 padding[7];\n};\n\nstruct ubi_ltree_entry {\n\tstruct rb_node rb;\n\tint vol_id;\n\tint lnum;\n\tint users;\n\tstruct rw_semaphore mutex;\n};\n\nstruct ubi_map_req {\n\t__s32 lnum;\n\t__s8 dtype;\n\t__s8 padding[3];\n};\n\nstruct ubi_mkvol_req {\n\t__s32 vol_id;\n\t__s32 alignment;\n\t__s64 bytes;\n\t__s8 vol_type;\n\t__u8 flags;\n\t__s16 name_len;\n\t__s8 padding2[4];\n\tchar name[128];\n};\n\nstruct ubi_volume_info {\n\tint ubi_num;\n\tint vol_id;\n\tint size;\n\tlong: 32;\n\tlong long int used_bytes;\n\tint used_ebs;\n\tint vol_type;\n\tint corrupted;\n\tint upd_marker;\n\tint alignment;\n\tint usable_leb_size;\n\tint name_len;\n\tconst char *name;\n\tdev_t cdev;\n\tstruct device *dev;\n};\n\nstruct ubi_notification {\n\tstruct ubi_device_info di;\n\tlong: 32;\n\tstruct ubi_volume_info vi;\n};\n\nstruct ubi_volume_desc;\n\nstruct ubi_rename_entry {\n\tint new_name_len;\n\tchar new_name[128];\n\tint remove;\n\tstruct ubi_volume_desc *desc;\n\tstruct list_head list;\n};\n\nstruct ubi_rnvol_req {\n\t__s32 count;\n\t__s8 padding1[12];\n\tstruct {\n\t\t__s32 vol_id;\n\t\t__s16 name_len;\n\t\t__s8 padding2[2];\n\t\tchar name[128];\n\t} ents[32];\n};\n\nstruct ubi_rsvol_req {\n\t__s64 bytes;\n\t__s32 vol_id;\n};\n\nstruct ubi_set_vol_prop_req {\n\t__u8 property;\n\t__u8 padding[7];\n\t__u64 value;\n};\n\nstruct ubi_sgl {\n\tint list_pos;\n\tint page_pos;\n\tstruct scatterlist sg[64];\n};\n\nstruct ubi_vid_hdr {\n\t__be32 magic;\n\t__u8 version;\n\t__u8 vol_type;\n\t__u8 copy_flag;\n\t__u8 compat;\n\t__be32 vol_id;\n\t__be32 lnum;\n\t__u8 padding1[4];\n\t__be32 data_size;\n\t__be32 used_ebs;\n\t__be32 data_pad;\n\t__be32 data_crc;\n\t__u8 padding2[4];\n\t__be64 sqnum;\n\t__u8 padding3[12];\n\t__be32 hdr_crc;\n};\n\nstruct ubi_vid_io_buf {\n\tstruct ubi_vid_hdr *hdr;\n\tvoid *buffer;\n};\n\nstruct ubi_volume {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct ubi_device *ubi;\n\tint vol_id;\n\tint ref_count;\n\tint readers;\n\tint writers;\n\tint exclusive;\n\tint metaonly;\n\tbool is_dead;\n\tint reserved_pebs;\n\tint vol_type;\n\tint usable_leb_size;\n\tint used_ebs;\n\tint last_eb_bytes;\n\tlong long int used_bytes;\n\tint alignment;\n\tint data_pad;\n\tint name_len;\n\tchar name[128];\n\tint upd_ebs;\n\tint ch_lnum;\n\tlong: 32;\n\tlong long int upd_bytes;\n\tlong long int upd_received;\n\tvoid *upd_buf;\n\tstruct ubi_eba_table *eba_tbl;\n\tunsigned int skip_check: 1;\n\tunsigned int checked: 1;\n\tunsigned int corrupted: 1;\n\tunsigned int upd_marker: 1;\n\tunsigned int updating: 1;\n\tunsigned int changing_leb: 1;\n\tunsigned int direct_writes: 1;\n\tlong: 32;\n};\n\nstruct ubi_volume_desc {\n\tstruct ubi_volume *vol;\n\tint mode;\n};\n\nstruct ubi_vtbl_record {\n\t__be32 reserved_pebs;\n\t__be32 alignment;\n\t__be32 data_pad;\n\t__u8 vol_type;\n\t__u8 upd_marker;\n\t__be16 name_len;\n\t__u8 name[128];\n\t__u8 flags;\n\t__u8 padding[23];\n\t__be32 crc;\n};\n\nstruct ubi_wl_entry {\n\tunion {\n\t\tstruct rb_node rb;\n\t\tstruct list_head list;\n\t} u;\n\tint ec;\n\tint pnum;\n};\n\nstruct ubi_work {\n\tstruct list_head list;\n\tint (*func)(struct ubi_device *, struct ubi_work *, int);\n\tstruct ubi_wl_entry *e;\n\tint vol_id;\n\tint lnum;\n\tint torture;\n};\n\nstruct ubifs_attr {\n\tstruct attribute attr;\n\tenum attr_id_t attr_id;\n};\n\nstruct ubifs_auth_node {\n\tstruct ubifs_ch ch;\n\t__u8 hmac[0];\n};\n\nstruct ubifs_branch {\n\t__le32 lnum;\n\t__le32 offs;\n\t__le32 len;\n\t__u8 key[0];\n};\n\nstruct ubifs_bud {\n\tint lnum;\n\tint start;\n\tint jhead;\n\tstruct list_head list;\n\tstruct rb_node rb;\n\tstruct shash_desc *log_hash;\n};\n\nstruct ubifs_budg_info {\n\tlong long int idx_growth;\n\tlong long int data_growth;\n\tlong long int dd_growth;\n\tlong long int uncommitted_idx;\n\tlong long unsigned int old_idx_sz;\n\tint min_idx_lebs;\n\tunsigned int nospace: 1;\n\tunsigned int nospace_rp: 1;\n\tint page_budget;\n\tint inode_budget;\n\tint dent_budget;\n\tlong: 32;\n};\n\nstruct ubifs_budget_req {\n\tunsigned int fast: 1;\n\tunsigned int recalculate: 1;\n\tunsigned int new_page: 1;\n\tunsigned int dirtied_page: 1;\n\tunsigned int new_dent: 1;\n\tunsigned int mod_dent: 1;\n\tunsigned int new_ino: 1;\n\tunsigned int new_ino_d: 13;\n\tunsigned int dirtied_ino: 4;\n\tlong: 8;\n\tunsigned int dirtied_ino_d: 15;\n\tint idx_growth;\n\tint data_growth;\n\tint dd_growth;\n};\n\nstruct ubifs_compressor {\n\tint compr_type;\n\tstruct crypto_acomp *cc;\n\tconst char *name;\n\tconst char *capi_name;\n};\n\nstruct ubifs_cs_node {\n\tstruct ubifs_ch ch;\n\t__le64 cmt_no;\n};\n\nstruct ubifs_data_node {\n\tstruct ubifs_ch ch;\n\t__u8 key[16];\n\t__le32 size;\n\t__le16 compr_type;\n\t__le16 compr_size;\n\t__u8 data[0];\n};\n\nstruct ubifs_lp_stats {\n\tint empty_lebs;\n\tint taken_empty_lebs;\n\tint idx_lebs;\n\tlong: 32;\n\tlong long int total_free;\n\tlong long int total_dirty;\n\tlong long int total_used;\n\tlong long int total_dead;\n\tlong long int total_dark;\n};\n\nstruct ubifs_debug_info {\n\tstruct ubifs_zbranch old_zroot;\n\tint old_zroot_level;\n\tlong: 32;\n\tlong long unsigned int old_zroot_sqnum;\n\tint pc_happened;\n\tint pc_delay;\n\tlong unsigned int pc_timeout;\n\tunsigned int pc_cnt;\n\tunsigned int pc_cnt_max;\n\tlong: 32;\n\tlong long int chk_lpt_sz;\n\tlong long int chk_lpt_sz2;\n\tlong long int chk_lpt_wastage;\n\tint chk_lpt_lebs;\n\tint new_nhead_offs;\n\tint new_ihead_lnum;\n\tint new_ihead_offs;\n\tstruct ubifs_lp_stats saved_lst;\n\tstruct ubifs_budg_info saved_bi;\n\tlong long int saved_free;\n\tint saved_idx_gc_cnt;\n\tunsigned int chk_gen: 1;\n\tunsigned int chk_index: 1;\n\tunsigned int chk_orph: 1;\n\tunsigned int chk_lprops: 1;\n\tunsigned int chk_fs: 1;\n\tunsigned int tst_rcvry: 1;\n\tchar dfs_dir_name[10];\n\tstruct dentry *dfs_dir;\n\tstruct dentry *dfs_dump_lprops;\n\tstruct dentry *dfs_dump_budg;\n\tstruct dentry *dfs_dump_tnc;\n\tstruct dentry *dfs_chk_gen;\n\tstruct dentry *dfs_chk_index;\n\tstruct dentry *dfs_chk_orph;\n\tstruct dentry *dfs_chk_lprops;\n\tstruct dentry *dfs_chk_fs;\n\tstruct dentry *dfs_tst_rcvry;\n\tstruct dentry *dfs_ro_error;\n\tlong: 32;\n};\n\nstruct ubifs_dent_node {\n\tstruct ubifs_ch ch;\n\t__u8 key[16];\n\t__le64 inum;\n\t__u8 padding1;\n\t__u8 type;\n\t__le16 nlen;\n\t__le32 cookie;\n\t__u8 name[0];\n};\n\nunion ubifs_dev_desc {\n\t__le32 new;\n\t__le64 huge;\n};\n\nstruct ubifs_dir_data {\n\tstruct ubifs_dent_node *dent;\n\tlong: 32;\n\tu64 cookie;\n};\n\nstruct ubifs_mount_opts {\n\tunsigned int unmount_mode: 2;\n\tunsigned int bulk_read: 2;\n\tunsigned int chk_data_crc: 2;\n\tunsigned int override_compr: 1;\n\tunsigned int compr_type: 2;\n};\n\nstruct ubifs_fs_context {\n\tstruct ubifs_mount_opts mount_opts;\n\tchar *auth_key_name;\n\tchar *auth_hash_name;\n\tunsigned int no_chk_data_crc: 1;\n\tunsigned int bulk_read: 1;\n\tunsigned int default_compr: 2;\n\tunsigned int assert_action: 2;\n};\n\nstruct ubifs_gced_idx_leb {\n\tstruct list_head list;\n\tint lnum;\n\tint unmap;\n};\n\nstruct ubifs_global_debug_info {\n\tunsigned int chk_gen: 1;\n\tunsigned int chk_index: 1;\n\tunsigned int chk_orph: 1;\n\tunsigned int chk_lprops: 1;\n\tunsigned int chk_fs: 1;\n\tunsigned int tst_rcvry: 1;\n};\n\nunion ubifs_in_ptr {\n\tconst void *buf;\n\tstruct folio *folio;\n};\n\nstruct ubifs_node_range {\n\tunion {\n\t\tint len;\n\t\tint min_len;\n\t};\n\tint max_len;\n};\n\nstruct ubifs_lpt_heap {\n\tstruct ubifs_lprops **arr;\n\tint cnt;\n\tint max_cnt;\n};\n\nstruct ubifs_sb_node;\n\nstruct ubifs_jhead;\n\nstruct ubifs_mst_node;\n\nstruct ubifs_orphan;\n\nstruct ubifs_lpt_lprops;\n\nstruct ubifs_stats_info;\n\nstruct ubifs_info {\n\tstruct super_block *vfs_sb;\n\tstruct ubifs_sb_node *sup_node;\n\tino_t highest_inum;\n\tlong: 32;\n\tlong long unsigned int max_sqnum;\n\tlong long unsigned int cmt_no;\n\tspinlock_t cnt_lock;\n\tint fmt_version;\n\tint ro_compat_version;\n\tunsigned char uuid[16];\n\tint lhead_lnum;\n\tint lhead_offs;\n\tint ltail_lnum;\n\tstruct mutex log_mutex;\n\tint min_log_bytes;\n\tlong long int cmt_bud_bytes;\n\tstruct rb_root buds;\n\tlong: 32;\n\tlong long int bud_bytes;\n\tspinlock_t buds_lock;\n\tint jhead_cnt;\n\tstruct ubifs_jhead *jheads;\n\tlong: 32;\n\tlong long int max_bud_bytes;\n\tlong long int bg_bud_bytes;\n\tstruct list_head old_buds;\n\tint max_bud_cnt;\n\tatomic_t need_wait_space;\n\twait_queue_head_t reserve_space_wq;\n\tstruct rw_semaphore commit_sem;\n\tint cmt_state;\n\tspinlock_t cs_lock;\n\twait_queue_head_t cmt_wq;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tunsigned int big_lpt: 1;\n\tunsigned int space_fixup: 1;\n\tunsigned int double_hash: 1;\n\tunsigned int encrypted: 1;\n\tunsigned int no_chk_data_crc: 1;\n\tunsigned int bulk_read: 1;\n\tunsigned int default_compr: 2;\n\tunsigned int rw_incompat: 1;\n\tunsigned int assert_action: 2;\n\tunsigned int authenticated: 1;\n\tunsigned int superblock_need_write: 1;\n\tstruct mutex tnc_mutex;\n\tlong: 32;\n\tstruct ubifs_zbranch zroot;\n\tstruct ubifs_znode *cnext;\n\tstruct ubifs_znode *enext;\n\tint *gap_lebs;\n\tvoid *cbuf;\n\tvoid *ileb_buf;\n\tint ileb_len;\n\tint ihead_lnum;\n\tint ihead_offs;\n\tint *ilebs;\n\tint ileb_cnt;\n\tint ileb_nxt;\n\tstruct rb_root old_idx;\n\tint *bottom_up_buf;\n\tstruct ubifs_mst_node *mst_node;\n\tint mst_offs;\n\tint max_bu_buf_len;\n\tstruct mutex bu_mutex;\n\tlong: 32;\n\tstruct bu_info bu;\n\tstruct mutex write_reserve_mutex;\n\tvoid *write_reserve_buf;\n\tint log_lebs;\n\tlong: 32;\n\tlong long int log_bytes;\n\tint log_last;\n\tint lpt_lebs;\n\tint lpt_first;\n\tint lpt_last;\n\tint orph_lebs;\n\tint orph_first;\n\tint orph_last;\n\tint main_lebs;\n\tint main_first;\n\tlong: 32;\n\tlong long int main_bytes;\n\tuint8_t key_hash_type;\n\tuint32_t (*key_hash)(const char *, int);\n\tint key_fmt;\n\tint key_len;\n\tint hash_len;\n\tint fanout;\n\tint min_io_size;\n\tint min_io_shift;\n\tint max_write_size;\n\tint max_write_shift;\n\tint leb_size;\n\tint leb_start;\n\tint half_leb_size;\n\tint idx_leb_size;\n\tint leb_cnt;\n\tint max_leb_cnt;\n\tunsigned int ro_media: 1;\n\tunsigned int ro_mount: 1;\n\tunsigned int ro_error: 1;\n\tatomic_long_t dirty_pg_cnt;\n\tatomic_long_t dirty_zn_cnt;\n\tatomic_long_t clean_zn_cnt;\n\tspinlock_t space_lock;\n\tlong: 32;\n\tstruct ubifs_lp_stats lst;\n\tstruct ubifs_budg_info bi;\n\tlong long unsigned int calc_idx_sz;\n\tint ref_node_alsz;\n\tint mst_node_alsz;\n\tint min_idx_node_sz;\n\tint max_idx_node_sz;\n\tlong long int max_inode_sz;\n\tint max_znode_sz;\n\tint leb_overhead;\n\tint dead_wm;\n\tint dark_wm;\n\tint block_cnt;\n\tstruct ubifs_node_range ranges[14];\n\tstruct ubi_volume_desc *ubi;\n\tstruct ubi_device_info di;\n\tlong: 32;\n\tstruct ubi_volume_info vi;\n\tstruct rb_root orph_tree;\n\tstruct list_head orph_list;\n\tstruct list_head orph_new;\n\tstruct ubifs_orphan *orph_cnext;\n\tstruct ubifs_orphan *orph_dnext;\n\tspinlock_t orphan_lock;\n\tvoid *orph_buf;\n\tint new_orphans;\n\tint cmt_orphans;\n\tint tot_orphans;\n\tint max_orphans;\n\tint ohead_lnum;\n\tint ohead_offs;\n\tint no_orphs;\n\tstruct task_struct *bgt;\n\tchar bgt_name[24];\n\tint need_bgt;\n\tint need_wbuf_sync;\n\tint gc_lnum;\n\tvoid *sbuf;\n\tstruct list_head idx_gc;\n\tint idx_gc_cnt;\n\tint gc_seq;\n\tint gced_lnum;\n\tstruct list_head infos_list;\n\tstruct mutex umount_mutex;\n\tunsigned int shrinker_run_no;\n\tint space_bits;\n\tint lpt_lnum_bits;\n\tint lpt_offs_bits;\n\tint lpt_spc_bits;\n\tint pcnt_bits;\n\tint lnum_bits;\n\tint nnode_sz;\n\tint pnode_sz;\n\tint ltab_sz;\n\tint lsave_sz;\n\tint pnode_cnt;\n\tint nnode_cnt;\n\tint lpt_hght;\n\tint pnodes_have;\n\tstruct mutex lp_mutex;\n\tint lpt_lnum;\n\tint lpt_offs;\n\tint nhead_lnum;\n\tint nhead_offs;\n\tint lpt_drty_flgs;\n\tint dirty_nn_cnt;\n\tint dirty_pn_cnt;\n\tint check_lpt_free;\n\tlong: 32;\n\tlong long int lpt_sz;\n\tvoid *lpt_nod_buf;\n\tvoid *lpt_buf;\n\tstruct ubifs_nnode *nroot;\n\tstruct ubifs_cnode *lpt_cnext;\n\tstruct ubifs_lpt_heap lpt_heap[3];\n\tstruct ubifs_lpt_heap dirty_idx;\n\tstruct list_head uncat_list;\n\tstruct list_head empty_list;\n\tstruct list_head freeable_list;\n\tstruct list_head frdi_idx_list;\n\tint freeable_cnt;\n\tint in_a_category_cnt;\n\tint ltab_lnum;\n\tint ltab_offs;\n\tstruct ubifs_lpt_lprops *ltab;\n\tstruct ubifs_lpt_lprops *ltab_cmt;\n\tint lsave_cnt;\n\tint lsave_lnum;\n\tint lsave_offs;\n\tint *lsave;\n\tint lscan_lnum;\n\tlong: 32;\n\tlong long int rp_size;\n\tlong long int report_rp_size;\n\tkuid_t rp_uid;\n\tkgid_t rp_gid;\n\tstruct crypto_shash *hash_tfm;\n\tstruct crypto_shash *hmac_tfm;\n\tint hmac_desc_len;\n\tchar *auth_key_name;\n\tchar *auth_hash_name;\n\tenum hash_algo auth_hash_algo;\n\tstruct shash_desc *log_hash;\n\tunsigned int empty: 1;\n\tunsigned int need_recovery: 1;\n\tunsigned int replaying: 1;\n\tunsigned int mounting: 1;\n\tunsigned int remounting_rw: 1;\n\tunsigned int probing: 1;\n\tstruct list_head replay_list;\n\tstruct list_head replay_buds;\n\tlong long unsigned int cs_sqnum;\n\tstruct list_head unclean_leb_list;\n\tstruct ubifs_mst_node *rcvrd_mst_node;\n\tstruct rb_root size_tree;\n\tstruct ubifs_mount_opts mount_opts;\n\tstruct ubifs_debug_info *dbg;\n\tstruct ubifs_stats_info *stats;\n\tlong: 32;\n};\n\nstruct ubifs_ino_node {\n\tstruct ubifs_ch ch;\n\t__u8 key[16];\n\t__le64 creat_sqnum;\n\t__le64 size;\n\t__le64 atime_sec;\n\t__le64 ctime_sec;\n\t__le64 mtime_sec;\n\t__le32 atime_nsec;\n\t__le32 ctime_nsec;\n\t__le32 mtime_nsec;\n\t__le32 nlink;\n\t__le32 uid;\n\t__le32 gid;\n\t__le32 mode;\n\t__le32 flags;\n\t__le32 data_len;\n\t__le32 xattr_cnt;\n\t__le32 xattr_size;\n\t__u8 padding1[4];\n\t__le32 xattr_names;\n\t__le16 compr_type;\n\t__u8 padding2[26];\n\t__u8 data[0];\n};\n\nstruct ubifs_inode {\n\tstruct inode vfs_inode;\n\tlong long unsigned int creat_sqnum;\n\tlong long unsigned int del_cmtno;\n\tunsigned int xattr_size;\n\tunsigned int xattr_cnt;\n\tunsigned int xattr_names;\n\tunsigned int dirty: 1;\n\tunsigned int xattr: 1;\n\tunsigned int bulk_read: 1;\n\tunsigned int compr_type: 2;\n\tstruct mutex ui_mutex;\n\tstruct rw_semaphore xattr_sem;\n\tspinlock_t ui_lock;\n\tloff_t synced_i_size;\n\tloff_t ui_size;\n\tint flags;\n\tlong unsigned int last_page_read;\n\tlong unsigned int read_in_a_row;\n\tint data_len;\n\tvoid *data;\n\tlong: 32;\n};\n\nstruct ubifs_wbuf {\n\tstruct ubifs_info *c;\n\tvoid *buf;\n\tint lnum;\n\tint offs;\n\tint avail;\n\tint used;\n\tint size;\n\tint jhead;\n\tint (*sync_callback)(struct ubifs_info *, int, int, int);\n\tstruct mutex io_mutex;\n\tspinlock_t lock;\n\tlong: 32;\n\tstruct hrtimer timer;\n\tunsigned int no_timer: 1;\n\tunsigned int need_sync: 1;\n\tint next_ino;\n\tino_t *inodes;\n\tlong: 32;\n};\n\nstruct ubifs_jhead {\n\tstruct ubifs_wbuf wbuf;\n\tstruct list_head buds_list;\n\tunsigned int grouped: 1;\n\tstruct shash_desc *log_hash;\n};\n\nstruct ubifs_lpt_lprops {\n\tint free;\n\tint dirty;\n\tunsigned int tgc: 1;\n\tunsigned int cmt: 1;\n};\n\nstruct ubifs_mst_node {\n\tstruct ubifs_ch ch;\n\t__le64 highest_inum;\n\t__le64 cmt_no;\n\t__le32 flags;\n\t__le32 log_lnum;\n\t__le32 root_lnum;\n\t__le32 root_offs;\n\t__le32 root_len;\n\t__le32 gc_lnum;\n\t__le32 ihead_lnum;\n\t__le32 ihead_offs;\n\t__le64 index_size;\n\t__le64 total_free;\n\t__le64 total_dirty;\n\t__le64 total_used;\n\t__le64 total_dead;\n\t__le64 total_dark;\n\t__le32 lpt_lnum;\n\t__le32 lpt_offs;\n\t__le32 nhead_lnum;\n\t__le32 nhead_offs;\n\t__le32 ltab_lnum;\n\t__le32 ltab_offs;\n\t__le32 lsave_lnum;\n\t__le32 lsave_offs;\n\t__le32 lscan_lnum;\n\t__le32 empty_lebs;\n\t__le32 idx_lebs;\n\t__le32 leb_cnt;\n\t__u8 hash_root_idx[64];\n\t__u8 hash_lpt[64];\n\t__u8 hmac[64];\n\t__u8 padding[152];\n};\n\nstruct ubifs_old_idx {\n\tstruct rb_node rb;\n\tint lnum;\n\tint offs;\n};\n\nstruct ubifs_orph_node {\n\tstruct ubifs_ch ch;\n\t__le64 cmt_no;\n\t__le64 inos[0];\n};\n\nstruct ubifs_orphan {\n\tstruct rb_node rb;\n\tstruct list_head list;\n\tstruct list_head new_list;\n\tstruct ubifs_orphan *cnext;\n\tstruct ubifs_orphan *dnext;\n\tino_t inum;\n\tunsigned int new: 1;\n\tunsigned int cmt: 1;\n\tunsigned int del: 1;\n};\n\nstruct ubifs_pad_node {\n\tstruct ubifs_ch ch;\n\t__le32 pad_len;\n};\n\nstruct ubifs_ref_node {\n\tstruct ubifs_ch ch;\n\t__le32 lnum;\n\t__le32 offs;\n\t__le32 jhead;\n\t__u8 padding[28];\n};\n\nstruct ubifs_sb_node {\n\tstruct ubifs_ch ch;\n\t__u8 padding[2];\n\t__u8 key_hash;\n\t__u8 key_fmt;\n\t__le32 flags;\n\t__le32 min_io_size;\n\t__le32 leb_size;\n\t__le32 leb_cnt;\n\t__le32 max_leb_cnt;\n\t__le64 max_bud_bytes;\n\t__le32 log_lebs;\n\t__le32 lpt_lebs;\n\t__le32 orph_lebs;\n\t__le32 jhead_cnt;\n\t__le32 fanout;\n\t__le32 lsave_cnt;\n\t__le32 fmt_version;\n\t__le16 default_compr;\n\t__u8 padding1[2];\n\t__le32 rp_uid;\n\t__le32 rp_gid;\n\t__le64 rp_size;\n\t__le32 time_gran;\n\t__u8 uuid[16];\n\t__le32 ro_compat_version;\n\t__u8 hmac[64];\n\t__u8 hmac_wkm[64];\n\t__le16 hash_algo;\n\t__u8 hash_mst[64];\n\t__u8 padding2[3774];\n};\n\nstruct ubifs_scan_leb {\n\tint lnum;\n\tint nodes_cnt;\n\tstruct list_head nodes;\n\tint endpt;\n\tvoid *buf;\n};\n\nstruct ubifs_scan_node {\n\tstruct list_head list;\n\tunion ubifs_key key;\n\tlong long unsigned int sqnum;\n\tint type;\n\tint offs;\n\tint len;\n\tvoid *node;\n};\n\nstruct ubifs_stats_info {\n\tunsigned int magic_errors;\n\tunsigned int node_errors;\n\tunsigned int crc_errors;\n};\n\nstruct ubifs_trun_node {\n\tstruct ubifs_ch ch;\n\t__le32 inum;\n\t__u8 padding[12];\n\t__le64 old_size;\n\t__le64 new_size;\n};\n\nstruct ubifs_unclean_leb {\n\tstruct list_head list;\n\tint lnum;\n\tint endpt;\n};\n\nstruct ubifs_znode {\n\tstruct ubifs_znode *parent;\n\tstruct ubifs_znode *cnext;\n\tstruct ubifs_znode *cparent;\n\tint ciip;\n\tlong unsigned int flags;\n\tlong: 32;\n\ttime64_t time;\n\tint level;\n\tint child_cnt;\n\tint iip;\n\tint alt;\n\tint lnum;\n\tint offs;\n\tint len;\n\tlong: 32;\n\tstruct ubifs_zbranch zbranch[0];\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[10];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udc_ep_regs;\n\nstruct udc_stp_dma;\n\nstruct udc_data_dma;\n\nstruct udc_request;\n\nstruct udc;\n\nstruct udc_ep {\n\tstruct usb_ep ep;\n\tstruct udc_ep_regs *regs;\n\tu32 *txfifo;\n\tu32 *dma;\n\tdma_addr_t td_phys;\n\tdma_addr_t td_stp_dma;\n\tstruct udc_stp_dma *td_stp;\n\tstruct udc_data_dma *td;\n\tstruct udc_request *req;\n\tunsigned int req_used;\n\tunsigned int req_completed;\n\tstruct udc_request *bna_dummy_req;\n\tunsigned int bna_occurred;\n\tunsigned int naking;\n\tstruct udc *dev;\n\tstruct list_head queue;\n\tunsigned int halted;\n\tunsigned int cancel_transfer;\n\tunsigned int num: 5;\n\tunsigned int fifo_depth: 14;\n\tunsigned int in: 1;\n};\n\nstruct udc_csrs;\n\nstruct udc_regs;\n\nstruct udc {\n\tstruct usb_gadget gadget;\n\tspinlock_t lock;\n\tstruct udc_ep ep[32];\n\tstruct usb_gadget_driver *driver;\n\tunsigned int stall_ep0in: 1;\n\tunsigned int waiting_zlp_ack_ep0in: 1;\n\tunsigned int set_cfg_not_acked: 1;\n\tunsigned int data_ep_enabled: 1;\n\tunsigned int data_ep_queued: 1;\n\tunsigned int sys_suspended: 1;\n\tunsigned int connected;\n\tu16 chiprev;\n\tstruct pci_dev *pdev;\n\tstruct udc_csrs *csr;\n\tstruct udc_regs *regs;\n\tstruct udc_ep_regs *ep_regs;\n\tu32 *rxfifo;\n\tu32 *txfifo;\n\tstruct dma_pool *data_requests;\n\tstruct dma_pool *stp_requests;\n\tlong unsigned int phys_addr;\n\tvoid *virt_addr;\n\tunsigned int irq;\n\tu16 cur_config;\n\tu16 cur_intf;\n\tu16 cur_alt;\n\tstruct device *dev;\n\tstruct phy *udc_phy;\n\tstruct extcon_dev *edev;\n\tstruct extcon_specific_cable_nb extcon_nb;\n\tstruct notifier_block nb;\n\tstruct delayed_work drd_work;\n\tu32 conn_type;\n};\n\nstruct udc_csrs {\n\tu32 sca;\n\tu32 ne[9];\n};\n\nstruct udc_data_dma {\n\tu32 status;\n\tu32 _reserved;\n\tu32 bufptr;\n\tu32 next;\n};\n\nstruct udc_ep_regs {\n\tu32 ctl;\n\tu32 sts;\n\tu32 bufin_framenum;\n\tu32 bufout_maxpkt;\n\tu32 subptr;\n\tu32 desptr;\n\tu32 reserved;\n\tu32 confirm;\n};\n\nstruct udc_regs {\n\tu32 cfg;\n\tu32 ctl;\n\tu32 sts;\n\tu32 irqsts;\n\tu32 irqmsk;\n\tu32 ep_irqsts;\n\tu32 ep_irqmsk;\n};\n\nstruct udc_request {\n\tstruct usb_request req;\n\tunsigned int dma_going: 1;\n\tunsigned int dma_done: 1;\n\tdma_addr_t td_phys;\n\tstruct udc_data_dma *td_data;\n\tstruct udc_data_dma *td_data_last;\n\tstruct list_head queue;\n\tunsigned int chain_len;\n};\n\nunion udc_setup_data {\n\tu32 data[2];\n\tstruct usb_ctrlrequest request;\n};\n\nstruct udc_stp_dma {\n\tu32 status;\n\tu32 _reserved;\n\tu32 data12;\n\tu32 data34;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n\tlong: 32;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 32;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct ulpi_device_id {\n\t__u16 vendor;\n\t__u16 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct ulpi {\n\tstruct device dev;\n\tstruct ulpi_device_id id;\n\tconst struct ulpi_ops *ops;\n\tlong: 32;\n};\n\nstruct ulpi_driver {\n\tconst struct ulpi_device_id *id_table;\n\tint (*probe)(struct ulpi *);\n\tvoid (*remove)(struct ulpi *);\n\tstruct device_driver driver;\n};\n\nstruct ulpi_info {\n\tunsigned int id;\n\tchar *name;\n};\n\nstruct ulpi_seq {\n\tu8 addr;\n\tu8 val;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct undef_hook {\n\tstruct list_head node;\n\tu32 instr_mask;\n\tu32 instr_val;\n\tu32 cpsr_mask;\n\tu32 cpsr_val;\n\tint (*fn)(struct pt_regs *, unsigned int);\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct unimac_mdio_pdata {\n\tu32 phy_mask;\n\tint (*wait_func)(void *);\n\tvoid *wait_func_data;\n\tconst char *bus_name;\n\tstruct clk *clk;\n};\n\nstruct unimac_mdio_priv {\n\tstruct mii_bus *mii_bus;\n\tvoid *base;\n\tint (*wait_func)(void *);\n\tvoid *wait_func_data;\n\tstruct clk *clk;\n\tu32 clk_freq;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct uniphier8250_priv {\n\tint line;\n\tstruct clk *clk;\n\tspinlock_t atomic_write_lock;\n};\n\nstruct uniphier_ahciphy_soc_data;\n\nstruct uniphier_ahciphy_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_parent_gio;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_parent;\n\tstruct reset_control *rst_parent_gio;\n\tstruct reset_control *rst_pm;\n\tstruct reset_control *rst_tx;\n\tstruct reset_control *rst_rx;\n\tconst struct uniphier_ahciphy_soc_data *data;\n};\n\nstruct uniphier_ahciphy_soc_data {\n\tint (*init)(struct uniphier_ahciphy_priv *);\n\tint (*power_on)(struct uniphier_ahciphy_priv *);\n\tint (*power_off)(struct uniphier_ahciphy_priv *);\n\tbool is_legacy;\n\tbool is_ready_high;\n\tbool is_phy_clk;\n};\n\nstruct uniphier_aidet_priv {\n\tstruct irq_domain *domain;\n\tvoid *reg_base;\n\tspinlock_t lock;\n\tu32 saved_vals[8];\n};\n\nstruct uniphier_clk_cpugear {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int regbase;\n\tunsigned int mask;\n};\n\nstruct uniphier_clk_cpugear_data {\n\tconst char *parent_names[16];\n\tunsigned int num_parents;\n\tunsigned int regbase;\n\tunsigned int mask;\n};\n\nstruct uniphier_clk_fixed_factor_data {\n\tconst char *parent_name;\n\tunsigned int mult;\n\tunsigned int div;\n};\n\nstruct uniphier_clk_fixed_rate_data {\n\tlong unsigned int fixed_rate;\n};\n\nstruct uniphier_clk_gate_data {\n\tconst char *parent_name;\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct uniphier_clk_mux_data {\n\tconst char *parent_names[8];\n\tunsigned int num_parents;\n\tunsigned int reg;\n\tunsigned int masks[8];\n\tunsigned int vals[8];\n};\n\nstruct uniphier_clk_data {\n\tconst char *name;\n\tenum uniphier_clk_type type;\n\tint idx;\n\tunion {\n\t\tstruct uniphier_clk_cpugear_data cpugear;\n\t\tstruct uniphier_clk_fixed_factor_data factor;\n\t\tstruct uniphier_clk_fixed_rate_data rate;\n\t\tstruct uniphier_clk_gate_data gate;\n\t\tstruct uniphier_clk_mux_data mux;\n\t} data;\n};\n\nstruct uniphier_clk_gate {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct uniphier_clk_mux {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int reg;\n\tconst unsigned int *masks;\n\tconst unsigned int *vals;\n};\n\nstruct uniphier_fi2c_priv {\n\tstruct completion comp;\n\tstruct i2c_adapter adap;\n\tvoid *membase;\n\tstruct clk *clk;\n\tunsigned int len;\n\tu8 *buf;\n\tu32 enabled_irqs;\n\tint error;\n\tunsigned int flags;\n\tunsigned int busy_cnt;\n\tunsigned int clk_cycle;\n\tspinlock_t lock;\n};\n\nstruct uniphier_glue_reset_soc_data;\n\nstruct uniphier_glue_reset_priv {\n\tstruct clk_bulk_data clk[2];\n\tstruct reset_control_bulk_data rst[2];\n\tstruct reset_simple_data rdata;\n\tconst struct uniphier_glue_reset_soc_data *data;\n};\n\nstruct uniphier_glue_reset_soc_data {\n\tint nclks;\n\tconst char * const *clock_names;\n\tint nrsts;\n\tconst char * const *reset_names;\n};\n\nstruct uniphier_gpio_priv {\n\tstruct gpio_chip chip;\n\tstruct irq_chip irq_chip;\n\tstruct irq_domain *domain;\n\tvoid *regs;\n\tspinlock_t lock;\n\tu32 saved_vals[0];\n};\n\nstruct uniphier_i2c_priv {\n\tstruct completion comp;\n\tstruct i2c_adapter adap;\n\tvoid *membase;\n\tstruct clk *clk;\n\tunsigned int busy_cnt;\n\tunsigned int clk_cycle;\n};\n\nstruct uniphier_mdmac_device;\n\nstruct uniphier_mdmac_desc;\n\nstruct uniphier_mdmac_chan {\n\tstruct virt_dma_chan vc;\n\tstruct uniphier_mdmac_device *mdev;\n\tstruct uniphier_mdmac_desc *md;\n\tvoid *reg_ch_base;\n\tunsigned int chan_id;\n};\n\nstruct uniphier_mdmac_desc {\n\tstruct virt_dma_desc vd;\n\tstruct scatterlist *sgl;\n\tunsigned int sg_len;\n\tunsigned int sg_cur;\n\tenum dma_transfer_direction dir;\n};\n\nstruct uniphier_mdmac_device {\n\tstruct dma_device ddev;\n\tstruct clk *clk;\n\tvoid *reg_base;\n\tstruct uniphier_mdmac_chan channels[0];\n};\n\nstruct uniphier_pinctrl_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int num_pins;\n\tconst int *muxvals;\n};\n\nstruct uniphier_pinctrl_socdata;\n\nstruct uniphier_pinctrl_priv {\n\tstruct pinctrl_desc pctldesc;\n\tstruct pinctrl_dev *pctldev;\n\tstruct regmap *regmap;\n\tconst struct uniphier_pinctrl_socdata *socdata;\n\tstruct list_head reg_regions;\n};\n\nstruct uniphier_pinctrl_reg_region {\n\tstruct list_head node;\n\tunsigned int base;\n\tunsigned int nregs;\n\tu32 vals[0];\n};\n\nstruct uniphier_pinmux_function;\n\nstruct uniphier_pinctrl_socdata {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct uniphier_pinctrl_group *groups;\n\tint groups_count;\n\tconst struct uniphier_pinmux_function *functions;\n\tint functions_count;\n\tint (*get_gpio_muxval)(unsigned int, unsigned int);\n\tunsigned int caps;\n};\n\nstruct uniphier_pinmux_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct uniphier_regulator_soc_data;\n\nstruct uniphier_regulator_priv {\n\tstruct clk_bulk_data clk[2];\n\tstruct reset_control *rst[2];\n\tconst struct uniphier_regulator_soc_data *data;\n};\n\nstruct uniphier_regulator_soc_data {\n\tint nclks;\n\tconst char * const *clock_names;\n\tint nrsts;\n\tconst char * const *reset_names;\n\tconst struct regulator_desc *desc;\n\tconst struct regmap_config *regconf;\n};\n\nstruct uniphier_reset_data {\n\tunsigned int id;\n\tunsigned int reg;\n\tunsigned int bit;\n\tunsigned int flags;\n};\n\nstruct uniphier_reset_priv {\n\tstruct reset_controller_dev rcdev;\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tconst struct uniphier_reset_data *data;\n};\n\nstruct uniphier_sd_priv {\n\tstruct tmio_mmc_data tmio_data;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pinstate_uhs;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_br;\n\tstruct reset_control *rst_hw;\n\tstruct dma_chan *chan;\n\tenum dma_data_direction dma_dir;\n\tstruct regmap *sdctrl_regmap;\n\tu32 sdctrl_ch;\n\tlong unsigned int clk_rate;\n\tlong unsigned int caps;\n};\n\nstruct uniphier_system_bus_bank {\n\tu32 base;\n\tu32 end;\n};\n\nstruct uniphier_system_bus_priv {\n\tstruct device *dev;\n\tvoid *membase;\n\tstruct uniphier_system_bus_bank bank[8];\n};\n\nstruct uniphier_tm_soc_data;\n\nstruct uniphier_tm_dev {\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tbool alert_en[3];\n\tstruct thermal_zone_device *tz_dev;\n\tconst struct uniphier_tm_soc_data *data;\n};\n\nstruct uniphier_tm_soc_data {\n\tu32 map_base;\n\tu32 block_base;\n\tu32 tmod_setup_addr;\n};\n\nstruct uniphier_u2phy_param {\n\tu32 offset;\n\tu32 value;\n};\n\nstruct uniphier_u2phy_soc_data;\n\nstruct uniphier_u2phy_priv {\n\tstruct regmap *regmap;\n\tstruct phy *phy;\n\tstruct regulator *vbus;\n\tconst struct uniphier_u2phy_soc_data *data;\n\tstruct uniphier_u2phy_priv *next;\n};\n\nstruct uniphier_u2phy_soc_data {\n\tstruct uniphier_u2phy_param config0;\n\tstruct uniphier_u2phy_param config1;\n};\n\nstruct uniphier_u3hsphy_param {\n\tstruct {\n\t\tint reg_no;\n\t\tint msb;\n\t\tint lsb;\n\t} field;\n\tu8 value;\n};\n\nstruct uniphier_u3hsphy_soc_data;\n\nstruct uniphier_u3hsphy_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_ext;\n\tstruct clk *clk_parent_gio;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_parent;\n\tstruct reset_control *rst_parent_gio;\n\tstruct regulator *vbus;\n\tconst struct uniphier_u3hsphy_soc_data *data;\n};\n\nstruct uniphier_u3hsphy_trim_param;\n\nstruct uniphier_u3hsphy_soc_data {\n\tbool is_legacy;\n\tint nparams;\n\tconst struct uniphier_u3hsphy_param param[4];\n\tu32 config0;\n\tu32 config1;\n\tvoid (*trim_func)(struct uniphier_u3hsphy_priv *, u32 *, struct uniphier_u3hsphy_trim_param *);\n};\n\nstruct uniphier_u3hsphy_trim_param {\n\tunsigned int rterm;\n\tunsigned int sel_t;\n\tunsigned int hs_i;\n};\n\nstruct uniphier_u3ssphy_param {\n\tstruct {\n\t\tint reg_no;\n\t\tint msb;\n\t\tint lsb;\n\t} field;\n\tu8 value;\n};\n\nstruct uniphier_u3ssphy_soc_data;\n\nstruct uniphier_u3ssphy_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *clk_ext;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_parent_gio;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_parent;\n\tstruct reset_control *rst_parent_gio;\n\tstruct regulator *vbus;\n\tconst struct uniphier_u3ssphy_soc_data *data;\n};\n\nstruct uniphier_u3ssphy_soc_data {\n\tbool is_legacy;\n\tint nparams;\n\tconst struct uniphier_u3ssphy_param param[7];\n};\n\nstruct uniqframe {\n\tconst struct sk_buff *skb;\n\tu32 hash;\n\tunsigned int join_rx_count;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_domain {\n\tstruct auth_domain h;\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_gid {\n\tstruct cache_head h;\n\tkuid_t uid;\n\tstruct group_info *gi;\n\tstruct callback_head rcu;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\nstruct unwind_ctrl_block {\n\tlong unsigned int vrs[16];\n\tconst long unsigned int *insn;\n\tlong unsigned int sp_high;\n\tlong unsigned int *lr_addr;\n\tint check_each_pop;\n\tint entries;\n\tint byte;\n};\n\nstruct unwind_idx {\n\tlong unsigned int addr_offset;\n\tlong unsigned int insn;\n};\n\nstruct unwind_stacktrace {\n\tunsigned int nr;\n\tlong unsigned int *entries;\n};\n\nstruct unwind_table {\n\tstruct list_head list;\n\tstruct list_head mod_list;\n\tconst struct unwind_idx *start;\n\tconst struct unwind_idx *origin;\n\tconst struct unwind_idx *stop;\n\tlong unsigned int begin_addr;\n\tlong unsigned int end_addr;\n};\n\nstruct unwind_work;\n\ntypedef void (*unwind_callback_t)(struct unwind_work *, struct unwind_stacktrace *, u64);\n\nstruct unwind_work {\n\tstruct list_head list;\n\tunwind_callback_t func;\n\tint bit;\n};\n\nunion upper_chunk {\n\tunion upper_chunk *next;\n\tunion lower_chunk *data[256];\n};\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct list_head consumers;\n\tstruct inode *inode;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tlong: 32;\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n\tlong: 32;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n\tint dsize;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunsigned int depth;\n\tstruct return_instance *return_instances;\n\tstruct return_instance *ri_pool;\n\tstruct timer_list ri_timer;\n\tseqcount_t ri_seqcount;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tbool signal_denied;\n\tstruct arch_uprobe *auprobe;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\ntypedef void (*usb_complete_t)(struct urb *);\n\nstruct usb_iso_packet_descriptor {\n\tunsigned int offset;\n\tunsigned int length;\n\tunsigned int actual_length;\n\tint status;\n};\n\nstruct usb_anchor;\n\nstruct urb {\n\tstruct kref kref;\n\tint unlinked;\n\tvoid *hcpriv;\n\tatomic_t use_count;\n\tatomic_t reject;\n\tstruct list_head urb_list;\n\tstruct list_head anchor_list;\n\tstruct usb_anchor *anchor;\n\tstruct usb_device *dev;\n\tstruct usb_host_endpoint *ep;\n\tunsigned int pipe;\n\tunsigned int stream_id;\n\tint status;\n\tunsigned int transfer_flags;\n\tvoid *transfer_buffer;\n\tdma_addr_t transfer_dma;\n\tstruct scatterlist *sg;\n\tstruct sg_table *sgt;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tu32 transfer_buffer_length;\n\tu32 actual_length;\n\tunsigned char *setup_packet;\n\tdma_addr_t setup_dma;\n\tint start_frame;\n\tint number_of_packets;\n\tint interval;\n\tint error_count;\n\tvoid *context;\n\tusb_complete_t complete;\n\tstruct usb_iso_packet_descriptor iso_frame_desc[0];\n};\n\nstruct urb_listitem {\n\tstruct list_head urb_list;\n\tstruct urb *urb;\n};\n\nstruct urb_priv {\n\tstruct ed *ed;\n\tu16 length;\n\tu16 td_cnt;\n\tstruct list_head pending;\n\tstruct td *td[0];\n};\n\nstruct xhci_segment;\n\nstruct xhci_td {\n\tstruct list_head td_list;\n\tstruct list_head cancelled_td_list;\n\tint status;\n\tenum xhci_cancelled_td_status cancel_status;\n\tstruct urb *urb;\n\tstruct xhci_segment *start_seg;\n\tunion xhci_trb *start_trb;\n\tstruct xhci_segment *end_seg;\n\tunion xhci_trb *end_trb;\n\tstruct xhci_segment *bounce_seg;\n\tbool urb_length_set;\n\tbool error_mid_td;\n};\n\nstruct urb_priv___2 {\n\tint num_tds;\n\tint num_tds_done;\n\tstruct xhci_td td[0];\n};\n\ntypedef struct urb_priv urb_priv_t;\n\nstruct us_data;\n\ntypedef int (*trans_cmnd)(struct scsi_cmnd *, struct us_data *);\n\ntypedef int (*trans_reset)(struct us_data *);\n\ntypedef void (*proto_cmnd)(struct scsi_cmnd *, struct us_data *);\n\nstruct usb_sg_request {\n\tint status;\n\tsize_t bytes;\n\tspinlock_t lock;\n\tstruct usb_device *dev;\n\tint pipe;\n\tint entries;\n\tstruct urb **urbs;\n\tint count;\n\tstruct completion complete;\n};\n\ntypedef void (*extra_data_destructor)(void *);\n\ntypedef void (*pm_hook)(struct us_data *, int);\n\nstruct us_unusual_dev;\n\nstruct us_data {\n\tstruct mutex dev_mutex;\n\tstruct usb_device *pusb_dev;\n\tstruct usb_interface *pusb_intf;\n\tconst struct us_unusual_dev *unusual_dev;\n\tu64 fflags;\n\tlong unsigned int dflags;\n\tunsigned int send_bulk_pipe;\n\tunsigned int recv_bulk_pipe;\n\tunsigned int send_ctrl_pipe;\n\tunsigned int recv_ctrl_pipe;\n\tunsigned int recv_intr_pipe;\n\tchar *transport_name;\n\tchar *protocol_name;\n\t__le32 bcs_signature;\n\tu8 subclass;\n\tu8 protocol;\n\tu8 max_lun;\n\tu8 ifnum;\n\tu8 ep_bInterval;\n\ttrans_cmnd transport;\n\ttrans_reset transport_reset;\n\tproto_cmnd proto_handler;\n\tstruct scsi_cmnd *srb;\n\tunsigned int tag;\n\tchar scsi_name[32];\n\tstruct urb *current_urb;\n\tstruct usb_ctrlrequest *cr;\n\tstruct usb_sg_request current_sg;\n\tunsigned char *iobuf;\n\tdma_addr_t iobuf_dma;\n\tstruct task_struct *ctl_thread;\n\tstruct completion cmnd_ready;\n\tstruct completion notify;\n\twait_queue_head_t delay_wait;\n\tstruct delayed_work scan_dwork;\n\tvoid *extra;\n\textra_data_destructor extra_destructor;\n\tpm_hook suspend_resume_hook;\n\tint use_last_sector_hacks;\n\tint last_sector_retries;\n};\n\nstruct us_unusual_dev {\n\tconst char *vendorName;\n\tconst char *productName;\n\t__u8 useProtocol;\n\t__u8 useTransport;\n\tint (*initFunction)(struct us_data *);\n};\n\nstruct usage_priority {\n\t__u32 usage;\n\tbool global;\n\tunsigned int slot_overwrite;\n};\n\nstruct usb2_lpm_parameters {\n\tunsigned int besl;\n\tint timeout;\n};\n\nstruct usb3503 {\n\tenum usb3503_mode mode;\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tu8 port_off_mask;\n\tstruct gpio_desc *bypass;\n\tstruct gpio_desc *intn;\n\tstruct gpio_desc *reset;\n\tstruct gpio_desc *connect;\n\tbool secondary_ref_clk;\n};\n\nstruct usb3503_platform_data {\n\tenum usb3503_mode initial_mode;\n\tu8 port_off_mask;\n};\n\nstruct usb3_lpm_parameters {\n\tunsigned int mel;\n\tunsigned int pel;\n\tunsigned int sel;\n\tint timeout;\n};\n\nstruct usb_anchor {\n\tstruct list_head urb_list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tatomic_t suspend_wakeups;\n\tunsigned int poisoned: 1;\n};\n\nstruct usb_bos_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumDeviceCaps;\n} __attribute__((packed));\n\nstruct usb_bus {\n\tstruct device *controller;\n\tstruct device *sysdev;\n\tint busnum;\n\tconst char *bus_name;\n\tu8 uses_pio_for_control;\n\tu8 otg_port;\n\tunsigned int is_b_host: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int no_stop_on_short: 1;\n\tunsigned int no_sg_constraint: 1;\n\tunsigned int sg_tablesize;\n\tint devnum_next;\n\tstruct mutex devnum_next_mutex;\n\tlong unsigned int devmap[4];\n\tstruct usb_device *root_hub;\n\tstruct usb_bus *hs_companion;\n\tint bandwidth_allocated;\n\tint bandwidth_int_reqs;\n\tint bandwidth_isoc_reqs;\n\tunsigned int resuming_ports;\n};\n\nstruct usb_cdc_acm_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n};\n\nstruct usb_cdc_call_mgmt_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n\t__u8 bDataInterface;\n};\n\nstruct usb_cdc_country_functional_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iCountryCodeRelDate;\n\tunion {\n\t\t__le16 wCountryCode0;\n\t\tstruct {\n\t\t\tstruct {} __empty_wCountryCodes;\n\t\t\t__le16 wCountryCodes[0];\n\t\t};\n\t};\n};\n\nstruct usb_cdc_dmm_desc {\n\t__u8 bFunctionLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubtype;\n\t__u16 bcdVersion;\n\t__le16 wMaxCommand;\n} __attribute__((packed));\n\nstruct usb_cdc_ether_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iMACAddress;\n\t__le32 bmEthernetStatistics;\n\t__le16 wMaxSegmentSize;\n\t__le16 wNumberMCFilters;\n\t__u8 bNumberPowerFilters;\n} __attribute__((packed));\n\nstruct usb_cdc_header_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdCDC;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMVersion;\n\t__le16 wMaxControlMessage;\n\t__u8 bNumberFilters;\n\t__u8 bMaxFilterSize;\n\t__le16 wMaxSegmentSize;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_extended_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMExtendedVersion;\n\t__u8 bMaxOutstandingCommandMessages;\n\t__le16 wMTU;\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n\t__u8 bGUID[16];\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_detail_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bGuidDescriptorType;\n\t__u8 bDetailData[0];\n};\n\nstruct usb_cdc_ncm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdNcmVersion;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_ncm_dpe16 {\n\t__le16 wDatagramIndex;\n\t__le16 wDatagramLength;\n};\n\nstruct usb_cdc_ncm_dpe32 {\n\t__le32 dwDatagramIndex;\n\t__le32 dwDatagramLength;\n};\n\nstruct usb_cdc_ncm_ndp16 {\n\t__le32 dwSignature;\n\t__le16 wLength;\n\t__le16 wNextNdpIndex;\n\tstruct usb_cdc_ncm_dpe16 dpe16[0];\n};\n\nstruct usb_cdc_ncm_ndp32 {\n\t__le32 dwSignature;\n\t__le16 wLength;\n\t__le16 wReserved6;\n\t__le32 dwNextNdpIndex;\n\t__le32 dwReserved12;\n\tstruct usb_cdc_ncm_dpe32 dpe32[0];\n};\n\nstruct usb_cdc_ncm_nth16 {\n\t__le32 dwSignature;\n\t__le16 wHeaderLength;\n\t__le16 wSequence;\n\t__le16 wBlockLength;\n\t__le16 wNdpIndex;\n};\n\nstruct usb_cdc_ncm_nth32 {\n\t__le32 dwSignature;\n\t__le16 wHeaderLength;\n\t__le16 wSequence;\n\t__le32 dwBlockLength;\n\t__le32 dwNdpIndex;\n};\n\nstruct usb_cdc_network_terminal_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bEntityId;\n\t__u8 iName;\n\t__u8 bChannelIndex;\n\t__u8 bPhysicalInterface;\n};\n\nstruct usb_cdc_notification {\n\t__u8 bmRequestType;\n\t__u8 bNotificationType;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_cdc_obex_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n} __attribute__((packed));\n\nstruct usb_cdc_parsed_header {\n\tstruct usb_cdc_union_desc *usb_cdc_union_desc;\n\tstruct usb_cdc_header_desc *usb_cdc_header_desc;\n\tstruct usb_cdc_call_mgmt_descriptor *usb_cdc_call_mgmt_descriptor;\n\tstruct usb_cdc_acm_descriptor *usb_cdc_acm_descriptor;\n\tstruct usb_cdc_country_functional_desc *usb_cdc_country_functional_desc;\n\tstruct usb_cdc_network_terminal_desc *usb_cdc_network_terminal_desc;\n\tstruct usb_cdc_ether_desc *usb_cdc_ether_desc;\n\tstruct usb_cdc_dmm_desc *usb_cdc_dmm_desc;\n\tstruct usb_cdc_mdlm_desc *usb_cdc_mdlm_desc;\n\tstruct usb_cdc_mdlm_detail_desc *usb_cdc_mdlm_detail_desc;\n\tstruct usb_cdc_obex_desc *usb_cdc_obex_desc;\n\tstruct usb_cdc_ncm_desc *usb_cdc_ncm_desc;\n\tstruct usb_cdc_mbim_desc *usb_cdc_mbim_desc;\n\tstruct usb_cdc_mbim_extended_desc *usb_cdc_mbim_extended_desc;\n\tbool phonet_magic_present;\n};\n\nstruct usb_cdc_speed_change {\n\t__le32 DLBitRRate;\n\t__le32 ULBitRate;\n};\n\nstruct usb_cdc_union_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bMasterInterface0;\n\tunion {\n\t\t__u8 bSlaveInterface0;\n\t\tstruct {\n\t\t\tstruct {} __empty_bSlaveInterfaces;\n\t\t\t__u8 bSlaveInterfaces[0];\n\t\t};\n\t};\n};\n\nstruct usb_class_driver {\n\tchar *name;\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tconst struct file_operations *fops;\n\tint minor_base;\n};\n\nstruct usb_clk_data {\n\tu32 clk_mask;\n\tu32 reset_mask;\n\tbool reset_needs_clk;\n};\n\nstruct usb_config_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumInterfaces;\n\t__u8 bConfigurationValue;\n\t__u8 iConfiguration;\n\t__u8 bmAttributes;\n\t__u8 bMaxPower;\n} __attribute__((packed));\n\nstruct usb_conn_info {\n\tstruct device *dev;\n\tint conn_id;\n\tstruct usb_role_switch *role_sw;\n\tenum usb_role last_role;\n\tstruct regulator *vbus;\n\tstruct delayed_work dw_det;\n\tlong unsigned int debounce_jiffies;\n\tstruct gpio_desc *id_gpiod;\n\tstruct gpio_desc *vbus_gpiod;\n\tint id_irq;\n\tint vbus_irq;\n\tstruct power_supply_desc desc;\n\tstruct power_supply *charger;\n\tbool initial_detection;\n};\n\nstruct usb_dcd_config_params {\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n\t__u8 besl_baseline;\n\t__u8 besl_deep;\n};\n\nstruct usb_descriptor_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n};\n\nstruct usb_dev_cap_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_dev_state {\n\tstruct list_head list;\n\tstruct usb_device *dev;\n\tstruct file *file;\n\tspinlock_t lock;\n\tstruct list_head async_pending;\n\tstruct list_head async_completed;\n\tstruct list_head memory_list;\n\twait_queue_head_t wait;\n\twait_queue_head_t wait_for_resume;\n\tunsigned int discsignr;\n\tstruct pid *disc_pid;\n\tconst struct cred *cred;\n\tsigval_t disccontext;\n\tlong unsigned int ifclaimed;\n\tu32 disabled_bulk_eps;\n\tlong unsigned int interface_allowed_mask;\n\tint not_yet_resumed;\n\tbool suspend_allowed;\n\tbool privileges_dropped;\n};\n\nstruct usb_endpoint_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bEndpointAddress;\n\t__u8 bmAttributes;\n\t__le16 wMaxPacketSize;\n\t__u8 bInterval;\n\t__u8 bRefresh;\n\t__u8 bSynchAddress;\n} __attribute__((packed));\n\nstruct usb_ss_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bMaxBurst;\n\t__u8 bmAttributes;\n\t__le16 wBytesPerInterval;\n};\n\nstruct usb_ssp_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wReseved;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_eusb2_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wMaxPacketSize;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_host_endpoint {\n\tstruct usb_endpoint_descriptor desc;\n\tstruct usb_ss_ep_comp_descriptor ss_ep_comp;\n\tstruct usb_ssp_isoc_ep_comp_descriptor ssp_isoc_ep_comp;\n\tstruct usb_eusb2_isoc_ep_comp_descriptor eusb2_isoc_ep_comp;\n\tlong: 0;\n\tstruct list_head urb_list;\n\tvoid *hcpriv;\n\tstruct ep_device *ep_dev;\n\tunsigned char *extra;\n\tint extralen;\n\tint enabled;\n\tint streams;\n} __attribute__((packed));\n\nstruct usb_device_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__le16 idVendor;\n\t__le16 idProduct;\n\t__le16 bcdDevice;\n\t__u8 iManufacturer;\n\t__u8 iProduct;\n\t__u8 iSerialNumber;\n\t__u8 bNumConfigurations;\n};\n\nstruct usb_host_bos;\n\nstruct usb_host_config;\n\nstruct usb_device {\n\tint devnum;\n\tchar devpath[16];\n\tu32 route;\n\tenum usb_device_state state;\n\tenum usb_device_speed speed;\n\tunsigned int rx_lanes;\n\tunsigned int tx_lanes;\n\tenum usb_ssp_rate ssp_rate;\n\tstruct usb_tt *tt;\n\tint ttport;\n\tunsigned int toggle[2];\n\tstruct usb_device *parent;\n\tstruct usb_bus *bus;\n\tstruct usb_host_endpoint ep0;\n\tlong: 32;\n\tstruct device dev;\n\tstruct usb_device_descriptor descriptor;\n\tstruct usb_host_bos *bos;\n\tstruct usb_host_config *config;\n\tstruct usb_host_config *actconfig;\n\tstruct usb_host_endpoint *ep_in[16];\n\tstruct usb_host_endpoint *ep_out[16];\n\tchar **rawdescriptors;\n\tshort unsigned int bus_mA;\n\tu8 portnum;\n\tu8 level;\n\tu8 devaddr;\n\tunsigned int can_submit: 1;\n\tunsigned int persist_enabled: 1;\n\tunsigned int reset_in_progress: 1;\n\tunsigned int have_langid: 1;\n\tunsigned int authorized: 1;\n\tunsigned int authenticated: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int lpm_devinit_allow: 1;\n\tunsigned int usb2_hw_lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_besl_capable: 1;\n\tunsigned int usb2_hw_lpm_enabled: 1;\n\tunsigned int usb2_hw_lpm_allowed: 1;\n\tunsigned int usb3_lpm_u1_enabled: 1;\n\tunsigned int usb3_lpm_u2_enabled: 1;\n\tint string_langid;\n\tchar *product;\n\tchar *manufacturer;\n\tchar *serial;\n\tstruct list_head filelist;\n\tint maxchild;\n\tu32 quirks;\n\tatomic_t urbnum;\n\tlong unsigned int active_duration;\n\tlong unsigned int connect_time;\n\tunsigned int do_remote_wakeup: 1;\n\tunsigned int reset_resume: 1;\n\tunsigned int port_is_suspended: 1;\n\tunsigned int offload_at_suspend: 1;\n\tint offload_usage;\n\tenum usb_link_tunnel_mode tunnel_mode;\n\tstruct device_link *usb4_link;\n\tint slot_id;\n\tstruct usb2_lpm_parameters l1_params;\n\tstruct usb3_lpm_parameters u1_params;\n\tstruct usb3_lpm_parameters u2_params;\n\tunsigned int lpm_disable_count;\n\tu16 hub_delay;\n\tunsigned int use_generic_driver: 1;\n\tlong: 32;\n};\n\nstruct usb_device_id;\n\nstruct usb_device_driver {\n\tconst char *name;\n\tbool (*match)(struct usb_device *);\n\tint (*probe)(struct usb_device *);\n\tvoid (*disconnect)(struct usb_device *);\n\tint (*suspend)(struct usb_device *, pm_message_t);\n\tint (*resume)(struct usb_device *, pm_message_t);\n\tint (*choose_configuration)(struct usb_device *);\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tconst struct usb_device_id *id_table;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int generic_subclass: 1;\n};\n\nstruct usb_device_id {\n\t__u16 match_flags;\n\t__u16 idVendor;\n\t__u16 idProduct;\n\t__u16 bcdDevice_lo;\n\t__u16 bcdDevice_hi;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 bInterfaceNumber;\n\tkernel_ulong_t driver_info;\n};\n\nstruct usb_dynids {\n\tstruct list_head list;\n};\n\nstruct usb_driver {\n\tconst char *name;\n\tint (*probe)(struct usb_interface *, const struct usb_device_id *);\n\tvoid (*disconnect)(struct usb_interface *);\n\tint (*unlocked_ioctl)(struct usb_interface *, unsigned int, void *);\n\tint (*suspend)(struct usb_interface *, pm_message_t);\n\tint (*resume)(struct usb_interface *);\n\tint (*reset_resume)(struct usb_interface *);\n\tint (*pre_reset)(struct usb_interface *);\n\tint (*post_reset)(struct usb_interface *);\n\tvoid (*shutdown)(struct usb_interface *);\n\tconst struct usb_device_id *id_table;\n\tconst struct attribute_group **dev_groups;\n\tstruct usb_dynids dynids;\n\tstruct device_driver driver;\n\tunsigned int no_dynamic_id: 1;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int disable_hub_initiated_lpm: 1;\n\tunsigned int soft_unbind: 1;\n};\n\nstruct usb_dynid {\n\tstruct list_head node;\n\tstruct usb_device_id id;\n};\n\nstruct usb_ehci_pdata {\n\tint caps_offset;\n\tunsigned int has_tt: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int no_io_watchdog: 1;\n\tunsigned int reset_on_resume: 1;\n\tunsigned int dma_mask_64: 1;\n\tunsigned int spurious_oc: 1;\n\tint (*power_on)(struct platform_device *);\n\tvoid (*power_off)(struct platform_device *);\n\tvoid (*power_suspend)(struct platform_device *);\n\tint (*pre_setup)(struct usb_hcd *);\n};\n\nstruct usb_ep_ops {\n\tint (*enable)(struct usb_ep *, const struct usb_endpoint_descriptor *);\n\tint (*disable)(struct usb_ep *);\n\tvoid (*dispose)(struct usb_ep *);\n\tstruct usb_request * (*alloc_request)(struct usb_ep *, gfp_t);\n\tvoid (*free_request)(struct usb_ep *, struct usb_request *);\n\tint (*queue)(struct usb_ep *, struct usb_request *, gfp_t);\n\tint (*dequeue)(struct usb_ep *, struct usb_request *);\n\tint (*set_halt)(struct usb_ep *, int);\n\tint (*set_wedge)(struct usb_ep *);\n\tint (*fifo_status)(struct usb_ep *);\n\tvoid (*fifo_flush)(struct usb_ep *);\n};\n\nstruct usb_eth_dev {\n\tchar *name;\n\t__u16 vendor;\n\t__u16 device;\n\t__u32 private;\n};\n\nstruct usb_ext_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__le32 bmAttributes;\n} __attribute__((packed));\n\nstruct usb_extcon_info {\n\tstruct device *dev;\n\tstruct extcon_dev *edev;\n\tstruct gpio_desc *id_gpiod;\n\tstruct gpio_desc *vbus_gpiod;\n\tint id_irq;\n\tint vbus_irq;\n\tlong unsigned int debounce_jiffies;\n\tstruct delayed_work wq_detcable;\n};\n\nstruct usb_gadget_driver {\n\tchar *function;\n\tenum usb_device_speed max_speed;\n\tint (*bind)(struct usb_gadget *, struct usb_gadget_driver *);\n\tvoid (*unbind)(struct usb_gadget *);\n\tint (*setup)(struct usb_gadget *, const struct usb_ctrlrequest *);\n\tvoid (*disconnect)(struct usb_gadget *);\n\tvoid (*suspend)(struct usb_gadget *);\n\tvoid (*resume)(struct usb_gadget *);\n\tvoid (*reset)(struct usb_gadget *);\n\tstruct device_driver driver;\n\tchar *udc_name;\n\tunsigned int match_existing_only: 1;\n\tbool is_bound: 1;\n};\n\nstruct usb_gadget_ops {\n\tint (*get_frame)(struct usb_gadget *);\n\tint (*wakeup)(struct usb_gadget *);\n\tint (*func_wakeup)(struct usb_gadget *, int);\n\tint (*set_remote_wakeup)(struct usb_gadget *, int);\n\tint (*set_selfpowered)(struct usb_gadget *, int);\n\tint (*vbus_session)(struct usb_gadget *, int);\n\tint (*vbus_draw)(struct usb_gadget *, unsigned int);\n\tint (*pullup)(struct usb_gadget *, int);\n\tint (*ioctl)(struct usb_gadget *, unsigned int, long unsigned int);\n\tvoid (*get_config_params)(struct usb_gadget *, struct usb_dcd_config_params *);\n\tint (*udc_start)(struct usb_gadget *, struct usb_gadget_driver *);\n\tint (*udc_stop)(struct usb_gadget *);\n\tvoid (*udc_set_speed)(struct usb_gadget *, enum usb_device_speed);\n\tvoid (*udc_set_ssp_rate)(struct usb_gadget *, enum usb_ssp_rate);\n\tvoid (*udc_async_callbacks)(struct usb_gadget *, bool);\n\tstruct usb_ep * (*match_ep)(struct usb_gadget *, struct usb_endpoint_descriptor *, struct usb_ss_ep_comp_descriptor *);\n\tint (*check_config)(struct usb_gadget *);\n};\n\nstruct usb_phy_roothub;\n\nstruct usb_hcd {\n\tstruct usb_bus self;\n\tstruct kref kref;\n\tconst char *product_desc;\n\tint speed;\n\tchar irq_descr[24];\n\tstruct timer_list rh_timer;\n\tstruct urb *status_urb;\n\tstruct work_struct wakeup_work;\n\tstruct work_struct died_work;\n\tconst struct hc_driver *driver;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_phy_roothub *phy_roothub;\n\tlong unsigned int flags;\n\tenum usb_dev_authorize_policy dev_policy;\n\tunsigned int rh_registered: 1;\n\tunsigned int rh_pollable: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int msi_enabled: 1;\n\tunsigned int skip_phy_initialization: 1;\n\tunsigned int uses_new_polling: 1;\n\tunsigned int has_tt: 1;\n\tunsigned int amd_resume_bug: 1;\n\tunsigned int can_do_streams: 1;\n\tunsigned int tpl_support: 1;\n\tunsigned int cant_recv_wakeups: 1;\n\tunsigned int irq;\n\tvoid *regs;\n\tresource_size_t rsrc_start;\n\tresource_size_t rsrc_len;\n\tunsigned int power_budget;\n\tstruct giveback_urb_bh high_prio_bh;\n\tstruct giveback_urb_bh low_prio_bh;\n\tstruct mutex *address0_mutex;\n\tstruct mutex *bandwidth_mutex;\n\tstruct usb_hcd *shared_hcd;\n\tstruct usb_hcd *primary_hcd;\n\tstruct dma_pool *pool[4];\n\tint state;\n\tstruct gen_pool *localmem_pool;\n\tlong unsigned int hcd_priv[0];\n};\n\nstruct usb_ss_cap_descriptor;\n\nstruct usb_ssp_cap_descriptor;\n\nstruct usb_ss_container_id_descriptor;\n\nstruct usb_ptm_cap_descriptor;\n\nstruct usb_host_bos {\n\tstruct usb_bos_descriptor *desc;\n\tstruct usb_ext_cap_descriptor *ext_cap;\n\tstruct usb_ss_cap_descriptor *ss_cap;\n\tstruct usb_ssp_cap_descriptor *ssp_cap;\n\tstruct usb_ss_container_id_descriptor *ss_id;\n\tstruct usb_ptm_cap_descriptor *ptm_cap;\n};\n\nstruct usb_interface_assoc_descriptor;\n\nstruct usb_interface_cache;\n\nstruct usb_host_config {\n\tstruct usb_config_descriptor desc;\n\tchar *string;\n\tstruct usb_interface_assoc_descriptor *intf_assoc[16];\n\tstruct usb_interface *interface[32];\n\tstruct usb_interface_cache *intf_cache[32];\n\tunsigned char *extra;\n\tint extralen;\n};\n\nstruct usb_interface_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bInterfaceNumber;\n\t__u8 bAlternateSetting;\n\t__u8 bNumEndpoints;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 iInterface;\n};\n\nstruct usb_host_interface {\n\tstruct usb_interface_descriptor desc;\n\tint extralen;\n\tunsigned char *extra;\n\tstruct usb_host_endpoint *endpoint;\n\tchar *string;\n};\n\nstruct usb_hub_status {\n\t__le16 wHubStatus;\n\t__le16 wHubChange;\n};\n\nstruct usb_port_status {\n\t__le16 wPortStatus;\n\t__le16 wPortChange;\n\t__le32 dwExtPortStatus;\n};\n\nstruct usb_tt {\n\tstruct usb_device *hub;\n\tint multi;\n\tunsigned int think_time;\n\tvoid *hcpriv;\n\tspinlock_t lock;\n\tstruct list_head clear_list;\n\tstruct work_struct clear_work;\n};\n\nstruct usb_hub_descriptor;\n\nstruct usb_port;\n\nstruct usb_hub {\n\tstruct device *intfdev;\n\tstruct usb_device *hdev;\n\tstruct kref kref;\n\tstruct urb *urb;\n\tu8 (*buffer)[8];\n\tunion {\n\t\tstruct usb_hub_status hub;\n\t\tstruct usb_port_status port;\n\t} *status;\n\tstruct mutex status_mutex;\n\tint error;\n\tint nerrors;\n\tlong unsigned int event_bits[1];\n\tlong unsigned int change_bits[1];\n\tlong unsigned int removed_bits[1];\n\tlong unsigned int wakeup_bits[1];\n\tlong unsigned int power_bits[1];\n\tlong unsigned int child_usage_bits[1];\n\tlong unsigned int warm_reset_bits[1];\n\tstruct usb_hub_descriptor *descriptor;\n\tstruct usb_tt tt;\n\tunsigned int mA_per_port;\n\tunsigned int wakeup_enabled_descendants;\n\tunsigned int limited_power: 1;\n\tunsigned int quiescing: 1;\n\tunsigned int disconnected: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int quirk_disable_autosuspend: 1;\n\tunsigned int quirk_check_port_auto_suspend: 1;\n\tunsigned int has_indicators: 1;\n\tu8 indicator[31];\n\tstruct delayed_work leds;\n\tstruct delayed_work init_work;\n\tstruct delayed_work post_resume_work;\n\tstruct work_struct events;\n\tspinlock_t irq_urb_lock;\n\tstruct timer_list irq_urb_retry;\n\tstruct usb_port **ports;\n\tstruct list_head onboard_devs;\n};\n\nstruct usb_hub_descriptor {\n\t__u8 bDescLength;\n\t__u8 bDescriptorType;\n\t__u8 bNbrPorts;\n\t__le16 wHubCharacteristics;\n\t__u8 bPwrOn2PwrGood;\n\t__u8 bHubContrCurrent;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 DeviceRemovable[4];\n\t\t\t__u8 PortPwrCtrlMask[4];\n\t\t} hs;\n\t\tstruct {\n\t\t\t__u8 bHubHdrDecLat;\n\t\t\t__le16 wHubDelay;\n\t\t\t__le16 DeviceRemovable;\n\t\t} __attribute__((packed)) ss;\n\t} u;\n} __attribute__((packed));\n\nstruct usb_interface {\n\tstruct usb_host_interface *altsetting;\n\tstruct usb_host_interface *cur_altsetting;\n\tunsigned int num_altsetting;\n\tstruct usb_interface_assoc_descriptor *intf_assoc;\n\tint minor;\n\tenum usb_interface_condition condition;\n\tunsigned int sysfs_files_created: 1;\n\tunsigned int ep_devs_created: 1;\n\tunsigned int unregistering: 1;\n\tunsigned int needs_remote_wakeup: 1;\n\tunsigned int needs_altsetting0: 1;\n\tunsigned int needs_binding: 1;\n\tunsigned int resetting_device: 1;\n\tunsigned int authorized: 1;\n\tenum usb_wireless_status wireless_status;\n\tstruct work_struct wireless_status_work;\n\tstruct device dev;\n\tstruct device *usb_dev;\n\tstruct work_struct reset_ws;\n\tlong: 32;\n};\n\nstruct usb_interface_assoc_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bFirstInterface;\n\t__u8 bInterfaceCount;\n\t__u8 bFunctionClass;\n\t__u8 bFunctionSubClass;\n\t__u8 bFunctionProtocol;\n\t__u8 iFunction;\n};\n\nstruct usb_interface_cache {\n\tunsigned int num_altsetting;\n\tstruct kref ref;\n\tstruct usb_host_interface altsetting[0];\n};\n\nstruct usb_memory {\n\tstruct list_head memlist;\n\tint vma_use_count;\n\tint urb_use_count;\n\tu32 size;\n\tvoid *mem;\n\tdma_addr_t dma_handle;\n\tlong unsigned int vm_start;\n\tstruct usb_dev_state *ps;\n};\n\nstruct usb_ohci_pdata {\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int no_big_frame_no: 1;\n\tunsigned int num_ports;\n\tint (*power_on)(struct platform_device *);\n\tvoid (*power_off)(struct platform_device *);\n\tvoid (*power_suspend)(struct platform_device *);\n};\n\nstruct usb_otg_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bmAttributes;\n};\n\nstruct usb_phy_data {\n\tconst char *label;\n\tu8 flags;\n\tu32 mask;\n\tu32 power_on;\n\tu32 power_off;\n};\n\nstruct usb_phy_generic {\n\tstruct usb_phy phy;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct regulator *vcc;\n\tstruct gpio_desc *gpiod_reset;\n\tstruct gpio_desc *gpiod_vbus;\n\tstruct regulator *vbus_draw;\n\tbool vbus_draw_enabled;\n\tlong unsigned int mA;\n\tunsigned int vbus;\n};\n\nstruct usb_phy_io_ops {\n\tint (*read)(struct usb_phy *, u32);\n\tint (*write)(struct usb_phy *, u32, u32);\n};\n\nstruct usb_phy_roothub {\n\tstruct phy *phy;\n\tstruct list_head list;\n};\n\nstruct usb_port {\n\tstruct usb_device *child;\n\tlong: 32;\n\tstruct device dev;\n\tstruct usb_dev_state *port_owner;\n\tstruct usb_port *peer;\n\tstruct typec_connector *connector;\n\tstruct dev_pm_qos_request *req;\n\tenum usb_port_connect_type connect_type;\n\tenum usb_device_state state;\n\tstruct kernfs_node *state_kn;\n\tusb_port_location_t location;\n\tstruct mutex status_lock;\n\tu32 over_current_count;\n\tu8 portnum;\n\tu32 quirks;\n\tunsigned int early_stop: 1;\n\tunsigned int ignore_event: 1;\n\tunsigned int is_superspeed: 1;\n\tunsigned int usb3_lpm_u1_permit: 1;\n\tunsigned int usb3_lpm_u2_permit: 1;\n\tlong: 32;\n};\n\nstruct usb_ptm_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_qualifier_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__u8 bNumConfigurations;\n\t__u8 bRESERVED;\n};\n\nstruct usb_reset_data {\n\tvoid *reg;\n\tspinlock_t *lock;\n\tstruct clk *clk;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct usb_role_switch {\n\tstruct device dev;\n\tstruct lock_class_key key;\n\tstruct mutex lock;\n\tstruct module *module;\n\tenum usb_role role;\n\tbool registered;\n\tstruct device *usb2_port;\n\tstruct device *usb3_port;\n\tstruct device *udc;\n\tusb_role_switch_set_t set;\n\tusb_role_switch_get_t get;\n\tbool allow_userspace_control;\n};\n\nstruct usb_set_sel_req {\n\t__u8 u1_sel;\n\t__u8 u1_pel;\n\t__le16 u2_sel;\n\t__le16 u2_pel;\n};\n\nstruct usb_ss_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bmAttributes;\n\t__le16 wSpeedSupported;\n\t__u8 bFunctionalitySupport;\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n};\n\nstruct usb_ss_container_id_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__u8 ContainerID[16];\n};\n\nstruct usb_ssp_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__le32 bmAttributes;\n\t__le16 wFunctionalitySupport;\n\t__le16 wReserved;\n\tunion {\n\t\t__le32 legacy_padding;\n\t\tstruct {\n\t\t\tstruct {} __empty_bmSublinkSpeedAttr;\n\t\t\t__le32 bmSublinkSpeedAttr[0];\n\t\t};\n\t};\n};\n\nstruct usb_tt_clear {\n\tstruct list_head clear_list;\n\tunsigned int tt;\n\tu16 devinfo;\n\tstruct usb_hcd *hcd;\n\tstruct usb_host_endpoint *ep;\n};\n\nstruct usb_udc {\n\tstruct usb_gadget_driver *driver;\n\tstruct usb_gadget *gadget;\n\tstruct device dev;\n\tstruct list_head list;\n\tbool vbus;\n\tbool started;\n\tbool allow_connect;\n\tstruct work_struct vbus_work;\n\tstruct mutex connect_lock;\n};\n\nstruct usbdevfs_bulktransfer {\n\tunsigned int ep;\n\tunsigned int len;\n\tunsigned int timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_connectinfo {\n\tunsigned int devnum;\n\tunsigned char slow;\n};\n\nstruct usbdevfs_conninfo_ex {\n\t__u32 size;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 speed;\n\t__u8 num_ports;\n\t__u8 ports[7];\n};\n\nstruct usbdevfs_ctrltransfer {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\t__u32 timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_disconnect_claim {\n\tunsigned int interface;\n\tunsigned int flags;\n\tchar driver[256];\n};\n\nstruct usbdevfs_disconnectsignal {\n\tunsigned int signr;\n\tvoid *context;\n};\n\nstruct usbdevfs_getdriver {\n\tunsigned int interface;\n\tchar driver[256];\n};\n\nstruct usbdevfs_hub_portinfo {\n\tchar nports;\n\tchar port[127];\n};\n\nstruct usbdevfs_ioctl {\n\tint ifno;\n\tint ioctl_code;\n\tvoid *data;\n};\n\nstruct usbdevfs_iso_packet_desc {\n\tunsigned int length;\n\tunsigned int actual_length;\n\tunsigned int status;\n};\n\nstruct usbdevfs_setinterface {\n\tunsigned int interface;\n\tunsigned int altsetting;\n};\n\nstruct usbdevfs_streams {\n\tunsigned int num_streams;\n\tunsigned int num_eps;\n\tunsigned char eps[0];\n};\n\nstruct usbdevfs_urb {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tint status;\n\tunsigned int flags;\n\tvoid *buffer;\n\tint buffer_length;\n\tint actual_length;\n\tint start_frame;\n\tunion {\n\t\tint number_of_packets;\n\t\tunsigned int stream_id;\n\t};\n\tint error_count;\n\tunsigned int signr;\n\tvoid *usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbhid_device {\n\tstruct hid_device *hid;\n\tstruct usb_interface *intf;\n\tint ifnum;\n\tunsigned int bufsize;\n\tstruct urb *urbin;\n\tchar *inbuf;\n\tdma_addr_t inbuf_dma;\n\tstruct urb *urbctrl;\n\tstruct usb_ctrlrequest *cr;\n\tstruct hid_control_fifo ctrl[256];\n\tunsigned char ctrlhead;\n\tunsigned char ctrltail;\n\tchar *ctrlbuf;\n\tdma_addr_t ctrlbuf_dma;\n\tlong unsigned int last_ctrl;\n\tstruct urb *urbout;\n\tstruct hid_output_fifo out[256];\n\tunsigned char outhead;\n\tunsigned char outtail;\n\tchar *outbuf;\n\tdma_addr_t outbuf_dma;\n\tlong unsigned int last_out;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tlong unsigned int iofl;\n\tstruct timer_list io_retry;\n\tlong unsigned int stop_retry;\n\tunsigned int retry_delay;\n\tstruct work_struct reset_work;\n\twait_queue_head_t wait;\n};\n\nstruct usbhs_omap_platform_data;\n\nstruct usbhs_hcd_omap {\n\tint nports;\n\tstruct clk **utmi_clk;\n\tstruct clk **hsic60m_clk;\n\tstruct clk **hsic480m_clk;\n\tstruct clk *xclk60mhsp1_ck;\n\tstruct clk *xclk60mhsp2_ck;\n\tstruct clk *utmi_p1_gfclk;\n\tstruct clk *utmi_p2_gfclk;\n\tstruct clk *init_60m_fclk;\n\tstruct clk *ehci_logic_fck;\n\tvoid *uhh_base;\n\tstruct usbhs_omap_platform_data *pdata;\n\tu32 usbhs_rev;\n};\n\nstruct usbhs_omap_platform_data {\n\tint nports;\n\tenum usbhs_omap_port_mode port_mode[3];\n\tint reset_gpio_port[3];\n\tstruct regulator *regulator[3];\n\tstruct ehci_hcd_omap_platform_data *ehci_data;\n\tstruct ohci_hcd_omap_platform_data *ohci_data;\n\tunsigned int single_ulpi_bypass: 1;\n\tunsigned int es2_compatibility: 1;\n\tunsigned int phy_reset: 1;\n};\n\nstruct usbmisc_ops {\n\tint (*init)(struct imx_usbmisc_data *);\n\tint (*post)(struct imx_usbmisc_data *);\n\tint (*set_wakeup)(struct imx_usbmisc_data *, bool);\n\tint (*hsic_set_connect)(struct imx_usbmisc_data *);\n\tint (*hsic_set_clk)(struct imx_usbmisc_data *, bool);\n\tint (*charger_detection)(struct imx_usbmisc_data *);\n\tint (*power_lost_check)(struct imx_usbmisc_data *);\n\tvoid (*pullup)(struct imx_usbmisc_data *, bool);\n\tvoid (*vbus_comparator_on)(struct imx_usbmisc_data *, bool);\n};\n\nstruct usbnet {\n\tstruct usb_device *udev;\n\tstruct usb_interface *intf;\n\tconst struct driver_info *driver_info;\n\tconst char *driver_name;\n\tvoid *driver_priv;\n\twait_queue_head_t wait;\n\tstruct mutex phy_mutex;\n\tunsigned char suspend_count;\n\tunsigned char pkt_cnt;\n\tunsigned char pkt_err;\n\tshort unsigned int rx_qlen;\n\tshort unsigned int tx_qlen;\n\tunsigned int can_dma_sg: 1;\n\tunsigned int in;\n\tunsigned int out;\n\tstruct usb_host_endpoint *status;\n\tunsigned int maxpacket;\n\tstruct timer_list delay;\n\tconst char *padding_pkt;\n\tstruct net_device *net;\n\tint msg_enable;\n\tlong unsigned int data[5];\n\tu32 xid;\n\tu32 hard_mtu;\n\tsize_t rx_urb_size;\n\tstruct mii_if_info mii;\n\tlong int rx_speed;\n\tlong int tx_speed;\n\tstruct sk_buff_head rxq;\n\tstruct sk_buff_head txq;\n\tstruct sk_buff_head done;\n\tstruct sk_buff_head rxq_pause;\n\tstruct urb *interrupt;\n\tunsigned int interrupt_count;\n\tstruct mutex interrupt_mutex;\n\tstruct usb_anchor deferred;\n\tstruct work_struct bh_work;\n\tspinlock_t bql_spinlock;\n\tstruct work_struct kevent;\n\tlong unsigned int flags;\n};\n\nstruct usbtll_omap {\n\tvoid *base;\n\tint nch;\n\tstruct clk *ch_clk[0];\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct used_entry {\n\tu32 id;\n\tu32 len;\n};\n\nstruct user_arg_ptr {\n\tunion {\n\t\tconst char * const *native;\n\t} ptr;\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 32;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[10];\n\tlong int rlimit_max[4];\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tlong: 32;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n\tlong: 32;\n};\n\nstruct user_threshold {\n\tstruct list_head list_node;\n\tint temperature;\n\tint direction;\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tlong unsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct ustring_buffer {\n\tchar buffer[1024];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct utmi_clk_param {\n\tu32 osc_frequency;\n\tu8 enable_delay_count;\n\tu8 stable_count;\n\tu8 active_delay_count;\n\tu8 xtal_freq_count;\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct v2m_data {\n\tstruct list_head entry;\n\tstruct fwnode_handle *fwnode;\n\tstruct resource res;\n\tvoid *base;\n\tu32 spi_start;\n\tu32 nr_spis;\n\tu32 spi_offset;\n\tlong unsigned int *bm;\n\tu32 flags;\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct variant_data {\n\tunsigned int clkreg;\n\tunsigned int clkreg_enable;\n\tunsigned int clkreg_8bit_bus_enable;\n\tunsigned int clkreg_neg_edge_enable;\n\tunsigned int cmdreg_cpsm_enable;\n\tunsigned int cmdreg_lrsp_crc;\n\tunsigned int cmdreg_srsp_crc;\n\tunsigned int cmdreg_srsp;\n\tunsigned int cmdreg_stop;\n\tunsigned int datalength_bits;\n\tunsigned int fifosize;\n\tunsigned int fifohalfsize;\n\tunsigned int data_cmd_enable;\n\tunsigned int datactrl_mask_ddrmode;\n\tunsigned int datactrl_mask_sdio;\n\tunsigned int datactrl_blocksz;\n\tu8 datactrl_any_blocksz: 1;\n\tu8 dma_power_of_2: 1;\n\tu8 datactrl_first: 1;\n\tu8 datacnt_useless: 1;\n\tu8 st_sdio: 1;\n\tu8 st_clkdiv: 1;\n\tu8 stm32_clkdiv: 1;\n\tu32 pwrreg_powerup;\n\tu32 f_max;\n\tu8 signal_direction: 1;\n\tu8 pwrreg_clkgate: 1;\n\tu8 busy_detect: 1;\n\tu8 busy_timeout: 1;\n\tu32 busy_dpsm_flag;\n\tu32 busy_detect_flag;\n\tu32 busy_detect_mask;\n\tu8 pwrreg_nopower: 1;\n\tu8 explicit_mclk_control: 1;\n\tu8 qcom_fifo: 1;\n\tu8 qcom_dml: 1;\n\tu8 reversed_irq_handling: 1;\n\tu8 mmcimask1: 1;\n\tunsigned int irq_pio_mask;\n\tu32 start_err;\n\tu32 opendrain;\n\tu8 dma_lli: 1;\n\tbool supports_sdio_irq;\n\tu32 stm32_idmabsize_mask;\n\tu32 stm32_idmabsize_align;\n\tbool dma_flow_controller;\n\tvoid (*init)(struct mmci_host *);\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[8];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcap_actionset_list {\n\tint max;\n\tint cnt;\n\tenum vcap_actionfield_set *actionsets;\n};\n\nstruct vcap_cache_data {\n\tu32 *keystream;\n\tu32 *maskstream;\n\tu32 *actionstream;\n\tu32 counter;\n\tbool sticky;\n};\n\nstruct vcap_admin {\n\tstruct list_head list;\n\tstruct list_head rules;\n\tstruct list_head enabled;\n\tstruct mutex lock;\n\tenum vcap_type vtype;\n\tint vinst;\n\tint first_cid;\n\tint last_cid;\n\tint tgt_inst;\n\tint lookups;\n\tint lookups_per_instance;\n\tint last_valid_addr;\n\tint first_valid_addr;\n\tint last_used_addr;\n\tbool w32be;\n\tbool ingress;\n\tstruct vcap_cache_data cache;\n};\n\nstruct vcap_control;\n\nstruct vcap_admin_debugfs_info {\n\tstruct vcap_control *vctrl;\n\tstruct vcap_admin *admin;\n};\n\nstruct vcap_client_actionfield_ctrl {\n\tstruct list_head list;\n\tenum vcap_action_field action;\n\tenum vcap_field_type type;\n};\n\nstruct vcap_u1_action {\n\tu8 value;\n};\n\nstruct vcap_u32_action {\n\tu32 value;\n};\n\nstruct vcap_u48_action {\n\tu8 value[6];\n};\n\nstruct vcap_u56_action {\n\tu8 value[7];\n};\n\nstruct vcap_u64_action {\n\tu8 value[8];\n};\n\nstruct vcap_u72_action {\n\tu8 value[9];\n};\n\nstruct vcap_u112_action {\n\tu8 value[14];\n};\n\nstruct vcap_u128_action {\n\tu8 value[16];\n};\n\nstruct vcap_client_actionfield_data {\n\tunion {\n\t\tstruct vcap_u1_action u1;\n\t\tstruct vcap_u32_action u32;\n\t\tstruct vcap_u48_action u48;\n\t\tstruct vcap_u56_action u56;\n\t\tstruct vcap_u64_action u64;\n\t\tstruct vcap_u72_action u72;\n\t\tstruct vcap_u112_action u112;\n\t\tstruct vcap_u128_action u128;\n\t};\n};\n\nstruct vcap_client_actionfield {\n\tstruct vcap_client_actionfield_ctrl ctrl;\n\tstruct vcap_client_actionfield_data data;\n};\n\nstruct vcap_client_keyfield_ctrl {\n\tstruct list_head list;\n\tenum vcap_key_field key;\n\tenum vcap_field_type type;\n};\n\nstruct vcap_u1_key {\n\tu8 value;\n\tu8 mask;\n};\n\nstruct vcap_u32_key {\n\tu32 value;\n\tu32 mask;\n};\n\nstruct vcap_u48_key {\n\tu8 value[6];\n\tu8 mask[6];\n};\n\nstruct vcap_u56_key {\n\tu8 value[7];\n\tu8 mask[7];\n};\n\nstruct vcap_u64_key {\n\tu8 value[8];\n\tu8 mask[8];\n};\n\nstruct vcap_u72_key {\n\tu8 value[9];\n\tu8 mask[9];\n};\n\nstruct vcap_u112_key {\n\tu8 value[14];\n\tu8 mask[14];\n};\n\nstruct vcap_u128_key {\n\tu8 value[16];\n\tu8 mask[16];\n};\n\nstruct vcap_client_keyfield_data {\n\tunion {\n\t\tstruct vcap_u1_key u1;\n\t\tstruct vcap_u32_key u32;\n\t\tstruct vcap_u48_key u48;\n\t\tstruct vcap_u56_key u56;\n\t\tstruct vcap_u64_key u64;\n\t\tstruct vcap_u72_key u72;\n\t\tstruct vcap_u112_key u112;\n\t\tstruct vcap_u128_key u128;\n\t};\n};\n\nstruct vcap_client_keyfield {\n\tstruct vcap_client_keyfield_ctrl ctrl;\n\tstruct vcap_client_keyfield_data data;\n};\n\nstruct vcap_operations;\n\nstruct vcap_info;\n\nstruct vcap_statistics;\n\nstruct vcap_control {\n\tconst struct vcap_operations *ops;\n\tconst struct vcap_info *vcaps;\n\tconst struct vcap_statistics *stats;\n\tstruct list_head list;\n};\n\nstruct vcap_counter {\n\tu32 value;\n\tbool sticky;\n};\n\nstruct vcap_enabled_port {\n\tstruct list_head list;\n\tstruct net_device *ndev;\n\tlong unsigned int cookie;\n\tint src_cid;\n\tint dst_cid;\n};\n\nstruct vcap_field {\n\tu16 type;\n\tu16 width;\n\tu16 offset;\n};\n\nstruct vcap_set;\n\nstruct vcap_typegroup;\n\nstruct vcap_info {\n\tchar *name;\n\tu16 rows;\n\tu16 sw_count;\n\tu16 sw_width;\n\tu16 sticky_width;\n\tu16 act_width;\n\tu16 default_cnt;\n\tu16 require_cnt_dis;\n\tu16 version;\n\tconst struct vcap_set *keyfield_set;\n\tint keyfield_set_size;\n\tconst struct vcap_set *actionfield_set;\n\tint actionfield_set_size;\n\tconst struct vcap_field **keyfield_set_map;\n\tint *keyfield_set_map_size;\n\tconst struct vcap_field **actionfield_set_map;\n\tint *actionfield_set_map_size;\n\tconst struct vcap_typegroup **keyfield_set_typegroups;\n\tconst struct vcap_typegroup **actionfield_set_typegroups;\n};\n\nstruct vcap_keyset_list {\n\tint max;\n\tint cnt;\n\tenum vcap_keyfield_set *keysets;\n};\n\nstruct vcap_rule;\n\nstruct vcap_output_print;\n\nstruct vcap_operations {\n\tenum vcap_keyfield_set (*validate_keyset)(struct net_device *, struct vcap_admin *, struct vcap_rule *, struct vcap_keyset_list *, u16);\n\tvoid (*add_default_fields)(struct net_device *, struct vcap_admin *, struct vcap_rule *);\n\tvoid (*cache_erase)(struct vcap_admin *);\n\tvoid (*cache_write)(struct net_device *, struct vcap_admin *, enum vcap_selection, u32, u32);\n\tvoid (*cache_read)(struct net_device *, struct vcap_admin *, enum vcap_selection, u32, u32);\n\tvoid (*init)(struct net_device *, struct vcap_admin *, u32, u32);\n\tvoid (*update)(struct net_device *, struct vcap_admin *, enum vcap_command, enum vcap_selection, u32);\n\tvoid (*move)(struct net_device *, struct vcap_admin *, u32, int, int);\n\tint (*port_info)(struct net_device *, struct vcap_admin *, struct vcap_output_print *);\n};\n\nstruct vcap_output_print {\n\tvoid (*prf)(void *, const char *, ...);\n\tvoid *dst;\n};\n\nstruct vcap_port_debugfs_info {\n\tstruct vcap_control *vctrl;\n\tstruct net_device *ndev;\n};\n\nstruct vcap_rule {\n\tint vcap_chain_id;\n\tenum vcap_user user;\n\tu16 priority;\n\tu32 id;\n\tu64 cookie;\n\tstruct list_head keyfields;\n\tstruct list_head actionfields;\n\tenum vcap_keyfield_set keyset;\n\tenum vcap_actionfield_set actionset;\n\tenum vcap_rule_error exterr;\n\tlong: 32;\n\tu64 client;\n};\n\nstruct vcap_rule_internal {\n\tstruct vcap_rule data;\n\tstruct list_head list;\n\tstruct vcap_admin *admin;\n\tstruct net_device *ndev;\n\tstruct vcap_control *vctrl;\n\tu32 sort_key;\n\tint keyset_sw;\n\tint actionset_sw;\n\tint keyset_sw_regs;\n\tint actionset_sw_regs;\n\tint size;\n\tu32 addr;\n\tu32 counter_id;\n\tstruct vcap_counter counter;\n\tenum vcap_rule_state state;\n};\n\nstruct vcap_rule_move {\n\tint addr;\n\tint offset;\n\tint count;\n};\n\nstruct vcap_set {\n\tu8 type_id;\n\tu8 sw_per_item;\n\tu8 sw_cnt;\n};\n\nstruct vcap_statistics {\n\tchar *name;\n\tint count;\n\tconst char * const *keyfield_set_names;\n\tconst char * const *actionfield_set_names;\n\tconst char * const *keyfield_names;\n\tconst char * const *actionfield_names;\n};\n\nstruct vcap_stream_iter {\n\tu32 offset;\n\tu32 sw_width;\n\tu32 regs_per_sw;\n\tu32 reg_idx;\n\tu32 reg_bitpos;\n\tconst struct vcap_typegroup *tg;\n};\n\nstruct vcap_tc_flower_parse_usage {\n\tstruct flow_cls_offload *fco;\n\tstruct flow_rule *frule;\n\tstruct vcap_rule *vrule;\n\tstruct vcap_admin *admin;\n\tu16 l3_proto;\n\tu8 l4_proto;\n\tu16 tpid;\n\tlong long unsigned int used_keys;\n};\n\nstruct vcap_typegroup {\n\tu16 offset;\n\tu16 width;\n\tu16 value;\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct ve_reset_data {\n\tvoid *reg;\n\tspinlock_t *lock;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct ve_spc_opp;\n\nstruct ve_spc_drvdata {\n\tvoid *baseaddr;\n\tu32 a15_clusid;\n\tuint32_t cur_rsp_mask;\n\tuint32_t cur_rsp_stat;\n\tstruct semaphore sem;\n\tstruct completion done;\n\tstruct ve_spc_opp *opps[2];\n\tint num_opps[2];\n};\n\nstruct ve_spc_opp {\n\tlong unsigned int freq;\n\tlong unsigned int u_volt;\n};\n\nstruct vendor_data {\n\tint fifodepth;\n\tint max_bpw;\n\tbool unidir;\n\tbool extended_cr;\n\tbool pl023;\n\tbool loopback;\n\tbool internal_cs_ctrl;\n};\n\nstruct vendor_data___2 {\n\tconst u16 *reg_offset;\n\tunsigned int ifls;\n\tunsigned int fr_busy;\n\tunsigned int fr_dsr;\n\tunsigned int fr_cts;\n\tunsigned int fr_ri;\n\tunsigned int inv_fr;\n\tbool access_32b;\n\tbool oversampling;\n\tbool dma_threshold;\n\tbool cts_event_workaround;\n\tbool always_enabled;\n\tbool fixed_options;\n\tunsigned int (*get_fifosize)(struct amba_device *);\n};\n\nstruct vexpress_config_bridge_ops;\n\nstruct vexpress_config_bridge {\n\tstruct vexpress_config_bridge_ops *ops;\n\tvoid *context;\n};\n\nstruct vexpress_config_bridge_ops {\n\tstruct regmap * (*regmap_init)(struct device *, void *);\n\tvoid (*regmap_exit)(struct regmap *, void *);\n};\n\nstruct vexpress_osc {\n\tstruct regmap *reg;\n\tstruct clk_hw hw;\n\tlong unsigned int rate_min;\n\tlong unsigned int rate_max;\n};\n\nstruct vexpress_syscfg {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct list_head funcs;\n};\n\nstruct vexpress_syscfg_func {\n\tstruct list_head list;\n\tstruct vexpress_syscfg *syscfg;\n\tstruct regmap *regmap;\n\tint num_templates;\n\tu32 template[0];\n};\n\nstruct vf610_gpio_port {\n\tstruct gpio_generic_chip chip;\n\tvoid *base;\n\tvoid *gpio_base;\n\tconst struct fsl_gpio_soc_data *sdata;\n\tu8 irqc[32];\n\tstruct clk *clk_port;\n\tstruct clk *clk_gpio;\n\tint irq;\n};\n\nstruct vf610_mscm_ir_chip_data {\n\tvoid *mscm_ir_base;\n\tu16 cpu_mask;\n\tu16 saved_irsprc[112];\n\tbool is_nvic;\n};\n\nstruct vf610_nfc {\n\tstruct nand_controller base;\n\tstruct nand_chip chip;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct completion cmd_done;\n\tenum vf610_nfc_variant variant;\n\tstruct clk *clk;\n\tbool data_access;\n\tu32 ecc_mode;\n};\n\nstruct vf610_ocotp {\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct device *dev;\n\tstruct nvmem_device *nvmem;\n\tint timing;\n};\n\nstruct vf_data_storage {\n\tunsigned char vf_mac_addresses[6];\n\tu16 vf_mc_hashes[30];\n\tu16 num_vf_mc_hashes;\n\tu32 flags;\n\tlong unsigned int last_nack;\n\tu16 pf_vlan;\n\tu16 pf_qos;\n\tu16 tx_rate;\n\tbool spoofchk_enabled;\n\tbool trusted;\n};\n\nstruct vfp_double {\n\ts16 exponent;\n\tu16 sign;\n\tlong: 32;\n\tu64 significand;\n};\n\nstruct vfp_single {\n\ts16 exponent;\n\tu16 sign;\n\tu32 significand;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tbool is_firmware_default;\n\tunsigned int (*set_decode)(struct pci_dev *, bool);\n};\n\nstruct vic_config;\n\nstruct vic {\n\tstruct falcon falcon;\n\tvoid *regs;\n\tstruct tegra_drm_client client;\n\tstruct host1x_channel *channel;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tbool can_use_context;\n\tconst struct vic_config *config;\n};\n\nstruct vic_config {\n\tconst char *firmware;\n\tunsigned int version;\n\tbool supports_sid;\n};\n\nstruct vic_device {\n\tvoid *base;\n\tint irq;\n\tu32 valid_sources;\n\tu32 resume_sources;\n\tu32 resume_irqs;\n\tu32 int_select;\n\tu32 int_enable;\n\tu32 soft_int;\n\tu32 protect;\n\tstruct irq_domain *domain;\n};\n\nstruct videomode {\n\tlong unsigned int pixelclock;\n\tu32 hactive;\n\tu32 hfront_porch;\n\tu32 hback_porch;\n\tu32 hsync_len;\n\tu32 vactive;\n\tu32 vfront_porch;\n\tu32 vback_porch;\n\tu32 vsync_len;\n\tenum display_flags flags;\n};\n\nstruct virtio_blk_outhdr {\n\t__virtio32 type;\n\t__virtio32 ioprio;\n\t__virtio64 sector;\n};\n\nstruct virtblk_req {\n\tstruct virtio_blk_outhdr out_hdr;\n\tunion {\n\t\tu8 status;\n\t\tstruct {\n\t\t\t__virtio64 sector;\n\t\t\tu8 status;\n\t\t\tlong: 32;\n\t\t} zone_append;\n\t} in_hdr;\n\tsize_t in_hdr_len;\n\tstruct sg_table sg_table;\n\tstruct scatterlist sg[0];\n};\n\nstruct virtio_admin_cmd {\n\t__le16 opcode;\n\t__le16 group_type;\n\tlong: 32;\n\t__le64 group_member_id;\n\tstruct scatterlist *data_sg;\n\tstruct scatterlist *result_sg;\n\tstruct completion completion;\n\tu32 result_sg_size;\n\tint ret;\n};\n\nstruct virtio_admin_cmd_cap_get_data {\n\t__le16 id;\n\t__u8 reserved[6];\n};\n\nstruct virtio_admin_cmd_cap_set_data {\n\t__le16 id;\n\t__u8 reserved[6];\n\t__u8 cap_specific_data[0];\n};\n\nstruct virtio_admin_cmd_dev_mode_set_data {\n\t__u8 flags;\n};\n\nstruct virtio_admin_cmd_resource_obj_cmd_hdr {\n\t__le16 type;\n\t__u8 reserved[2];\n\t__le32 id;\n};\n\nstruct virtio_dev_part_hdr {\n\t__le16 part_type;\n\t__u8 flags;\n\t__u8 reserved;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 offset;\n\t\t\t__le32 reserved;\n\t\t} pci_common_cfg;\n\t\tstruct {\n\t\t\t__le16 index;\n\t\t\t__u8 reserved[6];\n\t\t} vq_index;\n\t} selector;\n\t__le32 length;\n};\n\nstruct virtio_admin_cmd_dev_parts_get_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n\tstruct virtio_dev_part_hdr hdr_list[0];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_result {\n\tunion {\n\t\tstruct {\n\t\t\t__le32 size;\n\t\t\t__le32 reserved;\n\t\t} parts_size;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t} hdr_list_count;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t\tstruct virtio_dev_part_hdr hdrs[0];\n\t\t} hdr_list;\n\t};\n};\n\nstruct virtio_admin_cmd_hdr {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__u8 reserved1[12];\n\t__le64 group_member_id;\n};\n\nstruct virtio_admin_cmd_query_cap_id_result {\n\t__le64 supported_caps[1];\n};\n\nstruct virtio_admin_cmd_resource_obj_create_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__le64 flags;\n\t__u8 resource_obj_specific_data[0];\n};\n\nstruct virtio_admin_cmd_status {\n\t__le16 status;\n\t__le16 status_qualifier;\n\t__u8 reserved2[4];\n};\n\nstruct virtio_blk_vq;\n\nstruct virtio_blk {\n\tstruct mutex vdev_mutex;\n\tstruct virtio_device *vdev;\n\tstruct gendisk *disk;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct work_struct config_work;\n\tint index;\n\tint num_vqs;\n\tint io_queues[3];\n\tstruct virtio_blk_vq *vqs;\n\tunsigned int zone_sectors;\n};\n\nstruct virtio_blk_geometry {\n\t__virtio16 cylinders;\n\t__u8 heads;\n\t__u8 sectors;\n};\n\nstruct virtio_blk_zoned_characteristics {\n\t__virtio32 zone_sectors;\n\t__virtio32 max_open_zones;\n\t__virtio32 max_active_zones;\n\t__virtio32 max_append_sectors;\n\t__virtio32 write_granularity;\n\t__u8 model;\n\t__u8 unused2[3];\n};\n\nstruct virtio_blk_config {\n\t__virtio64 capacity;\n\t__virtio32 size_max;\n\t__virtio32 seg_max;\n\tstruct virtio_blk_geometry geometry;\n\t__virtio32 blk_size;\n\t__u8 physical_block_exp;\n\t__u8 alignment_offset;\n\t__virtio16 min_io_size;\n\t__virtio32 opt_io_size;\n\t__u8 wce;\n\t__u8 unused;\n\t__virtio16 num_queues;\n\t__virtio32 max_discard_sectors;\n\t__virtio32 max_discard_seg;\n\t__virtio32 discard_sector_alignment;\n\t__virtio32 max_write_zeroes_sectors;\n\t__virtio32 max_write_zeroes_seg;\n\t__u8 write_zeroes_may_unmap;\n\t__u8 unused1[3];\n\t__virtio32 max_secure_erase_sectors;\n\t__virtio32 max_secure_erase_seg;\n\t__virtio32 secure_erase_sector_alignment;\n\tstruct virtio_blk_zoned_characteristics zoned;\n};\n\nstruct virtio_blk_discard_write_zeroes {\n\t__le64 sector;\n\t__le32 num_sectors;\n\t__le32 flags;\n};\n\nstruct virtio_blk_vq {\n\tstruct virtqueue *vq;\n\tspinlock_t lock;\n\tchar name[16];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct virtqueue_info;\n\nstruct virtio_shm_region;\n\nstruct virtio_config_ops {\n\tvoid (*get)(struct virtio_device *, unsigned int, void *, unsigned int);\n\tvoid (*set)(struct virtio_device *, unsigned int, const void *, unsigned int);\n\tu32 (*generation)(struct virtio_device *);\n\tu8 (*get_status)(struct virtio_device *);\n\tvoid (*set_status)(struct virtio_device *, u8);\n\tvoid (*reset)(struct virtio_device *);\n\tint (*find_vqs)(struct virtio_device *, unsigned int, struct virtqueue **, struct virtqueue_info *, struct irq_affinity *);\n\tvoid (*del_vqs)(struct virtio_device *);\n\tvoid (*synchronize_cbs)(struct virtio_device *);\n\tu64 (*get_features)(struct virtio_device *);\n\tvoid (*get_extended_features)(struct virtio_device *, u64 *);\n\tint (*finalize_features)(struct virtio_device *);\n\tconst char * (*bus_name)(struct virtio_device *);\n\tint (*set_vq_affinity)(struct virtqueue *, const struct cpumask *);\n\tconst struct cpumask * (*get_vq_affinity)(struct virtio_device *, int);\n\tbool (*get_shm_region)(struct virtio_device *, struct virtio_shm_region *, u8);\n\tint (*disable_vq_and_reset)(struct virtqueue *);\n\tint (*enable_vq_after_reset)(struct virtqueue *);\n};\n\nstruct virtio_console_config {\n\t__virtio16 cols;\n\t__virtio16 rows;\n\t__virtio32 max_nr_ports;\n\t__virtio32 emerg_wr;\n};\n\nstruct virtio_dev_parts_cap {\n\t__u8 get_parts_resource_objects_limit;\n\t__u8 set_parts_resource_objects_limit;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct vringh_config_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_map_ops;\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tlong: 32;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_driver {\n\tstruct device_driver driver;\n\tconst struct virtio_device_id *id_table;\n\tconst unsigned int *feature_table;\n\tunsigned int feature_table_size;\n\tconst unsigned int *feature_table_legacy;\n\tunsigned int feature_table_size_legacy;\n\tint (*validate)(struct virtio_device *);\n\tint (*probe)(struct virtio_device *);\n\tvoid (*scan)(struct virtio_device *);\n\tvoid (*remove)(struct virtio_device *);\n\tvoid (*config_changed)(struct virtio_device *);\n\tint (*freeze)(struct virtio_device *);\n\tint (*restore)(struct virtio_device *);\n\tint (*reset_prepare)(struct virtio_device *);\n\tint (*reset_done)(struct virtio_device *);\n\tvoid (*shutdown)(struct virtio_device *);\n};\n\nstruct virtio_map_ops {\n\tdma_addr_t (*map_page)(union virtio_map, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid * (*alloc)(union virtio_map, size_t, dma_addr_t *, gfp_t);\n\tvoid (*free)(union virtio_map, size_t, void *, dma_addr_t, long unsigned int);\n\tbool (*need_sync)(union virtio_map, dma_addr_t);\n\tint (*mapping_error)(union virtio_map, dma_addr_t);\n\tsize_t (*max_mapping_size)(union virtio_map);\n};\n\nstruct virtio_mmio_device {\n\tstruct virtio_device vdev;\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tlong unsigned int version;\n\tlong: 32;\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1 {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\tunion {\n\t\tstruct {\n\t\t\t__virtio16 csum_start;\n\t\t\t__virtio16 csum_offset;\n\t\t};\n\t\tstruct {\n\t\t\t__virtio16 start;\n\t\t\t__virtio16 offset;\n\t\t} csum;\n\t\tstruct {\n\t\t\t__le16 segments;\n\t\t\t__le16 dup_acks;\n\t\t} rsc;\n\t};\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1_hash {\n\tstruct virtio_net_hdr_v1 hdr;\n\t__le16 hash_value_lo;\n\t__le16 hash_value_hi;\n\t__le16 hash_report;\n\t__le16 padding;\n};\n\nstruct virtio_net_hdr_v1_hash_tunnel {\n\tstruct virtio_net_hdr_v1_hash hash_hdr;\n\t__le16 outer_th_offset;\n\t__le16 inner_nh_offset;\n};\n\nstruct virtio_net_common_hdr {\n\tunion {\n\t\tstruct virtio_net_hdr hdr;\n\t\tstruct virtio_net_hdr_mrg_rxbuf mrg_hdr;\n\t\tstruct virtio_net_hdr_v1_hash hash_v1_hdr;\n\t\tstruct virtio_net_hdr_v1_hash_tunnel tnl_hdr;\n\t};\n};\n\nstruct virtio_net_config {\n\t__u8 mac[6];\n\t__virtio16 status;\n\t__virtio16 max_virtqueue_pairs;\n\t__virtio16 mtu;\n\t__le32 speed;\n\t__u8 duplex;\n\t__u8 rss_max_key_size;\n\t__le16 rss_max_indirection_table_length;\n\t__le32 supported_hash_types;\n};\n\nstruct virtio_net_ctrl_coal {\n\t__le32 max_packets;\n\t__le32 max_usecs;\n};\n\nstruct virtio_net_ctrl_coal_rx {\n\t__le32 rx_max_packets;\n\t__le32 rx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_tx {\n\t__le32 tx_max_packets;\n\t__le32 tx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_vq {\n\t__le16 vqn;\n\t__le16 reserved;\n\tstruct virtio_net_ctrl_coal coal;\n};\n\nstruct virtio_net_ctrl_mac {\n\t__virtio32 entries;\n\t__u8 macs[0];\n};\n\nstruct virtio_net_ctrl_mq {\n\t__virtio16 virtqueue_pairs;\n};\n\nstruct virtio_net_ctrl_queue_stats {\n\tstruct {\n\t\t__le16 vq_index;\n\t\t__le16 reserved[3];\n\t\t__le64 types_bitmap[1];\n\t} stats[1];\n};\n\nstruct virtio_net_rss_config_hdr {\n\t__le32 hash_types;\n\t__le16 indirection_table_mask;\n\t__le16 unclassified_queue;\n\t__le16 indirection_table[0];\n};\n\nstruct virtio_net_rss_config_trailer {\n\t__le16 max_tx_vq;\n\t__u8 hash_key_length;\n\t__u8 hash_key_data[0];\n};\n\nstruct virtio_net_stats_capabilities {\n\t__le64 supported_stats_types[1];\n};\n\nstruct virtio_net_stats_reply_hdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__le16 vq_index;\n\t__le16 reserved1;\n\t__le16 size;\n};\n\nstruct virtio_pci_vq_info;\n\nstruct virtio_pci_admin_vq {\n\tstruct virtio_pci_vq_info *info;\n\tspinlock_t lock;\n\tu64 supported_cmds;\n\tu64 supported_caps;\n\tu8 max_dev_parts_objects;\n\tstruct ida dev_parts_ida;\n\tchar name[10];\n\tu16 vq_index;\n\tlong: 32;\n};\n\nstruct virtio_pci_common_cfg {\n\t__le32 device_feature_select;\n\t__le32 device_feature;\n\t__le32 guest_feature_select;\n\t__le32 guest_feature;\n\t__le16 msix_config;\n\t__le16 num_queues;\n\t__u8 device_status;\n\t__u8 config_generation;\n\t__le16 queue_select;\n\t__le16 queue_size;\n\t__le16 queue_msix_vector;\n\t__le16 queue_enable;\n\t__le16 queue_notify_off;\n\t__le32 queue_desc_lo;\n\t__le32 queue_desc_hi;\n\t__le32 queue_avail_lo;\n\t__le32 queue_avail_hi;\n\t__le32 queue_used_lo;\n\t__le32 queue_used_hi;\n};\n\nstruct virtio_pci_legacy_device {\n\tstruct pci_dev *pci_dev;\n\tu8 *isr;\n\tvoid *ioaddr;\n\tstruct virtio_device_id id;\n};\n\nstruct virtio_pci_modern_device {\n\tstruct pci_dev *pci_dev;\n\tstruct virtio_pci_common_cfg *common;\n\tvoid *device;\n\tvoid *notify_base;\n\tresource_size_t notify_pa;\n\tu8 *isr;\n\tsize_t notify_len;\n\tsize_t device_len;\n\tsize_t common_len;\n\tint notify_map_cap;\n\tu32 notify_offset_multiplier;\n\tint modern_bars;\n\tstruct virtio_device_id id;\n\tint (*device_id_check)(struct pci_dev *);\n\tlong: 32;\n\tu64 dma_mask;\n};\n\nstruct virtio_pci_device {\n\tstruct virtio_device vdev;\n\tstruct pci_dev *pci_dev;\n\tlong: 32;\n\tunion {\n\t\tstruct virtio_pci_legacy_device ldev;\n\t\tstruct virtio_pci_modern_device mdev;\n\t};\n\tbool is_legacy;\n\tu8 *isr;\n\tspinlock_t lock;\n\tstruct list_head virtqueues;\n\tstruct list_head slow_virtqueues;\n\tstruct virtio_pci_vq_info **vqs;\n\tstruct virtio_pci_admin_vq admin_vq;\n\tint msix_enabled;\n\tint intx_enabled;\n\tcpumask_var_t *msix_affinity_masks;\n\tchar (*msix_names)[256];\n\tunsigned int msix_vectors;\n\tunsigned int msix_used_vectors;\n\tbool per_vq_vectors;\n\tstruct virtqueue * (*setup_vq)(struct virtio_pci_device *, struct virtio_pci_vq_info *, unsigned int, void (*)(struct virtqueue *), const char *, bool, u16);\n\tvoid (*del_vq)(struct virtio_pci_vq_info *);\n\tu16 (*config_vector)(struct virtio_pci_device *, u16);\n\tint (*avq_index)(struct virtio_device *, u16 *, u16 *);\n\tlong: 32;\n};\n\nstruct virtio_pci_modern_common_cfg {\n\tstruct virtio_pci_common_cfg cfg;\n\t__le16 queue_notify_data;\n\t__le16 queue_reset;\n\t__le16 admin_queue_index;\n\t__le16 admin_queue_num;\n};\n\nstruct virtio_pci_vq_info {\n\tstruct virtqueue *vq;\n\tstruct list_head node;\n\tunsigned int msix_vector;\n};\n\nstruct virtio_resource_obj_dev_parts {\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_shm_region {\n\tu64 addr;\n\tu64 len;\n};\n\nstruct virtnet_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *cvq;\n\tstruct net_device *dev;\n\tstruct send_queue *sq;\n\tstruct receive_queue *rq;\n\tunsigned int status;\n\tu16 max_queue_pairs;\n\tu16 curr_queue_pairs;\n\tu16 xdp_queue_pairs;\n\tbool xdp_enabled;\n\tbool big_packets;\n\tunsigned int big_packets_num_skbfrags;\n\tbool mergeable_rx_bufs;\n\tbool has_rss;\n\tbool has_rss_hash_report;\n\tu8 rss_key_size;\n\tu16 rss_indir_table_size;\n\tu32 rss_hash_types_supported;\n\tu32 rss_hash_types_saved;\n\tbool has_cvq;\n\tstruct mutex cvq_lock;\n\tbool any_header_sg;\n\tu8 hdr_len;\n\tbool tx_tnl;\n\tbool rx_tnl;\n\tbool rx_tnl_csum;\n\tstruct work_struct config_work;\n\tstruct work_struct rx_mode_work;\n\tbool rx_mode_work_enabled;\n\tbool affinity_hint_set;\n\tstruct hlist_node node;\n\tstruct hlist_node node_dead;\n\tstruct control_buf *ctrl;\n\tu8 duplex;\n\tu32 speed;\n\tbool rx_dim_enabled;\n\tstruct virtnet_interrupt_coalesce intr_coal_tx;\n\tstruct virtnet_interrupt_coalesce intr_coal_rx;\n\tlong unsigned int guest_offloads;\n\tlong unsigned int guest_offloads_capable;\n\tstruct failover *failover;\n\tlong: 32;\n\tu64 device_stats_cap;\n\tstruct virtio_net_rss_config_hdr *rss_hdr;\n\tunion {\n\t\tstruct virtio_net_rss_config_trailer rss_trailer;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[3];\n\t\t\tu8 rss_hash_key_data[40];\n\t\t};\n\t};\n};\n\nstruct virtnet_rq_dma {\n\tdma_addr_t addr;\n\tu32 ref;\n\tu16 len;\n\tu16 need_sync;\n};\n\nstruct virtnet_sq_free_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 napi_packets;\n\tu64 napi_bytes;\n\tu64 xsk;\n};\n\nstruct virtnet_stat_desc {\n\tchar desc[32];\n\tsize_t offset;\n\tsize_t qstat_offset;\n};\n\nstruct virtnet_stats_ctx {\n\tbool to_qstat;\n\tu32 desc_num[3];\n\tu64 bitmap[3];\n\tu32 size[3];\n\tu64 *data;\n};\n\nstruct virtqueue {\n\tstruct list_head list;\n\tvoid (*callback)(struct virtqueue *);\n\tconst char *name;\n\tstruct virtio_device *vdev;\n\tunsigned int index;\n\tunsigned int num_free;\n\tunsigned int num_max;\n\tbool reset;\n\tvoid *priv;\n};\n\ntypedef void vq_callback_t(struct virtqueue *);\n\nstruct virtqueue_info {\n\tconst char *name;\n\tvq_callback_t *callback;\n\tbool ctx;\n};\n\nstruct vring_virtqueue;\n\nstruct virtqueue_ops {\n\tint (*add)(struct vring_virtqueue *, struct scatterlist **, unsigned int, unsigned int, unsigned int, void *, void *, bool, gfp_t, long unsigned int);\n\tvoid * (*get)(struct vring_virtqueue *, unsigned int *, void **);\n\tbool (*kick_prepare)(struct vring_virtqueue *);\n\tvoid (*disable_cb)(struct vring_virtqueue *);\n\tbool (*enable_cb_delayed)(struct vring_virtqueue *);\n\tunsigned int (*enable_cb_prepare)(struct vring_virtqueue *);\n\tbool (*poll)(const struct vring_virtqueue *, unsigned int);\n\tvoid * (*detach_unused_buf)(struct vring_virtqueue *);\n\tbool (*more_used)(const struct vring_virtqueue *);\n\tint (*resize)(struct vring_virtqueue *, u32);\n\tvoid (*reset)(struct vring_virtqueue *);\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {};\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tunsigned int vm_lock_seq;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tlong: 32;\n\tlong: 32;\n\trefcount_t vm_refcnt;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[75];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct vm_stack {\n\tstruct callback_head rcu;\n\tstruct vm_struct *stack_vm_area;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_exclude_readers_state {\n\tstruct vm_area_struct *vma;\n\tint state;\n\tbool detaching;\n\tbool detached;\n\tbool exclusive;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[4];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmcore_cb {\n\tbool (*pfn_is_ram)(struct vmcore_cb *, long unsigned int);\n\tint (*get_device_ram)(struct vmcore_cb *, struct list_head *);\n\tstruct list_head next;\n};\n\nstruct vmcore_range {\n\tstruct list_head list;\n\tlong long unsigned int paddr;\n\tlong long unsigned int size;\n\tloff_t offset;\n};\n\nstruct voltage_info {\n\tunsigned int num_domains;\n\tstruct scmi_voltage_info *domains;\n};\n\nstruct voltagedomain {\n\tchar *name;\n\tbool scalable;\n\tstruct list_head node;\n\tstruct omap_vc_channel *vc;\n\tconst struct omap_vfsm_instance *vfsm;\n\tstruct omap_vp_instance *vp;\n\tstruct omap_voltdm_pmic *pmic;\n\tstruct omap_vp_param *vp_param;\n\tstruct omap_vc_param *vc_param;\n\tu32 (*read)(u8);\n\tvoid (*write)(u32, u8);\n\tu32 (*rmw)(u32, u32, u8);\n\tunion {\n\t\tconst char *name;\n\t\tu32 rate;\n\t} sys_clk;\n\tint (*scale)(struct voltagedomain *, long unsigned int);\n\tu32 nominal_volt;\n\tstruct omap_volt_data *volt_data;\n};\n\nstruct vring_desc;\n\ntypedef struct vring_desc vring_desc_t;\n\nstruct vring_avail;\n\ntypedef struct vring_avail vring_avail_t;\n\nstruct vring_used;\n\ntypedef struct vring_used vring_used_t;\n\nstruct vring {\n\tunsigned int num;\n\tvring_desc_t *desc;\n\tvring_avail_t *avail;\n\tvring_used_t *used;\n};\n\nstruct vring_avail {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\t__virtio16 ring[0];\n};\n\nstruct vring_desc {\n\t__virtio64 addr;\n\t__virtio32 len;\n\t__virtio16 flags;\n\t__virtio16 next;\n};\n\nstruct vring_desc_extra {\n\tdma_addr_t addr;\n\tu32 len;\n\tu16 flags;\n\tu16 next;\n};\n\nstruct vring_packed_desc;\n\nstruct vring_desc_state_packed {\n\tvoid *data;\n\tstruct vring_packed_desc *indir_desc;\n\tu16 num;\n\tu16 last;\n\tu32 total_in_len;\n};\n\nstruct vring_desc_state_split {\n\tvoid *data;\n\tstruct vring_desc *indir_desc;\n\tu32 total_in_len;\n};\n\nstruct vring_packed_desc {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 id;\n\t__le16 flags;\n};\n\nstruct vring_packed_desc_event {\n\t__le16 off_wrap;\n\t__le16 flags;\n};\n\nstruct vring_used_elem {\n\t__virtio32 id;\n\t__virtio32 len;\n};\n\ntypedef struct vring_used_elem vring_used_elem_t;\n\nstruct vring_used {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\tvring_used_elem_t ring[0];\n};\n\nstruct vring_virtqueue_split {\n\tstruct vring vring;\n\tu16 avail_flags_shadow;\n\tu16 avail_idx_shadow;\n\tstruct vring_desc_state_split *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t queue_dma_addr;\n\tsize_t queue_size_in_bytes;\n\tu32 vring_align;\n\tbool may_reduce_num;\n};\n\nstruct vring_virtqueue_packed {\n\tstruct {\n\t\tunsigned int num;\n\t\tstruct vring_packed_desc *desc;\n\t\tstruct vring_packed_desc_event *driver;\n\t\tstruct vring_packed_desc_event *device;\n\t} vring;\n\tbool avail_wrap_counter;\n\tu16 avail_used_flags;\n\tu16 next_avail_idx;\n\tu16 event_flags_shadow;\n\tstruct vring_desc_state_packed *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t ring_dma_addr;\n\tdma_addr_t driver_event_dma_addr;\n\tdma_addr_t device_event_dma_addr;\n\tsize_t ring_size_in_bytes;\n\tsize_t event_size_in_bytes;\n};\n\nstruct vring_virtqueue {\n\tstruct virtqueue vq;\n\tbool use_map_api;\n\tbool weak_barriers;\n\tbool broken;\n\tbool indirect;\n\tbool event;\n\tenum vq_layout layout;\n\tunsigned int free_head;\n\tstruct used_entry batch_last;\n\tunsigned int num_added;\n\tu16 last_used_idx;\n\tu16 last_used;\n\tbool event_triggered;\n\tunion {\n\t\tstruct vring_virtqueue_split split;\n\t\tstruct vring_virtqueue_packed packed;\n\t};\n\tbool (*notify)(struct virtqueue *);\n\tbool we_own_ring;\n\tunion virtio_map map;\n};\n\nstruct vt8500_chip {\n\tvoid *base;\n\tstruct clk *clk;\n};\n\nstruct vt8500_irq_data {\n\tvoid *base;\n\tstruct irq_domain *domain;\n};\n\nstruct vt8500_port {\n\tstruct uart_port uart;\n\tchar name[16];\n\tstruct clk *clk;\n\tunsigned int clk_predivisor;\n\tunsigned int ier;\n\tunsigned int vt8500_uart_flags;\n};\n\nstruct vt8500_rtc {\n\tvoid *regbase;\n\tint irq_alarm;\n\tstruct rtc_device *rtc;\n\tspinlock_t lock;\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n\tlong: 32;\n};\n\nstruct wakeup_source_info {\n\tunsigned int pmc_fsmr_bit;\n\tunsigned int shdwc_mr_bit;\n\tbool set_polarity;\n};\n\nstruct walk_rcec_data {\n\tstruct pci_dev *rcec;\n\tint (*user_callback)(struct pci_dev *, void *);\n\tvoid *user_data;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct watchdog_core_data {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct watchdog_device *wdd;\n\tstruct mutex lock;\n\tlong: 32;\n\tktime_t last_keepalive;\n\tktime_t last_hw_keepalive;\n\tktime_t open_deadline;\n\tstruct hrtimer timer;\n\tstruct kthread_work work;\n\tlong unsigned int status;\n};\n\nstruct watchdog_governor {\n\tconst char name[20];\n\tvoid (*pretimeout)(struct watchdog_device *);\n};\n\nstruct watchdog_info {\n\t__u32 options;\n\t__u32 firmware_version;\n\t__u8 identity[32];\n};\n\nstruct watchdog_ops {\n\tstruct module *owner;\n\tint (*start)(struct watchdog_device *);\n\tint (*stop)(struct watchdog_device *);\n\tint (*ping)(struct watchdog_device *);\n\tunsigned int (*status)(struct watchdog_device *);\n\tint (*set_timeout)(struct watchdog_device *, unsigned int);\n\tint (*set_pretimeout)(struct watchdog_device *, unsigned int);\n\tunsigned int (*get_timeleft)(struct watchdog_device *);\n\tint (*restart)(struct watchdog_device *, long unsigned int, void *);\n\tlong int (*ioctl)(struct watchdog_device *, unsigned int, long unsigned int);\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tlong: 32;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct wktmr_time {\n\tu32 sec;\n\tu32 pre;\n};\n\nstruct wm8505fb_info {\n\tstruct fb_info fb;\n\tvoid *regbase;\n\tunsigned int contrast;\n};\n\nstruct wmt_dma_descriptor {\n\tu32 flags;\n\tu32 data_buffer_addr;\n\tu32 branch_addr;\n\tu32 reserved1;\n};\n\nstruct wmt_mci_caps {\n\tunsigned int f_min;\n\tunsigned int f_max;\n\tu32 ocr_avail;\n\tu32 caps;\n\tu32 max_seg_size;\n\tu32 max_segs;\n\tu32 max_blk_size;\n};\n\nstruct wmt_mci_priv {\n\tstruct mmc_host *mmc;\n\tvoid *sdmmc_base;\n\tint irq_regular;\n\tint irq_dma;\n\tvoid *dma_desc_buffer;\n\tdma_addr_t dma_desc_device_addr;\n\tstruct completion cmdcomp;\n\tstruct completion datacomp;\n\tstruct completion *comp_cmd;\n\tstruct completion *comp_dma;\n\tstruct mmc_request *req;\n\tstruct mmc_command *cmd;\n\tstruct clk *clk_sdmmc;\n\tstruct device *dev;\n\tu8 power_inverted;\n\tu8 cd_inverted;\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int one_bits;\n\tconst long unsigned int high_bits;\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tlong: 32;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n\tlong: 32;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tlong: 32;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct wrapper_priv_data {\n\tstruct dwc2_hsotg *hsotg;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct x509_certificate {\n\tstruct x509_certificate *next;\n\tstruct x509_certificate *signer;\n\tstruct public_key *pub;\n\tstruct public_key_signature *sig;\n\tu8 sha256[32];\n\tchar *issuer;\n\tchar *subject;\n\tstruct asymmetric_key_id *id;\n\tstruct asymmetric_key_id *skid;\n\ttime64_t valid_from;\n\ttime64_t valid_to;\n\tconst void *tbs;\n\tunsigned int tbs_size;\n\tunsigned int raw_sig_size;\n\tconst void *raw_sig;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_subject;\n\tunsigned int raw_subject_size;\n\tunsigned int raw_skid_size;\n\tconst void *raw_skid;\n\tunsigned int index;\n\tbool seen;\n\tbool verified;\n\tbool self_signed;\n\tbool unsupported_sig;\n\tbool blacklisted;\n\tlong: 32;\n};\n\nstruct x509_parse_context {\n\tstruct x509_certificate *cert;\n\tlong unsigned int data;\n\tconst void *key;\n\tsize_t key_size;\n\tconst void *params;\n\tsize_t params_size;\n\tenum OID key_algo;\n\tenum OID last_oid;\n\tenum OID sig_algo;\n\tu8 o_size;\n\tu8 cn_size;\n\tu8 email_size;\n\tu16 o_offset;\n\tu16 cn_offset;\n\tu16 email_offset;\n\tunsigned int raw_akid_size;\n\tconst void *raw_akid;\n\tconst void *akid_raw_issuer;\n\tunsigned int akid_raw_issuer_size;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[6];\n\t\tlong unsigned int marks[6];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xadc_ops;\n\nstruct xadc {\n\tvoid *base;\n\tstruct clk *clk;\n\tconst struct xadc_ops *ops;\n\tuint16_t threshold[16];\n\tuint16_t temp_hysteresis;\n\tunsigned int alarm_mask;\n\tuint16_t *data;\n\tstruct iio_trigger *trigger;\n\tstruct iio_trigger *convst_trigger;\n\tstruct iio_trigger *samplerate_trigger;\n\tenum xadc_external_mux_mode external_mux_mode;\n\tunsigned int zynq_masked_alarm;\n\tunsigned int zynq_intmask;\n\tstruct delayed_work zynq_unmask_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tstruct completion completion;\n};\n\nstruct xadc_ops {\n\tint (*read)(struct xadc *, unsigned int, uint16_t *);\n\tint (*write)(struct xadc *, unsigned int, uint16_t);\n\tint (*setup)(struct platform_device *, struct iio_dev *, int);\n\tvoid (*update_alarm)(struct xadc *, unsigned int);\n\tlong unsigned int (*get_dclk_rate)(struct xadc *);\n\tirqreturn_t (*interrupt_handler)(int, void *);\n\tunsigned int flags;\n\tenum xadc_type type;\n\tint temp_scale;\n\tint temp_offset;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xcan_devtype_data {\n\tenum xcan_ip_type cantype;\n\tunsigned int flags;\n\tconst struct can_bittiming_const *bittiming_const;\n\tconst char *bus_clk_name;\n\tunsigned int btr_ts2_shift;\n\tunsigned int btr_sjw_shift;\n};\n\nstruct xcan_priv {\n\tstruct can_priv can;\n\tspinlock_t tx_lock;\n\tunsigned int tx_head;\n\tunsigned int tx_tail;\n\tunsigned int tx_max;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tu32 (*read_reg)(const struct xcan_priv *, enum xcan_reg);\n\tvoid (*write_reg)(const struct xcan_priv *, enum xcan_reg, u32);\n\tstruct device *dev;\n\tvoid *reg_base;\n\tlong unsigned int irq_flags;\n\tstruct clk *bus_clk;\n\tstruct clk *can_clk;\n\tstruct xcan_devtype_data devtype;\n\tstruct phy *transceiver;\n\tstruct reset_control *rstc;\n\tbool ecc_enable;\n\tstruct u64_stats_sync syncp;\n\tlong: 32;\n\tu64_stats_t ecc_rx_2_bit_errors;\n\tu64_stats_t ecc_rx_1_bit_errors;\n\tu64_stats_t ecc_txol_2_bit_errors;\n\tu64_stats_t ecc_txol_1_bit_errors;\n\tu64_stats_t ecc_txtl_2_bit_errors;\n\tu64_stats_t ecc_txtl_1_bit_errors;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n\tlong: 32;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tlong: 32;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n\tlong: 32;\n};\n\nstruct xdr_skb_reader {\n\tstruct sk_buff *skb;\n\tunsigned int offset;\n\tbool need_checksum;\n\tsize_t count;\n\t__wsum csum;\n};\n\nstruct xfrm4_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm4_protocol *next;\n\tint priority;\n};\n\nstruct xfrm6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tstruct xfrm6_protocol *next;\n\tint priority;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_dst {\n\tunion {\n\t\tstruct dst_entry dst;\n\t\tstruct rtable rt;\n\t\tstruct rt6_info rt6;\n\t} u;\n\tstruct dst_entry *route;\n\tstruct dst_entry *child;\n\tstruct dst_entry *path;\n\tstruct xfrm_policy *pols[2];\n\tint num_pols;\n\tint num_xfrms;\n\tu32 xfrm_genid;\n\tu32 policy_genid;\n\tu32 route_mtu_cached;\n\tu32 child_mtu_cached;\n\tu32 route_cookie;\n\tu32 path_cookie;\n};\n\nstruct xfrm_dst_lookup_params {\n\tstruct net *net;\n\tdscp_t dscp;\n\tint oif;\n\txfrm_address_t *saddr;\n\txfrm_address_t *daddr;\n\tu32 mark;\n\t__u8 ipproto;\n\tunion flowi_uli uli;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_flo {\n\tstruct dst_entry *dst_orig;\n\tu8 flags;\n};\n\nstruct xfrm_flow_keys {\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_control control;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t} addrs;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_keyid gre;\n};\n\nstruct xfrm_hash_state_ptrs {\n\tconst struct hlist_head *bydst;\n\tconst struct hlist_head *bysrc;\n\tconst struct hlist_head *byspi;\n\tunsigned int hmask;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_if_decode_session_result;\n\nstruct xfrm_if_cb {\n\tbool (*decode_session)(struct sk_buff *, short unsigned int, struct xfrm_if_decode_session_result *);\n};\n\nstruct xfrm_if_decode_session_result {\n\tstruct net *net;\n\tu32 if_id;\n};\n\nstruct xfrm_input_afinfo {\n\tu8 family;\n\tbool is_ipip;\n\tint (*callback)(struct sk_buff *, u8, int);\n};\n\nstruct xfrm_kmaddress {\n\txfrm_address_t local;\n\txfrm_address_t remote;\n\tu32 reserved;\n\tu16 family;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_tmpl;\n\nstruct xfrm_selector;\n\nstruct xfrm_migrate;\n\nstruct xfrm_mgr {\n\tstruct list_head list;\n\tint (*notify)(struct xfrm_state *, const struct km_event *);\n\tint (*acquire)(struct xfrm_state *, struct xfrm_tmpl *, struct xfrm_policy *);\n\tstruct xfrm_policy * (*compile_policy)(struct sock *, int, u8 *, int, int *);\n\tint (*new_mapping)(struct xfrm_state *, xfrm_address_t *, __be16);\n\tint (*notify_policy)(struct xfrm_policy *, int, const struct km_event *);\n\tint (*report)(struct net *, u8, struct xfrm_selector *, xfrm_address_t *);\n\tint (*migrate)(const struct xfrm_selector *, u8, u8, const struct xfrm_migrate *, int, const struct xfrm_kmaddress *, const struct xfrm_encap_tmpl *);\n\tbool (*is_alive)(const struct km_event *);\n};\n\nstruct xfrm_migrate {\n\txfrm_address_t old_daddr;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_daddr;\n\txfrm_address_t new_saddr;\n\tu8 proto;\n\tu8 mode;\n\tu16 reserved;\n\tu32 reqid;\n\tu16 old_family;\n\tu16 new_family;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_tunnel_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tunion {\n\t\tstruct ip_tunnel *ip4;\n\t\tstruct ip6_tnl *ip6;\n\t} tunnel;\n};\n\nstruct xfrm_mode_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\t__be16 id;\n\t__be16 frag_off;\n\tu8 ihl;\n\tu8 tos;\n\tu8 ttl;\n\tu8 protocol;\n\tu8 optlen;\n\tu8 flow_lbl[3];\n};\n\nstruct xfrm_pol_inexact_key {\n\tpossible_net_t net;\n\tu32 if_id;\n\tu16 family;\n\tu8 dir;\n\tu8 type;\n};\n\nstruct xfrm_pol_inexact_bin {\n\tstruct xfrm_pol_inexact_key k;\n\tstruct rhash_head head;\n\tstruct hlist_head hhead;\n\tseqcount_spinlock_t count;\n\tstruct rb_root root_d;\n\tstruct rb_root root_s;\n\tstruct list_head inexact_bins;\n\tstruct callback_head rcu;\n};\n\nstruct xfrm_pol_inexact_candidates {\n\tstruct hlist_head *res[4];\n};\n\nstruct xfrm_pol_inexact_node {\n\tstruct rb_node node;\n\tunion {\n\t\txfrm_address_t addr;\n\t\tstruct callback_head rcu;\n\t};\n\tu8 prefixlen;\n\tstruct rb_root root;\n\tstruct hlist_head hhead;\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_policy_walk_entry {\n\tstruct list_head all;\n\tu8 dead;\n};\n\nstruct xfrm_policy_queue {\n\tstruct sk_buff_head hold_queue;\n\tstruct timer_list hold_timer;\n\tlong unsigned int timeout;\n};\n\nstruct xfrm_tmpl {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tshort unsigned int encap_family;\n\tu32 reqid;\n\tu8 mode;\n\tu8 share;\n\tu8 optional;\n\tu8 allalgs;\n\tu32 aalgos;\n\tu32 ealgos;\n\tu32 calgos;\n};\n\nstruct xfrm_sec_ctx;\n\nstruct xfrm_policy {\n\tpossible_net_t xp_net;\n\tstruct hlist_node bydst;\n\tstruct hlist_node byidx;\n\tstruct hlist_head state_cache_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tu32 pos;\n\tstruct timer_list timer;\n\tatomic_t genid;\n\tu32 priority;\n\tu32 index;\n\tu32 if_id;\n\tstruct xfrm_mark mark;\n\tstruct xfrm_selector selector;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_policy_walk_entry walk;\n\tstruct xfrm_policy_queue polq;\n\tbool bydst_reinsert;\n\tu8 type;\n\tu8 action;\n\tu8 flags;\n\tu8 xfrm_nr;\n\tu16 family;\n\tstruct xfrm_sec_ctx *security;\n\tstruct xfrm_tmpl xfrm_vec[6];\n\tstruct callback_head rcu;\n\tstruct xfrm_dev_offload xdo;\n};\n\nstruct xfrm_policy_afinfo {\n\tstruct dst_ops *dst_ops;\n\tstruct dst_entry * (*dst_lookup)(const struct xfrm_dst_lookup_params *);\n\tint (*get_saddr)(xfrm_address_t *, const struct xfrm_dst_lookup_params *);\n\tint (*fill_dst)(struct xfrm_dst *, struct net_device *, const struct flowi *);\n\tstruct dst_entry * (*blackhole_route)(struct net *, struct dst_entry *);\n};\n\nstruct xfrm_policy_walk {\n\tstruct xfrm_policy_walk_entry walk;\n\tu8 type;\n\tu32 seq;\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 low;\n\t\t\t__u32 hi;\n\t\t} output;\n\t\tstruct {\n\t\t\t__be32 low;\n\t\t\t__be32 hi;\n\t\t} input;\n\t} seq;\n};\n\nstruct xfrm_spi_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunsigned int daddroff;\n\tunsigned int family;\n\t__be32 seq;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tlong: 32;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tlong: 32;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\tlong: 32;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_state_afinfo {\n\tu8 family;\n\tu8 proto;\n\tconst struct xfrm_type_offload *type_offload_esp;\n\tconst struct xfrm_type *type_esp;\n\tconst struct xfrm_type *type_ipip;\n\tconst struct xfrm_type *type_ipip6;\n\tconst struct xfrm_type *type_comp;\n\tconst struct xfrm_type *type_ah;\n\tconst struct xfrm_type *type_routing;\n\tconst struct xfrm_type *type_dstopts;\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*transport_finish)(struct sk_buff *, int);\n\tvoid (*local_error)(struct sk_buff *, u32);\n};\n\nstruct xfrm_trans_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tint (*finish)(struct net *, struct sock *, struct sk_buff *);\n\tstruct net *net;\n};\n\nstruct xfrm_trans_tasklet {\n\tstruct work_struct work;\n\tspinlock_t queue_lock;\n\tstruct sk_buff_head queue;\n};\n\nstruct xfrm_translator {\n\tint (*alloc_compat)(struct sk_buff *, const struct nlmsghdr *);\n\tstruct nlmsghdr * (*rcv_msg_compat)(const struct nlmsghdr *, int, const struct nla_policy *, struct netlink_ext_ack *);\n\tint (*xlate_user_policy_sockptr)(u8 **, int);\n\tstruct module *owner;\n};\n\nstruct xfrm_tunnel {\n\tint (*handler)(struct sk_buff *);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm_tunnel *next;\n\tint priority;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xfrmk_sadinfo {\n\tu32 sadhcnt;\n\tu32 sadhmcnt;\n\tu32 sadcnt;\n};\n\nstruct xfrmk_spdinfo {\n\tu32 incnt;\n\tu32 outcnt;\n\tu32 fwdcnt;\n\tu32 inscnt;\n\tu32 outscnt;\n\tu32 fwdscnt;\n\tu32 spdhcnt;\n\tu32 spdhmcnt;\n};\n\nstruct xgbe_hw_stats {\n\tu32 rx_good_frames;\n\tu32 rx_broadcast_frames;\n\tu32 rx_multicast_frames;\n\tu32 rx_pause_frames;\n\tu32 rx_crc_errors;\n\tu32 rx_align_code_errors;\n\tu32 rx_oversized_frames;\n\tu32 rx_jabber_frames;\n\tu32 rx_undersized_frames;\n\tu32 rx_fragments;\n\tu32 overrun_type4;\n\tu32 overrun_type5;\n\tu32 rx_bytes;\n\tu32 tx_good_frames;\n\tu32 tx_broadcast_frames;\n\tu32 tx_multicast_frames;\n\tu32 tx_pause_frames;\n\tu32 tx_deferred_frames;\n\tu32 tx_collision_frames;\n\tu32 tx_single_coll_frames;\n\tu32 tx_mult_coll_frames;\n\tu32 tx_excessive_collisions;\n\tu32 tx_late_collisions;\n\tu32 tx_underrun;\n\tu32 tx_carrier_sense_errors;\n\tu32 tx_bytes;\n\tu32 tx_64byte_frames;\n\tu32 tx_65_to_127byte_frames;\n\tu32 tx_128_to_255byte_frames;\n\tu32 tx_256_to_511byte_frames;\n\tu32 tx_512_to_1023byte_frames;\n\tu32 tx_1024byte_frames;\n\tu32 net_bytes;\n\tu32 rx_sof_overruns;\n\tu32 rx_mof_overruns;\n\tu32 rx_dma_overruns;\n};\n\nstruct xgmac_dma_desc {\n\t__le32 flags;\n\t__le32 buf_size;\n\t__le32 buf1_addr;\n\t__le32 buf2_addr;\n\t__le32 ext_status;\n\t__le32 res[3];\n};\n\nstruct xgmac_extra_stats {\n\tlong unsigned int tx_jabber;\n\tlong unsigned int tx_frame_flushed;\n\tlong unsigned int tx_payload_error;\n\tlong unsigned int tx_ip_header_error;\n\tlong unsigned int tx_local_fault;\n\tlong unsigned int tx_remote_fault;\n\tlong unsigned int rx_watchdog;\n\tlong unsigned int rx_da_filter_fail;\n\tlong unsigned int rx_payload_error;\n\tlong unsigned int rx_ip_header_error;\n\tlong unsigned int tx_process_stopped;\n\tlong unsigned int rx_buf_unav;\n\tlong unsigned int rx_process_stopped;\n\tlong unsigned int tx_early;\n\tlong unsigned int fatal_bus_error;\n};\n\nstruct xgmac_priv {\n\tstruct xgmac_dma_desc *dma_rx;\n\tstruct sk_buff **rx_skbuff;\n\tunsigned int rx_tail;\n\tunsigned int rx_head;\n\tstruct xgmac_dma_desc *dma_tx;\n\tstruct sk_buff **tx_skbuff;\n\tunsigned int tx_head;\n\tunsigned int tx_tail;\n\tint tx_irq_cnt;\n\tvoid *base;\n\tunsigned int dma_buf_sz;\n\tdma_addr_t dma_rx_phy;\n\tdma_addr_t dma_tx_phy;\n\tstruct net_device *dev;\n\tstruct device *device;\n\tlong: 32;\n\tstruct napi_struct napi;\n\tint max_macs;\n\tstruct xgmac_extra_stats xstats;\n\tspinlock_t stats_lock;\n\tint pmt_irq;\n\tchar rx_pause;\n\tchar tx_pause;\n\tint wolopts;\n\tstruct work_struct tx_timeout_work;\n};\n\nstruct xgmac_stats {\n\tchar stat_string[32];\n\tint stat_offset;\n\tbool is_reg;\n};\n\nstruct xgpio_instance {\n\tstruct gpio_chip gc;\n\tvoid *regs;\n\tlong unsigned int map[2];\n\tlong unsigned int state[2];\n\tlong unsigned int last_irq_read[2];\n\tlong unsigned int dir[2];\n\traw_spinlock_t gpio_lock;\n\tint irq;\n\tlong unsigned int enable[2];\n\tlong unsigned int rising_edge[2];\n\tlong unsigned int falling_edge[2];\n\tstruct clk *clk;\n};\n\nstruct xhci_bus_state {\n\tlong unsigned int bus_suspended;\n\tlong unsigned int next_statechange;\n\tu32 port_c_suspend;\n\tu32 suspended_ports;\n\tu32 port_remote_wakeup;\n\tlong unsigned int resuming_ports;\n};\n\nstruct xhci_bw_info {\n\tunsigned int ep_interval;\n\tunsigned int mult;\n\tunsigned int num_packets;\n\tunsigned int max_packet_size;\n\tunsigned int max_esit_payload;\n\tunsigned int type;\n};\n\nstruct xhci_cap_regs {\n\t__le32 hc_capbase;\n\t__le32 hcs_params1;\n\t__le32 hcs_params2;\n\t__le32 hcs_params3;\n\t__le32 hcc_params;\n\t__le32 db_off;\n\t__le32 run_regs_off;\n\t__le32 hcc_params2;\n};\n\nstruct xhci_container_ctx;\n\nstruct xhci_command {\n\tstruct xhci_container_ctx *in_ctx;\n\tu32 status;\n\tu32 comp_param;\n\tint slot_id;\n\tstruct completion *completion;\n\tunion xhci_trb *command_trb;\n\tstruct list_head cmd_list;\n\tunsigned int timeout_ms;\n};\n\nstruct xhci_container_ctx {\n\tunsigned int type;\n\tint size;\n\tu8 *bytes;\n\tdma_addr_t dma;\n};\n\nstruct xhci_erst_entry;\n\nstruct xhci_erst {\n\tstruct xhci_erst_entry *entries;\n\tunsigned int num_entries;\n\tdma_addr_t erst_dma_addr;\n};\n\nstruct xhci_hcd;\n\nstruct xhci_dbc {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tstruct xhci_hcd *xhci;\n\tstruct dbc_regs *regs;\n\tstruct xhci_ring *ring_evt;\n\tstruct xhci_ring *ring_in;\n\tstruct xhci_ring *ring_out;\n\tstruct xhci_erst erst;\n\tstruct xhci_container_ctx *ctx;\n\tstruct dbc_str_descs *str_descs;\n\tdma_addr_t str_descs_dma;\n\tsize_t str_descs_size;\n\tstruct dbc_str str;\n\tu16 idVendor;\n\tu16 idProduct;\n\tu16 bcdDevice;\n\tu8 bInterfaceProtocol;\n\tenum dbc_state state;\n\tstruct delayed_work event_work;\n\tunsigned int poll_interval;\n\tlong unsigned int xfer_timestamp;\n\tunsigned int resume_required: 1;\n\tstruct dbc_ep eps[2];\n\tconst struct dbc_driver *driver;\n\tvoid *priv;\n};\n\nstruct xhci_device_context_array {\n\t__le64 dev_context_ptrs[256];\n\tdma_addr_t dma;\n\tlong: 32;\n};\n\nstruct xhci_doorbell_array {\n\t__le32 doorbell[256];\n};\n\nstruct xhci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n};\n\nstruct xhci_ep_ctx {\n\t__le32 ep_info;\n\t__le32 ep_info2;\n\t__le64 deq;\n\t__le32 tx_info;\n\t__le32 reserved[3];\n};\n\nstruct xhci_stream_info;\n\nstruct xhci_ep_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *show_ring;\n\tunsigned int stream_id;\n};\n\nstruct xhci_erst_entry {\n\t__le64 seg_addr;\n\t__le32 seg_size;\n\t__le32 rsvd;\n};\n\nstruct xhci_event_cmd {\n\t__le64 cmd_trb;\n\t__le32 status;\n\t__le32 flags;\n};\n\nstruct xhci_file_map {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct xhci_generic_trb {\n\t__le32 field[4];\n};\n\nstruct xhci_port;\n\nstruct xhci_hub {\n\tstruct xhci_port **ports;\n\tunsigned int num_ports;\n\tstruct usb_hcd *hcd;\n\tstruct xhci_bus_state bus_state;\n\tu8 maj_rev;\n\tu8 min_rev;\n};\n\nstruct xhci_op_regs;\n\nstruct xhci_run_regs;\n\nstruct xhci_interrupter;\n\nstruct xhci_scratchpad;\n\nstruct xhci_virt_device;\n\nstruct xhci_root_port_bw_info;\n\nstruct xhci_port_cap;\n\nstruct xhci_hcd {\n\tstruct usb_hcd *main_hcd;\n\tstruct usb_hcd *shared_hcd;\n\tstruct xhci_cap_regs *cap_regs;\n\tstruct xhci_op_regs *op_regs;\n\tstruct xhci_run_regs *run_regs;\n\tstruct xhci_doorbell_array *dba;\n\t__u32 hcs_params2;\n\t__u32 hcs_params3;\n\t__u32 hcc_params;\n\t__u32 hcc_params2;\n\tspinlock_t lock;\n\tu16 hci_version;\n\tu16 max_interrupters;\n\tu8 max_slots;\n\tu8 max_ports;\n\tu32 imod_interval;\n\tu32 page_size;\n\tint nvecs;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\tstruct reset_control *reset;\n\tstruct xhci_device_context_array *dcbaa;\n\tstruct xhci_interrupter **interrupters;\n\tstruct xhci_ring *cmd_ring;\n\tunsigned int cmd_ring_state;\n\tstruct list_head cmd_list;\n\tunsigned int cmd_ring_reserved_trbs;\n\tstruct delayed_work cmd_timer;\n\tstruct completion cmd_ring_stop_completion;\n\tstruct xhci_command *current_cmd;\n\tstruct xhci_scratchpad *scratchpad;\n\tstruct mutex mutex;\n\tstruct xhci_virt_device *devs[256];\n\tstruct xhci_root_port_bw_info *rh_bw;\n\tstruct dma_pool *device_pool;\n\tstruct dma_pool *segment_pool;\n\tstruct dma_pool *small_streams_pool;\n\tstruct dma_pool *port_bw_pool;\n\tstruct dma_pool *medium_streams_pool;\n\tunsigned int xhc_state;\n\tlong unsigned int run_graceperiod;\n\tstruct s3_save s3;\n\tlong long unsigned int quirks;\n\tunsigned int num_active_eps;\n\tunsigned int limit_active_eps;\n\tstruct xhci_port *hw_ports;\n\tstruct xhci_hub usb2_rhub;\n\tstruct xhci_hub usb3_rhub;\n\tunsigned int hw_lpm_support: 1;\n\tunsigned int broken_suspend: 1;\n\tunsigned int allow_single_roothub: 1;\n\tstruct xhci_port_cap *port_caps;\n\tunsigned int num_port_caps;\n\tstruct timer_list comp_mode_recovery_timer;\n\tu32 port_status_u0;\n\tu16 test_mode;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_slots;\n\tstruct list_head regset_list;\n\tvoid *dbc;\n\tlong unsigned int priv[0];\n};\n\nstruct xhci_input_control_ctx {\n\t__le32 drop_flags;\n\t__le32 add_flags;\n\t__le32 rsvd2[6];\n};\n\nstruct xhci_intr_reg;\n\nstruct xhci_interrupter {\n\tstruct xhci_ring *event_ring;\n\tstruct xhci_erst erst;\n\tstruct xhci_intr_reg *ir_set;\n\tunsigned int intr_num;\n\tbool ip_autoclear;\n\tu32 isoc_bei_interval;\n\tu32 s3_iman;\n\tu32 s3_imod;\n\tu32 s3_erst_size;\n\tlong: 32;\n\tu64 s3_erst_base;\n\tu64 s3_erst_dequeue;\n};\n\nstruct xhci_interval_bw {\n\tunsigned int num_packets;\n\tstruct list_head endpoints;\n\tunsigned int overhead[3];\n};\n\nstruct xhci_interval_bw_table {\n\tunsigned int interval0_esit_payload;\n\tstruct xhci_interval_bw interval_bw[16];\n\tunsigned int bw_used;\n\tunsigned int ss_bw_in;\n\tunsigned int ss_bw_out;\n};\n\nstruct xhci_intr_reg {\n\t__le32 iman;\n\t__le32 imod;\n\t__le32 erst_size;\n\t__le32 rsvd;\n\t__le64 erst_base;\n\t__le64 erst_dequeue;\n};\n\nstruct xhci_link_trb {\n\t__le64 segment_ptr;\n\t__le32 intr_target;\n\t__le32 control;\n};\n\nstruct xhci_port_regs {\n\t__le32 portsc;\n\t__le32 portpmsc;\n\t__le32 portli;\n\t__le32 porthlmpc;\n};\n\nstruct xhci_op_regs {\n\t__le32 command;\n\t__le32 status;\n\t__le32 page_size;\n\t__le32 reserved1;\n\t__le32 reserved2;\n\t__le32 dev_notification;\n\t__le64 cmd_ring;\n\t__le32 reserved3[4];\n\t__le64 dcbaa_ptr;\n\t__le32 config_reg;\n\t__le32 reserved4[241];\n\tstruct xhci_port_regs port_regs[0];\n};\n\nstruct xhci_plat_priv {\n\tconst char *firmware_name;\n\tlong: 32;\n\tlong long unsigned int quirks;\n\tbool power_lost;\n\tunsigned int sideband_at_suspend: 1;\n\tvoid (*plat_start)(struct usb_hcd *);\n\tint (*init_quirk)(struct usb_hcd *);\n\tint (*suspend_quirk)(struct usb_hcd *);\n\tint (*resume_quirk)(struct usb_hcd *);\n\tint (*post_resume_quirk)(struct usb_hcd *);\n};\n\nstruct xhci_port {\n\tstruct xhci_port_regs *port_reg;\n\tint hw_portnum;\n\tint hcd_portnum;\n\tstruct xhci_hub *rhub;\n\tstruct xhci_port_cap *port_cap;\n\tunsigned int lpm_incapable: 1;\n\tlong unsigned int resume_timestamp;\n\tbool rexit_active;\n\tint slot_id;\n\tstruct completion rexit_done;\n\tstruct completion u3exit_done;\n};\n\nstruct xhci_port_cap {\n\tu32 *psi;\n\tu8 psi_count;\n\tu8 psi_uid_count;\n\tu8 maj_rev;\n\tu8 min_rev;\n\tu32 protocol_caps;\n};\n\nstruct xhci_regset {\n\tchar name[32];\n\tstruct debugfs_regset32 regset;\n\tsize_t nregs;\n\tstruct list_head list;\n};\n\nstruct xhci_ring {\n\tstruct xhci_segment *first_seg;\n\tstruct xhci_segment *last_seg;\n\tunion xhci_trb *enqueue;\n\tstruct xhci_segment *enq_seg;\n\tunion xhci_trb *dequeue;\n\tstruct xhci_segment *deq_seg;\n\tstruct list_head td_list;\n\tu32 cycle_state;\n\tunsigned int stream_id;\n\tunsigned int num_segs;\n\tunsigned int num_trbs_free;\n\tunsigned int bounce_buf_len;\n\tenum xhci_ring_type type;\n\tu32 old_trb_comp_code;\n\tstruct xarray *trb_address_map;\n};\n\nstruct xhci_root_port_bw_info {\n\tstruct list_head tts;\n\tunsigned int num_active_tts;\n\tstruct xhci_interval_bw_table bw_table;\n};\n\nstruct xhci_run_regs {\n\t__le32 microframe_index;\n\t__le32 rsvd[7];\n\tstruct xhci_intr_reg ir_set[1024];\n};\n\nstruct xhci_scratchpad {\n\tu64 *sp_array;\n\tdma_addr_t sp_dma;\n\tvoid **sp_buffers;\n};\n\nstruct xhci_segment {\n\tunion xhci_trb *trbs;\n\tstruct xhci_segment *next;\n\tunsigned int num;\n\tdma_addr_t dma;\n\tdma_addr_t bounce_dma;\n\tvoid *bounce_buf;\n\tunsigned int bounce_offs;\n\tunsigned int bounce_len;\n};\n\nstruct xhci_virt_ep;\n\nstruct xhci_sideband_event;\n\nstruct xhci_sideband {\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_virt_device *vdev;\n\tstruct xhci_virt_ep *eps[31];\n\tstruct xhci_interrupter *ir;\n\tenum xhci_sideband_type type;\n\tstruct mutex mutex;\n\tstruct usb_interface *intf;\n\tint (*notify_client)(struct usb_interface *, struct xhci_sideband_event *);\n};\n\nstruct xhci_sideband_event {\n\tenum xhci_sideband_notify_type type;\n\tvoid *evt_data;\n};\n\nstruct xhci_slot_ctx {\n\t__le32 dev_info;\n\t__le32 dev_info2;\n\t__le32 tt_info;\n\t__le32 dev_state;\n\t__le32 reserved[4];\n};\n\nstruct xhci_slot_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_ep_priv *eps[31];\n\tstruct xhci_virt_device *dev;\n};\n\nstruct xhci_stream_ctx {\n\t__le64 stream_ring;\n\t__le32 reserved[2];\n};\n\nstruct xhci_stream_info {\n\tstruct xhci_ring **stream_rings;\n\tunsigned int num_streams;\n\tstruct xhci_stream_ctx *stream_ctx_array;\n\tunsigned int num_stream_ctxs;\n\tdma_addr_t ctx_array_dma;\n\tstruct xarray trb_address_map;\n\tstruct xhci_command *free_streams_command;\n};\n\nstruct xhci_transfer_event {\n\t__le64 buffer;\n\t__le32 transfer_len;\n\t__le32 flags;\n};\n\nunion xhci_trb {\n\tstruct xhci_link_trb link;\n\tstruct xhci_transfer_event trans_event;\n\tstruct xhci_event_cmd event_cmd;\n\tstruct xhci_generic_trb generic;\n};\n\nstruct xhci_tt_bw_info {\n\tstruct list_head tt_list;\n\tint slot_id;\n\tint ttport;\n\tstruct xhci_interval_bw_table bw_table;\n\tint active_eps;\n};\n\nstruct xhci_virt_ep {\n\tstruct xhci_virt_device *vdev;\n\tunsigned int ep_index;\n\tstruct xhci_ring *ring;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *new_ring;\n\tunsigned int err_count;\n\tunsigned int ep_state;\n\tstruct list_head cancelled_td_list;\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_segment *queued_deq_seg;\n\tunion xhci_trb *queued_deq_ptr;\n\tbool skip;\n\tstruct xhci_bw_info bw_info;\n\tstruct list_head bw_endpoint_list;\n\tlong unsigned int stop_time;\n\tint next_frame_id;\n\tbool use_extended_tbc;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xhci_virt_device {\n\tint slot_id;\n\tstruct usb_device *udev;\n\tstruct xhci_container_ctx *out_ctx;\n\tstruct xhci_container_ctx *in_ctx;\n\tstruct xhci_virt_ep eps[31];\n\tstruct xhci_port *rhub_port;\n\tstruct xhci_interval_bw_table *bw_table;\n\tstruct xhci_tt_bw_info *tt_info;\n\tlong unsigned int flags;\n\tu16 current_mel;\n\tvoid *debugfs_private;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xiic_i2c {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct completion completion;\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *tx_msg;\n\tstruct mutex lock;\n\tunsigned int tx_pos;\n\tunsigned int nmsgs;\n\tstruct i2c_msg *rx_msg;\n\tint rx_pos;\n\tenum xiic_endian endianness;\n\tstruct clk *clk;\n\tenum xilinx_i2c_state state;\n\tbool singlemaster;\n\tbool dynamic;\n\tbool prev_msg_tx;\n\tu32 quirks;\n\tbool smbus_block_read;\n\tlong unsigned int input_clk;\n\tunsigned int i2c_clk;\n\tbool atomic;\n\tspinlock_t atomic_lock;\n\tenum xilinx_i2c_state atomic_xfer_state;\n\tlong: 32;\n};\n\nstruct xiic_i2c_platform_data {\n\tu8 num_devices;\n\tconst struct i2c_board_info *devices;\n};\n\nstruct xiic_version_data {\n\tu32 quirks;\n};\n\nstruct xilinx_axidma_desc_hw {\n\tu32 next_desc;\n\tu32 next_desc_msb;\n\tu32 buf_addr;\n\tu32 buf_addr_msb;\n\tu32 reserved1;\n\tu32 reserved2;\n\tu32 control;\n\tu32 status;\n\tu32 app[5];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xilinx_axidma_tx_segment {\n\tstruct xilinx_axidma_desc_hw hw;\n\tstruct list_head node;\n\tdma_addr_t phys;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xilinx_aximcdma_desc_hw {\n\tu32 next_desc;\n\tu32 next_desc_msb;\n\tu32 buf_addr;\n\tu32 buf_addr_msb;\n\tu32 rsvd;\n\tu32 control;\n\tu32 status;\n\tu32 sideband_status;\n\tu32 app[5];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xilinx_aximcdma_tx_segment {\n\tstruct xilinx_aximcdma_desc_hw hw;\n\tstruct list_head node;\n\tdma_addr_t phys;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xilinx_cdma_desc_hw {\n\tu32 next_desc;\n\tu32 next_desc_msb;\n\tu32 src_addr;\n\tu32 src_addr_msb;\n\tu32 dest_addr;\n\tu32 dest_addr_msb;\n\tu32 control;\n\tu32 status;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xilinx_cdma_tx_segment {\n\tstruct xilinx_cdma_desc_hw hw;\n\tstruct list_head node;\n\tdma_addr_t phys;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xilinx_vdma_config {\n\tint frm_dly;\n\tint gen_lock;\n\tint master;\n\tint frm_cnt_en;\n\tint park;\n\tint park_frm;\n\tint coalesc;\n\tint delay;\n\tint reset;\n\tint ext_fsync;\n\tbool vflip_en;\n};\n\nstruct xilinx_dma_device;\n\nstruct xilinx_dma_chan {\n\tstruct xilinx_dma_device *xdev;\n\tu32 ctrl_offset;\n\tu32 desc_offset;\n\tspinlock_t lock;\n\tstruct list_head pending_list;\n\tstruct list_head active_list;\n\tstruct list_head done_list;\n\tstruct list_head free_seg_list;\n\tstruct dma_chan common;\n\tstruct dma_pool *desc_pool;\n\tstruct device *dev;\n\tint irq;\n\tint id;\n\tenum dma_transfer_direction direction;\n\tint num_frms;\n\tbool has_sg;\n\tbool cyclic;\n\tbool genlock;\n\tbool err;\n\tbool idle;\n\tbool terminating;\n\tstruct tasklet_struct tasklet;\n\tstruct xilinx_vdma_config config;\n\tbool flush_on_fsync;\n\tu32 desc_pendingcount;\n\tbool ext_addr;\n\tu32 desc_submitcount;\n\tstruct xilinx_axidma_tx_segment *seg_v;\n\tstruct xilinx_aximcdma_tx_segment *seg_mv;\n\tdma_addr_t seg_p;\n\tstruct xilinx_axidma_tx_segment *cyclic_seg_v;\n\tdma_addr_t cyclic_seg_p;\n\tvoid (*start_transfer)(struct xilinx_dma_chan *);\n\tint (*stop_transfer)(struct xilinx_dma_chan *);\n\tu16 tdest;\n\tbool has_vflip;\n\tu8 irq_delay;\n};\n\nstruct xilinx_dma_config {\n\tenum xdma_ip_type dmatype;\n\tint (*clk_init)(struct platform_device *, struct clk **, struct clk **, struct clk **, struct clk **, struct clk **);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tconst int max_channels;\n};\n\nstruct xilinx_dma_device {\n\tvoid *regs;\n\tstruct device *dev;\n\tstruct dma_device common;\n\tstruct xilinx_dma_chan *chan[32];\n\tu32 flush_on_fsync;\n\tbool ext_addr;\n\tstruct platform_device *pdev;\n\tconst struct xilinx_dma_config *dma_config;\n\tstruct clk *axi_clk;\n\tstruct clk *tx_clk;\n\tstruct clk *txs_clk;\n\tstruct clk *rx_clk;\n\tstruct clk *rxs_clk;\n\tu32 s2mm_chan_id;\n\tu32 mm2s_chan_id;\n\tu32 max_buffer_len;\n\tbool has_axistream_connected;\n};\n\nstruct xilinx_dma_tx_descriptor {\n\tstruct dma_async_tx_descriptor async_tx;\n\tstruct list_head segments;\n\tstruct list_head node;\n\tbool cyclic;\n\tbool err;\n\tu32 residue;\n};\n\nstruct xilinx_spi {\n\tstruct spi_bitbang bitbang;\n\tstruct completion done;\n\tvoid *regs;\n\tint irq;\n\tbool force_irq;\n\tu8 *rx_ptr;\n\tconst u8 *tx_ptr;\n\tu8 bytes_per_word;\n\tint buffer_size;\n\tu32 cs_inactive;\n\tunsigned int (*read_fn)(void *);\n\tvoid (*write_fn)(u32, void *);\n};\n\nstruct xilinx_vdma_desc_hw {\n\tu32 next_desc;\n\tu32 pad1;\n\tu32 buf_addr;\n\tu32 buf_addr_msb;\n\tu32 vsize;\n\tu32 hsize;\n\tu32 stride;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xilinx_vdma_tx_segment {\n\tstruct xilinx_vdma_desc_hw hw;\n\tstruct list_head node;\n\tdma_addr_t phys;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tlong unsigned int *bitmap;\n\tstruct page *page;\n\tlong unsigned int vaddr;\n};\n\nstruct xprt_addr {\n\tconst char *addr;\n\tstruct callback_head rcu;\n};\n\nstruct xprt_create;\n\nstruct xprt_class {\n\tstruct list_head list;\n\tint ident;\n\tstruct rpc_xprt * (*setup)(struct xprt_create *);\n\tstruct module *owner;\n\tchar name[32];\n\tconst char *netid[0];\n};\n\nstruct xprt_create {\n\tint ident;\n\tstruct net *net;\n\tstruct sockaddr *srcaddr;\n\tstruct sockaddr *dstaddr;\n\tsize_t addrlen;\n\tconst char *servername;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rpc_xprt_switch *bc_xps;\n\tunsigned int flags;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tlong: 32;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n\tlong: 32;\n};\n\nstruct xsk_tx_metadata {\n\t__u64 flags;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 csum_start;\n\t\t\t__u16 csum_offset;\n\t\t\tlong: 32;\n\t\t\t__u64 launch_time;\n\t\t} request;\n\t\tstruct {\n\t\t\t__u64 tx_timestamp;\n\t\t} completion;\n\t};\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xspi_platform_data {\n\tstruct spi_board_info *devices;\n\tu8 num_devices;\n\tu8 num_chipselect;\n\tu8 bits_per_word;\n\tbool force_irq;\n};\n\nstruct xwdt_device {\n\tvoid *base;\n\tu32 wdt_interval;\n\tspinlock_t spinlock;\n\tstruct watchdog_device xilinx_wdt_wdd;\n\tstruct clk *clk;\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n\tlong: 32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t\tlong: 32;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tlong: 32;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n\tlong: 32;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\nstruct zstd_ctx {\n\tzstd_cctx *cctx;\n\tzstd_dctx *dctx;\n\tsize_t wksp_size;\n\tzstd_parameters params;\n\tlong: 32;\n\tu8 wksp[0];\n};\n\nstruct zynq_platform_data;\n\nstruct zynq_gpio {\n\tstruct gpio_chip chip;\n\tvoid *base_addr;\n\tstruct clk *clk;\n\tint irq;\n\tconst struct zynq_platform_data *p_data;\n\tstruct gpio_regs___2 context;\n\tspinlock_t dirlock;\n};\n\nstruct zynq_pctrl_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tconst unsigned int npins;\n};\n\nstruct zynq_pinmux_function;\n\nstruct zynq_pinctrl {\n\tstruct pinctrl_dev *pctrl;\n\tstruct regmap *syscon;\n\tu32 pctrl_offset;\n\tconst struct zynq_pctrl_group *groups;\n\tunsigned int ngroups;\n\tconst struct zynq_pinmux_function *funcs;\n\tunsigned int nfuncs;\n};\n\nstruct zynq_pinmux_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n\tunsigned int mux_val;\n\tu32 mux;\n\tu32 mux_mask;\n\tu8 mux_shift;\n};\n\nstruct zynq_platform_data {\n\tconst char *label;\n\tu32 quirks;\n\tu16 ngpio;\n\tint max_bank;\n\tint bank_min[6];\n\tint bank_max[6];\n};\n\nstruct zynq_pll {\n\tstruct clk_hw hw;\n\tvoid *pll_ctrl;\n\tvoid *pll_status;\n\tspinlock_t *lock;\n\tu8 lockbit;\n};\n\nstruct zynq_reset_data {\n\tstruct regmap *slcr;\n\tstruct reset_controller_dev rcdev;\n\tu32 offset;\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef void (*RecordEvents_f)(Fingerprint *, const void *, size_t);\n\ntypedef size_t (*ZSTD_BlockCompressor_f)(ZSTD_MatchState_t *, SeqStore_t *, U32 *, const void *, size_t);\n\ntypedef size_t (*ZSTD_SequenceCopier_f)(ZSTD_CCtx *, ZSTD_SequencePosition *, const ZSTD_Sequence * const, size_t, const void *, size_t, ZSTD_ParamSwitch_e);\n\ntypedef U32 (*ZSTD_getAllMatchesFn)(ZSTD_match_t *, ZSTD_MatchState_t *, U32 *, const BYTE *, const BYTE *, const U32 *, const U32, const U32);\n\ntypedef int (*ZSTD_match4Found)(const BYTE *, const BYTE *, U32, U32);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u32 (*bpf_prog_run_fn)(const struct bpf_prog *, const void *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_d_path)(const struct path *, char *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_pe)(struct bpf_perf_event_data_kern *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_trace)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_branch_snapshot)(void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_task)(void);\n\ntypedef u64 (*btf_bpf_get_current_task_btf)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_func_ip_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_pe)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_sleepable)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_pe)(struct bpf_perf_event_data_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack_sleepable)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_probe_read_compat)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_printf_btf)(struct seq_file *, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_get_xfrm_state)(struct sk_buff *, u32, struct bpf_xfrm_state *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_snprintf_btf)(char *, u32, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_task_pt_regs)(struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_vprintk)(char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_get_func_arg)(void *, u32, u64 *);\n\ntypedef u64 (*btf_get_func_arg_cnt)(void *);\n\ntypedef u64 (*btf_get_func_ret)(void *, u64 *);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_suspend)(void *, ktime_t, int);\n\ntypedef void (*btf_trace_alloc_vmap_area)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_arm_event)(void *, const struct cper_sec_proc_arm *, const u8 *, const u32, const u8 *, const u32, const u8 *, const u32, u8, int);\n\ntypedef void (*btf_trace_ata_bmdma_setup)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_start)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_status)(void *, struct ata_port *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_stop)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_about_to_do)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_done)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy)(void *, struct ata_device *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy_qc)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_exec_command)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_softreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_softreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_port_freeze)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_port_thaw)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_qc_complete_done)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_failed)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_internal)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_issue)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_prep)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_sff_flush_pio_task)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_sff_hsm_command_complete)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_hsm_state)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_sff_port_intr)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_slave_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_slave_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_slave_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_std_sched_eh)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_tf_load)(void *, struct ata_port *, const struct ata_taskfile *);\n\ntypedef void (*btf_trace_atapi_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_atapi_send_cdb)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, struct dirty_throttle_control *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_bl_ext_tree_prepare_commit)(void *, int, size_t, u64, bool);\n\ntypedef void (*btf_trace_bl_pr_key_reg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_reg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_bl_pr_key_unreg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_unreg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_blk_zone_append_update_request_bio)(void *, struct request *);\n\ntypedef void (*btf_trace_blk_zone_wplug_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_blkdev_zone_mgmt)(void *, struct bio *, sector_t);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_io_done)(void *, struct request *);\n\ntypedef void (*btf_trace_block_io_start)(void *, struct request *);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_error)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_merge)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_split)(void *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\ntypedef void (*btf_trace_bpf_trace_printk)(void *, const char *);\n\ntypedef void (*btf_trace_bpf_trigger_tp)(void *, int);\n\ntypedef void (*btf_trace_bpf_xdp_link_attach_failed)(void *, const char *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_cache_entry_expired)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_make_negative)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_no_listener)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_upcall)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_update)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cap_capable)(void *, const struct cred *, struct user_namespace *, const struct user_namespace *, int, int);\n\ntypedef void (*btf_trace_cdev_update)(void *, struct thermal_cooling_device *, long unsigned int);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rstat_lock_contended)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_locked)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_unlock)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_ci_complete_td)(void *, struct ci_hw_ep *, struct ci_hw_req *, struct td_node *);\n\ntypedef void (*btf_trace_ci_log)(void *, struct ci_hdrc *, struct va_format *);\n\ntypedef void (*btf_trace_ci_prepare_td)(void *, struct ci_hw_ep *, struct ci_hw_req *, struct td_node *);\n\ntypedef void (*btf_trace_clk_disable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_disable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_enable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_enable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_rate_request_done)(void *, struct clk_rate_request *);\n\ntypedef void (*btf_trace_clk_rate_request_start)(void *, struct clk_rate_request *);\n\ntypedef void (*btf_trace_clk_set_duty_cycle)(void *, struct clk_core *, struct clk_duty *);\n\ntypedef void (*btf_trace_clk_set_duty_cycle_complete)(void *, struct clk_core *, struct clk_duty *);\n\ntypedef void (*btf_trace_clk_set_max_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_min_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_parent)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_parent_complete)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_phase)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_phase_complete)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_rate_complete)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_rate_range)(void *, struct clk_core *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_clk_unprepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_unprepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_cma_alloc_busy_retry)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_alloc_finish)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_cma_alloc_start)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_release)(void *, const char *, long unsigned int, const struct page *, long unsigned int);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_contention_begin)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_contention_end)(void *, void *, int);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_idle_miss)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_csd_function_entry)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_function_exit)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_queue_cpu)(void *, const unsigned int, long unsigned int, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_ctime_ns_xchg)(void *, struct inode *, u32, u32, u32);\n\ntypedef void (*btf_trace_ctime_xchg_skip)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_dc_readl)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_dc_writel)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_devfreq_frequency)(void *, struct devfreq *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_devfreq_monitor)(void *, struct devfreq *);\n\ntypedef void (*btf_trace_device_pm_callback_end)(void *, struct device *, int);\n\ntypedef void (*btf_trace_device_pm_callback_start)(void *, struct device *, const char *, int);\n\ntypedef void (*btf_trace_devlink_health_recover_aborted)(void *, const struct devlink *, const char *, bool, u64);\n\ntypedef void (*btf_trace_devlink_health_report)(void *, const struct devlink *, const char *, const char *);\n\ntypedef void (*btf_trace_devlink_health_reporter_state_update)(void *, const struct devlink *, const char *, bool);\n\ntypedef void (*btf_trace_devlink_hwerr)(void *, const struct devlink *, int, const char *);\n\ntypedef void (*btf_trace_devlink_hwmsg)(void *, const struct devlink *, bool, long unsigned int, const u8 *, size_t);\n\ntypedef void (*btf_trace_devlink_trap_report)(void *, const struct devlink *, struct sk_buff *, const struct devlink_trap_metadata *);\n\ntypedef void (*btf_trace_devres_log)(void *, struct device *, const char *, void *, const char *, size_t);\n\ntypedef void (*btf_trace_disk_zone_wplug_add_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_dma_alloc)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt_err)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_buf_detach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_dynamic_attach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_export)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_fd)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_get)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_mmap)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_mmap_internal)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_put)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_free)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_map_phys)(void *, struct device *, phys_addr_t, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg_err)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_sync_sg_for_cpu)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_sg_for_device)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_cpu)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_device)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_unmap_phys)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_unmap_sg)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dpaux_readl)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_dpaux_writel)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_dql_stall_detected)(void *, short unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_drm_vblank_event)(void *, int, unsigned int, ktime_t, bool);\n\ntypedef void (*btf_trace_drm_vblank_event_delivered)(void *, struct drm_file *, int, unsigned int);\n\ntypedef void (*btf_trace_drm_vblank_event_queued)(void *, struct drm_file *, int, unsigned int);\n\ntypedef void (*btf_trace_dsi_readl)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_dsi_writel)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_dwc3_alloc_request)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_complete_trb)(void *, struct dwc3_ep *, struct dwc3_trb *);\n\ntypedef void (*btf_trace_dwc3_ctrl_req)(void *, struct dwc3 *, struct usb_ctrlrequest *);\n\ntypedef void (*btf_trace_dwc3_ep_dequeue)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_ep_queue)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_event)(void *, u32, struct dwc3 *);\n\ntypedef void (*btf_trace_dwc3_free_request)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_gadget_ep_cmd)(void *, struct dwc3_ep *, unsigned int, struct dwc3_gadget_ep_cmd_params *, int);\n\ntypedef void (*btf_trace_dwc3_gadget_ep_disable)(void *, struct dwc3_ep *);\n\ntypedef void (*btf_trace_dwc3_gadget_ep_enable)(void *, struct dwc3_ep *);\n\ntypedef void (*btf_trace_dwc3_gadget_generic_cmd)(void *, struct dwc3 *, unsigned int, u32, int);\n\ntypedef void (*btf_trace_dwc3_gadget_giveback)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_prepare_trb)(void *, struct dwc3_ep *, struct dwc3_trb *);\n\ntypedef void (*btf_trace_dwc3_readl)(void *, struct dwc3 *, void *, u32, u32);\n\ntypedef void (*btf_trace_dwc3_set_prtcap)(void *, struct dwc3 *, u32);\n\ntypedef void (*btf_trace_dwc3_writel)(void *, struct dwc3 *, void *, u32, u32);\n\ntypedef void (*btf_trace_e1000e_trace_mac_register)(void *, uint32_t);\n\ntypedef void (*btf_trace_edma_fill_tcd)(void *, struct fsl_edma_chan *, void *);\n\ntypedef void (*btf_trace_edma_readb)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_readl)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_readw)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_writeb)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_writel)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_writew)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_error_report_end)(void *, enum error_detector, long unsigned int);\n\ntypedef void (*btf_trace_exit_mmap)(void *, struct mm_struct *);\n\ntypedef void (*btf_trace_ext4_alloc_da_blocks)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_allocate_blocks)(void *, struct ext4_allocation_request *, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_allocate_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_begin_ordered_truncate)(void *, struct inode *, loff_t);\n\ntypedef void (*btf_trace_ext4_collapse_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_da_release_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_reserve_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_update_reserve_space)(void *, struct inode *, int, int);\n\ntypedef void (*btf_trace_ext4_da_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_end)(void *, struct inode *, loff_t, loff_t, struct writeback_control *, int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_start)(void *, struct inode *, loff_t, loff_t, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages_extent)(void *, struct inode *, struct ext4_map_blocks *);\n\ntypedef void (*btf_trace_ext4_discard_blocks)(void *, struct super_block *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_discard_preallocations)(void *, struct inode *, unsigned int);\n\ntypedef void (*btf_trace_ext4_drop_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_error)(void *, struct super_block *, const char *, unsigned int);\n\ntypedef void (*btf_trace_ext4_es_cache_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_exit)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_insert_delayed_extent)(void *, struct inode *, struct extent_status *, bool, bool);\n\ntypedef void (*btf_trace_ext4_es_insert_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_exit)(void *, struct inode *, struct extent_status *, int);\n\ntypedef void (*btf_trace_ext4_es_remove_extent)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_shrink)(void *, struct super_block *, int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_count)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_enter)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_exit)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_enter)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_fastpath)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_handle_unwritten_extents)(void *, struct inode *, struct ext4_map_blocks *, int, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_load_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space_done)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, struct partial_cluster *, __le16);\n\ntypedef void (*btf_trace_ext4_ext_rm_idx)(void *, struct inode *, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_rm_leaf)(void *, struct inode *, ext4_lblk_t, struct ext4_extent *, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_show_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t, short unsigned int);\n\ntypedef void (*btf_trace_ext4_fallocate_enter)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_fallocate_exit)(void *, struct inode *, loff_t, unsigned int, int);\n\ntypedef void (*btf_trace_ext4_fc_cleanup)(void *, journal_t *, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_start)(void *, struct super_block *, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_stop)(void *, struct super_block *, int, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_replay)(void *, struct super_block *, int, int, int, int);\n\ntypedef void (*btf_trace_ext4_fc_replay_scan)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_fc_stats)(void *, struct super_block *);\n\ntypedef void (*btf_trace_ext4_fc_track_create)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_inode)(void *, handle_t *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_link)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_range)(void *, handle_t *, struct inode *, long int, long int, int);\n\ntypedef void (*btf_trace_ext4_fc_track_unlink)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_forget)(void *, struct inode *, int, __u64);\n\ntypedef void (*btf_trace_ext4_free_blocks)(void *, struct inode *, __u64, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_fsmap_high_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_low_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_mapping)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_get_implied_cluster_alloc_exit)(void *, struct super_block *, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_getfsmap_high_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_low_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_mapping)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_insert_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journal_start_inode)(void *, struct inode *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_reserved)(void *, struct super_block *, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_sb)(void *, struct super_block *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journalled_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_lazy_itable_init)(void *, struct super_block *, ext4_group_t);\n\ntypedef void (*btf_trace_ext4_load_inode)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_load_inode_bitmap)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mark_inode_dirty)(void *, struct inode *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_buddy_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_discard_preallocations)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_mb_new_group_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_new_inode_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_group_pa)(void *, struct super_block *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_inode_pa)(void *, struct ext4_prealloc_space *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_mballoc_alloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_discard)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_free)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_prealloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_move_extent_enter)(void *, struct inode *, struct ext4_map_blocks *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_move_extent_exit)(void *, struct inode *, ext4_lblk_t, struct inode *, ext4_lblk_t, unsigned int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_nfs_commit_metadata)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_other_inode_update_time)(void *, struct inode *, ino_t);\n\ntypedef void (*btf_trace_ext4_prefetch_bitmaps)(void *, struct super_block *, ext4_group_t, ext4_group_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_punch_hole)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_read_block_bitmap_load)(void *, struct super_block *, long unsigned int, bool);\n\ntypedef void (*btf_trace_ext4_read_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_release_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_remove_blocks)(void *, struct inode *, struct ext4_extent *, ext4_lblk_t, ext4_fsblk_t, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_request_blocks)(void *, struct ext4_allocation_request *);\n\ntypedef void (*btf_trace_ext4_request_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_shutdown)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_sync_file_enter)(void *, struct file *, int);\n\ntypedef void (*btf_trace_ext4_sync_file_exit)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_sync_fs)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_trim_all_free)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_trim_extent)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_truncate_enter)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_truncate_exit)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_unlink_enter)(void *, struct inode *, struct dentry *);\n\ntypedef void (*btf_trace_ext4_unlink_exit)(void *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_update_sb)(void *, struct super_block *, ext4_fsblk_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_writepages)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_writepages_result)(void *, struct inode *, struct writeback_control *, int, int);\n\ntypedef void (*btf_trace_ext4_zero_range)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ff_layout_commit_error)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_ff_layout_read_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_ff_layout_write_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_fib6_table_lookup)(void *, const struct net *, const struct fib6_result *, struct fib6_table *, const struct flowi6 *);\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_fill_mg_cmtime)(void *, struct inode *, struct timespec64 *, struct timespec64 *);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_fl_getdevinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, char *);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_folio_wait_writeback)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_free_vmap_area_noflush)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_gpio_direction)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_gpio_value)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_gpu_mem_total)(void *, uint32_t, uint32_t, uint64_t);\n\ntypedef void (*btf_trace_guest_halt_poll_ns)(void *, bool, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_handshake_cancel)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_busy)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_none)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cmd_accept)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_accept_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_complete)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_destruct)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_notify_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_submit)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_submit_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_hdmi_readl)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_hdmi_writel)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_host1x_cdma_begin)(void *, const char *);\n\ntypedef void (*btf_trace_host1x_cdma_end)(void *, const char *);\n\ntypedef void (*btf_trace_host1x_cdma_push)(void *, const char *, u32, u32);\n\ntypedef void (*btf_trace_host1x_cdma_push_gather)(void *, const char *, struct host1x_bo *, u32, u32, void *);\n\ntypedef void (*btf_trace_host1x_cdma_push_wide)(void *, const char *, u32, u32, u32, u32);\n\ntypedef void (*btf_trace_host1x_channel_open)(void *, const char *);\n\ntypedef void (*btf_trace_host1x_channel_release)(void *, const char *);\n\ntypedef void (*btf_trace_host1x_channel_submit)(void *, const char *, u32, u32, u32, u32);\n\ntypedef void (*btf_trace_host1x_channel_submit_complete)(void *, const char *, int, u32);\n\ntypedef void (*btf_trace_host1x_channel_submitted)(void *, const char *, u32, u32);\n\ntypedef void (*btf_trace_host1x_syncpt_load_min)(void *, u32, u32);\n\ntypedef void (*btf_trace_host1x_syncpt_wait_check)(void *, struct host1x_bo *, u32, u32, u32, u32);\n\ntypedef void (*btf_trace_host1x_wait_cdma)(void *, const char *, u32);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_setup)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hw_pressure_update)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_hwmon_attr_show)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_hwmon_attr_show_string)(void *, int, const char *, const char *);\n\ntypedef void (*btf_trace_hwmon_attr_store)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_i2c_read)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_reply)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_result)(void *, const struct i2c_adapter *, int, int);\n\ntypedef void (*btf_trace_i2c_slave)(void *, const struct i2c_client *, enum i2c_slave_event, __u8 *, int);\n\ntypedef void (*btf_trace_i2c_write)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_icc_set_bw)(void *, struct icc_path *, struct icc_node *, int, u32, u32);\n\ntypedef void (*btf_trace_icc_set_bw_end)(void *, struct icc_path *, int);\n\ntypedef void (*btf_trace_icmp_send)(void *, const struct sk_buff *, int, int);\n\ntypedef void (*btf_trace_inet_sk_error_report)(void *, const struct sock *);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_inode_set_ctime_to_ts)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, struct io_ring_ctx *, void *, struct io_uring_cqe *);\n\ntypedef void (*btf_trace_io_uring_cqe_overflow)(void *, void *, long long unsigned int, s32, u32, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_local_work_run)(void *, void *, int, unsigned int);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, struct io_kiocb *, int, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, struct io_kiocb *, bool);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, long int);\n\ntypedef void (*btf_trace_io_uring_req_failed)(void *, const struct io_uring_sqe *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_short_write)(void *, void *, u64, u64, u64);\n\ntypedef void (*btf_trace_io_uring_submit_req)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_task_work_run)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_iomap_add_to_ioend)(void *, struct inode *, u64, unsigned int, struct iomap *);\n\ntypedef void (*btf_trace_iomap_dio_complete)(void *, struct kiocb *, int, ssize_t);\n\ntypedef void (*btf_trace_iomap_dio_invalidate_fail)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_dio_rw_begin)(void *, struct kiocb *, struct iov_iter *, unsigned int, size_t);\n\ntypedef void (*btf_trace_iomap_dio_rw_queued)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_invalidate_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_iter)(void *, struct iomap_iter *, const void *, long unsigned int);\n\ntypedef void (*btf_trace_iomap_iter_dstmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_iter_srcmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_release_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_writeback_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_zero_iter)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_ipi_entry)(void *, const char *);\n\ntypedef void (*btf_trace_ipi_exit)(void *, const char *);\n\ntypedef void (*btf_trace_ipi_raise)(void *, const struct cpumask *, const char *);\n\ntypedef void (*btf_trace_ipi_send_cpu)(void *, const unsigned int, long unsigned int, void *);\n\ntypedef void (*btf_trace_ipi_send_cpumask)(void *, const struct cpumask *, long unsigned int, void *);\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_jbd2_checkpoint)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_checkpoint_stats)(void *, dev_t, tid_t, struct transaction_chp_stats_s *);\n\ntypedef void (*btf_trace_jbd2_commit_flushing)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_locking)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_logging)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_drop_transaction)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_end_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_handle_extend)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int);\n\ntypedef void (*btf_trace_jbd2_handle_restart)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_start)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_stats)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int, int, int);\n\ntypedef void (*btf_trace_jbd2_lock_buffer_stall)(void *, dev_t, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_run_stats)(void *, dev_t, tid_t, struct transaction_run_stats_s *);\n\ntypedef void (*btf_trace_jbd2_shrink_checkpoint_list)(void *, journal_t *, tid_t, tid_t, tid_t, long unsigned int, tid_t);\n\ntypedef void (*btf_trace_jbd2_shrink_count)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_enter)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_exit)(void *, journal_t *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_start_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_submit_inode_data)(void *, struct inode *);\n\ntypedef void (*btf_trace_jbd2_update_log_tail)(void *, journal_t *, tid_t, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_write_superblock)(void *, journal_t *, blk_opf_t);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *, enum skb_drop_reason, struct sock *);\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, struct kmem_cache *, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *, const struct kmem_cache *);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, dev_t, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_latency)(void *, dev_t, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, dev_t, const char *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lease *, struct file_lease *);\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ma_op)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_read)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_write)(void *, const char *, struct ma_state *, long unsigned int, void *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_mark_victim)(void *, struct task_struct *, uid_t);\n\ntypedef void (*btf_trace_mc_event)(void *, const unsigned int, const char *, const char *, const int, const u8, const s8, const s8, const s8, long unsigned int, const u8, long unsigned int, const char *);\n\ntypedef void (*btf_trace_mdio_access)(void *, struct mii_bus *, char, u8, unsigned int, u16, int);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_mm_calculate_totalreserve_pages)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, struct compact_control *, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, struct compact_control *, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_fast_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_fault)(void *, struct address_space *, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_get_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_map_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_migrate_pages_start)(void *, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_lowmem_reserve)(void *, struct zone *, struct zone *, long int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_wmarks)(void *, struct zone *);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_clear_hopeless)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_reclaim_fail)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_reclaim_pages)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *);\n\ntypedef void (*btf_trace_mm_vmscan_throttled)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_write_folio)(void *, struct folio *);\n\ntypedef void (*btf_trace_mmap_lock_acquire_returned)(void *, struct mm_struct *, bool, bool);\n\ntypedef void (*btf_trace_mmap_lock_released)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmap_lock_start_locking)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmc_request_done)(void *, struct mmc_host *, struct mmc_request *);\n\ntypedef void (*btf_trace_mmc_request_start)(void *, struct mmc_host *, struct mmc_request *);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netlink_extack)(void *, const char *);\n\ntypedef void (*btf_trace_nfs41_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_access)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_bind_conn_to_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_cached_open)(void *, const struct nfs4_state *);\n\ntypedef void (*btf_trace_nfs4_cb_getattr)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_cb_layoutrecall_file)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_offload)(void *, const struct nfs_fh *, const nfs4_stateid *, uint64_t, int, int);\n\ntypedef void (*btf_trace_nfs4_cb_recall)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_seqid_err)(void *, const struct cb_sequenceargs *, __be32);\n\ntypedef void (*btf_trace_nfs4_cb_sequence)(void *, const struct cb_sequenceargs *, const struct cb_sequenceres *, __be32);\n\ntypedef void (*btf_trace_nfs4_clone)(void *, const struct inode *, const struct inode *, const struct nfs42_clone_args *, int);\n\ntypedef void (*btf_trace_nfs4_close)(void *, const struct nfs4_state *, const struct nfs_closeargs *, const struct nfs_closeres *, int);\n\ntypedef void (*btf_trace_nfs4_close_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_commit)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_copy)(void *, const struct inode *, const struct inode *, const struct nfs42_copy_args *, const struct nfs42_copy_res *, const struct nl4_server *, int);\n\ntypedef void (*btf_trace_nfs4_copy_notify)(void *, const struct inode *, const struct nfs42_copy_notify_args *, const struct nfs42_copy_notify_res *, int);\n\ntypedef void (*btf_trace_nfs4_create_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_deallocate)(void *, const struct inode *, const struct nfs42_falloc_args *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn_exit)(void *, const struct nfs4_delegreturnargs *, const struct nfs4_delegreturnres *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_clientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_detach_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_deviceid_free)(void *, const struct nfs_client *, const struct nfs4_deviceid *);\n\ntypedef void (*btf_trace_nfs4_exchange_id)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_fallocate)(void *, const struct inode *, const struct nfs42_falloc_args *, int);\n\ntypedef void (*btf_trace_nfs4_find_deviceid)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_fsinfo)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_get_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_get_fs_locations)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_get_lock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_getattr)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_getdeviceinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_getxattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_layoutcommit)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layouterror)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutget)(void *, const struct nfs_open_context *, const struct pnfs_layout_range *, const struct pnfs_layout_range *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn_on_close)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutstats)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_listxattr)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_llseek)(void *, const struct inode *, const struct nfs42_seek_args *, const struct nfs42_seek_res *, int);\n\ntypedef void (*btf_trace_nfs4_lookup)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_lookup_root)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_lookupp)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_map_gid_to_group)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_group_to_gid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_name_to_uid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_uid_to_name)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_mkdir)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_mknod)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_offload_cancel)(void *, const struct nfs42_offload_status_args *, int);\n\ntypedef void (*btf_trace_nfs4_offload_status)(void *, const struct nfs42_offload_status_args *, int);\n\ntypedef void (*btf_trace_nfs4_open_expired)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_file)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_reclaim)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_skip)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_commit_ds)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_readdir)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_readlink)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_complete)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_remove)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_removexattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_rename)(void *, const struct inode *, const struct qstr *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_renew)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_renew_async)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_secinfo)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_sequence)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_sequence_done)(void *, const struct nfs4_session *, const struct nfs4_sequence_res *);\n\ntypedef void (*btf_trace_nfs4_set_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_set_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_set_lock)(void *, const struct file_lock *, const struct nfs4_state *, const nfs4_stateid *, int, int);\n\ntypedef void (*btf_trace_nfs4_setattr)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid_confirm)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setup_sequence)(void *, const struct nfs4_session *, const struct nfs4_sequence_args *);\n\ntypedef void (*btf_trace_nfs4_setxattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_state_lock_reclaim)(void *, const struct nfs4_state *, const struct nfs4_lock_state *);\n\ntypedef void (*btf_trace_nfs4_state_mgr)(void *, const struct nfs_client *);\n\ntypedef void (*btf_trace_nfs4_state_mgr_failed)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_symlink)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_test_delegation_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_lock_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_open_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_trunked_exchange_id)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_unlock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_filehandle)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_operation)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_status)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs_access_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_access_exit)(void *, const struct inode *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readahead)(void *, const struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_nfs_aop_readahead_done)(void *, const struct inode *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readpage)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_aop_readpage_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_async_rename_done)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_atomic_open_enter)(void *, const struct inode *, const struct nfs_open_context *, unsigned int);\n\ntypedef void (*btf_trace_nfs_atomic_open_exit)(void *, const struct inode *, const struct nfs_open_context *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_cb_badprinc)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_cb_no_clp)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_commit_done)(void *, const struct rpc_task *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_commit_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_comp_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_create_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_create_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_delegation_need_return)(void *, const struct nfs_delegation *);\n\ntypedef void (*btf_trace_nfs_direct_commit_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_resched_write)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_completion)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_reschedule_io)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_schedule_iovec)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_do_writepage)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_fh_to_dentry)(void *, const struct super_block *, const struct nfs_fh *, u64, int);\n\ntypedef void (*btf_trace_nfs_file_read)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_file_write)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_fsync_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_fsync_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_getattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_getattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_initiate_commit)(void *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_initiate_read)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_initiate_write)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_invalidate_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_launder_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_link_enter)(void *, const struct inode *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_link_exit)(void *, const struct inode *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_local_open_fh)(void *, const struct nfs_fh *, fmode_t, int);\n\ntypedef void (*btf_trace_nfs_lookup_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_mkdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mkdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mknod_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mknod_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mount_assign)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_nfs_mount_option)(void *, const struct fs_parameter *);\n\ntypedef void (*btf_trace_nfs_mount_path)(void *, const char *);\n\ntypedef void (*btf_trace_nfs_pgio_error)(void *, const struct nfs_pgio_header *, int, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readdir_force_readdirplus)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_readdir_invalidate_cache_range)(void *, const struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_lookup)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate_failed)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readpage_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_readpage_short)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_remove_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_remove_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_rename_enter)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rename_exit)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_rmdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rmdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_set_cache_invalid)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_set_inode_stale)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_sillyrename_unlink)(void *, const struct nfs_unlinkdata *, int);\n\ntypedef void (*btf_trace_nfs_size_grow)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate_folio)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_update)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_wcc)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_symlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_symlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_try_to_update_request)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_try_to_update_request_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_unlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_unlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_update_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_update_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_begin)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_begin_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_end)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_end_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_writeback_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_writeback_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_writeback_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_writepage_setup)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_writepages)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writepages_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_xdr_bad_filehandle)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nfs_xdr_status)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nlmclnt_grant)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_lock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_test)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_unlock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_non_standard_event)(void *, const guid_t *, const guid_t *, const char *, const u8, const u8 *, const u32);\n\ntypedef void (*btf_trace_notifier_register)(void *, void *);\n\ntypedef void (*btf_trace_notifier_run)(void *, void *);\n\ntypedef void (*btf_trace_notifier_unregister)(void *, void *);\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_optee_invoke_fn_begin)(void *, struct optee_rpc_param *);\n\ntypedef void (*btf_trace_optee_invoke_fn_end)(void *, struct optee_rpc_param *, struct arm_smccc_res *);\n\ntypedef void (*btf_trace_page_cache_async_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_ra_order)(void *, struct inode *, long unsigned int, struct file_ra_state *);\n\ntypedef void (*btf_trace_page_cache_ra_unbounded)(void *, struct inode *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_sync_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_pool_release)(void *, const struct page_pool *, s32, u32, u32);\n\ntypedef void (*btf_trace_page_pool_state_hold)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_state_release)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_update_nid)(void *, const struct page_pool *, int);\n\ntypedef void (*btf_trace_pci_hp_event)(void *, const char *, const char *, const int);\n\ntypedef void (*btf_trace_pcie_link_event)(void *, struct pci_bus *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pelt_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_pelt_dl_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_hw_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_irq_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_rt_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, long unsigned int, bool, bool, size_t, size_t, void *, int, void *, size_t, gfp_t);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pmap_register)(void *, u32, u32, int, short unsigned int);\n\ntypedef void (*btf_trace_pnfs_ds_connect)(void *, char *, int);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_get_mirror_count)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_read)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_write)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_update_layout)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *, enum pnfs_update_layout_reason);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_power_domain_target)(void *, const char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_psci_domain_idle_enter)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_psci_domain_idle_exit)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_purge_vmap_area_lazy)(void *, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pwm_apply)(void *, struct pwm_device *, const struct pwm_state *, int);\n\ntypedef void (*btf_trace_pwm_get)(void *, struct pwm_device *, const struct pwm_state *, int);\n\ntypedef void (*btf_trace_pwm_read_waveform)(void *, struct pwm_device *, void *, int);\n\ntypedef void (*btf_trace_pwm_round_waveform_fromhw)(void *, struct pwm_device *, const void *, struct pwm_waveform *, int);\n\ntypedef void (*btf_trace_pwm_round_waveform_tohw)(void *, struct pwm_device *, const struct pwm_waveform *, void *, int);\n\ntypedef void (*btf_trace_pwm_write_waveform)(void *, struct pwm_device *, const void *, int);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_enqueue)(void *, struct Qdisc *, const struct netdev_queue *, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_invoke_kvfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_segcb_stats)(void *, struct rcu_segcblist *, const char *);\n\ntypedef void (*btf_trace_rcu_sr_normal)(void *, const char *, struct callback_head *, const char *);\n\ntypedef void (*btf_trace_rcu_stall_warning)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_watching)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_regcache_drop_region)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regcache_sync)(void *, struct regmap *, const char *, const char *);\n\ntypedef void (*btf_trace_regmap_async_complete_done)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_start)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_io_complete)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_bulk_read)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_bulk_write)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_cache_bypass)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_cache_only)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_hw_read_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_read_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_reg_read)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read_cache)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_write)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regulator_bypass_disable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_disable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_enable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_enable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_disable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_disable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable_delay)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_set_voltage)(void *, const char *, int, int);\n\ntypedef void (*btf_trace_regulator_set_voltage_complete)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_rpc__auth_tooweak)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__bad_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__garbage_args)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__proc_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__stale_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__unparsable)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_callhdr)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_verifier)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_buf_alloc)(void *, const struct rpc_task *, int);\n\ntypedef void (*btf_trace_rpc_call_rpcerror)(void *, const struct rpc_task *, int, int);\n\ntypedef void (*btf_trace_rpc_call_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_clnt_clone_err)(void *, const struct rpc_clnt *, int);\n\ntypedef void (*btf_trace_rpc_clnt_free)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_killall)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_new)(void *, const struct rpc_clnt *, const struct rpc_xprt *, const struct rpc_create_args *);\n\ntypedef void (*btf_trace_rpc_clnt_new_err)(void *, const char *, const char *, int);\n\ntypedef void (*btf_trace_rpc_clnt_release)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt_err)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_shutdown)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_connect_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_request)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_retry_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_socket_close)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_connect)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_error)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_nospace)(void *, const struct rpc_rqst *, const struct sock_xprt *);\n\ntypedef void (*btf_trace_rpc_socket_reset_connection)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_shutdown)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_state_change)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_stats_latency)(void *, const struct rpc_task *, ktime_t, ktime_t, ktime_t);\n\ntypedef void (*btf_trace_rpc_task_begin)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_call_done)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_complete)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_end)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_run_action)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_signalled)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sleep)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_task_sync_sleep)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sync_wake)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_timeout)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_wakeup)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_timeout_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_tls_not_started)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_tls_unavailable)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_xdr_alignment)(void *, const struct xdr_stream *, size_t, unsigned int);\n\ntypedef void (*btf_trace_rpc_xdr_overflow)(void *, const struct xdr_stream *, size_t);\n\ntypedef void (*btf_trace_rpc_xdr_recvfrom)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_reply_pages)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_sendto)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpcb_bind_version_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_getport)(void *, const struct rpc_clnt *, const struct rpc_task *, unsigned int);\n\ntypedef void (*btf_trace_rpcb_prog_unavail_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_register)(void *, u32, u32, const char *, const char *);\n\ntypedef void (*btf_trace_rpcb_setport)(void *, const struct rpc_task *, int, short unsigned int);\n\ntypedef void (*btf_trace_rpcb_timeout_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unreachable_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unrecognized_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unregister)(void *, u32, u32, const char *);\n\ntypedef void (*btf_trace_rpcgss_bad_seqno)(void *, const struct rpc_task *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_context)(void *, u32, long unsigned int, long unsigned int, unsigned int, unsigned int, const u8 *);\n\ntypedef void (*btf_trace_rpcgss_createauth)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rpcgss_ctx_destroy)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_ctx_init)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_get_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_import_ctx)(void *, int);\n\ntypedef void (*btf_trace_rpcgss_need_reencode)(void *, const struct rpc_task *, u32, bool);\n\ntypedef void (*btf_trace_rpcgss_oid_to_mech)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_seqno)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_svc_accept_upcall)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_authenticate)(void *, const struct svc_rqst *, const struct rpc_gss_wire_cred *);\n\ntypedef void (*btf_trace_rpcgss_svc_get_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_bad)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_large)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_low)(void *, const struct svc_rqst *, u32, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_seen)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_unwrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_unwrap_failed)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_upcall_msg)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_upcall_result)(void *, u32, int);\n\ntypedef void (*btf_trace_rpcgss_update_slack)(void *, const struct rpc_task *, const struct rpc_auth *);\n\ntypedef void (*btf_trace_rpcgss_verify_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_wrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpm_idle)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_resume)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_return_int)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_rpm_status)(void *, struct device *, enum rpm_status);\n\ntypedef void (*btf_trace_rpm_suspend)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_usage)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int);\n\ntypedef void (*btf_trace_rtc_alarm_irq_enable)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_freq)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_state)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_read_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_read_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_set_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_timer_dequeue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_enqueue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_fired)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sched_compute_energy_tp)(void *, struct task_struct *, int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_sched_cpu_capacity_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_sched_entry_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_exit_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_ext_bypass_lb)(void *, __u32, __u32, __u32, __u32, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_sched_ext_dump)(void *, const char *);\n\ntypedef void (*btf_trace_sched_ext_event)(void *, const char *, __s64);\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_end)(void *, struct kthread_work *, kthread_work_func_t);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_start)(void *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_kthread_work_queue_work)(void *, struct kthread_worker *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_overutilized_tp)(void *, struct root_domain *, bool);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_prepare_exec)(void *, struct task_struct *, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_set_need_resched_tp)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *, unsigned int);\n\ntypedef void (*btf_trace_sched_update_nr_running_tp)(void *, struct rq *, int);\n\ntypedef void (*btf_trace_sched_util_est_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_sched_util_est_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_scmi_fc_call)(void *, u8, u8, u32, u32, u32);\n\ntypedef void (*btf_trace_scmi_msg_dump)(void *, int, u8, u8, u8, unsigned char *, u16, int, void *, size_t);\n\ntypedef void (*btf_trace_scmi_rx_done)(void *, int, u8, u8, u16, u8);\n\ntypedef void (*btf_trace_scmi_xfer_begin)(void *, int, u8, u8, u16, bool, int);\n\ntypedef void (*btf_trace_scmi_xfer_end)(void *, int, u8, u8, u16, int, int);\n\ntypedef void (*btf_trace_scmi_xfer_response_wait)(void *, int, u8, u8, u16, u32, bool);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\ntypedef void (*btf_trace_set_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sk_data_ready)(void *, const struct sock *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_smbus_read)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int);\n\ntypedef void (*btf_trace_smbus_reply)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *, int);\n\ntypedef void (*btf_trace_smbus_result)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, int);\n\ntypedef void (*btf_trace_smbus_write)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *);\n\ntypedef void (*btf_trace_smp2p_negotiate)(void *, const struct device *, unsigned int);\n\ntypedef void (*btf_trace_smp2p_notify_in)(void *, struct smp2p_entry *, long unsigned int, u32);\n\ntypedef void (*btf_trace_smp2p_ssr_ack)(void *, const struct device *);\n\ntypedef void (*btf_trace_smp2p_update_bits)(void *, struct smp2p_entry *, u32, u32);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_recv_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_sock_send_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\ntypedef void (*btf_trace_sor_readl)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_sor_writel)(void *, struct device *, unsigned int, u32);\n\ntypedef void (*btf_trace_spi_controller_busy)(void *, struct spi_controller *);\n\ntypedef void (*btf_trace_spi_controller_idle)(void *, struct spi_controller *);\n\ntypedef void (*btf_trace_spi_mem_start_op)(void *, struct spi_mem *, const struct spi_mem_op *);\n\ntypedef void (*btf_trace_spi_mem_stop_op)(void *, struct spi_mem *, const struct spi_mem_op *);\n\ntypedef void (*btf_trace_spi_message_done)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_message_start)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_message_submit)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_set_cs)(void *, struct spi_device *, bool);\n\ntypedef void (*btf_trace_spi_setup)(void *, struct spi_device *, int);\n\ntypedef void (*btf_trace_spi_transfer_start)(void *, struct spi_message *, struct spi_transfer *);\n\ntypedef void (*btf_trace_spi_transfer_stop)(void *, struct spi_message *, struct spi_transfer *);\n\ntypedef void (*btf_trace_spmi_cmd)(void *, u8, u8, int);\n\ntypedef void (*btf_trace_spmi_read_begin)(void *, u8, u8, u16);\n\ntypedef void (*btf_trace_spmi_read_end)(void *, u8, u8, u16, int, u8, const u8 *);\n\ntypedef void (*btf_trace_spmi_write_begin)(void *, u8, u8, u16, u8, const u8 *);\n\ntypedef void (*btf_trace_spmi_write_end)(void *, u8, u8, u16, int);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_svc_alloc_arg_err)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_svc_authenticate)(void *, const struct svc_rqst *, enum svc_auth_status);\n\ntypedef void (*btf_trace_svc_defer)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_defer_drop)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_queue)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_recv)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_drop)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_noregister)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_pool_thread_noidle)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_running)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_wake)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_process)(void *, const struct svc_rqst *, const char *);\n\ntypedef void (*btf_trace_svc_register)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_replace_page_err)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_send)(void *, const struct svc_rqst *, int);\n\ntypedef void (*btf_trace_svc_stats_latency)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_tls_not_started)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_start)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_timed_out)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_unavailable)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_upcall)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_unregister)(void *, const char *, const u32, int);\n\ntypedef void (*btf_trace_svc_xdr_recvfrom)(void *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xdr_sendto)(void *, __be32, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xprt_accept)(void *, const struct svc_xprt *, const char *);\n\ntypedef void (*btf_trace_svc_xprt_close)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_create_err)(void *, const char *, const char *, struct sockaddr *, size_t, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_dequeue)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_xprt_detach)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_enqueue)(void *, const struct svc_xprt *, long unsigned int);\n\ntypedef void (*btf_trace_svc_xprt_free)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_no_write_space)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svcsock_accept_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_data_ready)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_free)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_getpeername_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_marker)(void *, const struct svc_xprt *, __be32);\n\ntypedef void (*btf_trace_svcsock_new)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_tcp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_eagain)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_short)(void *, const struct svc_xprt *, u32, u32);\n\ntypedef void (*btf_trace_svcsock_tcp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_state)(void *, const struct svc_xprt *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_udp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_write_space)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_task_prctl_unknown)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef void (*btf_trace_tasklet_entry)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tasklet_exit)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tcp_ao_handshake_failure)(void *, const struct sock *, const struct sk_buff *, const __u8, const __u8, const __u8);\n\ntypedef void (*btf_trace_tcp_bad_csum)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_cong_state_set)(void *, struct sock *, const u8);\n\ntypedef void (*btf_trace_tcp_cwnd_reduction_tp)(void *, const struct sock *, int, int, int);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_hash_ao_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_bad_header)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_mismatch)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_unexpected)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *, const enum sk_rst_reason);\n\ntypedef void (*btf_trace_tcp_sendmsg_locked)(void *, const struct sock *, const struct msghdr *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tegra_dma_complete_cb)(void *, struct dma_chan *, int, void *);\n\ntypedef void (*btf_trace_tegra_dma_isr)(void *, struct dma_chan *, int);\n\ntypedef void (*btf_trace_tegra_dma_tx_status)(void *, struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\ntypedef void (*btf_trace_test_pages_isolated)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_thermal_power_cpu_get_power_simple)(void *, int, u32);\n\ntypedef void (*btf_trace_thermal_power_cpu_limit)(void *, const struct cpumask *, unsigned int, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_power_devfreq_get_power)(void *, struct thermal_cooling_device *, struct devfreq_dev_status *, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_power_devfreq_limit)(void *, struct thermal_cooling_device *, long unsigned int, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_temperature)(void *, struct thermal_zone_device *);\n\ntypedef void (*btf_trace_thermal_zone_trip)(void *, struct thermal_zone_device *, int, enum thermal_trip_type);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_timer_base_idle)(void *, bool, unsigned int);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_tls_alert_recv)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_alert_send)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_contenttype)(void *, const struct sock *, unsigned char);\n\ntypedef void (*btf_trace_tmigr_connect_child_parent)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_connect_cpu_parent)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_active)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_available)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_unavailable)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_group_set)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_active)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_inactive)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_handle_remote)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_handle_remote_cpu)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_update_events)(void *, struct tmigr_group *, struct tmigr_group *, union tmigr_state, union tmigr_state, u64);\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_usb_alloc_dev)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_usb_ep_alloc_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_clear_halt)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_dequeue)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_disable)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_enable)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_fifo_flush)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_fifo_status)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_free_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_queue)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_set_halt)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_set_maxpacket_limit)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_set_wedge)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_gadget_activate)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_clear_selfpowered)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_connect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_deactivate)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_disconnect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_frame_number)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_giveback_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_remote_wakeup)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_selfpowered)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_state)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_connect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_disconnect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_draw)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_wakeup)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_set_device_state)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_watchdog_ping)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_set_timeout)(void *, struct watchdog_device *, unsigned int, int);\n\ntypedef void (*btf_trace_watchdog_start)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_stop)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_dirty_folio)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, long unsigned int, int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int, struct xdp_cpumap_stats *);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xhci_add_endpoint)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctx)(void *, struct xhci_hcd *, struct xhci_container_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_stream_info_ctx)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_alloc_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_dbc_alloc_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_free_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_gadget_ep_queue)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_giveback_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_queue_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbg_address)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_cancel_urb)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_context_change)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_init)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_quirks)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_reset_ep)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_ring_expansion)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_discover_or_reset_device)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_get_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_cmd_addr_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_config_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_disable_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_stream)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_handle_cmd_stop_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_command)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_hub_status_data)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_inc_deq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_inc_enq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_portsc_writel)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_queue_trb)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_ring_alloc)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_ep_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_ring_expansion)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_free)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_host_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_setup_addressable_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_stop_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_urb_dequeue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_enqueue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_giveback)(void *, struct urb *);\n\ntypedef void (*btf_trace_xprt_connect)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_create)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_destroy)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_auto)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_done)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_force)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_get_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_lookup_rqst)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_ping)(void *, const struct rpc_xprt *, int);\n\ntypedef void (*btf_trace_xprt_put_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_reserve_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_retransmit)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_timer)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_transmit)(void *, const struct rpc_rqst *, int);\n\ntypedef void (*btf_trace_xs_data_ready)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xs_stream_read_data)(void *, struct rpc_xprt *, ssize_t, size_t);\n\ntypedef void (*btf_trace_xs_stream_read_request)(void *, struct sock_xprt *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\ntypedef struct mtd_info *cfi_cmdset_fn_t(struct map_info *, int);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef long unsigned int (*clk_calc_rate)(struct clk_hw *, long unsigned int, int);\n\ntypedef void (*clock_access_fn)(struct timespec64 *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef void (*companion_fn)(struct pci_dev *, struct usb_hcd *, struct pci_dev *, struct usb_hcd *);\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\ntypedef int (*copy_fn_t)(void *, const void *, u32, struct task_struct *);\n\ntypedef long unsigned int (*count_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef int (*dbg_leaf_callback)(struct ubifs_info *, struct ubifs_zbranch *, void *);\n\ntypedef int (*dbg_znode_callback)(struct ubifs_info *, struct ubifs_znode *, void *);\n\ntypedef void detailed_cb(const struct detailed_timing *, void *);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int devlink_chunk_fill_t(void *, u8 *, u32, u64, struct netlink_ext_ack *);\n\ntypedef int devlink_nl_dump_one_func_t(struct sk_buff *, struct devlink *, struct netlink_callback *, int);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef void (*drm_crtc_set_lut_func)(struct drm_crtc *, unsigned int, u16, u16, u16);\n\ntypedef bool (*drm_vblank_get_scanout_position_func)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\ntypedef int (*efi_memattr_perm_setter)(struct mm_struct *, efi_memory_desc_t *, bool);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\ntypedef void ext4_update_sb_callback(struct ext4_sb_info *, struct ext4_super_block *, const void *);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, struct mm_struct *);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef struct irq_chip * (*gpio_get_irq_chip_cb_t)(unsigned int);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef void (*harden_branch_predictor_fn_t)(void);\n\ntypedef bool (*hid_usage_cmp_t)(struct hid_usage *, unsigned int, unsigned int);\n\ntypedef size_t (*huf_compress_f)(void *, size_t, const void *, size_t, unsigned int, unsigned int, void *, size_t, HUF_CElt *, HUF_repeat *, int);\n\ntypedef const struct iio_mount_matrix *iio_get_mount_matrix_t(const struct iio_dev *, const struct iio_chan_spec *);\n\ntypedef u32 inet6_ehashfn_t(const struct net *, const struct in6_addr *, const u16, const struct in6_addr *, const __be16);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef initcall_t initcall_entry_t;\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef int (*ioctl_fn)(struct file *, struct autofs_sb_info *, struct autofs_dev_ioctl *);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *, const struct inet6_skb_parm *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef struct its_collection * (*its_cmd_builder_t)(struct its_node *, struct its_cmd_block *, struct its_cmd_desc *);\n\ntypedef struct its_vpe * (*its_cmd_vbuilder_t)(struct its_node *, struct its_cmd_block *, struct its_cmd_desc *);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef void (*mapped_f)(struct perf_event *, struct mm_struct *);\n\ntypedef int mh_filter_t(struct sock *, struct sk_buff *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*nlm_host_match_fn_t)(void *, struct nlm_host *);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef struct gpio_desc * (*of_find_gpio_quirk)(struct device_node *, const char *, unsigned int, enum of_gpio_flags *);\n\ntypedef void (*of_init_fn_1)(struct device_node *);\n\ntypedef int (*of_init_fn_1_ret)(struct device_node *);\n\ntypedef int (*of_init_fn_2)(struct device_node *, struct device_node *);\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef void (*pci_parity_check_fn_t)(struct pci_dev *);\n\ntypedef int (*pcie_callback_t)(struct pcie_device *);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\ntypedef int perf_snapshot_branch_stack_t(struct perf_branch_entry *, unsigned int);\n\ntypedef void (*phys_reset_t)(long unsigned int, bool);\n\ntypedef void (*phys_reset_t___2)(long unsigned int, bool);\n\ntypedef void (*phys_reset_t___3)(long unsigned int);\n\ntypedef int (*platform_irq_probe_t)(struct platform_device *, struct device_node *);\n\ntypedef int (*pm_callback_t)(struct device *);\n\ntypedef struct rt6_info * (*pol_lookup_t)(struct net *, struct fib6_table *, struct flowi6 *, const struct sk_buff *, int);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef long unsigned int psci_fn(long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef int (*psci_initcall_t)(const struct device_node *);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\ntypedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\ntypedef int read_block_fn(void *, u8 *, unsigned int, size_t);\n\ntypedef int (*reservedmem_of_init_fn)(struct reserved_mem *);\n\ntypedef bool (*ring_buffer_cond_fn)(void *);\n\ntypedef void (*rpc_action)(struct rpc_task *);\n\ntypedef int (*rproc_handle_resource_t)(struct rproc *, void *, int, int);\n\ntypedef void (*rtl_generic_fct)(struct rtl8169_private *);\n\ntypedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *, struct phy_device *);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef long unsigned int (*scan_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef void (*set_params_cb)(struct dwc2_hsotg *);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef void tegra124_emc_complete_timing_change_cb___2(struct tegra_emc___3 *, long unsigned int);\n\ntypedef int tegra124_emc_prepare_timing_change_cb___2(struct tegra_emc___3 *, long unsigned int);\n\ntypedef void (*tegra_clk_apply_init_table_func)(void);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef int (*trace_user_buf_copy)(char *, const char *, size_t, void *);\n\ntypedef int (*ubifs_lpt_scan_callback)(struct ubifs_info *, const struct ubifs_lprops *, int, void *);\n\ntypedef struct sk_buff * (*udp_gro_receive_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*uprobe_write_verify_t)(struct page *, long unsigned int, uprobe_opcode_t *, int, void *);\n\ntypedef int (*varsize_frob_t)(struct map_info *, struct flchip *, long unsigned int, int, void *);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);\n\ntypedef struct rpc_xprt * (*xprt_switch_find_xprt_t)(struct rpc_xprt_switch *, const struct rpc_xprt *);\n\ntypedef ZSTD_sequenceProducer_F zstd_sequence_producer_f;\n\nstruct dmem_cgroup_region;\n\nstruct ftrace_regs;\n\ntypedef void *acpi_handle;\n\nstruct acpi_device;\n\nstruct amd5536udc;\n\nstruct audit_buffer;\n\nstruct audit_context;\n\nstruct bpf_iter;\n\nstruct fscrypt_inode_info;\n\nstruct fscrypt_operations;\n\nstruct hugepage_subpool;\n\nstruct io_tlb_pool;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_send_signal_task(struct task_struct *task, int sig, enum pid_type type, u64 value) __weak __ksym;\nextern __u64 *bpf_session_cookie(void *ctx) __weak __ksym;\nextern bool bpf_session_is_return(void *ctx) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_verify_pkcs7_signature(struct bpf_dynptr *data_p, struct bpf_dynptr *sig_p, struct bpf_key *trusted_keyring) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern struct xfrm_state *bpf_xdp_get_xfrm_state(struct xdp_md *ctx, struct bpf_xfrm_state_opts *opts, u32 opts__sz) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void bpf_xdp_xfrm_state_release(struct xfrm_state *x) __weak __ksym;\nextern void crash_kexec(struct pt_regs *regs) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n#pragma clang diagnostic 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wmissing-declarations\"\n#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAUTOP_INVALID = 0,\n\tAUTOP_HDD = 1,\n\tAUTOP_SSD_QD1 = 2,\n\tAUTOP_SSD_DFL = 3,\n\tAUTOP_SSD_FAST = 4,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tAudit_equal = 0,\n\tAudit_not_equal = 1,\n\tAudit_bitmask = 2,\n\tAudit_bittest = 3,\n\tAudit_lt = 4,\n\tAudit_gt = 5,\n\tAudit_le = 6,\n\tAudit_ge = 7,\n\tAudit_bad = 8,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_BPRM_SECUREEXEC = 1,\n};\n\nenum {\n\tBPF_F_CURRENT_NETNS = -1,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\nenum {\n\tBPF_F_SYSCTL_BASE_NAME = 1,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 27,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBPF_WRITE_HDR_TCP_CURRENT_MSS = 1,\n\tBPF_WRITE_HDR_TCP_SYNACK_COOKIE = 2,\n};\n\nenum {\n\tBPF_XFRM_STATE_OPTS_SZ = 36,\n};\n\nenum {\n\tBRCL_EXPOLINE = 0,\n\tBRASL_EXPOLINE = 1,\n};\n\nenum {\n\tBRIDGE_QUERIER_UNSPEC = 0,\n\tBRIDGE_QUERIER_IP_ADDRESS = 1,\n\tBRIDGE_QUERIER_IP_PORT = 2,\n\tBRIDGE_QUERIER_IP_OTHER_TIMER = 3,\n\tBRIDGE_QUERIER_PAD = 4,\n\tBRIDGE_QUERIER_IPV6_ADDRESS = 5,\n\tBRIDGE_QUERIER_IPV6_PORT = 6,\n\tBRIDGE_QUERIER_IPV6_OTHER_TIMER = 7,\n\t__BRIDGE_QUERIER_MAX = 8,\n};\n\nenum {\n\tBRIDGE_XSTATS_UNSPEC = 0,\n\tBRIDGE_XSTATS_VLAN = 1,\n\tBRIDGE_XSTATS_MCAST = 2,\n\tBRIDGE_XSTATS_PAD = 3,\n\tBRIDGE_XSTATS_STP = 4,\n\t__BRIDGE_XSTATS_MAX = 5,\n};\n\nenum {\n\tBR_FDB_LOCAL = 0,\n\tBR_FDB_STATIC = 1,\n\tBR_FDB_STICKY = 2,\n\tBR_FDB_ADDED_BY_USER = 3,\n\tBR_FDB_ADDED_BY_EXT_LEARN = 4,\n\tBR_FDB_OFFLOADED = 5,\n\tBR_FDB_NOTIFY = 6,\n\tBR_FDB_NOTIFY_INACTIVE = 7,\n\tBR_FDB_LOCKED = 8,\n\tBR_FDB_DYNAMIC_LEARNED = 9,\n};\n\nenum {\n\tBR_GROUPFWD_STP = 1,\n\tBR_GROUPFWD_MACPAUSE = 2,\n\tBR_GROUPFWD_LACP = 4,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBR_VLFLAG_PER_PORT_STATS = 1,\n\tBR_VLFLAG_ADDED_BY_SWITCHDEV = 2,\n\tBR_VLFLAG_MCAST_ENABLED = 4,\n\tBR_VLFLAG_GLOBAL_MCAST_ENABLED = 8,\n\tBR_VLFLAG_NEIGH_SUPPRESS_ENABLED = 16,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tBTRFS_FILE_EXTENT_INLINE = 0,\n\tBTRFS_FILE_EXTENT_REG = 1,\n\tBTRFS_FILE_EXTENT_PREALLOC = 2,\n\tBTRFS_NR_FILE_EXTENT_TYPES = 3,\n};\n\nenum {\n\tBTRFS_FS_CLOSING_START = 0,\n\tBTRFS_FS_CLOSING_DONE = 1,\n\tBTRFS_FS_LOG_RECOVERING = 2,\n\tBTRFS_FS_OPEN = 3,\n\tBTRFS_FS_QUOTA_ENABLED = 4,\n\tBTRFS_FS_UPDATE_UUID_TREE_GEN = 5,\n\tBTRFS_FS_CREATING_FREE_SPACE_TREE = 6,\n\tBTRFS_FS_BTREE_ERR = 7,\n\tBTRFS_FS_LOG1_ERR = 8,\n\tBTRFS_FS_LOG2_ERR = 9,\n\tBTRFS_FS_QUOTA_OVERRIDE = 10,\n\tBTRFS_FS_FROZEN = 11,\n\tBTRFS_FS_BALANCE_RUNNING = 12,\n\tBTRFS_FS_RELOC_RUNNING = 13,\n\tBTRFS_FS_CLEANER_RUNNING = 14,\n\tBTRFS_FS_CSUM_IMPL_FAST = 15,\n\tBTRFS_FS_DISCARD_RUNNING = 16,\n\tBTRFS_FS_CLEANUP_SPACE_CACHE_V1 = 17,\n\tBTRFS_FS_FREE_SPACE_TREE_UNTRUSTED = 18,\n\tBTRFS_FS_TREE_MOD_LOG_USERS = 19,\n\tBTRFS_FS_COMMIT_TRANS = 20,\n\tBTRFS_FS_UNFINISHED_DROPS = 21,\n\tBTRFS_FS_NEED_ZONE_FINISH = 22,\n\tBTRFS_FS_NEED_TRANS_COMMIT = 23,\n\tBTRFS_FS_ACTIVE_ZONE_TRACKING = 24,\n\tBTRFS_FS_FEATURE_CHANGED = 25,\n\tBTRFS_FS_UNALIGNED_TREE_BLOCK = 26,\n};\n\nenum {\n\tBTRFS_FS_STATE_REMOUNTING = 0,\n\tBTRFS_FS_STATE_RO = 1,\n\tBTRFS_FS_STATE_TRANS_ABORTED = 2,\n\tBTRFS_FS_STATE_LOG_REPLAY_ABORTED = 3,\n\tBTRFS_FS_STATE_DEV_REPLACING = 4,\n\tBTRFS_FS_STATE_DUMMY_FS_INFO = 5,\n\tBTRFS_FS_STATE_NO_DATA_CSUMS = 6,\n\tBTRFS_FS_STATE_SKIP_META_CSUMS = 7,\n\tBTRFS_FS_STATE_LOG_CLEANUP_ERROR = 8,\n\tBTRFS_FS_STATE_NO_DELAYED_IPUT = 9,\n\tBTRFS_FS_STATE_EMERGENCY_SHUTDOWN = 10,\n\tBTRFS_FS_STATE_COUNT = 11,\n};\n\nenum {\n\tBTRFS_INODE_FLUSH_ON_CLOSE = 0,\n\tBTRFS_INODE_DUMMY = 1,\n\tBTRFS_INODE_IN_DEFRAG = 2,\n\tBTRFS_INODE_HAS_ASYNC_EXTENT = 3,\n\tBTRFS_INODE_NEEDS_FULL_SYNC = 4,\n\tBTRFS_INODE_COPY_EVERYTHING = 5,\n\tBTRFS_INODE_HAS_PROPS = 6,\n\tBTRFS_INODE_SNAPSHOT_FLUSH = 7,\n\tBTRFS_INODE_NO_XATTRS = 8,\n\tBTRFS_INODE_NO_DELALLOC_FLUSH = 9,\n\tBTRFS_INODE_VERITY_IN_PROGRESS = 10,\n\tBTRFS_INODE_FREE_SPACE_INODE = 11,\n\tBTRFS_INODE_NO_CAP_XATTR = 12,\n\tBTRFS_INODE_COW_WRITE_ERROR = 13,\n\tBTRFS_INODE_ROOT_STUB = 14,\n};\n\nenum {\n\tBTRFS_MOUNT_NODATASUM = 1ULL,\n\tBTRFS_MOUNT_NODATACOW = 2ULL,\n\tBTRFS_MOUNT_NOBARRIER = 4ULL,\n\tBTRFS_MOUNT_SSD = 8ULL,\n\tBTRFS_MOUNT_DEGRADED = 16ULL,\n\tBTRFS_MOUNT_COMPRESS = 32ULL,\n\tBTRFS_MOUNT_NOTREELOG = 64ULL,\n\tBTRFS_MOUNT_FLUSHONCOMMIT = 128ULL,\n\tBTRFS_MOUNT_SSD_SPREAD = 256ULL,\n\tBTRFS_MOUNT_NOSSD = 512ULL,\n\tBTRFS_MOUNT_DISCARD_SYNC = 1024ULL,\n\tBTRFS_MOUNT_FORCE_COMPRESS = 2048ULL,\n\tBTRFS_MOUNT_SPACE_CACHE = 4096ULL,\n\tBTRFS_MOUNT_CLEAR_CACHE = 8192ULL,\n\tBTRFS_MOUNT_USER_SUBVOL_RM_ALLOWED = 16384ULL,\n\tBTRFS_MOUNT_ENOSPC_DEBUG = 32768ULL,\n\tBTRFS_MOUNT_AUTO_DEFRAG = 65536ULL,\n\tBTRFS_MOUNT_USEBACKUPROOT = 131072ULL,\n\tBTRFS_MOUNT_SKIP_BALANCE = 262144ULL,\n\tBTRFS_MOUNT_PANIC_ON_FATAL_ERROR = 524288ULL,\n\tBTRFS_MOUNT_RESCAN_UUID_TREE = 1048576ULL,\n\tBTRFS_MOUNT_FRAGMENT_DATA = 2097152ULL,\n\tBTRFS_MOUNT_FRAGMENT_METADATA = 4194304ULL,\n\tBTRFS_MOUNT_FREE_SPACE_TREE = 8388608ULL,\n\tBTRFS_MOUNT_NOLOGREPLAY = 16777216ULL,\n\tBTRFS_MOUNT_REF_VERIFY = 33554432ULL,\n\tBTRFS_MOUNT_DISCARD_ASYNC = 67108864ULL,\n\tBTRFS_MOUNT_IGNOREBADROOTS = 134217728ULL,\n\tBTRFS_MOUNT_IGNOREDATACSUMS = 268435456ULL,\n\tBTRFS_MOUNT_NODISCARD = 536870912ULL,\n\tBTRFS_MOUNT_NOSPACECACHE = 1073741824ULL,\n\tBTRFS_MOUNT_IGNOREMETACSUMS = 2147483648ULL,\n\tBTRFS_MOUNT_IGNORESUPERFLAGS = 4294967296ULL,\n\tBTRFS_MOUNT_REF_TRACKER = 8589934592ULL,\n};\n\nenum {\n\tBTRFS_ORDERED_REGULAR = 0,\n\tBTRFS_ORDERED_NOCOW = 1,\n\tBTRFS_ORDERED_PREALLOC = 2,\n\tBTRFS_ORDERED_COMPRESSED = 3,\n\tBTRFS_ORDERED_DIRECT = 4,\n\tBTRFS_ORDERED_IO_DONE = 5,\n\tBTRFS_ORDERED_COMPLETE = 6,\n\tBTRFS_ORDERED_IOERR = 7,\n\tBTRFS_ORDERED_TRUNCATED = 8,\n\tBTRFS_ORDERED_LOGGED = 9,\n\tBTRFS_ORDERED_LOGGED_CSUM = 10,\n\tBTRFS_ORDERED_PENDING = 11,\n\tBTRFS_ORDERED_ENCODED = 12,\n};\n\nenum {\n\tBTRFS_ROOT_IN_TRANS_SETUP = 0,\n\tBTRFS_ROOT_SHAREABLE = 1,\n\tBTRFS_ROOT_TRACK_DIRTY = 2,\n\tBTRFS_ROOT_IN_RADIX = 3,\n\tBTRFS_ROOT_ORPHAN_ITEM_INSERTED = 4,\n\tBTRFS_ROOT_DEFRAG_RUNNING = 5,\n\tBTRFS_ROOT_FORCE_COW = 6,\n\tBTRFS_ROOT_MULTI_LOG_TASKS = 7,\n\tBTRFS_ROOT_DIRTY = 8,\n\tBTRFS_ROOT_DELETING = 9,\n\tBTRFS_ROOT_DEAD_RELOC_TREE = 10,\n\tBTRFS_ROOT_DEAD_TREE = 11,\n\tBTRFS_ROOT_HAS_LOG_TREE = 12,\n\tBTRFS_ROOT_QGROUP_FLUSHING = 13,\n\tBTRFS_ROOT_ORPHAN_CLEANUP = 14,\n\tBTRFS_ROOT_UNFINISHED_DROP = 15,\n\tBTRFS_ROOT_RESET_LOCKDEP_CLASS = 16,\n};\n\nenum {\n\tBTRFS_SEND_A_UNSPEC = 0,\n\tBTRFS_SEND_A_UUID = 1,\n\tBTRFS_SEND_A_CTRANSID = 2,\n\tBTRFS_SEND_A_INO = 3,\n\tBTRFS_SEND_A_SIZE = 4,\n\tBTRFS_SEND_A_MODE = 5,\n\tBTRFS_SEND_A_UID = 6,\n\tBTRFS_SEND_A_GID = 7,\n\tBTRFS_SEND_A_RDEV = 8,\n\tBTRFS_SEND_A_CTIME = 9,\n\tBTRFS_SEND_A_MTIME = 10,\n\tBTRFS_SEND_A_ATIME = 11,\n\tBTRFS_SEND_A_OTIME = 12,\n\tBTRFS_SEND_A_XATTR_NAME = 13,\n\tBTRFS_SEND_A_XATTR_DATA = 14,\n\tBTRFS_SEND_A_PATH = 15,\n\tBTRFS_SEND_A_PATH_TO = 16,\n\tBTRFS_SEND_A_PATH_LINK = 17,\n\tBTRFS_SEND_A_FILE_OFFSET = 18,\n\tBTRFS_SEND_A_DATA = 19,\n\tBTRFS_SEND_A_CLONE_UUID = 20,\n\tBTRFS_SEND_A_CLONE_CTRANSID = 21,\n\tBTRFS_SEND_A_CLONE_PATH = 22,\n\tBTRFS_SEND_A_CLONE_OFFSET = 23,\n\tBTRFS_SEND_A_CLONE_LEN = 24,\n\tBTRFS_SEND_A_MAX_V1 = 24,\n\tBTRFS_SEND_A_FALLOCATE_MODE = 25,\n\tBTRFS_SEND_A_FILEATTR = 26,\n\tBTRFS_SEND_A_UNENCODED_FILE_LEN = 27,\n\tBTRFS_SEND_A_UNENCODED_LEN = 28,\n\tBTRFS_SEND_A_UNENCODED_OFFSET = 29,\n\tBTRFS_SEND_A_COMPRESSION = 30,\n\tBTRFS_SEND_A_ENCRYPTION = 31,\n\tBTRFS_SEND_A_MAX_V2 = 31,\n\tBTRFS_SEND_A_VERITY_ALGORITHM = 32,\n\tBTRFS_SEND_A_VERITY_BLOCK_SIZE = 33,\n\tBTRFS_SEND_A_VERITY_SALT_DATA = 34,\n\tBTRFS_SEND_A_VERITY_SIG_DATA = 35,\n\tBTRFS_SEND_A_MAX_V3 = 35,\n\t__BTRFS_SEND_A_MAX = 35,\n};\n\nenum {\n\tBTRFS_STAT_CURR = 0,\n\tBTRFS_STAT_PREV = 1,\n\tBTRFS_STAT_NR_ENTRIES = 2,\n};\n\nenum {\n\tBlktrace_setup = 1,\n\tBlktrace_running = 2,\n\tBlktrace_stopped = 3,\n};\n\nenum {\n\tCACHE_SCOPE_NOTEXISTS = 0,\n\tCACHE_SCOPE_PRIVATE = 1,\n\tCACHE_SCOPE_SHARED = 2,\n\tCACHE_SCOPE_RESERVED = 3,\n};\n\nenum {\n\tCACHE_TI_UNIFIED = 0,\n\tCACHE_TI_DATA = 0,\n\tCACHE_TI_INSTRUCTION = 1,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGROUPSTATS_CMD_ATTR_UNSPEC = 0,\n\tCGROUPSTATS_CMD_ATTR_FD = 1,\n\t__CGROUPSTATS_CMD_ATTR_MAX = 2,\n};\n\nenum {\n\tCGROUPSTATS_CMD_UNSPEC = 3,\n\tCGROUPSTATS_CMD_GET = 4,\n\tCGROUPSTATS_CMD_NEW = 5,\n\t__CGROUPSTATS_CMD_MAX = 6,\n};\n\nenum {\n\tCGROUPSTATS_TYPE_UNSPEC = 0,\n\tCGROUPSTATS_TYPE_CGROUP_STATS = 1,\n\t__CGROUPSTATS_TYPE_MAX = 2,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCOST_CTRL = 0,\n\tCOST_MODEL = 1,\n\tNR_COST_CTRL_PARAMS = 2,\n};\n\nenum {\n\tCPU_STATE_STANDBY = 0,\n\tCPU_STATE_CONFIGURED = 1,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 1000,\n\tCRNG_RESEED_INTERVAL = 60000,\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\t__CRYPTOA_MAX = 3,\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCTLREG_SET_BIT = 0,\n\tCTLREG_CLEAR_BIT = 1,\n\tCTLREG_LOAD = 2,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tCTYPE_SEPARATE = 0,\n\tCTYPE_DATA = 1,\n\tCTYPE_INSTRUCTION = 2,\n\tCTYPE_UNIFIED = 3,\n};\n\nenum {\n\tDAD_PROCESS = 0,\n\tDAD_BEGIN = 1,\n\tDAD_ABORT = 2,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEVCONF_FORWARDING = 0,\n\tDEVCONF_HOPLIMIT = 1,\n\tDEVCONF_MTU6 = 2,\n\tDEVCONF_ACCEPT_RA = 3,\n\tDEVCONF_ACCEPT_REDIRECTS = 4,\n\tDEVCONF_AUTOCONF = 5,\n\tDEVCONF_DAD_TRANSMITS = 6,\n\tDEVCONF_RTR_SOLICITS = 7,\n\tDEVCONF_RTR_SOLICIT_INTERVAL = 8,\n\tDEVCONF_RTR_SOLICIT_DELAY = 9,\n\tDEVCONF_USE_TEMPADDR = 10,\n\tDEVCONF_TEMP_VALID_LFT = 11,\n\tDEVCONF_TEMP_PREFERED_LFT = 12,\n\tDEVCONF_REGEN_MAX_RETRY = 13,\n\tDEVCONF_MAX_DESYNC_FACTOR = 14,\n\tDEVCONF_MAX_ADDRESSES = 15,\n\tDEVCONF_FORCE_MLD_VERSION = 16,\n\tDEVCONF_ACCEPT_RA_DEFRTR = 17,\n\tDEVCONF_ACCEPT_RA_PINFO = 18,\n\tDEVCONF_ACCEPT_RA_RTR_PREF = 19,\n\tDEVCONF_RTR_PROBE_INTERVAL = 20,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN = 21,\n\tDEVCONF_PROXY_NDP = 22,\n\tDEVCONF_OPTIMISTIC_DAD = 23,\n\tDEVCONF_ACCEPT_SOURCE_ROUTE = 24,\n\tDEVCONF_MC_FORWARDING = 25,\n\tDEVCONF_DISABLE_IPV6 = 26,\n\tDEVCONF_ACCEPT_DAD = 27,\n\tDEVCONF_FORCE_TLLAO = 28,\n\tDEVCONF_NDISC_NOTIFY = 29,\n\tDEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL = 30,\n\tDEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL = 31,\n\tDEVCONF_SUPPRESS_FRAG_NDISC = 32,\n\tDEVCONF_ACCEPT_RA_FROM_LOCAL = 33,\n\tDEVCONF_USE_OPTIMISTIC = 34,\n\tDEVCONF_ACCEPT_RA_MTU = 35,\n\tDEVCONF_STABLE_SECRET = 36,\n\tDEVCONF_USE_OIF_ADDRS_ONLY = 37,\n\tDEVCONF_ACCEPT_RA_MIN_HOP_LIMIT = 38,\n\tDEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 39,\n\tDEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 40,\n\tDEVCONF_DROP_UNSOLICITED_NA = 41,\n\tDEVCONF_KEEP_ADDR_ON_DOWN = 42,\n\tDEVCONF_RTR_SOLICIT_MAX_INTERVAL = 43,\n\tDEVCONF_SEG6_ENABLED = 44,\n\tDEVCONF_SEG6_REQUIRE_HMAC = 45,\n\tDEVCONF_ENHANCED_DAD = 46,\n\tDEVCONF_ADDR_GEN_MODE = 47,\n\tDEVCONF_DISABLE_POLICY = 48,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN = 49,\n\tDEVCONF_NDISC_TCLASS = 50,\n\tDEVCONF_RPL_SEG_ENABLED = 51,\n\tDEVCONF_RA_DEFRTR_METRIC = 52,\n\tDEVCONF_IOAM6_ENABLED = 53,\n\tDEVCONF_IOAM6_ID = 54,\n\tDEVCONF_IOAM6_ID_WIDE = 55,\n\tDEVCONF_NDISC_EVICT_NOCARRIER = 56,\n\tDEVCONF_ACCEPT_UNTRACKED_NA = 57,\n\tDEVCONF_ACCEPT_RA_MIN_LFT = 58,\n\tDEVCONF_FORCE_FORWARDING = 59,\n\tDEVCONF_MAX = 60,\n};\n\nenum {\n\tDEVLINK_ATTR_STATS_RX_PACKETS = 0,\n\tDEVLINK_ATTR_STATS_RX_BYTES = 1,\n\tDEVLINK_ATTR_STATS_RX_DROPPED = 2,\n\t__DEVLINK_ATTR_STATS_MAX = 3,\n\tDEVLINK_ATTR_STATS_MAX = 2,\n};\n\nenum {\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_IN_PORT = 0,\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_FA_COOKIE = 1,\n};\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDM_IO_ACCOUNTED = 0,\n\tDM_IO_WAS_SPLIT = 1,\n\tDM_IO_BLK_STAT = 2,\n};\n\nenum {\n\tDM_TIO_INSIDE_DM_IO = 0,\n\tDM_TIO_IS_DUPLICATE_BIO = 1,\n};\n\nenum {\n\tDM_VERSION_CMD = 0,\n\tDM_REMOVE_ALL_CMD = 1,\n\tDM_LIST_DEVICES_CMD = 2,\n\tDM_DEV_CREATE_CMD = 3,\n\tDM_DEV_REMOVE_CMD = 4,\n\tDM_DEV_RENAME_CMD = 5,\n\tDM_DEV_SUSPEND_CMD = 6,\n\tDM_DEV_STATUS_CMD = 7,\n\tDM_DEV_WAIT_CMD = 8,\n\tDM_TABLE_LOAD_CMD = 9,\n\tDM_TABLE_CLEAR_CMD = 10,\n\tDM_TABLE_DEPS_CMD = 11,\n\tDM_TABLE_STATUS_CMD = 12,\n\tDM_LIST_VERSIONS_CMD = 13,\n\tDM_TARGET_MSG_CMD = 14,\n\tDM_DEV_SET_GEOMETRY_CMD = 15,\n\tDM_DEV_ARM_POLL_CMD = 16,\n\tDM_GET_TARGET_VERSION_CMD = 17,\n\tDM_MPATH_PROBE_PATHS_CMD = 18,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDQF_INFO_DIRTY_B = 17,\n};\n\nenum {\n\tDQF_ROOT_SQUASH_B = 0,\n\tDQF_SYS_FILE_B = 16,\n\tDQF_PRIVATE = 17,\n};\n\nenum {\n\tDQST_LOOKUPS = 0,\n\tDQST_DROPS = 1,\n\tDQST_READS = 2,\n\tDQST_WRITES = 3,\n\tDQST_CACHE_HITS = 4,\n\tDQST_ALLOC_DQUOTS = 5,\n\tDQST_FREE_DQUOTS = 6,\n\tDQST_SYNCS = 7,\n\t_DQST_DQSTAT_LAST = 8,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tES_NORMAL = 0,\n\tES_ESC = 1,\n\tES_SQUARE = 2,\n\tES_PAREN = 3,\n\tES_GETPARS = 4,\n};\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENTFS_SAVE_MODE = 65536,\n\tEVENTFS_SAVE_UID = 131072,\n\tEVENTFS_SAVE_GID = 262144,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_DISABLED = 32,\n\tEVENT_FILE_FL_TRIGGER_MODE = 64,\n\tEVENT_FILE_FL_TRIGGER_COND = 128,\n\tEVENT_FILE_FL_PID_FILTER = 256,\n\tEVENT_FILE_FL_WAS_ENABLED = 512,\n\tEVENT_FILE_FL_FREED = 1024,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEVENT_TRIGGER_FL_PROBE = 1,\n\tEVENT_TRIGGER_FL_COUNT = 2,\n};\n\nenum {\n\tEXT4_FC_REASON_XATTR = 0,\n\tEXT4_FC_REASON_CROSS_RENAME = 1,\n\tEXT4_FC_REASON_JOURNAL_FLAG_CHANGE = 2,\n\tEXT4_FC_REASON_NOMEM = 3,\n\tEXT4_FC_REASON_SWAP_BOOT = 4,\n\tEXT4_FC_REASON_RESIZE = 5,\n\tEXT4_FC_REASON_RENAME_DIR = 6,\n\tEXT4_FC_REASON_FALLOC_RANGE = 7,\n\tEXT4_FC_REASON_INODE_JOURNAL_DATA = 8,\n\tEXT4_FC_REASON_ENCRYPTED_FILENAME = 9,\n\tEXT4_FC_REASON_MIGRATE = 10,\n\tEXT4_FC_REASON_VERITY = 11,\n\tEXT4_FC_REASON_MOVE_EXT = 12,\n\tEXT4_FC_REASON_MAX = 13,\n};\n\nenum {\n\tEXT4_FC_STATUS_OK = 0,\n\tEXT4_FC_STATUS_INELIGIBLE = 1,\n\tEXT4_FC_STATUS_SKIPPED = 2,\n\tEXT4_FC_STATUS_FAILED = 3,\n};\n\nenum {\n\tEXT4_FLAGS_RESIZING = 0,\n\tEXT4_FLAGS_SHUTDOWN = 1,\n\tEXT4_FLAGS_BDEV_IS_DAX = 2,\n\tEXT4_FLAGS_EMERGENCY_RO = 3,\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nenum {\n\tEXT4_MF_MNTDIR_SAMPLED = 0,\n\tEXT4_MF_FC_INELIGIBLE = 1,\n\tEXT4_MF_JOURNAL_DESTROY = 2,\n};\n\nenum {\n\tEXT4_STATE_NEW = 0,\n\tEXT4_STATE_XATTR = 1,\n\tEXT4_STATE_NO_EXPAND = 2,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 3,\n\tEXT4_STATE_EXT_MIGRATE = 4,\n\tEXT4_STATE_NEWENTRY = 5,\n\tEXT4_STATE_MAY_INLINE_DATA = 6,\n\tEXT4_STATE_EXT_PRECACHED = 7,\n\tEXT4_STATE_LUSTRE_EA_INODE = 8,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 9,\n\tEXT4_STATE_FC_COMMITTING = 10,\n\tEXT4_STATE_FC_FLUSHING_DATA = 11,\n\tEXT4_STATE_ORPHAN_FILE = 12,\n};\n\nenum {\n\tEXTENT_BUFFER_UPTODATE = 0,\n\tEXTENT_BUFFER_DIRTY = 1,\n\tEXTENT_BUFFER_TREE_REF = 2,\n\tEXTENT_BUFFER_STALE = 3,\n\tEXTENT_BUFFER_WRITEBACK = 4,\n\tEXTENT_BUFFER_UNMAPPED = 5,\n\tEXTENT_BUFFER_WRITE_ERR = 6,\n\tEXTENT_BUFFER_ZONED_ZEROOUT = 7,\n\tEXTENT_BUFFER_READING = 8,\n};\n\nenum {\n\tEXTRACT_TOPOLOGY = 0,\n\tEXTRACT_LINE_SIZE = 1,\n\tEXTRACT_SIZE = 2,\n\tEXTRACT_ASSOCIATIVITY = 3,\n};\n\nenum {\n\tFAN_EVENT_INIT = 0,\n\tFAN_EVENT_REPORTED = 1,\n\tFAN_EVENT_ANSWERED = 2,\n\tFAN_EVENT_CANCELED = 3,\n};\n\nenum {\n\tFBCON_LOGO_CANSHOW = -1,\n\tFBCON_LOGO_DRAW = -2,\n\tFBCON_LOGO_DONTSHOW = -3,\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nenum {\n\tFDB_NOTIFY_BIT = 1,\n\tFDB_NOTIFY_INACTIVE_BIT = 2,\n};\n\nenum {\n\tFGRAPH_TYPE_RESERVED = 0,\n\tFGRAPH_TYPE_BITMAP = 1,\n\tFGRAPH_TYPE_DATA = 2,\n};\n\nenum {\n\tFIB6_NO_SERNUM_CHANGE = 0,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_RDYN_STRING = 3,\n\tFILTER_PTR_STRING = 4,\n\tFILTER_TRACE_FN = 5,\n\tFILTER_CPUMASK = 6,\n\tFILTER_COMM = 7,\n\tFILTER_CPU = 8,\n\tFILTER_STACKTRACE = 9,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_MISSING_BRACE_OPEN = 5,\n\tFILT_ERR_MISSING_BRACE_CLOSE = 6,\n\tFILT_ERR_OPERAND_TOO_LONG = 7,\n\tFILT_ERR_EXPECT_STRING = 8,\n\tFILT_ERR_EXPECT_DIGIT = 9,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 10,\n\tFILT_ERR_FIELD_NOT_FOUND = 11,\n\tFILT_ERR_ILLEGAL_INTVAL = 12,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 13,\n\tFILT_ERR_TOO_MANY_PREDS = 14,\n\tFILT_ERR_INVALID_FILTER = 15,\n\tFILT_ERR_INVALID_CPULIST = 16,\n\tFILT_ERR_IP_FIELD_ONLY = 17,\n\tFILT_ERR_INVALID_VALUE = 18,\n\tFILT_ERR_NO_FUNCTION = 19,\n\tFILT_ERR_ERRNO = 20,\n\tFILT_ERR_NO_FILTER = 21,\n};\n\nenum {\n\tFLAGS_FILL_FULL = 268435456,\n\tFLAGS_FILL_START = 536870912,\n\tFLAGS_FILL_END = 805306368,\n};\n\nenum {\n\tFLOATING = 0,\n\tDIRECTED = 1,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\nenum {\n\tFRA_UNSPEC = 0,\n\tFRA_DST = 1,\n\tFRA_SRC = 2,\n\tFRA_IIFNAME = 3,\n\tFRA_GOTO = 4,\n\tFRA_UNUSED2 = 5,\n\tFRA_PRIORITY = 6,\n\tFRA_UNUSED3 = 7,\n\tFRA_UNUSED4 = 8,\n\tFRA_UNUSED5 = 9,\n\tFRA_FWMARK = 10,\n\tFRA_FLOW = 11,\n\tFRA_TUN_ID = 12,\n\tFRA_SUPPRESS_IFGROUP = 13,\n\tFRA_SUPPRESS_PREFIXLEN = 14,\n\tFRA_TABLE = 15,\n\tFRA_FWMASK = 16,\n\tFRA_OIFNAME = 17,\n\tFRA_PAD = 18,\n\tFRA_L3MDEV = 19,\n\tFRA_UID_RANGE = 20,\n\tFRA_PROTOCOL = 21,\n\tFRA_IP_PROTO = 22,\n\tFRA_SPORT_RANGE = 23,\n\tFRA_DPORT_RANGE = 24,\n\tFRA_DSCP = 25,\n\tFRA_FLOWLABEL = 26,\n\tFRA_FLOWLABEL_MASK = 27,\n\tFRA_SPORT_MASK = 28,\n\tFRA_DPORT_MASK = 29,\n\tFRA_DSCP_MASK = 30,\n\t__FRA_MAX = 31,\n};\n\nenum {\n\tFR_ACT_UNSPEC = 0,\n\tFR_ACT_TO_TBL = 1,\n\tFR_ACT_GOTO = 2,\n\tFR_ACT_NOP = 3,\n\tFR_ACT_RES3 = 4,\n\tFR_ACT_RES4 = 5,\n\tFR_ACT_BLACKHOLE = 6,\n\tFR_ACT_UNREACHABLE = 7,\n\tFR_ACT_PROHIBIT = 8,\n\t__FR_ACT_MAX = 9,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFTRACE_FL_ENABLED = 2147483648,\n\tFTRACE_FL_REGS = 1073741824,\n\tFTRACE_FL_REGS_EN = 536870912,\n\tFTRACE_FL_TRAMP = 268435456,\n\tFTRACE_FL_TRAMP_EN = 134217728,\n\tFTRACE_FL_IPMODIFY = 67108864,\n\tFTRACE_FL_DISABLED = 33554432,\n\tFTRACE_FL_DIRECT = 16777216,\n\tFTRACE_FL_DIRECT_EN = 8388608,\n\tFTRACE_FL_CALL_OPS = 4194304,\n\tFTRACE_FL_CALL_OPS_EN = 2097152,\n\tFTRACE_FL_TOUCHED = 1048576,\n\tFTRACE_FL_MODIFIED = 524288,\n};\n\nenum {\n\tFTRACE_HASH_FL_MOD = 1,\n};\n\nenum {\n\tFTRACE_ITER_FILTER = 1,\n\tFTRACE_ITER_NOTRACE = 2,\n\tFTRACE_ITER_PRINTALL = 4,\n\tFTRACE_ITER_DO_PROBES = 8,\n\tFTRACE_ITER_PROBE = 16,\n\tFTRACE_ITER_MOD = 32,\n\tFTRACE_ITER_ENABLED = 64,\n\tFTRACE_ITER_TOUCHED = 128,\n\tFTRACE_ITER_ADDRS = 256,\n};\n\nenum {\n\tFTRACE_MODIFY_ENABLE_FL = 1,\n\tFTRACE_MODIFY_MAY_SLEEP_FL = 2,\n};\n\nenum {\n\tFTRACE_OPS_FL_ENABLED = 1,\n\tFTRACE_OPS_FL_DYNAMIC = 2,\n\tFTRACE_OPS_FL_SAVE_REGS = 4,\n\tFTRACE_OPS_FL_SAVE_REGS_IF_SUPPORTED = 8,\n\tFTRACE_OPS_FL_RECURSION = 16,\n\tFTRACE_OPS_FL_STUB = 32,\n\tFTRACE_OPS_FL_INITIALIZED = 64,\n\tFTRACE_OPS_FL_DELETED = 128,\n\tFTRACE_OPS_FL_ADDING = 256,\n\tFTRACE_OPS_FL_REMOVING = 512,\n\tFTRACE_OPS_FL_MODIFYING = 1024,\n\tFTRACE_OPS_FL_ALLOC_TRAMP = 2048,\n\tFTRACE_OPS_FL_IPMODIFY = 4096,\n\tFTRACE_OPS_FL_PID = 8192,\n\tFTRACE_OPS_FL_RCU = 16384,\n\tFTRACE_OPS_FL_TRACE_ARRAY = 32768,\n\tFTRACE_OPS_FL_PERMANENT = 65536,\n\tFTRACE_OPS_FL_DIRECT = 131072,\n\tFTRACE_OPS_FL_SUBOP = 262144,\n\tFTRACE_OPS_FL_GRAPH = 524288,\n};\n\nenum {\n\tFTRACE_UPDATE_CALLS = 1,\n\tFTRACE_DISABLE_CALLS = 2,\n\tFTRACE_UPDATE_TRACE_FUNC = 4,\n\tFTRACE_START_FUNC_RET = 8,\n\tFTRACE_STOP_FUNC_RET = 16,\n\tFTRACE_MAY_SLEEP = 32,\n};\n\nenum {\n\tFTRACE_UPDATE_IGNORE = 0,\n\tFTRACE_UPDATE_MAKE_CALL = 1,\n\tFTRACE_UPDATE_MODIFY_CALL = 2,\n\tFTRACE_UPDATE_MAKE_NOP = 3,\n};\n\nenum {\n\tFUSE_I_ADVISE_RDPLUS = 0,\n\tFUSE_I_INIT_RDPLUS = 1,\n\tFUSE_I_SIZE_UNSTABLE = 2,\n\tFUSE_I_BAD = 3,\n\tFUSE_I_BTIME = 4,\n\tFUSE_I_CACHE_IO_MODE = 5,\n\tFUSE_I_EXCLUSIVE = 6,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tHANDSHAKE_A_ACCEPT_SOCKFD = 1,\n\tHANDSHAKE_A_ACCEPT_HANDLER_CLASS = 2,\n\tHANDSHAKE_A_ACCEPT_MESSAGE_TYPE = 3,\n\tHANDSHAKE_A_ACCEPT_TIMEOUT = 4,\n\tHANDSHAKE_A_ACCEPT_AUTH_MODE = 5,\n\tHANDSHAKE_A_ACCEPT_PEER_IDENTITY = 6,\n\tHANDSHAKE_A_ACCEPT_CERTIFICATE = 7,\n\tHANDSHAKE_A_ACCEPT_PEERNAME = 8,\n\tHANDSHAKE_A_ACCEPT_KEYRING = 9,\n\t__HANDSHAKE_A_ACCEPT_MAX = 10,\n\tHANDSHAKE_A_ACCEPT_MAX = 9,\n};\n\nenum {\n\tHANDSHAKE_A_DONE_STATUS = 1,\n\tHANDSHAKE_A_DONE_SOCKFD = 2,\n\tHANDSHAKE_A_DONE_REMOTE_AUTH = 3,\n\t__HANDSHAKE_A_DONE_MAX = 4,\n\tHANDSHAKE_A_DONE_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_A_X509_CERT = 1,\n\tHANDSHAKE_A_X509_PRIVKEY = 2,\n\t__HANDSHAKE_A_X509_MAX = 3,\n\tHANDSHAKE_A_X509_MAX = 2,\n};\n\nenum {\n\tHANDSHAKE_CMD_READY = 1,\n\tHANDSHAKE_CMD_ACCEPT = 2,\n\tHANDSHAKE_CMD_DONE = 3,\n\t__HANDSHAKE_CMD_MAX = 4,\n\tHANDSHAKE_CMD_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_NLGRP_NONE = 0,\n\tHANDSHAKE_NLGRP_TLSHD = 1,\n};\n\nenum {\n\tHASH_SIZE = 128,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHIST_ERR_NONE = 0,\n\tHIST_ERR_DUPLICATE_VAR = 1,\n\tHIST_ERR_VAR_NOT_UNIQUE = 2,\n\tHIST_ERR_TOO_MANY_VARS = 3,\n\tHIST_ERR_MALFORMED_ASSIGNMENT = 4,\n\tHIST_ERR_NAMED_MISMATCH = 5,\n\tHIST_ERR_TRIGGER_EEXIST = 6,\n\tHIST_ERR_TRIGGER_ENOENT_CLEAR = 7,\n\tHIST_ERR_SET_CLOCK_FAIL = 8,\n\tHIST_ERR_BAD_FIELD_MODIFIER = 9,\n\tHIST_ERR_TOO_MANY_SUBEXPR = 10,\n\tHIST_ERR_TIMESTAMP_MISMATCH = 11,\n\tHIST_ERR_TOO_MANY_FIELD_VARS = 12,\n\tHIST_ERR_EVENT_FILE_NOT_FOUND = 13,\n\tHIST_ERR_HIST_NOT_FOUND = 14,\n\tHIST_ERR_HIST_CREATE_FAIL = 15,\n\tHIST_ERR_SYNTH_VAR_NOT_FOUND = 16,\n\tHIST_ERR_SYNTH_EVENT_NOT_FOUND = 17,\n\tHIST_ERR_SYNTH_TYPE_MISMATCH = 18,\n\tHIST_ERR_SYNTH_COUNT_MISMATCH = 19,\n\tHIST_ERR_FIELD_VAR_PARSE_FAIL = 20,\n\tHIST_ERR_VAR_CREATE_FIND_FAIL = 21,\n\tHIST_ERR_ONX_NOT_VAR = 22,\n\tHIST_ERR_ONX_VAR_NOT_FOUND = 23,\n\tHIST_ERR_ONX_VAR_CREATE_FAIL = 24,\n\tHIST_ERR_FIELD_VAR_CREATE_FAIL = 25,\n\tHIST_ERR_TOO_MANY_PARAMS = 26,\n\tHIST_ERR_PARAM_NOT_FOUND = 27,\n\tHIST_ERR_INVALID_PARAM = 28,\n\tHIST_ERR_ACTION_NOT_FOUND = 29,\n\tHIST_ERR_NO_SAVE_PARAMS = 30,\n\tHIST_ERR_TOO_MANY_SAVE_ACTIONS = 31,\n\tHIST_ERR_ACTION_MISMATCH = 32,\n\tHIST_ERR_NO_CLOSING_PAREN = 33,\n\tHIST_ERR_SUBSYS_NOT_FOUND = 34,\n\tHIST_ERR_INVALID_SUBSYS_EVENT = 35,\n\tHIST_ERR_INVALID_REF_KEY = 36,\n\tHIST_ERR_VAR_NOT_FOUND = 37,\n\tHIST_ERR_FIELD_NOT_FOUND = 38,\n\tHIST_ERR_EMPTY_ASSIGNMENT = 39,\n\tHIST_ERR_INVALID_SORT_MODIFIER = 40,\n\tHIST_ERR_EMPTY_SORT_FIELD = 41,\n\tHIST_ERR_TOO_MANY_SORT_FIELDS = 42,\n\tHIST_ERR_INVALID_SORT_FIELD = 43,\n\tHIST_ERR_INVALID_STR_OPERAND = 44,\n\tHIST_ERR_EXPECT_NUMBER = 45,\n\tHIST_ERR_UNARY_MINUS_SUBEXPR = 46,\n\tHIST_ERR_DIVISION_BY_ZERO = 47,\n\tHIST_ERR_NEED_NOHC_VAL = 48,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHMM_NEED_FAULT = 1,\n\tHMM_NEED_WRITE_FAULT = 2,\n\tHMM_NEED_ALL_BITS = 3,\n};\n\nenum {\n\tHMM_PFN_INOUT_FLAGS = 2017612633061982208ULL,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tHWCAP_NR_ESAN3 = 0,\n\tHWCAP_NR_ZARCH = 1,\n\tHWCAP_NR_STFLE = 2,\n\tHWCAP_NR_MSA = 3,\n\tHWCAP_NR_LDISP = 4,\n\tHWCAP_NR_EIMM = 5,\n\tHWCAP_NR_DFP = 6,\n\tHWCAP_NR_HPAGE = 7,\n\tHWCAP_NR_ETF3EH = 8,\n\tHWCAP_NR_HIGH_GPRS = 9,\n\tHWCAP_NR_TE = 10,\n\tHWCAP_NR_VXRS = 11,\n\tHWCAP_NR_VXRS_BCD = 12,\n\tHWCAP_NR_VXRS_EXT = 13,\n\tHWCAP_NR_GS = 14,\n\tHWCAP_NR_VXRS_EXT2 = 15,\n\tHWCAP_NR_VXRS_PDE = 16,\n\tHWCAP_NR_SORT = 17,\n\tHWCAP_NR_DFLT = 18,\n\tHWCAP_NR_VXRS_PDE2 = 19,\n\tHWCAP_NR_NNPA = 20,\n\tHWCAP_NR_PCI_MIO = 21,\n\tHWCAP_NR_SIE = 22,\n\tHWCAP_NR_MAX = 23,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tICQ_EXITED = 4,\n\tICQ_DESTROYED = 8,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIFAL_ADDRESS = 1,\n\tIFAL_LABEL = 2,\n\t__IFAL_MAX = 3,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_INFO_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_INFO_RING_ID = 1,\n\tIFLA_BRIDGE_MRP_INFO_P_IFINDEX = 2,\n\tIFLA_BRIDGE_MRP_INFO_S_IFINDEX = 3,\n\tIFLA_BRIDGE_MRP_INFO_PRIO = 4,\n\tIFLA_BRIDGE_MRP_INFO_RING_STATE = 5,\n\tIFLA_BRIDGE_MRP_INFO_RING_ROLE = 6,\n\tIFLA_BRIDGE_MRP_INFO_TEST_INTERVAL = 7,\n\tIFLA_BRIDGE_MRP_INFO_TEST_MAX_MISS = 8,\n\tIFLA_BRIDGE_MRP_INFO_TEST_MONITOR = 9,\n\tIFLA_BRIDGE_MRP_INFO_I_IFINDEX = 10,\n\tIFLA_BRIDGE_MRP_INFO_IN_STATE = 11,\n\tIFLA_BRIDGE_MRP_INFO_IN_ROLE = 12,\n\tIFLA_BRIDGE_MRP_INFO_IN_TEST_INTERVAL = 13,\n\tIFLA_BRIDGE_MRP_INFO_IN_TEST_MAX_MISS = 14,\n\t__IFLA_BRIDGE_MRP_INFO_MAX = 15,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_INSTANCE_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_INSTANCE_RING_ID = 1,\n\tIFLA_BRIDGE_MRP_INSTANCE_P_IFINDEX = 2,\n\tIFLA_BRIDGE_MRP_INSTANCE_S_IFINDEX = 3,\n\tIFLA_BRIDGE_MRP_INSTANCE_PRIO = 4,\n\t__IFLA_BRIDGE_MRP_INSTANCE_MAX = 5,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_IN_ROLE_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_IN_ROLE_RING_ID = 1,\n\tIFLA_BRIDGE_MRP_IN_ROLE_IN_ID = 2,\n\tIFLA_BRIDGE_MRP_IN_ROLE_ROLE = 3,\n\tIFLA_BRIDGE_MRP_IN_ROLE_I_IFINDEX = 4,\n\t__IFLA_BRIDGE_MRP_IN_ROLE_MAX = 5,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_IN_STATE_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_IN_STATE_IN_ID = 1,\n\tIFLA_BRIDGE_MRP_IN_STATE_STATE = 2,\n\t__IFLA_BRIDGE_MRP_IN_STATE_MAX = 3,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_PORT_ROLE_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_PORT_ROLE_ROLE = 1,\n\t__IFLA_BRIDGE_MRP_PORT_ROLE_MAX = 2,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_PORT_STATE_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_PORT_STATE_STATE = 1,\n\t__IFLA_BRIDGE_MRP_PORT_STATE_MAX = 2,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_RING_ROLE_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_RING_ROLE_RING_ID = 1,\n\tIFLA_BRIDGE_MRP_RING_ROLE_ROLE = 2,\n\t__IFLA_BRIDGE_MRP_RING_ROLE_MAX = 3,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_RING_STATE_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_RING_STATE_RING_ID = 1,\n\tIFLA_BRIDGE_MRP_RING_STATE_STATE = 2,\n\t__IFLA_BRIDGE_MRP_RING_STATE_MAX = 3,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_START_IN_TEST_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_START_IN_TEST_IN_ID = 1,\n\tIFLA_BRIDGE_MRP_START_IN_TEST_INTERVAL = 2,\n\tIFLA_BRIDGE_MRP_START_IN_TEST_MAX_MISS = 3,\n\tIFLA_BRIDGE_MRP_START_IN_TEST_PERIOD = 4,\n\t__IFLA_BRIDGE_MRP_START_IN_TEST_MAX = 5,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_START_TEST_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_START_TEST_RING_ID = 1,\n\tIFLA_BRIDGE_MRP_START_TEST_INTERVAL = 2,\n\tIFLA_BRIDGE_MRP_START_TEST_MAX_MISS = 3,\n\tIFLA_BRIDGE_MRP_START_TEST_PERIOD = 4,\n\tIFLA_BRIDGE_MRP_START_TEST_MONITOR = 5,\n\t__IFLA_BRIDGE_MRP_START_TEST_MAX = 6,\n};\n\nenum {\n\tIFLA_BRIDGE_MRP_UNSPEC = 0,\n\tIFLA_BRIDGE_MRP_INSTANCE = 1,\n\tIFLA_BRIDGE_MRP_PORT_STATE = 2,\n\tIFLA_BRIDGE_MRP_PORT_ROLE = 3,\n\tIFLA_BRIDGE_MRP_RING_STATE = 4,\n\tIFLA_BRIDGE_MRP_RING_ROLE = 5,\n\tIFLA_BRIDGE_MRP_START_TEST = 6,\n\tIFLA_BRIDGE_MRP_INFO = 7,\n\tIFLA_BRIDGE_MRP_IN_ROLE = 8,\n\tIFLA_BRIDGE_MRP_IN_STATE = 9,\n\tIFLA_BRIDGE_MRP_START_IN_TEST = 10,\n\t__IFLA_BRIDGE_MRP_MAX = 11,\n};\n\nenum {\n\tIFLA_BRIDGE_VLAN_TUNNEL_UNSPEC = 0,\n\tIFLA_BRIDGE_VLAN_TUNNEL_ID = 1,\n\tIFLA_BRIDGE_VLAN_TUNNEL_VID = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_FLAGS = 3,\n\t__IFLA_BRIDGE_VLAN_TUNNEL_MAX = 4,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_BR_UNSPEC = 0,\n\tIFLA_BR_FORWARD_DELAY = 1,\n\tIFLA_BR_HELLO_TIME = 2,\n\tIFLA_BR_MAX_AGE = 3,\n\tIFLA_BR_AGEING_TIME = 4,\n\tIFLA_BR_STP_STATE = 5,\n\tIFLA_BR_PRIORITY = 6,\n\tIFLA_BR_VLAN_FILTERING = 7,\n\tIFLA_BR_VLAN_PROTOCOL = 8,\n\tIFLA_BR_GROUP_FWD_MASK = 9,\n\tIFLA_BR_ROOT_ID = 10,\n\tIFLA_BR_BRIDGE_ID = 11,\n\tIFLA_BR_ROOT_PORT = 12,\n\tIFLA_BR_ROOT_PATH_COST = 13,\n\tIFLA_BR_TOPOLOGY_CHANGE = 14,\n\tIFLA_BR_TOPOLOGY_CHANGE_DETECTED = 15,\n\tIFLA_BR_HELLO_TIMER = 16,\n\tIFLA_BR_TCN_TIMER = 17,\n\tIFLA_BR_TOPOLOGY_CHANGE_TIMER = 18,\n\tIFLA_BR_GC_TIMER = 19,\n\tIFLA_BR_GROUP_ADDR = 20,\n\tIFLA_BR_FDB_FLUSH = 21,\n\tIFLA_BR_MCAST_ROUTER = 22,\n\tIFLA_BR_MCAST_SNOOPING = 23,\n\tIFLA_BR_MCAST_QUERY_USE_IFADDR = 24,\n\tIFLA_BR_MCAST_QUERIER = 25,\n\tIFLA_BR_MCAST_HASH_ELASTICITY = 26,\n\tIFLA_BR_MCAST_HASH_MAX = 27,\n\tIFLA_BR_MCAST_LAST_MEMBER_CNT = 28,\n\tIFLA_BR_MCAST_STARTUP_QUERY_CNT = 29,\n\tIFLA_BR_MCAST_LAST_MEMBER_INTVL = 30,\n\tIFLA_BR_MCAST_MEMBERSHIP_INTVL = 31,\n\tIFLA_BR_MCAST_QUERIER_INTVL = 32,\n\tIFLA_BR_MCAST_QUERY_INTVL = 33,\n\tIFLA_BR_MCAST_QUERY_RESPONSE_INTVL = 34,\n\tIFLA_BR_MCAST_STARTUP_QUERY_INTVL = 35,\n\tIFLA_BR_NF_CALL_IPTABLES = 36,\n\tIFLA_BR_NF_CALL_IP6TABLES = 37,\n\tIFLA_BR_NF_CALL_ARPTABLES = 38,\n\tIFLA_BR_VLAN_DEFAULT_PVID = 39,\n\tIFLA_BR_PAD = 40,\n\tIFLA_BR_VLAN_STATS_ENABLED = 41,\n\tIFLA_BR_MCAST_STATS_ENABLED = 42,\n\tIFLA_BR_MCAST_IGMP_VERSION = 43,\n\tIFLA_BR_MCAST_MLD_VERSION = 44,\n\tIFLA_BR_VLAN_STATS_PER_PORT = 45,\n\tIFLA_BR_MULTI_BOOLOPT = 46,\n\tIFLA_BR_MCAST_QUERIER_STATE = 47,\n\tIFLA_BR_FDB_N_LEARNED = 48,\n\tIFLA_BR_FDB_MAX_LEARNED = 49,\n\t__IFLA_BR_MAX = 50,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET6_UNSPEC = 0,\n\tIFLA_INET6_FLAGS = 1,\n\tIFLA_INET6_CONF = 2,\n\tIFLA_INET6_STATS = 3,\n\tIFLA_INET6_MCAST = 4,\n\tIFLA_INET6_CACHEINFO = 5,\n\tIFLA_INET6_ICMP6STATS = 6,\n\tIFLA_INET6_TOKEN = 7,\n\tIFLA_INET6_ADDR_GEN_MODE = 8,\n\tIFLA_INET6_RA_MTU = 9,\n\t__IFLA_INET6_MAX = 10,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_ACT_NONE = -1,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nenum {\n\tINET6_IFADDR_STATE_PREDAD = 0,\n\tINET6_IFADDR_STATE_DAD = 1,\n\tINET6_IFADDR_STATE_POSTDAD = 2,\n\tINET6_IFADDR_STATE_ERRDAD = 3,\n\tINET6_IFADDR_STATE_DEAD = 4,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINET_ULP_INFO_UNSPEC = 0,\n\tINET_ULP_INFO_NAME = 1,\n\tINET_ULP_INFO_TLS = 2,\n\tINET_ULP_INFO_MPTCP = 3,\n\t__INET_ULP_INFO_MAX = 4,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINSTR_E = 0,\n\tINSTR_IE_UU = 1,\n\tINSTR_MII_UPP = 2,\n\tINSTR_RIE_R0IU = 3,\n\tINSTR_RIE_R0UU = 4,\n\tINSTR_RIE_RRI0 = 5,\n\tINSTR_RIE_RRP = 6,\n\tINSTR_RIE_RRPU = 7,\n\tINSTR_RIE_RRUUU = 8,\n\tINSTR_RIE_RUI0 = 9,\n\tINSTR_RIE_RUPI = 10,\n\tINSTR_RIE_RUPU = 11,\n\tINSTR_RIL_RI = 12,\n\tINSTR_RIL_RP = 13,\n\tINSTR_RIL_RU = 14,\n\tINSTR_RIL_UP = 15,\n\tINSTR_RIS_RURDI = 16,\n\tINSTR_RIS_RURDU = 17,\n\tINSTR_RI_RI = 18,\n\tINSTR_RI_RP = 19,\n\tINSTR_RI_RU = 20,\n\tINSTR_RI_UP = 21,\n\tINSTR_RRE_00 = 22,\n\tINSTR_RRE_AA = 23,\n\tINSTR_RRE_AR = 24,\n\tINSTR_RRE_F0 = 25,\n\tINSTR_RRE_FF = 26,\n\tINSTR_RRE_FR = 27,\n\tINSTR_RRE_R0 = 28,\n\tINSTR_RRE_RA = 29,\n\tINSTR_RRE_RF = 30,\n\tINSTR_RRE_RR = 31,\n\tINSTR_RRF_0UFF = 32,\n\tINSTR_RRF_0URF = 33,\n\tINSTR_RRF_F0FF = 34,\n\tINSTR_RRF_F0FF2 = 35,\n\tINSTR_RRF_F0FR = 36,\n\tINSTR_RRF_FFRU = 37,\n\tINSTR_RRF_FUFF = 38,\n\tINSTR_RRF_FUFF2 = 39,\n\tINSTR_RRF_R0RR = 40,\n\tINSTR_RRF_R0RR2 = 41,\n\tINSTR_RRF_RURR = 42,\n\tINSTR_RRF_RURR2 = 43,\n\tINSTR_RRF_U0FF = 44,\n\tINSTR_RRF_U0RF = 45,\n\tINSTR_RRF_U0RR = 46,\n\tINSTR_RRF_URR = 47,\n\tINSTR_RRF_UUFF = 48,\n\tINSTR_RRF_UUFR = 49,\n\tINSTR_RRF_UURF = 50,\n\tINSTR_RRS_RRRDU = 51,\n\tINSTR_RR_FF = 52,\n\tINSTR_RR_R0 = 53,\n\tINSTR_RR_RR = 54,\n\tINSTR_RR_U0 = 55,\n\tINSTR_RR_UR = 56,\n\tINSTR_RSI_RRP = 57,\n\tINSTR_RSL_LRDFU = 58,\n\tINSTR_RSL_R0RD = 59,\n\tINSTR_RSY_AARD = 60,\n\tINSTR_RSY_CCRD = 61,\n\tINSTR_RSY_RRRD = 62,\n\tINSTR_RSY_RURD = 63,\n\tINSTR_RSY_RURD2 = 64,\n\tINSTR_RS_AARD = 65,\n\tINSTR_RS_CCRD = 66,\n\tINSTR_RS_R0RD = 67,\n\tINSTR_RS_RRRD = 68,\n\tINSTR_RS_RURD = 69,\n\tINSTR_RXE_FRRD = 70,\n\tINSTR_RXE_RRRDU = 71,\n\tINSTR_RXF_FRRDF = 72,\n\tINSTR_RXY_FRRD = 73,\n\tINSTR_RXY_RRRD = 74,\n\tINSTR_RXY_URRD = 75,\n\tINSTR_RX_FRRD = 76,\n\tINSTR_RX_RRRD = 77,\n\tINSTR_RX_URRD = 78,\n\tINSTR_SIL_RDI = 79,\n\tINSTR_SIL_RDU = 80,\n\tINSTR_SIY_IRD = 81,\n\tINSTR_SIY_RD = 82,\n\tINSTR_SIY_URD = 83,\n\tINSTR_SI_RD = 84,\n\tINSTR_SI_URD = 85,\n\tINSTR_SMI_U0RDP = 86,\n\tINSTR_SSE_RDRD = 87,\n\tINSTR_SSF_RRDRD = 88,\n\tINSTR_SSF_RRDRD2 = 89,\n\tINSTR_SS_L0RDRD = 90,\n\tINSTR_SS_L2RDRD = 91,\n\tINSTR_SS_LIRDRD = 92,\n\tINSTR_SS_LLRDRD = 93,\n\tINSTR_SS_RRRDRD = 94,\n\tINSTR_SS_RRRDRD2 = 95,\n\tINSTR_SS_RRRDRD3 = 96,\n\tINSTR_S_00 = 97,\n\tINSTR_S_RD = 98,\n\tINSTR_VRI_V0IU = 99,\n\tINSTR_VRI_V0U = 100,\n\tINSTR_VRI_V0UU2 = 101,\n\tINSTR_VRI_V0UUU = 102,\n\tINSTR_VRI_VR0UU = 103,\n\tINSTR_VRI_VV0UU = 104,\n\tINSTR_VRI_VVUU = 105,\n\tINSTR_VRI_VVUUU = 106,\n\tINSTR_VRI_VVUUU2 = 107,\n\tINSTR_VRI_VVV0U = 108,\n\tINSTR_VRI_VVV0UU = 109,\n\tINSTR_VRI_VVV0UU2 = 110,\n\tINSTR_VRI_VVV0UV = 111,\n\tINSTR_VRR_0V0U = 112,\n\tINSTR_VRR_0VV0U = 113,\n\tINSTR_VRR_0VVU = 114,\n\tINSTR_VRR_RV0UU = 115,\n\tINSTR_VRR_VRR = 116,\n\tINSTR_VRR_VV = 117,\n\tINSTR_VRR_VV0U = 118,\n\tINSTR_VRR_VV0U0U = 119,\n\tINSTR_VRR_VV0U2 = 120,\n\tINSTR_VRR_VV0UU2 = 121,\n\tINSTR_VRR_VV0UUU = 122,\n\tINSTR_VRR_VVV = 123,\n\tINSTR_VRR_VVV0U = 124,\n\tINSTR_VRR_VVV0U0 = 125,\n\tINSTR_VRR_VVV0U0U = 126,\n\tINSTR_VRR_VVV0UU = 127,\n\tINSTR_VRR_VVV0UUU = 128,\n\tINSTR_VRR_VVV0V = 129,\n\tINSTR_VRR_VVVU0UV = 130,\n\tINSTR_VRR_VVVU0V = 131,\n\tINSTR_VRR_VVVUU0V = 132,\n\tINSTR_VRS_RRDV = 133,\n\tINSTR_VRS_RVRDU = 134,\n\tINSTR_VRS_VRRD = 135,\n\tINSTR_VRS_VRRDU = 136,\n\tINSTR_VRS_VVRDU = 137,\n\tINSTR_VRV_VVXRDU = 138,\n\tINSTR_VRX_VRRDU = 139,\n\tINSTR_VRX_VV = 140,\n\tINSTR_VSI_URDV = 141,\n};\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tIOAM6_ATTR_UNSPEC = 0,\n\tIOAM6_ATTR_NS_ID = 1,\n\tIOAM6_ATTR_NS_DATA = 2,\n\tIOAM6_ATTR_NS_DATA_WIDE = 3,\n\tIOAM6_ATTR_SC_ID = 4,\n\tIOAM6_ATTR_SC_DATA = 5,\n\tIOAM6_ATTR_SC_NONE = 6,\n\tIOAM6_ATTR_PAD = 7,\n\t__IOAM6_ATTR_MAX = 8,\n};\n\nenum {\n\tIOAM6_CMD_UNSPEC = 0,\n\tIOAM6_CMD_ADD_NAMESPACE = 1,\n\tIOAM6_CMD_DEL_NAMESPACE = 2,\n\tIOAM6_CMD_DUMP_NAMESPACES = 3,\n\tIOAM6_CMD_ADD_SCHEMA = 4,\n\tIOAM6_CMD_DEL_SCHEMA = 5,\n\tIOAM6_CMD_DUMP_SCHEMAS = 6,\n\tIOAM6_CMD_NS_SET_SCHEMA = 7,\n\t__IOAM6_CMD_MAX = 8,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOMMU_PASID_ARRAY_DOMAIN = 0,\n\tIOMMU_PASID_ARRAY_HANDLE = 1,\n};\n\nenum {\n\tIOMMU_SET_DOMAIN_MUST_SUCCEED = 1,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_TREE_FS_PINNED_EXTENTS = 0,\n\tIO_TREE_FS_EXCLUDED_EXTENTS = 1,\n\tIO_TREE_BTREE_INODE_IO = 2,\n\tIO_TREE_INODE_IO = 3,\n\tIO_TREE_RELOC_BLOCKS = 4,\n\tIO_TREE_TRANS_DIRTY_PAGES = 5,\n\tIO_TREE_ROOT_DIRTY_LOG_PAGES = 6,\n\tIO_TREE_INODE_FILE_EXTENT = 7,\n\tIO_TREE_LOG_CSUM_RANGE = 8,\n\tIO_TREE_SELFTEST = 9,\n\tIO_TREE_DEVICE_ALLOC_STATE = 10,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPMRA_CREPORT_UNSPEC = 0,\n\tIPMRA_CREPORT_MSGTYPE = 1,\n\tIPMRA_CREPORT_VIF_ID = 2,\n\tIPMRA_CREPORT_SRC_ADDR = 3,\n\tIPMRA_CREPORT_DST_ADDR = 4,\n\tIPMRA_CREPORT_PKT = 5,\n\tIPMRA_CREPORT_TABLE = 6,\n\t__IPMRA_CREPORT_MAX = 7,\n};\n\nenum {\n\tIPMRA_TABLE_UNSPEC = 0,\n\tIPMRA_TABLE_ID = 1,\n\tIPMRA_TABLE_CACHE_RES_QUEUE_LEN = 2,\n\tIPMRA_TABLE_MROUTE_REG_VIF_NUM = 3,\n\tIPMRA_TABLE_MROUTE_DO_ASSERT = 4,\n\tIPMRA_TABLE_MROUTE_DO_PIM = 5,\n\tIPMRA_TABLE_VIFS = 6,\n\tIPMRA_TABLE_MROUTE_DO_WRVIFWHOLE = 7,\n\t__IPMRA_TABLE_MAX = 8,\n};\n\nenum {\n\tIPMRA_VIFA_UNSPEC = 0,\n\tIPMRA_VIFA_IFINDEX = 1,\n\tIPMRA_VIFA_VIF_ID = 2,\n\tIPMRA_VIFA_FLAGS = 3,\n\tIPMRA_VIFA_BYTES_IN = 4,\n\tIPMRA_VIFA_BYTES_OUT = 5,\n\tIPMRA_VIFA_PACKETS_IN = 6,\n\tIPMRA_VIFA_PACKETS_OUT = 7,\n\tIPMRA_VIFA_LOCAL_ADDR = 8,\n\tIPMRA_VIFA_REMOTE_ADDR = 9,\n\tIPMRA_VIFA_PAD = 10,\n\t__IPMRA_VIFA_MAX = 11,\n};\n\nenum {\n\tIPMRA_VIF_UNSPEC = 0,\n\tIPMRA_VIF = 1,\n\t__IPMRA_VIF_MAX = 2,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIPV6_SADDR_RULE_INIT = 0,\n\tIPV6_SADDR_RULE_LOCAL = 1,\n\tIPV6_SADDR_RULE_SCOPE = 2,\n\tIPV6_SADDR_RULE_PREFERRED = 3,\n\tIPV6_SADDR_RULE_OIF = 4,\n\tIPV6_SADDR_RULE_LABEL = 5,\n\tIPV6_SADDR_RULE_PRIVACY = 6,\n\tIPV6_SADDR_RULE_ORCHID = 7,\n\tIPV6_SADDR_RULE_PREFIX = 8,\n\tIPV6_SADDR_RULE_MAX = 9,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_POLL_F_SCHED = 0,\n\tIRQ_POLL_F_DISABLE = 1,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tI_DATA_SEM_NORMAL = 0,\n\tI_DATA_SEM_OTHER = 1,\n\tI_DATA_SEM_QUOTA = 2,\n\tI_DATA_SEM_EA = 3,\n};\n\nenum {\n\tI_LCOEF_RBPS = 0,\n\tI_LCOEF_RSEQIOPS = 1,\n\tI_LCOEF_RRANDIOPS = 2,\n\tI_LCOEF_WBPS = 3,\n\tI_LCOEF_WSEQIOPS = 4,\n\tI_LCOEF_WRANDIOPS = 5,\n\tNR_I_LCOEFS = 6,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_FPC_BIT = 0,\n\tKERNEL_VXR_V0V7_BIT = 1,\n\tKERNEL_VXR_V8V15_BIT = 2,\n\tKERNEL_VXR_V16V23_BIT = 3,\n\tKERNEL_VXR_V24V31_BIT = 4,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLAT_OK = 1,\n\tLAT_UNKNOWN = 2,\n\tLAT_UNKNOWN_WRITES = 3,\n\tLAT_EXCEEDED = 4,\n};\n\nenum {\n\tLCOEF_RPAGE = 0,\n\tLCOEF_RSEQIO = 1,\n\tLCOEF_RRANDIO = 2,\n\tLCOEF_WPAGE = 3,\n\tLCOEF_WSEQIO = 4,\n\tLCOEF_WRANDIO = 5,\n\tNR_LCOEFS = 6,\n};\n\nenum {\n\tLINK_XSTATS_TYPE_UNSPEC = 0,\n\tLINK_XSTATS_TYPE_BRIDGE = 1,\n\tLINK_XSTATS_TYPE_BOND = 2,\n\t__LINK_XSTATS_TYPE_MAX = 3,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLOG_INODE_ALL = 0,\n\tLOG_INODE_EXISTS = 1,\n};\n\nenum {\n\tLOG_WALK_PIN_ONLY = 0,\n\tLOG_WALK_REPLAY_INODES = 1,\n\tLOG_WALK_REPLAY_DIR_INDEX = 2,\n\tLOG_WALK_REPLAY_ALL = 3,\n};\n\nenum {\n\tLONG_INSN_ALGHSIK = 0,\n\tLONG_INSN_ALHHHR = 1,\n\tLONG_INSN_ALHHLR = 2,\n\tLONG_INSN_ALHSIK = 3,\n\tLONG_INSN_ALSIHN = 4,\n\tLONG_INSN_CDFBRA = 5,\n\tLONG_INSN_CDGBRA = 6,\n\tLONG_INSN_CDGTRA = 7,\n\tLONG_INSN_CDLFBR = 8,\n\tLONG_INSN_CDLFTR = 9,\n\tLONG_INSN_CDLGBR = 10,\n\tLONG_INSN_CDLGTR = 11,\n\tLONG_INSN_CEFBRA = 12,\n\tLONG_INSN_CEGBRA = 13,\n\tLONG_INSN_CELFBR = 14,\n\tLONG_INSN_CELGBR = 15,\n\tLONG_INSN_CFDBRA = 16,\n\tLONG_INSN_CFEBRA = 17,\n\tLONG_INSN_CFXBRA = 18,\n\tLONG_INSN_CGDBRA = 19,\n\tLONG_INSN_CGDTRA = 20,\n\tLONG_INSN_CGEBRA = 21,\n\tLONG_INSN_CGXBRA = 22,\n\tLONG_INSN_CGXTRA = 23,\n\tLONG_INSN_CLFDBR = 24,\n\tLONG_INSN_CLFDTR = 25,\n\tLONG_INSN_CLFEBR = 26,\n\tLONG_INSN_CLFHSI = 27,\n\tLONG_INSN_CLFXBR = 28,\n\tLONG_INSN_CLFXTR = 29,\n\tLONG_INSN_CLGDBR = 30,\n\tLONG_INSN_CLGDTR = 31,\n\tLONG_INSN_CLGEBR = 32,\n\tLONG_INSN_CLGFRL = 33,\n\tLONG_INSN_CLGHRL = 34,\n\tLONG_INSN_CLGHSI = 35,\n\tLONG_INSN_CLGXBR = 36,\n\tLONG_INSN_CLGXTR = 37,\n\tLONG_INSN_CLHHSI = 38,\n\tLONG_INSN_CXFBRA = 39,\n\tLONG_INSN_CXGBRA = 40,\n\tLONG_INSN_CXGTRA = 41,\n\tLONG_INSN_CXLFBR = 42,\n\tLONG_INSN_CXLFTR = 43,\n\tLONG_INSN_CXLGBR = 44,\n\tLONG_INSN_CXLGTR = 45,\n\tLONG_INSN_DFLTCC = 46,\n\tLONG_INSN_FIDBRA = 47,\n\tLONG_INSN_FIEBRA = 48,\n\tLONG_INSN_FIXBRA = 49,\n\tLONG_INSN_ILLEGAL = 50,\n\tLONG_INSN_LDXBRA = 51,\n\tLONG_INSN_LEDBRA = 52,\n\tLONG_INSN_LEXBRA = 53,\n\tLONG_INSN_LLGFAT = 54,\n\tLONG_INSN_LLGFRL = 55,\n\tLONG_INSN_LLGFSG = 56,\n\tLONG_INSN_LLGHRL = 57,\n\tLONG_INSN_LLGTAT = 58,\n\tLONG_INSN_LLZRGF = 59,\n\tLONG_INSN_LOCFHR = 60,\n\tLONG_INSN_LOCGHI = 61,\n\tLONG_INSN_LOCHHI = 62,\n\tLONG_INSN_LPSWEY = 63,\n\tLONG_INSN_MPCIFC = 64,\n\tLONG_INSN_MSGRKC = 65,\n\tLONG_INSN_PCILGI = 66,\n\tLONG_INSN_PCISTB = 67,\n\tLONG_INSN_PCISTBI = 68,\n\tLONG_INSN_PCISTG = 69,\n\tLONG_INSN_PCISTGI = 70,\n\tLONG_INSN_POPCNT = 71,\n\tLONG_INSN_RIEMIT = 72,\n\tLONG_INSN_RINEXT = 73,\n\tLONG_INSN_RISBGN = 74,\n\tLONG_INSN_RISBHG = 75,\n\tLONG_INSN_RISBLG = 76,\n\tLONG_INSN_SELFHR = 77,\n\tLONG_INSN_SLHHHR = 78,\n\tLONG_INSN_SLHHLR = 79,\n\tLONG_INSN_STBEAR = 80,\n\tLONG_INSN_STCCTM = 81,\n\tLONG_INSN_STOCFH = 82,\n\tLONG_INSN_STPCIFC = 83,\n\tLONG_INSN_TABORT = 84,\n\tLONG_INSN_TBEGIN = 85,\n\tLONG_INSN_TBEGINC = 86,\n\tLONG_INSN_VBLEND = 87,\n\tLONG_INSN_VBPERM = 88,\n\tLONG_INSN_VCLFNH = 89,\n\tLONG_INSN_VCLFNL = 90,\n\tLONG_INSN_VCLZDP = 91,\n\tLONG_INSN_VERLLV = 92,\n\tLONG_INSN_VESRAV = 93,\n\tLONG_INSN_VESRLV = 94,\n\tLONG_INSN_VLBRREP = 95,\n\tLONG_INSN_VLEBRF = 96,\n\tLONG_INSN_VLEBRG = 97,\n\tLONG_INSN_VLEBRH = 98,\n\tLONG_INSN_VLLEBRZ = 99,\n\tLONG_INSN_VPOPCT = 100,\n\tLONG_INSN_VSBCBI = 101,\n\tLONG_INSN_VSCSHP = 102,\n\tLONG_INSN_VSTEBRF = 103,\n\tLONG_INSN_VSTEBRG = 104,\n\tLONG_INSN_VSTEBRH = 105,\n\tLONG_INSN_VSTRLR = 106,\n\tLONG_INSN_VUPKZH = 107,\n\tLONG_INSN_VUPKZL = 108,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLWT_BPF_PROG_UNSPEC = 0,\n\tLWT_BPF_PROG_FD = 1,\n\tLWT_BPF_PROG_NAME = 2,\n\t__LWT_BPF_PROG_MAX = 3,\n};\n\nenum {\n\tLWT_BPF_UNSPEC = 0,\n\tLWT_BPF_IN = 1,\n\tLWT_BPF_OUT = 2,\n\tLWT_BPF_XMIT = 3,\n\tLWT_BPF_XMIT_HEADROOM = 4,\n\t__LWT_BPF_MAX = 5,\n};\n\nenum {\n\tMAXIMUM_TEST_BUFFER_LEN = 4096,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMBE_REFERENCED_B = 0,\n\tMBE_REUSABLE_B = 1,\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_MDB_EATTR_UNSPEC = 0,\n\tMDBA_MDB_EATTR_TIMER = 1,\n\tMDBA_MDB_EATTR_SRC_LIST = 2,\n\tMDBA_MDB_EATTR_GROUP_MODE = 3,\n\tMDBA_MDB_EATTR_SOURCE = 4,\n\tMDBA_MDB_EATTR_RTPROT = 5,\n\tMDBA_MDB_EATTR_DST = 6,\n\tMDBA_MDB_EATTR_DST_PORT = 7,\n\tMDBA_MDB_EATTR_VNI = 8,\n\tMDBA_MDB_EATTR_IFINDEX = 9,\n\tMDBA_MDB_EATTR_SRC_VNI = 10,\n\t__MDBA_MDB_EATTR_MAX = 11,\n};\n\nenum {\n\tMDBA_MDB_ENTRY_UNSPEC = 0,\n\tMDBA_MDB_ENTRY_INFO = 1,\n\t__MDBA_MDB_ENTRY_MAX = 2,\n};\n\nenum {\n\tMDBA_MDB_SRCATTR_UNSPEC = 0,\n\tMDBA_MDB_SRCATTR_ADDRESS = 1,\n\tMDBA_MDB_SRCATTR_TIMER = 2,\n\t__MDBA_MDB_SRCATTR_MAX = 3,\n};\n\nenum {\n\tMDBA_MDB_SRCLIST_UNSPEC = 0,\n\tMDBA_MDB_SRCLIST_ENTRY = 1,\n\t__MDBA_MDB_SRCLIST_MAX = 2,\n};\n\nenum {\n\tMDBA_MDB_UNSPEC = 0,\n\tMDBA_MDB_ENTRY = 1,\n\t__MDBA_MDB_MAX = 2,\n};\n\nenum {\n\tMDBA_ROUTER_PATTR_UNSPEC = 0,\n\tMDBA_ROUTER_PATTR_TIMER = 1,\n\tMDBA_ROUTER_PATTR_TYPE = 2,\n\tMDBA_ROUTER_PATTR_INET_TIMER = 3,\n\tMDBA_ROUTER_PATTR_INET6_TIMER = 4,\n\tMDBA_ROUTER_PATTR_VID = 5,\n\t__MDBA_ROUTER_PATTR_MAX = 6,\n};\n\nenum {\n\tMDBA_ROUTER_UNSPEC = 0,\n\tMDBA_ROUTER_PORT = 1,\n\t__MDBA_ROUTER_MAX = 2,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_UNSPEC = 0,\n\tMDBA_MDB = 1,\n\tMDBA_ROUTER = 2,\n\t__MDBA_MAX = 3,\n};\n\nenum {\n\tMDBE_ATTR_UNSPEC = 0,\n\tMDBE_ATTR_SOURCE = 1,\n\tMDBE_ATTR_SRC_LIST = 2,\n\tMDBE_ATTR_GROUP_MODE = 3,\n\tMDBE_ATTR_RTPROT = 4,\n\tMDBE_ATTR_DST = 5,\n\tMDBE_ATTR_DST_PORT = 6,\n\tMDBE_ATTR_VNI = 7,\n\tMDBE_ATTR_IFINDEX = 8,\n\tMDBE_ATTR_SRC_VNI = 9,\n\tMDBE_ATTR_STATE_MASK = 10,\n\t__MDBE_ATTR_MAX = 11,\n};\n\nenum {\n\tMDBE_SRCATTR_UNSPEC = 0,\n\tMDBE_SRCATTR_ADDRESS = 1,\n\t__MDBE_SRCATTR_MAX = 2,\n};\n\nenum {\n\tMDBE_SRC_LIST_UNSPEC = 0,\n\tMDBE_SRC_LIST_ENTRY = 1,\n\t__MDBE_SRC_LIST_MAX = 2,\n};\n\nenum {\n\tMDB_RTR_TYPE_DISABLED = 0,\n\tMDB_RTR_TYPE_TEMP_QUERY = 1,\n\tMDB_RTR_TYPE_PERM = 2,\n\tMDB_RTR_TYPE_TEMP = 3,\n};\n\nenum {\n\tMD_RESYNC_NONE = 0,\n\tMD_RESYNC_YIELDED = 1,\n\tMD_RESYNC_DELAYED = 2,\n\tMD_RESYNC_ACTIVE = 3,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMMAP_ON_MEMORY_DISABLE = 0,\n\tMEMMAP_ON_MEMORY_ENABLE = 1,\n\tMEMMAP_ON_MEMORY_FORCE = 2,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMFC_STATIC = 1,\n\tMFC_OFFLOAD = 2,\n};\n\nenum {\n\tMILLION = 1000000,\n\tMIN_PERIOD = 1000,\n\tMAX_PERIOD = 1000000,\n\tMARGIN_MIN_PCT = 10,\n\tMARGIN_LOW_PCT = 20,\n\tMARGIN_TARGET_PCT = 50,\n\tINUSE_ADJ_STEP_PCT = 25,\n\tTIMER_SLACK_PCT = 1,\n\tWEIGHT_ONE = 65536,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMMOP_OFFLINE = 0,\n\tMMOP_ONLINE = 1,\n\tMMOP_ONLINE_KERNEL = 2,\n\tMMOP_ONLINE_MOVABLE = 3,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMPOL_DEFAULT = 0,\n\tMPOL_PREFERRED = 1,\n\tMPOL_BIND = 2,\n\tMPOL_INTERLEAVE = 3,\n\tMPOL_LOCAL = 4,\n\tMPOL_PREFERRED_MANY = 5,\n\tMPOL_WEIGHTED_INTERLEAVE = 6,\n\tMPOL_MAX = 7,\n};\n\nenum {\n\tMPTCP_CMSG_TS = 1,\n\tMPTCP_CMSG_INQ = 2,\n};\n\nenum {\n\tMPTCP_PM_ADDR_ATTR_UNSPEC = 0,\n\tMPTCP_PM_ADDR_ATTR_FAMILY = 1,\n\tMPTCP_PM_ADDR_ATTR_ID = 2,\n\tMPTCP_PM_ADDR_ATTR_ADDR4 = 3,\n\tMPTCP_PM_ADDR_ATTR_ADDR6 = 4,\n\tMPTCP_PM_ADDR_ATTR_PORT = 5,\n\tMPTCP_PM_ADDR_ATTR_FLAGS = 6,\n\tMPTCP_PM_ADDR_ATTR_IF_IDX = 7,\n\t__MPTCP_PM_ADDR_ATTR_MAX = 8,\n};\n\nenum {\n\tMPTCP_PM_ATTR_UNSPEC = 0,\n\tMPTCP_PM_ATTR_ADDR = 1,\n\tMPTCP_PM_ATTR_RCV_ADD_ADDRS = 2,\n\tMPTCP_PM_ATTR_SUBFLOWS = 3,\n\tMPTCP_PM_ATTR_TOKEN = 4,\n\tMPTCP_PM_ATTR_LOC_ID = 5,\n\tMPTCP_PM_ATTR_ADDR_REMOTE = 6,\n\t__MPTCP_ATTR_AFTER_LAST = 7,\n};\n\nenum {\n\tMPTCP_PM_CMD_UNSPEC = 0,\n\tMPTCP_PM_CMD_ADD_ADDR = 1,\n\tMPTCP_PM_CMD_DEL_ADDR = 2,\n\tMPTCP_PM_CMD_GET_ADDR = 3,\n\tMPTCP_PM_CMD_FLUSH_ADDRS = 4,\n\tMPTCP_PM_CMD_SET_LIMITS = 5,\n\tMPTCP_PM_CMD_GET_LIMITS = 6,\n\tMPTCP_PM_CMD_SET_FLAGS = 7,\n\tMPTCP_PM_CMD_ANNOUNCE = 8,\n\tMPTCP_PM_CMD_REMOVE = 9,\n\tMPTCP_PM_CMD_SUBFLOW_CREATE = 10,\n\tMPTCP_PM_CMD_SUBFLOW_DESTROY = 11,\n\t__MPTCP_PM_CMD_AFTER_LAST = 12,\n};\n\nenum {\n\tMPTCP_PM_ENDPOINT_ADDR = 1,\n\t__MPTCP_PM_ENDPOINT_MAX = 2,\n};\n\nenum {\n\tMPTCP_SUBFLOW_ATTR_UNSPEC = 0,\n\tMPTCP_SUBFLOW_ATTR_TOKEN_REM = 1,\n\tMPTCP_SUBFLOW_ATTR_TOKEN_LOC = 2,\n\tMPTCP_SUBFLOW_ATTR_RELWRITE_SEQ = 3,\n\tMPTCP_SUBFLOW_ATTR_MAP_SEQ = 4,\n\tMPTCP_SUBFLOW_ATTR_MAP_SFSEQ = 5,\n\tMPTCP_SUBFLOW_ATTR_SSN_OFFSET = 6,\n\tMPTCP_SUBFLOW_ATTR_MAP_DATALEN = 7,\n\tMPTCP_SUBFLOW_ATTR_FLAGS = 8,\n\tMPTCP_SUBFLOW_ATTR_ID_REM = 9,\n\tMPTCP_SUBFLOW_ATTR_ID_LOC = 10,\n\tMPTCP_SUBFLOW_ATTR_PAD = 11,\n\t__MPTCP_SUBFLOW_ATTR_MAX = 12,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNDUSEROPT_UNSPEC = 0,\n\tNDUSEROPT_SRCADDR = 1,\n\t__NDUSEROPT_MAX = 2,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFEA_UNSPEC = 0,\n\tNFEA_ACTIVITY_NOTIFY = 1,\n\tNFEA_DONT_REFRESH = 2,\n\t__NFEA_MAX = 3,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNODE_SIZE = 256,\n\tKEYS_PER_NODE = 16,\n\tRECS_PER_LEAF = 15,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 66,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tONLINE_POLICY_CONTIG_ZONES = 0,\n\tONLINE_POLICY_AUTO_MOVABLE = 1,\n};\n\nenum {\n\tOPT_SOURCE = 0,\n\tOPT_SUBTYPE = 1,\n\tOPT_FD = 2,\n\tOPT_ROOTMODE = 3,\n\tOPT_USER_ID = 4,\n\tOPT_GROUP_ID = 5,\n\tOPT_DEFAULT_PERMISSIONS = 6,\n\tOPT_ALLOW_OTHER = 7,\n\tOPT_MAX_READ = 8,\n\tOPT_BLKSIZE = 9,\n\tOPT_ERR = 10,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOp_deprecated = 0,\n\tOpt_logbufs = 1,\n\tOpt_logbsize = 2,\n\tOpt_logdev = 3,\n\tOpt_rtdev = 4,\n\tOpt_wsync = 5,\n\tOpt_noalign = 6,\n\tOpt_swalloc = 7,\n\tOpt_sunit = 8,\n\tOpt_swidth = 9,\n\tOpt_nouuid = 10,\n\tOpt_grpid = 11,\n\tOpt_nogrpid = 12,\n\tOpt_bsdgroups = 13,\n\tOpt_sysvgroups = 14,\n\tOpt_allocsize = 15,\n\tOpt_norecovery = 16,\n\tOpt_inode64 = 17,\n\tOpt_inode32 = 18,\n\tOpt_largeio = 19,\n\tOpt_nolargeio = 20,\n\tOpt_filestreams = 21,\n\tOpt_quota = 22,\n\tOpt_noquota = 23,\n\tOpt_usrquota = 24,\n\tOpt_grpquota = 25,\n\tOpt_prjquota = 26,\n\tOpt_uquota = 27,\n\tOpt_gquota = 28,\n\tOpt_pquota = 29,\n\tOpt_uqnoenforce = 30,\n\tOpt_gqnoenforce = 31,\n\tOpt_pqnoenforce = 32,\n\tOpt_qnoenforce = 33,\n\tOpt_discard = 34,\n\tOpt_nodiscard = 35,\n\tOpt_dax = 36,\n\tOpt_dax_enum = 37,\n\tOpt_max_open_zones = 38,\n\tOpt_lifetime = 39,\n\tOpt_nolifetime = 40,\n\tOpt_max_atomic_write = 41,\n\tOpt_errortag = 42,\n};\n\nenum {\n\tOpt_acl = 0,\n\tOpt_clear_cache = 1,\n\tOpt_commit_interval = 2,\n\tOpt_compress = 3,\n\tOpt_compress_force = 4,\n\tOpt_compress_force_type = 5,\n\tOpt_compress_type = 6,\n\tOpt_degraded = 7,\n\tOpt_device = 8,\n\tOpt_fatal_errors = 9,\n\tOpt_flushoncommit = 10,\n\tOpt_max_inline = 11,\n\tOpt_barrier = 12,\n\tOpt_datacow = 13,\n\tOpt_datasum = 14,\n\tOpt_defrag = 15,\n\tOpt_discard___2 = 16,\n\tOpt_discard_mode = 17,\n\tOpt_ratio = 18,\n\tOpt_rescan_uuid_tree = 19,\n\tOpt_skip_balance = 20,\n\tOpt_space_cache = 21,\n\tOpt_space_cache_version = 22,\n\tOpt_ssd = 23,\n\tOpt_ssd_spread = 24,\n\tOpt_subvol = 25,\n\tOpt_subvol_empty = 26,\n\tOpt_subvolid = 27,\n\tOpt_thread_pool = 28,\n\tOpt_treelog = 29,\n\tOpt_user_subvol_rm_allowed = 30,\n\tOpt_norecovery___2 = 31,\n\tOpt_rescue = 32,\n\tOpt_usebackuproot = 33,\n\tOpt_enospc_debug = 34,\n\tOpt_err = 35,\n};\n\nenum {\n\tOpt_block = 0,\n\tOpt_check = 1,\n\tOpt_cruft = 2,\n\tOpt_gid = 3,\n\tOpt_ignore = 4,\n\tOpt_iocharset = 5,\n\tOpt_map = 6,\n\tOpt_mode = 7,\n\tOpt_nojoliet = 8,\n\tOpt_norock = 9,\n\tOpt_sb = 10,\n\tOpt_session = 11,\n\tOpt_uid = 12,\n\tOpt_unhide = 13,\n\tOpt_utf8 = 14,\n\tOpt_err___2 = 15,\n\tOpt_nocompress = 16,\n\tOpt_hide = 17,\n\tOpt_showassoc = 18,\n\tOpt_dmode = 19,\n\tOpt_overriderockperm = 20,\n};\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid___2 = 2,\n\tOpt_nogrpid___2 = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb___2 = 6,\n\tOpt_nouid32 = 7,\n\tOpt_debug = 8,\n\tOpt_removed = 9,\n\tOpt_user_xattr = 10,\n\tOpt_acl___2 = 11,\n\tOpt_auto_da_alloc = 12,\n\tOpt_noauto_da_alloc = 13,\n\tOpt_noload = 14,\n\tOpt_commit = 15,\n\tOpt_min_batch_time = 16,\n\tOpt_max_batch_time = 17,\n\tOpt_journal_dev = 18,\n\tOpt_journal_path = 19,\n\tOpt_journal_checksum = 20,\n\tOpt_journal_async_commit = 21,\n\tOpt_abort = 22,\n\tOpt_data_journal = 23,\n\tOpt_data_ordered = 24,\n\tOpt_data_writeback = 25,\n\tOpt_data_err_abort = 26,\n\tOpt_data_err_ignore = 27,\n\tOpt_test_dummy_encryption = 28,\n\tOpt_inlinecrypt = 29,\n\tOpt_usrjquota = 30,\n\tOpt_grpjquota = 31,\n\tOpt_quota___2 = 32,\n\tOpt_noquota___2 = 33,\n\tOpt_barrier___2 = 34,\n\tOpt_nobarrier = 35,\n\tOpt_err___3 = 36,\n\tOpt_usrquota___2 = 37,\n\tOpt_grpquota___2 = 38,\n\tOpt_prjquota___2 = 39,\n\tOpt_dax___2 = 40,\n\tOpt_dax_always = 41,\n\tOpt_dax_inode = 42,\n\tOpt_dax_never = 43,\n\tOpt_stripe = 44,\n\tOpt_delalloc = 45,\n\tOpt_nodelalloc = 46,\n\tOpt_warn_on_error = 47,\n\tOpt_nowarn_on_error = 48,\n\tOpt_mblk_io_submit = 49,\n\tOpt_debug_want_extra_isize = 50,\n\tOpt_nomblk_io_submit = 51,\n\tOpt_block_validity = 52,\n\tOpt_noblock_validity = 53,\n\tOpt_inode_readahead_blks = 54,\n\tOpt_journal_ioprio = 55,\n\tOpt_dioread_nolock = 56,\n\tOpt_dioread_lock = 57,\n\tOpt_discard___3 = 58,\n\tOpt_nodiscard___2 = 59,\n\tOpt_init_itable = 60,\n\tOpt_noinit_itable = 61,\n\tOpt_max_dir_size_kb = 62,\n\tOpt_nojournal_checksum = 63,\n\tOpt_nombcache = 64,\n\tOpt_no_prefetch_block_bitmaps = 65,\n\tOpt_mb_optimize_scan = 66,\n\tOpt_errors = 67,\n\tOpt_data = 68,\n\tOpt_data_err = 69,\n\tOpt_jqfmt = 70,\n\tOpt_dax_type = 71,\n};\n\nenum {\n\tOpt_discard_sync = 0,\n\tOpt_discard_async = 1,\n};\n\nenum {\n\tOpt_err___4 = 0,\n\tOpt_enc = 1,\n\tOpt_hash = 2,\n};\n\nenum {\n\tOpt_error = -1,\n\tOpt_context = 0,\n\tOpt_defcontext = 1,\n\tOpt_fscontext = 2,\n\tOpt_rootcontext = 3,\n\tOpt_seclabel = 4,\n};\n\nenum {\n\tOpt_fatal_errors_panic = 0,\n\tOpt_fatal_errors_bug = 1,\n};\n\nenum {\n\tOpt_rescue_usebackuproot = 0,\n\tOpt_rescue_nologreplay = 1,\n\tOpt_rescue_ignorebadroots = 2,\n\tOpt_rescue_ignoredatacsums = 3,\n\tOpt_rescue_ignoremetacsums = 4,\n\tOpt_rescue_ignoresuperflags = 5,\n\tOpt_rescue_parameter_all = 6,\n};\n\nenum {\n\tOpt_space_cache_v1 = 0,\n\tOpt_space_cache_v2 = 1,\n};\n\nenum {\n\tOpt_uid___2 = 0,\n\tOpt_gid___2 = 1,\n};\n\nenum {\n\tOpt_uid___3 = 0,\n\tOpt_gid___3 = 1,\n\tOpt_mode___2 = 2,\n};\n\nenum {\n\tOpt_uid___4 = 0,\n\tOpt_gid___4 = 1,\n\tOpt_mode___3 = 2,\n\tOpt_source = 3,\n};\n\nenum {\n\tOpt_uid___5 = 0,\n\tOpt_gid___5 = 1,\n\tOpt_mode___4 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___5 = 6,\n};\n\nenum {\n\tPAGE_REPORTING_IDLE = 0,\n\tPAGE_REPORTING_REQUESTED = 1,\n\tPAGE_REPORTING_ACTIVE = 2,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPAIE1_CB_SZ = 512,\n\tPAIE1_CTRBLOCK_SZ = 1024,\n};\n\nenum {\n\tPAI_PMU_CRYPTO = 0,\n\tPAI_PMU_EXT = 1,\n\tPAI_PMU_MAX = 2,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_IOV_RESOURCES = 7,\n\tPCI_IOV_RESOURCE_END = 12,\n\tPCI_BRIDGE_RESOURCES = 13,\n\tPCI_BRIDGE_RESOURCE_END = 16,\n\tPCI_NUM_RESOURCES = 17,\n\tDEVICE_COUNT_RESOURCE = 17,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPG_DIRECT_MAP_4K = 0,\n\tPG_DIRECT_MAP_1M = 1,\n\tPG_DIRECT_MAP_2G = 2,\n\tPG_DIRECT_MAP_MAX = 3,\n};\n\nenum {\n\tPIM_TYPE_HELLO = 0,\n\tPIM_TYPE_REGISTER = 1,\n\tPIM_TYPE_REGISTER_STOP = 2,\n\tPIM_TYPE_JOIN_PRUNE = 3,\n\tPIM_TYPE_BOOTSTRAP = 4,\n\tPIM_TYPE_ASSERT = 5,\n\tPIM_TYPE_GRAFT = 6,\n\tPIM_TYPE_GRAFT_ACK = 7,\n\tPIM_TYPE_CANDIDATE_RP_ADV = 8,\n};\n\nenum {\n\tPOLICYDB_CAP_NETPEER = 0,\n\tPOLICYDB_CAP_OPENPERM = 1,\n\tPOLICYDB_CAP_EXTSOCKCLASS = 2,\n\tPOLICYDB_CAP_ALWAYSNETWORK = 3,\n\tPOLICYDB_CAP_CGROUPSECLABEL = 4,\n\tPOLICYDB_CAP_NNP_NOSUID_TRANSITION = 5,\n\tPOLICYDB_CAP_GENFS_SECLABEL_SYMLINKS = 6,\n\tPOLICYDB_CAP_IOCTL_SKIP_CLOEXEC = 7,\n\tPOLICYDB_CAP_USERSPACE_INITIAL_CONTEXT = 8,\n\tPOLICYDB_CAP_NETLINK_XPERM = 9,\n\tPOLICYDB_CAP_NETIF_WILDCARD = 10,\n\tPOLICYDB_CAP_GENFS_SECLABEL_WILDCARD = 11,\n\tPOLICYDB_CAP_FUNCTIONFS_SECLABEL = 12,\n\tPOLICYDB_CAP_MEMFD_CLASS = 13,\n\tPOLICYDB_CAP_BPF_TOKEN_PERMS = 14,\n\t__POLICYDB_CAP_MAX = 15,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPREFIX_UNSPEC = 0,\n\tPREFIX_ADDRESS = 1,\n\tPREFIX_CACHEINFO = 2,\n\t__PREFIX_MAX = 3,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tPSW_BITS_AMODE_24BIT = 0,\n\tPSW_BITS_AMODE_31BIT = 1,\n\tPSW_BITS_AMODE_64BIT = 3,\n};\n\nenum {\n\tPSW_BITS_AS_PRIMARY = 0,\n\tPSW_BITS_AS_ACCREG = 1,\n\tPSW_BITS_AS_SECONDARY = 2,\n\tPSW_BITS_AS_HOME = 3,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQIF_BLIMITS_B = 0,\n\tQIF_SPACE_B = 1,\n\tQIF_ILIMITS_B = 2,\n\tQIF_INODES_B = 3,\n\tQIF_BTIME_B = 4,\n\tQIF_ITIME_B = 5,\n};\n\nenum {\n\tQOS_ENABLE = 0,\n\tQOS_CTRL = 1,\n\tNR_QOS_CTRL_PARAMS = 2,\n};\n\nenum {\n\tQOS_RPPM = 0,\n\tQOS_RLAT = 1,\n\tQOS_WPPM = 2,\n\tQOS_WLAT = 3,\n\tQOS_MIN = 4,\n\tQOS_MAX = 5,\n\tNR_QOS_PARAMS = 6,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQUOTA_NL_A_UNSPEC = 0,\n\tQUOTA_NL_A_QTYPE = 1,\n\tQUOTA_NL_A_EXCESS_ID = 2,\n\tQUOTA_NL_A_WARNING = 3,\n\tQUOTA_NL_A_DEV_MAJOR = 4,\n\tQUOTA_NL_A_DEV_MINOR = 5,\n\tQUOTA_NL_A_CAUSED_ID = 6,\n\tQUOTA_NL_A_PAD = 7,\n\t__QUOTA_NL_A_MAX = 8,\n};\n\nenum {\n\tQUOTA_NL_C_UNSPEC = 0,\n\tQUOTA_NL_C_WARNING = 1,\n\t__QUOTA_NL_C_MAX = 2,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tRANGE_BOUNDARY_WRITTEN_EXTENT = 0,\n\tRANGE_BOUNDARY_PREALLOC_EXTENT = 1,\n\tRANGE_BOUNDARY_HOLE = 2,\n};\n\nenum {\n\tRB_ADD_STAMP_NONE = 0,\n\tRB_ADD_STAMP_EXTEND = 2,\n\tRB_ADD_STAMP_ABSOLUTE = 4,\n\tRB_ADD_STAMP_FORCE = 8,\n};\n\nenum {\n\tRB_CTX_TRANSITION = 0,\n\tRB_CTX_NMI = 1,\n\tRB_CTX_IRQ = 2,\n\tRB_CTX_SOFTIRQ = 3,\n\tRB_CTX_NORMAL = 4,\n\tRB_CTX_MAX = 5,\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nenum {\n\tREADA_NONE = 0,\n\tREADA_BACK = 1,\n\tREADA_FORWARD = 2,\n\tREADA_FORWARD_ALWAYS = 3,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tRELAY_STATS_BUF_FULL = 1,\n\tRELAY_STATS_WRT_BIG = 2,\n\tRELAY_STATS_LAST = 2,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 5000,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRES_USAGE = 0,\n\tRES_RSVD_USAGE = 1,\n\tRES_LIMIT = 2,\n\tRES_RSVD_LIMIT = 3,\n\tRES_MAX_USAGE = 4,\n\tRES_RSVD_MAX_USAGE = 5,\n\tRES_FAILCNT = 6,\n\tRES_RSVD_FAILCNT = 7,\n};\n\nenum {\n\tRPL_IPTUNNEL_UNSPEC = 0,\n\tRPL_IPTUNNEL_SRH = 1,\n\t__RPL_IPTUNNEL_MAX = 2,\n};\n\nenum {\n\tRQ_WAIT_BUSY_PCT = 5,\n\tUNBUSY_THR_PCT = 75,\n\tMIN_DELAY_THR_PCT = 500,\n\tMAX_DELAY_THR_PCT = 25000,\n\tMIN_DELAY = 250,\n\tMAX_DELAY = 250000,\n\tDFGV_USAGE_PCT = 50,\n\tDFGV_PERIOD = 100000,\n\tMAX_LAGGING_PERIODS = 10,\n\tIOC_PAGE_SHIFT = 12,\n\tIOC_PAGE_SIZE = 4096,\n\tIOC_SECT_TO_PAGE_SHIFT = 3,\n\tLCOEF_RANDIO_PAGES = 4096,\n};\n\nenum {\n\tRS_INIT_FAILURE_BSDES = 2,\n\tRS_INIT_FAILURE_ALRT = 3,\n\tRS_INIT_FAILURE_PERF = 4,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRWB_DEF_DEPTH = 16,\n\tRWB_WINDOW_NSEC = 100000000,\n\tRWB_MIN_WRITE_SAMPLES = 3,\n\tRWB_UNKNOWN_BUMP = 5,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tS390_CPU_FEATURE_MSA = 0,\n\tS390_CPU_FEATURE_VXRS = 1,\n\tS390_CPU_FEATURE_UV = 2,\n\tS390_CPU_FEATURE_D288 = 3,\n\tMAX_CPU_FEATURES = 4,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSCSI_DH_OK = 0,\n\tSCSI_DH_DEV_FAILED = 1,\n\tSCSI_DH_DEV_TEMP_BUSY = 2,\n\tSCSI_DH_DEV_UNSUPP = 3,\n\tSCSI_DH_DEVICE_MAX = 4,\n\tSCSI_DH_NOTCONN = 5,\n\tSCSI_DH_CONN_FAILURE = 6,\n\tSCSI_DH_TRANSPORT_MAX = 7,\n\tSCSI_DH_IO = 8,\n\tSCSI_DH_INVALID_IO = 9,\n\tSCSI_DH_RETRY = 10,\n\tSCSI_DH_IMM_RETRY = 11,\n\tSCSI_DH_TIMED_OUT = 12,\n\tSCSI_DH_RES_TEMP_UNAVAIL = 13,\n\tSCSI_DH_DEV_OFFLINED = 14,\n\tSCSI_DH_NOMEM = 15,\n\tSCSI_DH_NOSYS = 16,\n\tSCSI_DH_DRIVER_MAX = 17,\n};\n\nenum {\n\tSCTP_AUTH_HMAC_ID_RESERVED_0 = 0,\n\tSCTP_AUTH_HMAC_ID_SHA1 = 1,\n\tSCTP_AUTH_HMAC_ID_RESERVED_2 = 2,\n\tSCTP_AUTH_HMAC_ID_SHA256 = 3,\n\t__SCTP_AUTH_HMAC_MAX = 4,\n};\n\nenum {\n\tSCTP_MAX_DUP_TSNS = 16,\n};\n\nenum {\n\tSCTP_MAX_STREAM = 65535,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSECTION_MARKED_PRESENT_BIT = 0,\n\tSECTION_HAS_MEM_MAP_BIT = 1,\n\tSECTION_IS_ONLINE_BIT = 2,\n\tSECTION_IS_EARLY_BIT = 3,\n\tSECTION_TAINT_ZONE_DEVICE_BIT = 4,\n\tSECTION_MAP_LAST_BIT = 5,\n};\n\nenum {\n\tSEG6_ATTR_UNSPEC = 0,\n\tSEG6_ATTR_DST = 1,\n\tSEG6_ATTR_DSTLEN = 2,\n\tSEG6_ATTR_HMACKEYID = 3,\n\tSEG6_ATTR_SECRET = 4,\n\tSEG6_ATTR_SECRETLEN = 5,\n\tSEG6_ATTR_ALGID = 6,\n\tSEG6_ATTR_HMACINFO = 7,\n\t__SEG6_ATTR_MAX = 8,\n};\n\nenum {\n\tSEG6_CMD_UNSPEC = 0,\n\tSEG6_CMD_SETHMAC = 1,\n\tSEG6_CMD_DUMPHMAC = 2,\n\tSEG6_CMD_SET_TUNSRC = 3,\n\tSEG6_CMD_GET_TUNSRC = 4,\n\t__SEG6_CMD_MAX = 5,\n};\n\nenum {\n\tSELNL_MSG_SETENFORCE = 16,\n\tSELNL_MSG_POLICYLOAD = 17,\n\tSELNL_MSG_MAX = 18,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSF_CYCLES_BASIC_ATTR_IDX = 0,\n\tSF_CYCLES_BASIC_DIAG_ATTR_IDX = 1,\n\tSF_CYCLES_ATTR_MAX = 2,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSKCIPHER_WALK_SLOW = 1,\n\tSKCIPHER_WALK_COPY = 2,\n\tSKCIPHER_WALK_DIFF = 4,\n\tSKCIPHER_WALK_SLEEP = 8,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSYNTH_ERR_BAD_NAME = 0,\n\tSYNTH_ERR_INVALID_CMD = 1,\n\tSYNTH_ERR_INVALID_DYN_CMD = 2,\n\tSYNTH_ERR_EVENT_EXISTS = 3,\n\tSYNTH_ERR_TOO_MANY_FIELDS = 4,\n\tSYNTH_ERR_INCOMPLETE_TYPE = 5,\n\tSYNTH_ERR_INVALID_TYPE = 6,\n\tSYNTH_ERR_INVALID_FIELD = 7,\n\tSYNTH_ERR_INVALID_ARRAY_SPEC = 8,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_ATTR_UNSPEC = 0,\n\tTASKSTATS_CMD_ATTR_PID = 1,\n\tTASKSTATS_CMD_ATTR_TGID = 2,\n\tTASKSTATS_CMD_ATTR_REGISTER_CPUMASK = 3,\n\tTASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK = 4,\n\t__TASKSTATS_CMD_ATTR_MAX = 5,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASKSTATS_TYPE_UNSPEC = 0,\n\tTASKSTATS_TYPE_PID = 1,\n\tTASKSTATS_TYPE_TGID = 2,\n\tTASKSTATS_TYPE_STATS = 3,\n\tTASKSTATS_TYPE_AGGR_PID = 4,\n\tTASKSTATS_TYPE_AGGR_TGID = 5,\n\tTASKSTATS_TYPE_NULL = 6,\n\t__TASKSTATS_TYPE_MAX = 7,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTCA_ACT_UNSPEC = 0,\n\tTCA_ACT_KIND = 1,\n\tTCA_ACT_OPTIONS = 2,\n\tTCA_ACT_INDEX = 3,\n\tTCA_ACT_STATS = 4,\n\tTCA_ACT_PAD = 5,\n\tTCA_ACT_COOKIE = 6,\n\tTCA_ACT_FLAGS = 7,\n\tTCA_ACT_HW_STATS = 8,\n\tTCA_ACT_USED_HW_STATS = 9,\n\tTCA_ACT_IN_HW_COUNT = 10,\n\t__TCA_ACT_MAX = 11,\n};\n\nenum {\n\tTCA_CGROUP_UNSPEC = 0,\n\tTCA_CGROUP_ACT = 1,\n\tTCA_CGROUP_POLICE = 2,\n\tTCA_CGROUP_EMATCHES = 3,\n\t__TCA_CGROUP_MAX = 4,\n};\n\nenum {\n\tTCA_EMATCH_TREE_UNSPEC = 0,\n\tTCA_EMATCH_TREE_HDR = 1,\n\tTCA_EMATCH_TREE_LIST = 2,\n\t__TCA_EMATCH_TREE_MAX = 3,\n};\n\nenum {\n\tTCA_FLOWER_KEY_CT_FLAGS_NEW = 1,\n\tTCA_FLOWER_KEY_CT_FLAGS_ESTABLISHED = 2,\n\tTCA_FLOWER_KEY_CT_FLAGS_RELATED = 4,\n\tTCA_FLOWER_KEY_CT_FLAGS_TRACKED = 8,\n\tTCA_FLOWER_KEY_CT_FLAGS_INVALID = 16,\n\tTCA_FLOWER_KEY_CT_FLAGS_REPLY = 32,\n\t__TCA_FLOWER_KEY_CT_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_ROOT_UNSPEC = 0,\n\tTCA_ROOT_TAB = 1,\n\tTCA_ROOT_FLAGS = 2,\n\tTCA_ROOT_COUNT = 3,\n\tTCA_ROOT_TIME_DELTA = 4,\n\tTCA_ROOT_EXT_WARN_MSG = 5,\n\t__TCA_ROOT_MAX = 6,\n};\n\nenum {\n\tTCA_STAB_UNSPEC = 0,\n\tTCA_STAB_BASE = 1,\n\tTCA_STAB_DATA = 2,\n\t__TCA_STAB_MAX = 3,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 16777216,\n\tTCP_FLAG_CWR = 8388608,\n\tTCP_FLAG_ECE = 4194304,\n\tTCP_FLAG_URG = 2097152,\n\tTCP_FLAG_ACK = 1048576,\n\tTCP_FLAG_PSH = 524288,\n\tTCP_FLAG_RST = 262144,\n\tTCP_FLAG_SYN = 131072,\n\tTCP_FLAG_FIN = 65536,\n\tTCP_RESERVED_BITS = 234881024,\n\tTCP_DATA_OFFSET = 4026531840,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTEID_FSI_UNKNOWN = 0,\n\tTEID_FSI_STORE = 1,\n\tTEID_FSI_FETCH = 2,\n};\n\nenum {\n\tTLS_ALERT_DESC_CLOSE_NOTIFY = 0,\n\tTLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10,\n\tTLS_ALERT_DESC_BAD_RECORD_MAC = 20,\n\tTLS_ALERT_DESC_RECORD_OVERFLOW = 22,\n\tTLS_ALERT_DESC_HANDSHAKE_FAILURE = 40,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE = 42,\n\tTLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43,\n\tTLS_ALERT_DESC_CERTIFICATE_REVOKED = 44,\n\tTLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45,\n\tTLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46,\n\tTLS_ALERT_DESC_ILLEGAL_PARAMETER = 47,\n\tTLS_ALERT_DESC_UNKNOWN_CA = 48,\n\tTLS_ALERT_DESC_ACCESS_DENIED = 49,\n\tTLS_ALERT_DESC_DECODE_ERROR = 50,\n\tTLS_ALERT_DESC_DECRYPT_ERROR = 51,\n\tTLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52,\n\tTLS_ALERT_DESC_PROTOCOL_VERSION = 70,\n\tTLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71,\n\tTLS_ALERT_DESC_INTERNAL_ERROR = 80,\n\tTLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86,\n\tTLS_ALERT_DESC_USER_CANCELED = 90,\n\tTLS_ALERT_DESC_MISSING_EXTENSION = 109,\n\tTLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110,\n\tTLS_ALERT_DESC_UNRECOGNIZED_NAME = 112,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113,\n\tTLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115,\n\tTLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116,\n\tTLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120,\n};\n\nenum {\n\tTLS_ALERT_LEVEL_WARNING = 1,\n\tTLS_ALERT_LEVEL_FATAL = 2,\n};\n\nenum {\n\tTLS_NO_KEYRING = 0,\n\tTLS_NO_PEERID = 0,\n\tTLS_NO_CERT = 0,\n\tTLS_NO_PRIVKEY = 0,\n};\n\nenum {\n\tTLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20,\n\tTLS_RECORD_TYPE_ALERT = 21,\n\tTLS_RECORD_TYPE_HANDSHAKE = 22,\n\tTLS_RECORD_TYPE_DATA = 23,\n\tTLS_RECORD_TYPE_HEARTBEAT = 24,\n\tTLS_RECORD_TYPE_TLS12_CID = 25,\n\tTLS_RECORD_TYPE_ACK = 26,\n};\n\nenum {\n\tTOO_MANY_CLOSE = -1,\n\tTOO_MANY_OPEN = -2,\n\tMISSING_QUOTE = -3,\n};\n\nenum {\n\tTOPOLOGY_MODE_HW = 0,\n\tTOPOLOGY_MODE_SINGLE = 1,\n\tTOPOLOGY_MODE_PACKAGE = 2,\n\tTOPOLOGY_MODE_UNINITIALIZED = 3,\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_BAD_MAXACT_TYPE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_NON_UNIQ_SYMBOL = 10,\n\tTP_ERR_BAD_RETPROBE = 11,\n\tTP_ERR_NO_TRACEPOINT = 12,\n\tTP_ERR_BAD_TP_NAME = 13,\n\tTP_ERR_BAD_ADDR_SUFFIX = 14,\n\tTP_ERR_NO_GROUP_NAME = 15,\n\tTP_ERR_GROUP_TOO_LONG = 16,\n\tTP_ERR_BAD_GROUP_NAME = 17,\n\tTP_ERR_NO_EVENT_NAME = 18,\n\tTP_ERR_EVENT_TOO_LONG = 19,\n\tTP_ERR_BAD_EVENT_NAME = 20,\n\tTP_ERR_EVENT_EXIST = 21,\n\tTP_ERR_RETVAL_ON_PROBE = 22,\n\tTP_ERR_NO_RETVAL = 23,\n\tTP_ERR_BAD_STACK_NUM = 24,\n\tTP_ERR_BAD_ARG_NUM = 25,\n\tTP_ERR_BAD_VAR = 26,\n\tTP_ERR_BAD_REG_NAME = 27,\n\tTP_ERR_BAD_MEM_ADDR = 28,\n\tTP_ERR_BAD_IMM = 29,\n\tTP_ERR_IMMSTR_NO_CLOSE = 30,\n\tTP_ERR_FILE_ON_KPROBE = 31,\n\tTP_ERR_BAD_FILE_OFFS = 32,\n\tTP_ERR_SYM_ON_UPROBE = 33,\n\tTP_ERR_TOO_MANY_OPS = 34,\n\tTP_ERR_DEREF_NEED_BRACE = 35,\n\tTP_ERR_BAD_DEREF_OFFS = 36,\n\tTP_ERR_DEREF_OPEN_BRACE = 37,\n\tTP_ERR_COMM_CANT_DEREF = 38,\n\tTP_ERR_BAD_FETCH_ARG = 39,\n\tTP_ERR_ARRAY_NO_CLOSE = 40,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 41,\n\tTP_ERR_BAD_ARRAY_NUM = 42,\n\tTP_ERR_ARRAY_TOO_BIG = 43,\n\tTP_ERR_BAD_TYPE = 44,\n\tTP_ERR_BAD_STRING = 45,\n\tTP_ERR_BAD_SYMSTRING = 46,\n\tTP_ERR_BAD_BITFIELD = 47,\n\tTP_ERR_ARG_NAME_TOO_LONG = 48,\n\tTP_ERR_NO_ARG_NAME = 49,\n\tTP_ERR_BAD_ARG_NAME = 50,\n\tTP_ERR_USED_ARG_NAME = 51,\n\tTP_ERR_ARG_TOO_LONG = 52,\n\tTP_ERR_NO_ARG_BODY = 53,\n\tTP_ERR_BAD_INSN_BNDRY = 54,\n\tTP_ERR_FAIL_REG_PROBE = 55,\n\tTP_ERR_DIFF_PROBE_TYPE = 56,\n\tTP_ERR_DIFF_ARG_TYPE = 57,\n\tTP_ERR_SAME_PROBE = 58,\n\tTP_ERR_NO_EVENT_INFO = 59,\n\tTP_ERR_BAD_ATTACH_EVENT = 60,\n\tTP_ERR_BAD_ATTACH_ARG = 61,\n\tTP_ERR_NO_EP_FILTER = 62,\n\tTP_ERR_NOSUP_BTFARG = 63,\n\tTP_ERR_NO_BTFARG = 64,\n\tTP_ERR_NO_BTF_ENTRY = 65,\n\tTP_ERR_BAD_VAR_ARGS = 66,\n\tTP_ERR_NOFENTRY_ARGS = 67,\n\tTP_ERR_DOUBLE_ARGS = 68,\n\tTP_ERR_ARGS_2LONG = 69,\n\tTP_ERR_ARGIDX_2BIG = 70,\n\tTP_ERR_NO_PTR_STRCT = 71,\n\tTP_ERR_NOSUP_DAT_ARG = 72,\n\tTP_ERR_BAD_HYPHEN = 73,\n\tTP_ERR_NO_BTF_FIELD = 74,\n\tTP_ERR_BAD_BTF_TID = 75,\n\tTP_ERR_BAD_TYPE4STR = 76,\n\tTP_ERR_NEED_STRING_TYPE = 77,\n\tTP_ERR_TOO_MANY_ARGS = 78,\n\tTP_ERR_TOO_MANY_EARGS = 79,\n};\n\nenum {\n\tTRACEFS_EVENT_INODE = 2,\n\tTRACEFS_GID_PERM_SET = 4,\n\tTRACEFS_UID_PERM_SET = 8,\n\tTRACEFS_INSTANCE_INODE = 16,\n};\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n\tTRACE_ARRAY_FL_BOOT = 2,\n\tTRACE_ARRAY_FL_LAST_BOOT = 4,\n\tTRACE_ARRAY_FL_MOD_INIT = 8,\n\tTRACE_ARRAY_FL_MEMMAP = 16,\n\tTRACE_ARRAY_FL_VMALLOC = 32,\n};\n\nenum {\n\tTRACE_CTX_NMI = 0,\n\tTRACE_CTX_IRQ = 1,\n\tTRACE_CTX_SOFTIRQ = 2,\n\tTRACE_CTX_NORMAL = 3,\n\tTRACE_CTX_TRANSITION = 4,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 4,\n\tTRACE_EVENT_FL_TRACEPOINT = 8,\n\tTRACE_EVENT_FL_DYNAMIC = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n\tTRACE_EVENT_FL_EPROBE = 128,\n\tTRACE_EVENT_FL_FPROBE = 256,\n\tTRACE_EVENT_FL_CUSTOM = 512,\n\tTRACE_EVENT_FL_TEST_STR = 1024,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_FTRACE_BIT = 0,\n\tTRACE_FTRACE_NMI_BIT = 1,\n\tTRACE_FTRACE_IRQ_BIT = 2,\n\tTRACE_FTRACE_SIRQ_BIT = 3,\n\tTRACE_FTRACE_TRANSITION_BIT = 4,\n\tTRACE_INTERNAL_BIT = 5,\n\tTRACE_INTERNAL_NMI_BIT = 6,\n\tTRACE_INTERNAL_IRQ_BIT = 7,\n\tTRACE_INTERNAL_SIRQ_BIT = 8,\n\tTRACE_INTERNAL_TRANSITION_BIT = 9,\n\tTRACE_INTERNAL_EVENT_BIT = 10,\n\tTRACE_INTERNAL_EVENT_NMI_BIT = 11,\n\tTRACE_INTERNAL_EVENT_IRQ_BIT = 12,\n\tTRACE_INTERNAL_EVENT_SIRQ_BIT = 13,\n\tTRACE_INTERNAL_EVENT_TRANSITION_BIT = 14,\n\tTRACE_BRANCH_BIT = 15,\n\tTRACE_IRQ_BIT = 16,\n\tTRACE_RECORD_RECURSION_BIT = 17,\n};\n\nenum {\n\tTRACE_FUNC_NO_OPTS = 0,\n\tTRACE_FUNC_OPT_STACK = 1,\n\tTRACE_FUNC_OPT_NO_REPEATS = 2,\n\tTRACE_FUNC_OPT_ARGS = 4,\n\tTRACE_FUNC_OPT_HIGHEST_BIT = 8,\n};\n\nenum {\n\tTRACE_GRAPH_FL = 1,\n\tTRACE_GRAPH_DEPTH_START_BIT = 2,\n\tTRACE_GRAPH_DEPTH_END_BIT = 3,\n\tTRACE_GRAPH_NOTRACE_BIT = 4,\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tTYPE_HWCAP = 0,\n\tTYPE_FACILITY = 1,\n\tTYPE_MACHINE = 2,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tUNUSED = 0,\n\tA_8 = 1,\n\tA_12 = 2,\n\tA_24 = 3,\n\tA_28 = 4,\n\tB_16 = 5,\n\tB_32 = 6,\n\tC_8 = 7,\n\tC_12 = 8,\n\tD20_20 = 9,\n\tD_20 = 10,\n\tD_36 = 11,\n\tF_8 = 12,\n\tF_12 = 13,\n\tF_16 = 14,\n\tF_24 = 15,\n\tF_28 = 16,\n\tF_32 = 17,\n\tI8_8 = 18,\n\tI8_32 = 19,\n\tI16_16 = 20,\n\tI16_32 = 21,\n\tI32_16 = 22,\n\tJ12_12 = 23,\n\tJ16_16 = 24,\n\tJ16_32 = 25,\n\tJ24_24 = 26,\n\tJ32_16 = 27,\n\tL4_8 = 28,\n\tL4_12 = 29,\n\tL8_8 = 30,\n\tR_8 = 31,\n\tR_12 = 32,\n\tR_16 = 33,\n\tR_24 = 34,\n\tR_28 = 35,\n\tU4_8 = 36,\n\tU4_12 = 37,\n\tU4_16 = 38,\n\tU4_20 = 39,\n\tU4_24 = 40,\n\tU4_28 = 41,\n\tU4_32 = 42,\n\tU4_36 = 43,\n\tU8_8 = 44,\n\tU8_16 = 45,\n\tU8_24 = 46,\n\tU8_28 = 47,\n\tU8_32 = 48,\n\tU12_16 = 49,\n\tU16_16 = 50,\n\tU16_20 = 51,\n\tU16_32 = 52,\n\tU32_16 = 53,\n\tVX_12 = 54,\n\tV_8 = 55,\n\tV_12 = 56,\n\tV_16 = 57,\n\tV_32 = 58,\n\tX_12 = 59,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tVTIME_PER_SEC_SHIFT = 37ULL,\n\tVTIME_PER_SEC = 137438953472ULL,\n\tVTIME_PER_USEC = 137438ULL,\n\tVTIME_PER_NSEC = 137ULL,\n\tVRATE_MIN_PPM = 10000ULL,\n\tVRATE_MAX_PPM = 100000000ULL,\n\tVRATE_MIN = 1374ULL,\n\tVRATE_CLAMP_ADJ_PCT = 4ULL,\n\tAUTOP_CYCLE_NSEC = 10000000000ULL,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tWBT_RWQ_BG = 0,\n\tWBT_RWQ_SWAP = 1,\n\tWBT_RWQ_DISCARD = 2,\n\tWBT_NUM_RWQ = 3,\n};\n\nenum {\n\tWBT_STATE_ON_DEFAULT = 1,\n\tWBT_STATE_ON_MANUAL = 2,\n\tWBT_STATE_OFF_DEFAULT = 3,\n\tWBT_STATE_OFF_MANUAL = 4,\n};\n\nenum {\n\tWORK_DONE_BIT = 0,\n\tWORK_ORDER_DONE_BIT = 1,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_DEV_OFFLOAD_UNSPECIFIED = 0,\n\tXFRM_DEV_OFFLOAD_CRYPTO = 1,\n\tXFRM_DEV_OFFLOAD_PACKET = 2,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MODE_FLAG_TUNNEL = 1,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tXFRM_STATE_VOID = 0,\n\tXFRM_STATE_ACQ = 1,\n\tXFRM_STATE_VALID = 2,\n\tXFRM_STATE_ERROR = 3,\n\tXFRM_STATE_EXPIRED = 4,\n\tXFRM_STATE_DEAD = 5,\n};\n\nenum {\n\tXFS_ERR_DEFAULT = 0,\n\tXFS_ERR_EIO = 1,\n\tXFS_ERR_ENOSPC = 2,\n\tXFS_ERR_ENODEV = 3,\n\tXFS_ERR_ERRNO_MAX = 4,\n};\n\nenum {\n\tXFS_ERR_METADATA = 0,\n\tXFS_ERR_CLASS_MAX = 1,\n};\n\nenum {\n\tXFS_LOWSP_1_PCNT = 0,\n\tXFS_LOWSP_2_PCNT = 1,\n\tXFS_LOWSP_3_PCNT = 2,\n\tXFS_LOWSP_4_PCNT = 3,\n\tXFS_LOWSP_5_PCNT = 4,\n\tXFS_LOWSP_MAX = 5,\n};\n\nenum {\n\tXFS_QLOWSP_1_PCNT = 0,\n\tXFS_QLOWSP_3_PCNT = 1,\n\tXFS_QLOWSP_5_PCNT = 2,\n\tXFS_QLOWSP_MAX = 3,\n};\n\nenum {\n\tXFS_QM_TRANS_USR = 0,\n\tXFS_QM_TRANS_GRP = 1,\n\tXFS_QM_TRANS_PRJ = 2,\n\tXFS_QM_TRANS_DQTYPES = 3,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tZONELIST_NOFALLBACK = 1,\n\tMAX_ZONELISTS = 2,\n};\n\nenum {\n\tZSTDbss_compress = 0,\n\tZSTDbss_noCompress = 1,\n};\n\nenum {\n\t_DQUOT_USAGE_ENABLED = 0,\n\t_DQUOT_LIMITS_ENABLED = 1,\n\t_DQUOT_SUSPENDED = 2,\n\t_DQUOT_STATE_FLAGS = 3,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 0,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t_SET_MEMORY_RO_BIT = 0,\n\t_SET_MEMORY_RW_BIT = 1,\n\t_SET_MEMORY_NX_BIT = 2,\n\t_SET_MEMORY_X_BIT = 3,\n\t_SET_MEMORY_4K_BIT = 4,\n\t_SET_MEMORY_INV_BIT = 5,\n\t_SET_MEMORY_DEF_BIT = 6,\n};\n\nenum {\n\t__EXTENT_DIRTY_BIT = 0,\n\tEXTENT_DIRTY = 1,\n\t__EXTENT_DIRTY_SEQ = 0,\n\t__EXTENT_LOCKED_BIT = 1,\n\tEXTENT_LOCKED = 2,\n\t__EXTENT_LOCKED_SEQ = 1,\n\t__EXTENT_DIO_LOCKED_BIT = 2,\n\tEXTENT_DIO_LOCKED = 4,\n\t__EXTENT_DIO_LOCKED_SEQ = 2,\n\t__EXTENT_DIRTY_LOG1_BIT = 3,\n\tEXTENT_DIRTY_LOG1 = 8,\n\t__EXTENT_DIRTY_LOG1_SEQ = 3,\n\t__EXTENT_DIRTY_LOG2_BIT = 4,\n\tEXTENT_DIRTY_LOG2 = 16,\n\t__EXTENT_DIRTY_LOG2_SEQ = 4,\n\t__EXTENT_DELALLOC_BIT = 5,\n\tEXTENT_DELALLOC = 32,\n\t__EXTENT_DELALLOC_SEQ = 5,\n\t__EXTENT_DEFRAG_BIT = 6,\n\tEXTENT_DEFRAG = 64,\n\t__EXTENT_DEFRAG_SEQ = 6,\n\t__EXTENT_BOUNDARY_BIT = 7,\n\tEXTENT_BOUNDARY = 128,\n\t__EXTENT_BOUNDARY_SEQ = 7,\n\t__EXTENT_NODATASUM_BIT = 8,\n\tEXTENT_NODATASUM = 256,\n\t__EXTENT_NODATASUM_SEQ = 8,\n\t__EXTENT_CLEAR_META_RESV_BIT = 9,\n\tEXTENT_CLEAR_META_RESV = 512,\n\t__EXTENT_CLEAR_META_RESV_SEQ = 9,\n\t__EXTENT_NEED_WAIT_BIT = 10,\n\tEXTENT_NEED_WAIT = 1024,\n\t__EXTENT_NEED_WAIT_SEQ = 10,\n\t__EXTENT_NORESERVE_BIT = 11,\n\tEXTENT_NORESERVE = 2048,\n\t__EXTENT_NORESERVE_SEQ = 11,\n\t__EXTENT_QGROUP_RESERVED_BIT = 12,\n\tEXTENT_QGROUP_RESERVED = 4096,\n\t__EXTENT_QGROUP_RESERVED_SEQ = 12,\n\t__EXTENT_CLEAR_DATA_RESV_BIT = 13,\n\tEXTENT_CLEAR_DATA_RESV = 8192,\n\t__EXTENT_CLEAR_DATA_RESV_SEQ = 13,\n\t__EXTENT_DELALLOC_NEW_BIT = 14,\n\tEXTENT_DELALLOC_NEW = 16384,\n\t__EXTENT_DELALLOC_NEW_SEQ = 14,\n\t__EXTENT_FINISHING_ORDERED_BIT = 15,\n\tEXTENT_FINISHING_ORDERED = 32768,\n\t__EXTENT_FINISHING_ORDERED_SEQ = 15,\n\t__EXTENT_ADD_INODE_BYTES_BIT = 16,\n\tEXTENT_ADD_INODE_BYTES = 65536,\n\t__EXTENT_ADD_INODE_BYTES_SEQ = 16,\n\t__EXTENT_CLEAR_ALL_BITS_BIT = 17,\n\tEXTENT_CLEAR_ALL_BITS = 131072,\n\t__EXTENT_CLEAR_ALL_BITS_SEQ = 17,\n\t__EXTENT_NOWAIT_BIT = 18,\n\tEXTENT_NOWAIT = 262144,\n\t__EXTENT_NOWAIT_SEQ = 18,\n};\n\nenum {\n\t__EXTENT_FLAG_PINNED_BIT = 0,\n\tEXTENT_FLAG_PINNED = 1,\n\t__EXTENT_FLAG_PINNED_SEQ = 0,\n\t__EXTENT_FLAG_COMPRESS_ZLIB_BIT = 1,\n\tEXTENT_FLAG_COMPRESS_ZLIB = 2,\n\t__EXTENT_FLAG_COMPRESS_ZLIB_SEQ = 1,\n\t__EXTENT_FLAG_COMPRESS_LZO_BIT = 2,\n\tEXTENT_FLAG_COMPRESS_LZO = 4,\n\t__EXTENT_FLAG_COMPRESS_LZO_SEQ = 2,\n\t__EXTENT_FLAG_COMPRESS_ZSTD_BIT = 3,\n\tEXTENT_FLAG_COMPRESS_ZSTD = 8,\n\t__EXTENT_FLAG_COMPRESS_ZSTD_SEQ = 3,\n\t__EXTENT_FLAG_PREALLOC_BIT = 4,\n\tEXTENT_FLAG_PREALLOC = 16,\n\t__EXTENT_FLAG_PREALLOC_SEQ = 4,\n\t__EXTENT_FLAG_LOGGING_BIT = 5,\n\tEXTENT_FLAG_LOGGING = 32,\n\t__EXTENT_FLAG_LOGGING_SEQ = 5,\n\t__EXTENT_FLAG_MERGED_BIT = 6,\n\tEXTENT_FLAG_MERGED = 64,\n\t__EXTENT_FLAG_MERGED_SEQ = 6,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PAGE_UNLOCK_BIT = 0,\n\tPAGE_UNLOCK = 1,\n\t__PAGE_UNLOCK_SEQ = 0,\n\t__PAGE_START_WRITEBACK_BIT = 1,\n\tPAGE_START_WRITEBACK = 2,\n\t__PAGE_START_WRITEBACK_SEQ = 1,\n\t__PAGE_END_WRITEBACK_BIT = 2,\n\tPAGE_END_WRITEBACK = 4,\n\t__PAGE_END_WRITEBACK_SEQ = 2,\n\t__PAGE_SET_ORDERED_BIT = 3,\n\tPAGE_SET_ORDERED = 8,\n\t__PAGE_SET_ORDERED_SEQ = 3,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__QGROUP_RESERVE_BIT = 0,\n\tQGROUP_RESERVE = 1,\n\t__QGROUP_RESERVE_SEQ = 0,\n\t__QGROUP_RELEASE_BIT = 1,\n\tQGROUP_RELEASE = 2,\n\t__QGROUP_RELEASE_SEQ = 1,\n\t__QGROUP_FREE_BIT = 2,\n\tQGROUP_FREE = 4,\n\t__QGROUP_FREE_SEQ = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 10,\n\t__SCHED_FEAT_HRTICK = 11,\n\t__SCHED_FEAT_HRTICK_DL = 12,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 13,\n\t__SCHED_FEAT_TTWU_QUEUE = 14,\n\t__SCHED_FEAT_SIS_UTIL = 15,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 16,\n\t__SCHED_FEAT_RT_PUSH_IPI = 17,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 18,\n\t__SCHED_FEAT_LB_MIN = 19,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 20,\n\t__SCHED_FEAT_WA_IDLE = 21,\n\t__SCHED_FEAT_WA_WEIGHT = 22,\n\t__SCHED_FEAT_WA_BIAS = 23,\n\t__SCHED_FEAT_UTIL_EST = 24,\n\t__SCHED_FEAT_LATENCY_WARN = 25,\n\t__SCHED_FEAT_NI_RANDOM = 26,\n\t__SCHED_FEAT_NR = 27,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t__XBTS_lookup = 0,\n\t__XBTS_compare = 1,\n\t__XBTS_insrec = 2,\n\t__XBTS_delrec = 3,\n\t__XBTS_newroot = 4,\n\t__XBTS_killroot = 5,\n\t__XBTS_increment = 6,\n\t__XBTS_decrement = 7,\n\t__XBTS_lshift = 8,\n\t__XBTS_rshift = 9,\n\t__XBTS_split = 10,\n\t__XBTS_join = 11,\n\t__XBTS_alloc = 12,\n\t__XBTS_free = 13,\n\t__XBTS_moves = 14,\n\t__XBTS_MAX = 15,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NO_OBJ_EXT_BIT = 24,\n\t___GFP_LAST_BIT = 25,\n};\n\nenum {\n\t____TRANS_FREEZABLE_BIT = 0,\n\t__TRANS_FREEZABLE = 1,\n\t____TRANS_FREEZABLE_SEQ = 0,\n\t____TRANS_START_BIT = 1,\n\t__TRANS_START = 2,\n\t____TRANS_START_SEQ = 1,\n\t____TRANS_ATTACH_BIT = 2,\n\t__TRANS_ATTACH = 4,\n\t____TRANS_ATTACH_SEQ = 2,\n\t____TRANS_JOIN_BIT = 3,\n\t__TRANS_JOIN = 8,\n\t____TRANS_JOIN_SEQ = 3,\n\t____TRANS_JOIN_NOLOCK_BIT = 4,\n\t__TRANS_JOIN_NOLOCK = 16,\n\t____TRANS_JOIN_NOLOCK_SEQ = 4,\n\t____TRANS_DUMMY_BIT = 5,\n\t__TRANS_DUMMY = 32,\n\t____TRANS_DUMMY_SEQ = 5,\n\t____TRANS_JOIN_NOSTART_BIT = 6,\n\t__TRANS_JOIN_NOSTART = 64,\n\t____TRANS_JOIN_NOSTART_SEQ = 6,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SKB = 4,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK = 5,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 7,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 8,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 9,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 10,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 11,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 12,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 13,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 14,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 15,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 16,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 17,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 18,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 19,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 20,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_DEVICE = 21,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SYSCTL = 22,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCKOPT = 23,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 24,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 25,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 26,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 27,\n\t__ctx_convertBPF_PROG_TYPE_LSM = 28,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 29,\n\t__ctx_convertBPF_PROG_TYPE_NETFILTER = 30,\n\t__ctx_convert_unused = 31,\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_sra_exceeded_retry_limit = 5,\n\tattr_inode_readahead = 6,\n\tattr_trigger_test_error = 7,\n\tattr_first_error_time = 8,\n\tattr_last_error_time = 9,\n\tattr_clusters_in_group = 10,\n\tattr_mb_order = 11,\n\tattr_feature = 12,\n\tattr_pointer_pi = 13,\n\tattr_pointer_ui = 14,\n\tattr_pointer_ul = 15,\n\tattr_pointer_u64 = 16,\n\tattr_pointer_u8 = 17,\n\tattr_pointer_string = 18,\n\tattr_pointer_atomic = 19,\n\tattr_journal_task = 20,\n\tattr_err_report_sec = 21,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tbtrfs_bitmap_nr_uptodate = 0,\n\tbtrfs_bitmap_nr_dirty = 1,\n\tbtrfs_bitmap_nr_writeback = 2,\n\tbtrfs_bitmap_nr_ordered = 3,\n\tbtrfs_bitmap_nr_checked = 4,\n\tbtrfs_bitmap_nr_locked = 5,\n\tbtrfs_bitmap_nr_max = 6,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\tec_schedule = 0,\n\tec_call_function_single = 1,\n\tec_stop_cpu = 2,\n\tec_mcck_pending = 3,\n\tec_irq_work = 4,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\tmask_exec = 0,\n\tmask_write = 1,\n\tmask_read = 2,\n\tmask_append = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\nenum {\n\tsclp_init_state_uninitialized = 0,\n\tsclp_init_state_initializing = 1,\n\tsclp_init_state_initialized = 2,\n};\n\nenum {\n\tscrub_bitmap_nr_has_extent = 0,\n\tscrub_bitmap_nr_is_metadata = 1,\n\tscrub_bitmap_nr_error = 2,\n\tscrub_bitmap_nr_io_error = 3,\n\tscrub_bitmap_nr_csum_error = 4,\n\tscrub_bitmap_nr_meta_error = 5,\n\tscrub_bitmap_nr_meta_gen_error = 6,\n\tscrub_bitmap_nr_last = 7,\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tFSE_repeat_none = 0,\n\tFSE_repeat_check = 1,\n\tFSE_repeat_valid = 2,\n} FSE_repeat;\n\ntypedef enum {\n\ttrustInput = 0,\n\tcheckMaxSymbolValue = 1,\n} HIST_checkInput_e;\n\ntypedef enum {\n\tHUF_singleStream = 0,\n\tHUF_fourStreams = 1,\n} HUF_nbStreams_e;\n\ntypedef enum {\n\tHUF_repeat_none = 0,\n\tHUF_repeat_check = 1,\n\tHUF_repeat_valid = 2,\n} HUF_repeat;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_cpm_noAttachDict = 0,\n\tZSTD_cpm_attachDict = 1,\n\tZSTD_cpm_createCDict = 2,\n\tZSTD_cpm_unknown = 3,\n} ZSTD_CParamMode_e;\n\ntypedef enum {\n\tZSTD_defaultDisallowed = 0,\n\tZSTD_defaultAllowed = 1,\n} ZSTD_DefaultPolicy_e;\n\ntypedef enum {\n\tZSTD_e_continue = 0,\n\tZSTD_e_flush = 1,\n\tZSTD_e_end = 2,\n} ZSTD_EndDirective;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tzop_dynamic = 0,\n\tzop_predef = 1,\n} ZSTD_OptPrice_e;\n\ntypedef enum {\n\tZSTD_ps_auto = 0,\n\tZSTD_ps_enable = 1,\n\tZSTD_ps_disable = 2,\n} ZSTD_ParamSwitch_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_sf_noBlockDelimiters = 0,\n\tZSTD_sf_explicitBlockDelimiters = 1,\n} ZSTD_SequenceFormat_e;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTDb_not_buffered = 0,\n\tZSTDb_buffered = 1,\n} ZSTD_buffered_policy_e;\n\ntypedef enum {\n\tZSTD_c_compressionLevel = 100,\n\tZSTD_c_windowLog = 101,\n\tZSTD_c_hashLog = 102,\n\tZSTD_c_chainLog = 103,\n\tZSTD_c_searchLog = 104,\n\tZSTD_c_minMatch = 105,\n\tZSTD_c_targetLength = 106,\n\tZSTD_c_strategy = 107,\n\tZSTD_c_targetCBlockSize = 130,\n\tZSTD_c_enableLongDistanceMatching = 160,\n\tZSTD_c_ldmHashLog = 161,\n\tZSTD_c_ldmMinMatch = 162,\n\tZSTD_c_ldmBucketSizeLog = 163,\n\tZSTD_c_ldmHashRateLog = 164,\n\tZSTD_c_contentSizeFlag = 200,\n\tZSTD_c_checksumFlag = 201,\n\tZSTD_c_dictIDFlag = 202,\n\tZSTD_c_nbWorkers = 400,\n\tZSTD_c_jobSize = 401,\n\tZSTD_c_overlapLog = 402,\n\tZSTD_c_experimentalParam1 = 500,\n\tZSTD_c_experimentalParam2 = 10,\n\tZSTD_c_experimentalParam3 = 1000,\n\tZSTD_c_experimentalParam4 = 1001,\n\tZSTD_c_experimentalParam5 = 1002,\n\tZSTD_c_experimentalParam7 = 1004,\n\tZSTD_c_experimentalParam8 = 1005,\n\tZSTD_c_experimentalParam9 = 1006,\n\tZSTD_c_experimentalParam10 = 1007,\n\tZSTD_c_experimentalParam11 = 1008,\n\tZSTD_c_experimentalParam12 = 1009,\n\tZSTD_c_experimentalParam13 = 1010,\n\tZSTD_c_experimentalParam14 = 1011,\n\tZSTD_c_experimentalParam15 = 1012,\n\tZSTD_c_experimentalParam16 = 1013,\n\tZSTD_c_experimentalParam17 = 1014,\n\tZSTD_c_experimentalParam18 = 1015,\n\tZSTD_c_experimentalParam19 = 1016,\n\tZSTD_c_experimentalParam20 = 1017,\n} ZSTD_cParameter;\n\ntypedef enum {\n\tzcss_init = 0,\n\tzcss_load = 1,\n\tzcss_flush = 2,\n} ZSTD_cStreamStage;\n\ntypedef enum {\n\tZSTDcrp_makeClean = 0,\n\tZSTDcrp_leaveDirty = 1,\n} ZSTD_compResetPolicy_e;\n\ntypedef enum {\n\tZSTDcs_created = 0,\n\tZSTDcs_init = 1,\n\tZSTDcs_ongoing = 2,\n\tZSTDcs_ending = 3,\n} ZSTD_compressionStage_e;\n\ntypedef enum {\n\tZSTD_cwksp_alloc_objects = 0,\n\tZSTD_cwksp_alloc_aligned_init_once = 1,\n\tZSTD_cwksp_alloc_aligned = 2,\n\tZSTD_cwksp_alloc_buffers = 3,\n} ZSTD_cwksp_alloc_phase_e;\n\ntypedef enum {\n\tZSTD_cwksp_dynamic_alloc = 0,\n\tZSTD_cwksp_static_alloc = 1,\n} ZSTD_cwksp_static_alloc_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dictDefaultAttach = 0,\n\tZSTD_dictForceAttach = 1,\n\tZSTD_dictForceCopy = 2,\n\tZSTD_dictForceLoad = 3,\n} ZSTD_dictAttachPref_e;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_noDict = 0,\n\tZSTD_extDict = 1,\n\tZSTD_dictMatchState = 2,\n\tZSTD_dedicatedDictSearch = 3,\n} ZSTD_dictMode_e;\n\ntypedef enum {\n\tZSTD_dtlm_fast = 0,\n\tZSTD_dtlm_full = 1,\n} ZSTD_dictTableLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTDirp_continue = 0,\n\tZSTDirp_reset = 1,\n} ZSTD_indexResetPolicy_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_llt_none = 0,\n\tZSTD_llt_literalLength = 1,\n\tZSTD_llt_matchLength = 2,\n} ZSTD_longLengthType_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tZSTD_resetTarget_CDict = 0,\n\tZSTD_resetTarget_CCtx = 1,\n} ZSTD_resetTarget_e;\n\ntypedef enum {\n\tZSTD_fast = 1,\n\tZSTD_dfast = 2,\n\tZSTD_greedy = 3,\n\tZSTD_lazy = 4,\n\tZSTD_lazy2 = 5,\n\tZSTD_btlazy2 = 6,\n\tZSTD_btopt = 7,\n\tZSTD_btultra = 8,\n\tZSTD_btultra2 = 9,\n} ZSTD_strategy;\n\ntypedef enum {\n\tZSTD_tfp_forCCtx = 0,\n\tZSTD_tfp_forCDict = 1,\n} ZSTD_tableFillPurpose_e;\n\ntypedef enum {\n\tbase_0possible = 0,\n\tbase_1guaranteed = 1,\n} base_directive_e;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tneed_more = 0,\n\tblock_done = 1,\n\tfinish_started = 2,\n\tfinish_done = 3,\n} block_state;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tDFLTCC_CC_OK = 0,\n\tDFLTCC_CC_OP1_TOO_SHORT = 1,\n\tDFLTCC_CC_OP2_TOO_SHORT = 2,\n\tDFLTCC_CC_OP2_CORRUPT = 2,\n\tDFLTCC_CC_AGAIN = 3,\n} dfltcc_cc;\n\ntypedef enum {\n\tDFLTCC_INFLATE_CONTINUE = 0,\n\tDFLTCC_INFLATE_BREAK = 1,\n\tDFLTCC_INFLATE_SOFTWARE = 2,\n} dfltcc_inflate_action;\n\ntypedef enum {\n\tnoDictIssue = 0,\n\tdictSmall = 1,\n} dictIssue_directive;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n\tEXT4_IGET_BAD = 4,\n\tEXT4_IGET_EA_INODE = 8,\n} ext4_iget_flags;\n\ntypedef enum {\n\tFS_DECRYPT = 0,\n\tFS_ENCRYPT = 1,\n} fscrypt_direction_t;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tnoLimit = 0,\n\tlimitedOutput = 1,\n} limitedOutput_directive;\n\ntypedef enum {\n\tMAP_CHG_REUSE = 0,\n\tMAP_CHG_NEEDED = 1,\n\tMAP_CHG_ENFORCED = 2,\n} map_chg_state;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tadd = 0,\n\tfree = 1,\n} range_action;\n\ntypedef enum {\n\tsearch_hashChain = 0,\n\tsearch_binaryTree = 1,\n\tsearch_rowHash = 2,\n} searchMethod_e;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tSTATUSTYPE_INFO = 0,\n\tSTATUSTYPE_TABLE = 1,\n\tSTATUSTYPE_IMA = 2,\n} status_type_t;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef enum {\n\tbyPtr = 0,\n\tbyU32 = 1,\n\tbyU16 = 2,\n} tableType_t;\n\ntypedef enum {\n\tXFS_EXT_NORM = 0,\n\tXFS_EXT_UNWRITTEN = 1,\n} xfs_exntst_t;\n\ntypedef enum {\n\tXFS_LOOKUP_EQi = 0,\n\tXFS_LOOKUP_LEi = 1,\n\tXFS_LOOKUP_GEi = 2,\n} xfs_lookup_t;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecPublicKey = 2,\n\tOID_id_prime192v1 = 3,\n\tOID_id_prime256v1 = 4,\n\tOID_id_ecdsa_with_sha1 = 5,\n\tOID_id_ecdsa_with_sha224 = 6,\n\tOID_id_ecdsa_with_sha256 = 7,\n\tOID_id_ecdsa_with_sha384 = 8,\n\tOID_id_ecdsa_with_sha512 = 9,\n\tOID_rsaEncryption = 10,\n\tOID_sha1WithRSAEncryption = 11,\n\tOID_sha256WithRSAEncryption = 12,\n\tOID_sha384WithRSAEncryption = 13,\n\tOID_sha512WithRSAEncryption = 14,\n\tOID_sha224WithRSAEncryption = 15,\n\tOID_data = 16,\n\tOID_signed_data = 17,\n\tOID_email_address = 18,\n\tOID_contentType = 19,\n\tOID_messageDigest = 20,\n\tOID_signingTime = 21,\n\tOID_smimeCapabilites = 22,\n\tOID_smimeAuthenticatedAttrs = 23,\n\tOID_mskrb5 = 24,\n\tOID_krb5 = 25,\n\tOID_krb5u2u = 26,\n\tOID_msIndirectData = 27,\n\tOID_msStatementType = 28,\n\tOID_msSpOpusInfo = 29,\n\tOID_msPeImageDataObjId = 30,\n\tOID_msIndividualSPKeyPurpose = 31,\n\tOID_msOutlookExpress = 32,\n\tOID_ntlmssp = 33,\n\tOID_negoex = 34,\n\tOID_spnego = 35,\n\tOID_IAKerb = 36,\n\tOID_PKU2U = 37,\n\tOID_Scram = 38,\n\tOID_certAuthInfoAccess = 39,\n\tOID_sha1 = 40,\n\tOID_id_ansip384r1 = 41,\n\tOID_id_ansip521r1 = 42,\n\tOID_sha256 = 43,\n\tOID_sha384 = 44,\n\tOID_sha512 = 45,\n\tOID_sha224 = 46,\n\tOID_commonName = 47,\n\tOID_surname = 48,\n\tOID_countryName = 49,\n\tOID_locality = 50,\n\tOID_stateOrProvinceName = 51,\n\tOID_organizationName = 52,\n\tOID_organizationUnitName = 53,\n\tOID_title = 54,\n\tOID_description = 55,\n\tOID_name = 56,\n\tOID_givenName = 57,\n\tOID_initials = 58,\n\tOID_generationalQualifier = 59,\n\tOID_subjectKeyIdentifier = 60,\n\tOID_keyUsage = 61,\n\tOID_subjectAltName = 62,\n\tOID_issuerAltName = 63,\n\tOID_basicConstraints = 64,\n\tOID_crlDistributionPoints = 65,\n\tOID_certPolicies = 66,\n\tOID_authorityKeyIdentifier = 67,\n\tOID_extKeyUsage = 68,\n\tOID_NetlogonMechanism = 69,\n\tOID_appleLocalKdcSupported = 70,\n\tOID_gostCPSignA = 71,\n\tOID_gostCPSignB = 72,\n\tOID_gostCPSignC = 73,\n\tOID_gost2012PKey256 = 74,\n\tOID_gost2012PKey512 = 75,\n\tOID_gost2012Digest256 = 76,\n\tOID_gost2012Digest512 = 77,\n\tOID_gost2012Signature256 = 78,\n\tOID_gost2012Signature512 = 79,\n\tOID_gostTC26Sign256A = 80,\n\tOID_gostTC26Sign256B = 81,\n\tOID_gostTC26Sign256C = 82,\n\tOID_gostTC26Sign256D = 83,\n\tOID_gostTC26Sign512A = 84,\n\tOID_gostTC26Sign512B = 85,\n\tOID_gostTC26Sign512C = 86,\n\tOID_sm2 = 87,\n\tOID_sm3 = 88,\n\tOID_SM2_with_SM3 = 89,\n\tOID_sm3WithRSAEncryption = 90,\n\tOID_TPMLoadableKey = 91,\n\tOID_TPMImportableKey = 92,\n\tOID_TPMSealedData = 93,\n\tOID_sha3_256 = 94,\n\tOID_sha3_384 = 95,\n\tOID_sha3_512 = 96,\n\tOID_id_ecdsa_with_sha3_256 = 97,\n\tOID_id_ecdsa_with_sha3_384 = 98,\n\tOID_id_ecdsa_with_sha3_512 = 99,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102,\n\tOID_id_ml_dsa_44 = 103,\n\tOID_id_ml_dsa_65 = 104,\n\tOID_id_ml_dsa_87 = 105,\n\tOID__NR = 106,\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nenum TPM_OPS_FLAGS {\n\tTPM_OPS_AUTO_STARTUP = 1,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _record_type {\n\t_START_RECORD = 0,\n\t_COMMIT_RECORD = 1,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_ACCOUNT = 13,\n\t_SLAB_NO_USER_FLAGS = 14,\n\t_SLAB_RECLAIM_ACCOUNT = 15,\n\t_SLAB_OBJECT_POISON = 16,\n\t_SLAB_CMPXCHG_DOUBLE = 17,\n\t_SLAB_NO_OBJ_EXT = 18,\n\t_SLAB_OBJ_EXT_IN_OBJ = 19,\n\t_SLAB_FLAGS_LAST_BIT = 20,\n};\n\nenum access_coordinate_class {\n\tACCESS_COORDINATE_LOCAL = 0,\n\tACCESS_COORDINATE_CPU = 1,\n\tACCESS_COORDINATE_MAX = 2,\n};\n\nenum action_id {\n\tACTION_SAVE = 1,\n\tACTION_TRACE = 2,\n\tACTION_SNAPSHOT = 3,\n};\n\nenum actions {\n\tREGISTER = 0,\n\tDEREGISTER = 1,\n\tCPU_DONT_CARE = 2,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum addr_type_t {\n\tUNICAST_ADDR = 0,\n\tMULTICAST_ADDR = 1,\n\tANYCAST_ADDR = 2,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum ap_dev_state {\n\tAP_DEV_STATE_UNINITIATED = 0,\n\tAP_DEV_STATE_OPERATING = 1,\n\tAP_DEV_STATE_SHUTDOWN = 2,\n\tAP_DEV_STATE_ERROR = 3,\n\tNR_AP_DEV_STATES = 4,\n};\n\nenum ap_sm_event {\n\tAP_SM_EVENT_POLL = 0,\n\tAP_SM_EVENT_TIMEOUT = 1,\n\tNR_AP_SM_EVENTS = 2,\n};\n\nenum ap_sm_state {\n\tAP_SM_STATE_RESET_START = 0,\n\tAP_SM_STATE_RESET_WAIT = 1,\n\tAP_SM_STATE_SETIRQ_WAIT = 2,\n\tAP_SM_STATE_IDLE = 3,\n\tAP_SM_STATE_WORKING = 4,\n\tAP_SM_STATE_QUEUE_FULL = 5,\n\tAP_SM_STATE_ASSOC_WAIT = 6,\n\tNR_AP_SM_STATES = 7,\n};\n\nenum ap_sm_wait {\n\tAP_SM_WAIT_AGAIN = 0,\n\tAP_SM_WAIT_HIGH_TIMEOUT = 1,\n\tAP_SM_WAIT_LOW_TIMEOUT = 2,\n\tAP_SM_WAIT_INTERRUPT = 3,\n\tAP_SM_WAIT_NONE = 4,\n\tNR_AP_SM_WAIT = 5,\n};\n\nenum arch_id {\n\tARCH_S390 = 0,\n\tARCH_S390X = 1,\n};\n\nenum array_state {\n\tclear = 0,\n\tinactive = 1,\n\tsuspended = 2,\n\treadonly = 3,\n\tread_auto = 4,\n\tclean = 5,\n\tactive = 6,\n\twrite_pending = 7,\n\tactive_idle = 8,\n\tbroken = 9,\n\tbad_word = 10,\n};\n\nenum asn1_class {\n\tASN1_UNIV = 0,\n\tASN1_APPL = 1,\n\tASN1_CONT = 2,\n\tASN1_PRIV = 3,\n};\n\nenum asn1_method {\n\tASN1_PRIM = 0,\n\tASN1_CONS = 1,\n};\n\nenum asn1_opcode {\n\tASN1_OP_MATCH = 0,\n\tASN1_OP_MATCH_OR_SKIP = 1,\n\tASN1_OP_MATCH_ACT = 2,\n\tASN1_OP_MATCH_ACT_OR_SKIP = 3,\n\tASN1_OP_MATCH_JUMP = 4,\n\tASN1_OP_MATCH_JUMP_OR_SKIP = 5,\n\tASN1_OP_MATCH_ANY = 8,\n\tASN1_OP_MATCH_ANY_OR_SKIP = 9,\n\tASN1_OP_MATCH_ANY_ACT = 10,\n\tASN1_OP_MATCH_ANY_ACT_OR_SKIP = 11,\n\tASN1_OP_COND_MATCH_OR_SKIP = 17,\n\tASN1_OP_COND_MATCH_ACT_OR_SKIP = 19,\n\tASN1_OP_COND_MATCH_JUMP_OR_SKIP = 21,\n\tASN1_OP_COND_MATCH_ANY = 24,\n\tASN1_OP_COND_MATCH_ANY_OR_SKIP = 25,\n\tASN1_OP_COND_MATCH_ANY_ACT = 26,\n\tASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 27,\n\tASN1_OP_COND_FAIL = 28,\n\tASN1_OP_COMPLETE = 29,\n\tASN1_OP_ACT = 30,\n\tASN1_OP_MAYBE_ACT = 31,\n\tASN1_OP_END_SEQ = 32,\n\tASN1_OP_END_SET = 33,\n\tASN1_OP_END_SEQ_OF = 34,\n\tASN1_OP_END_SET_OF = 35,\n\tASN1_OP_END_SEQ_ACT = 36,\n\tASN1_OP_END_SET_ACT = 37,\n\tASN1_OP_END_SEQ_OF_ACT = 38,\n\tASN1_OP_END_SET_OF_ACT = 39,\n\tASN1_OP_RETURN = 40,\n\tASN1_OP__NR = 41,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum asymmetric_payload_bits {\n\tasym_crypto = 0,\n\tasym_subtype = 1,\n\tasym_key_ids = 2,\n\tasym_auth = 3,\n};\n\nenum audit_nfcfgop {\n\tAUDIT_XT_OP_REGISTER = 0,\n\tAUDIT_XT_OP_REPLACE = 1,\n\tAUDIT_XT_OP_UNREGISTER = 2,\n\tAUDIT_NFT_OP_TABLE_REGISTER = 3,\n\tAUDIT_NFT_OP_TABLE_UNREGISTER = 4,\n\tAUDIT_NFT_OP_CHAIN_REGISTER = 5,\n\tAUDIT_NFT_OP_CHAIN_UNREGISTER = 6,\n\tAUDIT_NFT_OP_RULE_REGISTER = 7,\n\tAUDIT_NFT_OP_RULE_UNREGISTER = 8,\n\tAUDIT_NFT_OP_SET_REGISTER = 9,\n\tAUDIT_NFT_OP_SET_UNREGISTER = 10,\n\tAUDIT_NFT_OP_SETELEM_REGISTER = 11,\n\tAUDIT_NFT_OP_SETELEM_UNREGISTER = 12,\n\tAUDIT_NFT_OP_GEN_REGISTER = 13,\n\tAUDIT_NFT_OP_OBJ_REGISTER = 14,\n\tAUDIT_NFT_OP_OBJ_UNREGISTER = 15,\n\tAUDIT_NFT_OP_OBJ_RESET = 16,\n\tAUDIT_NFT_OP_FLOWTABLE_REGISTER = 17,\n\tAUDIT_NFT_OP_FLOWTABLE_UNREGISTER = 18,\n\tAUDIT_NFT_OP_SETELEM_RESET = 19,\n\tAUDIT_NFT_OP_RULE_RESET = 20,\n\tAUDIT_NFT_OP_INVALID = 21,\n};\n\nenum audit_nlgrps {\n\tAUDIT_NLGRP_NONE = 0,\n\tAUDIT_NLGRP_READLOG = 1,\n\t__AUDIT_NLGRP_MAX = 2,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum audit_state {\n\tAUDIT_STATE_DISABLED = 0,\n\tAUDIT_STATE_BUILD = 1,\n\tAUDIT_STATE_RECORD = 2,\n};\n\nenum auditsc_class_t {\n\tAUDITSC_NATIVE = 0,\n\tAUDITSC_COMPAT = 1,\n\tAUDITSC_OPEN = 2,\n\tAUDITSC_OPENAT = 3,\n\tAUDITSC_SOCKETCALL = 4,\n\tAUDITSC_EXECVE = 5,\n\tAUDITSC_OPENAT2 = 6,\n\tAUDITSC_NVALS = 7,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bfqq_expiration {\n\tBFQQE_TOO_IDLE = 0,\n\tBFQQE_BUDGET_TIMEOUT = 1,\n\tBFQQE_BUDGET_EXHAUSTED = 2,\n\tBFQQE_NO_MORE_REQUESTS = 3,\n\tBFQQE_PREEMPTED = 4,\n};\n\nenum bfqq_state_flags {\n\tBFQQF_just_created = 0,\n\tBFQQF_busy = 1,\n\tBFQQF_wait_request = 2,\n\tBFQQF_non_blocking_wait_rq = 3,\n\tBFQQF_fifo_expire = 4,\n\tBFQQF_has_short_ttime = 5,\n\tBFQQF_sync = 6,\n\tBFQQF_IO_bound = 7,\n\tBFQQF_in_large_burst = 8,\n\tBFQQF_softrt_update = 9,\n\tBFQQF_coop = 10,\n\tBFQQF_split_coop = 11,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum bitmap_page_attr {\n\tBITMAP_PAGE_DIRTY = 0,\n\tBITMAP_PAGE_PENDING = 1,\n\tBITMAP_PAGE_NEEDWRITE = 2,\n};\n\nenum bitmap_state {\n\tBITMAP_STALE = 1,\n\tBITMAP_WRITE_ERROR = 2,\n\tBITMAP_FIRST_USE = 3,\n\tBITMAP_CLEAN = 4,\n\tBITMAP_DAEMON_BUSY = 5,\n\tBITMAP_HOSTENDIAN = 15,\n};\n\nenum blacklist_hash_type {\n\tBLACKLIST_HASH_X509_TBS = 1,\n\tBLACKLIST_HASH_BINARY = 2,\n};\n\nenum blake2b_iv {\n\tBLAKE2B_IV0 = 7640891576956012808ULL,\n\tBLAKE2B_IV1 = 13503953896175478587ULL,\n\tBLAKE2B_IV2 = 4354685564936845355ULL,\n\tBLAKE2B_IV3 = 11912009170470909681ULL,\n\tBLAKE2B_IV4 = 5840696475078001361ULL,\n\tBLAKE2B_IV5 = 11170449401992604703ULL,\n\tBLAKE2B_IV6 = 2270897969802886507ULL,\n\tBLAKE2B_IV7 = 6620516959819538809ULL,\n};\n\nenum blake2b_lengths {\n\tBLAKE2B_BLOCK_SIZE = 128,\n\tBLAKE2B_HASH_SIZE = 64,\n\tBLAKE2B_KEY_SIZE = 64,\n\tBLAKE2B_160_HASH_SIZE = 20,\n\tBLAKE2B_256_HASH_SIZE = 32,\n\tBLAKE2B_384_HASH_SIZE = 48,\n\tBLAKE2B_512_HASH_SIZE = 64,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blk_zone_cond {\n\tBLK_ZONE_COND_NOT_WP = 0,\n\tBLK_ZONE_COND_EMPTY = 1,\n\tBLK_ZONE_COND_IMP_OPEN = 2,\n\tBLK_ZONE_COND_EXP_OPEN = 3,\n\tBLK_ZONE_COND_CLOSED = 4,\n\tBLK_ZONE_COND_READONLY = 13,\n\tBLK_ZONE_COND_FULL = 14,\n\tBLK_ZONE_COND_OFFLINE = 15,\n\tBLK_ZONE_COND_ACTIVE = 255,\n};\n\nenum blk_zone_type {\n\tBLK_ZONE_TYPE_CONVENTIONAL = 1,\n\tBLK_ZONE_TYPE_SEQWRITE_REQ = 2,\n\tBLK_ZONE_TYPE_SEQWRITE_PREF = 3,\n};\n\nenum blkg_iostat_type {\n\tBLKG_IOSTAT_READ = 0,\n\tBLKG_IOSTAT_WRITE = 1,\n\tBLKG_IOSTAT_DISCARD = 2,\n\tBLKG_IOSTAT_NR = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum blktrace_cat {\n\tBLK_TC_READ = 1,\n\tBLK_TC_WRITE = 2,\n\tBLK_TC_FLUSH = 4,\n\tBLK_TC_SYNC = 8,\n\tBLK_TC_SYNCIO = 8,\n\tBLK_TC_QUEUE = 16,\n\tBLK_TC_REQUEUE = 32,\n\tBLK_TC_ISSUE = 64,\n\tBLK_TC_COMPLETE = 128,\n\tBLK_TC_FS = 256,\n\tBLK_TC_PC = 512,\n\tBLK_TC_NOTIFY = 1024,\n\tBLK_TC_AHEAD = 2048,\n\tBLK_TC_META = 4096,\n\tBLK_TC_DISCARD = 8192,\n\tBLK_TC_DRV_DATA = 16384,\n\tBLK_TC_FUA = 32768,\n\tBLK_TC_END_V1 = 32768,\n\tBLK_TC_ZONE_APPEND = 65536,\n\tBLK_TC_ZONE_RESET = 131072,\n\tBLK_TC_ZONE_RESET_ALL = 262144,\n\tBLK_TC_ZONE_FINISH = 524288,\n\tBLK_TC_ZONE_OPEN = 1048576,\n\tBLK_TC_ZONE_CLOSE = 2097152,\n\tBLK_TC_WRITE_ZEROES = 4194304,\n\tBLK_TC_END_V2 = 4194304,\n};\n\nenum blktrace_notify {\n\t__BLK_TN_PROCESS = 0,\n\t__BLK_TN_TIMESTAMP = 1,\n\t__BLK_TN_MESSAGE = 2,\n\t__BLK_TN_CGROUP = 256,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_lwt_encap_mode {\n\tBPF_LWT_ENCAP_SEG6 = 0,\n\tBPF_LWT_ENCAP_SEG6_INLINE = 1,\n\tBPF_LWT_ENCAP_IP = 2,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_perf_event_type {\n\tBPF_PERF_EVENT_UNSPEC = 0,\n\tBPF_PERF_EVENT_UPROBE = 1,\n\tBPF_PERF_EVENT_URETPROBE = 2,\n\tBPF_PERF_EVENT_KPROBE = 3,\n\tBPF_PERF_EVENT_KRETPROBE = 4,\n\tBPF_PERF_EVENT_TRACEPOINT = 5,\n\tBPF_PERF_EVENT_EVENT = 6,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum br_boolopt_id {\n\tBR_BOOLOPT_NO_LL_LEARN = 0,\n\tBR_BOOLOPT_MCAST_VLAN_SNOOPING = 1,\n\tBR_BOOLOPT_MST_ENABLE = 2,\n\tBR_BOOLOPT_MDB_OFFLOAD_FAIL_NOTIFICATION = 3,\n\tBR_BOOLOPT_FDB_LOCAL_VLAN_0 = 4,\n\tBR_BOOLOPT_MAX = 5,\n};\n\nenum br_mrp_hw_support {\n\tBR_MRP_NONE = 0,\n\tBR_MRP_SW = 1,\n\tBR_MRP_HW = 2,\n};\n\nenum br_mrp_in_role_type {\n\tBR_MRP_IN_ROLE_DISABLED = 0,\n\tBR_MRP_IN_ROLE_MIC = 1,\n\tBR_MRP_IN_ROLE_MIM = 2,\n};\n\nenum br_mrp_in_state_type {\n\tBR_MRP_IN_STATE_OPEN = 0,\n\tBR_MRP_IN_STATE_CLOSED = 1,\n};\n\nenum br_mrp_port_role_type {\n\tBR_MRP_PORT_ROLE_PRIMARY = 0,\n\tBR_MRP_PORT_ROLE_SECONDARY = 1,\n\tBR_MRP_PORT_ROLE_INTER = 2,\n};\n\nenum br_mrp_port_state_type {\n\tBR_MRP_PORT_STATE_DISABLED = 0,\n\tBR_MRP_PORT_STATE_BLOCKED = 1,\n\tBR_MRP_PORT_STATE_FORWARDING = 2,\n\tBR_MRP_PORT_STATE_NOT_CONNECTED = 3,\n};\n\nenum br_mrp_ring_role_type {\n\tBR_MRP_RING_ROLE_DISABLED = 0,\n\tBR_MRP_RING_ROLE_MRC = 1,\n\tBR_MRP_RING_ROLE_MRM = 2,\n\tBR_MRP_RING_ROLE_MRA = 3,\n};\n\nenum br_mrp_ring_state_type {\n\tBR_MRP_RING_STATE_OPEN = 0,\n\tBR_MRP_RING_STATE_CLOSED = 1,\n};\n\nenum br_mrp_sub_tlv_header_type {\n\tBR_MRP_SUB_TLV_HEADER_TEST_MGR_NACK = 1,\n\tBR_MRP_SUB_TLV_HEADER_TEST_PROPAGATE = 2,\n\tBR_MRP_SUB_TLV_HEADER_TEST_AUTO_MGR = 3,\n};\n\nenum br_mrp_tlv_header_type {\n\tBR_MRP_TLV_HEADER_END = 0,\n\tBR_MRP_TLV_HEADER_COMMON = 1,\n\tBR_MRP_TLV_HEADER_RING_TEST = 2,\n\tBR_MRP_TLV_HEADER_RING_TOPO = 3,\n\tBR_MRP_TLV_HEADER_RING_LINK_DOWN = 4,\n\tBR_MRP_TLV_HEADER_RING_LINK_UP = 5,\n\tBR_MRP_TLV_HEADER_IN_TEST = 6,\n\tBR_MRP_TLV_HEADER_IN_TOPO = 7,\n\tBR_MRP_TLV_HEADER_IN_LINK_DOWN = 8,\n\tBR_MRP_TLV_HEADER_IN_LINK_UP = 9,\n\tBR_MRP_TLV_HEADER_IN_LINK_STATUS = 10,\n\tBR_MRP_TLV_HEADER_OPTION = 127,\n};\n\nenum br_pkt_type {\n\tBR_PKT_UNICAST = 0,\n\tBR_PKT_MULTICAST = 1,\n\tBR_PKT_BROADCAST = 2,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum btrfs_block_group_flags {\n\tBLOCK_GROUP_FLAG_IREF = 0,\n\tBLOCK_GROUP_FLAG_REMOVED = 1,\n\tBLOCK_GROUP_FLAG_TO_COPY = 2,\n\tBLOCK_GROUP_FLAG_RELOCATING_REPAIR = 3,\n\tBLOCK_GROUP_FLAG_CHUNK_ITEM_INSERTED = 4,\n\tBLOCK_GROUP_FLAG_ZONE_IS_ACTIVE = 5,\n\tBLOCK_GROUP_FLAG_ZONED_DATA_RELOC = 6,\n\tBLOCK_GROUP_FLAG_NEEDS_FREE_SPACE = 7,\n\tBLOCK_GROUP_FLAG_FREE_SPACE_ADDED = 8,\n\tBLOCK_GROUP_FLAG_SEQUENTIAL_ZONE = 9,\n\tBLOCK_GROUP_FLAG_NEW = 10,\n\tBLOCK_GROUP_FLAG_FULLY_REMAPPED = 11,\n\tBLOCK_GROUP_FLAG_STRIPE_REMOVAL_PENDING = 12,\n};\n\nenum btrfs_block_group_size_class {\n\tBTRFS_BG_SZ_NONE = 0,\n\tBTRFS_BG_SZ_SMALL = 1,\n\tBTRFS_BG_SZ_MEDIUM = 2,\n\tBTRFS_BG_SZ_LARGE = 3,\n};\n\nenum btrfs_caching_type {\n\tBTRFS_CACHE_NO = 0,\n\tBTRFS_CACHE_STARTED = 1,\n\tBTRFS_CACHE_FINISHED = 2,\n\tBTRFS_CACHE_ERROR = 3,\n};\n\nenum btrfs_chunk_alloc_enum {\n\tCHUNK_ALLOC_NO_FORCE = 0,\n\tCHUNK_ALLOC_LIMITED = 1,\n\tCHUNK_ALLOC_FORCE = 2,\n\tCHUNK_ALLOC_FORCE_FOR_EXTENT = 3,\n};\n\nenum btrfs_chunk_allocation_policy {\n\tBTRFS_CHUNK_ALLOC_REGULAR = 0,\n\tBTRFS_CHUNK_ALLOC_ZONED = 1,\n};\n\nenum btrfs_compare_tree_result {\n\tBTRFS_COMPARE_TREE_NEW = 0,\n\tBTRFS_COMPARE_TREE_DELETED = 1,\n\tBTRFS_COMPARE_TREE_CHANGED = 2,\n\tBTRFS_COMPARE_TREE_SAME = 3,\n};\n\nenum btrfs_compression_type {\n\tBTRFS_COMPRESS_NONE = 0,\n\tBTRFS_COMPRESS_ZLIB = 1,\n\tBTRFS_COMPRESS_LZO = 2,\n\tBTRFS_COMPRESS_ZSTD = 3,\n\tBTRFS_NR_COMPRESS_TYPES = 4,\n\tBTRFS_DEFRAG_DONT_COMPRESS = 5,\n};\n\nenum btrfs_csum_type {\n\tBTRFS_CSUM_TYPE_CRC32 = 0,\n\tBTRFS_CSUM_TYPE_XXHASH = 1,\n\tBTRFS_CSUM_TYPE_SHA256 = 2,\n\tBTRFS_CSUM_TYPE_BLAKE2 = 3,\n};\n\nenum btrfs_delayed_item_type {\n\tBTRFS_DELAYED_INSERTION_ITEM = 0,\n\tBTRFS_DELAYED_DELETION_ITEM = 1,\n};\n\nenum btrfs_delayed_ref_action {\n\tBTRFS_ADD_DELAYED_REF = 1,\n\tBTRFS_DROP_DELAYED_REF = 2,\n\tBTRFS_ADD_DELAYED_EXTENT = 3,\n\tBTRFS_UPDATE_DELAYED_HEAD = 4,\n} __attribute__((mode(byte)));\n\nenum btrfs_delayed_ref_flags {\n\tBTRFS_DELAYED_REFS_FLUSHING = 0,\n};\n\nenum btrfs_dev_stat_values {\n\tBTRFS_DEV_STAT_WRITE_ERRS = 0,\n\tBTRFS_DEV_STAT_READ_ERRS = 1,\n\tBTRFS_DEV_STAT_FLUSH_ERRS = 2,\n\tBTRFS_DEV_STAT_CORRUPTION_ERRS = 3,\n\tBTRFS_DEV_STAT_GENERATION_ERRS = 4,\n\tBTRFS_DEV_STAT_VALUES_MAX = 5,\n};\n\nenum btrfs_discard_state {\n\tBTRFS_DISCARD_EXTENTS = 0,\n\tBTRFS_DISCARD_BITMAPS = 1,\n\tBTRFS_DISCARD_RESET_CURSOR = 2,\n\tBTRFS_DISCARD_FULLY_REMAPPED = 3,\n};\n\nenum btrfs_disk_cache_state {\n\tBTRFS_DC_WRITTEN = 0,\n\tBTRFS_DC_ERROR = 1,\n\tBTRFS_DC_CLEAR = 2,\n\tBTRFS_DC_SETUP = 3,\n};\n\nenum btrfs_err_code {\n\tBTRFS_ERROR_DEV_RAID1_MIN_NOT_MET = 1,\n\tBTRFS_ERROR_DEV_RAID10_MIN_NOT_MET = 2,\n\tBTRFS_ERROR_DEV_RAID5_MIN_NOT_MET = 3,\n\tBTRFS_ERROR_DEV_RAID6_MIN_NOT_MET = 4,\n\tBTRFS_ERROR_DEV_TGT_REPLACE = 5,\n\tBTRFS_ERROR_DEV_MISSING_NOT_FOUND = 6,\n\tBTRFS_ERROR_DEV_ONLY_WRITABLE = 7,\n\tBTRFS_ERROR_DEV_EXCL_RUN_IN_PROGRESS = 8,\n\tBTRFS_ERROR_DEV_RAID1C3_MIN_NOT_MET = 9,\n\tBTRFS_ERROR_DEV_RAID1C4_MIN_NOT_MET = 10,\n};\n\nenum btrfs_exclusive_operation {\n\tBTRFS_EXCLOP_NONE = 0,\n\tBTRFS_EXCLOP_BALANCE_PAUSED = 1,\n\tBTRFS_EXCLOP_BALANCE = 2,\n\tBTRFS_EXCLOP_DEV_ADD = 3,\n\tBTRFS_EXCLOP_DEV_REMOVE = 4,\n\tBTRFS_EXCLOP_DEV_REPLACE = 5,\n\tBTRFS_EXCLOP_RESIZE = 6,\n\tBTRFS_EXCLOP_SWAP_ACTIVATE = 7,\n};\n\nenum btrfs_extent_allocation_policy {\n\tBTRFS_EXTENT_ALLOC_CLUSTERED = 0,\n\tBTRFS_EXTENT_ALLOC_ZONED = 1,\n};\n\nenum btrfs_feature_set {\n\tFEAT_COMPAT = 0,\n\tFEAT_COMPAT_RO = 1,\n\tFEAT_INCOMPAT = 2,\n\tFEAT_MAX = 3,\n};\n\nenum btrfs_flush_state {\n\tFLUSH_DELAYED_ITEMS_NR = 1,\n\tFLUSH_DELAYED_ITEMS = 2,\n\tFLUSH_DELAYED_REFS_NR = 3,\n\tFLUSH_DELAYED_REFS = 4,\n\tFLUSH_DELALLOC = 5,\n\tFLUSH_DELALLOC_WAIT = 6,\n\tFLUSH_DELALLOC_FULL = 7,\n\tALLOC_CHUNK = 8,\n\tALLOC_CHUNK_FORCE = 9,\n\tRUN_DELAYED_IPUTS = 10,\n\tCOMMIT_TRANS = 11,\n\tRESET_ZONES = 12,\n};\n\nenum btrfs_folio_type {\n\tBTRFS_SUBPAGE_METADATA = 0,\n\tBTRFS_SUBPAGE_DATA = 1,\n};\n\nenum btrfs_ilock_type {\n\t__BTRFS_ILOCK_SHARED_BIT = 0,\n\tBTRFS_ILOCK_SHARED = 1,\n\t__BTRFS_ILOCK_SHARED_SEQ = 0,\n\t__BTRFS_ILOCK_TRY_BIT = 1,\n\tBTRFS_ILOCK_TRY = 2,\n\t__BTRFS_ILOCK_TRY_SEQ = 1,\n\t__BTRFS_ILOCK_MMAP_BIT = 2,\n\tBTRFS_ILOCK_MMAP = 4,\n\t__BTRFS_ILOCK_MMAP_SEQ = 2,\n};\n\nenum btrfs_inline_ref_type {\n\tBTRFS_REF_TYPE_INVALID = 0,\n\tBTRFS_REF_TYPE_BLOCK = 1,\n\tBTRFS_REF_TYPE_DATA = 2,\n\tBTRFS_REF_TYPE_ANY = 3,\n};\n\nenum btrfs_lock_nesting {\n\tBTRFS_NESTING_NORMAL = 0,\n\tBTRFS_NESTING_COW = 1,\n\tBTRFS_NESTING_LEFT = 2,\n\tBTRFS_NESTING_RIGHT = 3,\n\tBTRFS_NESTING_LEFT_COW = 4,\n\tBTRFS_NESTING_RIGHT_COW = 5,\n\tBTRFS_NESTING_SPLIT = 6,\n\tBTRFS_NESTING_NEW_ROOT = 7,\n\tBTRFS_NESTING_MAX = 8,\n};\n\nenum btrfs_loop_type {\n\tLOOP_CACHING_NOWAIT = 0,\n\tLOOP_CACHING_WAIT = 1,\n\tLOOP_UNSET_SIZE_CLASS = 2,\n\tLOOP_ALLOC_CHUNK = 3,\n\tLOOP_WRONG_SIZE_CLASS = 4,\n\tLOOP_NO_EMPTY_SIZE = 5,\n};\n\nenum btrfs_map_op {\n\tBTRFS_MAP_READ = 0,\n\tBTRFS_MAP_WRITE = 1,\n\tBTRFS_MAP_GET_READ_MIRRORS = 2,\n};\n\nenum btrfs_mod_log_op {\n\tBTRFS_MOD_LOG_KEY_REPLACE = 0,\n\tBTRFS_MOD_LOG_KEY_ADD = 1,\n\tBTRFS_MOD_LOG_KEY_REMOVE = 2,\n\tBTRFS_MOD_LOG_KEY_REMOVE_WHILE_FREEING = 3,\n\tBTRFS_MOD_LOG_KEY_REMOVE_WHILE_MOVING = 4,\n\tBTRFS_MOD_LOG_MOVE_KEYS = 5,\n\tBTRFS_MOD_LOG_ROOT_REPLACE = 6,\n};\n\nenum btrfs_qgroup_mode {\n\tBTRFS_QGROUP_MODE_DISABLED = 0,\n\tBTRFS_QGROUP_MODE_FULL = 1,\n\tBTRFS_QGROUP_MODE_SIMPLE = 2,\n};\n\nenum btrfs_qgroup_rsv_type {\n\tBTRFS_QGROUP_RSV_DATA = 0,\n\tBTRFS_QGROUP_RSV_META_PERTRANS = 1,\n\tBTRFS_QGROUP_RSV_META_PREALLOC = 2,\n\tBTRFS_QGROUP_RSV_LAST = 3,\n};\n\nenum btrfs_raid_types {\n\tBTRFS_RAID_SINGLE = 0,\n\tBTRFS_RAID_RAID0 = 1,\n\tBTRFS_RAID_RAID1 = 2,\n\tBTRFS_RAID_DUP = 3,\n\tBTRFS_RAID_RAID10 = 4,\n\tBTRFS_RAID_RAID5 = 5,\n\tBTRFS_RAID_RAID6 = 6,\n\tBTRFS_RAID_RAID1C3 = 7,\n\tBTRFS_RAID_RAID1C4 = 8,\n\tBTRFS_NR_RAID_TYPES = 9,\n};\n\nenum btrfs_rbio_ops {\n\tBTRFS_RBIO_WRITE = 0,\n\tBTRFS_RBIO_READ_REBUILD = 1,\n\tBTRFS_RBIO_PARITY_SCRUB = 2,\n};\n\nenum btrfs_read_policy {\n\tBTRFS_READ_POLICY_PID = 0,\n\tBTRFS_NR_READ_POLICY = 1,\n};\n\nenum btrfs_ref_type {\n\tBTRFS_REF_NOT_SET = 0,\n\tBTRFS_REF_DATA = 1,\n\tBTRFS_REF_METADATA = 2,\n} __attribute__((mode(byte)));\n\nenum btrfs_reserve_flush_enum {\n\tBTRFS_RESERVE_NO_FLUSH = 0,\n\tBTRFS_RESERVE_FLUSH_LIMIT = 1,\n\tBTRFS_RESERVE_FLUSH_EVICT = 2,\n\tBTRFS_RESERVE_FLUSH_DATA = 3,\n\tBTRFS_RESERVE_FLUSH_FREE_SPACE_INODE = 4,\n\tBTRFS_RESERVE_FLUSH_ALL = 5,\n\tBTRFS_RESERVE_FLUSH_ALL_STEAL = 6,\n\tBTRFS_RESERVE_FLUSH_EMERGENCY = 7,\n};\n\nenum btrfs_rsv_type {\n\tBTRFS_BLOCK_RSV_GLOBAL = 0,\n\tBTRFS_BLOCK_RSV_DELALLOC = 1,\n\tBTRFS_BLOCK_RSV_TRANS = 2,\n\tBTRFS_BLOCK_RSV_CHUNK = 3,\n\tBTRFS_BLOCK_RSV_REMAP = 4,\n\tBTRFS_BLOCK_RSV_DELOPS = 5,\n\tBTRFS_BLOCK_RSV_DELREFS = 6,\n\tBTRFS_BLOCK_RSV_TREELOG = 7,\n\tBTRFS_BLOCK_RSV_EMPTY = 8,\n\tBTRFS_BLOCK_RSV_TEMP = 9,\n};\n\nenum btrfs_send_cmd {\n\tBTRFS_SEND_C_UNSPEC = 0,\n\tBTRFS_SEND_C_SUBVOL = 1,\n\tBTRFS_SEND_C_SNAPSHOT = 2,\n\tBTRFS_SEND_C_MKFILE = 3,\n\tBTRFS_SEND_C_MKDIR = 4,\n\tBTRFS_SEND_C_MKNOD = 5,\n\tBTRFS_SEND_C_MKFIFO = 6,\n\tBTRFS_SEND_C_MKSOCK = 7,\n\tBTRFS_SEND_C_SYMLINK = 8,\n\tBTRFS_SEND_C_RENAME = 9,\n\tBTRFS_SEND_C_LINK = 10,\n\tBTRFS_SEND_C_UNLINK = 11,\n\tBTRFS_SEND_C_RMDIR = 12,\n\tBTRFS_SEND_C_SET_XATTR = 13,\n\tBTRFS_SEND_C_REMOVE_XATTR = 14,\n\tBTRFS_SEND_C_WRITE = 15,\n\tBTRFS_SEND_C_CLONE = 16,\n\tBTRFS_SEND_C_TRUNCATE = 17,\n\tBTRFS_SEND_C_CHMOD = 18,\n\tBTRFS_SEND_C_CHOWN = 19,\n\tBTRFS_SEND_C_UTIMES = 20,\n\tBTRFS_SEND_C_END = 21,\n\tBTRFS_SEND_C_UPDATE_EXTENT = 22,\n\tBTRFS_SEND_C_MAX_V1 = 22,\n\tBTRFS_SEND_C_FALLOCATE = 23,\n\tBTRFS_SEND_C_FILEATTR = 24,\n\tBTRFS_SEND_C_ENCODED_WRITE = 25,\n\tBTRFS_SEND_C_MAX_V2 = 25,\n\tBTRFS_SEND_C_ENABLE_VERITY = 26,\n\tBTRFS_SEND_C_MAX_V3 = 26,\n\tBTRFS_SEND_C_MAX = 26,\n};\n\nenum btrfs_space_info_sub_group {\n\tBTRFS_SUB_GROUP_PRIMARY = 0,\n\tBTRFS_SUB_GROUP_DATA_RELOC = 1,\n\tBTRFS_SUB_GROUP_TREELOG = 2,\n};\n\nenum btrfs_trans_state {\n\tTRANS_STATE_RUNNING = 0,\n\tTRANS_STATE_COMMIT_PREP = 1,\n\tTRANS_STATE_COMMIT_START = 2,\n\tTRANS_STATE_COMMIT_DOING = 3,\n\tTRANS_STATE_UNBLOCKED = 4,\n\tTRANS_STATE_SUPER_COMMITTED = 5,\n\tTRANS_STATE_COMPLETED = 6,\n\tTRANS_STATE_MAX = 7,\n};\n\nenum btrfs_tree_block_status {\n\tBTRFS_TREE_BLOCK_CLEAN = 0,\n\tBTRFS_TREE_BLOCK_INVALID_NRITEMS = 1,\n\tBTRFS_TREE_BLOCK_INVALID_PARENT_KEY = 2,\n\tBTRFS_TREE_BLOCK_BAD_KEY_ORDER = 3,\n\tBTRFS_TREE_BLOCK_INVALID_LEVEL = 4,\n\tBTRFS_TREE_BLOCK_INVALID_FREE_SPACE = 5,\n\tBTRFS_TREE_BLOCK_INVALID_OFFSETS = 6,\n\tBTRFS_TREE_BLOCK_INVALID_BLOCKPTR = 7,\n\tBTRFS_TREE_BLOCK_INVALID_ITEM = 8,\n\tBTRFS_TREE_BLOCK_INVALID_OWNER = 9,\n\tBTRFS_TREE_BLOCK_WRITTEN_NOT_SET = 10,\n};\n\nenum btrfs_trim_state {\n\tBTRFS_TRIM_STATE_UNTRIMMED = 0,\n\tBTRFS_TRIM_STATE_TRIMMED = 1,\n\tBTRFS_TRIM_STATE_TRIMMING = 2,\n};\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum cc_attr {\n\tCC_ATTR_MEM_ENCRYPT = 0,\n\tCC_ATTR_HOST_MEM_ENCRYPT = 1,\n\tCC_ATTR_GUEST_MEM_ENCRYPT = 2,\n\tCC_ATTR_GUEST_STATE_ENCRYPT = 3,\n\tCC_ATTR_GUEST_UNROLL_STRING_IO = 4,\n\tCC_ATTR_GUEST_SEV_SNP = 5,\n\tCC_ATTR_GUEST_SNP_SECURE_TSC = 6,\n\tCC_ATTR_HOST_SEV_SNP = 7,\n\tCC_ATTR_SNP_SECURE_AVIC = 8,\n};\n\nenum cdev_todo {\n\tCDEV_TODO_NOTHING = 0,\n\tCDEV_TODO_ENABLE_CMF = 1,\n\tCDEV_TODO_REBIND = 2,\n\tCDEV_TODO_REGISTER = 3,\n\tCDEV_TODO_UNREG = 4,\n\tCDEV_TODO_UNREG_EVAL = 5,\n};\n\nenum cfg_task_t {\n\tcfg_none = 0,\n\tcfg_configure = 1,\n\tcfg_deconfigure = 2,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_bpf_attach_type {\n\tCGROUP_BPF_ATTACH_TYPE_INVALID = -1,\n\tCGROUP_INET_INGRESS = 0,\n\tCGROUP_INET_EGRESS = 1,\n\tCGROUP_INET_SOCK_CREATE = 2,\n\tCGROUP_SOCK_OPS = 3,\n\tCGROUP_DEVICE = 4,\n\tCGROUP_INET4_BIND = 5,\n\tCGROUP_INET6_BIND = 6,\n\tCGROUP_INET4_CONNECT = 7,\n\tCGROUP_INET6_CONNECT = 8,\n\tCGROUP_UNIX_CONNECT = 9,\n\tCGROUP_INET4_POST_BIND = 10,\n\tCGROUP_INET6_POST_BIND = 11,\n\tCGROUP_UDP4_SENDMSG = 12,\n\tCGROUP_UDP6_SENDMSG = 13,\n\tCGROUP_UNIX_SENDMSG = 14,\n\tCGROUP_SYSCTL = 15,\n\tCGROUP_UDP4_RECVMSG = 16,\n\tCGROUP_UDP6_RECVMSG = 17,\n\tCGROUP_UNIX_RECVMSG = 18,\n\tCGROUP_GETSOCKOPT = 19,\n\tCGROUP_SETSOCKOPT = 20,\n\tCGROUP_INET4_GETPEERNAME = 21,\n\tCGROUP_INET6_GETPEERNAME = 22,\n\tCGROUP_UNIX_GETPEERNAME = 23,\n\tCGROUP_INET4_GETSOCKNAME = 24,\n\tCGROUP_INET6_GETSOCKNAME = 25,\n\tCGROUP_UNIX_GETSOCKNAME = 26,\n\tCGROUP_INET_SOCK_RELEASE = 27,\n\tCGROUP_LSM_START = 28,\n\tCGROUP_LSM_END = 37,\n\tMAX_CGROUP_BPF_ATTACH_TYPE = 38,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_COUNT = 0,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tio_cgrp_id = 3,\n\tmemory_cgrp_id = 4,\n\tdevices_cgrp_id = 5,\n\tfreezer_cgrp_id = 6,\n\tnet_cls_cgrp_id = 7,\n\tperf_event_cgrp_id = 8,\n\tnet_prio_cgrp_id = 9,\n\thugetlb_cgrp_id = 10,\n\tpids_cgrp_id = 11,\n\trdma_cgrp_id = 12,\n\tmisc_cgrp_id = 13,\n\tCGROUP_SUBSYS_COUNT = 14,\n};\n\nenum chacha20poly1305_lengths {\n\tXCHACHA20POLY1305_NONCE_SIZE = 24,\n\tCHACHA20POLY1305_KEY_SIZE = 32,\n\tCHACHA20POLY1305_AUTHTAG_SIZE = 16,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum chsc_notify_type {\n\tCHSC_NOTIFY_AP_CFG = 3,\n};\n\nenum class_map_type {\n\tDD_CLASS_TYPE_DISJOINT_BITS = 0,\n\tDD_CLASS_TYPE_LEVEL_NUM = 1,\n\tDD_CLASS_TYPE_DISJOINT_NAMES = 2,\n\tDD_CLASS_TYPE_LEVEL_NAMES = 3,\n};\n\nenum class_stat_type {\n\tZS_OBJS_ALLOCATED = 12,\n\tZS_OBJS_INUSE = 13,\n\tNR_CLASS_STAT_TYPES = 14,\n};\n\nenum cleanup_prefix_rt_t {\n\tCLEANUP_PREFIX_RT_NOP = 0,\n\tCLEANUP_PREFIX_RT_DEL = 1,\n\tCLEANUP_PREFIX_RT_EXPIRE = 2,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum closure_state {\n\tCLOSURE_BITS_START = 67108864,\n\tCLOSURE_DESTRUCTOR = 67108864,\n\tCLOSURE_WAITING = 268435456,\n\tCLOSURE_RUNNING = 1073741824,\n};\n\nenum cma_flags {\n\tCMA_RESERVE_PAGES_ON_ERROR = 0,\n\tCMA_ZONES_VALID = 1,\n\tCMA_ZONES_INVALID = 2,\n\tCMA_ACTIVATED = 3,\n};\n\nenum cmb_format {\n\tCMF_BASIC = 0,\n\tCMF_EXTENDED = 1,\n\tCMF_AUTODETECT = -1,\n};\n\nenum cmb_index {\n\tavg_utilization = -1,\n\tcmb_ssch_rsch_count = 0,\n\tcmb_sample_count = 1,\n\tcmb_device_connect_time = 2,\n\tcmb_function_pending_time = 3,\n\tcmb_device_disconnect_time = 4,\n\tcmb_control_unit_queuing_time = 5,\n\tcmb_device_active_only_time = 6,\n\tcmb_device_busy_time = 7,\n\tcmb_initial_command_response_time = 8,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tCPUTIME_FORCEIDLE = 10,\n\tNR_STATS = 11,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum cpumf_ctr_set {\n\tCPUMF_CTR_SET_BASIC = 0,\n\tCPUMF_CTR_SET_USER = 1,\n\tCPUMF_CTR_SET_CRYPTO = 2,\n\tCPUMF_CTR_SET_EXT = 3,\n\tCPUMF_CTR_SET_MT_DIAG = 4,\n\tCPUMF_CTR_SET_MAX = 5,\n};\n\nenum criteria {\n\tCR_POWER2_ALIGNED = 0,\n\tCR_GOAL_LEN_FAST = 1,\n\tCR_BEST_AVAIL_LEN = 2,\n\tCR_GOAL_LEN_SLOW = 3,\n\tCR_ANY_FREE = 4,\n\tEXT4_MB_NUM_CRS = 5,\n};\n\nenum crypto_attr_type_t {\n\tCRYPTOCFGA_UNSPEC = 0,\n\tCRYPTOCFGA_PRIORITY_VAL = 1,\n\tCRYPTOCFGA_REPORT_LARVAL = 2,\n\tCRYPTOCFGA_REPORT_HASH = 3,\n\tCRYPTOCFGA_REPORT_BLKCIPHER = 4,\n\tCRYPTOCFGA_REPORT_AEAD = 5,\n\tCRYPTOCFGA_REPORT_COMPRESS = 6,\n\tCRYPTOCFGA_REPORT_RNG = 7,\n\tCRYPTOCFGA_REPORT_CIPHER = 8,\n\tCRYPTOCFGA_REPORT_AKCIPHER = 9,\n\tCRYPTOCFGA_REPORT_KPP = 10,\n\tCRYPTOCFGA_REPORT_ACOMP = 11,\n\tCRYPTOCFGA_STAT_LARVAL = 12,\n\tCRYPTOCFGA_STAT_HASH = 13,\n\tCRYPTOCFGA_STAT_BLKCIPHER = 14,\n\tCRYPTOCFGA_STAT_AEAD = 15,\n\tCRYPTOCFGA_STAT_COMPRESS = 16,\n\tCRYPTOCFGA_STAT_RNG = 17,\n\tCRYPTOCFGA_STAT_CIPHER = 18,\n\tCRYPTOCFGA_STAT_AKCIPHER = 19,\n\tCRYPTOCFGA_STAT_KPP = 20,\n\tCRYPTOCFGA_STAT_ACOMP = 21,\n\tCRYPTOCFGA_REPORT_SIG = 22,\n\t__CRYPTOCFGA_MAX = 23,\n};\n\nenum css_eval_cond {\n\tCSS_EVAL_NO_PATH = 0,\n\tCSS_EVAL_NOT_ONLINE = 1,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum data_formats {\n\tDATA_FMT_DIGEST = 0,\n\tDATA_FMT_DIGEST_WITH_ALGO = 1,\n\tDATA_FMT_DIGEST_WITH_TYPE_AND_ALGO = 2,\n\tDATA_FMT_STRING = 3,\n\tDATA_FMT_HEX = 4,\n\tDATA_FMT_UINT = 5,\n};\n\nenum dax_access_mode {\n\tDAX_ACCESS = 0,\n\tDAX_RECOVERY_WRITE = 1,\n};\n\nenum dax_device_flags {\n\tDAXDEV_ALIVE = 0,\n\tDAXDEV_WRITE_CACHE = 1,\n\tDAXDEV_SYNC = 2,\n\tDAXDEV_NOCACHE = 3,\n\tDAXDEV_NOMC = 4,\n};\n\nenum dax_driver_type {\n\tDAXDRV_KMEM_TYPE = 0,\n\tDAXDRV_DEVICE_TYPE = 1,\n};\n\nenum dax_wake_mode {\n\tWAKE_ALL = 0,\n\tWAKE_NEXT = 1,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum depot_counter_id {\n\tDEPOT_COUNTER_REFD_ALLOCS = 0,\n\tDEPOT_COUNTER_REFD_FREES = 1,\n\tDEPOT_COUNTER_REFD_INUSE = 2,\n\tDEPOT_COUNTER_FREELIST_SIZE = 3,\n\tDEPOT_COUNTER_PERSIST_COUNT = 4,\n\tDEPOT_COUNTER_PERSIST_BYTES = 5,\n\tDEPOT_COUNTER_COUNT = 6,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_event {\n\tDEV_EVENT_NOTOPER = 0,\n\tDEV_EVENT_INTERRUPT = 1,\n\tDEV_EVENT_TIMEOUT = 2,\n\tDEV_EVENT_VERIFY = 3,\n\tNR_DEV_EVENTS = 4,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum dev_state {\n\tDEV_STATE_NOT_OPER = 0,\n\tDEV_STATE_SENSE_ID = 1,\n\tDEV_STATE_OFFLINE = 2,\n\tDEV_STATE_VERIFY = 3,\n\tDEV_STATE_ONLINE = 4,\n\tDEV_STATE_W4SENSE = 5,\n\tDEV_STATE_DISBAND_PGID = 6,\n\tDEV_STATE_BOXED = 7,\n\tDEV_STATE_TIMEOUT_KILL = 8,\n\tDEV_STATE_QUIESCE = 9,\n\tDEV_STATE_DISCONNECTED = 10,\n\tDEV_STATE_DISCONNECTED_SENSE_ID = 11,\n\tDEV_STATE_CMFCHANGE = 12,\n\tDEV_STATE_CMFUPDATE = 13,\n\tDEV_STATE_STEAL_LOCK = 14,\n\tNR_DEV_STATES = 15,\n};\n\nenum devcg_behavior {\n\tDEVCG_DEFAULT_NONE = 0,\n\tDEVCG_DEFAULT_ALLOW = 1,\n\tDEVCG_DEFAULT_DENY = 2,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_attr {\n\tDEVLINK_ATTR_UNSPEC = 0,\n\tDEVLINK_ATTR_BUS_NAME = 1,\n\tDEVLINK_ATTR_DEV_NAME = 2,\n\tDEVLINK_ATTR_PORT_INDEX = 3,\n\tDEVLINK_ATTR_PORT_TYPE = 4,\n\tDEVLINK_ATTR_PORT_DESIRED_TYPE = 5,\n\tDEVLINK_ATTR_PORT_NETDEV_IFINDEX = 6,\n\tDEVLINK_ATTR_PORT_NETDEV_NAME = 7,\n\tDEVLINK_ATTR_PORT_IBDEV_NAME = 8,\n\tDEVLINK_ATTR_PORT_SPLIT_COUNT = 9,\n\tDEVLINK_ATTR_PORT_SPLIT_GROUP = 10,\n\tDEVLINK_ATTR_SB_INDEX = 11,\n\tDEVLINK_ATTR_SB_SIZE = 12,\n\tDEVLINK_ATTR_SB_INGRESS_POOL_COUNT = 13,\n\tDEVLINK_ATTR_SB_EGRESS_POOL_COUNT = 14,\n\tDEVLINK_ATTR_SB_INGRESS_TC_COUNT = 15,\n\tDEVLINK_ATTR_SB_EGRESS_TC_COUNT = 16,\n\tDEVLINK_ATTR_SB_POOL_INDEX = 17,\n\tDEVLINK_ATTR_SB_POOL_TYPE = 18,\n\tDEVLINK_ATTR_SB_POOL_SIZE = 19,\n\tDEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE = 20,\n\tDEVLINK_ATTR_SB_THRESHOLD = 21,\n\tDEVLINK_ATTR_SB_TC_INDEX = 22,\n\tDEVLINK_ATTR_SB_OCC_CUR = 23,\n\tDEVLINK_ATTR_SB_OCC_MAX = 24,\n\tDEVLINK_ATTR_ESWITCH_MODE = 25,\n\tDEVLINK_ATTR_ESWITCH_INLINE_MODE = 26,\n\tDEVLINK_ATTR_DPIPE_TABLES = 27,\n\tDEVLINK_ATTR_DPIPE_TABLE = 28,\n\tDEVLINK_ATTR_DPIPE_TABLE_NAME = 29,\n\tDEVLINK_ATTR_DPIPE_TABLE_SIZE = 30,\n\tDEVLINK_ATTR_DPIPE_TABLE_MATCHES = 31,\n\tDEVLINK_ATTR_DPIPE_TABLE_ACTIONS = 32,\n\tDEVLINK_ATTR_DPIPE_TABLE_COUNTERS_ENABLED = 33,\n\tDEVLINK_ATTR_DPIPE_ENTRIES = 34,\n\tDEVLINK_ATTR_DPIPE_ENTRY = 35,\n\tDEVLINK_ATTR_DPIPE_ENTRY_INDEX = 36,\n\tDEVLINK_ATTR_DPIPE_ENTRY_MATCH_VALUES = 37,\n\tDEVLINK_ATTR_DPIPE_ENTRY_ACTION_VALUES = 38,\n\tDEVLINK_ATTR_DPIPE_ENTRY_COUNTER = 39,\n\tDEVLINK_ATTR_DPIPE_MATCH = 40,\n\tDEVLINK_ATTR_DPIPE_MATCH_VALUE = 41,\n\tDEVLINK_ATTR_DPIPE_MATCH_TYPE = 42,\n\tDEVLINK_ATTR_DPIPE_ACTION = 43,\n\tDEVLINK_ATTR_DPIPE_ACTION_VALUE = 44,\n\tDEVLINK_ATTR_DPIPE_ACTION_TYPE = 45,\n\tDEVLINK_ATTR_DPIPE_VALUE = 46,\n\tDEVLINK_ATTR_DPIPE_VALUE_MASK = 47,\n\tDEVLINK_ATTR_DPIPE_VALUE_MAPPING = 48,\n\tDEVLINK_ATTR_DPIPE_HEADERS = 49,\n\tDEVLINK_ATTR_DPIPE_HEADER = 50,\n\tDEVLINK_ATTR_DPIPE_HEADER_NAME = 51,\n\tDEVLINK_ATTR_DPIPE_HEADER_ID = 52,\n\tDEVLINK_ATTR_DPIPE_HEADER_FIELDS = 53,\n\tDEVLINK_ATTR_DPIPE_HEADER_GLOBAL = 54,\n\tDEVLINK_ATTR_DPIPE_HEADER_INDEX = 55,\n\tDEVLINK_ATTR_DPIPE_FIELD = 56,\n\tDEVLINK_ATTR_DPIPE_FIELD_NAME = 57,\n\tDEVLINK_ATTR_DPIPE_FIELD_ID = 58,\n\tDEVLINK_ATTR_DPIPE_FIELD_BITWIDTH = 59,\n\tDEVLINK_ATTR_DPIPE_FIELD_MAPPING_TYPE = 60,\n\tDEVLINK_ATTR_PAD = 61,\n\tDEVLINK_ATTR_ESWITCH_ENCAP_MODE = 62,\n\tDEVLINK_ATTR_RESOURCE_LIST = 63,\n\tDEVLINK_ATTR_RESOURCE = 64,\n\tDEVLINK_ATTR_RESOURCE_NAME = 65,\n\tDEVLINK_ATTR_RESOURCE_ID = 66,\n\tDEVLINK_ATTR_RESOURCE_SIZE = 67,\n\tDEVLINK_ATTR_RESOURCE_SIZE_NEW = 68,\n\tDEVLINK_ATTR_RESOURCE_SIZE_VALID = 69,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MIN = 70,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MAX = 71,\n\tDEVLINK_ATTR_RESOURCE_SIZE_GRAN = 72,\n\tDEVLINK_ATTR_RESOURCE_UNIT = 73,\n\tDEVLINK_ATTR_RESOURCE_OCC = 74,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID = 75,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS = 76,\n\tDEVLINK_ATTR_PORT_FLAVOUR = 77,\n\tDEVLINK_ATTR_PORT_NUMBER = 78,\n\tDEVLINK_ATTR_PORT_SPLIT_SUBPORT_NUMBER = 79,\n\tDEVLINK_ATTR_PARAM = 80,\n\tDEVLINK_ATTR_PARAM_NAME = 81,\n\tDEVLINK_ATTR_PARAM_GENERIC = 82,\n\tDEVLINK_ATTR_PARAM_TYPE = 83,\n\tDEVLINK_ATTR_PARAM_VALUES_LIST = 84,\n\tDEVLINK_ATTR_PARAM_VALUE = 85,\n\tDEVLINK_ATTR_PARAM_VALUE_DATA = 86,\n\tDEVLINK_ATTR_PARAM_VALUE_CMODE = 87,\n\tDEVLINK_ATTR_REGION_NAME = 88,\n\tDEVLINK_ATTR_REGION_SIZE = 89,\n\tDEVLINK_ATTR_REGION_SNAPSHOTS = 90,\n\tDEVLINK_ATTR_REGION_SNAPSHOT = 91,\n\tDEVLINK_ATTR_REGION_SNAPSHOT_ID = 92,\n\tDEVLINK_ATTR_REGION_CHUNKS = 93,\n\tDEVLINK_ATTR_REGION_CHUNK = 94,\n\tDEVLINK_ATTR_REGION_CHUNK_DATA = 95,\n\tDEVLINK_ATTR_REGION_CHUNK_ADDR = 96,\n\tDEVLINK_ATTR_REGION_CHUNK_LEN = 97,\n\tDEVLINK_ATTR_INFO_DRIVER_NAME = 98,\n\tDEVLINK_ATTR_INFO_SERIAL_NUMBER = 99,\n\tDEVLINK_ATTR_INFO_VERSION_FIXED = 100,\n\tDEVLINK_ATTR_INFO_VERSION_RUNNING = 101,\n\tDEVLINK_ATTR_INFO_VERSION_STORED = 102,\n\tDEVLINK_ATTR_INFO_VERSION_NAME = 103,\n\tDEVLINK_ATTR_INFO_VERSION_VALUE = 104,\n\tDEVLINK_ATTR_SB_POOL_CELL_SIZE = 105,\n\tDEVLINK_ATTR_FMSG = 106,\n\tDEVLINK_ATTR_FMSG_OBJ_NEST_START = 107,\n\tDEVLINK_ATTR_FMSG_PAIR_NEST_START = 108,\n\tDEVLINK_ATTR_FMSG_ARR_NEST_START = 109,\n\tDEVLINK_ATTR_FMSG_NEST_END = 110,\n\tDEVLINK_ATTR_FMSG_OBJ_NAME = 111,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_TYPE = 112,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_DATA = 113,\n\tDEVLINK_ATTR_HEALTH_REPORTER = 114,\n\tDEVLINK_ATTR_HEALTH_REPORTER_NAME = 115,\n\tDEVLINK_ATTR_HEALTH_REPORTER_STATE = 116,\n\tDEVLINK_ATTR_HEALTH_REPORTER_ERR_COUNT = 117,\n\tDEVLINK_ATTR_HEALTH_REPORTER_RECOVER_COUNT = 118,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS = 119,\n\tDEVLINK_ATTR_HEALTH_REPORTER_GRACEFUL_PERIOD = 120,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_RECOVER = 121,\n\tDEVLINK_ATTR_FLASH_UPDATE_FILE_NAME = 122,\n\tDEVLINK_ATTR_FLASH_UPDATE_COMPONENT = 123,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_MSG = 124,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_DONE = 125,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TOTAL = 126,\n\tDEVLINK_ATTR_PORT_PCI_PF_NUMBER = 127,\n\tDEVLINK_ATTR_PORT_PCI_VF_NUMBER = 128,\n\tDEVLINK_ATTR_STATS = 129,\n\tDEVLINK_ATTR_TRAP_NAME = 130,\n\tDEVLINK_ATTR_TRAP_ACTION = 131,\n\tDEVLINK_ATTR_TRAP_TYPE = 132,\n\tDEVLINK_ATTR_TRAP_GENERIC = 133,\n\tDEVLINK_ATTR_TRAP_METADATA = 134,\n\tDEVLINK_ATTR_TRAP_GROUP_NAME = 135,\n\tDEVLINK_ATTR_RELOAD_FAILED = 136,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS_NS = 137,\n\tDEVLINK_ATTR_NETNS_FD = 138,\n\tDEVLINK_ATTR_NETNS_PID = 139,\n\tDEVLINK_ATTR_NETNS_ID = 140,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_DUMP = 141,\n\tDEVLINK_ATTR_TRAP_POLICER_ID = 142,\n\tDEVLINK_ATTR_TRAP_POLICER_RATE = 143,\n\tDEVLINK_ATTR_TRAP_POLICER_BURST = 144,\n\tDEVLINK_ATTR_PORT_FUNCTION = 145,\n\tDEVLINK_ATTR_INFO_BOARD_SERIAL_NUMBER = 146,\n\tDEVLINK_ATTR_PORT_LANES = 147,\n\tDEVLINK_ATTR_PORT_SPLITTABLE = 148,\n\tDEVLINK_ATTR_PORT_EXTERNAL = 149,\n\tDEVLINK_ATTR_PORT_CONTROLLER_NUMBER = 150,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TIMEOUT = 151,\n\tDEVLINK_ATTR_FLASH_UPDATE_OVERWRITE_MASK = 152,\n\tDEVLINK_ATTR_RELOAD_ACTION = 153,\n\tDEVLINK_ATTR_RELOAD_ACTIONS_PERFORMED = 154,\n\tDEVLINK_ATTR_RELOAD_LIMITS = 155,\n\tDEVLINK_ATTR_DEV_STATS = 156,\n\tDEVLINK_ATTR_RELOAD_STATS = 157,\n\tDEVLINK_ATTR_RELOAD_STATS_ENTRY = 158,\n\tDEVLINK_ATTR_RELOAD_STATS_LIMIT = 159,\n\tDEVLINK_ATTR_RELOAD_STATS_VALUE = 160,\n\tDEVLINK_ATTR_REMOTE_RELOAD_STATS = 161,\n\tDEVLINK_ATTR_RELOAD_ACTION_INFO = 162,\n\tDEVLINK_ATTR_RELOAD_ACTION_STATS = 163,\n\tDEVLINK_ATTR_PORT_PCI_SF_NUMBER = 164,\n\tDEVLINK_ATTR_RATE_TYPE = 165,\n\tDEVLINK_ATTR_RATE_TX_SHARE = 166,\n\tDEVLINK_ATTR_RATE_TX_MAX = 167,\n\tDEVLINK_ATTR_RATE_NODE_NAME = 168,\n\tDEVLINK_ATTR_RATE_PARENT_NODE_NAME = 169,\n\tDEVLINK_ATTR_REGION_MAX_SNAPSHOTS = 170,\n\tDEVLINK_ATTR_LINECARD_INDEX = 171,\n\tDEVLINK_ATTR_LINECARD_STATE = 172,\n\tDEVLINK_ATTR_LINECARD_TYPE = 173,\n\tDEVLINK_ATTR_LINECARD_SUPPORTED_TYPES = 174,\n\tDEVLINK_ATTR_NESTED_DEVLINK = 175,\n\tDEVLINK_ATTR_SELFTESTS = 176,\n\tDEVLINK_ATTR_RATE_TX_PRIORITY = 177,\n\tDEVLINK_ATTR_RATE_TX_WEIGHT = 178,\n\tDEVLINK_ATTR_REGION_DIRECT = 179,\n\tDEVLINK_ATTR_RATE_TC_BWS = 180,\n\tDEVLINK_ATTR_HEALTH_REPORTER_BURST_PERIOD = 181,\n\tDEVLINK_ATTR_PARAM_VALUE_DEFAULT = 182,\n\tDEVLINK_ATTR_PARAM_RESET_DEFAULT = 183,\n\t__DEVLINK_ATTR_MAX = 184,\n\tDEVLINK_ATTR_MAX = 183,\n};\n\nenum devlink_attr_selftest_id {\n\tDEVLINK_ATTR_SELFTEST_ID_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_ID_FLASH = 1,\n\t__DEVLINK_ATTR_SELFTEST_ID_MAX = 2,\n\tDEVLINK_ATTR_SELFTEST_ID_MAX = 1,\n};\n\nenum devlink_attr_selftest_result {\n\tDEVLINK_ATTR_SELFTEST_RESULT_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_RESULT = 1,\n\tDEVLINK_ATTR_SELFTEST_RESULT_ID = 2,\n\tDEVLINK_ATTR_SELFTEST_RESULT_STATUS = 3,\n\t__DEVLINK_ATTR_SELFTEST_RESULT_MAX = 4,\n\tDEVLINK_ATTR_SELFTEST_RESULT_MAX = 3,\n};\n\nenum devlink_command {\n\tDEVLINK_CMD_UNSPEC = 0,\n\tDEVLINK_CMD_GET = 1,\n\tDEVLINK_CMD_SET = 2,\n\tDEVLINK_CMD_NEW = 3,\n\tDEVLINK_CMD_DEL = 4,\n\tDEVLINK_CMD_PORT_GET = 5,\n\tDEVLINK_CMD_PORT_SET = 6,\n\tDEVLINK_CMD_PORT_NEW = 7,\n\tDEVLINK_CMD_PORT_DEL = 8,\n\tDEVLINK_CMD_PORT_SPLIT = 9,\n\tDEVLINK_CMD_PORT_UNSPLIT = 10,\n\tDEVLINK_CMD_SB_GET = 11,\n\tDEVLINK_CMD_SB_SET = 12,\n\tDEVLINK_CMD_SB_NEW = 13,\n\tDEVLINK_CMD_SB_DEL = 14,\n\tDEVLINK_CMD_SB_POOL_GET = 15,\n\tDEVLINK_CMD_SB_POOL_SET = 16,\n\tDEVLINK_CMD_SB_POOL_NEW = 17,\n\tDEVLINK_CMD_SB_POOL_DEL = 18,\n\tDEVLINK_CMD_SB_PORT_POOL_GET = 19,\n\tDEVLINK_CMD_SB_PORT_POOL_SET = 20,\n\tDEVLINK_CMD_SB_PORT_POOL_NEW = 21,\n\tDEVLINK_CMD_SB_PORT_POOL_DEL = 22,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_GET = 23,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_SET = 24,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_NEW = 25,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_DEL = 26,\n\tDEVLINK_CMD_SB_OCC_SNAPSHOT = 27,\n\tDEVLINK_CMD_SB_OCC_MAX_CLEAR = 28,\n\tDEVLINK_CMD_ESWITCH_GET = 29,\n\tDEVLINK_CMD_ESWITCH_SET = 30,\n\tDEVLINK_CMD_DPIPE_TABLE_GET = 31,\n\tDEVLINK_CMD_DPIPE_ENTRIES_GET = 32,\n\tDEVLINK_CMD_DPIPE_HEADERS_GET = 33,\n\tDEVLINK_CMD_DPIPE_TABLE_COUNTERS_SET = 34,\n\tDEVLINK_CMD_RESOURCE_SET = 35,\n\tDEVLINK_CMD_RESOURCE_DUMP = 36,\n\tDEVLINK_CMD_RELOAD = 37,\n\tDEVLINK_CMD_PARAM_GET = 38,\n\tDEVLINK_CMD_PARAM_SET = 39,\n\tDEVLINK_CMD_PARAM_NEW = 40,\n\tDEVLINK_CMD_PARAM_DEL = 41,\n\tDEVLINK_CMD_REGION_GET = 42,\n\tDEVLINK_CMD_REGION_SET = 43,\n\tDEVLINK_CMD_REGION_NEW = 44,\n\tDEVLINK_CMD_REGION_DEL = 45,\n\tDEVLINK_CMD_REGION_READ = 46,\n\tDEVLINK_CMD_PORT_PARAM_GET = 47,\n\tDEVLINK_CMD_PORT_PARAM_SET = 48,\n\tDEVLINK_CMD_PORT_PARAM_NEW = 49,\n\tDEVLINK_CMD_PORT_PARAM_DEL = 50,\n\tDEVLINK_CMD_INFO_GET = 51,\n\tDEVLINK_CMD_HEALTH_REPORTER_GET = 52,\n\tDEVLINK_CMD_HEALTH_REPORTER_SET = 53,\n\tDEVLINK_CMD_HEALTH_REPORTER_RECOVER = 54,\n\tDEVLINK_CMD_HEALTH_REPORTER_DIAGNOSE = 55,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_GET = 56,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_CLEAR = 57,\n\tDEVLINK_CMD_FLASH_UPDATE = 58,\n\tDEVLINK_CMD_FLASH_UPDATE_END = 59,\n\tDEVLINK_CMD_FLASH_UPDATE_STATUS = 60,\n\tDEVLINK_CMD_TRAP_GET = 61,\n\tDEVLINK_CMD_TRAP_SET = 62,\n\tDEVLINK_CMD_TRAP_NEW = 63,\n\tDEVLINK_CMD_TRAP_DEL = 64,\n\tDEVLINK_CMD_TRAP_GROUP_GET = 65,\n\tDEVLINK_CMD_TRAP_GROUP_SET = 66,\n\tDEVLINK_CMD_TRAP_GROUP_NEW = 67,\n\tDEVLINK_CMD_TRAP_GROUP_DEL = 68,\n\tDEVLINK_CMD_TRAP_POLICER_GET = 69,\n\tDEVLINK_CMD_TRAP_POLICER_SET = 70,\n\tDEVLINK_CMD_TRAP_POLICER_NEW = 71,\n\tDEVLINK_CMD_TRAP_POLICER_DEL = 72,\n\tDEVLINK_CMD_HEALTH_REPORTER_TEST = 73,\n\tDEVLINK_CMD_RATE_GET = 74,\n\tDEVLINK_CMD_RATE_SET = 75,\n\tDEVLINK_CMD_RATE_NEW = 76,\n\tDEVLINK_CMD_RATE_DEL = 77,\n\tDEVLINK_CMD_LINECARD_GET = 78,\n\tDEVLINK_CMD_LINECARD_SET = 79,\n\tDEVLINK_CMD_LINECARD_NEW = 80,\n\tDEVLINK_CMD_LINECARD_DEL = 81,\n\tDEVLINK_CMD_SELFTESTS_GET = 82,\n\tDEVLINK_CMD_SELFTESTS_RUN = 83,\n\tDEVLINK_CMD_NOTIFY_FILTER_SET = 84,\n\t__DEVLINK_CMD_MAX = 85,\n\tDEVLINK_CMD_MAX = 84,\n};\n\nenum devlink_dpipe_action_type {\n\tDEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY = 0,\n};\n\nenum devlink_dpipe_field_ethernet_id {\n\tDEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC = 0,\n};\n\nenum devlink_dpipe_field_ipv4_id {\n\tDEVLINK_DPIPE_FIELD_IPV4_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_ipv6_id {\n\tDEVLINK_DPIPE_FIELD_IPV6_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_mapping_type {\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0,\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1,\n};\n\nenum devlink_dpipe_header_id {\n\tDEVLINK_DPIPE_HEADER_ETHERNET = 0,\n\tDEVLINK_DPIPE_HEADER_IPV4 = 1,\n\tDEVLINK_DPIPE_HEADER_IPV6 = 2,\n};\n\nenum devlink_dpipe_match_type {\n\tDEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT = 0,\n};\n\nenum devlink_eswitch_encap_mode {\n\tDEVLINK_ESWITCH_ENCAP_MODE_NONE = 0,\n\tDEVLINK_ESWITCH_ENCAP_MODE_BASIC = 1,\n};\n\nenum devlink_health_reporter_state {\n\tDEVLINK_HEALTH_REPORTER_STATE_HEALTHY = 0,\n\tDEVLINK_HEALTH_REPORTER_STATE_ERROR = 1,\n};\n\nenum devlink_info_version_type {\n\tDEVLINK_INFO_VERSION_TYPE_NONE = 0,\n\tDEVLINK_INFO_VERSION_TYPE_COMPONENT = 1,\n};\n\nenum devlink_linecard_state {\n\tDEVLINK_LINECARD_STATE_UNSPEC = 0,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONED = 1,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONING = 2,\n\tDEVLINK_LINECARD_STATE_PROVISIONING = 3,\n\tDEVLINK_LINECARD_STATE_PROVISIONING_FAILED = 4,\n\tDEVLINK_LINECARD_STATE_PROVISIONED = 5,\n\tDEVLINK_LINECARD_STATE_ACTIVE = 6,\n\t__DEVLINK_LINECARD_STATE_MAX = 7,\n\tDEVLINK_LINECARD_STATE_MAX = 6,\n};\n\nenum devlink_multicast_groups {\n\tDEVLINK_MCGRP_CONFIG = 0,\n};\n\nenum devlink_param_cmode {\n\tDEVLINK_PARAM_CMODE_RUNTIME = 0,\n\tDEVLINK_PARAM_CMODE_DRIVERINIT = 1,\n\tDEVLINK_PARAM_CMODE_PERMANENT = 2,\n\t__DEVLINK_PARAM_CMODE_MAX = 3,\n\tDEVLINK_PARAM_CMODE_MAX = 2,\n};\n\nenum devlink_param_generic_id {\n\tDEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET = 0,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MACS = 1,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_SRIOV = 2,\n\tDEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT = 3,\n\tDEVLINK_PARAM_GENERIC_ID_IGNORE_ARI = 4,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX = 5,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN = 6,\n\tDEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY = 7,\n\tDEVLINK_PARAM_GENERIC_ID_RESET_DEV_ON_DRV_PROBE = 8,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE = 9,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_REMOTE_DEV_RESET = 10,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ETH = 11,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA = 12,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_VNET = 13,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_IWARP = 14,\n\tDEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE = 15,\n\tDEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE = 16,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_PHC = 17,\n\tDEVLINK_PARAM_GENERIC_ID_CLOCK_ID = 18,\n\tDEVLINK_PARAM_GENERIC_ID_TOTAL_VFS = 19,\n\tDEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS = 20,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF = 21,\n\t__DEVLINK_PARAM_GENERIC_ID_MAX = 22,\n\tDEVLINK_PARAM_GENERIC_ID_MAX = 21,\n};\n\nenum devlink_param_type {\n\tDEVLINK_PARAM_TYPE_U8 = 1,\n\tDEVLINK_PARAM_TYPE_U16 = 2,\n\tDEVLINK_PARAM_TYPE_U32 = 3,\n\tDEVLINK_PARAM_TYPE_U64 = 4,\n\tDEVLINK_PARAM_TYPE_STRING = 5,\n\tDEVLINK_PARAM_TYPE_BOOL = 6,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_attr_cap {\n\tDEVLINK_PORT_FN_ATTR_CAP_ROCE_BIT = 0,\n\tDEVLINK_PORT_FN_ATTR_CAP_MIGRATABLE_BIT = 1,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_CRYPTO_BIT = 2,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_PACKET_BIT = 3,\n\t__DEVLINK_PORT_FN_ATTR_CAPS_MAX = 4,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_function_attr {\n\tDEVLINK_PORT_FUNCTION_ATTR_UNSPEC = 0,\n\tDEVLINK_PORT_FUNCTION_ATTR_HW_ADDR = 1,\n\tDEVLINK_PORT_FN_ATTR_STATE = 2,\n\tDEVLINK_PORT_FN_ATTR_OPSTATE = 3,\n\tDEVLINK_PORT_FN_ATTR_CAPS = 4,\n\tDEVLINK_PORT_FN_ATTR_DEVLINK = 5,\n\tDEVLINK_PORT_FN_ATTR_MAX_IO_EQS = 6,\n\t__DEVLINK_PORT_FUNCTION_ATTR_MAX = 7,\n\tDEVLINK_PORT_FUNCTION_ATTR_MAX = 6,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_tc_attr {\n\tDEVLINK_RATE_TC_ATTR_UNSPEC = 0,\n\tDEVLINK_RATE_TC_ATTR_INDEX = 1,\n\tDEVLINK_RATE_TC_ATTR_BW = 2,\n\t__DEVLINK_RATE_TC_ATTR_MAX = 3,\n\tDEVLINK_RATE_TC_ATTR_MAX = 2,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devlink_reload_action {\n\tDEVLINK_RELOAD_ACTION_UNSPEC = 0,\n\tDEVLINK_RELOAD_ACTION_DRIVER_REINIT = 1,\n\tDEVLINK_RELOAD_ACTION_FW_ACTIVATE = 2,\n\t__DEVLINK_RELOAD_ACTION_MAX = 3,\n\tDEVLINK_RELOAD_ACTION_MAX = 2,\n};\n\nenum devlink_reload_limit {\n\tDEVLINK_RELOAD_LIMIT_UNSPEC = 0,\n\tDEVLINK_RELOAD_LIMIT_NO_RESET = 1,\n\t__DEVLINK_RELOAD_LIMIT_MAX = 2,\n\tDEVLINK_RELOAD_LIMIT_MAX = 1,\n};\n\nenum devlink_resource_unit {\n\tDEVLINK_RESOURCE_UNIT_ENTRY = 0,\n};\n\nenum devlink_sb_pool_type {\n\tDEVLINK_SB_POOL_TYPE_INGRESS = 0,\n\tDEVLINK_SB_POOL_TYPE_EGRESS = 1,\n};\n\nenum devlink_sb_threshold_type {\n\tDEVLINK_SB_THRESHOLD_TYPE_STATIC = 0,\n\tDEVLINK_SB_THRESHOLD_TYPE_DYNAMIC = 1,\n};\n\nenum devlink_selftest_status {\n\tDEVLINK_SELFTEST_STATUS_SKIP = 0,\n\tDEVLINK_SELFTEST_STATUS_PASS = 1,\n\tDEVLINK_SELFTEST_STATUS_FAIL = 2,\n};\n\nenum devlink_trap_action {\n\tDEVLINK_TRAP_ACTION_DROP = 0,\n\tDEVLINK_TRAP_ACTION_TRAP = 1,\n\tDEVLINK_TRAP_ACTION_MIRROR = 2,\n};\n\nenum devlink_trap_generic_id {\n\tDEVLINK_TRAP_GENERIC_ID_SMAC_MC = 0,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_TAG_MISMATCH = 1,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_VLAN_FILTER = 2,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_STP_FILTER = 3,\n\tDEVLINK_TRAP_GENERIC_ID_EMPTY_TX_LIST = 4,\n\tDEVLINK_TRAP_GENERIC_ID_PORT_LOOPBACK_FILTER = 5,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_ROUTE = 6,\n\tDEVLINK_TRAP_GENERIC_ID_TTL_ERROR = 7,\n\tDEVLINK_TRAP_GENERIC_ID_TAIL_DROP = 8,\n\tDEVLINK_TRAP_GENERIC_ID_NON_IP_PACKET = 9,\n\tDEVLINK_TRAP_GENERIC_ID_UC_DIP_MC_DMAC = 10,\n\tDEVLINK_TRAP_GENERIC_ID_DIP_LB = 11,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_MC = 12,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_LB = 13,\n\tDEVLINK_TRAP_GENERIC_ID_CORRUPTED_IP_HDR = 14,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_SIP_BC = 15,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_RESERVED_SCOPE = 16,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_INTERFACE_LOCAL_SCOPE = 17,\n\tDEVLINK_TRAP_GENERIC_ID_MTU_ERROR = 18,\n\tDEVLINK_TRAP_GENERIC_ID_UNRESOLVED_NEIGH = 19,\n\tDEVLINK_TRAP_GENERIC_ID_RPF = 20,\n\tDEVLINK_TRAP_GENERIC_ID_REJECT_ROUTE = 21,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_LPM_UNICAST_MISS = 22,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_LPM_UNICAST_MISS = 23,\n\tDEVLINK_TRAP_GENERIC_ID_NON_ROUTABLE = 24,\n\tDEVLINK_TRAP_GENERIC_ID_DECAP_ERROR = 25,\n\tDEVLINK_TRAP_GENERIC_ID_OVERLAY_SMAC_MC = 26,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_FLOW_ACTION_DROP = 27,\n\tDEVLINK_TRAP_GENERIC_ID_EGRESS_FLOW_ACTION_DROP = 28,\n\tDEVLINK_TRAP_GENERIC_ID_STP = 29,\n\tDEVLINK_TRAP_GENERIC_ID_LACP = 30,\n\tDEVLINK_TRAP_GENERIC_ID_LLDP = 31,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_QUERY = 32,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V1_REPORT = 33,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_REPORT = 34,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V3_REPORT = 35,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_LEAVE = 36,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_QUERY = 37,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_REPORT = 38,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V2_REPORT = 39,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_DONE = 40,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_DHCP = 41,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DHCP = 42,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_REQUEST = 43,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_RESPONSE = 44,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_OVERLAY = 45,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_SOLICIT = 46,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_ADVERT = 47,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BFD = 48,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BFD = 49,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_OSPF = 50,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_OSPF = 51,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BGP = 52,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BGP = 53,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_VRRP = 54,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_VRRP = 55,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_PIM = 56,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_PIM = 57,\n\tDEVLINK_TRAP_GENERIC_ID_UC_LB = 58,\n\tDEVLINK_TRAP_GENERIC_ID_LOCAL_ROUTE = 59,\n\tDEVLINK_TRAP_GENERIC_ID_EXTERNAL_ROUTE = 60,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_UC_DIP_LINK_LOCAL_SCOPE = 61,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_NODES = 62,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_ROUTERS = 63,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_SOLICIT = 64,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ADVERT = 65,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_REDIRECT = 66,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_ROUTER_ALERT = 67,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ALERT = 68,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_EVENT = 69,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_GENERAL = 70,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_SAMPLE = 71,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_TRAP = 72,\n\tDEVLINK_TRAP_GENERIC_ID_EARLY_DROP = 73,\n\tDEVLINK_TRAP_GENERIC_ID_VXLAN_PARSING = 74,\n\tDEVLINK_TRAP_GENERIC_ID_LLC_SNAP_PARSING = 75,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_PARSING = 76,\n\tDEVLINK_TRAP_GENERIC_ID_PPPOE_PPP_PARSING = 77,\n\tDEVLINK_TRAP_GENERIC_ID_MPLS_PARSING = 78,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_PARSING = 79,\n\tDEVLINK_TRAP_GENERIC_ID_IP_1_PARSING = 80,\n\tDEVLINK_TRAP_GENERIC_ID_IP_N_PARSING = 81,\n\tDEVLINK_TRAP_GENERIC_ID_GRE_PARSING = 82,\n\tDEVLINK_TRAP_GENERIC_ID_UDP_PARSING = 83,\n\tDEVLINK_TRAP_GENERIC_ID_TCP_PARSING = 84,\n\tDEVLINK_TRAP_GENERIC_ID_IPSEC_PARSING = 85,\n\tDEVLINK_TRAP_GENERIC_ID_SCTP_PARSING = 86,\n\tDEVLINK_TRAP_GENERIC_ID_DCCP_PARSING = 87,\n\tDEVLINK_TRAP_GENERIC_ID_GTP_PARSING = 88,\n\tDEVLINK_TRAP_GENERIC_ID_ESP_PARSING = 89,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_NEXTHOP = 90,\n\tDEVLINK_TRAP_GENERIC_ID_DMAC_FILTER = 91,\n\tDEVLINK_TRAP_GENERIC_ID_EAPOL = 92,\n\tDEVLINK_TRAP_GENERIC_ID_LOCKED_PORT = 93,\n\t__DEVLINK_TRAP_GENERIC_ID_MAX = 94,\n\tDEVLINK_TRAP_GENERIC_ID_MAX = 93,\n};\n\nenum devlink_trap_group_generic_id {\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L2_DROPS = 0,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_DROPS = 1,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_EXCEPTIONS = 2,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BUFFER_DROPS = 3,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_TUNNEL_DROPS = 4,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_DROPS = 5,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_STP = 6,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LACP = 7,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LLDP = 8,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MC_SNOOPING = 9,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_DHCP = 10,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_NEIGH_DISCOVERY = 11,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BFD = 12,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_OSPF = 13,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BGP = 14,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_VRRP = 15,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PIM = 16,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_UC_LB = 17,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LOCAL_DELIVERY = 18,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EXTERNAL_DELIVERY = 19,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_IPV6 = 20,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_EVENT = 21,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_GENERAL = 22,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_SAMPLE = 23,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_TRAP = 24,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PARSER_ERROR_DROPS = 25,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EAPOL = 26,\n\t__DEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 27,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 26,\n};\n\nenum devlink_trap_type {\n\tDEVLINK_TRAP_TYPE_DROP = 0,\n\tDEVLINK_TRAP_TYPE_EXCEPTION = 1,\n\tDEVLINK_TRAP_TYPE_CONTROL = 2,\n};\n\nenum devlink_var_attr_type {\n\tDEVLINK_VAR_ATTR_TYPE_U8 = 1,\n\tDEVLINK_VAR_ATTR_TYPE_U16 = 2,\n\tDEVLINK_VAR_ATTR_TYPE_U32 = 3,\n\tDEVLINK_VAR_ATTR_TYPE_U64 = 4,\n\tDEVLINK_VAR_ATTR_TYPE_STRING = 5,\n\tDEVLINK_VAR_ATTR_TYPE_FLAG = 6,\n\tDEVLINK_VAR_ATTR_TYPE_NUL_STRING = 10,\n\tDEVLINK_VAR_ATTR_TYPE_BINARY = 11,\n\t__DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE = 128,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum diag204_cpu_flags {\n\tDIAG204_CPU_ONLINE = 32,\n\tDIAG204_CPU_CAPPED = 64,\n};\n\nenum diag204_format {\n\tDIAG204_INFO_SIMPLE = 0,\n\tDIAG204_INFO_EXT = 65536,\n};\n\nenum diag204_sc {\n\tDIAG204_SUBC_STIB4 = 4,\n\tDIAG204_SUBC_RSI = 5,\n\tDIAG204_SUBC_STIB6 = 6,\n\tDIAG204_SUBC_STIB7 = 7,\n};\n\nenum diag26c_sc {\n\tDIAG26C_PORT_VNIC = 36,\n\tDIAG26C_MAC_SERVICES = 48,\n};\n\nenum diag26c_version {\n\tDIAG26C_VERSION2 = 2,\n\tDIAG26C_VERSION6_VM65918 = 131078,\n};\n\nenum diag308_subcode {\n\tDIAG308_CLEAR_RESET = 0,\n\tDIAG308_LOAD_NORMAL_RESET = 1,\n\tDIAG308_REL_HSA = 2,\n\tDIAG308_LOAD_CLEAR = 3,\n\tDIAG308_LOAD_NORMAL_DUMP = 4,\n\tDIAG308_SET = 5,\n\tDIAG308_STORE = 6,\n\tDIAG308_LOAD_NORMAL = 7,\n};\n\nenum diag308_subcode_flags {\n\tDIAG308_FLAG_EI = 65536,\n};\n\nenum diag310_retcode {\n\tDIAG310_RET_SUCCESS = 1,\n\tDIAG310_RET_BUSY = 257,\n\tDIAG310_RET_OPNOTSUPP = 258,\n\tDIAG310_RET_SC4_INVAL = 1025,\n\tDIAG310_RET_SC4_NODATA = 1026,\n\tDIAG310_RET_SC5_INVAL = 1281,\n\tDIAG310_RET_SC5_NODATA = 1282,\n\tDIAG310_RET_SC5_ESIZE = 1283,\n};\n\nenum diag310_sc {\n\tDIAG310_SUBC_0 = 0,\n\tDIAG310_SUBC_1 = 1,\n\tDIAG310_SUBC_4 = 4,\n\tDIAG310_SUBC_5 = 5,\n};\n\nenum diag320_rc {\n\tDIAG320_RC_OK = 1,\n\tDIAG320_RC_CS_NOMATCH = 774,\n};\n\nenum diag320_subcode {\n\tDIAG320_SUBCODES = 0,\n\tDIAG320_STORAGE = 1,\n\tDIAG320_CERT_BLOCK = 2,\n};\n\nenum diag49c_sc {\n\tDIAG49C_SUBC_ACK = 0,\n\tDIAG49C_SUBC_REG = 1,\n};\n\nenum diag_stat_enum {\n\tDIAG_STAT_X008 = 0,\n\tDIAG_STAT_X00C = 1,\n\tDIAG_STAT_X010 = 2,\n\tDIAG_STAT_X014 = 3,\n\tDIAG_STAT_X044 = 4,\n\tDIAG_STAT_X064 = 5,\n\tDIAG_STAT_X08C = 6,\n\tDIAG_STAT_X09C = 7,\n\tDIAG_STAT_X0DC = 8,\n\tDIAG_STAT_X204 = 9,\n\tDIAG_STAT_X210 = 10,\n\tDIAG_STAT_X224 = 11,\n\tDIAG_STAT_X250 = 12,\n\tDIAG_STAT_X258 = 13,\n\tDIAG_STAT_X26C = 14,\n\tDIAG_STAT_X288 = 15,\n\tDIAG_STAT_X2C4 = 16,\n\tDIAG_STAT_X2FC = 17,\n\tDIAG_STAT_X304 = 18,\n\tDIAG_STAT_X308 = 19,\n\tDIAG_STAT_X310 = 20,\n\tDIAG_STAT_X318 = 21,\n\tDIAG_STAT_X320 = 22,\n\tDIAG_STAT_X324 = 23,\n\tDIAG_STAT_X49C = 24,\n\tDIAG_STAT_X500 = 25,\n\tNR_DIAG_STAT = 26,\n};\n\nenum die_val {\n\tDIE_OOPS = 1,\n\tDIE_BPT = 2,\n\tDIE_SSTEP = 3,\n\tDIE_PANIC = 4,\n\tDIE_NMI = 5,\n\tDIE_DIE = 6,\n\tDIE_NMIWATCHDOG = 7,\n\tDIE_KERNELDEBUG = 8,\n\tDIE_TRAP = 9,\n\tDIE_GPF = 10,\n\tDIE_CALL = 11,\n\tDIE_NMI_IPI = 12,\n};\n\nenum digest_type {\n\tDIGEST_TYPE_IMA = 0,\n\tDIGEST_TYPE_VERITY = 1,\n\tDIGEST_TYPE__LAST = 2,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dm_io_mem_type {\n\tDM_IO_PAGE_LIST = 0,\n\tDM_IO_BIO = 1,\n\tDM_IO_VMA = 2,\n\tDM_IO_KMEM = 3,\n};\n\nenum dm_queue_mode {\n\tDM_TYPE_NONE = 0,\n\tDM_TYPE_BIO_BASED = 1,\n\tDM_TYPE_REQUEST_BASED = 2,\n\tDM_TYPE_DAX_BIO_BASED = 3,\n};\n\nenum dm_uevent_type {\n\tDM_UEVENT_PATH_FAILED = 0,\n\tDM_UEVENT_PATH_REINSTATED = 1,\n};\n\nenum dm_wrappedkey_op {\n\tDERIVE_SW_SECRET = 0,\n\tIMPORT_KEY = 1,\n\tGENERATE_KEY = 2,\n\tPREPARE_KEY = 3,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SEQNO64_BIT = 0,\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 1,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 2,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 3,\n\tDMA_FENCE_FLAG_USER_BITS = 4,\n};\n\nenum dma_resv_usage {\n\tDMA_RESV_USAGE_KERNEL = 0,\n\tDMA_RESV_USAGE_WRITE = 1,\n\tDMA_RESV_USAGE_READ = 2,\n\tDMA_RESV_USAGE_BOOKKEEP = 3,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum drbg_prefixes {\n\tDRBG_PREFIX0 = 0,\n\tDRBG_PREFIX1 = 1,\n\tDRBG_PREFIX2 = 2,\n\tDRBG_PREFIX3 = 3,\n};\n\nenum drbg_seed_state {\n\tDRBG_SEED_STATE_UNSEEDED = 0,\n\tDRBG_SEED_STATE_PARTIAL = 1,\n\tDRBG_SEED_STATE_FULL = 2,\n};\n\nenum dump_type {\n\tDUMP_TYPE_NONE = 1,\n\tDUMP_TYPE_CCW = 2,\n\tDUMP_TYPE_FCP = 4,\n\tDUMP_TYPE_NVME = 8,\n\tDUMP_TYPE_ECKD = 16,\n};\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nenum eer_trigger {\n\tDASD_EER_FATALERROR = 1,\n\tDASD_EER_NOPATH = 2,\n\tDASD_EER_STATECHANGE = 3,\n\tDASD_EER_PPRCSUSPEND = 4,\n\tDASD_EER_NOSPC = 5,\n\tDASD_EER_TIMEOUTS = 6,\n\tDASD_EER_STARTIO = 7,\n\tDASD_EER_MAX = 8,\n\tDASD_EER_AUTOQUIESCE = 31,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n\tETT_EVENT_EPROBE = 64,\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_FROZEN = 8,\n\tEVENT_CPU = 16,\n\tEVENT_CGROUP = 32,\n\tEVENT_GUEST = 64,\n\tEVENT_FLAGS = 96,\n\tEVENT_ALL = 3,\n\tEVENT_TIME_FROZEN = 12,\n};\n\nenum evm_ima_xattr_type {\n\tIMA_XATTR_DIGEST = 1,\n\tEVM_XATTR_HMAC = 2,\n\tEVM_IMA_XATTR_DIGSIG = 3,\n\tIMA_XATTR_DIGEST_NG = 4,\n\tEVM_XATTR_PORTABLE_DIGSIG = 5,\n\tIMA_VERITY_DIGSIG = 6,\n\tIMA_XATTR_LAST = 7,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum ext4_journal_trigger_type {\n\tEXT4_JTR_ORPHAN_FILE = 0,\n\tEXT4_JTR_NONE = 1,\n};\n\nenum ext4_li_mode {\n\tEXT4_LI_MODE_PREFETCH_BBITMAP = 0,\n\tEXT4_LI_MODE_ITABLE = 1,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum fanotify_event_type {\n\tFANOTIFY_EVENT_TYPE_FID = 0,\n\tFANOTIFY_EVENT_TYPE_FID_NAME = 1,\n\tFANOTIFY_EVENT_TYPE_PATH = 2,\n\tFANOTIFY_EVENT_TYPE_PATH_PERM = 3,\n\tFANOTIFY_EVENT_TYPE_OVERFLOW = 4,\n\tFANOTIFY_EVENT_TYPE_FS_ERROR = 5,\n\tFANOTIFY_EVENT_TYPE_MNT = 6,\n\t__FANOTIFY_EVENT_TYPE_NUM = 7,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_EDATA = 10,\n\tFETCH_OP_DEREF = 11,\n\tFETCH_OP_UDEREF = 12,\n\tFETCH_OP_ST_RAW = 13,\n\tFETCH_OP_ST_MEM = 14,\n\tFETCH_OP_ST_UMEM = 15,\n\tFETCH_OP_ST_STRING = 16,\n\tFETCH_OP_ST_USTRING = 17,\n\tFETCH_OP_ST_SYMSTR = 18,\n\tFETCH_OP_ST_EDATA = 19,\n\tFETCH_OP_MOD_BF = 20,\n\tFETCH_OP_LP_ARRAY = 21,\n\tFETCH_OP_TP_ARG = 22,\n\tFETCH_OP_END = 23,\n\tFETCH_NOP_SYMBOL = 24,\n};\n\nenum fib6_walk_state {\n\tFWS_S = 0,\n\tFWS_L = 1,\n\tFWS_R = 2,\n\tFWS_C = 3,\n\tFWS_U = 4,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum field_op_id {\n\tFIELD_OP_NONE = 0,\n\tFIELD_OP_PLUS = 1,\n\tFIELD_OP_MINUS = 2,\n\tFIELD_OP_UNARY_MINUS = 3,\n\tFIELD_OP_DIV = 4,\n\tFIELD_OP_MULT = 5,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum filter_pred_fn {\n\tFILTER_PRED_FN_NOP = 0,\n\tFILTER_PRED_FN_64 = 1,\n\tFILTER_PRED_FN_64_CPUMASK = 2,\n\tFILTER_PRED_FN_S64 = 3,\n\tFILTER_PRED_FN_U64 = 4,\n\tFILTER_PRED_FN_32 = 5,\n\tFILTER_PRED_FN_32_CPUMASK = 6,\n\tFILTER_PRED_FN_S32 = 7,\n\tFILTER_PRED_FN_U32 = 8,\n\tFILTER_PRED_FN_16 = 9,\n\tFILTER_PRED_FN_16_CPUMASK = 10,\n\tFILTER_PRED_FN_S16 = 11,\n\tFILTER_PRED_FN_U16 = 12,\n\tFILTER_PRED_FN_8 = 13,\n\tFILTER_PRED_FN_8_CPUMASK = 14,\n\tFILTER_PRED_FN_S8 = 15,\n\tFILTER_PRED_FN_U8 = 16,\n\tFILTER_PRED_FN_COMM = 17,\n\tFILTER_PRED_FN_STRING = 18,\n\tFILTER_PRED_FN_STRLOC = 19,\n\tFILTER_PRED_FN_STRRELLOC = 20,\n\tFILTER_PRED_FN_PCHAR_USER = 21,\n\tFILTER_PRED_FN_PCHAR = 22,\n\tFILTER_PRED_FN_CPU = 23,\n\tFILTER_PRED_FN_CPU_CPUMASK = 24,\n\tFILTER_PRED_FN_CPUMASK = 25,\n\tFILTER_PRED_FN_CPUMASK_CPU = 26,\n\tFILTER_PRED_FN_FUNCTION = 27,\n\tFILTER_PRED_FN_ = 28,\n\tFILTER_PRED_TEST_VISITED = 29,\n};\n\nenum finalization_type {\n\tFINALIZATION_TYPE_FINAL = 0,\n\tFINALIZATION_TYPE_FINUP = 1,\n\tFINALIZATION_TYPE_DIGEST = 2,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum flag_bits {\n\tFaulty = 0,\n\tIn_sync = 1,\n\tBitmap_sync = 2,\n\tWriteMostly = 3,\n\tAutoDetected = 4,\n\tBlocked = 5,\n\tWriteErrorSeen = 6,\n\tFaultRecorded = 7,\n\tBlockedBadBlocks = 8,\n\tWantReplacement = 9,\n\tReplacement = 10,\n\tCandidate = 11,\n\tJournal = 12,\n\tClusterRemove = 13,\n\tExternalBbl = 14,\n\tFailFast = 15,\n\tLastDev = 16,\n\tCollisionCheck = 17,\n\tNonrot = 18,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum flowlabel_reflect {\n\tFLOWLABEL_REFLECT_ESTABLISHED = 1,\n\tFLOWLABEL_REFLECT_TCP_RESET = 2,\n\tFLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4,\n};\n\nenum flush_type {\n\tFLUSH_TYPE_NONE = 0,\n\tFLUSH_TYPE_FLUSH = 1,\n\tFLUSH_TYPE_REIMPORT = 2,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftrace_bug_type {\n\tFTRACE_BUG_UNKNOWN = 0,\n\tFTRACE_BUG_INIT = 1,\n\tFTRACE_BUG_NOP = 2,\n\tFTRACE_BUG_CALL = 3,\n\tFTRACE_BUG_UPDATE = 4,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum ftrace_ops_cmd {\n\tFTRACE_OPS_CMD_ENABLE_SHARE_IPMODIFY_SELF = 0,\n\tFTRACE_OPS_CMD_ENABLE_SHARE_IPMODIFY_PEER = 1,\n\tFTRACE_OPS_CMD_DISABLE_SHARE_IPMODIFY_PEER = 2,\n};\n\nenum fullness_group {\n\tZS_INUSE_RATIO_0 = 0,\n\tZS_INUSE_RATIO_10 = 1,\n\tZS_INUSE_RATIO_99 = 10,\n\tZS_INUSE_RATIO_100 = 11,\n\tNR_FULLNESS_GROUPS = 12,\n};\n\nenum fuse_dax_mode {\n\tFUSE_DAX_INODE_DEFAULT = 0,\n\tFUSE_DAX_ALWAYS = 1,\n\tFUSE_DAX_NEVER = 2,\n\tFUSE_DAX_INODE_USER = 3,\n};\n\nenum fuse_ext_type {\n\tFUSE_MAX_NR_SECCTX = 31,\n\tFUSE_EXT_GROUPS = 32,\n};\n\nenum fuse_notify_code {\n\tFUSE_NOTIFY_POLL = 1,\n\tFUSE_NOTIFY_INVAL_INODE = 2,\n\tFUSE_NOTIFY_INVAL_ENTRY = 3,\n\tFUSE_NOTIFY_STORE = 4,\n\tFUSE_NOTIFY_RETRIEVE = 5,\n\tFUSE_NOTIFY_DELETE = 6,\n\tFUSE_NOTIFY_RESEND = 7,\n\tFUSE_NOTIFY_INC_EPOCH = 8,\n\tFUSE_NOTIFY_PRUNE = 9,\n};\n\nenum fuse_opcode {\n\tFUSE_LOOKUP = 1,\n\tFUSE_FORGET = 2,\n\tFUSE_GETATTR = 3,\n\tFUSE_SETATTR = 4,\n\tFUSE_READLINK = 5,\n\tFUSE_SYMLINK = 6,\n\tFUSE_MKNOD = 8,\n\tFUSE_MKDIR = 9,\n\tFUSE_UNLINK = 10,\n\tFUSE_RMDIR = 11,\n\tFUSE_RENAME = 12,\n\tFUSE_LINK = 13,\n\tFUSE_OPEN = 14,\n\tFUSE_READ = 15,\n\tFUSE_WRITE = 16,\n\tFUSE_STATFS = 17,\n\tFUSE_RELEASE = 18,\n\tFUSE_FSYNC = 20,\n\tFUSE_SETXATTR = 21,\n\tFUSE_GETXATTR = 22,\n\tFUSE_LISTXATTR = 23,\n\tFUSE_REMOVEXATTR = 24,\n\tFUSE_FLUSH = 25,\n\tFUSE_INIT = 26,\n\tFUSE_OPENDIR = 27,\n\tFUSE_READDIR = 28,\n\tFUSE_RELEASEDIR = 29,\n\tFUSE_FSYNCDIR = 30,\n\tFUSE_GETLK = 31,\n\tFUSE_SETLK = 32,\n\tFUSE_SETLKW = 33,\n\tFUSE_ACCESS = 34,\n\tFUSE_CREATE = 35,\n\tFUSE_INTERRUPT = 36,\n\tFUSE_BMAP = 37,\n\tFUSE_DESTROY = 38,\n\tFUSE_IOCTL = 39,\n\tFUSE_POLL = 40,\n\tFUSE_NOTIFY_REPLY = 41,\n\tFUSE_BATCH_FORGET = 42,\n\tFUSE_FALLOCATE = 43,\n\tFUSE_READDIRPLUS = 44,\n\tFUSE_RENAME2 = 45,\n\tFUSE_LSEEK = 46,\n\tFUSE_COPY_FILE_RANGE = 47,\n\tFUSE_SETUPMAPPING = 48,\n\tFUSE_REMOVEMAPPING = 49,\n\tFUSE_SYNCFS = 50,\n\tFUSE_TMPFILE = 51,\n\tFUSE_STATX = 52,\n\tFUSE_COPY_FILE_RANGE_64 = 53,\n\tCUSE_INIT = 4096,\n\tCUSE_INIT_BSWAP_RESERVED = 1048576,\n\tFUSE_INIT_BSWAP_RESERVED = 436207616,\n};\n\nenum fuse_parse_result {\n\tFOUND_ERR = -1,\n\tFOUND_NONE = 0,\n\tFOUND_SOME = 1,\n\tFOUND_ALL = 2,\n};\n\nenum fuse_req_flag {\n\tFR_ISREPLY = 0,\n\tFR_FORCE = 1,\n\tFR_BACKGROUND = 2,\n\tFR_WAITING = 3,\n\tFR_ABORTED = 4,\n\tFR_INTERRUPTED = 5,\n\tFR_LOCKED = 6,\n\tFR_PENDING = 7,\n\tFR_SENT = 8,\n\tFR_FINISHED = 9,\n\tFR_PRIVATE = 10,\n\tFR_ASYNC = 11,\n\tFR_URING = 12,\n};\n\nenum fuse_ring_req_state {\n\tFRRS_INVALID = 0,\n\tFRRS_COMMIT = 1,\n\tFRRS_AVAILABLE = 2,\n\tFRRS_FUSE_REQ = 3,\n\tFRRS_USERSPACE = 4,\n\tFRRS_TEARDOWN = 5,\n\tFRRS_RELEASED = 6,\n};\n\nenum fuse_uring_cmd {\n\tFUSE_IO_URING_CMD_INVALID = 0,\n\tFUSE_IO_URING_CMD_REGISTER = 1,\n\tFUSE_IO_URING_CMD_COMMIT_AND_FETCH = 2,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum graph_filter_type {\n\tGRAPH_FILTER_NOTRACE = 0,\n\tGRAPH_FILTER_FUNCTION = 1,\n};\n\nenum gre_conntrack {\n\tGRE_CT_UNREPLIED = 0,\n\tGRE_CT_REPLIED = 1,\n\tGRE_CT_MAX = 2,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum handler_id {\n\tHANDLER_ONMATCH = 1,\n\tHANDLER_ONMAX = 2,\n\tHANDLER_ONCHANGE = 3,\n};\n\nenum handshake_auth {\n\tHANDSHAKE_AUTH_UNSPEC = 0,\n\tHANDSHAKE_AUTH_UNAUTH = 1,\n\tHANDSHAKE_AUTH_PSK = 2,\n\tHANDSHAKE_AUTH_X509 = 3,\n};\n\nenum handshake_handler_class {\n\tHANDSHAKE_HANDLER_CLASS_NONE = 0,\n\tHANDSHAKE_HANDLER_CLASS_TLSHD = 1,\n\tHANDSHAKE_HANDLER_CLASS_MAX = 2,\n};\n\nenum handshake_msg_type {\n\tHANDSHAKE_MSG_TYPE_UNSPEC = 0,\n\tHANDSHAKE_MSG_TYPE_CLIENTHELLO = 1,\n\tHANDSHAKE_MSG_TYPE_SERVERHELLO = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum hdmi_3d_structure {\n\tHDMI_3D_STRUCTURE_INVALID = -1,\n\tHDMI_3D_STRUCTURE_FRAME_PACKING = 0,\n\tHDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1,\n\tHDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3,\n\tHDMI_3D_STRUCTURE_L_DEPTH = 4,\n\tHDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5,\n\tHDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8,\n};\n\nenum hdmi_active_aspect {\n\tHDMI_ACTIVE_ASPECT_16_9_TOP = 2,\n\tHDMI_ACTIVE_ASPECT_14_9_TOP = 3,\n\tHDMI_ACTIVE_ASPECT_16_9_CENTER = 4,\n\tHDMI_ACTIVE_ASPECT_PICTURE = 8,\n\tHDMI_ACTIVE_ASPECT_4_3 = 9,\n\tHDMI_ACTIVE_ASPECT_16_9 = 10,\n\tHDMI_ACTIVE_ASPECT_14_9 = 11,\n\tHDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15,\n};\n\nenum hdmi_audio_coding_type {\n\tHDMI_AUDIO_CODING_TYPE_STREAM = 0,\n\tHDMI_AUDIO_CODING_TYPE_PCM = 1,\n\tHDMI_AUDIO_CODING_TYPE_AC3 = 2,\n\tHDMI_AUDIO_CODING_TYPE_MPEG1 = 3,\n\tHDMI_AUDIO_CODING_TYPE_MP3 = 4,\n\tHDMI_AUDIO_CODING_TYPE_MPEG2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_DTS = 7,\n\tHDMI_AUDIO_CODING_TYPE_ATRAC = 8,\n\tHDMI_AUDIO_CODING_TYPE_DSD = 9,\n\tHDMI_AUDIO_CODING_TYPE_EAC3 = 10,\n\tHDMI_AUDIO_CODING_TYPE_DTS_HD = 11,\n\tHDMI_AUDIO_CODING_TYPE_MLP = 12,\n\tHDMI_AUDIO_CODING_TYPE_DST = 13,\n\tHDMI_AUDIO_CODING_TYPE_WMA_PRO = 14,\n\tHDMI_AUDIO_CODING_TYPE_CXT = 15,\n};\n\nenum hdmi_audio_coding_type_ext {\n\tHDMI_AUDIO_CODING_TYPE_EXT_CT = 0,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_EXT_DRA = 7,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10,\n};\n\nenum hdmi_audio_sample_frequency {\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7,\n};\n\nenum hdmi_audio_sample_size {\n\tHDMI_AUDIO_SAMPLE_SIZE_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_SIZE_16 = 1,\n\tHDMI_AUDIO_SAMPLE_SIZE_20 = 2,\n\tHDMI_AUDIO_SAMPLE_SIZE_24 = 3,\n};\n\nenum hdmi_colorimetry {\n\tHDMI_COLORIMETRY_NONE = 0,\n\tHDMI_COLORIMETRY_ITU_601 = 1,\n\tHDMI_COLORIMETRY_ITU_709 = 2,\n\tHDMI_COLORIMETRY_EXTENDED = 3,\n};\n\nenum hdmi_colorspace {\n\tHDMI_COLORSPACE_RGB = 0,\n\tHDMI_COLORSPACE_YUV422 = 1,\n\tHDMI_COLORSPACE_YUV444 = 2,\n\tHDMI_COLORSPACE_YUV420 = 3,\n\tHDMI_COLORSPACE_RESERVED4 = 4,\n\tHDMI_COLORSPACE_RESERVED5 = 5,\n\tHDMI_COLORSPACE_RESERVED6 = 6,\n\tHDMI_COLORSPACE_IDO_DEFINED = 7,\n};\n\nenum hdmi_content_type {\n\tHDMI_CONTENT_TYPE_GRAPHICS = 0,\n\tHDMI_CONTENT_TYPE_PHOTO = 1,\n\tHDMI_CONTENT_TYPE_CINEMA = 2,\n\tHDMI_CONTENT_TYPE_GAME = 3,\n};\n\nenum hdmi_eotf {\n\tHDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0,\n\tHDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1,\n\tHDMI_EOTF_SMPTE_ST2084 = 2,\n\tHDMI_EOTF_BT_2100_HLG = 3,\n};\n\nenum hdmi_extended_colorimetry {\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0,\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1,\n\tHDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2,\n\tHDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3,\n\tHDMI_EXTENDED_COLORIMETRY_OPRGB = 4,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020 = 6,\n\tHDMI_EXTENDED_COLORIMETRY_RESERVED = 7,\n};\n\nenum hdmi_infoframe_type {\n\tHDMI_INFOFRAME_TYPE_VENDOR = 129,\n\tHDMI_INFOFRAME_TYPE_AVI = 130,\n\tHDMI_INFOFRAME_TYPE_SPD = 131,\n\tHDMI_INFOFRAME_TYPE_AUDIO = 132,\n\tHDMI_INFOFRAME_TYPE_DRM = 135,\n};\n\nenum hdmi_metadata_type {\n\tHDMI_STATIC_METADATA_TYPE1 = 0,\n};\n\nenum hdmi_nups {\n\tHDMI_NUPS_UNKNOWN = 0,\n\tHDMI_NUPS_HORIZONTAL = 1,\n\tHDMI_NUPS_VERTICAL = 2,\n\tHDMI_NUPS_BOTH = 3,\n};\n\nenum hdmi_picture_aspect {\n\tHDMI_PICTURE_ASPECT_NONE = 0,\n\tHDMI_PICTURE_ASPECT_4_3 = 1,\n\tHDMI_PICTURE_ASPECT_16_9 = 2,\n\tHDMI_PICTURE_ASPECT_64_27 = 3,\n\tHDMI_PICTURE_ASPECT_256_135 = 4,\n\tHDMI_PICTURE_ASPECT_RESERVED = 5,\n};\n\nenum hdmi_quantization_range {\n\tHDMI_QUANTIZATION_RANGE_DEFAULT = 0,\n\tHDMI_QUANTIZATION_RANGE_LIMITED = 1,\n\tHDMI_QUANTIZATION_RANGE_FULL = 2,\n\tHDMI_QUANTIZATION_RANGE_RESERVED = 3,\n};\n\nenum hdmi_scan_mode {\n\tHDMI_SCAN_MODE_NONE = 0,\n\tHDMI_SCAN_MODE_OVERSCAN = 1,\n\tHDMI_SCAN_MODE_UNDERSCAN = 2,\n\tHDMI_SCAN_MODE_RESERVED = 3,\n};\n\nenum hdmi_spd_sdi {\n\tHDMI_SPD_SDI_UNKNOWN = 0,\n\tHDMI_SPD_SDI_DSTB = 1,\n\tHDMI_SPD_SDI_DVDP = 2,\n\tHDMI_SPD_SDI_DVHS = 3,\n\tHDMI_SPD_SDI_HDDVR = 4,\n\tHDMI_SPD_SDI_DVC = 5,\n\tHDMI_SPD_SDI_DSC = 6,\n\tHDMI_SPD_SDI_VCD = 7,\n\tHDMI_SPD_SDI_GAME = 8,\n\tHDMI_SPD_SDI_PC = 9,\n\tHDMI_SPD_SDI_BD = 10,\n\tHDMI_SPD_SDI_SACD = 11,\n\tHDMI_SPD_SDI_HDDVD = 12,\n\tHDMI_SPD_SDI_PMP = 13,\n};\n\nenum hdmi_ycc_quantization_range {\n\tHDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0,\n\tHDMI_YCC_QUANTIZATION_RANGE_FULL = 1,\n};\n\nenum hdr_flags {\n\tHDR_NOT_LPAR = 16,\n\tHDR_STACK_INCM = 32,\n\tHDR_STSI_UNAV = 64,\n\tHDR_PERF_UNAV = 128,\n};\n\nenum header_fields {\n\tHDR_PCR = 0,\n\tHDR_DIGEST = 1,\n\tHDR_TEMPLATE_NAME = 2,\n\tHDR_TEMPLATE_DATA = 3,\n\tHDR__LAST = 4,\n};\n\nenum hist_field_flags {\n\tHIST_FIELD_FL_HITCOUNT = 1,\n\tHIST_FIELD_FL_KEY = 2,\n\tHIST_FIELD_FL_STRING = 4,\n\tHIST_FIELD_FL_HEX = 8,\n\tHIST_FIELD_FL_SYM = 16,\n\tHIST_FIELD_FL_SYM_OFFSET = 32,\n\tHIST_FIELD_FL_EXECNAME = 64,\n\tHIST_FIELD_FL_SYSCALL = 128,\n\tHIST_FIELD_FL_STACKTRACE = 256,\n\tHIST_FIELD_FL_LOG2 = 512,\n\tHIST_FIELD_FL_TIMESTAMP = 1024,\n\tHIST_FIELD_FL_TIMESTAMP_USECS = 2048,\n\tHIST_FIELD_FL_VAR = 4096,\n\tHIST_FIELD_FL_EXPR = 8192,\n\tHIST_FIELD_FL_VAR_REF = 16384,\n\tHIST_FIELD_FL_CPU = 32768,\n\tHIST_FIELD_FL_ALIAS = 65536,\n\tHIST_FIELD_FL_BUCKET = 131072,\n\tHIST_FIELD_FL_CONST = 262144,\n\tHIST_FIELD_FL_PERCENT = 524288,\n\tHIST_FIELD_FL_GRAPH = 1048576,\n\tHIST_FIELD_FL_COMM = 2097152,\n};\n\nenum hist_field_fn {\n\tHIST_FIELD_FN_NOP = 0,\n\tHIST_FIELD_FN_VAR_REF = 1,\n\tHIST_FIELD_FN_COUNTER = 2,\n\tHIST_FIELD_FN_CONST = 3,\n\tHIST_FIELD_FN_LOG2 = 4,\n\tHIST_FIELD_FN_BUCKET = 5,\n\tHIST_FIELD_FN_TIMESTAMP = 6,\n\tHIST_FIELD_FN_CPU = 7,\n\tHIST_FIELD_FN_COMM = 8,\n\tHIST_FIELD_FN_STRING = 9,\n\tHIST_FIELD_FN_DYNSTRING = 10,\n\tHIST_FIELD_FN_RELDYNSTRING = 11,\n\tHIST_FIELD_FN_PSTRING = 12,\n\tHIST_FIELD_FN_S64 = 13,\n\tHIST_FIELD_FN_U64 = 14,\n\tHIST_FIELD_FN_S32 = 15,\n\tHIST_FIELD_FN_U32 = 16,\n\tHIST_FIELD_FN_S16 = 17,\n\tHIST_FIELD_FN_U16 = 18,\n\tHIST_FIELD_FN_S8 = 19,\n\tHIST_FIELD_FN_U8 = 20,\n\tHIST_FIELD_FN_UMINUS = 21,\n\tHIST_FIELD_FN_MINUS = 22,\n\tHIST_FIELD_FN_PLUS = 23,\n\tHIST_FIELD_FN_DIV = 24,\n\tHIST_FIELD_FN_MULT = 25,\n\tHIST_FIELD_FN_DIV_POWER2 = 26,\n\tHIST_FIELD_FN_DIV_NOT_POWER2 = 27,\n\tHIST_FIELD_FN_DIV_MULT_SHIFT = 28,\n\tHIST_FIELD_FN_EXECNAME = 29,\n\tHIST_FIELD_FN_STACK = 30,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hmm_pfn_flags {\n\tHMM_PFN_VALID = 9223372036854775808ULL,\n\tHMM_PFN_WRITE = 4611686018427387904ULL,\n\tHMM_PFN_ERROR = 2305843009213693952ULL,\n\tHMM_PFN_DMA_MAPPED = 1152921504606846976ULL,\n\tHMM_PFN_P2PDMA = 576460752303423488ULL,\n\tHMM_PFN_P2PDMA_BUS = 288230376151711744ULL,\n\tHMM_PFN_ORDER_SHIFT = 53ULL,\n\tHMM_PFN_REQ_FAULT = 9223372036854775808ULL,\n\tHMM_PFN_REQ_WRITE = 4611686018427387904ULL,\n\tHMM_PFN_FLAGS = 18437736874454810624ULL,\n};\n\nenum hn_flags_bits {\n\tHANDSHAKE_F_NET_DRAINING = 0,\n};\n\nenum hp_flags_bits {\n\tHANDSHAKE_F_PROTO_NOTIFY = 0,\n};\n\nenum hprobe_state {\n\tHPROBE_LEASED = 0,\n\tHPROBE_STABLE = 1,\n\tHPROBE_GONE = 2,\n\tHPROBE_CONSUMED = 3,\n};\n\nenum hr_flags_bits {\n\tHANDSHAKE_F_REQ_COMPLETED = 0,\n\tHANDSHAKE_F_REQ_SESSION = 1,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hugetlb_memory_event {\n\tHUGETLB_MAX = 0,\n\tHUGETLB_NR_MEMORY_EVENTS = 1,\n};\n\nenum hugetlb_page_flags {\n\tHPG_restore_reserve = 0,\n\tHPG_migratable = 1,\n\tHPG_temporary = 2,\n\tHPG_freed = 3,\n\tHPG_vmemmap_optimized = 4,\n\tHPG_raw_hwp_unreliable = 5,\n\tHPG_cma = 6,\n\t__NR_HPAGEFLAGS = 7,\n};\n\nenum hugetlb_param {\n\tOpt_gid___6 = 0,\n\tOpt_min_size = 1,\n\tOpt_mode___5 = 2,\n\tOpt_nr_inodes = 3,\n\tOpt_pagesize = 4,\n\tOpt_size = 5,\n\tOpt_uid___6 = 6,\n};\n\nenum hugetlbfs_size_type {\n\tNO_SIZE = 0,\n\tSIZE_STD = 1,\n\tSIZE_PERCENT = 2,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwerr_error_type {\n\tHWERR_RECOV_CPU = 0,\n\tHWERR_RECOV_MEMORY = 1,\n\tHWERR_RECOV_PCI = 2,\n\tHWERR_RECOV_CXL = 3,\n\tHWERR_RECOV_OTHERS = 4,\n\tHWERR_RECOV_MAX = 5,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum ib_atomic_cap {\n\tIB_ATOMIC_NONE = 0,\n\tIB_ATOMIC_HCA = 1,\n\tIB_ATOMIC_GLOB = 2,\n};\n\nenum ib_cq_notify_flags {\n\tIB_CQ_SOLICITED = 1,\n\tIB_CQ_NEXT_COMP = 2,\n\tIB_CQ_SOLICITED_MASK = 3,\n\tIB_CQ_REPORT_MISSED_EVENTS = 4,\n};\n\nenum ib_event_type {\n\tIB_EVENT_CQ_ERR = 0,\n\tIB_EVENT_QP_FATAL = 1,\n\tIB_EVENT_QP_REQ_ERR = 2,\n\tIB_EVENT_QP_ACCESS_ERR = 3,\n\tIB_EVENT_COMM_EST = 4,\n\tIB_EVENT_SQ_DRAINED = 5,\n\tIB_EVENT_PATH_MIG = 6,\n\tIB_EVENT_PATH_MIG_ERR = 7,\n\tIB_EVENT_DEVICE_FATAL = 8,\n\tIB_EVENT_PORT_ACTIVE = 9,\n\tIB_EVENT_PORT_ERR = 10,\n\tIB_EVENT_LID_CHANGE = 11,\n\tIB_EVENT_PKEY_CHANGE = 12,\n\tIB_EVENT_SM_CHANGE = 13,\n\tIB_EVENT_SRQ_ERR = 14,\n\tIB_EVENT_SRQ_LIMIT_REACHED = 15,\n\tIB_EVENT_QP_LAST_WQE_REACHED = 16,\n\tIB_EVENT_CLIENT_REREGISTER = 17,\n\tIB_EVENT_GID_CHANGE = 18,\n\tIB_EVENT_WQ_FATAL = 19,\n\tIB_EVENT_DEVICE_SPEED_CHANGE = 20,\n};\n\nenum ib_flow_action_type {\n\tIB_FLOW_ACTION_UNSPECIFIED = 0,\n\tIB_FLOW_ACTION_ESP = 1,\n};\n\nenum ib_flow_attr_type {\n\tIB_FLOW_ATTR_NORMAL = 0,\n\tIB_FLOW_ATTR_ALL_DEFAULT = 1,\n\tIB_FLOW_ATTR_MC_DEFAULT = 2,\n\tIB_FLOW_ATTR_SNIFFER = 3,\n};\n\nenum ib_flow_spec_type {\n\tIB_FLOW_SPEC_ETH = 32,\n\tIB_FLOW_SPEC_IB = 34,\n\tIB_FLOW_SPEC_IPV4 = 48,\n\tIB_FLOW_SPEC_IPV6 = 49,\n\tIB_FLOW_SPEC_ESP = 52,\n\tIB_FLOW_SPEC_TCP = 64,\n\tIB_FLOW_SPEC_UDP = 65,\n\tIB_FLOW_SPEC_VXLAN_TUNNEL = 80,\n\tIB_FLOW_SPEC_GRE = 81,\n\tIB_FLOW_SPEC_MPLS = 96,\n\tIB_FLOW_SPEC_INNER = 256,\n\tIB_FLOW_SPEC_ACTION_TAG = 4096,\n\tIB_FLOW_SPEC_ACTION_DROP = 4097,\n\tIB_FLOW_SPEC_ACTION_HANDLE = 4098,\n\tIB_FLOW_SPEC_ACTION_COUNT = 4099,\n};\n\nenum ib_gid_type {\n\tIB_GID_TYPE_IB = 0,\n\tIB_GID_TYPE_ROCE = 1,\n\tIB_GID_TYPE_ROCE_UDP_ENCAP = 2,\n\tIB_GID_TYPE_SIZE = 3,\n};\n\nenum ib_mig_state {\n\tIB_MIG_MIGRATED = 0,\n\tIB_MIG_REARM = 1,\n\tIB_MIG_ARMED = 2,\n};\n\nenum ib_mr_type {\n\tIB_MR_TYPE_MEM_REG = 0,\n\tIB_MR_TYPE_SG_GAPS = 1,\n\tIB_MR_TYPE_DM = 2,\n\tIB_MR_TYPE_USER = 3,\n\tIB_MR_TYPE_DMA = 4,\n\tIB_MR_TYPE_INTEGRITY = 5,\n};\n\nenum ib_mtu {\n\tIB_MTU_256 = 1,\n\tIB_MTU_512 = 2,\n\tIB_MTU_1024 = 3,\n\tIB_MTU_2048 = 4,\n\tIB_MTU_4096 = 5,\n};\n\nenum ib_mw_type {\n\tIB_MW_TYPE_1 = 1,\n\tIB_MW_TYPE_2 = 2,\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nenum ib_port_state {\n\tIB_PORT_NOP = 0,\n\tIB_PORT_DOWN = 1,\n\tIB_PORT_INIT = 2,\n\tIB_PORT_ARMED = 3,\n\tIB_PORT_ACTIVE = 4,\n\tIB_PORT_ACTIVE_DEFER = 5,\n};\n\nenum ib_qp_state {\n\tIB_QPS_RESET = 0,\n\tIB_QPS_INIT = 1,\n\tIB_QPS_RTR = 2,\n\tIB_QPS_RTS = 3,\n\tIB_QPS_SQD = 4,\n\tIB_QPS_SQE = 5,\n\tIB_QPS_ERR = 6,\n};\n\nenum ib_qp_type {\n\tIB_QPT_SMI = 0,\n\tIB_QPT_GSI = 1,\n\tIB_QPT_RC = 2,\n\tIB_QPT_UC = 3,\n\tIB_QPT_UD = 4,\n\tIB_QPT_RAW_IPV6 = 5,\n\tIB_QPT_RAW_ETHERTYPE = 6,\n\tIB_QPT_RAW_PACKET = 8,\n\tIB_QPT_XRC_INI = 9,\n\tIB_QPT_XRC_TGT = 10,\n\tIB_QPT_MAX = 11,\n\tIB_QPT_DRIVER = 255,\n\tIB_QPT_RESERVED1 = 4096,\n\tIB_QPT_RESERVED2 = 4097,\n\tIB_QPT_RESERVED3 = 4098,\n\tIB_QPT_RESERVED4 = 4099,\n\tIB_QPT_RESERVED5 = 4100,\n\tIB_QPT_RESERVED6 = 4101,\n\tIB_QPT_RESERVED7 = 4102,\n\tIB_QPT_RESERVED8 = 4103,\n\tIB_QPT_RESERVED9 = 4104,\n\tIB_QPT_RESERVED10 = 4105,\n};\n\nenum ib_sig_err_type {\n\tIB_SIG_BAD_GUARD = 0,\n\tIB_SIG_BAD_REFTAG = 1,\n\tIB_SIG_BAD_APPTAG = 2,\n};\n\nenum ib_sig_type {\n\tIB_SIGNAL_ALL_WR = 0,\n\tIB_SIGNAL_REQ_WR = 1,\n};\n\nenum ib_signature_type {\n\tIB_SIG_TYPE_NONE = 0,\n\tIB_SIG_TYPE_T10_DIF = 1,\n};\n\nenum ib_srq_attr_mask {\n\tIB_SRQ_MAX_WR = 1,\n\tIB_SRQ_LIMIT = 2,\n};\n\nenum ib_srq_type {\n\tIB_SRQT_BASIC = 0,\n\tIB_SRQT_XRC = 1,\n\tIB_SRQT_TM = 2,\n};\n\nenum ib_t10_dif_bg_type {\n\tIB_T10DIF_CRC = 0,\n\tIB_T10DIF_CSUM = 1,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_FLUSH_GLOBAL = 256,\n\tIB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_advise_mr_advice {\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2,\n};\n\nenum ib_uverbs_device_cap_flags {\n\tIB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL,\n\tIB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL,\n\tIB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL,\n\tIB_UVERBS_DEVICE_RAW_MULTI = 8ULL,\n\tIB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL,\n\tIB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL,\n\tIB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL,\n\tIB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL,\n\tIB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL,\n\tIB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL,\n\tIB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL,\n\tIB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL,\n\tIB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL,\n\tIB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL,\n\tIB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL,\n\tIB_UVERBS_DEVICE_XRC = 1048576ULL,\n\tIB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL,\n\tIB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL,\n\tIB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL,\n\tIB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL,\n\tIB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL,\n\tIB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL,\n\tIB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL,\n\tIB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL,\n\tIB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL,\n};\n\nenum ib_uverbs_gid_type {\n\tIB_UVERBS_GID_TYPE_IB = 0,\n\tIB_UVERBS_GID_TYPE_ROCE_V1 = 1,\n\tIB_UVERBS_GID_TYPE_ROCE_V2 = 2,\n};\n\nenum ib_uverbs_odp_general_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT = 1,\n\tIB_UVERBS_ODP_SUPPORT_IMPLICIT = 2,\n};\n\nenum ib_uverbs_odp_transport_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT_SEND = 1,\n\tIB_UVERBS_ODP_SUPPORT_RECV = 2,\n\tIB_UVERBS_ODP_SUPPORT_WRITE = 4,\n\tIB_UVERBS_ODP_SUPPORT_READ = 8,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC = 16,\n\tIB_UVERBS_ODP_SUPPORT_SRQ_RECV = 32,\n\tIB_UVERBS_ODP_SUPPORT_FLUSH = 64,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 128,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_raw_packet_caps {\n\tIB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2,\n\tIB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4,\n\tIB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wc_opcode {\n\tIB_UVERBS_WC_SEND = 0,\n\tIB_UVERBS_WC_RDMA_WRITE = 1,\n\tIB_UVERBS_WC_RDMA_READ = 2,\n\tIB_UVERBS_WC_COMP_SWAP = 3,\n\tIB_UVERBS_WC_FETCH_ADD = 4,\n\tIB_UVERBS_WC_BIND_MW = 5,\n\tIB_UVERBS_WC_LOCAL_INV = 6,\n\tIB_UVERBS_WC_TSO = 7,\n\tIB_UVERBS_WC_FLUSH = 8,\n\tIB_UVERBS_WC_ATOMIC_WRITE = 9,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_UVERBS_WR_FLUSH = 14,\n\tIB_UVERBS_WR_ATOMIC_WRITE = 15,\n};\n\nenum ib_wc_opcode {\n\tIB_WC_SEND = 0,\n\tIB_WC_RDMA_WRITE = 1,\n\tIB_WC_RDMA_READ = 2,\n\tIB_WC_COMP_SWAP = 3,\n\tIB_WC_FETCH_ADD = 4,\n\tIB_WC_BIND_MW = 5,\n\tIB_WC_LOCAL_INV = 6,\n\tIB_WC_LSO = 7,\n\tIB_WC_ATOMIC_WRITE = 9,\n\tIB_WC_REG_MR = 10,\n\tIB_WC_MASKED_COMP_SWAP = 11,\n\tIB_WC_MASKED_FETCH_ADD = 12,\n\tIB_WC_FLUSH = 8,\n\tIB_WC_RECV = 128,\n\tIB_WC_RECV_RDMA_WITH_IMM = 129,\n};\n\nenum ib_wc_status {\n\tIB_WC_SUCCESS = 0,\n\tIB_WC_LOC_LEN_ERR = 1,\n\tIB_WC_LOC_QP_OP_ERR = 2,\n\tIB_WC_LOC_EEC_OP_ERR = 3,\n\tIB_WC_LOC_PROT_ERR = 4,\n\tIB_WC_WR_FLUSH_ERR = 5,\n\tIB_WC_MW_BIND_ERR = 6,\n\tIB_WC_BAD_RESP_ERR = 7,\n\tIB_WC_LOC_ACCESS_ERR = 8,\n\tIB_WC_REM_INV_REQ_ERR = 9,\n\tIB_WC_REM_ACCESS_ERR = 10,\n\tIB_WC_REM_OP_ERR = 11,\n\tIB_WC_RETRY_EXC_ERR = 12,\n\tIB_WC_RNR_RETRY_EXC_ERR = 13,\n\tIB_WC_LOC_RDD_VIOL_ERR = 14,\n\tIB_WC_REM_INV_RD_REQ_ERR = 15,\n\tIB_WC_REM_ABORT_ERR = 16,\n\tIB_WC_INV_EECN_ERR = 17,\n\tIB_WC_INV_EEC_STATE_ERR = 18,\n\tIB_WC_FATAL_ERR = 19,\n\tIB_WC_RESP_TIMEOUT_ERR = 20,\n\tIB_WC_GENERAL_ERR = 21,\n};\n\nenum ib_wq_state {\n\tIB_WQS_RESET = 0,\n\tIB_WQS_RDY = 1,\n\tIB_WQS_ERR = 2,\n};\n\nenum ib_wq_type {\n\tIB_WQT_RQ = 0,\n};\n\nenum ib_wr_opcode {\n\tIB_WR_RDMA_WRITE = 0,\n\tIB_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_WR_SEND = 2,\n\tIB_WR_SEND_WITH_IMM = 3,\n\tIB_WR_RDMA_READ = 4,\n\tIB_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_WR_BIND_MW = 8,\n\tIB_WR_LSO = 10,\n\tIB_WR_SEND_WITH_INV = 9,\n\tIB_WR_RDMA_READ_WITH_INV = 11,\n\tIB_WR_LOCAL_INV = 7,\n\tIB_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_WR_FLUSH = 14,\n\tIB_WR_ATOMIC_WRITE = 15,\n\tIB_WR_REG_MR = 32,\n\tIB_WR_REG_MR_INTEGRITY = 33,\n\tIB_WR_RESERVED1 = 240,\n\tIB_WR_RESERVED2 = 241,\n\tIB_WR_RESERVED3 = 242,\n\tIB_WR_RESERVED4 = 243,\n\tIB_WR_RESERVED5 = 244,\n\tIB_WR_RESERVED6 = 245,\n\tIB_WR_RESERVED7 = 246,\n\tIB_WR_RESERVED8 = 247,\n\tIB_WR_RESERVED9 = 248,\n\tIB_WR_RESERVED10 = 249,\n};\n\nenum id_action {\n\tID_REMOVE = 0,\n\tID_ADD = 1,\n};\n\nenum ima_fs_flags {\n\tIMA_FS_BUSY = 0,\n};\n\nenum ima_hooks {\n\tNONE = 0,\n\tFILE_CHECK = 1,\n\tMMAP_CHECK = 2,\n\tMMAP_CHECK_REQPROT = 3,\n\tBPRM_CHECK = 4,\n\tCREDS_CHECK = 5,\n\tPOST_SETATTR = 6,\n\tMODULE_CHECK = 7,\n\tFIRMWARE_CHECK = 8,\n\tKEXEC_KERNEL_CHECK = 9,\n\tKEXEC_INITRAMFS_CHECK = 10,\n\tPOLICY_CHECK = 11,\n\tKEXEC_CMDLINE = 12,\n\tKEY_CHECK = 13,\n\tCRITICAL_DATA = 14,\n\tSETXATTR_CHECK = 15,\n\tMAX_CHECK = 16,\n};\n\nenum ima_show_type {\n\tIMA_SHOW_BINARY = 0,\n\tIMA_SHOW_BINARY_NO_FIELD_LEN = 1,\n\tIMA_SHOW_BINARY_OLD_STRING_FMT = 2,\n\tIMA_SHOW_ASCII = 3,\n};\n\nenum in6_addr_gen_mode {\n\tIN6_ADDR_GEN_MODE_EUI64 = 0,\n\tIN6_ADDR_GEN_MODE_NONE = 1,\n\tIN6_ADDR_GEN_MODE_STABLE_PRIVACY = 2,\n\tIN6_ADDR_GEN_MODE_RANDOM = 3,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state {\n\tinode_state_no_change = 0,\n\tinode_state_will_create = 1,\n\tinode_state_did_create = 2,\n\tinode_state_will_delete = 3,\n\tinode_state_did_delete = 4,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum inplace_mode {\n\tOUT_OF_PLACE = 0,\n\tINPLACE_ONE_SGLIST = 1,\n\tINPLACE_TWO_SGLISTS = 2,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum integrity_status {\n\tINTEGRITY_PASS = 0,\n\tINTEGRITY_PASS_IMMUTABLE = 1,\n\tINTEGRITY_FAIL = 2,\n\tINTEGRITY_FAIL_IMMUTABLE = 3,\n\tINTEGRITY_NOLABEL = 4,\n\tINTEGRITY_NOXATTRS = 5,\n\tINTEGRITY_UNKNOWN = 6,\n};\n\nenum interruption_class {\n\tIRQEXT_CLK = 0,\n\tIRQEXT_EXC = 1,\n\tIRQEXT_EMS = 2,\n\tIRQEXT_TMR = 3,\n\tIRQEXT_TLA = 4,\n\tIRQEXT_PFL = 5,\n\tIRQEXT_DSD = 6,\n\tIRQEXT_VRT = 7,\n\tIRQEXT_SCP = 8,\n\tIRQEXT_IUC = 9,\n\tIRQEXT_CMS = 10,\n\tIRQEXT_CMC = 11,\n\tIRQEXT_FTP = 12,\n\tIRQEXT_WTI = 13,\n\tIRQIO_CIO = 14,\n\tIRQIO_DAS = 15,\n\tIRQIO_C15 = 16,\n\tIRQIO_C70 = 17,\n\tIRQIO_TAP = 18,\n\tIRQIO_VMR = 19,\n\tIRQIO_CTC = 20,\n\tIRQIO_ADM = 21,\n\tIRQIO_CSC = 22,\n\tIRQIO_VIR = 23,\n\tIRQIO_QAI = 24,\n\tIRQIO_APB = 25,\n\tIRQIO_PCF = 26,\n\tIRQIO_PCD = 27,\n\tIRQIO_MSI = 28,\n\tIRQIO_VAI = 29,\n\tIRQIO_GAL = 30,\n\tNMI_NMI = 31,\n\tCPU_RST = 32,\n\tNR_ARCH_IRQS = 33,\n};\n\nenum io_sch_action {\n\tIO_SCH_UNREG = 0,\n\tIO_SCH_ORPH_UNREG = 1,\n\tIO_SCH_UNREG_CDEV = 2,\n\tIO_SCH_ATTACH = 3,\n\tIO_SCH_UNREG_ATTACH = 4,\n\tIO_SCH_ORPH_ATTACH = 5,\n\tIO_SCH_REPROBE = 6,\n\tIO_SCH_VERIFY = 7,\n\tIO_SCH_DISC = 8,\n\tIO_SCH_NOP = 9,\n\tIO_SCH_ORPH_CDEV = 10,\n};\n\nenum io_status {\n\tIO_DONE = 0,\n\tIO_RUNNING = 1,\n\tIO_STATUS_ERROR = 2,\n\tIO_PATH_ERROR = 3,\n\tIO_REJECTED = 4,\n\tIO_KILLED = 5,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioam6_event_attr {\n\tIOAM6_EVENT_ATTR_UNSPEC = 0,\n\tIOAM6_EVENT_ATTR_TRACE_NAMESPACE = 1,\n\tIOAM6_EVENT_ATTR_TRACE_NODELEN = 2,\n\tIOAM6_EVENT_ATTR_TRACE_TYPE = 3,\n\tIOAM6_EVENT_ATTR_TRACE_DATA = 4,\n\t__IOAM6_EVENT_ATTR_MAX = 5,\n};\n\nenum ioam6_event_type {\n\tIOAM6_EVENT_UNSPEC = 0,\n\tIOAM6_EVENT_TRACE = 1,\n};\n\nenum ioc_running {\n\tIOC_IDLE = 0,\n\tIOC_RUNNING = 1,\n\tIOC_STOP = 2,\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_NOEXEC = 1,\n\tIOMMU_CAP_PRE_BOOT_PROTECTION = 2,\n\tIOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3,\n\tIOMMU_CAP_DEFERRED_FLUSH = 4,\n\tIOMMU_CAP_DIRTY_TRACKING = 5,\n};\n\nenum iommu_dma_queue_type {\n\tIOMMU_DMA_OPTS_PER_CPU_QUEUE = 0,\n\tIOMMU_DMA_OPTS_SINGLE_QUEUE = 1,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum iommu_hw_info_type {\n\tIOMMU_HW_INFO_TYPE_NONE = 0,\n\tIOMMU_HW_INFO_TYPE_DEFAULT = 0,\n\tIOMMU_HW_INFO_TYPE_INTEL_VTD = 1,\n\tIOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,\n\tIOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,\n\tIOMMU_HW_INFO_TYPE_AMD = 4,\n};\n\nenum iommu_hw_queue_type {\n\tIOMMU_HW_QUEUE_TYPE_DEFAULT = 0,\n\tIOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,\n};\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nenum iommu_viommu_type {\n\tIOMMU_VIOMMU_TYPE_DEFAULT = 0,\n\tIOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,\n\tIOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,\n};\n\nenum iommufd_hwpt_alloc_flags {\n\tIOMMU_HWPT_ALLOC_NEST_PARENT = 1,\n\tIOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2,\n\tIOMMU_HWPT_FAULT_ID_VALID = 4,\n\tIOMMU_HWPT_ALLOC_PASID = 8,\n};\n\nenum iommufd_object_type {\n\tIOMMUFD_OBJ_NONE = 0,\n\tIOMMUFD_OBJ_ANY = 0,\n\tIOMMUFD_OBJ_DEVICE = 1,\n\tIOMMUFD_OBJ_HWPT_PAGING = 2,\n\tIOMMUFD_OBJ_HWPT_NESTED = 3,\n\tIOMMUFD_OBJ_IOAS = 4,\n\tIOMMUFD_OBJ_ACCESS = 5,\n\tIOMMUFD_OBJ_FAULT = 6,\n\tIOMMUFD_OBJ_VIOMMU = 7,\n\tIOMMUFD_OBJ_VDEVICE = 8,\n\tIOMMUFD_OBJ_VEVENTQ = 9,\n\tIOMMUFD_OBJ_HW_QUEUE = 10,\n\tIOMMUFD_OBJ_MAX = 11,\n};\n\nenum ip6_defrag_users {\n\tIP6_DEFRAG_LOCAL_DELIVER = 0,\n\tIP6_DEFRAG_CONNTRACK_IN = 1,\n\t__IP6_DEFRAG_CONNTRACK_IN = 65536,\n\tIP6_DEFRAG_CONNTRACK_OUT = 65537,\n\t__IP6_DEFRAG_CONNTRACK_OUT = 131072,\n\tIP6_DEFRAG_CONNTRACK_BRIDGE_IN = 131073,\n\t__IP6_DEFRAG_CONNTRACK_BRIDGE_IN = 196608,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_conntrack_info {\n\tIP_CT_ESTABLISHED = 0,\n\tIP_CT_RELATED = 1,\n\tIP_CT_NEW = 2,\n\tIP_CT_IS_REPLY = 3,\n\tIP_CT_ESTABLISHED_REPLY = 3,\n\tIP_CT_RELATED_REPLY = 4,\n\tIP_CT_NUMBER = 5,\n\tIP_CT_UNTRACKED = 7,\n};\n\nenum ip_conntrack_status {\n\tIPS_EXPECTED_BIT = 0,\n\tIPS_EXPECTED = 1,\n\tIPS_SEEN_REPLY_BIT = 1,\n\tIPS_SEEN_REPLY = 2,\n\tIPS_ASSURED_BIT = 2,\n\tIPS_ASSURED = 4,\n\tIPS_CONFIRMED_BIT = 3,\n\tIPS_CONFIRMED = 8,\n\tIPS_SRC_NAT_BIT = 4,\n\tIPS_SRC_NAT = 16,\n\tIPS_DST_NAT_BIT = 5,\n\tIPS_DST_NAT = 32,\n\tIPS_NAT_MASK = 48,\n\tIPS_SEQ_ADJUST_BIT = 6,\n\tIPS_SEQ_ADJUST = 64,\n\tIPS_SRC_NAT_DONE_BIT = 7,\n\tIPS_SRC_NAT_DONE = 128,\n\tIPS_DST_NAT_DONE_BIT = 8,\n\tIPS_DST_NAT_DONE = 256,\n\tIPS_NAT_DONE_MASK = 384,\n\tIPS_DYING_BIT = 9,\n\tIPS_DYING = 512,\n\tIPS_FIXED_TIMEOUT_BIT = 10,\n\tIPS_FIXED_TIMEOUT = 1024,\n\tIPS_TEMPLATE_BIT = 11,\n\tIPS_TEMPLATE = 2048,\n\tIPS_UNTRACKED_BIT = 12,\n\tIPS_UNTRACKED = 4096,\n\tIPS_NAT_CLASH_BIT = 12,\n\tIPS_NAT_CLASH = 4096,\n\tIPS_HELPER_BIT = 13,\n\tIPS_HELPER = 8192,\n\tIPS_OFFLOAD_BIT = 14,\n\tIPS_OFFLOAD = 16384,\n\tIPS_HW_OFFLOAD_BIT = 15,\n\tIPS_HW_OFFLOAD = 32768,\n\tIPS_UNCHANGEABLE_MASK = 56313,\n\t__IPS_MAX_BIT = 16,\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum ipl_pbt {\n\tIPL_PBT_FCP = 0,\n\tIPL_PBT_SCP_DATA = 1,\n\tIPL_PBT_CCW = 2,\n\tIPL_PBT_ECKD = 3,\n\tIPL_PBT_NVME = 4,\n};\n\nenum ipl_rbt {\n\tIPL_RBT_CERTIFICATES = 1,\n\tIPL_RBT_COMPONENTS = 2,\n};\n\nenum ipl_type {\n\tIPL_TYPE_UNKNOWN = 1,\n\tIPL_TYPE_CCW = 2,\n\tIPL_TYPE_FCP = 4,\n\tIPL_TYPE_FCP_DUMP = 8,\n\tIPL_TYPE_NSS = 16,\n\tIPL_TYPE_NVME = 32,\n\tIPL_TYPE_NVME_DUMP = 64,\n\tIPL_TYPE_ECKD = 128,\n\tIPL_TYPE_ECKD_DUMP = 256,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irq_subclass {\n\tIRQ_SUBCLASS_MEASUREMENT_ALERT = 5,\n\tIRQ_SUBCLASS_SERVICE_SIGNAL = 9,\n\tIRQ_SUBCLASS_WARNING_TRACK = 33,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum isofs_file_format {\n\tisofs_file_normal = 0,\n\tisofs_file_sparse = 1,\n\tisofs_file_compressed = 2,\n};\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum iucv_command_codes {\n\tIUCV_QUERY = 0,\n\tIUCV_RETRIEVE_BUFFER = 2,\n\tIUCV_SEND = 4,\n\tIUCV_RECEIVE = 5,\n\tIUCV_REPLY = 6,\n\tIUCV_REJECT = 8,\n\tIUCV_PURGE = 9,\n\tIUCV_ACCEPT = 10,\n\tIUCV_CONNECT = 11,\n\tIUCV_DECLARE_BUFFER = 12,\n\tIUCV_QUIESCE = 13,\n\tIUCV_RESUME = 14,\n\tIUCV_SEVER = 15,\n\tIUCV_SETMASK = 16,\n\tIUCV_SETCONTROLMASK = 17,\n};\n\nenum iucv_state_t {\n\tIUCV_DISCONN = 0,\n\tIUCV_CONNECTED = 1,\n\tIUCV_SEVERED = 2,\n};\n\nenum iucv_tx_notify {\n\tTX_NOTIFY_OK = 0,\n\tTX_NOTIFY_UNREACHABLE = 1,\n\tTX_NOTIFY_TPQFULL = 2,\n\tTX_NOTIFY_GENERALERROR = 3,\n\tTX_NOTIFY_PENDING = 4,\n\tTX_NOTIFY_DELAYED_OK = 5,\n\tTX_NOTIFY_DELAYED_UNREACHABLE = 6,\n\tTX_NOTIFY_DELAYED_GENERALERROR = 7,\n};\n\nenum jbd2_shrink_type {\n\tJBD2_SHRINK_DESTROY = 0,\n\tJBD2_SHRINK_BUSY_STOP = 1,\n\tJBD2_SHRINK_BUSY_SKIP = 2,\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 17,\n\tBH_JWrite = 18,\n\tBH_Freed = 19,\n\tBH_Revoked = 20,\n\tBH_RevokeValid = 21,\n\tBH_JBDDirty = 22,\n\tBH_JournalHead = 23,\n\tBH_Shadow = 24,\n\tBH_Verified = 25,\n\tBH_JBDPrivateStart = 26,\n};\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nenum kcmp_type {\n\tKCMP_FILE = 0,\n\tKCMP_VM = 1,\n\tKCMP_FILES = 2,\n\tKCMP_FS = 3,\n\tKCMP_SIGHAND = 4,\n\tKCMP_IO = 5,\n\tKCMP_SYSVSEM = 6,\n\tKCMP_EPOLL_TFD = 7,\n\tKCMP_TYPES = 8,\n};\n\nenum kcore_type {\n\tKCORE_TEXT = 0,\n\tKCORE_VMALLOC = 1,\n\tKCORE_RAM = 2,\n\tKCORE_VMEMMAP = 3,\n\tKCORE_USER = 4,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_being_used_for {\n\tVERIFYING_MODULE_SIGNATURE = 0,\n\tVERIFYING_FIRMWARE_SIGNATURE = 1,\n\tVERIFYING_KEXEC_PE_SIGNATURE = 2,\n\tVERIFYING_KEY_SIGNATURE = 3,\n\tVERIFYING_KEY_SELF_SIGNATURE = 4,\n\tVERIFYING_UNSPECIFIED_SIGNATURE = 5,\n\tVERIFYING_BPF_SIGNATURE = 6,\n\tNR__KEY_BEING_USED_FOR = 7,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_DMA = 2,\n\tKMALLOC_CGROUP = 3,\n\tNR_KMALLOC_TYPES = 4,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum kprobe_slot_state {\n\tSLOT_CLEAN = 0,\n\tSLOT_DIRTY = 1,\n\tSLOT_USED = 2,\n};\n\nenum ksm_advisor_type {\n\tKSM_ADVISOR_NONE = 0,\n\tKSM_ADVISOR_SCAN_TIME = 1,\n};\n\nenum ksm_get_folio_flags {\n\tKSM_GET_FOLIO_NOLOCK = 0,\n\tKSM_GET_FOLIO_LOCK = 1,\n\tKSM_GET_FOLIO_TRYLOCK = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum kunit_speed {\n\tKUNIT_SPEED_UNSET = 0,\n\tKUNIT_SPEED_VERY_SLOW = 1,\n\tKUNIT_SPEED_SLOW = 2,\n\tKUNIT_SPEED_NORMAL = 3,\n\tKUNIT_SPEED_MAX = 3,\n};\n\nenum kunit_status {\n\tKUNIT_SUCCESS = 0,\n\tKUNIT_FAILURE = 1,\n\tKUNIT_SKIPPED = 2,\n};\n\nenum kvm_bus {\n\tKVM_MMIO_BUS = 0,\n\tKVM_PIO_BUS = 1,\n\tKVM_VIRTIO_CCW_NOTIFY_BUS = 2,\n\tKVM_FAST_MMIO_BUS = 3,\n\tKVM_IOCSR_BUS = 4,\n\tKVM_NR_BUSES = 5,\n};\n\nenum kvm_stat_kind {\n\tKVM_STAT_VM = 0,\n\tKVM_STAT_VCPU = 1,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum label_initialized {\n\tLABEL_INVALID = 0,\n\tLABEL_INITIALIZED = 1,\n\tLABEL_PENDING = 2,\n};\n\nenum landlock_key_type {\n\tLANDLOCK_KEY_INODE = 1,\n\tLANDLOCK_KEY_NET_PORT = 2,\n};\n\nenum landlock_log_status {\n\tLANDLOCK_LOG_PENDING = 0,\n\tLANDLOCK_LOG_RECORDED = 1,\n\tLANDLOCK_LOG_DISABLED = 2,\n};\n\nenum landlock_request_type {\n\tLANDLOCK_REQUEST_PTRACE = 1,\n\tLANDLOCK_REQUEST_FS_CHANGE_TOPOLOGY = 2,\n\tLANDLOCK_REQUEST_FS_ACCESS = 3,\n\tLANDLOCK_REQUEST_NET_ACCESS = 4,\n\tLANDLOCK_REQUEST_SCOPE_ABSTRACT_UNIX_SOCKET = 5,\n\tLANDLOCK_REQUEST_SCOPE_SIGNAL = 6,\n};\n\nenum landlock_rule_type {\n\tLANDLOCK_RULE_PATH_BENEATH = 1,\n\tLANDLOCK_RULE_NET_PORT = 2,\n};\n\nenum layout_break_reason {\n\tBREAK_WRITE = 0,\n\tBREAK_UNMAP = 1,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum linux_mptcp_mib_field {\n\tMPTCP_MIB_NUM = 0,\n\tMPTCP_MIB_MPCAPABLEPASSIVE = 1,\n\tMPTCP_MIB_MPCAPABLEACTIVE = 2,\n\tMPTCP_MIB_MPCAPABLEACTIVEACK = 3,\n\tMPTCP_MIB_MPCAPABLEPASSIVEACK = 4,\n\tMPTCP_MIB_MPCAPABLEPASSIVEFALLBACK = 5,\n\tMPTCP_MIB_MPCAPABLEACTIVEFALLBACK = 6,\n\tMPTCP_MIB_MPCAPABLEACTIVEDROP = 7,\n\tMPTCP_MIB_MPCAPABLEACTIVEDISABLED = 8,\n\tMPTCP_MIB_MPCAPABLEENDPATTEMPT = 9,\n\tMPTCP_MIB_TOKENFALLBACKINIT = 10,\n\tMPTCP_MIB_RETRANSSEGS = 11,\n\tMPTCP_MIB_JOINNOTOKEN = 12,\n\tMPTCP_MIB_JOINSYNRX = 13,\n\tMPTCP_MIB_JOINSYNBACKUPRX = 14,\n\tMPTCP_MIB_JOINSYNACKRX = 15,\n\tMPTCP_MIB_JOINSYNACKBACKUPRX = 16,\n\tMPTCP_MIB_JOINSYNACKMAC = 17,\n\tMPTCP_MIB_JOINACKRX = 18,\n\tMPTCP_MIB_JOINACKMAC = 19,\n\tMPTCP_MIB_JOINREJECTED = 20,\n\tMPTCP_MIB_JOINSYNTX = 21,\n\tMPTCP_MIB_JOINSYNTXCREATSKERR = 22,\n\tMPTCP_MIB_JOINSYNTXBINDERR = 23,\n\tMPTCP_MIB_JOINSYNTXCONNECTERR = 24,\n\tMPTCP_MIB_DSSNOMATCH = 25,\n\tMPTCP_MIB_DSSCORRUPTIONFALLBACK = 26,\n\tMPTCP_MIB_DSSCORRUPTIONRESET = 27,\n\tMPTCP_MIB_INFINITEMAPTX = 28,\n\tMPTCP_MIB_INFINITEMAPRX = 29,\n\tMPTCP_MIB_DSSTCPMISMATCH = 30,\n\tMPTCP_MIB_DATACSUMERR = 31,\n\tMPTCP_MIB_OFOQUEUETAIL = 32,\n\tMPTCP_MIB_OFOQUEUE = 33,\n\tMPTCP_MIB_OFOMERGE = 34,\n\tMPTCP_MIB_NODSSWINDOW = 35,\n\tMPTCP_MIB_DUPDATA = 36,\n\tMPTCP_MIB_ADDADDR = 37,\n\tMPTCP_MIB_ADDADDRTX = 38,\n\tMPTCP_MIB_ADDADDRTXDROP = 39,\n\tMPTCP_MIB_ECHOADD = 40,\n\tMPTCP_MIB_ECHOADDTX = 41,\n\tMPTCP_MIB_ECHOADDTXDROP = 42,\n\tMPTCP_MIB_PORTADD = 43,\n\tMPTCP_MIB_ADDADDRDROP = 44,\n\tMPTCP_MIB_JOINPORTSYNRX = 45,\n\tMPTCP_MIB_JOINPORTSYNACKRX = 46,\n\tMPTCP_MIB_JOINPORTACKRX = 47,\n\tMPTCP_MIB_MISMATCHPORTSYNRX = 48,\n\tMPTCP_MIB_MISMATCHPORTACKRX = 49,\n\tMPTCP_MIB_RMADDR = 50,\n\tMPTCP_MIB_RMADDRDROP = 51,\n\tMPTCP_MIB_RMADDRTX = 52,\n\tMPTCP_MIB_RMADDRTXDROP = 53,\n\tMPTCP_MIB_RMSUBFLOW = 54,\n\tMPTCP_MIB_MPPRIOTX = 55,\n\tMPTCP_MIB_MPPRIORX = 56,\n\tMPTCP_MIB_MPFAILTX = 57,\n\tMPTCP_MIB_MPFAILRX = 58,\n\tMPTCP_MIB_MPFASTCLOSETX = 59,\n\tMPTCP_MIB_MPFASTCLOSERX = 60,\n\tMPTCP_MIB_MPRSTTX = 61,\n\tMPTCP_MIB_MPRSTRX = 62,\n\tMPTCP_MIB_SUBFLOWSTALE = 63,\n\tMPTCP_MIB_SUBFLOWRECOVER = 64,\n\tMPTCP_MIB_SNDWNDSHARED = 65,\n\tMPTCP_MIB_RCVWNDSHARED = 66,\n\tMPTCP_MIB_RCVWNDCONFLICTUPDATE = 67,\n\tMPTCP_MIB_RCVWNDCONFLICT = 68,\n\tMPTCP_MIB_CURRESTAB = 69,\n\tMPTCP_MIB_BLACKHOLE = 70,\n\tMPTCP_MIB_MPCAPABLEDATAFALLBACK = 71,\n\tMPTCP_MIB_MD5SIGFALLBACK = 72,\n\tMPTCP_MIB_DSSFALLBACK = 73,\n\tMPTCP_MIB_SIMULTCONNFALLBACK = 74,\n\tMPTCP_MIB_FALLBACKFAILED = 75,\n\tMPTCP_MIB_WINPROBE = 76,\n\t__MPTCP_MIB_MAX = 77,\n};\n\nenum llbitmap_action {\n\tBitmapActionStartwrite = 0,\n\tBitmapActionStartsync = 1,\n\tBitmapActionEndsync = 2,\n\tBitmapActionAbortsync = 3,\n\tBitmapActionReload = 4,\n\tBitmapActionDaemon = 5,\n\tBitmapActionDiscard = 6,\n\tBitmapActionStale = 7,\n\tBitmapActionCount = 8,\n\tBitmapActionInit = 9,\n};\n\nenum llbitmap_page_state {\n\tLLPageFlush = 0,\n\tLLPageDirty = 1,\n};\n\nenum llbitmap_state {\n\tBitUnwritten = 0,\n\tBitClean = 1,\n\tBitDirty = 2,\n\tBitNeedSync = 3,\n\tBitSyncing = 4,\n\tBitStateCount = 5,\n\tBitNone = 255,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lsm_event {\n\tLSM_POLICY_CHANGE = 0,\n\tLSM_STARTED_ALL = 1,\n};\n\nenum lsm_integrity_type {\n\tLSM_INT_DMVERITY_SIG_VALID = 0,\n\tLSM_INT_DMVERITY_ROOTHASH = 1,\n\tLSM_INT_FSVERITY_BUILTINSIG_VALID = 2,\n};\n\nenum lsm_order {\n\tLSM_ORDER_FIRST = -1,\n\tLSM_ORDER_MUTABLE = 0,\n\tLSM_ORDER_LAST = 1,\n};\n\nenum lsm_rule_types {\n\tLSM_OBJ_USER = 0,\n\tLSM_OBJ_ROLE = 1,\n\tLSM_OBJ_TYPE = 2,\n\tLSM_SUBJ_USER = 3,\n\tLSM_SUBJ_ROLE = 4,\n\tLSM_SUBJ_TYPE = 5,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum mac_validity {\n\tMAC_NAME_VLD = 32,\n\tMAC_ID_VLD = 64,\n\tMAC_CNT_VLD = 128,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum mapping_status {\n\tMAPPING_OK = 0,\n\tMAPPING_INVALID = 1,\n\tMAPPING_EMPTY = 2,\n\tMAPPING_DATA_FIN = 3,\n\tMAPPING_DUMMY = 4,\n\tMAPPING_BAD_CSUM = 5,\n\tMAPPING_NODSS = 6,\n};\n\nenum md_ro_state {\n\tMD_RDWR = 0,\n\tMD_RDONLY = 1,\n\tMD_AUTO_READ = 2,\n\tMD_MAX_STATE = 3,\n};\n\nenum md_submodule_id {\n\tID_LINEAR = -1,\n\tID_RAID0 = 0,\n\tID_RAID1 = 1,\n\tID_RAID4 = 4,\n\tID_RAID5 = 5,\n\tID_RAID6 = 6,\n\tID_RAID10 = 10,\n\tID_CLUSTER = 11,\n\tID_BITMAP = 12,\n\tID_LLBITMAP = 13,\n\tID_BITMAP_NONE = 14,\n};\n\nenum md_submodule_type {\n\tMD_PERSONALITY = 0,\n\tMD_CLUSTER = 1,\n\tMD_BITMAP = 2,\n};\n\nenum mddev_flags {\n\tMD_ARRAY_FIRST_USE = 0,\n\tMD_CLOSING = 1,\n\tMD_JOURNAL_CLEAN = 2,\n\tMD_HAS_JOURNAL = 3,\n\tMD_CLUSTER_RESYNC_LOCKED = 4,\n\tMD_FAILFAST_SUPPORTED = 5,\n\tMD_HAS_PPL = 6,\n\tMD_HAS_MULTIPLE_PPLS = 7,\n\tMD_NOT_READY = 8,\n\tMD_BROKEN = 9,\n\tMD_DO_DELETE = 10,\n\tMD_DELETED = 11,\n\tMD_HAS_SUPERBLOCK = 12,\n\tMD_FAILLAST_DEV = 13,\n\tMD_SERIALIZE_POLICY = 14,\n};\n\nenum mddev_sb_flags {\n\tMD_SB_CHANGE_DEVS = 0,\n\tMD_SB_CHANGE_CLEAN = 1,\n\tMD_SB_CHANGE_PENDING = 2,\n\tMD_SB_NEED_REWRITE = 3,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 51,\n\tMEMCG_SOCK = 52,\n\tMEMCG_PERCPU_B = 53,\n\tMEMCG_VMALLOC = 54,\n\tMEMCG_KMEM = 55,\n\tMEMCG_ZSWAP_B = 56,\n\tMEMCG_ZSWAPPED = 57,\n\tMEMCG_NR_STAT = 58,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mext_move_type {\n\tMEXT_SKIP_EXTENT = 0,\n\tMEXT_MOVE_EXTENT = 1,\n\tMEXT_COPY_DATA = 2,\n};\n\nenum mf_flags {\n\tMF_COUNT_INCREASED = 1,\n\tMF_ACTION_REQUIRED = 2,\n\tMF_MUST_KILL = 4,\n\tMF_SOFT_OFFLINE = 8,\n\tMF_UNPOISON = 16,\n\tMF_SW_SIMULATED = 32,\n\tMF_NO_RETRY = 64,\n\tMF_MEM_PRE_REMOVE = 128,\n};\n\nenum mfill_atomic_mode {\n\tMFILL_ATOMIC_COPY = 0,\n\tMFILL_ATOMIC_ZEROPAGE = 1,\n\tMFILL_ATOMIC_CONTINUE = 2,\n\tMFILL_ATOMIC_POISON = 3,\n\tNR_MFILL_ATOMIC_MODES = 4,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migrate_vma_direction {\n\tMIGRATE_VMA_SELECT_SYSTEM = 1,\n\tMIGRATE_VMA_SELECT_DEVICE_PRIVATE = 2,\n\tMIGRATE_VMA_SELECT_DEVICE_COHERENT = 4,\n\tMIGRATE_VMA_SELECT_COMPOUND = 8,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\tMIGRATE_CMA = 4,\n\t__MIGRATE_TYPE_END = 4,\n\tMIGRATE_ISOLATE = 5,\n\tMIGRATE_TYPES = 6,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum misc_res_type {\n\tMISC_CG_RES_TYPES = 0,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mmu_notifier_event {\n\tMMU_NOTIFY_UNMAP = 0,\n\tMMU_NOTIFY_CLEAR = 1,\n\tMMU_NOTIFY_PROTECTION_VMA = 2,\n\tMMU_NOTIFY_PROTECTION_PAGE = 3,\n\tMMU_NOTIFY_SOFT_DIRTY = 4,\n\tMMU_NOTIFY_RELEASE = 5,\n\tMMU_NOTIFY_MIGRATE = 6,\n\tMMU_NOTIFY_EXCLUSIVE = 7,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mptcp_addr_signal_status {\n\tMPTCP_ADD_ADDR_SIGNAL = 0,\n\tMPTCP_ADD_ADDR_ECHO = 1,\n\tMPTCP_RM_ADDR_SIGNAL = 2,\n};\n\nenum mptcp_event_attr {\n\tMPTCP_ATTR_UNSPEC = 0,\n\tMPTCP_ATTR_TOKEN = 1,\n\tMPTCP_ATTR_FAMILY = 2,\n\tMPTCP_ATTR_LOC_ID = 3,\n\tMPTCP_ATTR_REM_ID = 4,\n\tMPTCP_ATTR_SADDR4 = 5,\n\tMPTCP_ATTR_SADDR6 = 6,\n\tMPTCP_ATTR_DADDR4 = 7,\n\tMPTCP_ATTR_DADDR6 = 8,\n\tMPTCP_ATTR_SPORT = 9,\n\tMPTCP_ATTR_DPORT = 10,\n\tMPTCP_ATTR_BACKUP = 11,\n\tMPTCP_ATTR_ERROR = 12,\n\tMPTCP_ATTR_FLAGS = 13,\n\tMPTCP_ATTR_TIMEOUT = 14,\n\tMPTCP_ATTR_IF_IDX = 15,\n\tMPTCP_ATTR_RESET_REASON = 16,\n\tMPTCP_ATTR_RESET_FLAGS = 17,\n\tMPTCP_ATTR_SERVER_SIDE = 18,\n\t__MPTCP_ATTR_MAX = 19,\n};\n\nenum mptcp_event_type {\n\tMPTCP_EVENT_UNSPEC = 0,\n\tMPTCP_EVENT_CREATED = 1,\n\tMPTCP_EVENT_ESTABLISHED = 2,\n\tMPTCP_EVENT_CLOSED = 3,\n\tMPTCP_EVENT_ANNOUNCED = 6,\n\tMPTCP_EVENT_REMOVED = 7,\n\tMPTCP_EVENT_SUB_ESTABLISHED = 10,\n\tMPTCP_EVENT_SUB_CLOSED = 11,\n\tMPTCP_EVENT_SUB_PRIORITY = 13,\n\tMPTCP_EVENT_LISTENER_CREATED = 15,\n\tMPTCP_EVENT_LISTENER_CLOSED = 16,\n};\n\nenum mptcp_pm_status {\n\tMPTCP_PM_ADD_ADDR_RECEIVED = 0,\n\tMPTCP_PM_ADD_ADDR_SEND_ACK = 1,\n\tMPTCP_PM_RM_ADDR_RECEIVED = 2,\n\tMPTCP_PM_ESTABLISHED = 3,\n\tMPTCP_PM_SUBFLOW_ESTABLISHED = 4,\n\tMPTCP_PM_ALREADY_ESTABLISHED = 5,\n\tMPTCP_PM_MPC_ENDPOINT_ACCOUNTED = 6,\n};\n\nenum mptcp_pm_type {\n\tMPTCP_PM_TYPE_KERNEL = 0,\n\tMPTCP_PM_TYPE_USERSPACE = 1,\n\t__MPTCP_PM_TYPE_NR = 2,\n\t__MPTCP_PM_TYPE_MAX = 1,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum net_bridge_opts {\n\tBROPT_VLAN_ENABLED = 0,\n\tBROPT_VLAN_STATS_ENABLED = 1,\n\tBROPT_NF_CALL_IPTABLES = 2,\n\tBROPT_NF_CALL_IP6TABLES = 3,\n\tBROPT_NF_CALL_ARPTABLES = 4,\n\tBROPT_GROUP_ADDR_SET = 5,\n\tBROPT_MULTICAST_ENABLED = 6,\n\tBROPT_MULTICAST_QUERY_USE_IFADDR = 7,\n\tBROPT_MULTICAST_STATS_ENABLED = 8,\n\tBROPT_HAS_IPV6_ADDR = 9,\n\tBROPT_NEIGH_SUPPRESS_ENABLED = 10,\n\tBROPT_MTU_SET_BY_USER = 11,\n\tBROPT_VLAN_STATS_PER_PORT = 12,\n\tBROPT_NO_LL_LEARN = 13,\n\tBROPT_VLAN_BRIDGE_BINDING = 14,\n\tBROPT_MCAST_VLAN_SNOOPING_ENABLED = 15,\n\tBROPT_MST_ENABLED = 16,\n\tBROPT_MDB_OFFLOAD_FAIL_NOTIFICATION = 17,\n\tBROPT_FDB_LOCAL_VLAN_0 = 18,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum net_xmit_qdisc_t {\n\t__NET_XMIT_STOLEN = 65536,\n\t__NET_XMIT_BYPASS = 131072,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_ct_ext_id {\n\tNF_CT_EXT_HELPER = 0,\n\tNF_CT_EXT_NAT = 1,\n\tNF_CT_EXT_SEQADJ = 2,\n\tNF_CT_EXT_ACCT = 3,\n\tNF_CT_EXT_ECACHE = 4,\n\tNF_CT_EXT_TSTAMP = 5,\n\tNF_CT_EXT_TIMEOUT = 6,\n\tNF_CT_EXT_LABELS = 7,\n\tNF_CT_EXT_SYNPROXY = 8,\n\tNF_CT_EXT_ACT_CT = 9,\n\tNF_CT_EXT_NUM = 10,\n};\n\nenum nf_dev_hooks {\n\tNF_NETDEV_INGRESS = 0,\n\tNF_NETDEV_EGRESS = 1,\n\tNF_NETDEV_NUMHOOKS = 2,\n};\n\nenum nf_hook_ops_type {\n\tNF_HOOK_OP_UNDEFINED = 0,\n\tNF_HOOK_OP_NF_TABLES = 1,\n\tNF_HOOK_OP_BPF = 2,\n\tNF_HOOK_OP_NFT_FT = 3,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nf_ip6_hook_priorities {\n\tNF_IP6_PRI_FIRST = -2147483648,\n\tNF_IP6_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP6_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP6_PRI_RAW = -300,\n\tNF_IP6_PRI_SELINUX_FIRST = -225,\n\tNF_IP6_PRI_CONNTRACK = -200,\n\tNF_IP6_PRI_MANGLE = -150,\n\tNF_IP6_PRI_NAT_DST = -100,\n\tNF_IP6_PRI_FILTER = 0,\n\tNF_IP6_PRI_SECURITY = 50,\n\tNF_IP6_PRI_NAT_SRC = 100,\n\tNF_IP6_PRI_SELINUX_LAST = 225,\n\tNF_IP6_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP6_PRI_LAST = 2147483647,\n};\n\nenum nf_ip_hook_priorities {\n\tNF_IP_PRI_FIRST = -2147483648,\n\tNF_IP_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP_PRI_RAW = -300,\n\tNF_IP_PRI_SELINUX_FIRST = -225,\n\tNF_IP_PRI_CONNTRACK = -200,\n\tNF_IP_PRI_MANGLE = -150,\n\tNF_IP_PRI_NAT_DST = -100,\n\tNF_IP_PRI_FILTER = 0,\n\tNF_IP_PRI_SECURITY = 50,\n\tNF_IP_PRI_NAT_SRC = 100,\n\tNF_IP_PRI_SELINUX_LAST = 225,\n\tNF_IP_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP_PRI_CONNTRACK_CONFIRM = 2147483647,\n\tNF_IP_PRI_LAST = 2147483647,\n};\n\nenum nf_log_type {\n\tNF_LOG_TYPE_LOG = 0,\n\tNF_LOG_TYPE_ULOG = 1,\n\tNF_LOG_TYPE_MAX = 2,\n};\n\nenum nf_nat_manip_type;\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n\tNFS4ERR_NOXATTR = 10095,\n\tNFS4ERR_XATTR2BIG = 10096,\n\tNFS4ERR_FIRST_FREE = 10097,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_IOMMU_PAGES = 39,\n\tNR_SWAPCACHE = 40,\n\tPGPROMOTE_SUCCESS = 41,\n\tPGPROMOTE_CANDIDATE = 42,\n\tPGPROMOTE_CANDIDATE_NRL = 43,\n\tPGDEMOTE_KSWAPD = 44,\n\tPGDEMOTE_DIRECT = 45,\n\tPGDEMOTE_KHUGEPAGED = 46,\n\tPGDEMOTE_PROACTIVE = 47,\n\tNR_HUGETLB = 48,\n\tNR_BALLOON_PAGES = 49,\n\tNR_KERNEL_FILE_PAGES = 50,\n\tNR_VM_NODE_STAT_ITEMS = 51,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 2,\n\tN_MEMORY = 3,\n\tN_CPU = 4,\n\tN_GENERIC_INITIATOR = 5,\n\tNR_NODE_STATES = 6,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum numa_faults_stats {\n\tNUMA_MEM = 0,\n\tNUMA_CPU = 1,\n\tNUMA_MEMBUF = 2,\n\tNUMA_CPUBUF = 3,\n};\n\nenum numa_stat_item {\n\tNUMA_HIT = 0,\n\tNUMA_MISS = 1,\n\tNUMA_FOREIGN = 2,\n\tNUMA_INTERLEAVE_HIT = 3,\n\tNUMA_LOCAL = 4,\n\tNUMA_OTHER = 5,\n\tNR_VM_NUMA_EVENT_ITEMS = 6,\n};\n\nenum numa_topology_type {\n\tNUMA_DIRECT = 0,\n\tNUMA_GLUELESS_MESH = 1,\n\tNUMA_BACKPLANE = 2,\n};\n\nenum numa_type {\n\tnode_has_spare = 0,\n\tnode_fully_busy = 1,\n\tnode_overloaded = 2,\n};\n\nenum numa_vmaskip_reason {\n\tNUMAB_SKIP_UNSUITABLE = 0,\n\tNUMAB_SKIP_SHARED_RO = 1,\n\tNUMAB_SKIP_INACCESSIBLE = 2,\n\tNUMAB_SKIP_SCAN_DELAY = 3,\n\tNUMAB_SKIP_PID_INACTIVE = 4,\n\tNUMAB_SKIP_IGNORE_PID = 5,\n\tNUMAB_SKIP_SEQ_COMPLETED = 6,\n};\n\nenum objext_flags {\n\tOBJEXTS_ALLOC_FAIL = 1,\n\t__OBJEXTS_FLAG_UNUSED = 4,\n\t__NR_OBJEXTS_FLAGS = 8,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum page_memcg_data_flags {\n\tMEMCG_DATA_OBJEXTS = 1,\n\tMEMCG_DATA_KMEM = 2,\n\t__NR_MEMCG_DATA_FLAGS = 4,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 4096,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\tPB_migrate_isolate = 4,\n\t__NR_PAGEBLOCK_BITS = 5,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\tPG_young = 21,\n\tPG_idle = 22,\n\t__NR_PAGEFLAGS = 23,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_vmemmap_self_hosted = 10,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum par_flag {\n\tPAR_MT_EN = 128,\n};\n\nenum par_validity {\n\tPAR_GRP_VLD = 8,\n\tPAR_ID_VLD = 16,\n\tPAR_ABS_VLD = 32,\n\tPAR_WGHT_VLD = 64,\n\tPAR_PCNT_VLD = 128,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nenum pavtype {\n\tNO_PAV = 0,\n\tBASE_PAV = 1,\n\tHYPER_PAV = 2,\n};\n\nenum pb_isolate_mode {\n\tPB_ISOLATE_MODE_MEM_OFFLINE = 0,\n\tPB_ISOLATE_MODE_CMA_ALLOC = 1,\n\tPB_ISOLATE_MODE_OTHER = 2,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_hotplug_event {\n\tPCI_HOTPLUG_LINK_UP = 0,\n\tPCI_HOTPLUG_LINK_DOWN = 1,\n\tPCI_HOTPLUG_CARD_PRESENT = 2,\n\tPCI_HOTPLUG_CARD_NOT_PRESENT = 3,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum pedit_cmd {\n\tTCA_PEDIT_KEY_EX_CMD_SET = 0,\n\tTCA_PEDIT_KEY_EX_CMD_ADD = 1,\n\t__PEDIT_CMD_MAX = 2,\n};\n\nenum pedit_header_type {\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK = 0,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_ETH = 1,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP4 = 2,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP6 = 3,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_TCP = 4,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_UDP = 5,\n\t__PEDIT_HDR_TYPE_MAX = 6,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE = 262144,\n\tPERF_SAMPLE_BRANCH_COUNTERS = 524288,\n\tPERF_SAMPLE_BRANCH_MAX = 1048576,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 18446744073709551584ULL,\n\tPERF_CONTEXT_KERNEL = 18446744073709551488ULL,\n\tPERF_CONTEXT_USER = 18446744073709551104ULL,\n\tPERF_CONTEXT_USER_DEFERRED = 18446744073709550976ULL,\n\tPERF_CONTEXT_GUEST = 18446744073709549568ULL,\n\tPERF_CONTEXT_GUEST_KERNEL = 18446744073709549440ULL,\n\tPERF_CONTEXT_GUEST_USER = 18446744073709549056ULL,\n\tPERF_CONTEXT_MAX = 18446744073709547521ULL,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_LOST = 16,\n\tPERF_FORMAT_MAX = 32,\n};\n\nenum perf_event_s390_regs {\n\tPERF_REG_S390_R0 = 0,\n\tPERF_REG_S390_R1 = 1,\n\tPERF_REG_S390_R2 = 2,\n\tPERF_REG_S390_R3 = 3,\n\tPERF_REG_S390_R4 = 4,\n\tPERF_REG_S390_R5 = 5,\n\tPERF_REG_S390_R6 = 6,\n\tPERF_REG_S390_R7 = 7,\n\tPERF_REG_S390_R8 = 8,\n\tPERF_REG_S390_R9 = 9,\n\tPERF_REG_S390_R10 = 10,\n\tPERF_REG_S390_R11 = 11,\n\tPERF_REG_S390_R12 = 12,\n\tPERF_REG_S390_R13 = 13,\n\tPERF_REG_S390_R14 = 14,\n\tPERF_REG_S390_R15 = 15,\n\tPERF_REG_S390_FP0 = 16,\n\tPERF_REG_S390_FP1 = 17,\n\tPERF_REG_S390_FP2 = 18,\n\tPERF_REG_S390_FP3 = 19,\n\tPERF_REG_S390_FP4 = 20,\n\tPERF_REG_S390_FP5 = 21,\n\tPERF_REG_S390_FP6 = 22,\n\tPERF_REG_S390_FP7 = 23,\n\tPERF_REG_S390_FP8 = 24,\n\tPERF_REG_S390_FP9 = 25,\n\tPERF_REG_S390_FP10 = 26,\n\tPERF_REG_S390_FP11 = 27,\n\tPERF_REG_S390_FP12 = 28,\n\tPERF_REG_S390_FP13 = 29,\n\tPERF_REG_S390_FP14 = 30,\n\tPERF_REG_S390_FP15 = 31,\n\tPERF_REG_S390_MASK = 32,\n\tPERF_REG_S390_PC = 33,\n\tPERF_REG_S390_MAX = 34,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_DATA_PAGE_SIZE = 4194304,\n\tPERF_SAMPLE_CODE_PAGE_SIZE = 8388608,\n\tPERF_SAMPLE_WEIGHT_STRUCT = 16777216,\n\tPERF_SAMPLE_MAX = 33554432,\n};\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = -5,\n\tPERF_EVENT_STATE_REVOKED = -4,\n\tPERF_EVENT_STATE_EXIT = -3,\n\tPERF_EVENT_STATE_ERROR = -2,\n\tPERF_EVENT_STATE_OFF = -1,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = -1,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_TEXT_POKE = 20,\n\tPERF_RECORD_AUX_OUTPUT_HW_ID = 21,\n\tPERF_RECORD_CALLCHAIN_DEFERRED = 22,\n\tPERF_RECORD_MAX = 23,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_pmu_scope {\n\tPERF_PMU_SCOPE_NONE = 0,\n\tPERF_PMU_SCOPE_CORE = 1,\n\tPERF_PMU_SCOPE_DIE = 2,\n\tPERF_PMU_SCOPE_CLUSTER = 3,\n\tPERF_PMU_SCOPE_PKG = 4,\n\tPERF_PMU_SCOPE_SYS_WIDE = 5,\n\tPERF_PMU_MAX_SCOPE = 6,\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum physmem_info_source {\n\tMEM_DETECT_NONE = 0,\n\tMEM_DETECT_SCLP_STOR_INFO = 1,\n\tMEM_DETECT_DIAG260 = 2,\n\tMEM_DETECT_DIAG500_STOR_LIMIT = 3,\n\tMEM_DETECT_SCLP_READ_INFO = 4,\n\tMEM_DETECT_BIN_SEARCH = 5,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidcg_event {\n\tPIDCG_MAX = 0,\n\tPIDCG_FORKFAIL = 1,\n\tNR_PIDCG_EVENTS = 2,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum pkcs7_actions {\n\tACT_pkcs7_check_content_type = 0,\n\tACT_pkcs7_extract_cert = 1,\n\tACT_pkcs7_note_OID = 2,\n\tACT_pkcs7_note_certificate_list = 3,\n\tACT_pkcs7_note_content = 4,\n\tACT_pkcs7_note_data = 5,\n\tACT_pkcs7_note_signed_info = 6,\n\tACT_pkcs7_note_signeddata_version = 7,\n\tACT_pkcs7_note_signerinfo_version = 8,\n\tACT_pkcs7_sig_note_authenticated_attr = 9,\n\tACT_pkcs7_sig_note_digest_algo = 10,\n\tACT_pkcs7_sig_note_issuer = 11,\n\tACT_pkcs7_sig_note_pkey_algo = 12,\n\tACT_pkcs7_sig_note_serial = 13,\n\tACT_pkcs7_sig_note_set_of_authattrs = 14,\n\tACT_pkcs7_sig_note_signature = 15,\n\tACT_pkcs7_sig_note_skid = 16,\n\tNR__pkcs7_actions = 17,\n};\n\nenum pkey_id_type {\n\tPKEY_ID_PGP = 0,\n\tPKEY_ID_X509 = 1,\n\tPKEY_ID_PKCS7 = 2,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum policy_opt {\n\tOpt_measure = 0,\n\tOpt_dont_measure = 1,\n\tOpt_appraise = 2,\n\tOpt_dont_appraise = 3,\n\tOpt_audit = 4,\n\tOpt_dont_audit = 5,\n\tOpt_hash___2 = 6,\n\tOpt_dont_hash = 7,\n\tOpt_obj_user = 8,\n\tOpt_obj_role = 9,\n\tOpt_obj_type = 10,\n\tOpt_subj_user = 11,\n\tOpt_subj_role = 12,\n\tOpt_subj_type = 13,\n\tOpt_func = 14,\n\tOpt_mask = 15,\n\tOpt_fsmagic = 16,\n\tOpt_fsname = 17,\n\tOpt_fs_subtype = 18,\n\tOpt_fsuuid = 19,\n\tOpt_uid_eq = 20,\n\tOpt_euid_eq = 21,\n\tOpt_gid_eq = 22,\n\tOpt_egid_eq = 23,\n\tOpt_fowner_eq = 24,\n\tOpt_fgroup_eq = 25,\n\tOpt_uid_gt = 26,\n\tOpt_euid_gt = 27,\n\tOpt_gid_gt = 28,\n\tOpt_egid_gt = 29,\n\tOpt_fowner_gt = 30,\n\tOpt_fgroup_gt = 31,\n\tOpt_uid_lt = 32,\n\tOpt_euid_lt = 33,\n\tOpt_gid_lt = 34,\n\tOpt_egid_lt = 35,\n\tOpt_fowner_lt = 36,\n\tOpt_fgroup_lt = 37,\n\tOpt_digest_type = 38,\n\tOpt_appraise_type = 39,\n\tOpt_appraise_flag = 40,\n\tOpt_appraise_algos = 41,\n\tOpt_permit_directio = 42,\n\tOpt_pcr = 43,\n\tOpt_template = 44,\n\tOpt_keyrings = 45,\n\tOpt_label = 46,\n\tOpt_err___6 = 47,\n};\n\nenum policy_rule_list {\n\tIMA_DEFAULT_POLICY = 1,\n\tIMA_CUSTOM_POLICY = 2,\n};\n\nenum policy_types {\n\tORIGINAL_TCB = 1,\n\tDEFAULT_TCB = 2,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port_pkey_state {\n\tIB_PORT_PKEY_NOT_VALID = 0,\n\tIB_PORT_PKEY_VALID = 1,\n\tIB_PORT_PKEY_LISTED = 2,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum prio_policy {\n\tPOLICY_NO_CHANGE = 0,\n\tPOLICY_PROMOTE_TO_RT = 1,\n\tPOLICY_RESTRICT_TO_BE = 2,\n\tPOLICY_ALL_TO_IDLE = 3,\n\tPOLICY_NONE_TO_RT = 4,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_print_type {\n\tPROBE_PRINT_NORMAL = 0,\n\tPROBE_PRINT_RETURN = 1,\n\tPROBE_PRINT_EVENT = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_cn_mcast_op {\n\tPROC_CN_MCAST_LISTEN = 1,\n\tPROC_CN_MCAST_IGNORE = 2,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___7 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum pubkey_algo {\n\tPUBKEY_ALGO_RSA = 0,\n\tPUBKEY_ALGO_MAX = 1,\n};\n\nenum qdio_irq_poll_states {\n\tQDIO_IRQ_DISABLED = 0,\n};\n\nenum qdio_irq_states {\n\tQDIO_IRQ_STATE_INACTIVE = 0,\n\tQDIO_IRQ_STATE_ESTABLISHED = 1,\n\tQDIO_IRQ_STATE_ACTIVE = 2,\n\tQDIO_IRQ_STATE_STOPPED = 3,\n\tQDIO_IRQ_STATE_CLEANUP = 4,\n\tQDIO_IRQ_STATE_ERR = 5,\n\tNR_QDIO_IRQ_STATES = 6,\n};\n\nenum qdisc_class_ops_flags {\n\tQDISC_CLASS_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum qeth_addr_disposition {\n\tQETH_DISP_ADDR_DELETE = 0,\n\tQETH_DISP_ADDR_DO_NOTHING = 1,\n\tQETH_DISP_ADDR_ADD = 2,\n};\n\nenum qeth_an_event_type {\n\tanev_reg_unreg = 0,\n\tanev_abort = 1,\n\tanev_reset = 2,\n};\n\nenum qeth_arp_ipaddrtype {\n\tQETHARP_IP_ADDR_V4 = 1,\n\tQETHARP_IP_ADDR_V6 = 2,\n};\n\nenum qeth_arp_process_subcmds {\n\tIPA_CMD_ASS_ARP_SET_NO_ENTRIES = 3,\n\tIPA_CMD_ASS_ARP_QUERY_CACHE = 4,\n\tIPA_CMD_ASS_ARP_ADD_ENTRY = 5,\n\tIPA_CMD_ASS_ARP_REMOVE_ENTRY = 6,\n\tIPA_CMD_ASS_ARP_FLUSH_CACHE = 7,\n\tIPA_CMD_ASS_ARP_QUERY_INFO = 260,\n\tIPA_CMD_ASS_ARP_QUERY_STATS = 516,\n};\n\nenum qeth_card_states {\n\tCARD_STATE_DOWN = 0,\n\tCARD_STATE_SOFTSETUP = 1,\n};\n\nenum qeth_card_types {\n\tQETH_CARD_TYPE_OSD = 1,\n\tQETH_CARD_TYPE_IQD = 5,\n\tQETH_CARD_TYPE_OSM = 3,\n\tQETH_CARD_TYPE_OSX = 2,\n};\n\nenum qeth_cast_flags {\n\tQETH_CAST_UNICAST = 6,\n\tQETH_CAST_MULTICAST = 4,\n\tQETH_CAST_BROADCAST = 5,\n\tQETH_CAST_ANYCAST = 7,\n\tQETH_CAST_NOCAST = 0,\n};\n\nenum qeth_channel_states {\n\tCH_STATE_UP = 0,\n\tCH_STATE_DOWN = 1,\n\tCH_STATE_HALTED = 2,\n\tCH_STATE_STOPPED = 3,\n};\n\nenum qeth_cq {\n\tQETH_CQ_DISABLED = 0,\n\tQETH_CQ_ENABLED = 1,\n\tQETH_CQ_NOTAVAILABLE = 2,\n};\n\nenum qeth_dbf_names {\n\tQETH_DBF_SETUP = 0,\n\tQETH_DBF_MSG = 1,\n\tQETH_DBF_CTRL = 2,\n\tQETH_DBF_INFOS = 3,\n};\n\nenum qeth_diags_cmds {\n\tQETH_DIAGS_CMD_QUERY = 1,\n\tQETH_DIAGS_CMD_TRAP = 2,\n\tQETH_DIAGS_CMD_TRACE = 4,\n\tQETH_DIAGS_CMD_NOLOG = 8,\n\tQETH_DIAGS_CMD_DUMP = 16,\n};\n\nenum qeth_diags_trace_cmds {\n\tQETH_DIAGS_CMD_TRACE_ENABLE = 1,\n\tQETH_DIAGS_CMD_TRACE_DISABLE = 2,\n\tQETH_DIAGS_CMD_TRACE_MODIFY = 4,\n\tQETH_DIAGS_CMD_TRACE_REPLACE = 8,\n\tQETH_DIAGS_CMD_TRACE_QUERY = 16,\n};\n\nenum qeth_diags_trace_types {\n\tQETH_DIAGS_TYPE_HIPERSOCKET = 2,\n};\n\nenum qeth_diags_trap_action {\n\tQETH_DIAGS_TRAP_ARM = 1,\n\tQETH_DIAGS_TRAP_DISARM = 2,\n\tQETH_DIAGS_TRAP_CAPTURE = 4,\n};\n\nenum qeth_discipline_id {\n\tQETH_DISCIPLINE_UNDETERMINED = -1,\n\tQETH_DISCIPLINE_LAYER3 = 0,\n\tQETH_DISCIPLINE_LAYER2 = 1,\n};\n\nenum qeth_header_ids {\n\tQETH_HEADER_TYPE_LAYER3 = 1,\n\tQETH_HEADER_TYPE_LAYER2 = 2,\n\tQETH_HEADER_TYPE_L3_TSO = 3,\n\tQETH_HEADER_TYPE_L2_TSO = 6,\n\tQETH_HEADER_MASK_INVAL = 128,\n};\n\nenum qeth_ip_ass_cmds {\n\tIPA_CMD_ASS_START = 1,\n\tIPA_CMD_ASS_STOP = 2,\n\tIPA_CMD_ASS_CONFIGURE = 3,\n\tIPA_CMD_ASS_ENABLE = 4,\n};\n\nenum qeth_ip_types {\n\tQETH_IP_TYPE_NORMAL = 0,\n\tQETH_IP_TYPE_VIPA = 1,\n\tQETH_IP_TYPE_RXIP = 2,\n};\n\nenum qeth_ipa_addr_change_code {\n\tIPA_ADDR_CHANGE_CODE_VLANID = 1,\n\tIPA_ADDR_CHANGE_CODE_MACADDR = 2,\n\tIPA_ADDR_CHANGE_CODE_REMOVAL = 128,\n};\n\nenum qeth_ipa_arp_return_codes {\n\tQETH_IPA_ARP_RC_SUCCESS = 0,\n\tQETH_IPA_ARP_RC_FAILED = 1,\n\tQETH_IPA_ARP_RC_NOTSUPP = 2,\n\tQETH_IPA_ARP_RC_OUT_OF_RANGE = 3,\n\tQETH_IPA_ARP_RC_Q_NOTSUPP = 4,\n\tQETH_IPA_ARP_RC_Q_NO_DATA = 8,\n};\n\nenum qeth_ipa_checksum_bits {\n\tQETH_IPA_CHECKSUM_IP_HDR = 2,\n\tQETH_IPA_CHECKSUM_UDP = 8,\n\tQETH_IPA_CHECKSUM_TCP = 16,\n\tQETH_IPA_CHECKSUM_LP2LP = 32,\n};\n\nenum qeth_ipa_cmds {\n\tIPA_CMD_STARTLAN = 1,\n\tIPA_CMD_STOPLAN = 2,\n\tIPA_CMD_SETVMAC = 33,\n\tIPA_CMD_DELVMAC = 34,\n\tIPA_CMD_SETGMAC = 35,\n\tIPA_CMD_DELGMAC = 36,\n\tIPA_CMD_SETVLAN = 37,\n\tIPA_CMD_DELVLAN = 38,\n\tIPA_CMD_VNICC = 42,\n\tIPA_CMD_SETBRIDGEPORT_OSA = 43,\n\tIPA_CMD_SETIP = 177,\n\tIPA_CMD_QIPASSIST = 178,\n\tIPA_CMD_SETASSPARMS = 179,\n\tIPA_CMD_SETIPM = 180,\n\tIPA_CMD_DELIPM = 181,\n\tIPA_CMD_SETRTG = 182,\n\tIPA_CMD_DELIP = 183,\n\tIPA_CMD_SETADAPTERPARMS = 184,\n\tIPA_CMD_SET_DIAG_ASS = 185,\n\tIPA_CMD_SETBRIDGEPORT_IQD = 190,\n\tIPA_CMD_CREATE_ADDR = 195,\n\tIPA_CMD_DESTROY_ADDR = 196,\n\tIPA_CMD_REGISTER_LOCAL_ADDR = 209,\n\tIPA_CMD_UNREGISTER_LOCAL_ADDR = 210,\n\tIPA_CMD_ADDRESS_CHANGE_NOTIF = 211,\n\tIPA_CMD_UNKNOWN = 0,\n};\n\nenum qeth_ipa_funcs {\n\tIPA_ARP_PROCESSING = 1,\n\tIPA_INBOUND_CHECKSUM = 2,\n\tIPA_OUTBOUND_CHECKSUM = 4,\n\tIPA_FILTERING = 16,\n\tIPA_IPV6 = 32,\n\tIPA_MULTICASTING = 64,\n\tIPA_IP_REASSEMBLY = 128,\n\tIPA_QUERY_ARP_COUNTERS = 256,\n\tIPA_QUERY_ARP_ADDR_INFO = 512,\n\tIPA_SETADAPTERPARMS = 1024,\n\tIPA_VLAN_PRIO = 2048,\n\tIPA_PASSTHRU = 4096,\n\tIPA_FLUSH_ARP_SUPPORT = 8192,\n\tIPA_FULL_VLAN = 16384,\n\tIPA_INBOUND_PASSTHRU = 32768,\n\tIPA_SOURCE_MAC = 65536,\n\tIPA_OSA_MC_ROUTER = 131072,\n\tIPA_QUERY_ARP_ASSIST = 262144,\n\tIPA_INBOUND_TSO = 524288,\n\tIPA_OUTBOUND_TSO = 1048576,\n\tIPA_INBOUND_CHECKSUM_V6 = 4194304,\n\tIPA_OUTBOUND_CHECKSUM_V6 = 8388608,\n};\n\nenum qeth_ipa_isolation_modes {\n\tISOLATION_MODE_NONE = 0,\n\tISOLATION_MODE_FWD = 1,\n\tISOLATION_MODE_DROP = 2,\n};\n\nenum qeth_ipa_large_send_caps {\n\tQETH_IPA_LARGE_SEND_TCP = 1,\n};\n\nenum qeth_ipa_mac_ops {\n\tCHANGE_ADDR_READ_MAC = 0,\n\tCHANGE_ADDR_REPLACE_MAC = 1,\n\tCHANGE_ADDR_ADD_MAC = 2,\n\tCHANGE_ADDR_DEL_MAC = 4,\n\tCHANGE_ADDR_RESET_MAC = 8,\n};\n\nenum qeth_ipa_promisc_modes {\n\tSET_PROMISC_MODE_OFF = 0,\n\tSET_PROMISC_MODE_ON = 1,\n};\n\nenum qeth_ipa_return_codes {\n\tIPA_RC_SUCCESS = 0,\n\tIPA_RC_NOTSUPP = 1,\n\tIPA_RC_IP_TABLE_FULL = 2,\n\tIPA_RC_INVALID_SUBCMD = 2,\n\tIPA_RC_UNKNOWN_ERROR = 3,\n\tIPA_RC_HARDWARE_AUTH_ERROR = 3,\n\tIPA_RC_UNSUPPORTED_COMMAND = 4,\n\tIPA_RC_TRACE_ALREADY_ACTIVE = 5,\n\tIPA_RC_VNICC_OOSEQ = 5,\n\tIPA_RC_INVALID_FORMAT = 6,\n\tIPA_RC_DUP_IPV6_REMOTE = 8,\n\tIPA_RC_SBP_IQD_NOT_CONFIGURED = 12,\n\tIPA_RC_DUP_IPV6_HOME = 16,\n\tIPA_RC_SBP_IQD_OS_MISMATCH = 16,\n\tIPA_RC_UNREGISTERED_ADDR = 17,\n\tIPA_RC_NO_ID_AVAILABLE = 18,\n\tIPA_RC_ID_NOT_FOUND = 19,\n\tIPA_RC_SBP_IQD_ANO_DEV_PRIMARY = 20,\n\tIPA_RC_SBP_IQD_CURRENT_SECOND = 24,\n\tIPA_RC_SBP_IQD_LIMIT_SECOND = 28,\n\tIPA_RC_INVALID_IP_VERSION = 32,\n\tIPA_RC_SBP_IQD_NOT_AUTHD_BY_ZMAN = 32,\n\tIPA_RC_SBP_IQD_CURRENT_PRIMARY = 36,\n\tIPA_RC_LAN_FRAME_MISMATCH = 64,\n\tIPA_RC_SBP_IQD_NO_QDIO_QUEUES = 235,\n\tIPA_RC_L2_UNSUPPORTED_CMD = 8195,\n\tIPA_RC_L2_DUP_MAC = 8197,\n\tIPA_RC_L2_ADDR_TABLE_FULL = 8198,\n\tIPA_RC_L2_DUP_LAYER3_MAC = 8202,\n\tIPA_RC_L2_GMAC_NOT_FOUND = 8203,\n\tIPA_RC_L2_MAC_NOT_AUTH_BY_HYP = 8204,\n\tIPA_RC_L2_MAC_NOT_AUTH_BY_ADP = 8205,\n\tIPA_RC_L2_MAC_NOT_FOUND = 8208,\n\tIPA_RC_L2_INVALID_VLAN_ID = 8213,\n\tIPA_RC_L2_DUP_VLAN_ID = 8214,\n\tIPA_RC_L2_VLAN_ID_NOT_FOUND = 8215,\n\tIPA_RC_L2_VLAN_ID_NOT_ALLOWED = 8272,\n\tIPA_RC_VNICC_VNICBP = 8368,\n\tIPA_RC_SBP_OSA_NOT_CONFIGURED = 11020,\n\tIPA_RC_SBP_OSA_OS_MISMATCH = 11024,\n\tIPA_RC_SBP_OSA_ANO_DEV_PRIMARY = 11028,\n\tIPA_RC_SBP_OSA_CURRENT_SECOND = 11032,\n\tIPA_RC_SBP_OSA_LIMIT_SECOND = 11036,\n\tIPA_RC_SBP_OSA_NOT_AUTHD_BY_ZMAN = 11040,\n\tIPA_RC_SBP_OSA_CURRENT_PRIMARY = 11044,\n\tIPA_RC_SBP_OSA_NO_QDIO_QUEUES = 11243,\n\tIPA_RC_DATA_MISMATCH = 57345,\n\tIPA_RC_INVALID_MTU_SIZE = 57346,\n\tIPA_RC_INVALID_LANTYPE = 57347,\n\tIPA_RC_INVALID_LANNUM = 57348,\n\tIPA_RC_DUPLICATE_IP_ADDRESS = 57349,\n\tIPA_RC_IP_ADDR_TABLE_FULL = 57350,\n\tIPA_RC_LAN_PORT_STATE_ERROR = 57351,\n\tIPA_RC_SETIP_NO_STARTLAN = 57352,\n\tIPA_RC_SETIP_ALREADY_RECEIVED = 57353,\n\tIPA_RC_IP_ADDR_ALREADY_USED = 57354,\n\tIPA_RC_MC_ADDR_NOT_FOUND = 57355,\n\tIPA_RC_SETIP_INVALID_VERSION = 57357,\n\tIPA_RC_UNSUPPORTED_SUBCMD = 57358,\n\tIPA_RC_ARP_ASSIST_NO_ENABLE = 57359,\n\tIPA_RC_PRIMARY_ALREADY_DEFINED = 57360,\n\tIPA_RC_SECOND_ALREADY_DEFINED = 57361,\n\tIPA_RC_INVALID_SETRTG_INDICATOR = 57362,\n\tIPA_RC_MC_ADDR_ALREADY_DEFINED = 57363,\n\tIPA_RC_LAN_OFFLINE = 57472,\n\tIPA_RC_VEPA_TO_VEB_TRANSITION = 57488,\n\tIPA_RC_INVALID_IP_VERSION2 = 61441,\n\tIPA_RC_FFFF = 65535,\n};\n\nenum qeth_ipa_sbp_cmd {\n\tIPA_SBP_QUERY_COMMANDS_SUPPORTED = 0,\n\tIPA_SBP_RESET_BRIDGE_PORT_ROLE = 1,\n\tIPA_SBP_SET_PRIMARY_BRIDGE_PORT = 2,\n\tIPA_SBP_SET_SECONDARY_BRIDGE_PORT = 4,\n\tIPA_SBP_QUERY_BRIDGE_PORTS = 8,\n\tIPA_SBP_BRIDGE_PORT_STATE_CHANGE = 16,\n};\n\nenum qeth_ipa_set_access_mode_rc {\n\tSET_ACCESS_CTRL_RC_SUCCESS = 0,\n\tSET_ACCESS_CTRL_RC_NOT_SUPPORTED = 4,\n\tSET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED = 8,\n\tSET_ACCESS_CTRL_RC_ALREADY_ISOLATED = 16,\n\tSET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER = 20,\n\tSET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF = 24,\n\tSET_ACCESS_CTRL_RC_REFLREL_UNSUPPORTED = 34,\n\tSET_ACCESS_CTRL_RC_REFLREL_FAILED = 36,\n\tSET_ACCESS_CTRL_RC_REFLREL_DEACT_FAILED = 40,\n};\n\nenum qeth_ipa_setadp_cmd {\n\tIPA_SETADP_QUERY_COMMANDS_SUPPORTED = 1,\n\tIPA_SETADP_ALTER_MAC_ADDRESS = 2,\n\tIPA_SETADP_ADD_DELETE_GROUP_ADDRESS = 4,\n\tIPA_SETADP_ADD_DELETE_FUNCTIONAL_ADDR = 8,\n\tIPA_SETADP_SET_ADDRESSING_MODE = 16,\n\tIPA_SETADP_SET_CONFIG_PARMS = 32,\n\tIPA_SETADP_SET_CONFIG_PARMS_EXTENDED = 64,\n\tIPA_SETADP_SET_BROADCAST_MODE = 128,\n\tIPA_SETADP_SEND_OSA_MESSAGE = 256,\n\tIPA_SETADP_SET_SNMP_CONTROL = 512,\n\tIPA_SETADP_QUERY_CARD_INFO = 1024,\n\tIPA_SETADP_SET_PROMISC_MODE = 2048,\n\tIPA_SETADP_SET_DIAG_ASSIST = 8192,\n\tIPA_SETADP_SET_ACCESS_CONTROL = 65536,\n\tIPA_SETADP_QUERY_OAT = 524288,\n\tIPA_SETADP_QUERY_SWITCH_ATTRIBUTES = 1048576,\n};\n\nenum qeth_ipa_setdelip_flags {\n\tQETH_IPA_SETDELIP_DEFAULT = 0,\n\tQETH_IPA_SETIP_VIPA_FLAG = 1,\n\tQETH_IPA_SETIP_TAKEOVER_FLAG = 2,\n\tQETH_IPA_DELIP_ADDR_2_B_TAKEN_OVER = 32,\n\tQETH_IPA_DELIP_VIPA_FLAG = 64,\n\tQETH_IPA_DELIP_ADDR_NEEDS_SETIP = 128,\n};\n\nenum qeth_layer2_frame_flags {\n\tQETH_LAYER2_FLAG_MULTICAST = 1,\n\tQETH_LAYER2_FLAG_BROADCAST = 2,\n\tQETH_LAYER2_FLAG_UNICAST = 4,\n\tQETH_LAYER2_FLAG_VLAN = 16,\n};\n\nenum qeth_link_mode {\n\tQETH_LINK_MODE_UNKNOWN = 0,\n\tQETH_LINK_MODE_FIBRE_SHORT = 1,\n\tQETH_LINK_MODE_FIBRE_LONG = 2,\n};\n\nenum qeth_link_types {\n\tQETH_LINK_TYPE_FAST_ETH = 1,\n\tQETH_LINK_TYPE_HSTR = 2,\n\tQETH_LINK_TYPE_GBIT_ETH = 3,\n\tQETH_LINK_TYPE_10GBIT_ETH = 16,\n\tQETH_LINK_TYPE_25GBIT_ETH = 18,\n\tQETH_LINK_TYPE_LANE_ETH100 = 129,\n\tQETH_LINK_TYPE_LANE_TR = 130,\n\tQETH_LINK_TYPE_LANE_ETH1000 = 131,\n\tQETH_LINK_TYPE_LANE = 136,\n};\n\nenum qeth_pnso_mode {\n\tQETH_PNSO_NONE = 0,\n\tQETH_PNSO_BRIDGEPORT = 1,\n\tQETH_PNSO_ADDR_INFO = 2,\n};\n\nenum qeth_prot_versions {\n\tQETH_PROT_NONE = 0,\n\tQETH_PROT_IPV4 = 4,\n\tQETH_PROT_IPV6 = 6,\n};\n\nenum qeth_qaob_state {\n\tQETH_QAOB_ISSUED = 0,\n\tQETH_QAOB_PENDING = 1,\n\tQETH_QAOB_DONE = 2,\n};\n\nenum qeth_qdio_info_states {\n\tQETH_QDIO_UNINITIALIZED = 0,\n\tQETH_QDIO_ALLOCATED = 1,\n\tQETH_QDIO_ESTABLISHED = 2,\n\tQETH_QDIO_CLEANING = 3,\n};\n\nenum qeth_qdio_out_buffer_state {\n\tQETH_QDIO_BUF_EMPTY = 0,\n\tQETH_QDIO_BUF_PRIMED = 1,\n};\n\nenum qeth_routing_types {\n\tNO_ROUTER = 0,\n\tPRIMARY_ROUTER = 1,\n\tSECONDARY_ROUTER = 2,\n\tMULTICAST_ROUTER = 3,\n\tPRIMARY_CONNECTOR = 4,\n\tSECONDARY_CONNECTOR = 5,\n};\n\nenum qeth_sbp_roles {\n\tQETH_SBP_ROLE_NONE = 0,\n\tQETH_SBP_ROLE_PRIMARY = 1,\n\tQETH_SBP_ROLE_SECONDARY = 2,\n};\n\nenum qeth_sbp_states {\n\tQETH_SBP_STATE_INACTIVE = 0,\n\tQETH_SBP_STATE_STANDBY = 1,\n\tQETH_SBP_STATE_ACTIVE = 2,\n};\n\nenum qeth_threads {\n\tQETH_RECOVER_THREAD = 1,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum ramfs_param {\n\tOpt_mode___6 = 0,\n};\n\nenum raw3215_type {\n\tRAW3215_FREE = 0,\n\tRAW3215_READ = 1,\n\tRAW3215_WRITE = 2,\n};\n\nenum rdma_ah_attr_type {\n\tRDMA_AH_ATTR_TYPE_UNDEFINED = 0,\n\tRDMA_AH_ATTR_TYPE_IB = 1,\n\tRDMA_AH_ATTR_TYPE_ROCE = 2,\n\tRDMA_AH_ATTR_TYPE_OPA = 3,\n};\n\nenum rdma_driver_id {\n\tRDMA_DRIVER_UNKNOWN = 0,\n\tRDMA_DRIVER_MLX5 = 1,\n\tRDMA_DRIVER_MLX4 = 2,\n\tRDMA_DRIVER_CXGB3 = 3,\n\tRDMA_DRIVER_CXGB4 = 4,\n\tRDMA_DRIVER_MTHCA = 5,\n\tRDMA_DRIVER_BNXT_RE = 6,\n\tRDMA_DRIVER_OCRDMA = 7,\n\tRDMA_DRIVER_NES = 8,\n\tRDMA_DRIVER_I40IW = 9,\n\tRDMA_DRIVER_IRDMA = 9,\n\tRDMA_DRIVER_VMW_PVRDMA = 10,\n\tRDMA_DRIVER_QEDR = 11,\n\tRDMA_DRIVER_HNS = 12,\n\tRDMA_DRIVER_USNIC = 13,\n\tRDMA_DRIVER_RXE = 14,\n\tRDMA_DRIVER_HFI1 = 15,\n\tRDMA_DRIVER_QIB = 16,\n\tRDMA_DRIVER_EFA = 17,\n\tRDMA_DRIVER_SIW = 18,\n\tRDMA_DRIVER_ERDMA = 19,\n\tRDMA_DRIVER_MANA = 20,\n\tRDMA_DRIVER_IONIC = 21,\n};\n\nenum rdma_link_layer {\n\tIB_LINK_LAYER_UNSPECIFIED = 0,\n\tIB_LINK_LAYER_INFINIBAND = 1,\n\tIB_LINK_LAYER_ETHERNET = 2,\n};\n\nenum rdma_netdev_t {\n\tRDMA_NETDEV_OPA_VNIC = 0,\n\tRDMA_NETDEV_IPOIB = 1,\n};\n\nenum rdma_nl_counter_mask {\n\tRDMA_COUNTER_MASK_QP_TYPE = 1,\n\tRDMA_COUNTER_MASK_PID = 2,\n};\n\nenum rdma_nl_counter_mode {\n\tRDMA_COUNTER_MODE_NONE = 0,\n\tRDMA_COUNTER_MODE_AUTO = 1,\n\tRDMA_COUNTER_MODE_MANUAL = 2,\n\tRDMA_COUNTER_MODE_MAX = 3,\n};\n\nenum rdma_nl_dev_type {\n\tRDMA_DEVICE_TYPE_SMI = 1,\n};\n\nenum rdma_nl_name_assign_type {\n\tRDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0,\n\tRDMA_NAME_ASSIGN_TYPE_USER = 1,\n};\n\nenum rdma_restrack_type {\n\tRDMA_RESTRACK_PD = 0,\n\tRDMA_RESTRACK_CQ = 1,\n\tRDMA_RESTRACK_QP = 2,\n\tRDMA_RESTRACK_CM_ID = 3,\n\tRDMA_RESTRACK_MR = 4,\n\tRDMA_RESTRACK_CTX = 5,\n\tRDMA_RESTRACK_COUNTER = 6,\n\tRDMA_RESTRACK_SRQ = 7,\n\tRDMA_RESTRACK_DMAH = 8,\n\tRDMA_RESTRACK_MAX = 9,\n};\n\nenum rdmacg_file_type {\n\tRDMACG_RESOURCE_TYPE_MAX = 0,\n\tRDMACG_RESOURCE_TYPE_STAT = 1,\n};\n\nenum rdmacg_resource_type {\n\tRDMACG_RESOURCE_HCA_HANDLE = 0,\n\tRDMACG_RESOURCE_HCA_OBJECT = 1,\n\tRDMACG_RESOURCE_MAX = 2,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum recovery_flags {\n\tMD_RECOVERY_NEEDED = 0,\n\tMD_RECOVERY_RUNNING = 1,\n\tMD_RECOVERY_INTR = 2,\n\tMD_RECOVERY_DONE = 3,\n\tMD_RECOVERY_FROZEN = 4,\n\tMD_RECOVERY_WAIT = 5,\n\tMD_RECOVERY_SYNC = 6,\n\tMD_RECOVERY_REQUESTED = 7,\n\tMD_RECOVERY_CHECK = 8,\n\tMD_RECOVERY_RECOVER = 9,\n\tMD_RECOVERY_RESHAPE = 10,\n\tMD_RESYNCING_REMOTE = 11,\n\tMD_RECOVERY_LAZY_RECOVER = 12,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum reloc_stage {\n\tMOVE_DATA_EXTENTS = 0,\n\tUPDATE_DATA_PTRS = 1,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reserved_range_type {\n\tRR_DECOMPRESSOR = 0,\n\tRR_INITRD = 1,\n\tRR_VMLINUX = 2,\n\tRR_AMODE31 = 3,\n\tRR_IPLREPORT = 4,\n\tRR_CERT_COMP_LIST = 5,\n\tRR_MEM_DETECT_EXT = 6,\n\tRR_VMEM = 7,\n\tRR_MAX = 8,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum retcode {\n\tDIAG324_RET_SUCCESS = 1,\n\tDIAG324_RET_SUBC_NOTAVAIL = 259,\n\tDIAG324_RET_INSUFFICIENT_SIZE = 260,\n\tDIAG324_RET_READING_UNAVAILABLE = 261,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rsaprivkey_actions {\n\tACT_rsa_get_d = 0,\n\tACT_rsa_get_dp = 1,\n\tACT_rsa_get_dq = 2,\n\tACT_rsa_get_e = 3,\n\tACT_rsa_get_n = 4,\n\tACT_rsa_get_p = 5,\n\tACT_rsa_get_q = 6,\n\tACT_rsa_get_qinv = 7,\n\tNR__rsaprivkey_actions = 8,\n};\n\nenum rsapubkey_actions {\n\tACT_rsa_get_e___2 = 0,\n\tACT_rsa_get_n___2 = 1,\n\tNR__rsapubkey_actions = 2,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rt6_nud_state {\n\tRT6_NUD_FAIL_HARD = -3,\n\tRT6_NUD_FAIL_PROBE = -2,\n\tRT6_NUD_FAIL_DO_RR = -1,\n\tRT6_NUD_SUCCEED = 1,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum scan_result {\n\tSCAN_FAIL = 0,\n\tSCAN_SUCCEED = 1,\n\tSCAN_NO_PTE_TABLE = 2,\n\tSCAN_PMD_MAPPED = 3,\n\tSCAN_EXCEED_NONE_PTE = 4,\n\tSCAN_EXCEED_SWAP_PTE = 5,\n\tSCAN_EXCEED_SHARED_PTE = 6,\n\tSCAN_PTE_NON_PRESENT = 7,\n\tSCAN_PTE_UFFD_WP = 8,\n\tSCAN_PTE_MAPPED_HUGEPAGE = 9,\n\tSCAN_LACK_REFERENCED_PAGE = 10,\n\tSCAN_PAGE_NULL = 11,\n\tSCAN_SCAN_ABORT = 12,\n\tSCAN_PAGE_COUNT = 13,\n\tSCAN_PAGE_LRU = 14,\n\tSCAN_PAGE_LOCK = 15,\n\tSCAN_PAGE_ANON = 16,\n\tSCAN_PAGE_COMPOUND = 17,\n\tSCAN_ANY_PROCESS = 18,\n\tSCAN_VMA_NULL = 19,\n\tSCAN_VMA_CHECK = 20,\n\tSCAN_ADDRESS_RANGE = 21,\n\tSCAN_DEL_PAGE_LRU = 22,\n\tSCAN_ALLOC_HUGE_PAGE_FAIL = 23,\n\tSCAN_CGROUP_CHARGE_FAIL = 24,\n\tSCAN_TRUNCATED = 25,\n\tSCAN_PAGE_HAS_PRIVATE = 26,\n\tSCAN_STORE_FAILED = 27,\n\tSCAN_COPY_MC = 28,\n\tSCAN_PAGE_FILLED = 29,\n\tSCAN_PAGE_DIRTY_OR_WRITEBACK = 30,\n};\n\nenum sch_todo {\n\tSCH_TODO_NOTHING = 0,\n\tSCH_TODO_EVAL = 1,\n\tSCH_TODO_UNREG = 2,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum sclp_activation_state_t {\n\tsclp_activation_state_active = 0,\n\tsclp_activation_state_deactivating = 1,\n\tsclp_activation_state_inactive = 2,\n\tsclp_activation_state_activating = 3,\n};\n\nenum sclp_mask_state_t {\n\tsclp_mask_state_idle = 0,\n\tsclp_mask_state_initializing = 1,\n};\n\nenum sclp_reading_state_t {\n\tsclp_reading_state_idle = 0,\n\tsclp_reading_state_reading = 1,\n};\n\nenum sclp_running_state_t {\n\tsclp_running_state_idle = 0,\n\tsclp_running_state_running = 1,\n\tsclp_running_state_reset_pending = 2,\n};\n\nenum scm_event {\n\tSCM_CHANGE = 0,\n\tSCM_AVAIL = 1,\n};\n\nenum scrub_stripe_flags {\n\tSCRUB_STRIPE_FLAG_INITIALIZED = 0,\n\tSCRUB_STRIPE_FLAG_REPAIR_DONE = 1,\n\tSCRUB_STRIPE_FLAG_NO_REPORT = 2,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_guard_type {\n\tSHOST_DIX_GUARD_CRC = 1,\n\tSHOST_DIX_GUARD_IP = 2,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 10000,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_cid {\n\tSCTP_CID_DATA = 0,\n\tSCTP_CID_INIT = 1,\n\tSCTP_CID_INIT_ACK = 2,\n\tSCTP_CID_SACK = 3,\n\tSCTP_CID_HEARTBEAT = 4,\n\tSCTP_CID_HEARTBEAT_ACK = 5,\n\tSCTP_CID_ABORT = 6,\n\tSCTP_CID_SHUTDOWN = 7,\n\tSCTP_CID_SHUTDOWN_ACK = 8,\n\tSCTP_CID_ERROR = 9,\n\tSCTP_CID_COOKIE_ECHO = 10,\n\tSCTP_CID_COOKIE_ACK = 11,\n\tSCTP_CID_ECN_ECNE = 12,\n\tSCTP_CID_ECN_CWR = 13,\n\tSCTP_CID_SHUTDOWN_COMPLETE = 14,\n\tSCTP_CID_AUTH = 15,\n\tSCTP_CID_I_DATA = 64,\n\tSCTP_CID_FWD_TSN = 192,\n\tSCTP_CID_ASCONF = 193,\n\tSCTP_CID_I_FWD_TSN = 194,\n\tSCTP_CID_ASCONF_ACK = 128,\n\tSCTP_CID_RECONF = 130,\n\tSCTP_CID_PAD = 132,\n};\n\nenum sctp_conntrack {\n\tSCTP_CONNTRACK_NONE = 0,\n\tSCTP_CONNTRACK_CLOSED = 1,\n\tSCTP_CONNTRACK_COOKIE_WAIT = 2,\n\tSCTP_CONNTRACK_COOKIE_ECHOED = 3,\n\tSCTP_CONNTRACK_ESTABLISHED = 4,\n\tSCTP_CONNTRACK_SHUTDOWN_SENT = 5,\n\tSCTP_CONNTRACK_SHUTDOWN_RECD = 6,\n\tSCTP_CONNTRACK_SHUTDOWN_ACK_SENT = 7,\n\tSCTP_CONNTRACK_HEARTBEAT_SENT = 8,\n\tSCTP_CONNTRACK_HEARTBEAT_ACKED = 9,\n\tSCTP_CONNTRACK_MAX = 10,\n};\n\nenum sctp_endpoint_type {\n\tSCTP_EP_TYPE_SOCKET = 0,\n\tSCTP_EP_TYPE_ASSOCIATION = 1,\n};\n\nenum sctp_event_timeout {\n\tSCTP_EVENT_TIMEOUT_NONE = 0,\n\tSCTP_EVENT_TIMEOUT_T1_COOKIE = 1,\n\tSCTP_EVENT_TIMEOUT_T1_INIT = 2,\n\tSCTP_EVENT_TIMEOUT_T2_SHUTDOWN = 3,\n\tSCTP_EVENT_TIMEOUT_T3_RTX = 4,\n\tSCTP_EVENT_TIMEOUT_T4_RTO = 5,\n\tSCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD = 6,\n\tSCTP_EVENT_TIMEOUT_HEARTBEAT = 7,\n\tSCTP_EVENT_TIMEOUT_RECONF = 8,\n\tSCTP_EVENT_TIMEOUT_PROBE = 9,\n\tSCTP_EVENT_TIMEOUT_SACK = 10,\n\tSCTP_EVENT_TIMEOUT_AUTOCLOSE = 11,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum sctp_param {\n\tSCTP_PARAM_HEARTBEAT_INFO = 1,\n\tSCTP_PARAM_IPV4_ADDRESS = 5,\n\tSCTP_PARAM_IPV6_ADDRESS = 6,\n\tSCTP_PARAM_STATE_COOKIE = 7,\n\tSCTP_PARAM_UNRECOGNIZED_PARAMETERS = 8,\n\tSCTP_PARAM_COOKIE_PRESERVATIVE = 9,\n\tSCTP_PARAM_HOST_NAME_ADDRESS = 11,\n\tSCTP_PARAM_SUPPORTED_ADDRESS_TYPES = 12,\n\tSCTP_PARAM_ECN_CAPABLE = 32768,\n\tSCTP_PARAM_RANDOM = 32770,\n\tSCTP_PARAM_CHUNKS = 32771,\n\tSCTP_PARAM_HMAC_ALGO = 32772,\n\tSCTP_PARAM_SUPPORTED_EXT = 32776,\n\tSCTP_PARAM_FWD_TSN_SUPPORT = 49152,\n\tSCTP_PARAM_ADD_IP = 49153,\n\tSCTP_PARAM_DEL_IP = 49154,\n\tSCTP_PARAM_ERR_CAUSE = 49155,\n\tSCTP_PARAM_SET_PRIMARY = 49156,\n\tSCTP_PARAM_SUCCESS_REPORT = 49157,\n\tSCTP_PARAM_ADAPTATION_LAYER_IND = 49158,\n\tSCTP_PARAM_RESET_OUT_REQUEST = 13,\n\tSCTP_PARAM_RESET_IN_REQUEST = 14,\n\tSCTP_PARAM_RESET_TSN_REQUEST = 15,\n\tSCTP_PARAM_RESET_RESPONSE = 16,\n\tSCTP_PARAM_RESET_ADD_OUT_STREAMS = 17,\n\tSCTP_PARAM_RESET_ADD_IN_STREAMS = 18,\n};\n\nenum sctp_scope {\n\tSCTP_SCOPE_GLOBAL = 0,\n\tSCTP_SCOPE_PRIVATE = 1,\n\tSCTP_SCOPE_LINK = 2,\n\tSCTP_SCOPE_LOOPBACK = 3,\n\tSCTP_SCOPE_UNUSABLE = 4,\n};\n\nenum sctp_socket_type {\n\tSCTP_SOCKET_UDP = 0,\n\tSCTP_SOCKET_UDP_HIGH_BANDWIDTH = 1,\n\tSCTP_SOCKET_TCP = 2,\n};\n\nenum sctp_state {\n\tSCTP_STATE_CLOSED = 0,\n\tSCTP_STATE_COOKIE_WAIT = 1,\n\tSCTP_STATE_COOKIE_ECHOED = 2,\n\tSCTP_STATE_ESTABLISHED = 3,\n\tSCTP_STATE_SHUTDOWN_PENDING = 4,\n\tSCTP_STATE_SHUTDOWN_SENT = 5,\n\tSCTP_STATE_SHUTDOWN_RECEIVED = 6,\n\tSCTP_STATE_SHUTDOWN_ACK_SENT = 7,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 30000,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_HAS_CGROUP_WEIGHT = 65536ULL,\n\tSCX_OPS_ALL_FLAGS = 65663ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1,\n\t__SCX_REENQ_FILTER_MASK = 65535,\n\t__SCX_REENQ_USER_MASK = 1,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum sel_inos {\n\tSEL_ROOT_INO = 2,\n\tSEL_LOAD = 3,\n\tSEL_ENFORCE = 4,\n\tSEL_CONTEXT = 5,\n\tSEL_ACCESS = 6,\n\tSEL_CREATE = 7,\n\tSEL_RELABEL = 8,\n\tSEL_USER = 9,\n\tSEL_POLICYVERS = 10,\n\tSEL_COMMIT_BOOLS = 11,\n\tSEL_MLS = 12,\n\tSEL_DISABLE = 13,\n\tSEL_MEMBER = 14,\n\tSEL_CHECKREQPROT = 15,\n\tSEL_COMPAT_NET = 16,\n\tSEL_REJECT_UNKNOWN = 17,\n\tSEL_DENY_UNKNOWN = 18,\n\tSEL_STATUS = 19,\n\tSEL_POLICY = 20,\n\tSEL_VALIDATE_TRANS = 21,\n\tSEL_INO_NEXT = 22,\n};\n\nenum selinux_nlgroups {\n\tSELNLGRP_NONE = 0,\n\tSELNLGRP_AVC = 1,\n\t__SELNLGRP_MAX = 2,\n};\n\nenum set_event_iter_type {\n\tSET_EVENT_FILE = 0,\n\tSET_EVENT_MOD = 1,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum shmem_param {\n\tOpt_gid___8 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___7 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes___2 = 5,\n\tOpt_size___2 = 6,\n\tOpt_uid___7 = 7,\n\tOpt_inode32___2 = 8,\n\tOpt_inode64___2 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota___3 = 11,\n\tOpt_usrquota___3 = 12,\n\tOpt_grpquota___3 = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_ext_id {\n\tSKB_EXT_BRIDGE_NF = 0,\n\tSKB_EXT_SEC_PATH = 1,\n\tTC_SKB_EXT = 2,\n\tSKB_EXT_MPTCP = 3,\n\tSKB_EXT_NUM = 4,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN = 0,\n\tPARTIAL = 1,\n\tUP = 2,\n\tFULL = 3,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum split_type {\n\tSPLIT_TYPE_UNIFORM = 0,\n\tSPLIT_TYPE_NON_UNIFORM = 1,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum stack_type {\n\tSTACK_TYPE_UNKNOWN = 0,\n\tSTACK_TYPE_TASK = 1,\n\tSTACK_TYPE_IRQ = 2,\n\tSTACK_TYPE_NODAT = 3,\n\tSTACK_TYPE_RESTART = 4,\n\tSTACK_TYPE_MCCK = 5,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum stcctm_ctr_set {\n\tEXTENDED = 0,\n\tBASIC = 1,\n\tPROBLEM_STATE = 2,\n\tCRYPTO_ACTIVITY = 3,\n\tMT_DIAG = 5,\n\tMT_DIAG_CLEARING = 9,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum subcode {\n\tDIAG324_SUBC_0 = 0,\n\tDIAG324_SUBC_1 = 1,\n\tDIAG324_SUBC_2 = 2,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum suspend_mode {\n\tPRESUSPEND = 0,\n\tPRESUSPEND_UNDO = 1,\n\tPOSTSUSPEND = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum switchdev_attr_id {\n\tSWITCHDEV_ATTR_ID_UNDEFINED = 0,\n\tSWITCHDEV_ATTR_ID_PORT_STP_STATE = 1,\n\tSWITCHDEV_ATTR_ID_PORT_MST_STATE = 2,\n\tSWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS = 3,\n\tSWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS = 4,\n\tSWITCHDEV_ATTR_ID_PORT_MROUTER = 5,\n\tSWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME = 6,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING = 7,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_PROTOCOL = 8,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED = 9,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MROUTER = 10,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MST = 11,\n\tSWITCHDEV_ATTR_ID_MRP_PORT_ROLE = 12,\n\tSWITCHDEV_ATTR_ID_VLAN_MSTI = 13,\n};\n\nenum switchdev_notifier_type {\n\tSWITCHDEV_FDB_ADD_TO_BRIDGE = 1,\n\tSWITCHDEV_FDB_DEL_TO_BRIDGE = 2,\n\tSWITCHDEV_FDB_ADD_TO_DEVICE = 3,\n\tSWITCHDEV_FDB_DEL_TO_DEVICE = 4,\n\tSWITCHDEV_FDB_OFFLOADED = 5,\n\tSWITCHDEV_FDB_FLUSH_TO_BRIDGE = 6,\n\tSWITCHDEV_PORT_OBJ_ADD = 7,\n\tSWITCHDEV_PORT_OBJ_DEL = 8,\n\tSWITCHDEV_PORT_ATTR_SET = 9,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_BRIDGE = 10,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_BRIDGE = 11,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_DEVICE = 12,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_DEVICE = 13,\n\tSWITCHDEV_VXLAN_FDB_OFFLOADED = 14,\n\tSWITCHDEV_BRPORT_OFFLOADED = 15,\n\tSWITCHDEV_BRPORT_UNOFFLOADED = 16,\n\tSWITCHDEV_BRPORT_REPLAY = 17,\n};\n\nenum switchdev_obj_id {\n\tSWITCHDEV_OBJ_ID_UNDEFINED = 0,\n\tSWITCHDEV_OBJ_ID_PORT_VLAN = 1,\n\tSWITCHDEV_OBJ_ID_PORT_MDB = 2,\n\tSWITCHDEV_OBJ_ID_HOST_MDB = 3,\n\tSWITCHDEV_OBJ_ID_MRP = 4,\n\tSWITCHDEV_OBJ_ID_RING_TEST_MRP = 5,\n\tSWITCHDEV_OBJ_ID_RING_ROLE_MRP = 6,\n\tSWITCHDEV_OBJ_ID_RING_STATE_MRP = 7,\n\tSWITCHDEV_OBJ_ID_IN_TEST_MRP = 8,\n\tSWITCHDEV_OBJ_ID_IN_ROLE_MRP = 9,\n\tSWITCHDEV_OBJ_ID_IN_STATE_MRP = 10,\n};\n\nenum sync_action {\n\tACTION_RESYNC = 0,\n\tACTION_RECOVER = 1,\n\tACTION_CHECK = 2,\n\tACTION_REPAIR = 3,\n\tACTION_RESHAPE = 4,\n\tACTION_FROZEN = 5,\n\tACTION_IDLE = 6,\n\tNR_SYNC_ACTIONS = 7,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum syscall_work_bit {\n\tSYSCALL_WORK_BIT_SECCOMP = 0,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACEPOINT = 1,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACE = 2,\n\tSYSCALL_WORK_BIT_SYSCALL_EMU = 3,\n\tSYSCALL_WORK_BIT_SYSCALL_AUDIT = 4,\n\tSYSCALL_WORK_BIT_SYSCALL_USER_DISPATCH = 5,\n\tSYSCALL_WORK_BIT_SYSCALL_EXIT_TRAP = 6,\n\tSYSCALL_WORK_BIT_SYSCALL_RSEQ_SLICE = 7,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_fifo_command {\n\tTC_FIFO_REPLACE = 0,\n\tTC_FIFO_DESTROY = 1,\n\tTC_FIFO_STATS = 2,\n};\n\nenum tc_link_layer {\n\tTC_LINKLAYER_UNAWARE = 0,\n\tTC_LINKLAYER_ETHERNET = 1,\n\tTC_LINKLAYER_ATM = 2,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_root_command {\n\tTC_ROOT_GRAFT = 0,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcf_proto_ops_flags {\n\tTCF_PROTO_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_conntrack {\n\tTCP_CONNTRACK_NONE = 0,\n\tTCP_CONNTRACK_SYN_SENT = 1,\n\tTCP_CONNTRACK_SYN_RECV = 2,\n\tTCP_CONNTRACK_ESTABLISHED = 3,\n\tTCP_CONNTRACK_FIN_WAIT = 4,\n\tTCP_CONNTRACK_CLOSE_WAIT = 5,\n\tTCP_CONNTRACK_LAST_ACK = 6,\n\tTCP_CONNTRACK_TIME_WAIT = 7,\n\tTCP_CONNTRACK_CLOSE = 8,\n\tTCP_CONNTRACK_LISTEN = 9,\n\tTCP_CONNTRACK_MAX = 10,\n\tTCP_CONNTRACK_IGNORE = 11,\n\tTCP_CONNTRACK_RETRANS = 12,\n\tTCP_CONNTRACK_UNACK = 13,\n\tTCP_CONNTRACK_TIMEOUT_MAX = 14,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED___2 = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nenum tcpa_pc_event_ids {\n\tSMBIOS = 1,\n\tBIS_CERT = 2,\n\tPOST_BIOS_ROM = 3,\n\tESCD = 4,\n\tCMOS = 5,\n\tNVRAM = 6,\n\tOPTION_ROM_EXEC = 7,\n\tOPTION_ROM_CONFIG = 8,\n\tOPTION_ROM_MICROCODE = 10,\n\tS_CRTM_VERSION = 11,\n\tS_CRTM_CONTENTS = 12,\n\tPOST_CONTENTS = 13,\n\tHOST_TABLE_OF_DEVICES = 14,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum tg_state_flags {\n\tTHROTL_TG_PENDING = 1,\n\tTHROTL_TG_WAS_EMPTY = 2,\n\tTHROTL_TG_IOPS_WAS_EMPTY = 4,\n\tTHROTL_TG_CANCELING = 8,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPER_AUX_FIRST = 1,\n\tTIMEKEEPER_AUX_LAST = 8,\n\tTIMEKEEPERS_MAX = 9,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum tls_offload_ctx_dir {\n\tTLS_OFFLOAD_CTX_DIR_RX = 0,\n\tTLS_OFFLOAD_CTX_DIR_TX = 1,\n};\n\nenum tp_func_state {\n\tTP_FUNC_0 = 0,\n\tTP_FUNC_1 = 1,\n\tTP_FUNC_2 = 2,\n\tTP_FUNC_N = 3,\n};\n\nenum tp_transition_sync {\n\tTP_TRANSITION_SYNC_1_0_1 = 0,\n\tTP_TRANSITION_SYNC_N_2_1 = 1,\n\t_NR_TP_TRANSITION_SYNC = 2,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tph_mem_type {\n\tTPH_MEM_TYPE_VM = 0,\n\tTPH_MEM_TYPE_PM = 1,\n};\n\nenum tpm2_capabilities {\n\tTPM2_CAP_HANDLES = 1,\n\tTPM2_CAP_COMMANDS = 2,\n\tTPM2_CAP_PCRS = 5,\n\tTPM2_CAP_TPM_PROPERTIES = 6,\n};\n\nenum tpm2_cc_attrs {\n\tTPM2_CC_ATTR_CHANDLES = 25,\n\tTPM2_CC_ATTR_RHANDLE = 28,\n\tTPM2_CC_ATTR_VENDOR = 29,\n};\n\nenum tpm2_command_codes {\n\tTPM2_CC_FIRST = 287,\n\tTPM2_CC_HIERARCHY_CONTROL = 289,\n\tTPM2_CC_HIERARCHY_CHANGE_AUTH = 297,\n\tTPM2_CC_CREATE_PRIMARY = 305,\n\tTPM2_CC_SEQUENCE_COMPLETE = 318,\n\tTPM2_CC_SELF_TEST = 323,\n\tTPM2_CC_STARTUP = 324,\n\tTPM2_CC_SHUTDOWN = 325,\n\tTPM2_CC_NV_READ = 334,\n\tTPM2_CC_CREATE = 339,\n\tTPM2_CC_LOAD = 343,\n\tTPM2_CC_SEQUENCE_UPDATE = 348,\n\tTPM2_CC_UNSEAL = 350,\n\tTPM2_CC_CONTEXT_LOAD = 353,\n\tTPM2_CC_CONTEXT_SAVE = 354,\n\tTPM2_CC_FLUSH_CONTEXT = 357,\n\tTPM2_CC_READ_PUBLIC = 371,\n\tTPM2_CC_START_AUTH_SESS = 374,\n\tTPM2_CC_VERIFY_SIGNATURE = 375,\n\tTPM2_CC_GET_CAPABILITY = 378,\n\tTPM2_CC_GET_RANDOM = 379,\n\tTPM2_CC_PCR_READ = 382,\n\tTPM2_CC_PCR_EXTEND = 386,\n\tTPM2_CC_EVENT_SEQUENCE_COMPLETE = 389,\n\tTPM2_CC_HASH_SEQUENCE_START = 390,\n\tTPM2_CC_CREATE_LOADED = 401,\n\tTPM2_CC_LAST = 403,\n};\n\nenum tpm2_const {\n\tTPM2_PLATFORM_PCR = 24,\n\tTPM2_PCR_SELECT_MIN = 3,\n};\n\nenum tpm2_durations {\n\tTPM2_DURATION_SHORT = 20,\n\tTPM2_DURATION_LONG = 2000,\n\tTPM2_DURATION_DEFAULT = 120000,\n};\n\nenum tpm2_handle_types {\n\tTPM2_HT_HMAC_SESSION = 33554432,\n\tTPM2_HT_POLICY_SESSION = 50331648,\n\tTPM2_HT_TRANSIENT = 2147483648,\n};\n\nenum tpm2_permanent_handles {\n\tTPM2_RH_NULL = 1073741831,\n\tTPM2_RS_PW = 1073741833,\n};\n\nenum tpm2_properties {\n\tTPM_PT_TOTAL_COMMANDS = 297,\n};\n\nenum tpm2_return_codes {\n\tTPM2_RC_SUCCESS = 0,\n\tTPM2_RC_HASH = 131,\n\tTPM2_RC_HANDLE = 139,\n\tTPM2_RC_INTEGRITY = 159,\n\tTPM2_RC_INITIALIZE = 256,\n\tTPM2_RC_FAILURE = 257,\n\tTPM2_RC_DISABLED = 288,\n\tTPM2_RC_UPGRADE = 301,\n\tTPM2_RC_COMMAND_CODE = 323,\n\tTPM2_RC_TESTING = 2314,\n\tTPM2_RC_REFERENCE_H0 = 2320,\n\tTPM2_RC_RETRY = 2338,\n\tTPM2_RC_SESSION_MEMORY = 2307,\n};\n\nenum tpm2_session_attributes {\n\tTPM2_SA_CONTINUE_SESSION = 1,\n\tTPM2_SA_AUDIT_EXCLUSIVE = 2,\n\tTPM2_SA_AUDIT_RESET = 8,\n\tTPM2_SA_DECRYPT = 32,\n\tTPM2_SA_ENCRYPT = 64,\n\tTPM2_SA_AUDIT = 128,\n};\n\nenum tpm2_startup_types {\n\tTPM2_SU_CLEAR = 0,\n\tTPM2_SU_STATE = 1,\n};\n\nenum tpm2_structures {\n\tTPM2_ST_NO_SESSIONS = 32769,\n\tTPM2_ST_SESSIONS = 32770,\n\tTPM2_ST_CREATION = 32801,\n};\n\nenum tpm2_timeouts {\n\tTPM2_TIMEOUT_A = 750,\n\tTPM2_TIMEOUT_B = 4000,\n\tTPM2_TIMEOUT_C = 200,\n\tTPM2_TIMEOUT_D = 30,\n};\n\nenum tpm_algorithms {\n\tTPM_ALG_ERROR = 0,\n\tTPM_ALG_SHA1 = 4,\n\tTPM_ALG_AES = 6,\n\tTPM_ALG_KEYEDHASH = 8,\n\tTPM_ALG_SHA256 = 11,\n\tTPM_ALG_SHA384 = 12,\n\tTPM_ALG_SHA512 = 13,\n\tTPM_ALG_NULL = 16,\n\tTPM_ALG_SM3_256 = 18,\n\tTPM_ALG_ECC = 35,\n\tTPM_ALG_CFB = 67,\n};\n\nenum tpm_buf_flags {\n\tTPM_BUF_OVERFLOW = 1,\n\tTPM_BUF_TPM2B = 2,\n\tTPM_BUF_BOUNDARY_ERROR = 4,\n};\n\nenum tpm_capabilities {\n\tTPM_CAP_FLAG = 4,\n\tTPM_CAP_PROP = 5,\n\tTPM_CAP_VERSION_1_1 = 6,\n\tTPM_CAP_VERSION_1_2 = 26,\n};\n\nenum tpm_chip_flags {\n\tTPM_CHIP_FLAG_BOOTSTRAPPED = 1,\n\tTPM_CHIP_FLAG_TPM2 = 2,\n\tTPM_CHIP_FLAG_IRQ = 4,\n\tTPM_CHIP_FLAG_VIRTUAL = 8,\n\tTPM_CHIP_FLAG_HAVE_TIMEOUTS = 16,\n\tTPM_CHIP_FLAG_ALWAYS_POWERED = 32,\n\tTPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED = 64,\n\tTPM_CHIP_FLAG_FIRMWARE_UPGRADE = 128,\n\tTPM_CHIP_FLAG_SUSPENDED = 256,\n\tTPM_CHIP_FLAG_HWRNG_DISABLED = 512,\n\tTPM_CHIP_FLAG_DISABLE = 1024,\n\tTPM_CHIP_FLAG_SYNC = 2048,\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum tpm_pcrs {\n\tTPM_PCR0 = 0,\n\tTPM_PCR8 = 8,\n\tTPM_PCR10 = 10,\n};\n\nenum tpm_sub_capabilities {\n\tTPM_CAP_PROP_PCR = 257,\n\tTPM_CAP_PROP_MANUFACTURER = 259,\n\tTPM_CAP_FLAG_PERM = 264,\n\tTPM_CAP_FLAG_VOL = 265,\n\tTPM_CAP_PROP_OWNER = 273,\n\tTPM_CAP_PROP_TIS_TIMEOUT = 277,\n\tTPM_CAP_PROP_TIS_DURATION = 288,\n};\n\nenum tpm_timeout {\n\tTPM_TIMEOUT = 5,\n\tTPM_TIMEOUT_RETRY = 100,\n\tTPM_TIMEOUT_RANGE_US = 300,\n\tTPM_TIMEOUT_POLL = 1,\n\tTPM_TIMEOUT_USECS_MIN = 100,\n\tTPM_TIMEOUT_USECS_MAX = 500,\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_NEED_RESCHED_LAZY = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n\tTRACE_FLAG_BH_OFF = 128,\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n\tTRACE_FILE_PAUSE = 8,\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_FIELDS_BIT = 8,\n\tTRACE_ITER_PRINTK_BIT = 9,\n\tTRACE_ITER_ANNOTATE_BIT = 10,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 11,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 12,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 13,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 14,\n\tTRACE_ITER_LATENCY_FMT_BIT = 15,\n\tTRACE_ITER_RECORD_CMD_BIT = 16,\n\tTRACE_ITER_RECORD_TGID_BIT = 17,\n\tTRACE_ITER_OVERWRITE_BIT = 18,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 19,\n\tTRACE_ITER_IRQ_INFO_BIT = 20,\n\tTRACE_ITER_MARKERS_BIT = 21,\n\tTRACE_ITER_EVENT_FORK_BIT = 22,\n\tTRACE_ITER_TRACE_PRINTK_BIT = 23,\n\tTRACE_ITER_COPY_MARKER_BIT = 24,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 25,\n\tTRACE_ITER_HASH_PTR_BIT = 26,\n\tTRACE_ITER_BITMASK_LIST_BIT = 27,\n\tTRACE_ITER_FUNCTION_BIT = 28,\n\tTRACE_ITER_FUNC_FORK_BIT = 29,\n\tTRACE_ITER_DISPLAY_GRAPH_BIT = 30,\n\tTRACE_ITER_STACKTRACE_BIT = 31,\n\tTRACE_ITER_PROF_TEXT_OFFSET_BIT = 32,\n\tTRACE_ITER_GRAPH_TIME_BIT = 33,\n\tTRACE_ITER_LAST_BIT = 34,\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_GRAPH_RETADDR_ENT = 12,\n\tTRACE_USER_STACK = 13,\n\tTRACE_BLK = 14,\n\tTRACE_BPUTS = 15,\n\tTRACE_HWLAT = 16,\n\tTRACE_OSNOISE = 17,\n\tTRACE_TIMERLAT = 18,\n\tTRACE_RAW_DATA = 19,\n\tTRACE_FUNC_REPEATS = 20,\n\t__TRACE_LAST_TYPE = 21,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum transparent_hugepage_flag {\n\tTRANSPARENT_HUGEPAGE_UNSUPPORTED = 0,\n\tTRANSPARENT_HUGEPAGE_FLAG = 1,\n\tTRANSPARENT_HUGEPAGE_REQ_MADV_FLAG = 2,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_DIRECT_FLAG = 3,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_FLAG = 4,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_OR_MADV_FLAG = 5,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_REQ_MADV_FLAG = 6,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KHUGEPAGED_FLAG = 7,\n\tTRANSPARENT_HUGEPAGE_USE_ZERO_PAGE_FLAG = 8,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_state_t {\n\tTTY_CLOSED = 0,\n\tTTY_OPENED = 1,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum uc_todo {\n\tUC_TODO_RETRY = 0,\n\tUC_TODO_RETRY_ON_NEW_PATH = 1,\n\tUC_TODO_STOP = 2,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_FANOTIFY_GROUPS = 10,\n\tUCOUNT_FANOTIFY_MARKS = 11,\n\tUCOUNT_COUNTS = 12,\n};\n\nenum udp_conntrack {\n\tUDP_CT_UNREPLIED = 0,\n\tUDP_CT_REPLIED = 1,\n\tUDP_CT_MAX = 2,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nenum user_reg_flag {\n\tUSER_EVENT_REG_PERSIST = 1,\n\tUSER_EVENT_REG_MULTI_FORMAT = 2,\n\tUSER_EVENT_REG_MAX = 4,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum utf8_normalization {\n\tUTF8_NFDI = 0,\n\tUTF8_NFDICF = 1,\n\tUTF8_NMAX = 2,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum uv_cmds_inst {\n\tBIT_UVC_CMD_QUI = 0,\n\tBIT_UVC_CMD_INIT_UV = 1,\n\tBIT_UVC_CMD_CREATE_SEC_CONF = 2,\n\tBIT_UVC_CMD_DESTROY_SEC_CONF = 3,\n\tBIT_UVC_CMD_CREATE_SEC_CPU = 4,\n\tBIT_UVC_CMD_DESTROY_SEC_CPU = 5,\n\tBIT_UVC_CMD_CONV_TO_SEC_STOR = 6,\n\tBIT_UVC_CMD_CONV_FROM_SEC_STOR = 7,\n\tBIT_UVC_CMD_SET_SHARED_ACCESS = 8,\n\tBIT_UVC_CMD_REMOVE_SHARED_ACCESS = 9,\n\tBIT_UVC_CMD_SET_SEC_PARMS = 11,\n\tBIT_UVC_CMD_UNPACK_IMG = 13,\n\tBIT_UVC_CMD_VERIFY_IMG = 14,\n\tBIT_UVC_CMD_CPU_RESET = 15,\n\tBIT_UVC_CMD_CPU_RESET_INITIAL = 16,\n\tBIT_UVC_CMD_CPU_SET_STATE = 17,\n\tBIT_UVC_CMD_PREPARE_RESET = 18,\n\tBIT_UVC_CMD_CPU_PERFORM_CLEAR_RESET = 19,\n\tBIT_UVC_CMD_UNSHARE_ALL = 20,\n\tBIT_UVC_CMD_PIN_PAGE_SHARED = 21,\n\tBIT_UVC_CMD_UNPIN_PAGE_SHARED = 22,\n\tBIT_UVC_CMD_DESTROY_SEC_CONF_FAST = 23,\n\tBIT_UVC_CMD_DUMP_INIT = 24,\n\tBIT_UVC_CMD_DUMP_CONFIG_STOR_STATE = 25,\n\tBIT_UVC_CMD_DUMP_CPU = 26,\n\tBIT_UVC_CMD_DUMP_COMPLETE = 27,\n\tBIT_UVC_CMD_RETR_ATTEST = 28,\n\tBIT_UVC_CMD_ADD_SECRET = 29,\n\tBIT_UVC_CMD_LIST_SECRETS = 30,\n\tBIT_UVC_CMD_LOCK_SECRETS = 31,\n\tBIT_UVC_CMD_RETR_SECRET = 33,\n\tBIT_UVC_CMD_QUERY_KEYS = 34,\n};\n\nenum uv_feat_ind {\n\tBIT_UV_FEAT_MISC = 0,\n\tBIT_UV_FEAT_AIV = 1,\n\tBIT_UV_FEAT_AP = 4,\n\tBIT_UV_FEAT_AP_INTR = 5,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_TOD = 1,\n\tVDSO_CLOCKMODE_MAX = 2,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum vhost_task_flags {\n\tVHOST_TASK_FLAGS_STOP = 0,\n\tVHOST_TASK_FLAGS_KILLED = 1,\n};\n\nenum virtio_input_config_select {\n\tVIRTIO_INPUT_CFG_UNSET = 0,\n\tVIRTIO_INPUT_CFG_ID_NAME = 1,\n\tVIRTIO_INPUT_CFG_ID_SERIAL = 2,\n\tVIRTIO_INPUT_CFG_ID_DEVIDS = 3,\n\tVIRTIO_INPUT_CFG_PROP_BITS = 16,\n\tVIRTIO_INPUT_CFG_EV_BITS = 17,\n\tVIRTIO_INPUT_CFG_ABS_INFO = 18,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vlan_flags {\n\tVLAN_FLAG_REORDER_HDR = 1,\n\tVLAN_FLAG_GVRP = 2,\n\tVLAN_FLAG_LOOSE_BINDING = 4,\n\tVLAN_FLAG_MVRP = 8,\n\tVLAN_FLAG_BRIDGE_BINDING = 16,\n};\n\nenum vlan_protos {\n\tVLAN_PROTO_8021Q = 0,\n\tVLAN_PROTO_8021AD = 1,\n\tVLAN_PROTO_NUM = 2,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_DMA = 4,\n\tPGALLOC_NORMAL = 5,\n\tPGALLOC_MOVABLE = 6,\n\tPGALLOC_DEVICE = 7,\n\tALLOCSTALL_DMA = 8,\n\tALLOCSTALL_NORMAL = 9,\n\tALLOCSTALL_MOVABLE = 10,\n\tALLOCSTALL_DEVICE = 11,\n\tPGSCAN_SKIP_DMA = 12,\n\tPGSCAN_SKIP_NORMAL = 13,\n\tPGSCAN_SKIP_MOVABLE = 14,\n\tPGSCAN_SKIP_DEVICE = 15,\n\tPGFREE = 16,\n\tPGACTIVATE = 17,\n\tPGDEACTIVATE = 18,\n\tPGLAZYFREE = 19,\n\tPGFAULT = 20,\n\tPGMAJFAULT = 21,\n\tPGLAZYFREED = 22,\n\tPGREFILL = 23,\n\tPGREUSE = 24,\n\tPGSTEAL_KSWAPD = 25,\n\tPGSTEAL_DIRECT = 26,\n\tPGSTEAL_KHUGEPAGED = 27,\n\tPGSTEAL_PROACTIVE = 28,\n\tPGSCAN_KSWAPD = 29,\n\tPGSCAN_DIRECT = 30,\n\tPGSCAN_KHUGEPAGED = 31,\n\tPGSCAN_PROACTIVE = 32,\n\tPGSCAN_DIRECT_THROTTLE = 33,\n\tPGSCAN_ANON = 34,\n\tPGSCAN_FILE = 35,\n\tPGSTEAL_ANON = 36,\n\tPGSTEAL_FILE = 37,\n\tPGSCAN_ZONE_RECLAIM_SUCCESS = 38,\n\tPGSCAN_ZONE_RECLAIM_FAILED = 39,\n\tPGINODESTEAL = 40,\n\tSLABS_SCANNED = 41,\n\tKSWAPD_INODESTEAL = 42,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 43,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 44,\n\tPAGEOUTRUN = 45,\n\tPGROTATED = 46,\n\tDROP_PAGECACHE = 47,\n\tDROP_SLAB = 48,\n\tOOM_KILL = 49,\n\tNUMA_PTE_UPDATES = 50,\n\tNUMA_HUGE_PTE_UPDATES = 51,\n\tNUMA_HINT_FAULTS = 52,\n\tNUMA_HINT_FAULTS_LOCAL = 53,\n\tNUMA_PAGE_MIGRATE = 54,\n\tPGMIGRATE_SUCCESS = 55,\n\tPGMIGRATE_FAIL = 56,\n\tTHP_MIGRATION_SUCCESS = 57,\n\tTHP_MIGRATION_FAIL = 58,\n\tTHP_MIGRATION_SPLIT = 59,\n\tCOMPACTMIGRATE_SCANNED = 60,\n\tCOMPACTFREE_SCANNED = 61,\n\tCOMPACTISOLATED = 62,\n\tCOMPACTSTALL = 63,\n\tCOMPACTFAIL = 64,\n\tCOMPACTSUCCESS = 65,\n\tKCOMPACTD_WAKE = 66,\n\tKCOMPACTD_MIGRATE_SCANNED = 67,\n\tKCOMPACTD_FREE_SCANNED = 68,\n\tHTLB_BUDDY_PGALLOC = 69,\n\tHTLB_BUDDY_PGALLOC_FAIL = 70,\n\tCMA_ALLOC_SUCCESS = 71,\n\tCMA_ALLOC_FAIL = 72,\n\tUNEVICTABLE_PGCULLED = 73,\n\tUNEVICTABLE_PGSCANNED = 74,\n\tUNEVICTABLE_PGRESCUED = 75,\n\tUNEVICTABLE_PGMLOCKED = 76,\n\tUNEVICTABLE_PGMUNLOCKED = 77,\n\tUNEVICTABLE_PGCLEARED = 78,\n\tUNEVICTABLE_PGSTRANDED = 79,\n\tTHP_FAULT_ALLOC = 80,\n\tTHP_FAULT_FALLBACK = 81,\n\tTHP_FAULT_FALLBACK_CHARGE = 82,\n\tTHP_COLLAPSE_ALLOC = 83,\n\tTHP_COLLAPSE_ALLOC_FAILED = 84,\n\tTHP_FILE_ALLOC = 85,\n\tTHP_FILE_FALLBACK = 86,\n\tTHP_FILE_FALLBACK_CHARGE = 87,\n\tTHP_FILE_MAPPED = 88,\n\tTHP_SPLIT_PAGE = 89,\n\tTHP_SPLIT_PAGE_FAILED = 90,\n\tTHP_DEFERRED_SPLIT_PAGE = 91,\n\tTHP_UNDERUSED_SPLIT_PAGE = 92,\n\tTHP_SPLIT_PMD = 93,\n\tTHP_SCAN_EXCEED_NONE_PTE = 94,\n\tTHP_SCAN_EXCEED_SWAP_PTE = 95,\n\tTHP_SCAN_EXCEED_SHARED_PTE = 96,\n\tTHP_ZERO_PAGE_ALLOC = 97,\n\tTHP_ZERO_PAGE_ALLOC_FAILED = 98,\n\tTHP_SWPOUT = 99,\n\tTHP_SWPOUT_FALLBACK = 100,\n\tBALLOON_INFLATE = 101,\n\tBALLOON_DEFLATE = 102,\n\tBALLOON_MIGRATE = 103,\n\tSWAP_RA = 104,\n\tSWAP_RA_HIT = 105,\n\tSWPIN_ZERO = 106,\n\tSWPOUT_ZERO = 107,\n\tKSM_SWPIN_COPY = 108,\n\tCOW_KSM = 109,\n\tZSWPIN = 110,\n\tZSWPOUT = 111,\n\tZSWPWB = 112,\n\tNR_VM_EVENT_ITEMS = 113,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vma_resv_mode {\n\tVMA_NEEDS_RESV = 0,\n\tVMA_COMMIT_RESV = 1,\n\tVMA_END_RESV = 2,\n\tVMA_ADD_RESV = 3,\n\tVMA_DEL_RESV = 4,\n};\n\nenum vmpressure_levels {\n\tVMPRESSURE_LOW = 0,\n\tVMPRESSURE_MEDIUM = 1,\n\tVMPRESSURE_CRITICAL = 2,\n\tVMPRESSURE_NUM_LEVELS = 3,\n};\n\nenum vmpressure_modes {\n\tVMPRESSURE_NO_PASSTHROUGH = 0,\n\tVMPRESSURE_HIERARCHY = 1,\n\tVMPRESSURE_LOCAL = 2,\n\tVMPRESSURE_NUM_MODES = 3,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum vq_layout {\n\tVQ_LAYOUT_SPLIT = 0,\n\tVQ_LAYOUT_PACKED = 1,\n\tVQ_LAYOUT_SPLIT_IN_ORDER = 2,\n\tVQ_LAYOUT_PACKED_IN_ORDER = 3,\n};\n\nenum vsock_net_mode {\n\tVSOCK_NET_MODE_GLOBAL = 0,\n\tVSOCK_NET_MODE_LOCAL = 1,\n};\n\nenum watch_meta_notification_subtype {\n\tWATCH_META_REMOVAL_NOTIFICATION = 0,\n\tWATCH_META_LOSS_NOTIFICATION = 1,\n};\n\nenum watch_notification_type {\n\tWATCH_TYPE_META = 0,\n\tWATCH_TYPE_KEY_NOTIFY = 1,\n\tWATCH_TYPE__NR = 2,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum wbt_flags {\n\tWBT_TRACKED = 1,\n\tWBT_READ = 2,\n\tWBT_SWAP = 4,\n\tWBT_DISCARD = 8,\n\tWBT_NR_BITS = 4,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 43,\n\tWORK_OFFQ_POOL_BITS = 31,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 300000,\n\tMAYDAY_INITIAL_TIMEOUT = 10,\n\tMAYDAY_INTERVAL = 100,\n\tCREATE_COOLDOWN = 1000,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 512,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum x509_actions {\n\tACT_x509_extract_key_data = 0,\n\tACT_x509_extract_name_segment = 1,\n\tACT_x509_note_OID = 2,\n\tACT_x509_note_issuer = 3,\n\tACT_x509_note_not_after = 4,\n\tACT_x509_note_not_before = 5,\n\tACT_x509_note_params = 6,\n\tACT_x509_note_serial = 7,\n\tACT_x509_note_sig_algo = 8,\n\tACT_x509_note_signature = 9,\n\tACT_x509_note_subject = 10,\n\tACT_x509_note_tbs_certificate = 11,\n\tACT_x509_process_extension = 12,\n\tNR__x509_actions = 13,\n};\n\nenum x509_akid_actions {\n\tACT_x509_akid_note_kid = 0,\n\tACT_x509_akid_note_name = 1,\n\tACT_x509_akid_note_serial = 2,\n\tACT_x509_extract_name_segment___2 = 3,\n\tACT_x509_note_OID___2 = 4,\n\tNR__x509_akid_actions = 5,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xbtree_key_contig {\n\tXBTREE_KEY_GAP = 0,\n\tXBTREE_KEY_CONTIGUOUS = 1,\n\tXBTREE_KEY_OVERLAP = 2,\n};\n\nenum xbtree_recpacking {\n\tXBTREE_RECPACKING_EMPTY = 0,\n\tXBTREE_RECPACKING_SPARSE = 1,\n\tXBTREE_RECPACKING_FULL = 2,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xfrm_ae_ftype_t {\n\tXFRM_AE_UNSPEC = 0,\n\tXFRM_AE_RTHR = 1,\n\tXFRM_AE_RVAL = 2,\n\tXFRM_AE_LVAL = 4,\n\tXFRM_AE_ETHR = 8,\n\tXFRM_AE_CR = 16,\n\tXFRM_AE_CE = 32,\n\tXFRM_AE_CU = 64,\n\t__XFRM_AE_MAX = 65,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_nlgroups {\n\tXFRMNLGRP_NONE = 0,\n\tXFRMNLGRP_ACQUIRE = 1,\n\tXFRMNLGRP_EXPIRE = 2,\n\tXFRMNLGRP_SA = 3,\n\tXFRMNLGRP_POLICY = 4,\n\tXFRMNLGRP_AEVENTS = 5,\n\tXFRMNLGRP_REPORT = 6,\n\tXFRMNLGRP_MIGRATE = 7,\n\tXFRMNLGRP_MAPPING = 8,\n\t__XFRMNLGRP_MAX = 9,\n};\n\nenum xfrm_pol_inexact_candidate_type {\n\tXFRM_POL_CAND_BOTH = 0,\n\tXFRM_POL_CAND_SADDR = 1,\n\tXFRM_POL_CAND_DADDR = 2,\n\tXFRM_POL_CAND_ANY = 3,\n\tXFRM_POL_CAND_MAX = 4,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xfrm_sa_dir {\n\tXFRM_SA_DIR_IN = 1,\n\tXFRM_SA_DIR_OUT = 2,\n};\n\nenum xfs_ag_resv_type {\n\tXFS_AG_RESV_NONE = 0,\n\tXFS_AG_RESV_AGFL = 1,\n\tXFS_AG_RESV_METADATA = 2,\n\tXFS_AG_RESV_RMAPBT = 3,\n\tXFS_AG_RESV_IGNORE = 4,\n\tXFS_AG_RESV_METAFILE = 5,\n};\n\nenum xfs_attr_defer_op {\n\tXFS_ATTR_DEFER_SET = 0,\n\tXFS_ATTR_DEFER_REMOVE = 1,\n\tXFS_ATTR_DEFER_REPLACE = 2,\n};\n\nenum xfs_attr_update {\n\tXFS_ATTRUPDATE_REMOVE = 0,\n\tXFS_ATTRUPDATE_UPSERT = 1,\n\tXFS_ATTRUPDATE_CREATE = 2,\n\tXFS_ATTRUPDATE_REPLACE = 3,\n};\n\nenum xfs_blft {\n\tXFS_BLFT_UNKNOWN_BUF = 0,\n\tXFS_BLFT_UDQUOT_BUF = 1,\n\tXFS_BLFT_PDQUOT_BUF = 2,\n\tXFS_BLFT_GDQUOT_BUF = 3,\n\tXFS_BLFT_BTREE_BUF = 4,\n\tXFS_BLFT_AGF_BUF = 5,\n\tXFS_BLFT_AGFL_BUF = 6,\n\tXFS_BLFT_AGI_BUF = 7,\n\tXFS_BLFT_DINO_BUF = 8,\n\tXFS_BLFT_SYMLINK_BUF = 9,\n\tXFS_BLFT_DIR_BLOCK_BUF = 10,\n\tXFS_BLFT_DIR_DATA_BUF = 11,\n\tXFS_BLFT_DIR_FREE_BUF = 12,\n\tXFS_BLFT_DIR_LEAF1_BUF = 13,\n\tXFS_BLFT_DIR_LEAFN_BUF = 14,\n\tXFS_BLFT_DA_NODE_BUF = 15,\n\tXFS_BLFT_ATTR_LEAF_BUF = 16,\n\tXFS_BLFT_ATTR_RMT_BUF = 17,\n\tXFS_BLFT_SB_BUF = 18,\n\tXFS_BLFT_RTBITMAP_BUF = 19,\n\tXFS_BLFT_RTSUMMARY_BUF = 20,\n\tXFS_BLFT_MAX_BUF = 32,\n};\n\nenum xfs_bmap_intent_type {\n\tXFS_BMAP_MAP = 1,\n\tXFS_BMAP_UNMAP = 2,\n};\n\nenum xfs_btree_type {\n\tXFS_BTREE_TYPE_AG = 0,\n\tXFS_BTREE_TYPE_INODE = 1,\n\tXFS_BTREE_TYPE_MEM = 2,\n};\n\nenum xfs_dacmp {\n\tXFS_CMP_DIFFERENT = 0,\n\tXFS_CMP_EXACT = 1,\n\tXFS_CMP_CASE = 2,\n};\n\nenum xfs_dax_mode {\n\tXFS_DAX_INODE = 0,\n\tXFS_DAX_ALWAYS = 1,\n\tXFS_DAX_NEVER = 2,\n};\n\nenum xfs_delattr_state {\n\tXFS_DAS_UNINIT = 0,\n\tXFS_DAS_SF_ADD = 1,\n\tXFS_DAS_SF_REMOVE = 2,\n\tXFS_DAS_LEAF_ADD = 3,\n\tXFS_DAS_LEAF_REMOVE = 4,\n\tXFS_DAS_NODE_ADD = 5,\n\tXFS_DAS_NODE_REMOVE = 6,\n\tXFS_DAS_LEAF_SET_RMT = 7,\n\tXFS_DAS_LEAF_ALLOC_RMT = 8,\n\tXFS_DAS_LEAF_REPLACE = 9,\n\tXFS_DAS_LEAF_REMOVE_OLD = 10,\n\tXFS_DAS_LEAF_REMOVE_RMT = 11,\n\tXFS_DAS_LEAF_REMOVE_ATTR = 12,\n\tXFS_DAS_NODE_SET_RMT = 13,\n\tXFS_DAS_NODE_ALLOC_RMT = 14,\n\tXFS_DAS_NODE_REPLACE = 15,\n\tXFS_DAS_NODE_REMOVE_OLD = 16,\n\tXFS_DAS_NODE_REMOVE_RMT = 17,\n\tXFS_DAS_NODE_REMOVE_ATTR = 18,\n\tXFS_DAS_DONE = 19,\n};\n\nenum xfs_device {\n\tXFS_DEV_DATA = 1,\n\tXFS_DEV_LOG = 2,\n\tXFS_DEV_RT = 3,\n};\n\nenum xfs_dinode_fmt {\n\tXFS_DINODE_FMT_DEV = 0,\n\tXFS_DINODE_FMT_LOCAL = 1,\n\tXFS_DINODE_FMT_EXTENTS = 2,\n\tXFS_DINODE_FMT_BTREE = 3,\n\tXFS_DINODE_FMT_UUID = 4,\n\tXFS_DINODE_FMT_META_BTREE = 5,\n};\n\nenum xfs_dir2_fmt {\n\tXFS_DIR2_FMT_SF = 0,\n\tXFS_DIR2_FMT_BLOCK = 1,\n\tXFS_DIR2_FMT_LEAF = 2,\n\tXFS_DIR2_FMT_NODE = 3,\n\tXFS_DIR2_FMT_ERROR = 4,\n};\n\nenum xfs_experimental_feat {\n\tXFS_EXPERIMENTAL_SHRINK = 0,\n\tXFS_EXPERIMENTAL_LARP = 1,\n\tXFS_EXPERIMENTAL_ZONED = 2,\n\tXFS_EXPERIMENTAL_MAX = 3,\n};\n\nenum xfs_free_counter {\n\tXC_FREE_BLOCKS = 0,\n\tXC_FREE_RTEXTENTS = 1,\n\tXC_FREE_RTAVAILABLE = 2,\n\tXC_FREE_NR = 3,\n};\n\nenum xfs_fstrm_alloc {\n\tXFS_PICK_USERDATA = 1,\n\tXFS_PICK_LOWSPACE = 2,\n};\n\nenum xfs_group_type {\n\tXG_TYPE_AG = 0,\n\tXG_TYPE_RTG = 1,\n\tXG_TYPE_MAX = 2,\n} __attribute__((mode(byte)));\n\nenum xfs_healthmon_domain {\n\tXFS_HEALTHMON_MOUNT = 0,\n\tXFS_HEALTHMON_FS = 1,\n\tXFS_HEALTHMON_AG = 2,\n\tXFS_HEALTHMON_INODE = 3,\n\tXFS_HEALTHMON_RTGROUP = 4,\n\tXFS_HEALTHMON_DATADEV = 5,\n\tXFS_HEALTHMON_RTDEV = 6,\n\tXFS_HEALTHMON_LOGDEV = 7,\n\tXFS_HEALTHMON_FILERANGE = 8,\n};\n\nenum xfs_healthmon_type {\n\tXFS_HEALTHMON_RUNNING = 0,\n\tXFS_HEALTHMON_LOST = 1,\n\tXFS_HEALTHMON_UNMOUNT = 2,\n\tXFS_HEALTHMON_SHUTDOWN = 3,\n\tXFS_HEALTHMON_SICK = 4,\n\tXFS_HEALTHMON_CORRUPT = 5,\n\tXFS_HEALTHMON_HEALTHY = 6,\n\tXFS_HEALTHMON_MEDIA_ERROR = 7,\n\tXFS_HEALTHMON_BUFREAD = 8,\n\tXFS_HEALTHMON_BUFWRITE = 9,\n\tXFS_HEALTHMON_DIOREAD = 10,\n\tXFS_HEALTHMON_DIOWRITE = 11,\n\tXFS_HEALTHMON_DATALOST = 12,\n};\n\nenum xfs_icwalk_goal {\n\tXFS_ICWALK_BLOCKGC = 1,\n\tXFS_ICWALK_RECLAIM = 0,\n};\n\nenum xfs_metafile_type {\n\tXFS_METAFILE_UNKNOWN = 0,\n\tXFS_METAFILE_DIR = 1,\n\tXFS_METAFILE_USRQUOTA = 2,\n\tXFS_METAFILE_GRPQUOTA = 3,\n\tXFS_METAFILE_PRJQUOTA = 4,\n\tXFS_METAFILE_RTBITMAP = 5,\n\tXFS_METAFILE_RTSUMMARY = 6,\n\tXFS_METAFILE_RTRMAP = 7,\n\tXFS_METAFILE_RTREFCOUNT = 8,\n\tXFS_METAFILE_MAX = 9,\n} __attribute__((mode(byte)));\n\nenum xfs_refc_adjust_op {\n\tXFS_REFCOUNT_ADJUST_INCREASE = 1,\n\tXFS_REFCOUNT_ADJUST_DECREASE = -1,\n\tXFS_REFCOUNT_ADJUST_COW_ALLOC = 0,\n\tXFS_REFCOUNT_ADJUST_COW_FREE = -1,\n};\n\nenum xfs_refc_domain {\n\tXFS_REFC_DOMAIN_SHARED = 0,\n\tXFS_REFC_DOMAIN_COW = 1,\n};\n\nenum xfs_refcount_intent_type {\n\tXFS_REFCOUNT_INCREASE = 1,\n\tXFS_REFCOUNT_DECREASE = 2,\n\tXFS_REFCOUNT_ALLOC_COW = 3,\n\tXFS_REFCOUNT_FREE_COW = 4,\n};\n\nenum xfs_rmap_intent_type {\n\tXFS_RMAP_MAP = 0,\n\tXFS_RMAP_MAP_SHARED = 1,\n\tXFS_RMAP_UNMAP = 2,\n\tXFS_RMAP_UNMAP_SHARED = 3,\n\tXFS_RMAP_CONVERT = 4,\n\tXFS_RMAP_CONVERT_SHARED = 5,\n\tXFS_RMAP_ALLOC = 6,\n\tXFS_RMAP_FREE = 7,\n};\n\nenum xfs_rtg_inodes {\n\tXFS_RTGI_BITMAP = 0,\n\tXFS_RTGI_SUMMARY = 1,\n\tXFS_RTGI_RMAP = 2,\n\tXFS_RTGI_REFCOUNT = 3,\n\tXFS_RTGI_MAX = 4,\n};\n\nenum xfs_zone_alloc_score {\n\tXFS_ZONE_ALLOC_ANY = 0,\n\tXFS_ZONE_ALLOC_OK = 1,\n\tXFS_ZONE_ALLOC_GOOD = 2,\n};\n\nenum xlog_iclog_state {\n\tXLOG_STATE_ACTIVE = 0,\n\tXLOG_STATE_WANT_SYNC = 1,\n\tXLOG_STATE_SYNCING = 2,\n\tXLOG_STATE_DONE_SYNC = 3,\n\tXLOG_STATE_CALLBACK = 4,\n\tXLOG_STATE_DIRTY = 5,\n};\n\nenum xlog_recover_reorder {\n\tXLOG_REORDER_BUFFER_LIST = 0,\n\tXLOG_REORDER_ITEM_LIST = 1,\n\tXLOG_REORDER_INODE_BUFFER_LIST = 2,\n\tXLOG_REORDER_CANCEL_LIST = 3,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_ZSPAGES = 9,\n\tNR_FREE_CMA_PAGES = 10,\n\tNR_VM_ZONE_STAT_ITEMS = 11,\n};\n\nenum zone_type {\n\tZONE_DMA = 0,\n\tZONE_NORMAL = 1,\n\tZONE_MOVABLE = 2,\n\tZONE_DEVICE = 3,\n\t__MAX_NR_ZONES = 4,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\nenum zpci_ioat_dtype {\n\tZPCI_IOTA_STO = 0,\n\tZPCI_IOTA_RTTO = 1,\n\tZPCI_IOTA_RSTO = 2,\n\tZPCI_IOTA_RFTO = 3,\n\tZPCI_IOTA_PFAA = 4,\n\tZPCI_IOTA_IOPFAA = 5,\n\tZPCI_IOTA_IOPTO = 7,\n};\n\nenum zpci_state {\n\tZPCI_FN_STATE_STANDBY = 0,\n\tZPCI_FN_STATE_CONFIGURED = 1,\n\tZPCI_FN_STATE_RESERVED = 2,\n};\n\nenum zram_pageflags {\n\tZRAM_SAME = 13,\n\tZRAM_ENTRY_LOCK = 14,\n\tZRAM_WB = 15,\n\tZRAM_PP_SLOT = 16,\n\tZRAM_HUGE = 17,\n\tZRAM_IDLE = 18,\n\tZRAM_INCOMPRESSIBLE = 19,\n\tZRAM_COMP_PRIORITY_BIT1 = 20,\n\tZRAM_COMP_PRIORITY_BIT2 = 21,\n\t__NR_ZRAM_PAGEFLAGS = 22,\n};\n\nenum zswap_init_type {\n\tZSWAP_UNINIT = 0,\n\tZSWAP_INIT_SUCCEED = 1,\n\tZSWAP_INIT_FAILED = 2,\n};\n\ntypedef _Bool bool;\n\ntypedef __int128 unsigned __u128;\n\ntypedef __u128 u128;\n\ntypedef u128 freelist_full_t;\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_daddr_t;\n\ntypedef int __kernel_ipc_pid_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_mqd_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __s32;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef __s32 s32;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef int ext4_grpblk_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef int mhp_t;\n\ntypedef int mm_id_mapcount_t;\n\ntypedef int mpi_size_t;\n\ntypedef __kernel_mqd_t mqd_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef int pcp_op_T__;\n\ntypedef s32 pcp_op_T_____2;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef __s32 sctp_assoc_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef int vma_flag_t;\n\ntypedef int32_t xfs_suminfo_t;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef long int __kernel_ptrdiff_t;\n\ntypedef long int __kernel_ssize_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef long int mpi_limb_signed_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef long int pcp_op_T_____3;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 Elf64_Sxword;\n\ntypedef __s64 s64;\n\ntypedef s64 int64_t;\n\ntypedef int64_t S64;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef s64 pcp_op_T_____4;\n\ntypedef long long int qsize_t;\n\ntypedef s64 sblocknum_t;\n\ntypedef __s64 time64_t;\n\ntypedef int64_t xfs_csn_t;\n\ntypedef __s64 xfs_daddr_t;\n\ntypedef __s64 xfs_off_t;\n\ntypedef xfs_off_t xfs_dir2_off_t;\n\ntypedef int64_t xfs_fsize_t;\n\ntypedef int64_t xfs_lsn_t;\n\ntypedef int64_t xfs_srtblock_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef U64 ZSTD_VecMask;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef __u64 __virtio64;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 blocknum_t;\n\ntypedef u64 compat_u64;\n\ntypedef u64 dma64_t;\n\ntypedef u64 dma_addr_t;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef u64 gfn_t;\n\ntypedef u64 gpa_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 pci_bus_addr_t;\n\ntypedef u64 pcp_op_T_____5;\n\ntypedef u64 phys_addr_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u64 sccb_mask_t;\n\ntypedef u64 sci_t;\n\ntypedef u64 sector_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef u64 unative_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef uint64_t vli_type;\n\ntypedef uint64_t xfbno_t;\n\ntypedef __be64 xfs_bmbt_ptr_t;\n\ntypedef uint64_t xfs_bmbt_rec_base_t;\n\ntypedef uint64_t xfs_extnum_t;\n\ntypedef uint64_t xfs_filblks_t;\n\ntypedef uint64_t xfs_fileoff_t;\n\ntypedef uint64_t xfs_fsblock_t;\n\ntypedef long long unsigned int xfs_ino_t;\n\ntypedef uint64_t xfs_inofree_t;\n\ntypedef uint64_t xfs_log_timestamp_t;\n\ntypedef uint64_t xfs_qcnt_t;\n\ntypedef uint64_t xfs_rfsblock_t;\n\ntypedef uint64_t xfs_rtblock_t;\n\ntypedef uint64_t xfs_rtbxlen_t;\n\ntypedef __be64 xfs_rtrefcount_ptr_t;\n\ntypedef __be64 xfs_rtrmap_ptr_t;\n\ntypedef uint64_t xfs_rtxnum_t;\n\ntypedef __be64 xfs_timestamp_t;\n\ntypedef uint64_t xfs_ufsize_t;\n\ntypedef long unsigned int __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef size_t HUF_CElt;\n\ntypedef long unsigned int mpi_limb_t;\n\ntypedef mpi_limb_t UWtype;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef long unsigned int addr_t;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int cycles_t;\n\ntypedef long unsigned int dax_entry_t;\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int kimage_entry_t;\n\ntypedef mpi_limb_t *mpi_ptr_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int old_sigset_t;\n\ntypedef long unsigned int p4d_t;\n\ntypedef long unsigned int pcp_op_T_____6;\n\ntypedef long unsigned int perf_trace_t[1024];\n\ntypedef long unsigned int pgd_t;\n\ntypedef long unsigned int pgprot_t;\n\ntypedef long unsigned int pte_t;\n\ntypedef pte_t *pgtable_t;\n\ntypedef long unsigned int pmd_t;\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int pud_t;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulg;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef short unsigned int ush;\n\ntypedef ush Pos;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef u16 access_mask_t;\n\ntypedef __u16 bitmap_counter_t;\n\ntypedef u16 blk_short_t;\n\ntypedef __u16 comp_t;\n\ntypedef __kernel_gid16_t gid16_t;\n\ntypedef u16 kprobe_opcode_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef __u16 port_id;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef u16 u_int16_t;\n\ntypedef short unsigned int u_short;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef u16 uprobe_opcode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef short unsigned int vifi_t;\n\ntypedef u16 wchar_t;\n\ntypedef uint16_t xfs_dir2_data_off_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef s8 pcp_op_T_____7;\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef u8 deny_masks_t;\n\ntypedef u8 dscp_t;\n\ntypedef u8 rmap_age_t;\n\ntypedef unsigned char u8___2;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef unsigned char uch;\n\ntypedef const unsigned char utf8leaf_t;\n\ntypedef const unsigned char utf8trie_t;\n\ntypedef uint8_t xfs_dqtype_t;\n\ntypedef unsigned int __u32;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_CTable;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef __u32 u32;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef unsigned int IPos;\n\ntypedef unsigned int UHWtype;\n\ntypedef __u32 __be32;\n\ntypedef u32 __compat_uid32_t;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_gid_t;\n\ntypedef unsigned int __kernel_mode_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __virtio32;\n\ntypedef __u32 __wsum;\n\ntypedef unsigned int acr_flags_t;\n\ntypedef unsigned int ap_qid_t;\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef u32 depot_flags_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef u32 dma32_t;\n\ntypedef uint32_t drbg_flag_t;\n\ntypedef u32 errseq_t;\n\ntypedef unsigned int ext4_group_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef unsigned int ioasid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef unsigned int mm_id_t;\n\ntypedef __kernel_mode_t mode_t;\n\ntypedef u32 nlink_t;\n\ntypedef u32 note_buf_t[92];\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef unsigned int pcp_op_T_____8;\n\ntypedef __u32 pcp_op_T_____9;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef unsigned int pipe_index_t;\n\ntypedef uint32_t prid_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef __kernel_uid32_t qid_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef unsigned int sclp_cmdw_t;\n\ntypedef unsigned int sk_buff_data_t;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int speed_t;\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int tid_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef u32 u_int32_t;\n\ntypedef unsigned int uffd_flags_t;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef uint32_t xfs_aextnum_t;\n\ntypedef uint32_t xfs_agblock_t;\n\ntypedef uint32_t xfs_agino_t;\n\ntypedef uint32_t xfs_agnumber_t;\n\ntypedef unsigned int xfs_buf_flags_t;\n\ntypedef uint32_t xfs_dablk_t;\n\ntypedef uint32_t xfs_dahash_t;\n\ntypedef __u32 xfs_dev_t;\n\ntypedef uint xfs_dir2_data_aoff_t;\n\ntypedef uint32_t xfs_dir2_dataptr_t;\n\ntypedef uint32_t xfs_dir2_db_t;\n\ntypedef uint32_t xfs_dqid_t;\n\ntypedef uint32_t xfs_extlen_t;\n\ntypedef __u32 xfs_nlink_t;\n\ntypedef uint32_t xfs_rgblock_t;\n\ntypedef uint32_t xfs_rgnumber_t;\n\ntypedef uint32_t xfs_rtsumoff_t;\n\ntypedef uint32_t xfs_rtword_t;\n\ntypedef uint32_t xfs_rtxlen_t;\n\ntypedef uint32_t xlog_tid_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitPos;\n\tchar *startPtr;\n\tchar *ptr;\n\tchar *endPtr;\n} BIT_CStream_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tsize_t nbSequences;\n\tsize_t blockSize;\n\tsize_t litSize;\n} BlockSummary;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\ntypedef struct {\n\tsize_t estLitSize;\n\tsize_t estBlockSize;\n} EstimatedBlockSize;\n\ntypedef struct {\n\tunsigned int events[1024];\n\tsize_t nbEvents;\n} Fingerprint;\n\ntypedef struct {\n\tFingerprint pastEvents;\n\tFingerprint newEvents;\n} FPStats;\n\ntypedef struct {\n\tptrdiff_t value;\n\tconst void *stateTable;\n\tconst void *symbolTT;\n\tunsigned int stateLog;\n} FSE_CState_t;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tint deltaFindState;\n\tU32 deltaNbBits;\n} FSE_symbolCompressionTransform;\n\ntypedef struct {\n\tsize_t bitContainer[2];\n\tsize_t bitPos[2];\n\tBYTE *startPtr;\n\tBYTE *ptr;\n\tBYTE *endPtr;\n} HUF_CStream_t;\n\ntypedef struct {\n\tBYTE tableLog;\n\tBYTE maxSymbolValue;\n\tBYTE unused[6];\n} HUF_CTableHeader;\n\ntypedef struct {\n\tFSE_CTable CTable[59];\n\tU32 scratchBuffer[41];\n\tunsigned int count[13];\n\tS16 norm[13];\n} HUF_CompressWeightsWksp;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\ntypedef struct {\n\tHUF_CompressWeightsWksp wksp;\n\tBYTE bitsToWeight[13];\n\tBYTE huffWeight[255];\n} HUF_WriteCTableWksp;\n\nstruct nodeElt_s {\n\tU32 count;\n\tU16 parent;\n\tBYTE byte;\n\tBYTE nbBits;\n};\n\ntypedef struct nodeElt_s nodeElt;\n\ntypedef nodeElt huffNodeTable[512];\n\ntypedef struct {\n\tU16 base;\n\tU16 curr;\n} rankPos;\n\ntypedef struct {\n\thuffNodeTable huffNodeTbl;\n\trankPos rankPosition[192];\n} HUF_buildCTable_wksp_tables;\n\ntypedef struct {\n\tunsigned int count[256];\n\tHUF_CElt CTable[257];\n\tunion {\n\t\tHUF_buildCTable_wksp_tables buildCTable_wksp;\n\t\tHUF_WriteCTableWksp writeCTable_wksp;\n\t\tU32 hist_wksp[1024];\n\t} wksps;\n} HUF_compress_tables_t;\n\nstruct buffer_head;\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\ntypedef struct {\n\tunsigned int hashTable[32768];\n\tshort unsigned int chainTable[65536];\n\tconst unsigned char *end;\n\tconst unsigned char *base;\n\tconst unsigned char *dictBase;\n\tunsigned int dictLimit;\n\tunsigned int lowLimit;\n\tunsigned int nextToUpdate;\n\tunsigned int compressionLevel;\n} LZ4HC_CCtx_internal;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\ntypedef union {\n\tsize_t table[32774];\n\tLZ4HC_CCtx_internal internal_donotuse;\n} LZ4_streamHC_t;\n\ntypedef struct {\n\tuint32_t hashTable[4096];\n\tuint32_t currentOffset;\n\tuint32_t initCheck;\n\tconst uint8_t *dictionary;\n\tuint8_t *bufferStart;\n\tuint32_t dictSize;\n} LZ4_stream_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[2052];\n\tLZ4_stream_t_internal internal_donotuse;\n} LZ4_stream_t;\n\ntypedef struct {\n\tU32 offset;\n\tU32 litLength;\n\tU32 matchLength;\n} rawSeq;\n\ntypedef struct {\n\trawSeq *seq;\n\tsize_t pos;\n\tsize_t posInSequence;\n\tsize_t size;\n\tsize_t capacity;\n} RawSeqStore_t;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\ntypedef struct {\n\tunsigned int offset;\n\tunsigned int litLength;\n\tunsigned int matchLength;\n\tunsigned int rep;\n} ZSTD_Sequence;\n\ntypedef struct {\n\tint collectSequences;\n\tZSTD_Sequence *seqStart;\n\tsize_t seqIndex;\n\tsize_t maxSequences;\n} SeqCollector;\n\nstruct SeqDef_s;\n\ntypedef struct SeqDef_s SeqDef;\n\ntypedef struct {\n\tSeqDef *sequencesStart;\n\tSeqDef *sequences;\n\tBYTE *litStart;\n\tBYTE *lit;\n\tBYTE *llCode;\n\tBYTE *mlCode;\n\tBYTE *ofCode;\n\tsize_t maxNbSeq;\n\tsize_t maxNbLit;\n\tZSTD_longLengthType_e longLengthType;\n\tU32 longLengthPos;\n} SeqStore_t;\n\ntypedef struct {\n\tS16 norm[53];\n\tU32 wksp[285];\n} ZSTD_BuildCTableWksp;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tU32 litLength;\n\tU32 matchLength;\n} ZSTD_SequenceLength;\n\ntypedef struct {\n\tU32 idx;\n\tU32 posInSequence;\n\tsize_t posInSrc;\n} ZSTD_SequencePosition;\n\ntypedef struct {\n\tSymbolEncodingType_e hType;\n\tBYTE hufDesBuffer[128];\n\tsize_t hufDesSize;\n} ZSTD_hufCTablesMetadata_t;\n\ntypedef struct {\n\tSymbolEncodingType_e llType;\n\tSymbolEncodingType_e ofType;\n\tSymbolEncodingType_e mlType;\n\tBYTE fseTablesBuffer[133];\n\tsize_t fseTablesSize;\n\tsize_t lastCountSize;\n} ZSTD_fseCTablesMetadata_t;\n\ntypedef struct {\n\tZSTD_hufCTablesMetadata_t hufMetadata;\n\tZSTD_fseCTablesMetadata_t fseMetadata;\n} ZSTD_entropyCTablesMetadata_t;\n\ntypedef struct {\n\tSeqStore_t fullSeqStoreChunk;\n\tSeqStore_t firstHalfSeqStore;\n\tSeqStore_t secondHalfSeqStore;\n\tSeqStore_t currSeqStore;\n\tSeqStore_t nextSeqStore;\n\tU32 partitions[196];\n\tZSTD_entropyCTablesMetadata_t entropyMetadata;\n} ZSTD_blockSplitCtx;\n\ntypedef struct {\n\tHUF_CElt CTable[257];\n\tHUF_repeat repeatMode;\n} ZSTD_hufCTables_t;\n\ntypedef struct {\n\tFSE_CTable offcodeCTable[193];\n\tFSE_CTable matchlengthCTable[363];\n\tFSE_CTable litlengthCTable[329];\n\tFSE_repeat offcode_repeatMode;\n\tFSE_repeat matchlength_repeatMode;\n\tFSE_repeat litlength_repeatMode;\n} ZSTD_fseCTables_t;\n\ntypedef struct {\n\tZSTD_hufCTables_t huf;\n\tZSTD_fseCTables_t fse;\n} ZSTD_entropyCTables_t;\n\ntypedef struct {\n\tZSTD_entropyCTables_t entropy;\n\tU32 rep[3];\n} ZSTD_compressedBlockState_t;\n\ntypedef struct {\n\tconst BYTE *nextSrc;\n\tconst BYTE *base;\n\tconst BYTE *dictBase;\n\tU32 dictLimit;\n\tU32 lowLimit;\n\tU32 nbOverflowCorrections;\n} ZSTD_window_t;\n\ntypedef struct {\n\tU32 off;\n\tU32 len;\n} ZSTD_match_t;\n\ntypedef struct {\n\tint price;\n\tU32 off;\n\tU32 mlen;\n\tU32 litlen;\n\tU32 rep[3];\n} ZSTD_optimal_t;\n\ntypedef struct {\n\tunsigned int *litFreq;\n\tunsigned int *litLengthFreq;\n\tunsigned int *matchLengthFreq;\n\tunsigned int *offCodeFreq;\n\tZSTD_match_t *matchTable;\n\tZSTD_optimal_t *priceTable;\n\tU32 litSum;\n\tU32 litLengthSum;\n\tU32 matchLengthSum;\n\tU32 offCodeSum;\n\tU32 litSumBasePrice;\n\tU32 litLengthSumBasePrice;\n\tU32 matchLengthSumBasePrice;\n\tU32 offCodeSumBasePrice;\n\tZSTD_OptPrice_e priceType;\n\tconst ZSTD_entropyCTables_t *symbolCosts;\n\tZSTD_ParamSwitch_e literalCompressionMode;\n} optState_t;\n\ntypedef struct {\n\tunsigned int windowLog;\n\tunsigned int chainLog;\n\tunsigned int hashLog;\n\tunsigned int searchLog;\n\tunsigned int minMatch;\n\tunsigned int targetLength;\n\tZSTD_strategy strategy;\n} ZSTD_compressionParameters;\n\nstruct ZSTD_MatchState_t;\n\ntypedef struct ZSTD_MatchState_t ZSTD_MatchState_t;\n\nstruct ZSTD_MatchState_t {\n\tZSTD_window_t window;\n\tU32 loadedDictEnd;\n\tU32 nextToUpdate;\n\tU32 hashLog3;\n\tU32 rowHashLog;\n\tBYTE *tagTable;\n\tU32 hashCache[8];\n\tU64 hashSalt;\n\tU32 hashSaltEntropy;\n\tU32 *hashTable;\n\tU32 *hashTable3;\n\tU32 *chainTable;\n\tint forceNonContiguous;\n\tint dedicatedDictSearch;\n\toptState_t opt;\n\tconst ZSTD_MatchState_t *dictMatchState;\n\tZSTD_compressionParameters cParams;\n\tconst RawSeqStore_t *ldmSeqStore;\n\tint prefetchCDictTables;\n\tint lazySkipping;\n};\n\ntypedef struct {\n\tZSTD_compressedBlockState_t *prevCBlock;\n\tZSTD_compressedBlockState_t *nextCBlock;\n\tZSTD_MatchState_t matchState;\n} ZSTD_blockState_t;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef struct {\n\tU32 f1c;\n\tU32 f1d;\n\tU32 f7b;\n\tU32 f7c;\n} ZSTD_cpuid_t;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tvoid *workspace;\n\tvoid *workspaceEnd;\n\tvoid *objectEnd;\n\tvoid *tableEnd;\n\tvoid *tableValidEnd;\n\tvoid *allocStart;\n\tvoid *initOnceStart;\n\tBYTE allocFailed;\n\tint workspaceOversizedDuration;\n\tZSTD_cwksp_alloc_phase_e phase;\n\tZSTD_cwksp_static_alloc_e isStatic;\n} ZSTD_cwksp;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tint contentSizeFlag;\n\tint checksumFlag;\n\tint noDictIDFlag;\n} ZSTD_frameParameters;\n\ntypedef struct {\n\tlong long unsigned int ingested;\n\tlong long unsigned int consumed;\n\tlong long unsigned int produced;\n\tlong long unsigned int flushed;\n\tunsigned int currentJobID;\n\tunsigned int nbActiveWorkers;\n} ZSTD_frameProgression;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\nstruct ZSTD_CDict_s;\n\ntypedef struct ZSTD_CDict_s ZSTD_CDict;\n\ntypedef struct {\n\tvoid *dictBuffer;\n\tconst void *dict;\n\tsize_t dictSize;\n\tZSTD_dictContentType_e dictContentType;\n\tZSTD_CDict *cdict;\n} ZSTD_localDict;\n\ntypedef struct {\n\tRawSeqStore_t seqStore;\n\tU32 startPosInBlock;\n\tU32 endPosInBlock;\n\tU32 offset;\n} ZSTD_optLdm_t;\n\ntypedef struct {\n\tZSTD_compressionParameters cParams;\n\tZSTD_frameParameters fParams;\n} ZSTD_parameters;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tU32 LLtype;\n\tU32 Offtype;\n\tU32 MLtype;\n\tsize_t size;\n\tsize_t lastCountSize;\n\tint longOffsets;\n} ZSTD_symbolEncodingTypeStats_t;\n\ntypedef struct {\n\tlong unsigned int fds_bits[16];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef struct {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 high;\n\t\t\t__u64 low;\n\t\t};\n\t\t__u32 u[4];\n\t};\n} __vector128;\n\ntypedef struct {\n\tlong unsigned int mask;\n\tlong unsigned int addr;\n} _psw_t;\n\ntypedef struct {\n\tunsigned int fpc;\n\tunsigned int pad;\n\tdouble fprs[16];\n} _s390_fp_regs;\n\ntypedef struct {\n\t_psw_t psw;\n\tlong unsigned int gprs[16];\n\tunsigned int acrs[16];\n} _s390_regs_common;\n\ntypedef struct {\n\t_s390_regs_common regs;\n\t_s390_fp_regs fpregs;\n} _sigregs;\n\ntypedef struct {\n\tlong long unsigned int vxrs_low[16];\n\t__vector128 vxrs_high[16];\n\tunsigned char __reserved[128];\n} _sigregs_ext;\n\ntypedef struct {\n\tchar _[4096];\n} addr_type;\n\nstruct dasd_diag_init_io {\n\tu16 dev_nr;\n\tu8 flaga;\n\tu8 spare1[21];\n\tu32 block_size;\n\tu8 spare2[4];\n\tblocknum_t offset;\n\tsblocknum_t start_block;\n\tblocknum_t end_block;\n\tu8 spare3[8];\n};\n\nstruct dasd_diag_bio;\n\nstruct dasd_diag_rw_io {\n\tu16 dev_nr;\n\tu8 flaga;\n\tu8 spare1[21];\n\tu8 key;\n\tu8 flags;\n\tu8 spare2[2];\n\tu32 block_count;\n\tu32 alet;\n\tu8 spare3[4];\n\tu64 interrupt_params;\n\tstruct dasd_diag_bio *bio_list;\n\tu8 spare4[8];\n};\n\ntypedef union {\n\tstruct dasd_diag_init_io init_io;\n\tstruct dasd_diag_rw_io rw_io;\n} addr_type___2;\n\ntypedef struct {\n\tu8 _[256];\n} addrtype;\n\ntypedef union {\n} aes_encrypt_arg;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\tint lock;\n} arch_spinlock_t;\n\ntypedef struct {\n\tint cnts;\n\tarch_spinlock_t wait;\n} arch_rwlock_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef atomic64_t atomic_long_t;\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\ntypedef struct {\n\t__be64 a;\n\t__be64 b;\n} be128;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tlong unsigned int mask;\n\tlong unsigned int addr;\n} psw_t;\n\ntypedef struct {\n\tlong unsigned int args[1];\n\tpsw_t psw;\n\tlong unsigned int gprs[16];\n} user_pt_regs;\n\ntypedef user_pt_regs bpf_user_pt_regs_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\nstruct permanent_flags_t {\n\t__be16 tag;\n\tu8 disable;\n\tu8 ownership;\n\tu8 deactivated;\n\tu8 readPubek;\n\tu8 disableOwnerClear;\n\tu8 allowMaintenance;\n\tu8 physicalPresenceLifetimeLock;\n\tu8 physicalPresenceHWEnable;\n\tu8 physicalPresenceCMDEnable;\n\tu8 CEKPUsed;\n\tu8 TPMpost;\n\tu8 TPMpostLock;\n\tu8 FIPS;\n\tu8 operator;\n\tu8 enableRevokeEK;\n\tu8 nvLocked;\n\tu8 readSRKPub;\n\tu8 tpmEstablished;\n\tu8 maintenanceDone;\n\tu8 disableFullDALogicInfo;\n};\n\nstruct stclear_flags_t {\n\t__be16 tag;\n\tu8 deactivated;\n\tu8 disableForceClear;\n\tu8 physicalPresence;\n\tu8 physicalPresenceLock;\n\tu8 bGlobalLock;\n} __attribute__((packed));\n\nstruct tpm1_version {\n\tu8 major;\n\tu8 minor;\n\tu8 rev_major;\n\tu8 rev_minor;\n};\n\nstruct tpm1_version2 {\n\t__be16 tag;\n\tstruct tpm1_version version;\n};\n\nstruct timeout_t {\n\t__be32 a;\n\t__be32 b;\n\t__be32 c;\n\t__be32 d;\n};\n\nstruct duration_t {\n\t__be32 tpm_short;\n\t__be32 tpm_medium;\n\t__be32 tpm_long;\n};\n\ntypedef union {\n\tstruct permanent_flags_t perm_flags;\n\tstruct stclear_flags_t stclear_flags;\n\t__u8 owned;\n\t__be32 num_pcrs;\n\tstruct tpm1_version version1;\n\tstruct tpm1_version2 version2;\n\t__be32 manufacturer_id;\n\tstruct timeout_t timeout;\n\tstruct duration_t duration;\n} cap_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tint *lock;\n\tlong unsigned int flags;\n} class_core_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\traw_spinlock_t *lock2;\n} class_double_raw_spinlock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_jump_label_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_init_t;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\nstruct perf_cpu_context;\n\nstruct perf_event_context;\n\ntypedef struct {\n\tstruct perf_cpu_context *cpuctx;\n\tstruct perf_event_context *ctx;\n} class_perf_ctx_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_notrace_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_nested_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\nstruct srcu_ctr;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tstruct srcu_ctr *scp;\n} class_srcu_fast_notrace_t;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef struct {\n\tunsigned char bytes[16];\n} cpacf_mask_t;\n\ntypedef struct {\n\tunsigned char bytes[256];\n} cpacf_qai_t;\n\ntypedef struct {\n\tchar *string;\n\tlong int args[0];\n} debug_sprintf_entry_t;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef union {\n\tfloat f;\n\tdouble d;\n\t__u64 ui;\n\tstruct {\n\t\t__u32 hi;\n\t\t__u32 lo;\n\t} fp;\n} freg_t;\n\ntypedef struct {\n\t__u32 fpc;\n\t__u32 pad;\n\tfreg_t fprs[16];\n} s390_fp_regs;\n\ntypedef s390_fp_regs elf_fpregset_t;\n\ntypedef struct {\n\tpsw_t psw;\n\tlong unsigned int gprs[16];\n\tunsigned int acrs[16];\n\tlong unsigned int orig_gpr2;\n} s390_regs;\n\ntypedef s390_regs elf_gregset_t;\n\ntypedef struct {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n} ext4_acl_entry;\n\ntypedef struct {\n\t__le32 a_version;\n} ext4_acl_header;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic64_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\tU32 offset;\n\tU32 checksum;\n} ldmEntry_t;\n\ntypedef struct {\n\tconst BYTE *split;\n\tU32 hash;\n\tU32 checksum;\n\tldmEntry_t *bucket;\n} ldmMatchCandidate_t;\n\ntypedef struct {\n\tZSTD_ParamSwitch_e enableLdm;\n\tU32 hashLog;\n\tU32 bucketSizeLog;\n\tU32 minMatchLength;\n\tU32 hashRateLog;\n\tU32 windowLog;\n} ldmParams_t;\n\ntypedef struct {\n\tU64 rolling;\n\tU64 stopMask;\n} ldmRollingHashState_t;\n\ntypedef struct {\n\tZSTD_window_t window;\n\tldmEntry_t *hashTable;\n\tU32 loadedDictEnd;\n\tBYTE *bucketOffsets;\n\tsize_t splitIndices[64];\n\tldmMatchCandidate_t matchCandidates[64];\n} ldmState_t;\n\ntypedef struct {\n\t__le64 b;\n\t__le64 a;\n} le128;\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef struct {\n\tlocal_t a;\n} local64_t;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\ntypedef struct {\n\tspinlock_t lock;\n\tcpumask_t cpu_attach_mask;\n\tatomic_t flush_count;\n\tunsigned int flush_mm;\n\tstruct list_head gmap_list;\n\tlong unsigned int gmap_asce;\n\tlong unsigned int asce;\n\tlong unsigned int asce_limit;\n\tlong unsigned int vdso_base;\n\tatomic_t protected_count;\n\tunsigned int allow_cow_sharing: 1;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[1];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tunsigned int len;\n\tlong unsigned int kernel_addr;\n\tlong unsigned int process_addr;\n} ptrace_area;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tU32 *splitLocations;\n\tsize_t idx;\n} seqStoreSplits;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[1];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\tlocal64_t v;\n} u64_stats_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_compressionParameters zstd_compression_parameters;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\ntypedef ZSTD_parameters zstd_parameters;\n\ntypedef ZSTD_Sequence zstd_sequence;\n\nstruct DCTL_data {\n\tunsigned char subcommand;\n\tunsigned char modifier;\n\tshort unsigned int res;\n};\n\nstruct ch_t {\n\t__u16 cyl;\n\t__u16 head;\n};\n\nstruct DE_eckd_data {\n\tstruct {\n\t\tunsigned char perm: 2;\n\t\tunsigned char reserved: 1;\n\t\tunsigned char seek: 2;\n\t\tunsigned char auth: 2;\n\t\tunsigned char pci: 1;\n\t} mask;\n\tstruct {\n\t\tunsigned char mode: 2;\n\t\tunsigned char ckd: 1;\n\t\tunsigned char operation: 3;\n\t\tunsigned char cfw: 1;\n\t\tunsigned char dfw: 1;\n\t} attributes;\n\t__u16 blk_size;\n\t__u16 fast_write_id;\n\t__u8 ga_additional;\n\t__u8 ga_extended;\n\tstruct ch_t beg_ext;\n\tstruct ch_t end_ext;\n\tlong unsigned int ep_sys_time;\n\t__u8 ep_format;\n\t__u8 ep_prio;\n\t__u8 ep_reserved1;\n\t__u8 ep_rec_per_track;\n\t__u8 ep_reserved[4];\n};\n\nstruct DE_fba_data {\n\tstruct {\n\t\tunsigned char perm: 2;\n\t\tunsigned char zero: 2;\n\t\tunsigned char da: 1;\n\t\tunsigned char diag: 1;\n\t\tunsigned char zero2: 2;\n\t} mask;\n\t__u8 zero;\n\t__u16 blk_size;\n\t__u32 ext_loc;\n\t__u32 ext_beg;\n\t__u32 ext_end;\n};\n\nstruct chr_t {\n\t__u16 cyl;\n\t__u16 head;\n\t__u8 record;\n} __attribute__((packed));\n\nstruct LO_eckd_data {\n\tstruct {\n\t\tunsigned char orientation: 2;\n\t\tunsigned char operation: 6;\n\t} operation;\n\tstruct {\n\t\tunsigned char last_bytes_used: 1;\n\t\tunsigned char reserved: 6;\n\t\tunsigned char read_count_suffix: 1;\n\t} auxiliary;\n\t__u8 unused;\n\t__u8 count;\n\tstruct ch_t seek_addr;\n\tstruct chr_t search_arg;\n\t__u8 sector;\n\t__u16 length;\n};\n\nstruct LO_fba_data {\n\tstruct {\n\t\tunsigned char zero: 4;\n\t\tunsigned char cmd: 4;\n\t} operation;\n\t__u8 auxiliary;\n\t__u16 blk_ct;\n\t__u32 blk_nr;\n};\n\nstruct LRE_eckd_data {\n\tstruct {\n\t\tunsigned char orientation: 2;\n\t\tunsigned char operation: 6;\n\t} operation;\n\tstruct {\n\t\tunsigned char length_valid: 1;\n\t\tunsigned char length_scope: 1;\n\t\tunsigned char imbedded_ccw_valid: 1;\n\t\tunsigned char check_bytes: 2;\n\t\tunsigned char imbedded_count_valid: 1;\n\t\tunsigned char reserved: 1;\n\t\tunsigned char read_count_suffix: 1;\n\t} auxiliary;\n\t__u8 imbedded_ccw;\n\t__u8 count;\n\tstruct ch_t seek_addr;\n\tstruct chr_t search_arg;\n\t__u8 sector;\n\t__u16 length;\n\t__u8 imbedded_count;\n\t__u8 extended_operation;\n\t__u16 extended_parameter_length;\n\t__u8 extended_parameter[0];\n};\n\nstruct PFX_eckd_data {\n\tunsigned char format;\n\tstruct {\n\t\tunsigned char define_extent: 1;\n\t\tunsigned char time_stamp: 1;\n\t\tunsigned char verify_base: 1;\n\t\tunsigned char hyper_pav: 1;\n\t\tunsigned char reserved: 4;\n\t} validity;\n\t__u8 base_address;\n\t__u8 aux;\n\t__u8 base_lss;\n\t__u8 reserved[7];\n\tstruct DE_eckd_data define_extent;\n\tstruct LRE_eckd_data locate_record;\n} __attribute__((packed));\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lock_class_key {};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong int privdata[0];\n};\n\nstruct Qdisc_class_common {\n\tu32 classid;\n\tunsigned int filter_cnt;\n\tstruct hlist_node hnode;\n};\n\nstruct hlist_head;\n\nstruct Qdisc_class_hash {\n\tstruct hlist_head *hash;\n\tunsigned int hashsize;\n\tunsigned int hashmask;\n\tunsigned int hashelems;\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct RR_CL_s {\n\t__u8 location[8];\n};\n\nstruct RR_NM_s {\n\t__u8 flags;\n\tchar name[0];\n};\n\nstruct RR_PL_s {\n\t__u8 location[8];\n};\n\nstruct RR_PN_s {\n\t__u8 dev_high[8];\n\t__u8 dev_low[8];\n};\n\nstruct RR_PX_s {\n\t__u8 mode[8];\n\t__u8 n_links[8];\n\t__u8 uid[8];\n\t__u8 gid[8];\n};\n\nstruct RR_RR_s {\n\t__u8 flags[1];\n};\n\nstruct SL_component {\n\t__u8 flags;\n\t__u8 len;\n\t__u8 text[0];\n};\n\nstruct RR_SL_s {\n\t__u8 flags;\n\tstruct SL_component link;\n};\n\nstruct RR_TF_s {\n\t__u8 flags;\n\t__u8 data[0];\n};\n\nstruct RR_ZF_s {\n\t__u8 algorithm[2];\n\t__u8 parms[2];\n\t__u8 real_size[8];\n};\n\nstruct SU_CE_s {\n\t__u8 extent[8];\n\t__u8 offset[8];\n\t__u8 size[8];\n};\n\nstruct SU_ER_s {\n\t__u8 len_id;\n\t__u8 len_des;\n\t__u8 len_src;\n\t__u8 ext_ver;\n\t__u8 data[0];\n};\n\nstruct SU_SP_s {\n\t__u8 magic[2];\n\t__u8 skip;\n};\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct lockdep_map {};\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tbool should_wakeup: 1;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct dev_archdata {};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct dma_map_ops;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct cma;\n\nstruct io_tlb_mem;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct dev_msi_info msi;\n\tconst struct dma_map_ops *dma_ops;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct cma *cma_area;\n\tstruct io_tlb_mem *dma_io_tlb_mem;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tint numa_node;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_skip_sync: 1;\n\tbool dma_iommu: 1;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct SeqDef_s {\n\tU32 offBase;\n\tU16 litLength;\n\tU16 mlBase;\n};\n\ntypedef size_t (*ZSTD_sequenceProducer_F)(void *, ZSTD_Sequence *, size_t, const void *, size_t, const void *, size_t, int, size_t);\n\nstruct ZSTD_CCtx_params_s {\n\tZSTD_format_e format;\n\tZSTD_compressionParameters cParams;\n\tZSTD_frameParameters fParams;\n\tint compressionLevel;\n\tint forceWindow;\n\tsize_t targetCBlockSize;\n\tint srcSizeHint;\n\tZSTD_dictAttachPref_e attachDictPref;\n\tZSTD_ParamSwitch_e literalCompressionMode;\n\tint nbWorkers;\n\tsize_t jobSize;\n\tint overlapLog;\n\tint rsyncable;\n\tldmParams_t ldmParams;\n\tint enableDedicatedDictSearch;\n\tZSTD_bufferMode_e inBufferMode;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_SequenceFormat_e blockDelimiters;\n\tint validateSequences;\n\tZSTD_ParamSwitch_e postBlockSplitter;\n\tint preBlockSplitter_level;\n\tsize_t maxBlockSize;\n\tZSTD_ParamSwitch_e useRowMatchFinder;\n\tint deterministicRefPrefix;\n\tZSTD_customMem customMem;\n\tZSTD_ParamSwitch_e prefetchCDictTables;\n\tint enableMatchFinderFallback;\n\tvoid *extSeqProdState;\n\tZSTD_sequenceProducer_F extSeqProdFunc;\n\tZSTD_ParamSwitch_e searchForExternalRepcodes;\n};\n\ntypedef struct ZSTD_CCtx_params_s ZSTD_CCtx_params;\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n};\n\nstruct POOL_ctx_s;\n\ntypedef struct POOL_ctx_s ZSTD_threadPool;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\nstruct ZSTD_prefixDict_s {\n\tconst void *dict;\n\tsize_t dictSize;\n\tZSTD_dictContentType_e dictContentType;\n};\n\ntypedef struct ZSTD_prefixDict_s ZSTD_prefixDict;\n\nstruct ZSTD_CCtx_s {\n\tZSTD_compressionStage_e stage;\n\tint cParamsChanged;\n\tint bmi2;\n\tZSTD_CCtx_params requestedParams;\n\tZSTD_CCtx_params appliedParams;\n\tZSTD_CCtx_params simpleApiParams;\n\tU32 dictID;\n\tsize_t dictContentSize;\n\tZSTD_cwksp workspace;\n\tsize_t blockSizeMax;\n\tlong long unsigned int pledgedSrcSizePlusOne;\n\tlong long unsigned int consumedSrcSize;\n\tlong long unsigned int producedCSize;\n\tstruct xxh64_state xxhState;\n\tZSTD_customMem customMem;\n\tZSTD_threadPool *pool;\n\tsize_t staticSize;\n\tSeqCollector seqCollector;\n\tint isFirstBlock;\n\tint initialized;\n\tSeqStore_t seqStore;\n\tldmState_t ldmState;\n\trawSeq *ldmSequences;\n\tsize_t maxNbLdmSequences;\n\tRawSeqStore_t externSeqStore;\n\tZSTD_blockState_t blockState;\n\tvoid *tmpWorkspace;\n\tsize_t tmpWkspSize;\n\tZSTD_buffered_policy_e bufferedPolicy;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inToCompress;\n\tsize_t inBuffPos;\n\tsize_t inBuffTarget;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outBuffContentSize;\n\tsize_t outBuffFlushedSize;\n\tZSTD_cStreamStage streamStage;\n\tU32 frameEnded;\n\tZSTD_inBuffer expectedInBuffer;\n\tsize_t stableIn_notConsumed;\n\tsize_t expectedOutBufferSize;\n\tZSTD_localDict localDict;\n\tconst ZSTD_CDict *cdict;\n\tZSTD_prefixDict prefixDict;\n\tZSTD_blockSplitCtx blockSplitCtx;\n\tZSTD_Sequence *extSeqBuf;\n\tsize_t extSeqBufCapacity;\n};\n\ntypedef struct ZSTD_CCtx_s ZSTD_CCtx;\n\ntypedef ZSTD_CCtx ZSTD_CStream;\n\ntypedef ZSTD_CCtx zstd_cctx;\n\ntypedef ZSTD_CStream zstd_cstream;\n\nstruct ZSTD_CDict_s {\n\tconst void *dictContent;\n\tsize_t dictContentSize;\n\tZSTD_dictContentType_e dictContentType;\n\tU32 *entropyWorkspace;\n\tZSTD_cwksp workspace;\n\tZSTD_MatchState_t matchState;\n\tZSTD_compressedBlockState_t cBlockState;\n\tZSTD_customMem customMem;\n\tU32 dictID;\n\tint compressionLevel;\n\tZSTD_ParamSwitch_e useRowMatchFinder;\n};\n\ntypedef ZSTD_CDict zstd_cdict;\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct __ap_calc_ctrs {\n\tunsigned int apqns;\n\tunsigned int bound;\n};\n\nstruct subchannel_id {\n\t__u32 cssid: 8;\n\tchar: 4;\n\t__u32 m: 1;\n\t__u32 ssid: 2;\n\t__u32 one: 1;\n\t__u32 sch_no: 16;\n};\n\nstruct tpi_info {\n\tstruct subchannel_id schid;\n\tu32 intparm;\n\tu32 adapter_IO: 1;\n\tu32 directed_irq: 1;\n\tu32 isc: 3;\n\tshort: 11;\n\tchar: 1;\n\tu32 type: 3;\n};\n\nstruct pt_regs {\n\tunion {\n\t\tuser_pt_regs user_regs;\n\t\tstruct {\n\t\t\tlong unsigned int args[1];\n\t\t\tpsw_t psw;\n\t\t\tlong unsigned int gprs[16];\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int orig_gpr2;\n\t\tlong unsigned int monitor_code;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int int_code;\n\t\t\tunsigned int int_parm;\n\t\t\tlong unsigned int int_parm_long;\n\t\t};\n\t\tstruct tpi_info tpi_info;\n\t};\n\tlong unsigned int flags;\n\tlong unsigned int last_break;\n};\n\nstruct __arch_ftrace_regs {\n\tstruct pt_regs regs;\n};\n\nstruct __bridge_info {\n\t__u64 designated_root;\n\t__u64 bridge_id;\n\t__u32 root_path_cost;\n\t__u32 max_age;\n\t__u32 hello_time;\n\t__u32 forward_delay;\n\t__u32 bridge_max_age;\n\t__u32 bridge_hello_time;\n\t__u32 bridge_forward_delay;\n\t__u8 topology_change;\n\t__u8 topology_change_detected;\n\t__u8 root_port;\n\t__u8 stp_enabled;\n\t__u32 ageing_time;\n\t__u32 gc_interval;\n\t__u32 hello_timer_value;\n\t__u32 tcn_timer_value;\n\t__u32 topology_change_timer_value;\n\t__u32 gc_timer_value;\n};\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n\tu16 src;\n\tu16 dst;\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct idr;\n\nstruct __class_idr {\n\tstruct idr *idr;\n\tint id;\n};\n\ntypedef struct __class_idr class_idr_alloc_t;\n\nstruct __cmp_key {\n\tconst struct cpumask *cpus;\n\tstruct cpumask ***masks;\n\tint node;\n\tint cpu;\n\tint w;\n};\n\nstruct __debug_entry {\n\tlong unsigned int clock: 60;\n\tlong unsigned int exception: 1;\n\tlong unsigned int level: 3;\n\tvoid *caller;\n\tshort unsigned int cpu;\n} __attribute__((packed));\n\ntypedef struct __debug_entry debug_entry_t;\n\nstruct __fdb_entry {\n\t__u8 mac_addr[6];\n\t__u8 port_no;\n\t__u8 is_local;\n\t__u32 ageing_timer_value;\n\t__u8 port_hi;\n\t__u8 pad0;\n\t__u16 unused;\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nstruct tracepoint;\n\nstruct __find_tracepoint_cb_data {\n\tconst char *tp_name;\n\tstruct tracepoint *tpoint;\n\tstruct module *mod;\n};\n\nstruct __fs_path {\n\tchar *start;\n\tchar *end;\n\tchar *buf;\n\tshort unsigned int buf_len: 15;\n\tshort unsigned int reversed: 1;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct pmu;\n\nstruct cgroup;\n\nstruct __group_key {\n\tint cpu;\n\tstruct pmu *pmu;\n\tstruct cgroup *cgroup;\n};\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct sha512_block_state {\n\tu64 h[8];\n};\n\nstruct __sha512_ctx {\n\tstruct sha512_block_state state;\n\tu64 bytecount_lo;\n\tu64 bytecount_hi;\n\tu8 buf[128];\n};\n\nstruct __hmac_sha512_ctx {\n\tstruct __sha512_ctx sha_ctx;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __hmac_sha512_key {\n\tstruct sha512_block_state istate;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __ip6_tnl_parm {\n\tchar name[16];\n\tint link;\n\t__u8 proto;\n\t__u8 encap_limit;\n\t__u8 hop_limit;\n\tbool collect_md;\n\t__be32 flowinfo;\n\t__u32 flags;\n\tstruct in6_addr laddr;\n\tstruct in6_addr raddr;\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\t__u32 fwmark;\n\t__u32 index;\n\t__u8 erspan_ver;\n\t__u8 dir;\n\t__u16 hwid;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct __port_info {\n\t__u64 designated_root;\n\t__u64 designated_bridge;\n\t__u16 port_id;\n\t__u16 designated_port;\n\t__u32 path_cost;\n\t__u32 designated_cost;\n\t__u8 state;\n\t__u8 top_change_ack;\n\t__u8 config_pending;\n\t__u8 unused0;\n\t__u32 message_age_timer_value;\n\t__u32 forward_delay_timer_value;\n\t__u32 hold_timer_value;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct net_device;\n\nstruct __rt6_probe_work {\n\tstruct work_struct work;\n\tstruct in6_addr target;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n};\n\nstruct sha3_state {\n\tunion {\n\t\t__le64 words[25];\n\t\tu8 bytes[200];\n\t\tu64 native_words[25];\n\t};\n};\n\nstruct __sha3_ctx {\n\tstruct sha3_state state;\n\tu8 digest_size;\n\tu8 block_size;\n\tu8 absorb_offset;\n\tu8 squeeze_offset;\n};\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[8];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[8];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct dentry;\n\nstruct __track_dentry_update_args {\n\tstruct dentry *dentry;\n\tint op;\n};\n\nstruct __track_range_args {\n\text4_lblk_t start;\n\text4_lblk_t end;\n};\n\nstruct inode;\n\nstruct __uprobe_key {\n\tstruct inode *inode;\n\tloff_t offset;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct __va_list_tag {\n\tlong int __gpr;\n\tlong int __fpr;\n\tvoid *__overflow_arg_area;\n\tvoid *__reg_save_area;\n};\n\ntypedef __builtin_va_list va_list;\n\nstruct __xfsstats {\n\tuint32_t xs_allocx;\n\tuint32_t xs_allocb;\n\tuint32_t xs_freex;\n\tuint32_t xs_freeb;\n\tuint32_t xs_abt_lookup;\n\tuint32_t xs_abt_compare;\n\tuint32_t xs_abt_insrec;\n\tuint32_t xs_abt_delrec;\n\tuint32_t xs_blk_mapr;\n\tuint32_t xs_blk_mapw;\n\tuint32_t xs_blk_unmap;\n\tuint32_t xs_add_exlist;\n\tuint32_t xs_del_exlist;\n\tuint32_t xs_look_exlist;\n\tuint32_t xs_cmp_exlist;\n\tuint32_t xs_bmbt_lookup;\n\tuint32_t xs_bmbt_compare;\n\tuint32_t xs_bmbt_insrec;\n\tuint32_t xs_bmbt_delrec;\n\tuint32_t xs_dir_lookup;\n\tuint32_t xs_dir_create;\n\tuint32_t xs_dir_remove;\n\tuint32_t xs_dir_getdents;\n\tuint32_t xs_trans_sync;\n\tuint32_t xs_trans_async;\n\tuint32_t xs_trans_empty;\n\tuint32_t xs_ig_attempts;\n\tuint32_t xs_ig_found;\n\tuint32_t xs_ig_frecycle;\n\tuint32_t xs_ig_missed;\n\tuint32_t xs_ig_dup;\n\tuint32_t xs_ig_reclaims;\n\tuint32_t xs_ig_attrchg;\n\tuint32_t xs_log_writes;\n\tuint32_t xs_log_blocks;\n\tuint32_t xs_log_noiclogs;\n\tuint32_t xs_log_force;\n\tuint32_t xs_log_force_sleep;\n\tuint32_t xs_try_logspace;\n\tuint32_t xs_sleep_logspace;\n\tuint32_t xs_push_ail;\n\tuint32_t xs_push_ail_success;\n\tuint32_t xs_push_ail_pushbuf;\n\tuint32_t xs_push_ail_pinned;\n\tuint32_t xs_push_ail_locked;\n\tuint32_t xs_push_ail_flushing;\n\tuint32_t xs_push_ail_restarts;\n\tuint32_t xs_push_ail_flush;\n\tuint32_t xs_xstrat_quick;\n\tuint32_t xs_xstrat_split;\n\tuint32_t xs_write_calls;\n\tuint32_t xs_read_calls;\n\tuint32_t xs_attr_get;\n\tuint32_t xs_attr_set;\n\tuint32_t xs_attr_remove;\n\tuint32_t xs_attr_list;\n\tuint32_t xs_iflush_count;\n\tuint32_t xs_icluster_flushcnt;\n\tuint32_t xs_icluster_flushinode;\n\tuint32_t xs_inodes_active;\n\tuint32_t __unused_vn_alloc;\n\tuint32_t __unused_vn_get;\n\tuint32_t __unused_vn_hold;\n\tuint32_t xs_inode_destroy;\n\tuint32_t xs_inode_destroy2;\n\tuint32_t xs_inode_mark_reclaimable;\n\tuint32_t __unused_vn_free;\n\tuint32_t xb_get;\n\tuint32_t xb_create;\n\tuint32_t xb_get_locked;\n\tuint32_t xb_get_locked_waited;\n\tuint32_t xb_busy_locked;\n\tuint32_t xb_miss_locked;\n\tuint32_t xb_page_retries;\n\tuint32_t xb_page_found;\n\tuint32_t xb_get_read;\n\tuint32_t xs_abtb_2[15];\n\tuint32_t xs_abtc_2[15];\n\tuint32_t xs_bmbt_2[15];\n\tuint32_t xs_ibt_2[15];\n\tuint32_t xs_fibt_2[15];\n\tuint32_t xs_rmap_2[15];\n\tuint32_t xs_refcbt_2[15];\n\tuint32_t xs_rmap_mem_2[15];\n\tuint32_t xs_rcbag_2[15];\n\tuint32_t xs_rtrmap_2[15];\n\tuint32_t xs_rtrmap_mem_2[15];\n\tuint32_t xs_rtrefcbt_2[15];\n\tuint32_t xs_qm_dqreclaims;\n\tuint32_t xs_qm_dqreclaim_misses;\n\tuint32_t xs_qm_dquot_dups;\n\tuint32_t xs_qm_dqcachemisses;\n\tuint32_t xs_qm_dqcachehits;\n\tuint32_t xs_qm_dqwants;\n\tuint32_t xs_qm_dquot;\n\tuint32_t xs_qm_dquot_unused;\n\tuint32_t xs_gc_read_calls;\n\tuint32_t xs_gc_write_calls;\n\tuint32_t xs_gc_zone_reset_calls;\n\tuint32_t xs_inodes_meta;\n\tuint64_t xs_xstrat_bytes;\n\tuint64_t xs_write_bytes;\n\tuint64_t xs_read_bytes;\n\tuint64_t xs_defer_relog;\n\tuint64_t xs_gc_bytes;\n};\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nstruct jump_entry;\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct _ddebug {\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n\tconst char *format;\n\tunsigned int lineno: 18;\n\tunsigned int class_id: 6;\n\tunsigned int flags: 8;\n\tunion {\n\t\tstruct static_key_true dd_key_true;\n\t\tstruct static_key_false dd_key_false;\n\t} key;\n};\n\nstruct ddebug_class_map;\n\nstruct _ddebug_info {\n\tstruct _ddebug *descs;\n\tstruct ddebug_class_map *classes;\n\tunsigned int num_descs;\n\tunsigned int num_classes;\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n} __attribute__((packed));\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct kvm_stats_desc {\n\t__u32 flags;\n\t__s16 exponent;\n\t__u16 size;\n\t__u32 offset;\n\t__u32 bucket_size;\n\tchar name[0];\n};\n\nstruct _kvm_stats_desc {\n\tstruct kvm_stats_desc desc;\n\tchar name[48];\n};\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct _qeth_sbp_cbctl {\n\tunion {\n\t\tu32 supported;\n\t\tstruct {\n\t\t\tenum qeth_sbp_roles *role;\n\t\t\tenum qeth_sbp_states *state;\n\t\t} qports;\n\t} data;\n};\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct ac6_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct access_coordinate {\n\tunsigned int read_bandwidth;\n\tunsigned int write_bandwidth;\n\tunsigned int read_latency;\n\tunsigned int write_latency;\n};\n\nstruct access_masks {\n\taccess_mask_t fs: 16;\n\taccess_mask_t net: 2;\n\taccess_mask_t scope: 2;\n};\n\nunion access_masks_all {\n\tstruct access_masks masks;\n\tu32 all;\n};\n\nstruct access_regs {\n\tunsigned int regs[16];\n};\n\nstruct acct_v3 {\n\tchar ac_flag;\n\tchar ac_version;\n\t__u16 ac_tty;\n\t__u32 ac_exitcode;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u32 ac_etime;\n\tcomp_t ac_utime;\n\tcomp_t ac_stime;\n\tcomp_t ac_mem;\n\tcomp_t ac_io;\n\tcomp_t ac_rw;\n\tcomp_t ac_minflt;\n\tcomp_t ac_majflt;\n\tcomp_t ac_swaps;\n\tchar ac_comm[16];\n};\n\ntypedef struct acct_v3 acct_t;\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n};\n\nstruct comp_alg_common {\n\tstruct crypto_alg base;\n};\n\nstruct acomp_req;\n\nstruct crypto_acomp;\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\ntypedef void (*crypto_completion_t)(void *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n\tunsigned int dma_length;\n\tunsigned int dma_flags;\n};\n\nstruct acomp_req_chain {\n\tcrypto_completion_t compl;\n\tvoid *data;\n\tstruct scatterlist ssg;\n\tstruct scatterlist dsg;\n\tunion {\n\t\tconst u8 *src;\n\t\tstruct folio *sfolio;\n\t};\n\tunion {\n\t\tu8 *dst;\n\t\tstruct folio *dfolio;\n\t};\n\tu32 flags;\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tunion {\n\t\tstruct scatterlist *dst;\n\t\tu8 *dvirt;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct acomp_req_chain chain;\n\tvoid *__ctx[0];\n};\n\nunion crypto_no_such_thing;\n\nstruct scatter_walk {\n\tunion {\n\t\tvoid * const addr;\n\t\tunion crypto_no_such_thing *__addr;\n\t};\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct acomp_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tint flags;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct action_cache {\n\tlong unsigned int allow_native[8];\n};\n\nstruct hist_trigger_data;\n\nstruct tracing_map_elt;\n\nstruct trace_buffer;\n\nstruct ring_buffer_event;\n\nstruct action_data;\n\ntypedef void (*action_fn_t)(struct hist_trigger_data *, struct tracing_map_elt *, struct trace_buffer *, void *, struct ring_buffer_event *, void *, struct action_data *, u64 *);\n\ntypedef bool (*check_track_val_fn_t)(u64, u64);\n\nstruct synth_event;\n\nstruct hist_field;\n\nstruct action_data {\n\tenum handler_id handler;\n\tenum action_id action;\n\tchar *action_name;\n\taction_fn_t fn;\n\tunsigned int n_params;\n\tchar *params[64];\n\tunsigned int var_ref_idx[64];\n\tstruct synth_event *synth_event;\n\tbool use_trace_keyword;\n\tchar *synth_event_name;\n\tunion {\n\t\tstruct {\n\t\t\tchar *event;\n\t\t\tchar *event_system;\n\t\t} match_data;\n\t\tstruct {\n\t\t\tchar *var_str;\n\t\t\tstruct hist_field *var_ref;\n\t\t\tstruct hist_field *track_var;\n\t\t\tcheck_track_val_fn_t check_val;\n\t\t\taction_fn_t save_data;\n\t\t} track_data;\n\t};\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct action_gate_entry {\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n};\n\nstruct addr_marker {\n\tint is_start;\n\tlong unsigned int start_address;\n\tlong unsigned int size;\n\tconst char *name;\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct rb_node;\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct file;\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct addrtype {\n\tchar _[16];\n};\n\nstruct addrtype___2 {\n\tchar _[24];\n};\n\nstruct addrtype___3 {\n\tchar _[32];\n};\n\nstruct addrtype___4 {\n\tchar _[128];\n};\n\nstruct addrtype___5 {\n\tchar _[256];\n};\n\nstruct audit_ntp_val {\n\tlong long int oldval;\n\tlong long int newval;\n};\n\nstruct audit_ntp_data {\n\tstruct audit_ntp_val vals[6];\n};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n};\n\nstruct advisor_ctx {\n\tktime_t start_scan;\n\tlong unsigned int scan_time;\n\tlong unsigned int change;\n\tlong long unsigned int cpu_time;\n};\n\nstruct crypto_aead;\n\nstruct aead_request;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tstruct crypto_alg base;\n};\n\nstruct aead_geniv_ctx {\n\tspinlock_t lock;\n\tstruct crypto_aead *child;\n\tu8 salt[0];\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tvoid *__ctx[0];\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tvoid *__ctx[0];\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct aead_testvec {\n\tconst char *key;\n\tconst char *iv;\n\tconst char *ptext;\n\tconst char *assoc;\n\tconst char *ctext;\n\tunsigned char novrfy;\n\tunsigned char wk;\n\tunsigned char klen;\n\tunsigned int plen;\n\tunsigned int clen;\n\tunsigned int alen;\n\tint setkey_error;\n\tint setauthsize_error;\n\tint crypt_error;\n};\n\nstruct test_sg_division {\n\tunsigned int proportion_of_total;\n\tunsigned int offset;\n\tbool offset_relative_to_alignmask;\n\tenum flush_type flush_type;\n\tbool nosimd;\n};\n\nstruct testvec_config {\n\tconst char *name;\n\tenum inplace_mode inplace_mode;\n\tu32 req_flags;\n\tstruct test_sg_division src_divs[8];\n\tstruct test_sg_division dst_divs[8];\n\tunsigned int iv_offset;\n\tunsigned int key_offset;\n\tbool iv_offset_relative_to_alignmask;\n\tbool key_offset_relative_to_alignmask;\n\tenum finalization_type finalization_type;\n\tbool nosimd;\n\tbool nosimd_setkey;\n};\n\nstruct alg_test_desc;\n\nstruct cipher_test_sglists;\n\nstruct aead_slow_tests_ctx {\n\tstruct rnd_state rng;\n\tstruct aead_request *req;\n\tstruct crypto_aead *tfm;\n\tconst struct alg_test_desc *test_desc;\n\tstruct cipher_test_sglists *tsgls;\n\tunsigned int maxdatasize;\n\tunsigned int maxkeysize;\n\tstruct aead_testvec vec;\n\tchar vec_name[64];\n\tchar cfgname[192];\n\tstruct testvec_config cfg;\n};\n\nstruct aead_test_suite {\n\tconst struct aead_testvec *vecs;\n\tunsigned int count;\n\tunsigned int einval_allowed: 1;\n\tunsigned int aad_iv: 1;\n};\n\nunion aes_enckey_arch {\n\tu32 rndkeys[60];\n\tu8 raw_key[32];\n};\n\nstruct aes_enckey {\n\tu32 len;\n\tu32 nrounds;\n\tu32 padding[2];\n\tunion aes_enckey_arch k;\n};\n\nunion aes_invkey_arch {\n\tu32 inv_rndkeys[60];\n};\n\nstruct aes_key {\n\tstruct aes_enckey;\n\tunion aes_invkey_arch inv_k;\n};\n\nstruct iucv_message {\n\tu32 id;\n\tu32 audit;\n\tu32 class;\n\tu32 tag;\n\tu32 length;\n\tu32 reply_size;\n\tu8 rmmsg[8];\n\tu8 flags;\n} __attribute__((packed));\n\nstruct af_iucv_trans_hdr {\n\tu16 magic;\n\tu8 version;\n\tu8 flags;\n\tu16 window;\n\tchar destNodeID[8];\n\tchar destUserID[8];\n\tchar destAppName[16];\n\tchar srcNodeID[8];\n\tchar srcUserID[8];\n\tchar srcAppName[16];\n\tstruct iucv_message iucv_hdr;\n\tu8 pad;\n};\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\nstruct aggregate_control {\n\tlong int *aggregate;\n\tlong int *local;\n\tlong int *pending;\n\tlong int *ppending;\n\tlong int *cstat;\n\tlong int *cstat_prev;\n\tint size;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct xfs_btree_ops;\n\nstruct aghdr_init_data {\n\txfs_agblock_t agno;\n\txfs_extlen_t agsize;\n\tstruct list_head buffer_list;\n\txfs_rfsblock_t nfree;\n\txfs_daddr_t daddr;\n\tsize_t numblks;\n\tconst struct xfs_btree_ops *bc_ops;\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request;\n\nstruct crypto_ahash;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*export_core)(struct ahash_request *, void *);\n\tint (*import_core)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_ahash *);\n\tvoid (*exit_tfm)(struct crypto_ahash *);\n\tint (*clone_tfm)(struct crypto_ahash *, struct crypto_ahash *);\n\tstruct hash_alg_common halg;\n};\n\nstruct ahash_hmac_ctx {\n\tstruct crypto_ahash *hash;\n\tu8 pads[0];\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[112];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tu8 *result;\n\tstruct scatterlist sg_head[2];\n\tcrypto_completion_t saved_complete;\n\tvoid *saved_data;\n\tvoid *__ctx[0];\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct eventfd_ctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n};\n\nstruct airq_struct {\n\tstruct hlist_node list;\n\tvoid (*handler)(struct airq_struct *, struct tpi_info *);\n\tu8 *lsi_ptr;\n\tu8 isc;\n\tu8 flags;\n};\n\nstruct airq_iv;\n\nstruct airq_info {\n\trwlock_t lock;\n\tu8 summary_indicator_idx;\n\tstruct airq_struct airq;\n\tstruct airq_iv *aiv;\n};\n\nstruct airq_iv {\n\tlong unsigned int *vector;\n\tdma_addr_t vector_dma;\n\tlong unsigned int *avail;\n\tlong unsigned int *bitlock;\n\tlong unsigned int *ptr;\n\tunsigned int *data;\n\tlong unsigned int bits;\n\tlong unsigned int end;\n\tlong unsigned int flags;\n\tspinlock_t lock;\n};\n\nstruct akcipher_request;\n\nstruct crypto_akcipher;\n\nstruct akcipher_alg {\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[56];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct akcipher_testvec;\n\nstruct akcipher_test_suite {\n\tconst struct akcipher_testvec *vecs;\n\tunsigned int count;\n};\n\nstruct akcipher_testvec {\n\tconst unsigned char *key;\n\tconst unsigned char *m;\n\tconst unsigned char *c;\n\tunsigned int key_len;\n\tunsigned int m_size;\n\tunsigned int c_size;\n\tbool public_key_vec;\n};\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct cipher_testvec;\n\nstruct cipher_test_suite {\n\tconst struct cipher_testvec *vecs;\n\tunsigned int count;\n};\n\nstruct comp_testvec;\n\nstruct comp_test_suite {\n\tstruct {\n\t\tconst struct comp_testvec *vecs;\n\t\tunsigned int count;\n\t} comp;\n\tstruct {\n\t\tconst struct comp_testvec *vecs;\n\t\tunsigned int count;\n\t} decomp;\n};\n\nstruct hash_testvec;\n\nstruct hash_test_suite {\n\tconst struct hash_testvec *vecs;\n\tunsigned int count;\n};\n\nstruct drbg_testvec;\n\nstruct drbg_test_suite {\n\tconst struct drbg_testvec *vecs;\n\tunsigned int count;\n};\n\nstruct sig_testvec;\n\nstruct sig_test_suite {\n\tconst struct sig_testvec *vecs;\n\tunsigned int count;\n};\n\nstruct kpp_testvec;\n\nstruct kpp_test_suite {\n\tconst struct kpp_testvec *vecs;\n\tunsigned int count;\n};\n\nstruct alg_test_desc {\n\tconst char *alg;\n\tconst char *generic_driver;\n\tint (*test)(const struct alg_test_desc *, const char *, u32, u32);\n\tint fips_allowed;\n\tunion {\n\t\tstruct aead_test_suite aead;\n\t\tstruct cipher_test_suite cipher;\n\t\tstruct comp_test_suite comp;\n\t\tstruct hash_test_suite hash;\n\t\tstruct drbg_test_suite drbg;\n\t\tstruct akcipher_test_suite akcipher;\n\t\tstruct sig_test_suite sig;\n\t\tstruct kpp_test_suite kpp;\n\t} suite;\n};\n\nstruct dasd_uid {\n\t__u8 type;\n\tchar vendor[4];\n\tchar serial[15];\n\t__u16 ssid;\n\t__u8 real_unit_addr;\n\t__u8 base_unit_addr;\n\tchar vduit[33];\n};\n\nstruct dasd_device;\n\nstruct summary_unit_check_work_data {\n\tchar reason;\n\tstruct dasd_device *device;\n\tstruct work_struct worker;\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct read_uac_work_data {\n\tstruct dasd_device *device;\n\tstruct delayed_work dwork;\n};\n\nstruct dasd_unit_address_configuration;\n\nstruct dasd_ccw_req;\n\nstruct alias_lcu {\n\tstruct list_head lcu;\n\tstruct dasd_uid uid;\n\tenum pavtype pav;\n\tchar flags;\n\tspinlock_t lock;\n\tstruct list_head grouplist;\n\tstruct list_head active_devices;\n\tstruct list_head inactive_devices;\n\tstruct dasd_unit_address_configuration *uac;\n\tstruct summary_unit_check_work_data suc_data;\n\tstruct read_uac_work_data ruac_data;\n\tstruct dasd_ccw_req *rsu_cqr;\n\tstruct completion lcu_setup;\n};\n\nstruct alias_pav_group {\n\tstruct list_head group;\n\tstruct dasd_uid uid;\n\tstruct alias_lcu *lcu;\n\tstruct list_head baselist;\n\tstruct list_head aliaslist;\n\tstruct dasd_device *next;\n};\n\nstruct alias_root {\n\tstruct list_head serverlist;\n\tspinlock_t lock;\n};\n\nstruct alias_server {\n\tstruct list_head server;\n\tstruct dasd_uid uid;\n\tstruct list_head lculist;\n};\n\nstruct btrfs_space_info;\n\nstruct alloc_chunk_ctl {\n\tu64 start;\n\tu64 type;\n\tint num_stripes;\n\tint sub_stripes;\n\tint dev_stripes;\n\tint devs_max;\n\tint devs_min;\n\tint devs_increment;\n\tint ncopies;\n\tint nparity;\n\tu64 max_stripe_size;\n\tu64 max_chunk_size;\n\tu64 dev_extent_min;\n\tu64 stripe_size;\n\tu64 chunk_size;\n\tint ndevs;\n\tstruct btrfs_space_info *space_info;\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alt_debug {\n\tlong unsigned int facilities[16];\n\tlong unsigned int mfeatures[1];\n\tint spec;\n};\n\nstruct alt_instr {\n\ts32 instr_offset;\n\ts32 repl_offset;\n\tunion {\n\t\tu32 feature;\n\t\tstruct {\n\t\t\tu32 ctx: 4;\n\t\t\tu32 type: 8;\n\t\t\tu32 data: 20;\n\t\t};\n\t};\n\tu8 instrlen;\n} __attribute__((packed));\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct dev_pm_ops;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct device_attribute;\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct vm_area_struct;\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct arqb {\n\tu64 data;\n\tu16 fmt: 4;\n\tu16 cmd_code;\n\tshort: 16;\n\tu16 msb_count;\n\tu32 reserved[12];\n};\n\nstruct arsb {\n\tu16 fmt: 4;\n\tint: 0;\n\tu8 ef;\n\tshort: 0;\n\tu8 ecbi;\n\tlong: 0;\n\tu8 fvf;\n\tshort: 0;\n\tchar: 8;\n\tu8 eqc;\n\tu64 fail_msb;\n\tu64 fail_aidaw;\n\tu64 fail_ms;\n\tu64 fail_scm;\n\tu32 reserved[4];\n};\n\nstruct msb {\n\tu8 fmt: 4;\n\tu8 oc: 4;\n\tu8 flags;\n\tshort: 12;\n\tu16 bs: 4;\n\tu32 blk_count;\n\tdma64_t data_addr;\n\tu64 scm_addr;\n\tlong: 64;\n};\n\nstruct aob {\n\tstruct arqb request;\n\tstruct arsb response;\n\tstruct msb msb[124];\n};\n\nstruct scm_device;\n\nstruct aob_rq_header {\n\tstruct scm_device *scmdev;\n\tchar data[0];\n};\n\nstruct ap_device {\n\tstruct device device;\n\tint device_type;\n\tconst char *driver_override;\n};\n\nstruct ap_tapq_hwinfo {\n\tunion {\n\t\tlong unsigned int value;\n\t\tstruct {\n\t\t\tunsigned int fac: 32;\n\t\t\tunsigned int apinfo: 32;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int apsc: 1;\n\t\t\tunsigned int mex4k: 1;\n\t\t\tunsigned int crt4k: 1;\n\t\t\tunsigned int cca: 1;\n\t\t\tunsigned int accel: 1;\n\t\t\tunsigned int ep11: 1;\n\t\t\tunsigned int apxa: 1;\n\t\t\tunsigned int slcf: 1;\n\t\t\tunsigned int class: 8;\n\t\t\tunsigned int bs: 2;\n\t\t\tint: 14;\n\t\t\tunsigned int at: 8;\n\t\t\tunsigned int nd: 8;\n\t\t\tchar: 4;\n\t\t\tunsigned int ml: 4;\n\t\t\tchar: 4;\n\t\t\tunsigned int qd: 4;\n\t\t};\n\t};\n};\n\nstruct ap_card {\n\tstruct ap_device ap_dev;\n\tstruct ap_tapq_hwinfo hwinfo;\n\tint id;\n\tunsigned int maxmsgsize;\n\tbool config;\n\tbool chkstop;\n\tatomic64_t total_request_count;\n};\n\nstruct sccb_header {\n\tu16 length;\n\tu8 function_code;\n\tu8 control_mask[3];\n\tu16 response_code;\n};\n\nstruct ap_cfg_sccb {\n\tstruct sccb_header header;\n};\n\nstruct ap_config_info {\n\tunion {\n\t\tunsigned int flags;\n\t\tstruct {\n\t\t\tunsigned int apsc: 1;\n\t\t\tunsigned int apxa: 1;\n\t\t\tunsigned int qact: 1;\n\t\t\tunsigned int rc8a: 1;\n\t\t\tchar: 4;\n\t\t\tunsigned int apsb: 1;\n\t\t};\n\t};\n\tunsigned char na;\n\tunsigned char nd;\n\tunsigned char _reserved0[10];\n\tunsigned int apm[8];\n\tunsigned int aqm[8];\n\tunsigned int adm[8];\n\tunsigned char _reserved1[16];\n};\n\nstruct ap_device_id {\n\t__u16 match_flags;\n\t__u8 dev_type;\n\tkernel_ulong_t driver_info;\n};\n\nstruct of_device_id;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct ap_driver {\n\tstruct device_driver driver;\n\tstruct ap_device_id *ids;\n\tunsigned int flags;\n\tint (*probe)(struct ap_device *);\n\tvoid (*remove)(struct ap_device *);\n\tint (*in_use)(long unsigned int *, long unsigned int *);\n\tvoid (*on_config_changed)(struct ap_config_info *, struct ap_config_info *);\n\tvoid (*on_scan_complete)(struct ap_config_info *, struct ap_config_info *);\n};\n\nstruct ap_response_type {\n\tstruct completion work;\n\tint type;\n};\n\nstruct ap_queue;\n\nstruct ap_message {\n\tstruct list_head list;\n\tlong unsigned int psmid;\n\tvoid *msg;\n\tsize_t len;\n\tsize_t bufsize;\n\tu16 flags;\n\tint rc;\n\tstruct ap_response_type response;\n\tvoid (*receive)(struct ap_queue *, struct ap_message *, struct ap_message *);\n};\n\nstruct ap_perms {\n\tlong unsigned int ioctlm[4];\n\tlong unsigned int apm[4];\n\tlong unsigned int aqm[4];\n\tlong unsigned int adm[4];\n};\n\nunion ap_qact_ap_info {\n\tlong unsigned int val;\n\tstruct {\n\t\tchar: 3;\n\t\tunsigned int mode: 3;\n\t\tint: 26;\n\t\tunsigned int cat: 8;\n\t\tshort: 0;\n\t\tunsigned char ver[2];\n\t};\n};\n\nunion ap_qirq_ctrl {\n\tlong unsigned int value;\n\tstruct {\n\t\tchar: 8;\n\t\tunsigned int zone: 8;\n\t\tunsigned int ir: 1;\n\t\tchar: 4;\n\t\tunsigned int gisc: 3;\n\t\tchar: 6;\n\t\tunsigned int gf: 2;\n\t\tchar: 1;\n\t\tunsigned int gisa: 27;\n\t\tchar: 1;\n\t\tunsigned int isc: 3;\n\t};\n};\n\nstruct ap_queue {\n\tstruct ap_device ap_dev;\n\tstruct hlist_node hnode;\n\tstruct ap_card *card;\n\tspinlock_t lock;\n\tenum ap_dev_state dev_state;\n\tbool config;\n\tbool chkstop;\n\tap_qid_t qid;\n\tunsigned int se_bstate;\n\tunsigned int assoc_idx;\n\tint queue_count;\n\tint pendingq_count;\n\tint requestq_count;\n\tu64 total_request_count;\n\tint request_timeout;\n\tstruct timer_list timeout;\n\tstruct list_head pendingq;\n\tstruct list_head requestq;\n\tstruct ap_message *reply;\n\tenum ap_sm_state sm_state;\n\tint rapq_fbit;\n\tint last_err_rc;\n};\n\nstruct ap_queue_status {\n\tunion {\n\t\tunsigned int value: 32;\n\t\tstruct {\n\t\t\tunsigned int status_bits: 8;\n\t\t\tunsigned int rc: 8;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int queue_empty: 1;\n\t\t\tunsigned int replies_waiting: 1;\n\t\t\tunsigned int queue_full: 1;\n\t\t\tchar: 3;\n\t\t\tunsigned int async: 1;\n\t\t\tunsigned int irq_enabled: 1;\n\t\t\tunsigned int response_code: 8;\n\t\t};\n\t};\n};\n\nunion ap_queue_status_reg {\n\tlong unsigned int value;\n\tstruct {\n\t\tu32 _pad;\n\t\tstruct ap_queue_status status;\n\t};\n};\n\nstruct ctl_table_header;\n\nstruct ctl_table;\n\nstruct appldata_ops {\n\tstruct list_head list;\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table *ctl_table;\n\tint active;\n\tchar name[16];\n\tunsigned char record_nr;\n\tvoid (*callback)(void *);\n\tvoid *data;\n\tunsigned int size;\n\tstruct module *owner;\n\tchar mod_lvl[2];\n};\n\nstruct appldata_parameter_list {\n\tu16 diag;\n\tu8 function;\n\tu8 parlist_length;\n\tu32 unused01;\n\tu16 reserved;\n\tu16 buffer_length;\n\tu32 unused02;\n\tu64 product_id_addr;\n\tu64 buffer_addr;\n};\n\nstruct appldata_product_id {\n\tchar prod_nr[7];\n\tu16 prod_fn;\n\tu8 record_nr;\n\tu16 version_nr;\n\tu16 release_nr;\n\tu16 mod_lvl;\n} __attribute__((packed));\n\nstruct page;\n\nstruct apply_range_data {\n\tstruct page **pages;\n\tint i;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct arch_elf_state {};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct arch_msi_msg_addr_hi {\n\tu32 address_hi;\n};\n\ntypedef struct arch_msi_msg_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct arch_msi_msg_addr_lo {\n\tu32 address_lo;\n};\n\ntypedef struct arch_msi_msg_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct arch_msi_msg_data {\n\tu32 data;\n};\n\ntypedef struct arch_msi_msg_data arch_msi_msg_data_t;\n\nstruct arch_specific_insn {\n\tkprobe_opcode_t *insn;\n};\n\nstruct arch_uprobe {\n\tunion {\n\t\tuprobe_opcode_t insn[3];\n\t\tuprobe_opcode_t ixol[3];\n\t};\n\tunsigned int saved_per: 1;\n\tunsigned int saved_int_code;\n};\n\nstruct arch_uprobe_task {};\n\nstruct arch_va_list {\n\tlong int __gpr;\n\tlong int __fpr;\n\tvoid *__overflow_arg_area;\n\tvoid *__reg_save_area;\n};\n\nstruct arch_vdso_time_data {\n\t__s64 tod_delta;\n};\n\nstruct arena_free_span {\n\tstruct llist_node node;\n\tlong unsigned int uaddr;\n\tu32 page_cnt;\n};\n\nstruct arg_dev_net_ip {\n\tstruct net *net;\n\tstruct in6_addr *addr;\n};\n\nstruct arg_netdev_event {\n\tconst struct net_device *dev;\n\tunion {\n\t\tunsigned char nh_flags;\n\t\tlong unsigned int event;\n\t};\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct trace_array;\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tu64 time_start;\n\tint cpu;\n};\n\ntypedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t);\n\nstruct asn1_decoder {\n\tconst unsigned char *machine;\n\tsize_t machlen;\n\tconst asn1_action_t *actions;\n};\n\nstruct assign_storage_sccb {\n\tstruct sccb_header header;\n\tu16 rn;\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct asymmetric_key_id {\n\tshort unsigned int len;\n\tunsigned char data[0];\n};\n\nstruct asymmetric_key_ids {\n\tvoid *id[3];\n};\n\nstruct key_preparsed_payload;\n\nstruct asymmetric_key_parser {\n\tstruct list_head link;\n\tstruct module *owner;\n\tconst char *name;\n\tint (*parse)(struct key_preparsed_payload *);\n};\n\nstruct key;\n\nstruct seq_file;\n\nstruct kernel_pkey_params;\n\nstruct kernel_pkey_query;\n\nstruct public_key_signature;\n\nstruct asymmetric_key_subtype {\n\tstruct module *owner;\n\tconst char *name;\n\tshort unsigned int name_len;\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tvoid (*destroy)(void *, void *);\n\tint (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*verify_signature)(const struct key *, const struct public_key_signature *);\n};\n\nstruct btrfs_work;\n\ntypedef void (*btrfs_func_t)(struct btrfs_work *);\n\ntypedef void (*btrfs_ordered_func_t)(struct btrfs_work *, bool);\n\nstruct btrfs_workqueue;\n\nstruct btrfs_work {\n\tbtrfs_func_t func;\n\tbtrfs_ordered_func_t ordered_func;\n\tstruct work_struct normal_work;\n\tstruct list_head ordered_list;\n\tstruct btrfs_workqueue *wq;\n\tlong unsigned int flags;\n};\n\nstruct btrfs_inode;\n\nstruct cgroup_subsys_state;\n\nstruct async_cow;\n\nstruct async_chunk {\n\tstruct btrfs_inode *inode;\n\tstruct folio *locked_folio;\n\tu64 start;\n\tu64 end;\n\tblk_opf_t write_flags;\n\tstruct list_head extents;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct btrfs_work work;\n\tstruct async_cow *async_cow;\n};\n\nstruct async_cow {\n\tatomic_t num_chunks;\n\tstruct async_chunk chunks[0];\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n};\n\nstruct compressed_bio;\n\nstruct async_extent {\n\tu64 start;\n\tu64 ram_size;\n\tstruct compressed_bio *cb;\n\tstruct list_head list;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct btrfs_device;\n\nstruct btrfs_io_context;\n\nstruct btrfs_io_stripe {\n\tstruct btrfs_device *dev;\n\tu64 physical;\n\tbool rst_search_commit_root;\n\tstruct btrfs_io_context *bioc;\n};\n\nstruct btrfs_bio;\n\nstruct async_submit_bio {\n\tstruct btrfs_bio *bbio;\n\tstruct btrfs_io_context *bioc;\n\tstruct btrfs_io_stripe smap;\n\tint mirror_num;\n\tstruct btrfs_work work;\n};\n\nstruct notifier_block;\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct attach_storage_sccb {\n\tstruct sccb_header header;\n\tshort: 16;\n\tu16 assigned;\n\tlong: 0;\n\tu32 entries[0];\n};\n\nstruct attr {\n\tu32 flags;\n};\n\nstruct attrib_data_t {\n\tunsigned char operation: 3;\n\tunsigned char reserved: 5;\n\t__u16 nr_cyl;\n\t__u8 reserved2[29];\n} __attribute__((packed));\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct bin_attribute;\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct audit_aux_data {\n\tstruct audit_aux_data *next;\n\tint type;\n};\n\nstruct audit_cap_data {\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n\tunion {\n\t\tunsigned int fE;\n\t\tkernel_cap_t effective;\n\t};\n\tkernel_cap_t ambient;\n\tkuid_t rootid;\n};\n\nstruct audit_aux_data_bprm_fcaps {\n\tstruct audit_aux_data d;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tstruct audit_cap_data old_pcap;\n\tstruct audit_cap_data new_pcap;\n};\n\nstruct lsm_prop_selinux {\n\tu32 secid;\n};\n\nstruct lsm_prop_smack {};\n\nstruct lsm_prop_apparmor {};\n\nstruct lsm_prop_bpf {\n\tu32 secid;\n};\n\nstruct lsm_prop {\n\tstruct lsm_prop_selinux selinux;\n\tstruct lsm_prop_smack smack;\n\tstruct lsm_prop_apparmor apparmor;\n\tstruct lsm_prop_bpf bpf;\n};\n\nstruct audit_aux_data_pids {\n\tstruct audit_aux_data d;\n\tpid_t target_pid[16];\n\tkuid_t target_auid[16];\n\tkuid_t target_uid[16];\n\tunsigned int target_sessionid[16];\n\tstruct lsm_prop target_ref[16];\n\tchar target_comm[256];\n\tint pid_count;\n};\n\nstruct audit_stamp {\n\tstruct timespec64 ctime;\n\tunsigned int serial;\n};\n\nstruct audit_context;\n\nstruct audit_buffer {\n\tstruct sk_buff *skb;\n\tstruct sk_buff_head skb_list;\n\tstruct audit_context *ctx;\n\tstruct audit_stamp stamp;\n\tgfp_t gfp_mask;\n};\n\nstruct audit_tree;\n\nstruct audit_node {\n\tstruct list_head list;\n\tstruct audit_tree *owner;\n\tunsigned int index;\n};\n\nstruct fsnotify_mark;\n\nstruct audit_chunk {\n\tstruct list_head hash;\n\tlong unsigned int key;\n\tstruct fsnotify_mark *mark;\n\tstruct list_head trees;\n\tint count;\n\tatomic_long_t refs;\n\tstruct callback_head head;\n\tstruct audit_node owners[0];\n};\n\nstruct filename;\n\nstruct audit_names {\n\tstruct list_head list;\n\tstruct filename *name;\n\tint name_len;\n\tbool hidden;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tstruct lsm_prop oprop;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tunsigned char type;\n\tbool should_free;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct mq_attr {\n\t__kernel_long_t mq_flags;\n\t__kernel_long_t mq_maxmsg;\n\t__kernel_long_t mq_msgsize;\n\t__kernel_long_t mq_curmsgs;\n\t__kernel_long_t __reserved[4];\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct audit_proctitle {\n\tint len;\n\tchar *value;\n};\n\nstruct audit_tree_refs;\n\nstruct audit_context {\n\tint dummy;\n\tenum {\n\t\tAUDIT_CTX_UNUSED = 0,\n\t\tAUDIT_CTX_SYSCALL = 1,\n\t\tAUDIT_CTX_URING = 2,\n\t} context;\n\tenum audit_state state;\n\tenum audit_state current_state;\n\tstruct audit_stamp stamp;\n\tint major;\n\tint uring_op;\n\tlong unsigned int argv[4];\n\tlong int return_code;\n\tu64 prio;\n\tint return_valid;\n\tstruct audit_names preallocated_names[5];\n\tint name_count;\n\tstruct list_head names_list;\n\tchar *filterkey;\n\tstruct path pwd;\n\tstruct audit_aux_data *aux;\n\tstruct audit_aux_data *aux_pids;\n\tstruct __kernel_sockaddr_storage *sockaddr;\n\tsize_t sockaddr_len;\n\tpid_t ppid;\n\tkuid_t uid;\n\tkuid_t euid;\n\tkuid_t suid;\n\tkuid_t fsuid;\n\tkgid_t gid;\n\tkgid_t egid;\n\tkgid_t sgid;\n\tkgid_t fsgid;\n\tlong unsigned int personality;\n\tint arch;\n\tpid_t target_pid;\n\tkuid_t target_auid;\n\tkuid_t target_uid;\n\tunsigned int target_sessionid;\n\tstruct lsm_prop target_ref;\n\tchar target_comm[16];\n\tstruct audit_tree_refs *trees;\n\tstruct audit_tree_refs *first_trees;\n\tstruct list_head killed_trees;\n\tint tree_count;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tint nargs;\n\t\t\tlong int args[6];\n\t\t} socketcall;\n\t\tstruct {\n\t\t\tkuid_t uid;\n\t\t\tkgid_t gid;\n\t\t\tumode_t mode;\n\t\t\tstruct lsm_prop oprop;\n\t\t\tint has_perm;\n\t\t\tuid_t perm_uid;\n\t\t\tgid_t perm_gid;\n\t\t\tumode_t perm_mode;\n\t\t\tlong unsigned int qbytes;\n\t\t} ipc;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tstruct mq_attr mqstat;\n\t\t} mq_getsetattr;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tint sigev_signo;\n\t\t} mq_notify;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tsize_t msg_len;\n\t\t\tunsigned int msg_prio;\n\t\t\tstruct timespec64 abs_timeout;\n\t\t} mq_sendrecv;\n\t\tstruct {\n\t\t\tint oflag;\n\t\t\tumode_t mode;\n\t\t\tstruct mq_attr attr;\n\t\t} mq_open;\n\t\tstruct {\n\t\t\tpid_t pid;\n\t\t\tstruct audit_cap_data cap;\n\t\t} capset;\n\t\tstruct {\n\t\t\tint fd;\n\t\t\tint flags;\n\t\t} mmap;\n\t\tstruct open_how openat2;\n\t\tstruct {\n\t\t\tint argc;\n\t\t} execve;\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t} module;\n\t\tstruct {\n\t\t\tstruct audit_ntp_data ntp_data;\n\t\t\tstruct timespec64 tk_injoffset;\n\t\t} time;\n\t};\n\tint fds[2];\n\tstruct audit_proctitle proctitle;\n};\n\nstruct audit_ctl_mutex {\n\tstruct mutex lock;\n\tvoid *owner;\n};\n\nstruct audit_field;\n\nstruct audit_watch;\n\nstruct audit_fsnotify_mark;\n\nstruct audit_krule {\n\tu32 pflags;\n\tu32 flags;\n\tu32 listnr;\n\tu32 action;\n\tu32 mask[64];\n\tu32 buflen;\n\tu32 field_count;\n\tchar *filterkey;\n\tstruct audit_field *fields;\n\tstruct audit_field *arch_f;\n\tstruct audit_field *inode_f;\n\tstruct audit_watch *watch;\n\tstruct audit_tree *tree;\n\tstruct audit_fsnotify_mark *exe;\n\tstruct list_head rlist;\n\tstruct list_head list;\n\tu64 prio;\n};\n\nstruct audit_entry {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tstruct audit_krule rule;\n};\n\nstruct audit_features {\n\t__u32 vers;\n\t__u32 mask;\n\t__u32 features;\n\t__u32 lock;\n};\n\nstruct audit_field {\n\tu32 type;\n\tunion {\n\t\tu32 val;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tstruct {\n\t\t\tchar *lsm_str;\n\t\t\tvoid *lsm_rule;\n\t\t};\n\t};\n\tu32 op;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark_connector;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct audit_fsnotify_mark {\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar *path;\n\tstruct fsnotify_mark mark;\n\tstruct audit_krule *rule;\n};\n\nstruct sock;\n\nstruct audit_net {\n\tstruct sock *sk;\n};\n\nstruct audit_netlink_list {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff_head q;\n};\n\nstruct audit_nfcfgop_tab {\n\tenum audit_nfcfgop op;\n\tconst char *s;\n};\n\nstruct audit_parent {\n\tstruct list_head watches;\n\tstruct fsnotify_mark mark;\n};\n\nstruct audit_reply {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff *skb;\n};\n\nstruct audit_rule_data {\n\t__u32 flags;\n\t__u32 action;\n\t__u32 field_count;\n\t__u32 mask[64];\n\t__u32 fields[64];\n\t__u32 values[64];\n\t__u32 fieldflags[64];\n\t__u32 buflen;\n\tchar buf[0];\n};\n\nstruct audit_sig_info {\n\tuid_t uid;\n\tpid_t pid;\n\tchar ctx[0];\n};\n\nstruct audit_status {\n\t__u32 mask;\n\t__u32 enabled;\n\t__u32 failure;\n\t__u32 pid;\n\t__u32 rate_limit;\n\t__u32 backlog_limit;\n\t__u32 lost;\n\t__u32 backlog;\n\tunion {\n\t\t__u32 version;\n\t\t__u32 feature_bitmap;\n\t};\n\t__u32 backlog_wait_time;\n\t__u32 backlog_wait_time_actual;\n};\n\nstruct audit_tree {\n\trefcount_t count;\n\tint goner;\n\tstruct audit_chunk *root;\n\tstruct list_head chunks;\n\tstruct list_head rules;\n\tstruct list_head list;\n\tstruct list_head same_root;\n\tstruct callback_head head;\n\tchar pathname[0];\n};\n\nstruct audit_tree_mark {\n\tstruct fsnotify_mark mark;\n\tstruct audit_chunk *chunk;\n};\n\nstruct audit_tree_refs {\n\tstruct audit_tree_refs *next;\n\tstruct audit_chunk *c[31];\n};\n\nstruct audit_tty_status {\n\t__u32 enabled;\n\t__u32 log_passwd;\n};\n\nstruct audit_watch {\n\trefcount_t count;\n\tdev_t dev;\n\tchar *path;\n\tlong unsigned int ino;\n\tstruct audit_parent *parent;\n\tstruct list_head wlist;\n\tstruct list_head rules;\n};\n\nstruct pid;\n\nstruct auditd_connection {\n\tstruct pid *pid;\n\tu32 portid;\n\tstruct net *net;\n\tstruct callback_head rcu;\n};\n\nstruct auto_mode_param {\n\tint qp_type;\n};\n\nstruct auto_movable_group_stats {\n\tlong unsigned int movable_pages;\n\tlong unsigned int req_kernel_early_pages;\n};\n\nstruct auto_movable_stats {\n\tlong unsigned int kernel_early_pages;\n\tlong unsigned int movable_pages;\n};\n\nstruct task_group;\n\nstruct autogroup {\n\tstruct kref kref;\n\tstruct task_group *tg;\n\tstruct rw_semaphore lock;\n\tlong unsigned int id;\n\tint nice;\n};\n\nstruct sf_buffer {\n\tlong unsigned int *sdbt;\n\tlong unsigned int num_sdb;\n\tlong unsigned int num_sdbt;\n\tlong unsigned int *tail;\n};\n\nstruct aux_buffer {\n\tstruct sf_buffer sfb;\n\tlong unsigned int head;\n\tlong unsigned int alert_mark;\n\tlong unsigned int empty_mark;\n\tlong unsigned int *sdb_index;\n\tlong unsigned int *sdbt_index;\n};\n\nstruct auxiliary_device {\n\tstruct device dev;\n\tconst char *name;\n\tu32 id;\n\tstruct {\n\t\tstruct xarray irqs;\n\t\tstruct mutex lock;\n\t\tbool irq_dir_exists;\n\t} sysfs;\n};\n\nstruct auxiliary_device_id {\n\tchar name[40];\n\tkernel_ulong_t driver_data;\n};\n\nstruct auxiliary_driver {\n\tint (*probe)(struct auxiliary_device *, const struct auxiliary_device_id *);\n\tvoid (*remove)(struct auxiliary_device *);\n\tvoid (*shutdown)(struct auxiliary_device *);\n\tint (*suspend)(struct auxiliary_device *, pm_message_t);\n\tint (*resume)(struct auxiliary_device *);\n\tconst char *name;\n\tstruct device_driver driver;\n\tconst struct auxiliary_device_id *id_table;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct auxiliary_irq_info {\n\tstruct device_attribute sysfs_attr;\n\tchar name[11];\n};\n\nstruct av_decision {\n\tu32 allowed;\n\tu32 auditallow;\n\tu32 auditdeny;\n\tu32 seqno;\n\tu32 flags;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct avc_cache {\n\tstruct hlist_head slots[512];\n\tspinlock_t slots_lock[512];\n\tatomic_t lru_hint;\n\tatomic_t active_nodes;\n\tu32 latest_notif;\n};\n\nstruct avc_cache_stats {\n\tunsigned int lookups;\n\tunsigned int misses;\n\tunsigned int allocations;\n\tunsigned int reclaims;\n\tunsigned int frees;\n};\n\nstruct avc_callback_node {\n\tint (*callback)(u32);\n\tu32 events;\n\tstruct avc_callback_node *next;\n};\n\nstruct avc_xperms_node;\n\nstruct avc_entry {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tstruct av_decision avd;\n\tstruct avc_xperms_node *xp_node;\n};\n\nstruct avc_node {\n\tstruct avc_entry ae;\n\tstruct hlist_node list;\n\tstruct callback_head rhead;\n};\n\nstruct extended_perms_data;\n\nstruct extended_perms_decision {\n\tu8 used;\n\tu8 driver;\n\tu8 base_perm;\n\tstruct extended_perms_data *allowed;\n\tstruct extended_perms_data *auditallow;\n\tstruct extended_perms_data *dontaudit;\n};\n\nstruct avc_xperms_decision_node {\n\tstruct extended_perms_decision xpd;\n\tstruct list_head xpd_list;\n};\n\nstruct extended_perms_data {\n\tu32 p[8];\n};\n\nstruct extended_perms {\n\tu16 len;\n\tu8 base_perms;\n\tstruct extended_perms_data drivers;\n};\n\nstruct avc_xperms_node {\n\tstruct extended_perms xp;\n\tstruct list_head xpd_head;\n};\n\nstruct avdc_entry {\n\tu32 isid;\n\tu32 allowed;\n\tu32 audited;\n\tbool permissive;\n};\n\nstruct avtab_node;\n\nstruct avtab {\n\tstruct avtab_node **htable;\n\tu32 nel;\n\tu32 nslot;\n\tu32 mask;\n};\n\nstruct avtab_extended_perms;\n\nstruct avtab_datum {\n\tunion {\n\t\tu32 data;\n\t\tstruct avtab_extended_perms *xperms;\n\t} u;\n};\n\nstruct avtab_extended_perms {\n\tu8 specified;\n\tu8 driver;\n\tstruct extended_perms_data perms;\n};\n\nstruct avtab_key {\n\tu16 source_type;\n\tu16 target_type;\n\tu16 target_class;\n\tu16 specified;\n};\n\nstruct avtab_node {\n\tstruct avtab_key key;\n\tstruct avtab_datum datum;\n\tstruct avtab_node *next;\n};\n\nstruct backing_aio {\n\tstruct kiocb iocb;\n\trefcount_t ref;\n\tstruct kiocb *orig_iocb;\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n\tstruct work_struct work;\n\tlong int res;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct backing_dev_info;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n\tstruct percpu_ref refcnt;\n\tstruct fprop_local_percpu memcg_completions;\n\tstruct cgroup_subsys_state *memcg_css;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct list_head memcg_node;\n\tstruct list_head blkcg_node;\n\tstruct list_head b_attached;\n\tstruct list_head offline_node;\n\tstruct work_struct switch_work;\n\tstruct llist_head switch_wbs_ctxs;\n\tunion {\n\t\tstruct work_struct release_work;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\tstruct xarray cgwb_tree;\n\tstruct mutex cgwb_release_mutex;\n\tstruct rw_semaphore wb_switch_rwsem;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tloff_t prev_pos;\n};\n\nstruct file_operations;\n\nstruct fown_struct;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\tvoid *f_security;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backing_file_ctx {\n\tconst struct cred *cred;\n\tvoid (*accessed)(struct file *);\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n};\n\nstruct btrfs_lru_cache_entry {\n\tstruct list_head lru_list;\n\tu64 key;\n\tu64 gen;\n\tstruct list_head list;\n};\n\nstruct backref_cache_entry {\n\tstruct btrfs_lru_cache_entry entry;\n\tu64 root_ids[17];\n\tint num_roots;\n};\n\nstruct send_ctx;\n\nstruct backref_ctx {\n\tstruct send_ctx *sctx;\n\tu64 found;\n\tu64 cur_objectid;\n\tu64 cur_offset;\n\tu64 extent_len;\n\tu64 bytenr;\n\tu64 backref_owner;\n\tu64 backref_offset;\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct balloon_dev_info {\n\tlong unsigned int isolated_pages;\n\tstruct list_head pages;\n\tint (*migratepage)(struct balloon_dev_info *, struct page *, struct page *, enum migrate_mode);\n\tbool adjust_managed_page_count;\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct local_lock {};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct bd_holder_disk {\n\tstruct list_head list;\n\tstruct kobject *holder_dir;\n\tint refcnt;\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tvoid *bd_security;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct super_block;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tvoid *i_security;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct bdi_writeback *i_wb;\n\tint i_wb_frn_winner;\n\tu16 i_wb_frn_avg_time;\n\tu16 i_wb_frn_history;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct bfq_sched_data;\n\nstruct bfq_queue;\n\nstruct bfq_entity {\n\tstruct rb_node rb_node;\n\tbool on_st_or_in_serv;\n\tu64 start;\n\tu64 finish;\n\tstruct rb_root *tree;\n\tu64 min_start;\n\tint service;\n\tint budget;\n\tint allocated;\n\tint dev_weight;\n\tint weight;\n\tint new_weight;\n\tint orig_weight;\n\tstruct bfq_entity *parent;\n\tstruct bfq_sched_data *my_sched_data;\n\tstruct bfq_sched_data *sched_data;\n\tint prio_changed;\n\tbool in_groups_with_pending_reqs;\n\tstruct bfq_queue *last_bfqq_created;\n};\n\nstruct bfq_ttime {\n\tu64 last_end_request;\n\tu64 ttime_total;\n\tlong unsigned int ttime_samples;\n\tu64 ttime_mean;\n};\n\nstruct bfq_data;\n\nstruct request;\n\nstruct bfq_weight_counter;\n\nstruct bfq_io_cq;\n\nstruct bfq_queue {\n\tint ref;\n\tint stable_ref;\n\tstruct bfq_data *bfqd;\n\tshort unsigned int ioprio;\n\tshort unsigned int ioprio_class;\n\tshort unsigned int new_ioprio;\n\tshort unsigned int new_ioprio_class;\n\tu64 last_serv_time_ns;\n\tunsigned int inject_limit;\n\tlong unsigned int decrease_time_jif;\n\tstruct bfq_queue *new_bfqq;\n\tstruct rb_node pos_node;\n\tstruct rb_root *pos_root;\n\tstruct rb_root sort_list;\n\tstruct request *next_rq;\n\tint queued[2];\n\tint meta_pending;\n\tstruct list_head fifo;\n\tstruct bfq_entity entity;\n\tstruct bfq_weight_counter *weight_counter;\n\tint max_budget;\n\tlong unsigned int budget_timeout;\n\tint dispatched;\n\tlong unsigned int flags;\n\tstruct list_head bfqq_list;\n\tstruct bfq_ttime ttime;\n\tu64 io_start_time;\n\tu64 tot_idle_time;\n\tu32 seek_history;\n\tstruct hlist_node burst_list_node;\n\tsector_t last_request_pos;\n\tunsigned int requests_within_timer;\n\tpid_t pid;\n\tstruct bfq_io_cq *bic;\n\tlong unsigned int wr_cur_max_time;\n\tlong unsigned int soft_rt_next_start;\n\tlong unsigned int last_wr_start_finish;\n\tunsigned int wr_coeff;\n\tlong unsigned int last_idle_bklogged;\n\tlong unsigned int service_from_backlogged;\n\tlong unsigned int service_from_wr;\n\tlong unsigned int wr_start_at_switch_to_srt;\n\tlong unsigned int split_time;\n\tlong unsigned int first_IO_time;\n\tlong unsigned int creation_time;\n\tstruct bfq_queue *waker_bfqq;\n\tstruct bfq_queue *tentative_waker_bfqq;\n\tunsigned int num_waker_detections;\n\tu64 waker_detection_started;\n\tstruct hlist_node woken_list_node;\n\tstruct hlist_head woken_list;\n\tunsigned int actuator_idx;\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct bfq_group;\n\nstruct bfq_data {\n\tstruct request_queue *queue;\n\tstruct list_head dispatch;\n\tstruct bfq_group *root_group;\n\tstruct rb_root_cached queue_weights_tree;\n\tunsigned int num_groups_with_pending_reqs;\n\tunsigned int busy_queues[3];\n\tint wr_busy_queues;\n\tint queued;\n\tint tot_rq_in_driver;\n\tint rq_in_driver[8];\n\tbool nonrot_with_queueing;\n\tint max_rq_in_driver;\n\tint hw_tag_samples;\n\tint hw_tag;\n\tint budgets_assigned;\n\tstruct hrtimer idle_slice_timer;\n\tstruct bfq_queue *in_service_queue;\n\tsector_t last_position;\n\tsector_t in_serv_last_pos;\n\tu64 last_completion;\n\tstruct bfq_queue *last_completed_rq_bfqq;\n\tstruct bfq_queue *last_bfqq_created;\n\tu64 last_empty_occupied_ns;\n\tbool wait_dispatch;\n\tstruct request *waited_rq;\n\tbool rqs_injected;\n\tu64 first_dispatch;\n\tu64 last_dispatch;\n\tktime_t last_budget_start;\n\tktime_t last_idling_start;\n\tlong unsigned int last_idling_start_jiffies;\n\tint peak_rate_samples;\n\tu32 sequential_samples;\n\tu64 tot_sectors_dispatched;\n\tu32 last_rq_max_size;\n\tu64 delta_from_first;\n\tu32 peak_rate;\n\tint bfq_max_budget;\n\tstruct list_head active_list[8];\n\tstruct list_head idle_list;\n\tu64 bfq_fifo_expire[2];\n\tunsigned int bfq_back_penalty;\n\tunsigned int bfq_back_max;\n\tu32 bfq_slice_idle;\n\tint bfq_user_max_budget;\n\tunsigned int bfq_timeout;\n\tbool strict_guarantees;\n\tlong unsigned int last_ins_in_burst;\n\tlong unsigned int bfq_burst_interval;\n\tint burst_size;\n\tstruct bfq_entity *burst_parent_entity;\n\tlong unsigned int bfq_large_burst_thresh;\n\tbool large_burst;\n\tstruct hlist_head burst_list;\n\tbool low_latency;\n\tunsigned int bfq_wr_coeff;\n\tunsigned int bfq_wr_rt_max_time;\n\tunsigned int bfq_wr_min_idle_time;\n\tlong unsigned int bfq_wr_min_inter_arr_async;\n\tunsigned int bfq_wr_max_softrt_rate;\n\tu64 rate_dur_prod;\n\tstruct bfq_queue oom_bfqq;\n\tspinlock_t lock;\n\tstruct bfq_io_cq *bio_bic;\n\tstruct bfq_queue *bio_bfqq;\n\tunsigned int async_depths[4];\n\tunsigned int num_actuators;\n\tsector_t sector[8];\n\tsector_t nr_sectors[8];\n\tstruct blk_independent_access_range ia_ranges[8];\n\tunsigned int actuator_load_threshold;\n};\n\nstruct blkcg_gq;\n\nstruct blkg_policy_data {\n\tstruct blkcg_gq *blkg;\n\tint plid;\n\tbool online;\n};\n\nstruct bfq_service_tree {\n\tstruct rb_root active;\n\tstruct rb_root idle;\n\tstruct bfq_entity *first_idle;\n\tstruct bfq_entity *last_idle;\n\tu64 vtime;\n\tlong unsigned int wsum;\n};\n\nstruct bfq_sched_data {\n\tstruct bfq_entity *in_service_entity;\n\tstruct bfq_entity *next_in_service;\n\tstruct bfq_service_tree service_tree[3];\n\tlong unsigned int bfq_class_idle_last_service;\n};\n\nstruct blkg_rwstat {\n\tstruct percpu_counter cpu_cnt[5];\n\tatomic64_t aux_cnt[5];\n};\n\nstruct bfqg_stats {\n\tstruct blkg_rwstat bytes;\n\tstruct blkg_rwstat ios;\n};\n\nstruct bfq_group {\n\tstruct blkg_policy_data pd;\n\trefcount_t ref;\n\tstruct bfq_entity entity;\n\tstruct bfq_sched_data sched_data;\n\tstruct bfq_data *bfqd;\n\tstruct bfq_queue *async_bfqq[128];\n\tstruct bfq_queue *async_idle_bfqq[8];\n\tstruct bfq_entity *my_entity;\n\tint active_entities;\n\tint num_queues_with_pending_reqs;\n\tstruct rb_root rq_pos_tree;\n\tstruct bfqg_stats stats;\n};\n\nstruct blkcg;\n\nstruct blkcg_policy_data {\n\tstruct blkcg *blkcg;\n\tint plid;\n};\n\nstruct bfq_group_data {\n\tstruct blkcg_policy_data pd;\n\tunsigned int weight;\n};\n\nstruct io_context;\n\nstruct kmem_cache;\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct bfq_iocq_bfqq_data {\n\tbool saved_has_short_ttime;\n\tbool saved_IO_bound;\n\tbool saved_in_large_burst;\n\tbool was_in_burst_list;\n\tunsigned int saved_weight;\n\tu64 saved_io_start_time;\n\tu64 saved_tot_idle_time;\n\tlong unsigned int saved_wr_coeff;\n\tlong unsigned int saved_last_wr_start_finish;\n\tlong unsigned int saved_service_from_wr;\n\tlong unsigned int saved_wr_start_at_switch_to_srt;\n\tstruct bfq_ttime saved_ttime;\n\tunsigned int saved_wr_cur_max_time;\n\tunsigned int saved_inject_limit;\n\tlong unsigned int saved_decrease_time_jif;\n\tu64 saved_last_serv_time_ns;\n\tstruct bfq_queue *stable_merge_bfqq;\n\tbool stably_merged;\n};\n\nstruct bfq_io_cq {\n\tstruct io_cq icq;\n\tstruct bfq_queue *bfqq[16];\n\tint ioprio;\n\tuint64_t blkcg_serial_nr;\n\tstruct bfq_iocq_bfqq_data bfqq_data[8];\n\tunsigned int requests;\n};\n\nstruct bfq_weight_counter {\n\tunsigned int weight;\n\tunsigned int num_active;\n\tstruct rb_node weights_node;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct big_key_payload {\n\tu8 *data;\n\tstruct path path;\n\tsize_t length;\n};\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct binfmt_misc {\n\tstruct list_head entries;\n\trwlock_t entries_lock;\n\tbool enabled;\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n} __attribute__((packed));\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct bio_crypt_ctx;\n\nstruct bio_integrity_payload;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tstruct blkcg_gq *bi_blkg;\n\tu64 issue_time_ns;\n\tu64 bi_iocost_cost;\n\tstruct bio_crypt_ctx *bi_crypt_context;\n\tstruct bio_integrity_payload *bi_integrity;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tu64 bc_dun[4];\n};\n\nstruct bio_fallback_crypt_ctx {\n\tstruct bio_crypt_ctx crypt_ctx;\n\tstruct bvec_iter crypt_iter;\n\tunion {\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t\tstruct bio *bio;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *bi_private_orig;\n\t\t\tbio_end_io_t *bi_end_io_orig;\n\t\t};\n\t};\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct bio_integrity_alloc {\n\tstruct bio_integrity_payload bip;\n\tstruct bio_vec bvecs[0];\n};\n\nstruct bio_integrity_data {\n\tstruct bio *bio;\n\tstruct bvec_iter saved_bio_iter;\n\tstruct work_struct work;\n\tstruct bio_integrity_payload bip;\n\tstruct bio_vec bvec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec;\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct fsverity_info;\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct fsverity_info *vi;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bitmap_page;\n\nstruct bitmap_counts {\n\tspinlock_t lock;\n\tstruct bitmap_page *bp;\n\tlong unsigned int pages;\n\tlong unsigned int missing_pages;\n\tlong unsigned int chunkshift;\n\tlong unsigned int chunks;\n};\n\nstruct bitmap_storage {\n\tstruct file *file;\n\tstruct page *sb_page;\n\tlong unsigned int sb_index;\n\tstruct page **filemap;\n\tlong unsigned int *filemap_attr;\n\tlong unsigned int file_pages;\n\tlong unsigned int bytes;\n};\n\nstruct mddev;\n\nstruct bitmap {\n\tstruct bitmap_counts counts;\n\tstruct mddev *mddev;\n\t__u64 events_cleared;\n\tint need_sync;\n\tstruct bitmap_storage storage;\n\tlong unsigned int flags;\n\tint allclean;\n\tatomic_t behind_writes;\n\tlong unsigned int behind_writes_used;\n\tlong unsigned int daemon_lastrun;\n\tlong unsigned int last_end_sync;\n\tatomic_t pending_writes;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t overflow_wait;\n\twait_queue_head_t behind_wait;\n\tstruct kernfs_node *sysfs_can_clear;\n\tint cluster_slot;\n};\n\nstruct md_submodule_head {\n\tenum md_submodule_type type;\n\tenum md_submodule_id id;\n\tconst char *name;\n\tstruct module *owner;\n};\n\ntypedef void md_bitmap_fn(struct mddev *, sector_t, long unsigned int);\n\nstruct md_bitmap_stats;\n\nstruct bitmap_operations {\n\tstruct md_submodule_head head;\n\tbool (*enabled)(void *, bool);\n\tint (*create)(struct mddev *);\n\tint (*resize)(struct mddev *, sector_t, int);\n\tint (*load)(struct mddev *);\n\tvoid (*destroy)(struct mddev *);\n\tvoid (*flush)(struct mddev *);\n\tvoid (*write_all)(struct mddev *);\n\tvoid (*dirty_bits)(struct mddev *, long unsigned int, long unsigned int);\n\tvoid (*unplug)(struct mddev *, bool);\n\tvoid (*daemon_work)(struct mddev *);\n\tvoid (*start_behind_write)(struct mddev *);\n\tvoid (*end_behind_write)(struct mddev *);\n\tvoid (*wait_behind_writes)(struct mddev *);\n\tmd_bitmap_fn *start_write;\n\tmd_bitmap_fn *end_write;\n\tmd_bitmap_fn *start_discard;\n\tmd_bitmap_fn *end_discard;\n\tsector_t (*skip_sync_blocks)(struct mddev *, sector_t);\n\tbool (*blocks_synced)(struct mddev *, sector_t);\n\tbool (*start_sync)(struct mddev *, sector_t, sector_t *, bool);\n\tvoid (*end_sync)(struct mddev *, sector_t, sector_t *);\n\tvoid (*cond_end_sync)(struct mddev *, sector_t, bool);\n\tvoid (*close_sync)(struct mddev *);\n\tvoid (*update_sb)(void *);\n\tint (*get_stats)(void *, struct md_bitmap_stats *);\n\tvoid (*sync_with_cluster)(struct mddev *, sector_t, sector_t, sector_t, sector_t);\n\tvoid * (*get_from_slot)(struct mddev *, int);\n\tint (*copy_from_slot)(struct mddev *, int, sector_t *, sector_t *, bool);\n\tvoid (*set_pages)(void *, long unsigned int);\n\tvoid (*free)(void *);\n\tstruct attribute_group *group;\n};\n\nstruct bitmap_page {\n\tchar *map;\n\tunsigned int hijacked: 1;\n\tunsigned int pending: 1;\n\tunsigned int count: 30;\n};\n\nstruct bitmap_super_s {\n\t__le32 magic;\n\t__le32 version;\n\t__u8 uuid[16];\n\t__le64 events;\n\t__le64 events_cleared;\n\t__le64 sync_size;\n\t__le32 state;\n\t__le32 chunksize;\n\t__le32 daemon_sleep;\n\t__le32 write_behind;\n\t__le32 sectors_reserved;\n\t__le32 nodes;\n\t__u8 cluster_name[64];\n\t__u8 pad[120];\n};\n\ntypedef struct bitmap_super_s bitmap_super_t;\n\nstruct bitmap_unplug_work {\n\tstruct work_struct work;\n\tstruct bitmap *bitmap;\n\tstruct completion *done;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2b_ctx {\n\tu64 h[8];\n\tu64 t[2];\n\tu64 f[2];\n\tu8 buf[128];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_profile;\n\nstruct blk_crypto_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_crypto_profile *, struct blk_crypto_attr *, char *);\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct crypto_sync_skcipher;\n\nstruct blk_crypto_fallback_keyslot {\n\tenum blk_crypto_mode_num crypto_mode;\n\tstruct crypto_sync_skcipher *tfms[5];\n};\n\nstruct blk_crypto_generate_key_arg {\n\t__u64 lt_key_ptr;\n\t__u64 lt_key_size;\n\t__u64 reserved[4];\n};\n\nstruct blk_crypto_import_key_arg {\n\t__u64 raw_key_ptr;\n\t__u64 raw_key_size;\n\t__u64 lt_key_ptr;\n\t__u64 lt_key_size;\n\t__u64 reserved[4];\n};\n\nunion blk_crypto_iv {\n\t__le64 dun[4];\n\tu8 bytes[32];\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct blk_crypto_keyslot {\n\tatomic_t slot_refs;\n\tstruct list_head idle_slot_node;\n\tstruct hlist_node hash_node;\n\tconst struct blk_crypto_key *key;\n\tstruct blk_crypto_profile *profile;\n};\n\nstruct blk_crypto_kobj {\n\tstruct kobject kobj;\n\tstruct blk_crypto_profile *profile;\n};\n\nstruct blk_crypto_ll_ops {\n\tint (*keyslot_program)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*keyslot_evict)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*derive_sw_secret)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*import_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*generate_key)(struct blk_crypto_profile *, u8 *);\n\tint (*prepare_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n};\n\nstruct blk_crypto_mode {\n\tconst char *name;\n\tconst char *cipher_str;\n\tunsigned int keysize;\n\tunsigned int security_strength;\n\tunsigned int ivsize;\n};\n\nstruct blk_crypto_prepare_key_arg {\n\t__u64 lt_key_ptr;\n\t__u64 lt_key_size;\n\t__u64 eph_key_ptr;\n\t__u64 eph_key_size;\n\t__u64 reserved[4];\n};\n\nstruct blk_crypto_profile {\n\tstruct blk_crypto_ll_ops ll_ops;\n\tunsigned int max_dun_bytes_supported;\n\tunsigned int key_types_supported;\n\tunsigned int modes_supported[5];\n\tstruct device *dev;\n\tunsigned int num_slots;\n\tstruct rw_semaphore lock;\n\tstruct lock_class_key lockdep_key;\n\twait_queue_head_t idle_slots_wait_queue;\n\tstruct list_head idle_slots;\n\tspinlock_t idle_slots_lock;\n\tstruct hlist_head *slot_hashtable;\n\tunsigned int log_slot_ht_size;\n\tstruct blk_crypto_keyslot *slots;\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_integrity_iter {\n\tvoid *prot_buf;\n\tvoid *data_buf;\n\tsector_t seed;\n\tunsigned int data_size;\n\tshort unsigned int interval;\n\tconst char *disk_name;\n};\n\nstruct blk_io_trace {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 action;\n\t__u32 pid;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n};\n\nstruct blk_io_trace2 {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 pid;\n\t__u64 action;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n\t__u8 pad[12];\n};\n\nstruct blk_io_trace_remap {\n\t__be32 device_from;\n\t__be32 device_to;\n\t__be64 sector_from;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct blk_iolatency {\n\tstruct rq_qos rqos;\n\tstruct timer_list timer;\n\tbool enabled;\n\tatomic_t enable_cnt;\n\tstruct work_struct enable_work;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct rchan;\n\nstruct blk_trace {\n\tint version;\n\tint trace_state;\n\tstruct rchan *rchan;\n\tlong unsigned int *sequence;\n\tunsigned char *msg_data;\n\tu64 act_mask;\n\tu64 start_lba;\n\tu64 end_lba;\n\tu32 pid;\n\tu32 dev;\n\tstruct dentry *dir;\n\tstruct list_head running_list;\n\tatomic_t dropped;\n};\n\nstruct blk_user_trace_setup {\n\tchar name[32];\n\t__u16 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n};\n\nstruct blk_user_trace_setup2 {\n\tchar name[64];\n\t__u64 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n\t__u32 flags;\n\t__u64 reserved[11];\n};\n\nstruct blk_zone {\n\t__u64 start;\n\t__u64 len;\n\t__u64 wp;\n\t__u8 type;\n\t__u8 cond;\n\t__u8 non_seq;\n\t__u8 reset;\n\t__u8 resv[4];\n\t__u64 capacity;\n\t__u8 reserved[24];\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct cgroup_subsys;\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n};\n\nstruct blkcg {\n\tstruct cgroup_subsys_state css;\n\tspinlock_t lock;\n\trefcount_t online_pin;\n\tatomic_t congestion_count;\n\tstruct xarray blkg_tree;\n\tstruct blkcg_gq *blkg_hint;\n\tstruct hlist_head blkg_list;\n\tstruct blkcg_policy_data *cpd[6];\n\tstruct list_head all_blkcgs_node;\n\tstruct llist_head *lhead;\n\tstruct list_head cgwb_list;\n};\n\nstruct blkg_iostat {\n\tu64 bytes[3];\n\tu64 ios[3];\n};\n\nstruct blkg_iostat_set {\n\tstruct u64_stats_sync sync;\n\tstruct blkcg_gq *blkg;\n\tstruct llist_node lnode;\n\tint lqueued;\n\tstruct blkg_iostat cur;\n\tstruct blkg_iostat last;\n};\n\nstruct blkcg_gq {\n\tstruct request_queue *q;\n\tstruct list_head q_node;\n\tstruct hlist_node blkcg_node;\n\tstruct blkcg *blkcg;\n\tstruct blkcg_gq *parent;\n\tstruct percpu_ref refcnt;\n\tbool online;\n\tstruct blkg_iostat_set *iostat_cpu;\n\tstruct blkg_iostat_set iostat;\n\tstruct blkg_policy_data *pd[6];\n\tspinlock_t async_bio_lock;\n\tstruct bio_list async_bios;\n\tunion {\n\t\tstruct work_struct async_bio_work;\n\t\tstruct work_struct free_work;\n\t};\n\tatomic_t use_delay;\n\tatomic64_t delay_nsec;\n\tatomic64_t delay_start;\n\tu64 last_delay;\n\tint last_use;\n\tstruct callback_head callback_head;\n};\n\ntypedef struct blkcg_policy_data *blkcg_pol_alloc_cpd_fn(gfp_t);\n\ntypedef void blkcg_pol_free_cpd_fn(struct blkcg_policy_data *);\n\ntypedef struct blkg_policy_data *blkcg_pol_alloc_pd_fn(struct gendisk *, struct blkcg *, gfp_t);\n\ntypedef void blkcg_pol_init_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_online_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_offline_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_free_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_reset_pd_stats_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_stat_pd_fn(struct blkg_policy_data *, struct seq_file *);\n\nstruct cftype;\n\nstruct blkcg_policy {\n\tint plid;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tblkcg_pol_alloc_cpd_fn *cpd_alloc_fn;\n\tblkcg_pol_free_cpd_fn *cpd_free_fn;\n\tblkcg_pol_alloc_pd_fn *pd_alloc_fn;\n\tblkcg_pol_init_pd_fn *pd_init_fn;\n\tblkcg_pol_online_pd_fn *pd_online_fn;\n\tblkcg_pol_offline_pd_fn *pd_offline_fn;\n\tblkcg_pol_free_pd_fn *pd_free_fn;\n\tblkcg_pol_reset_pd_stats_fn *pd_reset_stats_fn;\n\tblkcg_pol_stat_pd_fn *pd_stat_fn;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bio bio;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blkg_conf_ctx {\n\tchar *input;\n\tchar *body;\n\tstruct block_device *bdev;\n\tstruct blkcg_gq *blkg;\n};\n\nstruct blkg_rwstat_sample {\n\tu64 cnt[5];\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n};\n\nstruct block_buffer {\n\tu32 filled;\n\tbool is_root_hash;\n\tu8 *data;\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[128];\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct boot_triggers {\n\tconst char *event;\n\tchar *trigger;\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct obj_cgroup;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tvoid *security;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tstruct obj_cgroup *objcg;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n};\n\nstruct range_tree {\n\tstruct rb_root_cached it_root;\n\tstruct rb_root_cached range_size_root;\n};\n\nstruct rqspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tu32 locked;\n\t};\n};\n\ntypedef struct rqspinlock rqspinlock_t;\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct vm_struct;\n\nstruct bpf_arena {\n\tstruct bpf_map map;\n\tu64 user_vm_start;\n\tu64 user_vm_end;\n\tstruct vm_struct *kern_vm;\n\tstruct range_tree rt;\n\trqspinlock_t spinlock;\n\tstruct list_head vma_list;\n\tstruct mutex lock;\n\tstruct irq_work free_irq;\n\tstruct work_struct free_work;\n\tstruct llist_head free_spans;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct bpf_prog;\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 0;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_cgroup_dev_ctx {\n\t__u32 access_type;\n\t__u32 major;\n\t__u32 minor;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n};\n\nstruct bpf_cgroup_link {\n\tstruct bpf_link link;\n\tstruct cgroup *cgroup;\n};\n\nstruct bpf_cgroup_storage_key {\n\t__u64 cgroup_inode_id;\n\t__u32 attach_type;\n};\n\nstruct bpf_storage_buffer;\n\nstruct bpf_cgroup_storage_map;\n\nstruct bpf_cgroup_storage {\n\tunion {\n\t\tstruct bpf_storage_buffer *buf;\n\t\tvoid *percpu_buf;\n\t};\n\tstruct bpf_cgroup_storage_map *map;\n\tstruct bpf_cgroup_storage_key key;\n\tstruct list_head list_map;\n\tstruct list_head list_cg;\n\tstruct rb_node node;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_cgroup_storage_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tstruct rb_root root;\n\tstruct list_head list;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct skb_ext;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tlong unsigned int _nfct;\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\t__u8 active_extensions;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\tchar: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 ipvs_property: 1;\n\t\t\t__u8 nf_trace: 1;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 from_ingress: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 decrypted: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 csum_not_inet: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\tchar: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 ipvs_property: 1;\n\t\t\t__u8 nf_trace: 1;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 from_ingress: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 decrypted: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 csum_not_inet: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tstruct skb_ext *extensions;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_rxq_info;\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t};\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct sock_cgroup_data {\n\tstruct cgroup *cgroup;\n\tu32 classid;\n\tu16 prioidx;\n};\n\nstruct dst_entry;\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct socket;\n\nstruct mem_cgroup;\n\nstruct xfrm_policy;\n\nstruct sock_reuseport;\n\nstruct bpf_local_storage;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\tstruct mem_cgroup *sk_memcg;\n\tstruct xfrm_policy *sk_policy[2];\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tnetdev_features_t sk_route_caps;\n\tstruct sk_buff * (*sk_validate_xmit_skb)(struct sock *, struct net_device *, struct sk_buff *);\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tktime_t sk_stamp;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tvoid *sk_security;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_sample_data;\n\nstruct perf_event;\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nstruct bpf_sysctl {\n\t__u32 write;\n\t__u32 file_pos;\n};\n\nstruct bpf_sysctl_kern {\n\tstruct ctl_table_header *head;\n\tconst struct ctl_table *table;\n\tvoid *cur_val;\n\tsize_t cur_len;\n\tvoid *new_val;\n\tsize_t new_len;\n\tint new_updated;\n\tint write;\n\tloff_t *ppos;\n\tu64 tmp_reg;\n};\n\nstruct bpf_sockopt {\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *optval;\n\t};\n\tunion {\n\t\tvoid *optval_end;\n\t};\n\t__s32 level;\n\t__s32 optname;\n\t__s32 optlen;\n\t__s32 retval;\n};\n\nstruct bpf_sockopt_kern {\n\tstruct sock *sk;\n\tu8 *optval;\n\tu8 *optval_end;\n\ts32 level;\n\ts32 optname;\n\ts32 optlen;\n\tstruct task_struct *current_task;\n\tu64 tmp_reg;\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_CGROUP_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_CGROUP_SKB_kern;\n\tstruct bpf_sock BPF_PROG_TYPE_CGROUP_SOCK_prog;\n\tstruct sock BPF_PROG_TYPE_CGROUP_SOCK_kern;\n\tstruct bpf_sock_addr BPF_PROG_TYPE_CGROUP_SOCK_ADDR_prog;\n\tstruct bpf_sock_addr_kern BPF_PROG_TYPE_CGROUP_SOCK_ADDR_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_prog;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_kern;\n\tstruct bpf_sysctl BPF_PROG_TYPE_CGROUP_SYSCTL_prog;\n\tstruct bpf_sysctl_kern BPF_PROG_TYPE_CGROUP_SYSCTL_kern;\n\tstruct bpf_sockopt BPF_PROG_TYPE_CGROUP_SOCKOPT_prog;\n\tstruct bpf_sockopt_kern BPF_PROG_TYPE_CGROUP_SOCKOPT_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_LSM_prog;\n\tvoid *BPF_PROG_TYPE_LSM_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_prog;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_kern;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n};\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n};\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 0;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct dma_buf;\n\nstruct bpf_iter__dmabuf {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct dma_buf *dmabuf;\n\t};\n};\n\nstruct fib6_info;\n\nstruct bpf_iter__ipv6_route {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct fib6_info *rt;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 0;\n\tint bucket;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n};\n\nstruct bpf_iter_dmabuf {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_dmabuf_kern {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 0;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct mm_struct;\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit {\n\tu32 seen;\n\tu16 seen_regs;\n\tu32 *addrs;\n\tu8 *prg_buf;\n\tint size;\n\tint size_prg;\n\tint prg;\n\tint lit32_start;\n\tint lit32;\n\tint lit64_start;\n\tint lit64;\n\tint base_ip;\n\tint exit_ip;\n\tint tail_call_start;\n\tint excnt;\n\tint prologue_plt_ret;\n\tint prologue_plt;\n\tint kern_arena;\n\tu64 user_arena;\n\tu32 frame_off;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jit_probe {\n\tint prg;\n\tint nop_prg;\n\tint reg;\n\tint arena_reg;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct fprobe;\n\nstruct ftrace_regs;\n\ntypedef int (*fprobe_entry_cb)(struct fprobe *, long unsigned int, long unsigned int, struct ftrace_regs *, void *);\n\ntypedef void (*fprobe_exit_cb)(struct fprobe *, long unsigned int, long unsigned int, struct ftrace_regs *, void *);\n\nstruct fprobe_hlist;\n\nstruct fprobe {\n\tlong unsigned int nmissed;\n\tunsigned int flags;\n\tsize_t entry_data_size;\n\tfprobe_entry_cb entry_handler;\n\tfprobe_exit_cb exit_handler;\n\tstruct fprobe_hlist *hlist_array;\n};\n\nstruct bpf_kprobe_multi_link {\n\tstruct bpf_link link;\n\tstruct fprobe fp;\n\tlong unsigned int *addrs;\n\tu64 *cookies;\n\tu32 cnt;\n\tu32 mods_cnt;\n\tstruct module **mods;\n};\n\nstruct bpf_session_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tbool is_return;\n\tvoid *data;\n};\n\nstruct bpf_kprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tstruct bpf_kprobe_multi_link *link;\n\tlong unsigned int entry_ip;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n};\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_lwt_prog {\n\tstruct bpf_prog *prog;\n\tchar *name;\n};\n\nstruct bpf_lwt {\n\tstruct bpf_lwt_prog in;\n\tstruct bpf_lwt_prog out;\n\tstruct bpf_lwt_prog xmit;\n\tint family;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tatomic64_t revision;\n\tu32 count;\n};\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\ntypedef unsigned int nf_hookfn(void *, struct sk_buff *, const struct nf_hook_state *);\n\nstruct nf_hook_ops {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tnf_hookfn *hook;\n\tstruct net_device *dev;\n\tvoid *priv;\n\tu8 pf;\n\tenum nf_hook_ops_type hook_ops_type: 8;\n\tunsigned int hooknum;\n\tint priority;\n};\n\nstruct nf_defrag_hook;\n\nstruct bpf_nf_link {\n\tstruct bpf_link link;\n\tstruct nf_hook_ops hook_ops;\n\tnetns_tracker ns_tracker;\n\tstruct net *net;\n\tu32 dead;\n\tconst struct nf_defrag_hook *defrag_hook;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_perf_link {\n\tstruct bpf_link link;\n\tstruct file *perf_file;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_plt {\n\tchar code[16];\n\tvoid *ret;\n\tvoid *target;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tvoid *security;\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_list {\n\tstruct hlist_node node;\n\tstruct bpf_prog *prog;\n\tstruct bpf_cgroup_link *link;\n\tstruct bpf_cgroup_storage *storage[2];\n\tu32 flags;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 64;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\trqspinlock_t spinlock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t busy;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int consumer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct bpf_security_struct {\n\tu32 sid;\n\tu32 perms;\n\tu32 grantor_sid;\n};\n\nstruct bpf_shim_tramp_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_sockopt_buf {\n\tu8 data[32];\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nstruct stack_map_bucket;\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_storage_blob {\n\tstruct bpf_local_storage *storage;\n};\n\nstruct bpf_storage_buffer {\n\tstruct callback_head rcu;\n\tchar data[0];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_dummy_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_ext_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n\tvoid *security;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n};\n\nunion perf_sample_weight {\n\t__u64 full;\n\tstruct {\n\t\t__u16 var3_w;\n\t\t__u16 var2_w;\n\t\t__u32 var1_dw;\n\t};\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_rsvd: 13;\n\t\t__u64 mem_region: 5;\n\t\t__u64 mem_hops: 3;\n\t\t__u64 mem_blk: 3;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_op: 5;\n\t};\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n};\n\nstruct perf_callchain_entry;\n\nstruct perf_raw_record;\n\nstruct perf_branch_stack;\n\nstruct perf_sample_data {\n\tu64 sample_flags;\n\tu64 period;\n\tu64 dyn_size;\n\tu64 type;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tu64 ip;\n\tstruct perf_callchain_entry *callchain;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 *br_stack_cntr;\n\tunion perf_sample_weight weight;\n\tunion perf_mem_data_src data_src;\n\tu64 txn;\n\tstruct perf_regs regs_user;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 stream_id;\n\tu64 cgroup;\n\tu64 addr;\n\tu64 phys_addr;\n\tu64 data_page_size;\n\tu64 code_page_size;\n\tu64 aux_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_jit {\n\tstruct bpf_jit common;\n\tint orig_stack_args_off;\n\tint stack_size;\n\tint backchain_off;\n\tint stack_args_off;\n\tint reg_args_off;\n\tint ip_off;\n\tint arg_cnt_off;\n\tint bpf_args_off;\n\tint retval_off;\n\tint r7_r8_off;\n\tint run_ctx_off;\n\tint tccnt_off;\n\tint r14_off;\n\tint do_fexit;\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[27];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *, __u64 *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *, __u64 *);\n\tbool (*filter)(struct uprobe_consumer *, struct mm_struct *);\n\tstruct list_head cons_node;\n\t__u64 id;\n};\n\nstruct bpf_uprobe_multi_link;\n\nstruct uprobe;\n\nstruct bpf_uprobe {\n\tstruct bpf_uprobe_multi_link *link;\n\tloff_t offset;\n\tlong unsigned int ref_ctr_offset;\n\tu64 cookie;\n\tstruct uprobe *uprobe;\n\tstruct uprobe_consumer consumer;\n\tbool session;\n};\n\nstruct bpf_uprobe_multi_link {\n\tstruct path path;\n\tstruct bpf_link link;\n\tu32 cnt;\n\tstruct bpf_uprobe *uprobes;\n\tstruct task_struct *task;\n};\n\nstruct bpf_uprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tlong unsigned int entry_ip;\n\tstruct bpf_uprobe *uprobe;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpf_xfrm_state {\n\t__u32 reqid;\n\t__u32 spi;\n\t__u16 family;\n\t__u16 ext;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n};\n\nstruct bpf_xfrm_state_opts {\n\ts32 error;\n\ts32 netns_id;\n\tu32 mark;\n\txfrm_address_t daddr;\n\t__be32 spi;\n\tu8 proto;\n\tu16 family;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nstruct br_boolopt_multi {\n\t__u32 optval;\n\t__u32 optmask;\n};\n\nstruct bridge_id {\n\tunsigned char prio[2];\n\tunsigned char addr[6];\n};\n\ntypedef struct bridge_id bridge_id;\n\nstruct br_config_bpdu {\n\tunsigned int topology_change: 1;\n\tunsigned int topology_change_ack: 1;\n\tbridge_id root;\n\tint root_path_cost;\n\tbridge_id bridge_id;\n\tport_id port_id;\n\tint message_age;\n\tint max_age;\n\tint hello_time;\n\tint forward_delay;\n};\n\nstruct net_bridge_port;\n\nstruct br_frame_type {\n\t__be16 type;\n\tint (*frame_handler)(struct net_bridge_port *, struct sk_buff *);\n\tstruct hlist_node list;\n};\n\nstruct br_input_skb_cb {\n\tstruct net_device *brdev;\n\tu16 frag_max_size;\n\tu8 igmp;\n\tu8 mrouters_only: 1;\n\tu8 proxyarp_replied: 1;\n\tu8 src_port_isolated: 1;\n\tu8 promisc: 1;\n\tu8 br_netfilter_broute: 1;\n\tu8 tx_fwd_offload: 1;\n\tint src_hwdom;\n\tlong unsigned int fwd_hwdoms;\n\tu32 backup_nhid;\n};\n\nstruct br_ip {\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t} src;\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t\tunsigned char mac_addr[6];\n\t} dst;\n\t__be16 proto;\n\t__u16 vid;\n};\n\nstruct br_ip_list {\n\tstruct list_head list;\n\tstruct br_ip addr;\n};\n\nstruct br_mcast_stats {\n\t__u64 igmp_v1queries[2];\n\t__u64 igmp_v2queries[2];\n\t__u64 igmp_v3queries[2];\n\t__u64 igmp_leaves[2];\n\t__u64 igmp_v1reports[2];\n\t__u64 igmp_v2reports[2];\n\t__u64 igmp_v3reports[2];\n\t__u64 igmp_parse_errors;\n\t__u64 mld_v1queries[2];\n\t__u64 mld_v2queries[2];\n\t__u64 mld_leaves[2];\n\t__u64 mld_v1reports[2];\n\t__u64 mld_v2reports[2];\n\t__u64 mld_parse_errors;\n\t__u64 mcast_bytes[2];\n\t__u64 mcast_packets[2];\n};\n\nstruct net_bridge;\n\nstruct br_mdb_entry;\n\nstruct br_mdb_src_entry;\n\nstruct br_mdb_config {\n\tstruct net_bridge *br;\n\tstruct net_bridge_port *p;\n\tstruct br_mdb_entry *entry;\n\tstruct br_ip group;\n\tbool src_entry;\n\tu8 filter_mode;\n\tu16 nlflags;\n\tstruct br_mdb_src_entry *src_entries;\n\tint num_src_entries;\n\tu8 rt_protocol;\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_mdb_flush_desc {\n\tu32 port_ifindex;\n\tu16 vid;\n\tu8 rt_protocol;\n\tu8 state;\n\tu8 state_mask;\n};\n\nstruct br_mdb_src_entry {\n\tstruct br_ip addr;\n};\n\nstruct br_mrp {\n\tstruct hlist_node list;\n\tstruct net_bridge_port *p_port;\n\tstruct net_bridge_port *s_port;\n\tstruct net_bridge_port *i_port;\n\tu32 ring_id;\n\tu16 in_id;\n\tu16 prio;\n\tenum br_mrp_ring_role_type ring_role;\n\tu8 ring_role_offloaded;\n\tenum br_mrp_ring_state_type ring_state;\n\tu32 ring_transitions;\n\tenum br_mrp_in_role_type in_role;\n\tu8 in_role_offloaded;\n\tenum br_mrp_in_state_type in_state;\n\tu32 in_transitions;\n\tstruct delayed_work test_work;\n\tu32 test_interval;\n\tlong unsigned int test_end;\n\tu32 test_count_miss;\n\tu32 test_max_miss;\n\tbool test_monitor;\n\tstruct delayed_work in_test_work;\n\tu32 in_test_interval;\n\tlong unsigned int in_test_end;\n\tu32 in_test_count_miss;\n\tu32 in_test_max_miss;\n\tu32 seq_id;\n\tstruct callback_head rcu;\n};\n\nstruct br_mrp_common_hdr {\n\t__be16 seq_id;\n\t__u8 domain[16];\n};\n\nstruct br_mrp_in_role {\n\t__u32 ring_id;\n\t__u32 in_role;\n\t__u32 i_ifindex;\n\t__u16 in_id;\n};\n\nstruct br_mrp_in_state {\n\t__u32 in_state;\n\t__u16 in_id;\n};\n\nstruct br_mrp_in_test_hdr {\n\t__be16 id;\n\t__u8 sa[6];\n\t__be16 port_role;\n\t__be16 state;\n\t__be16 transitions;\n\t__be32 timestamp;\n} __attribute__((packed));\n\nstruct br_mrp_instance {\n\t__u32 ring_id;\n\t__u32 p_ifindex;\n\t__u32 s_ifindex;\n\t__u16 prio;\n};\n\nstruct br_mrp_oui_hdr {\n\t__u8 oui[3];\n};\n\nstruct br_mrp_ring_role {\n\t__u32 ring_id;\n\t__u32 ring_role;\n};\n\nstruct br_mrp_ring_state {\n\t__u32 ring_id;\n\t__u32 ring_state;\n};\n\nstruct br_mrp_ring_test_hdr {\n\t__be16 prio;\n\t__u8 sa[6];\n\t__be16 port_role;\n\t__be16 state;\n\t__be16 transitions;\n\t__be32 timestamp;\n} __attribute__((packed));\n\nstruct br_mrp_start_in_test {\n\t__u32 interval;\n\t__u32 max_miss;\n\t__u32 period;\n\t__u16 in_id;\n};\n\nstruct br_mrp_start_test {\n\t__u32 ring_id;\n\t__u32 interval;\n\t__u32 max_miss;\n\t__u32 period;\n\t__u32 monitor;\n};\n\nstruct br_mrp_sub_option1_hdr {\n\t__u8 type;\n\t__u8 data[2];\n};\n\nstruct br_mrp_tlv_hdr {\n\t__u8 type;\n\t__u8 length;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct br_switchdev_mdb_complete_info {\n\tstruct net_bridge_port *port;\n\tstruct br_ip ip;\n};\n\nstruct metadata_dst;\n\nstruct br_tunnel_info {\n\t__be64 tunnel_id;\n\tstruct metadata_dst *tunnel_dst;\n};\n\nstruct brd_device {\n\tint brd_number;\n\tstruct gendisk *brd_disk;\n\tstruct list_head brd_list;\n\tstruct xarray brd_pages;\n\tu64 brd_nr_pages;\n};\n\nstruct bridge_mcast_other_query {\n\tstruct timer_list timer;\n\tstruct timer_list delay_timer;\n};\n\nstruct bridge_mcast_own_query {\n\tstruct timer_list timer;\n\tu32 startup_sent;\n};\n\nstruct bridge_mcast_querier {\n\tstruct br_ip addr;\n\tint port_ifidx;\n\tseqcount_spinlock_t seq;\n};\n\nstruct bridge_mcast_stats {\n\tstruct br_mcast_stats mstats;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct bridge_stp_xstats {\n\t__u64 transition_blk;\n\t__u64 transition_fwd;\n\t__u64 rx_bpdu;\n\t__u64 tx_bpdu;\n\t__u64 rx_tcn;\n\t__u64 tx_tcn;\n};\n\nstruct bridge_vlan_info {\n\t__u16 flags;\n\t__u16 vid;\n};\n\nstruct bridge_vlan_xstats {\n\t__u64 rx_bytes;\n\t__u64 rx_packets;\n\t__u64 tx_bytes;\n\t__u64 tx_packets;\n\t__u16 vid;\n\t__u16 flags;\n\t__u32 pad2;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct brport_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct net_bridge_port *, char *);\n\tint (*store)(struct net_bridge_port *, long unsigned int);\n\tint (*store_raw)(struct net_bridge_port *, char *);\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct bsd_acct_struct {\n\tstruct fs_pin pin;\n\tatomic_long_t count;\n\tstruct callback_head rcu;\n\tstruct mutex lock;\n\tbool active;\n\tbool check_space;\n\tlong unsigned int needcheck;\n\tstruct file *file;\n\tstruct pid_namespace *ns;\n\tstruct work_struct work;\n\tstruct completion done;\n\tacct_t ac;\n};\n\nstruct bsd_partition {\n\t__le32 p_size;\n\t__le32 p_offset;\n\t__le32 p_fsize;\n\t__u8 p_fstype;\n\t__u8 p_frag;\n\t__le16 p_cpg;\n};\n\nstruct bsd_disklabel {\n\t__le32 d_magic;\n\t__s16 d_type;\n\t__s16 d_subtype;\n\tchar d_typename[16];\n\tchar d_packname[16];\n\t__u32 d_secsize;\n\t__u32 d_nsectors;\n\t__u32 d_ntracks;\n\t__u32 d_ncylinders;\n\t__u32 d_secpercyl;\n\t__u32 d_secperunit;\n\t__u16 d_sparespertrack;\n\t__u16 d_sparespercyl;\n\t__u32 d_acylinders;\n\t__u16 d_rpm;\n\t__u16 d_interleave;\n\t__u16 d_trackskew;\n\t__u16 d_cylskew;\n\t__u32 d_headswitch;\n\t__u32 d_trkseek;\n\t__u32 d_flags;\n\t__u32 d_drivedata[5];\n\t__u32 d_spare[5];\n\t__le32 d_magic2;\n\t__le16 d_checksum;\n\t__le16 d_npartitions;\n\t__le32 d_bbsize;\n\t__le32 d_sbsize;\n\tstruct bsd_partition d_partitions[16];\n};\n\nstruct bsg_buffer {\n\tunsigned int payload_len;\n\tint sg_cnt;\n\tstruct scatterlist *sg_list;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n};\n\nstruct bsg_job {\n\tstruct device *dev;\n\tstruct kref kref;\n\tunsigned int timeout;\n\tvoid *request;\n\tvoid *reply;\n\tunsigned int request_len;\n\tunsigned int reply_len;\n\tstruct bsg_buffer request_payload;\n\tstruct bsg_buffer reply_payload;\n\tint result;\n\tunsigned int reply_payload_rcv_len;\n\tstruct request *bidi_rq;\n\tstruct bio *bidi_bio;\n\tvoid *dd_data;\n};\n\ntypedef int bsg_job_fn(struct bsg_job *);\n\ntypedef enum blk_eh_timer_return bsg_timeout_fn(struct request *);\n\nstruct bsg_set {\n\tstruct blk_mq_tag_set tag_set;\n\tstruct bsg_device *bd;\n\tbsg_job_fn *job_fn;\n\tbsg_timeout_fn *timeout_fn;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[56];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_anon_stack {\n\tu32 tid;\n\tu32 offset;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_ptr {\n\tvoid *ptr;\n\t__u32 type_id;\n\t__u32 flags;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, struct __va_list_tag *);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct btrfs_delayed_root;\n\nstruct btrfs_async_delayed_work {\n\tstruct btrfs_delayed_root *delayed_root;\n\tint nr;\n\tstruct btrfs_work work;\n};\n\nstruct btrfs_backref_node;\n\nstruct btrfs_fs_info;\n\nstruct btrfs_backref_cache {\n\tstruct rb_root rb_root;\n\tstruct btrfs_backref_node *path[8];\n\tstruct list_head pending[8];\n\tu64 last_trans;\n\tint nr_nodes;\n\tint nr_edges;\n\tstruct list_head pending_edge;\n\tstruct list_head useless_node;\n\tstruct btrfs_fs_info *fs_info;\n\tbool is_reloc;\n};\n\nstruct btrfs_backref_edge {\n\tstruct list_head list[2];\n\tstruct btrfs_backref_node *node[2];\n};\n\nstruct btrfs_key {\n\t__u64 objectid;\n\t__u8 type;\n\t__u64 offset;\n} __attribute__((packed));\n\nstruct btrfs_path;\n\nstruct btrfs_backref_iter {\n\tu64 bytenr;\n\tstruct btrfs_path *path;\n\tstruct btrfs_fs_info *fs_info;\n\tstruct btrfs_key cur_key;\n\tu32 item_ptr;\n\tu32 cur_ptr;\n\tu32 end_ptr;\n};\n\nstruct rb_simple_node {\n\tstruct rb_node rb_node;\n\tu64 bytenr;\n};\n\nstruct btrfs_root;\n\nstruct extent_buffer;\n\nstruct btrfs_backref_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct rb_node rb_node;\n\t\t\tu64 bytenr;\n\t\t};\n\t\tstruct rb_simple_node simple_node;\n\t};\n\tu64 new_bytenr;\n\tu64 owner;\n\tstruct list_head list;\n\tstruct list_head upper;\n\tstruct list_head lower;\n\tstruct btrfs_root *root;\n\tstruct extent_buffer *eb;\n\tunsigned int level: 8;\n\tunsigned int locked: 1;\n\tunsigned int processed: 1;\n\tunsigned int checked: 1;\n\tunsigned int pending: 1;\n\tunsigned int detached: 1;\n\tunsigned int is_reloc_root: 1;\n};\n\nstruct ulist_node;\n\nstruct ulist {\n\tlong unsigned int nnodes;\n\tstruct list_head nodes;\n\tstruct rb_root root;\n\tstruct ulist_node *prealloc;\n};\n\nstruct btrfs_backref_shared_cache_entry {\n\tu64 bytenr;\n\tu64 gen;\n\tbool is_shared;\n};\n\nstruct btrfs_backref_share_check_ctx {\n\tstruct ulist refs;\n\tu64 curr_leaf_bytenr;\n\tu64 prev_leaf_bytenr;\n\tstruct btrfs_backref_shared_cache_entry path_cache_entries[8];\n\tbool use_path_cache;\n\tstruct {\n\t\tu64 bytenr;\n\t\tbool is_shared;\n\t} prev_extents_cache[8];\n\tint prev_extents_cache_slot;\n};\n\ntypedef int iterate_extent_inodes_t(u64, u64, u64, u64, void *);\n\nstruct btrfs_trans_handle;\n\nstruct btrfs_extent_item;\n\nstruct btrfs_backref_walk_ctx {\n\tu64 bytenr;\n\tu64 extent_item_pos;\n\tbool ignore_extent_item_pos;\n\tbool skip_inode_ref_list;\n\tstruct btrfs_trans_handle *trans;\n\tstruct btrfs_fs_info *fs_info;\n\tu64 time_seq;\n\tstruct ulist *refs;\n\tstruct ulist *roots;\n\tbool (*cache_lookup)(u64, void *, const u64 **, int *);\n\tvoid (*cache_store)(u64, const struct ulist *, void *);\n\titerate_extent_inodes_t *indirect_ref_iterator;\n\tint (*check_extent_item)(u64, const struct btrfs_extent_item *, const struct extent_buffer *, void *);\n\tbool (*skip_data_ref)(u64, u64, u64, void *);\n\tvoid *user_ctx;\n};\n\nstruct btrfs_balance_args {\n\t__u64 profiles;\n\tunion {\n\t\t__u64 usage;\n\t\tstruct {\n\t\t\t__u32 usage_min;\n\t\t\t__u32 usage_max;\n\t\t};\n\t};\n\t__u64 devid;\n\t__u64 pstart;\n\t__u64 pend;\n\t__u64 vstart;\n\t__u64 vend;\n\t__u64 target;\n\t__u64 flags;\n\tunion {\n\t\t__u64 limit;\n\t\tstruct {\n\t\t\t__u32 limit_min;\n\t\t\t__u32 limit_max;\n\t\t};\n\t};\n\t__u32 stripes_min;\n\t__u32 stripes_max;\n\t__u64 unused[6];\n};\n\nstruct btrfs_balance_progress {\n\t__u64 expected;\n\t__u64 considered;\n\t__u64 completed;\n};\n\nstruct btrfs_balance_control {\n\tstruct btrfs_balance_args data;\n\tstruct btrfs_balance_args meta;\n\tstruct btrfs_balance_args sys;\n\tu64 flags;\n\tstruct btrfs_balance_progress stat;\n};\n\nstruct btrfs_disk_balance_args {\n\t__le64 profiles;\n\tunion {\n\t\t__le64 usage;\n\t\tstruct {\n\t\t\t__le32 usage_min;\n\t\t\t__le32 usage_max;\n\t\t};\n\t};\n\t__le64 devid;\n\t__le64 pstart;\n\t__le64 pend;\n\t__le64 vstart;\n\t__le64 vend;\n\t__le64 target;\n\t__le64 flags;\n\tunion {\n\t\t__le64 limit;\n\t\tstruct {\n\t\t\t__le32 limit_min;\n\t\t\t__le32 limit_max;\n\t\t};\n\t};\n\t__le32 stripes_min;\n\t__le32 stripes_max;\n\t__le64 unused[6];\n};\n\nstruct btrfs_balance_item {\n\t__le64 flags;\n\tstruct btrfs_disk_balance_args data;\n\tstruct btrfs_disk_balance_args meta;\n\tstruct btrfs_disk_balance_args sys;\n\t__le64 unused[4];\n};\n\nstruct btrfs_tree_parent_check {\n\tu64 owner_root;\n\tu64 transid;\n\tstruct btrfs_key first_key;\n\tbool has_first_key;\n\tu8 level;\n};\n\ntypedef void (*btrfs_bio_end_io_t)(struct btrfs_bio *);\n\nstruct btrfs_ordered_extent;\n\nstruct btrfs_ordered_sum;\n\nstruct btrfs_bio {\n\tstruct btrfs_inode *inode;\n\tu64 file_offset;\n\tunion {\n\t\tstruct {\n\t\t\tu8 *csum;\n\t\t\tu8 csum_inline[64];\n\t\t\tstruct bvec_iter saved_iter;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btrfs_ordered_extent *ordered;\n\t\t\tstruct btrfs_ordered_sum *sums;\n\t\t\tstruct work_struct csum_work;\n\t\t\tstruct completion csum_done;\n\t\t\tstruct bvec_iter csum_saved_iter;\n\t\t\tu64 orig_physical;\n\t\t\tu64 orig_logical;\n\t\t};\n\t\tstruct btrfs_tree_parent_check parent_check;\n\t};\n\tstruct work_struct end_io_work;\n\tbtrfs_bio_end_io_t end_io;\n\tvoid *private;\n\tatomic_t pending_ios;\n\tu16 mirror_num;\n\tblk_status_t status;\n\tbool csum_search_commit_root: 1;\n\tbool is_scrub: 1;\n\tbool is_remap: 1;\n\tbool async_csum: 1;\n\tbool can_use_append: 1;\n\tstruct bio bio;\n};\n\nstruct btrfs_bio_ctrl {\n\tstruct btrfs_bio *bbio;\n\tloff_t next_file_offset;\n\tenum btrfs_compression_type compress_type;\n\tu32 len_to_oe_boundary;\n\tblk_opf_t opf;\n\tu64 generation;\n\tbtrfs_bio_end_io_t end_io_func;\n\tstruct writeback_control *wbc;\n\tlong unsigned int submit_bitmap;\n\tstruct readahead_control *ractl;\n\tu64 last_em_start;\n};\n\nstruct btrfs_io_ctl {\n\tvoid *cur;\n\tvoid *orig;\n\tstruct page *page;\n\tstruct page **pages;\n\tstruct btrfs_fs_info *fs_info;\n\tstruct inode *inode;\n\tlong unsigned int size;\n\tint index;\n\tint num_pages;\n\tint entries;\n\tint bitmaps;\n};\n\nstruct btrfs_caching_control;\n\nstruct btrfs_free_space_ctl;\n\nstruct btrfs_chunk_map;\n\nstruct btrfs_block_group {\n\tstruct btrfs_fs_info *fs_info;\n\tstruct btrfs_inode *inode;\n\tspinlock_t lock;\n\tu64 start;\n\tu64 length;\n\tu64 pinned;\n\tu64 reserved;\n\tu64 used;\n\tu64 delalloc_bytes;\n\tu64 bytes_super;\n\tu64 flags;\n\tu64 cache_generation;\n\tu64 global_root_id;\n\tu64 remap_bytes;\n\tu32 identity_remap_count;\n\tu64 last_used;\n\tu64 last_remap_bytes;\n\tu32 last_identity_remap_count;\n\tu64 last_flags;\n\tu32 bitmap_high_thresh;\n\tu32 bitmap_low_thresh;\n\tstruct rw_semaphore data_rwsem;\n\tlong unsigned int full_stripe_len;\n\tlong unsigned int runtime_flags;\n\tunsigned int ro;\n\tint disk_cache_state;\n\tint cached;\n\tstruct btrfs_caching_control *caching_ctl;\n\tstruct btrfs_space_info *space_info;\n\tstruct btrfs_free_space_ctl *free_space_ctl;\n\tstruct rb_node cache_node;\n\tstruct list_head list;\n\trefcount_t refs;\n\tstruct list_head cluster_list;\n\tstruct list_head bg_list;\n\tstruct list_head ro_list;\n\tatomic_t frozen;\n\tstruct list_head discard_list;\n\tint discard_index;\n\tu64 discard_eligible_time;\n\tu64 discard_cursor;\n\tenum btrfs_discard_state discard_state;\n\tstruct list_head dirty_list;\n\tstruct list_head io_list;\n\tstruct btrfs_io_ctl io_ctl;\n\tatomic_t reservations;\n\tatomic_t nocow_writers;\n\tstruct mutex free_space_lock;\n\tbool using_free_space_bitmaps;\n\tbool using_free_space_bitmaps_cached;\n\tint swap_extents;\n\tu64 alloc_offset;\n\tu64 zone_unusable;\n\tu64 zone_capacity;\n\tu64 meta_write_pointer;\n\tstruct btrfs_chunk_map *physical_map;\n\tstruct list_head active_bg_list;\n\tstruct work_struct zone_finish_work;\n\tstruct extent_buffer *last_eb;\n\tenum btrfs_block_group_size_class size_class;\n\tu64 reclaim_mark;\n};\n\nstruct btrfs_block_group_item {\n\t__le64 used;\n\t__le64 chunk_objectid;\n\t__le64 flags;\n};\n\nstruct btrfs_block_group_item_v2 {\n\t__le64 used;\n\t__le64 chunk_objectid;\n\t__le64 flags;\n\t__le64 remap_bytes;\n\t__le32 identity_remap_count;\n} __attribute__((packed));\n\nstruct btrfs_block_rsv {\n\tu64 size;\n\tu64 reserved;\n\tstruct btrfs_space_info *space_info;\n\tspinlock_t lock;\n\tbool full;\n\tbool failfast;\n\tenum btrfs_rsv_type type: 8;\n\tu64 qgroup_rsv_size;\n\tu64 qgroup_rsv_reserved;\n};\n\nstruct btrfs_caching_control {\n\tstruct list_head list;\n\tstruct mutex mutex;\n\twait_queue_head_t wait;\n\tstruct btrfs_work work;\n\tstruct btrfs_block_group *block_group;\n\tatomic_t progress;\n\trefcount_t count;\n};\n\nstruct btrfs_stripe {\n\t__le64 devid;\n\t__le64 offset;\n\t__u8 dev_uuid[16];\n};\n\nstruct btrfs_chunk {\n\t__le64 length;\n\t__le64 owner;\n\t__le64 stripe_len;\n\t__le64 type;\n\t__le32 io_align;\n\t__le32 io_width;\n\t__le32 sector_size;\n\t__le16 num_stripes;\n\t__le16 sub_stripes;\n\tstruct btrfs_stripe stripe;\n};\n\nstruct btrfs_chunk_map {\n\tstruct rb_node rb_node;\n\tint verified_stripes;\n\trefcount_t refs;\n\tu64 start;\n\tu64 chunk_len;\n\tu64 stripe_size;\n\tu64 type;\n\tint io_align;\n\tint io_width;\n\tint num_stripes;\n\tint sub_stripes;\n\tstruct btrfs_io_stripe stripes[0];\n};\n\nstruct btrfs_cmd_header {\n\t__le32 len;\n\t__le16 cmd;\n\t__le32 crc;\n} __attribute__((packed));\n\nstruct btrfs_commit_stats {\n\tu64 commit_count;\n\tu64 max_commit_dur;\n\tu64 last_commit_dur;\n\tu64 total_commit_dur;\n\tu64 critical_section_start_time;\n};\n\nstruct shrinker;\n\nstruct btrfs_compr_pool {\n\tstruct shrinker *shrinker;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tint count;\n\tint thresh;\n};\n\nstruct btrfs_compress_levels {\n\tint min_level;\n\tint max_level;\n\tint default_level;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct btrfs_csum_ctx {\n\tu16 csum_type;\n\tunion {\n\t\tu32 crc32;\n\t\tstruct xxh64_state xxh64;\n\t\tstruct sha256_ctx sha256;\n\t\tstruct blake2b_ctx blake2b;\n\t};\n};\n\nstruct btrfs_csum_item {\n\t__u8 csum;\n};\n\nstruct btrfs_csums {\n\tu16 size;\n\tconst char name[10];\n};\n\nstruct btrfs_data_container {\n\t__u32 bytes_left;\n\t__u32 bytes_missing;\n\t__u32 elem_cnt;\n\t__u32 elem_missed;\n\t__u64 val[0];\n};\n\nstruct btrfs_data_ref {\n\tu64 objectid;\n\tu64 offset;\n};\n\nstruct btrfs_delalloc_work {\n\tstruct inode *inode;\n\tstruct completion completion;\n\tstruct list_head list;\n\tstruct btrfs_work work;\n};\n\nstruct btrfs_disk_key {\n\t__le64 objectid;\n\t__u8 type;\n\t__le64 offset;\n} __attribute__((packed));\n\nstruct btrfs_delayed_extent_op {\n\tstruct btrfs_disk_key key;\n\tbool update_key;\n\tbool update_flags;\n\tu64 flags_to_set;\n};\n\nstruct btrfs_delayed_node;\n\nstruct btrfs_delayed_item {\n\tstruct rb_node rb_node;\n\tu64 index;\n\tstruct list_head tree_list;\n\tstruct list_head readdir_list;\n\tstruct list_head log_list;\n\tu64 bytes_reserved;\n\tstruct btrfs_delayed_node *delayed_node;\n\trefcount_t refs;\n\tenum btrfs_delayed_item_type type: 8;\n\tbool logged;\n\tu16 data_len;\n\tchar data[0];\n};\n\nstruct btrfs_timespec {\n\t__le64 sec;\n\t__le32 nsec;\n} __attribute__((packed));\n\nstruct btrfs_inode_item {\n\t__le64 generation;\n\t__le64 transid;\n\t__le64 size;\n\t__le64 nbytes;\n\t__le64 block_group;\n\t__le32 nlink;\n\t__le32 uid;\n\t__le32 gid;\n\t__le32 mode;\n\t__le64 rdev;\n\t__le64 flags;\n\t__le64 sequence;\n\t__le64 reserved[4];\n\tstruct btrfs_timespec atime;\n\tstruct btrfs_timespec ctime;\n\tstruct btrfs_timespec mtime;\n\tstruct btrfs_timespec otime;\n};\n\nstruct btrfs_ref_tracker_dir {\n\tstruct {} tracker;\n};\n\nstruct btrfs_ref_tracker {\n\tstruct {} tracker;\n};\n\nstruct btrfs_delayed_node {\n\tu64 inode_id;\n\tu64 bytes_reserved;\n\tstruct btrfs_root *root;\n\tstruct list_head n_list;\n\tstruct list_head p_list;\n\tstruct rb_root_cached ins_root;\n\tstruct rb_root_cached del_root;\n\tstruct mutex mutex;\n\tstruct btrfs_inode_item inode_item;\n\trefcount_t refs;\n\tint count;\n\tu64 index_cnt;\n\tlong unsigned int flags;\n\tu32 curr_index_batch_size;\n\tu32 index_item_leaves;\n\tstruct btrfs_ref_tracker_dir ref_dir;\n\tstruct btrfs_ref_tracker node_list_tracker;\n\tstruct btrfs_ref_tracker inode_cache_tracker;\n};\n\nstruct btrfs_delayed_ref_head {\n\tu64 bytenr;\n\tu64 num_bytes;\n\tstruct mutex mutex;\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct rb_root_cached ref_tree;\n\tstruct list_head ref_add_list;\n\tstruct btrfs_delayed_extent_op *extent_op;\n\tint total_ref_mod;\n\tint ref_mod;\n\tu64 owning_root;\n\tu64 reserved_bytes;\n\tu8 level;\n\tbool must_insert_reserved;\n\tbool is_data;\n\tbool is_system;\n\tbool processing;\n\tbool tracked;\n};\n\nstruct btrfs_tree_ref {\n\tint level;\n};\n\nstruct btrfs_delayed_ref_node {\n\tstruct rb_node ref_node;\n\tstruct list_head add_list;\n\tu64 bytenr;\n\tu64 num_bytes;\n\tu64 seq;\n\tu64 ref_root;\n\tu64 parent;\n\trefcount_t refs;\n\tint ref_mod;\n\tunsigned int action: 8;\n\tunsigned int type: 8;\n\tunion {\n\t\tstruct btrfs_tree_ref tree_ref;\n\t\tstruct btrfs_data_ref data_ref;\n\t};\n};\n\nstruct btrfs_delayed_ref_root {\n\tstruct xarray head_refs;\n\tstruct xarray dirty_extents;\n\tspinlock_t lock;\n\tlong unsigned int num_heads;\n\tlong unsigned int num_heads_ready;\n\tu64 pending_csums;\n\tlong unsigned int flags;\n\tu64 run_delayed_start;\n\tu64 qgroup_to_skip;\n};\n\nstruct btrfs_delayed_root {\n\tspinlock_t lock;\n\tint nodes;\n\tstruct list_head node_list;\n\tstruct list_head prepare_list;\n\tatomic_t items;\n\tatomic_t items_seq;\n\twait_queue_head_t wait;\n};\n\nstruct btrfs_dev_extent {\n\t__le64 chunk_tree;\n\t__le64 chunk_objectid;\n\t__le64 chunk_offset;\n\t__le64 length;\n\t__u8 chunk_tree_uuid[16];\n};\n\nstruct btrfs_dev_item {\n\t__le64 devid;\n\t__le64 total_bytes;\n\t__le64 bytes_used;\n\t__le32 io_align;\n\t__le32 io_width;\n\t__le32 sector_size;\n\t__le64 type;\n\t__le64 generation;\n\t__le64 start_offset;\n\t__le32 dev_group;\n\t__u8 seek_speed;\n\t__u8 bandwidth;\n\t__u8 uuid[16];\n\t__u8 fsid[16];\n} __attribute__((packed));\n\nstruct btrfs_dev_lookup_args {\n\tu64 devid;\n\tu8 *uuid;\n\tu8 *fsid;\n\tdev_t devt;\n\tbool missing;\n};\n\nstruct btrfs_scrub_progress {\n\t__u64 data_extents_scrubbed;\n\t__u64 tree_extents_scrubbed;\n\t__u64 data_bytes_scrubbed;\n\t__u64 tree_bytes_scrubbed;\n\t__u64 read_errors;\n\t__u64 csum_errors;\n\t__u64 verify_errors;\n\t__u64 no_csum;\n\t__u64 csum_discards;\n\t__u64 super_errors;\n\t__u64 malloc_errors;\n\t__u64 uncorrectable_errors;\n\t__u64 corrected_errors;\n\t__u64 last_physical;\n\t__u64 unverified_errors;\n};\n\nstruct btrfs_dev_replace {\n\tu64 replace_state;\n\ttime64_t time_started;\n\ttime64_t time_stopped;\n\tatomic64_t num_write_errors;\n\tatomic64_t num_uncorrectable_read_errors;\n\tu64 cursor_left;\n\tu64 committed_cursor_left;\n\tu64 cursor_left_last_write_of_item;\n\tu64 cursor_right;\n\tu64 cont_reading_from_srcdev_mode;\n\tint is_valid;\n\tint item_needs_writeback;\n\tstruct btrfs_device *srcdev;\n\tstruct btrfs_device *tgtdev;\n\tstruct mutex lock_finishing_cancel_unmount;\n\tstruct rw_semaphore rwsem;\n\tstruct btrfs_scrub_progress scrub_progress;\n\tstruct percpu_counter bio_counter;\n\twait_queue_head_t replace_wait;\n\tstruct task_struct *replace_task;\n};\n\nstruct btrfs_dev_replace_item {\n\t__le64 src_devid;\n\t__le64 cursor_left;\n\t__le64 cursor_right;\n\t__le64 cont_reading_from_srcdev_mode;\n\t__le64 replace_state;\n\t__le64 time_started;\n\t__le64 time_stopped;\n\t__le64 num_write_errors;\n\t__le64 num_uncorrectable_read_errors;\n};\n\nstruct btrfs_dev_stats_item {\n\t__le64 values[5];\n};\n\nstruct extent_io_tree {\n\tstruct rb_root state;\n\tunion {\n\t\tstruct btrfs_fs_info *fs_info;\n\t\tstruct btrfs_inode *inode;\n\t};\n\tu8 owner;\n\tspinlock_t lock;\n};\n\nstruct btrfs_fs_devices;\n\nstruct btrfs_zoned_device_info;\n\nstruct scrub_ctx;\n\nstruct btrfs_device {\n\tstruct list_head dev_list;\n\tstruct list_head dev_alloc_list;\n\tstruct list_head post_commit_list;\n\tstruct btrfs_fs_devices *fs_devices;\n\tstruct btrfs_fs_info *fs_info;\n\tconst char *name;\n\tu64 generation;\n\tstruct file *bdev_file;\n\tstruct block_device *bdev;\n\tstruct btrfs_zoned_device_info *zone_info;\n\tlong unsigned int dev_state;\n\tu64 devid;\n\tu64 total_bytes;\n\tu64 disk_total_bytes;\n\tu64 bytes_used;\n\tu32 io_align;\n\tu32 io_width;\n\tu64 type;\n\tatomic_t sb_write_errors;\n\tu32 sector_size;\n\tu8 uuid[16];\n\tu64 commit_total_bytes;\n\tu64 commit_bytes_used;\n\tstruct bio flush_bio;\n\tstruct completion flush_wait;\n\tstruct scrub_ctx *scrub_ctx;\n\tint dev_stats_valid;\n\tatomic_t dev_stats_ccnt;\n\tatomic_t dev_stat_values[5];\n\tdev_t devt;\n\tstruct extent_io_tree alloc_state;\n\tstruct completion kobj_unregister;\n\tstruct kobject devid_kobj;\n\tu64 scrub_speed_max;\n};\n\nstruct btrfs_device_info {\n\tstruct btrfs_device *dev;\n\tu64 dev_offset;\n\tu64 max_avail;\n\tu64 total_avail;\n};\n\nstruct extent_changeset;\n\nstruct btrfs_dio_data {\n\tssize_t submitted;\n\tstruct extent_changeset *data_reserved;\n\tstruct btrfs_ordered_extent *ordered;\n\tbool data_space_reserved;\n\tbool nocow_done;\n};\n\nstruct btrfs_dio_private {\n\tu64 file_offset;\n\tu32 bytes;\n\tstruct btrfs_bio bbio;\n};\n\nstruct btrfs_dir_item {\n\tstruct btrfs_disk_key location;\n\t__le64 transid;\n\t__le16 data_len;\n\t__le16 name_len;\n\t__u8 type;\n} __attribute__((packed));\n\nstruct btrfs_dir_list {\n\tu64 ino;\n\tstruct list_head list;\n};\n\nstruct btrfs_dir_log_item {\n\t__le64 end;\n};\n\nstruct btrfs_discard_ctl {\n\tstruct workqueue_struct *discard_workers;\n\tstruct delayed_work work;\n\tspinlock_t lock;\n\tstruct btrfs_block_group *block_group;\n\tstruct list_head discard_list[3];\n\tu64 prev_discard;\n\tu64 prev_discard_time;\n\tatomic_t discardable_extents;\n\tatomic64_t discardable_bytes;\n\tu64 max_discard_size;\n\tu64 delay_ms;\n\tu32 iops_limit;\n\tu32 kbps_limit;\n\tu64 discard_extent_bytes;\n\tu64 discard_bitmap_bytes;\n\tatomic64_t discard_bytes_saved;\n};\n\nstruct btrfs_discard_stripe {\n\tstruct btrfs_device *dev;\n\tu64 physical;\n\tu64 length;\n};\n\nstruct btrfs_drew_lock {\n\tatomic_t readers;\n\tatomic_t writers;\n\twait_queue_head_t pending_writers;\n\twait_queue_head_t pending_readers;\n};\n\nstruct btrfs_drop_extents_args {\n\tstruct btrfs_path *path;\n\tu64 start;\n\tu64 end;\n\tbool drop_cache;\n\tbool replace_extent;\n\tu32 extent_item_size;\n\tu64 drop_end;\n\tu64 bytes_found;\n\tbool extent_inserted;\n};\n\nstruct btrfs_eb_write_context {\n\tstruct writeback_control *wbc;\n\tstruct extent_buffer *eb;\n\tstruct btrfs_block_group *zoned_bg;\n};\n\nstruct btrfs_em_shrink_ctx {\n\tlong int nr_to_scan;\n\tlong int scanned;\n};\n\nstruct btrfs_encoded_read_private {\n\tstruct completion *sync_reads;\n\tvoid *uring_ctx;\n\trefcount_t pending_refs;\n\tblk_status_t status;\n};\n\nstruct btrfs_extent_data_ref {\n\t__le64 root;\n\t__le64 objectid;\n\t__le64 offset;\n\t__le32 count;\n} __attribute__((packed));\n\nstruct btrfs_extent_inline_ref {\n\t__u8 type;\n\t__le64 offset;\n} __attribute__((packed));\n\nstruct btrfs_extent_item {\n\t__le64 refs;\n\t__le64 generation;\n\t__le64 flags;\n};\n\nstruct btrfs_extent_owner_ref {\n\t__le64 root_id;\n};\n\nstruct btrfs_failed_bio {\n\tstruct btrfs_bio *bbio;\n\tint num_copies;\n\tatomic_t repair_count;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct btrfs_feature_attr {\n\tstruct kobj_attribute kobj_attr;\n\tenum btrfs_feature_set feature_set;\n\tu64 feature_bit;\n};\n\nstruct btrfs_fid {\n\tu64 objectid;\n\tu64 root_objectid;\n\tu32 gen;\n\tu64 parent_objectid;\n\tu32 parent_gen;\n\tu64 parent_root_objectid;\n} __attribute__((packed));\n\nstruct btrfs_fiemap_entry {\n\tu64 offset;\n\tu64 phys;\n\tu64 len;\n\tu32 flags;\n};\n\nstruct btrfs_file_extent {\n\tu64 disk_bytenr;\n\tu64 disk_num_bytes;\n\tu64 num_bytes;\n\tu64 ram_bytes;\n\tu64 offset;\n\tu8 compression;\n};\n\nstruct btrfs_file_extent_item {\n\t__le64 generation;\n\t__le64 ram_bytes;\n\t__u8 compression;\n\t__u8 encryption;\n\t__le16 other_encoding;\n\t__u8 type;\n\t__le64 disk_bytenr;\n\t__le64 disk_num_bytes;\n\t__le64 offset;\n\t__le64 num_bytes;\n} __attribute__((packed));\n\nstruct extent_state;\n\nstruct btrfs_file_private {\n\tvoid *filldir_buf;\n\tu64 last_index;\n\tstruct extent_state *llseek_cached_state;\n\tstruct task_struct *owner_task;\n};\n\nstruct btrfs_folio_state {\n\tspinlock_t lock;\n\tunion {\n\t\tatomic_t eb_refs;\n\t\tatomic_t nr_locked;\n\t};\n\tlong unsigned int bitmaps[0];\n};\n\nstruct btrfs_free_cluster {\n\tspinlock_t lock;\n\tspinlock_t refill_lock;\n\tstruct rb_root root;\n\tu64 max_size;\n\tu64 window_start;\n\tbool fragmented;\n\tstruct btrfs_block_group *block_group;\n\tstruct list_head block_group_list;\n};\n\nstruct btrfs_free_space {\n\tstruct rb_node offset_index;\n\tstruct rb_node bytes_index;\n\tu64 offset;\n\tu64 bytes;\n\tu64 max_extent_size;\n\tlong unsigned int *bitmap;\n\tstruct list_head list;\n\tenum btrfs_trim_state trim_state;\n\ts32 bitmap_extents;\n};\n\nstruct btrfs_free_space_op;\n\nstruct btrfs_free_space_ctl {\n\tspinlock_t tree_lock;\n\tstruct rb_root free_space_offset;\n\tstruct rb_root_cached free_space_bytes;\n\tu64 free_space;\n\tint extents_thresh;\n\tint free_extents;\n\tint total_bitmaps;\n\tint unit;\n\tu64 start;\n\ts32 discardable_extents[2];\n\ts64 discardable_bytes[2];\n\tconst struct btrfs_free_space_op *op;\n\tstruct btrfs_block_group *block_group;\n\tstruct mutex cache_writeout_mutex;\n\tstruct list_head trimming_ranges;\n};\n\nstruct btrfs_free_space_entry {\n\t__le64 offset;\n\t__le64 bytes;\n\t__u8 type;\n} __attribute__((packed));\n\nstruct btrfs_free_space_header {\n\tstruct btrfs_disk_key location;\n\t__le64 generation;\n\t__le64 num_entries;\n\t__le64 num_bitmaps;\n} __attribute__((packed));\n\nstruct btrfs_free_space_info {\n\t__le32 extent_count;\n\t__le32 flags;\n};\n\nstruct btrfs_free_space_op {\n\tbool (*use_bitmap)(struct btrfs_free_space_ctl *, struct btrfs_free_space *);\n};\n\nstruct btrfs_fs_context {\n\tchar *subvol_name;\n\tu64 subvol_objectid;\n\tu64 max_inline;\n\tu32 commit_interval;\n\tu32 metadata_ratio;\n\tu32 thread_pool_size;\n\tlong long unsigned int mount_opt;\n\tlong unsigned int compress_type: 4;\n\tint compress_level;\n\trefcount_t refs;\n};\n\nstruct btrfs_fs_devices {\n\tu8 fsid[16];\n\tu8 metadata_uuid[16];\n\tstruct list_head fs_list;\n\tu64 num_devices;\n\tu64 open_devices;\n\tu64 rw_devices;\n\tu64 missing_devices;\n\tu64 total_rw_bytes;\n\tu64 total_devices;\n\tu64 latest_generation;\n\tstruct btrfs_device *latest_dev;\n\tstruct mutex device_list_mutex;\n\tstruct list_head devices;\n\tstruct list_head alloc_list;\n\tstruct list_head seed_list;\n\tint opened;\n\tint holding;\n\tbool rotating;\n\tbool discardable;\n\tbool seeding;\n\tbool temp_fsid;\n\tbool collect_fs_stats;\n\tstruct btrfs_fs_info *fs_info;\n\tstruct kobject fsid_kobj;\n\tstruct kobject *devices_kobj;\n\tstruct kobject *devinfo_kobj;\n\tstruct completion kobj_unregister;\n\tenum btrfs_chunk_allocation_policy chunk_alloc_policy;\n\tenum btrfs_read_policy read_policy;\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct btrfs_transaction;\n\nstruct btrfs_super_block;\n\nstruct btrfs_stripe_hash_table;\n\nstruct reloc_control;\n\nstruct btrfs_fs_info {\n\tu8 chunk_tree_uuid[16];\n\tlong unsigned int flags;\n\tstruct btrfs_root *tree_root;\n\tstruct btrfs_root *chunk_root;\n\tstruct btrfs_root *dev_root;\n\tstruct btrfs_root *fs_root;\n\tstruct btrfs_root *quota_root;\n\tstruct btrfs_root *uuid_root;\n\tstruct btrfs_root *data_reloc_root;\n\tstruct btrfs_root *block_group_root;\n\tstruct btrfs_root *stripe_root;\n\tstruct btrfs_root *remap_root;\n\tstruct btrfs_root *log_root_tree;\n\trwlock_t global_root_lock;\n\tstruct rb_root global_root_tree;\n\tspinlock_t fs_roots_radix_lock;\n\tstruct xarray fs_roots_radix;\n\trwlock_t block_group_cache_lock;\n\tstruct rb_root_cached block_group_cache_tree;\n\tatomic64_t free_chunk_space;\n\tstruct extent_io_tree excluded_extents;\n\tstruct rb_root_cached mapping_tree;\n\trwlock_t mapping_tree_lock;\n\tstruct btrfs_block_rsv global_block_rsv;\n\tstruct btrfs_block_rsv trans_block_rsv;\n\tstruct btrfs_block_rsv chunk_block_rsv;\n\tstruct btrfs_block_rsv remap_block_rsv;\n\tstruct btrfs_block_rsv delayed_block_rsv;\n\tstruct btrfs_block_rsv delayed_refs_rsv;\n\tstruct btrfs_block_rsv treelog_rsv;\n\tstruct btrfs_block_rsv empty_block_rsv;\n\tu64 generation;\n\tu64 last_trans_committed;\n\tu64 last_reloc_trans;\n\tu64 last_trans_log_full_commit;\n\tlong long unsigned int mount_opt;\n\tvoid *compr_wsm[4];\n\tint compress_type;\n\tint compress_level;\n\tu32 commit_interval;\n\tu64 max_inline;\n\tstruct btrfs_transaction *running_transaction;\n\twait_queue_head_t transaction_throttle;\n\twait_queue_head_t transaction_wait;\n\twait_queue_head_t transaction_blocked_wait;\n\twait_queue_head_t async_submit_wait;\n\tspinlock_t super_lock;\n\tstruct btrfs_super_block *super_copy;\n\tstruct btrfs_super_block *super_for_commit;\n\tstruct super_block *sb;\n\tstruct inode *btree_inode;\n\tstruct mutex tree_log_mutex;\n\tstruct mutex transaction_kthread_mutex;\n\tstruct mutex cleaner_mutex;\n\tstruct mutex chunk_mutex;\n\tstruct mutex remap_mutex;\n\tstruct mutex ro_block_group_mutex;\n\tstruct btrfs_stripe_hash_table *stripe_hash_table;\n\tstruct mutex ordered_operations_mutex;\n\tstruct rw_semaphore commit_root_sem;\n\tstruct rw_semaphore cleanup_work_sem;\n\tstruct rw_semaphore subvol_sem;\n\tspinlock_t trans_lock;\n\tstruct mutex reloc_mutex;\n\tstruct list_head trans_list;\n\tstruct list_head dead_roots;\n\tstruct list_head caching_block_groups;\n\tspinlock_t delayed_iput_lock;\n\tstruct list_head delayed_iputs;\n\tatomic_t nr_delayed_iputs;\n\twait_queue_head_t delayed_iputs_wait;\n\tatomic64_t tree_mod_seq;\n\trwlock_t tree_mod_log_lock;\n\tstruct rb_root tree_mod_log;\n\tstruct list_head tree_mod_seq_list;\n\tatomic_t async_delalloc_pages;\n\tspinlock_t ordered_root_lock;\n\tstruct list_head ordered_roots;\n\tstruct mutex delalloc_root_mutex;\n\tspinlock_t delalloc_root_lock;\n\tstruct list_head delalloc_roots;\n\tstruct btrfs_workqueue *workers;\n\tstruct btrfs_workqueue *delalloc_workers;\n\tstruct btrfs_workqueue *flush_workers;\n\tstruct workqueue_struct *endio_workers;\n\tstruct workqueue_struct *endio_meta_workers;\n\tstruct workqueue_struct *rmw_workers;\n\tstruct btrfs_workqueue *endio_write_workers;\n\tstruct btrfs_workqueue *endio_freespace_worker;\n\tstruct btrfs_workqueue *caching_workers;\n\tstruct btrfs_workqueue *fixup_workers;\n\tstruct btrfs_workqueue *delayed_workers;\n\tstruct task_struct *transaction_kthread;\n\tstruct task_struct *cleaner_kthread;\n\tu32 thread_pool_size;\n\tstruct kobject *space_info_kobj;\n\tstruct kobject *qgroups_kobj;\n\tstruct kobject *discard_kobj;\n\tstruct percpu_counter stats_read_blocks;\n\tstruct percpu_counter dirty_metadata_bytes;\n\tstruct percpu_counter delalloc_bytes;\n\tstruct percpu_counter ordered_bytes;\n\ts32 dirty_metadata_batch;\n\ts32 delalloc_batch;\n\tstruct percpu_counter evictable_extent_maps;\n\tu64 em_shrinker_last_root;\n\tu64 em_shrinker_last_ino;\n\tatomic64_t em_shrinker_nr_to_scan;\n\tstruct work_struct em_shrinker_work;\n\tstruct list_head dirty_cowonly_roots;\n\tstruct btrfs_fs_devices *fs_devices;\n\tstruct list_head space_info;\n\tstruct btrfs_space_info *data_sinfo;\n\tstruct reloc_control *reloc_ctl;\n\tstruct btrfs_free_cluster data_alloc_cluster;\n\tstruct btrfs_free_cluster meta_alloc_cluster;\n\tspinlock_t defrag_inodes_lock;\n\tstruct rb_root defrag_inodes;\n\tatomic_t defrag_running;\n\tseqlock_t profiles_lock;\n\tu64 avail_data_alloc_bits;\n\tu64 avail_metadata_alloc_bits;\n\tu64 avail_system_alloc_bits;\n\tspinlock_t balance_lock;\n\tstruct mutex balance_mutex;\n\tatomic_t balance_pause_req;\n\tatomic_t balance_cancel_req;\n\tstruct btrfs_balance_control *balance_ctl;\n\twait_queue_head_t balance_wait_q;\n\tatomic_t reloc_cancel_req;\n\tu32 data_chunk_allocations;\n\tu32 metadata_ratio;\n\tstruct mutex scrub_lock;\n\tatomic_t scrubs_running;\n\tatomic_t scrub_pause_req;\n\tatomic_t scrubs_paused;\n\tatomic_t scrub_cancel_req;\n\twait_queue_head_t scrub_pause_wait;\n\trefcount_t scrub_workers_refcnt;\n\tstruct workqueue_struct *scrub_workers;\n\tstruct btrfs_discard_ctl discard_ctl;\n\tu64 qgroup_flags;\n\tstruct rb_root qgroup_tree;\n\tspinlock_t qgroup_lock;\n\tstruct mutex qgroup_ioctl_lock;\n\tstruct list_head dirty_qgroups;\n\tu64 qgroup_seq;\n\tstruct mutex qgroup_rescan_lock;\n\tstruct btrfs_key qgroup_rescan_progress;\n\tstruct btrfs_workqueue *qgroup_rescan_workers;\n\tstruct completion qgroup_rescan_completion;\n\tstruct btrfs_work qgroup_rescan_work;\n\tbool qgroup_rescan_running;\n\tu8 qgroup_drop_subtree_thres;\n\tu64 qgroup_enable_gen;\n\tint fs_error;\n\tlong unsigned int fs_state;\n\tstruct btrfs_delayed_root delayed_root;\n\tstruct xarray buffer_tree;\n\tint backup_root_index;\n\tstruct btrfs_dev_replace dev_replace;\n\tstruct semaphore uuid_tree_rescan_sem;\n\tstruct work_struct async_reclaim_work;\n\tstruct work_struct async_data_reclaim_work;\n\tstruct work_struct preempt_reclaim_work;\n\tstruct work_struct reclaim_bgs_work;\n\tstruct list_head reclaim_bgs;\n\tint bg_reclaim_threshold;\n\tspinlock_t unused_bgs_lock;\n\tstruct list_head unused_bgs;\n\tstruct list_head fully_remapped_bgs;\n\tstruct mutex unused_bg_unpin_mutex;\n\tstruct mutex reclaim_bgs_lock;\n\tu32 nodesize;\n\tu32 nodesize_bits;\n\tu32 sectorsize;\n\tu32 sectorsize_bits;\n\tu32 block_min_order;\n\tu32 block_max_order;\n\tu32 stripesize;\n\tu32 csum_size;\n\tu32 csums_per_leaf;\n\tu32 csum_type;\n\tu64 max_extent_size;\n\tspinlock_t swapfile_pins_lock;\n\tstruct rb_root swapfile_pins;\n\tenum btrfs_exclusive_operation exclusive_operation;\n\tu64 zone_size;\n\tstruct queue_limits limits;\n\tu64 max_zone_append_size;\n\tstruct mutex zoned_meta_io_lock;\n\tspinlock_t treelog_bg_lock;\n\tu64 treelog_bg;\n\tspinlock_t relocation_bg_lock;\n\tu64 data_reloc_bg;\n\tstruct mutex zoned_data_reloc_io_lock;\n\tstruct btrfs_block_group *active_meta_bg;\n\tstruct btrfs_block_group *active_system_bg;\n\tu64 nr_global_roots;\n\tspinlock_t zone_active_bgs_lock;\n\tstruct list_head zone_active_bgs;\n\tstruct btrfs_commit_stats commit_stats;\n\tu64 last_root_drop_gen;\n\tstruct lockdep_map btrfs_trans_num_writers_map;\n\tstruct lockdep_map btrfs_trans_num_extwriters_map;\n\tstruct lockdep_map btrfs_state_change_map[4];\n\tstruct lockdep_map btrfs_trans_pending_ordered_map;\n\tstruct lockdep_map btrfs_ordered_extent_map;\n};\n\nstruct btrfs_header {\n\t__u8 csum[32];\n\t__u8 fsid[16];\n\t__le64 bytenr;\n\t__le64 flags;\n\t__u8 chunk_tree_uuid[16];\n\t__le64 generation;\n\t__le64 owner;\n\t__le32 nritems;\n\t__u8 level;\n} __attribute__((packed));\n\nstruct btrfs_iget_args {\n\tu64 ino;\n\tstruct btrfs_root *root;\n};\n\nstruct btrfs_ino_list {\n\tu64 ino;\n\tu64 parent;\n\tstruct list_head list;\n};\n\nstruct extent_map_tree {\n\tstruct rb_root root;\n\tstruct list_head modified_extents;\n\trwlock_t lock;\n};\n\nstruct btrfs_inode {\n\tstruct btrfs_root *root;\n\tu8 prop_compress;\n\tu8 defrag_compress;\n\ts8 defrag_compress_level;\n\tspinlock_t lock;\n\tstruct extent_map_tree extent_tree;\n\tstruct extent_io_tree io_tree;\n\tstruct extent_io_tree *file_extent_tree;\n\tstruct mutex log_mutex;\n\tunsigned int outstanding_extents;\n\tspinlock_t ordered_tree_lock;\n\tstruct rb_root ordered_tree;\n\tstruct rb_node *ordered_tree_last;\n\tstruct list_head delalloc_inodes;\n\tlong unsigned int runtime_flags;\n\tu64 generation;\n\tu64 last_trans;\n\tu64 logged_trans;\n\tint last_sub_trans;\n\tint last_log_commit;\n\tunion {\n\t\tu64 delalloc_bytes;\n\t\tu64 first_dir_index_to_log;\n\t};\n\tunion {\n\t\tu64 new_delalloc_bytes;\n\t\tu64 last_dir_index_offset;\n\t};\n\tunion {\n\t\tu64 defrag_bytes;\n\t\tu64 reloc_block_group_start;\n\t};\n\tu64 disk_i_size;\n\tunion {\n\t\tu64 index_cnt;\n\t\tu64 csum_bytes;\n\t};\n\tu64 dir_index;\n\tu64 last_unlink_trans;\n\tunion {\n\t\tu64 last_reflink_trans;\n\t\tu64 ref_root_id;\n\t};\n\tu32 flags;\n\tu32 ro_flags;\n\tstruct btrfs_block_rsv block_rsv;\n\tstruct btrfs_delayed_node *delayed_node;\n\tu64 i_otime_sec;\n\tu32 i_otime_nsec;\n\tstruct list_head delayed_iput;\n\tstruct rw_semaphore i_mmap_lock;\n\tstruct inode vfs_inode;\n};\n\nstruct btrfs_inode_extref {\n\t__le64 parent_objectid;\n\t__le64 index;\n\t__le16 name_len;\n\t__u8 name[0];\n} __attribute__((packed));\n\nstruct btrfs_inode_info {\n\tu64 size;\n\tu64 gen;\n\tu64 mode;\n\tu64 uid;\n\tu64 gid;\n\tu64 rdev;\n\tu64 fileattr;\n\tu64 nlink;\n};\n\nstruct btrfs_inode_ref {\n\t__le64 index;\n\t__le16 name_len;\n} __attribute__((packed));\n\nstruct btrfs_io_context {\n\trefcount_t refs;\n\tstruct btrfs_fs_info *fs_info;\n\tu64 map_type;\n\tstruct bio *orig_bio;\n\tatomic_t error;\n\tu16 max_errors;\n\tbool use_rst;\n\tu64 logical;\n\tu64 size;\n\tstruct list_head rst_ordered_entry;\n\tu16 num_stripes;\n\tu16 mirror_num;\n\tu16 replace_nr_stripes;\n\ts16 replace_stripe_src;\n\tu64 full_stripe_logical;\n\tstruct btrfs_io_stripe stripes[0];\n};\n\nstruct btrfs_io_geometry {\n\tu32 stripe_index;\n\tu32 stripe_nr;\n\tint mirror_num;\n\tint num_stripes;\n\tu64 stripe_offset;\n\tu64 raid56_full_stripe_start;\n\tint max_errors;\n\tenum btrfs_map_op op;\n\tbool use_rst;\n};\n\nstruct btrfs_ioctl_balance_args {\n\t__u64 flags;\n\t__u64 state;\n\tstruct btrfs_balance_args data;\n\tstruct btrfs_balance_args meta;\n\tstruct btrfs_balance_args sys;\n\tstruct btrfs_balance_progress stat;\n\t__u64 unused[72];\n};\n\nstruct btrfs_ioctl_defrag_range_args {\n\t__u64 start;\n\t__u64 len;\n\t__u64 flags;\n\t__u32 extent_thresh;\n\tunion {\n\t\t__u32 compress_type;\n\t\tstruct {\n\t\t\t__u8 type;\n\t\t\t__s8 level;\n\t\t} compress;\n\t};\n\t__u32 unused[4];\n};\n\nstruct btrfs_ioctl_dev_info_args {\n\t__u64 devid;\n\t__u8 uuid[16];\n\t__u64 bytes_used;\n\t__u64 total_bytes;\n\t__u8 fsid[16];\n\t__u64 unused[377];\n\t__u8 path[1024];\n};\n\nstruct btrfs_ioctl_dev_replace_start_params {\n\t__u64 srcdevid;\n\t__u64 cont_reading_from_srcdev_mode;\n\t__u8 srcdev_name[1025];\n\t__u8 tgtdev_name[1025];\n};\n\nstruct btrfs_ioctl_dev_replace_status_params {\n\t__u64 replace_state;\n\t__u64 progress_1000;\n\t__u64 time_started;\n\t__u64 time_stopped;\n\t__u64 num_write_errors;\n\t__u64 num_uncorrectable_read_errors;\n};\n\nstruct btrfs_ioctl_dev_replace_args {\n\t__u64 cmd;\n\t__u64 result;\n\tunion {\n\t\tstruct btrfs_ioctl_dev_replace_start_params start;\n\t\tstruct btrfs_ioctl_dev_replace_status_params status;\n\t};\n\t__u64 spare[64];\n};\n\nstruct btrfs_ioctl_encoded_io_args {\n\tconst struct iovec *iov;\n\tlong unsigned int iovcnt;\n\t__s64 offset;\n\t__u64 flags;\n\t__u64 len;\n\t__u64 unencoded_len;\n\t__u64 unencoded_offset;\n\t__u32 compression;\n\t__u32 encryption;\n\t__u8 reserved[64];\n};\n\nstruct btrfs_ioctl_feature_flags {\n\t__u64 compat_flags;\n\t__u64 compat_ro_flags;\n\t__u64 incompat_flags;\n};\n\nstruct btrfs_ioctl_fs_info_args {\n\t__u64 max_id;\n\t__u64 num_devices;\n\t__u8 fsid[16];\n\t__u32 nodesize;\n\t__u32 sectorsize;\n\t__u32 clone_alignment;\n\t__u16 csum_type;\n\t__u16 csum_size;\n\t__u64 flags;\n\t__u64 generation;\n\t__u8 metadata_uuid[16];\n\t__u8 reserved[944];\n};\n\nstruct btrfs_ioctl_get_dev_stats {\n\t__u64 devid;\n\t__u64 nr_items;\n\t__u64 flags;\n\t__u64 values[5];\n\t__u64 unused[121];\n};\n\nstruct btrfs_ioctl_timespec {\n\t__u64 sec;\n\t__u32 nsec;\n};\n\nstruct btrfs_ioctl_get_subvol_info_args {\n\t__u64 treeid;\n\tchar name[256];\n\t__u64 parent_id;\n\t__u64 dirid;\n\t__u64 generation;\n\t__u64 flags;\n\t__u8 uuid[16];\n\t__u8 parent_uuid[16];\n\t__u8 received_uuid[16];\n\t__u64 ctransid;\n\t__u64 otransid;\n\t__u64 stransid;\n\t__u64 rtransid;\n\tstruct btrfs_ioctl_timespec ctime;\n\tstruct btrfs_ioctl_timespec otime;\n\tstruct btrfs_ioctl_timespec stime;\n\tstruct btrfs_ioctl_timespec rtime;\n\t__u64 reserved[8];\n};\n\nstruct btrfs_ioctl_get_subvol_rootref_args {\n\t__u64 min_treeid;\n\tstruct {\n\t\t__u64 treeid;\n\t\t__u64 dirid;\n\t} rootref[255];\n\t__u8 num_items;\n\t__u8 align[7];\n};\n\nstruct btrfs_ioctl_ino_lookup_args {\n\t__u64 treeid;\n\t__u64 objectid;\n\tchar name[4080];\n};\n\nstruct btrfs_ioctl_ino_lookup_user_args {\n\t__u64 dirid;\n\t__u64 treeid;\n\tchar name[256];\n\tchar path[3824];\n};\n\nstruct btrfs_ioctl_ino_path_args {\n\t__u64 inum;\n\t__u64 size;\n\t__u64 reserved[4];\n\t__u64 fspath;\n};\n\nstruct btrfs_ioctl_logical_ino_args {\n\t__u64 logical;\n\t__u64 size;\n\t__u64 reserved[3];\n\t__u64 flags;\n\t__u64 inodes;\n};\n\nstruct btrfs_ioctl_qgroup_assign_args {\n\t__u64 assign;\n\t__u64 src;\n\t__u64 dst;\n};\n\nstruct btrfs_ioctl_qgroup_create_args {\n\t__u64 create;\n\t__u64 qgroupid;\n};\n\nstruct btrfs_qgroup_limit {\n\t__u64 flags;\n\t__u64 max_rfer;\n\t__u64 max_excl;\n\t__u64 rsv_rfer;\n\t__u64 rsv_excl;\n};\n\nstruct btrfs_ioctl_qgroup_limit_args {\n\t__u64 qgroupid;\n\tstruct btrfs_qgroup_limit lim;\n};\n\nstruct btrfs_ioctl_quota_ctl_args {\n\t__u64 cmd;\n\t__u64 status;\n};\n\nstruct btrfs_ioctl_quota_rescan_args {\n\t__u64 flags;\n\t__u64 progress;\n\t__u64 reserved[6];\n};\n\nstruct btrfs_ioctl_received_subvol_args {\n\tchar uuid[16];\n\t__u64 stransid;\n\t__u64 rtransid;\n\tstruct btrfs_ioctl_timespec stime;\n\tstruct btrfs_ioctl_timespec rtime;\n\t__u64 flags;\n\t__u64 reserved[16];\n};\n\nstruct btrfs_ioctl_timespec_32 {\n\t__u64 sec;\n\t__u32 nsec;\n} __attribute__((packed));\n\nstruct btrfs_ioctl_received_subvol_args_32 {\n\tchar uuid[16];\n\t__u64 stransid;\n\t__u64 rtransid;\n\tstruct btrfs_ioctl_timespec_32 stime;\n\tstruct btrfs_ioctl_timespec_32 rtime;\n\t__u64 flags;\n\t__u64 reserved[16];\n};\n\nstruct btrfs_ioctl_scrub_args {\n\t__u64 devid;\n\t__u64 start;\n\t__u64 end;\n\t__u64 flags;\n\tstruct btrfs_scrub_progress progress;\n\t__u64 unused[109];\n};\n\nstruct btrfs_ioctl_search_key {\n\t__u64 tree_id;\n\t__u64 min_objectid;\n\t__u64 max_objectid;\n\t__u64 min_offset;\n\t__u64 max_offset;\n\t__u64 min_transid;\n\t__u64 max_transid;\n\t__u32 min_type;\n\t__u32 max_type;\n\t__u32 nr_items;\n\t__u32 unused;\n\t__u64 unused1;\n\t__u64 unused2;\n\t__u64 unused3;\n\t__u64 unused4;\n};\n\nstruct btrfs_ioctl_search_args {\n\tstruct btrfs_ioctl_search_key key;\n\tchar buf[3992];\n};\n\nstruct btrfs_ioctl_search_args_v2 {\n\tstruct btrfs_ioctl_search_key key;\n\t__u64 buf_size;\n\t__u64 buf[0];\n};\n\nstruct btrfs_ioctl_search_header {\n\t__u64 transid;\n\t__u64 objectid;\n\t__u64 offset;\n\t__u32 type;\n\t__u32 len;\n};\n\nstruct btrfs_ioctl_send_args {\n\t__s64 send_fd;\n\t__u64 clone_sources_count;\n\t__u64 *clone_sources;\n\t__u64 parent_root;\n\t__u64 flags;\n\t__u32 version;\n\t__u8 reserved[28];\n};\n\nstruct btrfs_ioctl_space_info {\n\t__u64 flags;\n\t__u64 total_bytes;\n\t__u64 used_bytes;\n};\n\nstruct btrfs_ioctl_space_args {\n\t__u64 space_slots;\n\t__u64 total_spaces;\n\tstruct btrfs_ioctl_space_info spaces[0];\n};\n\nstruct btrfs_ioctl_subvol_wait {\n\t__u64 subvolid;\n\t__u32 mode;\n\t__u32 count;\n};\n\nstruct btrfs_ioctl_vol_args {\n\t__s64 fd;\n\tchar name[4088];\n};\n\nstruct btrfs_qgroup_inherit;\n\nstruct btrfs_ioctl_vol_args_v2 {\n\t__s64 fd;\n\t__u64 transid;\n\t__u64 flags;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 size;\n\t\t\tstruct btrfs_qgroup_inherit *qgroup_inherit;\n\t\t};\n\t\t__u64 unused[4];\n\t};\n\tunion {\n\t\tchar name[4040];\n\t\t__u64 devid;\n\t\t__u64 subvolid;\n\t};\n};\n\nstruct btrfs_item {\n\tstruct btrfs_disk_key key;\n\t__le32 offset;\n\t__le32 size;\n} __attribute__((packed));\n\nstruct btrfs_item_batch {\n\tconst struct btrfs_key *keys;\n\tconst u32 *data_sizes;\n\tu32 total_data_size;\n\tint nr;\n};\n\nstruct btrfs_key_ptr {\n\tstruct btrfs_disk_key key;\n\t__le64 blockptr;\n\t__le64 generation;\n} __attribute__((packed));\n\nstruct btrfs_log_ctx {\n\tint log_ret;\n\tint log_transid;\n\tbool log_new_dentries;\n\tbool logging_new_name;\n\tbool logging_new_delayed_dentries;\n\tbool logged_before;\n\tstruct btrfs_inode *inode;\n\tstruct list_head list;\n\tstruct list_head ordered_extents;\n\tstruct list_head conflict_inodes;\n\tint num_conflict_inodes;\n\tbool logging_conflict_inodes;\n\tstruct extent_buffer *scratch_eb;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct btrfs_lru_cache {\n\tstruct list_head lru_list;\n\tstruct maple_tree entries;\n\tunsigned int size;\n\tunsigned int max_size;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nstruct qstr;\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_nokey_name;\n};\n\nstruct btrfs_new_inode_args {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool orphan;\n\tbool subvol;\n\tstruct posix_acl *default_acl;\n\tstruct posix_acl *acl;\n\tstruct fscrypt_name fname;\n};\n\nstruct btrfs_ordered_extent {\n\tu64 file_offset;\n\tu64 num_bytes;\n\tu64 ram_bytes;\n\tu64 disk_bytenr;\n\tu64 disk_num_bytes;\n\tu64 offset;\n\tu64 bytes_left;\n\tu64 truncated_len;\n\tlong unsigned int flags;\n\tint compress_type;\n\tint qgroup_rsv;\n\trefcount_t refs;\n\tstruct btrfs_inode *inode;\n\tstruct list_head list;\n\tstruct list_head log_list;\n\twait_queue_head_t wait;\n\tstruct rb_node rb_node;\n\tstruct list_head root_extent_list;\n\tstruct btrfs_work work;\n\tstruct completion completion;\n\tstruct btrfs_work flush_work;\n\tstruct list_head work_list;\n\tstruct list_head bioc_list;\n};\n\nstruct btrfs_ordered_sum {\n\tu64 logical;\n\tu32 len;\n\tstruct list_head list;\n\tu8 sums[0];\n};\n\nstruct btrfs_path {\n\tstruct extent_buffer *nodes[8];\n\tint slots[8];\n\tu8 locks[8];\n\tu8 reada;\n\tu8 lowest_level;\n\tbool search_for_split: 1;\n\tbool keep_locks: 1;\n\tbool skip_locking: 1;\n\tbool search_commit_root: 1;\n\tbool need_commit_sem: 1;\n\tbool skip_release_on_error: 1;\n\tbool search_for_extension: 1;\n\tbool nowait: 1;\n};\n\nstruct btrfs_root_item;\n\nstruct btrfs_pending_snapshot {\n\tstruct dentry *dentry;\n\tstruct btrfs_inode *dir;\n\tstruct btrfs_root *root;\n\tstruct btrfs_root_item *root_item;\n\tstruct btrfs_root *snap;\n\tstruct btrfs_qgroup_inherit *inherit;\n\tstruct btrfs_path *path;\n\tstruct btrfs_block_rsv block_rsv;\n\tint error;\n\tdev_t anon_dev;\n\tbool readonly;\n\tstruct list_head list;\n};\n\nstruct btrfs_plug_cb {\n\tstruct blk_plug_cb cb;\n\tstruct btrfs_fs_info *info;\n\tstruct list_head rbio_list;\n};\n\nstruct btrfs_qgroup_rsv {\n\tu64 values[3];\n};\n\nstruct btrfs_qgroup {\n\tu64 qgroupid;\n\tu64 rfer;\n\tu64 rfer_cmpr;\n\tu64 excl;\n\tu64 excl_cmpr;\n\tu64 lim_flags;\n\tu64 max_rfer;\n\tu64 max_excl;\n\tu64 rsv_rfer;\n\tu64 rsv_excl;\n\tstruct btrfs_qgroup_rsv rsv;\n\tstruct list_head groups;\n\tstruct list_head members;\n\tstruct list_head dirty;\n\tstruct list_head iterator;\n\tstruct list_head nested_iterator;\n\tstruct rb_node node;\n\tu64 old_refcnt;\n\tu64 new_refcnt;\n\tstruct kobject kobj;\n};\n\nstruct btrfs_qgroup_extent_record {\n\tu64 num_bytes;\n\tu32 data_rsv;\n\tu64 data_rsv_refroot;\n\tstruct ulist *old_roots;\n};\n\nstruct btrfs_qgroup_info_item {\n\t__le64 generation;\n\t__le64 rfer;\n\t__le64 rfer_cmpr;\n\t__le64 excl;\n\t__le64 excl_cmpr;\n};\n\nstruct btrfs_qgroup_inherit {\n\t__u64 flags;\n\t__u64 num_qgroups;\n\t__u64 num_ref_copies;\n\t__u64 num_excl_copies;\n\tstruct btrfs_qgroup_limit lim;\n\t__u64 qgroups[0];\n};\n\nstruct btrfs_qgroup_limit_item {\n\t__le64 flags;\n\t__le64 max_rfer;\n\t__le64 max_excl;\n\t__le64 rsv_rfer;\n\t__le64 rsv_excl;\n};\n\nstruct btrfs_qgroup_list {\n\tstruct list_head next_group;\n\tstruct list_head next_member;\n\tstruct btrfs_qgroup *group;\n\tstruct btrfs_qgroup *member;\n};\n\nstruct btrfs_qgroup_status_item {\n\t__le64 version;\n\t__le64 generation;\n\t__le64 flags;\n\t__le64 rescan;\n\t__le64 enable_gen;\n};\n\nstruct btrfs_qgroup_swapped_block {\n\tstruct rb_node node;\n\tint level;\n\tbool trace_leaf;\n\tu64 subvol_bytenr;\n\tu64 subvol_generation;\n\tu64 reloc_bytenr;\n\tu64 reloc_generation;\n\tu64 last_snapshot;\n\tstruct btrfs_key first_key;\n};\n\nstruct btrfs_qgroup_swapped_blocks {\n\tspinlock_t lock;\n\tbool swapped;\n\tstruct rb_root blocks[8];\n};\n\nstruct btrfs_raid_attr {\n\tu8 sub_stripes;\n\tu8 dev_stripes;\n\tu8 devs_max;\n\tu8 devs_min;\n\tu8 tolerated_failures;\n\tu8 devs_increment;\n\tu8 ncopies;\n\tu8 nparity;\n\tu8 mindev_error;\n\tconst char raid_name[8];\n\tu64 bg_flag;\n};\n\nstruct btrfs_raid_bio {\n\tstruct btrfs_io_context *bioc;\n\tstruct list_head hash_list;\n\tstruct list_head stripe_cache;\n\tstruct work_struct work;\n\tstruct bio_list bio_list;\n\tspinlock_t bio_list_lock;\n\tstruct list_head plug_list;\n\tlong unsigned int flags;\n\tenum btrfs_rbio_ops operation;\n\tu16 nr_pages;\n\tu16 nr_sectors;\n\tu8 nr_data;\n\tu8 real_stripes;\n\tu8 stripe_npages;\n\tu8 stripe_nsectors;\n\tu8 sector_nsteps;\n\tu8 scrubp;\n\tint bio_list_bytes;\n\trefcount_t refs;\n\tatomic_t stripes_pending;\n\twait_queue_head_t io_wait;\n\tlong unsigned int dbitmap;\n\tlong unsigned int finish_pbitmap;\n\tstruct page **stripe_pages;\n\tphys_addr_t *bio_paddrs;\n\tphys_addr_t *stripe_paddrs;\n\tlong unsigned int *stripe_uptodate_bitmap;\n\tvoid **finish_pointers;\n\tlong unsigned int *error_bitmap;\n\tu8 *csum_buf;\n\tlong unsigned int *csum_bitmap;\n};\n\nstruct btrfs_raid_stride {\n\t__le64 devid;\n\t__le64 physical;\n};\n\nstruct btrfs_ref {\n\tenum btrfs_ref_type type;\n\tenum btrfs_delayed_ref_action action;\n\tbool skip_qgroup;\n\tu64 bytenr;\n\tu64 num_bytes;\n\tu64 owning_root;\n\tu64 ref_root;\n\tu64 parent;\n\tunion {\n\t\tstruct btrfs_data_ref data_ref;\n\t\tstruct btrfs_tree_ref tree_ref;\n\t};\n};\n\nstruct btrfs_remap_item {\n\t__le64 address;\n};\n\nstruct btrfs_rename_ctx {\n\tu64 index;\n};\n\nstruct btrfs_replace_extent_info {\n\tu64 disk_offset;\n\tu64 disk_len;\n\tu64 data_offset;\n\tu64 data_len;\n\tu64 file_offset;\n\tchar *extent_buf;\n\tbool is_new_extent;\n\tbool update_times;\n\tint qgroup_reserved;\n\tint insertions;\n};\n\nstruct btrfs_root_item {\n\tstruct btrfs_inode_item inode;\n\t__le64 generation;\n\t__le64 root_dirid;\n\t__le64 bytenr;\n\t__le64 byte_limit;\n\t__le64 bytes_used;\n\t__le64 last_snapshot;\n\t__le64 flags;\n\t__le32 refs;\n\tstruct btrfs_disk_key drop_progress;\n\t__u8 drop_level;\n\t__u8 level;\n\t__le64 generation_v2;\n\t__u8 uuid[16];\n\t__u8 parent_uuid[16];\n\t__u8 received_uuid[16];\n\t__le64 ctransid;\n\t__le64 otransid;\n\t__le64 stransid;\n\t__le64 rtransid;\n\tstruct btrfs_timespec ctime;\n\tstruct btrfs_timespec otime;\n\tstruct btrfs_timespec stime;\n\tstruct btrfs_timespec rtime;\n\t__le64 reserved[8];\n} __attribute__((packed));\n\nstruct btrfs_root {\n\tstruct rb_node rb_node;\n\tstruct extent_buffer *node;\n\tstruct extent_buffer *commit_root;\n\tstruct btrfs_root *log_root;\n\tstruct btrfs_root *reloc_root;\n\tlong unsigned int state;\n\tstruct btrfs_root_item root_item;\n\tstruct btrfs_key root_key;\n\tstruct btrfs_fs_info *fs_info;\n\tstruct extent_io_tree dirty_log_pages;\n\tstruct mutex objectid_mutex;\n\tspinlock_t accounting_lock;\n\tstruct btrfs_block_rsv *block_rsv;\n\tstruct mutex log_mutex;\n\twait_queue_head_t log_writer_wait;\n\twait_queue_head_t log_commit_wait[2];\n\tstruct list_head log_ctxs[2];\n\tatomic_t log_writers;\n\tatomic_t log_commit[2];\n\tatomic_t log_batch;\n\tint log_transid;\n\tint log_transid_committed;\n\tint last_log_commit;\n\tpid_t log_start_pid;\n\tu64 last_trans;\n\tu64 free_objectid;\n\tstruct btrfs_key defrag_progress;\n\tstruct btrfs_key defrag_max;\n\tstruct list_head dirty_list;\n\tstruct list_head root_list;\n\tstruct xarray inodes;\n\tstruct xarray delayed_nodes;\n\tdev_t anon_dev;\n\tspinlock_t root_item_lock;\n\trefcount_t refs;\n\tstruct mutex delalloc_mutex;\n\tspinlock_t delalloc_lock;\n\tstruct list_head delalloc_inodes;\n\tstruct list_head delalloc_root;\n\tu64 nr_delalloc_inodes;\n\tstruct mutex ordered_extent_mutex;\n\tspinlock_t ordered_extent_lock;\n\tstruct list_head ordered_extents;\n\tstruct list_head ordered_root;\n\tu64 nr_ordered_extents;\n\tstruct list_head reloc_dirty_list;\n\tint send_in_progress;\n\tint dedupe_in_progress;\n\tstruct btrfs_drew_lock snapshot_lock;\n\tatomic_t snapshot_force_cow;\n\tspinlock_t qgroup_meta_rsv_lock;\n\tu64 qgroup_meta_rsv_pertrans;\n\tu64 qgroup_meta_rsv_prealloc;\n\twait_queue_head_t qgroup_flush_wait;\n\tatomic_t nr_swapfiles;\n\tstruct btrfs_qgroup_swapped_blocks swapped_blocks;\n\tstruct extent_io_tree log_csum_range;\n\tu64 relocation_src_root;\n};\n\nstruct btrfs_root_backup {\n\t__le64 tree_root;\n\t__le64 tree_root_gen;\n\t__le64 chunk_root;\n\t__le64 chunk_root_gen;\n\t__le64 extent_root;\n\t__le64 extent_root_gen;\n\t__le64 fs_root;\n\t__le64 fs_root_gen;\n\t__le64 dev_root;\n\t__le64 dev_root_gen;\n\t__le64 csum_root;\n\t__le64 csum_root_gen;\n\t__le64 total_bytes;\n\t__le64 bytes_used;\n\t__le64 num_devices;\n\t__le64 unused_64[4];\n\t__u8 tree_root_level;\n\t__u8 chunk_root_level;\n\t__u8 extent_root_level;\n\t__u8 fs_root_level;\n\t__u8 dev_root_level;\n\t__u8 csum_root_level;\n\t__u8 unused_8[10];\n};\n\nstruct btrfs_root_ref {\n\t__le64 dirid;\n\t__le64 sequence;\n\t__le16 name_len;\n} __attribute__((packed));\n\nstruct btrfs_seq_list {\n\tstruct list_head list;\n\tu64 seq;\n};\n\nstruct btrfs_shared_data_ref {\n\t__le32 count;\n};\n\nstruct btrfs_space_info {\n\tstruct btrfs_fs_info *fs_info;\n\tstruct btrfs_space_info *parent;\n\tstruct btrfs_space_info *sub_group[1];\n\tint subgroup_id;\n\tspinlock_t lock;\n\tu64 total_bytes;\n\tu64 bytes_used;\n\tu64 bytes_pinned;\n\tu64 bytes_reserved;\n\tu64 bytes_may_use;\n\tu64 bytes_readonly;\n\tu64 bytes_zone_unusable;\n\tu64 max_extent_size;\n\tu64 chunk_size;\n\tint bg_reclaim_threshold;\n\tint clamp;\n\tbool full;\n\tbool chunk_alloc;\n\tbool flush;\n\tunsigned int force_alloc;\n\tu64 disk_used;\n\tu64 disk_total;\n\tu64 flags;\n\tstruct list_head list;\n\tstruct list_head ro_bgs;\n\tstruct list_head priority_tickets;\n\tstruct list_head tickets;\n\tu64 reclaim_size;\n\tu64 tickets_id;\n\tstruct rw_semaphore groups_sem;\n\tstruct list_head block_groups[9];\n\tstruct kobject kobj;\n\tstruct kobject *block_group_kobjs[9];\n\tu64 reclaim_count;\n\tu64 reclaim_bytes;\n\tu64 reclaim_errors;\n\tbool dynamic_reclaim;\n\tbool periodic_reclaim;\n\tbool periodic_reclaim_ready;\n\ts64 reclaimable_bytes;\n};\n\nstruct btrfs_squota_delta {\n\tu64 root;\n\tu64 num_bytes;\n\tu64 generation;\n\tbool is_inc;\n\tbool is_data;\n};\n\nstruct btrfs_stream_header {\n\tchar magic[13];\n\t__le32 version;\n} __attribute__((packed));\n\nstruct btrfs_stripe_extent {\n\tstruct {\n\t\tstruct {} __empty_strides;\n\t\tstruct btrfs_raid_stride strides[0];\n\t};\n};\n\nstruct btrfs_stripe_hash {\n\tstruct list_head hash_list;\n\tspinlock_t lock;\n};\n\nstruct btrfs_stripe_hash_table {\n\tstruct list_head stripe_cache;\n\tspinlock_t cache_lock;\n\tint cache_size;\n\tstruct btrfs_stripe_hash table[0];\n};\n\nstruct btrfs_super_block {\n\t__u8 csum[32];\n\t__u8 fsid[16];\n\t__le64 bytenr;\n\t__le64 flags;\n\t__le64 magic;\n\t__le64 generation;\n\t__le64 root;\n\t__le64 chunk_root;\n\t__le64 log_root;\n\t__le64 __unused_log_root_transid;\n\t__le64 total_bytes;\n\t__le64 bytes_used;\n\t__le64 root_dir_objectid;\n\t__le64 num_devices;\n\t__le32 sectorsize;\n\t__le32 nodesize;\n\t__le32 __unused_leafsize;\n\t__le32 stripesize;\n\t__le32 sys_chunk_array_size;\n\t__le64 chunk_root_generation;\n\t__le64 compat_flags;\n\t__le64 compat_ro_flags;\n\t__le64 incompat_flags;\n\t__le16 csum_type;\n\t__u8 root_level;\n\t__u8 chunk_root_level;\n\t__u8 log_root_level;\n\tstruct btrfs_dev_item dev_item;\n\tchar label[256];\n\t__le64 cache_generation;\n\t__le64 uuid_tree_generation;\n\t__u8 metadata_uuid[16];\n\t__u64 nr_global_roots;\n\t__le64 remap_root;\n\t__le64 remap_root_generation;\n\t__u8 remap_root_level;\n\t__u8 reserved[199];\n\t__u8 sys_chunk_array[2048];\n\tstruct btrfs_root_backup super_roots[4];\n\t__u8 padding[565];\n} __attribute__((packed));\n\nstruct btrfs_swap_info {\n\tu64 start;\n\tu64 block_start;\n\tu64 block_len;\n\tu64 lowest_ppage;\n\tu64 highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n};\n\nstruct btrfs_swapfile_pin {\n\tstruct rb_node node;\n\tvoid *ptr;\n\tstruct inode *inode;\n\tbool is_block_group;\n\tint bg_extent_count;\n};\n\nstruct btrfs_tlv_header {\n\t__le16 tlv_type;\n\t__le16 tlv_len;\n};\n\nstruct btrfs_trans_handle {\n\tu64 transid;\n\tu64 bytes_reserved;\n\tu64 delayed_refs_bytes_reserved;\n\tu64 chunk_bytes_reserved;\n\tlong unsigned int delayed_ref_updates;\n\tlong unsigned int delayed_ref_csum_deletions;\n\tstruct btrfs_transaction *transaction;\n\tstruct btrfs_block_rsv *block_rsv;\n\tstruct btrfs_block_rsv *orig_rsv;\n\tstruct btrfs_pending_snapshot *pending_snapshot;\n\trefcount_t use_count;\n\tunsigned int type;\n\tshort int aborted;\n\tbool adding_csums;\n\tbool allocating_chunk;\n\tbool removing_chunk;\n\tbool reloc_reserved;\n\tbool in_fsync;\n\tstruct btrfs_fs_info *fs_info;\n\tstruct list_head new_bgs;\n\tstruct btrfs_block_rsv delayed_rsv;\n};\n\nstruct btrfs_transaction {\n\tu64 transid;\n\tatomic_t num_extwriters;\n\tatomic_t num_writers;\n\trefcount_t use_count;\n\tlong unsigned int flags;\n\tenum btrfs_trans_state state;\n\tint aborted;\n\tstruct list_head list;\n\tstruct extent_io_tree dirty_pages;\n\ttime64_t start_time;\n\twait_queue_head_t writer_wait;\n\twait_queue_head_t commit_wait;\n\tstruct list_head pending_snapshots;\n\tstruct list_head dev_update_list;\n\tstruct list_head switch_commits;\n\tstruct list_head dirty_bgs;\n\tstruct list_head io_bgs;\n\tstruct list_head dropped_roots;\n\tstruct extent_io_tree pinned_extents;\n\tstruct mutex cache_write_mutex;\n\tspinlock_t dirty_bgs_lock;\n\tstruct list_head deleted_bgs;\n\tspinlock_t dropped_roots_lock;\n\tstruct btrfs_delayed_ref_root delayed_refs;\n\tstruct btrfs_fs_info *fs_info;\n\tatomic_t pending_ordered;\n\twait_queue_head_t pending_wait;\n};\n\nstruct btrfs_tree_block_info {\n\tstruct btrfs_disk_key key;\n\t__u8 level;\n};\n\nstruct btrfs_trim_range {\n\tu64 start;\n\tu64 bytes;\n\tstruct list_head list;\n};\n\nstruct btrfs_truncate_control {\n\tstruct btrfs_inode *inode;\n\tu64 new_size;\n\tu64 extents_found;\n\tu64 last_size;\n\tu64 sub_bytes;\n\tu64 ino;\n\tu32 min_type;\n\tbool skip_ref_updates;\n\tbool clear_extent_range;\n};\n\nstruct btrfs_uring_encoded_data {\n\tstruct btrfs_ioctl_encoded_io_args args;\n\tstruct iovec iovstack[8];\n\tstruct iovec *iov;\n\tstruct iov_iter iter;\n};\n\nstruct io_uring_cmd;\n\nstruct btrfs_uring_priv {\n\tstruct io_uring_cmd *cmd;\n\tstruct page **pages;\n\tlong unsigned int nr_pages;\n\tstruct kiocb iocb;\n\tstruct iovec *iov;\n\tstruct iov_iter iter;\n\tstruct extent_state *cached_state;\n\tu64 count;\n\tu64 start;\n\tu64 lockend;\n\tint err;\n\tbool compressed;\n};\n\nstruct btrfs_verity_descriptor_item {\n\t__le64 size;\n\t__le64 reserved[2];\n\t__u8 encryption;\n} __attribute__((packed));\n\nstruct btrfs_workqueue {\n\tstruct workqueue_struct *normal_wq;\n\tstruct btrfs_fs_info *fs_info;\n\tstruct list_head ordered_list;\n\tspinlock_t list_lock;\n\tatomic_t pending;\n\tint limit_active;\n\tint current_active;\n\tint thresh;\n\tunsigned int count;\n\tspinlock_t thres_lock;\n};\n\nstruct btrfs_writepage_fixup {\n\tstruct folio *folio;\n\tstruct btrfs_inode *inode;\n\tstruct btrfs_work work;\n};\n\nstruct btrfs_zoned_device_info {\n\tu64 zone_size;\n\tu8 zone_size_shift;\n\tu32 nr_zones;\n\tunsigned int max_active_zones;\n\tint reserved_active_zones;\n\tatomic_t active_zones_left;\n\tlong unsigned int *seq_zones;\n\tlong unsigned int *empty_zones;\n\tlong unsigned int *active_zones;\n\tstruct blk_zone *zone_cache;\n\tstruct blk_zone sb_zones[6];\n};\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct bucket_item {\n\tu32 count;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n};\n\nstruct buffer_data_read_page {\n\tunsigned int order;\n\tstruct buffer_data_page *data;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tunsigned int order;\n\tu32 id: 30;\n\tu32 range: 1;\n\tstruct buffer_data_page *page;\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct bug_entry {\n\tint bug_addr_disp;\n\tint format_disp;\n\tint file_disp;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct cache_info {\n\tchar: 4;\n\tunsigned char scope: 2;\n\tunsigned char type: 2;\n};\n\nunion cache_topology {\n\tstruct cache_info ci[8];\n\tlong unsigned int raw;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nstruct can_nocow_file_extent_args {\n\tu64 start;\n\tu64 end;\n\tbool writeback_path;\n\tbool free_path;\n\tstruct btrfs_file_extent file_extent;\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct cat_datum {\n\tu32 value;\n\tunsigned char isalias;\n};\n\nstruct idset;\n\nstruct subchannel;\n\nstruct cb_data {\n\tvoid *data;\n\tstruct idset *set;\n\tint (*fn_known_sch)(struct subchannel *, void *);\n\tint (*fn_unknown_sch)(struct subchannel_id, void *);\n};\n\nstruct cb_id {\n\t__u32 idx;\n\t__u32 val;\n};\n\nstruct chp_id {\n\t__u8 reserved1;\n\t__u8 cssid;\n\t__u8 reserved2;\n\t__u8 id;\n};\n\nstruct ccl_parm_chpid {\n\tint m;\n\tstruct chp_id chp;\n};\n\nstruct ccl_parm_cssids {\n\t__u8 f_cssid;\n\t__u8 l_cssid;\n};\n\nstruct ccw1 {\n\t__u8 cmd_code;\n\t__u8 flags;\n\t__u16 count;\n\tdma32_t cda;\n};\n\nstruct ccw_dev_id {\n\tu8 ssid;\n\tu16 devno;\n};\n\nstruct ccw_device_id {\n\t__u16 match_flags;\n\t__u16 cu_type;\n\t__u16 dev_type;\n\t__u8 cu_model;\n\t__u8 dev_model;\n\tkernel_ulong_t driver_info;\n};\n\nstruct ccw_device_private;\n\nstruct ccw_driver;\n\nstruct irb;\n\nstruct ccw_device {\n\tspinlock_t *ccwlock;\n\tstruct ccw_device_private *private;\n\tstruct mutex reg_mutex;\n\tstruct ccw_device_id id;\n\tstruct ccw_driver *drv;\n\tstruct device dev;\n\tint online;\n\tvoid (*handler)(struct ccw_device *, long unsigned int, struct irb *);\n};\n\nstruct ciw {\n\t__u32 et: 2;\n\t__u32 reserved: 2;\n\t__u32 ct: 4;\n\t__u32 cmd: 8;\n\t__u32 count: 16;\n};\n\nstruct senseid {\n\tu8 reserved;\n\tu16 cu_type;\n\tu8 cu_model;\n\tu16 dev_type;\n\tu8 dev_model;\n\tu8 unused;\n\tstruct ciw ciw[8];\n} __attribute__((packed));\n\nstruct cmd_scsw {\n\t__u32 key: 4;\n\t__u32 sctl: 1;\n\t__u32 eswf: 1;\n\t__u32 cc: 2;\n\t__u32 fmt: 1;\n\t__u32 pfch: 1;\n\t__u32 isic: 1;\n\t__u32 alcc: 1;\n\t__u32 ssi: 1;\n\t__u32 zcc: 1;\n\t__u32 ectl: 1;\n\t__u32 pno: 1;\n\t__u32 res: 1;\n\t__u32 fctl: 3;\n\t__u32 actl: 7;\n\t__u32 stctl: 5;\n\tdma32_t cpa;\n\t__u32 dstat: 8;\n\t__u32 cstat: 8;\n\t__u32 count: 16;\n};\n\nstruct tm_scsw {\n\tu32 key: 4;\n\tchar: 1;\n\tu32 eswf: 1;\n\tu32 cc: 2;\n\tu32 fmt: 3;\n\tu32 x: 1;\n\tu32 q: 1;\n\tchar: 1;\n\tu32 ectl: 1;\n\tu32 pno: 1;\n\tchar: 1;\n\tu32 fctl: 3;\n\tu32 actl: 7;\n\tu32 stctl: 5;\n\tdma32_t tcw;\n\tu32 dstat: 8;\n\tu32 cstat: 8;\n\tu32 fcxs: 8;\n\tu32 ifob: 1;\n\tu32 sesq: 7;\n};\n\nstruct eadm_scsw {\n\tu32 key: 4;\n\tchar: 1;\n\tu32 eswf: 1;\n\tu32 cc: 2;\n\tchar: 6;\n\tu32 ectl: 1;\n\tshort: 1;\n\tchar: 1;\n\tu32 fctl: 3;\n\tu32 actl: 7;\n\tu32 stctl: 5;\n\tdma32_t aob;\n\tu32 dstat: 8;\n\tu32 cstat: 8;\n};\n\nunion scsw {\n\tstruct cmd_scsw cmd;\n\tstruct tm_scsw tm;\n\tstruct eadm_scsw eadm;\n};\n\nstruct sublog {\n\t__u32 res0: 1;\n\t__u32 esf: 7;\n\t__u32 lpum: 8;\n\t__u32 arep: 1;\n\t__u32 fvf: 5;\n\t__u32 sacc: 2;\n\t__u32 termc: 2;\n\t__u32 devsc: 1;\n\t__u32 serr: 1;\n\t__u32 ioerr: 1;\n\t__u32 seqc: 3;\n};\n\nstruct erw {\n\t__u32 res0: 3;\n\t__u32 auth: 1;\n\t__u32 pvrf: 1;\n\t__u32 cpt: 1;\n\t__u32 fsavf: 1;\n\t__u32 cons: 1;\n\t__u32 scavf: 1;\n\t__u32 fsaf: 1;\n\t__u32 scnt: 6;\n\t__u32 res16: 16;\n};\n\nstruct esw0 {\n\tstruct sublog sublog;\n\tstruct erw erw;\n\tdma32_t faddr[2];\n\tdma32_t saddr;\n};\n\nstruct esw1 {\n\t__u8 zero0;\n\t__u8 lpum;\n\t__u16 zero16;\n\tstruct erw erw;\n\t__u32 zeros[3];\n};\n\nstruct esw2 {\n\t__u8 zero0;\n\t__u8 lpum;\n\t__u16 dcti;\n\tstruct erw erw;\n\t__u32 zeros[3];\n};\n\nstruct esw3 {\n\t__u8 zero0;\n\t__u8 lpum;\n\t__u16 res;\n\tstruct erw erw;\n\t__u32 zeros[3];\n};\n\nstruct erw_eadm {\n\tshort: 16;\n\t__u32 b: 1;\n\t__u32 r: 1;\n};\n\nstruct esw_eadm {\n\t__u32 sublog;\n\tstruct erw_eadm erw;\n\tlong: 64;\n\tint: 32;\n};\n\nstruct irb {\n\tunion scsw scsw;\n\tunion {\n\t\tstruct esw0 esw0;\n\t\tstruct esw1 esw1;\n\t\tstruct esw2 esw2;\n\t\tstruct esw3 esw3;\n\t\tstruct esw_eadm eadm;\n\t} esw;\n\t__u8 ecw[32];\n};\n\nstruct path_state {\n\t__u8 state1: 2;\n\t__u8 state2: 2;\n\t__u8 state3: 1;\n\t__u8 resvd: 3;\n};\n\nstruct extended_cssid {\n\tu8 version;\n\tu8 cssid;\n};\n\nstruct pgid {\n\tunion {\n\t\t__u8 fc;\n\t\tstruct path_state ps;\n\t} inf;\n\tunion {\n\t\t__u32 cpu_addr: 16;\n\t\tstruct extended_cssid ext_cssid;\n\t} pgid_high;\n\t__u32 cpu_id: 24;\n\t__u32 cpu_model: 16;\n\t__u32 tod_high;\n};\n\nstruct ccw_device_dma_area {\n\tstruct senseid senseid;\n\tstruct ccw1 iccws[2];\n\tstruct irb irb;\n\tstruct pgid pgid[8];\n};\n\nstruct ccw_request {\n\tstruct ccw1 *cp;\n\tlong unsigned int timeout;\n\tu16 maxretries;\n\tu8 lpm;\n\tint (*check)(struct ccw_device *, void *);\n\tenum io_status (*filter)(struct ccw_device *, void *, struct irb *, enum io_status);\n\tvoid (*callback)(struct ccw_device *, void *, int);\n\tvoid *data;\n\tunsigned int singlepath: 1;\n\tunsigned int cancel: 1;\n\tunsigned int done: 1;\n\tu16 mask;\n\tu16 retries;\n\tint drc;\n} __attribute__((packed));\n\nstruct qdio_irq;\n\nstruct gen_pool;\n\nstruct ccw_device_private {\n\tstruct ccw_device *cdev;\n\tstruct subchannel *sch;\n\tint state;\n\tatomic_t onoff;\n\tstruct ccw_dev_id dev_id;\n\tstruct ccw_request req;\n\tint iretry;\n\tu8 pgid_valid_mask;\n\tu8 pgid_todo_mask;\n\tu8 pgid_reset_mask;\n\tu8 path_noirq_mask;\n\tu8 path_notoper_mask;\n\tu8 path_gone_mask;\n\tu8 path_new_mask;\n\tu8 path_broken_mask;\n\tstruct {\n\t\tunsigned int fast: 1;\n\t\tunsigned int repall: 1;\n\t\tunsigned int pgroup: 1;\n\t\tunsigned int force: 1;\n\t\tunsigned int mpath: 1;\n\t} __attribute__((packed)) options;\n\tstruct {\n\t\tunsigned int esid: 1;\n\t\tunsigned int dosense: 1;\n\t\tunsigned int doverify: 1;\n\t\tunsigned int donotify: 1;\n\t\tunsigned int recog_done: 1;\n\t\tunsigned int fake_irb: 2;\n\t\tunsigned int pgroup: 1;\n\t\tunsigned int mpath: 1;\n\t\tunsigned int pgid_unknown: 1;\n\t\tunsigned int initialized: 1;\n\t} __attribute__((packed)) flags;\n\tlong unsigned int intparm;\n\tstruct qdio_irq *qdio_data;\n\tint async_kill_io_rc;\n\tstruct work_struct todo_work;\n\tenum cdev_todo todo;\n\twait_queue_head_t wait_q;\n\tstruct timer_list timer;\n\tvoid *cmb;\n\tstruct list_head cmb_list;\n\tu64 cmb_start_time;\n\tvoid *cmb_wait;\n\tstruct gen_pool *dma_pool;\n\tstruct ccw_device_dma_area *dma_area;\n\tenum interruption_class int_class;\n};\n\nstruct ccw_driver {\n\tstruct ccw_device_id *ids;\n\tint (*probe)(struct ccw_device *);\n\tvoid (*remove)(struct ccw_device *);\n\tint (*set_online)(struct ccw_device *);\n\tint (*set_offline)(struct ccw_device *);\n\tint (*notify)(struct ccw_device *, int);\n\tvoid (*path_event)(struct ccw_device *, int *);\n\tvoid (*shutdown)(struct ccw_device *);\n\tenum uc_todo (*uc_handler)(struct ccw_device *, struct irb *);\n\tstruct device_driver driver;\n\tenum interruption_class int_class;\n};\n\nstruct ccwdev_iter {\n\tint devno;\n\tint ssid;\n\tint in_range;\n};\n\nstruct ccwgroup_device {\n\tenum {\n\t\tCCWGROUP_OFFLINE = 0,\n\t\tCCWGROUP_ONLINE = 1,\n\t} state;\n\tatomic_t onoff;\n\tstruct mutex reg_mutex;\n\tunsigned int count;\n\tstruct device dev;\n\tstruct work_struct ungroup_work;\n\tstruct ccw_device *cdev[0];\n};\n\nstruct ccwgroup_driver {\n\tint (*setup)(struct ccwgroup_device *);\n\tvoid (*remove)(struct ccwgroup_device *);\n\tint (*set_online)(struct ccwgroup_device *);\n\tint (*set_offline)(struct ccwgroup_device *);\n\tvoid (*shutdown)(struct ccwgroup_device *);\n\tstruct device_driver driver;\n\tstruct ccw_driver *ccw_driver;\n};\n\nstruct cdrom_msf0 {\n\t__u8 minute;\n\t__u8 second;\n\t__u8 frame;\n};\n\nunion cdrom_addr {\n\tstruct cdrom_msf0 msf;\n\tint lba;\n};\n\nstruct cdrom_device_ops;\n\nstruct cdrom_device_info {\n\tconst struct cdrom_device_ops *ops;\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tvoid *handle;\n\tint mask;\n\tint speed;\n\tint capacity;\n\tunsigned int options: 30;\n\tunsigned int mc_flags: 2;\n\tunsigned int vfs_events;\n\tunsigned int ioctl_events;\n\tint use_count;\n\tchar name[20];\n\t__u8 sanyo_slot: 2;\n\t__u8 keeplocked: 1;\n\t__u8 reserved: 5;\n\tint cdda_method;\n\t__u8 last_sense;\n\t__u8 media_written;\n\tshort unsigned int mmc3_profile;\n\tint mrw_mode_page;\n\tbool opened_for_data;\n\t__s64 last_media_change_ms;\n};\n\nstruct cdrom_multisession;\n\nstruct cdrom_mcn;\n\nstruct packet_command;\n\nstruct cdrom_device_ops {\n\tint (*open)(struct cdrom_device_info *, int);\n\tvoid (*release)(struct cdrom_device_info *);\n\tint (*drive_status)(struct cdrom_device_info *, int);\n\tunsigned int (*check_events)(struct cdrom_device_info *, unsigned int, int);\n\tint (*tray_move)(struct cdrom_device_info *, int);\n\tint (*lock_door)(struct cdrom_device_info *, int);\n\tint (*select_speed)(struct cdrom_device_info *, long unsigned int);\n\tint (*get_last_session)(struct cdrom_device_info *, struct cdrom_multisession *);\n\tint (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);\n\tint (*reset)(struct cdrom_device_info *);\n\tint (*audio_ioctl)(struct cdrom_device_info *, unsigned int, void *);\n\tint (*generic_packet)(struct cdrom_device_info *, struct packet_command *);\n\tint (*read_cdda_bpc)(struct cdrom_device_info *, void *, u32, u32, u8 *);\n\tconst int capability;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct cdrom_mcn {\n\t__u8 medium_catalog_number[14];\n};\n\nstruct cdrom_multisession {\n\tunion cdrom_addr addr;\n\t__u8 xa_flag;\n\t__u8 addr_format;\n};\n\nstruct cdrom_tocentry {\n\t__u8 cdte_track;\n\t__u8 cdte_adr: 4;\n\t__u8 cdte_ctrl: 4;\n\t__u8 cdte_format;\n\tunion cdrom_addr cdte_addr;\n\t__u8 cdte_datamode;\n};\n\nstruct clock_event_device;\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct cf_ctrset_entry {\n\tunsigned int def: 16;\n\tunsigned int set: 16;\n\tunsigned int ctr: 16;\n\tunsigned int res1: 16;\n};\n\nstruct cf_trailer_entry {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int clock_base: 1;\n\t\t\tunsigned int speed: 1;\n\t\t\tunsigned int mtda: 1;\n\t\t\tunsigned int caca: 1;\n\t\t\tunsigned int lcda: 1;\n\t\t};\n\t\tlong unsigned int flags;\n\t};\n\tunsigned int cfvn: 16;\n\tunsigned int csvn: 16;\n\tunsigned int cpu_speed: 32;\n\tlong unsigned int timestamp;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int progusage1;\n\t\t\tlong unsigned int progusage2;\n\t\t\tlong unsigned int progusage3;\n\t\t\tlong unsigned int tod_base;\n\t\t};\n\t\tlong unsigned int progusage[4];\n\t};\n\tunsigned int mach_type: 16;\n\tunsigned int res1: 16;\n\tunsigned int res2: 32;\n};\n\nstruct cfs_bandwidth {\n\traw_spinlock_t lock;\n\tktime_t period;\n\tu64 quota;\n\tu64 runtime;\n\tu64 burst;\n\tu64 runtime_snap;\n\ts64 hierarchical_quota;\n\tu8 idle;\n\tu8 period_active;\n\tu8 slack_started;\n\tstruct hrtimer period_timer;\n\tstruct hrtimer slack_timer;\n\tstruct list_head throttled_cfs_rq;\n\tint nr_periods;\n\tint nr_throttled;\n\tint nr_burst;\n\tu64 throttled_time;\n\tu64 burst_time;\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sched_entity;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tunsigned int forceidle_seq;\n\tu64 zero_vruntime_fi;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tint runtime_enabled;\n\ts64 runtime_remaining;\n\tu64 throttled_pelt_idle;\n\tu64 throttled_clock;\n\tu64 throttled_clock_pelt;\n\tu64 throttled_clock_pelt_time;\n\tu64 throttled_clock_self;\n\tu64 throttled_clock_self_time;\n\tbool throttled: 1;\n\tbool pelt_clock_throttled: 1;\n\tint throttle_count;\n\tstruct list_head throttled_list;\n\tstruct list_head throttled_csd_list;\n\tstruct list_head throttled_limbo_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cfs_schedulable_data {\n\tstruct task_group *tg;\n\tu64 period;\n\tu64 quota;\n};\n\nstruct cfset_call_on_cpu_parm {\n\tunsigned int sets;\n\tatomic_t cpus_ack;\n};\n\nstruct cfset_request {\n\tlong unsigned int ctrset;\n\tcpumask_t mask;\n\tstruct list_head node;\n};\n\nstruct cfset_session {\n\tstruct list_head head;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 forceidle_sum;\n\tu64 ntime;\n};\n\nstruct prev_cputime {};\n\nstruct cgroup_bpf {\n\tstruct bpf_prog_array *effective[38];\n\tstruct hlist_head progs[38];\n\tu8 flags[38];\n\tu64 revisions[38];\n\tstruct list_head storages;\n\tstruct bpf_prog_array *inactive;\n\tstruct percpu_ref refcnt;\n\tstruct work_struct release_work;\n};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[0];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[14];\n\tint nr_dying_subsys[14];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[14];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n\tlong: 64;\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct cgroup_cls_state {\n\tstruct cgroup_subsys_state css;\n\tu32 classid;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_lsm_atype {\n\tu32 attach_btf_id;\n\tint refcnt;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct chacha20poly1305_testvec {\n\tconst u8 *input;\n\tconst u8 *output;\n\tconst u8 *assoc;\n\tconst u8 *nonce;\n\tconst u8 *key;\n\tsize_t ilen;\n\tsize_t alen;\n\tsize_t nlen;\n\tbool failure;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct channel_path_desc_fmt0 {\n\tu8 flags;\n\tu8 lsn;\n\tu8 desc;\n\tu8 chpid;\n\tu8 swla;\n\tu8 zeroes;\n\tu8 chla;\n\tu8 chpp;\n};\n\nstruct channel_path_desc_fmt1 {\n\tu8 flags;\n\tu8 lsn;\n\tu8 desc;\n\tu8 chpid;\n\tshort: 16;\n\tu8 esc;\n\tu8 chpp;\n\tu32 unused[2];\n\tu16 chid;\n\tint: 0;\n\tu16 mdc;\n\tshort: 13;\n\tu8 r: 1;\n\tu8 s: 1;\n\tu8 f: 1;\n\tu32 zeros[2];\n};\n\nstruct channel_path_desc_fmt3 {\n\tstruct channel_path_desc_fmt1 fmt1_desc;\n\tu8 util_str[64];\n};\n\nstruct cmg_chars {\n\tu32 values[5];\n};\n\nstruct cmg_cmcb {\n\tu32 not_valid: 1;\n\tu32 shared: 1;\n\tu32 extended: 1;\n\tshort: 13;\n\tchar: 8;\n\tu32 chpid: 8;\n\tu32 cmcv: 5;\n\tchar: 3;\n\tchar: 4;\n\tu32 cmgp: 4;\n\tu32 cmgq: 8;\n\tu32 cmg: 8;\n\tshort: 16;\n\tu32 cmgs: 16;\n\tu32 data[5];\n};\n\nstruct channel_path {\n\tstruct device dev;\n\tstruct chp_id chpid;\n\tstruct mutex lock;\n\tint state;\n\tstruct channel_path_desc_fmt0 desc;\n\tstruct channel_path_desc_fmt1 desc_fmt1;\n\tstruct channel_path_desc_fmt3 desc_fmt3;\n\tint cmg;\n\tint shared;\n\tint extended;\n\tlong unsigned int speed;\n\tstruct cmg_chars cmg_chars;\n\tstruct cmg_cmcb cmcb;\n};\n\nstruct channel_subsystem {\n\tu8 cssid;\n\tu8 iid;\n\tbool id_valid;\n\tstruct channel_path *chps[256];\n\tstruct device device;\n\tstruct pgid global_pgid;\n\tstruct mutex mutex;\n\tint cm_enabled;\n\tvoid *cub[2];\n\tvoid *ecub[4];\n\tstruct subchannel *pseudo_subchannel;\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct check_attention_work_data {\n\tstruct work_struct worker;\n\tstruct dasd_device *device;\n\t__u8 lpum;\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct check_loop_arg {\n\tstruct qdisc_walker w;\n\tstruct Qdisc *p;\n\tint depth;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct iolatency_grp;\n\nstruct child_latency_info {\n\tspinlock_t lock;\n\tu64 last_scale_event;\n\tu64 scale_lat;\n\tu64 nr_samples;\n\tstruct iolatency_grp *scale_grp;\n\tatomic_t scale_cookie;\n};\n\nstruct chp_cfg_sccb {\n\tstruct sccb_header header;\n\tu8 ccm;\n\tu8 reserved[6];\n\tu8 cssid;\n};\n\nstruct chp_config_data {\n\tu8 map[32];\n\tu8 op;\n\tu8 pc;\n};\n\nstruct chp_info_sccb {\n\tstruct sccb_header header;\n\tu8 recognized[32];\n\tu8 standby[32];\n\tu8 configured[32];\n\tu8 ccm;\n\tu8 reserved[6];\n\tu8 cssid;\n};\n\nstruct chp_link {\n\tstruct chp_id chpid;\n\tu32 fla_mask;\n\tu16 fla;\n};\n\nstruct chsc_async_header {\n\t__u16 length;\n\t__u16 code;\n\t__u32 cmd_dependend;\n\t__u32 key: 4;\n\tstruct subchannel_id sid;\n};\n\nstruct chsc_async_area {\n\tstruct chsc_async_header header;\n\t__u8 data[4080];\n};\n\nstruct chsc_response_struct {\n\t__u16 length;\n\t__u16 code;\n\t__u32 parms;\n\t__u8 data[4088];\n};\n\nstruct chsc_chp_cd {\n\tstruct chp_id chpid;\n\tint m;\n\tint fmt;\n\tstruct chsc_response_struct cpcb;\n};\n\nstruct chsc_comp_list {\n\tstruct {\n\t\tenum {\n\t\t\tCCL_CU_ON_CHP = 1,\n\t\t\tCCL_CHP_TYPE_CAP = 2,\n\t\t\tCCL_CSS_IMG = 4,\n\t\t\tCCL_CSS_IMG_CONF_CHAR = 5,\n\t\t\tCCL_IOP_CHP = 6,\n\t\t} ctype;\n\t\tint fmt;\n\t\tstruct ccl_parm_chpid chpid;\n\t\tstruct ccl_parm_cssids cssids;\n\t} req;\n\tstruct chsc_response_struct sccl;\n};\n\nstruct conf_id {\n\tint m;\n\t__u8 cssid;\n\t__u8 ssid;\n};\n\nstruct chsc_conf_info {\n\tstruct conf_id id;\n\tint fmt;\n\tstruct chsc_response_struct scid;\n};\n\nstruct chsc_cpd_info {\n\tstruct chp_id chpid;\n\tint m;\n\tint fmt;\n\tint rfmt;\n\tint c;\n\tstruct chsc_response_struct chpdb;\n};\n\nstruct chsc_cu_cd {\n\t__u16 cun;\n\t__u8 cssid;\n\tint m;\n\tint fmt;\n\tstruct chsc_response_struct cucb;\n};\n\nstruct chsc_dcal {\n\tstruct {\n\t\tenum {\n\t\t\tDCAL_CSS_IID_PN = 4,\n\t\t} atype;\n\t\t__u32 list_parm[2];\n\t\tint fmt;\n\t} req;\n\tstruct chsc_response_struct sdcal;\n};\n\nstruct chsc_header {\n\t__u16 length;\n\t__u16 code;\n};\n\nstruct chsc_pnso_resume_token {\n\tu64 t1;\n\tu64 t2;\n};\n\nstruct chsc_pnso_naihdr {\n\tstruct chsc_pnso_resume_token resume_token;\n\tint: 32;\n\tu32 instance;\n\tint: 24;\n\tu8 naids;\n\tu32 reserved[3];\n};\n\nstruct chsc_pnso_naid_l2 {\n\tu64 nit;\n\tstruct {\n\t\tu8 mac[6];\n\t\tu16 lnid;\n\t} addr_lnid;\n};\n\nstruct chsc_pnso_area {\n\tstruct chsc_header request;\n\tchar: 2;\n\tu8 m: 1;\n\tchar: 5;\n\tchar: 2;\n\tu8 ssid: 2;\n\tu8 fmt: 4;\n\tu16 sch;\n\tchar: 8;\n\tu8 cssid;\n\tint: 0;\n\tu8 oc;\n\tstruct chsc_pnso_resume_token resume_token;\n\tu32 n: 1;\n\tu32 reserved[3];\n\tstruct chsc_header response;\n\tstruct chsc_pnso_naihdr naihdr;\n\tstruct chsc_pnso_naid_l2 entries[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct chsc_request;\n\nstruct chsc_private {\n\tstruct chsc_request *request;\n};\n\nstruct chsc_request {\n\tstruct completion completion;\n\tstruct irb irb;\n};\n\nstruct chsc_sch_cud {\n\tstruct subchannel_id schid;\n\tint fmt;\n\tstruct chsc_response_struct scub;\n};\n\nstruct sale {\n\tu64 sa;\n\tu32 p: 4;\n\tu32 op_state: 4;\n\tu32 data_state: 4;\n\tu32 rank: 4;\n\tu32 r: 1;\n\tchar: 7;\n\tu32 rid: 8;\n};\n\nstruct chsc_scm_info {\n\tstruct chsc_header request;\n\tu64 reqtok;\n\tu32 reserved1[4];\n\tstruct chsc_header response;\n\tlong: 0;\n\tint: 24;\n\tu8 rq;\n\tu32 mbc;\n\tu64 msa;\n\tu16 is;\n\tu16 mmc;\n\tu32 mci;\n\tu64 nr_scm_ini;\n\tu64 nr_scm_unini;\n\tu32 reserved2[10];\n\tu64 restok;\n\tstruct sale scmal[248];\n};\n\nstruct chsc_scpd {\n\tstruct chsc_header request;\n\tchar: 2;\n\tu32 m: 1;\n\tu32 c: 1;\n\tu32 fmt: 4;\n\tu32 cssid: 8;\n\tchar: 4;\n\tu32 rfmt: 4;\n\tu32 first_chpid: 8;\n\tint: 24;\n\tu32 last_chpid: 8;\n\tu32 zeroes1;\n\tstruct chsc_header response;\n\tlong: 0;\n\tu8 data[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct chsc_scssc_area {\n\tstruct chsc_header request;\n\tu16 operation_code;\n\tlong: 64;\n\tdma64_t summary_indicator_addr;\n\tdma64_t subchannel_indicator_addr;\n\tu32 ks: 4;\n\tu32 kc: 4;\n\tshort: 8;\n\tshort: 13;\n\tu32 isc: 3;\n\tu32 word_with_d_bit;\n\tint: 32;\n\tstruct subchannel_id schid;\n\tu32 reserved[1004];\n\tstruct chsc_header response;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct chse_cudb {\n\tu16 flags: 8;\n\tu16 chp_valid: 8;\n\tu16 cu;\n\tu32 esm_valid: 8;\n\tlong: 0;\n\tu8 chpid[8];\n\tlong: 64;\n\tu8 esm[8];\n\tu32 efla[8];\n};\n\nstruct chsc_scud {\n\tstruct chsc_header request;\n\tchar: 4;\n\tu16 fmt: 4;\n\tu16 cssid: 8;\n\tu16 first_cu;\n\tshort: 16;\n\tu16 last_cu;\n\tlong: 0;\n\tstruct chsc_header response;\n\tchar: 4;\n\tu16 fmt_resp: 4;\n\tstruct chse_cudb cudb[0];\n};\n\nstruct chsc_sda_area {\n\tstruct chsc_header request;\n\tchar: 4;\n\tu8 format: 4;\n\tu16 operation_code;\n\tlong: 64;\n\tu32 operation_data_area[252];\n\tstruct chsc_header response;\n\tchar: 4;\n\tu32 format2: 4;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct chsc_sei_nt0_area {\n\tu8 flags;\n\tu8 vf;\n\tu8 rs;\n\tu8 cc;\n\tu16 fla;\n\tu16 rsid;\n\tu32 reserved1;\n\tu32 reserved2;\n\tu8 ccdf[4056];\n};\n\nstruct chsc_sei_nt2_area {\n\tu8 flags;\n\tu8 reserved1;\n\tu8 reserved2;\n\tu8 cc;\n\tu32 reserved3[13];\n\tu8 ccdf[4016];\n};\n\nstruct chsc_sei {\n\tstruct chsc_header request;\n\tu32 reserved1;\n\tu64 ntsm;\n\tstruct chsc_header response;\n\tint: 24;\n\tu8 nt;\n\tunion {\n\t\tstruct chsc_sei_nt0_area nt0_area;\n\t\tstruct chsc_sei_nt2_area nt2_area;\n\t\tu8 nt_area[4072];\n\t} u;\n};\n\nstruct chsc_ssd_area {\n\tstruct chsc_header request;\n\tshort: 10;\n\tu16 ssid: 2;\n\tu16 f_sch;\n\tshort: 16;\n\tu16 l_sch;\n\tlong: 0;\n\tstruct chsc_header response;\n\tlong: 0;\n\tu8 sch_valid: 1;\n\tu8 dev_valid: 1;\n\tu8 st: 3;\n\tu8 zeroes: 3;\n\tu8 unit_addr;\n\tu16 devno;\n\tu8 path_mask;\n\tu8 fla_valid_mask;\n\tu16 sch;\n\tu8 chpid[8];\n\tu16 fla[8];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct chsc_ssd_info {\n\tu8 path_mask;\n\tu8 fla_valid_mask;\n\tstruct chp_id chpid[8];\n\tu16 fla[8];\n};\n\nstruct qdio_ssqd_desc {\n\tu8 flags;\n\tu16 sch;\n\tu8 qfmt;\n\tu8 parm;\n\tu8 qdioac1;\n\tu8 sch_class;\n\tu8 pcnt;\n\tu8 icnt;\n\tchar: 8;\n\tu8 ocnt;\n\tchar: 8;\n\tu8 mbccnt;\n\tu16 qdioac2;\n\tu64 sch_token;\n\tu8 mro;\n\tu8 mri;\n\tu16 qdioac3;\n\tint: 24;\n\tu8 mmwc;\n};\n\nstruct chsc_ssqd_area {\n\tstruct chsc_header request;\n\tshort: 10;\n\tu8 ssid: 2;\n\tu8 fmt: 4;\n\tu16 first_sch;\n\tshort: 16;\n\tu16 last_sch;\n\tlong: 0;\n\tstruct chsc_header response;\n\tstruct qdio_ssqd_desc qdio_ssqd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct chsc_sync_area {\n\tstruct chsc_header header;\n\t__u8 data[4092];\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct test_sglist {\n\tchar *bufs[8];\n\tstruct scatterlist sgl[8];\n\tstruct scatterlist sgl_saved[8];\n\tstruct scatterlist *sgl_ptr;\n\tunsigned int nents;\n};\n\nstruct cipher_test_sglists {\n\tstruct test_sglist src;\n\tstruct test_sglist dst;\n};\n\nstruct cipher_testvec {\n\tconst char *key;\n\tconst char *iv;\n\tconst char *iv_out;\n\tconst char *ptext;\n\tconst char *ctext;\n\tunsigned char wk;\n\tshort unsigned int klen;\n\tunsigned int len;\n\tbool fips_skip;\n\tint setkey_error;\n\tint crypt_error;\n};\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct hashtab_node;\n\nstruct hashtab {\n\tstruct hashtab_node **htable;\n\tu32 size;\n\tu32 nel;\n};\n\nstruct symtab {\n\tstruct hashtab table;\n\tu32 nprim;\n};\n\nstruct common_datum;\n\nstruct constraint_node;\n\nstruct class_datum {\n\tu32 value;\n\tchar *comkey;\n\tstruct common_datum *comdatum;\n\tstruct symtab permissions;\n\tstruct constraint_node *constraints;\n\tstruct constraint_node *validatetrans;\n\tchar default_user;\n\tchar default_role;\n\tchar default_type;\n\tchar default_range;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct clock_sync_data {\n\tatomic_t cpus;\n\tint in_sync;\n\tlong int clock_delta;\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct module *owner;\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct dm_table;\n\nstruct dm_io;\n\nstruct clone_info {\n\tstruct dm_table *map;\n\tstruct bio *bio;\n\tstruct dm_io *io;\n\tsector_t sector;\n\tunsigned int sector_count;\n\tbool is_abnormal_io: 1;\n\tbool submit_as_polled: 1;\n};\n\nstruct clone_root {\n\tstruct btrfs_root *root;\n\tu64 ino;\n\tu64 offset;\n\tu64 num_bytes;\n\tbool found_ref;\n};\n\ntypedef void closure_fn(struct work_struct *);\n\nstruct closure_syncer;\n\nstruct closure {\n\tunion {\n\t\tstruct {\n\t\t\tstruct workqueue_struct *wq;\n\t\t\tstruct closure_syncer *s;\n\t\t\tstruct llist_node list;\n\t\t\tclosure_fn *fn;\n\t\t};\n\t\tstruct work_struct work;\n\t};\n\tstruct closure *parent;\n\tatomic_t remaining;\n\tbool closure_get_happened;\n};\n\nstruct closure_syncer {\n\tstruct task_struct *task;\n\tint done;\n};\n\nstruct closure_waitlist {\n\tstruct llist_head list;\n};\n\nstruct clp_fh_list_entry {\n\tu16 device_id;\n\tu16 vendor_id;\n\tu32 config_state: 1;\n\tu32 fid;\n\tu32 fh;\n};\n\nstruct clp_req {\n\tunsigned int c: 1;\n\tunsigned int r: 1;\n\tunsigned int lps: 6;\n\tunsigned int cmd: 8;\n\tunsigned int reserved;\n\t__u64 data_p;\n};\n\nstruct clp_req_hdr {\n\tu16 len;\n\tu16 cmd;\n\tu32 fmt: 4;\n\tu32 reserved1: 28;\n\tu64 reserved2;\n};\n\nstruct clp_req_list_pci {\n\tstruct clp_req_hdr hdr;\n\tu64 resume_token;\n\tu64 reserved2;\n};\n\nstruct clp_req_query_pci {\n\tstruct clp_req_hdr hdr;\n\tu32 fh;\n\tu32 reserved2;\n\tu64 reserved3;\n};\n\nstruct clp_req_query_pci_grp {\n\tstruct clp_req_hdr hdr;\n\tu32 reserved2: 24;\n\tu32 pfgid: 8;\n\tu32 reserved3;\n\tu64 reserved4;\n};\n\nstruct clp_rsp_hdr {\n\tu16 len;\n\tu16 rsp;\n\tu32 fmt: 4;\n\tu32 reserved1: 28;\n\tu64 reserved2;\n};\n\nstruct clp_rsp_list_pci {\n\tstruct clp_rsp_hdr hdr;\n\tu64 resume_token;\n\tu32 reserved2;\n\tu16 max_fn;\n\tchar: 7;\n\tu8 uid_checking: 1;\n\tu8 entry_size;\n\tstruct clp_fh_list_entry fh_list[252];\n};\n\nstruct clp_req_rsp_list_pci {\n\tstruct clp_req_list_pci request;\n\tstruct clp_rsp_list_pci response;\n};\n\nstruct mio_info {\n\tu32 valid: 6;\n\tstruct {\n\t\tu64 wb;\n\t\tu64 wt;\n\t} addr[6];\n\tu32 reserved[6];\n};\n\nstruct clp_rsp_query_pci {\n\tstruct clp_rsp_hdr hdr;\n\tu16 vfn;\n\tchar: 2;\n\tu16 tid_avail: 1;\n\tu16 rid_avail: 1;\n\tu16 is_physfn: 1;\n\tu16 reserved1: 1;\n\tu16 mio_addr_avail: 1;\n\tu16 util_str_avail: 1;\n\tu16 pfgid: 8;\n\tu32 fid;\n\tu8 bar_size[6];\n\tu16 pchid;\n\t__le32 bar[6];\n\tu8 pfip[4];\n\tu8 fidparm;\n\tu8 reserved3: 4;\n\tu8 port: 4;\n\tu8 fmb_len;\n\tu8 pft;\n\tu64 sdma;\n\tu64 edma;\n\tu16 rid;\n\tu32 reserved0;\n\tu16 tid;\n\tu32 reserved[9];\n\tu32 uid;\n\tu8 util_str[64];\n\tu32 reserved2[16];\n\tstruct mio_info mio;\n} __attribute__((packed));\n\nstruct clp_req_rsp_query_pci {\n\tstruct clp_req_query_pci request;\n\tstruct clp_rsp_query_pci response;\n};\n\nstruct clp_rsp_query_pci_grp {\n\tstruct clp_rsp_hdr hdr;\n\tchar: 4;\n\tu16 noi: 12;\n\tu8 version;\n\tchar: 2;\n\tu8 rtr: 1;\n\tchar: 3;\n\tu8 frame: 1;\n\tu8 refresh: 1;\n\tchar: 3;\n\tu16 maxstbl: 13;\n\tu16 mui;\n\tu8 dtsm;\n\tu8 reserved3;\n\tu16 maxfaal;\n\tchar: 4;\n\tu16 dnoi: 12;\n\tu16 maxcpu;\n\tu64 dasm;\n\tu64 msia;\n\tu64 reserved4;\n\tu64 reserved5;\n};\n\nstruct clp_req_rsp_query_pci_grp {\n\tstruct clp_req_query_pci_grp request;\n\tstruct clp_rsp_query_pci_grp response;\n};\n\nstruct clp_req_set_pci {\n\tstruct clp_req_hdr hdr;\n\tu32 fh;\n\tu16 reserved2;\n\tu8 oc;\n\tu8 ndas;\n\tu32 reserved3;\n\tu32 gisa;\n};\n\nstruct clp_rsp_set_pci {\n\tstruct clp_rsp_hdr hdr;\n\tu32 fh;\n\tu32 reserved1;\n\tu64 reserved2;\n\tstruct mio_info mio;\n};\n\nstruct clp_req_rsp_set_pci {\n\tstruct clp_req_set_pci request;\n\tstruct clp_rsp_set_pci response;\n};\n\nstruct clp_req_slpc {\n\tstruct clp_req_hdr hdr;\n};\n\nstruct clp_rsp_slpc {\n\tstruct clp_rsp_hdr hdr;\n\tu32 reserved2[4];\n\tu32 lpif[8];\n\tu32 reserved3[8];\n\tu32 lpic[8];\n};\n\nstruct clp_req_rsp_slpc {\n\tstruct clp_req_slpc request;\n\tstruct clp_rsp_slpc response;\n};\n\nstruct clp_rsp_slpc_pci {\n\tstruct clp_rsp_hdr hdr;\n\tu32 reserved2[4];\n\tu32 lpif[8];\n\tu32 reserved3[4];\n\tu32 vwb: 1;\n\tchar: 1;\n\tu32 mio_wb: 6;\n\tu32 reserved5[3];\n\tu32 lpic[8];\n};\n\nstruct clp_req_rsp_slpc_pci {\n\tstruct clp_req_slpc request;\n\tstruct clp_rsp_slpc_pci response;\n};\n\nstruct tc_action;\n\nstruct tcf_exts_miss_cookie_node;\n\nstruct tcf_exts {\n\t__u32 type;\n\tint nr_actions;\n\tstruct tc_action **actions;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct tcf_exts_miss_cookie_node *miss_cookie_node;\n\tint action;\n\tint police;\n};\n\nstruct tcf_ematch_tree_hdr {\n\t__u16 nmatches;\n\t__u16 progid;\n};\n\nstruct tcf_ematch;\n\nstruct tcf_ematch_tree {\n\tstruct tcf_ematch_tree_hdr hdr;\n\tstruct tcf_ematch *matches;\n};\n\nstruct tcf_proto;\n\nstruct cls_cgroup_head {\n\tu32 handle;\n\tstruct tcf_exts exts;\n\tstruct tcf_ematch_tree ematches;\n\tstruct tcf_proto *tp;\n\tstruct rcu_work rwork;\n};\n\nstruct cma_memrange {\n\tlong unsigned int base_pfn;\n\tlong unsigned int count;\n\tunion {\n\t\tlong unsigned int early_pfn;\n\t\tlong unsigned int *bitmap;\n\t};\n};\n\nstruct cma_kobject;\n\nstruct cma {\n\tlong unsigned int count;\n\tlong unsigned int available_count;\n\tunsigned int order_per_bit;\n\tspinlock_t lock;\n\tstruct mutex alloc_mutex;\n\tchar name[64];\n\tint nranges;\n\tstruct cma_memrange ranges[8];\n\tatomic64_t nr_pages_succeeded;\n\tatomic64_t nr_pages_failed;\n\tatomic64_t nr_pages_released;\n\tstruct cma_kobject *cma_kobj;\n\tlong unsigned int flags;\n\tint nid;\n};\n\nstruct cma_init_memrange {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tstruct list_head list;\n};\n\nstruct cma_kobject {\n\tstruct kobject kobj;\n\tstruct cma *cma;\n};\n\nstruct cmb {\n\tu16 ssch_rsch_count;\n\tu16 sample_count;\n\tu32 device_connect_time;\n\tu32 function_pending_time;\n\tu32 device_disconnect_time;\n\tu32 control_unit_queuing_time;\n\tu32 device_active_only_time;\n\tu32 reserved[2];\n};\n\nstruct cmb_area {\n\tstruct cmb *mem;\n\tstruct list_head list;\n\tint num_channels;\n\tspinlock_t lock;\n};\n\nstruct cmb_data {\n\tvoid *hw_block;\n\tvoid *last_block;\n\tint size;\n\tlong long unsigned int last_update;\n};\n\nstruct cmbdata;\n\nstruct cmb_operations {\n\tint (*alloc)(struct ccw_device *);\n\tvoid (*free)(struct ccw_device *);\n\tint (*set)(struct ccw_device *, u32);\n\tu64 (*read)(struct ccw_device *, int);\n\tint (*readall)(struct ccw_device *, struct cmbdata *);\n\tvoid (*reset)(struct ccw_device *);\n\tstruct attribute_group *attr_group;\n};\n\nstruct cmbdata {\n\t__u64 size;\n\t__u64 elapsed_time;\n\t__u64 ssch_rsch_count;\n\t__u64 sample_count;\n\t__u64 device_connect_time;\n\t__u64 function_pending_time;\n\t__u64 device_disconnect_time;\n\t__u64 control_unit_queuing_time;\n\t__u64 device_active_only_time;\n\t__u64 device_busy_time;\n\t__u64 initial_command_response_time;\n};\n\nstruct cmbe {\n\tu32 ssch_rsch_count;\n\tu32 sample_count;\n\tu32 device_connect_time;\n\tu32 function_pending_time;\n\tu32 device_disconnect_time;\n\tu32 control_unit_queuing_time;\n\tu32 device_active_only_time;\n\tu32 device_busy_time;\n\tu32 initial_command_response_time;\n\tu32 reserved[7];\n};\n\nstruct cmd_orb {\n\tu32 intparm;\n\tu32 key: 4;\n\tu32 spnd: 1;\n\tu32 res1: 1;\n\tu32 mod: 1;\n\tu32 sync: 1;\n\tu32 fmt: 1;\n\tu32 pfch: 1;\n\tu32 isic: 1;\n\tu32 alcc: 1;\n\tu32 ssic: 1;\n\tu32 res2: 1;\n\tu32 c64: 1;\n\tu32 i2k: 1;\n\tu32 lpm: 8;\n\tu32 ils: 1;\n\tu32 zero: 6;\n\tu32 orbx: 1;\n\tdma32_t cpa;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct cn_callback_id {\n\tunsigned char name[32];\n\tstruct cb_id id;\n};\n\nstruct cn_queue_dev;\n\nstruct cn_msg;\n\nstruct netlink_skb_parms;\n\nstruct cn_callback_entry {\n\tstruct list_head callback_entry;\n\trefcount_t refcnt;\n\tstruct cn_queue_dev *pdev;\n\tstruct cn_callback_id id;\n\tvoid (*callback)(struct cn_msg *, struct netlink_skb_parms *);\n\tu32 seq;\n\tu32 group;\n};\n\nstruct cn_dev {\n\tstruct cb_id id;\n\tu32 seq;\n\tu32 groups;\n\tstruct sock *nls;\n\tstruct cn_queue_dev *cbdev;\n};\n\nstruct cn_msg {\n\tstruct cb_id id;\n\t__u32 seq;\n\t__u32 ack;\n\t__u16 len;\n\t__u16 flags;\n\t__u8 data[0];\n};\n\nstruct cn_queue_dev {\n\tatomic_t refcnt;\n\tunsigned char name[32];\n\tstruct list_head queue_list;\n\tspinlock_t queue_lock;\n\tstruct sock *nls;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct collapse_control {\n\tbool is_khugepaged;\n\tu32 node_load[2];\n\tnodemask_t alloc_nmask;\n};\n\nstruct comm_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tchar comm[16];\n};\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n};\n\nstruct lsm_network_audit;\n\nstruct lsm_ioctlop_audit;\n\nstruct lsm_ibpkey_audit;\n\nstruct lsm_ibendport_audit;\n\nstruct selinux_audit_data;\n\nstruct common_audit_data {\n\tchar type;\n\tunion {\n\t\tstruct path path;\n\t\tstruct dentry *dentry;\n\t\tstruct inode *inode;\n\t\tstruct lsm_network_audit *net;\n\t\tint cap;\n\t\tint ipc_id;\n\t\tstruct task_struct *tsk;\n\t\tstruct {\n\t\t\tkey_serial_t key;\n\t\t\tchar *key_desc;\n\t\t} key_struct;\n\t\tchar *kmod_name;\n\t\tstruct lsm_ioctlop_audit *op;\n\t\tstruct file *file;\n\t\tstruct lsm_ibpkey_audit *ibpkey;\n\t\tstruct lsm_ibendport_audit *ibendport;\n\t\tint reason;\n\t\tconst char *anonclass;\n\t\tu16 nlmsg_type;\n\t} u;\n\tunion {\n\t\tstruct selinux_audit_data *selinux_audit_data;\n\t};\n};\n\nstruct common_datum {\n\tu32 value;\n\tstruct symtab permissions;\n};\n\nstruct comp_testvec {\n\tint inlen;\n\tint outlen;\n\tchar input[512];\n\tchar output[512];\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[11];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t} __attribute__((packed));\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n} __attribute__((packed));\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n} __attribute__((packed));\n\nstruct compat_if_dqblk {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 dqb_bsoftlimit;\n\tcompat_u64 dqb_curspace;\n\tcompat_u64 dqb_ihardlimit;\n\tcompat_u64 dqb_isoftlimit;\n\tcompat_u64 dqb_curinodes;\n\tcompat_u64 dqb_btime;\n\tcompat_u64 dqb_itime;\n\tcompat_uint_t dqb_valid;\n};\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_sg_io_hdr {\n\tcompat_int_t interface_id;\n\tcompat_int_t dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tcompat_uint_t dxfer_len;\n\tcompat_uint_t dxferp;\n\tcompat_uptr_t cmdp;\n\tcompat_uptr_t sbp;\n\tcompat_uint_t timeout;\n\tcompat_uint_t flags;\n\tcompat_int_t pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tcompat_int_t resid;\n\tcompat_uint_t duration;\n\tcompat_uint_t info;\n};\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct compressed_bio {\n\tu64 start;\n\tunsigned int len;\n\tunsigned int compressed_len;\n\tu8 compress_type;\n\tbool writeback;\n\tstruct btrfs_bio *orig_bbio;\n\tstruct btrfs_bio bbio;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct cond_av_list {\n\tstruct avtab_node **nodes;\n\tu32 len;\n};\n\nstruct cond_bool_datum {\n\tu32 value;\n\tint state;\n};\n\nstruct cond_expr_node;\n\nstruct cond_expr {\n\tstruct cond_expr_node *nodes;\n\tu32 len;\n};\n\nstruct cond_expr_node {\n\tu32 expr_type;\n\tu32 boolean;\n};\n\nstruct policydb;\n\nstruct cond_insertf_data {\n\tstruct policydb *p;\n\tstruct avtab_node **dst;\n\tstruct cond_av_list *other;\n};\n\nstruct cond_node {\n\tint cur_state;\n\tstruct cond_expr expr;\n\tstruct cond_av_list true_list;\n\tstruct cond_av_list false_list;\n};\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\nstruct cond_snapshot {\n\tvoid *cond_data;\n\tcond_update_fn_t update;\n};\n\nstruct conf_mgm_data {\n\tu8 reserved;\n\tu8 ev_qualifier;\n};\n\nstruct config_group;\n\nstruct config_item_type;\n\nstruct config_item {\n\tchar *ci_name;\n\tchar ci_namebuf[20];\n\tstruct kref ci_kref;\n\tstruct list_head ci_entry;\n\tstruct config_item *ci_parent;\n\tstruct config_group *ci_group;\n\tconst struct config_item_type *ci_type;\n\tstruct dentry *ci_dentry;\n};\n\nstruct configfs_subsystem;\n\nstruct config_group {\n\tstruct config_item cg_item;\n\tstruct list_head cg_children;\n\tstruct configfs_subsystem *cg_subsys;\n\tstruct list_head default_groups;\n\tstruct list_head group_entry;\n};\n\nstruct configfs_item_operations;\n\nstruct configfs_group_operations;\n\nstruct configfs_attribute;\n\nstruct configfs_bin_attribute;\n\nstruct config_item_type {\n\tstruct module *ct_owner;\n\tconst struct configfs_item_operations *ct_item_ops;\n\tconst struct configfs_group_operations *ct_group_ops;\n\tstruct configfs_attribute **ct_attrs;\n\tstruct configfs_bin_attribute **ct_bin_attrs;\n};\n\nstruct config_key {\n\tstruct config_item item;\n\tconst char *description;\n};\n\nstruct deflate_state;\n\ntypedef struct deflate_state deflate_state;\n\ntypedef block_state (*compress_func)(deflate_state *, int);\n\nstruct config_s {\n\tush good_length;\n\tush max_lazy;\n\tush nice_length;\n\tush max_chain;\n\tcompress_func func;\n};\n\ntypedef struct config_s config;\n\nstruct configfs_attribute {\n\tconst char *ca_name;\n\tstruct module *ca_owner;\n\tumode_t ca_mode;\n\tssize_t (*show)(struct config_item *, char *);\n\tssize_t (*store)(struct config_item *, const char *, size_t);\n};\n\nstruct configfs_bin_attribute {\n\tstruct configfs_attribute cb_attr;\n\tvoid *cb_private;\n\tsize_t cb_max_size;\n\tssize_t (*read)(struct config_item *, void *, size_t);\n\tssize_t (*write)(struct config_item *, const void *, size_t);\n};\n\nstruct configfs_buffer {\n\tsize_t count;\n\tloff_t pos;\n\tchar *page;\n\tconst struct configfs_item_operations *ops;\n\tstruct mutex mutex;\n\tint needs_read_fill;\n\tbool read_in_progress;\n\tbool write_in_progress;\n\tchar *bin_buffer;\n\tint bin_buffer_size;\n\tint cb_max_size;\n\tstruct config_item *item;\n\tstruct module *owner;\n\tunion {\n\t\tstruct configfs_attribute *attr;\n\t\tstruct configfs_bin_attribute *bin_attr;\n\t};\n};\n\nstruct iattr;\n\nstruct configfs_fragment;\n\nstruct configfs_dirent {\n\tatomic_t s_count;\n\tint s_dependent_count;\n\tstruct list_head s_sibling;\n\tstruct list_head s_children;\n\tint s_links;\n\tvoid *s_element;\n\tint s_type;\n\tumode_t s_mode;\n\tstruct dentry *s_dentry;\n\tstruct iattr *s_iattr;\n\tstruct configfs_fragment *s_frag;\n};\n\nstruct configfs_fragment {\n\tatomic_t frag_count;\n\tstruct rw_semaphore frag_sem;\n\tbool frag_dead;\n};\n\nstruct configfs_group_operations {\n\tstruct config_item * (*make_item)(struct config_group *, const char *);\n\tstruct config_group * (*make_group)(struct config_group *, const char *);\n\tvoid (*disconnect_notify)(struct config_group *, struct config_item *);\n\tvoid (*drop_item)(struct config_group *, struct config_item *);\n\tbool (*is_visible)(struct config_item *, struct configfs_attribute *, int);\n\tbool (*is_bin_visible)(struct config_item *, struct configfs_bin_attribute *, int);\n};\n\nstruct configfs_item_operations {\n\tvoid (*release)(struct config_item *);\n\tint (*allow_link)(struct config_item *, struct config_item *);\n\tvoid (*drop_link)(struct config_item *, struct config_item *);\n};\n\nstruct configfs_subsystem {\n\tstruct config_group su_group;\n\tstruct mutex su_mutex;\n};\n\nstruct console;\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct ebitmap_node;\n\nstruct ebitmap {\n\tstruct ebitmap_node *node;\n\tu32 highbit;\n};\n\nstruct type_set;\n\nstruct constraint_expr {\n\tu32 expr_type;\n\tu32 attr;\n\tu32 op;\n\tstruct ebitmap names;\n\tstruct type_set *type_names;\n\tstruct constraint_expr *next;\n};\n\nstruct constraint_node {\n\tu32 permissions;\n\tstruct constraint_expr *expr;\n\tstruct constraint_node *next;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n};\n\nstruct mls_level {\n\tu32 sens;\n\tstruct ebitmap cat;\n};\n\nstruct mls_range {\n\tstruct mls_level level[2];\n};\n\nstruct context {\n\tu32 user;\n\tu32 role;\n\tu32 type;\n\tu32 len;\n\tstruct mls_range range;\n\tchar *str;\n};\n\nstruct context_tracking {\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct convert_context_args {\n\tstruct policydb *oldp;\n\tstruct policydb *newp;\n};\n\nstruct copy_block_struct {\n\twait_queue_head_t wait;\n\tint ret;\n};\n\nstruct copy_subpage_arg {\n\tstruct folio *dst;\n\tstruct folio *src;\n\tstruct vm_area_struct *vma;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct evbuf_header {\n\tu16 length;\n\tu8 type;\n\tu8 flags;\n\tu16 _reserved;\n};\n\nstruct cpi_evbuf {\n\tstruct evbuf_header header;\n\tu8 id_format;\n\tu8 reserved0;\n\tu8 system_type[8];\n\tu64 reserved1;\n\tu8 system_name[8];\n\tu64 reserved2;\n\tu64 system_level;\n\tu64 reserved3;\n\tu8 sysplex_name[8];\n\tu8 reserved4[16];\n};\n\nstruct cpi_sccb {\n\tstruct sccb_header header;\n\tstruct cpi_evbuf cpi_evbuf;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct cpu_cf_events {\n\trefcount_t refcnt;\n\tatomic_t ctr_set[5];\n\tu64 state;\n\tu64 dev_state;\n\tunsigned int flags;\n\tsize_t used;\n\tsize_t usedss;\n\tunsigned char start[4096];\n\tunsigned char stop[4096];\n\tunsigned char data[4096];\n\tunsigned int sets;\n};\n\nstruct cpu_cf_ptr {\n\tstruct cpu_cf_events *cpucf;\n};\n\nstruct cpu_cf_root {\n\trefcount_t refcnt;\n\tstruct cpu_cf_ptr *cfptr;\n};\n\nstruct cpu_configure_sccb {\n\tstruct sccb_header header;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct hws_qsi_info_block {\n\tunsigned int b0_13: 14;\n\tunsigned int as: 1;\n\tunsigned int ad: 1;\n\tunsigned int b16_21: 6;\n\tunsigned int es: 1;\n\tunsigned int ed: 1;\n\tunsigned int b24_29: 6;\n\tunsigned int cs: 1;\n\tunsigned int cd: 1;\n\tunsigned int bsdes: 16;\n\tunsigned int dsdes: 16;\n\tlong unsigned int min_sampl_rate;\n\tlong unsigned int max_sampl_rate;\n\tlong unsigned int tear;\n\tlong unsigned int dear;\n\tunsigned int rsvrd0: 24;\n\tunsigned int ribm: 8;\n\tunsigned int cpu_speed;\n\tlong long unsigned int rsvrd1;\n\tlong long unsigned int rsvrd2;\n};\n\nstruct hws_lsctl_request_block {\n\tunsigned int s: 1;\n\tunsigned int h: 1;\n\tlong long unsigned int b2_53: 52;\n\tunsigned int es: 1;\n\tunsigned int ed: 1;\n\tunsigned int b56_61: 6;\n\tunsigned int cs: 1;\n\tunsigned int cd: 1;\n\tlong unsigned int interval;\n\tlong unsigned int tear;\n\tlong unsigned int dear;\n\tlong unsigned int rsvrd1;\n\tlong unsigned int rsvrd2;\n\tlong unsigned int rsvrd3;\n\tlong unsigned int rsvrd4;\n};\n\nstruct perf_buffer;\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tunion {\n\t\tu64 flags;\n\t\tu64 aux_flags;\n\t\tstruct {\n\t\t\tu64 skip_read: 1;\n\t\t};\n\t};\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct cpu_hw_sf {\n\tstruct hws_qsi_info_block qsi;\n\tstruct hws_lsctl_request_block lsctl;\n\tstruct sf_buffer sfb;\n\tunsigned int flags;\n\tstruct perf_event *event;\n\tstruct perf_output_handle handle;\n};\n\nstruct cpu_inf {\n\tu64 lpar_cap;\n\tu64 lpar_grp_cap;\n\tu64 lpar_weight;\n\tu64 all_weight;\n\tint cpu_num_ded;\n\tint cpu_num_shd;\n};\n\nstruct cpuid {\n\tunsigned int version: 8;\n\tunsigned int ident: 24;\n\tunsigned int machine: 16;\n\tunsigned int unused: 16;\n};\n\nstruct cpu_info {\n\tunsigned int cpu_mhz_dynamic;\n\tunsigned int cpu_mhz_static;\n\tstruct cpuid cpu_id;\n};\n\nstruct cpu_irq_data {\n\tcall_single_data_t csd;\n\tatomic_t scheduled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_topology_s390 {\n\tshort unsigned int thread_id;\n\tshort unsigned int core_id;\n\tshort unsigned int socket_id;\n\tshort unsigned int book_id;\n\tshort unsigned int drawer_id;\n\tshort unsigned int dedicated: 1;\n\tint booted_cores;\n\tcpumask_t thread_mask;\n\tcpumask_t core_mask;\n\tcpumask_t book_mask;\n\tcpumask_t drawer_mask;\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct kernel_cpustat;\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tu64 *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_policy;\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tstruct list_head governor_list;\n\tstruct module *owner;\n\tu8 flags;\n};\n\nstruct clk;\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct cpufreq_stats;\n\nstruct thermal_cooling_device;\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct freq_qos_request;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tbool strict_target;\n\tbool efficiencies_available;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tbool boost_enabled;\n\tbool boost_supported;\n\tunsigned int cached_target_freq;\n\tunsigned int cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n};\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpumf_ctr_info {\n\tu16 cfvn;\n\tu16 auth_ctl;\n\tu16 enable_ctl;\n\tu16 act_ctl;\n\tu16 max_cpu;\n\tu16 csvn;\n\tu16 max_cg;\n\tu16 reserved1;\n\tu32 reserved2[12];\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct cramfs_info {\n\t__u32 crc;\n\t__u32 edition;\n\t__u32 blocks;\n\t__u32 files;\n};\n\nstruct cramfs_inode {\n\t__u32 mode: 16;\n\t__u32 uid: 16;\n\t__u32 size: 24;\n\t__u32 gid: 8;\n\t__u32 namelen: 6;\n\t__u32 offset: 26;\n};\n\nstruct cramfs_super {\n\t__u32 magic;\n\t__u32 size;\n\t__u32 flags;\n\t__u32 future;\n\t__u8 signature[16];\n\tstruct cramfs_info fsid;\n\t__u8 name[16];\n\tstruct cramfs_inode root;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct crash_mem {\n\tunsigned int max_nr_ranges;\n\tunsigned int nr_ranges;\n\tstruct range ranges[0];\n};\n\nstruct crc64_pi_tuple {\n\t__be64 guard_tag;\n\t__be16 app_tag;\n\t__u8 ref_tag[6];\n};\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tvoid *security;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct cred_security_struct {\n\tu32 osid;\n\tu32 sid;\n\tu32 exec_sid;\n\tu32 create_sid;\n\tu32 keycreate_sid;\n\tu32 sockcreate_sid;\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct crw {\n\t__u32 res1: 1;\n\t__u32 slct: 1;\n\t__u32 oflw: 1;\n\t__u32 chn: 1;\n\t__u32 rsc: 4;\n\t__u32 anc: 1;\n\t__u32 res2: 1;\n\t__u32 erc: 6;\n\t__u32 rsid: 16;\n};\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_acomp_ctx {\n\tstruct crypto_acomp *acomp;\n\tstruct acomp_req *req;\n\tstruct crypto_wait wait;\n\tu8 *buffer;\n\tstruct mutex mutex;\n};\n\nstruct crypto_acomp_stream {\n\tspinlock_t lock;\n\tvoid *ctx;\n};\n\nstruct crypto_acomp_streams {\n\tvoid * (*alloc_ctx)(void);\n\tvoid (*free_ctx)(void *);\n\tstruct crypto_acomp_stream *streams;\n\tstruct work_struct stream_work;\n\tcpumask_t stream_want;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_aes_ctx {\n\tu32 key_enc[60];\n\tu32 key_dec[60];\n\tu32 key_length;\n};\n\nstruct crypto_ahash {\n\tbool using_shash;\n\tunsigned int statesize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_akcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_akcipher_sync_data {\n\tstruct crypto_akcipher *tfm;\n\tconst void *src;\n\tvoid *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct akcipher_request *req;\n\tstruct crypto_wait cwait;\n\tstruct scatterlist sg;\n\tu8 *buf;\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher;\n\nstruct crypto_cts_ctx {\n\tstruct crypto_skcipher *child;\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_cts_reqctx {\n\tstruct scatterlist sg[2];\n\tunsigned int offset;\n\tstruct skcipher_request subreq;\n};\n\nstruct crypto_gcm_ctx {\n\tstruct crypto_skcipher *ctr;\n\tstruct crypto_ahash *ghash;\n};\n\nstruct crypto_gcm_ghash_ctx {\n\tunsigned int cryptlen;\n\tstruct scatterlist *src;\n\tint (*complete)(struct aead_request *, u32);\n};\n\nstruct crypto_gcm_req_priv_ctx {\n\tu8 iv[16];\n\tu8 auth_tag[16];\n\tu8 iauth_tag[16];\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct scatterlist sg;\n\tstruct crypto_gcm_ghash_ctx ghash_ctx;\n\tunion {\n\t\tstruct ahash_request ahreq;\n\t\tstruct skcipher_request skreq;\n\t} u;\n};\n\nstruct crypto_hash_walk {\n\tconst char *data;\n\tunsigned int offset;\n\tunsigned int flags;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n};\n\nstruct crypto_kpp {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_kpp_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n\tbool test_started;\n};\n\nstruct crypto_lskcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_lskcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct crypto_report_acomp {\n\tchar type[64];\n};\n\nstruct crypto_report_aead {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int maxauthsize;\n\tunsigned int ivsize;\n};\n\nstruct crypto_report_akcipher {\n\tchar type[64];\n};\n\nstruct crypto_report_blkcipher {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n};\n\nstruct crypto_report_comp {\n\tchar type[64];\n};\n\nstruct crypto_report_hash {\n\tchar type[64];\n\tunsigned int blocksize;\n\tunsigned int digestsize;\n};\n\nstruct crypto_report_kpp {\n\tchar type[64];\n};\n\nstruct crypto_report_rng {\n\tchar type[64];\n\tunsigned int seedsize;\n};\n\nstruct crypto_report_sig {\n\tchar type[64];\n};\n\nstruct crypto_rfc3686_ctx {\n\tstruct crypto_skcipher *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc3686_req_ctx {\n\tu8 iv[16];\n\tstruct skcipher_request subreq;\n};\n\nstruct crypto_rfc4106_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4106_req_ctx {\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rfc4543_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4543_instance_ctx {\n\tstruct crypto_aead_spawn aead;\n};\n\nstruct crypto_rfc4543_req_ctx {\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sig {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sig_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sync_aead {\n\tstruct crypto_aead base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct hlist_head dead;\n\tstruct module *module;\n\tstruct work_struct free_work;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tvoid (*destroy)(struct crypto_alg *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n\tunsigned int algsize;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_alg data;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct css_chsc_char {\n\tu64 res;\n\tint: 20;\n\tu32 secm: 1;\n\tchar: 1;\n\tu32 scmc: 1;\n\tint: 9;\n\tshort: 11;\n\tu32 scssc: 1;\n\tu32 scsscf: 1;\n\tshort: 3;\n\tchar: 4;\n\tu32 pnso: 1;\n};\n\nstruct css_device_id {\n\t__u8 match_flags;\n\t__u8 type;\n\tkernel_ulong_t driver_data;\n};\n\nstruct css_driver {\n\tstruct css_device_id *subchannel_type;\n\tstruct device_driver drv;\n\tvoid (*irq)(struct subchannel *);\n\tint (*chp_event)(struct subchannel *, struct chp_link *, int);\n\tint (*sch_event)(struct subchannel *, int);\n\tint (*probe)(struct subchannel *);\n\tvoid (*remove)(struct subchannel *);\n\tvoid (*shutdown)(struct subchannel *);\n\tint (*settle)(void);\n};\n\nstruct css_general_char {\n\tshort: 12;\n\tu64 dynio: 1;\n\tshort: 3;\n\tchar: 1;\n\tu64 eadm: 1;\n\tint: 14;\n\tshort: 9;\n\tu64 aif: 1;\n\tchar: 3;\n\tu64 mcss: 1;\n\tu64 fcs: 1;\n\tshort: 1;\n\tu64 ext_mb: 1;\n\tchar: 7;\n\tu64 aif_tdd: 1;\n\tchar: 1;\n\tu64 qebsm: 1;\n\tchar: 2;\n\tu64 aiv: 1;\n\tlong: 2;\n\tchar: 3;\n\tu64 aif_qdio: 1;\n\tshort: 12;\n\tu64 eadm_rf: 1;\n\tchar: 1;\n\tu64 cib: 1;\n\tchar: 5;\n\tu64 fcx: 1;\n\tint: 7;\n\tshort: 12;\n\tu64 alt_ssi: 1;\n\tchar: 1;\n\tu64 narf: 1;\n\tshort: 1;\n\tchar: 4;\n\tu64 enarf: 1;\n\tchar: 3;\n\tchar: 3;\n\tu64 util_str: 1;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[14];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[14];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct csum_pseudo_header {\n\t__be64 data_seq;\n\t__be32 subflow_seq;\n\t__be16 data_len;\n\t__sum16 csum;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ct_data_s {\n\tunion {\n\t\tush freq;\n\t\tush code;\n\t} fc;\n\tunion {\n\t\tush dad;\n\t\tush len;\n\t} dl;\n};\n\ntypedef struct ct_data_s ct_data;\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nstruct ctlreg {\n\tlong unsigned int val;\n};\n\nunion ctlreg0 {\n\tlong unsigned int val;\n\tstruct ctlreg reg;\n\tstruct {\n\t\tchar: 8;\n\t\tlong unsigned int tcx: 1;\n\t\tlong unsigned int pifo: 1;\n\t\tchar: 3;\n\t\tlong unsigned int ccc: 1;\n\t\tlong unsigned int pec: 1;\n\t\tshort: 1;\n\t\tshort: 14;\n\t\tlong unsigned int wti: 1;\n\t\tint: 1;\n\t\tchar: 3;\n\t\tlong unsigned int lap: 1;\n\t\tchar: 4;\n\t\tlong unsigned int edat: 1;\n\t\tchar: 2;\n\t\tlong unsigned int iep: 1;\n\t\tchar: 1;\n\t\tlong unsigned int afp: 1;\n\t\tlong unsigned int vx: 1;\n\t\tshort: 1;\n\t\tchar: 6;\n\t\tlong unsigned int sssm: 1;\n\t};\n};\n\nunion ctlreg15 {\n\tlong unsigned int val;\n\tstruct ctlreg reg;\n\tstruct {\n\t\tlong unsigned int lsea: 61;\n\t};\n};\n\nunion ctlreg2 {\n\tlong unsigned int val;\n\tstruct ctlreg reg;\n\tstruct {\n\t\tlong: 33;\n\t\tlong unsigned int ducto: 25;\n\t\tchar: 1;\n\t\tlong unsigned int gse: 1;\n\t\tchar: 1;\n\t\tlong unsigned int tds: 1;\n\t\tlong unsigned int tdc: 2;\n\t};\n};\n\nunion ctlreg5 {\n\tlong unsigned int val;\n\tstruct ctlreg reg;\n\tstruct {\n\t\tlong: 33;\n\t\tlong unsigned int pasteo: 25;\n\t};\n};\n\nstruct ctlreg_parms {\n\tlong unsigned int andval;\n\tlong unsigned int orval;\n\tlong unsigned int val;\n\tint request;\n\tint cr;\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct dahash_test {\n\tuint16_t start;\n\tuint16_t length;\n\txfs_dahash_t dahash;\n\txfs_dahash_t ascii_ci_dahash;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct dasd_profile_info;\n\nstruct dasd_profile {\n\tstruct dentry *dentry;\n\tstruct dasd_profile_info *data;\n\tspinlock_t lock;\n};\n\nstruct dasd_block {\n\tstruct gendisk *gdp;\n\tspinlock_t request_queue_lock;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct file *bdev_file;\n\tatomic_t open_count;\n\tlong unsigned int blocks;\n\tunsigned int bp_block;\n\tunsigned int s2b_shift;\n\tstruct dasd_device *base;\n\tstruct list_head ccw_queue;\n\tspinlock_t queue_lock;\n\tatomic_t tasklet_scheduled;\n\tstruct tasklet_struct tasklet;\n\tstruct timer_list timer;\n\tstruct dentry *debugfs_dentry;\n\tstruct dasd_profile profile;\n\tstruct list_head format_list;\n\tspinlock_t format_lock;\n\tatomic_t trkcount;\n};\n\nstruct dasd_queue;\n\nstruct dasd_ccw_req {\n\tunsigned int magic;\n\tint intrc;\n\tstruct list_head devlist;\n\tstruct list_head blocklist;\n\tstruct dasd_block *block;\n\tstruct dasd_device *memdev;\n\tstruct dasd_device *startdev;\n\tstruct dasd_device *basedev;\n\tvoid *cpaddr;\n\tshort int retries;\n\tunsigned char cpmode;\n\tchar status;\n\tchar lpm;\n\tlong unsigned int flags;\n\tstruct dasd_queue *dq;\n\tlong unsigned int starttime;\n\tlong unsigned int expires;\n\tvoid *data;\n\tstruct irb irb;\n\tstruct dasd_ccw_req *refers;\n\tvoid *function;\n\tvoid *mem_chunk;\n\tlong unsigned int buildclk;\n\tlong unsigned int startclk;\n\tlong unsigned int stopclk;\n\tlong unsigned int endclk;\n\tvoid (*callback)(struct dasd_ccw_req *, void *);\n\tvoid *callback_data;\n\tunsigned int proc_bytes;\n\tunsigned int trkcount;\n};\n\nstruct dasd_ckd_host_information {\n\t__u8 access_flags;\n\t__u8 entry_size;\n\t__u16 entry_count;\n\t__u8 entry[16390];\n};\n\nstruct dasd_ckd_path_group_entry {\n\t__u8 status_flags;\n\t__u8 pgid[11];\n\t__u8 sysplex_name[8];\n\t__u32 timestamp;\n\t__u32 cylinder;\n\t__u8 reserved[4];\n};\n\nstruct dasd_ned;\n\nstruct dasd_sneq;\n\nstruct vd_sneq;\n\nstruct dasd_gneq;\n\nstruct dasd_conf {\n\tu8 *data;\n\tint len;\n\tstruct dasd_ned *ned;\n\tstruct dasd_sneq *sneq;\n\tstruct vd_sneq *vdsneq;\n\tstruct dasd_gneq *gneq;\n};\n\nstruct dasd_ned {\n\tstruct {\n\t\t__u8 identifier: 2;\n\t\t__u8 token_id: 1;\n\t\t__u8 sno_valid: 1;\n\t\t__u8 subst_sno: 1;\n\t\t__u8 recNED: 1;\n\t\t__u8 emuNED: 1;\n\t\t__u8 reserved: 1;\n\t} flags;\n\t__u8 descriptor;\n\t__u8 dev_class;\n\t__u8 reserved;\n\t__u8 dev_type[6];\n\t__u8 dev_model[3];\n\t__u8 HDA_manufacturer[3];\n\tstruct {\n\t\t__u8 HDA_location[2];\n\t\t__u8 HDA_seqno[12];\n\t} serial;\n\t__u8 ID;\n\t__u8 unit_addr;\n};\n\nstruct dasd_gneq {\n\tstruct {\n\t\t__u8 identifier: 2;\n\t\t__u8 reserved: 6;\n\t} flags;\n\t__u8 record_selector;\n\t__u8 reserved[4];\n\tstruct {\n\t\t__u8 value: 2;\n\t\t__u8 number: 6;\n\t} timeout;\n\t__u8 reserved3;\n\t__u16 subsystemID;\n\t__u8 reserved2[22];\n};\n\nstruct dasd_conf_data {\n\tstruct dasd_ned neds[5];\n\tu8 reserved[64];\n\tstruct dasd_gneq gneq;\n};\n\nstruct dasd_copy_entry {\n\tchar busid[20];\n\tstruct dasd_device *device;\n\tbool primary;\n\tbool configured;\n};\n\nstruct dasd_copy_relation {\n\tstruct dasd_copy_entry entry[5];\n\tstruct dasd_copy_entry *active;\n};\n\nstruct dasd_copypair_swap_data_t {\n\tchar primary[20];\n\tchar secondary[20];\n\t__u8 reserved[64];\n};\n\nstruct dasd_cuir_message {\n\t__u16 length;\n\t__u8 format;\n\t__u8 code;\n\t__u32 message_id;\n\t__u8 flags;\n\t__u8 neq_map[3];\n\t__u8 ned_map;\n\t__u8 record_selector;\n} __attribute__((packed));\n\nstruct dasd_path {\n\tlong unsigned int flags;\n\tu8 cssid;\n\tu8 ssid;\n\tu8 chpid;\n\tstruct dasd_conf_data *conf_data;\n\tatomic_t error_count;\n\tlong unsigned int errorclk;\n\tu8 fc_security;\n\tstruct kobject kobj;\n\tbool in_sysfs;\n};\n\nstruct dasd_format_entry {\n\tstruct list_head list;\n\tsector_t track;\n};\n\nstruct dasd_discipline;\n\nstruct debug_info;\n\ntypedef struct debug_info debug_info_t;\n\nstruct dasd_device {\n\tstruct dasd_block *block;\n\tunsigned int devindex;\n\tlong unsigned int flags;\n\tshort unsigned int features;\n\tstruct dasd_ccw_req *eer_cqr;\n\tstruct dasd_discipline *discipline;\n\tstruct dasd_discipline *base_discipline;\n\tvoid *private;\n\tstruct dasd_path path[8];\n\t__u8 opm;\n\tint state;\n\tint target;\n\tstruct mutex state_mutex;\n\tint stopped;\n\tatomic_t ref_count;\n\tstruct list_head ccw_queue;\n\tspinlock_t mem_lock;\n\tvoid *ccw_mem;\n\tvoid *erp_mem;\n\tvoid *ese_mem;\n\tstruct list_head ccw_chunks;\n\tstruct list_head erp_chunks;\n\tstruct list_head ese_chunks;\n\tatomic_t tasklet_scheduled;\n\tstruct tasklet_struct tasklet;\n\tstruct work_struct kick_work;\n\tstruct work_struct reload_device;\n\tstruct work_struct kick_validate;\n\tstruct work_struct suc_work;\n\tstruct work_struct requeue_requests;\n\tstruct timer_list timer;\n\tdebug_info_t *debug_area;\n\tstruct ccw_device *cdev;\n\tstruct list_head alias_list;\n\tlong unsigned int default_expires;\n\tlong unsigned int default_retries;\n\tlong unsigned int blk_timeout;\n\tlong unsigned int path_thrhld;\n\tlong unsigned int path_interval;\n\tstruct dentry *debugfs_dentry;\n\tstruct dentry *hosts_dentry;\n\tstruct dasd_profile profile;\n\tstruct dasd_format_entry format_entry;\n\tstruct kset *paths_info;\n\tstruct dasd_copy_relation *copy;\n\tlong unsigned int aq_mask;\n\tunsigned int aq_timeouts;\n};\n\nstruct dasd_devmap {\n\tstruct list_head list;\n\tchar bus_id[20];\n\tunsigned int devindex;\n\tshort unsigned int features;\n\tstruct dasd_device *device;\n\tstruct dasd_copy_relation *copy;\n\tunsigned int aq_mask;\n};\n\nstruct dasd_diag_bio {\n\tu8 type;\n\tu8 status;\n\tu8 spare1[2];\n\tu32 alet;\n\tblocknum_t block_number;\n\tvoid *buffer;\n};\n\nstruct dasd_diag_characteristics {\n\tu16 dev_nr;\n\tu16 rdc_len;\n\tu8 vdev_class;\n\tu8 vdev_type;\n\tu8 vdev_status;\n\tu8 vdev_flags;\n\tu8 rdev_class;\n\tu8 rdev_type;\n\tu8 rdev_model;\n\tu8 rdev_features;\n};\n\nstruct dasd_diag_private {\n\tstruct dasd_diag_characteristics rdc_data;\n\tstruct dasd_diag_rw_io iob;\n\tstruct dasd_diag_init_io iib;\n\tblocknum_t pt_block;\n\tstruct ccw_dev_id dev_id;\n};\n\nstruct dasd_diag_req {\n\tunsigned int block_count;\n\tstruct dasd_diag_bio bio[0];\n};\n\ntypedef struct dasd_ccw_req * (*dasd_erp_fn_t)(struct dasd_ccw_req *);\n\nstruct format_data_t;\n\nstruct format_check_t;\n\nstruct dasd_information2_t;\n\nstruct dasd_pprc_data_sc4;\n\nstruct dasd_discipline {\n\tstruct module *owner;\n\tchar ebcname[8];\n\tchar name[8];\n\tbool has_discard;\n\tstruct list_head list;\n\tint (*check_device)(struct dasd_device *);\n\tvoid (*uncheck_device)(struct dasd_device *);\n\tint (*do_analysis)(struct dasd_block *);\n\tint (*pe_handler)(struct dasd_device *, __u8, __u8);\n\tint (*basic_to_ready)(struct dasd_device *);\n\tint (*online_to_ready)(struct dasd_device *);\n\tint (*basic_to_known)(struct dasd_device *);\n\tunsigned int (*max_sectors)(struct dasd_block *);\n\tstruct dasd_ccw_req * (*build_cp)(struct dasd_device *, struct dasd_block *, struct request *);\n\tint (*start_IO)(struct dasd_ccw_req *);\n\tint (*term_IO)(struct dasd_ccw_req *);\n\tvoid (*handle_terminated_request)(struct dasd_ccw_req *);\n\tint (*format_device)(struct dasd_device *, struct format_data_t *, int);\n\tint (*check_device_format)(struct dasd_device *, struct format_check_t *, int);\n\tint (*free_cp)(struct dasd_ccw_req *, struct request *);\n\tdasd_erp_fn_t (*erp_action)(struct dasd_ccw_req *);\n\tdasd_erp_fn_t (*erp_postaction)(struct dasd_ccw_req *);\n\tvoid (*dump_sense)(struct dasd_device *, struct dasd_ccw_req *, struct irb *);\n\tvoid (*dump_sense_dbf)(struct dasd_device *, struct irb *, char *);\n\tvoid (*check_for_device_change)(struct dasd_device *, struct dasd_ccw_req *, struct irb *);\n\tint (*fill_geometry)(struct dasd_block *, struct hd_geometry *);\n\tint (*fill_info)(struct dasd_device *, struct dasd_information2_t *);\n\tint (*ioctl)(struct dasd_block *, unsigned int, void *);\n\tint (*reload)(struct dasd_device *);\n\tint (*get_uid)(struct dasd_device *, struct dasd_uid *);\n\tvoid (*kick_validate)(struct dasd_device *);\n\tint (*check_attention)(struct dasd_device *, __u8);\n\tint (*host_access_count)(struct dasd_device *);\n\tint (*hosts_print)(struct dasd_device *, struct seq_file *);\n\tvoid (*handle_hpf_error)(struct dasd_device *, struct irb *);\n\tvoid (*disable_hpf)(struct dasd_device *);\n\tint (*hpf_enabled)(struct dasd_device *);\n\tvoid (*reset_path)(struct dasd_device *, __u8);\n\tint (*is_ese)(struct dasd_device *);\n\tint (*space_allocated)(struct dasd_device *);\n\tint (*space_configured)(struct dasd_device *);\n\tint (*logical_capacity)(struct dasd_device *);\n\tint (*release_space)(struct dasd_device *, struct format_data_t *);\n\tint (*ext_pool_id)(struct dasd_device *);\n\tint (*ext_size)(struct dasd_device *);\n\tint (*ext_pool_cap_at_warnlevel)(struct dasd_device *);\n\tint (*ext_pool_warn_thrshld)(struct dasd_device *);\n\tint (*ext_pool_oos)(struct dasd_device *);\n\tint (*ext_pool_exhaust)(struct dasd_device *, struct dasd_ccw_req *);\n\tstruct dasd_ccw_req * (*ese_format)(struct dasd_device *, struct dasd_ccw_req *, struct irb *);\n\tint (*ese_read)(struct dasd_ccw_req *, struct irb *);\n\tint (*pprc_status)(struct dasd_device *, struct dasd_pprc_data_sc4 *);\n\tbool (*pprc_enabled)(struct dasd_device *);\n\tint (*copy_pair_swap)(struct dasd_device *, char *, char *);\n\tint (*device_ping)(struct dasd_device *);\n};\n\nstruct dasd_dso_ras_data {\n\t__u8 order;\n\tstruct {\n\t\t__u8 message: 1;\n\t\t__u8 reserved1: 2;\n\t\t__u8 vol_type: 1;\n\t\t__u8 reserved2: 4;\n\t} flags;\n\tstruct {\n\t\t__u8 reserved1: 2;\n\t\t__u8 by_extent: 1;\n\t\t__u8 guarantee_init: 1;\n\t\t__u8 force_release: 1;\n\t\t__u16 reserved2: 11;\n\t} op_flags;\n\t__u8 lss;\n\t__u8 dev_addr;\n\t__u32 reserved1;\n\t__u8 reserved2[10];\n\t__u16 nr_exts;\n\t__u16 reserved3;\n} __attribute__((packed));\n\nstruct dasd_dso_ras_ext_range {\n\tstruct ch_t beg_ext;\n\tstruct ch_t end_ext;\n};\n\nstruct dasd_eckd_characteristics {\n\t__u16 cu_type;\n\tstruct {\n\t\tunsigned char support: 2;\n\t\tunsigned char async: 1;\n\t\tunsigned char reserved: 1;\n\t\tunsigned char cache_info: 1;\n\t\tunsigned char model: 3;\n\t} cu_model;\n\t__u16 dev_type;\n\t__u8 dev_model;\n\tstruct {\n\t\tunsigned char mult_burst: 1;\n\t\tunsigned char RT_in_LR: 1;\n\t\tunsigned char reserved1: 1;\n\t\tunsigned char RD_IN_LR: 1;\n\t\tunsigned char reserved2: 4;\n\t\tunsigned char reserved3: 8;\n\t\tunsigned char defect_wr: 1;\n\t\tunsigned char XRC_supported: 1;\n\t\tunsigned char PPRC_enabled: 1;\n\t\tunsigned char striping: 1;\n\t\tunsigned char reserved5: 4;\n\t\tunsigned char cfw: 1;\n\t\tunsigned char reserved6: 2;\n\t\tunsigned char cache: 1;\n\t\tunsigned char dual_copy: 1;\n\t\tunsigned char dfw: 1;\n\t\tunsigned char reset_alleg: 1;\n\t\tunsigned char sense_down: 1;\n\t} facilities;\n\t__u8 dev_class;\n\t__u8 unit_type;\n\t__u16 no_cyl;\n\t__u16 trk_per_cyl;\n\t__u8 sec_per_trk;\n\t__u8 byte_per_track[3];\n\t__u16 home_bytes;\n\t__u8 formula;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 f1;\n\t\t\t__u16 f2;\n\t\t\t__u16 f3;\n\t\t} __attribute__((packed)) f_0x01;\n\t\tstruct {\n\t\t\t__u8 f1;\n\t\t\t__u8 f2;\n\t\t\t__u8 f3;\n\t\t\t__u8 f4;\n\t\t\t__u8 f5;\n\t\t} f_0x02;\n\t} factors;\n\t__u16 first_alt_trk;\n\t__u16 no_alt_trk;\n\t__u16 first_dia_trk;\n\t__u16 no_dia_trk;\n\t__u16 first_sup_trk;\n\t__u16 no_sup_trk;\n\t__u8 MDR_ID;\n\t__u8 OBR_ID;\n\t__u8 director;\n\t__u8 rd_trk_set;\n\t__u16 max_rec_zero;\n\t__u8 reserved1;\n\t__u8 RWANY_in_LR;\n\t__u8 factor6;\n\t__u8 factor7;\n\t__u8 factor8;\n\t__u8 reserved2[3];\n\t__u8 reserved3[6];\n\t__u32 long_no_cyl;\n} __attribute__((packed));\n\nstruct eckd_count {\n\t__u16 cyl;\n\t__u16 head;\n\t__u8 record;\n\t__u8 kl;\n\t__u16 dl;\n};\n\nstruct dasd_rssd_features {\n\tchar feature[256];\n};\n\nstruct dasd_rssd_vsq {\n\tstruct {\n\t\t__u8 tse: 1;\n\t\t__u8 space_not_available: 1;\n\t\t__u8 ese: 1;\n\t\t__u8 unused: 5;\n\t} vol_info;\n\t__u8 unused1;\n\t__u16 extent_pool_id;\n\t__u8 warn_cap_limit;\n\t__u8 warn_cap_guaranteed;\n\t__u16 unused2;\n\t__u32 limit_capacity;\n\t__u32 guaranteed_capacity;\n\t__u32 space_allocated;\n\t__u32 space_configured;\n\t__u32 logical_capacity;\n};\n\nstruct dasd_ext_pool_sum {\n\t__u16 pool_id;\n\t__u8 repo_warn_thrshld;\n\t__u8 warn_thrshld;\n\tstruct {\n\t\t__u8 type: 1;\n\t\t__u8 track_space_efficient: 1;\n\t\t__u8 extent_space_efficient: 1;\n\t\t__u8 standard_volume: 1;\n\t\t__u8 extent_size_valid: 1;\n\t\t__u8 capacity_at_warnlevel: 1;\n\t\t__u8 pool_oos: 1;\n\t\t__u8 unused0: 1;\n\t\t__u8 unused1;\n\t} flags;\n\tstruct {\n\t\t__u8 reserved0: 1;\n\t\t__u8 size_1G: 1;\n\t\t__u8 reserved1: 5;\n\t\t__u8 size_16M: 1;\n\t} extent_size;\n\t__u8 unused;\n};\n\nstruct dasd_eckd_private {\n\tstruct dasd_eckd_characteristics rdc_data;\n\tstruct dasd_conf conf;\n\tstruct eckd_count count_area[5];\n\tint init_cqr_status;\n\tint uses_cdl;\n\tstruct attrib_data_t attrib;\n\tstruct dasd_rssd_features features;\n\tstruct dasd_rssd_vsq vsq;\n\tstruct dasd_ext_pool_sum eps;\n\tu32 real_cyl;\n\tstruct dasd_uid uid;\n\tstruct alias_pav_group *pavgroup;\n\tstruct alias_lcu *lcu;\n\tint count;\n\tu32 fcx_max_data;\n\tchar suc_reason;\n};\n\nstruct dasd_eer_header {\n\t__u32 total_size;\n\t__u32 trigger;\n\t__u64 tv_sec;\n\t__u64 tv_usec;\n\tchar busid[10];\n} __attribute__((packed));\n\nstruct dasd_fba_characteristics {\n\tunion {\n\t\t__u8 c;\n\t\tstruct {\n\t\t\tunsigned char reserved: 1;\n\t\t\tunsigned char overrunnable: 1;\n\t\t\tunsigned char burst_byte: 1;\n\t\t\tunsigned char data_chain: 1;\n\t\t\tunsigned char zeros: 4;\n\t\t} bits;\n\t} mode;\n\tunion {\n\t\t__u8 c;\n\t\tstruct {\n\t\t\tunsigned char zero0: 1;\n\t\t\tunsigned char removable: 1;\n\t\t\tunsigned char shared: 1;\n\t\t\tunsigned char zero1: 1;\n\t\t\tunsigned char mam: 1;\n\t\t\tunsigned char zeros: 3;\n\t\t} bits;\n\t} features;\n\t__u8 dev_class;\n\t__u8 unit_type;\n\t__u16 blk_size;\n\t__u32 blk_per_cycl;\n\t__u32 blk_per_bound;\n\t__u32 blk_bdsa;\n\t__u32 reserved0;\n\t__u16 reserved1;\n\t__u16 blk_ce;\n\t__u32 reserved2;\n\t__u16 reserved3;\n} __attribute__((packed));\n\nstruct dasd_fba_private {\n\tstruct dasd_fba_characteristics rdc_data;\n};\n\nstruct dasd_information2_t {\n\tunsigned int devno;\n\tunsigned int real_devno;\n\tunsigned int schid;\n\tunsigned int cu_type: 16;\n\tunsigned int cu_model: 8;\n\tlong: 8;\n\tunsigned int dev_type: 16;\n\tunsigned int dev_model: 8;\n\tunsigned int open_count;\n\tunsigned int req_queue_len;\n\tunsigned int chanq_len;\n\tchar type[4];\n\tunsigned int status;\n\tunsigned int label_block;\n\tunsigned int FBA_layout;\n\tunsigned int characteristics_size;\n\tunsigned int confdata_size;\n\tchar characteristics[64];\n\tchar configuration_data[256];\n\tunsigned int format;\n\tunsigned int features;\n\tunsigned int reserved0;\n\tunsigned int reserved1;\n\tunsigned int reserved2;\n\tunsigned int reserved3;\n\tunsigned int reserved4;\n\tunsigned int reserved5;\n\tunsigned int reserved6;\n\tunsigned int reserved7;\n};\n\ntypedef struct dasd_information2_t dasd_information2_t;\n\nstruct dasd_mchunk {\n\tstruct list_head list;\n\tlong unsigned int size;\n};\n\nstruct dasd_oos_message {\n\t__u16 length;\n\t__u8 format;\n\t__u8 code;\n\t__u8 percentage_empty;\n\t__u8 reserved;\n\t__u16 ext_pool_id;\n\t__u16 token;\n\t__u8 unused[6];\n};\n\nstruct dasd_pprc_header {\n\t__u8 entries;\n\t__u8 unused;\n\t__u16 entry_length;\n\t__u32 unused2;\n};\n\nstruct dasd_pprc_dev_info {\n\t__u8 state;\n\t__u8 flags;\n\t__u8 reserved1[2];\n\t__u8 prim_lss;\n\t__u8 primary;\n\t__u8 sec_lss;\n\t__u8 secondary;\n\t__u16 pprc_id;\n\t__u8 reserved2[12];\n\t__u16 prim_cu_ssid;\n\t__u8 reserved3[12];\n\t__u16 sec_cu_ssid;\n\t__u8 reserved4[90];\n};\n\nstruct dasd_pprc_data_sc4 {\n\tstruct dasd_pprc_header header;\n\tstruct dasd_pprc_dev_info dev_info[5];\n};\n\nstruct dasd_profile_info {\n\tunsigned int dasd_io_reqs;\n\tunsigned int dasd_io_sects;\n\tunsigned int dasd_io_secs[32];\n\tunsigned int dasd_io_times[32];\n\tunsigned int dasd_io_timps[32];\n\tunsigned int dasd_io_time1[32];\n\tunsigned int dasd_io_time2[32];\n\tunsigned int dasd_io_time2ps[32];\n\tunsigned int dasd_io_time3[32];\n\tunsigned int dasd_io_nr_req[32];\n\tstruct timespec64 starttod;\n\tunsigned int dasd_io_alias;\n\tunsigned int dasd_io_tpm;\n\tunsigned int dasd_read_reqs;\n\tunsigned int dasd_read_sects;\n\tunsigned int dasd_read_alias;\n\tunsigned int dasd_read_tpm;\n\tunsigned int dasd_read_secs[32];\n\tunsigned int dasd_read_times[32];\n\tunsigned int dasd_read_time1[32];\n\tunsigned int dasd_read_time2[32];\n\tunsigned int dasd_read_time3[32];\n\tunsigned int dasd_read_nr_req[32];\n\tlong unsigned int dasd_sum_times;\n\tlong unsigned int dasd_sum_time_str;\n\tlong unsigned int dasd_sum_time_irq;\n\tlong unsigned int dasd_sum_time_end;\n};\n\nstruct dasd_profile_info_t {\n\tunsigned int dasd_io_reqs;\n\tunsigned int dasd_io_sects;\n\tunsigned int dasd_io_secs[32];\n\tunsigned int dasd_io_times[32];\n\tunsigned int dasd_io_timps[32];\n\tunsigned int dasd_io_time1[32];\n\tunsigned int dasd_io_time2[32];\n\tunsigned int dasd_io_time2ps[32];\n\tunsigned int dasd_io_time3[32];\n\tunsigned int dasd_io_nr_req[32];\n};\n\nstruct dasd_psf_cuir_response {\n\t__u8 order;\n\t__u8 flags;\n\t__u8 cc;\n\t__u8 chpid;\n\t__u16 device_nr;\n\t__u16 reserved;\n\t__u32 message_id;\n\t__u64 system_id;\n\t__u8 cssid;\n\t__u8 ssid;\n} __attribute__((packed));\n\nstruct dasd_psf_prssd_data {\n\tunsigned char order;\n\tunsigned char flags;\n\tunsigned char reserved1;\n\tunsigned char reserved2;\n\tunsigned char lss;\n\tunsigned char volume;\n\tunsigned char suborder;\n\tunsigned char varies[5];\n};\n\nstruct dasd_psf_query_host_access {\n\t__u8 access_flag;\n\t__u8 version;\n\t__u16 CKD_length;\n\t__u16 SCSI_length;\n\t__u8 unused[10];\n\t__u8 host_access_information[16394];\n};\n\nstruct dasd_psf_ssc_data {\n\tunsigned char order;\n\tunsigned char flags;\n\tunsigned char cu_type[4];\n\tunsigned char suborder;\n\tunsigned char reserved[59];\n};\n\nstruct dasd_queue {\n\tspinlock_t lock;\n};\n\nstruct dasd_rssd_lcq {\n\t__u16 data_length;\n\t__u16 pool_count;\n\tstruct {\n\t\t__u8 pool_info_valid: 1;\n\t\t__u8 pool_id_volume: 1;\n\t\t__u8 pool_id_cec: 1;\n\t\t__u8 unused0: 5;\n\t\t__u8 unused1;\n\t} header_flags;\n\tchar sfi_type[6];\n\tchar sfi_model[3];\n\t__u8 sfi_seq_num[10];\n\t__u8 reserved[7];\n\tstruct dasd_ext_pool_sum ext_pool_sum[448];\n};\n\nstruct dasd_rssd_messages {\n\t__u16 length;\n\t__u8 format;\n\t__u8 code;\n\t__u32 message_id;\n\t__u8 flags;\n\tchar messages[4087];\n};\n\nstruct dasd_rssd_perf_stats_t {\n\tunsigned char invalid: 1;\n\tunsigned char format: 3;\n\tunsigned char data_format: 4;\n\tunsigned char unit_address;\n\tshort unsigned int device_status;\n\tunsigned int nr_read_normal;\n\tunsigned int nr_read_normal_hits;\n\tunsigned int nr_write_normal;\n\tunsigned int nr_write_fast_normal_hits;\n\tunsigned int nr_read_seq;\n\tunsigned int nr_read_seq_hits;\n\tunsigned int nr_write_seq;\n\tunsigned int nr_write_fast_seq_hits;\n\tunsigned int nr_read_cache;\n\tunsigned int nr_read_cache_hits;\n\tunsigned int nr_write_cache;\n\tunsigned int nr_write_fast_cache_hits;\n\tunsigned int nr_inhibit_cache;\n\tunsigned int nr_bybass_cache;\n\tunsigned int nr_seq_dasd_to_cache;\n\tunsigned int nr_dasd_to_cache;\n\tunsigned int nr_cache_to_dasd;\n\tunsigned int nr_delayed_fast_write;\n\tunsigned int nr_normal_fast_write;\n\tunsigned int nr_seq_fast_write;\n\tunsigned int nr_cache_miss;\n\tunsigned char status2;\n\tunsigned int nr_quick_write_promotes;\n\tunsigned char reserved;\n\tshort unsigned int ssid;\n\tunsigned char reseved2[96];\n} __attribute__((packed));\n\nstruct dasd_sneq {\n\tstruct {\n\t\t__u8 identifier: 2;\n\t\t__u8 reserved: 6;\n\t} flags;\n\t__u8 res1;\n\t__u16 format;\n\t__u8 res2[4];\n\t__u8 sua_flags;\n\t__u8 base_unit_addr;\n\t__u8 res3[22];\n};\n\nstruct dasd_snid_data {\n\tstruct {\n\t\t__u8 group: 2;\n\t\t__u8 reserve: 2;\n\t\t__u8 mode: 1;\n\t\t__u8 res: 3;\n\t} path_state;\n\t__u8 pgid[11];\n};\n\nstruct dasd_snid_ioctl_data {\n\tstruct dasd_snid_data data;\n\t__u8 path_mask;\n};\n\nstruct dasd_symmio_parms {\n\tunsigned char reserved[8];\n\tlong long unsigned int psf_data;\n\tlong long unsigned int rssd_result;\n\tint psf_data_len;\n\tint rssd_result_len;\n};\n\nstruct dasd_unit_address_configuration {\n\tstruct {\n\t\tchar ua_type;\n\t\tchar base_ua;\n\t} unit[256];\n};\n\nstruct dasd_vollabel {\n\tchar *type;\n\tint idx;\n};\n\nstruct data_reloc_warn {\n\tstruct btrfs_path path;\n\tstruct btrfs_fs_info *fs_info;\n\tu64 extent_item_size;\n\tu64 logical;\n\tint mirror_num;\n};\n\nstruct llc_sap;\n\nstruct packet_type;\n\nstruct datalink_proto {\n\tunsigned char type[8];\n\tstruct llc_sap *sap;\n\tshort unsigned int header_length;\n\tint (*rcvfunc)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tint (*request)(struct datalink_proto *, struct sk_buff *, const unsigned char *);\n\tstruct list_head node;\n};\n\nstruct dax_operations;\n\nstruct dax_holder_operations;\n\nstruct dax_device {\n\tstruct inode inode;\n\tstruct cdev cdev;\n\tvoid *private;\n\tlong unsigned int flags;\n\tconst struct dax_operations *ops;\n\tvoid *holder_data;\n\tconst struct dax_holder_operations *holder_ops;\n};\n\nstruct dev_dax;\n\nstruct dax_device_driver {\n\tstruct device_driver drv;\n\tstruct list_head ids;\n\tenum dax_driver_type type;\n\tint (*probe)(struct dev_dax *);\n\tvoid (*remove)(struct dev_dax *);\n};\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct dax_id {\n\tstruct list_head list;\n\tchar dev_name[30];\n};\n\nstruct dax_mapping {\n\tstruct device dev;\n\tint range_id;\n\tint id;\n};\n\nstruct dax_operations {\n\tlong int (*direct_access)(struct dax_device *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\tint (*zero_page_range)(struct dax_device *, long unsigned int, size_t);\n\tsize_t (*recovery_write)(struct dax_device *, long unsigned int, void *, size_t, struct iov_iter *);\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct dax_region {\n\tint id;\n\tint target_node;\n\tstruct kref kref;\n\tstruct device *dev;\n\tunsigned int align;\n\tstruct ida ida;\n\tstruct resource res;\n\tstruct device *seed;\n\tstruct device *youngest;\n};\n\nstruct dbfs_d204_hdr {\n\tu64 len;\n\tu16 version;\n\tu8 sc;\n\tchar reserved[53];\n};\n\nstruct dbfs_d204 {\n\tstruct dbfs_d204_hdr hdr;\n\tchar buf[0];\n};\n\nunion tod_clock {\n\t__int128 unsigned val;\n\tstruct {\n\t\t__int128 unsigned ei: 8;\n\t\t__int128 unsigned tod: 64;\n\t\tint: 24;\n\t\tshort: 16;\n\t\t__int128 unsigned pf: 16;\n\t};\n\tstruct {\n\t\t__int128 unsigned eitod: 72;\n\t};\n\tstruct {\n\t\t__int128 unsigned us: 60;\n\t\t__int128 unsigned sus: 12;\n\t};\n};\n\nstruct dbfs_d2fc_hdr {\n\tu64 len;\n\tu16 version;\n\tunion tod_clock tod_ext;\n\tu64 count;\n\tchar reserved[30];\n} __attribute__((packed));\n\nstruct dbfs_d2fc {\n\tstruct dbfs_d2fc_hdr hdr;\n\tchar buf[0];\n};\n\nstruct qrange {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct dcss_segment {\n\tstruct list_head list;\n\tchar dcss_name[8];\n\tchar res_name[16];\n\tlong unsigned int start_addr;\n\tlong unsigned int end;\n\trefcount_t ref_count;\n\tint do_nonshared;\n\tunsigned int vm_segtype;\n\tstruct qrange range[6];\n\tint segcnt;\n\tstruct resource *res;\n};\n\nstruct dcw {\n\tu32 cmd: 8;\n\tu32 flags: 8;\n\tchar: 8;\n\tu32 cd_count: 8;\n\tu32 count;\n\tu8 cd[0];\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct ddebug_class_map {\n\tstruct list_head link;\n\tstruct module *mod;\n\tconst char *mod_name;\n\tconst char **class_names;\n\tconst int length;\n\tconst int base;\n\tenum class_map_type map_type;\n};\n\nstruct ddebug_class_param {\n\tunion {\n\t\tlong unsigned int *bits;\n\t\tunsigned int *lvl;\n\t};\n\tchar flags[8];\n\tconst struct ddebug_class_map *map;\n};\n\nstruct ddebug_table;\n\nstruct ddebug_iter {\n\tstruct ddebug_table *table;\n\tint idx;\n};\n\nstruct ddebug_query {\n\tconst char *filename;\n\tconst char *module;\n\tconst char *function;\n\tconst char *format;\n\tconst char *class_string;\n\tunsigned int first_lineno;\n\tunsigned int last_lineno;\n};\n\nstruct ddebug_table {\n\tstruct list_head link;\n\tstruct list_head maps;\n\tconst char *mod_name;\n\tunsigned int num_ddebugs;\n\tstruct _ddebug *ddebugs;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct debug_view;\n\nstruct debug_info {\n\tstruct debug_info *next;\n\tstruct debug_info *prev;\n\trefcount_t ref_count;\n\traw_spinlock_t lock;\n\tint level;\n\tint nr_areas;\n\tint pages_per_area;\n\tint buf_size;\n\tint entry_size;\n\tdebug_entry_t ***areas;\n\tint active_area;\n\tint *active_pages;\n\tint *active_entries;\n\tstruct dentry *debugfs_root_entry;\n\tstruct dentry *debugfs_entries[10];\n\tstruct debug_view *views[10];\n\tchar name[64];\n\tumode_t mode;\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\ntypedef int debug_prolog_proc_t(debug_info_t *, struct debug_view *, char *, size_t);\n\ntypedef int debug_header_proc_t(debug_info_t *, struct debug_view *, int, debug_entry_t *, char *, size_t);\n\ntypedef int debug_format_proc_t(debug_info_t *, struct debug_view *, char *, size_t, const char *);\n\ntypedef int debug_input_proc_t(debug_info_t *, struct debug_view *, struct file *, const char *, size_t, loff_t *);\n\nstruct debug_view {\n\tchar name[64];\n\tdebug_prolog_proc_t *prolog_proc;\n\tdebug_header_proc_t *header_proc;\n\tdebug_format_proc_t *format_proc;\n\tdebug_input_proc_t *input_proc;\n\tvoid *private_data;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct deferred_split {\n\tspinlock_t split_queue_lock;\n\tstruct list_head split_queue;\n\tlong unsigned int split_queue_len;\n};\n\nstruct internal_state;\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\nstruct deflate_ctx {\n\tstruct z_stream_s cctx;\n\tstruct z_stream_s dctx;\n};\n\nstruct deflate_params {\n\ts32 winbits;\n};\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct static_tree_desc_s;\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\nstruct tree_desc_s {\n\tct_data *dyn_tree;\n\tint max_code;\n\tstatic_tree_desc *stat_desc;\n};\n\nstruct deflate_state {\n\tz_streamp strm;\n\tint status;\n\tByte *pending_buf;\n\tulg pending_buf_size;\n\tByte *pending_out;\n\tint pending;\n\tint noheader;\n\tByte data_type;\n\tByte method;\n\tint last_flush;\n\tuInt w_size;\n\tuInt w_bits;\n\tuInt w_mask;\n\tByte *window;\n\tulg window_size;\n\tPos *prev;\n\tPos *head;\n\tuInt ins_h;\n\tuInt hash_size;\n\tuInt hash_bits;\n\tuInt hash_mask;\n\tuInt hash_shift;\n\tlong int block_start;\n\tuInt match_length;\n\tIPos prev_match;\n\tint match_available;\n\tuInt strstart;\n\tuInt match_start;\n\tuInt lookahead;\n\tuInt prev_length;\n\tuInt max_chain_length;\n\tuInt max_lazy_match;\n\tint level;\n\tint strategy;\n\tuInt good_match;\n\tint nice_match;\n\tstruct ct_data_s dyn_ltree[573];\n\tstruct ct_data_s dyn_dtree[61];\n\tstruct ct_data_s bl_tree[39];\n\tstruct tree_desc_s l_desc;\n\tstruct tree_desc_s d_desc;\n\tstruct tree_desc_s bl_desc;\n\tush bl_count[16];\n\tint heap[573];\n\tint heap_len;\n\tint heap_max;\n\tuch depth[573];\n\tuch *l_buf;\n\tuInt lit_bufsize;\n\tuInt last_lit;\n\tush *d_buf;\n\tulg opt_len;\n\tulg static_len;\n\tulg compressed_len;\n\tuInt matches;\n\tint last_eob_len;\n\tush bi_buf;\n\tint bi_valid;\n};\n\nstruct dfltcc_param_v0 {\n\tuint16_t pbvn;\n\tuint8_t mvn;\n\tuint8_t ribm;\n\tunsigned int reserved32: 31;\n\tunsigned int cf: 1;\n\tuint8_t reserved64[8];\n\tunsigned int nt: 1;\n\tunsigned int reserved129: 1;\n\tunsigned int cvt: 1;\n\tunsigned int reserved131: 1;\n\tunsigned int htt: 1;\n\tunsigned int bcf: 1;\n\tunsigned int bcc: 1;\n\tunsigned int bhf: 1;\n\tunsigned int reserved136: 1;\n\tunsigned int reserved137: 1;\n\tunsigned int dhtgc: 1;\n\tunsigned int reserved139: 5;\n\tunsigned int reserved144: 5;\n\tunsigned int sbb: 3;\n\tuint8_t oesc;\n\tunsigned int reserved160: 12;\n\tunsigned int ifs: 4;\n\tuint16_t ifl;\n\tuint8_t reserved192[8];\n\tuint8_t reserved256[8];\n\tuint8_t reserved320[4];\n\tuint16_t hl;\n\tunsigned int reserved368: 1;\n\tuint16_t ho: 15;\n\tuint32_t cv;\n\tunsigned int eobs: 15;\n\tunsigned int reserved431: 1;\n\tuint8_t eobl: 4;\n\tunsigned int reserved436: 12;\n\tunsigned int reserved448: 4;\n\tuint16_t cdhtl: 12;\n\tuint8_t reserved464[6];\n\tuint8_t cdht[288];\n\tuint8_t reserved[32];\n\tuint8_t csb[1152];\n};\n\nstruct dfltcc_qaf_param {\n\tchar fns[16];\n\tchar reserved1[8];\n\tchar fmts[2];\n\tchar reserved2[6];\n};\n\nstruct dfltcc_state {\n\tstruct dfltcc_param_v0 param;\n\tstruct dfltcc_qaf_param af;\n\tchar msg[64];\n};\n\nstruct dfltcc_deflate_state {\n\tstruct dfltcc_state common;\n\tuLong level_mask;\n\tuLong block_size;\n\tuLong block_threshold;\n\tuLong dht_threshold;\n};\n\nstruct deflate_workspace {\n\tdeflate_state deflate_memory;\n\tstruct dfltcc_deflate_state dfltcc_memory;\n\tByte *window_memory;\n\tPos *prev_memory;\n\tPos *head_memory;\n\tchar *overlay_memory;\n};\n\ntypedef struct deflate_workspace deflate_workspace;\n\nstruct defrag_target_range {\n\tstruct list_head list;\n\tu64 start;\n\tu64 len;\n};\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct demotion_nodes {\n\tnodemask_t preferred;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 len;\n\t\t\tu32 hash;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n};\n\nunion shortname_store {\n\tunsigned char string[40];\n\tlong unsigned int words[5];\n};\n\nstruct lockref {\n\tunion {\n\t\t__u64 lock_count;\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_bucket {\n\tstruct rb_root tree;\n\tspinlock_t lock;\n};\n\nstruct dentry_info_args {\n\tint parent_ino;\n\tint dname_len;\n\tint ino;\n\tint inode_len;\n\tchar *dname;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct detected_devices_node {\n\tstruct list_head list;\n\tdev_t dev;\n};\n\nstruct dev_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head exceptions;\n\tenum devcg_behavior behavior;\n};\n\nstruct dev_pagemap;\n\nstruct dev_dax_range;\n\nstruct dev_dax {\n\tstruct dax_region *region;\n\tstruct dax_device *dax_dev;\n\tunsigned int align;\n\tint target_node;\n\tbool dyn_id;\n\tint id;\n\tstruct ida ida;\n\tstruct device dev;\n\tstruct dev_pagemap *pgmap;\n\tbool memmap_on_memory;\n\tint nr_range;\n\tstruct dev_dax_range *ranges;\n};\n\nstruct dev_dax_data {\n\tstruct dax_region *dax_region;\n\tstruct dev_pagemap *pgmap;\n\tresource_size_t size;\n\tint id;\n\tbool memmap_on_memory;\n};\n\nstruct dev_dax_range {\n\tlong unsigned int pgoff;\n\tstruct range range;\n\tstruct dax_mapping *mapping;\n};\n\nstruct dev_exception_item {\n\tu32 major;\n\tu32 minor;\n\tshort int type;\n\tshort int access;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct iommu_device;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n\tu32 max_pasids;\n\tu32 attach_deferred: 1;\n\tu32 pci_32bit_workaround: 1;\n\tu32 require_direct: 1;\n\tu32 shadow_on_flush: 1;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n};\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n};\n\nstruct devlink_dev_stats {\n\tu32 reload_stats[6];\n\tu32 remote_reload_stats[6];\n};\n\nstruct devlink_dpipe_headers;\n\nstruct devlink_ops;\n\nstruct devlink_rel;\n\nstruct devlink {\n\tu32 index;\n\tstruct xarray ports;\n\tstruct list_head rate_list;\n\tstruct list_head sb_list;\n\tstruct list_head dpipe_table_list;\n\tstruct list_head resource_list;\n\tstruct xarray params;\n\tstruct list_head region_list;\n\tstruct list_head reporter_list;\n\tstruct devlink_dpipe_headers *dpipe_headers;\n\tstruct list_head trap_list;\n\tstruct list_head trap_group_list;\n\tstruct list_head trap_policer_list;\n\tstruct list_head linecard_list;\n\tconst struct devlink_ops *ops;\n\tstruct xarray snapshot_ids;\n\tstruct devlink_dev_stats stats;\n\tstruct device *dev;\n\tpossible_net_t _net;\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tu8 reload_failed: 1;\n\trefcount_t refcount;\n\tstruct rcu_work rwork;\n\tstruct devlink_rel *rel;\n\tstruct xarray nested_rels;\n\tchar priv[0];\n};\n\nstruct devlink_dpipe_header;\n\nstruct devlink_dpipe_action {\n\tenum devlink_dpipe_action_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct genl_info;\n\nstruct devlink_dpipe_dump_ctx {\n\tstruct genl_info *info;\n\tenum devlink_command cmd;\n\tstruct sk_buff *skb;\n\tstruct nlattr *nest;\n\tvoid *hdr;\n};\n\nstruct devlink_dpipe_value;\n\nstruct devlink_dpipe_entry {\n\tu64 index;\n\tstruct devlink_dpipe_value *match_values;\n\tunsigned int match_values_count;\n\tstruct devlink_dpipe_value *action_values;\n\tunsigned int action_values_count;\n\tu64 counter;\n\tbool counter_valid;\n};\n\nstruct devlink_dpipe_field {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int bitwidth;\n\tenum devlink_dpipe_field_mapping_type mapping_type;\n};\n\nstruct devlink_dpipe_header {\n\tconst char *name;\n\tunsigned int id;\n\tstruct devlink_dpipe_field *fields;\n\tunsigned int fields_count;\n\tbool global;\n};\n\nstruct devlink_dpipe_headers {\n\tstruct devlink_dpipe_header **headers;\n\tunsigned int headers_count;\n};\n\nstruct devlink_dpipe_match {\n\tenum devlink_dpipe_match_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct devlink_dpipe_table_ops;\n\nstruct devlink_dpipe_table {\n\tvoid *priv;\n\tstruct list_head list;\n\tconst char *name;\n\tbool counters_enabled;\n\tbool counter_control_extern;\n\tbool resource_valid;\n\tu64 resource_id;\n\tu64 resource_units;\n\tconst struct devlink_dpipe_table_ops *table_ops;\n\tstruct callback_head rcu;\n};\n\nstruct devlink_dpipe_table_ops {\n\tint (*actions_dump)(void *, struct sk_buff *);\n\tint (*matches_dump)(void *, struct sk_buff *);\n\tint (*entries_dump)(void *, bool, struct devlink_dpipe_dump_ctx *);\n\tint (*counters_set_update)(void *, bool);\n\tu64 (*size_get)(void *);\n};\n\nstruct devlink_dpipe_value {\n\tunion {\n\t\tstruct devlink_dpipe_action *action;\n\t\tstruct devlink_dpipe_match *match;\n\t};\n\tunsigned int mapping_value;\n\tbool mapping_valid;\n\tunsigned int value_size;\n\tvoid *value;\n\tvoid *mask;\n};\n\nstruct devlink_flash_component_lookup_ctx {\n\tconst char *lookup_name;\n\tbool lookup_name_found;\n};\n\nstruct devlink_flash_notify {\n\tconst char *status_msg;\n\tconst char *component;\n\tlong unsigned int done;\n\tlong unsigned int total;\n\tlong unsigned int timeout;\n};\n\nstruct firmware;\n\nstruct devlink_flash_update_params {\n\tconst struct firmware *fw;\n\tconst char *component;\n\tu32 overwrite_mask;\n};\n\nstruct devlink_fmsg {\n\tstruct list_head item_list;\n\tint err;\n\tbool putting_binary;\n};\n\nstruct devlink_fmsg_item {\n\tstruct list_head list;\n\tint attrtype;\n\tu8 nla_type;\n\tu16 len;\n\tint value[0];\n};\n\nstruct devlink_health_reporter_ops;\n\nstruct devlink_port;\n\nstruct devlink_health_reporter {\n\tstruct list_head list;\n\tvoid *priv;\n\tconst struct devlink_health_reporter_ops *ops;\n\tstruct devlink *devlink;\n\tstruct devlink_port *devlink_port;\n\tstruct devlink_fmsg *dump_fmsg;\n\tu64 graceful_period;\n\tu64 burst_period;\n\tbool auto_recover;\n\tbool auto_dump;\n\tu8 health_state;\n\tu64 dump_ts;\n\tu64 dump_real_ts;\n\tu64 error_count;\n\tu64 recovery_count;\n\tu64 last_recovery_ts;\n};\n\nstruct devlink_health_reporter_ops {\n\tchar *name;\n\tint (*recover)(struct devlink_health_reporter *, void *, struct netlink_ext_ack *);\n\tint (*dump)(struct devlink_health_reporter *, struct devlink_fmsg *, void *, struct netlink_ext_ack *);\n\tint (*diagnose)(struct devlink_health_reporter *, struct devlink_fmsg *, struct netlink_ext_ack *);\n\tint (*test)(struct devlink_health_reporter *, struct netlink_ext_ack *);\n\tu64 default_graceful_period;\n\tu64 default_burst_period;\n};\n\nstruct devlink_info_req {\n\tstruct sk_buff *msg;\n\tvoid (*version_cb)(const char *, enum devlink_info_version_type, void *);\n\tvoid *version_cb_priv;\n};\n\nstruct devlink_linecard_ops;\n\nstruct devlink_linecard_type;\n\nstruct devlink_linecard {\n\tstruct list_head list;\n\tstruct devlink *devlink;\n\tunsigned int index;\n\tconst struct devlink_linecard_ops *ops;\n\tvoid *priv;\n\tenum devlink_linecard_state state;\n\tstruct mutex state_lock;\n\tconst char *type;\n\tstruct devlink_linecard_type *types;\n\tunsigned int types_count;\n\tu32 rel_index;\n};\n\nstruct devlink_linecard_ops {\n\tint (*provision)(struct devlink_linecard *, void *, const char *, const void *, struct netlink_ext_ack *);\n\tint (*unprovision)(struct devlink_linecard *, void *, struct netlink_ext_ack *);\n\tbool (*same_provision)(struct devlink_linecard *, void *, const char *, const void *);\n\tunsigned int (*types_count)(struct devlink_linecard *, void *);\n\tvoid (*types_get)(struct devlink_linecard *, void *, unsigned int, const char **, const void **);\n};\n\nstruct devlink_linecard_type {\n\tconst char *type;\n\tconst void *priv;\n};\n\nstruct devlink_nl_dump_state {\n\tlong unsigned int instance;\n\tint idx;\n\tunion {\n\t\tstruct {\n\t\t\tu64 start_offset;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dump_ts;\n\t\t};\n\t};\n};\n\nstruct devlink_obj_desc;\n\nstruct devlink_nl_sock_priv {\n\tstruct devlink_obj_desc *flt;\n\tspinlock_t flt_lock;\n};\n\nstruct devlink_obj_desc {\n\tstruct callback_head rcu;\n\tconst char *bus_name;\n\tconst char *dev_name;\n\tunsigned int port_index;\n\tbool port_index_valid;\n\tlong int data[0];\n};\n\nstruct devlink_sb_pool_info;\n\nstruct devlink_trap;\n\nstruct devlink_trap_group;\n\nstruct devlink_trap_policer;\n\nstruct devlink_port_new_attrs;\n\nstruct devlink_rate;\n\nstruct devlink_ops {\n\tu32 supported_flash_update_params;\n\tlong unsigned int reload_actions;\n\tlong unsigned int reload_limits;\n\tint (*reload_down)(struct devlink *, bool, enum devlink_reload_action, enum devlink_reload_limit, struct netlink_ext_ack *);\n\tint (*reload_up)(struct devlink *, enum devlink_reload_action, enum devlink_reload_limit, u32 *, struct netlink_ext_ack *);\n\tint (*sb_pool_get)(struct devlink *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*sb_pool_set)(struct devlink *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*sb_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *);\n\tint (*sb_port_pool_set)(struct devlink_port *, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_tc_pool_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*sb_tc_pool_bind_set)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_occ_snapshot)(struct devlink *, unsigned int);\n\tint (*sb_occ_max_clear)(struct devlink *, unsigned int);\n\tint (*sb_occ_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *, u32 *);\n\tint (*sb_occ_tc_port_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*eswitch_mode_get)(struct devlink *, u16 *);\n\tint (*eswitch_mode_set)(struct devlink *, u16, struct netlink_ext_ack *);\n\tint (*eswitch_inline_mode_get)(struct devlink *, u8 *);\n\tint (*eswitch_inline_mode_set)(struct devlink *, u8, struct netlink_ext_ack *);\n\tint (*eswitch_encap_mode_get)(struct devlink *, enum devlink_eswitch_encap_mode *);\n\tint (*eswitch_encap_mode_set)(struct devlink *, enum devlink_eswitch_encap_mode, struct netlink_ext_ack *);\n\tint (*info_get)(struct devlink *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*flash_update)(struct devlink *, struct devlink_flash_update_params *, struct netlink_ext_ack *);\n\tint (*trap_init)(struct devlink *, const struct devlink_trap *, void *);\n\tvoid (*trap_fini)(struct devlink *, const struct devlink_trap *, void *);\n\tint (*trap_action_set)(struct devlink *, const struct devlink_trap *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_group_init)(struct devlink *, const struct devlink_trap_group *);\n\tint (*trap_group_set)(struct devlink *, const struct devlink_trap_group *, const struct devlink_trap_policer *, struct netlink_ext_ack *);\n\tint (*trap_group_action_set)(struct devlink *, const struct devlink_trap_group *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_drop_counter_get)(struct devlink *, const struct devlink_trap *, u64 *);\n\tint (*trap_policer_init)(struct devlink *, const struct devlink_trap_policer *);\n\tvoid (*trap_policer_fini)(struct devlink *, const struct devlink_trap_policer *);\n\tint (*trap_policer_set)(struct devlink *, const struct devlink_trap_policer *, u64, u64, struct netlink_ext_ack *);\n\tint (*trap_policer_counter_get)(struct devlink *, const struct devlink_trap_policer *, u64 *);\n\tint (*port_new)(struct devlink *, const struct devlink_port_new_attrs *, struct netlink_ext_ack *, struct devlink_port **);\n\tint (*rate_leaf_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_new)(struct devlink_rate *, void **, struct netlink_ext_ack *);\n\tint (*rate_node_del)(struct devlink_rate *, void *, struct netlink_ext_ack *);\n\tint (*rate_leaf_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tint (*rate_node_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tbool (*selftest_check)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n\tenum devlink_selftest_status (*selftest_run)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n};\n\nstruct devlink_param_gset_ctx;\n\nunion devlink_param_value;\n\nstruct devlink_param {\n\tu32 id;\n\tconst char *name;\n\tbool generic;\n\tenum devlink_param_type type;\n\tlong unsigned int supported_cmodes;\n\tint (*get)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*set)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*validate)(struct devlink *, u32, union devlink_param_value, struct netlink_ext_ack *);\n\tint (*get_default)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*reset_default)(struct devlink *, u32, enum devlink_param_cmode, struct netlink_ext_ack *);\n};\n\nunion devlink_param_value {\n\tu8 vu8;\n\tu16 vu16;\n\tu32 vu32;\n\tu64 vu64;\n\tchar vstr[32];\n\tbool vbool;\n};\n\nstruct devlink_param_gset_ctx {\n\tunion devlink_param_value val;\n\tenum devlink_param_cmode cmode;\n};\n\nstruct devlink_param_item {\n\tstruct list_head list;\n\tconst struct devlink_param *param;\n\tunion devlink_param_value driverinit_value;\n\tbool driverinit_value_valid;\n\tunion devlink_param_value driverinit_value_new;\n\tbool driverinit_value_new_valid;\n\tunion devlink_param_value driverinit_default;\n};\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_port_ops;\n\nstruct ib_device;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct devlink_port_new_attrs {\n\tenum devlink_port_flavour flavour;\n\tunsigned int port_index;\n\tu32 controller;\n\tu32 sfnum;\n\tu16 pfnum;\n\tu8 port_index_valid: 1;\n\tu8 controller_valid: 1;\n\tu8 sfnum_valid: 1;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_port_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n};\n\nstruct devlink_region_ops;\n\nstruct devlink_region {\n\tstruct devlink *devlink;\n\tstruct devlink_port *port;\n\tstruct list_head list;\n\tunion {\n\t\tconst struct devlink_region_ops *ops;\n\t\tconst struct devlink_port_region_ops *port_ops;\n\t};\n\tstruct mutex snapshot_lock;\n\tstruct list_head snapshot_list;\n\tu32 max_snapshots;\n\tu32 cur_snapshots;\n\tu64 size;\n};\n\nstruct devlink_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\ntypedef void devlink_rel_notify_cb_t(struct devlink *, u32);\n\ntypedef void devlink_rel_cleanup_cb_t(struct devlink *, u32, u32);\n\nstruct devlink_rel {\n\tu32 index;\n\trefcount_t refcount;\n\tu32 devlink_index;\n\tstruct {\n\t\tu32 devlink_index;\n\t\tu32 obj_index;\n\t\tdevlink_rel_notify_cb_t *notify_cb;\n\t\tdevlink_rel_cleanup_cb_t *cleanup_cb;\n\t\tstruct delayed_work notify_work;\n\t} nested_in;\n};\n\nstruct devlink_reload_combination {\n\tenum devlink_reload_action action;\n\tenum devlink_reload_limit limit;\n};\n\nstruct devlink_resource_size_params {\n\tu64 size_min;\n\tu64 size_max;\n\tu64 size_granularity;\n\tenum devlink_resource_unit unit;\n};\n\ntypedef u64 devlink_resource_occ_get_t(void *);\n\nstruct devlink_resource {\n\tconst char *name;\n\tu64 id;\n\tu64 size;\n\tu64 size_new;\n\tbool size_valid;\n\tstruct devlink_resource *parent;\n\tstruct devlink_resource_size_params size_params;\n\tstruct list_head list;\n\tstruct list_head resource_list;\n\tdevlink_resource_occ_get_t *occ_get;\n\tvoid *occ_get_priv;\n};\n\nstruct devlink_sb {\n\tstruct list_head list;\n\tunsigned int index;\n\tu32 size;\n\tu16 ingress_pools_count;\n\tu16 egress_pools_count;\n\tu16 ingress_tc_count;\n\tu16 egress_tc_count;\n};\n\nstruct devlink_sb_pool_info {\n\tenum devlink_sb_pool_type pool_type;\n\tu32 size;\n\tenum devlink_sb_threshold_type threshold_type;\n\tu32 cell_size;\n};\n\nstruct devlink_snapshot {\n\tstruct list_head list;\n\tstruct devlink_region *region;\n\tu8 *data;\n\tu32 id;\n};\n\nstruct devlink_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct devlink_trap {\n\tenum devlink_trap_type type;\n\tenum devlink_trap_action init_action;\n\tbool generic;\n\tu16 id;\n\tconst char *name;\n\tu16 init_group_id;\n\tu32 metadata_cap;\n};\n\nstruct devlink_trap_group {\n\tconst char *name;\n\tu16 id;\n\tbool generic;\n\tu32 init_policer_id;\n};\n\nstruct devlink_trap_policer_item;\n\nstruct devlink_trap_group_item {\n\tconst struct devlink_trap_group *group;\n\tstruct devlink_trap_policer_item *policer_item;\n\tstruct list_head list;\n\tstruct devlink_stats *stats;\n};\n\nstruct devlink_trap_item {\n\tconst struct devlink_trap *trap;\n\tstruct devlink_trap_group_item *group_item;\n\tstruct list_head list;\n\tenum devlink_trap_action action;\n\tstruct devlink_stats *stats;\n\tvoid *priv;\n};\n\nstruct flow_action_cookie;\n\nstruct devlink_trap_metadata {\n\tconst char *trap_name;\n\tconst char *trap_group_name;\n\tstruct net_device *input_dev;\n\tnetdevice_tracker dev_tracker;\n\tconst struct flow_action_cookie *fa_cookie;\n\tenum devlink_trap_type trap_type;\n};\n\nstruct devlink_trap_policer {\n\tu32 id;\n\tu64 init_rate;\n\tu64 init_burst;\n\tu64 max_rate;\n\tu64 min_rate;\n\tu64 max_burst;\n\tu64 min_burst;\n};\n\nstruct devlink_trap_policer_item {\n\tconst struct devlink_trap_policer *policer;\n\tu64 rate;\n\tu64 burst;\n\tstruct list_head list;\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nstruct diag204_cpu_info {\n\t__u16 cpu_addr;\n\tchar reserved1[2];\n\t__u8 ctidx;\n\t__u8 cflag;\n\t__u16 weight;\n\t__u64 acc_time;\n\t__u64 lp_time;\n};\n\nstruct diag204_info_blk_hdr {\n\t__u8 npar;\n\t__u8 flags;\n\t__u16 tslice;\n\t__u16 phys_cpus;\n\t__u16 this_part;\n\t__u64 curtod;\n};\n\nstruct diag204_part_hdr {\n\t__u8 pn;\n\t__u8 cpus;\n\tchar reserved[6];\n\tchar part_name[8];\n};\n\nstruct diag204_phys_cpu {\n\t__u16 cpu_addr;\n\tchar reserved1[2];\n\t__u8 ctidx;\n\tchar reserved2[3];\n\t__u64 mgm_time;\n\tchar reserved3[8];\n};\n\nstruct diag204_phys_hdr {\n\tchar reserved1[1];\n\t__u8 cpus;\n\tchar reserved2[6];\n\tchar mgm_name[8];\n};\n\nstruct diag204_x_cpu_info {\n\t__u16 cpu_addr;\n\tchar reserved1[2];\n\t__u8 ctidx;\n\t__u8 cflag;\n\t__u16 weight;\n\t__u64 acc_time;\n\t__u64 lp_time;\n\t__u16 min_weight;\n\t__u16 cur_weight;\n\t__u16 max_weight;\n\tchar reseved2[2];\n\t__u64 online_time;\n\t__u64 wait_time;\n\t__u32 pma_weight;\n\t__u32 polar_weight;\n\t__u32 cpu_type_cap;\n\t__u32 group_cpu_type_cap;\n\tchar reserved3[32];\n};\n\nstruct diag204_x_info_blk_hdr {\n\t__u8 npar;\n\t__u8 flags;\n\t__u16 tslice;\n\t__u16 phys_cpus;\n\t__u16 this_part;\n\t__u64 curtod1;\n\t__u64 curtod2;\n\tchar reserved[40];\n};\n\nstruct diag204_x_part_hdr {\n\t__u8 pn;\n\t__u8 cpus;\n\t__u8 rcpus;\n\t__u8 pflag;\n\t__u32 mlu;\n\tchar part_name[8];\n\tchar lpc_name[8];\n\tchar os_name[8];\n\t__u64 online_cs;\n\t__u64 online_es;\n\t__u8 upid;\n\t__u8 reserved: 3;\n\t__u8 mtid: 5;\n\tchar reserved1[2];\n\t__u32 group_mlu;\n\tchar group_name[8];\n\tchar hardware_group_name[8];\n\tchar reserved2[24];\n};\n\nstruct diag204_x_part_block {\n\tstruct diag204_x_part_hdr hdr;\n\tstruct diag204_x_cpu_info cpus[0];\n};\n\nstruct diag204_x_phys_hdr {\n\tchar reserved1[1];\n\t__u8 cpus;\n\tchar reserved2[6];\n\tchar mgm_name[8];\n\tchar reserved3[80];\n};\n\nstruct diag204_x_phys_cpu {\n\t__u16 cpu_addr;\n\tchar reserved1[2];\n\t__u8 ctidx;\n\tchar reserved2[1];\n\t__u16 weight;\n\t__u64 mgm_time;\n\tchar reserved3[80];\n};\n\nstruct diag204_x_phys_block {\n\tstruct diag204_x_phys_hdr hdr;\n\tstruct diag204_x_phys_cpu cpus[0];\n};\n\nstruct diag210 {\n\tu16 vrdcdvno;\n\tu16 vrdclen;\n\tu8 vrdcvcla;\n\tu8 vrdcvtyp;\n\tu8 vrdcvsta;\n\tu8 vrdcvfla;\n\tu8 vrdcrccl;\n\tu8 vrdccrty;\n\tu8 vrdccrmd;\n\tu8 vrdccrft;\n};\n\nstruct diag26c_mac_req {\n\tu32 resp_buf_len;\n\tu32 resp_version;\n\tu16 op_code;\n\tu16 devno;\n\tu8 res[4];\n};\n\nstruct diag26c_mac_resp {\n\tu32 version;\n\tu8 mac[6];\n\tu8 res[2];\n\tlong: 0;\n};\n\nstruct diag26c_vnic_req {\n\tu32 resp_buf_len;\n\tu32 resp_version;\n\tu16 req_format;\n\tu16 vlan_id;\n\tu64 sys_name;\n\tu8 res[2];\n\tu16 devno;\n} __attribute__((packed));\n\nstruct diag26c_vnic_resp {\n\tu32 version;\n\tu32 entry_cnt;\n\tu32 next_entry;\n\tu64 owner;\n\tu16 devno;\n\tu8 status;\n\tu8 type;\n\tu64 lan_owner;\n\tu64 lan_name;\n\tu64 port_name;\n\tu8 port_type;\n\tu8 ext_status: 6;\n\tu8 protocol: 2;\n\tu16 base_devno;\n\tu32 port_num;\n\tu32 ifindex;\n\tu32 maxinfo;\n\tu32 dev_count;\n\tu8 dev_info1[28];\n\tu8 dev_info2[28];\n\tu8 dev_info3[28];\n} __attribute__((packed));\n\nstruct diag2fc_data {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 used_cpu;\n\t__u64 el_time;\n\t__u64 mem_min_kb;\n\t__u64 mem_max_kb;\n\t__u64 mem_share_kb;\n\t__u64 mem_used_kb;\n\t__u32 pcpus;\n\t__u32 lcpus;\n\t__u32 vcpus;\n\t__u32 ocpus;\n\t__u32 cpu_max;\n\t__u32 cpu_shares;\n\t__u32 cpu_use_samp;\n\t__u32 cpu_delay_samp;\n\t__u32 page_wait_samp;\n\t__u32 idle_samp;\n\t__u32 other_samp;\n\t__u32 total_samp;\n\tchar guest_name[8];\n};\n\nstruct diag2fc_parm_list {\n\tchar userid[8];\n\tchar aci_grp[8];\n\t__u64 addr;\n\t__u32 size;\n\t__u32 fmt;\n};\n\nstruct diag310_memtop {\n\t__u64 address;\n\t__u64 nesting_lvl;\n};\n\nunion diag310_req_size {\n\tu64 size;\n\tstruct {\n\t\tu64 page_count: 32;\n\t};\n};\n\nunion diag310_req_subcode {\n\tu64 subcode;\n\tstruct {\n\t\tlong: 48;\n\t\tu64 st: 8;\n\t\tu64 sc: 8;\n\t};\n};\n\nunion diag310_response {\n\tu64 response;\n\tstruct {\n\t\tu64 result: 32;\n\t\tshort: 16;\n\t\tu64 rc: 16;\n\t};\n};\n\nunion diag318_info {\n\tlong unsigned int val;\n\tstruct {\n\t\tlong unsigned int cpnc: 8;\n\t\tlong unsigned int cpvc: 56;\n\t};\n};\n\nstruct diag324_pib {\n\t__u64 address;\n\t__u64 sequence;\n};\n\nunion diag324_request {\n\tu64 request;\n\tstruct {\n\t\tint: 32;\n\t\tu64 allocated: 16;\n\t\tshort: 12;\n\t\tu64 sc: 4;\n\t} sc2;\n};\n\nunion diag324_response {\n\tu64 response;\n\tstruct {\n\t\tu64 installed: 32;\n\t\tshort: 16;\n\t\tu64 rc: 16;\n\t} sc0;\n\tstruct {\n\t\tu64 format: 16;\n\t\tint: 16;\n\t\tu64 pib_len: 16;\n\t\tu64 rc: 16;\n\t} sc1;\n\tstruct {\n\t\tlong: 48;\n\t\tu64 rc: 16;\n\t} sc2;\n};\n\nstruct diag8c {\n\tu8 flags;\n\tu8 num_partitions;\n\tu16 width;\n\tu16 height;\n\tu8 data[0];\n\tlong: 0;\n};\n\nstruct diag_desc {\n\tint code;\n\tchar *name;\n};\n\nstruct diag_ops {\n\tint (*diag210)(struct diag210 *);\n\tint (*diag26c)(long unsigned int, long unsigned int, enum diag26c_sc);\n\tint (*diag14)(long unsigned int, long unsigned int, long unsigned int);\n\tint (*diag8c)(struct diag8c *, struct ccw_dev_id *, size_t);\n\tvoid (*diag0c)(long unsigned int);\n\tvoid (*diag308_reset)(void);\n};\n\nstruct diag_stat {\n\tunsigned int counter[26];\n};\n\nstruct dibs_client_ops;\n\nstruct dibs_client {\n\tconst char *name;\n\tconst struct dibs_client_ops *ops;\n\tu8 id;\n};\n\nstruct dibs_dev;\n\nstruct dibs_event;\n\nstruct dibs_client_ops {\n\tvoid (*add_dev)(struct dibs_dev *);\n\tvoid (*del_dev)(struct dibs_dev *);\n\tvoid (*handle_irq)(struct dibs_dev *, unsigned int, u16);\n\tvoid (*handle_event)(struct dibs_dev *, const struct dibs_event *);\n};\n\nstruct dibs_dev_ops;\n\nstruct dibs_dev {\n\tstruct list_head list;\n\tstruct device dev;\n\tconst struct dibs_dev_ops *ops;\n\tuuid_t gid;\n\tvoid *drv_priv;\n\tvoid *priv[8];\n\tspinlock_t lock;\n\tu8 *dmb_clientid_arr;\n\tstruct dibs_client *subs[8];\n};\n\nstruct dibs_dev_list {\n\tstruct list_head list;\n\tstruct mutex mutex;\n};\n\nstruct dibs_dmb;\n\nstruct dibs_dev_ops {\n\tu16 (*get_fabric_id)(struct dibs_dev *);\n\tint (*query_remote_gid)(struct dibs_dev *, const uuid_t *, u32, u32);\n\tint (*max_dmbs)(void);\n\tint (*register_dmb)(struct dibs_dev *, struct dibs_dmb *, struct dibs_client *);\n\tint (*unregister_dmb)(struct dibs_dev *, struct dibs_dmb *);\n\tint (*move_data)(struct dibs_dev *, u64, unsigned int, bool, unsigned int, void *, unsigned int);\n\tint (*add_vlan_id)(struct dibs_dev *, u64);\n\tint (*del_vlan_id)(struct dibs_dev *, u64);\n\tint (*signal_event)(struct dibs_dev *, const uuid_t *, u32, u32, u64);\n\tint (*support_mmapped_rdmb)(struct dibs_dev *);\n\tint (*attach_dmb)(struct dibs_dev *, struct dibs_dmb *);\n\tint (*detach_dmb)(struct dibs_dev *, u64);\n};\n\nstruct dibs_dmb {\n\tu64 dmb_tok;\n\tuuid_t rgid;\n\tvoid *cpu_addr;\n\tu32 dmb_len;\n\tu32 idx;\n\tu32 vlan_valid;\n\tu32 vlan_id;\n\tdma_addr_t dma_addr;\n};\n\nstruct dibs_event {\n\tu32 type;\n\tu32 subtype;\n\tuuid_t gid;\n\tu64 buffer_tok;\n\tu64 time;\n\tu64 data;\n};\n\nstruct dibs_lo_dev {\n\tstruct dibs_dev *dibs;\n\tatomic_t dmb_cnt;\n\trwlock_t dmb_ht_lock;\n\tlong unsigned int sba_idx_mask[79];\n\tstruct hlist_head dmb_ht[4096];\n\twait_queue_head_t ldev_release;\n};\n\nstruct dibs_lo_dmb_node {\n\tstruct hlist_node list;\n\tu64 token;\n\tu32 len;\n\tu32 sba_idx;\n\tvoid *cpu_addr;\n\tdma_addr_t dma_addr;\n\trefcount_t refcnt;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\nstruct dio {\n\tint flags;\n\tblk_opf_t opf;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tbool is_pinned;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n};\n\nstruct dioattr {\n\t__u32 d_mem;\n\t__u32 d_miniosz;\n\t__u32 d_maxiosz;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct dir_entry {\n\tu64 ino;\n\tu64 offset;\n\tunsigned int type;\n\tint name_len;\n};\n\nstruct dir_entry___2 {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n\tu64 cookie;\n\tbool initialized;\n};\n\nstruct wb_domain;\n\nstruct dirty_throttle_control {\n\tstruct wb_domain *dom;\n\tstruct dirty_throttle_control *gdtc;\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\nstruct dm_arg {\n\tunsigned int min;\n\tunsigned int max;\n\tchar *error;\n};\n\nstruct dm_arg_set {\n\tunsigned int argc;\n\tchar **argv;\n};\n\nstruct dm_blkdev_id {\n\tu8 *id;\n\tenum blk_unique_id type;\n};\n\nstruct dm_crypt_key {\n\tunsigned int key_size;\n\tchar key_desc[128];\n\tu8 data[256];\n};\n\nstruct mapped_device;\n\nstruct dm_crypto_profile {\n\tstruct blk_crypto_profile profile;\n\tstruct mapped_device *md;\n};\n\nstruct dm_dev {\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct dax_device *dax_dev;\n\tblk_mode_t mode;\n\tchar name[16];\n};\n\nstruct dm_dev_internal {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev *dm_dev;\n};\n\nstruct dm_ioctl {\n\t__u32 version[3];\n\t__u32 data_size;\n\t__u32 data_start;\n\t__u32 target_count;\n\t__s32 open_count;\n\t__u32 flags;\n\t__u32 event_nr;\n\t__u32 padding;\n\t__u64 dev;\n\tchar name[128];\n\tchar uuid[129];\n\tchar data[7];\n};\n\nstruct dm_target_spec;\n\nstruct dm_device {\n\tstruct dm_ioctl dmi;\n\tstruct dm_target_spec *table[256];\n\tchar *target_args_array[256];\n\tstruct list_head list;\n};\n\nstruct dm_file {\n\tvolatile unsigned int global_event_nr;\n};\n\nstruct dm_ima_device_table_metadata {\n\tchar *device_metadata;\n\tunsigned int device_metadata_len;\n\tunsigned int num_targets;\n\tchar *hash;\n\tunsigned int hash_len;\n};\n\nstruct dm_ima_measurements {\n\tstruct dm_ima_device_table_metadata active_table;\n\tstruct dm_ima_device_table_metadata inactive_table;\n\tunsigned int dm_version_str_len;\n};\n\nstruct dm_stats_aux {\n\tbool merged;\n\tlong long unsigned int duration_ns;\n};\n\nstruct dm_target;\n\nstruct dm_target_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tunsigned int target_bio_nr;\n\tstruct dm_io *io;\n\tstruct dm_target *ti;\n\tunsigned int *len_ptr;\n\tsector_t old_sector;\n\tstruct bio clone;\n};\n\nstruct dm_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tspinlock_t lock;\n\tlong unsigned int start_time;\n\tvoid *data;\n\tstruct dm_io *next;\n\tstruct dm_stats_aux stats_aux;\n\tblk_status_t status;\n\tbool requeue_flush_with_data;\n\tatomic_t io_count;\n\tstruct mapped_device *md;\n\tstruct bio *orig_bio;\n\tunsigned int sector_offset;\n\tunsigned int sectors;\n\tstruct dm_target_io tio;\n};\n\nstruct dm_io_client {\n\tmempool_t pool;\n\tstruct bio_set bios;\n};\n\nstruct page_list;\n\nstruct dm_io_memory {\n\tenum dm_io_mem_type type;\n\tunsigned int offset;\n\tunion {\n\t\tstruct page_list *pl;\n\t\tstruct bio *bio;\n\t\tvoid *vma;\n\t\tvoid *addr;\n\t} ptr;\n};\n\ntypedef void (*io_notify_fn)(long unsigned int, void *);\n\nstruct dm_io_notify {\n\tio_notify_fn fn;\n\tvoid *context;\n};\n\nstruct dm_io_region {\n\tstruct block_device *bdev;\n\tsector_t sector;\n\tsector_t count;\n};\n\nstruct dm_io_request {\n\tblk_opf_t bi_opf;\n\tstruct dm_io_memory mem;\n\tstruct dm_io_notify notify;\n\tstruct dm_io_client *client;\n};\n\nstruct dm_kcopyd_throttle;\n\nstruct dm_kcopyd_client {\n\tstruct page_list *pages;\n\tunsigned int nr_reserved_pages;\n\tunsigned int nr_free_pages;\n\tunsigned int sub_job_size;\n\tstruct dm_io_client *io_client;\n\twait_queue_head_t destroyq;\n\tmempool_t job_pool;\n\tstruct workqueue_struct *kcopyd_wq;\n\tstruct work_struct kcopyd_work;\n\tstruct dm_kcopyd_throttle *throttle;\n\tatomic_t nr_jobs;\n\tspinlock_t job_lock;\n\tstruct list_head callback_jobs;\n\tstruct list_head complete_jobs;\n\tstruct list_head io_jobs;\n\tstruct list_head pages_jobs;\n};\n\nstruct dm_kcopyd_throttle {\n\tunsigned int throttle;\n\tunsigned int num_io_jobs;\n\tunsigned int io_period;\n\tunsigned int total_period;\n\tunsigned int last_jiffies;\n};\n\nstruct dm_kobject_holder {\n\tstruct kobject kobj;\n\tstruct completion completion;\n};\n\nstruct dm_md_mempools {\n\tstruct bio_set bs;\n\tstruct bio_set io_bs;\n};\n\nstruct dm_name_list {\n\t__u64 dev;\n\t__u32 next;\n\tchar name[0];\n};\n\nstruct pr_keys;\n\nstruct pr_held_reservation;\n\nstruct dm_pr {\n\tu64 old_key;\n\tu64 new_key;\n\tu32 flags;\n\tbool abort;\n\tbool fail_early;\n\tint ret;\n\tenum pr_type type;\n\tstruct pr_keys *read_keys;\n\tstruct pr_held_reservation *rsv;\n};\n\nstruct dm_rq_target_io;\n\nstruct dm_rq_clone_bio_info {\n\tstruct bio *orig;\n\tstruct dm_rq_target_io *tio;\n\tstruct bio clone;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_worker;\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nunion map_info {\n\tvoid *ptr;\n};\n\nstruct dm_rq_target_io {\n\tstruct mapped_device *md;\n\tstruct dm_target *ti;\n\tstruct request *orig;\n\tstruct request *clone;\n\tstruct kthread_work work;\n\tblk_status_t error;\n\tunion map_info info;\n\tstruct dm_stats_aux stats_aux;\n\tlong unsigned int duration_jiffies;\n\tunsigned int n_sectors;\n\tunsigned int completed;\n};\n\nstruct dm_stat_percpu {\n\tlong long unsigned int sectors[2];\n\tlong long unsigned int ios[2];\n\tlong long unsigned int merges[2];\n\tlong long unsigned int ticks[2];\n\tlong long unsigned int io_ticks[2];\n\tlong long unsigned int io_ticks_total;\n\tlong long unsigned int time_in_queue;\n\tlong long unsigned int *histogram;\n};\n\nstruct dm_stat_shared {\n\tatomic_t in_flight[2];\n\tlong long unsigned int stamp;\n\tstruct dm_stat_percpu tmp;\n};\n\nstruct dm_stat {\n\tstruct list_head list_entry;\n\tint id;\n\tunsigned int stat_flags;\n\tsize_t n_entries;\n\tsector_t start;\n\tsector_t end;\n\tsector_t step;\n\tunsigned int n_histogram_entries;\n\tlong long unsigned int *histogram_boundaries;\n\tconst char *program_id;\n\tconst char *aux_data;\n\tstruct callback_head callback_head;\n\tsize_t shared_alloc_size;\n\tsize_t percpu_alloc_size;\n\tsize_t histogram_alloc_size;\n\tstruct dm_stat_percpu *stat_percpu[512];\n\tstruct dm_stat_shared stat_shared[0];\n};\n\nstruct dm_stats_last_position;\n\nstruct dm_stats {\n\tstruct mutex mutex;\n\tstruct list_head list;\n\tstruct dm_stats_last_position *last;\n\tbool precise_timestamps;\n};\n\nstruct dm_stats_last_position {\n\tsector_t last_sector;\n\tunsigned int last_rw;\n};\n\nstruct dm_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mapped_device *, char *);\n\tssize_t (*store)(struct mapped_device *, const char *, size_t);\n};\n\nstruct target_type;\n\nstruct dm_table {\n\tstruct mapped_device *md;\n\tenum dm_queue_mode type;\n\tunsigned int depth;\n\tunsigned int counts[16];\n\tsector_t *index[16];\n\tunsigned int num_targets;\n\tunsigned int num_allocated;\n\tsector_t *highs;\n\tstruct dm_target *targets;\n\tstruct target_type *immutable_target_type;\n\tbool integrity_supported: 1;\n\tbool singleton: 1;\n\tbool flush_bypasses_map: 1;\n\tblk_mode_t mode;\n\tstruct list_head devices;\n\tvoid (*event_fn)(void *);\n\tvoid *event_context;\n\tstruct dm_md_mempools *mempools;\n\tstruct blk_crypto_profile *crypto_profile;\n};\n\nstruct dm_target {\n\tstruct dm_table *table;\n\tstruct target_type *type;\n\tsector_t begin;\n\tsector_t len;\n\tuint32_t max_io_len;\n\tunsigned int num_flush_bios;\n\tunsigned int num_discard_bios;\n\tunsigned int num_secure_erase_bios;\n\tunsigned int num_write_zeroes_bios;\n\tunsigned int per_io_data_size;\n\tvoid *private;\n\tchar *error;\n\tbool flush_supported: 1;\n\tbool discards_supported: 1;\n\tbool zone_reset_all_supported: 1;\n\tbool max_discard_granularity: 1;\n\tbool limit_swap_bios: 1;\n\tbool emulate_zone_append: 1;\n\tbool accounts_remapped_io: 1;\n\tbool needs_bio_set_dev: 1;\n\tbool flush_bypasses_map: 1;\n\tbool mempool_needs_integrity: 1;\n};\n\nstruct dm_target_deps {\n\t__u32 count;\n\t__u32 padding;\n\t__u64 dev[0];\n};\n\nstruct dm_target_msg {\n\t__u64 sector;\n\tchar message[0];\n};\n\nstruct dm_target_spec {\n\t__u64 sector_start;\n\t__u64 length;\n\t__s32 status;\n\t__u32 next;\n\tchar target_type[16];\n};\n\nstruct dm_target_versions {\n\t__u32 next;\n\t__u32 version[3];\n\tchar name[0];\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct dm_uevent {\n\tstruct mapped_device *md;\n\tenum kobject_action action;\n\tstruct kobj_uevent_env ku_env;\n\tstruct list_head elist;\n\tchar name[128];\n\tchar uuid[129];\n};\n\nstruct dm_wrappedkey_op_args {\n\tenum dm_wrappedkey_op op;\n\tint err;\n\tunion {\n\t\tstruct {\n\t\t\tconst u8 *eph_key;\n\t\t\tsize_t eph_key_size;\n\t\t\tu8 *sw_secret;\n\t\t} derive_sw_secret;\n\t\tstruct {\n\t\t\tconst u8 *raw_key;\n\t\t\tsize_t raw_key_size;\n\t\t\tu8 *lt_key;\n\t\t} import_key;\n\t\tstruct {\n\t\t\tu8 *lt_key;\n\t\t} generate_key;\n\t\tstruct {\n\t\t\tconst u8 *lt_key;\n\t\t\tsize_t lt_key_size;\n\t\t\tu8 *eph_key;\n\t\t} prepare_key;\n\t};\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_resv;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct dma_iova_state;\n\nstruct dma_buf_dma {\n\tstruct sg_table sgt;\n\tstruct dma_iova_state *state;\n\tsize_t size;\n};\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct dma_buf_export_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_import_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_buf_sg_table_wrapper {\n\tstruct sg_table *original;\n\tstruct sg_table wrapper;\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n};\n\nstruct dma_fence_array;\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n\tstruct dma_fence_array_cb callbacks[0];\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tstruct dma_fence *prev;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tunion {\n\t\tstruct dma_fence_cb cb;\n\t\tstruct irq_work work;\n\t};\n\tspinlock_t lock;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_fence_unwrap {\n\tstruct dma_fence *chain;\n\tstruct dma_fence *array;\n\tunsigned int index;\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct ww_acquire_ctx;\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tstruct dma_resv_list *fences;\n};\n\nstruct dma_resv_iter {\n\tstruct dma_resv *obj;\n\tenum dma_resv_usage usage;\n\tstruct dma_fence *fence;\n\tenum dma_resv_usage fence_usage;\n\tunsigned int index;\n\tstruct dma_resv_list *fences;\n\tunsigned int num_fences;\n\tbool is_restarted;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 num_fences;\n\tu32 max_fences;\n\tstruct dma_fence *table[0];\n};\n\nstruct dma_sgt_handle {\n\tstruct sg_table sgt;\n\tstruct page **pages;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct net_devmem_dmabuf_binding;\n\nstruct dmabuf_genpool_chunk_owner {\n\tstruct net_iov_area area;\n\tstruct net_devmem_dmabuf_binding *binding;\n\tdma_addr_t base_dma_addr;\n};\n\nstruct dmabuf_iter_priv {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct dp_sdp_header {\n\tu8 HB0;\n\tu8 HB1;\n\tu8 HB2;\n\tu8 HB3;\n};\n\nstruct dp_sdp {\n\tstruct dp_sdp_header sdp_header;\n\tu8 db[32];\n};\n\nstruct dpages {\n\tvoid (*get_page)(struct dpages *, struct page **, long unsigned int *, unsigned int *);\n\tvoid (*next_page)(struct dpages *);\n\tunion {\n\t\tunsigned int context_u;\n\t\tstruct bvec_iter context_bi;\n\t};\n\tvoid *context_ptr;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dqstats {\n\tlong unsigned int stat[8];\n\tstruct percpu_counter counter[8];\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct dquot_warn {\n\tstruct super_block *w_sb;\n\tstruct kqid w_dq_id;\n\tshort int w_type;\n};\n\nstruct drbg_core {\n\tdrbg_flag_t flags;\n\t__u8 statelen;\n\t__u8 blocklen_bytes;\n\tchar cra_name[128];\n\tchar backend_cra_name[128];\n};\n\nstruct drbg_string {\n\tconst unsigned char *buf;\n\tsize_t len;\n\tstruct list_head list;\n};\n\nstruct drbg_state_ops;\n\nstruct drbg_state {\n\tstruct mutex drbg_mutex;\n\tunsigned char *V;\n\tunsigned char *Vbuf;\n\tunsigned char *C;\n\tunsigned char *Cbuf;\n\tsize_t reseed_ctr;\n\tsize_t reseed_threshold;\n\tunsigned char *scratchpad;\n\tunsigned char *scratchpadbuf;\n\tvoid *priv_data;\n\tstruct crypto_skcipher *ctr_handle;\n\tstruct skcipher_request *ctr_req;\n\t__u8 *outscratchpadbuf;\n\t__u8 *outscratchpad;\n\tstruct crypto_wait ctr_wait;\n\tstruct scatterlist sg_in;\n\tstruct scatterlist sg_out;\n\tenum drbg_seed_state seeded;\n\tlong unsigned int last_seed_time;\n\tbool pr;\n\tbool fips_primed;\n\tunsigned char *prev;\n\tstruct crypto_rng *jent;\n\tconst struct drbg_state_ops *d_ops;\n\tconst struct drbg_core *core;\n\tstruct drbg_string test_data;\n};\n\nstruct drbg_state_ops {\n\tint (*update)(struct drbg_state *, struct list_head *, int);\n\tint (*generate)(struct drbg_state *, unsigned char *, unsigned int, struct list_head *);\n\tint (*crypto_init)(struct drbg_state *);\n\tint (*crypto_fini)(struct drbg_state *);\n};\n\nstruct drbg_test_data {\n\tstruct drbg_string *testentropy;\n};\n\nstruct drbg_testvec {\n\tconst unsigned char *entropy;\n\tsize_t entropylen;\n\tconst unsigned char *entpra;\n\tconst unsigned char *entprb;\n\tsize_t entprlen;\n\tconst unsigned char *addtla;\n\tconst unsigned char *addtlb;\n\tsize_t addtllen;\n\tconst unsigned char *pers;\n\tsize_t perslen;\n\tconst unsigned char *expected;\n\tsize_t expectedlen;\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct pci_driver;\n\nstruct pci_dev;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tlocal_lock_t bh_lock;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct dst_ops;\n\nstruct xfrm_state;\n\nstruct uncached_list;\n\nstruct lwtunnel_state;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tstruct xfrm_state *xfrm;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\trcuref_t __rcuref;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n\tstruct lwtunnel_state *lwtstate;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct dyn_arch_ftrace {};\n\nstruct dyn_event_operations;\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(const char *);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dyn_ftrace {\n\tlong unsigned int ip;\n\tlong unsigned int flags;\n\tstruct dyn_arch_ftrace arch;\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct eadm_orb {\n\tu32 intparm;\n\tu32 key: 4;\n\tchar: 4;\n\tu32 compat1: 1;\n\tu32 compat2: 1;\n\tshort: 6;\n\tshort: 15;\n\tu32 x: 1;\n\tdma32_t aob;\n\tu32 css_prio: 8;\n\tshort: 8;\n\tu32 scm_prio: 8;\n\tlong: 8;\n\tint: 29;\n\tu32 fmt: 3;\n\tlong: 64;\n};\n\nstruct eb_batch {\n\tunsigned int nr;\n\tunsigned int cur;\n\tstruct extent_buffer *ebs[31];\n};\n\nstruct ebitmap_node {\n\tstruct ebitmap_node *next;\n\tlong unsigned int maps[6];\n\tu32 startbit;\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[2];\n\tlong unsigned int advertised[2];\n\tlong unsigned int lp_advertised[2];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\nstruct eerbuffer {\n\tstruct list_head list;\n\tchar **buffer;\n\tint buffersize;\n\tint buffer_page_count;\n\tint head;\n\tint tail;\n\tint residual;\n};\n\nstruct elevator_queue;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_note {\n\tElf64_Word n_namesz;\n\tElf64_Word n_descsz;\n\tElf64_Word n_type;\n};\n\ntypedef struct elf64_note Elf64_Nhdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct elf64_rela {\n\tElf64_Addr r_offset;\n\tElf64_Xword r_info;\n\tElf64_Sxword r_addend;\n};\n\ntypedef struct elf64_rela Elf64_Rela;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\ntypedef struct elf64_shdr Elf64_Shdr;\n\nstruct elf64_sym {\n\tElf64_Word st_name;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf64_Half st_shndx;\n\tElf64_Addr st_value;\n\tElf64_Xword st_size;\n};\n\ntypedef struct elf64_sym Elf64_Sym;\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct trace_event_file;\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n} __attribute__((packed));\n\nstruct epoll_event {\n\t__poll_t events;\n\t__u64 data;\n};\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct wakeup_source;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct trace_eprobe;\n\nstruct eprobe_data {\n\tstruct trace_event_file *file;\n\tstruct trace_eprobe *ep;\n};\n\nstruct eprobe_trace_entry_head {\n\tstruct trace_entry ent;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu16 pos;\n\tu64 ts;\n};\n\nstruct err_notify_evbuf {\n\tstruct evbuf_header header;\n\tu8 action;\n\tu8 atype;\n\tu32 fh;\n\tu32 fid;\n\tu8 data[0];\n};\n\nstruct err_notify_sccb {\n\tstruct sccb_header header;\n\tstruct err_notify_evbuf evbuf;\n};\n\nstruct error_info {\n\tshort unsigned int code12;\n\tshort unsigned int size;\n};\n\nstruct error_info2 {\n\tunsigned char code1;\n\tunsigned char code2_min;\n\tunsigned char code2_max;\n\tconst char *str;\n\tconst char *fmt;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 p: 1;\n\t__u8 ft: 5;\n\t__u8 hwid_upper: 2;\n\t__u8 hwid: 4;\n\t__u8 dir: 1;\n\t__u8 gra: 2;\n\t__u8 o: 1;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nunion ipte_control {\n\tlong unsigned int val;\n\tstruct {\n\t\tlong unsigned int k: 1;\n\t\tlong unsigned int kh: 31;\n\t\tlong unsigned int kg: 32;\n\t};\n};\n\nunion sca_utility {\n\t__u32 val;\n\tstruct {\n\t\t__u32 mtcr: 1;\n\t};\n};\n\nunion esca_sigp_ctrl {\n\t__u16 value;\n\tstruct {\n\t\t__u8 c: 1;\n\t\t__u8 reserved: 7;\n\t\t__u8 scn;\n\t};\n};\n\nstruct esca_entry {\n\tunion esca_sigp_ctrl sigp_ctrl;\n\t__u16 reserved1[3];\n\t__u64 sda;\n\t__u64 reserved2[6];\n};\n\nstruct esca_block {\n\tunion ipte_control ipte_control;\n\t__u64 reserved1[6];\n\tunion sca_utility utility;\n\t__u8 reserved2[4];\n\t__u64 mcn[4];\n\t__u64 reserved3[20];\n\tstruct esca_entry cpu[248];\n};\n\nstruct strp_stats {\n\tlong long unsigned int msgs;\n\tlong long unsigned int bytes;\n\tunsigned int mem_fail;\n\tunsigned int need_more_hdr;\n\tunsigned int msg_too_big;\n\tunsigned int msg_timeouts;\n\tunsigned int bad_hdr_len;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\nstruct strparser;\n\nstruct strp_callbacks {\n\tint (*parse_msg)(struct strparser *, struct sk_buff *);\n\tvoid (*rcv_msg)(struct strparser *, struct sk_buff *);\n\tint (*read_sock)(struct strparser *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_sock_done)(struct strparser *, int);\n\tvoid (*abort_parser)(struct strparser *, int);\n\tvoid (*lock)(struct strparser *);\n\tvoid (*unlock)(struct strparser *);\n};\n\nstruct strparser {\n\tstruct sock *sk;\n\tu32 stopped: 1;\n\tu32 paused: 1;\n\tu32 aborted: 1;\n\tu32 interrupted: 1;\n\tu32 unrecov_intr: 1;\n\tstruct sk_buff **skb_nextp;\n\tstruct sk_buff *skb_head;\n\tunsigned int need_bytes;\n\tstruct delayed_work msg_timer_work;\n\tstruct work_struct work;\n\tstruct strp_stats stats;\n\tstruct strp_callbacks cb;\n};\n\nstruct espintcp_msg {\n\tstruct sk_buff *skb;\n\tstruct sk_msg skmsg;\n\tint offset;\n\tint len;\n};\n\nstruct espintcp_ctx {\n\tstruct strparser strp;\n\tstruct sk_buff_head ike_queue;\n\tstruct sk_buff_head out_queue;\n\tstruct espintcp_msg partial;\n\tvoid (*saved_data_ready)(struct sock *);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_destruct)(struct sock *);\n\tstruct work_struct work;\n\tbool tx_running;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[2];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[2];\n\t\tlong unsigned int advertising[2];\n\t\tlong unsigned int lp_advertising[2];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_regs;\n\nstruct ethtool_wolinfo;\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_test;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxnfc;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_ts_stats;\n\nstruct ethtool_tunable;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_device;\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\t__u64 ring_cookie;\n\t__u32 location;\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct input_dev;\n\nstruct input_handler;\n\nstruct input_value;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct fasync_struct;\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct event_trigger_data;\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*parse)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*trigger)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tbool (*count_func)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_data *);\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nstruct event_mod_load {\n\tstruct list_head list;\n\tchar *module;\n\tchar *match;\n\tchar *system;\n\tchar *event;\n};\n\nstruct event_probe_data {\n\tstruct trace_event_file *file;\n\tlong unsigned int count;\n\tint ref;\n\tbool enable;\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tint flags;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n\tstruct llist_node llist;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventfs_attr {\n\tint mode;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\ntypedef int (*eventfs_callback)(const char *, umode_t *, void **, const struct file_operations **);\n\ntypedef void (*eventfs_release)(const char *, void *);\n\nstruct eventfs_entry {\n\tconst char *name;\n\teventfs_callback callback;\n\teventfs_release release;\n};\n\nstruct eventfs_inode {\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head children;\n\tconst struct eventfs_entry *entries;\n\tconst char *name;\n\tstruct eventfs_attr *entry_attrs;\n\tvoid *data;\n\tstruct eventfs_attr attr;\n\tstruct kref kref;\n\tunsigned int is_freed: 1;\n\tunsigned int is_events: 1;\n\tunsigned int nr_entries: 30;\n\tunsigned int ino;\n};\n\nstruct eventfs_root_inode {\n\tstruct eventfs_inode ei;\n\tstruct dentry *events_dir;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n};\n\nstruct evm_ima_xattr_data_hdr {\n\tu8 type;\n};\n\nstruct evm_ima_xattr_data {\n\tunion {\n\t\tstruct {\n\t\t\tu8 type;\n\t\t};\n\t\tstruct evm_ima_xattr_data_hdr hdr;\n\t};\n\tu8 data[0];\n};\n\nstruct exception_table_entry {\n\tint insn;\n\tint fixup;\n\tshort int type;\n\tshort int data;\n};\n\nstruct exceptional_entry_key {\n\tstruct xarray *xa;\n\tlong unsigned int entry_start;\n};\n\nstruct exec_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct exit_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__u32 exit_code;\n\t__u32 exit_signal;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_buddy;\n\nstruct ext4_prealloc_space;\n\nstruct ext4_locality_group;\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\text4_grpblk_t ac_orig_goal_len;\n\text4_group_t ac_prefetch_grp;\n\tunsigned int ac_prefetch_ios;\n\tunsigned int ac_prefetch_nr;\n\tint ac_first_err;\n\t__u32 ac_flags;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_cX_found[5];\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct ext4_buddy *ac_e4b;\n\tstruct folio *ac_bitmap_folio;\n\tstruct folio *ac_buddy_folio;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_group_info;\n\nstruct ext4_buddy {\n\tstruct folio *bd_buddy_folio;\n\tvoid *bd_buddy;\n\tstruct folio *bd_bitmap_folio;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_hash {\n\t__le32 hash;\n\t__le32 minor_hash;\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\nstruct ext4_err_translation {\n\tint code;\n\tint errno;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct extent_status;\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_extent;\n\nstruct ext4_extent_idx;\n\nstruct ext4_extent_header;\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_fc_add_range {\n\t__le32 fc_ino;\n\t__u8 fc_ex[12];\n};\n\nstruct ext4_fc_alloc_region {\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tint ino;\n\tint len;\n};\n\nstruct ext4_fc_del_range {\n\t__le32 fc_ino;\n\t__le32 fc_lblk;\n\t__le32 fc_len;\n};\n\nstruct ext4_fc_dentry_info {\n\t__le32 fc_parent_ino;\n\t__le32 fc_ino;\n\t__u8 fc_dname[0];\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n};\n\nstruct ext4_fc_dentry_update {\n\tint fcd_op;\n\tint fcd_parent;\n\tint fcd_ino;\n\tstruct name_snapshot fcd_name;\n\tstruct list_head fcd_list;\n\tstruct list_head fcd_dilist;\n};\n\nstruct ext4_fc_head {\n\t__le32 fc_features;\n\t__le32 fc_tid;\n};\n\nstruct ext4_fc_inode {\n\t__le32 fc_ino;\n\t__u8 fc_raw_inode[0];\n};\n\nstruct ext4_fc_replay_state {\n\tint fc_replay_num_tags;\n\tint fc_replay_expected_off;\n\tint fc_current_pass;\n\tint fc_cur_tag;\n\tint fc_crc;\n\tstruct ext4_fc_alloc_region *fc_regions;\n\tint fc_regions_size;\n\tint fc_regions_used;\n\tint fc_regions_valid;\n\tint *fc_modified_inodes;\n\tint fc_modified_inodes_used;\n\tint fc_modified_inodes_size;\n};\n\nstruct ext4_fc_stats {\n\tunsigned int fc_ineligible_reason_count[13];\n\tlong unsigned int fc_num_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_failed_commits;\n\tlong unsigned int fc_skipped_commits;\n\tlong unsigned int fc_numblks;\n\tu64 s_fc_avg_commit_time;\n};\n\nstruct ext4_fc_tail {\n\t__le32 fc_tid;\n\t__le32 fc_crc;\n};\n\nstruct ext4_fc_tl {\n\t__le16 fc_tag;\n\t__le16 fc_len;\n};\n\nstruct ext4_fc_tl_mem {\n\tu16 fc_tag;\n\tu16 fc_len;\n};\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n\tstruct fscrypt_str crypto_buf;\n\tstruct qstr cf_name;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nunion fscrypt_policy;\n\nstruct fscrypt_dummy_policy {\n\tconst union fscrypt_policy *policy;\n};\n\nstruct ext4_fs_context {\n\tchar *s_qf_names[3];\n\tstruct fscrypt_dummy_policy dummy_enc_policy;\n\tint s_jquota_fmt;\n\tshort unsigned int qname_spec;\n\tlong unsigned int vals_s_flags;\n\tlong unsigned int mask_s_flags;\n\tlong unsigned int journal_devnum;\n\tlong unsigned int s_commit_interval;\n\tlong unsigned int s_stripe;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_want_extra_isize;\n\tunsigned int s_li_wait_mult;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int journal_ioprio;\n\tunsigned int vals_s_mount_opt;\n\tunsigned int mask_s_mount_opt;\n\tunsigned int vals_s_mount_opt2;\n\tunsigned int mask_s_mount_opt2;\n\tunsigned int opt_flags;\n\tunsigned int spec;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\text4_fsblk_t s_sb_block;\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\nstruct ext4_getfsmap_info;\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\tint bb_avg_fragment_size_order;\n\text4_grpblk_t bb_largest_free_order;\n\text4_group_t bb_group;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct jbd2_inode;\n\nstruct fscrypt_inode_info;\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tunion {\n\t\tstruct list_head i_orphan;\n\t\tunsigned int i_orphan_idx;\n\t};\n\tstruct list_head i_fc_dilist;\n\tstruct list_head i_fc_list;\n\text4_lblk_t i_fc_lblk_start;\n\text4_lblk_t i_fc_lblk_len;\n\tspinlock_t i_raw_lock;\n\twait_queue_head_t i_fc_wait;\n\tspinlock_t i_fc_lock;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tstruct timespec64 i_crtime;\n\tatomic_t i_prealloc_active;\n\tunsigned int i_reserved_data_blocks;\n\tstruct rb_root i_prealloc_node;\n\trwlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\tu64 i_es_seq;\n\text4_group_t i_last_alloc_group;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tqsize_t i_reserved_quota;\n\tspinlock_t i_block_reservation_lock;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\tstruct dquot *i_dquot[3];\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n\tstruct fscrypt_inode_info *i_crypt_info;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\trefcount_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n};\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tsector_t io_next_block;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct ext4_journal_trigger {\n\tstruct jbd2_buffer_trigger_type tr_triggers;\n\tstruct super_block *sb;\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tenum ext4_li_mode lr_mode;\n\text4_group_t lr_first_not_zeroed;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n\tu64 m_seq;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n\tint s_jquota_fmt;\n\tchar *s_qf_names[3];\n};\n\nstruct ext4_new_group_data;\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t resize_bg;\n\text4_group_t count;\n};\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct ext4_orphan_block {\n\tatomic_t ob_free_entries;\n\tstruct buffer_head *ob_bh;\n};\n\nstruct ext4_orphan_block_tail {\n\t__le32 ob_magic;\n\t__le32 ob_checksum;\n};\n\nstruct ext4_orphan_info {\n\tint of_blocks;\n\t__u32 of_csum_seed;\n\tstruct ext4_orphan_block *of_binfo;\n};\n\nstruct ext4_prealloc_space {\n\tunion {\n\t\tstruct rb_node inode_node;\n\t\tstruct list_head lg_list;\n\t} pa_node;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tunion {\n\t\trwlock_t *inode_lock;\n\t\tspinlock_t *lg_lock;\n\t} pa_node_lock;\n\tstruct inode *pa_inode;\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nstruct ext4_sb_encodings {\n\t__u16 magic;\n\tchar *name;\n\tunsigned int version;\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct ext4_super_block;\n\nstruct proc_dir_entry;\n\nstruct journal_s;\n\nstruct ext4_system_blocks;\n\nstruct flex_groups;\n\nstruct mb_cache;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tlong unsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\tunsigned int s_def_mount_opt2;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct percpu_counter s_sra_exceeded_retry_limit;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct buffer_head *s_mmp_bh;\n\tstruct journal_s *s_journal;\n\tlong unsigned int s_ext4_flags;\n\tstruct mutex s_orphan_lock;\n\tstruct list_head s_orphan;\n\tstruct ext4_orphan_info s_orphan_info;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct file *s_journal_bdev_file;\n\tchar *s_qf_names[3];\n\tint s_jquota_fmt;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *s_system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tatomic_t s_mb_free_pending;\n\tstruct list_head s_freed_data_list[2];\n\tstruct list_head s_discard_list;\n\tstruct work_struct s_discard_work;\n\tatomic_t s_retry_alloc_pending;\n\tstruct xarray *s_mb_avg_fragment_size;\n\tstruct xarray *s_mb_largest_free_orders;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_max_linear_groups;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int s_mb_prefetch;\n\tunsigned int s_mb_prefetch_limit;\n\tunsigned int s_mb_best_avail_max_trim_order;\n\tunsigned int s_sb_update_sec;\n\tunsigned int s_sb_update_kb;\n\text4_group_t *s_mb_last_groups;\n\tunsigned int s_mb_nr_global_goals;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_cX_ex_scanned[5];\n\tatomic_t s_bal_groups_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_stream_goals;\n\tatomic_t s_bal_len_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tatomic64_t s_bal_cX_groups_considered[5];\n\tatomic64_t s_bal_cX_hits[5];\n\tatomic64_t s_bal_cX_failed[5];\n\tatomic_t s_mb_buddies_generated;\n\tatomic64_t s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tlong unsigned int s_err_report_sec;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tlong unsigned int s_last_trim_minblks;\n\tu16 s_min_folio_order;\n\tu16 s_max_folio_order;\n\t__u32 s_csum_seed;\n\tstruct shrinker *s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache *s_ea_block_cache;\n\tstruct mb_cache *s_ea_inode_cache;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_es_lock;\n\tstruct ext4_journal_trigger s_journal_triggers[1];\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tatomic_t s_warning_count;\n\tatomic_t s_msg_count;\n\tstruct fscrypt_dummy_policy s_dummy_enc_policy;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tu64 s_dax_part_off;\n\terrseq_t s_bdev_wb_err;\n\tspinlock_t s_bdev_wb_lock;\n\tspinlock_t s_error_lock;\n\tint s_add_error_count;\n\tint s_first_error_code;\n\t__u32 s_first_error_line;\n\t__u32 s_first_error_ino;\n\t__u64 s_first_error_block;\n\tconst char *s_first_error_func;\n\ttime64_t s_first_error_time;\n\tint s_last_error_code;\n\t__u32 s_last_error_line;\n\t__u32 s_last_error_ino;\n\t__u64 s_last_error_block;\n\tconst char *s_last_error_func;\n\ttime64_t s_last_error_time;\n\tstruct work_struct s_sb_upd_work;\n\tunsigned int s_awu_min;\n\tunsigned int s_awu_max;\n\tatomic_t s_fc_subtid;\n\tstruct list_head s_fc_q[2];\n\tstruct list_head s_fc_dentry_q[2];\n\tunsigned int s_fc_bytes;\n\tstruct mutex s_fc_lock;\n\tstruct buffer_head *s_fc_bh;\n\tstruct ext4_fc_stats s_fc_stats;\n\ttid_t s_fc_ineligible_tid;\n\tstruct ext4_fc_replay_state s_fc_replay_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_orphan_file_inum;\n\t__le16 s_def_resuid_hi;\n\t__le16 s_def_resgid_hi;\n\t__le32 s_reserved[93];\n\t__le32 s_checksum;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n\tu32 ino;\n};\n\nstruct ext4_tune_sb_params {\n\t__u32 set_flags;\n\t__u32 checkinterval;\n\t__u16 errors_behavior;\n\t__u16 mnt_count;\n\t__u16 max_mnt_count;\n\t__u16 raid_stride;\n\t__u64 last_check_time;\n\t__u64 reserved_blocks;\n\t__u64 blocks_count;\n\t__u32 default_mnt_opts;\n\t__u32 reserved_uid;\n\t__u32 reserved_gid;\n\t__u32 raid_stripe_width;\n\t__u16 encoding;\n\t__u16 encoding_flags;\n\t__u8 def_hash_alg;\n\t__u8 pad_1;\n\t__u16 pad_2;\n\t__u32 feature_compat;\n\t__u32 feature_incompat;\n\t__u32 feature_ro_compat;\n\t__u32 set_feature_compat_mask;\n\t__u32 set_feature_incompat_mask;\n\t__u32 set_feature_ro_compat_mask;\n\t__u32 clear_feature_compat_mask;\n\t__u32 clear_feature_incompat_mask;\n\t__u32 clear_feature_ro_compat_mask;\n\t__u8 mount_opts[64];\n\t__u8 pad[68];\n};\n\nstruct ext4_xattr_entry;\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n};\n\nstruct ext_code {\n\tunion {\n\t\tstruct {\n\t\t\tshort unsigned int subcode;\n\t\t\tshort unsigned int code;\n\t\t};\n\t\tunsigned int int_code;\n\t};\n};\n\ntypedef void (*ext_int_handler_t)(struct ext_code, unsigned int, long unsigned int);\n\nstruct ext_int_info {\n\text_int_handler_t handler;\n\tstruct hlist_node entry;\n\tstruct callback_head rcu;\n\tu16 code;\n};\n\nstruct ext_pool_exhaust_work_data {\n\tstruct work_struct worker;\n\tstruct dasd_device *device;\n\tstruct dasd_device *base;\n};\n\nstruct msg_msg;\n\nstruct ext_wait_queue {\n\tstruct task_struct *task;\n\tstruct list_head list;\n\tstruct msg_msg *msg;\n\tint state;\n};\n\nstruct extent_buffer {\n\tu64 start;\n\tu32 len;\n\tu32 folio_size;\n\tlong unsigned int bflags;\n\tstruct btrfs_fs_info *fs_info;\n\tvoid *addr;\n\tspinlock_t refs_lock;\n\trefcount_t refs;\n\tint read_mirror;\n\ts8 log_index;\n\tu8 folio_shift;\n\tstruct callback_head callback_head;\n\tstruct rw_semaphore lock;\n\tstruct folio *folios[16];\n};\n\nstruct extent_changeset {\n\tu64 bytes_changed;\n\tstruct ulist range_changed;\n};\n\nstruct extent_inode_elem {\n\tu64 inum;\n\tu64 offset;\n\tu64 num_bytes;\n\tstruct extent_inode_elem *next;\n};\n\nstruct extent_map {\n\tstruct rb_node rb_node;\n\tu64 start;\n\tu64 len;\n\tu64 disk_bytenr;\n\tu64 disk_num_bytes;\n\tu64 offset;\n\tu64 ram_bytes;\n\tu64 generation;\n\tu32 flags;\n\trefcount_t refs;\n\tstruct list_head list;\n};\n\nstruct extent_state {\n\tu64 start;\n\tu64 end;\n\tstruct rb_node rb_node;\n\twait_queue_head_t wq;\n\trefcount_t refs;\n\tu32 state;\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\text4_fsblk_t es_pblk;\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct stack_frame {\n\tunion {\n\t\tlong unsigned int empty[9];\n\t\tstruct {\n\t\t\tlong unsigned int sie_control_block;\n\t\t\tlong unsigned int sie_savearea;\n\t\t\tlong unsigned int sie_reason;\n\t\t\tlong unsigned int sie_flags;\n\t\t\tlong unsigned int sie_control_block_phys;\n\t\t\tlong unsigned int sie_guest_asce;\n\t\t\tlong unsigned int sie_irq;\n\t\t};\n\t};\n\tlong unsigned int gprs[10];\n\tlong unsigned int back_chain;\n};\n\nstruct fake_frame {\n\tstruct stack_frame sf;\n\tstruct pt_regs childregs;\n};\n\nstruct falloc_range {\n\tstruct list_head list;\n\tu64 start;\n\tu64 len;\n};\n\nstruct fan_fsid {\n\tstruct super_block *sb;\n\t__kernel_fsid_t id;\n\tbool weak;\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct fanotify_event {\n\tstruct fsnotify_event fse;\n\tstruct hlist_node merge_list;\n\tu32 mask;\n\tstruct {\n\t\tunsigned int type: 3;\n\t\tunsigned int hash: 29;\n\t};\n\tstruct pid *pid;\n};\n\nstruct fanotify_fh {\n\tu8 type;\n\tu8 len;\n\tu8 flags;\n\tu8 pad;\n};\n\nstruct fanotify_error_event {\n\tstruct fanotify_event fae;\n\ts32 error;\n\tu32 err_count;\n\t__kernel_fsid_t fsid;\n\tstruct {\n\t\tstruct fanotify_fh object_fh;\n\t\tunsigned char _inline_fh_buf[128];\n\t};\n};\n\nstruct fanotify_event_info_header {\n\t__u8 info_type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_event_info_error {\n\tstruct fanotify_event_info_header hdr;\n\t__s32 error;\n\t__u32 error_count;\n};\n\nstruct fanotify_event_info_fid {\n\tstruct fanotify_event_info_header hdr;\n\t__kernel_fsid_t fsid;\n\tunsigned char handle[0];\n};\n\nstruct fanotify_event_info_mnt {\n\tstruct fanotify_event_info_header hdr;\n\t__u64 mnt_id;\n};\n\nstruct fanotify_event_info_pidfd {\n\tstruct fanotify_event_info_header hdr;\n\t__s32 pidfd;\n};\n\nstruct fanotify_event_info_range {\n\tstruct fanotify_event_info_header hdr;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 count;\n};\n\nstruct fanotify_event_metadata {\n\t__u32 event_len;\n\t__u8 vers;\n\t__u8 reserved;\n\t__u16 metadata_len;\n\t__u64 mask;\n\t__s32 fd;\n\t__s32 pid;\n};\n\nstruct fanotify_fid_event {\n\tstruct fanotify_event fae;\n\t__kernel_fsid_t fsid;\n\tstruct {\n\t\tstruct fanotify_fh object_fh;\n\t\tunsigned char _inline_fh_buf[12];\n\t};\n};\n\nstruct fanotify_group_private_data {\n\tstruct hlist_head *merge_hash;\n\tstruct list_head access_list;\n\twait_queue_head_t access_waitq;\n\tint flags;\n\tint f_flags;\n\tstruct ucounts *ucounts;\n\tmempool_t error_events_pool;\n\tstruct list_head perm_grp_list;\n};\n\nstruct fanotify_info {\n\tu8 dir_fh_totlen;\n\tu8 dir2_fh_totlen;\n\tu8 file_fh_totlen;\n\tu8 name_len;\n\tu8 name2_len;\n\tu8 pad[3];\n\tunsigned char buf[0];\n};\n\nstruct fanotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\t__kernel_fsid_t fsid;\n};\n\nstruct fanotify_mnt_event {\n\tstruct fanotify_event fae;\n\tu64 mnt_id;\n};\n\nstruct fanotify_name_event {\n\tstruct fanotify_event fae;\n\t__kernel_fsid_t fsid;\n\tstruct fanotify_info info;\n};\n\nstruct fanotify_path_event {\n\tstruct fanotify_event fae;\n\tstruct path path;\n};\n\nstruct fanotify_response_info_header {\n\t__u8 type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_response_info_audit_rule {\n\tstruct fanotify_response_info_header hdr;\n\t__u32 rule_number;\n\t__u32 subj_trust;\n\t__u32 obj_trust;\n};\n\nstruct fanotify_perm_event {\n\tstruct fanotify_event fae;\n\tstruct path path;\n\tconst loff_t *ppos;\n\tsize_t count;\n\tu32 response;\n\tshort unsigned int state;\n\tshort unsigned int watchdog_cnt;\n\tint fd;\n\tpid_t recv_pid;\n\tunion {\n\t\tstruct fanotify_response_info_header hdr;\n\t\tstruct fanotify_response_info_audit_rule audit_rule;\n\t};\n};\n\nstruct fanotify_response {\n\t__s32 fd;\n\t__u32 response;\n};\n\nstruct fanout_args {\n\t__u16 type_flags;\n\t__u16 id;\n\t__u32 max_num_members;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fault_attr {};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_address {\n\tvoid *address;\n\tint bits;\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_bitmap4x_iter {\n\tconst u8 *data;\n\tu32 fgxcolor;\n\tu32 bgcolor;\n\tint width;\n\tint i;\n\tconst u32 *expand;\n\tint bpp;\n\tbool top;\n};\n\nstruct fb_bitmap_iter {\n\tconst u8 *data;\n\tlong unsigned int colors[2];\n\tint width;\n\tint i;\n};\n\nstruct fb_blit_caps {\n\tlong unsigned int x[1];\n\tlong unsigned int y[2];\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_reverse {\n\tbool byte;\n\tbool pixel;\n};\n\nstruct fb_color_iter {\n\tconst u8 *data;\n\tconst u32 *palette;\n\tstruct fb_reverse reverse;\n\tint shift;\n\tint width;\n\tint i;\n};\n\nstruct fb_con2fbmap {\n\t__u32 console;\n\t__u32 framebuffer;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\nstruct fb_info;\n\nstruct fb_deferred_io {\n\tlong unsigned int delay;\n\tbool sort_pagereflist;\n\tint open_count;\n\tstruct mutex lock;\n\tstruct list_head pagereflist;\n\tstruct address_space *mapping;\n\tstruct page * (*get_page)(struct fb_info *, long unsigned int);\n\tvoid (*deferred_io)(struct fb_info *, struct list_head *);\n};\n\nstruct fb_deferred_io_pageref {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tstruct list_head list;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_videomode;\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tlong unsigned int blit_x[1];\n\tlong unsigned int blit_y[2];\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct lcd_device;\n\nstruct fb_ops;\n\nstruct fbcon_par;\n\nstruct fb_info {\n\trefcount_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tint blank;\n\tstruct lcd_device *lcd_dev;\n\tstruct delayed_work deferred_work;\n\tlong unsigned int npagerefs;\n\tstruct fb_deferred_io_pageref *pagerefs;\n\tstruct fb_deferred_io *fbdefio;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tstruct fbcon_par *fbcon_par;\n\tvoid *par;\n\tbool skip_vt_switch;\n\tbool skip_panic;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n};\n\nstruct fb_pattern {\n\tlong unsigned int pixels;\n\tint left;\n\tint right;\n\tstruct fb_reverse reverse;\n};\n\nstruct fbcon_bitops {\n\tvoid (*bmove)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*clear)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*putcs)(struct vc_data *, struct fb_info *, const short unsigned int *, int, int, int, int, int);\n\tvoid (*clear_margins)(struct vc_data *, struct fb_info *, int, int);\n\tvoid (*cursor)(struct vc_data *, struct fb_info *, bool, int, int);\n\tint (*update_start)(struct fb_info *);\n\tint (*rotate_font)(struct fb_info *, struct vc_data *);\n};\n\nstruct fbcon_display {\n\tconst u_char *fontdata;\n\tint userfont;\n\tshort int yscroll;\n\tint vrows;\n\tint cursor_shape;\n\tint con_rotate;\n\tu32 xres_virtual;\n\tu32 yres_virtual;\n\tu32 height;\n\tu32 width;\n\tu32 bits_per_pixel;\n\tu32 grayscale;\n\tu32 nonstd;\n\tu32 accel_flags;\n\tu32 rotate;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tconst struct fb_videomode *mode;\n};\n\nstruct fbcon_par {\n\tstruct fb_var_screeninfo var;\n\tstruct delayed_work cursor_work;\n\tstruct fb_cursor cursor_state;\n\tstruct fbcon_display *p;\n\tstruct fb_info *info;\n\tint currcon;\n\tint cur_blink_jiffies;\n\tint cursor_flash;\n\tint cursor_reset;\n\tint blank_state;\n\tint graphics;\n\tbool initialized;\n\tint rotate;\n\tint cur_rotate;\n\tchar *cursor_data;\n\tu8 *fontbuffer;\n\tu8 *fontdata;\n\tu8 *cursor_src;\n\tu32 cursor_size;\n\tu32 fd_size;\n\tconst struct fbcon_bitops *bitops;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[2];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct fentry_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct trace_seq;\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tbool is_signed;\n\tbool is_string;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct fexit_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int func;\n\tlong unsigned int ret_ip;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[2];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct fgraph_cpu_data {\n\tpid_t last_pid;\n\tint depth;\n\tint depth_irq;\n\tint ignore;\n\tlong unsigned int enter_funcs[50];\n};\n\nstruct ftrace_graph_ent {\n\tlong unsigned int func;\n\tlong int depth;\n};\n\nstruct ftrace_graph_ent_entry {\n\tstruct trace_entry ent;\n\tstruct ftrace_graph_ent graph_ent;\n\tlong unsigned int args[0];\n};\n\nstruct fgraph_ent_args {\n\tstruct ftrace_graph_ent_entry ent;\n\tlong unsigned int args[6];\n};\n\nstruct fgraph_retaddr_ent {\n\tstruct ftrace_graph_ent ent;\n\tlong unsigned int retaddr;\n};\n\nstruct fgraph_retaddr_ent_entry {\n\tstruct trace_entry ent;\n\tstruct fgraph_retaddr_ent graph_rent;\n\tlong unsigned int args[0];\n};\n\nstruct fgraph_retaddr_ent_args {\n\tstruct fgraph_retaddr_ent_entry ent;\n\tlong unsigned int args[6];\n};\n\nstruct ftrace_graph_ret {\n\tlong unsigned int func;\n\tlong unsigned int retval;\n\tint depth;\n\tunsigned int overrun;\n};\n\nstruct ftrace_graph_ret_entry {\n\tstruct trace_entry ent;\n\tstruct ftrace_graph_ret ret;\n\tlong long unsigned int calltime;\n\tlong long unsigned int rettime;\n};\n\nstruct fgraph_data {\n\tstruct fgraph_cpu_data *cpu_data;\n\tunion {\n\t\tstruct fgraph_ent_args ent;\n\t\tstruct fgraph_retaddr_ent_args rent;\n\t};\n\tstruct ftrace_graph_ret_entry ret;\n\tint failed;\n\tint cpu;\n};\n\nstruct fgraph_ops;\n\ntypedef int (*trace_func_graph_ent_t)(struct ftrace_graph_ent *, struct fgraph_ops *, struct ftrace_regs *);\n\ntypedef void (*trace_func_graph_ret_t)(struct ftrace_graph_ret *, struct fgraph_ops *, struct ftrace_regs *);\n\ntypedef void (*ftrace_func_t)(long unsigned int, long unsigned int, struct ftrace_ops *, struct ftrace_regs *);\n\nstruct ftrace_hash;\n\nstruct ftrace_ops_hash {\n\tstruct ftrace_hash *notrace_hash;\n\tstruct ftrace_hash *filter_hash;\n\tstruct mutex regex_lock;\n};\n\ntypedef int (*ftrace_ops_func_t)(struct ftrace_ops *, long unsigned int, enum ftrace_ops_cmd);\n\nstruct ftrace_ops {\n\tftrace_func_t func;\n\tstruct ftrace_ops *next;\n\tlong unsigned int flags;\n\tvoid *private;\n\tftrace_func_t saved_func;\n\tstruct ftrace_ops_hash local_hash;\n\tstruct ftrace_ops_hash *func_hash;\n\tstruct ftrace_ops_hash old_hash;\n\tlong unsigned int trampoline;\n\tlong unsigned int trampoline_size;\n\tstruct list_head list;\n\tstruct list_head subop_list;\n\tftrace_ops_func_t ops_func;\n\tstruct ftrace_ops *managed;\n\tlong unsigned int direct_call;\n};\n\nstruct fgraph_ops {\n\ttrace_func_graph_ent_t entryfunc;\n\ttrace_func_graph_ret_t retfunc;\n\tstruct ftrace_ops ops;\n\tvoid *private;\n\ttrace_func_graph_ent_t saved_func;\n\tint idx;\n};\n\nstruct fgraph_times {\n\tlong long unsigned int calltime;\n\tlong long unsigned int sleeptime;\n};\n\nstruct fib_kuid_range {\n\tkuid_t start;\n\tkuid_t end;\n};\n\nstruct fib_rule_port_range {\n\t__u16 start;\n\t__u16 end;\n};\n\nstruct fib_rule {\n\tstruct list_head list;\n\tint iifindex;\n\tint oifindex;\n\tu32 mark;\n\tu32 mark_mask;\n\tu32 flags;\n\tu32 table;\n\tu8 action;\n\tu8 l3mdev;\n\tu8 proto;\n\tu8 ip_proto;\n\tu32 target;\n\t__be64 tun_id;\n\tstruct fib_rule *ctarget;\n\tstruct net *fr_net;\n\trefcount_t refcnt;\n\tu32 pref;\n\tint suppress_ifgroup;\n\tint suppress_prefixlen;\n\tchar iifname[16];\n\tchar oifname[16];\n\tstruct fib_kuid_range uid_range;\n\tstruct fib_rule_port_range sport_range;\n\tstruct fib_rule_port_range dport_range;\n\tu16 sport_mask;\n\tu16 dport_mask;\n\tu8 iif_is_l3_master;\n\tu8 oif_is_l3_master;\n\tstruct callback_head rcu;\n};\n\nstruct fib4_rule {\n\tstruct fib_rule common;\n\tu8 dst_len;\n\tu8 src_len;\n\tdscp_t dscp;\n\tdscp_t dscp_mask;\n\tu8 dscp_full: 1;\n\t__be32 src;\n\t__be32 srcmask;\n\t__be32 dst;\n\t__be32 dstmask;\n\tu32 tclassid;\n};\n\nstruct fib6_node;\n\nstruct fib6_walker {\n\tstruct list_head lh;\n\tstruct fib6_node *root;\n\tstruct fib6_node *node;\n\tstruct fib6_info *leaf;\n\tenum fib6_walk_state state;\n\tunsigned int skip;\n\tunsigned int count;\n\tunsigned int skip_in_node;\n\tint (*func)(struct fib6_walker *);\n\tvoid *args;\n};\n\nstruct fib6_cleaner {\n\tstruct fib6_walker w;\n\tstruct net *net;\n\tint (*func)(struct fib6_info *, void *);\n\tint sernum;\n\tvoid *arg;\n\tbool skip_notify;\n};\n\nstruct nlmsghdr;\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct fib6_dump_arg {\n\tstruct net *net;\n\tstruct notifier_block *nb;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib6_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib6_info *rt;\n\tunsigned int nsiblings;\n};\n\nstruct fib6_gc_args {\n\tint timeout;\n\tint more;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tlong unsigned int last_probe;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_nh_age_excptn_arg {\n\tstruct fib6_gc_args *gc_args;\n\tlong unsigned int now;\n};\n\nstruct fib6_nh_del_cached_rt_arg {\n\tstruct fib6_config *cfg;\n\tstruct fib6_info *f6i;\n};\n\nstruct fib6_nh_dm_arg {\n\tstruct net *net;\n\tconst struct in6_addr *saddr;\n\tint oif;\n\tint flags;\n\tstruct fib6_nh *nh;\n};\n\nstruct rt6_rtnl_dump_arg;\n\nstruct fib6_nh_exception_dump_walker {\n\tstruct rt6_rtnl_dump_arg *dump;\n\tstruct fib6_info *rt;\n\tunsigned int flags;\n\tunsigned int skip;\n\tunsigned int count;\n};\n\nstruct fib6_nh_excptn_arg {\n\tstruct rt6_info *rt;\n\tint plen;\n};\n\nstruct fib6_nh_frl_arg {\n\tu32 flags;\n\tint oif;\n\tint strict;\n\tint *mpri;\n\tbool *do_rr;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_match_arg {\n\tconst struct net_device *dev;\n\tconst struct in6_addr *gw;\n\tstruct fib6_nh *match;\n};\n\nstruct fib6_result;\n\nstruct flowi6;\n\nstruct fib6_nh_rd_arg {\n\tstruct fib6_result *res;\n\tstruct flowi6 *fl6;\n\tconst struct in6_addr *gw;\n\tstruct rt6_info **ret;\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_node *subtree;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct fib6_rule {\n\tstruct fib_rule common;\n\tstruct rt6key src;\n\tstruct rt6key dst;\n\t__be32 flowlabel;\n\t__be32 flowlabel_mask;\n\tdscp_t dscp;\n\tdscp_t dscp_mask;\n\tu8 dscp_full: 1;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__u32 nh_tclassid;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_lookup_arg {\n\tvoid *lookup_ptr;\n\tconst void *lookup_data;\n\tvoid *result;\n\tstruct fib_rule *rule;\n\tu32 table;\n\tint flags;\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tloff_t pos;\n\tt_key key;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_rule_hdr {\n\t__u8 family;\n\t__u8 dst_len;\n\t__u8 src_len;\n\t__u8 tos;\n\t__u8 table;\n\t__u8 res1;\n\t__u8 res2;\n\t__u8 action;\n\t__u32 flags;\n};\n\nstruct fib_rule_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_rule *rule;\n};\n\nstruct fib_rule_uid_range {\n\t__u32 start;\n\t__u32 end;\n};\n\nstruct flowi;\n\nstruct fib_rules_ops {\n\tint family;\n\tstruct list_head list;\n\tint rule_size;\n\tint addr_size;\n\tint unresolved_rules;\n\tint nr_goto_rules;\n\tunsigned int fib_rules_seq;\n\tint (*action)(struct fib_rule *, struct flowi *, int, struct fib_lookup_arg *);\n\tbool (*suppress)(struct fib_rule *, int, struct fib_lookup_arg *);\n\tint (*match)(struct fib_rule *, struct flowi *, int);\n\tint (*configure)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*delete)(struct fib_rule *);\n\tint (*compare)(struct fib_rule *, struct fib_rule_hdr *, struct nlattr **);\n\tint (*fill)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *);\n\tsize_t (*nlmsg_payload)(struct fib_rule *);\n\tvoid (*flush_cache)(struct fib_rules_ops *);\n\tint nlgroup;\n\tstruct list_head rules_list;\n\tstruct module *owner;\n\tstruct net *fro_net;\n\tstruct callback_head rcu;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} __attribute__((packed)) i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct field_var {\n\tstruct hist_field *var;\n\tstruct hist_field *val;\n};\n\nstruct field_var_hist {\n\tstruct hist_trigger_data *hist_data;\n\tchar *cmd;\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_cache {\n\tstruct btrfs_fiemap_entry *entries;\n\tint entries_size;\n\tint entries_pos;\n\tu64 next_search_offset;\n\tunsigned int extents_mapped;\n\tu64 offset;\n\tu64 phys;\n\tu64 len;\n\tu32 flags;\n\tbool cached;\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_extent_cluster {\n\tu64 start;\n\tu64 end;\n\tu64 boundary[128];\n\tunsigned int nr;\n\tu64 owning_root;\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct tpm_chip;\n\nstruct tpm_space;\n\nstruct file_priv {\n\tstruct tpm_chip *chip;\n\tstruct tpm_space *space;\n\tstruct mutex buffer_mutex;\n\tstruct timer_list user_read_timer;\n\tstruct work_struct timeout_work;\n\tstruct work_struct async_work;\n\twait_queue_head_t async_wait;\n\tssize_t response_length;\n\tbool response_read;\n\tbool command_enqueued;\n\tu8 data_buffer[4096];\n};\n\nstruct file_private_info {\n\tloff_t offset;\n\tint act_area;\n\tint act_page;\n\tint act_entry;\n\tsize_t act_entry_offset;\n\tchar temp_buf[2048];\n\tdebug_info_t *debug_info_org;\n\tdebug_info_t *debug_info_snap;\n\tstruct debug_view *view;\n};\n\ntypedef struct file_private_info file_private_info_t;\n\nstruct file_range {\n\tconst struct path *path;\n\tloff_t pos;\n\tsize_t count;\n};\n\nstruct page_counter;\n\nstruct file_region {\n\tstruct list_head link;\n\tlong int from;\n\tlong int to;\n\tstruct page_counter *reservation_counter;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct file_security_struct {\n\tu32 sid;\n\tu32 fown_sid;\n\tu32 isid;\n\tu32 pseqno;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[168];\n};\n\nstruct filename_trans_datum {\n\tstruct ebitmap stypes;\n\tu32 otype;\n\tstruct filename_trans_datum *next;\n};\n\nstruct filename_trans_key {\n\tu32 ttype;\n\tu16 tclass;\n\tconst char *name;\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct filter_head {\n\tstruct list_head list;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rcu_work rwork;\n\t};\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct filter_match_data {\n\tconst char *filter;\n\tconst char *notfilter;\n\tsize_t index;\n\tsize_t size;\n\tlong unsigned int *addrs;\n\tstruct module **mods;\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\nstruct regex;\n\nstruct ftrace_event_field;\n\nstruct filter_pred {\n\tstruct regex *regex;\n\tstruct cpumask *mask;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tu64 val;\n\tu64 val2;\n\tenum filter_pred_fn fn_num;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nstruct find_free_extent_ctl {\n\tu64 ram_bytes;\n\tu64 num_bytes;\n\tu64 min_alloc_size;\n\tu64 empty_size;\n\tu64 flags;\n\tu64 search_start;\n\tu64 empty_cluster;\n\tstruct btrfs_free_cluster *last_ptr;\n\tbool use_cluster;\n\tbool delalloc;\n\tbool have_caching_bg;\n\tbool orig_have_caching_bg;\n\tbool for_treelog;\n\tbool for_data_reloc;\n\tbool retry_uncached;\n\tbool hinted;\n\tint index;\n\tint loop;\n\tint cached;\n\tu64 max_extent_size;\n\tu64 total_free_space;\n\tu64 found_offset;\n\tu64 hint_byte;\n\tenum btrfs_extent_allocation_policy policy;\n\tenum btrfs_block_group_size_class size_class;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct find_xattr_ctx {\n\tconst char *name;\n\tint name_len;\n\tint found_idx;\n\tchar *found_data;\n\tint found_data_len;\n\tbool copy_data;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct flag_settings {\n\tunsigned int flags;\n\tunsigned int mask;\n};\n\nstruct flags_map {\n\tunsigned int in_mask;\n\tunsigned int out_mask;\n};\n\nstruct flagsbuf {\n\tchar buf[9];\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct flow_action_police {\n\tu32 burst;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n};\n\nstruct nf_flowtable;\n\nstruct ip_tunnel_info;\n\nstruct psample_group;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 0;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct page_pool;\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t\tlong unsigned int memcg_data;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tatomic_t _entire_mapcount;\n\t\t\t\t\tatomic_t _pincount;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t\tunsigned int _nr_pages;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_or_pfn {\n\tunion {\n\t\tstruct folio *folio;\n\t\tlong unsigned int pfn;\n\t};\n\tbool is_folio;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct font_data {\n\tunsigned int extra[4];\n\tconst unsigned char data[0];\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tconst void *data;\n\tint pref;\n};\n\nstruct memory_block;\n\ntypedef int (*walk_memory_blocks_func_t)(struct memory_block *, void *);\n\nstruct for_each_memory_block_cb_data {\n\twalk_memory_blocks_func_t func;\n\tvoid *arg;\n};\n\nstruct fork_proc_event {\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n\t__kernel_pid_t child_pid;\n\t__kernel_pid_t child_tgid;\n};\n\nstruct format_data_t {\n\tunsigned int start_unit;\n\tunsigned int stop_unit;\n\tunsigned int blksize;\n\tunsigned int intensity;\n};\n\nstruct format_check_t {\n\tstruct format_data_t expect;\n\tunsigned int result;\n\tunsigned int unit;\n\tunsigned int rec;\n\tunsigned int num_records;\n\tunsigned int blksize;\n\tunsigned int key_length;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fprobe_addr_list {\n\tint index;\n\tint size;\n\tlong unsigned int *addrs;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct fprobe_hlist_node {\n\tstruct rhlist_head hlist;\n\tlong unsigned int addr;\n\tstruct fprobe *fp;\n};\n\nstruct fprobe_hlist {\n\tstruct hlist_node hlist;\n\tstruct callback_head rcu;\n\tstruct fprobe *fp;\n\tint size;\n\tstruct fprobe_hlist_node array[0];\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\nstruct fpu {\n\tu32 fpc;\n\t__vector128 vxrs[32];\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhashtable rhashtable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct frag_queue {\n\tstruct inet_frag_queue q;\n\tint iif;\n\t__u16 nhoffset;\n\tu8 ecn;\n};\n\nstruct free_area {\n\tstruct list_head free_list[6];\n\tlong unsigned int nr_free;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t\tshort unsigned int stride;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tfreelist_full_t freelist_counters;\n\t};\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n};\n\nstruct raw3270;\n\nstruct raw3270_fn;\n\nstruct raw3270_view {\n\tstruct list_head list;\n\tspinlock_t lock;\n\tatomic_t ref_count;\n\tstruct raw3270 *dev;\n\tstruct raw3270_fn *fn;\n\tunsigned int model;\n\tunsigned int rows;\n\tunsigned int cols;\n\tunsigned char *ascebc;\n};\n\nstruct raw3270_request;\n\nstruct idal_buffer;\n\nstruct fs3270 {\n\tstruct raw3270_view view;\n\tstruct pid *fs_pid;\n\tint read_command;\n\tint write_command;\n\tint attention;\n\tint active;\n\tstruct raw3270_request *init;\n\twait_queue_head_t wait;\n\tstruct idal_buffer *rdbuf;\n\tsize_t rdbuf_size;\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_disk_quota {\n\t__s8 d_version;\n\t__s8 d_flags;\n\t__u16 d_fieldmask;\n\t__u32 d_id;\n\t__u64 d_blk_hardlimit;\n\t__u64 d_blk_softlimit;\n\t__u64 d_ino_hardlimit;\n\t__u64 d_ino_softlimit;\n\t__u64 d_bcount;\n\t__u64 d_icount;\n\t__s32 d_itimer;\n\t__s32 d_btimer;\n\t__u16 d_iwarns;\n\t__u16 d_bwarns;\n\t__s8 d_itimer_hi;\n\t__s8 d_btimer_hi;\n\t__s8 d_rtbtimer_hi;\n\t__s8 d_padding2;\n\t__u64 d_rtb_hardlimit;\n\t__u64 d_rtb_softlimit;\n\t__u64 d_rtbcount;\n\t__s32 d_rtbtimer;\n\t__u16 d_rtbwarns;\n\t__s16 d_padding3;\n\tchar d_padding4[8];\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_path {\n\tstruct __fs_path;\n\tchar inline_buf[224];\n};\n\nstruct fs_qfilestat {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n};\n\ntypedef struct fs_qfilestat fs_qfilestat_t;\n\nstruct fs_qfilestatv {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n\t__u32 qfs_pad;\n};\n\nstruct fs_quota_stat {\n\t__s8 qs_version;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tfs_qfilestat_t qs_uquota;\n\tfs_qfilestat_t qs_gquota;\n\t__u32 qs_incoredqs;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n};\n\nstruct fs_quota_statv {\n\t__s8 qs_version;\n\t__u8 qs_pad1;\n\t__u16 qs_flags;\n\t__u32 qs_incoredqs;\n\tstruct fs_qfilestatv qs_uquota;\n\tstruct fs_qfilestatv qs_gquota;\n\tstruct fs_qfilestatv qs_pquota;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n\t__u16 qs_rtbwarnlimit;\n\t__u16 qs_pad3;\n\t__u32 qs_pad4;\n\t__u64 qs_pad2[7];\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fscrypt_key_specifier {\n\t__u32 type;\n\t__u32 __reserved;\n\tunion {\n\t\t__u8 __reserved[32];\n\t\t__u8 descriptor[8];\n\t\t__u8 identifier[16];\n\t} u;\n};\n\nstruct fscrypt_add_key_arg {\n\tstruct fscrypt_key_specifier key_spec;\n\t__u32 raw_size;\n\t__u32 key_id;\n\t__u32 flags;\n\t__u32 __reserved[7];\n\t__u8 raw[0];\n};\n\nstruct fscrypt_context_v1 {\n\tu8 version;\n\tu8 contents_encryption_mode;\n\tu8 filenames_encryption_mode;\n\tu8 flags;\n\tu8 master_key_descriptor[8];\n\tu8 nonce[16];\n};\n\nstruct fscrypt_context_v2 {\n\tu8 version;\n\tu8 contents_encryption_mode;\n\tu8 filenames_encryption_mode;\n\tu8 flags;\n\tu8 log2_data_unit_size;\n\tu8 __reserved[3];\n\tu8 master_key_identifier[16];\n\tu8 nonce[16];\n};\n\nunion fscrypt_context {\n\tu8 version;\n\tstruct fscrypt_context_v1 v1;\n\tstruct fscrypt_context_v2 v2;\n};\n\nstruct fscrypt_prepared_key {\n\tstruct crypto_sync_skcipher *tfm;\n};\n\nstruct fscrypt_mode;\n\nstruct fscrypt_direct_key {\n\tstruct super_block *dk_sb;\n\tstruct hlist_node dk_node;\n\trefcount_t dk_refcount;\n\tconst struct fscrypt_mode *dk_mode;\n\tstruct fscrypt_prepared_key dk_key;\n\tu8 dk_descriptor[8];\n\tu8 dk_raw[64];\n};\n\nstruct fscrypt_get_key_status_arg {\n\tstruct fscrypt_key_specifier key_spec;\n\t__u32 __reserved[6];\n\t__u32 status;\n\t__u32 status_flags;\n\t__u32 user_count;\n\t__u32 __out_reserved[13];\n};\n\nstruct fscrypt_policy_v1 {\n\t__u8 version;\n\t__u8 contents_encryption_mode;\n\t__u8 filenames_encryption_mode;\n\t__u8 flags;\n\t__u8 master_key_descriptor[8];\n};\n\nstruct fscrypt_policy_v2 {\n\t__u8 version;\n\t__u8 contents_encryption_mode;\n\t__u8 filenames_encryption_mode;\n\t__u8 flags;\n\t__u8 log2_data_unit_size;\n\t__u8 __reserved[3];\n\t__u8 master_key_identifier[16];\n};\n\nstruct fscrypt_get_policy_ex_arg {\n\t__u64 policy_size;\n\tunion {\n\t\t__u8 version;\n\t\tstruct fscrypt_policy_v1 v1;\n\t\tstruct fscrypt_policy_v2 v2;\n\t} policy;\n};\n\nunion fscrypt_policy {\n\tu8 version;\n\tstruct fscrypt_policy_v1 v1;\n\tstruct fscrypt_policy_v2 v2;\n};\n\nstruct fscrypt_master_key;\n\nstruct fscrypt_inode_info {\n\tstruct fscrypt_prepared_key ci_enc_key;\n\tu8 ci_owns_key: 1;\n\tu8 ci_dirhash_key_initialized: 1;\n\tu8 ci_data_unit_bits;\n\tu8 ci_data_units_per_block_bits;\n\tu32 ci_hashed_ino;\n\tstruct fscrypt_mode *ci_mode;\n\tstruct inode *ci_inode;\n\tstruct fscrypt_master_key *ci_master_key;\n\tstruct list_head ci_master_key_link;\n\tstruct fscrypt_direct_key *ci_direct_key;\n\tsiphash_key_t ci_dirhash_key;\n\tunion fscrypt_policy ci_policy;\n\tu8 ci_nonce[16];\n};\n\nunion fscrypt_iv {\n\tstruct {\n\t\t__le64 index;\n\t\tu8 nonce[16];\n\t};\n\tu8 raw[32];\n\t__le64 dun[4];\n};\n\nstruct fscrypt_key {\n\t__u32 mode;\n\t__u8 raw[64];\n\t__u32 size;\n};\n\nstruct fscrypt_keyring {\n\tspinlock_t lock;\n\tstruct hlist_head key_hashtable[128];\n};\n\nstruct hmac_sha512_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct fscrypt_master_key_secret {\n\tstruct hmac_sha512_key hkdf;\n\tbool is_hw_wrapped;\n\tu32 size;\n\tu8 bytes[128];\n};\n\nstruct fscrypt_master_key {\n\tstruct hlist_node mk_node;\n\tstruct rw_semaphore mk_sem;\n\trefcount_t mk_active_refs;\n\trefcount_t mk_struct_refs;\n\tstruct callback_head mk_rcu_head;\n\tstruct fscrypt_master_key_secret mk_secret;\n\tstruct fscrypt_key_specifier mk_spec;\n\tstruct key *mk_users;\n\tstruct list_head mk_decrypted_inodes;\n\tspinlock_t mk_decrypted_inodes_lock;\n\tstruct fscrypt_prepared_key mk_direct_keys[11];\n\tstruct fscrypt_prepared_key mk_iv_ino_lblk_64_keys[11];\n\tstruct fscrypt_prepared_key mk_iv_ino_lblk_32_keys[11];\n\tsiphash_key_t mk_ino_hash_key;\n\tbool mk_ino_hash_key_initialized;\n\tbool mk_present;\n};\n\nstruct fscrypt_mode {\n\tconst char *friendly_name;\n\tconst char *cipher_str;\n\tint keysize;\n\tint security_strength;\n\tint ivsize;\n\tint logged_cryptoapi_impl;\n\tint logged_blk_crypto_native;\n\tint logged_blk_crypto_fallback;\n\tenum blk_crypto_mode_num blk_crypto_mode;\n};\n\nstruct fscrypt_nokey_name {\n\tu32 dirhash[2];\n\tu8 bytes[149];\n\tu8 sha256[32];\n};\n\nstruct fscrypt_operations {\n\tptrdiff_t inode_info_offs;\n\tunsigned int needs_bounce_pages: 1;\n\tunsigned int has_32bit_inodes: 1;\n\tunsigned int supports_subblock_data_units: 1;\n\tconst char *legacy_key_prefix;\n\tint (*get_context)(struct inode *, void *, size_t);\n\tint (*set_context)(struct inode *, const void *, size_t, void *);\n\tconst union fscrypt_policy * (*get_dummy_policy)(struct super_block *);\n\tbool (*empty_dir)(struct inode *);\n\tbool (*has_stable_inodes)(struct super_block *);\n\tstruct block_device ** (*get_devices)(struct super_block *, unsigned int *);\n};\n\nstruct fscrypt_provisioning_key_payload {\n\t__u32 type;\n\t__u32 flags;\n\t__u8 raw[0];\n};\n\nstruct fscrypt_remove_key_arg {\n\tstruct fscrypt_key_specifier key_spec;\n\t__u32 removal_status_flags;\n\t__u32 __reserved[5];\n};\n\nstruct fscrypt_symlink_data {\n\t__le16 len;\n\tchar encrypted_path[0];\n};\n\nstruct fscrypt_zero_done {\n\tatomic_t pending;\n\tblk_status_t status;\n\tstruct completion done;\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_io;\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu32 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n\tconst char *driver_override;\n};\n\nstruct fsl_mc_resource_pool;\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tunsigned int virq;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\traw_spinlock_t spinlock;\n\t};\n};\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\ntypedef struct fsnotify_group *class_fsnotify_group_t;\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t\tstruct fanotify_group_private_data fanotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct fsuuid {\n\t__u32 fsu_len;\n\t__u32 fsu_flags;\n\t__u8 fsu_uuid[0];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsverity_descriptor {\n\t__u8 version;\n\t__u8 hash_algorithm;\n\t__u8 log_blocksize;\n\t__u8 salt_size;\n\t__le32 sig_size;\n\t__le64 data_size;\n\t__u8 root_hash[64];\n\t__u8 salt[32];\n\t__u8 __reserved[144];\n\t__u8 signature[0];\n};\n\nstruct fsverity_digest {\n\t__u16 digest_algorithm;\n\t__u16 digest_size;\n\t__u8 digest[0];\n};\n\nstruct fsverity_enable_arg {\n\t__u32 version;\n\t__u32 hash_algorithm;\n\t__u32 block_size;\n\t__u32 salt_size;\n\t__u64 salt_ptr;\n\t__u32 sig_size;\n\t__u32 __reserved1;\n\t__u64 sig_ptr;\n\t__u64 __reserved2[11];\n};\n\nstruct fsverity_formatted_digest {\n\tchar magic[8];\n\t__le16 digest_algorithm;\n\t__le16 digest_size;\n\t__u8 digest[0];\n};\n\nstruct fsverity_hash_alg {\n\tconst char *name;\n\tunsigned int digest_size;\n\tunsigned int block_size;\n\tenum hash_algo algo_id;\n};\n\nstruct sha512_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nunion fsverity_hash_ctx {\n\tstruct sha256_ctx sha256;\n\tstruct sha512_ctx sha512;\n};\n\nstruct merkle_tree_params {\n\tconst struct fsverity_hash_alg *hash_alg;\n\tconst union fsverity_hash_ctx *hashstate;\n\tunsigned int digest_size;\n\tunsigned int block_size;\n\tunsigned int hashes_per_block;\n\tunsigned int blocks_per_page;\n\tu8 log_digestsize;\n\tu8 log_blocksize;\n\tu8 log_arity;\n\tu8 log_blocks_per_page;\n\tunsigned int num_levels;\n\tu64 tree_size;\n\tlong unsigned int tree_pages;\n\tlong unsigned int level_start[8];\n};\n\nstruct fsverity_info {\n\tstruct rhash_head rhash_head;\n\tstruct merkle_tree_params tree_params;\n\tu8 root_hash[64];\n\tu8 file_digest[64];\n\tstruct inode *inode;\n\tlong unsigned int *hash_block_verified;\n};\n\nstruct fsverity_operations {\n\tint (*begin_enable_verity)(struct file *);\n\tint (*end_enable_verity)(struct file *, const void *, size_t, u64);\n\tint (*get_verity_descriptor)(struct inode *, void *, size_t);\n\tstruct page * (*read_merkle_tree_page)(struct inode *, long unsigned int);\n\tvoid (*readahead_merkle_tree)(struct inode *, long unsigned int, long unsigned int);\n\tint (*write_merkle_tree_block)(struct file *, const void *, u64, unsigned int);\n};\n\nstruct fsverity_pending_block {\n\tconst void *data;\n\tu64 pos;\n\tu8 real_hash[64];\n};\n\nstruct fsverity_read_metadata_arg {\n\t__u64 metadata_type;\n\t__u64 offset;\n\t__u64 length;\n\t__u64 buf_ptr;\n\t__u64 __reserved;\n};\n\nstruct fsverity_verification_context {\n\tstruct fsverity_info *vi;\n\tint num_pending;\n\tint max_pending;\n\tstruct fsverity_pending_block pending_blocks[2];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8156];\n};\n\nstruct tracer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tchar *fmt;\n\tunsigned int fmt_size;\n\tatomic_t wait_index;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool closed;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int spare_size;\n\tunsigned int read;\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int args[0];\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tunsigned int is_signed: 1;\n\tunsigned int needs_test: 1;\n\tint len;\n};\n\nstruct ftrace_func_command {\n\tstruct list_head list;\n\tchar *name;\n\tint (*func)(struct trace_array *, struct ftrace_hash *, char *, char *, char *, int);\n};\n\nstruct ftrace_func_entry {\n\tstruct hlist_node hlist;\n\tlong unsigned int ip;\n\tlong unsigned int direct;\n};\n\nstruct ftrace_func_map {\n\tstruct ftrace_func_entry entry;\n\tvoid *data;\n};\n\nstruct ftrace_hash {\n\tlong unsigned int size_bits;\n\tstruct hlist_head *buckets;\n\tlong unsigned int count;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct ftrace_func_mapper {\n\tstruct ftrace_hash hash;\n};\n\nstruct ftrace_probe_ops;\n\nstruct ftrace_func_probe {\n\tstruct ftrace_probe_ops *probe_ops;\n\tstruct ftrace_ops ops;\n\tstruct trace_array *tr;\n\tstruct list_head list;\n\tvoid *data;\n\tint ref;\n};\n\nstruct ftrace_glob {\n\tchar *search;\n\tunsigned int len;\n\tint type;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tbool fail;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nstruct ftrace_graph_data {\n\tstruct ftrace_hash *hash;\n\tstruct ftrace_func_entry *entry;\n\tint idx;\n\tenum graph_filter_type type;\n\tstruct ftrace_hash *new_hash;\n\tconst struct seq_operations *seq_ops;\n\tstruct trace_parser parser;\n};\n\nstruct ftrace_hotpatch_trampoline {\n\tu16 brasl_opc;\n\ts32 brasl_disp;\n\tlong: 0;\n\tu64 rest_of_intercepted_function;\n\tu64 interceptor;\n} __attribute__((packed));\n\nstruct ftrace_init_func {\n\tstruct list_head list;\n\tlong unsigned int ip;\n};\n\nstruct ftrace_insn {\n\tu16 opc;\n\ts32 disp;\n} __attribute__((packed));\n\nstruct ftrace_page;\n\nstruct ftrace_iterator {\n\tloff_t pos;\n\tloff_t func_pos;\n\tloff_t mod_pos;\n\tstruct ftrace_page *pg;\n\tstruct dyn_ftrace *func;\n\tstruct ftrace_func_probe *probe;\n\tstruct ftrace_func_entry *probe_entry;\n\tstruct trace_parser parser;\n\tstruct ftrace_hash *hash;\n\tstruct ftrace_ops *ops;\n\tstruct trace_array *tr;\n\tstruct list_head *mod_list;\n\tint pidx;\n\tint idx;\n\tunsigned int flags;\n};\n\nstruct ftrace_mod_func {\n\tstruct list_head list;\n\tchar *name;\n\tlong unsigned int ip;\n\tunsigned int size;\n};\n\nstruct ftrace_mod_load {\n\tstruct list_head list;\n\tchar *func;\n\tchar *module;\n\tint enable;\n};\n\nstruct ftrace_mod_map {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct module *mod;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tstruct list_head funcs;\n\tunsigned int num_funcs;\n};\n\nstruct ftrace_page {\n\tstruct ftrace_page *next;\n\tstruct dyn_ftrace *records;\n\tint index;\n\tint order;\n};\n\nstruct ftrace_probe_ops {\n\tvoid (*func)(long unsigned int, long unsigned int, struct trace_array *, struct ftrace_probe_ops *, void *);\n\tint (*init)(struct ftrace_probe_ops *, struct trace_array *, long unsigned int, void *, void **);\n\tvoid (*free)(struct ftrace_probe_ops *, struct trace_array *, long unsigned int, void *);\n\tint (*print)(struct seq_file *, long unsigned int, struct ftrace_probe_ops *, void *);\n};\n\nstruct ftrace_profile {\n\tstruct hlist_node node;\n\tlong unsigned int ip;\n\tlong unsigned int counter;\n\tlong long unsigned int time;\n\tlong long unsigned int time_squared;\n};\n\nstruct ftrace_profile_page {\n\tstruct ftrace_profile_page *next;\n\tlong unsigned int index;\n\tstruct ftrace_profile records[0];\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct ftrace_profile_stat {\n\tatomic_t disabled;\n\tstruct hlist_head *hash;\n\tstruct ftrace_profile_page *pages;\n\tstruct ftrace_profile_page *start;\n\tstruct tracer_stat stat;\n};\n\nstruct ftrace_rec_iter {\n\tstruct ftrace_page *pg;\n\tint index;\n};\n\nstruct ftrace_regs {};\n\nstruct ftrace_ret_stack {\n\tlong unsigned int ret;\n\tlong unsigned int func;\n\tlong unsigned int *retp;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct func_repeats_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu16 count;\n\tu16 top_delta_ts;\n\tu32 bottom_delta_ts;\n};\n\nstruct function_filter_data {\n\tstruct ftrace_ops *ops;\n\tint first_filter;\n\tint first_notrace;\n};\n\nstruct fuse_access_in {\n\tuint32_t mask;\n\tuint32_t padding;\n};\n\nstruct fuse_arg {\n\tunsigned int size;\n\tvoid *value;\n};\n\nstruct fuse_in_arg {\n\tunsigned int size;\n\tconst void *value;\n};\n\nstruct fuse_mount;\n\nstruct fuse_args {\n\tuint64_t nodeid;\n\tuint32_t opcode;\n\tuint8_t in_numargs;\n\tuint8_t out_numargs;\n\tuint8_t ext_idx;\n\tbool force: 1;\n\tbool noreply: 1;\n\tbool nocreds: 1;\n\tbool in_pages: 1;\n\tbool out_pages: 1;\n\tbool user_pages: 1;\n\tbool out_argvar: 1;\n\tbool page_zeroing: 1;\n\tbool page_replace: 1;\n\tbool may_block: 1;\n\tbool is_ext: 1;\n\tbool is_pinned: 1;\n\tbool invalidate_vmap: 1;\n\tstruct fuse_in_arg in_args[4];\n\tstruct fuse_arg out_args[2];\n\tvoid (*end)(struct fuse_mount *, struct fuse_args *, int);\n\tvoid *vmap_base;\n};\n\nstruct fuse_folio_desc;\n\nstruct fuse_args_pages {\n\tstruct fuse_args args;\n\tstruct folio **folios;\n\tstruct fuse_folio_desc *descs;\n\tunsigned int num_folios;\n};\n\nstruct fuse_attr {\n\tuint64_t ino;\n\tuint64_t size;\n\tuint64_t blocks;\n\tuint64_t atime;\n\tuint64_t mtime;\n\tuint64_t ctime;\n\tuint32_t atimensec;\n\tuint32_t mtimensec;\n\tuint32_t ctimensec;\n\tuint32_t mode;\n\tuint32_t nlink;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t rdev;\n\tuint32_t blksize;\n\tuint32_t flags;\n};\n\nstruct fuse_attr_out {\n\tuint64_t attr_valid;\n\tuint32_t attr_valid_nsec;\n\tuint32_t dummy;\n\tstruct fuse_attr attr;\n};\n\nstruct fuse_backing {\n\tstruct file *file;\n\tstruct cred *cred;\n\trefcount_t count;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_backing_map {\n\tint32_t fd;\n\tuint32_t flags;\n\tuint64_t padding;\n};\n\nstruct fuse_batch_forget_in {\n\tuint32_t count;\n\tuint32_t dummy;\n};\n\nstruct fuse_bmap_in {\n\tuint64_t block;\n\tuint32_t blocksize;\n\tuint32_t padding;\n};\n\nstruct fuse_bmap_out {\n\tuint64_t block;\n};\n\nstruct fuse_forget_one {\n\tuint64_t nodeid;\n\tuint64_t nlookup;\n};\n\nstruct fuse_forget_link {\n\tstruct fuse_forget_one forget_one;\n\tstruct fuse_forget_link *next;\n};\n\nstruct fuse_iqueue_ops;\n\nstruct fuse_iqueue {\n\tunsigned int connected;\n\tspinlock_t lock;\n\twait_queue_head_t waitq;\n\tu64 reqctr;\n\tstruct list_head pending;\n\tstruct list_head interrupts;\n\tstruct fuse_forget_link forget_list_head;\n\tstruct fuse_forget_link *forget_list_tail;\n\tint forget_batch;\n\tstruct fasync_struct *fasync;\n\tconst struct fuse_iqueue_ops *ops;\n\tvoid *priv;\n};\n\nstruct fuse_conn_dax;\n\nstruct fuse_sync_bucket;\n\nstruct fuse_ring;\n\nstruct fuse_conn {\n\tspinlock_t lock;\n\trefcount_t count;\n\tatomic_t dev_count;\n\tatomic_t epoch;\n\tstruct work_struct epoch_work;\n\tstruct callback_head rcu;\n\tkuid_t user_id;\n\tkgid_t group_id;\n\tstruct pid_namespace *pid_ns;\n\tstruct user_namespace *user_ns;\n\tunsigned int max_read;\n\tunsigned int max_write;\n\tunsigned int max_pages;\n\tunsigned int max_pages_limit;\n\tstruct fuse_iqueue iq;\n\tatomic64_t khctr;\n\tstruct rb_root polled_files;\n\tunsigned int max_background;\n\tunsigned int congestion_threshold;\n\tunsigned int num_background;\n\tunsigned int active_background;\n\tstruct list_head bg_queue;\n\tspinlock_t bg_lock;\n\tint initialized;\n\tint blocked;\n\twait_queue_head_t blocked_waitq;\n\tunsigned int connected;\n\tbool aborted;\n\tunsigned int conn_error: 1;\n\tunsigned int conn_init: 1;\n\tunsigned int async_read: 1;\n\tunsigned int abort_err: 1;\n\tunsigned int atomic_o_trunc: 1;\n\tunsigned int export_support: 1;\n\tunsigned int writeback_cache: 1;\n\tunsigned int parallel_dirops: 1;\n\tunsigned int handle_killpriv: 1;\n\tunsigned int cache_symlinks: 1;\n\tunsigned int legacy_opts_show: 1;\n\tunsigned int handle_killpriv_v2: 1;\n\tunsigned int no_open: 1;\n\tunsigned int no_opendir: 1;\n\tunsigned int no_fsync: 1;\n\tunsigned int no_fsyncdir: 1;\n\tunsigned int no_flush: 1;\n\tunsigned int no_setxattr: 1;\n\tunsigned int setxattr_ext: 1;\n\tunsigned int no_getxattr: 1;\n\tunsigned int no_listxattr: 1;\n\tunsigned int no_removexattr: 1;\n\tunsigned int no_lock: 1;\n\tunsigned int no_access: 1;\n\tunsigned int no_create: 1;\n\tunsigned int no_interrupt: 1;\n\tunsigned int no_bmap: 1;\n\tunsigned int no_poll: 1;\n\tunsigned int big_writes: 1;\n\tunsigned int dont_mask: 1;\n\tunsigned int no_flock: 1;\n\tunsigned int no_fallocate: 1;\n\tunsigned int no_rename2: 1;\n\tunsigned int auto_inval_data: 1;\n\tunsigned int explicit_inval_data: 1;\n\tunsigned int do_readdirplus: 1;\n\tunsigned int readdirplus_auto: 1;\n\tunsigned int async_dio: 1;\n\tunsigned int no_lseek: 1;\n\tunsigned int posix_acl: 1;\n\tunsigned int default_permissions: 1;\n\tunsigned int allow_other: 1;\n\tunsigned int no_copy_file_range: 1;\n\tunsigned int no_copy_file_range_64: 1;\n\tunsigned int destroy: 1;\n\tunsigned int delete_stale: 1;\n\tunsigned int no_control: 1;\n\tunsigned int no_force_umount: 1;\n\tunsigned int auto_submounts: 1;\n\tunsigned int sync_fs: 1;\n\tunsigned int init_security: 1;\n\tunsigned int create_supp_group: 1;\n\tunsigned int inode_dax: 1;\n\tunsigned int no_tmpfile: 1;\n\tunsigned int direct_io_allow_mmap: 1;\n\tunsigned int no_statx: 1;\n\tunsigned int passthrough: 1;\n\tunsigned int use_pages_for_kvec_io: 1;\n\tunsigned int no_link: 1;\n\tunsigned int sync_init: 1;\n\tunsigned int io_uring;\n\tint max_stack_depth;\n\tatomic_t num_waiting;\n\tunsigned int minor;\n\tstruct list_head entry;\n\tdev_t dev;\n\tu32 scramble_key[4];\n\tatomic64_t attr_version;\n\tatomic64_t evict_ctr;\n\tu32 name_max;\n\tvoid (*release)(struct fuse_conn *);\n\tstruct rw_semaphore killsb;\n\tstruct list_head devices;\n\tenum fuse_dax_mode dax_mode;\n\tstruct fuse_conn_dax *dax;\n\tstruct list_head mounts;\n\tstruct fuse_sync_bucket *curr_bucket;\n\tstruct idr backing_files_map;\n\tstruct fuse_ring *ring;\n\tstruct {\n\t\tstruct delayed_work work;\n\t\tunsigned int req_timeout;\n\t} timeout;\n};\n\nstruct fuse_conn_dax {\n\tstruct dax_device *dev;\n\tspinlock_t lock;\n\tlong unsigned int nr_busy_ranges;\n\tstruct list_head busy_ranges;\n\tstruct delayed_work free_work;\n\twait_queue_head_t range_waitq;\n\tlong int nr_free_ranges;\n\tstruct list_head free_ranges;\n\tlong unsigned int nr_ranges;\n};\n\nstruct fuse_copy_file_range_in {\n\tuint64_t fh_in;\n\tuint64_t off_in;\n\tuint64_t nodeid_out;\n\tuint64_t fh_out;\n\tuint64_t off_out;\n\tuint64_t len;\n\tuint64_t flags;\n};\n\nstruct fuse_copy_file_range_out {\n\tuint64_t bytes_copied;\n};\n\nstruct fuse_req;\n\nstruct pipe_buffer;\n\nstruct fuse_copy_state {\n\tstruct fuse_req *req;\n\tstruct iov_iter *iter;\n\tstruct pipe_buffer *pipebufs;\n\tstruct pipe_buffer *currbuf;\n\tstruct pipe_inode_info *pipe;\n\tlong unsigned int nr_segs;\n\tstruct page *pg;\n\tunsigned int len;\n\tunsigned int offset;\n\tbool write: 1;\n\tbool move_folios: 1;\n\tbool is_uring: 1;\n\tstruct {\n\t\tunsigned int copied_sz;\n\t} ring;\n};\n\nstruct fuse_create_in {\n\tuint32_t flags;\n\tuint32_t mode;\n\tuint32_t umask;\n\tuint32_t open_flags;\n};\n\nstruct interval_tree_node {\n\tstruct rb_node rb;\n\tlong unsigned int start;\n\tlong unsigned int last;\n\tlong unsigned int __subtree_last;\n};\n\nstruct fuse_dax_mapping {\n\tstruct inode *inode;\n\tstruct list_head list;\n\tstruct interval_tree_node itn;\n\tstruct list_head busy_list;\n\tu64 window_offset;\n\tloff_t length;\n\tbool writable;\n\trefcount_t refcnt;\n};\n\nstruct fuse_dentry {\n\tu64 time;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rb_node node;\n\t};\n\tstruct dentry *dentry;\n};\n\nstruct fuse_pqueue {\n\tunsigned int connected;\n\tspinlock_t lock;\n\tstruct list_head *processing;\n\tstruct list_head io;\n};\n\nstruct fuse_dev {\n\tstruct fuse_conn *fc;\n\tstruct fuse_pqueue pq;\n\tstruct list_head entry;\n};\n\nstruct fuse_dirent {\n\tuint64_t ino;\n\tuint64_t off;\n\tuint32_t namelen;\n\tuint32_t type;\n\tchar name[0];\n};\n\nstruct fuse_entry_out {\n\tuint64_t nodeid;\n\tuint64_t generation;\n\tuint64_t entry_valid;\n\tuint64_t attr_valid;\n\tuint32_t entry_valid_nsec;\n\tuint32_t attr_valid_nsec;\n\tstruct fuse_attr attr;\n};\n\nstruct fuse_direntplus {\n\tstruct fuse_entry_out entry_out;\n\tstruct fuse_dirent dirent;\n};\n\nstruct fuse_ext_header {\n\tuint32_t size;\n\tuint32_t type;\n};\n\nstruct fuse_fallocate_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint64_t length;\n\tuint32_t mode;\n\tuint32_t padding;\n};\n\nunion fuse_file_args;\n\nstruct fuse_file {\n\tstruct fuse_mount *fm;\n\tunion fuse_file_args *args;\n\tu64 kh;\n\tu64 fh;\n\tu64 nodeid;\n\trefcount_t count;\n\tu32 open_flags;\n\tstruct list_head write_entry;\n\tstruct {\n\t\tloff_t pos;\n\t\tloff_t cache_off;\n\t\tu64 version;\n\t} readdir;\n\tstruct rb_node polled_node;\n\twait_queue_head_t poll_wait;\n\tenum {\n\t\tIOM_NONE = 0,\n\t\tIOM_CACHED = 1,\n\t\tIOM_UNCACHED = 2,\n\t} iomode;\n\tstruct file *passthrough;\n\tconst struct cred *cred;\n\tbool flock: 1;\n};\n\nstruct fuse_open_out {\n\tuint64_t fh;\n\tuint32_t open_flags;\n\tint32_t backing_id;\n};\n\nstruct fuse_release_in {\n\tuint64_t fh;\n\tuint32_t flags;\n\tuint32_t release_flags;\n\tuint64_t lock_owner;\n};\n\nstruct fuse_release_args {\n\tstruct fuse_args args;\n\tstruct fuse_release_in inarg;\n\tstruct inode *inode;\n};\n\nunion fuse_file_args {\n\tstruct fuse_open_out open_outarg;\n\tstruct fuse_release_args release_args;\n};\n\nstruct fuse_file_lock {\n\tuint64_t start;\n\tuint64_t end;\n\tuint32_t type;\n\tuint32_t pid;\n};\n\nstruct fuse_io_args;\n\nstruct fuse_fill_read_data {\n\tstruct file *file;\n\tstruct fuse_conn *fc;\n\tstruct fuse_io_args *ia;\n\tunsigned int nr_bytes;\n};\n\nstruct fuse_writepage_args;\n\nstruct fuse_fill_wb_data {\n\tstruct fuse_writepage_args *wpa;\n\tstruct fuse_file *ff;\n\tunsigned int max_folios;\n\tunsigned int nr_bytes;\n};\n\nstruct fuse_flush_in {\n\tuint64_t fh;\n\tuint32_t unused;\n\tuint32_t padding;\n\tuint64_t lock_owner;\n};\n\nstruct fuse_folio_desc {\n\tunsigned int length;\n\tunsigned int offset;\n};\n\nstruct fuse_forget_in {\n\tuint64_t nlookup;\n};\n\nstruct fuse_fs_context {\n\tint fd;\n\tstruct file *file;\n\tunsigned int rootmode;\n\tkuid_t user_id;\n\tkgid_t group_id;\n\tbool is_bdev: 1;\n\tbool fd_present: 1;\n\tbool rootmode_present: 1;\n\tbool user_id_present: 1;\n\tbool group_id_present: 1;\n\tbool default_permissions: 1;\n\tbool allow_other: 1;\n\tbool destroy: 1;\n\tbool no_control: 1;\n\tbool no_force_umount: 1;\n\tbool legacy_opts_show: 1;\n\tenum fuse_dax_mode dax_mode;\n\tunsigned int max_read;\n\tunsigned int blksize;\n\tconst char *subtype;\n\tstruct dax_device *dax_dev;\n\tvoid **fudptr;\n};\n\nstruct fuse_fsync_in {\n\tuint64_t fh;\n\tuint32_t fsync_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_getattr_in {\n\tuint32_t getattr_flags;\n\tuint32_t dummy;\n\tuint64_t fh;\n};\n\nstruct fuse_getxattr_in {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_getxattr_out {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_in_header {\n\tuint32_t len;\n\tuint32_t opcode;\n\tuint64_t unique;\n\tuint64_t nodeid;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t pid;\n\tuint16_t total_extlen;\n\tuint16_t padding;\n};\n\nstruct fuse_init_in {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t max_readahead;\n\tuint32_t flags;\n\tuint32_t flags2;\n\tuint32_t unused[11];\n};\n\nstruct fuse_init_out {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t max_readahead;\n\tuint32_t flags;\n\tuint16_t max_background;\n\tuint16_t congestion_threshold;\n\tuint32_t max_write;\n\tuint32_t time_gran;\n\tuint16_t max_pages;\n\tuint16_t map_alignment;\n\tuint32_t flags2;\n\tuint32_t max_stack_depth;\n\tuint16_t request_timeout;\n\tuint16_t unused[11];\n};\n\nstruct fuse_init_args {\n\tstruct fuse_args args;\n\tstruct fuse_init_in in;\n\tstruct fuse_init_out out;\n};\n\nstruct fuse_inode_dax;\n\nstruct fuse_submount_lookup;\n\nstruct fuse_inode {\n\tstruct inode inode;\n\tu64 nodeid;\n\tu64 nlookup;\n\tstruct fuse_forget_link *forget;\n\tu64 i_time;\n\tu32 inval_mask;\n\tumode_t orig_i_mode;\n\tstruct timespec64 i_btime;\n\tu64 orig_ino;\n\tu64 attr_version;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head write_files;\n\t\t\tstruct list_head queued_writes;\n\t\t\tint writectr;\n\t\t\tint iocachectr;\n\t\t\twait_queue_head_t page_waitq;\n\t\t\twait_queue_head_t direct_io_waitq;\n\t\t};\n\t\tstruct {\n\t\t\tbool cached;\n\t\t\tloff_t size;\n\t\t\tloff_t pos;\n\t\t\tu64 version;\n\t\t\tstruct timespec64 mtime;\n\t\t\tu64 iversion;\n\t\t\tspinlock_t lock;\n\t\t} rdc;\n\t};\n\tlong unsigned int state;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tstruct fuse_inode_dax *dax;\n\tstruct fuse_submount_lookup *submount_lookup;\n\tstruct fuse_backing *fb;\n\tu8 cached_i_blkbits;\n};\n\nstruct fuse_inode_dax {\n\tstruct rw_semaphore sem;\n\tstruct rb_root_cached tree;\n\tlong unsigned int nr;\n};\n\nstruct fuse_inode_handle {\n\tu64 nodeid;\n\tu32 generation;\n};\n\nstruct fuse_interrupt_in {\n\tuint64_t unique;\n};\n\nstruct fuse_read_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t read_flags;\n\tuint64_t lock_owner;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_write_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t write_flags;\n\tuint64_t lock_owner;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_write_out {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_io_priv;\n\nstruct fuse_io_args {\n\tunion {\n\t\tstruct {\n\t\t\tstruct fuse_read_in in;\n\t\t\tu64 attr_ver;\n\t\t} read;\n\t\tstruct {\n\t\t\tstruct fuse_write_in in;\n\t\t\tstruct fuse_write_out out;\n\t\t\tbool folio_locked;\n\t\t} write;\n\t};\n\tstruct fuse_args_pages ap;\n\tstruct fuse_io_priv *io;\n\tstruct fuse_file *ff;\n};\n\nstruct fuse_io_priv {\n\tstruct kref refcnt;\n\tint async;\n\tspinlock_t lock;\n\tunsigned int reqs;\n\tssize_t bytes;\n\tsize_t size;\n\t__u64 offset;\n\tbool write;\n\tbool should_dirty;\n\tint err;\n\tstruct kiocb *iocb;\n\tstruct completion *done;\n\tbool blocking;\n};\n\nstruct fuse_ioctl_in {\n\tuint64_t fh;\n\tuint32_t flags;\n\tuint32_t cmd;\n\tuint64_t arg;\n\tuint32_t in_size;\n\tuint32_t out_size;\n};\n\nstruct fuse_ioctl_iovec {\n\tuint64_t base;\n\tuint64_t len;\n};\n\nstruct fuse_ioctl_out {\n\tint32_t result;\n\tuint32_t flags;\n\tuint32_t in_iovs;\n\tuint32_t out_iovs;\n};\n\nstruct fuse_iqueue_ops {\n\tvoid (*send_forget)(struct fuse_iqueue *, struct fuse_forget_link *);\n\tvoid (*send_interrupt)(struct fuse_iqueue *, struct fuse_req *);\n\tvoid (*send_req)(struct fuse_iqueue *, struct fuse_req *);\n\tvoid (*release)(struct fuse_iqueue *);\n};\n\nstruct fuse_kstatfs {\n\tuint64_t blocks;\n\tuint64_t bfree;\n\tuint64_t bavail;\n\tuint64_t files;\n\tuint64_t ffree;\n\tuint32_t bsize;\n\tuint32_t namelen;\n\tuint32_t frsize;\n\tuint32_t padding;\n\tuint32_t spare[6];\n};\n\nstruct fuse_link_in {\n\tuint64_t oldnodeid;\n};\n\nstruct fuse_lk_in {\n\tuint64_t fh;\n\tuint64_t owner;\n\tstruct fuse_file_lock lk;\n\tuint32_t lk_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_lk_out {\n\tstruct fuse_file_lock lk;\n};\n\nstruct fuse_lseek_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t whence;\n\tuint32_t padding;\n};\n\nstruct fuse_lseek_out {\n\tuint64_t offset;\n};\n\nstruct fuse_mkdir_in {\n\tuint32_t mode;\n\tuint32_t umask;\n};\n\nstruct fuse_mknod_in {\n\tuint32_t mode;\n\tuint32_t rdev;\n\tuint32_t umask;\n\tuint32_t padding;\n};\n\nstruct fuse_mount {\n\tstruct fuse_conn *fc;\n\tstruct super_block *sb;\n\tstruct list_head fc_entry;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_notify_delete_out {\n\tuint64_t parent;\n\tuint64_t child;\n\tuint32_t namelen;\n\tuint32_t padding;\n};\n\nstruct fuse_notify_inval_entry_out {\n\tuint64_t parent;\n\tuint32_t namelen;\n\tuint32_t flags;\n};\n\nstruct fuse_notify_inval_inode_out {\n\tuint64_t ino;\n\tint64_t off;\n\tint64_t len;\n};\n\nstruct fuse_notify_poll_wakeup_out {\n\tuint64_t kh;\n};\n\nstruct fuse_notify_prune_out {\n\tuint32_t count;\n\tuint32_t padding;\n\tuint64_t spare;\n};\n\nstruct fuse_notify_retrieve_in {\n\tuint64_t dummy1;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t dummy2;\n\tuint64_t dummy3;\n\tuint64_t dummy4;\n};\n\nstruct fuse_notify_retrieve_out {\n\tuint64_t notify_unique;\n\tuint64_t nodeid;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_notify_store_out {\n\tuint64_t nodeid;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_open_in {\n\tuint32_t flags;\n\tuint32_t open_flags;\n};\n\nstruct fuse_out_header {\n\tuint32_t len;\n\tint32_t error;\n\tuint64_t unique;\n};\n\nstruct fuse_poll_in {\n\tuint64_t fh;\n\tuint64_t kh;\n\tuint32_t flags;\n\tuint32_t events;\n};\n\nstruct fuse_poll_out {\n\tuint32_t revents;\n\tuint32_t padding;\n};\n\nstruct fuse_removemapping_in {\n\tuint32_t count;\n};\n\nstruct fuse_removemapping_one {\n\tuint64_t moffset;\n\tuint64_t len;\n};\n\nstruct fuse_rename2_in {\n\tuint64_t newdir;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_req {\n\tstruct list_head list;\n\tstruct list_head intr_entry;\n\tstruct fuse_args *args;\n\trefcount_t count;\n\tlong unsigned int flags;\n\tstruct {\n\t\tstruct fuse_in_header h;\n\t} in;\n\tstruct {\n\t\tstruct fuse_out_header h;\n\t} out;\n\twait_queue_head_t waitq;\n\tvoid *argbuf;\n\tstruct fuse_mount *fm;\n\tvoid *ring_entry;\n\tvoid *ring_queue;\n\tlong unsigned int create_time;\n};\n\nstruct fuse_retrieve_args {\n\tstruct fuse_args_pages ap;\n\tstruct fuse_notify_retrieve_in inarg;\n};\n\nstruct fuse_ring_queue;\n\nstruct fuse_ring {\n\tstruct fuse_conn *fc;\n\tsize_t nr_queues;\n\tsize_t max_payload_sz;\n\tstruct fuse_ring_queue **queues;\n\tunsigned int stop_debug_log: 1;\n\twait_queue_head_t stop_waitq;\n\tstruct delayed_work async_teardown_work;\n\tlong unsigned int teardown_time;\n\tatomic_t queue_refs;\n\tbool ready;\n};\n\nstruct fuse_uring_req_header;\n\nstruct fuse_ring_ent {\n\tstruct fuse_uring_req_header *headers;\n\tvoid *payload;\n\tstruct fuse_ring_queue *queue;\n\tstruct io_uring_cmd *cmd;\n\tstruct list_head list;\n\tenum fuse_ring_req_state state;\n\tstruct fuse_req *fuse_req;\n};\n\nstruct fuse_ring_queue {\n\tstruct fuse_ring *ring;\n\tunsigned int qid;\n\tspinlock_t lock;\n\tstruct list_head ent_avail_queue;\n\tstruct list_head ent_w_req_queue;\n\tstruct list_head ent_commit_queue;\n\tstruct list_head ent_in_userspace;\n\tstruct list_head ent_released;\n\tstruct list_head fuse_req_queue;\n\tstruct list_head fuse_req_bg_queue;\n\tstruct fuse_pqueue fpq;\n\tunsigned int active_background;\n\tbool stopped;\n};\n\nstruct fuse_secctx {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_secctx_header {\n\tuint32_t size;\n\tuint32_t nr_secctx;\n};\n\nstruct fuse_setattr_in {\n\tuint32_t valid;\n\tuint32_t padding;\n\tuint64_t fh;\n\tuint64_t size;\n\tuint64_t lock_owner;\n\tuint64_t atime;\n\tuint64_t mtime;\n\tuint64_t ctime;\n\tuint32_t atimensec;\n\tuint32_t mtimensec;\n\tuint32_t ctimensec;\n\tuint32_t mode;\n\tuint32_t unused4;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t unused5;\n};\n\nstruct fuse_setupmapping_in {\n\tuint64_t fh;\n\tuint64_t foffset;\n\tuint64_t len;\n\tuint64_t flags;\n\tuint64_t moffset;\n};\n\nstruct fuse_setxattr_in {\n\tuint32_t size;\n\tuint32_t flags;\n\tuint32_t setxattr_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_statfs_out {\n\tstruct fuse_kstatfs st;\n};\n\nstruct fuse_sx_time {\n\tint64_t tv_sec;\n\tuint32_t tv_nsec;\n\tint32_t __reserved;\n};\n\nstruct fuse_statx {\n\tuint32_t mask;\n\tuint32_t blksize;\n\tuint64_t attributes;\n\tuint32_t nlink;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint16_t mode;\n\tuint16_t __spare0[1];\n\tuint64_t ino;\n\tuint64_t size;\n\tuint64_t blocks;\n\tuint64_t attributes_mask;\n\tstruct fuse_sx_time atime;\n\tstruct fuse_sx_time btime;\n\tstruct fuse_sx_time ctime;\n\tstruct fuse_sx_time mtime;\n\tuint32_t rdev_major;\n\tuint32_t rdev_minor;\n\tuint32_t dev_major;\n\tuint32_t dev_minor;\n\tuint64_t __spare2[14];\n};\n\nstruct fuse_statx_in {\n\tuint32_t getattr_flags;\n\tuint32_t reserved;\n\tuint64_t fh;\n\tuint32_t sx_flags;\n\tuint32_t sx_mask;\n};\n\nstruct fuse_statx_out {\n\tuint64_t attr_valid;\n\tuint32_t attr_valid_nsec;\n\tuint32_t flags;\n\tuint64_t spare[2];\n\tstruct fuse_statx stat;\n};\n\nstruct fuse_submount_lookup {\n\trefcount_t count;\n\tu64 nodeid;\n\tstruct fuse_forget_link *forget;\n};\n\nstruct fuse_supp_groups {\n\tuint32_t nr_groups;\n\tuint32_t groups[0];\n};\n\nstruct fuse_sync_bucket {\n\tatomic_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_syncfs_in {\n\tuint64_t padding;\n};\n\nstruct fuse_uring_cmd_req {\n\tuint64_t flags;\n\tuint64_t commit_id;\n\tuint16_t qid;\n\tuint8_t padding[6];\n};\n\nstruct fuse_uring_ent_in_out {\n\tuint64_t flags;\n\tuint64_t commit_id;\n\tuint32_t payload_sz;\n\tuint32_t padding;\n\tuint64_t reserved;\n};\n\nstruct fuse_uring_pdu {\n\tstruct fuse_ring_ent *ent;\n};\n\nstruct fuse_uring_req_header {\n\tchar in_out[128];\n\tchar op_in[128];\n\tstruct fuse_uring_ent_in_out ring_ent_in_out;\n};\n\nstruct fuse_writepage_args {\n\tstruct fuse_io_args ia;\n\tstruct list_head queue_entry;\n\tstruct inode *inode;\n\tstruct fuse_sync_bucket *bucket;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t} both;\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nunion fwnet_hwaddr {\n\tu8 u[16];\n\tstruct {\n\t\t__be64 uniq_id;\n\t\tu8 max_rec;\n\t\tu8 sspd;\n\t\tu8 fifo[6];\n\t} uc;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_reference_args;\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct gcm_instance_ctx {\n\tstruct crypto_skcipher_spawn ctr;\n\tstruct crypto_ahash_spawn ghash;\n};\n\nstruct gcry_mpi;\n\ntypedef struct gcry_mpi *MPI;\n\nstruct gcry_mpi {\n\tint alloced;\n\tint nlimbs;\n\tint nbits;\n\tint sign;\n\tunsigned int flags;\n\tmpi_limb_t *d;\n};\n\nstruct gds_subvector {\n\tu8 length;\n\tu8 key;\n};\n\nstruct gds_vector {\n\tu16 length;\n\tu16 gds_id;\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct list_head slave_bdevs;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tstruct cdrom_device_info *cdi;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 r1: 1;\n\tu8 r2: 1;\n\tu8 r3: 1;\n\tu8 length: 5;\n\tu8 opt_data[0];\n};\n\nstruct ocontext;\n\nstruct genfs {\n\tchar *fstype;\n\tstruct ocontext *head;\n\tstruct genfs *next;\n};\n\nstruct netlink_callback;\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[64];\n\t\tu8 data[512];\n\t};\n};\n\nstruct getbmapx {\n\t__s64 bmv_offset;\n\t__s64 bmv_block;\n\t__s64 bmv_length;\n\t__s32 bmv_count;\n\t__s32 bmv_entries;\n\t__s32 bmv_iflags;\n\t__s32 bmv_oflags;\n\t__s32 bmv_unused1;\n\t__s32 bmv_unused2;\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct gf128mul_4k {\n\tbe128 t[256];\n};\n\nstruct gf128mul_64k {\n\tstruct gf128mul_4k *t[16];\n};\n\nstruct ghash_ctx {\n\tstruct gf128mul_4k *gf128;\n};\n\nstruct ghash_desc_ctx {\n\tu8 buffer[16];\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct go {\n\tu16 length;\n\tu16 type;\n\tu32 domid;\n\tu8 hhmmss_time[8];\n\tu8 th_time[3];\n\tu8 reserved_0;\n\tu8 dddyyyy_date[7];\n\tu8 _reserved_1;\n\tu16 general_msg_flags;\n\tu8 _reserved_2[10];\n\tu8 originating_system_name[8];\n\tu8 job_guest_name[8];\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct napi_config;\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n};\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct gs_cb {\n\t__u64 reserved;\n\t__u64 gsd;\n\t__u64 gssm;\n\t__u64 gs_epl_a;\n};\n\nunion handle_parts {\n\tdepot_stack_handle_t handle;\n\tstruct {\n\t\tu32 pool_index_plus_1: 17;\n\t\tu32 offset: 10;\n\t\tu32 extra: 5;\n\t};\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct handshake_net {\n\tspinlock_t hn_lock;\n\tint hn_pending;\n\tint hn_pending_max;\n\tstruct list_head hn_requests;\n\tlong unsigned int hn_flags;\n};\n\nstruct handshake_req;\n\nstruct handshake_proto {\n\tint hp_handler_class;\n\tsize_t hp_privsize;\n\tlong unsigned int hp_flags;\n\tint (*hp_accept)(struct handshake_req *, struct genl_info *, int);\n\tvoid (*hp_done)(struct handshake_req *, unsigned int, struct genl_info *);\n\tvoid (*hp_destroy)(struct handshake_req *);\n};\n\nstruct handshake_req {\n\tstruct list_head hr_list;\n\tstruct rhash_head hr_rhash;\n\tlong unsigned int hr_flags;\n\tconst struct handshake_proto *hr_proto;\n\tstruct sock *hr_sk;\n\tvoid (*hr_odestruct)(struct sock *);\n\tchar hr_priv[0];\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hash_cell {\n\tstruct rb_node name_node;\n\tstruct rb_node uuid_node;\n\tbool name_set;\n\tbool uuid_set;\n\tchar *name;\n\tchar *uuid;\n\tstruct mapped_device *md;\n\tstruct dm_table *new_map;\n};\n\nstruct hash_prefix {\n\tconst char *name;\n\tconst u8 *data;\n\tsize_t size;\n};\n\nstruct hash_testvec {\n\tconst char *key;\n\tconst char *plaintext;\n\tconst char *digest;\n\tunsigned int psize;\n\tshort unsigned int ksize;\n\tint setkey_error;\n\tint digest_error;\n\tbool fips_skip;\n};\n\nstruct hashtab_key_params {\n\tu32 (*hash)(const void *);\n\tint (*cmp)(const void *, const void *);\n};\n\nstruct hashtab_node {\n\tvoid *key;\n\tvoid *datum;\n\tstruct hashtab_node *next;\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hdmi_any_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n};\n\nstruct hdmi_audio_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned char channels;\n\tenum hdmi_audio_coding_type coding_type;\n\tenum hdmi_audio_sample_size sample_size;\n\tenum hdmi_audio_sample_frequency sample_frequency;\n\tenum hdmi_audio_coding_type_ext coding_type_ext;\n\tunsigned char channel_allocation;\n\tunsigned char level_shift_value;\n\tbool downmix_inhibit;\n};\n\nstruct hdmi_avi_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tbool itc;\n\tunsigned char pixel_repeat;\n\tenum hdmi_colorspace colorspace;\n\tenum hdmi_scan_mode scan_mode;\n\tenum hdmi_colorimetry colorimetry;\n\tenum hdmi_picture_aspect picture_aspect;\n\tenum hdmi_active_aspect active_aspect;\n\tenum hdmi_extended_colorimetry extended_colorimetry;\n\tenum hdmi_quantization_range quantization_range;\n\tenum hdmi_nups nups;\n\tunsigned char video_code;\n\tenum hdmi_ycc_quantization_range ycc_quantization_range;\n\tenum hdmi_content_type content_type;\n\tshort unsigned int top_bar;\n\tshort unsigned int bottom_bar;\n\tshort unsigned int left_bar;\n\tshort unsigned int right_bar;\n};\n\nstruct hdmi_drm_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_eotf eotf;\n\tenum hdmi_metadata_type metadata_type;\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} white_point;\n\tu16 max_display_mastering_luminance;\n\tu16 min_display_mastering_luminance;\n\tu16 max_cll;\n\tu16 max_fall;\n};\n\nstruct hdmi_spd_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tchar vendor[8];\n\tchar product[16];\n\tenum hdmi_spd_sdi sdi;\n};\n\nstruct hdmi_vendor_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned int oui;\n\tu8 vic;\n\tenum hdmi_3d_structure s3d_struct;\n\tunsigned int s3d_ext_data;\n};\n\nunion hdmi_vendor_any_infoframe {\n\tstruct {\n\t\tenum hdmi_infoframe_type type;\n\t\tunsigned char version;\n\t\tunsigned char length;\n\t\tunsigned int oui;\n\t} any;\n\tstruct hdmi_vendor_infoframe hdmi;\n};\n\nunion hdmi_infoframe {\n\tstruct hdmi_any_infoframe any;\n\tstruct hdmi_avi_infoframe avi;\n\tstruct hdmi_spd_infoframe spd;\n\tunion hdmi_vendor_any_infoframe vendor;\n\tstruct hdmi_audio_infoframe audio;\n\tstruct hdmi_drm_infoframe drm;\n};\n\nstruct hdr_sctn {\n\tu8 infhflg1;\n\tu8 infhflg2;\n\tu8 infhval1;\n\tu8 infhval2;\n\tu8 reserved[3];\n\tu8 infhygct;\n\tu16 infhtotl;\n\tu16 infhdln;\n\tu16 infmoff;\n\tu16 infmlen;\n\tu16 infpoff;\n\tu16 infplen;\n\tu16 infhoff1;\n\tu16 infhlen1;\n\tu16 infgoff1;\n\tu16 infglen1;\n\tu16 infhoff2;\n\tu16 infhlen2;\n\tu16 infgoff2;\n\tu16 infglen2;\n\tu16 infhoff3;\n\tu16 infhlen3;\n\tu16 infgoff3;\n\tu16 infglen3;\n\tu8 reserved2[4];\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct heuristic_ws {\n\tu8 *sample;\n\tu32 sample_size;\n\tstruct bucket_item *bucket;\n\tstruct bucket_item *bucket_b;\n\tstruct list_head list;\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[4];\n};\n\nstruct hist_elt_data {\n\tchar *comm;\n\tu64 *var_ref_vals;\n\tchar **field_var_str;\n\tint n_field_var_str;\n};\n\nstruct hist_var {\n\tchar *name;\n\tstruct hist_trigger_data *hist_data;\n\tunsigned int idx;\n};\n\nstruct hist_field {\n\tstruct ftrace_event_field *field;\n\tlong unsigned int flags;\n\tlong unsigned int buckets;\n\tconst char *type;\n\tstruct hist_field *operands[2];\n\tstruct hist_trigger_data *hist_data;\n\tenum hist_field_fn fn_num;\n\tunsigned int ref;\n\tunsigned int size;\n\tunsigned int offset;\n\tunsigned int is_signed;\n\tstruct hist_var var;\n\tenum field_op_id operator;\n\tchar *system;\n\tchar *event_name;\n\tchar *name;\n\tunsigned int var_ref_idx;\n\tbool read_once;\n\tunsigned int var_str_idx;\n\tu64 constant;\n\tu64 div_multiplier;\n};\n\nstruct hist_file_data {\n\tstruct file *file;\n\tu64 last_read;\n\tu64 last_act;\n};\n\nstruct hist_pad {\n\tlong unsigned int entries[31];\n\tu64 var_ref_vals[16];\n\tchar compound_key[504];\n};\n\nstruct var_defs {\n\tunsigned int n_vars;\n\tchar *name[16];\n\tchar *expr[16];\n};\n\nstruct hist_trigger_attrs {\n\tchar *keys_str;\n\tchar *vals_str;\n\tchar *sort_key_str;\n\tchar *name;\n\tchar *clock;\n\tbool pause;\n\tbool cont;\n\tbool clear;\n\tbool ts_in_usecs;\n\tbool no_hitcount;\n\tunsigned int map_bits;\n\tchar *assignment_str[16];\n\tunsigned int n_assignments;\n\tchar *action_str[8];\n\tunsigned int n_actions;\n\tstruct var_defs var_defs;\n};\n\nstruct tracing_map_sort_key {\n\tunsigned int field_idx;\n\tbool descending;\n};\n\nstruct tracing_map;\n\nstruct hist_trigger_data {\n\tstruct hist_field *fields[22];\n\tunsigned int n_vals;\n\tunsigned int n_keys;\n\tunsigned int n_fields;\n\tunsigned int n_vars;\n\tunsigned int n_var_str;\n\tunsigned int key_size;\n\tstruct tracing_map_sort_key sort_keys[2];\n\tunsigned int n_sort_keys;\n\tstruct trace_event_file *event_file;\n\tstruct hist_trigger_attrs *attrs;\n\tstruct tracing_map *map;\n\tbool enable_timestamps;\n\tbool remove;\n\tstruct hist_field *var_refs[16];\n\tunsigned int n_var_refs;\n\tstruct action_data *actions[8];\n\tunsigned int n_actions;\n\tstruct field_var *field_vars[64];\n\tunsigned int n_field_vars;\n\tunsigned int n_field_var_str;\n\tstruct field_var_hist *field_var_hists[64];\n\tunsigned int n_field_var_hists;\n\tstruct field_var *save_vars[64];\n\tunsigned int n_save_vars;\n\tunsigned int n_save_var_str;\n};\n\nstruct hist_val_stat {\n\tu64 max;\n\tu64 total;\n};\n\nstruct hist_var_data {\n\tstruct list_head list;\n\tstruct hist_trigger_data *hist_data;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct hmac_ctx {\n\tstruct crypto_shash *hash;\n\tu8 pads[0];\n};\n\nstruct md5_block_state {\n\tu32 h[4];\n};\n\nstruct md5_ctx {\n\tstruct md5_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_md5_ctx {\n\tstruct md5_ctx hash_ctx;\n\tstruct md5_block_state ostate;\n};\n\nstruct hmac_md5_key {\n\tstruct md5_block_state istate;\n\tstruct md5_block_state ostate;\n};\n\nstruct sha1_block_state {\n\tu32 h[5];\n};\n\nstruct sha1_ctx {\n\tstruct sha1_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_sha1_ctx {\n\tstruct sha1_ctx sha_ctx;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha1_key {\n\tstruct sha1_block_state istate;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha384_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha384_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hmac_sha512_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmm_dma_map {\n\tstruct dma_iova_state state;\n\tlong unsigned int *pfn_list;\n\tdma_addr_t *dma_list;\n\tsize_t dma_entry_size;\n};\n\nstruct mmu_interval_notifier;\n\nstruct hmm_range {\n\tstruct mmu_interval_notifier *notifier;\n\tlong unsigned int notifier_seq;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int *hmm_pfns;\n\tlong unsigned int default_flags;\n\tlong unsigned int pfn_flags_mask;\n\tvoid *dev_private_owner;\n};\n\nstruct hmm_vma_walk {\n\tstruct hmm_range *range;\n\tlong unsigned int last;\n};\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct hprobe {\n\tenum hprobe_state state;\n\tint srcu_idx;\n\tstruct uprobe *uprobe;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tktime_t offset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hrtimer_clock_base clock_base[8];\n\tcall_single_data_t csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n};\n\nstruct hs_primary_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\t__u8 id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 unused4[28];\n\t__u8 root_directory_record[34];\n};\n\nstruct hs_volume_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2033];\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {\n\tstruct mutex resize_lock;\n\tstruct lock_class_key resize_key;\n\tint next_nid_to_alloc;\n\tint next_nid_to_free;\n\tunsigned int order;\n\tunsigned int demote_order;\n\tlong unsigned int mask;\n\tlong unsigned int max_huge_pages;\n\tlong unsigned int nr_huge_pages;\n\tlong unsigned int free_huge_pages;\n\tlong unsigned int resv_huge_pages;\n\tlong unsigned int surplus_huge_pages;\n\tlong unsigned int nr_overcommit_huge_pages;\n\tstruct list_head hugepage_activelist;\n\tstruct list_head hugepage_freelists[2];\n\tunsigned int max_huge_pages_node[2];\n\tunsigned int nr_huge_pages_node[2];\n\tunsigned int free_huge_pages_node[2];\n\tunsigned int surplus_huge_pages_node[2];\n\tchar name[32];\n};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tlong: 0;\n\tchar key[0];\n};\n\nstruct huge_bootmem_page {\n\tstruct list_head list;\n\tstruct hstate *hstate;\n\tlong unsigned int flags;\n\tstruct cma *cma;\n};\n\nstruct hugepage_subpool {\n\tspinlock_t lock;\n\tlong int count;\n\tlong int max_hpages;\n\tlong int used_hpages;\n\tstruct hstate *hstate;\n\tlong int min_hpages;\n\tlong int rsv_hpages;\n};\n\nstruct page_counter {\n\tatomic_long_t usage;\n\tlong unsigned int failcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int emin;\n\tatomic_long_t min_usage;\n\tatomic_long_t children_min_usage;\n\tlong unsigned int elow;\n\tatomic_long_t low_usage;\n\tatomic_long_t children_low_usage;\n\tlong unsigned int watermark;\n\tlong unsigned int local_watermark;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tbool protection_support;\n\tbool track_failcnt;\n\tlong unsigned int min;\n\tlong unsigned int low;\n\tlong unsigned int high;\n\tlong unsigned int max;\n\tstruct page_counter *parent;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hugetlb_cgroup_per_node;\n\nstruct hugetlb_cgroup {\n\tstruct cgroup_subsys_state css;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter hugepage[2];\n\tstruct page_counter rsvd_hugepage[2];\n\tatomic_long_t events[2];\n\tatomic_long_t events_local[2];\n\tstruct cgroup_file events_file[2];\n\tstruct cgroup_file events_local_file[2];\n\tstruct hugetlb_cgroup_per_node *nodeinfo[0];\n};\n\nstruct hugetlb_cgroup_per_node {\n\tlong unsigned int usage[2];\n};\n\nstruct hugetlb_cmdline {\n\tchar *val;\n\tint (*setup)(char *);\n};\n\nstruct hugetlb_vma_lock {\n\tstruct kref refs;\n\tstruct rw_semaphore rw_sema;\n\tstruct vm_area_struct *vma;\n};\n\nstruct hugetlbfs_fs_context {\n\tstruct hstate *hstate;\n\tlong long unsigned int max_size_opt;\n\tlong long unsigned int min_size_opt;\n\tlong int max_hpages;\n\tlong int nr_inodes;\n\tlong int min_hpages;\n\tenum hugetlbfs_size_type max_val_type;\n\tenum hugetlbfs_size_type min_val_type;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hugetlbfs_inode_info {\n\tstruct inode vfs_inode;\n\tunsigned int seals;\n};\n\nstruct hugetlbfs_sb_info {\n\tlong int max_inodes;\n\tlong int free_inodes;\n\tspinlock_t stat_lock;\n\tstruct hstate *hstate;\n\tstruct hugepage_subpool *spool;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hvc_struct;\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct iucv_path;\n\nstruct hvc_iucv_private {\n\tstruct hvc_struct *hvc;\n\tu8 srv_name[8];\n\tunsigned char is_console;\n\tenum iucv_state_t iucv_state;\n\tenum tty_state_t tty_state;\n\tstruct iucv_path *path;\n\tspinlock_t lock;\n\tvoid *sndbuf;\n\tsize_t sndbuf_len;\n\tstruct delayed_work sndbuf_work;\n\twait_queue_head_t sndbuf_waitq;\n\tstruct list_head tty_outqueue;\n\tstruct list_head tty_inqueue;\n\tstruct device *dev;\n\tu8 info_path[16];\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 config1;\n\t\t\tu64 last_tag;\n\t\t\tu64 dyn_constraint;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tu64 aux_config;\n\t\t\tunsigned int aux_paused;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tunion {\n\t\tstruct {\n\t\t\tu64 last_period;\n\t\t\tlocal64_t period_left;\n\t\t};\n\t\tstruct {\n\t\t\tu64 saved_metric;\n\t\t\tu64 saved_slots;\n\t\t};\n\t};\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hwerr_info {\n\tatomic_t count;\n\ttime64_t timestamp;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct hws_basic_entry {\n\tunsigned int def: 16;\n\tunsigned int R: 4;\n\tunsigned int U: 4;\n\tunsigned int z: 2;\n\tunsigned int T: 1;\n\tunsigned int W: 1;\n\tunsigned int P: 1;\n\tunsigned int AS: 2;\n\tunsigned int I: 1;\n\tunsigned int CL: 2;\n\tunsigned int H: 1;\n\tunsigned int LS: 1;\n\tshort: 12;\n\tunsigned int prim_asn: 16;\n\tlong long unsigned int ia;\n\tlong long unsigned int gpp;\n\tlong long unsigned int hpp;\n};\n\nunion hws_trailer_header {\n\tstruct {\n\t\tunsigned int f: 1;\n\t\tunsigned int a: 1;\n\t\tunsigned int t: 1;\n\t\tint: 29;\n\t\tunsigned int bsdes: 16;\n\t\tunsigned int dsdes: 16;\n\t\tlong long unsigned int overflow;\n\t};\n\tu128 val;\n};\n\nstruct hws_trailer_entry {\n\tunion hws_trailer_header header;\n\tunsigned char timestamp[16];\n\tlong long unsigned int reserved1;\n\tlong long unsigned int reserved2;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int clock_base: 1;\n\t\t\tlong long unsigned int progusage1: 63;\n\t\t\tlong long unsigned int progusage2;\n\t\t};\n\t\tlong long unsigned int progusage[2];\n\t};\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct hypfs_dbfs_file;\n\nstruct hypfs_dbfs_data {\n\tvoid *buf;\n\tvoid *buf_free_ptr;\n\tsize_t size;\n\tstruct hypfs_dbfs_file *dbfs_file;\n};\n\nstruct hypfs_dbfs_file {\n\tconst char *name;\n\tint (*data_create)(void **, void **, size_t *);\n\tvoid (*data_free)(const void *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tstruct mutex lock;\n\tstruct dentry *dentry;\n};\n\nstruct hypfs_diag0c_hdr {\n\t__u64 len;\n\t__u16 version;\n\tchar reserved1[6];\n\tchar tod_ext[16];\n\t__u64 count;\n\tchar reserved2[24];\n};\n\nstruct hypfs_diag0c_entry {\n\tchar date[8];\n\tchar time[8];\n\t__u64 virtcpu;\n\t__u64 totalproc;\n\t__u32 cpu;\n\t__u32 reserved;\n};\n\nstruct hypfs_diag0c_data {\n\tstruct hypfs_diag0c_hdr hdr;\n\tstruct hypfs_diag0c_entry entry[0];\n};\n\nstruct hypfs_diag304 {\n\t__u32 args[2];\n\t__u64 data;\n\t__u64 rc;\n};\n\nstruct hypfs_sb_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct dentry *update_file;\n\ttime64_t last_update;\n\tstruct mutex lock;\n};\n\nstruct software_node;\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n};\n\nstruct ib_pd;\n\nstruct ib_uobject;\n\nstruct ib_gid_attr;\n\nstruct ib_ah {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tconst struct ib_gid_attr *sgid_attr;\n\tenum rdma_ah_attr_type type;\n};\n\nstruct ib_ah_attr {\n\tu16 dlid;\n\tu8 src_path_bits;\n};\n\nstruct ib_core_device {\n\tstruct device dev;\n\tpossible_net_t rdma_net;\n\tstruct kobject *ports_kobj;\n\tstruct list_head port_list;\n\tstruct ib_device *owner;\n};\n\nstruct ib_counters {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_counters_read_attr {\n\tu64 *counters_buff;\n\tu32 ncounters;\n\tu32 flags;\n};\n\nstruct ib_ucq_object;\n\nstruct ib_cq;\n\ntypedef void (*ib_comp_handler)(struct ib_cq *, void *);\n\nstruct irq_poll;\n\ntypedef int irq_poll_fn(struct irq_poll *, int);\n\nstruct irq_poll {\n\tstruct list_head list;\n\tlong unsigned int state;\n\tint weight;\n\tirq_poll_fn *poll;\n};\n\nstruct rdma_restrack_entry {\n\tbool valid;\n\tu8 no_track: 1;\n\tstruct kref kref;\n\tstruct completion comp;\n\tstruct task_struct *task;\n\tconst char *kern_name;\n\tenum rdma_restrack_type type;\n\tbool user;\n\tu32 id;\n};\n\nstruct ib_event;\n\nstruct ib_wc;\n\nstruct ib_cq {\n\tstruct ib_device *device;\n\tstruct ib_ucq_object *uobject;\n\tib_comp_handler comp_handler;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *cq_context;\n\tint cqe;\n\tunsigned int cqe_used;\n\tatomic_t usecnt;\n\tenum ib_poll_context poll_ctx;\n\tstruct ib_wc *wc;\n\tstruct list_head pool_entry;\n\tunion {\n\t\tstruct irq_poll iop;\n\t\tstruct work_struct work;\n\t};\n\tstruct workqueue_struct *comp_wq;\n\tstruct dim *dim;\n\tktime_t timestamp;\n\tu8 interrupt: 1;\n\tu8 shared: 1;\n\tunsigned int comp_vector;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_cq_caps {\n\tu16 max_cq_moderation_count;\n\tu16 max_cq_moderation_period;\n};\n\nstruct ib_cq_init_attr {\n\tunsigned int cqe;\n\tu32 comp_vector;\n\tu32 flags;\n};\n\nstruct ib_cqe {\n\tvoid (*done)(struct ib_cq *, struct ib_wc *);\n};\n\nstruct ib_mad;\n\nstruct uverbs_attr_bundle;\n\nstruct ib_umem;\n\nstruct rdma_cm_id;\n\nstruct iw_cm_id;\n\nstruct iw_cm_conn_param;\n\nstruct ib_uverbs_file;\n\nstruct ib_qp;\n\nstruct ib_send_wr;\n\nstruct ib_recv_wr;\n\nstruct ib_srq;\n\nstruct ib_grh;\n\nstruct ib_device_attr;\n\nstruct ib_udata;\n\nstruct ib_device_modify;\n\nstruct ib_port_attr;\n\nstruct ib_port_modify;\n\nstruct ib_port_immutable;\n\nstruct rdma_netdev_alloc_params;\n\nunion ib_gid;\n\nstruct ib_ucontext;\n\nstruct rdma_user_mmap_entry;\n\nstruct phys_vec;\n\nstruct rdma_ah_init_attr;\n\nstruct rdma_ah_attr;\n\nstruct ib_srq_init_attr;\n\nstruct ib_srq_attr;\n\nstruct ib_qp_init_attr;\n\nstruct ib_qp_attr;\n\nstruct ib_mr;\n\nstruct ib_dmah;\n\nstruct ib_sge;\n\nstruct ib_mr_status;\n\nstruct ib_mw;\n\nstruct ib_xrcd;\n\nstruct ib_flow;\n\nstruct ib_flow_attr;\n\nstruct ib_flow_action;\n\nstruct ifla_vf_info;\n\nstruct ifla_vf_stats;\n\nstruct ifla_vf_guid;\n\nstruct ib_wq;\n\nstruct ib_wq_init_attr;\n\nstruct ib_wq_attr;\n\nstruct ib_rwq_ind_table;\n\nstruct ib_rwq_ind_table_init_attr;\n\nstruct ib_dm;\n\nstruct ib_dm_alloc_attr;\n\nstruct ib_dm_mr_attr;\n\nstruct rdma_hw_stats;\n\nstruct rdma_counter;\n\nstruct ib_device_ops {\n\tstruct module *owner;\n\tenum rdma_driver_id driver_id;\n\tu32 uverbs_abi_ver;\n\tunsigned int uverbs_no_driver_id_binding: 1;\n\tconst struct attribute_group *device_group;\n\tconst struct attribute_group **port_groups;\n\tint (*post_send)(struct ib_qp *, const struct ib_send_wr *, const struct ib_send_wr **);\n\tint (*post_recv)(struct ib_qp *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tvoid (*drain_rq)(struct ib_qp *);\n\tvoid (*drain_sq)(struct ib_qp *);\n\tint (*poll_cq)(struct ib_cq *, int, struct ib_wc *);\n\tint (*peek_cq)(struct ib_cq *, int);\n\tint (*req_notify_cq)(struct ib_cq *, enum ib_cq_notify_flags);\n\tint (*post_srq_recv)(struct ib_srq *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tint (*process_mad)(struct ib_device *, int, u32, const struct ib_wc *, const struct ib_grh *, const struct ib_mad *, struct ib_mad *, size_t *, u16 *);\n\tint (*query_device)(struct ib_device *, struct ib_device_attr *, struct ib_udata *);\n\tint (*modify_device)(struct ib_device *, int, struct ib_device_modify *);\n\tvoid (*get_dev_fw_str)(struct ib_device *, char *);\n\tconst struct cpumask * (*get_vector_affinity)(struct ib_device *, int);\n\tint (*query_port)(struct ib_device *, u32, struct ib_port_attr *);\n\tint (*query_port_speed)(struct ib_device *, u32, u64 *);\n\tint (*modify_port)(struct ib_device *, u32, int, struct ib_port_modify *);\n\tint (*get_port_immutable)(struct ib_device *, u32, struct ib_port_immutable *);\n\tenum rdma_link_layer (*get_link_layer)(struct ib_device *, u32);\n\tstruct net_device * (*get_netdev)(struct ib_device *, u32);\n\tstruct net_device * (*alloc_rdma_netdev)(struct ib_device *, u32, enum rdma_netdev_t, const char *, unsigned char, void (*)(struct net_device *));\n\tint (*rdma_netdev_get_params)(struct ib_device *, u32, enum rdma_netdev_t, struct rdma_netdev_alloc_params *);\n\tint (*query_gid)(struct ib_device *, u32, int, union ib_gid *);\n\tint (*add_gid)(const struct ib_gid_attr *, void **);\n\tint (*del_gid)(const struct ib_gid_attr *, void **);\n\tint (*query_pkey)(struct ib_device *, u32, u16, u16 *);\n\tint (*alloc_ucontext)(struct ib_ucontext *, struct ib_udata *);\n\tvoid (*dealloc_ucontext)(struct ib_ucontext *);\n\tint (*mmap)(struct ib_ucontext *, struct vm_area_struct *);\n\tvoid (*mmap_free)(struct rdma_user_mmap_entry *);\n\tint (*mmap_get_pfns)(struct rdma_user_mmap_entry *, struct phys_vec *, struct p2pdma_provider **);\n\tstruct rdma_user_mmap_entry * (*pgoff_to_mmap_entry)(struct ib_ucontext *, off_t);\n\tvoid (*disassociate_ucontext)(struct ib_ucontext *);\n\tint (*alloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*dealloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*create_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*create_user_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*modify_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*query_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*destroy_ah)(struct ib_ah *, u32);\n\tint (*create_srq)(struct ib_srq *, struct ib_srq_init_attr *, struct ib_udata *);\n\tint (*modify_srq)(struct ib_srq *, struct ib_srq_attr *, enum ib_srq_attr_mask, struct ib_udata *);\n\tint (*query_srq)(struct ib_srq *, struct ib_srq_attr *);\n\tint (*destroy_srq)(struct ib_srq *, struct ib_udata *);\n\tint (*create_qp)(struct ib_qp *, struct ib_qp_init_attr *, struct ib_udata *);\n\tint (*modify_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);\n\tint (*query_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_qp_init_attr *);\n\tint (*destroy_qp)(struct ib_qp *, struct ib_udata *);\n\tint (*create_cq)(struct ib_cq *, const struct ib_cq_init_attr *, struct uverbs_attr_bundle *);\n\tint (*create_cq_umem)(struct ib_cq *, const struct ib_cq_init_attr *, struct ib_umem *, struct uverbs_attr_bundle *);\n\tint (*modify_cq)(struct ib_cq *, u16, u16);\n\tint (*destroy_cq)(struct ib_cq *, struct ib_udata *);\n\tint (*resize_cq)(struct ib_cq *, int, struct ib_udata *);\n\tint (*pre_destroy_cq)(struct ib_cq *);\n\tvoid (*post_destroy_cq)(struct ib_cq *);\n\tstruct ib_mr * (*get_dma_mr)(struct ib_pd *, int);\n\tstruct ib_mr * (*reg_user_mr)(struct ib_pd *, u64, u64, u64, int, struct ib_dmah *, struct ib_udata *);\n\tstruct ib_mr * (*reg_user_mr_dmabuf)(struct ib_pd *, u64, u64, u64, int, int, struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*rereg_user_mr)(struct ib_mr *, int, u64, u64, u64, int, struct ib_pd *, struct ib_udata *);\n\tint (*dereg_mr)(struct ib_mr *, struct ib_udata *);\n\tstruct ib_mr * (*alloc_mr)(struct ib_pd *, enum ib_mr_type, u32);\n\tstruct ib_mr * (*alloc_mr_integrity)(struct ib_pd *, u32, u32);\n\tint (*advise_mr)(struct ib_pd *, enum ib_uverbs_advise_mr_advice, u32, struct ib_sge *, u32, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg)(struct ib_mr *, struct scatterlist *, int, unsigned int *);\n\tint (*check_mr_status)(struct ib_mr *, u32, struct ib_mr_status *);\n\tint (*alloc_mw)(struct ib_mw *, struct ib_udata *);\n\tint (*dealloc_mw)(struct ib_mw *);\n\tint (*attach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*detach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*alloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tint (*dealloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tstruct ib_flow * (*create_flow)(struct ib_qp *, struct ib_flow_attr *, struct ib_udata *);\n\tint (*destroy_flow)(struct ib_flow *);\n\tint (*destroy_flow_action)(struct ib_flow_action *);\n\tint (*set_vf_link_state)(struct ib_device *, int, u32, int);\n\tint (*get_vf_config)(struct ib_device *, int, u32, struct ifla_vf_info *);\n\tint (*get_vf_stats)(struct ib_device *, int, u32, struct ifla_vf_stats *);\n\tint (*get_vf_guid)(struct ib_device *, int, u32, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*set_vf_guid)(struct ib_device *, int, u32, u64, int);\n\tstruct ib_wq * (*create_wq)(struct ib_pd *, struct ib_wq_init_attr *, struct ib_udata *);\n\tint (*destroy_wq)(struct ib_wq *, struct ib_udata *);\n\tint (*modify_wq)(struct ib_wq *, struct ib_wq_attr *, u32, struct ib_udata *);\n\tint (*create_rwq_ind_table)(struct ib_rwq_ind_table *, struct ib_rwq_ind_table_init_attr *, struct ib_udata *);\n\tint (*destroy_rwq_ind_table)(struct ib_rwq_ind_table *);\n\tstruct ib_dm * (*alloc_dm)(struct ib_device *, struct ib_ucontext *, struct ib_dm_alloc_attr *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dm)(struct ib_dm *, struct uverbs_attr_bundle *);\n\tint (*alloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*reg_dm_mr)(struct ib_pd *, struct ib_dm *, struct ib_dm_mr_attr *, struct uverbs_attr_bundle *);\n\tint (*create_counters)(struct ib_counters *, struct uverbs_attr_bundle *);\n\tint (*destroy_counters)(struct ib_counters *);\n\tint (*read_counters)(struct ib_counters *, struct ib_counters_read_attr *, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg_pi)(struct ib_mr *, struct scatterlist *, int, unsigned int *, struct scatterlist *, int, unsigned int *);\n\tstruct rdma_hw_stats * (*alloc_hw_device_stats)(struct ib_device *);\n\tstruct rdma_hw_stats * (*alloc_hw_port_stats)(struct ib_device *, u32);\n\tint (*get_hw_stats)(struct ib_device *, struct rdma_hw_stats *, u32, int);\n\tint (*modify_hw_stat)(struct ib_device *, u32, unsigned int, bool);\n\tint (*fill_res_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_mr_entry_raw)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_cq_entry)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_cq_entry_raw)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_qp_entry)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_qp_entry_raw)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_cm_id_entry)(struct sk_buff *, struct rdma_cm_id *);\n\tint (*fill_res_srq_entry)(struct sk_buff *, struct ib_srq *);\n\tint (*fill_res_srq_entry_raw)(struct sk_buff *, struct ib_srq *);\n\tint (*enable_driver)(struct ib_device *);\n\tvoid (*dealloc_driver)(struct ib_device *);\n\tvoid (*iw_add_ref)(struct ib_qp *);\n\tvoid (*iw_rem_ref)(struct ib_qp *);\n\tstruct ib_qp * (*iw_get_qp)(struct ib_device *, int);\n\tint (*iw_connect)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_accept)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_reject)(struct iw_cm_id *, const void *, u8);\n\tint (*iw_create_listen)(struct iw_cm_id *, int);\n\tint (*iw_destroy_listen)(struct iw_cm_id *);\n\tint (*counter_bind_qp)(struct rdma_counter *, struct ib_qp *, u32);\n\tint (*counter_unbind_qp)(struct ib_qp *, u32);\n\tint (*counter_dealloc)(struct rdma_counter *);\n\tstruct rdma_hw_stats * (*counter_alloc_stats)(struct rdma_counter *);\n\tint (*counter_update_stats)(struct rdma_counter *);\n\tvoid (*counter_init)(struct rdma_counter *);\n\tint (*fill_stat_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*query_ucontext)(struct ib_ucontext *, struct uverbs_attr_bundle *);\n\tint (*get_numa_node)(struct ib_device *);\n\tstruct ib_device * (*add_sub_dev)(struct ib_device *, enum rdma_nl_dev_type, const char *);\n\tvoid (*del_sub_dev)(struct ib_device *);\n\tvoid (*ufile_hw_cleanup)(struct ib_uverbs_file *);\n\tvoid (*report_port_event)(struct ib_device *, struct net_device *, long unsigned int);\n\tsize_t size_ib_ah;\n\tsize_t size_ib_counters;\n\tsize_t size_ib_cq;\n\tsize_t size_ib_dmah;\n\tsize_t size_ib_mw;\n\tsize_t size_ib_pd;\n\tsize_t size_ib_qp;\n\tsize_t size_ib_rwq_ind_table;\n\tsize_t size_ib_srq;\n\tsize_t size_ib_ucontext;\n\tsize_t size_ib_xrcd;\n\tsize_t size_rdma_counter;\n};\n\nstruct ib_odp_caps {\n\tuint64_t general_caps;\n\tstruct {\n\t\tuint32_t rc_odp_caps;\n\t\tuint32_t uc_odp_caps;\n\t\tuint32_t ud_odp_caps;\n\t\tuint32_t xrc_odp_caps;\n\t} per_transport_caps;\n};\n\nstruct ib_rss_caps {\n\tu32 supported_qpts;\n\tu32 max_rwq_indirection_tables;\n\tu32 max_rwq_indirection_table_size;\n};\n\nstruct ib_tm_caps {\n\tu32 max_rndv_hdr_size;\n\tu32 max_num_tags;\n\tu32 flags;\n\tu32 max_ops;\n\tu32 max_sge;\n};\n\nstruct ib_device_attr {\n\tu64 fw_ver;\n\t__be64 sys_image_guid;\n\tu64 max_mr_size;\n\tu64 page_size_cap;\n\tu32 vendor_id;\n\tu32 vendor_part_id;\n\tu32 hw_ver;\n\tint max_qp;\n\tint max_qp_wr;\n\tu64 device_cap_flags;\n\tu64 kernel_cap_flags;\n\tint max_send_sge;\n\tint max_recv_sge;\n\tint max_sge_rd;\n\tint max_cq;\n\tint max_cqe;\n\tint max_mr;\n\tint max_pd;\n\tint max_qp_rd_atom;\n\tint max_ee_rd_atom;\n\tint max_res_rd_atom;\n\tint max_qp_init_rd_atom;\n\tint max_ee_init_rd_atom;\n\tenum ib_atomic_cap atomic_cap;\n\tenum ib_atomic_cap masked_atomic_cap;\n\tint max_ee;\n\tint max_rdd;\n\tint max_mw;\n\tint max_raw_ipv6_qp;\n\tint max_raw_ethy_qp;\n\tint max_mcast_grp;\n\tint max_mcast_qp_attach;\n\tint max_total_mcast_qp_attach;\n\tint max_ah;\n\tint max_srq;\n\tint max_srq_wr;\n\tint max_srq_sge;\n\tunsigned int max_fast_reg_page_list_len;\n\tunsigned int max_pi_fast_reg_page_list_len;\n\tu16 max_pkeys;\n\tu8 local_ca_ack_delay;\n\tint sig_prot_cap;\n\tint sig_guard_cap;\n\tstruct ib_odp_caps odp_caps;\n\tuint64_t timestamp_mask;\n\tuint64_t hca_core_clock;\n\tstruct ib_rss_caps rss_caps;\n\tu32 max_wq_type_rq;\n\tu32 raw_packet_caps;\n\tstruct ib_tm_caps tm_caps;\n\tstruct ib_cq_caps cq_caps;\n\tu64 max_dm_size;\n\tu32 max_sgl_rd;\n};\n\nstruct hw_stats_device_data;\n\nstruct rdmacg_device {\n\tstruct list_head dev_node;\n\tstruct list_head rpools;\n\tchar *name;\n};\n\nstruct rdma_restrack_root;\n\nstruct uapi_definition;\n\nstruct ib_port_data;\n\nstruct rdma_link_ops;\n\nstruct ib_device {\n\tstruct device *dma_device;\n\tstruct ib_device_ops ops;\n\tchar name[64];\n\tstruct callback_head callback_head;\n\tstruct list_head event_handler_list;\n\tstruct rw_semaphore event_handler_rwsem;\n\tspinlock_t qp_open_list_lock;\n\tstruct rw_semaphore client_data_rwsem;\n\tstruct xarray client_data;\n\tstruct mutex unregistration_lock;\n\trwlock_t cache_lock;\n\tstruct ib_port_data *port_data;\n\tint num_comp_vectors;\n\tunion {\n\t\tstruct device dev;\n\t\tstruct ib_core_device coredev;\n\t};\n\tconst struct attribute_group *groups[4];\n\tu8 hw_stats_attr_index;\n\tu64 uverbs_cmd_mask;\n\tchar node_desc[64];\n\t__be64 node_guid;\n\tu32 local_dma_lkey;\n\tu16 is_switch: 1;\n\tu16 kverbs_provider: 1;\n\tu16 use_cq_dim: 1;\n\tu8 node_type;\n\tu32 phys_port_cnt;\n\tstruct ib_device_attr attrs;\n\tstruct hw_stats_device_data *hw_stats_data;\n\tstruct rdmacg_device cg_device;\n\tu32 index;\n\tspinlock_t cq_pools_lock;\n\tstruct list_head cq_pools[3];\n\tstruct rdma_restrack_root *res;\n\tconst struct uapi_definition *driver_def;\n\trefcount_t refcount;\n\tstruct completion unreg_completion;\n\tstruct work_struct unregistration_work;\n\tconst struct rdma_link_ops *link_ops;\n\tstruct mutex compat_devs_mutex;\n\tstruct xarray compat_devs;\n\tchar iw_ifname[16];\n\tu32 iw_driver_flags;\n\tu32 lag_flags;\n\tstruct mutex subdev_lock;\n\tstruct list_head subdev_list_head;\n\tenum rdma_nl_dev_type type;\n\tstruct ib_device *parent;\n\tstruct list_head subdev_list;\n\tenum rdma_nl_name_assign_type name_assign_type;\n};\n\nstruct ib_device_modify {\n\tu64 sys_image_guid;\n\tchar node_desc[64];\n};\n\nstruct ib_dm {\n\tstruct ib_device *device;\n\tu32 length;\n\tu32 flags;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_dm_alloc_attr {\n\tu64 length;\n\tu32 alignment;\n\tu32 flags;\n};\n\nstruct ib_dm_mr_attr {\n\tu64 length;\n\tu64 offset;\n\tu32 access_flags;\n};\n\nstruct ib_dmah {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tstruct rdma_restrack_entry res;\n\tu32 cpu_id;\n\tenum tph_mem_type mem_type;\n\tatomic_t usecnt;\n\tu8 ph;\n\tu8 valid_fields;\n};\n\nstruct ib_event {\n\tstruct ib_device *device;\n\tunion {\n\t\tstruct ib_cq *cq;\n\t\tstruct ib_qp *qp;\n\t\tstruct ib_srq *srq;\n\t\tstruct ib_wq *wq;\n\t\tu32 port_num;\n\t} element;\n\tenum ib_event_type event;\n};\n\nstruct ib_flow {\n\tstruct ib_qp *qp;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n};\n\nstruct ib_flow_action {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tenum ib_flow_action_type type;\n\tatomic_t usecnt;\n};\n\nstruct ib_flow_eth_filter {\n\tu8 dst_mac[6];\n\tu8 src_mac[6];\n\t__be16 ether_type;\n\t__be16 vlan_tag;\n};\n\nstruct ib_flow_spec_eth {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_eth_filter val;\n\tstruct ib_flow_eth_filter mask;\n};\n\nstruct ib_flow_ib_filter {\n\t__be16 dlid;\n\t__u8 sl;\n};\n\nstruct ib_flow_spec_ib {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ib_filter val;\n\tstruct ib_flow_ib_filter mask;\n};\n\nstruct ib_flow_ipv4_filter {\n\t__be32 src_ip;\n\t__be32 dst_ip;\n\tu8 proto;\n\tu8 tos;\n\tu8 ttl;\n\tu8 flags;\n};\n\nstruct ib_flow_spec_ipv4 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv4_filter val;\n\tstruct ib_flow_ipv4_filter mask;\n};\n\nstruct ib_flow_tcp_udp_filter {\n\t__be16 dst_port;\n\t__be16 src_port;\n};\n\nstruct ib_flow_spec_tcp_udp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tcp_udp_filter val;\n\tstruct ib_flow_tcp_udp_filter mask;\n};\n\nstruct ib_flow_ipv6_filter {\n\tu8 src_ip[16];\n\tu8 dst_ip[16];\n\t__be32 flow_label;\n\tu8 next_hdr;\n\tu8 traffic_class;\n\tu8 hop_limit;\n} __attribute__((packed));\n\nstruct ib_flow_spec_ipv6 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv6_filter val;\n\tstruct ib_flow_ipv6_filter mask;\n};\n\nstruct ib_flow_tunnel_filter {\n\t__be32 tunnel_id;\n};\n\nstruct ib_flow_spec_tunnel {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tunnel_filter val;\n\tstruct ib_flow_tunnel_filter mask;\n};\n\nstruct ib_flow_esp_filter {\n\t__be32 spi;\n\t__be32 seq;\n};\n\nstruct ib_flow_spec_esp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_esp_filter val;\n\tstruct ib_flow_esp_filter mask;\n};\n\nstruct ib_flow_gre_filter {\n\t__be16 c_ks_res0_ver;\n\t__be16 protocol;\n\t__be32 key;\n};\n\nstruct ib_flow_spec_gre {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_gre_filter val;\n\tstruct ib_flow_gre_filter mask;\n};\n\nstruct ib_flow_mpls_filter {\n\t__be32 tag;\n};\n\nstruct ib_flow_spec_mpls {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_mpls_filter val;\n\tstruct ib_flow_mpls_filter mask;\n};\n\nstruct ib_flow_spec_action_tag {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tu32 tag_id;\n};\n\nstruct ib_flow_spec_action_drop {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n};\n\nstruct ib_flow_spec_action_handle {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_flow_action *act;\n};\n\nstruct ib_flow_spec_action_count {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_counters *counters;\n};\n\nunion ib_flow_spec {\n\tstruct {\n\t\tu32 type;\n\t\tu16 size;\n\t};\n\tstruct ib_flow_spec_eth eth;\n\tstruct ib_flow_spec_ib ib;\n\tstruct ib_flow_spec_ipv4 ipv4;\n\tstruct ib_flow_spec_tcp_udp tcp_udp;\n\tstruct ib_flow_spec_ipv6 ipv6;\n\tstruct ib_flow_spec_tunnel tunnel;\n\tstruct ib_flow_spec_esp esp;\n\tstruct ib_flow_spec_gre gre;\n\tstruct ib_flow_spec_mpls mpls;\n\tstruct ib_flow_spec_action_tag flow_tag;\n\tstruct ib_flow_spec_action_drop drop;\n\tstruct ib_flow_spec_action_handle action;\n\tstruct ib_flow_spec_action_count flow_count;\n};\n\nstruct ib_flow_attr {\n\tenum ib_flow_attr_type type;\n\tu16 size;\n\tu16 priority;\n\tu32 flags;\n\tu8 num_of_specs;\n\tu32 port;\n\tunion ib_flow_spec flows[0];\n};\n\nunion ib_gid {\n\tu8 raw[16];\n\tstruct {\n\t\t__be64 subnet_prefix;\n\t\t__be64 interface_id;\n\t} global;\n};\n\nstruct ib_gid_attr {\n\tstruct net_device *ndev;\n\tstruct ib_device *device;\n\tunion ib_gid gid;\n\tenum ib_gid_type gid_type;\n\tu16 index;\n\tu32 port_num;\n};\n\nstruct ib_global_route {\n\tconst struct ib_gid_attr *sgid_attr;\n\tunion ib_gid dgid;\n\tu32 flow_label;\n\tu8 sgid_index;\n\tu8 hop_limit;\n\tu8 traffic_class;\n};\n\nstruct ib_grh {\n\t__be32 version_tclass_flow;\n\t__be16 paylen;\n\tu8 next_hdr;\n\tu8 hop_limit;\n\tunion ib_gid sgid;\n\tunion ib_gid dgid;\n};\n\nstruct ib_sig_attrs;\n\nstruct ib_mr {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tu32 lkey;\n\tu32 rkey;\n\tu64 iova;\n\tu64 length;\n\tunsigned int page_size;\n\tenum ib_mr_type type;\n\tbool need_inval;\n\tunion {\n\t\tstruct ib_uobject *uobject;\n\t\tstruct list_head qp_entry;\n\t};\n\tstruct ib_dm *dm;\n\tstruct ib_sig_attrs *sig_attrs;\n\tstruct ib_dmah *dmah;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_sig_err {\n\tenum ib_sig_err_type err_type;\n\tu32 expected;\n\tu32 actual;\n\tu64 sig_err_offset;\n\tu32 key;\n};\n\nstruct ib_mr_status {\n\tu32 fail_status;\n\tstruct ib_sig_err sig_err;\n};\n\nstruct ib_mw {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tu32 rkey;\n\tenum ib_mw_type type;\n};\n\nstruct ib_pd {\n\tu32 local_dma_lkey;\n\tu32 flags;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 unsafe_global_rkey;\n\tstruct ib_mr *__internal_mr;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_port_attr {\n\tu64 subnet_prefix;\n\tenum ib_port_state state;\n\tenum ib_mtu max_mtu;\n\tenum ib_mtu active_mtu;\n\tu32 phys_mtu;\n\tint gid_tbl_len;\n\tunsigned int ip_gids: 1;\n\tu32 port_cap_flags;\n\tu32 max_msg_sz;\n\tu32 bad_pkey_cntr;\n\tu32 qkey_viol_cntr;\n\tu16 pkey_tbl_len;\n\tu32 sm_lid;\n\tu32 lid;\n\tu8 lmc;\n\tu8 max_vl_num;\n\tu8 sm_sl;\n\tu8 subnet_timeout;\n\tu8 init_type_reply;\n\tu8 active_width;\n\tu16 active_speed;\n\tu8 phys_state;\n\tu16 port_cap_flags2;\n};\n\nstruct ib_pkey_cache;\n\nstruct ib_gid_table;\n\nstruct ib_port_cache {\n\tu64 subnet_prefix;\n\tstruct ib_pkey_cache *pkey;\n\tstruct ib_gid_table *gid;\n\tu8 lmc;\n\tenum ib_port_state port_state;\n\tenum ib_port_state last_port_state;\n};\n\nstruct ib_port_immutable {\n\tint pkey_tbl_len;\n\tint gid_tbl_len;\n\tu32 core_cap_flags;\n\tu32 max_mad_size;\n};\n\nstruct rdma_counter_mode {\n\tenum rdma_nl_counter_mode mode;\n\tenum rdma_nl_counter_mask mask;\n\tstruct auto_mode_param param;\n\tbool bind_opcnt;\n};\n\nstruct rdma_port_counter {\n\tstruct rdma_counter_mode mode;\n\tstruct rdma_hw_stats *hstats;\n\tunsigned int num_counters;\n\tstruct mutex lock;\n};\n\nstruct ib_port;\n\nstruct ib_port_data {\n\tstruct ib_device *ib_dev;\n\tstruct ib_port_immutable immutable;\n\tspinlock_t pkey_list_lock;\n\tspinlock_t netdev_lock;\n\tstruct list_head pkey_list;\n\tstruct ib_port_cache cache;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\tstruct hlist_node ndev_hash_link;\n\tstruct rdma_port_counter port_counter;\n\tstruct ib_port *sysfs;\n};\n\nstruct ib_port_modify {\n\tu32 set_port_cap_mask;\n\tu32 clr_port_cap_mask;\n\tu8 init_type;\n};\n\nstruct ib_qp_security;\n\nstruct ib_port_pkey {\n\tenum port_pkey_state state;\n\tu16 pkey_index;\n\tu32 port_num;\n\tstruct list_head qp_list;\n\tstruct list_head to_error_list;\n\tstruct ib_qp_security *sec;\n};\n\nstruct ib_ports_pkeys {\n\tstruct ib_port_pkey main;\n\tstruct ib_port_pkey alt;\n};\n\nstruct ib_uqp_object;\n\nstruct ib_qp {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tspinlock_t mr_lock;\n\tint mrs_used;\n\tstruct list_head rdma_mrs;\n\tstruct list_head sig_mrs;\n\tstruct ib_srq *srq;\n\tstruct completion srq_completion;\n\tstruct ib_xrcd *xrcd;\n\tstruct list_head xrcd_list;\n\tatomic_t usecnt;\n\tstruct list_head open_list;\n\tstruct ib_qp *real_qp;\n\tstruct ib_uqp_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid (*registered_event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tconst struct ib_gid_attr *av_sgid_attr;\n\tconst struct ib_gid_attr *alt_path_sgid_attr;\n\tu32 qp_num;\n\tu32 max_write_sge;\n\tu32 max_read_sge;\n\tenum ib_qp_type qp_type;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tstruct ib_qp_security *qp_sec;\n\tu32 port;\n\tbool integrity_en;\n\tstruct rdma_restrack_entry res;\n\tstruct rdma_counter *counter;\n};\n\nstruct ib_qp_cap {\n\tu32 max_send_wr;\n\tu32 max_recv_wr;\n\tu32 max_send_sge;\n\tu32 max_recv_sge;\n\tu32 max_inline_data;\n\tu32 max_rdma_ctxs;\n};\n\nstruct roce_ah_attr {\n\tu8 dmac[6];\n};\n\nstruct opa_ah_attr {\n\tu32 dlid;\n\tu8 src_path_bits;\n\tbool make_grd;\n};\n\nstruct rdma_ah_attr {\n\tstruct ib_global_route grh;\n\tu8 sl;\n\tu8 static_rate;\n\tu32 port_num;\n\tu8 ah_flags;\n\tenum rdma_ah_attr_type type;\n\tunion {\n\t\tstruct ib_ah_attr ib;\n\t\tstruct roce_ah_attr roce;\n\t\tstruct opa_ah_attr opa;\n\t};\n};\n\nstruct ib_qp_attr {\n\tenum ib_qp_state qp_state;\n\tenum ib_qp_state cur_qp_state;\n\tenum ib_mtu path_mtu;\n\tenum ib_mig_state path_mig_state;\n\tu32 qkey;\n\tu32 rq_psn;\n\tu32 sq_psn;\n\tu32 dest_qp_num;\n\tint qp_access_flags;\n\tstruct ib_qp_cap cap;\n\tstruct rdma_ah_attr ah_attr;\n\tstruct rdma_ah_attr alt_ah_attr;\n\tu16 pkey_index;\n\tu16 alt_pkey_index;\n\tu8 en_sqd_async_notify;\n\tu8 sq_draining;\n\tu8 max_rd_atomic;\n\tu8 max_dest_rd_atomic;\n\tu8 min_rnr_timer;\n\tu32 port_num;\n\tu8 timeout;\n\tu8 retry_cnt;\n\tu8 rnr_retry;\n\tu32 alt_port_num;\n\tu8 alt_timeout;\n\tu32 rate_limit;\n\tstruct net_device *xmit_slave;\n};\n\nstruct ib_qp_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tstruct ib_srq *srq;\n\tstruct ib_xrcd *xrcd;\n\tstruct ib_qp_cap cap;\n\tenum ib_sig_type sq_sig_type;\n\tenum ib_qp_type qp_type;\n\tu32 create_flags;\n\tu32 port_num;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tu32 source_qpn;\n};\n\nstruct ib_qp_security {\n\tstruct ib_qp *qp;\n\tstruct ib_device *dev;\n\tstruct mutex mutex;\n\tstruct ib_ports_pkeys *ports_pkeys;\n\tstruct list_head shared_qp_list;\n\tvoid *security;\n\tbool destroying;\n\tatomic_t error_list_count;\n\tstruct completion error_complete;\n\tint error_comps_pending;\n};\n\nstruct rdma_cgroup;\n\nstruct ib_rdmacg_object {\n\tstruct rdma_cgroup *cg;\n};\n\nstruct ib_recv_wr {\n\tstruct ib_recv_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n};\n\nstruct ib_rwq_ind_table {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 ind_tbl_num;\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_rwq_ind_table_init_attr {\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_send_wr {\n\tstruct ib_send_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n\tenum ib_wr_opcode opcode;\n\tint send_flags;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n};\n\nstruct ib_sge {\n\tu64 addr;\n\tu32 length;\n\tu32 lkey;\n};\n\nstruct ib_t10_dif_domain {\n\tenum ib_t10_dif_bg_type bg_type;\n\tu16 pi_interval;\n\tu16 bg;\n\tu16 app_tag;\n\tu32 ref_tag;\n\tbool ref_remap;\n\tbool app_escape;\n\tbool ref_escape;\n\tu16 apptag_check_mask;\n};\n\nstruct ib_sig_domain {\n\tenum ib_signature_type sig_type;\n\tunion {\n\t\tstruct ib_t10_dif_domain dif;\n\t} sig;\n};\n\nstruct ib_sig_attrs {\n\tu8 check_mask;\n\tstruct ib_sig_domain mem;\n\tstruct ib_sig_domain wire;\n\tint meta_length;\n};\n\nstruct ib_usrq_object;\n\nstruct ib_srq {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_usrq_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tenum ib_srq_type srq_type;\n\tatomic_t usecnt;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t\tu32 srq_num;\n\t\t\t} xrc;\n\t\t};\n\t} ext;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_srq_attr {\n\tu32 max_wr;\n\tu32 max_sge;\n\tu32 srq_limit;\n};\n\nstruct ib_srq_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tstruct ib_srq_attr attr;\n\tenum ib_srq_type srq_type;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t} xrc;\n\t\t\tstruct {\n\t\t\t\tu32 max_num_tags;\n\t\t\t} tag_matching;\n\t\t};\n\t} ext;\n};\n\nstruct ib_ucontext {\n\tstruct ib_device *device;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_rdmacg_object cg_obj;\n\tu64 enabled_caps;\n\tstruct rdma_restrack_entry res;\n\tstruct xarray mmap_xa;\n};\n\nstruct ib_udata {\n\tconst void *inbuf;\n\tvoid *outbuf;\n\tsize_t inlen;\n\tsize_t outlen;\n};\n\nstruct uverbs_api_object;\n\nstruct ib_uobject {\n\tu64 user_handle;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_ucontext *context;\n\tvoid *object;\n\tstruct list_head list;\n\tstruct ib_rdmacg_object cg_obj;\n\tint id;\n\tstruct kref ref;\n\tatomic_t usecnt;\n\tstruct callback_head rcu;\n\tconst struct uverbs_api_object *uapi_object;\n};\n\nstruct ib_wc {\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tenum ib_wc_status status;\n\tenum ib_wc_opcode opcode;\n\tu32 vendor_err;\n\tu32 byte_len;\n\tstruct ib_qp *qp;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tu32 src_qp;\n\tu32 slid;\n\tint wc_flags;\n\tu16 pkey_index;\n\tu8 sl;\n\tu8 dlid_path_bits;\n\tu32 port_num;\n\tu8 smac[6];\n\tu16 vlan_id;\n\tu8 network_hdr_type;\n};\n\nstruct ib_uwq_object;\n\nstruct ib_wq {\n\tstruct ib_device *device;\n\tstruct ib_uwq_object *uobject;\n\tvoid *wq_context;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tstruct ib_pd *pd;\n\tstruct ib_cq *cq;\n\tu32 wq_num;\n\tenum ib_wq_state state;\n\tenum ib_wq_type wq_type;\n\tatomic_t usecnt;\n};\n\nstruct ib_wq_attr {\n\tenum ib_wq_state wq_state;\n\tenum ib_wq_state curr_wq_state;\n\tu32 flags;\n\tu32 flags_mask;\n};\n\nstruct ib_wq_init_attr {\n\tvoid *wq_context;\n\tenum ib_wq_type wq_type;\n\tu32 max_wr;\n\tu32 max_sge;\n\tstruct ib_cq *cq;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tu32 create_flags;\n};\n\nstruct ib_xrcd {\n\tstruct ib_device *device;\n\tatomic_t usecnt;\n\tstruct inode *inode;\n\tstruct rw_semaphore tgt_qps_rwsem;\n\tstruct xarray tgt_qps;\n};\n\nstruct icmp6_err {\n\tint err;\n\tint fatal;\n};\n\nstruct icmp6_ext_iio_addr6_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\tstruct in6_addr addr6;\n};\n\nstruct icmp6_filter {\n\t__u32 data[8];\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 router: 1;\n\t__u32 solicited: 1;\n\t__u32 override: 1;\n\t__u32 reserved: 29;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 managed: 1;\n\t__u8 other: 1;\n\t__u8 home_agent: 1;\n\t__u8 router_pref: 2;\n\t__u8 reserved: 3;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 version: 4;\n\t__u8 reserved1: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[7];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6_msg {\n\tstruct sk_buff *skb;\n\tint offset;\n\tuint8_t type;\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct id_bitmap {\n\tlong unsigned int map[4];\n};\n\nstruct id_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tunion {\n\t\t__u32 ruid;\n\t\t__u32 rgid;\n\t} r;\n\tunion {\n\t\t__u32 euid;\n\t\t__u32 egid;\n\t} e;\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[16];\n};\n\nstruct idal_buffer {\n\tsize_t size;\n\tsize_t page_order;\n\tdma64_t data[0];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n};\n\nstruct idmap_key {\n\tbool map_up;\n\tu32 id;\n\tu32 count;\n};\n\nstruct idset {\n\tint num_ssid;\n\tint num_id;\n\tlong unsigned int bitmap[0];\n};\n\nstruct if6_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tint offset;\n};\n\nstruct if_dqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n};\n\nstruct if_dqinfo {\n\t__u64 dqi_bgrace;\n\t__u64 dqi_igrace;\n\t__u32 dqi_flags;\n\t__u32 dqi_valid;\n};\n\nstruct if_nextdqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n\t__u32 dqb_id;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa6_config {\n\tconst struct in6_addr *pfx;\n\tunsigned int plen;\n\tu8 ifa_proto;\n\tconst struct in6_addr *peer_pfx;\n\tu32 rt_priority;\n\tu32 ifa_flags;\n\tu32 preferred_lft;\n\tu32 valid_lft;\n\tu16 scope;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifaddrlblmsg {\n\t__u8 ifal_family;\n\t__u8 __ifal_reserved;\n\t__u8 ifal_prefixlen;\n\t__u8 ifal_flags;\n\t__u32 ifal_index;\n\t__u32 ifal_seq;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifreq;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_cacheinfo {\n\t__u32 max_reasm_len;\n\t__u32 tstamp;\n\t__u32 reachable_time;\n\t__u32 retrans_time;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct inet6_dev;\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct igmp6_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct igmp6_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *im;\n};\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpmsg {\n\t__u32 unused1;\n\t__u32 unused2;\n\tunsigned char im_msgtype;\n\tunsigned char im_mbz;\n\tunsigned char im_vif;\n\tunsigned char im_vif_hi;\n\tstruct in_addr im_src;\n\tstruct in_addr im_dst;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 resv: 4;\n\t__u8 suppress: 1;\n\t__u8 qrv: 3;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct ima_algo_desc {\n\tstruct crypto_shash *tfm;\n\tenum hash_algo algo;\n};\n\nstruct ima_digest_data_hdr {\n\tu8 algo;\n\tu8 length;\n\tunion {\n\t\tstruct {\n\t\t\tu8 unused;\n\t\t\tu8 type;\n\t\t} sha1;\n\t\tstruct {\n\t\t\tu8 type;\n\t\t\tu8 algo;\n\t\t} ng;\n\t\tu8 data[2];\n\t} xattr;\n};\n\nstruct ima_digest_data {\n\tunion {\n\t\tstruct {\n\t\t\tu8 algo;\n\t\t\tu8 length;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tu8 unused;\n\t\t\t\t\tu8 type;\n\t\t\t\t} sha1;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 type;\n\t\t\t\t\tu8 algo;\n\t\t\t\t} ng;\n\t\t\t\tu8 data[2];\n\t\t\t} xattr;\n\t\t};\n\t\tstruct ima_digest_data_hdr hdr;\n\t};\n\tu8 digest[0];\n};\n\nstruct modsig;\n\nstruct ima_iint_cache;\n\nstruct ima_event_data {\n\tstruct ima_iint_cache *iint;\n\tstruct file *file;\n\tconst unsigned char *filename;\n\tstruct evm_ima_xattr_data *xattr_value;\n\tint xattr_len;\n\tconst struct modsig *modsig;\n\tconst char *violation;\n\tconst void *buf;\n\tint buf_len;\n};\n\nstruct ima_field_data {\n\tu8 *data;\n\tu32 len;\n};\n\nstruct ima_file_id {\n\t__u8 hash_type;\n\t__u8 hash_algorithm;\n\t__u8 hash[64];\n};\n\nstruct ima_h_table {\n\tatomic_long_t len;\n\tatomic_long_t violations;\n\tstruct hlist_head queue[1024];\n};\n\nstruct integrity_inode_attributes {\n\tu64 version;\n\tlong unsigned int ino;\n\tdev_t dev;\n};\n\nstruct ima_iint_cache {\n\tstruct mutex mutex;\n\tstruct integrity_inode_attributes real_inode;\n\tlong unsigned int flags;\n\tlong unsigned int measured_pcrs;\n\tlong unsigned int atomic_flags;\n\tenum integrity_status ima_file_status: 4;\n\tenum integrity_status ima_mmap_status: 4;\n\tenum integrity_status ima_bprm_status: 4;\n\tenum integrity_status ima_read_status: 4;\n\tenum integrity_status ima_creds_status: 4;\n\tstruct ima_digest_data *ima_hash;\n};\n\nstruct ima_kexec_hdr {\n\tu16 version;\n\tu16 _reserved0;\n\tu32 _reserved1;\n\tu64 buffer_size;\n\tu64 count;\n};\n\nstruct ima_key_entry {\n\tstruct list_head list;\n\tvoid *payload;\n\tsize_t payload_len;\n\tchar *keyring_name;\n};\n\nstruct ima_max_digest_data {\n\tstruct ima_digest_data_hdr hdr;\n\tu8 digest[64];\n};\n\nstruct ima_template_entry;\n\nstruct ima_queue_entry {\n\tstruct hlist_node hnext;\n\tstruct list_head later;\n\tstruct ima_template_entry *entry;\n};\n\nstruct ima_rule_opt_list;\n\nstruct ima_template_desc;\n\nstruct ima_rule_entry {\n\tstruct list_head list;\n\tint action;\n\tunsigned int flags;\n\tenum ima_hooks func;\n\tint mask;\n\tlong unsigned int fsmagic;\n\tuuid_t fsuuid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t fowner;\n\tkgid_t fgroup;\n\tbool (*uid_op)(kuid_t, kuid_t);\n\tbool (*gid_op)(kgid_t, kgid_t);\n\tbool (*fowner_op)(vfsuid_t, kuid_t);\n\tbool (*fgroup_op)(vfsgid_t, kgid_t);\n\tint pcr;\n\tunsigned int allowed_algos;\n\tstruct {\n\t\tvoid *rule;\n\t\tchar *args_p;\n\t\tint type;\n\t} lsm[6];\n\tchar *fsname;\n\tchar *fs_subtype;\n\tstruct ima_rule_opt_list *keyrings;\n\tstruct ima_rule_opt_list *label;\n\tstruct ima_template_desc *template;\n};\n\nstruct ima_rule_opt_list {\n\tsize_t count;\n\tchar *items[0];\n};\n\nstruct ima_template_field;\n\nstruct ima_template_desc {\n\tstruct list_head list;\n\tchar *name;\n\tchar *fmt;\n\tint num_fields;\n\tconst struct ima_template_field **fields;\n};\n\nstruct tpm_digest;\n\nstruct ima_template_entry {\n\tint pcr;\n\tstruct tpm_digest *digests;\n\tstruct ima_template_desc *template_desc;\n\tu32 template_data_len;\n\tstruct ima_field_data template_data[0];\n};\n\nstruct ima_template_field {\n\tconst char field_id[16];\n\tint (*field_init)(struct ima_event_data *, struct ima_field_data *);\n\tvoid (*field_show)(struct seq_file *, enum ima_show_type, struct ima_field_data *);\n};\n\nstruct in6_flowlabel_req {\n\tstruct in6_addr flr_dst;\n\t__be32 flr_label;\n\t__u8 flr_action;\n\t__u8 flr_share;\n\t__u16 flr_flags;\n\t__u16 flr_expires;\n\t__u16 flr_linger;\n\t__u32 __flr_pad;\n};\n\nstruct in6_ifreq {\n\tstruct in6_addr ifr6_addr;\n\t__u32 ifr6_prefixlen;\n\tint ifr6_ifindex;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\t__u32 rtmsg_type;\n\t__u16 rtmsg_dst_len;\n\t__u16 rtmsg_src_len;\n\t__u32 rtmsg_metric;\n\tlong unsigned int rtmsg_info;\n\t__u32 rtmsg_flags;\n\tint rtmsg_ifindex;\n};\n\nstruct in6_validator_info {\n\tstruct in6_addr i6vi_addr;\n\tstruct inet6_dev *i6vi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[1];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct indicator_t {\n\tu32 ind;\n\tatomic_t count;\n};\n\nstruct ipv6_txoptions;\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n\tu8 dontfrag: 1;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_ra_rtr_pref;\n\t__s32 rtr_probe_interval;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n\tenum addr_type_t type;\n\tbool force_rt_scope_universe;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_skb_parm;\n\nstruct inet6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 dsthao;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tshort unsigned int addr_type;\n\tstruct in6_addr v6_rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n\tstruct inet6_cork base6;\n};\n\nstruct ipv6_pinfo;\n\nstruct ipv6_fl_socklist;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct proto_ops;\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n\tstruct sk_buff * (*tw_validate_xmit_skb)(struct sock *, struct net_device *, struct sk_buff *);\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tstruct dfltcc_state dfltcc_state;\n\tunsigned char working_window[36864];\n};\n\nstruct init_sccb {\n\tstruct sccb_header header;\n\tu16 _reserved;\n\tu16 mask_length;\n\tu8 masks[4084];\n};\n\nstruct init_sequence {\n\tint (*init_func)(void);\n\tvoid (*exit_func)(void);\n};\n\nstruct inode_defrag {\n\tstruct rb_node rb_node;\n\tu64 ino;\n\tu64 transid;\n\tu64 root;\n\tu32 extent_thresh;\n};\n\nstruct inode_fs_paths {\n\tstruct btrfs_path *btrfs_path;\n\tstruct btrfs_root *fs_root;\n\tstruct btrfs_data_container *fspath;\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inode_security_struct {\n\tstruct inode *inode;\n\tstruct list_head list;\n\tu32 task_sid;\n\tu32 sid;\n\tu16 sclass;\n\tunsigned char initialized;\n\tspinlock_t lock;\n};\n\nstruct inode_switch_wbs_context {\n\tstruct llist_node list;\n\tstruct inode *inodes[0];\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[12];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[1];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[2];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[12];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[12];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[1];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[2];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insn {\n\tu16 opcode;\n\ts32 offset;\n} __attribute__((packed));\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nstruct insn_ril {\n\tu8 opc0;\n\tu8 reg: 4;\n\tu8 opc1: 4;\n\ts32 disp;\n} __attribute__((packed));\n\nstruct insn_ssf {\n\tu64 opc1: 8;\n\tu64 r3: 4;\n\tu64 opc2: 4;\n\tu64 b1: 4;\n\tu64 d1: 12;\n\tu64 b2: 4;\n\tu64 d2: 12;\n} __attribute__((packed));\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct io {\n\tlong unsigned int error_bits;\n\tatomic_t count;\n\tstruct dm_io_client *client;\n\tio_notify_fn callback;\n\tvoid *context;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n\tlong: 64;\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_btrfs_cmd {\n\tstruct btrfs_uring_encoded_data *data;\n\tstruct btrfs_uring_priv *priv;\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n\tspinlock_t lock;\n\tstruct xarray icq_tree;\n\tstruct io_cq *icq_hint;\n\tstruct hlist_head icq_list;\n\tstruct work_struct release_work;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_err_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[1];\n\tlong unsigned int sqe_op[2];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_subchannel_dma_area {\n\tstruct ccw1 sense_ccw;\n};\n\nstruct tm_orb {\n\tu32 intparm;\n\tu32 key: 4;\n\tchar: 4;\n\tchar: 5;\n\tu32 b: 1;\n\tshort: 2;\n\tu32 lpm: 8;\n\tchar: 7;\n\tu32 x: 1;\n\tdma32_t tcw;\n\tu32 prio: 8;\n\tshort: 8;\n\tu32 rsvpgm: 8;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion orb {\n\tstruct cmd_orb cmd;\n\tstruct tm_orb tm;\n\tstruct eadm_orb eadm;\n};\n\nstruct io_subchannel_private {\n\tunion orb orb;\n\tstruct ccw_device *cdev;\n\tstruct {\n\t\tunsigned int suspend: 1;\n\t\tunsigned int prefetch: 1;\n\t\tunsigned int inter: 1;\n\t} __attribute__((packed)) options;\n\tstruct io_subchannel_dma_area *dma_area;\n\tdma_addr_t dma_area_dma;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tlb_area {\n\tlong unsigned int used;\n\tunsigned int index;\n\tspinlock_t lock;\n};\n\nstruct io_tlb_slot;\n\nstruct io_tlb_pool {\n\tphys_addr_t start;\n\tphys_addr_t end;\n\tvoid *vaddr;\n\tlong unsigned int nslabs;\n\tbool late_alloc;\n\tunsigned int nareas;\n\tunsigned int area_nslabs;\n\tstruct io_tlb_area *areas;\n\tstruct io_tlb_slot *slots;\n};\n\nstruct io_tlb_mem {\n\tstruct io_tlb_pool defpool;\n\tlong unsigned int nslabs;\n\tstruct dentry *debugfs;\n\tbool force_bounce;\n\tbool for_alloc;\n\tatomic_long_t total_used;\n\tatomic_long_t used_hiwater;\n\tatomic_long_t transient_nslabs;\n};\n\nstruct io_tlb_slot {\n\tphys_addr_t orig_addr;\n\tsize_t alloc_size;\n\tshort unsigned int list;\n\tshort unsigned int pad_slots;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 64;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[64];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ioam6_hdr {\n\t__u8 opt_type;\n\t__u8 opt_len;\n\tchar: 8;\n\t__u8 type;\n};\n\nstruct ioam6_schema;\n\nstruct ioam6_namespace {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_schema *schema;\n\t__be16 id;\n\t__be32 data;\n\t__be64 data_wide;\n};\n\nstruct ioam6_pernet_data {\n\tstruct mutex lock;\n\tstruct rhashtable namespaces;\n\tstruct rhashtable schemas;\n};\n\nstruct ioam6_schema {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_namespace *ns;\n\tu32 id;\n\tint len;\n\t__be32 hdr;\n\tu8 data[0];\n};\n\nstruct ioam6_trace_hdr {\n\t__be16 namespace_id;\n\t__u8 nodelen: 5;\n\t__u8 overflow: 1;\n\tchar: 2;\n\tchar: 1;\n\t__u8 remlen: 7;\n\tunion {\n\t\t__be32 type_be32;\n\t\tstruct {\n\t\t\t__u32 bit0: 1;\n\t\t\t__u32 bit1: 1;\n\t\t\t__u32 bit2: 1;\n\t\t\t__u32 bit3: 1;\n\t\t\t__u32 bit4: 1;\n\t\t\t__u32 bit5: 1;\n\t\t\t__u32 bit6: 1;\n\t\t\t__u32 bit7: 1;\n\t\t\t__u32 bit8: 1;\n\t\t\t__u32 bit9: 1;\n\t\t\t__u32 bit10: 1;\n\t\t\t__u32 bit11: 1;\n\t\t\t__u32 bit12: 1;\n\t\t\t__u32 bit13: 1;\n\t\t\t__u32 bit14: 1;\n\t\t\t__u32 bit15: 1;\n\t\t\t__u32 bit16: 1;\n\t\t\t__u32 bit17: 1;\n\t\t\t__u32 bit18: 1;\n\t\t\t__u32 bit19: 1;\n\t\t\t__u32 bit20: 1;\n\t\t\t__u32 bit21: 1;\n\t\t\t__u32 bit22: 1;\n\t\t\t__u32 bit23: 1;\n\t\t} type;\n\t};\n\t__u8 data[0];\n};\n\nstruct ioc_params {\n\tu32 qos[6];\n\tu64 i_lcoefs[6];\n\tu64 lcoefs[6];\n\tu32 too_fast_vrate_pct;\n\tu32 too_slow_vrate_pct;\n};\n\nstruct ioc_margins {\n\ts64 min;\n\ts64 low;\n\ts64 target;\n};\n\nstruct ioc_pcpu_stat;\n\nstruct ioc {\n\tstruct rq_qos rqos;\n\tbool enabled;\n\tstruct ioc_params params;\n\tstruct ioc_margins margins;\n\tu32 period_us;\n\tu32 timer_slack_ns;\n\tu64 vrate_min;\n\tu64 vrate_max;\n\tspinlock_t lock;\n\tstruct timer_list timer;\n\tstruct list_head active_iocgs;\n\tstruct ioc_pcpu_stat *pcpu_stat;\n\tenum ioc_running running;\n\tatomic64_t vtime_rate;\n\tu64 vtime_base_rate;\n\ts64 vtime_err;\n\tseqcount_spinlock_t period_seqcount;\n\tu64 period_at;\n\tu64 period_at_vtime;\n\tatomic64_t cur_period;\n\tint busy_level;\n\tbool weights_updated;\n\tatomic_t hweight_gen;\n\tu64 dfgv_period_at;\n\tu64 dfgv_period_rem;\n\tu64 dfgv_usage_us_sum;\n\tu64 autop_too_fast_at;\n\tu64 autop_too_slow_at;\n\tint autop_idx;\n\tbool user_qos_params: 1;\n\tbool user_cost_model: 1;\n};\n\nstruct ioc_cgrp {\n\tstruct blkcg_policy_data cpd;\n\tunsigned int dfl_weight;\n};\n\nstruct iocg_stat {\n\tu64 usage_us;\n\tu64 wait_us;\n\tu64 indebt_us;\n\tu64 indelay_us;\n};\n\nstruct iocg_pcpu_stat;\n\nstruct ioc_gq {\n\tstruct blkg_policy_data pd;\n\tstruct ioc *ioc;\n\tu32 cfg_weight;\n\tu32 weight;\n\tu32 active;\n\tu32 inuse;\n\tu32 last_inuse;\n\ts64 saved_margin;\n\tsector_t cursor;\n\tatomic64_t vtime;\n\tatomic64_t done_vtime;\n\tu64 abs_vdebt;\n\tu64 delay;\n\tu64 delay_at;\n\tatomic64_t active_period;\n\tstruct list_head active_list;\n\tu64 child_active_sum;\n\tu64 child_inuse_sum;\n\tu64 child_adjusted_sum;\n\tint hweight_gen;\n\tu32 hweight_active;\n\tu32 hweight_inuse;\n\tu32 hweight_donating;\n\tu32 hweight_after_donation;\n\tstruct list_head walk_list;\n\tstruct list_head surplus_list;\n\tstruct wait_queue_head waitq;\n\tstruct hrtimer waitq_timer;\n\tu64 activated_at;\n\tstruct iocg_pcpu_stat *pcpu_stat;\n\tstruct iocg_stat stat;\n\tstruct iocg_stat last_stat;\n\tu64 last_stat_abs_vusage;\n\tu64 usage_delta_us;\n\tu64 wait_since;\n\tu64 indebt_since;\n\tu64 indelay_since;\n\tint level;\n\tstruct ioc_gq *ancestors[0];\n};\n\nstruct ioc_missed {\n\tlocal_t nr_met;\n\tlocal_t nr_missed;\n\tu32 last_met;\n\tu32 last_missed;\n};\n\nstruct ioc_now {\n\tu64 now_ns;\n\tu64 now;\n\tu64 vnow;\n};\n\nstruct ioc_pcpu_stat {\n\tstruct ioc_missed missed[2];\n\tlocal64_t rq_wait_ns;\n\tu64 last_rq_wait_ns;\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u32 aio_key;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct iocg_pcpu_stat {\n\tlocal64_t abs_vusage;\n};\n\nstruct iocg_wait {\n\tstruct wait_queue_entry wait;\n\tstruct bio *bio;\n\tu64 abs_cost;\n\tbool committed;\n};\n\nstruct iocg_wake_ctx {\n\tstruct ioc_gq *iocg;\n\tu32 hw_inuse;\n\ts64 vbudget;\n};\n\nstruct ioctl_sick_map {\n\tunsigned int sick_mask;\n\tunsigned int ioctl_mask;\n};\n\nstruct percentile_stats {\n\tu64 total;\n\tu64 missed;\n};\n\nstruct latency_stat {\n\tunion {\n\t\tstruct percentile_stats ps;\n\t\tstruct blk_rq_stat rqs;\n\t};\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct iolatency_grp {\n\tstruct blkg_policy_data pd;\n\tstruct latency_stat *stats;\n\tstruct latency_stat cur_stat;\n\tstruct blk_iolatency *blkiolat;\n\tunsigned int max_depth;\n\tstruct rq_wait rq_wait;\n\tatomic64_t window_start;\n\tatomic_t scale_cookie;\n\tu64 min_lat_nsec;\n\tu64 cur_win_nsec;\n\tu64 lat_avg;\n\tu64 nr_samples;\n\tbool ssd;\n\tstruct child_latency_info child_lat;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tstruct bio io_bio;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n};\n\nstruct iommu_domain;\n\nstruct iommu_attach_handle {\n\tstruct iommu_domain *domain;\n};\n\nstruct iommu_ops;\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n\tstruct iommu_group *singleton_group;\n\tu32 max_pasids;\n\tbool ready;\n};\n\nstruct iova_bitmap;\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_dirty_bitmap {\n\tstruct iova_bitmap *bitmap;\n\tstruct iommu_iotlb_gather *gather;\n};\n\nstruct iommu_dirty_ops {\n\tint (*set_dirty_tracking)(struct iommu_domain *, bool);\n\tint (*read_and_clear_dirty)(struct iommu_domain *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct iova {\n\tstruct rb_node node;\n\tlong unsigned int pfn_hi;\n\tlong unsigned int pfn_lo;\n};\n\nstruct iova_rcache;\n\nstruct iova_domain {\n\tspinlock_t iova_rbtree_lock;\n\tstruct rb_root rbroot;\n\tstruct rb_node *cached_node;\n\tstruct rb_node *cached32_node;\n\tlong unsigned int granule;\n\tlong unsigned int start_pfn;\n\tlong unsigned int dma_32bit_pfn;\n\tlong unsigned int max32_alloc_size;\n\tstruct iova anchor;\n\tstruct iova_rcache *rcaches;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct iommu_dma_options {\n\tenum iommu_dma_queue_type qt;\n\tsize_t fq_size;\n\tunsigned int fq_timeout;\n};\n\nstruct iova_fq;\n\nstruct iommu_dma_cookie {\n\tstruct iova_domain iovad;\n\tstruct list_head msi_page_list;\n\tunion {\n\t\tstruct iova_fq *single_fq;\n\t\tstruct iova_fq *percpu_fq;\n\t};\n\tatomic64_t fq_flush_start_cnt;\n\tatomic64_t fq_flush_finish_cnt;\n\tstruct timer_list fq_timer;\n\tatomic_t fq_timer_on;\n\tstruct iommu_domain *fq_domain;\n\tstruct iommu_dma_options options;\n};\n\nstruct iommu_dma_msi_cookie {\n\tdma_addr_t msi_iova;\n\tstruct list_head msi_page_list;\n};\n\nstruct iommu_dma_msi_page {\n\tstruct list_head list;\n\tdma_addr_t iova;\n\tphys_addr_t phys;\n};\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommufd_hw_pagetable;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_ops;\n\nstruct iopf_group;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct iommu_user_data_array;\n\nstruct iommu_domain_ops {\n\tint (*attach_dev)(struct iommu_domain *, struct device *, struct iommu_domain *);\n\tint (*set_dev_pasid)(struct iommu_domain *, struct device *, ioasid_t, struct iommu_domain *);\n\tint (*map_pages)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct iommu_domain *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tint (*iotlb_sync_map)(struct iommu_domain *, long unsigned int, size_t);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tint (*cache_invalidate_user)(struct iommu_domain *, struct iommu_user_data_array *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tbool (*enforce_cache_coherency)(struct iommu_domain *);\n\tint (*set_pgtable_quirks)(struct iommu_domain *, long unsigned int);\n\tvoid (*free)(struct iommu_domain *);\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iopf_queue;\n\nstruct iommu_fault_param {\n\tstruct mutex lock;\n\trefcount_t users;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n\tstruct iopf_queue *queue;\n\tstruct list_head queue_list;\n\tstruct list_head partial;\n\tstruct list_head faults;\n};\n\nstruct iommu_fwspec {\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct xarray pasid_array;\n\tstruct mutex mutex;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *blocking_domain;\n\tstruct iommu_domain *resetting_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n\tunsigned int owner_cnt;\n\tvoid *owner;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct iommu_pages_list {\n\tstruct list_head pages;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n\tstruct iommu_pages_list freelist;\n\tbool queued;\n};\n\nstruct iommu_user_data;\n\nstruct of_phandle_args;\n\nstruct iopf_fault;\n\nstruct iommu_page_response;\n\nstruct iommufd_viommu;\n\nstruct iommu_ops {\n\tbool (*capable)(struct device *, enum iommu_cap);\n\tvoid * (*hw_info)(struct device *, u32 *, enum iommu_hw_info_type *);\n\tstruct iommu_domain * (*domain_alloc_identity)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_paging_flags)(struct device *, u32, const struct iommu_user_data *);\n\tstruct iommu_domain * (*domain_alloc_paging)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_sva)(struct device *, struct mm_struct *);\n\tstruct iommu_domain * (*domain_alloc_nested)(struct device *, struct iommu_domain *, u32, const struct iommu_user_data *);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tint (*of_xlate)(struct device *, const struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct device *);\n\tvoid (*page_response)(struct device *, struct iopf_fault *, struct iommu_page_response *);\n\tint (*def_domain_type)(struct device *);\n\tsize_t (*get_viommu_size)(struct device *, enum iommu_viommu_type);\n\tint (*viommu_init)(struct iommufd_viommu *, struct iommu_domain *, const struct iommu_user_data *);\n\tconst struct iommu_domain_ops *default_domain_ops;\n\tstruct module *owner;\n\tstruct iommu_domain *identity_domain;\n\tstruct iommu_domain *blocked_domain;\n\tstruct iommu_domain *release_domain;\n\tstruct iommu_domain *default_domain;\n\tu8 user_pasid_table: 1;\n};\n\nstruct iommu_page_response {\n\tu32 pasid;\n\tu32 grpid;\n\tu32 code;\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n\tvoid (*free)(struct device *, struct iommu_resv_region *);\n};\n\nstruct iommu_user_data {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t len;\n};\n\nstruct iommu_user_data_array {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t entry_len;\n\tu32 entry_num;\n};\n\nstruct iommufd_object {\n\trefcount_t wait_cnt;\n\trefcount_t users;\n\tenum iommufd_object_type type;\n\tunsigned int id;\n};\n\nstruct iommufd_access;\n\nstruct iommufd_hw_queue {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_access *access;\n\tu64 base_addr;\n\tsize_t length;\n\tenum iommu_hw_queue_type type;\n\tvoid (*destroy)(struct iommufd_hw_queue *);\n};\n\nstruct iommufd_device;\n\nstruct iommufd_vdevice {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_device *idev;\n\tu64 virt_id;\n\tvoid (*destroy)(struct iommufd_vdevice *);\n};\n\nstruct iommufd_ctx;\n\nstruct iommufd_hwpt_paging;\n\nstruct iommufd_viommu_ops;\n\nstruct iommufd_viommu {\n\tstruct iommufd_object obj;\n\tstruct iommufd_ctx *ictx;\n\tstruct iommu_device *iommu_dev;\n\tstruct iommufd_hwpt_paging *hwpt;\n\tconst struct iommufd_viommu_ops *ops;\n\tstruct xarray vdevs;\n\tstruct list_head veventqs;\n\tstruct rw_semaphore veventqs_rwsem;\n\tenum iommu_viommu_type type;\n};\n\nstruct iommufd_viommu_ops {\n\tvoid (*destroy)(struct iommufd_viommu *);\n\tstruct iommu_domain * (*alloc_domain_nested)(struct iommufd_viommu *, u32, const struct iommu_user_data *);\n\tint (*cache_invalidate)(struct iommufd_viommu *, struct iommu_user_data_array *);\n\tconst size_t vdevice_size;\n\tint (*vdevice_init)(struct iommufd_vdevice *);\n\tsize_t (*get_hw_queue_size)(struct iommufd_viommu *, enum iommu_hw_queue_type);\n\tint (*hw_queue_init_phys)(struct iommufd_hw_queue *, u32, phys_addr_t);\n};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct iopf_queue {\n\tstruct workqueue_struct *wq;\n\tstruct list_head devices;\n\tstruct mutex lock;\n};\n\nstruct ioprio_blkcg {\n\tstruct blkcg_policy_data cpd;\n\tenum prio_policy prio_policy;\n};\n\nstruct ioptdesc {\n\tlong unsigned int __page_flags;\n\tstruct list_head iopt_freelist_elm;\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tu8 incoherent;\n\t\tlong unsigned int __index;\n\t};\n\tvoid *_private;\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct iova_bitmap_map {\n\tlong unsigned int iova;\n\tlong unsigned int length;\n\tlong unsigned int pgshift;\n\tlong unsigned int pgoff;\n\tlong unsigned int npages;\n\tstruct page **pages;\n};\n\nstruct iova_bitmap {\n\tstruct iova_bitmap_map mapped;\n\tu8 *bitmap;\n\tlong unsigned int mapped_base_index;\n\tlong unsigned int mapped_total_index;\n\tlong unsigned int iova;\n\tsize_t length;\n};\n\nstruct iova_magazine;\n\nstruct iova_cpu_rcache {\n\tspinlock_t lock;\n\tstruct iova_magazine *loaded;\n\tstruct iova_magazine *prev;\n};\n\nstruct iova_fq_entry {\n\tlong unsigned int iova_pfn;\n\tlong unsigned int pages;\n\tstruct iommu_pages_list freelist;\n\tu64 counter;\n};\n\nstruct iova_fq {\n\tspinlock_t lock;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int mod_mask;\n\tstruct iova_fq_entry entries[0];\n};\n\nstruct iova_magazine {\n\tunion {\n\t\tlong unsigned int size;\n\t\tstruct iova_magazine *next;\n\t};\n\tlong unsigned int pfns[127];\n};\n\nstruct iova_rcache {\n\tspinlock_t lock;\n\tunsigned int depot_size;\n\tstruct iova_magazine *depot;\n\tstruct iova_cpu_rcache *cpu_rcaches;\n\tstruct iova_domain *iovad;\n\tstruct delayed_work work;\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct ip6_frag_state {\n\tu8 *prevhdr;\n\tunsigned int hlen;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\tint hroom;\n\tint troom;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ipv6hdr;\n\nstruct ip6_fraglist_iter {\n\tstruct ipv6hdr *tmp_hdr;\n\tstruct sk_buff *frag;\n\tint offset;\n\tunsigned int hlen;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct ip6_mtuinfo {\n\tstruct sockaddr_in6 ip6m_addr;\n\t__u32 ip6m_mtu;\n};\n\nstruct ip6_ra_chain {\n\tstruct ip6_ra_chain *next;\n\tstruct sock *sk;\n\tint sel;\n\tvoid (*destructor)(struct sock *);\n};\n\nstruct ip6_rt_info {\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\tu_int32_t mark;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip6_tnl {\n\tstruct ip6_tnl *next;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tstruct __ip6_tnl_parm parms;\n\tstruct flowi fl;\n\tstruct dst_cache dst_cache;\n\tstruct gro_cells gro_cells;\n\tint err_count;\n\tlong unsigned int err_time;\n\t__u32 i_seqno;\n\tatomic_t o_seqno;\n\tint hlen;\n\tint tun_hlen;\n\tint encap_hlen;\n\tstruct ip_tunnel_encap encap;\n\tint mlink;\n};\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip6addrlbl_entry {\n\tstruct in6_addr prefix;\n\tint prefixlen;\n\tint ifindex;\n\tint addrtype;\n\tu32 label;\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n};\n\nstruct ip6addrlbl_init_table {\n\tconst struct in6_addr *prefix;\n\tint prefixlen;\n\tu32 label;\n};\n\nstruct ip6fl_iter_state {\n\tstruct seq_net_private p;\n\tstruct pid_namespace *pid_ns;\n\tint bucket;\n};\n\nstruct ip6rd_flowi {\n\tstruct flowi6 fl6;\n\tstruct in6_addr gateway;\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_beet_phdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 padlen;\n\t__u8 reserved;\n};\n\nstruct ip_conntrack_stat {\n\tunsigned int found;\n\tunsigned int invalid;\n\tunsigned int insert;\n\tunsigned int insert_failed;\n\tunsigned int clash_resolve;\n\tunsigned int drop;\n\tunsigned int early_drop;\n\tunsigned int error;\n\tunsigned int expect_new;\n\tunsigned int expect_create;\n\tunsigned int expect_delete;\n\tunsigned int search_restart;\n\tunsigned int chaintoolong;\n};\n\nstruct ip_ct_sctp {\n\tenum sctp_conntrack state;\n\t__be32 vtag[2];\n\tu8 init[2];\n\tu8 last_dir;\n\tu8 flags;\n};\n\nstruct ip_ct_tcp_state {\n\tu_int32_t td_end;\n\tu_int32_t td_maxend;\n\tu_int32_t td_maxwin;\n\tu_int32_t td_maxack;\n\tu_int8_t td_scale;\n\tu_int8_t flags;\n};\n\nstruct ip_ct_tcp {\n\tstruct ip_ct_tcp_state seen[2];\n\tu_int8_t state;\n\tu_int8_t last_dir;\n\tu_int8_t retrans;\n\tu_int8_t last_index;\n\tu_int32_t last_seq;\n\tu_int32_t last_ack;\n\tu_int32_t last_end;\n\tu_int16_t last_win;\n\tu_int8_t last_wscale;\n\tu_int8_t last_flags;\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct iphdr;\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_rt_acct {\n\t__u32 o_bytes;\n\t__u32 o_packets;\n\t__u32 i_bytes;\n\t__u32 i_packets;\n};\n\nstruct ip_rt_info {\n\t__be32 daddr;\n\t__be32 saddr;\n\tu_int8_t tos;\n\tu_int32_t mark;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct iphdr {\n\t__u8 version: 4;\n\t__u8 ihl: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl_entry;\n\nstruct ip_tunnel {\n\tstruct ip_tunnel *next;\n\tstruct hlist_node hash_node;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tlong unsigned int err_time;\n\tint err_count;\n\tu32 i_seqno;\n\tatomic_t o_seqno;\n\tint tun_hlen;\n\tu32 index;\n\tu8 erspan_ver;\n\tu8 dir;\n\tu16 hwid;\n\tstruct dst_cache dst_cache;\n\tstruct ip_tunnel_parm_kern parms;\n\tint mlink;\n\tint encap_hlen;\n\tint hlen;\n\tstruct ip_tunnel_encap encap;\n\tstruct ip_tunnel_prl_entry *prl;\n\tunsigned int prl_count;\n\tunsigned int ip_tnl_net_id;\n\tstruct gro_cells gro_cells;\n\t__u32 fwmark;\n\tbool collect_md;\n\tbool ignore_df;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 0;\n\tu8 options[0];\n};\n\nstruct ip_tunnel_prl_entry {\n\tstruct ip_tunnel_prl_entry *next;\n\t__be32 addr;\n\tu16 flags;\n\tstruct callback_head callback_head;\n};\n\nstruct ipa_cmd_names {\n\tenum qeth_ipa_cmds cmd;\n\tconst char *name;\n};\n\nstruct ipa_rc_msg;\n\nstruct ipa_cmd_rc_map {\n\tenum qeth_ipa_cmds cmd;\n\tconst struct ipa_rc_msg *msg_arr;\n\tconst size_t arr_len;\n};\n\nstruct ipa_rc_msg {\n\tenum qeth_ipa_return_codes rc;\n\tconst char *msg;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int __pad1;\n\tshort unsigned int seq;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tint next_id;\n\tstruct rhashtable key_ht;\n};\n\nstruct msgbuf;\n\nstruct ipc_kludge {\n\tstruct msgbuf *msgp;\n\tlong int msgtyp;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct ipc_security_struct {\n\tu16 sclass;\n\tu32 sid;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n};\n\nstruct ipcm6_cookie {\n\tstruct sockcm_cookie sockc;\n\t__s16 hlimit;\n\t__s16 tclass;\n\t__u16 gso_size;\n\t__s8 dontfrag;\n\tstruct ipv6_txoptions *opt;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipib_info {\n\tlong unsigned int ipib;\n\tu32 checksum;\n} __attribute__((packed));\n\nstruct ipl_info {\n\tenum ipl_type type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ccw_dev_id dev_id;\n\t\t} ccw;\n\t\tstruct {\n\t\t\tstruct ccw_dev_id dev_id;\n\t\t} eckd;\n\t\tstruct {\n\t\t\tstruct ccw_dev_id dev_id;\n\t\t\tu64 wwpn;\n\t\t\tu64 lun;\n\t\t} fcp;\n\t\tstruct {\n\t\t\tu32 fid;\n\t\t\tu32 nsid;\n\t\t} nvme;\n\t\tstruct {\n\t\t\tchar name[9];\n\t\t} nss;\n\t} data;\n};\n\nstruct ipl_pl_hdr {\n\t__u32 len;\n\t__u8 flags;\n\t__u8 reserved1[2];\n\t__u8 version;\n};\n\nstruct ipl_pb_hdr {\n\t__u32 len;\n\t__u8 pbt;\n} __attribute__((packed));\n\nstruct ipl_pb0_common {\n\t__u32 len;\n\t__u8 pbt;\n\t__u8 flags;\n\t__u8 reserved1[2];\n\t__u8 loadparm[8];\n\t__u8 reserved2[84];\n};\n\nstruct ipl_pb0_fcp {\n\t__u32 len;\n\t__u8 pbt;\n\t__u8 reserved1[3];\n\t__u8 loadparm[8];\n\t__u8 reserved2[304];\n\t__u8 opt;\n\t__u8 reserved3[3];\n\t__u8 cssid;\n\t__u8 reserved4[1];\n\t__u16 devno;\n\t__u8 reserved5[4];\n\t__u64 wwpn;\n\t__u64 lun;\n\t__u32 bootprog;\n\t__u8 reserved6[12];\n\t__u64 br_lba;\n\t__u32 scp_data_len;\n\t__u8 reserved7[260];\n\t__u8 scp_data[0];\n} __attribute__((packed));\n\nstruct ipl_pb0_ccw {\n\t__u32 len;\n\t__u8 pbt;\n\t__u8 flags;\n\t__u8 reserved1[2];\n\t__u8 loadparm[8];\n\t__u8 reserved2[84];\n\t__u16 reserved3: 13;\n\t__u8 ssid: 3;\n\t__u16 devno;\n\t__u8 vm_flags;\n\t__u8 reserved4[3];\n\t__u32 vm_parm_len;\n\t__u8 nss_name[8];\n\t__u8 vm_parm[64];\n\t__u8 reserved5[8];\n};\n\nstruct ipl_pb0_eckd {\n\t__u32 len;\n\t__u8 pbt;\n\t__u8 reserved1[3];\n\t__u32 reserved2[78];\n\t__u8 opt;\n\t__u8 reserved4[4];\n\t__u8 reserved5: 5;\n\t__u8 ssid: 3;\n\t__u16 devno;\n\t__u32 reserved6[5];\n\t__u32 bootprog;\n\t__u8 reserved7[12];\n\tstruct {\n\t\t__u16 cyl;\n\t\t__u8 head;\n\t\t__u8 record;\n\t\t__u32 reserved;\n\t} br_chr;\n\t__u32 scp_data_len;\n\t__u8 reserved8[260];\n\t__u8 scp_data[0];\n};\n\nstruct ipl_pb0_nvme {\n\t__u32 len;\n\t__u8 pbt;\n\t__u8 reserved1[3];\n\t__u8 loadparm[8];\n\t__u8 reserved2[304];\n\t__u8 opt;\n\t__u8 reserved3[3];\n\t__u32 fid;\n\t__u8 reserved4[12];\n\t__u32 nsid;\n\t__u8 reserved5[4];\n\t__u32 bootprog;\n\t__u8 reserved6[12];\n\t__u64 br_lba;\n\t__u32 scp_data_len;\n\t__u8 reserved7[260];\n\t__u8 scp_data[0];\n} __attribute__((packed));\n\nstruct ipl_parameter_block {\n\tstruct ipl_pl_hdr hdr;\n\tunion {\n\t\tstruct ipl_pb_hdr pb0_hdr;\n\t\tstruct ipl_pb0_common common;\n\t\tstruct ipl_pb0_fcp fcp;\n\t\tstruct ipl_pb0_ccw ccw;\n\t\tstruct ipl_pb0_eckd eckd;\n\t\tstruct ipl_pb0_nvme nvme;\n\t\tchar raw[4088];\n\t};\n};\n\nstruct ipl_rb_certificate_entry {\n\t__u64 addr;\n\t__u64 len;\n};\n\nstruct ipl_rb_certificates {\n\t__u32 len;\n\t__u8 rbt;\n\t__u8 reserved1[11];\n\tstruct ipl_rb_certificate_entry entries[0];\n};\n\nstruct ipl_rb_component_entry {\n\t__u64 addr;\n\t__u64 len;\n\t__u8 flags;\n\t__u8 reserved1[5];\n\t__u16 certificate_index;\n\t__u8 reserved2[8];\n};\n\nstruct ipl_rb_components {\n\t__u32 len;\n\t__u8 rbt;\n\t__u8 reserved1[11];\n\tstruct ipl_rb_component_entry entries[0];\n};\n\nstruct ipl_report {\n\tstruct ipl_parameter_block *ipib;\n\tstruct list_head components;\n\tstruct list_head certificates;\n\tsize_t size;\n};\n\nstruct ipl_report_certificate {\n\tstruct list_head list;\n\tstruct ipl_rb_certificate_entry entry;\n\tvoid *key;\n};\n\nstruct ipl_report_component {\n\tstruct list_head list;\n\tstruct ipl_rb_component_entry entry;\n};\n\nstruct ipl_rl_hdr {\n\t__u32 len;\n\t__u8 flags;\n\t__u8 reserved1[2];\n\t__u8 version;\n\t__u8 reserved2[8];\n};\n\nstruct mr_table;\n\nstruct ipmr_result {\n\tstruct mr_table *mrt;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_destopt_hao {\n\t__u8 type;\n\t__u8 length;\n\tstruct in6_addr addr;\n} __attribute__((packed));\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mreq {\n\tstruct in6_addr ipv6mr_multiaddr;\n\tint ipv6mr_ifindex;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_params {\n\t__s32 disable_ipv6;\n\t__s32 autoconf;\n};\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool saddr_cache;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib6_walker w;\n\tloff_t skip;\n\tstruct fib6_table *tbl;\n\tint sernum;\n};\n\nstruct ipv6_rpl_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u32 cmpri: 4;\n\t__u32 cmpre: 4;\n\t__u32 pad: 4;\n\t__u32 reserved: 20;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_addr;\n\t\t\tstruct in6_addr addr[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\t__u8 data[0];\n\t\t};\n\t} segments;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct ipv6_saddr_dst {\n\tconst struct in6_addr *addr;\n\tint ifindex;\n\tint scope;\n\tint label;\n\tunsigned int prefs;\n};\n\nstruct ipv6_saddr_score {\n\tint rule;\n\tint addr_type;\n\tstruct inet6_ifaddr *ifa;\n\tlong unsigned int scorebits[1];\n\tint scopedist;\n\tint matchlen;\n};\n\nstruct ipv6_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u8 first_segment;\n\t__u8 flags;\n\t__u16 tag;\n\tstruct in6_addr segments[0];\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tvoid (*xfrm6_local_rxpmtu)(struct sk_buff *, u32);\n\tint (*xfrm6_udp_encap_rcv)(struct sock *, struct sk_buff *);\n\tstruct sk_buff * (*xfrm6_gro_udp_encap_rcv)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*xfrm6_rcv_encap)(struct sk_buff *, int, __be32, int);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 version: 4;\n\t__u8 priority: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct irq_data;\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct irq_class {\n\tint irq;\n\tchar *name;\n\tchar *desc;\n};\n\nstruct msi_desc;\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tunsigned int node;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_ops;\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec;\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_stat {\n\tunsigned int irqs[33];\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqentry_state {\n\tunion {\n\t\tbool exit_rcu;\n\t\tbool lockdep;\n\t};\n};\n\ntypedef struct irqentry_state irqentry_state_t;\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct iso_directory_record {\n\t__u8 length[1];\n\t__u8 ext_attr_length[1];\n\t__u8 extent[8];\n\t__u8 size[8];\n\t__u8 date[7];\n\t__u8 flags[1];\n\t__u8 file_unit_size[1];\n\t__u8 interleave[1];\n\t__u8 volume_sequence_number[4];\n\t__u8 name_len[1];\n\tchar name[0];\n};\n\nstruct iso_inode_info {\n\tlong unsigned int i_iget5_block;\n\tlong unsigned int i_iget5_offset;\n\tunsigned int i_first_extent;\n\tunsigned char i_file_format;\n\tunsigned char i_format_parm[3];\n\tlong unsigned int i_next_section_block;\n\tlong unsigned int i_next_section_offset;\n\toff_t i_section_size;\n\tstruct inode vfs_inode;\n};\n\nstruct iso_primary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_supplementary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 flags[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 escape[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_volume_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2041];\n};\n\nstruct isofs_fid {\n\tu32 block;\n\tu16 offset;\n\tu16 parent_offset;\n\tu32 generation;\n\tu32 parent_block;\n\tu32 parent_generation;\n};\n\nstruct isofs_iget5_callback_data {\n\tlong unsigned int block;\n\tlong unsigned int offset;\n};\n\nstruct isofs_options {\n\tunsigned int rock: 1;\n\tunsigned int joliet: 1;\n\tunsigned int cruft: 1;\n\tunsigned int hide: 1;\n\tunsigned int showassoc: 1;\n\tunsigned int nocompress: 1;\n\tunsigned int overriderockperm: 1;\n\tunsigned int uid_set: 1;\n\tunsigned int gid_set: 1;\n\tunsigned char map;\n\tunsigned char check;\n\tunsigned int blocksize;\n\tumode_t fmode;\n\tumode_t dmode;\n\tkgid_t gid;\n\tkuid_t uid;\n\tchar *iocharset;\n\ts32 session;\n\ts32 sbsector;\n};\n\nstruct nls_table;\n\nstruct isofs_sb_info {\n\tlong unsigned int s_ninodes;\n\tlong unsigned int s_nzones;\n\tlong unsigned int s_firstdatazone;\n\tlong unsigned int s_log_zone_size;\n\tlong unsigned int s_max_size;\n\tint s_rock_offset;\n\ts32 s_sbsector;\n\tunsigned char s_joliet_level;\n\tunsigned char s_mapping;\n\tunsigned char s_check;\n\tunsigned char s_session;\n\tunsigned int s_high_sierra: 1;\n\tunsigned int s_rock: 2;\n\tunsigned int s_cruft: 1;\n\tunsigned int s_nocompress: 1;\n\tunsigned int s_hide: 1;\n\tunsigned int s_showassoc: 1;\n\tunsigned int s_overriderockperm: 1;\n\tunsigned int s_uid_set: 1;\n\tunsigned int s_gid_set: 1;\n\tumode_t s_fmode;\n\tumode_t s_dmode;\n\tkgid_t s_gid;\n\tkuid_t s_uid;\n\tstruct nls_table *s_nls_iocharset;\n};\n\nstruct tcw;\n\nstruct itcw {\n\tstruct tcw *tcw;\n\tstruct tcw *intrg_tcw;\n\tint num_tidaws;\n\tint max_tidaws;\n\tint intrg_num_tidaws;\n\tint intrg_max_tidaws;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct iucv_array {\n\tdma32_t address;\n\tu32 length;\n};\n\nstruct iucv_cmd_control {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iprcode;\n\tu16 ipmsglim;\n\tu16 res1;\n\tu8 ipvmid[8];\n\tu8 ipuser[16];\n\tu8 iptarget[8];\n};\n\nstruct iucv_cmd_db {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iprcode;\n\tu32 ipmsgid;\n\tu32 iptrgcls;\n\tdma32_t ipbfadr1;\n\tu32 ipbfln1f;\n\tu32 ipsrccls;\n\tu32 ipmsgtag;\n\tdma32_t ipbfadr2;\n\tu32 ipbfln2f;\n\tu32 res;\n};\n\nstruct iucv_cmd_dpl {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iprcode;\n\tu32 ipmsgid;\n\tu32 iptrgcls;\n\tu8 iprmmsg[8];\n\tu32 ipsrccls;\n\tu32 ipmsgtag;\n\tdma32_t ipbfadr2;\n\tu32 ipbfln2f;\n\tu32 res;\n};\n\nstruct iucv_cmd_purge {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iprcode;\n\tu32 ipmsgid;\n\tu8 ipaudit[3];\n\tu8 res1[5];\n\tu32 res2;\n\tu32 ipsrccls;\n\tu32 ipmsgtag;\n\tu32 res3[3];\n};\n\nstruct iucv_cmd_set_mask {\n\tu8 ipmask;\n\tu8 res1[2];\n\tu8 iprcode;\n\tu32 res2[9];\n};\n\nstruct iucv_handler {\n\tint (*path_pending)(struct iucv_path *, u8 *, u8 *);\n\tvoid (*path_complete)(struct iucv_path *, u8 *);\n\tvoid (*path_severed)(struct iucv_path *, u8 *);\n\tvoid (*path_quiesced)(struct iucv_path *, u8 *);\n\tvoid (*path_resumed)(struct iucv_path *, u8 *);\n\tvoid (*message_pending)(struct iucv_path *, struct iucv_message *);\n\tvoid (*message_complete)(struct iucv_path *, struct iucv_message *);\n\tstruct list_head list;\n\tstruct list_head paths;\n};\n\nstruct iucv_interface {\n\tint (*message_receive)(struct iucv_path *, struct iucv_message *, u8, void *, size_t, size_t *);\n\tint (*__message_receive)(struct iucv_path *, struct iucv_message *, u8, void *, size_t, size_t *);\n\tint (*message_reply)(struct iucv_path *, struct iucv_message *, u8, void *, size_t);\n\tint (*message_reject)(struct iucv_path *, struct iucv_message *);\n\tint (*message_send)(struct iucv_path *, struct iucv_message *, u8, u32, void *, size_t);\n\tint (*__message_send)(struct iucv_path *, struct iucv_message *, u8, u32, void *, size_t);\n\tint (*message_send2way)(struct iucv_path *, struct iucv_message *, u8, u32, void *, size_t, void *, size_t, size_t *);\n\tint (*message_purge)(struct iucv_path *, struct iucv_message *, u32);\n\tint (*path_accept)(struct iucv_path *, struct iucv_handler *, u8 *, void *);\n\tint (*path_connect)(struct iucv_path *, struct iucv_handler *, u8 *, u8 *, u8 *, void *);\n\tint (*path_quiesce)(struct iucv_path *, u8 *);\n\tint (*path_resume)(struct iucv_path *, u8 *);\n\tint (*path_sever)(struct iucv_path *, u8 *);\n\tint (*iucv_register)(struct iucv_handler *, int);\n\tvoid (*iucv_unregister)(struct iucv_handler *, int);\n\tconst struct bus_type *bus;\n\tstruct device *root;\n};\n\nstruct iucv_irq_data {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iptype;\n\tu32 res2[9];\n};\n\nstruct iucv_irq_list {\n\tstruct list_head list;\n\tstruct iucv_irq_data data;\n};\n\nstruct iucv_message_complete {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iptype;\n\tu32 ipmsgid;\n\tu32 ipaudit;\n\tu8 iprmmsg[8];\n\tu32 ipsrccls;\n\tu32 ipmsgtag;\n\tu32 res;\n\tu32 ipbfln2f;\n\tu8 ippollfg;\n\tu8 res2[3];\n};\n\nstruct iucv_message_pending {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iptype;\n\tu32 ipmsgid;\n\tu32 iptrgcls;\n\tstruct {\n\t\tunion {\n\t\t\tu32 iprmmsg1_u32;\n\t\t\tu8 iprmmsg1[4];\n\t\t} ln1msg1;\n\t\tunion {\n\t\t\tu32 ipbfln1f;\n\t\t\tu8 iprmmsg2[4];\n\t\t} ln1msg2;\n\t} rmmsg;\n\tu32 res1[3];\n\tu32 ipbfln2f;\n\tu8 ippollfg;\n\tu8 res2[3];\n};\n\nunion iucv_param {\n\tstruct iucv_cmd_control ctrl;\n\tstruct iucv_cmd_dpl dpl;\n\tstruct iucv_cmd_db db;\n\tstruct iucv_cmd_purge purge;\n\tstruct iucv_cmd_set_mask set_mask;\n};\n\nstruct iucv_path {\n\tu16 pathid;\n\tu16 msglim;\n\tu8 flags;\n\tvoid *private;\n\tstruct iucv_handler *handler;\n\tstruct list_head list;\n};\n\nstruct iucv_path_complete {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iptype;\n\tu16 ipmsglim;\n\tu16 res1;\n\tu8 res2[8];\n\tu8 ipuser[16];\n\tu32 res3;\n\tu8 ippollfg;\n\tu8 res4[3];\n};\n\nstruct iucv_path_pending {\n\tu16 ippathid;\n\tu8 ipflags1;\n\tu8 iptype;\n\tu16 ipmsglim;\n\tu16 res1;\n\tu8 ipvmid[8];\n\tu8 ipuser[16];\n\tu32 res3;\n\tu8 ippollfg;\n\tu8 res4[3];\n};\n\nstruct iucv_path_quiesced {\n\tu16 ippathid;\n\tu8 res1;\n\tu8 iptype;\n\tu32 res2;\n\tu8 res3[8];\n\tu8 ipuser[16];\n\tu32 res4;\n\tu8 ippollfg;\n\tu8 res5[3];\n};\n\nstruct iucv_path_resumed {\n\tu16 ippathid;\n\tu8 res1;\n\tu8 iptype;\n\tu32 res2;\n\tu8 res3[8];\n\tu8 ipuser[16];\n\tu32 res4;\n\tu8 ippollfg;\n\tu8 res5[3];\n};\n\nstruct iucv_path_severed {\n\tu16 ippathid;\n\tu8 res1;\n\tu8 iptype;\n\tu32 res2;\n\tu8 res3[8];\n\tu8 ipuser[16];\n\tu32 res4;\n\tu8 ippollfg;\n\tu8 res5[3];\n};\n\nstruct sock_msg_q {\n\tstruct iucv_path *path;\n\tstruct iucv_message msg;\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct iucv_sock {\n\tstruct sock sk;\n\tunion {\n\t\tstruct {\n\t\t\tchar src_user_id[8];\n\t\t\tchar src_name[8];\n\t\t\tchar dst_user_id[8];\n\t\t\tchar dst_name[8];\n\t\t};\n\t\tstruct {\n\t\t\tchar src_user_id[8];\n\t\t\tchar src_name[8];\n\t\t\tchar dst_user_id[8];\n\t\t\tchar dst_name[8];\n\t\t} init;\n\t};\n\tstruct list_head accept_q;\n\tspinlock_t accept_q_lock;\n\tstruct sock *parent;\n\tstruct iucv_path *path;\n\tstruct net_device *hs_dev;\n\tstruct sk_buff_head send_skb_q;\n\tstruct sk_buff_head backlog_skb_q;\n\tstruct sock_msg_q message_q;\n\tunsigned int send_tag;\n\tu8 flags;\n\tu16 msglimit;\n\tu16 msglimit_peer;\n\tatomic_t skbs_in_xmit;\n\tatomic_t msg_sent;\n\tatomic_t msg_recv;\n\tatomic_t pendings;\n\tint transport;\n\tvoid (*sk_txnotify)(struct sock *, enum iucv_tx_notify);\n};\n\nstruct iucv_tty_msg;\n\nstruct iucv_tty_buffer {\n\tstruct list_head list;\n\tstruct iucv_message msg;\n\tsize_t offset;\n\tstruct iucv_tty_msg *mbuf;\n};\n\nstruct iucv_tty_msg {\n\tu8 version;\n\tu8 type;\n\tu16 datalen;\n\tu8 data[0];\n};\n\nstruct iw_node_attr {\n\tstruct kobj_attribute kobj_attr;\n\tint nid;\n};\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_s journal_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong long unsigned int blocknr;\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct transaction_stats_s;\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct rand_data;\n\nstruct shash_desc;\n\nstruct jitterentropy {\n\tspinlock_t jent_lock;\n\tstruct rand_data *entropy_collector;\n\tstruct crypto_shash *tfm;\n\tstruct shash_desc *sdesc;\n};\n\nstruct join_entry {\n\tu32 token;\n\tu32 remote_nonce;\n\tu32 local_nonce;\n\tu8 join_id;\n\tu8 local_id;\n\tu8 backup;\n\tu8 valid;\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\twait_queue_head_t j_fc_wait;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tstruct shrinker *j_shrinker;\n\tstruct percpu_counter j_checkpoint_jh_count;\n\ttransaction_t *j_shrink_transaction;\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tlong unsigned int j_fc_first;\n\tlong unsigned int j_fc_off;\n\tlong unsigned int j_fc_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\terrseq_t j_fs_dev_wb_err;\n\tunsigned int j_total_len;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tint j_transaction_overhead_buffers;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tstruct buffer_head **j_fc_wbuf;\n\tint j_wbufsize;\n\tint j_fc_wbufsize;\n\tpid_t j_last_sync_writer;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tint (*j_submit_inode_data_buffers)(struct jbd2_inode *);\n\tint (*j_finish_inode_data_buffers)(struct jbd2_inode *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\t__u32 j_csum_seed;\n\tstruct lock_class_key jbd2_trans_commit_key;\n\tvoid (*j_fc_cleanup_callback)(struct journal_s *, int, tid_t);\n\tint (*j_fc_replay_callback)(struct journal_s *, struct buffer_head *, enum passtype, int, tid_t);\n\tint (*j_bmap)(struct journal_s *, sector_t *);\n};\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__be32 s_num_fc_blks;\n\t__be32 s_head;\n\t__u32 s_padding[40];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nstruct jump_entry {\n\ts32 code;\n\ts32 target;\n\tlong int key;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\ntypedef void __restorefn_t(void);\n\ntypedef __restorefn_t *__sigrestore_t;\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[56];\n\tint exported;\n\tint show_value;\n};\n\nstruct kallsyms_data {\n\tlong unsigned int *addrs;\n\tconst char **syms;\n\tsize_t cnt;\n\tsize_t found;\n};\n\nstruct karatsuba_ctx {\n\tstruct karatsuba_ctx *next;\n\tmpi_ptr_t tspace;\n\tmpi_size_t tspace_size;\n\tmpi_ptr_t tp;\n\tmpi_size_t tp_size;\n};\n\nstruct kbd_data;\n\ntypedef void fn_handler_fn(struct kbd_data *);\n\nstruct kbdiacruc;\n\nstruct kbd_data {\n\tstruct tty_port *port;\n\tshort unsigned int **key_maps;\n\tchar **func_table;\n\tfn_handler_fn **fn_handler;\n\tstruct kbdiacruc *accent_table;\n\tunsigned int accent_table_size;\n\tunsigned int diacr;\n\tshort unsigned int sysrq;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tint: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcmp_epoll_slot {\n\t__u32 efd;\n\t__u32 tfd;\n\t__u32 toff;\n};\n\ntypedef void (*dm_kcopyd_notify_fn)(int, long unsigned int, void *);\n\nstruct kcopyd_job {\n\tstruct dm_kcopyd_client *kc;\n\tstruct list_head list;\n\tunsigned int flags;\n\tint read_err;\n\tlong unsigned int write_err;\n\tenum req_op op;\n\tstruct dm_io_region source;\n\tunsigned int num_dests;\n\tstruct dm_io_region dests[8];\n\tstruct page_list *pages;\n\tdm_kcopyd_notify_fn fn;\n\tvoid *context;\n\tstruct mutex lock;\n\tatomic_t sub_jobs;\n\tsector_t progress;\n\tsector_t write_offset;\n\tstruct kcopyd_job *master_job;\n};\n\nstruct kcore_list {\n\tstruct list_head list;\n\tlong unsigned int addr;\n\tsize_t size;\n\tint type;\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[11];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_fpu_hdr {\n\tint mask;\n\tu32 fpc;\n};\n\nstruct kernel_fpu {\n\tstruct kernel_fpu_hdr hdr;\n\t__vector128 vxrs[0];\n};\n\nstruct kernel_fpu_16 {\n\tstruct kernel_fpu_hdr hdr;\n\t__vector128 vxrs[16];\n};\n\nstruct kernel_fpu_32 {\n\tstruct kernel_fpu_hdr hdr;\n\t__vector128 vxrs[32];\n};\n\nstruct kernel_fpu_8 {\n\tstruct kernel_fpu_hdr hdr;\n\t__vector128 vxrs[8];\n};\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tlong unsigned int value;\n\tconst char *name;\n\tconst char *namespace;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[1024];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct vm_operations_struct;\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct kimage;\n\nstruct kexec_buf {\n\tstruct kimage *image;\n\tvoid *buffer;\n\tlong unsigned int bufsz;\n\tlong unsigned int mem;\n\tlong unsigned int memsz;\n\tlong unsigned int buf_align;\n\tlong unsigned int buf_min;\n\tlong unsigned int buf_max;\n\tstruct page *cma;\n\tbool top_down;\n\tbool random;\n};\n\ntypedef int kexec_probe_t(const char *, long unsigned int);\n\ntypedef void *kexec_load_t(struct kimage *, char *, long unsigned int, char *, long unsigned int, char *, long unsigned int);\n\ntypedef int kexec_cleanup_t(void *);\n\ntypedef int kexec_verify_sig_t(const char *, long unsigned int);\n\nstruct kexec_file_ops {\n\tkexec_probe_t *probe;\n\tkexec_load_t *load;\n\tkexec_cleanup_t *cleanup;\n\tkexec_verify_sig_t *verify_sig;\n};\n\nstruct kexec_link_entry {\n\tconst char *target;\n\tconst char *name;\n};\n\nstruct kexec_load_limit {\n\tstruct mutex mutex;\n\tint limit;\n};\n\nstruct kexec_segment {\n\tunion {\n\t\tvoid *buf;\n\t\tvoid *kbuf;\n\t};\n\tsize_t bufsz;\n\tlong unsigned int mem;\n\tsize_t memsz;\n};\n\nstruct kexec_sha_region {\n\tlong unsigned int start;\n\tlong unsigned int len;\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tchar desc[6];\n\t\t\tu16 desc_len;\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct watch_list;\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct watch_list *watchers;\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct watch_notification {\n\t__u32 type: 24;\n\t__u32 subtype: 8;\n\t__u32 info;\n};\n\nstruct key_notification {\n\tstruct watch_notification watch;\n\t__u32 key_id;\n\t__u32 aux;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_security_struct {\n\tu32 sid;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\ttime64_t now;\n};\n\nstruct keys_header {\n\tunsigned int total_keys;\n\tstruct dm_crypt_key keys[0];\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct kgetbmap {\n\t__s64 bmv_offset;\n\t__s64 bmv_block;\n\t__s64 bmv_length;\n\t__s32 bmv_oflags;\n};\n\nstruct mm_slot;\n\nstruct khugepaged_scan {\n\tstruct list_head mm_head;\n\tstruct mm_slot *mm_slot;\n\tlong unsigned int address;\n};\n\nstruct kimage_arch {\n\tvoid *ipl_buf;\n};\n\nstruct purgatory_info {\n\tconst Elf64_Ehdr *ehdr;\n\tElf64_Shdr *sechdrs;\n\tvoid *purgatory_buf;\n};\n\nstruct kimage {\n\tkimage_entry_t head;\n\tkimage_entry_t *entry;\n\tkimage_entry_t *last_entry;\n\tlong unsigned int start;\n\tstruct page *control_code_page;\n\tstruct page *swap_page;\n\tvoid *vmcoreinfo_data_copy;\n\tlong unsigned int nr_segments;\n\tstruct kexec_segment segment[16];\n\tstruct page *segment_cma[16];\n\tstruct list_head control_pages;\n\tstruct list_head dest_pages;\n\tstruct list_head unusable_pages;\n\tlong unsigned int control_page;\n\tunsigned int type: 1;\n\tunsigned int preserve_context: 1;\n\tunsigned int file_mode: 1;\n\tunsigned int no_cma: 1;\n\tstruct kimage_arch arch;\n\tvoid *kernel_buf;\n\tlong unsigned int kernel_buf_len;\n\tvoid *initrd_buf;\n\tlong unsigned int initrd_buf_len;\n\tchar *cmdline_buf;\n\tlong unsigned int cmdline_buf_len;\n\tconst struct kexec_file_ops *fops;\n\tvoid *image_loader_data;\n\tstruct purgatory_info purgatory_info;\n\tbool force_dtb;\n\tstruct {\n\t\tstruct kexec_segment *scratch;\n\t\tphys_addr_t fdt;\n\t} kho;\n\tvoid *elf_headers;\n\tlong unsigned int elf_headers_sz;\n\tlong unsigned int elf_load_addr;\n\tlong unsigned int dm_crypt_keys_addr;\n\tlong unsigned int dm_crypt_keys_sz;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct klp_object;\n\ntypedef int (*klp_pre_patch_t)(struct klp_object *);\n\ntypedef void (*klp_post_patch_t)(struct klp_object *);\n\ntypedef void (*klp_pre_unpatch_t)(struct klp_object *);\n\ntypedef void (*klp_post_unpatch_t)(struct klp_object *);\n\nstruct klp_callbacks {\n\tklp_pre_patch_t pre_patch;\n\tklp_post_patch_t post_patch;\n\tklp_pre_unpatch_t pre_unpatch;\n\tklp_post_unpatch_t post_unpatch;\n\tbool post_unpatch_enabled;\n};\n\nstruct klp_find_arg {\n\tconst char *name;\n\tlong unsigned int addr;\n\tlong unsigned int count;\n\tlong unsigned int pos;\n};\n\nstruct klp_func {\n\tconst char *old_name;\n\tvoid *new_func;\n\tlong unsigned int old_sympos;\n\tvoid *old_func;\n\tstruct kobject kobj;\n\tstruct list_head node;\n\tstruct list_head stack_node;\n\tlong unsigned int old_size;\n\tlong unsigned int new_size;\n\tbool nop;\n\tbool patched;\n\tbool transition;\n};\n\nstruct klp_modinfo {\n\tElf64_Ehdr hdr;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tunsigned int symndx;\n};\n\nstruct klp_object {\n\tconst char *name;\n\tstruct klp_func *funcs;\n\tstruct klp_callbacks callbacks;\n\tstruct kobject kobj;\n\tstruct list_head func_list;\n\tstruct list_head node;\n\tstruct module *mod;\n\tbool dynamic;\n\tbool patched;\n};\n\nstruct klp_ops {\n\tstruct list_head node;\n\tstruct list_head func_stack;\n\tstruct ftrace_ops fops;\n};\n\nstruct klp_state;\n\nstruct klp_patch {\n\tstruct module *mod;\n\tstruct klp_object *objs;\n\tstruct klp_state *states;\n\tbool replace;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tstruct list_head obj_list;\n\tbool enabled;\n\tbool forced;\n\tstruct work_struct free_work;\n\tstruct completion finish;\n};\n\nstruct klp_shadow {\n\tstruct hlist_node node;\n\tstruct callback_head callback_head;\n\tvoid *obj;\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct klp_state {\n\tlong unsigned int id;\n\tunsigned int version;\n\tvoid *data;\n};\n\nstruct km_event {\n\tunion {\n\t\tu32 hard;\n\t\tu32 proto;\n\t\tu32 byid;\n\t\tu32 aevent;\n\t\tu32 type;\n\t} data;\n\tu32 seq;\n\tu32 portid;\n\tu32 event;\n\tstruct net *net;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[4];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {};\n\ntypedef struct kmem_cache *kmem_buckets[14];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tunsigned int remote_node_defrag_ratio;\n\tstruct kmem_cache_node *node[2];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kpp_request;\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tstruct crypto_alg base;\n};\n\nstruct kpp_instance {\n\tvoid (*free)(struct kpp_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[48];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct kpp_alg alg;\n\t};\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct kpp_testvec {\n\tconst unsigned char *secret;\n\tconst unsigned char *b_secret;\n\tconst unsigned char *b_public;\n\tconst unsigned char *expected_a_public;\n\tconst unsigned char *expected_ss;\n\tshort unsigned int secret_size;\n\tshort unsigned int b_secret_size;\n\tshort unsigned int b_public_size;\n\tshort unsigned int expected_a_public_size;\n\tshort unsigned int expected_ss_size;\n\tbool genkey;\n};\n\nstruct kprobe;\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct kprobe_blacklist_entry {\n\tstruct list_head list;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n};\n\nstruct prev_kprobe {\n\tstruct kprobe *kp;\n\tlong unsigned int status;\n};\n\nstruct kprobe_ctlblk {\n\tlong unsigned int kprobe_status;\n\tlong unsigned int kprobe_saved_imask;\n\tstruct ctlreg kprobe_saved_ctl[3];\n\tstruct prev_kprobe prev_kprobe;\n};\n\nstruct kprobe_insn_cache {\n\tstruct mutex mutex;\n\tvoid * (*alloc)(void);\n\tvoid (*free)(void *);\n\tconst char *sym;\n\tstruct list_head pages;\n\tsize_t insn_size;\n\tint nr_garbage;\n};\n\nstruct kprobe_insn_page {\n\tstruct list_head list;\n\tkprobe_opcode_t *insns;\n\tstruct kprobe_insn_cache *cache;\n\tint nused;\n\tint ngarbage;\n\tchar slot_used[0];\n};\n\nstruct kprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n};\n\nstruct kretprobe_instance;\n\ntypedef int (*kretprobe_handler_t)(struct kretprobe_instance *, struct pt_regs *);\n\nstruct rethook;\n\nstruct kretprobe {\n\tstruct kprobe kp;\n\tkretprobe_handler_t handler;\n\tkretprobe_handler_t entry_handler;\n\tint maxactive;\n\tint nmissed;\n\tsize_t data_size;\n\tstruct rethook *rh;\n};\n\nstruct kretprobe_blackpoint {\n\tconst char *name;\n\tvoid *addr;\n};\n\nstruct rethook_node {\n\tstruct callback_head rcu;\n\tstruct llist_node llist;\n\tstruct rethook *rethook;\n\tlong unsigned int ret_addr;\n\tlong unsigned int frame;\n};\n\nstruct kretprobe_instance {\n\tstruct rethook_node node;\n\tchar data[0];\n};\n\nstruct kretprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int func;\n\tlong unsigned int ret_ip;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct mm_slot {\n\tstruct hlist_node hash;\n\tstruct list_head mm_node;\n\tstruct mm_struct *mm;\n};\n\nstruct ksm_rmap_item;\n\nstruct ksm_mm_slot {\n\tstruct mm_slot slot;\n\tstruct ksm_rmap_item *rmap_list;\n};\n\nstruct ksm_next_page_arg {\n\tstruct folio *folio;\n\tstruct page *page;\n\tlong unsigned int addr;\n};\n\nstruct ksm_stable_node;\n\nstruct ksm_rmap_item {\n\tstruct ksm_rmap_item *rmap_list;\n\tunion {\n\t\tstruct anon_vma *anon_vma;\n\t\tint nid;\n\t};\n\tstruct mm_struct *mm;\n\tlong unsigned int address;\n\tunsigned int oldchecksum;\n\trmap_age_t age;\n\trmap_age_t remaining_skips;\n\tunion {\n\t\tstruct rb_node node;\n\t\tstruct {\n\t\t\tstruct ksm_stable_node *head;\n\t\t\tstruct hlist_node hlist;\n\t\t};\n\t};\n};\n\nstruct ksm_scan {\n\tstruct ksm_mm_slot *mm_slot;\n\tlong unsigned int address;\n\tstruct ksm_rmap_item **rmap_list;\n\tlong unsigned int seqnr;\n};\n\nstruct ksm_stable_node {\n\tunion {\n\t\tstruct rb_node node;\n\t\tstruct {\n\t\t\tstruct list_head *head;\n\t\t\tstruct {\n\t\t\t\tstruct hlist_node hlist_dup;\n\t\t\t\tstruct list_head list;\n\t\t\t};\n\t\t};\n\t};\n\tstruct hlist_head hlist;\n\tunion {\n\t\tlong unsigned int kpfn;\n\t\tlong unsigned int chain_prune_time;\n\t};\n\tint rmap_hlist_len;\n\tint nid;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kunit;\n\nstruct kunit_params {\n\tconst void *params;\n\tvoid (*get_description)(struct kunit *, const void *, char *);\n\tsize_t num_params;\n\tsize_t elem_size;\n};\n\nstruct string_stream;\n\ntypedef void (*kunit_try_catch_func_t)(void *);\n\nstruct kunit_try_catch {\n\tstruct kunit *test;\n\tint try_result;\n\tkunit_try_catch_func_t try;\n\tkunit_try_catch_func_t catch;\n\tlong unsigned int timeout;\n\tvoid *context;\n};\n\nstruct kunit_loc {\n\tint line;\n\tconst char *file;\n};\n\nstruct kunit {\n\tvoid *priv;\n\tstruct kunit *parent;\n\tstruct kunit_params params_array;\n\tconst char *name;\n\tstruct string_stream *log;\n\tstruct kunit_try_catch try_catch;\n\tconst void *param_value;\n\tint param_index;\n\tspinlock_t lock;\n\tenum kunit_status status;\n\tstruct list_head resources;\n\tchar status_comment[256];\n\tstruct kunit_loc last_seen;\n};\n\nstruct kunit_attributes {\n\tenum kunit_speed speed;\n};\n\nstruct kunit_case {\n\tvoid (*run_case)(struct kunit *);\n\tconst char *name;\n\tconst void * (*generate_params)(struct kunit *, const void *, char *);\n\tstruct kunit_attributes attr;\n\tint (*param_init)(struct kunit *);\n\tvoid (*param_exit)(struct kunit *);\n\tenum kunit_status status;\n\tchar *module_name;\n\tstruct string_stream *log;\n};\n\nstruct kunit_hooks_table {\n\tvoid (*fail_current_test)(const char *, int, const char *, ...);\n\tvoid * (*get_static_stub_address)(struct kunit *, void *);\n};\n\nstruct kunit_resource;\n\ntypedef void (*kunit_resource_free_t)(struct kunit_resource *);\n\nstruct kunit_resource {\n\tvoid *data;\n\tconst char *name;\n\tkunit_resource_free_t free;\n\tstruct kref refcount;\n\tstruct list_head node;\n\tbool should_kfree;\n};\n\nstruct kunit_suite {\n\tconst char name[256];\n\tint (*suite_init)(struct kunit_suite *);\n\tvoid (*suite_exit)(struct kunit_suite *);\n\tint (*init)(struct kunit *);\n\tvoid (*exit)(struct kunit *);\n\tstruct kunit_case *test_cases;\n\tstruct kunit_attributes attr;\n\tchar status_comment[256];\n\tstruct dentry *debugfs;\n\tstruct string_stream *log;\n\tint suite_init_err;\n\tbool is_init;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kvm_memslots {\n\tu64 generation;\n\tatomic_long_t last_used_slot;\n\tstruct rb_root_cached hva_tree;\n\tstruct rb_root gfn_tree;\n\tstruct hlist_head id_hash[128];\n\tint node_idx;\n};\n\nstruct kvm_vm_stat_generic {\n\tu64 remote_tlb_flush;\n\tu64 remote_tlb_flush_requests;\n};\n\nstruct kvm_vm_stat {\n\tstruct kvm_vm_stat_generic generic;\n\tu64 inject_io;\n\tu64 inject_float_mchk;\n\tu64 inject_pfault_done;\n\tu64 inject_service_signal;\n\tu64 inject_virtio;\n\tu64 aen_forward;\n\tu64 gmap_shadow_create;\n\tu64 gmap_shadow_reuse;\n\tu64 gmap_shadow_r1_entry;\n\tu64 gmap_shadow_r2_entry;\n\tu64 gmap_shadow_r3_entry;\n\tu64 gmap_shadow_sg_entry;\n\tu64 gmap_shadow_pg_entry;\n};\n\nstruct kvm_s390_mchk_info {\n\t__u64 cr14;\n\t__u64 mcic;\n\t__u64 failing_storage_address;\n\t__u32 ext_damage_code;\n\t__u32 pad;\n\t__u8 fixed_logout[16];\n};\n\nstruct kvm_s390_ext_info {\n\t__u32 ext_params;\n\t__u32 pad;\n\t__u64 ext_params2;\n};\n\nstruct kvm_s390_float_interrupt {\n\tlong unsigned int pending_irqs;\n\tlong unsigned int masked_irqs;\n\tspinlock_t lock;\n\tstruct list_head lists[10];\n\tint counters[4];\n\tstruct kvm_s390_mchk_info mchk;\n\tstruct kvm_s390_ext_info srv_signal;\n\tint last_sleep_cpu;\n\tstruct mutex ais_lock;\n\tu8 simm;\n\tu8 nimm;\n};\n\nstruct gmap;\n\nstruct kvm_s390_vm_cpu_subfunc {\n\t__u8 plo[32];\n\t__u8 ptff[16];\n\t__u8 kmac[16];\n\t__u8 kmc[16];\n\t__u8 km[16];\n\t__u8 kimd[16];\n\t__u8 klmd[16];\n\t__u8 pckmo[16];\n\t__u8 kmctr[16];\n\t__u8 kmf[16];\n\t__u8 kmo[16];\n\t__u8 pcc[16];\n\t__u8 ppno[16];\n\t__u8 kma[16];\n\t__u8 kdsa[16];\n\t__u8 sortl[32];\n\t__u8 dfltcc[32];\n\t__u8 pfcr[16];\n\t__u8 reserved[1712];\n};\n\nstruct kvm_s390_vm_cpu_uv_feat {\n\tunion {\n\t\tstruct {\n\t\t\tchar: 4;\n\t\t\t__u64 ap: 1;\n\t\t\t__u64 ap_intr: 1;\n\t\t};\n\t\t__u64 feat;\n\t};\n};\n\nstruct kvm_s390_cpu_model {\n\t__u64 fac_mask[256];\n\tstruct kvm_s390_vm_cpu_subfunc subfuncs;\n\t__u64 *fac_list;\n\tu64 cpuid;\n\tshort unsigned int ibc;\n\tstruct kvm_s390_vm_cpu_uv_feat uv_feat_guest;\n};\n\nstruct kvm_vcpu;\n\ntypedef int (*crypto_hook)(struct kvm_vcpu *);\n\nstruct kvm_s390_crypto_cb;\n\nstruct kvm_s390_crypto {\n\tstruct kvm_s390_crypto_cb *crycb;\n\tstruct rw_semaphore pqap_hook_rwsem;\n\tcrypto_hook *pqap_hook;\n\t__u32 crycbd;\n\t__u8 aes_kw;\n\t__u8 dea_kw;\n\t__u8 apie;\n};\n\nstruct vsie_page;\n\nstruct kvm_s390_vsie {\n\tstruct mutex mutex;\n\tstruct xarray addr_to_page;\n\tint page_count;\n\tint next;\n\tstruct vsie_page *pages[255];\n};\n\nstruct kvm_s390_gisa_iam {\n\tu8 mask;\n\tspinlock_t ref_lock;\n\tu32 ref_count[8];\n};\n\nstruct kvm_s390_gisa;\n\nstruct kvm_s390_gisa_interrupt {\n\tstruct kvm_s390_gisa *origin;\n\tstruct kvm_s390_gisa_iam alert;\n\tstruct hrtimer timer;\n\tu64 expires;\n\tlong unsigned int kicked_mask[4];\n};\n\nstruct mmu_notifier_ops;\n\nstruct mmu_notifier {\n\tstruct hlist_node hlist;\n\tconst struct mmu_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct callback_head rcu;\n\tunsigned int users;\n};\n\nstruct kvm_s390_pv {\n\tu64 handle;\n\tu64 guest_len;\n\tlong unsigned int stor_base;\n\tvoid *stor_var;\n\tbool dumping;\n\tvoid *set_aside;\n\tstruct list_head need_cleanup;\n\tstruct mmu_notifier mmu_notifier;\n\tstruct mutex import_lock;\n};\n\nstruct kvm_s390_mmu_cache;\n\nstruct kvm_device;\n\nstruct s390_io_adapter;\n\nstruct sie_page2;\n\nstruct kvm_arch {\n\tstruct esca_block *sca;\n\tdebug_info_t *dbf;\n\tstruct kvm_s390_float_interrupt float_int;\n\tstruct kvm_device *flic;\n\tstruct gmap *gmap;\n\tlong unsigned int mem_limit;\n\tint css_support;\n\tint use_irqchip;\n\tint use_cmma;\n\tint use_pfmfi;\n\tint use_skf;\n\tint use_zpci_interp;\n\tint user_cpu_state_ctrl;\n\tint user_sigp;\n\tint user_stsi;\n\tint user_instr0;\n\tint user_operexec;\n\tstruct s390_io_adapter *adapters[64];\n\twait_queue_head_t ipte_wq;\n\tint ipte_lock_count;\n\tstruct mutex ipte_mutex;\n\tspinlock_t start_stop_lock;\n\tstruct sie_page2 *sie_page2;\n\tstruct kvm_s390_cpu_model model;\n\tstruct kvm_s390_crypto crypto;\n\tstruct kvm_s390_vsie vsie;\n\tu8 epdx;\n\tu64 epoch;\n\tint migration_mode;\n\tatomic64_t cmma_dirty_pages;\n\tlong unsigned int cpu_feat[16];\n\tlong unsigned int idle_mask[4];\n\tstruct kvm_s390_gisa_interrupt gisa_int;\n\tstruct kvm_s390_pv pv;\n\tstruct list_head kzdev_list;\n\tspinlock_t kzdev_list_lock;\n\tstruct kvm_s390_mmu_cache *mc;\n};\n\nstruct kvm_io_bus;\n\nstruct kvm_irq_routing_table;\n\nstruct kvm_stat_data;\n\nstruct kvm {\n\trwlock_t mmu_lock;\n\tstruct mutex slots_lock;\n\tstruct mutex slots_arch_lock;\n\tstruct mm_struct *mm;\n\tlong unsigned int nr_memslot_pages;\n\tstruct kvm_memslots __memslots[2];\n\tstruct kvm_memslots *memslots[1];\n\tstruct xarray vcpu_array;\n\tatomic_t nr_memslots_dirty_logging;\n\tspinlock_t mn_invalidate_lock;\n\tlong unsigned int mn_active_invalidate_count;\n\tstruct rcuwait mn_memslots_update_rcuwait;\n\tspinlock_t gpc_lock;\n\tstruct list_head gpc_list;\n\tatomic_t online_vcpus;\n\tint max_vcpus;\n\tint created_vcpus;\n\tint last_boosted_vcpu;\n\tstruct list_head vm_list;\n\tstruct mutex lock;\n\tstruct kvm_io_bus *buses[5];\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head items;\n\t\tstruct list_head resampler_list;\n\t\tstruct mutex resampler_lock;\n\t} irqfds;\n\tstruct list_head ioeventfds;\n\tstruct kvm_vm_stat stat;\n\tstruct kvm_arch arch;\n\trefcount_t users_count;\n\tstruct mutex irq_lock;\n\tstruct kvm_irq_routing_table *irq_routing;\n\tstruct hlist_head irq_ack_notifier_list;\n\tstruct mmu_notifier mmu_notifier;\n\tlong unsigned int mmu_invalidate_seq;\n\tlong int mmu_invalidate_in_progress;\n\tgfn_t mmu_invalidate_range_start;\n\tgfn_t mmu_invalidate_range_end;\n\tstruct list_head devices;\n\tu64 manual_dirty_log_protect;\n\tstruct dentry *debugfs_dentry;\n\tstruct kvm_stat_data **debugfs_stat_data;\n\tstruct srcu_struct srcu;\n\tstruct srcu_struct irq_srcu;\n\tpid_t userspace_pid;\n\tbool override_halt_poll_ns;\n\tunsigned int max_halt_poll_ns;\n\tu32 dirty_ring_size;\n\tbool dirty_ring_with_bitmap;\n\tbool vm_bugged;\n\tbool vm_dead;\n\tchar stats_id[48];\n};\n\nstruct kvm_arch_memory_slot {};\n\nstruct kvm_debug_exit_arch {\n\t__u64 addr;\n\t__u8 type;\n\t__u8 pad[7];\n};\n\nstruct kvm_device_ops;\n\nstruct kvm_device {\n\tconst struct kvm_device_ops *ops;\n\tstruct kvm *kvm;\n\tvoid *private;\n\tstruct list_head vm_node;\n};\n\nstruct kvm_device_attr {\n\t__u32 flags;\n\t__u32 group;\n\t__u64 attr;\n\t__u64 addr;\n};\n\nstruct kvm_device_ops {\n\tconst char *name;\n\tint (*create)(struct kvm_device *, u32);\n\tvoid (*init)(struct kvm_device *);\n\tvoid (*destroy)(struct kvm_device *);\n\tvoid (*release)(struct kvm_device *);\n\tint (*set_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*get_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*has_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tlong int (*ioctl)(struct kvm_device *, unsigned int, long unsigned int);\n\tint (*mmap)(struct kvm_device *, struct vm_area_struct *);\n};\n\nstruct kvm_dirty_gfn {\n\t__u32 flags;\n\t__u32 slot;\n\t__u64 offset;\n};\n\nstruct kvm_dirty_ring {\n\tu32 dirty_index;\n\tu32 reset_index;\n\tu32 size;\n\tu32 soft_limit;\n\tstruct kvm_dirty_gfn *dirty_gfns;\n\tint index;\n};\n\nstruct kvm_exit_snp_req_certs {\n\t__u64 gpa;\n\t__u64 npages;\n\t__u64 ret;\n};\n\nstruct kvm_hw_bp_info_arch;\n\nstruct kvm_hw_wp_info_arch;\n\nstruct kvm_guestdbg_info_arch {\n\tlong unsigned int cr0;\n\tlong unsigned int cr9;\n\tlong unsigned int cr10;\n\tlong unsigned int cr11;\n\tstruct kvm_hw_bp_info_arch *hw_bp_info;\n\tstruct kvm_hw_wp_info_arch *hw_wp_info;\n\tint nr_hw_bp;\n\tint nr_hw_wp;\n\tlong unsigned int last_bp;\n};\n\nstruct kvm_hw_bp_info_arch {\n\tlong unsigned int addr;\n\tint len;\n};\n\nstruct kvm_hw_wp_info_arch {\n\tlong unsigned int addr;\n\tlong unsigned int phys_addr;\n\tint len;\n\tchar *old_data;\n};\n\nstruct kvm_hyperv_exit {\n\t__u32 type;\n\t__u32 pad1;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 evt_page;\n\t\t\t__u64 msg_page;\n\t\t} synic;\n\t\tstruct {\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[2];\n\t\t} hcall;\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 status;\n\t\t\t__u64 send_page;\n\t\t\t__u64 recv_page;\n\t\t\t__u64 pending_page;\n\t\t} syndbg;\n\t} u;\n};\n\nstruct kvm_io_device;\n\nstruct kvm_io_range {\n\tgpa_t addr;\n\tint len;\n\tstruct kvm_io_device *dev;\n};\n\nstruct kvm_io_bus {\n\tint dev_count;\n\tint ioeventfd_count;\n\tstruct callback_head rcu;\n\tstruct kvm_io_range range[0];\n};\n\nstruct kvm_irq_routing_table {\n\tint chip[1];\n\tu32 nr_rt_entries;\n\tstruct hlist_head map[0];\n};\n\nstruct kvm_memory_slot {\n\tstruct hlist_node id_node[2];\n\tstruct interval_tree_node hva_node[2];\n\tstruct rb_node gfn_node[2];\n\tgfn_t base_gfn;\n\tlong unsigned int npages;\n\tlong unsigned int *dirty_bitmap;\n\tstruct kvm_arch_memory_slot arch;\n\tlong unsigned int userspace_addr;\n\tu32 flags;\n\tshort int id;\n\tu16 as_id;\n};\n\nstruct kvm_mmio_fragment {\n\tgpa_t gpa;\n\tvoid *data;\n\tunsigned int len;\n};\n\nstruct kvm_xen_exit {\n\t__u32 type;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 longmode;\n\t\t\t__u32 cpl;\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[6];\n\t\t} hcall;\n\t} u;\n};\n\nstruct kvm_sync_regs {\n\t__u64 prefix;\n\t__u64 gprs[16];\n\t__u32 acrs[16];\n\t__u64 crs[16];\n\t__u64 todpr;\n\t__u64 cputm;\n\t__u64 ckc;\n\t__u64 pp;\n\t__u64 gbea;\n\t__u64 pft;\n\t__u64 pfs;\n\t__u64 pfc;\n\tunion {\n\t\t__u64 vrs[64];\n\t\t__u64 fprs[16];\n\t};\n\t__u8 reserved[512];\n\t__u32 fpc;\n\t__u8 bpbc: 1;\n\t__u8 reserved2: 7;\n\t__u8 padding1[51];\n\t__u8 riccb[64];\n\t__u64 diag318;\n\t__u8 padding2[184];\n\tunion {\n\t\t__u8 sdnx[256];\n\t\tstruct {\n\t\t\t__u64 reserved1[2];\n\t\t\t__u64 gscb[4];\n\t\t\t__u64 etoken;\n\t\t\t__u64 etoken_extension;\n\t\t};\n\t};\n};\n\nstruct kvm_run {\n\t__u8 request_interrupt_window;\n\t__u8 immediate_exit__unsafe;\n\t__u8 padding1[6];\n\t__u32 exit_reason;\n\t__u8 ready_for_interrupt_injection;\n\t__u8 if_flag;\n\t__u16 flags;\n\t__u64 cr8;\n\t__u64 apic_base;\n\t__u64 psw_mask;\n\t__u64 psw_addr;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 hardware_exit_reason;\n\t\t} hw;\n\t\tstruct {\n\t\t\t__u64 hardware_entry_failure_reason;\n\t\t\t__u32 cpu;\n\t\t} fail_entry;\n\t\tstruct {\n\t\t\t__u32 exception;\n\t\t\t__u32 error_code;\n\t\t} ex;\n\t\tstruct {\n\t\t\t__u8 direction;\n\t\t\t__u8 size;\n\t\t\t__u16 port;\n\t\t\t__u32 count;\n\t\t\t__u64 data_offset;\n\t\t} io;\n\t\tstruct {\n\t\t\tstruct kvm_debug_exit_arch arch;\n\t\t} debug;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} mmio;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} iocsr_io;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u64 ret;\n\t\t\tunion {\n\t\t\t\t__u64 flags;\n\t\t\t};\n\t\t} hypercall;\n\t\tstruct {\n\t\t\t__u64 rip;\n\t\t\t__u32 is_write;\n\t\t\t__u32 pad;\n\t\t} tpr_access;\n\t\tstruct {\n\t\t\t__u8 icptcode;\n\t\t\t__u16 ipa;\n\t\t\t__u32 ipb;\n\t\t} s390_sieic;\n\t\t__u64 s390_reset_flags;\n\t\tstruct {\n\t\t\t__u64 trans_exc_code;\n\t\t\t__u32 pgm_code;\n\t\t} s390_ucontrol;\n\t\tstruct {\n\t\t\t__u32 dcrn;\n\t\t\t__u32 data;\n\t\t\t__u8 is_write;\n\t\t} dcr;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 data[16];\n\t\t} internal;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 flags;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 insn_size;\n\t\t\t\t\t__u8 insn_bytes[15];\n\t\t\t\t};\n\t\t\t};\n\t\t} emulation_failure;\n\t\tstruct {\n\t\t\t__u64 gprs[32];\n\t\t} osi;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 ret;\n\t\t\t__u64 args[9];\n\t\t} papr_hcall;\n\t\tstruct {\n\t\t\t__u16 subchannel_id;\n\t\t\t__u16 subchannel_nr;\n\t\t\t__u32 io_int_parm;\n\t\t\t__u32 io_int_word;\n\t\t\t__u32 ipb;\n\t\t\t__u8 dequeued;\n\t\t} s390_tsch;\n\t\tstruct {\n\t\t\t__u32 epr;\n\t\t} epr;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\t__u32 ndata;\n\t\t\tunion {\n\t\t\t\t__u64 data[16];\n\t\t\t};\n\t\t} system_event;\n\t\tstruct {\n\t\t\t__u64 addr;\n\t\t\t__u8 ar;\n\t\t\t__u8 reserved;\n\t\t\t__u8 fc;\n\t\t\t__u8 sel1;\n\t\t\t__u16 sel2;\n\t\t} s390_stsi;\n\t\tstruct {\n\t\t\t__u8 vector;\n\t\t} eoi;\n\t\tstruct kvm_hyperv_exit hyperv;\n\t\tstruct {\n\t\t\t__u64 esr_iss;\n\t\t\t__u64 fault_ipa;\n\t\t} arm_nisv;\n\t\tstruct {\n\t\t\t__u8 error;\n\t\t\t__u8 pad[7];\n\t\t\t__u32 reason;\n\t\t\t__u32 index;\n\t\t\t__u64 data;\n\t\t} msr;\n\t\tstruct kvm_xen_exit xen;\n\t\tstruct {\n\t\t\tlong unsigned int extension_id;\n\t\t\tlong unsigned int function_id;\n\t\t\tlong unsigned int args[6];\n\t\t\tlong unsigned int ret[2];\n\t\t} riscv_sbi;\n\t\tstruct {\n\t\t\tlong unsigned int csr_num;\n\t\t\tlong unsigned int new_value;\n\t\t\tlong unsigned int write_mask;\n\t\t\tlong unsigned int ret_value;\n\t\t} riscv_csr;\n\t\tstruct {\n\t\t\t__u32 flags;\n\t\t} notify;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 gpa;\n\t\t\t__u64 size;\n\t\t} memory_fault;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 nr;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 data[5];\n\t\t\t\t} unknown;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 gpa;\n\t\t\t\t\t__u64 size;\n\t\t\t\t} get_quote;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 leaf;\n\t\t\t\t\t__u64 r11;\n\t\t\t\t\t__u64 r12;\n\t\t\t\t\t__u64 r13;\n\t\t\t\t\t__u64 r14;\n\t\t\t\t} get_tdvmcall_info;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 vector;\n\t\t\t\t} setup_event_notify;\n\t\t\t};\n\t\t} tdx;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 esr;\n\t\t\t__u64 gva;\n\t\t\t__u64 gpa;\n\t\t} arm_sea;\n\t\tstruct kvm_exit_snp_req_certs snp_req_certs;\n\t\tchar padding[256];\n\t};\n\t__u64 kvm_valid_regs;\n\t__u64 kvm_dirty_regs;\n\tunion {\n\t\tstruct kvm_sync_regs regs;\n\t\tchar padding[2048];\n\t} s;\n};\n\nstruct kvm_s390_apcb0 {\n\t__u64 apm[1];\n\t__u64 aqm[1];\n\t__u64 adm[1];\n\t__u64 reserved18;\n};\n\nstruct kvm_s390_apcb1 {\n\t__u64 apm[4];\n\t__u64 aqm[4];\n\t__u64 adm[4];\n\t__u64 reserved60[4];\n};\n\nstruct kvm_s390_crypto_cb {\n\tstruct kvm_s390_apcb0 apcb0;\n\t__u8 reserved20[40];\n\t__u8 dea_wrapping_key_mask[24];\n\t__u8 aes_wrapping_key_mask[32];\n\tstruct kvm_s390_apcb1 apcb1;\n};\n\nstruct kvm_s390_emerg_info {\n\t__u16 code;\n};\n\nstruct kvm_s390_extcall_info {\n\t__u16 code;\n};\n\nstruct kvm_s390_gisa {\n\tunion {\n\t\tstruct {\n\t\t\tu32 next_alert;\n\t\t\tu8 ipm;\n\t\t\tu8 reserved01[2];\n\t\t\tu8 iam;\n\t\t};\n\t\tstruct {\n\t\t\tu32 next_alert;\n\t\t\tu8 ipm;\n\t\t\tu8 reserved01;\n\t\t\tchar: 6;\n\t\t\tu8 g: 1;\n\t\t\tu8 c: 1;\n\t\t\tu8 iam;\n\t\t\tu8 reserved02[4];\n\t\t\tu32 airq_count;\n\t\t} g0;\n\t\tstruct {\n\t\t\tu32 next_alert;\n\t\t\tu8 ipm;\n\t\t\tu8 simm;\n\t\t\tu8 nimm;\n\t\t\tu8 iam;\n\t\t\tu8 aism[8];\n\t\t\tchar: 6;\n\t\t\tu8 g: 1;\n\t\t\tu8 c: 1;\n\t\t\tu8 reserved03[11];\n\t\t\tu32 airq_count;\n\t\t} g1;\n\t\tstruct {\n\t\t\tu64 word[4];\n\t\t} u64;\n\t};\n};\n\nstruct kvm_s390_io_info {\n\t__u16 subchannel_id;\n\t__u16 subchannel_nr;\n\t__u32 io_int_parm;\n\t__u32 io_int_word;\n};\n\nstruct kvm_s390_pgm_info {\n\t__u64 trans_exc_code;\n\t__u64 mon_code;\n\t__u64 per_address;\n\t__u32 data_exc_code;\n\t__u16 code;\n\t__u16 mon_class_nr;\n\t__u8 per_code;\n\t__u8 per_atmid;\n\t__u8 exc_access_id;\n\t__u8 per_access_id;\n\t__u8 op_access_id;\n\t__u8 flags;\n\t__u8 pad[2];\n};\n\nstruct kvm_s390_prefix_info {\n\t__u32 address;\n};\n\nstruct kvm_s390_stop_info {\n\t__u32 flags;\n};\n\nstruct kvm_s390_irq_payload {\n\tstruct kvm_s390_io_info io;\n\tstruct kvm_s390_ext_info ext;\n\tstruct kvm_s390_pgm_info pgm;\n\tstruct kvm_s390_emerg_info emerg;\n\tstruct kvm_s390_extcall_info extcall;\n\tstruct kvm_s390_prefix_info prefix;\n\tstruct kvm_s390_stop_info stop;\n\tstruct kvm_s390_mchk_info mchk;\n};\n\nstruct kvm_s390_itdb {\n\t__u8 data[256];\n};\n\nstruct kvm_s390_local_interrupt {\n\tspinlock_t lock;\n\tlong unsigned int sigp_emerg_pending[4];\n\tstruct kvm_s390_irq_payload irq;\n\tlong unsigned int pending_irqs;\n};\n\nstruct kvm_s390_pv_vcpu {\n\tu64 handle;\n\tlong unsigned int stor_base;\n};\n\nstruct kvm_s390_sie_block {\n\tatomic_t cpuflags;\n\tchar: 1;\n\t__u32 prefix: 18;\n\tchar: 1;\n\t__u32 ibc: 12;\n\t__u8 reserved08[4];\n\t__u32 prog0c;\n\tunion {\n\t\t__u8 reserved10[16];\n\t\tstruct {\n\t\t\t__u64 pv_handle_cpu;\n\t\t\t__u64 pv_handle_config;\n\t\t};\n\t};\n\tatomic_t prog20;\n\t__u8 reserved24[4];\n\t__u64 cputm;\n\t__u64 ckc;\n\t__u64 epoch;\n\t__u32 svcc;\n\t__u16 lctl;\n\t__s16 icpua;\n\t__u32 ictl;\n\t__u32 eca;\n\t__u8 icptcode;\n\t__u8 icptstatus;\n\t__u16 ihcpu;\n\t__u8 reserved54;\n\t__u8 iictl;\n\t__u16 ipa;\n\t__u32 ipb;\n\t__u32 scaoh;\n\t__u8 fpf;\n\t__u8 ecb;\n\t__u8 ecb2;\n\t__u8 ecb3;\n\t__u32 scaol;\n\t__u8 sdf;\n\t__u8 epdx;\n\t__u8 cpnc;\n\t__u8 reserved6b;\n\t__u32 todpr;\n\t__u32 gd;\n\t__u8 reserved74[12];\n\t__u64 mso;\n\t__u64 msl;\n\tpsw_t gpsw;\n\t__u64 gg14;\n\t__u64 gg15;\n\t__u8 reservedb0[8];\n\t__u8 hpid;\n\t__u8 reservedb9[7];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 eiparams;\n\t\t\t__u16 extcpuaddr;\n\t\t\t__u16 eic;\n\t\t};\n\t\t__u64 mcic;\n\t};\n\t__u32 reservedc8;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 pgmilc;\n\t\t\t__u16 iprcc;\n\t\t};\n\t\t__u32 edc;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 dxc;\n\t\t\t__u16 mcn;\n\t\t\t__u8 perc;\n\t\t\t__u8 peratmid;\n\t\t};\n\t\t__u64 faddr;\n\t};\n\t__u64 peraddr;\n\t__u8 eai;\n\t__u8 peraid;\n\t__u8 oai;\n\t__u8 armid;\n\t__u8 reservede4[4];\n\tunion {\n\t\t__u64 tecmc;\n\t\tstruct {\n\t\t\t__u16 subchannel_id;\n\t\t\t__u16 subchannel_nr;\n\t\t\t__u32 io_int_parm;\n\t\t\t__u32 io_int_word;\n\t\t};\n\t};\n\t__u8 reservedf4[8];\n\t__u32 crycbd;\n\t__u64 gcr[16];\n\tunion {\n\t\t__u64 gbea;\n\t\t__u64 sidad;\n\t};\n\t__u8 reserved188[8];\n\t__u64 sdnxo;\n\t__u8 reserved198[8];\n\t__u32 fac;\n\t__u8 reserved1a4[20];\n\t__u64 cbrlo;\n\t__u8 reserved1c0[8];\n\t__u32 ecd;\n\t__u8 reserved1cc[18];\n\t__u64 pp;\n\t__u8 reserved1e6[2];\n\t__u64 itdba;\n\t__u64 riccbd;\n\t__u64 gvrd;\n} __attribute__((packed));\n\nstruct kvm_stat_data {\n\tstruct kvm *kvm;\n\tconst struct _kvm_stats_desc *desc;\n\tenum kvm_stat_kind kind;\n};\n\nstruct preempt_ops;\n\nstruct preempt_notifier {\n\tstruct hlist_node link;\n\tstruct preempt_ops *ops;\n};\n\nstruct kvm_vcpu_arch {\n\tstruct kvm_s390_sie_block *sie_block;\n\tstruct kvm_s390_sie_block *vsie_block;\n\tunsigned int host_acrs[16];\n\tstruct gs_cb *host_gscb;\n\tstruct kvm_s390_local_interrupt local_int;\n\tstruct hrtimer ckc_timer;\n\tstruct kvm_s390_pgm_info pgm;\n\tstruct gmap *gmap;\n\tstruct kvm_guestdbg_info_arch guestdbg;\n\tlong unsigned int pfault_token;\n\tlong unsigned int pfault_select;\n\tlong unsigned int pfault_compare;\n\tbool cputm_enabled;\n\tseqcount_t cputm_seqcount;\n\t__u64 cputm_start;\n\tbool gs_enabled;\n\tbool skey_enabled;\n\tbool acrs_loaded;\n\tstruct kvm_s390_pv_vcpu pv;\n\tunion diag318_info diag318_info;\n\tstruct kvm_s390_mmu_cache *mc;\n};\n\nstruct kvm_vcpu_stat_generic {\n\tu64 halt_successful_poll;\n\tu64 halt_attempted_poll;\n\tu64 halt_poll_invalid;\n\tu64 halt_wakeup;\n\tu64 halt_poll_success_ns;\n\tu64 halt_poll_fail_ns;\n\tu64 halt_wait_ns;\n\tu64 halt_poll_success_hist[32];\n\tu64 halt_poll_fail_hist[32];\n\tu64 halt_wait_hist[32];\n\tu64 blocking;\n};\n\nstruct kvm_vcpu_stat {\n\tstruct kvm_vcpu_stat_generic generic;\n\tu64 exit_userspace;\n\tu64 exit_null;\n\tu64 exit_external_request;\n\tu64 exit_io_request;\n\tu64 exit_external_interrupt;\n\tu64 exit_stop_request;\n\tu64 exit_validity;\n\tu64 exit_instruction;\n\tu64 exit_pei;\n\tu64 halt_no_poll_steal;\n\tu64 instruction_lctl;\n\tu64 instruction_lctlg;\n\tu64 instruction_stctl;\n\tu64 instruction_stctg;\n\tu64 exit_program_interruption;\n\tu64 exit_instr_and_program;\n\tu64 exit_operation_exception;\n\tu64 deliver_ckc;\n\tu64 deliver_cputm;\n\tu64 deliver_external_call;\n\tu64 deliver_emergency_signal;\n\tu64 deliver_service_signal;\n\tu64 deliver_virtio;\n\tu64 deliver_stop_signal;\n\tu64 deliver_prefix_signal;\n\tu64 deliver_restart_signal;\n\tu64 deliver_program;\n\tu64 deliver_io;\n\tu64 deliver_machine_check;\n\tu64 exit_wait_state;\n\tu64 inject_ckc;\n\tu64 inject_cputm;\n\tu64 inject_external_call;\n\tu64 inject_emergency_signal;\n\tu64 inject_mchk;\n\tu64 inject_pfault_init;\n\tu64 inject_program;\n\tu64 inject_restart;\n\tu64 inject_set_prefix;\n\tu64 inject_stop_signal;\n\tu64 instruction_epsw;\n\tu64 instruction_gs;\n\tu64 instruction_io_other;\n\tu64 instruction_lpsw;\n\tu64 instruction_lpswe;\n\tu64 instruction_lpswey;\n\tu64 instruction_pfmf;\n\tu64 instruction_ptff;\n\tu64 instruction_sck;\n\tu64 instruction_sckpf;\n\tu64 instruction_stidp;\n\tu64 instruction_spx;\n\tu64 instruction_stpx;\n\tu64 instruction_stap;\n\tu64 instruction_iske;\n\tu64 instruction_ri;\n\tu64 instruction_rrbe;\n\tu64 instruction_sske;\n\tu64 instruction_ipte_interlock;\n\tu64 instruction_stsi;\n\tu64 instruction_stfl;\n\tu64 instruction_tb;\n\tu64 instruction_tpi;\n\tu64 instruction_tprot;\n\tu64 instruction_tsch;\n\tu64 instruction_sie;\n\tu64 instruction_essa;\n\tu64 instruction_sthyi;\n\tu64 instruction_sigp_sense;\n\tu64 instruction_sigp_sense_running;\n\tu64 instruction_sigp_external_call;\n\tu64 instruction_sigp_emergency;\n\tu64 instruction_sigp_cond_emergency;\n\tu64 instruction_sigp_start;\n\tu64 instruction_sigp_stop;\n\tu64 instruction_sigp_stop_store_status;\n\tu64 instruction_sigp_store_status;\n\tu64 instruction_sigp_store_adtl_status;\n\tu64 instruction_sigp_arch;\n\tu64 instruction_sigp_prefix;\n\tu64 instruction_sigp_restart;\n\tu64 instruction_sigp_init_cpu_reset;\n\tu64 instruction_sigp_cpu_reset;\n\tu64 instruction_sigp_unknown;\n\tu64 instruction_diagnose_10;\n\tu64 instruction_diagnose_44;\n\tu64 instruction_diagnose_9c;\n\tu64 diag_9c_ignored;\n\tu64 diag_9c_forward;\n\tu64 instruction_diagnose_258;\n\tu64 instruction_diagnose_308;\n\tu64 instruction_diagnose_500;\n\tu64 instruction_diagnose_other;\n\tu64 pfault_sync;\n\tu64 signal_exits;\n};\n\nstruct kvm_vcpu {\n\tstruct kvm *kvm;\n\tstruct preempt_notifier preempt_notifier;\n\tint cpu;\n\tint vcpu_id;\n\tint vcpu_idx;\n\tint ____srcu_idx;\n\tint mode;\n\tu64 requests;\n\tlong unsigned int guest_debug;\n\tstruct mutex mutex;\n\tstruct kvm_run *run;\n\tstruct rcuwait wait;\n\tstruct pid *pid;\n\trwlock_t pid_lock;\n\tint sigset_active;\n\tsigset_t sigset;\n\tunsigned int halt_poll_ns;\n\tbool valid_wakeup;\n\tint mmio_needed;\n\tint mmio_read_completed;\n\tint mmio_is_write;\n\tint mmio_cur_fragment;\n\tint mmio_nr_fragments;\n\tstruct kvm_mmio_fragment mmio_fragments[2];\n\tstruct {\n\t\tu32 queued;\n\t\tstruct list_head queue;\n\t\tstruct list_head done;\n\t\tspinlock_t lock;\n\t} async_pf;\n\tstruct {\n\t\tbool in_spin_loop;\n\t\tbool dy_eligible;\n\t} spin_loop;\n\tbool wants_to_run;\n\tbool preempted;\n\tbool ready;\n\tbool scheduled_out;\n\tstruct kvm_vcpu_arch arch;\n\tstruct kvm_vcpu_stat stat;\n\tchar stats_id[48];\n\tstruct kvm_dirty_ring dirty_ring;\n\tstruct kvm_memory_slot *last_used_slot;\n\tu64 last_used_slot_gen;\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nstruct vtoc_cchhb {\n\t__u16 cc;\n\t__u16 hh;\n\t__u8 b;\n} __attribute__((packed));\n\nstruct vtoc_volume_label_cdl {\n\tchar volkey[4];\n\tchar vollbl[4];\n\tchar volid[6];\n\t__u8 security;\n\tstruct vtoc_cchhb vtoc;\n\tchar res1[5];\n\tchar cisize[4];\n\tchar blkperci[4];\n\tchar labperci[4];\n\tchar res2[4];\n\tchar lvtoc[14];\n\tchar res3[29];\n};\n\nstruct vtoc_volume_label_ldl {\n\tchar vollbl[4];\n\tchar volid[6];\n\tchar res3[69];\n\tchar ldl_version;\n\t__u64 formatted_blocks;\n};\n\nstruct vtoc_cms_label {\n\t__u8 label_id[4];\n\t__u8 vol_id[6];\n\t__u16 version_id;\n\t__u32 block_size;\n\t__u32 origin_ptr;\n\t__u32 usable_count;\n\t__u32 formatted_count;\n\t__u32 block_count;\n\t__u32 used_count;\n\t__u32 fst_size;\n\t__u32 fst_count;\n\t__u8 format_date[6];\n\t__u8 reserved1[2];\n\t__u32 disk_offset;\n\t__u32 map_block;\n\t__u32 hblk_disp;\n\t__u32 user_disp;\n\t__u8 reserved2[4];\n\t__u8 segment_name[8];\n};\n\nunion label_t {\n\tstruct vtoc_volume_label_cdl vol;\n\tstruct vtoc_volume_label_ldl lnx;\n\tstruct vtoc_cms_label cms;\n};\n\nstruct landlock_ruleset;\n\nstruct landlock_cred_security {\n\tstruct landlock_ruleset *domain;\n\tu16 domain_exec;\n\tu8 log_subdomains_off: 1;\n} __attribute__((packed));\n\nstruct landlock_details {\n\tstruct pid *pid;\n\tuid_t uid;\n\tchar comm[16];\n\tchar exe_path[0];\n};\n\nstruct landlock_erratum {\n\tconst int abi;\n\tconst u8 number;\n};\n\nstruct landlock_file_security {\n\taccess_mask_t allowed_access;\n\tdeny_masks_t deny_masks;\n\tu8 fown_layer;\n\tstruct landlock_cred_security fown_subject;\n};\n\nstruct landlock_hierarchy {\n\tstruct landlock_hierarchy *parent;\n\trefcount_t usage;\n\tenum landlock_log_status log_status;\n\tatomic64_t num_denials;\n\tu64 id;\n\tconst struct landlock_details *details;\n\tu32 log_same_exec: 1;\n\tu32 log_new_exec: 1;\n};\n\nstruct landlock_object;\n\nunion landlock_key {\n\tstruct landlock_object *object;\n\tuintptr_t data;\n};\n\nstruct landlock_id {\n\tunion landlock_key key;\n\tconst enum landlock_key_type type;\n};\n\nstruct landlock_inode_security {\n\tstruct landlock_object *object;\n};\n\nstruct landlock_layer {\n\tu16 level;\n\taccess_mask_t access;\n};\n\nstruct landlock_net_port_attr {\n\t__u64 allowed_access;\n\t__u64 port;\n};\n\nstruct landlock_object_underops;\n\nstruct landlock_object {\n\trefcount_t usage;\n\tspinlock_t lock;\n\tvoid *underobj;\n\tunion {\n\t\tstruct callback_head rcu_free;\n\t\tconst struct landlock_object_underops *underops;\n\t};\n};\n\nstruct landlock_object_underops {\n\tvoid (*release)(struct landlock_object * const);\n};\n\nstruct landlock_path_beneath_attr {\n\t__u64 allowed_access;\n\t__s32 parent_fd;\n} __attribute__((packed));\n\nstruct layer_access_masks;\n\nstruct landlock_request {\n\tenum landlock_request_type type;\n\tstruct common_audit_data audit;\n\tsize_t layer_plus_one;\n\taccess_mask_t access;\n\tconst struct layer_access_masks *layer_masks;\n\tconst access_mask_t all_existing_optional_access;\n\tdeny_masks_t deny_masks;\n};\n\nstruct landlock_rule {\n\tstruct rb_node node;\n\tunion landlock_key key;\n\tu32 num_layers;\n\tstruct landlock_layer layers[0];\n};\n\nstruct landlock_ruleset {\n\tstruct rb_root root_inode;\n\tstruct rb_root root_net_port;\n\tstruct landlock_hierarchy *hierarchy;\n\tunion {\n\t\tstruct work_struct work_free;\n\t\tstruct {\n\t\t\tstruct mutex lock;\n\t\t\trefcount_t usage;\n\t\t\tu32 num_rules;\n\t\t\tu32 num_layers;\n\t\t\tstruct access_masks access_masks[0];\n\t\t};\n\t};\n};\n\nstruct landlock_ruleset_attr {\n\t__u64 handled_access_fs;\n\t__u64 handled_access_net;\n\t__u64 scoped;\n};\n\nstruct landlock_superblock_security {\n\tatomic_long_t inode_refs;\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tu64 val[2];\n};\n\nstruct latency_record {\n\tlong unsigned int backtrace[12];\n\tunsigned int count;\n\tlong unsigned int time;\n\tlong unsigned int max;\n};\n\nstruct layer_access_masks {\n\taccess_mask_t access[16];\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct lcd_properties {\n\tint max_contrast;\n};\n\nstruct lcd_ops;\n\nstruct lcd_device {\n\tstruct lcd_properties props;\n\tstruct mutex ops_lock;\n\tconst struct lcd_ops *ops;\n\tstruct mutex update_lock;\n\tstruct list_head entry;\n\tstruct device dev;\n};\n\nstruct lcd_ops {\n\tint (*get_power)(struct lcd_device *);\n\tint (*set_power)(struct lcd_device *, int);\n\tint (*get_contrast)(struct lcd_device *);\n\tint (*set_contrast)(struct lcd_device *, int);\n\tint (*set_mode)(struct lcd_device *, u32, u32);\n\tbool (*controls_device)(struct lcd_device *, struct device *);\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct level_datum {\n\tstruct mls_level level;\n\tunsigned char isalias;\n};\n\nstruct lgr_info {\n\tu64 stfle_fac_list[4];\n\tu32 level;\n\tchar manufacturer[16];\n\tchar type[4];\n\tchar sequence[16];\n\tchar plant[4];\n\tchar model[16];\n\tu16 lpar_number;\n\tchar name[8];\n\tu8 vm_count;\n\tstruct {\n\t\tchar name[8];\n\t\tchar cpi[16];\n\t} vm[2];\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linear_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_free {\n\tunion {\n\t\tlong unsigned int next;\n\t\tlong unsigned int handle;\n\t};\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct linux_tls_mib {\n\tlong unsigned int mibs[18];\n};\n\nstruct node_descriptor {\n\tunion {\n\t\tstruct {\n\t\t\tu32 validity: 3;\n\t\t\tu32 reserved: 5;\n\t\t} __attribute__((packed));\n\t\tu8 byte0;\n\t};\n\tu32 params: 24;\n\tchar type[6];\n\tchar model[3];\n\tchar manufacturer[3];\n\tchar plant[2];\n\tchar seq[12];\n\tu16 tag;\n};\n\nstruct lir {\n\tstruct {\n\t\tu32 null: 1;\n\t\tu32 reserved: 3;\n\t\tu32 class: 2;\n\t\tu32 reserved2: 2;\n\t} __attribute__((packed)) iq;\n\tu32 ic: 8;\n\tu32 reserved: 16;\n\tstruct node_descriptor incident_node;\n\tstruct node_descriptor attached_node;\n\tu8 reserved2[32];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n\tstruct list_head list;\n\tint shrinker_id;\n\tbool memcg_aware;\n\tstruct xarray xa;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_memcg {\n\tstruct callback_head rcu;\n\tstruct list_lru_one node[0];\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct listener {\n\tstruct list_head list;\n\tpid_t pid;\n\tchar valid;\n};\n\nstruct listener_list {\n\tstruct rw_semaphore sem;\n\tstruct list_head list;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct llbitmap_page_ctl;\n\nstruct llbitmap {\n\tstruct mddev *mddev;\n\tstruct llbitmap_page_ctl **pctl;\n\tunsigned int nr_pages;\n\tunsigned int io_size;\n\tunsigned int blocks_per_page;\n\tlong unsigned int chunkshift;\n\tlong unsigned int chunksize;\n\tlong unsigned int chunks;\n\tlong unsigned int last_end_sync;\n\tlong unsigned int barrier_idle;\n\tstruct timer_list pending_timer;\n\tstruct work_struct daemon_work;\n\tlong unsigned int flags;\n\t__u64 events_cleared;\n\tatomic_t behind_writes;\n\twait_queue_head_t behind_wait;\n};\n\nstruct llbitmap_page_ctl {\n\tchar *state;\n\tstruct page *page;\n\tlong unsigned int expire;\n\tlong unsigned int flags;\n\twait_queue_head_t wait;\n\tstruct percpu_ref active;\n\tlong unsigned int dirty[0];\n};\n\nstruct llbitmap_unplug_work {\n\tstruct work_struct work;\n\tstruct llbitmap *llbitmap;\n\tstruct completion *done;\n};\n\nstruct llc_addr {\n\tunsigned char lsap;\n\tunsigned char mac[6];\n};\n\nstruct llc_pdu_sn {\n\tu8 dsap;\n\tu8 ssap;\n\tu8 ctrl_1;\n\tu8 ctrl_2;\n};\n\nstruct llc_pdu_un {\n\tu8 dsap;\n\tu8 ssap;\n\tu8 ctrl_1;\n};\n\nstruct llc_sap {\n\tunsigned char state;\n\tunsigned char p_bit;\n\tunsigned char f_bit;\n\trefcount_t refcnt;\n\tint (*rcv_func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tstruct llc_addr laddr;\n\tstruct list_head node;\n\tspinlock_t sk_lock;\n\tint sk_count;\n\tstruct hlist_nulls_head sk_laddr_hash[64];\n\tstruct hlist_head sk_dev_hash[64];\n\tstruct callback_head rcu;\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf64_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct location;\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n\tloff_t idx;\n};\n\nstruct local_event {\n\tlocal_lock_t lock;\n\t__u32 count;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct location {\n\tdepot_stack_handle_t handle;\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong unsigned int waste;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[8];\n\tnodemask_t nodes;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tloff_t li_pos;\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct lookup_args {\n\tint offset;\n\tconst struct in6_addr *addr;\n};\n\nstruct pgm_tdb {\n\tu64 data[32];\n};\n\nstruct lowcore {\n\t__u8 pad_0x0000[20];\n\t__u32 ipl_parmblock_ptr;\n\t__u8 pad_0x0018[104];\n\t__u32 ext_params;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 ext_cpu_addr;\n\t\t\t__u16 ext_int_code;\n\t\t};\n\t\t__u32 ext_int_code_addr;\n\t};\n\t__u32 svc_int_code;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 pgm_ilc;\n\t\t\t__u16 pgm_code;\n\t\t};\n\t\t__u32 pgm_int_code;\n\t};\n\t__u32 data_exc_code;\n\t__u16 mon_class_num;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 per_code;\n\t\t\t__u8 per_atmid;\n\t\t};\n\t\t__u16 per_code_combined;\n\t};\n\t__u64 per_address;\n\t__u8 exc_access_id;\n\t__u8 per_access_id;\n\t__u8 op_access_id;\n\t__u8 ar_mode_id;\n\t__u8 pad_0x00a4[4];\n\t__u64 trans_exc_code;\n\t__u64 monitor_code;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 subchannel_id;\n\t\t\t__u16 subchannel_nr;\n\t\t\t__u32 io_int_parm;\n\t\t\t__u32 io_int_word;\n\t\t};\n\t\tstruct tpi_info tpi_info;\n\t};\n\t__u8 pad_0x00c4[4];\n\t__u32 stfl_fac_list;\n\t__u8 pad_0x00cc[28];\n\t__u64 mcck_interruption_code;\n\t__u8 pad_0x00f0[4];\n\t__u32 external_damage_code;\n\t__u64 failing_storage_address;\n\t__u8 pad_0x0100[16];\n\t__u64 pgm_last_break;\n\t__u8 pad_0x0118[8];\n\tpsw_t restart_old_psw;\n\tpsw_t external_old_psw;\n\tpsw_t svc_old_psw;\n\tpsw_t program_old_psw;\n\tpsw_t mcck_old_psw;\n\tpsw_t io_old_psw;\n\t__u8 pad_0x0180[32];\n\tpsw_t restart_psw;\n\tpsw_t external_new_psw;\n\tpsw_t svc_new_psw;\n\tpsw_t program_new_psw;\n\tpsw_t mcck_new_psw;\n\tpsw_t io_new_psw;\n\t__u64 save_area[8];\n\t__u64 stack_canary;\n\t__u8 pad_0x0248[56];\n\t__u64 save_area_restart[1];\n\t__u64 pcpu;\n\tpsw_t return_psw;\n\tpsw_t return_mcck_psw;\n\t__u64 last_break;\n\t__u64 sys_enter_timer;\n\t__u64 mcck_enter_timer;\n\t__u64 exit_timer;\n\t__u64 user_timer;\n\t__u64 guest_timer;\n\t__u64 system_timer;\n\t__u64 hardirq_timer;\n\t__u64 softirq_timer;\n\t__u64 steal_timer;\n\t__u64 avg_steal_timer;\n\t__u64 last_update_timer;\n\t__u64 last_update_clock;\n\t__u64 int_clock;\n\t__u8 pad_0x0320[8];\n\t__u64 clock_comparator;\n\t__u8 pad_0x0330[16];\n\t__u64 current_task;\n\t__u64 kernel_stack;\n\t__u64 async_stack;\n\t__u64 nodat_stack;\n\t__u64 restart_stack;\n\t__u64 mcck_stack;\n\t__u64 restart_fn;\n\t__u64 restart_data;\n\t__u32 restart_source;\n\t__u32 restart_flags;\n\tstruct ctlreg kernel_asce;\n\tstruct ctlreg user_asce;\n\t__u32 lpp;\n\t__u32 current_pid;\n\t__u32 cpu_nr;\n\t__u32 softirq_pending;\n\t__s32 preempt_count;\n\t__u32 spinlock_lockval;\n\t__u32 spinlock_index;\n\t__u8 pad_0x03b4[4];\n\t__u64 percpu_offset;\n\t__u8 pad_0x03c0[64];\n\t__u32 return_lpswe;\n\t__u32 return_mcck_lpswe;\n\t__u8 pad_0x040a[2552];\n\t__u64 ipib;\n\t__u32 ipib_checksum;\n\t__u64 vmcore_info;\n\t__u8 pad_0x0e14[4];\n\t__u64 os_info;\n\t__u8 pad_0x0e20[912];\n\t__u64 mcesad;\n\t__u64 ext_params2;\n\t__u8 pad_0x11c0[64];\n\t__u64 floating_pt_save_area[16];\n\t__u64 gpregs_save_area[16];\n\tpsw_t psw_save_area;\n\t__u8 pad_0x1310[8];\n\t__u32 prefixreg_save_area;\n\t__u32 fpt_creg_save_area;\n\t__u8 pad_0x1320[4];\n\t__u32 tod_progreg_save_area;\n\t__u32 cpu_timer_save_area[2];\n\t__u32 clock_comp_save_area[2];\n\t__u64 last_break_save_area;\n\t__u32 access_regs_save_area[16];\n\tstruct ctlreg cregs_save_area[16];\n\t__u8 pad_0x1400[256];\n\t__u64 ccd;\n\t__u64 aicd;\n\t__u8 pad_0x1510[752];\n\tstruct pgm_tdb pgm_tdb;\n\t__u8 pad_0x1900[1792];\n} __attribute__((packed));\n\nunion lower_chunk {\n\tunion lower_chunk *next;\n\tlong unsigned int data[256];\n};\n\nstruct lpar_cpu_inf {\n\tstruct cpu_inf cp;\n\tstruct cpu_inf ifl;\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct zswap_lruvec_state {\n\tatomic_long_t nr_disk_swapins;\n};\n\nstruct pglist_data;\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct pglist_data *pgdat;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct lruvec_stats {\n\tlong int state[33];\n\tlong int state_local[33];\n\tlong int state_pending[33];\n};\n\nstruct lruvec_stats_percpu {\n\tlong int state[33];\n\tlong int state_prev[33];\n};\n\nstruct skcipher_alg_common {\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct lskcipher_alg {\n\tint (*setkey)(struct crypto_lskcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*decrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*init)(struct crypto_lskcipher *);\n\tvoid (*exit)(struct crypto_lskcipher *);\n\tstruct skcipher_alg_common co;\n};\n\nstruct lskcipher_instance {\n\tvoid (*free)(struct lskcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct lskcipher_alg alg;\n\t};\n};\n\nstruct lsm_blob_sizes {\n\tunsigned int lbs_cred;\n\tunsigned int lbs_file;\n\tunsigned int lbs_ib;\n\tunsigned int lbs_inode;\n\tunsigned int lbs_sock;\n\tunsigned int lbs_superblock;\n\tunsigned int lbs_ipc;\n\tunsigned int lbs_key;\n\tunsigned int lbs_msg_msg;\n\tunsigned int lbs_perf_event;\n\tunsigned int lbs_task;\n\tunsigned int lbs_xattr_count;\n\tunsigned int lbs_tun_dev;\n\tunsigned int lbs_bdev;\n\tunsigned int lbs_bpf_map;\n\tunsigned int lbs_bpf_prog;\n\tunsigned int lbs_bpf_token;\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct lsm_ctx {\n\t__u64 id;\n\t__u64 flags;\n\t__u64 len;\n\t__u64 ctx_len;\n\t__u8 ctx[0];\n};\n\nstruct lsm_ibendport_audit {\n\tconst char *dev_name;\n\tu8 port;\n};\n\nstruct lsm_ibpkey_audit {\n\tu64 subnet_prefix;\n\tu16 pkey;\n};\n\nstruct lsm_id {\n\tconst char *name;\n\tu64 id;\n};\n\nstruct lsm_info {\n\tconst struct lsm_id *id;\n\tenum lsm_order order;\n\tlong unsigned int flags;\n\tstruct lsm_blob_sizes *blobs;\n\tint *enabled;\n\tint (*init)(void);\n\tint (*initcall_pure)(void);\n\tint (*initcall_early)(void);\n\tint (*initcall_core)(void);\n\tint (*initcall_subsys)(void);\n\tint (*initcall_fs)(void);\n\tint (*initcall_device)(void);\n\tint (*initcall_late)(void);\n};\n\nstruct lsm_ioctlop_audit {\n\tstruct path path;\n\tu16 cmd;\n};\n\nstruct lsm_network_audit {\n\tint netif;\n\tconst struct sock *sk;\n\tu16 family;\n\t__be16 dport;\n\t__be16 sport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 daddr;\n\t\t\t__be32 saddr;\n\t\t} v4;\n\t\tstruct {\n\t\t\tstruct in6_addr daddr;\n\t\t\tstruct in6_addr saddr;\n\t\t} v6;\n\t} fam;\n};\n\nstruct static_call_key;\n\nstruct security_hook_list;\n\nstruct lsm_static_call {\n\tstruct static_call_key *key;\n\tvoid *trampoline;\n\tstruct security_hook_list *hl;\n\tstruct static_key_false *active;\n};\n\nstruct lsm_static_calls_table {\n\tstruct lsm_static_call binder_set_context_mgr[6];\n\tstruct lsm_static_call binder_transaction[6];\n\tstruct lsm_static_call binder_transfer_binder[6];\n\tstruct lsm_static_call binder_transfer_file[6];\n\tstruct lsm_static_call ptrace_access_check[6];\n\tstruct lsm_static_call ptrace_traceme[6];\n\tstruct lsm_static_call capget[6];\n\tstruct lsm_static_call capset[6];\n\tstruct lsm_static_call capable[6];\n\tstruct lsm_static_call quotactl[6];\n\tstruct lsm_static_call quota_on[6];\n\tstruct lsm_static_call syslog[6];\n\tstruct lsm_static_call settime[6];\n\tstruct lsm_static_call vm_enough_memory[6];\n\tstruct lsm_static_call bprm_creds_for_exec[6];\n\tstruct lsm_static_call bprm_creds_from_file[6];\n\tstruct lsm_static_call bprm_check_security[6];\n\tstruct lsm_static_call bprm_committing_creds[6];\n\tstruct lsm_static_call bprm_committed_creds[6];\n\tstruct lsm_static_call fs_context_submount[6];\n\tstruct lsm_static_call fs_context_dup[6];\n\tstruct lsm_static_call fs_context_parse_param[6];\n\tstruct lsm_static_call sb_alloc_security[6];\n\tstruct lsm_static_call sb_delete[6];\n\tstruct lsm_static_call sb_free_security[6];\n\tstruct lsm_static_call sb_free_mnt_opts[6];\n\tstruct lsm_static_call sb_eat_lsm_opts[6];\n\tstruct lsm_static_call sb_mnt_opts_compat[6];\n\tstruct lsm_static_call sb_remount[6];\n\tstruct lsm_static_call sb_kern_mount[6];\n\tstruct lsm_static_call sb_show_options[6];\n\tstruct lsm_static_call sb_statfs[6];\n\tstruct lsm_static_call sb_mount[6];\n\tstruct lsm_static_call sb_umount[6];\n\tstruct lsm_static_call sb_pivotroot[6];\n\tstruct lsm_static_call sb_set_mnt_opts[6];\n\tstruct lsm_static_call sb_clone_mnt_opts[6];\n\tstruct lsm_static_call move_mount[6];\n\tstruct lsm_static_call dentry_init_security[6];\n\tstruct lsm_static_call dentry_create_files_as[6];\n\tstruct lsm_static_call path_unlink[6];\n\tstruct lsm_static_call path_mkdir[6];\n\tstruct lsm_static_call path_rmdir[6];\n\tstruct lsm_static_call path_mknod[6];\n\tstruct lsm_static_call path_post_mknod[6];\n\tstruct lsm_static_call path_truncate[6];\n\tstruct lsm_static_call path_symlink[6];\n\tstruct lsm_static_call path_link[6];\n\tstruct lsm_static_call path_rename[6];\n\tstruct lsm_static_call path_chmod[6];\n\tstruct lsm_static_call path_chown[6];\n\tstruct lsm_static_call path_chroot[6];\n\tstruct lsm_static_call path_notify[6];\n\tstruct lsm_static_call inode_alloc_security[6];\n\tstruct lsm_static_call inode_free_security[6];\n\tstruct lsm_static_call inode_free_security_rcu[6];\n\tstruct lsm_static_call inode_init_security[6];\n\tstruct lsm_static_call inode_init_security_anon[6];\n\tstruct lsm_static_call inode_create[6];\n\tstruct lsm_static_call inode_post_create_tmpfile[6];\n\tstruct lsm_static_call inode_link[6];\n\tstruct lsm_static_call inode_unlink[6];\n\tstruct lsm_static_call inode_symlink[6];\n\tstruct lsm_static_call inode_mkdir[6];\n\tstruct lsm_static_call inode_rmdir[6];\n\tstruct lsm_static_call inode_mknod[6];\n\tstruct lsm_static_call inode_rename[6];\n\tstruct lsm_static_call inode_readlink[6];\n\tstruct lsm_static_call inode_follow_link[6];\n\tstruct lsm_static_call inode_permission[6];\n\tstruct lsm_static_call inode_setattr[6];\n\tstruct lsm_static_call inode_post_setattr[6];\n\tstruct lsm_static_call inode_getattr[6];\n\tstruct lsm_static_call inode_xattr_skipcap[6];\n\tstruct lsm_static_call inode_setxattr[6];\n\tstruct lsm_static_call inode_post_setxattr[6];\n\tstruct lsm_static_call inode_getxattr[6];\n\tstruct lsm_static_call inode_listxattr[6];\n\tstruct lsm_static_call inode_removexattr[6];\n\tstruct lsm_static_call inode_post_removexattr[6];\n\tstruct lsm_static_call inode_file_setattr[6];\n\tstruct lsm_static_call inode_file_getattr[6];\n\tstruct lsm_static_call inode_set_acl[6];\n\tstruct lsm_static_call inode_post_set_acl[6];\n\tstruct lsm_static_call inode_get_acl[6];\n\tstruct lsm_static_call inode_remove_acl[6];\n\tstruct lsm_static_call inode_post_remove_acl[6];\n\tstruct lsm_static_call inode_need_killpriv[6];\n\tstruct lsm_static_call inode_killpriv[6];\n\tstruct lsm_static_call inode_getsecurity[6];\n\tstruct lsm_static_call inode_setsecurity[6];\n\tstruct lsm_static_call inode_listsecurity[6];\n\tstruct lsm_static_call inode_getlsmprop[6];\n\tstruct lsm_static_call inode_copy_up[6];\n\tstruct lsm_static_call inode_copy_up_xattr[6];\n\tstruct lsm_static_call inode_setintegrity[6];\n\tstruct lsm_static_call kernfs_init_security[6];\n\tstruct lsm_static_call file_permission[6];\n\tstruct lsm_static_call file_alloc_security[6];\n\tstruct lsm_static_call file_release[6];\n\tstruct lsm_static_call file_free_security[6];\n\tstruct lsm_static_call file_ioctl[6];\n\tstruct lsm_static_call file_ioctl_compat[6];\n\tstruct lsm_static_call mmap_addr[6];\n\tstruct lsm_static_call mmap_file[6];\n\tstruct lsm_static_call file_mprotect[6];\n\tstruct lsm_static_call file_lock[6];\n\tstruct lsm_static_call file_fcntl[6];\n\tstruct lsm_static_call file_set_fowner[6];\n\tstruct lsm_static_call file_send_sigiotask[6];\n\tstruct lsm_static_call file_receive[6];\n\tstruct lsm_static_call file_open[6];\n\tstruct lsm_static_call file_post_open[6];\n\tstruct lsm_static_call file_truncate[6];\n\tstruct lsm_static_call task_alloc[6];\n\tstruct lsm_static_call task_free[6];\n\tstruct lsm_static_call cred_alloc_blank[6];\n\tstruct lsm_static_call cred_free[6];\n\tstruct lsm_static_call cred_prepare[6];\n\tstruct lsm_static_call cred_transfer[6];\n\tstruct lsm_static_call cred_getsecid[6];\n\tstruct lsm_static_call cred_getlsmprop[6];\n\tstruct lsm_static_call kernel_act_as[6];\n\tstruct lsm_static_call kernel_create_files_as[6];\n\tstruct lsm_static_call kernel_module_request[6];\n\tstruct lsm_static_call kernel_load_data[6];\n\tstruct lsm_static_call kernel_post_load_data[6];\n\tstruct lsm_static_call kernel_read_file[6];\n\tstruct lsm_static_call kernel_post_read_file[6];\n\tstruct lsm_static_call task_fix_setuid[6];\n\tstruct lsm_static_call task_fix_setgid[6];\n\tstruct lsm_static_call task_fix_setgroups[6];\n\tstruct lsm_static_call task_setpgid[6];\n\tstruct lsm_static_call task_getpgid[6];\n\tstruct lsm_static_call task_getsid[6];\n\tstruct lsm_static_call current_getlsmprop_subj[6];\n\tstruct lsm_static_call task_getlsmprop_obj[6];\n\tstruct lsm_static_call task_setnice[6];\n\tstruct lsm_static_call task_setioprio[6];\n\tstruct lsm_static_call task_getioprio[6];\n\tstruct lsm_static_call task_prlimit[6];\n\tstruct lsm_static_call task_setrlimit[6];\n\tstruct lsm_static_call task_setscheduler[6];\n\tstruct lsm_static_call task_getscheduler[6];\n\tstruct lsm_static_call task_movememory[6];\n\tstruct lsm_static_call task_kill[6];\n\tstruct lsm_static_call task_prctl[6];\n\tstruct lsm_static_call task_to_inode[6];\n\tstruct lsm_static_call userns_create[6];\n\tstruct lsm_static_call ipc_permission[6];\n\tstruct lsm_static_call ipc_getlsmprop[6];\n\tstruct lsm_static_call msg_msg_alloc_security[6];\n\tstruct lsm_static_call msg_msg_free_security[6];\n\tstruct lsm_static_call msg_queue_alloc_security[6];\n\tstruct lsm_static_call msg_queue_free_security[6];\n\tstruct lsm_static_call msg_queue_associate[6];\n\tstruct lsm_static_call msg_queue_msgctl[6];\n\tstruct lsm_static_call msg_queue_msgsnd[6];\n\tstruct lsm_static_call msg_queue_msgrcv[6];\n\tstruct lsm_static_call shm_alloc_security[6];\n\tstruct lsm_static_call shm_free_security[6];\n\tstruct lsm_static_call shm_associate[6];\n\tstruct lsm_static_call shm_shmctl[6];\n\tstruct lsm_static_call shm_shmat[6];\n\tstruct lsm_static_call sem_alloc_security[6];\n\tstruct lsm_static_call sem_free_security[6];\n\tstruct lsm_static_call sem_associate[6];\n\tstruct lsm_static_call sem_semctl[6];\n\tstruct lsm_static_call sem_semop[6];\n\tstruct lsm_static_call netlink_send[6];\n\tstruct lsm_static_call d_instantiate[6];\n\tstruct lsm_static_call getselfattr[6];\n\tstruct lsm_static_call setselfattr[6];\n\tstruct lsm_static_call getprocattr[6];\n\tstruct lsm_static_call setprocattr[6];\n\tstruct lsm_static_call ismaclabel[6];\n\tstruct lsm_static_call secid_to_secctx[6];\n\tstruct lsm_static_call lsmprop_to_secctx[6];\n\tstruct lsm_static_call secctx_to_secid[6];\n\tstruct lsm_static_call release_secctx[6];\n\tstruct lsm_static_call inode_invalidate_secctx[6];\n\tstruct lsm_static_call inode_notifysecctx[6];\n\tstruct lsm_static_call inode_setsecctx[6];\n\tstruct lsm_static_call inode_getsecctx[6];\n\tstruct lsm_static_call post_notification[6];\n\tstruct lsm_static_call watch_key[6];\n\tstruct lsm_static_call unix_stream_connect[6];\n\tstruct lsm_static_call unix_may_send[6];\n\tstruct lsm_static_call socket_create[6];\n\tstruct lsm_static_call socket_post_create[6];\n\tstruct lsm_static_call socket_socketpair[6];\n\tstruct lsm_static_call socket_bind[6];\n\tstruct lsm_static_call socket_connect[6];\n\tstruct lsm_static_call socket_listen[6];\n\tstruct lsm_static_call socket_accept[6];\n\tstruct lsm_static_call socket_sendmsg[6];\n\tstruct lsm_static_call socket_recvmsg[6];\n\tstruct lsm_static_call socket_getsockname[6];\n\tstruct lsm_static_call socket_getpeername[6];\n\tstruct lsm_static_call socket_getsockopt[6];\n\tstruct lsm_static_call socket_setsockopt[6];\n\tstruct lsm_static_call socket_shutdown[6];\n\tstruct lsm_static_call socket_sock_rcv_skb[6];\n\tstruct lsm_static_call socket_getpeersec_stream[6];\n\tstruct lsm_static_call socket_getpeersec_dgram[6];\n\tstruct lsm_static_call sk_alloc_security[6];\n\tstruct lsm_static_call sk_free_security[6];\n\tstruct lsm_static_call sk_clone_security[6];\n\tstruct lsm_static_call sk_getsecid[6];\n\tstruct lsm_static_call sock_graft[6];\n\tstruct lsm_static_call inet_conn_request[6];\n\tstruct lsm_static_call inet_csk_clone[6];\n\tstruct lsm_static_call inet_conn_established[6];\n\tstruct lsm_static_call secmark_relabel_packet[6];\n\tstruct lsm_static_call secmark_refcount_inc[6];\n\tstruct lsm_static_call secmark_refcount_dec[6];\n\tstruct lsm_static_call req_classify_flow[6];\n\tstruct lsm_static_call tun_dev_alloc_security[6];\n\tstruct lsm_static_call tun_dev_create[6];\n\tstruct lsm_static_call tun_dev_attach_queue[6];\n\tstruct lsm_static_call tun_dev_attach[6];\n\tstruct lsm_static_call tun_dev_open[6];\n\tstruct lsm_static_call sctp_assoc_request[6];\n\tstruct lsm_static_call sctp_bind_connect[6];\n\tstruct lsm_static_call sctp_sk_clone[6];\n\tstruct lsm_static_call sctp_assoc_established[6];\n\tstruct lsm_static_call mptcp_add_subflow[6];\n\tstruct lsm_static_call key_alloc[6];\n\tstruct lsm_static_call key_permission[6];\n\tstruct lsm_static_call key_getsecurity[6];\n\tstruct lsm_static_call key_post_create_or_update[6];\n\tstruct lsm_static_call audit_rule_init[6];\n\tstruct lsm_static_call audit_rule_known[6];\n\tstruct lsm_static_call audit_rule_match[6];\n\tstruct lsm_static_call audit_rule_free[6];\n\tstruct lsm_static_call bpf[6];\n\tstruct lsm_static_call bpf_map[6];\n\tstruct lsm_static_call bpf_prog[6];\n\tstruct lsm_static_call bpf_map_create[6];\n\tstruct lsm_static_call bpf_map_free[6];\n\tstruct lsm_static_call bpf_prog_load[6];\n\tstruct lsm_static_call bpf_prog_free[6];\n\tstruct lsm_static_call bpf_token_create[6];\n\tstruct lsm_static_call bpf_token_free[6];\n\tstruct lsm_static_call bpf_token_cmd[6];\n\tstruct lsm_static_call bpf_token_capable[6];\n\tstruct lsm_static_call locked_down[6];\n\tstruct lsm_static_call perf_event_open[6];\n\tstruct lsm_static_call perf_event_alloc[6];\n\tstruct lsm_static_call perf_event_read[6];\n\tstruct lsm_static_call perf_event_write[6];\n\tstruct lsm_static_call uring_override_creds[6];\n\tstruct lsm_static_call uring_sqpoll[6];\n\tstruct lsm_static_call uring_cmd[6];\n\tstruct lsm_static_call uring_allowed[6];\n\tstruct lsm_static_call initramfs_populated[6];\n\tstruct lsm_static_call bdev_alloc_security[6];\n\tstruct lsm_static_call bdev_free_security[6];\n\tstruct lsm_static_call bdev_setintegrity[6];\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lz4_ctx {\n\tvoid *mem;\n\tLZ4_streamDecode_t *dstrm;\n\tLZ4_stream_t *cstrm;\n};\n\nstruct lz4hc_ctx {\n\tvoid *mem;\n\tLZ4_streamDecode_t *dstrm;\n\tLZ4_streamHC_t *cstrm;\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n\tbool pedantic_microlzma;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct mac_addr {\n\tunsigned char addr[6];\n};\n\ntypedef struct mac_addr mac_addr;\n\nstruct mac_addr_lnid {\n\t__u8 mac[6];\n\t__u16 lnid;\n};\n\nstruct mac_sctn {\n\tu8 infmflg1;\n\tu8 infmflg2;\n\tu8 infmval1;\n\tu8 infmval2;\n\tu16 infmscps;\n\tu16 infmdcps;\n\tu16 infmsifl;\n\tu16 infmdifl;\n\tchar infmname[8];\n\tchar infmtype[4];\n\tchar infmmanu[16];\n\tchar infmseq[16];\n\tchar infmpman[4];\n\tu8 reserved[4];\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct map_info___2 {\n\tstruct map_info___2 *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[9];\n\tvoid *slot[10];\n\tlong unsigned int gap[10];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[33];\n\tunion {\n\t\tstruct maple_enode *slot[34];\n\t\tstruct {\n\t\t\tlong unsigned int padding[21];\n\t\t\tlong unsigned int gap[21];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[15];\n\tunion {\n\t\tvoid *slot[16];\n\t\tstruct {\n\t\t\tvoid *pad[15];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[31];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct mapped_device {\n\tstruct mutex suspend_lock;\n\tstruct mutex table_devices_lock;\n\tstruct list_head table_devices;\n\tvoid *map;\n\tlong unsigned int flags;\n\tstruct mutex type_lock;\n\tenum dm_queue_mode type;\n\tint numa_node_id;\n\tstruct request_queue *queue;\n\tatomic_t holders;\n\tatomic_t open_count;\n\tstruct dm_target *immutable_target;\n\tstruct target_type *immutable_target_type;\n\tchar name[16];\n\tstruct gendisk *disk;\n\tstruct dax_device *dax_dev;\n\twait_queue_head_t wait;\n\tlong unsigned int *pending_io;\n\tstruct hd_geometry geometry;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct work;\n\tspinlock_t deferred_lock;\n\tstruct bio_list deferred;\n\tstruct work_struct requeue_work;\n\tstruct dm_io *requeue_list;\n\tvoid *interface_ptr;\n\twait_queue_head_t eventq;\n\tatomic_t event_nr;\n\tatomic_t uevent_seq;\n\tstruct list_head uevent_list;\n\tspinlock_t uevent_lock;\n\tbool init_tio_pdu: 1;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct dm_stats stats;\n\tunsigned int internal_suspend_count;\n\tint swap_bios;\n\tstruct semaphore swap_bios_semaphore;\n\tstruct mutex swap_bios_lock;\n\tstruct dm_md_mempools *mempools;\n\tstruct dm_kobject_holder kobj_holder;\n\tstruct srcu_struct io_barrier;\n\tstruct dm_ima_measurements ima;\n};\n\nstruct mapping_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct rb_node rb_node;\n\t\t\tu64 bytenr;\n\t\t};\n\t\tstruct rb_simple_node simple_node;\n\t};\n\tvoid *data;\n};\n\nstruct mapping_tree {\n\tstruct rb_root rb_root;\n\tspinlock_t lock;\n};\n\nstruct mask_info {\n\tstruct mask_info *next;\n\tunsigned char id;\n\tcpumask_t mask;\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker *c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tlong unsigned int e_flags;\n\tu64 e_value;\n};\n\nstruct mcck_struct {\n\tunsigned int kill_task: 1;\n\tunsigned int channel_report: 1;\n\tunsigned int warning: 1;\n\tunsigned int stp_queue: 1;\n\tlong unsigned int mcck_code;\n};\n\nstruct mcck_volatile_info {\n\t__u64 mcic;\n\t__u64 failing_storage_address;\n\t__u32 ext_damage_code;\n\t__u32 reserved;\n};\n\nstruct mcesa {\n\tu8 vector_save_area[1024];\n\tu8 guarded_storage_save_area[32];\n};\n\nunion mci {\n\tlong unsigned int val;\n\tstruct {\n\t\tu64 sd: 1;\n\t\tu64 pd: 1;\n\t\tu64 sr: 1;\n\t\tchar: 1;\n\t\tu64 cd: 1;\n\t\tu64 ed: 1;\n\t\tchar: 1;\n\t\tu64 dg: 1;\n\t\tu64 w: 1;\n\t\tu64 cp: 1;\n\t\tu64 sp: 1;\n\t\tu64 ck: 1;\n\t\tchar: 2;\n\t\tu64 b: 1;\n\t\tshort: 1;\n\t\tu64 se: 1;\n\t\tu64 sc: 1;\n\t\tu64 ke: 1;\n\t\tu64 ds: 1;\n\t\tu64 wp: 1;\n\t\tu64 ms: 1;\n\t\tu64 pm: 1;\n\t\tu64 ia: 1;\n\t\tu64 fa: 1;\n\t\tu64 vr: 1;\n\t\tu64 ec: 1;\n\t\tu64 fp: 1;\n\t\tu64 gr: 1;\n\t\tu64 cr: 1;\n\t\tchar: 1;\n\t\tu64 st: 1;\n\t\tu64 ie: 1;\n\t\tu64 ar: 1;\n\t\tu64 da: 1;\n\t\tchar: 1;\n\t\tu64 gs: 1;\n\t\tchar: 3;\n\t\tchar: 2;\n\t\tu64 pr: 1;\n\t\tu64 fc: 1;\n\t\tu64 ap: 1;\n\t\tchar: 1;\n\t\tu64 ct: 1;\n\t\tu64 cc: 1;\n\t};\n};\n\nstruct md_bitmap_stats {\n\tu64 events_cleared;\n\tint behind_writes;\n\tbool behind_wait;\n\tlong unsigned int missing_pages;\n\tlong unsigned int file_pages;\n\tlong unsigned int sync_size;\n\tlong unsigned int pages;\n\tstruct file *file;\n};\n\nstruct md_rdev;\n\nstruct md_cluster_operations {\n\tstruct md_submodule_head head;\n\tint (*join)(struct mddev *, int);\n\tint (*leave)(struct mddev *);\n\tint (*slot_number)(struct mddev *);\n\tint (*resync_info_update)(struct mddev *, sector_t, sector_t);\n\tint (*resync_start_notify)(struct mddev *);\n\tint (*resync_status_get)(struct mddev *);\n\tvoid (*resync_info_get)(struct mddev *, sector_t *, sector_t *);\n\tint (*metadata_update_start)(struct mddev *);\n\tint (*metadata_update_finish)(struct mddev *);\n\tvoid (*metadata_update_cancel)(struct mddev *);\n\tint (*resync_start)(struct mddev *);\n\tint (*resync_finish)(struct mddev *);\n\tint (*area_resyncing)(struct mddev *, int, sector_t, sector_t);\n\tint (*add_new_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*add_new_disk_cancel)(struct mddev *);\n\tint (*new_disk_ack)(struct mddev *, bool);\n\tint (*remove_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*load_bitmaps)(struct mddev *, int);\n\tint (*gather_bitmaps)(struct md_rdev *);\n\tint (*resize_bitmaps)(struct mddev *, sector_t, sector_t);\n\tint (*lock_all_bitmaps)(struct mddev *);\n\tvoid (*unlock_all_bitmaps)(struct mddev *);\n\tvoid (*update_size)(struct mddev *, sector_t);\n};\n\nstruct md_io_clone {\n\tstruct mddev *mddev;\n\tstruct bio *orig_bio;\n\tlong unsigned int start_time;\n\tsector_t offset;\n\tlong unsigned int sectors;\n\tenum stat_group rw;\n\tstruct bio bio_clone;\n};\n\nstruct md_personality {\n\tstruct md_submodule_head head;\n\tbool (*make_request)(struct mddev *, struct bio *);\n\tint (*run)(struct mddev *);\n\tint (*start)(struct mddev *);\n\tvoid (*free)(struct mddev *, void *);\n\tvoid (*status)(struct seq_file *, struct mddev *);\n\tvoid (*error_handler)(struct mddev *, struct md_rdev *);\n\tint (*hot_add_disk)(struct mddev *, struct md_rdev *);\n\tint (*hot_remove_disk)(struct mddev *, struct md_rdev *);\n\tint (*spare_active)(struct mddev *);\n\tsector_t (*sync_request)(struct mddev *, sector_t, sector_t, int *);\n\tint (*resize)(struct mddev *, sector_t);\n\tsector_t (*size)(struct mddev *, sector_t, int);\n\tint (*check_reshape)(struct mddev *);\n\tint (*start_reshape)(struct mddev *);\n\tvoid (*finish_reshape)(struct mddev *);\n\tvoid (*update_reshape_pos)(struct mddev *);\n\tvoid (*prepare_suspend)(struct mddev *);\n\tvoid (*quiesce)(struct mddev *, int);\n\tvoid * (*takeover)(struct mddev *);\n\tint (*change_consistency_policy)(struct mddev *, const char *);\n\tvoid (*bitmap_sector)(struct mddev *, sector_t *, long unsigned int *);\n};\n\nstruct serial_in_rdev;\n\nstruct md_rdev {\n\tstruct list_head same_set;\n\tsector_t sectors;\n\tstruct mddev *mddev;\n\tlong unsigned int last_events;\n\tstruct block_device *meta_bdev;\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct page *sb_page;\n\tstruct page *bb_page;\n\tint sb_loaded;\n\t__u64 sb_events;\n\tsector_t data_offset;\n\tsector_t new_data_offset;\n\tsector_t sb_start;\n\tint sb_size;\n\tint preferred_minor;\n\tstruct kobject kobj;\n\tlong unsigned int flags;\n\twait_queue_head_t blocked_wait;\n\tint desc_nr;\n\tint raid_disk;\n\tint new_raid_disk;\n\tint saved_raid_disk;\n\tunion {\n\t\tsector_t recovery_offset;\n\t\tsector_t journal_tail;\n\t};\n\tatomic_t nr_pending;\n\tatomic_t read_errors;\n\ttime64_t last_read_error;\n\tatomic_t corrected_errors;\n\tstruct serial_in_rdev *serial;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_unack_badblocks;\n\tstruct kernfs_node *sysfs_badblocks;\n\tstruct badblocks badblocks;\n\tstruct {\n\t\tshort int offset;\n\t\tunsigned int size;\n\t\tsector_t sector;\n\t} ppl;\n};\n\nstruct md_setup_args {\n\tint minor;\n\tint partitioned;\n\tint level;\n\tint chunk;\n\tchar *device_names;\n};\n\nstruct md_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mddev *, char *);\n\tssize_t (*store)(struct mddev *, const char *, size_t);\n};\n\nstruct md_thread {\n\tvoid (*run)(struct md_thread *);\n\tstruct mddev *mddev;\n\twait_queue_head_t wqueue;\n\tlong unsigned int flags;\n\tstruct task_struct *tsk;\n\tlong unsigned int timeout;\n\tvoid *private;\n};\n\nstruct mdb_header {\n\tu16 length;\n\tu16 type;\n\tu32 tag;\n\tu32 revision_code;\n};\n\nstruct mto {\n\tu16 length;\n\tu16 type;\n\tu16 line_type_flags;\n\tu8 alarm_control;\n\tu8 _reserved[3];\n};\n\nstruct mdb {\n\tstruct mdb_header header;\n\tstruct go go;\n\tstruct mto mto;\n} __attribute__((packed));\n\nstruct md_cluster_info;\n\nstruct mddev {\n\tvoid *private;\n\tstruct md_personality *pers;\n\tdev_t unit;\n\tint md_minor;\n\tstruct list_head disks;\n\tlong unsigned int flags;\n\tlong unsigned int sb_flags;\n\tint suspended;\n\tstruct mutex suspend_mutex;\n\tstruct percpu_ref active_io;\n\tint ro;\n\tint sysfs_active;\n\tstruct gendisk *gendisk;\n\tstruct gendisk *dm_gendisk;\n\tstruct kobject kobj;\n\tint hold_active;\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tint persistent;\n\tint external;\n\tchar metadata_type[17];\n\tint chunk_sectors;\n\ttime64_t ctime;\n\ttime64_t utime;\n\tint level;\n\tint layout;\n\tchar clevel[16];\n\tint raid_disks;\n\tint max_disks;\n\tsector_t dev_sectors;\n\tsector_t array_sectors;\n\tint external_size;\n\tunsigned int logical_block_size;\n\t__u64 events;\n\tint can_decrease_events;\n\tchar uuid[16];\n\tsector_t reshape_position;\n\tint delta_disks;\n\tint new_level;\n\tint new_layout;\n\tint new_chunk_sectors;\n\tint reshape_backwards;\n\tstruct md_thread *thread;\n\tstruct md_thread *sync_thread;\n\tenum sync_action last_sync_action;\n\tsector_t curr_resync;\n\tsector_t curr_resync_completed;\n\tlong unsigned int resync_mark;\n\tsector_t resync_mark_cnt;\n\tsector_t curr_mark_cnt;\n\tsector_t resync_max_sectors;\n\tatomic64_t resync_mismatches;\n\tsector_t suspend_lo;\n\tsector_t suspend_hi;\n\tint sync_speed_min;\n\tint sync_speed_max;\n\tint sync_io_depth;\n\tint parallel_resync;\n\tint ok_start_degraded;\n\tlong unsigned int recovery;\n\tint in_sync;\n\tstruct mutex open_mutex;\n\tstruct mutex reconfig_mutex;\n\tatomic_t active;\n\tatomic_t openers;\n\tint changed;\n\tint degraded;\n\tlong unsigned int normal_io_events;\n\tatomic_t recovery_active;\n\twait_queue_head_t recovery_wait;\n\tsector_t resync_offset;\n\tsector_t resync_min;\n\tsector_t resync_max;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_action;\n\tstruct kernfs_node *sysfs_completed;\n\tstruct kernfs_node *sysfs_degraded;\n\tstruct kernfs_node *sysfs_level;\n\tstruct work_struct del_work;\n\tstruct work_struct sync_work;\n\tspinlock_t lock;\n\twait_queue_head_t sb_wait;\n\tatomic_t pending_writes;\n\tunsigned int safemode;\n\tunsigned int safemode_delay;\n\tstruct timer_list safemode_timer;\n\tstruct percpu_ref writes_pending;\n\tint sync_checkers;\n\tenum md_submodule_id bitmap_id;\n\tvoid *bitmap;\n\tstruct bitmap_operations *bitmap_ops;\n\tstruct {\n\t\tstruct file *file;\n\t\tloff_t offset;\n\t\tlong unsigned int space;\n\t\tloff_t default_offset;\n\t\tlong unsigned int default_space;\n\t\tstruct mutex mutex;\n\t\tlong unsigned int chunksize;\n\t\tlong unsigned int daemon_sleep;\n\t\tlong unsigned int max_write_behind;\n\t\tint external;\n\t\tint nodes;\n\t\tchar cluster_name[64];\n\t} bitmap_info;\n\tatomic_t max_corr_read_errors;\n\tstruct list_head all_mddevs;\n\tconst struct attribute_group *to_remove;\n\tstruct bio_set bio_set;\n\tstruct bio_set sync_set;\n\tstruct bio_set io_clone_set;\n\tstruct work_struct event_work;\n\tmempool_t *serial_info_pool;\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tstruct md_cluster_info *cluster_info;\n\tstruct md_cluster_operations *cluster_ops;\n\tunsigned int good_device_nr;\n\tunsigned int noio_flag;\n\tstruct list_head deleting;\n\tatomic_t sync_seq;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gpio_desc;\n\nstruct reset_control;\n\nstruct mii_bus;\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdp_device_descriptor_s {\n\t__u32 number;\n\t__u32 major;\n\t__u32 minor;\n\t__u32 raid_disk;\n\t__u32 state;\n\t__u32 reserved[27];\n};\n\ntypedef struct mdp_device_descriptor_s mdp_disk_t;\n\nstruct mdp_superblock_1 {\n\t__le32 magic;\n\t__le32 major_version;\n\t__le32 feature_map;\n\t__le32 pad0;\n\t__u8 set_uuid[16];\n\tchar set_name[32];\n\t__le64 ctime;\n\t__le32 level;\n\t__le32 layout;\n\t__le64 size;\n\t__le32 chunksize;\n\t__le32 raid_disks;\n\tunion {\n\t\t__le32 bitmap_offset;\n\t\tstruct {\n\t\t\t__le16 offset;\n\t\t\t__le16 size;\n\t\t} ppl;\n\t};\n\t__le32 new_level;\n\t__le64 reshape_position;\n\t__le32 delta_disks;\n\t__le32 new_layout;\n\t__le32 new_chunk;\n\t__le32 new_offset;\n\t__le64 data_offset;\n\t__le64 data_size;\n\t__le64 super_offset;\n\tunion {\n\t\t__le64 recovery_offset;\n\t\t__le64 journal_tail;\n\t};\n\t__le32 dev_number;\n\t__le32 cnt_corrected_read;\n\t__u8 device_uuid[16];\n\t__u8 devflags;\n\t__u8 bblog_shift;\n\t__le16 bblog_size;\n\t__le32 bblog_offset;\n\t__le64 utime;\n\t__le64 events;\n\t__le64 resync_offset;\n\t__le32 sb_csum;\n\t__le32 max_dev;\n\t__le32 logical_block_size;\n\t__u8 pad3[28];\n\t__le16 dev_roles[0];\n};\n\nstruct mdp_superblock_s {\n\t__u32 md_magic;\n\t__u32 major_version;\n\t__u32 minor_version;\n\t__u32 patch_version;\n\t__u32 gvalid_words;\n\t__u32 set_uuid0;\n\t__u32 ctime;\n\t__u32 level;\n\t__u32 size;\n\t__u32 nr_disks;\n\t__u32 raid_disks;\n\t__u32 md_minor;\n\t__u32 not_persistent;\n\t__u32 set_uuid1;\n\t__u32 set_uuid2;\n\t__u32 set_uuid3;\n\t__u32 gstate_creserved[16];\n\t__u32 utime;\n\t__u32 state;\n\t__u32 active_disks;\n\t__u32 working_disks;\n\t__u32 failed_disks;\n\t__u32 spare_disks;\n\t__u32 sb_csum;\n\t__u32 events_hi;\n\t__u32 events_lo;\n\t__u32 cp_events_hi;\n\t__u32 cp_events_lo;\n\t__u32 recovery_cp;\n\t__u64 reshape_position;\n\t__u32 new_level;\n\t__u32 delta_disks;\n\t__u32 new_layout;\n\t__u32 new_chunk;\n\t__u32 gstate_sreserved[14];\n\t__u32 layout;\n\t__u32 chunk_size;\n\t__u32 root_pv;\n\t__u32 root_block;\n\t__u32 pstate_reserved[60];\n\tmdp_disk_t disks[27];\n\t__u32 reserved[0];\n\tmdp_disk_t this_disk;\n};\n\ntypedef struct mdp_superblock_s mdp_super_t;\n\nstruct mdu_array_info_s {\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tunsigned int ctime;\n\tint level;\n\tint size;\n\tint nr_disks;\n\tint raid_disks;\n\tint md_minor;\n\tint not_persistent;\n\tunsigned int utime;\n\tint state;\n\tint active_disks;\n\tint working_disks;\n\tint failed_disks;\n\tint spare_disks;\n\tint layout;\n\tint chunk_size;\n};\n\ntypedef struct mdu_array_info_s mdu_array_info_t;\n\nstruct mdu_bitmap_file_s {\n\tchar pathname[4096];\n};\n\ntypedef struct mdu_bitmap_file_s mdu_bitmap_file_t;\n\nstruct mdu_disk_info_s {\n\tint number;\n\tint major;\n\tint minor;\n\tint raid_disk;\n\tint state;\n};\n\ntypedef struct mdu_disk_info_s mdu_disk_info_t;\n\nstruct mdu_version_s {\n\tint major;\n\tint minor;\n\tint patchlevel;\n};\n\ntypedef struct mdu_version_s mdu_version_t;\n\nstruct mem_cgroup_private_id {\n\tint id;\n\trefcount_t ref;\n};\n\nstruct vmpressure {\n\tlong unsigned int scanned;\n\tlong unsigned int reclaimed;\n\tlong unsigned int tree_scanned;\n\tlong unsigned int tree_reclaimed;\n\tspinlock_t sr_lock;\n\tstruct list_head events;\n\tstruct mutex events_lock;\n\tstruct work_struct work;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct memcg_cgwb_frn {\n\tu64 bdi_id;\n\tint memcg_id;\n\tu64 at;\n\tstruct wb_completion done;\n};\n\nstruct memcg_vmstats;\n\nstruct memcg_vmstats_percpu;\n\nstruct mem_cgroup_per_node;\n\nstruct mem_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct mem_cgroup_private_id id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter memory;\n\tunion {\n\t\tstruct page_counter swap;\n\t\tstruct page_counter memsw;\n\t};\n\tstruct list_head memory_peaks;\n\tstruct list_head swap_peaks;\n\tspinlock_t peaks_lock;\n\tstruct work_struct high_work;\n\tlong unsigned int zswap_max;\n\tbool zswap_writeback;\n\tstruct vmpressure vmpressure;\n\tbool oom_group;\n\tint swappiness;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct cgroup_file swap_events_file;\n\tstruct memcg_vmstats *vmstats;\n\tatomic_long_t memory_events[10];\n\tatomic_long_t memory_events_local[10];\n\tu64 socket_pressure;\n\tint kmemcg_id;\n\tstruct obj_cgroup *objcg;\n\tstruct obj_cgroup *orig_objcg;\n\tstruct list_head objcg_list;\n\tstruct memcg_vmstats_percpu *vmstats_percpu;\n\tstruct list_head cgwb_list;\n\tstruct wb_domain cgwb_domain;\n\tstruct memcg_cgwb_frn cgwb_frn[4];\n\tstruct deferred_split deferred_split_queue;\n\tstruct mem_cgroup_per_node *nodeinfo[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mem_cgroup_reclaim_iter {\n\tstruct mem_cgroup *position;\n\tatomic_t generation;\n};\n\nstruct shrinker_info;\n\nstruct mem_cgroup_per_node {\n\tstruct mem_cgroup *memcg;\n\tstruct lruvec_stats_percpu *lruvec_stats_percpu;\n\tstruct lruvec_stats *lruvec_stats;\n\tstruct shrinker_info *shrinker_info;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct lruvec lruvec;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int lru_zone_size[20];\n\tstruct mem_cgroup_reclaim_iter iter;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n};\n\nstruct mem_section_usage;\n\nstruct mem_section {\n\tlong unsigned int section_mem_map;\n\tstruct mem_section_usage *usage;\n};\n\nstruct mem_section_usage {\n\tstruct callback_head rcu;\n\tlong unsigned int subsection_map[1];\n\tlong unsigned int pageblock_flags[0];\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n\tint nid;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memcg_stock_pcp {\n\tlocal_trylock_t lock;\n\tuint8_t nr_pages[7];\n\tstruct mem_cgroup *cached[7];\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct memcg_vmstats {\n\tlong int state[40];\n\tlong unsigned int events[29];\n\tlong int state_local[40];\n\tlong unsigned int events_local[29];\n\tlong int state_pending[40];\n\tlong unsigned int events_pending[29];\n\tatomic_t stats_updates;\n};\n\nstruct memcg_vmstats_percpu {\n\tunsigned int stats_updates;\n\tstruct memcg_vmstats_percpu *parent_pcpu;\n\tstruct memcg_vmstats *vmstats;\n\tlong int state[40];\n\tlong unsigned int events[29];\n\tlong int state_prev[40];\n\tlong unsigned int events_prev[29];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct memory_group;\n\nstruct memory_block {\n\tlong unsigned int start_section_nr;\n\tenum memory_block_state state;\n\tint online_type;\n\tint nid;\n\tstruct zone *zone;\n\tstruct device dev;\n\tstruct vmem_altmap *altmap;\n\tstruct memory_group *group;\n\tstruct list_head group_next;\n};\n\nstruct memory_dev_type {\n\tstruct list_head tier_sibling;\n\tstruct list_head list;\n\tint adistance;\n\tnodemask_t nodes;\n\tstruct kref kref;\n};\n\nstruct memory_group {\n\tint nid;\n\tstruct list_head memory_blocks;\n\tlong unsigned int present_kernel_pages;\n\tlong unsigned int present_movable_pages;\n\tbool is_dynamic;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int max_pages;\n\t\t} s;\n\t\tstruct {\n\t\t\tlong unsigned int unit_pages;\n\t\t} d;\n\t};\n};\n\nstruct memory_increment {\n\tstruct list_head list;\n\tu16 rn;\n\tint standby;\n};\n\nstruct memory_notify {\n\tlong unsigned int start_pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct memory_stat {\n\tconst char *name;\n\tunsigned int idx;\n};\n\nstruct memory_tier {\n\tstruct list_head list;\n\tstruct list_head memory_types;\n\tint adistance_start;\n\tstruct device dev;\n\tnodemask_t lower_tier_mask;\n};\n\nstruct mempolicy {\n\tatomic_t refcnt;\n\tshort unsigned int mode;\n\tshort unsigned int flags;\n\tnodemask_t nodes;\n\tint home_node;\n\tunion {\n\t\tnodemask_t cpuset_mems_allowed;\n\t\tnodemask_t user_nodemask;\n\t} w;\n};\n\nstruct mempolicy_operations {\n\tint (*create)(struct mempolicy *, const nodemask_t *);\n\tvoid (*rebind)(struct mempolicy *, const nodemask_t *);\n};\n\nstruct merge_sched_data {\n\tint can_add_hw;\n\tenum event_type_t event_type;\n};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mext_data {\n\tstruct inode *orig_inode;\n\tstruct inode *donor_inode;\n\tstruct ext4_map_blocks orig_map;\n\text4_lblk_t donor_lblk;\n};\n\nstruct mr_mfc {\n\tstruct rhlist_head mnode;\n\tshort unsigned int mfc_parent;\n\tint mfc_flags;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int expires;\n\t\t\tstruct sk_buff_head unresolved;\n\t\t} unres;\n\t\tstruct {\n\t\t\tlong unsigned int last_assert;\n\t\t\tint minvif;\n\t\t\tint maxvif;\n\t\t\tatomic_long_t bytes;\n\t\t\tatomic_long_t pkt;\n\t\t\tatomic_long_t wrong_if;\n\t\t\tlong unsigned int lastuse;\n\t\t\tunsigned char ttls[32];\n\t\t\trefcount_t refcount;\n\t\t} res;\n\t} mfc_un;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tvoid (*free)(struct callback_head *);\n};\n\nstruct mfc_cache_cmp_arg {\n\t__be32 mfc_mcastgrp;\n\t__be32 mfc_origin;\n};\n\nstruct mfc_cache {\n\tstruct mr_mfc _c;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 mfc_mcastgrp;\n\t\t\t__be32 mfc_origin;\n\t\t};\n\t\tstruct mfc_cache_cmp_arg cmparg;\n\t};\n};\n\nstruct mfc_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct mr_mfc *mfc;\n\tu32 tb_id;\n};\n\nstruct mfcctl {\n\tstruct in_addr mfcc_origin;\n\tstruct in_addr mfcc_mcastgrp;\n\tvifi_t mfcc_parent;\n\tunsigned char mfcc_ttls[32];\n\tunsigned int mfcc_pkt_cnt;\n\tunsigned int mfcc_byte_cnt;\n\tunsigned int mfcc_wrong_if;\n\tint mfcc_expire;\n};\n\nstruct mhp_params {\n\tstruct vmem_altmap *altmap;\n\tpgprot_t pgprot;\n\tstruct dev_pagemap *pgmap;\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct migrate_vma {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int *dst;\n\tlong unsigned int *src;\n\tlong unsigned int cpages;\n\tlong unsigned int npages;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvoid *pgmap_owner;\n\tlong unsigned int flags;\n\tstruct page *fault_page;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_mpol {\n\tstruct mempolicy *pol;\n\tlong unsigned int ilx;\n};\n\nstruct migration_swap_arg {\n\tstruct task_struct *src_task;\n\tstruct task_struct *dst_task;\n\tint src_cpu;\n\tint dst_cpu;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct min_heap_callbacks {\n\tbool (*less)(const void *, const void *, void *);\n\tvoid (*swp)(void *, void *, void *);\n};\n\nstruct min_heap_char {\n\tsize_t nr;\n\tsize_t size;\n\tchar *data;\n\tchar preallocated[0];\n};\n\ntypedef struct min_heap_char min_heap_char;\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minix_super_block {\n\t__u16 s_ninodes;\n\t__u16 s_nzones;\n\t__u16 s_imap_blocks;\n\t__u16 s_zmap_blocks;\n\t__u16 s_firstdatazone;\n\t__u16 s_log_zone_size;\n\t__u32 s_max_size;\n\t__u16 s_magic;\n\t__u16 s_state;\n\t__u32 s_zones;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct misc_res {\n\tu64 max;\n\tatomic64_t watermark;\n\tatomic64_t usage;\n\tatomic64_t events;\n\tatomic64_t events_local;\n};\n\nstruct misc_cg {\n\tstruct cgroup_subsys_state css;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct misc_res res[0];\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct mld2_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\tstruct in6_addr grec_mca;\n\tstruct in6_addr grec_src[0];\n};\n\nstruct mld2_query {\n\tstruct icmp6hdr mld2q_hdr;\n\tstruct in6_addr mld2q_mca;\n\t__u8 mld2q_resv2: 4;\n\t__u8 mld2q_suppress: 1;\n\t__u8 mld2q_qrv: 3;\n\t__u8 mld2q_qqic;\n\t__be16 mld2q_nsrcs;\n\tstruct in6_addr mld2q_srcs[0];\n};\n\nstruct mld2_report {\n\tstruct icmp6hdr mld2r_hdr;\n\tstruct mld2_grec mld2r_grec[0];\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tstruct ethtool_mm_stats stats;\n};\n\ntypedef struct mm_struct *class_mmap_read_lock_t;\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n};\n\nstruct mmu_notifier_subscriptions;\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct rcuwait vma_writer_wait;\n\t\tseqcount_t mm_lock_seq;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[48];\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct task_struct *owner;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tstruct mmu_notifier_subscriptions *notifier_subscriptions;\n\t\tlong unsigned int numa_next_scan;\n\t\tlong unsigned int numa_scan_offset;\n\t\tint numa_scan_seq;\n\t\tatomic_t tlb_flush_pending;\n\t\tstruct uprobes_state uprobes_state;\n\t\tatomic_long_t hugetlb_usage;\n\t\tstruct work_struct async_put_work;\n\t\tlong unsigned int ksm_merging_pages;\n\t\tlong unsigned int ksm_rmap_items;\n\t\tatomic_long_t ksm_zero_pages;\n\t\tmm_id_t mm_id;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n\tstruct task_struct *owner;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct mmap_arg_struct {\n\tlong unsigned int addr;\n\tlong unsigned int len;\n\tlong unsigned int prot;\n\tlong unsigned int flags;\n\tlong unsigned int fd;\n\tlong unsigned int offset;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mminit_pfnnid_cache {\n\tlong unsigned int last_start;\n\tlong unsigned int last_end;\n\tint last_nid;\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct mmu_table_batch;\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tstruct mmu_table_batch *batch;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n};\n\nstruct mmu_interval_notifier_ops;\n\nstruct mmu_interval_notifier {\n\tstruct interval_tree_node interval_tree;\n\tconst struct mmu_interval_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct hlist_node deferred_item;\n\tlong unsigned int invalidate_seq;\n};\n\nstruct mmu_notifier_range;\n\nstruct mmu_interval_notifier_ops {\n\tbool (*invalidate)(struct mmu_interval_notifier *, const struct mmu_notifier_range *, long unsigned int);\n};\n\nstruct mmu_notifier_ops {\n\tvoid (*release)(struct mmu_notifier *, struct mm_struct *);\n\tint (*clear_flush_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*clear_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*test_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int);\n\tint (*invalidate_range_start)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range_end)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*arch_invalidate_secondary_tlbs)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tstruct mmu_notifier * (*alloc_notifier)(struct mm_struct *);\n\tvoid (*free_notifier)(struct mmu_notifier *);\n};\n\nstruct mmu_notifier_range {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int flags;\n\tenum mmu_notifier_event event;\n\tvoid *owner;\n};\n\nstruct mmu_notifier_subscriptions {\n\tstruct hlist_head list;\n\tbool has_itree;\n\tspinlock_t lock;\n\tlong unsigned int invalidate_seq;\n\tlong unsigned int active_invalidate_ranges;\n\tstruct rb_root_cached itree;\n\twait_queue_head_t wq;\n\tstruct hlist_head deferred_list;\n};\n\nstruct mmu_table_batch {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tvoid *tables[0];\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct mod_arch_syminfo;\n\nstruct mod_arch_specific {\n\tlong unsigned int got_offset;\n\tlong unsigned int plt_offset;\n\tlong unsigned int got_size;\n\tlong unsigned int plt_size;\n\tint nsyms;\n\tstruct mod_arch_syminfo *syminfo;\n\tstruct ftrace_hotpatch_trampoline *trampolines_start;\n\tstruct ftrace_hotpatch_trampoline *trampolines_end;\n\tstruct ftrace_hotpatch_trampoline *next_trampoline;\n};\n\nstruct mod_arch_syminfo {\n\tlong unsigned int got_offset;\n\tlong unsigned int plt_offset;\n\tint got_initialized;\n\tint plt_initialized;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf64_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct mod_unload_taint {\n\tstruct list_head list;\n\tchar name[56];\n\tlong unsigned int taints;\n\tu64 count;\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n\tstruct mod_tree_node mtn;\n};\n\ntypedef struct tracepoint * const tracepoint_ptr_t;\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_event_call;\n\nstruct trace_eval_map;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[56];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool sig_ok;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tunsigned int num_ftrace_callsites;\n\tlong unsigned int *ftrace_callsites;\n\tvoid *kprobes_text_start;\n\tunsigned int kprobes_text_size;\n\tlong unsigned int *kprobe_blacklist;\n\tunsigned int num_kprobe_blacklist;\n\tint num_kunit_init_suites;\n\tstruct kunit_suite **kunit_init_suites;\n\tint num_kunit_suites;\n\tstruct kunit_suite **kunit_suites;\n\tbool klp;\n\tbool klp_alive;\n\tstruct klp_modinfo *klp_info;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n\tstruct _ddebug_info dyndbg_info;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_signature {\n\tu8 algo;\n\tu8 hash;\n\tu8 id_type;\n\tu8 signer_len;\n\tu8 key_id_len;\n\tu8 __pad[3];\n\t__be32 sig_len;\n};\n\nstruct module_string {\n\tstruct list_head next;\n\tstruct module *module;\n\tchar *str;\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct modules_array {\n\tstruct module **mods;\n\tint mods_cnt;\n\tint mods_cap;\n};\n\nstruct modversion_info {\n\tlong unsigned int crc;\n\tchar name[56];\n};\n\nstruct modversion_info_ext {\n\tsize_t remaining;\n\tconst u32 *crc;\n\tconst char *name;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tunsigned int can_map: 1;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tloff_t end_pos;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n\tunsigned int journalled_more_data: 1;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mptcp_addr_info {\n\tu8 id;\n\tsa_family_t family;\n\t__be16 port;\n\tunion {\n\t\tstruct in_addr addr;\n\t\tstruct in6_addr addr6;\n\t};\n};\n\nstruct mptcp_rm_list {\n\tu8 ids[8];\n\tu8 nr;\n};\n\nstruct mptcp_pm_data {\n\tstruct mptcp_addr_info local;\n\tstruct mptcp_addr_info remote;\n\tstruct list_head anno_list;\n\tstruct list_head userspace_pm_local_addr_list;\n\tspinlock_t lock;\n\tunion {\n\t\tstruct {\n\t\t\tu8 addr_signal;\n\t\t\tbool server_side;\n\t\t\tbool work_pending;\n\t\t\tbool accept_addr;\n\t\t\tbool accept_subflow;\n\t\t\tbool remote_deny_join_id0;\n\t\t\tu8 add_addr_signaled;\n\t\t\tu8 add_addr_accepted;\n\t\t\tu8 local_addr_used;\n\t\t\tu8 pm_type;\n\t\t\tu8 extra_subflows;\n\t\t\tu8 status;\n\t\t};\n\t\tstruct {\n\t\t\tu8 addr_signal;\n\t\t\tbool server_side;\n\t\t\tbool work_pending;\n\t\t\tbool accept_addr;\n\t\t\tbool accept_subflow;\n\t\t\tbool remote_deny_join_id0;\n\t\t\tu8 add_addr_signaled;\n\t\t\tu8 add_addr_accepted;\n\t\t\tu8 local_addr_used;\n\t\t\tu8 pm_type;\n\t\t\tu8 extra_subflows;\n\t\t\tu8 status;\n\t\t} reset;\n\t};\n\tlong unsigned int id_avail_bitmap[4];\n\tstruct mptcp_rm_list rm_list_tx;\n\tstruct mptcp_rm_list rm_list_rx;\n};\n\nstruct mptcp_data_frag;\n\nstruct mptcp_sched_ops;\n\nstruct mptcp_sock {\n\tstruct inet_connection_sock sk;\n\tu64 local_key;\n\tu64 remote_key;\n\tu64 write_seq;\n\tu64 bytes_sent;\n\tu64 snd_nxt;\n\tu64 bytes_received;\n\tu64 ack_seq;\n\tatomic64_t rcv_wnd_sent;\n\tu64 rcv_data_fin_seq;\n\tu64 bytes_retrans;\n\tu64 bytes_consumed;\n\tint snd_burst;\n\tint old_wspace;\n\tu64 recovery_snd_nxt;\n\tu64 bytes_acked;\n\tu64 snd_una;\n\tu64 wnd_end;\n\tu32 last_data_sent;\n\tu32 last_data_recv;\n\tu32 last_ack_recv;\n\tlong unsigned int timer_ival;\n\tu32 token;\n\tlong unsigned int flags;\n\tlong unsigned int cb_flags;\n\tbool recovery;\n\tbool can_ack;\n\tbool fully_established;\n\tbool rcv_data_fin;\n\tbool snd_data_fin_enable;\n\tbool rcv_fastclose;\n\tbool use_64bit_ack;\n\tbool csum_enabled;\n\tbool allow_infinite_fallback;\n\tu8 pending_state;\n\tu8 mpc_endpoint_id;\n\tu8 recvmsg_inq: 1;\n\tu8 cork: 1;\n\tu8 nodelay: 1;\n\tu8 fastopening: 1;\n\tu8 in_accept_queue: 1;\n\tu8 free_first: 1;\n\tu8 rcvspace_init: 1;\n\tu8 fastclosing: 1;\n\tu32 notsent_lowat;\n\tint keepalive_cnt;\n\tint keepalive_idle;\n\tint keepalive_intvl;\n\tint maxseg;\n\tstruct work_struct work;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct rb_root out_of_order_queue;\n\tstruct list_head conn_list;\n\tstruct list_head rtx_queue;\n\tstruct mptcp_data_frag *first_pending;\n\tstruct list_head join_list;\n\tstruct sock *first;\n\tstruct mptcp_pm_data pm;\n\tstruct mptcp_sched_ops *sched;\n\tstruct {\n\t\tint space;\n\t\tint copied;\n\t\tu64 time;\n\t\tu64 rtt_us;\n\t} rcvq_space;\n\tu8 scaling_ratio;\n\tbool allow_subflows;\n\tu32 subflow_id;\n\tu32 setsockopt_seq;\n\tchar ca_name[16];\n\tspinlock_t fallback_lock;\n\tstruct list_head backlog_list;\n\tu32 backlog_len;\n\tu32 backlog_unaccounted;\n};\n\nstruct mptcp6_sock {\n\tstruct mptcp_sock msk;\n\tstruct ipv6_pinfo np;\n};\n\nstruct mptcp_data_frag {\n\tstruct list_head list;\n\tu64 data_seq;\n\tu16 data_len;\n\tu16 offset;\n\tu16 overhead;\n\tu16 already_sent;\n\tstruct page *page;\n};\n\nstruct mptcp_delegated_action {\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n\tstruct list_head head;\n};\n\nstruct mptcp_ext {\n\tunion {\n\t\tu64 data_ack;\n\t\tu32 data_ack32;\n\t};\n\tu64 data_seq;\n\tu32 subflow_seq;\n\tu16 data_len;\n\t__sum16 csum;\n\tu8 use_map: 1;\n\tu8 dsn64: 1;\n\tu8 data_fin: 1;\n\tu8 use_ack: 1;\n\tu8 ack64: 1;\n\tu8 mpc_map: 1;\n\tu8 frozen: 1;\n\tu8 reset_transient: 1;\n\tu8 reset_reason: 4;\n\tu8 csum_reqd: 1;\n\tu8 infinite_map: 1;\n};\n\nstruct mptcp_info {\n\t__u8 mptcpi_subflows;\n\t__u8 mptcpi_add_addr_signal;\n\t__u8 mptcpi_add_addr_accepted;\n\t__u8 mptcpi_subflows_max;\n\t__u8 mptcpi_add_addr_signal_max;\n\t__u8 mptcpi_add_addr_accepted_max;\n\t__u32 mptcpi_flags;\n\t__u32 mptcpi_token;\n\t__u64 mptcpi_write_seq;\n\t__u64 mptcpi_snd_una;\n\t__u64 mptcpi_rcv_nxt;\n\t__u8 mptcpi_local_addr_used;\n\t__u8 mptcpi_local_addr_max;\n\t__u8 mptcpi_csum_enabled;\n\t__u32 mptcpi_retransmits;\n\t__u64 mptcpi_bytes_retrans;\n\t__u64 mptcpi_bytes_sent;\n\t__u64 mptcpi_bytes_received;\n\t__u64 mptcpi_bytes_acked;\n\t__u8 mptcpi_subflows_total;\n\t__u8 mptcpi_endp_laminar_max;\n\t__u8 mptcpi_endp_fullmesh_max;\n\t__u8 reserved;\n\t__u32 mptcpi_last_data_sent;\n\t__u32 mptcpi_last_data_recv;\n\t__u32 mptcpi_last_ack_recv;\n};\n\nstruct mptcp_full_info {\n\t__u32 size_tcpinfo_kernel;\n\t__u32 size_tcpinfo_user;\n\t__u32 size_sfinfo_kernel;\n\t__u32 size_sfinfo_user;\n\t__u32 num_subflows;\n\t__u32 size_arrays_user;\n\t__u64 subflow_info;\n\t__u64 tcp_info;\n\tstruct mptcp_info mptcp_info;\n};\n\nstruct mptcp_mib {\n\tlong unsigned int mibs[77];\n};\n\nstruct mptcp_options_received {\n\tu64 sndr_key;\n\tu64 rcvr_key;\n\tu64 data_ack;\n\tu64 data_seq;\n\tu32 subflow_seq;\n\tu16 data_len;\n\t__sum16 csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 suboptions;\n\t\t\tu16 use_map: 1;\n\t\t\tu16 dsn64: 1;\n\t\t\tu16 data_fin: 1;\n\t\t\tu16 use_ack: 1;\n\t\t\tu16 ack64: 1;\n\t\t\tu16 mpc_map: 1;\n\t\t\tu16 reset_reason: 4;\n\t\t\tu16 reset_transient: 1;\n\t\t\tu16 echo: 1;\n\t\t\tu16 backup: 1;\n\t\t\tu16 deny_join_id0: 1;\n\t\t\tu16 __unused: 2;\n\t\t};\n\t\tstruct {\n\t\t\tu16 suboptions;\n\t\t\tu16 use_map: 1;\n\t\t\tu16 dsn64: 1;\n\t\t\tu16 data_fin: 1;\n\t\t\tu16 use_ack: 1;\n\t\t\tu16 ack64: 1;\n\t\t\tu16 mpc_map: 1;\n\t\t\tu16 reset_reason: 4;\n\t\t\tu16 reset_transient: 1;\n\t\t\tu16 echo: 1;\n\t\t\tu16 backup: 1;\n\t\t\tu16 deny_join_id0: 1;\n\t\t\tu16 __unused: 2;\n\t\t} status;\n\t};\n\tu8 join_id;\n\tu32 token;\n\tu32 nonce;\n\tu64 thmac;\n\tu8 hmac[20];\n\tstruct mptcp_addr_info addr;\n\tstruct mptcp_rm_list rm_list;\n\tu64 ahmac;\n\tu64 fail_seq;\n};\n\nstruct mptcp_out_options {\n\tu16 suboptions;\n\tstruct mptcp_rm_list rm_list;\n\tu8 join_id;\n\tu8 backup;\n\tu8 reset_reason: 4;\n\tu8 reset_transient: 1;\n\tu8 csum_reqd: 1;\n\tu8 allow_join_id0: 1;\n\tunion {\n\t\tstruct {\n\t\t\tu64 sndr_key;\n\t\t\tu64 rcvr_key;\n\t\t\tu64 data_seq;\n\t\t\tu32 subflow_seq;\n\t\t\tu16 data_len;\n\t\t\t__sum16 csum;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mptcp_addr_info addr;\n\t\t\tu64 ahmac;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mptcp_ext ext_copy;\n\t\t\tu64 fail_seq;\n\t\t};\n\t\tstruct {\n\t\t\tu32 nonce;\n\t\t\tu32 token;\n\t\t\tu64 thmac;\n\t\t\tu8 hmac[20];\n\t\t};\n\t};\n};\n\nstruct mptcp_pernet {\n\tstruct ctl_table_header *ctl_table_hdr;\n\tunsigned int add_addr_timeout;\n\tunsigned int blackhole_timeout;\n\tunsigned int close_timeout;\n\tunsigned int stale_loss_cnt;\n\tatomic_t active_disable_times;\n\tu8 syn_retrans_before_tcp_fallback;\n\tlong unsigned int active_disable_stamp;\n\tu8 mptcp_enabled;\n\tu8 checksum_enabled;\n\tu8 allow_join_initial_addr_port;\n\tu8 pm_type;\n\tchar scheduler[16];\n\tchar path_manager[16];\n};\n\nstruct mptcp_pm_add_entry {\n\tstruct list_head list;\n\tstruct mptcp_addr_info addr;\n\tu8 retrans_times;\n\tstruct timer_list add_timer;\n\tstruct mptcp_sock *sock;\n\tstruct callback_head rcu;\n};\n\nstruct mptcp_pm_addr_entry {\n\tstruct list_head list;\n\tstruct mptcp_addr_info addr;\n\tu32 flags;\n\tint ifindex;\n\tstruct socket *lsk;\n};\n\nstruct mptcp_pm_local {\n\tstruct mptcp_addr_info addr;\n\tu32 flags;\n\tint ifindex;\n};\n\nstruct mptcp_pm_ops {\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tvoid (*init)(struct mptcp_sock *);\n\tvoid (*release)(struct mptcp_sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mptcp_sched_ops {\n\tint (*get_send)(struct mptcp_sock *);\n\tint (*get_retrans)(struct mptcp_sock *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tvoid (*init)(struct mptcp_sock *);\n\tvoid (*release)(struct mptcp_sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mptcp_sendmsg_info {\n\tint mss_now;\n\tint size_goal;\n\tu16 limit;\n\tu16 sent;\n\tunsigned int flags;\n\tbool data_lock_held;\n};\n\nstruct mptcp_skb_cb {\n\tu64 map_seq;\n\tu64 end_seq;\n\tu32 offset;\n\tu8 has_rxtstamp;\n\tu8 cant_coalesce;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct mptcp_subflow_addrs {\n\tunion {\n\t\t__kernel_sa_family_t sa_family;\n\t\tstruct sockaddr sa_local;\n\t\tstruct sockaddr_in sin_local;\n\t\tstruct sockaddr_in6 sin6_local;\n\t\tstruct __kernel_sockaddr_storage ss_local;\n\t};\n\tunion {\n\t\tstruct sockaddr sa_remote;\n\t\tstruct sockaddr_in sin_remote;\n\t\tstruct sockaddr_in6 sin6_remote;\n\t\tstruct __kernel_sockaddr_storage ss_remote;\n\t};\n};\n\nstruct mptcp_subflow_context {\n\tstruct list_head node;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int avg_pacing_rate;\n\t\t\tu64 local_key;\n\t\t\tu64 remote_key;\n\t\t\tu64 idsn;\n\t\t\tu64 map_seq;\n\t\t\tu64 rcv_wnd_sent;\n\t\t\tu32 snd_isn;\n\t\t\tu32 token;\n\t\t\tu32 rel_write_seq;\n\t\t\tu32 map_subflow_seq;\n\t\t\tu32 ssn_offset;\n\t\t\tu32 map_data_len;\n\t\t\t__wsum map_data_csum;\n\t\t\tu32 map_csum_len;\n\t\t\tu32 request_mptcp: 1;\n\t\t\tu32 request_join: 1;\n\t\t\tu32 request_bkup: 1;\n\t\t\tu32 mp_capable: 1;\n\t\t\tu32 mp_join: 1;\n\t\t\tu32 pm_notified: 1;\n\t\t\tu32 conn_finished: 1;\n\t\t\tu32 map_valid: 1;\n\t\t\tu32 map_csum_reqd: 1;\n\t\t\tu32 map_data_fin: 1;\n\t\t\tu32 mpc_map: 1;\n\t\t\tu32 backup: 1;\n\t\t\tu32 send_mp_prio: 1;\n\t\t\tu32 send_mp_fail: 1;\n\t\t\tu32 send_fastclose: 1;\n\t\t\tu32 send_infinite_map: 1;\n\t\t\tu32 remote_key_valid: 1;\n\t\t\tu32 disposable: 1;\n\t\t\tu32 closing: 1;\n\t\t\tu32 stale: 1;\n\t\t\tu32 valid_csum_seen: 1;\n\t\t\tu32 is_mptfo: 1;\n\t\t\tu32 close_event_done: 1;\n\t\t\tu32 mpc_drop: 1;\n\t\t\tu32 __unused: 8;\n\t\t\tbool data_avail;\n\t\t\tbool scheduled;\n\t\t\tbool pm_listener;\n\t\t\tbool fully_established;\n\t\t\tu32 lent_mem_frag;\n\t\t\tu32 remote_nonce;\n\t\t\tu64 thmac;\n\t\t\tu32 local_nonce;\n\t\t\tu32 remote_token;\n\t\t\tunion {\n\t\t\t\tu8 hmac[20];\n\t\t\t\tu64 iasn;\n\t\t\t};\n\t\t\ts16 local_id;\n\t\t\tu8 remote_id;\n\t\t\tu8 reset_seen: 1;\n\t\t\tu8 reset_transient: 1;\n\t\t\tu8 reset_reason: 4;\n\t\t\tu8 stale_count;\n\t\t\tu32 subflow_id;\n\t\t\tlong int delegated_status;\n\t\t\tlong unsigned int fail_tout;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int avg_pacing_rate;\n\t\t\tu64 local_key;\n\t\t\tu64 remote_key;\n\t\t\tu64 idsn;\n\t\t\tu64 map_seq;\n\t\t\tu64 rcv_wnd_sent;\n\t\t\tu32 snd_isn;\n\t\t\tu32 token;\n\t\t\tu32 rel_write_seq;\n\t\t\tu32 map_subflow_seq;\n\t\t\tu32 ssn_offset;\n\t\t\tu32 map_data_len;\n\t\t\t__wsum map_data_csum;\n\t\t\tu32 map_csum_len;\n\t\t\tu32 request_mptcp: 1;\n\t\t\tu32 request_join: 1;\n\t\t\tu32 request_bkup: 1;\n\t\t\tu32 mp_capable: 1;\n\t\t\tu32 mp_join: 1;\n\t\t\tu32 pm_notified: 1;\n\t\t\tu32 conn_finished: 1;\n\t\t\tu32 map_valid: 1;\n\t\t\tu32 map_csum_reqd: 1;\n\t\t\tu32 map_data_fin: 1;\n\t\t\tu32 mpc_map: 1;\n\t\t\tu32 backup: 1;\n\t\t\tu32 send_mp_prio: 1;\n\t\t\tu32 send_mp_fail: 1;\n\t\t\tu32 send_fastclose: 1;\n\t\t\tu32 send_infinite_map: 1;\n\t\t\tu32 remote_key_valid: 1;\n\t\t\tu32 disposable: 1;\n\t\t\tu32 closing: 1;\n\t\t\tu32 stale: 1;\n\t\t\tu32 valid_csum_seen: 1;\n\t\t\tu32 is_mptfo: 1;\n\t\t\tu32 close_event_done: 1;\n\t\t\tu32 mpc_drop: 1;\n\t\t\tu32 __unused: 8;\n\t\t\tbool data_avail;\n\t\t\tbool scheduled;\n\t\t\tbool pm_listener;\n\t\t\tbool fully_established;\n\t\t\tu32 lent_mem_frag;\n\t\t\tu32 remote_nonce;\n\t\t\tu64 thmac;\n\t\t\tu32 local_nonce;\n\t\t\tu32 remote_token;\n\t\t\tunion {\n\t\t\t\tu8 hmac[20];\n\t\t\t\tu64 iasn;\n\t\t\t};\n\t\t\ts16 local_id;\n\t\t\tu8 remote_id;\n\t\t\tu8 reset_seen: 1;\n\t\t\tu8 reset_transient: 1;\n\t\t\tu8 reset_reason: 4;\n\t\t\tu8 stale_count;\n\t\t\tu32 subflow_id;\n\t\t\tlong int delegated_status;\n\t\t\tlong unsigned int fail_tout;\n\t\t} reset;\n\t};\n\tstruct list_head delegated_node;\n\tu32 setsockopt_seq;\n\tu32 stale_rcv_tstamp;\n\tint cached_sndbuf;\n\tstruct sock *tcp_sock;\n\tstruct sock *conn;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tvoid (*tcp_state_change)(struct sock *);\n\tvoid (*tcp_error_report)(struct sock *);\n\tstruct callback_head rcu;\n};\n\nstruct mptcp_subflow_data {\n\t__u32 size_subflow_data;\n\t__u32 num_subflows;\n\t__u32 size_kernel;\n\t__u32 size_user;\n};\n\nstruct mptcp_subflow_info {\n\t__u32 id;\n\tstruct mptcp_subflow_addrs addrs;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tbool drop_req;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nstruct mptcp_subflow_request_sock {\n\tstruct tcp_request_sock sk;\n\tu16 mp_capable: 1;\n\tu16 mp_join: 1;\n\tu16 backup: 1;\n\tu16 request_bkup: 1;\n\tu16 csum_reqd: 1;\n\tu16 allow_join_id0: 1;\n\tu8 local_id;\n\tu8 remote_id;\n\tu64 local_key;\n\tu64 idsn;\n\tu32 token;\n\tu32 ssn_offset;\n\tu64 thmac;\n\tu32 local_nonce;\n\tu32 remote_nonce;\n\tstruct mptcp_sock *msk;\n\tstruct hlist_nulls_node token_node;\n};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct mqueue_fs_context {\n\tstruct ipc_namespace *ipc_ns;\n\tbool newns;\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[12];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct posix_msg_tree_node;\n\nstruct mqueue_inode_info {\n\tspinlock_t lock;\n\tstruct inode vfs_inode;\n\twait_queue_head_t wait_q;\n\tstruct rb_root msg_tree;\n\tstruct rb_node *msg_tree_rightmost;\n\tstruct posix_msg_tree_node *node_cache;\n\tstruct mq_attr attr;\n\tstruct sigevent notify;\n\tstruct pid *notify_owner;\n\tu32 notify_self_exec_id;\n\tstruct user_namespace *notify_user_ns;\n\tstruct ucounts *ucounts;\n\tstruct sock *notify_sock;\n\tstruct sk_buff *notify_cookie;\n\tstruct ext_wait_queue e_wait_q[2];\n\tlong unsigned int qsize;\n};\n\nstruct mr_mfc_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tstruct list_head *cache;\n\tspinlock_t *lock;\n};\n\nstruct mr_table_ops {\n\tconst struct rhashtable_params *rht_params;\n\tvoid *cmparg_any;\n};\n\nstruct vif_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tlong unsigned int bytes_in;\n\tlong unsigned int bytes_out;\n\tlong unsigned int pkt_in;\n\tlong unsigned int pkt_out;\n\tlong unsigned int rate_limit;\n\tunsigned char threshold;\n\tshort unsigned int flags;\n\tint link;\n\tstruct netdev_phys_item_id dev_parent_id;\n\t__be32 local;\n\t__be32 remote;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct mr_table {\n\tstruct list_head list;\n\tpossible_net_t net;\n\tstruct mr_table_ops ops;\n\tu32 id;\n\tstruct sock *mroute_sk;\n\tstruct timer_list ipmr_expire_timer;\n\tstruct list_head mfc_unres_queue;\n\tstruct vif_device vif_table[32];\n\tstruct rhltable mfc_hash;\n\tstruct list_head mfc_cache_list;\n\tint maxvif;\n\tatomic_t cache_resolve_queue_len;\n\tbool mroute_do_assert;\n\tbool mroute_do_pim;\n\tbool mroute_do_wrvifwhole;\n\tint mroute_reg_vif_num;\n};\n\nstruct mr_vif_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tint ct;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n};\n\nstruct msg_buf {\n\tstruct evbuf_header header;\n\tstruct mdb mdb;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_security_struct {\n\tu32 sid;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_alloc_info {\n\tstruct msi_desc *desc;\n\tirq_hw_number_t hwirq;\n\tlong unsigned int flags;\n\tunion {\n\t\tlong unsigned int ul;\n\t\tvoid *ptr;\n\t} scratchpad[2];\n};\n\ntypedef struct msi_alloc_info msi_alloc_info_t;\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong int msg_stime;\n\tlong int msg_rtime;\n\tlong int msg_ctime;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct mthp_stat {\n\tlong unsigned int stats[153];\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multi_symbols_sort {\n\tconst char **funcs;\n\tu64 *cookies;\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[4];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[64];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct name_cache_entry {\n\tstruct btrfs_lru_cache_entry entry;\n\tu64 parent_ino;\n\tu64 parent_gen;\n\tint ret;\n\tint need_later_update;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u32 offset;\n\t__u32 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct nat_keepalive {\n\tstruct net *net;\n\tu16 family;\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\t__u32 smark;\n};\n\nstruct nat_keepalive_work_ctx {\n\ttime64_t next_run;\n\ttime64_t now;\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n};\n\nstruct nd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\t__u8 opt[0];\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct nduseroptmsg {\n\tunsigned char nduseropt_family;\n\tunsigned char nduseropt_pad1;\n\tshort unsigned int nduseropt_opts_len;\n\tint nduseropt_ifindex;\n\t__u8 nduseropt_icmp_type;\n\t__u8 nduseropt_icmp_code;\n\tshort unsigned int nduseropt_pad2;\n\tunsigned int nduseropt_pad3;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tlong: 0;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct ref_tracker_dir {};\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct linux_tls_mib *tls_statistics;\n\tstruct mptcp_mib *mptcp_statistics;\n\tstruct udp_mib *udplite_statistics;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct udp_tunnel_gro {\n\tstruct sock *sk;\n\tstruct hlist_head list;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct sysctl_fib_multipath_hash_seed {\n\tu32 user_seed;\n\tu32 mp_seed;\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct udp_tunnel_gro udp_tunnel_gro[2];\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tstruct fib_rules_ops *rules_ops;\n\tstruct fib_table *fib_main;\n\tstruct fib_table *fib_default;\n\tunsigned int fib_rules_require_fldissect;\n\tbool fib_has_custom_rules;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tatomic_t fib_num_tclassid_users;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct list_head mr_tables;\n\tstruct fib_rules_ops *mr_rules_ops;\n\tstruct sysctl_fib_multipath_hash_seed sysctl_fib_multipath_hash_seed;\n\tu32 sysctl_fib_multipath_hash_fields;\n\tu8 sysctl_fib_multipath_use_neigh;\n\tu8 sysctl_fib_multipath_hash_policy;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tu32 multipath_hash_fields;\n\tu8 multipath_hash_policy;\n\t__u8 __cacheline_group_begin__sysctl_ipv6_flowlabel[0];\n\tu8 flowlabel_consistency;\n\tu8 auto_flowlabels;\n\tu8 flowlabel_state_ranges;\n\t__u8 __cacheline_group_end__sysctl_ipv6_flowlabel[0];\n\tu8 icmpv6_echo_ignore_all;\n\tu8 icmpv6_echo_ignore_multicast;\n\tu8 icmpv6_echo_ignore_anycast;\n\tint icmpv6_time;\n\tlong unsigned int icmpv6_ratemask[4];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tu8 anycast_src_echo_reply;\n\tu8 bindv6only;\n\tu8 ip_nonlocal_bind;\n\tu8 fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tu32 ioam6_id;\n\tu64 ioam6_id_wide;\n\tu8 skip_notify_on_dev_down;\n\tu8 fib_notify_on_flag_change;\n\tu8 icmpv6_error_anycast_as_unicast;\n\tu8 icmpv6_errors_extension_mask;\n};\n\nstruct rt6_statistics;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct dst_ops ip6_dst_ops;\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tspinlock_t fib_table_hash_lock;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tatomic_t ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned char flowlabel_has_excl;\n\tbool fib6_has_custom_rules;\n\tunsigned int fib6_rules_require_fldissect;\n\tunsigned int fib6_routes_require_src;\n\tstruct rt6_info *ip6_prohibit_entry;\n\tstruct rt6_info *ip6_blk_hole_entry;\n\tstruct fib6_table *fib6_local_tbl;\n\tstruct fib_rules_ops *fib6_rules_ops;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct hlist_head *inet6_addr_lst;\n\tspinlock_t addrconf_hash_lock;\n\tstruct delayed_work addr_chk_work;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tstruct ioam6_pernet_data *ioam6_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sctp_mib;\n\nstruct netns_sctp {\n\tstruct sctp_mib *sctp_statistics;\n\tstruct proc_dir_entry *proc_net_sctp;\n\tstruct ctl_table_header *sysctl_header;\n\tstruct sock *ctl_sock;\n\tstruct sock *udp4_sock;\n\tstruct sock *udp6_sock;\n\tint udp_port;\n\tint encap_port;\n\tstruct list_head local_addr_list;\n\tstruct list_head addr_waitq;\n\tstruct timer_list addr_wq_timer;\n\tstruct list_head auto_asconf_splist;\n\tspinlock_t addr_wq_lock;\n\tspinlock_t local_addr_lock;\n\tunsigned int rto_initial;\n\tunsigned int rto_min;\n\tunsigned int rto_max;\n\tint rto_alpha;\n\tint rto_beta;\n\tint max_burst;\n\tint cookie_preserve_enable;\n\tint cookie_auth_enable;\n\tunsigned int valid_cookie_life;\n\tunsigned int sack_timeout;\n\tunsigned int hb_interval;\n\tunsigned int probe_interval;\n\tint max_retrans_association;\n\tint max_retrans_path;\n\tint max_retrans_init;\n\tint pf_retrans;\n\tint ps_retrans;\n\tint pf_enable;\n\tint pf_expose;\n\tint sndbuf_policy;\n\tint rcvbuf_policy;\n\tint default_auto_asconf;\n\tint addip_enable;\n\tint addip_noauth;\n\tint prsctp_enable;\n\tint reconf_enable;\n\tint auth_enable;\n\tint intl_enable;\n\tint ecn_enable;\n\tint scope_policy;\n\tint rwnd_upd_shift;\n\tlong unsigned int max_autoclose;\n};\n\nstruct nf_logger;\n\nstruct nf_hook_entries;\n\nstruct netns_nf {\n\tstruct proc_dir_entry *proc_netfilter;\n\tconst struct nf_logger *nf_loggers[11];\n\tstruct ctl_table_header *nf_log_dir_header;\n\tstruct ctl_table_header *nf_lwtnl_dir_header;\n\tstruct nf_hook_entries *hooks_ipv4[5];\n\tstruct nf_hook_entries *hooks_ipv6[5];\n\tstruct nf_hook_entries *hooks_arp[3];\n\tstruct nf_hook_entries *hooks_bridge[5];\n\tunsigned int defrag_ipv4_users;\n\tunsigned int defrag_ipv6_users;\n};\n\nstruct nf_generic_net {\n\tunsigned int timeout;\n};\n\nstruct nf_tcp_net {\n\tunsigned int timeouts[14];\n\tu8 tcp_loose;\n\tu8 tcp_be_liberal;\n\tu8 tcp_max_retrans;\n\tu8 tcp_ignore_invalid_rst;\n\tunsigned int offload_timeout;\n};\n\nstruct nf_udp_net {\n\tunsigned int timeouts[2];\n\tunsigned int offload_timeout;\n};\n\nstruct nf_icmp_net {\n\tunsigned int timeout;\n};\n\nstruct nf_sctp_net {\n\tunsigned int timeouts[10];\n};\n\nstruct nf_gre_net {\n\tstruct list_head keymap_list;\n\tunsigned int timeouts[2];\n};\n\nstruct nf_ip_net {\n\tstruct nf_generic_net generic;\n\tstruct nf_tcp_net tcp;\n\tstruct nf_udp_net udp;\n\tstruct nf_icmp_net icmp;\n\tstruct nf_icmp_net icmpv6;\n\tstruct nf_sctp_net sctp;\n\tstruct nf_gre_net gre;\n};\n\nstruct nf_ct_event_notifier;\n\nstruct netns_ct {\n\tbool ecache_dwork_pending;\n\tu8 sysctl_log_invalid;\n\tu8 sysctl_events;\n\tu8 sysctl_acct;\n\tu8 sysctl_tstamp;\n\tu8 sysctl_checksum;\n\tstruct ip_conntrack_stat *stat;\n\tstruct nf_ct_event_notifier *nf_conntrack_event_cb;\n\tstruct nf_ip_net nf_ct_proto;\n\tatomic_t labels_used;\n};\n\nstruct netns_nftables {\n\tunsigned int base_seq;\n\tu8 gencursor;\n};\n\nstruct nf_flow_table_stat;\n\nstruct netns_ft {\n\tstruct nf_flow_table_stat *stat;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct xfrm_policy_hash {\n\tstruct hlist_head *table;\n\tunsigned int hmask;\n\tu8 dbits4;\n\tu8 sbits4;\n\tu8 dbits6;\n\tu8 sbits6;\n};\n\nstruct xfrm_policy_hthresh {\n\tstruct work_struct work;\n\tseqlock_t lock;\n\tu8 lbits4;\n\tu8 rbits4;\n\tu8 lbits6;\n\tu8 rbits6;\n};\n\nstruct netns_xfrm {\n\tstruct list_head state_all;\n\tstruct hlist_head *state_bydst;\n\tstruct hlist_head *state_bysrc;\n\tstruct hlist_head *state_byspi;\n\tstruct hlist_head *state_byseq;\n\tstruct hlist_head *state_cache_input;\n\tunsigned int state_hmask;\n\tunsigned int state_num;\n\tstruct work_struct state_hash_work;\n\tstruct list_head policy_all;\n\tstruct hlist_head *policy_byidx;\n\tunsigned int policy_idx_hmask;\n\tunsigned int idx_generator;\n\tstruct xfrm_policy_hash policy_bydst[3];\n\tunsigned int policy_count[6];\n\tstruct work_struct policy_hash_work;\n\tstruct xfrm_policy_hthresh policy_hthresh;\n\tstruct list_head inexact_bins;\n\tstruct sock *nlsk;\n\tstruct sock *nlsk_stash;\n\tu32 sysctl_aevent_etime;\n\tu32 sysctl_aevent_rseqth;\n\tint sysctl_larval_drop;\n\tu32 sysctl_acq_expires;\n\tu8 policy_default[3];\n\tstruct ctl_table_header *sysctl_hdr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct dst_ops xfrm4_dst_ops;\n\tstruct dst_ops xfrm6_dst_ops;\n\tspinlock_t xfrm_state_lock;\n\tseqcount_spinlock_t xfrm_state_hash_generation;\n\tseqcount_spinlock_t xfrm_policy_hash_generation;\n\tspinlock_t xfrm_policy_lock;\n\tstruct mutex xfrm_cfg_mutex;\n\tstruct delayed_work nat_keepalive_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_ipvs;\n\nstruct mpls_route;\n\nstruct netns_mpls {\n\tint ip_ttl_propagate;\n\tint default_ttl;\n\tsize_t platform_labels;\n\tstruct mpls_route **platform_label;\n\tstruct mutex platform_mutex;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_xdp {\n\tstruct mutex lock;\n\tstruct hlist_head list;\n};\n\nstruct smc_stats;\n\nstruct smc_stats_rsn;\n\nstruct smc_hs_ctrl;\n\nstruct netns_smc {\n\tstruct smc_stats *smc_stats;\n\tstruct mutex mutex_fback_rsn;\n\tstruct smc_stats_rsn *fback_rsn;\n\tbool limit_smc_hs;\n\tstruct ctl_table_header *smc_hdr;\n\tstruct smc_hs_ctrl *hs_ctrl;\n\tunsigned int sysctl_autocorking_size;\n\tunsigned int sysctl_smcr_buf_type;\n\tint sysctl_smcr_testlink_time;\n\tint sysctl_wmem;\n\tint sysctl_rmem;\n\tint sysctl_max_links_per_lgr;\n\tint sysctl_max_conns_per_lgr;\n\tunsigned int sysctl_smcr_max_send_wr;\n\tunsigned int sysctl_smcr_max_recv_wr;\n};\n\nstruct netns_vsock {\n\tstruct ctl_table_header *sysctl_hdr;\n\tu32 port;\n\tenum vsock_net_mode mode;\n\tenum vsock_net_mode child_ns_mode;\n\tint child_ns_mode_locked;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct netns_sctp sctp;\n\tstruct netns_nf nf;\n\tstruct netns_ct ct;\n\tstruct netns_nftables nft;\n\tstruct netns_ft ft;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_xfrm xfrm;\n\tu64 net_cookie;\n\tstruct netns_ipvs *ipvs;\n\tstruct netns_mpls mpls;\n\tstruct netns_xdp xdp;\n\tstruct sock *crypto_nlsk;\n\tstruct sock *diag_nlsk;\n\tstruct netns_smc smc;\n\tstruct netns_vsock vsock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct net_bridge_vlan;\n\nstruct net_bridge_mcast {\n\tstruct net_bridge *br;\n\tstruct net_bridge_vlan *vlan;\n\tu32 multicast_last_member_count;\n\tu32 multicast_startup_query_count;\n\tu8 multicast_querier;\n\tu8 multicast_igmp_version;\n\tu8 multicast_router;\n\tu8 multicast_mld_version;\n\tlong unsigned int multicast_last_member_interval;\n\tlong unsigned int multicast_membership_interval;\n\tlong unsigned int multicast_querier_interval;\n\tlong unsigned int multicast_query_interval;\n\tlong unsigned int multicast_query_response_interval;\n\tlong unsigned int multicast_startup_query_interval;\n\tstruct hlist_head ip4_mc_router_list;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct bridge_mcast_other_query ip4_other_query;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct bridge_mcast_querier ip4_querier;\n\tstruct hlist_head ip6_mc_router_list;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct bridge_mcast_other_query ip6_other_query;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct bridge_mcast_querier ip6_querier;\n};\n\nstruct net_bridge {\n\tspinlock_t lock;\n\tspinlock_t hash_lock;\n\tstruct hlist_head frame_type_list;\n\tstruct net_device *dev;\n\tlong unsigned int options;\n\tstruct rhashtable fdb_hash_tbl;\n\tstruct list_head port_list;\n\tunion {\n\t\tstruct rtable fake_rtable;\n\t\tstruct rt6_info fake_rt6_info;\n\t};\n\tu32 metrics[17];\n\tu16 group_fwd_mask;\n\tu16 group_fwd_mask_required;\n\tbridge_id designated_root;\n\tbridge_id bridge_id;\n\tunsigned char topology_change;\n\tunsigned char topology_change_detected;\n\tu16 root_port;\n\tlong unsigned int max_age;\n\tlong unsigned int hello_time;\n\tlong unsigned int forward_delay;\n\tlong unsigned int ageing_time;\n\tlong unsigned int bridge_max_age;\n\tlong unsigned int bridge_hello_time;\n\tlong unsigned int bridge_forward_delay;\n\tlong unsigned int bridge_ageing_time;\n\tu32 root_path_cost;\n\tu8 group_addr[6];\n\tenum {\n\t\tBR_NO_STP = 0,\n\t\tBR_KERNEL_STP = 1,\n\t\tBR_USER_STP = 2,\n\t} stp_enabled;\n\tstruct net_bridge_mcast multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 hash_max;\n\tspinlock_t multicast_lock;\n\tstruct rhashtable mdb_hash_tbl;\n\tstruct rhashtable sg_port_tbl;\n\tstruct hlist_head mcast_gc_list;\n\tstruct hlist_head mdb_list;\n\tstruct work_struct mcast_gc_work;\n\tstruct timer_list hello_timer;\n\tstruct timer_list tcn_timer;\n\tstruct timer_list topology_change_timer;\n\tstruct delayed_work gc_work;\n\tstruct kobject *ifobj;\n\tu32 auto_cnt;\n\tatomic_t fdb_n_learned;\n\tu32 fdb_max_learned;\n\tint last_hwdom;\n\tlong unsigned int busy_hwdoms;\n\tstruct hlist_head fdb_list;\n\tstruct hlist_head mrp_list;\n};\n\nunion net_bridge_eht_addr {\n\t__be32 ip4;\n\tstruct in6_addr ip6;\n};\n\nstruct net_bridge_fdb_key {\n\tmac_addr addr;\n\tu16 vlan_id;\n};\n\nstruct net_bridge_fdb_entry {\n\tstruct rhash_head rhnode;\n\tstruct net_bridge_port *dst;\n\tstruct net_bridge_fdb_key key;\n\tstruct hlist_node fdb_node;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_bridge_fdb_flush_desc {\n\tlong unsigned int flags;\n\tlong unsigned int flags_mask;\n\tint port_ifindex;\n\tu16 vlan_id;\n};\n\nstruct net_bridge_port_group;\n\nstruct net_bridge_group_eht_host {\n\tstruct rb_node rb_node;\n\tunion net_bridge_eht_addr h_addr;\n\tstruct hlist_head set_entries;\n\tunsigned int num_entries;\n\tunsigned char filter_mode;\n\tstruct net_bridge_port_group *pg;\n};\n\nstruct net_bridge_mcast_gc {\n\tstruct hlist_node gc_node;\n\tvoid (*destroy)(struct net_bridge_mcast_gc *);\n};\n\nstruct net_bridge_group_eht_set {\n\tstruct rb_node rb_node;\n\tunion net_bridge_eht_addr src_addr;\n\tstruct rb_root entry_tree;\n\tstruct timer_list timer;\n\tstruct net_bridge_port_group *pg;\n\tstruct net_bridge *br;\n\tstruct net_bridge_mcast_gc mcast_gc;\n};\n\nstruct net_bridge_group_eht_set_entry {\n\tstruct rb_node rb_node;\n\tstruct hlist_node host_list;\n\tunion net_bridge_eht_addr h_addr;\n\tstruct timer_list timer;\n\tstruct net_bridge *br;\n\tstruct net_bridge_group_eht_set *eht_set;\n\tstruct net_bridge_group_eht_host *h_parent;\n\tstruct net_bridge_mcast_gc mcast_gc;\n};\n\nstruct net_bridge_group_src {\n\tstruct hlist_node node;\n\tstruct br_ip addr;\n\tstruct net_bridge_port_group *pg;\n\tu8 flags;\n\tu8 src_query_rexmit_cnt;\n\tstruct timer_list timer;\n\tstruct net_bridge *br;\n\tstruct net_bridge_mcast_gc mcast_gc;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_mcast_port {\n\tstruct net_bridge_port *port;\n\tstruct net_bridge_vlan *vlan;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct hlist_node ip4_rlist;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct hlist_node ip6_rlist;\n\tunsigned char multicast_router;\n\tu32 mdb_n_entries;\n\tu32 mdb_max_entries;\n};\n\nstruct net_bridge_mdb_entry {\n\tstruct rhash_head rhnode;\n\tstruct net_bridge *br;\n\tstruct net_bridge_port_group *ports;\n\tstruct br_ip addr;\n\tbool host_joined;\n\tstruct timer_list timer;\n\tstruct hlist_node mdb_node;\n\tstruct net_bridge_mcast_gc mcast_gc;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_port {\n\tstruct net_bridge *br;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tstruct net_bridge_port *backup_port;\n\tu32 backup_nhid;\n\tu8 priority;\n\tu8 state;\n\tu16 port_no;\n\tunsigned char topology_change_ack;\n\tunsigned char config_pending;\n\tport_id port_id;\n\tport_id designated_port;\n\tbridge_id designated_root;\n\tbridge_id designated_bridge;\n\tu32 path_cost;\n\tu32 designated_cost;\n\tlong unsigned int designated_age;\n\tstruct timer_list forward_delay_timer;\n\tstruct timer_list hold_timer;\n\tstruct timer_list message_age_timer;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n\tstruct net_bridge_mcast_port multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 multicast_eht_hosts_limit;\n\tu32 multicast_eht_hosts_cnt;\n\tstruct hlist_head mglist;\n\tchar sysfs_name[16];\n\tint hwdom;\n\tint offload_count;\n\tstruct netdev_phys_item_id ppid;\n\tu16 group_fwd_mask;\n\tu16 backup_redirected_cnt;\n\tstruct bridge_stp_xstats stp_xstats;\n};\n\nstruct net_bridge_port_group_sg_key {\n\tstruct net_bridge_port *port;\n\tstruct br_ip addr;\n};\n\nstruct net_bridge_port_group {\n\tstruct net_bridge_port_group *next;\n\tstruct net_bridge_port_group_sg_key key;\n\tunsigned char eth_addr[6];\n\tunsigned char flags;\n\tunsigned char filter_mode;\n\tunsigned char grp_query_rexmit_cnt;\n\tunsigned char rt_protocol;\n\tstruct hlist_head src_list;\n\tunsigned int src_ents;\n\tstruct timer_list timer;\n\tstruct timer_list rexmit_timer;\n\tstruct hlist_node mglist;\n\tstruct rb_root eht_set_tree;\n\tstruct rb_root eht_host_tree;\n\tstruct rhash_head rhnode;\n\tstruct net_bridge_mcast_gc mcast_gc;\n\tstruct callback_head rcu;\n};\n\nstruct pcpu_sw_netstats;\n\nstruct net_bridge_vlan {\n\tstruct rhash_head vnode;\n\tstruct rhash_head tnode;\n\tu16 vid;\n\tu16 flags;\n\tu16 priv_flags;\n\tu8 state;\n\tstruct pcpu_sw_netstats *stats;\n\tunion {\n\t\tstruct net_bridge *br;\n\t\tstruct net_bridge_port *port;\n\t};\n\tunion {\n\t\trefcount_t refcnt;\n\t\tstruct net_bridge_vlan *brvlan;\n\t};\n\tstruct br_tunnel_info tinfo;\n\tunion {\n\t\tstruct net_bridge_mcast br_mcast_ctx;\n\t\tstruct net_bridge_mcast_port port_mcast_ctx;\n\t};\n\tu16 msti;\n\tstruct list_head vlist;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_vlan_group {\n\tstruct rhashtable vlan_hash;\n\tstruct rhashtable tunnel_hash;\n\tstruct list_head vlan_list;\n\tu16 num_vlans;\n\tu16 pvid;\n\tu8 pvid_state;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct garp_port;\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_dstats;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct tlsdev_ops;\n\nstruct vlan_info;\n\nstruct xdp_dev_bulk_queue;\n\nstruct rtnl_link_ops;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct netprio_map;\n\nstruct phy_link_topology;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct nf_hook_entries *nf_hooks_egress;\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tconst struct tlsdev_ops *tlsdev_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tstruct vlan_info *vlan_info;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tstruct nf_hook_entries *nf_hooks_ingress;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct hlist_head qdisc_hash[16];\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct garp_port *garp_port;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct netprio_map *priomap;\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct rtnl_link_stats64;\n\nstruct netdev_bpf;\n\nstruct xdp_frame;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct inet6_protocol tcpv6_protocol;\n\tstruct inet6_protocol udpv6_protocol;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct net_if_token {\n\t__u16 devnum;\n\t__u8 cssid;\n\t__u8 iid;\n\t__u8 ssid;\n\t__u8 chpid;\n\t__u16 chid;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct xsk_buff_pool;\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tstruct xsk_buff_pool *pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tint numa_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct xsk_buff_pool *pool;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n\tu8 sched_mirred_nest;\n\tstruct net_device *sched_mirred_dev[4];\n\tu8 nf_dup_skb_recursion;\n};\n\nstruct netevent_redirect {\n\tstruct dst_entry *old;\n\tstruct dst_entry *new;\n\tstruct neighbour *neigh;\n\tconst void *daddr;\n};\n\nstruct netif_security_struct {\n\tconst struct net *ns;\n\tint ifindex;\n\tu32 sid;\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netnode_security_struct {\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} addr;\n\tu32 sid;\n\tu16 family;\n};\n\nstruct netport_security_struct {\n\tu32 sid;\n\tu16 port;\n\tu8 protocol;\n};\n\nstruct netprio_map {\n\tstruct callback_head rcu;\n\tu32 priomap_len;\n\tu32 priomap[0];\n};\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_br_ops {\n\tint (*br_dev_xmit_hook)(struct sk_buff *);\n};\n\nstruct nf_bridge_info {\n\tenum {\n\t\tBRNF_PROTO_UNCHANGED = 0,\n\t\tBRNF_PROTO_8021Q = 1,\n\t\tBRNF_PROTO_PPPOE = 2,\n\t} orig_proto: 8;\n\tu8 pkt_otherhost: 1;\n\tu8 in_prerouting: 1;\n\tu8 bridged_dnat: 1;\n\tu8 sabotage_in_done: 1;\n\t__u16 frag_max_size;\n\tint physinif;\n\tstruct net_device *physoutdev;\n\tunion {\n\t\t__be32 ipv4_daddr;\n\t\tstruct in6_addr ipv6_daddr;\n\t\tchar neigh_header[8];\n\t};\n};\n\nstruct nf_conntrack {\n\trefcount_t use;\n};\n\nstruct nf_conntrack_zone {\n\tu16 id;\n\tu8 flags;\n\tu8 dir;\n};\n\nunion nf_inet_addr {\n\t__u32 all[4];\n\t__be32 ip;\n\t__be32 ip6[4];\n\tstruct in_addr in;\n\tstruct in6_addr in6;\n};\n\nunion nf_conntrack_man_proto {\n\t__be16 all;\n\tstruct {\n\t\t__be16 port;\n\t} tcp;\n\tstruct {\n\t\t__be16 port;\n\t} udp;\n\tstruct {\n\t\t__be16 id;\n\t} icmp;\n\tstruct {\n\t\t__be16 port;\n\t} dccp;\n\tstruct {\n\t\t__be16 port;\n\t} sctp;\n\tstruct {\n\t\t__be16 key;\n\t} gre;\n};\n\nstruct nf_conntrack_man {\n\tunion nf_inet_addr u3;\n\tunion nf_conntrack_man_proto u;\n\tu_int16_t l3num;\n};\n\nstruct nf_conntrack_tuple {\n\tstruct nf_conntrack_man src;\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion {\n\t\t\t__be16 all;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} tcp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} udp;\n\t\t\tstruct {\n\t\t\t\tu_int8_t type;\n\t\t\t\tu_int8_t code;\n\t\t\t} icmp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} dccp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} sctp;\n\t\t\tstruct {\n\t\t\t\t__be16 key;\n\t\t\t} gre;\n\t\t} u;\n\t\tu_int8_t protonum;\n\t\tstruct {} __nfct_hash_offsetend;\n\t\tu_int8_t dir;\n\t} dst;\n};\n\nstruct nf_conntrack_tuple_hash {\n\tstruct hlist_nulls_node hnnode;\n\tstruct nf_conntrack_tuple tuple;\n};\n\nstruct nf_ct_udp {\n\tlong unsigned int stream_ts;\n};\n\nstruct nf_ct_gre {\n\tunsigned int stream_timeout;\n\tunsigned int timeout;\n};\n\nunion nf_conntrack_proto {\n\tstruct ip_ct_sctp sctp;\n\tstruct ip_ct_tcp tcp;\n\tstruct nf_ct_udp udp;\n\tstruct nf_ct_gre gre;\n\tunsigned int tmpl_padto;\n};\n\nstruct nf_ct_ext;\n\nstruct nf_conn {\n\tstruct nf_conntrack ct_general;\n\tspinlock_t lock;\n\tu32 timeout;\n\tstruct nf_conntrack_zone zone;\n\tstruct nf_conntrack_tuple_hash tuplehash[2];\n\tlong unsigned int status;\n\tpossible_net_t ct_net;\n\tstruct hlist_node nat_bysource;\n\tstruct {} __nfct_init_offset;\n\tstruct nf_conn *master;\n\tu_int32_t mark;\n\tu_int32_t secmark;\n\tstruct nf_ct_ext *ext;\n\tunion nf_conntrack_proto proto;\n};\n\nstruct nf_conn___init {\n\tstruct nf_conn ct;\n};\n\nstruct nf_conn_labels {\n\tlong unsigned int bits[2];\n};\n\nstruct nf_conntrack_tuple_mask {\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion nf_conntrack_man_proto u;\n\t} src;\n};\n\nstruct nf_conntrack_helper;\n\nstruct nf_conntrack_expect {\n\tstruct hlist_node lnode;\n\tstruct hlist_node hnode;\n\tstruct nf_conntrack_tuple tuple;\n\tstruct nf_conntrack_tuple_mask mask;\n\trefcount_t use;\n\tunsigned int flags;\n\tunsigned int class;\n\tvoid (*expectfn)(struct nf_conn *, struct nf_conntrack_expect *);\n\tstruct nf_conntrack_helper *helper;\n\tstruct nf_conn *master;\n\tstruct timer_list timeout;\n\tunion nf_inet_addr saved_addr;\n\tunion nf_conntrack_man_proto saved_proto;\n\tenum ip_conntrack_dir dir;\n\tstruct callback_head rcu;\n};\n\nstruct nf_ct_event {\n\tstruct nf_conn *ct;\n\tu32 portid;\n\tint report;\n};\n\nstruct nf_exp_event;\n\nstruct nf_ct_event_notifier {\n\tint (*ct_event)(unsigned int, const struct nf_ct_event *);\n\tint (*exp_event)(unsigned int, const struct nf_exp_event *);\n};\n\nstruct nf_ct_ext {\n\tu8 offset[10];\n\tu8 len;\n\tunsigned int gen_id;\n\tchar data[0];\n};\n\nstruct nf_ct_hook {\n\tint (*update)(struct net *, struct sk_buff *);\n\tvoid (*destroy)(struct nf_conntrack *);\n\tbool (*get_tuple_skb)(struct nf_conntrack_tuple *, const struct sk_buff *);\n\tvoid (*attach)(struct sk_buff *, const struct sk_buff *);\n\tvoid (*set_closing)(struct nf_conntrack *);\n\tint (*confirm)(struct sk_buff *);\n\tu32 (*get_id)(const struct nf_conntrack *);\n};\n\nstruct nf_defrag_hook {\n\tstruct module *owner;\n\tint (*enable)(struct net *);\n\tvoid (*disable)(struct net *);\n};\n\nstruct nf_exp_event {\n\tstruct nf_conntrack_expect *exp;\n\tu32 portid;\n\tint report;\n};\n\nstruct nf_flow_table_stat {\n\tunsigned int count_wq_add;\n\tunsigned int count_wq_del;\n\tunsigned int count_wq_stats;\n};\n\nstruct nf_hook_entry {\n\tnf_hookfn *hook;\n\tvoid *priv;\n};\n\nstruct nf_hook_entries {\n\tu16 num_hook_entries;\n\tstruct nf_hook_entry hooks[0];\n};\n\nstruct nf_hook_entries_rcu_head {\n\tstruct callback_head head;\n\tvoid *allocation;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nf_queue_entry;\n\nstruct nf_ipv6_ops {\n\tvoid (*route_input)(struct sk_buff *);\n\tint (*fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tint (*reroute)(struct sk_buff *, const struct nf_queue_entry *);\n};\n\nstruct nf_log_buf {\n\tunsigned int count;\n\tchar buf[1020];\n};\n\nstruct nf_loginfo;\n\ntypedef void nf_logfn(struct net *, u_int8_t, unsigned int, const struct sk_buff *, const struct net_device *, const struct net_device *, const struct nf_loginfo *, const char *);\n\nstruct nf_logger {\n\tchar *name;\n\tenum nf_log_type type;\n\tnf_logfn *logfn;\n\tstruct module *me;\n};\n\nstruct nf_loginfo {\n\tu_int8_t type;\n\tunion {\n\t\tstruct {\n\t\t\tu_int32_t copy_len;\n\t\t\tu_int16_t group;\n\t\t\tu_int16_t qthreshold;\n\t\t\tu_int16_t flags;\n\t\t} ulog;\n\t\tstruct {\n\t\t\tu_int8_t level;\n\t\t\tu_int8_t logflags;\n\t\t} log;\n\t} u;\n};\n\nstruct nf_nat_hook {\n\tint (*parse_nat_setup)(struct nf_conn *, enum nf_nat_manip_type, const struct nlattr *);\n\tvoid (*decode_session)(struct sk_buff *, struct flowi *);\n\tvoid (*remove_nat_bysrc)(struct nf_conn *);\n};\n\nstruct nf_queue_entry {\n\tstruct list_head list;\n\tstruct rhash_head hash_node;\n\tstruct sk_buff *skb;\n\tunsigned int id;\n\tunsigned int hook_index;\n\tstruct net_device *physin;\n\tstruct net_device *physout;\n\tstruct nf_hook_state state;\n\tbool nf_ct_is_unconfirmed;\n\tu16 size;\n\tu16 queue_num;\n};\n\nstruct nf_queue_handler {\n\tint (*outfn)(struct nf_queue_entry *, unsigned int);\n\tvoid (*nf_hook_drop)(struct net *);\n};\n\nstruct nf_sockopt_ops {\n\tstruct list_head list;\n\tu_int8_t pf;\n\tint set_optmin;\n\tint set_optmax;\n\tint (*set)(struct sock *, int, sockptr_t, unsigned int);\n\tint get_optmin;\n\tint get_optmax;\n\tint (*get)(struct sock *, int, void *, int *);\n\tstruct module *owner;\n};\n\nstruct nfnl_ct_hook {\n\tsize_t (*build_size)(const struct nf_conn *);\n\tint (*build)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, u_int16_t, u_int16_t);\n\tint (*parse)(const struct nlattr *, struct nf_conn *);\n\tint (*attach_expect)(const struct nlattr *, struct nf_conn *, u32, u32);\n\tvoid (*seq_adjust)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, s32);\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlmsg_perm {\n\tu16 nlmsg_type;\n\tu32 perm;\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\nstruct node {\n\tstruct device dev;\n\tstruct list_head access_list;\n};\n\nstruct node_access_nodes {\n\tstruct device dev;\n\tstruct list_head list_node;\n\tunsigned int access;\n};\n\nstruct node_attr {\n\tstruct device_attribute attr;\n\tenum node_states state;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_hstate {\n\tstruct kobject *hugepages_kobj;\n\tstruct kobject *hstate_kobjs[2];\n};\n\nstruct node_memory_type_map {\n\tstruct memory_dev_type *memtype;\n\tint map_count;\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct nodemask_scratch {\n\tnodemask_t mask1;\n\tnodemask_t mask2;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n} __attribute__((packed));\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t drops1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct numa_group {\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tint nr_tasks;\n\tpid_t gid;\n\tint active_nodes;\n\tstruct callback_head rcu;\n\tlong unsigned int total_faults;\n\tlong unsigned int max_faults_cpu;\n\tlong unsigned int faults[0];\n};\n\nstruct numa_maps {\n\tlong unsigned int pages;\n\tlong unsigned int anon;\n\tlong unsigned int active;\n\tlong unsigned int writeback;\n\tlong unsigned int mapcount_max;\n\tlong unsigned int dirty;\n\tlong unsigned int swapcache;\n\tlong unsigned int node[2];\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n\tbool mmap_locked;\n\tstruct vm_area_struct *locked_vma;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tstruct mempolicy *task_mempolicy;\n};\n\nstruct numa_maps_private {\n\tstruct proc_maps_private proc_maps;\n\tstruct numa_maps md;\n};\n\nstruct numa_stats {\n\tlong unsigned int load;\n\tlong unsigned int runnable;\n\tlong unsigned int util;\n\tlong unsigned int compute_capacity;\n\tunsigned int nr_running;\n\tunsigned int weight;\n\tenum numa_type node_type;\n\tint idle_cpu;\n};\n\nstruct obj_cgroup {\n\tstruct percpu_ref refcnt;\n\tstruct mem_cgroup *memcg;\n\tatomic_t nr_charged_bytes;\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct obj_stock_pcp {\n\tlocal_trylock_t lock;\n\tunsigned int nr_bytes;\n\tstruct obj_cgroup *cached_objcg;\n\tstruct pglist_data *cached_pgdat;\n\tint nr_slab_reclaimable_b;\n\tint nr_slab_unreclaimable_b;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct ocontext {\n\tunion {\n\t\tchar *name;\n\t\tstruct {\n\t\t\tu8 protocol;\n\t\t\tu16 low_port;\n\t\t\tu16 high_port;\n\t\t} port;\n\t\tstruct {\n\t\t\tu32 addr;\n\t\t\tu32 mask;\n\t\t} node;\n\t\tstruct {\n\t\t\tu32 addr[4];\n\t\t\tu32 mask[4];\n\t\t} node6;\n\t\tstruct {\n\t\t\tu64 subnet_prefix;\n\t\t\tu16 low_pkey;\n\t\t\tu16 high_pkey;\n\t\t} ibpkey;\n\t\tstruct {\n\t\t\tchar *dev_name;\n\t\t\tu8 port;\n\t\t} ibendport;\n\t} u;\n\tunion {\n\t\tu32 sclass;\n\t\tu32 behavior;\n\t} v;\n\tstruct context context[2];\n\tu32 sid[2];\n\tstruct ocontext *next;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct old_sigaction {\n\t__sighandler_t sa_handler;\n\told_sigset_t sa_mask;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct oldmem_data {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\nstruct orphan_dir_info {\n\tstruct rb_node node;\n\tu64 ino;\n\tu64 gen;\n\tu64 last_dir_index_offset;\n\tu64 dir_high_seq_ino;\n};\n\nstruct os_info_entry {\n\tunion {\n\t\tu64 addr;\n\t\tu64 val;\n\t};\n\tu64 size;\n\tu32 csum;\n} __attribute__((packed));\n\nstruct os_info {\n\tu64 magic;\n\tu32 csum;\n\tu16 version_major;\n\tu16 version_minor;\n\tu64 crashkernel_addr;\n\tu64 crashkernel_size;\n\tstruct os_info_entry entry[13];\n\tu8 reserved[3804];\n};\n\nstruct osnoise_entry {\n\tstruct trace_entry ent;\n\tu64 noise;\n\tu64 runtime;\n\tu64 max_sample;\n\tunsigned int hw_count;\n\tunsigned int nmi_count;\n\tunsigned int irq_count;\n\tunsigned int softirq_count;\n\tunsigned int thread_count;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tu64 bus_offset;\n};\n\nstruct pacct_struct {\n\tint ac_flag;\n\tlong int ac_exitcode;\n\tlong unsigned int ac_mem;\n\tu64 ac_utime;\n\tu64 ac_stime;\n\tlong unsigned int ac_minflt;\n\tlong unsigned int ac_majflt;\n};\n\nstruct scsi_sense_hdr;\n\nstruct packet_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct scsi_sense_hdr *sshdr;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 history[64];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t tp_drops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct padata_cpumask {\n\tcpumask_var_t pcpu;\n\tcpumask_var_t cbcpu;\n};\n\nstruct padata_instance {\n\tstruct hlist_node cpu_online_node;\n\tstruct hlist_node cpu_dead_node;\n\tstruct workqueue_struct *parallel_wq;\n\tstruct workqueue_struct *serial_wq;\n\tstruct list_head pslist;\n\tstruct padata_cpumask cpumask;\n\tstruct kobject kobj;\n\tstruct mutex lock;\n\tu8 flags;\n};\n\nstruct padata_list {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct padata_mt_job {\n\tvoid (*thread_fn)(long unsigned int, long unsigned int, void *);\n\tvoid *fn_arg;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int min_chunk;\n\tint max_threads;\n\tbool numa_aware;\n};\n\nstruct padata_mt_job_state {\n\tspinlock_t lock;\n\tstruct completion completion;\n\tstruct padata_mt_job *job;\n\tint nworks;\n\tint nworks_fini;\n\tlong unsigned int chunk_size;\n};\n\nstruct parallel_data;\n\nstruct padata_priv {\n\tstruct list_head list;\n\tstruct parallel_data *pd;\n\tint cb_cpu;\n\tunsigned int seq_nr;\n\tint info;\n\tvoid (*parallel)(struct padata_priv *);\n\tvoid (*serial)(struct padata_priv *);\n};\n\nstruct padata_serial_queue {\n\tstruct padata_list serial;\n\tstruct work_struct work;\n\tstruct parallel_data *pd;\n};\n\nstruct padata_shell {\n\tstruct padata_instance *pinst;\n\tstruct parallel_data *pd;\n\tstruct parallel_data *opd;\n\tstruct list_head list;\n};\n\nstruct padata_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct padata_instance *, const struct attribute *, char *);\n\tssize_t (*store)(struct padata_instance *, const struct attribute *, const char *, size_t);\n};\n\nstruct padata_work {\n\tstruct work_struct pw_work;\n\tstruct list_head pw_list;\n\tvoid *pw_data;\n};\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_list {\n\tstruct page_list *next;\n\tstruct page *page;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct page_pool_alloc_stats {\n\tu64 fast;\n\tu64 slow;\n\tu64 slow_high_order;\n\tu64 empty;\n\tu64 refill;\n\tu64 waive;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool_recycle_stats;\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tbool system: 1;\n\tlong: 0;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\tlong: 0;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tstruct page_pool_alloc_stats alloc_stats;\n\tu32 xdp_mem_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pp_alloc_cache alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tstruct page_pool_recycle_stats *recycle_stats;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t} user;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_pool_recycle_stats {\n\tu64 cached;\n\tu64 cache_full;\n\tu64 ring;\n\tu64 ring_full;\n\tu64 released_refcnt;\n};\n\nstruct page_pool_stats {\n\tstruct page_pool_alloc_stats alloc_stats;\n\tstruct page_pool_recycle_stats recycle_stats;\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_reporting_dev_info {\n\tint (*report)(struct page_reporting_dev_info *, struct scatterlist *, unsigned int);\n\tstruct delayed_work work;\n\tatomic_t state;\n\tunsigned int order;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n\tlong: 64;\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct pai_userdata;\n\nstruct paiext_cb;\n\nstruct pai_map {\n\tlong unsigned int *area;\n\tstruct pai_userdata *save;\n\tunsigned int active_events;\n\trefcount_t refcnt;\n\tstruct perf_event *event;\n\tstruct list_head syswide_list;\n\tstruct paiext_cb *paiext_cb;\n\tbool fullpage;\n};\n\nstruct pai_mapptr {\n\tstruct pai_map *mapptr;\n};\n\nstruct pai_pmu {\n\tconst char *pmuname;\n\tconst int facility_nr;\n\tunsigned int num_avail;\n\tunsigned int num_named;\n\tlong unsigned int base;\n\tlong unsigned int kernel_offset;\n\tlong unsigned int area_size;\n\tconst char * const *names;\n\tstruct pmu *pmu;\n\tint (*init)(struct pai_pmu *);\n\tvoid (*exit)(struct pai_pmu *);\n\tstruct attribute_group *event_group;\n};\n\nstruct pai_root {\n\trefcount_t refcnt;\n\tstruct pai_mapptr *mapptr;\n};\n\nstruct pai_userdata {\n\tu16 num;\n\tu64 value;\n} __attribute__((packed));\n\nstruct paiext_cb {\n\tu64 header;\n\tu64 reserved1;\n\tu64 acc;\n\tu8 reserved2[1000];\n};\n\nstruct par_sctn {\n\tu8 infpflg1;\n\tu8 infpflg2;\n\tu8 infpval1;\n\tu8 infpval2;\n\tu16 infppnum;\n\tu16 infpscps;\n\tu16 infpdcps;\n\tu16 infpsifl;\n\tu16 infpdifl;\n\tu16 reserved;\n\tchar infppnam[8];\n\tu32 infpwbcp;\n\tu32 infpabcp;\n\tu32 infpwbif;\n\tu32 infpabif;\n\tchar infplgnm[8];\n\tu32 infplgcp;\n\tu32 infplgif;\n};\n\nstruct parallel_data {\n\tstruct padata_shell *ps;\n\tstruct padata_list *reorder_list;\n\tstruct padata_serial_queue *squeue;\n\trefcount_t refcnt;\n\tunsigned int seq_nr;\n\tunsigned int processed;\n\tint cpu;\n\tstruct padata_cpumask cpumask;\n};\n\nstruct parmarea {\n\tlong unsigned int ipl_device;\n\tlong unsigned int initrd_start;\n\tlong unsigned int initrd_size;\n\tlong unsigned int oldmem_base;\n\tlong unsigned int oldmem_size;\n\tlong unsigned int kernel_version;\n\tlong unsigned int max_command_line_size;\n\tchar pad1[72];\n\tchar command_line[4096];\n};\n\nstruct parsed_desc {\n\tu32 mb;\n\tu32 valid;\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_ops;\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_cfg_sccb {\n\tstruct sccb_header header;\n\tu8 atype;\n\tu8 reserved1;\n\tu16 reserved2;\n\tu32 aid;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct pcie_bwctrl_data;\n\nstruct pci_sriov;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[17];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[17];\n\tstruct bin_attribute *res_attr_wc[17];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tunion {\n\t\tstruct pci_sriov *sriov;\n\t\tstruct pci_dev *physfn;\n\t};\n\tu16 ats_cap;\n\tu8 ats_stu;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tvoid (*hook)(struct pci_dev *);\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pci_sriov {\n\tint pos;\n\tint nres;\n\tu32 cap;\n\tu16 ctrl;\n\tu16 total_VFs;\n\tu16 initial_VFs;\n\tu16 num_VFs;\n\tu16 offset;\n\tu16 stride;\n\tu16 vf_device;\n\tu32 pgsz;\n\tu8 link;\n\tu8 max_VF_buses;\n\tu16 driver_max_VFs;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *self;\n\tu32 class;\n\tu8 hdr_type;\n\tu16 subsystem_vendor;\n\tu16 subsystem_device;\n\tresource_size_t barsz[6];\n\tu16 vf_rebar_cap;\n\tbool drivers_autoprobe;\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[17];\n};\n\nstruct pcpu {\n\tlong unsigned int ec_mask;\n\tlong unsigned int ec_clk;\n\tlong unsigned int flags;\n\tlong unsigned int capacity;\n\tsigned char state;\n\tsigned char polarization;\n\tu16 address;\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpuobj_ext;\n\nstruct pcpu_chunk {\n\tint nr_alloc;\n\tsize_t max_alloc_size;\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tstruct pcpuobj_ext *obj_exts;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpuobj_ext {\n\tstruct obj_cgroup *cgroup;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pdev_archdata {};\n\nstruct pe_handler_work_data {\n\tstruct work_struct worker;\n\tstruct dasd_device *device;\n\tstruct dasd_ccw_req cqr;\n\tstruct ccw1 ccw;\n\t__u8 rcd_buffer[256];\n\tint isglobal;\n\t__u8 tbvpm;\n\t__u8 fcsecpm;\n};\n\nstruct pending_dir_move {\n\tstruct rb_node node;\n\tstruct list_head list;\n\tu64 parent_ino;\n\tu64 ino;\n\tu64 gen;\n\tstruct list_head update_refs;\n};\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[51];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tu8 expire;\n\tshort int free_count;\n\tstruct list_head lists[14];\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[11];\n\ts8 stat_threshold;\n\tlong unsigned int vm_numa_event[6];\n};\n\nstruct per_event {\n\tshort unsigned int cause;\n\tlong unsigned int address;\n\tunsigned char paid;\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\nstruct per_regs {\n\tlong unsigned int control;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct percpu_free_defer {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\ntypedef struct percpu_rw_semaphore *class_percpu_read_t;\n\ntypedef struct percpu_rw_semaphore *class_percpu_write_t;\n\nstruct percpu_stats {\n\tu64 nr_alloc;\n\tu64 nr_dealloc;\n\tu64 nr_cur_alloc;\n\tu64 nr_max_alloc;\n\tu32 nr_chunks;\n\tu32 nr_max_chunks;\n\tsize_t min_alloc_size;\n\tsize_t max_alloc_size;\n};\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[9];\n\tlong unsigned int offset[9];\n\tlocal_lock_t lock;\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu64 hw_id;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___3 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 spec: 2;\n\t__u64 new_type: 4;\n\t__u64 priv: 3;\n\t__u64 reserved: 31;\n};\n\nstruct perf_branch_stack {\n\tu64 nr;\n\tu64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct perf_event_mmap_page;\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\trefcount_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tstruct mutex aux_mutex;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\trefcount_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tint aux_in_pause_resume;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct unwind_stacktrace;\n\nstruct perf_callchain_deferred_event {\n\tstruct unwind_stacktrace *trace;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 cookie;\n\t\tu64 nr;\n\t\tu64 ips[0];\n\t} event;\n};\n\nstruct perf_callchain_entry {\n\tu64 nr;\n\tu64 ip[0];\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nstruct perf_cgroup_info;\n\nstruct perf_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct perf_cgroup_info *info;\n};\n\nstruct perf_cgroup_event {\n\tchar *path;\n\tint path_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 id;\n\t\tchar path[0];\n\t} event_id;\n};\n\nstruct perf_time_ctx {\n\tu64 time;\n\tu64 stamp;\n\tu64 offset;\n};\n\nstruct perf_cgroup_info {\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tint active;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tu64 index;\n};\n\nstruct perf_event_context {\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head pmu_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tint nr_events;\n\tint nr_user;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tstruct perf_event_context *parent_ctx;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tint nr_cgroups;\n\tstruct callback_head callback_head;\n\tlocal_t nr_no_switch_fast;\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint online;\n\tstruct perf_cgroup *cgrp;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_event_pmu_context {\n\tstruct pmu *pmu;\n\tstruct perf_event_context *ctx;\n\tstruct list_head pmu_ctx_entry;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tunsigned int embedded: 1;\n\tunsigned int nr_events;\n\tunsigned int nr_cgroups;\n\tunsigned int nr_freq;\n\tatomic_t refcount;\n\tstruct callback_head callback_head;\n\tint rotate_necessary;\n};\n\nstruct perf_cpu_pmu_context {\n\tstruct perf_event_pmu_context epc;\n\tstruct perf_event_pmu_context *task_epc;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint active_oncpu;\n\tint exclusive;\n\tint pmu_disable_count;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n};\n\nstruct perf_ctx_data {\n\tstruct callback_head callback_head;\n\trefcount_t refcount;\n\tint global;\n\tstruct kmem_cache *ctx_cache;\n\tvoid *data;\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 text_poke: 1;\n\t__u64 build_id: 1;\n\t__u64 inherit_thread: 1;\n\t__u64 remove_on_exec: 1;\n\t__u64 sigtrap: 1;\n\t__u64 defer_callchain: 1;\n\t__u64 defer_output: 1;\n\t__u64 __reserved_1: 24;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\tunion {\n\t\t__u32 aux_action;\n\t\tstruct {\n\t\t\t__u32 aux_start_paused: 1;\n\t\t\t__u32 aux_pause: 1;\n\t\t\t__u32 aux_resume: 1;\n\t\t\t__u32 __reserved_3: 29;\n\t\t};\n\t};\n\t__u64 sig_data;\n\t__u64 config3;\n\t__u64 config4;\n};\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tunsigned int group_generation;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tstruct perf_event_pmu_context *pmu_ctx;\n\tatomic_long_t refcount;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\trefcount_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tunsigned int pending_wakeup;\n\tunsigned int pending_kill;\n\tunsigned int pending_disable;\n\tlong unsigned int pending_addr;\n\tstruct irq_work pending_irq;\n\tstruct irq_work pending_disable_irq;\n\tstruct callback_head pending_task;\n\tunsigned int pending_work;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tu64 id;\n\tatomic64_t lost_samples;\n\tu64 (*clock)(void);\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tstruct bpf_prog *prog;\n\tu64 bpf_cookie;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tstruct ftrace_ops ftrace_ops;\n\tstruct perf_cgroup *cgrp;\n\tvoid *security;\n\tstruct list_head sb_list;\n\tstruct list_head pmu_list;\n\tu32 orig_type;\n};\n\nstruct perf_event_min_heap {\n\tsize_t nr;\n\tsize_t size;\n\tstruct perf_event **data;\n\tstruct perf_event *preallocated[0];\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_user_time_short: 1;\n\t\t\t__u64 cap_____res: 58;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u32 __reserved_1;\n\t__u64 time_cycles;\n\t__u64 time_mask;\n\t__u8 __reserved[928];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct perf_event_security_struct {\n\tu32 sid;\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tu8 build_id[20];\n\tu32 build_id_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n} __attribute__((packed));\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_sf_sde_regs {\n\tunsigned char in_guest: 1;\n\tlong unsigned int reserved: 63;\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_text_poke_event {\n\tconst void *old_bytes;\n\tconst void *new_bytes;\n\tsize_t pad;\n\tu16 old_len;\n\tu16 new_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t} event_id;\n};\n\nstruct perm_datum {\n\tu32 value;\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct pfault_refbk {\n\tu16 refdiagc;\n\tu16 reffcode;\n\tu16 refdwlen;\n\tu16 refversn;\n\tu64 refgaddr;\n\tu64 refselmk;\n\tu64 refcmpmk;\n\tu64 reserved;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct ptdump_range;\n\nstruct ptdump_state {\n\tvoid (*note_page_pte)(struct ptdump_state *, long unsigned int, pte_t);\n\tvoid (*note_page_pmd)(struct ptdump_state *, long unsigned int, pmd_t);\n\tvoid (*note_page_pud)(struct ptdump_state *, long unsigned int, pud_t);\n\tvoid (*note_page_p4d)(struct ptdump_state *, long unsigned int, p4d_t);\n\tvoid (*note_page_pgd)(struct ptdump_state *, long unsigned int, pgd_t);\n\tvoid (*note_page_flush)(struct ptdump_state *);\n\tvoid (*effective_prot_pte)(struct ptdump_state *, pte_t);\n\tvoid (*effective_prot_pmd)(struct ptdump_state *, pmd_t);\n\tvoid (*effective_prot_pud)(struct ptdump_state *, pud_t);\n\tvoid (*effective_prot_p4d)(struct ptdump_state *, p4d_t);\n\tvoid (*effective_prot_pgd)(struct ptdump_state *, pgd_t);\n\tconst struct ptdump_range *range;\n};\n\nstruct pg_state {\n\tstruct ptdump_state ptdump;\n\tstruct seq_file *seq;\n\tint level;\n\tunsigned int current_prot;\n\tbool check_wx;\n\tlong unsigned int wx_pages;\n\tlong unsigned int start_address;\n\tconst struct addr_marker *marker;\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[4];\n\tint node;\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tlong unsigned int present_early_pages;\n\tlong unsigned int cma_pages;\n\tconst char *name;\n\tlong unsigned int nr_isolate_pageblock;\n\tseqlock_t span_seqlock;\n\tint initialized;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[11];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[11];\n\tatomic_long_t vm_numa_event[6];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[9];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[4];\n\tstruct zonelist node_zonelists[2];\n\tint nr_zones;\n\tspinlock_t node_size_lock;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct mutex kswapd_lock;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tlong unsigned int min_unmapped_pages;\n\tlong unsigned int min_slab_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int first_deferred_pfn;\n\tstruct deferred_split deferred_split_queue;\n\tunsigned int nbp_rl_start;\n\tlong unsigned int nbp_rl_nr_cand;\n\tunsigned int nbp_threshold;\n\tunsigned int nbp_th_start;\n\tlong unsigned int nbp_th_nr_cand;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[51];\n\tstruct memory_tier *memtier;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phylink;\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[1];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tlong unsigned int adv_old[2];\n\tlong unsigned int supported_eee[2];\n\tlong unsigned int advertising_eee[2];\n\tlong unsigned int eee_disabled_modes[2];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[1];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct reserved_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct reserved_range *chain;\n};\n\nstruct physmem_range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct physmem_info {\n\tu32 range_count;\n\tu8 info_source;\n\tlong unsigned int usable;\n\tstruct reserved_range reserved[8];\n\tstruct physmem_range online[255];\n\tstruct physmem_range *online_extended;\n};\n\nstruct pib {\n\tchar: 8;\n\tu32 num: 8;\n\tu32 len: 16;\n\tint: 24;\n\tu32 hlen: 8;\n\tlong: 64;\n\tu64 intv;\n\tu8 r[0];\n};\n\nstruct pibdata {\n\tstruct pib *pib;\n\tktime_t expire;\n\tu64 sequence;\n\tsize_t len;\n\tint rc;\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct fs_pin *bacct;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pids_cgroup {\n\tstruct cgroup_subsys_state css;\n\tatomic64_t counter;\n\tatomic64_t limit;\n\tint64_t watermark;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tatomic64_t events[2];\n\tatomic64_t events_local[2];\n};\n\nstruct pimhdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__be16 csum;\n};\n\nstruct pimreghdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__be16 csum;\n\t__be32 flags;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct watch_queue;\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tbool note_loss;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n\tstruct watch_queue *watch_queue;\n};\n\nstruct pipe_wait {\n\tstruct trace_iterator *iter;\n\tint wait_index;\n};\n\nstruct pkcs1pad_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct pkcs1pad_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n};\n\nstruct pkcs1pad_request {\n\tstruct scatterlist in_sg[2];\n\tstruct scatterlist out_sg[1];\n\tuint8_t *in_buf;\n\tuint8_t *out_buf;\n\tstruct akcipher_request child_req;\n};\n\nstruct x509_certificate;\n\nstruct pkcs7_signed_info;\n\nstruct pkcs7_message {\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate *crl;\n\tstruct pkcs7_signed_info *signed_infos;\n\tu8 version;\n\tbool have_authattrs;\n\tenum OID data_type;\n\tsize_t data_len;\n\tsize_t data_hdrlen;\n\tconst void *data;\n};\n\nstruct pkcs7_parse_context {\n\tstruct pkcs7_message *msg;\n\tstruct pkcs7_signed_info *sinfo;\n\tstruct pkcs7_signed_info **ppsinfo;\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate **ppcerts;\n\tlong unsigned int data;\n\tenum OID last_oid;\n\tunsigned int x509_index;\n\tunsigned int sinfo_index;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_skid;\n\tunsigned int raw_skid_size;\n\tbool expect_skid;\n};\n\nstruct pkcs7_signed_info {\n\tstruct pkcs7_signed_info *next;\n\tstruct x509_certificate *signer;\n\tunsigned int index;\n\tbool unsupported_crypto;\n\tbool blacklisted;\n\tconst void *msgdigest;\n\tunsigned int msgdigest_len;\n\tunsigned int authattrs_len;\n\tconst void *authattrs;\n\tlong unsigned int aa_set;\n\ttime64_t signing_time;\n\tstruct public_key_signature *sig;\n};\n\nstruct mfd_cell;\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct property_entry;\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct pm_nl_pernet {\n\tspinlock_t lock;\n\tstruct list_head endp_list;\n\tu8 endpoints;\n\tu8 endp_signal_max;\n\tu8 endp_subflow_max;\n\tu8 endp_laminar_max;\n\tu8 endp_fullmesh_max;\n\tu8 limit_add_addr_accepted;\n\tu8 limit_extra_subflows;\n\tu8 next_id;\n\tlong unsigned int id_bitmap[4];\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n};\n\nstruct pmcw {\n\tu32 intparm;\n\tu32 qf: 1;\n\tu32 w: 1;\n\tu32 isc: 3;\n\tu32 res5: 3;\n\tu32 ena: 1;\n\tu32 lm: 2;\n\tu32 mme: 2;\n\tu32 mp: 1;\n\tu32 tf: 1;\n\tu32 dnv: 1;\n\tu32 dev: 16;\n\tu8 lpm;\n\tu8 pnom;\n\tu8 lpum;\n\tu8 pim;\n\tu16 mbi;\n\tu8 pom;\n\tu8 pam;\n\tu8 chpid[8];\n\tu32 unused1: 8;\n\tu32 st: 3;\n\tu32 unused2: 18;\n\tu32 mbfc: 1;\n\tu32 xmwme: 1;\n\tu32 csense: 1;\n};\n\nstruct pmu {\n\tstruct list_head entry;\n\tspinlock_t events_lock;\n\tstruct list_head events;\n\tstruct module *module;\n\tstruct device *dev;\n\tstruct device *parent;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tunsigned int scope;\n\tstruct perf_cpu_pmu_context **cpu_pmu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tstruct kmem_cache *task_ctx_cache;\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tbool (*filter)(struct pmu *, int);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct policy_file;\n\nstruct policy_data {\n\tstruct policydb *p;\n\tstruct policy_file *fp;\n};\n\nstruct policy_file {\n\tchar *data;\n\tsize_t len;\n};\n\nstruct policy_load_memory {\n\tsize_t len;\n\tvoid *data;\n};\n\nstruct role_datum;\n\nstruct user_datum;\n\nstruct type_datum;\n\nstruct role_allow;\n\nstruct policydb {\n\tint mls_enabled;\n\tstruct symtab symtab[8];\n\tchar **sym_val_to_name[8];\n\tstruct class_datum **class_val_to_struct;\n\tstruct role_datum **role_val_to_struct;\n\tstruct user_datum **user_val_to_struct;\n\tstruct type_datum **type_val_to_struct;\n\tstruct avtab te_avtab;\n\tstruct hashtab role_tr;\n\tstruct ebitmap filename_trans_ttypes;\n\tstruct hashtab filename_trans;\n\tu32 compat_filename_trans_count;\n\tstruct cond_bool_datum **bool_val_to_struct;\n\tstruct avtab te_cond_avtab;\n\tstruct cond_node *cond_list;\n\tu32 cond_list_len;\n\tstruct role_allow *role_allow;\n\tstruct ocontext *ocontexts[9];\n\tstruct genfs *genfs;\n\tstruct hashtab range_tr;\n\tstruct ebitmap *type_attr_map_array;\n\tstruct ebitmap policycaps;\n\tstruct ebitmap permissive_map;\n\tstruct ebitmap neveraudit_map;\n\tsize_t len;\n\tunsigned int policyvers;\n\tunsigned int reject_unknown: 1;\n\tunsigned int allow_unknown: 1;\n\tu16 process_class;\n\tu32 process_trans_perms;\n};\n\nstruct policydb_compat_info {\n\tunsigned int version;\n\tunsigned int sym_num;\n\tunsigned int ocon_num;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[9];\n};\n\nstruct poly1305_state {\n\tunion {\n\t\tu32 h[5];\n\t\tu64 h64[3];\n\t};\n};\n\nstruct poly1305_key {\n\tunion {\n\t\tu32 r[5];\n\t\tu64 r64[3];\n\t};\n};\n\nstruct poly1305_core_key {\n\tstruct poly1305_key key;\n\tstruct poly1305_key precomputed_s;\n};\n\nstruct poly1305_block_state {\n\tstruct poly1305_state h;\n\tunion {\n\t\tstruct poly1305_key opaque_r[1];\n\t\tstruct poly1305_core_key core_r;\n\t};\n};\n\nstruct poly1305_desc_ctx {\n\tu8 buf[16];\n\tunsigned int buflen;\n\tu32 s[4];\n\tstruct poly1305_block_state state;\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct posix_cputimers_work {\n\tstruct callback_head work;\n\tstruct mutex mutex;\n\tunsigned int scheduled;\n};\n\nstruct posix_msg_tree_node {\n\tstruct rb_node rb_node;\n\tstruct list_head msg_list;\n\tint priority;\n};\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 ver: 4;\n\t__u8 type: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n};\n\nstruct preempt_ops {\n\tvoid (*sched_in)(struct preempt_notifier *, int);\n\tvoid (*sched_out)(struct preempt_notifier *, struct task_struct *);\n};\n\nstruct prefix_cacheinfo {\n\t__u32 preferred_time;\n\t__u32 valid_time;\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\tunion {\n\t\t__u8 flags;\n\t\tstruct {\n\t\t\t__u8 onlink: 1;\n\t\t\t__u8 autoconf: 1;\n\t\t\t__u8 routeraddr: 1;\n\t\t\t__u8 preferpd: 1;\n\t\t\t__u8 reserved: 4;\n\t\t};\n\t};\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct prefixmsg {\n\tunsigned char prefix_family;\n\tunsigned char prefix_pad1;\n\tshort unsigned int prefix_pad2;\n\tint prefix_ifindex;\n\tunsigned char prefix_type;\n\tunsigned char prefix_len;\n\tunsigned char prefix_flags;\n\tunsigned char prefix_pad3;\n};\n\nstruct preftree {\n\tstruct rb_root_cached root;\n\tunsigned int count;\n};\n\nstruct preftrees {\n\tstruct preftree direct;\n\tstruct preftree indirect;\n\tstruct preftree indirect_missing_keys;\n};\n\nstruct prelim_ref {\n\tstruct rb_node rbnode;\n\tu64 root_id;\n\tstruct btrfs_key key_for_search;\n\tu8 level;\n\tint count;\n\tstruct extent_inode_elem *inode_list;\n\tu64 parent;\n\tu64 wanted_disk_byte;\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct probe_entry_arg {\n\tstruct fetch_insn *code;\n\tunsigned int size;\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n};\n\nstruct sid_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct ptrace_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t tracer_pid;\n\t__kernel_pid_t tracer_tgid;\n};\n\nstruct proc_event {\n\tenum proc_cn_event what;\n\t__u32 cpu;\n\t__u64 timestamp_ns;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 err;\n\t\t} ack;\n\t\tstruct fork_proc_event fork;\n\t\tstruct exec_proc_event exec;\n\t\tstruct id_proc_event id;\n\t\tstruct sid_proc_event sid;\n\t\tstruct ptrace_proc_event ptrace;\n\t\tstruct comm_proc_event comm;\n\t\tstruct coredump_proc_event coredump;\n\t\tstruct exit_proc_event exit;\n\t} event_data;\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_input {\n\tenum proc_cn_mcast_op mcast_op;\n\tenum proc_cn_event event_type;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tstruct timespec64 val;\n};\n\nstruct proc_xfs_info {\n\tuint64_t flag;\n\tchar *str;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct profile_fgraph_data {\n\tlong long unsigned int calltime;\n\tlong long unsigned int subtime;\n\tlong long unsigned int sleeptime;\n};\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\nstruct prog_frame {\n\tu64 unused[8];\n\tu32 tail_call_cnt;\n\tu32 pad;\n\tu64 r6[10];\n\tu64 backchain;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct prop_handler {\n\tstruct hlist_node node;\n\tconst char *xattr_name;\n\tint (*validate)(const struct btrfs_inode *, const char *, size_t);\n\tint (*apply)(struct btrfs_inode *, const char *, size_t);\n\tconst char * (*extract)(const struct btrfs_inode *);\n\tbool (*ignore)(const struct btrfs_inode *);\n\tint inheritable;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[1];\n\t\t} value;\n\t};\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct psample_group {\n\tstruct list_head list;\n\tstruct net *net;\n\tu32 group_num;\n\tu32 refcount;\n\tu32 seq;\n\tstruct callback_head rcu;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psi_group {};\n\nstruct psw_bits {\n\tchar: 1;\n\tlong unsigned int per: 1;\n\tchar: 3;\n\tlong unsigned int dat: 1;\n\tlong unsigned int io: 1;\n\tlong unsigned int ext: 1;\n\tlong unsigned int key: 4;\n\tchar: 1;\n\tlong unsigned int mcheck: 1;\n\tlong unsigned int wait: 1;\n\tlong unsigned int pstate: 1;\n\tlong unsigned int as: 2;\n\tlong unsigned int cc: 2;\n\tlong unsigned int pm: 4;\n\tlong unsigned int ri: 1;\n\tchar: 6;\n\tlong unsigned int eaba: 2;\n\tlong: 31;\n\tlong unsigned int ia: 64;\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int pt_memcg_data;\n};\n\nstruct ptdump_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct ptff_qto {\n\tlong unsigned int physical_clock;\n\tlong unsigned int tod_offset;\n\tlong unsigned int logical_tod_offset;\n\tlong unsigned int tod_epoch_difference;\n};\n\nstruct ptff_qui {\n\tunsigned int tm: 2;\n\tunsigned int ts: 2;\n\tunsigned int pad_0x04;\n\tlong unsigned int leap_event;\n\tshort int old_leap;\n\tshort int new_leap;\n\tunsigned int pad_0x14;\n\tlong unsigned int prt[5];\n\tlong unsigned int cst[3];\n\tunsigned int skew;\n\tunsigned int pad_0x5c[41];\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_sud_config {\n\t__u64 mode;\n\t__u64 selector;\n\t__u64 offset;\n\t__u64 len;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct pubkey_hdr {\n\tuint8_t version;\n\tuint32_t timestamp;\n\tuint8_t algo;\n\tuint8_t nmpi;\n\tchar mpi[0];\n} __attribute__((packed));\n\nstruct public_key {\n\tvoid *key;\n\tu32 keylen;\n\tenum OID algo;\n\tvoid *params;\n\tu32 paramlen;\n\tbool key_is_private;\n\tconst char *id_type;\n\tconst char *pkey_algo;\n\tlong unsigned int key_eflags;\n};\n\nstruct public_key_signature {\n\tstruct asymmetric_key_id *auth_ids[3];\n\tu8 *s;\n\tu8 *m;\n\tu32 s_size;\n\tu32 m_size;\n\tbool m_free;\n\tbool algo_takes_data;\n\tconst char *pkey_algo;\n\tconst char *hash_algo;\n\tconst char *encoding;\n};\n\nstruct qaob {\n\tu64 res0[6];\n\tu8 res1;\n\tu8 res2;\n\tu8 res3;\n\tu8 aorc;\n\tu8 flags;\n\tu16 cbtbs;\n\tu8 sb_count;\n\tdma64_t sba[16];\n\tu16 dcount[16];\n\tu64 user0;\n\tu64 res4[2];\n\tu8 user1[16];\n} __attribute__((packed));\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qdesfmt0 {\n\tdma64_t sliba;\n\tdma64_t sla;\n\tdma64_t slsba;\n\tint: 32;\n\tu32 akey: 4;\n\tu32 bkey: 4;\n\tu32 ckey: 4;\n\tu32 dkey: 4;\n};\n\nstruct qdio_buffer_element {\n\tu8 eflags;\n\tu8 res1;\n\tu8 scount;\n\tu8 sflags;\n\tu32 length;\n\tdma64_t addr;\n};\n\nstruct qdio_buffer {\n\tstruct qdio_buffer_element element[16];\n};\n\nstruct qdio_dbf_entry {\n\tchar dbf_name[20];\n\tdebug_info_t *dbf_info;\n\tstruct list_head dbf_list;\n};\n\nstruct qdio_dev_perf_stat {\n\tunsigned int adapter_int;\n\tunsigned int qdio_int;\n\tunsigned int siga_read;\n\tunsigned int siga_write;\n\tunsigned int siga_sync;\n\tunsigned int inbound_call;\n\tunsigned int stop_polling;\n\tunsigned int inbound_queue_full;\n\tunsigned int outbound_call;\n\tunsigned int outbound_queue_full;\n\tunsigned int fast_requeue;\n\tunsigned int target_full;\n\tunsigned int eqbs;\n\tunsigned int eqbs_partial;\n\tunsigned int sqbs;\n\tunsigned int sqbs_partial;\n\tunsigned int int_discarded;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef void qdio_handler_t(struct ccw_device *, unsigned int, int, int, int, long unsigned int);\n\nstruct qdio_initialize {\n\tunsigned char q_format;\n\tunsigned char qdr_ac;\n\tunsigned int qib_param_field_format;\n\tunsigned char *qib_param_field;\n\tunsigned char qib_rflags;\n\tunsigned int no_input_qs;\n\tunsigned int no_output_qs;\n\tqdio_handler_t *input_handler;\n\tqdio_handler_t *output_handler;\n\tvoid (*irq_poll)(struct ccw_device *, long unsigned int);\n\tlong unsigned int int_parm;\n\tstruct qdio_buffer ***input_sbal_addr_array;\n\tstruct qdio_buffer ***output_sbal_addr_array;\n};\n\nstruct qdio_input_q {\n\tunsigned int batch_start;\n\tunsigned int batch_count;\n};\n\nstruct qib {\n\tu32 qfmt: 8;\n\tu32 pfmt: 8;\n\tu32 rflags: 8;\n\tu32 ac: 8;\n\tu64 isliba;\n\tu64 osliba;\n\tlong: 64;\n\tu8 ebcnam[8];\n\tu8 res[88];\n\tu8 parm[128];\n};\n\nstruct qdr;\n\nstruct qdio_q;\n\nstruct qdio_irq {\n\tstruct qib qib;\n\tu32 *dsci;\n\tstruct ccw_device *cdev;\n\tstruct list_head entry;\n\tstruct dentry *debugfs_dev;\n\tu64 last_data_irq_time;\n\tlong unsigned int int_parm;\n\tstruct subchannel_id schid;\n\tlong unsigned int sch_token;\n\tenum qdio_irq_states state;\n\tu8 qdioac1;\n\tint nr_input_qs;\n\tint nr_output_qs;\n\tstruct ccw1 *ccw;\n\tstruct qdio_ssqd_desc ssqd_desc;\n\tvoid (*orig_handler)(struct ccw_device *, long unsigned int, struct irb *);\n\tqdio_handler_t *error_handler;\n\tint perf_stat_enabled;\n\tstruct qdr *qdr;\n\tlong unsigned int chsc_page;\n\tstruct qdio_q *input_qs[4];\n\tstruct qdio_q *output_qs[4];\n\tunsigned int max_input_qs;\n\tunsigned int max_output_qs;\n\tvoid (*irq_poll)(struct ccw_device *, long unsigned int);\n\tlong unsigned int poll_state;\n\tdebug_info_t *debug_area;\n\tstruct mutex setup_mutex;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct qdio_dev_perf_stat perf_stat;\n};\n\nstruct qdio_output_q {};\n\nstruct slsb {\n\tu8 val[128];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct qdio_queue_perf_stat {\n\tunsigned int nr_sbals[8];\n\tunsigned int nr_sbal_error;\n\tunsigned int nr_sbal_nop;\n\tunsigned int nr_sbal_total;\n};\n\nstruct sl;\n\nstruct slib;\n\nstruct qdio_q {\n\tstruct slsb slsb;\n\tunion {\n\t\tstruct qdio_input_q in;\n\t\tstruct qdio_output_q out;\n\t} u;\n\tint first_to_check;\n\tatomic_t nr_buf_used;\n\tu64 timestamp;\n\tstruct qdio_queue_perf_stat q_stats;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct qdio_buffer *sbal[128];\n\tint nr;\n\tint mask;\n\tint is_input_q;\n\tqdio_handler_t *handler;\n\tstruct qdio_irq *irq_ptr;\n\tvoid *sl_page;\n\tstruct sl *sl;\n\tstruct slib *slib;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct qdisc_dump_args {\n\tstruct qdisc_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct qdisc_rate_table {\n\tstruct tc_ratespec rate;\n\tu32 data[256];\n\tstruct qdisc_rate_table *next;\n\tint refcnt;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_watchdog {\n\tstruct hrtimer timer;\n\tstruct Qdisc *qdisc;\n};\n\nstruct qdr {\n\tu32 qfmt: 8;\n\tshort: 8;\n\tchar: 8;\n\tu32 ac: 8;\n\tchar: 8;\n\tu32 iqdcnt: 8;\n\tchar: 8;\n\tu32 oqdcnt: 8;\n\tchar: 8;\n\tu32 iqdsz: 8;\n\tchar: 8;\n\tu32 oqdsz: 8;\n\tu32 res[9];\n\tdma64_t qiba;\n\tint: 32;\n\tu32 qkey: 4;\n\tstruct qdesfmt0 qdf0[126];\n};\n\nstruct qeth_ipacmd_addr_change_entry {\n\tstruct net_if_token token;\n\tstruct mac_addr_lnid addr_lnid;\n\t__u8 change_code;\n\t__u8 reserved1;\n\t__u16 reserved2;\n};\n\nstruct qeth_ipacmd_addr_change {\n\t__u8 lost_event_mask;\n\t__u8 reserved;\n\t__u16 num_entries;\n\tstruct qeth_ipacmd_addr_change_entry entry[0];\n};\n\nstruct qeth_card;\n\nstruct qeth_addr_change_data {\n\tstruct delayed_work dwork;\n\tstruct qeth_card *card;\n\tstruct qeth_ipacmd_addr_change ac_event;\n};\n\nstruct qeth_arp_cache_entry {\n\t__u8 macaddr[6];\n\t__u8 reserved1[2];\n\t__u8 ipaddr[16];\n\t__u8 reserved2[32];\n};\n\nstruct qeth_arp_entrytype {\n\t__u8 mac;\n\t__u8 ip;\n};\n\nstruct qeth_arp_qi_entry5 {\n\t__u8 media_specific[32];\n\tstruct qeth_arp_entrytype type;\n\t__u8 ipaddr[4];\n};\n\nstruct qeth_arp_query_data {\n\t__u16 request_bits;\n\t__u16 reply_bits;\n\t__u32 no_entries;\n\tchar data;\n} __attribute__((packed));\n\nstruct qeth_arp_query_info {\n\t__u32 udata_len;\n\t__u16 mask_bits;\n\t__u32 udata_offset;\n\t__u32 no_entries;\n\tchar *udata;\n};\n\nstruct qeth_bridge_state_data {\n\tstruct work_struct worker;\n\tstruct qeth_card *card;\n\tu8 role;\n\tu8 state;\n};\n\nstruct qeth_buffer_pool_entry {\n\tstruct list_head list;\n\tstruct list_head init_list;\n\tstruct page *elements[16];\n};\n\nstruct qeth_cmd_buffer;\n\nstruct qeth_channel {\n\tstruct ccw_device *ccwdev;\n\tstruct qeth_cmd_buffer *active_cmd;\n\tenum qeth_channel_states state;\n};\n\nstruct qeth_card_stats {\n\tu64 rx_bufs;\n\tu64 rx_skb_csum;\n\tu64 rx_sg_skbs;\n\tu64 rx_sg_frags;\n\tu64 rx_sg_alloc_page;\n\tu64 rx_dropped_nomem;\n\tu64 rx_dropped_notsupp;\n\tu64 rx_dropped_runt;\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_multicast;\n\tu64 rx_length_errors;\n\tu64 rx_frame_errors;\n\tu64 rx_fifo_errors;\n};\n\nstruct qeth_card_blkt {\n\tint time_total;\n\tint inter_packet;\n\tint inter_packet_jumbo;\n};\n\nstruct qeth_link_info {\n\tu32 speed;\n\tu8 duplex;\n\tu8 port;\n\tenum qeth_link_mode link_mode;\n};\n\nstruct qeth_card_info {\n\tshort unsigned int unit_addr2;\n\tshort unsigned int cula;\n\t__u16 func_level;\n\tchar mcl_level[5];\n\tu16 ddev_devno;\n\tu8 cssid;\n\tu8 iid;\n\tu8 ssid;\n\tu8 chpid;\n\tu16 chid;\n\tu8 ids_valid: 1;\n\tu8 dev_addr_is_registered: 1;\n\tu8 promisc_mode: 1;\n\tu8 use_v1_blkt: 1;\n\tu8 is_vm_nic: 1;\n\tu8 has_lp2lp_cso_v6;\n\tu8 has_lp2lp_cso_v4;\n\tenum qeth_pnso_mode pnso_mode;\n\tenum qeth_card_types type;\n\tenum qeth_link_types link_type;\n\tint broadcast_capable;\n\tbool layer_enforced;\n\tstruct qeth_card_blkt blkt;\n\t__u32 diagass_support;\n\t__u32 hwtrap;\n\tstruct qeth_link_info link_info;\n};\n\nstruct qeth_token {\n\t__u32 issuer_rm_w;\n\t__u32 issuer_rm_r;\n\t__u32 cm_filter_w;\n\t__u32 cm_filter_r;\n\t__u32 cm_connection_w;\n\t__u32 cm_connection_r;\n\t__u32 ulp_filter_w;\n\t__u32 ulp_filter_r;\n\t__u32 ulp_connection_w;\n\t__u32 ulp_connection_r;\n};\n\nstruct qeth_seqno {\n\t__u32 trans_hdr;\n\t__u32 pdu_hdr;\n\t__u32 pdu_hdr_ack;\n\t__u16 ipa;\n};\n\nstruct qeth_ipa_caps {\n\tu32 supported;\n\tu32 enabled;\n};\n\nstruct qeth_routing_info {\n\tenum qeth_routing_types type;\n};\n\nstruct qeth_sbp_info {\n\t__u32 supported_funcs;\n\tenum qeth_sbp_roles role;\n\t__u32 hostnotification: 1;\n\t__u32 reflect_promisc: 1;\n\t__u32 reflect_promisc_primary: 1;\n};\n\nstruct qeth_vnicc_info {\n\tu32 sup_chars;\n\tu32 cur_chars;\n\tu32 set_char_sup;\n\tu32 getset_timeout_sup;\n\tu32 learning_timeout;\n\tu32 wanted_chars;\n\tbool rx_bcast_enabled;\n};\n\nstruct qeth_card_options {\n\tstruct qeth_ipa_caps ipa4;\n\tstruct qeth_ipa_caps ipa6;\n\tstruct qeth_routing_info route4;\n\tstruct qeth_routing_info route6;\n\tstruct qeth_ipa_caps adp;\n\tstruct qeth_sbp_info sbp;\n\tstruct qeth_vnicc_info vnicc;\n\tenum qeth_discipline_id layer;\n\tenum qeth_ipa_isolation_modes isolation;\n\tint sniffer;\n\tenum qeth_cq cq;\n\tchar hsuid[9];\n};\n\nstruct qeth_ipato {\n\tbool enabled;\n\tbool invert4;\n\tbool invert6;\n\tstruct list_head entries;\n};\n\nstruct qeth_qdio_buffer_pool {\n\tstruct list_head entry_list;\n\tint buf_count;\n};\n\nstruct qeth_qdio_q;\n\nstruct qeth_qdio_out_q;\n\nstruct qeth_qdio_info {\n\tatomic_t state;\n\tstruct qeth_qdio_q *in_q;\n\tstruct qeth_qdio_q *c_q;\n\tstruct qeth_qdio_buffer_pool in_buf_pool;\n\tstruct qeth_qdio_buffer_pool init_pool;\n\tint in_buf_size;\n\tunsigned int no_out_queues;\n\tstruct qeth_qdio_out_q *out_qs[4];\n\tint do_prio_queueing;\n\tint default_out_queue;\n};\n\nstruct service_level {\n\tstruct list_head list;\n\tvoid (*seq_print)(struct seq_file *, struct service_level *);\n};\n\nstruct qeth_rx {\n\tint b_count;\n\tint b_index;\n\tu8 buf_element;\n\tint e_offset;\n\tint qdio_err;\n\tu8 bufs_refill;\n};\n\nstruct qeth_discipline;\n\nstruct qeth_card {\n\tenum qeth_card_states state;\n\tspinlock_t lock;\n\tstruct ccwgroup_device *gdev;\n\tstruct qeth_cmd_buffer *read_cmd;\n\tstruct qeth_channel read;\n\tstruct qeth_channel write;\n\tstruct qeth_channel data;\n\tstruct net_device *dev;\n\tstruct dentry *debugfs;\n\tstruct qeth_card_stats stats;\n\tstruct qeth_card_info info;\n\tstruct qeth_token token;\n\tstruct qeth_seqno seqno;\n\tstruct qeth_card_options options;\n\tstruct workqueue_struct *event_wq;\n\tstruct workqueue_struct *cmd_wq;\n\twait_queue_head_t wait_q;\n\tstruct mutex ip_lock;\n\tstruct hlist_head ip_htable[16];\n\tstruct qeth_ipato ipato;\n\tstruct hlist_head local_addrs4[16];\n\tstruct hlist_head local_addrs6[16];\n\tspinlock_t local_addrs4_lock;\n\tspinlock_t local_addrs6_lock;\n\tstruct hlist_head rx_mode_addrs[16];\n\tstruct work_struct rx_mode_work;\n\tstruct work_struct kernel_thread_starter;\n\tspinlock_t thread_mask_lock;\n\tlong unsigned int thread_start_mask;\n\tlong unsigned int thread_allowed_mask;\n\tlong unsigned int thread_running_mask;\n\tstruct list_head cmd_waiter_list;\n\tstruct qeth_qdio_info qdio;\n\tint read_or_write_problem;\n\tconst struct qeth_discipline *discipline;\n\tatomic_t force_alloc_skb;\n\tstruct service_level qeth_service_level;\n\tstruct qdio_ssqd_desc ssqd;\n\tdebug_info_t *debug;\n\tstruct mutex sbp_lock;\n\tstruct mutex conf_mutex;\n\tstruct mutex discipline_mutex;\n\tstruct napi_struct napi;\n\tstruct qeth_rx rx;\n\tstruct delayed_work buffer_reclaim_work;\n};\n\nstruct qeth_change_addr {\n\tu32 cmd;\n\tu32 addr_size;\n\tu32 no_macs;\n\tu8 addr[6];\n};\n\nstruct qeth_reply {\n\tint (*callback)(struct qeth_card *, struct qeth_reply *, long unsigned int);\n\tvoid *param;\n};\n\nstruct qeth_cmd_buffer {\n\tstruct list_head list_entry;\n\tstruct completion done;\n\tspinlock_t lock;\n\tunsigned int length;\n\trefcount_t ref_count;\n\tstruct qeth_channel *channel;\n\tstruct qeth_reply reply;\n\tlong int timeout;\n\tunsigned char *data;\n\tvoid (*finalize)(struct qeth_card *, struct qeth_cmd_buffer *);\n\tbool (*match)(struct qeth_cmd_buffer *, struct qeth_cmd_buffer *);\n\tvoid (*callback)(struct qeth_card *, struct qeth_cmd_buffer *, unsigned int);\n\tint rc;\n};\n\nstruct qeth_create_destroy_address {\n\tu8 mac_addr[6];\n\tu16 uid;\n};\n\nstruct qeth_dbf_entry {\n\tchar dbf_name[20];\n\tdebug_info_t *dbf_info;\n\tstruct list_head dbf_list;\n};\n\nstruct qeth_dbf_info {\n\tchar name[64];\n\tint pages;\n\tint areas;\n\tint len;\n\tint level;\n\tstruct debug_view *view;\n\tdebug_info_t *id;\n};\n\nstruct qeth_ipa_cmd;\n\nstruct qeth_discipline {\n\tint (*setup)(struct ccwgroup_device *);\n\tvoid (*remove)(struct ccwgroup_device *);\n\tint (*set_online)(struct qeth_card *, bool);\n\tvoid (*set_offline)(struct qeth_card *);\n\tint (*control_event_handler)(struct qeth_card *, struct qeth_ipa_cmd *);\n};\n\nstruct qeth_hdr_layer2 {\n\t__u8 id;\n\t__u8 flags[3];\n\t__u8 port_no;\n\t__u8 hdr_length;\n\t__u16 pkt_length;\n\t__u16 seq_no;\n\t__u16 vlan_id;\n\t__u32 reserved;\n\t__u8 reserved2[16];\n};\n\nstruct rx {\n\tu8 res1[2];\n\tu8 src_mac[6];\n\tu8 res2[4];\n\tu16 vlan_id;\n\tu8 res3[2];\n};\n\nstruct qeth_hdr_layer3 {\n\t__u8 id;\n\t__u8 flags;\n\t__u16 inbound_checksum;\n\t__u32 token;\n\t__u16 length;\n\t__u8 vlan_prio;\n\t__u8 ext_flags;\n\t__u16 vlan_id;\n\t__u16 frame_offset;\n\tunion {\n\t\tstruct in6_addr addr;\n\t\tstruct rx rx;\n\t} next_hop;\n};\n\nstruct qeth_hdr {\n\tunion {\n\t\tstruct qeth_hdr_layer2 l2;\n\t\tstruct qeth_hdr_layer3 l3;\n\t} hdr;\n};\n\nstruct qeth_hdr_ext_tso {\n\t__u16 hdr_tot_len;\n\t__u8 imb_hdr_no;\n\t__u8 reserved;\n\t__u8 hdr_type;\n\t__u8 hdr_version;\n\t__u16 hdr_len;\n\t__u32 payload_len;\n\t__u16 mss;\n\t__u16 dg_hdr_len;\n\t__u8 padding[16];\n};\n\nstruct qeth_hdr_tso {\n\tstruct qeth_hdr hdr;\n\tstruct qeth_hdr_ext_tso ext;\n};\n\nstruct qeth_ipacmd_hdr {\n\t__u8 command;\n\t__u8 initiator;\n\t__u16 seqno;\n\t__u16 return_code;\n\t__u8 adapter_type;\n\t__u8 rel_adapter_no;\n\t__u8 prim_version_no;\n\t__u8 param_count;\n\t__u16 prot_version;\n\tstruct qeth_ipa_caps assists;\n};\n\nstruct qeth_ipacmd_setdelip4 {\n\t__be32 addr;\n\t__be32 mask;\n\t__u32 flags;\n};\n\nstruct qeth_ipacmd_setdelip6 {\n\tstruct in6_addr addr;\n\tstruct in6_addr prefix;\n\t__u32 flags;\n};\n\nstruct qeth_ipacmd_setdelipm {\n\t__u8 mac[6];\n\t__u8 padding[2];\n\tstruct in6_addr ip;\n};\n\nstruct qeth_ipacmd_setassparms_hdr {\n\t__u16 length;\n\t__u16 command_code;\n\t__u16 return_code;\n\t__u8 number_of_replies;\n\t__u8 seq_no;\n};\n\nstruct qeth_tso_start_data {\n\tu32 mss;\n\tu32 supported;\n};\n\nstruct qeth_ipacmd_setassparms {\n\tu32 assist_no;\n\tstruct qeth_ipacmd_setassparms_hdr hdr;\n\tunion {\n\t\t__u32 flags_32bit;\n\t\tstruct qeth_ipa_caps caps;\n\t\tstruct qeth_arp_cache_entry arp_entry;\n\t\tstruct qeth_arp_query_data query_arp;\n\t\tstruct qeth_tso_start_data tso;\n\t} data;\n};\n\nstruct qeth_ipacmd_layer2setdelmac {\n\t__u32 mac_length;\n\t__u8 mac[6];\n} __attribute__((packed));\n\nstruct qeth_ipacmd_layer2setdelvlan {\n\t__u16 vlan_id;\n};\n\nstruct qeth_ipacmd_setadpparms_hdr {\n\tu16 cmdlength;\n\tu16 reserved2;\n\tu32 command_code;\n\tu16 return_code;\n\tu8 used_total;\n\tu8 seq_no;\n\tu8 flags;\n\tu8 reserved3[3];\n};\n\nstruct qeth_query_cmds_supp {\n\t__u32 no_lantypes_supp;\n\t__u8 lan_type;\n\t__u8 reserved1[3];\n\t__u32 supported_cmds;\n\t__u8 reserved2[8];\n};\n\nstruct qeth_snmp_cmd {\n\t__u8 token[16];\n\t__u32 request;\n\t__u32 interface;\n\t__u32 returncode;\n\t__u32 firmwarelevel;\n\t__u32 seqno;\n\t__u8 data;\n} __attribute__((packed));\n\nstruct qeth_set_access_ctrl {\n\t__u32 subcmd_code;\n\t__u8 reserved[8];\n};\n\nstruct qeth_query_oat_physical_if {\n\tu8 res_head[33];\n\tu8 speed_duplex;\n\tu8 media_type;\n\tu8 res_tail[29];\n};\n\nstruct qeth_query_oat_reply {\n\tu16 type;\n\tu16 length;\n\tu16 version;\n\tu8 res[10];\n\tstruct qeth_query_oat_physical_if phys_if;\n};\n\nstruct qeth_query_oat {\n\tu32 subcmd_code;\n\tu8 reserved[12];\n\tstruct qeth_query_oat_reply reply[0];\n};\n\nstruct qeth_query_card_info {\n\t__u8 card_type;\n\t__u8 reserved1;\n\t__u16 port_mode;\n\t__u32 port_speed;\n\t__u32 reserved2;\n};\n\nstruct qeth_query_switch_attributes {\n\t__u8 version;\n\t__u8 reserved1;\n\t__u16 reserved2;\n\t__u32 capabilities;\n\t__u32 settings;\n\t__u8 reserved3[8];\n};\n\nstruct qeth_ipacmd_setadpparms {\n\tstruct qeth_ipa_caps hw_cmds;\n\tstruct qeth_ipacmd_setadpparms_hdr hdr;\n\tunion {\n\t\tstruct qeth_query_cmds_supp query_cmds_supp;\n\t\tstruct qeth_change_addr change_addr;\n\t\tstruct qeth_snmp_cmd snmp;\n\t\tstruct qeth_set_access_ctrl set_access_ctrl;\n\t\tstruct qeth_query_oat query_oat;\n\t\tstruct qeth_query_card_info card_info;\n\t\tstruct qeth_query_switch_attributes query_switch_attributes;\n\t\t__u32 mode;\n\t} data;\n};\n\nstruct qeth_set_routing {\n\t__u8 type;\n};\n\nstruct qeth_ipacmd_diagass {\n\t__u32 host_tod2;\n\tlong: 0;\n\t__u16 subcmd_len;\n\t__u32 subcmd;\n\t__u8 type;\n\t__u8 action;\n\t__u16 options;\n\t__u32 ext;\n\t__u8 cdata[64];\n};\n\nstruct qeth_ipacmd_sbp_hdr {\n\t__u16 cmdlength;\n\t__u16 reserved1;\n\t__u32 command_code;\n\t__u16 return_code;\n\t__u8 used_total;\n\t__u8 seq_no;\n\t__u32 reserved2;\n};\n\nstruct qeth_sbp_query_cmds_supp {\n\t__u32 supported_cmds;\n\t__u32 reserved;\n};\n\nstruct qeth_sbp_set_primary {\n\tstruct net_if_token token;\n};\n\nstruct qeth_sbp_port_entry {\n\t__u8 role;\n\t__u8 state;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\tstruct net_if_token token;\n};\n\nstruct qeth_sbp_port_data {\n\t__u8 primary_bp_supported;\n\t__u8 secondary_bp_supported;\n\t__u8 num_entries;\n\t__u8 entry_length;\n\tstruct qeth_sbp_port_entry entry[0];\n};\n\nstruct qeth_ipacmd_setbridgeport {\n\tstruct qeth_ipa_caps sbp_cmds;\n\tstruct qeth_ipacmd_sbp_hdr hdr;\n\tunion {\n\t\tstruct qeth_sbp_query_cmds_supp query_cmds_supp;\n\t\tstruct qeth_sbp_set_primary set_primary;\n\t\tstruct qeth_sbp_port_data port_data;\n\t} data;\n};\n\nstruct qeth_ipacmd_vnicc_hdr {\n\tu16 data_length;\n\tu16 reserved;\n\tu32 sub_command;\n};\n\nstruct qeth_vnicc_query_cmds {\n\tu32 vnic_char;\n\tu32 sup_cmds;\n};\n\nstruct qeth_vnicc_set_char {\n\tu32 vnic_char;\n};\n\nstruct qeth_vnicc_getset_timeout {\n\tu32 vnic_char;\n\tu32 timeout;\n};\n\nstruct qeth_ipacmd_vnicc {\n\tstruct qeth_ipa_caps vnicc_cmds;\n\tstruct qeth_ipacmd_vnicc_hdr hdr;\n\tunion {\n\t\tstruct qeth_vnicc_query_cmds query_cmds;\n\t\tstruct qeth_vnicc_set_char set_char;\n\t\tstruct qeth_vnicc_getset_timeout getset_timeout;\n\t} data;\n};\n\nstruct qeth_ipacmd_local_addr4 {\n\t__be32 addr;\n\tu32 flags;\n};\n\nstruct qeth_ipacmd_local_addrs4 {\n\tu32 count;\n\tu32 addr_length;\n\tstruct qeth_ipacmd_local_addr4 addrs[0];\n};\n\nstruct qeth_ipacmd_local_addr6 {\n\tstruct in6_addr addr;\n\tu32 flags;\n};\n\nstruct qeth_ipacmd_local_addrs6 {\n\tu32 count;\n\tu32 addr_length;\n\tstruct qeth_ipacmd_local_addr6 addrs[0];\n};\n\nstruct qeth_ipa_cmd {\n\tstruct qeth_ipacmd_hdr hdr;\n\tunion {\n\t\tstruct qeth_ipacmd_setdelip4 setdelip4;\n\t\tstruct qeth_ipacmd_setdelip6 setdelip6;\n\t\tstruct qeth_ipacmd_setdelipm setdelipm;\n\t\tstruct qeth_ipacmd_setassparms setassparms;\n\t\tstruct qeth_ipacmd_layer2setdelmac setdelmac;\n\t\tstruct qeth_ipacmd_layer2setdelvlan setdelvlan;\n\t\tstruct qeth_create_destroy_address create_destroy_addr;\n\t\tstruct qeth_ipacmd_setadpparms setadapterparms;\n\t\tstruct qeth_set_routing setrtg;\n\t\tstruct qeth_ipacmd_diagass diagass;\n\t\tstruct qeth_ipacmd_setbridgeport sbp;\n\t\tstruct qeth_ipacmd_addr_change addrchange;\n\t\tstruct qeth_ipacmd_vnicc vnicc;\n\t\tstruct qeth_ipacmd_local_addrs4 local_addrs4;\n\t\tstruct qeth_ipacmd_local_addrs6 local_addrs6;\n\t} data;\n};\n\nstruct qeth_ipaddr {\n\tstruct hlist_node hnode;\n\tenum qeth_ip_types type;\n\tu8 is_multicast: 1;\n\tu8 disp_flag: 2;\n\tu8 ipato: 1;\n\tint ref_counter;\n\tenum qeth_prot_versions proto;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 addr;\n\t\t\t__be32 mask;\n\t\t} a4;\n\t\tstruct {\n\t\t\tstruct in6_addr addr;\n\t\t\tunsigned int pfxlen;\n\t\t} a6;\n\t} u;\n};\n\nstruct qeth_ipato_entry {\n\tstruct list_head entry;\n\tenum qeth_prot_versions proto;\n\tchar addr[16];\n\tunsigned int mask_bits;\n};\n\nstruct qeth_l2_br2dev_event_work {\n\tstruct work_struct work;\n\tstruct net_device *br_dev;\n\tstruct net_device *lsync_dev;\n\tstruct net_device *dst_dev;\n\tlong unsigned int event;\n\tunsigned char addr[6];\n};\n\nstruct qeth_l3_ip_event_work {\n\tstruct work_struct work;\n\tstruct qeth_card *card;\n\tstruct qeth_ipaddr addr;\n};\n\nstruct qeth_local_addr {\n\tstruct hlist_node hnode;\n\tstruct callback_head rcu;\n\tstruct in6_addr addr;\n};\n\nstruct qeth_mac {\n\tu8 mac_addr[6];\n\tu8 disp_flag: 2;\n\tstruct hlist_node hnode;\n};\n\nstruct qeth_node_desc {\n\tstruct node_descriptor nd1;\n\tstruct node_descriptor nd2;\n\tstruct node_descriptor nd3;\n};\n\nstruct qeth_out_q_stats {\n\tu64 bufs;\n\tu64 bufs_pack;\n\tu64 buf_elements;\n\tu64 skbs_pack;\n\tu64 skbs_sg;\n\tu64 skbs_csum;\n\tu64 skbs_tso;\n\tu64 skbs_linearized;\n\tu64 skbs_linearized_fail;\n\tu64 tso_bytes;\n\tu64 packing_mode_switch;\n\tu64 stopped;\n\tu64 doorbell;\n\tu64 coal_frames;\n\tu64 completion_irq;\n\tu64 completion_yield;\n\tu64 completion_timer;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n\tu64 tx_dropped;\n};\n\nstruct qeth_priv {\n\tunsigned int rx_copybreak;\n\tunsigned int tx_wanted_queues;\n\tu32 brport_hw_features;\n\tu32 brport_features;\n};\n\nstruct qeth_qaob_priv1 {\n\tunsigned int state;\n\tu8 queue_no;\n};\n\nstruct qeth_qdio_buffer {\n\tstruct qdio_buffer *buffer;\n\tstruct qeth_buffer_pool_entry *pool_entry;\n\tstruct sk_buff *rx_skb;\n};\n\nstruct qeth_qdio_out_buffer {\n\tstruct qdio_buffer *buffer;\n\tatomic_t state;\n\tint next_element_to_fill;\n\tunsigned int frames;\n\tunsigned int bytes;\n\tstruct sk_buff_head skb_list;\n\tlong unsigned int from_kmem_cache[1];\n\tstruct list_head list_entry;\n\tstruct qaob *aob;\n};\n\nstruct qeth_qdio_out_q {\n\tstruct qdio_buffer *qdio_bufs[128];\n\tstruct qeth_qdio_out_buffer *bufs[128];\n\tstruct list_head pending_bufs;\n\tstruct qeth_out_q_stats stats;\n\tspinlock_t lock;\n\tunsigned int priority;\n\tu8 next_buf_to_fill;\n\tu8 max_elements;\n\tu8 queue_no;\n\tu8 do_pack;\n\tstruct qeth_card *card;\n\tatomic_t used_buffers;\n\tatomic_t set_pci_flags_count;\n\tstruct napi_struct napi;\n\tstruct timer_list timer;\n\tstruct qeth_hdr *prev_hdr;\n\tunsigned int coalesced_frames;\n\tu8 bulk_start;\n\tu8 bulk_count;\n\tu8 bulk_max;\n\tunsigned int coalesce_usecs;\n\tunsigned int max_coalesced_frames;\n\tunsigned int rescan_usecs;\n};\n\nstruct qeth_qdio_q {\n\tstruct qdio_buffer *qdio_bufs[128];\n\tstruct qeth_qdio_buffer bufs[128];\n\tint next_buf_to_init;\n};\n\nstruct qeth_qib_parms {\n\tchar pcit_magic[4];\n\tu32 pcit_a;\n\tu32 pcit_b;\n\tu32 pcit_c;\n\tchar blkt_magic[4];\n\tu32 blkt_total;\n\tu32 blkt_inter_packet;\n\tu32 blkt_inter_packet_jumbo;\n\tchar pque_magic[4];\n\tu8 pque_order;\n\tu8 pque_units;\n\tu16 reserved;\n\tu32 pque_priority[4];\n};\n\nstruct qeth_qoat_priv {\n\t__u32 buffer_len;\n\t__u32 response_len;\n\tchar *buffer;\n};\n\nstruct qeth_query_oat_data {\n\t__u32 command;\n\t__u32 buffer_len;\n\t__u32 response_len;\n\t__u64 ptr;\n};\n\nstruct qeth_snmp_ureq_hdr {\n\t__u32 data_len;\n\t__u32 req_len;\n\t__u32 reserved1;\n\t__u32 reserved2;\n};\n\nstruct qeth_snmp_ureq {\n\tstruct qeth_snmp_ureq_hdr hdr;\n\tstruct qeth_snmp_cmd cmd;\n} __attribute__((packed));\n\nstruct qeth_stats {\n\tchar name[32];\n\tunsigned int offset;\n};\n\nstruct qeth_switch_info {\n\t__u32 capabilities;\n\t__u32 settings;\n};\n\nstruct qeth_trap_id {\n\t__u16 lparnr;\n\tchar vmname[8];\n\t__u8 chpid;\n\t__u8 ssid;\n\t__u16 devno;\n};\n\nstruct qin64 {\n\tchar qopcode;\n\tchar rsrv1[3];\n\tchar qrcode;\n\tchar rsrv2[3];\n\tchar qname[8];\n\tunsigned int qoutptr;\n\tshort int qoutlen;\n};\n\nstruct qout64 {\n\tlong unsigned int segstart;\n\tlong unsigned int segend;\n\tint segcnt;\n\tint segrcnt;\n\tstruct qrange range[6];\n};\n\nstruct qpaci_info_block {\n\tu64 header;\n\tstruct {\n\t\tchar: 8;\n\t\tu64 num_cc: 8;\n\t\tshort: 9;\n\t\tu64 num_nnpa: 7;\n\t};\n};\n\nstruct queue_pages {\n\tstruct list_head *pagelist;\n\tlong unsigned int flags;\n\tnodemask_t *nmask;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct vm_area_struct *first;\n\tstruct folio *large;\n\tlong int nr_failed;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_id {\n\tstruct rb_node node;\n\tqid_t id;\n\tqsize_t bhardlimit;\n\tqsize_t bsoftlimit;\n\tqsize_t ihardlimit;\n\tqsize_t isoftlimit;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n};\n\nstruct quota_module_name {\n\tint qm_fmt_id;\n\tchar *qm_mod_name;\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct ra_msg {\n\tstruct icmp6hdr icmph;\n\t__be32 reachable_time;\n\t__be32 retrans_timer;\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct raid56_bio_trace_info {\n\tu64 devid;\n\tu32 offset;\n\tu8 stripe_nr;\n};\n\nstruct raid6_calls {\n\tvoid (*gen_syndrome)(int, size_t, void **);\n\tvoid (*xor_syndrome)(int, int, int, size_t, void **);\n\tint (*valid)(void);\n\tconst char *name;\n\tint priority;\n};\n\nstruct raid6_recov_calls {\n\tvoid (*data2)(int, size_t, int, int, void **);\n\tvoid (*datap)(int, size_t, int, void **);\n\tint (*valid)(void);\n\tconst char *name;\n\tint priority;\n};\n\nstruct raid_kobject {\n\tu64 flags;\n\tstruct kobject kobj;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct rand_data {\n\tvoid *hash_state;\n\t__u64 prev_time;\n\t__u64 last_delta;\n\t__s64 last_delta2;\n\tunsigned int flags;\n\tunsigned int osr;\n\tunsigned char *mem;\n\tunsigned int memlocation;\n\tunsigned int memblocks;\n\tunsigned int memblocksize;\n\tunsigned int memaccessloops;\n\tunsigned int rct_count;\n\tunsigned int apt_cutoff;\n\tunsigned int apt_cutoff_permanent;\n\tunsigned int apt_observations;\n\tunsigned int apt_count;\n\tunsigned int apt_base;\n\tunsigned int health_failure;\n\tunsigned int apt_base_set: 1;\n};\n\nstruct range_node {\n\tstruct rb_node rn_rbnode;\n\tstruct rb_node rb_range_size;\n\tu32 rn_start;\n\tu32 rn_last;\n\tu32 __rn_subtree_last;\n};\n\nstruct range_trans {\n\tu32 source_type;\n\tu32 target_type;\n\tu32 target_class;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n};\n\nstruct raw3215_req;\n\nstruct raw3215_info {\n\tstruct tty_port port;\n\tstruct ccw_device *cdev;\n\tspinlock_t *lock;\n\tint flags;\n\tu8 *buffer;\n\tu8 *inbuf;\n\tint head;\n\tint count;\n\tint written;\n\tstruct raw3215_req *queued_read;\n\tstruct raw3215_req *queued_write;\n\twait_queue_head_t empty_wait;\n\tstruct timer_list timer;\n\tint line_pos;\n};\n\nstruct raw3215_req {\n\tenum raw3215_type type;\n\tint start;\n\tint len;\n\tint delayable;\n\tint residual;\n\tlong: 0;\n\tstruct ccw1 ccws[3];\n\tstruct raw3215_info *info;\n\tstruct raw3215_req *next;\n};\n\nstruct raw3270_request {\n\tstruct list_head list;\n\tstruct raw3270_view *view;\n\tstruct ccw1 ccw;\n\tvoid *buffer;\n\tsize_t size;\n\tint rescnt;\n\tint rc;\n\tvoid (*callback)(struct raw3270_request *, void *);\n\tvoid *callback_data;\n};\n\nstruct raw3270 {\n\tstruct list_head list;\n\tstruct ccw_device *cdev;\n\tint minor;\n\tint model;\n\tint rows;\n\tint cols;\n\tint old_model;\n\tint old_rows;\n\tint old_cols;\n\tunsigned int state;\n\tlong unsigned int flags;\n\tstruct list_head req_queue;\n\tstruct list_head view_list;\n\tstruct raw3270_view *view;\n\tstruct timer_list timer;\n\tunsigned char *ascebc;\n\tstruct raw3270_view init_view;\n\tstruct raw3270_request init_reset;\n\tstruct raw3270_request init_readpart;\n\tstruct raw3270_request init_readmod;\n\tunsigned char init_data[256];\n\tstruct work_struct resize_work;\n};\n\nstruct raw3270_fn {\n\tint (*activate)(struct raw3270_view *);\n\tvoid (*deactivate)(struct raw3270_view *);\n\tvoid (*intv)(struct raw3270_view *, struct raw3270_request *, struct irb *);\n\tvoid (*release)(struct raw3270_view *);\n\tvoid (*free)(struct raw3270_view *);\n\tvoid (*resize)(struct raw3270_view *, int, int, int, int, int, int);\n};\n\nstruct raw3270_iocb {\n\t__u16 model;\n\t__u16 line_cnt;\n\t__u16 col_cnt;\n\t__u16 pf_cnt;\n\t__u16 re_cnt;\n\t__u16 map;\n};\n\nstruct raw3270_notifier {\n\tstruct list_head list;\n\tvoid (*create)(int);\n\tvoid (*destroy)(int);\n};\n\nstruct raw3270_ua {\n\tstruct {\n\t\tshort int l;\n\t\tchar sfid;\n\t\tchar qcode;\n\t\tchar flags0;\n\t\tchar flags1;\n\t\tshort int w;\n\t\tshort int h;\n\t\tchar units;\n\t\tint xr;\n\t\tint yr;\n\t\tchar aw;\n\t\tchar ah;\n\t\tshort int buffsz;\n\t\tchar xmin;\n\t\tchar ymin;\n\t\tchar xmax;\n\t\tchar ymax;\n\t} __attribute__((packed)) uab;\n\tstruct {\n\t\tchar l;\n\t\tchar sdpid;\n\t\tchar res;\n\t\tchar auaid;\n\t\tshort int wauai;\n\t\tshort int hauai;\n\t\tchar auaunits;\n\t\tint auaxr;\n\t\tint auayr;\n\t\tchar awauai;\n\t\tchar ahauai;\n\t} __attribute__((packed)) aua;\n};\n\nstruct raw6_frag_vec {\n\tstruct msghdr *msg;\n\tint hlen;\n\tchar c[4];\n};\n\nstruct raw6_sock {\n\tstruct inet_sock inet;\n\t__u32 checksum;\n\t__u32 offset;\n\tstruct icmp6_filter filter;\n\t__u32 ip6mr_table;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tstruct ipv6_pinfo inet6;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tu64 before;\n\tu64 after;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tatomic_t seq;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rb_time_struct {\n\tlocal64_t time;\n};\n\ntypedef struct rb_time_struct rb_time_t;\n\nstruct rb_wait_data {\n\tstruct rb_irq_work *irq_work;\n\tint seq;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct rchan_callbacks;\n\nstruct rchan_buf;\n\nstruct rchan {\n\tu32 version;\n\tsize_t subbuf_size;\n\tsize_t n_subbufs;\n\tsize_t alloc_size;\n\tconst struct rchan_callbacks *cb;\n\tstruct kref kref;\n\tvoid *private_data;\n\tstruct rchan_buf **buf;\n\tint is_global;\n\tstruct list_head list;\n\tstruct dentry *parent;\n\tint has_base_filename;\n\tchar base_filename[255];\n};\n\nstruct rchan_buf_stats {\n\tunsigned int full_count;\n\tunsigned int big_count;\n};\n\nstruct rchan_buf {\n\tvoid *start;\n\tvoid *data;\n\tsize_t offset;\n\tsize_t subbufs_produced;\n\tsize_t subbufs_consumed;\n\tstruct rchan *chan;\n\twait_queue_head_t read_wait;\n\tstruct irq_work wakeup_work;\n\tstruct dentry *dentry;\n\tstruct kref kref;\n\tstruct rchan_buf_stats stats;\n\tstruct page **page_array;\n\tunsigned int page_count;\n\tunsigned int finalized;\n\tsize_t *padding;\n\tsize_t bytes_consumed;\n\tsize_t early_bytes;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rchan_callbacks {\n\tint (*subbuf_start)(struct rchan_buf *, void *, void *);\n\tstruct dentry * (*create_buf_file)(const char *, struct dentry *, umode_t, struct rchan_buf *, int *);\n\tint (*remove_buf_file)(struct dentry *);\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t fqslock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[33];\n\tstruct rcu_node *level[3];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rcu_tasks;\n\ntypedef void (*rcu_tasks_gp_func_t)(struct rcu_tasks *);\n\ntypedef void (*pregp_func_t)(struct list_head *);\n\ntypedef void (*pertask_func_t)(struct task_struct *, struct list_head *);\n\ntypedef void (*postscan_func_t)(struct list_head *);\n\ntypedef void (*holdouts_func_t)(struct list_head *, bool, bool *);\n\ntypedef void (*postgp_func_t)(struct rcu_tasks *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\nstruct rcu_tasks_percpu;\n\nstruct rcu_tasks {\n\tstruct rcuwait cbs_wait;\n\traw_spinlock_t cbs_gbl_lock;\n\tstruct mutex tasks_gp_mutex;\n\tint gp_state;\n\tint gp_sleep;\n\tint init_fract;\n\tlong unsigned int gp_jiffies;\n\tlong unsigned int gp_start;\n\tlong unsigned int tasks_gp_seq;\n\tlong unsigned int n_ipis;\n\tlong unsigned int n_ipis_fails;\n\tstruct task_struct *kthread_ptr;\n\tlong unsigned int lazy_jiffies;\n\trcu_tasks_gp_func_t gp_func;\n\tpregp_func_t pregp_func;\n\tpertask_func_t pertask_func;\n\tpostscan_func_t postscan_func;\n\tholdouts_func_t holdouts_func;\n\tpostgp_func_t postgp_func;\n\tcall_rcu_func_t call_func;\n\tunsigned int wait_state;\n\tstruct rcu_tasks_percpu *rtpcpu;\n\tstruct rcu_tasks_percpu **rtpcp_array;\n\tint percpu_enqueue_shift;\n\tint percpu_enqueue_lim;\n\tint percpu_dequeue_lim;\n\tlong unsigned int percpu_dequeue_gpseq;\n\tstruct mutex barrier_q_mutex;\n\tatomic_t barrier_q_count;\n\tstruct completion barrier_q_completion;\n\tlong unsigned int barrier_q_seq;\n\tlong unsigned int barrier_q_start;\n\tchar *name;\n\tchar *kname;\n};\n\nstruct rcu_tasks_percpu {\n\tstruct rcu_segcblist cblist;\n\traw_spinlock_t lock;\n\tlong unsigned int rtp_jiffies;\n\tlong unsigned int rtp_n_lock_retries;\n\tstruct timer_list lazy_timer;\n\tunsigned int urgent_gp;\n\tstruct work_struct rtp_work;\n\tstruct irq_work rtp_irq_work;\n\tstruct callback_head barrier_q_head;\n\tstruct list_head rtp_blkd_tasks;\n\tstruct list_head rtp_exit_list;\n\tint cpu;\n\tint index;\n\tstruct rcu_tasks *rtpp;\n};\n\nstruct rd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\tstruct in6_addr dest;\n\t__u8 opt[0];\n};\n\nstruct rdev_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct md_rdev *, char *);\n\tssize_t (*store)(struct md_rdev *, const char *, size_t);\n};\n\nstruct rdma_ah_init_attr {\n\tstruct rdma_ah_attr *ah_attr;\n\tu32 flags;\n\tstruct net_device *xmit_slave;\n};\n\nstruct rdma_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head rpools;\n};\n\nstruct rdma_counter {\n\tstruct rdma_restrack_entry res;\n\tstruct ib_device *device;\n\tuint32_t id;\n\tstruct kref kref;\n\tstruct rdma_counter_mode mode;\n\tstruct mutex lock;\n\tstruct rdma_hw_stats *stats;\n\tu32 port;\n};\n\nstruct rdma_stat_desc;\n\nstruct rdma_hw_stats {\n\tstruct mutex lock;\n\tlong unsigned int timestamp;\n\tlong unsigned int lifespan;\n\tconst struct rdma_stat_desc *descs;\n\tlong unsigned int *is_disabled;\n\tint num_counters;\n\tu64 value[0];\n};\n\nstruct rdma_link_ops {\n\tstruct list_head list;\n\tconst char *type;\n\tint (*newlink)(const char *, struct net_device *);\n};\n\nstruct rdma_netdev_alloc_params {\n\tsize_t sizeof_priv;\n\tunsigned int txqs;\n\tunsigned int rxqs;\n\tvoid *param;\n\tint (*initialize_rdma_netdev)(struct ib_device *, u32, struct net_device *, void *);\n};\n\nstruct rdma_stat_desc {\n\tconst char *name;\n\tunsigned int flags;\n\tconst void *priv;\n};\n\nstruct rdma_user_mmap_entry {\n\tstruct kref ref;\n\tstruct ib_ucontext *ucontext;\n\tlong unsigned int start_pgoff;\n\tsize_t npages;\n\tbool driver_removed;\n\tstruct mutex dmabufs_lock;\n\tstruct list_head dmabufs;\n};\n\nstruct rdmacg_resource {\n\tint max;\n\tint usage;\n};\n\nstruct rdmacg_resource_pool {\n\tstruct rdmacg_device *device;\n\tstruct rdmacg_resource resources[2];\n\tstruct list_head cg_node;\n\tstruct list_head dev_node;\n\tu64 usage_sum;\n\tint num_max_cnt;\n};\n\nstruct read_cpu_info_sccb {\n\tstruct sccb_header header;\n\tu16 nr_configured;\n\tu16 offset_configured;\n\tu16 nr_standby;\n\tu16 offset_standby;\n\tu8 reserved[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct read_info_sccb {\n\tstruct sccb_header header;\n\tu16 rnmax;\n\tu8 rnsize;\n\tu8 _pad_11[5];\n\tu16 ncpurl;\n\tu16 cpuoff;\n\tu8 _pad_20[4];\n\tu8 loadparm[8];\n\tu8 _pad_32[10];\n\tu8 fac42;\n\tu8 fac43;\n\tu8 _pad_44[4];\n\tu64 facilities;\n\tu8 _pad_56[10];\n\tu8 fac66;\n\tu8 _pad_67[9];\n\tu32 ibc;\n\tu8 _pad80[4];\n\tu8 fac84;\n\tu8 fac85;\n\tu8 _pad_86[5];\n\tu8 fac91;\n\tu8 _pad_92[6];\n\tu8 fac98;\n\tu8 hamaxpow;\n\tu32 rnsize2;\n\tu64 rnmax2;\n\tu32 hsa_size;\n\tu8 fac116;\n\tu8 fac117;\n\tu8 fac118;\n\tu8 fac119;\n\tu16 hcpua;\n\tu8 _pad_122[2];\n\tu32 hmfai;\n\tu8 _pad_128[6];\n\tu8 byte_134;\n\tu8 cpudirq;\n\tu16 cbl;\n\tu8 byte_138;\n\tu8 byte_139;\n\tu8 _pad_140[12148];\n};\n\nstruct read_storage_sccb {\n\tstruct sccb_header header;\n\tu16 max_id;\n\tu16 assigned;\n\tu16 standby;\n\tu32 entries[0];\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct readdir_callback {\n\tstruct dir_context ctx;\n\tstruct old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct recorded_ref {\n\tstruct list_head list;\n\tchar *name;\n\tstruct fs_path *full_path;\n\tu64 dir;\n\tu64 dir_gen;\n\tint name_len;\n\tstruct rb_node node;\n\tstruct rb_root *root;\n};\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tlong unsigned int head_block;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\nunion register_pair {\n\t__int128 unsigned pair;\n\tstruct {\n\t\tlong unsigned int even;\n\t\tlong unsigned int odd;\n\t};\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\nstruct reloc_control {\n\tstruct btrfs_block_group *block_group;\n\tstruct btrfs_root *extent_root;\n\tstruct inode *data_inode;\n\tstruct btrfs_block_rsv *block_rsv;\n\tstruct btrfs_backref_cache backref_cache;\n\tstruct file_extent_cluster cluster;\n\tstruct extent_io_tree processed_blocks;\n\tstruct mapping_tree reloc_root_tree;\n\tstruct list_head reloc_roots;\n\tstruct list_head dirty_subvol_roots;\n\tu64 merging_rsv_size;\n\tu64 nodes_relocated;\n\tu64 reserved_bytes;\n\tu64 search_start;\n\tu64 extents_found;\n\tenum reloc_stage stage;\n\tbool create_reloc_tree;\n\tbool merge_reloc_tree;\n\tbool found_file_extent;\n};\n\nstruct reloc_io_private {\n\tstruct completion done;\n\trefcount_t pending_refs;\n\tblk_status_t status;\n};\n\nstruct remap_chunk_info {\n\tstruct list_head list;\n\tu64 offset;\n\tstruct btrfs_block_group *bg;\n\tbool made_ro;\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct repcodes_s {\n\tU32 rep[3];\n};\n\ntypedef struct repcodes_s Repcodes_t;\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tu64 alloc_time_ns;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int wbt_flags;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tstruct bio_crypt_ctx *crypt_ctx;\n\tstruct blk_crypto_keyslot *crypt_keyslot;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct throtl_data;\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct blk_crypto_profile *crypto_profile;\n\tstruct kobject *crypto_kobject;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tlong unsigned int blkcg_pols[1];\n\tstruct blkcg_gq *root_blkg;\n\tstruct list_head blkg_list;\n\tstruct mutex blkcg_mutex;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_trace *blk_trace;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct throtl_data *td;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 valid: 1;\n\t__u8 error_code: 7;\n\t__u8 segment_number;\n\t__u8 reserved1: 2;\n\t__u8 ili: 1;\n\t__u8 reserved2: 1;\n\t__u8 sense_key: 4;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\nstruct reserve_ticket {\n\tu64 bytes;\n\tint error;\n\tbool steal;\n\tstruct list_head list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct resv_map {\n\tstruct kref refs;\n\tspinlock_t lock;\n\tstruct list_head regions;\n\tlong int adds_in_progress;\n\tstruct list_head region_cache;\n\tlong int region_cache_count;\n\tstruct rw_semaphore rw_sema;\n\tstruct page_counter *reservation_counter;\n\tlong unsigned int pages_per_hpage;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct rethook {\n\tvoid *data;\n\tvoid (*handler)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\tstruct objpool_head pool;\n\tstruct callback_head rcu;\n};\n\nstruct return_consumer {\n\t__u64 cookie;\n\t__u64 id;\n};\n\nstruct return_instance {\n\tstruct hprobe hprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tint cons_cnt;\n\tstruct return_instance *next;\n\tstruct callback_head rcu;\n\tstruct return_consumer consumer;\n\tstruct return_consumer *extra_consumers;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct ring_buffer_cpu_meta {\n\tlong unsigned int first_buffer;\n\tlong unsigned int head_buffer;\n\tlong unsigned int commit_buffer;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tint buffers[0];\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tlong unsigned int cache_pages_removed;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tsize_t event_size;\n\tint missed_events;\n};\n\nstruct ring_buffer_meta {\n\tint magic;\n\tint struct_sizes;\n\tlong unsigned int total_size;\n\tlong unsigned int buffers_offset;\n};\n\nstruct trace_buffer_meta;\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tlong unsigned int cnt;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_lost;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\trb_time_t write_stamp;\n\trb_time_t before_stamp;\n\tu64 event_stamp[5];\n\tu64 read_stamp;\n\tlong unsigned int pages_removed;\n\tunsigned int mapped;\n\tunsigned int user_mapped;\n\tstruct mutex mapping_lock;\n\tlong unsigned int *subbuf_ids;\n\tstruct trace_buffer_meta *meta_page;\n\tstruct ring_buffer_cpu_meta *ring_meta;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tstruct crypto_alg base;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct rock_ridge {\n\t__u8 signature[2];\n\t__u8 len;\n\t__u8 version;\n\tunion {\n\t\tstruct SU_SP_s SP;\n\t\tstruct SU_CE_s CE;\n\t\tstruct SU_ER_s ER;\n\t\tstruct RR_RR_s RR;\n\t\tstruct RR_PX_s PX;\n\t\tstruct RR_PN_s PN;\n\t\tstruct RR_SL_s SL;\n\t\tstruct RR_NM_s NM;\n\t\tstruct RR_CL_s CL;\n\t\tstruct RR_PL_s PL;\n\t\tstruct RR_TF_s TF;\n\t\tstruct RR_ZF_s ZF;\n\t} u;\n};\n\nstruct rock_state {\n\tvoid *buffer;\n\tunsigned char *chr;\n\tint len;\n\tint cont_size;\n\tint cont_extent;\n\tint cont_offset;\n\tint cont_loops;\n\tstruct inode *inode;\n};\n\nstruct role_allow {\n\tu32 role;\n\tu32 new_role;\n\tstruct role_allow *next;\n};\n\nstruct role_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap dominates;\n\tstruct ebitmap types;\n};\n\nstruct role_trans_datum {\n\tu32 new_role;\n};\n\nstruct role_trans_key {\n\tu32 role;\n\tu32 type;\n\tu32 tclass;\n};\n\nstruct romfs_super_block {\n\t__be32 word0;\n\t__be32 word1;\n\t__be32 size;\n\t__be32 checksum;\n\tchar name[0];\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct root_name_map {\n\tu64 id;\n\tconst char *name;\n};\n\nstruct rpl_iptunnel_encap {\n\tstruct {\n\t\tstruct {} __empty_srh;\n\t\tstruct ipv6_rpl_sr_hdr srh[0];\n\t};\n};\n\nstruct rpl_lwt {\n\tstruct dst_cache cache;\n\tstruct rpl_iptunnel_encap tuninfo;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[2];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n};\n\nstruct sched_info {\n\tlong unsigned int pcount;\n\tlong long unsigned int run_delay;\n\tlong long unsigned int max_run_delay;\n\tlong long unsigned int min_run_delay;\n\tlong long unsigned int last_arrival;\n\tlong long unsigned int last_queued;\n\tstruct timespec64 max_run_delay_ts;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tcall_single_data_t nohz_csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tunsigned int numa_migrate_on;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tktime_t hrtick_time;\n\tstruct sched_info rq_sched_info;\n\tlong long unsigned int rq_cpu_time;\n\tunsigned int yld_count;\n\tunsigned int sched_count;\n\tunsigned int sched_goidle;\n\tunsigned int ttwu_count;\n\tunsigned int ttwu_local;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tstruct rq *core;\n\tstruct task_struct *core_pick;\n\tstruct sched_dl_entity *core_dl_server;\n\tunsigned int core_enabled;\n\tunsigned int core_sched_seq;\n\tstruct rb_root core_tree;\n\tunsigned int core_task_seq;\n\tunsigned int core_pick_seq;\n\tlong unsigned int core_cookie;\n\tunsigned int core_forceidle_count;\n\tunsigned int core_forceidle_seq;\n\tunsigned int core_forceidle_occupation;\n\tu64 core_forceidle_start;\n\tcpumask_var_t scratch_mask;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t cfsb_csd;\n\tstruct list_head cfsb_csd_list;\n\tatomic_t nr_iowait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rq_wb {\n\tunsigned int wb_background;\n\tunsigned int wb_normal;\n\tshort int enable_state;\n\tunsigned int unknown_cnt;\n\tu64 win_nsec;\n\tu64 cur_win_nsec;\n\tstruct blk_stat_callback *cb;\n\tu64 sync_issue;\n\tvoid *sync_cookie;\n\tlong unsigned int last_issue;\n\tlong unsigned int last_comp;\n\tlong unsigned int min_lat_nsec;\n\tstruct rq_qos rqos;\n\tstruct rq_wait rq_wait[3];\n\tstruct rq_depth rq_depth;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n};\n\nstruct rs_msg {\n\tstruct icmp6hdr icmph;\n\t__u8 opt[0];\n};\n\nstruct rsa_key {\n\tconst u8 *n;\n\tconst u8 *e;\n\tconst u8 *d;\n\tconst u8 *p;\n\tconst u8 *q;\n\tconst u8 *dp;\n\tconst u8 *dq;\n\tconst u8 *qinv;\n\tsize_t n_sz;\n\tsize_t e_sz;\n\tsize_t d_sz;\n\tsize_t p_sz;\n\tsize_t q_sz;\n\tsize_t dp_sz;\n\tsize_t dq_sz;\n\tsize_t qinv_sz;\n};\n\nstruct rsa_mpi_key {\n\tMPI n;\n\tMPI e;\n\tMPI d;\n\tMPI p;\n\tMPI q;\n\tMPI dp;\n\tMPI dq;\n\tMPI qinv;\n};\n\nstruct rsassa_pkcs1_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct rsassa_pkcs1_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n\tconst struct hash_prefix *hash_prefix;\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rsvd_count {\n\tint ndelayed;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct rt0_hdr {\n\tstruct ipv6_rt_hdr rt_hdr;\n\t__u32 reserved;\n\tstruct in6_addr addr[0];\n};\n\nstruct rt6_exception {\n\tstruct hlist_node hlist;\n\tstruct rt6_info *rt6i;\n\tlong unsigned int stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_mtu_change_arg {\n\tstruct net_device *dev;\n\tunsigned int mtu;\n\tstruct fib6_info *f6i;\n};\n\nstruct rt6_nh {\n\tstruct fib6_info *fib6_info;\n\tstruct fib6_config r_cfg;\n\tstruct list_head list;\n};\n\nstruct rt6_rtnl_dump_arg {\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct net *net;\n\tstruct fib_dump_filter filter;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\t__kernel_size_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct ucontext;\n\nstruct ucontext_extended {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\t_sigregs uc_mcontext;\n\tsigset_t uc_sigmask;\n\tunsigned char __unused[120];\n\t_sigregs_ext uc_mcontext_ext;\n};\n\nstruct rt_sigframe {\n\t__u8 callee_used_stack[160];\n\t__u16 svc_insn;\n\tstruct siginfo info;\n\tstruct ucontext_extended uc;\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rta_mfc_stats {\n\t__u64 mfcs_packets;\n\t__u64 mfcs_bytes;\n\t__u64 mfcs_wrong_if;\n};\n\nstruct rtc_time;\n\nstruct rtc_wkalrm;\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct rtc_device;\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct runtime_instr_cb {\n\t__u64 rca;\n\t__u64 roa;\n\t__u64 rla;\n\t__u32 v: 1;\n\t__u32 s: 1;\n\t__u32 k: 1;\n\t__u32 h: 1;\n\t__u32 a: 1;\n\t__u32 reserved1: 3;\n\t__u32 ps: 1;\n\t__u32 qs: 1;\n\t__u32 pc: 1;\n\t__u32 qc: 1;\n\t__u32 reserved2: 1;\n\t__u32 g: 1;\n\t__u32 u: 1;\n\t__u32 l: 1;\n\t__u32 key: 4;\n\t__u32 reserved3: 8;\n\t__u32 t: 1;\n\t__u32 rgs: 3;\n\t__u32 m: 4;\n\t__u32 n: 1;\n\t__u32 mae: 1;\n\t__u32 reserved4: 2;\n\t__u32 c: 1;\n\t__u32 r: 1;\n\t__u32 b: 1;\n\t__u32 j: 1;\n\t__u32 e: 1;\n\t__u32 x: 1;\n\t__u32 reserved5: 2;\n\t__u32 bpxn: 1;\n\t__u32 bpxt: 1;\n\t__u32 bpti: 1;\n\t__u32 bpni: 1;\n\t__u32 reserved6: 2;\n\t__u32 d: 1;\n\t__u32 f: 1;\n\t__u32 ic: 4;\n\t__u32 dc: 4;\n\t__u64 reserved7;\n\t__u64 sf;\n\t__u64 rsic;\n\t__u64 reserved8;\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct s390_cma_mem_data {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct s390_cpu_feature {\n\tunsigned int type: 4;\n\tunsigned int num: 28;\n};\n\nstruct s390_ctrset_setdata {\n\t__u32 set;\n\t__u32 no_cnts;\n\t__u64 cv[0];\n};\n\nstruct s390_ctrset_cpudata {\n\t__u32 cpu_nr;\n\t__u32 no_sets;\n\tstruct s390_ctrset_setdata data[0];\n};\n\nstruct s390_ctrset_read {\n\t__u64 no_cpus;\n\tstruct s390_ctrset_cpudata data[0];\n};\n\nstruct s390_ctrset_start {\n\t__u64 version;\n\t__u64 data_bytes;\n\t__u64 cpumask_len;\n\t__u64 *cpumask;\n\t__u64 counter_sets;\n};\n\nstruct zpci_iommu_ctrs {\n\tatomic64_t mapped_pages;\n\tatomic64_t unmapped_pages;\n\tatomic64_t global_rpcits;\n\tatomic64_t sync_map_rpcits;\n\tatomic64_t sync_rpcits;\n};\n\nstruct s390_domain {\n\tstruct iommu_domain domain;\n\tstruct list_head devices;\n\tstruct zpci_iommu_ctrs ctrs;\n\tlong unsigned int *dma_table;\n\tspinlock_t list_lock;\n\tstruct callback_head rcu;\n\tu8 origin_type;\n};\n\nstruct s390_idle_data {\n\tlong unsigned int idle_count;\n\tlong unsigned int idle_time;\n\tlong unsigned int clock_idle_enter;\n\tlong unsigned int timer_idle_enter;\n\tlong unsigned int mt_cycles_enter[8];\n};\n\nstruct s390_insn {\n\tunion {\n\t\tconst char name[5];\n\t\tstruct {\n\t\t\tunsigned char zero;\n\t\t\tunsigned int offset;\n\t\t} __attribute__((packed));\n\t};\n\tunsigned char opfrag;\n\tunsigned char format;\n};\n\nstruct s390_io_adapter {\n\tunsigned int id;\n\tint isc;\n\tbool maskable;\n\tbool masked;\n\tbool swap;\n\tbool suppressible;\n};\n\nstruct s390_jit_data {\n\tstruct bpf_binary_header *header;\n\tstruct bpf_jit ctx;\n\tint pass;\n};\n\nstruct s390_load_data {\n\tvoid *kernel_buf;\n\tlong unsigned int kernel_mem;\n\tstruct parmarea *parm;\n\tsize_t memsz;\n\tstruct ipl_report *report;\n};\n\nstruct s390_opcode_offset {\n\tunsigned char opcode;\n\tunsigned char mask;\n\tunsigned char byte;\n\tshort unsigned int offset;\n\tshort unsigned int count;\n} __attribute__((packed));\n\nstruct s390_operand {\n\tunsigned char bits;\n\tunsigned char shift;\n\tshort unsigned int flags;\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct value_name_pair;\n\nstruct sa_name_list {\n\tint opcode;\n\tconst struct value_name_pair *arr;\n\tint arr_sz;\n};\n\nstruct save_area {\n\tstruct list_head list;\n\tu64 psw[2];\n\tu64 ctrs[16];\n\tu64 gprs[16];\n\tu32 acrs[16];\n\tu64 fprs[16];\n\tu32 fpc;\n\tu32 prefix;\n\tu32 todpreg;\n\tu64 timer;\n\tu64 todcmp;\n\tu64 vxrs_low[16];\n\t__vector128 vxrs_high[16];\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar saved_cmdlines[0];\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n\tint (*task_is_throttled)(struct task_struct *, int);\n};\n\nstruct sched_core_cookie {\n\trefcount_t refcnt;\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tunsigned int lb_count[3];\n\tunsigned int lb_failed[3];\n\tunsigned int lb_balanced[3];\n\tunsigned int lb_imbalance_load[3];\n\tunsigned int lb_imbalance_util[3];\n\tunsigned int lb_imbalance_task[3];\n\tunsigned int lb_imbalance_misfit[3];\n\tunsigned int lb_gained[3];\n\tunsigned int lb_hot_gained[3];\n\tunsigned int lb_nobusyg[3];\n\tunsigned int lb_nobusyq[3];\n\tunsigned int alb_count;\n\tunsigned int alb_failed;\n\tunsigned int alb_pushed;\n\tunsigned int sbe_count;\n\tunsigned int sbe_balanced;\n\tunsigned int sbe_pushed;\n\tunsigned int sbf_count;\n\tunsigned int sbf_balanced;\n\tunsigned int sbf_pushed;\n\tunsigned int ttwu_wake_remote;\n\tunsigned int ttwu_move_affine;\n\tunsigned int ttwu_move_balance;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n};\n\nstruct sched_statistics {\n\tu64 wait_start;\n\tu64 wait_max;\n\tu64 wait_count;\n\tu64 wait_sum;\n\tu64 iowait_count;\n\tu64 iowait_sum;\n\tu64 sleep_start;\n\tu64 sleep_max;\n\ts64 sum_sleep_runtime;\n\tu64 block_start;\n\tu64 block_max;\n\ts64 sum_block_runtime;\n\ts64 exec_max;\n\tu64 slice_max;\n\tu64 nr_migrations_cold;\n\tu64 nr_failed_migrations_affine;\n\tu64 nr_failed_migrations_running;\n\tu64 nr_failed_migrations_hot;\n\tu64 nr_forced_migrations;\n\tu64 nr_wakeups;\n\tu64 nr_wakeups_sync;\n\tu64 nr_wakeups_migrate;\n\tu64 nr_wakeups_local;\n\tu64 nr_wakeups_remote;\n\tu64 nr_wakeups_affine;\n\tu64 nr_wakeups_affine_attempts;\n\tu64 nr_wakeups_passive;\n\tu64 nr_wakeups_idle;\n\tu64 core_forceidle_sum;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sched_entity_stats {\n\tstruct sched_entity se;\n\tstruct sched_statistics stats;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 core_sched_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct schib {\n\tstruct pmcw pmcw;\n\tunion scsw scsw;\n\t__u64 mba;\n\t__u8 mda[4];\n} __attribute__((packed));\n\nstruct schib_config {\n\tu64 mba;\n\tu32 intparm;\n\tu16 mbi;\n\tu32 isc: 3;\n\tu32 ena: 1;\n\tu32 mme: 2;\n\tu32 mp: 1;\n\tu32 csense: 1;\n\tu32 mbfc: 1;\n};\n\nstruct sclp_req {\n\tstruct list_head list;\n\tsclp_cmdw_t command;\n\tvoid *sccb;\n\tchar status;\n\tint start_count;\n\tvoid (*callback)(struct sclp_req *, void *);\n\tvoid *callback_data;\n\tint queue_timeout;\n\tlong unsigned int queue_expires;\n};\n\nstruct sclp_buffer {\n\tstruct list_head list;\n\tstruct sclp_req request;\n\tvoid *sccb;\n\tstruct msg_buf *current_msg;\n\tchar *current_line;\n\tint current_length;\n\tint retry_count;\n\tshort unsigned int columns;\n\tshort unsigned int htab;\n\tunsigned int char_sum;\n\tunsigned int messages;\n\tvoid (*callback)(struct sclp_buffer *, int);\n};\n\nstruct sclp_chp_info {\n\tu8 recognized[32];\n\tu8 standby[32];\n\tu8 configured[32];\n};\n\nstruct sclp_core_entry {\n\tu8 core_id;\n\tu8 reserved0;\n\tchar: 4;\n\tu8 sief2: 1;\n\tu8 skey: 1;\n\tchar: 2;\n\tchar: 2;\n\tu8 gpere: 1;\n\tu8 siif: 1;\n\tu8 sigpif: 1;\n\tu8 reserved2[3];\n\tchar: 2;\n\tu8 ib: 1;\n\tu8 cei: 1;\n\tu8 reserved3[6];\n\tu8 type;\n\tu8 reserved1;\n};\n\nstruct sclp_core_info {\n\tunsigned int configured;\n\tunsigned int standby;\n\tunsigned int combined;\n\tstruct sclp_core_entry core[512];\n};\n\nstruct sclp_ctl_sccb {\n\t__u32 cmdw;\n\t__u64 sccb;\n} __attribute__((packed));\n\nstruct sclp_info {\n\tunsigned char has_linemode: 1;\n\tunsigned char has_vt220: 1;\n\tunsigned char has_siif: 1;\n\tunsigned char has_sigpif: 1;\n\tunsigned char has_core_type: 1;\n\tunsigned char has_sprp: 1;\n\tunsigned char has_hvs: 1;\n\tunsigned char has_wti: 1;\n\tunsigned char has_esca: 1;\n\tunsigned char has_sief2: 1;\n\tunsigned char has_64bscao: 1;\n\tunsigned char has_gpere: 1;\n\tunsigned char has_cmma: 1;\n\tunsigned char has_gsls: 1;\n\tunsigned char has_ib: 1;\n\tunsigned char has_cei: 1;\n\tunsigned char has_pfmfi: 1;\n\tunsigned char has_ibs: 1;\n\tunsigned char has_skey: 1;\n\tunsigned char has_kss: 1;\n\tunsigned char has_diag204_bif: 1;\n\tunsigned char has_gisaf: 1;\n\tunsigned char has_diag310: 1;\n\tunsigned char has_diag318: 1;\n\tunsigned char has_diag320: 1;\n\tunsigned char has_diag324: 1;\n\tunsigned char has_sipl: 1;\n\tunsigned char has_sipl_eckd: 1;\n\tunsigned char has_dirq: 1;\n\tunsigned char has_iplcc: 1;\n\tunsigned char has_zpci_lsi: 1;\n\tunsigned char has_aisii: 1;\n\tunsigned char has_aeni: 1;\n\tunsigned char has_aisi: 1;\n\tunsigned int ibc;\n\tunsigned int mtid;\n\tunsigned int mtid_cp;\n\tunsigned int mtid_prev;\n\tlong unsigned int rzm;\n\tlong unsigned int rnmax;\n\tlong unsigned int hamax;\n\tunsigned int max_cores;\n\tlong unsigned int hsa_size;\n\tlong unsigned int facilities;\n\tunsigned int hmfai;\n};\n\nstruct sclp_ipl_info {\n\tint is_valid;\n\tint has_dump;\n\tchar loadparm[8];\n};\n\nstruct sclp_mem {\n\tstruct kobject kobj;\n\tunsigned int id;\n\tunsigned int memmap_on_memory;\n\tunsigned int config;\n};\n\nstruct sclp_mem_arg {\n\tstruct sclp_mem *sclp_mems;\n\tstruct kset *kset;\n};\n\nstruct sclp_register {\n\tstruct list_head list;\n\tsccb_mask_t receive_mask;\n\tsccb_mask_t send_mask;\n\tsccb_mask_t sclp_receive_mask;\n\tsccb_mask_t sclp_send_mask;\n\tvoid (*state_change_fn)(struct sclp_register *);\n\tvoid (*receiver_fn)(struct evbuf_header *);\n};\n\nstruct sclp_sd_data {\n\tsize_t esize_bytes;\n\tsize_t dsize_bytes;\n\tvoid *data;\n};\n\nstruct sclp_sd_evbuf {\n\tstruct evbuf_header hdr;\n\tu8 eq;\n\tu8 di;\n\tu8 rflags;\n\tlong: 0;\n\tu32 id;\n\tshort: 16;\n\tu8 fmt;\n\tu8 status;\n\tu64 sat;\n\tu64 sa;\n\tu32 esize;\n\tu32 dsize;\n};\n\nstruct sclp_sd_file {\n\tstruct kobject kobj;\n\tstruct bin_attribute data_attr;\n\tstruct mutex data_mutex;\n\tstruct sclp_sd_data data;\n\tu8 di;\n};\n\nstruct sclp_sd_listener {\n\tstruct list_head list;\n\tu32 id;\n\tstruct completion completion;\n\tstruct sclp_sd_evbuf evbuf;\n};\n\nstruct sclp_sd_sccb {\n\tstruct sccb_header hdr;\n\tstruct sclp_sd_evbuf evbuf;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sclp_statechangebuf {\n\tstruct evbuf_header header;\n\tu8 validity_sclp_active_facility_mask: 1;\n\tu8 validity_sclp_receive_mask: 1;\n\tu8 validity_sclp_send_mask: 1;\n\tu8 validity_read_data_function_mask: 1;\n\tu16 _zeros: 12;\n\tu16 mask_length;\n\tu64 sclp_active_facility_mask;\n\tu8 masks[2046];\n} __attribute__((packed));\n\nstruct sclp_trace_entry {\n\tchar id[4];\n\tu32 a;\n\tu64 b;\n};\n\nstruct sclp_vt220_request {\n\tstruct list_head list;\n\tstruct sclp_req sclp_req;\n\tint retry_count;\n};\n\nstruct sclp_vt220_sccb {\n\tstruct sccb_header header;\n\tstruct evbuf_header evbuf;\n};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n\tu32 secid;\n};\n\nstruct scm_device {\n\tu64 address;\n\tu64 size;\n\tunsigned int nr_max_block;\n\tstruct device dev;\n\tstruct {\n\t\tunsigned int persistence: 4;\n\t\tunsigned int oper_state: 4;\n\t\tunsigned int data_state: 4;\n\t\tunsigned int rank: 4;\n\t\tunsigned int release: 1;\n\t\tunsigned int res_id: 8;\n\t} attrs;\n};\n\nstruct scm_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct scm_device *);\n\tvoid (*remove)(struct scm_device *);\n\tvoid (*notify)(struct scm_device *, enum scm_event);\n\tvoid (*handler)(struct scm_device *, void *, blk_status_t);\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scomp_alg {\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_acomp_streams streams;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tunion {\n\t\tvoid *src;\n\t\tlong unsigned int saddr;\n\t};\n};\n\nstruct scrub_sector_verification;\n\nstruct scrub_stripe {\n\tstruct scrub_ctx *sctx;\n\tstruct btrfs_block_group *bg;\n\tstruct folio *folios[16];\n\tstruct scrub_sector_verification *sectors;\n\tstruct btrfs_device *dev;\n\tu64 logical;\n\tu64 physical;\n\tu16 mirror_num;\n\tu16 nr_sectors;\n\tu16 nr_data_extents;\n\tu16 nr_meta_extents;\n\tatomic_t pending_io;\n\twait_queue_head_t io_wait;\n\twait_queue_head_t repair_wait;\n\tlong unsigned int state;\n\tlong unsigned int bitmaps[2];\n\tlong unsigned int write_error_bitmap;\n\tspinlock_t write_error_lock;\n\tu8 *csums;\n\tstruct work_struct work;\n};\n\nstruct scrub_ctx {\n\tstruct scrub_stripe stripes[128];\n\tstruct scrub_stripe *raid56_data_stripes;\n\tstruct btrfs_fs_info *fs_info;\n\tstruct btrfs_path extent_path;\n\tstruct btrfs_path csum_path;\n\tint first_free;\n\tint cur_stripe;\n\tatomic_t cancel_req;\n\tint readonly;\n\tktime_t throttle_deadline;\n\tu64 throttle_sent;\n\tbool is_dev_replace;\n\tu64 write_pointer;\n\tstruct mutex wr_lock;\n\tstruct btrfs_device *wr_tgtdev;\n\tstruct btrfs_scrub_progress stat;\n\tspinlock_t stat_lock;\n\trefcount_t refs;\n};\n\nstruct scrub_error_records {\n\tlong unsigned int init_error_bitmap;\n\tunsigned int nr_io_errors;\n\tunsigned int nr_csum_errors;\n\tunsigned int nr_meta_errors;\n\tunsigned int nr_meta_gen_errors;\n};\n\nstruct scrub_sector_verification {\n\tunion {\n\t\tu8 *csum;\n\t\tu64 generation;\n\t};\n};\n\nstruct scrub_warning {\n\tstruct btrfs_path *path;\n\tu64 extent_item_size;\n\tconst char *errstr;\n\tu64 physical;\n\tu64 logical;\n\tstruct btrfs_device *dev;\n};\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct scsi_dh_blist {\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *driver;\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n\tstruct bio_crypt_ctx *rq_crypt_ctx;\n\tstruct blk_crypto_keyslot *rq_crypt_keyslot;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved1: 3;\n\tu8 st_enble: 1;\n\tu8 cs_enble: 1;\n\tu8 ic_enable: 1;\n\tu8 reserved2[3];\n\tu8 acdlu: 1;\n\tu8 reserved3: 1;\n\tu8 rlbsr: 2;\n\tu8 lbm_descriptor_type: 4;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_nl_hdr {\n\t__u8 version;\n\t__u8 transport;\n\t__u16 magic;\n\t__u16 msgtype;\n\t__u16 msglen;\n};\n\nstruct scsi_proc_entry {\n\tstruct list_head entry;\n\tconst struct scsi_host_template *sht;\n\tstruct proc_dir_entry *proc_dir;\n\tunsigned int present;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 perm: 1;\n\tu8 reserved1: 7;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 reserved3: 2;\n\tu8 rel_lifetime: 6;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct sctp_paramhdr {\n\t__be16 type;\n\t__be16 length;\n};\n\nstruct sctp_adaptation_ind_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 adaptation_ind;\n};\n\nstruct sctp_addip_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 crr_id;\n};\n\nstruct sctp_addiphdr {\n\t__be32 serial;\n};\n\nstruct sockaddr_inet {\n\tshort unsigned int sa_family;\n\tchar sa_data[26];\n};\n\nunion sctp_addr {\n\tstruct sockaddr_inet sa;\n\tstruct sockaddr_in v4;\n\tstruct sockaddr_in6 v6;\n};\n\nstruct sctp_ipv4addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in_addr addr;\n};\n\nstruct sctp_ipv6addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in6_addr addr;\n};\n\nunion sctp_addr_param {\n\tstruct sctp_paramhdr p;\n\tstruct sctp_ipv4addr_param v4;\n\tstruct sctp_ipv6addr_param v6;\n};\n\nstruct sctp_transport;\n\nstruct sctp_sock;\n\nstruct sctp_af {\n\tint (*sctp_xmit)(struct sk_buff *, struct sctp_transport *);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*get_dst)(struct sctp_transport *, union sctp_addr *, struct flowi *, struct sock *);\n\tvoid (*get_saddr)(struct sctp_sock *, struct sctp_transport *, struct flowi *);\n\tvoid (*copy_addrlist)(struct list_head *, struct net_device *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *);\n\tvoid (*addr_copy)(union sctp_addr *, union sctp_addr *);\n\tvoid (*from_skb)(union sctp_addr *, struct sk_buff *, int);\n\tvoid (*from_sk)(union sctp_addr *, struct sock *);\n\tbool (*from_addr_param)(union sctp_addr *, union sctp_addr_param *, __be16, int);\n\tint (*to_addr_param)(const union sctp_addr *, union sctp_addr_param *);\n\tint (*addr_valid)(union sctp_addr *, struct sctp_sock *, const struct sk_buff *);\n\tenum sctp_scope (*scope)(union sctp_addr *);\n\tvoid (*inaddr_any)(union sctp_addr *, __be16);\n\tint (*is_any)(const union sctp_addr *);\n\tint (*available)(union sctp_addr *, struct sctp_sock *);\n\tint (*skb_iif)(const struct sk_buff *);\n\tint (*skb_sdif)(const struct sk_buff *);\n\tint (*is_ce)(const struct sk_buff *);\n\tvoid (*seq_dump_addr)(struct seq_file *, union sctp_addr *);\n\tvoid (*ecn_capable)(struct sock *);\n\t__u16 net_header_len;\n\tint sockaddr_len;\n\tint (*ip_options_len)(struct sock *);\n\tsa_family_t sa_family;\n\tstruct list_head list;\n};\n\nstruct sctp_chunk;\n\nstruct sctp_inq {\n\tstruct list_head in_chunk_list;\n\tstruct sctp_chunk *in_progress;\n\tstruct work_struct immediate;\n};\n\nstruct sctp_bind_addr {\n\t__u16 port;\n\tstruct list_head address_list;\n};\n\nstruct sctp_ep_common {\n\tenum sctp_endpoint_type type;\n\trefcount_t refcnt;\n\tbool dead;\n\tstruct sock *sk;\n\tstruct net *net;\n\tstruct sctp_inq inqueue;\n\tstruct sctp_bind_addr bind_addr;\n};\n\nstruct sctp_cookie {\n\t__u32 my_vtag;\n\t__u32 peer_vtag;\n\t__u32 my_ttag;\n\t__u32 peer_ttag;\n\tktime_t expiration;\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u32 initial_tsn;\n\tunion sctp_addr peer_addr;\n\t__u16 my_port;\n\t__u8 prsctp_capable;\n\t__u8 padding;\n\t__u32 adaptation_ind;\n\t__u8 auth_random[36];\n\t__u8 auth_hmacs[10];\n\t__u8 auth_chunks[20];\n\t__u32 raw_addr_list_len;\n};\n\nstruct sctp_tsnmap {\n\tlong unsigned int *tsn_map;\n\t__u32 base_tsn;\n\t__u32 cumulative_tsn_ack_point;\n\t__u32 max_tsn_seen;\n\t__u16 len;\n\t__u16 pending_data;\n\t__u16 num_dup_tsns;\n\t__be32 dup_tsns[16];\n};\n\nstruct sctp_inithdr_host {\n\t__u32 init_tag;\n\t__u32 a_rwnd;\n\t__u16 num_outbound_streams;\n\t__u16 num_inbound_streams;\n\t__u32 initial_tsn;\n};\n\nstruct sctp_stream_out_ext;\n\nstruct sctp_stream_out {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\tstruct sctp_stream_out_ext *ext;\n\t__u8 state;\n};\n\nstruct sctp_stream_in {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\t__u32 fsn;\n\t__u32 fsn_uo;\n\tchar pd_mode;\n\tchar pd_mode_uo;\n};\n\nstruct sctp_stream_interleave;\n\nstruct sctp_stream {\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_out type[0];\n\t} out;\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_in type[0];\n\t} in;\n\t__u16 outcnt;\n\t__u16 incnt;\n\tstruct sctp_stream_out *out_curr;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t\tstruct sctp_stream_out_ext *rr_next;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t};\n\t};\n\tstruct sctp_stream_interleave *si;\n};\n\nstruct sctp_sched_ops;\n\nstruct sctp_association;\n\nstruct sctp_outq {\n\tstruct sctp_association *asoc;\n\tstruct list_head out_chunk_list;\n\tconst struct sctp_sched_ops *sched;\n\tunsigned int out_qlen;\n\tunsigned int error;\n\tstruct list_head control_chunk_list;\n\tstruct list_head sacked;\n\tstruct list_head retransmit;\n\tstruct list_head abandoned;\n\t__u32 outstanding_bytes;\n\tchar fast_rtx;\n\tchar cork;\n};\n\nstruct sctp_ulpq {\n\tchar pd_mode;\n\tstruct sctp_association *asoc;\n\tstruct sk_buff_head reasm;\n\tstruct sk_buff_head reasm_uo;\n\tstruct sk_buff_head lobby;\n};\n\nstruct sctp_priv_assoc_stats {\n\tstruct __kernel_sockaddr_storage obs_rto_ipaddr;\n\t__u64 max_obs_rto;\n\t__u64 isacks;\n\t__u64 osacks;\n\t__u64 opackets;\n\t__u64 ipackets;\n\t__u64 rtxchunks;\n\t__u64 outofseqtsns;\n\t__u64 idupchunks;\n\t__u64 gapcnt;\n\t__u64 ouodchunks;\n\t__u64 iuodchunks;\n\t__u64 oodchunks;\n\t__u64 iodchunks;\n\t__u64 octrlchunks;\n\t__u64 ictrlchunks;\n};\n\nstruct sctp_endpoint;\n\nstruct sctp_random_param;\n\nstruct sctp_chunks_param;\n\nstruct sctp_hmac_algo_param;\n\nstruct sctp_auth_bytes;\n\nstruct sctp_shared_key;\n\nstruct sctp_association {\n\tstruct sctp_ep_common base;\n\tstruct list_head asocs;\n\tsctp_assoc_t assoc_id;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_cookie c;\n\tstruct {\n\t\tstruct list_head transport_addr_list;\n\t\t__u32 rwnd;\n\t\t__u16 transport_count;\n\t\t__u16 port;\n\t\tstruct sctp_transport *primary_path;\n\t\tunion sctp_addr primary_addr;\n\t\tstruct sctp_transport *active_path;\n\t\tstruct sctp_transport *retran_path;\n\t\tstruct sctp_transport *last_sent_to;\n\t\tstruct sctp_transport *last_data_from;\n\t\tstruct sctp_tsnmap tsn_map;\n\t\t__be16 addip_disabled_mask;\n\t\t__u16 ecn_capable: 1;\n\t\t__u16 ipv4_address: 1;\n\t\t__u16 ipv6_address: 1;\n\t\t__u16 asconf_capable: 1;\n\t\t__u16 prsctp_capable: 1;\n\t\t__u16 reconf_capable: 1;\n\t\t__u16 intl_capable: 1;\n\t\t__u16 auth_capable: 1;\n\t\t__u16 sack_needed: 1;\n\t\t__u16 sack_generation: 1;\n\t\t__u16 zero_window_announced: 1;\n\t\t__u32 sack_cnt;\n\t\t__u32 adaptation_ind;\n\t\tstruct sctp_inithdr_host i;\n\t\tvoid *cookie;\n\t\tint cookie_len;\n\t\t__u32 addip_serial;\n\t\tstruct sctp_random_param *peer_random;\n\t\tstruct sctp_chunks_param *peer_chunks;\n\t\tstruct sctp_hmac_algo_param *peer_hmacs;\n\t} peer;\n\tenum sctp_state state;\n\tint overall_error_count;\n\tktime_t cookie_life;\n\tlong unsigned int rto_initial;\n\tlong unsigned int rto_max;\n\tlong unsigned int rto_min;\n\tint max_burst;\n\tint max_retrans;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u16 max_init_attempts;\n\t__u16 init_retries;\n\tlong unsigned int max_init_timeo;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u8 pmtu_pending;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\t__u32 sackfreq;\n\tlong unsigned int sackdelay;\n\tlong unsigned int timeouts[12];\n\tstruct timer_list timers[12];\n\tstruct sctp_transport *shutdown_last_sent_to;\n\tstruct sctp_transport *init_last_sent_to;\n\tint shutdown_retries;\n\t__u32 next_tsn;\n\t__u32 ctsn_ack_point;\n\t__u32 adv_peer_ack_point;\n\t__u32 highest_sacked;\n\t__u32 fast_recovery_exit;\n\t__u8 fast_recovery;\n\t__u16 unack_data;\n\t__u32 rtx_data_chunks;\n\t__u32 rwnd;\n\t__u32 a_rwnd;\n\t__u32 rwnd_over;\n\t__u32 rwnd_press;\n\tint sndbuf_used;\n\tatomic_t rmem_alloc;\n\twait_queue_head_t wait;\n\t__u32 frag_point;\n\t__u32 user_frag;\n\tint init_err_counter;\n\tint init_cycle;\n\t__u16 default_stream;\n\t__u16 default_flags;\n\t__u32 default_ppid;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tstruct sctp_stream stream;\n\tstruct sctp_outq outqueue;\n\tstruct sctp_ulpq ulpq;\n\t__u32 last_ecne_tsn;\n\t__u32 last_cwr_tsn;\n\tint numduptsns;\n\tstruct sctp_chunk *addip_last_asconf;\n\tstruct list_head asconf_ack_list;\n\tstruct list_head addip_chunk_list;\n\t__u32 addip_serial;\n\tint src_out_of_asoc_ok;\n\tunion sctp_addr *asconf_addr_del_pending;\n\tstruct sctp_transport *new_transport;\n\tstruct list_head endpoint_shared_keys;\n\tstruct sctp_auth_bytes *asoc_shared_key;\n\tstruct sctp_shared_key *shkey;\n\t__u16 default_hmac_id;\n\t__u16 active_key_id;\n\t__u8 need_ecne: 1;\n\t__u8 temp: 1;\n\t__u8 pf_expose: 2;\n\t__u8 force_delay: 1;\n\t__u8 strreset_enable;\n\t__u8 strreset_outstanding;\n\t__u32 strreset_outseq;\n\t__u32 strreset_inseq;\n\t__u32 strreset_result[2];\n\tstruct sctp_chunk *strreset_chunk;\n\tstruct sctp_priv_assoc_stats stats;\n\tint sent_cnt_removable;\n\t__u16 subscribe;\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tu32 secid;\n\tu32 peer_secid;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_assocparams {\n\tsctp_assoc_t sasoc_assoc_id;\n\t__u16 sasoc_asocmaxrxt;\n\t__u16 sasoc_number_peer_destinations;\n\t__u32 sasoc_peer_rwnd;\n\t__u32 sasoc_local_rwnd;\n\t__u32 sasoc_cookie_life;\n};\n\nstruct sctp_auth_bytes {\n\trefcount_t refcnt;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct sctp_authhdr {\n\t__be16 shkey_id;\n\t__be16 hmac_id;\n};\n\nstruct sctp_bind_bucket {\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct hlist_node node;\n\tstruct hlist_head owner;\n\tstruct net *net;\n};\n\nstruct sctp_cookie_preserve_param;\n\nstruct sctp_hostname_param;\n\nstruct sctp_cookie_param;\n\nstruct sctp_supported_addrs_param;\n\nstruct sctp_supported_ext_param;\n\nunion sctp_params {\n\tvoid *v;\n\tstruct sctp_paramhdr *p;\n\tstruct sctp_cookie_preserve_param *life;\n\tstruct sctp_hostname_param *dns;\n\tstruct sctp_cookie_param *cookie;\n\tstruct sctp_supported_addrs_param *sat;\n\tstruct sctp_ipv4addr_param *v4;\n\tstruct sctp_ipv6addr_param *v6;\n\tunion sctp_addr_param *addr;\n\tstruct sctp_adaptation_ind_param *aind;\n\tstruct sctp_supported_ext_param *ext;\n\tstruct sctp_random_param *random;\n\tstruct sctp_chunks_param *chunks;\n\tstruct sctp_hmac_algo_param *hmac_algo;\n\tstruct sctp_addip_param *addip;\n};\n\nstruct sctp_sndrcvinfo {\n\t__u16 sinfo_stream;\n\t__u16 sinfo_ssn;\n\t__u16 sinfo_flags;\n\t__u32 sinfo_ppid;\n\t__u32 sinfo_context;\n\t__u32 sinfo_timetolive;\n\t__u32 sinfo_tsn;\n\t__u32 sinfo_cumtsn;\n\tsctp_assoc_t sinfo_assoc_id;\n};\n\nstruct sctp_datahdr;\n\nstruct sctp_inithdr;\n\nstruct sctp_sackhdr;\n\nstruct sctp_heartbeathdr;\n\nstruct sctp_sender_hb_info;\n\nstruct sctp_shutdownhdr;\n\nstruct sctp_signed_cookie;\n\nstruct sctp_ecnehdr;\n\nstruct sctp_cwrhdr;\n\nstruct sctp_errhdr;\n\nstruct sctp_fwdtsn_hdr;\n\nstruct sctp_idatahdr;\n\nstruct sctp_ifwdtsn_hdr;\n\nstruct sctp_chunkhdr;\n\nstruct sctphdr;\n\nstruct sctp_datamsg;\n\nstruct sctp_chunk {\n\tstruct list_head list;\n\trefcount_t refcnt;\n\tint sent_count;\n\tunion {\n\t\tstruct list_head transmitted_list;\n\t\tstruct list_head stream_list;\n\t};\n\tstruct list_head frag_list;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct sk_buff *head_skb;\n\t\tstruct sctp_shared_key *shkey;\n\t};\n\tunion sctp_params param_hdr;\n\tunion {\n\t\t__u8 *v;\n\t\tstruct sctp_datahdr *data_hdr;\n\t\tstruct sctp_inithdr *init_hdr;\n\t\tstruct sctp_sackhdr *sack_hdr;\n\t\tstruct sctp_heartbeathdr *hb_hdr;\n\t\tstruct sctp_sender_hb_info *hbs_hdr;\n\t\tstruct sctp_shutdownhdr *shutdown_hdr;\n\t\tstruct sctp_signed_cookie *cookie_hdr;\n\t\tstruct sctp_ecnehdr *ecne_hdr;\n\t\tstruct sctp_cwrhdr *ecn_cwr_hdr;\n\t\tstruct sctp_errhdr *err_hdr;\n\t\tstruct sctp_addiphdr *addip_hdr;\n\t\tstruct sctp_fwdtsn_hdr *fwdtsn_hdr;\n\t\tstruct sctp_authhdr *auth_hdr;\n\t\tstruct sctp_idatahdr *idata_hdr;\n\t\tstruct sctp_ifwdtsn_hdr *ifwdtsn_hdr;\n\t} subh;\n\t__u8 *chunk_end;\n\tstruct sctp_chunkhdr *chunk_hdr;\n\tstruct sctphdr *sctp_hdr;\n\tstruct sctp_sndrcvinfo sinfo;\n\tstruct sctp_association *asoc;\n\tstruct sctp_ep_common *rcvr;\n\tlong unsigned int sent_at;\n\tunion sctp_addr source;\n\tunion sctp_addr dest;\n\tstruct sctp_datamsg *msg;\n\tstruct sctp_transport *transport;\n\tstruct sk_buff *auth_chunk;\n\t__u16 rtt_in_progress: 1;\n\t__u16 has_tsn: 1;\n\t__u16 has_ssn: 1;\n\t__u16 singleton: 1;\n\t__u16 end_of_packet: 1;\n\t__u16 ecn_ce_done: 1;\n\t__u16 pdiscard: 1;\n\t__u16 tsn_gap_acked: 1;\n\t__u16 data_accepted: 1;\n\t__u16 auth: 1;\n\t__u16 has_asconf: 1;\n\t__u16 pmtu_probe: 1;\n\t__u16 tsn_missing_report: 2;\n\t__u16 fast_retransmit: 2;\n};\n\nstruct sctp_chunkhdr {\n\t__u8 type;\n\t__u8 flags;\n\t__be16 length;\n};\n\nstruct sctp_chunks_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_cookie_param {\n\tstruct sctp_paramhdr p;\n\t__u8 body[0];\n};\n\nstruct sctp_cookie_preserve_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 lifespan_increment;\n};\n\nstruct sctp_cwrhdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_datahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 ssn;\n\t__u32 ppid;\n};\n\nstruct sctp_datamsg {\n\tstruct list_head chunks;\n\trefcount_t refcnt;\n\tlong unsigned int expires_at;\n\tint send_error;\n\tu8 send_failed: 1;\n\tu8 can_delay: 1;\n\tu8 abandoned: 1;\n};\n\nstruct sctp_ecnehdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_endpoint {\n\tstruct sctp_ep_common base;\n\tstruct hlist_node node;\n\tint hashent;\n\tstruct list_head asocs;\n\tstruct hmac_sha256_key cookie_auth_key;\n\t__u32 sndbuf_policy;\n\t__u32 rcvbuf_policy;\n\tstruct sctp_hmac_algo_param *auth_hmacs_list;\n\tstruct sctp_chunks_param *auth_chunk_list;\n\tstruct list_head endpoint_shared_keys;\n\t__u16 active_key_id;\n\t__u8 ecn_enable: 1;\n\t__u8 auth_enable: 1;\n\t__u8 intl_enable: 1;\n\t__u8 prsctp_enable: 1;\n\t__u8 asconf_enable: 1;\n\t__u8 reconf_enable: 1;\n\t__u8 strreset_enable;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_errhdr {\n\t__be16 cause;\n\t__be16 length;\n};\n\nstruct sctp_fwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_heartbeathdr {\n\tstruct sctp_paramhdr info;\n};\n\nstruct sctp_hmac_algo_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 hmac_ids[0];\n};\n\nstruct sctp_hostname_param {\n\tstruct sctp_paramhdr param_hdr;\n\tuint8_t hostname[0];\n};\n\nstruct sctp_idatahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 reserved;\n\t__be32 mid;\n\tunion {\n\t\t__u32 ppid;\n\t\t__be32 fsn;\n\t};\n};\n\nstruct sctp_ifwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_inithdr {\n\t__be32 init_tag;\n\t__be32 a_rwnd;\n\t__be16 num_outbound_streams;\n\t__be16 num_inbound_streams;\n\t__be32 initial_tsn;\n};\n\nstruct sctp_initmsg {\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u16 sinit_max_attempts;\n\t__u16 sinit_max_init_timeo;\n};\n\nstruct sctp_packet {\n\t__u16 source_port;\n\t__u16 destination_port;\n\t__u32 vtag;\n\tstruct list_head chunk_list;\n\tsize_t overhead;\n\tsize_t size;\n\tsize_t max_size;\n\tstruct sctp_transport *transport;\n\tstruct sctp_chunk *auth;\n\tu8 has_cookie_echo: 1;\n\tu8 has_sack: 1;\n\tu8 has_auth: 1;\n\tu8 has_data: 1;\n\tu8 ipfragok: 1;\n};\n\nstruct sctp_paddrparams {\n\tsctp_assoc_t spp_assoc_id;\n\tstruct __kernel_sockaddr_storage spp_address;\n\t__u32 spp_hbinterval;\n\t__u16 spp_pathmaxrxt;\n\t__u32 spp_pathmtu;\n\t__u32 spp_sackdelay;\n\t__u32 spp_flags;\n\t__u32 spp_ipv6_flowlabel;\n\t__u8 spp_dscp;\n\tint: 0;\n} __attribute__((packed));\n\nstruct sctp_ulpevent;\n\nstruct sctp_pf {\n\tvoid (*event_msgname)(struct sctp_ulpevent *, char *, int *);\n\tvoid (*skb_msgname)(struct sk_buff *, char *, int *);\n\tint (*af_supported)(sa_family_t, struct sctp_sock *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *, struct sctp_sock *);\n\tint (*bind_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*send_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*supported_addrs)(const struct sctp_sock *, __be16 *);\n\tint (*addr_to_user)(struct sctp_sock *, union sctp_addr *);\n\tvoid (*to_sk_saddr)(union sctp_addr *, struct sock *);\n\tvoid (*to_sk_daddr)(union sctp_addr *, struct sock *);\n\tvoid (*copy_ip_options)(struct sock *, struct sock *);\n\tstruct sctp_af *af;\n};\n\nstruct sctp_random_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 random_val[0];\n};\n\nstruct sctp_rtoinfo {\n\tsctp_assoc_t srto_assoc_id;\n\t__u32 srto_initial;\n\t__u32 srto_max;\n\t__u32 srto_min;\n};\n\nstruct sctp_sackhdr {\n\t__be32 cum_tsn_ack;\n\t__be32 a_rwnd;\n\t__be16 num_gap_ack_blocks;\n\t__be16 num_dup_tsns;\n};\n\nstruct sctp_sender_hb_info {\n\tstruct sctp_paramhdr param_hdr;\n\tunion sctp_addr daddr;\n\tlong unsigned int sent_at;\n\t__u64 hb_nonce;\n\t__u32 probe_size;\n};\n\nstruct sctp_shared_key {\n\tstruct list_head key_list;\n\tstruct sctp_auth_bytes *key;\n\trefcount_t refcnt;\n\t__u16 key_id;\n\t__u8 deactivated;\n};\n\nstruct sctp_shutdownhdr {\n\t__be32 cum_tsn_ack;\n};\n\nstruct sctp_signed_cookie {\n\t__u8 mac[32];\n\t__u32 __pad;\n\tstruct sctp_cookie c;\n} __attribute__((packed));\n\nstruct sctp_sock {\n\tstruct inet_sock inet;\n\tenum sctp_socket_type type;\n\tstruct sctp_pf *pf;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_bind_bucket *bind_hash;\n\t__u16 default_stream;\n\t__u32 default_ppid;\n\t__u16 default_flags;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tint max_burst;\n\t__u32 hbinterval;\n\t__u32 probe_interval;\n\t__be16 udp_port;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 sackdelay;\n\t__u32 sackfreq;\n\t__u32 param_flags;\n\t__u32 default_ss;\n\tstruct sctp_rtoinfo rtoinfo;\n\tstruct sctp_paddrparams paddrparam;\n\tstruct sctp_assocparams assocparams;\n\t__u16 subscribe;\n\tstruct sctp_initmsg initmsg;\n\tint user_frag;\n\t__u32 autoclose;\n\t__u32 adaptation_ind;\n\t__u32 pd_point;\n\t__u16 nodelay: 1;\n\t__u16 pf_expose: 2;\n\t__u16 reuse: 1;\n\t__u16 disable_fragments: 1;\n\t__u16 v4mapped: 1;\n\t__u16 frag_interleave: 1;\n\t__u16 recvrcvinfo: 1;\n\t__u16 recvnxtinfo: 1;\n\t__u16 data_ready_signalled: 1;\n\t__u16 cookie_auth_enable: 1;\n\tatomic_t pd_mode;\n\tstruct sk_buff_head pd_lobby;\n\tstruct list_head auto_asconf_list;\n\tint do_auto_asconf;\n};\n\nstruct sctp_stream_interleave {\n\t__u16 data_chunk_len;\n\t__u16 ftsn_chunk_len;\n\tstruct sctp_chunk * (*make_datafrag)(const struct sctp_association *, const struct sctp_sndrcvinfo *, int, __u8, gfp_t);\n\tvoid (*assign_number)(struct sctp_chunk *);\n\tbool (*validate_data)(struct sctp_chunk *);\n\tint (*ulpevent_data)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tint (*enqueue_event)(struct sctp_ulpq *, struct sctp_ulpevent *);\n\tvoid (*renege_events)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tvoid (*start_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*abort_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*generate_ftsn)(struct sctp_outq *, __u32);\n\tbool (*validate_ftsn)(struct sctp_chunk *);\n\tvoid (*report_ftsn)(struct sctp_ulpq *, __u32);\n\tvoid (*handle_ftsn)(struct sctp_ulpq *, struct sctp_chunk *);\n};\n\nstruct sctp_stream_priorities;\n\nstruct sctp_stream_out_ext {\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tstruct list_head outq;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t\tstruct sctp_stream_priorities *prio_head;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t\t__u32 fc_length;\n\t\t\t__u16 fc_weight;\n\t\t};\n\t};\n};\n\nstruct sctp_stream_priorities {\n\tstruct list_head prio_sched;\n\tstruct list_head active;\n\tstruct sctp_stream_out_ext *next;\n\t__u16 prio;\n\t__u16 users;\n};\n\nstruct sctp_supported_addrs_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 types[0];\n};\n\nstruct sctp_supported_ext_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_transport {\n\tstruct list_head transports;\n\tstruct rhlist_head node;\n\trefcount_t refcnt;\n\t__u32 dead: 1;\n\t__u32 rto_pending: 1;\n\t__u32 hb_sent: 1;\n\t__u32 pmtu_pending: 1;\n\t__u32 dst_pending_confirm: 1;\n\t__u32 sack_generation: 1;\n\tu32 dst_cookie;\n\tstruct flowi fl;\n\tunion sctp_addr ipaddr;\n\tstruct sctp_af *af_specific;\n\tstruct sctp_association *asoc;\n\tlong unsigned int rto;\n\t__u32 rtt;\n\t__u32 rttvar;\n\t__u32 srtt;\n\t__u32 cwnd;\n\t__u32 ssthresh;\n\t__u32 partial_bytes_acked;\n\t__u32 flight_size;\n\t__u32 burst_limited;\n\tstruct dst_entry *dst;\n\tunion sctp_addr saddr;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\tlong unsigned int sackdelay;\n\t__u32 sackfreq;\n\tatomic_t mtu_info;\n\tktime_t last_time_heard;\n\tlong unsigned int last_time_sent;\n\tlong unsigned int last_time_ecne_reduced;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\tint init_sent_count;\n\tint state;\n\tshort unsigned int error_count;\n\tstruct timer_list T3_rtx_timer;\n\tstruct timer_list hb_timer;\n\tstruct timer_list proto_unreach_timer;\n\tstruct timer_list reconf_timer;\n\tstruct timer_list probe_timer;\n\tstruct list_head transmitted;\n\tstruct sctp_packet packet;\n\tstruct list_head send_ready;\n\tstruct {\n\t\t__u32 next_tsn_at_change;\n\t\tchar changeover_active;\n\t\tchar cycling_changeover;\n\t\tchar cacc_saw_newack;\n\t} cacc;\n\tstruct {\n\t\t__u16 pmtu;\n\t\t__u16 probe_size;\n\t\t__u16 probe_high;\n\t\t__u8 probe_count;\n\t\t__u8 state;\n\t} pl;\n\t__u64 hb_nonce;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_ulpevent {\n\tstruct sctp_association *asoc;\n\tstruct sctp_chunk *chunk;\n\tunsigned int rmem_len;\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\tunion {\n\t\t__u32 ppid;\n\t\t__u32 fsn;\n\t};\n\t__u32 tsn;\n\t__u32 cumtsn;\n\t__u16 stream;\n\t__u16 flags;\n\t__u16 msg_flags;\n} __attribute__((packed));\n\nstruct sctphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 vtag;\n\t__le32 checksum;\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tconst char *reason;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[1];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work error_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tvoid *__ctx[0];\n};\n\nstruct sdesc {\n\tstruct shash_desc shash;\n};\n\nstruct sdias_evbuf {\n\tstruct evbuf_header hdr;\n\tu8 event_qual;\n\tu8 data_id;\n\tu64 reserved2;\n\tu32 event_id;\n\tu16 reserved3;\n\tu8 asa_size;\n\tu8 event_status;\n\tu32 reserved4;\n\tu32 blk_cnt;\n\tu64 asa;\n\tu32 reserved5;\n\tu32 fbn;\n\tu32 reserved6;\n\tu32 lbn;\n\tu16 reserved7;\n\tu16 dbs;\n} __attribute__((packed));\n\nstruct sdias_sccb {\n\tstruct sccb_header hdr;\n\tstruct sdias_evbuf evbuf;\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_metadata {\n\t__u64 filter_off;\n\t__u64 flags;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct security_class_mapping {\n\tconst char *name;\n\tconst char *perms[33];\n};\n\nstruct timezone;\n\nstruct xattr;\n\nstruct sembuf;\n\nunion security_list_options {\n\tint (*binder_set_context_mgr)(const struct cred *);\n\tint (*binder_transaction)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_binder)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_file)(const struct cred *, const struct cred *, const struct file *);\n\tint (*ptrace_access_check)(struct task_struct *, unsigned int);\n\tint (*ptrace_traceme)(struct task_struct *);\n\tint (*capget)(const struct task_struct *, kernel_cap_t *, kernel_cap_t *, kernel_cap_t *);\n\tint (*capset)(struct cred *, const struct cred *, const kernel_cap_t *, const kernel_cap_t *, const kernel_cap_t *);\n\tint (*capable)(const struct cred *, struct user_namespace *, int, unsigned int);\n\tint (*quotactl)(int, int, int, const struct super_block *);\n\tint (*quota_on)(struct dentry *);\n\tint (*syslog)(int);\n\tint (*settime)(const struct timespec64 *, const struct timezone *);\n\tint (*vm_enough_memory)(struct mm_struct *, long int);\n\tint (*bprm_creds_for_exec)(struct linux_binprm *);\n\tint (*bprm_creds_from_file)(struct linux_binprm *, const struct file *);\n\tint (*bprm_check_security)(struct linux_binprm *);\n\tvoid (*bprm_committing_creds)(const struct linux_binprm *);\n\tvoid (*bprm_committed_creds)(const struct linux_binprm *);\n\tint (*fs_context_submount)(struct fs_context *, struct super_block *);\n\tint (*fs_context_dup)(struct fs_context *, struct fs_context *);\n\tint (*fs_context_parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*sb_alloc_security)(struct super_block *);\n\tvoid (*sb_delete)(struct super_block *);\n\tvoid (*sb_free_security)(struct super_block *);\n\tvoid (*sb_free_mnt_opts)(void *);\n\tint (*sb_eat_lsm_opts)(char *, void **);\n\tint (*sb_mnt_opts_compat)(struct super_block *, void *);\n\tint (*sb_remount)(struct super_block *, void *);\n\tint (*sb_kern_mount)(const struct super_block *);\n\tint (*sb_show_options)(struct seq_file *, struct super_block *);\n\tint (*sb_statfs)(struct dentry *);\n\tint (*sb_mount)(const char *, const struct path *, const char *, long unsigned int, void *);\n\tint (*sb_umount)(struct vfsmount *, int);\n\tint (*sb_pivotroot)(const struct path *, const struct path *);\n\tint (*sb_set_mnt_opts)(struct super_block *, void *, long unsigned int, long unsigned int *);\n\tint (*sb_clone_mnt_opts)(const struct super_block *, struct super_block *, long unsigned int, long unsigned int *);\n\tint (*move_mount)(const struct path *, const struct path *);\n\tint (*dentry_init_security)(struct dentry *, int, const struct qstr *, const char **, struct lsm_context *);\n\tint (*dentry_create_files_as)(struct dentry *, int, const struct qstr *, const struct cred *, struct cred *);\n\tint (*path_unlink)(const struct path *, struct dentry *);\n\tint (*path_mkdir)(const struct path *, struct dentry *, umode_t);\n\tint (*path_rmdir)(const struct path *, struct dentry *);\n\tint (*path_mknod)(const struct path *, struct dentry *, umode_t, unsigned int);\n\tvoid (*path_post_mknod)(struct mnt_idmap *, struct dentry *);\n\tint (*path_truncate)(const struct path *);\n\tint (*path_symlink)(const struct path *, struct dentry *, const char *);\n\tint (*path_link)(struct dentry *, const struct path *, struct dentry *);\n\tint (*path_rename)(const struct path *, struct dentry *, const struct path *, struct dentry *, unsigned int);\n\tint (*path_chmod)(const struct path *, umode_t);\n\tint (*path_chown)(const struct path *, kuid_t, kgid_t);\n\tint (*path_chroot)(const struct path *);\n\tint (*path_notify)(const struct path *, u64, unsigned int);\n\tint (*inode_alloc_security)(struct inode *);\n\tvoid (*inode_free_security)(struct inode *);\n\tvoid (*inode_free_security_rcu)(void *);\n\tint (*inode_init_security)(struct inode *, struct inode *, const struct qstr *, struct xattr *, int *);\n\tint (*inode_init_security_anon)(struct inode *, const struct qstr *, const struct inode *);\n\tint (*inode_create)(struct inode *, struct dentry *, umode_t);\n\tvoid (*inode_post_create_tmpfile)(struct mnt_idmap *, struct inode *);\n\tint (*inode_link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_unlink)(struct inode *, struct dentry *);\n\tint (*inode_symlink)(struct inode *, struct dentry *, const char *);\n\tint (*inode_mkdir)(struct inode *, struct dentry *, umode_t);\n\tint (*inode_rmdir)(struct inode *, struct dentry *);\n\tint (*inode_mknod)(struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*inode_rename)(struct inode *, struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_readlink)(struct dentry *);\n\tint (*inode_follow_link)(struct dentry *, struct inode *, bool);\n\tint (*inode_permission)(struct inode *, int);\n\tint (*inode_setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tvoid (*inode_post_setattr)(struct mnt_idmap *, struct dentry *, int);\n\tint (*inode_getattr)(const struct path *);\n\tint (*inode_xattr_skipcap)(const char *);\n\tint (*inode_setxattr)(struct mnt_idmap *, struct dentry *, const char *, const void *, size_t, int);\n\tvoid (*inode_post_setxattr)(struct dentry *, const char *, const void *, size_t, int);\n\tint (*inode_getxattr)(struct dentry *, const char *);\n\tint (*inode_listxattr)(struct dentry *);\n\tint (*inode_removexattr)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_removexattr)(struct dentry *, const char *);\n\tint (*inode_file_setattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_file_getattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_set_acl)(struct mnt_idmap *, struct dentry *, const char *, struct posix_acl *);\n\tvoid (*inode_post_set_acl)(struct dentry *, const char *, struct posix_acl *);\n\tint (*inode_get_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_need_killpriv)(struct dentry *);\n\tint (*inode_killpriv)(struct mnt_idmap *, struct dentry *);\n\tint (*inode_getsecurity)(struct mnt_idmap *, struct inode *, const char *, void **, bool);\n\tint (*inode_setsecurity)(struct inode *, const char *, const void *, size_t, int);\n\tint (*inode_listsecurity)(struct inode *, char *, size_t);\n\tvoid (*inode_getlsmprop)(struct inode *, struct lsm_prop *);\n\tint (*inode_copy_up)(struct dentry *, struct cred **);\n\tint (*inode_copy_up_xattr)(struct dentry *, const char *);\n\tint (*inode_setintegrity)(const struct inode *, enum lsm_integrity_type, const void *, size_t);\n\tint (*kernfs_init_security)(struct kernfs_node *, struct kernfs_node *);\n\tint (*file_permission)(struct file *, int);\n\tint (*file_alloc_security)(struct file *);\n\tvoid (*file_release)(struct file *);\n\tvoid (*file_free_security)(struct file *);\n\tint (*file_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*file_ioctl_compat)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap_addr)(long unsigned int);\n\tint (*mmap_file)(struct file *, long unsigned int, long unsigned int, long unsigned int);\n\tint (*file_mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int);\n\tint (*file_lock)(struct file *, unsigned int);\n\tint (*file_fcntl)(struct file *, unsigned int, long unsigned int);\n\tvoid (*file_set_fowner)(struct file *);\n\tint (*file_send_sigiotask)(struct task_struct *, struct fown_struct *, int);\n\tint (*file_receive)(struct file *);\n\tint (*file_open)(struct file *);\n\tint (*file_post_open)(struct file *, int);\n\tint (*file_truncate)(struct file *);\n\tint (*task_alloc)(struct task_struct *, u64);\n\tvoid (*task_free)(struct task_struct *);\n\tint (*cred_alloc_blank)(struct cred *, gfp_t);\n\tvoid (*cred_free)(struct cred *);\n\tint (*cred_prepare)(struct cred *, const struct cred *, gfp_t);\n\tvoid (*cred_transfer)(struct cred *, const struct cred *);\n\tvoid (*cred_getsecid)(const struct cred *, u32 *);\n\tvoid (*cred_getlsmprop)(const struct cred *, struct lsm_prop *);\n\tint (*kernel_act_as)(struct cred *, u32);\n\tint (*kernel_create_files_as)(struct cred *, struct inode *);\n\tint (*kernel_module_request)(char *);\n\tint (*kernel_load_data)(enum kernel_load_data_id, bool);\n\tint (*kernel_post_load_data)(char *, loff_t, enum kernel_load_data_id, char *);\n\tint (*kernel_read_file)(struct file *, enum kernel_read_file_id, bool);\n\tint (*kernel_post_read_file)(struct file *, char *, loff_t, enum kernel_read_file_id);\n\tint (*task_fix_setuid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgroups)(struct cred *, const struct cred *);\n\tint (*task_setpgid)(struct task_struct *, pid_t);\n\tint (*task_getpgid)(struct task_struct *);\n\tint (*task_getsid)(struct task_struct *);\n\tvoid (*current_getlsmprop_subj)(struct lsm_prop *);\n\tvoid (*task_getlsmprop_obj)(struct task_struct *, struct lsm_prop *);\n\tint (*task_setnice)(struct task_struct *, int);\n\tint (*task_setioprio)(struct task_struct *, int);\n\tint (*task_getioprio)(struct task_struct *);\n\tint (*task_prlimit)(const struct cred *, const struct cred *, unsigned int);\n\tint (*task_setrlimit)(struct task_struct *, unsigned int, struct rlimit *);\n\tint (*task_setscheduler)(struct task_struct *);\n\tint (*task_getscheduler)(struct task_struct *);\n\tint (*task_movememory)(struct task_struct *);\n\tint (*task_kill)(struct task_struct *, struct kernel_siginfo *, int, const struct cred *);\n\tint (*task_prctl)(int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tvoid (*task_to_inode)(struct task_struct *, struct inode *);\n\tint (*userns_create)(const struct cred *);\n\tint (*ipc_permission)(struct kern_ipc_perm *, short int);\n\tvoid (*ipc_getlsmprop)(struct kern_ipc_perm *, struct lsm_prop *);\n\tint (*msg_msg_alloc_security)(struct msg_msg *);\n\tvoid (*msg_msg_free_security)(struct msg_msg *);\n\tint (*msg_queue_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*msg_queue_free_security)(struct kern_ipc_perm *);\n\tint (*msg_queue_associate)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgctl)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgsnd)(struct kern_ipc_perm *, struct msg_msg *, int);\n\tint (*msg_queue_msgrcv)(struct kern_ipc_perm *, struct msg_msg *, struct task_struct *, long int, int);\n\tint (*shm_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*shm_free_security)(struct kern_ipc_perm *);\n\tint (*shm_associate)(struct kern_ipc_perm *, int);\n\tint (*shm_shmctl)(struct kern_ipc_perm *, int);\n\tint (*shm_shmat)(struct kern_ipc_perm *, char *, int);\n\tint (*sem_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*sem_free_security)(struct kern_ipc_perm *);\n\tint (*sem_associate)(struct kern_ipc_perm *, int);\n\tint (*sem_semctl)(struct kern_ipc_perm *, int);\n\tint (*sem_semop)(struct kern_ipc_perm *, struct sembuf *, unsigned int, int);\n\tint (*netlink_send)(struct sock *, struct sk_buff *);\n\tvoid (*d_instantiate)(struct dentry *, struct inode *);\n\tint (*getselfattr)(unsigned int, struct lsm_ctx *, u32 *, u32);\n\tint (*setselfattr)(unsigned int, struct lsm_ctx *, u32, u32);\n\tint (*getprocattr)(struct task_struct *, const char *, char **);\n\tint (*setprocattr)(const char *, void *, size_t);\n\tint (*ismaclabel)(const char *);\n\tint (*secid_to_secctx)(u32, struct lsm_context *);\n\tint (*lsmprop_to_secctx)(struct lsm_prop *, struct lsm_context *);\n\tint (*secctx_to_secid)(const char *, u32, u32 *);\n\tvoid (*release_secctx)(struct lsm_context *);\n\tvoid (*inode_invalidate_secctx)(struct inode *);\n\tint (*inode_notifysecctx)(struct inode *, void *, u32);\n\tint (*inode_setsecctx)(struct dentry *, void *, u32);\n\tint (*inode_getsecctx)(struct inode *, struct lsm_context *);\n\tint (*post_notification)(const struct cred *, const struct cred *, struct watch_notification *);\n\tint (*watch_key)(struct key *);\n\tint (*unix_stream_connect)(struct sock *, struct sock *, struct sock *);\n\tint (*unix_may_send)(struct socket *, struct socket *);\n\tint (*socket_create)(int, int, int, int);\n\tint (*socket_post_create)(struct socket *, int, int, int, int);\n\tint (*socket_socketpair)(struct socket *, struct socket *);\n\tint (*socket_bind)(struct socket *, struct sockaddr *, int);\n\tint (*socket_connect)(struct socket *, struct sockaddr *, int);\n\tint (*socket_listen)(struct socket *, int);\n\tint (*socket_accept)(struct socket *, struct socket *);\n\tint (*socket_sendmsg)(struct socket *, struct msghdr *, int);\n\tint (*socket_recvmsg)(struct socket *, struct msghdr *, int, int);\n\tint (*socket_getsockname)(struct socket *);\n\tint (*socket_getpeername)(struct socket *);\n\tint (*socket_getsockopt)(struct socket *, int, int);\n\tint (*socket_setsockopt)(struct socket *, int, int);\n\tint (*socket_shutdown)(struct socket *, int);\n\tint (*socket_sock_rcv_skb)(struct sock *, struct sk_buff *);\n\tint (*socket_getpeersec_stream)(struct socket *, sockptr_t, sockptr_t, unsigned int);\n\tint (*socket_getpeersec_dgram)(struct socket *, struct sk_buff *, u32 *);\n\tint (*sk_alloc_security)(struct sock *, int, gfp_t);\n\tvoid (*sk_free_security)(struct sock *);\n\tvoid (*sk_clone_security)(const struct sock *, struct sock *);\n\tvoid (*sk_getsecid)(const struct sock *, u32 *);\n\tvoid (*sock_graft)(struct sock *, struct socket *);\n\tint (*inet_conn_request)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*inet_csk_clone)(struct sock *, const struct request_sock *);\n\tvoid (*inet_conn_established)(struct sock *, struct sk_buff *);\n\tint (*secmark_relabel_packet)(u32);\n\tvoid (*secmark_refcount_inc)(void);\n\tvoid (*secmark_refcount_dec)(void);\n\tvoid (*req_classify_flow)(const struct request_sock *, struct flowi_common *);\n\tint (*tun_dev_alloc_security)(void *);\n\tint (*tun_dev_create)(void);\n\tint (*tun_dev_attach_queue)(void *);\n\tint (*tun_dev_attach)(struct sock *, void *);\n\tint (*tun_dev_open)(void *);\n\tint (*sctp_assoc_request)(struct sctp_association *, struct sk_buff *);\n\tint (*sctp_bind_connect)(struct sock *, int, struct sockaddr *, int);\n\tvoid (*sctp_sk_clone)(struct sctp_association *, struct sock *, struct sock *);\n\tint (*sctp_assoc_established)(struct sctp_association *, struct sk_buff *);\n\tint (*mptcp_add_subflow)(struct sock *, struct sock *);\n\tint (*key_alloc)(struct key *, const struct cred *, long unsigned int);\n\tint (*key_permission)(key_ref_t, const struct cred *, enum key_need_perm);\n\tint (*key_getsecurity)(struct key *, char **);\n\tvoid (*key_post_create_or_update)(struct key *, struct key *, const void *, size_t, long unsigned int, bool);\n\tint (*audit_rule_init)(u32, u32, char *, void **, gfp_t);\n\tint (*audit_rule_known)(struct audit_krule *);\n\tint (*audit_rule_match)(struct lsm_prop *, u32, u32, void *);\n\tvoid (*audit_rule_free)(void *);\n\tint (*bpf)(int, union bpf_attr *, unsigned int, bool);\n\tint (*bpf_map)(struct bpf_map *, fmode_t);\n\tint (*bpf_prog)(struct bpf_prog *);\n\tint (*bpf_map_create)(struct bpf_map *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_map_free)(struct bpf_map *);\n\tint (*bpf_prog_load)(struct bpf_prog *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_prog_free)(struct bpf_prog *);\n\tint (*bpf_token_create)(struct bpf_token *, union bpf_attr *, const struct path *);\n\tvoid (*bpf_token_free)(struct bpf_token *);\n\tint (*bpf_token_cmd)(const struct bpf_token *, enum bpf_cmd);\n\tint (*bpf_token_capable)(const struct bpf_token *, int);\n\tint (*locked_down)(enum lockdown_reason);\n\tint (*perf_event_open)(int);\n\tint (*perf_event_alloc)(struct perf_event *);\n\tint (*perf_event_read)(struct perf_event *);\n\tint (*perf_event_write)(struct perf_event *);\n\tint (*uring_override_creds)(const struct cred *);\n\tint (*uring_sqpoll)(void);\n\tint (*uring_cmd)(struct io_uring_cmd *);\n\tint (*uring_allowed)(void);\n\tvoid (*initramfs_populated)(void);\n\tint (*bdev_alloc_security)(struct block_device *);\n\tvoid (*bdev_free_security)(struct block_device *);\n\tint (*bdev_setintegrity)(struct block_device *, enum lsm_integrity_type, const void *, size_t);\n\tvoid *lsm_func_addr;\n};\n\nstruct security_hook_list {\n\tstruct lsm_static_call *scalls;\n\tunion security_list_options hook;\n\tconst struct lsm_id *lsmid;\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nstruct sel_netif {\n\tstruct list_head list;\n\tstruct netif_security_struct nsec;\n\tstruct callback_head callback_head;\n};\n\nstruct sel_netnode {\n\tstruct netnode_security_struct nsec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netnode_bkt {\n\tunsigned int size;\n\tstruct list_head list;\n};\n\nstruct sel_netport {\n\tstruct netport_security_struct psec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netport_bkt {\n\tint size;\n\tstruct list_head list;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct selinux_audit_data {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tu32 requested;\n\tu32 audited;\n\tu32 denied;\n\tint result;\n};\n\nstruct selinux_audit_rule {\n\tu32 au_seqno;\n\tstruct context au_ctxt;\n};\n\nstruct selinux_avc {\n\tunsigned int avc_cache_threshold;\n\tstruct avc_cache avc_cache;\n};\n\nstruct selinux_fs_info {\n\tstruct dentry *bool_dir;\n\tunsigned int bool_num;\n\tchar **bool_pending_names;\n\tint *bool_pending_values;\n\tstruct dentry *class_dir;\n\tlong unsigned int last_class_ino;\n\tbool policy_opened;\n\tlong unsigned int last_ino;\n\tstruct super_block *sb;\n};\n\nstruct selinux_kernel_status {\n\tu32 version;\n\tu32 sequence;\n\tu32 enforcing;\n\tu32 policyload;\n\tu32 deny_unknown;\n};\n\nstruct selinux_policy;\n\nstruct selinux_policy_convert_data;\n\nstruct selinux_load_state {\n\tstruct selinux_policy *policy;\n\tstruct selinux_policy_convert_data *convert_data;\n};\n\nstruct selinux_mapping;\n\nstruct selinux_map {\n\tstruct selinux_mapping *mapping;\n\tu16 size;\n};\n\nstruct selinux_mapping {\n\tu16 value;\n\tu16 num_perms;\n\tu32 perms[32];\n};\n\nstruct selinux_mnt_opts {\n\tu32 fscontext_sid;\n\tu32 context_sid;\n\tu32 rootcontext_sid;\n\tu32 defcontext_sid;\n};\n\nstruct sidtab;\n\nstruct selinux_policy {\n\tstruct sidtab *sidtab;\n\tstruct policydb policydb;\n\tstruct selinux_map map;\n\tu32 latest_granting;\n};\n\nstruct sidtab_convert_params {\n\tstruct convert_context_args *args;\n\tstruct sidtab *target;\n};\n\nstruct selinux_policy_convert_data {\n\tstruct convert_context_args args;\n\tstruct sidtab_convert_params sidtab_params;\n};\n\nstruct selinux_state {\n\tbool enforcing;\n\tbool initialized;\n\tbool policycap[15];\n\tstruct page *status_page;\n\tstruct mutex status_lock;\n\tstruct selinux_policy *policy;\n\tstruct mutex policy_mutex;\n};\n\nstruct selnl_msg_policyload {\n\t__u32 seqno;\n};\n\nstruct selnl_msg_setenforce {\n\t__s32 val;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\ttime64_t sem_otime;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\tlong int sem_otime;\n\tlong int sem_ctime;\n\tlong unsigned int sem_nsems;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct send_ctx {\n\tstruct file *send_filp;\n\tloff_t send_off;\n\tchar *send_buf;\n\tu32 send_size;\n\tu32 send_max_size;\n\tbool put_data;\n\tstruct page **send_buf_pages;\n\tu64 flags;\n\tu32 proto;\n\tstruct btrfs_root *send_root;\n\tstruct btrfs_root *parent_root;\n\tstruct clone_root *clone_roots;\n\tint clone_roots_cnt;\n\tstruct btrfs_path *left_path;\n\tstruct btrfs_path *right_path;\n\tstruct btrfs_key *cmp_key;\n\tu64 last_reloc_trans;\n\tu64 cur_ino;\n\tu64 cur_inode_gen;\n\tu64 cur_inode_size;\n\tu64 cur_inode_mode;\n\tu64 cur_inode_rdev;\n\tu64 cur_inode_last_extent;\n\tu64 cur_inode_next_write_offset;\n\tbool cur_inode_new;\n\tbool cur_inode_new_gen;\n\tbool cur_inode_deleted;\n\tbool ignore_cur_inode;\n\tbool cur_inode_needs_verity;\n\tvoid *verity_descriptor;\n\tu64 send_progress;\n\tstruct list_head new_refs;\n\tstruct list_head deleted_refs;\n\tstruct btrfs_lru_cache name_cache;\n\tstruct inode *cur_inode;\n\tstruct file_ra_state ra;\n\tu64 page_cache_clear_start;\n\tbool clean_page_cache;\n\tstruct rb_root pending_dir_moves;\n\tstruct rb_root waiting_dir_moves;\n\tstruct rb_root orphan_dirs;\n\tstruct rb_root rbtree_new_refs;\n\tstruct rb_root rbtree_deleted_refs;\n\tstruct btrfs_lru_cache backref_cache;\n\tu64 backref_cache_last_reloc_trans;\n\tstruct btrfs_lru_cache dir_created_cache;\n\tstruct btrfs_lru_cache dir_utimes_cache;\n\tstruct fs_path cur_inode_path;\n};\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n\tbool has_siginfo;\n\tstruct kernel_siginfo info;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct seqcount_rwlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_rwlock seqcount_rwlock_t;\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_in_rdev {\n\tstruct rb_root_cached serial_rb;\n\tspinlock_t serial_lock;\n\twait_queue_head_t serial_io_wait;\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_event_iter {\n\tenum set_event_iter_type type;\n\tunion {\n\t\tstruct trace_event_file *file;\n\t\tstruct event_mod_load *event_mod;\n\t};\n};\n\nstruct set_schib_struct {\n\tu32 mme;\n\tint mbfc;\n\tlong unsigned int address;\n\twait_queue_head_t wait;\n\tint ret;\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_device {\n\tstruct scsi_device *device;\n\twait_queue_head_t open_wait;\n\tstruct mutex open_rel_lock;\n\tint sg_tablesize;\n\tu32 index;\n\tstruct list_head sfds;\n\trwlock_t sfd_lock;\n\tatomic_t detaching;\n\tbool exclude;\n\tint open_cnt;\n\tchar sgdebug;\n\tchar name[32];\n\tstruct cdev *cdev;\n\tstruct kref d_ref;\n};\n\ntypedef struct sg_device Sg_device;\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_scatter_hold {\n\tshort unsigned int k_use_sg;\n\tunsigned int sglist_len;\n\tunsigned int bufflen;\n\tstruct page **pages;\n\tint page_order;\n\tchar dio_in_use;\n\tunsigned char cmd_opcode;\n};\n\ntypedef struct sg_scatter_hold Sg_scatter_hold;\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\ntypedef struct sg_io_hdr sg_io_hdr_t;\n\nstruct sg_fd;\n\nstruct sg_request {\n\tstruct list_head entry;\n\tstruct sg_fd *parentfp;\n\tSg_scatter_hold data;\n\tsg_io_hdr_t header;\n\tunsigned char sense_b[96];\n\tchar res_used;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar done;\n\tstruct request *rq;\n\tstruct bio *bio;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_request Sg_request;\n\nstruct sg_fd {\n\tstruct list_head sfd_siblings;\n\tstruct sg_device *parentdp;\n\twait_queue_head_t read_wait;\n\trwlock_t rq_list_lock;\n\tstruct mutex f_mutex;\n\tint timeout;\n\tint timeout_user;\n\tSg_scatter_hold reserve;\n\tstruct list_head rq_list;\n\tstruct fasync_struct *async_qp;\n\tSg_request req_arr[16];\n\tchar force_packid;\n\tchar cmd_q;\n\tunsigned char next_cmd_len;\n\tchar keep_orphan;\n\tchar mmap_called;\n\tchar res_in_use;\n\tstruct kref f_ref;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_fd Sg_fd;\n\nstruct sg_header {\n\tint pack_len;\n\tint reply_len;\n\tint pack_id;\n\tint result;\n\tunsigned int twelve_byte: 1;\n\tunsigned int target_status: 5;\n\tunsigned int host_status: 8;\n\tunsigned int driver_status: 8;\n\tunsigned int other_flags: 10;\n\tunsigned char sense_buffer[16];\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sg_proc_deviter {\n\tloff_t index;\n\tsize_t max;\n};\n\nstruct sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\ntypedef struct sg_req_info sg_req_info_t;\n\nstruct sg_scsi_id {\n\tint host_no;\n\tint channel;\n\tint scsi_id;\n\tint lun;\n\tint scsi_type;\n\tshort int h_cmd_per_lun;\n\tshort int d_queue_depth;\n\tint unused[2];\n};\n\ntypedef struct sg_scsi_id sg_scsi_id_t;\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha384_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct sha3_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct shake_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct share_check {\n\tstruct btrfs_backref_share_check_ctx *ctx;\n\tstruct btrfs_root *root;\n\tu64 inum;\n\tu64 data_bytenr;\n\tu64 data_extent_gen;\n\tint share_count;\n\tint self_ref_count;\n\tbool have_delayed_delete_refs;\n};\n\nstruct shared_policy {\n\tstruct rb_root root;\n\trwlock_t lock;\n};\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*export_core)(struct shash_desc *, void *);\n\tint (*import_core)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tint (*clone_tfm)(struct crypto_shash *, struct crypto_shash *);\n\tunsigned int descsize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int digestsize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct hash_alg_common halg;\n\t};\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[120];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tstruct dquot *i_dquot[3];\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct unicode_map;\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tstruct shmem_quota_limits qlimits;\n\tstruct unicode_map *encoding;\n\tbool strict_encoding;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\t__kernel_size_t shm_segsz;\n\tlong int shm_atime;\n\tlong int shm_dtime;\n\tlong int shm_ctime;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tint id;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct shrinker_info_unit;\n\nstruct shrinker_info {\n\tstruct callback_head rcu;\n\tint map_nr_max;\n\tstruct shrinker_info_unit *unit[0];\n};\n\nstruct shrinker_info_unit {\n\tatomic_long_t nr_deferred[64];\n\tlong unsigned int map[1];\n};\n\nstruct shutdown_trigger;\n\nstruct shutdown_action {\n\tchar *name;\n\tvoid (*fn)(struct shutdown_trigger *);\n\tint (*init)(void);\n\tint init_rc;\n};\n\nstruct shutdown_trigger {\n\tchar *name;\n\tstruct shutdown_action *action;\n};\n\nstruct sidtab_node_inner;\n\nstruct sidtab_node_leaf;\n\nunion sidtab_entry_inner {\n\tstruct sidtab_node_inner *ptr_inner;\n\tstruct sidtab_node_leaf *ptr_leaf;\n};\n\nstruct sidtab_str_cache;\n\nstruct sidtab_entry {\n\tu32 sid;\n\tu32 hash;\n\tstruct context context;\n\tstruct sidtab_str_cache *cache;\n\tstruct hlist_node list;\n};\n\nstruct sidtab_isid_entry {\n\tint set;\n\tstruct sidtab_entry entry;\n};\n\nstruct sidtab {\n\tunion sidtab_entry_inner roots[4];\n\tu32 count;\n\tstruct sidtab_convert_params *convert;\n\tbool frozen;\n\tspinlock_t lock;\n\tu32 cache_free_slots;\n\tstruct list_head cache_lru_list;\n\tspinlock_t cache_lock;\n\tstruct sidtab_isid_entry isids[27];\n\tstruct hlist_head context_to_sid[512];\n};\n\nstruct sidtab_node_inner {\n\tunion sidtab_entry_inner entries[512];\n};\n\nstruct sidtab_node_leaf {\n\tstruct sidtab_entry entries[39];\n};\n\nstruct sidtab_str_cache {\n\tstruct callback_head rcu_member;\n\tstruct list_head lru_member;\n\tstruct sidtab_entry *parent;\n\tu32 len;\n\tchar str[0];\n};\n\nstruct sie_page {\n\tstruct kvm_s390_sie_block sie_block;\n\tstruct mcck_volatile_info mcck_info;\n\t__u8 reserved218[360];\n\t__u64 pv_grregs[16];\n\t__u8 reserved400[512];\n\tstruct kvm_s390_itdb itdb;\n\t__u8 reserved700[2304];\n};\n\nstruct sie_page2 {\n\t__u64 fac_list[256];\n\tstruct kvm_s390_crypto_cb crycb;\n\tstruct kvm_s390_gisa gisa;\n\tstruct kvm *kvm;\n\tu8 reserved928[1752];\n};\n\nstruct sig_alg {\n\tint (*sign)(struct crypto_sig *, const void *, unsigned int, void *, unsigned int);\n\tint (*verify)(struct crypto_sig *, const void *, unsigned int, const void *, unsigned int);\n\tint (*set_pub_key)(struct crypto_sig *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_sig *, const void *, unsigned int);\n\tunsigned int (*key_size)(struct crypto_sig *);\n\tunsigned int (*digest_size)(struct crypto_sig *);\n\tunsigned int (*max_size)(struct crypto_sig *);\n\tint (*init)(struct crypto_sig *);\n\tvoid (*exit)(struct crypto_sig *);\n\tstruct crypto_alg base;\n};\n\nstruct sig_instance {\n\tvoid (*free)(struct sig_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[72];\n\t\t\tstruct crypto_instance base;\n\t\t};\n\t\tstruct sig_alg alg;\n\t};\n};\n\nstruct sig_testvec {\n\tconst unsigned char *key;\n\tconst unsigned char *params;\n\tconst unsigned char *m;\n\tconst unsigned char *c;\n\tunsigned int key_len;\n\tunsigned int param_len;\n\tunsigned int m_size;\n\tunsigned int c_size;\n\tbool public_key_vec;\n\tenum OID algo;\n};\n\nstruct sigcontext {\n\tlong unsigned int oldmask[1];\n\t_sigregs *sregs;\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sigframe {\n\t__u8 callee_used_stack[160];\n\tstruct sigcontext sc;\n\t_sigregs sregs;\n\tint signo;\n\t_sigregs_ext sregs_ext;\n\t__u16 svc_insn;\n};\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {\n\tu64 rchar;\n\tu64 wchar;\n\tu64 syscr;\n\tu64 syscw;\n\tu64 read_bytes;\n\tu64 write_bytes;\n\tu64 cancelled_write_bytes;\n};\n\nstruct taskstats;\n\nstruct tty_audit_buf;\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tstruct autogroup *autogroup;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct pacct_struct pacct;\n\tstruct taskstats *stats;\n\tunsigned int audit_tty;\n\tstruct tty_audit_buf *tty_audit_buf;\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct signature_hdr {\n\tuint8_t version;\n\tuint32_t timestamp;\n\tuint8_t algo;\n\tuint8_t hash;\n\tuint8_t keyid[8];\n\tuint8_t nmpi;\n\tchar mpi[0];\n} __attribute__((packed));\n\nstruct signature_v2_hdr {\n\tuint8_t type;\n\tuint8_t version;\n\tuint8_t hash_algo;\n\t__be32 keyid;\n\t__be16 sig_size;\n\tuint8_t sig[0];\n} __attribute__((packed));\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct sioc_sg_req {\n\tstruct in_addr src;\n\tstruct in_addr grp;\n\tlong unsigned int pktcnt;\n\tlong unsigned int bytecnt;\n\tlong unsigned int wrong_if;\n};\n\nstruct sioc_vif_req {\n\tvifi_t vifi;\n\tlong unsigned int icount;\n\tlong unsigned int ocount;\n\tlong unsigned int ibytes;\n\tlong unsigned int obytes;\n};\n\nstruct zs_size_stat {\n\tlong unsigned int objs[14];\n};\n\nstruct size_class {\n\tspinlock_t lock;\n\tstruct list_head fullness_list[12];\n\tint size;\n\tint objs_per_zspage;\n\tint pages_per_zspage;\n\tunsigned int index;\n\tstruct zs_size_stat stats;\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct sk_security_struct {\n\tu32 sid;\n\tu32 peer_sid;\n\tu16 sclass;\n\tenum {\n\t\tSCTP_ASSOC_UNSET = 0,\n\t\tSCTP_ASSOC_SET = 1,\n\t} sctp_assoc_state;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct skb_ext {\n\trefcount_t refcnt;\n\tu8 offset[4];\n\tu8 chunks;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*export)(struct skcipher_request *, void *);\n\tint (*import)(struct skcipher_request *, const void *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int walksize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int min_keysize;\n\t\t\tunsigned int max_keysize;\n\t\t\tunsigned int ivsize;\n\t\t\tunsigned int chunksize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct skcipher_alg_common co;\n\t};\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[88];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int nbytes;\n\tunsigned int total;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct skey_region {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct sl_element {\n\tdma64_t sbal;\n};\n\nstruct sl {\n\tstruct sl_element element[128];\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int obj_exts;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct slabobj_ext {\n\tstruct obj_cgroup *objcg;\n};\n\nstruct slibe {\n\tu64 parms;\n};\n\nstruct slib {\n\tu64 nsliba;\n\tu64 sla;\n\tu64 slsba;\n\tu8 res[1000];\n\tstruct slibe slibe[128];\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct tcp_sock;\n\nstruct smc_hs_ctrl {\n\tstruct list_head list;\n\tstruct module *owner;\n\tchar name[16];\n\tint flags;\n\tint (*syn_option)(struct tcp_sock *);\n\tint (*synack_option)(const struct tcp_sock *, struct inet_request_sock *);\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct snapshot_context {\n\tstruct tracing_map_elt *elt;\n\tvoid *key;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct sockaddr_xdp {\n\t__u16 sxdp_family;\n\t__u16 sxdp_flags;\n\t__u32 sxdp_ifindex;\n\t__u32 sxdp_queue_id;\n\t__u32 sxdp_shared_umem_fd;\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int input_queue_head;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t defer_csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct solaris_x86_slice {\n\t__le16 s_tag;\n\t__le16 s_flag;\n\t__le32 s_start;\n\t__le32 s_size;\n};\n\nstruct solaris_x86_vtoc {\n\tunsigned int v_bootinfo[3];\n\t__le32 v_sanity;\n\t__le32 v_version;\n\tchar v_volume[8];\n\t__le16 v_sectorsz;\n\t__le16 v_nparts;\n\tunsigned int v_reserved[10];\n\tstruct solaris_x86_slice v_slice[16];\n\tunsigned int timestamp[16];\n\tchar v_asciilabel[128];\n};\n\nstruct sp_node {\n\tstruct rb_node nd;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct mempolicy *policy;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct space_run {\n\tu64 start;\n\tu64 end;\n};\n\nstruct spin_wait {\n\tstruct spin_wait *next;\n\tstruct spin_wait *prev;\n\tint node_id;\n\tlong: 64;\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nunion split_register {\n\tu64 u64;\n\tu32 u32[2];\n\tu16 u16[4];\n\ts64 s64;\n\ts32 s32[2];\n\ts16 s16[4];\n};\n\nstruct squashfs_super_block {\n\t__le32 s_magic;\n\t__le32 inodes;\n\t__le32 mkfs_time;\n\t__le32 block_size;\n\t__le32 fragments;\n\t__le16 compression;\n\t__le16 block_log;\n\t__le16 flags;\n\t__le16 no_ids;\n\t__le16 s_major;\n\t__le16 s_minor;\n\t__le64 root_inode;\n\t__le64 bytes_used;\n\t__le64 id_table_start;\n\t__le64 xattr_id_table_start;\n\t__le64 inode_table_start;\n\t__le64 directory_table_start;\n\t__le64 fragment_table_start;\n\t__le64 lookup_table_start;\n};\n\nstruct sr6_tlv {\n\t__u8 type;\n\t__u8 len;\n\t__u8 data[0];\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_node;\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[3];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[0];\n};\n\nstruct stack_frame_user {\n\tlong unsigned int back_chain;\n\tlong unsigned int empty1[5];\n\tlong unsigned int gprs[10];\n\tlong unsigned int empty2[4];\n};\n\nstruct stack_frame_vdso_wrapper {\n\tstruct stack_frame_user sf;\n\tlong unsigned int return_address;\n};\n\nstruct stack_info {\n\tenum stack_type type;\n\tlong unsigned int begin;\n\tlong unsigned int end;\n};\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tu64 data[0];\n};\n\nstruct stack_record {\n\tstruct list_head hash_list;\n\tu32 hash;\n\tu32 size;\n\tunion handle_parts handle;\n\trefcount_t count;\n\tunion {\n\t\tlong unsigned int entries[64];\n\t\tstruct {\n\t\t\tstruct list_head free_list;\n\t\t\tlong unsigned int rcu_state;\n\t\t};\n\t};\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\tlong unsigned int st_dev;\n\tlong unsigned int st_ino;\n\tlong unsigned int st_nlink;\n\tunsigned int st_mode;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tunsigned int __pad1;\n\tlong unsigned int st_rdev;\n\tlong unsigned int st_size;\n\tlong unsigned int st_atime;\n\tlong unsigned int st_atime_nsec;\n\tlong unsigned int st_mtime;\n\tlong unsigned int st_mtime_nsec;\n\tlong unsigned int st_ctime;\n\tlong unsigned int st_ctime_nsec;\n\tlong unsigned int st_blksize;\n\tlong int st_blocks;\n\tlong unsigned int __unused[3];\n};\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct statfs {\n\tunsigned int f_type;\n\tunsigned int f_bsize;\n\tlong unsigned int f_blocks;\n\tlong unsigned int f_bfree;\n\tlong unsigned int f_bavail;\n\tlong unsigned int f_files;\n\tlong unsigned int f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tunsigned int f_namelen;\n\tunsigned int f_frsize;\n\tunsigned int f_flags;\n\tunsigned int f_spare[5];\n};\n\nstruct statfs64 {\n\tunsigned int f_type;\n\tunsigned int f_bsize;\n\tlong long unsigned int f_blocks;\n\tlong long unsigned int f_bfree;\n\tlong long unsigned int f_bavail;\n\tlong long unsigned int f_files;\n\tlong long unsigned int f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tunsigned int f_namelen;\n\tunsigned int f_frsize;\n\tunsigned int f_flags;\n\tunsigned int f_spare[5];\n};\n\nstruct static_call_key {\n\tvoid *func;\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_tree_desc_s {\n\tconst ct_data *static_tree;\n\tconst int *extra_bits;\n\tint extra_base;\n\tint elems;\n\tint max_length;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct sthyi_info {\n\tvoid *info;\n\tlong unsigned int end;\n};\n\nstruct sthyi_sctns {\n\tstruct hdr_sctn hdr;\n\tstruct mac_sctn mac;\n\tstruct par_sctn par;\n};\n\nstruct stlck_data {\n\tstruct completion done;\n\tint rc;\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct stp_irq_parm {\n\tshort: 14;\n\tu32 tsc: 1;\n\tu32 lac: 1;\n\tu32 tcpc: 1;\n};\n\nstruct stp_lsoib {\n\tu32 p: 1;\n\tint: 31;\n\ts32 also: 16;\n\ts32 nlso: 16;\n\tu64 nlsout;\n};\n\nstruct stp_proto {\n\tunsigned char group_address[6];\n\tvoid (*rcv)(const struct stp_proto *, struct sk_buff *, struct net_device *);\n\tvoid *data;\n};\n\nstruct stp_sstpi {\n\tint: 32;\n\tu32 tu: 1;\n\tu32 lu: 1;\n\tchar: 6;\n\tu32 stratum: 8;\n\tu32 vbits: 16;\n\tu32 leaps: 16;\n\tu32 tmd: 4;\n\tu32 ctn: 4;\n\tchar: 3;\n\tu32 c: 1;\n\tu32 tst: 4;\n\tu32 tzo: 16;\n\tu32 dsto: 16;\n\tu32 ctrl: 16;\n\tint: 0;\n\tu32 tto;\n\tint: 32;\n\tu32 ctnid[3];\n\tint: 32;\n\tu64 todoff;\n\tu32 rsvd[50];\n} __attribute__((packed));\n\nstruct stp_tzib {\n\tu32 tzan: 16;\n\tint: 16;\n\tu32 tzo: 16;\n\tu32 dsto: 16;\n\tu32 stn;\n\tu32 dstn;\n\tu64 dst_on_alg;\n\tu64 dst_off_alg;\n};\n\nstruct stp_tcpib {\n\tu32 atcode: 4;\n\tu32 ntcode: 4;\n\tu32 d: 1;\n\ts32 tto;\n\tstruct stp_tzib atzib;\n\tstruct stp_tzib ntzib;\n\ts32 adst_offset: 16;\n\ts32 ndst_offset: 16;\n\tu32 rsvd1;\n\tu64 ntzib_update;\n\tu64 ndsto_update;\n};\n\nstruct stp_stzi {\n\tu32 rsvd0[3];\n\tu64 data_ts;\n\tu32 rsvd1[22];\n\tstruct stp_tcpib tcpib;\n\tstruct stp_lsoib lsoib;\n} __attribute__((packed));\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct stripe {\n\tstruct dm_dev *dev;\n\tsector_t physical_start;\n\tatomic_t error_count;\n};\n\nstruct stripe_c {\n\tuint32_t stripes;\n\tint stripes_shift;\n\tsector_t stripe_width;\n\tuint32_t chunk_size;\n\tint chunk_size_shift;\n\tstruct dm_target *ti;\n\tstruct work_struct trigger_event;\n\tstruct stripe stripe[0];\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct stsi_file {\n\tconst struct file_operations *fops;\n\tchar *name;\n};\n\nstruct subchannel {\n\tstruct subchannel_id schid;\n\tspinlock_t lock;\n\tstruct mutex reg_mutex;\n\tenum {\n\t\tSUBCHANNEL_TYPE_IO = 0,\n\t\tSUBCHANNEL_TYPE_CHSC = 1,\n\t\tSUBCHANNEL_TYPE_MSG = 2,\n\t\tSUBCHANNEL_TYPE_ADM = 3,\n\t} st;\n\t__u8 vpm;\n\t__u8 lpm;\n\t__u8 opm;\n\tlong: 0;\n\tstruct schib schib;\n\tint isc;\n\tstruct chsc_ssd_info ssd_info;\n\tstruct device dev;\n\tstruct css_driver *driver;\n\tenum sch_todo todo;\n\tstruct work_struct todo_work;\n\tstruct schib_config config;\n\tu64 dma_mask;\n\tconst char *driver_override;\n};\n\nstruct subflow_send_info {\n\tstruct sock *ssk;\n\tu64 linger_time;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct mtd_info;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tvoid *s_security;\n\tconst struct xattr_handler * const *s_xattr;\n\tconst struct fscrypt_operations *s_cop;\n\tstruct fscrypt_keyring *s_master_keys;\n\tconst struct fsverity_operations *s_vop;\n\tstruct unicode_map *s_encoding;\n\t__u16 s_encoding_flags;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t);\n\tssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t);\n\tstruct dquot ** (*get_dquots)(struct inode *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct super_type {\n\tchar *name;\n\tstruct module *owner;\n\tint (*load_super)(struct md_rdev *, struct md_rdev *, int);\n\tint (*validate_super)(struct mddev *, struct md_rdev *, struct md_rdev *);\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tlong long unsigned int (*rdev_size_change)(struct md_rdev *, sector_t);\n\tint (*allow_new_offset)(struct md_rdev *, long long unsigned int);\n};\n\nstruct superblock_security_struct {\n\tu32 sid;\n\tu32 def_sid;\n\tu32 mntpoint_sid;\n\tu32 creator_sid;\n\tshort unsigned int behavior;\n\tshort unsigned int flags;\n\tstruct mutex lock;\n\tstruct list_head isec_head;\n\tspinlock_t isec_lock;\n};\n\nstruct sw842_hlist_node2 {\n\tstruct hlist_node node;\n\tu16 data;\n\tu8 index;\n};\n\nstruct sw842_hlist_node4 {\n\tstruct hlist_node node;\n\tu32 data;\n\tu16 index;\n};\n\nstruct sw842_hlist_node8 {\n\tstruct hlist_node node;\n\tu64 data;\n\tu8 index;\n};\n\nstruct sw842_param {\n\tu8 *in;\n\tu8 *instart;\n\tu64 ilen;\n\tu8 *out;\n\tu64 olen;\n\tu8 bit;\n\tu64 data8[1];\n\tu32 data4[2];\n\tu16 data2[4];\n\tint index8[1];\n\tint index4[2];\n\tint index2[4];\n\tstruct hlist_head htable8[1024];\n\tstruct hlist_head htable4[2048];\n\tstruct hlist_head htable2[1024];\n\tstruct sw842_hlist_node8 node8[256];\n\tstruct sw842_hlist_node4 node4[512];\n\tstruct sw842_hlist_node2 node2[256];\n};\n\nstruct sw842_param___2 {\n\tu8 *in;\n\tu8 bit;\n\tu64 ilen;\n\tu8 *out;\n\tu8 *ostart;\n\tu64 olen;\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cgroup {\n\tatomic_t ids;\n};\n\nstruct swap_cgroup_ctrl {\n\tstruct swap_cgroup *map;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[9];\n\tstruct list_head frag_clusters[9];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_insn_args {\n\tstruct kprobe *p;\n\tunsigned int arm_kprobe: 1;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[9];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[256];\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n};\n\nstruct switchdev_mst_state {\n\tu16 msti;\n\tu8 state;\n};\n\nstruct switchdev_brport_flags {\n\tlong unsigned int val;\n\tlong unsigned int mask;\n};\n\nstruct switchdev_vlan_msti {\n\tu16 vid;\n\tu16 msti;\n};\n\nstruct switchdev_attr {\n\tstruct net_device *orig_dev;\n\tenum switchdev_attr_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n\tunion {\n\t\tu8 stp_state;\n\t\tstruct switchdev_mst_state mst_state;\n\t\tstruct switchdev_brport_flags brport_flags;\n\t\tbool mrouter;\n\t\tclock_t ageing_time;\n\t\tbool vlan_filtering;\n\t\tu16 vlan_protocol;\n\t\tbool mst;\n\t\tbool mc_disabled;\n\t\tu8 mrp_port_role;\n\t\tstruct switchdev_vlan_msti vlan_msti;\n\t} u;\n};\n\nstruct switchdev_brport {\n\tstruct net_device *dev;\n\tconst void *ctx;\n\tstruct notifier_block *atomic_nb;\n\tstruct notifier_block *blocking_nb;\n\tbool tx_fwd_offload;\n};\n\ntypedef void switchdev_deferred_func_t(struct net_device *, const void *);\n\nstruct switchdev_deferred_item {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tswitchdev_deferred_func_t *func;\n\tlong unsigned int data[0];\n};\n\nstruct switchdev_nested_priv {\n\tbool (*check_cb)(const struct net_device *);\n\tbool (*foreign_dev_check_cb)(const struct net_device *, const struct net_device *);\n\tconst struct net_device *dev;\n\tstruct net_device *lower_dev;\n};\n\nstruct switchdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n\tconst void *ctx;\n};\n\nstruct switchdev_notifier_brport_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_brport brport;\n};\n\nstruct switchdev_notifier_fdb_info {\n\tstruct switchdev_notifier_info info;\n\tconst unsigned char *addr;\n\tu16 vid;\n\tu8 added_by_user: 1;\n\tu8 is_local: 1;\n\tu8 locked: 1;\n\tu8 offloaded: 1;\n};\n\nstruct switchdev_notifier_port_attr_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_attr *attr;\n\tbool handled;\n};\n\nstruct switchdev_obj;\n\nstruct switchdev_notifier_port_obj_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_obj *obj;\n\tbool handled;\n};\n\nstruct switchdev_obj {\n\tstruct list_head list;\n\tstruct net_device *orig_dev;\n\tenum switchdev_obj_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n};\n\nstruct switchdev_obj_in_role_mrp {\n\tstruct switchdev_obj obj;\n\tstruct net_device *i_port;\n\tu32 ring_id;\n\tu16 in_id;\n\tu8 in_role;\n\tu8 sw_backup;\n};\n\nstruct switchdev_obj_in_state_mrp {\n\tstruct switchdev_obj obj;\n\tu32 in_id;\n\tu8 in_state;\n};\n\nstruct switchdev_obj_in_test_mrp {\n\tstruct switchdev_obj obj;\n\tu32 interval;\n\tu32 in_id;\n\tu32 period;\n\tu8 max_miss;\n};\n\nstruct switchdev_obj_mrp {\n\tstruct switchdev_obj obj;\n\tstruct net_device *p_port;\n\tstruct net_device *s_port;\n\tu32 ring_id;\n\tu16 prio;\n};\n\nstruct switchdev_obj_port_mdb {\n\tstruct switchdev_obj obj;\n\tunsigned char addr[6];\n\tu16 vid;\n};\n\nstruct switchdev_obj_port_vlan {\n\tstruct switchdev_obj obj;\n\tu16 flags;\n\tu16 vid;\n\tbool changed;\n};\n\nstruct switchdev_obj_ring_role_mrp {\n\tstruct switchdev_obj obj;\n\tu8 ring_role;\n\tu32 ring_id;\n\tu8 sw_backup;\n};\n\nstruct switchdev_obj_ring_state_mrp {\n\tstruct switchdev_obj obj;\n\tu8 ring_state;\n\tu32 ring_id;\n};\n\nstruct switchdev_obj_ring_test_mrp {\n\tstruct switchdev_obj obj;\n\tu32 interval;\n\tu8 max_miss;\n\tu32 ring_id;\n\tu32 period;\n\tbool monitor;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct sym_count_ctx {\n\tunsigned int count;\n\tconst char *name;\n};\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct sync_fence_info {\n\tchar obj_name[32];\n\tchar driver_name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u64 timestamp_ns;\n};\n\nstruct sync_file {\n\tstruct file *file;\n\tchar user_name[32];\n\tstruct list_head sync_file_list;\n\twait_queue_head_t wq;\n\tlong unsigned int flags;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct sync_file_info {\n\tchar name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u32 num_fences;\n\t__u32 pad;\n\t__u64 sync_fence_info;\n};\n\nstruct sync_io {\n\tlong unsigned int error_bits;\n\tstruct completion wait;\n};\n\nstruct sync_merge_data {\n\tchar name[32];\n\t__s32 fd2;\n\t__s32 fence;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct sync_set_deadline {\n\t__u64 deadline_ns;\n\t__u64 pad;\n};\n\nstruct trace_event_fields;\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tconst char *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tunion {\n\t\tvoid *module;\n\t\tatomic_t refcnt;\n\t};\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct synth_field;\n\nstruct synth_event {\n\tstruct dyn_event devent;\n\tint ref;\n\tchar *name;\n\tstruct synth_field **fields;\n\tunsigned int n_fields;\n\tstruct synth_field **dynamic_fields;\n\tunsigned int n_dynamic_fields;\n\tunsigned int n_u64;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct tracepoint *tp;\n\tstruct module *mod;\n};\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tunsigned int trace_ctx;\n\tstruct pt_regs *regs;\n};\n\nstruct synth_trace_event;\n\nstruct synth_event_trace_state {\n\tstruct trace_event_buffer fbuffer;\n\tstruct synth_trace_event *entry;\n\tstruct trace_buffer *buffer;\n\tstruct synth_event *event;\n\tunsigned int cur_field;\n\tunsigned int n_u64;\n\tbool disabled;\n\tbool add_next;\n\tbool add_name;\n};\n\nstruct synth_field {\n\tchar *type;\n\tchar *name;\n\tsize_t size;\n\tunsigned int offset;\n\tunsigned int field_pos;\n\tbool is_signed;\n\tbool is_string;\n\tbool is_dynamic;\n\tbool is_stack;\n};\n\nstruct synth_field_desc {\n\tconst char *type;\n\tconst char *name;\n};\n\nstruct trace_dynamic_info {\n\tu16 len;\n\tu16 offset;\n};\n\nunion trace_synth_field {\n\tu8 as_u8;\n\tu16 as_u16;\n\tu32 as_u32;\n\tu64 as_u64;\n\tstruct trace_dynamic_info as_dynamic;\n};\n\nstruct synth_trace_event {\n\tstruct trace_entry ent;\n\tunion trace_synth_field fields[0];\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct syscall_args {\n\tchar *ptr_array[3];\n\tint read[3];\n\tint uargs;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_metadata {\n\tconst char *name;\n\tint syscall_nr;\n\tu8 nb_args: 7;\n\tu8 user_arg_is_str: 1;\n\ts8 user_arg_size;\n\tshort int user_mask;\n\tconst char **types;\n\tconst char **args;\n\tstruct list_head enter_fields;\n\tstruct trace_event_call *enter_event;\n\tstruct trace_event_call *exit_event;\n};\n\nstruct syscall_tp_t {\n\tstruct trace_entry ent;\n\tint syscall_nr;\n\tlong unsigned int ret;\n};\n\nstruct syscall_tp_t___2 {\n\tstruct trace_entry ent;\n\tint syscall_nr;\n\tlong unsigned int args[6];\n};\n\nstruct syscall_trace_enter {\n\tstruct trace_entry ent;\n\tint nr;\n\tlong unsigned int args[0];\n};\n\nstruct syscall_trace_exit {\n\tstruct trace_entry ent;\n\tint nr;\n\tlong int ret;\n};\n\nstruct trace_user_buf;\n\nstruct trace_user_buf_info {\n\tstruct trace_user_buf *tbuf;\n\tsize_t size;\n\tint ref;\n};\n\nstruct syscall_user_buffer {\n\tstruct trace_user_buf_info buf;\n\tstruct callback_head rcu;\n};\n\nstruct syscall_user_dispatch {\n\tchar *selector;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tbool on_dispatch;\n};\n\nstruct syscore_ops;\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysfs_wi_group {\n\tstruct kobject wi_kobj;\n\tstruct mutex kobj_lock;\n\tstruct iw_node_attr *nattrs[0];\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[0];\n};\n\nstruct topology_core {\n\tunsigned char nl;\n\tunsigned char reserved0[3];\n\tchar: 5;\n\tunsigned char d: 1;\n\tunsigned char pp: 2;\n\tunsigned char reserved1;\n\tshort unsigned int origin;\n\tlong unsigned int mask;\n};\n\nstruct topology_container {\n\tunsigned char nl;\n\tunsigned char reserved[6];\n\tunsigned char id;\n};\n\nunion topology_entry {\n\tunsigned char nl;\n\tstruct topology_core cpu;\n\tstruct topology_container container;\n};\n\nstruct sysinfo_15_1_x {\n\tunsigned char reserved0[2];\n\tshort unsigned int length;\n\tunsigned char mag[6];\n\tunsigned char reserved1;\n\tunsigned char mnest;\n\tunsigned char reserved2[4];\n\tunion topology_entry tle[0];\n};\n\nstruct sysinfo_1_1_1 {\n\tunsigned char p: 1;\n\tchar: 6;\n\tunsigned char t: 1;\n\tshort: 0;\n\tunsigned char ccr;\n\tunsigned char cai;\n\tchar reserved_0[20];\n\tlong unsigned int lic;\n\tchar manufacturer[16];\n\tchar type[4];\n\tchar reserved_1[12];\n\tchar model_capacity[16];\n\tchar sequence[16];\n\tchar plant[4];\n\tchar model[16];\n\tchar model_perm_cap[16];\n\tchar model_temp_cap[16];\n\tunsigned int model_cap_rating;\n\tunsigned int model_perm_cap_rating;\n\tunsigned int model_temp_cap_rating;\n\tunsigned char typepct[5];\n\tunsigned char reserved_2[3];\n\tunsigned int ncr;\n\tunsigned int npr;\n\tunsigned int ntr;\n\tchar reserved_3[4];\n\tchar model_var_cap[16];\n\tunsigned int model_var_cap_rating;\n\tunsigned int nvr;\n};\n\nstruct sysinfo_1_2_2 {\n\tchar format;\n\tchar reserved_0[1];\n\tshort unsigned int acc_offset;\n\tunsigned char mt_installed: 1;\n\tchar: 2;\n\tunsigned char mt_stid: 5;\n\tchar: 3;\n\tunsigned char mt_gtid: 5;\n\tchar reserved_1[18];\n\tunsigned int nominal_cap;\n\tunsigned int secondary_cap;\n\tunsigned int capability;\n\tshort unsigned int cpus_total;\n\tshort unsigned int cpus_configured;\n\tshort unsigned int cpus_standby;\n\tshort unsigned int cpus_reserved;\n\tshort unsigned int adjustment[0];\n};\n\nstruct sysinfo_1_2_2_extension {\n\tunsigned int alt_capability;\n\tshort unsigned int alt_adjustment[0];\n};\n\nstruct sysinfo_2_2_2 {\n\tchar reserved_0[32];\n\tshort unsigned int lpar_number;\n\tchar reserved_1;\n\tunsigned char characteristics;\n\tshort unsigned int cpus_total;\n\tshort unsigned int cpus_configured;\n\tshort unsigned int cpus_standby;\n\tshort unsigned int cpus_reserved;\n\tchar name[8];\n\tunsigned int caf;\n\tchar reserved_2[8];\n\tunsigned char mt_installed: 1;\n\tchar: 2;\n\tunsigned char mt_stid: 5;\n\tchar: 3;\n\tunsigned char mt_gtid: 5;\n\tchar: 3;\n\tunsigned char mt_psmtid: 5;\n\tchar reserved_3[5];\n\tshort unsigned int cpus_dedicated;\n\tshort unsigned int cpus_shared;\n\tchar reserved_4[3];\n\tunsigned char vsne;\n\tuuid_t uuid;\n\tchar reserved_5[160];\n\tchar ext_name[256];\n};\n\nstruct sysinfo_3_2_2 {\n\tchar reserved_0[31];\n\tchar: 4;\n\tunsigned char count: 4;\n\tstruct {\n\t\tchar reserved_0[4];\n\t\tshort unsigned int cpus_total;\n\t\tshort unsigned int cpus_configured;\n\t\tshort unsigned int cpus_standby;\n\t\tshort unsigned int cpus_reserved;\n\t\tchar name[8];\n\t\tunsigned int caf;\n\t\tchar cpi[16];\n\t\tchar reserved_1[3];\n\t\tunsigned char evmne;\n\t\tunsigned int reserved_2;\n\t\tuuid_t uuid;\n\t} vm[8];\n\tchar reserved_3[1504];\n\tchar ext_names[2048];\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[12];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tunsigned int shift;\n\tunsigned int shift_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[12];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct sysrq_work {\n\tint key;\n\tstruct work_struct work;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct t10_pi_tuple {\n\t__be16 guard_tag;\n\t__be16 app_tag;\n\t__be32 ref_tag;\n};\n\nstruct table_device {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev dm_dev;\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\ntypedef int (*dm_ctr_fn)(struct dm_target *, unsigned int, char **);\n\ntypedef void (*dm_dtr_fn)(struct dm_target *);\n\ntypedef int (*dm_map_fn)(struct dm_target *, struct bio *);\n\ntypedef int (*dm_clone_and_map_request_fn)(struct dm_target *, struct request *, union map_info *, struct request **);\n\ntypedef void (*dm_release_clone_request_fn)(struct request *, union map_info *);\n\ntypedef int (*dm_endio_fn)(struct dm_target *, struct bio *, blk_status_t *);\n\ntypedef int (*dm_request_endio_fn)(struct dm_target *, struct request *, blk_status_t, union map_info *);\n\ntypedef void (*dm_presuspend_fn)(struct dm_target *);\n\ntypedef void (*dm_presuspend_undo_fn)(struct dm_target *);\n\ntypedef void (*dm_postsuspend_fn)(struct dm_target *);\n\ntypedef int (*dm_preresume_fn)(struct dm_target *);\n\ntypedef void (*dm_resume_fn)(struct dm_target *);\n\ntypedef void (*dm_status_fn)(struct dm_target *, status_type_t, unsigned int, char *, unsigned int);\n\ntypedef int (*dm_message_fn)(struct dm_target *, unsigned int, char **, char *, unsigned int);\n\ntypedef int (*dm_prepare_ioctl_fn)(struct dm_target *, struct block_device **, unsigned int, long unsigned int, bool *);\n\ntypedef int (*dm_report_zones_fn)(struct dm_target *);\n\ntypedef int (*dm_busy_fn)(struct dm_target *);\n\ntypedef int (*iterate_devices_callout_fn)(struct dm_target *, struct dm_dev *, sector_t, sector_t, void *);\n\ntypedef int (*dm_iterate_devices_fn)(struct dm_target *, iterate_devices_callout_fn, void *);\n\ntypedef void (*dm_io_hints_fn)(struct dm_target *, struct queue_limits *);\n\ntypedef long int (*dm_dax_direct_access_fn)(struct dm_target *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\ntypedef int (*dm_dax_zero_page_range_fn)(struct dm_target *, long unsigned int, size_t);\n\ntypedef size_t (*dm_dax_recovery_write_fn)(struct dm_target *, long unsigned int, void *, size_t, struct iov_iter *);\n\nstruct target_type {\n\tuint64_t features;\n\tconst char *name;\n\tstruct module *module;\n\tunsigned int version[3];\n\tdm_ctr_fn ctr;\n\tdm_dtr_fn dtr;\n\tdm_map_fn map;\n\tdm_clone_and_map_request_fn clone_and_map_rq;\n\tdm_release_clone_request_fn release_clone_rq;\n\tdm_endio_fn end_io;\n\tdm_request_endio_fn rq_end_io;\n\tdm_presuspend_fn presuspend;\n\tdm_presuspend_undo_fn presuspend_undo;\n\tdm_postsuspend_fn postsuspend;\n\tdm_preresume_fn preresume;\n\tdm_resume_fn resume;\n\tdm_status_fn status;\n\tdm_message_fn message;\n\tdm_prepare_ioctl_fn prepare_ioctl;\n\tdm_report_zones_fn report_zones;\n\tdm_busy_fn busy;\n\tdm_iterate_devices_fn iterate_devices;\n\tdm_io_hints_fn io_hints;\n\tdm_dax_direct_access_fn direct_access;\n\tdm_dax_zero_page_range_fn dax_zero_page_range;\n\tdm_dax_recovery_write_fn dax_recovery_write;\n\tstruct list_head list;\n};\n\nstruct task_delay_info {\n\traw_spinlock_t lock;\n\tu64 blkio_start;\n\tu64 blkio_delay_max;\n\tu64 blkio_delay_min;\n\tu64 blkio_delay;\n\tu64 swapin_start;\n\tu64 swapin_delay_max;\n\tu64 swapin_delay_min;\n\tu64 swapin_delay;\n\tu32 blkio_count;\n\tu32 swapin_count;\n\tu64 freepages_start;\n\tu64 freepages_delay_max;\n\tu64 freepages_delay_min;\n\tu64 freepages_delay;\n\tu64 thrashing_start;\n\tu64 thrashing_delay_max;\n\tu64 thrashing_delay_min;\n\tu64 thrashing_delay;\n\tu64 compact_start;\n\tu64 compact_delay_max;\n\tu64 compact_delay_min;\n\tu64 compact_delay;\n\tu64 wpcopy_start;\n\tu64 wpcopy_delay_max;\n\tu64 wpcopy_delay_min;\n\tu64 wpcopy_delay;\n\tu64 irq_delay_max;\n\tu64 irq_delay_min;\n\tu64 irq_delay;\n\tu32 freepages_count;\n\tu32 thrashing_count;\n\tu32 compact_count;\n\tu32 wpcopy_count;\n\tu32 irq_count;\n\tstruct timespec64 blkio_delay_max_ts;\n\tstruct timespec64 swapin_delay_max_ts;\n\tstruct timespec64 freepages_delay_max_ts;\n\tstruct timespec64 thrashing_delay_max_ts;\n\tstruct timespec64 compact_delay_max_ts;\n\tstruct timespec64 wpcopy_delay_max_ts;\n\tstruct timespec64 irq_delay_max_ts;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t load_avg;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct autogroup *autogroup;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_numa_env {\n\tstruct task_struct *p;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tint imb_numa_nr;\n\tstruct numa_stats src_stats;\n\tstruct numa_stats dst_stats;\n\tint imbalance_pct;\n\tint dist;\n\tstruct task_struct *best_task;\n\tlong int best_imp;\n\tint best_cpu;\n};\n\nstruct task_security_struct {\n\tstruct {\n\t\tu32 sid;\n\t\tu32 seqno;\n\t\tunsigned int dir_spot;\n\t\tstruct avdc_entry dir[4];\n\t\tbool permissive_neveraudit;\n\t} avdcache;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct thread_info {\n\tlong unsigned int flags;\n\tlong unsigned int syscall_work;\n\tunsigned int cpu;\n\tunsigned char sie;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {};\n\nunion teid {\n\tlong unsigned int val;\n\tstruct {\n\t\tlong unsigned int addr: 52;\n\t\tlong unsigned int fsi: 2;\n\t\tchar: 2;\n\t\tlong unsigned int b56: 1;\n\t\tchar: 3;\n\t\tlong unsigned int b60: 1;\n\t\tlong unsigned int b61: 1;\n\t\tlong unsigned int as: 2;\n\t};\n};\n\nstruct thread_struct {\n\tunsigned int acrs[16];\n\tlong unsigned int ksp;\n\tlong unsigned int user_timer;\n\tlong unsigned int guest_timer;\n\tlong unsigned int system_timer;\n\tlong unsigned int hardirq_timer;\n\tlong unsigned int softirq_timer;\n\tunion teid gmap_teid;\n\tunsigned int gmap_int_code;\n\tint ufpu_flags;\n\tint kfpu_flags;\n\tstruct per_regs per_user;\n\tstruct per_event per_event;\n\tlong unsigned int per_flags;\n\tunsigned int system_call;\n\tlong unsigned int last_break;\n\tlong unsigned int pfault_wait;\n\tstruct list_head list;\n\tstruct runtime_instr_cb *ri_cb;\n\tstruct gs_cb *gs_cb;\n\tstruct gs_cb *gs_bc_cb;\n\tstruct pgm_tdb trap_tdb;\n\tstruct fpu ufpu;\n\tstruct fpu kfpu;\n};\n\nstruct uprobe_task;\n\nstruct user_event_mm;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct rb_node core_node;\n\tlong unsigned int core_cookie;\n\tunsigned int core_occupation;\n\tstruct task_group *sched_task_group;\n\tstruct callback_head sched_throttle_work;\n\tstruct list_head throttle_node;\n\tbool throttled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_statistics stats;\n\tstruct hlist_head preempt_notifiers;\n\tunsigned int btrace_seq;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tlong unsigned int rcu_tasks_nvcsw;\n\tu8 rcu_tasks_holdout;\n\tu8 rcu_tasks_idx;\n\tint rcu_tasks_idle_cpu;\n\tstruct list_head rcu_tasks_holdout_list;\n\tint rcu_tasks_exit_cpu;\n\tstruct list_head rcu_tasks_exit_list;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int use_memdelay: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int in_thrashing: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tu64 utime;\n\tu64 stime;\n\tu64 utimescaled;\n\tu64 stimescaled;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct posix_cputimers_work posix_cputimers_work;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct audit_context *audit_context;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tu64 acct_rss_mem1;\n\tu64 acct_vm_mem1;\n\tu64 acct_timexpd;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tu8 perf_recursion[4];\n\tstruct perf_event_context *perf_event_ctxp;\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct perf_ctx_data *perf_ctx_data;\n\tstruct mempolicy *mempolicy;\n\tshort int il_prev;\n\tu8 il_weight;\n\tshort int pref_node_fork;\n\tint numa_scan_seq;\n\tunsigned int numa_scan_period;\n\tunsigned int numa_scan_period_max;\n\tint numa_preferred_nid;\n\tlong unsigned int numa_migrate_retry;\n\tu64 node_stamp;\n\tu64 last_task_numa_placement;\n\tu64 last_sum_exec_runtime;\n\tstruct callback_head numa_work;\n\tstruct numa_group *numa_group;\n\tlong unsigned int *numa_faults;\n\tlong unsigned int total_numa_faults;\n\tlong unsigned int numa_faults_locality[3];\n\tlong unsigned int numa_pages_migrated;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tstruct task_delay_info *delays;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tint latency_record_count;\n\tstruct latency_record latency_record[32];\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tstruct kunit *kunit_test;\n\tint curr_ret_stack;\n\tint curr_ret_depth;\n\tlong unsigned int *ret_stack;\n\tlong long unsigned int ftrace_timestamp;\n\tlong long unsigned int ftrace_sleeptime;\n\tatomic_t trace_overrun;\n\tatomic_t tracing_graph_pause;\n\tlong unsigned int trace_recursion;\n\tunsigned int memcg_nr_pages_over_high;\n\tstruct mem_cgroup *active_memcg;\n\tstruct obj_cgroup *objcg;\n\tstruct gendisk *throttle_disk;\n\tstruct uprobe_task *utask;\n\tunsigned int sequential_io;\n\tunsigned int sequential_io_avg;\n\tstruct kmap_ctrl kmap_ctrl;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\tstruct vm_struct *stack_vm_area;\n\trefcount_t stack_refcount;\n\tint patch_state;\n\tvoid *security;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tstruct llist_head kretprobe_instances;\n\tstruct llist_head rethooks;\n\tstruct user_event_mm *user_event_mm;\n\tstruct thread_struct thread;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct taskstats {\n\t__u16 version;\n\t__u32 ac_exitcode;\n\t__u8 ac_flag;\n\t__u8 ac_nice;\n\t__u64 cpu_count;\n\t__u64 cpu_delay_total;\n\t__u64 blkio_count;\n\t__u64 blkio_delay_total;\n\t__u64 swapin_count;\n\t__u64 swapin_delay_total;\n\t__u64 cpu_run_real_total;\n\t__u64 cpu_run_virtual_total;\n\tchar ac_comm[32];\n\t__u8 ac_sched;\n\t__u8 ac_pad[3];\n\tlong: 0;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u64 ac_etime;\n\t__u64 ac_utime;\n\t__u64 ac_stime;\n\t__u64 ac_minflt;\n\t__u64 ac_majflt;\n\t__u64 coremem;\n\t__u64 virtmem;\n\t__u64 hiwater_rss;\n\t__u64 hiwater_vm;\n\t__u64 read_char;\n\t__u64 write_char;\n\t__u64 read_syscalls;\n\t__u64 write_syscalls;\n\t__u64 read_bytes;\n\t__u64 write_bytes;\n\t__u64 cancelled_write_bytes;\n\t__u64 nvcsw;\n\t__u64 nivcsw;\n\t__u64 ac_utimescaled;\n\t__u64 ac_stimescaled;\n\t__u64 cpu_scaled_run_real_total;\n\t__u64 freepages_count;\n\t__u64 freepages_delay_total;\n\t__u64 thrashing_count;\n\t__u64 thrashing_delay_total;\n\t__u64 ac_btime64;\n\t__u64 compact_count;\n\t__u64 compact_delay_total;\n\t__u32 ac_tgid;\n\t__u64 ac_tgetime;\n\t__u64 ac_exe_dev;\n\t__u64 ac_exe_inode;\n\t__u64 wpcopy_count;\n\t__u64 wpcopy_delay_total;\n\t__u64 irq_count;\n\t__u64 irq_delay_total;\n\t__u64 cpu_delay_max;\n\t__u64 cpu_delay_min;\n\t__u64 blkio_delay_max;\n\t__u64 blkio_delay_min;\n\t__u64 swapin_delay_max;\n\t__u64 swapin_delay_min;\n\t__u64 freepages_delay_max;\n\t__u64 freepages_delay_min;\n\t__u64 thrashing_delay_max;\n\t__u64 thrashing_delay_min;\n\t__u64 compact_delay_max;\n\t__u64 compact_delay_min;\n\t__u64 wpcopy_delay_max;\n\t__u64 wpcopy_delay_min;\n\t__u64 irq_delay_max;\n\t__u64 irq_delay_min;\n\tstruct __kernel_timespec cpu_delay_max_ts;\n\tstruct __kernel_timespec blkio_delay_max_ts;\n\tstruct __kernel_timespec swapin_delay_max_ts;\n\tstruct __kernel_timespec freepages_delay_max_ts;\n\tstruct __kernel_timespec thrashing_delay_max_ts;\n\tstruct __kernel_timespec compact_delay_max_ts;\n\tstruct __kernel_timespec wpcopy_delay_max_ts;\n\tstruct __kernel_timespec irq_delay_max_ts;\n};\n\nstruct tc_act_pernet_id {\n\tstruct list_head list;\n\tunsigned int id;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tstruct tcf_t tcfa_tm;\n\tlong: 64;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n};\n\nstruct tc_action_net {\n\tstruct tcf_idrinfo *idrinfo;\n\tconst struct tc_action_ops *ops;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_bind_class_args {\n\tstruct qdisc_walker w;\n\tlong unsigned int new_cl;\n\tu32 portid;\n\tu32 clid;\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_fifo_qopt {\n\t__u32 limit;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_fifo_qopt_offload {\n\tenum tc_fifo_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t};\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_pedit_key {\n\t__u32 mask;\n\t__u32 val;\n\t__u32 off;\n\t__u32 at;\n\t__u32 offmask;\n\t__u32 shift;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_root_qopt_offload {\n\tenum tc_root_command command;\n\tu32 handle;\n\tbool ingress;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tc_skb_ext {\n\tunion {\n\t\tu64 act_miss_cookie;\n\t\t__u32 chain;\n\t};\n\t__u16 mru;\n\t__u16 zone;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n\tu8 act_miss: 1;\n\tu8 l2_miss: 1;\n};\n\nstruct tcamsg {\n\tunsigned char tca_family;\n\tunsigned char tca__pad1;\n\tshort unsigned int tca__pad2;\n};\n\nstruct tccb_tcah {\n\tu32 format: 8;\n\tint: 24;\n\tint: 24;\n\tu32 tcal: 8;\n\tu32 sac: 16;\n\tchar: 8;\n\tu32 prio: 8;\n\tlong: 0;\n};\n\nstruct tccb {\n\tstruct tccb_tcah tcah;\n\tu8 tca[0];\n};\n\nstruct tccb_tcat {\n\tint: 32;\n\tu32 count;\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcf_bind_args {\n\tstruct tcf_walker w;\n\tlong unsigned int base;\n\tlong unsigned int cl;\n\tu32 classid;\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\ntypedef void tcf_chain_head_change_t(struct tcf_proto *, void *);\n\nstruct tcf_block_ext_info {\n\tenum flow_block_binder_type binder_type;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n\tu32 block_index;\n};\n\nstruct tcf_block_owner_item {\n\tstruct list_head list;\n\tstruct Qdisc *q;\n\tenum flow_block_binder_type binder_type;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_chain_info {\n\tstruct tcf_proto **pprev;\n\tstruct tcf_proto *next;\n};\n\nstruct tcf_dump_args {\n\tstruct tcf_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct tcf_block *block;\n\tstruct Qdisc *q;\n\tu32 parent;\n\tbool terse_dump;\n};\n\nstruct tcf_ematch_ops;\n\nstruct tcf_ematch {\n\tstruct tcf_ematch_ops *ops;\n\tlong unsigned int data;\n\tunsigned int datalen;\n\tu16 matchid;\n\tu16 flags;\n\tstruct net *net;\n};\n\nstruct tcf_ematch_hdr {\n\t__u16 matchid;\n\t__u16 kind;\n\t__u16 flags;\n\t__u16 pad;\n};\n\nstruct tcf_pkt_info;\n\nstruct tcf_ematch_ops {\n\tint kind;\n\tint datalen;\n\tint (*change)(struct net *, void *, int, struct tcf_ematch *);\n\tint (*match)(struct sk_buff *, struct tcf_ematch *, struct tcf_pkt_info *);\n\tvoid (*destroy)(struct tcf_ematch *);\n\tint (*dump)(struct sk_buff *, struct tcf_ematch *);\n\tstruct module *owner;\n\tstruct list_head link;\n};\n\nunion tcf_exts_miss_cookie {\n\tstruct {\n\t\tu32 miss_cookie_base;\n\t\tu32 act_index;\n\t};\n\tu64 miss_cookie;\n};\n\nstruct tcf_exts_miss_cookie_node {\n\tconst struct tcf_chain *chain;\n\tconst struct tcf_proto *tp;\n\tconst struct tcf_exts *exts;\n\tu32 chain_index;\n\tu32 tp_prio;\n\tu32 handle;\n\tu32 miss_cookie_base;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_filter_chain_list_item {\n\tstruct list_head list;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_net {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n};\n\nstruct tcf_pedit_parms;\n\nstruct tcf_pedit {\n\tstruct tc_action common;\n\tstruct tcf_pedit_parms *parms;\n\tlong: 64;\n};\n\nstruct tcf_pedit_key_ex {\n\tenum pedit_header_type htype;\n\tenum pedit_cmd cmd;\n};\n\nstruct tcf_pedit_parms {\n\tstruct tc_pedit_key *tcfp_keys;\n\tstruct tcf_pedit_key_ex *tcfp_keys_ex;\n\tint action;\n\tu32 tcfp_off_max_hint;\n\tunsigned char tcfp_nkeys;\n\tunsigned char tcfp_flags;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_pkt_info {\n\tunsigned char *ptr;\n\tint nexthdr;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_qevent {\n\tstruct tcf_block *block;\n\tstruct tcf_block_ext_info info;\n\tstruct tcf_proto *filter_chain;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\tvoid (*tcp_clean_acked)(struct sock *, u32);\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tbool is_mptcp;\n\tbool syn_smc;\n\tbool (*smc_hs_congested)(const struct sock *);\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\t__u32 (*cookie_init_seq)(const struct sk_buff *, __u16 *);\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t};\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 doff: 4;\n\t__u16 res1: 3;\n\t__u16 ae: 1;\n\t__u16 cwr: 1;\n\t__u16 ece: 1;\n\t__u16 urg: 1;\n\t__u16 ack: 1;\n\t__u16 psh: 1;\n\t__u16 rst: 1;\n\t__u16 syn: 1;\n\t__u16 fin: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpa_event {\n\tu32 pcr_index;\n\tu32 event_type;\n\tu8 pcr_value[20];\n\tu32 event_size;\n\tu8 event_data[0];\n};\n\nstruct tcpa_pc_event {\n\tu32 event_id;\n\tu32 event_size;\n\tu8 event_data[0];\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcw {\n\tu32 format: 2;\n\tchar: 6;\n\tu32 flags: 24;\n\tchar: 8;\n\tu32 tccbl: 6;\n\tu32 r: 1;\n\tu32 w: 1;\n\tdma64_t output;\n\tdma64_t input;\n\tdma64_t tsb;\n\tdma64_t tccb;\n\tu32 output_count;\n\tu32 input_count;\n\tlong: 64;\n\tint: 32;\n\tdma32_t intrg;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[8];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct thpsize {\n\tstruct kobject kobj;\n\tstruct list_head node;\n\tint order;\n};\n\nstruct throtl_service_queue {\n\tstruct throtl_service_queue *parent_sq;\n\tstruct list_head queued[2];\n\tunsigned int nr_queued_bps[2];\n\tunsigned int nr_queued_iops[2];\n\tstruct rb_root_cached pending_tree;\n\tunsigned int nr_pending;\n\tlong unsigned int first_pending_disptime;\n\tstruct timer_list pending_timer;\n};\n\nstruct throtl_data {\n\tstruct throtl_service_queue service_queue;\n\tstruct request_queue *queue;\n\tunsigned int nr_queued[2];\n\tstruct work_struct dispatch_work;\n};\n\nstruct throtl_grp;\n\nstruct throtl_qnode {\n\tstruct list_head node;\n\tstruct bio_list bios_bps;\n\tstruct bio_list bios_iops;\n\tstruct throtl_grp *tg;\n};\n\nstruct throtl_grp {\n\tstruct blkg_policy_data pd;\n\tstruct rb_node rb_node;\n\tstruct throtl_data *td;\n\tstruct throtl_service_queue service_queue;\n\tstruct throtl_qnode qnode_on_self[2];\n\tstruct throtl_qnode qnode_on_parent[2];\n\tlong unsigned int disptime;\n\tunsigned int flags;\n\tbool has_rules_bps[2];\n\tbool has_rules_iops[2];\n\tuint64_t bps[2];\n\tunsigned int iops[2];\n\tint64_t bytes_disp[2];\n\tint io_disp[2];\n\tlong unsigned int last_check_time;\n\tlong unsigned int slice_start[2];\n\tlong unsigned int slice_end[2];\n\tstruct blkg_rwstat stat_bytes;\n\tstruct blkg_rwstat stat_ios;\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct tidaw {\n\tu32 flags: 8;\n\tu32 count;\n\tdma64_t addr;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[9];\n\tstruct hlist_head vectors[576];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timerlat_entry {\n\tstruct trace_entry ent;\n\tunsigned int seqnum;\n\tint context;\n\tu64 timer_latency;\n};\n\nstruct timers_private {\n\tstruct pid *pid;\n\tstruct task_struct *task;\n\tstruct pid_namespace *ns;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tstruct tk_read_base base[2];\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\ntypedef void (*tls_done_func_t)(void *, int, key_serial_t);\n\nstruct tls_handshake_args {\n\tstruct socket *ta_sock;\n\ttls_done_func_t ta_done;\n\tvoid *ta_data;\n\tconst char *ta_peername;\n\tunsigned int ta_timeout_ms;\n\tkey_serial_t ta_keyring;\n\tkey_serial_t ta_my_cert;\n\tkey_serial_t ta_my_privkey;\n\tunsigned int ta_num_peerids;\n\tkey_serial_t ta_my_peerids[5];\n};\n\nstruct tls_handshake_req {\n\tvoid (*th_consumer_done)(void *, int, key_serial_t);\n\tvoid *th_consumer_data;\n\tint th_type;\n\tunsigned int th_timeout_ms;\n\tint th_auth_mode;\n\tconst char *th_peername;\n\tkey_serial_t th_keyring;\n\tkey_serial_t th_certificate;\n\tkey_serial_t th_privkey;\n\tunsigned int th_num_peerids;\n\tkey_serial_t th_peerid[5];\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tlsdev_ops {\n\tint (*tls_dev_add)(struct net_device *, struct sock *, enum tls_offload_ctx_dir, struct tls_crypto_info *, u32);\n\tvoid (*tls_dev_del)(struct net_device *, struct tls_context *, enum tls_offload_ctx_dir);\n\tint (*tls_dev_resync)(struct net_device *, struct sock *, u32, u8 *, enum tls_offload_ctx_dir);\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tu64 now;\n\tbool check;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct token_bucket {\n\tspinlock_t lock;\n\tint chain_len;\n\tstruct hlist_nulls_head req_chain;\n\tstruct hlist_nulls_head msk_chain;\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nstruct tp_transition_snapshot {\n\tlong unsigned int rcu;\n\tlong unsigned int srcu_gp;\n\tbool ongoing;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct tpm1_get_random_out {\n\t__be32 rng_data_len;\n\tu8 rng_data[128];\n};\n\nstruct tpm2_auth {\n\tu32 handle;\n\tu32 session;\n\tu8 our_nonce[32];\n\tu8 tpm_nonce[32];\n\tunion {\n\t\tu8 salt[32];\n\t\tu8 scratch[32];\n\t};\n\tu8 session_key[32];\n\tu8 passphrase[32];\n\tint passphrase_len;\n\tstruct aes_enckey aes_key;\n\tu8 attrs;\n\t__be32 ordinal;\n\tu32 name_h[3];\n\tu8 name[198];\n};\n\nstruct tpm2_cap_handles {\n\tu8 more_data;\n\t__be32 capability;\n\t__be32 count;\n\t__be32 handles[0];\n} __attribute__((packed));\n\nstruct tpm2_context {\n\t__be64 sequence;\n\t__be32 saved_handle;\n\t__be32 hierarchy;\n\t__be16 blob_size;\n} __attribute__((packed));\n\nstruct tpm2_get_cap_out {\n\tu8 more_data;\n\t__be32 subcap_id;\n\t__be32 property_cnt;\n\t__be32 property_id;\n\t__be32 value;\n} __attribute__((packed));\n\nstruct tpm2_get_random_out {\n\t__be16 size;\n\tu8 buffer[128];\n};\n\nstruct tpm2_hash {\n\tunsigned int crypto_id;\n\tunsigned int tpm_id;\n};\n\nstruct tpm2_pcr_read_out {\n\t__be32 update_cnt;\n\t__be32 pcr_selects_cnt;\n\t__be16 hash_alg;\n\tu8 pcr_select_size;\n\tu8 pcr_select[3];\n\t__be32 digests_cnt;\n\t__be16 digest_size;\n\tu8 digest[0];\n} __attribute__((packed));\n\nstruct tpm2_pcr_selection {\n\t__be16 hash_alg;\n\tu8 size_of_select;\n\tu8 pcr_select[3];\n};\n\nstruct tpm_bank_info {\n\tu16 alg_id;\n\tu16 digest_size;\n\tu16 crypto_id;\n};\n\nstruct tpm_bios_log {\n\tvoid *bios_event_log;\n\tvoid *bios_event_log_end;\n};\n\nstruct tpm_buf {\n\tu32 flags;\n\tu32 length;\n\tu8 *data;\n\tu8 handles;\n};\n\nstruct tpm_chip_seqops {\n\tstruct tpm_chip *chip;\n\tconst struct seq_operations *seqops;\n};\n\nstruct tpm_space {\n\tu32 context_tbl[3];\n\tu8 *context_buf;\n\tu32 session_tbl[3];\n\tu8 *session_buf;\n\tu32 buf_size;\n};\n\nstruct tpm_class_ops;\n\nstruct tpm_chip {\n\tstruct device dev;\n\tstruct device devs;\n\tstruct cdev cdev;\n\tstruct cdev cdevs;\n\tstruct rw_semaphore ops_sem;\n\tconst struct tpm_class_ops *ops;\n\tstruct tpm_bios_log log;\n\tstruct tpm_chip_seqops bin_log_seqops;\n\tstruct tpm_chip_seqops ascii_log_seqops;\n\tunsigned int flags;\n\tint dev_num;\n\tlong unsigned int is_open;\n\tchar hwrng_name[64];\n\tstruct hwrng hwrng;\n\tstruct mutex tpm_mutex;\n\tlong unsigned int timeout_a;\n\tlong unsigned int timeout_b;\n\tlong unsigned int timeout_c;\n\tlong unsigned int timeout_d;\n\tbool timeout_adjusted;\n\tlong unsigned int duration[4];\n\tbool duration_adjusted;\n\tstruct dentry *bios_dir;\n\tconst struct attribute_group *groups[8];\n\tunsigned int groups_cnt;\n\tu32 nr_allocated_banks;\n\tstruct tpm_bank_info allocated_banks[8];\n\tstruct tpm_space work_space;\n\tu32 last_cc;\n\tu32 nr_commands;\n\tu32 *cc_attrs_tbl;\n\tint locality;\n};\n\nstruct tpm_class_ops {\n\tunsigned int flags;\n\tconst u8 req_complete_mask;\n\tconst u8 req_complete_val;\n\tbool (*req_canceled)(struct tpm_chip *, u8);\n\tint (*recv)(struct tpm_chip *, u8 *, size_t);\n\tint (*send)(struct tpm_chip *, u8 *, size_t, size_t);\n\tvoid (*cancel)(struct tpm_chip *);\n\tu8 (*status)(struct tpm_chip *);\n\tvoid (*update_timeouts)(struct tpm_chip *, long unsigned int *);\n\tvoid (*update_durations)(struct tpm_chip *, long unsigned int *);\n\tint (*go_idle)(struct tpm_chip *);\n\tint (*cmd_ready)(struct tpm_chip *);\n\tint (*request_locality)(struct tpm_chip *, int);\n\tint (*relinquish_locality)(struct tpm_chip *, int);\n\tvoid (*clk_enable)(struct tpm_chip *, bool);\n};\n\nstruct tpm_header {\n\t__be16 tag;\n\t__be32 length;\n\tunion {\n\t\t__be32 ordinal;\n\t\t__be32 return_code;\n\t};\n} __attribute__((packed));\n\nstruct tpm_pcr_attr {\n\tint alg_id;\n\tint pcr;\n\tstruct device_attribute attr;\n};\n\nstruct tpm_readpubek_out {\n\tu8 algorithm[4];\n\tu8 encscheme[2];\n\tu8 sigscheme[2];\n\t__be32 paramsize;\n\tu8 parameters[12];\n\t__be32 keysize;\n\tu8 modulus[256];\n\tu8 checksum[20];\n};\n\nstruct tpmrm_priv {\n\tstruct file_priv priv;\n\tstruct tpm_space space;\n};\n\nstruct trace_module_delta;\n\nstruct trace_pid_list;\n\nstruct tracer_flags;\n\nstruct trace_options;\n\nstruct trace_func_repeats;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tstruct array_buffer array_buffer;\n\tstruct array_buffer snapshot_buffer;\n\tbool allocated_snapshot;\n\tspinlock_t snapshot_trigger_lock;\n\tunsigned int snapshot;\n\tlong unsigned int max_latency;\n\tstruct dentry *d_max_latency;\n\tstruct work_struct fsnotify_work;\n\tstruct irq_work fsnotify_irqwork;\n\tunsigned int mapped;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_size;\n\tchar *range_name;\n\tlong int text_delta;\n\tstruct trace_module_delta *module_delta;\n\tvoid *scratch;\n\tint scratch_size;\n\tint buffer_disabled;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint sys_refcount_enter;\n\tint sys_refcount_exit;\n\tstruct trace_event_file *enter_syscall_files[472];\n\tstruct trace_event_file *exit_syscall_files[472];\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tstruct tracer_flags *current_trace_flags;\n\tu64 trace_flags;\n\tunsigned char trace_flags_index[64];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tconst char *system_names;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct eventfs_inode *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct list_head marker_list;\n\tstruct list_head tracers;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tcpumask_var_t pipe_cpumask;\n\tint ref;\n\tint trace_ref;\n\tstruct list_head mod_events;\n\tstruct ftrace_ops *ops;\n\tstruct trace_pid_list *function_pids;\n\tstruct trace_pid_list *function_no_pids;\n\tstruct fgraph_ops *gops;\n\tstruct list_head func_probes;\n\tstruct list_head mod_trace;\n\tstruct list_head mod_notrace;\n\tint function_enabled;\n\tint no_filter_buffering_ref;\n\tunsigned int syscall_buf_sz;\n\tstruct list_head hist_vars;\n\tstruct cond_snapshot *cond_snapshot;\n\tstruct trace_func_repeats *last_func_repeats;\n\tbool ring_buffer_expanded;\n};\n\nstruct trace_array_cpu {\n\tlocal_t disabled;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tint ftrace_ignore_pid;\n\tbool ignore_pid;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\ntypedef struct trace_buffer *class_ring_buffer_nest_t;\n\nstruct trace_buffer {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tatomic_t resizing;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)(void);\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_end;\n\tstruct ring_buffer_meta *meta;\n\tunsigned int subbuf_size;\n\tunsigned int subbuf_order;\n\tunsigned int max_data_size;\n};\n\nstruct trace_buffer_meta {\n\t__u32 meta_page_size;\n\t__u32 meta_struct_len;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tstruct {\n\t\t__u64 lost_events;\n\t\t__u32 id;\n\t\t__u32 read;\n\t} reader;\n\t__u64 flags;\n\t__u64 entries;\n\t__u64 overrun;\n\t__u64 read;\n\t__u64 Reserved1;\n\t__u64 Reserved2;\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct trace_probe_event;\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_entry_arg *entry_arg;\n\tstruct probe_arg args[0];\n};\n\nstruct trace_eprobe {\n\tconst char *event_system;\n\tconst char *event_name;\n\tchar *filter_str;\n\tstruct trace_event_call *event;\n\tstruct dyn_event devent;\n\tstruct trace_probe tp;\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct trace_event_data_offsets_ack_update_msk {};\n\nstruct trace_event_data_offsets_alarm_class {};\n\nstruct trace_event_data_offsets_alloc_vmap_area {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_blkdev_zone_mgmt {};\n\nstruct trace_event_data_offsets_block_bio {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_completion {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_zwplug {};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\nstruct trace_event_data_offsets_bpf_trace_printk {\n\tu32 bpf_string;\n\tconst void *bpf_string_ptr_;\n};\n\nstruct trace_event_data_offsets_bpf_trigger_tp {};\n\nstruct trace_event_data_offsets_bpf_xdp_link_attach_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_add {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_external_learn_add {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_update {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_mdb_full {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_btrfs__block_group {};\n\nstruct trace_event_data_offsets_btrfs__chunk {};\n\nstruct trace_event_data_offsets_btrfs__file_extent_item_inline {};\n\nstruct trace_event_data_offsets_btrfs__file_extent_item_regular {};\n\nstruct trace_event_data_offsets_btrfs__inode {};\n\nstruct trace_event_data_offsets_btrfs__ordered_extent {};\n\nstruct trace_event_data_offsets_btrfs__prelim_ref {};\n\nstruct trace_event_data_offsets_btrfs__qgroup_rsv_data {};\n\nstruct trace_event_data_offsets_btrfs__reserve_extent {};\n\nstruct trace_event_data_offsets_btrfs__reserved_extent {};\n\nstruct trace_event_data_offsets_btrfs__space_info_update {};\n\nstruct trace_event_data_offsets_btrfs__work {};\n\nstruct trace_event_data_offsets_btrfs__work__done {};\n\nstruct trace_event_data_offsets_btrfs__writepage {};\n\nstruct trace_event_data_offsets_btrfs_add_block_group {};\n\nstruct trace_event_data_offsets_btrfs_alloc_extent_state {};\n\nstruct trace_event_data_offsets_btrfs_clear_extent_bit {};\n\nstruct trace_event_data_offsets_btrfs_convert_extent_bit {};\n\nstruct trace_event_data_offsets_btrfs_cow_block {};\n\nstruct trace_event_data_offsets_btrfs_delayed_data_ref {};\n\nstruct trace_event_data_offsets_btrfs_delayed_ref_head {};\n\nstruct trace_event_data_offsets_btrfs_delayed_tree_ref {};\n\nstruct trace_event_data_offsets_btrfs_dump_space_info {};\n\nstruct trace_event_data_offsets_btrfs_extent_map_shrinker_count {};\n\nstruct trace_event_data_offsets_btrfs_extent_map_shrinker_remove_em {};\n\nstruct trace_event_data_offsets_btrfs_extent_map_shrinker_scan_enter {};\n\nstruct trace_event_data_offsets_btrfs_extent_map_shrinker_scan_exit {};\n\nstruct trace_event_data_offsets_btrfs_failed_cluster_setup {};\n\nstruct trace_event_data_offsets_btrfs_find_cluster {};\n\nstruct trace_event_data_offsets_btrfs_find_free_extent {};\n\nstruct trace_event_data_offsets_btrfs_find_free_extent_have_block_group {};\n\nstruct trace_event_data_offsets_btrfs_find_free_extent_search_loop {};\n\nstruct trace_event_data_offsets_btrfs_finish_ordered_extent {};\n\nstruct trace_event_data_offsets_btrfs_flush_space {};\n\nstruct trace_event_data_offsets_btrfs_free_extent_state {};\n\nstruct trace_event_data_offsets_btrfs_get_extent {};\n\nstruct trace_event_data_offsets_btrfs_get_raid_extent_offset {};\n\nstruct trace_event_data_offsets_btrfs_handle_em_exist {};\n\nstruct trace_event_data_offsets_btrfs_inode_mod_outstanding_extents {};\n\nstruct trace_event_data_offsets_btrfs_insert_one_raid_extent {};\n\nstruct trace_event_data_offsets_btrfs_locking_events {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_account_extent {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_extent {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_meta_convert {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_meta_free_all_pertrans {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_meta_reserve {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_num_dirty_extents {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_update_counters {};\n\nstruct trace_event_data_offsets_btrfs_qgroup_update_reserve {};\n\nstruct trace_event_data_offsets_btrfs_raid56_bio {};\n\nstruct trace_event_data_offsets_btrfs_raid_extent_delete {};\n\nstruct trace_event_data_offsets_btrfs_reserve_ticket {};\n\nstruct trace_event_data_offsets_btrfs_set_extent_bit {};\n\nstruct trace_event_data_offsets_btrfs_setup_cluster {};\n\nstruct trace_event_data_offsets_btrfs_sleep_tree_lock {};\n\nstruct trace_event_data_offsets_btrfs_space_reservation {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_btrfs_sync_file {};\n\nstruct trace_event_data_offsets_btrfs_sync_fs {};\n\nstruct trace_event_data_offsets_btrfs_transaction_commit {};\n\nstruct trace_event_data_offsets_btrfs_trigger_flush {\n\tu32 reason;\n\tconst void *reason_ptr_;\n};\n\nstruct trace_event_data_offsets_btrfs_workqueue {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_btrfs_workqueue_done {};\n\nstruct trace_event_data_offsets_btrfs_writepage_end_io_hook {};\n\nstruct trace_event_data_offsets_cap_capable {};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tconst void *dst_path_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_rstat {};\n\nstruct trace_event_data_offsets_cma_alloc_busy_retry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_finish {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_start {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_release {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_compact_retry {};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_contention_begin {};\n\nstruct trace_event_data_offsets_contention_end {};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_cpu_idle_miss {};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_csd_function {};\n\nstruct trace_event_data_offsets_csd_queue_cpu {};\n\nstruct trace_event_data_offsets_ctime {};\n\nstruct trace_event_data_offsets_ctime_ns_xchg {};\n\nstruct trace_event_data_offsets_dax_pmd_fault_class {};\n\nstruct trace_event_data_offsets_dax_pmd_load_hole_class {};\n\nstruct trace_event_data_offsets_dax_pte_fault_class {};\n\nstruct trace_event_data_offsets_dax_writeback_one {};\n\nstruct trace_event_data_offsets_dax_writeback_range_class {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_recover_aborted {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_reporter_state_update {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwerr {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwmsg {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_trap_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 trap_name;\n\tconst void *trap_name_ptr_;\n\tu32 trap_group_name;\n\tconst void *trap_group_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devres {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_attach_dev {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_fd {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence_unsignaled {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg_err {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_single {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 addrs;\n\tconst void *addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dql_stall_detected {};\n\nstruct trace_event_data_offsets_error_report_template {};\n\nstruct trace_event_data_offsets_exit_mmap {};\n\nstruct trace_event_data_offsets_ext4__bitmap_load {};\n\nstruct trace_event_data_offsets_ext4__es_extent {};\n\nstruct trace_event_data_offsets_ext4__es_shrink_enter {};\n\nstruct trace_event_data_offsets_ext4__fallocate_mode {};\n\nstruct trace_event_data_offsets_ext4__folio_op {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_enter {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_exit {};\n\nstruct trace_event_data_offsets_ext4__mb_new_pa {};\n\nstruct trace_event_data_offsets_ext4__mballoc {};\n\nstruct trace_event_data_offsets_ext4__trim {};\n\nstruct trace_event_data_offsets_ext4__truncate {};\n\nstruct trace_event_data_offsets_ext4__write_begin {};\n\nstruct trace_event_data_offsets_ext4__write_end {};\n\nstruct trace_event_data_offsets_ext4_alloc_da_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_inode {};\n\nstruct trace_event_data_offsets_ext4_begin_ordered_truncate {};\n\nstruct trace_event_data_offsets_ext4_collapse_range {};\n\nstruct trace_event_data_offsets_ext4_da_release_space {};\n\nstruct trace_event_data_offsets_ext4_da_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_update_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_end {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_start {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages_extent {};\n\nstruct trace_event_data_offsets_ext4_discard_blocks {};\n\nstruct trace_event_data_offsets_ext4_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_drop_inode {};\n\nstruct trace_event_data_offsets_ext4_error {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_enter {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_exit {};\n\nstruct trace_event_data_offsets_ext4_es_insert_delayed_extent {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_es_remove_extent {};\n\nstruct trace_event_data_offsets_ext4_es_shrink {};\n\nstruct trace_event_data_offsets_ext4_es_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_ext4_evict_inode {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_enter {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_fastpath {};\n\nstruct trace_event_data_offsets_ext4_ext_handle_unwritten_extents {};\n\nstruct trace_event_data_offsets_ext4_ext_load_extent {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space_done {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_idx {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_leaf {};\n\nstruct trace_event_data_offsets_ext4_ext_show_extent {};\n\nstruct trace_event_data_offsets_ext4_fallocate_exit {};\n\nstruct trace_event_data_offsets_ext4_fc_cleanup {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_start {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_stop {};\n\nstruct trace_event_data_offsets_ext4_fc_replay {};\n\nstruct trace_event_data_offsets_ext4_fc_replay_scan {};\n\nstruct trace_event_data_offsets_ext4_fc_stats {};\n\nstruct trace_event_data_offsets_ext4_fc_track_dentry {};\n\nstruct trace_event_data_offsets_ext4_fc_track_inode {};\n\nstruct trace_event_data_offsets_ext4_fc_track_range {};\n\nstruct trace_event_data_offsets_ext4_forget {};\n\nstruct trace_event_data_offsets_ext4_free_blocks {};\n\nstruct trace_event_data_offsets_ext4_free_inode {};\n\nstruct trace_event_data_offsets_ext4_fsmap_class {};\n\nstruct trace_event_data_offsets_ext4_get_implied_cluster_alloc_exit {};\n\nstruct trace_event_data_offsets_ext4_getfsmap_class {};\n\nstruct trace_event_data_offsets_ext4_insert_range {};\n\nstruct trace_event_data_offsets_ext4_invalidate_folio_op {};\n\nstruct trace_event_data_offsets_ext4_journal_start_inode {};\n\nstruct trace_event_data_offsets_ext4_journal_start_reserved {};\n\nstruct trace_event_data_offsets_ext4_journal_start_sb {};\n\nstruct trace_event_data_offsets_ext4_lazy_itable_init {};\n\nstruct trace_event_data_offsets_ext4_load_inode {};\n\nstruct trace_event_data_offsets_ext4_mark_inode_dirty {};\n\nstruct trace_event_data_offsets_ext4_mb_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_mb_release_group_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_inode_pa {};\n\nstruct trace_event_data_offsets_ext4_mballoc_alloc {};\n\nstruct trace_event_data_offsets_ext4_mballoc_prealloc {};\n\nstruct trace_event_data_offsets_ext4_move_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_move_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_nfs_commit_metadata {};\n\nstruct trace_event_data_offsets_ext4_other_inode_update_time {};\n\nstruct trace_event_data_offsets_ext4_prefetch_bitmaps {};\n\nstruct trace_event_data_offsets_ext4_read_block_bitmap_load {};\n\nstruct trace_event_data_offsets_ext4_remove_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_inode {};\n\nstruct trace_event_data_offsets_ext4_shutdown {};\n\nstruct trace_event_data_offsets_ext4_sync_file_enter {};\n\nstruct trace_event_data_offsets_ext4_sync_file_exit {};\n\nstruct trace_event_data_offsets_ext4_sync_fs {};\n\nstruct trace_event_data_offsets_ext4_unlink_enter {};\n\nstruct trace_event_data_offsets_ext4_unlink_exit {};\n\nstruct trace_event_data_offsets_ext4_update_sb {};\n\nstruct trace_event_data_offsets_ext4_writepages {};\n\nstruct trace_event_data_offsets_ext4_writepages_result {};\n\nstruct trace_event_data_offsets_fdb_delete {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_fib6_table_lookup {};\n\nstruct trace_event_data_offsets_fib_table_lookup {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_fill_mg_cmtime {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_flush_foreign {};\n\nstruct trace_event_data_offsets_free_vmap_area_noflush {};\n\nstruct trace_event_data_offsets_fsverity_enable {};\n\nstruct trace_event_data_offsets_fsverity_merkle_hit {};\n\nstruct trace_event_data_offsets_fsverity_tree_done {\n\tu32 root_hash;\n\tconst void *root_hash_ptr_;\n\tu32 file_digest;\n\tconst void *file_digest_ptr_;\n};\n\nstruct trace_event_data_offsets_fsverity_verify_data_block {};\n\nstruct trace_event_data_offsets_fsverity_verify_merkle_block {};\n\nstruct trace_event_data_offsets_fuse_request_end {};\n\nstruct trace_event_data_offsets_fuse_request_send {};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_guest_halt_poll_ns {};\n\nstruct trace_event_data_offsets_handshake_alert_class {};\n\nstruct trace_event_data_offsets_handshake_complete {};\n\nstruct trace_event_data_offsets_handshake_error_class {};\n\nstruct trace_event_data_offsets_handshake_event_class {};\n\nstruct trace_event_data_offsets_handshake_fd_class {};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_setup {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hugetlbfs__inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_alloc_inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_fallocate {};\n\nstruct trace_event_data_offsets_hugetlbfs_setattr {\n\tu32 d_name;\n\tconst void *d_name_ptr_;\n};\n\nstruct trace_event_data_offsets_icmp_send {};\n\nstruct trace_event_data_offsets_inet_sk_error_report {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n\tconst void *level_ptr_;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_inode_foreign_history {};\n\nstruct trace_event_data_offsets_inode_switch_wbs {};\n\nstruct trace_event_data_offsets_inode_switch_wbs_queue {};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_cqe_overflow {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_defer {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_fail_link {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_local_work_run {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_req_failed {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_short_write {};\n\nstruct trace_event_data_offsets_io_uring_submit_req {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_add {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_work_run {};\n\nstruct trace_event_data_offsets_iocg_inuse_update {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_ioc_vrate_adj {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_iocg_forgive_debt {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_iocg_state {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iomap_add_to_ioend {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_dio_complete {};\n\nstruct trace_event_data_offsets_iomap_dio_rw_begin {};\n\nstruct trace_event_data_offsets_iomap_iter {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_send_cpu {};\n\nstruct trace_event_data_offsets_ipi_send_cpumask {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint_stats {};\n\nstruct trace_event_data_offsets_jbd2_commit {};\n\nstruct trace_event_data_offsets_jbd2_end_commit {};\n\nstruct trace_event_data_offsets_jbd2_handle_extend {};\n\nstruct trace_event_data_offsets_jbd2_handle_start_class {};\n\nstruct trace_event_data_offsets_jbd2_handle_stats {};\n\nstruct trace_event_data_offsets_jbd2_journal_shrink {};\n\nstruct trace_event_data_offsets_jbd2_lock_buffer_stall {};\n\nstruct trace_event_data_offsets_jbd2_run_stats {};\n\nstruct trace_event_data_offsets_jbd2_shrink_checkpoint_list {};\n\nstruct trace_event_data_offsets_jbd2_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_jbd2_submit_inode_data {};\n\nstruct trace_event_data_offsets_jbd2_update_log_tail {};\n\nstruct trace_event_data_offsets_jbd2_write_superblock {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\nstruct trace_event_data_offsets_kfree {};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_kmalloc {};\n\nstruct trace_event_data_offsets_kmem_cache_alloc {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kmem_cache_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_ksm_advisor {};\n\nstruct trace_event_data_offsets_ksm_enter_exit_template {};\n\nstruct trace_event_data_offsets_ksm_merge_one_page {};\n\nstruct trace_event_data_offsets_ksm_merge_with_ksm_page {};\n\nstruct trace_event_data_offsets_ksm_remove_ksm_page {};\n\nstruct trace_event_data_offsets_ksm_remove_rmap_item {};\n\nstruct trace_event_data_offsets_ksm_scan_template {};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_ma_op {};\n\nstruct trace_event_data_offsets_ma_read {};\n\nstruct trace_event_data_offsets_ma_write {};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_mark_victim {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_memcg_flush_stats {};\n\nstruct trace_event_data_offsets_memcg_rstat_events {};\n\nstruct trace_event_data_offsets_memcg_rstat_stats {};\n\nstruct trace_event_data_offsets_migration_pmd {};\n\nstruct trace_event_data_offsets_migration_pte {};\n\nstruct trace_event_data_offsets_mm_calculate_totalreserve_pages {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page_isolate {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page_swapin {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_filemap_fault {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache_range {};\n\nstruct trace_event_data_offsets_mm_khugepaged_collapse_file {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_khugepaged_scan_file {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_khugepaged_scan_pmd {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\nstruct trace_event_data_offsets_mm_migrate_pages_start {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_lowmem_reserve {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 upper_name;\n\tconst void *upper_name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_wmarks {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_clear_hopeless {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_reclaim_fail {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\nstruct trace_event_data_offsets_mm_vmscan_reclaim_pages {};\n\nstruct trace_event_data_offsets_mm_vmscan_throttled {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_write_folio {};\n\nstruct trace_event_data_offsets_mmap_lock {};\n\nstruct trace_event_data_offsets_mmap_lock_acquire_returned {};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mptcp_dump_mpext {};\n\nstruct trace_event_data_offsets_mptcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_mptcp_subflow_get_send {};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_netlink_extack {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_notifier_info {};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_page_cache_ra_op {};\n\nstruct trace_event_data_offsets_page_cache_ra_order {};\n\nstruct trace_event_data_offsets_page_cache_ra_unbounded {};\n\nstruct trace_event_data_offsets_page_pool_release {};\n\nstruct trace_event_data_offsets_page_pool_state_hold {};\n\nstruct trace_event_data_offsets_page_pool_state_release {};\n\nstruct trace_event_data_offsets_page_pool_update_nid {};\n\nstruct trace_event_data_offsets_pci_hp_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n\tu32 slot;\n\tconst void *slot_ptr_;\n};\n\nstruct trace_event_data_offsets_pcie_link_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_purge_vmap_area_lazy {};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_enqueue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kvfree_callback {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_segcb_stats {};\n\nstruct trace_event_data_offsets_rcu_sr_normal {};\n\nstruct trace_event_data_offsets_rcu_stall_warning {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_watching {};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\nstruct trace_event_data_offsets_s390_ap_nqapdqap_template {};\n\nstruct trace_event_data_offsets_s390_cio_adapter_int {};\n\nstruct trace_event_data_offsets_s390_cio_chsc {};\n\nstruct trace_event_data_offsets_s390_cio_interrupt {};\n\nstruct trace_event_data_offsets_s390_cio_ssch {};\n\nstruct trace_event_data_offsets_s390_cio_stcrw {};\n\nstruct trace_event_data_offsets_s390_cio_tpi {};\n\nstruct trace_event_data_offsets_s390_cio_tsch {};\n\nstruct trace_event_data_offsets_s390_class_schib {};\n\nstruct trace_event_data_offsets_s390_class_schid {};\n\nstruct trace_event_data_offsets_s390_diagnose {};\n\nstruct trace_event_data_offsets_s390_hd_rebuild_domains {};\n\nstruct trace_event_data_offsets_s390_hd_work_fn {};\n\nstruct trace_event_data_offsets_sched_ext_bypass_lb {};\n\nstruct trace_event_data_offsets_sched_ext_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_ext_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_end {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_start {};\n\nstruct trace_event_data_offsets_sched_kthread_work_queue_work {};\n\nstruct trace_event_data_offsets_sched_migrate_task {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_move_numa {};\n\nstruct trace_event_data_offsets_sched_numa_pair_template {};\n\nstruct trace_event_data_offsets_sched_pi_setprio {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_prepare_exec {\n\tu32 interp;\n\tconst void *interp_ptr_;\n\tu32 filename;\n\tconst void *filename_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exit {};\n\nstruct trace_event_data_offsets_sched_process_fork {\n\tu32 parent_comm;\n\tconst void *parent_comm_ptr_;\n\tu32 child_comm;\n\tconst void *child_comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_wait {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_skip_cpuset_numa {};\n\nstruct trace_event_data_offsets_sched_skip_vma_numa {};\n\nstruct trace_event_data_offsets_sched_stat_runtime {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_stat_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\nstruct trace_event_data_offsets_selinux_audited {\n\tu32 scontext;\n\tconst void *scontext_ptr_;\n\tu32 tcontext;\n\tconst void *tcontext_ptr_;\n\tu32 tclass;\n\tconst void *tclass_ptr_;\n};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_sk_data_ready {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_sock_msg_length {};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_softirq {};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_subflow_check_data_avail {};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_swiotlb_bounced {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_prctl_unknown {};\n\nstruct trace_event_data_offsets_task_rename {};\n\nstruct trace_event_data_offsets_tasklet {};\n\nstruct trace_event_data_offsets_tcp_ao_event {};\n\nstruct trace_event_data_offsets_tcp_cong_state_set {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_event_skb {};\n\nstruct trace_event_data_offsets_tcp_hash_event {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\nstruct trace_event_data_offsets_tcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_tcp_retransmit_skb {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_send_reset {};\n\nstruct trace_event_data_offsets_tcp_sendmsg_locked {};\n\nstruct trace_event_data_offsets_test_pages_isolated {};\n\nstruct trace_event_data_offsets_tick_stop {};\n\nstruct trace_event_data_offsets_timer_base_idle {};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_tls_contenttype {};\n\nstruct trace_event_data_offsets_tmigr_connect_child_parent {};\n\nstruct trace_event_data_offsets_tmigr_connect_cpu_parent {};\n\nstruct trace_event_data_offsets_tmigr_cpugroup {};\n\nstruct trace_event_data_offsets_tmigr_group_and_cpu {};\n\nstruct trace_event_data_offsets_tmigr_group_set {};\n\nstruct trace_event_data_offsets_tmigr_handle_remote {};\n\nstruct trace_event_data_offsets_tmigr_idle {};\n\nstruct trace_event_data_offsets_tmigr_update_events {};\n\nstruct trace_event_data_offsets_track_foreign_dirty {};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_watchdog_set_timeout {};\n\nstruct trace_event_data_offsets_watchdog_template {};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_wbt_lat {};\n\nstruct trace_event_data_offsets_wbt_stat {};\n\nstruct trace_event_data_offsets_wbt_step {};\n\nstruct trace_event_data_offsets_wbt_timer {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_queue_work {\n\tu32 workqueue;\n\tconst void *workqueue_ptr_;\n};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_folio_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_data_offsets_xfs_ag_class {};\n\nstruct trace_event_data_offsets_xfs_ag_inode_class {};\n\nstruct trace_event_data_offsets_xfs_ag_resv_class {};\n\nstruct trace_event_data_offsets_xfs_ag_resv_init_error {};\n\nstruct trace_event_data_offsets_xfs_agf_class {};\n\nstruct trace_event_data_offsets_xfs_ail_class {};\n\nstruct trace_event_data_offsets_xfs_alloc_class {};\n\nstruct trace_event_data_offsets_xfs_alloc_cur_check {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_attr_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_attr_list_class {};\n\nstruct trace_event_data_offsets_xfs_attr_list_node_descend {};\n\nstruct trace_event_data_offsets_xfs_bmap_class {};\n\nstruct trace_event_data_offsets_xfs_bmap_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_btree_alloc_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_bload_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_bload_level_geometry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_commit_afakeroot {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_commit_ifakeroot {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_cur_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_error_class {};\n\nstruct trace_event_data_offsets_xfs_btree_free_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_buf_class {};\n\nstruct trace_event_data_offsets_xfs_buf_flags_class {};\n\nstruct trace_event_data_offsets_xfs_buf_ioerror {};\n\nstruct trace_event_data_offsets_xfs_buf_item_class {};\n\nstruct trace_event_data_offsets_xfs_bunmap {};\n\nstruct trace_event_data_offsets_xfs_calc_atomic_write_unit_max {};\n\nstruct trace_event_data_offsets_xfs_calc_max_atomic_write_fsblocks {};\n\nstruct trace_event_data_offsets_xfs_calc_max_atomic_write_log_geometry {};\n\nstruct trace_event_data_offsets_xfs_check_new_dalign {};\n\nstruct trace_event_data_offsets_xfs_da_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_das_state_class {};\n\nstruct trace_event_data_offsets_xfs_defer_class {};\n\nstruct trace_event_data_offsets_xfs_defer_error_class {};\n\nstruct trace_event_data_offsets_xfs_defer_pending_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_defer_pending_item_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_dir2_leafn_moveents {};\n\nstruct trace_event_data_offsets_xfs_dir2_space_class {};\n\nstruct trace_event_data_offsets_xfs_discard_class {};\n\nstruct trace_event_data_offsets_xfs_double_io_class {};\n\nstruct trace_event_data_offsets_xfs_dqtrx_class {};\n\nstruct trace_event_data_offsets_xfs_dquot_class {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_delta_nextents {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_delta_nextents_step {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_estimate_class {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_intent_class {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_overhead {};\n\nstruct trace_event_data_offsets_xfs_exchrange_class {};\n\nstruct trace_event_data_offsets_xfs_exchrange_freshness {};\n\nstruct trace_event_data_offsets_xfs_exchrange_inode_class {};\n\nstruct trace_event_data_offsets_xfs_extent_busy_class {};\n\nstruct trace_event_data_offsets_xfs_extent_busy_trim {};\n\nstruct trace_event_data_offsets_xfs_fault_class {};\n\nstruct trace_event_data_offsets_xfs_file_class {};\n\nstruct trace_event_data_offsets_xfs_filestream_class {};\n\nstruct trace_event_data_offsets_xfs_filestream_pick {};\n\nstruct trace_event_data_offsets_xfs_force_shutdown {\n\tu32 fname;\n\tconst void *fname_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_free_extent {};\n\nstruct trace_event_data_offsets_xfs_free_extent_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_freeblocks_resv_class {};\n\nstruct trace_event_data_offsets_xfs_fs_class {};\n\nstruct trace_event_data_offsets_xfs_fs_corrupt_class {};\n\nstruct trace_event_data_offsets_xfs_fsmap_group_key_class {};\n\nstruct trace_event_data_offsets_xfs_fsmap_linear_key_class {};\n\nstruct trace_event_data_offsets_xfs_fsmap_mapping {};\n\nstruct trace_event_data_offsets_xfs_getfsmap_class {};\n\nstruct trace_event_data_offsets_xfs_getparents_class {};\n\nstruct trace_event_data_offsets_xfs_getparents_rec_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_group_class {};\n\nstruct trace_event_data_offsets_xfs_group_corrupt_class {};\n\nstruct trace_event_data_offsets_xfs_growfs_check_rtgeom {};\n\nstruct trace_event_data_offsets_xfs_healthmon_class {};\n\nstruct trace_event_data_offsets_xfs_healthmon_copybuf {};\n\nstruct trace_event_data_offsets_xfs_healthmon_create {};\n\nstruct trace_event_data_offsets_xfs_healthmon_event_class {};\n\nstruct trace_event_data_offsets_xfs_healthmon_lost_event {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_file_ioerror {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_fs {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_group {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_inode {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_media {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_shutdown {};\n\nstruct trace_event_data_offsets_xfs_icwalk_class {};\n\nstruct trace_event_data_offsets_xfs_imap_class {};\n\nstruct trace_event_data_offsets_xfs_inode_class {};\n\nstruct trace_event_data_offsets_xfs_inode_corrupt_class {};\n\nstruct trace_event_data_offsets_xfs_inode_error_class {};\n\nstruct trace_event_data_offsets_xfs_inode_irec_class {};\n\nstruct trace_event_data_offsets_xfs_inode_reload_unlinked_bucket {};\n\nstruct trace_event_data_offsets_xfs_inodegc_shrinker_scan {};\n\nstruct trace_event_data_offsets_xfs_inodegc_worker {};\n\nstruct trace_event_data_offsets_xfs_iomap_atomic_write_cow {};\n\nstruct trace_event_data_offsets_xfs_iomap_invalid_class {};\n\nstruct trace_event_data_offsets_xfs_iomap_prealloc_size {};\n\nstruct trace_event_data_offsets_xfs_irec_merge_post {};\n\nstruct trace_event_data_offsets_xfs_irec_merge_pre {};\n\nstruct trace_event_data_offsets_xfs_iref_class {};\n\nstruct trace_event_data_offsets_xfs_itrunc_class {};\n\nstruct trace_event_data_offsets_xfs_iunlink_reload_next {};\n\nstruct trace_event_data_offsets_xfs_iunlink_update_bucket {};\n\nstruct trace_event_data_offsets_xfs_iunlink_update_dinode {};\n\nstruct trace_event_data_offsets_xfs_iwalk_ag_rec {};\n\nstruct trace_event_data_offsets_xfs_lock_class {};\n\nstruct trace_event_data_offsets_xfs_log_assign_tail_lsn {};\n\nstruct trace_event_data_offsets_xfs_log_force {};\n\nstruct trace_event_data_offsets_xfs_log_get_max_trans_res {};\n\nstruct trace_event_data_offsets_xfs_log_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover {};\n\nstruct trace_event_data_offsets_xfs_log_recover_buf_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_icreate_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_ino_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_record {};\n\nstruct trace_event_data_offsets_xfs_loggrant_class {};\n\nstruct trace_event_data_offsets_xfs_metadir_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_metadir_update_class {\n\tu32 fname;\n\tconst void *fname_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_metadir_update_error_class {\n\tu32 fname;\n\tconst void *fname_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_metafile_resv_class {};\n\nstruct trace_event_data_offsets_xfs_namespace_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_perag_class {};\n\nstruct trace_event_data_offsets_xfs_pwork_init {};\n\nstruct trace_event_data_offsets_xfs_refcount_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_double_extent_at_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_double_extent_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_extent_at_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_extent_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_lookup {};\n\nstruct trace_event_data_offsets_xfs_refcount_triple_extent_class {};\n\nstruct trace_event_data_offsets_xfs_reflink_remap_blocks {};\n\nstruct trace_event_data_offsets_xfs_rename {\n\tu32 src_name;\n\tconst void *src_name_ptr_;\n\tu32 target_name;\n\tconst void *target_name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_rmap_class {};\n\nstruct trace_event_data_offsets_xfs_rmap_convert_state {};\n\nstruct trace_event_data_offsets_xfs_rmap_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_rmapbt_class {};\n\nstruct trace_event_data_offsets_xfs_rtalloc_extent_busy {};\n\nstruct trace_event_data_offsets_xfs_rtalloc_extent_busy_trim {};\n\nstruct trace_event_data_offsets_xfs_rtdiscard_class {};\n\nstruct trace_event_data_offsets_xfs_simple_io_class {};\n\nstruct trace_event_data_offsets_xfs_swap_extent_class {};\n\nstruct trace_event_data_offsets_xfs_timestamp_range_class {};\n\nstruct trace_event_data_offsets_xfs_trans_class {};\n\nstruct trace_event_data_offsets_xfs_trans_mod_dquot {};\n\nstruct trace_event_data_offsets_xfs_trans_resv_class {};\n\nstruct trace_event_data_offsets_xfs_verify_media {};\n\nstruct trace_event_data_offsets_xfs_verify_media_end {};\n\nstruct trace_event_data_offsets_xfs_verify_media_error {};\n\nstruct trace_event_data_offsets_xfs_wb_invalid_class {};\n\nstruct trace_event_data_offsets_xfs_zone_alloc_class {};\n\nstruct trace_event_data_offsets_xfs_zone_class {};\n\nstruct trace_event_data_offsets_xfs_zone_free_blocks {};\n\nstruct trace_event_data_offsets_xfs_zone_gc_select_victim {};\n\nstruct trace_event_data_offsets_xfs_zones_mount {};\n\nstruct trace_event_data_offsets_xlog_iclog_class {};\n\nstruct trace_event_data_offsets_xlog_intent_recovery_failed {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst unsigned int is_signed: 1;\n\t\t\tunsigned int needs_test: 1;\n\t\t\tconst int filter_type;\n\t\t\tconst int len;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct eventfs_inode *ei;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\trefcount_t ref;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nstruct trace_event_raw_ack_update_msk {\n\tstruct trace_entry ent;\n\tu64 data_ack;\n\tu64 old_snd_una;\n\tu64 new_snd_una;\n\tu64 new_wnd_end;\n\tu64 msk_wnd_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alloc_vmap_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int vstart;\n\tlong unsigned int vend;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int wb_setpoint;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_blkdev_zone_mgmt {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t nr_sectors;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_completion {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_zwplug {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int zno;\n\tsector_t sector;\n\tunsigned int nr_sectors;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trace_printk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bpf_string;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trigger_tp {\n\tstruct trace_entry ent;\n\tint nonce;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_xdp_link_attach_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_add {\n\tstruct trace_entry ent;\n\tu8 ndm_flags;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tu16 nlh_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_external_learn_add {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_mdb_full {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tint af;\n\tu16 vid;\n\t__u8 src[16];\n\t__u8 grp[16];\n\t__u8 grpmac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__block_group {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bytenr;\n\tu64 len;\n\tu64 used;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__chunk {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tint num_stripes;\n\tu64 type;\n\tint sub_stripes;\n\tu64 offset;\n\tu64 size;\n\tu64 root_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__file_extent_item_inline {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_obj;\n\tu64 ino;\n\tloff_t isize;\n\tu64 disk_isize;\n\tu8 extent_type;\n\tu8 compression;\n\tu64 extent_start;\n\tu64 extent_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__file_extent_item_regular {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_obj;\n\tu64 ino;\n\tloff_t isize;\n\tu64 disk_isize;\n\tu64 num_bytes;\n\tu64 ram_bytes;\n\tu64 disk_bytenr;\n\tu64 disk_num_bytes;\n\tu64 extent_offset;\n\tu8 extent_type;\n\tu8 compression;\n\tu64 extent_start;\n\tu64 extent_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__inode {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 ino;\n\tu64 blocks;\n\tu64 disk_i_size;\n\tu64 generation;\n\tu64 last_trans;\n\tu64 logged_trans;\n\tu64 root_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__ordered_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 ino;\n\tu64 file_offset;\n\tu64 start;\n\tu64 len;\n\tu64 disk_len;\n\tu64 bytes_left;\n\tlong unsigned int flags;\n\tint compress_type;\n\tint refs;\n\tu64 root_objectid;\n\tu64 truncated_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__prelim_ref {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_id;\n\tu64 objectid;\n\tu8 type;\n\tu64 offset;\n\tint level;\n\tint old_count;\n\tu64 parent;\n\tu64 bytenr;\n\tint mod_count;\n\tu64 tree_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__qgroup_rsv_data {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 rootid;\n\tu64 ino;\n\tu64 start;\n\tu64 len;\n\tu64 reserved;\n\tint op;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__reserve_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bg_objectid;\n\tu64 flags;\n\tint bg_size_class;\n\tu64 start;\n\tu64 len;\n\tu64 loop;\n\tbool hinted;\n\tint size_class;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__reserved_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 start;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__space_info_update {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 type;\n\tu64 old;\n\ts64 diff;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__work {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tconst void *work;\n\tconst void *wq;\n\tconst void *func;\n\tconst void *ordered_func;\n\tconst void *normal_work;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__work__done {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tconst void *wtag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs__writepage {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 ino;\n\tlong unsigned int index;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tlong unsigned int writeback_index;\n\tu64 root_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_add_block_group {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n\tu64 bytes_used;\n\tu64 bytes_super;\n\tint create;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_alloc_extent_state {\n\tstruct trace_entry ent;\n\tconst struct extent_state *state;\n\tlong unsigned int mask;\n\tconst void *ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_clear_extent_bit {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tunsigned int owner;\n\tu64 ino;\n\tu64 rootid;\n\tu64 start;\n\tu64 len;\n\tunsigned int clear_bits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_convert_extent_bit {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tunsigned int owner;\n\tu64 ino;\n\tu64 rootid;\n\tu64 start;\n\tu64 len;\n\tunsigned int set_bits;\n\tunsigned int clear_bits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_cow_block {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_objectid;\n\tu64 buf_start;\n\tint refs;\n\tu64 cow_start;\n\tint buf_level;\n\tint cow_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_delayed_data_ref {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bytenr;\n\tu64 num_bytes;\n\tint action;\n\tu64 parent;\n\tu64 ref_root;\n\tu64 owner;\n\tu64 offset;\n\tint type;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_delayed_ref_head {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bytenr;\n\tu64 num_bytes;\n\tint action;\n\tint is_data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_delayed_tree_ref {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bytenr;\n\tu64 num_bytes;\n\tint action;\n\tu64 parent;\n\tu64 ref_root;\n\tint level;\n\tint type;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_dump_space_info {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 flags;\n\tu64 total_bytes;\n\tu64 bytes_used;\n\tu64 bytes_pinned;\n\tu64 bytes_reserved;\n\tu64 bytes_may_use;\n\tu64 bytes_readonly;\n\tu64 reclaim_size;\n\tint clamp;\n\tu64 global_reserved;\n\tu64 trans_reserved;\n\tu64 delayed_refs_reserved;\n\tu64 delayed_reserved;\n\tu64 free_chunk_space;\n\tu64 delalloc_bytes;\n\tu64 ordered_bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_extent_map_shrinker_count {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tlong int nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_extent_map_shrinker_remove_em {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 ino;\n\tu64 root_id;\n\tu64 start;\n\tu64 len;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_extent_map_shrinker_scan_enter {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tlong int nr_to_scan;\n\tlong int nr;\n\tu64 last_root_id;\n\tu64 last_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_extent_map_shrinker_scan_exit {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tlong int nr_dropped;\n\tlong int nr;\n\tu64 last_root_id;\n\tu64 last_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_failed_cluster_setup {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bg_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_find_cluster {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bg_objectid;\n\tu64 flags;\n\tu64 start;\n\tu64 bytes;\n\tu64 empty_size;\n\tu64 min_bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_find_free_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_objectid;\n\tu64 num_bytes;\n\tu64 empty_size;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_find_free_extent_have_block_group {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_objectid;\n\tu64 num_bytes;\n\tu64 empty_size;\n\tu64 flags;\n\tu64 loop;\n\tbool hinted;\n\tu64 bg_start;\n\tu64 bg_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_find_free_extent_search_loop {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_objectid;\n\tu64 num_bytes;\n\tu64 empty_size;\n\tu64 flags;\n\tu64 loop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_finish_ordered_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 ino;\n\tu64 start;\n\tu64 len;\n\tbool uptodate;\n\tu64 root_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_flush_space {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 flags;\n\tu64 num_bytes;\n\tint state;\n\tint ret;\n\tbool for_preempt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_free_extent_state {\n\tstruct trace_entry ent;\n\tconst struct extent_state *state;\n\tconst void *ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_get_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_objectid;\n\tu64 ino;\n\tu64 start;\n\tu64 len;\n\tu32 flags;\n\tint refs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_get_raid_extent_offset {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 logical;\n\tu64 length;\n\tu64 physical;\n\tu64 devid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_handle_em_exist {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 e_start;\n\tu64 e_len;\n\tu64 map_start;\n\tu64 map_len;\n\tu64 start;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_inode_mod_outstanding_extents {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 root_objectid;\n\tu64 ino;\n\tint mod;\n\tunsigned int outstanding;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_insert_one_raid_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 logical;\n\tu64 length;\n\tint num_stripes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_locking_events {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 block;\n\tu64 generation;\n\tu64 owner;\n\tint is_log_tree;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_account_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 transid;\n\tu64 bytenr;\n\tu64 num_bytes;\n\tu64 nr_old_roots;\n\tu64 nr_new_roots;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_extent {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bytenr;\n\tu64 num_bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_meta_convert {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 refroot;\n\ts64 diff;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_meta_free_all_pertrans {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 refroot;\n\ts64 diff;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_meta_reserve {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 refroot;\n\ts64 diff;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_num_dirty_extents {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 transid;\n\tu64 num_dirty_extents;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_update_counters {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 qgid;\n\tu64 old_rfer;\n\tu64 old_excl;\n\tu64 cur_old_count;\n\tu64 cur_new_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_qgroup_update_reserve {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 qgid;\n\tu64 cur_reserved;\n\ts64 diff;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_raid56_bio {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 full_stripe;\n\tu64 physical;\n\tu64 devid;\n\tu32 offset;\n\tu32 len;\n\tu8 opf;\n\tu8 total_stripes;\n\tu8 real_stripes;\n\tu8 nr_data;\n\tu8 stripe_nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_raid_extent_delete {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 start;\n\tu64 end;\n\tu64 found_start;\n\tu64 found_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_reserve_ticket {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 flags;\n\tu64 bytes;\n\tu64 start_ns;\n\tint flush;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_set_extent_bit {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tunsigned int owner;\n\tu64 ino;\n\tu64 rootid;\n\tu64 start;\n\tu64 len;\n\tunsigned int set_bits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_setup_cluster {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 bg_objectid;\n\tu64 flags;\n\tu64 start;\n\tu64 max_size;\n\tu64 size;\n\tint bitmap;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_sleep_tree_lock {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 block;\n\tu64 generation;\n\tu64 start_ns;\n\tu64 end_ns;\n\tu64 diff_ns;\n\tu64 owner;\n\tint is_log_tree;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_space_reservation {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu32 __data_loc_type;\n\tu64 val;\n\tu64 bytes;\n\tint reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_sync_file {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 ino;\n\tu64 parent;\n\tint datasync;\n\tu64 root_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_sync_fs {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_transaction_commit {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 generation;\n\tu64 root_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_trigger_flush {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 flags;\n\tu64 bytes;\n\tint flush;\n\tu32 __data_loc_reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_workqueue {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tconst void *wq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_workqueue_done {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tconst void *wq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_btrfs_writepage_end_io_hook {\n\tstruct trace_entry ent;\n\tu8 fsid[16];\n\tu64 ino;\n\tu64 start;\n\tu64 end;\n\tint uptodate;\n\tu64 root_objectid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cap_capable {\n\tstruct trace_entry ent;\n\tconst struct cred *cred;\n\tstruct user_namespace *target_ns;\n\tconst struct user_namespace *capable_ns;\n\tint cap;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_level;\n\tu64 dst_id;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu32 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_rstat {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tint cpu;\n\tbool contended;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_busy_retry {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_finish {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tint errorno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int request_count;\n\tlong unsigned int available_count;\n\tlong unsigned int total_count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_release {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_begin {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_end {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_idle_miss {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool below;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_function {\n\tstruct trace_entry ent;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_queue_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\tu32 ctime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime_ns_xchg {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tu32 gen;\n\tu32 old;\n\tu32 new;\n\tu32 cur;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pmd_fault_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tlong unsigned int pgoff;\n\tlong unsigned int max_pgoff;\n\tdev_t dev;\n\tunsigned int flags;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pmd_load_hole_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tstruct folio *zero_folio;\n\tvoid *radix_entry;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pte_fault_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tlong unsigned int pgoff;\n\tdev_t dev;\n\tunsigned int flags;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_writeback_one {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_writeback_range_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int start_index;\n\tlong unsigned int end_index;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_recover_aborted {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tbool health_state;\n\tu64 time_since_last_recover;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_reporter_state_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu8 new_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwerr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tint err;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwmsg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tbool incoming;\n\tlong unsigned int type;\n\tu32 __data_loc_buf;\n\tsize_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_trap_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_trap_name;\n\tu32 __data_loc_trap_group_name;\n\tchar input_dev_name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devres {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tstruct device *dev;\n\tconst char *op;\n\tvoid *node;\n\tu32 __data_loc_name;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tgfp_t flags;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tgfp_t flags;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_attach_dev {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tstruct dma_buf_attachment *attach;\n\tbool is_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_fd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence_unsignaled {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 phys_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tint full_nents;\n\tint full_ents;\n\tbool truncated;\n\tu32 __data_loc_phys_addrs;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tint err;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_single {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_addrs;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dql_stall_detected {\n\tstruct trace_entry ent;\n\tshort unsigned int thrs;\n\tunsigned int len;\n\tlong unsigned int last_reap;\n\tlong unsigned int hist_head;\n\tlong unsigned int now;\n\tlong unsigned int hist[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_error_report_template {\n\tstruct trace_entry ent;\n\tenum error_detector error_detector;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exit_mmap {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tstruct maple_tree *mt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_shrink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_to_scan;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__fallocate_mode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tint mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int flags;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int mflags;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mb_new_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 pa_pstart;\n\t__u64 pa_lstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mballoc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__trim {\n\tstruct trace_entry ent;\n\tint dev_major;\n\tint dev_minor;\n\t__u32 group;\n\tint start;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int copied;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_alloc_da_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int data_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_begin_ordered_truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_collapse_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_release_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint freed_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint reserve_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_update_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint used_blocks;\n\tint reserved_data_blocks;\n\tint quota_claim;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 lblk;\n\t__u32 len;\n\t__u32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 blk;\n\t__u64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_drop_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint drop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tconst char *function;\n\tunsigned int line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_insert_delayed_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tbool lclu_allocated;\n\tbool end_allocated;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tint found;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_remove_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t lblk;\n\tloff_t len;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tlong long unsigned int scan_time;\n\tint nr_skipped;\n\tint retried;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_evict_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_fastpath {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\text4_lblk_t i_lblk;\n\tunsigned int i_len;\n\text4_fsblk_t i_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_handle_unwritten_extents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tunsigned int allocated;\n\text4_fsblk_t newblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_load_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tshort unsigned int eh_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_idx {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_leaf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t ee_lblk;\n\text4_fsblk_t ee_pblk;\n\tshort int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_show_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tshort unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fallocate_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int blocks;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_cleanup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint j_fc_off;\n\tint full;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_stop {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nblks;\n\tint reason;\n\tint num_fc;\n\tint num_fc_ineligible;\n\tint nblks_agg;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint tag;\n\tint ino;\n\tint priv1;\n\tint priv2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint error;\n\tint off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int fc_ineligible_rc[13];\n\tlong unsigned int fc_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_numblks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_dentry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tlong int start;\n\tlong int end;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_forget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tint is_metadata;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tlong unsigned int count;\n\tint flags;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u64 blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu32 agno;\n\tu64 bno;\n\tu64 len;\n\tu64 owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_implied_cluster_alloc_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu64 block;\n\tu64 len;\n\tu64 owner;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_insert_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_invalidate_folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tsize_t offset;\n\tsize_t length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_inode {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_reserved {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_lazy_itable_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_load_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mark_inode_dirty {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint needed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_group_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 pa_pstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_inode_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\t__u32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 goal_logical;\n\tint goal_start;\n\t__u32 goal_group;\n\tint goal_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\t__u16 found;\n\t__u16 groups;\n\t__u16 buddy;\n\t__u16 flags;\n\t__u16 tail;\n\t__u8 cr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_prealloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tunsigned int orig_flags;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int m_len;\n\tu64 move_len;\n\tint move_type;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_nfs_commit_metadata {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_other_inode_update_time {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t orig_ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_prefetch_bitmaps {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\t__u32 next;\n\t__u32 ios;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_read_block_bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tbool prefetch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_remove_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\text4_fsblk_t ee_pblk;\n\text4_lblk_t ee_lblk;\n\tshort unsigned int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tint datasync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_update_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\text4_fsblk_t fsblk;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages_result {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tint pages_written;\n\tlong int pages_skipped;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fdb_delete {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib6_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu32 flowlabel;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[16];\n\t__u8 dst[16];\n\tu16 sport;\n\tu16 dport;\n\tu8 proto;\n\tu8 rt_type;\n\tchar name[16];\n\t__u8 gw[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tchar name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lease *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tlong unsigned int break_time;\n\tlong unsigned int downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int pid;\n\tunsigned int flags;\n\tunsigned char type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fill_mg_cmtime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\ttime64_t mtime_s;\n\tu32 ctime_ns;\n\tu32 mtime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_flush_foreign {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tunsigned int frn_bdi_id;\n\tunsigned int frn_memcg_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_free_vmap_area_noflush {\n\tstruct trace_entry ent;\n\tlong unsigned int va_start;\n\tlong unsigned int nr_lazy;\n\tlong unsigned int nr_lazy_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fsverity_enable {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tu64 data_size;\n\tu64 tree_size;\n\tunsigned int merkle_block;\n\tunsigned int num_levels;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fsverity_merkle_hit {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tu64 data_pos;\n\tlong unsigned int hblock_idx;\n\tunsigned int level;\n\tunsigned int hidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fsverity_tree_done {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tu64 data_size;\n\tu64 tree_size;\n\tunsigned int merkle_block;\n\tunsigned int levels;\n\tu32 __data_loc_root_hash;\n\tu32 __data_loc_file_digest;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fsverity_verify_data_block {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tu64 data_pos;\n\tunsigned int merkle_block;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fsverity_verify_merkle_block {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tlong unsigned int hblock_idx;\n\tunsigned int level;\n\tunsigned int hidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fuse_request_end {\n\tstruct trace_entry ent;\n\tdev_t connection;\n\tuint64_t unique;\n\tuint32_t len;\n\tint32_t error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fuse_request_send {\n\tstruct trace_entry ent;\n\tdev_t connection;\n\tuint64_t unique;\n\tenum fuse_opcode opcode;\n\tuint32_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_guest_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_alert_class {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int level;\n\tlong unsigned int description;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_complete {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint status;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_error_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint err;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_event_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_fd_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint fd;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_setup {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs__inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u16 mode;\n\tloff_t size;\n\tunsigned int nlink;\n\tunsigned int seals;\n\tblkcnt_t blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_alloc_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_fallocate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint mode;\n\tloff_t offset;\n\tloff_t len;\n\tloff_t size;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_setattr {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int d_len;\n\tu32 __data_loc_d_name;\n\tunsigned int ia_valid;\n\tunsigned int ia_mode;\n\tloff_t old_size;\n\tloff_t ia_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icmp_send {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint type;\n\tint code;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u16 sport;\n\t__u16 dport;\n\tshort unsigned int ulen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sk_error_report {\n\tstruct trace_entry ent;\n\tint error;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\ntypedef int (*initcall_t)(void);\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_foreign_history {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t cgroup_ino;\n\tunsigned int history;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs_queue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint res;\n\tunsigned int cflags;\n\tu64 extra1;\n\tu64 extra2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqe_overflow {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong long unsigned int user_data;\n\ts32 res;\n\tu32 cflags;\n\tvoid *ocqe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tu8 opcode;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tvoid *link;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_local_work_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint count;\n\tunsigned int loops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tint events;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tstruct io_wq_work *work;\n\tbool hashed;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_req_failed {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tu8 flags;\n\tu8 ioprio;\n\tu64 off;\n\tu64 addr;\n\tu32 len;\n\tu32 op_flags;\n\tu16 buf_index;\n\tu16 personality;\n\tu32 file_index;\n\tu64 pad1;\n\tu64 addr3;\n\tint error;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_short_write {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu64 fpos;\n\tu64 wanted;\n\tu64 got;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_req {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tbool sq_thread;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_work_run {\n\tstruct trace_entry ent;\n\tvoid *tctx;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocg_inuse_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu32 old_inuse;\n\tu32 new_inuse;\n\tu64 old_hweight_inuse;\n\tu64 new_hweight_inuse;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_ioc_vrate_adj {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu64 old_vrate;\n\tu64 new_vrate;\n\tint busy_level;\n\tu32 read_missed_ppm;\n\tu32 write_missed_ppm;\n\tu32 rq_wait_pct;\n\tint nr_lagging;\n\tint nr_shortages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_iocg_forgive_debt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu64 vnow;\n\tu32 usage_pct;\n\tu64 old_debt;\n\tu64 new_debt;\n\tu64 old_delay;\n\tu64 new_delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_iocg_state {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu64 vnow;\n\tu64 vrate;\n\tu64 last_period;\n\tu64 cur_period;\n\tu64 vtime;\n\tu32 weight;\n\tu32 inuse;\n\tu64 hweight_active;\n\tu64 hweight_inuse;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_add_to_ioend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 pos;\n\tu64 dirty_len;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tint ki_flags;\n\tbool aio;\n\tint error;\n\tssize_t ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_rw_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tsize_t count;\n\tsize_t done_before;\n\tint ki_flags;\n\tunsigned int dio_flags;\n\tbool aio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_iter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t pos;\n\tu64 length;\n\tint status;\n\tunsigned int flags;\n\tconst void *ops;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t size;\n\tloff_t offset;\n\tu64 length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpumask {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int chp_time;\n\t__u32 forced_to_close;\n\t__u32 written;\n\t__u32 dropped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_end_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\ttid_t head;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_extend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint buffer_credits;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_start_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint interval;\n\tint sync;\n\tint requested_blocks;\n\tint dirtied_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_journal_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_lock_buffer_stall {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int stall_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_run_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int wait;\n\tlong unsigned int request_delay;\n\tlong unsigned int running;\n\tlong unsigned int locked;\n\tlong unsigned int flushing;\n\tlong unsigned int logging;\n\t__u32 handle_count;\n\t__u32 blocks;\n\t__u32 blocks_logged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_checkpoint_list {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t first_tid;\n\ttid_t tid;\n\ttid_t last_tid;\n\tlong unsigned int nr_freed;\n\ttid_t next_tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_shrunk;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_submit_inode_data {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_update_log_tail {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tail_sequence;\n\ttid_t first_tid;\n\tlong unsigned int block_nr;\n\tlong unsigned int freed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_write_superblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tblk_opf_t write_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tvoid *rx_sk;\n\tshort unsigned int protocol;\n\tenum skb_drop_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmalloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tbool accounted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_advisor {\n\tstruct trace_entry ent;\n\ts64 scan_time;\n\tlong unsigned int pages_to_scan;\n\tunsigned int cpu_percent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_enter_exit_template {\n\tstruct trace_entry ent;\n\tvoid *mm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_merge_one_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_merge_with_ksm_page {\n\tstruct trace_entry ent;\n\tvoid *ksm_page;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_remove_ksm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_remove_rmap_item {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_scan_template {\n\tstruct trace_entry ent;\n\tint seq;\n\tu32 rmap_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_op {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_read {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_write {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tlong unsigned int piv;\n\tvoid *val;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tu32 __data_loc_comm;\n\tlong unsigned int total_vm;\n\tlong unsigned int anon_rss;\n\tlong unsigned int file_rss;\n\tlong unsigned int shmem_rss;\n\tuid_t uid;\n\tlong unsigned int pgtables;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct xdp_mem_allocator;\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_flush_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\ts64 stats_updates;\n\tbool force;\n\tbool needs_flush;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_events {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tlong unsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pmd {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pte {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_calculate_totalreserve_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int totalreserve_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tint isolated;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page_isolate {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint none_or_zero;\n\tint referenced;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page_swapin {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tint swapped_in;\n\tint referenced;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tunsigned char order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache_range {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int last_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_collapse_file {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int hpfn;\n\tlong unsigned int index;\n\tlong unsigned int addr;\n\tbool is_shmem;\n\tu32 __data_loc_filename;\n\tint nr;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_scan_file {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tu32 __data_loc_filename;\n\tint present;\n\tint swap;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_scan_pmd {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tint referenced;\n\tint none_or_zero;\n\tint status;\n\tint unmapped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tenum lru_list lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tlong unsigned int thp_succeeded;\n\tlong unsigned int thp_failed;\n\tlong unsigned int thp_split;\n\tlong unsigned int large_folio_split;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages_start {\n\tstruct trace_entry ent;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tint percpu_refill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tlong unsigned int gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_lowmem_reserve {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tu32 __data_loc_upper_name;\n\tlong int lowmem_reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_wmarks {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tlong unsigned int watermark_min;\n\tlong unsigned int watermark_low;\n\tlong unsigned int watermark_high;\n\tlong unsigned int watermark_promo;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tlong unsigned int gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_clear_hopeless {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_reclaim_fail {\n\tstruct trace_entry ent;\n\tint nid;\n\tint failures;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_reclaim_pages {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_throttled {\n\tstruct trace_entry ent;\n\tint nid;\n\tint usec_timeout;\n\tint usec_delayed;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_write_folio {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock_acquire_returned {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tbool success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mptcp_dump_mpext {\n\tstruct trace_entry ent;\n\tu64 data_ack;\n\tu64 data_seq;\n\tu32 subflow_seq;\n\tu16 data_len;\n\tu16 csum;\n\tu8 use_map;\n\tu8 dsn64;\n\tu8 data_fin;\n\tu8 use_ack;\n\tu8 ack64;\n\tu8 mpc_map;\n\tu8 frozen;\n\tu8 reset_transient;\n\tu8 reset_reason;\n\tu8 csum_reqd;\n\tu8 infinite_map;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mptcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mptcp_subflow_get_send {\n\tstruct trace_entry ent;\n\tbool active;\n\tbool free;\n\tu32 snd_wnd;\n\tu32 pace;\n\tu8 backup;\n\tu64 ratio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netlink_extack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_notifier_info {\n\tstruct trace_entry ent;\n\tvoid *cb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_op {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n\tlong unsigned int req_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_order {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_unbounded {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int nr_to_read;\n\tlong unsigned int lookahead_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\ts32 inflight;\n\tu32 hold;\n\tu32 release;\n\tu64 cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_hold {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 hold;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 release;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_update_nid {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tint pool_nid;\n\tint new_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pci_hp_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tu32 __data_loc_slot;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pcie_link_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tunsigned int type;\n\tunsigned int reason;\n\tunsigned int cur_bus_speed;\n\tunsigned int max_bus_speed;\n\tunsigned int width;\n\tunsigned int flit_mode;\n\tunsigned int link_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_purge_vmap_area_lazy {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int npurged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_enqueue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kvfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_segcb_stats {\n\tstruct trace_entry ent;\n\tconst char *ctx;\n\tlong unsigned int gp_seq[4];\n\tlong int seglen[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_sr_normal {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tconst char *srevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_stall_warning {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_watching {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint counter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\ts32 node_id;\n\ts32 mm_cid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_ap_nqapdqap_template {\n\tstruct trace_entry ent;\n\tu16 card;\n\tu16 dom;\n\tu32 status;\n\tu64 psmid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_cio_adapter_int {\n\tstruct trace_entry ent;\n\tstruct tpi_info tpi_info;\n\tu8 isc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_cio_chsc {\n\tstruct trace_entry ent;\n\tint cc;\n\tu16 code;\n\tu16 rcode;\n\tu8 request[64];\n\tu8 response[64];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_cio_interrupt {\n\tstruct trace_entry ent;\n\tstruct tpi_info tpi_info;\n\tu8 cssid;\n\tu8 ssid;\n\tu16 schno;\n\tu8 isc;\n\tu8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_cio_ssch {\n\tstruct trace_entry ent;\n\tu8 cssid;\n\tu8 ssid;\n\tu16 schno;\n\tunion orb orb;\n\tint cc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_cio_stcrw {\n\tstruct trace_entry ent;\n\tstruct crw crw;\n\tint cc;\n\tu8 slct;\n\tu8 oflw;\n\tu8 chn;\n\tu8 rsc;\n\tu8 anc;\n\tu8 erc;\n\tu16 rsid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_cio_tpi {\n\tstruct trace_entry ent;\n\tint cc;\n\tstruct tpi_info tpi_info;\n\tu8 cssid;\n\tu8 ssid;\n\tu16 schno;\n\tu8 adapter_IO;\n\tu8 isc;\n\tu8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_cio_tsch {\n\tstruct trace_entry ent;\n\tu8 cssid;\n\tu8 ssid;\n\tu16 schno;\n\tstruct irb irb;\n\tu8 scsw_dcc;\n\tu8 scsw_pno;\n\tu8 scsw_fctl;\n\tu8 scsw_actl;\n\tu8 scsw_stctl;\n\tu8 scsw_dstat;\n\tu8 scsw_cstat;\n\tint cc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_class_schib {\n\tstruct trace_entry ent;\n\tu8 cssid;\n\tu8 ssid;\n\tu16 schno;\n\tu16 devno;\n\tlong: 0;\n\tstruct schib schib;\n\tu8 pmcw_ena;\n\tu8 pmcw_st;\n\tu8 pmcw_dnv;\n\tu16 pmcw_dev;\n\tu8 pmcw_lpm;\n\tu8 pmcw_pnom;\n\tu8 pmcw_lpum;\n\tu8 pmcw_pim;\n\tu8 pmcw_pam;\n\tu8 pmcw_pom;\n\tu64 pmcw_chpid;\n\tint cc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_class_schid {\n\tstruct trace_entry ent;\n\tu8 cssid;\n\tu8 ssid;\n\tu16 schno;\n\tint cc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_diagnose {\n\tstruct trace_entry ent;\n\tshort unsigned int nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_hd_rebuild_domains {\n\tstruct trace_entry ent;\n\tint current_highcap_core_count;\n\tint new_highcap_core_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_s390_hd_work_fn {\n\tstruct trace_entry ent;\n\tint steal_time_percentage;\n\tint entitled_core_count;\n\tint highcap_core_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_bypass_lb {\n\tstruct trace_entry ent;\n\t__u32 node;\n\t__u32 nr_cpus;\n\t__u32 nr_tasks;\n\t__u32 nr_balanced;\n\t__u32 before_min;\n\t__u32 before_max;\n\t__u32 after_min;\n\t__u32 after_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_dump {\n\tstruct trace_entry ent;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\t__s64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *worker;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_move_numa {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_numa_pair_template {\n\tstruct trace_entry ent;\n\tpid_t src_pid;\n\tpid_t src_tgid;\n\tpid_t src_ngid;\n\tint src_cpu;\n\tint src_nid;\n\tpid_t dst_pid;\n\tpid_t dst_tgid;\n\tpid_t dst_ngid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_prepare_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_interp;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exit {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tbool group_dead;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tu32 __data_loc_parent_comm;\n\tpid_t parent_pid;\n\tu32 __data_loc_child_comm;\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_cpuset_numa {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tlong unsigned int mem_allowed[1];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_vma_numa {\n\tstruct trace_entry ent;\n\tlong unsigned int numa_scan_offset;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tenum numa_vmaskip_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 runtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_selinux_audited {\n\tstruct trace_entry ent;\n\tu32 requested;\n\tu32 denied;\n\tu32 audited;\n\tint result;\n\tu32 __data_loc_scontext;\n\tu32 __data_loc_tcontext;\n\tu32 __data_loc_tclass;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sk_data_ready {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 family;\n\t__u16 protocol;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int sysctl_mem[3];\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_msg_length {\n\tstruct trace_entry ent;\n\tvoid *sk;\n\t__u16 family;\n\t__u16 protocol;\n\tint ret;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_subflow_check_data_avail {\n\tstruct trace_entry ent;\n\tu8 status;\n\tconst void *skb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_swiotlb_bounced {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu64 dma_mask;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tbool force;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tu64 clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_prctl_unknown {\n\tstruct trace_entry ent;\n\tint option;\n\tlong unsigned int arg2;\n\tlong unsigned int arg3;\n\tlong unsigned int arg4;\n\tlong unsigned int arg5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tasklet {\n\tstruct trace_entry ent;\n\tvoid *tasklet;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_ao_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\t__u8 keyid;\n\t__u8 rnext;\n\t__u8 maclen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_cong_state_set {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u8 cong_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_hash_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\t__u64 sock_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_ssthresh;\n\t__u32 window_clamp;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_send_reset {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\tenum sk_rst_reason reason;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_sendmsg_locked {\n\tstruct trace_entry ent;\n\tconst void *skb_addr;\n\tint skb_len;\n\tint msg_left;\n\tint size_goal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_test_pages_isolated {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int fin_pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_base_idle {\n\tstruct trace_entry ent;\n\tbool is_idle;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int bucket_expiry;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tls_contenttype {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_child_parent {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_cpu_parent {\n\tstruct trace_entry ent;\n\tvoid *parent;\n\tunsigned int cpu;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_cpugroup {\n\tstruct trace_entry ent;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_and_cpu {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tu32 childmask;\n\tu8 active;\n\tu8 migrator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_set {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_handle_remote {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_idle {\n\tstruct trace_entry ent;\n\tu64 nextevt;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_update_events {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *group;\n\tu64 nextevt;\n\tu64 group_next_expiry;\n\tu64 child_evt_expiry;\n\tunsigned int group_lvl;\n\tunsigned int child_evtcpu;\n\tu8 child_active;\n\tu8 group_active;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_track_foreign_dirty {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tu64 bdi_id;\n\tino_t ino;\n\tunsigned int memcg_id;\n\tino_t cgroup_ino;\n\tino_t page_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_set_timeout {\n\tstruct trace_entry ent;\n\tint id;\n\tunsigned int timeout;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_template {\n\tstruct trace_entry ent;\n\tint id;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbt_lat {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int lat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbt_stat {\n\tstruct trace_entry ent;\n\tchar name[32];\n\ts64 rmean;\n\tu64 rmin;\n\tu64 rmax;\n\ts64 rnr_samples;\n\ts64 rtime;\n\ts64 wmean;\n\tu64 wmin;\n\tu64 wmax;\n\ts64 wnr_samples;\n\ts64 wtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbt_step {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tconst char *msg;\n\tint step;\n\tlong unsigned int window;\n\tunsigned int bg;\n\tunsigned int normal;\n\tunsigned int max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbt_timer {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tunsigned int status;\n\tint step;\n\tunsigned int inflight;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tu32 __data_loc_workqueue;\n\tint req_cpu;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_folio_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tunsigned int xdp_pass;\n\tunsigned int xdp_drop;\n\tunsigned int xdp_redirect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_inode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint resv;\n\txfs_extlen_t freeblks;\n\txfs_extlen_t flcount;\n\txfs_extlen_t reserved;\n\txfs_extlen_t asked;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_resv_init_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint error;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_agf_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint flags;\n\t__u32 length;\n\t__u32 bno_root;\n\t__u32 cnt_root;\n\t__u32 bno_level;\n\t__u32 cnt_level;\n\t__u32 flfirst;\n\t__u32 fllast;\n\t__u32 flcount;\n\t__u32 freeblks;\n\t__u32 longest;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ail_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tvoid *lip;\n\tuint type;\n\tlong unsigned int flags;\n\txfs_lsn_t old_lsn;\n\txfs_lsn_t new_lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_alloc_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t minlen;\n\txfs_extlen_t maxlen;\n\txfs_extlen_t mod;\n\txfs_extlen_t prod;\n\txfs_extlen_t minleft;\n\txfs_extlen_t total;\n\txfs_extlen_t alignment;\n\txfs_extlen_t minalignslop;\n\txfs_extlen_t len;\n\tchar wasdel;\n\tchar wasfromfl;\n\tint resv;\n\tint datatype;\n\txfs_agnumber_t highest_agno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_alloc_cur_check {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\txfs_agblock_t bno;\n\txfs_extlen_t len;\n\txfs_extlen_t diff;\n\tbool new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_attr_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\tint namelen;\n\tint valuelen;\n\txfs_dahash_t hashval;\n\tunsigned int attr_filter;\n\tuint32_t op_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_attr_list_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 hashval;\n\tu32 blkno;\n\tu32 offset;\n\tvoid *buffer;\n\tint bufsize;\n\tint count;\n\tint firstu;\n\tint dupcnt;\n\tunsigned int attr_filter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_attr_list_node_descend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 hashval;\n\tu32 blkno;\n\tu32 offset;\n\tvoid *buffer;\n\tint bufsize;\n\tint count;\n\tint firstu;\n\tint dupcnt;\n\tunsigned int attr_filter;\n\tu32 bt_hashval;\n\tu32 bt_before;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_bmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tvoid *leaf;\n\tint pos;\n\txfs_fileoff_t startoff;\n\txfs_fsblock_t startblock;\n\txfs_filblks_t blockcount;\n\txfs_exntst_t state;\n\tint bmap_state;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_bmap_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tlong long unsigned int gbno;\n\tint whichfork;\n\txfs_fileoff_t l_loff;\n\txfs_filblks_t l_len;\n\txfs_exntst_t l_state;\n\tint op;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_alloc_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\tint error;\n\txfs_agblock_t agbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_bload_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tunsigned int level;\n\tlong long unsigned int block_idx;\n\tlong long unsigned int nr_blocks;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tunsigned int nr_records;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_bload_level_geometry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tunsigned int level;\n\tunsigned int nlevels;\n\tuint64_t nr_this_level;\n\tunsigned int nr_per_block;\n\tunsigned int desired_npb;\n\tlong long unsigned int blocks;\n\tlong long unsigned int blocks_with_extra;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_commit_afakeroot {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tunsigned int levels;\n\tunsigned int blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_commit_ifakeroot {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tunsigned int levels;\n\tunsigned int blocks;\n\tint whichfork;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_cur_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tint level;\n\tint nlevels;\n\tint ptr;\n\txfs_daddr_t daddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tint error;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_free_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\txfs_agblock_t agbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_buf_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t bno;\n\tint nblks;\n\tint hold;\n\tint pincount;\n\tunsigned int lockval;\n\tunsigned int flags;\n\tlong unsigned int caller_ip;\n\tconst void *buf_ops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_buf_flags_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t bno;\n\tunsigned int length;\n\tint hold;\n\tint pincount;\n\tunsigned int lockval;\n\tunsigned int flags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\ntypedef void *xfs_failaddr_t;\n\nstruct trace_event_raw_xfs_buf_ioerror {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t bno;\n\tunsigned int length;\n\tunsigned int flags;\n\tint hold;\n\tint pincount;\n\tunsigned int lockval;\n\tint error;\n\txfs_failaddr_t caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_buf_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t buf_bno;\n\tunsigned int buf_len;\n\tint buf_hold;\n\tint buf_pincount;\n\tint buf_lockval;\n\tunsigned int buf_flags;\n\tunsigned int bli_recur;\n\tint bli_refcount;\n\tunsigned int bli_flags;\n\tlong unsigned int li_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_bunmap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsize_t size;\n\txfs_fileoff_t fileoff;\n\txfs_filblks_t len;\n\tlong unsigned int caller_ip;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_calc_atomic_write_unit_max {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\tunsigned int max_write;\n\tunsigned int max_ioend;\n\tunsigned int max_gsize;\n\tunsigned int awu_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_calc_max_atomic_write_fsblocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int per_intent;\n\tunsigned int step_size;\n\tunsigned int logres;\n\tunsigned int blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_calc_max_atomic_write_log_geometry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int per_intent;\n\tunsigned int step_size;\n\tunsigned int blockcount;\n\tunsigned int min_logblocks;\n\tunsigned int cur_logblocks;\n\tunsigned int logres;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_check_new_dalign {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint new_dalign;\n\txfs_ino_t sb_rootino;\n\txfs_ino_t calc_rootino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_da_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\tint namelen;\n\txfs_dahash_t hashval;\n\txfs_ino_t inumber;\n\tuint32_t op_flags;\n\txfs_ino_t owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_das_state_class {\n\tstruct trace_entry ent;\n\tint das;\n\txfs_ino_t ino;\n\tchar __data[0];\n};\n\nstruct xfs_trans;\n\nstruct trace_event_raw_xfs_defer_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tstruct xfs_trans *tp;\n\tchar committed;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_defer_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tstruct xfs_trans *tp;\n\tchar committed;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_defer_pending_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tvoid *intent;\n\tunsigned int flags;\n\tchar committed;\n\tint nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_defer_pending_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tvoid *intent;\n\tvoid *item;\n\tchar committed;\n\tunsigned int flags;\n\tint nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dir2_leafn_moveents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tuint32_t op_flags;\n\tint src_idx;\n\tint dst_idx;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dir2_space_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tuint32_t op_flags;\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_discard_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_double_io_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t src_ino;\n\tloff_t src_isize;\n\tloff_t src_disize;\n\tloff_t src_offset;\n\tlong long int len;\n\txfs_ino_t dest_ino;\n\tloff_t dest_isize;\n\tloff_t dest_disize;\n\tloff_t dest_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dqtrx_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_dqtype_t type;\n\tunsigned int flags;\n\tu32 dqid;\n\tuint64_t blk_res;\n\tint64_t bcount_delta;\n\tint64_t delbcnt_delta;\n\tuint64_t rtblk_res;\n\tuint64_t rtblk_res_used;\n\tint64_t rtbcount_delta;\n\tint64_t delrtb_delta;\n\tuint64_t ino_res;\n\tuint64_t ino_res_used;\n\tint64_t icount_delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dquot_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 id;\n\txfs_dqtype_t type;\n\tunsigned int flags;\n\tunsigned int nrefs;\n\tlong long unsigned int res_bcount;\n\tlong long unsigned int res_rtbcount;\n\tlong long unsigned int res_icount;\n\tlong long unsigned int bcount;\n\tlong long unsigned int rtbcount;\n\tlong long unsigned int icount;\n\tlong long unsigned int blk_hardlimit;\n\tlong long unsigned int blk_softlimit;\n\tlong long unsigned int rtb_hardlimit;\n\tlong long unsigned int rtb_softlimit;\n\tlong long unsigned int ino_hardlimit;\n\tlong long unsigned int ino_softlimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_delta_nextents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino1;\n\txfs_ino_t ino2;\n\txfs_extnum_t nexts1;\n\txfs_extnum_t nexts2;\n\tint64_t d_nexts1;\n\tint64_t d_nexts2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_delta_nextents_step {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_fileoff_t loff;\n\txfs_fsblock_t lstart;\n\txfs_filblks_t lcount;\n\txfs_fileoff_t coff;\n\txfs_fsblock_t cstart;\n\txfs_filblks_t ccount;\n\txfs_fileoff_t noff;\n\txfs_fsblock_t nstart;\n\txfs_filblks_t ncount;\n\txfs_fileoff_t roff;\n\txfs_fsblock_t rstart;\n\txfs_filblks_t rcount;\n\tint delta;\n\tunsigned int state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_estimate_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino1;\n\txfs_ino_t ino2;\n\txfs_fileoff_t startoff1;\n\txfs_fileoff_t startoff2;\n\txfs_filblks_t blockcount;\n\tuint64_t flags;\n\txfs_filblks_t ip1_bcount;\n\txfs_filblks_t ip2_bcount;\n\txfs_filblks_t ip1_rtbcount;\n\txfs_filblks_t ip2_rtbcount;\n\tlong long unsigned int resblks;\n\tlong long unsigned int nr_exchanges;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_intent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino1;\n\txfs_ino_t ino2;\n\tuint64_t flags;\n\txfs_fileoff_t startoff1;\n\txfs_fileoff_t startoff2;\n\txfs_filblks_t blockcount;\n\txfs_fsize_t isize1;\n\txfs_fsize_t isize2;\n\txfs_fsize_t new_isize1;\n\txfs_fsize_t new_isize2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_overhead {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int bmbt_blocks;\n\tlong long unsigned int rmapbt_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchrange_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ip1_ino;\n\tloff_t ip1_isize;\n\tloff_t ip1_disize;\n\txfs_ino_t ip2_ino;\n\tloff_t ip2_isize;\n\tloff_t ip2_disize;\n\tloff_t file1_offset;\n\tloff_t file2_offset;\n\tlong long unsigned int length;\n\tlong long unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchrange_freshness {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ip2_ino;\n\tlong long int ip2_mtime;\n\tlong long int ip2_ctime;\n\tint ip2_mtime_nsec;\n\tint ip2_ctime_nsec;\n\txfs_ino_t file2_ino;\n\tlong long int file2_mtime;\n\tlong long int file2_ctime;\n\tint file2_mtime_nsec;\n\tint file2_ctime_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchrange_inode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint whichfile;\n\txfs_ino_t ino;\n\tint format;\n\txfs_extnum_t nex;\n\tint broot_size;\n\tint fork_off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_extent_busy_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_extent_busy_trim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\txfs_agblock_t tbno;\n\txfs_extlen_t tlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fault_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_file_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsize_t size;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_filestream_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_agnumber_t agno;\n\tint streams;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_filestream_pick {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_agnumber_t agno;\n\tint streams;\n\txfs_extlen_t free;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_force_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint ptag;\n\tint flags;\n\tu32 __data_loc_fname;\n\tint line_num;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_free_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tint resv;\n\tint haveleft;\n\tint haveright;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_free_extent_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_freeblocks_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_free_counter ctr;\n\tuint64_t delta;\n\tuint64_t avail;\n\tuint64_t total;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fs_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int mflags;\n\tlong unsigned int opstate;\n\tlong unsigned int sbflags;\n\tvoid *caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fs_corrupt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fsmap_group_key_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fsmap_linear_key_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_fsblock_t bno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fsmap_mapping {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t len_daddr;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_daddr_t block;\n\txfs_daddr_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tuint64_t flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_getparents_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tshort unsigned int iflags;\n\tshort unsigned int oflags;\n\tunsigned int bufsize;\n\tunsigned int hashval;\n\tunsigned int blkno;\n\tunsigned int offset;\n\tint initted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_getparents_rec_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int firstu;\n\tshort unsigned int reclen;\n\tunsigned int bufsize;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_group_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tint refcount;\n\tint active_refcount;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_group_corrupt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\tuint32_t index;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_growfs_check_rtgeom {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int logblocks;\n\tunsigned int min_logfsbs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int events;\n\tlong long unsigned int lost_prev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_copybuf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsize_t bufsize;\n\tsize_t inpos;\n\tsize_t outpos;\n\tsize_t to_copy;\n\tsize_t iter_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_create {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 flags;\n\tu8 format;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_event_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int mask;\n\tlong long unsigned int ino;\n\tunsigned int gen;\n\tunsigned int group;\n\tlong long unsigned int offset;\n\tlong long unsigned int length;\n\tlong long unsigned int lostcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_lost_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int lost_prev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_file_ioerror {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tlong long unsigned int ino;\n\tunsigned int gen;\n\tlong long int pos;\n\tlong long unsigned int len;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int old_mask;\n\tunsigned int new_mask;\n\tunsigned int fsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_group {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int old_mask;\n\tunsigned int new_mask;\n\tunsigned int grpmask;\n\tunsigned int group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int old_mask;\n\tunsigned int new_mask;\n\tunsigned int imask;\n\tlong long unsigned int ino;\n\tunsigned int gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_media {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int error_dev;\n\tuint64_t daddr;\n\tuint64_t bbcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint32_t shutdown_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_icwalk_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 flags;\n\tuint32_t uid;\n\tuint32_t gid;\n\tprid_t prid;\n\t__u64 min_file_size;\n\tlong int scan_limit;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_imap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tloff_t size;\n\tloff_t offset;\n\tsize_t count;\n\tint whichfork;\n\txfs_fileoff_t startoff;\n\txfs_fsblock_t startblock;\n\txfs_filblks_t blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tlong unsigned int iflags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_corrupt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint error;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_irec_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fileoff_t lblk;\n\txfs_extlen_t len;\n\txfs_fsblock_t pblk;\n\tint state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_reload_unlinked_bucket {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inodegc_shrinker_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tvoid *caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inodegc_worker {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int shrinker_hits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iomap_atomic_write_cow {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_off_t offset;\n\tssize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iomap_invalid_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu64 addr;\n\tloff_t pos;\n\tu64 len;\n\tu64 validity_cookie;\n\tu64 inodeseq;\n\tu16 type;\n\tu16 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iomap_prealloc_size {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsblock_t blocks;\n\tint shift;\n\tunsigned int writeio_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_irec_merge_post {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tuint16_t holemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_irec_merge_pre {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tuint16_t holemask;\n\txfs_agino_t nagino;\n\tuint16_t nholemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iref_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint count;\n\tint pincount;\n\tlong unsigned int iflags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_itrunc_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsize_t size;\n\txfs_fsize_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iunlink_reload_next {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\txfs_agino_t prev_agino;\n\txfs_agino_t next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iunlink_update_bucket {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tunsigned int bucket;\n\txfs_agino_t old_ptr;\n\txfs_agino_t new_ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iunlink_update_dinode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\txfs_agino_t old_ptr;\n\txfs_agino_t new_ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iwalk_ag_rec {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t startino;\n\tuint64_t freemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_lock_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint lock_flags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_assign_tail_lsn {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_lsn_t new_lsn;\n\txfs_lsn_t old_lsn;\n\txfs_lsn_t head_lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_force {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_lsn_t lsn;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_get_max_trans_res {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint logres;\n\tint logcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tvoid *lip;\n\tuint type;\n\tlong unsigned int flags;\n\txfs_lsn_t lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t headblk;\n\txfs_daddr_t tailblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_buf_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint64_t blkno;\n\tshort unsigned int len;\n\tshort unsigned int flags;\n\tshort unsigned int size;\n\tunsigned int map_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_icreate_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tunsigned int count;\n\tunsigned int isize;\n\txfs_agblock_t length;\n\tunsigned int gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_ino_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tshort unsigned int size;\n\tint fields;\n\tshort unsigned int asize;\n\tshort unsigned int dsize;\n\tint64_t blkno;\n\tint len;\n\tint boffset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int item;\n\txlog_tid_t tid;\n\txfs_lsn_t lsn;\n\tint type;\n\tint pass;\n\tint count;\n\tint total;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_record {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_lsn_t lsn;\n\tint len;\n\tint num_logops;\n\tint pass;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_loggrant_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int tic;\n\tchar ocnt;\n\tchar cnt;\n\tint curr_res;\n\tint unit_res;\n\tunsigned int flags;\n\tint reserveq;\n\tint writeq;\n\tuint64_t grant_reserve_bytes;\n\tuint64_t grant_write_bytes;\n\tuint64_t tail_space;\n\tint curr_cycle;\n\tint curr_block;\n\txfs_lsn_t tail_lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metadir_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\txfs_ino_t ino;\n\tint ftype;\n\tint namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metadir_update_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\txfs_ino_t ino;\n\tu32 __data_loc_fname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metadir_update_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\txfs_ino_t ino;\n\tint error;\n\tu32 __data_loc_fname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metafile_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int freeblks;\n\tlong long unsigned int reserved;\n\tlong long unsigned int asked;\n\tlong long unsigned int used;\n\tlong long unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_namespace_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\tint namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_perag_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint refcount;\n\tint active_refcount;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_pwork_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int nr_threads;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tint op;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_double_extent_at_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain i1_domain;\n\txfs_agblock_t i1_startblock;\n\txfs_extlen_t i1_blockcount;\n\txfs_nlink_t i1_refcount;\n\tenum xfs_refc_domain i2_domain;\n\txfs_agblock_t i2_startblock;\n\txfs_extlen_t i2_blockcount;\n\txfs_nlink_t i2_refcount;\n\txfs_agblock_t gbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_double_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain i1_domain;\n\txfs_agblock_t i1_startblock;\n\txfs_extlen_t i1_blockcount;\n\txfs_nlink_t i1_refcount;\n\tenum xfs_refc_domain i2_domain;\n\txfs_agblock_t i2_startblock;\n\txfs_extlen_t i2_blockcount;\n\txfs_nlink_t i2_refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_extent_at_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain domain;\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\txfs_nlink_t refcount;\n\txfs_agblock_t gbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain domain;\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\txfs_nlink_t refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_lookup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_lookup_t dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_triple_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain i1_domain;\n\txfs_agblock_t i1_startblock;\n\txfs_extlen_t i1_blockcount;\n\txfs_nlink_t i1_refcount;\n\tenum xfs_refc_domain i2_domain;\n\txfs_agblock_t i2_startblock;\n\txfs_extlen_t i2_blockcount;\n\txfs_nlink_t i2_refcount;\n\tenum xfs_refc_domain i3_domain;\n\txfs_agblock_t i3_startblock;\n\txfs_extlen_t i3_blockcount;\n\txfs_nlink_t i3_refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_reflink_remap_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t src_ino;\n\txfs_fileoff_t src_lblk;\n\txfs_filblks_t len;\n\txfs_ino_t dest_ino;\n\txfs_fileoff_t dest_lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t src_dp_ino;\n\txfs_ino_t target_dp_ino;\n\tint src_namelen;\n\tint target_namelen;\n\tu32 __data_loc_src_name;\n\tu32 __data_loc_target_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmap_convert_state {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tint state;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmap_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int owner;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\tint whichfork;\n\txfs_fileoff_t l_loff;\n\txfs_filblks_t l_len;\n\txfs_exntst_t l_state;\n\tint op;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmapbt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rtalloc_extent_busy {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rgnumber_t rgno;\n\txfs_rtxnum_t start;\n\txfs_rtxlen_t minlen;\n\txfs_rtxlen_t maxlen;\n\txfs_rtxlen_t mod;\n\txfs_rtxlen_t prod;\n\txfs_rtxlen_t len;\n\txfs_rtxnum_t rtx;\n\tunsigned int busy_gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rtalloc_extent_busy_trim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rgnumber_t rgno;\n\txfs_rtxnum_t old_rtx;\n\txfs_rtxnum_t new_rtx;\n\txfs_rtxlen_t old_len;\n\txfs_rtxlen_t new_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rtdiscard_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rtblock_t rtbno;\n\txfs_rtblock_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_simple_io_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tloff_t isize;\n\tloff_t disize;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_swap_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint which;\n\txfs_ino_t ino;\n\tint format;\n\txfs_extnum_t nex;\n\tint broot_size;\n\tint fork_off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_timestamp_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long int min;\n\tlong long int max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_trans_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint32_t tid;\n\tuint32_t flags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_trans_mod_dquot {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_dqtype_t type;\n\tunsigned int flags;\n\tunsigned int dqid;\n\tunsigned int field;\n\tint64_t delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_trans_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint type;\n\tuint logres;\n\tint logcount;\n\tint logflags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_verify_media {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t fdev;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t end_daddr;\n\tunsigned int flags;\n\txfs_daddr_t daddr;\n\tuint64_t bbcount;\n\tunsigned int bufsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_verify_media_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t fdev;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t end_daddr;\n\tint ioerror;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_verify_media_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t fdev;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t end_daddr;\n\tunsigned int flags;\n\txfs_daddr_t daddr;\n\tuint64_t bbcount;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_wb_invalid_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu64 addr;\n\tloff_t pos;\n\tu64 len;\n\tu16 type;\n\tu16 flags;\n\tu32 wpcseq;\n\tu32 forkseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_zone_alloc_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rgnumber_t rgno;\n\txfs_rgblock_t used;\n\txfs_rgblock_t allocated;\n\txfs_rgblock_t written;\n\txfs_rgblock_t rgbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_zone_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rgnumber_t rgno;\n\txfs_rgblock_t used;\n\tunsigned int nr_open;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_zone_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rgnumber_t rgno;\n\txfs_rgblock_t used;\n\txfs_rgblock_t rgbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_zone_gc_select_victim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rgnumber_t rgno;\n\txfs_rgblock_t used;\n\tunsigned int bucket;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_zones_mount {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rgnumber_t rgcount;\n\tuint32_t blocks;\n\tunsigned int max_open_zones;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xlog_iclog_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint32_t state;\n\tint32_t refcount;\n\tuint32_t offset;\n\tuint32_t flags;\n\tlong long unsigned int lsn;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xlog_intent_recovery_failed {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n\tint flags;\n};\n\nstruct tracepoint_user;\n\nstruct trace_fprobe {\n\tstruct dyn_event devent;\n\tstruct fprobe fp;\n\tconst char *symbol;\n\tbool tprobe;\n\tstruct tracepoint_user *tuser;\n\tstruct trace_probe tp;\n};\n\nstruct trace_func_repeats {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int count;\n\tu64 ts_last_call;\n};\n\nstruct trace_kprobe {\n\tstruct dyn_event devent;\n\tstruct kretprobe rp;\n\tlong unsigned int *nhit;\n\tconst char *symbol;\n\tstruct trace_probe tp;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n};\n\nstruct trace_min_max_param {\n\tstruct mutex *lock;\n\tu64 *val;\n\tu64 *min;\n\tu64 *max;\n};\n\nstruct trace_mod_entry {\n\tlong unsigned int mod_addr;\n\tchar mod_name[56];\n};\n\nstruct trace_module_delta {\n\tstruct callback_head rcu;\n\tlong int delta[0];\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nunion upper_chunk;\n\nstruct trace_pid_list {\n\tseqcount_raw_spinlock_t seqcount;\n\traw_spinlock_t lock;\n\tstruct irq_work refill_irqwork;\n\tunion upper_chunk *upper[256];\n\tunion upper_chunk *upper_list;\n\tunion lower_chunk *lower_list;\n\tint free_upper_chunks;\n\tint free_lower_chunks;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nstruct trace_scratch {\n\tunsigned int clock_id;\n\tlong unsigned int text_addr;\n\tlong unsigned int nr_entries;\n\tstruct trace_mod_entry entries[0];\n};\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct eventfs_inode *ei;\n\tint ref_count;\n\tint nr_events;\n};\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tchar *filename;\n\tstruct uprobe *uprobe;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int *nhits;\n\tstruct trace_probe tp;\n};\n\nstruct trace_user_buf {\n\tchar *buf;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct tracefs_inode {\n\tstruct inode vfs_inode;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tvoid *private;\n};\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct tracepoint_user {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct tracepoint *tpoint;\n\tunsigned int refcount;\n};\n\nstruct traceprobe_parse_context {\n\tstruct trace_event_call *event;\n\tconst char *funcname;\n\tconst struct btf_type *proto;\n\tconst struct btf_param *params;\n\ts32 nr_params;\n\tstruct btf *btf;\n\tconst struct btf_type *last_type;\n\tu32 last_bitoffs;\n\tu32 last_bitsize;\n\tstruct trace_probe *tp;\n\tunsigned int flags;\n\tint offset;\n};\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u64, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tstruct tracer_flags *default_flags;\n\tint enabled;\n\tbool print_max;\n\tbool allow_instances;\n\tbool use_max_tr;\n\tbool noboot;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\nstruct tracers {\n\tstruct list_head list;\n\tstruct tracer *tracer;\n\tstruct tracer_flags *flags;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar *cmd;\n};\n\ntypedef int (*tracing_map_cmp_fn_t)(void *, void *);\n\nstruct tracing_map_field {\n\ttracing_map_cmp_fn_t cmp_fn;\n\tunion {\n\t\tatomic64_t sum;\n\t\tunsigned int offset;\n\t};\n};\n\nstruct tracing_map_array;\n\nstruct tracing_map_ops;\n\nstruct tracing_map {\n\tunsigned int key_size;\n\tunsigned int map_bits;\n\tunsigned int map_size;\n\tunsigned int max_elts;\n\tatomic_t next_elt;\n\tstruct tracing_map_array *elts;\n\tstruct tracing_map_array *map;\n\tconst struct tracing_map_ops *ops;\n\tvoid *private_data;\n\tstruct tracing_map_field fields[6];\n\tunsigned int n_fields;\n\tint key_idx[3];\n\tunsigned int n_keys;\n\tstruct tracing_map_sort_key sort_key;\n\tunsigned int n_vars;\n\tatomic64_t hits;\n\tatomic64_t drops;\n};\n\nstruct tracing_map_array {\n\tunsigned int entries_per_page;\n\tunsigned int entry_size_shift;\n\tunsigned int entry_shift;\n\tunsigned int entry_mask;\n\tunsigned int n_pages;\n\tvoid **pages;\n};\n\nstruct tracing_map_elt {\n\tstruct tracing_map *map;\n\tstruct tracing_map_field *fields;\n\tatomic64_t *vars;\n\tbool *var_set;\n\tvoid *key;\n\tvoid *private_data;\n};\n\nstruct tracing_map_entry {\n\tu32 key;\n\tstruct tracing_map_elt *val;\n};\n\nstruct tracing_map_ops {\n\tint (*elt_alloc)(struct tracing_map_elt *);\n\tvoid (*elt_free)(struct tracing_map_elt *);\n\tvoid (*elt_clear)(struct tracing_map_elt *);\n\tvoid (*elt_init)(struct tracing_map_elt *);\n};\n\nstruct tracing_map_sort_entry {\n\tvoid *key;\n\tstruct tracing_map_elt *elt;\n\tbool elt_copied;\n\tbool dup;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tdepot_stack_handle_t handle;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct track_data {\n\tu64 track_val;\n\tbool updated;\n\tunsigned int key_len;\n\tvoid *key;\n\tstruct tracing_map_elt elt;\n\tstruct action_data *action_data;\n\tstruct hist_trigger_data *hist_data;\n};\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n};\n\nstruct tree_block {\n\tunion {\n\t\tstruct {\n\t\t\tstruct rb_node rb_node;\n\t\t\tu64 bytenr;\n\t\t};\n\t\tstruct rb_simple_node simple_node;\n\t};\n\tu64 owner;\n\tstruct btrfs_key key;\n\tu8 level;\n\tbool key_ready;\n};\n\ntypedef struct tree_desc_s tree_desc;\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct tree_mod_root {\n\tu64 logical;\n\tu8 level;\n};\n\nstruct tree_mod_elem {\n\tstruct rb_node node;\n\tu64 logical;\n\tu64 seq;\n\tenum btrfs_mod_log_op op;\n\tint slot;\n\tu64 generation;\n\tunion {\n\t\tstruct {\n\t\t\tstruct btrfs_disk_key key;\n\t\t\tu64 blockptr;\n\t\t} slot_change;\n\t\tstruct {\n\t\t\tint dst_slot;\n\t\t\tint nr_items;\n\t\t} move;\n\t\tstruct tree_mod_root old_root;\n\t};\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_linear_state {\n\tunsigned int len;\n\tconst void *data;\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsa_ddpc {\n\tint: 24;\n\tu32 rc: 8;\n\tu8 rcq[16];\n\tu8 sense[32];\n};\n\nstruct tsa_intrg {\n\tu32 format: 8;\n\tu32 flags: 8;\n\tu32 cu_state: 8;\n\tu32 dev_state: 8;\n\tu32 op_state: 8;\n\tlong: 0;\n\tu8 sd_info[12];\n\tu32 dl_id;\n\tu8 dd_data[28];\n};\n\nstruct tsa_iostat {\n\tu32 dev_time;\n\tu32 def_time;\n\tu32 queue_time;\n\tu32 dev_busy_time;\n\tu32 dev_act_time;\n\tu8 sense[32];\n};\n\nstruct tsb {\n\tu32 length: 8;\n\tu32 flags: 8;\n\tu32 dcw_offset: 16;\n\tu32 count;\n\tint: 32;\n\tunion {\n\t\tstruct tsa_iostat iostat;\n\t\tstruct tsa_ddpc ddpc;\n\t\tstruct tsa_intrg intrg;\n\t} tsa;\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct tsync_shared_context {\n\tconst struct cred *old_cred;\n\tconst struct cred *new_cred;\n\tbool set_no_new_privs;\n\tatomic_t preparation_error;\n\tatomic_t num_preparing;\n\tstruct completion all_prepared;\n\tstruct completion ready_to_commit;\n\tatomic_t num_unfinished;\n\tstruct completion all_finished;\n};\n\nstruct tsync_work {\n\tstruct callback_head work;\n\tstruct task_struct *task;\n\tstruct tsync_shared_context *shared_ctx;\n};\n\nstruct tsync_works {\n\tstruct tsync_work **works;\n\tsize_t size;\n\tsize_t capacity;\n};\n\nstruct tty3270_attribute {\n\tunsigned char alternate_charset: 1;\n\tunsigned char highlight: 3;\n\tunsigned char f_color: 4;\n\tunsigned char b_color: 4;\n};\n\nstruct tty3270_line;\n\nstruct tty3270 {\n\tstruct raw3270_view view;\n\tstruct tty_port port;\n\tunsigned char wcc;\n\tint nr_up;\n\tlong unsigned int update_flags;\n\tstruct raw3270_request *write;\n\tstruct timer_list timer;\n\tchar *converted_line;\n\tunsigned int line_view_start;\n\tunsigned int line_write_start;\n\tunsigned int oops_line;\n\tunsigned int cx;\n\tunsigned int cy;\n\tstruct tty3270_attribute attributes;\n\tstruct tty3270_attribute saved_attributes;\n\tint allocated_lines;\n\tstruct tty3270_line *screen;\n\tchar *prompt;\n\tsize_t prompt_sz;\n\tchar *input;\n\tstruct raw3270_request *read;\n\tstruct raw3270_request *kreset;\n\tstruct raw3270_request *readpartreq;\n\tunsigned char inattr;\n\tint throttle;\n\tint attn;\n\tstruct tasklet_struct readlet;\n\tstruct tasklet_struct hanglet;\n\tstruct kbd_data *kbd;\n\tint esc_state;\n\tint esc_ques;\n\tint esc_npar;\n\tint esc_par[8];\n\tunsigned int saved_cx;\n\tunsigned int saved_cy;\n\tchar **rcl_lines;\n\tint rcl_write_index;\n\tint rcl_read_index;\n\tunsigned int char_count;\n\tu8 char_buf[256];\n};\n\nstruct tty3270_cell {\n\tu8 character;\n\tstruct tty3270_attribute attributes;\n};\n\nstruct tty3270_line {\n\tstruct tty3270_cell *cells;\n\tint len;\n\tint dirty;\n};\n\nstruct tty_audit_buf {\n\tstruct mutex mutex;\n\tdev_t dev;\n\tbool icanon;\n\tsize_t valid;\n\tu8 *data;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct tun_security_struct {\n\tu32 sid;\n};\n\nstruct type_datum {\n\tu32 value;\n\tu32 bounds;\n\tunsigned char primary;\n\tunsigned char attribute;\n};\n\nstruct type_set {\n\tstruct ebitmap types;\n\tstruct ebitmap negset;\n\tu32 flags;\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\t_sigregs uc_mcontext;\n\tsigset_t uc_sigmask;\n\tunsigned char __unused[120];\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[12];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n\tu16 len;\n\tbool is_linear;\n\tbool csum_unnecessary;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 64;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\ntypedef struct sk_buff * (*udp_tunnel_gro_rcv_t)(struct sock *, struct list_head *, struct sk_buff *);\n\nstruct udp_tunnel_type_entry {\n\tudp_tunnel_gro_rcv_t gro_receive;\n\trefcount_t count;\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct uffd_msg {\n\t__u8 event;\n\t__u8 reserved1;\n\t__u16 reserved2;\n\t__u32 reserved3;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 address;\n\t\t\tunion {\n\t\t\t\t__u32 ptid;\n\t\t\t} feat;\n\t\t} pagefault;\n\t\tstruct {\n\t\t\t__u32 ufd;\n\t\t} fork;\n\t\tstruct {\n\t\t\t__u64 from;\n\t\t\t__u64 to;\n\t\t\t__u64 len;\n\t\t} remap;\n\t\tstruct {\n\t\t\t__u64 start;\n\t\t\t__u64 end;\n\t\t} remove;\n\t\tstruct {\n\t\t\t__u64 reserved1;\n\t\t\t__u64 reserved2;\n\t\t\t__u64 reserved3;\n\t\t} reserved;\n\t} arg;\n};\n\nstruct uffdio_api {\n\t__u64 api;\n\t__u64 features;\n\t__u64 ioctls;\n};\n\nstruct uffdio_range {\n\t__u64 start;\n\t__u64 len;\n};\n\nstruct uffdio_continue {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__s64 mapped;\n};\n\nstruct uffdio_copy {\n\t__u64 dst;\n\t__u64 src;\n\t__u64 len;\n\t__u64 mode;\n\t__s64 copy;\n};\n\nstruct uffdio_move {\n\t__u64 dst;\n\t__u64 src;\n\t__u64 len;\n\t__u64 mode;\n\t__s64 move;\n};\n\nstruct uffdio_poison {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__s64 updated;\n};\n\nstruct uffdio_register {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__u64 ioctls;\n};\n\nstruct uffdio_writeprotect {\n\tstruct uffdio_range range;\n\t__u64 mode;\n};\n\nstruct uffdio_zeropage {\n\tstruct uffdio_range range;\n\t__u64 mode;\n\t__s64 zeropage;\n};\n\nstruct ulist_iterator {\n\tstruct list_head *cur_list;\n};\n\nstruct ulist_node {\n\tu64 val;\n\tu64 aux;\n\tstruct list_head list;\n\tstruct rb_node rb_node;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct uncharge_gather {\n\tstruct mem_cgroup *memcg;\n\tlong unsigned int nr_memory;\n\tlong unsigned int pgpgout;\n\tlong unsigned int nr_kmem;\n\tint nid;\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct utf8data;\n\nstruct utf8data_table;\n\nstruct unicode_map {\n\tunsigned int version;\n\tconst struct utf8data *ntab[2];\n\tconst struct utf8data_table *tables;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 secid;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unixware_slice {\n\t__le16 s_label;\n\t__le16 s_flags;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct unixware_vtoc {\n\t__le32 v_magic;\n\t__le32 v_version;\n\tchar v_name[8];\n\t__le16 v_nslices;\n\t__le16 v_unknown1;\n\t__le32 v_reserved[10];\n\tstruct unixware_slice v_slice[16];\n};\n\nstruct unixware_disklabel {\n\t__le32 d_type;\n\t__le32 d_magic;\n\t__le32 d_version;\n\tchar d_serial[12];\n\t__le32 d_ncylinders;\n\t__le32 d_ntracks;\n\t__le32 d_nsectors;\n\t__le32 d_secsize;\n\t__le32 d_part_start;\n\t__le32 d_unknown1[12];\n\t__le32 d_alt_tbl;\n\t__le32 d_alt_len;\n\t__le32 d_phys_cyl;\n\t__le32 d_phys_trk;\n\t__le32 d_phys_sec;\n\t__le32 d_phys_bytes;\n\t__le32 d_unknown2;\n\t__le32 d_unknown3;\n\t__le32 d_pad[8];\n\tstruct unixware_vtoc vtoc;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\nstruct unwind_stacktrace {\n\tunsigned int nr;\n\tlong unsigned int *entries;\n};\n\nstruct unwind_state {\n\tstruct stack_info stack_info;\n\tlong unsigned int stack_mask;\n\tstruct task_struct *task;\n\tstruct pt_regs *regs;\n\tlong unsigned int sp;\n\tlong unsigned int ip;\n\tint graph_idx;\n\tstruct llist_node *kr_cur;\n\tbool reliable;\n\tbool error;\n};\n\nstruct unwind_work;\n\ntypedef void (*unwind_callback_t)(struct unwind_work *, struct unwind_stacktrace *, u64);\n\nstruct unwind_work {\n\tstruct list_head list;\n\tunwind_callback_t func;\n\tint bit;\n};\n\nstruct update_classid_context {\n\tu32 classid;\n\tunsigned int batch;\n};\n\nunion upper_chunk {\n\tunion upper_chunk *next;\n\tunion lower_chunk *data[256];\n};\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct list_head consumers;\n\tstruct inode *inode;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n\tint dsize;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunsigned int depth;\n\tstruct return_instance *return_instances;\n\tstruct return_instance *ri_pool;\n\tstruct timer_list ri_timer;\n\tseqcount_t ri_seqcount;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tbool signal_denied;\n\tstruct arch_uprobe *auprobe;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct used_entry {\n\tu32 id;\n\tu32 len;\n};\n\nstruct user_arg_ptr {\n\tunion {\n\t\tconst char * const *native;\n\t} ptr;\n};\n\nstruct user_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap roles;\n\tstruct mls_range range;\n\tstruct mls_level dfltlevel;\n};\n\nstruct user_event_group;\n\nstruct user_event {\n\tstruct user_event_group *group;\n\tchar *reg_name;\n\tstruct tracepoint tracepoint;\n\tstruct trace_event_call call;\n\tstruct trace_event_class class;\n\tstruct dyn_event devent;\n\tstruct hlist_node node;\n\tstruct list_head fields;\n\tstruct list_head validators;\n\tstruct work_struct put_work;\n\trefcount_t refcnt;\n\tint min_size;\n\tint reg_flags;\n\tchar status;\n};\n\nstruct user_event_enabler {\n\tstruct list_head mm_enablers_link;\n\tstruct user_event *event;\n\tlong unsigned int addr;\n\tlong unsigned int values;\n};\n\nstruct user_event_enabler_fault {\n\tstruct work_struct work;\n\tstruct user_event_mm *mm;\n\tstruct user_event_enabler *enabler;\n\tint attempt;\n};\n\nstruct user_event_refs;\n\nstruct user_event_file_info {\n\tstruct user_event_group *group;\n\tstruct user_event_refs *refs;\n};\n\nstruct user_event_group {\n\tchar *system_name;\n\tchar *system_multi_name;\n\tstruct hlist_node node;\n\tstruct mutex reg_mutex;\n\tstruct hlist_head register_table[256];\n\tu64 multi_id;\n};\n\nstruct user_event_mm {\n\tstruct list_head mms_link;\n\tstruct list_head enablers;\n\tstruct mm_struct *mm;\n\tstruct user_event_mm *next;\n\trefcount_t refcnt;\n\trefcount_t tasks;\n\tstruct rcu_work put_rwork;\n};\n\nstruct user_event_refs {\n\tstruct callback_head rcu;\n\tint count;\n\tstruct user_event *events[0];\n};\n\nstruct user_event_validator {\n\tstruct list_head user_event_link;\n\tint offset;\n\tint flags;\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct key *persistent_keyring_register;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[12];\n\tlong int rlimit_max[4];\n\tstruct binfmt_misc *binfmt_misc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct user_reg {\n\t__u32 size;\n\t__u8 enable_bit;\n\t__u8 enable_size;\n\t__u16 flags;\n\t__u64 enable_addr;\n\t__u64 name_args;\n\t__u32 write_index;\n} __attribute__((packed));\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tatomic_t nr_watches;\n\tstruct ratelimit_state ratelimit;\n};\n\nstruct user_syms {\n\tconst char **syms;\n\tchar *buf;\n};\n\nstruct user_unreg {\n\t__u32 size;\n\t__u8 disable_bit;\n\t__u8 __reserved;\n\t__u16 __reserved2;\n\t__u64 disable_addr;\n};\n\nstruct userfaultfd_ctx {\n\twait_queue_head_t fault_pending_wqh;\n\twait_queue_head_t fault_wqh;\n\twait_queue_head_t fd_wqh;\n\twait_queue_head_t event_wqh;\n\tseqcount_spinlock_t refile_seq;\n\trefcount_t refcount;\n\tunsigned int flags;\n\tunsigned int features;\n\tbool released;\n\tstruct rw_semaphore map_changing_lock;\n\tatomic_t mmap_changing;\n\tstruct mm_struct *mm;\n};\n\nstruct userfaultfd_fork_ctx {\n\tstruct userfaultfd_ctx *orig;\n\tstruct userfaultfd_ctx *new;\n\tstruct list_head list;\n};\n\nstruct userfaultfd_unmap_ctx {\n\tstruct userfaultfd_ctx *ctx;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct list_head list;\n};\n\nstruct userfaultfd_wait_queue {\n\tstruct uffd_msg msg;\n\twait_queue_entry_t wq;\n\tstruct userfaultfd_ctx *ctx;\n\tbool waken;\n};\n\nstruct userfaultfd_wake_range {\n\tlong unsigned int start;\n\tlong unsigned int len;\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tunsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct ustring_buffer {\n\tchar buffer[1024];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct utf8cursor {\n\tconst struct unicode_map *um;\n\tenum utf8_normalization n;\n\tconst char *s;\n\tconst char *p;\n\tconst char *ss;\n\tconst char *sp;\n\tunsigned int len;\n\tunsigned int slen;\n\tshort int ccc;\n\tshort int nccc;\n\tunsigned char hangul[12];\n};\n\nstruct utf8data {\n\tunsigned int maxage;\n\tunsigned int offset;\n};\n\nstruct utf8data_table {\n\tconst unsigned int *utf8agetab;\n\tint utf8agetab_size;\n\tconst struct utf8data *utf8nfdicfdata;\n\tint utf8nfdicfdata_size;\n\tconst struct utf8data *utf8nfdidata;\n\tint utf8nfdidata_size;\n\tconst unsigned char *utf8data;\n};\n\nstruct utimbuf {\n\t__kernel_old_time_t actime;\n\t__kernel_old_time_t modtime;\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct uv_cb_header {\n\tu16 len;\n\tu16 cmd;\n\tu16 rc;\n\tu16 rrc;\n};\n\nstruct uv_cb_cfs {\n\tstruct uv_cb_header header;\n\tu64 reserved08[2];\n\tu64 paddr;\n};\n\nstruct uv_cb_init {\n\tstruct uv_cb_header header;\n\tu64 reserved08[2];\n\tu64 stor_origin;\n\tu64 stor_len;\n\tu64 reserved28[4];\n};\n\nstruct uv_cb_list_secrets {\n\tstruct uv_cb_header header;\n\tu64 reserved08[2];\n\tu8 reserved18[6];\n\tu16 start_idx;\n\tu64 list_addr;\n\tu64 reserved28[4];\n};\n\nstruct uv_key_hash {\n\tu64 dword[4];\n};\n\nstruct uv_cb_query_keys {\n\tstruct uv_cb_header header;\n\tu64 reserved08[3];\n\tstruct uv_key_hash key_hashes[15];\n};\n\nstruct uv_cb_retr_secr {\n\tstruct uv_cb_header header;\n\tu64 reserved08[2];\n\tu16 secret_idx;\n\tu16 reserved1a;\n\tu32 buf_size;\n\tu64 buf_addr;\n\tu64 reserved28[4];\n};\n\nstruct uv_cb_share {\n\tstruct uv_cb_header header;\n\tu64 reserved08[3];\n\tu64 paddr;\n\tu64 reserved28;\n};\n\nstruct uv_info {\n\tlong unsigned int inst_calls_list[4];\n\tlong unsigned int uv_base_stor_len;\n\tlong unsigned int guest_base_stor_len;\n\tlong unsigned int guest_virt_base_stor_len;\n\tlong unsigned int guest_virt_var_stor_len;\n\tlong unsigned int guest_cpu_stor_len;\n\tlong unsigned int max_sec_stor_addr;\n\tunsigned int max_num_sec_conf;\n\tshort unsigned int max_guest_cpu_id;\n\tlong unsigned int uv_feature_indications;\n\tlong unsigned int supp_se_hdr_ver;\n\tlong unsigned int supp_se_hdr_pcf;\n\tlong unsigned int conf_dump_storage_state_len;\n\tlong unsigned int conf_dump_finalize_len;\n\tlong unsigned int supp_att_req_hdr_ver;\n\tlong unsigned int supp_att_pflags;\n\tlong unsigned int supp_add_secret_req_ver;\n\tlong unsigned int supp_add_secret_pcf;\n\tlong unsigned int supp_secret_types;\n\tshort unsigned int max_assoc_secrets;\n\tshort unsigned int max_retr_secrets;\n};\n\nstruct uv_secret_list_item_hdr {\n\tu16 index;\n\tu16 type;\n\tu32 length;\n};\n\nstruct uv_secret_list_item {\n\tstruct uv_secret_list_item_hdr hdr;\n\tu64 reserverd08;\n\tu8 id[32];\n};\n\nstruct uv_secret_list {\n\tu16 num_secr_stored;\n\tu16 total_num_secrets;\n\tu16 next_secret_idx;\n\tu16 reserved_06;\n\tu64 reserved_08;\n\tstruct uv_secret_list_item secrets[85];\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct value_name_pair {\n\tint value;\n\tconst char *name;\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[4];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcb_header {\n\tu32 vcb_input_length;\n\tu8 pad_0x04[4];\n\tu16 first_vc_index;\n\tu16 last_vc_index;\n\tu32 pad_0x0c;\n\tu32 cs_token;\n\tu8 pad_0x14[12];\n\tu32 vcb_output_length;\n\tu8 pad_0x24[3];\n\tu8 version;\n\tu16 stored_vc_count;\n\tu16 remaining_vc_count;\n\tu8 pad_0x2c[20];\n};\n\nstruct vcb {\n\tstruct vcb_header vcb_hdr;\n\tu8 vcb_buf[0];\n};\n\nstruct vq_config_block {\n\t__u16 index;\n\t__u16 num;\n};\n\nstruct vcdev_dma_area {\n\tlong unsigned int indicators;\n\tlong unsigned int indicators2;\n\tstruct vq_config_block config_block;\n\t__u8 status;\n};\n\nstruct vce_header {\n\tu32 vce_length;\n\tu8 flags;\n\tu8 key_type;\n\tu16 vc_index;\n\tu8 vc_name[64];\n\tu8 vc_format;\n\tu8 pad_0x49;\n\tu16 key_id_length;\n\tu8 pad_0x4c;\n\tu8 vc_hash_type;\n\tu16 vc_hash_length;\n\tu8 pad_0x50[4];\n\tu32 vc_length;\n\tu8 pad_0x58[8];\n\tu16 vc_hash_offset;\n\tu16 vc_offset;\n\tu8 pad_0x64[28];\n};\n\nstruct vce {\n\tstruct vce_header vce_hdr;\n\tu8 cert_data_buf[0];\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vcssb {\n\tu32 vcssb_length;\n\tu8 pad_0x04[3];\n\tu8 version;\n\tu8 pad_0x08[8];\n\tu32 cs_token;\n\tu8 pad_0x14[12];\n\tu16 total_vc_index_count;\n\tu16 max_vc_index_count;\n\tu8 pad_0x24[28];\n\tu32 max_vce_length;\n\tu32 max_vcxe_length;\n\tu8 pad_0x48[8];\n\tu32 max_single_vcb_length;\n\tu32 total_vcb_length;\n\tu32 max_single_vcxb_length;\n\tu32 total_vcxb_length;\n\tu8 pad_0x60[32];\n};\n\nstruct vd_sneq {\n\tstruct {\n\t\t__u8 identifier: 2;\n\t\t__u8 reserved: 6;\n\t} flags;\n\t__u8 res1;\n\t__u16 format;\n\t__u8 res2[4];\n\t__u8 uit[16];\n\t__u8 res3[8];\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_rng_data {\n\tu64 generation;\n\tu8 is_ready;\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vers_iter {\n\tsize_t param_size;\n\tstruct dm_target_versions *vers;\n\tstruct dm_target_versions *old_vers;\n\tchar *end;\n\tuint32_t flags;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vhost_task {\n\tbool (*fn)(void *);\n\tvoid (*handle_sigkill)(void *);\n\tvoid *data;\n\tstruct completion exited;\n\tlong unsigned int flags;\n\tstruct task_struct *task;\n\tstruct mutex exit_mutex;\n};\n\nstruct vif_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct net_device *dev;\n\tshort unsigned int vif_index;\n\tshort unsigned int vif_flags;\n\tu32 tb_id;\n};\n\nstruct vifctl {\n\tvifi_t vifc_vifi;\n\tunsigned char vifc_flags;\n\tunsigned char vifc_threshold;\n\tunsigned int vifc_rate_limit;\n\tunion {\n\t\tstruct in_addr vifc_lcl_addr;\n\t\tint vifc_lcl_ifindex;\n\t};\n\tstruct in_addr vifc_rmt_addr;\n};\n\nstruct virtio_blk_outhdr {\n\t__virtio32 type;\n\t__virtio32 ioprio;\n\t__virtio64 sector;\n};\n\nstruct virtblk_req {\n\tstruct virtio_blk_outhdr out_hdr;\n\tunion {\n\t\tu8 status;\n\t\tstruct {\n\t\t\t__virtio64 sector;\n\t\t\tu8 status;\n\t\t} zone_append;\n\t} in_hdr;\n\tsize_t in_hdr_len;\n\tstruct sg_table sg_table;\n\tstruct scatterlist sg[0];\n};\n\nstruct virtio_device;\n\nstruct virtio_blk_vq;\n\nstruct virtio_blk {\n\tstruct mutex vdev_mutex;\n\tstruct virtio_device *vdev;\n\tstruct gendisk *disk;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct work_struct config_work;\n\tint index;\n\tint num_vqs;\n\tint io_queues[3];\n\tstruct virtio_blk_vq *vqs;\n\tunsigned int zone_sectors;\n};\n\nstruct virtio_blk_geometry {\n\t__virtio16 cylinders;\n\t__u8 heads;\n\t__u8 sectors;\n};\n\nstruct virtio_blk_zoned_characteristics {\n\t__virtio32 zone_sectors;\n\t__virtio32 max_open_zones;\n\t__virtio32 max_active_zones;\n\t__virtio32 max_append_sectors;\n\t__virtio32 write_granularity;\n\t__u8 model;\n\t__u8 unused2[3];\n};\n\nstruct virtio_blk_config {\n\t__virtio64 capacity;\n\t__virtio32 size_max;\n\t__virtio32 seg_max;\n\tstruct virtio_blk_geometry geometry;\n\t__virtio32 blk_size;\n\t__u8 physical_block_exp;\n\t__u8 alignment_offset;\n\t__virtio16 min_io_size;\n\t__virtio32 opt_io_size;\n\t__u8 wce;\n\t__u8 unused;\n\t__virtio16 num_queues;\n\t__virtio32 max_discard_sectors;\n\t__virtio32 max_discard_seg;\n\t__virtio32 discard_sector_alignment;\n\t__virtio32 max_write_zeroes_sectors;\n\t__virtio32 max_write_zeroes_seg;\n\t__u8 write_zeroes_may_unmap;\n\t__u8 unused1[3];\n\t__virtio32 max_secure_erase_sectors;\n\t__virtio32 max_secure_erase_seg;\n\t__virtio32 secure_erase_sector_alignment;\n\tstruct virtio_blk_zoned_characteristics zoned;\n};\n\nstruct virtio_blk_discard_write_zeroes {\n\t__le64 sector;\n\t__le32 num_sectors;\n\t__le32 flags;\n};\n\nstruct virtqueue;\n\nstruct virtio_blk_vq {\n\tstruct virtqueue *vq;\n\tspinlock_t lock;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct vringh_config_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_config_ops;\n\nstruct virtio_map_ops;\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_ccw_device {\n\tstruct virtio_device vdev;\n\t__u8 config[256];\n\tstruct ccw_device *cdev;\n\tstruct device_dma_parameters dma_parms;\n\t__u32 curr_io;\n\tint err;\n\tunsigned int revision;\n\twait_queue_head_t wait_q;\n\tspinlock_t lock;\n\trwlock_t irq_lock;\n\tstruct mutex io_lock;\n\tstruct list_head virtqueues;\n\tbool is_thinint;\n\tbool going_away;\n\tbool device_lost;\n\tunsigned int config_ready;\n\tvoid *airq_info;\n\tstruct vcdev_dma_area *dma_area;\n\tdma32_t dma_area_addr;\n};\n\nstruct vq_info_block {\n\tdma64_t desc;\n\t__u32 res0;\n\t__u16 index;\n\t__u16 num;\n\tdma64_t avail;\n\tdma64_t used;\n};\n\nstruct vq_info_block_legacy {\n\tdma64_t queue;\n\t__u32 align;\n\t__u16 index;\n\t__u16 num;\n};\n\nstruct virtio_ccw_vq_info {\n\tstruct virtqueue *vq;\n\tdma32_t info_block_addr;\n\tint num;\n\tunion {\n\t\tstruct vq_info_block s;\n\t\tstruct vq_info_block_legacy l;\n\t} *info_block;\n\tint bit_nr;\n\tstruct list_head node;\n\tlong int cookie;\n};\n\nstruct virtqueue_info;\n\nstruct virtio_shm_region;\n\nstruct virtio_config_ops {\n\tvoid (*get)(struct virtio_device *, unsigned int, void *, unsigned int);\n\tvoid (*set)(struct virtio_device *, unsigned int, const void *, unsigned int);\n\tu32 (*generation)(struct virtio_device *);\n\tu8 (*get_status)(struct virtio_device *);\n\tvoid (*set_status)(struct virtio_device *, u8);\n\tvoid (*reset)(struct virtio_device *);\n\tint (*find_vqs)(struct virtio_device *, unsigned int, struct virtqueue **, struct virtqueue_info *, struct irq_affinity *);\n\tvoid (*del_vqs)(struct virtio_device *);\n\tvoid (*synchronize_cbs)(struct virtio_device *);\n\tu64 (*get_features)(struct virtio_device *);\n\tvoid (*get_extended_features)(struct virtio_device *, u64 *);\n\tint (*finalize_features)(struct virtio_device *);\n\tconst char * (*bus_name)(struct virtio_device *);\n\tint (*set_vq_affinity)(struct virtqueue *, const struct cpumask *);\n\tconst struct cpumask * (*get_vq_affinity)(struct virtio_device *, int);\n\tbool (*get_shm_region)(struct virtio_device *, struct virtio_shm_region *, u8);\n\tint (*disable_vq_and_reset)(struct virtqueue *);\n\tint (*enable_vq_after_reset)(struct virtqueue *);\n};\n\nstruct virtio_driver {\n\tstruct device_driver driver;\n\tconst struct virtio_device_id *id_table;\n\tconst unsigned int *feature_table;\n\tunsigned int feature_table_size;\n\tconst unsigned int *feature_table_legacy;\n\tunsigned int feature_table_size_legacy;\n\tint (*validate)(struct virtio_device *);\n\tint (*probe)(struct virtio_device *);\n\tvoid (*scan)(struct virtio_device *);\n\tvoid (*remove)(struct virtio_device *);\n\tvoid (*config_changed)(struct virtio_device *);\n\tint (*freeze)(struct virtio_device *);\n\tint (*restore)(struct virtio_device *);\n\tint (*reset_prepare)(struct virtio_device *);\n\tint (*reset_done)(struct virtio_device *);\n\tvoid (*shutdown)(struct virtio_device *);\n};\n\nstruct virtio_feature_desc {\n\t__le32 features;\n\t__u8 index;\n} __attribute__((packed));\n\nstruct virtio_input_event {\n\t__le16 type;\n\t__le16 code;\n\t__le32 value;\n};\n\nstruct virtio_input {\n\tstruct virtio_device *vdev;\n\tstruct input_dev *idev;\n\tchar name[64];\n\tchar serial[64];\n\tchar phys[64];\n\tstruct virtqueue *evt;\n\tstruct virtqueue *sts;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_input_event evts[64];\n\t__u8 __cacheline_group_end__[0];\n\tspinlock_t lock;\n\tbool ready;\n};\n\nstruct virtio_input_absinfo {\n\t__le32 min;\n\t__le32 max;\n\t__le32 fuzz;\n\t__le32 flat;\n\t__le32 res;\n};\n\nstruct virtio_input_devids {\n\t__le16 bustype;\n\t__le16 vendor;\n\t__le16 product;\n\t__le16 version;\n};\n\nstruct virtio_input_config {\n\t__u8 select;\n\t__u8 subsel;\n\t__u8 size;\n\t__u8 reserved[5];\n\tunion {\n\t\tchar string[128];\n\t\t__u8 bitmap[128];\n\t\tstruct virtio_input_absinfo abs;\n\t\tstruct virtio_input_devids ids;\n\t} u;\n};\n\nstruct virtio_map_ops {\n\tdma_addr_t (*map_page)(union virtio_map, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid * (*alloc)(union virtio_map, size_t, dma_addr_t *, gfp_t);\n\tvoid (*free)(union virtio_map, size_t, void *, dma_addr_t, long unsigned int);\n\tbool (*need_sync)(union virtio_map, dma_addr_t);\n\tint (*mapping_error)(union virtio_map, dma_addr_t);\n\tsize_t (*max_mapping_size)(union virtio_map);\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_rev_info {\n\t__u16 revision;\n\t__u16 length;\n\t__u8 data[0];\n};\n\nstruct virtio_shm_region {\n\tu64 addr;\n\tu64 len;\n};\n\nstruct virtio_thinint_area {\n\tdma64_t summary_indicator;\n\tdma64_t indicator;\n\tu64 bit_nr;\n\tu8 isc;\n} __attribute__((packed));\n\nstruct virtqueue {\n\tstruct list_head list;\n\tvoid (*callback)(struct virtqueue *);\n\tconst char *name;\n\tstruct virtio_device *vdev;\n\tunsigned int index;\n\tunsigned int num_free;\n\tunsigned int num_max;\n\tbool reset;\n\tvoid *priv;\n};\n\ntypedef void vq_callback_t(struct virtqueue *);\n\nstruct virtqueue_info {\n\tconst char *name;\n\tvq_callback_t *callback;\n\tbool ctx;\n};\n\nstruct vring_virtqueue;\n\nstruct virtqueue_ops {\n\tint (*add)(struct vring_virtqueue *, struct scatterlist **, unsigned int, unsigned int, unsigned int, void *, void *, bool, gfp_t, long unsigned int);\n\tvoid * (*get)(struct vring_virtqueue *, unsigned int *, void **);\n\tbool (*kick_prepare)(struct vring_virtqueue *);\n\tvoid (*disable_cb)(struct vring_virtqueue *);\n\tbool (*enable_cb_delayed)(struct vring_virtqueue *);\n\tunsigned int (*enable_cb_prepare)(struct vring_virtqueue *);\n\tbool (*poll)(const struct vring_virtqueue *, unsigned int);\n\tvoid * (*detach_unused_buf)(struct vring_virtqueue *);\n\tbool (*more_used)(const struct vring_virtqueue *);\n\tint (*resize)(struct vring_virtqueue *, u32);\n\tvoid (*reset)(struct vring_virtqueue *);\n};\n\nstruct vlan_priority_tci_mapping;\n\nstruct vlan_pcpu_stats;\n\nstruct vlan_dev_priv {\n\tunsigned int nr_ingress_mappings;\n\tu32 ingress_priority_map[8];\n\tunsigned int nr_egress_mappings;\n\tstruct vlan_priority_tci_mapping *egress_priority_map[16];\n\t__be16 vlan_proto;\n\tu16 vlan_id;\n\tu16 flags;\n\tstruct net_device *real_dev;\n\tnetdevice_tracker dev_tracker;\n\tunsigned char real_dev_addr[6];\n\tstruct proc_dir_entry *dent;\n\tstruct vlan_pcpu_stats *vlan_pcpu_stats;\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_group {\n\tunsigned int nr_vlan_devs;\n\tstruct hlist_node hlist;\n\tstruct net_device **vlan_devices_arrays[16];\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_info {\n\tstruct net_device *real_dev;\n\tstruct vlan_group grp;\n\tstruct list_head vid_list;\n\tunsigned int nr_vids;\n\tbool auto_vid0;\n\tstruct callback_head rcu;\n};\n\nstruct vlan_pcpu_stats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_multicast;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n\tu32 rx_errors;\n\tu32 tx_dropped;\n};\n\nstruct vlan_priority_tci_mapping {\n\tu32 priority;\n\tu16 vlan_qos;\n\tstruct vlan_priority_tci_mapping *next;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vlan_vid_info {\n\tstruct list_head list;\n\t__be16 proto;\n\tu16 vid;\n\tint refcount;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {\n\tstruct userfaultfd_ctx *ctx;\n};\n\nstruct vma_numab_state;\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tunsigned int vm_lock_seq;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct mempolicy *vm_policy;\n\tstruct vma_numab_state *numab_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\trefcount_t vm_refcnt;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct anon_vma_name *anon_name;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[113];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_layout {\n\tlong unsigned int kaslr_offset;\n\tlong unsigned int kaslr_offset_phys;\n\tlong unsigned int identity_base;\n\tlong unsigned int identity_size;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n\tint (*set_policy)(struct vm_area_struct *, struct mempolicy *);\n\tstruct mempolicy * (*get_policy)(struct vm_area_struct *, long unsigned int, long unsigned int *);\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct vm_stack {\n\tstruct callback_head rcu;\n\tstruct vm_struct *stack_vm_area;\n};\n\ntypedef struct vm_struct *pcp_op_T_____10;\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_exclude_readers_state {\n\tstruct vm_area_struct *vma;\n\tint state;\n\tbool detaching;\n\tbool detached;\n\tbool exclusive;\n};\n\nstruct vma_list {\n\tstruct vm_area_struct *vma;\n\tstruct list_head head;\n\trefcount_t mmap_count;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_numab_state {\n\tlong unsigned int next_scan;\n\tlong unsigned int pids_active_reset;\n\tlong unsigned int pids_active[2];\n\tint start_scan_seq;\n\tint prev_scan_seq;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[16];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmcore_cb {\n\tbool (*pfn_is_ram)(struct vmcore_cb *, long unsigned int);\n\tint (*get_device_ram)(struct vmcore_cb *, struct list_head *);\n\tstruct list_head next;\n};\n\nstruct vmcore_range {\n\tstruct list_head list;\n\tlong long unsigned int paddr;\n\tlong long unsigned int size;\n\tloff_t offset;\n};\n\nstruct vmcp_session {\n\tchar *response;\n\tunsigned int bufsize;\n\tunsigned int cma_alloc: 1;\n\tint resp_size;\n\tint resp_code;\n\tstruct mutex mutex;\n};\n\nstruct vmpressure_event {\n\tstruct eventfd_ctx *efd;\n\tenum vmpressure_levels level;\n\tenum vmpressure_modes mode;\n\tstruct list_head node;\n};\n\nstruct vring_desc;\n\ntypedef struct vring_desc vring_desc_t;\n\nstruct vring_avail;\n\ntypedef struct vring_avail vring_avail_t;\n\nstruct vring_used;\n\ntypedef struct vring_used vring_used_t;\n\nstruct vring {\n\tunsigned int num;\n\tvring_desc_t *desc;\n\tvring_avail_t *avail;\n\tvring_used_t *used;\n};\n\nstruct vring_avail {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\t__virtio16 ring[0];\n};\n\nstruct vring_desc {\n\t__virtio64 addr;\n\t__virtio32 len;\n\t__virtio16 flags;\n\t__virtio16 next;\n};\n\nstruct vring_desc_extra {\n\tdma_addr_t addr;\n\tu32 len;\n\tu16 flags;\n\tu16 next;\n};\n\nstruct vring_packed_desc;\n\nstruct vring_desc_state_packed {\n\tvoid *data;\n\tstruct vring_packed_desc *indir_desc;\n\tu16 num;\n\tu16 last;\n\tu32 total_in_len;\n};\n\nstruct vring_desc_state_split {\n\tvoid *data;\n\tstruct vring_desc *indir_desc;\n\tu32 total_in_len;\n};\n\nstruct vring_packed_desc {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 id;\n\t__le16 flags;\n};\n\nstruct vring_packed_desc_event {\n\t__le16 off_wrap;\n\t__le16 flags;\n};\n\nstruct vring_used_elem {\n\t__virtio32 id;\n\t__virtio32 len;\n};\n\ntypedef struct vring_used_elem vring_used_elem_t;\n\nstruct vring_used {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\tvring_used_elem_t ring[0];\n};\n\nstruct vring_virtqueue_split {\n\tstruct vring vring;\n\tu16 avail_flags_shadow;\n\tu16 avail_idx_shadow;\n\tstruct vring_desc_state_split *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t queue_dma_addr;\n\tsize_t queue_size_in_bytes;\n\tu32 vring_align;\n\tbool may_reduce_num;\n};\n\nstruct vring_virtqueue_packed {\n\tstruct {\n\t\tunsigned int num;\n\t\tstruct vring_packed_desc *desc;\n\t\tstruct vring_packed_desc_event *driver;\n\t\tstruct vring_packed_desc_event *device;\n\t} vring;\n\tbool avail_wrap_counter;\n\tu16 avail_used_flags;\n\tu16 next_avail_idx;\n\tu16 event_flags_shadow;\n\tstruct vring_desc_state_packed *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t ring_dma_addr;\n\tdma_addr_t driver_event_dma_addr;\n\tdma_addr_t device_event_dma_addr;\n\tsize_t ring_size_in_bytes;\n\tsize_t event_size_in_bytes;\n};\n\nstruct vring_virtqueue {\n\tstruct virtqueue vq;\n\tbool use_map_api;\n\tbool weak_barriers;\n\tbool broken;\n\tbool indirect;\n\tbool event;\n\tenum vq_layout layout;\n\tunsigned int free_head;\n\tstruct used_entry batch_last;\n\tunsigned int num_added;\n\tu16 last_used_idx;\n\tu16 last_used;\n\tbool event_triggered;\n\tunion {\n\t\tstruct vring_virtqueue_split split;\n\t\tstruct vring_virtqueue_packed packed;\n\t};\n\tbool (*notify)(struct virtqueue *);\n\tbool we_own_ring;\n\tunion virtio_map map;\n};\n\nstruct vt220_sccb {\n\tstruct sccb_header header;\n\tstruct {\n\t\tstruct evbuf_header header;\n\t\tchar data[0];\n\t} msg;\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vtimer_list {\n\tstruct list_head entry;\n\tu64 expires;\n\tu64 interval;\n\tvoid (*function)(long unsigned int);\n\tlong unsigned int data;\n};\n\nstruct vtoc_cchh {\n\t__u16 cc;\n\t__u16 hh;\n};\n\nstruct vtoc_extent {\n\t__u8 typeind;\n\t__u8 seqno;\n\tstruct vtoc_cchh llimit;\n\tstruct vtoc_cchh ulimit;\n};\n\nstruct vtoc_labeldate {\n\t__u8 year;\n\t__u16 day;\n} __attribute__((packed));\n\nstruct vtoc_ttr {\n\t__u16 tt;\n\t__u8 r;\n} __attribute__((packed));\n\nstruct vtoc_format1_label {\n\tchar DS1DSNAM[44];\n\t__u8 DS1FMTID;\n\tchar DS1DSSN[6];\n\t__u16 DS1VOLSQ;\n\tstruct vtoc_labeldate DS1CREDT;\n\tstruct vtoc_labeldate DS1EXPDT;\n\t__u8 DS1NOEPV;\n\t__u8 DS1NOBDB;\n\t__u8 DS1FLAG1;\n\tchar DS1SYSCD[13];\n\tstruct vtoc_labeldate DS1REFD;\n\t__u8 DS1SMSFG;\n\t__u8 DS1SCXTF;\n\t__u16 DS1SCXTV;\n\t__u8 DS1DSRG1;\n\t__u8 DS1DSRG2;\n\t__u8 DS1RECFM;\n\t__u8 DS1OPTCD;\n\t__u16 DS1BLKL;\n\t__u16 DS1LRECL;\n\t__u8 DS1KEYL;\n\t__u16 DS1RKP;\n\t__u8 DS1DSIND;\n\t__u8 DS1SCAL1;\n\tchar DS1SCAL3[3];\n\tstruct vtoc_ttr DS1LSTAR;\n\t__u16 DS1TRBAL;\n\t__u16 res1;\n\tstruct vtoc_extent DS1EXT1;\n\tstruct vtoc_extent DS1EXT2;\n\tstruct vtoc_extent DS1EXT3;\n\tstruct vtoc_cchhb DS1PTRDS;\n} __attribute__((packed));\n\nstruct vtunnel_info {\n\tu32 tunid;\n\tu16 vid;\n\tu16 flags;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_exceptional_entry_queue {\n\twait_queue_entry_t wait;\n\tstruct exceptional_entry_key key;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct waiting_dir_move {\n\tstruct rb_node node;\n\tu64 ino;\n\tu64 rmdir_ino;\n\tu64 rmdir_gen;\n\tbool orphanized;\n};\n\nstruct wake_irq;\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n};\n\nstruct walk_control {\n\tu64 refs[8];\n\tu64 flags[8];\n\tstruct btrfs_key update_progress;\n\tstruct btrfs_key drop_progress;\n\tint drop_level;\n\tint stage;\n\tint level;\n\tint shared_level;\n\tint update_ref;\n\tint keep_locks;\n\tint reada_slot;\n\tint reada_count;\n\tint restarted;\n\tint lookup_info;\n};\n\nstruct walk_control___2 {\n\tbool free;\n\tbool pin;\n\tint stage;\n\tbool ignore_cur_inode;\n\tstruct btrfs_root *root;\n\tstruct btrfs_root *log;\n\tstruct btrfs_trans_handle *trans;\n\tint (*process_func)(struct extent_buffer *, struct walk_control___2 *, u64, int);\n\tstruct extent_buffer *log_leaf;\n\tstruct btrfs_key log_key;\n\tint log_slot;\n\tstruct btrfs_path *subvol_path;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct watch {\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tu32 info_id;\n\t};\n\tstruct watch_queue *queue;\n\tstruct hlist_node queue_node;\n\tstruct watch_list *watch_list;\n\tstruct hlist_node list_node;\n\tconst struct cred *cred;\n\tvoid *private;\n\tu64 id;\n\tstruct kref usage;\n};\n\nstruct watch_type_filter {\n\tenum watch_notification_type type;\n\t__u32 subtype_filter[1];\n\t__u32 info_filter;\n\t__u32 info_mask;\n};\n\nstruct watch_filter {\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tlong unsigned int type_filter[1];\n\t};\n\tu32 nr_filters;\n\tstruct watch_type_filter filters[0];\n};\n\nstruct watch_list {\n\tstruct callback_head rcu;\n\tstruct hlist_head watchers;\n\tvoid (*release_watch)(struct watch *);\n\tspinlock_t lock;\n};\n\nstruct watch_notification_type_filter {\n\t__u32 type;\n\t__u32 info_filter;\n\t__u32 info_mask;\n\t__u32 subtype_filter[8];\n};\n\nstruct watch_notification_filter {\n\t__u32 nr_filters;\n\t__u32 __reserved;\n\tstruct watch_notification_type_filter filters[0];\n};\n\nstruct watch_notification_removal {\n\tstruct watch_notification watch;\n\t__u64 id;\n};\n\nstruct watch_queue {\n\tstruct callback_head rcu;\n\tstruct watch_filter *filter;\n\tstruct pipe_inode_info *pipe;\n\tstruct hlist_head watches;\n\tstruct page **notes;\n\tlong unsigned int *notes_bitmap;\n\tstruct kref usage;\n\tspinlock_t lock;\n\tunsigned int nr_notes;\n\tunsigned int nr_pages;\n};\n\nstruct watchdog_device;\n\nstruct watchdog_core_data {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct watchdog_device *wdd;\n\tstruct mutex lock;\n\tktime_t last_keepalive;\n\tktime_t last_hw_keepalive;\n\tktime_t open_deadline;\n\tstruct hrtimer timer;\n\tstruct kthread_work work;\n\tlong unsigned int status;\n};\n\nstruct watchdog_info;\n\nstruct watchdog_ops;\n\nstruct watchdog_governor;\n\nstruct watchdog_device {\n\tint id;\n\tstruct device *parent;\n\tconst struct attribute_group **groups;\n\tconst struct watchdog_info *info;\n\tconst struct watchdog_ops *ops;\n\tconst struct watchdog_governor *gov;\n\tunsigned int bootstatus;\n\tunsigned int timeout;\n\tunsigned int pretimeout;\n\tunsigned int min_timeout;\n\tunsigned int max_timeout;\n\tunsigned int min_hw_heartbeat_ms;\n\tunsigned int max_hw_heartbeat_ms;\n\tstruct notifier_block reboot_nb;\n\tstruct notifier_block restart_nb;\n\tstruct notifier_block pm_nb;\n\tvoid *driver_data;\n\tstruct watchdog_core_data *wd_data;\n\tlong unsigned int status;\n\tstruct list_head deferred;\n};\n\nstruct watchdog_governor {\n\tconst char name[20];\n\tvoid (*pretimeout)(struct watchdog_device *);\n};\n\nstruct watchdog_info {\n\t__u32 options;\n\t__u32 firmware_version;\n\t__u8 identity[32];\n};\n\nstruct watchdog_ops {\n\tstruct module *owner;\n\tint (*start)(struct watchdog_device *);\n\tint (*stop)(struct watchdog_device *);\n\tint (*ping)(struct watchdog_device *);\n\tunsigned int (*status)(struct watchdog_device *);\n\tint (*set_timeout)(struct watchdog_device *, unsigned int);\n\tint (*set_pretimeout)(struct watchdog_device *, unsigned int);\n\tunsigned int (*get_timeleft)(struct watchdog_device *);\n\tint (*restart)(struct watchdog_device *, long unsigned int, void *);\n\tlong int (*ioctl)(struct watchdog_device *, unsigned int, long unsigned int);\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct wbt_wait_data {\n\tstruct rq_wb *rwb;\n\tenum wbt_flags wb_acct;\n\tblk_opf_t opf;\n};\n\nstruct weighted_interleave_state {\n\tbool mode_auto;\n\tu8 iw_table[0];\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int bits;\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct workspace {\n\tvoid *mem;\n\tvoid *buf;\n\tvoid *cbuf;\n\tstruct list_head list;\n};\n\nstruct workspace___2 {\n\tz_stream strm;\n\tchar *buf;\n\tunsigned int buf_size;\n\tstruct list_head list;\n\tint level;\n};\n\nstruct workspace___3 {\n\tvoid *mem;\n\tsize_t size;\n\tchar *buf;\n\tint level;\n\tint req_level;\n\tlong unsigned int last_used;\n\tstruct list_head list;\n\tstruct list_head lru_list;\n\tzstd_in_buffer in_buf;\n\tzstd_out_buffer out_buf;\n\tzstd_parameters params;\n};\n\nstruct workspace_manager {\n\tstruct list_head idle_ws;\n\tspinlock_t ws_lock;\n\tint free_ws;\n\tatomic_t total_ws;\n\twait_queue_head_t ws_wait;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct write_sccb {\n\tstruct sccb_header header;\n\tstruct msg_buf msg;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n\tstruct bdi_writeback *wb;\n\tstruct inode *inode;\n\tint wb_id;\n\tint wb_lcand_id;\n\tint wb_tcand_id;\n\tsize_t wb_bytes;\n\tsize_t wb_lcand_bytes;\n\tsize_t wb_tcand_bytes;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct wti_debug {\n\tlong unsigned int missed;\n\tlong unsigned int addr;\n\tpid_t pid;\n};\n\nstruct wti_state {\n\tstruct wti_debug dbg;\n\tstruct task_struct *thread;\n\tbool pending;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct x509_certificate {\n\tstruct x509_certificate *next;\n\tstruct x509_certificate *signer;\n\tstruct public_key *pub;\n\tstruct public_key_signature *sig;\n\tu8 sha256[32];\n\tchar *issuer;\n\tchar *subject;\n\tstruct asymmetric_key_id *id;\n\tstruct asymmetric_key_id *skid;\n\ttime64_t valid_from;\n\ttime64_t valid_to;\n\tconst void *tbs;\n\tunsigned int tbs_size;\n\tunsigned int raw_sig_size;\n\tconst void *raw_sig;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_subject;\n\tunsigned int raw_subject_size;\n\tunsigned int raw_skid_size;\n\tconst void *raw_skid;\n\tunsigned int index;\n\tbool seen;\n\tbool verified;\n\tbool self_signed;\n\tbool unsupported_sig;\n\tbool blacklisted;\n};\n\nstruct x509_parse_context {\n\tstruct x509_certificate *cert;\n\tlong unsigned int data;\n\tconst void *key;\n\tsize_t key_size;\n\tconst void *params;\n\tsize_t params_size;\n\tenum OID key_algo;\n\tenum OID last_oid;\n\tenum OID sig_algo;\n\tu8 o_size;\n\tu8 cn_size;\n\tu8 email_size;\n\tu16 o_offset;\n\tu16 cn_offset;\n\tu16 email_offset;\n\tunsigned int raw_akid_size;\n\tconst void *raw_akid;\n\tconst void *akid_raw_issuer;\n\tunsigned int akid_raw_issuer_size;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[3];\n\t\tlong unsigned int marks[3];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xbc_node {\n\tuint16_t next;\n\tuint16_t child;\n\tuint16_t parent;\n\tuint16_t data;\n};\n\nstruct xbtree_afakeroot {\n\txfs_agblock_t af_root;\n\tunsigned int af_levels;\n\tunsigned int af_blocks;\n};\n\nstruct xfs_ifork;\n\nstruct xbtree_ifakeroot {\n\tstruct xfs_ifork *if_fork;\n\tint64_t if_blocks;\n\tunsigned int if_levels;\n\tunsigned int if_fork_size;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xsk_tx_metadata;\n\nstruct xdp_desc_ctx {\n\tdma_addr_t dma;\n\tstruct xsk_tx_metadata *meta;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_ring_offset {\n\t__u64 producer;\n\t__u64 consumer;\n\t__u64 desc;\n\t__u64 flags;\n};\n\nstruct xdp_mmap_offsets {\n\tstruct xdp_ring_offset rx;\n\tstruct xdp_ring_offset tx;\n\tstruct xdp_ring_offset fr;\n\tstruct xdp_ring_offset cr;\n};\n\nstruct xdp_ring_offset_v1 {\n\t__u64 producer;\n\t__u64 consumer;\n\t__u64 desc;\n};\n\nstruct xdp_mmap_offsets_v1 {\n\tstruct xdp_ring_offset_v1 rx;\n\tstruct xdp_ring_offset_v1 tx;\n\tstruct xdp_ring_offset_v1 fr;\n\tstruct xdp_ring_offset_v1 cr;\n};\n\nstruct xdp_options {\n\t__u32 flags;\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xdp_ring {\n\tu32 producer;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 pad1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 consumer;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 pad2;\n\tu32 flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 pad3;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_rxtx_ring {\n\tstruct xdp_ring ptrs;\n\tstruct xdp_desc desc[0];\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_statistics {\n\t__u64 rx_dropped;\n\t__u64 rx_invalid_descs;\n\t__u64 tx_invalid_descs;\n\t__u64 rx_ring_full;\n\t__u64 rx_fill_ring_empty_descs;\n\t__u64 tx_ring_empty_descs;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n};\n\nstruct xdp_umem_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u32 chunk_size;\n\t__u32 headroom;\n\t__u32 flags;\n\t__u32 tx_metadata_len;\n};\n\nstruct xdp_umem_ring {\n\tstruct xdp_ring ptrs;\n\tu64 desc[0];\n};\n\nunion xfs_btree_ptr {\n\t__be32 s;\n\t__be64 l;\n};\n\nstruct xfs_buftarg;\n\nstruct xfbtree {\n\tstruct xfs_buftarg *target;\n\txfbno_t highest_bno;\n\tlong long unsigned int owner;\n\tunion xfs_btree_ptr root;\n\tunsigned int nlevels;\n\tunsigned int maxrecs[2];\n\tunsigned int minrecs[2];\n};\n\nstruct xfrm4_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm4_protocol *next;\n\tint priority;\n};\n\nstruct xfrm6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tstruct xfrm6_protocol *next;\n\tint priority;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_dst {\n\tunion {\n\t\tstruct dst_entry dst;\n\t\tstruct rtable rt;\n\t\tstruct rt6_info rt6;\n\t} u;\n\tstruct dst_entry *route;\n\tstruct dst_entry *child;\n\tstruct dst_entry *path;\n\tstruct xfrm_policy *pols[2];\n\tint num_pols;\n\tint num_xfrms;\n\tu32 xfrm_genid;\n\tu32 policy_genid;\n\tu32 route_mtu_cached;\n\tu32 child_mtu_cached;\n\tu32 route_cookie;\n\tu32 path_cookie;\n};\n\nstruct xfrm_dst_lookup_params {\n\tstruct net *net;\n\tdscp_t dscp;\n\tint oif;\n\txfrm_address_t *saddr;\n\txfrm_address_t *daddr;\n\tu32 mark;\n\t__u8 ipproto;\n\tunion flowi_uli uli;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_flo {\n\tstruct dst_entry *dst_orig;\n\tu8 flags;\n};\n\nstruct xfrm_flow_keys {\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_control control;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t} addrs;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_keyid gre;\n};\n\nstruct xfrm_hash_state_ptrs {\n\tconst struct hlist_head *bydst;\n\tconst struct hlist_head *bysrc;\n\tconst struct hlist_head *byspi;\n\tunsigned int hmask;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_if_decode_session_result;\n\nstruct xfrm_if_cb {\n\tbool (*decode_session)(struct sk_buff *, short unsigned int, struct xfrm_if_decode_session_result *);\n};\n\nstruct xfrm_if_decode_session_result {\n\tstruct net *net;\n\tu32 if_id;\n};\n\nstruct xfrm_input_afinfo {\n\tu8 family;\n\tbool is_ipip;\n\tint (*callback)(struct sk_buff *, u8, int);\n};\n\nstruct xfrm_kmaddress {\n\txfrm_address_t local;\n\txfrm_address_t remote;\n\tu32 reserved;\n\tu16 family;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_tmpl;\n\nstruct xfrm_selector;\n\nstruct xfrm_migrate;\n\nstruct xfrm_mgr {\n\tstruct list_head list;\n\tint (*notify)(struct xfrm_state *, const struct km_event *);\n\tint (*acquire)(struct xfrm_state *, struct xfrm_tmpl *, struct xfrm_policy *);\n\tstruct xfrm_policy * (*compile_policy)(struct sock *, int, u8 *, int, int *);\n\tint (*new_mapping)(struct xfrm_state *, xfrm_address_t *, __be16);\n\tint (*notify_policy)(struct xfrm_policy *, int, const struct km_event *);\n\tint (*report)(struct net *, u8, struct xfrm_selector *, xfrm_address_t *);\n\tint (*migrate)(const struct xfrm_selector *, u8, u8, const struct xfrm_migrate *, int, const struct xfrm_kmaddress *, const struct xfrm_encap_tmpl *);\n\tbool (*is_alive)(const struct km_event *);\n};\n\nstruct xfrm_migrate {\n\txfrm_address_t old_daddr;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_daddr;\n\txfrm_address_t new_saddr;\n\tu8 proto;\n\tu8 mode;\n\tu16 reserved;\n\tu32 reqid;\n\tu16 old_family;\n\tu16 new_family;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_tunnel_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tunion {\n\t\tstruct ip_tunnel *ip4;\n\t\tstruct ip6_tnl *ip6;\n\t} tunnel;\n};\n\nstruct xfrm_mode_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\t__be16 id;\n\t__be16 frag_off;\n\tu8 ihl;\n\tu8 tos;\n\tu8 ttl;\n\tu8 protocol;\n\tu8 optlen;\n\tu8 flow_lbl[3];\n};\n\nstruct xfrm_pol_inexact_key {\n\tpossible_net_t net;\n\tu32 if_id;\n\tu16 family;\n\tu8 dir;\n\tu8 type;\n};\n\nstruct xfrm_pol_inexact_bin {\n\tstruct xfrm_pol_inexact_key k;\n\tstruct rhash_head head;\n\tstruct hlist_head hhead;\n\tseqcount_spinlock_t count;\n\tstruct rb_root root_d;\n\tstruct rb_root root_s;\n\tstruct list_head inexact_bins;\n\tstruct callback_head rcu;\n};\n\nstruct xfrm_pol_inexact_candidates {\n\tstruct hlist_head *res[4];\n};\n\nstruct xfrm_pol_inexact_node {\n\tstruct rb_node node;\n\tunion {\n\t\txfrm_address_t addr;\n\t\tstruct callback_head rcu;\n\t};\n\tu8 prefixlen;\n\tstruct rb_root root;\n\tstruct hlist_head hhead;\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_policy_walk_entry {\n\tstruct list_head all;\n\tu8 dead;\n};\n\nstruct xfrm_policy_queue {\n\tstruct sk_buff_head hold_queue;\n\tstruct timer_list hold_timer;\n\tlong unsigned int timeout;\n};\n\nstruct xfrm_tmpl {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tshort unsigned int encap_family;\n\tu32 reqid;\n\tu8 mode;\n\tu8 share;\n\tu8 optional;\n\tu8 allalgs;\n\tu32 aalgos;\n\tu32 ealgos;\n\tu32 calgos;\n};\n\nstruct xfrm_sec_ctx;\n\nstruct xfrm_policy {\n\tpossible_net_t xp_net;\n\tstruct hlist_node bydst;\n\tstruct hlist_node byidx;\n\tstruct hlist_head state_cache_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tu32 pos;\n\tstruct timer_list timer;\n\tatomic_t genid;\n\tu32 priority;\n\tu32 index;\n\tu32 if_id;\n\tstruct xfrm_mark mark;\n\tstruct xfrm_selector selector;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_policy_walk_entry walk;\n\tstruct xfrm_policy_queue polq;\n\tbool bydst_reinsert;\n\tu8 type;\n\tu8 action;\n\tu8 flags;\n\tu8 xfrm_nr;\n\tu16 family;\n\tstruct xfrm_sec_ctx *security;\n\tstruct xfrm_tmpl xfrm_vec[6];\n\tstruct callback_head rcu;\n\tstruct xfrm_dev_offload xdo;\n};\n\nstruct xfrm_policy_afinfo {\n\tstruct dst_ops *dst_ops;\n\tstruct dst_entry * (*dst_lookup)(const struct xfrm_dst_lookup_params *);\n\tint (*get_saddr)(xfrm_address_t *, const struct xfrm_dst_lookup_params *);\n\tint (*fill_dst)(struct xfrm_dst *, struct net_device *, const struct flowi *);\n\tstruct dst_entry * (*blackhole_route)(struct net *, struct dst_entry *);\n};\n\nstruct xfrm_policy_walk {\n\tstruct xfrm_policy_walk_entry walk;\n\tu8 type;\n\tu32 seq;\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 low;\n\t\t\t__u32 hi;\n\t\t} output;\n\t\tstruct {\n\t\t\t__be32 low;\n\t\t\t__be32 hi;\n\t\t} input;\n\t} seq;\n};\n\nstruct xfrm_spi_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunsigned int daddroff;\n\tunsigned int family;\n\t__be32 seq;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_state_afinfo {\n\tu8 family;\n\tu8 proto;\n\tconst struct xfrm_type_offload *type_offload_esp;\n\tconst struct xfrm_type *type_esp;\n\tconst struct xfrm_type *type_ipip;\n\tconst struct xfrm_type *type_ipip6;\n\tconst struct xfrm_type *type_comp;\n\tconst struct xfrm_type *type_ah;\n\tconst struct xfrm_type *type_routing;\n\tconst struct xfrm_type *type_dstopts;\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*transport_finish)(struct sk_buff *, int);\n\tvoid (*local_error)(struct sk_buff *, u32);\n};\n\nstruct xfrm_trans_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tint (*finish)(struct net *, struct sock *, struct sk_buff *);\n\tstruct net *net;\n};\n\nstruct xfrm_trans_tasklet {\n\tstruct work_struct work;\n\tspinlock_t queue_lock;\n\tstruct sk_buff_head queue;\n};\n\nstruct xfrm_translator {\n\tint (*alloc_compat)(struct sk_buff *, const struct nlmsghdr *);\n\tstruct nlmsghdr * (*rcv_msg_compat)(const struct nlmsghdr *, int, const struct nla_policy *, struct netlink_ext_ack *);\n\tint (*xlate_user_policy_sockptr)(u8 **, int);\n\tstruct module *owner;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xfrmk_sadinfo {\n\tu32 sadhcnt;\n\tu32 sadhmcnt;\n\tu32 sadcnt;\n};\n\nstruct xfrmk_spdinfo {\n\tu32 incnt;\n\tu32 outcnt;\n\tu32 fwdcnt;\n\tu32 inscnt;\n\tu32 outscnt;\n\tu32 fwdscnt;\n\tu32 spdhcnt;\n\tu32 spdhmcnt;\n};\n\nstruct xfs_acl_entry {\n\t__be32 ae_tag;\n\t__be32 ae_id;\n\t__be16 ae_perm;\n\t__be16 ae_pad;\n};\n\nstruct xfs_acl {\n\t__be32 acl_cnt;\n\tstruct xfs_acl_entry acl_entry[0];\n};\n\nstruct xfs_ag_geometry {\n\tuint32_t ag_number;\n\tuint32_t ag_length;\n\tuint32_t ag_freeblks;\n\tuint32_t ag_icount;\n\tuint32_t ag_ifree;\n\tuint32_t ag_sick;\n\tuint32_t ag_checked;\n\tuint32_t ag_flags;\n\tuint64_t ag_reserved[12];\n};\n\nstruct xfs_ag_resv {\n\txfs_extlen_t ar_orig_reserved;\n\txfs_extlen_t ar_reserved;\n\txfs_extlen_t ar_asked;\n};\n\nstruct xfs_agf {\n\t__be32 agf_magicnum;\n\t__be32 agf_versionnum;\n\t__be32 agf_seqno;\n\t__be32 agf_length;\n\t__be32 agf_bno_root;\n\t__be32 agf_cnt_root;\n\t__be32 agf_rmap_root;\n\t__be32 agf_bno_level;\n\t__be32 agf_cnt_level;\n\t__be32 agf_rmap_level;\n\t__be32 agf_flfirst;\n\t__be32 agf_fllast;\n\t__be32 agf_flcount;\n\t__be32 agf_freeblks;\n\t__be32 agf_longest;\n\t__be32 agf_btreeblks;\n\tuuid_t agf_uuid;\n\t__be32 agf_rmap_blocks;\n\t__be32 agf_refcount_blocks;\n\t__be32 agf_refcount_root;\n\t__be32 agf_refcount_level;\n\t__be64 agf_spare64[14];\n\t__be64 agf_lsn;\n\t__be32 agf_crc;\n\t__be32 agf_spare2;\n};\n\nstruct xfs_agfl {\n\t__be32 agfl_magicnum;\n\t__be32 agfl_seqno;\n\tuuid_t agfl_uuid;\n\t__be64 agfl_lsn;\n\t__be32 agfl_crc;\n} __attribute__((packed));\n\nstruct xfs_mount;\n\nstruct xfs_buf;\n\ntypedef void (*aghdr_init_work_f)(struct xfs_mount *, struct xfs_buf *, struct aghdr_init_data *);\n\nstruct xfs_buf_ops;\n\nstruct xfs_aghdr_grow_data {\n\txfs_daddr_t daddr;\n\tsize_t numblks;\n\tconst struct xfs_buf_ops *ops;\n\taghdr_init_work_f work;\n\tconst struct xfs_btree_ops *bc_ops;\n\tbool need_init;\n};\n\nstruct xfs_agi {\n\t__be32 agi_magicnum;\n\t__be32 agi_versionnum;\n\t__be32 agi_seqno;\n\t__be32 agi_length;\n\t__be32 agi_count;\n\t__be32 agi_root;\n\t__be32 agi_level;\n\t__be32 agi_freecount;\n\t__be32 agi_newino;\n\t__be32 agi_dirino;\n\t__be32 agi_unlinked[64];\n\tuuid_t agi_uuid;\n\t__be32 agi_crc;\n\t__be32 agi_pad32;\n\t__be64 agi_lsn;\n\t__be32 agi_free_root;\n\t__be32 agi_free_level;\n\t__be32 agi_iblocks;\n\t__be32 agi_fblocks;\n};\n\nstruct xlog;\n\nstruct xfs_ail {\n\tstruct xlog *ail_log;\n\tstruct task_struct *ail_task;\n\tstruct list_head ail_head;\n\tstruct list_head ail_cursors;\n\tspinlock_t ail_lock;\n\txfs_lsn_t ail_last_pushed_lsn;\n\txfs_lsn_t ail_head_lsn;\n\tint ail_log_flush;\n\tlong unsigned int ail_opstate;\n\tstruct list_head ail_buf_list;\n\twait_queue_head_t ail_empty;\n\txfs_lsn_t ail_target;\n};\n\nstruct xfs_log_item;\n\nstruct xfs_ail_cursor {\n\tstruct list_head list;\n\tstruct xfs_log_item *item;\n};\n\nstruct xfs_owner_info {\n\tuint64_t oi_owner;\n\txfs_fileoff_t oi_offset;\n\tunsigned int oi_flags;\n};\n\nstruct xfs_perag;\n\nstruct xfs_alloc_arg {\n\tstruct xfs_trans *tp;\n\tstruct xfs_mount *mp;\n\tstruct xfs_buf *agbp;\n\tstruct xfs_perag *pag;\n\txfs_fsblock_t fsbno;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t minlen;\n\txfs_extlen_t maxlen;\n\txfs_extlen_t mod;\n\txfs_extlen_t prod;\n\txfs_extlen_t minleft;\n\txfs_extlen_t total;\n\txfs_extlen_t alignment;\n\txfs_extlen_t minalignslop;\n\txfs_agblock_t min_agbno;\n\txfs_agblock_t max_agbno;\n\txfs_extlen_t len;\n\tint datatype;\n\tchar wasdel;\n\tchar wasfromfl;\n\tbool alloc_minlen_only;\n\tstruct xfs_owner_info oinfo;\n\tenum xfs_ag_resv_type resv;\n};\n\ntypedef struct xfs_alloc_arg xfs_alloc_arg_t;\n\nstruct xfs_defer_pending;\n\nstruct xfs_alloc_autoreap {\n\tstruct xfs_defer_pending *dfp;\n};\n\nstruct xfs_btree_cur;\n\nstruct xfs_alloc_cur {\n\tstruct xfs_btree_cur *cnt;\n\tstruct xfs_btree_cur *bnolt;\n\tstruct xfs_btree_cur *bnogt;\n\txfs_extlen_t cur_len;\n\txfs_agblock_t rec_bno;\n\txfs_extlen_t rec_len;\n\txfs_agblock_t bno;\n\txfs_extlen_t len;\n\txfs_extlen_t diff;\n\tunsigned int busy_gen;\n\tbool busy;\n};\n\nstruct xfs_alloc_rec_incore;\n\ntypedef int (*xfs_alloc_query_range_fn)(struct xfs_btree_cur *, const struct xfs_alloc_rec_incore *, void *);\n\nstruct xfs_alloc_query_range_info {\n\txfs_alloc_query_range_fn fn;\n\tvoid *priv;\n};\n\nstruct xfs_alloc_rec {\n\t__be32 ar_startblock;\n\t__be32 ar_blockcount;\n};\n\ntypedef struct xfs_alloc_rec xfs_alloc_key_t;\n\ntypedef struct xfs_alloc_rec xfs_alloc_rec_t;\n\nstruct xfs_alloc_rec_incore {\n\txfs_agblock_t ar_startblock;\n\txfs_extlen_t ar_blockcount;\n};\n\nstruct xfs_attr3_icleaf_hdr {\n\tuint32_t forw;\n\tuint32_t back;\n\tuint16_t magic;\n\tuint16_t count;\n\tuint16_t usedbytes;\n\tuint32_t firstused;\n\t__u8 holes;\n\tstruct {\n\t\tuint16_t base;\n\t\tuint16_t size;\n\t} freemap[3];\n};\n\nstruct xfs_da_blkinfo {\n\t__be32 forw;\n\t__be32 back;\n\t__be16 magic;\n\t__be16 pad;\n};\n\nstruct xfs_da3_blkinfo {\n\tstruct xfs_da_blkinfo hdr;\n\t__be32 crc;\n\t__be64 blkno;\n\t__be64 lsn;\n\tuuid_t uuid;\n\t__be64 owner;\n};\n\nstruct xfs_attr_leaf_map {\n\t__be16 base;\n\t__be16 size;\n};\n\nstruct xfs_attr3_leaf_hdr {\n\tstruct xfs_da3_blkinfo info;\n\t__be16 count;\n\t__be16 usedbytes;\n\t__be16 firstused;\n\t__u8 holes;\n\t__u8 pad1;\n\tstruct xfs_attr_leaf_map freemap[3];\n\t__be32 pad2;\n};\n\nstruct xfs_attr_leaf_entry {\n\t__be32 hashval;\n\t__be16 nameidx;\n\t__u8 flags;\n\t__u8 pad2;\n};\n\nstruct xfs_attr3_leafblock {\n\tstruct xfs_attr3_leaf_hdr hdr;\n\tstruct xfs_attr_leaf_entry entries[0];\n};\n\nstruct xfs_attr3_rmt_hdr {\n\t__be32 rm_magic;\n\t__be32 rm_offset;\n\t__be32 rm_bytes;\n\t__be32 rm_crc;\n\tuuid_t rm_uuid;\n\t__be64 rm_owner;\n\t__be64 rm_blkno;\n\t__be64 rm_lsn;\n};\n\nstruct xfs_bmbt_irec {\n\txfs_fileoff_t br_startoff;\n\txfs_fsblock_t br_startblock;\n\txfs_filblks_t br_blockcount;\n\txfs_exntst_t br_state;\n};\n\nstruct xfs_da_state;\n\nstruct xfs_da_args;\n\nstruct xfs_attri_log_nameval;\n\nstruct xfs_attr_intent {\n\tstruct list_head xattri_list;\n\tstruct xfs_da_state *xattri_da_state;\n\tstruct xfs_da_args *xattri_da_args;\n\tstruct xfs_attri_log_nameval *xattri_nameval;\n\tenum xfs_delattr_state xattri_dela_state;\n\tunsigned int xattri_op_flags;\n\txfs_dablk_t xattri_lblkno;\n\tint xattri_blkcnt;\n\tstruct xfs_bmbt_irec xattri_map;\n};\n\ntypedef struct xfs_attr_leaf_entry xfs_attr_leaf_entry_t;\n\ntypedef struct xfs_da_blkinfo xfs_da_blkinfo_t;\n\ntypedef struct xfs_attr_leaf_map xfs_attr_leaf_map_t;\n\nstruct xfs_attr_leaf_hdr {\n\txfs_da_blkinfo_t info;\n\t__be16 count;\n\t__be16 usedbytes;\n\t__be16 firstused;\n\t__u8 holes;\n\t__u8 pad1;\n\txfs_attr_leaf_map_t freemap[3];\n};\n\ntypedef struct xfs_attr_leaf_hdr xfs_attr_leaf_hdr_t;\n\nstruct xfs_attr_leaf_name_local {\n\t__be16 valuelen;\n\t__u8 namelen;\n\t__u8 nameval[0];\n};\n\ntypedef struct xfs_attr_leaf_name_local xfs_attr_leaf_name_local_t;\n\nstruct xfs_attr_leaf_name_remote {\n\t__be32 valueblk;\n\t__be32 valuelen;\n\t__u8 namelen;\n\t__u8 name[0];\n};\n\ntypedef struct xfs_attr_leaf_name_remote xfs_attr_leaf_name_remote_t;\n\nstruct xfs_attr_leafblock {\n\txfs_attr_leaf_hdr_t hdr;\n\txfs_attr_leaf_entry_t entries[0];\n};\n\ntypedef struct xfs_attr_leafblock xfs_attr_leafblock_t;\n\nstruct xfs_attrlist_cursor_kern {\n\t__u32 hashval;\n\t__u32 blkno;\n\t__u32 offset;\n\t__u16 pad1;\n\t__u8 pad2;\n\t__u8 initted;\n};\n\nstruct xfs_attr_list_context;\n\ntypedef void (*put_listent_func_t)(struct xfs_attr_list_context *, int, unsigned char *, int, void *, int);\n\nstruct xfs_inode;\n\nstruct xfs_attr_list_context {\n\tstruct xfs_trans *tp;\n\tstruct xfs_inode *dp;\n\tstruct xfs_attrlist_cursor_kern cursor;\n\tvoid *buffer;\n\tint seen_enough;\n\tbool allow_incomplete;\n\tssize_t count;\n\tint dupcnt;\n\tint bufsize;\n\tint firstu;\n\tunsigned int attr_filter;\n\tint resynch;\n\tput_listent_func_t put_listent;\n\tint index;\n};\n\nstruct xfs_attr_multiop {\n\t__u32 am_opcode;\n\t__s32 am_error;\n\tvoid *am_attrname;\n\tvoid *am_attrvalue;\n\t__u32 am_length;\n\t__u32 am_flags;\n};\n\ntypedef struct xfs_attr_multiop xfs_attr_multiop_t;\n\nstruct xfs_attr_sf_entry {\n\t__u8 namelen;\n\t__u8 valuelen;\n\t__u8 flags;\n\t__u8 nameval[0];\n};\n\nstruct xfs_attr_sf_hdr {\n\t__be16 totsize;\n\t__u8 count;\n\t__u8 padding;\n};\n\nstruct xfs_attr_sf_sort {\n\tuint8_t entno;\n\tuint8_t namelen;\n\tuint8_t valuelen;\n\tuint8_t flags;\n\txfs_dahash_t hash;\n\tunsigned char *name;\n\tvoid *value;\n};\n\ntypedef struct xfs_attr_sf_sort xfs_attr_sf_sort_t;\n\nstruct xfs_attrd_log_format {\n\tuint16_t alfd_type;\n\tuint16_t alfd_size;\n\tuint32_t __pad;\n\tuint64_t alfd_alf_id;\n};\n\nstruct xfs_item_ops;\n\nstruct xfs_log_vec;\n\nstruct xfs_log_item {\n\tstruct list_head li_ail;\n\tstruct list_head li_trans;\n\txfs_lsn_t li_lsn;\n\tstruct xlog *li_log;\n\tstruct xfs_ail *li_ailp;\n\tuint li_type;\n\tlong unsigned int li_flags;\n\tstruct xfs_buf *li_buf;\n\tstruct list_head li_bio_list;\n\tconst struct xfs_item_ops *li_ops;\n\tstruct list_head li_cil;\n\tstruct xfs_log_vec *li_lv;\n\tstruct xfs_log_vec *li_lv_shadow;\n\txfs_csn_t li_seq;\n\tuint32_t li_order_id;\n};\n\nstruct xfs_attri_log_item;\n\nstruct xfs_attrd_log_item {\n\tstruct xfs_log_item attrd_item;\n\tstruct xfs_attri_log_item *attrd_attrip;\n\tstruct xfs_attrd_log_format attrd_format;\n};\n\nstruct xfs_attri_log_format {\n\tuint16_t alfi_type;\n\tuint16_t alfi_size;\n\tuint32_t alfi_igen;\n\tuint64_t alfi_id;\n\tuint64_t alfi_ino;\n\tuint32_t alfi_op_flags;\n\tunion {\n\t\tuint32_t alfi_name_len;\n\t\tstruct {\n\t\t\tuint16_t alfi_old_name_len;\n\t\t\tuint16_t alfi_new_name_len;\n\t\t};\n\t};\n\tuint32_t alfi_value_len;\n\tuint32_t alfi_attr_filter;\n};\n\nstruct xfs_attri_log_item {\n\tstruct xfs_log_item attri_item;\n\tatomic_t attri_refcount;\n\tstruct xfs_attri_log_nameval *attri_nameval;\n\tstruct xfs_attri_log_format attri_format;\n};\n\nstruct xfs_attri_log_nameval {\n\tstruct kvec name;\n\tstruct kvec new_name;\n\tstruct kvec value;\n\tstruct kvec new_value;\n\trefcount_t refcount;\n};\n\nstruct xfs_attrlist {\n\t__s32 al_count;\n\t__s32 al_more;\n\t__s32 al_offset[0];\n};\n\nstruct xfs_attrlist_cursor {\n\t__u32 opaque[4];\n};\n\nstruct xfs_attrlist_ent {\n\t__u32 a_valuelen;\n\tchar a_name[0];\n};\n\nstruct xfs_iext_leaf;\n\nstruct xfs_iext_cursor {\n\tstruct xfs_iext_leaf *leaf;\n\tint pos;\n};\n\nstruct xfs_bmalloca {\n\tstruct xfs_trans *tp;\n\tstruct xfs_inode *ip;\n\tstruct xfs_bmbt_irec prev;\n\tstruct xfs_bmbt_irec got;\n\txfs_fileoff_t offset;\n\txfs_extlen_t length;\n\txfs_fsblock_t blkno;\n\tstruct xfs_btree_cur *cur;\n\tstruct xfs_iext_cursor icur;\n\tint nallocs;\n\tint logflags;\n\txfs_extlen_t total;\n\txfs_extlen_t minlen;\n\txfs_extlen_t minleft;\n\tbool eof;\n\tbool wasdel;\n\tbool aeof;\n\tbool conv;\n\tint datatype;\n\tuint32_t flags;\n};\n\nstruct xfs_group;\n\nstruct xfs_bmap_intent {\n\tstruct list_head bi_list;\n\tenum xfs_bmap_intent_type bi_type;\n\tint bi_whichfork;\n\tstruct xfs_inode *bi_owner;\n\tstruct xfs_group *bi_group;\n\tstruct xfs_bmbt_irec bi_bmap;\n};\n\ntypedef int (*xfs_bmap_query_range_fn)(struct xfs_btree_cur *, struct xfs_bmbt_irec *, void *);\n\nstruct xfs_bmap_query_range {\n\txfs_bmap_query_range_fn fn;\n\tvoid *priv;\n};\n\ntypedef struct xfs_bmbt_irec xfs_bmbt_irec_t;\n\nstruct xfs_bmbt_key {\n\t__be64 br_startoff;\n};\n\ntypedef struct xfs_bmbt_key xfs_bmbt_key_t;\n\ntypedef struct xfs_bmbt_key xfs_bmdr_key_t;\n\nstruct xfs_bmbt_rec {\n\t__be64 l0;\n\t__be64 l1;\n};\n\ntypedef struct xfs_bmbt_rec xfs_bmbt_rec_t;\n\ntypedef xfs_bmbt_rec_t xfs_bmdr_rec_t;\n\nstruct xfs_bmdr_block {\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n};\n\ntypedef struct xfs_bmdr_block xfs_bmdr_block_t;\n\nstruct xfs_bstime {\n\t__kernel_long_t tv_sec;\n\t__s32 tv_nsec;\n};\n\ntypedef struct xfs_bstime xfs_bstime_t;\n\nstruct xfs_bstat {\n\t__u64 bs_ino;\n\t__u16 bs_mode;\n\t__u16 bs_nlink;\n\t__u32 bs_uid;\n\t__u32 bs_gid;\n\t__u32 bs_rdev;\n\t__s32 bs_blksize;\n\t__s64 bs_size;\n\txfs_bstime_t bs_atime;\n\txfs_bstime_t bs_mtime;\n\txfs_bstime_t bs_ctime;\n\tint64_t bs_blocks;\n\t__u32 bs_xflags;\n\t__s32 bs_extsize;\n\t__s32 bs_extents;\n\t__u32 bs_gen;\n\t__u16 bs_projid_lo;\n\t__u16 bs_forkoff;\n\t__u16 bs_projid_hi;\n\tuint16_t bs_sick;\n\tuint16_t bs_checked;\n\tunsigned char bs_pad[2];\n\t__u32 bs_cowextsize;\n\t__u32 bs_dmevmask;\n\t__u16 bs_dmstate;\n\t__u16 bs_aextents;\n};\n\nstruct xfs_ibulk;\n\nstruct xfs_bulkstat;\n\ntypedef int (*bulkstat_one_fmt_pf)(struct xfs_ibulk *, const struct xfs_bulkstat *);\n\nstruct xfs_bstat_chunk {\n\tbulkstat_one_fmt_pf formatter;\n\tstruct xfs_ibulk *breq;\n\tstruct xfs_bulkstat *buf;\n};\n\nstruct xfs_btree_block;\n\ntypedef int (*xfs_btree_bload_get_records_fn)(struct xfs_btree_cur *, unsigned int, struct xfs_btree_block *, unsigned int, void *);\n\ntypedef int (*xfs_btree_bload_claim_block_fn)(struct xfs_btree_cur *, union xfs_btree_ptr *, void *);\n\ntypedef size_t (*xfs_btree_bload_iroot_size_fn)(struct xfs_btree_cur *, unsigned int, unsigned int, void *);\n\nstruct xfs_btree_bload {\n\txfs_btree_bload_get_records_fn get_records;\n\txfs_btree_bload_claim_block_fn claim_block;\n\txfs_btree_bload_iroot_size_fn iroot_size;\n\tuint64_t nr_records;\n\tint leaf_slack;\n\tint node_slack;\n\tuint64_t nr_blocks;\n\tunsigned int btree_height;\n\tuint16_t max_dirty;\n\tuint16_t nr_dirty;\n};\n\nstruct xfs_btree_block_shdr {\n\t__be32 bb_leftsib;\n\t__be32 bb_rightsib;\n\t__be64 bb_blkno;\n\t__be64 bb_lsn;\n\tuuid_t bb_uuid;\n\t__be32 bb_owner;\n\t__le32 bb_crc;\n};\n\nstruct xfs_btree_block_lhdr {\n\t__be64 bb_leftsib;\n\t__be64 bb_rightsib;\n\t__be64 bb_blkno;\n\t__be64 bb_lsn;\n\tuuid_t bb_uuid;\n\t__be64 bb_owner;\n\t__le32 bb_crc;\n\t__be32 bb_pad;\n};\n\nstruct xfs_btree_block {\n\t__be32 bb_magic;\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n\tunion {\n\t\tstruct xfs_btree_block_shdr s;\n\t\tstruct xfs_btree_block_lhdr l;\n\t} bb_u;\n};\n\nstruct xfs_btree_block_change_owner_info {\n\tuint64_t new_owner;\n\tstruct list_head *buffer_list;\n};\n\nstruct xfs_inobt_rec_incore {\n\txfs_agino_t ir_startino;\n\tuint16_t ir_holemask;\n\tuint8_t ir_count;\n\tuint8_t ir_freecount;\n\txfs_inofree_t ir_free;\n};\n\nstruct xfs_rmap_irec {\n\txfs_agblock_t rm_startblock;\n\txfs_extlen_t rm_blockcount;\n\tuint64_t rm_owner;\n\tuint64_t rm_offset;\n\tunsigned int rm_flags;\n};\n\nstruct xfs_refcount_irec {\n\txfs_agblock_t rc_startblock;\n\txfs_extlen_t rc_blockcount;\n\txfs_nlink_t rc_refcount;\n\tenum xfs_refc_domain rc_domain;\n};\n\nunion xfs_btree_irec {\n\tstruct xfs_alloc_rec_incore a;\n\tstruct xfs_bmbt_irec b;\n\tstruct xfs_inobt_rec_incore i;\n\tstruct xfs_rmap_irec r;\n\tstruct xfs_refcount_irec rc;\n};\n\nstruct xfs_btree_level {\n\tstruct xfs_buf *bp;\n\tuint16_t ptr;\n\tuint16_t ra;\n};\n\nstruct xfs_btree_cur {\n\tstruct xfs_trans *bc_tp;\n\tstruct xfs_mount *bc_mp;\n\tconst struct xfs_btree_ops *bc_ops;\n\tstruct kmem_cache *bc_cache;\n\tunsigned int bc_flags;\n\tunion xfs_btree_irec bc_rec;\n\tuint8_t bc_nlevels;\n\tuint8_t bc_maxlevels;\n\tstruct xfs_group *bc_group;\n\tunion {\n\t\tstruct {\n\t\t\tstruct xfs_inode *ip;\n\t\t\tshort int forksize;\n\t\t\tchar whichfork;\n\t\t\tstruct xbtree_ifakeroot *ifake;\n\t\t} bc_ino;\n\t\tstruct {\n\t\t\tstruct xfs_buf *agbp;\n\t\t\tstruct xbtree_afakeroot *afake;\n\t\t} bc_ag;\n\t\tstruct {\n\t\t\tstruct xfbtree *xfbtree;\n\t\t} bc_mem;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tint allocated;\n\t\t} bc_bmap;\n\t\tstruct {\n\t\t\tunsigned int nr_ops;\n\t\t\tunsigned int shape_changes;\n\t\t} bc_refc;\n\t};\n\tstruct xfs_btree_level bc_levels[0];\n};\n\nstruct xfs_inobt_key {\n\t__be32 ir_startino;\n};\n\nstruct xfs_rmap_key {\n\t__be32 rm_startblock;\n\t__be64 rm_owner;\n\t__be64 rm_offset;\n} __attribute__((packed));\n\nstruct xfs_refcount_key {\n\t__be32 rc_startblock;\n};\n\nunion xfs_btree_key {\n\tstruct xfs_bmbt_key bmbt;\n\txfs_bmdr_key_t bmbr;\n\txfs_alloc_key_t alloc;\n\tstruct xfs_inobt_key inobt;\n\tstruct xfs_rmap_key rmap;\n\tstruct xfs_rmap_key __rmap_bigkey[2];\n\tstruct xfs_refcount_key refc;\n};\n\nstruct xfs_btree_has_records {\n\tunion xfs_btree_key start_key;\n\tunion xfs_btree_key end_key;\n\tconst union xfs_btree_key *key_mask;\n\tunion xfs_btree_key high_key;\n\tenum xbtree_recpacking outcome;\n};\n\nunion xfs_btree_rec;\n\nstruct xfs_btree_ops {\n\tconst char *name;\n\tenum xfs_btree_type type;\n\tunsigned int geom_flags;\n\tsize_t key_len;\n\tsize_t ptr_len;\n\tsize_t rec_len;\n\tunsigned int lru_refs;\n\tunsigned int statoff;\n\tunsigned int sick_mask;\n\tstruct xfs_btree_cur * (*dup_cursor)(struct xfs_btree_cur *);\n\tvoid (*update_cursor)(struct xfs_btree_cur *, struct xfs_btree_cur *);\n\tvoid (*set_root)(struct xfs_btree_cur *, const union xfs_btree_ptr *, int);\n\tint (*alloc_block)(struct xfs_btree_cur *, const union xfs_btree_ptr *, union xfs_btree_ptr *, int *);\n\tint (*free_block)(struct xfs_btree_cur *, struct xfs_buf *);\n\tint (*get_minrecs)(struct xfs_btree_cur *, int);\n\tint (*get_maxrecs)(struct xfs_btree_cur *, int);\n\tint (*get_dmaxrecs)(struct xfs_btree_cur *, int);\n\tvoid (*init_key_from_rec)(union xfs_btree_key *, const union xfs_btree_rec *);\n\tvoid (*init_rec_from_cur)(struct xfs_btree_cur *, union xfs_btree_rec *);\n\tvoid (*init_ptr_from_cur)(struct xfs_btree_cur *, union xfs_btree_ptr *);\n\tvoid (*init_high_key_from_rec)(union xfs_btree_key *, const union xfs_btree_rec *);\n\tint (*cmp_key_with_cur)(struct xfs_btree_cur *, const union xfs_btree_key *);\n\tint (*cmp_two_keys)(struct xfs_btree_cur *, const union xfs_btree_key *, const union xfs_btree_key *, const union xfs_btree_key *);\n\tconst struct xfs_buf_ops *buf_ops;\n\tint (*keys_inorder)(struct xfs_btree_cur *, const union xfs_btree_key *, const union xfs_btree_key *);\n\tint (*recs_inorder)(struct xfs_btree_cur *, const union xfs_btree_rec *, const union xfs_btree_rec *);\n\tenum xbtree_key_contig (*keys_contiguous)(struct xfs_btree_cur *, const union xfs_btree_key *, const union xfs_btree_key *, const union xfs_btree_key *);\n\tstruct xfs_btree_block * (*broot_realloc)(struct xfs_btree_cur *, unsigned int);\n};\n\nstruct xfs_inobt_rec {\n\t__be32 ir_startino;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ir_freecount;\n\t\t} f;\n\t\tstruct {\n\t\t\t__be16 ir_holemask;\n\t\t\t__u8 ir_count;\n\t\t\t__u8 ir_freecount;\n\t\t} sp;\n\t} ir_u;\n\t__be64 ir_free;\n};\n\nstruct xfs_rmap_rec {\n\t__be32 rm_startblock;\n\t__be32 rm_blockcount;\n\t__be64 rm_owner;\n\t__be64 rm_offset;\n};\n\nstruct xfs_refcount_rec {\n\t__be32 rc_startblock;\n\t__be32 rc_blockcount;\n\t__be32 rc_refcount;\n};\n\nunion xfs_btree_rec {\n\tstruct xfs_bmbt_rec bmbt;\n\txfs_bmdr_rec_t bmbr;\n\tstruct xfs_alloc_rec alloc;\n\tstruct xfs_inobt_rec inobt;\n\tstruct xfs_rmap_rec rmap;\n\tstruct xfs_refcount_rec refc;\n};\n\nstruct xfs_btree_split_args {\n\tstruct xfs_btree_cur *cur;\n\tint level;\n\tunion xfs_btree_ptr *ptrp;\n\tunion xfs_btree_key *key;\n\tstruct xfs_btree_cur **curp;\n\tint *stat;\n\tint result;\n\tbool kswapd;\n\tstruct completion *done;\n\tstruct work_struct work;\n};\n\nstruct xfs_bud_log_format {\n\tuint16_t bud_type;\n\tuint16_t bud_size;\n\tuint32_t __pad;\n\tuint64_t bud_bui_id;\n};\n\nstruct xfs_bui_log_item;\n\nstruct xfs_bud_log_item {\n\tstruct xfs_log_item bud_item;\n\tstruct xfs_bui_log_item *bud_buip;\n\tstruct xfs_bud_log_format bud_format;\n};\n\nstruct xfs_buf_map {\n\txfs_daddr_t bm_bn;\n\tint bm_len;\n\tunsigned int bm_flags;\n};\n\nstruct xfs_buf_log_item;\n\nstruct xfs_buf {\n\tstruct rhash_head b_rhash_head;\n\txfs_daddr_t b_rhash_key;\n\tint b_length;\n\tunsigned int b_hold;\n\tatomic_t b_lru_ref;\n\txfs_buf_flags_t b_flags;\n\tstruct semaphore b_sema;\n\tstruct list_head b_lru;\n\tspinlock_t b_lock;\n\tunsigned int b_state;\n\twait_queue_head_t b_waiters;\n\tstruct list_head b_list;\n\tstruct xfs_perag *b_pag;\n\tstruct xfs_mount *b_mount;\n\tstruct xfs_buftarg *b_target;\n\tvoid *b_addr;\n\tstruct work_struct b_ioend_work;\n\tstruct completion b_iowait;\n\tstruct xfs_buf_log_item *b_log_item;\n\tstruct list_head b_li_list;\n\tstruct xfs_trans *b_transp;\n\tstruct xfs_buf_map *b_maps;\n\tstruct xfs_buf_map __b_map;\n\tint b_map_count;\n\tatomic_t b_pin_count;\n\tint b_error;\n\tvoid (*b_iodone)(struct xfs_buf *);\n\tint b_retries;\n\tlong unsigned int b_first_retry_time;\n\tint b_last_error;\n\tconst struct xfs_buf_ops *b_ops;\n\tstruct callback_head b_rcu;\n};\n\nstruct xfs_buf_cache {\n\tstruct rhashtable bc_hash;\n};\n\nstruct xfs_buf_cancel {\n\txfs_daddr_t bc_blkno;\n\tuint bc_len;\n\tint bc_refcount;\n\tstruct list_head bc_list;\n};\n\nstruct xfs_buf_log_format {\n\tshort unsigned int blf_type;\n\tshort unsigned int blf_size;\n\tshort unsigned int blf_flags;\n\tshort unsigned int blf_len;\n\tint64_t blf_blkno;\n\tunsigned int blf_map_size;\n\tunsigned int blf_data_map[17];\n};\n\nstruct xfs_buf_log_item {\n\tstruct xfs_log_item bli_item;\n\tstruct xfs_buf *bli_buf;\n\tunsigned int bli_flags;\n\tunsigned int bli_recur;\n\tatomic_t bli_refcount;\n\tint bli_format_count;\n\tstruct xfs_buf_log_format *bli_formats;\n\tstruct xfs_buf_log_format __bli_format;\n};\n\nstruct xfs_buf_ops {\n\tchar *name;\n\tunion {\n\t\t__be32 magic[2];\n\t\t__be16 magic16[2];\n\t};\n\tvoid (*verify_read)(struct xfs_buf *);\n\tvoid (*verify_write)(struct xfs_buf *);\n\txfs_failaddr_t (*verify_struct)(struct xfs_buf *);\n};\n\nstruct xfs_buftarg {\n\tdev_t bt_dev;\n\tstruct block_device *bt_bdev;\n\tstruct dax_device *bt_daxdev;\n\tstruct file *bt_file;\n\tu64 bt_dax_part_off;\n\tstruct xfs_mount *bt_mount;\n\tunsigned int bt_meta_sectorsize;\n\tsize_t bt_meta_sectormask;\n\tsize_t bt_logical_sectorsize;\n\tsize_t bt_logical_sectormask;\n\txfs_daddr_t bt_nr_sectors;\n\tstruct shrinker *bt_shrinker;\n\tstruct list_lru bt_lru;\n\tstruct percpu_counter bt_readahead_count;\n\tstruct ratelimit_state bt_ioerror_rl;\n\tunsigned int bt_awu_min;\n\tunsigned int bt_awu_max;\n\tstruct xfs_buf_cache bt_cache[0];\n};\n\nstruct xfs_map_extent {\n\tuint64_t me_owner;\n\tuint64_t me_startblock;\n\tuint64_t me_startoff;\n\tuint32_t me_len;\n\tuint32_t me_flags;\n};\n\nstruct xfs_bui_log_format {\n\tuint16_t bui_type;\n\tuint16_t bui_size;\n\tuint32_t bui_nextents;\n\tuint64_t bui_id;\n\tstruct xfs_map_extent bui_extents[0];\n};\n\nstruct xfs_bui_log_item {\n\tstruct xfs_log_item bui_item;\n\tatomic_t bui_refcount;\n\tatomic_t bui_next_extent;\n\tstruct xfs_bui_log_format bui_format;\n};\n\nstruct xfs_bulk_ireq {\n\tuint64_t ino;\n\tuint32_t flags;\n\tuint32_t icount;\n\tuint32_t ocount;\n\tuint32_t agno;\n\tuint64_t reserved[5];\n};\n\nstruct xfs_bulkstat {\n\tuint64_t bs_ino;\n\tuint64_t bs_size;\n\tuint64_t bs_blocks;\n\tuint64_t bs_xflags;\n\tint64_t bs_atime;\n\tint64_t bs_mtime;\n\tint64_t bs_ctime;\n\tint64_t bs_btime;\n\tuint32_t bs_gen;\n\tuint32_t bs_uid;\n\tuint32_t bs_gid;\n\tuint32_t bs_projectid;\n\tuint32_t bs_atime_nsec;\n\tuint32_t bs_mtime_nsec;\n\tuint32_t bs_ctime_nsec;\n\tuint32_t bs_btime_nsec;\n\tuint32_t bs_blksize;\n\tuint32_t bs_rdev;\n\tuint32_t bs_cowextsize_blks;\n\tuint32_t bs_extsize_blks;\n\tuint32_t bs_nlink;\n\tuint32_t bs_extents;\n\tuint32_t bs_aextents;\n\tuint16_t bs_version;\n\tuint16_t bs_forkoff;\n\tuint16_t bs_sick;\n\tuint16_t bs_checked;\n\tuint16_t bs_mode;\n\tuint16_t bs_pad2;\n\tuint64_t bs_extents64;\n\tuint64_t bs_pad[6];\n};\n\nstruct xfs_bulkstat_req {\n\tstruct xfs_bulk_ireq hdr;\n\tstruct xfs_bulkstat bulkstat[0];\n};\n\nstruct xfs_busy_extents {\n\tstruct list_head extent_list;\n\tstruct work_struct endio_work;\n\tvoid *owner;\n};\n\nstruct xfs_cil_ctx;\n\nstruct xfs_cil {\n\tstruct xlog *xc_log;\n\tlong unsigned int xc_flags;\n\tatomic_t xc_iclog_hdrs;\n\tstruct workqueue_struct *xc_push_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rw_semaphore xc_ctx_lock;\n\tstruct xfs_cil_ctx *xc_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t xc_push_lock;\n\txfs_csn_t xc_push_seq;\n\tbool xc_push_commit_stable;\n\tstruct list_head xc_committing;\n\twait_queue_head_t xc_commit_wait;\n\twait_queue_head_t xc_start_wait;\n\txfs_csn_t xc_current_sequence;\n\twait_queue_head_t xc_push_wait;\n\tvoid *xc_pcp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xlog_in_core;\n\nstruct xlog_ticket;\n\nstruct xfs_cil_ctx {\n\tstruct xfs_cil *cil;\n\txfs_csn_t sequence;\n\txfs_lsn_t start_lsn;\n\txfs_lsn_t commit_lsn;\n\tstruct xlog_in_core *commit_iclog;\n\tstruct xlog_ticket *ticket;\n\tatomic_t space_used;\n\tstruct xfs_busy_extents busy_extents;\n\tstruct list_head log_items;\n\tstruct list_head lv_chain;\n\tstruct list_head iclog_entry;\n\tstruct list_head committing;\n\tstruct work_struct push_work;\n\tatomic_t order_id;\n\tstruct cpumask cil_pcpmask;\n};\n\nstruct xfs_commit_range {\n\t__s32 file1_fd;\n\t__u32 pad;\n\t__u64 file1_offset;\n\t__u64 file2_offset;\n\t__u64 length;\n\t__u64 flags;\n\t__u64 file2_freshness[6];\n};\n\nstruct xfs_fsid {\n\t__u32 val[2];\n};\n\ntypedef struct xfs_fsid xfs_fsid_t;\n\nstruct xfs_commit_range_fresh {\n\txfs_fsid_t fsid;\n\t__u64 file2_ino;\n\t__s64 file2_mtime;\n\t__s64 file2_ctime;\n\t__s32 file2_mtime_nsec;\n\t__s32 file2_ctime_nsec;\n\t__u32 file2_gen;\n\t__u32 magic;\n};\n\nstruct xfs_cud_log_format {\n\tuint16_t cud_type;\n\tuint16_t cud_size;\n\tuint32_t __pad;\n\tuint64_t cud_cui_id;\n};\n\nstruct xfs_cui_log_item;\n\nstruct xfs_cud_log_item {\n\tstruct xfs_log_item cud_item;\n\tstruct xfs_cui_log_item *cud_cuip;\n\tstruct xfs_cud_log_format cud_format;\n};\n\nstruct xfs_phys_extent {\n\tuint64_t pe_startblock;\n\tuint32_t pe_len;\n\tuint32_t pe_flags;\n};\n\nstruct xfs_cui_log_format {\n\tuint16_t cui_type;\n\tuint16_t cui_size;\n\tuint32_t cui_nextents;\n\tuint64_t cui_id;\n\tstruct xfs_phys_extent cui_extents[0];\n};\n\nstruct xfs_cui_log_item {\n\tstruct xfs_log_item cui_item;\n\tatomic_t cui_refcount;\n\tatomic_t cui_next_extent;\n\tstruct xfs_cui_log_format cui_format;\n};\n\nstruct xfs_da_node_entry;\n\nstruct xfs_da3_icnode_hdr {\n\tuint32_t forw;\n\tuint32_t back;\n\tuint16_t magic;\n\tuint16_t count;\n\tuint16_t level;\n\tstruct xfs_da_node_entry *btree;\n};\n\nstruct xfs_da3_node_hdr {\n\tstruct xfs_da3_blkinfo info;\n\t__be16 __count;\n\t__be16 __level;\n\t__be32 __pad32;\n};\n\nstruct xfs_da_node_entry {\n\t__be32 hashval;\n\t__be32 before;\n};\n\nstruct xfs_da3_intnode {\n\tstruct xfs_da3_node_hdr hdr;\n\tstruct xfs_da_node_entry __btree[0];\n};\n\nstruct xfs_da_geometry;\n\nstruct xfs_da_args {\n\tstruct xfs_da_geometry *geo;\n\tconst uint8_t *name;\n\tconst uint8_t *new_name;\n\tvoid *value;\n\tvoid *new_value;\n\tstruct xfs_inode *dp;\n\tstruct xfs_trans *trans;\n\txfs_ino_t inumber;\n\txfs_ino_t owner;\n\tint valuelen;\n\tint new_valuelen;\n\tuint8_t filetype;\n\tuint8_t op_flags;\n\tuint8_t attr_filter;\n\tshort int namelen;\n\tshort int new_namelen;\n\txfs_dahash_t hashval;\n\txfs_extlen_t total;\n\tint whichfork;\n\txfs_dablk_t blkno;\n\tint index;\n\txfs_dablk_t rmtblkno;\n\tint rmtblkcnt;\n\tint rmtvaluelen;\n\txfs_dablk_t blkno2;\n\tint index2;\n\txfs_dablk_t rmtblkno2;\n\tint rmtblkcnt2;\n\tint rmtvaluelen2;\n\tenum xfs_dacmp cmpresult;\n};\n\ntypedef struct xfs_da_args xfs_da_args_t;\n\nstruct xfs_da_geometry {\n\tunsigned int blksize;\n\tunsigned int fsbcount;\n\tuint8_t fsblog;\n\tuint8_t blklog;\n\tunsigned int node_hdr_size;\n\tunsigned int node_ents;\n\tunsigned int magicpct;\n\txfs_dablk_t datablk;\n\tunsigned int leaf_hdr_size;\n\tunsigned int leaf_max_ents;\n\txfs_dablk_t leafblk;\n\tunsigned int free_hdr_size;\n\tunsigned int free_max_bests;\n\txfs_dablk_t freeblk;\n\txfs_extnum_t max_extents;\n\txfs_dir2_data_aoff_t data_first_offset;\n\tsize_t data_entry_offset;\n};\n\nstruct xfs_da_node_hdr {\n\tstruct xfs_da_blkinfo info;\n\t__be16 __count;\n\t__be16 __level;\n};\n\nstruct xfs_da_intnode {\n\tstruct xfs_da_node_hdr hdr;\n\tstruct xfs_da_node_entry __btree[0];\n};\n\ntypedef struct xfs_da_intnode xfs_da_intnode_t;\n\nstruct xfs_da_state_blk {\n\tstruct xfs_buf *bp;\n\txfs_dablk_t blkno;\n\txfs_daddr_t disk_blkno;\n\tint index;\n\txfs_dahash_t hashval;\n\tint magic;\n};\n\ntypedef struct xfs_da_state_blk xfs_da_state_blk_t;\n\nstruct xfs_da_state_path {\n\tint active;\n\txfs_da_state_blk_t blk[5];\n};\n\ntypedef struct xfs_da_state_path xfs_da_state_path_t;\n\nstruct xfs_da_state {\n\txfs_da_args_t *args;\n\tstruct xfs_mount *mp;\n\txfs_da_state_path_t path;\n\txfs_da_state_path_t altpath;\n\tunsigned char inleaf;\n\tunsigned char extravalid;\n\tunsigned char extraafter;\n\txfs_da_state_blk_t extrablk;\n};\n\ntypedef struct xfs_da_state xfs_da_state_t;\n\nstruct xfs_quota_limits {\n\txfs_qcnt_t hard;\n\txfs_qcnt_t soft;\n\ttime64_t time;\n};\n\nstruct xfs_def_quota {\n\tstruct xfs_quota_limits blk;\n\tstruct xfs_quota_limits ino;\n\tstruct xfs_quota_limits rtb;\n};\n\nstruct xfs_defer_resources {\n\tstruct xfs_buf *dr_bp[2];\n\tstruct xfs_inode *dr_ip[5];\n\tshort unsigned int dr_bufs;\n\tshort unsigned int dr_ordered;\n\tshort unsigned int dr_inos;\n};\n\nstruct xfs_defer_capture {\n\tstruct list_head dfc_list;\n\tstruct list_head dfc_dfops;\n\tunsigned int dfc_tpflags;\n\tunsigned int dfc_blkres;\n\tunsigned int dfc_rtxres;\n\tunsigned int dfc_logres;\n\tstruct xfs_defer_resources dfc_held;\n};\n\nstruct xfs_defer_drain {};\n\nstruct xfs_defer_op_type {\n\tconst char *name;\n\tunsigned int max_items;\n\tstruct xfs_log_item * (*create_intent)(struct xfs_trans *, struct list_head *, unsigned int, bool);\n\tvoid (*abort_intent)(struct xfs_log_item *);\n\tstruct xfs_log_item * (*create_done)(struct xfs_trans *, struct xfs_log_item *, unsigned int);\n\tint (*finish_item)(struct xfs_trans *, struct xfs_log_item *, struct list_head *, struct xfs_btree_cur **);\n\tvoid (*finish_cleanup)(struct xfs_trans *, struct xfs_btree_cur *, int);\n\tvoid (*cancel_item)(struct list_head *);\n\tint (*recover_work)(struct xfs_defer_pending *, struct list_head *);\n\tstruct xfs_log_item * (*relog_intent)(struct xfs_trans *, struct xfs_log_item *, struct xfs_log_item *);\n};\n\nstruct xfs_defer_pending {\n\tstruct list_head dfp_list;\n\tstruct list_head dfp_work;\n\tstruct xfs_log_item *dfp_intent;\n\tstruct xfs_log_item *dfp_done;\n\tconst struct xfs_defer_op_type *dfp_ops;\n\tunsigned int dfp_count;\n\tunsigned int dfp_flags;\n};\n\nstruct xfs_dinode {\n\t__be16 di_magic;\n\t__be16 di_mode;\n\t__u8 di_version;\n\t__u8 di_format;\n\t__be16 di_metatype;\n\t__be32 di_uid;\n\t__be32 di_gid;\n\t__be32 di_nlink;\n\t__be16 di_projid_lo;\n\t__be16 di_projid_hi;\n\tunion {\n\t\t__be64 di_big_nextents;\n\t\t__be64 di_v3_pad;\n\t\tstruct {\n\t\t\t__u8 di_v2_pad[6];\n\t\t\t__be16 di_flushiter;\n\t\t};\n\t};\n\txfs_timestamp_t di_atime;\n\txfs_timestamp_t di_mtime;\n\txfs_timestamp_t di_ctime;\n\t__be64 di_size;\n\t__be64 di_nblocks;\n\t__be32 di_extsize;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 di_nextents;\n\t\t\t__be16 di_anextents;\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__be32 di_big_anextents;\n\t\t\t__be16 di_nrext64_pad;\n\t\t} __attribute__((packed));\n\t};\n\t__u8 di_forkoff;\n\t__s8 di_aformat;\n\t__be32 di_dmevmask;\n\t__be16 di_dmstate;\n\t__be16 di_flags;\n\t__be32 di_gen;\n\t__be32 di_next_unlinked;\n\t__le32 di_crc;\n\t__be64 di_changecount;\n\t__be64 di_lsn;\n\t__be64 di_flags2;\n\tunion {\n\t\t__be32 di_cowextsize;\n\t\t__be32 di_used_blocks;\n\t};\n\t__u8 di_pad2[12];\n\txfs_timestamp_t di_crtime;\n\t__be64 di_ino;\n\tuuid_t di_uuid;\n};\n\nstruct xfs_dir2_block_tail {\n\t__be32 count;\n\t__be32 stale;\n};\n\ntypedef struct xfs_dir2_block_tail xfs_dir2_block_tail_t;\n\nstruct xfs_dir2_data_entry {\n\t__be64 inumber;\n\t__u8 namelen;\n\t__u8 name[0];\n};\n\ntypedef struct xfs_dir2_data_entry xfs_dir2_data_entry_t;\n\nstruct xfs_dir2_data_free {\n\t__be16 offset;\n\t__be16 length;\n};\n\ntypedef struct xfs_dir2_data_free xfs_dir2_data_free_t;\n\nstruct xfs_dir2_data_hdr {\n\t__be32 magic;\n\txfs_dir2_data_free_t bestfree[3];\n};\n\ntypedef struct xfs_dir2_data_hdr xfs_dir2_data_hdr_t;\n\nstruct xfs_dir2_data_unused {\n\t__be16 freetag;\n\t__be16 length;\n\t__be16 tag;\n};\n\ntypedef struct xfs_dir2_data_unused xfs_dir2_data_unused_t;\n\nstruct xfs_dir2_free_hdr {\n\t__be32 magic;\n\t__be32 firstdb;\n\t__be32 nvalid;\n\t__be32 nused;\n};\n\ntypedef struct xfs_dir2_free_hdr xfs_dir2_free_hdr_t;\n\nstruct xfs_dir2_free {\n\txfs_dir2_free_hdr_t hdr;\n\t__be16 bests[0];\n};\n\ntypedef struct xfs_dir2_free xfs_dir2_free_t;\n\nstruct xfs_dir2_leaf_hdr {\n\txfs_da_blkinfo_t info;\n\t__be16 count;\n\t__be16 stale;\n};\n\ntypedef struct xfs_dir2_leaf_hdr xfs_dir2_leaf_hdr_t;\n\nstruct xfs_dir2_leaf_entry {\n\t__be32 hashval;\n\t__be32 address;\n};\n\ntypedef struct xfs_dir2_leaf_entry xfs_dir2_leaf_entry_t;\n\nstruct xfs_dir2_leaf {\n\txfs_dir2_leaf_hdr_t hdr;\n\txfs_dir2_leaf_entry_t __ents[0];\n};\n\ntypedef struct xfs_dir2_leaf xfs_dir2_leaf_t;\n\nstruct xfs_dir2_leaf_tail {\n\t__be32 bestcount;\n};\n\ntypedef struct xfs_dir2_leaf_tail xfs_dir2_leaf_tail_t;\n\nstruct xfs_dir2_sf_entry {\n\t__u8 namelen;\n\t__u8 offset[2];\n\t__u8 name[0];\n};\n\ntypedef struct xfs_dir2_sf_entry xfs_dir2_sf_entry_t;\n\nstruct xfs_dir2_sf_hdr {\n\tuint8_t count;\n\tuint8_t i8count;\n\tuint8_t parent[8];\n};\n\ntypedef struct xfs_dir2_sf_hdr xfs_dir2_sf_hdr_t;\n\nstruct xfs_dir3_blk_hdr {\n\t__be32 magic;\n\t__be32 crc;\n\t__be64 blkno;\n\t__be64 lsn;\n\tuuid_t uuid;\n\t__be64 owner;\n};\n\nstruct xfs_dir3_data_hdr {\n\tstruct xfs_dir3_blk_hdr hdr;\n\txfs_dir2_data_free_t best_free[3];\n\t__be32 pad;\n};\n\nstruct xfs_dir3_free_hdr {\n\tstruct xfs_dir3_blk_hdr hdr;\n\t__be32 firstdb;\n\t__be32 nvalid;\n\t__be32 nused;\n\t__be32 pad;\n};\n\nstruct xfs_dir3_free {\n\tstruct xfs_dir3_free_hdr hdr;\n\t__be16 bests[0];\n};\n\nstruct xfs_dir3_icfree_hdr {\n\tuint32_t magic;\n\tuint32_t firstdb;\n\tuint32_t nvalid;\n\tuint32_t nused;\n\t__be16 *bests;\n};\n\nstruct xfs_dir3_icleaf_hdr {\n\tuint32_t forw;\n\tuint32_t back;\n\tuint16_t magic;\n\tuint16_t count;\n\tuint16_t stale;\n\tstruct xfs_dir2_leaf_entry *ents;\n};\n\nstruct xfs_dir3_leaf_hdr {\n\tstruct xfs_da3_blkinfo info;\n\t__be16 count;\n\t__be16 stale;\n\t__be32 pad;\n};\n\nstruct xfs_dir3_leaf {\n\tstruct xfs_dir3_leaf_hdr hdr;\n\tstruct xfs_dir2_leaf_entry __ents[0];\n};\n\nstruct xfs_name;\n\nstruct xfs_parent_args;\n\nstruct xfs_dir_update {\n\tstruct xfs_inode *dp;\n\tconst struct xfs_name *name;\n\tstruct xfs_inode *ip;\n\tstruct xfs_parent_args *ppargs;\n};\n\nstruct xfs_disk_dquot {\n\t__be16 d_magic;\n\t__u8 d_version;\n\t__u8 d_type;\n\t__be32 d_id;\n\t__be64 d_blk_hardlimit;\n\t__be64 d_blk_softlimit;\n\t__be64 d_ino_hardlimit;\n\t__be64 d_ino_softlimit;\n\t__be64 d_bcount;\n\t__be64 d_icount;\n\t__be32 d_itimer;\n\t__be32 d_btimer;\n\t__be16 d_iwarns;\n\t__be16 d_bwarns;\n\t__be32 d_pad0;\n\t__be64 d_rtb_hardlimit;\n\t__be64 d_rtb_softlimit;\n\t__be64 d_rtbcount;\n\t__be32 d_rtbtimer;\n\t__be16 d_rtbwarns;\n\t__be16 d_pad;\n};\n\nstruct xfs_dq_logformat {\n\tuint16_t qlf_type;\n\tuint16_t qlf_size;\n\txfs_dqid_t qlf_id;\n\tint64_t qlf_blkno;\n\tint32_t qlf_len;\n\tuint32_t qlf_boffset;\n};\n\nstruct xfs_dquot;\n\nstruct xfs_dq_logitem {\n\tstruct xfs_log_item qli_item;\n\tstruct xfs_dquot *qli_dquot;\n\txfs_lsn_t qli_flush_lsn;\n\tspinlock_t qli_lock;\n\tbool qli_dirty;\n};\n\nstruct xfs_dqblk {\n\tstruct xfs_disk_dquot dd_diskdq;\n\tchar dd_fill[4];\n\t__be32 dd_crc;\n\t__be64 dd_lsn;\n\tuuid_t dd_uuid;\n};\n\nstruct xfs_dqtrx {\n\tstruct xfs_dquot *qt_dquot;\n\tuint64_t qt_blk_res;\n\tint64_t qt_bcount_delta;\n\tint64_t qt_delbcnt_delta;\n\tuint64_t qt_rtblk_res;\n\tuint64_t qt_rtblk_res_used;\n\tint64_t qt_rtbcount_delta;\n\tint64_t qt_delrtb_delta;\n\tuint64_t qt_ino_res;\n\tuint64_t qt_ino_res_used;\n\tint64_t qt_icount_delta;\n};\n\nstruct xfs_dquot_res {\n\txfs_qcnt_t reserved;\n\txfs_qcnt_t count;\n\txfs_qcnt_t hardlimit;\n\txfs_qcnt_t softlimit;\n\ttime64_t timer;\n};\n\nstruct xfs_dquot_pre {\n\txfs_qcnt_t q_prealloc_lo_wmark;\n\txfs_qcnt_t q_prealloc_hi_wmark;\n\tint64_t q_low_space[3];\n};\n\nstruct xfs_dquot {\n\tstruct list_head q_lru;\n\tstruct xfs_mount *q_mount;\n\txfs_dqtype_t q_type;\n\tuint16_t q_flags;\n\txfs_dqid_t q_id;\n\tstruct lockref q_lockref;\n\tint q_bufoffset;\n\txfs_daddr_t q_blkno;\n\txfs_fileoff_t q_fileoffset;\n\tstruct xfs_dquot_res q_blk;\n\tstruct xfs_dquot_res q_ino;\n\tstruct xfs_dquot_res q_rtb;\n\tstruct xfs_dq_logitem q_logitem;\n\tstruct xfs_dquot_pre q_blk_prealloc;\n\tstruct xfs_dquot_pre q_rtb_prealloc;\n\tstruct mutex q_qlock;\n\tstruct completion q_flush;\n\tatomic_t q_pincount;\n\tstruct wait_queue_head q_pinwait;\n};\n\nstruct xfs_dquot_acct {\n\tstruct xfs_dqtrx dqs[15];\n};\n\nstruct xfs_dsb {\n\t__be32 sb_magicnum;\n\t__be32 sb_blocksize;\n\t__be64 sb_dblocks;\n\t__be64 sb_rblocks;\n\t__be64 sb_rextents;\n\tuuid_t sb_uuid;\n\t__be64 sb_logstart;\n\t__be64 sb_rootino;\n\t__be64 sb_rbmino;\n\t__be64 sb_rsumino;\n\t__be32 sb_rextsize;\n\t__be32 sb_agblocks;\n\t__be32 sb_agcount;\n\t__be32 sb_rbmblocks;\n\t__be32 sb_logblocks;\n\t__be16 sb_versionnum;\n\t__be16 sb_sectsize;\n\t__be16 sb_inodesize;\n\t__be16 sb_inopblock;\n\tchar sb_fname[12];\n\t__u8 sb_blocklog;\n\t__u8 sb_sectlog;\n\t__u8 sb_inodelog;\n\t__u8 sb_inopblog;\n\t__u8 sb_agblklog;\n\t__u8 sb_rextslog;\n\t__u8 sb_inprogress;\n\t__u8 sb_imax_pct;\n\t__be64 sb_icount;\n\t__be64 sb_ifree;\n\t__be64 sb_fdblocks;\n\t__be64 sb_frextents;\n\t__be64 sb_uquotino;\n\t__be64 sb_gquotino;\n\t__be16 sb_qflags;\n\t__u8 sb_flags;\n\t__u8 sb_shared_vn;\n\t__be32 sb_inoalignmt;\n\t__be32 sb_unit;\n\t__be32 sb_width;\n\t__u8 sb_dirblklog;\n\t__u8 sb_logsectlog;\n\t__be16 sb_logsectsize;\n\t__be32 sb_logsunit;\n\t__be32 sb_features2;\n\t__be32 sb_bad_features2;\n\t__be32 sb_features_compat;\n\t__be32 sb_features_ro_compat;\n\t__be32 sb_features_incompat;\n\t__be32 sb_features_log_incompat;\n\t__le32 sb_crc;\n\t__be32 sb_spino_align;\n\t__be64 sb_pquotino;\n\t__be64 sb_lsn;\n\tuuid_t sb_meta_uuid;\n\t__be64 sb_metadirino;\n\t__be32 sb_rgcount;\n\t__be32 sb_rgextents;\n\t__u8 sb_rgblklog;\n\t__u8 sb_pad[7];\n\t__be64 sb_rtstart;\n\t__be64 sb_rtreserved;\n};\n\nstruct xfs_dsymlink_hdr {\n\t__be32 sl_magic;\n\t__be32 sl_offset;\n\t__be32 sl_bytes;\n\t__be32 sl_crc;\n\tuuid_t sl_uuid;\n\t__be64 sl_owner;\n\t__be64 sl_blkno;\n\t__be64 sl_lsn;\n};\n\nstruct xfs_extent {\n\txfs_fsblock_t ext_start;\n\txfs_extlen_t ext_len;\n};\n\nstruct xfs_efd_log_format {\n\tuint16_t efd_type;\n\tuint16_t efd_size;\n\tuint32_t efd_nextents;\n\tuint64_t efd_efi_id;\n\tstruct xfs_extent efd_extents[0];\n};\n\nstruct xfs_efi_log_item;\n\nstruct xfs_efd_log_item {\n\tstruct xfs_log_item efd_item;\n\tstruct xfs_efi_log_item *efd_efip;\n\tuint efd_next_extent;\n\tstruct xfs_efd_log_format efd_format;\n};\n\nstruct xfs_efi_log_format {\n\tuint16_t efi_type;\n\tuint16_t efi_size;\n\tuint32_t efi_nextents;\n\tuint64_t efi_id;\n\tstruct xfs_extent efi_extents[0];\n};\n\nstruct xfs_extent_32 {\n\tuint64_t ext_start;\n\tuint32_t ext_len;\n} __attribute__((packed));\n\nstruct xfs_efi_log_format_32 {\n\tuint16_t efi_type;\n\tuint16_t efi_size;\n\tuint32_t efi_nextents;\n\tuint64_t efi_id;\n\tstruct xfs_extent_32 efi_extents[0];\n};\n\nstruct xfs_extent_64 {\n\tuint64_t ext_start;\n\tuint32_t ext_len;\n\tuint32_t ext_pad;\n};\n\nstruct xfs_efi_log_format_64 {\n\tuint16_t efi_type;\n\tuint16_t efi_size;\n\tuint32_t efi_nextents;\n\tuint64_t efi_id;\n\tstruct xfs_extent_64 efi_extents[0];\n};\n\nstruct xfs_efi_log_item {\n\tstruct xfs_log_item efi_item;\n\tatomic_t efi_refcount;\n\tatomic_t efi_next_extent;\n\tstruct xfs_efi_log_format efi_format;\n};\n\nstruct xfs_kobj {\n\tstruct kobject kobject;\n\tstruct completion complete;\n};\n\nstruct xfs_error_cfg {\n\tstruct xfs_kobj kobj;\n\tint max_retries;\n\tlong int retry_timeout;\n};\n\nstruct xfs_error_init {\n\tchar *name;\n\tint max_retries;\n\tint retry_timeout;\n};\n\nstruct xfs_error_injection {\n\t__s32 fd;\n\t__s32 errtag;\n};\n\ntypedef struct xfs_error_injection xfs_error_injection_t;\n\nstruct xfs_exchange_range {\n\t__s32 file1_fd;\n\t__u32 pad;\n\t__u64 file1_offset;\n\t__u64 file2_offset;\n\t__u64 length;\n\t__u64 flags;\n};\n\nstruct xfs_exchmaps_adjacent {\n\tstruct xfs_bmbt_irec left1;\n\tstruct xfs_bmbt_irec right1;\n\tstruct xfs_bmbt_irec left2;\n\tstruct xfs_bmbt_irec right2;\n};\n\nstruct xfs_exchmaps_intent {\n\tstruct list_head xmi_list;\n\tstruct xfs_inode *xmi_ip1;\n\tstruct xfs_inode *xmi_ip2;\n\txfs_fileoff_t xmi_startoff1;\n\txfs_fileoff_t xmi_startoff2;\n\txfs_filblks_t xmi_blockcount;\n\txfs_fsize_t xmi_isize1;\n\txfs_fsize_t xmi_isize2;\n\tuint64_t xmi_flags;\n};\n\nstruct xfs_exchmaps_req {\n\tstruct xfs_inode *ip1;\n\tstruct xfs_inode *ip2;\n\txfs_fileoff_t startoff1;\n\txfs_fileoff_t startoff2;\n\txfs_filblks_t blockcount;\n\tuint64_t flags;\n\txfs_filblks_t ip1_bcount;\n\txfs_filblks_t ip2_bcount;\n\txfs_filblks_t ip1_rtbcount;\n\txfs_filblks_t ip2_rtbcount;\n\tlong long unsigned int resblks;\n\tlong long unsigned int nr_exchanges;\n};\n\nstruct xfs_exchrange {\n\tstruct file *file1;\n\tstruct file *file2;\n\tloff_t file1_offset;\n\tloff_t file2_offset;\n\tu64 length;\n\tu64 flags;\n\tu64 file2_ino;\n\tstruct timespec64 file2_mtime;\n\tstruct timespec64 file2_ctime;\n\tu32 file2_gen;\n};\n\nstruct xfs_extent_busy {\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tstruct xfs_group *group;\n\txfs_agblock_t bno;\n\txfs_extlen_t length;\n\tunsigned int flags;\n};\n\nstruct xfs_extent_busy_tree {\n\tspinlock_t eb_lock;\n\tstruct rb_root eb_tree;\n\tunsigned int eb_gen;\n\twait_queue_head_t eb_wait;\n};\n\nstruct xfs_extent_free_item {\n\tstruct list_head xefi_list;\n\tuint64_t xefi_owner;\n\txfs_fsblock_t xefi_startblock;\n\txfs_extlen_t xefi_blockcount;\n\tstruct xfs_group *xefi_group;\n\tunsigned int xefi_flags;\n\tenum xfs_ag_resv_type xefi_agresv;\n};\n\nstruct xfs_fid {\n\t__u16 fid_len;\n\t__u16 fid_pad;\n\t__u32 fid_gen;\n\t__u64 fid_ino;\n};\n\ntypedef struct xfs_fid xfs_fid_t;\n\nstruct xfs_fid64 {\n\tu64 ino;\n\tu32 gen;\n\tu64 parent_ino;\n\tu32 parent_gen;\n} __attribute__((packed));\n\nstruct xfs_find_left_neighbor_info {\n\tstruct xfs_rmap_irec high;\n\tstruct xfs_rmap_irec *irec;\n};\n\nstruct xfs_freecounter {\n\tstruct percpu_counter count;\n\tuint64_t res_total;\n\tuint64_t res_avail;\n\tuint64_t res_saved;\n};\n\nstruct xfs_fs_eofblocks {\n\t__u32 eof_version;\n\t__u32 eof_flags;\n\tuid_t eof_uid;\n\tgid_t eof_gid;\n\tprid_t eof_prid;\n\t__u32 pad32;\n\t__u64 eof_min_file_size;\n\t__u64 pad64[12];\n};\n\nstruct xfs_fsmap {\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\txfs_fileoff_t fmr_offset;\n\txfs_filblks_t fmr_length;\n};\n\nstruct xfs_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct xfs_fsmap fmh_keys[2];\n};\n\nstruct xfs_fsmap_irec {\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t len_daddr;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int rm_flags;\n\txfs_agblock_t rec_key;\n};\n\nstruct xfs_fsop_handlereq {\n\t__u32 fd;\n\tvoid *path;\n\t__u32 oflags;\n\tvoid *ihandle;\n\t__u32 ihandlen;\n\tvoid *ohandle;\n\t__u32 *ohandlen;\n};\n\nstruct xfs_fsop_attrlist_handlereq {\n\tstruct xfs_fsop_handlereq hreq;\n\tstruct xfs_attrlist_cursor pos;\n\t__u32 flags;\n\t__u32 buflen;\n\tvoid *buffer;\n};\n\nstruct xfs_fsop_attrmulti_handlereq {\n\tstruct xfs_fsop_handlereq hreq;\n\t__u32 opcount;\n\tstruct xfs_attr_multiop *ops;\n};\n\ntypedef struct xfs_fsop_attrmulti_handlereq xfs_fsop_attrmulti_handlereq_t;\n\nstruct xfs_fsop_bulkreq {\n\t__u64 *lastip;\n\t__s32 icount;\n\tvoid *ubuffer;\n\t__s32 *ocount;\n};\n\nstruct xfs_fsop_counts {\n\t__u64 freedata;\n\t__u64 freertx;\n\t__u64 freeino;\n\t__u64 allocino;\n};\n\nstruct xfs_fsop_geom {\n\t__u32 blocksize;\n\t__u32 rtextsize;\n\t__u32 agblocks;\n\t__u32 agcount;\n\t__u32 logblocks;\n\t__u32 sectsize;\n\t__u32 inodesize;\n\t__u32 imaxpct;\n\t__u64 datablocks;\n\t__u64 rtblocks;\n\t__u64 rtextents;\n\t__u64 logstart;\n\tunsigned char uuid[16];\n\t__u32 sunit;\n\t__u32 swidth;\n\t__s32 version;\n\t__u32 flags;\n\t__u32 logsectsize;\n\t__u32 rtsectsize;\n\t__u32 dirblocksize;\n\t__u32 logsunit;\n\tuint32_t sick;\n\tuint32_t checked;\n\t__u32 rgextents;\n\t__u32 rgcount;\n\t__u64 rtstart;\n\t__u64 rtreserved;\n\t__u64 reserved[14];\n};\n\ntypedef struct xfs_fsop_handlereq xfs_fsop_handlereq_t;\n\nstruct xfs_fsop_resblks {\n\t__u64 resblks;\n\t__u64 resblks_avail;\n};\n\nstruct xfs_mru_cache_elem {\n\tstruct list_head list_node;\n\tlong unsigned int key;\n};\n\nstruct xfs_fstrm_item {\n\tstruct xfs_mru_cache_elem mru;\n\tstruct xfs_perag *pag;\n};\n\nstruct xfs_zone_scratch;\n\nstruct xfs_zone_gc_data;\n\nstruct xfs_open_zone;\n\nstruct xfs_rtgroup;\n\nstruct xfs_gc_bio {\n\tstruct xfs_zone_gc_data *data;\n\tstruct list_head entry;\n\tenum {\n\t\tXFS_GC_BIO_NEW = 0,\n\t\tXFS_GC_BIO_DONE = 1,\n\t} state;\n\tstruct xfs_inode *ip;\n\tloff_t offset;\n\tunsigned int len;\n\txfs_fsblock_t old_startblock;\n\txfs_daddr_t new_daddr;\n\tstruct xfs_zone_scratch *scratch;\n\tbool is_seq;\n\tstruct xfs_open_zone *oz;\n\tstruct xfs_rtgroup *victim_rtg;\n\tstruct bio bio;\n};\n\nstruct xfs_getfsmap_info;\n\nstruct xfs_getfsmap_dev {\n\tu32 dev;\n\tint (*fn)(struct xfs_trans *, const struct xfs_fsmap *, struct xfs_getfsmap_info *);\n\tsector_t nr_sectors;\n};\n\nstruct xfs_getfsmap_info {\n\tstruct xfs_fsmap_head *head;\n\tstruct fsmap *fsmap_recs;\n\tstruct xfs_buf *agf_bp;\n\tstruct xfs_group *group;\n\txfs_daddr_t next_daddr;\n\txfs_daddr_t low_daddr;\n\txfs_daddr_t end_daddr;\n\tu64 missing_owner;\n\tu32 dev;\n\tstruct xfs_rmap_irec low;\n\tstruct xfs_rmap_irec high;\n\tbool last;\n};\n\nstruct xfs_getparents {\n\tstruct xfs_attrlist_cursor gp_cursor;\n\t__u16 gp_iflags;\n\t__u16 gp_oflags;\n\t__u32 gp_bufsize;\n\t__u64 gp_reserved;\n\t__u64 gp_buffer;\n};\n\nstruct xfs_handle {\n\tunion {\n\t\t__s64 align;\n\t\txfs_fsid_t _ha_fsid;\n\t} ha_u;\n\txfs_fid_t ha_fid;\n};\n\nstruct xfs_getparents_by_handle {\n\tstruct xfs_handle gph_handle;\n\tstruct xfs_getparents gph_request;\n};\n\nstruct xfs_getparents_rec;\n\nstruct xfs_getparents_ctx {\n\tstruct xfs_attr_list_context context;\n\tstruct xfs_getparents_by_handle gph;\n\tstruct xfs_inode *ip;\n\tvoid *krecords;\n\tstruct xfs_getparents_rec *lastrec;\n\tunsigned int count;\n};\n\nstruct xfs_getparents_rec {\n\tstruct xfs_handle gpr_parent;\n\t__u32 gpr_reclen;\n\t__u32 gpr_reserved;\n\tchar gpr_name[0];\n};\n\nstruct xfs_globals {\n\tint bload_leaf_slack;\n\tint bload_node_slack;\n\tint log_recovery_delay;\n\tint mount_delay;\n\tbool bug_on_assert;\n\tbool always_cow;\n};\n\nstruct xfs_hooks {};\n\nstruct xfs_group {\n\tstruct xfs_mount *xg_mount;\n\tuint32_t xg_gno;\n\tenum xfs_group_type xg_type;\n\tatomic_t xg_ref;\n\tatomic_t xg_active_ref;\n\tuint32_t xg_block_count;\n\tuint32_t xg_min_gbno;\n\tunion {\n\t\tstruct xfs_extent_busy_tree *xg_busy_extents;\n\t\tstruct xfs_group *xg_next_reset;\n\t};\n\tuint16_t xg_checked;\n\tuint16_t xg_sick;\n\tspinlock_t xg_state_lock;\n\tstruct xfs_defer_drain xg_intents_drain;\n\tstruct xfs_hooks xg_rmap_update_hooks;\n};\n\nstruct xfs_group_data_lost {\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n};\n\nstruct xfs_groups {\n\tstruct xarray xa;\n\tuint32_t blocks;\n\tuint8_t blklog;\n\tbool has_daddr_gaps;\n\tuint64_t blkmask;\n\txfs_fsblock_t start_fsb;\n\txfs_extlen_t awu_max;\n};\n\nstruct xfs_growfs_data {\n\t__u64 newblocks;\n\t__u32 imaxpct;\n};\n\nstruct xfs_growfs_log {\n\t__u32 newblocks;\n\t__u32 isint;\n};\n\nstruct xfs_growfs_rt {\n\t__u64 newblocks;\n\t__u32 extsize;\n};\n\ntypedef struct xfs_growfs_rt xfs_growfs_rt_t;\n\ntypedef struct xfs_handle xfs_handle_t;\n\nstruct xfs_health_file_on_monitored_fs {\n\t__s32 fd;\n\t__u32 flags;\n};\n\nstruct xfs_health_monitor {\n\t__u64 flags;\n\t__u8 format;\n\t__u8 pad[23];\n};\n\nstruct xfs_health_monitor_lost {\n\t__u64 count;\n};\n\nstruct xfs_health_monitor_fs {\n\t__u32 mask;\n};\n\nstruct xfs_health_monitor_group {\n\t__u32 mask;\n\t__u32 gno;\n};\n\nstruct xfs_health_monitor_inode {\n\t__u32 mask;\n\t__u32 gen;\n\t__u64 ino;\n};\n\nstruct xfs_health_monitor_shutdown {\n\t__u32 reasons;\n};\n\nstruct xfs_health_monitor_media {\n\t__u64 daddr;\n\t__u64 bbcount;\n};\n\nstruct xfs_health_monitor_filerange {\n\t__u64 pos;\n\t__u64 len;\n\t__u64 ino;\n\t__u32 gen;\n\t__u32 error;\n};\n\nstruct xfs_health_monitor_event {\n\t__u32 domain;\n\t__u32 type;\n\t__u64 time_ns;\n\tunion {\n\t\tstruct xfs_health_monitor_lost lost;\n\t\tstruct xfs_health_monitor_fs fs;\n\t\tstruct xfs_health_monitor_group group;\n\t\tstruct xfs_health_monitor_inode inode;\n\t\tstruct xfs_health_monitor_shutdown shutdown;\n\t\tstruct xfs_health_monitor_media media;\n\t\tstruct xfs_health_monitor_filerange filerange;\n\t} e;\n\t__u64 pad[2];\n};\n\nstruct xfs_healthmon_event;\n\nstruct xfs_healthmon {\n\tuintptr_t mount_cookie;\n\tdev_t dev;\n\trefcount_t ref;\n\tstruct mutex lock;\n\tstruct xfs_healthmon_event *first_event;\n\tstruct xfs_healthmon_event *last_event;\n\tstruct xfs_healthmon_event *unmount_event;\n\tunsigned int events;\n\tbool verbose: 1;\n\tstruct wait_queue_head wait;\n\tchar *buffer;\n\tsize_t bufsize;\n\tsize_t bufhead;\n\tsize_t buftail;\n\tlong long unsigned int lost_prev_event;\n\tlong long unsigned int total_events;\n\tlong long unsigned int total_lost;\n};\n\nstruct xfs_healthmon_event {\n\tstruct xfs_healthmon_event *next;\n\tenum xfs_healthmon_type type;\n\tenum xfs_healthmon_domain domain;\n\tuint64_t time_ns;\n\tunion {\n\t\tstruct {\n\t\t\tuint64_t lostcount;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int fsmask;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int grpmask;\n\t\t\tunsigned int group;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int imask;\n\t\t\tuint32_t gen;\n\t\t\txfs_ino_t ino;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int flags;\n\t\t};\n\t\tstruct {\n\t\t\txfs_daddr_t daddr;\n\t\t\tuint64_t bbcount;\n\t\t};\n\t\tstruct {\n\t\t\txfs_ino_t fino;\n\t\t\tloff_t fpos;\n\t\t\tuint64_t flen;\n\t\t\tuint32_t fgen;\n\t\t\tint error;\n\t\t};\n\t};\n};\n\nstruct xfs_ialloc_count_inodes {\n\txfs_agino_t count;\n\txfs_agino_t freecount;\n};\n\nstruct xfs_ibulk {\n\tstruct xfs_mount *mp;\n\tstruct mnt_idmap *idmap;\n\tvoid *ubuffer;\n\txfs_ino_t startino;\n\tunsigned int icount;\n\tunsigned int ocount;\n\tunsigned int flags;\n\tunsigned int iwalk_flags;\n};\n\nstruct xfs_icluster {\n\tbool deleted;\n\txfs_ino_t first_ino;\n\tuint64_t alloc;\n};\n\nstruct xfs_icreate_args {\n\tstruct mnt_idmap *idmap;\n\tstruct xfs_inode *pip;\n\tdev_t rdev;\n\tumode_t mode;\n\tuint16_t flags;\n};\n\nstruct xfs_icreate_log {\n\tuint16_t icl_type;\n\tuint16_t icl_size;\n\t__be32 icl_ag;\n\t__be32 icl_agbno;\n\t__be32 icl_count;\n\t__be32 icl_isize;\n\t__be32 icl_length;\n\t__be32 icl_gen;\n};\n\nstruct xfs_icreate_item {\n\tstruct xfs_log_item ic_item;\n\tstruct xfs_icreate_log ic_format;\n};\n\nstruct xfs_icwalk {\n\t__u32 icw_flags;\n\tkuid_t icw_uid;\n\tkgid_t icw_gid;\n\tprid_t icw_prid;\n\t__u64 icw_min_file_size;\n\tlong int icw_scan_limit;\n};\n\nstruct xfs_iext_rec {\n\tuint64_t lo;\n\tuint64_t hi;\n};\n\nstruct xfs_iext_leaf {\n\tstruct xfs_iext_rec recs[15];\n\tstruct xfs_iext_leaf *prev;\n\tstruct xfs_iext_leaf *next;\n};\n\nstruct xfs_iext_node {\n\tuint64_t keys[16];\n\tvoid *ptrs[16];\n};\n\nstruct xfs_ifork {\n\tint64_t if_bytes;\n\tstruct xfs_btree_block *if_broot;\n\tunsigned int if_seq;\n\tint if_height;\n\tvoid *if_data;\n\txfs_extnum_t if_nextents;\n\tshort int if_broot_bytes;\n\tint8_t if_format;\n\tuint8_t if_needextents;\n};\n\nstruct xfs_imap {\n\txfs_daddr_t im_blkno;\n\tshort unsigned int im_len;\n\tshort unsigned int im_boffset;\n};\n\nstruct xfs_init_zones {\n\tuint32_t zone_size;\n\tuint32_t zone_capacity;\n\tuint64_t available;\n\tuint64_t reclaimable;\n};\n\nstruct xfs_ino_geometry {\n\tuint64_t maxicount;\n\tunsigned int inode_cluster_size;\n\tunsigned int inode_cluster_size_raw;\n\tunsigned int inodes_per_cluster;\n\tunsigned int blocks_per_cluster;\n\tunsigned int cluster_align;\n\tunsigned int cluster_align_inodes;\n\tunsigned int inoalign_mask;\n\tunsigned int inobt_mxr[2];\n\tunsigned int inobt_mnr[2];\n\tunsigned int inobt_maxlevels;\n\tunsigned int ialloc_inos;\n\tunsigned int ialloc_blks;\n\tunsigned int ialloc_min_blks;\n\tunsigned int ialloc_align;\n\tunsigned int agino_log;\n\tunsigned int attr_fork_offset;\n\tuint64_t new_diflags2;\n\tunsigned int min_folio_order;\n};\n\ntypedef struct xfs_inobt_rec_incore xfs_inobt_rec_incore_t;\n\nstruct xfs_inode_log_item;\n\nstruct xfs_inode {\n\tstruct xfs_mount *i_mount;\n\tstruct xfs_dquot *i_udquot;\n\tstruct xfs_dquot *i_gdquot;\n\tstruct xfs_dquot *i_pdquot;\n\txfs_ino_t i_ino;\n\tstruct xfs_imap i_imap;\n\tstruct xfs_ifork *i_cowfp;\n\tstruct xfs_ifork i_df;\n\tstruct xfs_ifork i_af;\n\tstruct xfs_inode_log_item *i_itemp;\n\tstruct rw_semaphore i_lock;\n\tatomic_t i_pincount;\n\tstruct llist_node i_gclist;\n\tuint16_t i_checked;\n\tuint16_t i_sick;\n\tspinlock_t i_flags_lock;\n\tlong unsigned int i_flags;\n\tuint64_t i_delayed_blks;\n\txfs_fsize_t i_disk_size;\n\txfs_rfsblock_t i_nblocks;\n\tprid_t i_projid;\n\txfs_extlen_t i_extsize;\n\tunion {\n\t\tuint32_t i_used_blocks;\n\t\txfs_extlen_t i_cowextsize;\n\t\tuint16_t i_flushiter;\n\t};\n\tuint8_t i_forkoff;\n\tenum xfs_metafile_type i_metatype;\n\tuint16_t i_diflags;\n\tuint64_t i_diflags2;\n\tstruct timespec64 i_crtime;\n\txfs_agino_t i_next_unlinked;\n\txfs_agino_t i_prev_unlinked;\n\tstruct inode i_vnode;\n\tspinlock_t i_ioend_lock;\n\tstruct work_struct i_ioend_work;\n\tstruct list_head i_ioend_list;\n};\n\ntypedef struct xfs_inode xfs_inode_t;\n\nstruct xfs_inode_log_format {\n\tuint16_t ilf_type;\n\tuint16_t ilf_size;\n\tuint32_t ilf_fields;\n\tuint16_t ilf_asize;\n\tuint16_t ilf_dsize;\n\tuint32_t ilf_pad;\n\tuint64_t ilf_ino;\n\tunion {\n\t\tuint32_t ilfu_rdev;\n\t\tuint8_t __pad[16];\n\t} ilf_u;\n\tint64_t ilf_blkno;\n\tint32_t ilf_len;\n\tint32_t ilf_boffset;\n};\n\nstruct xfs_inode_log_format_32 {\n\tuint16_t ilf_type;\n\tuint16_t ilf_size;\n\tuint32_t ilf_fields;\n\tuint16_t ilf_asize;\n\tuint16_t ilf_dsize;\n\tuint64_t ilf_ino;\n\tunion {\n\t\tuint32_t ilfu_rdev;\n\t\tuint8_t __pad[16];\n\t} ilf_u;\n\tint64_t ilf_blkno;\n\tint32_t ilf_len;\n\tint32_t ilf_boffset;\n} __attribute__((packed));\n\nstruct xfs_inode_log_item {\n\tstruct xfs_log_item ili_item;\n\tstruct xfs_inode *ili_inode;\n\tshort unsigned int ili_lock_flags;\n\tunsigned int ili_dirty_flags;\n\tspinlock_t ili_lock;\n\tunsigned int ili_last_fields;\n\tunsigned int ili_fields;\n\txfs_lsn_t ili_flush_lsn;\n\txfs_csn_t ili_commit_seq;\n\txfs_csn_t ili_datasync_seq;\n};\n\nstruct xfs_inodegc {\n\tstruct xfs_mount *mp;\n\tstruct llist_head list;\n\tstruct delayed_work work;\n\tint error;\n\tunsigned int items;\n\tunsigned int shrinker_hits;\n\tunsigned int cpu;\n};\n\nstruct xfs_inogrp {\n\t__u64 xi_startino;\n\t__s32 xi_alloccount;\n\t__u64 xi_allocmask;\n};\n\nstruct xfs_inumbers {\n\tuint64_t xi_startino;\n\tuint64_t xi_allocmask;\n\tuint8_t xi_alloccount;\n\tuint8_t xi_version;\n\tuint8_t xi_padding[6];\n};\n\ntypedef int (*inumbers_fmt_pf)(struct xfs_ibulk *, const struct xfs_inumbers *);\n\nstruct xfs_inumbers_chunk {\n\tinumbers_fmt_pf formatter;\n\tstruct xfs_ibulk *breq;\n};\n\nstruct xfs_inumbers_req {\n\tstruct xfs_bulk_ireq hdr;\n\tstruct xfs_inumbers inumbers[0];\n};\n\nstruct xfs_iread_state {\n\tstruct xfs_iext_cursor icur;\n\txfs_extnum_t loaded;\n};\n\nstruct xlog_format_buf;\n\nstruct xfs_item_ops {\n\tunsigned int flags;\n\tvoid (*iop_size)(struct xfs_log_item *, int *, int *);\n\tvoid (*iop_format)(struct xfs_log_item *, struct xlog_format_buf *);\n\tvoid (*iop_pin)(struct xfs_log_item *);\n\tvoid (*iop_unpin)(struct xfs_log_item *, int);\n\tuint64_t (*iop_sort)(struct xfs_log_item *);\n\tint (*iop_precommit)(struct xfs_trans *, struct xfs_log_item *);\n\tvoid (*iop_committing)(struct xfs_log_item *, xfs_csn_t);\n\txfs_lsn_t (*iop_committed)(struct xfs_log_item *, xfs_lsn_t);\n\tuint (*iop_push)(struct xfs_log_item *, struct list_head *);\n\tvoid (*iop_release)(struct xfs_log_item *);\n\tbool (*iop_match)(struct xfs_log_item *, uint64_t);\n\tstruct xfs_log_item * (*iop_intent)(struct xfs_log_item *);\n};\n\nstruct xfs_iunlink_item {\n\tstruct xfs_log_item item;\n\tstruct xfs_inode *ip;\n\tstruct xfs_perag *pag;\n\txfs_agino_t next_agino;\n\txfs_agino_t old_agino;\n};\n\nstruct xfs_pwork_ctl;\n\nstruct xfs_pwork {\n\tstruct work_struct work;\n\tstruct xfs_pwork_ctl *pctl;\n};\n\ntypedef int (*xfs_iwalk_fn)(struct xfs_mount *, struct xfs_trans *, xfs_ino_t, void *);\n\ntypedef int (*xfs_inobt_walk_fn)(struct xfs_mount *, struct xfs_trans *, xfs_agnumber_t, const struct xfs_inobt_rec_incore *, void *);\n\nstruct xfs_iwalk_ag {\n\tstruct xfs_pwork pwork;\n\tstruct xfs_mount *mp;\n\tstruct xfs_trans *tp;\n\tstruct xfs_perag *pag;\n\txfs_ino_t startino;\n\txfs_ino_t lastino;\n\tstruct xfs_inobt_rec_incore *recs;\n\tunsigned int sz_recs;\n\tunsigned int nr_recs;\n\txfs_iwalk_fn iwalk_fn;\n\txfs_inobt_walk_fn inobt_walk_fn;\n\tvoid *data;\n\tunsigned int trim_start: 1;\n\tunsigned int skip_empty: 1;\n\tunsigned int drop_trans: 1;\n};\n\nstruct xfs_legacy_timestamp {\n\t__be32 t_sec;\n\t__be32 t_nsec;\n};\n\nstruct xfs_log_dinode {\n\tuint16_t di_magic;\n\tuint16_t di_mode;\n\tint8_t di_version;\n\tint8_t di_format;\n\tuint16_t di_metatype;\n\tuint32_t di_uid;\n\tuint32_t di_gid;\n\tuint32_t di_nlink;\n\tuint16_t di_projid_lo;\n\tuint16_t di_projid_hi;\n\tunion {\n\t\tuint64_t di_big_nextents;\n\t\tuint64_t di_v3_pad;\n\t\tstruct {\n\t\t\tuint8_t di_v2_pad[6];\n\t\t\tuint16_t di_flushiter;\n\t\t};\n\t};\n\txfs_log_timestamp_t di_atime;\n\txfs_log_timestamp_t di_mtime;\n\txfs_log_timestamp_t di_ctime;\n\txfs_fsize_t di_size;\n\txfs_rfsblock_t di_nblocks;\n\txfs_extlen_t di_extsize;\n\tunion {\n\t\tstruct {\n\t\t\tuint32_t di_nextents;\n\t\t\tuint16_t di_anextents;\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\tuint32_t di_big_anextents;\n\t\t\tuint16_t di_nrext64_pad;\n\t\t} __attribute__((packed));\n\t};\n\tuint8_t di_forkoff;\n\tint8_t di_aformat;\n\tuint32_t di_dmevmask;\n\tuint16_t di_dmstate;\n\tuint16_t di_flags;\n\tuint32_t di_gen;\n\txfs_agino_t di_next_unlinked;\n\tuint32_t di_crc;\n\tuint64_t di_changecount;\n\txfs_lsn_t di_lsn;\n\tuint64_t di_flags2;\n\tunion {\n\t\tuint32_t di_cowextsize;\n\t\tuint32_t di_used_blocks;\n\t};\n\tuint8_t di_pad2[12];\n\txfs_log_timestamp_t di_crtime;\n\txfs_ino_t di_ino;\n\tuuid_t di_uuid;\n};\n\nstruct xfs_log_iovec {\n\tvoid *i_addr;\n\tint i_len;\n\tuint i_type;\n};\n\nstruct xfs_log_legacy_timestamp {\n\tint32_t t_sec;\n\tint32_t t_nsec;\n};\n\nstruct xfs_log_vec {\n\tstruct list_head lv_list;\n\tuint32_t lv_order_id;\n\tint lv_niovecs;\n\tstruct xfs_log_iovec *lv_iovecp;\n\tstruct xfs_log_item *lv_item;\n\tchar *lv_buf;\n\tint lv_bytes;\n\tint lv_buf_used;\n\tint lv_alloc_size;\n};\n\nstruct xfs_metadir_update {\n\tstruct xfs_inode *dp;\n\tconst char *path;\n\tstruct xfs_parent_args *ppargs;\n\tstruct xfs_inode *ip;\n\tstruct xfs_trans *tp;\n\tenum xfs_metafile_type metafile_type;\n\tunsigned int dp_locked: 1;\n\tunsigned int ip_locked: 1;\n};\n\nstruct xfs_sb {\n\tuint32_t sb_magicnum;\n\tuint32_t sb_blocksize;\n\txfs_rfsblock_t sb_dblocks;\n\txfs_rfsblock_t sb_rblocks;\n\txfs_rtbxlen_t sb_rextents;\n\tuuid_t sb_uuid;\n\txfs_fsblock_t sb_logstart;\n\txfs_ino_t sb_rootino;\n\txfs_ino_t sb_rbmino;\n\txfs_ino_t sb_rsumino;\n\txfs_agblock_t sb_rextsize;\n\txfs_agblock_t sb_agblocks;\n\txfs_agnumber_t sb_agcount;\n\txfs_extlen_t sb_rbmblocks;\n\txfs_extlen_t sb_logblocks;\n\tuint16_t sb_versionnum;\n\tuint16_t sb_sectsize;\n\tuint16_t sb_inodesize;\n\tuint16_t sb_inopblock;\n\tchar sb_fname[12];\n\tuint8_t sb_blocklog;\n\tuint8_t sb_sectlog;\n\tuint8_t sb_inodelog;\n\tuint8_t sb_inopblog;\n\tuint8_t sb_agblklog;\n\tuint8_t sb_rextslog;\n\tuint8_t sb_inprogress;\n\tuint8_t sb_imax_pct;\n\tuint64_t sb_icount;\n\tuint64_t sb_ifree;\n\tuint64_t sb_fdblocks;\n\tuint64_t sb_frextents;\n\txfs_ino_t sb_uquotino;\n\txfs_ino_t sb_gquotino;\n\tuint16_t sb_qflags;\n\tuint8_t sb_flags;\n\tuint8_t sb_shared_vn;\n\txfs_extlen_t sb_inoalignmt;\n\tuint32_t sb_unit;\n\tuint32_t sb_width;\n\tuint8_t sb_dirblklog;\n\tuint8_t sb_logsectlog;\n\tuint16_t sb_logsectsize;\n\tuint32_t sb_logsunit;\n\tuint32_t sb_features2;\n\tuint32_t sb_bad_features2;\n\tuint32_t sb_features_compat;\n\tuint32_t sb_features_ro_compat;\n\tuint32_t sb_features_incompat;\n\tuint32_t sb_features_log_incompat;\n\tuint32_t sb_crc;\n\txfs_extlen_t sb_spino_align;\n\txfs_ino_t sb_pquotino;\n\txfs_lsn_t sb_lsn;\n\tuuid_t sb_meta_uuid;\n\txfs_ino_t sb_metadirino;\n\txfs_rgnumber_t sb_rgcount;\n\txfs_rtxlen_t sb_rgextents;\n\tuint8_t sb_rgblklog;\n\tuint8_t sb_pad[7];\n\txfs_rfsblock_t sb_rtstart;\n\txfs_filblks_t sb_rtreserved;\n};\n\nstruct xfs_trans_res {\n\tuint tr_logres;\n\tint tr_logcount;\n\tint tr_logflags;\n};\n\nstruct xfs_trans_resv {\n\tstruct xfs_trans_res tr_write;\n\tstruct xfs_trans_res tr_itruncate;\n\tstruct xfs_trans_res tr_rename;\n\tstruct xfs_trans_res tr_link;\n\tstruct xfs_trans_res tr_remove;\n\tstruct xfs_trans_res tr_symlink;\n\tstruct xfs_trans_res tr_create;\n\tstruct xfs_trans_res tr_create_tmpfile;\n\tstruct xfs_trans_res tr_mkdir;\n\tstruct xfs_trans_res tr_ifree;\n\tstruct xfs_trans_res tr_ichange;\n\tstruct xfs_trans_res tr_growdata;\n\tstruct xfs_trans_res tr_addafork;\n\tstruct xfs_trans_res tr_writeid;\n\tstruct xfs_trans_res tr_attrinval;\n\tstruct xfs_trans_res tr_attrsetm;\n\tstruct xfs_trans_res tr_attrsetrt;\n\tstruct xfs_trans_res tr_attrrm;\n\tstruct xfs_trans_res tr_clearagi;\n\tstruct xfs_trans_res tr_growrtalloc;\n\tstruct xfs_trans_res tr_growrtzero;\n\tstruct xfs_trans_res tr_growrtfree;\n\tstruct xfs_trans_res tr_qm_setqlim;\n\tstruct xfs_trans_res tr_qm_dqalloc;\n\tstruct xfs_trans_res tr_sb;\n\tstruct xfs_trans_res tr_fsyncts;\n\tstruct xfs_trans_res tr_atomic_ioend;\n};\n\nstruct xfsstats;\n\nstruct xstats {\n\tstruct xfsstats *xs_stats;\n\tstruct xfs_kobj xs_kobj;\n};\n\nstruct xfs_quotainfo;\n\nstruct xfs_mru_cache;\n\nstruct xfs_zone_info;\n\nstruct xfs_mount {\n\tstruct xfs_sb m_sb;\n\tstruct super_block *m_super;\n\tstruct xfs_ail *m_ail;\n\tstruct xfs_buf *m_sb_bp;\n\tstruct xfs_buf *m_rtsb_bp;\n\tchar *m_rtname;\n\tchar *m_logname;\n\tstruct xfs_da_geometry *m_dir_geo;\n\tstruct xfs_da_geometry *m_attr_geo;\n\tstruct xlog *m_log;\n\tstruct xfs_inode *m_rootip;\n\tstruct xfs_inode *m_metadirip;\n\tstruct xfs_inode *m_rtdirip;\n\tstruct xfs_quotainfo *m_quotainfo;\n\tstruct xfs_buftarg *m_ddev_targp;\n\tstruct xfs_buftarg *m_logdev_targp;\n\tstruct xfs_buftarg *m_rtdev_targp;\n\tvoid *m_inodegc;\n\tstruct xfs_mru_cache *m_filestream;\n\tstruct workqueue_struct *m_buf_workqueue;\n\tstruct workqueue_struct *m_unwritten_workqueue;\n\tstruct workqueue_struct *m_reclaim_workqueue;\n\tstruct workqueue_struct *m_sync_workqueue;\n\tstruct workqueue_struct *m_blockgc_wq;\n\tstruct workqueue_struct *m_inodegc_wq;\n\tint m_bsize;\n\tuint8_t m_blkbit_log;\n\tuint8_t m_blkbb_log;\n\tuint8_t m_agno_log;\n\tuint8_t m_sectbb_log;\n\tint8_t m_rtxblklog;\n\tuint m_blockmask;\n\tuint m_blockwsize;\n\tunsigned int m_rtx_per_rbmblock;\n\tuint m_alloc_mxr[2];\n\tuint m_alloc_mnr[2];\n\tuint m_bmap_dmxr[2];\n\tuint m_bmap_dmnr[2];\n\tuint m_rmap_mxr[2];\n\tuint m_rmap_mnr[2];\n\tuint m_rtrmap_mxr[2];\n\tuint m_rtrmap_mnr[2];\n\tuint m_refc_mxr[2];\n\tuint m_refc_mnr[2];\n\tuint m_rtrefc_mxr[2];\n\tuint m_rtrefc_mnr[2];\n\tuint m_alloc_maxlevels;\n\tuint m_bm_maxlevels[2];\n\tuint m_rmap_maxlevels;\n\tuint m_rtrmap_maxlevels;\n\tuint m_refc_maxlevels;\n\tuint m_rtrefc_maxlevels;\n\tunsigned int m_agbtree_maxlevels;\n\tunsigned int m_rtbtree_maxlevels;\n\txfs_extlen_t m_ag_prealloc_blocks;\n\tuint m_alloc_set_aside;\n\tuint m_ag_max_usable;\n\tint m_dalign;\n\tint m_swidth;\n\txfs_agnumber_t m_maxagi;\n\tuint m_allocsize_log;\n\tuint m_allocsize_blocks;\n\tint m_logbufs;\n\tint m_logbsize;\n\tunsigned int m_rsumlevels;\n\txfs_filblks_t m_rsumblocks;\n\tint m_fixedfsid[2];\n\tuint m_qflags;\n\tuint64_t m_features;\n\tuint64_t m_low_space[5];\n\tuint64_t m_low_rtexts[5];\n\tuint64_t m_rtxblkmask;\n\tstruct xfs_ino_geometry m_ino_geo;\n\tstruct xfs_trans_resv m_resv;\n\tlong unsigned int m_opstate;\n\tbool m_always_cow;\n\tbool m_fail_unmount;\n\tbool m_finobt_nores;\n\tbool m_update_sb;\n\tunsigned int m_max_open_zones;\n\tunsigned int m_zonegc_low_space;\n\tlong long unsigned int m_awu_max_bytes;\n\tuint8_t m_fs_checked;\n\tuint8_t m_fs_sick;\n\tuint8_t m_rt_checked;\n\tuint8_t m_rt_sick;\n\tlong: 0;\n\tspinlock_t m_sb_lock;\n\tstruct percpu_counter m_icount;\n\tstruct percpu_counter m_ifree;\n\tstruct xfs_freecounter m_free[3];\n\tstruct percpu_counter m_delalloc_blks;\n\tstruct percpu_counter m_delalloc_rtextents;\n\tatomic64_t m_allocbt_blks;\n\tstruct xfs_groups m_groups[2];\n\tstruct delayed_work m_reclaim_work;\n\tstruct xfs_zone_info *m_zone_info;\n\tstruct dentry *m_debugfs;\n\tstruct xfs_kobj m_kobj;\n\tstruct xfs_kobj m_error_kobj;\n\tstruct xfs_kobj m_error_meta_kobj;\n\tstruct xfs_error_cfg m_error_cfg[4];\n\tstruct xstats m_stats;\n\tstruct xfs_kobj m_zoned_kobj;\n\txfs_agnumber_t m_agfrotor;\n\tatomic_t m_agirotor;\n\tatomic_t m_rtgrotor;\n\tstruct mutex m_metafile_resv_lock;\n\tuint64_t m_metafile_resv_target;\n\tuint64_t m_metafile_resv_used;\n\tuint64_t m_metafile_resv_avail;\n\tstruct shrinker *m_inodegc_shrinker;\n\tstruct work_struct m_flush_inodes_work;\n\tuint32_t m_generation;\n\tstruct mutex m_growlock;\n\tstruct cpumask m_inodegc_cpumask;\n\tstruct xfs_hooks m_dir_update_hooks;\n\tstruct xfs_healthmon *m_healthmon;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct xfs_mount xfs_mount_t;\n\ntypedef void (*xfs_mru_cache_free_func_t)(void *, struct xfs_mru_cache_elem *);\n\nstruct xfs_mru_cache {\n\tstruct xarray store;\n\tstruct list_head *lists;\n\tstruct list_head reap_list;\n\tspinlock_t lock;\n\tunsigned int grp_count;\n\tunsigned int grp_time;\n\tunsigned int lru_grp;\n\tlong unsigned int time_zero;\n\txfs_mru_cache_free_func_t free_func;\n\tstruct delayed_work work;\n\tunsigned int queued;\n\tvoid *data;\n};\n\nstruct xfs_name {\n\tconst unsigned char *name;\n\tint len;\n\tint type;\n};\n\nstruct xfs_open_zone {\n\tstruct list_head oz_entry;\n\tatomic_t oz_ref;\n\tspinlock_t oz_alloc_lock;\n\txfs_rgblock_t oz_allocated;\n\txfs_rgblock_t oz_written;\n\tenum rw_hint oz_write_hint;\n\tbool oz_is_gc;\n\tstruct xfs_rtgroup *oz_rtg;\n\tstruct callback_head oz_rcu;\n};\n\nstruct xfs_sysctl_val {\n\tint min;\n\tint val;\n\tint max;\n};\n\ntypedef struct xfs_sysctl_val xfs_sysctl_val_t;\n\nstruct xfs_param {\n\txfs_sysctl_val_t panic_mask;\n\txfs_sysctl_val_t error_level;\n\txfs_sysctl_val_t syncd_timer;\n\txfs_sysctl_val_t stats_clear;\n\txfs_sysctl_val_t inherit_sync;\n\txfs_sysctl_val_t inherit_nodump;\n\txfs_sysctl_val_t inherit_noatim;\n\txfs_sysctl_val_t inherit_nosym;\n\txfs_sysctl_val_t rotorstep;\n\txfs_sysctl_val_t inherit_nodfrg;\n\txfs_sysctl_val_t fstrm_timer;\n\txfs_sysctl_val_t blockgc_timer;\n};\n\ntypedef struct xfs_param xfs_param_t;\n\nstruct xfs_parent_rec {\n\t__be64 p_ino;\n\t__be32 p_gen;\n} __attribute__((packed));\n\nstruct xfs_parent_args {\n\tstruct xfs_parent_rec rec;\n\tstruct xfs_parent_rec new_rec;\n\tstruct xfs_da_args args;\n};\n\nstruct xfs_perag {\n\tstruct xfs_group pag_group;\n\tlong unsigned int pag_opstate;\n\tuint8_t pagf_bno_level;\n\tuint8_t pagf_cnt_level;\n\tuint8_t pagf_rmap_level;\n\tuint32_t pagf_flcount;\n\txfs_extlen_t pagf_freeblks;\n\txfs_extlen_t pagf_longest;\n\tuint32_t pagf_btreeblks;\n\txfs_agino_t pagi_freecount;\n\txfs_agino_t pagi_count;\n\txfs_agino_t pagl_pagino;\n\txfs_agino_t pagl_leftrec;\n\txfs_agino_t pagl_rightrec;\n\tuint8_t pagf_refcount_level;\n\tstruct xfs_ag_resv pag_meta_resv;\n\tstruct xfs_ag_resv pag_rmapbt_resv;\n\txfs_agino_t agino_min;\n\txfs_agino_t agino_max;\n\tatomic_t pagf_fstrms;\n\tspinlock_t pag_ici_lock;\n\tstruct xarray pag_ici_root;\n\tint pag_ici_reclaimable;\n\tlong unsigned int pag_ici_reclaim_cursor;\n\tstruct xfs_buf_cache pag_bcache;\n\tstruct delayed_work pag_blockgc_work;\n};\n\ntypedef int (*xfs_pwork_work_fn)(struct xfs_mount *, struct xfs_pwork *);\n\nstruct xfs_pwork_ctl {\n\tstruct workqueue_struct *wq;\n\tstruct xfs_mount *mp;\n\txfs_pwork_work_fn work_fn;\n\tstruct wait_queue_head poll_wait;\n\tatomic_t nr_work;\n\tint error;\n};\n\nstruct xfs_qm_isolate {\n\tstruct list_head buffers;\n\tstruct list_head dispose;\n};\n\nstruct xfs_qoff_logformat {\n\tshort unsigned int qf_type;\n\tshort unsigned int qf_size;\n\tunsigned int qf_flags;\n\tchar qf_pad[12];\n};\n\nstruct xfs_quotainfo {\n\tstruct xarray qi_uquota_tree;\n\tstruct xarray qi_gquota_tree;\n\tstruct xarray qi_pquota_tree;\n\tstruct mutex qi_tree_lock;\n\tstruct xfs_inode *qi_uquotaip;\n\tstruct xfs_inode *qi_gquotaip;\n\tstruct xfs_inode *qi_pquotaip;\n\tstruct xfs_inode *qi_dirip;\n\tstruct list_lru qi_lru;\n\tuint64_t qi_dquots;\n\tstruct mutex qi_quotaofflock;\n\txfs_filblks_t qi_dqchunklen;\n\tuint qi_dqperchunk;\n\tstruct xfs_def_quota qi_usr_default;\n\tstruct xfs_def_quota qi_grp_default;\n\tstruct xfs_def_quota qi_prj_default;\n\tstruct shrinker *qi_shrinker;\n\ttime64_t qi_expiry_min;\n\ttime64_t qi_expiry_max;\n\tstruct xfs_hooks qi_mod_ino_dqtrx_hooks;\n\tstruct xfs_hooks qi_apply_dqtrx_hooks;\n};\n\nstruct xfs_refcount_intent {\n\tstruct list_head ri_list;\n\tstruct xfs_group *ri_group;\n\tenum xfs_refcount_intent_type ri_type;\n\txfs_extlen_t ri_blockcount;\n\txfs_fsblock_t ri_startblock;\n\tbool ri_realtime;\n};\n\ntypedef int (*xfs_refcount_query_range_fn)(struct xfs_btree_cur *, const struct xfs_refcount_irec *, void *);\n\nstruct xfs_refcount_query_range_info {\n\txfs_refcount_query_range_fn fn;\n\tvoid *priv;\n};\n\nstruct xfs_refcount_recovery {\n\tstruct list_head rr_list;\n\tstruct xfs_refcount_irec rr_rrec;\n};\n\nstruct xfs_rmap_intent {\n\tstruct list_head ri_list;\n\tenum xfs_rmap_intent_type ri_type;\n\tint ri_whichfork;\n\tuint64_t ri_owner;\n\tstruct xfs_bmbt_irec ri_bmap;\n\tstruct xfs_group *ri_group;\n\tbool ri_realtime;\n};\n\nstruct xfs_rmap_matches {\n\tlong long unsigned int matches;\n\tlong long unsigned int non_owner_matches;\n\tlong long unsigned int bad_non_owner_matches;\n};\n\nstruct xfs_rmap_ownercount {\n\tstruct xfs_rmap_irec good;\n\tstruct xfs_rmap_irec low;\n\tstruct xfs_rmap_irec high;\n\tstruct xfs_rmap_matches *results;\n\tbool stop_on_nonmatch;\n};\n\ntypedef int (*xfs_rmap_query_range_fn)(struct xfs_btree_cur *, const struct xfs_rmap_irec *, void *);\n\nstruct xfs_rmap_query_range_info {\n\txfs_rmap_query_range_fn fn;\n\tvoid *priv;\n};\n\nstruct xfs_rtalloc_args {\n\tstruct xfs_rtgroup *rtg;\n\tstruct xfs_mount *mp;\n\tstruct xfs_trans *tp;\n\tstruct xfs_buf *rbmbp;\n\tstruct xfs_buf *sumbp;\n\txfs_fileoff_t rbmoff;\n\txfs_fileoff_t sumoff;\n};\n\nstruct xfs_rtalloc_rec {\n\txfs_rtxnum_t ar_startext;\n\txfs_rtbxlen_t ar_extcount;\n};\n\nstruct xfs_rtbuf_blkinfo {\n\t__be32 rt_magic;\n\t__be32 rt_crc;\n\t__be64 rt_owner;\n\t__be64 rt_blkno;\n\t__be64 rt_lsn;\n\tuuid_t rt_uuid;\n};\n\nstruct xfs_rtginode_ops {\n\tconst char *name;\n\tenum xfs_metafile_type metafile_type;\n\tunsigned int sick;\n\tunsigned int fmt_mask;\n\tbool (*enabled)(const struct xfs_mount *);\n\tint (*create)(struct xfs_rtgroup *, struct xfs_inode *, struct xfs_trans *, bool);\n};\n\nstruct xfs_rtgroup {\n\tstruct xfs_group rtg_group;\n\tstruct xfs_inode *rtg_inodes[4];\n\txfs_rtxnum_t rtg_extents;\n\tunion {\n\t\tuint8_t *rtg_rsum_cache;\n\t\tstruct xfs_open_zone *rtg_open_zone;\n\t};\n\tatomic_t rtg_gccount;\n};\n\nstruct xfs_rtgroup_geometry {\n\t__u32 rg_number;\n\t__u32 rg_length;\n\t__u32 rg_sick;\n\t__u32 rg_checked;\n\t__u32 rg_flags;\n\t__u32 rg_reserved[27];\n};\n\nstruct xfs_rtrefcount_root {\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n};\n\nstruct xfs_rtrmap_root {\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n};\n\nstruct xfs_rtsb {\n\t__be32 rsb_magicnum;\n\t__le32 rsb_crc;\n\t__be32 rsb_pad;\n\tunsigned char rsb_fname[12];\n\tuuid_t rsb_uuid;\n\tuuid_t rsb_meta_uuid;\n};\n\nunion xfs_rtword_raw {\n\t__u32 old;\n\t__be32 rtg;\n};\n\nstruct xfs_rtx_busy {\n\tstruct list_head list;\n\txfs_rtblock_t bno;\n\txfs_rtblock_t length;\n};\n\nstruct xfs_rud_log_format {\n\tuint16_t rud_type;\n\tuint16_t rud_size;\n\tuint32_t __pad;\n\tuint64_t rud_rui_id;\n};\n\nstruct xfs_rui_log_item;\n\nstruct xfs_rud_log_item {\n\tstruct xfs_log_item rud_item;\n\tstruct xfs_rui_log_item *rud_ruip;\n\tstruct xfs_rud_log_format rud_format;\n};\n\nstruct xfs_rui_log_format {\n\tuint16_t rui_type;\n\tuint16_t rui_size;\n\tuint32_t rui_nextents;\n\tuint64_t rui_id;\n\tstruct xfs_map_extent rui_extents[0];\n};\n\nstruct xfs_rui_log_item {\n\tstruct xfs_log_item rui_item;\n\tatomic_t rui_refcount;\n\tatomic_t rui_next_extent;\n\tstruct xfs_rui_log_format rui_format;\n};\n\ntypedef struct xfs_sb xfs_sb_t;\n\nunion xfs_suminfo_raw {\n\t__u32 old;\n\t__be32 rtg;\n};\n\nstruct xfs_swapext {\n\tint64_t sx_version;\n\tint64_t sx_fdtarget;\n\tint64_t sx_fdtmp;\n\txfs_off_t sx_offset;\n\txfs_off_t sx_length;\n\tchar sx_pad[16];\n\tstruct xfs_bstat sx_stat;\n};\n\ntypedef struct xfs_swapext xfs_swapext_t;\n\nstruct xfs_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, char *);\n\tssize_t (*store)(struct kobject *, const char *, size_t);\n};\n\nstruct xfs_trans {\n\tunsigned int t_log_res;\n\tunsigned int t_log_count;\n\tunsigned int t_blk_res;\n\tunsigned int t_blk_res_used;\n\tunsigned int t_rtx_res;\n\tunsigned int t_rtx_res_used;\n\tunsigned int t_flags;\n\txfs_agnumber_t t_highest_agno;\n\tstruct xlog_ticket *t_ticket;\n\tstruct xfs_mount *t_mountp;\n\tstruct xfs_dquot_acct *t_dqinfo;\n\tint64_t t_icount_delta;\n\tint64_t t_ifree_delta;\n\tint64_t t_fdblocks_delta;\n\tint64_t t_res_fdblocks_delta;\n\tint64_t t_frextents_delta;\n\tint64_t t_res_frextents_delta;\n\tint64_t t_dblocks_delta;\n\tint64_t t_agcount_delta;\n\tint64_t t_imaxpct_delta;\n\tint64_t t_rextsize_delta;\n\tint64_t t_rbmblocks_delta;\n\tint64_t t_rblocks_delta;\n\tint64_t t_rextents_delta;\n\tint64_t t_rextslog_delta;\n\tint64_t t_rgcount_delta;\n\tstruct list_head t_items;\n\tstruct list_head t_busy;\n\tstruct list_head t_dfops;\n\tlong unsigned int t_pflags;\n};\n\ntypedef struct xfs_trans xfs_trans_t;\n\nstruct xfs_trans_header {\n\tuint th_magic;\n\tuint th_type;\n\tint32_t th_tid;\n\tuint th_num_items;\n};\n\nstruct xfs_trim_cur {\n\txfs_agblock_t start;\n\txfs_extlen_t count;\n\txfs_agblock_t end;\n\txfs_extlen_t minlen;\n\tbool by_bno;\n};\n\nstruct xfs_trim_rtdev {\n\tstruct list_head extent_list;\n\txfs_rtblock_t minlen_fsb;\n\txfs_rtxnum_t restart_rtx;\n\txfs_rtxnum_t stop_rtx;\n};\n\nstruct xfs_trim_rtgroup {\n\tstruct xfs_busy_extents *extents;\n\txfs_rtblock_t minlen_fsb;\n\txfs_rtxnum_t restart_rtx;\n\tint batch;\n\tint queued;\n};\n\nstruct xfs_unmount_log_format {\n\tuint16_t magic;\n\tuint16_t pad1;\n\tuint32_t pad2;\n};\n\nstruct xfs_verify_media {\n\t__u32 me_dev;\n\t__u32 me_flags;\n\t__u64 me_start_daddr;\n\t__u64 me_end_daddr;\n\t__u32 me_ioerror;\n\t__u32 me_max_io_size;\n\t__u32 me_rest_us;\n\t__u32 me_pad;\n};\n\nstruct xfs_writepage_ctx {\n\tstruct iomap_writepage_ctx ctx;\n\tunsigned int data_seq;\n\tunsigned int cow_seq;\n};\n\nstruct xfs_xmd_log_format {\n\tuint16_t xmd_type;\n\tuint16_t xmd_size;\n\tuint32_t __pad;\n\tuint64_t xmd_xmi_id;\n};\n\nstruct xfs_xmi_log_item;\n\nstruct xfs_xmd_log_item {\n\tstruct xfs_log_item xmd_item;\n\tstruct xfs_xmi_log_item *xmd_intent_log_item;\n\tstruct xfs_xmd_log_format xmd_format;\n};\n\nstruct xfs_xmi_log_format {\n\tuint16_t xmi_type;\n\tuint16_t xmi_size;\n\tuint32_t __pad;\n\tuint64_t xmi_id;\n\tuint64_t xmi_inode1;\n\tuint64_t xmi_inode2;\n\tuint32_t xmi_igen1;\n\tuint32_t xmi_igen2;\n\tuint64_t xmi_startoff1;\n\tuint64_t xmi_startoff2;\n\tuint64_t xmi_blockcount;\n\tuint64_t xmi_flags;\n\tuint64_t xmi_isize1;\n\tuint64_t xmi_isize2;\n};\n\nstruct xfs_xmi_log_item {\n\tstruct xfs_log_item xmi_item;\n\tatomic_t xmi_refcount;\n\tstruct xfs_xmi_log_format xmi_format;\n};\n\nstruct xfs_zone_alloc_ctx {\n\tstruct xfs_open_zone *open_zone;\n\txfs_filblks_t reserved_blocks;\n};\n\nstruct xfs_zone_gc_iter {\n\tstruct xfs_rtgroup *victim_rtg;\n\tunsigned int rec_count;\n\tunsigned int rec_idx;\n\txfs_agblock_t next_startblock;\n\tstruct xfs_rmap_irec *recs;\n};\n\nstruct xfs_zone_gc_data {\n\tstruct xfs_mount *mp;\n\tstruct bio_set bio_set;\n\tstruct folio *scratch_folios[2];\n\tunsigned int scratch_size;\n\tunsigned int scratch_available;\n\tunsigned int scratch_head;\n\tunsigned int scratch_tail;\n\tstruct list_head reading;\n\tstruct list_head writing;\n\tstruct list_head resetting;\n\tstruct xfs_zone_gc_iter iter;\n};\n\nstruct xfs_zone_info {\n\tspinlock_t zi_reservation_lock;\n\tstruct list_head zi_reclaim_reservations;\n\tspinlock_t zi_open_zones_lock;\n\tstruct list_head zi_open_zones;\n\tunsigned int zi_nr_open_zones;\n\tatomic_t zi_nr_free_zones;\n\twait_queue_head_t zi_zone_wait;\n\tstruct task_struct *zi_gc_thread;\n\tstruct xfs_open_zone *zi_open_gc_zone;\n\tspinlock_t zi_reset_list_lock;\n\tstruct xfs_group *zi_reset_list;\n\tspinlock_t zi_used_buckets_lock;\n\tunsigned int zi_used_bucket_entries[10];\n\tlong unsigned int *zi_used_bucket_bitmap[10];\n};\n\nstruct xfs_zone_reservation {\n\tstruct list_head entry;\n\tstruct task_struct *task;\n\txfs_filblks_t count_fsb;\n};\n\nstruct xfs_zoned_writepage_ctx {\n\tstruct iomap_writepage_ctx ctx;\n\tstruct xfs_open_zone *open_zone;\n};\n\nstruct xfsstats {\n\tunion {\n\t\tstruct __xfsstats s;\n\t\tuint32_t a[262];\n\t};\n};\n\nstruct xlog_grant_head {\n\tspinlock_t lock;\n\tstruct list_head waiters;\n\tatomic64_t grant;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xlog {\n\tstruct xfs_mount *l_mp;\n\tstruct xfs_ail *l_ailp;\n\tstruct xfs_cil *l_cilp;\n\tstruct xfs_buftarg *l_targ;\n\tstruct workqueue_struct *l_ioend_workqueue;\n\tstruct delayed_work l_work;\n\tlong int l_opstate;\n\tuint l_quotaoffs_flag;\n\tstruct list_head *l_buf_cancel_table;\n\tstruct list_head r_dfops;\n\tint l_iclog_hsize;\n\tuint l_sectBBsize;\n\tint l_iclog_size;\n\tint l_iclog_bufs;\n\txfs_daddr_t l_logBBstart;\n\tint l_logsize;\n\tint l_logBBsize;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\twait_queue_head_t l_flush_wait;\n\tint l_covered_state;\n\tstruct xlog_in_core *l_iclog;\n\tspinlock_t l_icloglock;\n\tint l_curr_cycle;\n\tint l_prev_cycle;\n\tint l_curr_block;\n\tint l_prev_block;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t l_tail_lsn;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xlog_grant_head l_reserve_head;\n\tstruct xlog_grant_head l_write_head;\n\tuint64_t l_tail_space;\n\tstruct xfs_kobj l_kobj;\n\txfs_lsn_t l_recovery_lsn;\n\tuint32_t l_iclog_roundoff;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xlog_cil_pcp {\n\tint32_t space_used;\n\tuint32_t space_reserved;\n\tstruct list_head busy_extents;\n\tstruct list_head log_items;\n};\n\nstruct xlog_op_header {\n\t__be32 oh_tid;\n\t__be32 oh_len;\n\t__u8 oh_clientid;\n\t__u8 oh_flags;\n\t__u16 oh_res2;\n};\n\nstruct xlog_cil_trans_hdr {\n\tstruct xlog_op_header oph[2];\n\tstruct xfs_trans_header thdr;\n\tstruct xfs_log_iovec lhdr[2];\n};\n\nstruct xlog_format_buf {\n\tstruct xfs_log_vec *lv;\n\tunsigned int idx;\n};\n\nstruct xlog_rec_header;\n\nstruct xlog_in_core {\n\twait_queue_head_t ic_force_wait;\n\twait_queue_head_t ic_write_wait;\n\tstruct xlog_in_core *ic_next;\n\tstruct xlog_in_core *ic_prev;\n\tstruct xlog *ic_log;\n\tu32 ic_size;\n\tu32 ic_offset;\n\tenum xlog_iclog_state ic_state;\n\tunsigned int ic_flags;\n\tvoid *ic_datap;\n\tstruct list_head ic_callbacks;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t ic_refcnt;\n\tstruct xlog_rec_header *ic_header;\n\tstruct semaphore ic_sema;\n\tstruct work_struct ic_end_io_work;\n\tstruct bio ic_bio;\n\tstruct bio_vec ic_bvec[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xlog_rec_ext_header {\n\t__be32 xh_cycle;\n\t__be32 xh_cycle_data[64];\n\t__u8 xh_reserved[252];\n};\n\nstruct xlog_rec_header {\n\t__be32 h_magicno;\n\t__be32 h_cycle;\n\t__be32 h_version;\n\t__be32 h_len;\n\t__be64 h_lsn;\n\t__be64 h_tail_lsn;\n\t__le32 h_crc;\n\t__be32 h_prev_block;\n\t__be32 h_num_logops;\n\t__be32 h_cycle_data[64];\n\t__be32 h_fmt;\n\tuuid_t h_fs_uuid;\n\t__be32 h_size;\n\t__u32 h_pad0;\n\t__u8 h_reserved[184];\n\tstruct xlog_rec_ext_header h_ext[0];\n};\n\nstruct xlog_recover {\n\tstruct hlist_node r_list;\n\txlog_tid_t r_log_tid;\n\tstruct xfs_trans_header r_theader;\n\tint r_state;\n\txfs_lsn_t r_lsn;\n\tstruct list_head r_itemq;\n};\n\nstruct xlog_recover_item_ops;\n\nstruct xlog_recover_item {\n\tstruct list_head ri_list;\n\tint ri_cnt;\n\tint ri_total;\n\tstruct kvec *ri_buf;\n\tconst struct xlog_recover_item_ops *ri_ops;\n};\n\nstruct xlog_recover_item_ops {\n\tuint16_t item_type;\n\tenum xlog_recover_reorder (*reorder)(struct xlog_recover_item *);\n\tvoid (*ra_pass2)(struct xlog *, struct xlog_recover_item *);\n\tint (*commit_pass1)(struct xlog *, struct xlog_recover_item *);\n\tint (*commit_pass2)(struct xlog *, struct list_head *, struct xlog_recover_item *, xfs_lsn_t);\n};\n\nstruct xlog_ticket {\n\tstruct list_head t_queue;\n\tstruct task_struct *t_task;\n\txlog_tid_t t_tid;\n\tatomic_t t_ref;\n\tint t_curr_res;\n\tint t_unit_res;\n\tchar t_ocnt;\n\tchar t_cnt;\n\tuint8_t t_flags;\n\tint t_iclog_hdrs;\n};\n\nstruct xlog_write_data {\n\tstruct xlog_ticket *ticket;\n\tstruct xlog_in_core *iclog;\n\tuint32_t bytes_left;\n\tuint32_t record_cnt;\n\tuint32_t data_cnt;\n\tint log_offset;\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tlong unsigned int *bitmap;\n\tstruct page *page;\n\tlong unsigned int vaddr;\n};\n\nstruct xor_block_template {\n\tstruct xor_block_template *next;\n\tconst char *name;\n\tint speed;\n\tvoid (*do_2)(long unsigned int, long unsigned int * restrict, const long unsigned int * restrict);\n\tvoid (*do_3)(long unsigned int, long unsigned int * restrict, const long unsigned int * restrict, const long unsigned int * restrict);\n\tvoid (*do_4)(long unsigned int, long unsigned int * restrict, const long unsigned int * restrict, const long unsigned int * restrict, const long unsigned int * restrict);\n\tvoid (*do_5)(long unsigned int, long unsigned int * restrict, const long unsigned int * restrict, const long unsigned int * restrict, const long unsigned int * restrict, const long unsigned int * restrict);\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xsk_addrs {\n\tu32 num_descs;\n\tu64 addrs[18];\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xsk_cb_desc {\n\tvoid *src;\n\tu8 off;\n\tu8 bytes;\n};\n\nstruct xsk_dma_map {\n\tdma_addr_t *dma_pages;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\trefcount_t users;\n\tstruct list_head list;\n\tu32 dma_pages_cnt;\n};\n\nstruct xsk_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tatomic_t count;\n\tstruct xdp_sock *xsk_map[0];\n};\n\nstruct xsk_map_node {\n\tstruct list_head node;\n\tstruct xsk_map *map;\n\tstruct xdp_sock **map_entry;\n};\n\nstruct xsk_queue {\n\tu32 ring_mask;\n\tu32 nentries;\n\tu32 cached_prod;\n\tu32 cached_cons;\n\tstruct xdp_ring *ring;\n\tu64 invalid_descs;\n\tu64 queue_empty_descs;\n\tsize_t ring_vmalloc_size;\n\tspinlock_t cq_cached_prod_lock;\n};\n\nstruct xsk_tx_metadata {\n\t__u64 flags;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 csum_start;\n\t\t\t__u16 csum_offset;\n\t\t\t__u64 launch_time;\n\t\t} request;\n\t\tstruct {\n\t\t\t__u64 tx_timestamp;\n\t\t} completion;\n\t};\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xstats_entry {\n\tchar *desc;\n\tint endpoint;\n};\n\nstruct xts_instance_ctx {\n\tstruct crypto_skcipher_spawn spawn;\n\tstruct crypto_cipher_spawn tweak_spawn;\n};\n\nstruct xts_request_ctx {\n\tle128 t;\n\tstruct scatterlist *tail;\n\tstruct scatterlist sg[2];\n\tstruct skcipher_request subreq;\n};\n\nstruct xts_tfm_ctx {\n\tstruct crypto_skcipher *child;\n\tstruct crypto_cipher *tweak;\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct xz_dec_microlzma {\n\tstruct xz_dec_lzma2 s;\n};\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcomp_strm;\n\nstruct zcomp_ops;\n\nstruct zcomp_params;\n\nstruct zcomp {\n\tstruct zcomp_strm *stream;\n\tconst struct zcomp_ops *ops;\n\tstruct zcomp_params *params;\n\tstruct hlist_node node;\n};\n\nstruct zcomp_ctx {\n\tvoid *context;\n};\n\nstruct zcomp_req;\n\nstruct zcomp_ops {\n\tint (*compress)(struct zcomp_params *, struct zcomp_ctx *, struct zcomp_req *);\n\tint (*decompress)(struct zcomp_params *, struct zcomp_ctx *, struct zcomp_req *);\n\tint (*create_ctx)(struct zcomp_params *, struct zcomp_ctx *);\n\tvoid (*destroy_ctx)(struct zcomp_ctx *);\n\tint (*setup_params)(struct zcomp_params *);\n\tvoid (*release_params)(struct zcomp_params *);\n\tconst char *name;\n};\n\nstruct zcomp_params {\n\tvoid *dict;\n\tsize_t dict_sz;\n\ts32 level;\n\tunion {\n\t\tstruct deflate_params deflate;\n\t};\n\tvoid *drv_data;\n};\n\nstruct zcomp_req {\n\tconst unsigned char *src;\n\tconst size_t src_len;\n\tunsigned char *dst;\n\tsize_t dst_len;\n};\n\nstruct zcomp_strm {\n\tstruct mutex lock;\n\tvoid *buffer;\n\tvoid *local_copy;\n\tstruct zcomp_ctx ctx;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\nstruct zpci_aipb {\n\tu64 faisb;\n\tu64 gait;\n\tshort: 13;\n\tu16 afi: 3;\n\tint: 0;\n\tshort: 16;\n\tu16 faal;\n};\n\nstruct zpci_bar_struct {\n\tstruct resource *res;\n\tvoid *mio_wb;\n\tvoid *mio_wt;\n\tu32 val;\n\tu16 map_idx;\n\tu8 size;\n};\n\nstruct zpci_dev;\n\nstruct zpci_bus {\n\tstruct kref kref;\n\tstruct pci_bus *bus;\n\tstruct zpci_dev *function[256];\n\tstruct list_head resources;\n\tstruct list_head bus_next;\n\tstruct resource bus_resource;\n\tstruct irq_domain *msi_parent_domain;\n\tint topo;\n\tint domain_nr;\n\tu8 multifunction: 1;\n\tu8 topo_is_tid: 1;\n\tenum pci_bus_speed max_bus_speed;\n};\n\nstruct zpci_ccdf_avail {\n\tu32 reserved1;\n\tu32 fh;\n\tu32 fid;\n\tu32 reserved2;\n\tu32 reserved3;\n\tu32 reserved4;\n\tu32 reserved5;\n\tu16 reserved6;\n\tu16 pec;\n};\n\nstruct zpci_ccdf_err {\n\tu32 reserved1;\n\tu32 fh;\n\tu32 fid;\n\tu32 ett: 4;\n\tu32 mvn: 12;\n\tu32 dmaas: 8;\n\tchar: 6;\n\tu32 q: 1;\n\tu32 rw: 1;\n\tu64 faddr;\n\tu32 reserved3;\n\tu16 reserved4;\n\tu16 pec;\n};\n\nstruct zpci_cdiib {\n\tlong: 64;\n\tu64 dibv_addr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kvm_zdev;\n\nstruct zpci_fmb;\n\nstruct zpci_dev {\n\tstruct zpci_bus *zbus;\n\tstruct list_head entry;\n\tstruct list_head iommu_list;\n\tstruct kref kref;\n\tstruct callback_head rcu;\n\tstruct hotplug_slot hotplug_slot;\n\tstruct mutex state_lock;\n\tenum zpci_state state;\n\tu32 fid;\n\tu32 fh;\n\tu32 gisa;\n\tu16 vfn;\n\tu16 pchid;\n\tu16 maxstbl;\n\tu16 rid;\n\tu16 tid;\n\tu8 pfgid;\n\tu8 pft;\n\tu8 port;\n\tu8 fidparm;\n\tu8 dtsm;\n\tu8 rid_available: 1;\n\tu8 has_hp_slot: 1;\n\tu8 has_resources: 1;\n\tu8 is_physfn: 1;\n\tu8 util_str_avail: 1;\n\tu8 tid_avail: 1;\n\tu8 rtr_avail: 1;\n\tunsigned int devfn;\n\tu8 pfip[4];\n\tu32 uid;\n\tu8 util_str[64];\n\tu64 msi_addr;\n\tunsigned int max_msi;\n\tunsigned int msi_first_bit;\n\tunsigned int msi_nr_irqs;\n\tstruct airq_iv *aibv;\n\tlong unsigned int aisb;\n\tlong unsigned int *dma_table;\n\tint tlb_refresh;\n\tstruct iommu_device iommu_dev;\n\tchar res_name[16];\n\tbool mio_capable;\n\tstruct zpci_bar_struct bars[6];\n\tu64 start_dma;\n\tu64 end_dma;\n\tu64 dma_mask;\n\tstruct mutex fmb_lock;\n\tstruct zpci_fmb *fmb;\n\tu16 fmb_update;\n\tu16 fmb_length;\n\tu8 version;\n\tenum pci_bus_speed max_bus_speed;\n\tstruct dentry *debugfs_dev;\n\tstruct iommu_domain *s390_domain;\n\tstruct kvm_zdev *kzdev;\n\tstruct mutex kzdev_lock;\n\tspinlock_t dom_lock;\n};\n\nstruct zpci_diib {\n\tchar: 1;\n\tu32 isc: 3;\n\tint: 0;\n\tshort: 16;\n\tu16 nr_cpus;\n\tu64 disb_addr;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct zpci_err_insn_data {\n\tu8 insn;\n\tu8 cc;\n\tu8 status;\n\tunion {\n\t\tstruct {\n\t\t\tu64 req;\n\t\t\tu64 offset;\n\t\t};\n\t\tstruct {\n\t\t\tu64 addr;\n\t\t\tu64 len;\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct zpci_fib_fmt0 {\n\tchar: 1;\n\tu32 isc: 3;\n\tu32 noi: 12;\n\tchar: 2;\n\tu32 aibvo: 6;\n\tu32 sum: 1;\n\tchar: 1;\n\tu32 aisbo: 6;\n\tu64 aibv;\n\tu64 aisb;\n};\n\nstruct zpci_fib_fmt1 {\n\tchar: 4;\n\tu32 noi: 12;\n\tint: 16;\n\tu32 dibvo: 16;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct zpci_fib {\n\tu32 fmt: 8;\n\tlong: 0;\n\tu8 fc;\n\tu64 pba;\n\tu64 pal;\n\tu64 iota;\n\tunion {\n\t\tstruct zpci_fib_fmt0 fmt0;\n\t\tstruct zpci_fib_fmt1 fmt1;\n\t};\n\tu64 fmb_addr;\n\tint: 32;\n\tu32 gd;\n};\n\nstruct zpci_fmb_fmt0 {\n\tu64 dma_rbytes;\n\tu64 dma_wbytes;\n};\n\nstruct zpci_fmb_fmt1 {\n\tu64 rx_bytes;\n\tu64 rx_packets;\n\tu64 tx_bytes;\n\tu64 tx_packets;\n};\n\nstruct zpci_fmb_fmt2 {\n\tu64 consumed_work_units;\n\tu64 max_work_units;\n};\n\nstruct zpci_fmb_fmt3 {\n\tu64 tx_bytes;\n};\n\nstruct zpci_fmb {\n\tu32 format: 8;\n\tu32 fmt_ind: 24;\n\tu32 samples;\n\tu64 last_update;\n\tu64 ld_ops;\n\tu64 st_ops;\n\tu64 stb_ops;\n\tu64 rpcit_ops;\n\tunion {\n\t\tstruct zpci_fmb_fmt0 fmt0;\n\t\tstruct zpci_fmb_fmt1 fmt1;\n\t\tstruct zpci_fmb_fmt2 fmt2;\n\t\tstruct zpci_fmb_fmt3 fmt3;\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct zpci_iomap_entry {\n\tu32 fh;\n\tu8 bar;\n\tu16 count;\n};\n\nstruct zpci_kvm_hook {\n\tint (*kvm_register)(void *, struct kvm *);\n\tvoid (*kvm_unregister)(void *);\n};\n\nstruct zpci_report_error_header {\n\tu8 version;\n\tu8 action;\n\tu16 length;\n\tu8 data[0];\n};\n\nstruct zpci_report_error_data {\n\tu64 timestamp;\n\tu64 err_log_id;\n\tchar log_data[0];\n};\n\nstruct zpci_report_error {\n\tstruct zpci_report_error_header header;\n\tstruct zpci_report_error_data data;\n} __attribute__((packed));\n\nunion zpci_sic_iib {\n\tstruct zpci_diib diib;\n\tstruct zpci_cdiib cdiib;\n\tstruct zpci_aipb aipb;\n};\n\nstruct zspage;\n\nstruct zpdesc {\n\tlong unsigned int flags;\n\tstruct list_head lru;\n\tlong unsigned int movable_ops;\n\tunion {\n\t\tstruct zpdesc *next;\n\t\tlong unsigned int handle;\n\t};\n\tstruct zspage *zspage;\n\tunsigned int first_obj_offset;\n\tatomic_t _refcount;\n};\n\nstruct zram_stats {\n\tatomic64_t compr_data_size;\n\tatomic64_t failed_reads;\n\tatomic64_t failed_writes;\n\tatomic64_t notify_free;\n\tatomic64_t same_pages;\n\tatomic64_t huge_pages;\n\tatomic64_t huge_pages_since;\n\tatomic64_t pages_stored;\n\tatomic_long_t max_used_pages;\n\tatomic64_t miss_free;\n};\n\nstruct zram_table_entry;\n\nstruct zs_pool;\n\nstruct zram {\n\tstruct zram_table_entry *table;\n\tstruct zs_pool *mem_pool;\n\tstruct zcomp *comps[1];\n\tstruct zcomp_params params[1];\n\tstruct gendisk *disk;\n\tstruct rw_semaphore dev_lock;\n\tlong unsigned int limit_pages;\n\tstruct zram_stats stats;\n\tu64 disksize;\n\tconst char *comp_algs[1];\n\ts8 num_active_comps;\n\tbool claim;\n};\n\nstruct zram_table_entry {\n\tlong unsigned int handle;\n\tunion {\n\t\tlong unsigned int __lock;\n\t\tstruct attr attr;\n\t};\n\tstruct lockdep_map dep_map;\n};\n\nstruct zs_pool_stats {\n\tatomic_long_t pages_compacted;\n};\n\nstruct zs_pool {\n\tconst char *name;\n\tstruct size_class *size_class[255];\n\tatomic_long_t pages_allocated;\n\tstruct zs_pool_stats stats;\n\tstruct shrinker *shrinker;\n\tstruct dentry *stat_dentry;\n\tstruct work_struct free_work;\n\trwlock_t lock;\n\tatomic_t compaction_in_progress;\n};\n\nstruct zspage_lock {\n\tspinlock_t lock;\n\tint cnt;\n\tstruct lockdep_map dep_map;\n};\n\nstruct zspage {\n\tstruct {\n\t\tunsigned int huge: 1;\n\t\tunsigned int fullness: 4;\n\t\tunsigned int class: 9;\n\t\tunsigned int magic: 8;\n\t};\n\tunsigned int inuse;\n\tunsigned int freeobj;\n\tstruct zpdesc *first_zpdesc;\n\tstruct list_head list;\n\tstruct zs_pool *pool;\n\tstruct zspage_lock zsl;\n};\n\nstruct zstd_ctx {\n\tzstd_cctx *cctx;\n\tzstd_dctx *dctx;\n\tvoid *cctx_mem;\n\tvoid *dctx_mem;\n};\n\nstruct zstd_params {\n\tzstd_custom_mem custom_mem;\n\tzstd_cdict *cdict;\n\tzstd_ddict *ddict;\n\tzstd_parameters cprm;\n};\n\nstruct zstd_workspace_manager {\n\tspinlock_t lock;\n\tstruct list_head lru_list;\n\tstruct list_head idle_ws[15];\n\tlong unsigned int active_map;\n\twait_queue_head_t wait;\n\tstruct timer_list timer;\n};\n\nstruct zswap_pool;\n\nstruct zswap_entry {\n\tswp_entry_t swpentry;\n\tunsigned int length;\n\tbool referenced;\n\tstruct zswap_pool *pool;\n\tlong unsigned int handle;\n\tstruct obj_cgroup *objcg;\n\tstruct list_head lru;\n};\n\nstruct zswap_pool {\n\tstruct zs_pool *zs_pool;\n\tstruct crypto_acomp_ctx *acomp_ctx;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct work_struct release_work;\n\tstruct hlist_node node;\n\tchar tfm_name[128];\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef void (*RecordEvents_f)(Fingerprint *, const void *, size_t);\n\ntypedef size_t (*ZSTD_BlockCompressor_f)(ZSTD_MatchState_t *, SeqStore_t *, U32 *, const void *, size_t);\n\ntypedef size_t (*ZSTD_SequenceCopier_f)(ZSTD_CCtx *, ZSTD_SequencePosition *, const ZSTD_Sequence * const, size_t, const void *, size_t, ZSTD_ParamSwitch_e);\n\ntypedef U32 (*ZSTD_getAllMatchesFn)(ZSTD_match_t *, ZSTD_MatchState_t *, U32 *, const BYTE *, const BYTE *, const U32 *, const U32, const U32);\n\ntypedef int (*ZSTD_match4Found)(const BYTE *, const BYTE *, U32, U32);\n\ntypedef enum ap_sm_wait ap_func_t(struct ap_queue *);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef void blk_log_action_t(struct trace_iterator *, const char *, bool);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u32 (*bpf_prog_run_fn)(const struct bpf_prog *, const void *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_bprm_opts_set)(struct linux_binprm *, u64);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_d_path)(const struct path *, char *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_attach_cookie)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_pe)(struct bpf_perf_event_data_kern *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_trace)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_branch_snapshot)(void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid_curr)(void);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_task)(void);\n\ntypedef u64 (*btf_bpf_get_current_task_btf)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_func_ip_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_local_storage)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sockopt)(struct bpf_sockopt_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_retval)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_pe)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_sleepable)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_pe)(struct bpf_perf_event_data_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack_sleepable)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_ima_file_hash)(struct file *, void *, u32);\n\ntypedef u64 (*btf_bpf_ima_inode_hash)(struct inode *, void *, u32);\n\ntypedef u64 (*btf_bpf_inode_storage_delete)(struct bpf_map *, struct inode *);\n\ntypedef u64 (*btf_bpf_inode_storage_get)(struct bpf_map *, struct inode *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_printf_btf)(struct seq_file *, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_set_retval)(int);\n\ntypedef u64 (*btf_bpf_sk_ancestor_cgroup_id)(struct sock *, int);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_cgroup_id)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_ancestor_cgroup_id)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_cgroup_id)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_get_xfrm_state)(struct sk_buff *, u32, struct bpf_xfrm_state *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_snprintf_btf)(char *, u32, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_sysctl_get_current_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_get_name)(struct bpf_sysctl_kern *, char *, size_t, u64);\n\ntypedef u64 (*btf_bpf_sysctl_get_new_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_set_new_value)(struct bpf_sysctl_kern *, const char *, size_t);\n\ntypedef u64 (*btf_bpf_task_pt_regs)(struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv4)(struct iphdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv4)(struct iphdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_vprintk)(char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_get_func_arg)(void *, u32, u64 *);\n\ntypedef u64 (*btf_get_func_arg_cnt)(void *);\n\ntypedef u64 (*btf_get_func_ret)(void *, u64 *);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*btf_trace_ack_update_msk)(void *, u64, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_add_delayed_data_ref)(void *, const struct btrfs_fs_info *, const struct btrfs_delayed_ref_node *);\n\ntypedef void (*btf_trace_add_delayed_ref_head)(void *, const struct btrfs_fs_info *, const struct btrfs_delayed_ref_head *, int);\n\ntypedef void (*btf_trace_add_delayed_tree_ref)(void *, const struct btrfs_fs_info *, const struct btrfs_delayed_ref_node *);\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alloc_vmap_area)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, struct dirty_throttle_control *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_blk_zone_append_update_request_bio)(void *, struct request *);\n\ntypedef void (*btf_trace_blk_zone_wplug_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_blkdev_zone_mgmt)(void *, struct bio *, sector_t);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_io_done)(void *, struct request *);\n\ntypedef void (*btf_trace_block_io_start)(void *, struct request *);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_error)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_merge)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_split)(void *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\ntypedef void (*btf_trace_bpf_trace_printk)(void *, const char *);\n\ntypedef void (*btf_trace_bpf_trigger_tp)(void *, int);\n\ntypedef void (*btf_trace_bpf_xdp_link_attach_failed)(void *, const char *);\n\ntypedef void (*btf_trace_br_fdb_add)(void *, struct ndmsg *, struct net_device *, const unsigned char *, u16, u16);\n\ntypedef void (*btf_trace_br_fdb_external_learn_add)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16);\n\ntypedef void (*btf_trace_br_fdb_update)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16, long unsigned int);\n\ntypedef void (*btf_trace_br_mdb_full)(void *, const struct net_device *, const struct br_ip *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_btrfs_add_block_group)(void *, const struct btrfs_fs_info *, const struct btrfs_block_group *, int);\n\ntypedef void (*btf_trace_btrfs_add_reclaim_block_group)(void *, const struct btrfs_block_group *);\n\ntypedef void (*btf_trace_btrfs_add_unused_block_group)(void *, const struct btrfs_block_group *);\n\ntypedef void (*btf_trace_btrfs_all_work_done)(void *, const struct btrfs_fs_info *, const void *);\n\ntypedef void (*btf_trace_btrfs_alloc_extent_state)(void *, const struct extent_state *, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_btrfs_chunk_alloc)(void *, const struct btrfs_fs_info *, const struct btrfs_chunk_map *, u64, u64);\n\ntypedef void (*btf_trace_btrfs_chunk_free)(void *, const struct btrfs_fs_info *, const struct btrfs_chunk_map *, u64, u64);\n\ntypedef void (*btf_trace_btrfs_clear_extent_bit)(void *, const struct extent_io_tree *, u64, u64, unsigned int);\n\ntypedef void (*btf_trace_btrfs_convert_extent_bit)(void *, const struct extent_io_tree *, u64, u64, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_btrfs_cow_block)(void *, const struct btrfs_root *, const struct extent_buffer *, const struct extent_buffer *);\n\ntypedef void (*btf_trace_btrfs_done_preemptive_reclaim)(void *, struct btrfs_fs_info *, const struct btrfs_space_info *);\n\ntypedef void (*btf_trace_btrfs_extent_map_shrinker_count)(void *, const struct btrfs_fs_info *, long int);\n\ntypedef void (*btf_trace_btrfs_extent_map_shrinker_remove_em)(void *, const struct btrfs_inode *, const struct extent_map *);\n\ntypedef void (*btf_trace_btrfs_extent_map_shrinker_scan_enter)(void *, const struct btrfs_fs_info *, long int);\n\ntypedef void (*btf_trace_btrfs_extent_map_shrinker_scan_exit)(void *, const struct btrfs_fs_info *, long int, long int);\n\ntypedef void (*btf_trace_btrfs_fail_all_tickets)(void *, struct btrfs_fs_info *, const struct btrfs_space_info *);\n\ntypedef void (*btf_trace_btrfs_failed_cluster_setup)(void *, const struct btrfs_block_group *);\n\ntypedef void (*btf_trace_btrfs_find_cluster)(void *, const struct btrfs_block_group *, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_btrfs_find_free_extent)(void *, const struct btrfs_root *, const struct find_free_extent_ctl *);\n\ntypedef void (*btf_trace_btrfs_find_free_extent_have_block_group)(void *, const struct btrfs_root *, const struct find_free_extent_ctl *, const struct btrfs_block_group *);\n\ntypedef void (*btf_trace_btrfs_find_free_extent_search_loop)(void *, const struct btrfs_root *, const struct find_free_extent_ctl *);\n\ntypedef void (*btf_trace_btrfs_finish_ordered_extent)(void *, const struct btrfs_inode *, u64, u64, bool);\n\ntypedef void (*btf_trace_btrfs_flush_space)(void *, const struct btrfs_fs_info *, u64, u64, int, int, bool);\n\ntypedef void (*btf_trace_btrfs_free_extent_state)(void *, const struct extent_state *, long unsigned int);\n\ntypedef void (*btf_trace_btrfs_get_extent)(void *, const struct btrfs_root *, const struct btrfs_inode *, const struct extent_map *);\n\ntypedef void (*btf_trace_btrfs_get_extent_show_fi_inline)(void *, const struct btrfs_inode *, const struct extent_buffer *, const struct btrfs_file_extent_item *, int, u64);\n\ntypedef void (*btf_trace_btrfs_get_extent_show_fi_regular)(void *, const struct btrfs_inode *, const struct extent_buffer *, const struct btrfs_file_extent_item *, u64);\n\ntypedef void (*btf_trace_btrfs_get_raid_extent_offset)(void *, const struct btrfs_fs_info *, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_btrfs_handle_em_exist)(void *, const struct btrfs_fs_info *, const struct extent_map *, const struct extent_map *, u64, u64);\n\ntypedef void (*btf_trace_btrfs_inode_evict)(void *, const struct inode *);\n\ntypedef void (*btf_trace_btrfs_inode_mod_outstanding_extents)(void *, const struct btrfs_root *, u64, int, unsigned int);\n\ntypedef void (*btf_trace_btrfs_inode_new)(void *, const struct inode *);\n\ntypedef void (*btf_trace_btrfs_inode_request)(void *, const struct inode *);\n\ntypedef void (*btf_trace_btrfs_insert_one_raid_extent)(void *, const struct btrfs_fs_info *, u64, u64, int);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_add)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_dec_test_pending)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_lookup)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_lookup_first)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_lookup_first_range)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_lookup_for_logging)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_lookup_range)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_mark_finished)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_put)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_remove)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_split)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_extent_start)(void *, const struct btrfs_inode *, const struct btrfs_ordered_extent *);\n\ntypedef void (*btf_trace_btrfs_ordered_sched)(void *, const struct btrfs_work *);\n\ntypedef void (*btf_trace_btrfs_prelim_ref_insert)(void *, const struct btrfs_fs_info *, const struct prelim_ref *, const struct prelim_ref *, u64);\n\ntypedef void (*btf_trace_btrfs_prelim_ref_merge)(void *, const struct btrfs_fs_info *, const struct prelim_ref *, const struct prelim_ref *, u64);\n\ntypedef void (*btf_trace_btrfs_qgroup_account_extent)(void *, const struct btrfs_fs_info *, u64, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_btrfs_qgroup_account_extents)(void *, const struct btrfs_fs_info *, const struct btrfs_qgroup_extent_record *, u64);\n\ntypedef void (*btf_trace_btrfs_qgroup_meta_convert)(void *, const struct btrfs_root *, s64);\n\ntypedef void (*btf_trace_btrfs_qgroup_meta_free_all_pertrans)(void *, struct btrfs_root *);\n\ntypedef void (*btf_trace_btrfs_qgroup_meta_reserve)(void *, const struct btrfs_root *, s64, int);\n\ntypedef void (*btf_trace_btrfs_qgroup_num_dirty_extents)(void *, const struct btrfs_fs_info *, u64, u64);\n\ntypedef void (*btf_trace_btrfs_qgroup_release_data)(void *, const struct inode *, u64, u64, u64, int);\n\ntypedef void (*btf_trace_btrfs_qgroup_reserve_data)(void *, const struct inode *, u64, u64, u64, int);\n\ntypedef void (*btf_trace_btrfs_qgroup_trace_extent)(void *, const struct btrfs_fs_info *, const struct btrfs_qgroup_extent_record *, u64);\n\ntypedef void (*btf_trace_btrfs_qgroup_update_counters)(void *, const struct btrfs_fs_info *, const struct btrfs_qgroup *, u64, u64);\n\ntypedef void (*btf_trace_btrfs_qgroup_update_reserve)(void *, const struct btrfs_fs_info *, const struct btrfs_qgroup *, s64, int);\n\ntypedef void (*btf_trace_btrfs_raid_extent_delete)(void *, const struct btrfs_fs_info *, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_btrfs_reclaim_block_group)(void *, const struct btrfs_block_group *);\n\ntypedef void (*btf_trace_btrfs_remove_block_group)(void *, const struct btrfs_block_group *);\n\ntypedef void (*btf_trace_btrfs_reserve_extent)(void *, const struct btrfs_block_group *, const struct find_free_extent_ctl *);\n\ntypedef void (*btf_trace_btrfs_reserve_extent_cluster)(void *, const struct btrfs_block_group *, const struct find_free_extent_ctl *);\n\ntypedef void (*btf_trace_btrfs_reserve_ticket)(void *, const struct btrfs_fs_info *, u64, u64, u64, int, int);\n\ntypedef void (*btf_trace_btrfs_reserved_extent_alloc)(void *, const struct btrfs_fs_info *, u64, u64);\n\ntypedef void (*btf_trace_btrfs_reserved_extent_free)(void *, const struct btrfs_fs_info *, u64, u64);\n\ntypedef void (*btf_trace_btrfs_set_extent_bit)(void *, const struct extent_io_tree *, u64, u64, unsigned int);\n\ntypedef void (*btf_trace_btrfs_setup_cluster)(void *, const struct btrfs_block_group *, const struct btrfs_free_cluster *, u64, int);\n\ntypedef void (*btf_trace_btrfs_skip_unused_block_group)(void *, const struct btrfs_block_group *);\n\ntypedef void (*btf_trace_btrfs_space_reservation)(void *, const struct btrfs_fs_info *, const char *, u64, u64, int);\n\ntypedef void (*btf_trace_btrfs_sync_file)(void *, const struct file *, int);\n\ntypedef void (*btf_trace_btrfs_sync_fs)(void *, const struct btrfs_fs_info *, int);\n\ntypedef void (*btf_trace_btrfs_transaction_commit)(void *, const struct btrfs_fs_info *);\n\ntypedef void (*btf_trace_btrfs_tree_lock)(void *, const struct extent_buffer *, u64);\n\ntypedef void (*btf_trace_btrfs_tree_read_lock)(void *, const struct extent_buffer *, u64);\n\ntypedef void (*btf_trace_btrfs_tree_read_unlock)(void *, const struct extent_buffer *);\n\ntypedef void (*btf_trace_btrfs_tree_unlock)(void *, const struct extent_buffer *);\n\ntypedef void (*btf_trace_btrfs_trigger_flush)(void *, const struct btrfs_fs_info *, u64, u64, int, const char *);\n\ntypedef void (*btf_trace_btrfs_truncate_show_fi_inline)(void *, const struct btrfs_inode *, const struct extent_buffer *, const struct btrfs_file_extent_item *, int, u64);\n\ntypedef void (*btf_trace_btrfs_truncate_show_fi_regular)(void *, const struct btrfs_inode *, const struct extent_buffer *, const struct btrfs_file_extent_item *, u64);\n\ntypedef void (*btf_trace_btrfs_try_tree_read_lock)(void *, const struct extent_buffer *);\n\ntypedef void (*btf_trace_btrfs_work_queued)(void *, const struct btrfs_work *);\n\ntypedef void (*btf_trace_btrfs_work_sched)(void *, const struct btrfs_work *);\n\ntypedef void (*btf_trace_btrfs_workqueue_alloc)(void *, const struct btrfs_workqueue *, const char *);\n\ntypedef void (*btf_trace_btrfs_workqueue_destroy)(void *, const struct btrfs_workqueue *);\n\ntypedef void (*btf_trace_btrfs_writepage_end_io_hook)(void *, const struct btrfs_inode *, u64, u64, int);\n\ntypedef void (*btf_trace_cap_capable)(void *, const struct cred *, struct user_namespace *, const struct user_namespace *, int, int);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rstat_lock_contended)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_locked)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_unlock)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cma_alloc_busy_retry)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_alloc_finish)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_cma_alloc_start)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_release)(void *, const char *, long unsigned int, const struct page *, long unsigned int);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_contention_begin)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_contention_end)(void *, void *, int);\n\ntypedef void (*btf_trace_count_memcg_events)(void *, struct mem_cgroup *, int, long unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_idle_miss)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_csd_function_entry)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_function_exit)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_queue_cpu)(void *, const unsigned int, long unsigned int, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_ctime_ns_xchg)(void *, struct inode *, u32, u32, u32);\n\ntypedef void (*btf_trace_ctime_xchg_skip)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_dax_insert_pfn_mkwrite)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_insert_pfn_mkwrite_no_entry)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_load_hole)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_pmd_fault)(void *, struct inode *, struct vm_fault *, long unsigned int, int);\n\ntypedef void (*btf_trace_dax_pmd_fault_done)(void *, struct inode *, struct vm_fault *, long unsigned int, int);\n\ntypedef void (*btf_trace_dax_pmd_load_hole)(void *, struct inode *, struct vm_fault *, struct folio *, void *);\n\ntypedef void (*btf_trace_dax_pmd_load_hole_fallback)(void *, struct inode *, struct vm_fault *, struct folio *, void *);\n\ntypedef void (*btf_trace_dax_pte_fault)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_pte_fault_done)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_writeback_one)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dax_writeback_range)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dax_writeback_range_done)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_devlink_health_recover_aborted)(void *, const struct devlink *, const char *, bool, u64);\n\ntypedef void (*btf_trace_devlink_health_report)(void *, const struct devlink *, const char *, const char *);\n\ntypedef void (*btf_trace_devlink_health_reporter_state_update)(void *, const struct devlink *, const char *, bool);\n\ntypedef void (*btf_trace_devlink_hwerr)(void *, const struct devlink *, int, const char *);\n\ntypedef void (*btf_trace_devlink_hwmsg)(void *, const struct devlink *, bool, long unsigned int, const u8 *, size_t);\n\ntypedef void (*btf_trace_devlink_trap_report)(void *, const struct devlink *, struct sk_buff *, const struct devlink_trap_metadata *);\n\ntypedef void (*btf_trace_devres_log)(void *, struct device *, const char *, void *, const char *, size_t);\n\ntypedef void (*btf_trace_disk_zone_wplug_add_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_dma_alloc)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt_err)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_buf_detach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_dynamic_attach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_export)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_fd)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_get)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_mmap)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_mmap_internal)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_put)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_free)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_map_phys)(void *, struct device *, phys_addr_t, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg_err)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_sync_sg_for_cpu)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_sg_for_device)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_cpu)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_device)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_unmap_phys)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_unmap_sg)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dql_stall_detected)(void *, short unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_error_report_end)(void *, enum error_detector, long unsigned int);\n\ntypedef void (*btf_trace_exit_mmap)(void *, struct mm_struct *);\n\ntypedef void (*btf_trace_ext4_alloc_da_blocks)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_allocate_blocks)(void *, struct ext4_allocation_request *, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_allocate_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_begin_ordered_truncate)(void *, struct inode *, loff_t);\n\ntypedef void (*btf_trace_ext4_collapse_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_da_release_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_reserve_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_update_reserve_space)(void *, struct inode *, int, int);\n\ntypedef void (*btf_trace_ext4_da_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_end)(void *, struct inode *, loff_t, loff_t, struct writeback_control *, int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_start)(void *, struct inode *, loff_t, loff_t, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages_extent)(void *, struct inode *, struct ext4_map_blocks *);\n\ntypedef void (*btf_trace_ext4_discard_blocks)(void *, struct super_block *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_discard_preallocations)(void *, struct inode *, unsigned int);\n\ntypedef void (*btf_trace_ext4_drop_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_error)(void *, struct super_block *, const char *, unsigned int);\n\ntypedef void (*btf_trace_ext4_es_cache_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_exit)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_insert_delayed_extent)(void *, struct inode *, struct extent_status *, bool, bool);\n\ntypedef void (*btf_trace_ext4_es_insert_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_exit)(void *, struct inode *, struct extent_status *, int);\n\ntypedef void (*btf_trace_ext4_es_remove_extent)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_shrink)(void *, struct super_block *, int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_count)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_enter)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_exit)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_enter)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_fastpath)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_handle_unwritten_extents)(void *, struct inode *, struct ext4_map_blocks *, int, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_load_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space_done)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, struct partial_cluster *, __le16);\n\ntypedef void (*btf_trace_ext4_ext_rm_idx)(void *, struct inode *, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_rm_leaf)(void *, struct inode *, ext4_lblk_t, struct ext4_extent *, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_show_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t, short unsigned int);\n\ntypedef void (*btf_trace_ext4_fallocate_enter)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_fallocate_exit)(void *, struct inode *, loff_t, unsigned int, int);\n\ntypedef void (*btf_trace_ext4_fc_cleanup)(void *, journal_t *, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_start)(void *, struct super_block *, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_stop)(void *, struct super_block *, int, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_replay)(void *, struct super_block *, int, int, int, int);\n\ntypedef void (*btf_trace_ext4_fc_replay_scan)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_fc_stats)(void *, struct super_block *);\n\ntypedef void (*btf_trace_ext4_fc_track_create)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_inode)(void *, handle_t *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_link)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_range)(void *, handle_t *, struct inode *, long int, long int, int);\n\ntypedef void (*btf_trace_ext4_fc_track_unlink)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_forget)(void *, struct inode *, int, __u64);\n\ntypedef void (*btf_trace_ext4_free_blocks)(void *, struct inode *, __u64, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_fsmap_high_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_low_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_mapping)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_get_implied_cluster_alloc_exit)(void *, struct super_block *, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_getfsmap_high_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_low_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_mapping)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_insert_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journal_start_inode)(void *, struct inode *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_reserved)(void *, struct super_block *, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_sb)(void *, struct super_block *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journalled_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_lazy_itable_init)(void *, struct super_block *, ext4_group_t);\n\ntypedef void (*btf_trace_ext4_load_inode)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_load_inode_bitmap)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mark_inode_dirty)(void *, struct inode *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_buddy_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_discard_preallocations)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_mb_new_group_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_new_inode_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_group_pa)(void *, struct super_block *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_inode_pa)(void *, struct ext4_prealloc_space *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_mballoc_alloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_discard)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_free)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_prealloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_move_extent_enter)(void *, struct inode *, struct ext4_map_blocks *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_move_extent_exit)(void *, struct inode *, ext4_lblk_t, struct inode *, ext4_lblk_t, unsigned int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_nfs_commit_metadata)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_other_inode_update_time)(void *, struct inode *, ino_t);\n\ntypedef void (*btf_trace_ext4_prefetch_bitmaps)(void *, struct super_block *, ext4_group_t, ext4_group_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_punch_hole)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_read_block_bitmap_load)(void *, struct super_block *, long unsigned int, bool);\n\ntypedef void (*btf_trace_ext4_read_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_release_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_remove_blocks)(void *, struct inode *, struct ext4_extent *, ext4_lblk_t, ext4_fsblk_t, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_request_blocks)(void *, struct ext4_allocation_request *);\n\ntypedef void (*btf_trace_ext4_request_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_shutdown)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_sync_file_enter)(void *, struct file *, int);\n\ntypedef void (*btf_trace_ext4_sync_file_exit)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_sync_fs)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_trim_all_free)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_trim_extent)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_truncate_enter)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_truncate_exit)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_unlink_enter)(void *, struct inode *, struct dentry *);\n\ntypedef void (*btf_trace_ext4_unlink_exit)(void *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_update_sb)(void *, struct super_block *, ext4_fsblk_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_writepages)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_writepages_result)(void *, struct inode *, struct writeback_control *, int, int);\n\ntypedef void (*btf_trace_ext4_zero_range)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_extent_writepage)(void *, const struct folio *, const struct inode *, const struct writeback_control *);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_fdb_delete)(void *, struct net_bridge *, struct net_bridge_fdb_entry *);\n\ntypedef void (*btf_trace_fib6_table_lookup)(void *, const struct net *, const struct fib6_result *, struct fib6_table *, const struct flowi6 *);\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_fill_mg_cmtime)(void *, struct inode *, struct timespec64 *, struct timespec64 *);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_flush_foreign)(void *, struct bdi_writeback *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_folio_wait_writeback)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_free_vmap_area_noflush)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_fsverity_enable)(void *, const struct inode *, const struct merkle_tree_params *);\n\ntypedef void (*btf_trace_fsverity_merkle_hit)(void *, const struct inode *, u64, long unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_fsverity_tree_done)(void *, const struct inode *, const struct fsverity_info *, const struct merkle_tree_params *);\n\ntypedef void (*btf_trace_fsverity_verify_data_block)(void *, const struct inode *, const struct merkle_tree_params *, u64);\n\ntypedef void (*btf_trace_fsverity_verify_merkle_block)(void *, const struct inode *, long unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_fuse_request_end)(void *, const struct fuse_req *);\n\ntypedef void (*btf_trace_fuse_request_send)(void *, const struct fuse_req *);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_get_mapping_status)(void *, struct mptcp_ext *);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_guest_halt_poll_ns)(void *, bool, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_handshake_cancel)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_busy)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_none)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cmd_accept)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_accept_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_complete)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_destruct)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_notify_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_submit)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_submit_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_setup)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hugetlbfs_alloc_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_hugetlbfs_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_fallocate)(void *, struct inode *, int, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_hugetlbfs_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_setattr)(void *, struct inode *, struct dentry *, struct iattr *);\n\ntypedef void (*btf_trace_icmp_send)(void *, const struct sk_buff *, int, int);\n\ntypedef void (*btf_trace_inet_sk_error_report)(void *, const struct sock *);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_inode_foreign_history)(void *, struct inode *, struct writeback_control *, unsigned int);\n\ntypedef void (*btf_trace_inode_set_ctime_to_ts)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_inode_switch_wbs)(void *, struct inode *, struct bdi_writeback *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_inode_switch_wbs_queue)(void *, struct bdi_writeback *, struct bdi_writeback *, unsigned int);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, struct io_ring_ctx *, void *, struct io_uring_cqe *);\n\ntypedef void (*btf_trace_io_uring_cqe_overflow)(void *, void *, long long unsigned int, s32, u32, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_local_work_run)(void *, void *, int, unsigned int);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, struct io_kiocb *, int, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, struct io_kiocb *, bool);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, long int);\n\ntypedef void (*btf_trace_io_uring_req_failed)(void *, const struct io_uring_sqe *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_short_write)(void *, void *, u64, u64, u64);\n\ntypedef void (*btf_trace_io_uring_submit_req)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_task_work_run)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_iocost_inuse_adjust)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_inuse_shortage)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_inuse_transfer)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_ioc_vrate_adj)(void *, struct ioc *, u64, u32 *, u32, int, int);\n\ntypedef void (*btf_trace_iocost_iocg_activate)(void *, struct ioc_gq *, const char *, struct ioc_now *, u64, u64, u64);\n\ntypedef void (*btf_trace_iocost_iocg_forgive_debt)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_iocost_iocg_idle)(void *, struct ioc_gq *, const char *, struct ioc_now *, u64, u64, u64);\n\ntypedef void (*btf_trace_iomap_add_to_ioend)(void *, struct inode *, u64, unsigned int, struct iomap *);\n\ntypedef void (*btf_trace_iomap_dio_complete)(void *, struct kiocb *, int, ssize_t);\n\ntypedef void (*btf_trace_iomap_dio_invalidate_fail)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_dio_rw_begin)(void *, struct kiocb *, struct iov_iter *, unsigned int, size_t);\n\ntypedef void (*btf_trace_iomap_dio_rw_queued)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_invalidate_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_iter)(void *, struct iomap_iter *, const void *, long unsigned int);\n\ntypedef void (*btf_trace_iomap_iter_dstmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_iter_srcmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_release_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_writeback_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_zero_iter)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_ipi_send_cpu)(void *, const unsigned int, long unsigned int, void *);\n\ntypedef void (*btf_trace_ipi_send_cpumask)(void *, const struct cpumask *, long unsigned int, void *);\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_jbd2_checkpoint)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_checkpoint_stats)(void *, dev_t, tid_t, struct transaction_chp_stats_s *);\n\ntypedef void (*btf_trace_jbd2_commit_flushing)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_locking)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_logging)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_drop_transaction)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_end_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_handle_extend)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int);\n\ntypedef void (*btf_trace_jbd2_handle_restart)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_start)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_stats)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int, int, int);\n\ntypedef void (*btf_trace_jbd2_lock_buffer_stall)(void *, dev_t, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_run_stats)(void *, dev_t, tid_t, struct transaction_run_stats_s *);\n\ntypedef void (*btf_trace_jbd2_shrink_checkpoint_list)(void *, journal_t *, tid_t, tid_t, tid_t, long unsigned int, tid_t);\n\ntypedef void (*btf_trace_jbd2_shrink_count)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_enter)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_exit)(void *, journal_t *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_start_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_submit_inode_data)(void *, struct inode *);\n\ntypedef void (*btf_trace_jbd2_update_log_tail)(void *, journal_t *, tid_t, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_write_superblock)(void *, journal_t *, blk_opf_t);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *, enum skb_drop_reason, struct sock *);\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, struct kmem_cache *, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *, const struct kmem_cache *);\n\ntypedef void (*btf_trace_ksm_advisor)(void *, s64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ksm_enter)(void *, void *);\n\ntypedef void (*btf_trace_ksm_exit)(void *, void *);\n\ntypedef void (*btf_trace_ksm_merge_one_page)(void *, long unsigned int, void *, void *, int);\n\ntypedef void (*btf_trace_ksm_merge_with_ksm_page)(void *, void *, long unsigned int, void *, void *, int);\n\ntypedef void (*btf_trace_ksm_remove_ksm_page)(void *, long unsigned int);\n\ntypedef void (*btf_trace_ksm_remove_rmap_item)(void *, long unsigned int, void *, void *);\n\ntypedef void (*btf_trace_ksm_start_scan)(void *, int, u32);\n\ntypedef void (*btf_trace_ksm_stop_scan)(void *, int, u32);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, dev_t, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_latency)(void *, dev_t, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, dev_t, const char *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lease *, struct file_lease *);\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ma_op)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_read)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_write)(void *, const char *, struct ma_state *, long unsigned int, void *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_mark_victim)(void *, struct task_struct *, uid_t);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_memcg_flush_stats)(void *, struct mem_cgroup *, s64, bool, bool);\n\ntypedef void (*btf_trace_mm_calculate_totalreserve_pages)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page)(void *, struct mm_struct *, int, int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page_isolate)(void *, struct folio *, int, int, int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page_swapin)(void *, struct mm_struct *, int, int, int);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, struct compact_control *, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, struct compact_control *, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_fast_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_fault)(void *, struct address_space *, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_get_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_map_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_khugepaged_collapse_file)(void *, struct mm_struct *, struct folio *, long unsigned int, long unsigned int, bool, struct file *, int, int);\n\ntypedef void (*btf_trace_mm_khugepaged_scan_file)(void *, struct mm_struct *, struct folio *, struct file *, int, int, int);\n\ntypedef void (*btf_trace_mm_khugepaged_scan_pmd)(void *, struct mm_struct *, struct folio *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_migrate_pages_start)(void *, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_lowmem_reserve)(void *, struct zone *, struct zone *, long int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_wmarks)(void *, struct zone *);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_clear_hopeless)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_reclaim_fail)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_reclaim_pages)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *);\n\ntypedef void (*btf_trace_mm_vmscan_throttled)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_write_folio)(void *, struct folio *);\n\ntypedef void (*btf_trace_mmap_lock_acquire_returned)(void *, struct mm_struct *, bool, bool);\n\ntypedef void (*btf_trace_mmap_lock_released)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmap_lock_start_locking)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mod_memcg_lruvec_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_mod_memcg_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_mptcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_mptcp_sendmsg_frag)(void *, struct mptcp_ext *);\n\ntypedef void (*btf_trace_mptcp_subflow_get_send)(void *, struct mptcp_subflow_context *);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netlink_extack)(void *, const char *);\n\ntypedef void (*btf_trace_notifier_register)(void *, void *);\n\ntypedef void (*btf_trace_notifier_run)(void *, void *);\n\ntypedef void (*btf_trace_notifier_unregister)(void *, void *);\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_page_cache_async_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_ra_order)(void *, struct inode *, long unsigned int, struct file_ra_state *);\n\ntypedef void (*btf_trace_page_cache_ra_unbounded)(void *, struct inode *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_sync_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_pool_release)(void *, const struct page_pool *, s32, u32, u32);\n\ntypedef void (*btf_trace_page_pool_state_hold)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_state_release)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_update_nid)(void *, const struct page_pool *, int);\n\ntypedef void (*btf_trace_pci_hp_event)(void *, const char *, const char *, const int);\n\ntypedef void (*btf_trace_pcie_link_event)(void *, struct pci_bus *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pelt_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_pelt_dl_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_hw_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_irq_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_rt_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, long unsigned int, bool, bool, size_t, size_t, void *, int, void *, size_t, gfp_t);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_purge_vmap_area_lazy)(void *, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_enqueue)(void *, struct Qdisc *, const struct netdev_queue *, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_raid56_read)(void *, const struct btrfs_raid_bio *, const struct bio *, const struct raid56_bio_trace_info *);\n\ntypedef void (*btf_trace_raid56_write)(void *, const struct btrfs_raid_bio *, const struct bio *, const struct raid56_bio_trace_info *);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_invoke_kvfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_segcb_stats)(void *, struct rcu_segcblist *, const char *);\n\ntypedef void (*btf_trace_rcu_sr_normal)(void *, const char *, struct callback_head *, const char *);\n\ntypedef void (*btf_trace_rcu_stall_warning)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_watching)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_migration_pmd)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_remove_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int);\n\ntypedef void (*btf_trace_run_delayed_data_ref)(void *, const struct btrfs_fs_info *, const struct btrfs_delayed_ref_node *);\n\ntypedef void (*btf_trace_run_delayed_ref_head)(void *, const struct btrfs_fs_info *, const struct btrfs_delayed_ref_head *, int);\n\ntypedef void (*btf_trace_run_delayed_tree_ref)(void *, const struct btrfs_fs_info *, const struct btrfs_delayed_ref_node *);\n\ntypedef void (*btf_trace_s390_ap_dqap)(void *, u16, u16, u32, u64);\n\ntypedef void (*btf_trace_s390_ap_nqap)(void *, u16, u16, u32, u64);\n\ntypedef void (*btf_trace_s390_cio_adapter_int)(void *, struct tpi_info *);\n\ntypedef void (*btf_trace_s390_cio_chsc)(void *, struct chsc_header *, int);\n\ntypedef void (*btf_trace_s390_cio_csch)(void *, struct subchannel_id, int);\n\ntypedef void (*btf_trace_s390_cio_hsch)(void *, struct subchannel_id, int);\n\ntypedef void (*btf_trace_s390_cio_interrupt)(void *, struct tpi_info *);\n\ntypedef void (*btf_trace_s390_cio_msch)(void *, struct subchannel_id, struct schib *, int);\n\ntypedef void (*btf_trace_s390_cio_rsch)(void *, struct subchannel_id, int);\n\ntypedef void (*btf_trace_s390_cio_ssch)(void *, struct subchannel_id, union orb *, int);\n\ntypedef void (*btf_trace_s390_cio_stcrw)(void *, struct crw *, int);\n\ntypedef void (*btf_trace_s390_cio_stsch)(void *, struct subchannel_id, struct schib *, int);\n\ntypedef void (*btf_trace_s390_cio_tpi)(void *, struct tpi_info *, int);\n\ntypedef void (*btf_trace_s390_cio_tsch)(void *, struct subchannel_id, struct irb *, int);\n\ntypedef void (*btf_trace_s390_cio_xsch)(void *, struct subchannel_id, int);\n\ntypedef void (*btf_trace_s390_diagnose)(void *, short unsigned int);\n\ntypedef void (*btf_trace_s390_hd_rebuild_domains)(void *, int, int);\n\ntypedef void (*btf_trace_s390_hd_work_fn)(void *, int, int, int);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sched_compute_energy_tp)(void *, struct task_struct *, int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_sched_cpu_capacity_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_sched_entry_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_exit_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_ext_bypass_lb)(void *, __u32, __u32, __u32, __u32, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_sched_ext_dump)(void *, const char *);\n\ntypedef void (*btf_trace_sched_ext_event)(void *, const char *, __s64);\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_end)(void *, struct kthread_work *, kthread_work_func_t);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_start)(void *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_kthread_work_queue_work)(void *, struct kthread_worker *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_move_numa)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_overutilized_tp)(void *, struct root_domain *, bool);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_prepare_exec)(void *, struct task_struct *, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_set_need_resched_tp)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_skip_cpuset_numa)(void *, struct task_struct *, nodemask_t *);\n\ntypedef void (*btf_trace_sched_skip_vma_numa)(void *, struct mm_struct *, struct vm_area_struct *, enum numa_vmaskip_reason);\n\ntypedef void (*btf_trace_sched_stat_blocked)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_iowait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_sleep)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_wait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stick_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_swap_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *, unsigned int);\n\ntypedef void (*btf_trace_sched_update_nr_running_tp)(void *, struct rq *, int);\n\ntypedef void (*btf_trace_sched_util_est_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_sched_util_est_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\ntypedef void (*btf_trace_selinux_audited)(void *, struct selinux_audit_data *, char *, char *, const char *);\n\ntypedef void (*btf_trace_set_migration_pmd)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_set_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sk_data_ready)(void *, const struct sock *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_recv_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_sock_send_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_subflow_check_data_avail)(void *, __u8, struct sk_buff *);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_swiotlb_bounced)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_task_prctl_unknown)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef void (*btf_trace_tasklet_entry)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tasklet_exit)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tcp_ao_handshake_failure)(void *, const struct sock *, const struct sk_buff *, const __u8, const __u8, const __u8);\n\ntypedef void (*btf_trace_tcp_bad_csum)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_cong_state_set)(void *, struct sock *, const u8);\n\ntypedef void (*btf_trace_tcp_cwnd_reduction_tp)(void *, const struct sock *, int, int, int);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_hash_ao_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_bad_header)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_mismatch)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_unexpected)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *, const enum sk_rst_reason);\n\ntypedef void (*btf_trace_tcp_sendmsg_locked)(void *, const struct sock *, const struct msghdr *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_test_pages_isolated)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_timer_base_idle)(void *, bool, unsigned int);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_tls_alert_recv)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_alert_send)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_contenttype)(void *, const struct sock *, unsigned char);\n\ntypedef void (*btf_trace_tmigr_connect_child_parent)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_connect_cpu_parent)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_active)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_available)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_unavailable)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_group_set)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_active)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_inactive)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_handle_remote)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_handle_remote_cpu)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_update_events)(void *, struct tmigr_group *, struct tmigr_group *, union tmigr_state, union tmigr_state, u64);\n\ntypedef void (*btf_trace_track_foreign_dirty)(void *, struct folio *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_update_bytes_may_use)(void *, const struct btrfs_fs_info *, const struct btrfs_space_info *, u64, s64);\n\ntypedef void (*btf_trace_update_bytes_pinned)(void *, const struct btrfs_fs_info *, const struct btrfs_space_info *, u64, s64);\n\ntypedef void (*btf_trace_update_bytes_zone_unusable)(void *, const struct btrfs_fs_info *, const struct btrfs_space_info *, u64, s64);\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_watchdog_ping)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_set_timeout)(void *, struct watchdog_device *, unsigned int, int);\n\ntypedef void (*btf_trace_watchdog_start)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_stop)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_wbt_lat)(void *, struct backing_dev_info *, long unsigned int);\n\ntypedef void (*btf_trace_wbt_stat)(void *, struct backing_dev_info *, struct blk_rq_stat *);\n\ntypedef void (*btf_trace_wbt_step)(void *, struct backing_dev_info *, const char *, int, long unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_wbt_timer)(void *, struct backing_dev_info *, unsigned int, int, unsigned int);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_dirty_folio)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, long unsigned int, int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int, struct xdp_cpumap_stats *);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xfs_ag_resv_alloc_extent)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_critical)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_free)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_free_extent)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_init)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_init_error)(void *, const struct xfs_perag *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ag_resv_needed)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_agf)(void *, struct xfs_mount *, struct xfs_agf *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_agfl_free_deferred)(void *, struct xfs_mount *, struct xfs_extent_free_item *);\n\ntypedef void (*btf_trace_xfs_agfl_reset)(void *, struct xfs_mount *, struct xfs_agf *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ail_delete)(void *, struct xfs_log_item *, xfs_lsn_t, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_ail_flushing)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_ail_insert)(void *, struct xfs_log_item *, xfs_lsn_t, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_ail_locked)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_ail_move)(void *, struct xfs_log_item *, xfs_lsn_t, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_ail_pinned)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_ail_push)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_alloc_cur)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_check)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, xfs_extlen_t, bool);\n\ntypedef void (*btf_trace_xfs_alloc_cur_left)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_lookup)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_lookup_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_right)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_exact_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_exact_error)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_exact_notfound)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_alloc_near_busy)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_near_first)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_near_noentry)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_read_agf)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_alloc_size_busy)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_error)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_neither)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_noentry)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_nominleft)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_error)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_freelist)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_notenough)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_allfailed)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_badargs)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_exact_bno)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_finish)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_first_ag)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_loopfailed)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_near_bno)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_noagbp)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_nofix)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_skip_deadlock)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_start_ag)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_this_ag)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_attr_defer_add)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add_new)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add_old)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add_work)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_addname_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_clearflag)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_compact)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_flipflags)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_get)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_list)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_rebalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_remove)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_setflag)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_split_after)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_split_before)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_to_node)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_to_sf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_toosmall)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_unbalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_list_add)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_full)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_leaf)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_leaf_end)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_node_descend)(void *, struct xfs_attr_list_context *, struct xfs_da_node_entry *);\n\ntypedef void (*btf_trace_xfs_attr_list_notfound)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_sf)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_sf_all)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_wrong_blk)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_node_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_node_addname_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_node_get)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_node_list)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_node_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_rmtval_alloc)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_rmtval_get)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_rmtval_remove_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_set_iter_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_sf_add)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_addname_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_sf_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_remove)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_to_leaf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_blockgc_flush_all)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_blockgc_free_space)(void *, struct xfs_mount *, struct xfs_icwalk *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_blockgc_start)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_blockgc_stop)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_blockgc_worker)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_bmap_defer)(void *, struct xfs_bmap_intent *);\n\ntypedef void (*btf_trace_xfs_bmap_deferred)(void *, struct xfs_bmap_intent *);\n\ntypedef void (*btf_trace_xfs_bmap_post_update)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_bmap_pre_update)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_btree_alloc_block)(void *, struct xfs_btree_cur *, union xfs_btree_ptr *, int, int);\n\ntypedef void (*btf_trace_xfs_btree_bload_block)(void *, struct xfs_btree_cur *, unsigned int, uint64_t, uint64_t, union xfs_btree_ptr *, unsigned int);\n\ntypedef void (*btf_trace_xfs_btree_bload_level_geometry)(void *, struct xfs_btree_cur *, unsigned int, uint64_t, unsigned int, unsigned int, uint64_t, uint64_t);\n\ntypedef void (*btf_trace_xfs_btree_commit_afakeroot)(void *, struct xfs_btree_cur *);\n\ntypedef void (*btf_trace_xfs_btree_commit_ifakeroot)(void *, struct xfs_btree_cur *);\n\ntypedef void (*btf_trace_xfs_btree_corrupt)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_btree_free_block)(void *, struct xfs_btree_cur *, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfs_btree_overlapped_query_range)(void *, struct xfs_btree_cur *, int, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfs_btree_updkeys)(void *, struct xfs_btree_cur *, int, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfs_buf_backing_fallback)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_backing_folio)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_backing_kmem)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_backing_vmalloc)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_delwri_queue)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_delwri_queued)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_delwri_split)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_drain_buftarg)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_error_relse)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_find)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_free)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_get)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_get_uncached)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_hold)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_init)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_iodone)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_iodone_async)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_ioerror)(void *, struct xfs_buf *, int, xfs_failaddr_t);\n\ntypedef void (*btf_trace_xfs_buf_iowait)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_iowait_done)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_item_committed)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_format)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_format_stale)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_ordered)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_pin)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_push)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_release)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_relse)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_item_size)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_size_ordered)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_size_stale)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_unpin)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_unpin_stale)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_lock)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_lock_done)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_read)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_readahead)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_rele)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_submit)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_trylock)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_trylock_fail)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_unlock)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_bunmap)(void *, struct xfs_inode *, xfs_fileoff_t, xfs_filblks_t, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_calc_atomic_write_unit_max)(void *, struct xfs_mount *, enum xfs_group_type, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xfs_calc_max_atomic_write_fsblocks)(void *, struct xfs_mount *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xfs_calc_max_atomic_write_log_geometry)(void *, struct xfs_mount *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xfs_check_new_dalign)(void *, struct xfs_mount *, int, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_cil_whiteout_mark)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_cil_whiteout_skip)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_cil_whiteout_unpin)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_collapse_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_create)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_da_fixhashpath)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_grow_inode)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_join)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_link_after)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_link_before)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_add)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_rebalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_remove)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_toosmall)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_unbalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_path_shift)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_root_join)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_root_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_shrink_inode)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_swap_lastblock)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_unlink_back)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_unlink_forward)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_defer_add_item)(void *, struct xfs_mount *, struct xfs_defer_pending *, void *);\n\ntypedef void (*btf_trace_xfs_defer_cancel)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_cancel_item)(void *, struct xfs_mount *, struct xfs_defer_pending *, void *);\n\ntypedef void (*btf_trace_xfs_defer_cancel_list)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_create_intent)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_finish)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_finish_done)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_finish_error)(void *, struct xfs_trans *, int);\n\ntypedef void (*btf_trace_xfs_defer_finish_item)(void *, struct xfs_mount *, struct xfs_defer_pending *, void *);\n\ntypedef void (*btf_trace_xfs_defer_isolate_paused)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_item_pause)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_item_unpause)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_pending_abort)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_pending_finish)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_relog_intent)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_trans_abort)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_trans_roll)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_trans_roll_error)(void *, struct xfs_trans *, int);\n\ntypedef void (*btf_trace_xfs_delalloc_enospc)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_destroy_inode)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_dir2_block_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_to_leaf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_to_sf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_grow_inode)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_to_block)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_to_node)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leafn_add)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir2_leafn_moveents)(void *, struct xfs_da_args *, int, int, int);\n\ntypedef void (*btf_trace_xfs_dir2_leafn_remove)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir2_node_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_to_leaf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_to_block)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_toino4)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_toino8)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_shrink_inode)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir_fsync)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_discard_busy)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_discard_exclude)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_discard_extent)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_discard_rtextent)(void *, struct xfs_mount *, xfs_rtblock_t, xfs_rtblock_t);\n\ntypedef void (*btf_trace_xfs_discard_rttoosmall)(void *, struct xfs_mount *, xfs_rtblock_t, xfs_rtblock_t);\n\ntypedef void (*btf_trace_xfs_discard_toosmall)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_dqadjust)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqalloc)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqattach_get)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqflush)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqflush_done)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqflush_force)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_dup)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_freeing)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_hit)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_miss)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqread)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqread_fail)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqreclaim_busy)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqreclaim_done)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqreclaim_want)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqrele)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqrele_free)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqtobp_read)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dquot_dqalloc)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_dquot_dqdetach)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_end_io_direct_write)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_exchmaps_defer)(void *, struct xfs_mount *, const struct xfs_exchmaps_intent *);\n\ntypedef void (*btf_trace_xfs_exchmaps_delta_nextents)(void *, const struct xfs_exchmaps_req *, int64_t, int64_t);\n\ntypedef void (*btf_trace_xfs_exchmaps_delta_nextents_step)(void *, struct xfs_mount *, const struct xfs_bmbt_irec *, const struct xfs_bmbt_irec *, const struct xfs_bmbt_irec *, const struct xfs_bmbt_irec *, int, unsigned int);\n\ntypedef void (*btf_trace_xfs_exchmaps_final_estimate)(void *, const struct xfs_exchmaps_req *);\n\ntypedef void (*btf_trace_xfs_exchmaps_initial_estimate)(void *, const struct xfs_exchmaps_req *);\n\ntypedef void (*btf_trace_xfs_exchmaps_mapping1)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_exchmaps_mapping1_skip)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_exchmaps_mapping2)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_exchmaps_overhead)(void *, struct xfs_mount *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_xfs_exchmaps_recover)(void *, struct xfs_mount *, const struct xfs_exchmaps_intent *);\n\ntypedef void (*btf_trace_xfs_exchmaps_update_inode_size)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_exchrange_after)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_exchrange_before)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_exchrange_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_exchrange_flush)(void *, const struct xfs_exchrange *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_exchrange_freshness)(void *, const struct xfs_exchrange *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_exchrange_mappings)(void *, const struct xfs_exchrange *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_exchrange_prep)(void *, const struct xfs_exchrange *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_extent_busy)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_clear)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_force)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_reuse)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_trim)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_free_defer)(void *, struct xfs_mount *, struct xfs_extent_free_item *);\n\ntypedef void (*btf_trace_xfs_extent_free_deferred)(void *, struct xfs_mount *, struct xfs_extent_free_item *);\n\ntypedef void (*btf_trace_xfs_file_buffered_read)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_buffered_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_dax_read)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_dax_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_direct_read)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_direct_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_fsync)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_file_ioctl)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_file_splice_read)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_filestream_free)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_filestream_lookup)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_filestream_pick)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_filestream_scan)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_force_shutdown)(void *, struct xfs_mount *, int, int, const char *, int);\n\ntypedef void (*btf_trace_xfs_free_extent)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_extlen_t, enum xfs_ag_resv_type, int, int);\n\ntypedef void (*btf_trace_xfs_free_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_freecounter_enospc)(void *, struct xfs_mount *, enum xfs_free_counter, uint64_t, long unsigned int);\n\ntypedef void (*btf_trace_xfs_freecounter_reserved)(void *, struct xfs_mount *, enum xfs_free_counter, uint64_t, long unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_mark_corrupt)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_mark_healthy)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_mark_sick)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_sync_fs)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_fs_unfixed_corruption)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fsmap_high_group_key)(void *, struct xfs_mount *, u32, xfs_agnumber_t, const struct xfs_rmap_irec *);\n\ntypedef void (*btf_trace_xfs_fsmap_high_linear_key)(void *, struct xfs_mount *, u32, uint64_t);\n\ntypedef void (*btf_trace_xfs_fsmap_low_group_key)(void *, struct xfs_mount *, u32, xfs_agnumber_t, const struct xfs_rmap_irec *);\n\ntypedef void (*btf_trace_xfs_fsmap_low_linear_key)(void *, struct xfs_mount *, u32, uint64_t);\n\ntypedef void (*btf_trace_xfs_fsmap_mapping)(void *, struct xfs_mount *, u32, xfs_agnumber_t, const struct xfs_fsmap_irec *);\n\ntypedef void (*btf_trace_xfs_get_acl)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_getattr)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_getfsmap_high_key)(void *, struct xfs_mount *, struct xfs_fsmap *);\n\ntypedef void (*btf_trace_xfs_getfsmap_low_key)(void *, struct xfs_mount *, struct xfs_fsmap *);\n\ntypedef void (*btf_trace_xfs_getfsmap_mapping)(void *, struct xfs_mount *, struct xfs_fsmap *);\n\ntypedef void (*btf_trace_xfs_getparents_begin)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attrlist_cursor_kern *);\n\ntypedef void (*btf_trace_xfs_getparents_end)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attrlist_cursor_kern *);\n\ntypedef void (*btf_trace_xfs_getparents_expand_lastrec)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attr_list_context *, const struct xfs_getparents_rec *);\n\ntypedef void (*btf_trace_xfs_getparents_put_listent)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attr_list_context *, const struct xfs_getparents_rec *);\n\ntypedef void (*btf_trace_xfs_group_get)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_grab)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_grab_next_tag)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_hold)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_mark_corrupt)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_group_mark_healthy)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_group_mark_sick)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_group_put)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_rele)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_unfixed_corruption)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_growfs_check_rtgeom)(void *, const struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_healthmon_copybuf)(void *, const struct xfs_healthmon *, const struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_healthmon_create)(void *, dev_t, u64, u8);\n\ntypedef void (*btf_trace_xfs_healthmon_detach)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_drop)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_format)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_format_overflow)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_insert)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_lost_event)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_merge)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_pop)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_push)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_read_finish)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_read_start)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_release)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_file_ioerror)(void *, const struct xfs_healthmon *, const struct fserror_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_fs)(void *, const struct xfs_healthmon *, unsigned int, unsigned int, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_group)(void *, const struct xfs_healthmon *, unsigned int, unsigned int, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_inode)(void *, const struct xfs_healthmon *, unsigned int, unsigned int, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_media)(void *, const struct xfs_healthmon *, enum xfs_device, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_shutdown)(void *, const struct xfs_healthmon *, uint32_t);\n\ntypedef void (*btf_trace_xfs_healthmon_report_unmount)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_ialloc_read_agi)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_iext_insert)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_iext_remove)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_iget_hit)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_miss)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_recycle)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_recycle_fail)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_skip)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_ilock)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ilock_demote)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ilock_nowait)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inactive_symlink)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_clear_cowblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_clear_eofblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_free_cowblocks_invalid)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_free_eofblocks_invalid)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_inactivating)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_mark_corrupt)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_mark_healthy)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_mark_sick)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_pin)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_push_pinned)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_push_stale)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_reclaiming)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_reload_unlinked_bucket)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_cowblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_eofblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_need_inactive)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_reclaimable)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_timestamp_range)(void *, struct xfs_mount *, long long int, long long int);\n\ntypedef void (*btf_trace_xfs_inode_unfixed_corruption)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_unpin)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_unpin_nowait)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inodegc_flush)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_push)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_queue)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_shrinker_scan)(void *, struct xfs_mount *, struct shrink_control *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_start)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_stop)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_throttle)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_worker)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_insert_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_ioc_free_eofblocks)(void *, struct xfs_mount *, struct xfs_icwalk *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ioctl_setattr)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iomap_alloc)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_iomap_atomic_write_cow)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_iomap_found)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_iomap_invalid)(void *, struct xfs_inode *, const struct iomap *);\n\ntypedef void (*btf_trace_xfs_iomap_prealloc_size)(void *, struct xfs_inode *, xfs_fsblock_t, int, unsigned int);\n\ntypedef void (*btf_trace_xfs_irec_merge_post)(void *, const struct xfs_perag *, const struct xfs_inobt_rec_incore *);\n\ntypedef void (*btf_trace_xfs_irec_merge_pre)(void *, const struct xfs_perag *, const struct xfs_inobt_rec_incore *, const struct xfs_inobt_rec_incore *);\n\ntypedef void (*btf_trace_xfs_irele)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_itruncate_extents_end)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_itruncate_extents_start)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_iunlink)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iunlink_reload_next)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iunlink_remove)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iunlink_update_bucket)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xfs_iunlink_update_dinode)(void *, const struct xfs_iunlink_item *, xfs_agino_t);\n\ntypedef void (*btf_trace_xfs_iunlock)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_iwalk_ag_rec)(void *, const struct xfs_perag *, struct xfs_inobt_rec_incore *);\n\ntypedef void (*btf_trace_xfs_link)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_log_assign_tail_lsn)(void *, struct xlog *, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_log_cil_wait)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_force)(void *, struct xfs_mount *, xfs_lsn_t, long unsigned int);\n\ntypedef void (*btf_trace_xfs_log_get_max_trans_res)(void *, struct xfs_mount *, const struct xfs_trans_res *);\n\ntypedef void (*btf_trace_xfs_log_grant_sleep)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_grant_wake)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_grant_wake_up)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_recover)(void *, struct xlog *, xfs_daddr_t, xfs_daddr_t);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_cancel)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_cancel_add)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_cancel_ref_inc)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_dquot_buf)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_inode_buf)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_not_cancel)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_recover)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_reg_buf)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_skip)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_icreate_cancel)(void *, struct xlog *, struct xfs_icreate_log *);\n\ntypedef void (*btf_trace_xfs_log_recover_icreate_recover)(void *, struct xlog *, struct xfs_icreate_log *);\n\ntypedef void (*btf_trace_xfs_log_recover_inode_cancel)(void *, struct xlog *, struct xfs_inode_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_inode_recover)(void *, struct xlog *, struct xfs_inode_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_inode_skip)(void *, struct xlog *, struct xfs_inode_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_item_add)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_add_cont)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_recover)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_reorder_head)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_reorder_tail)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_record)(void *, struct xlog *, struct xlog_rec_header *, int);\n\ntypedef void (*btf_trace_xfs_log_regrant)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_regrant_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_reserve)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_reserve_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_regrant)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_regrant_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_regrant_sub)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_ungrant)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_ungrant_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_ungrant_sub)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_umount_write)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_lookup)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_map_blocks_alloc)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_map_blocks_found)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_metadir_cancel)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_commit)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_create)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_link)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_lookup)(void *, struct xfs_inode *, struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_metadir_start_create)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_start_link)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_teardown)(void *, const struct xfs_metadir_update *, int);\n\ntypedef void (*btf_trace_xfs_metadir_try_create)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metafile_resv_alloc_space)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_critical)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_free)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_free_space)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_init)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_init_error)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_perag_clear_inode_tag)(void *, const struct xfs_perag *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_perag_set_inode_tag)(void *, const struct xfs_perag *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_pwork_init)(void *, struct xfs_mount *, unsigned int, pid_t);\n\ntypedef void (*btf_trace_xfs_quota_expiry_range)(void *, struct xfs_mount *, long long int, long long int);\n\ntypedef void (*btf_trace_xfs_read_agf)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_read_agi)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_read_extent)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_read_fault)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_readdir)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_readlink)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_reclaim_inodes_count)(void *, const struct xfs_perag *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_adjust_cow_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_adjust_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_cow_decrease)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_cow_increase)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_decrease)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_defer)(void *, struct xfs_mount *, struct xfs_refcount_intent *);\n\ntypedef void (*btf_trace_xfs_refcount_deferred)(void *, struct xfs_mount *, struct xfs_refcount_intent *);\n\ntypedef void (*btf_trace_xfs_refcount_delete)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_delete_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_left_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *, xfs_agblock_t);\n\ntypedef void (*btf_trace_xfs_refcount_find_left_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_right_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *, xfs_agblock_t);\n\ntypedef void (*btf_trace_xfs_refcount_find_right_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_shared)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_find_shared_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_shared_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_finish_one_leftover)(void *, struct xfs_mount *, struct xfs_refcount_intent *);\n\ntypedef void (*btf_trace_xfs_refcount_get)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_increase)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_insert)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_insert_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_lookup)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_lookup_t);\n\ntypedef void (*btf_trace_xfs_refcount_merge_center_extents)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_merge_center_extents_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_merge_left_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_merge_left_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_merge_right_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_merge_right_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_modify_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_modify_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_split_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, xfs_agblock_t);\n\ntypedef void (*btf_trace_xfs_refcount_split_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_update)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_update_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_bounce_dio_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_reflink_cancel_cow)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cancel_cow_range)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_reflink_cancel_cow_range_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_convert_cow)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_found)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_remap_from)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_remap_skip)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_remap_to)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_end_cow)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_reflink_end_cow_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_remap_blocks)(void *, struct xfs_inode *, xfs_fileoff_t, xfs_filblks_t, struct xfs_inode *, xfs_fileoff_t);\n\ntypedef void (*btf_trace_xfs_reflink_remap_blocks_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_remap_extent_dest)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_remap_extent_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_remap_extent_src)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_remap_range)(void *, struct xfs_inode *, xfs_off_t, xfs_off_t, struct xfs_inode *, xfs_off_t);\n\ntypedef void (*btf_trace_xfs_reflink_remap_range_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_set_inode_flag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_reflink_set_inode_flag_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_trim_around_shared)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_unset_inode_flag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_reflink_unshare)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_reflink_unshare_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_update_inode_size)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_reflink_update_inode_size_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_remove)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_rename)(void *, struct xfs_inode *, struct xfs_inode *, struct xfs_name *, struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_reset_dqcounts)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_convert)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_convert_done)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_convert_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_convert_state)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_defer)(void *, struct xfs_mount *, struct xfs_rmap_intent *);\n\ntypedef void (*btf_trace_xfs_rmap_deferred)(void *, struct xfs_mount *, struct xfs_rmap_intent *);\n\ntypedef void (*btf_trace_xfs_rmap_delete)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_delete_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_left_neighbor_candidate)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_left_neighbor_query)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_left_neighbor_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_right_neighbor_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_insert)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_insert_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_lookup_le_range)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_lookup_le_range_candidate)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_lookup_le_range_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_map)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_map_done)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_map_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_unmap)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_unmap_done)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_unmap_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_update)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_update_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rtalloc_extent_busy)(void *, struct xfs_rtgroup *, xfs_rtxnum_t, xfs_rtxlen_t, xfs_rtxlen_t, xfs_rtxlen_t, xfs_rtxlen_t, xfs_rtxnum_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rtalloc_extent_busy_trim)(void *, struct xfs_rtgroup *, xfs_rtxnum_t, xfs_rtxlen_t, xfs_rtxnum_t, xfs_rtxlen_t);\n\ntypedef void (*btf_trace_xfs_setattr)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_setfilesize)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_swap_extent_after)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_swap_extent_before)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_swap_extent_rmap_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_swap_extent_rmap_remap)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_swap_extent_rmap_remap_piece)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_symlink)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_trans_add_item)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_alloc)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_apply_dquot_deltas)(void *, struct xfs_dqtrx *);\n\ntypedef void (*btf_trace_xfs_trans_apply_dquot_deltas_after)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_trans_apply_dquot_deltas_before)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_trans_bdetach)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_bhold)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_bhold_release)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_binval)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_bjoin)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_brelse)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_cancel)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_commit)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_commit_items)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_dup)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_free)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_free_abort)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_free_items)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_get_buf)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_get_buf_recur)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_getsb)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_getsb_recur)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_log_buf)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_mod_dquot)(void *, struct xfs_trans *, struct xfs_dquot *, unsigned int, int64_t);\n\ntypedef void (*btf_trace_xfs_trans_mod_dquot_after)(void *, struct xfs_dqtrx *);\n\ntypedef void (*btf_trace_xfs_trans_mod_dquot_before)(void *, struct xfs_dqtrx *);\n\ntypedef void (*btf_trace_xfs_trans_read_buf)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_read_buf_recur)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_read_buf_shut)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_resv_calc)(void *, struct xfs_mount *, unsigned int, struct xfs_trans_res *);\n\ntypedef void (*btf_trace_xfs_trans_resv_calc_minlogsize)(void *, struct xfs_mount *, unsigned int, struct xfs_trans_res *);\n\ntypedef void (*btf_trace_xfs_trans_roll)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_unwritten_convert)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_update_time)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_verify_media)(void *, const struct xfs_mount *, const struct xfs_verify_media *, dev_t, xfs_daddr_t, uint64_t, const struct folio *);\n\ntypedef void (*btf_trace_xfs_verify_media_end)(void *, const struct xfs_mount *, const struct xfs_verify_media *, dev_t);\n\ntypedef void (*btf_trace_xfs_verify_media_error)(void *, const struct xfs_mount *, const struct xfs_verify_media *, dev_t, xfs_daddr_t, uint64_t, blk_status_t);\n\ntypedef void (*btf_trace_xfs_vm_bmap)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_wb_cow_iomap_invalid)(void *, struct xfs_inode *, const struct iomap *, unsigned int, int);\n\ntypedef void (*btf_trace_xfs_wb_data_iomap_invalid)(void *, struct xfs_inode *, const struct iomap *, unsigned int, int);\n\ntypedef void (*btf_trace_xfs_write_extent)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_write_fault)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_zero_eof)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_zero_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_zone_alloc_blocks)(void *, struct xfs_open_zone *, xfs_rgblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_zone_emptied)(void *, struct xfs_rtgroup *);\n\ntypedef void (*btf_trace_xfs_zone_free_blocks)(void *, struct xfs_rtgroup *, xfs_rgblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_zone_full)(void *, struct xfs_rtgroup *);\n\ntypedef void (*btf_trace_xfs_zone_gc_select_victim)(void *, struct xfs_rtgroup *, unsigned int);\n\ntypedef void (*btf_trace_xfs_zone_gc_target_opened)(void *, struct xfs_rtgroup *);\n\ntypedef void (*btf_trace_xfs_zone_opened)(void *, struct xfs_rtgroup *);\n\ntypedef void (*btf_trace_xfs_zone_record_blocks)(void *, struct xfs_open_zone *, xfs_rgblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_zone_reset)(void *, struct xfs_rtgroup *);\n\ntypedef void (*btf_trace_xfs_zone_skip_blocks)(void *, struct xfs_open_zone *, xfs_rgblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_zoned_map_blocks)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_zones_mount)(void *, struct xfs_mount *);\n\ntypedef void (*btf_trace_xlog_ail_insert_abort)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xlog_iclog_activate)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_callback)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_callbacks_done)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_callbacks_start)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_clean)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_force)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_force_lsn)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_get_space)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_release)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_switch)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_sync)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_sync_done)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_syncing)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_wait_on)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_write)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_intent_recovery_failed)(void *, struct xfs_mount *, const struct xfs_defer_op_type *, int);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef int (*copy_fn_t)(void *, const void *, u32, struct task_struct *);\n\ntypedef void (*crw_handler_t)(struct crw *, struct crw *, int);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int devlink_chunk_fill_t(void *, u8 *, u32, u64, struct netlink_ext_ack *);\n\ntypedef int devlink_nl_dump_one_func_t(struct sk_buff *, struct devlink *, struct netlink_callback *, int);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\ntypedef void ext4_update_sb_callback(struct ext4_sb_info *, struct ext4_super_block *, const void *);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, struct mm_struct *);\n\ntypedef void fn_handler_fn___2(struct vc_data *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef void fsm_func_t(struct ccw_device *, enum dev_event);\n\ntypedef int (*ftrace_mapper_func)(void *);\n\ntypedef access_mask_t get_access_mask_t(const struct landlock_ruleset * const, const u16);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef size_t (*huf_compress_f)(void *, size_t, const void *, size_t, unsigned int, unsigned int, void *, size_t, HUF_CElt *, HUF_repeat *, int);\n\ntypedef u32 inet6_ehashfn_t(const struct net *, const struct in6_addr *, const u16, const struct in6_addr *, const __be16);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef initcall_t initcall_entry_t;\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef int (*ioctl_fn)(struct file *, struct dm_ioctl *, size_t);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef int (*iova_bitmap_fn_t)(struct iova_bitmap *, long unsigned int, size_t, void *);\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *, const struct inet6_skb_parm *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef int (*iterate_dir_item_t)(int, struct btrfs_key *, const char *, int, const char *, int, void *);\n\ntypedef int (*iterate_inode_ref_t)(u64, struct fs_path *, void *);\n\ntypedef void iucv_irq_fn(struct iucv_irq_data *);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef void k_handler_fn___2(struct kbd_data *, unsigned char);\n\ntypedef int (*klp_shadow_ctor_t)(void *, void *, void *);\n\ntypedef void (*klp_shadow_dtor_t)(void *, void *);\n\ntypedef bool (*kunit_resource_match_t)(struct kunit *, struct kunit_resource *, void *);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef void (*mapped_f)(struct perf_event *, struct mm_struct *);\n\ntypedef int mh_filter_t(struct sock *, struct sk_buff *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef void (*online_page_callback_t)(struct page *, unsigned int);\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef void pcpu_delegate_fn(void *);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\ntypedef int perf_snapshot_branch_stack_t(struct perf_branch_entry *, unsigned int);\n\ntypedef struct rt6_info * (*pol_lookup_t)(struct net *, struct fib6_table *, struct flowi6 *, const struct sk_buff *, int);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*purgatory_t)(int);\n\ntypedef void (*relocate_kernel_t)(long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*rethook_handler_t)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\ntypedef bool (*ring_buffer_cond_fn)(void *);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef void (*synth_probe_func_t)(void *, u64 *, unsigned int *);\n\ntypedef long int (*sys_call_ptr_t)(struct pt_regs *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef int (*trace_user_buf_copy)(char *, const char *, size_t, void *);\n\ntypedef struct sk_buff * (*udp_gro_receive_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*uprobe_write_verify_t)(struct page *, long unsigned int, uprobe_opcode_t *, int, void *);\n\ntypedef void (*user_event_func_t)(struct user_event *, struct iov_iter *, void *, bool *);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef int (*walk_memory_groups_func_t)(struct memory_group *, void *);\n\ntypedef int (*xfs_agfl_walk_fn)(struct xfs_mount *, xfs_agblock_t, void *);\n\ntypedef int (*xfs_btree_query_range_fn)(struct xfs_btree_cur *, const union xfs_btree_rec *, void *);\n\ntypedef int (*xfs_btree_visit_blocks_fn)(struct xfs_btree_cur *, int, void *);\n\ntypedef int (*xfs_rtalloc_query_range_fn)(struct xfs_rtgroup *, struct xfs_trans *, const struct xfs_rtalloc_rec *, void *);\n\ntypedef ZSTD_sequenceProducer_F zstd_sequence_producer_f;\n\nstruct nf_bridge_frag_data;\n\nstruct encoded_page;\n\ntypedef void *acpi_handle;\n\nstruct acpi_device;\n\nstruct bpf_iter;\n\nstruct nvmem_cell;\n\nstruct x_info_blk_hdr;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern void __attribute__((address_space(1))) *bpf_arena_alloc_pages(void *p__map, void __attribute__((address_space(1))) *addr__ign, u32 page_cnt, int node_id, u64 flags) __weak __ksym;\nextern void bpf_arena_free_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern int bpf_arena_reserve_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern struct cgroup *bpf_cgroup_from_id(u64 cgid) __weak __ksym;\nextern int bpf_cgroup_read_xattr(struct cgroup *cgroup, const char *name__str, struct bpf_dynptr *value_p) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_task_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_dynptr_adjust(const struct bpf_dynptr *p, u64 start, u64 end) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_copy(struct bpf_dynptr *dst_ptr, u64 dst_off, struct bpf_dynptr *src_ptr, u64 src_off, u64 size) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb(struct __sk_buff *s, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb_meta(struct __sk_buff *skb_, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_xdp(struct xdp_md *x, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_dynptr_memset(struct bpf_dynptr *p, u64 offset, u64 size, u8 val) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern void *bpf_dynptr_slice(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern void *bpf_dynptr_slice_rdwr(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern int bpf_get_dentry_xattr(struct dentry *dentry, const char *name__str, struct bpf_dynptr *value_p) __weak __ksym;\nextern int bpf_get_file_xattr(struct file *file, const char *name__str, struct bpf_dynptr *value_p) __weak __ksym;\nextern int bpf_get_fsverity_digest(struct file *file, struct bpf_dynptr *digest_p) __weak __ksym;\nextern struct kmem_cache *bpf_get_kmem_cache(u64 addr) __weak __ksym;\nextern struct mem_cgroup *bpf_get_mem_cgroup(struct cgroup_subsys_state *css) __weak __ksym;\nextern struct mem_cgroup *bpf_get_root_mem_cgroup(void) __weak __ksym;\nextern struct file *bpf_get_task_exe_file(struct task_struct *task) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern int bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it, struct task_struct *task, u64 addr) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern struct bpf_key *bpf_lookup_system_key(u64 id) __weak __ksym;\nextern struct bpf_key *bpf_lookup_user_key(s32 serial, u64 flags) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern void bpf_mem_cgroup_flush_stats(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_memory_events(struct mem_cgroup *memcg, enum memcg_memory_event event) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_page_state(struct mem_cgroup *memcg, int idx) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_usage(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_vm_events(struct mem_cgroup *memcg, enum vm_event_item event) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern int bpf_path_d_path(const struct path *path, char *buf, size_t buf__sz) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_percpu_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern int bpf_probe_read_kernel_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_kernel_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern void bpf_put_file(struct file *file) __weak __ksym;\nextern void bpf_put_mem_cgroup(struct mem_cgroup *memcg) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_remove_dentry_xattr(struct dentry *dentry, const char *name__str) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_send_signal_task(struct task_struct *task, int sig, enum pid_type type, u64 value) __weak __ksym;\nextern __u64 *bpf_session_cookie(void *ctx) __weak __ksym;\nextern bool bpf_session_is_return(void *ctx) __weak __ksym;\nextern int bpf_set_dentry_xattr(struct dentry *dentry, const char *name__str, const struct bpf_dynptr *value_p, int flags) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_sock_ops_enable_tx_tstamp(struct bpf_sock_ops_kern *skops, u64 flags) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern void bpf_throw(u64 cookie) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_verify_pkcs7_signature(struct bpf_dynptr *data_p, struct bpf_dynptr *sig_p, struct bpf_key *trusted_keyring) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern struct xfrm_state *bpf_xdp_get_xfrm_state(struct xdp_md *ctx, struct bpf_xfrm_state_opts *opts, u32 opts__sz) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void bpf_xdp_xfrm_state_release(struct xfrm_state *x) __weak __ksym;\nextern void crash_kexec(struct pt_regs *regs) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __weak __ksym;\nextern void scx_bpf_destroy_dsq(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_insert___v2(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local(u64 dsq_id) __weak __ksym;\nextern bool scx_bpf_dsq_move_vtime(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __weak __ksym;\nextern struct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern void scx_bpf_exit_bstr(s64 exit_code, char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern void scx_bpf_kick_cpu(s32 cpu, u64 flags) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern s32 scx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags, const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __weak __ksym;\nextern bool scx_bpf_sub_dispatch(u64 cgroup_id) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime) __weak __ksym;\nextern bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n#pragma clang diagnostic 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wmissing-declarations\"\n#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tACPI_BATTERY_ALARM_PRESENT = 0,\n\tACPI_BATTERY_XINFO_PRESENT = 1,\n\tACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY = 2,\n\tACPI_BATTERY_QUIRK_THINKPAD_MAH = 3,\n\tACPI_BATTERY_QUIRK_DEGRADED_FULL_CHARGE = 4,\n};\n\nenum {\n\tACPI_BUTTON_LID_INIT_IGNORE = 0,\n\tACPI_BUTTON_LID_INIT_OPEN = 1,\n\tACPI_BUTTON_LID_INIT_METHOD = 2,\n\tACPI_BUTTON_LID_INIT_DISABLED = 3,\n};\n\nenum {\n\tACPI_GENL_ATTR_UNSPEC = 0,\n\tACPI_GENL_ATTR_EVENT = 1,\n\t__ACPI_GENL_ATTR_MAX = 2,\n};\n\nenum {\n\tACPI_GENL_CMD_UNSPEC = 0,\n\tACPI_GENL_CMD_EVENT = 1,\n\t__ACPI_GENL_CMD_MAX = 2,\n};\n\nenum {\n\tACPI_REFCLASS_LOCAL = 0,\n\tACPI_REFCLASS_ARG = 1,\n\tACPI_REFCLASS_REFOF = 2,\n\tACPI_REFCLASS_INDEX = 3,\n\tACPI_REFCLASS_TABLE = 4,\n\tACPI_REFCLASS_NAME = 5,\n\tACPI_REFCLASS_DEBUG = 6,\n\tACPI_REFCLASS_MAX = 6,\n};\n\nenum {\n\tACPI_RSC_INITGET = 0,\n\tACPI_RSC_INITSET = 1,\n\tACPI_RSC_FLAGINIT = 2,\n\tACPI_RSC_1BITFLAG = 3,\n\tACPI_RSC_2BITFLAG = 4,\n\tACPI_RSC_3BITFLAG = 5,\n\tACPI_RSC_6BITFLAG = 6,\n\tACPI_RSC_ADDRESS = 7,\n\tACPI_RSC_BITMASK = 8,\n\tACPI_RSC_BITMASK16 = 9,\n\tACPI_RSC_COUNT = 10,\n\tACPI_RSC_COUNT16 = 11,\n\tACPI_RSC_COUNT_GPIO_PIN = 12,\n\tACPI_RSC_COUNT_GPIO_RES = 13,\n\tACPI_RSC_COUNT_GPIO_VEN = 14,\n\tACPI_RSC_COUNT_SERIAL_RES = 15,\n\tACPI_RSC_COUNT_SERIAL_VEN = 16,\n\tACPI_RSC_DATA8 = 17,\n\tACPI_RSC_EXIT_EQ = 18,\n\tACPI_RSC_EXIT_LE = 19,\n\tACPI_RSC_EXIT_NE = 20,\n\tACPI_RSC_LENGTH = 21,\n\tACPI_RSC_MOVE_GPIO_PIN = 22,\n\tACPI_RSC_MOVE_GPIO_RES = 23,\n\tACPI_RSC_MOVE_SERIAL_RES = 24,\n\tACPI_RSC_MOVE_SERIAL_VEN = 25,\n\tACPI_RSC_MOVE8 = 26,\n\tACPI_RSC_MOVE16 = 27,\n\tACPI_RSC_MOVE32 = 28,\n\tACPI_RSC_MOVE64 = 29,\n\tACPI_RSC_SET8 = 30,\n\tACPI_RSC_SOURCE = 31,\n\tACPI_RSC_SOURCEX = 32,\n};\n\nenum {\n\tACPI_RSD_TITLE = 0,\n\tACPI_RSD_1BITFLAG = 1,\n\tACPI_RSD_2BITFLAG = 2,\n\tACPI_RSD_3BITFLAG = 3,\n\tACPI_RSD_6BITFLAG = 4,\n\tACPI_RSD_ADDRESS = 5,\n\tACPI_RSD_DWORDLIST = 6,\n\tACPI_RSD_LITERAL = 7,\n\tACPI_RSD_LONGLIST = 8,\n\tACPI_RSD_SHORTLIST = 9,\n\tACPI_RSD_SHORTLISTX = 10,\n\tACPI_RSD_SOURCE = 11,\n\tACPI_RSD_STRING = 12,\n\tACPI_RSD_UINT8 = 13,\n\tACPI_RSD_UINT16 = 14,\n\tACPI_RSD_UINT32 = 15,\n\tACPI_RSD_UINT64 = 16,\n\tACPI_RSD_WORDLIST = 17,\n\tACPI_RSD_LABEL = 18,\n\tACPI_RSD_SOURCE_LABEL = 19,\n};\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DMPS = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_CPD = 1048576,\n\tPORT_CMD_MPSP = 524288,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_CMD_CAP = 8126464,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_SUSPEND_PHYS = 33554432,\n\tAHCI_HFLAG_NO_SXS = 67108864,\n\tAHCI_HFLAG_43BIT_ONLY = 134217728,\n\tAHCI_HFLAG_INTEL_PCS_QUIRK = 268435456,\n\tAHCI_HFLAG_ATAPI_DMA_QUIRK = 536870912,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 15,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum {\n\tAML_FIELD_ACCESS_ANY = 0,\n\tAML_FIELD_ACCESS_BYTE = 1,\n\tAML_FIELD_ACCESS_WORD = 2,\n\tAML_FIELD_ACCESS_DWORD = 3,\n\tAML_FIELD_ACCESS_QWORD = 4,\n\tAML_FIELD_ACCESS_BUFFER = 5,\n};\n\nenum {\n\tAML_FIELD_ATTRIB_QUICK = 2,\n\tAML_FIELD_ATTRIB_SEND_RECEIVE = 4,\n\tAML_FIELD_ATTRIB_BYTE = 6,\n\tAML_FIELD_ATTRIB_WORD = 8,\n\tAML_FIELD_ATTRIB_BLOCK = 10,\n\tAML_FIELD_ATTRIB_BYTES = 11,\n\tAML_FIELD_ATTRIB_PROCESS_CALL = 12,\n\tAML_FIELD_ATTRIB_BLOCK_PROCESS_CALL = 13,\n\tAML_FIELD_ATTRIB_RAW_BYTES = 14,\n\tAML_FIELD_ATTRIB_RAW_PROCESS_BYTES = 15,\n};\n\nenum {\n\tAML_FIELD_UPDATE_PRESERVE = 0,\n\tAML_FIELD_UPDATE_WRITE_AS_ONES = 32,\n\tAML_FIELD_UPDATE_WRITE_AS_ZEROS = 64,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tASSUME_PERFECT = 255,\n\tASSUME_VALID_DTB = 1,\n\tASSUME_VALID_INPUT = 2,\n\tASSUME_LATEST = 4,\n\tASSUME_NO_ROLLBACK = 8,\n\tASSUME_LIBFDT_ORDER = 16,\n\tASSUME_LIBFDT_FLAWLESS = 32,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = -2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = -2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_CDL = 24,\n\tATA_LOG_CDL_SIZE = 512,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SENSE_NCQ = 15,\n\tATA_LOG_SENSE_NCQ_SIZE = 1024,\n\tATA_LOG_CONCURRENT_POSITIONING_RANGES = 71,\n\tATA_LOG_SUPPORTED_CAPABILITIES = 3,\n\tATA_LOG_CURRENT_SETTINGS = 4,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSETFEATURES_CDL = 13,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tSETFEATURE_SENSE_DATA_SUCC_NCQ = 196,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum {\n\tATA_QUIRK_DIAGNOSTIC = 1,\n\tATA_QUIRK_NODMA = 2,\n\tATA_QUIRK_NONCQ = 4,\n\tATA_QUIRK_BROKEN_HPA = 8,\n\tATA_QUIRK_DISABLE = 16,\n\tATA_QUIRK_HPA_SIZE = 32,\n\tATA_QUIRK_IVB = 64,\n\tATA_QUIRK_STUCK_ERR = 128,\n\tATA_QUIRK_BRIDGE_OK = 256,\n\tATA_QUIRK_ATAPI_MOD16_DMA = 512,\n\tATA_QUIRK_FIRMWARE_WARN = 1024,\n\tATA_QUIRK_1_5_GBPS = 2048,\n\tATA_QUIRK_NOSETXFER = 4096,\n\tATA_QUIRK_BROKEN_FPDMA_AA = 8192,\n\tATA_QUIRK_DUMP_ID = 16384,\n\tATA_QUIRK_MAX_SEC_LBA48 = 32768,\n\tATA_QUIRK_ATAPI_DMADIR = 65536,\n\tATA_QUIRK_NO_NCQ_TRIM = 131072,\n\tATA_QUIRK_NOLPM = 262144,\n\tATA_QUIRK_WD_BROKEN_LPM = 524288,\n\tATA_QUIRK_ZERO_AFTER_TRIM = 1048576,\n\tATA_QUIRK_NO_DMA_LOG = 2097152,\n\tATA_QUIRK_NOTRIM = 4194304,\n\tATA_QUIRK_MAX_SEC = 8388608,\n\tATA_QUIRK_MAX_TRIM_128M = 16777216,\n\tATA_QUIRK_NO_NCQ_ON_ATI = 33554432,\n\tATA_QUIRK_NO_LPM_ON_ATI = 67108864,\n\tATA_QUIRK_NO_ID_DEV_LOG = 134217728,\n\tATA_QUIRK_NO_LOG_DIR = 268435456,\n\tATA_QUIRK_NO_FUA = 536870912,\n};\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = -2147483648,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAUTOFS_DEV_IOCTL_VERSION_CMD = 113,\n\tAUTOFS_DEV_IOCTL_PROTOVER_CMD = 114,\n\tAUTOFS_DEV_IOCTL_PROTOSUBVER_CMD = 115,\n\tAUTOFS_DEV_IOCTL_OPENMOUNT_CMD = 116,\n\tAUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD = 117,\n\tAUTOFS_DEV_IOCTL_READY_CMD = 118,\n\tAUTOFS_DEV_IOCTL_FAIL_CMD = 119,\n\tAUTOFS_DEV_IOCTL_SETPIPEFD_CMD = 120,\n\tAUTOFS_DEV_IOCTL_CATATONIC_CMD = 121,\n\tAUTOFS_DEV_IOCTL_TIMEOUT_CMD = 122,\n\tAUTOFS_DEV_IOCTL_REQUESTER_CMD = 123,\n\tAUTOFS_DEV_IOCTL_EXPIRE_CMD = 124,\n\tAUTOFS_DEV_IOCTL_ASKUMOUNT_CMD = 125,\n\tAUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD = 126,\n};\n\nenum {\n\tAUTOFS_IOC_EXPIRE_MULTI_CMD = 102,\n\tAUTOFS_IOC_PROTOSUBVER_CMD = 103,\n\tAUTOFS_IOC_ASKUMOUNT_CMD = 112,\n};\n\nenum {\n\tAUTOFS_IOC_READY_CMD = 96,\n\tAUTOFS_IOC_FAIL_CMD = 97,\n\tAUTOFS_IOC_CATATONIC_CMD = 98,\n\tAUTOFS_IOC_PROTOVER_CMD = 99,\n\tAUTOFS_IOC_SETTIMEOUT_CMD = 100,\n\tAUTOFS_IOC_EXPIRE_CMD = 101,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tAXP15060_DCDC1 = 0,\n\tAXP15060_DCDC2 = 1,\n\tAXP15060_DCDC3 = 2,\n\tAXP15060_DCDC4 = 3,\n\tAXP15060_DCDC5 = 4,\n\tAXP15060_DCDC6 = 5,\n\tAXP15060_ALDO1 = 6,\n\tAXP15060_ALDO2 = 7,\n\tAXP15060_ALDO3 = 8,\n\tAXP15060_ALDO4 = 9,\n\tAXP15060_ALDO5 = 10,\n\tAXP15060_BLDO1 = 11,\n\tAXP15060_BLDO2 = 12,\n\tAXP15060_BLDO3 = 13,\n\tAXP15060_BLDO4 = 14,\n\tAXP15060_BLDO5 = 15,\n\tAXP15060_CLDO1 = 16,\n\tAXP15060_CLDO2 = 17,\n\tAXP15060_CLDO3 = 18,\n\tAXP15060_CLDO4 = 19,\n\tAXP15060_CPUSLDO = 20,\n\tAXP15060_SW = 21,\n\tAXP15060_RTC_LDO = 22,\n\tAXP15060_REG_ID_MAX = 23,\n};\n\nenum {\n\tAXP152_IRQ_LDO0IN_CONNECT = 1,\n\tAXP152_IRQ_LDO0IN_REMOVAL = 2,\n\tAXP152_IRQ_ALDO0IN_CONNECT = 3,\n\tAXP152_IRQ_ALDO0IN_REMOVAL = 4,\n\tAXP152_IRQ_DCDC1_V_LOW = 5,\n\tAXP152_IRQ_DCDC2_V_LOW = 6,\n\tAXP152_IRQ_DCDC3_V_LOW = 7,\n\tAXP152_IRQ_DCDC4_V_LOW = 8,\n\tAXP152_IRQ_PEK_SHORT = 9,\n\tAXP152_IRQ_PEK_LONG = 10,\n\tAXP152_IRQ_TIMER = 11,\n\tAXP152_IRQ_PEK_FAL_EDGE = 12,\n\tAXP152_IRQ_PEK_RIS_EDGE = 13,\n\tAXP152_IRQ_GPIO3_INPUT = 14,\n\tAXP152_IRQ_GPIO2_INPUT = 15,\n\tAXP152_IRQ_GPIO1_INPUT = 16,\n\tAXP152_IRQ_GPIO0_INPUT = 17,\n};\n\nenum {\n\tAXP20X_IRQ_ACIN_OVER_V = 1,\n\tAXP20X_IRQ_ACIN_PLUGIN = 2,\n\tAXP20X_IRQ_ACIN_REMOVAL = 3,\n\tAXP20X_IRQ_VBUS_OVER_V = 4,\n\tAXP20X_IRQ_VBUS_PLUGIN = 5,\n\tAXP20X_IRQ_VBUS_REMOVAL = 6,\n\tAXP20X_IRQ_VBUS_V_LOW = 7,\n\tAXP20X_IRQ_BATT_PLUGIN = 8,\n\tAXP20X_IRQ_BATT_REMOVAL = 9,\n\tAXP20X_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP20X_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP20X_IRQ_CHARG = 12,\n\tAXP20X_IRQ_CHARG_DONE = 13,\n\tAXP20X_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP20X_IRQ_BATT_TEMP_LOW = 15,\n\tAXP20X_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP20X_IRQ_CHARG_I_LOW = 17,\n\tAXP20X_IRQ_DCDC1_V_LONG = 18,\n\tAXP20X_IRQ_DCDC2_V_LONG = 19,\n\tAXP20X_IRQ_DCDC3_V_LONG = 20,\n\tAXP20X_IRQ_PEK_SHORT = 22,\n\tAXP20X_IRQ_PEK_LONG = 23,\n\tAXP20X_IRQ_N_OE_PWR_ON = 24,\n\tAXP20X_IRQ_N_OE_PWR_OFF = 25,\n\tAXP20X_IRQ_VBUS_VALID = 26,\n\tAXP20X_IRQ_VBUS_NOT_VALID = 27,\n\tAXP20X_IRQ_VBUS_SESS_VALID = 28,\n\tAXP20X_IRQ_VBUS_SESS_END = 29,\n\tAXP20X_IRQ_LOW_PWR_LVL1 = 30,\n\tAXP20X_IRQ_LOW_PWR_LVL2 = 31,\n\tAXP20X_IRQ_TIMER = 32,\n\tAXP20X_IRQ_PEK_FAL_EDGE = 33,\n\tAXP20X_IRQ_PEK_RIS_EDGE = 34,\n\tAXP20X_IRQ_GPIO3_INPUT = 35,\n\tAXP20X_IRQ_GPIO2_INPUT = 36,\n\tAXP20X_IRQ_GPIO1_INPUT = 37,\n\tAXP20X_IRQ_GPIO0_INPUT = 38,\n};\n\nenum {\n\tAXP20X_LDO1 = 0,\n\tAXP20X_LDO2 = 1,\n\tAXP20X_LDO3 = 2,\n\tAXP20X_LDO4 = 3,\n\tAXP20X_LDO5 = 4,\n\tAXP20X_DCDC2 = 5,\n\tAXP20X_DCDC3 = 6,\n\tAXP20X_REG_ID_MAX = 7,\n};\n\nenum {\n\tAXP22X_DCDC1 = 0,\n\tAXP22X_DCDC2 = 1,\n\tAXP22X_DCDC3 = 2,\n\tAXP22X_DCDC4 = 3,\n\tAXP22X_DCDC5 = 4,\n\tAXP22X_DC1SW = 5,\n\tAXP22X_DC5LDO = 6,\n\tAXP22X_ALDO1 = 7,\n\tAXP22X_ALDO2 = 8,\n\tAXP22X_ALDO3 = 9,\n\tAXP22X_ELDO1 = 10,\n\tAXP22X_ELDO2 = 11,\n\tAXP22X_ELDO3 = 12,\n\tAXP22X_DLDO1 = 13,\n\tAXP22X_DLDO2 = 14,\n\tAXP22X_DLDO3 = 15,\n\tAXP22X_DLDO4 = 16,\n\tAXP22X_RTC_LDO = 17,\n\tAXP22X_LDO_IO0 = 18,\n\tAXP22X_LDO_IO1 = 19,\n\tAXP22X_REG_ID_MAX = 20,\n};\n\nenum {\n\tAXP313A_DCDC1 = 0,\n\tAXP313A_DCDC2 = 1,\n\tAXP313A_DCDC3 = 2,\n\tAXP313A_ALDO1 = 3,\n\tAXP313A_DLDO1 = 4,\n\tAXP313A_RTC_LDO = 5,\n\tAXP313A_REG_ID_MAX = 6,\n};\n\nenum {\n\tAXP717_DCDC1 = 0,\n\tAXP717_DCDC2 = 1,\n\tAXP717_DCDC3 = 2,\n\tAXP717_DCDC4 = 3,\n\tAXP717_ALDO1 = 4,\n\tAXP717_ALDO2 = 5,\n\tAXP717_ALDO3 = 6,\n\tAXP717_ALDO4 = 7,\n\tAXP717_BLDO1 = 8,\n\tAXP717_BLDO2 = 9,\n\tAXP717_BLDO3 = 10,\n\tAXP717_BLDO4 = 11,\n\tAXP717_CLDO1 = 12,\n\tAXP717_CLDO2 = 13,\n\tAXP717_CLDO3 = 14,\n\tAXP717_CLDO4 = 15,\n\tAXP717_CPUSLDO = 16,\n\tAXP717_BOOST = 17,\n\tAXP717_REG_ID_MAX = 18,\n};\n\nenum {\n\tAXP803_DCDC1 = 0,\n\tAXP803_DCDC2 = 1,\n\tAXP803_DCDC3 = 2,\n\tAXP803_DCDC4 = 3,\n\tAXP803_DCDC5 = 4,\n\tAXP803_DCDC6 = 5,\n\tAXP803_DC1SW = 6,\n\tAXP803_ALDO1 = 7,\n\tAXP803_ALDO2 = 8,\n\tAXP803_ALDO3 = 9,\n\tAXP803_DLDO1 = 10,\n\tAXP803_DLDO2 = 11,\n\tAXP803_DLDO3 = 12,\n\tAXP803_DLDO4 = 13,\n\tAXP803_ELDO1 = 14,\n\tAXP803_ELDO2 = 15,\n\tAXP803_ELDO3 = 16,\n\tAXP803_FLDO1 = 17,\n\tAXP803_FLDO2 = 18,\n\tAXP803_RTC_LDO = 19,\n\tAXP803_LDO_IO0 = 20,\n\tAXP803_LDO_IO1 = 21,\n\tAXP803_REG_ID_MAX = 22,\n};\n\nenum {\n\tAXP806_DCDCA = 0,\n\tAXP806_DCDCB = 1,\n\tAXP806_DCDCC = 2,\n\tAXP806_DCDCD = 3,\n\tAXP806_DCDCE = 4,\n\tAXP806_ALDO1 = 5,\n\tAXP806_ALDO2 = 6,\n\tAXP806_ALDO3 = 7,\n\tAXP806_BLDO1 = 8,\n\tAXP806_BLDO2 = 9,\n\tAXP806_BLDO3 = 10,\n\tAXP806_BLDO4 = 11,\n\tAXP806_CLDO1 = 12,\n\tAXP806_CLDO2 = 13,\n\tAXP806_CLDO3 = 14,\n\tAXP806_SW = 15,\n\tAXP806_REG_ID_MAX = 16,\n};\n\nenum {\n\tAXP809_DCDC1 = 0,\n\tAXP809_DCDC2 = 1,\n\tAXP809_DCDC3 = 2,\n\tAXP809_DCDC4 = 3,\n\tAXP809_DCDC5 = 4,\n\tAXP809_DC1SW = 5,\n\tAXP809_DC5LDO = 6,\n\tAXP809_ALDO1 = 7,\n\tAXP809_ALDO2 = 8,\n\tAXP809_ALDO3 = 9,\n\tAXP809_ELDO1 = 10,\n\tAXP809_ELDO2 = 11,\n\tAXP809_ELDO3 = 12,\n\tAXP809_DLDO1 = 13,\n\tAXP809_DLDO2 = 14,\n\tAXP809_RTC_LDO = 15,\n\tAXP809_LDO_IO0 = 16,\n\tAXP809_LDO_IO1 = 17,\n\tAXP809_SW = 18,\n\tAXP809_REG_ID_MAX = 19,\n};\n\nenum {\n\tAXP813_DCDC1 = 0,\n\tAXP813_DCDC2 = 1,\n\tAXP813_DCDC3 = 2,\n\tAXP813_DCDC4 = 3,\n\tAXP813_DCDC5 = 4,\n\tAXP813_DCDC6 = 5,\n\tAXP813_DCDC7 = 6,\n\tAXP813_ALDO1 = 7,\n\tAXP813_ALDO2 = 8,\n\tAXP813_ALDO3 = 9,\n\tAXP813_DLDO1 = 10,\n\tAXP813_DLDO2 = 11,\n\tAXP813_DLDO3 = 12,\n\tAXP813_DLDO4 = 13,\n\tAXP813_ELDO1 = 14,\n\tAXP813_ELDO2 = 15,\n\tAXP813_ELDO3 = 16,\n\tAXP813_FLDO1 = 17,\n\tAXP813_FLDO2 = 18,\n\tAXP813_FLDO3 = 19,\n\tAXP813_RTC_LDO = 20,\n\tAXP813_LDO_IO0 = 21,\n\tAXP813_LDO_IO1 = 22,\n\tAXP813_SW = 23,\n\tAXP813_REG_ID_MAX = 24,\n};\n\nenum {\n\tAudit_equal = 0,\n\tAudit_not_equal = 1,\n\tAudit_bitmask = 2,\n\tAudit_bittest = 3,\n\tAudit_lt = 4,\n\tAudit_gt = 5,\n\tAudit_le = 6,\n\tAudit_ge = 7,\n\tAudit_bad = 8,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_CURRENT_NETNS = -1,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\nenum {\n\tBPF_F_SYSCTL_BASE_NAME = 1,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 38,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBPF_WRITE_HDR_TCP_CURRENT_MSS = 1,\n\tBPF_WRITE_HDR_TCP_SYNACK_COOKIE = 2,\n};\n\nenum {\n\tBPF_XFRM_STATE_OPTS_SZ = 36,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tCACHE_RH_CNT = 14,\n};\n\nenum {\n\tCACHE_VALID = 0,\n\tCACHE_NEGATIVE = 1,\n\tCACHE_PENDING = 2,\n\tCACHE_CLEANED = 3,\n};\n\nenum {\n\tCACHE_WH_CNT = 15,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCMD_PIPE_ID = 1,\n\tSTATUS_PIPE_ID = 2,\n\tDATA_IN_PIPE_ID = 3,\n\tDATA_OUT_PIPE_ID = 4,\n\tUAS_SIMPLE_TAG = 0,\n\tUAS_HEAD_TAG = 1,\n\tUAS_ORDERED_TAG = 2,\n\tUAS_ACA = 4,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCRI_RES_UTIL = 5,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 250,\n\tCRNG_RESEED_INTERVAL = 15000,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCTL_RES_CNT = 1,\n};\n\nenum {\n\tCTL_RES_TM = 2,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tDAD_PROCESS = 0,\n\tDAD_BEGIN = 1,\n\tDAD_ABORT = 2,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEVCONF_FORWARDING = 0,\n\tDEVCONF_HOPLIMIT = 1,\n\tDEVCONF_MTU6 = 2,\n\tDEVCONF_ACCEPT_RA = 3,\n\tDEVCONF_ACCEPT_REDIRECTS = 4,\n\tDEVCONF_AUTOCONF = 5,\n\tDEVCONF_DAD_TRANSMITS = 6,\n\tDEVCONF_RTR_SOLICITS = 7,\n\tDEVCONF_RTR_SOLICIT_INTERVAL = 8,\n\tDEVCONF_RTR_SOLICIT_DELAY = 9,\n\tDEVCONF_USE_TEMPADDR = 10,\n\tDEVCONF_TEMP_VALID_LFT = 11,\n\tDEVCONF_TEMP_PREFERED_LFT = 12,\n\tDEVCONF_REGEN_MAX_RETRY = 13,\n\tDEVCONF_MAX_DESYNC_FACTOR = 14,\n\tDEVCONF_MAX_ADDRESSES = 15,\n\tDEVCONF_FORCE_MLD_VERSION = 16,\n\tDEVCONF_ACCEPT_RA_DEFRTR = 17,\n\tDEVCONF_ACCEPT_RA_PINFO = 18,\n\tDEVCONF_ACCEPT_RA_RTR_PREF = 19,\n\tDEVCONF_RTR_PROBE_INTERVAL = 20,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN = 21,\n\tDEVCONF_PROXY_NDP = 22,\n\tDEVCONF_OPTIMISTIC_DAD = 23,\n\tDEVCONF_ACCEPT_SOURCE_ROUTE = 24,\n\tDEVCONF_MC_FORWARDING = 25,\n\tDEVCONF_DISABLE_IPV6 = 26,\n\tDEVCONF_ACCEPT_DAD = 27,\n\tDEVCONF_FORCE_TLLAO = 28,\n\tDEVCONF_NDISC_NOTIFY = 29,\n\tDEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL = 30,\n\tDEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL = 31,\n\tDEVCONF_SUPPRESS_FRAG_NDISC = 32,\n\tDEVCONF_ACCEPT_RA_FROM_LOCAL = 33,\n\tDEVCONF_USE_OPTIMISTIC = 34,\n\tDEVCONF_ACCEPT_RA_MTU = 35,\n\tDEVCONF_STABLE_SECRET = 36,\n\tDEVCONF_USE_OIF_ADDRS_ONLY = 37,\n\tDEVCONF_ACCEPT_RA_MIN_HOP_LIMIT = 38,\n\tDEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 39,\n\tDEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 40,\n\tDEVCONF_DROP_UNSOLICITED_NA = 41,\n\tDEVCONF_KEEP_ADDR_ON_DOWN = 42,\n\tDEVCONF_RTR_SOLICIT_MAX_INTERVAL = 43,\n\tDEVCONF_SEG6_ENABLED = 44,\n\tDEVCONF_SEG6_REQUIRE_HMAC = 45,\n\tDEVCONF_ENHANCED_DAD = 46,\n\tDEVCONF_ADDR_GEN_MODE = 47,\n\tDEVCONF_DISABLE_POLICY = 48,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN = 49,\n\tDEVCONF_NDISC_TCLASS = 50,\n\tDEVCONF_RPL_SEG_ENABLED = 51,\n\tDEVCONF_RA_DEFRTR_METRIC = 52,\n\tDEVCONF_IOAM6_ENABLED = 53,\n\tDEVCONF_IOAM6_ID = 54,\n\tDEVCONF_IOAM6_ID_WIDE = 55,\n\tDEVCONF_NDISC_EVICT_NOCARRIER = 56,\n\tDEVCONF_ACCEPT_UNTRACKED_NA = 57,\n\tDEVCONF_ACCEPT_RA_MIN_LFT = 58,\n\tDEVCONF_FORCE_FORWARDING = 59,\n\tDEVCONF_MAX = 60,\n};\n\nenum {\n\tDEVLINK_ATTR_STATS_RX_PACKETS = 0,\n\tDEVLINK_ATTR_STATS_RX_BYTES = 1,\n\tDEVLINK_ATTR_STATS_RX_DROPPED = 2,\n\t__DEVLINK_ATTR_STATS_MAX = 3,\n\tDEVLINK_ATTR_STATS_MAX = 2,\n};\n\nenum {\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_IN_PORT = 0,\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_FA_COOKIE = 1,\n};\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIR_CORR = 0,\n\tDATA_CORR = 1,\n\tDATA_UNCORR = 2,\n\tDIR_UNCORR = 3,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tDWAXIDMAC_ARWLEN_1 = 0,\n\tDWAXIDMAC_ARWLEN_2 = 1,\n\tDWAXIDMAC_ARWLEN_4 = 3,\n\tDWAXIDMAC_ARWLEN_8 = 7,\n\tDWAXIDMAC_ARWLEN_16 = 15,\n\tDWAXIDMAC_ARWLEN_32 = 31,\n\tDWAXIDMAC_ARWLEN_64 = 63,\n\tDWAXIDMAC_ARWLEN_128 = 127,\n\tDWAXIDMAC_ARWLEN_256 = 255,\n\tDWAXIDMAC_ARWLEN_MIN = 0,\n\tDWAXIDMAC_ARWLEN_MAX = 255,\n};\n\nenum {\n\tDWAXIDMAC_BURST_TRANS_LEN_1 = 0,\n\tDWAXIDMAC_BURST_TRANS_LEN_4 = 1,\n\tDWAXIDMAC_BURST_TRANS_LEN_8 = 2,\n\tDWAXIDMAC_BURST_TRANS_LEN_16 = 3,\n\tDWAXIDMAC_BURST_TRANS_LEN_32 = 4,\n\tDWAXIDMAC_BURST_TRANS_LEN_64 = 5,\n\tDWAXIDMAC_BURST_TRANS_LEN_128 = 6,\n\tDWAXIDMAC_BURST_TRANS_LEN_256 = 7,\n\tDWAXIDMAC_BURST_TRANS_LEN_512 = 8,\n\tDWAXIDMAC_BURST_TRANS_LEN_1024 = 9,\n};\n\nenum {\n\tDWAXIDMAC_CH_CTL_L_INC = 0,\n\tDWAXIDMAC_CH_CTL_L_NOINC = 1,\n};\n\nenum {\n\tDWAXIDMAC_HS_SEL_HW = 0,\n\tDWAXIDMAC_HS_SEL_SW = 1,\n};\n\nenum {\n\tDWAXIDMAC_IRQ_NONE = 0,\n\tDWAXIDMAC_IRQ_BLOCK_TRF = 1,\n\tDWAXIDMAC_IRQ_DMA_TRF = 2,\n\tDWAXIDMAC_IRQ_SRC_TRAN = 8,\n\tDWAXIDMAC_IRQ_DST_TRAN = 16,\n\tDWAXIDMAC_IRQ_SRC_DEC_ERR = 32,\n\tDWAXIDMAC_IRQ_DST_DEC_ERR = 64,\n\tDWAXIDMAC_IRQ_SRC_SLV_ERR = 128,\n\tDWAXIDMAC_IRQ_DST_SLV_ERR = 256,\n\tDWAXIDMAC_IRQ_LLI_RD_DEC_ERR = 512,\n\tDWAXIDMAC_IRQ_LLI_WR_DEC_ERR = 1024,\n\tDWAXIDMAC_IRQ_LLI_RD_SLV_ERR = 2048,\n\tDWAXIDMAC_IRQ_LLI_WR_SLV_ERR = 4096,\n\tDWAXIDMAC_IRQ_INVALID_ERR = 8192,\n\tDWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = 16384,\n\tDWAXIDMAC_IRQ_DEC_ERR = 65536,\n\tDWAXIDMAC_IRQ_WR2RO_ERR = 131072,\n\tDWAXIDMAC_IRQ_RD2RWO_ERR = 262144,\n\tDWAXIDMAC_IRQ_WRONCHEN_ERR = 524288,\n\tDWAXIDMAC_IRQ_SHADOWREG_ERR = 1048576,\n\tDWAXIDMAC_IRQ_WRONHOLD_ERR = 2097152,\n\tDWAXIDMAC_IRQ_LOCK_CLEARED = 134217728,\n\tDWAXIDMAC_IRQ_SRC_SUSPENDED = 268435456,\n\tDWAXIDMAC_IRQ_SUSPENDED = 536870912,\n\tDWAXIDMAC_IRQ_DISABLED = 1073741824,\n\tDWAXIDMAC_IRQ_ABORTED = 2147483648,\n\tDWAXIDMAC_IRQ_ALL_ERR = 4161504,\n\tDWAXIDMAC_IRQ_ALL = 4294967295,\n};\n\nenum {\n\tDWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0,\n\tDWAXIDMAC_MBLK_TYPE_RELOAD = 1,\n\tDWAXIDMAC_MBLK_TYPE_SHADOW_REG = 2,\n\tDWAXIDMAC_MBLK_TYPE_LL = 3,\n};\n\nenum {\n\tDWAXIDMAC_TRANS_WIDTH_8 = 0,\n\tDWAXIDMAC_TRANS_WIDTH_16 = 1,\n\tDWAXIDMAC_TRANS_WIDTH_32 = 2,\n\tDWAXIDMAC_TRANS_WIDTH_64 = 3,\n\tDWAXIDMAC_TRANS_WIDTH_128 = 4,\n\tDWAXIDMAC_TRANS_WIDTH_256 = 5,\n\tDWAXIDMAC_TRANS_WIDTH_512 = 6,\n\tDWAXIDMAC_TRANS_WIDTH_MAX = 6,\n};\n\nenum {\n\tDWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0,\n\tDWAXIDMAC_TT_FC_MEM_TO_PER_DMAC = 1,\n\tDWAXIDMAC_TT_FC_PER_TO_MEM_DMAC = 2,\n\tDWAXIDMAC_TT_FC_PER_TO_PER_DMAC = 3,\n\tDWAXIDMAC_TT_FC_PER_TO_MEM_SRC = 4,\n\tDWAXIDMAC_TT_FC_PER_TO_PER_SRC = 5,\n\tDWAXIDMAC_TT_FC_MEM_TO_PER_DST = 6,\n\tDWAXIDMAC_TT_FC_PER_TO_PER_DST = 7,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_CODE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_CODE_OK = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE_OPEN = 2,\n\tETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT = 3,\n\tETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT = 4,\n\tETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH = 5,\n\tETHTOOL_A_CABLE_RESULT_CODE_NOISE = 6,\n\tETHTOOL_A_CABLE_RESULT_CODE_RESOLUTION_NOT_POSSIBLE = 7,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENTFS_SAVE_MODE = 65536,\n\tEVENTFS_SAVE_UID = 131072,\n\tEVENTFS_SAVE_GID = 262144,\n};\n\nenum {\n\tEVENT_CMD_COMPLETE = 0,\n\tEVENT_XFER_COMPLETE = 1,\n\tEVENT_DATA_COMPLETE = 2,\n\tEVENT_DATA_ERROR = 3,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_DISABLED = 32,\n\tEVENT_FILE_FL_TRIGGER_MODE = 64,\n\tEVENT_FILE_FL_TRIGGER_COND = 128,\n\tEVENT_FILE_FL_PID_FILTER = 256,\n\tEVENT_FILE_FL_WAS_ENABLED = 512,\n\tEVENT_FILE_FL_FREED = 1024,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEVENT_TRIGGER_FL_PROBE = 1,\n\tEVENT_TRIGGER_FL_COUNT = 2,\n};\n\nenum {\n\tEXT4_FC_REASON_XATTR = 0,\n\tEXT4_FC_REASON_CROSS_RENAME = 1,\n\tEXT4_FC_REASON_JOURNAL_FLAG_CHANGE = 2,\n\tEXT4_FC_REASON_NOMEM = 3,\n\tEXT4_FC_REASON_SWAP_BOOT = 4,\n\tEXT4_FC_REASON_RESIZE = 5,\n\tEXT4_FC_REASON_RENAME_DIR = 6,\n\tEXT4_FC_REASON_FALLOC_RANGE = 7,\n\tEXT4_FC_REASON_INODE_JOURNAL_DATA = 8,\n\tEXT4_FC_REASON_ENCRYPTED_FILENAME = 9,\n\tEXT4_FC_REASON_MIGRATE = 10,\n\tEXT4_FC_REASON_VERITY = 11,\n\tEXT4_FC_REASON_MOVE_EXT = 12,\n\tEXT4_FC_REASON_MAX = 13,\n};\n\nenum {\n\tEXT4_FC_STATUS_OK = 0,\n\tEXT4_FC_STATUS_INELIGIBLE = 1,\n\tEXT4_FC_STATUS_SKIPPED = 2,\n\tEXT4_FC_STATUS_FAILED = 3,\n};\n\nenum {\n\tEXT4_FLAGS_RESIZING = 0,\n\tEXT4_FLAGS_SHUTDOWN = 1,\n\tEXT4_FLAGS_BDEV_IS_DAX = 2,\n\tEXT4_FLAGS_EMERGENCY_RO = 3,\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nenum {\n\tEXT4_MF_MNTDIR_SAMPLED = 0,\n\tEXT4_MF_FC_INELIGIBLE = 1,\n\tEXT4_MF_JOURNAL_DESTROY = 2,\n};\n\nenum {\n\tEXT4_STATE_NEW = 0,\n\tEXT4_STATE_XATTR = 1,\n\tEXT4_STATE_NO_EXPAND = 2,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 3,\n\tEXT4_STATE_EXT_MIGRATE = 4,\n\tEXT4_STATE_NEWENTRY = 5,\n\tEXT4_STATE_MAY_INLINE_DATA = 6,\n\tEXT4_STATE_EXT_PRECACHED = 7,\n\tEXT4_STATE_LUSTRE_EA_INODE = 8,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 9,\n\tEXT4_STATE_FC_COMMITTING = 10,\n\tEXT4_STATE_FC_FLUSHING_DATA = 11,\n\tEXT4_STATE_ORPHAN_FILE = 12,\n};\n\nenum {\n\tFAST_W_CNT = 16,\n};\n\nenum {\n\tFATTR4_CLONE_BLKSIZE = 77,\n\tFATTR4_SPACE_FREED = 78,\n\tFATTR4_CHANGE_ATTR_TYPE = 79,\n\tFATTR4_SEC_LABEL = 80,\n};\n\nenum {\n\tFATTR4_DIR_NOTIF_DELAY = 56,\n\tFATTR4_DIRENT_NOTIF_DELAY = 57,\n\tFATTR4_DACL = 58,\n\tFATTR4_SACL = 59,\n\tFATTR4_CHANGE_POLICY = 60,\n\tFATTR4_FS_STATUS = 61,\n\tFATTR4_FS_LAYOUT_TYPES = 62,\n\tFATTR4_LAYOUT_HINT = 63,\n\tFATTR4_LAYOUT_TYPES = 64,\n\tFATTR4_LAYOUT_BLKSIZE = 65,\n\tFATTR4_LAYOUT_ALIGNMENT = 66,\n\tFATTR4_FS_LOCATIONS_INFO = 67,\n\tFATTR4_MDSTHRESHOLD = 68,\n\tFATTR4_RETENTION_GET = 69,\n\tFATTR4_RETENTION_SET = 70,\n\tFATTR4_RETENTEVT_GET = 71,\n\tFATTR4_RETENTEVT_SET = 72,\n\tFATTR4_RETENTION_HOLD = 73,\n\tFATTR4_MODE_SET_MASKED = 74,\n\tFATTR4_SUPPATTR_EXCLCREAT = 75,\n\tFATTR4_FS_CHARSET_CAP = 76,\n};\n\nenum {\n\tFATTR4_MODE_UMASK = 81,\n};\n\nenum {\n\tFATTR4_OPEN_ARGUMENTS = 86,\n};\n\nenum {\n\tFATTR4_SUPPORTED_ATTRS = 0,\n\tFATTR4_TYPE = 1,\n\tFATTR4_FH_EXPIRE_TYPE = 2,\n\tFATTR4_CHANGE = 3,\n\tFATTR4_SIZE = 4,\n\tFATTR4_LINK_SUPPORT = 5,\n\tFATTR4_SYMLINK_SUPPORT = 6,\n\tFATTR4_NAMED_ATTR = 7,\n\tFATTR4_FSID = 8,\n\tFATTR4_UNIQUE_HANDLES = 9,\n\tFATTR4_LEASE_TIME = 10,\n\tFATTR4_RDATTR_ERROR = 11,\n\tFATTR4_ACL = 12,\n\tFATTR4_ACLSUPPORT = 13,\n\tFATTR4_ARCHIVE = 14,\n\tFATTR4_CANSETTIME = 15,\n\tFATTR4_CASE_INSENSITIVE = 16,\n\tFATTR4_CASE_PRESERVING = 17,\n\tFATTR4_CHOWN_RESTRICTED = 18,\n\tFATTR4_FILEHANDLE = 19,\n\tFATTR4_FILEID = 20,\n\tFATTR4_FILES_AVAIL = 21,\n\tFATTR4_FILES_FREE = 22,\n\tFATTR4_FILES_TOTAL = 23,\n\tFATTR4_FS_LOCATIONS = 24,\n\tFATTR4_HIDDEN = 25,\n\tFATTR4_HOMOGENEOUS = 26,\n\tFATTR4_MAXFILESIZE = 27,\n\tFATTR4_MAXLINK = 28,\n\tFATTR4_MAXNAME = 29,\n\tFATTR4_MAXREAD = 30,\n\tFATTR4_MAXWRITE = 31,\n\tFATTR4_MIMETYPE = 32,\n\tFATTR4_MODE = 33,\n\tFATTR4_NO_TRUNC = 34,\n\tFATTR4_NUMLINKS = 35,\n\tFATTR4_OWNER = 36,\n\tFATTR4_OWNER_GROUP = 37,\n\tFATTR4_QUOTA_AVAIL_HARD = 38,\n\tFATTR4_QUOTA_AVAIL_SOFT = 39,\n\tFATTR4_QUOTA_USED = 40,\n\tFATTR4_RAWDEV = 41,\n\tFATTR4_SPACE_AVAIL = 42,\n\tFATTR4_SPACE_FREE = 43,\n\tFATTR4_SPACE_TOTAL = 44,\n\tFATTR4_SPACE_USED = 45,\n\tFATTR4_SYSTEM = 46,\n\tFATTR4_TIME_ACCESS = 47,\n\tFATTR4_TIME_ACCESS_SET = 48,\n\tFATTR4_TIME_BACKUP = 49,\n\tFATTR4_TIME_CREATE = 50,\n\tFATTR4_TIME_DELTA = 51,\n\tFATTR4_TIME_METADATA = 52,\n\tFATTR4_TIME_MODIFY = 53,\n\tFATTR4_TIME_MODIFY_SET = 54,\n\tFATTR4_MOUNTED_ON_FILEID = 55,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_ACCESS = 84,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_MODIFY = 85,\n};\n\nenum {\n\tFATTR4_XATTR_SUPPORT = 82,\n};\n\nenum {\n\tFBCON_LOGO_CANSHOW = -1,\n\tFBCON_LOGO_DRAW = -2,\n\tFBCON_LOGO_DONTSHOW = -3,\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nenum {\n\tFIB6_NO_SERNUM_CHANGE = 0,\n};\n\nenum {\n\tFILEID_HIGH_OFF = 0,\n\tFILEID_LOW_OFF = 1,\n\tFILE_I_TYPE_OFF = 2,\n\tEMBED_FH_OFF = 3,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_RDYN_STRING = 3,\n\tFILTER_PTR_STRING = 4,\n\tFILTER_TRACE_FN = 5,\n\tFILTER_CPUMASK = 6,\n\tFILTER_COMM = 7,\n\tFILTER_CPU = 8,\n\tFILTER_STACKTRACE = 9,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_MISSING_BRACE_OPEN = 5,\n\tFILT_ERR_MISSING_BRACE_CLOSE = 6,\n\tFILT_ERR_OPERAND_TOO_LONG = 7,\n\tFILT_ERR_EXPECT_STRING = 8,\n\tFILT_ERR_EXPECT_DIGIT = 9,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 10,\n\tFILT_ERR_FIELD_NOT_FOUND = 11,\n\tFILT_ERR_ILLEGAL_INTVAL = 12,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 13,\n\tFILT_ERR_TOO_MANY_PREDS = 14,\n\tFILT_ERR_INVALID_FILTER = 15,\n\tFILT_ERR_INVALID_CPULIST = 16,\n\tFILT_ERR_IP_FIELD_ONLY = 17,\n\tFILT_ERR_INVALID_VALUE = 18,\n\tFILT_ERR_NO_FUNCTION = 19,\n\tFILT_ERR_ERRNO = 20,\n\tFILT_ERR_NO_FILTER = 21,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\nenum {\n\tFRACTION_DENOM = 128,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tHANDSHAKE_A_ACCEPT_SOCKFD = 1,\n\tHANDSHAKE_A_ACCEPT_HANDLER_CLASS = 2,\n\tHANDSHAKE_A_ACCEPT_MESSAGE_TYPE = 3,\n\tHANDSHAKE_A_ACCEPT_TIMEOUT = 4,\n\tHANDSHAKE_A_ACCEPT_AUTH_MODE = 5,\n\tHANDSHAKE_A_ACCEPT_PEER_IDENTITY = 6,\n\tHANDSHAKE_A_ACCEPT_CERTIFICATE = 7,\n\tHANDSHAKE_A_ACCEPT_PEERNAME = 8,\n\tHANDSHAKE_A_ACCEPT_KEYRING = 9,\n\t__HANDSHAKE_A_ACCEPT_MAX = 10,\n\tHANDSHAKE_A_ACCEPT_MAX = 9,\n};\n\nenum {\n\tHANDSHAKE_A_DONE_STATUS = 1,\n\tHANDSHAKE_A_DONE_SOCKFD = 2,\n\tHANDSHAKE_A_DONE_REMOTE_AUTH = 3,\n\t__HANDSHAKE_A_DONE_MAX = 4,\n\tHANDSHAKE_A_DONE_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_A_X509_CERT = 1,\n\tHANDSHAKE_A_X509_PRIVKEY = 2,\n\t__HANDSHAKE_A_X509_MAX = 3,\n\tHANDSHAKE_A_X509_MAX = 2,\n};\n\nenum {\n\tHANDSHAKE_CMD_READY = 1,\n\tHANDSHAKE_CMD_ACCEPT = 2,\n\tHANDSHAKE_CMD_DONE = 3,\n\t__HANDSHAKE_CMD_MAX = 4,\n\tHANDSHAKE_CMD_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_NLGRP_NONE = 0,\n\tHANDSHAKE_NLGRP_TLSHD = 1,\n};\n\nenum {\n\tHASH_SIZE = 128,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHOST_L_CNT = 6,\n};\n\nenum {\n\tHOST_L_DUR = 9,\n};\n\nenum {\n\tHOST_S_CNT = 7,\n};\n\nenum {\n\tHOST_S_DUR = 8,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tICQ_EXITED = 4,\n\tICQ_DESTROYED = 8,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIFAL_ADDRESS = 1,\n\tIFAL_LABEL = 2,\n\t__IFAL_MAX = 3,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET6_UNSPEC = 0,\n\tIFLA_INET6_FLAGS = 1,\n\tIFLA_INET6_CONF = 2,\n\tIFLA_INET6_STATS = 3,\n\tIFLA_INET6_MCAST = 4,\n\tIFLA_INET6_CACHEINFO = 5,\n\tIFLA_INET6_ICMP6STATS = 6,\n\tIFLA_INET6_TOKEN = 7,\n\tIFLA_INET6_ADDR_GEN_MODE = 8,\n\tIFLA_INET6_RA_MTU = 9,\n\t__IFLA_INET6_MAX = 10,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_ACT_NONE = -1,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nenum {\n\tINET6_IFADDR_STATE_PREDAD = 0,\n\tINET6_IFADDR_STATE_DAD = 1,\n\tINET6_IFADDR_STATE_POSTDAD = 2,\n\tINET6_IFADDR_STATE_ERRDAD = 3,\n\tINET6_IFADDR_STATE_DEAD = 4,\n};\n\nenum {\n\tINET_DIAG_BC_NOP = 0,\n\tINET_DIAG_BC_JMP = 1,\n\tINET_DIAG_BC_S_GE = 2,\n\tINET_DIAG_BC_S_LE = 3,\n\tINET_DIAG_BC_D_GE = 4,\n\tINET_DIAG_BC_D_LE = 5,\n\tINET_DIAG_BC_AUTO = 6,\n\tINET_DIAG_BC_S_COND = 7,\n\tINET_DIAG_BC_D_COND = 8,\n\tINET_DIAG_BC_DEV_COND = 9,\n\tINET_DIAG_BC_MARK_COND = 10,\n\tINET_DIAG_BC_S_EQ = 11,\n\tINET_DIAG_BC_D_EQ = 12,\n\tINET_DIAG_BC_CGROUP_COND = 13,\n};\n\nenum {\n\tINET_DIAG_NONE = 0,\n\tINET_DIAG_MEMINFO = 1,\n\tINET_DIAG_INFO = 2,\n\tINET_DIAG_VEGASINFO = 3,\n\tINET_DIAG_CONG = 4,\n\tINET_DIAG_TOS = 5,\n\tINET_DIAG_TCLASS = 6,\n\tINET_DIAG_SKMEMINFO = 7,\n\tINET_DIAG_SHUTDOWN = 8,\n\tINET_DIAG_DCTCPINFO = 9,\n\tINET_DIAG_PROTOCOL = 10,\n\tINET_DIAG_SKV6ONLY = 11,\n\tINET_DIAG_LOCALS = 12,\n\tINET_DIAG_PEERS = 13,\n\tINET_DIAG_PAD = 14,\n\tINET_DIAG_MARK = 15,\n\tINET_DIAG_BBRINFO = 16,\n\tINET_DIAG_CLASS_ID = 17,\n\tINET_DIAG_MD5SIG = 18,\n\tINET_DIAG_ULP_INFO = 19,\n\tINET_DIAG_SK_BPF_STORAGES = 20,\n\tINET_DIAG_CGROUP_ID = 21,\n\tINET_DIAG_SOCKOPT = 22,\n\t__INET_DIAG_MAX = 23,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINET_ULP_INFO_UNSPEC = 0,\n\tINET_ULP_INFO_NAME = 1,\n\tINET_ULP_INFO_TLS = 2,\n\tINET_ULP_INFO_MPTCP = 3,\n\t__INET_ULP_INFO_MAX = 4,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tIOAM6_ATTR_UNSPEC = 0,\n\tIOAM6_ATTR_NS_ID = 1,\n\tIOAM6_ATTR_NS_DATA = 2,\n\tIOAM6_ATTR_NS_DATA_WIDE = 3,\n\tIOAM6_ATTR_SC_ID = 4,\n\tIOAM6_ATTR_SC_DATA = 5,\n\tIOAM6_ATTR_SC_NONE = 6,\n\tIOAM6_ATTR_PAD = 7,\n\t__IOAM6_ATTR_MAX = 8,\n};\n\nenum {\n\tIOAM6_CMD_UNSPEC = 0,\n\tIOAM6_CMD_ADD_NAMESPACE = 1,\n\tIOAM6_CMD_DEL_NAMESPACE = 2,\n\tIOAM6_CMD_DUMP_NAMESPACES = 3,\n\tIOAM6_CMD_ADD_SCHEMA = 4,\n\tIOAM6_CMD_DEL_SCHEMA = 5,\n\tIOAM6_CMD_DUMP_SCHEMAS = 6,\n\tIOAM6_CMD_NS_SET_SCHEMA = 7,\n\t__IOAM6_CMD_MAX = 8,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOMMU_PASID_ARRAY_DOMAIN = 0,\n\tIOMMU_PASID_ARRAY_HANDLE = 1,\n};\n\nenum {\n\tIOMMU_SET_DOMAIN_MUST_SUCCEED = 1,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIPV6_SADDR_RULE_INIT = 0,\n\tIPV6_SADDR_RULE_LOCAL = 1,\n\tIPV6_SADDR_RULE_SCOPE = 2,\n\tIPV6_SADDR_RULE_PREFERRED = 3,\n\tIPV6_SADDR_RULE_OIF = 4,\n\tIPV6_SADDR_RULE_LABEL = 5,\n\tIPV6_SADDR_RULE_PRIVACY = 6,\n\tIPV6_SADDR_RULE_ORCHID = 7,\n\tIPV6_SADDR_RULE_PREFIX = 8,\n\tIPV6_SADDR_RULE_MAX = 9,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tIU_ID_COMMAND = 1,\n\tIU_ID_STATUS = 3,\n\tIU_ID_RESPONSE = 4,\n\tIU_ID_TASK_MGMT = 5,\n\tIU_ID_READ_READY = 6,\n\tIU_ID_WRITE_READY = 7,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = -1,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_FUA = 512,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_NCQ_SEND_RECV = 2048,\n\tATA_DFLAG_NCQ_PRIO = 4096,\n\tATA_DFLAG_CDL = 8192,\n\tATA_DFLAG_CFG_MASK = 16383,\n\tATA_DFLAG_PIO = 16384,\n\tATA_DFLAG_NCQ_OFF = 32768,\n\tATA_DFLAG_SLEEPING = 65536,\n\tATA_DFLAG_DUBIOUS_XFER = 131072,\n\tATA_DFLAG_NO_UNLOAD = 262144,\n\tATA_DFLAG_UNLOCK_HPA = 524288,\n\tATA_DFLAG_INIT_MASK = 1048575,\n\tATA_DFLAG_NCQ_PRIO_ENABLED = 1048576,\n\tATA_DFLAG_CDL_ENABLED = 2097152,\n\tATA_DFLAG_RESUMING = 4194304,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_FEATURES_MASK = 201341696,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DEBOUNCE_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_RESUMING = 65536,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_RTF_FILLED = 4,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_HAS_CDL = 256,\n\tATA_QCFLAG_EH = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_QCFLAG_EH_SUCCESS_CMD = 524288,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_HOST_NO_PART = 16,\n\tATA_HOST_NO_SSC = 32,\n\tATA_HOST_NO_DEVSLP = 64,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 10000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_GET_SUCCESS_SENSE = 64,\n\tATA_EH_SET_ACTIVE = 128,\n\tATA_EH_PERDEV_MASK = 225,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_PRINT_QUIRKS = 2097152,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum {\n\tLINK_CAPA_10HD = 0,\n\tLINK_CAPA_10FD = 1,\n\tLINK_CAPA_100HD = 2,\n\tLINK_CAPA_100FD = 3,\n\tLINK_CAPA_1000HD = 4,\n\tLINK_CAPA_1000FD = 5,\n\tLINK_CAPA_2500FD = 6,\n\tLINK_CAPA_5000FD = 7,\n\tLINK_CAPA_10000FD = 8,\n\tLINK_CAPA_20000FD = 9,\n\tLINK_CAPA_25000FD = 10,\n\tLINK_CAPA_40000FD = 11,\n\tLINK_CAPA_50000FD = 12,\n\tLINK_CAPA_56000FD = 13,\n\tLINK_CAPA_80000FD = 14,\n\tLINK_CAPA_100000FD = 15,\n\tLINK_CAPA_200000FD = 16,\n\tLINK_CAPA_400000FD = 17,\n\tLINK_CAPA_800000FD = 18,\n\tLINK_CAPA_1600000FD = 19,\n\t__LINK_CAPA_MAX = 20,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLK_STATE_IN_USE = 0,\n\tNFS_DELEGATED_STATE = 1,\n\tNFS_OPEN_STATE = 2,\n\tNFS_O_RDONLY_STATE = 3,\n\tNFS_O_WRONLY_STATE = 4,\n\tNFS_O_RDWR_STATE = 5,\n\tNFS_STATE_RECLAIM_REBOOT = 6,\n\tNFS_STATE_RECLAIM_NOGRACE = 7,\n\tNFS_STATE_POSIX_LOCKS = 8,\n\tNFS_STATE_RECOVERY_FAILED = 9,\n\tNFS_STATE_MAY_NOTIFY_LOCK = 10,\n\tNFS_STATE_CHANGE_WAIT = 11,\n\tNFS_CLNT_DST_SSC_COPY_STATE = 12,\n\tNFS_CLNT_SRC_SSC_COPY_STATE = 13,\n\tNFS_SRV_SSC_COPY_STATE = 14,\n};\n\nenum {\n\tLOCKD_A_SERVER_GRACETIME = 1,\n\tLOCKD_A_SERVER_TCP_PORT = 2,\n\tLOCKD_A_SERVER_UDP_PORT = 3,\n\t__LOCKD_A_SERVER_MAX = 4,\n\tLOCKD_A_SERVER_MAX = 3,\n};\n\nenum {\n\tLOCKD_CMD_SERVER_SET = 1,\n\tLOCKD_CMD_SERVER_GET = 2,\n\t__LOCKD_CMD_MAX = 3,\n\tLOCKD_CMD_MAX = 2,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n\tLo_deleting = 3,\n};\n\nenum {\n\tMAGNITUDE_STRONG = 2,\n\tMAGNITUDE_WEAK = 3,\n\tMAGNITUDE_NUM = 4,\n};\n\nenum {\n\tMATCH_MTR = 0,\n\tMATCH_MEQ = 1,\n\tMATCH_MLE = 2,\n\tMATCH_MLT = 3,\n\tMATCH_MGE = 4,\n\tMATCH_MGT = 5,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMBE_REFERENCED_B = 0,\n\tMBE_REUSABLE_B = 1,\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMED_R_CNT = 10,\n};\n\nenum {\n\tMED_R_DUR = 12,\n};\n\nenum {\n\tMED_W_CNT = 11,\n};\n\nenum {\n\tMED_W_DUR = 13,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMEM_LIFE = 4,\n};\n\nenum {\n\tMIPI_DCS_NOP = 0,\n\tMIPI_DCS_SOFT_RESET = 1,\n\tMIPI_DCS_GET_COMPRESSION_MODE = 3,\n\tMIPI_DCS_GET_DISPLAY_ID = 4,\n\tMIPI_DCS_GET_ERROR_COUNT_ON_DSI = 5,\n\tMIPI_DCS_GET_RED_CHANNEL = 6,\n\tMIPI_DCS_GET_GREEN_CHANNEL = 7,\n\tMIPI_DCS_GET_BLUE_CHANNEL = 8,\n\tMIPI_DCS_GET_DISPLAY_STATUS = 9,\n\tMIPI_DCS_GET_POWER_MODE = 10,\n\tMIPI_DCS_GET_ADDRESS_MODE = 11,\n\tMIPI_DCS_GET_PIXEL_FORMAT = 12,\n\tMIPI_DCS_GET_DISPLAY_MODE = 13,\n\tMIPI_DCS_GET_SIGNAL_MODE = 14,\n\tMIPI_DCS_GET_DIAGNOSTIC_RESULT = 15,\n\tMIPI_DCS_ENTER_SLEEP_MODE = 16,\n\tMIPI_DCS_EXIT_SLEEP_MODE = 17,\n\tMIPI_DCS_ENTER_PARTIAL_MODE = 18,\n\tMIPI_DCS_ENTER_NORMAL_MODE = 19,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 20,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_CT = 21,\n\tMIPI_DCS_EXIT_INVERT_MODE = 32,\n\tMIPI_DCS_ENTER_INVERT_MODE = 33,\n\tMIPI_DCS_SET_GAMMA_CURVE = 38,\n\tMIPI_DCS_SET_DISPLAY_OFF = 40,\n\tMIPI_DCS_SET_DISPLAY_ON = 41,\n\tMIPI_DCS_SET_COLUMN_ADDRESS = 42,\n\tMIPI_DCS_SET_PAGE_ADDRESS = 43,\n\tMIPI_DCS_WRITE_MEMORY_START = 44,\n\tMIPI_DCS_WRITE_LUT = 45,\n\tMIPI_DCS_READ_MEMORY_START = 46,\n\tMIPI_DCS_SET_PARTIAL_ROWS = 48,\n\tMIPI_DCS_SET_PARTIAL_COLUMNS = 49,\n\tMIPI_DCS_SET_SCROLL_AREA = 51,\n\tMIPI_DCS_SET_TEAR_OFF = 52,\n\tMIPI_DCS_SET_TEAR_ON = 53,\n\tMIPI_DCS_SET_ADDRESS_MODE = 54,\n\tMIPI_DCS_SET_SCROLL_START = 55,\n\tMIPI_DCS_EXIT_IDLE_MODE = 56,\n\tMIPI_DCS_ENTER_IDLE_MODE = 57,\n\tMIPI_DCS_SET_PIXEL_FORMAT = 58,\n\tMIPI_DCS_WRITE_MEMORY_CONTINUE = 60,\n\tMIPI_DCS_SET_3D_CONTROL = 61,\n\tMIPI_DCS_READ_MEMORY_CONTINUE = 62,\n\tMIPI_DCS_GET_3D_CONTROL = 63,\n\tMIPI_DCS_SET_VSYNC_TIMING = 64,\n\tMIPI_DCS_SET_TEAR_SCANLINE = 68,\n\tMIPI_DCS_GET_SCANLINE = 69,\n\tMIPI_DCS_SET_DISPLAY_BRIGHTNESS = 81,\n\tMIPI_DCS_GET_DISPLAY_BRIGHTNESS = 82,\n\tMIPI_DCS_WRITE_CONTROL_DISPLAY = 83,\n\tMIPI_DCS_GET_CONTROL_DISPLAY = 84,\n\tMIPI_DCS_WRITE_POWER_SAVE = 85,\n\tMIPI_DCS_GET_POWER_SAVE = 86,\n\tMIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 94,\n\tMIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 95,\n\tMIPI_DCS_READ_DDB_START = 161,\n\tMIPI_DCS_READ_PPS_START = 162,\n\tMIPI_DCS_READ_DDB_CONTINUE = 168,\n\tMIPI_DCS_READ_PPS_CONTINUE = 169,\n};\n\nenum {\n\tMIPI_DSI_V_SYNC_START = 1,\n\tMIPI_DSI_V_SYNC_END = 17,\n\tMIPI_DSI_H_SYNC_START = 33,\n\tMIPI_DSI_H_SYNC_END = 49,\n\tMIPI_DSI_COMPRESSION_MODE = 7,\n\tMIPI_DSI_END_OF_TRANSMISSION = 8,\n\tMIPI_DSI_COLOR_MODE_OFF = 2,\n\tMIPI_DSI_COLOR_MODE_ON = 18,\n\tMIPI_DSI_SHUTDOWN_PERIPHERAL = 34,\n\tMIPI_DSI_TURN_ON_PERIPHERAL = 50,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 3,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 19,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 35,\n\tMIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 4,\n\tMIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 20,\n\tMIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 36,\n\tMIPI_DSI_DCS_SHORT_WRITE = 5,\n\tMIPI_DSI_DCS_SHORT_WRITE_PARAM = 21,\n\tMIPI_DSI_DCS_READ = 6,\n\tMIPI_DSI_EXECUTE_QUEUE = 22,\n\tMIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 55,\n\tMIPI_DSI_NULL_PACKET = 9,\n\tMIPI_DSI_BLANKING_PACKET = 25,\n\tMIPI_DSI_GENERIC_LONG_WRITE = 41,\n\tMIPI_DSI_DCS_LONG_WRITE = 57,\n\tMIPI_DSI_PICTURE_PARAMETER_SET = 10,\n\tMIPI_DSI_COMPRESSED_PIXEL_STREAM = 11,\n\tMIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 12,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 28,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 44,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_30 = 13,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_36 = 29,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 61,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_16 = 14,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_18 = 30,\n\tMIPI_DSI_PIXEL_STREAM_3BYTE_18 = 46,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_24 = 62,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMLO_PAUSE_NONE = 0,\n\tMLO_PAUSE_RX = 1,\n\tMLO_PAUSE_TX = 2,\n\tMLO_PAUSE_TXRX_MASK = 3,\n\tMLO_PAUSE_AN = 4,\n\tMLO_AN_PHY = 0,\n\tMLO_AN_FIXED = 1,\n\tMLO_AN_INBAND = 2,\n\tPHYLINK_PCS_NEG_NONE = 0,\n\tPHYLINK_PCS_NEG_ENABLED = 16,\n\tPHYLINK_PCS_NEG_OUTBAND = 32,\n\tPHYLINK_PCS_NEG_INBAND = 64,\n\tPHYLINK_PCS_NEG_INBAND_DISABLED = 64,\n\tPHYLINK_PCS_NEG_INBAND_ENABLED = 80,\n\tMAC_SYM_PAUSE = 1,\n\tMAC_ASYM_PAUSE = 2,\n\tMAC_10HD = 4,\n\tMAC_10FD = 8,\n\tMAC_10 = 12,\n\tMAC_100HD = 16,\n\tMAC_100FD = 32,\n\tMAC_100 = 48,\n\tMAC_1000HD = 64,\n\tMAC_1000FD = 128,\n\tMAC_1000 = 192,\n\tMAC_2500FD = 256,\n\tMAC_5000FD = 512,\n\tMAC_10000FD = 1024,\n\tMAC_20000FD = 2048,\n\tMAC_25000FD = 4096,\n\tMAC_40000FD = 8192,\n\tMAC_50000FD = 16384,\n\tMAC_56000FD = 32768,\n\tMAC_80000FD = 65536,\n\tMAC_100000FD = 131072,\n\tMAC_200000FD = 262144,\n\tMAC_400000FD = 524288,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMOUNTPROC3_NULL = 0,\n\tMOUNTPROC3_MNT = 1,\n\tMOUNTPROC3_DUMP = 2,\n\tMOUNTPROC3_UMNT = 3,\n\tMOUNTPROC3_UMNTALL = 4,\n\tMOUNTPROC3_EXPORT = 5,\n};\n\nenum {\n\tMOUNTPROC_NULL = 0,\n\tMOUNTPROC_MNT = 1,\n\tMOUNTPROC_DUMP = 2,\n\tMOUNTPROC_UMNT = 3,\n\tMOUNTPROC_UMNTALL = 4,\n\tMOUNTPROC_EXPORT = 5,\n};\n\nenum {\n\tMOXA_SUPP_RS232 = 1,\n\tMOXA_SUPP_RS422 = 2,\n\tMOXA_SUPP_RS485 = 4,\n};\n\nenum {\n\tMPOL_DEFAULT = 0,\n\tMPOL_PREFERRED = 1,\n\tMPOL_BIND = 2,\n\tMPOL_INTERLEAVE = 3,\n\tMPOL_LOCAL = 4,\n\tMPOL_PREFERRED_MANY = 5,\n\tMPOL_WEIGHTED_INTERLEAVE = 6,\n\tMPOL_MAX = 7,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tMTD_OPS_PLACE_OOB = 0,\n\tMTD_OPS_AUTO_OOB = 1,\n\tMTD_OPS_RAW = 2,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDD_UNARMED = 1,\n\tNDD_LOCKED = 2,\n\tNDD_SECURITY_OVERWRITE = 3,\n\tNDD_WORK_PENDING = 4,\n\tNDD_LABELING = 6,\n\tNDD_INCOHERENT = 7,\n\tNDD_REGISTER_SYNC = 8,\n\tND_IOCTL_MAX_BUFLEN = 4194304,\n\tND_CMD_MAX_ELEM = 5,\n\tND_CMD_MAX_ENVELOPE = 256,\n\tND_MAX_MAPPINGS = 32,\n\tND_REGION_PAGEMAP = 0,\n\tND_REGION_PERSIST_CACHE = 1,\n\tND_REGION_PERSIST_MEMCTRL = 2,\n\tND_REGION_ASYNC = 3,\n\tND_REGION_CXL = 4,\n\tDPA_RESOURCE_ADJUSTED = 1,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNDUSEROPT_UNSPEC = 0,\n\tNDUSEROPT_SRCADDR = 1,\n\t__NDUSEROPT_MAX = 2,\n};\n\nenum {\n\tND_CMD_IMPLEMENTED = 0,\n\tND_CMD_ARS_CAP = 1,\n\tND_CMD_ARS_START = 2,\n\tND_CMD_ARS_STATUS = 3,\n\tND_CMD_CLEAR_ERROR = 4,\n\tND_CMD_SMART = 1,\n\tND_CMD_SMART_THRESHOLD = 2,\n\tND_CMD_DIMM_FLAGS = 3,\n\tND_CMD_GET_CONFIG_SIZE = 4,\n\tND_CMD_GET_CONFIG_DATA = 5,\n\tND_CMD_SET_CONFIG_DATA = 6,\n\tND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,\n\tND_CMD_VENDOR_EFFECT_LOG = 8,\n\tND_CMD_VENDOR = 9,\n\tND_CMD_CALL = 10,\n};\n\nenum {\n\tND_MAX_LANES = 256,\n\tINT_LBASIZE_ALIGNMENT = 64,\n\tNVDIMM_IO_ATOMIC = 1,\n};\n\nenum {\n\tND_MIN_NAMESPACE_SIZE = 4096,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETDEV_STATS = 0,\n\tE1000_STATS = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_DIAG_MEMINFO = 0,\n\tNETLINK_DIAG_GROUPS = 1,\n\tNETLINK_DIAG_RX_RING = 2,\n\tNETLINK_DIAG_TX_RING = 3,\n\tNETLINK_DIAG_FLAGS = 4,\n\t__NETLINK_DIAG_MAX = 5,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNFSPROC4_CLNT_NULL = 0,\n\tNFSPROC4_CLNT_READ = 1,\n\tNFSPROC4_CLNT_WRITE = 2,\n\tNFSPROC4_CLNT_COMMIT = 3,\n\tNFSPROC4_CLNT_OPEN = 4,\n\tNFSPROC4_CLNT_OPEN_CONFIRM = 5,\n\tNFSPROC4_CLNT_OPEN_NOATTR = 6,\n\tNFSPROC4_CLNT_OPEN_DOWNGRADE = 7,\n\tNFSPROC4_CLNT_CLOSE = 8,\n\tNFSPROC4_CLNT_SETATTR = 9,\n\tNFSPROC4_CLNT_FSINFO = 10,\n\tNFSPROC4_CLNT_RENEW = 11,\n\tNFSPROC4_CLNT_SETCLIENTID = 12,\n\tNFSPROC4_CLNT_SETCLIENTID_CONFIRM = 13,\n\tNFSPROC4_CLNT_LOCK = 14,\n\tNFSPROC4_CLNT_LOCKT = 15,\n\tNFSPROC4_CLNT_LOCKU = 16,\n\tNFSPROC4_CLNT_ACCESS = 17,\n\tNFSPROC4_CLNT_GETATTR = 18,\n\tNFSPROC4_CLNT_LOOKUP = 19,\n\tNFSPROC4_CLNT_LOOKUP_ROOT = 20,\n\tNFSPROC4_CLNT_REMOVE = 21,\n\tNFSPROC4_CLNT_RENAME = 22,\n\tNFSPROC4_CLNT_LINK = 23,\n\tNFSPROC4_CLNT_SYMLINK = 24,\n\tNFSPROC4_CLNT_CREATE = 25,\n\tNFSPROC4_CLNT_PATHCONF = 26,\n\tNFSPROC4_CLNT_STATFS = 27,\n\tNFSPROC4_CLNT_READLINK = 28,\n\tNFSPROC4_CLNT_READDIR = 29,\n\tNFSPROC4_CLNT_SERVER_CAPS = 30,\n\tNFSPROC4_CLNT_DELEGRETURN = 31,\n\tNFSPROC4_CLNT_GETACL = 32,\n\tNFSPROC4_CLNT_SETACL = 33,\n\tNFSPROC4_CLNT_FS_LOCATIONS = 34,\n\tNFSPROC4_CLNT_RELEASE_LOCKOWNER = 35,\n\tNFSPROC4_CLNT_SECINFO = 36,\n\tNFSPROC4_CLNT_FSID_PRESENT = 37,\n\tNFSPROC4_CLNT_EXCHANGE_ID = 38,\n\tNFSPROC4_CLNT_CREATE_SESSION = 39,\n\tNFSPROC4_CLNT_DESTROY_SESSION = 40,\n\tNFSPROC4_CLNT_SEQUENCE = 41,\n\tNFSPROC4_CLNT_GET_LEASE_TIME = 42,\n\tNFSPROC4_CLNT_RECLAIM_COMPLETE = 43,\n\tNFSPROC4_CLNT_LAYOUTGET = 44,\n\tNFSPROC4_CLNT_GETDEVICEINFO = 45,\n\tNFSPROC4_CLNT_LAYOUTCOMMIT = 46,\n\tNFSPROC4_CLNT_LAYOUTRETURN = 47,\n\tNFSPROC4_CLNT_SECINFO_NO_NAME = 48,\n\tNFSPROC4_CLNT_TEST_STATEID = 49,\n\tNFSPROC4_CLNT_FREE_STATEID = 50,\n\tNFSPROC4_CLNT_GETDEVICELIST = 51,\n\tNFSPROC4_CLNT_BIND_CONN_TO_SESSION = 52,\n\tNFSPROC4_CLNT_DESTROY_CLIENTID = 53,\n\tNFSPROC4_CLNT_SEEK = 54,\n\tNFSPROC4_CLNT_ALLOCATE = 55,\n\tNFSPROC4_CLNT_DEALLOCATE = 56,\n\tNFSPROC4_CLNT_ZERO_RANGE = 57,\n\tNFSPROC4_CLNT_LAYOUTSTATS = 58,\n\tNFSPROC4_CLNT_CLONE = 59,\n\tNFSPROC4_CLNT_COPY = 60,\n\tNFSPROC4_CLNT_OFFLOAD_CANCEL = 61,\n\tNFSPROC4_CLNT_LOOKUPP = 62,\n\tNFSPROC4_CLNT_LAYOUTERROR = 63,\n\tNFSPROC4_CLNT_COPY_NOTIFY = 64,\n\tNFSPROC4_CLNT_GETXATTR = 65,\n\tNFSPROC4_CLNT_SETXATTR = 66,\n\tNFSPROC4_CLNT_LISTXATTRS = 67,\n\tNFSPROC4_CLNT_REMOVEXATTR = 68,\n\tNFSPROC4_CLNT_READ_PLUS = 69,\n\tNFSPROC4_CLNT_OFFLOAD_STATUS = 70,\n};\n\nenum {\n\tNFS_DELEGATION_NEED_RECLAIM = 0,\n\tNFS_DELEGATION_RETURN_IF_CLOSED = 1,\n\tNFS_DELEGATION_REFERENCED = 2,\n\tNFS_DELEGATION_RETURNING = 3,\n\tNFS_DELEGATION_REVOKED = 4,\n\tNFS_DELEGATION_TEST_EXPIRED = 5,\n\tNFS_DELEGATION_DELEGTIME = 6,\n};\n\nenum {\n\tNFS_DEVICEID_INVALID = 0,\n\tNFS_DEVICEID_UNAVAILABLE = 1,\n\tNFS_DEVICEID_NOCACHE = 2,\n};\n\nenum {\n\tNFS_IOHDR_ERROR = 0,\n\tNFS_IOHDR_EOF = 1,\n\tNFS_IOHDR_REDO = 2,\n\tNFS_IOHDR_STAT = 3,\n\tNFS_IOHDR_RESEND_PNFS = 4,\n\tNFS_IOHDR_RESEND_MDS = 5,\n\tNFS_IOHDR_UNSTABLE_WRITES = 6,\n\tNFS_IOHDR_ODIRECT = 7,\n};\n\nenum {\n\tNFS_LAYOUT_RO_FAILED = 0,\n\tNFS_LAYOUT_RW_FAILED = 1,\n\tNFS_LAYOUT_BULK_RECALL = 2,\n\tNFS_LAYOUT_RETURN = 3,\n\tNFS_LAYOUT_RETURN_LOCK = 4,\n\tNFS_LAYOUT_RETURN_REQUESTED = 5,\n\tNFS_LAYOUT_INVALID_STID = 6,\n\tNFS_LAYOUT_FIRST_LAYOUTGET = 7,\n\tNFS_LAYOUT_INODE_FREEING = 8,\n\tNFS_LAYOUT_HASHED = 9,\n\tNFS_LAYOUT_DRAIN = 10,\n};\n\nenum {\n\tNFS_LSEG_VALID = 0,\n\tNFS_LSEG_ROC = 1,\n\tNFS_LSEG_LAYOUTCOMMIT = 2,\n\tNFS_LSEG_LAYOUTRETURN = 3,\n\tNFS_LSEG_UNAVAILABLE = 4,\n};\n\nenum {\n\tNFS_OWNER_RECLAIM_REBOOT = 0,\n\tNFS_OWNER_RECLAIM_NOGRACE = 1,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNLM_LCK_GRANTED = 0,\n\tNLM_LCK_DENIED = 1,\n\tNLM_LCK_DENIED_NOLOCKS = 2,\n\tNLM_LCK_BLOCKED = 3,\n\tNLM_LCK_DENIED_GRACE_PERIOD = 4,\n\tNLM_DEADLCK = 5,\n\tNLM_ROFS = 6,\n\tNLM_STALE_FH = 7,\n\tNLM_FBIG = 8,\n\tNLM_FAILED = 9,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNSINDEX_SIG_LEN = 16,\n\tNSINDEX_ALIGN = 256,\n\tNSINDEX_SEQ_MASK = 3,\n\tNSLABEL_UUID_LEN = 16,\n\tNSLABEL_NAME_LEN = 64,\n\tNSLABEL_FLAG_ROLABEL = 1,\n\tNSLABEL_FLAG_LOCAL = 2,\n\tNSLABEL_FLAG_BTT = 4,\n\tNSLABEL_FLAG_UPDATING = 8,\n\tBTT_ALIGN = 4096,\n\tBTTINFO_SIG_LEN = 16,\n\tBTTINFO_UUID_LEN = 16,\n\tBTTINFO_FLAG_ERROR = 1,\n\tBTTINFO_MAJOR_VERSION = 1,\n\tND_LABEL_MIN_SIZE = 1024,\n\tND_LABEL_ID_SIZE = 50,\n\tND_NSINDEX_INIT = 1,\n};\n\nenum {\n\tNSMPROC_NULL = 0,\n\tNSMPROC_STAT = 1,\n\tNSMPROC_MON = 2,\n\tNSMPROC_UNMON = 3,\n\tNSMPROC_UNMON_ALL = 4,\n\tNSMPROC_SIMU_CRASH = 5,\n\tNSMPROC_NOTIFY = 6,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 16,\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n\tNVMEM_LAYOUT_ADD = 5,\n\tNVMEM_LAYOUT_REMOVE = 6,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tOD_NORMAL_SAMPLE = 0,\n\tOD_SUB_SAMPLE = 1,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOpt_block = 0,\n\tOpt_check = 1,\n\tOpt_cruft = 2,\n\tOpt_gid = 3,\n\tOpt_ignore = 4,\n\tOpt_iocharset = 5,\n\tOpt_map = 6,\n\tOpt_mode = 7,\n\tOpt_nojoliet = 8,\n\tOpt_norock = 9,\n\tOpt_sb = 10,\n\tOpt_session = 11,\n\tOpt_uid = 12,\n\tOpt_unhide = 13,\n\tOpt_utf8 = 14,\n\tOpt_err = 15,\n\tOpt_nocompress = 16,\n\tOpt_hide = 17,\n\tOpt_showassoc = 18,\n\tOpt_dmode = 19,\n\tOpt_overriderockperm = 20,\n};\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid = 2,\n\tOpt_nogrpid = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb___2 = 6,\n\tOpt_nouid32 = 7,\n\tOpt_debug = 8,\n\tOpt_removed = 9,\n\tOpt_user_xattr = 10,\n\tOpt_acl = 11,\n\tOpt_auto_da_alloc = 12,\n\tOpt_noauto_da_alloc = 13,\n\tOpt_noload = 14,\n\tOpt_commit = 15,\n\tOpt_min_batch_time = 16,\n\tOpt_max_batch_time = 17,\n\tOpt_journal_dev = 18,\n\tOpt_journal_path = 19,\n\tOpt_journal_checksum = 20,\n\tOpt_journal_async_commit = 21,\n\tOpt_abort = 22,\n\tOpt_data_journal = 23,\n\tOpt_data_ordered = 24,\n\tOpt_data_writeback = 25,\n\tOpt_data_err_abort = 26,\n\tOpt_data_err_ignore = 27,\n\tOpt_test_dummy_encryption = 28,\n\tOpt_inlinecrypt = 29,\n\tOpt_usrjquota = 30,\n\tOpt_grpjquota = 31,\n\tOpt_quota = 32,\n\tOpt_noquota = 33,\n\tOpt_barrier = 34,\n\tOpt_nobarrier = 35,\n\tOpt_err___2 = 36,\n\tOpt_usrquota = 37,\n\tOpt_grpquota = 38,\n\tOpt_prjquota = 39,\n\tOpt_dax = 40,\n\tOpt_dax_always = 41,\n\tOpt_dax_inode = 42,\n\tOpt_dax_never = 43,\n\tOpt_stripe = 44,\n\tOpt_delalloc = 45,\n\tOpt_nodelalloc = 46,\n\tOpt_warn_on_error = 47,\n\tOpt_nowarn_on_error = 48,\n\tOpt_mblk_io_submit = 49,\n\tOpt_debug_want_extra_isize = 50,\n\tOpt_nomblk_io_submit = 51,\n\tOpt_block_validity = 52,\n\tOpt_noblock_validity = 53,\n\tOpt_inode_readahead_blks = 54,\n\tOpt_journal_ioprio = 55,\n\tOpt_dioread_nolock = 56,\n\tOpt_dioread_lock = 57,\n\tOpt_discard = 58,\n\tOpt_nodiscard = 59,\n\tOpt_init_itable = 60,\n\tOpt_noinit_itable = 61,\n\tOpt_max_dir_size_kb = 62,\n\tOpt_nojournal_checksum = 63,\n\tOpt_nombcache = 64,\n\tOpt_no_prefetch_block_bitmaps = 65,\n\tOpt_mb_optimize_scan = 66,\n\tOpt_errors = 67,\n\tOpt_data = 68,\n\tOpt_data_err = 69,\n\tOpt_jqfmt = 70,\n\tOpt_dax_type = 71,\n};\n\nenum {\n\tOpt_check___2 = 0,\n\tOpt_uid___2 = 1,\n\tOpt_gid___2 = 2,\n\tOpt_umask = 3,\n\tOpt_dmask = 4,\n\tOpt_fmask = 5,\n\tOpt_allow_utime = 6,\n\tOpt_codepage = 7,\n\tOpt_usefree = 8,\n\tOpt_nocase = 9,\n\tOpt_quiet = 10,\n\tOpt_showexec = 11,\n\tOpt_debug___2 = 12,\n\tOpt_immutable = 13,\n\tOpt_dots = 14,\n\tOpt_dotsOK = 15,\n\tOpt_charset = 16,\n\tOpt_shortname = 17,\n\tOpt_utf8___2 = 18,\n\tOpt_utf8_bool = 19,\n\tOpt_uni_xl = 20,\n\tOpt_uni_xl_bool = 21,\n\tOpt_nonumtail = 22,\n\tOpt_nonumtail_bool = 23,\n\tOpt_obsolete = 24,\n\tOpt_flush = 25,\n\tOpt_tz = 26,\n\tOpt_rodir = 27,\n\tOpt_errors___2 = 28,\n\tOpt_discard___2 = 29,\n\tOpt_nfs = 30,\n\tOpt_nfs_enum = 31,\n\tOpt_time_offset = 32,\n\tOpt_dos1xfloppy = 33,\n};\n\nenum {\n\tOpt_direct = 0,\n\tOpt_fd = 1,\n\tOpt_gid___3 = 2,\n\tOpt_ignore___2 = 3,\n\tOpt_indirect = 4,\n\tOpt_maxproto = 5,\n\tOpt_minproto = 6,\n\tOpt_offset = 7,\n\tOpt_pgrp = 8,\n\tOpt_strictexpire = 9,\n\tOpt_uid___3 = 10,\n};\n\nenum {\n\tOpt_error = -1,\n\tOpt_context = 0,\n\tOpt_defcontext = 1,\n\tOpt_fscontext = 2,\n\tOpt_rootcontext = 3,\n\tOpt_seclabel = 4,\n};\n\nenum {\n\tOpt_fatal_neterrors_default = 0,\n\tOpt_fatal_neterrors_enetunreach = 1,\n\tOpt_fatal_neterrors_none = 2,\n};\n\nenum {\n\tOpt_find_uid = 0,\n\tOpt_find_gid = 1,\n\tOpt_find_user = 2,\n\tOpt_find_group = 3,\n\tOpt_find_err = 4,\n};\n\nenum {\n\tOpt_local_lock_all = 0,\n\tOpt_local_lock_flock = 1,\n\tOpt_local_lock_none = 2,\n\tOpt_local_lock_posix = 3,\n};\n\nenum {\n\tOpt_lookupcache_all = 0,\n\tOpt_lookupcache_none = 1,\n\tOpt_lookupcache_positive = 2,\n};\n\nenum {\n\tOpt_sec_krb5 = 0,\n\tOpt_sec_krb5i = 1,\n\tOpt_sec_krb5p = 2,\n\tOpt_sec_lkey = 3,\n\tOpt_sec_lkeyi = 4,\n\tOpt_sec_lkeyp = 5,\n\tOpt_sec_none = 6,\n\tOpt_sec_spkm = 7,\n\tOpt_sec_spkmi = 8,\n\tOpt_sec_spkmp = 9,\n\tOpt_sec_sys = 10,\n\tnr__Opt_sec = 11,\n};\n\nenum {\n\tOpt_source = 0,\n\tOpt_debug___3 = 1,\n\tOpt_dfltuid = 2,\n\tOpt_dfltgid = 3,\n\tOpt_afid = 4,\n\tOpt_uname = 5,\n\tOpt_remotename = 6,\n\tOpt_cache = 7,\n\tOpt_cachetag = 8,\n\tOpt_nodevmap = 9,\n\tOpt_noxattr = 10,\n\tOpt_directio = 11,\n\tOpt_ignoreqv = 12,\n\tOpt_access = 13,\n\tOpt_posixacl = 14,\n\tOpt_locktimeout = 15,\n\tOpt_msize = 16,\n\tOpt_trans = 17,\n\tOpt_legacy = 18,\n\tOpt_version = 19,\n\tOpt_rfdno = 20,\n\tOpt_wfdno = 21,\n\tOpt_rq_depth = 22,\n\tOpt_sq_depth = 23,\n\tOpt_timeout = 24,\n\tOpt_port = 25,\n\tOpt_privport = 26,\n};\n\nenum {\n\tOpt_uid___4 = 0,\n\tOpt_gid___4 = 1,\n\tOpt_mode___2 = 2,\n};\n\nenum {\n\tOpt_uid___5 = 0,\n\tOpt_gid___5 = 1,\n\tOpt_mode___3 = 2,\n\tOpt_source___2 = 3,\n};\n\nenum {\n\tOpt_uid___6 = 0,\n\tOpt_gid___6 = 1,\n\tOpt_mode___4 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___3 = 6,\n};\n\nenum {\n\tOpt_vers_2 = 0,\n\tOpt_vers_3 = 1,\n\tOpt_vers_4 = 2,\n\tOpt_vers_4_0 = 3,\n\tOpt_vers_4_1 = 4,\n\tOpt_vers_4_2 = 5,\n};\n\nenum {\n\tOpt_write_lazy = 0,\n\tOpt_write_eager = 1,\n\tOpt_write_wait = 2,\n};\n\nenum {\n\tOpt_xprt_rdma = 0,\n\tOpt_xprt_rdma6 = 1,\n\tOpt_xprt_tcp = 2,\n\tOpt_xprt_tcp6 = 3,\n\tOpt_xprt_udp = 4,\n\tOpt_xprt_udp6 = 5,\n\tnr__Opt_xprt = 6,\n};\n\nenum {\n\tOpt_xprtsec_none = 0,\n\tOpt_xprtsec_tls = 1,\n\tOpt_xprtsec_mtls = 2,\n\tnr__Opt_xprtsec = 3,\n};\n\nenum {\n\tPAGE_REPORTING_IDLE = 0,\n\tPAGE_REPORTING_REQUESTED = 1,\n\tPAGE_REPORTING_ACTIVE = 2,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPARSE_INVALID = 1,\n\tPARSE_NOT_LONGNAME = 2,\n\tPARSE_EOF = 3,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_BRIDGE_RESOURCES = 7,\n\tPCI_BRIDGE_RESOURCE_END = 10,\n\tPCI_NUM_RESOURCES = 11,\n\tDEVICE_COUNT_RESOURCE = 11,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPG_BUSY = 0,\n\tPG_MAPPED = 1,\n\tPG_FOLIO = 2,\n\tPG_CLEAN = 3,\n\tPG_COMMIT_TO_DS = 4,\n\tPG_INODE_REF = 5,\n\tPG_HEADLOCK = 6,\n\tPG_TEARDOWN = 7,\n\tPG_UNLOCKPAGE = 8,\n\tPG_UPTODATE = 9,\n\tPG_WB_END = 10,\n\tPG_REMOVE = 11,\n\tPG_CONTENDED1 = 12,\n\tPG_CONTENDED2 = 13,\n};\n\nenum {\n\tPHYLINK_DISABLE_STOPPED = 0,\n\tPHYLINK_DISABLE_LINK = 1,\n\tPHYLINK_DISABLE_MAC_WOL = 2,\n\tPHYLINK_DISABLE_REPLAY = 3,\n\tPCS_STATE_DOWN = 0,\n\tPCS_STATE_STARTING = 1,\n\tPCS_STATE_STARTED = 2,\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = -1,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nenum {\n\tPMLEN_0 = 0,\n\tPMLEN_7 = 7,\n\tPMLEN_16 = 16,\n};\n\nenum {\n\tPOLICYDB_CAP_NETPEER = 0,\n\tPOLICYDB_CAP_OPENPERM = 1,\n\tPOLICYDB_CAP_EXTSOCKCLASS = 2,\n\tPOLICYDB_CAP_ALWAYSNETWORK = 3,\n\tPOLICYDB_CAP_CGROUPSECLABEL = 4,\n\tPOLICYDB_CAP_NNP_NOSUID_TRANSITION = 5,\n\tPOLICYDB_CAP_GENFS_SECLABEL_SYMLINKS = 6,\n\tPOLICYDB_CAP_IOCTL_SKIP_CLOEXEC = 7,\n\tPOLICYDB_CAP_USERSPACE_INITIAL_CONTEXT = 8,\n\tPOLICYDB_CAP_NETLINK_XPERM = 9,\n\tPOLICYDB_CAP_NETIF_WILDCARD = 10,\n\tPOLICYDB_CAP_GENFS_SECLABEL_WILDCARD = 11,\n\tPOLICYDB_CAP_FUNCTIONFS_SECLABEL = 12,\n\tPOLICYDB_CAP_MEMFD_CLASS = 13,\n\tPOLICYDB_CAP_BPF_TOKEN_PERMS = 14,\n\t__POLICYDB_CAP_MAX = 15,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPOWERON_SECS = 3,\n};\n\nenum {\n\tPOWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_LOW = 2,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_FULL = 5,\n};\n\nenum {\n\tPOWER_SUPPLY_HEALTH_UNKNOWN = 0,\n\tPOWER_SUPPLY_HEALTH_GOOD = 1,\n\tPOWER_SUPPLY_HEALTH_OVERHEAT = 2,\n\tPOWER_SUPPLY_HEALTH_DEAD = 3,\n\tPOWER_SUPPLY_HEALTH_OVERVOLTAGE = 4,\n\tPOWER_SUPPLY_HEALTH_UNDERVOLTAGE = 5,\n\tPOWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 6,\n\tPOWER_SUPPLY_HEALTH_COLD = 7,\n\tPOWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 8,\n\tPOWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 9,\n\tPOWER_SUPPLY_HEALTH_OVERCURRENT = 10,\n\tPOWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 11,\n\tPOWER_SUPPLY_HEALTH_WARM = 12,\n\tPOWER_SUPPLY_HEALTH_COOL = 13,\n\tPOWER_SUPPLY_HEALTH_HOT = 14,\n\tPOWER_SUPPLY_HEALTH_NO_BATTERY = 15,\n\tPOWER_SUPPLY_HEALTH_BLOWN_FUSE = 16,\n\tPOWER_SUPPLY_HEALTH_CELL_IMBALANCE = 17,\n};\n\nenum {\n\tPOWER_SUPPLY_SCOPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_SCOPE_SYSTEM = 1,\n\tPOWER_SUPPLY_SCOPE_DEVICE = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_STATUS_UNKNOWN = 0,\n\tPOWER_SUPPLY_STATUS_CHARGING = 1,\n\tPOWER_SUPPLY_STATUS_DISCHARGING = 2,\n\tPOWER_SUPPLY_STATUS_NOT_CHARGING = 3,\n\tPOWER_SUPPLY_STATUS_FULL = 4,\n};\n\nenum {\n\tPOWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,\n\tPOWER_SUPPLY_TECHNOLOGY_NiMH = 1,\n\tPOWER_SUPPLY_TECHNOLOGY_LION = 2,\n\tPOWER_SUPPLY_TECHNOLOGY_LIPO = 3,\n\tPOWER_SUPPLY_TECHNOLOGY_LiFe = 4,\n\tPOWER_SUPPLY_TECHNOLOGY_NiCd = 5,\n\tPOWER_SUPPLY_TECHNOLOGY_LiMn = 6,\n};\n\nenum {\n\tPREFIX_UNSPEC = 0,\n\tPREFIX_ADDRESS = 1,\n\tPREFIX_CACHEINFO = 2,\n\t__PREFIX_MAX = 3,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tPWMF_REQUESTED = 0,\n\tPWMF_EXPORTED = 1,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQUIRK_NONSTANDARD_CACHE_OPS = 1,\n\tQUIRK_BROKEN_DATA_UNCORR = 2,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tRB_ADD_STAMP_NONE = 0,\n\tRB_ADD_STAMP_EXTEND = 2,\n\tRB_ADD_STAMP_ABSOLUTE = 4,\n\tRB_ADD_STAMP_FORCE = 8,\n};\n\nenum {\n\tRB_CTX_TRANSITION = 0,\n\tRB_CTX_NMI = 1,\n\tRB_CTX_IRQ = 2,\n\tRB_CTX_SOFTIRQ = 3,\n\tRB_CTX_NORMAL = 4,\n\tRB_CTX_MAX = 5,\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nenum {\n\tRC_TMF_COMPLETE = 0,\n\tRC_INVALID_INFO_UNIT = 2,\n\tRC_TMF_NOT_SUPPORTED = 4,\n\tRC_TMF_FAILED = 5,\n\tRC_TMF_SUCCEEDED = 8,\n\tRC_INCORRECT_LUN = 9,\n\tRC_OVERLAPPED_TAG = 10,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tREGULATOR_ERROR_CLEARED = 0,\n\tREGULATOR_FAILED_RETRY = 1,\n\tREGULATOR_ERROR_ON = 2,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 1250,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRES_USAGE = 0,\n\tRES_RSVD_USAGE = 1,\n\tRES_LIMIT = 2,\n\tRES_RSVD_LIMIT = 3,\n\tRES_MAX_USAGE = 4,\n\tRES_RSVD_MAX_USAGE = 5,\n\tRES_FAILCNT = 6,\n\tRES_RSVD_FAILCNT = 7,\n};\n\nenum {\n\tRPCAUTH_lockd = 0,\n\tRPCAUTH_mount = 1,\n\tRPCAUTH_nfs = 2,\n\tRPCAUTH_portmap = 3,\n\tRPCAUTH_statd = 4,\n\tRPCAUTH_nfsd4_cb = 5,\n\tRPCAUTH_cache = 6,\n\tRPCAUTH_nfsd = 7,\n\tRPCAUTH_RootEOF = 8,\n};\n\nenum {\n\tRPCBPROC_NULL = 0,\n\tRPCBPROC_SET = 1,\n\tRPCBPROC_UNSET = 2,\n\tRPCBPROC_GETPORT = 3,\n\tRPCBPROC_GETADDR = 3,\n\tRPCBPROC_DUMP = 4,\n\tRPCBPROC_CALLIT = 5,\n\tRPCBPROC_BCAST = 5,\n\tRPCBPROC_GETTIME = 6,\n\tRPCBPROC_UADDR2TADDR = 7,\n\tRPCBPROC_TADDR2UADDR = 8,\n\tRPCBPROC_GETVERSADDR = 9,\n\tRPCBPROC_INDIRECT = 10,\n\tRPCBPROC_GETADDRLIST = 11,\n\tRPCBPROC_GETSTAT = 12,\n};\n\nenum {\n\tRPCSVC_MAXPAYLOAD = 4194304,\n\tRPCSVC_MAXPAYLOAD_TCP = 4194304,\n\tRPCSVC_MAXPAYLOAD_UDP = 32768,\n};\n\nenum {\n\tRPC_PIPEFS_MOUNT = 0,\n\tRPC_PIPEFS_UMOUNT = 1,\n};\n\nenum {\n\tRPC_TASK_RUNNING = 0,\n\tRPC_TASK_QUEUED = 1,\n\tRPC_TASK_ACTIVE = 2,\n\tRPC_TASK_NEED_XMIT = 3,\n\tRPC_TASK_NEED_RECV = 4,\n\tRPC_TASK_MSG_PIN_WAIT = 5,\n};\n\nenum {\n\tRQ_SECURE = 0,\n\tRQ_LOCAL = 1,\n\tRQ_USEDEFERRAL = 2,\n\tRQ_DROPME = 3,\n\tRQ_VICTIM = 4,\n\tRQ_DATA = 5,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRV_CTX_F_SEEN_TAIL_CALL = 0,\n\tRV_CTX_F_SEEN_CALL = 1,\n\tRV_CTX_F_SEEN_S1 = 9,\n\tRV_CTX_F_SEEN_S2 = 18,\n\tRV_CTX_F_SEEN_S3 = 19,\n\tRV_CTX_F_SEEN_S4 = 20,\n\tRV_CTX_F_SEEN_S5 = 21,\n\tRV_CTX_F_SEEN_S6 = 22,\n};\n\nenum {\n\tRV_REG_ZERO = 0,\n\tRV_REG_RA = 1,\n\tRV_REG_SP = 2,\n\tRV_REG_GP = 3,\n\tRV_REG_TP = 4,\n\tRV_REG_T0 = 5,\n\tRV_REG_T1 = 6,\n\tRV_REG_T2 = 7,\n\tRV_REG_FP = 8,\n\tRV_REG_S1 = 9,\n\tRV_REG_A0 = 10,\n\tRV_REG_A1 = 11,\n\tRV_REG_A2 = 12,\n\tRV_REG_A3 = 13,\n\tRV_REG_A4 = 14,\n\tRV_REG_A5 = 15,\n\tRV_REG_A6 = 16,\n\tRV_REG_A7 = 17,\n\tRV_REG_S2 = 18,\n\tRV_REG_S3 = 19,\n\tRV_REG_S4 = 20,\n\tRV_REG_S5 = 21,\n\tRV_REG_S6 = 22,\n\tRV_REG_S7 = 23,\n\tRV_REG_S8 = 24,\n\tRV_REG_S9 = 25,\n\tRV_REG_S10 = 26,\n\tRV_REG_S11 = 27,\n\tRV_REG_T3 = 28,\n\tRV_REG_T4 = 29,\n\tRV_REG_T5 = 30,\n\tRV_REG_T6 = 31,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tRworksched = 1,\n\tRpending = 2,\n\tWworksched = 4,\n\tWpending = 8,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSCTP_AUTH_HMAC_ID_RESERVED_0 = 0,\n\tSCTP_AUTH_HMAC_ID_SHA1 = 1,\n\tSCTP_AUTH_HMAC_ID_RESERVED_2 = 2,\n\tSCTP_AUTH_HMAC_ID_SHA256 = 3,\n\t__SCTP_AUTH_HMAC_MAX = 4,\n};\n\nenum {\n\tSCTP_MAX_DUP_TSNS = 16,\n};\n\nenum {\n\tSCTP_MAX_STREAM = 65535,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSECTION_MARKED_PRESENT_BIT = 0,\n\tSECTION_HAS_MEM_MAP_BIT = 1,\n\tSECTION_IS_ONLINE_BIT = 2,\n\tSECTION_IS_EARLY_BIT = 3,\n\tSECTION_MAP_LAST_BIT = 4,\n};\n\nenum {\n\tSEG6_ATTR_UNSPEC = 0,\n\tSEG6_ATTR_DST = 1,\n\tSEG6_ATTR_DSTLEN = 2,\n\tSEG6_ATTR_HMACKEYID = 3,\n\tSEG6_ATTR_SECRET = 4,\n\tSEG6_ATTR_SECRETLEN = 5,\n\tSEG6_ATTR_ALGID = 6,\n\tSEG6_ATTR_HMACINFO = 7,\n\t__SEG6_ATTR_MAX = 8,\n};\n\nenum {\n\tSEG6_CMD_UNSPEC = 0,\n\tSEG6_CMD_SETHMAC = 1,\n\tSEG6_CMD_DUMPHMAC = 2,\n\tSEG6_CMD_SET_TUNSRC = 3,\n\tSEG6_CMD_GET_TUNSRC = 4,\n\t__SEG6_CMD_MAX = 5,\n};\n\nenum {\n\tSELNL_MSG_SETENFORCE = 16,\n\tSELNL_MSG_POLICYLOAD = 17,\n\tSELNL_MSG_MAX = 18,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSNDRV_CHMAP_UNKNOWN = 0,\n\tSNDRV_CHMAP_NA = 1,\n\tSNDRV_CHMAP_MONO = 2,\n\tSNDRV_CHMAP_FL = 3,\n\tSNDRV_CHMAP_FR = 4,\n\tSNDRV_CHMAP_RL = 5,\n\tSNDRV_CHMAP_RR = 6,\n\tSNDRV_CHMAP_FC = 7,\n\tSNDRV_CHMAP_LFE = 8,\n\tSNDRV_CHMAP_SL = 9,\n\tSNDRV_CHMAP_SR = 10,\n\tSNDRV_CHMAP_RC = 11,\n\tSNDRV_CHMAP_FLC = 12,\n\tSNDRV_CHMAP_FRC = 13,\n\tSNDRV_CHMAP_RLC = 14,\n\tSNDRV_CHMAP_RRC = 15,\n\tSNDRV_CHMAP_FLW = 16,\n\tSNDRV_CHMAP_FRW = 17,\n\tSNDRV_CHMAP_FLH = 18,\n\tSNDRV_CHMAP_FCH = 19,\n\tSNDRV_CHMAP_FRH = 20,\n\tSNDRV_CHMAP_TC = 21,\n\tSNDRV_CHMAP_TFL = 22,\n\tSNDRV_CHMAP_TFR = 23,\n\tSNDRV_CHMAP_TFC = 24,\n\tSNDRV_CHMAP_TRL = 25,\n\tSNDRV_CHMAP_TRR = 26,\n\tSNDRV_CHMAP_TRC = 27,\n\tSNDRV_CHMAP_TFLC = 28,\n\tSNDRV_CHMAP_TFRC = 29,\n\tSNDRV_CHMAP_TSL = 30,\n\tSNDRV_CHMAP_TSR = 31,\n\tSNDRV_CHMAP_LLFE = 32,\n\tSNDRV_CHMAP_RLFE = 33,\n\tSNDRV_CHMAP_BC = 34,\n\tSNDRV_CHMAP_BLC = 35,\n\tSNDRV_CHMAP_BRC = 36,\n\tSNDRV_CHMAP_LAST = 36,\n};\n\nenum {\n\tSNDRV_CTL_IOCTL_ELEM_LIST32 = 3225965840,\n\tSNDRV_CTL_IOCTL_ELEM_INFO32 = 3239073041,\n\tSNDRV_CTL_IOCTL_ELEM_READ32 = 3267908882,\n\tSNDRV_CTL_IOCTL_ELEM_WRITE32 = 3267908883,\n\tSNDRV_CTL_IOCTL_ELEM_ADD32 = 3239073047,\n\tSNDRV_CTL_IOCTL_ELEM_REPLACE32 = 3239073048,\n};\n\nenum {\n\tSNDRV_CTL_TLV_OP_READ = 0,\n\tSNDRV_CTL_TLV_OP_WRITE = 1,\n\tSNDRV_CTL_TLV_OP_CMD = -1,\n};\n\nenum {\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = 5,\n};\n\nenum {\n\tSNDRV_PCM_CLASS_GENERIC = 0,\n\tSNDRV_PCM_CLASS_MULTI = 1,\n\tSNDRV_PCM_CLASS_MODEM = 2,\n\tSNDRV_PCM_CLASS_DIGITIZER = 3,\n\tSNDRV_PCM_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_PCM_IOCTL_HW_REFINE32 = 3260825872,\n\tSNDRV_PCM_IOCTL_HW_PARAMS32 = 3260825873,\n\tSNDRV_PCM_IOCTL_SW_PARAMS32 = 3228057875,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT32 = 2154578208,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT32 = 3228320036,\n\tSNDRV_PCM_IOCTL_DELAY32 = 2147762465,\n\tSNDRV_PCM_IOCTL_CHANNEL_INFO32 = 2148548914,\n\tSNDRV_PCM_IOCTL_REWIND32 = 1074020678,\n\tSNDRV_PCM_IOCTL_FORWARD32 = 1074020681,\n\tSNDRV_PCM_IOCTL_WRITEI_FRAMES32 = 1074544976,\n\tSNDRV_PCM_IOCTL_READI_FRAMES32 = 2148286801,\n\tSNDRV_PCM_IOCTL_WRITEN_FRAMES32 = 1074544978,\n\tSNDRV_PCM_IOCTL_READN_FRAMES32 = 2148286803,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT64 = 2155888928,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT64 = 3229630756,\n};\n\nenum {\n\tSNDRV_PCM_MMAP_OFFSET_DATA = 0,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_OLD = 2147483648,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_OLD = 2164260864,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_NEW = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_NEW = 2197815296,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL = 2197815296,\n};\n\nenum {\n\tSNDRV_PCM_STREAM_PLAYBACK = 0,\n\tSNDRV_PCM_STREAM_CAPTURE = 1,\n\tSNDRV_PCM_STREAM_LAST = 1,\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_NONE = 0,\n\tSNDRV_PCM_TSTAMP_ENABLE = 1,\n\tSNDRV_PCM_TSTAMP_LAST = 1,\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC = 1,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW = 2,\n\tSNDRV_PCM_TSTAMP_TYPE_LAST = 2,\n};\n\nenum {\n\tSNDRV_TIMER_CLASS_NONE = -1,\n\tSNDRV_TIMER_CLASS_SLAVE = 0,\n\tSNDRV_TIMER_CLASS_GLOBAL = 1,\n\tSNDRV_TIMER_CLASS_CARD = 2,\n\tSNDRV_TIMER_CLASS_PCM = 3,\n\tSNDRV_TIMER_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_TIMER_EVENT_RESOLUTION = 0,\n\tSNDRV_TIMER_EVENT_TICK = 1,\n\tSNDRV_TIMER_EVENT_START = 2,\n\tSNDRV_TIMER_EVENT_STOP = 3,\n\tSNDRV_TIMER_EVENT_CONTINUE = 4,\n\tSNDRV_TIMER_EVENT_PAUSE = 5,\n\tSNDRV_TIMER_EVENT_EARLY = 6,\n\tSNDRV_TIMER_EVENT_SUSPEND = 7,\n\tSNDRV_TIMER_EVENT_RESUME = 8,\n\tSNDRV_TIMER_EVENT_MSTART = 12,\n\tSNDRV_TIMER_EVENT_MSTOP = 13,\n\tSNDRV_TIMER_EVENT_MCONTINUE = 14,\n\tSNDRV_TIMER_EVENT_MPAUSE = 15,\n\tSNDRV_TIMER_EVENT_MSUSPEND = 17,\n\tSNDRV_TIMER_EVENT_MRESUME = 18,\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_GPARAMS32 = 1077695492,\n\tSNDRV_TIMER_IOCTL_INFO32 = 2162185233,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT32 = 1079530516,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT64 = 1080054804,\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_START_OLD = 21536,\n\tSNDRV_TIMER_IOCTL_STOP_OLD = 21537,\n\tSNDRV_TIMER_IOCTL_CONTINUE_OLD = 21538,\n\tSNDRV_TIMER_IOCTL_PAUSE_OLD = 21539,\n};\n\nenum {\n\tSNDRV_TIMER_SCLASS_NONE = 0,\n\tSNDRV_TIMER_SCLASS_APPLICATION = 1,\n\tSNDRV_TIMER_SCLASS_SEQUENCER = 2,\n\tSNDRV_TIMER_SCLASS_OSS_SEQUENCER = 3,\n\tSNDRV_TIMER_SCLASS_LAST = 3,\n};\n\nenum {\n\tSND_CTL_SUBDEV_PCM = 0,\n\tSND_CTL_SUBDEV_RAWMIDI = 1,\n\tSND_CTL_SUBDEV_ITEMS = 2,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSP_TASK_PENDING = 0,\n\tSP_NEED_VICTIM = 1,\n\tSP_VICTIM_REMAINS = 2,\n\tSP_TASK_STARTING = 3,\n};\n\nenum {\n\tSUBMIT_STATUS_URB = 2,\n\tALLOC_DATA_IN_URB = 4,\n\tSUBMIT_DATA_IN_URB = 8,\n\tALLOC_DATA_OUT_URB = 16,\n\tSUBMIT_DATA_OUT_URB = 32,\n\tALLOC_CMD_URB = 64,\n\tSUBMIT_CMD_URB = 128,\n\tCOMMAND_INFLIGHT = 256,\n\tDATA_IN_URB_INFLIGHT = 512,\n\tDATA_OUT_URB_INFLIGHT = 1024,\n\tCOMMAND_ABORTED = 2048,\n\tIS_IN_WORK_LIST = 4096,\n};\n\nenum {\n\tSUNRPC_MAX_UDP_SENDPAGES = 11,\n};\n\nenum {\n\tSUNRPC_PIPEFS_NFS_PRIO = 0,\n\tSUNRPC_PIPEFS_RPC_PRIO = 1,\n};\n\nenum {\n\tSVC_HANDSHAKE_TO = 1250,\n};\n\nenum {\n\tSVC_POOL_AUTO = -1,\n\tSVC_POOL_GLOBAL = 0,\n\tSVC_POOL_PERCPU = 1,\n\tSVC_POOL_PERNODE = 2,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWMII_SPEED_10 = 0,\n\tSWMII_SPEED_100 = 1,\n\tSWMII_SPEED_1000 = 2,\n\tSWMII_DUPLEX_HALF = 0,\n\tSWMII_DUPLEX_FULL = 1,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = -1,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nenum {\n\tSYSTAB = 0,\n\tMMBASE = 1,\n\tMMSIZE = 2,\n\tDCSIZE = 3,\n\tDCVERS = 4,\n\tPARAMCOUNT = 5,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTCA_FLOWER_KEY_CT_FLAGS_NEW = 1,\n\tTCA_FLOWER_KEY_CT_FLAGS_ESTABLISHED = 2,\n\tTCA_FLOWER_KEY_CT_FLAGS_RELATED = 4,\n\tTCA_FLOWER_KEY_CT_FLAGS_TRACKED = 8,\n\tTCA_FLOWER_KEY_CT_FLAGS_INVALID = 16,\n\tTCA_FLOWER_KEY_CT_FLAGS_REPLY = 32,\n\t__TCA_FLOWER_KEY_CT_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_STAB_UNSPEC = 0,\n\tTCA_STAB_BASE = 1,\n\tTCA_STAB_DATA = 2,\n\t__TCA_STAB_MAX = 3,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 1,\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 14,\n\tTCP_DATA_OFFSET = 240,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTC_TAPRIO_CMD_SET_GATES = 0,\n\tTC_TAPRIO_CMD_SET_AND_HOLD = 1,\n\tTC_TAPRIO_CMD_SET_AND_RELEASE = 2,\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nenum {\n\tTLS_ALERT_DESC_CLOSE_NOTIFY = 0,\n\tTLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10,\n\tTLS_ALERT_DESC_BAD_RECORD_MAC = 20,\n\tTLS_ALERT_DESC_RECORD_OVERFLOW = 22,\n\tTLS_ALERT_DESC_HANDSHAKE_FAILURE = 40,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE = 42,\n\tTLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43,\n\tTLS_ALERT_DESC_CERTIFICATE_REVOKED = 44,\n\tTLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45,\n\tTLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46,\n\tTLS_ALERT_DESC_ILLEGAL_PARAMETER = 47,\n\tTLS_ALERT_DESC_UNKNOWN_CA = 48,\n\tTLS_ALERT_DESC_ACCESS_DENIED = 49,\n\tTLS_ALERT_DESC_DECODE_ERROR = 50,\n\tTLS_ALERT_DESC_DECRYPT_ERROR = 51,\n\tTLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52,\n\tTLS_ALERT_DESC_PROTOCOL_VERSION = 70,\n\tTLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71,\n\tTLS_ALERT_DESC_INTERNAL_ERROR = 80,\n\tTLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86,\n\tTLS_ALERT_DESC_USER_CANCELED = 90,\n\tTLS_ALERT_DESC_MISSING_EXTENSION = 109,\n\tTLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110,\n\tTLS_ALERT_DESC_UNRECOGNIZED_NAME = 112,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113,\n\tTLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115,\n\tTLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116,\n\tTLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120,\n};\n\nenum {\n\tTLS_ALERT_LEVEL_WARNING = 1,\n\tTLS_ALERT_LEVEL_FATAL = 2,\n};\n\nenum {\n\tTLS_NO_KEYRING = 0,\n\tTLS_NO_PEERID = 0,\n\tTLS_NO_CERT = 0,\n\tTLS_NO_PRIVKEY = 0,\n};\n\nenum {\n\tTLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20,\n\tTLS_RECORD_TYPE_ALERT = 21,\n\tTLS_RECORD_TYPE_HANDSHAKE = 22,\n\tTLS_RECORD_TYPE_DATA = 23,\n\tTLS_RECORD_TYPE_HEARTBEAT = 24,\n\tTLS_RECORD_TYPE_TLS12_CID = 25,\n\tTLS_RECORD_TYPE_ACK = 26,\n};\n\nenum {\n\tTOO_MANY_CLOSE = -1,\n\tTOO_MANY_OPEN = -2,\n\tMISSING_QUOTE = -3,\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_BAD_MAXACT_TYPE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_NON_UNIQ_SYMBOL = 10,\n\tTP_ERR_BAD_RETPROBE = 11,\n\tTP_ERR_NO_TRACEPOINT = 12,\n\tTP_ERR_BAD_TP_NAME = 13,\n\tTP_ERR_BAD_ADDR_SUFFIX = 14,\n\tTP_ERR_NO_GROUP_NAME = 15,\n\tTP_ERR_GROUP_TOO_LONG = 16,\n\tTP_ERR_BAD_GROUP_NAME = 17,\n\tTP_ERR_NO_EVENT_NAME = 18,\n\tTP_ERR_EVENT_TOO_LONG = 19,\n\tTP_ERR_BAD_EVENT_NAME = 20,\n\tTP_ERR_EVENT_EXIST = 21,\n\tTP_ERR_RETVAL_ON_PROBE = 22,\n\tTP_ERR_NO_RETVAL = 23,\n\tTP_ERR_BAD_STACK_NUM = 24,\n\tTP_ERR_BAD_ARG_NUM = 25,\n\tTP_ERR_BAD_VAR = 26,\n\tTP_ERR_BAD_REG_NAME = 27,\n\tTP_ERR_BAD_MEM_ADDR = 28,\n\tTP_ERR_BAD_IMM = 29,\n\tTP_ERR_IMMSTR_NO_CLOSE = 30,\n\tTP_ERR_FILE_ON_KPROBE = 31,\n\tTP_ERR_BAD_FILE_OFFS = 32,\n\tTP_ERR_SYM_ON_UPROBE = 33,\n\tTP_ERR_TOO_MANY_OPS = 34,\n\tTP_ERR_DEREF_NEED_BRACE = 35,\n\tTP_ERR_BAD_DEREF_OFFS = 36,\n\tTP_ERR_DEREF_OPEN_BRACE = 37,\n\tTP_ERR_COMM_CANT_DEREF = 38,\n\tTP_ERR_BAD_FETCH_ARG = 39,\n\tTP_ERR_ARRAY_NO_CLOSE = 40,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 41,\n\tTP_ERR_BAD_ARRAY_NUM = 42,\n\tTP_ERR_ARRAY_TOO_BIG = 43,\n\tTP_ERR_BAD_TYPE = 44,\n\tTP_ERR_BAD_STRING = 45,\n\tTP_ERR_BAD_SYMSTRING = 46,\n\tTP_ERR_BAD_BITFIELD = 47,\n\tTP_ERR_ARG_NAME_TOO_LONG = 48,\n\tTP_ERR_NO_ARG_NAME = 49,\n\tTP_ERR_BAD_ARG_NAME = 50,\n\tTP_ERR_USED_ARG_NAME = 51,\n\tTP_ERR_ARG_TOO_LONG = 52,\n\tTP_ERR_NO_ARG_BODY = 53,\n\tTP_ERR_BAD_INSN_BNDRY = 54,\n\tTP_ERR_FAIL_REG_PROBE = 55,\n\tTP_ERR_DIFF_PROBE_TYPE = 56,\n\tTP_ERR_DIFF_ARG_TYPE = 57,\n\tTP_ERR_SAME_PROBE = 58,\n\tTP_ERR_NO_EVENT_INFO = 59,\n\tTP_ERR_BAD_ATTACH_EVENT = 60,\n\tTP_ERR_BAD_ATTACH_ARG = 61,\n\tTP_ERR_NO_EP_FILTER = 62,\n\tTP_ERR_NOSUP_BTFARG = 63,\n\tTP_ERR_NO_BTFARG = 64,\n\tTP_ERR_NO_BTF_ENTRY = 65,\n\tTP_ERR_BAD_VAR_ARGS = 66,\n\tTP_ERR_NOFENTRY_ARGS = 67,\n\tTP_ERR_DOUBLE_ARGS = 68,\n\tTP_ERR_ARGS_2LONG = 69,\n\tTP_ERR_ARGIDX_2BIG = 70,\n\tTP_ERR_NO_PTR_STRCT = 71,\n\tTP_ERR_NOSUP_DAT_ARG = 72,\n\tTP_ERR_BAD_HYPHEN = 73,\n\tTP_ERR_NO_BTF_FIELD = 74,\n\tTP_ERR_BAD_BTF_TID = 75,\n\tTP_ERR_BAD_TYPE4STR = 76,\n\tTP_ERR_NEED_STRING_TYPE = 77,\n\tTP_ERR_TOO_MANY_ARGS = 78,\n\tTP_ERR_TOO_MANY_EARGS = 79,\n};\n\nenum {\n\tTRACEFS_EVENT_INODE = 2,\n\tTRACEFS_GID_PERM_SET = 4,\n\tTRACEFS_UID_PERM_SET = 8,\n\tTRACEFS_INSTANCE_INODE = 16,\n};\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n\tTRACE_ARRAY_FL_BOOT = 2,\n\tTRACE_ARRAY_FL_LAST_BOOT = 4,\n\tTRACE_ARRAY_FL_MOD_INIT = 8,\n\tTRACE_ARRAY_FL_MEMMAP = 16,\n\tTRACE_ARRAY_FL_VMALLOC = 32,\n};\n\nenum {\n\tTRACE_CTX_NMI = 0,\n\tTRACE_CTX_IRQ = 1,\n\tTRACE_CTX_SOFTIRQ = 2,\n\tTRACE_CTX_NORMAL = 3,\n\tTRACE_CTX_TRANSITION = 4,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 4,\n\tTRACE_EVENT_FL_TRACEPOINT = 8,\n\tTRACE_EVENT_FL_DYNAMIC = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n\tTRACE_EVENT_FL_EPROBE = 128,\n\tTRACE_EVENT_FL_FPROBE = 256,\n\tTRACE_EVENT_FL_CUSTOM = 512,\n\tTRACE_EVENT_FL_TEST_STR = 1024,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_FTRACE_BIT = 0,\n\tTRACE_FTRACE_NMI_BIT = 1,\n\tTRACE_FTRACE_IRQ_BIT = 2,\n\tTRACE_FTRACE_SIRQ_BIT = 3,\n\tTRACE_FTRACE_TRANSITION_BIT = 4,\n\tTRACE_INTERNAL_BIT = 5,\n\tTRACE_INTERNAL_NMI_BIT = 6,\n\tTRACE_INTERNAL_IRQ_BIT = 7,\n\tTRACE_INTERNAL_SIRQ_BIT = 8,\n\tTRACE_INTERNAL_TRANSITION_BIT = 9,\n\tTRACE_INTERNAL_EVENT_BIT = 10,\n\tTRACE_INTERNAL_EVENT_NMI_BIT = 11,\n\tTRACE_INTERNAL_EVENT_IRQ_BIT = 12,\n\tTRACE_INTERNAL_EVENT_SIRQ_BIT = 13,\n\tTRACE_INTERNAL_EVENT_TRANSITION_BIT = 14,\n\tTRACE_BRANCH_BIT = 15,\n\tTRACE_IRQ_BIT = 16,\n\tTRACE_RECORD_RECURSION_BIT = 17,\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tTRANS_MODE_PIO = 0,\n\tTRANS_MODE_IDMAC = 1,\n\tTRANS_MODE_EDMAC = 2,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tUS_FL_SINGLE_LUN = 1,\n\tUS_FL_NEED_OVERRIDE = 2,\n\tUS_FL_SCM_MULT_TARG = 4,\n\tUS_FL_FIX_INQUIRY = 8,\n\tUS_FL_FIX_CAPACITY = 16,\n\tUS_FL_IGNORE_RESIDUE = 32,\n\tUS_FL_BULK32 = 64,\n\tUS_FL_NOT_LOCKABLE = 128,\n\tUS_FL_GO_SLOW = 256,\n\tUS_FL_NO_WP_DETECT = 512,\n\tUS_FL_MAX_SECTORS_64 = 1024,\n\tUS_FL_IGNORE_DEVICE = 2048,\n\tUS_FL_CAPACITY_HEURISTICS = 4096,\n\tUS_FL_MAX_SECTORS_MIN = 8192,\n\tUS_FL_BULK_IGNORE_TAG = 16384,\n\tUS_FL_SANE_SENSE = 32768,\n\tUS_FL_CAPACITY_OK = 65536,\n\tUS_FL_BAD_SENSE = 131072,\n\tUS_FL_NO_READ_DISC_INFO = 262144,\n\tUS_FL_NO_READ_CAPACITY_16 = 524288,\n\tUS_FL_INITIAL_READ10 = 1048576,\n\tUS_FL_WRITE_CACHE = 2097152,\n\tUS_FL_NEEDS_CAP16 = 4194304,\n\tUS_FL_IGNORE_UAS = 8388608,\n\tUS_FL_BROKEN_FUA = 16777216,\n\tUS_FL_NO_ATA_1X = 33554432,\n\tUS_FL_NO_REPORT_OPCODES = 67108864,\n\tUS_FL_MAX_SECTORS_240 = 134217728,\n\tUS_FL_NO_REPORT_LUNS = 268435456,\n\tUS_FL_ALWAYS_SYNC = 536870912,\n\tUS_FL_NO_SAME = 1073741824,\n\tUS_FL_SENSE_AFTER_SYNC = 2147483648,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tVP_MSIX_CONFIG_VECTOR = 0,\n\tVP_MSIX_VQ_VECTOR = 1,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_DEV_OFFLOAD_UNSPECIFIED = 0,\n\tXFRM_DEV_OFFLOAD_CRYPTO = 1,\n\tXFRM_DEV_OFFLOAD_PACKET = 2,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MODE_FLAG_TUNNEL = 1,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tXFRM_STATE_VOID = 0,\n\tXFRM_STATE_ACQ = 1,\n\tXFRM_STATE_VALID = 2,\n\tXFRM_STATE_ERROR = 3,\n\tXFRM_STATE_EXPIRED = 4,\n\tXFRM_STATE_DEAD = 5,\n};\n\nenum {\n\tXPT_BUSY = 0,\n\tXPT_CONN = 1,\n\tXPT_CLOSE = 2,\n\tXPT_DATA = 3,\n\tXPT_TEMP = 4,\n\tXPT_DEAD = 5,\n\tXPT_CHNGBUF = 6,\n\tXPT_DEFERRED = 7,\n\tXPT_OLD = 8,\n\tXPT_LISTENER = 9,\n\tXPT_CACHE_AUTH = 10,\n\tXPT_LOCAL = 11,\n\tXPT_KILL_TEMP = 12,\n\tXPT_CONG_CTRL = 13,\n\tXPT_HANDSHAKE = 14,\n\tXPT_TLS_SESSION = 15,\n\tXPT_PEER_AUTH = 16,\n\tXPT_PEER_VALID = 17,\n\tXPT_RPCB_UNREG = 18,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tZONELIST_NOFALLBACK = 1,\n\tMAX_ZONELISTS = 2,\n};\n\nenum {\n\tZSTDbss_compress = 0,\n\tZSTDbss_noCompress = 1,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 0,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 10,\n\t__SCHED_FEAT_HRTICK = 11,\n\t__SCHED_FEAT_HRTICK_DL = 12,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 13,\n\t__SCHED_FEAT_TTWU_QUEUE = 14,\n\t__SCHED_FEAT_SIS_UTIL = 15,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 16,\n\t__SCHED_FEAT_RT_PUSH_IPI = 17,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 18,\n\t__SCHED_FEAT_LB_MIN = 19,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 20,\n\t__SCHED_FEAT_WA_IDLE = 21,\n\t__SCHED_FEAT_WA_WEIGHT = 22,\n\t__SCHED_FEAT_WA_BIAS = 23,\n\t__SCHED_FEAT_UTIL_EST = 24,\n\t__SCHED_FEAT_LATENCY_WARN = 25,\n\t__SCHED_FEAT_NI_RANDOM = 26,\n\t__SCHED_FEAT_NR = 27,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NO_OBJ_EXT_BIT = 24,\n\t___GFP_LAST_BIT = 25,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SKB = 4,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK = 5,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 7,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 8,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 9,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 10,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 11,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 12,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 13,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 14,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 15,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 16,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 17,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 18,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 19,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 20,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_DEVICE = 21,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SYSCTL = 22,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCKOPT = 23,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 24,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 25,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 26,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 27,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 28,\n\t__ctx_convertBPF_PROG_TYPE_NETFILTER = 29,\n\t__ctx_convert_unused = 30,\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_sra_exceeded_retry_limit = 5,\n\tattr_inode_readahead = 6,\n\tattr_trigger_test_error = 7,\n\tattr_first_error_time = 8,\n\tattr_last_error_time = 9,\n\tattr_clusters_in_group = 10,\n\tattr_mb_order = 11,\n\tattr_feature = 12,\n\tattr_pointer_pi = 13,\n\tattr_pointer_ui = 14,\n\tattr_pointer_ul = 15,\n\tattr_pointer_u64 = 16,\n\tattr_pointer_u8 = 17,\n\tattr_pointer_string = 18,\n\tattr_pointer_atomic = 19,\n\tattr_journal_task = 20,\n\tattr_err_report_sec = 21,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\tmechtype_caddy = 0,\n\tmechtype_tray = 1,\n\tmechtype_popup = 2,\n\tmechtype_individual_changer = 4,\n\tmechtype_cartridge_changer = 5,\n};\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tEfiPciIoWidthUint8 = 0,\n\tEfiPciIoWidthUint16 = 1,\n\tEfiPciIoWidthUint32 = 2,\n\tEfiPciIoWidthUint64 = 3,\n\tEfiPciIoWidthFifoUint8 = 4,\n\tEfiPciIoWidthFifoUint16 = 5,\n\tEfiPciIoWidthFifoUint32 = 6,\n\tEfiPciIoWidthFifoUint64 = 7,\n\tEfiPciIoWidthFillUint8 = 8,\n\tEfiPciIoWidthFillUint16 = 9,\n\tEfiPciIoWidthFillUint32 = 10,\n\tEfiPciIoWidthFillUint64 = 11,\n\tEfiPciIoWidthMaximum = 12,\n} EFI_PCI_IO_PROTOCOL_WIDTH;\n\ntypedef enum {\n\tEfiTimerCancel = 0,\n\tEfiTimerPeriodic = 1,\n\tEfiTimerRelative = 2,\n} EFI_TIMER_DELAY;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tFSE_repeat_none = 0,\n\tFSE_repeat_check = 1,\n\tFSE_repeat_valid = 2,\n} FSE_repeat;\n\ntypedef enum {\n\ttrustInput = 0,\n\tcheckMaxSymbolValue = 1,\n} HIST_checkInput_e;\n\ntypedef enum {\n\tHUF_singleStream = 0,\n\tHUF_fourStreams = 1,\n} HUF_nbStreams_e;\n\ntypedef enum {\n\tHUF_repeat_none = 0,\n\tHUF_repeat_check = 1,\n\tHUF_repeat_valid = 2,\n} HUF_repeat;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_cpm_noAttachDict = 0,\n\tZSTD_cpm_attachDict = 1,\n\tZSTD_cpm_createCDict = 2,\n\tZSTD_cpm_unknown = 3,\n} ZSTD_CParamMode_e;\n\ntypedef enum {\n\tZSTD_defaultDisallowed = 0,\n\tZSTD_defaultAllowed = 1,\n} ZSTD_DefaultPolicy_e;\n\ntypedef enum {\n\tZSTD_e_continue = 0,\n\tZSTD_e_flush = 1,\n\tZSTD_e_end = 2,\n} ZSTD_EndDirective;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tzop_dynamic = 0,\n\tzop_predef = 1,\n} ZSTD_OptPrice_e;\n\ntypedef enum {\n\tZSTD_ps_auto = 0,\n\tZSTD_ps_enable = 1,\n\tZSTD_ps_disable = 2,\n} ZSTD_ParamSwitch_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_sf_noBlockDelimiters = 0,\n\tZSTD_sf_explicitBlockDelimiters = 1,\n} ZSTD_SequenceFormat_e;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTDb_not_buffered = 0,\n\tZSTDb_buffered = 1,\n} ZSTD_buffered_policy_e;\n\ntypedef enum {\n\tZSTD_c_compressionLevel = 100,\n\tZSTD_c_windowLog = 101,\n\tZSTD_c_hashLog = 102,\n\tZSTD_c_chainLog = 103,\n\tZSTD_c_searchLog = 104,\n\tZSTD_c_minMatch = 105,\n\tZSTD_c_targetLength = 106,\n\tZSTD_c_strategy = 107,\n\tZSTD_c_targetCBlockSize = 130,\n\tZSTD_c_enableLongDistanceMatching = 160,\n\tZSTD_c_ldmHashLog = 161,\n\tZSTD_c_ldmMinMatch = 162,\n\tZSTD_c_ldmBucketSizeLog = 163,\n\tZSTD_c_ldmHashRateLog = 164,\n\tZSTD_c_contentSizeFlag = 200,\n\tZSTD_c_checksumFlag = 201,\n\tZSTD_c_dictIDFlag = 202,\n\tZSTD_c_nbWorkers = 400,\n\tZSTD_c_jobSize = 401,\n\tZSTD_c_overlapLog = 402,\n\tZSTD_c_experimentalParam1 = 500,\n\tZSTD_c_experimentalParam2 = 10,\n\tZSTD_c_experimentalParam3 = 1000,\n\tZSTD_c_experimentalParam4 = 1001,\n\tZSTD_c_experimentalParam5 = 1002,\n\tZSTD_c_experimentalParam7 = 1004,\n\tZSTD_c_experimentalParam8 = 1005,\n\tZSTD_c_experimentalParam9 = 1006,\n\tZSTD_c_experimentalParam10 = 1007,\n\tZSTD_c_experimentalParam11 = 1008,\n\tZSTD_c_experimentalParam12 = 1009,\n\tZSTD_c_experimentalParam13 = 1010,\n\tZSTD_c_experimentalParam14 = 1011,\n\tZSTD_c_experimentalParam15 = 1012,\n\tZSTD_c_experimentalParam16 = 1013,\n\tZSTD_c_experimentalParam17 = 1014,\n\tZSTD_c_experimentalParam18 = 1015,\n\tZSTD_c_experimentalParam19 = 1016,\n\tZSTD_c_experimentalParam20 = 1017,\n} ZSTD_cParameter;\n\ntypedef enum {\n\tzcss_init = 0,\n\tzcss_load = 1,\n\tzcss_flush = 2,\n} ZSTD_cStreamStage;\n\ntypedef enum {\n\tZSTDcrp_makeClean = 0,\n\tZSTDcrp_leaveDirty = 1,\n} ZSTD_compResetPolicy_e;\n\ntypedef enum {\n\tZSTDcs_created = 0,\n\tZSTDcs_init = 1,\n\tZSTDcs_ongoing = 2,\n\tZSTDcs_ending = 3,\n} ZSTD_compressionStage_e;\n\ntypedef enum {\n\tZSTD_cwksp_alloc_objects = 0,\n\tZSTD_cwksp_alloc_aligned_init_once = 1,\n\tZSTD_cwksp_alloc_aligned = 2,\n\tZSTD_cwksp_alloc_buffers = 3,\n} ZSTD_cwksp_alloc_phase_e;\n\ntypedef enum {\n\tZSTD_cwksp_dynamic_alloc = 0,\n\tZSTD_cwksp_static_alloc = 1,\n} ZSTD_cwksp_static_alloc_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dictDefaultAttach = 0,\n\tZSTD_dictForceAttach = 1,\n\tZSTD_dictForceCopy = 2,\n\tZSTD_dictForceLoad = 3,\n} ZSTD_dictAttachPref_e;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_noDict = 0,\n\tZSTD_extDict = 1,\n\tZSTD_dictMatchState = 2,\n\tZSTD_dedicatedDictSearch = 3,\n} ZSTD_dictMode_e;\n\ntypedef enum {\n\tZSTD_dtlm_fast = 0,\n\tZSTD_dtlm_full = 1,\n} ZSTD_dictTableLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTDirp_continue = 0,\n\tZSTDirp_reset = 1,\n} ZSTD_indexResetPolicy_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_llt_none = 0,\n\tZSTD_llt_literalLength = 1,\n\tZSTD_llt_matchLength = 2,\n} ZSTD_longLengthType_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tZSTD_resetTarget_CDict = 0,\n\tZSTD_resetTarget_CCtx = 1,\n} ZSTD_resetTarget_e;\n\ntypedef enum {\n\tZSTD_fast = 1,\n\tZSTD_dfast = 2,\n\tZSTD_greedy = 3,\n\tZSTD_lazy = 4,\n\tZSTD_lazy2 = 5,\n\tZSTD_btlazy2 = 6,\n\tZSTD_btopt = 7,\n\tZSTD_btultra = 8,\n\tZSTD_btultra2 = 9,\n} ZSTD_strategy;\n\ntypedef enum {\n\tZSTD_tfp_forCCtx = 0,\n\tZSTD_tfp_forCDict = 1,\n} ZSTD_tableFillPurpose_e;\n\ntypedef enum {\n\tOSL_GLOBAL_LOCK_HANDLER = 0,\n\tOSL_NOTIFY_HANDLER = 1,\n\tOSL_GPE_HANDLER = 2,\n\tOSL_DEBUGGER_MAIN_THREAD = 3,\n\tOSL_DEBUGGER_EXEC_THREAD = 4,\n\tOSL_EC_POLL_HANDLER = 5,\n\tOSL_EC_BURST_HANDLER = 6,\n} acpi_execute_type;\n\ntypedef enum {\n\tACPI_IMODE_LOAD_PASS1 = 1,\n\tACPI_IMODE_LOAD_PASS2 = 2,\n\tACPI_IMODE_EXECUTE = 3,\n} acpi_interpreter_mode;\n\ntypedef enum {\n\tACPI_TRACE_AML_METHOD = 0,\n\tACPI_TRACE_AML_OPCODE = 1,\n\tACPI_TRACE_AML_REGION = 2,\n} acpi_trace_event_type;\n\ntypedef enum {\n\tbase_0possible = 0,\n\tbase_1guaranteed = 1,\n} base_directive_e;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n\tEXT4_IGET_BAD = 4,\n\tEXT4_IGET_EA_INODE = 8,\n} ext4_iget_flags;\n\ntypedef enum {\n\tFL_READY = 0,\n\tFL_STATUS = 1,\n\tFL_CFI_QUERY = 2,\n\tFL_JEDEC_QUERY = 3,\n\tFL_ERASING = 4,\n\tFL_ERASE_SUSPENDING = 5,\n\tFL_ERASE_SUSPENDED = 6,\n\tFL_WRITING = 7,\n\tFL_WRITING_TO_BUFFER = 8,\n\tFL_OTP_WRITE = 9,\n\tFL_WRITE_SUSPENDING = 10,\n\tFL_WRITE_SUSPENDED = 11,\n\tFL_PM_SUSPENDED = 12,\n\tFL_SYNCING = 13,\n\tFL_UNLOADING = 14,\n\tFL_LOCKING = 15,\n\tFL_UNLOCKING = 16,\n\tFL_POINT = 17,\n\tFL_XIP_WHILE_ERASING = 18,\n\tFL_XIP_WHILE_WRITING = 19,\n\tFL_SHUTDOWN = 20,\n\tFL_READING = 21,\n\tFL_CACHEDPRG = 22,\n\tFL_RESETTING = 23,\n\tFL_OTPING = 24,\n\tFL_PREPARING_ERASE = 25,\n\tFL_VERIFYING_ERASE = 26,\n\tFL_UNKNOWN = 27,\n} flstate_t;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tMAP_CHG_REUSE = 0,\n\tMAP_CHG_NEEDED = 1,\n\tMAP_CHG_ENFORCED = 2,\n} map_chg_state;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\ntypedef enum {\n\tsearch_hashChain = 0,\n\tsearch_binaryTree = 1,\n\tsearch_rowHash = 2,\n} searchMethod_e;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum CV1800B_POWER_DOMAIN {\n\tVDD18A_AUD = 0,\n\tVDD18A_USB_PLL_ETH_CSI = 1,\n\tVDD33A_ETH_USB_SD1 = 2,\n\tVDDIO_RTC = 3,\n\tVDDIO_SD0_SPI = 4,\n};\n\nenum CV1812H_POWER_DOMAIN {\n\tVDD18A_EPHY = 0,\n\tVDD18A_MIPI = 1,\n\tVDDIO18_1 = 2,\n\tVDDIO_EMMC = 3,\n\tVDDIO_RTC___2 = 4,\n\tVDDIO_SD0 = 5,\n\tVDDIO_SD1 = 6,\n\tVDDIO_VIVO = 7,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum SG2000_POWER_DOMAIN {\n\tVDD18A_EPHY___2 = 0,\n\tVDD18A_MIPI___2 = 1,\n\tVDDIO18_1___2 = 2,\n\tVDDIO_EMMC___2 = 3,\n\tVDDIO_RTC___3 = 4,\n\tVDDIO_SD0___2 = 5,\n\tVDDIO_SD1___2 = 6,\n\tVDDIO_VIVO___2 = 7,\n};\n\nenum SG2002_POWER_DOMAIN {\n\tVDD18A_MIPI___3 = 0,\n\tVDD18A_USB_PLL_ETH = 1,\n\tVDDIO_RTC___4 = 2,\n\tVDDIO_SD0_EMMC = 3,\n\tVDDIO_SD1___3 = 4,\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum UART_TX_FLAGS {\n\tUART_TX_NOSTOP = 1,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_ACCOUNT = 13,\n\t_SLAB_NO_USER_FLAGS = 14,\n\t_SLAB_RECLAIM_ACCOUNT = 15,\n\t_SLAB_OBJECT_POISON = 16,\n\t_SLAB_CMPXCHG_DOUBLE = 17,\n\t_SLAB_NO_OBJ_EXT = 18,\n\t_SLAB_OBJ_EXT_IN_OBJ = 19,\n\t_SLAB_FLAGS_LAST_BIT = 20,\n};\n\nenum aa_code {\n\tAA_U8 = 0,\n\tAA_U16 = 1,\n\tAA_U32 = 2,\n\tAA_U64 = 3,\n\tAA_NAME = 4,\n\tAA_STRING = 5,\n\tAA_BLOB = 6,\n\tAA_STRUCT = 7,\n\tAA_STRUCTEND = 8,\n\tAA_LIST = 9,\n\tAA_LISTEND = 10,\n\tAA_ARRAY = 11,\n\tAA_ARRAYEND = 12,\n};\n\nenum aa_sfs_type {\n\tAA_SFS_TYPE_BOOLEAN = 0,\n\tAA_SFS_TYPE_STRING = 1,\n\tAA_SFS_TYPE_U64 = 2,\n\tAA_SFS_TYPE_FOPS = 3,\n\tAA_SFS_TYPE_DIR = 4,\n};\n\nenum aafs_ns_type {\n\tAAFS_NS_DIR = 0,\n\tAAFS_NS_PROFS = 1,\n\tAAFS_NS_NS = 2,\n\tAAFS_NS_RAW_DATA = 3,\n\tAAFS_NS_LOAD = 4,\n\tAAFS_NS_REPLACE = 5,\n\tAAFS_NS_REMOVE = 6,\n\tAAFS_NS_REVISION = 7,\n\tAAFS_NS_COUNT = 8,\n\tAAFS_NS_MAX_COUNT = 9,\n\tAAFS_NS_SIZE = 10,\n\tAAFS_NS_MAX_SIZE = 11,\n\tAAFS_NS_OWNER = 12,\n\tAAFS_NS_SIZEOF = 13,\n};\n\nenum aafs_prof_type {\n\tAAFS_PROF_DIR = 0,\n\tAAFS_PROF_PROFS = 1,\n\tAAFS_PROF_NAME = 2,\n\tAAFS_PROF_MODE = 3,\n\tAAFS_PROF_ATTACH = 4,\n\tAAFS_PROF_HASH = 5,\n\tAAFS_PROF_RAW_DATA = 6,\n\tAAFS_PROF_RAW_HASH = 7,\n\tAAFS_PROF_RAW_ABI = 8,\n\tAAFS_PROF_SIZEOF = 9,\n};\n\nenum access_coordinate_class {\n\tACCESS_COORDINATE_LOCAL = 0,\n\tACCESS_COORDINATE_CPU = 1,\n\tACCESS_COORDINATE_MAX = 2,\n};\n\nenum acpi_attr_enum {\n\tACPI_ATTR_LABEL_SHOW = 0,\n\tACPI_ATTR_INDEX_SHOW = 1,\n};\n\nenum acpi_bridge_type {\n\tACPI_BRIDGE_TYPE_PCIE = 1,\n\tACPI_BRIDGE_TYPE_CXL = 2,\n};\n\nenum acpi_bus_device_type {\n\tACPI_BUS_TYPE_DEVICE = 0,\n\tACPI_BUS_TYPE_POWER = 1,\n\tACPI_BUS_TYPE_PROCESSOR = 2,\n\tACPI_BUS_TYPE_THERMAL = 3,\n\tACPI_BUS_TYPE_POWER_BUTTON = 4,\n\tACPI_BUS_TYPE_SLEEP_BUTTON = 5,\n\tACPI_BUS_TYPE_ECDT_EC = 6,\n\tACPI_BUS_DEVICE_TYPE_COUNT = 7,\n};\n\nenum acpi_cdat_type {\n\tACPI_CDAT_TYPE_DSMAS = 0,\n\tACPI_CDAT_TYPE_DSLBIS = 1,\n\tACPI_CDAT_TYPE_DSMSCIS = 2,\n\tACPI_CDAT_TYPE_DSIS = 3,\n\tACPI_CDAT_TYPE_DSEMTS = 4,\n\tACPI_CDAT_TYPE_SSLBIS = 5,\n\tACPI_CDAT_TYPE_RESERVED = 6,\n};\n\nenum acpi_cedt_type {\n\tACPI_CEDT_TYPE_CHBS = 0,\n\tACPI_CEDT_TYPE_CFMWS = 1,\n\tACPI_CEDT_TYPE_CXIMS = 2,\n\tACPI_CEDT_TYPE_RDPAS = 3,\n\tACPI_CEDT_TYPE_RESERVED = 4,\n};\n\nenum acpi_device_swnode_dev_props {\n\tACPI_DEVICE_SWNODE_DEV_ROTATION = 0,\n\tACPI_DEVICE_SWNODE_DEV_CLOCK_FREQUENCY = 1,\n\tACPI_DEVICE_SWNODE_DEV_LED_MAX_MICROAMP = 2,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_MICROAMP = 3,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_TIMEOUT_US = 4,\n\tACPI_DEVICE_SWNODE_DEV_NUM_OF = 5,\n\tACPI_DEVICE_SWNODE_DEV_NUM_ENTRIES = 6,\n};\n\nenum acpi_device_swnode_ep_props {\n\tACPI_DEVICE_SWNODE_EP_REMOTE_EP = 0,\n\tACPI_DEVICE_SWNODE_EP_BUS_TYPE = 1,\n\tACPI_DEVICE_SWNODE_EP_REG = 2,\n\tACPI_DEVICE_SWNODE_EP_CLOCK_LANES = 3,\n\tACPI_DEVICE_SWNODE_EP_DATA_LANES = 4,\n\tACPI_DEVICE_SWNODE_EP_LANE_POLARITIES = 5,\n\tACPI_DEVICE_SWNODE_EP_LINK_FREQUENCIES = 6,\n\tACPI_DEVICE_SWNODE_EP_NUM_OF = 7,\n\tACPI_DEVICE_SWNODE_EP_NUM_ENTRIES = 8,\n};\n\nenum acpi_device_swnode_port_props {\n\tACPI_DEVICE_SWNODE_PORT_REG = 0,\n\tACPI_DEVICE_SWNODE_PORT_NUM_OF = 1,\n\tACPI_DEVICE_SWNODE_PORT_NUM_ENTRIES = 2,\n};\n\nenum acpi_gpio_ignore_list {\n\tACPI_GPIO_IGNORE_WAKE = 0,\n\tACPI_GPIO_IGNORE_INTERRUPT = 1,\n};\n\nenum acpi_irq_model_id {\n\tACPI_IRQ_MODEL_PIC = 0,\n\tACPI_IRQ_MODEL_IOAPIC = 1,\n\tACPI_IRQ_MODEL_IOSAPIC = 2,\n\tACPI_IRQ_MODEL_PLATFORM = 3,\n\tACPI_IRQ_MODEL_GIC = 4,\n\tACPI_IRQ_MODEL_GIC_V5 = 5,\n\tACPI_IRQ_MODEL_LPIC = 6,\n\tACPI_IRQ_MODEL_RINTC = 7,\n\tACPI_IRQ_MODEL_COUNT = 8,\n};\n\nenum acpi_madt_multiproc_wakeup_version {\n\tACPI_MADT_MP_WAKEUP_VERSION_NONE = 0,\n\tACPI_MADT_MP_WAKEUP_VERSION_V1 = 1,\n\tACPI_MADT_MP_WAKEUP_VERSION_RESERVED = 2,\n};\n\nenum acpi_madt_rintc_version {\n\tACPI_MADT_RINTC_VERSION_NONE = 0,\n\tACPI_MADT_RINTC_VERSION_V1 = 1,\n\tACPI_MADT_RINTC_VERSION_RESERVED = 2,\n};\n\nenum acpi_madt_type {\n\tACPI_MADT_TYPE_LOCAL_APIC = 0,\n\tACPI_MADT_TYPE_IO_APIC = 1,\n\tACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,\n\tACPI_MADT_TYPE_NMI_SOURCE = 3,\n\tACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,\n\tACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,\n\tACPI_MADT_TYPE_IO_SAPIC = 6,\n\tACPI_MADT_TYPE_LOCAL_SAPIC = 7,\n\tACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,\n\tACPI_MADT_TYPE_LOCAL_X2APIC = 9,\n\tACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,\n\tACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,\n\tACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,\n\tACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,\n\tACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,\n\tACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,\n\tACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,\n\tACPI_MADT_TYPE_CORE_PIC = 17,\n\tACPI_MADT_TYPE_LIO_PIC = 18,\n\tACPI_MADT_TYPE_HT_PIC = 19,\n\tACPI_MADT_TYPE_EIO_PIC = 20,\n\tACPI_MADT_TYPE_MSI_PIC = 21,\n\tACPI_MADT_TYPE_BIO_PIC = 22,\n\tACPI_MADT_TYPE_LPC_PIC = 23,\n\tACPI_MADT_TYPE_RINTC = 24,\n\tACPI_MADT_TYPE_IMSIC = 25,\n\tACPI_MADT_TYPE_APLIC = 26,\n\tACPI_MADT_TYPE_PLIC = 27,\n\tACPI_MADT_TYPE_GICV5_IRS = 28,\n\tACPI_MADT_TYPE_GICV5_ITS = 29,\n\tACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,\n\tACPI_MADT_TYPE_RESERVED = 31,\n\tACPI_MADT_TYPE_OEM_RESERVED = 128,\n};\n\nenum acpi_pcct_type {\n\tACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2,\n\tACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3,\n\tACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4,\n\tACPI_PCCT_TYPE_HW_REG_COMM_SUBSPACE = 5,\n\tACPI_PCCT_TYPE_RESERVED = 6,\n};\n\nenum acpi_pptt_type {\n\tACPI_PPTT_TYPE_PROCESSOR = 0,\n\tACPI_PPTT_TYPE_CACHE = 1,\n\tACPI_PPTT_TYPE_ID = 2,\n\tACPI_PPTT_TYPE_RESERVED = 3,\n};\n\nenum acpi_predicate {\n\tall_versions = 0,\n\tless_than_or_equal = 1,\n\tequal = 2,\n\tgreater_than_or_equal = 3,\n};\n\nenum acpi_reconfig_event {\n\tACPI_RECONFIG_DEVICE_ADD = 0,\n\tACPI_RECONFIG_DEVICE_REMOVE = 1,\n};\n\nenum acpi_return_package_types {\n\tACPI_PTYPE1_FIXED = 1,\n\tACPI_PTYPE1_VAR = 2,\n\tACPI_PTYPE1_OPTION = 3,\n\tACPI_PTYPE2 = 4,\n\tACPI_PTYPE2_COUNT = 5,\n\tACPI_PTYPE2_PKG_COUNT = 6,\n\tACPI_PTYPE2_FIXED = 7,\n\tACPI_PTYPE2_MIN = 8,\n\tACPI_PTYPE2_REV_FIXED = 9,\n\tACPI_PTYPE2_FIX_VAR = 10,\n\tACPI_PTYPE2_VAR_VAR = 11,\n\tACPI_PTYPE2_UUID_PAIR = 12,\n\tACPI_PTYPE_CUSTOM = 13,\n};\n\nenum acpi_rhct_node_type {\n\tACPI_RHCT_NODE_TYPE_ISA_STRING = 0,\n\tACPI_RHCT_NODE_TYPE_CMO = 1,\n\tACPI_RHCT_NODE_TYPE_MMU = 2,\n\tACPI_RHCT_NODE_TYPE_RESERVED = 3,\n\tACPI_RHCT_NODE_TYPE_HART_INFO = 65535,\n};\n\nenum acpi_rimt_node_type {\n\tACPI_RIMT_NODE_TYPE_IOMMU = 0,\n\tACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX = 1,\n\tACPI_RIMT_NODE_TYPE_PLAT_DEVICE = 2,\n};\n\nenum acpi_srat_type {\n\tACPI_SRAT_TYPE_CPU_AFFINITY = 0,\n\tACPI_SRAT_TYPE_MEMORY_AFFINITY = 1,\n\tACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2,\n\tACPI_SRAT_TYPE_GICC_AFFINITY = 3,\n\tACPI_SRAT_TYPE_GIC_ITS_AFFINITY = 4,\n\tACPI_SRAT_TYPE_GENERIC_AFFINITY = 5,\n\tACPI_SRAT_TYPE_GENERIC_PORT_AFFINITY = 6,\n\tACPI_SRAT_TYPE_RINTC_AFFINITY = 7,\n\tACPI_SRAT_TYPE_RESERVED = 8,\n};\n\nenum acpi_subtable_type {\n\tACPI_SUBTABLE_COMMON = 0,\n\tACPI_SUBTABLE_HMAT = 1,\n\tACPI_SUBTABLE_PRMT = 2,\n\tACPI_SUBTABLE_CEDT = 3,\n\tCDAT_SUBTABLE = 4,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum addr_type_t {\n\tUNICAST_ADDR = 0,\n\tMULTICAST_ADDR = 1,\n\tANYCAST_ADDR = 2,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum alloc_loc {\n\tALLOC_ERR = 0,\n\tALLOC_BEFORE = 1,\n\tALLOC_MID = 2,\n\tALLOC_AFTER = 3,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nenum ata_quirks {\n\t__ATA_QUIRK_DIAGNOSTIC = 0,\n\t__ATA_QUIRK_NODMA = 1,\n\t__ATA_QUIRK_NONCQ = 2,\n\t__ATA_QUIRK_BROKEN_HPA = 3,\n\t__ATA_QUIRK_DISABLE = 4,\n\t__ATA_QUIRK_HPA_SIZE = 5,\n\t__ATA_QUIRK_IVB = 6,\n\t__ATA_QUIRK_STUCK_ERR = 7,\n\t__ATA_QUIRK_BRIDGE_OK = 8,\n\t__ATA_QUIRK_ATAPI_MOD16_DMA = 9,\n\t__ATA_QUIRK_FIRMWARE_WARN = 10,\n\t__ATA_QUIRK_1_5_GBPS = 11,\n\t__ATA_QUIRK_NOSETXFER = 12,\n\t__ATA_QUIRK_BROKEN_FPDMA_AA = 13,\n\t__ATA_QUIRK_DUMP_ID = 14,\n\t__ATA_QUIRK_MAX_SEC_LBA48 = 15,\n\t__ATA_QUIRK_ATAPI_DMADIR = 16,\n\t__ATA_QUIRK_NO_NCQ_TRIM = 17,\n\t__ATA_QUIRK_NOLPM = 18,\n\t__ATA_QUIRK_WD_BROKEN_LPM = 19,\n\t__ATA_QUIRK_ZERO_AFTER_TRIM = 20,\n\t__ATA_QUIRK_NO_DMA_LOG = 21,\n\t__ATA_QUIRK_NOTRIM = 22,\n\t__ATA_QUIRK_MAX_SEC = 23,\n\t__ATA_QUIRK_MAX_TRIM_128M = 24,\n\t__ATA_QUIRK_NO_NCQ_ON_ATI = 25,\n\t__ATA_QUIRK_NO_LPM_ON_ATI = 26,\n\t__ATA_QUIRK_NO_ID_DEV_LOG = 27,\n\t__ATA_QUIRK_NO_LOG_DIR = 28,\n\t__ATA_QUIRK_NO_FUA = 29,\n\t__ATA_QUIRK_MAX = 30,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum audit_mode {\n\tAUDIT_NORMAL = 0,\n\tAUDIT_QUIET_DENIED = 1,\n\tAUDIT_QUIET = 2,\n\tAUDIT_NOQUIET = 3,\n\tAUDIT_ALL = 4,\n};\n\nenum audit_nfcfgop {\n\tAUDIT_XT_OP_REGISTER = 0,\n\tAUDIT_XT_OP_REPLACE = 1,\n\tAUDIT_XT_OP_UNREGISTER = 2,\n\tAUDIT_NFT_OP_TABLE_REGISTER = 3,\n\tAUDIT_NFT_OP_TABLE_UNREGISTER = 4,\n\tAUDIT_NFT_OP_CHAIN_REGISTER = 5,\n\tAUDIT_NFT_OP_CHAIN_UNREGISTER = 6,\n\tAUDIT_NFT_OP_RULE_REGISTER = 7,\n\tAUDIT_NFT_OP_RULE_UNREGISTER = 8,\n\tAUDIT_NFT_OP_SET_REGISTER = 9,\n\tAUDIT_NFT_OP_SET_UNREGISTER = 10,\n\tAUDIT_NFT_OP_SETELEM_REGISTER = 11,\n\tAUDIT_NFT_OP_SETELEM_UNREGISTER = 12,\n\tAUDIT_NFT_OP_GEN_REGISTER = 13,\n\tAUDIT_NFT_OP_OBJ_REGISTER = 14,\n\tAUDIT_NFT_OP_OBJ_UNREGISTER = 15,\n\tAUDIT_NFT_OP_OBJ_RESET = 16,\n\tAUDIT_NFT_OP_FLOWTABLE_REGISTER = 17,\n\tAUDIT_NFT_OP_FLOWTABLE_UNREGISTER = 18,\n\tAUDIT_NFT_OP_SETELEM_RESET = 19,\n\tAUDIT_NFT_OP_RULE_RESET = 20,\n\tAUDIT_NFT_OP_INVALID = 21,\n};\n\nenum audit_nlgrps {\n\tAUDIT_NLGRP_NONE = 0,\n\tAUDIT_NLGRP_READLOG = 1,\n\t__AUDIT_NLGRP_MAX = 2,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum audit_state {\n\tAUDIT_STATE_DISABLED = 0,\n\tAUDIT_STATE_BUILD = 1,\n\tAUDIT_STATE_RECORD = 2,\n};\n\nenum audit_type {\n\tAUDIT_APPARMOR_AUDIT = 0,\n\tAUDIT_APPARMOR_ALLOWED = 1,\n\tAUDIT_APPARMOR_DENIED = 2,\n\tAUDIT_APPARMOR_HINT = 3,\n\tAUDIT_APPARMOR_STATUS = 4,\n\tAUDIT_APPARMOR_ERROR = 5,\n\tAUDIT_APPARMOR_KILL = 6,\n\tAUDIT_APPARMOR_AUTO = 7,\n};\n\nenum auditsc_class_t {\n\tAUDITSC_NATIVE = 0,\n\tAUDITSC_COMPAT = 1,\n\tAUDITSC_OPEN = 2,\n\tAUDITSC_OPENAT = 3,\n\tAUDITSC_SOCKETCALL = 4,\n\tAUDITSC_EXECVE = 5,\n\tAUDITSC_OPENAT2 = 6,\n\tAUDITSC_NVALS = 7,\n};\n\nenum autofs_notify {\n\tNFY_NONE = 0,\n\tNFY_MOUNT = 1,\n\tNFY_EXPIRE = 2,\n};\n\nenum axp15060_irqs {\n\tAXP15060_IRQ_DIE_TEMP_HIGH_LV1 = 1,\n\tAXP15060_IRQ_DIE_TEMP_HIGH_LV2 = 2,\n\tAXP15060_IRQ_DCDC1_V_LOW = 3,\n\tAXP15060_IRQ_DCDC2_V_LOW = 4,\n\tAXP15060_IRQ_DCDC3_V_LOW = 5,\n\tAXP15060_IRQ_DCDC4_V_LOW = 6,\n\tAXP15060_IRQ_DCDC5_V_LOW = 7,\n\tAXP15060_IRQ_DCDC6_V_LOW = 8,\n\tAXP15060_IRQ_PEK_LONG = 9,\n\tAXP15060_IRQ_PEK_SHORT = 10,\n\tAXP15060_IRQ_GPIO1_INPUT = 11,\n\tAXP15060_IRQ_PEK_FAL_EDGE = 12,\n\tAXP15060_IRQ_PEK_RIS_EDGE = 13,\n\tAXP15060_IRQ_GPIO2_INPUT = 14,\n};\n\nenum axp192_irqs {\n\tAXP192_IRQ_ACIN_OVER_V = 1,\n\tAXP192_IRQ_ACIN_PLUGIN = 2,\n\tAXP192_IRQ_ACIN_REMOVAL = 3,\n\tAXP192_IRQ_VBUS_OVER_V = 4,\n\tAXP192_IRQ_VBUS_PLUGIN = 5,\n\tAXP192_IRQ_VBUS_REMOVAL = 6,\n\tAXP192_IRQ_VBUS_V_LOW = 7,\n\tAXP192_IRQ_BATT_PLUGIN = 8,\n\tAXP192_IRQ_BATT_REMOVAL = 9,\n\tAXP192_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP192_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP192_IRQ_CHARG = 12,\n\tAXP192_IRQ_CHARG_DONE = 13,\n\tAXP192_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP192_IRQ_BATT_TEMP_LOW = 15,\n\tAXP192_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP192_IRQ_CHARG_I_LOW = 17,\n\tAXP192_IRQ_DCDC1_V_LONG = 18,\n\tAXP192_IRQ_DCDC2_V_LONG = 19,\n\tAXP192_IRQ_DCDC3_V_LONG = 20,\n\tAXP192_IRQ_PEK_SHORT = 22,\n\tAXP192_IRQ_PEK_LONG = 23,\n\tAXP192_IRQ_N_OE_PWR_ON = 24,\n\tAXP192_IRQ_N_OE_PWR_OFF = 25,\n\tAXP192_IRQ_VBUS_VALID = 26,\n\tAXP192_IRQ_VBUS_NOT_VALID = 27,\n\tAXP192_IRQ_VBUS_SESS_VALID = 28,\n\tAXP192_IRQ_VBUS_SESS_END = 29,\n\tAXP192_IRQ_LOW_PWR_LVL = 31,\n\tAXP192_IRQ_TIMER = 32,\n\tAXP192_IRQ_GPIO2_INPUT = 37,\n\tAXP192_IRQ_GPIO1_INPUT = 38,\n\tAXP192_IRQ_GPIO0_INPUT = 39,\n};\n\nenum axp20x_variants {\n\tAXP152_ID = 0,\n\tAXP192_ID = 1,\n\tAXP202_ID = 2,\n\tAXP209_ID = 3,\n\tAXP221_ID = 4,\n\tAXP223_ID = 5,\n\tAXP288_ID = 6,\n\tAXP313A_ID = 7,\n\tAXP323_ID = 8,\n\tAXP717_ID = 9,\n\tAXP803_ID = 10,\n\tAXP806_ID = 11,\n\tAXP809_ID = 12,\n\tAXP813_ID = 13,\n\tAXP15060_ID = 14,\n\tNR_AXP20X_VARIANTS = 15,\n};\n\nenum axp22x_irqs {\n\tAXP22X_IRQ_ACIN_OVER_V = 1,\n\tAXP22X_IRQ_ACIN_PLUGIN = 2,\n\tAXP22X_IRQ_ACIN_REMOVAL = 3,\n\tAXP22X_IRQ_VBUS_OVER_V = 4,\n\tAXP22X_IRQ_VBUS_PLUGIN = 5,\n\tAXP22X_IRQ_VBUS_REMOVAL = 6,\n\tAXP22X_IRQ_VBUS_V_LOW = 7,\n\tAXP22X_IRQ_BATT_PLUGIN = 8,\n\tAXP22X_IRQ_BATT_REMOVAL = 9,\n\tAXP22X_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP22X_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP22X_IRQ_CHARG = 12,\n\tAXP22X_IRQ_CHARG_DONE = 13,\n\tAXP22X_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP22X_IRQ_BATT_TEMP_LOW = 15,\n\tAXP22X_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP22X_IRQ_PEK_SHORT = 17,\n\tAXP22X_IRQ_PEK_LONG = 18,\n\tAXP22X_IRQ_LOW_PWR_LVL1 = 19,\n\tAXP22X_IRQ_LOW_PWR_LVL2 = 20,\n\tAXP22X_IRQ_TIMER = 21,\n\tAXP22X_IRQ_PEK_FAL_EDGE = 22,\n\tAXP22X_IRQ_PEK_RIS_EDGE = 23,\n\tAXP22X_IRQ_GPIO1_INPUT = 24,\n\tAXP22X_IRQ_GPIO0_INPUT = 25,\n};\n\nenum axp288_irqs {\n\tAXP288_IRQ_VBUS_FALL = 2,\n\tAXP288_IRQ_VBUS_RISE = 3,\n\tAXP288_IRQ_OV = 4,\n\tAXP288_IRQ_FALLING_ALT = 5,\n\tAXP288_IRQ_RISING_ALT = 6,\n\tAXP288_IRQ_OV_ALT = 7,\n\tAXP288_IRQ_DONE = 10,\n\tAXP288_IRQ_CHARGING = 11,\n\tAXP288_IRQ_SAFE_QUIT = 12,\n\tAXP288_IRQ_SAFE_ENTER = 13,\n\tAXP288_IRQ_ABSENT = 14,\n\tAXP288_IRQ_APPEND = 15,\n\tAXP288_IRQ_QWBTU = 16,\n\tAXP288_IRQ_WBTU = 17,\n\tAXP288_IRQ_QWBTO = 18,\n\tAXP288_IRQ_WBTO = 19,\n\tAXP288_IRQ_QCBTU = 20,\n\tAXP288_IRQ_CBTU = 21,\n\tAXP288_IRQ_QCBTO = 22,\n\tAXP288_IRQ_CBTO = 23,\n\tAXP288_IRQ_WL2 = 24,\n\tAXP288_IRQ_WL1 = 25,\n\tAXP288_IRQ_GPADC = 26,\n\tAXP288_IRQ_OT = 31,\n\tAXP288_IRQ_GPIO0 = 32,\n\tAXP288_IRQ_GPIO1 = 33,\n\tAXP288_IRQ_POKO = 34,\n\tAXP288_IRQ_POKL = 35,\n\tAXP288_IRQ_POKS = 36,\n\tAXP288_IRQ_POKN = 37,\n\tAXP288_IRQ_POKP = 38,\n\tAXP288_IRQ_TIMER = 39,\n\tAXP288_IRQ_MV_CHNG = 40,\n\tAXP288_IRQ_BC_USB_CHNG = 41,\n};\n\nenum axp313a_irqs {\n\tAXP313A_IRQ_DIE_TEMP_HIGH = 0,\n\tAXP313A_IRQ_DCDC2_V_LOW = 2,\n\tAXP313A_IRQ_DCDC3_V_LOW = 3,\n\tAXP313A_IRQ_PEK_LONG = 4,\n\tAXP313A_IRQ_PEK_SHORT = 5,\n\tAXP313A_IRQ_PEK_FAL_EDGE = 6,\n\tAXP313A_IRQ_PEK_RIS_EDGE = 7,\n};\n\nenum axp717_irqs {\n\tAXP717_IRQ_VBUS_FAULT = 0,\n\tAXP717_IRQ_VBUS_OVER_V = 1,\n\tAXP717_IRQ_BOOST_OVER_V = 2,\n\tAXP717_IRQ_GAUGE_NEW_SOC = 4,\n\tAXP717_IRQ_SOC_DROP_LVL1 = 6,\n\tAXP717_IRQ_SOC_DROP_LVL2 = 7,\n\tAXP717_IRQ_PEK_RIS_EDGE = 8,\n\tAXP717_IRQ_PEK_FAL_EDGE = 9,\n\tAXP717_IRQ_PEK_LONG = 10,\n\tAXP717_IRQ_PEK_SHORT = 11,\n\tAXP717_IRQ_BATT_REMOVAL = 12,\n\tAXP717_IRQ_BATT_PLUGIN = 13,\n\tAXP717_IRQ_VBUS_REMOVAL = 14,\n\tAXP717_IRQ_VBUS_PLUGIN = 15,\n\tAXP717_IRQ_BATT_OVER_V = 16,\n\tAXP717_IRQ_CHARG_TIMER = 17,\n\tAXP717_IRQ_DIE_TEMP_HIGH = 18,\n\tAXP717_IRQ_CHARG = 19,\n\tAXP717_IRQ_CHARG_DONE = 20,\n\tAXP717_IRQ_BATT_OVER_CURR = 21,\n\tAXP717_IRQ_LDO_OVER_CURR = 22,\n\tAXP717_IRQ_WDOG_EXPIRE = 23,\n\tAXP717_IRQ_BATT_ACT_TEMP_LOW = 24,\n\tAXP717_IRQ_BATT_ACT_TEMP_HIGH = 25,\n\tAXP717_IRQ_BATT_CHG_TEMP_LOW = 26,\n\tAXP717_IRQ_BATT_CHG_TEMP_HIGH = 27,\n\tAXP717_IRQ_BATT_QUIT_TEMP_HIGH = 28,\n\tAXP717_IRQ_BC_USB_CHNG = 30,\n\tAXP717_IRQ_BC_USB_DONE = 31,\n\tAXP717_IRQ_TYPEC_PLUGIN = 37,\n\tAXP717_IRQ_TYPEC_REMOVE = 38,\n};\n\nenum axp803_irqs {\n\tAXP803_IRQ_ACIN_OVER_V = 1,\n\tAXP803_IRQ_ACIN_PLUGIN = 2,\n\tAXP803_IRQ_ACIN_REMOVAL = 3,\n\tAXP803_IRQ_VBUS_OVER_V = 4,\n\tAXP803_IRQ_VBUS_PLUGIN = 5,\n\tAXP803_IRQ_VBUS_REMOVAL = 6,\n\tAXP803_IRQ_BATT_PLUGIN = 7,\n\tAXP803_IRQ_BATT_REMOVAL = 8,\n\tAXP803_IRQ_BATT_ENT_ACT_MODE = 9,\n\tAXP803_IRQ_BATT_EXIT_ACT_MODE = 10,\n\tAXP803_IRQ_CHARG = 11,\n\tAXP803_IRQ_CHARG_DONE = 12,\n\tAXP803_IRQ_BATT_CHG_TEMP_HIGH = 13,\n\tAXP803_IRQ_BATT_CHG_TEMP_HIGH_END = 14,\n\tAXP803_IRQ_BATT_CHG_TEMP_LOW = 15,\n\tAXP803_IRQ_BATT_CHG_TEMP_LOW_END = 16,\n\tAXP803_IRQ_BATT_ACT_TEMP_HIGH = 17,\n\tAXP803_IRQ_BATT_ACT_TEMP_HIGH_END = 18,\n\tAXP803_IRQ_BATT_ACT_TEMP_LOW = 19,\n\tAXP803_IRQ_BATT_ACT_TEMP_LOW_END = 20,\n\tAXP803_IRQ_DIE_TEMP_HIGH = 21,\n\tAXP803_IRQ_GPADC = 22,\n\tAXP803_IRQ_LOW_PWR_LVL1 = 23,\n\tAXP803_IRQ_LOW_PWR_LVL2 = 24,\n\tAXP803_IRQ_TIMER = 25,\n\tAXP803_IRQ_PEK_FAL_EDGE = 26,\n\tAXP803_IRQ_PEK_RIS_EDGE = 27,\n\tAXP803_IRQ_PEK_SHORT = 28,\n\tAXP803_IRQ_PEK_LONG = 29,\n\tAXP803_IRQ_PEK_OVER_OFF = 30,\n\tAXP803_IRQ_GPIO1_INPUT = 31,\n\tAXP803_IRQ_GPIO0_INPUT = 32,\n\tAXP803_IRQ_BC_USB_CHNG = 33,\n\tAXP803_IRQ_MV_CHNG = 34,\n};\n\nenum axp806_irqs {\n\tAXP806_IRQ_DIE_TEMP_HIGH_LV1 = 0,\n\tAXP806_IRQ_DIE_TEMP_HIGH_LV2 = 1,\n\tAXP806_IRQ_DCDCA_V_LOW = 2,\n\tAXP806_IRQ_DCDCB_V_LOW = 3,\n\tAXP806_IRQ_DCDCC_V_LOW = 4,\n\tAXP806_IRQ_DCDCD_V_LOW = 5,\n\tAXP806_IRQ_DCDCE_V_LOW = 6,\n\tAXP806_IRQ_POK_LONG = 7,\n\tAXP806_IRQ_POK_SHORT = 8,\n\tAXP806_IRQ_WAKEUP = 9,\n\tAXP806_IRQ_POK_FALL = 10,\n\tAXP806_IRQ_POK_RISE = 11,\n};\n\nenum axp809_irqs {\n\tAXP809_IRQ_ACIN_OVER_V = 1,\n\tAXP809_IRQ_ACIN_PLUGIN = 2,\n\tAXP809_IRQ_ACIN_REMOVAL = 3,\n\tAXP809_IRQ_VBUS_OVER_V = 4,\n\tAXP809_IRQ_VBUS_PLUGIN = 5,\n\tAXP809_IRQ_VBUS_REMOVAL = 6,\n\tAXP809_IRQ_VBUS_V_LOW = 7,\n\tAXP809_IRQ_BATT_PLUGIN = 8,\n\tAXP809_IRQ_BATT_REMOVAL = 9,\n\tAXP809_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP809_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP809_IRQ_CHARG = 12,\n\tAXP809_IRQ_CHARG_DONE = 13,\n\tAXP809_IRQ_BATT_CHG_TEMP_HIGH = 14,\n\tAXP809_IRQ_BATT_CHG_TEMP_HIGH_END = 15,\n\tAXP809_IRQ_BATT_CHG_TEMP_LOW = 16,\n\tAXP809_IRQ_BATT_CHG_TEMP_LOW_END = 17,\n\tAXP809_IRQ_BATT_ACT_TEMP_HIGH = 18,\n\tAXP809_IRQ_BATT_ACT_TEMP_HIGH_END = 19,\n\tAXP809_IRQ_BATT_ACT_TEMP_LOW = 20,\n\tAXP809_IRQ_BATT_ACT_TEMP_LOW_END = 21,\n\tAXP809_IRQ_DIE_TEMP_HIGH = 22,\n\tAXP809_IRQ_LOW_PWR_LVL1 = 23,\n\tAXP809_IRQ_LOW_PWR_LVL2 = 24,\n\tAXP809_IRQ_TIMER = 25,\n\tAXP809_IRQ_PEK_FAL_EDGE = 26,\n\tAXP809_IRQ_PEK_RIS_EDGE = 27,\n\tAXP809_IRQ_PEK_SHORT = 28,\n\tAXP809_IRQ_PEK_LONG = 29,\n\tAXP809_IRQ_PEK_OVER_OFF = 30,\n\tAXP809_IRQ_GPIO1_INPUT = 31,\n\tAXP809_IRQ_GPIO0_INPUT = 32,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bfqq_expiration {\n\tBFQQE_TOO_IDLE = 0,\n\tBFQQE_BUDGET_TIMEOUT = 1,\n\tBFQQE_BUDGET_EXHAUSTED = 2,\n\tBFQQE_NO_MORE_REQUESTS = 3,\n\tBFQQE_PREEMPTED = 4,\n};\n\nenum bfqq_state_flags {\n\tBFQQF_just_created = 0,\n\tBFQQF_busy = 1,\n\tBFQQF_wait_request = 2,\n\tBFQQF_non_blocking_wait_rq = 3,\n\tBFQQF_fifo_expire = 4,\n\tBFQQF_has_short_ttime = 5,\n\tBFQQF_sync = 6,\n\tBFQQF_IO_bound = 7,\n\tBFQQF_in_large_burst = 8,\n\tBFQQF_softrt_update = 9,\n\tBFQQF_coop = 10,\n\tBFQQF_split_coop = 11,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blkg_iostat_type {\n\tBLKG_IOSTAT_READ = 0,\n\tBLKG_IOSTAT_WRITE = 1,\n\tBLKG_IOSTAT_DISCARD = 2,\n\tBLKG_IOSTAT_NR = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_43bit_dma = 1,\n\tboard_ahci_ign_iferr = 2,\n\tboard_ahci_no_debounce_delay = 3,\n\tboard_ahci_no_msi = 4,\n\tboard_ahci_pcs_quirk = 5,\n\tboard_ahci_pcs_quirk_no_devslp = 6,\n\tboard_ahci_pcs_quirk_no_sntf = 7,\n\tboard_ahci_yes_fbs = 8,\n\tboard_ahci_yes_fbs_atapi_dma = 9,\n\tboard_ahci_al = 10,\n\tboard_ahci_avn = 11,\n\tboard_ahci_mcp65 = 12,\n\tboard_ahci_mcp77 = 13,\n\tboard_ahci_mcp89 = 14,\n\tboard_ahci_mv = 15,\n\tboard_ahci_sb600 = 16,\n\tboard_ahci_sb700 = 17,\n\tboard_ahci_vt8251 = 18,\n\tboard_ahci_mcp_linux = 12,\n\tboard_ahci_mcp67 = 12,\n\tboard_ahci_mcp73 = 12,\n\tboard_ahci_mcp79 = 13,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_perf_event_type {\n\tBPF_PERF_EVENT_UNSPEC = 0,\n\tBPF_PERF_EVENT_UPROBE = 1,\n\tBPF_PERF_EVENT_URETPROBE = 2,\n\tBPF_PERF_EVENT_KPROBE = 3,\n\tBPF_PERF_EVENT_KRETPROBE = 4,\n\tBPF_PERF_EVENT_TRACEPOINT = 5,\n\tBPF_PERF_EVENT_EVENT = 6,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum btt_init_state {\n\tINIT_UNCHECKED = 0,\n\tINIT_NOTFOUND = 1,\n\tINIT_READY = 2,\n};\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum cc_attr {\n\tCC_ATTR_MEM_ENCRYPT = 0,\n\tCC_ATTR_HOST_MEM_ENCRYPT = 1,\n\tCC_ATTR_GUEST_MEM_ENCRYPT = 2,\n\tCC_ATTR_GUEST_STATE_ENCRYPT = 3,\n\tCC_ATTR_GUEST_UNROLL_STRING_IO = 4,\n\tCC_ATTR_GUEST_SEV_SNP = 5,\n\tCC_ATTR_GUEST_SNP_SECURE_TSC = 6,\n\tCC_ATTR_HOST_SEV_SNP = 7,\n\tCC_ATTR_SNP_SECURE_AVIC = 8,\n};\n\nenum cdrom_print_option {\n\tCTL_NAME = 0,\n\tCTL_SPEED = 1,\n\tCTL_SLOTS = 2,\n\tCTL_CAPABILITY = 3,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_bpf_attach_type {\n\tCGROUP_BPF_ATTACH_TYPE_INVALID = -1,\n\tCGROUP_INET_INGRESS = 0,\n\tCGROUP_INET_EGRESS = 1,\n\tCGROUP_INET_SOCK_CREATE = 2,\n\tCGROUP_SOCK_OPS = 3,\n\tCGROUP_DEVICE = 4,\n\tCGROUP_INET4_BIND = 5,\n\tCGROUP_INET6_BIND = 6,\n\tCGROUP_INET4_CONNECT = 7,\n\tCGROUP_INET6_CONNECT = 8,\n\tCGROUP_UNIX_CONNECT = 9,\n\tCGROUP_INET4_POST_BIND = 10,\n\tCGROUP_INET6_POST_BIND = 11,\n\tCGROUP_UDP4_SENDMSG = 12,\n\tCGROUP_UDP6_SENDMSG = 13,\n\tCGROUP_UNIX_SENDMSG = 14,\n\tCGROUP_SYSCTL = 15,\n\tCGROUP_UDP4_RECVMSG = 16,\n\tCGROUP_UDP6_RECVMSG = 17,\n\tCGROUP_UNIX_RECVMSG = 18,\n\tCGROUP_GETSOCKOPT = 19,\n\tCGROUP_SETSOCKOPT = 20,\n\tCGROUP_INET4_GETPEERNAME = 21,\n\tCGROUP_INET6_GETPEERNAME = 22,\n\tCGROUP_UNIX_GETPEERNAME = 23,\n\tCGROUP_INET4_GETSOCKNAME = 24,\n\tCGROUP_INET6_GETSOCKNAME = 25,\n\tCGROUP_UNIX_GETSOCKNAME = 26,\n\tCGROUP_INET_SOCK_RELEASE = 27,\n\tCGROUP_LSM_START = 28,\n\tCGROUP_LSM_END = 27,\n\tMAX_CGROUP_BPF_ATTACH_TYPE = 28,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_COUNT = 0,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tio_cgrp_id = 3,\n\tmemory_cgrp_id = 4,\n\tdevices_cgrp_id = 5,\n\tfreezer_cgrp_id = 6,\n\tnet_cls_cgrp_id = 7,\n\tperf_event_cgrp_id = 8,\n\tnet_prio_cgrp_id = 9,\n\thugetlb_cgrp_id = 10,\n\tpids_cgrp_id = 11,\n\tCGROUP_SUBSYS_COUNT = 12,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum cleanup_prefix_rt_t {\n\tCLEANUP_PREFIX_RT_NOP = 0,\n\tCLEANUP_PREFIX_RT_DEL = 1,\n\tCLEANUP_PREFIX_RT_EXPIRE = 2,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cppc_regs {\n\tHIGHEST_PERF = 0,\n\tNOMINAL_PERF = 1,\n\tLOW_NON_LINEAR_PERF = 2,\n\tLOWEST_PERF = 3,\n\tGUARANTEED_PERF = 4,\n\tDESIRED_PERF = 5,\n\tMIN_PERF = 6,\n\tMAX_PERF = 7,\n\tPERF_REDUC_TOLERANCE = 8,\n\tTIME_WINDOW = 9,\n\tCTR_WRAP_TIME = 10,\n\tREFERENCE_CTR = 11,\n\tDELIVERED_CTR = 12,\n\tPERF_LIMITED = 13,\n\tENABLE = 14,\n\tAUTO_SEL_ENABLE = 15,\n\tAUTO_ACT_WINDOW = 16,\n\tENERGY_PERF = 17,\n\tREFERENCE_PERF = 18,\n\tLOWEST_FREQ = 19,\n\tNOMINAL_FREQ = 20,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_pm_event {\n\tCPU_PM_ENTER = 0,\n\tCPU_PM_ENTER_FAILED = 1,\n\tCPU_PM_EXIT = 2,\n\tCPU_CLUSTER_PM_ENTER = 3,\n\tCPU_CLUSTER_PM_ENTER_FAILED = 4,\n\tCPU_CLUSTER_PM_EXIT = 5,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tNR_STATS = 10,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum createmode4 {\n\tNFS4_CREATE_UNCHECKED = 0,\n\tNFS4_CREATE_GUARDED = 1,\n\tNFS4_CREATE_EXCLUSIVE = 2,\n\tNFS4_CREATE_EXCLUSIVE4_1 = 3,\n};\n\nenum criteria {\n\tCR_POWER2_ALIGNED = 0,\n\tCR_GOAL_LEN_FAST = 1,\n\tCR_BEST_AVAIL_LEN = 2,\n\tCR_GOAL_LEN_SLOW = 3,\n\tCR_ANY_FREE = 4,\n\tEXT4_MB_NUM_CRS = 5,\n};\n\nenum csr_target {\n\tMACRO_CTRL = 7,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum cti_port_type {\n\tCTI_PORT_TYPE_NONE = 0,\n\tCTI_PORT_TYPE_RS232 = 1,\n\tCTI_PORT_TYPE_RS422_485 = 2,\n\tCTI_PORT_TYPE_RS232_422_485_HW = 3,\n\tCTI_PORT_TYPE_RS232_422_485_SW = 4,\n\tCTI_PORT_TYPE_RS232_422_485_4B = 5,\n\tCTI_PORT_TYPE_RS232_422_485_2B = 6,\n\tCTI_PORT_TYPE_MAX = 7,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum cv1800_pin_io_type {\n\tIO_TYPE_1V8_ONLY = 0,\n\tIO_TYPE_1V8_OR_3V3 = 1,\n\tIO_TYPE_AUDIO = 2,\n\tIO_TYPE_ETH = 3,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum data_content4 {\n\tNFS4_CONTENT_DATA = 0,\n\tNFS4_CONTENT_HOLE = 1,\n};\n\nenum dax_access_mode {\n\tDAX_ACCESS = 0,\n\tDAX_RECOVERY_WRITE = 1,\n};\n\nenum dax_device_flags {\n\tDAXDEV_ALIVE = 0,\n\tDAXDEV_WRITE_CACHE = 1,\n\tDAXDEV_SYNC = 2,\n\tDAXDEV_NOCACHE = 3,\n\tDAXDEV_NOMC = 4,\n};\n\nenum dax_driver_type {\n\tDAXDRV_KMEM_TYPE = 0,\n\tDAXDRV_DEVICE_TYPE = 1,\n};\n\nenum dbc_state {\n\tDS_DISABLED = 0,\n\tDS_INITIALIZED = 1,\n\tDS_ENABLED = 2,\n\tDS_CONNECTED = 3,\n\tDS_CONFIGURED = 4,\n\tDS_MAX = 5,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum depot_counter_id {\n\tDEPOT_COUNTER_REFD_ALLOCS = 0,\n\tDEPOT_COUNTER_REFD_FREES = 1,\n\tDEPOT_COUNTER_REFD_INUSE = 2,\n\tDEPOT_COUNTER_FREELIST_SIZE = 3,\n\tDEPOT_COUNTER_PERSIST_COUNT = 4,\n\tDEPOT_COUNTER_PERSIST_BYTES = 5,\n\tDEPOT_COUNTER_COUNT = 6,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_pm_opp_event {\n\tOPP_EVENT_ADD = 0,\n\tOPP_EVENT_REMOVE = 1,\n\tOPP_EVENT_ENABLE = 2,\n\tOPP_EVENT_DISABLE = 3,\n\tOPP_EVENT_ADJUST_VOLTAGE = 4,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum devcg_behavior {\n\tDEVCG_DEFAULT_NONE = 0,\n\tDEVCG_DEFAULT_ALLOW = 1,\n\tDEVCG_DEFAULT_DENY = 2,\n};\n\nenum devfreq_timer {\n\tDEVFREQ_TIMER_DEFERRABLE = 0,\n\tDEVFREQ_TIMER_DELAYED = 1,\n\tDEVFREQ_TIMER_NUM = 2,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_attr {\n\tDEVLINK_ATTR_UNSPEC = 0,\n\tDEVLINK_ATTR_BUS_NAME = 1,\n\tDEVLINK_ATTR_DEV_NAME = 2,\n\tDEVLINK_ATTR_PORT_INDEX = 3,\n\tDEVLINK_ATTR_PORT_TYPE = 4,\n\tDEVLINK_ATTR_PORT_DESIRED_TYPE = 5,\n\tDEVLINK_ATTR_PORT_NETDEV_IFINDEX = 6,\n\tDEVLINK_ATTR_PORT_NETDEV_NAME = 7,\n\tDEVLINK_ATTR_PORT_IBDEV_NAME = 8,\n\tDEVLINK_ATTR_PORT_SPLIT_COUNT = 9,\n\tDEVLINK_ATTR_PORT_SPLIT_GROUP = 10,\n\tDEVLINK_ATTR_SB_INDEX = 11,\n\tDEVLINK_ATTR_SB_SIZE = 12,\n\tDEVLINK_ATTR_SB_INGRESS_POOL_COUNT = 13,\n\tDEVLINK_ATTR_SB_EGRESS_POOL_COUNT = 14,\n\tDEVLINK_ATTR_SB_INGRESS_TC_COUNT = 15,\n\tDEVLINK_ATTR_SB_EGRESS_TC_COUNT = 16,\n\tDEVLINK_ATTR_SB_POOL_INDEX = 17,\n\tDEVLINK_ATTR_SB_POOL_TYPE = 18,\n\tDEVLINK_ATTR_SB_POOL_SIZE = 19,\n\tDEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE = 20,\n\tDEVLINK_ATTR_SB_THRESHOLD = 21,\n\tDEVLINK_ATTR_SB_TC_INDEX = 22,\n\tDEVLINK_ATTR_SB_OCC_CUR = 23,\n\tDEVLINK_ATTR_SB_OCC_MAX = 24,\n\tDEVLINK_ATTR_ESWITCH_MODE = 25,\n\tDEVLINK_ATTR_ESWITCH_INLINE_MODE = 26,\n\tDEVLINK_ATTR_DPIPE_TABLES = 27,\n\tDEVLINK_ATTR_DPIPE_TABLE = 28,\n\tDEVLINK_ATTR_DPIPE_TABLE_NAME = 29,\n\tDEVLINK_ATTR_DPIPE_TABLE_SIZE = 30,\n\tDEVLINK_ATTR_DPIPE_TABLE_MATCHES = 31,\n\tDEVLINK_ATTR_DPIPE_TABLE_ACTIONS = 32,\n\tDEVLINK_ATTR_DPIPE_TABLE_COUNTERS_ENABLED = 33,\n\tDEVLINK_ATTR_DPIPE_ENTRIES = 34,\n\tDEVLINK_ATTR_DPIPE_ENTRY = 35,\n\tDEVLINK_ATTR_DPIPE_ENTRY_INDEX = 36,\n\tDEVLINK_ATTR_DPIPE_ENTRY_MATCH_VALUES = 37,\n\tDEVLINK_ATTR_DPIPE_ENTRY_ACTION_VALUES = 38,\n\tDEVLINK_ATTR_DPIPE_ENTRY_COUNTER = 39,\n\tDEVLINK_ATTR_DPIPE_MATCH = 40,\n\tDEVLINK_ATTR_DPIPE_MATCH_VALUE = 41,\n\tDEVLINK_ATTR_DPIPE_MATCH_TYPE = 42,\n\tDEVLINK_ATTR_DPIPE_ACTION = 43,\n\tDEVLINK_ATTR_DPIPE_ACTION_VALUE = 44,\n\tDEVLINK_ATTR_DPIPE_ACTION_TYPE = 45,\n\tDEVLINK_ATTR_DPIPE_VALUE = 46,\n\tDEVLINK_ATTR_DPIPE_VALUE_MASK = 47,\n\tDEVLINK_ATTR_DPIPE_VALUE_MAPPING = 48,\n\tDEVLINK_ATTR_DPIPE_HEADERS = 49,\n\tDEVLINK_ATTR_DPIPE_HEADER = 50,\n\tDEVLINK_ATTR_DPIPE_HEADER_NAME = 51,\n\tDEVLINK_ATTR_DPIPE_HEADER_ID = 52,\n\tDEVLINK_ATTR_DPIPE_HEADER_FIELDS = 53,\n\tDEVLINK_ATTR_DPIPE_HEADER_GLOBAL = 54,\n\tDEVLINK_ATTR_DPIPE_HEADER_INDEX = 55,\n\tDEVLINK_ATTR_DPIPE_FIELD = 56,\n\tDEVLINK_ATTR_DPIPE_FIELD_NAME = 57,\n\tDEVLINK_ATTR_DPIPE_FIELD_ID = 58,\n\tDEVLINK_ATTR_DPIPE_FIELD_BITWIDTH = 59,\n\tDEVLINK_ATTR_DPIPE_FIELD_MAPPING_TYPE = 60,\n\tDEVLINK_ATTR_PAD = 61,\n\tDEVLINK_ATTR_ESWITCH_ENCAP_MODE = 62,\n\tDEVLINK_ATTR_RESOURCE_LIST = 63,\n\tDEVLINK_ATTR_RESOURCE = 64,\n\tDEVLINK_ATTR_RESOURCE_NAME = 65,\n\tDEVLINK_ATTR_RESOURCE_ID = 66,\n\tDEVLINK_ATTR_RESOURCE_SIZE = 67,\n\tDEVLINK_ATTR_RESOURCE_SIZE_NEW = 68,\n\tDEVLINK_ATTR_RESOURCE_SIZE_VALID = 69,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MIN = 70,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MAX = 71,\n\tDEVLINK_ATTR_RESOURCE_SIZE_GRAN = 72,\n\tDEVLINK_ATTR_RESOURCE_UNIT = 73,\n\tDEVLINK_ATTR_RESOURCE_OCC = 74,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID = 75,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS = 76,\n\tDEVLINK_ATTR_PORT_FLAVOUR = 77,\n\tDEVLINK_ATTR_PORT_NUMBER = 78,\n\tDEVLINK_ATTR_PORT_SPLIT_SUBPORT_NUMBER = 79,\n\tDEVLINK_ATTR_PARAM = 80,\n\tDEVLINK_ATTR_PARAM_NAME = 81,\n\tDEVLINK_ATTR_PARAM_GENERIC = 82,\n\tDEVLINK_ATTR_PARAM_TYPE = 83,\n\tDEVLINK_ATTR_PARAM_VALUES_LIST = 84,\n\tDEVLINK_ATTR_PARAM_VALUE = 85,\n\tDEVLINK_ATTR_PARAM_VALUE_DATA = 86,\n\tDEVLINK_ATTR_PARAM_VALUE_CMODE = 87,\n\tDEVLINK_ATTR_REGION_NAME = 88,\n\tDEVLINK_ATTR_REGION_SIZE = 89,\n\tDEVLINK_ATTR_REGION_SNAPSHOTS = 90,\n\tDEVLINK_ATTR_REGION_SNAPSHOT = 91,\n\tDEVLINK_ATTR_REGION_SNAPSHOT_ID = 92,\n\tDEVLINK_ATTR_REGION_CHUNKS = 93,\n\tDEVLINK_ATTR_REGION_CHUNK = 94,\n\tDEVLINK_ATTR_REGION_CHUNK_DATA = 95,\n\tDEVLINK_ATTR_REGION_CHUNK_ADDR = 96,\n\tDEVLINK_ATTR_REGION_CHUNK_LEN = 97,\n\tDEVLINK_ATTR_INFO_DRIVER_NAME = 98,\n\tDEVLINK_ATTR_INFO_SERIAL_NUMBER = 99,\n\tDEVLINK_ATTR_INFO_VERSION_FIXED = 100,\n\tDEVLINK_ATTR_INFO_VERSION_RUNNING = 101,\n\tDEVLINK_ATTR_INFO_VERSION_STORED = 102,\n\tDEVLINK_ATTR_INFO_VERSION_NAME = 103,\n\tDEVLINK_ATTR_INFO_VERSION_VALUE = 104,\n\tDEVLINK_ATTR_SB_POOL_CELL_SIZE = 105,\n\tDEVLINK_ATTR_FMSG = 106,\n\tDEVLINK_ATTR_FMSG_OBJ_NEST_START = 107,\n\tDEVLINK_ATTR_FMSG_PAIR_NEST_START = 108,\n\tDEVLINK_ATTR_FMSG_ARR_NEST_START = 109,\n\tDEVLINK_ATTR_FMSG_NEST_END = 110,\n\tDEVLINK_ATTR_FMSG_OBJ_NAME = 111,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_TYPE = 112,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_DATA = 113,\n\tDEVLINK_ATTR_HEALTH_REPORTER = 114,\n\tDEVLINK_ATTR_HEALTH_REPORTER_NAME = 115,\n\tDEVLINK_ATTR_HEALTH_REPORTER_STATE = 116,\n\tDEVLINK_ATTR_HEALTH_REPORTER_ERR_COUNT = 117,\n\tDEVLINK_ATTR_HEALTH_REPORTER_RECOVER_COUNT = 118,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS = 119,\n\tDEVLINK_ATTR_HEALTH_REPORTER_GRACEFUL_PERIOD = 120,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_RECOVER = 121,\n\tDEVLINK_ATTR_FLASH_UPDATE_FILE_NAME = 122,\n\tDEVLINK_ATTR_FLASH_UPDATE_COMPONENT = 123,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_MSG = 124,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_DONE = 125,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TOTAL = 126,\n\tDEVLINK_ATTR_PORT_PCI_PF_NUMBER = 127,\n\tDEVLINK_ATTR_PORT_PCI_VF_NUMBER = 128,\n\tDEVLINK_ATTR_STATS = 129,\n\tDEVLINK_ATTR_TRAP_NAME = 130,\n\tDEVLINK_ATTR_TRAP_ACTION = 131,\n\tDEVLINK_ATTR_TRAP_TYPE = 132,\n\tDEVLINK_ATTR_TRAP_GENERIC = 133,\n\tDEVLINK_ATTR_TRAP_METADATA = 134,\n\tDEVLINK_ATTR_TRAP_GROUP_NAME = 135,\n\tDEVLINK_ATTR_RELOAD_FAILED = 136,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS_NS = 137,\n\tDEVLINK_ATTR_NETNS_FD = 138,\n\tDEVLINK_ATTR_NETNS_PID = 139,\n\tDEVLINK_ATTR_NETNS_ID = 140,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_DUMP = 141,\n\tDEVLINK_ATTR_TRAP_POLICER_ID = 142,\n\tDEVLINK_ATTR_TRAP_POLICER_RATE = 143,\n\tDEVLINK_ATTR_TRAP_POLICER_BURST = 144,\n\tDEVLINK_ATTR_PORT_FUNCTION = 145,\n\tDEVLINK_ATTR_INFO_BOARD_SERIAL_NUMBER = 146,\n\tDEVLINK_ATTR_PORT_LANES = 147,\n\tDEVLINK_ATTR_PORT_SPLITTABLE = 148,\n\tDEVLINK_ATTR_PORT_EXTERNAL = 149,\n\tDEVLINK_ATTR_PORT_CONTROLLER_NUMBER = 150,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TIMEOUT = 151,\n\tDEVLINK_ATTR_FLASH_UPDATE_OVERWRITE_MASK = 152,\n\tDEVLINK_ATTR_RELOAD_ACTION = 153,\n\tDEVLINK_ATTR_RELOAD_ACTIONS_PERFORMED = 154,\n\tDEVLINK_ATTR_RELOAD_LIMITS = 155,\n\tDEVLINK_ATTR_DEV_STATS = 156,\n\tDEVLINK_ATTR_RELOAD_STATS = 157,\n\tDEVLINK_ATTR_RELOAD_STATS_ENTRY = 158,\n\tDEVLINK_ATTR_RELOAD_STATS_LIMIT = 159,\n\tDEVLINK_ATTR_RELOAD_STATS_VALUE = 160,\n\tDEVLINK_ATTR_REMOTE_RELOAD_STATS = 161,\n\tDEVLINK_ATTR_RELOAD_ACTION_INFO = 162,\n\tDEVLINK_ATTR_RELOAD_ACTION_STATS = 163,\n\tDEVLINK_ATTR_PORT_PCI_SF_NUMBER = 164,\n\tDEVLINK_ATTR_RATE_TYPE = 165,\n\tDEVLINK_ATTR_RATE_TX_SHARE = 166,\n\tDEVLINK_ATTR_RATE_TX_MAX = 167,\n\tDEVLINK_ATTR_RATE_NODE_NAME = 168,\n\tDEVLINK_ATTR_RATE_PARENT_NODE_NAME = 169,\n\tDEVLINK_ATTR_REGION_MAX_SNAPSHOTS = 170,\n\tDEVLINK_ATTR_LINECARD_INDEX = 171,\n\tDEVLINK_ATTR_LINECARD_STATE = 172,\n\tDEVLINK_ATTR_LINECARD_TYPE = 173,\n\tDEVLINK_ATTR_LINECARD_SUPPORTED_TYPES = 174,\n\tDEVLINK_ATTR_NESTED_DEVLINK = 175,\n\tDEVLINK_ATTR_SELFTESTS = 176,\n\tDEVLINK_ATTR_RATE_TX_PRIORITY = 177,\n\tDEVLINK_ATTR_RATE_TX_WEIGHT = 178,\n\tDEVLINK_ATTR_REGION_DIRECT = 179,\n\tDEVLINK_ATTR_RATE_TC_BWS = 180,\n\tDEVLINK_ATTR_HEALTH_REPORTER_BURST_PERIOD = 181,\n\tDEVLINK_ATTR_PARAM_VALUE_DEFAULT = 182,\n\tDEVLINK_ATTR_PARAM_RESET_DEFAULT = 183,\n\t__DEVLINK_ATTR_MAX = 184,\n\tDEVLINK_ATTR_MAX = 183,\n};\n\nenum devlink_attr_selftest_id {\n\tDEVLINK_ATTR_SELFTEST_ID_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_ID_FLASH = 1,\n\t__DEVLINK_ATTR_SELFTEST_ID_MAX = 2,\n\tDEVLINK_ATTR_SELFTEST_ID_MAX = 1,\n};\n\nenum devlink_attr_selftest_result {\n\tDEVLINK_ATTR_SELFTEST_RESULT_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_RESULT = 1,\n\tDEVLINK_ATTR_SELFTEST_RESULT_ID = 2,\n\tDEVLINK_ATTR_SELFTEST_RESULT_STATUS = 3,\n\t__DEVLINK_ATTR_SELFTEST_RESULT_MAX = 4,\n\tDEVLINK_ATTR_SELFTEST_RESULT_MAX = 3,\n};\n\nenum devlink_command {\n\tDEVLINK_CMD_UNSPEC = 0,\n\tDEVLINK_CMD_GET = 1,\n\tDEVLINK_CMD_SET = 2,\n\tDEVLINK_CMD_NEW = 3,\n\tDEVLINK_CMD_DEL = 4,\n\tDEVLINK_CMD_PORT_GET = 5,\n\tDEVLINK_CMD_PORT_SET = 6,\n\tDEVLINK_CMD_PORT_NEW = 7,\n\tDEVLINK_CMD_PORT_DEL = 8,\n\tDEVLINK_CMD_PORT_SPLIT = 9,\n\tDEVLINK_CMD_PORT_UNSPLIT = 10,\n\tDEVLINK_CMD_SB_GET = 11,\n\tDEVLINK_CMD_SB_SET = 12,\n\tDEVLINK_CMD_SB_NEW = 13,\n\tDEVLINK_CMD_SB_DEL = 14,\n\tDEVLINK_CMD_SB_POOL_GET = 15,\n\tDEVLINK_CMD_SB_POOL_SET = 16,\n\tDEVLINK_CMD_SB_POOL_NEW = 17,\n\tDEVLINK_CMD_SB_POOL_DEL = 18,\n\tDEVLINK_CMD_SB_PORT_POOL_GET = 19,\n\tDEVLINK_CMD_SB_PORT_POOL_SET = 20,\n\tDEVLINK_CMD_SB_PORT_POOL_NEW = 21,\n\tDEVLINK_CMD_SB_PORT_POOL_DEL = 22,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_GET = 23,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_SET = 24,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_NEW = 25,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_DEL = 26,\n\tDEVLINK_CMD_SB_OCC_SNAPSHOT = 27,\n\tDEVLINK_CMD_SB_OCC_MAX_CLEAR = 28,\n\tDEVLINK_CMD_ESWITCH_GET = 29,\n\tDEVLINK_CMD_ESWITCH_SET = 30,\n\tDEVLINK_CMD_DPIPE_TABLE_GET = 31,\n\tDEVLINK_CMD_DPIPE_ENTRIES_GET = 32,\n\tDEVLINK_CMD_DPIPE_HEADERS_GET = 33,\n\tDEVLINK_CMD_DPIPE_TABLE_COUNTERS_SET = 34,\n\tDEVLINK_CMD_RESOURCE_SET = 35,\n\tDEVLINK_CMD_RESOURCE_DUMP = 36,\n\tDEVLINK_CMD_RELOAD = 37,\n\tDEVLINK_CMD_PARAM_GET = 38,\n\tDEVLINK_CMD_PARAM_SET = 39,\n\tDEVLINK_CMD_PARAM_NEW = 40,\n\tDEVLINK_CMD_PARAM_DEL = 41,\n\tDEVLINK_CMD_REGION_GET = 42,\n\tDEVLINK_CMD_REGION_SET = 43,\n\tDEVLINK_CMD_REGION_NEW = 44,\n\tDEVLINK_CMD_REGION_DEL = 45,\n\tDEVLINK_CMD_REGION_READ = 46,\n\tDEVLINK_CMD_PORT_PARAM_GET = 47,\n\tDEVLINK_CMD_PORT_PARAM_SET = 48,\n\tDEVLINK_CMD_PORT_PARAM_NEW = 49,\n\tDEVLINK_CMD_PORT_PARAM_DEL = 50,\n\tDEVLINK_CMD_INFO_GET = 51,\n\tDEVLINK_CMD_HEALTH_REPORTER_GET = 52,\n\tDEVLINK_CMD_HEALTH_REPORTER_SET = 53,\n\tDEVLINK_CMD_HEALTH_REPORTER_RECOVER = 54,\n\tDEVLINK_CMD_HEALTH_REPORTER_DIAGNOSE = 55,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_GET = 56,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_CLEAR = 57,\n\tDEVLINK_CMD_FLASH_UPDATE = 58,\n\tDEVLINK_CMD_FLASH_UPDATE_END = 59,\n\tDEVLINK_CMD_FLASH_UPDATE_STATUS = 60,\n\tDEVLINK_CMD_TRAP_GET = 61,\n\tDEVLINK_CMD_TRAP_SET = 62,\n\tDEVLINK_CMD_TRAP_NEW = 63,\n\tDEVLINK_CMD_TRAP_DEL = 64,\n\tDEVLINK_CMD_TRAP_GROUP_GET = 65,\n\tDEVLINK_CMD_TRAP_GROUP_SET = 66,\n\tDEVLINK_CMD_TRAP_GROUP_NEW = 67,\n\tDEVLINK_CMD_TRAP_GROUP_DEL = 68,\n\tDEVLINK_CMD_TRAP_POLICER_GET = 69,\n\tDEVLINK_CMD_TRAP_POLICER_SET = 70,\n\tDEVLINK_CMD_TRAP_POLICER_NEW = 71,\n\tDEVLINK_CMD_TRAP_POLICER_DEL = 72,\n\tDEVLINK_CMD_HEALTH_REPORTER_TEST = 73,\n\tDEVLINK_CMD_RATE_GET = 74,\n\tDEVLINK_CMD_RATE_SET = 75,\n\tDEVLINK_CMD_RATE_NEW = 76,\n\tDEVLINK_CMD_RATE_DEL = 77,\n\tDEVLINK_CMD_LINECARD_GET = 78,\n\tDEVLINK_CMD_LINECARD_SET = 79,\n\tDEVLINK_CMD_LINECARD_NEW = 80,\n\tDEVLINK_CMD_LINECARD_DEL = 81,\n\tDEVLINK_CMD_SELFTESTS_GET = 82,\n\tDEVLINK_CMD_SELFTESTS_RUN = 83,\n\tDEVLINK_CMD_NOTIFY_FILTER_SET = 84,\n\t__DEVLINK_CMD_MAX = 85,\n\tDEVLINK_CMD_MAX = 84,\n};\n\nenum devlink_dpipe_action_type {\n\tDEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY = 0,\n};\n\nenum devlink_dpipe_field_ethernet_id {\n\tDEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC = 0,\n};\n\nenum devlink_dpipe_field_ipv4_id {\n\tDEVLINK_DPIPE_FIELD_IPV4_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_ipv6_id {\n\tDEVLINK_DPIPE_FIELD_IPV6_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_mapping_type {\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0,\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1,\n};\n\nenum devlink_dpipe_header_id {\n\tDEVLINK_DPIPE_HEADER_ETHERNET = 0,\n\tDEVLINK_DPIPE_HEADER_IPV4 = 1,\n\tDEVLINK_DPIPE_HEADER_IPV6 = 2,\n};\n\nenum devlink_dpipe_match_type {\n\tDEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT = 0,\n};\n\nenum devlink_eswitch_encap_mode {\n\tDEVLINK_ESWITCH_ENCAP_MODE_NONE = 0,\n\tDEVLINK_ESWITCH_ENCAP_MODE_BASIC = 1,\n};\n\nenum devlink_health_reporter_state {\n\tDEVLINK_HEALTH_REPORTER_STATE_HEALTHY = 0,\n\tDEVLINK_HEALTH_REPORTER_STATE_ERROR = 1,\n};\n\nenum devlink_info_version_type {\n\tDEVLINK_INFO_VERSION_TYPE_NONE = 0,\n\tDEVLINK_INFO_VERSION_TYPE_COMPONENT = 1,\n};\n\nenum devlink_linecard_state {\n\tDEVLINK_LINECARD_STATE_UNSPEC = 0,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONED = 1,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONING = 2,\n\tDEVLINK_LINECARD_STATE_PROVISIONING = 3,\n\tDEVLINK_LINECARD_STATE_PROVISIONING_FAILED = 4,\n\tDEVLINK_LINECARD_STATE_PROVISIONED = 5,\n\tDEVLINK_LINECARD_STATE_ACTIVE = 6,\n\t__DEVLINK_LINECARD_STATE_MAX = 7,\n\tDEVLINK_LINECARD_STATE_MAX = 6,\n};\n\nenum devlink_multicast_groups {\n\tDEVLINK_MCGRP_CONFIG = 0,\n};\n\nenum devlink_param_cmode {\n\tDEVLINK_PARAM_CMODE_RUNTIME = 0,\n\tDEVLINK_PARAM_CMODE_DRIVERINIT = 1,\n\tDEVLINK_PARAM_CMODE_PERMANENT = 2,\n\t__DEVLINK_PARAM_CMODE_MAX = 3,\n\tDEVLINK_PARAM_CMODE_MAX = 2,\n};\n\nenum devlink_param_generic_id {\n\tDEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET = 0,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MACS = 1,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_SRIOV = 2,\n\tDEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT = 3,\n\tDEVLINK_PARAM_GENERIC_ID_IGNORE_ARI = 4,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX = 5,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN = 6,\n\tDEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY = 7,\n\tDEVLINK_PARAM_GENERIC_ID_RESET_DEV_ON_DRV_PROBE = 8,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE = 9,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_REMOTE_DEV_RESET = 10,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ETH = 11,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA = 12,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_VNET = 13,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_IWARP = 14,\n\tDEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE = 15,\n\tDEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE = 16,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_PHC = 17,\n\tDEVLINK_PARAM_GENERIC_ID_CLOCK_ID = 18,\n\tDEVLINK_PARAM_GENERIC_ID_TOTAL_VFS = 19,\n\tDEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS = 20,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF = 21,\n\t__DEVLINK_PARAM_GENERIC_ID_MAX = 22,\n\tDEVLINK_PARAM_GENERIC_ID_MAX = 21,\n};\n\nenum devlink_param_type {\n\tDEVLINK_PARAM_TYPE_U8 = 1,\n\tDEVLINK_PARAM_TYPE_U16 = 2,\n\tDEVLINK_PARAM_TYPE_U32 = 3,\n\tDEVLINK_PARAM_TYPE_U64 = 4,\n\tDEVLINK_PARAM_TYPE_STRING = 5,\n\tDEVLINK_PARAM_TYPE_BOOL = 6,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_attr_cap {\n\tDEVLINK_PORT_FN_ATTR_CAP_ROCE_BIT = 0,\n\tDEVLINK_PORT_FN_ATTR_CAP_MIGRATABLE_BIT = 1,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_CRYPTO_BIT = 2,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_PACKET_BIT = 3,\n\t__DEVLINK_PORT_FN_ATTR_CAPS_MAX = 4,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_function_attr {\n\tDEVLINK_PORT_FUNCTION_ATTR_UNSPEC = 0,\n\tDEVLINK_PORT_FUNCTION_ATTR_HW_ADDR = 1,\n\tDEVLINK_PORT_FN_ATTR_STATE = 2,\n\tDEVLINK_PORT_FN_ATTR_OPSTATE = 3,\n\tDEVLINK_PORT_FN_ATTR_CAPS = 4,\n\tDEVLINK_PORT_FN_ATTR_DEVLINK = 5,\n\tDEVLINK_PORT_FN_ATTR_MAX_IO_EQS = 6,\n\t__DEVLINK_PORT_FUNCTION_ATTR_MAX = 7,\n\tDEVLINK_PORT_FUNCTION_ATTR_MAX = 6,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_tc_attr {\n\tDEVLINK_RATE_TC_ATTR_UNSPEC = 0,\n\tDEVLINK_RATE_TC_ATTR_INDEX = 1,\n\tDEVLINK_RATE_TC_ATTR_BW = 2,\n\t__DEVLINK_RATE_TC_ATTR_MAX = 3,\n\tDEVLINK_RATE_TC_ATTR_MAX = 2,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devlink_reload_action {\n\tDEVLINK_RELOAD_ACTION_UNSPEC = 0,\n\tDEVLINK_RELOAD_ACTION_DRIVER_REINIT = 1,\n\tDEVLINK_RELOAD_ACTION_FW_ACTIVATE = 2,\n\t__DEVLINK_RELOAD_ACTION_MAX = 3,\n\tDEVLINK_RELOAD_ACTION_MAX = 2,\n};\n\nenum devlink_reload_limit {\n\tDEVLINK_RELOAD_LIMIT_UNSPEC = 0,\n\tDEVLINK_RELOAD_LIMIT_NO_RESET = 1,\n\t__DEVLINK_RELOAD_LIMIT_MAX = 2,\n\tDEVLINK_RELOAD_LIMIT_MAX = 1,\n};\n\nenum devlink_resource_unit {\n\tDEVLINK_RESOURCE_UNIT_ENTRY = 0,\n};\n\nenum devlink_sb_pool_type {\n\tDEVLINK_SB_POOL_TYPE_INGRESS = 0,\n\tDEVLINK_SB_POOL_TYPE_EGRESS = 1,\n};\n\nenum devlink_sb_threshold_type {\n\tDEVLINK_SB_THRESHOLD_TYPE_STATIC = 0,\n\tDEVLINK_SB_THRESHOLD_TYPE_DYNAMIC = 1,\n};\n\nenum devlink_selftest_status {\n\tDEVLINK_SELFTEST_STATUS_SKIP = 0,\n\tDEVLINK_SELFTEST_STATUS_PASS = 1,\n\tDEVLINK_SELFTEST_STATUS_FAIL = 2,\n};\n\nenum devlink_trap_action {\n\tDEVLINK_TRAP_ACTION_DROP = 0,\n\tDEVLINK_TRAP_ACTION_TRAP = 1,\n\tDEVLINK_TRAP_ACTION_MIRROR = 2,\n};\n\nenum devlink_trap_generic_id {\n\tDEVLINK_TRAP_GENERIC_ID_SMAC_MC = 0,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_TAG_MISMATCH = 1,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_VLAN_FILTER = 2,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_STP_FILTER = 3,\n\tDEVLINK_TRAP_GENERIC_ID_EMPTY_TX_LIST = 4,\n\tDEVLINK_TRAP_GENERIC_ID_PORT_LOOPBACK_FILTER = 5,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_ROUTE = 6,\n\tDEVLINK_TRAP_GENERIC_ID_TTL_ERROR = 7,\n\tDEVLINK_TRAP_GENERIC_ID_TAIL_DROP = 8,\n\tDEVLINK_TRAP_GENERIC_ID_NON_IP_PACKET = 9,\n\tDEVLINK_TRAP_GENERIC_ID_UC_DIP_MC_DMAC = 10,\n\tDEVLINK_TRAP_GENERIC_ID_DIP_LB = 11,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_MC = 12,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_LB = 13,\n\tDEVLINK_TRAP_GENERIC_ID_CORRUPTED_IP_HDR = 14,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_SIP_BC = 15,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_RESERVED_SCOPE = 16,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_INTERFACE_LOCAL_SCOPE = 17,\n\tDEVLINK_TRAP_GENERIC_ID_MTU_ERROR = 18,\n\tDEVLINK_TRAP_GENERIC_ID_UNRESOLVED_NEIGH = 19,\n\tDEVLINK_TRAP_GENERIC_ID_RPF = 20,\n\tDEVLINK_TRAP_GENERIC_ID_REJECT_ROUTE = 21,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_LPM_UNICAST_MISS = 22,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_LPM_UNICAST_MISS = 23,\n\tDEVLINK_TRAP_GENERIC_ID_NON_ROUTABLE = 24,\n\tDEVLINK_TRAP_GENERIC_ID_DECAP_ERROR = 25,\n\tDEVLINK_TRAP_GENERIC_ID_OVERLAY_SMAC_MC = 26,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_FLOW_ACTION_DROP = 27,\n\tDEVLINK_TRAP_GENERIC_ID_EGRESS_FLOW_ACTION_DROP = 28,\n\tDEVLINK_TRAP_GENERIC_ID_STP = 29,\n\tDEVLINK_TRAP_GENERIC_ID_LACP = 30,\n\tDEVLINK_TRAP_GENERIC_ID_LLDP = 31,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_QUERY = 32,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V1_REPORT = 33,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_REPORT = 34,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V3_REPORT = 35,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_LEAVE = 36,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_QUERY = 37,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_REPORT = 38,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V2_REPORT = 39,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_DONE = 40,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_DHCP = 41,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DHCP = 42,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_REQUEST = 43,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_RESPONSE = 44,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_OVERLAY = 45,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_SOLICIT = 46,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_ADVERT = 47,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BFD = 48,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BFD = 49,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_OSPF = 50,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_OSPF = 51,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BGP = 52,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BGP = 53,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_VRRP = 54,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_VRRP = 55,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_PIM = 56,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_PIM = 57,\n\tDEVLINK_TRAP_GENERIC_ID_UC_LB = 58,\n\tDEVLINK_TRAP_GENERIC_ID_LOCAL_ROUTE = 59,\n\tDEVLINK_TRAP_GENERIC_ID_EXTERNAL_ROUTE = 60,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_UC_DIP_LINK_LOCAL_SCOPE = 61,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_NODES = 62,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_ROUTERS = 63,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_SOLICIT = 64,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ADVERT = 65,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_REDIRECT = 66,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_ROUTER_ALERT = 67,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ALERT = 68,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_EVENT = 69,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_GENERAL = 70,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_SAMPLE = 71,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_TRAP = 72,\n\tDEVLINK_TRAP_GENERIC_ID_EARLY_DROP = 73,\n\tDEVLINK_TRAP_GENERIC_ID_VXLAN_PARSING = 74,\n\tDEVLINK_TRAP_GENERIC_ID_LLC_SNAP_PARSING = 75,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_PARSING = 76,\n\tDEVLINK_TRAP_GENERIC_ID_PPPOE_PPP_PARSING = 77,\n\tDEVLINK_TRAP_GENERIC_ID_MPLS_PARSING = 78,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_PARSING = 79,\n\tDEVLINK_TRAP_GENERIC_ID_IP_1_PARSING = 80,\n\tDEVLINK_TRAP_GENERIC_ID_IP_N_PARSING = 81,\n\tDEVLINK_TRAP_GENERIC_ID_GRE_PARSING = 82,\n\tDEVLINK_TRAP_GENERIC_ID_UDP_PARSING = 83,\n\tDEVLINK_TRAP_GENERIC_ID_TCP_PARSING = 84,\n\tDEVLINK_TRAP_GENERIC_ID_IPSEC_PARSING = 85,\n\tDEVLINK_TRAP_GENERIC_ID_SCTP_PARSING = 86,\n\tDEVLINK_TRAP_GENERIC_ID_DCCP_PARSING = 87,\n\tDEVLINK_TRAP_GENERIC_ID_GTP_PARSING = 88,\n\tDEVLINK_TRAP_GENERIC_ID_ESP_PARSING = 89,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_NEXTHOP = 90,\n\tDEVLINK_TRAP_GENERIC_ID_DMAC_FILTER = 91,\n\tDEVLINK_TRAP_GENERIC_ID_EAPOL = 92,\n\tDEVLINK_TRAP_GENERIC_ID_LOCKED_PORT = 93,\n\t__DEVLINK_TRAP_GENERIC_ID_MAX = 94,\n\tDEVLINK_TRAP_GENERIC_ID_MAX = 93,\n};\n\nenum devlink_trap_group_generic_id {\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L2_DROPS = 0,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_DROPS = 1,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_EXCEPTIONS = 2,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BUFFER_DROPS = 3,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_TUNNEL_DROPS = 4,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_DROPS = 5,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_STP = 6,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LACP = 7,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LLDP = 8,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MC_SNOOPING = 9,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_DHCP = 10,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_NEIGH_DISCOVERY = 11,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BFD = 12,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_OSPF = 13,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BGP = 14,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_VRRP = 15,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PIM = 16,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_UC_LB = 17,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LOCAL_DELIVERY = 18,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EXTERNAL_DELIVERY = 19,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_IPV6 = 20,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_EVENT = 21,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_GENERAL = 22,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_SAMPLE = 23,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_TRAP = 24,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PARSER_ERROR_DROPS = 25,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EAPOL = 26,\n\t__DEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 27,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 26,\n};\n\nenum devlink_trap_type {\n\tDEVLINK_TRAP_TYPE_DROP = 0,\n\tDEVLINK_TRAP_TYPE_EXCEPTION = 1,\n\tDEVLINK_TRAP_TYPE_CONTROL = 2,\n};\n\nenum devlink_var_attr_type {\n\tDEVLINK_VAR_ATTR_TYPE_U8 = 1,\n\tDEVLINK_VAR_ATTR_TYPE_U16 = 2,\n\tDEVLINK_VAR_ATTR_TYPE_U32 = 3,\n\tDEVLINK_VAR_ATTR_TYPE_U64 = 4,\n\tDEVLINK_VAR_ATTR_TYPE_STRING = 5,\n\tDEVLINK_VAR_ATTR_TYPE_FLAG = 6,\n\tDEVLINK_VAR_ATTR_TYPE_NUL_STRING = 10,\n\tDEVLINK_VAR_ATTR_TYPE_BINARY = 11,\n\t__DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE = 128,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum dfa_accept_flags {\n\tACCEPT_FLAG_OWNER = 1,\n};\n\nenum die_val {\n\tDIE_UNUSED = 0,\n\tDIE_TRAP = 1,\n\tDIE_OOPS = 2,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum display_flags {\n\tDISPLAY_FLAGS_HSYNC_LOW = 1,\n\tDISPLAY_FLAGS_HSYNC_HIGH = 2,\n\tDISPLAY_FLAGS_VSYNC_LOW = 4,\n\tDISPLAY_FLAGS_VSYNC_HIGH = 8,\n\tDISPLAY_FLAGS_DE_LOW = 16,\n\tDISPLAY_FLAGS_DE_HIGH = 32,\n\tDISPLAY_FLAGS_PIXDATA_POSEDGE = 64,\n\tDISPLAY_FLAGS_PIXDATA_NEGEDGE = 128,\n\tDISPLAY_FLAGS_INTERLACED = 256,\n\tDISPLAY_FLAGS_DOUBLESCAN = 512,\n\tDISPLAY_FLAGS_DOUBLECLK = 1024,\n\tDISPLAY_FLAGS_SYNC_POSEDGE = 2048,\n\tDISPLAY_FLAGS_SYNC_NEGEDGE = 4096,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n\tDMA_PREP_REPEAT = 256,\n\tDMA_PREP_LOAD_EOT = 512,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SEQNO64_BIT = 0,\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 1,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 2,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 3,\n\tDMA_FENCE_FLAG_USER_BITS = 4,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nenum dma_resv_usage {\n\tDMA_RESV_USAGE_KERNEL = 0,\n\tDMA_RESV_USAGE_WRITE = 1,\n\tDMA_RESV_USAGE_READ = 2,\n\tDMA_RESV_USAGE_BOOKKEEP = 3,\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n\tDMA_SLAVE_BUSWIDTH_128_BYTES = 128,\n};\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n\tDMA_OUT_OF_ORDER = 4,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_COMPLETION_NO_ORDER = 13,\n\tDMA_REPEAT = 14,\n\tDMA_LOAD_EOT = 15,\n\tDMA_TX_TYPE_END = 16,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n\tDMAENGINE_ALIGN_128_BYTES = 7,\n\tDMAENGINE_ALIGN_256_BYTES = 8,\n};\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nenum dmi_device_type {\n\tDMI_DEV_TYPE_ANY = 0,\n\tDMI_DEV_TYPE_OTHER = 1,\n\tDMI_DEV_TYPE_UNKNOWN = 2,\n\tDMI_DEV_TYPE_VIDEO = 3,\n\tDMI_DEV_TYPE_SCSI = 4,\n\tDMI_DEV_TYPE_ETHERNET = 5,\n\tDMI_DEV_TYPE_TOKENRING = 6,\n\tDMI_DEV_TYPE_SOUND = 7,\n\tDMI_DEV_TYPE_PATA = 8,\n\tDMI_DEV_TYPE_SATA = 9,\n\tDMI_DEV_TYPE_SAS = 10,\n\tDMI_DEV_TYPE_IPMI = -1,\n\tDMI_DEV_TYPE_OEM_STRING = -2,\n\tDMI_DEV_TYPE_DEV_ONBOARD = -3,\n\tDMI_DEV_TYPE_DEV_SLOT = -4,\n};\n\nenum dmi_entry_type {\n\tDMI_ENTRY_BIOS = 0,\n\tDMI_ENTRY_SYSTEM = 1,\n\tDMI_ENTRY_BASEBOARD = 2,\n\tDMI_ENTRY_CHASSIS = 3,\n\tDMI_ENTRY_PROCESSOR = 4,\n\tDMI_ENTRY_MEM_CONTROLLER = 5,\n\tDMI_ENTRY_MEM_MODULE = 6,\n\tDMI_ENTRY_CACHE = 7,\n\tDMI_ENTRY_PORT_CONNECTOR = 8,\n\tDMI_ENTRY_SYSTEM_SLOT = 9,\n\tDMI_ENTRY_ONBOARD_DEVICE = 10,\n\tDMI_ENTRY_OEMSTRINGS = 11,\n\tDMI_ENTRY_SYSCONF = 12,\n\tDMI_ENTRY_BIOS_LANG = 13,\n\tDMI_ENTRY_GROUP_ASSOC = 14,\n\tDMI_ENTRY_SYSTEM_EVENT_LOG = 15,\n\tDMI_ENTRY_PHYS_MEM_ARRAY = 16,\n\tDMI_ENTRY_MEM_DEVICE = 17,\n\tDMI_ENTRY_32_MEM_ERROR = 18,\n\tDMI_ENTRY_MEM_ARRAY_MAPPED_ADDR = 19,\n\tDMI_ENTRY_MEM_DEV_MAPPED_ADDR = 20,\n\tDMI_ENTRY_BUILTIN_POINTING_DEV = 21,\n\tDMI_ENTRY_PORTABLE_BATTERY = 22,\n\tDMI_ENTRY_SYSTEM_RESET = 23,\n\tDMI_ENTRY_HW_SECURITY = 24,\n\tDMI_ENTRY_SYSTEM_POWER_CONTROLS = 25,\n\tDMI_ENTRY_VOLTAGE_PROBE = 26,\n\tDMI_ENTRY_COOLING_DEV = 27,\n\tDMI_ENTRY_TEMP_PROBE = 28,\n\tDMI_ENTRY_ELECTRICAL_CURRENT_PROBE = 29,\n\tDMI_ENTRY_OOB_REMOTE_ACCESS = 30,\n\tDMI_ENTRY_BIS_ENTRY = 31,\n\tDMI_ENTRY_SYSTEM_BOOT = 32,\n\tDMI_ENTRY_MGMT_DEV = 33,\n\tDMI_ENTRY_MGMT_DEV_COMPONENT = 34,\n\tDMI_ENTRY_MGMT_DEV_THRES = 35,\n\tDMI_ENTRY_MEM_CHANNEL = 36,\n\tDMI_ENTRY_IPMI_DEV = 37,\n\tDMI_ENTRY_SYS_POWER_SUPPLY = 38,\n\tDMI_ENTRY_ADDITIONAL = 39,\n\tDMI_ENTRY_ONBOARD_DEV_EXT = 40,\n\tDMI_ENTRY_MGMT_CONTROLLER_HOST = 41,\n\tDMI_ENTRY_INACTIVE = 126,\n\tDMI_ENTRY_END_OF_TABLE = 127,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum dw_edma_chip_flags {\n\tDW_EDMA_CHIP_LOCAL = 1,\n};\n\nenum dw_edma_map_format {\n\tEDMA_MF_EDMA_LEGACY = 0,\n\tEDMA_MF_EDMA_UNROLL = 1,\n\tEDMA_MF_HDMA_COMPAT = 5,\n\tEDMA_MF_HDMA_NATIVE = 7,\n};\n\nenum dw_mci_cookie {\n\tCOOKIE_UNMAPPED = 0,\n\tCOOKIE_PRE_MAPPED = 1,\n\tCOOKIE_MAPPED = 2,\n};\n\nenum dw_mci_state {\n\tSTATE_IDLE = 0,\n\tSTATE_SENDING_CMD = 1,\n\tSTATE_SENDING_DATA = 2,\n\tSTATE_DATA_BUSY = 3,\n\tSTATE_SENDING_STOP = 4,\n\tSTATE_DATA_ERROR = 5,\n\tSTATE_SENDING_CMD11 = 6,\n\tSTATE_WAITING_CMD11_DONE = 7,\n};\n\nenum dw_pcie_app_clk {\n\tDW_PCIE_DBI_CLK = 0,\n\tDW_PCIE_MSTR_CLK = 1,\n\tDW_PCIE_SLV_CLK = 2,\n\tDW_PCIE_NUM_APP_CLKS = 3,\n};\n\nenum dw_pcie_app_rst {\n\tDW_PCIE_DBI_RST = 0,\n\tDW_PCIE_MSTR_RST = 1,\n\tDW_PCIE_SLV_RST = 2,\n\tDW_PCIE_NUM_APP_RSTS = 3,\n};\n\nenum dw_pcie_core_clk {\n\tDW_PCIE_PIPE_CLK = 0,\n\tDW_PCIE_CORE_CLK = 1,\n\tDW_PCIE_AUX_CLK = 2,\n\tDW_PCIE_REF_CLK = 3,\n\tDW_PCIE_NUM_CORE_CLKS = 4,\n};\n\nenum dw_pcie_core_rst {\n\tDW_PCIE_NON_STICKY_RST = 0,\n\tDW_PCIE_STICKY_RST = 1,\n\tDW_PCIE_CORE_RST = 2,\n\tDW_PCIE_PIPE_RST = 3,\n\tDW_PCIE_PHY_RST = 4,\n\tDW_PCIE_HOT_RST = 5,\n\tDW_PCIE_PWR_RST = 6,\n\tDW_PCIE_NUM_CORE_RSTS = 7,\n};\n\nenum dw_pcie_device_mode {\n\tDW_PCIE_UNKNOWN_TYPE = 0,\n\tDW_PCIE_EP_TYPE = 1,\n\tDW_PCIE_LEG_EP_TYPE = 2,\n\tDW_PCIE_RC_TYPE = 3,\n};\n\nenum dw_pcie_ltssm {\n\tDW_PCIE_LTSSM_DETECT_QUIET = 0,\n\tDW_PCIE_LTSSM_DETECT_ACT = 1,\n\tDW_PCIE_LTSSM_POLL_ACTIVE = 2,\n\tDW_PCIE_LTSSM_POLL_COMPLIANCE = 3,\n\tDW_PCIE_LTSSM_POLL_CONFIG = 4,\n\tDW_PCIE_LTSSM_PRE_DETECT_QUIET = 5,\n\tDW_PCIE_LTSSM_DETECT_WAIT = 6,\n\tDW_PCIE_LTSSM_CFG_LINKWD_START = 7,\n\tDW_PCIE_LTSSM_CFG_LINKWD_ACEPT = 8,\n\tDW_PCIE_LTSSM_CFG_LANENUM_WAI = 9,\n\tDW_PCIE_LTSSM_CFG_LANENUM_ACEPT = 10,\n\tDW_PCIE_LTSSM_CFG_COMPLETE = 11,\n\tDW_PCIE_LTSSM_CFG_IDLE = 12,\n\tDW_PCIE_LTSSM_RCVRY_LOCK = 13,\n\tDW_PCIE_LTSSM_RCVRY_SPEED = 14,\n\tDW_PCIE_LTSSM_RCVRY_RCVRCFG = 15,\n\tDW_PCIE_LTSSM_RCVRY_IDLE = 16,\n\tDW_PCIE_LTSSM_L0 = 17,\n\tDW_PCIE_LTSSM_L0S = 18,\n\tDW_PCIE_LTSSM_L123_SEND_EIDLE = 19,\n\tDW_PCIE_LTSSM_L1_IDLE = 20,\n\tDW_PCIE_LTSSM_L2_IDLE = 21,\n\tDW_PCIE_LTSSM_L2_WAKE = 22,\n\tDW_PCIE_LTSSM_DISABLED_ENTRY = 23,\n\tDW_PCIE_LTSSM_DISABLED_IDLE = 24,\n\tDW_PCIE_LTSSM_DISABLED = 25,\n\tDW_PCIE_LTSSM_LPBK_ENTRY = 26,\n\tDW_PCIE_LTSSM_LPBK_ACTIVE = 27,\n\tDW_PCIE_LTSSM_LPBK_EXIT = 28,\n\tDW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT = 29,\n\tDW_PCIE_LTSSM_HOT_RESET_ENTRY = 30,\n\tDW_PCIE_LTSSM_HOT_RESET = 31,\n\tDW_PCIE_LTSSM_RCVRY_EQ0 = 32,\n\tDW_PCIE_LTSSM_RCVRY_EQ1 = 33,\n\tDW_PCIE_LTSSM_RCVRY_EQ2 = 34,\n\tDW_PCIE_LTSSM_RCVRY_EQ3 = 35,\n\tDW_PCIE_LTSSM_L1_1 = 321,\n\tDW_PCIE_LTSSM_L1_2 = 322,\n\tDW_PCIE_LTSSM_UNKNOWN = 4294967295,\n};\n\nenum dwcmshc_rk_type {\n\tDWCMSHC_RK3568 = 0,\n\tDWCMSHC_RK3588 = 1,\n};\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok = 1,\n\te1000_1000t_rx_status_undefined = 255,\n};\n\nenum e1000_boards {\n\tboard_82571 = 0,\n\tboard_82572 = 1,\n\tboard_82573 = 2,\n\tboard_82574 = 3,\n\tboard_82583 = 4,\n\tboard_80003es2lan = 5,\n\tboard_ich8lan = 6,\n\tboard_ich9lan = 7,\n\tboard_ich10lan = 8,\n\tboard_pchlan = 9,\n\tboard_pch2lan = 10,\n\tboard_pch_lpt = 11,\n\tboard_pch_spt = 12,\n\tboard_pch_cnp = 13,\n\tboard_pch_tgp = 14,\n\tboard_pch_adp = 15,\n\tboard_pch_mtp = 16,\n\tboard_pch_ptp = 17,\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_pcie_x1 = 1,\n\te1000_bus_width_pcie_x2 = 2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32 = 9,\n\te1000_bus_width_64 = 10,\n\te1000_bus_width_reserved = 11,\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause = 1,\n\te1000_fc_tx_pause = 2,\n\te1000_fc_full = 3,\n\te1000_fc_default = 255,\n};\n\nenum e1000_mac_type {\n\te1000_82571 = 0,\n\te1000_82572 = 1,\n\te1000_82573 = 2,\n\te1000_82574 = 3,\n\te1000_82583 = 4,\n\te1000_80003es2lan = 5,\n\te1000_ich8lan = 6,\n\te1000_ich9lan = 7,\n\te1000_ich10lan = 8,\n\te1000_pchlan = 9,\n\te1000_pch2lan = 10,\n\te1000_pch_lpt = 11,\n\te1000_pch_spt = 12,\n\te1000_pch_cnp = 13,\n\te1000_pch_tgp = 14,\n\te1000_pch_adp = 15,\n\te1000_pch_mtp = 16,\n\te1000_pch_lnp = 17,\n\te1000_pch_ptp = 18,\n\te1000_pch_nvp = 19,\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper = 1,\n\te1000_media_type_fiber = 2,\n\te1000_media_type_internal_serdes = 3,\n\te1000_num_media_types = 4,\n};\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf = 1,\n\te1000_mng_mode_pt = 2,\n\te1000_mng_mode_ipmi = 3,\n\te1000_mng_mode_host_if_only = 4,\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master = 1,\n\te1000_ms_force_slave = 2,\n\te1000_ms_auto = 3,\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small = 1,\n\te1000_nvm_override_spi_large = 2,\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none = 1,\n\te1000_nvm_eeprom_spi = 2,\n\te1000_nvm_flash_hw = 3,\n\te1000_nvm_flash_sw = 4,\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none = 1,\n\te1000_phy_m88 = 2,\n\te1000_phy_igp = 3,\n\te1000_phy_igp_2 = 4,\n\te1000_phy_gg82563 = 5,\n\te1000_phy_igp_3 = 6,\n\te1000_phy_ife = 7,\n\te1000_phy_bm = 8,\n\te1000_phy_82578 = 9,\n\te1000_phy_82577 = 10,\n\te1000_phy_82579 = 11,\n\te1000_phy_i217 = 12,\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed = 1,\n\te1000_rev_polarity_undefined = 255,\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress = 1,\n\te1000_serdes_link_autoneg_complete = 2,\n\te1000_serdes_link_forced_up = 3,\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on = 1,\n\te1000_smart_speed_off = 2,\n};\n\nenum e1000_state_t {\n\t__E1000_TESTING = 0,\n\t__E1000_RESETTING = 1,\n\t__E1000_ACCESS_SHARED_RESOURCE = 2,\n\t__E1000_DOWN = 3,\n};\n\nenum e1000_ulp_state {\n\te1000_ulp_state_unknown = 0,\n\te1000_ulp_state_off = 1,\n\te1000_ulp_state_on = 2,\n};\n\nenum efi_cmdline_option {\n\tEFI_CMDLINE_NONE = 0,\n\tEFI_CMDLINE_MODE_NUM = 1,\n\tEFI_CMDLINE_RES = 2,\n\tEFI_CMDLINE_AUTO = 3,\n\tEFI_CMDLINE_LIST = 4,\n};\n\nenum efi_rts_ids {\n\tEFI_NONE = 0,\n\tEFI_GET_TIME = 1,\n\tEFI_SET_TIME = 2,\n\tEFI_GET_WAKEUP_TIME = 3,\n\tEFI_SET_WAKEUP_TIME = 4,\n\tEFI_GET_VARIABLE = 5,\n\tEFI_GET_NEXT_VARIABLE = 6,\n\tEFI_SET_VARIABLE = 7,\n\tEFI_QUERY_VARIABLE_INFO = 8,\n\tEFI_GET_NEXT_HIGH_MONO_COUNT = 9,\n\tEFI_RESET_SYSTEM = 10,\n\tEFI_UPDATE_CAPSULE = 11,\n\tEFI_QUERY_CAPSULE_CAPS = 12,\n\tEFI_ACPI_PRM_HANDLER = 13,\n};\n\nenum efi_secureboot_mode {\n\tefi_secureboot_mode_unset = 0,\n\tefi_secureboot_mode_unknown = 1,\n\tefi_secureboot_mode_disabled = 2,\n\tefi_secureboot_mode_enabled = 3,\n};\n\nenum efistub_event_type {\n\tEFISTUB_EVT_INITRD = 0,\n\tEFISTUB_EVT_LOAD_OPTIONS = 1,\n\tEFISTUB_EVT_COUNT = 2,\n};\n\nenum ehci_hrtimer_event {\n\tEHCI_HRTIMER_POLL_ASS = 0,\n\tEHCI_HRTIMER_POLL_PSS = 1,\n\tEHCI_HRTIMER_POLL_DEAD = 2,\n\tEHCI_HRTIMER_UNLINK_INTR = 3,\n\tEHCI_HRTIMER_FREE_ITDS = 4,\n\tEHCI_HRTIMER_ACTIVE_UNLINK = 5,\n\tEHCI_HRTIMER_START_UNLINK_INTR = 6,\n\tEHCI_HRTIMER_ASYNC_UNLINKS = 7,\n\tEHCI_HRTIMER_IAA_WATCHDOG = 8,\n\tEHCI_HRTIMER_DISABLE_PERIODIC = 9,\n\tEHCI_HRTIMER_DISABLE_ASYNC = 10,\n\tEHCI_HRTIMER_IO_WATCHDOG = 11,\n\tEHCI_HRTIMER_NUM_EVENTS = 12,\n};\n\nenum ehci_rh_state {\n\tEHCI_RH_HALTED = 0,\n\tEHCI_RH_SUSPENDED = 1,\n\tEHCI_RH_RUNNING = 2,\n\tEHCI_RH_STOPPING = 3,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n\tETT_EVENT_EPROBE = 64,\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_FROZEN = 8,\n\tEVENT_CPU = 16,\n\tEVENT_CGROUP = 32,\n\tEVENT_GUEST = 64,\n\tEVENT_FLAGS = 96,\n\tEVENT_ALL = 3,\n\tEVENT_TIME_FROZEN = 12,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum ext4_journal_trigger_type {\n\tEXT4_JTR_ORPHAN_FILE = 0,\n\tEXT4_JTR_NONE = 1,\n};\n\nenum ext4_li_mode {\n\tEXT4_LI_MODE_PREFETCH_BBITMAP = 0,\n\tEXT4_LI_MODE_ITABLE = 1,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_EDATA = 10,\n\tFETCH_OP_DEREF = 11,\n\tFETCH_OP_UDEREF = 12,\n\tFETCH_OP_ST_RAW = 13,\n\tFETCH_OP_ST_MEM = 14,\n\tFETCH_OP_ST_UMEM = 15,\n\tFETCH_OP_ST_STRING = 16,\n\tFETCH_OP_ST_USTRING = 17,\n\tFETCH_OP_ST_SYMSTR = 18,\n\tFETCH_OP_ST_EDATA = 19,\n\tFETCH_OP_MOD_BF = 20,\n\tFETCH_OP_LP_ARRAY = 21,\n\tFETCH_OP_TP_ARG = 22,\n\tFETCH_OP_END = 23,\n\tFETCH_NOP_SYMBOL = 24,\n};\n\nenum fib6_walk_state {\n\tFWS_L = 0,\n\tFWS_R = 1,\n\tFWS_C = 2,\n\tFWS_U = 3,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum filter_pred_fn {\n\tFILTER_PRED_FN_NOP = 0,\n\tFILTER_PRED_FN_64 = 1,\n\tFILTER_PRED_FN_64_CPUMASK = 2,\n\tFILTER_PRED_FN_S64 = 3,\n\tFILTER_PRED_FN_U64 = 4,\n\tFILTER_PRED_FN_32 = 5,\n\tFILTER_PRED_FN_32_CPUMASK = 6,\n\tFILTER_PRED_FN_S32 = 7,\n\tFILTER_PRED_FN_U32 = 8,\n\tFILTER_PRED_FN_16 = 9,\n\tFILTER_PRED_FN_16_CPUMASK = 10,\n\tFILTER_PRED_FN_S16 = 11,\n\tFILTER_PRED_FN_U16 = 12,\n\tFILTER_PRED_FN_8 = 13,\n\tFILTER_PRED_FN_8_CPUMASK = 14,\n\tFILTER_PRED_FN_S8 = 15,\n\tFILTER_PRED_FN_U8 = 16,\n\tFILTER_PRED_FN_COMM = 17,\n\tFILTER_PRED_FN_STRING = 18,\n\tFILTER_PRED_FN_STRLOC = 19,\n\tFILTER_PRED_FN_STRRELLOC = 20,\n\tFILTER_PRED_FN_PCHAR_USER = 21,\n\tFILTER_PRED_FN_PCHAR = 22,\n\tFILTER_PRED_FN_CPU = 23,\n\tFILTER_PRED_FN_CPU_CPUMASK = 24,\n\tFILTER_PRED_FN_CPUMASK = 25,\n\tFILTER_PRED_FN_CPUMASK_CPU = 26,\n\tFILTER_PRED_FN_FUNCTION = 27,\n\tFILTER_PRED_FN_ = 28,\n\tFILTER_PRED_TEST_VISITED = 29,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum fixed_addresses {\n\tFIX_HOLE = 0,\n\tFIX_FDT_END = 1,\n\tFIX_FDT = 1024,\n\tFIX_PTE = 1025,\n\tFIX_PMD = 1026,\n\tFIX_PUD = 1027,\n\tFIX_P4D = 1028,\n\tFIX_TEXT_POKE1 = 1029,\n\tFIX_TEXT_POKE0 = 1030,\n\tFIX_EARLYCON_MEM_BASE = 1031,\n\t__end_of_permanent_fixed_addresses = 1032,\n\tFIX_BTMAP_END = 1032,\n\tFIX_BTMAP_BEGIN = 1479,\n\t__end_of_fixed_addresses = 1480,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum flowlabel_reflect {\n\tFLOWLABEL_REFLECT_ESTABLISHED = 1,\n\tFLOWLABEL_REFLECT_TCP_RESET = 2,\n\tFLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fscache_cache_state {\n\tFSCACHE_CACHE_IS_NOT_PRESENT = 0,\n\tFSCACHE_CACHE_IS_PREPARING = 1,\n\tFSCACHE_CACHE_IS_ACTIVE = 2,\n\tFSCACHE_CACHE_GOT_IOERROR = 3,\n\tFSCACHE_CACHE_IS_WITHDRAWN = 4,\n};\n\nenum fscache_cookie_state {\n\tFSCACHE_COOKIE_STATE_QUIESCENT = 0,\n\tFSCACHE_COOKIE_STATE_LOOKING_UP = 1,\n\tFSCACHE_COOKIE_STATE_CREATING = 2,\n\tFSCACHE_COOKIE_STATE_ACTIVE = 3,\n\tFSCACHE_COOKIE_STATE_INVALIDATING = 4,\n\tFSCACHE_COOKIE_STATE_FAILED = 5,\n\tFSCACHE_COOKIE_STATE_LRU_DISCARDING = 6,\n\tFSCACHE_COOKIE_STATE_WITHDRAWING = 7,\n\tFSCACHE_COOKIE_STATE_RELINQUISHING = 8,\n\tFSCACHE_COOKIE_STATE_DROPPED = 9,\n} __attribute__((mode(byte)));\n\nenum fscache_want_state {\n\tFSCACHE_WANT_PARAMS = 0,\n\tFSCACHE_WANT_WRITE = 1,\n\tFSCACHE_WANT_READ = 2,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n\tFW_OPT_PARTIAL = 128,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nenum gddrnf4_status {\n\tGDD4_OK = 0,\n\tGDD4_UNAVAIL = 1,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum genpd_notication {\n\tGENPD_NOTIFY_PRE_OFF = 0,\n\tGENPD_NOTIFY_OFF = 1,\n\tGENPD_NOTIFY_PRE_ON = 2,\n\tGENPD_NOTIFY_ON = 3,\n};\n\nenum genpd_sync_state {\n\tGENPD_SYNC_STATE_OFF = 0,\n\tGENPD_SYNC_STATE_SIMPLE = 1,\n\tGENPD_SYNC_STATE_ONECELL = 2,\n};\n\nenum gpd_status {\n\tGENPD_STATE_ON = 0,\n\tGENPD_STATE_OFF = 1,\n};\n\nenum gpio_lookup_flags {\n\tGPIO_ACTIVE_HIGH = 0,\n\tGPIO_ACTIVE_LOW = 1,\n\tGPIO_OPEN_DRAIN = 2,\n\tGPIO_OPEN_SOURCE = 4,\n\tGPIO_PERSISTENT = 0,\n\tGPIO_TRANSITORY = 8,\n\tGPIO_PULL_UP = 16,\n\tGPIO_PULL_DOWN = 32,\n\tGPIO_PULL_DISABLE = 64,\n\tGPIO_LOOKUP_FLAGS_DEFAULT = 0,\n};\n\nenum gpio_v2_line_attr_id {\n\tGPIO_V2_LINE_ATTR_ID_FLAGS = 1,\n\tGPIO_V2_LINE_ATTR_ID_OUTPUT_VALUES = 2,\n\tGPIO_V2_LINE_ATTR_ID_DEBOUNCE = 3,\n};\n\nenum gpio_v2_line_changed_type {\n\tGPIO_V2_LINE_CHANGED_REQUESTED = 1,\n\tGPIO_V2_LINE_CHANGED_RELEASED = 2,\n\tGPIO_V2_LINE_CHANGED_CONFIG = 3,\n};\n\nenum gpio_v2_line_event_id {\n\tGPIO_V2_LINE_EVENT_RISING_EDGE = 1,\n\tGPIO_V2_LINE_EVENT_FALLING_EDGE = 2,\n};\n\nenum gpio_v2_line_flag {\n\tGPIO_V2_LINE_FLAG_USED = 1,\n\tGPIO_V2_LINE_FLAG_ACTIVE_LOW = 2,\n\tGPIO_V2_LINE_FLAG_INPUT = 4,\n\tGPIO_V2_LINE_FLAG_OUTPUT = 8,\n\tGPIO_V2_LINE_FLAG_EDGE_RISING = 16,\n\tGPIO_V2_LINE_FLAG_EDGE_FALLING = 32,\n\tGPIO_V2_LINE_FLAG_OPEN_DRAIN = 64,\n\tGPIO_V2_LINE_FLAG_OPEN_SOURCE = 128,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_UP = 256,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_DOWN = 512,\n\tGPIO_V2_LINE_FLAG_BIAS_DISABLED = 1024,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME = 2048,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE = 4096,\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum handshake_auth {\n\tHANDSHAKE_AUTH_UNSPEC = 0,\n\tHANDSHAKE_AUTH_UNAUTH = 1,\n\tHANDSHAKE_AUTH_PSK = 2,\n\tHANDSHAKE_AUTH_X509 = 3,\n};\n\nenum handshake_handler_class {\n\tHANDSHAKE_HANDLER_CLASS_NONE = 0,\n\tHANDSHAKE_HANDLER_CLASS_TLSHD = 1,\n\tHANDSHAKE_HANDLER_CLASS_MAX = 2,\n};\n\nenum handshake_msg_type {\n\tHANDSHAKE_MSG_TYPE_UNSPEC = 0,\n\tHANDSHAKE_MSG_TYPE_CLIENTHELLO = 1,\n\tHANDSHAKE_MSG_TYPE_SERVERHELLO = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum hdmi_3d_structure {\n\tHDMI_3D_STRUCTURE_INVALID = -1,\n\tHDMI_3D_STRUCTURE_FRAME_PACKING = 0,\n\tHDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1,\n\tHDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3,\n\tHDMI_3D_STRUCTURE_L_DEPTH = 4,\n\tHDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5,\n\tHDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8,\n};\n\nenum hdmi_active_aspect {\n\tHDMI_ACTIVE_ASPECT_16_9_TOP = 2,\n\tHDMI_ACTIVE_ASPECT_14_9_TOP = 3,\n\tHDMI_ACTIVE_ASPECT_16_9_CENTER = 4,\n\tHDMI_ACTIVE_ASPECT_PICTURE = 8,\n\tHDMI_ACTIVE_ASPECT_4_3 = 9,\n\tHDMI_ACTIVE_ASPECT_16_9 = 10,\n\tHDMI_ACTIVE_ASPECT_14_9 = 11,\n\tHDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15,\n};\n\nenum hdmi_audio_coding_type {\n\tHDMI_AUDIO_CODING_TYPE_STREAM = 0,\n\tHDMI_AUDIO_CODING_TYPE_PCM = 1,\n\tHDMI_AUDIO_CODING_TYPE_AC3 = 2,\n\tHDMI_AUDIO_CODING_TYPE_MPEG1 = 3,\n\tHDMI_AUDIO_CODING_TYPE_MP3 = 4,\n\tHDMI_AUDIO_CODING_TYPE_MPEG2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_DTS = 7,\n\tHDMI_AUDIO_CODING_TYPE_ATRAC = 8,\n\tHDMI_AUDIO_CODING_TYPE_DSD = 9,\n\tHDMI_AUDIO_CODING_TYPE_EAC3 = 10,\n\tHDMI_AUDIO_CODING_TYPE_DTS_HD = 11,\n\tHDMI_AUDIO_CODING_TYPE_MLP = 12,\n\tHDMI_AUDIO_CODING_TYPE_DST = 13,\n\tHDMI_AUDIO_CODING_TYPE_WMA_PRO = 14,\n\tHDMI_AUDIO_CODING_TYPE_CXT = 15,\n};\n\nenum hdmi_audio_coding_type_ext {\n\tHDMI_AUDIO_CODING_TYPE_EXT_CT = 0,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_EXT_DRA = 7,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10,\n};\n\nenum hdmi_audio_sample_frequency {\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7,\n};\n\nenum hdmi_audio_sample_size {\n\tHDMI_AUDIO_SAMPLE_SIZE_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_SIZE_16 = 1,\n\tHDMI_AUDIO_SAMPLE_SIZE_20 = 2,\n\tHDMI_AUDIO_SAMPLE_SIZE_24 = 3,\n};\n\nenum hdmi_colorimetry {\n\tHDMI_COLORIMETRY_NONE = 0,\n\tHDMI_COLORIMETRY_ITU_601 = 1,\n\tHDMI_COLORIMETRY_ITU_709 = 2,\n\tHDMI_COLORIMETRY_EXTENDED = 3,\n};\n\nenum hdmi_colorspace {\n\tHDMI_COLORSPACE_RGB = 0,\n\tHDMI_COLORSPACE_YUV422 = 1,\n\tHDMI_COLORSPACE_YUV444 = 2,\n\tHDMI_COLORSPACE_YUV420 = 3,\n\tHDMI_COLORSPACE_RESERVED4 = 4,\n\tHDMI_COLORSPACE_RESERVED5 = 5,\n\tHDMI_COLORSPACE_RESERVED6 = 6,\n\tHDMI_COLORSPACE_IDO_DEFINED = 7,\n};\n\nenum hdmi_content_type {\n\tHDMI_CONTENT_TYPE_GRAPHICS = 0,\n\tHDMI_CONTENT_TYPE_PHOTO = 1,\n\tHDMI_CONTENT_TYPE_CINEMA = 2,\n\tHDMI_CONTENT_TYPE_GAME = 3,\n};\n\nenum hdmi_eotf {\n\tHDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0,\n\tHDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1,\n\tHDMI_EOTF_SMPTE_ST2084 = 2,\n\tHDMI_EOTF_BT_2100_HLG = 3,\n};\n\nenum hdmi_extended_colorimetry {\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0,\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1,\n\tHDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2,\n\tHDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3,\n\tHDMI_EXTENDED_COLORIMETRY_OPRGB = 4,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020 = 6,\n\tHDMI_EXTENDED_COLORIMETRY_RESERVED = 7,\n};\n\nenum hdmi_infoframe_type {\n\tHDMI_INFOFRAME_TYPE_VENDOR = 129,\n\tHDMI_INFOFRAME_TYPE_AVI = 130,\n\tHDMI_INFOFRAME_TYPE_SPD = 131,\n\tHDMI_INFOFRAME_TYPE_AUDIO = 132,\n\tHDMI_INFOFRAME_TYPE_DRM = 135,\n};\n\nenum hdmi_metadata_type {\n\tHDMI_STATIC_METADATA_TYPE1 = 0,\n};\n\nenum hdmi_nups {\n\tHDMI_NUPS_UNKNOWN = 0,\n\tHDMI_NUPS_HORIZONTAL = 1,\n\tHDMI_NUPS_VERTICAL = 2,\n\tHDMI_NUPS_BOTH = 3,\n};\n\nenum hdmi_picture_aspect {\n\tHDMI_PICTURE_ASPECT_NONE = 0,\n\tHDMI_PICTURE_ASPECT_4_3 = 1,\n\tHDMI_PICTURE_ASPECT_16_9 = 2,\n\tHDMI_PICTURE_ASPECT_64_27 = 3,\n\tHDMI_PICTURE_ASPECT_256_135 = 4,\n\tHDMI_PICTURE_ASPECT_RESERVED = 5,\n};\n\nenum hdmi_quantization_range {\n\tHDMI_QUANTIZATION_RANGE_DEFAULT = 0,\n\tHDMI_QUANTIZATION_RANGE_LIMITED = 1,\n\tHDMI_QUANTIZATION_RANGE_FULL = 2,\n\tHDMI_QUANTIZATION_RANGE_RESERVED = 3,\n};\n\nenum hdmi_scan_mode {\n\tHDMI_SCAN_MODE_NONE = 0,\n\tHDMI_SCAN_MODE_OVERSCAN = 1,\n\tHDMI_SCAN_MODE_UNDERSCAN = 2,\n\tHDMI_SCAN_MODE_RESERVED = 3,\n};\n\nenum hdmi_spd_sdi {\n\tHDMI_SPD_SDI_UNKNOWN = 0,\n\tHDMI_SPD_SDI_DSTB = 1,\n\tHDMI_SPD_SDI_DVDP = 2,\n\tHDMI_SPD_SDI_DVHS = 3,\n\tHDMI_SPD_SDI_HDDVR = 4,\n\tHDMI_SPD_SDI_DVC = 5,\n\tHDMI_SPD_SDI_DSC = 6,\n\tHDMI_SPD_SDI_VCD = 7,\n\tHDMI_SPD_SDI_GAME = 8,\n\tHDMI_SPD_SDI_PC = 9,\n\tHDMI_SPD_SDI_BD = 10,\n\tHDMI_SPD_SDI_SACD = 11,\n\tHDMI_SPD_SDI_HDDVD = 12,\n\tHDMI_SPD_SDI_PMP = 13,\n};\n\nenum hdmi_ycc_quantization_range {\n\tHDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0,\n\tHDMI_YCC_QUANTIZATION_RANGE_FULL = 1,\n};\n\nenum hid_class_request {\n\tHID_REQ_GET_REPORT = 1,\n\tHID_REQ_GET_IDLE = 2,\n\tHID_REQ_GET_PROTOCOL = 3,\n\tHID_REQ_SET_REPORT = 9,\n\tHID_REQ_SET_IDLE = 10,\n\tHID_REQ_SET_PROTOCOL = 11,\n};\n\nenum hid_report_type {\n\tHID_INPUT_REPORT = 0,\n\tHID_OUTPUT_REPORT = 1,\n\tHID_FEATURE_REPORT = 2,\n\tHID_REPORT_TYPES = 3,\n};\n\nenum hid_type {\n\tHID_TYPE_OTHER = 0,\n\tHID_TYPE_USBMOUSE = 1,\n\tHID_TYPE_USBNONE = 2,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hn_flags_bits {\n\tHANDSHAKE_F_NET_DRAINING = 0,\n};\n\nenum hp_flags_bits {\n\tHANDSHAKE_F_PROTO_NOTIFY = 0,\n};\n\nenum hprobe_state {\n\tHPROBE_LEASED = 0,\n\tHPROBE_STABLE = 1,\n\tHPROBE_GONE = 2,\n\tHPROBE_CONSUMED = 3,\n};\n\nenum hpx_type3_cfg_loc {\n\tHPX_CFG_PCICFG = 0,\n\tHPX_CFG_PCIE_CAP = 1,\n\tHPX_CFG_PCIE_CAP_EXT = 2,\n\tHPX_CFG_VEND_CAP = 3,\n\tHPX_CFG_DVSEC = 4,\n\tHPX_CFG_MAX = 5,\n};\n\nenum hpx_type3_dev_type {\n\tHPX_TYPE_ENDPOINT = 1,\n\tHPX_TYPE_LEG_END = 2,\n\tHPX_TYPE_RC_END = 4,\n\tHPX_TYPE_RC_EC = 8,\n\tHPX_TYPE_ROOT_PORT = 16,\n\tHPX_TYPE_UPSTREAM = 32,\n\tHPX_TYPE_DOWNSTREAM = 64,\n\tHPX_TYPE_PCI_BRIDGE = 128,\n\tHPX_TYPE_PCIE_BRIDGE = 256,\n};\n\nenum hpx_type3_fn_type {\n\tHPX_FN_NORMAL = 1,\n\tHPX_FN_SRIOV_PHYS = 2,\n\tHPX_FN_SRIOV_VIRT = 4,\n};\n\nenum hr_flags_bits {\n\tHANDSHAKE_F_REQ_COMPLETED = 0,\n\tHANDSHAKE_F_REQ_SESSION = 1,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nenum hub_activation_type {\n\tHUB_INIT = 0,\n\tHUB_INIT2 = 1,\n\tHUB_INIT3 = 2,\n\tHUB_POST_RESET = 3,\n\tHUB_RESUME = 4,\n\tHUB_RESET_RESUME = 5,\n};\n\nenum hub_led_mode {\n\tINDICATOR_AUTO = 0,\n\tINDICATOR_CYCLE = 1,\n\tINDICATOR_GREEN_BLINK = 2,\n\tINDICATOR_GREEN_BLINK_OFF = 3,\n\tINDICATOR_AMBER_BLINK = 4,\n\tINDICATOR_AMBER_BLINK_OFF = 5,\n\tINDICATOR_ALT_BLINK = 6,\n\tINDICATOR_ALT_BLINK_OFF = 7,\n} __attribute__((mode(byte)));\n\nenum hub_quiescing_type {\n\tHUB_DISCONNECT = 0,\n\tHUB_PRE_RESET = 1,\n\tHUB_SUSPEND = 2,\n};\n\nenum hugetlb_memory_event {\n\tHUGETLB_MAX = 0,\n\tHUGETLB_NR_MEMORY_EVENTS = 1,\n};\n\nenum hugetlb_page_flags {\n\tHPG_restore_reserve = 0,\n\tHPG_migratable = 1,\n\tHPG_temporary = 2,\n\tHPG_freed = 3,\n\tHPG_vmemmap_optimized = 4,\n\tHPG_raw_hwp_unreliable = 5,\n\tHPG_cma = 6,\n\t__NR_HPAGEFLAGS = 7,\n};\n\nenum hugetlb_param {\n\tOpt_gid___7 = 0,\n\tOpt_min_size = 1,\n\tOpt_mode___5 = 2,\n\tOpt_nr_inodes = 3,\n\tOpt_pagesize = 4,\n\tOpt_size = 5,\n\tOpt_uid___7 = 6,\n};\n\nenum hugetlbfs_size_type {\n\tNO_SIZE = 0,\n\tSIZE_STD = 1,\n\tSIZE_PERCENT = 2,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwmon_chip_attributes {\n\thwmon_chip_temp_reset_history = 0,\n\thwmon_chip_in_reset_history = 1,\n\thwmon_chip_curr_reset_history = 2,\n\thwmon_chip_power_reset_history = 3,\n\thwmon_chip_register_tz = 4,\n\thwmon_chip_update_interval = 5,\n\thwmon_chip_alarms = 6,\n\thwmon_chip_samples = 7,\n\thwmon_chip_curr_samples = 8,\n\thwmon_chip_in_samples = 9,\n\thwmon_chip_power_samples = 10,\n\thwmon_chip_temp_samples = 11,\n\thwmon_chip_beep_enable = 12,\n\thwmon_chip_pec = 13,\n};\n\nenum hwmon_curr_attributes {\n\thwmon_curr_enable = 0,\n\thwmon_curr_input = 1,\n\thwmon_curr_min = 2,\n\thwmon_curr_max = 3,\n\thwmon_curr_lcrit = 4,\n\thwmon_curr_crit = 5,\n\thwmon_curr_average = 6,\n\thwmon_curr_lowest = 7,\n\thwmon_curr_highest = 8,\n\thwmon_curr_reset_history = 9,\n\thwmon_curr_label = 10,\n\thwmon_curr_alarm = 11,\n\thwmon_curr_min_alarm = 12,\n\thwmon_curr_max_alarm = 13,\n\thwmon_curr_lcrit_alarm = 14,\n\thwmon_curr_crit_alarm = 15,\n\thwmon_curr_rated_min = 16,\n\thwmon_curr_rated_max = 17,\n\thwmon_curr_beep = 18,\n};\n\nenum hwmon_energy_attributes {\n\thwmon_energy_enable = 0,\n\thwmon_energy_input = 1,\n\thwmon_energy_label = 2,\n};\n\nenum hwmon_fan_attributes {\n\thwmon_fan_enable = 0,\n\thwmon_fan_input = 1,\n\thwmon_fan_label = 2,\n\thwmon_fan_min = 3,\n\thwmon_fan_max = 4,\n\thwmon_fan_div = 5,\n\thwmon_fan_pulses = 6,\n\thwmon_fan_target = 7,\n\thwmon_fan_alarm = 8,\n\thwmon_fan_min_alarm = 9,\n\thwmon_fan_max_alarm = 10,\n\thwmon_fan_fault = 11,\n\thwmon_fan_beep = 12,\n};\n\nenum hwmon_humidity_attributes {\n\thwmon_humidity_enable = 0,\n\thwmon_humidity_input = 1,\n\thwmon_humidity_label = 2,\n\thwmon_humidity_min = 3,\n\thwmon_humidity_min_hyst = 4,\n\thwmon_humidity_max = 5,\n\thwmon_humidity_max_hyst = 6,\n\thwmon_humidity_alarm = 7,\n\thwmon_humidity_fault = 8,\n\thwmon_humidity_rated_min = 9,\n\thwmon_humidity_rated_max = 10,\n\thwmon_humidity_min_alarm = 11,\n\thwmon_humidity_max_alarm = 12,\n};\n\nenum hwmon_in_attributes {\n\thwmon_in_enable = 0,\n\thwmon_in_input = 1,\n\thwmon_in_min = 2,\n\thwmon_in_max = 3,\n\thwmon_in_lcrit = 4,\n\thwmon_in_crit = 5,\n\thwmon_in_average = 6,\n\thwmon_in_lowest = 7,\n\thwmon_in_highest = 8,\n\thwmon_in_reset_history = 9,\n\thwmon_in_label = 10,\n\thwmon_in_alarm = 11,\n\thwmon_in_min_alarm = 12,\n\thwmon_in_max_alarm = 13,\n\thwmon_in_lcrit_alarm = 14,\n\thwmon_in_crit_alarm = 15,\n\thwmon_in_rated_min = 16,\n\thwmon_in_rated_max = 17,\n\thwmon_in_beep = 18,\n\thwmon_in_fault = 19,\n};\n\nenum hwmon_intrusion_attributes {\n\thwmon_intrusion_alarm = 0,\n\thwmon_intrusion_beep = 1,\n};\n\nenum hwmon_power_attributes {\n\thwmon_power_enable = 0,\n\thwmon_power_average = 1,\n\thwmon_power_average_interval = 2,\n\thwmon_power_average_interval_max = 3,\n\thwmon_power_average_interval_min = 4,\n\thwmon_power_average_highest = 5,\n\thwmon_power_average_lowest = 6,\n\thwmon_power_average_max = 7,\n\thwmon_power_average_min = 8,\n\thwmon_power_input = 9,\n\thwmon_power_input_highest = 10,\n\thwmon_power_input_lowest = 11,\n\thwmon_power_reset_history = 12,\n\thwmon_power_accuracy = 13,\n\thwmon_power_cap = 14,\n\thwmon_power_cap_hyst = 15,\n\thwmon_power_cap_max = 16,\n\thwmon_power_cap_min = 17,\n\thwmon_power_min = 18,\n\thwmon_power_max = 19,\n\thwmon_power_crit = 20,\n\thwmon_power_lcrit = 21,\n\thwmon_power_label = 22,\n\thwmon_power_alarm = 23,\n\thwmon_power_cap_alarm = 24,\n\thwmon_power_min_alarm = 25,\n\thwmon_power_max_alarm = 26,\n\thwmon_power_lcrit_alarm = 27,\n\thwmon_power_crit_alarm = 28,\n\thwmon_power_rated_min = 29,\n\thwmon_power_rated_max = 30,\n};\n\nenum hwmon_pwm_attributes {\n\thwmon_pwm_input = 0,\n\thwmon_pwm_enable = 1,\n\thwmon_pwm_mode = 2,\n\thwmon_pwm_freq = 3,\n\thwmon_pwm_auto_channels_temp = 4,\n};\n\nenum hwmon_sensor_types {\n\thwmon_chip = 0,\n\thwmon_temp = 1,\n\thwmon_in = 2,\n\thwmon_curr = 3,\n\thwmon_power = 4,\n\thwmon_energy = 5,\n\thwmon_energy64 = 6,\n\thwmon_humidity = 7,\n\thwmon_fan = 8,\n\thwmon_pwm = 9,\n\thwmon_intrusion = 10,\n\thwmon_max = 11,\n};\n\nenum hwmon_temp_attributes {\n\thwmon_temp_enable = 0,\n\thwmon_temp_input = 1,\n\thwmon_temp_type = 2,\n\thwmon_temp_lcrit = 3,\n\thwmon_temp_lcrit_hyst = 4,\n\thwmon_temp_min = 5,\n\thwmon_temp_min_hyst = 6,\n\thwmon_temp_max = 7,\n\thwmon_temp_max_hyst = 8,\n\thwmon_temp_crit = 9,\n\thwmon_temp_crit_hyst = 10,\n\thwmon_temp_emergency = 11,\n\thwmon_temp_emergency_hyst = 12,\n\thwmon_temp_alarm = 13,\n\thwmon_temp_lcrit_alarm = 14,\n\thwmon_temp_min_alarm = 15,\n\thwmon_temp_max_alarm = 16,\n\thwmon_temp_crit_alarm = 17,\n\thwmon_temp_emergency_alarm = 18,\n\thwmon_temp_fault = 19,\n\thwmon_temp_offset = 20,\n\thwmon_temp_label = 21,\n\thwmon_temp_lowest = 22,\n\thwmon_temp_highest = 23,\n\thwmon_temp_reset_history = 24,\n\thwmon_temp_rated_min = 25,\n\thwmon_temp_rated_max = 26,\n\thwmon_temp_beep = 27,\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nenum i2c_driver_flags {\n\tI2C_DRV_ACPI_WAIVE_D0_PROBE = 1,\n};\n\nenum ib_atomic_cap {\n\tIB_ATOMIC_NONE = 0,\n\tIB_ATOMIC_HCA = 1,\n\tIB_ATOMIC_GLOB = 2,\n};\n\nenum ib_cq_notify_flags {\n\tIB_CQ_SOLICITED = 1,\n\tIB_CQ_NEXT_COMP = 2,\n\tIB_CQ_SOLICITED_MASK = 3,\n\tIB_CQ_REPORT_MISSED_EVENTS = 4,\n};\n\nenum ib_event_type {\n\tIB_EVENT_CQ_ERR = 0,\n\tIB_EVENT_QP_FATAL = 1,\n\tIB_EVENT_QP_REQ_ERR = 2,\n\tIB_EVENT_QP_ACCESS_ERR = 3,\n\tIB_EVENT_COMM_EST = 4,\n\tIB_EVENT_SQ_DRAINED = 5,\n\tIB_EVENT_PATH_MIG = 6,\n\tIB_EVENT_PATH_MIG_ERR = 7,\n\tIB_EVENT_DEVICE_FATAL = 8,\n\tIB_EVENT_PORT_ACTIVE = 9,\n\tIB_EVENT_PORT_ERR = 10,\n\tIB_EVENT_LID_CHANGE = 11,\n\tIB_EVENT_PKEY_CHANGE = 12,\n\tIB_EVENT_SM_CHANGE = 13,\n\tIB_EVENT_SRQ_ERR = 14,\n\tIB_EVENT_SRQ_LIMIT_REACHED = 15,\n\tIB_EVENT_QP_LAST_WQE_REACHED = 16,\n\tIB_EVENT_CLIENT_REREGISTER = 17,\n\tIB_EVENT_GID_CHANGE = 18,\n\tIB_EVENT_WQ_FATAL = 19,\n\tIB_EVENT_DEVICE_SPEED_CHANGE = 20,\n};\n\nenum ib_flow_action_type {\n\tIB_FLOW_ACTION_UNSPECIFIED = 0,\n\tIB_FLOW_ACTION_ESP = 1,\n};\n\nenum ib_flow_attr_type {\n\tIB_FLOW_ATTR_NORMAL = 0,\n\tIB_FLOW_ATTR_ALL_DEFAULT = 1,\n\tIB_FLOW_ATTR_MC_DEFAULT = 2,\n\tIB_FLOW_ATTR_SNIFFER = 3,\n};\n\nenum ib_flow_spec_type {\n\tIB_FLOW_SPEC_ETH = 32,\n\tIB_FLOW_SPEC_IB = 34,\n\tIB_FLOW_SPEC_IPV4 = 48,\n\tIB_FLOW_SPEC_IPV6 = 49,\n\tIB_FLOW_SPEC_ESP = 52,\n\tIB_FLOW_SPEC_TCP = 64,\n\tIB_FLOW_SPEC_UDP = 65,\n\tIB_FLOW_SPEC_VXLAN_TUNNEL = 80,\n\tIB_FLOW_SPEC_GRE = 81,\n\tIB_FLOW_SPEC_MPLS = 96,\n\tIB_FLOW_SPEC_INNER = 256,\n\tIB_FLOW_SPEC_ACTION_TAG = 4096,\n\tIB_FLOW_SPEC_ACTION_DROP = 4097,\n\tIB_FLOW_SPEC_ACTION_HANDLE = 4098,\n\tIB_FLOW_SPEC_ACTION_COUNT = 4099,\n};\n\nenum ib_gid_type {\n\tIB_GID_TYPE_IB = 0,\n\tIB_GID_TYPE_ROCE = 1,\n\tIB_GID_TYPE_ROCE_UDP_ENCAP = 2,\n\tIB_GID_TYPE_SIZE = 3,\n};\n\nenum ib_mig_state {\n\tIB_MIG_MIGRATED = 0,\n\tIB_MIG_REARM = 1,\n\tIB_MIG_ARMED = 2,\n};\n\nenum ib_mr_type {\n\tIB_MR_TYPE_MEM_REG = 0,\n\tIB_MR_TYPE_SG_GAPS = 1,\n\tIB_MR_TYPE_DM = 2,\n\tIB_MR_TYPE_USER = 3,\n\tIB_MR_TYPE_DMA = 4,\n\tIB_MR_TYPE_INTEGRITY = 5,\n};\n\nenum ib_mtu {\n\tIB_MTU_256 = 1,\n\tIB_MTU_512 = 2,\n\tIB_MTU_1024 = 3,\n\tIB_MTU_2048 = 4,\n\tIB_MTU_4096 = 5,\n};\n\nenum ib_mw_type {\n\tIB_MW_TYPE_1 = 1,\n\tIB_MW_TYPE_2 = 2,\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nenum ib_port_state {\n\tIB_PORT_NOP = 0,\n\tIB_PORT_DOWN = 1,\n\tIB_PORT_INIT = 2,\n\tIB_PORT_ARMED = 3,\n\tIB_PORT_ACTIVE = 4,\n\tIB_PORT_ACTIVE_DEFER = 5,\n};\n\nenum ib_qp_state {\n\tIB_QPS_RESET = 0,\n\tIB_QPS_INIT = 1,\n\tIB_QPS_RTR = 2,\n\tIB_QPS_RTS = 3,\n\tIB_QPS_SQD = 4,\n\tIB_QPS_SQE = 5,\n\tIB_QPS_ERR = 6,\n};\n\nenum ib_qp_type {\n\tIB_QPT_SMI = 0,\n\tIB_QPT_GSI = 1,\n\tIB_QPT_RC = 2,\n\tIB_QPT_UC = 3,\n\tIB_QPT_UD = 4,\n\tIB_QPT_RAW_IPV6 = 5,\n\tIB_QPT_RAW_ETHERTYPE = 6,\n\tIB_QPT_RAW_PACKET = 8,\n\tIB_QPT_XRC_INI = 9,\n\tIB_QPT_XRC_TGT = 10,\n\tIB_QPT_MAX = 11,\n\tIB_QPT_DRIVER = 255,\n\tIB_QPT_RESERVED1 = 4096,\n\tIB_QPT_RESERVED2 = 4097,\n\tIB_QPT_RESERVED3 = 4098,\n\tIB_QPT_RESERVED4 = 4099,\n\tIB_QPT_RESERVED5 = 4100,\n\tIB_QPT_RESERVED6 = 4101,\n\tIB_QPT_RESERVED7 = 4102,\n\tIB_QPT_RESERVED8 = 4103,\n\tIB_QPT_RESERVED9 = 4104,\n\tIB_QPT_RESERVED10 = 4105,\n};\n\nenum ib_sig_err_type {\n\tIB_SIG_BAD_GUARD = 0,\n\tIB_SIG_BAD_REFTAG = 1,\n\tIB_SIG_BAD_APPTAG = 2,\n};\n\nenum ib_sig_type {\n\tIB_SIGNAL_ALL_WR = 0,\n\tIB_SIGNAL_REQ_WR = 1,\n};\n\nenum ib_signature_type {\n\tIB_SIG_TYPE_NONE = 0,\n\tIB_SIG_TYPE_T10_DIF = 1,\n};\n\nenum ib_srq_attr_mask {\n\tIB_SRQ_MAX_WR = 1,\n\tIB_SRQ_LIMIT = 2,\n};\n\nenum ib_srq_type {\n\tIB_SRQT_BASIC = 0,\n\tIB_SRQT_XRC = 1,\n\tIB_SRQT_TM = 2,\n};\n\nenum ib_t10_dif_bg_type {\n\tIB_T10DIF_CRC = 0,\n\tIB_T10DIF_CSUM = 1,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_FLUSH_GLOBAL = 256,\n\tIB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_advise_mr_advice {\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2,\n};\n\nenum ib_uverbs_device_cap_flags {\n\tIB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL,\n\tIB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL,\n\tIB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL,\n\tIB_UVERBS_DEVICE_RAW_MULTI = 8ULL,\n\tIB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL,\n\tIB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL,\n\tIB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL,\n\tIB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL,\n\tIB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL,\n\tIB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL,\n\tIB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL,\n\tIB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL,\n\tIB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL,\n\tIB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL,\n\tIB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL,\n\tIB_UVERBS_DEVICE_XRC = 1048576ULL,\n\tIB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL,\n\tIB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL,\n\tIB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL,\n\tIB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL,\n\tIB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL,\n\tIB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL,\n\tIB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL,\n\tIB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL,\n\tIB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL,\n};\n\nenum ib_uverbs_gid_type {\n\tIB_UVERBS_GID_TYPE_IB = 0,\n\tIB_UVERBS_GID_TYPE_ROCE_V1 = 1,\n\tIB_UVERBS_GID_TYPE_ROCE_V2 = 2,\n};\n\nenum ib_uverbs_odp_general_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT = 1,\n\tIB_UVERBS_ODP_SUPPORT_IMPLICIT = 2,\n};\n\nenum ib_uverbs_odp_transport_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT_SEND = 1,\n\tIB_UVERBS_ODP_SUPPORT_RECV = 2,\n\tIB_UVERBS_ODP_SUPPORT_WRITE = 4,\n\tIB_UVERBS_ODP_SUPPORT_READ = 8,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC = 16,\n\tIB_UVERBS_ODP_SUPPORT_SRQ_RECV = 32,\n\tIB_UVERBS_ODP_SUPPORT_FLUSH = 64,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 128,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_raw_packet_caps {\n\tIB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2,\n\tIB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4,\n\tIB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wc_opcode {\n\tIB_UVERBS_WC_SEND = 0,\n\tIB_UVERBS_WC_RDMA_WRITE = 1,\n\tIB_UVERBS_WC_RDMA_READ = 2,\n\tIB_UVERBS_WC_COMP_SWAP = 3,\n\tIB_UVERBS_WC_FETCH_ADD = 4,\n\tIB_UVERBS_WC_BIND_MW = 5,\n\tIB_UVERBS_WC_LOCAL_INV = 6,\n\tIB_UVERBS_WC_TSO = 7,\n\tIB_UVERBS_WC_FLUSH = 8,\n\tIB_UVERBS_WC_ATOMIC_WRITE = 9,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_UVERBS_WR_FLUSH = 14,\n\tIB_UVERBS_WR_ATOMIC_WRITE = 15,\n};\n\nenum ib_wc_opcode {\n\tIB_WC_SEND = 0,\n\tIB_WC_RDMA_WRITE = 1,\n\tIB_WC_RDMA_READ = 2,\n\tIB_WC_COMP_SWAP = 3,\n\tIB_WC_FETCH_ADD = 4,\n\tIB_WC_BIND_MW = 5,\n\tIB_WC_LOCAL_INV = 6,\n\tIB_WC_LSO = 7,\n\tIB_WC_ATOMIC_WRITE = 9,\n\tIB_WC_REG_MR = 10,\n\tIB_WC_MASKED_COMP_SWAP = 11,\n\tIB_WC_MASKED_FETCH_ADD = 12,\n\tIB_WC_FLUSH = 8,\n\tIB_WC_RECV = 128,\n\tIB_WC_RECV_RDMA_WITH_IMM = 129,\n};\n\nenum ib_wc_status {\n\tIB_WC_SUCCESS = 0,\n\tIB_WC_LOC_LEN_ERR = 1,\n\tIB_WC_LOC_QP_OP_ERR = 2,\n\tIB_WC_LOC_EEC_OP_ERR = 3,\n\tIB_WC_LOC_PROT_ERR = 4,\n\tIB_WC_WR_FLUSH_ERR = 5,\n\tIB_WC_MW_BIND_ERR = 6,\n\tIB_WC_BAD_RESP_ERR = 7,\n\tIB_WC_LOC_ACCESS_ERR = 8,\n\tIB_WC_REM_INV_REQ_ERR = 9,\n\tIB_WC_REM_ACCESS_ERR = 10,\n\tIB_WC_REM_OP_ERR = 11,\n\tIB_WC_RETRY_EXC_ERR = 12,\n\tIB_WC_RNR_RETRY_EXC_ERR = 13,\n\tIB_WC_LOC_RDD_VIOL_ERR = 14,\n\tIB_WC_REM_INV_RD_REQ_ERR = 15,\n\tIB_WC_REM_ABORT_ERR = 16,\n\tIB_WC_INV_EECN_ERR = 17,\n\tIB_WC_INV_EEC_STATE_ERR = 18,\n\tIB_WC_FATAL_ERR = 19,\n\tIB_WC_RESP_TIMEOUT_ERR = 20,\n\tIB_WC_GENERAL_ERR = 21,\n};\n\nenum ib_wq_state {\n\tIB_WQS_RESET = 0,\n\tIB_WQS_RDY = 1,\n\tIB_WQS_ERR = 2,\n};\n\nenum ib_wq_type {\n\tIB_WQT_RQ = 0,\n};\n\nenum ib_wr_opcode {\n\tIB_WR_RDMA_WRITE = 0,\n\tIB_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_WR_SEND = 2,\n\tIB_WR_SEND_WITH_IMM = 3,\n\tIB_WR_RDMA_READ = 4,\n\tIB_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_WR_BIND_MW = 8,\n\tIB_WR_LSO = 10,\n\tIB_WR_SEND_WITH_INV = 9,\n\tIB_WR_RDMA_READ_WITH_INV = 11,\n\tIB_WR_LOCAL_INV = 7,\n\tIB_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_WR_FLUSH = 14,\n\tIB_WR_ATOMIC_WRITE = 15,\n\tIB_WR_REG_MR = 32,\n\tIB_WR_REG_MR_INTEGRITY = 33,\n\tIB_WR_RESERVED1 = 240,\n\tIB_WR_RESERVED2 = 241,\n\tIB_WR_RESERVED3 = 242,\n\tIB_WR_RESERVED4 = 243,\n\tIB_WR_RESERVED5 = 244,\n\tIB_WR_RESERVED6 = 245,\n\tIB_WR_RESERVED7 = 246,\n\tIB_WR_RESERVED8 = 247,\n\tIB_WR_RESERVED9 = 248,\n\tIB_WR_RESERVED10 = 249,\n};\n\nenum id_action {\n\tID_REMOVE = 0,\n\tID_ADD = 1,\n};\n\nenum iio_available_type {\n\tIIO_AVAIL_LIST = 0,\n\tIIO_AVAIL_RANGE = 1,\n};\n\nenum iio_chan_info_enum {\n\tIIO_CHAN_INFO_RAW = 0,\n\tIIO_CHAN_INFO_PROCESSED = 1,\n\tIIO_CHAN_INFO_SCALE = 2,\n\tIIO_CHAN_INFO_OFFSET = 3,\n\tIIO_CHAN_INFO_CALIBSCALE = 4,\n\tIIO_CHAN_INFO_CALIBBIAS = 5,\n\tIIO_CHAN_INFO_PEAK = 6,\n\tIIO_CHAN_INFO_PEAK_SCALE = 7,\n\tIIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW = 8,\n\tIIO_CHAN_INFO_AVERAGE_RAW = 9,\n\tIIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY = 10,\n\tIIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY = 11,\n\tIIO_CHAN_INFO_SAMP_FREQ = 12,\n\tIIO_CHAN_INFO_FREQUENCY = 13,\n\tIIO_CHAN_INFO_PHASE = 14,\n\tIIO_CHAN_INFO_HARDWAREGAIN = 15,\n\tIIO_CHAN_INFO_HYSTERESIS = 16,\n\tIIO_CHAN_INFO_HYSTERESIS_RELATIVE = 17,\n\tIIO_CHAN_INFO_INT_TIME = 18,\n\tIIO_CHAN_INFO_ENABLE = 19,\n\tIIO_CHAN_INFO_CALIBHEIGHT = 20,\n\tIIO_CHAN_INFO_CALIBWEIGHT = 21,\n\tIIO_CHAN_INFO_DEBOUNCE_COUNT = 22,\n\tIIO_CHAN_INFO_DEBOUNCE_TIME = 23,\n\tIIO_CHAN_INFO_CALIBEMISSIVITY = 24,\n\tIIO_CHAN_INFO_OVERSAMPLING_RATIO = 25,\n\tIIO_CHAN_INFO_THERMOCOUPLE_TYPE = 26,\n\tIIO_CHAN_INFO_CALIBAMBIENT = 27,\n\tIIO_CHAN_INFO_ZEROPOINT = 28,\n\tIIO_CHAN_INFO_TROUGH = 29,\n\tIIO_CHAN_INFO_CONVDELAY = 30,\n\tIIO_CHAN_INFO_POWERFACTOR = 31,\n};\n\nenum iio_chan_type {\n\tIIO_VOLTAGE = 0,\n\tIIO_CURRENT = 1,\n\tIIO_POWER = 2,\n\tIIO_ACCEL = 3,\n\tIIO_ANGL_VEL = 4,\n\tIIO_MAGN = 5,\n\tIIO_LIGHT = 6,\n\tIIO_INTENSITY = 7,\n\tIIO_PROXIMITY = 8,\n\tIIO_TEMP = 9,\n\tIIO_INCLI = 10,\n\tIIO_ROT = 11,\n\tIIO_ANGL = 12,\n\tIIO_TIMESTAMP = 13,\n\tIIO_CAPACITANCE = 14,\n\tIIO_ALTVOLTAGE = 15,\n\tIIO_CCT = 16,\n\tIIO_PRESSURE = 17,\n\tIIO_HUMIDITYRELATIVE = 18,\n\tIIO_ACTIVITY = 19,\n\tIIO_STEPS = 20,\n\tIIO_ENERGY = 21,\n\tIIO_DISTANCE = 22,\n\tIIO_VELOCITY = 23,\n\tIIO_CONCENTRATION = 24,\n\tIIO_RESISTANCE = 25,\n\tIIO_PH = 26,\n\tIIO_UVINDEX = 27,\n\tIIO_ELECTRICALCONDUCTIVITY = 28,\n\tIIO_COUNT = 29,\n\tIIO_INDEX = 30,\n\tIIO_GRAVITY = 31,\n\tIIO_POSITIONRELATIVE = 32,\n\tIIO_PHASE = 33,\n\tIIO_MASSCONCENTRATION = 34,\n\tIIO_DELTA_ANGL = 35,\n\tIIO_DELTA_VELOCITY = 36,\n\tIIO_COLORTEMP = 37,\n\tIIO_CHROMATICITY = 38,\n\tIIO_ATTENTION = 39,\n\tIIO_ALTCURRENT = 40,\n};\n\nenum iio_endian {\n\tIIO_CPU = 0,\n\tIIO_BE = 1,\n\tIIO_LE = 2,\n};\n\nenum iio_event_direction {\n\tIIO_EV_DIR_EITHER = 0,\n\tIIO_EV_DIR_RISING = 1,\n\tIIO_EV_DIR_FALLING = 2,\n\tIIO_EV_DIR_NONE = 3,\n\tIIO_EV_DIR_SINGLETAP = 4,\n\tIIO_EV_DIR_DOUBLETAP = 5,\n\tIIO_EV_DIR_FAULT_OPENWIRE = 6,\n};\n\nenum iio_event_info {\n\tIIO_EV_INFO_ENABLE = 0,\n\tIIO_EV_INFO_VALUE = 1,\n\tIIO_EV_INFO_HYSTERESIS = 2,\n\tIIO_EV_INFO_PERIOD = 3,\n\tIIO_EV_INFO_HIGH_PASS_FILTER_3DB = 4,\n\tIIO_EV_INFO_LOW_PASS_FILTER_3DB = 5,\n\tIIO_EV_INFO_TIMEOUT = 6,\n\tIIO_EV_INFO_RESET_TIMEOUT = 7,\n\tIIO_EV_INFO_TAP2_MIN_DELAY = 8,\n\tIIO_EV_INFO_RUNNING_PERIOD = 9,\n\tIIO_EV_INFO_RUNNING_COUNT = 10,\n};\n\nenum iio_event_type {\n\tIIO_EV_TYPE_THRESH = 0,\n\tIIO_EV_TYPE_MAG = 1,\n\tIIO_EV_TYPE_ROC = 2,\n\tIIO_EV_TYPE_THRESH_ADAPTIVE = 3,\n\tIIO_EV_TYPE_MAG_ADAPTIVE = 4,\n\tIIO_EV_TYPE_CHANGE = 5,\n\tIIO_EV_TYPE_MAG_REFERENCED = 6,\n\tIIO_EV_TYPE_GESTURE = 7,\n\tIIO_EV_TYPE_FAULT = 8,\n};\n\nenum iio_modifier {\n\tIIO_NO_MOD = 0,\n\tIIO_MOD_X = 1,\n\tIIO_MOD_Y = 2,\n\tIIO_MOD_Z = 3,\n\tIIO_MOD_X_AND_Y = 4,\n\tIIO_MOD_X_AND_Z = 5,\n\tIIO_MOD_Y_AND_Z = 6,\n\tIIO_MOD_X_AND_Y_AND_Z = 7,\n\tIIO_MOD_X_OR_Y = 8,\n\tIIO_MOD_X_OR_Z = 9,\n\tIIO_MOD_Y_OR_Z = 10,\n\tIIO_MOD_X_OR_Y_OR_Z = 11,\n\tIIO_MOD_LIGHT_BOTH = 12,\n\tIIO_MOD_LIGHT_IR = 13,\n\tIIO_MOD_ROOT_SUM_SQUARED_X_Y = 14,\n\tIIO_MOD_SUM_SQUARED_X_Y_Z = 15,\n\tIIO_MOD_LIGHT_CLEAR = 16,\n\tIIO_MOD_LIGHT_RED = 17,\n\tIIO_MOD_LIGHT_GREEN = 18,\n\tIIO_MOD_LIGHT_BLUE = 19,\n\tIIO_MOD_QUATERNION = 20,\n\tIIO_MOD_TEMP_AMBIENT = 21,\n\tIIO_MOD_TEMP_OBJECT = 22,\n\tIIO_MOD_NORTH_MAGN = 23,\n\tIIO_MOD_NORTH_TRUE = 24,\n\tIIO_MOD_NORTH_MAGN_TILT_COMP = 25,\n\tIIO_MOD_NORTH_TRUE_TILT_COMP = 26,\n\tIIO_MOD_RUNNING = 27,\n\tIIO_MOD_JOGGING = 28,\n\tIIO_MOD_WALKING = 29,\n\tIIO_MOD_STILL = 30,\n\tIIO_MOD_ROOT_SUM_SQUARED_X_Y_Z = 31,\n\tIIO_MOD_I = 32,\n\tIIO_MOD_Q = 33,\n\tIIO_MOD_CO2 = 34,\n\tIIO_MOD_VOC = 35,\n\tIIO_MOD_LIGHT_UV = 36,\n\tIIO_MOD_LIGHT_DUV = 37,\n\tIIO_MOD_PM1 = 38,\n\tIIO_MOD_PM2P5 = 39,\n\tIIO_MOD_PM4 = 40,\n\tIIO_MOD_PM10 = 41,\n\tIIO_MOD_ETHANOL = 42,\n\tIIO_MOD_H2 = 43,\n\tIIO_MOD_O2 = 44,\n\tIIO_MOD_LINEAR_X = 45,\n\tIIO_MOD_LINEAR_Y = 46,\n\tIIO_MOD_LINEAR_Z = 47,\n\tIIO_MOD_PITCH = 48,\n\tIIO_MOD_YAW = 49,\n\tIIO_MOD_ROLL = 50,\n\tIIO_MOD_LIGHT_UVA = 51,\n\tIIO_MOD_LIGHT_UVB = 52,\n\tIIO_MOD_RMS = 53,\n\tIIO_MOD_ACTIVE = 54,\n\tIIO_MOD_REACTIVE = 55,\n\tIIO_MOD_APPARENT = 56,\n};\n\nenum iio_shared_by {\n\tIIO_SEPARATE = 0,\n\tIIO_SHARED_BY_TYPE = 1,\n\tIIO_SHARED_BY_DIR = 2,\n\tIIO_SHARED_BY_ALL = 3,\n};\n\nenum in6_addr_gen_mode {\n\tIN6_ADDR_GEN_MODE_EUI64 = 0,\n\tIN6_ADDR_GEN_MODE_NONE = 1,\n\tIN6_ADDR_GEN_MODE_STABLE_PRIVACY = 2,\n\tIN6_ADDR_GEN_MODE_RANDOM = 3,\n};\n\nenum inband_type {\n\tINBAND_NONE = 0,\n\tINBAND_CISCO_SGMII = 1,\n\tINBAND_BASEX = 2,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioam6_event_attr {\n\tIOAM6_EVENT_ATTR_UNSPEC = 0,\n\tIOAM6_EVENT_ATTR_TRACE_NAMESPACE = 1,\n\tIOAM6_EVENT_ATTR_TRACE_NODELEN = 2,\n\tIOAM6_EVENT_ATTR_TRACE_TYPE = 3,\n\tIOAM6_EVENT_ATTR_TRACE_DATA = 4,\n\t__IOAM6_EVENT_ATTR_MAX = 5,\n};\n\nenum ioam6_event_type {\n\tIOAM6_EVENT_UNSPEC = 0,\n\tIOAM6_EVENT_TRACE = 1,\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_NOEXEC = 1,\n\tIOMMU_CAP_PRE_BOOT_PROTECTION = 2,\n\tIOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3,\n\tIOMMU_CAP_DEFERRED_FLUSH = 4,\n\tIOMMU_CAP_DIRTY_TRACKING = 5,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum iommu_hw_info_type {\n\tIOMMU_HW_INFO_TYPE_NONE = 0,\n\tIOMMU_HW_INFO_TYPE_DEFAULT = 0,\n\tIOMMU_HW_INFO_TYPE_INTEL_VTD = 1,\n\tIOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,\n\tIOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,\n\tIOMMU_HW_INFO_TYPE_AMD = 4,\n};\n\nenum iommu_hw_queue_type {\n\tIOMMU_HW_QUEUE_TYPE_DEFAULT = 0,\n\tIOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,\n};\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nenum iommu_viommu_type {\n\tIOMMU_VIOMMU_TYPE_DEFAULT = 0,\n\tIOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,\n\tIOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,\n};\n\nenum iommufd_hwpt_alloc_flags {\n\tIOMMU_HWPT_ALLOC_NEST_PARENT = 1,\n\tIOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2,\n\tIOMMU_HWPT_FAULT_ID_VALID = 4,\n\tIOMMU_HWPT_ALLOC_PASID = 8,\n};\n\nenum iommufd_object_type {\n\tIOMMUFD_OBJ_NONE = 0,\n\tIOMMUFD_OBJ_ANY = 0,\n\tIOMMUFD_OBJ_DEVICE = 1,\n\tIOMMUFD_OBJ_HWPT_PAGING = 2,\n\tIOMMUFD_OBJ_HWPT_NESTED = 3,\n\tIOMMUFD_OBJ_IOAS = 4,\n\tIOMMUFD_OBJ_ACCESS = 5,\n\tIOMMUFD_OBJ_FAULT = 6,\n\tIOMMUFD_OBJ_VIOMMU = 7,\n\tIOMMUFD_OBJ_VDEVICE = 8,\n\tIOMMUFD_OBJ_VEVENTQ = 9,\n\tIOMMUFD_OBJ_HW_QUEUE = 10,\n\tIOMMUFD_OBJ_MAX = 11,\n};\n\nenum ip6_defrag_users {\n\tIP6_DEFRAG_LOCAL_DELIVER = 0,\n\tIP6_DEFRAG_CONNTRACK_IN = 1,\n\t__IP6_DEFRAG_CONNTRACK_IN = 65536,\n\tIP6_DEFRAG_CONNTRACK_OUT = 65537,\n\t__IP6_DEFRAG_CONNTRACK_OUT = 131072,\n\tIP6_DEFRAG_CONNTRACK_BRIDGE_IN = 131073,\n\t__IP6_DEFRAG_CONNTRACK_BRIDGE_IN = 196608,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_conntrack_info {\n\tIP_CT_ESTABLISHED = 0,\n\tIP_CT_RELATED = 1,\n\tIP_CT_NEW = 2,\n\tIP_CT_IS_REPLY = 3,\n\tIP_CT_ESTABLISHED_REPLY = 3,\n\tIP_CT_RELATED_REPLY = 4,\n\tIP_CT_NUMBER = 5,\n\tIP_CT_UNTRACKED = 7,\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum ipi_message_type {\n\tIPI_RESCHEDULE = 0,\n\tIPI_CALL_FUNC = 1,\n\tIPI_CPU_STOP = 2,\n\tIPI_CPU_CRASH_STOP = 3,\n\tIPI_IRQ_WORK = 4,\n\tIPI_TIMER = 5,\n\tIPI_CPU_BACKTRACE = 6,\n\tIPI_KGDB_ROUNDUP = 7,\n\tIPI_MAX = 8,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum isofs_file_format {\n\tisofs_file_normal = 0,\n\tisofs_file_sparse = 1,\n\tisofs_file_compressed = 2,\n};\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum jbd2_shrink_type {\n\tJBD2_SHRINK_DESTROY = 0,\n\tJBD2_SHRINK_BUSY_STOP = 1,\n\tJBD2_SHRINK_BUSY_SKIP = 2,\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 17,\n\tBH_JWrite = 18,\n\tBH_Freed = 19,\n\tBH_Revoked = 20,\n\tBH_RevokeValid = 21,\n\tBH_JBDDirty = 22,\n\tBH_JournalHead = 23,\n\tBH_Shadow = 24,\n\tBH_Verified = 25,\n\tBH_JBDPrivateStart = 26,\n};\n\nenum jh7110_pll_mode {\n\tJH7110_PLL_MODE_FRACTION = 0,\n\tJH7110_PLL_MODE_INTEGER = 1,\n};\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nenum k230_rst_type {\n\tRST_TYPE_CPU0 = 0,\n\tRST_TYPE_CPU1 = 1,\n\tRST_TYPE_FLUSH = 2,\n\tRST_TYPE_HW_DONE = 3,\n\tRST_TYPE_SW_DONE = 4,\n};\n\nenum kcmp_type {\n\tKCMP_FILE = 0,\n\tKCMP_VM = 1,\n\tKCMP_FILES = 2,\n\tKCMP_FS = 3,\n\tKCMP_SIGHAND = 4,\n\tKCMP_IO = 5,\n\tKCMP_SYSVSEM = 6,\n\tKCMP_EPOLL_TFD = 7,\n\tKCMP_TYPES = 8,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_DMA = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_CGROUP = 2,\n\tNR_KMALLOC_TYPES = 3,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum l3mdev_type {\n\tL3MDEV_TYPE_UNSPEC = 0,\n\tL3MDEV_TYPE_VRF = 1,\n\t__L3MDEV_TYPE_MAX = 2,\n};\n\nenum label_flags {\n\tFLAG_HAT = 1,\n\tFLAG_UNCONFINED = 2,\n\tFLAG_NULL = 4,\n\tFLAG_IX_ON_NAME_ERROR = 8,\n\tFLAG_IMMUTIBLE = 16,\n\tFLAG_USER_DEFINED = 32,\n\tFLAG_NO_LIST_REF = 64,\n\tFLAG_NS_COUNT = 128,\n\tFLAG_IN_TREE = 256,\n\tFLAG_PROFILE = 512,\n\tFLAG_EXPLICIT = 1024,\n\tFLAG_STALE = 2048,\n\tFLAG_RENAMED = 4096,\n\tFLAG_REVOKED = 8192,\n\tFLAG_DEBUG1 = 16384,\n\tFLAG_DEBUG2 = 32768,\n};\n\nenum label_initialized {\n\tLABEL_INVALID = 0,\n\tLABEL_INITIALIZED = 1,\n\tLABEL_PENDING = 2,\n};\n\nenum latency_range {\n\tlowest_latency = 0,\n\tlow_latency = 1,\n\tbulk_latency = 2,\n\tlatency_invalid = 255,\n};\n\nenum layoutdriver_policy_flags {\n\tPNFS_LAYOUTRET_ON_SETATTR = 1,\n\tPNFS_LAYOUTRET_ON_ERROR = 2,\n\tPNFS_READ_WHOLE_PAGE = 4,\n\tPNFS_LAYOUTGET_ON_OPEN = 8,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum led_trigger_netdev_modes {\n\tTRIGGER_NETDEV_LINK = 0,\n\tTRIGGER_NETDEV_LINK_10 = 1,\n\tTRIGGER_NETDEV_LINK_100 = 2,\n\tTRIGGER_NETDEV_LINK_1000 = 3,\n\tTRIGGER_NETDEV_LINK_2500 = 4,\n\tTRIGGER_NETDEV_LINK_5000 = 5,\n\tTRIGGER_NETDEV_LINK_10000 = 6,\n\tTRIGGER_NETDEV_HALF_DUPLEX = 7,\n\tTRIGGER_NETDEV_FULL_DUPLEX = 8,\n\tTRIGGER_NETDEV_TX = 9,\n\tTRIGGER_NETDEV_RX = 10,\n\tTRIGGER_NETDEV_TX_ERR = 11,\n\tTRIGGER_NETDEV_RX_ERR = 12,\n\t__TRIGGER_NETDEV_MAX = 13,\n};\n\nenum limit_by4 {\n\tNFS4_LIMIT_SIZE = 1,\n\tNFS4_LIMIT_BLOCKS = 2,\n};\n\nenum link_inband_signalling {\n\tLINK_INBAND_DISABLE = 1,\n\tLINK_INBAND_ENABLE = 2,\n\tLINK_INBAND_BYPASS = 4,\n};\n\nenum lock_type4 {\n\tNFS4_UNLOCK_LT = 0,\n\tNFS4_READ_LT = 1,\n\tNFS4_WRITE_LT = 2,\n\tNFS4_READW_LT = 3,\n\tNFS4_WRITEW_LT = 4,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum log_ent_request {\n\tLOG_NEW_ENT = 0,\n\tLOG_OLD_ENT = 1,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lsm_event {\n\tLSM_POLICY_CHANGE = 0,\n\tLSM_STARTED_ALL = 1,\n};\n\nenum lsm_integrity_type {\n\tLSM_INT_DMVERITY_SIG_VALID = 0,\n\tLSM_INT_DMVERITY_ROOTHASH = 1,\n\tLSM_INT_FSVERITY_BUILTINSIG_VALID = 2,\n};\n\nenum lsm_order {\n\tLSM_ORDER_FIRST = -1,\n\tLSM_ORDER_MUTABLE = 0,\n\tLSM_ORDER_LAST = 1,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum mac_version {\n\tRTL_GIGA_MAC_VER_02 = 0,\n\tRTL_GIGA_MAC_VER_03 = 1,\n\tRTL_GIGA_MAC_VER_04 = 2,\n\tRTL_GIGA_MAC_VER_05 = 3,\n\tRTL_GIGA_MAC_VER_06 = 4,\n\tRTL_GIGA_MAC_VER_07 = 5,\n\tRTL_GIGA_MAC_VER_08 = 6,\n\tRTL_GIGA_MAC_VER_09 = 7,\n\tRTL_GIGA_MAC_VER_10 = 8,\n\tRTL_GIGA_MAC_VER_14 = 9,\n\tRTL_GIGA_MAC_VER_17 = 10,\n\tRTL_GIGA_MAC_VER_18 = 11,\n\tRTL_GIGA_MAC_VER_19 = 12,\n\tRTL_GIGA_MAC_VER_20 = 13,\n\tRTL_GIGA_MAC_VER_21 = 14,\n\tRTL_GIGA_MAC_VER_22 = 15,\n\tRTL_GIGA_MAC_VER_23 = 16,\n\tRTL_GIGA_MAC_VER_24 = 17,\n\tRTL_GIGA_MAC_VER_25 = 18,\n\tRTL_GIGA_MAC_VER_26 = 19,\n\tRTL_GIGA_MAC_VER_28 = 20,\n\tRTL_GIGA_MAC_VER_29 = 21,\n\tRTL_GIGA_MAC_VER_30 = 22,\n\tRTL_GIGA_MAC_VER_31 = 23,\n\tRTL_GIGA_MAC_VER_32 = 24,\n\tRTL_GIGA_MAC_VER_33 = 25,\n\tRTL_GIGA_MAC_VER_34 = 26,\n\tRTL_GIGA_MAC_VER_35 = 27,\n\tRTL_GIGA_MAC_VER_36 = 28,\n\tRTL_GIGA_MAC_VER_37 = 29,\n\tRTL_GIGA_MAC_VER_38 = 30,\n\tRTL_GIGA_MAC_VER_39 = 31,\n\tRTL_GIGA_MAC_VER_40 = 32,\n\tRTL_GIGA_MAC_VER_42 = 33,\n\tRTL_GIGA_MAC_VER_43 = 34,\n\tRTL_GIGA_MAC_VER_44 = 35,\n\tRTL_GIGA_MAC_VER_46 = 36,\n\tRTL_GIGA_MAC_VER_48 = 37,\n\tRTL_GIGA_MAC_VER_51 = 38,\n\tRTL_GIGA_MAC_VER_52 = 39,\n\tRTL_GIGA_MAC_VER_61 = 40,\n\tRTL_GIGA_MAC_VER_63 = 41,\n\tRTL_GIGA_MAC_VER_64 = 42,\n\tRTL_GIGA_MAC_VER_66 = 43,\n\tRTL_GIGA_MAC_VER_70 = 44,\n\tRTL_GIGA_MAC_VER_80 = 45,\n\tRTL_GIGA_MAC_NONE = 46,\n\tRTL_GIGA_MAC_VER_LAST = 45,\n\tRTL_GIGA_MAC_VER_EXTENDED = 46,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum mctrl_gpio_idx {\n\tUART_GPIO_CTS = 0,\n\tUART_GPIO_DSR = 1,\n\tUART_GPIO_DCD = 2,\n\tUART_GPIO_RNG = 3,\n\tUART_GPIO_RI = 3,\n\tUART_GPIO_RTS = 4,\n\tUART_GPIO_DTR = 5,\n\tUART_GPIO_MAX = 6,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 51,\n\tMEMCG_SOCK = 52,\n\tMEMCG_PERCPU_B = 53,\n\tMEMCG_VMALLOC = 54,\n\tMEMCG_KMEM = 55,\n\tMEMCG_ZSWAP_B = 56,\n\tMEMCG_ZSWAPPED = 57,\n\tMEMCG_NR_STAT = 58,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mext_move_type {\n\tMEXT_SKIP_EXTENT = 0,\n\tMEXT_MOVE_EXTENT = 1,\n\tMEXT_COPY_DATA = 2,\n};\n\nenum mf_flags {\n\tMF_COUNT_INCREASED = 1,\n\tMF_ACTION_REQUIRED = 2,\n\tMF_MUST_KILL = 4,\n\tMF_SOFT_OFFLINE = 8,\n\tMF_UNPOISON = 16,\n\tMF_SW_SIMULATED = 32,\n\tMF_NO_RETRY = 64,\n\tMF_MEM_PRE_REMOVE = 128,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\t__MIGRATE_TYPE_END = 3,\n\tMIGRATE_TYPES = 4,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum mipi_dsi_compression_algo {\n\tMIPI_DSI_COMPRESSION_DSC = 0,\n\tMIPI_DSI_COMPRESSION_VENDOR = 3,\n};\n\nenum mipi_dsi_dcs_tear_mode {\n\tMIPI_DSI_DCS_TEAR_MODE_VBLANK = 0,\n\tMIPI_DSI_DCS_TEAR_MODE_VHBLANK = 1,\n};\n\nenum mipi_dsi_pixel_format {\n\tMIPI_DSI_FMT_RGB888 = 0,\n\tMIPI_DSI_FMT_RGB666 = 1,\n\tMIPI_DSI_FMT_RGB666_PACKED = 2,\n\tMIPI_DSI_FMT_RGB565 = 3,\n};\n\nenum misaligned_access_type {\n\tMISALIGNED_STORE = 0,\n\tMISALIGNED_LOAD = 1,\n};\n\nenum mitigation_state {\n\tUNAFFECTED = 0,\n\tMITIGATED = 1,\n\tVULNERABLE = 2,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mmc_busy_cmd {\n\tMMC_BUSY_CMD6 = 0,\n\tMMC_BUSY_ERASE = 1,\n\tMMC_BUSY_HPI = 2,\n\tMMC_BUSY_EXTR_SINGLE = 3,\n\tMMC_BUSY_IO = 4,\n};\n\nenum mmc_drv_op {\n\tMMC_DRV_OP_IOCTL = 0,\n\tMMC_DRV_OP_IOCTL_RPMB = 1,\n\tMMC_DRV_OP_BOOT_WP = 2,\n\tMMC_DRV_OP_GET_CARD_STATUS = 3,\n\tMMC_DRV_OP_GET_EXT_CSD = 4,\n};\n\nenum mmc_err_stat {\n\tMMC_ERR_CMD_TIMEOUT = 0,\n\tMMC_ERR_CMD_CRC = 1,\n\tMMC_ERR_DAT_TIMEOUT = 2,\n\tMMC_ERR_DAT_CRC = 3,\n\tMMC_ERR_AUTO_CMD = 4,\n\tMMC_ERR_ADMA = 5,\n\tMMC_ERR_TUNING = 6,\n\tMMC_ERR_CMDQ_RED = 7,\n\tMMC_ERR_CMDQ_GCE = 8,\n\tMMC_ERR_CMDQ_ICCE = 9,\n\tMMC_ERR_REQ_TIMEOUT = 10,\n\tMMC_ERR_CMDQ_REQ_TIMEOUT = 11,\n\tMMC_ERR_ICE_CFG = 12,\n\tMMC_ERR_CTRL_TIMEOUT = 13,\n\tMMC_ERR_UNEXPECTED_IRQ = 14,\n\tMMC_ERR_MAX = 15,\n};\n\nenum mmc_issue_type {\n\tMMC_ISSUE_SYNC = 0,\n\tMMC_ISSUE_DCMD = 1,\n\tMMC_ISSUE_ASYNC = 2,\n\tMMC_ISSUE_MAX = 3,\n};\n\nenum mmc_issued {\n\tMMC_REQ_STARTED = 0,\n\tMMC_REQ_BUSY = 1,\n\tMMC_REQ_FAILED_TO_START = 2,\n\tMMC_REQ_FINISHED = 3,\n};\n\nenum mmc_poweroff_type {\n\tMMC_POWEROFF_SUSPEND = 0,\n\tMMC_POWEROFF_SHUTDOWN = 1,\n\tMMC_POWEROFF_UNDERVOLTAGE = 2,\n\tMMC_POWEROFF_UNBIND = 3,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mmu_notifier_event {\n\tMMU_NOTIFY_UNMAP = 0,\n\tMMU_NOTIFY_CLEAR = 1,\n\tMMU_NOTIFY_PROTECTION_VMA = 2,\n\tMMU_NOTIFY_PROTECTION_PAGE = 3,\n\tMMU_NOTIFY_SOFT_DIRTY = 4,\n\tMMU_NOTIFY_RELEASE = 5,\n\tMMU_NOTIFY_MIGRATE = 6,\n\tMMU_NOTIFY_EXCLUSIVE = 7,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mountstat {\n\tMNT_OK = 0,\n\tMNT_EPERM = 1,\n\tMNT_ENOENT = 2,\n\tMNT_EACCES = 13,\n\tMNT_EINVAL = 22,\n};\n\nenum mountstat3 {\n\tMNT3_OK = 0,\n\tMNT3ERR_PERM = 1,\n\tMNT3ERR_NOENT = 2,\n\tMNT3ERR_IO = 5,\n\tMNT3ERR_ACCES = 13,\n\tMNT3ERR_NOTDIR = 20,\n\tMNT3ERR_INVAL = 22,\n\tMNT3ERR_NAMETOOLONG = 63,\n\tMNT3ERR_NOTSUPP = 10004,\n\tMNT3ERR_SERVERFAULT = 10006,\n};\n\nenum mousedev_emul {\n\tMOUSEDEV_EMUL_PS2 = 0,\n\tMOUSEDEV_EMUL_IMPS = 1,\n\tMOUSEDEV_EMUL_EXPS = 2,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum mtd_file_modes {\n\tMTD_FILE_MODE_NORMAL = 0,\n\tMTD_FILE_MODE_OTP_FACTORY = 1,\n\tMTD_FILE_MODE_OTP_USER = 2,\n\tMTD_FILE_MODE_RAW = 3,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum napot_cont_order {\n\tNAPOT_CONT64KB_ORDER = 4,\n\tNAPOT_ORDER_MAX = 5,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum nd_async_mode {\n\tND_SYNC = 0,\n\tND_ASYNC = 1,\n};\n\nenum nd_driver_flags {\n\tND_DRIVER_DIMM = 2,\n\tND_DRIVER_REGION_PMEM = 4,\n\tND_DRIVER_REGION_BLK = 8,\n\tND_DRIVER_NAMESPACE_IO = 16,\n\tND_DRIVER_NAMESPACE_PMEM = 32,\n\tND_DRIVER_DAX_PMEM = 128,\n};\n\nenum nd_ioctl_mode {\n\tBUS_IOCTL = 0,\n\tDIMM_IOCTL = 1,\n};\n\nenum nd_label_flags {\n\tND_LABEL_REAP = 0,\n};\n\nenum nd_pfn_mode {\n\tPFN_MODE_NONE = 0,\n\tPFN_MODE_RAM = 1,\n\tPFN_MODE_PMEM = 2,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum net_xmit_qdisc_t {\n\t__NET_XMIT_STOLEN = 65536,\n\t__NET_XMIT_BYPASS = 131072,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_lag_hash {\n\tNETDEV_LAG_HASH_NONE = 0,\n\tNETDEV_LAG_HASH_L2 = 1,\n\tNETDEV_LAG_HASH_L34 = 2,\n\tNETDEV_LAG_HASH_L23 = 3,\n\tNETDEV_LAG_HASH_E23 = 4,\n\tNETDEV_LAG_HASH_E34 = 5,\n\tNETDEV_LAG_HASH_VLAN_SRCMAC = 6,\n\tNETDEV_LAG_HASH_UNKNOWN = 7,\n};\n\nenum netdev_lag_tx_type {\n\tNETDEV_LAG_TX_TYPE_UNKNOWN = 0,\n\tNETDEV_LAG_TX_TYPE_RANDOM = 1,\n\tNETDEV_LAG_TX_TYPE_BROADCAST = 2,\n\tNETDEV_LAG_TX_TYPE_ROUNDROBIN = 3,\n\tNETDEV_LAG_TX_TYPE_ACTIVEBACKUP = 4,\n\tNETDEV_LAG_TX_TYPE_HASH = 5,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netfs_collect_contig_trace {\n\tnetfs_contig_trace_collect = 0,\n\tnetfs_contig_trace_jump = 1,\n\tnetfs_contig_trace_unlock = 2,\n} __attribute__((mode(byte)));\n\nenum netfs_donate_trace {\n\tnetfs_trace_donate_tail_to_prev = 0,\n\tnetfs_trace_donate_to_prev = 1,\n\tnetfs_trace_donate_to_next = 2,\n\tnetfs_trace_donate_to_deferred_next = 3,\n} __attribute__((mode(byte)));\n\nenum netfs_failure {\n\tnetfs_fail_check_write_begin = 0,\n\tnetfs_fail_copy_to_cache = 1,\n\tnetfs_fail_dio_read_short = 2,\n\tnetfs_fail_dio_read_zero = 3,\n\tnetfs_fail_read = 4,\n\tnetfs_fail_short_read = 5,\n\tnetfs_fail_prepare_write = 6,\n\tnetfs_fail_write = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_folio_trace {\n\tnetfs_folio_is_uptodate = 0,\n\tnetfs_just_prefetch = 1,\n\tnetfs_whole_folio_modify = 2,\n\tnetfs_modify_and_clear = 3,\n\tnetfs_streaming_write = 4,\n\tnetfs_streaming_write_cont = 5,\n\tnetfs_flush_content = 6,\n\tnetfs_streaming_filled_page = 7,\n\tnetfs_streaming_cont_filled_page = 8,\n\tnetfs_folio_trace_abandon = 9,\n\tnetfs_folio_trace_alloc_buffer = 10,\n\tnetfs_folio_trace_cancel_copy = 11,\n\tnetfs_folio_trace_cancel_store = 12,\n\tnetfs_folio_trace_clear = 13,\n\tnetfs_folio_trace_clear_cc = 14,\n\tnetfs_folio_trace_clear_g = 15,\n\tnetfs_folio_trace_clear_s = 16,\n\tnetfs_folio_trace_copy_to_cache = 17,\n\tnetfs_folio_trace_end_copy = 18,\n\tnetfs_folio_trace_filled_gaps = 19,\n\tnetfs_folio_trace_kill = 20,\n\tnetfs_folio_trace_kill_cc = 21,\n\tnetfs_folio_trace_kill_g = 22,\n\tnetfs_folio_trace_kill_s = 23,\n\tnetfs_folio_trace_mkwrite = 24,\n\tnetfs_folio_trace_mkwrite_plus = 25,\n\tnetfs_folio_trace_not_under_wback = 26,\n\tnetfs_folio_trace_not_locked = 27,\n\tnetfs_folio_trace_put = 28,\n\tnetfs_folio_trace_read = 29,\n\tnetfs_folio_trace_read_done = 30,\n\tnetfs_folio_trace_read_gaps = 31,\n\tnetfs_folio_trace_read_unlock = 32,\n\tnetfs_folio_trace_redirtied = 33,\n\tnetfs_folio_trace_store = 34,\n\tnetfs_folio_trace_store_copy = 35,\n\tnetfs_folio_trace_store_plus = 36,\n\tnetfs_folio_trace_wthru = 37,\n\tnetfs_folio_trace_wthru_plus = 38,\n} __attribute__((mode(byte)));\n\nenum netfs_folioq_trace {\n\tnetfs_trace_folioq_alloc_buffer = 0,\n\tnetfs_trace_folioq_clear = 1,\n\tnetfs_trace_folioq_delete = 2,\n\tnetfs_trace_folioq_make_space = 3,\n\tnetfs_trace_folioq_rollbuf_init = 4,\n\tnetfs_trace_folioq_read_progress = 5,\n} __attribute__((mode(byte)));\n\nenum netfs_io_origin {\n\tNETFS_READAHEAD = 0,\n\tNETFS_READPAGE = 1,\n\tNETFS_READ_GAPS = 2,\n\tNETFS_READ_SINGLE = 3,\n\tNETFS_READ_FOR_WRITE = 4,\n\tNETFS_UNBUFFERED_READ = 5,\n\tNETFS_DIO_READ = 6,\n\tNETFS_WRITEBACK = 7,\n\tNETFS_WRITEBACK_SINGLE = 8,\n\tNETFS_WRITETHROUGH = 9,\n\tNETFS_UNBUFFERED_WRITE = 10,\n\tNETFS_DIO_WRITE = 11,\n\tNETFS_PGPRIV2_COPY_TO_CACHE = 12,\n\tnr__netfs_io_origin = 13,\n} __attribute__((mode(byte)));\n\nenum netfs_io_source {\n\tNETFS_SOURCE_UNKNOWN = 0,\n\tNETFS_FILL_WITH_ZEROES = 1,\n\tNETFS_DOWNLOAD_FROM_SERVER = 2,\n\tNETFS_READ_FROM_CACHE = 3,\n\tNETFS_INVALID_READ = 4,\n\tNETFS_UPLOAD_TO_SERVER = 5,\n\tNETFS_WRITE_TO_CACHE = 6,\n} __attribute__((mode(byte)));\n\nenum netfs_read_from_hole {\n\tNETFS_READ_HOLE_IGNORE = 0,\n\tNETFS_READ_HOLE_FAIL = 1,\n};\n\nenum netfs_read_trace {\n\tnetfs_read_trace_dio_read = 0,\n\tnetfs_read_trace_expanded = 1,\n\tnetfs_read_trace_readahead = 2,\n\tnetfs_read_trace_readpage = 3,\n\tnetfs_read_trace_read_gaps = 4,\n\tnetfs_read_trace_read_single = 5,\n\tnetfs_read_trace_prefetch_for_write = 6,\n\tnetfs_read_trace_write_begin = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_ref_trace {\n\tnetfs_rreq_trace_get_for_outstanding = 0,\n\tnetfs_rreq_trace_get_subreq = 1,\n\tnetfs_rreq_trace_put_complete = 2,\n\tnetfs_rreq_trace_put_discard = 3,\n\tnetfs_rreq_trace_put_failed = 4,\n\tnetfs_rreq_trace_put_no_submit = 5,\n\tnetfs_rreq_trace_put_return = 6,\n\tnetfs_rreq_trace_put_subreq = 7,\n\tnetfs_rreq_trace_put_work_ip = 8,\n\tnetfs_rreq_trace_see_work = 9,\n\tnetfs_rreq_trace_see_work_complete = 10,\n\tnetfs_rreq_trace_new = 11,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_trace {\n\tnetfs_rreq_trace_assess = 0,\n\tnetfs_rreq_trace_collect = 1,\n\tnetfs_rreq_trace_complete = 2,\n\tnetfs_rreq_trace_copy = 3,\n\tnetfs_rreq_trace_dirty = 4,\n\tnetfs_rreq_trace_done = 5,\n\tnetfs_rreq_trace_end_copy_to_cache = 6,\n\tnetfs_rreq_trace_free = 7,\n\tnetfs_rreq_trace_intr = 8,\n\tnetfs_rreq_trace_ki_complete = 9,\n\tnetfs_rreq_trace_recollect = 10,\n\tnetfs_rreq_trace_redirty = 11,\n\tnetfs_rreq_trace_resubmit = 12,\n\tnetfs_rreq_trace_set_abandon = 13,\n\tnetfs_rreq_trace_set_pause = 14,\n\tnetfs_rreq_trace_unlock = 15,\n\tnetfs_rreq_trace_unlock_pgpriv2 = 16,\n\tnetfs_rreq_trace_unmark = 17,\n\tnetfs_rreq_trace_unpause = 18,\n\tnetfs_rreq_trace_wait_ip = 19,\n\tnetfs_rreq_trace_wait_pause = 20,\n\tnetfs_rreq_trace_wait_quiesce = 21,\n\tnetfs_rreq_trace_waited_ip = 22,\n\tnetfs_rreq_trace_waited_pause = 23,\n\tnetfs_rreq_trace_waited_quiesce = 24,\n\tnetfs_rreq_trace_wake_ip = 25,\n\tnetfs_rreq_trace_wake_queue = 26,\n\tnetfs_rreq_trace_write_done = 27,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_ref_trace {\n\tnetfs_sreq_trace_get_copy_to_cache = 0,\n\tnetfs_sreq_trace_get_resubmit = 1,\n\tnetfs_sreq_trace_get_submit = 2,\n\tnetfs_sreq_trace_get_short_read = 3,\n\tnetfs_sreq_trace_new = 4,\n\tnetfs_sreq_trace_put_abandon = 5,\n\tnetfs_sreq_trace_put_cancel = 6,\n\tnetfs_sreq_trace_put_clear = 7,\n\tnetfs_sreq_trace_put_consumed = 8,\n\tnetfs_sreq_trace_put_done = 9,\n\tnetfs_sreq_trace_put_failed = 10,\n\tnetfs_sreq_trace_put_merged = 11,\n\tnetfs_sreq_trace_put_no_copy = 12,\n\tnetfs_sreq_trace_put_oom = 13,\n\tnetfs_sreq_trace_put_wip = 14,\n\tnetfs_sreq_trace_put_work = 15,\n\tnetfs_sreq_trace_put_terminated = 16,\n\tnetfs_sreq_trace_see_failed = 17,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_trace {\n\tnetfs_sreq_trace_abandoned = 0,\n\tnetfs_sreq_trace_add_donations = 1,\n\tnetfs_sreq_trace_added = 2,\n\tnetfs_sreq_trace_cache_nowrite = 3,\n\tnetfs_sreq_trace_cache_prepare = 4,\n\tnetfs_sreq_trace_cache_write = 5,\n\tnetfs_sreq_trace_cancel = 6,\n\tnetfs_sreq_trace_clear = 7,\n\tnetfs_sreq_trace_consumed = 8,\n\tnetfs_sreq_trace_discard = 9,\n\tnetfs_sreq_trace_donate_to_prev = 10,\n\tnetfs_sreq_trace_donate_to_next = 11,\n\tnetfs_sreq_trace_download_instead = 12,\n\tnetfs_sreq_trace_fail = 13,\n\tnetfs_sreq_trace_free = 14,\n\tnetfs_sreq_trace_hit_eof = 15,\n\tnetfs_sreq_trace_io_bad = 16,\n\tnetfs_sreq_trace_io_malformed = 17,\n\tnetfs_sreq_trace_io_unknown = 18,\n\tnetfs_sreq_trace_io_progress = 19,\n\tnetfs_sreq_trace_io_req_submitted = 20,\n\tnetfs_sreq_trace_io_retry_needed = 21,\n\tnetfs_sreq_trace_limited = 22,\n\tnetfs_sreq_trace_need_clear = 23,\n\tnetfs_sreq_trace_partial_read = 24,\n\tnetfs_sreq_trace_need_retry = 25,\n\tnetfs_sreq_trace_prepare = 26,\n\tnetfs_sreq_trace_prep_failed = 27,\n\tnetfs_sreq_trace_progress = 28,\n\tnetfs_sreq_trace_reprep_failed = 29,\n\tnetfs_sreq_trace_retry = 30,\n\tnetfs_sreq_trace_short = 31,\n\tnetfs_sreq_trace_split = 32,\n\tnetfs_sreq_trace_submit = 33,\n\tnetfs_sreq_trace_superfluous = 34,\n\tnetfs_sreq_trace_terminated = 35,\n\tnetfs_sreq_trace_wait_for = 36,\n\tnetfs_sreq_trace_write = 37,\n\tnetfs_sreq_trace_write_skip = 38,\n\tnetfs_sreq_trace_write_term = 39,\n} __attribute__((mode(byte)));\n\nenum netfs_write_trace {\n\tnetfs_write_trace_copy_to_cache = 0,\n\tnetfs_write_trace_dio_write = 1,\n\tnetfs_write_trace_unbuffered_write = 2,\n\tnetfs_write_trace_writeback = 3,\n\tnetfs_write_trace_writeback_single = 4,\n\tnetfs_write_trace_writethrough = 5,\n} __attribute__((mode(byte)));\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netloc_type4 {\n\tNL4_NAME = 1,\n\tNL4_URL = 2,\n\tNL4_NETADDR = 3,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_ct_ext_id {\n\tNF_CT_EXT_HELPER = 0,\n\tNF_CT_EXT_SEQADJ = 1,\n\tNF_CT_EXT_ACCT = 2,\n\tNF_CT_EXT_NUM = 3,\n};\n\nenum nf_dev_hooks {\n\tNF_NETDEV_INGRESS = 0,\n\tNF_NETDEV_EGRESS = 1,\n\tNF_NETDEV_NUMHOOKS = 2,\n};\n\nenum nf_hook_ops_type {\n\tNF_HOOK_OP_UNDEFINED = 0,\n\tNF_HOOK_OP_NF_TABLES = 1,\n\tNF_HOOK_OP_BPF = 2,\n\tNF_HOOK_OP_NFT_FT = 3,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nf_ip6_hook_priorities {\n\tNF_IP6_PRI_FIRST = -2147483648,\n\tNF_IP6_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP6_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP6_PRI_RAW = -300,\n\tNF_IP6_PRI_SELINUX_FIRST = -225,\n\tNF_IP6_PRI_CONNTRACK = -200,\n\tNF_IP6_PRI_MANGLE = -150,\n\tNF_IP6_PRI_NAT_DST = -100,\n\tNF_IP6_PRI_FILTER = 0,\n\tNF_IP6_PRI_SECURITY = 50,\n\tNF_IP6_PRI_NAT_SRC = 100,\n\tNF_IP6_PRI_SELINUX_LAST = 225,\n\tNF_IP6_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP6_PRI_LAST = 2147483647,\n};\n\nenum nf_ip_hook_priorities {\n\tNF_IP_PRI_FIRST = -2147483648,\n\tNF_IP_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP_PRI_RAW = -300,\n\tNF_IP_PRI_SELINUX_FIRST = -225,\n\tNF_IP_PRI_CONNTRACK = -200,\n\tNF_IP_PRI_MANGLE = -150,\n\tNF_IP_PRI_NAT_DST = -100,\n\tNF_IP_PRI_FILTER = 0,\n\tNF_IP_PRI_SECURITY = 50,\n\tNF_IP_PRI_NAT_SRC = 100,\n\tNF_IP_PRI_SELINUX_LAST = 225,\n\tNF_IP_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP_PRI_CONNTRACK_CONFIRM = 2147483647,\n\tNF_IP_PRI_LAST = 2147483647,\n};\n\nenum nf_log_type {\n\tNF_LOG_TYPE_LOG = 0,\n\tNF_LOG_TYPE_ULOG = 1,\n\tNF_LOG_TYPE_MAX = 2,\n};\n\nenum nf_nat_manip_type;\n\nenum nfs3_createmode {\n\tNFS3_CREATE_UNCHECKED = 0,\n\tNFS3_CREATE_GUARDED = 1,\n\tNFS3_CREATE_EXCLUSIVE = 2,\n};\n\nenum nfs3_ftype {\n\tNF3NON = 0,\n\tNF3REG = 1,\n\tNF3DIR = 2,\n\tNF3BLK = 3,\n\tNF3CHR = 4,\n\tNF3LNK = 5,\n\tNF3SOCK = 6,\n\tNF3FIFO = 7,\n\tNF3BAD = 8,\n};\n\nenum nfs3_stable_how {\n\tNFS_UNSTABLE = 0,\n\tNFS_DATA_SYNC = 1,\n\tNFS_FILE_SYNC = 2,\n\tNFS_INVALID_STABLE_HOW = -1,\n};\n\nenum nfs4_acl_type {\n\tNFS4ACL_NONE = 0,\n\tNFS4ACL_ACL = 1,\n\tNFS4ACL_DACL = 2,\n\tNFS4ACL_SACL = 3,\n};\n\nenum nfs4_callback_procnum {\n\tCB_NULL = 0,\n\tCB_COMPOUND = 1,\n};\n\nenum nfs4_change_attr_type {\n\tNFS4_CHANGE_TYPE_IS_MONOTONIC_INCR = 0,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER = 1,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER_NOPNFS = 2,\n\tNFS4_CHANGE_TYPE_IS_TIME_METADATA = 3,\n\tNFS4_CHANGE_TYPE_IS_UNDEFINED = 4,\n};\n\nenum nfs4_client_state {\n\tNFS4CLNT_MANAGER_RUNNING = 0,\n\tNFS4CLNT_CHECK_LEASE = 1,\n\tNFS4CLNT_LEASE_EXPIRED = 2,\n\tNFS4CLNT_RECLAIM_REBOOT = 3,\n\tNFS4CLNT_RECLAIM_NOGRACE = 4,\n\tNFS4CLNT_DELEGRETURN = 5,\n\tNFS4CLNT_SESSION_RESET = 6,\n\tNFS4CLNT_LEASE_CONFIRM = 7,\n\tNFS4CLNT_SERVER_SCOPE_MISMATCH = 8,\n\tNFS4CLNT_PURGE_STATE = 9,\n\tNFS4CLNT_BIND_CONN_TO_SESSION = 10,\n\tNFS4CLNT_MOVED = 11,\n\tNFS4CLNT_LEASE_MOVED = 12,\n\tNFS4CLNT_DELEGATION_EXPIRED = 13,\n\tNFS4CLNT_RUN_MANAGER = 14,\n\tNFS4CLNT_MANAGER_AVAILABLE = 15,\n\tNFS4CLNT_RECALL_RUNNING = 16,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_READ = 17,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_RW = 18,\n\tNFS4CLNT_DELEGRETURN_DELAYED = 19,\n};\n\nenum nfs4_ff_op_type {\n\tNFS4_FF_OP_LAYOUTSTATS = 0,\n\tNFS4_FF_OP_LAYOUTRETURN = 1,\n};\n\nenum nfs4_open_delegation_type4 {\n\tNFS4_OPEN_DELEGATE_NONE = 0,\n\tNFS4_OPEN_DELEGATE_READ = 1,\n\tNFS4_OPEN_DELEGATE_WRITE = 2,\n\tNFS4_OPEN_DELEGATE_NONE_EXT = 3,\n\tNFS4_OPEN_DELEGATE_READ_ATTRS_DELEG = 4,\n\tNFS4_OPEN_DELEGATE_WRITE_ATTRS_DELEG = 5,\n};\n\nenum nfs4_session_state {\n\tNFS4_SESSION_INITING = 0,\n\tNFS4_SESSION_ESTABLISHED = 1,\n};\n\nenum nfs4_setxattr_options {\n\tSETXATTR4_EITHER = 0,\n\tSETXATTR4_CREATE = 1,\n\tSETXATTR4_REPLACE = 2,\n};\n\nenum nfs4_slot_tbl_state {\n\tNFS4_SLOT_TBL_DRAINING = 0,\n};\n\nenum nfs_cb_opnum4 {\n\tOP_CB_GETATTR = 3,\n\tOP_CB_RECALL = 4,\n\tOP_CB_LAYOUTRECALL = 5,\n\tOP_CB_NOTIFY = 6,\n\tOP_CB_PUSH_DELEG = 7,\n\tOP_CB_RECALL_ANY = 8,\n\tOP_CB_RECALLABLE_OBJ_AVAIL = 9,\n\tOP_CB_RECALL_SLOT = 10,\n\tOP_CB_SEQUENCE = 11,\n\tOP_CB_WANTS_CANCELLED = 12,\n\tOP_CB_NOTIFY_LOCK = 13,\n\tOP_CB_NOTIFY_DEVICEID = 14,\n\tOP_CB_OFFLOAD = 15,\n\tOP_CB_ILLEGAL = 10044,\n};\n\nenum nfs_ftype4 {\n\tNF4BAD = 0,\n\tNF4REG = 1,\n\tNF4DIR = 2,\n\tNF4BLK = 3,\n\tNF4CHR = 4,\n\tNF4LNK = 5,\n\tNF4SOCK = 6,\n\tNF4FIFO = 7,\n\tNF4ATTRDIR = 8,\n\tNF4NAMEDATTR = 9,\n};\n\nenum nfs_lock_status {\n\tNFS_LOCK_NOT_SET = 0,\n\tNFS_LOCK_LOCK = 1,\n\tNFS_LOCK_NOLOCK = 2,\n};\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nfs_param {\n\tOpt_ac = 0,\n\tOpt_acdirmax = 1,\n\tOpt_acdirmin = 2,\n\tOpt_acl___2 = 3,\n\tOpt_acregmax = 4,\n\tOpt_acregmin = 5,\n\tOpt_actimeo = 6,\n\tOpt_addr = 7,\n\tOpt_bg = 8,\n\tOpt_bsize = 9,\n\tOpt_clientaddr = 10,\n\tOpt_cto = 11,\n\tOpt_alignwrite = 12,\n\tOpt_fatal_neterrors = 13,\n\tOpt_fg = 14,\n\tOpt_fscache = 15,\n\tOpt_fscache_flag = 16,\n\tOpt_hard = 17,\n\tOpt_intr = 18,\n\tOpt_local_lock = 19,\n\tOpt_lock = 20,\n\tOpt_lookupcache = 21,\n\tOpt_migration = 22,\n\tOpt_minorversion = 23,\n\tOpt_mountaddr = 24,\n\tOpt_mounthost = 25,\n\tOpt_mountport = 26,\n\tOpt_mountproto = 27,\n\tOpt_mountvers = 28,\n\tOpt_namelen = 29,\n\tOpt_nconnect = 30,\n\tOpt_max_connect = 31,\n\tOpt_port___2 = 32,\n\tOpt_posix = 33,\n\tOpt_proto = 34,\n\tOpt_rdirplus = 35,\n\tOpt_rdirplus_none = 36,\n\tOpt_rdirplus_force = 37,\n\tOpt_rdma = 38,\n\tOpt_resvport = 39,\n\tOpt_retrans = 40,\n\tOpt_retry = 41,\n\tOpt_rsize = 42,\n\tOpt_sec = 43,\n\tOpt_sharecache = 44,\n\tOpt_sloppy = 45,\n\tOpt_soft = 46,\n\tOpt_softerr = 47,\n\tOpt_softreval = 48,\n\tOpt_source___3 = 49,\n\tOpt_tcp = 50,\n\tOpt_timeo = 51,\n\tOpt_trunkdiscovery = 52,\n\tOpt_udp = 53,\n\tOpt_v = 54,\n\tOpt_vers = 55,\n\tOpt_wsize = 56,\n\tOpt_write = 57,\n\tOpt_xprtsec = 58,\n\tOpt_cert_serial = 59,\n\tOpt_privkey_serial = 60,\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nenum nfs_stat_bytecounters {\n\tNFSIOS_NORMALREADBYTES = 0,\n\tNFSIOS_NORMALWRITTENBYTES = 1,\n\tNFSIOS_DIRECTREADBYTES = 2,\n\tNFSIOS_DIRECTWRITTENBYTES = 3,\n\tNFSIOS_SERVERREADBYTES = 4,\n\tNFSIOS_SERVERWRITTENBYTES = 5,\n\tNFSIOS_READPAGES = 6,\n\tNFSIOS_WRITEPAGES = 7,\n\t__NFSIOS_BYTESMAX = 8,\n};\n\nenum nfs_stat_eventcounters {\n\tNFSIOS_INODEREVALIDATE = 0,\n\tNFSIOS_DENTRYREVALIDATE = 1,\n\tNFSIOS_DATAINVALIDATE = 2,\n\tNFSIOS_ATTRINVALIDATE = 3,\n\tNFSIOS_VFSOPEN = 4,\n\tNFSIOS_VFSLOOKUP = 5,\n\tNFSIOS_VFSACCESS = 6,\n\tNFSIOS_VFSUPDATEPAGE = 7,\n\tNFSIOS_VFSREADPAGE = 8,\n\tNFSIOS_VFSREADPAGES = 9,\n\tNFSIOS_VFSWRITEPAGE = 10,\n\tNFSIOS_VFSWRITEPAGES = 11,\n\tNFSIOS_VFSGETDENTS = 12,\n\tNFSIOS_VFSSETATTR = 13,\n\tNFSIOS_VFSFLUSH = 14,\n\tNFSIOS_VFSFSYNC = 15,\n\tNFSIOS_VFSLOCK = 16,\n\tNFSIOS_VFSRELEASE = 17,\n\tNFSIOS_CONGESTIONWAIT = 18,\n\tNFSIOS_SETATTRTRUNC = 19,\n\tNFSIOS_EXTENDWRITE = 20,\n\tNFSIOS_SILLYRENAME = 21,\n\tNFSIOS_SHORTREAD = 22,\n\tNFSIOS_SHORTWRITE = 23,\n\tNFSIOS_DELAY = 24,\n\tNFSIOS_PNFS_READ = 25,\n\tNFSIOS_PNFS_WRITE = 26,\n\t__NFSIOS_COUNTSMAX = 27,\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n\tNFS4ERR_NOXATTR = 10095,\n\tNFS4ERR_XATTR2BIG = 10096,\n\tNFS4ERR_FIRST_FREE = 10097,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_IOMMU_PAGES = 39,\n\tNR_SWAPCACHE = 40,\n\tPGPROMOTE_SUCCESS = 41,\n\tPGPROMOTE_CANDIDATE = 42,\n\tPGPROMOTE_CANDIDATE_NRL = 43,\n\tPGDEMOTE_KSWAPD = 44,\n\tPGDEMOTE_DIRECT = 45,\n\tPGDEMOTE_KHUGEPAGED = 46,\n\tPGDEMOTE_PROACTIVE = 47,\n\tNR_HUGETLB = 48,\n\tNR_BALLOON_PAGES = 49,\n\tNR_KERNEL_FILE_PAGES = 50,\n\tNR_VM_NODE_STAT_ITEMS = 51,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 2,\n\tN_MEMORY = 3,\n\tN_CPU = 4,\n\tN_GENERIC_INITIATOR = 5,\n\tNR_NODE_STATES = 6,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum numa_faults_stats {\n\tNUMA_MEM = 0,\n\tNUMA_CPU = 1,\n\tNUMA_MEMBUF = 2,\n\tNUMA_CPUBUF = 3,\n};\n\nenum numa_stat_item {\n\tNUMA_HIT = 0,\n\tNUMA_MISS = 1,\n\tNUMA_FOREIGN = 2,\n\tNUMA_INTERLEAVE_HIT = 3,\n\tNUMA_LOCAL = 4,\n\tNUMA_OTHER = 5,\n\tNR_VM_NUMA_EVENT_ITEMS = 6,\n};\n\nenum numa_topology_type {\n\tNUMA_DIRECT = 0,\n\tNUMA_GLUELESS_MESH = 1,\n\tNUMA_BACKPLANE = 2,\n};\n\nenum numa_type {\n\tnode_has_spare = 0,\n\tnode_fully_busy = 1,\n\tnode_overloaded = 2,\n};\n\nenum numa_vmaskip_reason {\n\tNUMAB_SKIP_UNSUITABLE = 0,\n\tNUMAB_SKIP_SHARED_RO = 1,\n\tNUMAB_SKIP_INACCESSIBLE = 2,\n\tNUMAB_SKIP_SCAN_DELAY = 3,\n\tNUMAB_SKIP_PID_INACTIVE = 4,\n\tNUMAB_SKIP_IGNORE_PID = 5,\n\tNUMAB_SKIP_SEQ_COMPLETED = 6,\n};\n\nenum nvdimm_claim_class {\n\tNVDIMM_CCLASS_NONE = 0,\n\tNVDIMM_CCLASS_BTT = 1,\n\tNVDIMM_CCLASS_BTT2 = 2,\n\tNVDIMM_CCLASS_PFN = 3,\n\tNVDIMM_CCLASS_DAX = 4,\n\tNVDIMM_CCLASS_UNKNOWN = 5,\n};\n\nenum nvdimm_event {\n\tNVDIMM_REVALIDATE_POISON = 0,\n\tNVDIMM_REVALIDATE_REGION = 1,\n};\n\nenum nvdimm_fwa_capability {\n\tNVDIMM_FWA_CAP_INVALID = 0,\n\tNVDIMM_FWA_CAP_NONE = 1,\n\tNVDIMM_FWA_CAP_QUIESCE = 2,\n\tNVDIMM_FWA_CAP_LIVE = 3,\n};\n\nenum nvdimm_fwa_result {\n\tNVDIMM_FWA_RESULT_INVALID = 0,\n\tNVDIMM_FWA_RESULT_NONE = 1,\n\tNVDIMM_FWA_RESULT_SUCCESS = 2,\n\tNVDIMM_FWA_RESULT_NOTSTAGED = 3,\n\tNVDIMM_FWA_RESULT_NEEDRESET = 4,\n\tNVDIMM_FWA_RESULT_FAIL = 5,\n};\n\nenum nvdimm_fwa_state {\n\tNVDIMM_FWA_INVALID = 0,\n\tNVDIMM_FWA_IDLE = 1,\n\tNVDIMM_FWA_ARMED = 2,\n\tNVDIMM_FWA_BUSY = 3,\n\tNVDIMM_FWA_ARM_OVERFLOW = 4,\n};\n\nenum nvdimm_fwa_trigger {\n\tNVDIMM_FWA_ARM = 0,\n\tNVDIMM_FWA_DISARM = 1,\n};\n\nenum nvdimm_passphrase_type {\n\tNVDIMM_USER = 0,\n\tNVDIMM_MASTER = 1,\n};\n\nenum nvdimm_security_bits {\n\tNVDIMM_SECURITY_DISABLED = 0,\n\tNVDIMM_SECURITY_UNLOCKED = 1,\n\tNVDIMM_SECURITY_LOCKED = 2,\n\tNVDIMM_SECURITY_FROZEN = 3,\n\tNVDIMM_SECURITY_OVERWRITE = 4,\n};\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n\tNVMEM_TYPE_FRAM = 4,\n};\n\nenum oatc14_hdd_status {\n\tOATC14_HDD_STATUS_CABLE_OK = 0,\n\tOATC14_HDD_STATUS_OPEN = 1,\n\tOATC14_HDD_STATUS_SHORT = 2,\n\tOATC14_HDD_STATUS_NOT_DETECTABLE = 3,\n};\n\nenum objext_flags {\n\tOBJEXTS_ALLOC_FAIL = 1,\n\t__OBJEXTS_FLAG_UNUSED = 4,\n\t__NR_OBJEXTS_FLAGS = 8,\n};\n\nenum of_gpio_flags {\n\tOF_GPIO_ACTIVE_LOW = 1,\n\tOF_GPIO_SINGLE_ENDED = 2,\n\tOF_GPIO_OPEN_DRAIN = 4,\n\tOF_GPIO_TRANSITORY = 8,\n\tOF_GPIO_PULL_UP = 16,\n\tOF_GPIO_PULL_DOWN = 32,\n\tOF_GPIO_PULL_DISABLE = 64,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum ohci_rh_state {\n\tOHCI_RH_HALTED = 0,\n\tOHCI_RH_SUSPENDED = 1,\n\tOHCI_RH_RUNNING = 2,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum open_claim_type4 {\n\tNFS4_OPEN_CLAIM_NULL = 0,\n\tNFS4_OPEN_CLAIM_PREVIOUS = 1,\n\tNFS4_OPEN_CLAIM_DELEGATE_CUR = 2,\n\tNFS4_OPEN_CLAIM_DELEGATE_PREV = 3,\n\tNFS4_OPEN_CLAIM_FH = 4,\n\tNFS4_OPEN_CLAIM_DELEG_CUR_FH = 5,\n\tNFS4_OPEN_CLAIM_DELEG_PREV_FH = 6,\n};\n\nenum opentype4 {\n\tNFS4_OPEN_NOCREATE = 0,\n\tNFS4_OPEN_CREATE = 1,\n};\n\nenum opp_table_access {\n\tOPP_TABLE_ACCESS_UNKNOWN = 0,\n\tOPP_TABLE_ACCESS_EXCLUSIVE = 1,\n\tOPP_TABLE_ACCESS_SHARED = 2,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum p1_regulator_id {\n\tP1_BUCK1 = 0,\n\tP1_BUCK2 = 1,\n\tP1_BUCK3 = 2,\n\tP1_BUCK4 = 3,\n\tP1_BUCK5 = 4,\n\tP1_BUCK6 = 5,\n\tP1_ALDO1 = 6,\n\tP1_ALDO2 = 7,\n\tP1_ALDO3 = 8,\n\tP1_ALDO4 = 9,\n\tP1_DLDO1 = 10,\n\tP1_DLDO2 = 11,\n\tP1_DLDO3 = 12,\n\tP1_DLDO4 = 13,\n\tP1_DLDO5 = 14,\n\tP1_DLDO6 = 15,\n\tP1_DLDO7 = 16,\n};\n\nenum p9_cache_bits {\n\tCACHE_NONE = 0,\n\tCACHE_FILE = 1,\n\tCACHE_META = 2,\n\tCACHE_WRITEBACK = 4,\n\tCACHE_LOOSE = 8,\n\tCACHE_FSCACHE = 128,\n};\n\nenum p9_cache_shortcuts {\n\tCACHE_SC_NONE = 0,\n\tCACHE_SC_READAHEAD = 1,\n\tCACHE_SC_MMAP = 5,\n\tCACHE_SC_LOOSE = 15,\n\tCACHE_SC_FSCACHE = 143,\n};\n\nenum p9_fid_reftype {\n\tP9_FID_REF_CREATE = 0,\n\tP9_FID_REF_GET = 1,\n\tP9_FID_REF_PUT = 2,\n\tP9_FID_REF_DESTROY = 3,\n} __attribute__((mode(byte)));\n\nenum p9_msg_t {\n\tP9_TLERROR = 6,\n\tP9_RLERROR = 7,\n\tP9_TSTATFS = 8,\n\tP9_RSTATFS = 9,\n\tP9_TLOPEN = 12,\n\tP9_RLOPEN = 13,\n\tP9_TLCREATE = 14,\n\tP9_RLCREATE = 15,\n\tP9_TSYMLINK = 16,\n\tP9_RSYMLINK = 17,\n\tP9_TMKNOD = 18,\n\tP9_RMKNOD = 19,\n\tP9_TRENAME = 20,\n\tP9_RRENAME = 21,\n\tP9_TREADLINK = 22,\n\tP9_RREADLINK = 23,\n\tP9_TGETATTR = 24,\n\tP9_RGETATTR = 25,\n\tP9_TSETATTR = 26,\n\tP9_RSETATTR = 27,\n\tP9_TXATTRWALK = 30,\n\tP9_RXATTRWALK = 31,\n\tP9_TXATTRCREATE = 32,\n\tP9_RXATTRCREATE = 33,\n\tP9_TREADDIR = 40,\n\tP9_RREADDIR = 41,\n\tP9_TFSYNC = 50,\n\tP9_RFSYNC = 51,\n\tP9_TLOCK = 52,\n\tP9_RLOCK = 53,\n\tP9_TGETLOCK = 54,\n\tP9_RGETLOCK = 55,\n\tP9_TLINK = 70,\n\tP9_RLINK = 71,\n\tP9_TMKDIR = 72,\n\tP9_RMKDIR = 73,\n\tP9_TRENAMEAT = 74,\n\tP9_RRENAMEAT = 75,\n\tP9_TUNLINKAT = 76,\n\tP9_RUNLINKAT = 77,\n\tP9_TVERSION = 100,\n\tP9_RVERSION = 101,\n\tP9_TAUTH = 102,\n\tP9_RAUTH = 103,\n\tP9_TATTACH = 104,\n\tP9_RATTACH = 105,\n\tP9_TERROR = 106,\n\tP9_RERROR = 107,\n\tP9_TFLUSH = 108,\n\tP9_RFLUSH = 109,\n\tP9_TWALK = 110,\n\tP9_RWALK = 111,\n\tP9_TOPEN = 112,\n\tP9_ROPEN = 113,\n\tP9_TCREATE = 114,\n\tP9_RCREATE = 115,\n\tP9_TREAD = 116,\n\tP9_RREAD = 117,\n\tP9_TWRITE = 118,\n\tP9_RWRITE = 119,\n\tP9_TCLUNK = 120,\n\tP9_RCLUNK = 121,\n\tP9_TREMOVE = 122,\n\tP9_RREMOVE = 123,\n\tP9_TSTAT = 124,\n\tP9_RSTAT = 125,\n\tP9_TWSTAT = 126,\n\tP9_RWSTAT = 127,\n};\n\nenum p9_open_mode_t {\n\tP9_OREAD = 0,\n\tP9_OWRITE = 1,\n\tP9_ORDWR = 2,\n\tP9_OEXEC = 3,\n\tP9_OTRUNC = 16,\n\tP9_OREXEC = 32,\n\tP9_ORCLOSE = 64,\n\tP9_OAPPEND = 128,\n\tP9_OEXCL = 4096,\n\tP9L_MODE_MASK = 8191,\n\tP9L_DIRECT = 8192,\n\tP9L_NOWRITECACHE = 16384,\n\tP9L_LOOSE = 32768,\n};\n\nenum p9_perm_t {\n\tP9_DMDIR = 2147483648,\n\tP9_DMAPPEND = 1073741824,\n\tP9_DMEXCL = 536870912,\n\tP9_DMMOUNT = 268435456,\n\tP9_DMAUTH = 134217728,\n\tP9_DMTMP = 67108864,\n\tP9_DMSYMLINK = 33554432,\n\tP9_DMLINK = 16777216,\n\tP9_DMDEVICE = 8388608,\n\tP9_DMNAMEDPIPE = 2097152,\n\tP9_DMSOCKET = 1048576,\n\tP9_DMSETUID = 524288,\n\tP9_DMSETGID = 262144,\n\tP9_DMSETVTX = 65536,\n};\n\nenum p9_proto_versions {\n\tp9_proto_legacy = 0,\n\tp9_proto_2000u = 1,\n\tp9_proto_2000L = 2,\n};\n\nenum p9_req_status_t {\n\tREQ_STATUS_ALLOC = 0,\n\tREQ_STATUS_UNSENT = 1,\n\tREQ_STATUS_SENT = 2,\n\tREQ_STATUS_RCVD = 3,\n\tREQ_STATUS_FLSHD = 4,\n\tREQ_STATUS_ERROR = 5,\n};\n\nenum p9_session_flags {\n\tV9FS_PROTO_2000U = 1,\n\tV9FS_PROTO_2000L = 2,\n\tV9FS_ACCESS_SINGLE = 4,\n\tV9FS_ACCESS_USER = 8,\n\tV9FS_ACCESS_CLIENT = 16,\n\tV9FS_POSIX_ACL = 32,\n\tV9FS_NO_XATTR = 64,\n\tV9FS_IGNORE_QV = 128,\n\tV9FS_DIRECT_IO = 256,\n\tV9FS_SYNC = 512,\n};\n\nenum p9_trans_status {\n\tConnected = 0,\n\tBeginDisconnect = 1,\n\tDisconnected = 2,\n\tHung = 3,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum page_memcg_data_flags {\n\tMEMCG_DATA_OBJEXTS = 1,\n\tMEMCG_DATA_KMEM = 2,\n\t__NR_MEMCG_DATA_FLAGS = 4,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 4096,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\t__NR_PAGEBLOCK_BITS = 4,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\t__NR_PAGEFLAGS = 21,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nenum path_flags {\n\tPATH_IS_DIR = 1,\n\tPATH_SOCK_COND = 2,\n\tPATH_CONNECT_PATH = 4,\n\tPATH_CHROOT_REL = 8,\n\tPATH_CHROOT_NSCONNECT = 16,\n\tPATH_DELEGATE_DELETED = 65536,\n\tPATH_MEDIATE_DELETED = 131072,\n};\n\nenum pce_status {\n\tPCE_STATUS_NONE = 0,\n\tPCE_STATUS_ACQUIRED = 1,\n\tPCE_STATUS_PREPARED = 2,\n\tPCE_STATUS_ENABLED = 3,\n\tPCE_STATUS_ERROR = 4,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_barno {\n\tNO_BAR = -1,\n\tBAR_0 = 0,\n\tBAR_1 = 1,\n\tBAR_2 = 2,\n\tBAR_3 = 3,\n\tBAR_4 = 4,\n\tBAR_5 = 5,\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_15625000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_oxsemi = 71,\n\tpbn_oxsemi_1_15625000 = 72,\n\tpbn_oxsemi_2_15625000 = 73,\n\tpbn_oxsemi_4_15625000 = 74,\n\tpbn_oxsemi_8_15625000 = 75,\n\tpbn_intel_i960 = 76,\n\tpbn_sgi_ioc3 = 77,\n\tpbn_computone_4 = 78,\n\tpbn_computone_6 = 79,\n\tpbn_computone_8 = 80,\n\tpbn_sbsxrsio = 81,\n\tpbn_pasemi_1682M = 82,\n\tpbn_ni8430_2 = 83,\n\tpbn_ni8430_4 = 84,\n\tpbn_ni8430_8 = 85,\n\tpbn_ni8430_16 = 86,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 87,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 90,\n\tpbn_ce4100_1_115200 = 91,\n\tpbn_omegapci = 92,\n\tpbn_NETMOS9900_2s_115200 = 93,\n\tpbn_brcm_trumanage = 94,\n\tpbn_fintek_4 = 95,\n\tpbn_fintek_8 = 96,\n\tpbn_fintek_12 = 97,\n\tpbn_fintek_F81504A = 98,\n\tpbn_fintek_F81508A = 99,\n\tpbn_fintek_F81512A = 100,\n\tpbn_wch382_2 = 101,\n\tpbn_wch384_4 = 102,\n\tpbn_wch384_8 = 103,\n\tpbn_sunix_pci_1s = 104,\n\tpbn_sunix_pci_2s = 105,\n\tpbn_sunix_pci_4s = 106,\n\tpbn_sunix_pci_8s = 107,\n\tpbn_sunix_pci_16s = 108,\n\tpbn_titan_1_4000000 = 109,\n\tpbn_titan_2_4000000 = 110,\n\tpbn_titan_4_4000000 = 111,\n\tpbn_titan_8_4000000 = 112,\n\tpbn_moxa_2 = 113,\n\tpbn_moxa_4 = 114,\n\tpbn_moxa_8 = 115,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_epc_bar_type {\n\tBAR_PROGRAMMABLE = 0,\n\tBAR_FIXED = 1,\n\tBAR_RESIZABLE = 2,\n\tBAR_RESERVED = 3,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_hotplug_event {\n\tPCI_HOTPLUG_LINK_UP = 0,\n\tPCI_HOTPLUG_LINK_DOWN = 1,\n\tPCI_HOTPLUG_CARD_PRESENT = 2,\n\tPCI_HOTPLUG_CARD_NOT_PRESENT = 3,\n};\n\nenum pci_interrupt_pin {\n\tPCI_INTERRUPT_UNKNOWN = 0,\n\tPCI_INTERRUPT_INTA = 1,\n\tPCI_INTERRUPT_INTB = 2,\n\tPCI_INTERRUPT_INTC = 3,\n\tPCI_INTERRUPT_INTD = 4,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE = 262144,\n\tPERF_SAMPLE_BRANCH_COUNTERS = 524288,\n\tPERF_SAMPLE_BRANCH_MAX = 1048576,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 18446744073709551584ULL,\n\tPERF_CONTEXT_KERNEL = 18446744073709551488ULL,\n\tPERF_CONTEXT_USER = 18446744073709551104ULL,\n\tPERF_CONTEXT_USER_DEFERRED = 18446744073709550976ULL,\n\tPERF_CONTEXT_GUEST = 18446744073709549568ULL,\n\tPERF_CONTEXT_GUEST_KERNEL = 18446744073709549440ULL,\n\tPERF_CONTEXT_GUEST_USER = 18446744073709549056ULL,\n\tPERF_CONTEXT_MAX = 18446744073709547521ULL,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_LOST = 16,\n\tPERF_FORMAT_MAX = 32,\n};\n\nenum perf_event_riscv_regs {\n\tPERF_REG_RISCV_PC = 0,\n\tPERF_REG_RISCV_RA = 1,\n\tPERF_REG_RISCV_SP = 2,\n\tPERF_REG_RISCV_GP = 3,\n\tPERF_REG_RISCV_TP = 4,\n\tPERF_REG_RISCV_T0 = 5,\n\tPERF_REG_RISCV_T1 = 6,\n\tPERF_REG_RISCV_T2 = 7,\n\tPERF_REG_RISCV_S0 = 8,\n\tPERF_REG_RISCV_S1 = 9,\n\tPERF_REG_RISCV_A0 = 10,\n\tPERF_REG_RISCV_A1 = 11,\n\tPERF_REG_RISCV_A2 = 12,\n\tPERF_REG_RISCV_A3 = 13,\n\tPERF_REG_RISCV_A4 = 14,\n\tPERF_REG_RISCV_A5 = 15,\n\tPERF_REG_RISCV_A6 = 16,\n\tPERF_REG_RISCV_A7 = 17,\n\tPERF_REG_RISCV_S2 = 18,\n\tPERF_REG_RISCV_S3 = 19,\n\tPERF_REG_RISCV_S4 = 20,\n\tPERF_REG_RISCV_S5 = 21,\n\tPERF_REG_RISCV_S6 = 22,\n\tPERF_REG_RISCV_S7 = 23,\n\tPERF_REG_RISCV_S8 = 24,\n\tPERF_REG_RISCV_S9 = 25,\n\tPERF_REG_RISCV_S10 = 26,\n\tPERF_REG_RISCV_S11 = 27,\n\tPERF_REG_RISCV_T3 = 28,\n\tPERF_REG_RISCV_T4 = 29,\n\tPERF_REG_RISCV_T5 = 30,\n\tPERF_REG_RISCV_T6 = 31,\n\tPERF_REG_RISCV_MAX = 32,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_DATA_PAGE_SIZE = 4194304,\n\tPERF_SAMPLE_CODE_PAGE_SIZE = 8388608,\n\tPERF_SAMPLE_WEIGHT_STRUCT = 16777216,\n\tPERF_SAMPLE_MAX = 33554432,\n};\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = -5,\n\tPERF_EVENT_STATE_REVOKED = -4,\n\tPERF_EVENT_STATE_EXIT = -3,\n\tPERF_EVENT_STATE_ERROR = -2,\n\tPERF_EVENT_STATE_OFF = -1,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = -1,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_TEXT_POKE = 20,\n\tPERF_RECORD_AUX_OUTPUT_HW_ID = 21,\n\tPERF_RECORD_CALLCHAIN_DEFERRED = 22,\n\tPERF_RECORD_MAX = 23,\n};\n\nenum perf_hw_cache_id {\n\tPERF_COUNT_HW_CACHE_L1D = 0,\n\tPERF_COUNT_HW_CACHE_L1I = 1,\n\tPERF_COUNT_HW_CACHE_LL = 2,\n\tPERF_COUNT_HW_CACHE_DTLB = 3,\n\tPERF_COUNT_HW_CACHE_ITLB = 4,\n\tPERF_COUNT_HW_CACHE_BPU = 5,\n\tPERF_COUNT_HW_CACHE_NODE = 6,\n\tPERF_COUNT_HW_CACHE_MAX = 7,\n};\n\nenum perf_hw_cache_op_id {\n\tPERF_COUNT_HW_CACHE_OP_READ = 0,\n\tPERF_COUNT_HW_CACHE_OP_WRITE = 1,\n\tPERF_COUNT_HW_CACHE_OP_PREFETCH = 2,\n\tPERF_COUNT_HW_CACHE_OP_MAX = 3,\n};\n\nenum perf_hw_cache_op_result_id {\n\tPERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,\n\tPERF_COUNT_HW_CACHE_RESULT_MISS = 1,\n\tPERF_COUNT_HW_CACHE_RESULT_MAX = 2,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_pmu_scope {\n\tPERF_PMU_SCOPE_NONE = 0,\n\tPERF_PMU_SCOPE_CORE = 1,\n\tPERF_PMU_SCOPE_DIE = 2,\n\tPERF_PMU_SCOPE_CLUSTER = 3,\n\tPERF_PMU_SCOPE_PKG = 4,\n\tPERF_PMU_SCOPE_SYS_WIDE = 5,\n\tPERF_PMU_MAX_SCOPE = 6,\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum phy_media {\n\tPHY_MEDIA_DEFAULT = 0,\n\tPHY_MEDIA_SR = 1,\n\tPHY_MEDIA_DAC = 2,\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n\tPHY_MODE_HDMI = 20,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_port_parent {\n\tPHY_PORT_PHY = 0,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_state_work {\n\tPHY_STATE_WORK_NONE = 0,\n\tPHY_STATE_WORK_ANEG = 1,\n\tPHY_STATE_WORK_SUSPEND = 2,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_ufs_state {\n\tPHY_UFS_HIBERN8_ENTER = 0,\n\tPHY_UFS_HIBERN8_EXIT = 1,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum phylink_op_type {\n\tPHYLINK_NETDEV = 0,\n\tPHYLINK_DEV = 1,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidcg_event {\n\tPIDCG_MAX = 0,\n\tPIDCG_FORKFAIL = 1,\n\tNR_PIDCG_EVENTS = 2,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum pin_config_param {\n\tPIN_CONFIG_BIAS_BUS_HOLD = 0,\n\tPIN_CONFIG_BIAS_DISABLE = 1,\n\tPIN_CONFIG_BIAS_HIGH_IMPEDANCE = 2,\n\tPIN_CONFIG_BIAS_PULL_DOWN = 3,\n\tPIN_CONFIG_BIAS_PULL_PIN_DEFAULT = 4,\n\tPIN_CONFIG_BIAS_PULL_UP = 5,\n\tPIN_CONFIG_DRIVE_OPEN_DRAIN = 6,\n\tPIN_CONFIG_DRIVE_OPEN_SOURCE = 7,\n\tPIN_CONFIG_DRIVE_PUSH_PULL = 8,\n\tPIN_CONFIG_DRIVE_STRENGTH = 9,\n\tPIN_CONFIG_DRIVE_STRENGTH_UA = 10,\n\tPIN_CONFIG_INPUT_DEBOUNCE = 11,\n\tPIN_CONFIG_INPUT_ENABLE = 12,\n\tPIN_CONFIG_INPUT_SCHMITT = 13,\n\tPIN_CONFIG_INPUT_SCHMITT_ENABLE = 14,\n\tPIN_CONFIG_INPUT_SCHMITT_UV = 15,\n\tPIN_CONFIG_MODE_LOW_POWER = 16,\n\tPIN_CONFIG_MODE_PWM = 17,\n\tPIN_CONFIG_LEVEL = 18,\n\tPIN_CONFIG_OUTPUT_ENABLE = 19,\n\tPIN_CONFIG_OUTPUT_IMPEDANCE_OHMS = 20,\n\tPIN_CONFIG_PERSIST_STATE = 21,\n\tPIN_CONFIG_POWER_SOURCE = 22,\n\tPIN_CONFIG_SKEW_DELAY = 23,\n\tPIN_CONFIG_SKEW_DELAY_INPUT_PS = 24,\n\tPIN_CONFIG_SKEW_DELAY_OUTPUT_PS = 25,\n\tPIN_CONFIG_SLEEP_HARDWARE_STATE = 26,\n\tPIN_CONFIG_SLEW_RATE = 27,\n\tPIN_CONFIG_END = 127,\n\tPIN_CONFIG_MAX = 255,\n};\n\nenum pinctrl_map_type {\n\tPIN_MAP_TYPE_INVALID = 0,\n\tPIN_MAP_TYPE_DUMMY_STATE = 1,\n\tPIN_MAP_TYPE_MUX_GROUP = 2,\n\tPIN_MAP_TYPE_CONFIGS_PIN = 3,\n\tPIN_MAP_TYPE_CONFIGS_GROUP = 4,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum plda_int_event {\n\tPLDA_AXI_POST_ERR = 0,\n\tPLDA_AXI_FETCH_ERR = 1,\n\tPLDA_AXI_DISCARD_ERR = 2,\n\tPLDA_AXI_DOORBELL = 3,\n\tPLDA_PCIE_POST_ERR = 4,\n\tPLDA_PCIE_FETCH_ERR = 5,\n\tPLDA_PCIE_DISCARD_ERR = 6,\n\tPLDA_PCIE_DOORBELL = 7,\n\tPLDA_INTX = 8,\n\tPLDA_MSI = 9,\n\tPLDA_AER_EVENT = 10,\n\tPLDA_MISC_EVENTS = 11,\n\tPLDA_SYS_ERR = 12,\n\tPLDA_INT_EVENT_NUM = 13,\n};\n\nenum pm_api_id {\n\tPM_API_FEATURES = 0,\n\tPM_GET_API_VERSION = 1,\n\tPM_GET_NODE_STATUS = 3,\n\tPM_REGISTER_NOTIFIER = 5,\n\tPM_FORCE_POWERDOWN = 8,\n\tPM_REQUEST_WAKEUP = 10,\n\tPM_SYSTEM_SHUTDOWN = 12,\n\tPM_REQUEST_NODE = 13,\n\tPM_RELEASE_NODE = 14,\n\tPM_SET_REQUIREMENT = 15,\n\tPM_RESET_ASSERT = 17,\n\tPM_RESET_GET_STATUS = 18,\n\tPM_MMIO_WRITE = 19,\n\tPM_MMIO_READ = 20,\n\tPM_PM_INIT_FINALIZE = 21,\n\tPM_FPGA_LOAD = 22,\n\tPM_FPGA_GET_STATUS = 23,\n\tPM_GET_CHIPID = 24,\n\tPM_SECURE_SHA = 26,\n\tPM_PINCTRL_REQUEST = 28,\n\tPM_PINCTRL_RELEASE = 29,\n\tPM_PINCTRL_SET_FUNCTION = 31,\n\tPM_PINCTRL_CONFIG_PARAM_GET = 32,\n\tPM_PINCTRL_CONFIG_PARAM_SET = 33,\n\tPM_IOCTL = 34,\n\tPM_QUERY_DATA = 35,\n\tPM_CLOCK_ENABLE = 36,\n\tPM_CLOCK_DISABLE = 37,\n\tPM_CLOCK_GETSTATE = 38,\n\tPM_CLOCK_SETDIVIDER = 39,\n\tPM_CLOCK_GETDIVIDER = 40,\n\tPM_CLOCK_SETPARENT = 43,\n\tPM_CLOCK_GETPARENT = 44,\n\tPM_FPGA_READ = 46,\n\tPM_SECURE_AES = 47,\n\tPM_EFUSE_ACCESS = 53,\n\tPM_FEATURE_CHECK = 63,\n};\n\nenum pm_gem_config_type {\n\tGEM_CONFIG_SGMII_MODE = 1,\n\tGEM_CONFIG_FIXED = 2,\n};\n\nenum pm_ioctl_id {\n\tIOCTL_GET_RPU_OPER_MODE = 0,\n\tIOCTL_SET_RPU_OPER_MODE = 1,\n\tIOCTL_RPU_BOOT_ADDR_CONFIG = 2,\n\tIOCTL_TCM_COMB_CONFIG = 3,\n\tIOCTL_SET_TAPDELAY_BYPASS = 4,\n\tIOCTL_SD_DLL_RESET = 6,\n\tIOCTL_SET_SD_TAPDELAY = 7,\n\tIOCTL_SET_PLL_FRAC_MODE = 8,\n\tIOCTL_GET_PLL_FRAC_MODE = 9,\n\tIOCTL_SET_PLL_FRAC_DATA = 10,\n\tIOCTL_GET_PLL_FRAC_DATA = 11,\n\tIOCTL_WRITE_GGS = 12,\n\tIOCTL_READ_GGS = 13,\n\tIOCTL_WRITE_PGGS = 14,\n\tIOCTL_READ_PGGS = 15,\n\tIOCTL_SET_BOOT_HEALTH_STATUS = 17,\n\tIOCTL_OSPI_MUX_SELECT = 21,\n\tIOCTL_REGISTER_SGI = 25,\n\tIOCTL_SET_FEATURE_CONFIG = 26,\n\tIOCTL_GET_FEATURE_CONFIG = 27,\n\tIOCTL_READ_REG = 28,\n\tIOCTL_MASK_WRITE_REG = 29,\n\tIOCTL_SET_SD_CONFIG = 30,\n\tIOCTL_SET_GEM_CONFIG = 31,\n\tIOCTL_GET_QOS = 34,\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = -1,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum pnfs_iomode {\n\tIOMODE_READ = 1,\n\tIOMODE_RW = 2,\n\tIOMODE_ANY = 3,\n};\n\nenum pnfs_layout_destroy_mode {\n\tPNFS_LAYOUT_INVALIDATE = 0,\n\tPNFS_LAYOUT_BULK_RETURN = 1,\n\tPNFS_LAYOUT_FILE_BULK_RETURN = 2,\n};\n\nenum pnfs_layoutreturn_type {\n\tRETURN_FILE = 1,\n\tRETURN_FSID = 2,\n\tRETURN_ALL = 3,\n};\n\nenum pnfs_layouttype {\n\tLAYOUT_NFSV4_1_FILES = 1,\n\tLAYOUT_OSD2_OBJECTS = 2,\n\tLAYOUT_BLOCK_VOLUME = 3,\n\tLAYOUT_FLEX_FILES = 4,\n\tLAYOUT_SCSI = 5,\n\tLAYOUT_TYPE_MAX = 6,\n};\n\nenum pnfs_notify_deviceid_type4 {\n\tNOTIFY_DEVICEID4_CHANGE = 2,\n\tNOTIFY_DEVICEID4_DELETE = 4,\n};\n\nenum pnfs_try_status {\n\tPNFS_ATTEMPTED = 0,\n\tPNFS_NOT_ATTEMPTED = 1,\n\tPNFS_TRY_AGAIN = 2,\n};\n\nenum pnfs_update_layout_reason {\n\tPNFS_UPDATE_LAYOUT_UNKNOWN = 0,\n\tPNFS_UPDATE_LAYOUT_NO_PNFS = 1,\n\tPNFS_UPDATE_LAYOUT_RD_ZEROLEN = 2,\n\tPNFS_UPDATE_LAYOUT_MDSTHRESH = 3,\n\tPNFS_UPDATE_LAYOUT_NOMEM = 4,\n\tPNFS_UPDATE_LAYOUT_BULK_RECALL = 5,\n\tPNFS_UPDATE_LAYOUT_IO_TEST_FAIL = 6,\n\tPNFS_UPDATE_LAYOUT_FOUND_CACHED = 7,\n\tPNFS_UPDATE_LAYOUT_RETURN = 8,\n\tPNFS_UPDATE_LAYOUT_RETRY = 9,\n\tPNFS_UPDATE_LAYOUT_BLOCKED = 10,\n\tPNFS_UPDATE_LAYOUT_INVALID_OPEN = 11,\n\tPNFS_UPDATE_LAYOUT_SEND_LAYOUTGET = 12,\n\tPNFS_UPDATE_LAYOUT_EXIT = 13,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port_pkey_state {\n\tIB_PORT_PKEY_NOT_VALID = 0,\n\tIB_PORT_PKEY_VALID = 1,\n\tIB_PORT_PKEY_LISTED = 2,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum power_supply_charge_behaviour {\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO = 0,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE = 1,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE_AWAKE = 2,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE = 3,\n};\n\nenum power_supply_charge_type {\n\tPOWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_CHARGE_TYPE_NONE = 1,\n\tPOWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2,\n\tPOWER_SUPPLY_CHARGE_TYPE_FAST = 3,\n\tPOWER_SUPPLY_CHARGE_TYPE_STANDARD = 4,\n\tPOWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5,\n\tPOWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6,\n\tPOWER_SUPPLY_CHARGE_TYPE_LONGLIFE = 7,\n\tPOWER_SUPPLY_CHARGE_TYPE_BYPASS = 8,\n};\n\nenum power_supply_notifier_events {\n\tPSY_EVENT_PROP_CHANGED = 0,\n};\n\nenum power_supply_property {\n\tPOWER_SUPPLY_PROP_STATUS = 0,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPE = 1,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPES = 2,\n\tPOWER_SUPPLY_PROP_HEALTH = 3,\n\tPOWER_SUPPLY_PROP_PRESENT = 4,\n\tPOWER_SUPPLY_PROP_ONLINE = 5,\n\tPOWER_SUPPLY_PROP_AUTHENTIC = 6,\n\tPOWER_SUPPLY_PROP_TECHNOLOGY = 7,\n\tPOWER_SUPPLY_PROP_CYCLE_COUNT = 8,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX = 9,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN = 10,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN = 11,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN = 12,\n\tPOWER_SUPPLY_PROP_VOLTAGE_NOW = 13,\n\tPOWER_SUPPLY_PROP_VOLTAGE_AVG = 14,\n\tPOWER_SUPPLY_PROP_VOLTAGE_OCV = 15,\n\tPOWER_SUPPLY_PROP_VOLTAGE_BOOT = 16,\n\tPOWER_SUPPLY_PROP_CURRENT_MAX = 17,\n\tPOWER_SUPPLY_PROP_CURRENT_NOW = 18,\n\tPOWER_SUPPLY_PROP_CURRENT_AVG = 19,\n\tPOWER_SUPPLY_PROP_CURRENT_BOOT = 20,\n\tPOWER_SUPPLY_PROP_POWER_NOW = 21,\n\tPOWER_SUPPLY_PROP_POWER_AVG = 22,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL_DESIGN = 23,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN = 24,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL = 25,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY = 26,\n\tPOWER_SUPPLY_PROP_CHARGE_NOW = 27,\n\tPOWER_SUPPLY_PROP_CHARGE_AVG = 28,\n\tPOWER_SUPPLY_PROP_CHARGE_COUNTER = 29,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT = 30,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX = 31,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE = 32,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX = 33,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT = 34,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX = 35,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD = 36,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD = 37,\n\tPOWER_SUPPLY_PROP_CHARGE_BEHAVIOUR = 38,\n\tPOWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT = 39,\n\tPOWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT = 40,\n\tPOWER_SUPPLY_PROP_INPUT_POWER_LIMIT = 41,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL_DESIGN = 42,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN = 43,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL = 44,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY = 45,\n\tPOWER_SUPPLY_PROP_ENERGY_NOW = 46,\n\tPOWER_SUPPLY_PROP_ENERGY_AVG = 47,\n\tPOWER_SUPPLY_PROP_CAPACITY = 48,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MIN = 49,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MAX = 50,\n\tPOWER_SUPPLY_PROP_CAPACITY_ERROR_MARGIN = 51,\n\tPOWER_SUPPLY_PROP_CAPACITY_LEVEL = 52,\n\tPOWER_SUPPLY_PROP_TEMP = 53,\n\tPOWER_SUPPLY_PROP_TEMP_MAX = 54,\n\tPOWER_SUPPLY_PROP_TEMP_MIN = 55,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MIN = 56,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MAX = 57,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT = 58,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN = 59,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX = 60,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW = 61,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG = 62,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_NOW = 63,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_AVG = 64,\n\tPOWER_SUPPLY_PROP_TYPE = 65,\n\tPOWER_SUPPLY_PROP_USB_TYPE = 66,\n\tPOWER_SUPPLY_PROP_SCOPE = 67,\n\tPOWER_SUPPLY_PROP_PRECHARGE_CURRENT = 68,\n\tPOWER_SUPPLY_PROP_CHARGE_TERM_CURRENT = 69,\n\tPOWER_SUPPLY_PROP_CALIBRATE = 70,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_YEAR = 71,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_MONTH = 72,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_DAY = 73,\n\tPOWER_SUPPLY_PROP_INTERNAL_RESISTANCE = 74,\n\tPOWER_SUPPLY_PROP_STATE_OF_HEALTH = 75,\n\tPOWER_SUPPLY_PROP_MODEL_NAME = 76,\n\tPOWER_SUPPLY_PROP_MANUFACTURER = 77,\n\tPOWER_SUPPLY_PROP_SERIAL_NUMBER = 78,\n};\n\nenum power_supply_type {\n\tPOWER_SUPPLY_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_TYPE_BATTERY = 1,\n\tPOWER_SUPPLY_TYPE_UPS = 2,\n\tPOWER_SUPPLY_TYPE_MAINS = 3,\n\tPOWER_SUPPLY_TYPE_USB = 4,\n\tPOWER_SUPPLY_TYPE_USB_DCP = 5,\n\tPOWER_SUPPLY_TYPE_USB_CDP = 6,\n\tPOWER_SUPPLY_TYPE_USB_ACA = 7,\n\tPOWER_SUPPLY_TYPE_USB_TYPE_C = 8,\n\tPOWER_SUPPLY_TYPE_USB_PD = 9,\n\tPOWER_SUPPLY_TYPE_USB_PD_DRP = 10,\n\tPOWER_SUPPLY_TYPE_APPLE_BRICK_ID = 11,\n\tPOWER_SUPPLY_TYPE_WIRELESS = 12,\n};\n\nenum power_supply_usb_type {\n\tPOWER_SUPPLY_USB_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_USB_TYPE_SDP = 1,\n\tPOWER_SUPPLY_USB_TYPE_DCP = 2,\n\tPOWER_SUPPLY_USB_TYPE_CDP = 3,\n\tPOWER_SUPPLY_USB_TYPE_ACA = 4,\n\tPOWER_SUPPLY_USB_TYPE_C = 5,\n\tPOWER_SUPPLY_USB_TYPE_PD = 6,\n\tPOWER_SUPPLY_USB_TYPE_PD_DRP = 7,\n\tPOWER_SUPPLY_USB_TYPE_PD_PPS = 8,\n\tPOWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID = 9,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_insn {\n\tINSN_REJECTED = 0,\n\tINSN_GOOD_NO_SLOT = 1,\n\tINSN_GOOD = 2,\n};\n\nenum probe_print_type {\n\tPROBE_PRINT_NORMAL = 0,\n\tPROBE_PRINT_RETURN = 1,\n\tPROBE_PRINT_EVENT = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___8 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum profile_mode {\n\tAPPARMOR_ENFORCE = 0,\n\tAPPARMOR_COMPLAIN = 1,\n\tAPPARMOR_KILL = 2,\n\tAPPARMOR_UNCONFINED = 3,\n\tAPPARMOR_USER = 4,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum ps2_disposition {\n\tPS2_PROCESS = 0,\n\tPS2_IGNORE = 1,\n\tPS2_ERROR = 2,\n};\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_EXTOFF = 2,\n\tPTP_CLOCK_PPS = 3,\n\tPTP_CLOCK_PPSUSR = 4,\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nenum pwm_polarity {\n\tPWM_POLARITY_NORMAL = 0,\n\tPWM_POLARITY_INVERSED = 1,\n};\n\nenum qdisc_class_ops_flags {\n\tQDISC_CLASS_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum ramfs_param {\n\tOpt_mode___6 = 0,\n};\n\nenum rdma_ah_attr_type {\n\tRDMA_AH_ATTR_TYPE_UNDEFINED = 0,\n\tRDMA_AH_ATTR_TYPE_IB = 1,\n\tRDMA_AH_ATTR_TYPE_ROCE = 2,\n\tRDMA_AH_ATTR_TYPE_OPA = 3,\n};\n\nenum rdma_driver_id {\n\tRDMA_DRIVER_UNKNOWN = 0,\n\tRDMA_DRIVER_MLX5 = 1,\n\tRDMA_DRIVER_MLX4 = 2,\n\tRDMA_DRIVER_CXGB3 = 3,\n\tRDMA_DRIVER_CXGB4 = 4,\n\tRDMA_DRIVER_MTHCA = 5,\n\tRDMA_DRIVER_BNXT_RE = 6,\n\tRDMA_DRIVER_OCRDMA = 7,\n\tRDMA_DRIVER_NES = 8,\n\tRDMA_DRIVER_I40IW = 9,\n\tRDMA_DRIVER_IRDMA = 9,\n\tRDMA_DRIVER_VMW_PVRDMA = 10,\n\tRDMA_DRIVER_QEDR = 11,\n\tRDMA_DRIVER_HNS = 12,\n\tRDMA_DRIVER_USNIC = 13,\n\tRDMA_DRIVER_RXE = 14,\n\tRDMA_DRIVER_HFI1 = 15,\n\tRDMA_DRIVER_QIB = 16,\n\tRDMA_DRIVER_EFA = 17,\n\tRDMA_DRIVER_SIW = 18,\n\tRDMA_DRIVER_ERDMA = 19,\n\tRDMA_DRIVER_MANA = 20,\n\tRDMA_DRIVER_IONIC = 21,\n};\n\nenum rdma_link_layer {\n\tIB_LINK_LAYER_UNSPECIFIED = 0,\n\tIB_LINK_LAYER_INFINIBAND = 1,\n\tIB_LINK_LAYER_ETHERNET = 2,\n};\n\nenum rdma_netdev_t {\n\tRDMA_NETDEV_OPA_VNIC = 0,\n\tRDMA_NETDEV_IPOIB = 1,\n};\n\nenum rdma_nl_counter_mask {\n\tRDMA_COUNTER_MASK_QP_TYPE = 1,\n\tRDMA_COUNTER_MASK_PID = 2,\n};\n\nenum rdma_nl_counter_mode {\n\tRDMA_COUNTER_MODE_NONE = 0,\n\tRDMA_COUNTER_MODE_AUTO = 1,\n\tRDMA_COUNTER_MODE_MANUAL = 2,\n\tRDMA_COUNTER_MODE_MAX = 3,\n};\n\nenum rdma_nl_dev_type {\n\tRDMA_DEVICE_TYPE_SMI = 1,\n};\n\nenum rdma_nl_name_assign_type {\n\tRDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0,\n\tRDMA_NAME_ASSIGN_TYPE_USER = 1,\n};\n\nenum rdma_restrack_type {\n\tRDMA_RESTRACK_PD = 0,\n\tRDMA_RESTRACK_CQ = 1,\n\tRDMA_RESTRACK_QP = 2,\n\tRDMA_RESTRACK_CM_ID = 3,\n\tRDMA_RESTRACK_MR = 4,\n\tRDMA_RESTRACK_CTX = 5,\n\tRDMA_RESTRACK_COUNTER = 6,\n\tRDMA_RESTRACK_SRQ = 7,\n\tRDMA_RESTRACK_DMAH = 8,\n\tRDMA_RESTRACK_MAX = 9,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_FLAT = 2,\n\tREGCACHE_MAPLE = 3,\n\tREGCACHE_FLAT_S = 4,\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nenum regulator_active_discharge {\n\tREGULATOR_ACTIVE_DISCHARGE_DEFAULT = 0,\n\tREGULATOR_ACTIVE_DISCHARGE_DISABLE = 1,\n\tREGULATOR_ACTIVE_DISCHARGE_ENABLE = 2,\n};\n\nenum regulator_detection_severity {\n\tREGULATOR_SEVERITY_PROT = 0,\n\tREGULATOR_SEVERITY_ERR = 1,\n\tREGULATOR_SEVERITY_WARN = 2,\n};\n\nenum regulator_get_type {\n\tNORMAL_GET = 0,\n\tEXCLUSIVE_GET = 1,\n\tOPTIONAL_GET = 2,\n\tMAX_GET_TYPE = 3,\n};\n\nenum regulator_status {\n\tREGULATOR_STATUS_OFF = 0,\n\tREGULATOR_STATUS_ON = 1,\n\tREGULATOR_STATUS_ERROR = 2,\n\tREGULATOR_STATUS_FAST = 3,\n\tREGULATOR_STATUS_NORMAL = 4,\n\tREGULATOR_STATUS_IDLE = 5,\n\tREGULATOR_STATUS_STANDBY = 6,\n\tREGULATOR_STATUS_BYPASS = 7,\n\tREGULATOR_STATUS_UNDEFINED = 8,\n};\n\nenum regulator_type {\n\tREGULATOR_VOLTAGE = 0,\n\tREGULATOR_CURRENT = 1,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reset_control_flags {\n\tRESET_CONTROL_EXCLUSIVE = 4,\n\tRESET_CONTROL_EXCLUSIVE_DEASSERTED = 12,\n\tRESET_CONTROL_EXCLUSIVE_RELEASED = 0,\n\tRESET_CONTROL_SHARED = 1,\n\tRESET_CONTROL_SHARED_DEASSERTED = 9,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE = 6,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_DEASSERTED = 14,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_RELEASED = 2,\n\tRESET_CONTROL_OPTIONAL_SHARED = 3,\n\tRESET_CONTROL_OPTIONAL_SHARED_DEASSERTED = 11,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum rgmii_clock_delay {\n\tRGMII_CLK_DELAY_0_2_NS = 0,\n\tRGMII_CLK_DELAY_0_8_NS = 1,\n\tRGMII_CLK_DELAY_1_1_NS = 2,\n\tRGMII_CLK_DELAY_1_7_NS = 3,\n\tRGMII_CLK_DELAY_2_0_NS = 4,\n\tRGMII_CLK_DELAY_2_3_NS = 5,\n\tRGMII_CLK_DELAY_2_6_NS = 6,\n\tRGMII_CLK_DELAY_3_4_NS = 7,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum riscv_iommu_dc_fsc_atp_modes {\n\tRISCV_IOMMU_DC_FSC_MODE_BARE = 0,\n\tRISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 = 8,\n\tRISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 = 8,\n\tRISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 = 9,\n\tRISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 = 10,\n\tRISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 = 1,\n\tRISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 = 2,\n\tRISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 = 3,\n};\n\nenum riscv_iommu_ddtp_modes {\n\tRISCV_IOMMU_DDTP_IOMMU_MODE_OFF = 0,\n\tRISCV_IOMMU_DDTP_IOMMU_MODE_BARE = 1,\n\tRISCV_IOMMU_DDTP_IOMMU_MODE_1LVL = 2,\n\tRISCV_IOMMU_DDTP_IOMMU_MODE_2LVL = 3,\n\tRISCV_IOMMU_DDTP_IOMMU_MODE_3LVL = 4,\n\tRISCV_IOMMU_DDTP_IOMMU_MODE_MAX = 4,\n};\n\nenum riscv_iommu_igs_settings {\n\tRISCV_IOMMU_CAPABILITIES_IGS_MSI = 0,\n\tRISCV_IOMMU_CAPABILITIES_IGS_WSI = 1,\n\tRISCV_IOMMU_CAPABILITIES_IGS_BOTH = 2,\n\tRISCV_IOMMU_CAPABILITIES_IGS_RSRV = 3,\n};\n\nenum riscv_irqchip_type {\n\tACPI_RISCV_IRQCHIP_INTC = 0,\n\tACPI_RISCV_IRQCHIP_IMSIC = 1,\n\tACPI_RISCV_IRQCHIP_PLIC = 2,\n\tACPI_RISCV_IRQCHIP_APLIC = 3,\n\tACPI_RISCV_IRQCHIP_SMSI = 4,\n};\n\nenum riscv_regset {\n\tREGSET_X = 0,\n\tREGSET_F = 1,\n\tREGSET_V = 2,\n\tREGSET_TAGGED_ADDR_CTRL = 3,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nenum rpc_accept_stat {\n\tRPC_SUCCESS = 0,\n\tRPC_PROG_UNAVAIL = 1,\n\tRPC_PROG_MISMATCH = 2,\n\tRPC_PROC_UNAVAIL = 3,\n\tRPC_GARBAGE_ARGS = 4,\n\tRPC_SYSTEM_ERR = 5,\n\tRPC_DROP_REPLY = 60000,\n};\n\nenum rpc_auth_flavors {\n\tRPC_AUTH_NULL = 0,\n\tRPC_AUTH_UNIX = 1,\n\tRPC_AUTH_SHORT = 2,\n\tRPC_AUTH_DES = 3,\n\tRPC_AUTH_KRB = 4,\n\tRPC_AUTH_GSS = 6,\n\tRPC_AUTH_TLS = 7,\n\tRPC_AUTH_MAXFLAVOR = 8,\n\tRPC_AUTH_GSS_KRB5 = 390003,\n\tRPC_AUTH_GSS_KRB5I = 390004,\n\tRPC_AUTH_GSS_KRB5P = 390005,\n\tRPC_AUTH_GSS_LKEY = 390006,\n\tRPC_AUTH_GSS_LKEYI = 390007,\n\tRPC_AUTH_GSS_LKEYP = 390008,\n\tRPC_AUTH_GSS_SPKM = 390009,\n\tRPC_AUTH_GSS_SPKMI = 390010,\n\tRPC_AUTH_GSS_SPKMP = 390011,\n};\n\nenum rpc_auth_stat {\n\tRPC_AUTH_OK = 0,\n\tRPC_AUTH_BADCRED = 1,\n\tRPC_AUTH_REJECTEDCRED = 2,\n\tRPC_AUTH_BADVERF = 3,\n\tRPC_AUTH_REJECTEDVERF = 4,\n\tRPC_AUTH_TOOWEAK = 5,\n\tRPC_AUTH_INVALIDRESP = 6,\n\tRPC_AUTH_FAILED = 7,\n\tRPCSEC_GSS_CREDPROBLEM = 13,\n\tRPCSEC_GSS_CTXPROBLEM = 14,\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum rpc_msg_type {\n\tRPC_CALL = 0,\n\tRPC_REPLY = 1,\n};\n\nenum rpc_reject_stat {\n\tRPC_MISMATCH = 0,\n\tRPC_AUTH_ERROR = 1,\n};\n\nenum rpc_reply_stat {\n\tRPC_MSG_ACCEPTED = 0,\n\tRPC_MSG_DENIED = 1,\n};\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rpmb_type {\n\tRPMB_TYPE_EMMC = 0,\n\tRPMB_TYPE_UFS = 1,\n\tRPMB_TYPE_NVME = 2,\n};\n\nenum rpmi_clk_config {\n\tRPMI_CLK_DISABLE = 0,\n\tRPMI_CLK_ENABLE = 1,\n\tRPMI_CLK_CONFIG_MAX_IDX = 2,\n};\n\nenum rpmi_clk_type {\n\tRPMI_CLK_DISCRETE = 0,\n\tRPMI_CLK_LINEAR = 1,\n\tRPMI_CLK_TYPE_MAX_IDX = 2,\n};\n\nenum rpmi_clock_service_id {\n\tRPMI_CLK_SRV_ENABLE_NOTIFICATION = 1,\n\tRPMI_CLK_SRV_GET_NUM_CLOCKS = 2,\n\tRPMI_CLK_SRV_GET_ATTRIBUTES = 3,\n\tRPMI_CLK_SRV_GET_SUPPORTED_RATES = 4,\n\tRPMI_CLK_SRV_SET_CONFIG = 5,\n\tRPMI_CLK_SRV_GET_CONFIG = 6,\n\tRPMI_CLK_SRV_SET_RATE = 7,\n\tRPMI_CLK_SRV_GET_RATE = 8,\n\tRPMI_CLK_SRV_ID_MAX_COUNT = 9,\n};\n\nenum rpmi_error_codes {\n\tRPMI_SUCCESS = 0,\n\tRPMI_ERR_FAILED = -1,\n\tRPMI_ERR_NOTSUPP = -2,\n\tRPMI_ERR_INVALID_PARAM = -3,\n\tRPMI_ERR_DENIED = -4,\n\tRPMI_ERR_INVALID_ADDR = -5,\n\tRPMI_ERR_ALREADY = -6,\n\tRPMI_ERR_EXTENSION = -7,\n\tRPMI_ERR_HW_FAULT = -8,\n\tRPMI_ERR_BUSY = -9,\n\tRPMI_ERR_INVALID_STATE = -10,\n\tRPMI_ERR_BAD_RANGE = -11,\n\tRPMI_ERR_TIMEOUT = -12,\n\tRPMI_ERR_IO = -13,\n\tRPMI_ERR_NO_DATA = -14,\n\tRPMI_ERR_RESERVED_START = -15,\n\tRPMI_ERR_RESERVED_END = -127,\n\tRPMI_ERR_VENDOR_START = -128,\n};\n\nenum rpmi_mbox_attribute_id {\n\tRPMI_MBOX_ATTR_SPEC_VERSION = 0,\n\tRPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE = 1,\n\tRPMI_MBOX_ATTR_SERVICEGROUP_ID = 2,\n\tRPMI_MBOX_ATTR_SERVICEGROUP_VERSION = 3,\n\tRPMI_MBOX_ATTR_IMPL_ID = 4,\n\tRPMI_MBOX_ATTR_IMPL_VERSION = 5,\n\tRPMI_MBOX_ATTR_MAX_ID = 6,\n};\n\nenum rpmi_mbox_message_type {\n\tRPMI_MBOX_MSG_TYPE_GET_ATTRIBUTE = 0,\n\tRPMI_MBOX_MSG_TYPE_SET_ATTRIBUTE = 1,\n\tRPMI_MBOX_MSG_TYPE_SEND_WITH_RESPONSE = 2,\n\tRPMI_MBOX_MSG_TYPE_SEND_WITHOUT_RESPONSE = 3,\n\tRPMI_MBOX_MSG_TYPE_NOTIFICATION_EVENT = 4,\n\tRPMI_MBOX_MSG_MAX_TYPE = 5,\n};\n\nenum rpmi_sysmsi_service_id {\n\tRPMI_SYSMSI_SRV_ENABLE_NOTIFICATION = 1,\n\tRPMI_SYSMSI_SRV_GET_ATTRIBUTES = 2,\n\tRPMI_SYSMSI_SRV_GET_MSI_ATTRIBUTES = 3,\n\tRPMI_SYSMSI_SRV_SET_MSI_STATE = 4,\n\tRPMI_SYSMSI_SRV_GET_MSI_STATE = 5,\n\tRPMI_SYSMSI_SRV_SET_MSI_TARGET = 6,\n\tRPMI_SYSMSI_SRV_GET_MSI_TARGET = 7,\n\tRPMI_SYSMSI_SRV_ID_MAX_COUNT = 8,\n};\n\nenum rpmsg_ns_flags {\n\tRPMSG_NS_CREATE = 0,\n\tRPMSG_NS_DESTROY = 1,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rt6_nud_state {\n\tRT6_NUD_FAIL_HARD = -3,\n\tRT6_NUD_FAIL_PROBE = -2,\n\tRT6_NUD_FAIL_DO_RR = -1,\n\tRT6_NUD_SUCCEED = 1,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtl8125_registers {\n\tLEDSEL0 = 24,\n\tINT_CFG0_8125 = 52,\n\tIntrMask_8125 = 56,\n\tIntrStatus_8125 = 60,\n\tINT_CFG1_8125 = 122,\n\tLEDSEL2 = 132,\n\tLEDSEL1 = 134,\n\tTxPoll_8125 = 144,\n\tLEDSEL3 = 150,\n\tMAC0_BKP = 6624,\n\tRSS_CTRL_8125 = 17664,\n\tQ_NUM_CTRL_8125 = 18432,\n\tEEE_TXIDLE_TIMER_8125 = 24648,\n};\n\nenum rtl8168_8101_registers {\n\tCSIDR = 100,\n\tCSIAR = 104,\n\tPMCH = 111,\n\tEPHYAR = 128,\n\tDLLPR = 208,\n\tDBG_REG = 209,\n\tTWSI = 210,\n\tMCU = 211,\n\tEFUSEAR = 220,\n\tMISC_1 = 242,\n};\n\nenum rtl8168_registers {\n\tLED_CTRL = 24,\n\tLED_FREQ = 26,\n\tEEE_LED = 27,\n\tERIDR = 112,\n\tERIAR = 116,\n\tEPHY_RXER_NUM = 124,\n\tOCPDR = 176,\n\tOCPAR = 180,\n\tGPHY_OCP = 184,\n\tRDSAR1 = 208,\n\tMISC = 240,\n\tCOMBO_LTR_EXTEND = 182,\n};\n\nenum rtl_dash_type {\n\tRTL_DASH_NONE = 0,\n\tRTL_DASH_DP = 1,\n\tRTL_DASH_EP = 2,\n\tRTL_DASH_25_BP = 3,\n};\n\nenum rtl_desc_bit {\n\tDescOwn = -2147483648,\n\tRingEnd = 1073741824,\n\tFirstFrag = 536870912,\n\tLastFrag = 268435456,\n};\n\nenum rtl_flag {\n\tRTL_FLAG_TASK_RESET_PENDING = 0,\n\tRTL_FLAG_TASK_TX_TIMEOUT = 1,\n\tRTL_FLAG_MAX = 2,\n};\n\nenum rtl_fw_opcode {\n\tPHY_READ = 0,\n\tPHY_DATA_OR = 1,\n\tPHY_DATA_AND = 2,\n\tPHY_BJMPN = 3,\n\tPHY_MDIO_CHG = 4,\n\tPHY_CLEAR_READCOUNT = 7,\n\tPHY_WRITE = 8,\n\tPHY_READCOUNT_EQ_SKIP = 9,\n\tPHY_COMP_EQ_SKIPN = 10,\n\tPHY_COMP_NEQ_SKIPN = 11,\n\tPHY_WRITE_PREVIOUS = 12,\n\tPHY_SKIPN = 13,\n\tPHY_DELAY_MS = 14,\n};\n\nenum rtl_register_content {\n\tSYSErr = 32768,\n\tPCSTimeout = 16384,\n\tSWInt = 256,\n\tTxDescUnavail = 128,\n\tRxFIFOOver = 64,\n\tLinkChg = 32,\n\tRxOverflow = 16,\n\tTxErr = 8,\n\tTxOK = 4,\n\tRxErr = 2,\n\tRxOK = 1,\n\tRxRWT = 4194304,\n\tRxRES = 2097152,\n\tRxRUNT = 1048576,\n\tRxCRC = 524288,\n\tStopReq = 128,\n\tCmdReset = 16,\n\tCmdRxEnb = 8,\n\tCmdTxEnb = 4,\n\tRxBufEmpty = 1,\n\tHPQ = 128,\n\tNPQ = 64,\n\tFSWInt = 1,\n\tCfg9346_Lock = 0,\n\tCfg9346_Unlock = 192,\n\tAcceptErr = 32,\n\tAcceptRunt = 16,\n\tAcceptBroadcast = 8,\n\tAcceptMulticast = 4,\n\tAcceptMyPhys = 2,\n\tAcceptAllPhys = 1,\n\tTxInterFrameGapShift = 24,\n\tTxDMAShift = 8,\n\tLEDS1 = 128,\n\tLEDS0 = 64,\n\tSpeed_down = 16,\n\tMEMMAP = 8,\n\tIOMAP = 4,\n\tVPD = 2,\n\tPMEnable = 1,\n\tClkReqEn = 128,\n\tMSIEnable = 32,\n\tPCI_Clock_66MHz = 1,\n\tPCI_Clock_33MHz = 0,\n\tMagicPacket = 32,\n\tLinkUp = 16,\n\tJumbo_En0 = 4,\n\tRdy_to_L23 = 2,\n\tBeacon_en = 1,\n\tJumbo_En1 = 2,\n\tBWF = 64,\n\tMWF = 32,\n\tUWF = 16,\n\tSpi_en = 8,\n\tLanWake = 2,\n\tPMEStatus = 1,\n\tASPM_en = 1,\n\tEnableBist = 32768,\n\tMac_dbgo_oe = 16384,\n\tEnAnaPLL = 16384,\n\tNormal_mode = 8192,\n\tForce_half_dup = 4096,\n\tForce_rxflow_en = 2048,\n\tForce_txflow_en = 1024,\n\tCxpl_dbg_sel = 512,\n\tASF = 256,\n\tPktCntrDisable = 128,\n\tMac_dbgo_sel = 28,\n\tRxVlan = 64,\n\tRxChkSum = 32,\n\tPCIDAC = 16,\n\tPCIMulRW = 8,\n\tTBI_Enable = 128,\n\tTxFlowCtrl = 64,\n\tRxFlowCtrl = 32,\n\t_1000bpsF = 16,\n\t_100bps = 8,\n\t_10bps = 4,\n\tLinkStatus = 2,\n\tFullDup = 1,\n\tCounterReset = 1,\n\tCounterDump = 8,\n\tMagicPacket_v2 = 65536,\n};\n\nenum rtl_registers {\n\tMAC0 = 0,\n\tMAC4 = 4,\n\tMAR0 = 8,\n\tCounterAddrLow = 16,\n\tCounterAddrHigh = 20,\n\tTxDescStartAddrLow = 32,\n\tTxDescStartAddrHigh = 36,\n\tTxHDescStartAddrLow = 40,\n\tTxHDescStartAddrHigh = 44,\n\tFLASH = 48,\n\tERSR = 54,\n\tChipCmd = 55,\n\tTxPoll = 56,\n\tIntrMask = 60,\n\tIntrStatus = 62,\n\tTxConfig = 64,\n\tTX_CONFIG_V2 = 24752,\n\tRxConfig = 68,\n\tCfg9346 = 80,\n\tConfig0 = 81,\n\tConfig1 = 82,\n\tConfig2 = 83,\n\tConfig3 = 84,\n\tConfig4 = 85,\n\tConfig5 = 86,\n\tPHYAR = 96,\n\tPHYstatus = 108,\n\tRxMaxSize = 218,\n\tCPlusCmd = 224,\n\tIntrMitigate = 226,\n\tRxDescAddrLow = 228,\n\tRxDescAddrHigh = 232,\n\tEarlyTxThres = 236,\n\tMaxTxPacketSize = 236,\n\tFuncEvent = 240,\n\tFuncEventMask = 244,\n\tFuncPresetState = 248,\n\tIBCR0 = 248,\n\tIBCR2 = 249,\n\tIBIMR0 = 250,\n\tIBISR0 = 251,\n\tFuncForceEvent = 252,\n\tALDPS_LTR = 57506,\n\tLTR_OBFF_LOCK = 57394,\n\tLTR_SNOOP = 57396,\n};\n\nenum rtl_rx_desc_bit {\n\tPID1 = 262144,\n\tPID0 = 131072,\n\tIPFail = 65536,\n\tUDPFail = 32768,\n\tTCPFail = 16384,\n\tRxVlanTag = 65536,\n};\n\nenum rtl_tx_desc_bit {\n\tTD_LSO = 134217728,\n\tTxVlanTag = 131072,\n};\n\nenum rtl_tx_desc_bit_0 {\n\tTD0_TCP_CS = 65536,\n\tTD0_UDP_CS = 131072,\n\tTD0_IP_CS = 262144,\n};\n\nenum rtl_tx_desc_bit_1 {\n\tTD1_GTSENV4 = 67108864,\n\tTD1_GTSENV6 = 33554432,\n\tTD1_IPv6_CS = 268435456,\n\tTD1_IPv4_CS = 536870912,\n\tTD1_TCP_CS = 1073741824,\n\tTD1_UDP_CS = -2147483648,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum sbi_ext_base_fid {\n\tSBI_EXT_BASE_GET_SPEC_VERSION = 0,\n\tSBI_EXT_BASE_GET_IMP_ID = 1,\n\tSBI_EXT_BASE_GET_IMP_VERSION = 2,\n\tSBI_EXT_BASE_PROBE_EXT = 3,\n\tSBI_EXT_BASE_GET_MVENDORID = 4,\n\tSBI_EXT_BASE_GET_MARCHID = 5,\n\tSBI_EXT_BASE_GET_MIMPID = 6,\n};\n\nenum sbi_ext_dbcn_fid {\n\tSBI_EXT_DBCN_CONSOLE_WRITE = 0,\n\tSBI_EXT_DBCN_CONSOLE_READ = 1,\n\tSBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,\n};\n\nenum sbi_ext_hsm_fid {\n\tSBI_EXT_HSM_HART_START = 0,\n\tSBI_EXT_HSM_HART_STOP = 1,\n\tSBI_EXT_HSM_HART_STATUS = 2,\n\tSBI_EXT_HSM_HART_SUSPEND = 3,\n};\n\nenum sbi_ext_id {\n\tSBI_EXT_BASE = 16,\n\tSBI_EXT_TIME = 1414090053,\n\tSBI_EXT_IPI = 7557193,\n\tSBI_EXT_RFENCE = 1380339267,\n\tSBI_EXT_HSM = 4739917,\n\tSBI_EXT_SRST = 1397904212,\n\tSBI_EXT_SUSP = 1398100816,\n\tSBI_EXT_PMU = 5262677,\n\tSBI_EXT_DBCN = 1145193294,\n\tSBI_EXT_STA = 5461057,\n\tSBI_EXT_NACL = 1312899916,\n\tSBI_EXT_FWFT = 1180124756,\n\tSBI_EXT_MPXY = 1297111129,\n\tSBI_EXT_DBTR = 1145197650,\n\tSBI_EXT_EXPERIMENTAL_START = 134217728,\n\tSBI_EXT_EXPERIMENTAL_END = 150994943,\n\tSBI_EXT_VENDOR_START = 150994944,\n\tSBI_EXT_VENDOR_END = 167772159,\n};\n\nenum sbi_ext_ipi_fid {\n\tSBI_EXT_IPI_SEND_IPI = 0,\n};\n\nenum sbi_ext_mpxy_fid {\n\tSBI_EXT_MPXY_GET_SHMEM_SIZE = 0,\n\tSBI_EXT_MPXY_SET_SHMEM = 1,\n\tSBI_EXT_MPXY_GET_CHANNEL_IDS = 2,\n\tSBI_EXT_MPXY_READ_ATTRS = 3,\n\tSBI_EXT_MPXY_WRITE_ATTRS = 4,\n\tSBI_EXT_MPXY_SEND_MSG_WITH_RESP = 5,\n\tSBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP = 6,\n\tSBI_EXT_MPXY_GET_NOTIFICATION_EVENTS = 7,\n};\n\nenum sbi_ext_pmu_fid {\n\tSBI_EXT_PMU_NUM_COUNTERS = 0,\n\tSBI_EXT_PMU_COUNTER_GET_INFO = 1,\n\tSBI_EXT_PMU_COUNTER_CFG_MATCH = 2,\n\tSBI_EXT_PMU_COUNTER_START = 3,\n\tSBI_EXT_PMU_COUNTER_STOP = 4,\n\tSBI_EXT_PMU_COUNTER_FW_READ = 5,\n\tSBI_EXT_PMU_COUNTER_FW_READ_HI = 6,\n\tSBI_EXT_PMU_SNAPSHOT_SET_SHMEM = 7,\n\tSBI_EXT_PMU_EVENT_GET_INFO = 8,\n};\n\nenum sbi_ext_rfence_fid {\n\tSBI_EXT_RFENCE_REMOTE_FENCE_I = 0,\n\tSBI_EXT_RFENCE_REMOTE_SFENCE_VMA = 1,\n\tSBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID = 2,\n\tSBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID = 3,\n\tSBI_EXT_RFENCE_REMOTE_HFENCE_GVMA = 4,\n\tSBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID = 5,\n\tSBI_EXT_RFENCE_REMOTE_HFENCE_VVMA = 6,\n};\n\nenum sbi_ext_srst_fid {\n\tSBI_EXT_SRST_RESET = 0,\n};\n\nenum sbi_ext_susp_fid {\n\tSBI_EXT_SUSP_SYSTEM_SUSPEND = 0,\n};\n\nenum sbi_ext_susp_sleep_type {\n\tSBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0,\n};\n\nenum sbi_ext_time_fid {\n\tSBI_EXT_TIME_SET_TIMER = 0,\n};\n\nenum sbi_fwft_feature_t {\n\tSBI_FWFT_MISALIGNED_EXC_DELEG = 0,\n\tSBI_FWFT_LANDING_PAD = 1,\n\tSBI_FWFT_SHADOW_STACK = 2,\n\tSBI_FWFT_DOUBLE_TRAP = 3,\n\tSBI_FWFT_PTE_AD_HW_UPDATING = 4,\n\tSBI_FWFT_POINTER_MASKING_PMLEN = 5,\n\tSBI_FWFT_LOCAL_RESERVED_START = 6,\n\tSBI_FWFT_LOCAL_RESERVED_END = 1073741823,\n\tSBI_FWFT_LOCAL_PLATFORM_START = 1073741824,\n\tSBI_FWFT_LOCAL_PLATFORM_END = 2147483647,\n\tSBI_FWFT_GLOBAL_RESERVED_START = 2147483648,\n\tSBI_FWFT_GLOBAL_RESERVED_END = 3221225471,\n\tSBI_FWFT_GLOBAL_PLATFORM_START = 3221225472,\n\tSBI_FWFT_GLOBAL_PLATFORM_END = 4294967295,\n};\n\nenum sbi_hsm_hart_state {\n\tSBI_HSM_STATE_STARTED = 0,\n\tSBI_HSM_STATE_STOPPED = 1,\n\tSBI_HSM_STATE_START_PENDING = 2,\n\tSBI_HSM_STATE_STOP_PENDING = 3,\n\tSBI_HSM_STATE_SUSPENDED = 4,\n\tSBI_HSM_STATE_SUSPEND_PENDING = 5,\n\tSBI_HSM_STATE_RESUME_PENDING = 6,\n};\n\nenum sbi_mpxy_attribute_id {\n\tSBI_MPXY_ATTR_MSG_PROT_ID = 0,\n\tSBI_MPXY_ATTR_MSG_PROT_VER = 1,\n\tSBI_MPXY_ATTR_MSG_MAX_LEN = 2,\n\tSBI_MPXY_ATTR_MSG_SEND_TIMEOUT = 3,\n\tSBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT = 4,\n\tSBI_MPXY_ATTR_CHANNEL_CAPABILITY = 5,\n\tSBI_MPXY_ATTR_SSE_EVENT_ID = 6,\n\tSBI_MPXY_ATTR_MSI_CONTROL = 7,\n\tSBI_MPXY_ATTR_MSI_ADDR_LO = 8,\n\tSBI_MPXY_ATTR_MSI_ADDR_HI = 9,\n\tSBI_MPXY_ATTR_MSI_DATA = 10,\n\tSBI_MPXY_ATTR_EVENTS_STATE_CONTROL = 11,\n\tSBI_MPXY_ATTR_STD_ATTR_MAX_IDX = 12,\n\tSBI_MPXY_ATTR_MSGPROTO_ATTR_START = 2147483648,\n\tSBI_MPXY_ATTR_MSGPROTO_ATTR_END = 4294967295,\n};\n\nenum sbi_mpxy_msgproto_id {\n\tSBI_MPXY_MSGPROTO_RPMI_ID = 0,\n};\n\nenum sbi_pmu_ctr_type {\n\tSBI_PMU_CTR_TYPE_HW = 0,\n\tSBI_PMU_CTR_TYPE_FW = 1,\n};\n\nenum sbi_pmu_event_type {\n\tSBI_PMU_EVENT_TYPE_HW = 0,\n\tSBI_PMU_EVENT_TYPE_CACHE = 1,\n\tSBI_PMU_EVENT_TYPE_RAW = 2,\n\tSBI_PMU_EVENT_TYPE_RAW_V2 = 3,\n\tSBI_PMU_EVENT_TYPE_FW = 15,\n};\n\nenum sbi_pmu_hw_generic_events_t {\n\tSBI_PMU_HW_NO_EVENT = 0,\n\tSBI_PMU_HW_CPU_CYCLES = 1,\n\tSBI_PMU_HW_INSTRUCTIONS = 2,\n\tSBI_PMU_HW_CACHE_REFERENCES = 3,\n\tSBI_PMU_HW_CACHE_MISSES = 4,\n\tSBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,\n\tSBI_PMU_HW_BRANCH_MISSES = 6,\n\tSBI_PMU_HW_BUS_CYCLES = 7,\n\tSBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,\n\tSBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,\n\tSBI_PMU_HW_REF_CPU_CYCLES = 10,\n\tSBI_PMU_HW_GENERAL_MAX = 11,\n};\n\nenum sbi_srst_reset_reason {\n\tSBI_SRST_RESET_REASON_NONE = 0,\n\tSBI_SRST_RESET_REASON_SYS_FAILURE = 1,\n};\n\nenum sbi_srst_reset_type {\n\tSBI_SRST_RESET_TYPE_SHUTDOWN = 0,\n\tSBI_SRST_RESET_TYPE_COLD_REBOOT = 1,\n\tSBI_SRST_RESET_TYPE_WARM_REBOOT = 2,\n};\n\nenum scale_freq_source {\n\tSCALE_FREQ_SOURCE_CPUFREQ = 0,\n\tSCALE_FREQ_SOURCE_ARCH = 1,\n\tSCALE_FREQ_SOURCE_CPPC = 2,\n\tSCALE_FREQ_SOURCE_VIRT = 3,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 2500,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_cid {\n\tSCTP_CID_DATA = 0,\n\tSCTP_CID_INIT = 1,\n\tSCTP_CID_INIT_ACK = 2,\n\tSCTP_CID_SACK = 3,\n\tSCTP_CID_HEARTBEAT = 4,\n\tSCTP_CID_HEARTBEAT_ACK = 5,\n\tSCTP_CID_ABORT = 6,\n\tSCTP_CID_SHUTDOWN = 7,\n\tSCTP_CID_SHUTDOWN_ACK = 8,\n\tSCTP_CID_ERROR = 9,\n\tSCTP_CID_COOKIE_ECHO = 10,\n\tSCTP_CID_COOKIE_ACK = 11,\n\tSCTP_CID_ECN_ECNE = 12,\n\tSCTP_CID_ECN_CWR = 13,\n\tSCTP_CID_SHUTDOWN_COMPLETE = 14,\n\tSCTP_CID_AUTH = 15,\n\tSCTP_CID_I_DATA = 64,\n\tSCTP_CID_FWD_TSN = 192,\n\tSCTP_CID_ASCONF = 193,\n\tSCTP_CID_I_FWD_TSN = 194,\n\tSCTP_CID_ASCONF_ACK = 128,\n\tSCTP_CID_RECONF = 130,\n\tSCTP_CID_PAD = 132,\n};\n\nenum sctp_conntrack {\n\tSCTP_CONNTRACK_NONE = 0,\n\tSCTP_CONNTRACK_CLOSED = 1,\n\tSCTP_CONNTRACK_COOKIE_WAIT = 2,\n\tSCTP_CONNTRACK_COOKIE_ECHOED = 3,\n\tSCTP_CONNTRACK_ESTABLISHED = 4,\n\tSCTP_CONNTRACK_SHUTDOWN_SENT = 5,\n\tSCTP_CONNTRACK_SHUTDOWN_RECD = 6,\n\tSCTP_CONNTRACK_SHUTDOWN_ACK_SENT = 7,\n\tSCTP_CONNTRACK_HEARTBEAT_SENT = 8,\n\tSCTP_CONNTRACK_HEARTBEAT_ACKED = 9,\n\tSCTP_CONNTRACK_MAX = 10,\n};\n\nenum sctp_endpoint_type {\n\tSCTP_EP_TYPE_SOCKET = 0,\n\tSCTP_EP_TYPE_ASSOCIATION = 1,\n};\n\nenum sctp_event_timeout {\n\tSCTP_EVENT_TIMEOUT_NONE = 0,\n\tSCTP_EVENT_TIMEOUT_T1_COOKIE = 1,\n\tSCTP_EVENT_TIMEOUT_T1_INIT = 2,\n\tSCTP_EVENT_TIMEOUT_T2_SHUTDOWN = 3,\n\tSCTP_EVENT_TIMEOUT_T3_RTX = 4,\n\tSCTP_EVENT_TIMEOUT_T4_RTO = 5,\n\tSCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD = 6,\n\tSCTP_EVENT_TIMEOUT_HEARTBEAT = 7,\n\tSCTP_EVENT_TIMEOUT_RECONF = 8,\n\tSCTP_EVENT_TIMEOUT_PROBE = 9,\n\tSCTP_EVENT_TIMEOUT_SACK = 10,\n\tSCTP_EVENT_TIMEOUT_AUTOCLOSE = 11,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum sctp_param {\n\tSCTP_PARAM_HEARTBEAT_INFO = 256,\n\tSCTP_PARAM_IPV4_ADDRESS = 1280,\n\tSCTP_PARAM_IPV6_ADDRESS = 1536,\n\tSCTP_PARAM_STATE_COOKIE = 1792,\n\tSCTP_PARAM_UNRECOGNIZED_PARAMETERS = 2048,\n\tSCTP_PARAM_COOKIE_PRESERVATIVE = 2304,\n\tSCTP_PARAM_HOST_NAME_ADDRESS = 2816,\n\tSCTP_PARAM_SUPPORTED_ADDRESS_TYPES = 3072,\n\tSCTP_PARAM_ECN_CAPABLE = 128,\n\tSCTP_PARAM_RANDOM = 640,\n\tSCTP_PARAM_CHUNKS = 896,\n\tSCTP_PARAM_HMAC_ALGO = 1152,\n\tSCTP_PARAM_SUPPORTED_EXT = 2176,\n\tSCTP_PARAM_FWD_TSN_SUPPORT = 192,\n\tSCTP_PARAM_ADD_IP = 448,\n\tSCTP_PARAM_DEL_IP = 704,\n\tSCTP_PARAM_ERR_CAUSE = 960,\n\tSCTP_PARAM_SET_PRIMARY = 1216,\n\tSCTP_PARAM_SUCCESS_REPORT = 1472,\n\tSCTP_PARAM_ADAPTATION_LAYER_IND = 1728,\n\tSCTP_PARAM_RESET_OUT_REQUEST = 3328,\n\tSCTP_PARAM_RESET_IN_REQUEST = 3584,\n\tSCTP_PARAM_RESET_TSN_REQUEST = 3840,\n\tSCTP_PARAM_RESET_RESPONSE = 4096,\n\tSCTP_PARAM_RESET_ADD_OUT_STREAMS = 4352,\n\tSCTP_PARAM_RESET_ADD_IN_STREAMS = 4608,\n};\n\nenum sctp_scope {\n\tSCTP_SCOPE_GLOBAL = 0,\n\tSCTP_SCOPE_PRIVATE = 1,\n\tSCTP_SCOPE_LINK = 2,\n\tSCTP_SCOPE_LOOPBACK = 3,\n\tSCTP_SCOPE_UNUSABLE = 4,\n};\n\nenum sctp_socket_type {\n\tSCTP_SOCKET_UDP = 0,\n\tSCTP_SOCKET_UDP_HIGH_BANDWIDTH = 1,\n\tSCTP_SOCKET_TCP = 2,\n};\n\nenum sctp_state {\n\tSCTP_STATE_CLOSED = 0,\n\tSCTP_STATE_COOKIE_WAIT = 1,\n\tSCTP_STATE_COOKIE_ECHOED = 2,\n\tSCTP_STATE_ESTABLISHED = 3,\n\tSCTP_STATE_SHUTDOWN_PENDING = 4,\n\tSCTP_STATE_SHUTDOWN_SENT = 5,\n\tSCTP_STATE_SHUTDOWN_RECEIVED = 6,\n\tSCTP_STATE_SHUTDOWN_ACK_SENT = 7,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 7500,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_HAS_CGROUP_WEIGHT = 65536ULL,\n\tSCX_OPS_ALL_FLAGS = 65663ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1,\n\t__SCX_REENQ_FILTER_MASK = 65535,\n\t__SCX_REENQ_USER_MASK = 1,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum sd_uhs2_operation {\n\tUHS2_PHY_INIT = 0,\n\tUHS2_SET_CONFIG = 1,\n\tUHS2_ENABLE_INT = 2,\n\tUHS2_DISABLE_INT = 3,\n\tUHS2_ENABLE_CLK = 4,\n\tUHS2_DISABLE_CLK = 5,\n\tUHS2_CHECK_DORMANT = 6,\n\tUHS2_SET_IOS = 7,\n};\n\nenum sdhci_cookie {\n\tCOOKIE_UNMAPPED___2 = 0,\n\tCOOKIE_PRE_MAPPED___2 = 1,\n\tCOOKIE_MAPPED___2 = 2,\n};\n\nenum sdhci_reset_reason {\n\tSDHCI_RESET_FOR_INIT = 0,\n\tSDHCI_RESET_FOR_REQUEST_ERROR = 1,\n\tSDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY = 2,\n\tSDHCI_RESET_FOR_TUNING_ABORT = 3,\n\tSDHCI_RESET_FOR_CARD_REMOVED = 4,\n\tSDHCI_RESET_FOR_CQE_RECOVERY = 5,\n};\n\nenum sel_inos {\n\tSEL_ROOT_INO = 2,\n\tSEL_LOAD = 3,\n\tSEL_ENFORCE = 4,\n\tSEL_CONTEXT = 5,\n\tSEL_ACCESS = 6,\n\tSEL_CREATE = 7,\n\tSEL_RELABEL = 8,\n\tSEL_USER = 9,\n\tSEL_POLICYVERS = 10,\n\tSEL_COMMIT_BOOLS = 11,\n\tSEL_MLS = 12,\n\tSEL_DISABLE = 13,\n\tSEL_MEMBER = 14,\n\tSEL_CHECKREQPROT = 15,\n\tSEL_COMPAT_NET = 16,\n\tSEL_REJECT_UNKNOWN = 17,\n\tSEL_DENY_UNKNOWN = 18,\n\tSEL_STATUS = 19,\n\tSEL_POLICY = 20,\n\tSEL_VALIDATE_TRANS = 21,\n\tSEL_INO_NEXT = 22,\n};\n\nenum selinux_nlgroups {\n\tSELNLGRP_NONE = 0,\n\tSELNLGRP_AVC = 1,\n\t__SELNLGRP_MAX = 2,\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nenum set_event_iter_type {\n\tSET_EVENT_FILE = 0,\n\tSET_EVENT_MOD = 1,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum shmem_param {\n\tOpt_gid___9 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___7 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes___2 = 5,\n\tOpt_size___2 = 6,\n\tOpt_uid___8 = 7,\n\tOpt_inode32 = 8,\n\tOpt_inode64 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota___2 = 11,\n\tOpt_usrquota___2 = 12,\n\tOpt_grpquota___2 = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_ext_id {\n\tSKB_EXT_BRIDGE_NF = 0,\n\tSKB_EXT_SEC_PATH = 1,\n\tSKB_EXT_CAN = 2,\n\tSKB_EXT_NUM = 3,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN = 0,\n\tPARTIAL = 1,\n\tUP = 2,\n\tFULL = 3,\n};\n\nenum smbios_attr_enum {\n\tSMBIOS_ATTR_NONE = 0,\n\tSMBIOS_ATTR_LABEL_SHOW = 1,\n\tSMBIOS_ATTR_INSTANCE_SHOW = 2,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum snd_compr_direction {\n\tSND_COMPRESS_PLAYBACK = 0,\n\tSND_COMPRESS_CAPTURE = 1,\n\tSND_COMPRESS_ACCEL = 2,\n};\n\nenum snd_ctl_add_mode {\n\tCTL_ADD_EXCLUSIVE = 0,\n\tCTL_REPLACE = 1,\n\tCTL_ADD_ON_REPLACE = 2,\n};\n\nenum snd_device_state {\n\tSNDRV_DEV_BUILD = 0,\n\tSNDRV_DEV_REGISTERED = 1,\n\tSNDRV_DEV_DISCONNECTED = 2,\n};\n\nenum snd_device_type {\n\tSNDRV_DEV_LOWLEVEL = 0,\n\tSNDRV_DEV_INFO = 1,\n\tSNDRV_DEV_BUS = 2,\n\tSNDRV_DEV_CODEC = 3,\n\tSNDRV_DEV_PCM = 4,\n\tSNDRV_DEV_COMPRESS = 5,\n\tSNDRV_DEV_RAWMIDI = 6,\n\tSNDRV_DEV_TIMER = 7,\n\tSNDRV_DEV_SEQUENCER = 8,\n\tSNDRV_DEV_HWDEP = 9,\n\tSNDRV_DEV_JACK = 10,\n\tSNDRV_DEV_CONTROL = 11,\n};\n\nenum snd_dma_sync_mode {\n\tSNDRV_DMA_SYNC_CPU = 0,\n\tSNDRV_DMA_SYNC_DEVICE = 1,\n};\n\nenum snd_jack_types {\n\tSND_JACK_HEADPHONE = 1,\n\tSND_JACK_MICROPHONE = 2,\n\tSND_JACK_HEADSET = 3,\n\tSND_JACK_LINEOUT = 4,\n\tSND_JACK_MECHANICAL = 8,\n\tSND_JACK_VIDEOOUT = 16,\n\tSND_JACK_AVOUT = 20,\n\tSND_JACK_LINEIN = 32,\n\tSND_JACK_USB = 64,\n\tSND_JACK_BTN_0 = 16384,\n\tSND_JACK_BTN_1 = 8192,\n\tSND_JACK_BTN_2 = 4096,\n\tSND_JACK_BTN_3 = 2048,\n\tSND_JACK_BTN_4 = 1024,\n\tSND_JACK_BTN_5 = 512,\n};\n\nenum snd_soc_bias_level {\n\tSND_SOC_BIAS_OFF = 0,\n\tSND_SOC_BIAS_STANDBY = 1,\n\tSND_SOC_BIAS_PREPARE = 2,\n\tSND_SOC_BIAS_ON = 3,\n};\n\nenum snd_soc_dapm_direction {\n\tSND_SOC_DAPM_DIR_IN = 0,\n\tSND_SOC_DAPM_DIR_OUT = 1,\n};\n\nenum snd_soc_dapm_type {\n\tsnd_soc_dapm_input = 0,\n\tsnd_soc_dapm_output = 1,\n\tsnd_soc_dapm_mux = 2,\n\tsnd_soc_dapm_demux = 3,\n\tsnd_soc_dapm_mixer = 4,\n\tsnd_soc_dapm_mixer_named_ctl = 5,\n\tsnd_soc_dapm_pga = 6,\n\tsnd_soc_dapm_out_drv = 7,\n\tsnd_soc_dapm_adc = 8,\n\tsnd_soc_dapm_dac = 9,\n\tsnd_soc_dapm_micbias = 10,\n\tsnd_soc_dapm_mic = 11,\n\tsnd_soc_dapm_hp = 12,\n\tsnd_soc_dapm_spk = 13,\n\tsnd_soc_dapm_line = 14,\n\tsnd_soc_dapm_switch = 15,\n\tsnd_soc_dapm_vmid = 16,\n\tsnd_soc_dapm_pre = 17,\n\tsnd_soc_dapm_post = 18,\n\tsnd_soc_dapm_supply = 19,\n\tsnd_soc_dapm_pinctrl = 20,\n\tsnd_soc_dapm_regulator_supply = 21,\n\tsnd_soc_dapm_clock_supply = 22,\n\tsnd_soc_dapm_aif_in = 23,\n\tsnd_soc_dapm_aif_out = 24,\n\tsnd_soc_dapm_siggen = 25,\n\tsnd_soc_dapm_sink = 26,\n\tsnd_soc_dapm_dai_in = 27,\n\tsnd_soc_dapm_dai_out = 28,\n\tsnd_soc_dapm_dai_link = 29,\n\tsnd_soc_dapm_kcontrol = 30,\n\tsnd_soc_dapm_buffer = 31,\n\tsnd_soc_dapm_scheduler = 32,\n\tsnd_soc_dapm_effect = 33,\n\tsnd_soc_dapm_src = 34,\n\tsnd_soc_dapm_asrc = 35,\n\tsnd_soc_dapm_encoder = 36,\n\tsnd_soc_dapm_decoder = 37,\n\tSND_SOC_DAPM_TYPE_COUNT = 38,\n};\n\nenum snd_soc_dobj_type {\n\tSND_SOC_DOBJ_NONE = 0,\n\tSND_SOC_DOBJ_MIXER = 1,\n\tSND_SOC_DOBJ_BYTES = 2,\n\tSND_SOC_DOBJ_ENUM = 3,\n\tSND_SOC_DOBJ_GRAPH = 4,\n\tSND_SOC_DOBJ_WIDGET = 5,\n\tSND_SOC_DOBJ_DAI_LINK = 6,\n\tSND_SOC_DOBJ_PCM = 7,\n\tSND_SOC_DOBJ_CODEC_LINK = 8,\n\tSND_SOC_DOBJ_BACKEND_LINK = 9,\n};\n\nenum snd_soc_dpcm_link_state {\n\tSND_SOC_DPCM_LINK_STATE_NEW = 0,\n\tSND_SOC_DPCM_LINK_STATE_FREE = 1,\n};\n\nenum snd_soc_dpcm_state {\n\tSND_SOC_DPCM_STATE_NEW = 0,\n\tSND_SOC_DPCM_STATE_OPEN = 1,\n\tSND_SOC_DPCM_STATE_HW_PARAMS = 2,\n\tSND_SOC_DPCM_STATE_PREPARE = 3,\n\tSND_SOC_DPCM_STATE_START = 4,\n\tSND_SOC_DPCM_STATE_STOP = 5,\n\tSND_SOC_DPCM_STATE_PAUSED = 6,\n\tSND_SOC_DPCM_STATE_SUSPEND = 7,\n\tSND_SOC_DPCM_STATE_HW_FREE = 8,\n\tSND_SOC_DPCM_STATE_CLOSE = 9,\n};\n\nenum snd_soc_dpcm_trigger {\n\tSND_SOC_DPCM_TRIGGER_PRE = 0,\n\tSND_SOC_DPCM_TRIGGER_POST = 1,\n};\n\nenum snd_soc_dpcm_update {\n\tSND_SOC_DPCM_UPDATE_NO = 0,\n\tSND_SOC_DPCM_UPDATE_BE = 1,\n\tSND_SOC_DPCM_UPDATE_FE = 2,\n};\n\nenum snd_soc_pcm_subclass {\n\tSND_SOC_PCM_CLASS_PCM = 0,\n\tSND_SOC_PCM_CLASS_BE = 1,\n};\n\nenum snd_soc_trigger_order {\n\tSND_SOC_TRIGGER_ORDER_DEFAULT = 0,\n\tSND_SOC_TRIGGER_ORDER_LDC = 1,\n\tSND_SOC_TRIGGER_ORDER_MAX = 2,\n};\n\nenum sndrv_ctl_event_type {\n\tSNDRV_CTL_EVENT_ELEM = 0,\n\tSNDRV_CTL_EVENT_LAST = 0,\n};\n\nenum snoop_when {\n\tSUBMIT = 0,\n\tCOMPLETE = 1,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum spacemit_gpio_registers {\n\tSPACEMIT_GPLR = 0,\n\tSPACEMIT_GPDR = 1,\n\tSPACEMIT_GPSR = 2,\n\tSPACEMIT_GPCR = 3,\n\tSPACEMIT_GRER = 4,\n\tSPACEMIT_GFER = 5,\n\tSPACEMIT_GEDR = 6,\n\tSPACEMIT_GSDR = 7,\n\tSPACEMIT_GCDR = 8,\n\tSPACEMIT_GSRER = 9,\n\tSPACEMIT_GCRER = 10,\n\tSPACEMIT_GSFER = 11,\n\tSPACEMIT_GCFER = 12,\n\tSPACEMIT_GAPMASK = 13,\n\tSPACEMIT_GCPMASK = 14,\n};\n\nenum spacemit_pin_io_type {\n\tIO_TYPE_NONE = 0,\n\tIO_TYPE_1V8 = 1,\n\tIO_TYPE_3V3 = 2,\n\tIO_TYPE_EXTERNAL = 3,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum spi_mem_data_dir {\n\tSPI_MEM_NO_DATA = 0,\n\tSPI_MEM_DATA_IN = 1,\n\tSPI_MEM_DATA_OUT = 2,\n};\n\nenum spi_nor_cmd_ext {\n\tSPI_NOR_EXT_NONE = 0,\n\tSPI_NOR_EXT_REPEAT = 1,\n\tSPI_NOR_EXT_INVERT = 2,\n\tSPI_NOR_EXT_HEX = 3,\n};\n\nenum spi_nor_option_flags {\n\tSNOR_F_HAS_SR_TB = 1,\n\tSNOR_F_NO_OP_CHIP_ERASE = 2,\n\tSNOR_F_BROKEN_RESET = 4,\n\tSNOR_F_4B_OPCODES = 8,\n\tSNOR_F_HAS_4BAIT = 16,\n\tSNOR_F_HAS_LOCK = 32,\n\tSNOR_F_HAS_16BIT_SR = 64,\n\tSNOR_F_NO_READ_CR = 128,\n\tSNOR_F_HAS_SR_TB_BIT6 = 256,\n\tSNOR_F_HAS_4BIT_BP = 512,\n\tSNOR_F_HAS_SR_BP3_BIT6 = 1024,\n\tSNOR_F_IO_MODE_EN_VOLATILE = 2048,\n\tSNOR_F_SOFT_RESET = 4096,\n\tSNOR_F_SWP_IS_VOLATILE = 8192,\n\tSNOR_F_RWW = 16384,\n\tSNOR_F_ECC = 32768,\n\tSNOR_F_NO_WP = 65536,\n\tSNOR_F_SWAP16 = 131072,\n};\n\nenum spi_nor_pp_command_index {\n\tSNOR_CMD_PP = 0,\n\tSNOR_CMD_PP_1_1_4 = 1,\n\tSNOR_CMD_PP_1_4_4 = 2,\n\tSNOR_CMD_PP_4_4_4 = 3,\n\tSNOR_CMD_PP_1_1_8 = 4,\n\tSNOR_CMD_PP_1_8_8 = 5,\n\tSNOR_CMD_PP_8_8_8 = 6,\n\tSNOR_CMD_PP_8_8_8_DTR = 7,\n\tSNOR_CMD_PP_MAX = 8,\n};\n\nenum spi_nor_protocol {\n\tSNOR_PROTO_1_1_1 = 65793,\n\tSNOR_PROTO_1_1_2 = 65794,\n\tSNOR_PROTO_1_1_4 = 65796,\n\tSNOR_PROTO_1_1_8 = 65800,\n\tSNOR_PROTO_1_2_2 = 66050,\n\tSNOR_PROTO_1_4_4 = 66564,\n\tSNOR_PROTO_1_8_8 = 67592,\n\tSNOR_PROTO_2_2_2 = 131586,\n\tSNOR_PROTO_4_4_4 = 263172,\n\tSNOR_PROTO_8_8_8 = 526344,\n\tSNOR_PROTO_1_1_1_DTR = 16843009,\n\tSNOR_PROTO_1_2_2_DTR = 16843266,\n\tSNOR_PROTO_1_4_4_DTR = 16843780,\n\tSNOR_PROTO_1_8_8_DTR = 16844808,\n\tSNOR_PROTO_8_8_8_DTR = 17303560,\n};\n\nenum spi_nor_read_command_index {\n\tSNOR_CMD_READ = 0,\n\tSNOR_CMD_READ_FAST = 1,\n\tSNOR_CMD_READ_1_1_1_DTR = 2,\n\tSNOR_CMD_READ_1_1_2 = 3,\n\tSNOR_CMD_READ_1_2_2 = 4,\n\tSNOR_CMD_READ_2_2_2 = 5,\n\tSNOR_CMD_READ_1_2_2_DTR = 6,\n\tSNOR_CMD_READ_1_1_4 = 7,\n\tSNOR_CMD_READ_1_4_4 = 8,\n\tSNOR_CMD_READ_4_4_4 = 9,\n\tSNOR_CMD_READ_1_4_4_DTR = 10,\n\tSNOR_CMD_READ_1_1_8 = 11,\n\tSNOR_CMD_READ_1_8_8 = 12,\n\tSNOR_CMD_READ_8_8_8 = 13,\n\tSNOR_CMD_READ_1_8_8_DTR = 14,\n\tSNOR_CMD_READ_8_8_8_DTR = 15,\n\tSNOR_CMD_READ_MAX = 16,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum state_protect_how4 {\n\tSP4_NONE = 0,\n\tSP4_MACH_CRED = 1,\n\tSP4_SSV = 2,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum stripetype4 {\n\tSTRIPE_SPARSE = 1,\n\tSTRIPE_DENSE = 2,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\nenum sun50i_iommu_aci {\n\tSUN50I_IOMMU_ACI_DO_NOT_USE = 0,\n\tSUN50I_IOMMU_ACI_NONE = 1,\n\tSUN50I_IOMMU_ACI_RD = 2,\n\tSUN50I_IOMMU_ACI_WR = 3,\n\tSUN50I_IOMMU_ACI_RD_WR = 4,\n};\n\nenum sunxi_desc_bias_voltage {\n\tBIAS_VOLTAGE_NONE = 0,\n\tBIAS_VOLTAGE_GRP_CONFIG = 1,\n\tBIAS_VOLTAGE_PIO_POW_MODE_SEL = 2,\n\tBIAS_VOLTAGE_PIO_POW_MODE_CTL = 3,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum suspend_stat_step {\n\tSUSPEND_WORKING = 0,\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nenum svc_auth_status {\n\tSVC_GARBAGE = 1,\n\tSVC_VALID = 2,\n\tSVC_NEGATIVE = 3,\n\tSVC_OK = 4,\n\tSVC_DROP = 5,\n\tSVC_CLOSE = 6,\n\tSVC_DENIED = 7,\n\tSVC_PENDING = 8,\n\tSVC_COMPLETE = 9,\n};\n\nenum sw_activity {\n\tOFF = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum syscall_work_bit {\n\tSYSCALL_WORK_BIT_SECCOMP = 0,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACEPOINT = 1,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACE = 2,\n\tSYSCALL_WORK_BIT_SYSCALL_EMU = 3,\n\tSYSCALL_WORK_BIT_SYSCALL_AUDIT = 4,\n\tSYSCALL_WORK_BIT_SYSCALL_USER_DISPATCH = 5,\n\tSYSCALL_WORK_BIT_SYSCALL_EXIT_TRAP = 6,\n\tSYSCALL_WORK_BIT_SYSCALL_RSEQ_SLICE = 7,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_fifo_command {\n\tTC_FIFO_REPLACE = 0,\n\tTC_FIFO_DESTROY = 1,\n\tTC_FIFO_STATS = 2,\n};\n\nenum tc_link_layer {\n\tTC_LINKLAYER_UNAWARE = 0,\n\tTC_LINKLAYER_ETHERNET = 1,\n\tTC_LINKLAYER_ATM = 2,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_root_command {\n\tTC_ROOT_GRAFT = 0,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tc_taprio_qopt_cmd {\n\tTAPRIO_CMD_REPLACE = 0,\n\tTAPRIO_CMD_DESTROY = 1,\n\tTAPRIO_CMD_STATS = 2,\n\tTAPRIO_CMD_QUEUE_STATS = 3,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcf_proto_ops_flags {\n\tTCF_PROTO_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_conntrack {\n\tTCP_CONNTRACK_NONE = 0,\n\tTCP_CONNTRACK_SYN_SENT = 1,\n\tTCP_CONNTRACK_SYN_RECV = 2,\n\tTCP_CONNTRACK_ESTABLISHED = 3,\n\tTCP_CONNTRACK_FIN_WAIT = 4,\n\tTCP_CONNTRACK_CLOSE_WAIT = 5,\n\tTCP_CONNTRACK_LAST_ACK = 6,\n\tTCP_CONNTRACK_TIME_WAIT = 7,\n\tTCP_CONNTRACK_CLOSE = 8,\n\tTCP_CONNTRACK_LISTEN = 9,\n\tTCP_CONNTRACK_MAX = 10,\n\tTCP_CONNTRACK_IGNORE = 11,\n\tTCP_CONNTRACK_RETRANS = 12,\n\tTCP_CONNTRACK_UNACK = 13,\n\tTCP_CONNTRACK_TIMEOUT_MAX = 14,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum tg_state_flags {\n\tTHROTL_TG_PENDING = 1,\n\tTHROTL_TG_WAS_EMPTY = 2,\n\tTHROTL_TG_IOPS_WAS_EMPTY = 4,\n\tTHROTL_TG_CANCELING = 8,\n};\n\nenum th1520_muxtype {\n\tTH1520_MUX_____ = 0,\n\tTH1520_MUX_GPIO = 1,\n\tTH1520_MUX_PWM = 2,\n\tTH1520_MUX_UART = 3,\n\tTH1520_MUX_IR = 4,\n\tTH1520_MUX_I2C = 5,\n\tTH1520_MUX_SPI = 6,\n\tTH1520_MUX_QSPI = 7,\n\tTH1520_MUX_SDIO = 8,\n\tTH1520_MUX_AUD = 9,\n\tTH1520_MUX_I2S = 10,\n\tTH1520_MUX_MAC0 = 11,\n\tTH1520_MUX_MAC1 = 12,\n\tTH1520_MUX_DPU0 = 13,\n\tTH1520_MUX_DPU1 = 14,\n\tTH1520_MUX_ISP = 15,\n\tTH1520_MUX_HDMI = 16,\n\tTH1520_MUX_BSEL = 17,\n\tTH1520_MUX_DBG = 18,\n\tTH1520_MUX_CLK = 19,\n\tTH1520_MUX_JTAG = 20,\n\tTH1520_MUX_ISO = 21,\n\tTH1520_MUX_FUSE = 22,\n\tTH1520_MUX_RST = 23,\n};\n\nenum thermal_device_mode {\n\tTHERMAL_DEVICE_DISABLED = 0,\n\tTHERMAL_DEVICE_ENABLED = 1,\n};\n\nenum thermal_notify_event {\n\tTHERMAL_EVENT_UNSPECIFIED = 0,\n\tTHERMAL_EVENT_TEMP_SAMPLE = 1,\n\tTHERMAL_TRIP_VIOLATED = 2,\n\tTHERMAL_TRIP_CHANGED = 3,\n\tTHERMAL_DEVICE_DOWN = 4,\n\tTHERMAL_DEVICE_UP = 5,\n\tTHERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6,\n\tTHERMAL_TABLE_CHANGED = 7,\n\tTHERMAL_EVENT_KEEP_ALIVE = 8,\n\tTHERMAL_TZ_BIND_CDEV = 9,\n\tTHERMAL_TZ_UNBIND_CDEV = 10,\n\tTHERMAL_INSTANCE_WEIGHT_CHANGED = 11,\n\tTHERMAL_TZ_RESUME = 12,\n\tTHERMAL_TZ_ADD_THRESHOLD = 13,\n\tTHERMAL_TZ_DEL_THRESHOLD = 14,\n\tTHERMAL_TZ_FLUSH_THRESHOLDS = 15,\n};\n\nenum thermal_trend {\n\tTHERMAL_TREND_STABLE = 0,\n\tTHERMAL_TREND_RAISING = 1,\n\tTHERMAL_TREND_DROPPING = 2,\n};\n\nenum thermal_trip_type {\n\tTHERMAL_TRIP_ACTIVE = 0,\n\tTHERMAL_TRIP_PASSIVE = 1,\n\tTHERMAL_TRIP_HOT = 2,\n\tTHERMAL_TRIP_CRITICAL = 3,\n};\n\nenum tick_broadcast_mode {\n\tTICK_BROADCAST_OFF = 0,\n\tTICK_BROADCAST_ON = 1,\n\tTICK_BROADCAST_FORCE = 2,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPERS_MAX = 1,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timer_tread_format {\n\tTREAD_FORMAT_NONE = 0,\n\tTREAD_FORMAT_TIME64 = 1,\n\tTREAD_FORMAT_TIME32 = 2,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum tp_func_state {\n\tTP_FUNC_0 = 0,\n\tTP_FUNC_1 = 1,\n\tTP_FUNC_2 = 2,\n\tTP_FUNC_N = 3,\n};\n\nenum tp_transition_sync {\n\tTP_TRANSITION_SYNC_1_0_1 = 0,\n\tTP_TRANSITION_SYNC_N_2_1 = 1,\n\t_NR_TP_TRANSITION_SYNC = 2,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tph_mem_type {\n\tTPH_MEM_TYPE_VM = 0,\n\tTPH_MEM_TYPE_PM = 1,\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_NEED_RESCHED_LAZY = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n\tTRACE_FLAG_BH_OFF = 128,\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n\tTRACE_FILE_PAUSE = 8,\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_FIELDS_BIT = 8,\n\tTRACE_ITER_PRINTK_BIT = 9,\n\tTRACE_ITER_ANNOTATE_BIT = 10,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 11,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 12,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 13,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 14,\n\tTRACE_ITER_LATENCY_FMT_BIT = 15,\n\tTRACE_ITER_RECORD_CMD_BIT = 16,\n\tTRACE_ITER_RECORD_TGID_BIT = 17,\n\tTRACE_ITER_OVERWRITE_BIT = 18,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 19,\n\tTRACE_ITER_IRQ_INFO_BIT = 20,\n\tTRACE_ITER_MARKERS_BIT = 21,\n\tTRACE_ITER_EVENT_FORK_BIT = 22,\n\tTRACE_ITER_TRACE_PRINTK_BIT = 23,\n\tTRACE_ITER_COPY_MARKER_BIT = 24,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 25,\n\tTRACE_ITER_HASH_PTR_BIT = 26,\n\tTRACE_ITER_BITMASK_LIST_BIT = 27,\n\tTRACE_ITER_STACKTRACE_BIT = 28,\n\tTRACE_ITER_LAST_BIT = 29,\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_GRAPH_RETADDR_ENT = 12,\n\tTRACE_USER_STACK = 13,\n\tTRACE_BLK = 14,\n\tTRACE_BPUTS = 15,\n\tTRACE_HWLAT = 16,\n\tTRACE_OSNOISE = 17,\n\tTRACE_TIMERLAT = 18,\n\tTRACE_RAW_DATA = 19,\n\tTRACE_FUNC_REPEATS = 20,\n\t__TRACE_LAST_TYPE = 21,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tunnel_encap_types {\n\tTUNNEL_ENCAP_NONE = 0,\n\tTUNNEL_ENCAP_FOU = 1,\n\tTUNNEL_ENCAP_GUE = 2,\n\tTUNNEL_ENCAP_MPLS = 3,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum uart_iotype {\n\tUPIO_UNKNOWN = -1,\n\tUPIO_PORT = 0,\n\tUPIO_HUB6 = 1,\n\tUPIO_MEM = 2,\n\tUPIO_MEM32 = 3,\n\tUPIO_AU = 4,\n\tUPIO_TSI = 5,\n\tUPIO_MEM32BE = 6,\n\tUPIO_MEM16 = 7,\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_COUNTS = 10,\n};\n\nenum udp_conntrack {\n\tUDP_CT_UNREPLIED = 0,\n\tUDP_CT_REPLIED = 1,\n\tUDP_CT_MAX = 2,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nenum usb3_link_state {\n\tUSB3_LPM_U0 = 0,\n\tUSB3_LPM_U1 = 1,\n\tUSB3_LPM_U2 = 2,\n\tUSB3_LPM_U3 = 3,\n};\n\nenum usb_charger_state {\n\tUSB_CHARGER_DEFAULT = 0,\n\tUSB_CHARGER_PRESENT = 1,\n\tUSB_CHARGER_ABSENT = 2,\n};\n\nenum usb_charger_type {\n\tUNKNOWN_TYPE = 0,\n\tSDP_TYPE = 1,\n\tDCP_TYPE = 2,\n\tCDP_TYPE = 3,\n\tACA_TYPE = 4,\n};\n\nenum usb_dev_authorize_policy {\n\tUSB_DEVICE_AUTHORIZE_NONE = 0,\n\tUSB_DEVICE_AUTHORIZE_ALL = 1,\n\tUSB_DEVICE_AUTHORIZE_INTERNAL = 2,\n};\n\nenum usb_device_speed {\n\tUSB_SPEED_UNKNOWN = 0,\n\tUSB_SPEED_LOW = 1,\n\tUSB_SPEED_FULL = 2,\n\tUSB_SPEED_HIGH = 3,\n\tUSB_SPEED_WIRELESS = 4,\n\tUSB_SPEED_SUPER = 5,\n\tUSB_SPEED_SUPER_PLUS = 6,\n};\n\nenum usb_device_state {\n\tUSB_STATE_NOTATTACHED = 0,\n\tUSB_STATE_ATTACHED = 1,\n\tUSB_STATE_POWERED = 2,\n\tUSB_STATE_RECONNECTING = 3,\n\tUSB_STATE_UNAUTHENTICATED = 4,\n\tUSB_STATE_DEFAULT = 5,\n\tUSB_STATE_ADDRESS = 6,\n\tUSB_STATE_CONFIGURED = 7,\n\tUSB_STATE_SUSPENDED = 8,\n};\n\nenum usb_dr_mode {\n\tUSB_DR_MODE_UNKNOWN = 0,\n\tUSB_DR_MODE_HOST = 1,\n\tUSB_DR_MODE_PERIPHERAL = 2,\n\tUSB_DR_MODE_OTG = 3,\n};\n\nenum usb_interface_condition {\n\tUSB_INTERFACE_UNBOUND = 0,\n\tUSB_INTERFACE_BINDING = 1,\n\tUSB_INTERFACE_BOUND = 2,\n\tUSB_INTERFACE_UNBINDING = 3,\n};\n\nenum usb_led_event {\n\tUSB_LED_EVENT_HOST = 0,\n\tUSB_LED_EVENT_GADGET = 1,\n};\n\nenum usb_link_tunnel_mode {\n\tUSB_LINK_UNKNOWN = 0,\n\tUSB_LINK_NATIVE = 1,\n\tUSB_LINK_TUNNELED = 2,\n};\n\nenum usb_otg_state {\n\tOTG_STATE_UNDEFINED = 0,\n\tOTG_STATE_B_IDLE = 1,\n\tOTG_STATE_B_SRP_INIT = 2,\n\tOTG_STATE_B_PERIPHERAL = 3,\n\tOTG_STATE_B_WAIT_ACON = 4,\n\tOTG_STATE_B_HOST = 5,\n\tOTG_STATE_A_IDLE = 6,\n\tOTG_STATE_A_WAIT_VRISE = 7,\n\tOTG_STATE_A_WAIT_BCON = 8,\n\tOTG_STATE_A_HOST = 9,\n\tOTG_STATE_A_SUSPEND = 10,\n\tOTG_STATE_A_PERIPHERAL = 11,\n\tOTG_STATE_A_WAIT_VFALL = 12,\n\tOTG_STATE_A_VBUS_ERR = 13,\n};\n\nenum usb_phy_events {\n\tUSB_EVENT_NONE = 0,\n\tUSB_EVENT_VBUS = 1,\n\tUSB_EVENT_ID = 2,\n\tUSB_EVENT_CHARGER = 3,\n\tUSB_EVENT_ENUMERATED = 4,\n};\n\nenum usb_phy_interface {\n\tUSBPHY_INTERFACE_MODE_UNKNOWN = 0,\n\tUSBPHY_INTERFACE_MODE_UTMI = 1,\n\tUSBPHY_INTERFACE_MODE_UTMIW = 2,\n\tUSBPHY_INTERFACE_MODE_ULPI = 3,\n\tUSBPHY_INTERFACE_MODE_SERIAL = 4,\n\tUSBPHY_INTERFACE_MODE_HSIC = 5,\n};\n\nenum usb_phy_type {\n\tUSB_PHY_TYPE_UNDEFINED = 0,\n\tUSB_PHY_TYPE_USB2 = 1,\n\tUSB_PHY_TYPE_USB3 = 2,\n};\n\nenum usb_port_connect_type {\n\tUSB_PORT_CONNECT_TYPE_UNKNOWN = 0,\n\tUSB_PORT_CONNECT_TYPE_HOT_PLUG = 1,\n\tUSB_PORT_CONNECT_TYPE_HARD_WIRED = 2,\n\tUSB_PORT_NOT_USED = 3,\n};\n\nenum usb_ssp_rate {\n\tUSB_SSP_GEN_UNKNOWN = 0,\n\tUSB_SSP_GEN_2x1 = 1,\n\tUSB_SSP_GEN_1x2 = 2,\n\tUSB_SSP_GEN_2x2 = 3,\n};\n\nenum usb_wireless_status {\n\tUSB_WIRELESS_STATUS_NA = 0,\n\tUSB_WIRELESS_STATUS_DISCONNECTED = 1,\n\tUSB_WIRELESS_STATUS_CONNECTED = 2,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum v4l2_av1_segment_feature {\n\tV4L2_AV1_SEG_LVL_ALT_Q = 0,\n\tV4L2_AV1_SEG_LVL_ALT_LF_Y_V = 1,\n\tV4L2_AV1_SEG_LVL_REF_FRAME = 5,\n\tV4L2_AV1_SEG_LVL_REF_SKIP = 6,\n\tV4L2_AV1_SEG_LVL_REF_GLOBALMV = 7,\n\tV4L2_AV1_SEG_LVL_MAX = 8,\n};\n\nenum v4l2_fwnode_bus_type {\n\tV4L2_FWNODE_BUS_TYPE_GUESS = 0,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_CPHY = 1,\n\tV4L2_FWNODE_BUS_TYPE_CSI1 = 2,\n\tV4L2_FWNODE_BUS_TYPE_CCP2 = 3,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_DPHY = 4,\n\tV4L2_FWNODE_BUS_TYPE_PARALLEL = 5,\n\tV4L2_FWNODE_BUS_TYPE_BT656 = 6,\n\tV4L2_FWNODE_BUS_TYPE_DPI = 7,\n\tNR_OF_V4L2_FWNODE_BUS_TYPE = 8,\n};\n\nenum v4l2_preemphasis {\n\tV4L2_PREEMPHASIS_DISABLED = 0,\n\tV4L2_PREEMPHASIS_50_uS = 1,\n\tV4L2_PREEMPHASIS_75_uS = 2,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_ARCHTIMER = 1,\n\tVDSO_CLOCKMODE_MAX = 2,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum virtio_balloon_config_read {\n\tVIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0,\n};\n\nenum virtio_balloon_vq {\n\tVIRTIO_BALLOON_VQ_INFLATE = 0,\n\tVIRTIO_BALLOON_VQ_DEFLATE = 1,\n\tVIRTIO_BALLOON_VQ_STATS = 2,\n\tVIRTIO_BALLOON_VQ_FREE_PAGE = 3,\n\tVIRTIO_BALLOON_VQ_REPORTING = 4,\n\tVIRTIO_BALLOON_VQ_MAX = 5,\n};\n\nenum virtio_input_config_select {\n\tVIRTIO_INPUT_CFG_UNSET = 0,\n\tVIRTIO_INPUT_CFG_ID_NAME = 1,\n\tVIRTIO_INPUT_CFG_ID_SERIAL = 2,\n\tVIRTIO_INPUT_CFG_ID_DEVIDS = 3,\n\tVIRTIO_INPUT_CFG_PROP_BITS = 16,\n\tVIRTIO_INPUT_CFG_EV_BITS = 17,\n\tVIRTIO_INPUT_CFG_ABS_INFO = 18,\n};\n\nenum virtnet_xmit_type {\n\tVIRTNET_XMIT_TYPE_SKB = 0,\n\tVIRTNET_XMIT_TYPE_SKB_ORPHAN = 1,\n\tVIRTNET_XMIT_TYPE_XDP = 2,\n\tVIRTNET_XMIT_TYPE_XSK = 3,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vlan_flags {\n\tVLAN_FLAG_REORDER_HDR = 1,\n\tVLAN_FLAG_GVRP = 2,\n\tVLAN_FLAG_LOOSE_BINDING = 4,\n\tVLAN_FLAG_MVRP = 8,\n\tVLAN_FLAG_BRIDGE_BINDING = 16,\n};\n\nenum vlan_protos {\n\tVLAN_PROTO_8021Q = 0,\n\tVLAN_PROTO_8021AD = 1,\n\tVLAN_PROTO_NUM = 2,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_DMA32 = 4,\n\tPGALLOC_NORMAL = 5,\n\tPGALLOC_MOVABLE = 6,\n\tALLOCSTALL_DMA32 = 7,\n\tALLOCSTALL_NORMAL = 8,\n\tALLOCSTALL_MOVABLE = 9,\n\tPGSCAN_SKIP_DMA32 = 10,\n\tPGSCAN_SKIP_NORMAL = 11,\n\tPGSCAN_SKIP_MOVABLE = 12,\n\tPGFREE = 13,\n\tPGACTIVATE = 14,\n\tPGDEACTIVATE = 15,\n\tPGLAZYFREE = 16,\n\tPGFAULT = 17,\n\tPGMAJFAULT = 18,\n\tPGLAZYFREED = 19,\n\tPGREFILL = 20,\n\tPGREUSE = 21,\n\tPGSTEAL_KSWAPD = 22,\n\tPGSTEAL_DIRECT = 23,\n\tPGSTEAL_KHUGEPAGED = 24,\n\tPGSTEAL_PROACTIVE = 25,\n\tPGSCAN_KSWAPD = 26,\n\tPGSCAN_DIRECT = 27,\n\tPGSCAN_KHUGEPAGED = 28,\n\tPGSCAN_PROACTIVE = 29,\n\tPGSCAN_DIRECT_THROTTLE = 30,\n\tPGSCAN_ANON = 31,\n\tPGSCAN_FILE = 32,\n\tPGSTEAL_ANON = 33,\n\tPGSTEAL_FILE = 34,\n\tPGSCAN_ZONE_RECLAIM_SUCCESS = 35,\n\tPGSCAN_ZONE_RECLAIM_FAILED = 36,\n\tPGINODESTEAL = 37,\n\tSLABS_SCANNED = 38,\n\tKSWAPD_INODESTEAL = 39,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 40,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 41,\n\tPAGEOUTRUN = 42,\n\tPGROTATED = 43,\n\tDROP_PAGECACHE = 44,\n\tDROP_SLAB = 45,\n\tOOM_KILL = 46,\n\tNUMA_PTE_UPDATES = 47,\n\tNUMA_HUGE_PTE_UPDATES = 48,\n\tNUMA_HINT_FAULTS = 49,\n\tNUMA_HINT_FAULTS_LOCAL = 50,\n\tNUMA_PAGE_MIGRATE = 51,\n\tPGMIGRATE_SUCCESS = 52,\n\tPGMIGRATE_FAIL = 53,\n\tTHP_MIGRATION_SUCCESS = 54,\n\tTHP_MIGRATION_FAIL = 55,\n\tTHP_MIGRATION_SPLIT = 56,\n\tCOMPACTMIGRATE_SCANNED = 57,\n\tCOMPACTFREE_SCANNED = 58,\n\tCOMPACTISOLATED = 59,\n\tCOMPACTSTALL = 60,\n\tCOMPACTFAIL = 61,\n\tCOMPACTSUCCESS = 62,\n\tKCOMPACTD_WAKE = 63,\n\tKCOMPACTD_MIGRATE_SCANNED = 64,\n\tKCOMPACTD_FREE_SCANNED = 65,\n\tHTLB_BUDDY_PGALLOC = 66,\n\tHTLB_BUDDY_PGALLOC_FAIL = 67,\n\tUNEVICTABLE_PGCULLED = 68,\n\tUNEVICTABLE_PGSCANNED = 69,\n\tUNEVICTABLE_PGRESCUED = 70,\n\tUNEVICTABLE_PGMLOCKED = 71,\n\tUNEVICTABLE_PGMUNLOCKED = 72,\n\tUNEVICTABLE_PGCLEARED = 73,\n\tUNEVICTABLE_PGSTRANDED = 74,\n\tBALLOON_INFLATE = 75,\n\tBALLOON_DEFLATE = 76,\n\tBALLOON_MIGRATE = 77,\n\tSWAP_RA = 78,\n\tSWAP_RA_HIT = 79,\n\tSWPIN_ZERO = 80,\n\tSWPOUT_ZERO = 81,\n\tNR_VM_EVENT_ITEMS = 82,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vma_resv_mode {\n\tVMA_NEEDS_RESV = 0,\n\tVMA_COMMIT_RESV = 1,\n\tVMA_END_RESV = 2,\n\tVMA_ADD_RESV = 3,\n\tVMA_DEL_RESV = 4,\n};\n\nenum vmpressure_levels {\n\tVMPRESSURE_LOW = 0,\n\tVMPRESSURE_MEDIUM = 1,\n\tVMPRESSURE_CRITICAL = 2,\n\tVMPRESSURE_NUM_LEVELS = 3,\n};\n\nenum vmpressure_modes {\n\tVMPRESSURE_NO_PASSTHROUGH = 0,\n\tVMPRESSURE_HIERARCHY = 1,\n\tVMPRESSURE_LOCAL = 2,\n\tVMPRESSURE_NUM_MODES = 3,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum vp_vq_vector_policy {\n\tVP_VQ_VECTOR_POLICY_EACH = 0,\n\tVP_VQ_VECTOR_POLICY_SHARED_SLOW = 1,\n\tVP_VQ_VECTOR_POLICY_SHARED = 2,\n};\n\nenum vq_layout {\n\tVQ_LAYOUT_SPLIT = 0,\n\tVQ_LAYOUT_PACKED = 1,\n\tVQ_LAYOUT_SPLIT_IN_ORDER = 2,\n\tVQ_LAYOUT_PACKED_IN_ORDER = 3,\n};\n\nenum vsc85xx_global_phy {\n\tVSC88XX_BASE_ADDR = 0,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum why_no_delegation4 {\n\tWND4_NOT_WANTED = 0,\n\tWND4_CONTENTION = 1,\n\tWND4_RESOURCE = 2,\n\tWND4_NOT_SUPP_FTYPE = 3,\n\tWND4_WRITE_DELEG_NOT_SUPP_FTYPE = 4,\n\tWND4_NOT_SUPP_UPGRADE = 5,\n\tWND4_NOT_SUPP_DOWNGRADE = 6,\n\tWND4_CANCELLED = 7,\n\tWND4_IS_DIR = 8,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 43,\n\tWORK_OFFQ_POOL_BITS = 31,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 75000,\n\tMAYDAY_INITIAL_TIMEOUT = 2,\n\tMAYDAY_INTERVAL = 25,\n\tCREATE_COOLDOWN = 250,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 64,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xfer_buf_dir {\n\tTO_XFER_BUF = 0,\n\tFROM_XFER_BUF = 1,\n};\n\nenum xfrm_ae_ftype_t {\n\tXFRM_AE_UNSPEC = 0,\n\tXFRM_AE_RTHR = 1,\n\tXFRM_AE_RVAL = 2,\n\tXFRM_AE_LVAL = 4,\n\tXFRM_AE_ETHR = 8,\n\tXFRM_AE_CR = 16,\n\tXFRM_AE_CE = 32,\n\tXFRM_AE_CU = 64,\n\t__XFRM_AE_MAX = 65,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_nlgroups {\n\tXFRMNLGRP_NONE = 0,\n\tXFRMNLGRP_ACQUIRE = 1,\n\tXFRMNLGRP_EXPIRE = 2,\n\tXFRMNLGRP_SA = 3,\n\tXFRMNLGRP_POLICY = 4,\n\tXFRMNLGRP_AEVENTS = 5,\n\tXFRMNLGRP_REPORT = 6,\n\tXFRMNLGRP_MIGRATE = 7,\n\tXFRMNLGRP_MAPPING = 8,\n\t__XFRMNLGRP_MAX = 9,\n};\n\nenum xfrm_pol_inexact_candidate_type {\n\tXFRM_POL_CAND_BOTH = 0,\n\tXFRM_POL_CAND_SADDR = 1,\n\tXFRM_POL_CAND_DADDR = 2,\n\tXFRM_POL_CAND_ANY = 3,\n\tXFRM_POL_CAND_MAX = 4,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xfrm_sa_dir {\n\tXFRM_SA_DIR_IN = 1,\n\tXFRM_SA_DIR_OUT = 2,\n};\n\nenum xhci_cancelled_td_status {\n\tTD_DIRTY = 0,\n\tTD_HALTED = 1,\n\tTD_CLEARING_CACHE = 2,\n\tTD_CLEARING_CACHE_DEFERRED = 3,\n\tTD_CLEARED = 4,\n};\n\nenum xhci_ep_reset_type {\n\tEP_HARD_RESET = 0,\n\tEP_SOFT_RESET = 1,\n};\n\nenum xhci_overhead_type {\n\tLS_OVERHEAD_TYPE = 0,\n\tFS_OVERHEAD_TYPE = 1,\n\tHS_OVERHEAD_TYPE = 2,\n};\n\nenum xhci_ring_type {\n\tTYPE_CTRL = 0,\n\tTYPE_ISOC = 1,\n\tTYPE_BULK = 2,\n\tTYPE_INTR = 3,\n\tTYPE_STREAM = 4,\n\tTYPE_COMMAND = 5,\n\tTYPE_EVENT = 6,\n};\n\nenum xhci_setup_dev {\n\tSETUP_CONTEXT_ONLY = 0,\n\tSETUP_CONTEXT_ADDRESS = 1,\n};\n\nenum xhci_sideband_notify_type {\n\tXHCI_SIDEBAND_XFER_RING_FREE = 0,\n};\n\nenum xhci_sideband_type {\n\tXHCI_SIDEBAND_AUDIO = 0,\n\tXHCI_SIDEBAND_VENDOR = 1,\n};\n\nenum xprt_transports {\n\tXPRT_TRANSPORT_UDP = 17,\n\tXPRT_TRANSPORT_TCP = 6,\n\tXPRT_TRANSPORT_BC_TCP = -2147483642,\n\tXPRT_TRANSPORT_RDMA = 256,\n\tXPRT_TRANSPORT_BC_RDMA = -2147483392,\n\tXPRT_TRANSPORT_LOCAL = 257,\n\tXPRT_TRANSPORT_TCP_TLS = 258,\n};\n\nenum xprt_xid_rb_cmp {\n\tXID_RB_EQUAL = 0,\n\tXID_RB_LEFT = 1,\n\tXID_RB_RIGHT = 2,\n};\n\nenum xprtsec_policies {\n\tRPC_XPRTSEC_NONE = 0,\n\tRPC_XPRTSEC_TLS_ANON = 1,\n\tRPC_XPRTSEC_TLS_X509 = 2,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_FREE_CMA_PAGES = 9,\n\tNR_VM_ZONE_STAT_ITEMS = 10,\n};\n\nenum zone_type {\n\tZONE_DMA32 = 0,\n\tZONE_NORMAL = 1,\n\tZONE_MOVABLE = 2,\n\t__MAX_NR_ZONES = 3,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\ntypedef _Bool bool;\n\ntypedef __int128 unsigned __u128;\n\ntypedef __u128 u128;\n\ntypedef char __pad_after_uframe[0];\n\ntypedef char __pad_before_u32[0];\n\ntypedef char __pad_before_uframe[0];\n\ntypedef char acpi_bus_id[8];\n\ntypedef char acpi_device_class[20];\n\ntypedef char acpi_device_name[40];\n\ntypedef char *acpi_string;\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_daddr_t;\n\ntypedef int __kernel_ipc_pid_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_mqd_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __s32;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef __s32 s32;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_daddr_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_ipc_pid_t;\n\ntypedef s32 compat_key_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_off_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef s32 dma_cookie_t;\n\ntypedef int ext4_grpblk_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef int kprobe_opcode_t;\n\ntypedef int mm_id_mapcount_t;\n\ntypedef __kernel_mqd_t mqd_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef __s32 sctp_assoc_t;\n\ntypedef int snd_ctl_elem_iface_t;\n\ntypedef int snd_ctl_elem_type_t;\n\ntypedef int snd_pcm_access_t;\n\ntypedef int snd_pcm_format_t;\n\ntypedef int snd_pcm_hw_param_t;\n\ntypedef int snd_pcm_state_t;\n\ntypedef int snd_pcm_subformat_t;\n\ntypedef int suspend_state_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef int vma_flag_t;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_long_t __kernel_ptrdiff_t;\n\ntypedef __kernel_long_t __kernel_ssize_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef long int snd_pcm_sframes_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 Elf64_Sxword;\n\ntypedef __s64 s64;\n\ntypedef s64 int64_t;\n\ntypedef int64_t S64;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef s64 compat_loff_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef long long int qsize_t;\n\ntypedef __s64 time64_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef U64 ZSTD_VecMask;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef __u64 __virtio64;\n\ntypedef u64 acpi_bus_address;\n\ntypedef u64 acpi_integer;\n\ntypedef u64 acpi_io_address;\n\ntypedef u64 acpi_physical_address;\n\ntypedef u64 acpi_size;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 clientid4;\n\ntypedef u64 compat_u64;\n\ntypedef u64 dma_addr_t;\n\ntypedef u64 efi_physical_addr_t;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef __be64 fdt64_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef long long unsigned int llu;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 pci_bus_addr_t;\n\ntypedef u64 phys_addr_t;\n\ntypedef u64 phys_cpuid_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u64 sci_t;\n\ntypedef u64 sector_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef u64 u_int64_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef u64 upf_t;\n\ntypedef uint64_t vli_type;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef __kernel_ulong_t __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef size_t HUF_CElt;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int cycles_t;\n\ntypedef long unsigned int efi_status_t;\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int perf_trace_t[1024];\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int snd_pcm_uframes_t;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int u_long;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef __u16 __hc16;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __rpmsg16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef u16 acpi_owner_id;\n\ntypedef u16 acpi_rs_length;\n\ntypedef u16 compat_ushort_t;\n\ntypedef u16 efi_char16_t;\n\ntypedef __kernel_gid16_t gid16_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef __u16 port_id;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef u16 u_int16_t;\n\ntypedef short unsigned int u_short;\n\ntypedef u16 ucs2_char_t;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef u16 wchar_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 acpi_adr_space_type;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef u8 dscp_t;\n\ntypedef __u8 dvd_challenge[10];\n\ntypedef __u8 dvd_key[5];\n\ntypedef u8 efi_bool_t;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef __u8 virtio_net_ctrl_ack;\n\ntypedef unsigned int __u32;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_CTable;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef __u32 u32;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef __u32 __be32;\n\ntypedef u32 __compat_gid32_t;\n\ntypedef u32 __compat_gid_t;\n\ntypedef u32 __compat_uid32_t;\n\ntypedef u32 __compat_uid_t;\n\ntypedef __u32 __hc32;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_gid_t;\n\ntypedef unsigned int __kernel_mode_t;\n\ntypedef unsigned int __kernel_old_dev_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __rpmsg32;\n\ntypedef __u32 __virtio32;\n\ntypedef __u32 __wsum;\n\ntypedef u32 acpi_event_status;\n\ntypedef u32 acpi_mutex_handle;\n\ntypedef u32 acpi_name;\n\ntypedef u32 acpi_object_type;\n\ntypedef u32 acpi_rsdesc_size;\n\ntypedef u32 acpi_status;\n\ntypedef unsigned int autofs_wqt_t;\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef u32 bug_insn_t;\n\ntypedef u32 compat_aio_context_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_dev_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef compat_ulong_t compat_elf_greg_t;\n\ntypedef compat_elf_greg_t compat_elf_gregset_t[32];\n\ntypedef u32 compat_ino_t;\n\ntypedef u32 compat_mode_t;\n\ntypedef u32 compat_sigset_word;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef u32 crc_t;\n\ntypedef u32 depot_flags_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef u32 efi_cc_event_algorithm_bitmap_t;\n\ntypedef u32 efi_cc_event_log_bitmap_t;\n\ntypedef u32 efi_cc_event_log_format_t;\n\ntypedef u32 efi_cc_mr_index_t;\n\ntypedef u32 efi_tcg2_event_log_format;\n\ntypedef u32 errseq_t;\n\ntypedef unsigned int ext4_group_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef __be32 fdt32_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef unsigned int ioasid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef unsigned int mm_id_t;\n\ntypedef unsigned int mmc_pm_flag_t;\n\ntypedef __kernel_mode_t mode_t;\n\ntypedef u32 nlink_t;\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef unsigned int pipe_index_t;\n\ntypedef u32 probe_opcode_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef u32 rpc_authflavor_t;\n\ntypedef __be32 rpc_fraghdr;\n\ntypedef unsigned int sk_buff_data_t;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int speed_t;\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int tid_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef u32 u_int32_t;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef u32 uprobe_opcode_t;\n\ntypedef unsigned int upstat_t;\n\ntypedef u32 usb_port_location_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitPos;\n\tchar *startPtr;\n\tchar *ptr;\n\tchar *endPtr;\n} BIT_CStream_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tsize_t nbSequences;\n\tsize_t blockSize;\n\tsize_t litSize;\n} BlockSummary;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\ntypedef struct {\n\tsize_t estLitSize;\n\tsize_t estBlockSize;\n} EstimatedBlockSize;\n\ntypedef struct {\n\tunsigned int events[1024];\n\tsize_t nbEvents;\n} Fingerprint;\n\ntypedef struct {\n\tFingerprint pastEvents;\n\tFingerprint newEvents;\n} FPStats;\n\ntypedef struct {\n\tptrdiff_t value;\n\tconst void *stateTable;\n\tconst void *symbolTT;\n\tunsigned int stateLog;\n} FSE_CState_t;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tint deltaFindState;\n\tU32 deltaNbBits;\n} FSE_symbolCompressionTransform;\n\ntypedef struct {\n\tsize_t bitContainer[2];\n\tsize_t bitPos[2];\n\tBYTE *startPtr;\n\tBYTE *ptr;\n\tBYTE *endPtr;\n} HUF_CStream_t;\n\ntypedef struct {\n\tBYTE tableLog;\n\tBYTE maxSymbolValue;\n\tBYTE unused[6];\n} HUF_CTableHeader;\n\ntypedef struct {\n\tFSE_CTable CTable[59];\n\tU32 scratchBuffer[41];\n\tunsigned int count[13];\n\tS16 norm[13];\n} HUF_CompressWeightsWksp;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\ntypedef struct {\n\tHUF_CompressWeightsWksp wksp;\n\tBYTE bitsToWeight[13];\n\tBYTE huffWeight[255];\n} HUF_WriteCTableWksp;\n\nstruct nodeElt_s {\n\tU32 count;\n\tU16 parent;\n\tBYTE byte;\n\tBYTE nbBits;\n};\n\ntypedef struct nodeElt_s nodeElt;\n\ntypedef nodeElt huffNodeTable[512];\n\ntypedef struct {\n\tU16 base;\n\tU16 curr;\n} rankPos;\n\ntypedef struct {\n\thuffNodeTable huffNodeTbl;\n\trankPos rankPosition[192];\n} HUF_buildCTable_wksp_tables;\n\ntypedef struct {\n\tunsigned int count[256];\n\tHUF_CElt CTable[257];\n\tunion {\n\t\tHUF_buildCTable_wksp_tables buildCTable_wksp;\n\t\tHUF_WriteCTableWksp writeCTable_wksp;\n\t\tU32 hist_wksp[1024];\n\t} wksps;\n} HUF_compress_tables_t;\n\nstruct buffer_head;\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\ntypedef struct {\n\tU32 offset;\n\tU32 litLength;\n\tU32 matchLength;\n} rawSeq;\n\ntypedef struct {\n\trawSeq *seq;\n\tsize_t pos;\n\tsize_t posInSequence;\n\tsize_t size;\n\tsize_t capacity;\n} RawSeqStore_t;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\ntypedef struct {\n\tunsigned int offset;\n\tunsigned int litLength;\n\tunsigned int matchLength;\n\tunsigned int rep;\n} ZSTD_Sequence;\n\ntypedef struct {\n\tint collectSequences;\n\tZSTD_Sequence *seqStart;\n\tsize_t seqIndex;\n\tsize_t maxSequences;\n} SeqCollector;\n\nstruct SeqDef_s;\n\ntypedef struct SeqDef_s SeqDef;\n\ntypedef struct {\n\tSeqDef *sequencesStart;\n\tSeqDef *sequences;\n\tBYTE *litStart;\n\tBYTE *lit;\n\tBYTE *llCode;\n\tBYTE *mlCode;\n\tBYTE *ofCode;\n\tsize_t maxNbSeq;\n\tsize_t maxNbLit;\n\tZSTD_longLengthType_e longLengthType;\n\tU32 longLengthPos;\n} SeqStore_t;\n\ntypedef struct {\n\tS16 norm[53];\n\tU32 wksp[285];\n} ZSTD_BuildCTableWksp;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tU32 litLength;\n\tU32 matchLength;\n} ZSTD_SequenceLength;\n\ntypedef struct {\n\tU32 idx;\n\tU32 posInSequence;\n\tsize_t posInSrc;\n} ZSTD_SequencePosition;\n\ntypedef struct {\n\tSymbolEncodingType_e hType;\n\tBYTE hufDesBuffer[128];\n\tsize_t hufDesSize;\n} ZSTD_hufCTablesMetadata_t;\n\ntypedef struct {\n\tSymbolEncodingType_e llType;\n\tSymbolEncodingType_e ofType;\n\tSymbolEncodingType_e mlType;\n\tBYTE fseTablesBuffer[133];\n\tsize_t fseTablesSize;\n\tsize_t lastCountSize;\n} ZSTD_fseCTablesMetadata_t;\n\ntypedef struct {\n\tZSTD_hufCTablesMetadata_t hufMetadata;\n\tZSTD_fseCTablesMetadata_t fseMetadata;\n} ZSTD_entropyCTablesMetadata_t;\n\ntypedef struct {\n\tSeqStore_t fullSeqStoreChunk;\n\tSeqStore_t firstHalfSeqStore;\n\tSeqStore_t secondHalfSeqStore;\n\tSeqStore_t currSeqStore;\n\tSeqStore_t nextSeqStore;\n\tU32 partitions[196];\n\tZSTD_entropyCTablesMetadata_t entropyMetadata;\n} ZSTD_blockSplitCtx;\n\ntypedef struct {\n\tHUF_CElt CTable[257];\n\tHUF_repeat repeatMode;\n} ZSTD_hufCTables_t;\n\ntypedef struct {\n\tFSE_CTable offcodeCTable[193];\n\tFSE_CTable matchlengthCTable[363];\n\tFSE_CTable litlengthCTable[329];\n\tFSE_repeat offcode_repeatMode;\n\tFSE_repeat matchlength_repeatMode;\n\tFSE_repeat litlength_repeatMode;\n} ZSTD_fseCTables_t;\n\ntypedef struct {\n\tZSTD_hufCTables_t huf;\n\tZSTD_fseCTables_t fse;\n} ZSTD_entropyCTables_t;\n\ntypedef struct {\n\tZSTD_entropyCTables_t entropy;\n\tU32 rep[3];\n} ZSTD_compressedBlockState_t;\n\ntypedef struct {\n\tconst BYTE *nextSrc;\n\tconst BYTE *base;\n\tconst BYTE *dictBase;\n\tU32 dictLimit;\n\tU32 lowLimit;\n\tU32 nbOverflowCorrections;\n} ZSTD_window_t;\n\ntypedef struct {\n\tU32 off;\n\tU32 len;\n} ZSTD_match_t;\n\ntypedef struct {\n\tint price;\n\tU32 off;\n\tU32 mlen;\n\tU32 litlen;\n\tU32 rep[3];\n} ZSTD_optimal_t;\n\ntypedef struct {\n\tunsigned int *litFreq;\n\tunsigned int *litLengthFreq;\n\tunsigned int *matchLengthFreq;\n\tunsigned int *offCodeFreq;\n\tZSTD_match_t *matchTable;\n\tZSTD_optimal_t *priceTable;\n\tU32 litSum;\n\tU32 litLengthSum;\n\tU32 matchLengthSum;\n\tU32 offCodeSum;\n\tU32 litSumBasePrice;\n\tU32 litLengthSumBasePrice;\n\tU32 matchLengthSumBasePrice;\n\tU32 offCodeSumBasePrice;\n\tZSTD_OptPrice_e priceType;\n\tconst ZSTD_entropyCTables_t *symbolCosts;\n\tZSTD_ParamSwitch_e literalCompressionMode;\n} optState_t;\n\ntypedef struct {\n\tunsigned int windowLog;\n\tunsigned int chainLog;\n\tunsigned int hashLog;\n\tunsigned int searchLog;\n\tunsigned int minMatch;\n\tunsigned int targetLength;\n\tZSTD_strategy strategy;\n} ZSTD_compressionParameters;\n\nstruct ZSTD_MatchState_t;\n\ntypedef struct ZSTD_MatchState_t ZSTD_MatchState_t;\n\nstruct ZSTD_MatchState_t {\n\tZSTD_window_t window;\n\tU32 loadedDictEnd;\n\tU32 nextToUpdate;\n\tU32 hashLog3;\n\tU32 rowHashLog;\n\tBYTE *tagTable;\n\tU32 hashCache[8];\n\tU64 hashSalt;\n\tU32 hashSaltEntropy;\n\tU32 *hashTable;\n\tU32 *hashTable3;\n\tU32 *chainTable;\n\tint forceNonContiguous;\n\tint dedicatedDictSearch;\n\toptState_t opt;\n\tconst ZSTD_MatchState_t *dictMatchState;\n\tZSTD_compressionParameters cParams;\n\tconst RawSeqStore_t *ldmSeqStore;\n\tint prefetchCDictTables;\n\tint lazySkipping;\n};\n\ntypedef struct {\n\tZSTD_compressedBlockState_t *prevCBlock;\n\tZSTD_compressedBlockState_t *nextCBlock;\n\tZSTD_MatchState_t matchState;\n} ZSTD_blockState_t;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef struct {\n\tU32 f1c;\n\tU32 f1d;\n\tU32 f7b;\n\tU32 f7c;\n} ZSTD_cpuid_t;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tvoid *workspace;\n\tvoid *workspaceEnd;\n\tvoid *objectEnd;\n\tvoid *tableEnd;\n\tvoid *tableValidEnd;\n\tvoid *allocStart;\n\tvoid *initOnceStart;\n\tBYTE allocFailed;\n\tint workspaceOversizedDuration;\n\tZSTD_cwksp_alloc_phase_e phase;\n\tZSTD_cwksp_static_alloc_e isStatic;\n} ZSTD_cwksp;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tint contentSizeFlag;\n\tint checksumFlag;\n\tint noDictIDFlag;\n} ZSTD_frameParameters;\n\ntypedef struct {\n\tlong long unsigned int ingested;\n\tlong long unsigned int consumed;\n\tlong long unsigned int produced;\n\tlong long unsigned int flushed;\n\tunsigned int currentJobID;\n\tunsigned int nbActiveWorkers;\n} ZSTD_frameProgression;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\nstruct ZSTD_CDict_s;\n\ntypedef struct ZSTD_CDict_s ZSTD_CDict;\n\ntypedef struct {\n\tvoid *dictBuffer;\n\tconst void *dict;\n\tsize_t dictSize;\n\tZSTD_dictContentType_e dictContentType;\n\tZSTD_CDict *cdict;\n} ZSTD_localDict;\n\ntypedef struct {\n\tRawSeqStore_t seqStore;\n\tU32 startPosInBlock;\n\tU32 endPosInBlock;\n\tU32 offset;\n} ZSTD_optLdm_t;\n\ntypedef struct {\n\tZSTD_compressionParameters cParams;\n\tZSTD_frameParameters fParams;\n} ZSTD_parameters;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tU32 LLtype;\n\tU32 Offtype;\n\tU32 MLtype;\n\tsize_t size;\n\tsize_t lastCountSize;\n\tint longOffsets;\n} ZSTD_symbolEncodingTypeStats_t;\n\ntypedef struct {\n\tlong unsigned int fds_bits[16];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef atomic64_t atomic_long_t;\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\traw_spinlock_t *lock2;\n} class_double_raw_spinlock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\nstruct gpio_generic_chip;\n\ntypedef struct {\n\tstruct gpio_generic_chip *lock;\n\tlong unsigned int flags;\n} class_gpio_generic_lock_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\nstruct snd_pcm_substream;\n\ntypedef struct {\n\tstruct snd_pcm_substream *lock;\n} class_pcm_stream_lock_irq_t;\n\ntypedef struct {\n\tstruct snd_pcm_substream *lock;\n\tlong unsigned int flags;\n} class_pcm_stream_lock_irqsave_t;\n\nstruct perf_cpu_context;\n\nstruct perf_event_context;\n\ntypedef struct {\n\tstruct perf_cpu_context *cpuctx;\n\tstruct perf_event_context *ctx;\n} class_perf_ctx_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_notrace_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\nstruct srcu_ctr;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tstruct srcu_ctr *scp;\n} class_srcu_fast_notrace_t;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\nstruct uart_port;\n\ntypedef struct {\n\tstruct uart_port *lock;\n\tlong unsigned int flags;\n} class_uart_port_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_write_lock_irqsave_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef __kernel_fsid_t compat_fsid_t;\n\ntypedef struct {\n\tcompat_sigset_word sig[2];\n} compat_sigset_t;\n\ntypedef struct {\n\t__be16 disc_information_length;\n\t__u8 disc_status: 2;\n\t__u8 border_status: 2;\n\t__u8 erasable: 1;\n\t__u8 reserved1: 3;\n\t__u8 n_first_track;\n\t__u8 n_sessions_lsb;\n\t__u8 first_track_lsb;\n\t__u8 last_track_lsb;\n\t__u8 mrw_status: 2;\n\t__u8 dbit: 1;\n\t__u8 reserved2: 2;\n\t__u8 uru: 1;\n\t__u8 dbc_v: 1;\n\t__u8 did_v: 1;\n\t__u8 disc_type;\n\t__u8 n_sessions_msb;\n\t__u8 first_track_msb;\n\t__u8 last_track_msb;\n\t__u32 disc_id;\n\t__u32 lead_in;\n\t__u32 lead_out;\n\t__u8 disc_bar_code[8];\n\t__u8 reserved3;\n\t__u8 n_opc;\n} disc_information;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\nstruct dvd_lu_send_agid {\n\t__u8 type;\n\tunsigned int agid: 2;\n};\n\nstruct dvd_host_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_send_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key key;\n};\n\nstruct dvd_lu_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_lu_send_title_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key title_key;\n\tint lba;\n\tunsigned int cpm: 1;\n\tunsigned int cp_sec: 1;\n\tunsigned int cgms: 2;\n};\n\nstruct dvd_lu_send_asf {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tunsigned int asf: 1;\n};\n\nstruct dvd_host_send_rpcstate {\n\t__u8 type;\n\t__u8 pdrc;\n};\n\nstruct dvd_lu_send_rpcstate {\n\t__u8 type: 2;\n\t__u8 vra: 3;\n\t__u8 ucca: 3;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_lu_send_agid lsa;\n\tstruct dvd_host_send_challenge hsc;\n\tstruct dvd_send_key lsk;\n\tstruct dvd_lu_send_challenge lsc;\n\tstruct dvd_send_key hsk;\n\tstruct dvd_lu_send_title_key lstk;\n\tstruct dvd_lu_send_asf lsasf;\n\tstruct dvd_host_send_rpcstate hrpcs;\n\tstruct dvd_lu_send_rpcstate lrpcs;\n} dvd_authinfo;\n\nstruct dvd_layer {\n\t__u8 book_version: 4;\n\t__u8 book_type: 4;\n\t__u8 min_rate: 4;\n\t__u8 disc_size: 4;\n\t__u8 layer_type: 4;\n\t__u8 track_path: 1;\n\t__u8 nlayers: 2;\n\tchar: 1;\n\t__u8 track_density: 4;\n\t__u8 linear_density: 4;\n\t__u8 bca: 1;\n\t__u32 start_sector;\n\t__u32 end_sector;\n\t__u32 end_sector_l0;\n};\n\nstruct dvd_physical {\n\t__u8 type;\n\t__u8 layer_num;\n\tstruct dvd_layer layer[4];\n};\n\nstruct dvd_copyright {\n\t__u8 type;\n\t__u8 layer_num;\n\t__u8 cpst;\n\t__u8 rmi;\n};\n\nstruct dvd_disckey {\n\t__u8 type;\n\tunsigned int agid: 2;\n\t__u8 value[2048];\n};\n\nstruct dvd_bca {\n\t__u8 type;\n\tint len;\n\t__u8 value[188];\n};\n\nstruct dvd_manufact {\n\t__u8 type;\n\t__u8 layer_num;\n\tint len;\n\t__u8 value[2048];\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_physical physical;\n\tstruct dvd_copyright copyright;\n\tstruct dvd_disckey disckey;\n\tstruct dvd_bca bca;\n\tstruct dvd_manufact manufact;\n} dvd_struct;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 headersize;\n\tu32 flags;\n\tu32 imagesize;\n} efi_capsule_header_t;\n\ntypedef struct {\n\tu8 major;\n\tu8 minor;\n} efi_cc_version_t;\n\ntypedef struct {\n\tu8 type;\n\tu8 sub_type;\n} efi_cc_type_t;\n\ntypedef struct {\n\tu8 size;\n\tefi_cc_version_t structure_version;\n\tefi_cc_version_t protocol_version;\n\tefi_cc_event_algorithm_bitmap_t hash_algorithm_bitmap;\n\tefi_cc_event_log_bitmap_t supported_event_logs;\n\tefi_cc_type_t cc_type;\n} efi_cc_boot_service_cap_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 table;\n} efi_config_table_32_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu64 table;\n} efi_config_table_64_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_guid_t guid;\n\t\tvoid *table;\n\t};\n\tefi_config_table_32_t mixed_mode;\n} efi_config_table_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tlong unsigned int *ptr;\n\tconst char name[16];\n} efi_config_table_type_t;\n\ntypedef struct {\n\tu16 year;\n\tu8 month;\n\tu8 day;\n\tu8 hour;\n\tu8 minute;\n\tu8 second;\n\tu8 pad1;\n\tu32 nanosecond;\n\ts16 timezone;\n\tu8 daylight;\n\tu8 pad2;\n} efi_time_t;\n\ntypedef struct {\n\tu64 size;\n\tu64 file_size;\n\tu64 phys_size;\n\tefi_time_t create_time;\n\tefi_time_t last_access_time;\n\tefi_time_t modification_time;\n\t__u64 attribute;\n\tefi_char16_t filename[0];\n} efi_file_info_t;\n\ntypedef struct {\n\tu32 red_mask;\n\tu32 green_mask;\n\tu32 blue_mask;\n\tu32 reserved_mask;\n} efi_pixel_bitmask_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 horizontal_resolution;\n\tu32 vertical_resolution;\n\tint pixel_format;\n\tefi_pixel_bitmask_t pixel_information;\n\tu32 pixels_per_scan_line;\n} efi_graphics_output_mode_info_t;\n\ntypedef struct {\n\tu16 scan_code;\n\tefi_char16_t unicode_char;\n} efi_input_key_t;\n\ntypedef struct {\n\tu32 attributes;\n\tu16 file_path_list_length;\n\tu8 variable_data[0];\n} __attribute__((packed)) efi_load_option_t;\n\nstruct efi_generic_dev_path;\n\ntypedef struct efi_generic_dev_path efi_device_path_protocol_t;\n\ntypedef struct {\n\tu32 attributes;\n\tu16 file_path_list_length;\n\tconst efi_char16_t *description;\n\tconst efi_device_path_protocol_t *file_path_list;\n\tu32 optional_data_size;\n\tconst void *optional_data;\n} efi_load_option_unpacked_t;\n\ntypedef void *efi_handle_t;\n\ntypedef struct {\n\tu64 signature;\n\tu32 revision;\n\tu32 headersize;\n\tu32 crc32;\n\tu32 reserved;\n} efi_table_hdr_t;\n\ntypedef struct {\n\tu32 resolution;\n\tu32 accuracy;\n\tu8 sets_to_zero;\n} efi_time_cap_t;\n\ntypedef efi_status_t efi_get_time_t(efi_time_t *, efi_time_cap_t *);\n\ntypedef efi_status_t efi_set_time_t(efi_time_t *);\n\ntypedef efi_status_t efi_get_wakeup_time_t(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\ntypedef efi_status_t efi_set_wakeup_time_t(efi_bool_t, efi_time_t *);\n\ntypedef struct {\n\tu32 type;\n\tu32 pad;\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu64 num_pages;\n\tu64 attribute;\n} efi_memory_desc_t;\n\ntypedef efi_status_t efi_set_virtual_address_map_t(long unsigned int, long unsigned int, u32, efi_memory_desc_t *);\n\ntypedef efi_status_t efi_get_variable_t(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\ntypedef efi_status_t efi_get_next_variable_t(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\ntypedef efi_status_t efi_set_variable_t(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\ntypedef efi_status_t efi_get_next_high_mono_count_t(u32 *);\n\ntypedef void efi_reset_system_t(int, efi_status_t, long unsigned int, efi_char16_t *);\n\ntypedef efi_status_t efi_update_capsule_t(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\ntypedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\ntypedef efi_status_t efi_query_variable_info_t(u32, u64 *, u64 *, u64 *);\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 get_time;\n\tu32 set_time;\n\tu32 get_wakeup_time;\n\tu32 set_wakeup_time;\n\tu32 set_virtual_address_map;\n\tu32 convert_pointer;\n\tu32 get_variable;\n\tu32 get_next_variable;\n\tu32 set_variable;\n\tu32 get_next_high_mono_count;\n\tu32 reset_system;\n\tu32 update_capsule;\n\tu32 query_capsule_caps;\n\tu32 query_variable_info;\n} efi_runtime_services_32_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tefi_get_time_t *get_time;\n\t\tefi_set_time_t *set_time;\n\t\tefi_get_wakeup_time_t *get_wakeup_time;\n\t\tefi_set_wakeup_time_t *set_wakeup_time;\n\t\tefi_set_virtual_address_map_t *set_virtual_address_map;\n\t\tvoid *convert_pointer;\n\t\tefi_get_variable_t *get_variable;\n\t\tefi_get_next_variable_t *get_next_variable;\n\t\tefi_set_variable_t *set_variable;\n\t\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\t\tefi_reset_system_t *reset_system;\n\t\tefi_update_capsule_t *update_capsule;\n\t\tefi_query_capsule_caps_t *query_capsule_caps;\n\t\tefi_query_variable_info_t *query_variable_info;\n\t};\n\tefi_runtime_services_32_t mixed_mode;\n} efi_runtime_services_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 fw_vendor;\n\tu32 fw_revision;\n\tu32 con_in_handle;\n\tu32 con_in;\n\tu32 con_out_handle;\n\tu32 con_out;\n\tu32 stderr_handle;\n\tu32 stderr;\n\tu32 runtime;\n\tu32 boottime;\n\tu32 nr_tables;\n\tu32 tables;\n} efi_system_table_32_t;\n\nunion efi_simple_text_input_protocol;\n\ntypedef union efi_simple_text_input_protocol efi_simple_text_input_protocol_t;\n\nunion efi_simple_text_output_protocol;\n\ntypedef union efi_simple_text_output_protocol efi_simple_text_output_protocol_t;\n\nunion efi_boot_services;\n\ntypedef union efi_boot_services efi_boot_services_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tlong unsigned int fw_vendor;\n\t\tu32 fw_revision;\n\t\tlong unsigned int con_in_handle;\n\t\tefi_simple_text_input_protocol_t *con_in;\n\t\tlong unsigned int con_out_handle;\n\t\tefi_simple_text_output_protocol_t *con_out;\n\t\tlong unsigned int stderr_handle;\n\t\tlong unsigned int stderr;\n\t\tefi_runtime_services_t *runtime;\n\t\tefi_boot_services_t *boottime;\n\t\tlong unsigned int nr_tables;\n\t\tlong unsigned int tables;\n\t};\n\tefi_system_table_32_t mixed_mode;\n} efi_system_table_t;\n\ntypedef union {\n\tstruct {\n\t\tu32 revision;\n\t\tefi_handle_t parent_handle;\n\t\tefi_system_table_t *system_table;\n\t\tefi_handle_t device_handle;\n\t\tvoid *file_path;\n\t\tvoid *reserved;\n\t\tu32 load_options_size;\n\t\tvoid *load_options;\n\t\tvoid *image_base;\n\t\t__u64 image_size;\n\t\tunsigned int image_code_type;\n\t\tunsigned int image_data_type;\n\t\tefi_status_t (*unload)(efi_handle_t);\n\t};\n\tstruct {\n\t\tu32 revision;\n\t\tu32 parent_handle;\n\t\tu32 system_table;\n\t\tu32 device_handle;\n\t\tu32 file_path;\n\t\tu32 reserved;\n\t\tu32 load_options_size;\n\t\tu32 load_options;\n\t\tu32 image_base;\n\t\t__u64 image_size;\n\t\tu32 image_code_type;\n\t\tu32 image_data_type;\n\t\tu32 unload;\n\t} mixed_mode;\n} efi_loaded_image_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 num_entries;\n\tu32 desc_size;\n\tu32 flags;\n\tefi_memory_desc_t entry[0];\n} efi_memory_attributes_table_t;\n\ntypedef struct {\n\tu32 read;\n\tu32 write;\n} efi_pci_io_protocol_access_32_t;\n\ntypedef struct {\n\tvoid *read;\n\tvoid *write;\n} efi_pci_io_protocol_access_t;\n\nunion efi_pci_io_protocol;\n\ntypedef union efi_pci_io_protocol efi_pci_io_protocol_t;\n\ntypedef efi_status_t (*efi_pci_io_protocol_cfg_t)(efi_pci_io_protocol_t *, EFI_PCI_IO_PROTOCOL_WIDTH, u32, long unsigned int, void *);\n\ntypedef struct {\n\tefi_pci_io_protocol_cfg_t read;\n\tefi_pci_io_protocol_cfg_t write;\n} efi_pci_io_protocol_config_access_t;\n\ntypedef struct {\n\tu16 version;\n\tu16 length;\n\tu32 runtime_services_supported;\n} efi_rt_properties_table_t;\n\ntypedef struct {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n} ext4_acl_entry;\n\ntypedef struct {\n\t__le32 a_version;\n} ext4_acl_header;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic64_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tunsigned int __softirq_pending;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n} irq_cpustat_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\tU32 offset;\n\tU32 checksum;\n} ldmEntry_t;\n\ntypedef struct {\n\tconst BYTE *split;\n\tU32 hash;\n\tU32 checksum;\n\tldmEntry_t *bucket;\n} ldmMatchCandidate_t;\n\ntypedef struct {\n\tZSTD_ParamSwitch_e enableLdm;\n\tU32 hashLog;\n\tU32 bucketSizeLog;\n\tU32 minMatchLength;\n\tU32 hashRateLog;\n\tU32 windowLog;\n} ldmParams_t;\n\ntypedef struct {\n\tU64 rolling;\n\tU64 stopMask;\n} ldmRollingHashState_t;\n\ntypedef struct {\n\tZSTD_window_t window;\n\tldmEntry_t *hashTable;\n\tU32 loadedDictEnd;\n\tBYTE *bucketOffsets;\n\tsize_t splitIndices[64];\n\tldmMatchCandidate_t matchCandidates[64];\n} ldmState_t;\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef struct {\n\tlocal_t a;\n} local64_t;\n\ntypedef union {\n\tlong unsigned int x[1];\n} map_word;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_t;\n\ntypedef struct {\n\tatomic_long_t id;\n\tvoid *vdso;\n\tcpumask_t icache_stale_mask;\n\tbool force_icache_flush;\n\tlong unsigned int flags;\n\tu8 pmlen;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[1];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tchar data[8];\n} nfs4_verifier;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\ntypedef struct {\n\tlong unsigned int p4d;\n} p4d_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\ntypedef struct {\n\tlong unsigned int pgd;\n} pgd_t;\n\ntypedef struct {\n\tlong unsigned int pgprot;\n} pgprot_t;\n\ntypedef struct {\n\tlong unsigned int pmd;\n} pmd_t;\n\ntypedef struct {\n\tlong unsigned int bits[4];\n} pnp_irq_mask_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tlong unsigned int pte;\n} pte_t;\n\ntypedef struct {\n\tlong unsigned int pud;\n} pud_t;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\t__u16 report_key_length;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 ucca: 3;\n\t__u8 vra: 3;\n\t__u8 type_code: 2;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n\t__u8 reserved3;\n} rpc_state_t;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tU32 *splitLocations;\n\tsize_t idx;\n} seqStoreSplits;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[1];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\nstruct qspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tstruct {\n\t\t\tu8 locked;\n\t\t\tu8 pending;\n\t\t};\n\t\tstruct {\n\t\t\tu16 locked_pending;\n\t\t\tu16 tail;\n\t\t};\n\t};\n};\n\ntypedef struct qspinlock arch_spinlock_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\t__be16 track_information_length;\n\t__u8 track_lsb;\n\t__u8 session_lsb;\n\t__u8 reserved1;\n\t__u8 track_mode: 4;\n\t__u8 copy: 1;\n\t__u8 damage: 1;\n\t__u8 reserved2: 2;\n\t__u8 data_mode: 4;\n\t__u8 fp: 1;\n\t__u8 packet: 1;\n\t__u8 blank: 1;\n\t__u8 rt: 1;\n\t__u8 nwa_v: 1;\n\t__u8 lra_v: 1;\n\t__u8 reserved3: 6;\n\t__be32 track_start;\n\t__be32 next_writable;\n\t__be32 free_blocks;\n\t__be32 fixed_packet_size;\n\t__be32 track_size;\n\t__be32 last_rec_address;\n} track_information;\n\ntypedef struct {\n\tint data;\n\tint audio;\n\tint cdi;\n\tint xa;\n\tlong int error;\n} tracktype;\n\ntypedef struct {\n\tlocal64_t v;\n} u64_stats_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_compressionParameters zstd_compression_parameters;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\ntypedef ZSTD_parameters zstd_parameters;\n\ntypedef ZSTD_Sequence zstd_sequence;\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lock_class_key {};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong int privdata[0];\n};\n\nstruct Qdisc_class_common {\n\tu32 classid;\n\tunsigned int filter_cnt;\n\tstruct hlist_node hnode;\n};\n\nstruct hlist_head;\n\nstruct Qdisc_class_hash {\n\tstruct hlist_head *hash;\n\tunsigned int hashsize;\n\tunsigned int hashmask;\n\tunsigned int hashelems;\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct RR_CL_s {\n\t__u8 location[8];\n};\n\nstruct RR_NM_s {\n\t__u8 flags;\n\tchar name[0];\n};\n\nstruct RR_PL_s {\n\t__u8 location[8];\n};\n\nstruct RR_PN_s {\n\t__u8 dev_high[8];\n\t__u8 dev_low[8];\n};\n\nstruct RR_PX_s {\n\t__u8 mode[8];\n\t__u8 n_links[8];\n\t__u8 uid[8];\n\t__u8 gid[8];\n};\n\nstruct RR_RR_s {\n\t__u8 flags[1];\n};\n\nstruct SL_component {\n\t__u8 flags;\n\t__u8 len;\n\t__u8 text[0];\n};\n\nstruct RR_SL_s {\n\t__u8 flags;\n\tstruct SL_component link;\n};\n\nstruct RR_TF_s {\n\t__u8 flags;\n\t__u8 data[0];\n};\n\nstruct RR_ZF_s {\n\t__u8 algorithm[2];\n\t__u8 parms[2];\n\t__u8 real_size[8];\n};\n\nstruct RxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\nstruct SU_CE_s {\n\t__u8 extent[8];\n\t__u8 offset[8];\n\t__u8 size[8];\n};\n\nstruct SU_ER_s {\n\t__u8 len_id;\n\t__u8 len_des;\n\t__u8 len_src;\n\t__u8 ext_ver;\n\t__u8 data[0];\n};\n\nstruct SU_SP_s {\n\t__u8 magic[2];\n\t__u8 skip;\n};\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct lockdep_map {};\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool work_in_progress;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tbool smart_suspend: 1;\n\tbool must_resume: 1;\n\tbool may_skip_resume: 1;\n\tbool out_band_wakeup: 1;\n\tbool strict_midlayer: 1;\n\tstruct hrtimer suspend_timer;\n\tu64 timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tbool idle_notification: 1;\n\tbool request_pending: 1;\n\tbool deferred_resume: 1;\n\tbool needs_force_resume: 1;\n\tbool runtime_auto: 1;\n\tbool ignore_children: 1;\n\tbool no_callbacks: 1;\n\tbool irq_safe: 1;\n\tbool use_autosuspend: 1;\n\tbool timer_autosuspends: 1;\n\tbool memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tenum rpm_status last_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct dev_archdata {};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct dev_pin_info;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct dma_coherent_mem;\n\nstruct io_tlb_mem;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct dev_pin_info *pins;\n\tstruct dev_msi_info msi;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct dma_coherent_mem *dma_mem;\n\tstruct io_tlb_mem *dma_io_tlb_mem;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tint numa_node;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_coherent: 1;\n\tbool dma_skip_sync: 1;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct SeqDef_s {\n\tU32 offBase;\n\tU16 litLength;\n\tU16 mlBase;\n};\n\nstruct TxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\ntypedef size_t (*ZSTD_sequenceProducer_F)(void *, ZSTD_Sequence *, size_t, const void *, size_t, const void *, size_t, int, size_t);\n\nstruct ZSTD_CCtx_params_s {\n\tZSTD_format_e format;\n\tZSTD_compressionParameters cParams;\n\tZSTD_frameParameters fParams;\n\tint compressionLevel;\n\tint forceWindow;\n\tsize_t targetCBlockSize;\n\tint srcSizeHint;\n\tZSTD_dictAttachPref_e attachDictPref;\n\tZSTD_ParamSwitch_e literalCompressionMode;\n\tint nbWorkers;\n\tsize_t jobSize;\n\tint overlapLog;\n\tint rsyncable;\n\tldmParams_t ldmParams;\n\tint enableDedicatedDictSearch;\n\tZSTD_bufferMode_e inBufferMode;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_SequenceFormat_e blockDelimiters;\n\tint validateSequences;\n\tZSTD_ParamSwitch_e postBlockSplitter;\n\tint preBlockSplitter_level;\n\tsize_t maxBlockSize;\n\tZSTD_ParamSwitch_e useRowMatchFinder;\n\tint deterministicRefPrefix;\n\tZSTD_customMem customMem;\n\tZSTD_ParamSwitch_e prefetchCDictTables;\n\tint enableMatchFinderFallback;\n\tvoid *extSeqProdState;\n\tZSTD_sequenceProducer_F extSeqProdFunc;\n\tZSTD_ParamSwitch_e searchForExternalRepcodes;\n};\n\ntypedef struct ZSTD_CCtx_params_s ZSTD_CCtx_params;\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n};\n\nstruct POOL_ctx_s;\n\ntypedef struct POOL_ctx_s ZSTD_threadPool;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\nstruct ZSTD_prefixDict_s {\n\tconst void *dict;\n\tsize_t dictSize;\n\tZSTD_dictContentType_e dictContentType;\n};\n\ntypedef struct ZSTD_prefixDict_s ZSTD_prefixDict;\n\nstruct ZSTD_CCtx_s {\n\tZSTD_compressionStage_e stage;\n\tint cParamsChanged;\n\tint bmi2;\n\tZSTD_CCtx_params requestedParams;\n\tZSTD_CCtx_params appliedParams;\n\tZSTD_CCtx_params simpleApiParams;\n\tU32 dictID;\n\tsize_t dictContentSize;\n\tZSTD_cwksp workspace;\n\tsize_t blockSizeMax;\n\tlong long unsigned int pledgedSrcSizePlusOne;\n\tlong long unsigned int consumedSrcSize;\n\tlong long unsigned int producedCSize;\n\tstruct xxh64_state xxhState;\n\tZSTD_customMem customMem;\n\tZSTD_threadPool *pool;\n\tsize_t staticSize;\n\tSeqCollector seqCollector;\n\tint isFirstBlock;\n\tint initialized;\n\tSeqStore_t seqStore;\n\tldmState_t ldmState;\n\trawSeq *ldmSequences;\n\tsize_t maxNbLdmSequences;\n\tRawSeqStore_t externSeqStore;\n\tZSTD_blockState_t blockState;\n\tvoid *tmpWorkspace;\n\tsize_t tmpWkspSize;\n\tZSTD_buffered_policy_e bufferedPolicy;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inToCompress;\n\tsize_t inBuffPos;\n\tsize_t inBuffTarget;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outBuffContentSize;\n\tsize_t outBuffFlushedSize;\n\tZSTD_cStreamStage streamStage;\n\tU32 frameEnded;\n\tZSTD_inBuffer expectedInBuffer;\n\tsize_t stableIn_notConsumed;\n\tsize_t expectedOutBufferSize;\n\tZSTD_localDict localDict;\n\tconst ZSTD_CDict *cdict;\n\tZSTD_prefixDict prefixDict;\n\tZSTD_blockSplitCtx blockSplitCtx;\n\tZSTD_Sequence *extSeqBuf;\n\tsize_t extSeqBufCapacity;\n};\n\ntypedef struct ZSTD_CCtx_s ZSTD_CCtx;\n\ntypedef ZSTD_CCtx ZSTD_CStream;\n\ntypedef ZSTD_CCtx zstd_cctx;\n\ntypedef ZSTD_CStream zstd_cstream;\n\nstruct ZSTD_CDict_s {\n\tconst void *dictContent;\n\tsize_t dictContentSize;\n\tZSTD_dictContentType_e dictContentType;\n\tU32 *entropyWorkspace;\n\tZSTD_cwksp workspace;\n\tZSTD_MatchState_t matchState;\n\tZSTD_compressedBlockState_t cBlockState;\n\tZSTD_customMem customMem;\n\tU32 dictID;\n\tint compressionLevel;\n\tZSTD_ParamSwitch_e useRowMatchFinder;\n};\n\ntypedef ZSTD_CDict zstd_cdict;\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct pt_regs {\n\tlong unsigned int epc;\n\tlong unsigned int ra;\n\tlong unsigned int sp;\n\tlong unsigned int gp;\n\tlong unsigned int tp;\n\tlong unsigned int t0;\n\tlong unsigned int t1;\n\tlong unsigned int t2;\n\tlong unsigned int s0;\n\tlong unsigned int s1;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int a0;\n\t\t\tlong unsigned int a1;\n\t\t\tlong unsigned int a2;\n\t\t\tlong unsigned int a3;\n\t\t\tlong unsigned int a4;\n\t\t\tlong unsigned int a5;\n\t\t\tlong unsigned int a6;\n\t\t\tlong unsigned int a7;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int a0;\n\t\t\tlong unsigned int a1;\n\t\t\tlong unsigned int a2;\n\t\t\tlong unsigned int a3;\n\t\t\tlong unsigned int a4;\n\t\t\tlong unsigned int a5;\n\t\t\tlong unsigned int a6;\n\t\t\tlong unsigned int a7;\n\t\t} a_regs;\n\t};\n\tlong unsigned int s2;\n\tlong unsigned int s3;\n\tlong unsigned int s4;\n\tlong unsigned int s5;\n\tlong unsigned int s6;\n\tlong unsigned int s7;\n\tlong unsigned int s8;\n\tlong unsigned int s9;\n\tlong unsigned int s10;\n\tlong unsigned int s11;\n\tlong unsigned int t3;\n\tlong unsigned int t4;\n\tlong unsigned int t5;\n\tlong unsigned int t6;\n\tlong unsigned int status;\n\tlong unsigned int badaddr;\n\tlong unsigned int cause;\n\tlong unsigned int orig_a0;\n};\n\nstruct __arch_ftrace_regs {\n\tstruct pt_regs regs;\n};\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n\tu16 src;\n\tu16 dst;\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct idr;\n\nstruct __class_idr {\n\tstruct idr *idr;\n\tint id;\n};\n\ntypedef struct __class_idr class_idr_alloc_t;\n\nstruct __cmp_key {\n\tconst struct cpumask *cpus;\n\tstruct cpumask ***masks;\n\tint node;\n\tint cpu;\n\tint w;\n};\n\nstruct __compat_aio_sigset {\n\tcompat_uptr_t sigmask;\n\tcompat_size_t sigsetsize;\n};\n\nstruct __extcon_info {\n\tunsigned int type;\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct __fat_dirent {\n\tlong int d_ino;\n\t__kernel_off_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[256];\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct pmu;\n\nstruct cgroup;\n\nstruct __group_key {\n\tint cpu;\n\tstruct pmu *pmu;\n\tstruct cgroup *cgroup;\n};\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __ip6_tnl_parm {\n\tchar name[16];\n\tint link;\n\t__u8 proto;\n\t__u8 encap_limit;\n\t__u8 hop_limit;\n\tbool collect_md;\n\t__be32 flowinfo;\n\t__u32 flags;\n\tstruct in6_addr laddr;\n\tstruct in6_addr raddr;\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\t__u32 fwmark;\n\t__u32 index;\n\t__u8 erspan_ver;\n\t__u8 dir;\n\t__u16 hwid;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct clk_core;\n\nstruct clk;\n\nstruct clk_init_data;\n\nstruct clk_hw {\n\tstruct clk_core *core;\n\tstruct clk *clk;\n\tconst struct clk_init_data *init;\n};\n\nstruct clk_ops;\n\nstruct __prci_wrpll_data;\n\nstruct __prci_data;\n\nstruct __prci_clock {\n\tconst char *name;\n\tconst char *parent_name;\n\tconst struct clk_ops *ops;\n\tstruct clk_hw hw;\n\tstruct __prci_wrpll_data *pwd;\n\tstruct __prci_data *pd;\n};\n\nstruct reset_control_ops;\n\nstruct of_phandle_args;\n\nstruct reset_controller_dev {\n\tconst struct reset_control_ops *ops;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct list_head reset_control_head;\n\tstruct device *dev;\n\tstruct device_node *of_node;\n\tconst struct of_phandle_args *of_args;\n\tint of_reset_n_cells;\n\tint (*of_xlate)(struct reset_controller_dev *, const struct of_phandle_args *);\n\tunsigned int nr_resets;\n};\n\nstruct reset_simple_data {\n\tspinlock_t lock;\n\tvoid *membase;\n\tstruct reset_controller_dev rcdev;\n\tbool active_low;\n\tbool status_active_low;\n\tunsigned int reset_us;\n};\n\nstruct clk_hw_onecell_data {\n\tunsigned int num;\n\tstruct clk_hw *hws[0];\n};\n\nstruct __prci_data {\n\tvoid *va;\n\tstruct reset_simple_data reset;\n\tstruct clk_hw_onecell_data hw_clks;\n};\n\nstruct wrpll_cfg {\n\tu8 divr;\n\tu8 divq;\n\tu8 range;\n\tu8 flags;\n\tu16 divf;\n\tu32 output_rate_cache[6];\n\tlong unsigned int parent_rate;\n\tu8 max_r;\n\tu8 init_r;\n};\n\nstruct __prci_wrpll_data {\n\tstruct wrpll_cfg c;\n\tvoid (*enable_bypass)(struct __prci_data *);\n\tvoid (*disable_bypass)(struct __prci_data *);\n\tu8 cfg0_offs;\n\tu8 cfg1_offs;\n};\n\nstruct __riscv_ctx_hdr {\n\t__u32 magic;\n\t__u32 size;\n};\n\nstruct __riscv_d_ext_state {\n\t__u64 f[32];\n\t__u32 fcsr;\n};\n\nstruct __riscv_extra_ext_header {\n\t__u32 __padding[129];\n\t__u32 reserved;\n\tstruct __riscv_ctx_hdr hdr;\n};\n\nstruct __riscv_f_ext_state {\n\t__u32 f[32];\n\t__u32 fcsr;\n};\n\nstruct __riscv_q_ext_state {\n\t__u64 f[64];\n\t__u32 fcsr;\n\t__u32 reserved[3];\n};\n\nunion __riscv_fp_state {\n\tstruct __riscv_f_ext_state f;\n\tstruct __riscv_d_ext_state d;\n\tstruct __riscv_q_ext_state q;\n};\n\nstruct __riscv_v_ext_state {\n\tlong unsigned int vstart;\n\tlong unsigned int vl;\n\tlong unsigned int vtype;\n\tlong unsigned int vcsr;\n\tlong unsigned int vlenb;\n\tvoid *datap;\n};\n\nstruct __riscv_v_regset_state {\n\tlong unsigned int vstart;\n\tlong unsigned int vl;\n\tlong unsigned int vtype;\n\tlong unsigned int vcsr;\n\tlong unsigned int vlenb;\n\tchar vreg[0];\n};\n\nstruct __sc_riscv_cfi_state {\n\tlong unsigned int ss_ptr;\n};\n\nstruct __sc_riscv_v_state {\n\tstruct __riscv_v_ext_state v_state;\n};\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[8];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[8];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct __snd_pcm_mmap_control64_buggy {\n\t__pad_before_u32 __pad1;\n\t__u32 appl_ptr;\n\t__pad_before_u32 __pad2;\n\t__pad_before_u32 __pad3;\n\t__u32 avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct __snd_timespec {\n\t__s32 tv_sec;\n\t__s32 tv_nsec;\n};\n\nstruct dentry;\n\nstruct __track_dentry_update_args {\n\tstruct dentry *dentry;\n\tint op;\n};\n\nstruct __track_range_args {\n\text4_lblk_t start;\n\text4_lblk_t end;\n};\n\nstruct inode;\n\nstruct __uprobe_key {\n\tstruct inode *inode;\n\tloff_t offset;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct vm_special_mapping;\n\nstruct __vdso_info {\n\tconst char *name;\n\tconst char *vdso_code_start;\n\tconst char *vdso_code_end;\n\tlong unsigned int vdso_pages;\n\tstruct vm_special_mapping *cm;\n};\n\nstruct net_device;\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nstruct _ccu_mult {\n\tlong unsigned int mult;\n\tlong unsigned int min;\n\tlong unsigned int max;\n};\n\nstruct _ccu_nk {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n};\n\nstruct _ccu_nkm {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n};\n\nstruct _ccu_nkmp {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n\tlong unsigned int p;\n\tlong unsigned int min_p;\n\tlong unsigned int max_p;\n};\n\nstruct _ccu_nm {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n} __attribute__((packed));\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct a4tech_sc {\n\tlong unsigned int quirks;\n\tunsigned int hw_wheel;\n\t__s32 delayed_value;\n};\n\nstruct aa_policydb;\n\nstruct aa_attachment {\n\tconst char *xmatch_str;\n\tstruct aa_policydb *xmatch;\n\tunsigned int xmatch_len;\n\tint xattr_count;\n\tchar **xattrs;\n};\n\nstruct aa_label;\n\nstruct aa_audit_rule {\n\tstruct aa_label *label;\n};\n\nunion aa_buffer {\n\tstruct list_head list;\n\tstruct {\n\t\tstruct {} __empty_buffer;\n\t\tchar buffer[0];\n\t};\n};\n\nstruct aa_caps {\n\tkernel_cap_t allow;\n\tkernel_cap_t audit;\n\tkernel_cap_t denied;\n\tkernel_cap_t quiet;\n\tkernel_cap_t kill;\n\tkernel_cap_t extended;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct aa_data {\n\tchar *key;\n\tu32 size;\n\tchar *data;\n\tstruct rhash_head head;\n};\n\nstruct table_header;\n\nstruct aa_dfa {\n\tstruct kref count;\n\tu16 flags;\n\tu32 max_oob;\n\tstruct table_header *tables[8];\n};\n\nstruct aa_ext {\n\tvoid *start;\n\tvoid *end;\n\tvoid *pos;\n\tu32 version;\n};\n\nstruct aa_file_ctx {\n\tspinlock_t lock;\n\tstruct aa_label *label;\n\tu32 allow;\n};\n\nstruct aa_proxy;\n\nstruct aa_profile;\n\nstruct aa_ruleset;\n\nstruct aa_label {\n\tstruct kref count;\n\tstruct rb_node node;\n\tstruct callback_head rcu;\n\tstruct aa_proxy *proxy;\n\tchar *hname;\n\tlong int flags;\n\tu32 secid;\n\tint size;\n\tu64 mediates;\n\tunion {\n\t\tstruct {\n\t\t\tstruct aa_profile *profile[2];\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty_rules;\n\t\t\t\tstruct aa_ruleset *rules[0];\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_vec;\n\t\t\tstruct aa_profile *vec[0];\n\t\t};\n\t};\n};\n\nstruct qrwlock {\n\tunion {\n\t\tatomic_t cnts;\n\t\tstruct {\n\t\t\tu8 wlocked;\n\t\t\tu8 __lstate[3];\n\t\t};\n\t};\n\tarch_spinlock_t wait_lock;\n};\n\ntypedef struct qrwlock arch_rwlock_t;\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct aa_labelset {\n\trwlock_t lock;\n\tstruct rb_root root;\n};\n\nstruct aa_load_ent {\n\tstruct list_head list;\n\tstruct aa_profile *new;\n\tstruct aa_profile *old;\n\tstruct aa_profile *rename;\n\tconst char *ns_name;\n};\n\nstruct aa_ns;\n\nstruct aa_loaddata {\n\tstruct kref count;\n\tstruct list_head list;\n\tstruct work_struct work;\n\tstruct dentry *dents[6];\n\tstruct aa_ns *ns;\n\tchar *name;\n\tsize_t size;\n\tsize_t compressed_size;\n\tlong int revision;\n\tint abi;\n\tunsigned char *hash;\n\tchar *data;\n};\n\nstruct aa_local_cache {\n\tunsigned int hold;\n\tunsigned int count;\n\tstruct list_head head;\n};\n\nstruct aa_policy {\n\tconst char *name;\n\tchar *hname;\n\tstruct list_head list;\n\tstruct list_head profiles;\n};\n\nstruct aa_ns_acct {\n\tint max_size;\n\tint max_count;\n\tint size;\n\tint count;\n};\n\nstruct aa_ns {\n\tstruct aa_policy base;\n\tstruct aa_ns *parent;\n\tstruct mutex lock;\n\tstruct aa_ns_acct acct;\n\tstruct aa_profile *unconfined;\n\tstruct list_head sub_ns;\n\tatomic_t uniq_null;\n\tlong int uniq_id;\n\tint level;\n\tlong int revision;\n\twait_queue_head_t wait;\n\tstruct aa_labelset labels;\n\tstruct list_head rawdata_list;\n\tstruct dentry *dents[13];\n};\n\nstruct aa_perms {\n\tu32 allow;\n\tu32 deny;\n\tu32 subtree;\n\tu32 cond;\n\tu32 kill;\n\tu32 complain;\n\tu32 prompt;\n\tu32 audit;\n\tu32 quiet;\n\tu32 hide;\n\tu32 xindex;\n\tu32 tag;\n\tu32 label;\n};\n\nstruct aa_str_table_ent;\n\nstruct aa_str_table {\n\tint size;\n\tstruct aa_str_table_ent *table;\n};\n\nstruct aa_tags_header;\n\nstruct aa_tags_struct {\n\tstruct {\n\t\tu32 size;\n\t\tu32 *table;\n\t} sets;\n\tstruct {\n\t\tu32 size;\n\t\tstruct aa_tags_header *table;\n\t} hdrs;\n\tstruct aa_str_table strs;\n};\n\nstruct aa_policydb {\n\tstruct kref count;\n\tstruct aa_dfa *dfa;\n\tstruct {\n\t\tstruct aa_perms *perms;\n\t\tu32 size;\n\t};\n\tstruct aa_str_table trans;\n\tstruct aa_tags_struct tags;\n\tunsigned int start[33];\n};\n\nstruct rhashtable;\n\nstruct aa_profile {\n\tstruct aa_policy base;\n\tstruct aa_profile *parent;\n\tstruct aa_ns *ns;\n\tconst char *rename;\n\tenum audit_mode audit;\n\tlong int mode;\n\tu32 path_flags;\n\tint signal;\n\tconst char *disconnected;\n\tstruct aa_attachment attach;\n\tstruct aa_loaddata *rawdata;\n\tunsigned char *hash;\n\tchar *dirname;\n\tstruct dentry *dents[9];\n\tstruct rhashtable *data;\n\tint n_rules;\n\tstruct aa_label label;\n};\n\nstruct aa_proxy {\n\tstruct kref count;\n\tstruct aa_label *label;\n};\n\nstruct aa_revision {\n\tstruct aa_ns *ns;\n\tlong int last_read;\n};\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct aa_rlimit {\n\tunsigned int mask;\n\tstruct rlimit limits[16];\n};\n\nstruct aa_secmark;\n\nstruct aa_ruleset {\n\tint size;\n\tstruct aa_policydb *policy;\n\tstruct aa_policydb *file;\n\tstruct aa_caps caps;\n\tstruct aa_rlimit rlimits;\n\tint secmark_count;\n\tstruct aa_secmark *secmark;\n};\n\nstruct aa_secmark {\n\tu8 audit;\n\tu8 deny;\n\tu32 secid;\n\tchar *label;\n};\n\nstruct file_operations;\n\nstruct aa_sfs_entry {\n\tconst char *name;\n\tstruct dentry *dentry;\n\tumode_t mode;\n\tenum aa_sfs_type v_type;\n\tunion {\n\t\tbool boolean;\n\t\tchar *string;\n\t\tlong unsigned int u64;\n\t\tstruct aa_sfs_entry *files;\n\t} v;\n\tconst struct file_operations *file_ops;\n};\n\nstruct aa_sk_ctx {\n\tstruct aa_label *label;\n\tstruct aa_label *peer;\n\tstruct aa_label *peer_lastupdate;\n};\n\nstruct aa_str_table_ent {\n\tint count;\n\tint size;\n\tchar *strs;\n};\n\nstruct aa_tags_header {\n\tu32 mask;\n\tu32 count;\n\tu32 size;\n\tu32 tags;\n};\n\nstruct aa_task_ctx {\n\tstruct aa_label *nnp;\n\tstruct aa_label *onexec;\n\tstruct aa_label *previous;\n\tu64 token;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct ac6_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct access_coordinate {\n\tunsigned int read_bandwidth;\n\tunsigned int write_bandwidth;\n\tunsigned int read_latency;\n\tunsigned int write_latency;\n};\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct power_supply;\n\nunion power_supply_propval;\n\nstruct power_supply_desc {\n\tconst char *name;\n\tenum power_supply_type type;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tu32 usb_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, enum power_supply_property);\n\tvoid (*external_power_changed)(struct power_supply *);\n\tbool no_thermal;\n\tint use_for_apm;\n};\n\nstruct notifier_block;\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct acpi_device;\n\nstruct acpi_ac {\n\tstruct power_supply *charger;\n\tstruct power_supply_desc charger_desc;\n\tstruct acpi_device *device;\n\tlong long unsigned int state;\n\tstruct notifier_block battery_nb;\n};\n\nstruct acpi_address16_attribute {\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n};\n\nstruct acpi_address32_attribute {\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n};\n\nstruct acpi_address64_attribute {\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n};\n\nstruct acpi_namespace_node;\n\nstruct acpi_address_range {\n\tstruct acpi_address_range *next;\n\tstruct acpi_namespace_node *region_node;\n\tacpi_physical_address start_address;\n\tacpi_physical_address end_address;\n};\n\nstruct acpi_battery {\n\tstruct mutex update_lock;\n\tstruct power_supply *bat;\n\tstruct power_supply_desc bat_desc;\n\tstruct acpi_device *device;\n\tstruct notifier_block pm_nb;\n\tstruct list_head list;\n\tlong unsigned int update_time;\n\tint revision;\n\tint rate_now;\n\tint capacity_now;\n\tint voltage_now;\n\tint design_capacity;\n\tint full_charge_capacity;\n\tint technology;\n\tint design_voltage;\n\tint design_capacity_warning;\n\tint design_capacity_low;\n\tint cycle_count;\n\tint measurement_accuracy;\n\tint max_sampling_time;\n\tint min_sampling_time;\n\tint max_averaging_interval;\n\tint min_averaging_interval;\n\tint capacity_granularity_1;\n\tint capacity_granularity_2;\n\tint alarm;\n\tchar model_number[64];\n\tchar serial_number[64];\n\tchar type[64];\n\tchar oem_info[64];\n\tint state;\n\tint power_unit;\n\tlong unsigned int flags;\n};\n\nstruct acpi_battery_hook {\n\tconst char *name;\n\tint (*add_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tint (*remove_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tstruct list_head list;\n};\n\nstruct acpi_buffer {\n\tacpi_size length;\n\tvoid *pointer;\n};\n\nstruct acpi_bus_event {\n\tstruct list_head node;\n\tacpi_device_class device_class;\n\tacpi_bus_id bus_id;\n\tu32 type;\n\tu32 data;\n};\n\nstruct acpi_bus_type {\n\tstruct list_head list;\n\tconst char *name;\n\tbool (*match)(struct device *);\n\tstruct acpi_device * (*find_companion)(struct device *);\n\tvoid (*setup)(struct device *);\n};\n\nstruct input_dev;\n\nstruct acpi_button {\n\tstruct acpi_device *adev;\n\tstruct device *dev;\n\tunsigned int type;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tlong unsigned int pushed;\n\tint last_state;\n\tktime_t last_time;\n\tbool suspended;\n\tbool lid_state_initialized;\n};\n\nstruct acpi_cdat_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_cfmws {\n\tstruct acpi_cedt_header header;\n\tu32 reserved1;\n\tu64 base_hpa;\n\tu64 window_size;\n\tu8 interleave_ways;\n\tu8 interleave_arithmetic;\n\tu16 reserved2;\n\tu32 granularity;\n\tu16 restrictions;\n\tu16 qtg_id;\n\tu32 interleave_targets[0];\n} __attribute__((packed));\n\nstruct acpi_comment_node {\n\tchar *comment;\n\tstruct acpi_comment_node *next;\n};\n\nstruct acpi_common_descriptor {\n\tvoid *common_pointer;\n\tu8 descriptor_type;\n};\n\nstruct acpi_common_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n};\n\nstruct acpi_connection_info {\n\tu8 *connection;\n\tu16 length;\n\tu8 access_length;\n};\n\nunion acpi_parse_object;\n\nstruct acpi_control_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu16 opcode;\n\tunion acpi_parse_object *predicate_op;\n\tu8 *aml_predicate_start;\n\tu8 *package_end;\n\tu64 loop_timeout;\n};\n\nstruct acpi_create_field_info {\n\tstruct acpi_namespace_node *region_node;\n\tstruct acpi_namespace_node *field_node;\n\tstruct acpi_namespace_node *register_node;\n\tstruct acpi_namespace_node *data_register_node;\n\tstruct acpi_namespace_node *connection_node;\n\tu8 *resource_buffer;\n\tu32 bank_value;\n\tu32 field_bit_position;\n\tu32 field_bit_length;\n\tu16 resource_length;\n\tu16 pin_number_index;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 field_type;\n\tu8 access_length;\n};\n\nstruct acpi_csrt_group {\n\tu32 length;\n\tu32 vendor_id;\n\tu32 subvendor_id;\n\tu16 device_id;\n\tu16 subdevice_id;\n\tu16 revision;\n\tu16 reserved;\n\tu32 shared_info_length;\n};\n\nstruct acpi_csrt_shared_info {\n\tu16 major_version;\n\tu16 minor_version;\n\tu32 mmio_base_low;\n\tu32 mmio_base_high;\n\tu32 gsi_interrupt;\n\tu8 interrupt_polarity;\n\tu8 interrupt_mode;\n\tu8 num_channels;\n\tu8 dma_address_width;\n\tu16 base_request_line;\n\tu16 num_handshake_signals;\n\tu32 max_block_size;\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct address_space;\n\nstruct file;\n\nstruct vm_area_struct;\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct acpi_data_attr {\n\tstruct bin_attribute attr;\n\tu64 addr;\n};\n\ntypedef void *acpi_handle;\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nunion acpi_object;\n\nstruct acpi_device_data {\n\tconst union acpi_object *pointer;\n\tstruct list_head properties;\n\tconst union acpi_object *of_compatible;\n\tstruct list_head subnodes;\n};\n\nstruct acpi_data_node {\n\tstruct list_head sibling;\n\tconst char *name;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tstruct acpi_device_data data;\n\tstruct kobject kobj;\n\tstruct completion kobj_done;\n};\n\nstruct acpi_data_node_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct acpi_data_node *, char *);\n\tssize_t (*store)(struct acpi_data_node *, const char *, size_t);\n};\n\nstruct acpi_data_obj {\n\tchar *name;\n\tint (*fn)(void *, struct acpi_data_attr *);\n};\n\nstruct acpi_data_table_mapping {\n\tvoid *pointer;\n};\n\nstruct acpi_dep_data {\n\tstruct list_head node;\n\tacpi_handle supplier;\n\tacpi_handle consumer;\n\tbool honor_dep;\n\tbool met;\n\tbool free_when_met;\n};\n\nunion acpi_operand_object;\n\nstruct acpi_object_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n};\n\nstruct acpi_object_integer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 fill[3];\n\tu64 value;\n};\n\nstruct acpi_object_string {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tchar *pointer;\n\tu32 length;\n};\n\nstruct acpi_object_buffer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 *pointer;\n\tu32 length;\n\tu32 aml_length;\n\tu8 *aml_start;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_object_package {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **elements;\n\tu8 *aml_start;\n\tu32 aml_length;\n\tu32 count;\n};\n\nstruct acpi_object_event {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tvoid *os_semaphore;\n};\n\nstruct acpi_walk_state;\n\ntypedef acpi_status (*acpi_internal_method)(struct acpi_walk_state *);\n\nstruct acpi_object_method {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 info_flags;\n\tu8 param_count;\n\tu8 sync_level;\n\tunion acpi_operand_object *mutex;\n\tunion acpi_operand_object *node;\n\tu8 *aml_start;\n\tunion {\n\t\tacpi_internal_method implementation;\n\t\tunion acpi_operand_object *handler;\n\t} dispatch;\n\tu32 aml_length;\n\tacpi_owner_id owner_id;\n\tu8 thread_count;\n};\n\nstruct acpi_thread_state;\n\nstruct acpi_object_mutex {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 sync_level;\n\tu16 acquisition_depth;\n\tvoid *os_mutex;\n\tu64 thread_id;\n\tstruct acpi_thread_state *owner_thread;\n\tunion acpi_operand_object *prev;\n\tunion acpi_operand_object *next;\n\tstruct acpi_namespace_node *node;\n\tu8 original_sync_level;\n};\n\nstruct acpi_object_region {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler;\n\tunion acpi_operand_object *next;\n\tacpi_physical_address address;\n\tu32 length;\n\tvoid *pointer;\n};\n\nstruct acpi_object_notify_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_gpe_block_info;\n\nstruct acpi_object_device {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tstruct acpi_gpe_block_info *gpe_block;\n};\n\nstruct acpi_object_power_resource {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tu32 system_level;\n\tu32 resource_order;\n};\n\nstruct acpi_object_processor {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 proc_id;\n\tu8 length;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tacpi_io_address address;\n};\n\nstruct acpi_object_thermal_zone {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_object_field_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n};\n\nstruct acpi_object_region_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu16 resource_length;\n\tunion acpi_operand_object *region_obj;\n\tu8 *resource_buffer;\n\tu16 pin_number_index;\n\tu8 *internal_pcc_buffer;\n};\n\nstruct acpi_object_buffer_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu8 is_create_field;\n\tunion acpi_operand_object *buffer_obj;\n};\n\nstruct acpi_object_bank_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n\tunion acpi_operand_object *bank_obj;\n};\n\nstruct acpi_object_index_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *index_obj;\n\tunion acpi_operand_object *data_obj;\n};\n\ntypedef void (*acpi_notify_handler)(acpi_handle, u32, void *);\n\nstruct acpi_object_notify_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tu32 handler_type;\n\tacpi_notify_handler handler;\n\tvoid *context;\n\tunion acpi_operand_object *next[2];\n};\n\ntypedef acpi_status (*acpi_adr_space_handler)(u32, acpi_physical_address, u32, u64 *, void *, void *);\n\ntypedef acpi_status (*acpi_adr_space_setup)(acpi_handle, u32, void *, void **);\n\nstruct acpi_object_addr_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tu8 handler_flags;\n\tacpi_adr_space_handler handler;\n\tstruct acpi_namespace_node *node;\n\tvoid *context;\n\tvoid *context_mutex;\n\tacpi_adr_space_setup setup;\n\tunion acpi_operand_object *region_list;\n\tunion acpi_operand_object *next;\n};\n\nstruct acpi_object_reference {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 class;\n\tu8 target_type;\n\tu8 resolved;\n\tvoid *object;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **where;\n\tu8 *index_pointer;\n\tu8 *aml;\n\tu32 value;\n};\n\nstruct acpi_object_extra {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *method_REG;\n\tstruct acpi_namespace_node *scope_node;\n\tvoid *region_context;\n\tu8 *aml_start;\n\tu32 aml_length;\n};\n\ntypedef void (*acpi_object_handler)(acpi_handle, void *);\n\nstruct acpi_object_data {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tacpi_object_handler handler;\n\tvoid *pointer;\n};\n\nstruct acpi_object_cache_list {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *next;\n};\n\nunion acpi_name_union {\n\tu32 integer;\n\tchar ascii[4];\n};\n\nstruct acpi_namespace_node {\n\tunion acpi_operand_object *object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 flags;\n\tunion acpi_name_union name;\n\tstruct acpi_namespace_node *parent;\n\tstruct acpi_namespace_node *child;\n\tstruct acpi_namespace_node *peer;\n\tacpi_owner_id owner_id;\n};\n\nunion acpi_operand_object {\n\tstruct acpi_object_common common;\n\tstruct acpi_object_integer integer;\n\tstruct acpi_object_string string;\n\tstruct acpi_object_buffer buffer;\n\tstruct acpi_object_package package;\n\tstruct acpi_object_event event;\n\tstruct acpi_object_method method;\n\tstruct acpi_object_mutex mutex;\n\tstruct acpi_object_region region;\n\tstruct acpi_object_notify_common common_notify;\n\tstruct acpi_object_device device;\n\tstruct acpi_object_power_resource power_resource;\n\tstruct acpi_object_processor processor;\n\tstruct acpi_object_thermal_zone thermal_zone;\n\tstruct acpi_object_field_common common_field;\n\tstruct acpi_object_region_field field;\n\tstruct acpi_object_buffer_field buffer_field;\n\tstruct acpi_object_bank_field bank_field;\n\tstruct acpi_object_index_field index_field;\n\tstruct acpi_object_notify_handler notify;\n\tstruct acpi_object_addr_handler address_space;\n\tstruct acpi_object_reference reference;\n\tstruct acpi_object_extra extra;\n\tstruct acpi_object_data data;\n\tstruct acpi_object_cache_list cache;\n\tstruct acpi_namespace_node node;\n};\n\nunion acpi_parse_value {\n\tu64 integer;\n\tu32 size;\n\tchar *string;\n\tu8 *buffer;\n\tchar *name;\n\tunion acpi_parse_object *arg;\n};\n\nstruct acpi_parse_obj_common {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n};\n\nstruct acpi_parse_obj_named {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tchar *path;\n\tu8 *data;\n\tu32 length;\n\tu32 name;\n};\n\nstruct acpi_parse_obj_asl {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tunion acpi_parse_object *child;\n\tunion acpi_parse_object *parent_method;\n\tchar *filename;\n\tu8 file_changed;\n\tchar *parent_filename;\n\tchar *external_name;\n\tchar *namepath;\n\tchar name_seg[4];\n\tu32 extra_value;\n\tu32 column;\n\tu32 line_number;\n\tu32 logical_line_number;\n\tu32 logical_byte_offset;\n\tu32 end_line;\n\tu32 end_logical_line;\n\tu32 acpi_btype;\n\tu32 aml_length;\n\tu32 aml_subtree_length;\n\tu32 final_aml_length;\n\tu32 final_aml_offset;\n\tu32 compile_flags;\n\tu16 parse_opcode;\n\tu8 aml_opcode_length;\n\tu8 aml_pkg_len_bytes;\n\tu8 extra;\n\tchar parse_op_name[20];\n};\n\nunion acpi_parse_object {\n\tstruct acpi_parse_obj_common common;\n\tstruct acpi_parse_obj_named named;\n\tstruct acpi_parse_obj_asl asl;\n};\n\nunion acpi_descriptor {\n\tstruct acpi_common_descriptor common;\n\tunion acpi_operand_object object;\n\tstruct acpi_namespace_node node;\n\tunion acpi_parse_object op;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct acpi_dev_match_info {\n\tstruct acpi_device_id hid[2];\n\tconst char *uid;\n\ts64 hrv;\n};\n\nstruct acpi_dev_walk_context {\n\tint (*fn)(struct acpi_device *, void *);\n\tvoid *data;\n};\n\nstruct acpi_device_status {\n\tu32 present: 1;\n\tu32 enabled: 1;\n\tu32 show_in_ui: 1;\n\tu32 functional: 1;\n\tu32 battery_present: 1;\n\tu32 reserved: 27;\n};\n\nstruct acpi_device_flags {\n\tu32 dynamic_status: 1;\n\tu32 removable: 1;\n\tu32 ejectable: 1;\n\tu32 power_manageable: 1;\n\tu32 match_driver: 1;\n\tu32 initialized: 1;\n\tu32 visited: 1;\n\tu32 hotplug_notify: 1;\n\tu32 is_dock_station: 1;\n\tu32 of_compatible_ok: 1;\n\tu32 coherent_dma: 1;\n\tu32 cca_seen: 1;\n\tu32 enumeration_by_parent: 1;\n\tu32 honor_deps: 1;\n\tu32 reserved: 18;\n};\n\nstruct acpi_pnp_type {\n\tu32 hardware_id: 1;\n\tu32 bus_address: 1;\n\tu32 platform_id: 1;\n\tu32 backlight: 1;\n\tu32 reserved: 28;\n};\n\nstruct acpi_device_pnp {\n\tacpi_bus_id bus_id;\n\tint instance_no;\n\tstruct acpi_pnp_type type;\n\tacpi_bus_address bus_address;\n\tchar *unique_id;\n\tstruct list_head ids;\n\tacpi_device_name device_name;\n\tacpi_device_class device_class;\n};\n\nstruct acpi_device_power_flags {\n\tu32 explicit_get: 1;\n\tu32 power_resources: 1;\n\tu32 inrush_current: 1;\n\tu32 power_removed: 1;\n\tu32 ignore_parent: 1;\n\tu32 dsw_present: 1;\n\tu32 reserved: 26;\n};\n\nstruct acpi_device_power_state {\n\tstruct list_head resources;\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 explicit_set: 1;\n\t\tu8 reserved: 6;\n\t} flags;\n\tint power;\n\tint latency;\n};\n\nstruct acpi_device_power {\n\tint state;\n\tstruct acpi_device_power_flags flags;\n\tstruct acpi_device_power_state states[5];\n\tu8 state_for_enumeration;\n};\n\nstruct acpi_device_wakeup_flags {\n\tu8 valid: 1;\n\tu8 notifier_present: 1;\n};\n\nstruct acpi_device_wakeup_context {\n\tvoid (*func)(struct acpi_device_wakeup_context *);\n\tstruct device *dev;\n};\n\nstruct acpi_device_wakeup {\n\tacpi_handle gpe_device;\n\tu64 gpe_number;\n\tu64 sleep_state;\n\tstruct list_head resources;\n\tstruct acpi_device_wakeup_flags flags;\n\tstruct acpi_device_wakeup_context context;\n\tstruct wakeup_source *ws;\n\tint prepare_count;\n\tint enable_count;\n};\n\nstruct acpi_device_perf_flags {\n\tu8 reserved: 8;\n};\n\nstruct acpi_device_perf_state;\n\nstruct acpi_device_perf {\n\tint state;\n\tstruct acpi_device_perf_flags flags;\n\tint state_count;\n\tstruct acpi_device_perf_state *states;\n};\n\nstruct proc_dir_entry;\n\nstruct acpi_device_dir {\n\tstruct proc_dir_entry *entry;\n};\n\nstruct acpi_scan_handler;\n\nstruct acpi_hotplug_context;\n\nstruct acpi_device_software_nodes;\n\nstruct acpi_gpio_mapping;\n\nstruct acpi_device {\n\tu32 pld_crc;\n\tint device_type;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct list_head wakeup_list;\n\tstruct list_head del_list;\n\tstruct acpi_device_status status;\n\tstruct acpi_device_flags flags;\n\tstruct acpi_device_pnp pnp;\n\tstruct acpi_device_power power;\n\tstruct acpi_device_wakeup wakeup;\n\tstruct acpi_device_perf performance;\n\tstruct acpi_device_dir dir;\n\tstruct acpi_device_data data;\n\tstruct acpi_scan_handler *handler;\n\tstruct acpi_hotplug_context *hp;\n\tstruct acpi_device_software_nodes *swnodes;\n\tconst struct acpi_gpio_mapping *driver_gpios;\n\tvoid *driver_data;\n\tstruct device dev;\n\tunsigned int physical_node_count;\n\tunsigned int dep_unmet;\n\tstruct list_head physical_node_list;\n\tstruct mutex physical_node_lock;\n\tvoid (*remove)(struct acpi_device *);\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct acpi_device_bus_id {\n\tconst char *bus_id;\n\tstruct ida instance_ida;\n\tstruct list_head node;\n};\n\nstruct acpi_pnp_device_id {\n\tu32 length;\n\tchar *string;\n};\n\nstruct acpi_pnp_device_id_list {\n\tu32 count;\n\tu32 list_size;\n\tstruct acpi_pnp_device_id ids[0];\n};\n\nstruct acpi_device_info {\n\tu32 info_size;\n\tu32 name;\n\tacpi_object_type type;\n\tu8 param_count;\n\tu16 valid;\n\tu8 flags;\n\tu8 highest_dstates[4];\n\tu8 lowest_dstates[5];\n\tu64 address;\n\tstruct acpi_pnp_device_id hardware_id;\n\tstruct acpi_pnp_device_id unique_id;\n\tstruct acpi_pnp_device_id class_code;\n\tstruct acpi_pnp_device_id_list compatible_id_list;\n};\n\ntypedef int (*acpi_op_add)(struct acpi_device *);\n\ntypedef void (*acpi_op_remove)(struct acpi_device *);\n\ntypedef void (*acpi_op_notify)(struct acpi_device *, u32);\n\nstruct acpi_device_ops {\n\tacpi_op_add add;\n\tacpi_op_remove remove;\n\tacpi_op_notify notify;\n};\n\nstruct acpi_device_perf_state {\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 reserved: 7;\n\t} flags;\n\tu8 power;\n\tu8 performance;\n\tint latency;\n};\n\nstruct acpi_device_physical_node {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int node_id;\n\tbool put_online: 1;\n};\n\nstruct acpi_device_properties {\n\tstruct list_head list;\n\tconst guid_t *guid;\n\tunion acpi_object *properties;\n\tvoid **bufs;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[1];\n\t\t} value;\n\t};\n};\n\nstruct software_node;\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct acpi_device_software_node_port {\n\tchar port_name[9];\n\tu32 data_lanes[8];\n\tu32 lane_polarities[9];\n\tu64 link_frequencies[8];\n\tunsigned int port_nr;\n\tbool crs_csi2_local;\n\tstruct property_entry port_props[2];\n\tstruct property_entry ep_props[8];\n\tstruct software_node_ref_args remote_ep[1];\n};\n\nstruct acpi_device_software_nodes {\n\tstruct property_entry dev_props[6];\n\tstruct software_node *nodes;\n\tconst struct software_node **nodeptrs;\n\tstruct acpi_device_software_node_port *ports;\n\tunsigned int num_ports;\n};\n\nstruct acpi_table_desc;\n\nstruct acpi_evaluate_info;\n\nstruct acpi_device_walk_info {\n\tstruct acpi_table_desc *table_desc;\n\tstruct acpi_evaluate_info *evaluate_info;\n\tu32 device_count;\n\tu32 num_STA;\n\tu32 num_INI;\n};\n\nstruct acpi_dlayer {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct acpi_dlevel {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct dma_chan;\n\nstruct acpi_dma_spec;\n\nstruct acpi_dma {\n\tstruct list_head dma_controllers;\n\tstruct device *dev;\n\tstruct dma_chan * (*acpi_dma_xlate)(struct acpi_dma_spec *, struct acpi_dma *);\n\tvoid *data;\n\tshort unsigned int base_request_line;\n\tshort unsigned int end_request_line;\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan *, void *);\n\nstruct acpi_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct acpi_dma_spec {\n\tint chan_id;\n\tint slave_id;\n\tstruct device *dev;\n};\n\nstruct acpi_dma_parser_data {\n\tstruct acpi_dma_spec dma_spec;\n\tsize_t index;\n\tsize_t n;\n};\n\nstruct of_device_id;\n\nstruct dev_pm_ops;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct acpi_driver {\n\tchar name[80];\n\tchar class[80];\n\tconst struct acpi_device_id *ids;\n\tunsigned int flags;\n\tstruct acpi_device_ops ops;\n\tstruct device_driver drv;\n};\n\nunion acpi_predefined_info;\n\nstruct acpi_evaluate_info {\n\tstruct acpi_namespace_node *prefix_node;\n\tconst char *relative_pathname;\n\tunion acpi_operand_object **parameters;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *obj_desc;\n\tchar *full_pathname;\n\tconst union acpi_predefined_info *predefined;\n\tunion acpi_operand_object *return_object;\n\tunion acpi_operand_object *parent_package;\n\tu32 return_flags;\n\tu32 return_btype;\n\tu16 param_count;\n\tu16 node_flags;\n\tu8 pass_number;\n\tu8 return_object_type;\n\tu8 flags;\n};\n\nstruct acpi_exception_info {\n\tchar *name;\n};\n\nstruct acpi_exdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n} __attribute__((packed));\n\nstruct acpi_fadt_info {\n\tconst char *name;\n\tu16 address64;\n\tu16 address32;\n\tu16 length;\n\tu8 default_length;\n\tu8 flags;\n};\n\nstruct acpi_generic_address;\n\nstruct acpi_fadt_pm_info {\n\tstruct acpi_generic_address *target;\n\tu16 source;\n\tu8 register_num;\n};\n\nstruct acpi_fan_fif {\n\tu8 revision;\n\tu8 fine_grain_ctrl;\n\tu8 step_size;\n\tu8 low_speed_notification;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct acpi_fan_fps;\n\nstruct thermal_cooling_device;\n\nstruct acpi_fan {\n\tacpi_handle handle;\n\tbool acpi4;\n\tbool has_fst;\n\tstruct acpi_fan_fif fif;\n\tstruct acpi_fan_fps *fps;\n\tint fps_count;\n\tu32 fan_trip_granularity;\n\tstruct device *hdev;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device_attribute fst_speed;\n\tstruct device_attribute fine_grain_control;\n};\n\nstruct acpi_fan_fps {\n\tu64 control;\n\tu64 trip_point;\n\tu64 speed;\n\tu64 noise_level;\n\tu64 power;\n\tchar name[20];\n\tstruct device_attribute dev_attr;\n};\n\nstruct acpi_fan_fst {\n\tu64 revision;\n\tu64 control;\n\tu64 speed;\n};\n\nstruct acpi_ffh_info {\n\tu64 offset;\n\tu64 length;\n};\n\nstruct acpi_ged_device {\n\tstruct device *dev;\n\tstruct list_head event_list;\n};\n\nstruct acpi_ged_event {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int gsi;\n\tunsigned int irq;\n\tacpi_handle handle;\n};\n\nstruct acpi_ged_handler_info {\n\tstruct acpi_ged_handler_info *next;\n\tu32 int_id;\n\tstruct acpi_namespace_node *evt_method;\n};\n\nstruct acpi_generic_address {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_update_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *object;\n};\n\nstruct acpi_scope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_pscope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 arg_count;\n\tunion acpi_parse_object *op;\n\tu8 *arg_end;\n\tu8 *pkg_end;\n\tu32 arg_list;\n};\n\nstruct acpi_pkg_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 index;\n\tunion acpi_operand_object *source_object;\n\tunion acpi_operand_object *dest_object;\n\tstruct acpi_walk_state *walk_state;\n\tvoid *this_target_obj;\n\tu32 num_packages;\n};\n\nstruct acpi_thread_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 current_sync_level;\n\tstruct acpi_walk_state *walk_state_list;\n\tunion acpi_operand_object *acquired_mutex_list;\n\tu64 thread_id;\n};\n\nstruct acpi_result_values {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *obj_desc[8];\n};\n\nstruct acpi_global_notify_handler;\n\nstruct acpi_notify_info {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 handler_list_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler_list_head;\n\tstruct acpi_global_notify_handler *global;\n};\n\nunion acpi_generic_state {\n\tstruct acpi_common_state common;\n\tstruct acpi_control_state control;\n\tstruct acpi_update_state update;\n\tstruct acpi_scope_state scope;\n\tstruct acpi_pscope_state parse_scope;\n\tstruct acpi_pkg_state pkg;\n\tstruct acpi_thread_state thread;\n\tstruct acpi_result_values results;\n\tstruct acpi_notify_info notify;\n};\n\nstruct acpi_genl_event {\n\tacpi_device_class device_class;\n\tchar bus_id[15];\n\tu32 type;\n\tu32 data;\n};\n\ntypedef acpi_status (*acpi_walk_callback)(acpi_handle, u32, void *, void **);\n\nstruct acpi_get_devices_info {\n\tacpi_walk_callback user_function;\n\tvoid *context;\n\tconst char *hid;\n};\n\nstruct acpi_global_notify_handler {\n\tacpi_notify_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_gpe_address {\n\tu8 space_id;\n\tu64 address;\n};\n\nstruct acpi_gpe_xrupt_info;\n\nstruct acpi_gpe_register_info;\n\nstruct acpi_gpe_event_info;\n\nstruct acpi_gpe_block_info {\n\tstruct acpi_namespace_node *node;\n\tstruct acpi_gpe_block_info *previous;\n\tstruct acpi_gpe_block_info *next;\n\tstruct acpi_gpe_xrupt_info *xrupt_block;\n\tstruct acpi_gpe_register_info *register_info;\n\tstruct acpi_gpe_event_info *event_info;\n\tu64 address;\n\tu32 register_count;\n\tu16 gpe_count;\n\tu16 block_base_number;\n\tu8 space_id;\n\tu8 initialized;\n};\n\nstruct acpi_gpe_handler_info;\n\nstruct acpi_gpe_notify_info;\n\nunion acpi_gpe_dispatch_info {\n\tstruct acpi_namespace_node *method_node;\n\tstruct acpi_gpe_handler_info *handler;\n\tstruct acpi_gpe_notify_info *notify_list;\n};\n\nstruct acpi_gpe_event_info {\n\tunion acpi_gpe_dispatch_info dispatch;\n\tstruct acpi_gpe_register_info *register_info;\n\tu8 flags;\n\tu8 gpe_number;\n\tu8 runtime_count;\n\tu8 disable_for_dispatch;\n};\n\ntypedef u32 (*acpi_gpe_handler)(acpi_handle, u32, void *);\n\nstruct acpi_gpe_handler_info {\n\tacpi_gpe_handler address;\n\tvoid *context;\n\tstruct acpi_namespace_node *method_node;\n\tu8 original_flags;\n\tu8 originally_enabled;\n};\n\nstruct acpi_gpe_notify_info {\n\tstruct acpi_namespace_node *device_node;\n\tstruct acpi_gpe_notify_info *next;\n};\n\nstruct acpi_gpe_register_info {\n\tstruct acpi_gpe_address status_address;\n\tstruct acpi_gpe_address enable_address;\n\tu16 base_gpe_number;\n\tu8 enable_for_wake;\n\tu8 enable_for_run;\n\tu8 mask_for_run;\n\tu8 enable_mask;\n};\n\nstruct acpi_gpe_xrupt_info {\n\tstruct acpi_gpe_xrupt_info *previous;\n\tstruct acpi_gpe_xrupt_info *next;\n\tstruct acpi_gpe_block_info *gpe_block_list_head;\n\tu32 interrupt_number;\n};\n\nstruct gpio_chip;\n\nstruct acpi_gpio_chip {\n\tstruct acpi_connection_info conn_info;\n\tstruct list_head conns;\n\tstruct mutex conn_lock;\n\tstruct gpio_chip *chip;\n\tstruct list_head events;\n\tstruct list_head deferred_req_irqs_list_entry;\n};\n\nstruct gpio_desc;\n\nstruct acpi_gpio_connection {\n\tstruct list_head node;\n\tunsigned int pin;\n\tstruct gpio_desc *desc;\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct acpi_gpio_event {\n\tstruct list_head node;\n\tacpi_handle handle;\n\tirq_handler_t handler;\n\tunsigned int pin;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tbool irq_is_wake;\n\tbool irq_requested;\n\tstruct gpio_desc *desc;\n};\n\nstruct acpi_gpio_info {\n\tstruct acpi_device *adev;\n\tenum gpiod_flags flags;\n\tbool gpioint;\n\tbool wake_capable;\n\tint pin_config;\n\tint polarity;\n\tint triggering;\n\tunsigned int debounce;\n\tunsigned int quirks;\n};\n\nstruct acpi_gpio_params {\n\tunsigned int crs_entry_index;\n\tshort unsigned int line_index;\n\tbool active_low;\n};\n\nstruct acpi_gpio_lookup {\n\tstruct acpi_gpio_params params;\n\tstruct acpi_gpio_info *info;\n\tstruct gpio_desc *desc;\n\tint n;\n};\n\nstruct acpi_gpio_mapping {\n\tconst char *name;\n\tconst struct acpi_gpio_params *data;\n\tunsigned int size;\n\tunsigned int quirks;\n};\n\nstruct acpi_gpiolib_dmi_quirk {\n\tbool no_edge_events_on_boot;\n\tchar *ignore_wake;\n\tchar *ignore_interrupt;\n};\n\nstruct acpi_handle_list {\n\tu32 count;\n\tacpi_handle *handles;\n};\n\nstruct acpi_hardware_id {\n\tstruct list_head list;\n\tconst char *id;\n};\n\nstruct acpi_hmat_structure {\n\tu16 type;\n\tu16 reserved;\n\tu32 length;\n};\n\ntypedef int (*acpi_hp_notify)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_uevent)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_fixup)(struct acpi_device *);\n\nstruct acpi_hotplug_context {\n\tstruct acpi_device *self;\n\tacpi_hp_notify notify;\n\tacpi_hp_uevent uevent;\n\tacpi_hp_fixup fixup;\n};\n\nstruct acpi_hotplug_profile {\n\tstruct kobject kobj;\n\tint (*scan_dependent)(struct acpi_device *);\n\tvoid (*notify_online)(struct acpi_device *);\n\tbool enabled: 1;\n\tbool demand_offline: 1;\n};\n\nstruct acpi_hp_work {\n\tstruct work_struct work;\n\tstruct acpi_device *adev;\n\tu32 src;\n};\n\nstruct acpi_init_walk_info {\n\tu32 table_index;\n\tu32 object_count;\n\tu32 method_count;\n\tu32 serial_method_count;\n\tu32 non_serial_method_count;\n\tu32 serialized_method_count;\n\tu32 device_count;\n\tu32 op_region_count;\n\tu32 field_count;\n\tu32 buffer_count;\n\tu32 package_count;\n\tu32 op_region_init;\n\tu32 field_init;\n\tu32 buffer_init;\n\tu32 package_init;\n\tacpi_owner_id owner_id;\n};\n\nstruct acpi_interface_info {\n\tchar *name;\n\tstruct acpi_interface_info *next;\n\tu8 flags;\n\tu8 value;\n};\n\nstruct acpi_io_attribute {\n\tu8 range_type;\n\tu8 translation;\n\tu8 translation_type;\n\tu8 reserved1;\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct acpi_ioremap {\n\tstruct list_head list;\n\tvoid *virt;\n\tacpi_physical_address phys;\n\tacpi_size size;\n\tunion {\n\t\tlong unsigned int refcount;\n\t\tstruct rcu_work rwork;\n\t} track;\n};\n\nstruct acpi_irq_dep_ctx {\n\tint rc;\n\tunsigned int index;\n\tacpi_handle handle;\n};\n\nstruct irq_fwspec;\n\nstruct acpi_irq_parse_one_ctx {\n\tint rc;\n\tunsigned int index;\n\tlong unsigned int *res_flags;\n\tstruct irq_fwspec *fwspec;\n};\n\nstruct acpi_lpat {\n\tint temp;\n\tint raw;\n};\n\nstruct acpi_lpat_conversion_table {\n\tstruct acpi_lpat *lpat;\n\tint lpat_count;\n};\n\nstruct acpi_lpi_state {\n\tu32 min_residency;\n\tu32 wake_latency;\n\tu32 flags;\n\tu32 arch_flags;\n\tu32 res_cnt_freq;\n\tu32 enable_parent_state;\n\tu64 address;\n\tu8 index;\n\tu8 entry_method;\n\tchar desc[32];\n};\n\nstruct acpi_lpi_states_array {\n\tunsigned int size;\n\tunsigned int composite_states_size;\n\tstruct acpi_lpi_state *entries;\n\tstruct acpi_lpi_state *composite_states[8];\n};\n\nstruct acpi_subtable_header {\n\tu8 type;\n\tu8 length;\n};\n\nstruct acpi_madt_aplic {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 id;\n\tu32 flags;\n\tu8 hw_id[8];\n\tu16 num_idcs;\n\tu16 num_sources;\n\tu32 gsi_base;\n\tu64 base_addr;\n\tu32 size;\n} __attribute__((packed));\n\nstruct acpi_madt_core_pic {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu32 processor_id;\n\tu32 core_id;\n\tu32 flags;\n} __attribute__((packed));\n\nstruct acpi_madt_generic_distributor {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 gic_id;\n\tu64 base_address;\n\tu32 global_irq_base;\n\tu8 version;\n\tu8 reserved2[3];\n};\n\nstruct acpi_madt_generic_interrupt {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 cpu_interface_number;\n\tu32 uid;\n\tu32 flags;\n\tu32 parking_version;\n\tu32 performance_interrupt;\n\tu64 parked_address;\n\tu64 base_address;\n\tu64 gicv_base_address;\n\tu64 gich_base_address;\n\tu32 vgic_interrupt;\n\tu64 gicr_base_address;\n\tu64 arm_mpidr;\n\tu8 efficiency_class;\n\tu8 reserved2[1];\n\tu16 spe_interrupt;\n\tu16 trbe_interrupt;\n\tu16 iaffid;\n\tu32 irs_id;\n} __attribute__((packed));\n\nstruct acpi_madt_imsic {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 reserved;\n\tu32 flags;\n\tu16 num_ids;\n\tu16 num_guest_ids;\n\tu8 guest_index_bits;\n\tu8 hart_index_bits;\n\tu8 group_index_bits;\n\tu8 group_index_shift;\n};\n\nstruct acpi_madt_interrupt_override {\n\tstruct acpi_subtable_header header;\n\tu8 bus;\n\tu8 source_irq;\n\tu32 global_irq;\n\tu16 inti_flags;\n} __attribute__((packed));\n\nstruct acpi_madt_interrupt_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu8 type;\n\tu8 id;\n\tu8 eid;\n\tu8 io_sapic_vector;\n\tu32 global_irq;\n\tu32 flags;\n};\n\nstruct acpi_madt_io_apic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 address;\n\tu32 global_irq_base;\n};\n\nstruct acpi_madt_io_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 global_irq_base;\n\tu64 address;\n};\n\nstruct acpi_madt_local_apic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu32 lapic_flags;\n};\n\nstruct acpi_madt_local_apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu16 inti_flags;\n\tu8 lint;\n} __attribute__((packed));\n\nstruct acpi_madt_local_apic_override {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_madt_local_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu8 eid;\n\tu8 reserved[3];\n\tu32 lapic_flags;\n\tu32 uid;\n\tchar uid_string[0];\n};\n\nstruct acpi_madt_local_x2apic {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 local_apic_id;\n\tu32 lapic_flags;\n\tu32 uid;\n};\n\nstruct acpi_madt_local_x2apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 uid;\n\tu8 lint;\n\tu8 reserved[3];\n};\n\nstruct acpi_madt_multiproc_wakeup {\n\tstruct acpi_subtable_header header;\n\tu16 version;\n\tu32 reserved;\n\tu64 mailbox_address;\n\tu64 reset_vector;\n};\n\nstruct acpi_madt_nmi_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 global_irq;\n};\n\nstruct acpi_madt_plic {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 id;\n\tu8 hw_id[8];\n\tu16 num_irqs;\n\tu16 max_prio;\n\tu32 flags;\n\tu32 size;\n\tu64 base_addr;\n\tu32 gsi_base;\n} __attribute__((packed));\n\nstruct acpi_madt_rintc {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 reserved;\n\tu32 flags;\n\tu64 hart_id;\n\tu32 uid;\n\tu32 ext_intc_id;\n\tu64 imsic_addr;\n\tu32 imsic_size;\n} __attribute__((packed));\n\nstruct acpi_mcfg_allocation {\n\tu64 address;\n\tu16 pci_segment;\n\tu8 start_bus_number;\n\tu8 end_bus_number;\n\tu32 reserved;\n};\n\nstruct acpi_mem_mapping {\n\tacpi_physical_address physical_address;\n\tu8 *logical_address;\n\tacpi_size length;\n\tstruct acpi_mem_mapping *next_mm;\n};\n\nstruct acpi_mem_space_context {\n\tu32 length;\n\tacpi_physical_address address;\n\tstruct acpi_mem_mapping *cur_mm;\n\tstruct acpi_mem_mapping *first_mm;\n};\n\nstruct acpi_memory_attribute {\n\tu8 write_protect;\n\tu8 caching;\n\tu8 range_type;\n\tu8 translation;\n};\n\nstruct acpi_mutex_info {\n\tvoid *mutex;\n\tu32 use_count;\n\tu64 thread_id;\n};\n\nstruct acpi_name_info {\n\tchar name[4];\n\tu16 argument_list;\n\tu8 expected_btypes;\n} __attribute__((packed));\n\nstruct acpi_namestring_info {\n\tconst char *external_name;\n\tconst char *next_external_char;\n\tchar *internal_name;\n\tu32 length;\n\tu32 num_segments;\n\tu32 num_carats;\n\tu8 fully_qualified;\n};\n\nunion acpi_object {\n\tacpi_object_type type;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu64 value;\n\t} integer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tchar *pointer;\n\t} string;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tu8 *pointer;\n\t} buffer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 count;\n\t\tunion acpi_object *elements;\n\t} package;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tacpi_object_type actual_type;\n\t\tacpi_handle handle;\n\t} reference;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 proc_id;\n\t\tacpi_io_address pblk_address;\n\t\tu32 pblk_length;\n\t} processor;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 system_level;\n\t\tu32 resource_order;\n\t} power_resource;\n};\n\nstruct acpi_object_list {\n\tu32 count;\n\tunion acpi_object *pointer;\n};\n\nstruct acpi_offsets {\n\tsize_t offset;\n\tu8 mode;\n};\n\nstruct acpi_opcode_info {\n\tchar *name;\n\tu32 parse_args;\n\tu32 runtime_args;\n\tu16 flags;\n\tu8 object_type;\n\tu8 class;\n\tu8 type;\n};\n\ntypedef void (*acpi_osd_exec_callback)(void *);\n\nstruct acpi_os_dpc {\n\tacpi_osd_exec_callback function;\n\tvoid *context;\n\tstruct work_struct work;\n};\n\nstruct acpi_osc_context {\n\tchar *uuid_str;\n\tint rev;\n\tstruct acpi_buffer cap;\n\tstruct acpi_buffer ret;\n};\n\nstruct acpi_osi_config {\n\tu8 default_disabling;\n\tunsigned int linux_enable: 1;\n\tunsigned int linux_dmi: 1;\n\tunsigned int linux_cmdline: 1;\n\tunsigned int darwin_enable: 1;\n\tunsigned int darwin_dmi: 1;\n\tunsigned int darwin_cmdline: 1;\n};\n\nstruct acpi_osi_entry {\n\tchar string[64];\n\tbool enable;\n};\n\nstruct acpi_package_info {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 object_type2;\n\tu8 count2;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info2 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[4];\n\tu8 reserved;\n};\n\nstruct acpi_package_info3 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[2];\n\tu8 tail_object_type;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info4 {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 sub_object_types;\n\tu8 pkg_count;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_parse_state {\n\tu8 *aml_start;\n\tu8 *aml;\n\tu8 *aml_end;\n\tu8 *pkg_start;\n\tu8 *pkg_end;\n\tunion acpi_parse_object *start_op;\n\tstruct acpi_namespace_node *start_node;\n\tunion acpi_generic_state *scope;\n\tunion acpi_parse_object *start_scope;\n\tu32 aml_size;\n};\n\nstruct acpi_pcc_info {\n\tu8 subspace_id;\n\tu16 length;\n\tu8 *internal_buffer;\n};\n\nstruct acpi_pcct_ext_pcc_master {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved1;\n\tu64 base_address;\n\tu32 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu32 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_set_mask;\n\tu64 reserved2;\n\tstruct acpi_generic_address cmd_complete_register;\n\tu64 cmd_complete_mask;\n\tstruct acpi_generic_address cmd_update_register;\n\tu64 cmd_update_preserve_mask;\n\tu64 cmd_update_set_mask;\n\tstruct acpi_generic_address error_status_register;\n\tu64 error_status_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_ext_pcc_shared_memory {\n\tu32 signature;\n\tu32 flags;\n\tu32 length;\n\tu32 command;\n};\n\nstruct acpi_pcct_hw_reduced {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pcct_hw_reduced_type2 {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_write_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_shared_memory {\n\tu32 signature;\n\tu16 command;\n\tu16 status;\n};\n\nstruct acpi_pcct_subspace {\n\tstruct acpi_subtable_header header;\n\tu8 reserved[6];\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pci_device {\n\tacpi_handle device;\n\tstruct acpi_pci_device *next;\n};\n\nstruct acpi_pci_root;\n\nstruct acpi_pci_root_ops;\n\nstruct acpi_pci_root_info {\n\tstruct acpi_pci_root *root;\n\tstruct acpi_device *bridge;\n\tstruct acpi_pci_root_ops *ops;\n\tstruct list_head resources;\n\tchar name[16];\n};\n\nstruct pci_config_window;\n\nstruct acpi_pci_generic_root_info {\n\tstruct acpi_pci_root_info common;\n\tstruct pci_config_window *cfg;\n};\n\nstruct acpi_pci_id {\n\tu16 segment;\n\tu16 bus;\n\tu16 device;\n\tu16 function;\n};\n\nstruct acpi_pci_link_irq {\n\tu32 active;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 resource_type;\n\tu8 possible_count;\n\tu32 possible[16];\n\tu8 initialized: 1;\n\tu8 reserved: 7;\n};\n\nstruct acpi_pci_link {\n\tstruct list_head list;\n\tstruct acpi_device *device;\n\tstruct acpi_pci_link_irq irq;\n\tint refcnt;\n};\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct pci_bus;\n\nstruct acpi_pci_root {\n\tstruct acpi_device *device;\n\tstruct pci_bus *bus;\n\tu16 segment;\n\tint bridge_type;\n\tstruct resource secondary;\n\tu32 osc_support_set;\n\tu32 osc_control_set;\n\tu32 osc_ext_support_set;\n\tu32 osc_ext_control_set;\n\tphys_addr_t mcfg_addr;\n};\n\nstruct pci_ops;\n\nstruct acpi_pci_root_ops {\n\tstruct pci_ops *pci_ops;\n\tint (*init_info)(struct acpi_pci_root_info *);\n\tvoid (*release_info)(struct acpi_pci_root_info *);\n\tint (*prepare_resources)(struct acpi_pci_root_info *);\n};\n\nstruct acpi_pci_routing_table {\n\tu32 length;\n\tu32 pin;\n\tu64 address;\n\tu32 source_index;\n\tunion {\n\t\tchar pad[4];\n\t\tstruct {\n\t\t\tstruct {} __Empty_source;\n\t\t\tchar source[0];\n\t\t};\n\t};\n};\n\nstruct acpi_pct_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_pkg_info {\n\tu8 *free_space;\n\tacpi_size length;\n\tu32 object_space;\n\tu32 num_packages;\n};\n\nstruct acpi_platform_list {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n\tchar *table;\n\tenum acpi_predicate pred;\n\tchar *reason;\n\tu32 data;\n};\n\nstruct acpi_pld_info {\n\tu8 revision;\n\tu8 ignore_color;\n\tu8 red;\n\tu8 green;\n\tu8 blue;\n\tu16 width;\n\tu16 height;\n\tu8 user_visible;\n\tu8 dock;\n\tu8 lid;\n\tu8 panel;\n\tu8 vertical_position;\n\tu8 horizontal_position;\n\tu8 shape;\n\tu8 group_orientation;\n\tu8 group_token;\n\tu8 group_position;\n\tu8 bay;\n\tu8 ejectable;\n\tu8 ospm_eject_required;\n\tu8 cabinet_number;\n\tu8 card_cage_number;\n\tu8 reference;\n\tu8 rotation;\n\tu8 order;\n\tu8 reserved;\n\tu16 vertical_offset;\n\tu16 horizontal_offset;\n};\n\nstruct acpi_port_info {\n\tchar *name;\n\tu16 start;\n\tu16 end;\n\tu8 osi_dependency;\n};\n\nstruct acpi_power_dependent_device {\n\tstruct device *dev;\n\tstruct list_head node;\n};\n\nstruct acpi_power_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_power_resource {\n\tstruct acpi_device device;\n\tstruct list_head list_node;\n\tu32 system_level;\n\tu32 order;\n\tunsigned int ref_count;\n\tu8 state;\n\tstruct mutex resource_lock;\n\tstruct list_head dependents;\n};\n\nstruct acpi_power_resource_entry {\n\tstruct list_head node;\n\tstruct acpi_power_resource *resource;\n};\n\nstruct acpi_pptt_cache {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 flags;\n\tu32 next_level_of_cache;\n\tu32 size;\n\tu32 number_of_sets;\n\tu8 associativity;\n\tu8 attributes;\n\tu16 line_size;\n};\n\nstruct acpi_pptt_cache_v1_full {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 flags;\n\tu32 next_level_of_cache;\n\tu32 size;\n\tu32 number_of_sets;\n\tu8 associativity;\n\tu8 attributes;\n\tu16 line_size;\n\tu32 cache_id;\n};\n\nstruct acpi_pptt_processor {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 flags;\n\tu32 parent;\n\tu32 acpi_processor_id;\n\tu32 number_of_priv_resources;\n};\n\nunion acpi_predefined_info {\n\tstruct acpi_name_info info;\n\tstruct acpi_package_info ret_info;\n\tstruct acpi_package_info2 ret_info2;\n\tstruct acpi_package_info3 ret_info3;\n\tstruct acpi_package_info4 ret_info4;\n};\n\nstruct acpi_predefined_names {\n\tconst char *name;\n\tu8 type;\n\tchar *val;\n};\n\nstruct acpi_prmt_module_header {\n\tu16 revision;\n\tu16 length;\n};\n\nstruct acpi_probe_entry;\n\ntypedef bool (*acpi_probe_entry_validate_subtbl)(struct acpi_subtable_header *, struct acpi_probe_entry *);\n\nstruct acpi_table_header;\n\ntypedef int (*acpi_tbl_table_handler)(struct acpi_table_header *);\n\nunion acpi_subtable_headers;\n\ntypedef int (*acpi_tbl_entry_handler)(union acpi_subtable_headers *, const long unsigned int);\n\nstruct acpi_probe_entry {\n\t__u8 id[5];\n\t__u8 type;\n\tacpi_probe_entry_validate_subtbl subtable_valid;\n\tunion {\n\t\tacpi_tbl_table_handler probe_table;\n\t\tacpi_tbl_entry_handler probe_subtbl;\n\t};\n\tkernel_ulong_t driver_data;\n};\n\nstruct acpi_processor_flags {\n\tu8 power: 1;\n\tu8 performance: 1;\n\tu8 throttling: 1;\n\tu8 limit: 1;\n\tu8 bm_control: 1;\n\tu8 bm_check: 1;\n\tu8 has_cst: 1;\n\tu8 has_lpi: 1;\n\tu8 power_setup_done: 1;\n\tu8 bm_rld_set: 1;\n\tu8 previously_online: 1;\n};\n\nstruct acpi_processor_cx {\n\tu8 valid;\n\tu8 type;\n\tu32 address;\n\tu8 entry_method;\n\tu8 index;\n\tu32 latency;\n\tu8 bm_sts_skip;\n\tchar desc[32];\n};\n\nstruct acpi_processor_power {\n\tint count;\n\tunion {\n\t\tstruct acpi_processor_cx states[8];\n\t\tstruct acpi_lpi_state lpi_states[8];\n\t};\n\tint timer_broadcast_on_state;\n};\n\nstruct acpi_tsd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct acpi_processor_tx {\n\tu16 power;\n\tu16 performance;\n};\n\nstruct acpi_processor_tx_tss;\n\nstruct acpi_processor;\n\nstruct acpi_processor_throttling {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_tx_tss *states_tss;\n\tstruct acpi_tsd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tint (*acpi_processor_get_throttling)(struct acpi_processor *);\n\tint (*acpi_processor_set_throttling)(struct acpi_processor *, int, bool);\n\tu32 address;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 tsd_valid_flag;\n\tunsigned int shared_type;\n\tstruct acpi_processor_tx states[16];\n};\n\nstruct acpi_processor_lx {\n\tint px;\n\tint tx;\n};\n\nstruct acpi_processor_limit {\n\tstruct acpi_processor_lx state;\n\tstruct acpi_processor_lx thermal;\n\tstruct acpi_processor_lx user;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct freq_constraints;\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct acpi_processor_performance;\n\nstruct acpi_processor {\n\tacpi_handle handle;\n\tu32 acpi_id;\n\tphys_cpuid_t phys_id;\n\tu32 id;\n\tu32 pblk;\n\tint performance_platform_limit;\n\tint throttling_platform_limit;\n\tstruct acpi_processor_flags flags;\n\tstruct acpi_processor_power power;\n\tstruct acpi_processor_performance *performance;\n\tstruct acpi_processor_throttling throttling;\n\tstruct acpi_processor_limit limit;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device *dev;\n\tstruct freq_qos_request perflib_req;\n\tstruct freq_qos_request thermal_req;\n};\n\nstruct acpi_processor_errata {\n\tu8 smp;\n\tstruct {\n\t\tu8 throttle: 1;\n\t\tu8 fdma: 1;\n\t\tu8 reserved: 6;\n\t\tu32 bmisx;\n\t} piix4;\n};\n\nstruct acpi_psd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_processor_px;\n\nstruct acpi_processor_performance {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_px *states;\n\tstruct acpi_psd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tunsigned int shared_type;\n};\n\nstruct acpi_processor_px {\n\tu64 core_frequency;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 bus_master_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_processor_tx_tss {\n\tu64 freqpercentage;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_prt_entry {\n\tstruct acpi_pci_id id;\n\tu8 pin;\n\tacpi_handle link;\n\tu32 index;\n};\n\nstruct acpi_reg_walk_info {\n\tu32 function;\n\tu32 reg_run_count;\n\tacpi_adr_space_type space_id;\n};\n\ntypedef acpi_status (*acpi_repair_function)(struct acpi_evaluate_info *, union acpi_operand_object **);\n\nstruct acpi_repair_info {\n\tchar name[4];\n\tacpi_repair_function repair_function;\n};\n\nstruct acpi_resource_irq {\n\tu8 descriptor_length;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tunion {\n\t\tu8 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu8 interrupts[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_dma {\n\tu8 type;\n\tu8 bus_master;\n\tu8 transfer;\n\tu8 channel_count;\n\tunion {\n\t\tu8 channel;\n\t\tstruct {\n\t\t\tstruct {} __Empty_channels;\n\t\t\tu8 channels[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_start_dependent {\n\tu8 descriptor_length;\n\tu8 compatibility_priority;\n\tu8 performance_robustness;\n};\n\nstruct acpi_resource_io {\n\tu8 io_decode;\n\tu8 alignment;\n\tu8 address_length;\n\tu16 minimum;\n\tu16 maximum;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_io {\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_dma {\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct acpi_resource_vendor {\n\tu16 byte_length;\n\tu8 byte_data[0];\n};\n\nstruct acpi_resource_vendor_typed {\n\tu16 byte_length;\n\tu8 uuid_subtype;\n\tu8 uuid[16];\n\tu8 byte_data[0];\n} __attribute__((packed));\n\nstruct acpi_resource_end_tag {\n\tu8 checksum;\n};\n\nstruct acpi_resource_memory24 {\n\tu8 write_protect;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_memory32 {\n\tu8 write_protect;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_memory32 {\n\tu8 write_protect;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nunion acpi_resource_attribute {\n\tstruct acpi_memory_attribute mem;\n\tstruct acpi_io_attribute io;\n\tu8 type_specific;\n};\n\nstruct acpi_resource_source {\n\tu8 index;\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_address16 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address16_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address32 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address32_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address64_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tu8 revision_ID;\n\tstruct acpi_address64_attribute address;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_irq {\n\tu8 producer_consumer;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tstruct acpi_resource_source resource_source;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct acpi_resource_generic_register {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_resource_gpio {\n\tu8 revision_id;\n\tu8 connection_type;\n\tu8 producer_consumer;\n\tu8 pin_config;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 io_restriction;\n\tu8 triggering;\n\tu8 polarity;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_i2c_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 access_mode;\n\tu16 slave_address;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_spi_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 wire_mode;\n\tu8 device_polarity;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_uart_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 endian;\n\tu8 data_bits;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 parity;\n\tu8 lines_enabled;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu32 default_baud_rate;\n} __attribute__((packed));\n\nstruct acpi_resource_csi2_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 local_port_instance;\n\tu8 phy_type;\n} __attribute__((packed));\n\nstruct acpi_resource_common_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_function {\n\tu8 revision_id;\n\tu8 pin_config;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_label {\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tu16 *pin_table;\n\tstruct acpi_resource_label resource_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_function {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_clock_input {\n\tu8 revision_id;\n\tu8 mode;\n\tu8 scale;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n};\n\nunion acpi_resource_data {\n\tstruct acpi_resource_irq irq;\n\tstruct acpi_resource_dma dma;\n\tstruct acpi_resource_start_dependent start_dpf;\n\tstruct acpi_resource_io io;\n\tstruct acpi_resource_fixed_io fixed_io;\n\tstruct acpi_resource_fixed_dma fixed_dma;\n\tstruct acpi_resource_vendor vendor;\n\tstruct acpi_resource_vendor_typed vendor_typed;\n\tstruct acpi_resource_end_tag end_tag;\n\tstruct acpi_resource_memory24 memory24;\n\tstruct acpi_resource_memory32 memory32;\n\tstruct acpi_resource_fixed_memory32 fixed_memory32;\n\tstruct acpi_resource_address16 address16;\n\tstruct acpi_resource_address32 address32;\n\tstruct acpi_resource_address64 address64;\n\tstruct acpi_resource_extended_address64 ext_address64;\n\tstruct acpi_resource_extended_irq extended_irq;\n\tstruct acpi_resource_generic_register generic_reg;\n\tstruct acpi_resource_gpio gpio;\n\tstruct acpi_resource_i2c_serialbus i2c_serial_bus;\n\tstruct acpi_resource_spi_serialbus spi_serial_bus;\n\tstruct acpi_resource_uart_serialbus uart_serial_bus;\n\tstruct acpi_resource_csi2_serialbus csi2_serial_bus;\n\tstruct acpi_resource_common_serialbus common_serial_bus;\n\tstruct acpi_resource_pin_function pin_function;\n\tstruct acpi_resource_pin_config pin_config;\n\tstruct acpi_resource_pin_group pin_group;\n\tstruct acpi_resource_pin_group_function pin_group_function;\n\tstruct acpi_resource_pin_group_config pin_group_config;\n\tstruct acpi_resource_clock_input clock_input;\n\tstruct acpi_resource_address address;\n};\n\nstruct acpi_resource {\n\tu32 type;\n\tu32 length;\n\tunion acpi_resource_data data;\n};\n\nstruct acpi_rhct_cmo_node {\n\tu8 reserved;\n\tu8 cbom_size;\n\tu8 cbop_size;\n\tu8 cboz_size;\n};\n\nstruct acpi_rhct_hart_info {\n\tu16 num_offsets;\n\tu32 uid;\n} __attribute__((packed));\n\nstruct acpi_rhct_isa_string {\n\tu16 isa_length;\n\tchar isa[0];\n};\n\nstruct acpi_rhct_node_header {\n\tu16 type;\n\tu16 length;\n\tu16 revision;\n};\n\nstruct acpi_rimt_id_mapping {\n\tu32 source_id_base;\n\tu32 num_ids;\n\tu32 dest_id_base;\n\tu32 dest_offset;\n\tu32 flags;\n};\n\nstruct acpi_rimt_iommu {\n\tu8 hardware_id[8];\n\tu64 base_address;\n\tu32 flags;\n\tu32 proximity_domain;\n\tu16 pcie_segment_number;\n\tu16 pcie_bdf;\n\tu16 num_interrupt_wires;\n\tu16 interrupt_wire_offset;\n\tu64 interrupt_wire[0];\n};\n\nstruct acpi_rimt_node {\n\tu8 type;\n\tu8 revision;\n\tu16 length;\n\tu16 reserved;\n\tu16 id;\n\tchar node_data[0];\n};\n\nstruct acpi_rimt_pcie_rc {\n\tu32 flags;\n\tu16 reserved;\n\tu16 pcie_segment_number;\n\tu16 id_mapping_offset;\n\tu16 num_id_mappings;\n};\n\nstruct acpi_rimt_platform_device {\n\tu16 id_mapping_offset;\n\tu16 num_id_mappings;\n\tchar device_name[0];\n};\n\nstruct acpi_rsconvert_info {\n\tu8 opcode;\n\tu8 resource_offset;\n\tu8 aml_offset;\n\tu8 value;\n};\n\nstruct acpi_rsdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n\tconst char **pointer;\n} __attribute__((packed));\n\nstruct acpi_rw_lock {\n\tvoid *writer_mutex;\n\tvoid *reader_mutex;\n\tu32 num_readers;\n};\n\nstruct acpi_scan_handler {\n\tstruct list_head list_node;\n\tconst struct acpi_device_id *ids;\n\tbool (*match)(const char *, const struct acpi_device_id **);\n\tint (*attach)(struct acpi_device *, const struct acpi_device_id *);\n\tvoid (*detach)(struct acpi_device *);\n\tvoid (*post_eject)(struct acpi_device *);\n\tvoid (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n\tstruct acpi_hotplug_profile hotplug;\n};\n\nstruct acpi_scan_system_dev {\n\tstruct list_head node;\n\tstruct acpi_device *adev;\n};\n\ntypedef u32 (*acpi_sci_handler)(void *);\n\nstruct acpi_sci_handler_info {\n\tstruct acpi_sci_handler_info *next;\n\tacpi_sci_handler address;\n\tvoid *context;\n};\n\nstruct acpi_signal_fatal_info {\n\tu32 type;\n\tu32 code;\n\tu32 argument;\n};\n\ntypedef acpi_status (*acpi_object_converter)(struct acpi_namespace_node *, union acpi_operand_object *, union acpi_operand_object **);\n\nstruct acpi_simple_repair_info {\n\tchar name[4];\n\tu32 unexpected_btypes;\n\tu32 package_index;\n\tacpi_object_converter object_converter;\n};\n\nstruct spi_controller;\n\nstruct acpi_spi_lookup {\n\tstruct spi_controller *ctlr;\n\tu32 max_speed_hz;\n\tu32 mode;\n\tint irq;\n\tu8 bits_per_word;\n\tu8 chip_select;\n\tint n;\n\tint index;\n};\n\nstruct acpi_srat_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 proximity_domain_lo;\n\tu8 apic_id;\n\tu32 flags;\n\tu8 local_sapic_eid;\n\tu8 proximity_domain_hi[3];\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_generic_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 reserved;\n\tu8 device_handle_type;\n\tu32 proximity_domain;\n\tu8 device_handle[16];\n\tu32 flags;\n\tu32 reserved1;\n};\n\nstruct acpi_srat_gicc_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n} __attribute__((packed));\n\nstruct acpi_srat_mem_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu16 reserved;\n\tu64 base_address;\n\tu64 length;\n\tu32 reserved1;\n\tu32 flags;\n\tu64 reserved2;\n} __attribute__((packed));\n\nstruct acpi_srat_rintc_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_x2apic_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 apic_id;\n\tu32 flags;\n\tu32 clock_domain;\n\tu32 reserved2;\n};\n\nstruct acpi_subtable_entry {\n\tunion acpi_subtable_headers *hdr;\n\tenum acpi_subtable_type type;\n};\n\nunion acpi_subtable_headers {\n\tstruct acpi_subtable_header common;\n\tstruct acpi_hmat_structure hmat;\n\tstruct acpi_prmt_module_header prmt;\n\tstruct acpi_cedt_header cedt;\n\tstruct acpi_cdat_header cdat;\n};\n\ntypedef int (*acpi_tbl_entry_handler_arg)(union acpi_subtable_headers *, void *, const long unsigned int);\n\nstruct acpi_subtable_proc {\n\tint id;\n\tacpi_tbl_entry_handler handler;\n\tacpi_tbl_entry_handler_arg handler_arg;\n\tvoid *arg;\n\tint count;\n};\n\nstruct acpi_table_attr {\n\tstruct bin_attribute attr;\n\tchar name[4];\n\tint instance;\n\tchar filename[8];\n\tstruct list_head node;\n};\n\nstruct acpi_table_header {\n\tchar signature[4];\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tchar oem_id[6];\n\tchar oem_table_id[8];\n\tu32 oem_revision;\n\tchar asl_compiler_id[4];\n\tu32 asl_compiler_revision;\n};\n\nstruct acpi_table_bert {\n\tstruct acpi_table_header header;\n\tu32 region_length;\n\tu64 address;\n};\n\nstruct acpi_table_ccel {\n\tstruct acpi_table_header header;\n\tu8 CCtype;\n\tu8 Ccsub_type;\n\tu16 reserved;\n\tu64 log_area_minimum_length;\n\tu64 log_area_start_address;\n};\n\nstruct acpi_table_cdat {\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tu8 reserved[6];\n\tu32 sequence;\n};\n\nstruct acpi_table_csrt {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_table_desc {\n\tacpi_physical_address address;\n\tstruct acpi_table_header *pointer;\n\tu32 length;\n\tunion acpi_name_union signature;\n\tacpi_owner_id owner_id;\n\tu8 flags;\n\tu16 validation_count;\n};\n\nstruct acpi_table_facs {\n\tchar signature[4];\n\tu32 length;\n\tu32 hardware_signature;\n\tu32 firmware_waking_vector;\n\tu32 global_lock;\n\tu32 flags;\n\tu64 xfirmware_waking_vector;\n\tu8 version;\n\tu8 reserved[3];\n\tu32 ospm_flags;\n\tu8 reserved1[24];\n};\n\nstruct acpi_table_fadt {\n\tstruct acpi_table_header header;\n\tu32 facs;\n\tu32 dsdt;\n\tu8 model;\n\tu8 preferred_profile;\n\tu16 sci_interrupt;\n\tu32 smi_command;\n\tu8 acpi_enable;\n\tu8 acpi_disable;\n\tu8 s4_bios_request;\n\tu8 pstate_control;\n\tu32 pm1a_event_block;\n\tu32 pm1b_event_block;\n\tu32 pm1a_control_block;\n\tu32 pm1b_control_block;\n\tu32 pm2_control_block;\n\tu32 pm_timer_block;\n\tu32 gpe0_block;\n\tu32 gpe1_block;\n\tu8 pm1_event_length;\n\tu8 pm1_control_length;\n\tu8 pm2_control_length;\n\tu8 pm_timer_length;\n\tu8 gpe0_block_length;\n\tu8 gpe1_block_length;\n\tu8 gpe1_base;\n\tu8 cst_control;\n\tu16 c2_latency;\n\tu16 c3_latency;\n\tu16 flush_size;\n\tu16 flush_stride;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 day_alarm;\n\tu8 month_alarm;\n\tu8 century;\n\tu16 boot_flags;\n\tu8 reserved;\n\tu32 flags;\n\tstruct acpi_generic_address reset_register;\n\tu8 reset_value;\n\tu16 arm_boot_flags;\n\tu8 minor_revision;\n\tu64 Xfacs;\n\tu64 Xdsdt;\n\tstruct acpi_generic_address xpm1a_event_block;\n\tstruct acpi_generic_address xpm1b_event_block;\n\tstruct acpi_generic_address xpm1a_control_block;\n\tstruct acpi_generic_address xpm1b_control_block;\n\tstruct acpi_generic_address xpm2_control_block;\n\tstruct acpi_generic_address xpm_timer_block;\n\tstruct acpi_generic_address xgpe0_block;\n\tstruct acpi_generic_address xgpe1_block;\n\tstruct acpi_generic_address sleep_control;\n\tstruct acpi_generic_address sleep_status;\n\tu64 hypervisor_id;\n} __attribute__((packed));\n\nstruct acpi_table_list {\n\tstruct acpi_table_desc *tables;\n\tu32 current_table_count;\n\tu32 max_table_count;\n\tu8 flags;\n};\n\nstruct acpi_table_madt {\n\tstruct acpi_table_header header;\n\tu32 address;\n\tu32 flags;\n};\n\nstruct acpi_table_mcfg {\n\tstruct acpi_table_header header;\n\tu8 reserved[8];\n};\n\nstruct acpi_table_pcct {\n\tstruct acpi_table_header header;\n\tu32 flags;\n\tu64 reserved;\n};\n\nstruct acpi_table_rhct {\n\tstruct acpi_table_header header;\n\tu32 flags;\n\tu64 time_base_freq;\n\tu32 node_count;\n\tu32 node_offset;\n};\n\nstruct acpi_table_rimt {\n\tstruct acpi_table_header header;\n\tu32 num_nodes;\n\tu32 node_offset;\n\tu32 reserved;\n};\n\nstruct acpi_table_rsdp {\n\tchar signature[8];\n\tu8 checksum;\n\tchar oem_id[6];\n\tu8 revision;\n\tu32 rsdt_physical_address;\n\tu32 length;\n\tu64 xsdt_physical_address;\n\tu8 extended_checksum;\n\tu8 reserved[3];\n} __attribute__((packed));\n\nstruct acpi_table_slit {\n\tstruct acpi_table_header header;\n\tu64 locality_count;\n\tu8 entry[0];\n} __attribute__((packed));\n\nstruct acpi_table_spcr {\n\tstruct acpi_table_header header;\n\tu8 interface_type;\n\tu8 reserved[3];\n\tstruct acpi_generic_address serial_port;\n\tu8 interrupt_type;\n\tu8 pc_interrupt;\n\tu32 interrupt;\n\tu8 baud_rate;\n\tu8 parity;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 terminal_type;\n\tu8 language;\n\tu16 pci_device_id;\n\tu16 pci_vendor_id;\n\tu8 pci_bus;\n\tu8 pci_device;\n\tu8 pci_function;\n\tu32 pci_flags;\n\tu8 pci_segment;\n\tu32 uart_clk_freq;\n\tu32 precise_baudrate;\n\tu16 name_space_string_length;\n\tu16 name_space_string_offset;\n\tchar name_space_string[0];\n} __attribute__((packed));\n\nstruct acpi_table_srat {\n\tstruct acpi_table_header header;\n\tu32 table_revision;\n\tu64 reserved;\n};\n\nstruct acpi_table_stao {\n\tstruct acpi_table_header header;\n\tu8 ignore_uart;\n} __attribute__((packed));\n\nstruct acpi_thermal_trip {\n\tlong unsigned int temp_dk;\n\tstruct acpi_handle_list devices;\n};\n\nstruct acpi_thermal_passive {\n\tstruct acpi_thermal_trip trip;\n\tlong unsigned int tc1;\n\tlong unsigned int tc2;\n\tlong unsigned int delay;\n};\n\nstruct acpi_thermal_active {\n\tstruct acpi_thermal_trip trip;\n};\n\nstruct acpi_thermal_trips {\n\tstruct acpi_thermal_passive passive;\n\tstruct acpi_thermal_active active[10];\n};\n\nstruct thermal_zone_device;\n\nstruct acpi_thermal {\n\tstruct acpi_device *device;\n\tacpi_bus_id name;\n\tlong unsigned int temp_dk;\n\tlong unsigned int last_temp_dk;\n\tlong unsigned int polling_frequency;\n\tvolatile u8 zombie;\n\tstruct acpi_thermal_trips trips;\n\tstruct thermal_zone_device *thermal_zone;\n\tint kelvin_offset;\n\tstruct work_struct thermal_check_work;\n\tstruct mutex thermal_check_lock;\n\trefcount_t thermal_check_count;\n};\n\nstruct acpi_vendor_uuid {\n\tu8 subtype;\n\tu8 data[16];\n};\n\nstruct acpi_vendor_walk_info {\n\tstruct acpi_vendor_uuid *uuid;\n\tstruct acpi_buffer *buffer;\n\tacpi_status status;\n};\n\nstruct acpi_wakeup_handler {\n\tstruct list_head list_node;\n\tbool (*wakeup)(void *);\n\tvoid *context;\n};\n\nstruct acpi_walk_info {\n\tu32 debug_level;\n\tu32 count;\n\tacpi_owner_id owner_id;\n\tu8 display_type;\n};\n\ntypedef acpi_status (*acpi_parse_downwards)(struct acpi_walk_state *, union acpi_parse_object **);\n\ntypedef acpi_status (*acpi_parse_upwards)(struct acpi_walk_state *);\n\nstruct acpi_walk_state {\n\tstruct acpi_walk_state *next;\n\tu8 descriptor_type;\n\tu8 walk_type;\n\tu16 opcode;\n\tu8 next_op_info;\n\tu8 num_operands;\n\tu8 operand_index;\n\tacpi_owner_id owner_id;\n\tu8 last_predicate;\n\tu8 current_result;\n\tu8 return_used;\n\tu8 scope_depth;\n\tu8 pass_number;\n\tu8 namespace_override;\n\tu8 result_size;\n\tu8 result_count;\n\tu8 *aml;\n\tu32 arg_types;\n\tu32 method_breakpoint;\n\tu32 user_breakpoint;\n\tu32 parse_flags;\n\tstruct acpi_parse_state parser_state;\n\tu32 prev_arg_types;\n\tu32 arg_count;\n\tu16 method_nesting_depth;\n\tu8 method_is_nested;\n\tstruct acpi_namespace_node arguments[7];\n\tstruct acpi_namespace_node local_variables[8];\n\tunion acpi_operand_object *operands[9];\n\tunion acpi_operand_object **params;\n\tu8 *aml_last_while;\n\tunion acpi_operand_object **caller_return_desc;\n\tunion acpi_generic_state *control_state;\n\tstruct acpi_namespace_node *deferred_node;\n\tunion acpi_operand_object *implicit_return_obj;\n\tstruct acpi_namespace_node *method_call_node;\n\tunion acpi_parse_object *method_call_op;\n\tunion acpi_operand_object *method_desc;\n\tstruct acpi_namespace_node *method_node;\n\tchar *method_pathname;\n\tunion acpi_parse_object *op;\n\tconst struct acpi_opcode_info *op_info;\n\tunion acpi_parse_object *origin;\n\tunion acpi_operand_object *result_obj;\n\tunion acpi_generic_state *results;\n\tunion acpi_operand_object *return_desc;\n\tunion acpi_generic_state *scope_info;\n\tunion acpi_parse_object *prev_op;\n\tunion acpi_parse_object *next_op;\n\tstruct acpi_thread_state *thread;\n\tacpi_parse_downwards descending_callback;\n\tacpi_parse_upwards ascending_callback;\n};\n\nstruct pnp_dev;\n\nstruct acpipnp_parse_option_s {\n\tstruct pnp_dev *dev;\n\tunsigned int option_flags;\n};\n\nstruct action_cache {\n\tlong unsigned int allow_native[8];\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct action_gate_entry {\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n};\n\nstruct action_ops {\n\tint (*pre_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tint (*do_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*undo_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*post_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct audit_ntp_val {\n\tlong long int oldval;\n\tlong long int newval;\n};\n\nstruct audit_ntp_data {\n\tstruct audit_ntp_val vals[6];\n};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n};\n\nstruct adjust_trip_data {\n\tstruct acpi_thermal *tz;\n\tu32 event;\n};\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\nstruct aggregate_control {\n\tlong int *aggregate;\n\tlong int *local;\n\tlong int *pending;\n\tlong int *ppending;\n\tlong int *cstat;\n\tlong int *cstat_prev;\n\tint size;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\nstruct ata_link;\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct clk_bulk_data;\n\nstruct reset_control;\n\nstruct regulator;\n\nstruct phy;\n\nstruct ata_port;\n\nstruct ata_host;\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 mask_port_map;\n\tu32 mask_port_ext;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 saved_port_cap[32];\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tunsigned int n_clks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int f_rsts;\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[15];\n\tchar *irq_desc;\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct eventfd_ctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct alias_prop {\n\tstruct list_head link;\n\tconst char *alias;\n\tstruct device_node *np;\n\tint id;\n\tchar stem[0];\n};\n\nstruct aligned_lock {\n\tunion {\n\t\tspinlock_t lock;\n\t\tu8 cacheline_padding[64];\n\t};\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct psmouse;\n\nstruct alps_nibble_commands;\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct alt_entry {\n\ts32 old_offset;\n\ts32 alt_offset;\n\tu16 vendor_id;\n\tu16 alt_len;\n\tu32 patch_id;\n};\n\nstruct amba_cs_uci_id {\n\tunsigned int devarch;\n\tunsigned int devarch_mask;\n\tunsigned int devtype;\n\tvoid *data;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct amba_device {\n\tstruct device dev;\n\tstruct resource res;\n\tstruct clk *pclk;\n\tstruct device_dma_parameters dma_parms;\n\tunsigned int periphid;\n\tstruct mutex periphid_lock;\n\tunsigned int cid;\n\tstruct amba_cs_uci_id uci;\n\tunsigned int irq[9];\n\tconst char *driver_override;\n};\n\nstruct amba_id;\n\nstruct amba_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct amba_device *, const struct amba_id *);\n\tvoid (*remove)(struct amba_device *);\n\tvoid (*shutdown)(struct amba_device *);\n\tconst struct amba_id *id_table;\n\tbool driver_managed_dma;\n};\n\nstruct amba_id {\n\tunsigned int id;\n\tunsigned int mask;\n\tvoid *data;\n};\n\nstruct aml_resource_small_header {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_large_header {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_irq {\n\tu8 descriptor_type;\n\tu16 irq_mask;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct aml_resource_dma {\n\tu8 descriptor_type;\n\tu8 dma_channel_mask;\n\tu8 flags;\n};\n\nstruct aml_resource_start_dependent {\n\tu8 descriptor_type;\n\tu8 flags;\n};\n\nstruct aml_resource_end_dependent {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_io {\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu8 alignment;\n\tu8 address_length;\n};\n\nstruct aml_resource_fixed_io {\n\tu8 descriptor_type;\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_dma {\n\tu8 descriptor_type;\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_small {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_end_tag {\n\tu8 descriptor_type;\n\tu8 checksum;\n};\n\nstruct aml_resource_memory24 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_generic_register {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 address_space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_large {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address16 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_extended_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu8 revision_ID;\n\tu8 reserved;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct aml_resource_extended_irq {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu8 interrupt_count;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct aml_resource_gpio {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 connection_type;\n\tu16 flags;\n\tu16 int_flags;\n\tu8 pin_config;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_i2c_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu16 slave_address;\n} __attribute__((packed));\n\nstruct aml_resource_spi_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n} __attribute__((packed));\n\nstruct aml_resource_uart_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 default_baud_rate;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu8 parity;\n\tu8 lines_enabled;\n} __attribute__((packed));\n\nstruct aml_resource_csi2_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_common_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config;\n\tu16 function_number;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 pin_table_offset;\n\tu16 label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 function_number;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_clock_input {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n} __attribute__((packed));\n\nstruct aml_resource_address {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n} __attribute__((packed));\n\nunion aml_resource {\n\tu8 descriptor_type;\n\tstruct aml_resource_small_header small_header;\n\tstruct aml_resource_large_header large_header;\n\tstruct aml_resource_irq irq;\n\tstruct aml_resource_dma dma;\n\tstruct aml_resource_start_dependent start_dpf;\n\tstruct aml_resource_end_dependent end_dpf;\n\tstruct aml_resource_io io;\n\tstruct aml_resource_fixed_io fixed_io;\n\tstruct aml_resource_fixed_dma fixed_dma;\n\tstruct aml_resource_vendor_small vendor_small;\n\tstruct aml_resource_end_tag end_tag;\n\tstruct aml_resource_memory24 memory24;\n\tstruct aml_resource_generic_register generic_reg;\n\tstruct aml_resource_vendor_large vendor_large;\n\tstruct aml_resource_memory32 memory32;\n\tstruct aml_resource_fixed_memory32 fixed_memory32;\n\tstruct aml_resource_address16 address16;\n\tstruct aml_resource_address32 address32;\n\tstruct aml_resource_address64 address64;\n\tstruct aml_resource_extended_address64 ext_address64;\n\tstruct aml_resource_extended_irq extended_irq;\n\tstruct aml_resource_gpio gpio;\n\tstruct aml_resource_i2c_serialbus i2c_serial_bus;\n\tstruct aml_resource_spi_serialbus spi_serial_bus;\n\tstruct aml_resource_uart_serialbus uart_serial_bus;\n\tstruct aml_resource_csi2_serialbus csi2_serial_bus;\n\tstruct aml_resource_common_serialbus common_serial_bus;\n\tstruct aml_resource_pin_function pin_function;\n\tstruct aml_resource_pin_config pin_config;\n\tstruct aml_resource_pin_group pin_group;\n\tstruct aml_resource_pin_group_function pin_group_function;\n\tstruct aml_resource_pin_group_config pin_group_config;\n\tstruct aml_resource_clock_input clock_input;\n\tstruct aml_resource_address address;\n\tu32 dword_item;\n\tu16 word_item;\n\tu8 byte_item;\n};\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct apd_private_data;\n\nstruct apd_device_desc {\n\tunsigned int fixed_clk_rate;\n\tstruct property_entry *properties;\n\tint (*setup)(struct apd_private_data *);\n};\n\nstruct apd_private_data {\n\tstruct clk *clk;\n\tstruct acpi_device *adev;\n\tconst struct apd_device_desc *dev_desc;\n};\n\nstruct api_context {\n\tstruct completion done;\n\tint status;\n};\n\nstruct aplic_src_ctrl;\n\nstruct aplic_saved_regs {\n\tu32 domaincfg;\n\tstruct aplic_src_ctrl *srcs;\n};\n\nstruct aplic_msicfg {\n\tphys_addr_t base_ppn;\n\tu32 hhxs;\n\tu32 hhxw;\n\tu32 lhxs;\n\tu32 lhxw;\n};\n\nstruct aplic_priv {\n\tstruct list_head head;\n\tstruct notifier_block genpd_nb;\n\tstruct aplic_saved_regs saved_hw_regs;\n\tstruct device *dev;\n\tu32 gsi_base;\n\tu32 nr_irqs;\n\tu32 nr_idcs;\n\tu32 acpi_aplic_id;\n\tvoid *regs;\n\tstruct aplic_msicfg msicfg;\n};\n\nstruct aplic_direct {\n\tstruct aplic_priv priv;\n\tstruct irq_domain *irqdomain;\n\tstruct cpumask lmask;\n};\n\nstruct aplic_idc {\n\tu32 hart_index;\n\tvoid *regs;\n\tstruct aplic_direct *direct;\n};\n\nstruct aplic_src_ctrl {\n\tu32 sourcecfg;\n\tu32 target;\n\tu32 ie;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct lsm_network_audit;\n\nstruct lsm_ioctlop_audit;\n\nstruct lsm_ibpkey_audit;\n\nstruct lsm_ibendport_audit;\n\nstruct selinux_audit_data;\n\nstruct apparmor_audit_data;\n\nstruct common_audit_data {\n\tchar type;\n\tunion {\n\t\tstruct path path;\n\t\tstruct dentry *dentry;\n\t\tstruct inode *inode;\n\t\tstruct lsm_network_audit *net;\n\t\tint cap;\n\t\tint ipc_id;\n\t\tstruct task_struct *tsk;\n\t\tstruct {\n\t\t\tkey_serial_t key;\n\t\t\tchar *key_desc;\n\t\t} key_struct;\n\t\tchar *kmod_name;\n\t\tstruct lsm_ioctlop_audit *op;\n\t\tstruct file *file;\n\t\tstruct lsm_ibpkey_audit *ibpkey;\n\t\tstruct lsm_ibendport_audit *ibendport;\n\t\tint reason;\n\t\tconst char *anonclass;\n\t\tu16 nlmsg_type;\n\t} u;\n\tunion {\n\t\tstruct selinux_audit_data *selinux_audit_data;\n\t\tstruct apparmor_audit_data *apparmor_audit_data;\n\t};\n};\n\nstruct apparmor_audit_data {\n\tint error;\n\tint type;\n\tu16 class;\n\tconst char *op;\n\tconst struct cred *subj_cred;\n\tstruct aa_label *subj_label;\n\tconst char *name;\n\tconst char *info;\n\tu32 request;\n\tu32 denied;\n\tu32 tags;\n\tunion {\n\t\tstruct {\n\t\t\tstruct aa_label *peer;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tconst char *target;\n\t\t\t\t\tkuid_t ouid;\n\t\t\t\t} fs;\n\t\t\t\tstruct {\n\t\t\t\t\tint rlim;\n\t\t\t\t\tlong unsigned int max;\n\t\t\t\t} rlim;\n\t\t\t\tstruct {\n\t\t\t\t\tint signal;\n\t\t\t\t\tint unmappedsig;\n\t\t\t\t};\n\t\t\t\tstruct {\n\t\t\t\t\tint type;\n\t\t\t\t\tint protocol;\n\t\t\t\t\tvoid *addr;\n\t\t\t\t\tint addrlen;\n\t\t\t\t\tstruct {\n\t\t\t\t\t\tvoid *addr;\n\t\t\t\t\t\tint addrlen;\n\t\t\t\t\t} peer;\n\t\t\t\t} net;\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct aa_profile *profile;\n\t\t\tconst char *ns;\n\t\t\tlong int pos;\n\t\t} iface;\n\t\tstruct {\n\t\t\tconst char *src_name;\n\t\t\tconst char *type;\n\t\t\tconst char *trans;\n\t\t\tconst char *data;\n\t\t\tlong unsigned int flags;\n\t\t} mnt;\n\t\tstruct {\n\t\t\tstruct aa_label *target;\n\t\t} uring;\n\t};\n\tstruct common_audit_data common;\n};\n\nstruct page;\n\nstruct apply_range_data {\n\tstruct page **pages;\n\tint i;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct arch_elf_state {};\n\nstruct arch_ext_priv {\n\t__u32 magic;\n\tlong int (*save)(struct pt_regs *, void *);\n};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct arch_msi_msg_addr_hi {\n\tu32 address_hi;\n};\n\ntypedef struct arch_msi_msg_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct arch_msi_msg_addr_lo {\n\tu32 address_lo;\n};\n\ntypedef struct arch_msi_msg_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct arch_msi_msg_data {\n\tu32 data;\n};\n\ntypedef struct arch_msi_msg_data arch_msi_msg_data_t;\n\ntypedef bool probes_handler_t(u32, long unsigned int, struct pt_regs *);\n\nstruct arch_probe_insn {\n\tprobe_opcode_t *insn;\n\tprobes_handler_t *handler;\n\tlong unsigned int restore;\n};\n\nstruct arch_specific_insn {\n\tint dummy;\n};\n\nstruct arch_tlbflush_unmap_batch {\n\tstruct cpumask cpumask;\n};\n\nstruct arch_uprobe {\n\tunion {\n\t\tu8 insn[8];\n\t\tu8 ixol[8];\n\t};\n\tstruct arch_probe_insn api;\n\tlong unsigned int insn_size;\n\tbool simulate;\n};\n\nstruct arch_uprobe_task {\n\tlong unsigned int saved_cause;\n};\n\nstruct arch_vdso_time_data {};\n\nstruct arena_free_span {\n\tstruct llist_node node;\n\tlong unsigned int uaddr;\n\tu32 page_cnt;\n};\n\nstruct free_entry;\n\nstruct nd_btt;\n\nstruct arena_info {\n\tu64 size;\n\tu64 external_lba_start;\n\tu32 internal_nlba;\n\tu32 internal_lbasize;\n\tu32 external_nlba;\n\tu32 external_lbasize;\n\tu32 nfree;\n\tu16 version_major;\n\tu16 version_minor;\n\tu32 sector_size;\n\tu64 nextoff;\n\tu64 infooff;\n\tu64 dataoff;\n\tu64 mapoff;\n\tu64 logoff;\n\tu64 info2off;\n\tstruct free_entry *freelist;\n\tu32 *rtt;\n\tstruct aligned_lock *map_locks;\n\tstruct nd_btt *nd_btt;\n\tstruct list_head list;\n\tstruct dentry *debugfs_dir;\n\tu32 flags;\n\tstruct mutex err_lock;\n\tint log_index[2];\n};\n\nstruct arg_dev_net_ip {\n\tstruct net *net;\n\tstruct in6_addr *addr;\n};\n\nstruct arg_netdev_event {\n\tconst struct net_device *dev;\n\tunion {\n\t\tunsigned char nh_flags;\n\t\tlong unsigned int event;\n\t};\n};\n\nstruct args_askumount {\n\t__u32 may_umount;\n};\n\nstruct args_expire {\n\t__u32 how;\n};\n\nstruct args_fail {\n\t__u32 token;\n\t__s32 status;\n};\n\nstruct args_in {\n\t__u32 type;\n};\n\nstruct args_out {\n\t__u32 devid;\n\t__u32 magic;\n};\n\nstruct args_ismountpoint {\n\tunion {\n\t\tstruct args_in in;\n\t\tstruct args_out out;\n\t};\n};\n\nstruct args_openmount {\n\t__u32 devid;\n};\n\nstruct args_protosubver {\n\t__u32 sub_version;\n};\n\nstruct args_protover {\n\t__u32 version;\n};\n\nstruct args_ready {\n\t__u32 token;\n};\n\nstruct args_requester {\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct args_setpipefd {\n\t__s32 pipefd;\n};\n\nstruct args_timeout {\n\t__u64 timeout;\n};\n\nstruct arm_smccc_quirk {\n\tint id;\n\tunion {\n\t\tlong unsigned int a6;\n\t} state;\n};\n\nstruct arm_smccc_res {\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n\tlong unsigned int a3;\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct trace_array;\n\nstruct trace_buffer;\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tu64 time_start;\n\tint cpu;\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct usb_dev_state;\n\nstruct pid;\n\nstruct urb;\n\nstruct usb_memory;\n\nstruct async {\n\tstruct list_head asynclist;\n\tstruct usb_dev_state *ps;\n\tstruct pid *pid;\n\tconst struct cred *cred;\n\tunsigned int signr;\n\tunsigned int ifnum;\n\tvoid *userbuffer;\n\tvoid *userurb;\n\tsigval_t userurb_sigval;\n\tstruct urb *urb;\n\tstruct usb_memory *usbm;\n\tunsigned int mem_usage;\n\tint status;\n\tu8 bulk_addr;\n\tu8 bulk_status;\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct ata_acpi_drive {\n\tu32 pio;\n\tu32 dma;\n};\n\nstruct ata_acpi_gtf {\n\tu8 tf[7];\n};\n\nstruct ata_acpi_gtm {\n\tstruct ata_acpi_drive drive[2];\n\tu32 flags;\n};\n\nstruct ata_device;\n\nstruct ata_acpi_hotplug_context {\n\tstruct acpi_hotplug_context hp;\n\tunion {\n\t\tstruct ata_port *ap;\n\t\tstruct ata_device *dev;\n\t} data;\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nstruct ata_cdl {\n\tu8 desc_log_buf[512];\n\tu8 ncq_sense_log_buf[1024];\n};\n\nstruct ata_cpr {\n\tu8 num;\n\tu8 num_storage_elements;\n\tu64 start_lba;\n\tu64 num_lbas;\n};\n\nstruct ata_cpr_log {\n\tu8 nr_cpr;\n\tstruct ata_cpr cpr[0];\n};\n\nstruct ata_dev_quirk_value {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 val;\n};\n\nstruct ata_dev_quirks_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 quirks;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tu64 quirks;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tunion acpi_object *gtf_cache;\n\tunsigned int gtf_filter;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 gp_log_dir[512];\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tstruct ata_cpr_log *cpr_log;\n\tstruct ata_cdl *cdl;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 sector_buf[512];\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst unsigned int *timeouts;\n};\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[16];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tu64 value;\n\tu8 cbl;\n\tu8 spd_limit;\n\tunsigned int xfer_mask;\n\tu64 quirk_on;\n\tu64 quirk_off;\n\tunsigned int pflags_on;\n\tu16 lflags_on;\n\tu16 lflags_off;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tunion {\n\t\tu8 error;\n\t\tu8 feature;\n\t};\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tunion {\n\t\tu8 status;\n\t\tu8 command;\n\t};\n\tu32 auxiliary;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct scsi_cmnd;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tu64 qc_active;\n\tint nr_active_links;\n\tstruct work_struct deferred_qc_work;\n\tstruct ata_queued_cmd *deferred_qc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct delayed_work scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tunsigned int fastdrain_cnt;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tstruct ata_acpi_gtm __acpi_init_gtm;\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nstruct ata_reset_operations {\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tvoid (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tvoid (*qc_ncq_fill_rtf)(struct ata_port *, u64);\n\tint (*cable_detect)(struct ata_port *);\n\tunsigned int (*mode_filter)(struct ata_device *, unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, __le16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tstruct ata_reset_operations reset;\n\tstruct ata_reset_operations pmp_reset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nstruct ata_timing {\n\tshort unsigned int mode;\n\tshort unsigned int setup;\n\tshort unsigned int act8b;\n\tshort unsigned int rec8b;\n\tshort unsigned int cyc8b;\n\tshort unsigned int active;\n\tshort unsigned int recover;\n\tshort unsigned int dmack_hold;\n\tshort unsigned int cycle;\n\tshort unsigned int udma;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ps2dev;\n\ntypedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int);\n\ntypedef void (*ps2_receive_handler_t)(struct ps2dev *, u8);\n\nstruct serio;\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n\tps2_pre_receive_handler_t pre_receive_handler;\n\tps2_receive_handler_t receive_handler;\n};\n\nstruct vivaldi_data {\n\tu32 function_row_physmap[24];\n\tunsigned int num_function_row_keys;\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[8];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tstruct vivaldi_data vdata;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct atmel_trng {\n\tstruct clk *clk;\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tbool has_half_rate;\n};\n\nstruct atmel_trng_data {\n\tbool has_half_rate;\n};\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct audit_aux_data {\n\tstruct audit_aux_data *next;\n\tint type;\n};\n\nstruct audit_cap_data {\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n\tunion {\n\t\tunsigned int fE;\n\t\tkernel_cap_t effective;\n\t};\n\tkernel_cap_t ambient;\n\tkuid_t rootid;\n};\n\nstruct audit_aux_data_bprm_fcaps {\n\tstruct audit_aux_data d;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tstruct audit_cap_data old_pcap;\n\tstruct audit_cap_data new_pcap;\n};\n\nstruct lsm_prop_selinux {\n\tu32 secid;\n};\n\nstruct lsm_prop_smack {};\n\nstruct lsm_prop_apparmor {\n\tstruct aa_label *label;\n};\n\nstruct lsm_prop_bpf {};\n\nstruct lsm_prop {\n\tstruct lsm_prop_selinux selinux;\n\tstruct lsm_prop_smack smack;\n\tstruct lsm_prop_apparmor apparmor;\n\tstruct lsm_prop_bpf bpf;\n};\n\nstruct audit_aux_data_pids {\n\tstruct audit_aux_data d;\n\tpid_t target_pid[16];\n\tkuid_t target_auid[16];\n\tkuid_t target_uid[16];\n\tunsigned int target_sessionid[16];\n\tstruct lsm_prop target_ref[16];\n\tchar target_comm[256];\n\tint pid_count;\n};\n\nstruct audit_stamp {\n\tstruct timespec64 ctime;\n\tunsigned int serial;\n};\n\nstruct audit_context;\n\nstruct audit_buffer {\n\tstruct sk_buff *skb;\n\tstruct sk_buff_head skb_list;\n\tstruct audit_context *ctx;\n\tstruct audit_stamp stamp;\n\tgfp_t gfp_mask;\n};\n\nstruct audit_cache {\n\tconst struct cred *ad_subj_cred;\n\tu64 ktime_ns_expiration[41];\n};\n\nstruct audit_tree;\n\nstruct audit_node {\n\tstruct list_head list;\n\tstruct audit_tree *owner;\n\tunsigned int index;\n};\n\nstruct fsnotify_mark;\n\nstruct audit_chunk {\n\tstruct list_head hash;\n\tlong unsigned int key;\n\tstruct fsnotify_mark *mark;\n\tstruct list_head trees;\n\tint count;\n\tatomic_long_t refs;\n\tstruct callback_head head;\n\tstruct audit_node owners[0];\n};\n\nstruct filename;\n\nstruct audit_names {\n\tstruct list_head list;\n\tstruct filename *name;\n\tint name_len;\n\tbool hidden;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tstruct lsm_prop oprop;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tunsigned char type;\n\tbool should_free;\n};\n\nstruct mq_attr {\n\t__kernel_long_t mq_flags;\n\t__kernel_long_t mq_maxmsg;\n\t__kernel_long_t mq_msgsize;\n\t__kernel_long_t mq_curmsgs;\n\t__kernel_long_t __reserved[4];\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct audit_proctitle {\n\tint len;\n\tchar *value;\n};\n\nstruct audit_tree_refs;\n\nstruct audit_context {\n\tint dummy;\n\tenum {\n\t\tAUDIT_CTX_UNUSED = 0,\n\t\tAUDIT_CTX_SYSCALL = 1,\n\t\tAUDIT_CTX_URING = 2,\n\t} context;\n\tenum audit_state state;\n\tenum audit_state current_state;\n\tstruct audit_stamp stamp;\n\tint major;\n\tint uring_op;\n\tlong unsigned int argv[4];\n\tlong int return_code;\n\tu64 prio;\n\tint return_valid;\n\tstruct audit_names preallocated_names[5];\n\tint name_count;\n\tstruct list_head names_list;\n\tchar *filterkey;\n\tstruct path pwd;\n\tstruct audit_aux_data *aux;\n\tstruct audit_aux_data *aux_pids;\n\tstruct __kernel_sockaddr_storage *sockaddr;\n\tsize_t sockaddr_len;\n\tpid_t ppid;\n\tkuid_t uid;\n\tkuid_t euid;\n\tkuid_t suid;\n\tkuid_t fsuid;\n\tkgid_t gid;\n\tkgid_t egid;\n\tkgid_t sgid;\n\tkgid_t fsgid;\n\tlong unsigned int personality;\n\tint arch;\n\tpid_t target_pid;\n\tkuid_t target_auid;\n\tkuid_t target_uid;\n\tunsigned int target_sessionid;\n\tstruct lsm_prop target_ref;\n\tchar target_comm[16];\n\tstruct audit_tree_refs *trees;\n\tstruct audit_tree_refs *first_trees;\n\tstruct list_head killed_trees;\n\tint tree_count;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tint nargs;\n\t\t\tlong int args[6];\n\t\t} socketcall;\n\t\tstruct {\n\t\t\tkuid_t uid;\n\t\t\tkgid_t gid;\n\t\t\tumode_t mode;\n\t\t\tstruct lsm_prop oprop;\n\t\t\tint has_perm;\n\t\t\tuid_t perm_uid;\n\t\t\tgid_t perm_gid;\n\t\t\tumode_t perm_mode;\n\t\t\tlong unsigned int qbytes;\n\t\t} ipc;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tstruct mq_attr mqstat;\n\t\t} mq_getsetattr;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tint sigev_signo;\n\t\t} mq_notify;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tsize_t msg_len;\n\t\t\tunsigned int msg_prio;\n\t\t\tstruct timespec64 abs_timeout;\n\t\t} mq_sendrecv;\n\t\tstruct {\n\t\t\tint oflag;\n\t\t\tumode_t mode;\n\t\t\tstruct mq_attr attr;\n\t\t} mq_open;\n\t\tstruct {\n\t\t\tpid_t pid;\n\t\t\tstruct audit_cap_data cap;\n\t\t} capset;\n\t\tstruct {\n\t\t\tint fd;\n\t\t\tint flags;\n\t\t} mmap;\n\t\tstruct open_how openat2;\n\t\tstruct {\n\t\t\tint argc;\n\t\t} execve;\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t} module;\n\t\tstruct {\n\t\t\tstruct audit_ntp_data ntp_data;\n\t\t\tstruct timespec64 tk_injoffset;\n\t\t} time;\n\t};\n\tint fds[2];\n\tstruct audit_proctitle proctitle;\n};\n\nstruct audit_ctl_mutex {\n\tstruct mutex lock;\n\tvoid *owner;\n};\n\nstruct audit_field;\n\nstruct audit_watch;\n\nstruct audit_fsnotify_mark;\n\nstruct audit_krule {\n\tu32 pflags;\n\tu32 flags;\n\tu32 listnr;\n\tu32 action;\n\tu32 mask[64];\n\tu32 buflen;\n\tu32 field_count;\n\tchar *filterkey;\n\tstruct audit_field *fields;\n\tstruct audit_field *arch_f;\n\tstruct audit_field *inode_f;\n\tstruct audit_watch *watch;\n\tstruct audit_tree *tree;\n\tstruct audit_fsnotify_mark *exe;\n\tstruct list_head rlist;\n\tstruct list_head list;\n\tu64 prio;\n};\n\nstruct audit_entry {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tstruct audit_krule rule;\n};\n\nstruct audit_features {\n\t__u32 vers;\n\t__u32 mask;\n\t__u32 features;\n\t__u32 lock;\n};\n\nstruct audit_field {\n\tu32 type;\n\tunion {\n\t\tu32 val;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tstruct {\n\t\t\tchar *lsm_str;\n\t\t\tvoid *lsm_rule;\n\t\t};\n\t};\n\tu32 op;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark_connector;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct audit_fsnotify_mark {\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar *path;\n\tstruct fsnotify_mark mark;\n\tstruct audit_krule *rule;\n};\n\nstruct sock;\n\nstruct audit_net {\n\tstruct sock *sk;\n};\n\nstruct audit_netlink_list {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff_head q;\n};\n\nstruct audit_nfcfgop_tab {\n\tenum audit_nfcfgop op;\n\tconst char *s;\n};\n\nstruct audit_parent {\n\tstruct list_head watches;\n\tstruct fsnotify_mark mark;\n};\n\nstruct audit_reply {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff *skb;\n};\n\nstruct audit_rule_data {\n\t__u32 flags;\n\t__u32 action;\n\t__u32 field_count;\n\t__u32 mask[64];\n\t__u32 fields[64];\n\t__u32 values[64];\n\t__u32 fieldflags[64];\n\t__u32 buflen;\n\tchar buf[0];\n};\n\nstruct audit_sig_info {\n\tuid_t uid;\n\tpid_t pid;\n\tchar ctx[0];\n};\n\nstruct audit_status {\n\t__u32 mask;\n\t__u32 enabled;\n\t__u32 failure;\n\t__u32 pid;\n\t__u32 rate_limit;\n\t__u32 backlog_limit;\n\t__u32 lost;\n\t__u32 backlog;\n\tunion {\n\t\t__u32 version;\n\t\t__u32 feature_bitmap;\n\t};\n\t__u32 backlog_wait_time;\n\t__u32 backlog_wait_time_actual;\n};\n\nstruct audit_tree {\n\trefcount_t count;\n\tint goner;\n\tstruct audit_chunk *root;\n\tstruct list_head chunks;\n\tstruct list_head rules;\n\tstruct list_head list;\n\tstruct list_head same_root;\n\tstruct callback_head head;\n\tchar pathname[0];\n};\n\nstruct audit_tree_mark {\n\tstruct fsnotify_mark mark;\n\tstruct audit_chunk *chunk;\n};\n\nstruct audit_tree_refs {\n\tstruct audit_tree_refs *next;\n\tstruct audit_chunk *c[31];\n};\n\nstruct audit_tty_status {\n\t__u32 enabled;\n\t__u32 log_passwd;\n};\n\nstruct audit_watch {\n\trefcount_t count;\n\tdev_t dev;\n\tchar *path;\n\tlong unsigned int ino;\n\tstruct audit_parent *parent;\n\tstruct list_head wlist;\n\tstruct list_head rules;\n};\n\nstruct auditd_connection {\n\tstruct pid *pid;\n\tu32 portid;\n\tstruct net *net;\n\tstruct callback_head rcu;\n};\n\nstruct auth_cred {\n\tconst struct cred *cred;\n\tconst char *principal;\n};\n\nstruct auth_ops;\n\nstruct auth_domain {\n\tstruct kref ref;\n\tstruct hlist_node hash;\n\tchar *name;\n\tstruct auth_ops *flavour;\n\tstruct callback_head callback_head;\n};\n\nstruct svc_rqst;\n\nstruct auth_ops {\n\tchar *name;\n\tstruct module *owner;\n\tint flavour;\n\tenum svc_auth_status (*accept)(struct svc_rqst *);\n\tint (*release)(struct svc_rqst *);\n\tvoid (*domain_release)(struct auth_domain *);\n\tenum svc_auth_status (*set_client)(struct svc_rqst *);\n\trpc_authflavor_t (*pseudoflavor)(struct svc_rqst *);\n};\n\nstruct auto_mode_param {\n\tint qp_type;\n};\n\nstruct autofs_dev_ioctl {\n\t__u32 ver_major;\n\t__u32 ver_minor;\n\t__u32 size;\n\t__s32 ioctlfd;\n\tunion {\n\t\tstruct args_protover protover;\n\t\tstruct args_protosubver protosubver;\n\t\tstruct args_openmount openmount;\n\t\tstruct args_ready ready;\n\t\tstruct args_fail fail;\n\t\tstruct args_setpipefd setpipefd;\n\t\tstruct args_timeout timeout;\n\t\tstruct args_requester requester;\n\t\tstruct args_expire expire;\n\t\tstruct args_askumount askumount;\n\t\tstruct args_ismountpoint ismountpoint;\n\t};\n\tchar path[0];\n};\n\nstruct autofs_fs_context {\n\tkuid_t uid;\n\tkgid_t gid;\n\tint pgrp;\n\tbool pgrp_set;\n};\n\nstruct autofs_sb_info;\n\nstruct autofs_info {\n\tstruct dentry *dentry;\n\tint flags;\n\tstruct completion expire_complete;\n\tstruct list_head active;\n\tstruct list_head expiring;\n\tstruct autofs_sb_info *sbi;\n\tlong unsigned int exp_timeout;\n\tlong unsigned int last_used;\n\tint count;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_packet_hdr {\n\tint proto_version;\n\tint type;\n};\n\nstruct autofs_packet_expire {\n\tstruct autofs_packet_hdr hdr;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_expire_multi {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_missing {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nunion autofs_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_packet_missing missing;\n\tstruct autofs_packet_expire expire;\n\tstruct autofs_packet_expire_multi expire_multi;\n};\n\nstruct super_block;\n\nstruct autofs_wait_queue;\n\nstruct autofs_sb_info {\n\tu32 magic;\n\tint pipefd;\n\tstruct file *pipe;\n\tstruct pid *oz_pgrp;\n\tu64 mnt_ns_id;\n\tint version;\n\tint sub_version;\n\tint min_proto;\n\tint max_proto;\n\tunsigned int flags;\n\tlong unsigned int exp_timeout;\n\tunsigned int type;\n\tstruct super_block *sb;\n\tstruct mutex wq_mutex;\n\tstruct mutex pipe_mutex;\n\tspinlock_t fs_lock;\n\tstruct autofs_wait_queue *queues;\n\tspinlock_t lookup_lock;\n\tstruct list_head active_list;\n\tstruct list_head expiring_list;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_v5_packet {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\t__u32 dev;\n\t__u64 ino;\n\t__u32 uid;\n\t__u32 gid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 len;\n\tchar name[256];\n};\n\ntypedef struct autofs_v5_packet autofs_packet_expire_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_expire_indirect_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_indirect_t;\n\nunion autofs_v5_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_v5_packet v5_packet;\n\tautofs_packet_missing_indirect_t missing_indirect;\n\tautofs_packet_expire_indirect_t expire_indirect;\n\tautofs_packet_missing_direct_t missing_direct;\n\tautofs_packet_expire_direct_t expire_direct;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n};\n\nstruct autofs_wait_queue {\n\twait_queue_head_t queue;\n\tstruct autofs_wait_queue *next;\n\tautofs_wqt_t wait_queue_token;\n\tstruct qstr name;\n\tu32 offset;\n\tu32 dev;\n\tu64 ino;\n\tkuid_t uid;\n\tkgid_t gid;\n\tpid_t pid;\n\tpid_t tgid;\n\tint status;\n\tunsigned int wait_ctr;\n};\n\nstruct auxiliary_device {\n\tstruct device dev;\n\tconst char *name;\n\tu32 id;\n\tstruct {\n\t\tstruct xarray irqs;\n\t\tstruct mutex lock;\n\t\tbool irq_dir_exists;\n\t} sysfs;\n};\n\nstruct auxiliary_device_id {\n\tchar name[40];\n\tkernel_ulong_t driver_data;\n};\n\nstruct auxiliary_driver {\n\tint (*probe)(struct auxiliary_device *, const struct auxiliary_device_id *);\n\tvoid (*remove)(struct auxiliary_device *);\n\tvoid (*shutdown)(struct auxiliary_device *);\n\tint (*suspend)(struct auxiliary_device *, pm_message_t);\n\tint (*resume)(struct auxiliary_device *);\n\tconst char *name;\n\tstruct device_driver driver;\n\tconst struct auxiliary_device_id *id_table;\n};\n\nstruct auxiliary_irq_info {\n\tstruct device_attribute sysfs_attr;\n\tchar name[11];\n};\n\nstruct av_decision {\n\tu32 allowed;\n\tu32 auditallow;\n\tu32 auditdeny;\n\tu32 seqno;\n\tu32 flags;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct avc_cache {\n\tstruct hlist_head slots[512];\n\tspinlock_t slots_lock[512];\n\tatomic_t lru_hint;\n\tatomic_t active_nodes;\n\tu32 latest_notif;\n};\n\nstruct avc_cache_stats {\n\tunsigned int lookups;\n\tunsigned int misses;\n\tunsigned int allocations;\n\tunsigned int reclaims;\n\tunsigned int frees;\n};\n\nstruct avc_callback_node {\n\tint (*callback)(u32);\n\tu32 events;\n\tstruct avc_callback_node *next;\n};\n\nstruct avc_xperms_node;\n\nstruct avc_entry {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tstruct av_decision avd;\n\tstruct avc_xperms_node *xp_node;\n};\n\nstruct avc_node {\n\tstruct avc_entry ae;\n\tstruct hlist_node list;\n\tstruct callback_head rhead;\n};\n\nstruct extended_perms_data;\n\nstruct extended_perms_decision {\n\tu8 used;\n\tu8 driver;\n\tu8 base_perm;\n\tstruct extended_perms_data *allowed;\n\tstruct extended_perms_data *auditallow;\n\tstruct extended_perms_data *dontaudit;\n};\n\nstruct avc_xperms_decision_node {\n\tstruct extended_perms_decision xpd;\n\tstruct list_head xpd_list;\n};\n\nstruct extended_perms_data {\n\tu32 p[8];\n};\n\nstruct extended_perms {\n\tu16 len;\n\tu8 base_perms;\n\tstruct extended_perms_data drivers;\n};\n\nstruct avc_xperms_node {\n\tstruct extended_perms xp;\n\tstruct list_head xpd_head;\n};\n\nstruct avdc_entry {\n\tu32 isid;\n\tu32 allowed;\n\tu32 audited;\n\tbool permissive;\n};\n\nstruct avtab_node;\n\nstruct avtab {\n\tstruct avtab_node **htable;\n\tu32 nel;\n\tu32 nslot;\n\tu32 mask;\n};\n\nstruct avtab_extended_perms;\n\nstruct avtab_datum {\n\tunion {\n\t\tu32 data;\n\t\tstruct avtab_extended_perms *xperms;\n\t} u;\n};\n\nstruct avtab_extended_perms {\n\tu8 specified;\n\tu8 driver;\n\tstruct extended_perms_data perms;\n};\n\nstruct avtab_key {\n\tu16 source_type;\n\tu16 target_type;\n\tu16 target_class;\n\tu16 specified;\n};\n\nstruct avtab_node {\n\tstruct avtab_key key;\n\tstruct avtab_datum datum;\n\tstruct avtab_node *next;\n};\n\nstruct dma_device;\n\nstruct dma_chan_dev;\n\nstruct dma_chan_percpu;\n\nstruct dma_router;\n\nstruct dma_chan {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct virt_dma_desc;\n\nstruct virt_dma_chan {\n\tstruct dma_chan chan;\n\tstruct tasklet_struct task;\n\tvoid (*desc_free)(struct virt_dma_desc *);\n\tspinlock_t lock;\n\tstruct list_head desc_allocated;\n\tstruct list_head desc_submitted;\n\tstruct list_head desc_issued;\n\tstruct list_head desc_completed;\n\tstruct list_head desc_terminated;\n\tstruct virt_dma_desc *cyclic;\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n};\n\nstruct axi_dma_chip;\n\nstruct dma_pool;\n\nstruct axi_dma_desc;\n\nstruct axi_dma_chan {\n\tstruct axi_dma_chip *chip;\n\tvoid *chan_regs;\n\tu8 id;\n\tu8 hw_handshake_num;\n\tatomic_t descs_allocated;\n\tstruct dma_pool *desc_pool;\n\tstruct virt_dma_chan vc;\n\tstruct axi_dma_desc *desc;\n\tstruct dma_slave_config config;\n\tenum dma_transfer_direction direction;\n\tbool cyclic;\n\tbool is_paused;\n};\n\nstruct axi_dma_chan_config {\n\tu8 dst_multblk_type;\n\tu8 src_multblk_type;\n\tu8 dst_per;\n\tu8 src_per;\n\tu8 tt_fc;\n\tu8 prior;\n\tu8 hs_sel_dst;\n\tu8 hs_sel_src;\n};\n\nstruct dw_axi_dma;\n\nstruct axi_dma_chip {\n\tstruct device *dev;\n\tint irq[32];\n\tvoid *regs;\n\tvoid *apb_regs;\n\tstruct clk *core_clk;\n\tstruct clk *cfgr_clk;\n\tstruct dw_axi_dma *dw;\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nstruct dmaengine_result;\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dmaengine_unmap_data;\n\nstruct dma_descriptor_metadata_ops;\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\nstruct virt_dma_desc {\n\tstruct dma_async_tx_descriptor tx;\n\tstruct dmaengine_result tx_result;\n\tstruct list_head node;\n};\n\nstruct axi_dma_hw_desc;\n\nstruct axi_dma_desc {\n\tstruct axi_dma_hw_desc *hw_desc;\n\tstruct virt_dma_desc vd;\n\tstruct axi_dma_chan *chan;\n\tu32 completed_blocks;\n\tu32 length;\n\tu32 period_len;\n\tu32 nr_hw_descs;\n};\n\nstruct axi_dma_lli;\n\nstruct axi_dma_hw_desc {\n\tstruct axi_dma_lli *lli;\n\tdma_addr_t llp;\n\tu32 len;\n};\n\nstruct axi_dma_lli {\n\t__le64 sar;\n\t__le64 dar;\n\t__le32 block_ts_lo;\n\t__le32 block_ts_hi;\n\t__le64 llp;\n\t__le32 ctl_lo;\n\t__le32 ctl_hi;\n\t__le32 sstat;\n\t__le32 dstat;\n\t__le32 status_lo;\n\t__le32 status_hi;\n\t__le32 reserved_lo;\n\t__le32 reserved_hi;\n};\n\nstruct regmap;\n\nstruct regmap_irq_chip_data;\n\nstruct mfd_cell;\n\nstruct regmap_config;\n\nstruct regmap_irq_chip;\n\nstruct axp20x_dev {\n\tstruct device *dev;\n\tint irq;\n\tlong unsigned int irq_flags;\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip_data *regmap_irqc;\n\tenum axp20x_variants variant;\n\tint nr_cells;\n\tconst struct mfd_cell *cells;\n\tconst struct regmap_config *regmap_cfg;\n\tconst struct regmap_irq_chip *regmap_irq_chip;\n};\n\nstruct backing_aio {\n\tstruct kiocb iocb;\n\trefcount_t ref;\n\tstruct kiocb *orig_iocb;\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n\tstruct work_struct work;\n\tlong int res;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct backing_dev_info;\n\nstruct cgroup_subsys_state;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n\tstruct percpu_ref refcnt;\n\tstruct fprop_local_percpu memcg_completions;\n\tstruct cgroup_subsys_state *memcg_css;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct list_head memcg_node;\n\tstruct list_head blkcg_node;\n\tstruct list_head b_attached;\n\tstruct list_head offline_node;\n\tstruct work_struct switch_work;\n\tstruct llist_head switch_wbs_ctxs;\n\tunion {\n\t\tstruct work_struct release_work;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\tstruct xarray cgwb_tree;\n\tstruct mutex cgwb_release_mutex;\n\tstruct rw_semaphore wb_switch_rwsem;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tloff_t prev_pos;\n};\n\nstruct fown_struct;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\tvoid *f_security;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backing_file_ctx {\n\tconst struct cred *cred;\n\tvoid (*accessed)(struct file *);\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n};\n\nstruct badrange {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct badrange_entry {\n\tu64 start;\n\tu64 length;\n\tstruct list_head list;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct balloon_dev_info {\n\tlong unsigned int isolated_pages;\n\tstruct list_head pages;\n\tint (*migratepage)(struct balloon_dev_info *, struct page *, struct page *, enum migrate_mode);\n\tbool adjust_managed_page_count;\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct local_lock {};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct bd_holder_disk {\n\tstruct list_head list;\n\tstruct kobject *holder_dir;\n\tint refcnt;\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tvoid *bd_security;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tvoid *i_security;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct bdi_writeback *i_wb;\n\tint i_wb_frn_winner;\n\tu16 i_wb_frn_avg_time;\n\tu16 i_wb_frn_history;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct bfq_sched_data;\n\nstruct bfq_queue;\n\nstruct bfq_entity {\n\tstruct rb_node rb_node;\n\tbool on_st_or_in_serv;\n\tu64 start;\n\tu64 finish;\n\tstruct rb_root *tree;\n\tu64 min_start;\n\tint service;\n\tint budget;\n\tint allocated;\n\tint dev_weight;\n\tint weight;\n\tint new_weight;\n\tint orig_weight;\n\tstruct bfq_entity *parent;\n\tstruct bfq_sched_data *my_sched_data;\n\tstruct bfq_sched_data *sched_data;\n\tint prio_changed;\n\tbool in_groups_with_pending_reqs;\n\tstruct bfq_queue *last_bfqq_created;\n};\n\nstruct bfq_ttime {\n\tu64 last_end_request;\n\tu64 ttime_total;\n\tlong unsigned int ttime_samples;\n\tu64 ttime_mean;\n};\n\nstruct bfq_data;\n\nstruct request;\n\nstruct bfq_weight_counter;\n\nstruct bfq_io_cq;\n\nstruct bfq_queue {\n\tint ref;\n\tint stable_ref;\n\tstruct bfq_data *bfqd;\n\tshort unsigned int ioprio;\n\tshort unsigned int ioprio_class;\n\tshort unsigned int new_ioprio;\n\tshort unsigned int new_ioprio_class;\n\tu64 last_serv_time_ns;\n\tunsigned int inject_limit;\n\tlong unsigned int decrease_time_jif;\n\tstruct bfq_queue *new_bfqq;\n\tstruct rb_node pos_node;\n\tstruct rb_root *pos_root;\n\tstruct rb_root sort_list;\n\tstruct request *next_rq;\n\tint queued[2];\n\tint meta_pending;\n\tstruct list_head fifo;\n\tstruct bfq_entity entity;\n\tstruct bfq_weight_counter *weight_counter;\n\tint max_budget;\n\tlong unsigned int budget_timeout;\n\tint dispatched;\n\tlong unsigned int flags;\n\tstruct list_head bfqq_list;\n\tstruct bfq_ttime ttime;\n\tu64 io_start_time;\n\tu64 tot_idle_time;\n\tu32 seek_history;\n\tstruct hlist_node burst_list_node;\n\tsector_t last_request_pos;\n\tunsigned int requests_within_timer;\n\tpid_t pid;\n\tstruct bfq_io_cq *bic;\n\tlong unsigned int wr_cur_max_time;\n\tlong unsigned int soft_rt_next_start;\n\tlong unsigned int last_wr_start_finish;\n\tunsigned int wr_coeff;\n\tlong unsigned int last_idle_bklogged;\n\tlong unsigned int service_from_backlogged;\n\tlong unsigned int service_from_wr;\n\tlong unsigned int wr_start_at_switch_to_srt;\n\tlong unsigned int split_time;\n\tlong unsigned int first_IO_time;\n\tlong unsigned int creation_time;\n\tstruct bfq_queue *waker_bfqq;\n\tstruct bfq_queue *tentative_waker_bfqq;\n\tunsigned int num_waker_detections;\n\tu64 waker_detection_started;\n\tstruct hlist_node woken_list_node;\n\tstruct hlist_head woken_list;\n\tunsigned int actuator_idx;\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct bfq_group;\n\nstruct bfq_data {\n\tstruct request_queue *queue;\n\tstruct list_head dispatch;\n\tstruct bfq_group *root_group;\n\tstruct rb_root_cached queue_weights_tree;\n\tunsigned int num_groups_with_pending_reqs;\n\tunsigned int busy_queues[3];\n\tint wr_busy_queues;\n\tint queued;\n\tint tot_rq_in_driver;\n\tint rq_in_driver[8];\n\tbool nonrot_with_queueing;\n\tint max_rq_in_driver;\n\tint hw_tag_samples;\n\tint hw_tag;\n\tint budgets_assigned;\n\tstruct hrtimer idle_slice_timer;\n\tstruct bfq_queue *in_service_queue;\n\tsector_t last_position;\n\tsector_t in_serv_last_pos;\n\tu64 last_completion;\n\tstruct bfq_queue *last_completed_rq_bfqq;\n\tstruct bfq_queue *last_bfqq_created;\n\tu64 last_empty_occupied_ns;\n\tbool wait_dispatch;\n\tstruct request *waited_rq;\n\tbool rqs_injected;\n\tu64 first_dispatch;\n\tu64 last_dispatch;\n\tktime_t last_budget_start;\n\tktime_t last_idling_start;\n\tlong unsigned int last_idling_start_jiffies;\n\tint peak_rate_samples;\n\tu32 sequential_samples;\n\tu64 tot_sectors_dispatched;\n\tu32 last_rq_max_size;\n\tu64 delta_from_first;\n\tu32 peak_rate;\n\tint bfq_max_budget;\n\tstruct list_head active_list[8];\n\tstruct list_head idle_list;\n\tu64 bfq_fifo_expire[2];\n\tunsigned int bfq_back_penalty;\n\tunsigned int bfq_back_max;\n\tu32 bfq_slice_idle;\n\tint bfq_user_max_budget;\n\tunsigned int bfq_timeout;\n\tbool strict_guarantees;\n\tlong unsigned int last_ins_in_burst;\n\tlong unsigned int bfq_burst_interval;\n\tint burst_size;\n\tstruct bfq_entity *burst_parent_entity;\n\tlong unsigned int bfq_large_burst_thresh;\n\tbool large_burst;\n\tstruct hlist_head burst_list;\n\tbool low_latency;\n\tunsigned int bfq_wr_coeff;\n\tunsigned int bfq_wr_rt_max_time;\n\tunsigned int bfq_wr_min_idle_time;\n\tlong unsigned int bfq_wr_min_inter_arr_async;\n\tunsigned int bfq_wr_max_softrt_rate;\n\tu64 rate_dur_prod;\n\tstruct bfq_queue oom_bfqq;\n\tspinlock_t lock;\n\tstruct bfq_io_cq *bio_bic;\n\tstruct bfq_queue *bio_bfqq;\n\tunsigned int async_depths[4];\n\tunsigned int num_actuators;\n\tsector_t sector[8];\n\tsector_t nr_sectors[8];\n\tstruct blk_independent_access_range ia_ranges[8];\n\tunsigned int actuator_load_threshold;\n};\n\nstruct blkcg_gq;\n\nstruct blkg_policy_data {\n\tstruct blkcg_gq *blkg;\n\tint plid;\n\tbool online;\n};\n\nstruct bfq_service_tree {\n\tstruct rb_root active;\n\tstruct rb_root idle;\n\tstruct bfq_entity *first_idle;\n\tstruct bfq_entity *last_idle;\n\tu64 vtime;\n\tlong unsigned int wsum;\n};\n\nstruct bfq_sched_data {\n\tstruct bfq_entity *in_service_entity;\n\tstruct bfq_entity *next_in_service;\n\tstruct bfq_service_tree service_tree[3];\n\tlong unsigned int bfq_class_idle_last_service;\n};\n\nstruct blkg_rwstat {\n\tstruct percpu_counter cpu_cnt[5];\n\tatomic64_t aux_cnt[5];\n};\n\nstruct bfqg_stats {\n\tstruct blkg_rwstat bytes;\n\tstruct blkg_rwstat ios;\n};\n\nstruct bfq_group {\n\tstruct blkg_policy_data pd;\n\trefcount_t ref;\n\tstruct bfq_entity entity;\n\tstruct bfq_sched_data sched_data;\n\tstruct bfq_data *bfqd;\n\tstruct bfq_queue *async_bfqq[128];\n\tstruct bfq_queue *async_idle_bfqq[8];\n\tstruct bfq_entity *my_entity;\n\tint active_entities;\n\tint num_queues_with_pending_reqs;\n\tstruct rb_root rq_pos_tree;\n\tstruct bfqg_stats stats;\n};\n\nstruct blkcg;\n\nstruct blkcg_policy_data {\n\tstruct blkcg *blkcg;\n\tint plid;\n};\n\nstruct bfq_group_data {\n\tstruct blkcg_policy_data pd;\n\tunsigned int weight;\n};\n\nstruct io_context;\n\nstruct kmem_cache;\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct bfq_iocq_bfqq_data {\n\tbool saved_has_short_ttime;\n\tbool saved_IO_bound;\n\tbool saved_in_large_burst;\n\tbool was_in_burst_list;\n\tunsigned int saved_weight;\n\tu64 saved_io_start_time;\n\tu64 saved_tot_idle_time;\n\tlong unsigned int saved_wr_coeff;\n\tlong unsigned int saved_last_wr_start_finish;\n\tlong unsigned int saved_service_from_wr;\n\tlong unsigned int saved_wr_start_at_switch_to_srt;\n\tstruct bfq_ttime saved_ttime;\n\tunsigned int saved_wr_cur_max_time;\n\tunsigned int saved_inject_limit;\n\tlong unsigned int saved_decrease_time_jif;\n\tu64 saved_last_serv_time_ns;\n\tstruct bfq_queue *stable_merge_bfqq;\n\tbool stably_merged;\n};\n\nstruct bfq_io_cq {\n\tstruct io_cq icq;\n\tstruct bfq_queue *bfqq[16];\n\tint ioprio;\n\tuint64_t blkcg_serial_nr;\n\tstruct bfq_iocq_bfqq_data bfqq_data[8];\n\tunsigned int requests;\n};\n\nstruct bfq_weight_counter {\n\tunsigned int weight;\n\tunsigned int num_active;\n\tstruct rb_node weights_node;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n} __attribute__((packed));\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tstruct blkcg_gq *bi_blkg;\n\tu64 issue_time_ns;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tu64 bc_dun[4];\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec;\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct fsverity_info;\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct fsverity_info *vi;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bl_dev_msg {\n\tint32_t status;\n\tuint32_t major;\n\tuint32_t minor;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 64;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 64;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_file;\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct cgroup_subsys;\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n};\n\nstruct blkcg {\n\tstruct cgroup_subsys_state css;\n\tspinlock_t lock;\n\trefcount_t online_pin;\n\tatomic_t congestion_count;\n\tstruct xarray blkg_tree;\n\tstruct blkcg_gq *blkg_hint;\n\tstruct hlist_head blkg_list;\n\tstruct blkcg_policy_data *cpd[6];\n\tstruct list_head all_blkcgs_node;\n\tstruct llist_head *lhead;\n\tstruct list_head cgwb_list;\n};\n\nstruct blkg_iostat {\n\tu64 bytes[3];\n\tu64 ios[3];\n};\n\nstruct blkg_iostat_set {\n\tstruct u64_stats_sync sync;\n\tstruct blkcg_gq *blkg;\n\tstruct llist_node lnode;\n\tint lqueued;\n\tstruct blkg_iostat cur;\n\tstruct blkg_iostat last;\n};\n\nstruct blkcg_gq {\n\tstruct request_queue *q;\n\tstruct list_head q_node;\n\tstruct hlist_node blkcg_node;\n\tstruct blkcg *blkcg;\n\tstruct blkcg_gq *parent;\n\tstruct percpu_ref refcnt;\n\tbool online;\n\tstruct blkg_iostat_set *iostat_cpu;\n\tstruct blkg_iostat_set iostat;\n\tstruct blkg_policy_data *pd[6];\n\tspinlock_t async_bio_lock;\n\tstruct bio_list async_bios;\n\tunion {\n\t\tstruct work_struct async_bio_work;\n\t\tstruct work_struct free_work;\n\t};\n\tatomic_t use_delay;\n\tatomic64_t delay_nsec;\n\tatomic64_t delay_start;\n\tu64 last_delay;\n\tint last_use;\n\tstruct callback_head callback_head;\n};\n\ntypedef struct blkcg_policy_data *blkcg_pol_alloc_cpd_fn(gfp_t);\n\ntypedef void blkcg_pol_free_cpd_fn(struct blkcg_policy_data *);\n\ntypedef struct blkg_policy_data *blkcg_pol_alloc_pd_fn(struct gendisk *, struct blkcg *, gfp_t);\n\ntypedef void blkcg_pol_init_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_online_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_offline_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_free_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_reset_pd_stats_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_stat_pd_fn(struct blkg_policy_data *, struct seq_file *);\n\nstruct cftype;\n\nstruct blkcg_policy {\n\tint plid;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tblkcg_pol_alloc_cpd_fn *cpd_alloc_fn;\n\tblkcg_pol_free_cpd_fn *cpd_free_fn;\n\tblkcg_pol_alloc_pd_fn *pd_alloc_fn;\n\tblkcg_pol_init_pd_fn *pd_init_fn;\n\tblkcg_pol_online_pd_fn *pd_online_fn;\n\tblkcg_pol_offline_pd_fn *pd_offline_fn;\n\tblkcg_pol_free_pd_fn *pd_free_fn;\n\tblkcg_pol_reset_pd_stats_fn *pd_reset_stats_fn;\n\tblkcg_pol_stat_pd_fn *pd_stat_fn;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bio bio;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blkg_conf_ctx {\n\tchar *input;\n\tchar *body;\n\tstruct block_device *bdev;\n\tstruct blkcg_gq *blkg;\n};\n\nstruct blkg_rwstat_sample {\n\tu64 cnt[5];\n};\n\nstruct blkpg_compat_ioctl_arg {\n\tcompat_int_t op;\n\tcompat_int_t flags;\n\tcompat_int_t datalen;\n\tcompat_uptr_t data;\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[128];\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct spi_board_info {\n\tchar modalias[32];\n\tconst void *platform_data;\n\tconst struct software_node *swnode;\n\tvoid *controller_data;\n\tint irq;\n\tu32 max_speed_hz;\n\tu16 bus_num;\n\tu16 chip_select;\n\tu32 mode;\n};\n\nstruct boardinfo {\n\tstruct list_head list;\n\tstruct spi_board_info board_info;\n};\n\nstruct boot_triggers {\n\tconst char *event;\n\tchar *trigger;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct obj_cgroup;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tvoid *security;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tstruct obj_cgroup *objcg;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n};\n\nstruct range_tree {\n\tstruct rb_root_cached it_root;\n\tstruct rb_root_cached range_size_root;\n};\n\ntypedef struct qspinlock rqspinlock_t;\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct vm_struct;\n\nstruct bpf_arena {\n\tstruct bpf_map map;\n\tu64 user_vm_start;\n\tu64 user_vm_end;\n\tstruct vm_struct *kern_vm;\n\tstruct range_tree rt;\n\trqspinlock_t spinlock;\n\tstruct list_head vma_list;\n\tstruct mutex lock;\n\tstruct irq_work free_irq;\n\tstruct work_struct free_work;\n\tstruct llist_head free_spans;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct bpf_prog;\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 0;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_cgroup_dev_ctx {\n\t__u32 access_type;\n\t__u32 major;\n\t__u32 minor;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n};\n\nstruct bpf_cgroup_link {\n\tstruct bpf_link link;\n\tstruct cgroup *cgroup;\n};\n\nstruct bpf_cgroup_storage_key {\n\t__u64 cgroup_inode_id;\n\t__u32 attach_type;\n};\n\nstruct bpf_storage_buffer;\n\nstruct bpf_cgroup_storage_map;\n\nstruct bpf_cgroup_storage {\n\tunion {\n\t\tstruct bpf_storage_buffer *buf;\n\t\tvoid *percpu_buf;\n\t};\n\tstruct bpf_cgroup_storage_map *map;\n\tstruct bpf_cgroup_storage_key key;\n\tstruct list_head list_map;\n\tstruct list_head list_cg;\n\tstruct rb_node node;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_cgroup_storage_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tstruct rb_root root;\n\tstruct list_head list;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct skb_ext;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tlong unsigned int _nfct;\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\t__u8 active_extensions;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 ipvs_property: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 ipvs_property: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tstruct skb_ext *extensions;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_rxq_info;\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t\tu64 frame_sz_flags_init;\n\t};\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct sock_cgroup_data {\n\tstruct cgroup *cgroup;\n\tu32 classid;\n\tu16 prioidx;\n};\n\nstruct dst_entry;\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct socket;\n\nstruct mem_cgroup;\n\nstruct xfrm_policy;\n\nstruct sock_reuseport;\n\nstruct bpf_local_storage;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\tstruct mem_cgroup *sk_memcg;\n\tstruct xfrm_policy *sk_policy[2];\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tnetdev_features_t sk_route_caps;\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tktime_t sk_stamp;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tvoid *sk_security;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\nstruct user_regs_struct {\n\tlong unsigned int pc;\n\tlong unsigned int ra;\n\tlong unsigned int sp;\n\tlong unsigned int gp;\n\tlong unsigned int tp;\n\tlong unsigned int t0;\n\tlong unsigned int t1;\n\tlong unsigned int t2;\n\tlong unsigned int s0;\n\tlong unsigned int s1;\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n\tlong unsigned int a3;\n\tlong unsigned int a4;\n\tlong unsigned int a5;\n\tlong unsigned int a6;\n\tlong unsigned int a7;\n\tlong unsigned int s2;\n\tlong unsigned int s3;\n\tlong unsigned int s4;\n\tlong unsigned int s5;\n\tlong unsigned int s6;\n\tlong unsigned int s7;\n\tlong unsigned int s8;\n\tlong unsigned int s9;\n\tlong unsigned int s10;\n\tlong unsigned int s11;\n\tlong unsigned int t3;\n\tlong unsigned int t4;\n\tlong unsigned int t5;\n\tlong unsigned int t6;\n};\n\ntypedef struct user_regs_struct bpf_user_pt_regs_t;\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_sample_data;\n\nstruct perf_event;\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nstruct bpf_sysctl {\n\t__u32 write;\n\t__u32 file_pos;\n};\n\nstruct ctl_table_header;\n\nstruct ctl_table;\n\nstruct bpf_sysctl_kern {\n\tstruct ctl_table_header *head;\n\tconst struct ctl_table *table;\n\tvoid *cur_val;\n\tsize_t cur_len;\n\tvoid *new_val;\n\tsize_t new_len;\n\tint new_updated;\n\tint write;\n\tloff_t *ppos;\n\tu64 tmp_reg;\n};\n\nstruct bpf_sockopt {\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *optval;\n\t};\n\tunion {\n\t\tvoid *optval_end;\n\t};\n\t__s32 level;\n\t__s32 optname;\n\t__s32 optlen;\n\t__s32 retval;\n};\n\nstruct bpf_sockopt_kern {\n\tstruct sock *sk;\n\tu8 *optval;\n\tu8 *optval_end;\n\ts32 level;\n\ts32 optname;\n\ts32 optlen;\n\tstruct task_struct *current_task;\n\tu64 tmp_reg;\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_CGROUP_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_CGROUP_SKB_kern;\n\tstruct bpf_sock BPF_PROG_TYPE_CGROUP_SOCK_prog;\n\tstruct sock BPF_PROG_TYPE_CGROUP_SOCK_kern;\n\tstruct bpf_sock_addr BPF_PROG_TYPE_CGROUP_SOCK_ADDR_prog;\n\tstruct bpf_sock_addr_kern BPF_PROG_TYPE_CGROUP_SOCK_ADDR_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_prog;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_kern;\n\tstruct bpf_sysctl BPF_PROG_TYPE_CGROUP_SYSCTL_prog;\n\tstruct bpf_sysctl_kern BPF_PROG_TYPE_CGROUP_SYSCTL_kern;\n\tstruct bpf_sockopt BPF_PROG_TYPE_CGROUP_SOCKOPT_prog;\n\tstruct bpf_sockopt_kern BPF_PROG_TYPE_CGROUP_SOCKOPT_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_prog;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_kern;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n};\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n};\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 0;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct dma_buf;\n\nstruct bpf_iter__dmabuf {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct dma_buf *dmabuf;\n\t};\n};\n\nstruct fib6_info;\n\nstruct bpf_iter__ipv6_route {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct fib6_info *rt;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 0;\n\tint bucket;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n};\n\nstruct bpf_iter_dmabuf {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_dmabuf_kern {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 0;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct mm_struct;\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct key;\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n};\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tatomic64_t revision;\n\tu32 count;\n};\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\ntypedef unsigned int nf_hookfn(void *, struct sk_buff *, const struct nf_hook_state *);\n\nstruct nf_hook_ops {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tnf_hookfn *hook;\n\tstruct net_device *dev;\n\tvoid *priv;\n\tu8 pf;\n\tenum nf_hook_ops_type hook_ops_type: 8;\n\tunsigned int hooknum;\n\tint priority;\n};\n\nstruct nf_defrag_hook;\n\nstruct bpf_nf_link {\n\tstruct bpf_link link;\n\tstruct nf_hook_ops hook_ops;\n\tnetns_tracker ns_tracker;\n\tstruct net *net;\n\tu32 dead;\n\tconst struct nf_defrag_hook *defrag_hook;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_perf_link {\n\tstruct bpf_link link;\n\tstruct file *perf_file;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tvoid *security;\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_list {\n\tstruct hlist_node node;\n\tstruct bpf_prog *prog;\n\tstruct bpf_cgroup_link *link;\n\tstruct bpf_cgroup_storage *storage[2];\n\tu32 flags;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct tracepoint;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 64;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\trqspinlock_t spinlock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t busy;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int consumer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct bpf_security_struct {\n\tu32 sid;\n\tu32 perms;\n\tu32 grantor_sid;\n};\n\nstruct bpf_session_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tbool is_return;\n\tvoid *data;\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_sockopt_buf {\n\tu8 data[32];\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nstruct stack_map_bucket;\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_storage_buffer {\n\tstruct callback_head rcu;\n\tchar data[0];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_dummy_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_ext_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n\tvoid *security;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n};\n\nunion perf_sample_weight {\n\t__u64 full;\n\tstruct {\n\t\t__u32 var1_dw;\n\t\t__u16 var2_w;\n\t\t__u16 var3_w;\n\t};\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_op: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_blk: 3;\n\t\t__u64 mem_hops: 3;\n\t\t__u64 mem_region: 5;\n\t\t__u64 mem_rsvd: 13;\n\t};\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n};\n\nstruct perf_callchain_entry;\n\nstruct perf_raw_record;\n\nstruct perf_branch_stack;\n\nstruct perf_sample_data {\n\tu64 sample_flags;\n\tu64 period;\n\tu64 dyn_size;\n\tu64 type;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tu64 ip;\n\tstruct perf_callchain_entry *callchain;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 *br_stack_cntr;\n\tunion perf_sample_weight weight;\n\tunion perf_mem_data_src data_src;\n\tu64 txn;\n\tstruct perf_regs regs_user;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 stream_id;\n\tu64 cgroup;\n\tu64 addr;\n\tu64 phys_addr;\n\tu64 data_page_size;\n\tu64 code_page_size;\n\tu64 aux_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[38];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *, __u64 *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *, __u64 *);\n\tbool (*filter)(struct uprobe_consumer *, struct mm_struct *);\n\tstruct list_head cons_node;\n\t__u64 id;\n};\n\nstruct bpf_uprobe_multi_link;\n\nstruct uprobe;\n\nstruct bpf_uprobe {\n\tstruct bpf_uprobe_multi_link *link;\n\tloff_t offset;\n\tlong unsigned int ref_ctr_offset;\n\tu64 cookie;\n\tstruct uprobe *uprobe;\n\tstruct uprobe_consumer consumer;\n\tbool session;\n};\n\nstruct bpf_uprobe_multi_link {\n\tstruct path path;\n\tstruct bpf_link link;\n\tu32 cnt;\n\tstruct bpf_uprobe *uprobes;\n\tstruct task_struct *task;\n};\n\nstruct bpf_uprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tlong unsigned int entry_ip;\n\tstruct bpf_uprobe *uprobe;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpf_xfrm_state {\n\t__u32 reqid;\n\t__u32 spi;\n\t__u16 family;\n\t__u16 ext;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n};\n\nstruct bpf_xfrm_state_opts {\n\ts32 error;\n\ts32 netns_id;\n\tu32 mark;\n\txfrm_address_t daddr;\n\t__be32 spi;\n\tu8 proto;\n\tu16 family;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nstruct br_input_skb_cb {\n\tstruct net_device *brdev;\n\tu16 frag_max_size;\n\tu8 igmp;\n\tu8 mrouters_only: 1;\n\tu8 proxyarp_replied: 1;\n\tu8 src_port_isolated: 1;\n\tu8 promisc: 1;\n\tu8 vlan_filtered: 1;\n\tu8 br_netfilter_broute: 1;\n\tu32 backup_nhid;\n};\n\nstruct br_ip {\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t} src;\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t\tunsigned char mac_addr[6];\n\t} dst;\n\t__be16 proto;\n\t__u16 vid;\n};\n\nstruct br_mcast_stats {\n\t__u64 igmp_v1queries[2];\n\t__u64 igmp_v2queries[2];\n\t__u64 igmp_v3queries[2];\n\t__u64 igmp_leaves[2];\n\t__u64 igmp_v1reports[2];\n\t__u64 igmp_v2reports[2];\n\t__u64 igmp_v3reports[2];\n\t__u64 igmp_parse_errors;\n\t__u64 mld_v1queries[2];\n\t__u64 mld_v2queries[2];\n\t__u64 mld_leaves[2];\n\t__u64 mld_v1reports[2];\n\t__u64 mld_v2reports[2];\n\t__u64 mld_parse_errors;\n\t__u64 mcast_bytes[2];\n\t__u64 mcast_packets[2];\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct metadata_dst;\n\nstruct br_tunnel_info {\n\t__be64 tunnel_id;\n\tstruct metadata_dst *tunnel_dst;\n};\n\nstruct bridge_id {\n\tunsigned char prio[2];\n\tunsigned char addr[6];\n};\n\ntypedef struct bridge_id bridge_id;\n\nstruct bridge_mcast_other_query {\n\tstruct timer_list timer;\n\tstruct timer_list delay_timer;\n};\n\nstruct bridge_mcast_own_query {\n\tstruct timer_list timer;\n\tu32 startup_sent;\n};\n\nstruct bridge_mcast_querier {\n\tstruct br_ip addr;\n\tint port_ifidx;\n\tseqcount_spinlock_t seq;\n};\n\nstruct bridge_mcast_stats {\n\tstruct br_mcast_stats mstats;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct bridge_stp_xstats {\n\t__u64 transition_blk;\n\t__u64 transition_fwd;\n\t__u64 rx_bpdu;\n\t__u64 tx_bpdu;\n\t__u64 rx_tcn;\n\t__u64 tx_tcn;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[56];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_ptr {\n\tvoid *ptr;\n\t__u32 type_id;\n\t__u32 flags;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\ntypedef void *va_list;\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, va_list);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct nd_region;\n\nstruct btt {\n\tstruct gendisk *btt_disk;\n\tstruct list_head arena_list;\n\tstruct dentry *debugfs_dir;\n\tstruct nd_btt *nd_btt;\n\tu64 nlba;\n\tlong long unsigned int rawsize;\n\tu32 lbasize;\n\tu32 sector_size;\n\tstruct nd_region *nd_region;\n\tstruct mutex init_lock;\n\tint init_state;\n\tint num_arenas;\n\tstruct badblocks *phys_bb;\n};\n\nstruct btt_sb {\n\tu8 signature[16];\n\tu8 uuid[16];\n\tu8 parent_uuid[16];\n\t__le32 flags;\n\t__le16 version_major;\n\t__le16 version_minor;\n\t__le32 external_lbasize;\n\t__le32 external_nlba;\n\t__le32 internal_lbasize;\n\t__le32 internal_nlba;\n\t__le32 nfree;\n\t__le32 infosize;\n\t__le64 nextoff;\n\t__le64 dataoff;\n\t__le64 mapoff;\n\t__le64 logoff;\n\t__le64 info2off;\n\tu8 padding[3968];\n\t__le64 checksum;\n};\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 64;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n};\n\nstruct buffer_data_read_page {\n\tunsigned int order;\n\tstruct buffer_data_page *data;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tunsigned int order;\n\tu32 id: 30;\n\tu32 range: 1;\n\tstruct buffer_data_page *page;\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct bug_entry {\n\tint bug_addr_disp;\n\tint file_disp;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct bulk_cb_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 DataTransferLength;\n\t__u8 Flags;\n\t__u8 Lun;\n\t__u8 Length;\n\t__u8 CDB[16];\n};\n\nstruct bulk_cs_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 Residue;\n\t__u8 Status;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct cache_head;\n\nstruct cache_deferred_req {\n\tstruct hlist_node hash;\n\tstruct list_head recent;\n\tstruct cache_head *item;\n\tvoid *owner;\n\tvoid (*revisit)(struct cache_deferred_req *, int);\n};\n\nstruct cache_detail {\n\tstruct module *owner;\n\tint hash_size;\n\tstruct hlist_head *hash_table;\n\tspinlock_t hash_lock;\n\tchar *name;\n\tvoid (*cache_put)(struct kref *);\n\tint (*cache_upcall)(struct cache_detail *, struct cache_head *);\n\tvoid (*cache_request)(struct cache_detail *, struct cache_head *, char **, int *);\n\tint (*cache_parse)(struct cache_detail *, char *, int);\n\tint (*cache_show)(struct seq_file *, struct cache_detail *, struct cache_head *);\n\tvoid (*warn_no_listener)(struct cache_detail *, int);\n\tstruct cache_head * (*alloc)(void);\n\tvoid (*flush)(void);\n\tint (*match)(struct cache_head *, struct cache_head *);\n\tvoid (*init)(struct cache_head *, struct cache_head *);\n\tvoid (*update)(struct cache_head *, struct cache_head *);\n\ttime64_t flush_time;\n\tstruct list_head others;\n\ttime64_t nextcheck;\n\tint entries;\n\tstruct list_head queue;\n\tatomic_t writers;\n\ttime64_t last_close;\n\ttime64_t last_warn;\n\tunion {\n\t\tstruct proc_dir_entry *procfs;\n\t\tstruct dentry *pipefs;\n\t};\n\tstruct net *net;\n};\n\nstruct cache_head {\n\tstruct hlist_node cache_list;\n\ttime64_t expiry_time;\n\ttime64_t last_refresh;\n\tstruct kref ref;\n\tlong unsigned int flags;\n};\n\nstruct cache_queue {\n\tstruct list_head list;\n\tint reader;\n};\n\nstruct cache_reader {\n\tstruct cache_queue q;\n\tint offset;\n};\n\nstruct cache_req {\n\tstruct cache_deferred_req * (*defer)(struct cache_req *);\n\tlong unsigned int thread_wait;\n};\n\nstruct cache_request {\n\tstruct cache_queue q;\n\tstruct cache_head *item;\n\tchar *buf;\n\tint len;\n\tint readers;\n};\n\nstruct cache_type_info {\n\tconst char *size_prop;\n\tconst char *line_size_props[2];\n\tconst char *nr_sets_prop;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct cb_process_state;\n\nstruct xdr_stream;\n\nstruct callback_op {\n\t__be32 (*process_op)(void *, void *, struct cb_process_state *);\n\t__be32 (*decode_args)(struct svc_rqst *, struct xdr_stream *, void *);\n\t__be32 (*encode_res)(struct svc_rqst *, struct xdr_stream *, const void *);\n\tlong int res_maxsize;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct cat_datum {\n\tu32 value;\n\tunsigned char isalias;\n};\n\nstruct cb_compound_hdr_arg {\n\tunsigned int taglen;\n\tconst char *tag;\n\tunsigned int minorversion;\n\tunsigned int cb_ident;\n\tunsigned int nops;\n};\n\nstruct cb_compound_hdr_res {\n\t__be32 *status;\n\tunsigned int taglen;\n\tconst char *tag;\n\t__be32 *nops;\n};\n\nstruct cb_devicenotifyitem;\n\nstruct cb_devicenotifyargs {\n\tuint32_t ndevs;\n\tstruct cb_devicenotifyitem *devs;\n};\n\nstruct nfs4_deviceid {\n\tchar data[16];\n};\n\nstruct cb_devicenotifyitem {\n\tuint32_t cbd_notify_type;\n\tuint32_t cbd_layout_type;\n\tstruct nfs4_deviceid cbd_dev_id;\n\tuint32_t cbd_immediate;\n};\n\nstruct nfs_fh {\n\tshort unsigned int size;\n\tunsigned char data[128];\n};\n\nstruct cb_getattrargs {\n\tstruct nfs_fh fh;\n\tuint32_t bitmap[3];\n};\n\nstruct cb_getattrres {\n\t__be32 status;\n\tuint32_t bitmap[3];\n\tuint64_t size;\n\tuint64_t change_attr;\n\tstruct timespec64 atime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 mtime;\n};\n\nstruct pnfs_layout_range {\n\tu32 iomode;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct nfs4_stateid_struct {\n\tunion {\n\t\tchar data[16];\n\t\tstruct {\n\t\t\t__be32 seqid;\n\t\t\tchar other[12];\n\t\t};\n\t};\n\tenum {\n\t\tNFS4_INVALID_STATEID_TYPE = 0,\n\t\tNFS4_SPECIAL_STATEID_TYPE = 1,\n\t\tNFS4_OPEN_STATEID_TYPE = 2,\n\t\tNFS4_LOCK_STATEID_TYPE = 3,\n\t\tNFS4_DELEGATION_STATEID_TYPE = 4,\n\t\tNFS4_LAYOUT_STATEID_TYPE = 5,\n\t\tNFS4_PNFS_DS_STATEID_TYPE = 6,\n\t\tNFS4_REVOKED_STATEID_TYPE = 7,\n\t\tNFS4_FREED_STATEID_TYPE = 8,\n\t} type;\n};\n\ntypedef struct nfs4_stateid_struct nfs4_stateid;\n\nstruct nfs_fsid {\n\tuint64_t major;\n\tuint64_t minor;\n};\n\nstruct cb_layoutrecallargs {\n\tuint32_t cbl_recall_type;\n\tuint32_t cbl_layout_type;\n\tuint32_t cbl_layoutchanged;\n\tunion {\n\t\tstruct {\n\t\t\tstruct nfs_fh cbl_fh;\n\t\t\tstruct pnfs_layout_range cbl_range;\n\t\t\tnfs4_stateid cbl_stateid;\n\t\t};\n\t\tstruct nfs_fsid cbl_fsid;\n\t};\n};\n\nstruct nfs_lowner {\n\t__u64 clientid;\n\t__u64 id;\n\tdev_t s_dev;\n};\n\nstruct cb_notify_lock_args {\n\tstruct nfs_fh cbnl_fh;\n\tstruct nfs_lowner cbnl_owner;\n\tbool cbnl_valid;\n};\n\nstruct nfs_write_verifier {\n\tchar data[8];\n};\n\nstruct nfs_writeverf {\n\tstruct nfs_write_verifier verifier;\n\tenum nfs3_stable_how committed;\n};\n\nstruct cb_offloadargs {\n\tstruct nfs_fh coa_fh;\n\tnfs4_stateid coa_stateid;\n\tuint32_t error;\n\tuint64_t wr_count;\n\tstruct nfs_writeverf wr_writeverf;\n};\n\nstruct nfs_client;\n\nstruct nfs4_slot;\n\nstruct cb_process_state {\n\tstruct nfs_client *clp;\n\tstruct nfs4_slot *slot;\n\tstruct net *net;\n\tu32 minorversion;\n\t__be32 drc_status;\n\tunsigned int referring_calls;\n};\n\nstruct cb_recallanyargs {\n\tuint32_t craa_objs_to_keep;\n\tuint32_t craa_type_mask;\n};\n\nstruct cb_recallargs {\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tuint32_t truncate;\n};\n\nstruct cb_recallslotargs {\n\tuint32_t crsa_target_highest_slotid;\n};\n\nstruct nfs4_sessionid {\n\tunsigned char data[16];\n};\n\nstruct referring_call_list;\n\nstruct cb_sequenceargs {\n\tstruct sockaddr *csa_addr;\n\tstruct nfs4_sessionid csa_sessionid;\n\tuint32_t csa_sequenceid;\n\tuint32_t csa_slotid;\n\tuint32_t csa_highestslotid;\n\tuint32_t csa_cachethis;\n\tuint32_t csa_nrclists;\n\tstruct referring_call_list *csa_rclists;\n};\n\nstruct cb_sequenceres {\n\t__be32 csr_status;\n\tstruct nfs4_sessionid csr_sessionid;\n\tuint32_t csr_sequenceid;\n\tuint32_t csr_slotid;\n\tuint32_t csr_highestslotid;\n\tuint32_t csr_target_highestslotid;\n};\n\nstruct ccs_modesel_head {\n\t__u8 _r1;\n\t__u8 medium;\n\t__u8 _r2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_blocks_hi;\n\t__u8 number_blocks_med;\n\t__u8 number_blocks_lo;\n\t__u8 _r3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct ccu_common {\n\tstruct regmap *regmap;\n\tstruct regmap *lock_regmap;\n\tunion {\n\t\tstruct {\n\t\t\tu32 reg_ctrl;\n\t\t\tu32 reg_fc;\n\t\t\tu32 mask_fc;\n\t\t};\n\t\tstruct {\n\t\t\tu32 reg_swcr1;\n\t\t\tu32 reg_swcr2;\n\t\t\tu32 reg_swcr3;\n\t\t};\n\t};\n\tstruct clk_hw hw;\n};\n\nstruct ccu_common___2 {\n\tvoid *base;\n\tu16 reg;\n\tu16 lock_reg;\n\tu32 prediv;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int features;\n\tspinlock_t *lock;\n\tstruct clk_hw hw;\n};\n\nstruct ccu_common___3 {\n\tint clkid;\n\tstruct regmap *map;\n\tu16 cfg0;\n\tu16 cfg1;\n\tstruct clk_hw hw;\n};\n\nstruct ccu_ddn {\n\tstruct ccu_common common;\n\tunsigned int num_mask;\n\tunsigned int num_shift;\n\tunsigned int den_mask;\n\tunsigned int den_shift;\n\tunsigned int pre_div;\n};\n\nstruct ccu_div_internal {\n\tu8 shift;\n\tu8 width;\n\tu32 flags;\n};\n\nstruct ccu_internal {\n\tu8 shift;\n\tu8 width;\n};\n\nstruct ccu_div {\n\tu32 enable;\n\tu32 div_en;\n\tstruct ccu_div_internal div;\n\tstruct ccu_internal mux;\n\tstruct ccu_common___3 common;\n};\n\nstruct clk_div_table;\n\nstruct ccu_div_internal___2 {\n\tu8 shift;\n\tu8 width;\n\tu32 max;\n\tu32 offset;\n\tu32 flags;\n\tstruct clk_div_table *table;\n};\n\nstruct ccu_mux_fixed_prediv;\n\nstruct ccu_mux_var_prediv;\n\nstruct ccu_mux_internal {\n\tu8 shift;\n\tu8 width;\n\tconst u8 *table;\n\tconst struct ccu_mux_fixed_prediv *fixed_predivs;\n\tu8 n_predivs;\n\tconst struct ccu_mux_var_prediv *var_predivs;\n\tu8 n_var_predivs;\n};\n\nstruct ccu_div___2 {\n\tu32 enable;\n\tstruct ccu_div_internal___2 div;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common___2 common;\n\tunsigned int fixed_post_div;\n};\n\nstruct ccu_div_config {\n\tu8 shift;\n\tu8 width;\n};\n\nstruct ccu_factor_config {\n\tu32 div;\n\tu32 mul;\n};\n\nstruct ccu_frac_internal {\n\tu32 enable;\n\tu32 select;\n\tlong unsigned int rates[2];\n};\n\nstruct clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct ccu_gate {\n\tint clkid;\n\tu32 reg;\n\tstruct clk_gate gate;\n};\n\nstruct ccu_gate___2 {\n\tu32 enable;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_gate_config {\n\tu32 mask;\n\tbool inverted;\n};\n\nstruct ccu_mux_config {\n\tu8 shift;\n\tu8 width;\n};\n\nstruct ccu_mix {\n\tstruct ccu_factor_config factor;\n\tstruct ccu_gate_config gate;\n\tstruct ccu_div_config div;\n\tstruct ccu_mux_config mux;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mp {\n\tu32 enable;\n\tstruct ccu_div_internal___2 m;\n\tstruct ccu_div_internal___2 p;\n\tstruct ccu_mux_internal mux;\n\tunsigned int fixed_post_div;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_mult_internal {\n\tu8 offset;\n\tu8 shift;\n\tu8 width;\n\tu8 min;\n\tu8 max;\n};\n\nstruct ccu_mult {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_frac_internal frac;\n\tstruct ccu_mult_internal mult;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_mux {\n\tu32 enable;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common___2 common;\n};\n\nstruct clk_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tconst u32 *table;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct ccu_mux___2 {\n\tint clkid;\n\tu32 reg;\n\tstruct clk_mux mux;\n};\n\nstruct ccu_mux_fixed_prediv {\n\tu8 index;\n\tu16 div;\n};\n\nstruct ccu_mux_nb {\n\tstruct notifier_block clk_nb;\n\tstruct ccu_common___2 *common;\n\tstruct ccu_mux_internal *cm;\n\tu32 delay_us;\n\tu8 bypass_index;\n\tu8 original_index;\n};\n\nstruct ccu_mux_var_prediv {\n\tu8 index;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct ccu_nk {\n\tu16 reg;\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tunsigned int fixed_post_div;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_nkm {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tstruct ccu_div_internal___2 m;\n\tstruct ccu_mux_internal mux;\n\tunsigned int fixed_post_div;\n\tlong unsigned int max_m_n_ratio;\n\tlong unsigned int min_parent_m_ratio;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_nkmp {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tstruct ccu_div_internal___2 m;\n\tstruct ccu_div_internal___2 p;\n\tunsigned int fixed_post_div;\n\tunsigned int max_rate;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_sdm_setting;\n\nstruct ccu_sdm_internal {\n\tstruct ccu_sdm_setting *table;\n\tu32 table_size;\n\tu32 enable;\n\tu32 tuning_enable;\n\tu16 tuning_reg;\n};\n\nstruct ccu_nm {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_div_internal___2 m;\n\tstruct ccu_frac_internal frac;\n\tstruct ccu_sdm_internal sdm;\n\tunsigned int fixed_post_div;\n\tunsigned int min_rate;\n\tunsigned int max_rate;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_phase {\n\tu8 shift;\n\tu8 width;\n\tstruct ccu_common___2 common;\n};\n\nstruct ccu_pll_rate_tbl;\n\nstruct ccu_pll_config {\n\tconst struct ccu_pll_rate_tbl *rate_tbl;\n\tu32 tbl_num;\n\tu32 reg_lock;\n\tu32 mask_lock;\n};\n\nstruct ccu_pll {\n\tstruct ccu_common common;\n\tstruct ccu_pll_config config;\n};\n\nstruct ccu_pll_cfg;\n\nstruct ccu_pll___2 {\n\tstruct ccu_common___3 common;\n\tu32 lock_sts_mask;\n\tint cfgnum;\n\tconst struct ccu_pll_cfg *cfgs;\n};\n\nstruct ccu_pll_cfg {\n\tlong unsigned int freq;\n\tu32 fbdiv;\n\tu32 frac;\n\tu32 postdiv1;\n\tu32 postdiv2;\n};\n\nstruct ccu_pll_nb {\n\tstruct notifier_block clk_nb;\n\tstruct ccu_common___2 *common;\n\tu32 enable;\n\tu32 lock;\n};\n\nstruct ccu_pll_rate_tbl {\n\tlong unsigned int rate;\n\tu32 swcr1;\n\tu32 swcr2;\n\tu32 swcr3;\n};\n\nstruct ccu_reset_map;\n\nstruct ccu_reset {\n\tvoid *base;\n\tconst struct ccu_reset_map *reset_map;\n\tspinlock_t *lock;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct ccu_reset_controller_data;\n\nstruct ccu_reset_controller {\n\tstruct reset_controller_dev rcdev;\n\tconst struct ccu_reset_controller_data *data;\n\tstruct regmap *regmap;\n};\n\nstruct ccu_reset_data;\n\nstruct ccu_reset_controller_data {\n\tconst struct ccu_reset_data *reset_data;\n\tsize_t count;\n};\n\nstruct ccu_reset_data {\n\tu32 offset;\n\tu32 assert_mask;\n\tu32 deassert_mask;\n};\n\nstruct ccu_reset_map {\n\tu16 reg;\n\tu32 bit;\n};\n\nstruct ccu_sdm_setting {\n\tlong unsigned int rate;\n\tu32 pattern;\n\tu32 m;\n\tu32 n;\n};\n\nstruct cdrom_msf0 {\n\t__u8 minute;\n\t__u8 second;\n\t__u8 frame;\n};\n\nunion cdrom_addr {\n\tstruct cdrom_msf0 msf;\n\tint lba;\n};\n\nstruct cdrom_blk {\n\tunsigned int from;\n\tshort unsigned int len;\n};\n\nstruct cdrom_mechstat_header {\n\t__u8 curslot: 5;\n\t__u8 changer_state: 2;\n\t__u8 fault: 1;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 mech_state: 3;\n\t__u8 curlba[3];\n\t__u8 nslots;\n\t__u16 slot_tablelen;\n};\n\nstruct cdrom_slot {\n\t__u8 change: 1;\n\t__u8 reserved1: 6;\n\t__u8 disc_present: 1;\n\t__u8 reserved2[3];\n};\n\nstruct cdrom_changer_info {\n\tstruct cdrom_mechstat_header hdr;\n\tstruct cdrom_slot slots[256];\n};\n\nstruct cdrom_device_ops;\n\nstruct cdrom_device_info {\n\tconst struct cdrom_device_ops *ops;\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tvoid *handle;\n\tint mask;\n\tint speed;\n\tint capacity;\n\tunsigned int options: 30;\n\tunsigned int mc_flags: 2;\n\tunsigned int vfs_events;\n\tunsigned int ioctl_events;\n\tint use_count;\n\tchar name[20];\n\t__u8 sanyo_slot: 2;\n\t__u8 keeplocked: 1;\n\t__u8 reserved: 5;\n\tint cdda_method;\n\t__u8 last_sense;\n\t__u8 media_written;\n\tshort unsigned int mmc3_profile;\n\tint mrw_mode_page;\n\tbool opened_for_data;\n\t__s64 last_media_change_ms;\n};\n\nstruct cdrom_multisession;\n\nstruct cdrom_mcn;\n\nstruct packet_command;\n\nstruct cdrom_device_ops {\n\tint (*open)(struct cdrom_device_info *, int);\n\tvoid (*release)(struct cdrom_device_info *);\n\tint (*drive_status)(struct cdrom_device_info *, int);\n\tunsigned int (*check_events)(struct cdrom_device_info *, unsigned int, int);\n\tint (*tray_move)(struct cdrom_device_info *, int);\n\tint (*lock_door)(struct cdrom_device_info *, int);\n\tint (*select_speed)(struct cdrom_device_info *, long unsigned int);\n\tint (*get_last_session)(struct cdrom_device_info *, struct cdrom_multisession *);\n\tint (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);\n\tint (*reset)(struct cdrom_device_info *);\n\tint (*audio_ioctl)(struct cdrom_device_info *, unsigned int, void *);\n\tint (*generic_packet)(struct cdrom_device_info *, struct packet_command *);\n\tint (*read_cdda_bpc)(struct cdrom_device_info *, void *, u32, u32, u8 *);\n\tconst int capability;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct cdrom_mcn {\n\t__u8 medium_catalog_number[14];\n};\n\nstruct cdrom_msf {\n\t__u8 cdmsf_min0;\n\t__u8 cdmsf_sec0;\n\t__u8 cdmsf_frame0;\n\t__u8 cdmsf_min1;\n\t__u8 cdmsf_sec1;\n\t__u8 cdmsf_frame1;\n};\n\nstruct cdrom_multisession {\n\tunion cdrom_addr addr;\n\t__u8 xa_flag;\n\t__u8 addr_format;\n};\n\nstruct cdrom_read_audio {\n\tunion cdrom_addr addr;\n\t__u8 addr_format;\n\tint nframes;\n\t__u8 *buf;\n};\n\nstruct cdrom_subchnl {\n\t__u8 cdsc_format;\n\t__u8 cdsc_audiostatus;\n\t__u8 cdsc_adr: 4;\n\t__u8 cdsc_ctrl: 4;\n\t__u8 cdsc_trk;\n\t__u8 cdsc_ind;\n\tunion cdrom_addr cdsc_absaddr;\n\tunion cdrom_addr cdsc_reladdr;\n};\n\nstruct cdrom_sysctl_settings {\n\tchar info[1000];\n\tint autoclose;\n\tint autoeject;\n\tint debug;\n\tint lock;\n\tint check;\n};\n\nstruct cdrom_ti {\n\t__u8 cdti_trk0;\n\t__u8 cdti_ind0;\n\t__u8 cdti_trk1;\n\t__u8 cdti_ind1;\n};\n\nstruct cdrom_timed_media_change_info {\n\t__s64 last_media_change;\n\t__u64 media_flags;\n};\n\nstruct cdrom_tocentry {\n\t__u8 cdte_track;\n\t__u8 cdte_adr: 4;\n\t__u8 cdte_ctrl: 4;\n\t__u8 cdte_format;\n\tunion cdrom_addr cdte_addr;\n\t__u8 cdte_datamode;\n};\n\nstruct cdrom_tochdr {\n\t__u8 cdth_trk0;\n\t__u8 cdth_trk1;\n};\n\nstruct cdrom_volctrl {\n\t__u8 channel0;\n\t__u8 channel1;\n\t__u8 channel2;\n\t__u8 channel3;\n};\n\nstruct clock_event_device;\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct cfi_private;\n\nstruct cfi_early_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct cfi_private *);\n};\n\nstruct cfi_extquery {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n};\n\nstruct mtd_info;\n\nstruct cfi_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct mtd_info *);\n};\n\nstruct cfi_ident {\n\tuint8_t qry[3];\n\tuint16_t P_ID;\n\tuint16_t P_ADR;\n\tuint16_t A_ID;\n\tuint16_t A_ADR;\n\tuint8_t VccMin;\n\tuint8_t VccMax;\n\tuint8_t VppMin;\n\tuint8_t VppMax;\n\tuint8_t WordWriteTimeoutTyp;\n\tuint8_t BufWriteTimeoutTyp;\n\tuint8_t BlockEraseTimeoutTyp;\n\tuint8_t ChipEraseTimeoutTyp;\n\tuint8_t WordWriteTimeoutMax;\n\tuint8_t BufWriteTimeoutMax;\n\tuint8_t BlockEraseTimeoutMax;\n\tuint8_t ChipEraseTimeoutMax;\n\tuint8_t DevSize;\n\tuint16_t InterfaceDesc;\n\tuint16_t MaxBufWriteSize;\n\tuint8_t NumEraseRegions;\n\tuint32_t EraseRegionInfo[0];\n} __attribute__((packed));\n\nstruct flchip {\n\tlong unsigned int start;\n\tint ref_point_counter;\n\tflstate_t state;\n\tflstate_t oldstate;\n\tunsigned int write_suspended: 1;\n\tunsigned int erase_suspended: 1;\n\tlong unsigned int in_progress_block_addr;\n\tlong unsigned int in_progress_block_mask;\n\tstruct mutex mutex;\n\twait_queue_head_t wq;\n\tint word_write_time;\n\tint buffer_write_time;\n\tint erase_time;\n\tint word_write_time_max;\n\tint buffer_write_time_max;\n\tint erase_time_max;\n\tvoid *priv;\n};\n\nstruct map_info;\n\nstruct cfi_private {\n\tuint16_t cmdset;\n\tvoid *cmdset_priv;\n\tint interleave;\n\tint device_type;\n\tint cfi_mode;\n\tint addr_unlock1;\n\tint addr_unlock2;\n\tstruct mtd_info * (*cmdset_setup)(struct map_info *);\n\tstruct cfi_ident *cfiq;\n\tint mfr;\n\tint id;\n\tint numchips;\n\tmap_word sector_erase_cmd;\n\tlong unsigned int chipshift;\n\tconst char *im_name;\n\tlong unsigned int quirks;\n\tstruct flchip chips[0];\n};\n\nstruct cfs_bandwidth {\n\traw_spinlock_t lock;\n\tktime_t period;\n\tu64 quota;\n\tu64 runtime;\n\tu64 burst;\n\tu64 runtime_snap;\n\ts64 hierarchical_quota;\n\tu8 idle;\n\tu8 period_active;\n\tu8 slack_started;\n\tstruct hrtimer period_timer;\n\tstruct hrtimer slack_timer;\n\tstruct list_head throttled_cfs_rq;\n\tint nr_periods;\n\tint nr_throttled;\n\tint nr_burst;\n\tu64 throttled_time;\n\tu64 burst_time;\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n};\n\nstruct sched_entity;\n\nstruct task_group;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tint runtime_enabled;\n\ts64 runtime_remaining;\n\tu64 throttled_pelt_idle;\n\tu64 throttled_clock;\n\tu64 throttled_clock_pelt;\n\tu64 throttled_clock_pelt_time;\n\tu64 throttled_clock_self;\n\tu64 throttled_clock_self_time;\n\tbool throttled: 1;\n\tbool pelt_clock_throttled: 1;\n\tint throttle_count;\n\tstruct list_head throttled_list;\n\tstruct list_head throttled_csd_list;\n\tstruct list_head throttled_limbo_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cfs_schedulable_data {\n\tstruct task_group *tg;\n\tu64 period;\n\tu64 quota;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 ntime;\n};\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n};\n\nstruct cgroup_bpf {\n\tstruct bpf_prog_array *effective[28];\n\tstruct hlist_head progs[28];\n\tu8 flags[28];\n\tu64 revisions[28];\n\tstruct list_head storages;\n\tstruct bpf_prog_array *inactive;\n\tstruct percpu_ref refcnt;\n\tstruct work_struct release_work;\n};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[0];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[12];\n\tint nr_dying_subsys[12];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[12];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct cgroup_cls_state {\n\tstruct cgroup_subsys_state css;\n\tu32 classid;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 64;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct check_loop_arg {\n\tstruct qdisc_walker w;\n\tstruct Qdisc *p;\n\tint depth;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct chip_probe {\n\tchar *name;\n\tint (*probe_chip)(struct map_info *, __u32, long unsigned int *, struct cfi_private *);\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct mmc_card;\n\nstruct sdio_func;\n\ntypedef int tpl_parse_t(struct mmc_card *, struct sdio_func *, const unsigned char *, unsigned int);\n\nstruct cis_tpl {\n\tunsigned char code;\n\tunsigned char min_size;\n\ttpl_parse_t *parse;\n};\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct hashtab_node;\n\nstruct hashtab {\n\tstruct hashtab_node **htable;\n\tu32 size;\n\tu32 nel;\n};\n\nstruct symtab {\n\tstruct hashtab table;\n\tu32 nprim;\n};\n\nstruct common_datum;\n\nstruct constraint_node;\n\nstruct class_datum {\n\tu32 value;\n\tchar *comkey;\n\tstruct common_datum *comdatum;\n\tstruct symtab permissions;\n\tstruct constraint_node *constraints;\n\tstruct constraint_node *validatetrans;\n\tchar default_user;\n\tchar default_role;\n\tchar default_type;\n\tchar default_range;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_info {\n\tint class;\n\tchar *class_name;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct clear_badblocks_context {\n\tresource_size_t phys;\n\tresource_size_t cleared;\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct clk {\n\tstruct clk_core *core;\n\tstruct device *dev;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tunsigned int exclusive_count;\n\tstruct hlist_node clks_node;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct clk_bulk_devres {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct clk_rate_request;\n\nstruct clk_duty;\n\nstruct clk_ops {\n\tint (*prepare)(struct clk_hw *);\n\tvoid (*unprepare)(struct clk_hw *);\n\tint (*is_prepared)(struct clk_hw *);\n\tvoid (*unprepare_unused)(struct clk_hw *);\n\tint (*enable)(struct clk_hw *);\n\tvoid (*disable)(struct clk_hw *);\n\tint (*is_enabled)(struct clk_hw *);\n\tvoid (*disable_unused)(struct clk_hw *);\n\tint (*save_context)(struct clk_hw *);\n\tvoid (*restore_context)(struct clk_hw *);\n\tlong unsigned int (*recalc_rate)(struct clk_hw *, long unsigned int);\n\tlong int (*round_rate)(struct clk_hw *, long unsigned int, long unsigned int *);\n\tint (*determine_rate)(struct clk_hw *, struct clk_rate_request *);\n\tint (*set_parent)(struct clk_hw *, u8);\n\tu8 (*get_parent)(struct clk_hw *);\n\tint (*set_rate)(struct clk_hw *, long unsigned int, long unsigned int);\n\tint (*set_rate_and_parent)(struct clk_hw *, long unsigned int, long unsigned int, u8);\n\tlong unsigned int (*recalc_accuracy)(struct clk_hw *, long unsigned int);\n\tint (*get_phase)(struct clk_hw *);\n\tint (*set_phase)(struct clk_hw *, int);\n\tint (*get_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*set_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*init)(struct clk_hw *);\n\tvoid (*terminate)(struct clk_hw *);\n\tvoid (*debug_init)(struct clk_hw *, struct dentry *);\n};\n\nstruct clk_composite {\n\tstruct clk_hw hw;\n\tstruct clk_ops ops;\n\tstruct clk_hw *mux_hw;\n\tstruct clk_hw *rate_hw;\n\tstruct clk_hw *gate_hw;\n\tconst struct clk_ops *mux_ops;\n\tconst struct clk_ops *rate_ops;\n\tconst struct clk_ops *gate_ops;\n};\n\nstruct clk_duty {\n\tunsigned int num;\n\tunsigned int den;\n};\n\nstruct clk_parent_map;\n\nstruct clk_core {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tstruct clk_hw *hw;\n\tstruct module *owner;\n\tstruct device *dev;\n\tstruct hlist_node rpm_node;\n\tstruct device_node *of_node;\n\tstruct clk_core *parent;\n\tstruct clk_parent_map *parents;\n\tu8 num_parents;\n\tu8 new_parent_index;\n\tlong unsigned int rate;\n\tlong unsigned int req_rate;\n\tlong unsigned int new_rate;\n\tstruct clk_core *new_parent;\n\tstruct clk_core *new_child;\n\tlong unsigned int flags;\n\tbool orphan;\n\tbool rpm_enabled;\n\tunsigned int enable_count;\n\tunsigned int prepare_count;\n\tunsigned int protect_count;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int accuracy;\n\tint phase;\n\tstruct clk_duty duty;\n\tstruct hlist_head children;\n\tstruct hlist_node child_node;\n\tstruct hlist_node hashtable_node;\n\tstruct hlist_head clks;\n\tunsigned int notifier_count;\n\tstruct dentry *dentry;\n\tstruct hlist_node debug_node;\n\tstruct kref ref;\n};\n\nstruct clk_div_table {\n\tunsigned int val;\n\tunsigned int div;\n};\n\nstruct clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu16 flags;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct clk_fixed_factor {\n\tstruct clk_hw hw;\n\tunsigned int mult;\n\tunsigned int div;\n\tlong unsigned int acc;\n\tunsigned int flags;\n};\n\nstruct clk_fixed_rate {\n\tstruct clk_hw hw;\n\tlong unsigned int fixed_rate;\n\tlong unsigned int fixed_accuracy;\n\tlong unsigned int flags;\n};\n\nstruct clk_fractional_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 mshift;\n\tu8 mwidth;\n\tu8 nshift;\n\tu8 nwidth;\n\tu8 flags;\n\tvoid (*approximation)(struct clk_hw *, long unsigned int, long unsigned int *, long unsigned int *, long unsigned int *);\n\tspinlock_t *lock;\n};\n\nstruct clk_gpio {\n\tstruct clk_hw hw;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct clk_gated_fixed {\n\tstruct clk_gpio clk_gpio;\n\tstruct regulator *supply;\n\tlong unsigned int rate;\n};\n\nstruct clk_parent_data;\n\nstruct clk_init_data {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tconst char * const *parent_names;\n\tconst struct clk_parent_data *parent_data;\n\tconst struct clk_hw **parent_hws;\n\tu8 num_parents;\n\tlong unsigned int flags;\n};\n\nstruct clk_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct clk *clk;\n\tstruct clk_hw *clk_hw;\n};\n\nstruct clk_lookup_alloc {\n\tstruct clk_lookup cl;\n\tchar dev_id[24];\n\tchar con_id[16];\n};\n\nstruct clk_multiplier {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct srcu_node;\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[3];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct clk_notifier {\n\tstruct clk *clk;\n\tstruct srcu_notifier_head notifier_head;\n\tstruct list_head node;\n};\n\nstruct clk_notifier_data {\n\tstruct clk *clk;\n\tlong unsigned int old_rate;\n\tlong unsigned int new_rate;\n};\n\nstruct clk_notifier_devres {\n\tstruct clk *clk;\n\tstruct notifier_block *nb;\n};\n\nstruct clk_onecell_data {\n\tstruct clk **clks;\n\tunsigned int clk_num;\n};\n\nstruct clk_parent_data {\n\tconst struct clk_hw *hw;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_parent_map {\n\tconst struct clk_hw *hw;\n\tstruct clk_core *core;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_rate_request {\n\tstruct clk_core *core;\n\tlong unsigned int rate;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int best_parent_rate;\n\tstruct clk_hw *best_parent_hw;\n};\n\nstruct clock_read_data {\n\tu64 epoch_ns;\n\tu64 epoch_cyc;\n\tu64 sched_clock_mask;\n\tu64 (*read_sched_clock)(void);\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct clock_data {\n\tseqcount_latch_t seq;\n\tstruct clock_read_data read_data[2];\n\tktime_t wrap_kt;\n\tlong unsigned int rate;\n\tu64 (*actual_read_sched_clock)(void);\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct clock_provider {\n\tvoid (*clk_init_cb)(struct device_node *);\n\tstruct device_node *np;\n\tstruct list_head node;\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct module *owner;\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clocksource_mmio {\n\tvoid *reg;\n\tstruct clocksource clksrc;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct command_iu {\n\t__u8 iu_id;\n\t__u8 rsvd1;\n\t__be16 tag;\n\t__u8 prio_attr;\n\t__u8 rsvd5;\n\t__u8 len;\n\t__u8 rsvd7;\n\tstruct scsi_lun lun;\n\t__u8 cdb[16];\n};\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n};\n\nstruct common_datum {\n\tu32 value;\n\tstruct symtab permissions;\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[11];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_blkpg_ioctl_arg {\n\tcompat_int_t op;\n\tcompat_int_t flags;\n\tcompat_int_t datalen;\n\tcompat_caddr_t data;\n};\n\nstruct compat_cdrom_generic_command {\n\tunsigned char cmd[12];\n\tcompat_caddr_t buffer;\n\tcompat_uint_t buflen;\n\tcompat_int_t stat;\n\tcompat_caddr_t sense;\n\tunsigned char data_direction;\n\tunsigned char pad[3];\n\tcompat_int_t quiet;\n\tcompat_int_t timeout;\n\tcompat_caddr_t unused;\n};\n\nstruct compat_cdrom_read_audio {\n\tunion cdrom_addr addr;\n\tu8 addr_format;\n\tcompat_int_t nframes;\n\tcompat_caddr_t buf;\n};\n\nstruct compat_cmsghdr {\n\tcompat_size_t cmsg_len;\n\tcompat_int_t cmsg_level;\n\tcompat_int_t cmsg_type;\n};\n\nstruct compat_console_font_op {\n\tcompat_uint_t op;\n\tcompat_uint_t flags;\n\tcompat_uint_t width;\n\tcompat_uint_t height;\n\tcompat_uint_t charcount;\n\tcompat_caddr_t data;\n};\n\nstruct compat_dirent {\n\tu32 d_ino;\n\tcompat_off_t d_off;\n\tu16 d_reclen;\n\tchar d_name[256];\n};\n\nstruct compat_elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tcompat_ulong_t pr_flag;\n\t__compat_uid_t pr_uid;\n\t__compat_gid_t pr_gid;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct compat_elf_siginfo {\n\tcompat_int_t si_signo;\n\tcompat_int_t si_code;\n\tcompat_int_t si_errno;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct compat_elf_prstatus_common {\n\tstruct compat_elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tcompat_ulong_t pr_sigpend;\n\tcompat_ulong_t pr_sighold;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tstruct old_timeval32 pr_utime;\n\tstruct old_timeval32 pr_stime;\n\tstruct old_timeval32 pr_cutime;\n\tstruct old_timeval32 pr_cstime;\n};\n\nstruct compat_elf_prstatus {\n\tstruct compat_elf_prstatus_common common;\n\tcompat_elf_gregset_t pr_reg;\n\tcompat_int_t pr_fpvalid;\n};\n\nstruct compat_ext4_new_group_input {\n\tu32 group;\n\tcompat_u64 block_bitmap;\n\tcompat_u64 inode_bitmap;\n\tcompat_u64 inode_table;\n\tu32 blocks_count;\n\tu16 reserved_blocks;\n\tu16 unused;\n};\n\nstruct compat_flock {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_off_t l_start;\n\tcompat_off_t l_len;\n\tcompat_pid_t l_pid;\n};\n\nstruct compat_flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_loff_t l_start;\n\tcompat_loff_t l_len;\n\tcompat_pid_t l_pid;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct compat_linux_dirent;\n\nstruct compat_getdents_callback {\n\tstruct dir_context ctx;\n\tstruct compat_linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t} __attribute__((packed));\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n} __attribute__((packed));\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n} __attribute__((packed));\n\nstruct compat_hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tu32 start;\n};\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\tu32 rtmsg_type;\n\tu16 rtmsg_dst_len;\n\tu16 rtmsg_src_len;\n\tu32 rtmsg_metric;\n\tu32 rtmsg_info;\n\tu32 rtmsg_flags;\n\ts32 rtmsg_ifindex;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_ipc64_perm {\n\tcompat_key_t key;\n\t__compat_uid32_t uid;\n\t__compat_gid32_t gid;\n\t__compat_uid32_t cuid;\n\t__compat_gid32_t cgid;\n\tcompat_mode_t mode;\n\tunsigned char __pad1[0];\n\tcompat_ushort_t seq;\n\tcompat_ushort_t __pad2;\n\tcompat_ulong_t unused1;\n\tcompat_ulong_t unused2;\n};\n\nstruct compat_ipc_perm {\n\tkey_t key;\n\t__compat_uid_t uid;\n\t__compat_gid_t gid;\n\t__compat_uid_t cuid;\n\t__compat_gid_t cgid;\n\tcompat_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct compat_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct compat_loop_info {\n\tcompat_int_t lo_number;\n\tcompat_dev_t lo_device;\n\tcompat_ulong_t lo_inode;\n\tcompat_dev_t lo_rdevice;\n\tcompat_int_t lo_offset;\n\tcompat_int_t lo_encrypt_type;\n\tcompat_int_t lo_encrypt_key_size;\n\tcompat_int_t lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tcompat_ulong_t lo_init[2];\n\tchar reserved[4];\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_mq_attr {\n\tcompat_long_t mq_flags;\n\tcompat_long_t mq_maxmsg;\n\tcompat_long_t mq_msgsize;\n\tcompat_long_t mq_curmsgs;\n\tcompat_long_t __reserved[4];\n};\n\nstruct compat_msgbuf {\n\tcompat_long_t mtype;\n\tchar mtext[0];\n};\n\nstruct compat_msqid64_ds {\n\tstruct compat_ipc64_perm msg_perm;\n\tcompat_ulong_t msg_stime;\n\tcompat_ulong_t msg_stime_high;\n\tcompat_ulong_t msg_rtime;\n\tcompat_ulong_t msg_rtime_high;\n\tcompat_ulong_t msg_ctime;\n\tcompat_ulong_t msg_ctime_high;\n\tcompat_ulong_t msg_cbytes;\n\tcompat_ulong_t msg_qnum;\n\tcompat_ulong_t msg_qbytes;\n\tcompat_pid_t msg_lspid;\n\tcompat_pid_t msg_lrpid;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_msqid_ds {\n\tstruct compat_ipc_perm msg_perm;\n\tcompat_uptr_t msg_first;\n\tcompat_uptr_t msg_last;\n\told_time32_t msg_stime;\n\told_time32_t msg_rtime;\n\told_time32_t msg_ctime;\n\tcompat_ulong_t msg_lcbytes;\n\tcompat_ulong_t msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\tcompat_ipc_pid_t msg_lspid;\n\tcompat_ipc_pid_t msg_lrpid;\n};\n\nstruct compat_nfs_string {\n\tcompat_uint_t len;\n\tcompat_uptr_t data;\n};\n\nstruct compat_nfs4_mount_data_v1 {\n\tcompat_int_t version;\n\tcompat_int_t flags;\n\tcompat_int_t rsize;\n\tcompat_int_t wsize;\n\tcompat_int_t timeo;\n\tcompat_int_t retrans;\n\tcompat_int_t acregmin;\n\tcompat_int_t acregmax;\n\tcompat_int_t acdirmin;\n\tcompat_int_t acdirmax;\n\tstruct compat_nfs_string client_addr;\n\tstruct compat_nfs_string mnt_path;\n\tstruct compat_nfs_string hostname;\n\tcompat_uint_t host_addrlen;\n\tcompat_uptr_t host_addr;\n\tcompat_int_t proto;\n\tcompat_int_t auth_flavourlen;\n\tcompat_uptr_t auth_flavours;\n};\n\nstruct compat_old_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct compat_readdir_callback {\n\tstruct dir_context ctx;\n\tstruct compat_old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct compat_rlimit {\n\tcompat_ulong_t rlim_cur;\n\tcompat_ulong_t rlim_max;\n};\n\nstruct compat_robust_list {\n\tcompat_uptr_t next;\n};\n\nstruct compat_robust_list_head {\n\tstruct compat_robust_list list;\n\tcompat_long_t futex_offset;\n\tcompat_uptr_t list_op_pending;\n};\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\nstruct compat_sigaltstack {\n\tcompat_uptr_t ss_sp;\n\tint ss_flags;\n\tcompat_size_t ss_size;\n};\n\ntypedef struct compat_sigaltstack compat_stack_t;\n\nstruct compat_user_regs_struct {\n\tcompat_ulong_t pc;\n\tcompat_ulong_t ra;\n\tcompat_ulong_t sp;\n\tcompat_ulong_t gp;\n\tcompat_ulong_t tp;\n\tcompat_ulong_t t0;\n\tcompat_ulong_t t1;\n\tcompat_ulong_t t2;\n\tcompat_ulong_t s0;\n\tcompat_ulong_t s1;\n\tcompat_ulong_t a0;\n\tcompat_ulong_t a1;\n\tcompat_ulong_t a2;\n\tcompat_ulong_t a3;\n\tcompat_ulong_t a4;\n\tcompat_ulong_t a5;\n\tcompat_ulong_t a6;\n\tcompat_ulong_t a7;\n\tcompat_ulong_t s2;\n\tcompat_ulong_t s3;\n\tcompat_ulong_t s4;\n\tcompat_ulong_t s5;\n\tcompat_ulong_t s6;\n\tcompat_ulong_t s7;\n\tcompat_ulong_t s8;\n\tcompat_ulong_t s9;\n\tcompat_ulong_t s10;\n\tcompat_ulong_t s11;\n\tcompat_ulong_t t3;\n\tcompat_ulong_t t4;\n\tcompat_ulong_t t5;\n\tcompat_ulong_t t6;\n};\n\nstruct compat_sigcontext {\n\tstruct compat_user_regs_struct sc_regs;\n\tunion __riscv_fp_state sc_fpregs;\n};\n\nstruct compat_ucontext {\n\tcompat_ulong_t uc_flags;\n\tstruct compat_ucontext *uc_link;\n\tcompat_stack_t uc_stack;\n\tsigset_t uc_sigmask;\n\t__u8 __unused[120];\n\tstruct compat_sigcontext uc_mcontext;\n};\n\nstruct compat_rt_sigframe {\n\tstruct compat_siginfo info;\n\tstruct compat_ucontext uc;\n};\n\nstruct compat_rtentry {\n\tu32 rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tu32 rt_pad3;\n\tunsigned char rt_tos;\n\tunsigned char rt_class;\n\tshort int rt_pad4;\n\tshort int rt_metric;\n\tcompat_uptr_t rt_dev;\n\tu32 rt_mtu;\n\tu32 rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct compat_rusage {\n\tstruct old_timeval32 ru_utime;\n\tstruct old_timeval32 ru_stime;\n\tcompat_long_t ru_maxrss;\n\tcompat_long_t ru_ixrss;\n\tcompat_long_t ru_idrss;\n\tcompat_long_t ru_isrss;\n\tcompat_long_t ru_minflt;\n\tcompat_long_t ru_majflt;\n\tcompat_long_t ru_nswap;\n\tcompat_long_t ru_inblock;\n\tcompat_long_t ru_oublock;\n\tcompat_long_t ru_msgsnd;\n\tcompat_long_t ru_msgrcv;\n\tcompat_long_t ru_nsignals;\n\tcompat_long_t ru_nvcsw;\n\tcompat_long_t ru_nivcsw;\n};\n\nstruct compat_sel_arg_struct {\n\tcompat_ulong_t n;\n\tcompat_uptr_t inp;\n\tcompat_uptr_t outp;\n\tcompat_uptr_t exp;\n\tcompat_uptr_t tvp;\n};\n\nstruct compat_semid64_ds {\n\tstruct compat_ipc64_perm sem_perm;\n\tcompat_ulong_t sem_otime;\n\tcompat_ulong_t sem_otime_high;\n\tcompat_ulong_t sem_ctime;\n\tcompat_ulong_t sem_ctime_high;\n\tcompat_ulong_t sem_nsems;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_semid_ds {\n\tstruct compat_ipc_perm sem_perm;\n\told_time32_t sem_otime;\n\told_time32_t sem_ctime;\n\tcompat_uptr_t sem_base;\n\tcompat_uptr_t sem_pending;\n\tcompat_uptr_t sem_pending_last;\n\tcompat_uptr_t undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct compat_sg_io_hdr {\n\tcompat_int_t interface_id;\n\tcompat_int_t dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tcompat_uint_t dxfer_len;\n\tcompat_uint_t dxferp;\n\tcompat_uptr_t cmdp;\n\tcompat_uptr_t sbp;\n\tcompat_uint_t timeout;\n\tcompat_uint_t flags;\n\tcompat_int_t pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tcompat_int_t resid;\n\tcompat_uint_t duration;\n\tcompat_uint_t info;\n};\n\nstruct compat_shm_info {\n\tcompat_int_t used_ids;\n\tcompat_ulong_t shm_tot;\n\tcompat_ulong_t shm_rss;\n\tcompat_ulong_t shm_swp;\n\tcompat_ulong_t swap_attempts;\n\tcompat_ulong_t swap_successes;\n};\n\nstruct compat_shmid64_ds {\n\tstruct compat_ipc64_perm shm_perm;\n\tcompat_size_t shm_segsz;\n\tcompat_ulong_t shm_atime;\n\tcompat_ulong_t shm_atime_high;\n\tcompat_ulong_t shm_dtime;\n\tcompat_ulong_t shm_dtime_high;\n\tcompat_ulong_t shm_ctime;\n\tcompat_ulong_t shm_ctime_high;\n\tcompat_pid_t shm_cpid;\n\tcompat_pid_t shm_lpid;\n\tcompat_ulong_t shm_nattch;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_shmid_ds {\n\tstruct compat_ipc_perm shm_perm;\n\tint shm_segsz;\n\told_time32_t shm_atime;\n\told_time32_t shm_dtime;\n\told_time32_t shm_ctime;\n\tcompat_ipc_pid_t shm_cpid;\n\tcompat_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tcompat_uptr_t shm_unused2;\n\tcompat_uptr_t shm_unused3;\n};\n\nstruct compat_shminfo64 {\n\tcompat_ulong_t shmmax;\n\tcompat_ulong_t shmmin;\n\tcompat_ulong_t shmmni;\n\tcompat_ulong_t shmseg;\n\tcompat_ulong_t shmall;\n\tcompat_ulong_t __unused1;\n\tcompat_ulong_t __unused2;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_ulong_t sa_flags;\n\tcompat_sigset_t sa_mask;\n};\n\nstruct compat_sigevent {\n\tcompat_sigval_t sigev_value;\n\tcompat_int_t sigev_signo;\n\tcompat_int_t sigev_notify;\n\tunion {\n\t\tcompat_int_t _pad[13];\n\t\tcompat_int_t _tid;\n\t\tstruct {\n\t\t\tcompat_uptr_t _function;\n\t\t\tcompat_uptr_t _attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\ntypedef struct compat_siginfo compat_siginfo_t;\n\nstruct compat_sigset_argpack {\n\tcompat_uptr_t p;\n\tcompat_size_t size;\n};\n\nstruct compat_snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct compat_statfs {\n\tcompat_int_t f_type;\n\tcompat_int_t f_bsize;\n\tcompat_int_t f_blocks;\n\tcompat_int_t f_bfree;\n\tcompat_int_t f_bavail;\n\tcompat_int_t f_files;\n\tcompat_int_t f_ffree;\n\tcompat_fsid_t f_fsid;\n\tcompat_int_t f_namelen;\n\tcompat_int_t f_frsize;\n\tcompat_int_t f_flags;\n\tcompat_int_t f_spare[4];\n};\n\nstruct compat_statfs64 {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_frsize;\n\t__u32 f_flags;\n\t__u32 f_spare[4];\n};\n\nstruct compat_sysinfo {\n\ts32 uptime;\n\tu32 loads[3];\n\tu32 totalram;\n\tu32 freeram;\n\tu32 sharedram;\n\tu32 bufferram;\n\tu32 totalswap;\n\tu32 freeswap;\n\tu16 procs;\n\tu16 pad;\n\tu32 totalhigh;\n\tu32 freehigh;\n\tu32 mem_unit;\n\tchar _f[8];\n};\n\nstruct compat_tms {\n\tcompat_clock_t tms_utime;\n\tcompat_clock_t tms_stime;\n\tcompat_clock_t tms_cutime;\n\tcompat_clock_t tms_cstime;\n};\n\nstruct compat_unimapdesc {\n\tshort unsigned int entry_ct;\n\tcompat_caddr_t entries;\n};\n\nstruct compat_ustat {\n\tcompat_daddr_t f_tfree;\n\tcompat_ino_t f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\nstruct compound_hdr {\n\tint32_t status;\n\tuint32_t nops;\n\t__be32 *nops_p;\n\tuint32_t taglen;\n\tchar *tag;\n\tuint32_t replen;\n\tu32 minorversion;\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct cond_av_list {\n\tstruct avtab_node **nodes;\n\tu32 len;\n};\n\nstruct cond_bool_datum {\n\tu32 value;\n\tint state;\n};\n\nstruct cond_expr_node;\n\nstruct cond_expr {\n\tstruct cond_expr_node *nodes;\n\tu32 len;\n};\n\nstruct cond_expr_node {\n\tu32 expr_type;\n\tu32 boolean;\n};\n\nstruct policydb;\n\nstruct cond_insertf_data {\n\tstruct policydb *p;\n\tstruct avtab_node **dst;\n\tstruct cond_av_list *other;\n};\n\nstruct cond_node {\n\tint cur_state;\n\tstruct cond_expr expr;\n\tstruct cond_av_list true_list;\n\tstruct cond_av_list false_list;\n};\n\nstruct config_group;\n\nstruct config_item_type;\n\nstruct config_item {\n\tchar *ci_name;\n\tchar ci_namebuf[20];\n\tstruct kref ci_kref;\n\tstruct list_head ci_entry;\n\tstruct config_item *ci_parent;\n\tstruct config_group *ci_group;\n\tconst struct config_item_type *ci_type;\n\tstruct dentry *ci_dentry;\n};\n\nstruct configfs_subsystem;\n\nstruct config_group {\n\tstruct config_item cg_item;\n\tstruct list_head cg_children;\n\tstruct configfs_subsystem *cg_subsys;\n\tstruct list_head default_groups;\n\tstruct list_head group_entry;\n};\n\nstruct configfs_item_operations;\n\nstruct configfs_group_operations;\n\nstruct configfs_attribute;\n\nstruct configfs_bin_attribute;\n\nstruct config_item_type {\n\tstruct module *ct_owner;\n\tconst struct configfs_item_operations *ct_item_ops;\n\tconst struct configfs_group_operations *ct_group_ops;\n\tstruct configfs_attribute **ct_attrs;\n\tstruct configfs_bin_attribute **ct_bin_attrs;\n};\n\nstruct configfs_attribute {\n\tconst char *ca_name;\n\tstruct module *ca_owner;\n\tumode_t ca_mode;\n\tssize_t (*show)(struct config_item *, char *);\n\tssize_t (*store)(struct config_item *, const char *, size_t);\n};\n\nstruct configfs_bin_attribute {\n\tstruct configfs_attribute cb_attr;\n\tvoid *cb_private;\n\tsize_t cb_max_size;\n\tssize_t (*read)(struct config_item *, void *, size_t);\n\tssize_t (*write)(struct config_item *, const void *, size_t);\n};\n\nstruct configfs_group_operations {\n\tstruct config_item * (*make_item)(struct config_group *, const char *);\n\tstruct config_group * (*make_group)(struct config_group *, const char *);\n\tvoid (*disconnect_notify)(struct config_group *, struct config_item *);\n\tvoid (*drop_item)(struct config_group *, struct config_item *);\n\tbool (*is_visible)(struct config_item *, struct configfs_attribute *, int);\n\tbool (*is_bin_visible)(struct config_item *, struct configfs_bin_attribute *, int);\n};\n\nstruct configfs_item_operations {\n\tvoid (*release)(struct config_item *);\n\tint (*allow_link)(struct config_item *, struct config_item *);\n\tvoid (*drop_link)(struct config_item *, struct config_item *);\n};\n\nstruct configfs_subsystem {\n\tstruct config_group su_group;\n\tstruct mutex su_mutex;\n};\n\nstruct connect_timeout_data {\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct console;\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct;\n\nstruct console___2 {\n\tstruct list_head list;\n\tstruct hvc_struct *hvc;\n\tstruct winsize ws;\n\tu32 vtermno;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct ebitmap_node;\n\nstruct ebitmap {\n\tstruct ebitmap_node *node;\n\tu32 highbit;\n};\n\nstruct type_set;\n\nstruct constraint_expr {\n\tu32 expr_type;\n\tu32 attr;\n\tu32 op;\n\tstruct ebitmap names;\n\tstruct type_set *type_names;\n\tstruct constraint_expr *next;\n};\n\nstruct constraint_node {\n\tu32 permissions;\n\tstruct constraint_expr *expr;\n\tstruct constraint_node *next;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n};\n\nstruct mls_level {\n\tu32 sens;\n\tstruct ebitmap cat;\n};\n\nstruct mls_range {\n\tstruct mls_level level[2];\n};\n\nstruct context {\n\tu32 user;\n\tu32 role;\n\tu32 type;\n\tu32 len;\n\tstruct mls_range range;\n\tchar *str;\n};\n\nstruct context_tracking {\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct virtio_net_ctrl_hdr {\n\t__u8 class;\n\t__u8 cmd;\n};\n\nstruct control_buf {\n\tstruct virtio_net_ctrl_hdr hdr;\n\tvirtio_net_ctrl_ack status;\n};\n\nstruct convert_context_args {\n\tstruct policydb *oldp;\n\tstruct policydb *newp;\n};\n\nstruct cooling_spec {\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tunsigned int weight;\n};\n\nstruct copy_subpage_arg {\n\tstruct folio *dst;\n\tstruct folio *src;\n\tstruct vm_area_struct *vma;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct counted_str {\n\tstruct kref count;\n\tchar name[0];\n};\n\nstruct regulator_dev;\n\nstruct regulator_coupler;\n\nstruct coupling_desc {\n\tstruct regulator_dev **coupled_rdevs;\n\tstruct regulator_coupler *coupler;\n\tint n_resolved;\n\tint n_coupled;\n};\n\nstruct cpc_reg {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct cpc_register_resource {\n\tacpi_object_type type;\n\tu64 *sys_mem_vaddr;\n\tunion {\n\t\tstruct cpc_reg reg;\n\t\tu64 int_value;\n\t} cpc_entry;\n};\n\nstruct cpc_desc {\n\tint num_entries;\n\tint version;\n\tint cpu_id;\n\tint write_cmd_status;\n\tint write_cmd_id;\n\traw_spinlock_t rmw_lock;\n\tstruct cpc_register_resource cpc_regs[21];\n\tstruct acpi_psd_package domain_info;\n\tstruct kobject kobj;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cppc_perf_caps {\n\tu32 guaranteed_perf;\n\tu32 highest_perf;\n\tu32 nominal_perf;\n\tu32 lowest_perf;\n\tu32 lowest_nonlinear_perf;\n\tu32 lowest_freq;\n\tu32 nominal_freq;\n};\n\nstruct cppc_perf_ctrls {\n\tu32 max_perf;\n\tu32 min_perf;\n\tu32 desired_perf;\n\tu32 energy_perf;\n\tbool auto_sel;\n};\n\nstruct cppc_perf_fb_ctrs {\n\tu64 reference;\n\tu64 delivered;\n\tu64 reference_perf;\n\tu64 wraparound_time;\n};\n\nstruct cppc_cpudata {\n\tstruct cppc_perf_caps perf_caps;\n\tstruct cppc_perf_ctrls perf_ctrls;\n\tstruct cppc_perf_fb_ctrs perf_fb_ctrs;\n\tunsigned int shared_type;\n\tcpumask_var_t shared_cpu_map;\n};\n\nstruct pcc_mbox_chan;\n\nstruct cppc_pcc_data {\n\tstruct pcc_mbox_chan *pcc_channel;\n\tbool pcc_channel_acquired;\n\tunsigned int deadline_us;\n\tunsigned int pcc_mpar;\n\tunsigned int pcc_mrtt;\n\tunsigned int pcc_nominal;\n\tbool pending_pcc_write_cmd;\n\tbool platform_owns_pcc;\n\tunsigned int pcc_write_cnt;\n\tstruct rw_semaphore pcc_lock;\n\twait_queue_head_t pcc_write_wait_q;\n\tktime_t last_cmd_cmpl_time;\n\tktime_t last_mpar_reset;\n\tint mpar_count;\n\tint refcount;\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct update_util_data {\n\tvoid (*func)(struct update_util_data *, u64, unsigned int);\n};\n\nstruct policy_dbs_info;\n\nstruct cpu_dbs_info {\n\tu64 prev_cpu_idle;\n\tu64 prev_update_time;\n\tu64 prev_cpu_nice;\n\tunsigned int prev_load;\n\tstruct update_util_data update_util;\n\tstruct policy_dbs_info *policy_dbs;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct cpu_hw_events {\n\tint n_events;\n\tint irq;\n\tstruct perf_event *events[64];\n\tlong unsigned int used_hw_ctrs[1];\n\tlong unsigned int used_fw_ctrs[1];\n\tvoid *snapshot_addr;\n\tphys_addr_t snapshot_addr_phys;\n\tbool snapshot_set_done;\n\tu64 snapshot_cval_shcopy[64];\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_manufacturer_info_t {\n\tlong unsigned int vendor_id;\n\tlong unsigned int arch_id;\n\tlong unsigned int imp_id;\n\tvoid (*patch_func)(struct alt_entry *, struct alt_entry *, long unsigned int, long unsigned int, unsigned int);\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_operations {\n\tint (*cpu_start)(unsigned int, struct task_struct *);\n\tvoid (*cpu_stop)(void);\n\tint (*cpu_is_stopped)(unsigned int);\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_smt_info {\n\tunsigned int thread_num;\n\tint core_id;\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_topology {\n\tint thread_id;\n\tint core_id;\n\tint cluster_id;\n\tint package_id;\n\tcpumask_t thread_sibling;\n\tcpumask_t core_sibling;\n\tcpumask_t cluster_sibling;\n\tcpumask_t llc_sibling;\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct kernel_cpustat;\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tu64 *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct thermal_cooling_device_ops {\n\tint (*get_max_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*get_cur_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*set_cur_state)(struct thermal_cooling_device *, long unsigned int);\n\tint (*get_requested_power)(struct thermal_cooling_device *, u32 *);\n\tint (*state2power)(struct thermal_cooling_device *, long unsigned int, u32 *);\n\tint (*power2state)(struct thermal_cooling_device *, u32, long unsigned int *);\n};\n\nstruct em_perf_domain;\n\nstruct cpufreq_policy;\n\nstruct cpufreq_cooling_device {\n\tu32 last_load;\n\tunsigned int cpufreq_state;\n\tunsigned int max_level;\n\tstruct em_perf_domain *em;\n\tstruct cpufreq_policy *policy;\n\tstruct thermal_cooling_device_ops cooling_ops;\n\tstruct freq_qos_request qos_req;\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_policy_data;\n\nstruct freq_attr;\n\nstruct cpufreq_driver {\n\tchar name[16];\n\tu16 flags;\n\tvoid *driver_data;\n\tint (*init)(struct cpufreq_policy *);\n\tint (*verify)(struct cpufreq_policy_data *);\n\tint (*setpolicy)(struct cpufreq_policy *);\n\tint (*target)(struct cpufreq_policy *, unsigned int, unsigned int);\n\tint (*target_index)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*fast_switch)(struct cpufreq_policy *, unsigned int);\n\tvoid (*adjust_perf)(unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get)(unsigned int);\n\tvoid (*update_limits)(struct cpufreq_policy *);\n\tint (*bios_limit)(int, unsigned int *);\n\tint (*online)(struct cpufreq_policy *);\n\tint (*offline)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n\tvoid (*ready)(struct cpufreq_policy *);\n\tstruct freq_attr **attr;\n\tbool boost_enabled;\n\tint (*set_boost)(struct cpufreq_policy *, int);\n\tvoid (*register_em)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_dt_platform_data {\n\tbool have_governor_per_policy;\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_freqs {\n\tstruct cpufreq_policy *policy;\n\tunsigned int old;\n\tunsigned int new;\n\tu8 flags;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tstruct list_head governor_list;\n\tstruct module *owner;\n\tu8 flags;\n};\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_read_t;\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_write_t;\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct cpufreq_stats;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tbool strict_target;\n\tbool efficiencies_available;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tbool boost_enabled;\n\tbool boost_supported;\n\tunsigned int cached_target_freq;\n\tunsigned int cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpufreq_policy_data {\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tstruct cpufreq_frequency_table *freq_table;\n\tunsigned int cpu;\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct cpufreq_stats {\n\tunsigned int total_trans;\n\tlong long unsigned int last_time;\n\tunsigned int max_state;\n\tunsigned int state_num;\n\tunsigned int last_index;\n\tu64 *time_in_state;\n\tunsigned int *freq_table;\n\tunsigned int *trans_table;\n\tunsigned int reset_pending;\n\tlong long unsigned int reset_time;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nstruct cpuidle_device;\n\nstruct cpuidle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_device *, char *);\n\tssize_t (*store)(struct cpuidle_device *, const char *, size_t);\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct cpuidle_device_kobj {\n\tstruct cpuidle_device *dev;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct cpuidle_driver_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_driver *, char *);\n\tssize_t (*store)(struct cpuidle_driver *, const char *, size_t);\n};\n\nstruct cpuidle_driver_kobj {\n\tstruct cpuidle_driver *drv;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_governor {\n\tchar name[16];\n\tstruct list_head governor_list;\n\tunsigned int rating;\n\tint (*enable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tvoid (*disable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tint (*select)(struct cpuidle_driver *, struct cpuidle_device *, bool *);\n\tvoid (*reflect)(struct cpuidle_device *, int);\n};\n\nstruct cpuidle_state_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_state *, struct cpuidle_state_usage *, char *);\n\tssize_t (*store)(struct cpuidle_state *, struct cpuidle_state_usage *, const char *, size_t);\n};\n\nstruct cpuidle_state_kobj {\n\tstruct cpuidle_state *state;\n\tstruct cpuidle_state_usage *state_usage;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n\tstruct cpuidle_device *device;\n};\n\nstruct cpumap {\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int managed_allocated;\n\tbool initialized;\n\tbool online;\n\tlong unsigned int *managed_map;\n\tlong unsigned int alloc_map[0];\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct cqhci_host_ops;\n\nstruct mmc_host;\n\nstruct cqhci_slot;\n\nstruct cqhci_host {\n\tconst struct cqhci_host_ops *ops;\n\tvoid *mmio;\n\tstruct mmc_host *mmc;\n\tspinlock_t lock;\n\tunsigned int rca;\n\tbool dma64;\n\tint num_slots;\n\tint qcnt;\n\tu32 dcmd_slot;\n\tu32 caps;\n\tu32 quirks;\n\tbool enabled;\n\tbool halted;\n\tbool init_done;\n\tbool activated;\n\tbool waiting_for_idle;\n\tbool recovery_halt;\n\tsize_t desc_size;\n\tsize_t data_size;\n\tu8 *desc_base;\n\tu8 slot_sz;\n\tu8 task_desc_len;\n\tu8 link_desc_len;\n\tu8 *trans_desc_base;\n\tu8 trans_desc_len;\n\tdma_addr_t desc_dma_base;\n\tdma_addr_t trans_desc_dma_base;\n\tstruct completion halt_comp;\n\twait_queue_head_t wait_queue;\n\tstruct cqhci_slot *slot;\n};\n\nstruct mmc_request;\n\nstruct cqhci_host_ops {\n\tvoid (*dumpregs)(struct mmc_host *);\n\tvoid (*write_l)(struct cqhci_host *, u32, int);\n\tu32 (*read_l)(struct cqhci_host *, int);\n\tvoid (*enable)(struct mmc_host *);\n\tvoid (*disable)(struct mmc_host *, bool);\n\tvoid (*update_dcmd_desc)(struct mmc_host *, struct mmc_request *, u64 *);\n\tvoid (*pre_enable)(struct mmc_host *);\n\tvoid (*post_disable)(struct mmc_host *);\n\tvoid (*set_tran_desc)(struct cqhci_host *, u8 **, dma_addr_t, int, bool, bool);\n};\n\nstruct cqhci_slot {\n\tstruct mmc_request *mrq;\n\tunsigned int flags;\n};\n\nstruct crc_clmul_consts {\n\tlong unsigned int fold_across_2_longs_const_hi;\n\tlong unsigned int fold_across_2_longs_const_lo;\n\tlong unsigned int barrett_reduction_const_1;\n\tlong unsigned int barrett_reduction_const_2;\n};\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tvoid *security;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct cred_label {\n\tconst struct cred *cred;\n\tstruct aa_label *label;\n};\n\nstruct cred_security_struct {\n\tu32 osid;\n\tu32 sid;\n\tu32 exec_sid;\n\tu32 create_sid;\n\tu32 keycreate_sid;\n\tu32 sockcreate_sid;\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct crs_csi2 {\n\tstruct list_head entry;\n\tacpi_handle handle;\n\tstruct acpi_device_software_nodes *swnodes;\n\tstruct list_head connections;\n\tu32 port_count;\n};\n\nstruct crs_csi2_connection {\n\tstruct list_head entry;\n\tstruct acpi_resource_csi2_serialbus csi2_data;\n\tacpi_handle remote_handle;\n\tchar remote_name[0];\n};\n\nstruct crypto_alg;\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct csi2_resources_walk_data {\n\tacpi_handle handle;\n\tstruct list_head connections;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[12];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[12];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct cv1800_clk_common {\n\tvoid *base;\n\tspinlock_t *lock;\n\tstruct clk_hw hw;\n\tlong unsigned int features;\n};\n\nstruct cv1800_clk_regbit {\n\tu16 reg;\n\ts8 shift;\n};\n\nstruct cv1800_clk_regfield {\n\tu16 reg;\n\tu8 shift;\n\tu8 width;\n\ts16 initval;\n\tlong unsigned int flags;\n};\n\nstruct cv1800_clk_audio {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit src_en;\n\tstruct cv1800_clk_regbit output_en;\n\tstruct cv1800_clk_regbit div_en;\n\tstruct cv1800_clk_regbit div_up;\n\tstruct cv1800_clk_regfield m;\n\tstruct cv1800_clk_regfield n;\n\tu32 target_rate;\n};\n\nstruct cv1800_clk_div {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n\tstruct cv1800_clk_regfield div;\n};\n\nstruct cv1800_clk_bypass_div {\n\tstruct cv1800_clk_div div;\n\tstruct cv1800_clk_regbit bypass;\n};\n\nstruct cv1800_clk_mux {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n\tstruct cv1800_clk_regfield div;\n\tstruct cv1800_clk_regfield mux;\n};\n\nstruct cv1800_clk_bypass_mux {\n\tstruct cv1800_clk_mux mux;\n\tstruct cv1800_clk_regbit bypass;\n};\n\nstruct cv1800_clk_desc;\n\nstruct cv1800_clk_ctrl {\n\tconst struct cv1800_clk_desc *desc;\n\tspinlock_t lock;\n};\n\nstruct cv1800_clk_desc {\n\tstruct clk_hw_onecell_data *clks_data;\n\tint (*pre_init)(struct device *, void *, struct cv1800_clk_ctrl *, const struct cv1800_clk_desc *);\n};\n\nstruct cv1800_clk_gate {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n};\n\nstruct cv1800_clk_mmux {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n\tstruct cv1800_clk_regfield div[2];\n\tstruct cv1800_clk_regfield mux[2];\n\tstruct cv1800_clk_regbit bypass;\n\tstruct cv1800_clk_regbit clk_sel;\n\tconst s8 *parent2sel;\n\tconst u8 *sel2parent[2];\n};\n\nstruct cv1800_clk_pll_limit;\n\nstruct cv1800_clk_pll_synthesizer;\n\nstruct cv1800_clk_pll {\n\tstruct cv1800_clk_common common;\n\tu32 pll_reg;\n\tstruct cv1800_clk_regbit pll_pwd;\n\tstruct cv1800_clk_regbit pll_status;\n\tconst struct cv1800_clk_pll_limit *pll_limit;\n\tstruct cv1800_clk_pll_synthesizer *pll_syn;\n};\n\nstruct cv1800_clk_pll_limit {\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} pre_div;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} div;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} post_div;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} ictrl;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} mode;\n};\n\nstruct cv1800_clk_pll_synthesizer {\n\tstruct cv1800_clk_regbit en;\n\tstruct cv1800_clk_regbit clk_half;\n\tu32 ctrl;\n\tu32 set;\n};\n\nstruct sophgo_pin {\n\tu16 id;\n\tu16 flags;\n};\n\nstruct cv1800_pinmux {\n\tu16 offset;\n\tu8 area;\n\tu8 max;\n};\n\nstruct cv1800_pinmux2 {\n\tu16 offset;\n\tu8 area;\n\tu8 max;\n\tu8 pfunc;\n};\n\nstruct cv1800_pinconf {\n\tu16 offset;\n\tu8 area;\n};\n\nstruct cv1800_pin {\n\tstruct sophgo_pin pin;\n\tu8 power_domain;\n\tstruct cv1800_pinmux mux;\n\tstruct cv1800_pinmux2 mux2;\n\tstruct cv1800_pinconf conf;\n};\n\nstruct cv1800_priv {\n\tu32 *power_cfg;\n\tvoid *regs[2];\n};\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct snd_soc_dapm_widget;\n\nstruct snd_soc_dapm_widget_list;\n\nstruct dapm_kcontrol_data {\n\tunsigned int value;\n\tstruct snd_soc_dapm_widget *widget;\n\tstruct list_head paths;\n\tstruct snd_soc_dapm_widget_list *wlist;\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct dax_operations;\n\nstruct dax_holder_operations;\n\nstruct dax_device {\n\tstruct inode inode;\n\tstruct cdev cdev;\n\tvoid *private;\n\tlong unsigned int flags;\n\tconst struct dax_operations *ops;\n\tvoid *holder_data;\n\tconst struct dax_holder_operations *holder_ops;\n};\n\nstruct dev_dax;\n\nstruct dax_device_driver {\n\tstruct device_driver drv;\n\tstruct list_head ids;\n\tenum dax_driver_type type;\n\tint (*probe)(struct dev_dax *);\n\tvoid (*remove)(struct dev_dax *);\n};\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct dax_id {\n\tstruct list_head list;\n\tchar dev_name[30];\n};\n\nstruct dax_mapping {\n\tstruct device dev;\n\tint range_id;\n\tint id;\n};\n\nstruct dax_operations {\n\tlong int (*direct_access)(struct dax_device *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\tint (*zero_page_range)(struct dax_device *, long unsigned int, size_t);\n\tsize_t (*recovery_write)(struct dax_device *, long unsigned int, void *, size_t, struct iov_iter *);\n};\n\nstruct dax_region {\n\tint id;\n\tint target_node;\n\tstruct kref kref;\n\tstruct device *dev;\n\tunsigned int align;\n\tstruct ida ida;\n\tstruct resource res;\n\tstruct device *seed;\n\tstruct device *youngest;\n};\n\nstruct xhci_dbc;\n\nstruct dbc_driver {\n\tint (*configure)(struct xhci_dbc *);\n\tvoid (*disconnect)(struct xhci_dbc *);\n};\n\nstruct xhci_ring;\n\nstruct dbc_ep {\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tstruct xhci_ring *ring;\n\tunsigned int direction: 1;\n\tunsigned int halted: 1;\n};\n\nstruct dbc_regs {\n\t__le32 capability;\n\t__le32 doorbell;\n\t__le32 ersts;\n\t__le32 __reserved_0;\n\t__le64 erstba;\n\t__le64 erdp;\n\t__le32 control;\n\t__le32 status;\n\t__le32 portsc;\n\t__le32 __reserved_1;\n\t__le64 dccp;\n\t__le32 devinfo1;\n\t__le32 devinfo2;\n};\n\nunion xhci_trb;\n\nstruct dbc_request {\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tvoid (*complete)(struct xhci_dbc *, struct dbc_request *);\n\tstruct list_head list_pool;\n\tint status;\n\tunsigned int actual;\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tdma_addr_t trb_dma;\n\tunion xhci_trb *trb;\n\tunsigned int direction: 1;\n};\n\nstruct dbc_str {\n\tchar manufacturer[127];\n\tchar product[127];\n\tchar serial[127];\n};\n\nstruct dbc_str_descs {\n\tchar string0[254];\n\tchar manufacturer[254];\n\tchar product[254];\n\tchar serial[254];\n};\n\nstruct gov_attr_set {\n\tstruct kobject kobj;\n\tstruct list_head policy_list;\n\tstruct mutex update_lock;\n\tint usage_count;\n};\n\nstruct dbs_governor;\n\nstruct dbs_data {\n\tstruct gov_attr_set attr_set;\n\tstruct dbs_governor *gov;\n\tvoid *tuners;\n\tunsigned int ignore_nice_load;\n\tunsigned int sampling_rate;\n\tunsigned int sampling_down_factor;\n\tunsigned int up_threshold;\n\tunsigned int io_is_busy;\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct dbs_governor {\n\tstruct cpufreq_governor gov;\n\tstruct kobj_type kobj_type;\n\tstruct dbs_data *gdbs_data;\n\tunsigned int (*gov_dbs_update)(struct cpufreq_policy *);\n\tstruct policy_dbs_info * (*alloc)(void);\n\tvoid (*free)(struct policy_dbs_info *);\n\tint (*init)(struct dbs_data *);\n\tvoid (*exit)(struct dbs_data *);\n\tvoid (*start)(struct cpufreq_policy *);\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct ohci_hcd;\n\nstruct debug_buffer {\n\tssize_t (*fill_func)(struct debug_buffer *);\n\tstruct ohci_hcd *ohci;\n\tstruct mutex mutex;\n\tsize_t count;\n\tchar *page;\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\nstruct debugfs_info {\n\tstruct dentry *debug_dir;\n\tvoid *rasdes_info;\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct demotion_nodes {\n\tnodemask_t preferred;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nunion shortname_store {\n\tunsigned char string[40];\n\tlong unsigned int words[5];\n};\n\nstruct lockref {\n\tunion {\n\t\t__u64 lock_count;\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_info_args {\n\tint parent_ino;\n\tint dname_len;\n\tint ino;\n\tint inode_len;\n\tchar *dname;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 64;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct dev_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head exceptions;\n\tenum devcg_behavior behavior;\n};\n\nstruct dev_pagemap;\n\nstruct dev_dax_range;\n\nstruct dev_dax {\n\tstruct dax_region *region;\n\tstruct dax_device *dax_dev;\n\tunsigned int align;\n\tint target_node;\n\tbool dyn_id;\n\tint id;\n\tstruct ida ida;\n\tstruct device dev;\n\tstruct dev_pagemap *pgmap;\n\tbool memmap_on_memory;\n\tint nr_range;\n\tstruct dev_dax_range *ranges;\n};\n\nstruct dev_dax_data {\n\tstruct dax_region *dax_region;\n\tstruct dev_pagemap *pgmap;\n\tresource_size_t size;\n\tint id;\n\tbool memmap_on_memory;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct dev_dax_range {\n\tlong unsigned int pgoff;\n\tstruct range range;\n\tstruct dax_mapping *mapping;\n};\n\nstruct dev_exception_item {\n\tu32 major;\n\tu32 minor;\n\tshort int type;\n\tshort int access;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct iommu_device;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n\tu32 max_pasids;\n\tu32 attach_deferred: 1;\n\tu32 pci_32bit_workaround: 1;\n\tu32 require_direct: 1;\n\tu32 shadow_on_flush: 1;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct dev_pin_info {\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *default_state;\n\tstruct pinctrl_state *init_state;\n\tstruct pinctrl_state *sleep_state;\n\tstruct pinctrl_state *idle_state;\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct dev_pm_domain_attach_data {\n\tconst char * const *pd_names;\n\tconst u32 num_pd_names;\n\tconst u32 pd_flags;\n};\n\nstruct device_link;\n\nstruct dev_pm_domain_list {\n\tstruct device **pd_devs;\n\tstruct device_link **pd_links;\n\tu32 *opp_tokens;\n\tu32 num_pds;\n};\n\nstruct dev_pm_opp_supply;\n\nstruct dev_pm_opp_icc_bw;\n\nstruct opp_table;\n\nstruct dev_pm_opp {\n\tstruct list_head node;\n\tstruct kref kref;\n\tbool available;\n\tbool dynamic;\n\tbool turbo;\n\tbool suspend;\n\tbool removed;\n\tlong unsigned int *rates;\n\tunsigned int level;\n\tstruct dev_pm_opp_supply *supplies;\n\tstruct dev_pm_opp_icc_bw *bandwidth;\n\tlong unsigned int clock_latency_ns;\n\tstruct dev_pm_opp **required_opps;\n\tstruct opp_table *opp_table;\n\tstruct device_node *np;\n\tstruct dentry *dentry;\n\tconst char *of_name;\n};\n\ntypedef int (*config_clks_t)(struct device *, struct opp_table *, struct dev_pm_opp *, void *, bool);\n\ntypedef int (*config_regulators_t)(struct device *, struct dev_pm_opp *, struct dev_pm_opp *, struct regulator **, unsigned int);\n\nstruct dev_pm_opp_config {\n\tconst char * const *clk_names;\n\tconfig_clks_t config_clks;\n\tconst char *prop_name;\n\tconfig_regulators_t config_regulators;\n\tconst unsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char * const *regulator_names;\n\tstruct device *required_dev;\n\tunsigned int required_dev_index;\n};\n\nstruct dev_pm_opp_data {\n\tbool turbo;\n\tunsigned int level;\n\tlong unsigned int freq;\n\tlong unsigned int u_volt;\n};\n\nstruct dev_pm_opp_icc_bw {\n\tu32 avg;\n\tu32 peak;\n};\n\nstruct dev_pm_opp_key {\n\tlong unsigned int freq;\n\tunsigned int level;\n\tu32 bw;\n};\n\nstruct dev_pm_opp_supply {\n\tlong unsigned int u_volt;\n\tlong unsigned int u_volt_min;\n\tlong unsigned int u_volt_max;\n\tlong unsigned int u_amp;\n\tlong unsigned int u_watt;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_power_governor {\n\tbool (*system_power_down_ok)(struct dev_pm_domain *);\n\tbool (*power_down_ok)(struct dev_pm_domain *);\n\tbool (*suspend_ok)(struct device *);\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\nstruct devfreq_dev_status {\n\tlong unsigned int total_time;\n\tlong unsigned int busy_time;\n\tlong unsigned int current_frequency;\n\tvoid *private_data;\n};\n\nstruct devfreq_stats {\n\tunsigned int total_trans;\n\tunsigned int *trans_table;\n\tu64 *time_in_state;\n\tu64 last_update;\n};\n\nstruct devfreq_dev_profile;\n\nstruct devfreq_governor;\n\nstruct devfreq {\n\tstruct list_head node;\n\tstruct mutex lock;\n\tstruct device dev;\n\tstruct devfreq_dev_profile *profile;\n\tconst struct devfreq_governor *governor;\n\tstruct opp_table *opp_table;\n\tstruct notifier_block nb;\n\tstruct delayed_work work;\n\tlong unsigned int *freq_table;\n\tunsigned int max_state;\n\tlong unsigned int previous_freq;\n\tstruct devfreq_dev_status last_status;\n\tvoid *data;\n\tvoid *governor_data;\n\tstruct dev_pm_qos_request user_min_freq_req;\n\tstruct dev_pm_qos_request user_max_freq_req;\n\tlong unsigned int scaling_min_freq;\n\tlong unsigned int scaling_max_freq;\n\tbool stop_polling;\n\tlong unsigned int suspend_freq;\n\tlong unsigned int resume_freq;\n\tatomic_t suspend_count;\n\tstruct devfreq_stats stats;\n\tstruct srcu_notifier_head transition_notifier_list;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct devfreq_cooling_power;\n\nstruct devfreq_cooling_device {\n\tstruct thermal_cooling_device *cdev;\n\tstruct thermal_cooling_device_ops cooling_ops;\n\tstruct devfreq *devfreq;\n\tlong unsigned int cooling_state;\n\tu32 *freq_table;\n\tsize_t max_state;\n\tstruct devfreq_cooling_power *power_ops;\n\tu32 res_util;\n\tint capped_state;\n\tstruct dev_pm_qos_request req_max_freq;\n\tstruct em_perf_domain *em_pd;\n};\n\nstruct devfreq_cooling_power {\n\tint (*get_real_power)(struct devfreq *, u32 *, long unsigned int, long unsigned int);\n};\n\nstruct devfreq_dev_profile {\n\tlong unsigned int initial_freq;\n\tunsigned int polling_ms;\n\tenum devfreq_timer timer;\n\tint (*target)(struct device *, long unsigned int *, u32);\n\tint (*get_dev_status)(struct device *, struct devfreq_dev_status *);\n\tint (*get_cur_freq)(struct device *, long unsigned int *);\n\tvoid (*exit)(struct device *);\n\tlong unsigned int *freq_table;\n\tunsigned int max_state;\n\tbool is_cooling_device;\n\tconst struct attribute_group **dev_groups;\n};\n\nstruct devfreq_freqs {\n\tlong unsigned int old;\n\tlong unsigned int new;\n};\n\nstruct devfreq_governor {\n\tstruct list_head node;\n\tconst char name[16];\n\tconst u64 attrs;\n\tconst u64 flags;\n\tint (*get_target_freq)(struct devfreq *, long unsigned int *);\n\tint (*event_handler)(struct devfreq *, unsigned int, void *);\n};\n\nstruct devfreq_notifier_devres {\n\tstruct devfreq *devfreq;\n\tstruct notifier_block *nb;\n\tunsigned int list;\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_nvdimm_bus_t;\n\ntypedef struct device *class_pm_runtime_active_auto_t;\n\ntypedef class_pm_runtime_active_auto_t class_pm_runtime_active_auto_try_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\ntypedef struct device *class_pm_runtime_noresume_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tstruct kobject kobj;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n};\n\nstruct devlink_dev_stats {\n\tu32 reload_stats[6];\n\tu32 remote_reload_stats[6];\n};\n\nstruct devlink_dpipe_headers;\n\nstruct devlink_ops;\n\nstruct devlink_rel;\n\nstruct devlink {\n\tu32 index;\n\tstruct xarray ports;\n\tstruct list_head rate_list;\n\tstruct list_head sb_list;\n\tstruct list_head dpipe_table_list;\n\tstruct list_head resource_list;\n\tstruct xarray params;\n\tstruct list_head region_list;\n\tstruct list_head reporter_list;\n\tstruct devlink_dpipe_headers *dpipe_headers;\n\tstruct list_head trap_list;\n\tstruct list_head trap_group_list;\n\tstruct list_head trap_policer_list;\n\tstruct list_head linecard_list;\n\tconst struct devlink_ops *ops;\n\tstruct xarray snapshot_ids;\n\tstruct devlink_dev_stats stats;\n\tstruct device *dev;\n\tpossible_net_t _net;\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tu8 reload_failed: 1;\n\trefcount_t refcount;\n\tstruct rcu_work rwork;\n\tstruct devlink_rel *rel;\n\tstruct xarray nested_rels;\n\tchar priv[0];\n};\n\nstruct devlink_dpipe_header;\n\nstruct devlink_dpipe_action {\n\tenum devlink_dpipe_action_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct genl_info;\n\nstruct devlink_dpipe_dump_ctx {\n\tstruct genl_info *info;\n\tenum devlink_command cmd;\n\tstruct sk_buff *skb;\n\tstruct nlattr *nest;\n\tvoid *hdr;\n};\n\nstruct devlink_dpipe_value;\n\nstruct devlink_dpipe_entry {\n\tu64 index;\n\tstruct devlink_dpipe_value *match_values;\n\tunsigned int match_values_count;\n\tstruct devlink_dpipe_value *action_values;\n\tunsigned int action_values_count;\n\tu64 counter;\n\tbool counter_valid;\n};\n\nstruct devlink_dpipe_field {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int bitwidth;\n\tenum devlink_dpipe_field_mapping_type mapping_type;\n};\n\nstruct devlink_dpipe_header {\n\tconst char *name;\n\tunsigned int id;\n\tstruct devlink_dpipe_field *fields;\n\tunsigned int fields_count;\n\tbool global;\n};\n\nstruct devlink_dpipe_headers {\n\tstruct devlink_dpipe_header **headers;\n\tunsigned int headers_count;\n};\n\nstruct devlink_dpipe_match {\n\tenum devlink_dpipe_match_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct devlink_dpipe_table_ops;\n\nstruct devlink_dpipe_table {\n\tvoid *priv;\n\tstruct list_head list;\n\tconst char *name;\n\tbool counters_enabled;\n\tbool counter_control_extern;\n\tbool resource_valid;\n\tu64 resource_id;\n\tu64 resource_units;\n\tconst struct devlink_dpipe_table_ops *table_ops;\n\tstruct callback_head rcu;\n};\n\nstruct devlink_dpipe_table_ops {\n\tint (*actions_dump)(void *, struct sk_buff *);\n\tint (*matches_dump)(void *, struct sk_buff *);\n\tint (*entries_dump)(void *, bool, struct devlink_dpipe_dump_ctx *);\n\tint (*counters_set_update)(void *, bool);\n\tu64 (*size_get)(void *);\n};\n\nstruct devlink_dpipe_value {\n\tunion {\n\t\tstruct devlink_dpipe_action *action;\n\t\tstruct devlink_dpipe_match *match;\n\t};\n\tunsigned int mapping_value;\n\tbool mapping_valid;\n\tunsigned int value_size;\n\tvoid *value;\n\tvoid *mask;\n};\n\nstruct devlink_flash_component_lookup_ctx {\n\tconst char *lookup_name;\n\tbool lookup_name_found;\n};\n\nstruct devlink_flash_notify {\n\tconst char *status_msg;\n\tconst char *component;\n\tlong unsigned int done;\n\tlong unsigned int total;\n\tlong unsigned int timeout;\n};\n\nstruct firmware;\n\nstruct devlink_flash_update_params {\n\tconst struct firmware *fw;\n\tconst char *component;\n\tu32 overwrite_mask;\n};\n\nstruct devlink_fmsg {\n\tstruct list_head item_list;\n\tint err;\n\tbool putting_binary;\n};\n\nstruct devlink_fmsg_item {\n\tstruct list_head list;\n\tint attrtype;\n\tu8 nla_type;\n\tu16 len;\n\tint value[0];\n};\n\nstruct devlink_health_reporter_ops;\n\nstruct devlink_port;\n\nstruct devlink_health_reporter {\n\tstruct list_head list;\n\tvoid *priv;\n\tconst struct devlink_health_reporter_ops *ops;\n\tstruct devlink *devlink;\n\tstruct devlink_port *devlink_port;\n\tstruct devlink_fmsg *dump_fmsg;\n\tu64 graceful_period;\n\tu64 burst_period;\n\tbool auto_recover;\n\tbool auto_dump;\n\tu8 health_state;\n\tu64 dump_ts;\n\tu64 dump_real_ts;\n\tu64 error_count;\n\tu64 recovery_count;\n\tu64 last_recovery_ts;\n};\n\nstruct devlink_health_reporter_ops {\n\tchar *name;\n\tint (*recover)(struct devlink_health_reporter *, void *, struct netlink_ext_ack *);\n\tint (*dump)(struct devlink_health_reporter *, struct devlink_fmsg *, void *, struct netlink_ext_ack *);\n\tint (*diagnose)(struct devlink_health_reporter *, struct devlink_fmsg *, struct netlink_ext_ack *);\n\tint (*test)(struct devlink_health_reporter *, struct netlink_ext_ack *);\n\tu64 default_graceful_period;\n\tu64 default_burst_period;\n};\n\nstruct devlink_info_req {\n\tstruct sk_buff *msg;\n\tvoid (*version_cb)(const char *, enum devlink_info_version_type, void *);\n\tvoid *version_cb_priv;\n};\n\nstruct devlink_linecard_ops;\n\nstruct devlink_linecard_type;\n\nstruct devlink_linecard {\n\tstruct list_head list;\n\tstruct devlink *devlink;\n\tunsigned int index;\n\tconst struct devlink_linecard_ops *ops;\n\tvoid *priv;\n\tenum devlink_linecard_state state;\n\tstruct mutex state_lock;\n\tconst char *type;\n\tstruct devlink_linecard_type *types;\n\tunsigned int types_count;\n\tu32 rel_index;\n};\n\nstruct devlink_linecard_ops {\n\tint (*provision)(struct devlink_linecard *, void *, const char *, const void *, struct netlink_ext_ack *);\n\tint (*unprovision)(struct devlink_linecard *, void *, struct netlink_ext_ack *);\n\tbool (*same_provision)(struct devlink_linecard *, void *, const char *, const void *);\n\tunsigned int (*types_count)(struct devlink_linecard *, void *);\n\tvoid (*types_get)(struct devlink_linecard *, void *, unsigned int, const char **, const void **);\n};\n\nstruct devlink_linecard_type {\n\tconst char *type;\n\tconst void *priv;\n};\n\nstruct devlink_nl_dump_state {\n\tlong unsigned int instance;\n\tint idx;\n\tunion {\n\t\tstruct {\n\t\t\tu64 start_offset;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dump_ts;\n\t\t};\n\t};\n};\n\nstruct devlink_obj_desc;\n\nstruct devlink_nl_sock_priv {\n\tstruct devlink_obj_desc *flt;\n\tspinlock_t flt_lock;\n};\n\nstruct devlink_obj_desc {\n\tstruct callback_head rcu;\n\tconst char *bus_name;\n\tconst char *dev_name;\n\tunsigned int port_index;\n\tbool port_index_valid;\n\tlong int data[0];\n};\n\nstruct devlink_sb_pool_info;\n\nstruct devlink_trap;\n\nstruct devlink_trap_group;\n\nstruct devlink_trap_policer;\n\nstruct devlink_port_new_attrs;\n\nstruct devlink_rate;\n\nstruct devlink_ops {\n\tu32 supported_flash_update_params;\n\tlong unsigned int reload_actions;\n\tlong unsigned int reload_limits;\n\tint (*reload_down)(struct devlink *, bool, enum devlink_reload_action, enum devlink_reload_limit, struct netlink_ext_ack *);\n\tint (*reload_up)(struct devlink *, enum devlink_reload_action, enum devlink_reload_limit, u32 *, struct netlink_ext_ack *);\n\tint (*sb_pool_get)(struct devlink *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*sb_pool_set)(struct devlink *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*sb_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *);\n\tint (*sb_port_pool_set)(struct devlink_port *, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_tc_pool_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*sb_tc_pool_bind_set)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_occ_snapshot)(struct devlink *, unsigned int);\n\tint (*sb_occ_max_clear)(struct devlink *, unsigned int);\n\tint (*sb_occ_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *, u32 *);\n\tint (*sb_occ_tc_port_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*eswitch_mode_get)(struct devlink *, u16 *);\n\tint (*eswitch_mode_set)(struct devlink *, u16, struct netlink_ext_ack *);\n\tint (*eswitch_inline_mode_get)(struct devlink *, u8 *);\n\tint (*eswitch_inline_mode_set)(struct devlink *, u8, struct netlink_ext_ack *);\n\tint (*eswitch_encap_mode_get)(struct devlink *, enum devlink_eswitch_encap_mode *);\n\tint (*eswitch_encap_mode_set)(struct devlink *, enum devlink_eswitch_encap_mode, struct netlink_ext_ack *);\n\tint (*info_get)(struct devlink *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*flash_update)(struct devlink *, struct devlink_flash_update_params *, struct netlink_ext_ack *);\n\tint (*trap_init)(struct devlink *, const struct devlink_trap *, void *);\n\tvoid (*trap_fini)(struct devlink *, const struct devlink_trap *, void *);\n\tint (*trap_action_set)(struct devlink *, const struct devlink_trap *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_group_init)(struct devlink *, const struct devlink_trap_group *);\n\tint (*trap_group_set)(struct devlink *, const struct devlink_trap_group *, const struct devlink_trap_policer *, struct netlink_ext_ack *);\n\tint (*trap_group_action_set)(struct devlink *, const struct devlink_trap_group *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_drop_counter_get)(struct devlink *, const struct devlink_trap *, u64 *);\n\tint (*trap_policer_init)(struct devlink *, const struct devlink_trap_policer *);\n\tvoid (*trap_policer_fini)(struct devlink *, const struct devlink_trap_policer *);\n\tint (*trap_policer_set)(struct devlink *, const struct devlink_trap_policer *, u64, u64, struct netlink_ext_ack *);\n\tint (*trap_policer_counter_get)(struct devlink *, const struct devlink_trap_policer *, u64 *);\n\tint (*port_new)(struct devlink *, const struct devlink_port_new_attrs *, struct netlink_ext_ack *, struct devlink_port **);\n\tint (*rate_leaf_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_new)(struct devlink_rate *, void **, struct netlink_ext_ack *);\n\tint (*rate_node_del)(struct devlink_rate *, void *, struct netlink_ext_ack *);\n\tint (*rate_leaf_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tint (*rate_node_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tbool (*selftest_check)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n\tenum devlink_selftest_status (*selftest_run)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n};\n\nstruct devlink_param_gset_ctx;\n\nunion devlink_param_value;\n\nstruct devlink_param {\n\tu32 id;\n\tconst char *name;\n\tbool generic;\n\tenum devlink_param_type type;\n\tlong unsigned int supported_cmodes;\n\tint (*get)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*set)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*validate)(struct devlink *, u32, union devlink_param_value, struct netlink_ext_ack *);\n\tint (*get_default)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*reset_default)(struct devlink *, u32, enum devlink_param_cmode, struct netlink_ext_ack *);\n};\n\nunion devlink_param_value {\n\tu8 vu8;\n\tu16 vu16;\n\tu32 vu32;\n\tu64 vu64;\n\tchar vstr[32];\n\tbool vbool;\n};\n\nstruct devlink_param_gset_ctx {\n\tunion devlink_param_value val;\n\tenum devlink_param_cmode cmode;\n};\n\nstruct devlink_param_item {\n\tstruct list_head list;\n\tconst struct devlink_param *param;\n\tunion devlink_param_value driverinit_value;\n\tbool driverinit_value_valid;\n\tunion devlink_param_value driverinit_value_new;\n\tbool driverinit_value_new_valid;\n\tunion devlink_param_value driverinit_default;\n};\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_port_ops;\n\nstruct ib_device;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct devlink_port_new_attrs {\n\tenum devlink_port_flavour flavour;\n\tunsigned int port_index;\n\tu32 controller;\n\tu32 sfnum;\n\tu16 pfnum;\n\tu8 port_index_valid: 1;\n\tu8 controller_valid: 1;\n\tu8 sfnum_valid: 1;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_port_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n};\n\nstruct devlink_region_ops;\n\nstruct devlink_region {\n\tstruct devlink *devlink;\n\tstruct devlink_port *port;\n\tstruct list_head list;\n\tunion {\n\t\tconst struct devlink_region_ops *ops;\n\t\tconst struct devlink_port_region_ops *port_ops;\n\t};\n\tstruct mutex snapshot_lock;\n\tstruct list_head snapshot_list;\n\tu32 max_snapshots;\n\tu32 cur_snapshots;\n\tu64 size;\n};\n\nstruct devlink_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\ntypedef void devlink_rel_notify_cb_t(struct devlink *, u32);\n\ntypedef void devlink_rel_cleanup_cb_t(struct devlink *, u32, u32);\n\nstruct devlink_rel {\n\tu32 index;\n\trefcount_t refcount;\n\tu32 devlink_index;\n\tstruct {\n\t\tu32 devlink_index;\n\t\tu32 obj_index;\n\t\tdevlink_rel_notify_cb_t *notify_cb;\n\t\tdevlink_rel_cleanup_cb_t *cleanup_cb;\n\t\tstruct delayed_work notify_work;\n\t} nested_in;\n};\n\nstruct devlink_reload_combination {\n\tenum devlink_reload_action action;\n\tenum devlink_reload_limit limit;\n};\n\nstruct devlink_resource_size_params {\n\tu64 size_min;\n\tu64 size_max;\n\tu64 size_granularity;\n\tenum devlink_resource_unit unit;\n};\n\ntypedef u64 devlink_resource_occ_get_t(void *);\n\nstruct devlink_resource {\n\tconst char *name;\n\tu64 id;\n\tu64 size;\n\tu64 size_new;\n\tbool size_valid;\n\tstruct devlink_resource *parent;\n\tstruct devlink_resource_size_params size_params;\n\tstruct list_head list;\n\tstruct list_head resource_list;\n\tdevlink_resource_occ_get_t *occ_get;\n\tvoid *occ_get_priv;\n};\n\nstruct devlink_sb {\n\tstruct list_head list;\n\tunsigned int index;\n\tu32 size;\n\tu16 ingress_pools_count;\n\tu16 egress_pools_count;\n\tu16 ingress_tc_count;\n\tu16 egress_tc_count;\n};\n\nstruct devlink_sb_pool_info {\n\tenum devlink_sb_pool_type pool_type;\n\tu32 size;\n\tenum devlink_sb_threshold_type threshold_type;\n\tu32 cell_size;\n};\n\nstruct devlink_snapshot {\n\tstruct list_head list;\n\tstruct devlink_region *region;\n\tu8 *data;\n\tu32 id;\n};\n\nstruct devlink_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct devlink_trap {\n\tenum devlink_trap_type type;\n\tenum devlink_trap_action init_action;\n\tbool generic;\n\tu16 id;\n\tconst char *name;\n\tu16 init_group_id;\n\tu32 metadata_cap;\n};\n\nstruct devlink_trap_group {\n\tconst char *name;\n\tu16 id;\n\tbool generic;\n\tu32 init_policer_id;\n};\n\nstruct devlink_trap_policer_item;\n\nstruct devlink_trap_group_item {\n\tconst struct devlink_trap_group *group;\n\tstruct devlink_trap_policer_item *policer_item;\n\tstruct list_head list;\n\tstruct devlink_stats *stats;\n};\n\nstruct devlink_trap_item {\n\tconst struct devlink_trap *trap;\n\tstruct devlink_trap_group_item *group_item;\n\tstruct list_head list;\n\tenum devlink_trap_action action;\n\tstruct devlink_stats *stats;\n\tvoid *priv;\n};\n\nstruct flow_action_cookie;\n\nstruct devlink_trap_metadata {\n\tconst char *trap_name;\n\tconst char *trap_group_name;\n\tstruct net_device *input_dev;\n\tnetdevice_tracker dev_tracker;\n\tconst struct flow_action_cookie *fa_cookie;\n\tenum devlink_trap_type trap_type;\n};\n\nstruct devlink_trap_policer {\n\tu32 id;\n\tu64 init_rate;\n\tu64 init_burst;\n\tu64 max_rate;\n\tu64 min_rate;\n\tu64 max_burst;\n\tu64 min_burst;\n};\n\nstruct devlink_trap_policer_item {\n\tconst struct devlink_trap_policer *policer;\n\tu64 rate;\n\tu64 burst;\n\tstruct list_head list;\n};\n\nstruct devm_clk_state {\n\tstruct clk *clk;\n\tvoid (*exit)(struct clk *);\n};\n\nstruct of_regulator_match;\n\nstruct devm_of_regulator_matches {\n\tstruct of_regulator_match *matches;\n\tunsigned int num_matches;\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\nstruct dio {\n\tint flags;\n\tblk_opf_t opf;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tbool is_pinned;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 64;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n\tu64 cookie;\n\tbool initialized;\n};\n\nstruct wb_domain;\n\nstruct dirty_throttle_control {\n\tstruct wb_domain *dom;\n\tstruct dirty_throttle_control *gdtc;\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct timing_entry {\n\tu32 min;\n\tu32 typ;\n\tu32 max;\n};\n\nstruct display_timing {\n\tstruct timing_entry pixelclock;\n\tstruct timing_entry hactive;\n\tstruct timing_entry hfront_porch;\n\tstruct timing_entry hback_porch;\n\tstruct timing_entry hsync_len;\n\tstruct timing_entry vactive;\n\tstruct timing_entry vfront_porch;\n\tstruct timing_entry vback_porch;\n\tstruct timing_entry vsync_len;\n\tenum display_flags flags;\n};\n\nstruct display_timings {\n\tunsigned int num_timings;\n\tunsigned int native_mode;\n\tstruct display_timing **timings;\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\nstruct dm_kobject_holder {\n\tstruct kobject kobj;\n\tstruct completion completion;\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_resv;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct dma_iova_state;\n\nstruct dma_buf_dma {\n\tstruct sg_table sgt;\n\tstruct dma_iova_state *state;\n\tsize_t size;\n};\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct dma_buf_export_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_import_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_buf_sg_table_wrapper {\n\tstruct sg_table *original;\n\tstruct sg_table wrapper;\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan *chan;\n\tstruct device device;\n\tint dev_id;\n\tbool chan_dma_dev;\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_chan_tbl_ent {\n\tstruct dma_chan *chan;\n};\n\nstruct dma_coherent_mem {\n\tvoid *virt_base;\n\tdma_addr_t device_base;\n\tlong unsigned int pfn_base;\n\tint size;\n\tlong unsigned int *bitmap;\n\tspinlock_t spinlock;\n\tbool use_dev_dma_pfn_offset;\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nstruct dma_vec;\n\nstruct dma_interleaved_template;\n\nstruct dma_slave_caps;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan *);\n\tint (*device_router_config)(struct dma_chan *);\n\tvoid (*device_free_chan_resources)(struct dma_chan *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_peripheral_dma_vec)(struct dma_chan *, const struct dma_vec *, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan *, struct dma_interleaved_template *, long unsigned int);\n\tvoid (*device_caps)(struct dma_chan *, struct dma_slave_caps *);\n\tint (*device_config)(struct dma_chan *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan *);\n\tint (*device_resume)(struct dma_chan *);\n\tint (*device_terminate_all)(struct dma_chan *);\n\tvoid (*device_synchronize)(struct dma_chan *);\n\tenum dma_status (*device_tx_status)(struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n};\n\nstruct dma_fence_array;\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n\tstruct dma_fence_array_cb callbacks[0];\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tstruct dma_fence *prev;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tunion {\n\t\tstruct dma_fence_cb cb;\n\t\tstruct irq_work work;\n\t};\n\tspinlock_t lock;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_fence_unwrap {\n\tstruct dma_fence *chain;\n\tstruct dma_fence *array;\n\tunsigned int index;\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct ww_acquire_ctx;\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tstruct dma_resv_list *fences;\n};\n\nstruct dma_resv_iter {\n\tstruct dma_resv *obj;\n\tenum dma_resv_usage usage;\n\tstruct dma_fence *fence;\n\tenum dma_resv_usage fence_usage;\n\tunsigned int index;\n\tstruct dma_resv_list *fences;\n\tunsigned int num_fences;\n\tbool is_restarted;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 num_fences;\n\tu32 max_fences;\n\tstruct dma_fence *table[0];\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_vec {\n\tdma_addr_t addr;\n\tsize_t len;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct net_devmem_dmabuf_binding;\n\nstruct dmabuf_genpool_chunk_owner {\n\tstruct net_iov_area area;\n\tstruct net_devmem_dmabuf_binding *binding;\n\tdma_addr_t base_dma_addr;\n};\n\nstruct dmabuf_iter_priv {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmaengine_desc_callback {\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n};\n\nstruct snd_soc_card;\n\nstruct snd_soc_component_driver;\n\nstruct snd_soc_dapm_context;\n\nstruct snd_compr_stream;\n\nstruct snd_soc_component {\n\tconst char *name;\n\tconst char *name_prefix;\n\tstruct device *dev;\n\tstruct snd_soc_card *card;\n\tunsigned int active;\n\tunsigned int suspended: 1;\n\tstruct list_head list;\n\tstruct list_head card_aux_list;\n\tstruct list_head card_list;\n\tconst struct snd_soc_component_driver *driver;\n\tstruct list_head dai_list;\n\tint num_dai;\n\tstruct regmap *regmap;\n\tint val_bytes;\n\tstruct mutex io_mutex;\n\tstruct list_head dobj_list;\n\tstruct snd_soc_dapm_context *dapm;\n\tint (*init)(struct snd_soc_component *);\n\tvoid *mark_module;\n\tstruct snd_pcm_substream *mark_open;\n\tstruct snd_pcm_substream *mark_hw_params;\n\tstruct snd_pcm_substream *mark_trigger;\n\tstruct snd_compr_stream *mark_compr_open;\n\tvoid *mark_pm;\n\tstruct dentry *debugfs_root;\n\tconst char *debugfs_prefix;\n};\n\nstruct snd_dmaengine_pcm_config;\n\nstruct dmaengine_pcm {\n\tstruct dma_chan *chan[2];\n\tconst struct snd_dmaengine_pcm_config *config;\n\tstruct snd_soc_component component;\n\tunsigned int flags;\n};\n\nstruct dmaengine_pcm_runtime_data {\n\tstruct dma_chan *dma_chan;\n\tdma_cookie_t cookie;\n\tunsigned int pos;\n};\n\nstruct dmaengine_unmap_data {\n\tu8 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dmaengine_unmap_pool {\n\tstruct kmem_cache *cache;\n\tconst char *name;\n\tmempool_t *pool;\n\tsize_t size;\n};\n\nstruct dmi_device {\n\tstruct list_head list;\n\tint type;\n\tconst char *name;\n\tvoid *device_data;\n};\n\nstruct dmi_dev_onboard {\n\tstruct dmi_device dev;\n\tint instance;\n\tint segment;\n\tint bus;\n\tint devfn;\n};\n\nstruct dmi_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint field;\n};\n\nstruct dmi_header {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n};\n\nstruct dmi_memdev_info {\n\tconst char *device;\n\tconst char *bank;\n\tu64 size;\n\tu16 handle;\n\tu8 type;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct dotl_iattr_map {\n\tint iattr_valid;\n\tint p9_iattr_valid;\n};\n\nstruct dotl_openflag_map {\n\tint open_flag;\n\tint dotl_flag;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct dp_sdp_header {\n\tu8 HB0;\n\tu8 HB1;\n\tu8 HB2;\n\tu8 HB3;\n};\n\nstruct dp_sdp {\n\tstruct dp_sdp_header sdp_header;\n\tu8 db[32];\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 64;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drm_dsc_rc_range_parameters {\n\tu8 range_min_qp;\n\tu8 range_max_qp;\n\tu8 range_bpg_offset;\n};\n\nstruct drm_dsc_config {\n\tu8 line_buf_depth;\n\tu8 bits_per_component;\n\tbool convert_rgb;\n\tu8 slice_count;\n\tu16 slice_width;\n\tu16 slice_height;\n\tbool simple_422;\n\tu16 pic_width;\n\tu16 pic_height;\n\tu8 rc_tgt_offset_high;\n\tu8 rc_tgt_offset_low;\n\tu16 bits_per_pixel;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_quant_incr_limit0;\n\tu16 initial_xmit_delay;\n\tu16 initial_dec_delay;\n\tbool block_pred_enable;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu16 rc_buf_thresh[14];\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n\tu16 rc_model_size;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 initial_scale_value;\n\tu16 scale_decrement_interval;\n\tu16 scale_increment_interval;\n\tu16 nfl_bpg_offset;\n\tu16 slice_bpg_offset;\n\tu16 final_offset;\n\tbool vbr_enable;\n\tu8 mux_word_size;\n\tu16 slice_chunk_size;\n\tu16 rc_bits;\n\tu8 dsc_version_minor;\n\tu8 dsc_version_major;\n\tbool native_422;\n\tbool native_420;\n\tu8 second_line_bpg_offset;\n\tu16 nsl_bpg_offset;\n\tu16 second_line_offset_adj;\n};\n\nstruct drm_dsc_picture_parameter_set {\n\tu8 dsc_version;\n\tu8 pps_identifier;\n\tu8 pps_reserved;\n\tu8 pps_3;\n\tu8 pps_4;\n\tu8 bits_per_pixel_low;\n\t__be16 pic_height;\n\t__be16 pic_width;\n\t__be16 slice_height;\n\t__be16 slice_width;\n\t__be16 chunk_size;\n\tu8 initial_xmit_delay_high;\n\tu8 initial_xmit_delay_low;\n\t__be16 initial_dec_delay;\n\tu8 pps20_reserved;\n\tu8 initial_scale_value;\n\t__be16 scale_increment_interval;\n\tu8 scale_decrement_interval_high;\n\tu8 scale_decrement_interval_low;\n\tu8 pps26_reserved;\n\tu8 first_line_bpg_offset;\n\t__be16 nfl_bpg_offset;\n\t__be16 slice_bpg_offset;\n\t__be16 initial_offset;\n\t__be16 final_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\t__be16 rc_model_size;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_tgt_offset;\n\tu8 rc_buf_thresh[14];\n\t__be16 rc_range_parameters[15];\n\tu8 native_422_420;\n\tu8 second_line_bpg_offset;\n\t__be16 nsl_bpg_offset;\n\t__be16 second_line_offset_adj;\n\tu32 pps_long_94_reserved;\n\tu32 pps_long_98_reserved;\n\tu32 pps_long_102_reserved;\n\tu32 pps_long_106_reserved;\n\tu32 pps_long_110_reserved;\n\tu32 pps_long_114_reserved;\n\tu32 pps_long_118_reserved;\n\tu32 pps_long_122_reserved;\n\t__be16 pps_short_126_reserved;\n} __attribute__((packed));\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct pci_driver;\n\nstruct pci_dev;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tlocal_lock_t bh_lock;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct dst_ops;\n\nstruct xfrm_state;\n\nstruct uncached_list;\n\nstruct lwtunnel_state;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tstruct xfrm_state *xfrm;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\trcuref_t __rcuref;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n\tstruct lwtunnel_state *lwtstate;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct uart_8250_port;\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_tx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan *rxchan;\n\tstruct dma_chan *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct dw8250_port_data {\n\tint line;\n\tstruct uart_8250_dma dma;\n\tu32 cpr_value;\n\tu8 dlf_size;\n\tbool hw_rs485_support;\n};\n\nstruct dw8250_platform_data;\n\nstruct dw8250_data {\n\tstruct dw8250_port_data data;\n\tconst struct dw8250_platform_data *pdata;\n\tu32 msr_mask_on;\n\tu32 msr_mask_off;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_notifier;\n\tstruct work_struct clk_work;\n\tstruct reset_control *rst;\n\tunsigned int skip_autocfg: 1;\n\tunsigned int uart_16550_compatible: 1;\n};\n\nstruct dw8250_platform_data {\n\tu8 usr_reg;\n\tu32 cpr_value;\n\tunsigned int quirks;\n};\n\nstruct dw_axi_dma_hcfg;\n\nstruct dw_axi_dma {\n\tstruct dma_device dma;\n\tstruct dw_axi_dma_hcfg *hdata;\n\tstruct device_dma_parameters dma_parms;\n\tstruct axi_dma_chan *chan;\n};\n\nstruct dw_axi_dma_hcfg {\n\tu32 nr_channels;\n\tu32 nr_masters;\n\tu32 m_data_width;\n\tu32 block_size[32];\n\tu32 priority[32];\n\tu32 axi_rw_burst_len;\n\tbool reg_map_8_channels;\n\tbool restrict_axi_burst_len;\n\tbool use_cfg2;\n};\n\nstruct dw_edma_region {\n\tu64 paddr;\n\tunion {\n\t\tvoid *mem;\n\t\tvoid *io;\n\t} vaddr;\n\tsize_t sz;\n};\n\nstruct dw_edma;\n\nstruct dw_edma_plat_ops;\n\nstruct dw_edma_chip {\n\tstruct device *dev;\n\tint nr_irqs;\n\tconst struct dw_edma_plat_ops *ops;\n\tu32 flags;\n\tvoid *reg_base;\n\tu16 ll_wr_cnt;\n\tu16 ll_rd_cnt;\n\tstruct dw_edma_region ll_region_wr[8];\n\tstruct dw_edma_region ll_region_rd[8];\n\tstruct dw_edma_region dt_region_wr[8];\n\tstruct dw_edma_region dt_region_rd[8];\n\tenum dw_edma_map_format mf;\n\tstruct dw_edma *dw;\n};\n\nstruct dw_edma_plat_ops {\n\tint (*irq_vector)(struct device *, unsigned int);\n\tu64 (*pci_address)(struct device *, phys_addr_t);\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n\tstruct regulator *bus_regulator;\n\tstruct dentry *debugfs;\n\tlong unsigned int addrs_in_instantiation[2];\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_gpio;\n};\n\nstruct i2c_client;\n\nstruct i2c_msg;\n\nstruct dw_i2c_dev {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct regmap *sysmap;\n\tvoid *base;\n\tvoid *ext;\n\tstruct completion cmd_complete;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct reset_control *rst;\n\tstruct i2c_client *slave;\n\tu32 (*get_clk_rate_khz)(struct dw_i2c_dev *);\n\tint cmd_err;\n\tstruct i2c_msg *msgs;\n\tint msgs_num;\n\tint msg_write_idx;\n\tu32 tx_buf_len;\n\tu8 *tx_buf;\n\tint msg_read_idx;\n\tu32 rx_buf_len;\n\tu8 *rx_buf;\n\tint msg_err;\n\tunsigned int status;\n\tunsigned int abort_source;\n\tunsigned int sw_mask;\n\tint irq;\n\tu32 flags;\n\tstruct i2c_adapter adapter;\n\tu32 functionality;\n\tu32 master_cfg;\n\tu32 slave_cfg;\n\tunsigned int tx_fifo_depth;\n\tunsigned int rx_fifo_depth;\n\tint rx_outstanding;\n\tstruct i2c_timings timings;\n\tu32 sda_hold_time;\n\tu16 ss_hcnt;\n\tu16 ss_lcnt;\n\tu16 fs_hcnt;\n\tu16 fs_lcnt;\n\tu16 fp_hcnt;\n\tu16 fp_lcnt;\n\tu16 hs_hcnt;\n\tu16 hs_lcnt;\n\tint (*acquire_lock)(void);\n\tvoid (*release_lock)(void);\n\tint semaphore_idx;\n\tbool shared_with_punit;\n\tint (*set_sda_hold_time)(struct dw_i2c_dev *);\n\tint mode;\n\tstruct i2c_bus_recovery_info rinfo;\n\tu32 bus_capacitance_pF;\n\tbool clk_freq_optimized;\n\tbool emptyfifo_hold_master;\n};\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct mmc_data;\n\nstruct uhs2_command;\n\nstruct mmc_command {\n\tu32 opcode;\n\tu32 arg;\n\tu32 resp[4];\n\tunsigned int flags;\n\tunsigned int retries;\n\tint error;\n\tunsigned int busy_timeout;\n\tstruct mmc_data *data;\n\tstruct mmc_request *mrq;\n\tstruct uhs2_command *uhs2_cmd;\n\tbool has_ext_addr;\n\tu8 ext_addr;\n};\n\nstruct dw_mci_dma_ops;\n\nstruct dw_mci_dma_slave;\n\nstruct dw_mci_board;\n\nstruct dw_mci_drv_data;\n\nstruct dw_mci_slot;\n\nstruct dw_mci {\n\tspinlock_t lock;\n\tspinlock_t irq_lock;\n\tvoid *regs;\n\tvoid *fifo_reg;\n\tu32 data_addr_override;\n\tbool wm_aligned;\n\tstruct scatterlist *sg;\n\tstruct sg_mapping_iter sg_miter;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command stop_abort;\n\tunsigned int prev_blksz;\n\tunsigned char timing;\n\tint use_dma;\n\tint using_dma;\n\tint dma_64bit_address;\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tconst struct dw_mci_dma_ops *dma_ops;\n\tunsigned int ring_size;\n\tstruct dw_mci_dma_slave *dms;\n\tresource_size_t phy_regs;\n\tu32 cmd_status;\n\tu32 data_status;\n\tu32 stop_cmdr;\n\tu32 dir_status;\n\tstruct work_struct bh_work;\n\tlong unsigned int pending_events;\n\tlong unsigned int completed_events;\n\tenum dw_mci_state state;\n\tstruct list_head queue;\n\tu32 bus_hz;\n\tu32 current_speed;\n\tu32 minimum_speed;\n\tu32 fifoth_val;\n\tu16 verid;\n\tstruct device *dev;\n\tstruct dw_mci_board *pdata;\n\tconst struct dw_mci_drv_data *drv_data;\n\tvoid *priv;\n\tstruct clk *biu_clk;\n\tstruct clk *ciu_clk;\n\tstruct dw_mci_slot *slot;\n\tint fifo_depth;\n\tint data_shift;\n\tu8 part_buf_start;\n\tu8 part_buf_count;\n\tunion {\n\t\tu16 part_buf16;\n\t\tu32 part_buf32;\n\t\tu64 part_buf;\n\t};\n\tvoid (*push_data)(struct dw_mci *, void *, int);\n\tvoid (*pull_data)(struct dw_mci *, void *, int);\n\tu32 quirks;\n\tbool vqmmc_enabled;\n\tlong unsigned int irq_flags;\n\tint irq;\n\tint sdio_id0;\n\tstruct timer_list cmd11_timer;\n\tstruct timer_list cto_timer;\n\tstruct timer_list dto_timer;\n};\n\nstruct dma_pdata;\n\nstruct dw_mci_board {\n\tunsigned int bus_hz;\n\tu32 caps;\n\tu32 caps2;\n\tu32 pm_caps;\n\tunsigned int fifo_depth;\n\tu32 detect_delay_ms;\n\tstruct reset_control *rstc;\n\tstruct dw_mci_dma_ops *dma_ops;\n\tstruct dma_pdata *data;\n};\n\nstruct dw_mci_dma_ops {\n\tint (*init)(struct dw_mci *);\n\tint (*start)(struct dw_mci *, unsigned int);\n\tvoid (*complete)(void *);\n\tvoid (*stop)(struct dw_mci *);\n\tvoid (*cleanup)(struct dw_mci *);\n\tvoid (*exit)(struct dw_mci *);\n};\n\nstruct dw_mci_dma_slave {\n\tstruct dma_chan *ch;\n\tenum dma_transfer_direction direction;\n};\n\nstruct mmc_ios;\n\nstruct dw_mci_drv_data {\n\tlong unsigned int *caps;\n\tu32 num_caps;\n\tu32 common_caps;\n\tint (*init)(struct dw_mci *);\n\tvoid (*set_ios)(struct dw_mci *, struct mmc_ios *);\n\tint (*parse_dt)(struct dw_mci *);\n\tint (*execute_tuning)(struct dw_mci_slot *, u32);\n\tint (*prepare_hs400_tuning)(struct dw_mci *, struct mmc_ios *);\n\tint (*switch_voltage)(struct mmc_host *, struct mmc_ios *);\n\tvoid (*set_data_timeout)(struct dw_mci *, unsigned int);\n\tu32 (*get_drto_clks)(struct dw_mci *);\n\tvoid (*hw_reset)(struct dw_mci *);\n};\n\nstruct dw_mci_slot {\n\tstruct mmc_host *mmc;\n\tstruct dw_mci *host;\n\tu32 ctype;\n\tstruct mmc_request *mrq;\n\tstruct list_head queue_node;\n\tunsigned int clock;\n\tunsigned int __clk_old;\n\tlong unsigned int flags;\n\tint id;\n\tint sdio_id;\n};\n\nstruct pci_eq_presets {\n\tu16 eq_presets_8gts[16];\n\tu8 eq_presets_Ngts[48];\n};\n\nstruct dw_pcie_host_ops;\n\nstruct irq_chip;\n\nstruct pci_host_bridge;\n\nstruct dw_pcie_rp {\n\tbool use_imsi_rx: 1;\n\tbool cfg0_io_shared: 1;\n\tu64 cfg0_base;\n\tvoid *va_cfg0_base;\n\tu32 cfg0_size;\n\tresource_size_t io_base;\n\tphys_addr_t io_bus_addr;\n\tu32 io_size;\n\tint irq;\n\tconst struct dw_pcie_host_ops *ops;\n\tint msi_irq[8];\n\tstruct irq_domain *irq_domain;\n\tdma_addr_t msi_data;\n\tstruct irq_chip *msi_irq_chip;\n\tu32 num_vectors;\n\tu32 irq_mask[8];\n\tstruct pci_host_bridge *bridge;\n\traw_spinlock_t lock;\n\tlong unsigned int msi_irq_in_use[4];\n\tbool use_atu_msg;\n\tint msg_atu_index;\n\tstruct resource *msg_res;\n\tstruct pci_eq_presets presets;\n\tstruct pci_config_window *cfg;\n\tbool ecam_enabled;\n\tbool native_ecam;\n\tbool skip_l23_ready;\n};\n\nstruct pci_epc;\n\nstruct dw_pcie_ep_ops;\n\nstruct dw_pcie_ep {\n\tstruct pci_epc *epc;\n\tstruct list_head func_list;\n\tconst struct dw_pcie_ep_ops *ops;\n\tphys_addr_t phys_base;\n\tsize_t addr_size;\n\tsize_t page_size;\n\tphys_addr_t *outbound_addr;\n\tlong unsigned int *ib_window_map;\n\tlong unsigned int *ob_window_map;\n\tvoid *msi_mem;\n\tphys_addr_t msi_mem_phys;\n\tbool msi_iatu_mapped;\n\tu64 msi_msg_addr;\n\tsize_t msi_map_size;\n};\n\nstruct reset_control_bulk_data {\n\tconst char *id;\n\tstruct reset_control *rstc;\n};\n\nstruct dw_pcie_ops;\n\nstruct pci_ptm_debugfs;\n\nstruct dw_pcie {\n\tstruct device *dev;\n\tvoid *dbi_base;\n\tresource_size_t dbi_phys_addr;\n\tvoid *dbi_base2;\n\tvoid *atu_base;\n\tvoid *elbi_base;\n\tresource_size_t atu_phys_addr;\n\tsize_t atu_size;\n\tresource_size_t parent_bus_offset;\n\tu32 num_ib_windows;\n\tu32 num_ob_windows;\n\tu32 region_align;\n\tu64 region_limit;\n\tstruct dw_pcie_rp pp;\n\tstruct dw_pcie_ep ep;\n\tconst struct dw_pcie_ops *ops;\n\tu32 version;\n\tu32 type;\n\tlong unsigned int caps;\n\tint num_lanes;\n\tint max_link_speed;\n\tu8 n_fts[2];\n\tstruct dw_edma_chip edma;\n\tbool l1ss_support;\n\tstruct clk_bulk_data app_clks[3];\n\tstruct clk_bulk_data core_clks[4];\n\tstruct reset_control_bulk_data app_rsts[3];\n\tstruct reset_control_bulk_data core_rsts[7];\n\tstruct gpio_desc *pe_rst;\n\tbool suspended;\n\tstruct debugfs_info *debugfs;\n\tenum dw_pcie_device_mode mode;\n\tu16 ptm_vsec_offset;\n\tstruct pci_ptm_debugfs *ptm_debugfs;\n\tbool use_parent_dt_ranges;\n};\n\nstruct pci_epc_features;\n\nstruct dw_pcie_ep_ops {\n\tvoid (*pre_init)(struct dw_pcie_ep *);\n\tvoid (*init)(struct dw_pcie_ep *);\n\tint (*raise_irq)(struct dw_pcie_ep *, u8, unsigned int, u16);\n\tconst struct pci_epc_features * (*get_features)(struct dw_pcie_ep *);\n\tunsigned int (*get_dbi_offset)(struct dw_pcie_ep *, u8);\n\tunsigned int (*get_dbi2_offset)(struct dw_pcie_ep *, u8);\n};\n\nstruct dw_pcie_host_ops {\n\tint (*init)(struct dw_pcie_rp *);\n\tvoid (*deinit)(struct dw_pcie_rp *);\n\tvoid (*post_init)(struct dw_pcie_rp *);\n\tint (*msi_init)(struct dw_pcie_rp *);\n\tvoid (*pme_turn_off)(struct dw_pcie_rp *);\n};\n\nstruct dw_pcie_ob_atu_cfg {\n\tint index;\n\tint type;\n\tu8 func_no;\n\tu8 code;\n\tu8 routing;\n\tu32 ctrl2;\n\tu64 parent_bus_addr;\n\tu64 pci_addr;\n\tu64 size;\n};\n\nstruct dw_pcie_ops {\n\tu64 (*cpu_addr_fixup)(struct dw_pcie *, u64);\n\tu32 (*read_dbi)(struct dw_pcie *, void *, u32, size_t);\n\tvoid (*write_dbi)(struct dw_pcie *, void *, u32, size_t, u32);\n\tvoid (*write_dbi2)(struct dw_pcie *, void *, u32, size_t, u32);\n\tbool (*link_up)(struct dw_pcie *);\n\tenum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *);\n\tint (*start_link)(struct dw_pcie *);\n\tvoid (*stop_link)(struct dw_pcie *);\n};\n\nstruct dwapb_context {\n\tu32 data;\n\tu32 dir;\n\tu32 ext;\n\tu32 int_en;\n\tu32 int_mask;\n\tu32 int_type;\n\tu32 int_pol;\n\tu32 int_deb;\n\tu32 wake_en;\n};\n\nstruct dwapb_gpio_port;\n\nstruct dwapb_gpio {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct dwapb_gpio_port *ports;\n\tunsigned int nr_ports;\n\tunsigned int flags;\n\tstruct reset_control *rst;\n\tstruct clk_bulk_data clks[2];\n};\n\nstruct irq_data;\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nunion gpio_irq_fwspec;\n\nstruct gpio_irq_chip {\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *parent_domain;\n\tint (*child_to_parent_hwirq)(struct gpio_chip *, unsigned int, unsigned int, unsigned int *, unsigned int *);\n\tint (*populate_parent_alloc_arg)(struct gpio_chip *, union gpio_irq_fwspec *, unsigned int, unsigned int);\n\tunsigned int (*child_offset_to_irq)(struct gpio_chip *, unsigned int);\n\tstruct irq_domain_ops child_irq_domain_ops;\n\tirq_flow_handler_t handler;\n\tunsigned int default_type;\n\tstruct lock_class_key *lock_key;\n\tstruct lock_class_key *request_key;\n\tirq_flow_handler_t parent_handler;\n\tunion {\n\t\tvoid *parent_handler_data;\n\t\tvoid **parent_handler_data_array;\n\t};\n\tunsigned int num_parents;\n\tunsigned int *parents;\n\tunsigned int *map;\n\tbool threaded;\n\tbool per_parent_data;\n\tbool initialized;\n\tbool domain_is_allocated_externally;\n\tint (*init_hw)(struct gpio_chip *);\n\tvoid (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tlong unsigned int *valid_mask;\n\tunsigned int first;\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n};\n\nstruct gpio_device;\n\nstruct gpio_chip {\n\tconst char *label;\n\tstruct gpio_device *gpiodev;\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tstruct module *owner;\n\tint (*request)(struct gpio_chip *, unsigned int);\n\tvoid (*free)(struct gpio_chip *, unsigned int);\n\tint (*get_direction)(struct gpio_chip *, unsigned int);\n\tint (*direction_input)(struct gpio_chip *, unsigned int);\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tint (*get)(struct gpio_chip *, unsigned int);\n\tint (*get_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n\tint (*set_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set_config)(struct gpio_chip *, unsigned int, long unsigned int);\n\tint (*to_irq)(struct gpio_chip *, unsigned int);\n\tvoid (*dbg_show)(struct seq_file *, struct gpio_chip *);\n\tint (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tint (*add_pin_ranges)(struct gpio_chip *);\n\tint (*en_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint (*dis_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint base;\n\tu16 ngpio;\n\tu16 offset;\n\tconst char * const *names;\n\tbool can_sleep;\n\tstruct gpio_irq_chip irq;\n\tunsigned int of_gpio_n_cells;\n\tbool (*of_node_instance_match)(struct gpio_chip *, unsigned int);\n\tint (*of_xlate)(struct gpio_chip *, const struct of_phandle_args *, u32 *);\n};\n\nstruct gpio_generic_chip {\n\tstruct gpio_chip gc;\n\tlong unsigned int (*read_reg)(void *);\n\tvoid (*write_reg)(void *, long unsigned int);\n\tbool be_bits;\n\tvoid *reg_dat;\n\tvoid *reg_set;\n\tvoid *reg_clr;\n\tvoid *reg_dir_out;\n\tvoid *reg_dir_in;\n\tbool dir_unreadable;\n\tbool pinctrl;\n\tint bits;\n\traw_spinlock_t lock;\n\tlong unsigned int sdata;\n\tlong unsigned int sdir;\n};\n\nstruct dwapb_gpio_port_irqchip;\n\nstruct dwapb_gpio_port {\n\tstruct gpio_generic_chip chip;\n\tstruct dwapb_gpio_port_irqchip *pirq;\n\tstruct dwapb_gpio *gpio;\n\tstruct dwapb_context *ctx;\n\tunsigned int idx;\n};\n\nstruct dwapb_gpio_port_irqchip {\n\tunsigned int nr_irqs;\n\tunsigned int irq[32];\n};\n\nstruct dwapb_port_property;\n\nstruct dwapb_platform_data {\n\tstruct dwapb_port_property *properties;\n\tunsigned int nports;\n};\n\nstruct dwapb_port_property {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int idx;\n\tunsigned int ngpio;\n\tunsigned int gpio_base;\n\tint irq[32];\n};\n\nstruct dwc_pcie_vsec_id {\n\tu16 vendor_id;\n\tu16 vsec_id;\n\tu8 vsec_rev;\n};\n\nstruct sdhci_ops;\n\nstruct sdhci_pltfm_data {\n\tconst struct sdhci_ops *ops;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n};\n\nstruct sdhci_host;\n\nstruct dwcmshc_priv;\n\nstruct dwcmshc_pltfm_data {\n\tconst struct sdhci_pltfm_data pdata;\n\tconst struct cqhci_host_ops *cqhci_host_ops;\n\tint (*init)(struct device *, struct sdhci_host *, struct dwcmshc_priv *);\n\tvoid (*postinit)(struct sdhci_host *, struct dwcmshc_priv *);\n};\n\nstruct dwcmshc_priv {\n\tstruct clk *bus_clk;\n\tint vendor_specific_area1;\n\tint vendor_specific_area2;\n\tint num_other_clks;\n\tstruct clk_bulk_data other_clks[3];\n\tvoid *priv;\n\tu16 delay_line;\n\tu16 flags;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct dyn_event_operations;\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(const char *);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct napi_config;\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n};\n\nstruct e1000_hw;\n\nstruct e1000_mac_operations {\n\ts32 (*id_led_init)(struct e1000_hw *);\n\ts32 (*blink_led)(struct e1000_hw *);\n\tbool (*check_mng_mode)(struct e1000_hw *);\n\ts32 (*check_for_link)(struct e1000_hw *);\n\ts32 (*cleanup_led)(struct e1000_hw *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw *);\n\tvoid (*clear_vfta)(struct e1000_hw *);\n\ts32 (*get_bus_info)(struct e1000_hw *);\n\tvoid (*set_lan_id)(struct e1000_hw *);\n\ts32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw *);\n\ts32 (*led_off)(struct e1000_hw *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw *);\n\ts32 (*init_hw)(struct e1000_hw *);\n\ts32 (*setup_link)(struct e1000_hw *);\n\ts32 (*setup_physical_interface)(struct e1000_hw *);\n\ts32 (*setup_led)(struct e1000_hw *);\n\tvoid (*write_vfta)(struct e1000_hw *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw *);\n\tint (*rar_set)(struct e1000_hw *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw *);\n\tu32 (*rar_get_count)(struct e1000_hw *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type type;\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tenum e1000_serdes_link_state serdes_link_state;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tu16 refresh_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_phy_operations {\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*cfg_on_link_up)(struct e1000_hw *);\n\ts32 (*check_polarity)(struct e1000_hw *);\n\ts32 (*check_reset_block)(struct e1000_hw *);\n\ts32 (*commit)(struct e1000_hw *);\n\ts32 (*force_speed_duplex)(struct e1000_hw *);\n\ts32 (*get_cfg_done)(struct e1000_hw *);\n\ts32 (*get_cable_length)(struct e1000_hw *);\n\ts32 (*get_info)(struct e1000_hw *);\n\ts32 (*set_page)(struct e1000_hw *, u16);\n\ts32 (*read_reg)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\ts32 (*reset)(struct e1000_hw *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*write_reg)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw *);\n\tvoid (*power_down)(struct e1000_hw *);\n};\n\nstruct e1000_phy_info {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tu32 retry_count;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n\tbool retry_enabled;\n};\n\nstruct e1000_nvm_operations {\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*read)(struct e1000_hw *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\tvoid (*reload)(struct e1000_hw *);\n\ts32 (*update)(struct e1000_hw *);\n\ts32 (*valid_led_default)(struct e1000_hw *, u16 *);\n\ts32 (*validate)(struct e1000_hw *);\n\ts32 (*write)(struct e1000_hw *, u16, u16, u16 *);\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_width width;\n\tu16 func;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\nstruct e1000_dev_spec_82571 {\n\tbool laa_is_present;\n\tu32 smb_counter;\n};\n\nstruct e1000_dev_spec_80003es2lan {\n\tbool mdic_wa_enable;\n};\n\nstruct e1000_shadow_ram {\n\tu16 value;\n\tbool modified;\n};\n\nstruct e1000_dev_spec_ich8lan {\n\tbool kmrn_lock_loss_workaround_enabled;\n\tstruct e1000_shadow_ram shadow_ram[2048];\n\tbool nvm_k1_enabled;\n\tbool eee_disable;\n\tu16 eee_lp_ability;\n\tenum e1000_ulp_state ulp_state;\n};\n\nstruct e1000_adapter;\n\nstruct e1000_hw {\n\tstruct e1000_adapter *adapter;\n\tvoid *hw_addr;\n\tvoid *flash_address;\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82571 e82571;\n\t\tstruct e1000_dev_spec_80003es2lan e80003es2lan;\n\t\tstruct e1000_dev_spec_ich8lan ich8lan;\n\t} dev_spec;\n};\n\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_phy_regs {\n\tu16 bmcr;\n\tu16 bmsr;\n\tu16 advertise;\n\tu16 lpa;\n\tu16 expansion;\n\tu16 ctrl1000;\n\tu16 stat1000;\n\tu16 estatus;\n};\n\nstruct e1000_buffer;\n\nstruct e1000_ring {\n\tstruct e1000_adapter *adapter;\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\tvoid *head;\n\tvoid *tail;\n\tstruct e1000_buffer *buffer_info;\n\tchar name[21];\n\tu32 ims_val;\n\tu32 itr_val;\n\tvoid *itr_register;\n\tint set_itr;\n\tstruct sk_buff *rx_skb_top;\n};\n\nstruct ifreq;\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct ptp_clock;\n\nstruct ptp_pin_desc;\n\nstruct ptp_system_timestamp;\n\nstruct system_device_crosststamp;\n\nstruct ptp_clock_request;\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[32];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint n_per_lp;\n\tint pps;\n\tunsigned int supported_perout_flags;\n\tunsigned int supported_extts_flags;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\ts32 (*getmaxphase)(struct ptp_clock_info *);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*getcycles64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n\tint (*perout_loopback)(struct ptp_clock_info *, unsigned int, int);\n};\n\nstruct pm_qos_request {\n\tstruct plist_node node;\n\tstruct pm_qos_constraints *qos;\n};\n\nstruct e1000_info;\n\nstruct msix_entry;\n\nstruct e1000_adapter {\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tstruct timer_list blink_timer;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tconst struct e1000_info *ei;\n\tlong unsigned int active_vlans[64];\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu16 mng_vlan_id;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu16 eeprom_vers;\n\tlong unsigned int state;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct e1000_ring *tx_ring;\n\tu32 tx_fifo_limit;\n\tstruct napi_struct napi;\n\tunsigned int uncorr_errors;\n\tunsigned int corr_errors;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tbool detect_tx_hung;\n\tbool tx_hang_recheck;\n\tu8 tx_timeout_factor;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 gotc;\n\tu64 gotc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu32 tx_dma_failed;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tlong: 64;\n\tlong: 64;\n\tbool (*clean_rx)(struct e1000_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_ring *, int, gfp_t);\n\tstruct e1000_ring *rx_ring;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu64 rx_hdr_split;\n\tu32 gorc;\n\tu64 gorc_old;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_dma_failed;\n\tu32 rx_hwtstamp_cleared;\n\tunsigned int rx_ps_pages;\n\tu16 rx_ps_bsize0;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw hw;\n\tspinlock_t stats64_lock;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_phy_info phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tstruct e1000_phy_regs phy_regs;\n\tstruct e1000_ring test_tx_ring;\n\tstruct e1000_ring test_rx_ring;\n\tu32 test_icr;\n\tu32 msg_enable;\n\tunsigned int num_vectors;\n\tstruct msix_entry *msix_entries;\n\tint int_mode;\n\tu32 eiac_mask;\n\tu32 eeprom_wol;\n\tu32 wol;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\tbool fc_autoneg;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tstruct work_struct downshift_task;\n\tstruct work_struct update_phy_task;\n\tstruct work_struct print_hang_task;\n\tint phy_hang_count;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tstruct kernel_hwtstamp_config hwtstamp_config;\n\tstruct delayed_work systim_overflow_work;\n\tstruct sk_buff *tx_hwtstamp_skb;\n\tlong unsigned int tx_hwtstamp_start;\n\tstruct work_struct tx_hwtstamp_work;\n\tspinlock_t systim_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct pm_qos_request pm_qos_req;\n\tlong int ptp_delta;\n\tu16 eee_advert;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct e1000_ps_page;\n\nstruct e1000_buffer {\n\tdma_addr_t dma;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int time_stamp;\n\t\t\tu16 length;\n\t\t\tu16 next_to_watch;\n\t\t\tunsigned int segs;\n\t\t\tunsigned int bytecount;\n\t\t\tu16 mapped_as_page;\n\t\t};\n\t\tstruct {\n\t\t\tstruct e1000_ps_page *ps_pages;\n\t\t\tstruct page *page;\n\t\t};\n\t};\n};\n\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss;\n\t\t\tu8 ipcso;\n\t\t\t__le16 ipcse;\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss;\n\t\t\tu8 tucso;\n\t\t\t__le16 tucse;\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 hdr_len;\n\t\t\t__le16 mss;\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\nstruct e1000_info {\n\tenum e1000_mac_type mac;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\ts32 (*get_variants)(struct e1000_adapter *);\n\tconst struct e1000_mac_operations *mac_ops;\n\tconst struct e1000_phy_operations *phy_ops;\n\tconst struct e1000_nvm_operations *nvm_ops;\n};\n\nstruct e1000_opt_list {\n\tint i;\n\tchar *str;\n};\n\nstruct e1000_option {\n\tenum {\n\t\tenable_option = 0,\n\t\trange_option = 1,\n\t\tlist_option = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tstruct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_ps_page {\n\tstruct page *page;\n\tu64 dma;\n};\n\nstruct e1000_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t__le64 buffer_addr[4];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length0;\n\t\t\t__le16 vlan;\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t__le16 length[3];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb;\n};\n\nstruct e1000_stats {\n\tchar stat_string[32];\n\tint type;\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct e1000_tx_desc {\n\t__le64 buffer_addr;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length;\n\t\t\tu8 cso;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 css;\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\nstruct usb_device;\n\nstruct each_dev_arg {\n\tvoid *data;\n\tint (*fn)(struct usb_device *, void *);\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\tunion {\n\t\t__u32 padding[5];\n\t\tstruct {\n\t\t\t__u8 addr_recv;\n\t\t\t__u8 addr_dest;\n\t\t\t__u8 padding0[2];\n\t\t\t__u32 padding1[4];\n\t\t};\n\t};\n};\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct ktermios;\n\nstruct uart_state;\n\nstruct uart_ops;\n\nstruct serial_port_device;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int ctrl_id;\n\tunsigned int port_id;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char quirks;\n\tenum uart_iotype iotype;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tupf_t flags;\n\tupstat_t status;\n\tbool hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int frame_time;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tstruct serial_port_device *port_dev;\n\tlong unsigned int sysrq;\n\tu8 sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tunsigned char console_reinit;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct serial_rs485 rs485_supported;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct gpio_desc *rs485_rx_during_tx_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tstruct uart_port port;\n\tchar options[32];\n\tunsigned int baud;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nstruct ebitmap_node {\n\tstruct ebitmap_node *next;\n\tlong unsigned int maps[6];\n\tu32 startbit;\n};\n\nstruct td;\n\nstruct ed {\n\t__hc32 hwINFO;\n\t__hc32 hwTailP;\n\t__hc32 hwHeadP;\n\t__hc32 hwNextED;\n\tdma_addr_t dma;\n\tstruct td *dummy;\n\tstruct ed *ed_next;\n\tstruct ed *ed_prev;\n\tstruct list_head td_list;\n\tstruct list_head in_use_list;\n\tu8 state;\n\tu8 type;\n\tu8 branch;\n\tu16 interval;\n\tu16 load;\n\tu16 last_iso;\n\tu16 tick;\n\tunsigned int takeback_wdh_cnt;\n\tstruct td *pending_td;\n\tlong: 64;\n};\n\nstruct edid_info {\n\tunsigned char dummy[128];\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[2];\n\tlong unsigned int advertised[2];\n\tlong unsigned int lp_advertised[2];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct eeprom_93cx6 {\n\tvoid *data;\n\tvoid (*register_read)(struct eeprom_93cx6 *);\n\tvoid (*register_write)(struct eeprom_93cx6 *);\n\tint width;\n\tunsigned int quirks;\n\tchar drive_data;\n\tchar reg_data_in;\n\tchar reg_data_out;\n\tchar reg_data_clock;\n\tchar reg_chip_select;\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\nstruct efi_memory_map {\n\tphys_addr_t phys_map;\n\tvoid *map;\n\tvoid *map_end;\n\tint nr_map;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nstruct efi {\n\tconst efi_runtime_services_t *runtime;\n\tunsigned int runtime_version;\n\tunsigned int runtime_supported_mask;\n\tlong unsigned int acpi;\n\tlong unsigned int acpi20;\n\tlong unsigned int smbios;\n\tlong unsigned int smbios3;\n\tlong unsigned int esrt;\n\tlong unsigned int tpm_log;\n\tlong unsigned int tpm_final_log;\n\tlong unsigned int ovmf_debug_log;\n\tlong unsigned int mokvar_table;\n\tlong unsigned int coco_secret;\n\tlong unsigned int unaccepted;\n\tefi_get_time_t *get_time;\n\tefi_set_time_t *set_time;\n\tefi_get_wakeup_time_t *get_wakeup_time;\n\tefi_set_wakeup_time_t *set_wakeup_time;\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_info_t *query_variable_info;\n\tefi_query_variable_info_t *query_variable_info_nonblocking;\n\tefi_update_capsule_t *update_capsule;\n\tefi_query_capsule_caps_t *query_capsule_caps;\n\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\tefi_reset_system_t *reset_system;\n\tstruct efi_memory_map memmap;\n\tlong unsigned int flags;\n};\n\nstruct efi_boot_memmap {\n\tlong unsigned int map_size;\n\tlong unsigned int desc_size;\n\tu32 desc_ver;\n\tlong unsigned int map_key;\n\tlong unsigned int buff_size;\n\tefi_memory_desc_t map[0];\n};\n\ntypedef void *efi_event_t;\n\ntypedef void (*efi_event_notify_t)(efi_event_t, void *);\n\nunion efi_boot_services {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tvoid *raise_tpl;\n\t\tvoid *restore_tpl;\n\t\tefi_status_t (*allocate_pages)(int, int, long unsigned int, efi_physical_addr_t *);\n\t\tefi_status_t (*free_pages)(efi_physical_addr_t, long unsigned int);\n\t\tefi_status_t (*get_memory_map)(long unsigned int *, void *, long unsigned int *, long unsigned int *, u32 *);\n\t\tefi_status_t (*allocate_pool)(int, long unsigned int, void **);\n\t\tefi_status_t (*free_pool)(void *);\n\t\tefi_status_t (*create_event)(u32, long unsigned int, efi_event_notify_t, void *, efi_event_t *);\n\t\tefi_status_t (*set_timer)(efi_event_t, EFI_TIMER_DELAY, u64);\n\t\tefi_status_t (*wait_for_event)(long unsigned int, efi_event_t *, long unsigned int *);\n\t\tvoid *signal_event;\n\t\tefi_status_t (*close_event)(efi_event_t);\n\t\tvoid *check_event;\n\t\tvoid *install_protocol_interface;\n\t\tvoid *reinstall_protocol_interface;\n\t\tvoid *uninstall_protocol_interface;\n\t\tefi_status_t (*handle_protocol)(efi_handle_t, efi_guid_t *, void **);\n\t\tvoid *__reserved;\n\t\tvoid *register_protocol_notify;\n\t\tefi_status_t (*locate_handle)(int, efi_guid_t *, void *, long unsigned int *, efi_handle_t *);\n\t\tefi_status_t (*locate_device_path)(efi_guid_t *, efi_device_path_protocol_t **, efi_handle_t *);\n\t\tefi_status_t (*install_configuration_table)(efi_guid_t *, void *);\n\t\tefi_status_t (*load_image)(bool, efi_handle_t, efi_device_path_protocol_t *, void *, long unsigned int, efi_handle_t *);\n\t\tefi_status_t (*start_image)(efi_handle_t, long unsigned int *, efi_char16_t **);\n\t\tefi_status_t (*exit)(efi_handle_t, efi_status_t, long unsigned int, efi_char16_t *);\n\t\tefi_status_t (*unload_image)(efi_handle_t);\n\t\tefi_status_t (*exit_boot_services)(efi_handle_t, long unsigned int);\n\t\tvoid *get_next_monotonic_count;\n\t\tefi_status_t (*stall)(long unsigned int);\n\t\tvoid *set_watchdog_timer;\n\t\tvoid *connect_controller;\n\t\tefi_status_t (*disconnect_controller)(efi_handle_t, efi_handle_t, efi_handle_t);\n\t\tvoid *open_protocol;\n\t\tvoid *close_protocol;\n\t\tvoid *open_protocol_information;\n\t\tvoid *protocols_per_handle;\n\t\tefi_status_t (*locate_handle_buffer)(int, efi_guid_t *, void *, long unsigned int *, efi_handle_t **);\n\t\tefi_status_t (*locate_protocol)(efi_guid_t *, void *, void **);\n\t\tefi_status_t (*install_multiple_protocol_interfaces)(efi_handle_t *, ...);\n\t\tefi_status_t (*uninstall_multiple_protocol_interfaces)(efi_handle_t, ...);\n\t\tvoid *calculate_crc32;\n\t\tvoid (*copy_mem)(void *, const void *, long unsigned int);\n\t\tvoid (*set_mem)(void *, long unsigned int, unsigned char);\n\t\tvoid *create_event_ex;\n\t};\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tu32 raise_tpl;\n\t\tu32 restore_tpl;\n\t\tu32 allocate_pages;\n\t\tu32 free_pages;\n\t\tu32 get_memory_map;\n\t\tu32 allocate_pool;\n\t\tu32 free_pool;\n\t\tu32 create_event;\n\t\tu32 set_timer;\n\t\tu32 wait_for_event;\n\t\tu32 signal_event;\n\t\tu32 close_event;\n\t\tu32 check_event;\n\t\tu32 install_protocol_interface;\n\t\tu32 reinstall_protocol_interface;\n\t\tu32 uninstall_protocol_interface;\n\t\tu32 handle_protocol;\n\t\tu32 __reserved;\n\t\tu32 register_protocol_notify;\n\t\tu32 locate_handle;\n\t\tu32 locate_device_path;\n\t\tu32 install_configuration_table;\n\t\tu32 load_image;\n\t\tu32 start_image;\n\t\tu32 exit;\n\t\tu32 unload_image;\n\t\tu32 exit_boot_services;\n\t\tu32 get_next_monotonic_count;\n\t\tu32 stall;\n\t\tu32 set_watchdog_timer;\n\t\tu32 connect_controller;\n\t\tu32 disconnect_controller;\n\t\tu32 open_protocol;\n\t\tu32 close_protocol;\n\t\tu32 open_protocol_information;\n\t\tu32 protocols_per_handle;\n\t\tu32 locate_handle_buffer;\n\t\tu32 locate_protocol;\n\t\tu32 install_multiple_protocol_interfaces;\n\t\tu32 uninstall_multiple_protocol_interfaces;\n\t\tu32 calculate_crc32;\n\t\tu32 copy_mem;\n\t\tu32 set_mem;\n\t\tu32 create_event_ex;\n\t} mixed_mode;\n};\n\nstruct efi_cc_event {\n\tu32 event_size;\n\tstruct {\n\t\tu32 header_size;\n\t\tu16 header_version;\n\t\tu32 mr_index;\n\t\tu32 event_type;\n\t} __attribute__((packed)) event_header;\n} __attribute__((packed));\n\ntypedef struct efi_cc_event efi_cc_event_t;\n\nunion efi_cc_protocol;\n\ntypedef union efi_cc_protocol efi_cc_protocol_t;\n\nunion efi_cc_protocol {\n\tstruct {\n\t\tefi_status_t (*get_capability)(efi_cc_protocol_t *, efi_cc_boot_service_cap_t *);\n\t\tefi_status_t (*get_event_log)(efi_cc_protocol_t *, efi_cc_event_log_format_t, efi_physical_addr_t *, efi_physical_addr_t *, efi_bool_t *);\n\t\tefi_status_t (*hash_log_extend_event)(efi_cc_protocol_t *, u64, efi_physical_addr_t, u64, const efi_cc_event_t *);\n\t\tefi_status_t (*map_pcr_to_mr_index)(efi_cc_protocol_t *, u32, efi_cc_mr_index_t *);\n\t};\n\tstruct {\n\t\tu32 get_capability;\n\t\tu32 get_event_log;\n\t\tu32 hash_log_extend_event;\n\t\tu32 map_pcr_to_mr_index;\n\t} mixed_mode;\n};\n\nunion efi_device_path_from_text_protocol {\n\tstruct {\n\t\tefi_device_path_protocol_t * (*convert_text_to_device_node)(const efi_char16_t *);\n\t\tefi_device_path_protocol_t * (*convert_text_to_device_path)(const efi_char16_t *);\n\t};\n\tstruct {\n\t\tu32 convert_text_to_device_node;\n\t\tu32 convert_text_to_device_path;\n\t} mixed_mode;\n};\n\ntypedef union efi_device_path_from_text_protocol efi_device_path_from_text_protocol_t;\n\nunion efi_edid_active_protocol {\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu8 *edid;\n\t};\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu32 edid;\n\t} mixed_mode;\n};\n\ntypedef union efi_edid_active_protocol efi_edid_active_protocol_t;\n\nunion efi_edid_discovered_protocol {\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu8 *edid;\n\t};\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu32 edid;\n\t} mixed_mode;\n};\n\ntypedef union efi_edid_discovered_protocol efi_edid_discovered_protocol_t;\n\nstruct efi_generic_dev_path {\n\tu8 type;\n\tu8 sub_type;\n\tu16 length;\n};\n\nstruct efi_file_path_dev_path {\n\tstruct efi_generic_dev_path header;\n\tefi_char16_t filename[0];\n};\n\nunion efi_file_protocol;\n\ntypedef union efi_file_protocol efi_file_protocol_t;\n\nunion efi_file_protocol {\n\tstruct {\n\t\tu64 revision;\n\t\tefi_status_t (*open)(efi_file_protocol_t *, efi_file_protocol_t **, efi_char16_t *, u64, u64);\n\t\tefi_status_t (*close)(efi_file_protocol_t *);\n\t\tefi_status_t (*delete)(efi_file_protocol_t *);\n\t\tefi_status_t (*read)(efi_file_protocol_t *, long unsigned int *, void *);\n\t\tefi_status_t (*write)(efi_file_protocol_t *, long unsigned int, void *);\n\t\tefi_status_t (*get_position)(efi_file_protocol_t *, u64 *);\n\t\tefi_status_t (*set_position)(efi_file_protocol_t *, u64);\n\t\tefi_status_t (*get_info)(efi_file_protocol_t *, efi_guid_t *, long unsigned int *, void *);\n\t\tefi_status_t (*set_info)(efi_file_protocol_t *, efi_guid_t *, long unsigned int, void *);\n\t\tefi_status_t (*flush)(efi_file_protocol_t *);\n\t};\n\tstruct {\n\t\tu64 revision;\n\t\tu32 open;\n\t\tu32 close;\n\t\tu32 delete;\n\t\tu32 read;\n\t\tu32 write;\n\t\tu32 get_position;\n\t\tu32 set_position;\n\t\tu32 get_info;\n\t\tu32 set_info;\n\t\tu32 flush;\n\t} mixed_mode;\n};\n\nunion efi_graphics_output_protocol;\n\ntypedef union efi_graphics_output_protocol efi_graphics_output_protocol_t;\n\nunion efi_graphics_output_protocol_mode;\n\ntypedef union efi_graphics_output_protocol_mode efi_graphics_output_protocol_mode_t;\n\nunion efi_graphics_output_protocol {\n\tstruct {\n\t\tefi_status_t (*query_mode)(efi_graphics_output_protocol_t *, u32, long unsigned int *, efi_graphics_output_mode_info_t **);\n\t\tefi_status_t (*set_mode)(efi_graphics_output_protocol_t *, u32);\n\t\tvoid *blt;\n\t\tefi_graphics_output_protocol_mode_t *mode;\n\t};\n\tstruct {\n\t\tu32 query_mode;\n\t\tu32 set_mode;\n\t\tu32 blt;\n\t\tu32 mode;\n\t} mixed_mode;\n};\n\nunion efi_graphics_output_protocol_mode {\n\tstruct {\n\t\tu32 max_mode;\n\t\tu32 mode;\n\t\tefi_graphics_output_mode_info_t *info;\n\t\tlong unsigned int size_of_info;\n\t\tefi_physical_addr_t frame_buffer_base;\n\t\tlong unsigned int frame_buffer_size;\n\t};\n\tstruct {\n\t\tu32 max_mode;\n\t\tu32 mode;\n\t\tu32 info;\n\t\tu32 size_of_info;\n\t\tu64 frame_buffer_base;\n\t\tu32 frame_buffer_size;\n\t} mixed_mode;\n};\n\nunion efi_load_file_protocol;\n\ntypedef union efi_load_file_protocol efi_load_file_protocol_t;\n\nunion efi_load_file_protocol {\n\tstruct {\n\t\tefi_status_t (*load_file)(efi_load_file_protocol_t *, efi_device_path_protocol_t *, bool, long unsigned int *, void *);\n\t};\n\tstruct {\n\t\tu32 load_file;\n\t} mixed_mode;\n};\n\ntypedef union efi_load_file_protocol efi_load_file2_protocol_t;\n\nunion efi_memory_attribute_protocol;\n\ntypedef union efi_memory_attribute_protocol efi_memory_attribute_protocol_t;\n\nunion efi_memory_attribute_protocol {\n\tstruct {\n\t\tefi_status_t (*get_memory_attributes)(efi_memory_attribute_protocol_t *, efi_physical_addr_t, u64, u64 *);\n\t\tefi_status_t (*set_memory_attributes)(efi_memory_attribute_protocol_t *, efi_physical_addr_t, u64, u64);\n\t\tefi_status_t (*clear_memory_attributes)(efi_memory_attribute_protocol_t *, efi_physical_addr_t, u64, u64);\n\t};\n\tstruct {\n\t\tu32 get_memory_attributes;\n\t\tu32 set_memory_attributes;\n\t\tu32 clear_memory_attributes;\n\t} mixed_mode;\n};\n\nstruct efi_memory_map_data {\n\tphys_addr_t phys_map;\n\tlong unsigned int size;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nunion efi_pci_io_protocol {\n\tstruct {\n\t\tvoid *poll_mem;\n\t\tvoid *poll_io;\n\t\tefi_pci_io_protocol_access_t mem;\n\t\tefi_pci_io_protocol_access_t io;\n\t\tefi_pci_io_protocol_config_access_t pci;\n\t\tvoid *copy_mem;\n\t\tvoid *map;\n\t\tvoid *unmap;\n\t\tvoid *allocate_buffer;\n\t\tvoid *free_buffer;\n\t\tvoid *flush;\n\t\tefi_status_t (*get_location)(efi_pci_io_protocol_t *, long unsigned int *, long unsigned int *, long unsigned int *, long unsigned int *);\n\t\tvoid *attributes;\n\t\tvoid *get_bar_attributes;\n\t\tvoid *set_bar_attributes;\n\t\tuint64_t romsize;\n\t\tvoid *romimage;\n\t};\n\tstruct {\n\t\tu32 poll_mem;\n\t\tu32 poll_io;\n\t\tefi_pci_io_protocol_access_32_t mem;\n\t\tefi_pci_io_protocol_access_32_t io;\n\t\tefi_pci_io_protocol_access_32_t pci;\n\t\tu32 copy_mem;\n\t\tu32 map;\n\t\tu32 unmap;\n\t\tu32 allocate_buffer;\n\t\tu32 free_buffer;\n\t\tu32 flush;\n\t\tu32 get_location;\n\t\tu32 attributes;\n\t\tu32 get_bar_attributes;\n\t\tu32 set_bar_attributes;\n\t\tu64 romsize;\n\t\tu32 romimage;\n\t} mixed_mode;\n};\n\nunion efi_rng_protocol;\n\ntypedef union efi_rng_protocol efi_rng_protocol_t;\n\nunion efi_rng_protocol {\n\tstruct {\n\t\tefi_status_t (*get_info)(efi_rng_protocol_t *, long unsigned int *, efi_guid_t *);\n\t\tefi_status_t (*get_rng)(efi_rng_protocol_t *, efi_guid_t *, long unsigned int, u8 *);\n\t};\n\tstruct {\n\t\tu32 get_info;\n\t\tu32 get_rng;\n\t} mixed_mode;\n};\n\nunion efi_rts_args {\n\tstruct {\n\t\tefi_time_t *time;\n\t\tefi_time_cap_t *capabilities;\n\t} GET_TIME;\n\tstruct {\n\t\tefi_time_t *time;\n\t} SET_TIME;\n\tstruct {\n\t\tefi_bool_t *enabled;\n\t\tefi_bool_t *pending;\n\t\tefi_time_t *time;\n\t} GET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_bool_t enable;\n\t\tefi_time_t *time;\n\t} SET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 *attr;\n\t\tlong unsigned int *data_size;\n\t\tvoid *data;\n\t} GET_VARIABLE;\n\tstruct {\n\t\tlong unsigned int *name_size;\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t} GET_NEXT_VARIABLE;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 attr;\n\t\tlong unsigned int data_size;\n\t\tvoid *data;\n\t} SET_VARIABLE;\n\tstruct {\n\t\tu32 attr;\n\t\tu64 *storage_space;\n\t\tu64 *remaining_space;\n\t\tu64 *max_variable_size;\n\t} QUERY_VARIABLE_INFO;\n\tstruct {\n\t\tu32 *high_count;\n\t} GET_NEXT_HIGH_MONO_COUNT;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tlong unsigned int sg_list;\n\t} UPDATE_CAPSULE;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tu64 *max_size;\n\t\tint *reset_type;\n\t} QUERY_CAPSULE_CAPS;\n\tstruct {\n\t\tefi_status_t (*acpi_prm_handler)(u64, void *);\n\t\tu64 param_buffer_addr;\n\t\tvoid *context;\n\t} ACPI_PRM_HANDLER;\n};\n\nstruct efi_runtime_work {\n\tunion efi_rts_args *args;\n\tefi_status_t status;\n\tstruct work_struct work;\n\tenum efi_rts_ids efi_rts_id;\n\tstruct completion efi_rts_comp;\n\tconst void *caller;\n};\n\nunion efi_simple_file_system_protocol;\n\ntypedef union efi_simple_file_system_protocol efi_simple_file_system_protocol_t;\n\nunion efi_simple_file_system_protocol {\n\tstruct {\n\t\tu64 revision;\n\t\tefi_status_t (*open_volume)(efi_simple_file_system_protocol_t *, efi_file_protocol_t **);\n\t};\n\tstruct {\n\t\tu64 revision;\n\t\tu32 open_volume;\n\t} mixed_mode;\n};\n\nunion efi_simple_text_input_protocol {\n\tstruct {\n\t\tvoid *reset;\n\t\tefi_status_t (*read_keystroke)(efi_simple_text_input_protocol_t *, efi_input_key_t *);\n\t\tefi_event_t wait_for_key;\n\t};\n\tstruct {\n\t\tu32 reset;\n\t\tu32 read_keystroke;\n\t\tu32 wait_for_key;\n\t} mixed_mode;\n};\n\nunion efi_simple_text_output_protocol {\n\tstruct {\n\t\tvoid *reset;\n\t\tefi_status_t (*output_string)(efi_simple_text_output_protocol_t *, efi_char16_t *);\n\t\tvoid *test_string;\n\t};\n\tstruct {\n\t\tu32 reset;\n\t\tu32 output_string;\n\t\tu32 test_string;\n\t} mixed_mode;\n};\n\nstruct efi_system_resource_entry_v1 {\n\tefi_guid_t fw_class;\n\tu32 fw_type;\n\tu32 fw_version;\n\tu32 lowest_supported_fw_version;\n\tu32 capsule_flags;\n\tu32 last_attempt_version;\n\tu32 last_attempt_status;\n};\n\nstruct efi_system_resource_table {\n\tu32 fw_resource_count;\n\tu32 fw_resource_count_max;\n\tu64 fw_resource_version;\n\tu8 entries[0];\n};\n\nstruct efi_tcg2_event {\n\tu32 event_size;\n\tstruct {\n\t\tu32 header_size;\n\t\tu16 header_version;\n\t\tu32 pcr_index;\n\t\tu32 event_type;\n\t} __attribute__((packed)) event_header;\n} __attribute__((packed));\n\ntypedef struct efi_tcg2_event efi_tcg2_event_t;\n\nstruct efi_tcg2_final_events_table {\n\tu64 version;\n\tu64 nr_events;\n\tu8 events[0];\n};\n\nunion efi_tcg2_protocol;\n\ntypedef union efi_tcg2_protocol efi_tcg2_protocol_t;\n\nunion efi_tcg2_protocol {\n\tstruct {\n\t\tvoid *get_capability;\n\t\tefi_status_t (*get_event_log)(efi_tcg2_protocol_t *, efi_tcg2_event_log_format, efi_physical_addr_t *, efi_physical_addr_t *, efi_bool_t *);\n\t\tefi_status_t (*hash_log_extend_event)(efi_tcg2_protocol_t *, u64, efi_physical_addr_t, u64, const efi_tcg2_event_t *);\n\t\tvoid *submit_command;\n\t\tvoid *get_active_pcr_banks;\n\t\tvoid *set_active_pcr_banks;\n\t\tvoid *get_result_of_set_active_pcr_banks;\n\t};\n\tstruct {\n\t\tu32 get_capability;\n\t\tu32 get_event_log;\n\t\tu32 hash_log_extend_event;\n\t\tu32 submit_command;\n\t\tu32 get_active_pcr_banks;\n\t\tu32 set_active_pcr_banks;\n\t\tu32 get_result_of_set_active_pcr_banks;\n\t} mixed_mode;\n};\n\nstruct efi_unaccepted_memory {\n\tu32 version;\n\tu32 unit_size;\n\tu64 phys_base;\n\tu64 size;\n\tlong unsigned int bitmap[0];\n};\n\nstruct efi_vendor_dev_path {\n\tstruct efi_generic_dev_path header;\n\tefi_guid_t vendorguid;\n\tu8 vendordata[0];\n};\n\nunion efistub_event {\n\tefi_tcg2_event_t tcg2_data;\n\tefi_cc_event_t cc_data;\n};\n\nstruct tdTCG_PCClientTaggedEvent {\n\tu32 tagged_event_id;\n\tu32 tagged_event_data_size;\n\tu8 tagged_event_data[0];\n};\n\ntypedef struct tdTCG_PCClientTaggedEvent TCG_PCClientTaggedEvent;\n\nstruct efistub_measured_event {\n\tunion efistub_event event_data;\n\tTCG_PCClientTaggedEvent tagged_event;\n} __attribute__((packed));\n\ntypedef efi_status_t efi_query_variable_store_t(u32, long unsigned int, bool);\n\nstruct efivar_operations {\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_store_t *query_variable_store;\n\tefi_query_variable_info_t *query_variable_info;\n};\n\nstruct efivars {\n\tstruct kset *kset;\n\tconst struct efivar_operations *ops;\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct usb_hcd;\n\nstruct ehci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\nstruct ehci_qh;\n\nstruct ehci_itd;\n\nstruct ehci_sitd;\n\nstruct ehci_fstn;\n\nunion ehci_shadow {\n\tstruct ehci_qh *qh;\n\tstruct ehci_itd *itd;\n\tstruct ehci_sitd *sitd;\n\tstruct ehci_fstn *fstn;\n\t__le32 *hw_next;\n\tvoid *ptr;\n};\n\nstruct ehci_fstn {\n\t__le32 hw_next;\n\t__le32 hw_prev;\n\tdma_addr_t fstn_dma;\n\tunion ehci_shadow fstn_next;\n\tlong: 64;\n};\n\nstruct ehci_regs;\n\nstruct ehci_hcd {\n\tenum ehci_hrtimer_event next_hrtimer_event;\n\tunsigned int enabled_hrtimer_events;\n\tktime_t hr_timeouts[12];\n\tstruct hrtimer hrtimer;\n\tint PSS_poll_count;\n\tint ASS_poll_count;\n\tint died_poll_count;\n\tstruct ehci_caps *caps;\n\tstruct ehci_regs *regs;\n\tstruct ehci_dbg_port *debug;\n\t__u32 hcs_params;\n\tspinlock_t lock;\n\tenum ehci_rh_state rh_state;\n\tbool scanning: 1;\n\tbool need_rescan: 1;\n\tbool intr_unlinking: 1;\n\tbool iaa_in_progress: 1;\n\tbool async_unlinking: 1;\n\tbool shutdown: 1;\n\tstruct ehci_qh *qh_scan_next;\n\tstruct ehci_qh *async;\n\tstruct ehci_qh *dummy;\n\tstruct list_head async_unlink;\n\tstruct list_head async_idle;\n\tunsigned int async_unlink_cycle;\n\tunsigned int async_count;\n\t__le32 old_current;\n\t__le32 old_token;\n\tunsigned int periodic_size;\n\t__le32 *periodic;\n\tdma_addr_t periodic_dma;\n\tstruct list_head intr_qh_list;\n\tunsigned int i_thresh;\n\tunion ehci_shadow *pshadow;\n\tstruct list_head intr_unlink_wait;\n\tstruct list_head intr_unlink;\n\tunsigned int intr_unlink_wait_cycle;\n\tunsigned int intr_unlink_cycle;\n\tunsigned int now_frame;\n\tunsigned int last_iso_frame;\n\tunsigned int intr_count;\n\tunsigned int isoc_count;\n\tunsigned int periodic_count;\n\tunsigned int uframe_periodic_max;\n\tstruct list_head cached_itd_list;\n\tstruct ehci_itd *last_itd_to_free;\n\tstruct list_head cached_sitd_list;\n\tstruct ehci_sitd *last_sitd_to_free;\n\tlong unsigned int reset_done[15];\n\tlong unsigned int bus_suspended;\n\tlong unsigned int companion_ports;\n\tlong unsigned int owned_ports;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int suspended_ports;\n\tlong unsigned int resuming_ports;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *qtd_pool;\n\tstruct dma_pool *itd_pool;\n\tstruct dma_pool *sitd_pool;\n\tunsigned int random_frame;\n\tlong unsigned int next_statechange;\n\tktime_t last_periodic_enable;\n\tu32 command;\n\tunsigned int no_selective_suspend: 1;\n\tunsigned int has_fsl_port_bug: 1;\n\tunsigned int has_fsl_hs_errata: 1;\n\tunsigned int has_fsl_susp_errata: 1;\n\tunsigned int has_ci_pec_bug: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_capbase: 1;\n\tunsigned int has_amcc_usb23: 1;\n\tunsigned int need_io_watchdog: 1;\n\tunsigned int amd_pll_fix: 1;\n\tunsigned int use_dummy_qh: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int frame_index_bug: 1;\n\tunsigned int need_oc_pp_cycle: 1;\n\tunsigned int imx28_write_fix: 1;\n\tunsigned int spurious_oc: 1;\n\tunsigned int is_aspeed: 1;\n\tunsigned int zx_wakeup_clear_needed: 1;\n\t__le32 *ohci_hcctrl_reg;\n\tunsigned int has_hostpc: 1;\n\tunsigned int has_tdi_phy_lpm: 1;\n\tunsigned int has_ppcd: 1;\n\tu8 sbrn;\n\tu8 bandwidth[64];\n\tu8 tt_budget[64];\n\tstruct list_head tt_list;\n\tlong unsigned int priv[0];\n};\n\nstruct ehci_iso_packet {\n\tu64 bufp;\n\t__le32 transaction;\n\tu8 cross;\n\tu32 buf1;\n};\n\nstruct ehci_iso_sched {\n\tstruct list_head td_list;\n\tunsigned int span;\n\tunsigned int first_packet;\n\tstruct ehci_iso_packet packet[0];\n};\n\nstruct usb_host_endpoint;\n\nstruct ehci_per_sched {\n\tstruct usb_device *udev;\n\tstruct usb_host_endpoint *ep;\n\tstruct list_head ps_list;\n\tu16 tt_usecs;\n\tu16 cs_mask;\n\tu16 period;\n\tu16 phase;\n\tu8 bw_phase;\n\tu8 phase_uf;\n\tu8 usecs;\n\tu8 c_usecs;\n\tu8 bw_uperiod;\n\tu8 bw_period;\n};\n\nstruct ehci_qh_hw;\n\nstruct ehci_iso_stream {\n\tstruct ehci_qh_hw *hw;\n\tu8 bEndpointAddress;\n\tu8 highspeed;\n\tstruct list_head td_list;\n\tstruct list_head free_list;\n\tstruct ehci_per_sched ps;\n\tunsigned int next_uframe;\n\t__le32 splits;\n\tu16 uperiod;\n\tu16 maxp;\n\tunsigned int bandwidth;\n\t__le32 buf0;\n\t__le32 buf1;\n\t__le32 buf2;\n\t__le32 address;\n};\n\nstruct ehci_itd {\n\t__le32 hw_next;\n\t__le32 hw_transaction[8];\n\t__le32 hw_bufp[7];\n\t__le32 hw_bufp_hi[7];\n\tdma_addr_t itd_dma;\n\tunion ehci_shadow itd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head itd_list;\n\tunsigned int frame;\n\tunsigned int pg;\n\tunsigned int index[8];\n\tlong: 64;\n};\n\nstruct ehci_platform_priv {\n\tstruct clk *clks[4];\n\tstruct reset_control *rsts;\n\tbool reset_on_resume;\n\tbool quirk_poll;\n\tstruct timer_list poll_timer;\n\tstruct delayed_work poll_work;\n};\n\nstruct ehci_qtd;\n\nstruct ehci_qh {\n\tstruct ehci_qh_hw *hw;\n\tdma_addr_t qh_dma;\n\tunion ehci_shadow qh_next;\n\tstruct list_head qtd_list;\n\tstruct list_head intr_node;\n\tstruct ehci_qtd *dummy;\n\tstruct list_head unlink_node;\n\tstruct ehci_per_sched ps;\n\tunsigned int unlink_cycle;\n\tu8 qh_state;\n\tu8 xacterrs;\n\tu8 unlink_reason;\n\tu8 gap_uf;\n\tunsigned int is_out: 1;\n\tunsigned int clearing_tt: 1;\n\tunsigned int dequeue_during_giveback: 1;\n\tunsigned int should_be_inactive: 1;\n};\n\nstruct ehci_qh_hw {\n\t__le32 hw_next;\n\t__le32 hw_info1;\n\t__le32 hw_info2;\n\t__le32 hw_current;\n\t__le32 hw_qtd_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ehci_qtd {\n\t__le32 hw_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tdma_addr_t qtd_dma;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tunion {\n\t\tu32 port_status[15];\n\t\tstruct {\n\t\t\tu32 reserved3[9];\n\t\t\tu32 usbmode;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved4;\n\t\t\tu32 hostpc[15];\n\t\t};\n\t\tu32 brcm_insnreg[4];\n\t};\n\tu32 reserved5[2];\n\tu32 usbmode_ex;\n};\n\nstruct ehci_sitd {\n\t__le32 hw_next;\n\t__le32 hw_fullspeed_ep;\n\t__le32 hw_uframe;\n\t__le32 hw_results;\n\t__le32 hw_buf[2];\n\t__le32 hw_backpointer;\n\t__le32 hw_buf_hi[2];\n\tdma_addr_t sitd_dma;\n\tunion ehci_shadow sitd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head sitd_list;\n\tunsigned int frame;\n\tunsigned int index;\n};\n\nstruct usb_tt;\n\nstruct ehci_tt {\n\tu16 bandwidth[8];\n\tstruct list_head tt_list;\n\tstruct list_head ps_list;\n\tstruct usb_tt *usb_tt;\n\tint tt_port;\n};\n\nstruct eic7700_priv {\n\tstruct reset_control *reset;\n\tunsigned int drive_impedance;\n};\n\nstruct elevator_queue;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf32_shdr {\n\tElf32_Word sh_name;\n\tElf32_Word sh_type;\n\tElf32_Word sh_flags;\n\tElf32_Addr sh_addr;\n\tElf32_Off sh_offset;\n\tElf32_Word sh_size;\n\tElf32_Word sh_link;\n\tElf32_Word sh_info;\n\tElf32_Word sh_addralign;\n\tElf32_Word sh_entsize;\n};\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_note {\n\tElf64_Word n_namesz;\n\tElf64_Word n_descsz;\n\tElf64_Word n_type;\n};\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct elf64_rela {\n\tElf64_Addr r_offset;\n\tElf64_Xword r_info;\n\tElf64_Sxword r_addend;\n};\n\ntypedef struct elf64_rela Elf64_Rela;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\ntypedef struct elf64_shdr Elf64_Shdr;\n\nstruct elf64_sym {\n\tElf64_Word st_name;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf64_Half st_shndx;\n\tElf64_Addr st_value;\n\tElf64_Xword st_size;\n};\n\ntypedef struct elf64_sym Elf64_Sym;\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tcompat_siginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info___2;\n\nstruct elf_note_info___2 {\n\tstruct elf_thread_core_info___2 *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\ntypedef struct user_regs_struct elf_gregset_t;\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info___2 {\n\tstruct elf_thread_core_info___2 *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct compat_elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_data_callback {};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct trace_event_file;\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\nstruct usb_endpoint_descriptor;\n\nstruct ep_device {\n\tstruct usb_endpoint_descriptor *desc;\n\tstruct usb_device *udev;\n\tstruct device dev;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct ephy_info {\n\tunsigned int offset;\n\tu16 mask;\n\tu16 bits;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n} __attribute__((packed));\n\nstruct epoll_event {\n\t__poll_t events;\n\t__u64 data;\n};\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct trace_eprobe;\n\nstruct eprobe_data {\n\tstruct trace_event_file *file;\n\tstruct trace_eprobe *ep;\n};\n\nstruct eprobe_trace_entry_head {\n\tstruct trace_entry ent;\n};\n\nstruct erase_info {\n\tuint64_t addr;\n\tuint64_t len;\n\tuint64_t fail_addr;\n};\n\nstruct erase_info_user {\n\t__u32 start;\n\t__u32 length;\n};\n\nstruct erase_info_user64 {\n\t__u64 start;\n\t__u64 length;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu16 pos;\n\tu64 ts;\n};\n\nstruct errata_info_t {\n\tchar name[32];\n\tbool (*check_func)(long unsigned int, long unsigned int);\n};\n\nstruct errormap {\n\tchar *name;\n\tint val;\n\tint namelen;\n\tstruct hlist_node list;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct esre_entry;\n\nstruct esre_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct esre_entry *, char *);\n};\n\nstruct esre_entry {\n\tunion {\n\t\tstruct efi_system_resource_entry_v1 *esre1;\n\t} esre;\n\tstruct kobject kobj;\n\tstruct list_head list;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[2];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[2];\n\t\tlong unsigned int advertising[2];\n\t\tlong unsigned int lp_advertising[2];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_regs;\n\nstruct ethtool_wolinfo;\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_test;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxnfc;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_ts_stats;\n\nstruct ethtool_tunable;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_device;\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\t__u64 ring_cookie;\n\t__u32 location;\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rx_fs_item {\n\tstruct ethtool_rx_flow_spec fs;\n\tstruct list_head list;\n};\n\nstruct ethtool_rx_fs_list {\n\tstruct list_head list;\n\tunsigned int count;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct input_handler;\n\nstruct input_value;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct fasync_struct;\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct event_trigger_data;\n\nstruct ring_buffer_event;\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*parse)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*trigger)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tbool (*count_func)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_data *);\n};\n\nstruct event_counter {\n\tu32 count;\n\tu32 flags;\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nstruct event_header {\n\t__be16 data_len;\n\t__u8 notification_class: 3;\n\t__u8 reserved1: 4;\n\t__u8 nea: 1;\n\t__u8 supp_event_class;\n};\n\nstruct event_mod_load {\n\tstruct list_head list;\n\tchar *module;\n\tchar *match;\n\tchar *system;\n\tchar *event;\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tint flags;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n\tstruct llist_node llist;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventfs_attr {\n\tint mode;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\ntypedef int (*eventfs_callback)(const char *, umode_t *, void **, const struct file_operations **);\n\ntypedef void (*eventfs_release)(const char *, void *);\n\nstruct eventfs_entry {\n\tconst char *name;\n\teventfs_callback callback;\n\teventfs_release release;\n};\n\nstruct eventfs_inode {\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head children;\n\tconst struct eventfs_entry *entries;\n\tconst char *name;\n\tstruct eventfs_attr *entry_attrs;\n\tvoid *data;\n\tstruct eventfs_attr attr;\n\tstruct kref kref;\n\tunsigned int is_freed: 1;\n\tunsigned int is_events: 1;\n\tunsigned int nr_entries: 30;\n\tunsigned int ino;\n};\n\nstruct eventfs_root_inode {\n\tstruct eventfs_inode ei;\n\tstruct dentry *events_dir;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n};\n\nstruct ewma_pkt_len {\n\tlong unsigned int internal;\n};\n\nstruct exar8250_board;\n\nstruct exar8250 {\n\tunsigned int nr;\n\tunsigned int osc_freq;\n\tstruct exar8250_board *board;\n\tstruct eeprom_93cx6 eeprom;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tconst struct serial_rs485 *rs485_supported;\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n\tvoid (*unregister_gpio)(struct uart_8250_port *);\n};\n\nstruct exception_table_entry {\n\tint insn;\n\tint fixup;\n\tshort int type;\n\tshort int data;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct exit_boot_struct {\n\tstruct efi_boot_memmap *boot_memmap;\n\tefi_memory_desc_t *runtime_map;\n\tint runtime_entry_count;\n\tvoid *new_fdt_addr;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct iattr;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_buddy;\n\nstruct ext4_prealloc_space;\n\nstruct ext4_locality_group;\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\text4_grpblk_t ac_orig_goal_len;\n\text4_group_t ac_prefetch_grp;\n\tunsigned int ac_prefetch_ios;\n\tunsigned int ac_prefetch_nr;\n\tint ac_first_err;\n\t__u32 ac_flags;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_cX_found[5];\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct ext4_buddy *ac_e4b;\n\tstruct folio *ac_bitmap_folio;\n\tstruct folio *ac_buddy_folio;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_group_info;\n\nstruct ext4_buddy {\n\tstruct folio *bd_buddy_folio;\n\tvoid *bd_buddy;\n\tstruct folio *bd_bitmap_folio;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_hash {\n\t__le32 hash;\n\t__le32 minor_hash;\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\nstruct ext4_err_translation {\n\tint code;\n\tint errno;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct extent_status;\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_extent;\n\nstruct ext4_extent_idx;\n\nstruct ext4_extent_header;\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_fc_add_range {\n\t__le32 fc_ino;\n\t__u8 fc_ex[12];\n};\n\nstruct ext4_fc_alloc_region {\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tint ino;\n\tint len;\n};\n\nstruct ext4_fc_del_range {\n\t__le32 fc_ino;\n\t__le32 fc_lblk;\n\t__le32 fc_len;\n};\n\nstruct ext4_fc_dentry_info {\n\t__le32 fc_parent_ino;\n\t__le32 fc_ino;\n\t__u8 fc_dname[0];\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n};\n\nstruct ext4_fc_dentry_update {\n\tint fcd_op;\n\tint fcd_parent;\n\tint fcd_ino;\n\tstruct name_snapshot fcd_name;\n\tstruct list_head fcd_list;\n\tstruct list_head fcd_dilist;\n};\n\nstruct ext4_fc_head {\n\t__le32 fc_features;\n\t__le32 fc_tid;\n};\n\nstruct ext4_fc_inode {\n\t__le32 fc_ino;\n\t__u8 fc_raw_inode[0];\n};\n\nstruct ext4_fc_replay_state {\n\tint fc_replay_num_tags;\n\tint fc_replay_expected_off;\n\tint fc_current_pass;\n\tint fc_cur_tag;\n\tint fc_crc;\n\tstruct ext4_fc_alloc_region *fc_regions;\n\tint fc_regions_size;\n\tint fc_regions_used;\n\tint fc_regions_valid;\n\tint *fc_modified_inodes;\n\tint fc_modified_inodes_used;\n\tint fc_modified_inodes_size;\n};\n\nstruct ext4_fc_stats {\n\tunsigned int fc_ineligible_reason_count[13];\n\tlong unsigned int fc_num_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_failed_commits;\n\tlong unsigned int fc_skipped_commits;\n\tlong unsigned int fc_numblks;\n\tu64 s_fc_avg_commit_time;\n};\n\nstruct ext4_fc_tail {\n\t__le32 fc_tid;\n\t__le32 fc_crc;\n};\n\nstruct ext4_fc_tl {\n\t__le16 fc_tag;\n\t__le16 fc_len;\n};\n\nstruct ext4_fc_tl_mem {\n\tu16 fc_tag;\n\tu16 fc_len;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nstruct fscrypt_dummy_policy {};\n\nstruct ext4_fs_context {\n\tchar *s_qf_names[3];\n\tstruct fscrypt_dummy_policy dummy_enc_policy;\n\tint s_jquota_fmt;\n\tshort unsigned int qname_spec;\n\tlong unsigned int vals_s_flags;\n\tlong unsigned int mask_s_flags;\n\tlong unsigned int journal_devnum;\n\tlong unsigned int s_commit_interval;\n\tlong unsigned int s_stripe;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_want_extra_isize;\n\tunsigned int s_li_wait_mult;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int journal_ioprio;\n\tunsigned int vals_s_mount_opt;\n\tunsigned int mask_s_mount_opt;\n\tunsigned int vals_s_mount_opt2;\n\tunsigned int mask_s_mount_opt2;\n\tunsigned int opt_flags;\n\tunsigned int spec;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\text4_fsblk_t s_sb_block;\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\nstruct ext4_getfsmap_info;\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\tint bb_avg_fragment_size_order;\n\text4_grpblk_t bb_largest_free_order;\n\text4_group_t bb_group;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct jbd2_inode;\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tunion {\n\t\tstruct list_head i_orphan;\n\t\tunsigned int i_orphan_idx;\n\t};\n\tstruct list_head i_fc_dilist;\n\tstruct list_head i_fc_list;\n\text4_lblk_t i_fc_lblk_start;\n\text4_lblk_t i_fc_lblk_len;\n\tspinlock_t i_raw_lock;\n\twait_queue_head_t i_fc_wait;\n\tspinlock_t i_fc_lock;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tstruct timespec64 i_crtime;\n\tatomic_t i_prealloc_active;\n\tunsigned int i_reserved_data_blocks;\n\tstruct rb_root i_prealloc_node;\n\trwlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\tu64 i_es_seq;\n\text4_group_t i_last_alloc_group;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tspinlock_t i_block_reservation_lock;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\trefcount_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n};\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tsector_t io_next_block;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct ext4_journal_trigger {\n\tstruct jbd2_buffer_trigger_type tr_triggers;\n\tstruct super_block *sb;\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tenum ext4_li_mode lr_mode;\n\text4_group_t lr_first_not_zeroed;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n\tu64 m_seq;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n};\n\nstruct ext4_new_group_data;\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t resize_bg;\n\text4_group_t count;\n};\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct ext4_orphan_block {\n\tatomic_t ob_free_entries;\n\tstruct buffer_head *ob_bh;\n};\n\nstruct ext4_orphan_block_tail {\n\t__le32 ob_magic;\n\t__le32 ob_checksum;\n};\n\nstruct ext4_orphan_info {\n\tint of_blocks;\n\t__u32 of_csum_seed;\n\tstruct ext4_orphan_block *of_binfo;\n};\n\nstruct ext4_prealloc_space {\n\tunion {\n\t\tstruct rb_node inode_node;\n\t\tstruct list_head lg_list;\n\t} pa_node;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tunion {\n\t\trwlock_t *inode_lock;\n\t\tspinlock_t *lg_lock;\n\t} pa_node_lock;\n\tstruct inode *pa_inode;\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct ext4_super_block;\n\nstruct journal_s;\n\nstruct ext4_system_blocks;\n\nstruct flex_groups;\n\nstruct shrinker;\n\nstruct mb_cache;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tlong unsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\tunsigned int s_def_mount_opt2;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct percpu_counter s_sra_exceeded_retry_limit;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct buffer_head *s_mmp_bh;\n\tstruct journal_s *s_journal;\n\tlong unsigned int s_ext4_flags;\n\tstruct mutex s_orphan_lock;\n\tstruct list_head s_orphan;\n\tstruct ext4_orphan_info s_orphan_info;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct file *s_journal_bdev_file;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *s_system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tatomic_t s_mb_free_pending;\n\tstruct list_head s_freed_data_list[2];\n\tstruct list_head s_discard_list;\n\tstruct work_struct s_discard_work;\n\tatomic_t s_retry_alloc_pending;\n\tstruct xarray *s_mb_avg_fragment_size;\n\tstruct xarray *s_mb_largest_free_orders;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_max_linear_groups;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int s_mb_prefetch;\n\tunsigned int s_mb_prefetch_limit;\n\tunsigned int s_mb_best_avail_max_trim_order;\n\tunsigned int s_sb_update_sec;\n\tunsigned int s_sb_update_kb;\n\text4_group_t *s_mb_last_groups;\n\tunsigned int s_mb_nr_global_goals;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_cX_ex_scanned[5];\n\tatomic_t s_bal_groups_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_stream_goals;\n\tatomic_t s_bal_len_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tatomic64_t s_bal_cX_groups_considered[5];\n\tatomic64_t s_bal_cX_hits[5];\n\tatomic64_t s_bal_cX_failed[5];\n\tatomic_t s_mb_buddies_generated;\n\tatomic64_t s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tlong unsigned int s_err_report_sec;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tlong unsigned int s_last_trim_minblks;\n\tu16 s_min_folio_order;\n\tu16 s_max_folio_order;\n\t__u32 s_csum_seed;\n\tstruct shrinker *s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache *s_ea_block_cache;\n\tstruct mb_cache *s_ea_inode_cache;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_es_lock;\n\tstruct ext4_journal_trigger s_journal_triggers[1];\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tatomic_t s_warning_count;\n\tatomic_t s_msg_count;\n\tstruct fscrypt_dummy_policy s_dummy_enc_policy;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tu64 s_dax_part_off;\n\terrseq_t s_bdev_wb_err;\n\tspinlock_t s_bdev_wb_lock;\n\tspinlock_t s_error_lock;\n\tint s_add_error_count;\n\tint s_first_error_code;\n\t__u32 s_first_error_line;\n\t__u32 s_first_error_ino;\n\t__u64 s_first_error_block;\n\tconst char *s_first_error_func;\n\ttime64_t s_first_error_time;\n\tint s_last_error_code;\n\t__u32 s_last_error_line;\n\t__u32 s_last_error_ino;\n\t__u64 s_last_error_block;\n\tconst char *s_last_error_func;\n\ttime64_t s_last_error_time;\n\tstruct work_struct s_sb_upd_work;\n\tunsigned int s_awu_min;\n\tunsigned int s_awu_max;\n\tatomic_t s_fc_subtid;\n\tstruct list_head s_fc_q[2];\n\tstruct list_head s_fc_dentry_q[2];\n\tunsigned int s_fc_bytes;\n\tstruct mutex s_fc_lock;\n\tstruct buffer_head *s_fc_bh;\n\tstruct ext4_fc_stats s_fc_stats;\n\ttid_t s_fc_ineligible_tid;\n\tstruct ext4_fc_replay_state s_fc_replay_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_orphan_file_inum;\n\t__le16 s_def_resuid_hi;\n\t__le16 s_def_resgid_hi;\n\t__le32 s_reserved[93];\n\t__le32 s_checksum;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n\tu32 ino;\n};\n\nstruct ext4_tune_sb_params {\n\t__u32 set_flags;\n\t__u32 checkinterval;\n\t__u16 errors_behavior;\n\t__u16 mnt_count;\n\t__u16 max_mnt_count;\n\t__u16 raid_stride;\n\t__u64 last_check_time;\n\t__u64 reserved_blocks;\n\t__u64 blocks_count;\n\t__u32 default_mnt_opts;\n\t__u32 reserved_uid;\n\t__u32 reserved_gid;\n\t__u32 raid_stripe_width;\n\t__u16 encoding;\n\t__u16 encoding_flags;\n\t__u8 def_hash_alg;\n\t__u8 pad_1;\n\t__u16 pad_2;\n\t__u32 feature_compat;\n\t__u32 feature_incompat;\n\t__u32 feature_ro_compat;\n\t__u32 set_feature_compat_mask;\n\t__u32 set_feature_incompat_mask;\n\t__u32 set_feature_ro_compat_mask;\n\t__u32 clear_feature_compat_mask;\n\t__u32 clear_feature_incompat_mask;\n\t__u32 clear_feature_ro_compat_mask;\n\t__u8 mount_opts[64];\n\t__u8 pad[68];\n};\n\nstruct ext4_xattr_entry;\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n};\n\nstruct msg_msg;\n\nstruct ext_wait_queue {\n\tstruct task_struct *task;\n\tstruct list_head list;\n\tstruct msg_msg *msg;\n\tint state;\n};\n\nunion extcon_property_value {\n\tint intval;\n};\n\nstruct extcon_dev;\n\nstruct extcon_cable {\n\tstruct extcon_dev *edev;\n\tint cable_index;\n\tstruct attribute_group attr_g;\n\tstruct device_attribute attr_name;\n\tstruct device_attribute attr_state;\n\tstruct attribute *attrs[3];\n\tunion extcon_property_value usb_propval[3];\n\tunion extcon_property_value chg_propval[1];\n\tunion extcon_property_value jack_propval[1];\n\tunion extcon_property_value disp_propval[2];\n\tlong unsigned int usb_bits[1];\n\tlong unsigned int chg_bits[1];\n\tlong unsigned int jack_bits[1];\n\tlong unsigned int disp_bits[1];\n};\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct extcon_dev {\n\tconst char *name;\n\tconst unsigned int *supported_cable;\n\tconst u32 *mutually_exclusive;\n\tstruct device dev;\n\tunsigned int id;\n\tstruct raw_notifier_head nh_all;\n\tstruct raw_notifier_head *nh;\n\tstruct list_head entry;\n\tint max_supported;\n\tspinlock_t lock;\n\tu32 state;\n\tstruct device_type extcon_dev_type;\n\tstruct extcon_cable *cables;\n\tstruct attribute_group attr_g_muex;\n\tstruct attribute **attrs_muex;\n\tstruct device_attribute *d_attrs_muex;\n};\n\nstruct extcon_dev_notifier_devres {\n\tstruct extcon_dev *edev;\n\tunsigned int id;\n\tstruct notifier_block *nb;\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\text4_fsblk_t es_pblk;\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct failover_ops;\n\nstruct failover {\n\tstruct list_head list;\n\tstruct net_device *failover_dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct failover_ops *ops;\n};\n\nstruct failover_ops {\n\tint (*slave_pre_register)(struct net_device *, struct net_device *);\n\tint (*slave_register)(struct net_device *, struct net_device *);\n\tint (*slave_pre_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_link_change)(struct net_device *, struct net_device *);\n\tint (*slave_name_change)(struct net_device *, struct net_device *);\n\trx_handler_result_t (*slave_handle_frame)(struct sk_buff **);\n};\n\nstruct fanotify_response_info_header {\n\t__u8 type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_response_info_audit_rule {\n\tstruct fanotify_response_info_header hdr;\n\t__u32 rule_number;\n\t__u32 subj_trust;\n\t__u32 obj_trust;\n};\n\nstruct fanout_args {\n\t__u16 id;\n\t__u16 type_flags;\n\t__u32 max_num_members;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_bios_param_block {\n\tu16 fat_sector_size;\n\tu8 fat_sec_per_clus;\n\tu16 fat_reserved;\n\tu8 fat_fats;\n\tu16 fat_dir_entries;\n\tu16 fat_sectors;\n\tu16 fat_fat_length;\n\tu32 fat_total_sect;\n\tu8 fat16_state;\n\tu32 fat16_vol_id;\n\tu32 fat32_length;\n\tu32 fat32_root_cluster;\n\tu16 fat32_info_sector;\n\tu8 fat32_state;\n\tu32 fat32_vol_id;\n};\n\nstruct fat_boot_fsinfo {\n\t__le32 signature1;\n\t__le32 reserved1[120];\n\t__le32 signature2;\n\t__le32 free_clusters;\n\t__le32 next_cluster;\n\t__le32 reserved2[4];\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fat_cache {\n\tstruct list_head cache_list;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_cache_id {\n\tunsigned int id;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_entry {\n\tint entry;\n\tunion {\n\t\tu8 *ent12_p[2];\n\t\t__le16 *ent16_p;\n\t\t__le32 *ent32_p;\n\t} u;\n\tint nr_bhs;\n\tstruct buffer_head *bhs[2];\n\tstruct inode *fat_inode;\n};\n\nstruct fat_fid {\n\tu32 i_gen;\n\tu32 i_pos_low;\n\tu16 i_pos_hi;\n\tu16 parent_i_pos_hi;\n\tu32 parent_i_pos_low;\n\tu32 parent_i_gen;\n};\n\nstruct fat_floppy_defaults {\n\tunsigned int nr_sectors;\n\tunsigned int sec_per_clus;\n\tunsigned int dir_entries;\n\tunsigned int media;\n\tunsigned int fat_length;\n};\n\nstruct fat_ioctl_filldir_callback {\n\tstruct dir_context ctx;\n\tvoid *dirent;\n\tint result;\n\tconst char *longname;\n\tint long_len;\n\tconst char *shortname;\n\tint short_len;\n};\n\nstruct fat_mount_options {\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tshort unsigned int fs_fmask;\n\tshort unsigned int fs_dmask;\n\tshort unsigned int codepage;\n\tint time_offset;\n\tchar *iocharset;\n\tshort unsigned int shortname;\n\tunsigned char name_check;\n\tunsigned char errors;\n\tunsigned char nfs;\n\tshort unsigned int allow_utime;\n\tunsigned int quiet: 1;\n\tunsigned int showexec: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int dotsOK: 1;\n\tunsigned int isvfat: 1;\n\tunsigned int utf8: 1;\n\tunsigned int unicode_xlate: 1;\n\tunsigned int numtail: 1;\n\tunsigned int flush: 1;\n\tunsigned int nocase: 1;\n\tunsigned int usefree: 1;\n\tunsigned int tz_set: 1;\n\tunsigned int rodir: 1;\n\tunsigned int discard: 1;\n\tunsigned int dos1xfloppy: 1;\n\tunsigned int debug: 1;\n};\n\nstruct msdos_dir_entry;\n\nstruct fat_slot_info {\n\tloff_t i_pos;\n\tloff_t slot_off;\n\tint nr_slots;\n\tstruct msdos_dir_entry *de;\n\tstruct buffer_head *bh;\n};\n\nstruct fatent_operations {\n\tvoid (*ent_blocknr)(struct super_block *, int, int *, sector_t *);\n\tvoid (*ent_set_ptr)(struct fat_entry *, int);\n\tint (*ent_bread)(struct super_block *, struct fat_entry *, int, sector_t);\n\tint (*ent_get)(struct fat_entry *);\n\tvoid (*ent_put)(struct fat_entry *, int);\n\tint (*ent_next)(struct fat_entry *);\n};\n\nstruct fatent_ra {\n\tsector_t cur;\n\tsector_t limit;\n\tunsigned int ra_blocks;\n\tsector_t ra_advance;\n\tsector_t ra_next;\n\tsector_t ra_limit;\n};\n\nstruct fault_attr {};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_address {\n\tvoid *address;\n\tint bits;\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_bitmap4x_iter {\n\tconst u8 *data;\n\tu32 fgxcolor;\n\tu32 bgcolor;\n\tint width;\n\tint i;\n\tconst u32 *expand;\n\tint bpp;\n\tbool top;\n};\n\nstruct fb_bitmap_iter {\n\tconst u8 *data;\n\tlong unsigned int colors[2];\n\tint width;\n\tint i;\n};\n\nstruct fb_blit_caps {\n\tlong unsigned int x[1];\n\tlong unsigned int y[2];\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_cmap32 {\n\tu32 start;\n\tu32 len;\n\tcompat_caddr_t red;\n\tcompat_caddr_t green;\n\tcompat_caddr_t blue;\n\tcompat_caddr_t transp;\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_reverse {\n\tbool byte;\n\tbool pixel;\n};\n\nstruct fb_color_iter {\n\tconst u8 *data;\n\tconst u32 *palette;\n\tstruct fb_reverse reverse;\n\tint shift;\n\tint width;\n\tint i;\n};\n\nstruct fb_con2fbmap {\n\t__u32 console;\n\t__u32 framebuffer;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\nstruct fb_info;\n\nstruct fb_deferred_io {\n\tlong unsigned int delay;\n\tbool sort_pagereflist;\n\tint open_count;\n\tstruct mutex lock;\n\tstruct list_head pagereflist;\n\tstruct address_space *mapping;\n\tstruct page * (*get_page)(struct fb_info *, long unsigned int);\n\tvoid (*deferred_io)(struct fb_info *, struct list_head *);\n};\n\nstruct fb_deferred_io_pageref {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tstruct list_head list;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_fix_screeninfo32 {\n\tchar id[16];\n\tcompat_caddr_t smem_start;\n\tu32 smem_len;\n\tu32 type;\n\tu32 type_aux;\n\tu32 visual;\n\tu16 xpanstep;\n\tu16 ypanstep;\n\tu16 ywrapstep;\n\tu32 line_length;\n\tcompat_caddr_t mmio_start;\n\tu32 mmio_len;\n\tu32 accel;\n\tu16 reserved[3];\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_videomode;\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tlong unsigned int blit_x[1];\n\tlong unsigned int blit_y[2];\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct lcd_device;\n\nstruct fb_ops;\n\nstruct fbcon_par;\n\nstruct fb_info {\n\trefcount_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tint blank;\n\tstruct lcd_device *lcd_dev;\n\tstruct delayed_work deferred_work;\n\tlong unsigned int npagerefs;\n\tstruct fb_deferred_io_pageref *pagerefs;\n\tstruct fb_deferred_io *fbdefio;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tstruct device *dev;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tstruct fbcon_par *fbcon_par;\n\tvoid *par;\n\tbool skip_vt_switch;\n\tbool skip_panic;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n};\n\nstruct fb_pattern {\n\tlong unsigned int pixels;\n\tint left;\n\tint right;\n\tstruct fb_reverse reverse;\n};\n\nstruct fbcon_bitops {\n\tvoid (*bmove)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*clear)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*putcs)(struct vc_data *, struct fb_info *, const short unsigned int *, int, int, int, int, int);\n\tvoid (*clear_margins)(struct vc_data *, struct fb_info *, int, int);\n\tvoid (*cursor)(struct vc_data *, struct fb_info *, bool, int, int);\n\tint (*update_start)(struct fb_info *);\n\tint (*rotate_font)(struct fb_info *, struct vc_data *);\n};\n\nstruct fbcon_display {\n\tconst u_char *fontdata;\n\tint userfont;\n\tshort int yscroll;\n\tint vrows;\n\tint cursor_shape;\n\tint con_rotate;\n\tu32 xres_virtual;\n\tu32 yres_virtual;\n\tu32 height;\n\tu32 width;\n\tu32 bits_per_pixel;\n\tu32 grayscale;\n\tu32 nonstd;\n\tu32 accel_flags;\n\tu32 rotate;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tconst struct fb_videomode *mode;\n};\n\nstruct fbcon_par {\n\tstruct fb_var_screeninfo var;\n\tstruct delayed_work cursor_work;\n\tstruct fb_cursor cursor_state;\n\tstruct fbcon_display *p;\n\tstruct fb_info *info;\n\tint currcon;\n\tint cur_blink_jiffies;\n\tint cursor_flash;\n\tint cursor_reset;\n\tint blank_state;\n\tint graphics;\n\tbool initialized;\n\tint rotate;\n\tint cur_rotate;\n\tchar *cursor_data;\n\tu8 *fontbuffer;\n\tu8 *fontdata;\n\tu8 *cursor_src;\n\tu32 cursor_size;\n\tu32 fd_size;\n\tconst struct fbcon_bitops *bitops;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdt_errtabent {\n\tconst char *str;\n};\n\nstruct fdt_header {\n\tfdt32_t magic;\n\tfdt32_t totalsize;\n\tfdt32_t off_dt_struct;\n\tfdt32_t off_dt_strings;\n\tfdt32_t off_mem_rsvmap;\n\tfdt32_t version;\n\tfdt32_t last_comp_version;\n\tfdt32_t boot_cpuid_phys;\n\tfdt32_t size_dt_strings;\n\tfdt32_t size_dt_struct;\n};\n\nstruct fdt_node_header {\n\tfdt32_t tag;\n\tchar name[0];\n};\n\nstruct fdt_property {\n\tfdt32_t tag;\n\tfdt32_t len;\n\tfdt32_t nameoff;\n\tchar data[0];\n};\n\nstruct fdt_reserve_entry {\n\tfdt64_t address;\n\tfdt64_t size;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[2];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct trace_seq;\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tbool is_signed;\n\tbool is_string;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[2];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct ff_periodic_effect_compat {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\tcompat_uptr_t custom_data;\n};\n\nstruct ff_effect_compat {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect_compat periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t} u;\n};\n\nstruct fib6_node;\n\nstruct fib6_walker {\n\tstruct list_head lh;\n\tstruct fib6_node *root;\n\tstruct fib6_node *node;\n\tstruct fib6_info *leaf;\n\tenum fib6_walk_state state;\n\tunsigned int skip;\n\tunsigned int count;\n\tunsigned int skip_in_node;\n\tint (*func)(struct fib6_walker *);\n\tvoid *args;\n};\n\nstruct fib6_cleaner {\n\tstruct fib6_walker w;\n\tstruct net *net;\n\tint (*func)(struct fib6_info *, void *);\n\tint sernum;\n\tvoid *arg;\n\tbool skip_notify;\n};\n\nstruct nlmsghdr;\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct fib6_dump_arg {\n\tstruct net *net;\n\tstruct notifier_block *nb;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib6_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib6_info *rt;\n\tunsigned int nsiblings;\n};\n\nstruct fib6_gc_args {\n\tint timeout;\n\tint more;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_nh_age_excptn_arg {\n\tstruct fib6_gc_args *gc_args;\n\tlong unsigned int now;\n};\n\nstruct fib6_nh_del_cached_rt_arg {\n\tstruct fib6_config *cfg;\n\tstruct fib6_info *f6i;\n};\n\nstruct fib6_nh_dm_arg {\n\tstruct net *net;\n\tconst struct in6_addr *saddr;\n\tint oif;\n\tint flags;\n\tstruct fib6_nh *nh;\n};\n\nstruct rt6_rtnl_dump_arg;\n\nstruct fib6_nh_exception_dump_walker {\n\tstruct rt6_rtnl_dump_arg *dump;\n\tstruct fib6_info *rt;\n\tunsigned int flags;\n\tunsigned int skip;\n\tunsigned int count;\n};\n\nstruct fib6_nh_excptn_arg {\n\tstruct rt6_info *rt;\n\tint plen;\n};\n\nstruct fib6_nh_frl_arg {\n\tu32 flags;\n\tint oif;\n\tint strict;\n\tint *mpri;\n\tbool *do_rr;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_match_arg {\n\tconst struct net_device *dev;\n\tconst struct in6_addr *gw;\n\tstruct fib6_nh *match;\n};\n\nstruct fib6_result;\n\nstruct flowi6;\n\nstruct fib6_nh_rd_arg {\n\tstruct fib6_result *res;\n\tstruct flowi6 *fl6;\n\tconst struct in6_addr *gw;\n\tstruct rt6_info **ret;\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_kuid_range {\n\tkuid_t start;\n\tkuid_t end;\n};\n\nstruct fib_rule;\n\nstruct fib_lookup_arg {\n\tvoid *lookup_ptr;\n\tconst void *lookup_data;\n\tvoid *result;\n\tstruct fib_rule *rule;\n\tu32 table;\n\tint flags;\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tloff_t pos;\n\tt_key key;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_rule_port_range {\n\t__u16 start;\n\t__u16 end;\n};\n\nstruct fib_rule {\n\tstruct list_head list;\n\tint iifindex;\n\tint oifindex;\n\tu32 mark;\n\tu32 mark_mask;\n\tu32 flags;\n\tu32 table;\n\tu8 action;\n\tu8 l3mdev;\n\tu8 proto;\n\tu8 ip_proto;\n\tu32 target;\n\t__be64 tun_id;\n\tstruct fib_rule *ctarget;\n\tstruct net *fr_net;\n\trefcount_t refcnt;\n\tu32 pref;\n\tint suppress_ifgroup;\n\tint suppress_prefixlen;\n\tchar iifname[16];\n\tchar oifname[16];\n\tstruct fib_kuid_range uid_range;\n\tstruct fib_rule_port_range sport_range;\n\tstruct fib_rule_port_range dport_range;\n\tu16 sport_mask;\n\tu16 dport_mask;\n\tu8 iif_is_l3_master;\n\tu8 oif_is_l3_master;\n\tstruct callback_head rcu;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} __attribute__((packed)) i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct io_uring_cmd;\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct file_range {\n\tconst struct path *path;\n\tloff_t pos;\n\tsize_t count;\n};\n\nstruct page_counter;\n\nstruct file_region {\n\tstruct list_head link;\n\tlong int from;\n\tlong int to;\n\tstruct page_counter *reservation_counter;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct file_security_struct {\n\tu32 sid;\n\tu32 fown_sid;\n\tu32 isid;\n\tu32 pseqno;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[168];\n};\n\nstruct filename_trans_datum {\n\tstruct ebitmap stypes;\n\tu32 otype;\n\tstruct filename_trans_datum *next;\n};\n\nstruct filename_trans_key {\n\tu32 ttype;\n\tu16 tclass;\n\tconst char *name;\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct filter_head {\n\tstruct list_head list;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rcu_work rwork;\n\t};\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\nstruct regex;\n\nstruct ftrace_event_field;\n\nstruct filter_pred {\n\tstruct regex *regex;\n\tstruct cpumask *mask;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tu64 val;\n\tu64 val2;\n\tenum filter_pred_fn fn_num;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nstruct find_child_walk_data {\n\tstruct acpi_device *adev;\n\tu64 address;\n\tint score;\n\tbool check_sta;\n\tbool check_children;\n};\n\nstruct find_interface_arg {\n\tint minor;\n\tstruct device_driver *drv;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct finfo {\n\tefi_file_info_t info;\n\tefi_char16_t filename[256];\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\nstruct fixed_dev_type {\n\tbool has_enable_clock;\n\tbool has_performance_state;\n};\n\nstruct mtd_partition;\n\nstruct fixed_partitions_quirks {\n\tint (*post_parse)(struct mtd_info *, struct mtd_partition *, int);\n};\n\nstruct fixed_phy_status {\n\tint speed;\n\tint duplex;\n\tbool link: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n};\n\nstruct fixed_phy {\n\tstruct phy_device *phydev;\n\tstruct fixed_phy_status status;\n\tint (*link_update)(struct net_device *, struct fixed_phy_status *);\n};\n\nstruct regulator_init_data;\n\nstruct fixed_voltage_config {\n\tconst char *supply_name;\n\tconst char *input_supply;\n\tint microvolts;\n\tunsigned int startup_delay;\n\tunsigned int off_on_delay;\n\tunsigned int enabled_at_boot: 1;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct regulator_state {\n\tint uV;\n\tint min_uV;\n\tint max_uV;\n\tunsigned int mode;\n\tint enabled;\n\tbool changeable;\n};\n\nstruct notification_limit {\n\tint prot;\n\tint err;\n\tint warn;\n};\n\nstruct regulation_constraints {\n\tconst char *name;\n\tint min_uV;\n\tint max_uV;\n\tint uV_offset;\n\tint min_uA;\n\tint max_uA;\n\tint ilim_uA;\n\tint pw_budget_mW;\n\tint system_load;\n\tu32 *max_spread;\n\tint max_uV_step;\n\tunsigned int valid_modes_mask;\n\tunsigned int valid_ops_mask;\n\tint input_uV;\n\tstruct regulator_state state_disk;\n\tstruct regulator_state state_mem;\n\tstruct regulator_state state_standby;\n\tstruct notification_limit over_curr_limits;\n\tstruct notification_limit over_voltage_limits;\n\tstruct notification_limit under_voltage_limits;\n\tstruct notification_limit temp_limits;\n\tsuspend_state_t initial_state;\n\tunsigned int initial_mode;\n\tunsigned int ramp_delay;\n\tunsigned int settling_time;\n\tunsigned int settling_time_up;\n\tunsigned int settling_time_down;\n\tunsigned int enable_time;\n\tunsigned int uv_less_critical_window_ms;\n\tunsigned int active_discharge;\n\tunsigned int always_on: 1;\n\tunsigned int boot_on: 1;\n\tunsigned int apply_uV: 1;\n\tunsigned int ramp_disable: 1;\n\tunsigned int soft_start: 1;\n\tunsigned int pull_down: 1;\n\tunsigned int system_critical: 1;\n\tunsigned int over_current_protection: 1;\n\tunsigned int over_current_detection: 1;\n\tunsigned int over_voltage_detection: 1;\n\tunsigned int under_voltage_detection: 1;\n\tunsigned int over_temp_detection: 1;\n};\n\nstruct regulator_consumer_supply;\n\nstruct regulator_init_data {\n\tconst char *supply_regulator;\n\tstruct regulation_constraints constraints;\n\tint num_consumer_supplies;\n\tstruct regulator_consumer_supply *consumer_supplies;\n\tvoid *driver_data;\n};\n\nstruct pdev_archdata {};\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct fixed_regulator_data {\n\tstruct fixed_voltage_config cfg;\n\tstruct regulator_init_data init_data;\n\tstruct platform_device pdev;\n};\n\nstruct regulator_config;\n\nstruct regulator_ops;\n\nstruct linear_range;\n\nstruct regulator_desc {\n\tconst char *name;\n\tconst char *supply_name;\n\tconst char *of_match;\n\tbool of_match_full_name;\n\tconst char *regulators_node;\n\tint (*of_parse_cb)(struct device_node *, const struct regulator_desc *, struct regulator_config *);\n\tint (*init_cb)(struct regulator_dev *, struct regulator_config *);\n\tint id;\n\tunsigned int continuous_voltage_range: 1;\n\tunsigned int n_voltages;\n\tunsigned int n_current_limits;\n\tconst struct regulator_ops *ops;\n\tint irq;\n\tenum regulator_type type;\n\tstruct module *owner;\n\tunsigned int min_uV;\n\tunsigned int uV_step;\n\tunsigned int linear_min_sel;\n\tint fixed_uV;\n\tunsigned int ramp_delay;\n\tint min_dropout_uV;\n\tconst struct linear_range *linear_ranges;\n\tconst unsigned int *linear_range_selectors_bitfield;\n\tint n_linear_ranges;\n\tconst unsigned int *volt_table;\n\tconst unsigned int *curr_table;\n\tunsigned int vsel_range_reg;\n\tunsigned int vsel_range_mask;\n\tbool range_applied_by_vsel;\n\tunsigned int vsel_reg;\n\tunsigned int vsel_mask;\n\tunsigned int vsel_step;\n\tunsigned int csel_reg;\n\tunsigned int csel_mask;\n\tunsigned int apply_reg;\n\tunsigned int apply_bit;\n\tunsigned int enable_reg;\n\tunsigned int enable_mask;\n\tunsigned int enable_val;\n\tunsigned int disable_val;\n\tbool enable_is_inverted;\n\tunsigned int bypass_reg;\n\tunsigned int bypass_mask;\n\tunsigned int bypass_val_on;\n\tunsigned int bypass_val_off;\n\tunsigned int active_discharge_on;\n\tunsigned int active_discharge_off;\n\tunsigned int active_discharge_mask;\n\tunsigned int active_discharge_reg;\n\tunsigned int soft_start_reg;\n\tunsigned int soft_start_mask;\n\tunsigned int soft_start_val_on;\n\tunsigned int pull_down_reg;\n\tunsigned int pull_down_mask;\n\tunsigned int pull_down_val_on;\n\tunsigned int ramp_reg;\n\tunsigned int ramp_mask;\n\tconst unsigned int *ramp_delay_table;\n\tunsigned int n_ramp_values;\n\tunsigned int enable_time;\n\tunsigned int off_on_delay;\n\tunsigned int poll_enabled_time;\n\tunsigned int (*of_map_mode)(unsigned int);\n};\n\nstruct fixed_voltage_data {\n\tstruct regulator_desc desc;\n\tstruct regulator_dev *dev;\n\tstruct clk *enable_clock;\n\tunsigned int enable_counter;\n\tint performance_state;\n};\n\nstruct spi_nor_id;\n\nstruct spi_nor_otp_organization;\n\nstruct spi_nor_fixups;\n\nstruct flash_info {\n\tchar *name;\n\tconst struct spi_nor_id *id;\n\tsize_t size;\n\tunsigned int sector_size;\n\tu16 page_size;\n\tu8 n_banks;\n\tu8 addr_nbytes;\n\tu16 flags;\n\tu8 no_sfdp_flags;\n\tu8 fixup_flags;\n\tu8 mfr_flags;\n\tconst struct spi_nor_otp_organization *otp;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct flash_platform_data {\n\tchar *name;\n\tstruct mtd_partition *parts;\n\tunsigned int nr_parts;\n\tchar *type;\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct flow_action_police {\n\tu32 burst;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n};\n\nstruct nf_flowtable;\n\nstruct ip_tunnel_info;\n\nstruct psample_group;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 0;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct flush_tlb_range_data {\n\tlong unsigned int asid;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int stride;\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nstruct page_pool;\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t\tlong unsigned int memcg_data;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tatomic_t _entire_mapcount;\n\t\t\t\t\tatomic_t _pincount;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t\tunsigned int _nr_pages;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct font_data {\n\tunsigned int extra[4];\n\tconst unsigned char data[0];\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tconst void *data;\n\tint pref;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhashtable rhashtable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct frag_queue {\n\tstruct inet_frag_queue q;\n\tint iif;\n\t__u16 nhoffset;\n\tu8 ecn;\n};\n\nstruct free_area {\n\tstruct list_head free_list[4];\n\tlong unsigned int nr_free;\n};\n\nstruct free_entry {\n\tu32 block;\n\tu8 sub;\n\tu8 seq;\n\tu8 has_err;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t\tshort unsigned int stride;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n};\n\nstruct freq_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpufreq_policy *, char *);\n\tssize_t (*store)(struct cpufreq_policy *, const char *, size_t);\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fscache_cache_ops;\n\nstruct fscache_cache {\n\tconst struct fscache_cache_ops *ops;\n\tstruct list_head cache_link;\n\tvoid *cache_priv;\n\trefcount_t ref;\n\tatomic_t n_volumes;\n\tatomic_t n_accesses;\n\tatomic_t object_count;\n\tunsigned int debug_id;\n\tenum fscache_cache_state state;\n\tchar *name;\n};\n\nstruct fscache_volume;\n\nstruct fscache_cookie;\n\nstruct netfs_cache_resources;\n\nstruct fscache_cache_ops {\n\tconst char *name;\n\tvoid (*acquire_volume)(struct fscache_volume *);\n\tvoid (*free_volume)(struct fscache_volume *);\n\tbool (*lookup_cookie)(struct fscache_cookie *);\n\tvoid (*withdraw_cookie)(struct fscache_cookie *);\n\tvoid (*resize_cookie)(struct netfs_cache_resources *, loff_t);\n\tbool (*invalidate_cookie)(struct fscache_cookie *);\n\tbool (*begin_operation)(struct netfs_cache_resources *, enum fscache_want_state);\n\tvoid (*prepare_to_write)(struct fscache_cookie *);\n};\n\nstruct fscache_cookie {\n\trefcount_t ref;\n\tatomic_t n_active;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n\tspinlock_t lock;\n\tstruct fscache_volume *volume;\n\tvoid *cache_priv;\n\tstruct hlist_bl_node hash_link;\n\tstruct list_head proc_link;\n\tstruct list_head commit_link;\n\tstruct work_struct work;\n\tloff_t object_size;\n\tlong unsigned int unused_at;\n\tlong unsigned int flags;\n\tenum fscache_cookie_state state;\n\tu8 advice;\n\tu8 key_len;\n\tu8 aux_len;\n\tu32 key_hash;\n\tunion {\n\t\tvoid *key;\n\t\tu8 inline_key[16];\n\t};\n\tunion {\n\t\tvoid *aux;\n\t\tu8 inline_aux[8];\n\t};\n};\n\nstruct fscache_volume {\n\trefcount_t ref;\n\tatomic_t n_cookies;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int key_hash;\n\tu8 *key;\n\tstruct list_head proc_link;\n\tstruct hlist_bl_node hash_link;\n\tstruct work_struct work;\n\tstruct fscache_cache *cache;\n\tvoid *cache_priv;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu8 coherency_len;\n\tu8 coherency[0];\n};\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_nokey_name;\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_io;\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu32 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n\tconst char *driver_override;\n};\n\nstruct fsl_mc_resource_pool;\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tunsigned int virq;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\traw_spinlock_t spinlock;\n\t};\n};\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct fsuuid {\n\t__u32 fsu_len;\n\t__u32 fsu_flags;\n\t__u8 fsu_uuid[0];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8156];\n};\n\nstruct tracer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tchar *fmt;\n\tunsigned int fmt_size;\n\tatomic_t wait_index;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool closed;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int spare_size;\n\tunsigned int read;\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int args[0];\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tunsigned int is_signed: 1;\n\tunsigned int needs_test: 1;\n\tint len;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct fu740_pcie {\n\tstruct dw_pcie pci;\n\tvoid *mgmt_base;\n\tstruct gpio_desc *reset;\n\tstruct gpio_desc *pwren;\n\tstruct clk *pcie_aux;\n\tstruct reset_control *rst;\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct func_repeats_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu16 count;\n\tu16 top_delta_ts;\n\tu32 bottom_delta_ts;\n};\n\nstruct pinfunction;\n\nstruct function_desc {\n\tconst struct pinfunction *func;\n\tvoid *data;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_info {\n\tu32 magic;\n\tchar version[32];\n\t__le32 fw_start;\n\t__le32 fw_len;\n\tu8 chksum;\n} __attribute__((packed));\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tsize_t offset;\n\tu32 opt_flags;\n\tconst char *fw_name;\n};\n\nunion fw_table_header {\n\tstruct acpi_table_header acpi;\n\tstruct acpi_table_cdat cdat;\n};\n\nstruct fwft_set_req {\n\tu32 feature;\n\tlong unsigned int value;\n\tlong unsigned int flags;\n\tatomic_t error;\n};\n\nunion fwnet_hwaddr {\n\tu8 u[16];\n\tstruct {\n\t\t__be64 uniq_id;\n\t\tu8 max_rec;\n\t\tu8 sspd;\n\t\tu8 fifo[6];\n\t} uc;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_reference_args;\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct gem_statistic {\n\tchar stat_string[32];\n\tint offset;\n\tu32 stat_bits;\n};\n\nstruct gem_stats {\n\tu64 tx_octets;\n\tu64 tx_frames;\n\tu64 tx_broadcast_frames;\n\tu64 tx_multicast_frames;\n\tu64 tx_pause_frames;\n\tu64 tx_64_byte_frames;\n\tu64 tx_65_127_byte_frames;\n\tu64 tx_128_255_byte_frames;\n\tu64 tx_256_511_byte_frames;\n\tu64 tx_512_1023_byte_frames;\n\tu64 tx_1024_1518_byte_frames;\n\tu64 tx_greater_than_1518_byte_frames;\n\tu64 tx_underrun;\n\tu64 tx_single_collision_frames;\n\tu64 tx_multiple_collision_frames;\n\tu64 tx_excessive_collisions;\n\tu64 tx_late_collisions;\n\tu64 tx_deferred_frames;\n\tu64 tx_carrier_sense_errors;\n\tu64 rx_octets;\n\tu64 rx_frames;\n\tu64 rx_broadcast_frames;\n\tu64 rx_multicast_frames;\n\tu64 rx_pause_frames;\n\tu64 rx_64_byte_frames;\n\tu64 rx_65_127_byte_frames;\n\tu64 rx_128_255_byte_frames;\n\tu64 rx_256_511_byte_frames;\n\tu64 rx_512_1023_byte_frames;\n\tu64 rx_1024_1518_byte_frames;\n\tu64 rx_greater_than_1518_byte_frames;\n\tu64 rx_undersized_frames;\n\tu64 rx_oversize_frames;\n\tu64 rx_jabbers;\n\tu64 rx_frame_check_sequence_errors;\n\tu64 rx_length_field_frame_errors;\n\tu64 rx_symbol_errors;\n\tu64 rx_alignment_errors;\n\tu64 rx_resource_errors;\n\tu64 rx_overruns;\n\tu64 rx_ip_header_checksum_errors;\n\tu64 rx_tcp_checksum_errors;\n\tu64 rx_udp_checksum_errors;\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct gen_pool;\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct list_head slave_bdevs;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tstruct cdrom_device_info *cdi;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n};\n\nstruct gpd_dev_ops {\n\tint (*start)(struct device *);\n\tint (*stop)(struct device *);\n};\n\nstruct genpd_governor_data;\n\nstruct genpd_power_state;\n\nstruct genpd_lock_ops;\n\nstruct generic_pm_domain {\n\tstruct device dev;\n\tstruct dev_pm_domain domain;\n\tstruct list_head gpd_list_node;\n\tstruct list_head parent_links;\n\tstruct list_head child_links;\n\tstruct list_head dev_list;\n\tstruct dev_power_governor *gov;\n\tstruct genpd_governor_data *gd;\n\tstruct work_struct power_off_work;\n\tstruct fwnode_handle *provider;\n\tbool has_provider;\n\tconst char *name;\n\tatomic_t sd_count;\n\tenum gpd_status status;\n\tunsigned int device_count;\n\tunsigned int device_id;\n\tunsigned int suspended_count;\n\tunsigned int prepared_count;\n\tunsigned int performance_state;\n\tcpumask_var_t cpus;\n\tbool synced_poweroff;\n\tbool stay_on;\n\tenum genpd_sync_state sync_state;\n\tint (*power_off)(struct generic_pm_domain *);\n\tint (*power_on)(struct generic_pm_domain *);\n\tstruct raw_notifier_head power_notifiers;\n\tstruct opp_table *opp_table;\n\tint (*set_performance_state)(struct generic_pm_domain *, unsigned int);\n\tstruct gpd_dev_ops dev_ops;\n\tint (*set_hwmode_dev)(struct generic_pm_domain *, struct device *, bool);\n\tbool (*get_hwmode_dev)(struct generic_pm_domain *, struct device *);\n\tint (*attach_dev)(struct generic_pm_domain *, struct device *);\n\tvoid (*detach_dev)(struct generic_pm_domain *, struct device *);\n\tunsigned int flags;\n\tstruct genpd_power_state *states;\n\tvoid (*free_states)(struct genpd_power_state *, unsigned int);\n\tunsigned int state_count;\n\tunsigned int state_idx;\n\tu64 on_time;\n\tu64 accounting_time;\n\tconst struct genpd_lock_ops *lock_ops;\n\tunion {\n\t\tstruct mutex mlock;\n\t\tstruct {\n\t\t\tspinlock_t slock;\n\t\t\tlong unsigned int lock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_slock;\n\t\t\tlong unsigned int raw_lock_flags;\n\t\t};\n\t};\n};\n\nstruct pm_domain_data {\n\tstruct list_head list_node;\n\tstruct device *dev;\n};\n\nstruct gpd_timing_data;\n\nstruct generic_pm_domain_data {\n\tstruct pm_domain_data base;\n\tstruct gpd_timing_data *td;\n\tstruct notifier_block nb;\n\tstruct notifier_block *power_nb;\n\tint cpu;\n\tunsigned int performance_state;\n\tunsigned int default_pstate;\n\tunsigned int rpm_pstate;\n\tunsigned int opp_token;\n\tbool hw_mode;\n\tbool rpm_always_on;\n\tvoid *data;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct ocontext;\n\nstruct genfs {\n\tchar *fstype;\n\tstruct ocontext *head;\n\tstruct genfs *next;\n};\n\nstruct netlink_callback;\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpd_governor_data {\n\ts64 max_off_time_ns;\n\tbool max_off_time_changed;\n\tktime_t next_wakeup;\n\tktime_t next_hrtimer;\n\tktime_t last_enter;\n\tbool reflect_residency;\n\tbool cached_power_down_ok;\n\tbool cached_power_down_state_idx;\n};\n\nstruct genpd_lock_ops {\n\tvoid (*lock)(struct generic_pm_domain *);\n\tvoid (*lock_nested)(struct generic_pm_domain *, int);\n\tint (*lock_interruptible)(struct generic_pm_domain *);\n\tvoid (*unlock)(struct generic_pm_domain *);\n};\n\ntypedef struct generic_pm_domain * (*genpd_xlate_t)(const struct of_phandle_args *, void *);\n\nstruct genpd_onecell_data {\n\tstruct generic_pm_domain **domains;\n\tunsigned int num_domains;\n\tgenpd_xlate_t xlate;\n};\n\nstruct genpd_power_state {\n\tconst char *name;\n\ts64 power_off_latency_ns;\n\ts64 power_on_latency_ns;\n\ts64 residency_ns;\n\tu64 usage;\n\tu64 rejected;\n\tu64 above;\n\tu64 below;\n\tstruct fwnode_handle *fwnode;\n\tu64 idle_time;\n\tvoid *data;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[64];\n\t\tu8 data[512];\n\t};\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct giveback_urb_bh {\n\tbool running;\n\tbool high_prio;\n\tspinlock_t lock;\n\tstruct list_head head;\n\tstruct work_struct bh;\n\tstruct usb_host_endpoint *completing_ep;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct rtc_device;\n\nstruct goldfish_rtc {\n\tvoid *base;\n\tint irq;\n\tstruct rtc_device *rtc;\n};\n\nstruct governor_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gov_attr_set *, char *);\n\tssize_t (*store)(struct gov_attr_set *, const char *, size_t);\n};\n\nstruct gpd_link {\n\tstruct generic_pm_domain *parent;\n\tstruct list_head parent_node;\n\tstruct generic_pm_domain *child;\n\tstruct list_head child_node;\n\tunsigned int performance_state;\n\tunsigned int prev_performance_state;\n};\n\nstruct gpd_timing_data {\n\ts64 suspend_latency_ns;\n\ts64 resume_latency_ns;\n\ts64 effective_constraint_ns;\n\tktime_t next_wakeup;\n\tbool constraint_changed;\n\tbool cached_suspend_ok;\n};\n\nstruct gpio_array {\n\tstruct gpio_desc **desc;\n\tunsigned int size;\n\tstruct gpio_device *gdev;\n\tlong unsigned int *get_mask;\n\tlong unsigned int *set_mask;\n\tlong unsigned int invert_mask[0];\n};\n\nstruct gpio_keys_button;\n\nstruct gpio_button_data {\n\tconst struct gpio_keys_button *button;\n\tstruct input_dev *input;\n\tstruct gpio_desc *gpiod;\n\tshort unsigned int *code;\n\tstruct hrtimer release_timer;\n\tunsigned int release_delay;\n\tstruct delayed_work work;\n\tstruct hrtimer debounce_timer;\n\tunsigned int software_debounce;\n\tunsigned int irq;\n\tunsigned int wakeirq;\n\tunsigned int wakeup_trigger_type;\n\tspinlock_t lock;\n\tbool disabled;\n\tbool key_pressed;\n\tbool suspended;\n\tbool debounce_use_hrtimer;\n};\n\nstruct gpio_v2_line_attribute {\n\t__u32 id;\n\t__u32 padding;\n\tunion {\n\t\t__u64 flags;\n\t\t__u64 values;\n\t\t__u32 debounce_period_us;\n\t};\n};\n\nstruct gpio_v2_line_info {\n\tchar name[32];\n\tchar consumer[32];\n\t__u32 offset;\n\t__u32 num_attrs;\n\t__u64 flags;\n\tstruct gpio_v2_line_attribute attrs[10];\n\t__u32 padding[4];\n};\n\nstruct gpio_v2_line_info_changed {\n\tstruct gpio_v2_line_info info;\n\t__u64 timestamp_ns;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct gpio_chardev_data {\n\tstruct gpio_device *gdev;\n\twait_queue_head_t wait;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_info_changed *type;\n\t\t\tconst struct gpio_v2_line_info_changed *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_info_changed *ptr;\n\t\t\tconst struct gpio_v2_line_info_changed *ptr_const;\n\t\t};\n\t\tstruct gpio_v2_line_info_changed buf[32];\n\t} events;\n\tstruct notifier_block lineinfo_changed_nb;\n\tstruct notifier_block device_unregistered_nb;\n\tlong unsigned int *watched_lines;\n\tatomic_t watch_abi_version;\n\tstruct file *fp;\n};\n\nstruct gpio_chip_guard {\n\tstruct gpio_device *gdev;\n\tstruct gpio_chip *gc;\n\tint idx;\n};\n\ntypedef struct gpio_chip_guard class_gpio_chip_guard_t;\n\nstruct gpio_desc_label;\n\nstruct gpio_desc {\n\tstruct gpio_device *gdev;\n\tlong unsigned int flags;\n\tstruct gpio_desc_label *label;\n\tconst char *name;\n\tunsigned int debounce_period_us;\n};\n\nstruct gpio_desc_label {\n\tstruct callback_head rh;\n\tchar str[0];\n};\n\nstruct gpio_descs {\n\tstruct gpio_array *info;\n\tunsigned int ndescs;\n\tstruct gpio_desc *desc[0];\n};\n\nstruct gpio_device {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tstruct module *owner;\n\tstruct gpio_chip *chip;\n\tstruct gpio_desc *descs;\n\tlong unsigned int *valid_mask;\n\tstruct srcu_struct desc_srcu;\n\tunsigned int base;\n\tu16 ngpio;\n\tbool can_sleep;\n\tconst char *label;\n\tvoid *data;\n\tstruct list_head list;\n\tstruct raw_notifier_head line_state_notifier;\n\trwlock_t line_state_lock;\n\tstruct workqueue_struct *line_state_wq;\n\tstruct blocking_notifier_head device_notifier;\n\tstruct srcu_struct srcu;\n\tstruct list_head pin_ranges;\n};\n\nstruct gpio_generic_chip_config {\n\tstruct device *dev;\n\tlong unsigned int sz;\n\tvoid *dat;\n\tvoid *set;\n\tvoid *clr;\n\tvoid *dirout;\n\tvoid *dirin;\n\tlong unsigned int flags;\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct msi_desc;\n\nstruct msi_alloc_info {\n\tstruct msi_desc *desc;\n\tirq_hw_number_t hwirq;\n\tlong unsigned int flags;\n\tunion {\n\t\tlong unsigned int ul;\n\t\tvoid *ptr;\n\t} scratchpad[2];\n};\n\ntypedef struct msi_alloc_info msi_alloc_info_t;\n\nunion gpio_irq_fwspec {\n\tstruct irq_fwspec fwspec;\n\tmsi_alloc_info_t msiinfo;\n};\n\nstruct gpio_keys_button {\n\tunsigned int code;\n\tint gpio;\n\tint active_low;\n\tconst char *desc;\n\tunsigned int type;\n\tint wakeup;\n\tint wakeup_event_action;\n\tint debounce_interval;\n\tbool can_disable;\n\tint value;\n\tunsigned int irq;\n\tunsigned int wakeirq;\n};\n\nstruct gpio_keys_platform_data;\n\nstruct gpio_keys_drvdata {\n\tconst struct gpio_keys_platform_data *pdata;\n\tstruct input_dev *input;\n\tstruct mutex disable_lock;\n\tshort unsigned int *keymap;\n\tstruct gpio_button_data data[0];\n};\n\nstruct gpio_keys_platform_data {\n\tconst struct gpio_keys_button *buttons;\n\tint nbuttons;\n\tunsigned int poll_interval;\n\tunsigned int rep: 1;\n\tint (*enable)(struct device *);\n\tvoid (*disable)(struct device *);\n\tconst char *name;\n};\n\nstruct pinctrl_gpio_range {\n\tstruct list_head node;\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int base;\n\tunsigned int pin_base;\n\tunsigned int npins;\n\tconst unsigned int *pins;\n\tstruct gpio_chip *gc;\n};\n\nstruct pinctrl_dev;\n\nstruct gpio_pin_range {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_gpio_range range;\n};\n\nstruct gpio_regulator_state;\n\nstruct gpio_regulator_config {\n\tconst char *supply_name;\n\tconst char *input_supply;\n\tunsigned int enabled_at_boot: 1;\n\tunsigned int startup_delay;\n\tenum gpiod_flags *gflags;\n\tint ngpios;\n\tstruct gpio_regulator_state *states;\n\tint nr_states;\n\tenum regulator_type type;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct gpio_regulator_data {\n\tstruct regulator_desc desc;\n\tstruct gpio_desc **gpiods;\n\tint nr_gpios;\n\tstruct gpio_regulator_state *states;\n\tint nr_states;\n\tint state;\n};\n\nstruct gpio_regulator_state {\n\tint value;\n\tint gpios;\n};\n\nstruct gpio_restart {\n\tstruct gpio_desc *reset_gpio;\n\tu32 active_delay_ms;\n\tu32 inactive_delay_ms;\n\tu32 wait_delay_ms;\n};\n\nstruct gpio_v2_line_config_attribute {\n\tstruct gpio_v2_line_attribute attr;\n\t__u64 mask;\n};\n\nstruct gpio_v2_line_config {\n\t__u64 flags;\n\t__u32 num_attrs;\n\t__u32 padding[5];\n\tstruct gpio_v2_line_config_attribute attrs[10];\n};\n\nstruct gpio_v2_line_event {\n\t__u64 timestamp_ns;\n\t__u32 id;\n\t__u32 offset;\n\t__u32 seqno;\n\t__u32 line_seqno;\n\t__u32 padding[6];\n};\n\nstruct gpio_v2_line_request {\n\t__u32 offsets[64];\n\tchar consumer[32];\n\tstruct gpio_v2_line_config config;\n\t__u32 num_lines;\n\t__u32 event_buffer_size;\n\t__u32 padding[5];\n\t__s32 fd;\n};\n\nstruct gpio_v2_line_values {\n\t__u64 bits;\n\t__u64 mask;\n};\n\nstruct gpiochip_info {\n\tchar name[32];\n\tchar label[32];\n\t__u32 lines;\n};\n\nstruct gpiod_hog {\n\tstruct list_head list;\n\tconst char *chip_label;\n\tu16 chip_hwnum;\n\tconst char *line_name;\n\tlong unsigned int lflags;\n\tint dflags;\n};\n\nstruct gpiod_lookup {\n\tconst char *key;\n\tu16 chip_hwnum;\n\tconst char *con_id;\n\tunsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct gpiod_lookup_table {\n\tstruct list_head list;\n\tconst char *dev_id;\n\tstruct gpiod_lookup table[0];\n};\n\nstruct gpioevent_data {\n\t__u64 timestamp;\n\t__u32 id;\n};\n\nstruct gpioevent_request {\n\t__u32 lineoffset;\n\t__u32 handleflags;\n\t__u32 eventflags;\n\tchar consumer_label[32];\n\tint fd;\n};\n\nstruct gpiohandle_config {\n\t__u32 flags;\n\t__u8 default_values[64];\n\t__u32 padding[4];\n};\n\nstruct gpiohandle_data {\n\t__u8 values[64];\n};\n\nstruct gpiohandle_request {\n\t__u32 lineoffsets[64];\n\t__u32 flags;\n\t__u8 default_values[64];\n\tchar consumer_label[32];\n\t__u32 lines;\n\tint fd;\n};\n\nstruct gpiolib_seq_priv {\n\tbool newline;\n\tint idx;\n};\n\nstruct gpioline_info {\n\t__u32 line_offset;\n\t__u32 flags;\n\tchar name[32];\n\tchar consumer[32];\n};\n\nstruct gpioline_info_changed {\n\tstruct gpioline_info info;\n\t__u64 timestamp;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n};\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tsize_t npins;\n};\n\nstruct group_desc {\n\tstruct pingroup grp;\n\tvoid *data;\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct gsb_buffer {\n\tu8 status;\n\tu8 len;\n\tunion {\n\t\tu16 wdata;\n\t\tu8 bdata;\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct rpcsec_gss_oid {\n\tunsigned int len;\n\tu8 data[32];\n};\n\nstruct gss_api_ops;\n\nstruct pf_desc;\n\nstruct gss_api_mech {\n\tstruct list_head gm_list;\n\tstruct module *gm_owner;\n\tstruct rpcsec_gss_oid gm_oid;\n\tchar *gm_name;\n\tconst struct gss_api_ops *gm_ops;\n\tint gm_pf_num;\n\tstruct pf_desc *gm_pfs;\n\tconst char *gm_upcall_enctypes;\n};\n\nstruct gss_ctx;\n\nstruct xdr_buf;\n\nstruct xdr_netobj;\n\nstruct gss_api_ops {\n\tint (*gss_import_sec_context)(const void *, size_t, struct gss_ctx *, time64_t *, gfp_t);\n\tu32 (*gss_get_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_verify_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_wrap)(struct gss_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*gss_unwrap)(struct gss_ctx *, int, int, struct xdr_buf *);\n\tvoid (*gss_delete_sec_context)(void *);\n};\n\nstruct gss_ctx {\n\tstruct gss_api_mech *mech_type;\n\tvoid *internal_ctx_id;\n\tunsigned int slack;\n\tunsigned int align;\n};\n\nunion handle_parts {\n\tdepot_stack_handle_t handle;\n\tstruct {\n\t\tu32 pool_index_plus_1: 17;\n\t\tu32 offset: 10;\n\t\tu32 extra: 5;\n\t};\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct handshake_net {\n\tspinlock_t hn_lock;\n\tint hn_pending;\n\tint hn_pending_max;\n\tstruct list_head hn_requests;\n\tlong unsigned int hn_flags;\n};\n\nstruct handshake_req;\n\nstruct handshake_proto {\n\tint hp_handler_class;\n\tsize_t hp_privsize;\n\tlong unsigned int hp_flags;\n\tint (*hp_accept)(struct handshake_req *, struct genl_info *, int);\n\tvoid (*hp_done)(struct handshake_req *, unsigned int, struct genl_info *);\n\tvoid (*hp_destroy)(struct handshake_req *);\n};\n\nstruct handshake_req {\n\tstruct list_head hr_list;\n\tstruct rhash_head hr_rhash;\n\tlong unsigned int hr_flags;\n\tconst struct handshake_proto *hr_proto;\n\tstruct sock *hr_sk;\n\tvoid (*hr_odestruct)(struct sock *);\n\tchar hr_priv[0];\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hashtab_key_params {\n\tu32 (*hash)(const void *);\n\tint (*cmp)(const void *, const void *);\n};\n\nstruct hashtab_node {\n\tvoid *key;\n\tvoid *datum;\n\tstruct hashtab_node *next;\n};\n\nstruct hc_driver {\n\tconst char *description;\n\tconst char *product_desc;\n\tsize_t hcd_priv_size;\n\tirqreturn_t (*irq)(struct usb_hcd *);\n\tint flags;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*pci_suspend)(struct usb_hcd *, bool);\n\tint (*pci_resume)(struct usb_hcd *, pm_message_t);\n\tint (*pci_poweroff_late)(struct usb_hcd *, bool);\n\tvoid (*stop)(struct usb_hcd *);\n\tvoid (*shutdown)(struct usb_hcd *);\n\tint (*get_frame_number)(struct usb_hcd *);\n\tint (*urb_enqueue)(struct usb_hcd *, struct urb *, gfp_t);\n\tint (*urb_dequeue)(struct usb_hcd *, struct urb *, int);\n\tint (*map_urb_for_dma)(struct usb_hcd *, struct urb *, gfp_t);\n\tvoid (*unmap_urb_for_dma)(struct usb_hcd *, struct urb *);\n\tvoid (*endpoint_disable)(struct usb_hcd *, struct usb_host_endpoint *);\n\tvoid (*endpoint_reset)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*hub_status_data)(struct usb_hcd *, char *);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n\tint (*bus_suspend)(struct usb_hcd *);\n\tint (*bus_resume)(struct usb_hcd *);\n\tint (*start_port_reset)(struct usb_hcd *, unsigned int);\n\tlong unsigned int (*get_resuming_ports)(struct usb_hcd *);\n\tvoid (*relinquish_port)(struct usb_hcd *, int);\n\tint (*port_handed_over)(struct usb_hcd *, int);\n\tvoid (*clear_tt_buffer_complete)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*alloc_dev)(struct usb_hcd *, struct usb_device *);\n\tvoid (*free_dev)(struct usb_hcd *, struct usb_device *);\n\tint (*alloc_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, unsigned int, gfp_t);\n\tint (*free_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, gfp_t);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*address_device)(struct usb_hcd *, struct usb_device *, unsigned int);\n\tint (*enable_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*reset_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_device)(struct usb_hcd *, struct usb_device *);\n\tint (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);\n\tint (*enable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*disable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*find_raw_port_number)(struct usb_hcd *, int);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n\tint (*submit_single_step_set_feature)(struct usb_hcd *, struct urb *, int);\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hdmi_any_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n};\n\nstruct hdmi_audio_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned char channels;\n\tenum hdmi_audio_coding_type coding_type;\n\tenum hdmi_audio_sample_size sample_size;\n\tenum hdmi_audio_sample_frequency sample_frequency;\n\tenum hdmi_audio_coding_type_ext coding_type_ext;\n\tunsigned char channel_allocation;\n\tunsigned char level_shift_value;\n\tbool downmix_inhibit;\n};\n\nstruct hdmi_avi_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tbool itc;\n\tunsigned char pixel_repeat;\n\tenum hdmi_colorspace colorspace;\n\tenum hdmi_scan_mode scan_mode;\n\tenum hdmi_colorimetry colorimetry;\n\tenum hdmi_picture_aspect picture_aspect;\n\tenum hdmi_active_aspect active_aspect;\n\tenum hdmi_extended_colorimetry extended_colorimetry;\n\tenum hdmi_quantization_range quantization_range;\n\tenum hdmi_nups nups;\n\tunsigned char video_code;\n\tenum hdmi_ycc_quantization_range ycc_quantization_range;\n\tenum hdmi_content_type content_type;\n\tshort unsigned int top_bar;\n\tshort unsigned int bottom_bar;\n\tshort unsigned int left_bar;\n\tshort unsigned int right_bar;\n};\n\nstruct hdmi_drm_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_eotf eotf;\n\tenum hdmi_metadata_type metadata_type;\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} white_point;\n\tu16 max_display_mastering_luminance;\n\tu16 min_display_mastering_luminance;\n\tu16 max_cll;\n\tu16 max_fall;\n};\n\nstruct hdmi_spd_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tchar vendor[8];\n\tchar product[16];\n\tenum hdmi_spd_sdi sdi;\n};\n\nstruct hdmi_vendor_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned int oui;\n\tu8 vic;\n\tenum hdmi_3d_structure s3d_struct;\n\tunsigned int s3d_ext_data;\n};\n\nunion hdmi_vendor_any_infoframe {\n\tstruct {\n\t\tenum hdmi_infoframe_type type;\n\t\tunsigned char version;\n\t\tunsigned char length;\n\t\tunsigned int oui;\n\t} any;\n\tstruct hdmi_vendor_infoframe hdmi;\n};\n\nunion hdmi_infoframe {\n\tstruct hdmi_any_infoframe any;\n\tstruct hdmi_avi_infoframe avi;\n\tstruct hdmi_spd_infoframe spd;\n\tunion hdmi_vendor_any_infoframe vendor;\n\tstruct hdmi_audio_infoframe audio;\n\tstruct hdmi_drm_infoframe drm;\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[12];\n};\n\nstruct hid_class_descriptor {\n\t__u8 bDescriptorType;\n\t__le16 wDescriptorLength;\n} __attribute__((packed));\n\nstruct hid_collection {\n\tint parent_idx;\n\tunsigned int type;\n\tunsigned int usage;\n\tunsigned int level;\n};\n\nstruct hid_report;\n\nstruct hid_control_fifo {\n\tunsigned char dir;\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_device;\n\nstruct hid_debug_list {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tchar *type;\n\t\t\tconst char *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tchar *ptr;\n\t\t\tconst char *ptr_const;\n\t\t};\n\t\tchar buf[0];\n\t} hid_debug_fifo;\n\tstruct fasync_struct *fasync;\n\tstruct hid_device *hdev;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct hid_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdHID;\n\t__u8 bCountryCode;\n\t__u8 bNumDescriptors;\n\tstruct hid_class_descriptor rpt_desc;\n\tstruct hid_class_descriptor opt_descs[0];\n} __attribute__((packed));\n\nstruct hid_report_enum {\n\tunsigned int numbered;\n\tstruct list_head report_list;\n\tstruct hid_report *report_id_hash[256];\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct hid_driver;\n\nstruct hid_ll_driver;\n\nstruct hid_field;\n\nstruct hid_usage;\n\nstruct hid_device {\n\tconst __u8 *dev_rdesc;\n\tconst __u8 *bpf_rdesc;\n\tconst __u8 *rdesc;\n\tunsigned int dev_rsize;\n\tunsigned int bpf_rsize;\n\tunsigned int rsize;\n\tunsigned int collection_size;\n\tstruct hid_collection *collection;\n\tunsigned int maxcollection;\n\tunsigned int maxapplication;\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\t__u32 version;\n\tenum hid_type type;\n\tunsigned int country;\n\tstruct hid_report_enum report_enum[3];\n\tstruct work_struct led_work;\n\tstruct semaphore driver_input_lock;\n\tstruct device dev;\n\tstruct hid_driver *driver;\n\tvoid *devres_group_id;\n\tconst struct hid_ll_driver *ll_driver;\n\tstruct mutex ll_open_lock;\n\tunsigned int ll_open_count;\n\tlong unsigned int status;\n\tunsigned int claimed;\n\tunsigned int quirks;\n\tunsigned int initial_quirks;\n\tbool io_started;\n\tstruct list_head inputs;\n\tvoid *hiddev;\n\tvoid *hidraw;\n\tchar name[128];\n\tchar phys[64];\n\tchar uniq[64];\n\tvoid *driver_data;\n\tint (*ff_init)(struct hid_device *);\n\tint (*hiddev_connect)(struct hid_device *, unsigned int);\n\tvoid (*hiddev_disconnect)(struct hid_device *);\n\tvoid (*hiddev_hid_event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*hiddev_report_event)(struct hid_device *, struct hid_report *);\n\tshort unsigned int debug;\n\tstruct dentry *debug_dir;\n\tstruct dentry *debug_rdesc;\n\tstruct dentry *debug_events;\n\tstruct list_head debug_list;\n\tspinlock_t debug_list_lock;\n\twait_queue_head_t debug_wait;\n\tstruct kref ref;\n\tunsigned int id;\n};\n\nstruct hid_device_id {\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hid_report_id;\n\nstruct hid_usage_id;\n\nstruct hid_input;\n\nstruct hid_driver {\n\tconst char *name;\n\tconst struct hid_device_id *id_table;\n\tstruct list_head dyn_list;\n\tspinlock_t dyn_lock;\n\tbool (*match)(struct hid_device *, bool);\n\tint (*probe)(struct hid_device *, const struct hid_device_id *);\n\tvoid (*remove)(struct hid_device *);\n\tconst struct hid_report_id *report_table;\n\tint (*raw_event)(struct hid_device *, struct hid_report *, u8 *, int);\n\tconst struct hid_usage_id *usage_table;\n\tint (*event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*report)(struct hid_device *, struct hid_report *);\n\tconst __u8 * (*report_fixup)(struct hid_device *, __u8 *, unsigned int *);\n\tint (*input_mapping)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_mapped)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_configured)(struct hid_device *, struct hid_input *);\n\tvoid (*feature_mapping)(struct hid_device *, struct hid_field *, struct hid_usage *);\n\tint (*suspend)(struct hid_device *, pm_message_t);\n\tint (*resume)(struct hid_device *);\n\tint (*reset_resume)(struct hid_device *);\n\tvoid (*on_hid_hw_open)(struct hid_device *);\n\tvoid (*on_hid_hw_close)(struct hid_device *);\n\tstruct device_driver driver;\n};\n\nstruct hid_dynid {\n\tstruct list_head list;\n\tstruct hid_device_id id;\n};\n\nstruct hid_field {\n\tunsigned int physical;\n\tunsigned int logical;\n\tunsigned int application;\n\tstruct hid_usage *usage;\n\tunsigned int maxusage;\n\tunsigned int flags;\n\tunsigned int report_offset;\n\tunsigned int report_size;\n\tunsigned int report_count;\n\tunsigned int report_type;\n\t__s32 *value;\n\t__s32 *new_value;\n\t__s32 *usages_priorities;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tbool ignored;\n\tstruct hid_report *report;\n\tunsigned int index;\n\tstruct hid_input *hidinput;\n\t__u16 dpad;\n\tunsigned int slot_idx;\n};\n\nstruct hid_field_entry {\n\tstruct list_head list;\n\tstruct hid_field *field;\n\tunsigned int index;\n\t__s32 priority;\n};\n\nstruct hid_global {\n\tunsigned int usage_page;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tunsigned int report_id;\n\tunsigned int report_size;\n\tunsigned int report_count;\n};\n\nstruct hid_input {\n\tstruct list_head list;\n\tstruct hid_report *report;\n\tstruct input_dev *input;\n\tconst char *name;\n\tstruct list_head reports;\n\tunsigned int application;\n\tbool registered;\n};\n\nstruct hid_item {\n\tunsigned int format;\n\t__u8 size;\n\t__u8 type;\n\t__u8 tag;\n\tunion {\n\t\t__u8 u8;\n\t\t__s8 s8;\n\t\t__u16 u16;\n\t\t__s16 s16;\n\t\t__u32 u32;\n\t\t__s32 s32;\n\t\tconst __u8 *longdata;\n\t} data;\n};\n\nstruct hid_ll_driver {\n\tint (*start)(struct hid_device *);\n\tvoid (*stop)(struct hid_device *);\n\tint (*open)(struct hid_device *);\n\tvoid (*close)(struct hid_device *);\n\tint (*power)(struct hid_device *, int);\n\tint (*parse)(struct hid_device *);\n\tvoid (*request)(struct hid_device *, struct hid_report *, int);\n\tint (*wait)(struct hid_device *);\n\tint (*raw_request)(struct hid_device *, unsigned char, __u8 *, size_t, unsigned char, int);\n\tint (*output_report)(struct hid_device *, __u8 *, size_t);\n\tint (*idle)(struct hid_device *, int, int, int);\n\tbool (*may_wakeup)(struct hid_device *);\n\tunsigned int max_buffer_size;\n};\n\nstruct hid_local {\n\tunsigned int usage[12288];\n\tu8 usage_size[12288];\n\tunsigned int collection_index[12288];\n\tunsigned int usage_index;\n\tunsigned int usage_minimum;\n\tunsigned int delimiter_depth;\n\tunsigned int delimiter_branch;\n};\n\nstruct hid_output_fifo {\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_parser {\n\tstruct hid_global global;\n\tstruct hid_global global_stack[4];\n\tunsigned int global_stack_ptr;\n\tstruct hid_local local;\n\tunsigned int *collection_stack;\n\tunsigned int collection_stack_ptr;\n\tunsigned int collection_stack_size;\n\tstruct hid_device *device;\n\tunsigned int scan_flags;\n};\n\nstruct hid_report {\n\tstruct list_head list;\n\tstruct list_head hidinput_list;\n\tstruct list_head field_entry_list;\n\tunsigned int id;\n\tenum hid_report_type type;\n\tunsigned int application;\n\tstruct hid_field *field[256];\n\tstruct hid_field_entry *field_entries;\n\tunsigned int maxfield;\n\tunsigned int size;\n\tstruct hid_device *device;\n\tbool tool_active;\n\tunsigned int tool;\n};\n\nstruct hid_report_id {\n\t__u32 report_type;\n};\n\nstruct hid_usage {\n\tunsigned int hid;\n\tunsigned int collection_index;\n\tunsigned int usage_index;\n\t__s8 resolution_multiplier;\n\t__s8 wheel_factor;\n\t__u16 code;\n\t__u8 type;\n\t__s16 hat_min;\n\t__s16 hat_max;\n\t__s16 hat_dir;\n\t__s16 wheel_accumulated;\n};\n\nstruct hid_usage_entry {\n\tunsigned int page;\n\tunsigned int usage;\n\tconst char *description;\n};\n\nstruct hid_usage_id {\n\t__u32 usage_hid;\n\t__u32 usage_type;\n\t__u32 usage_code;\n};\n\nstruct hiddev {\n\tint minor;\n\tint exist;\n\tint open;\n\tstruct mutex existancelock;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tbool initialized;\n};\n\nstruct hidraw {\n\tunsigned int minor;\n\tint exist;\n\tint open;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct device *dev;\n\tspinlock_t list_lock;\n\tstruct list_head list;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct sha1_block_state {\n\tu32 h[5];\n};\n\nstruct sha1_ctx {\n\tstruct sha1_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_sha1_ctx {\n\tstruct sha1_ctx sha_ctx;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha1_key {\n\tstruct sha1_block_state istate;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct hprobe {\n\tenum hprobe_state state;\n\tint srcu_idx;\n\tstruct uprobe *uprobe;\n};\n\nstruct hpx_type0 {\n\tu32 revision;\n\tu8 cache_line_size;\n\tu8 latency_timer;\n\tu8 enable_serr;\n\tu8 enable_perr;\n};\n\nstruct hpx_type1 {\n\tu32 revision;\n\tu8 max_mem_read;\n\tu8 avg_max_split;\n\tu16 tot_max_split;\n};\n\nstruct hpx_type2 {\n\tu32 revision;\n\tu32 unc_err_mask_and;\n\tu32 unc_err_mask_or;\n\tu32 unc_err_sever_and;\n\tu32 unc_err_sever_or;\n\tu32 cor_err_mask_and;\n\tu32 cor_err_mask_or;\n\tu32 adv_err_cap_and;\n\tu32 adv_err_cap_or;\n\tu16 pci_exp_devctl_and;\n\tu16 pci_exp_devctl_or;\n\tu16 pci_exp_lnkctl_and;\n\tu16 pci_exp_lnkctl_or;\n\tu32 sec_unc_err_sever_and;\n\tu32 sec_unc_err_sever_or;\n\tu32 sec_unc_err_mask_and;\n\tu32 sec_unc_err_mask_or;\n};\n\nstruct hpx_type3 {\n\tu16 device_type;\n\tu16 function_type;\n\tu16 config_space_location;\n\tu16 pci_exp_cap_id;\n\tu16 pci_exp_cap_ver;\n\tu16 pci_exp_vendor_id;\n\tu16 dvsec_id;\n\tu16 dvsec_rev;\n\tu16 match_offset;\n\tu32 match_mask_and;\n\tu32 match_value;\n\tu16 reg_offset;\n\tu32 reg_mask_and;\n\tu32 reg_mask_or;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tktime_t offset;\n\tlong: 64;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tstruct hrtimer_clock_base clock_base[8];\n\tcall_single_data_t csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n};\n\nstruct hs_primary_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\t__u8 id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 unused4[28];\n\t__u8 root_directory_record[34];\n};\n\nstruct hs_volume_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2033];\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {\n\tstruct mutex resize_lock;\n\tstruct lock_class_key resize_key;\n\tint next_nid_to_alloc;\n\tint next_nid_to_free;\n\tunsigned int order;\n\tunsigned int demote_order;\n\tlong unsigned int mask;\n\tlong unsigned int max_huge_pages;\n\tlong unsigned int nr_huge_pages;\n\tlong unsigned int free_huge_pages;\n\tlong unsigned int resv_huge_pages;\n\tlong unsigned int surplus_huge_pages;\n\tlong unsigned int nr_overcommit_huge_pages;\n\tstruct list_head hugepage_activelist;\n\tstruct list_head hugepage_freelists[4];\n\tunsigned int max_huge_pages_node[4];\n\tunsigned int nr_huge_pages_node[4];\n\tunsigned int free_huge_pages_node[4];\n\tunsigned int surplus_huge_pages_node[4];\n\tchar name[32];\n};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tlong: 0;\n\tchar key[0];\n};\n\nstruct cma;\n\nstruct huge_bootmem_page {\n\tstruct list_head list;\n\tstruct hstate *hstate;\n\tlong unsigned int flags;\n\tstruct cma *cma;\n};\n\nstruct hugepage_subpool {\n\tspinlock_t lock;\n\tlong int count;\n\tlong int max_hpages;\n\tlong int used_hpages;\n\tstruct hstate *hstate;\n\tlong int min_hpages;\n\tlong int rsv_hpages;\n};\n\nstruct page_counter {\n\tatomic_long_t usage;\n\tlong unsigned int failcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int emin;\n\tatomic_long_t min_usage;\n\tatomic_long_t children_min_usage;\n\tlong unsigned int elow;\n\tatomic_long_t low_usage;\n\tatomic_long_t children_low_usage;\n\tlong unsigned int watermark;\n\tlong unsigned int local_watermark;\n\tstruct cacheline_padding _pad2_;\n\tbool protection_support;\n\tbool track_failcnt;\n\tlong unsigned int min;\n\tlong unsigned int low;\n\tlong unsigned int high;\n\tlong unsigned int max;\n\tstruct page_counter *parent;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hugetlb_cgroup_per_node;\n\nstruct hugetlb_cgroup {\n\tstruct cgroup_subsys_state css;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter hugepage[3];\n\tstruct page_counter rsvd_hugepage[3];\n\tatomic_long_t events[3];\n\tatomic_long_t events_local[3];\n\tstruct cgroup_file events_file[3];\n\tstruct cgroup_file events_local_file[3];\n\tstruct hugetlb_cgroup_per_node *nodeinfo[0];\n};\n\nstruct hugetlb_cgroup_per_node {\n\tlong unsigned int usage[3];\n};\n\nstruct hugetlb_cmdline {\n\tchar *val;\n\tint (*setup)(char *);\n};\n\nstruct hugetlb_vma_lock {\n\tstruct kref refs;\n\tstruct rw_semaphore rw_sema;\n\tstruct vm_area_struct *vma;\n};\n\nstruct hugetlbfs_fs_context {\n\tstruct hstate *hstate;\n\tlong long unsigned int max_size_opt;\n\tlong long unsigned int min_size_opt;\n\tlong int max_hpages;\n\tlong int nr_inodes;\n\tlong int min_hpages;\n\tenum hugetlbfs_size_type max_val_type;\n\tenum hugetlbfs_size_type min_val_type;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hugetlbfs_inode_info {\n\tstruct inode vfs_inode;\n\tunsigned int seals;\n};\n\nstruct hugetlbfs_sb_info {\n\tlong int max_inodes;\n\tlong int free_inodes;\n\tspinlock_t stat_lock;\n\tstruct hstate *hstate;\n\tstruct hugepage_subpool *spool;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct hw_cache_event {\n\tuint32_t result_id: 1;\n\tuint32_t op_id: 2;\n\tuint32_t cache_id: 13;\n\tuint32_t event_type: 4;\n\tuint32_t reserved: 12;\n};\n\nstruct hw_gen_event {\n\tuint32_t event_code: 16;\n\tuint32_t event_type: 4;\n\tuint32_t reserved: 12;\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 config1;\n\t\t\tu64 last_tag;\n\t\t\tu64 dyn_constraint;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tu64 aux_config;\n\t\t\tunsigned int aux_paused;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tunion {\n\t\tstruct {\n\t\t\tu64 last_period;\n\t\t\tlocal64_t period_left;\n\t\t};\n\t\tstruct {\n\t\t\tu64 saved_metric;\n\t\t\tu64 saved_slots;\n\t\t};\n\t};\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n};\n\nstruct hwmon_channel_info {\n\tenum hwmon_sensor_types type;\n\tconst u32 *config;\n};\n\nstruct hwmon_ops;\n\nstruct hwmon_chip_info {\n\tconst struct hwmon_ops *ops;\n\tconst struct hwmon_channel_info * const *info;\n};\n\nstruct hwmon_device {\n\tconst char *name;\n\tconst char *label;\n\tstruct device dev;\n\tconst struct hwmon_chip_info *chip;\n\tstruct mutex lock;\n\tstruct list_head tzdata;\n\tstruct attribute_group group;\n\tconst struct attribute_group **groups;\n};\n\nstruct hwmon_device_attribute {\n\tstruct device_attribute dev_attr;\n\tconst struct hwmon_ops *ops;\n\tenum hwmon_sensor_types type;\n\tu32 attr;\n\tint index;\n\tchar name[32];\n};\n\nstruct hwmon_ops {\n\tumode_t visible;\n\tumode_t (*is_visible)(const void *, enum hwmon_sensor_types, u32, int);\n\tint (*read)(struct device *, enum hwmon_sensor_types, u32, int, long int *);\n\tint (*read_string)(struct device *, enum hwmon_sensor_types, u32, int, const char **);\n\tint (*write)(struct device *, enum hwmon_sensor_types, u32, int, long int);\n};\n\nstruct hwmon_thermal_data {\n\tstruct list_head node;\n\tstruct device *dev;\n\tint index;\n\tstruct thermal_zone_device *tzd;\n};\n\nstruct hwmon_type_attr_list {\n\tconst u32 *attrs;\n\tsize_t n_attrs;\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct i2c_acpi_handler_data {\n\tstruct acpi_connection_info info;\n\tstruct i2c_adapter *adapter;\n};\n\nstruct i2c_acpi_irq_context {\n\tint irq;\n\tbool wake_capable;\n};\n\nstruct i2c_board_info;\n\nstruct i2c_acpi_lookup {\n\tstruct i2c_board_info *info;\n\tacpi_handle adapter_handle;\n\tacpi_handle device_handle;\n\tacpi_handle search_handle;\n\tint n;\n\tint index;\n\tu32 speed;\n\tu32 min_speed;\n\tu32 force_speed;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n};\n\nunion i2c_smbus_data;\n\nstruct i2c_algorithm {\n\tunion {\n\t\tint (*xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tunion {\n\t\tint (*xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n};\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n\tvoid *devres_group_id;\n\tstruct dentry *debugfs;\n};\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *);\n\tvoid (*remove)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tu32 flags;\n};\n\nstruct i2c_dw_semaphore_callbacks {\n\tint (*probe)(struct dw_i2c_dev *);\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n};\n\nstruct ib_pd;\n\nstruct ib_uobject;\n\nstruct ib_gid_attr;\n\nstruct ib_ah {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tconst struct ib_gid_attr *sgid_attr;\n\tenum rdma_ah_attr_type type;\n};\n\nstruct ib_ah_attr {\n\tu16 dlid;\n\tu8 src_path_bits;\n};\n\nstruct ib_core_device {\n\tstruct device dev;\n\tpossible_net_t rdma_net;\n\tstruct kobject *ports_kobj;\n\tstruct list_head port_list;\n\tstruct ib_device *owner;\n};\n\nstruct ib_counters {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_counters_read_attr {\n\tu64 *counters_buff;\n\tu32 ncounters;\n\tu32 flags;\n};\n\nstruct ib_ucq_object;\n\nstruct ib_cq;\n\ntypedef void (*ib_comp_handler)(struct ib_cq *, void *);\n\nstruct irq_poll;\n\ntypedef int irq_poll_fn(struct irq_poll *, int);\n\nstruct irq_poll {\n\tstruct list_head list;\n\tlong unsigned int state;\n\tint weight;\n\tirq_poll_fn *poll;\n};\n\nstruct rdma_restrack_entry {\n\tbool valid;\n\tu8 no_track: 1;\n\tstruct kref kref;\n\tstruct completion comp;\n\tstruct task_struct *task;\n\tconst char *kern_name;\n\tenum rdma_restrack_type type;\n\tbool user;\n\tu32 id;\n};\n\nstruct ib_event;\n\nstruct ib_wc;\n\nstruct ib_cq {\n\tstruct ib_device *device;\n\tstruct ib_ucq_object *uobject;\n\tib_comp_handler comp_handler;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *cq_context;\n\tint cqe;\n\tunsigned int cqe_used;\n\tatomic_t usecnt;\n\tenum ib_poll_context poll_ctx;\n\tstruct ib_wc *wc;\n\tstruct list_head pool_entry;\n\tunion {\n\t\tstruct irq_poll iop;\n\t\tstruct work_struct work;\n\t};\n\tstruct workqueue_struct *comp_wq;\n\tstruct dim *dim;\n\tktime_t timestamp;\n\tu8 interrupt: 1;\n\tu8 shared: 1;\n\tunsigned int comp_vector;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_cq_caps {\n\tu16 max_cq_moderation_count;\n\tu16 max_cq_moderation_period;\n};\n\nstruct ib_cq_init_attr {\n\tunsigned int cqe;\n\tu32 comp_vector;\n\tu32 flags;\n};\n\nstruct ib_cqe {\n\tvoid (*done)(struct ib_cq *, struct ib_wc *);\n};\n\nstruct ib_mad;\n\nstruct uverbs_attr_bundle;\n\nstruct ib_umem;\n\nstruct rdma_cm_id;\n\nstruct iw_cm_id;\n\nstruct iw_cm_conn_param;\n\nstruct ib_uverbs_file;\n\nstruct ib_qp;\n\nstruct ib_send_wr;\n\nstruct ib_recv_wr;\n\nstruct ib_srq;\n\nstruct ib_grh;\n\nstruct ib_device_attr;\n\nstruct ib_udata;\n\nstruct ib_device_modify;\n\nstruct ib_port_attr;\n\nstruct ib_port_modify;\n\nstruct ib_port_immutable;\n\nstruct rdma_netdev_alloc_params;\n\nunion ib_gid;\n\nstruct ib_ucontext;\n\nstruct rdma_user_mmap_entry;\n\nstruct phys_vec;\n\nstruct rdma_ah_init_attr;\n\nstruct rdma_ah_attr;\n\nstruct ib_srq_init_attr;\n\nstruct ib_srq_attr;\n\nstruct ib_qp_init_attr;\n\nstruct ib_qp_attr;\n\nstruct ib_mr;\n\nstruct ib_dmah;\n\nstruct ib_sge;\n\nstruct ib_mr_status;\n\nstruct ib_mw;\n\nstruct ib_xrcd;\n\nstruct ib_flow;\n\nstruct ib_flow_attr;\n\nstruct ib_flow_action;\n\nstruct ifla_vf_info;\n\nstruct ifla_vf_stats;\n\nstruct ifla_vf_guid;\n\nstruct ib_wq;\n\nstruct ib_wq_init_attr;\n\nstruct ib_wq_attr;\n\nstruct ib_rwq_ind_table;\n\nstruct ib_rwq_ind_table_init_attr;\n\nstruct ib_dm;\n\nstruct ib_dm_alloc_attr;\n\nstruct ib_dm_mr_attr;\n\nstruct rdma_hw_stats;\n\nstruct rdma_counter;\n\nstruct ib_device_ops {\n\tstruct module *owner;\n\tenum rdma_driver_id driver_id;\n\tu32 uverbs_abi_ver;\n\tunsigned int uverbs_no_driver_id_binding: 1;\n\tconst struct attribute_group *device_group;\n\tconst struct attribute_group **port_groups;\n\tint (*post_send)(struct ib_qp *, const struct ib_send_wr *, const struct ib_send_wr **);\n\tint (*post_recv)(struct ib_qp *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tvoid (*drain_rq)(struct ib_qp *);\n\tvoid (*drain_sq)(struct ib_qp *);\n\tint (*poll_cq)(struct ib_cq *, int, struct ib_wc *);\n\tint (*peek_cq)(struct ib_cq *, int);\n\tint (*req_notify_cq)(struct ib_cq *, enum ib_cq_notify_flags);\n\tint (*post_srq_recv)(struct ib_srq *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tint (*process_mad)(struct ib_device *, int, u32, const struct ib_wc *, const struct ib_grh *, const struct ib_mad *, struct ib_mad *, size_t *, u16 *);\n\tint (*query_device)(struct ib_device *, struct ib_device_attr *, struct ib_udata *);\n\tint (*modify_device)(struct ib_device *, int, struct ib_device_modify *);\n\tvoid (*get_dev_fw_str)(struct ib_device *, char *);\n\tconst struct cpumask * (*get_vector_affinity)(struct ib_device *, int);\n\tint (*query_port)(struct ib_device *, u32, struct ib_port_attr *);\n\tint (*query_port_speed)(struct ib_device *, u32, u64 *);\n\tint (*modify_port)(struct ib_device *, u32, int, struct ib_port_modify *);\n\tint (*get_port_immutable)(struct ib_device *, u32, struct ib_port_immutable *);\n\tenum rdma_link_layer (*get_link_layer)(struct ib_device *, u32);\n\tstruct net_device * (*get_netdev)(struct ib_device *, u32);\n\tstruct net_device * (*alloc_rdma_netdev)(struct ib_device *, u32, enum rdma_netdev_t, const char *, unsigned char, void (*)(struct net_device *));\n\tint (*rdma_netdev_get_params)(struct ib_device *, u32, enum rdma_netdev_t, struct rdma_netdev_alloc_params *);\n\tint (*query_gid)(struct ib_device *, u32, int, union ib_gid *);\n\tint (*add_gid)(const struct ib_gid_attr *, void **);\n\tint (*del_gid)(const struct ib_gid_attr *, void **);\n\tint (*query_pkey)(struct ib_device *, u32, u16, u16 *);\n\tint (*alloc_ucontext)(struct ib_ucontext *, struct ib_udata *);\n\tvoid (*dealloc_ucontext)(struct ib_ucontext *);\n\tint (*mmap)(struct ib_ucontext *, struct vm_area_struct *);\n\tvoid (*mmap_free)(struct rdma_user_mmap_entry *);\n\tint (*mmap_get_pfns)(struct rdma_user_mmap_entry *, struct phys_vec *, struct p2pdma_provider **);\n\tstruct rdma_user_mmap_entry * (*pgoff_to_mmap_entry)(struct ib_ucontext *, off_t);\n\tvoid (*disassociate_ucontext)(struct ib_ucontext *);\n\tint (*alloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*dealloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*create_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*create_user_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*modify_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*query_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*destroy_ah)(struct ib_ah *, u32);\n\tint (*create_srq)(struct ib_srq *, struct ib_srq_init_attr *, struct ib_udata *);\n\tint (*modify_srq)(struct ib_srq *, struct ib_srq_attr *, enum ib_srq_attr_mask, struct ib_udata *);\n\tint (*query_srq)(struct ib_srq *, struct ib_srq_attr *);\n\tint (*destroy_srq)(struct ib_srq *, struct ib_udata *);\n\tint (*create_qp)(struct ib_qp *, struct ib_qp_init_attr *, struct ib_udata *);\n\tint (*modify_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);\n\tint (*query_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_qp_init_attr *);\n\tint (*destroy_qp)(struct ib_qp *, struct ib_udata *);\n\tint (*create_cq)(struct ib_cq *, const struct ib_cq_init_attr *, struct uverbs_attr_bundle *);\n\tint (*create_cq_umem)(struct ib_cq *, const struct ib_cq_init_attr *, struct ib_umem *, struct uverbs_attr_bundle *);\n\tint (*modify_cq)(struct ib_cq *, u16, u16);\n\tint (*destroy_cq)(struct ib_cq *, struct ib_udata *);\n\tint (*resize_cq)(struct ib_cq *, int, struct ib_udata *);\n\tint (*pre_destroy_cq)(struct ib_cq *);\n\tvoid (*post_destroy_cq)(struct ib_cq *);\n\tstruct ib_mr * (*get_dma_mr)(struct ib_pd *, int);\n\tstruct ib_mr * (*reg_user_mr)(struct ib_pd *, u64, u64, u64, int, struct ib_dmah *, struct ib_udata *);\n\tstruct ib_mr * (*reg_user_mr_dmabuf)(struct ib_pd *, u64, u64, u64, int, int, struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*rereg_user_mr)(struct ib_mr *, int, u64, u64, u64, int, struct ib_pd *, struct ib_udata *);\n\tint (*dereg_mr)(struct ib_mr *, struct ib_udata *);\n\tstruct ib_mr * (*alloc_mr)(struct ib_pd *, enum ib_mr_type, u32);\n\tstruct ib_mr * (*alloc_mr_integrity)(struct ib_pd *, u32, u32);\n\tint (*advise_mr)(struct ib_pd *, enum ib_uverbs_advise_mr_advice, u32, struct ib_sge *, u32, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg)(struct ib_mr *, struct scatterlist *, int, unsigned int *);\n\tint (*check_mr_status)(struct ib_mr *, u32, struct ib_mr_status *);\n\tint (*alloc_mw)(struct ib_mw *, struct ib_udata *);\n\tint (*dealloc_mw)(struct ib_mw *);\n\tint (*attach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*detach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*alloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tint (*dealloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tstruct ib_flow * (*create_flow)(struct ib_qp *, struct ib_flow_attr *, struct ib_udata *);\n\tint (*destroy_flow)(struct ib_flow *);\n\tint (*destroy_flow_action)(struct ib_flow_action *);\n\tint (*set_vf_link_state)(struct ib_device *, int, u32, int);\n\tint (*get_vf_config)(struct ib_device *, int, u32, struct ifla_vf_info *);\n\tint (*get_vf_stats)(struct ib_device *, int, u32, struct ifla_vf_stats *);\n\tint (*get_vf_guid)(struct ib_device *, int, u32, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*set_vf_guid)(struct ib_device *, int, u32, u64, int);\n\tstruct ib_wq * (*create_wq)(struct ib_pd *, struct ib_wq_init_attr *, struct ib_udata *);\n\tint (*destroy_wq)(struct ib_wq *, struct ib_udata *);\n\tint (*modify_wq)(struct ib_wq *, struct ib_wq_attr *, u32, struct ib_udata *);\n\tint (*create_rwq_ind_table)(struct ib_rwq_ind_table *, struct ib_rwq_ind_table_init_attr *, struct ib_udata *);\n\tint (*destroy_rwq_ind_table)(struct ib_rwq_ind_table *);\n\tstruct ib_dm * (*alloc_dm)(struct ib_device *, struct ib_ucontext *, struct ib_dm_alloc_attr *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dm)(struct ib_dm *, struct uverbs_attr_bundle *);\n\tint (*alloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*reg_dm_mr)(struct ib_pd *, struct ib_dm *, struct ib_dm_mr_attr *, struct uverbs_attr_bundle *);\n\tint (*create_counters)(struct ib_counters *, struct uverbs_attr_bundle *);\n\tint (*destroy_counters)(struct ib_counters *);\n\tint (*read_counters)(struct ib_counters *, struct ib_counters_read_attr *, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg_pi)(struct ib_mr *, struct scatterlist *, int, unsigned int *, struct scatterlist *, int, unsigned int *);\n\tstruct rdma_hw_stats * (*alloc_hw_device_stats)(struct ib_device *);\n\tstruct rdma_hw_stats * (*alloc_hw_port_stats)(struct ib_device *, u32);\n\tint (*get_hw_stats)(struct ib_device *, struct rdma_hw_stats *, u32, int);\n\tint (*modify_hw_stat)(struct ib_device *, u32, unsigned int, bool);\n\tint (*fill_res_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_mr_entry_raw)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_cq_entry)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_cq_entry_raw)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_qp_entry)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_qp_entry_raw)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_cm_id_entry)(struct sk_buff *, struct rdma_cm_id *);\n\tint (*fill_res_srq_entry)(struct sk_buff *, struct ib_srq *);\n\tint (*fill_res_srq_entry_raw)(struct sk_buff *, struct ib_srq *);\n\tint (*enable_driver)(struct ib_device *);\n\tvoid (*dealloc_driver)(struct ib_device *);\n\tvoid (*iw_add_ref)(struct ib_qp *);\n\tvoid (*iw_rem_ref)(struct ib_qp *);\n\tstruct ib_qp * (*iw_get_qp)(struct ib_device *, int);\n\tint (*iw_connect)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_accept)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_reject)(struct iw_cm_id *, const void *, u8);\n\tint (*iw_create_listen)(struct iw_cm_id *, int);\n\tint (*iw_destroy_listen)(struct iw_cm_id *);\n\tint (*counter_bind_qp)(struct rdma_counter *, struct ib_qp *, u32);\n\tint (*counter_unbind_qp)(struct ib_qp *, u32);\n\tint (*counter_dealloc)(struct rdma_counter *);\n\tstruct rdma_hw_stats * (*counter_alloc_stats)(struct rdma_counter *);\n\tint (*counter_update_stats)(struct rdma_counter *);\n\tvoid (*counter_init)(struct rdma_counter *);\n\tint (*fill_stat_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*query_ucontext)(struct ib_ucontext *, struct uverbs_attr_bundle *);\n\tint (*get_numa_node)(struct ib_device *);\n\tstruct ib_device * (*add_sub_dev)(struct ib_device *, enum rdma_nl_dev_type, const char *);\n\tvoid (*del_sub_dev)(struct ib_device *);\n\tvoid (*ufile_hw_cleanup)(struct ib_uverbs_file *);\n\tvoid (*report_port_event)(struct ib_device *, struct net_device *, long unsigned int);\n\tsize_t size_ib_ah;\n\tsize_t size_ib_counters;\n\tsize_t size_ib_cq;\n\tsize_t size_ib_dmah;\n\tsize_t size_ib_mw;\n\tsize_t size_ib_pd;\n\tsize_t size_ib_qp;\n\tsize_t size_ib_rwq_ind_table;\n\tsize_t size_ib_srq;\n\tsize_t size_ib_ucontext;\n\tsize_t size_ib_xrcd;\n\tsize_t size_rdma_counter;\n};\n\nstruct ib_odp_caps {\n\tuint64_t general_caps;\n\tstruct {\n\t\tuint32_t rc_odp_caps;\n\t\tuint32_t uc_odp_caps;\n\t\tuint32_t ud_odp_caps;\n\t\tuint32_t xrc_odp_caps;\n\t} per_transport_caps;\n};\n\nstruct ib_rss_caps {\n\tu32 supported_qpts;\n\tu32 max_rwq_indirection_tables;\n\tu32 max_rwq_indirection_table_size;\n};\n\nstruct ib_tm_caps {\n\tu32 max_rndv_hdr_size;\n\tu32 max_num_tags;\n\tu32 flags;\n\tu32 max_ops;\n\tu32 max_sge;\n};\n\nstruct ib_device_attr {\n\tu64 fw_ver;\n\t__be64 sys_image_guid;\n\tu64 max_mr_size;\n\tu64 page_size_cap;\n\tu32 vendor_id;\n\tu32 vendor_part_id;\n\tu32 hw_ver;\n\tint max_qp;\n\tint max_qp_wr;\n\tu64 device_cap_flags;\n\tu64 kernel_cap_flags;\n\tint max_send_sge;\n\tint max_recv_sge;\n\tint max_sge_rd;\n\tint max_cq;\n\tint max_cqe;\n\tint max_mr;\n\tint max_pd;\n\tint max_qp_rd_atom;\n\tint max_ee_rd_atom;\n\tint max_res_rd_atom;\n\tint max_qp_init_rd_atom;\n\tint max_ee_init_rd_atom;\n\tenum ib_atomic_cap atomic_cap;\n\tenum ib_atomic_cap masked_atomic_cap;\n\tint max_ee;\n\tint max_rdd;\n\tint max_mw;\n\tint max_raw_ipv6_qp;\n\tint max_raw_ethy_qp;\n\tint max_mcast_grp;\n\tint max_mcast_qp_attach;\n\tint max_total_mcast_qp_attach;\n\tint max_ah;\n\tint max_srq;\n\tint max_srq_wr;\n\tint max_srq_sge;\n\tunsigned int max_fast_reg_page_list_len;\n\tunsigned int max_pi_fast_reg_page_list_len;\n\tu16 max_pkeys;\n\tu8 local_ca_ack_delay;\n\tint sig_prot_cap;\n\tint sig_guard_cap;\n\tstruct ib_odp_caps odp_caps;\n\tuint64_t timestamp_mask;\n\tuint64_t hca_core_clock;\n\tstruct ib_rss_caps rss_caps;\n\tu32 max_wq_type_rq;\n\tu32 raw_packet_caps;\n\tstruct ib_tm_caps tm_caps;\n\tstruct ib_cq_caps cq_caps;\n\tu64 max_dm_size;\n\tu32 max_sgl_rd;\n};\n\nstruct hw_stats_device_data;\n\nstruct rdma_restrack_root;\n\nstruct uapi_definition;\n\nstruct ib_port_data;\n\nstruct rdma_link_ops;\n\nstruct ib_device {\n\tstruct device *dma_device;\n\tstruct ib_device_ops ops;\n\tchar name[64];\n\tstruct callback_head callback_head;\n\tstruct list_head event_handler_list;\n\tstruct rw_semaphore event_handler_rwsem;\n\tspinlock_t qp_open_list_lock;\n\tstruct rw_semaphore client_data_rwsem;\n\tstruct xarray client_data;\n\tstruct mutex unregistration_lock;\n\trwlock_t cache_lock;\n\tstruct ib_port_data *port_data;\n\tint num_comp_vectors;\n\tunion {\n\t\tstruct device dev;\n\t\tstruct ib_core_device coredev;\n\t};\n\tconst struct attribute_group *groups[4];\n\tu8 hw_stats_attr_index;\n\tu64 uverbs_cmd_mask;\n\tchar node_desc[64];\n\t__be64 node_guid;\n\tu32 local_dma_lkey;\n\tu16 is_switch: 1;\n\tu16 kverbs_provider: 1;\n\tu16 use_cq_dim: 1;\n\tu8 node_type;\n\tu32 phys_port_cnt;\n\tstruct ib_device_attr attrs;\n\tstruct hw_stats_device_data *hw_stats_data;\n\tu32 index;\n\tspinlock_t cq_pools_lock;\n\tstruct list_head cq_pools[3];\n\tstruct rdma_restrack_root *res;\n\tconst struct uapi_definition *driver_def;\n\trefcount_t refcount;\n\tstruct completion unreg_completion;\n\tstruct work_struct unregistration_work;\n\tconst struct rdma_link_ops *link_ops;\n\tstruct mutex compat_devs_mutex;\n\tstruct xarray compat_devs;\n\tchar iw_ifname[16];\n\tu32 iw_driver_flags;\n\tu32 lag_flags;\n\tstruct mutex subdev_lock;\n\tstruct list_head subdev_list_head;\n\tenum rdma_nl_dev_type type;\n\tstruct ib_device *parent;\n\tstruct list_head subdev_list;\n\tenum rdma_nl_name_assign_type name_assign_type;\n};\n\nstruct ib_device_modify {\n\tu64 sys_image_guid;\n\tchar node_desc[64];\n};\n\nstruct ib_dm {\n\tstruct ib_device *device;\n\tu32 length;\n\tu32 flags;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_dm_alloc_attr {\n\tu64 length;\n\tu32 alignment;\n\tu32 flags;\n};\n\nstruct ib_dm_mr_attr {\n\tu64 length;\n\tu64 offset;\n\tu32 access_flags;\n};\n\nstruct ib_dmah {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tstruct rdma_restrack_entry res;\n\tu32 cpu_id;\n\tenum tph_mem_type mem_type;\n\tatomic_t usecnt;\n\tu8 ph;\n\tu8 valid_fields;\n};\n\nstruct ib_event {\n\tstruct ib_device *device;\n\tunion {\n\t\tstruct ib_cq *cq;\n\t\tstruct ib_qp *qp;\n\t\tstruct ib_srq *srq;\n\t\tstruct ib_wq *wq;\n\t\tu32 port_num;\n\t} element;\n\tenum ib_event_type event;\n};\n\nstruct ib_flow {\n\tstruct ib_qp *qp;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n};\n\nstruct ib_flow_action {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tenum ib_flow_action_type type;\n\tatomic_t usecnt;\n};\n\nstruct ib_flow_eth_filter {\n\tu8 dst_mac[6];\n\tu8 src_mac[6];\n\t__be16 ether_type;\n\t__be16 vlan_tag;\n};\n\nstruct ib_flow_spec_eth {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_eth_filter val;\n\tstruct ib_flow_eth_filter mask;\n};\n\nstruct ib_flow_ib_filter {\n\t__be16 dlid;\n\t__u8 sl;\n};\n\nstruct ib_flow_spec_ib {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ib_filter val;\n\tstruct ib_flow_ib_filter mask;\n};\n\nstruct ib_flow_ipv4_filter {\n\t__be32 src_ip;\n\t__be32 dst_ip;\n\tu8 proto;\n\tu8 tos;\n\tu8 ttl;\n\tu8 flags;\n};\n\nstruct ib_flow_spec_ipv4 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv4_filter val;\n\tstruct ib_flow_ipv4_filter mask;\n};\n\nstruct ib_flow_tcp_udp_filter {\n\t__be16 dst_port;\n\t__be16 src_port;\n};\n\nstruct ib_flow_spec_tcp_udp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tcp_udp_filter val;\n\tstruct ib_flow_tcp_udp_filter mask;\n};\n\nstruct ib_flow_ipv6_filter {\n\tu8 src_ip[16];\n\tu8 dst_ip[16];\n\t__be32 flow_label;\n\tu8 next_hdr;\n\tu8 traffic_class;\n\tu8 hop_limit;\n} __attribute__((packed));\n\nstruct ib_flow_spec_ipv6 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv6_filter val;\n\tstruct ib_flow_ipv6_filter mask;\n};\n\nstruct ib_flow_tunnel_filter {\n\t__be32 tunnel_id;\n};\n\nstruct ib_flow_spec_tunnel {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tunnel_filter val;\n\tstruct ib_flow_tunnel_filter mask;\n};\n\nstruct ib_flow_esp_filter {\n\t__be32 spi;\n\t__be32 seq;\n};\n\nstruct ib_flow_spec_esp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_esp_filter val;\n\tstruct ib_flow_esp_filter mask;\n};\n\nstruct ib_flow_gre_filter {\n\t__be16 c_ks_res0_ver;\n\t__be16 protocol;\n\t__be32 key;\n};\n\nstruct ib_flow_spec_gre {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_gre_filter val;\n\tstruct ib_flow_gre_filter mask;\n};\n\nstruct ib_flow_mpls_filter {\n\t__be32 tag;\n};\n\nstruct ib_flow_spec_mpls {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_mpls_filter val;\n\tstruct ib_flow_mpls_filter mask;\n};\n\nstruct ib_flow_spec_action_tag {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tu32 tag_id;\n};\n\nstruct ib_flow_spec_action_drop {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n};\n\nstruct ib_flow_spec_action_handle {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_flow_action *act;\n};\n\nstruct ib_flow_spec_action_count {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_counters *counters;\n};\n\nunion ib_flow_spec {\n\tstruct {\n\t\tu32 type;\n\t\tu16 size;\n\t};\n\tstruct ib_flow_spec_eth eth;\n\tstruct ib_flow_spec_ib ib;\n\tstruct ib_flow_spec_ipv4 ipv4;\n\tstruct ib_flow_spec_tcp_udp tcp_udp;\n\tstruct ib_flow_spec_ipv6 ipv6;\n\tstruct ib_flow_spec_tunnel tunnel;\n\tstruct ib_flow_spec_esp esp;\n\tstruct ib_flow_spec_gre gre;\n\tstruct ib_flow_spec_mpls mpls;\n\tstruct ib_flow_spec_action_tag flow_tag;\n\tstruct ib_flow_spec_action_drop drop;\n\tstruct ib_flow_spec_action_handle action;\n\tstruct ib_flow_spec_action_count flow_count;\n};\n\nstruct ib_flow_attr {\n\tenum ib_flow_attr_type type;\n\tu16 size;\n\tu16 priority;\n\tu32 flags;\n\tu8 num_of_specs;\n\tu32 port;\n\tunion ib_flow_spec flows[0];\n};\n\nunion ib_gid {\n\tu8 raw[16];\n\tstruct {\n\t\t__be64 subnet_prefix;\n\t\t__be64 interface_id;\n\t} global;\n};\n\nstruct ib_gid_attr {\n\tstruct net_device *ndev;\n\tstruct ib_device *device;\n\tunion ib_gid gid;\n\tenum ib_gid_type gid_type;\n\tu16 index;\n\tu32 port_num;\n};\n\nstruct ib_global_route {\n\tconst struct ib_gid_attr *sgid_attr;\n\tunion ib_gid dgid;\n\tu32 flow_label;\n\tu8 sgid_index;\n\tu8 hop_limit;\n\tu8 traffic_class;\n};\n\nstruct ib_grh {\n\t__be32 version_tclass_flow;\n\t__be16 paylen;\n\tu8 next_hdr;\n\tu8 hop_limit;\n\tunion ib_gid sgid;\n\tunion ib_gid dgid;\n};\n\nstruct ib_sig_attrs;\n\nstruct ib_mr {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tu32 lkey;\n\tu32 rkey;\n\tu64 iova;\n\tu64 length;\n\tunsigned int page_size;\n\tenum ib_mr_type type;\n\tbool need_inval;\n\tunion {\n\t\tstruct ib_uobject *uobject;\n\t\tstruct list_head qp_entry;\n\t};\n\tstruct ib_dm *dm;\n\tstruct ib_sig_attrs *sig_attrs;\n\tstruct ib_dmah *dmah;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_sig_err {\n\tenum ib_sig_err_type err_type;\n\tu32 expected;\n\tu32 actual;\n\tu64 sig_err_offset;\n\tu32 key;\n};\n\nstruct ib_mr_status {\n\tu32 fail_status;\n\tstruct ib_sig_err sig_err;\n};\n\nstruct ib_mw {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tu32 rkey;\n\tenum ib_mw_type type;\n};\n\nstruct ib_pd {\n\tu32 local_dma_lkey;\n\tu32 flags;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 unsafe_global_rkey;\n\tstruct ib_mr *__internal_mr;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_port_attr {\n\tu64 subnet_prefix;\n\tenum ib_port_state state;\n\tenum ib_mtu max_mtu;\n\tenum ib_mtu active_mtu;\n\tu32 phys_mtu;\n\tint gid_tbl_len;\n\tunsigned int ip_gids: 1;\n\tu32 port_cap_flags;\n\tu32 max_msg_sz;\n\tu32 bad_pkey_cntr;\n\tu32 qkey_viol_cntr;\n\tu16 pkey_tbl_len;\n\tu32 sm_lid;\n\tu32 lid;\n\tu8 lmc;\n\tu8 max_vl_num;\n\tu8 sm_sl;\n\tu8 subnet_timeout;\n\tu8 init_type_reply;\n\tu8 active_width;\n\tu16 active_speed;\n\tu8 phys_state;\n\tu16 port_cap_flags2;\n};\n\nstruct ib_pkey_cache;\n\nstruct ib_gid_table;\n\nstruct ib_port_cache {\n\tu64 subnet_prefix;\n\tstruct ib_pkey_cache *pkey;\n\tstruct ib_gid_table *gid;\n\tu8 lmc;\n\tenum ib_port_state port_state;\n\tenum ib_port_state last_port_state;\n};\n\nstruct ib_port_immutable {\n\tint pkey_tbl_len;\n\tint gid_tbl_len;\n\tu32 core_cap_flags;\n\tu32 max_mad_size;\n};\n\nstruct rdma_counter_mode {\n\tenum rdma_nl_counter_mode mode;\n\tenum rdma_nl_counter_mask mask;\n\tstruct auto_mode_param param;\n\tbool bind_opcnt;\n};\n\nstruct rdma_port_counter {\n\tstruct rdma_counter_mode mode;\n\tstruct rdma_hw_stats *hstats;\n\tunsigned int num_counters;\n\tstruct mutex lock;\n};\n\nstruct ib_port;\n\nstruct ib_port_data {\n\tstruct ib_device *ib_dev;\n\tstruct ib_port_immutable immutable;\n\tspinlock_t pkey_list_lock;\n\tspinlock_t netdev_lock;\n\tstruct list_head pkey_list;\n\tstruct ib_port_cache cache;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\tstruct hlist_node ndev_hash_link;\n\tstruct rdma_port_counter port_counter;\n\tstruct ib_port *sysfs;\n};\n\nstruct ib_port_modify {\n\tu32 set_port_cap_mask;\n\tu32 clr_port_cap_mask;\n\tu8 init_type;\n};\n\nstruct ib_qp_security;\n\nstruct ib_port_pkey {\n\tenum port_pkey_state state;\n\tu16 pkey_index;\n\tu32 port_num;\n\tstruct list_head qp_list;\n\tstruct list_head to_error_list;\n\tstruct ib_qp_security *sec;\n};\n\nstruct ib_ports_pkeys {\n\tstruct ib_port_pkey main;\n\tstruct ib_port_pkey alt;\n};\n\nstruct ib_uqp_object;\n\nstruct ib_qp {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tspinlock_t mr_lock;\n\tint mrs_used;\n\tstruct list_head rdma_mrs;\n\tstruct list_head sig_mrs;\n\tstruct ib_srq *srq;\n\tstruct completion srq_completion;\n\tstruct ib_xrcd *xrcd;\n\tstruct list_head xrcd_list;\n\tatomic_t usecnt;\n\tstruct list_head open_list;\n\tstruct ib_qp *real_qp;\n\tstruct ib_uqp_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid (*registered_event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tconst struct ib_gid_attr *av_sgid_attr;\n\tconst struct ib_gid_attr *alt_path_sgid_attr;\n\tu32 qp_num;\n\tu32 max_write_sge;\n\tu32 max_read_sge;\n\tenum ib_qp_type qp_type;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tstruct ib_qp_security *qp_sec;\n\tu32 port;\n\tbool integrity_en;\n\tstruct rdma_restrack_entry res;\n\tstruct rdma_counter *counter;\n};\n\nstruct ib_qp_cap {\n\tu32 max_send_wr;\n\tu32 max_recv_wr;\n\tu32 max_send_sge;\n\tu32 max_recv_sge;\n\tu32 max_inline_data;\n\tu32 max_rdma_ctxs;\n};\n\nstruct roce_ah_attr {\n\tu8 dmac[6];\n};\n\nstruct opa_ah_attr {\n\tu32 dlid;\n\tu8 src_path_bits;\n\tbool make_grd;\n};\n\nstruct rdma_ah_attr {\n\tstruct ib_global_route grh;\n\tu8 sl;\n\tu8 static_rate;\n\tu32 port_num;\n\tu8 ah_flags;\n\tenum rdma_ah_attr_type type;\n\tunion {\n\t\tstruct ib_ah_attr ib;\n\t\tstruct roce_ah_attr roce;\n\t\tstruct opa_ah_attr opa;\n\t};\n};\n\nstruct ib_qp_attr {\n\tenum ib_qp_state qp_state;\n\tenum ib_qp_state cur_qp_state;\n\tenum ib_mtu path_mtu;\n\tenum ib_mig_state path_mig_state;\n\tu32 qkey;\n\tu32 rq_psn;\n\tu32 sq_psn;\n\tu32 dest_qp_num;\n\tint qp_access_flags;\n\tstruct ib_qp_cap cap;\n\tstruct rdma_ah_attr ah_attr;\n\tstruct rdma_ah_attr alt_ah_attr;\n\tu16 pkey_index;\n\tu16 alt_pkey_index;\n\tu8 en_sqd_async_notify;\n\tu8 sq_draining;\n\tu8 max_rd_atomic;\n\tu8 max_dest_rd_atomic;\n\tu8 min_rnr_timer;\n\tu32 port_num;\n\tu8 timeout;\n\tu8 retry_cnt;\n\tu8 rnr_retry;\n\tu32 alt_port_num;\n\tu8 alt_timeout;\n\tu32 rate_limit;\n\tstruct net_device *xmit_slave;\n};\n\nstruct ib_qp_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tstruct ib_srq *srq;\n\tstruct ib_xrcd *xrcd;\n\tstruct ib_qp_cap cap;\n\tenum ib_sig_type sq_sig_type;\n\tenum ib_qp_type qp_type;\n\tu32 create_flags;\n\tu32 port_num;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tu32 source_qpn;\n};\n\nstruct ib_qp_security {\n\tstruct ib_qp *qp;\n\tstruct ib_device *dev;\n\tstruct mutex mutex;\n\tstruct ib_ports_pkeys *ports_pkeys;\n\tstruct list_head shared_qp_list;\n\tvoid *security;\n\tbool destroying;\n\tatomic_t error_list_count;\n\tstruct completion error_complete;\n\tint error_comps_pending;\n};\n\nstruct ib_rdmacg_object {};\n\nstruct ib_recv_wr {\n\tstruct ib_recv_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n};\n\nstruct ib_rwq_ind_table {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 ind_tbl_num;\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_rwq_ind_table_init_attr {\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_send_wr {\n\tstruct ib_send_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n\tenum ib_wr_opcode opcode;\n\tint send_flags;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n};\n\nstruct ib_sge {\n\tu64 addr;\n\tu32 length;\n\tu32 lkey;\n};\n\nstruct ib_t10_dif_domain {\n\tenum ib_t10_dif_bg_type bg_type;\n\tu16 pi_interval;\n\tu16 bg;\n\tu16 app_tag;\n\tu32 ref_tag;\n\tbool ref_remap;\n\tbool app_escape;\n\tbool ref_escape;\n\tu16 apptag_check_mask;\n};\n\nstruct ib_sig_domain {\n\tenum ib_signature_type sig_type;\n\tunion {\n\t\tstruct ib_t10_dif_domain dif;\n\t} sig;\n};\n\nstruct ib_sig_attrs {\n\tu8 check_mask;\n\tstruct ib_sig_domain mem;\n\tstruct ib_sig_domain wire;\n\tint meta_length;\n};\n\nstruct ib_usrq_object;\n\nstruct ib_srq {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_usrq_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tenum ib_srq_type srq_type;\n\tatomic_t usecnt;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t\tu32 srq_num;\n\t\t\t} xrc;\n\t\t};\n\t} ext;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_srq_attr {\n\tu32 max_wr;\n\tu32 max_sge;\n\tu32 srq_limit;\n};\n\nstruct ib_srq_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tstruct ib_srq_attr attr;\n\tenum ib_srq_type srq_type;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t} xrc;\n\t\t\tstruct {\n\t\t\t\tu32 max_num_tags;\n\t\t\t} tag_matching;\n\t\t};\n\t} ext;\n};\n\nstruct ib_ucontext {\n\tstruct ib_device *device;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_rdmacg_object cg_obj;\n\tu64 enabled_caps;\n\tstruct rdma_restrack_entry res;\n\tstruct xarray mmap_xa;\n};\n\nstruct ib_udata {\n\tconst void *inbuf;\n\tvoid *outbuf;\n\tsize_t inlen;\n\tsize_t outlen;\n};\n\nstruct uverbs_api_object;\n\nstruct ib_uobject {\n\tu64 user_handle;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_ucontext *context;\n\tvoid *object;\n\tstruct list_head list;\n\tstruct ib_rdmacg_object cg_obj;\n\tint id;\n\tstruct kref ref;\n\tatomic_t usecnt;\n\tstruct callback_head rcu;\n\tconst struct uverbs_api_object *uapi_object;\n};\n\nstruct ib_wc {\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tenum ib_wc_status status;\n\tenum ib_wc_opcode opcode;\n\tu32 vendor_err;\n\tu32 byte_len;\n\tstruct ib_qp *qp;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tu32 src_qp;\n\tu32 slid;\n\tint wc_flags;\n\tu16 pkey_index;\n\tu8 sl;\n\tu8 dlid_path_bits;\n\tu32 port_num;\n\tu8 smac[6];\n\tu16 vlan_id;\n\tu8 network_hdr_type;\n};\n\nstruct ib_uwq_object;\n\nstruct ib_wq {\n\tstruct ib_device *device;\n\tstruct ib_uwq_object *uobject;\n\tvoid *wq_context;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tstruct ib_pd *pd;\n\tstruct ib_cq *cq;\n\tu32 wq_num;\n\tenum ib_wq_state state;\n\tenum ib_wq_type wq_type;\n\tatomic_t usecnt;\n};\n\nstruct ib_wq_attr {\n\tenum ib_wq_state wq_state;\n\tenum ib_wq_state curr_wq_state;\n\tu32 flags;\n\tu32 flags_mask;\n};\n\nstruct ib_wq_init_attr {\n\tvoid *wq_context;\n\tenum ib_wq_type wq_type;\n\tu32 max_wr;\n\tu32 max_sge;\n\tstruct ib_cq *cq;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tu32 create_flags;\n};\n\nstruct ib_xrcd {\n\tstruct ib_device *device;\n\tatomic_t usecnt;\n\tstruct inode *inode;\n\tstruct rw_semaphore tgt_qps_rwsem;\n\tstruct xarray tgt_qps;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct ich8_pr {\n\tu32 base: 13;\n\tu32 reserved1: 2;\n\tu32 rpe: 1;\n\tu32 limit: 13;\n\tu32 reserved2: 2;\n\tu32 wpe: 1;\n};\n\nunion ich8_flash_protected_range {\n\tstruct ich8_pr range;\n\tu32 regval;\n};\n\nstruct ich8_hsflctl {\n\tu16 flcgo: 1;\n\tu16 flcycle: 2;\n\tu16 reserved: 5;\n\tu16 fldbcount: 2;\n\tu16 flockdn: 6;\n};\n\nstruct ich8_hsfsts {\n\tu16 flcdone: 1;\n\tu16 flcerr: 1;\n\tu16 dael: 1;\n\tu16 berasesz: 2;\n\tu16 flcinprog: 1;\n\tu16 reserved1: 2;\n\tu16 reserved2: 6;\n\tu16 fldesvalid: 1;\n\tu16 flockdn: 1;\n};\n\nunion ich8_hws_flash_ctrl {\n\tstruct ich8_hsflctl hsf_ctrl;\n\tu16 regval;\n};\n\nunion ich8_hws_flash_status {\n\tstruct ich8_hsfsts hsf_status;\n\tu16 regval;\n};\n\nstruct icmp6_err {\n\tint err;\n\tint fatal;\n};\n\nstruct icmp6_ext_iio_addr6_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\tstruct in6_addr addr6;\n};\n\nstruct icmp6_filter {\n\t__u32 data[8];\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 reserved1: 4;\n\t__u8 version: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[7];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6_msg {\n\tstruct sk_buff *skb;\n\tint offset;\n\tuint8_t type;\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[16];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n};\n\nstruct idmac_desc {\n\t__le32 des0;\n\t__le32 des1;\n\t__le32 des2;\n\t__le32 des3;\n};\n\nstruct idmac_desc_64addr {\n\tu32 des0;\n\tu32 des1;\n\tu32 des2;\n\tu32 des3;\n\tu32 des4;\n\tu32 des5;\n\tu32 des6;\n\tu32 des7;\n};\n\nstruct rpc_pipe_dir_object_ops;\n\nstruct rpc_pipe_dir_object {\n\tstruct list_head pdo_head;\n\tconst struct rpc_pipe_dir_object_ops *pdo_ops;\n\tvoid *pdo_data;\n};\n\nstruct rpc_pipe;\n\nstruct idmap_legacy_upcalldata;\n\nstruct idmap {\n\tstruct rpc_pipe_dir_object idmap_pdo;\n\tstruct rpc_pipe *idmap_pipe;\n\tstruct idmap_legacy_upcalldata *idmap_upcall_data;\n\tstruct mutex idmap_mutex;\n\tstruct user_namespace *user_ns;\n};\n\nstruct idmap_key {\n\tbool map_up;\n\tu32 id;\n\tu32 count;\n};\n\nstruct rpc_pipe_msg {\n\tstruct list_head list;\n\tvoid *data;\n\tsize_t len;\n\tsize_t copied;\n\tint errno;\n};\n\nstruct idmap_msg {\n\t__u8 im_type;\n\t__u8 im_conv;\n\tchar im_name[128];\n\t__u32 im_id;\n\t__u8 im_status;\n};\n\nstruct idmap_legacy_upcalldata {\n\tstruct rpc_pipe_msg pipe_msg;\n\tstruct idmap_msg idmap_msg;\n\tstruct key *authkey;\n\tstruct idmap *idmap;\n};\n\nstruct if6_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tint offset;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa6_config {\n\tconst struct in6_addr *pfx;\n\tunsigned int plen;\n\tu8 ifa_proto;\n\tconst struct in6_addr *peer_pfx;\n\tu32 rt_priority;\n\tu32 ifa_flags;\n\tu32 preferred_lft;\n\tu32 valid_lft;\n\tu16 scope;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifaddrlblmsg {\n\t__u8 ifal_family;\n\t__u8 __ifal_reserved;\n\t__u8 ifal_prefixlen;\n\t__u8 ifal_flags;\n\t__u32 ifal_index;\n\t__u32 ifal_seq;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_cacheinfo {\n\t__u32 max_reasm_len;\n\t__u32 tstamp;\n\t__u32 reachable_time;\n\t__u32 retrans_time;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct inet6_dev;\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct igmp6_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct igmp6_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *im;\n};\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 qrv: 3;\n\t__u8 suppress: 1;\n\t__u8 resv: 4;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct ignore_entry {\n\tu16 vid;\n\tu16 pid;\n\tu16 bcdmin;\n\tu16 bcdmax;\n};\n\nstruct iio_dev;\n\nstruct iio_buffer_setup_ops {\n\tint (*preenable)(struct iio_dev *);\n\tint (*postenable)(struct iio_dev *);\n\tint (*predisable)(struct iio_dev *);\n\tint (*postdisable)(struct iio_dev *);\n\tbool (*validate_scan_mask)(struct iio_dev *, const long unsigned int *);\n};\n\nstruct iio_scan_type {\n\tchar sign;\n\tu8 realbits;\n\tu8 storagebits;\n\tu8 shift;\n\tu8 repeat;\n\tenum iio_endian endianness;\n};\n\nstruct iio_event_spec;\n\nstruct iio_chan_spec_ext_info;\n\nstruct iio_chan_spec {\n\tenum iio_chan_type type;\n\tint channel;\n\tint channel2;\n\tlong unsigned int address;\n\tint scan_index;\n\tunion {\n\t\tstruct iio_scan_type scan_type;\n\t\tstruct {\n\t\t\tconst struct iio_scan_type *ext_scan_type;\n\t\t\tunsigned int num_ext_scan_type;\n\t\t};\n\t};\n\tlong unsigned int info_mask_separate;\n\tlong unsigned int info_mask_separate_available;\n\tlong unsigned int info_mask_shared_by_type;\n\tlong unsigned int info_mask_shared_by_type_available;\n\tlong unsigned int info_mask_shared_by_dir;\n\tlong unsigned int info_mask_shared_by_dir_available;\n\tlong unsigned int info_mask_shared_by_all;\n\tlong unsigned int info_mask_shared_by_all_available;\n\tconst struct iio_event_spec *event_spec;\n\tunsigned int num_event_specs;\n\tconst struct iio_chan_spec_ext_info *ext_info;\n\tconst char *extend_name;\n\tconst char *datasheet_name;\n\tunsigned int modified: 1;\n\tunsigned int indexed: 1;\n\tunsigned int output: 1;\n\tunsigned int differential: 1;\n\tunsigned int has_ext_scan_type: 1;\n};\n\nstruct iio_chan_spec_ext_info {\n\tconst char *name;\n\tenum iio_shared_by shared;\n\tssize_t (*read)(struct iio_dev *, uintptr_t, const struct iio_chan_spec *, char *);\n\tssize_t (*write)(struct iio_dev *, uintptr_t, const struct iio_chan_spec *, const char *, size_t);\n\tuintptr_t private;\n};\n\nstruct iio_channel {\n\tstruct iio_dev *indio_dev;\n\tconst struct iio_chan_spec *channel;\n\tvoid *data;\n};\n\nstruct iio_const_attr {\n\tconst char *string;\n\tstruct device_attribute dev_attr;\n};\n\nstruct iio_buffer;\n\nstruct iio_trigger;\n\nstruct iio_poll_func;\n\nstruct iio_info;\n\nstruct iio_dev {\n\tint modes;\n\tstruct device dev;\n\tstruct iio_buffer *buffer;\n\tint scan_bytes;\n\tconst long unsigned int *available_scan_masks;\n\tunsigned int masklength;\n\tconst long unsigned int *active_scan_mask;\n\tbool scan_timestamp;\n\tstruct iio_trigger *trig;\n\tstruct iio_poll_func *pollfunc;\n\tstruct iio_poll_func *pollfunc_event;\n\tconst struct iio_chan_spec *channels;\n\tint num_channels;\n\tconst char *name;\n\tconst char *label;\n\tconst struct iio_info *info;\n\tconst struct iio_buffer_setup_ops *setup_ops;\n\tvoid *priv;\n};\n\nstruct iio_dev_attr {\n\tstruct device_attribute dev_attr;\n\tu64 address;\n\tstruct list_head l;\n\tconst struct iio_chan_spec *c;\n\tstruct iio_buffer *buffer;\n};\n\nstruct iio_dev_buffer_pair {\n\tstruct iio_dev *indio_dev;\n\tstruct iio_buffer *buffer;\n};\n\nstruct iio_event_interface;\n\nstruct iio_ioctl_handler;\n\nstruct iio_dev_opaque {\n\tstruct iio_dev indio_dev;\n\tint currentmode;\n\tint id;\n\tstruct module *driver_module;\n\tstruct mutex mlock;\n\tstruct lock_class_key mlock_key;\n\tstruct mutex info_exist_lock;\n\tstruct lock_class_key info_exist_key;\n\tbool trig_readonly;\n\tstruct iio_event_interface *event_interface;\n\tstruct iio_buffer **attached_buffers;\n\tunsigned int attached_buffers_cnt;\n\tstruct iio_ioctl_handler *buffer_ioctl_handler;\n\tstruct list_head buffer_list;\n\tstruct list_head channel_attr_list;\n\tstruct attribute_group chan_attr_group;\n\tstruct list_head ioctl_handlers;\n\tconst struct attribute_group **groups;\n\tint groupcounter;\n\tstruct attribute_group legacy_scan_el_group;\n\tstruct attribute_group legacy_buffer_group;\n\tvoid *bounce_buffer;\n\tsize_t bounce_buffer_size;\n\tunsigned int scan_index_timestamp;\n\tclockid_t clock_id;\n\tstruct cdev chrdev;\n\tlong unsigned int flags;\n\tstruct dentry *debugfs_dentry;\n\tunsigned int cached_reg_addr;\n\tchar read_buf[20];\n\tunsigned int read_buf_len;\n};\n\nstruct iio_enum {\n\tconst char * const *items;\n\tunsigned int num_items;\n\tint (*set)(struct iio_dev *, const struct iio_chan_spec *, unsigned int);\n\tint (*get)(struct iio_dev *, const struct iio_chan_spec *);\n};\n\nstruct iio_event_data {\n\t__u64 id;\n\t__s64 timestamp;\n};\n\nstruct iio_ioctl_handler {\n\tstruct list_head entry;\n\tlong int (*ioctl)(struct iio_dev *, struct file *, unsigned int, long unsigned int);\n};\n\nstruct iio_event_interface {\n\twait_queue_head_t wait;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct iio_event_data *type;\n\t\t\tconst struct iio_event_data *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct iio_event_data *ptr;\n\t\t\tconst struct iio_event_data *ptr_const;\n\t\t};\n\t\tstruct iio_event_data buf[16];\n\t} det_events;\n\tstruct list_head dev_attr_list;\n\tlong unsigned int flags;\n\tstruct attribute_group group;\n\tstruct mutex read_lock;\n\tstruct iio_ioctl_handler ioctl_handler;\n};\n\nstruct iio_event_spec {\n\tenum iio_event_type type;\n\tenum iio_event_direction dir;\n\tlong unsigned int mask_separate;\n\tlong unsigned int mask_shared_by_type;\n\tlong unsigned int mask_shared_by_dir;\n\tlong unsigned int mask_shared_by_all;\n};\n\nstruct iio_info {\n\tconst struct attribute_group *event_attrs;\n\tconst struct attribute_group *attrs;\n\tint (*read_raw)(struct iio_dev *, const struct iio_chan_spec *, int *, int *, long int);\n\tint (*read_raw_multi)(struct iio_dev *, const struct iio_chan_spec *, int, int *, int *, long int);\n\tint (*read_avail)(struct iio_dev *, const struct iio_chan_spec *, const int **, int *, int *, long int);\n\tint (*write_raw)(struct iio_dev *, const struct iio_chan_spec *, int, int, long int);\n\tint (*read_label)(struct iio_dev *, const struct iio_chan_spec *, char *);\n\tint (*write_raw_get_fmt)(struct iio_dev *, const struct iio_chan_spec *, long int);\n\tint (*read_event_config)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction);\n\tint (*write_event_config)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, bool);\n\tint (*read_event_value)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, enum iio_event_info, int *, int *);\n\tint (*write_event_value)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, enum iio_event_info, int, int);\n\tint (*read_event_label)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, char *);\n\tint (*validate_trigger)(struct iio_dev *, struct iio_trigger *);\n\tint (*get_current_scan_type)(const struct iio_dev *, const struct iio_chan_spec *);\n\tint (*update_scan_mode)(struct iio_dev *, const long unsigned int *);\n\tint (*debugfs_reg_access)(struct iio_dev *, unsigned int, unsigned int, unsigned int *);\n\tint (*fwnode_xlate)(struct iio_dev *, const struct fwnode_reference_args *);\n\tint (*hwfifo_set_watermark)(struct iio_dev *, unsigned int);\n\tint (*hwfifo_flush_to_buffer)(struct iio_dev *, unsigned int);\n};\n\nstruct iio_map {\n\tconst char *adc_channel_label;\n\tconst char *consumer_dev_name;\n\tconst char *consumer_channel;\n\tvoid *consumer_data;\n};\n\nstruct iio_map_internal {\n\tstruct iio_dev *indio_dev;\n\tconst struct iio_map *map;\n\tstruct list_head l;\n};\n\nstruct iio_mount_matrix {\n\tconst char *rotation[9];\n};\n\nstruct imsic_local_config;\n\nstruct imsic_global_config {\n\tu32 guest_index_bits;\n\tu32 hart_index_bits;\n\tu32 group_index_bits;\n\tu32 group_index_shift;\n\tphys_addr_t base_addr;\n\tu32 nr_ids;\n\tu32 nr_guest_ids;\n\tu32 nr_guest_files;\n\tstruct imsic_local_config *local;\n};\n\nstruct imsic_local_config {\n\tphys_addr_t msi_pa;\n\tvoid *msi_va;\n};\n\nstruct imsic_vector;\n\nstruct imsic_local_priv {\n\traw_spinlock_t lock;\n\tlong unsigned int *dirty_bitmap;\n\tstruct timer_list timer;\n\tstruct imsic_vector *vectors;\n};\n\nstruct irq_matrix;\n\nstruct imsic_priv {\n\tstruct fwnode_handle *fwnode;\n\tstruct imsic_global_config global;\n\tstruct imsic_local_priv *lpriv;\n\traw_spinlock_t matrix_lock;\n\tstruct irq_matrix *matrix;\n\tstruct irq_domain *base_domain;\n};\n\nstruct imsic_vector {\n\tunsigned int cpu;\n\tunsigned int local_id;\n\tunsigned int irq;\n\tbool enable;\n\tstruct imsic_vector *move_next;\n\tstruct imsic_vector *move_prev;\n};\n\nstruct in6_flowlabel_req {\n\tstruct in6_addr flr_dst;\n\t__be32 flr_label;\n\t__u8 flr_action;\n\t__u8 flr_share;\n\t__u16 flr_flags;\n\t__u16 flr_expires;\n\t__u16 flr_linger;\n\t__u32 __flr_pad;\n};\n\nstruct in6_ifreq {\n\tstruct in6_addr ifr6_addr;\n\t__u32 ifr6_prefixlen;\n\tint ifr6_ifindex;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\t__u32 rtmsg_type;\n\t__u16 rtmsg_dst_len;\n\t__u16 rtmsg_src_len;\n\t__u32 rtmsg_metric;\n\tlong unsigned int rtmsg_info;\n\t__u32 rtmsg_flags;\n\tint rtmsg_ifindex;\n};\n\nstruct in6_validator_info {\n\tstruct in6_addr i6vi_addr;\n\tstruct inet6_dev *i6vi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[1];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv6_txoptions;\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n\tu8 dontfrag: 1;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n\tenum addr_type_t type;\n\tbool force_rt_scope_universe;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_skb_parm;\n\nstruct inet6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tshort unsigned int addr_type;\n\tstruct in6_addr v6_rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n\tstruct inet6_cork base6;\n};\n\nstruct ipv6_pinfo;\n\nstruct ipv6_fl_socklist;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_diag_bc_op {\n\tunsigned char code;\n\tunsigned char yes;\n\tshort unsigned int no;\n};\n\nstruct inet_diag_dump_data {\n\tstruct nlattr *req_nlas[4];\n\tstruct bpf_sk_storage_diag *bpf_stg_diag;\n\tbool mark_needed;\n\tbool cgroup_needed;\n\tbool userlocks_needed;\n};\n\nstruct inet_diag_entry {\n\tconst __be32 *saddr;\n\tconst __be32 *daddr;\n\tu16 sport;\n\tu16 dport;\n\tu16 family;\n\tu16 userlocks;\n\tu32 ifindex;\n\tu32 mark;\n\tu64 cgroup_id;\n};\n\nstruct inet_diag_req_v2;\n\nstruct inet_diag_msg;\n\nstruct inet_diag_handler {\n\tstruct module *owner;\n\tvoid (*dump)(struct sk_buff *, struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tint (*dump_one)(struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tvoid (*idiag_get_info)(struct sock *, struct inet_diag_msg *, void *);\n\tint (*idiag_get_aux)(struct sock *, bool, struct sk_buff *);\n\tint (*destroy)(struct sk_buff *, const struct inet_diag_req_v2 *);\n\t__u16 idiag_type;\n\t__u16 idiag_info_size;\n};\n\nstruct inet_diag_hostcond {\n\t__u8 family;\n\t__u8 prefix_len;\n\tint port;\n\t__be32 addr[0];\n};\n\nstruct inet_diag_markcond {\n\t__u32 mark;\n\t__u32 mask;\n};\n\nstruct inet_diag_meminfo {\n\t__u32 idiag_rmem;\n\t__u32 idiag_wmem;\n\t__u32 idiag_fmem;\n\t__u32 idiag_tmem;\n};\n\nstruct inet_diag_sockid {\n\t__be16 idiag_sport;\n\t__be16 idiag_dport;\n\t__be32 idiag_src[4];\n\t__be32 idiag_dst[4];\n\t__u32 idiag_if;\n\t__u32 idiag_cookie[2];\n};\n\nstruct inet_diag_msg {\n\t__u8 idiag_family;\n\t__u8 idiag_state;\n\t__u8 idiag_timer;\n\t__u8 idiag_retrans;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_expires;\n\t__u32 idiag_rqueue;\n\t__u32 idiag_wqueue;\n\t__u32 idiag_uid;\n\t__u32 idiag_inode;\n};\n\nstruct inet_diag_req {\n\t__u8 idiag_family;\n\t__u8 idiag_src_len;\n\t__u8 idiag_dst_len;\n\t__u8 idiag_ext;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_states;\n\t__u32 idiag_dbs;\n};\n\nstruct inet_diag_req_v2 {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u8 idiag_ext;\n\t__u8 pad;\n\t__u32 idiag_states;\n\tstruct inet_diag_sockid id;\n};\n\nstruct inet_diag_sockopt {\n\t__u8 recverr: 1;\n\t__u8 is_icsk: 1;\n\t__u8 freebind: 1;\n\t__u8 hdrincl: 1;\n\t__u8 mc_loop: 1;\n\t__u8 transparent: 1;\n\t__u8 mc_all: 1;\n\t__u8 nodefrag: 1;\n\t__u8 bind_address_no_port: 1;\n\t__u8 recverr_rfc4884: 1;\n\t__u8 defer_connect: 1;\n\t__u8 unused: 5;\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct proto_ops;\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inode_security_struct {\n\tstruct inode *inode;\n\tstruct list_head list;\n\tu32 task_sid;\n\tu32 sid;\n\tu16 sclass;\n\tunsigned char initialized;\n\tspinlock_t lock;\n};\n\nstruct inode_switch_wbs_context {\n\tstruct llist_node list;\n\tstruct inode *inodes[0];\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[12];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[1];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[2];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[12];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[12];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[1];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[2];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_event_compat {\n\tcompat_ulong_t sec;\n\tcompat_ulong_t usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct interval_tree_node {\n\tstruct rb_node rb;\n\tlong unsigned int start;\n\tlong unsigned int last;\n\tlong unsigned int __subtree_last;\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n\tspinlock_t lock;\n\tstruct xarray icq_tree;\n\tstruct io_cq *icq_hint;\n\tstruct hlist_head icq_list;\n\tstruct work_struct release_work;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[1];\n\tlong unsigned int sqe_op[2];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 64;\n\tlong: 64;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tlb_area {\n\tlong unsigned int used;\n\tunsigned int index;\n\tspinlock_t lock;\n};\n\nstruct io_tlb_slot;\n\nstruct io_tlb_pool {\n\tphys_addr_t start;\n\tphys_addr_t end;\n\tvoid *vaddr;\n\tlong unsigned int nslabs;\n\tbool late_alloc;\n\tunsigned int nareas;\n\tunsigned int area_nslabs;\n\tstruct io_tlb_area *areas;\n\tstruct io_tlb_slot *slots;\n};\n\nstruct io_tlb_mem {\n\tstruct io_tlb_pool defpool;\n\tlong unsigned int nslabs;\n\tstruct dentry *debugfs;\n\tbool force_bounce;\n\tbool for_alloc;\n\tatomic_long_t total_used;\n\tatomic_long_t used_hiwater;\n\tatomic_long_t transient_nslabs;\n};\n\nstruct io_tlb_slot {\n\tphys_addr_t orig_addr;\n\tsize_t alloc_size;\n\tshort unsigned int list;\n\tshort unsigned int pad_slots;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 64;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[64];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n\tlong: 64;\n};\n\nstruct ioam6_hdr {\n\t__u8 opt_type;\n\t__u8 opt_len;\n\tchar: 8;\n\t__u8 type;\n};\n\nstruct ioam6_schema;\n\nstruct ioam6_namespace {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_schema *schema;\n\t__be16 id;\n\t__be32 data;\n\t__be64 data_wide;\n};\n\nstruct ioam6_pernet_data {\n\tstruct mutex lock;\n\tstruct rhashtable namespaces;\n\tstruct rhashtable schemas;\n};\n\nstruct ioam6_schema {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_namespace *ns;\n\tu32 id;\n\tint len;\n\t__be32 hdr;\n\tu8 data[0];\n};\n\nstruct ioam6_trace_hdr {\n\t__be16 namespace_id;\n\tchar: 2;\n\t__u8 overflow: 1;\n\t__u8 nodelen: 5;\n\t__u8 remlen: 7;\n\tunion {\n\t\t__be32 type_be32;\n\t\tstruct {\n\t\t\t__u32 bit7: 1;\n\t\t\t__u32 bit6: 1;\n\t\t\t__u32 bit5: 1;\n\t\t\t__u32 bit4: 1;\n\t\t\t__u32 bit3: 1;\n\t\t\t__u32 bit2: 1;\n\t\t\t__u32 bit1: 1;\n\t\t\t__u32 bit0: 1;\n\t\t\t__u32 bit15: 1;\n\t\t\t__u32 bit14: 1;\n\t\t\t__u32 bit13: 1;\n\t\t\t__u32 bit12: 1;\n\t\t\t__u32 bit11: 1;\n\t\t\t__u32 bit10: 1;\n\t\t\t__u32 bit9: 1;\n\t\t\t__u32 bit8: 1;\n\t\t\t__u32 bit23: 1;\n\t\t\t__u32 bit22: 1;\n\t\t\t__u32 bit21: 1;\n\t\t\t__u32 bit20: 1;\n\t\t\t__u32 bit19: 1;\n\t\t\t__u32 bit18: 1;\n\t\t\t__u32 bit17: 1;\n\t\t\t__u32 bit16: 1;\n\t\t} type;\n\t};\n\t__u8 data[0];\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tstruct bio io_bio;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n};\n\nstruct iommu_domain;\n\nstruct iommu_attach_handle {\n\tstruct iommu_domain *domain;\n};\n\nstruct iommu_ops;\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n\tstruct iommu_group *singleton_group;\n\tu32 max_pasids;\n\tbool ready;\n};\n\nstruct iova_bitmap;\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_dirty_bitmap {\n\tstruct iova_bitmap *bitmap;\n\tstruct iommu_iotlb_gather *gather;\n};\n\nstruct iommu_dirty_ops {\n\tint (*set_dirty_tracking)(struct iommu_domain *, bool);\n\tint (*read_and_clear_dirty)(struct iommu_domain *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommu_dma_cookie;\n\nstruct iommu_dma_msi_cookie;\n\nstruct iommufd_hw_pagetable;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_ops;\n\nstruct iopf_group;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct iommu_user_data_array;\n\nstruct iommu_domain_ops {\n\tint (*attach_dev)(struct iommu_domain *, struct device *, struct iommu_domain *);\n\tint (*set_dev_pasid)(struct iommu_domain *, struct device *, ioasid_t, struct iommu_domain *);\n\tint (*map_pages)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct iommu_domain *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tint (*iotlb_sync_map)(struct iommu_domain *, long unsigned int, size_t);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tint (*cache_invalidate_user)(struct iommu_domain *, struct iommu_user_data_array *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tbool (*enforce_cache_coherency)(struct iommu_domain *);\n\tint (*set_pgtable_quirks)(struct iommu_domain *, long unsigned int);\n\tvoid (*free)(struct iommu_domain *);\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iopf_queue;\n\nstruct iommu_fault_param {\n\tstruct mutex lock;\n\trefcount_t users;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n\tstruct iopf_queue *queue;\n\tstruct list_head queue_list;\n\tstruct list_head partial;\n\tstruct list_head faults;\n};\n\nstruct iommu_fwspec {\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct xarray pasid_array;\n\tstruct mutex mutex;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *blocking_domain;\n\tstruct iommu_domain *resetting_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n\tunsigned int owner_cnt;\n\tvoid *owner;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct iommu_pages_list {\n\tstruct list_head pages;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n\tstruct iommu_pages_list freelist;\n\tbool queued;\n};\n\nstruct iommu_user_data;\n\nstruct iopf_fault;\n\nstruct iommu_page_response;\n\nstruct iommufd_viommu;\n\nstruct iommu_ops {\n\tbool (*capable)(struct device *, enum iommu_cap);\n\tvoid * (*hw_info)(struct device *, u32 *, enum iommu_hw_info_type *);\n\tstruct iommu_domain * (*domain_alloc_identity)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_paging_flags)(struct device *, u32, const struct iommu_user_data *);\n\tstruct iommu_domain * (*domain_alloc_paging)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_sva)(struct device *, struct mm_struct *);\n\tstruct iommu_domain * (*domain_alloc_nested)(struct device *, struct iommu_domain *, u32, const struct iommu_user_data *);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tint (*of_xlate)(struct device *, const struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct device *);\n\tvoid (*page_response)(struct device *, struct iopf_fault *, struct iommu_page_response *);\n\tint (*def_domain_type)(struct device *);\n\tsize_t (*get_viommu_size)(struct device *, enum iommu_viommu_type);\n\tint (*viommu_init)(struct iommufd_viommu *, struct iommu_domain *, const struct iommu_user_data *);\n\tconst struct iommu_domain_ops *default_domain_ops;\n\tstruct module *owner;\n\tstruct iommu_domain *identity_domain;\n\tstruct iommu_domain *blocked_domain;\n\tstruct iommu_domain *release_domain;\n\tstruct iommu_domain *default_domain;\n\tu8 user_pasid_table: 1;\n};\n\nstruct iommu_page_response {\n\tu32 pasid;\n\tu32 grpid;\n\tu32 code;\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n\tvoid (*free)(struct device *, struct iommu_resv_region *);\n};\n\nstruct iommu_user_data {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t len;\n};\n\nstruct iommu_user_data_array {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t entry_len;\n\tu32 entry_num;\n};\n\nstruct iommufd_object {\n\trefcount_t wait_cnt;\n\trefcount_t users;\n\tenum iommufd_object_type type;\n\tunsigned int id;\n};\n\nstruct iommufd_access;\n\nstruct iommufd_hw_queue {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_access *access;\n\tu64 base_addr;\n\tsize_t length;\n\tenum iommu_hw_queue_type type;\n\tvoid (*destroy)(struct iommufd_hw_queue *);\n};\n\nstruct iommufd_device;\n\nstruct iommufd_vdevice {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_device *idev;\n\tu64 virt_id;\n\tvoid (*destroy)(struct iommufd_vdevice *);\n};\n\nstruct iommufd_ctx;\n\nstruct iommufd_hwpt_paging;\n\nstruct iommufd_viommu_ops;\n\nstruct iommufd_viommu {\n\tstruct iommufd_object obj;\n\tstruct iommufd_ctx *ictx;\n\tstruct iommu_device *iommu_dev;\n\tstruct iommufd_hwpt_paging *hwpt;\n\tconst struct iommufd_viommu_ops *ops;\n\tstruct xarray vdevs;\n\tstruct list_head veventqs;\n\tstruct rw_semaphore veventqs_rwsem;\n\tenum iommu_viommu_type type;\n};\n\nstruct iommufd_viommu_ops {\n\tvoid (*destroy)(struct iommufd_viommu *);\n\tstruct iommu_domain * (*alloc_domain_nested)(struct iommufd_viommu *, u32, const struct iommu_user_data *);\n\tint (*cache_invalidate)(struct iommufd_viommu *, struct iommu_user_data_array *);\n\tconst size_t vdevice_size;\n\tint (*vdevice_init)(struct iommufd_vdevice *);\n\tsize_t (*get_hw_queue_size)(struct iommufd_viommu *, enum iommu_hw_queue_type);\n\tint (*hw_queue_init_phys)(struct iommufd_hw_queue *, u32, phys_addr_t);\n};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct iopf_queue {\n\tstruct workqueue_struct *wq;\n\tstruct list_head devices;\n\tstruct mutex lock;\n};\n\nstruct ioptdesc {\n\tlong unsigned int __page_flags;\n\tstruct list_head iopt_freelist_elm;\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tu8 incoherent;\n\t\tlong unsigned int __index;\n\t};\n\tvoid *_private;\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct ip6_frag_state {\n\tu8 *prevhdr;\n\tunsigned int hlen;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\tint hroom;\n\tint troom;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ipv6hdr;\n\nstruct ip6_fraglist_iter {\n\tstruct ipv6hdr *tmp_hdr;\n\tstruct sk_buff *frag;\n\tint offset;\n\tunsigned int hlen;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct ip6_mtuinfo {\n\tstruct sockaddr_in6 ip6m_addr;\n\t__u32 ip6m_mtu;\n};\n\nstruct ip6_ra_chain {\n\tstruct ip6_ra_chain *next;\n\tstruct sock *sk;\n\tint sel;\n\tvoid (*destructor)(struct sock *);\n};\n\nstruct ip6_rt_info {\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\tu_int32_t mark;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip6_tnl {\n\tstruct ip6_tnl *next;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tstruct __ip6_tnl_parm parms;\n\tstruct flowi fl;\n\tstruct dst_cache dst_cache;\n\tstruct gro_cells gro_cells;\n\tint err_count;\n\tlong unsigned int err_time;\n\t__u32 i_seqno;\n\tatomic_t o_seqno;\n\tint hlen;\n\tint tun_hlen;\n\tint encap_hlen;\n\tstruct ip_tunnel_encap encap;\n\tint mlink;\n};\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip6addrlbl_entry {\n\tstruct in6_addr prefix;\n\tint prefixlen;\n\tint ifindex;\n\tint addrtype;\n\tu32 label;\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n};\n\nstruct ip6addrlbl_init_table {\n\tconst struct in6_addr *prefix;\n\tint prefixlen;\n\tu32 label;\n};\n\nstruct ip6fl_iter_state {\n\tstruct seq_net_private p;\n\tstruct pid_namespace *pid_ns;\n\tint bucket;\n};\n\nstruct ip6rd_flowi {\n\tstruct flowi6 fl6;\n\tstruct in6_addr gateway;\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_beet_phdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 padlen;\n\t__u8 reserved;\n};\n\nstruct ip_conntrack_stat {\n\tunsigned int found;\n\tunsigned int invalid;\n\tunsigned int insert;\n\tunsigned int insert_failed;\n\tunsigned int clash_resolve;\n\tunsigned int drop;\n\tunsigned int early_drop;\n\tunsigned int error;\n\tunsigned int expect_new;\n\tunsigned int expect_create;\n\tunsigned int expect_delete;\n\tunsigned int search_restart;\n\tunsigned int chaintoolong;\n};\n\nstruct ip_ct_sctp {\n\tenum sctp_conntrack state;\n\t__be32 vtag[2];\n\tu8 init[2];\n\tu8 last_dir;\n\tu8 flags;\n};\n\nstruct ip_ct_tcp_state {\n\tu_int32_t td_end;\n\tu_int32_t td_maxend;\n\tu_int32_t td_maxwin;\n\tu_int32_t td_maxack;\n\tu_int8_t td_scale;\n\tu_int8_t flags;\n};\n\nstruct ip_ct_tcp {\n\tstruct ip_ct_tcp_state seen[2];\n\tu_int8_t state;\n\tu_int8_t last_dir;\n\tu_int8_t retrans;\n\tu_int8_t last_index;\n\tu_int32_t last_seq;\n\tu_int32_t last_ack;\n\tu_int32_t last_end;\n\tu_int16_t last_win;\n\tu_int8_t last_wscale;\n\tu_int8_t last_flags;\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct unix_domain;\n\nstruct ip_map {\n\tstruct cache_head h;\n\tchar m_class[8];\n\tstruct in6_addr m_addr;\n\tstruct unix_domain *m_client;\n\tstruct callback_head m_rcu;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_rt_info {\n\t__be32 daddr;\n\t__be32 saddr;\n\tu_int8_t tos;\n\tu_int32_t mark;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl_entry;\n\nstruct ip_tunnel {\n\tstruct ip_tunnel *next;\n\tstruct hlist_node hash_node;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tlong unsigned int err_time;\n\tint err_count;\n\tu32 i_seqno;\n\tatomic_t o_seqno;\n\tint tun_hlen;\n\tu32 index;\n\tu8 erspan_ver;\n\tu8 dir;\n\tu16 hwid;\n\tstruct dst_cache dst_cache;\n\tstruct ip_tunnel_parm_kern parms;\n\tint mlink;\n\tint encap_hlen;\n\tint hlen;\n\tstruct ip_tunnel_encap encap;\n\tstruct ip_tunnel_prl_entry *prl;\n\tunsigned int prl_count;\n\tunsigned int ip_tnl_net_id;\n\tstruct gro_cells gro_cells;\n\t__u32 fwmark;\n\tbool collect_md;\n\tbool ignore_df;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 0;\n\tu8 options[0];\n};\n\nstruct rtnl_link_ops;\n\nstruct ip_tunnel_net {\n\tstruct net_device *fb_tunnel_dev;\n\tstruct rtnl_link_ops *rtnl_link_ops;\n\tstruct hlist_head tunnels[128];\n\tstruct ip_tunnel *collect_md_tun;\n\tint type;\n};\n\nstruct ip_tunnel_parm {\n\tchar name[16];\n\tint link;\n\t__be16 i_flags;\n\t__be16 o_flags;\n\t__be32 i_key;\n\t__be32 o_key;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl {\n\t__be32 addr;\n\t__u16 flags;\n\t__u16 __reserved;\n\t__u32 datalen;\n\t__u32 __reserved2;\n};\n\nstruct ip_tunnel_prl_entry {\n\tstruct ip_tunnel_prl_entry *next;\n\t__be32 addr;\n\tu16 flags;\n\tstruct callback_head callback_head;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned char __pad1[0];\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\t__kernel_ulong_t __unused1;\n\t__kernel_ulong_t __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tint next_id;\n\tstruct rhashtable key_ht;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct ipc_security_struct {\n\tu16 sclass;\n\tu32 sid;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n};\n\nstruct ipcm6_cookie {\n\tstruct sockcm_cookie sockc;\n\t__s16 hlimit;\n\t__s16 tclass;\n\t__u16 gso_size;\n\t__s8 dontfrag;\n\tstruct ipv6_txoptions *opt;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipi_mux_cpu {\n\tatomic_t enable;\n\tatomic_t bits;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mreq {\n\tstruct in6_addr ipv6mr_multiaddr;\n\tint ipv6mr_ifindex;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_params {\n\t__s32 disable_ipv6;\n\t__s32 autoconf;\n};\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib6_walker w;\n\tloff_t skip;\n\tstruct fib6_table *tbl;\n\tint sernum;\n};\n\nstruct ipv6_rpl_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u32 cmpre: 4;\n\t__u32 cmpri: 4;\n\t__u32 reserved: 4;\n\t__u32 pad: 4;\n\t__u32 reserved1: 16;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_addr;\n\t\t\tstruct in6_addr addr[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\t__u8 data[0];\n\t\t};\n\t} segments;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct ipv6_saddr_dst {\n\tconst struct in6_addr *addr;\n\tint ifindex;\n\tint scope;\n\tint label;\n\tunsigned int prefs;\n};\n\nstruct ipv6_saddr_score {\n\tint rule;\n\tint addr_type;\n\tstruct inet6_ifaddr *ifa;\n\tlong unsigned int scorebits[1];\n\tint scopedist;\n\tint matchlen;\n};\n\nstruct ipv6_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u8 first_segment;\n\t__u8 flags;\n\t__u16 tag;\n\tstruct in6_addr segments[0];\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tvoid (*xfrm6_local_rxpmtu)(struct sk_buff *, u32);\n\tint (*xfrm6_udp_encap_rcv)(struct sock *, struct sk_buff *);\n\tstruct sk_buff * (*xfrm6_gro_udp_encap_rcv)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*xfrm6_rcv_encap)(struct sk_buff *, int, __be32, int);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tunsigned int node;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n\tcpumask_var_t effective_affinity;\n\tunsigned int ipi_offset;\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tcpumask_var_t pending_mask;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct hlist_node resend_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_info {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\nstruct irq_matrix {\n\tunsigned int matrix_bits;\n\tunsigned int alloc_start;\n\tunsigned int alloc_end;\n\tunsigned int alloc_size;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int systembits_inalloc;\n\tunsigned int total_allocated;\n\tunsigned int online_maps;\n\tstruct cpumap *maps;\n\tlong unsigned int *system_map;\n\tlong unsigned int scratch_map[0];\n};\n\nstruct irq_override_cmp {\n\tconst struct dmi_system_id *system;\n\tunsigned char irq;\n\tunsigned char triggering;\n\tunsigned char polarity;\n\tunsigned char shareable;\n\tbool override;\n};\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqentry_state {\n\tunion {\n\t\tbool exit_rcu;\n\t\tbool lockdep;\n\t};\n};\n\ntypedef struct irqentry_state irqentry_state_t;\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct iso_directory_record {\n\t__u8 length[1];\n\t__u8 ext_attr_length[1];\n\t__u8 extent[8];\n\t__u8 size[8];\n\t__u8 date[7];\n\t__u8 flags[1];\n\t__u8 file_unit_size[1];\n\t__u8 interleave[1];\n\t__u8 volume_sequence_number[4];\n\t__u8 name_len[1];\n\tchar name[0];\n};\n\nstruct iso_inode_info {\n\tlong unsigned int i_iget5_block;\n\tlong unsigned int i_iget5_offset;\n\tunsigned int i_first_extent;\n\tunsigned char i_file_format;\n\tunsigned char i_format_parm[3];\n\tlong unsigned int i_next_section_block;\n\tlong unsigned int i_next_section_offset;\n\toff_t i_section_size;\n\tstruct inode vfs_inode;\n};\n\nstruct iso_primary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_supplementary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 flags[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 escape[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_volume_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2041];\n};\n\nstruct isofs_fid {\n\tu32 block;\n\tu16 offset;\n\tu16 parent_offset;\n\tu32 generation;\n\tu32 parent_block;\n\tu32 parent_generation;\n};\n\nstruct isofs_iget5_callback_data {\n\tlong unsigned int block;\n\tlong unsigned int offset;\n};\n\nstruct isofs_options {\n\tunsigned int rock: 1;\n\tunsigned int joliet: 1;\n\tunsigned int cruft: 1;\n\tunsigned int hide: 1;\n\tunsigned int showassoc: 1;\n\tunsigned int nocompress: 1;\n\tunsigned int overriderockperm: 1;\n\tunsigned int uid_set: 1;\n\tunsigned int gid_set: 1;\n\tunsigned char map;\n\tunsigned char check;\n\tunsigned int blocksize;\n\tumode_t fmode;\n\tumode_t dmode;\n\tkgid_t gid;\n\tkuid_t uid;\n\tchar *iocharset;\n\ts32 session;\n\ts32 sbsector;\n};\n\nstruct nls_table;\n\nstruct isofs_sb_info {\n\tlong unsigned int s_ninodes;\n\tlong unsigned int s_nzones;\n\tlong unsigned int s_firstdatazone;\n\tlong unsigned int s_log_zone_size;\n\tlong unsigned int s_max_size;\n\tint s_rock_offset;\n\ts32 s_sbsector;\n\tunsigned char s_joliet_level;\n\tunsigned char s_mapping;\n\tunsigned char s_check;\n\tunsigned char s_session;\n\tunsigned int s_high_sierra: 1;\n\tunsigned int s_rock: 2;\n\tunsigned int s_cruft: 1;\n\tunsigned int s_nocompress: 1;\n\tunsigned int s_hide: 1;\n\tunsigned int s_showassoc: 1;\n\tunsigned int s_overriderockperm: 1;\n\tunsigned int s_uid_set: 1;\n\tunsigned int s_gid_set: 1;\n\tumode_t s_fmode;\n\tumode_t s_dmode;\n\tkgid_t s_gid;\n\tkuid_t s_uid;\n\tstruct nls_table *s_nls_iocharset;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct iu {\n\t__u8 iu_id;\n\t__u8 rsvd1;\n\t__be16 tag;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct iw_node_attr {\n\tstruct kobj_attribute kobj_attr;\n\tint nid;\n};\n\nstruct snd_soc_jack;\n\nstruct snd_soc_jack_gpio;\n\nstruct jack_gpio_tbl {\n\tint count;\n\tstruct snd_soc_jack *jack;\n\tstruct snd_soc_jack_gpio *gpios;\n};\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_s journal_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong long unsigned int blocknr;\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct transaction_stats_s;\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct jh7110_func_sel {\n\tu16 offset;\n\tu8 shift;\n\tu8 max;\n};\n\nstruct jh7110_gpio_irq_reg {\n\tunsigned int is_reg_base;\n\tunsigned int ic_reg_base;\n\tunsigned int ibe_reg_base;\n\tunsigned int iev_reg_base;\n\tunsigned int ie_reg_base;\n\tunsigned int ris_reg_base;\n\tunsigned int mis_reg_base;\n};\n\nstruct jh7110_pinctrl_soc_info;\n\nstruct jh7110_pinctrl {\n\tstruct device *dev;\n\tstruct gpio_chip gc;\n\tstruct pinctrl_gpio_range gpios;\n\traw_spinlock_t lock;\n\tvoid *base;\n\tstruct pinctrl_dev *pctl;\n\tstruct mutex mutex;\n\tconst struct jh7110_pinctrl_soc_info *info;\n\tu32 *saved_regs;\n};\n\nstruct pinctrl_pin_desc;\n\nstruct jh7110_pinctrl_soc_info {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tunsigned int ngpios;\n\tunsigned int dout_reg_base;\n\tunsigned int dout_mask;\n\tunsigned int doen_reg_base;\n\tunsigned int doen_mask;\n\tunsigned int gpi_reg_base;\n\tunsigned int gpi_mask;\n\tunsigned int gpioin_reg_base;\n\tconst struct jh7110_gpio_irq_reg *irq_reg;\n\tunsigned int nsaved_regs;\n\tint (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *, unsigned int, unsigned int, u32, u32, u32);\n\tint (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *, unsigned int);\n\tvoid (*jh7110_gpio_irq_handler)(struct irq_desc *);\n\tint (*jh7110_gpio_init_hw)(struct gpio_chip *);\n};\n\nstruct jh7110_pll_data {\n\tstruct clk_hw hw;\n\tunsigned int idx;\n};\n\nstruct jh7110_pll_preset;\n\nstruct jh7110_pll_info {\n\tchar *name;\n\tconst struct jh7110_pll_preset *presets;\n\tunsigned int npresets;\n\tstruct {\n\t\tunsigned int pd;\n\t\tunsigned int fbdiv;\n\t\tunsigned int frac;\n\t\tunsigned int prediv;\n\t} offsets;\n\tstruct {\n\t\tu32 dacpd;\n\t\tu32 dsmpd;\n\t\tu32 fbdiv;\n\t} masks;\n\tstruct {\n\t\tchar dacpd;\n\t\tchar dsmpd;\n\t\tchar fbdiv;\n\t} shifts;\n};\n\nstruct jh7110_pll_preset {\n\tlong unsigned int freq;\n\tu32 frac;\n\tunsigned int fbdiv: 12;\n\tunsigned int prediv: 6;\n\tunsigned int postdiv1: 2;\n\tunsigned int mode: 1;\n};\n\nstruct jh7110_pll_priv {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct jh7110_pll_data pll[3];\n};\n\nstruct jh7110_pll_regvals {\n\tu32 dacpd;\n\tu32 dsmpd;\n\tu32 fbdiv;\n\tu32 frac;\n\tu32 postdiv1;\n\tu32 prediv;\n};\n\nstruct jh7110_reset_info {\n\tunsigned int nr_resets;\n\tunsigned int assert_offset;\n\tunsigned int status_offset;\n};\n\nstruct jh7110_vin_group_sel {\n\tu16 offset;\n\tu8 shift;\n\tu8 group;\n};\n\nstruct jh71x0_clk {\n\tstruct clk_hw hw;\n\tunsigned int idx;\n\tunsigned int max_div;\n};\n\nstruct jh71x0_clk_data {\n\tconst char *name;\n\tlong unsigned int flags;\n\tu32 max;\n\tu8 parents[4];\n};\n\nstruct jh71x0_clk_priv {\n\tspinlock_t rmw_lock;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *original_clk;\n\tstruct notifier_block pll_clk_nb;\n\tstruct clk_hw *pll[3];\n\tunsigned int num_reg;\n\tstruct jh71x0_clk reg[0];\n};\n\nstruct jh71x0_reset {\n\tstruct reset_controller_dev rcdev;\n\tspinlock_t lock;\n\tvoid *assert;\n\tvoid *status;\n\tconst u32 *asserted;\n};\n\nstruct jh71x0_reset_adev {\n\tvoid *base;\n\tstruct auxiliary_device adev;\n};\n\nstruct jh71xx_domain_info {\n\tconst char * const name;\n\tunsigned int flags;\n\tu8 bit;\n};\n\nstruct jh71xx_pmu_match_data;\n\nstruct jh71xx_pmu {\n\tstruct device *dev;\n\tconst struct jh71xx_pmu_match_data *match_data;\n\tvoid *base;\n\tstruct generic_pm_domain **genpd;\n\tstruct genpd_onecell_data genpd_data;\n\tint irq;\n\tspinlock_t lock;\n};\n\nstruct jh71xx_pmu_dev {\n\tconst struct jh71xx_domain_info *domain_info;\n\tstruct jh71xx_pmu *pmu;\n\tstruct generic_pm_domain genpd;\n};\n\nstruct jh71xx_pmu_match_data {\n\tconst struct jh71xx_domain_info *domain_info;\n\tint num_domains;\n\tunsigned int pmu_status;\n\tint (*pmu_parse_irq)(struct platform_device *, struct jh71xx_pmu *);\n\tint (*pmu_set_state)(struct jh71xx_pmu_dev *, u32, bool);\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\twait_queue_head_t j_fc_wait;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tstruct shrinker *j_shrinker;\n\tstruct percpu_counter j_checkpoint_jh_count;\n\ttransaction_t *j_shrink_transaction;\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tlong unsigned int j_fc_first;\n\tlong unsigned int j_fc_off;\n\tlong unsigned int j_fc_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\terrseq_t j_fs_dev_wb_err;\n\tunsigned int j_total_len;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tint j_transaction_overhead_buffers;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tstruct buffer_head **j_fc_wbuf;\n\tint j_wbufsize;\n\tint j_fc_wbufsize;\n\tpid_t j_last_sync_writer;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tint (*j_submit_inode_data_buffers)(struct jbd2_inode *);\n\tint (*j_finish_inode_data_buffers)(struct jbd2_inode *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\t__u32 j_csum_seed;\n\tstruct lock_class_key jbd2_trans_commit_key;\n\tvoid (*j_fc_cleanup_callback)(struct journal_s *, int, tid_t);\n\tint (*j_fc_replay_callback)(struct journal_s *, struct buffer_head *, enum passtype, int, tid_t);\n\tint (*j_bmap)(struct journal_s *, sector_t *);\n};\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__be32 s_num_fc_blks;\n\t__be32 s_head;\n\t__u32 s_padding[40];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nstruct jump_entry {\n\ts32 code;\n\ts32 target;\n\tlong int key;\n};\n\nstruct k1_pcie {\n\tstruct dw_pcie pci;\n\tstruct phy *phy;\n\tvoid *link;\n\tstruct regmap *pmu;\n\tu32 pmu_off;\n};\n\nstruct k1_pcie_phy {\n\tstruct device *dev;\n\tstruct phy *phy;\n\tvoid *regs;\n\tu32 pcie_lanes;\n\tstruct clk *pll;\n\tstruct clk_hw pll_hw;\n\tu32 type;\n\tstruct regmap *pmu;\n};\n\nstruct k230_rst {\n\tstruct reset_controller_dev rcdev;\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct k230_rst_map {\n\tu32 offset;\n\tenum k230_rst_type type;\n\tu32 done;\n\tu32 reset;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[56];\n\tint exported;\n\tint show_value;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tint: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcmp_epoll_slot {\n\t__u32 efd;\n\t__u32 tfd;\n\t__u32 toff;\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[10];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_mapping {\n\tlong unsigned int virt_addr;\n\tlong unsigned int virt_offset;\n\tuintptr_t phys_addr;\n\tuintptr_t size;\n\tlong unsigned int va_pa_offset;\n\tlong unsigned int page_offset;\n\tlong unsigned int va_kernel_pa_offset;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tlong unsigned int value;\n\tconst char *name;\n\tconst char *namespace;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[1024];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct vm_operations_struct;\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[6];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_security_struct {\n\tu32 sid;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\ttime64_t now;\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct km_event {\n\tunion {\n\t\tu32 hard;\n\t\tu32 proto;\n\t\tu32 byid;\n\t\tu32 aevent;\n\t\tu32 type;\n\t} data;\n\tu32 seq;\n\tu32 portid;\n\tu32 event;\n\tstruct net *net;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[3];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {};\n\ntypedef struct kmem_cache *kmem_buckets[14];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tunsigned int remote_node_defrag_ratio;\n\tstruct kmem_cache_node *node[4];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kprobe;\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ksz9477_errata_write {\n\tu8 dev_addr;\n\tu8 reg_addr;\n\tu16 val;\n};\n\nstruct kszphy_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct kszphy_phy_stats {\n\tu64 rx_err_pkt_cnt;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct kszphy_ptp_priv {\n\tstruct mii_timestamper mii_ts;\n\tstruct phy_device *phydev;\n\tstruct sk_buff_head tx_queue;\n\tstruct sk_buff_head rx_queue;\n\tstruct list_head rx_ts_list;\n\tspinlock_t rx_ts_lock;\n\tint hwts_tx_type;\n\tenum hwtstamp_rx_filters rx_filter;\n\tint layer;\n\tint version;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct mutex ptp_lock;\n\tstruct ptp_pin_desc *pin_config;\n\ts64 seconds;\n\tspinlock_t seconds_lock;\n};\n\nstruct kszphy_type;\n\nstruct kszphy_priv {\n\tstruct kszphy_ptp_priv ptp_priv;\n\tconst struct kszphy_type *type;\n\tstruct clk *clk;\n\tint led_mode;\n\tu16 vct_ctrl1000;\n\tbool rmii_ref_clk_sel;\n\tbool rmii_ref_clk_sel_val;\n\tbool clk_enable;\n\tbool is_ptp_available;\n\tu64 stats[2];\n\tstruct kszphy_phy_stats phy_stats;\n};\n\nstruct kszphy_type {\n\tu32 led_mode_reg;\n\tu16 interrupt_level_mask;\n\tu16 cable_diag_reg;\n\tlong unsigned int pair_mask;\n\tu16 disable_dll_tx_bit;\n\tu16 disable_dll_rx_bit;\n\tu16 disable_dll_mask;\n\tbool has_broadcast_disable;\n\tbool has_nand_tree_disable;\n\tbool has_rmii_ref_clk_sel;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_worker;\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\ntypedef int (*lookup_by_table_id_t)(struct net *, u32);\n\nstruct l3mdev_handler {\n\tlookup_by_table_id_t dev_lookup;\n};\n\nstruct l3mdev_ops {\n\tu32 (*l3mdev_fib_table)(const struct net_device *);\n\tstruct sk_buff * (*l3mdev_l3_rcv)(struct net_device *, struct sk_buff *, u16);\n\tstruct sk_buff * (*l3mdev_l3_out)(struct net_device *, struct sock *, struct sk_buff *, u16);\n\tstruct dst_entry * (*l3mdev_link_scope_lookup)(const struct net_device *, struct flowi6 *);\n};\n\nstruct label_it {\n\tint i;\n\tint j;\n};\n\nstruct lan8814_ptp_rx_ts {\n\tstruct list_head list;\n\tu32 seconds;\n\tu32 nsec;\n\tu16 seq_id;\n};\n\nstruct lan8814_shared_priv {\n\tstruct phy_device *phydev;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct ptp_pin_desc *pin_config;\n\tstruct mutex shared_lock;\n};\n\nstruct lan8842_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_errors;\n};\n\nstruct lan8842_priv {\n\tstruct lan8842_phy_stats phy_stats;\n\tstruct kszphy_ptp_priv ptp_priv;\n\tu16 rev;\n};\n\nstruct lanphy_reg_data {\n\tint page;\n\tu16 addr;\n\tu16 val;\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tu64 val[2];\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct lcd_properties {\n\tint max_contrast;\n};\n\nstruct lcd_ops;\n\nstruct lcd_device {\n\tstruct lcd_properties props;\n\tstruct mutex ops_lock;\n\tconst struct lcd_ops *ops;\n\tstruct mutex update_lock;\n\tstruct list_head entry;\n\tstruct device dev;\n};\n\nstruct lcd_ops {\n\tint (*get_power)(struct lcd_device *);\n\tint (*set_power)(struct lcd_device *, int);\n\tint (*get_contrast)(struct lcd_device *);\n\tint (*set_contrast)(struct lcd_device *, int);\n\tint (*set_mode)(struct lcd_device *, u32, u32);\n\tbool (*controls_device)(struct lcd_device *, struct device *);\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct led_trigger {};\n\nstruct level_datum {\n\tstruct mls_level level;\n\tunsigned char isalias;\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linereq;\n\nstruct line {\n\tstruct gpio_desc *desc;\n\tstruct linereq *req;\n\tunsigned int irq;\n\tu64 edflags;\n\tu64 timestamp_ns;\n\tu32 req_seqno;\n\tu32 line_seqno;\n\tstruct delayed_work work;\n\tunsigned int sw_debounced;\n\tunsigned int level;\n};\n\nstruct linear_range {\n\tunsigned int min;\n\tunsigned int min_sel;\n\tunsigned int max_sel;\n\tunsigned int step;\n};\n\nstruct lineevent_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *desc;\n\tu32 eflags;\n\tint irq;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpioevent_data *type;\n\t\t\tconst struct gpioevent_data *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpioevent_data *ptr;\n\t\t\tconst struct gpioevent_data *ptr_const;\n\t\t};\n\t\tstruct gpioevent_data buf[16];\n\t} events;\n\tu64 timestamp;\n};\n\nstruct linehandle_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *descs[64];\n\tu32 num_descs;\n};\n\nstruct lineinfo_changed_ctx {\n\tstruct work_struct work;\n\tstruct gpio_v2_line_info_changed chg;\n\tstruct gpio_device *gdev;\n\tstruct gpio_chardev_data *cdev;\n};\n\nstruct linereq {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tu32 num_lines;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tu32 event_buffer_size;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_event *type;\n\t\t\tconst struct gpio_v2_line_event *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_event *ptr;\n\t\t\tconst struct gpio_v2_line_event *ptr_const;\n\t\t};\n\t\tstruct gpio_v2_line_event buf[0];\n\t} events;\n\tatomic_t seqno;\n\tstruct mutex config_mutex;\n\tstruct line lines[0];\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_capabilities {\n\tint speed;\n\tunsigned int duplex;\n\tlong unsigned int linkmodes[2];\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n};\n\nstruct linux_efi_initrd {\n\tlong unsigned int base;\n\tlong unsigned int size;\n};\n\nstruct linux_efi_memreserve {\n\tint size;\n\tatomic_t count;\n\tphys_addr_t next;\n\tstruct {\n\t\tphys_addr_t base;\n\t\tphys_addr_t size;\n\t} entry[0];\n};\n\nstruct linux_efi_random_seed {\n\tu32 size;\n\tu8 bits[0];\n};\n\nstruct linux_efi_tpm_eventlog {\n\tu32 size;\n\tu32 final_events_preboot_size;\n\tu8 version;\n\tu8 log[0];\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n\tstruct list_head list;\n\tint shrinker_id;\n\tbool memcg_aware;\n\tstruct xarray xa;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_memcg {\n\tstruct callback_head rcu;\n\tstruct list_lru_one node[0];\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf64_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct location;\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n\tloff_t idx;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct location {\n\tdepot_stack_handle_t handle;\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong unsigned int waste;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[1];\n\tnodemask_t nodes;\n};\n\nstruct lock_manager {\n\tstruct list_head list;\n\tbool block_opens;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct lockd_net {\n\tunsigned int nlmsvc_users;\n\tlong unsigned int next_gc;\n\tlong unsigned int nrhosts;\n\tu32 gracetime;\n\tu16 tcp_port;\n\tu16 udp_port;\n\tstruct delayed_work grace_period_end;\n\tstruct lock_manager lockd_manager;\n\tstruct list_head nsm_handles;\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tloff_t li_pos;\n};\n\nstruct log_entry {\n\t__le32 lba;\n\t__le32 old_map;\n\t__le32 new_map;\n\t__le32 seq;\n};\n\nstruct log_group {\n\tstruct log_entry ent[4];\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct lookup_args {\n\tint offset;\n\tconst struct in6_addr *addr;\n};\n\nstruct loop_cmd {\n\tstruct list_head list_entry;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct cgroup_subsys_state *memcg_css;\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nstruct loop_device {\n\tint lo_number;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tchar lo_file_name[64];\n\tstruct file *lo_backing_file;\n\tunsigned int lo_min_dio_size;\n\tstruct block_device *lo_device;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tspinlock_t lo_work_lock;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rootcg_work;\n\tstruct list_head rootcg_cmd_list;\n\tstruct list_head idle_worker_list;\n\tstruct rb_root worker_tree;\n\tstruct timer_list timer;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n\tstruct mutex lo_mutex;\n\tbool idr_visible;\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_worker {\n\tstruct rb_node rb_node;\n\tstruct work_struct work;\n\tstruct list_head cmd_list;\n\tstruct list_head idle_list;\n\tstruct loop_device *lo;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tlong unsigned int last_ran_at;\n};\n\nunion lower_chunk {\n\tunion lower_chunk *next;\n\tlong unsigned int data[256];\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct zswap_lruvec_state {};\n\nstruct pglist_data;\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct pglist_data *pgdat;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct lruvec_stats {\n\tlong int state[33];\n\tlong int state_local[33];\n\tlong int state_pending[33];\n};\n\nstruct lruvec_stats_percpu {\n\tlong int state[33];\n\tlong int state_prev[33];\n};\n\nstruct lsm_blob_sizes {\n\tunsigned int lbs_cred;\n\tunsigned int lbs_file;\n\tunsigned int lbs_ib;\n\tunsigned int lbs_inode;\n\tunsigned int lbs_sock;\n\tunsigned int lbs_superblock;\n\tunsigned int lbs_ipc;\n\tunsigned int lbs_key;\n\tunsigned int lbs_msg_msg;\n\tunsigned int lbs_perf_event;\n\tunsigned int lbs_task;\n\tunsigned int lbs_xattr_count;\n\tunsigned int lbs_tun_dev;\n\tunsigned int lbs_bdev;\n\tunsigned int lbs_bpf_map;\n\tunsigned int lbs_bpf_prog;\n\tunsigned int lbs_bpf_token;\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct lsm_ctx {\n\t__u64 id;\n\t__u64 flags;\n\t__u64 len;\n\t__u64 ctx_len;\n\t__u8 ctx[0];\n};\n\nstruct lsm_ibendport_audit {\n\tconst char *dev_name;\n\tu8 port;\n};\n\nstruct lsm_ibpkey_audit {\n\tu64 subnet_prefix;\n\tu16 pkey;\n};\n\nstruct lsm_id {\n\tconst char *name;\n\tu64 id;\n};\n\nstruct lsm_info {\n\tconst struct lsm_id *id;\n\tenum lsm_order order;\n\tlong unsigned int flags;\n\tstruct lsm_blob_sizes *blobs;\n\tint *enabled;\n\tint (*init)(void);\n\tint (*initcall_pure)(void);\n\tint (*initcall_early)(void);\n\tint (*initcall_core)(void);\n\tint (*initcall_subsys)(void);\n\tint (*initcall_fs)(void);\n\tint (*initcall_device)(void);\n\tint (*initcall_late)(void);\n};\n\nstruct lsm_ioctlop_audit {\n\tstruct path path;\n\tu16 cmd;\n};\n\nstruct lsm_network_audit {\n\tint netif;\n\tconst struct sock *sk;\n\tu16 family;\n\t__be16 dport;\n\t__be16 sport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 daddr;\n\t\t\t__be32 saddr;\n\t\t} v4;\n\t\tstruct {\n\t\t\tstruct in6_addr daddr;\n\t\t\tstruct in6_addr saddr;\n\t\t} v6;\n\t} fam;\n};\n\nstruct static_call_key;\n\nstruct security_hook_list;\n\nstruct static_key_false;\n\nstruct lsm_static_call {\n\tstruct static_call_key *key;\n\tvoid *trampoline;\n\tstruct security_hook_list *hl;\n\tstruct static_key_false *active;\n};\n\nstruct lsm_static_calls_table {\n\tstruct lsm_static_call binder_set_context_mgr[3];\n\tstruct lsm_static_call binder_transaction[3];\n\tstruct lsm_static_call binder_transfer_binder[3];\n\tstruct lsm_static_call binder_transfer_file[3];\n\tstruct lsm_static_call ptrace_access_check[3];\n\tstruct lsm_static_call ptrace_traceme[3];\n\tstruct lsm_static_call capget[3];\n\tstruct lsm_static_call capset[3];\n\tstruct lsm_static_call capable[3];\n\tstruct lsm_static_call quotactl[3];\n\tstruct lsm_static_call quota_on[3];\n\tstruct lsm_static_call syslog[3];\n\tstruct lsm_static_call settime[3];\n\tstruct lsm_static_call vm_enough_memory[3];\n\tstruct lsm_static_call bprm_creds_for_exec[3];\n\tstruct lsm_static_call bprm_creds_from_file[3];\n\tstruct lsm_static_call bprm_check_security[3];\n\tstruct lsm_static_call bprm_committing_creds[3];\n\tstruct lsm_static_call bprm_committed_creds[3];\n\tstruct lsm_static_call fs_context_submount[3];\n\tstruct lsm_static_call fs_context_dup[3];\n\tstruct lsm_static_call fs_context_parse_param[3];\n\tstruct lsm_static_call sb_alloc_security[3];\n\tstruct lsm_static_call sb_delete[3];\n\tstruct lsm_static_call sb_free_security[3];\n\tstruct lsm_static_call sb_free_mnt_opts[3];\n\tstruct lsm_static_call sb_eat_lsm_opts[3];\n\tstruct lsm_static_call sb_mnt_opts_compat[3];\n\tstruct lsm_static_call sb_remount[3];\n\tstruct lsm_static_call sb_kern_mount[3];\n\tstruct lsm_static_call sb_show_options[3];\n\tstruct lsm_static_call sb_statfs[3];\n\tstruct lsm_static_call sb_mount[3];\n\tstruct lsm_static_call sb_umount[3];\n\tstruct lsm_static_call sb_pivotroot[3];\n\tstruct lsm_static_call sb_set_mnt_opts[3];\n\tstruct lsm_static_call sb_clone_mnt_opts[3];\n\tstruct lsm_static_call move_mount[3];\n\tstruct lsm_static_call dentry_init_security[3];\n\tstruct lsm_static_call dentry_create_files_as[3];\n\tstruct lsm_static_call path_unlink[3];\n\tstruct lsm_static_call path_mkdir[3];\n\tstruct lsm_static_call path_rmdir[3];\n\tstruct lsm_static_call path_mknod[3];\n\tstruct lsm_static_call path_post_mknod[3];\n\tstruct lsm_static_call path_truncate[3];\n\tstruct lsm_static_call path_symlink[3];\n\tstruct lsm_static_call path_link[3];\n\tstruct lsm_static_call path_rename[3];\n\tstruct lsm_static_call path_chmod[3];\n\tstruct lsm_static_call path_chown[3];\n\tstruct lsm_static_call path_chroot[3];\n\tstruct lsm_static_call path_notify[3];\n\tstruct lsm_static_call inode_alloc_security[3];\n\tstruct lsm_static_call inode_free_security[3];\n\tstruct lsm_static_call inode_free_security_rcu[3];\n\tstruct lsm_static_call inode_init_security[3];\n\tstruct lsm_static_call inode_init_security_anon[3];\n\tstruct lsm_static_call inode_create[3];\n\tstruct lsm_static_call inode_post_create_tmpfile[3];\n\tstruct lsm_static_call inode_link[3];\n\tstruct lsm_static_call inode_unlink[3];\n\tstruct lsm_static_call inode_symlink[3];\n\tstruct lsm_static_call inode_mkdir[3];\n\tstruct lsm_static_call inode_rmdir[3];\n\tstruct lsm_static_call inode_mknod[3];\n\tstruct lsm_static_call inode_rename[3];\n\tstruct lsm_static_call inode_readlink[3];\n\tstruct lsm_static_call inode_follow_link[3];\n\tstruct lsm_static_call inode_permission[3];\n\tstruct lsm_static_call inode_setattr[3];\n\tstruct lsm_static_call inode_post_setattr[3];\n\tstruct lsm_static_call inode_getattr[3];\n\tstruct lsm_static_call inode_xattr_skipcap[3];\n\tstruct lsm_static_call inode_setxattr[3];\n\tstruct lsm_static_call inode_post_setxattr[3];\n\tstruct lsm_static_call inode_getxattr[3];\n\tstruct lsm_static_call inode_listxattr[3];\n\tstruct lsm_static_call inode_removexattr[3];\n\tstruct lsm_static_call inode_post_removexattr[3];\n\tstruct lsm_static_call inode_file_setattr[3];\n\tstruct lsm_static_call inode_file_getattr[3];\n\tstruct lsm_static_call inode_set_acl[3];\n\tstruct lsm_static_call inode_post_set_acl[3];\n\tstruct lsm_static_call inode_get_acl[3];\n\tstruct lsm_static_call inode_remove_acl[3];\n\tstruct lsm_static_call inode_post_remove_acl[3];\n\tstruct lsm_static_call inode_need_killpriv[3];\n\tstruct lsm_static_call inode_killpriv[3];\n\tstruct lsm_static_call inode_getsecurity[3];\n\tstruct lsm_static_call inode_setsecurity[3];\n\tstruct lsm_static_call inode_listsecurity[3];\n\tstruct lsm_static_call inode_getlsmprop[3];\n\tstruct lsm_static_call inode_copy_up[3];\n\tstruct lsm_static_call inode_copy_up_xattr[3];\n\tstruct lsm_static_call inode_setintegrity[3];\n\tstruct lsm_static_call kernfs_init_security[3];\n\tstruct lsm_static_call file_permission[3];\n\tstruct lsm_static_call file_alloc_security[3];\n\tstruct lsm_static_call file_release[3];\n\tstruct lsm_static_call file_free_security[3];\n\tstruct lsm_static_call file_ioctl[3];\n\tstruct lsm_static_call file_ioctl_compat[3];\n\tstruct lsm_static_call mmap_addr[3];\n\tstruct lsm_static_call mmap_file[3];\n\tstruct lsm_static_call file_mprotect[3];\n\tstruct lsm_static_call file_lock[3];\n\tstruct lsm_static_call file_fcntl[3];\n\tstruct lsm_static_call file_set_fowner[3];\n\tstruct lsm_static_call file_send_sigiotask[3];\n\tstruct lsm_static_call file_receive[3];\n\tstruct lsm_static_call file_open[3];\n\tstruct lsm_static_call file_post_open[3];\n\tstruct lsm_static_call file_truncate[3];\n\tstruct lsm_static_call task_alloc[3];\n\tstruct lsm_static_call task_free[3];\n\tstruct lsm_static_call cred_alloc_blank[3];\n\tstruct lsm_static_call cred_free[3];\n\tstruct lsm_static_call cred_prepare[3];\n\tstruct lsm_static_call cred_transfer[3];\n\tstruct lsm_static_call cred_getsecid[3];\n\tstruct lsm_static_call cred_getlsmprop[3];\n\tstruct lsm_static_call kernel_act_as[3];\n\tstruct lsm_static_call kernel_create_files_as[3];\n\tstruct lsm_static_call kernel_module_request[3];\n\tstruct lsm_static_call kernel_load_data[3];\n\tstruct lsm_static_call kernel_post_load_data[3];\n\tstruct lsm_static_call kernel_read_file[3];\n\tstruct lsm_static_call kernel_post_read_file[3];\n\tstruct lsm_static_call task_fix_setuid[3];\n\tstruct lsm_static_call task_fix_setgid[3];\n\tstruct lsm_static_call task_fix_setgroups[3];\n\tstruct lsm_static_call task_setpgid[3];\n\tstruct lsm_static_call task_getpgid[3];\n\tstruct lsm_static_call task_getsid[3];\n\tstruct lsm_static_call current_getlsmprop_subj[3];\n\tstruct lsm_static_call task_getlsmprop_obj[3];\n\tstruct lsm_static_call task_setnice[3];\n\tstruct lsm_static_call task_setioprio[3];\n\tstruct lsm_static_call task_getioprio[3];\n\tstruct lsm_static_call task_prlimit[3];\n\tstruct lsm_static_call task_setrlimit[3];\n\tstruct lsm_static_call task_setscheduler[3];\n\tstruct lsm_static_call task_getscheduler[3];\n\tstruct lsm_static_call task_movememory[3];\n\tstruct lsm_static_call task_kill[3];\n\tstruct lsm_static_call task_prctl[3];\n\tstruct lsm_static_call task_to_inode[3];\n\tstruct lsm_static_call userns_create[3];\n\tstruct lsm_static_call ipc_permission[3];\n\tstruct lsm_static_call ipc_getlsmprop[3];\n\tstruct lsm_static_call msg_msg_alloc_security[3];\n\tstruct lsm_static_call msg_msg_free_security[3];\n\tstruct lsm_static_call msg_queue_alloc_security[3];\n\tstruct lsm_static_call msg_queue_free_security[3];\n\tstruct lsm_static_call msg_queue_associate[3];\n\tstruct lsm_static_call msg_queue_msgctl[3];\n\tstruct lsm_static_call msg_queue_msgsnd[3];\n\tstruct lsm_static_call msg_queue_msgrcv[3];\n\tstruct lsm_static_call shm_alloc_security[3];\n\tstruct lsm_static_call shm_free_security[3];\n\tstruct lsm_static_call shm_associate[3];\n\tstruct lsm_static_call shm_shmctl[3];\n\tstruct lsm_static_call shm_shmat[3];\n\tstruct lsm_static_call sem_alloc_security[3];\n\tstruct lsm_static_call sem_free_security[3];\n\tstruct lsm_static_call sem_associate[3];\n\tstruct lsm_static_call sem_semctl[3];\n\tstruct lsm_static_call sem_semop[3];\n\tstruct lsm_static_call netlink_send[3];\n\tstruct lsm_static_call d_instantiate[3];\n\tstruct lsm_static_call getselfattr[3];\n\tstruct lsm_static_call setselfattr[3];\n\tstruct lsm_static_call getprocattr[3];\n\tstruct lsm_static_call setprocattr[3];\n\tstruct lsm_static_call ismaclabel[3];\n\tstruct lsm_static_call secid_to_secctx[3];\n\tstruct lsm_static_call lsmprop_to_secctx[3];\n\tstruct lsm_static_call secctx_to_secid[3];\n\tstruct lsm_static_call release_secctx[3];\n\tstruct lsm_static_call inode_invalidate_secctx[3];\n\tstruct lsm_static_call inode_notifysecctx[3];\n\tstruct lsm_static_call inode_setsecctx[3];\n\tstruct lsm_static_call inode_getsecctx[3];\n\tstruct lsm_static_call unix_stream_connect[3];\n\tstruct lsm_static_call unix_may_send[3];\n\tstruct lsm_static_call socket_create[3];\n\tstruct lsm_static_call socket_post_create[3];\n\tstruct lsm_static_call socket_socketpair[3];\n\tstruct lsm_static_call socket_bind[3];\n\tstruct lsm_static_call socket_connect[3];\n\tstruct lsm_static_call socket_listen[3];\n\tstruct lsm_static_call socket_accept[3];\n\tstruct lsm_static_call socket_sendmsg[3];\n\tstruct lsm_static_call socket_recvmsg[3];\n\tstruct lsm_static_call socket_getsockname[3];\n\tstruct lsm_static_call socket_getpeername[3];\n\tstruct lsm_static_call socket_getsockopt[3];\n\tstruct lsm_static_call socket_setsockopt[3];\n\tstruct lsm_static_call socket_shutdown[3];\n\tstruct lsm_static_call socket_sock_rcv_skb[3];\n\tstruct lsm_static_call socket_getpeersec_stream[3];\n\tstruct lsm_static_call socket_getpeersec_dgram[3];\n\tstruct lsm_static_call sk_alloc_security[3];\n\tstruct lsm_static_call sk_free_security[3];\n\tstruct lsm_static_call sk_clone_security[3];\n\tstruct lsm_static_call sk_getsecid[3];\n\tstruct lsm_static_call sock_graft[3];\n\tstruct lsm_static_call inet_conn_request[3];\n\tstruct lsm_static_call inet_csk_clone[3];\n\tstruct lsm_static_call inet_conn_established[3];\n\tstruct lsm_static_call secmark_relabel_packet[3];\n\tstruct lsm_static_call secmark_refcount_inc[3];\n\tstruct lsm_static_call secmark_refcount_dec[3];\n\tstruct lsm_static_call req_classify_flow[3];\n\tstruct lsm_static_call tun_dev_alloc_security[3];\n\tstruct lsm_static_call tun_dev_create[3];\n\tstruct lsm_static_call tun_dev_attach_queue[3];\n\tstruct lsm_static_call tun_dev_attach[3];\n\tstruct lsm_static_call tun_dev_open[3];\n\tstruct lsm_static_call sctp_assoc_request[3];\n\tstruct lsm_static_call sctp_bind_connect[3];\n\tstruct lsm_static_call sctp_sk_clone[3];\n\tstruct lsm_static_call sctp_assoc_established[3];\n\tstruct lsm_static_call mptcp_add_subflow[3];\n\tstruct lsm_static_call key_alloc[3];\n\tstruct lsm_static_call key_permission[3];\n\tstruct lsm_static_call key_getsecurity[3];\n\tstruct lsm_static_call key_post_create_or_update[3];\n\tstruct lsm_static_call audit_rule_init[3];\n\tstruct lsm_static_call audit_rule_known[3];\n\tstruct lsm_static_call audit_rule_match[3];\n\tstruct lsm_static_call audit_rule_free[3];\n\tstruct lsm_static_call bpf[3];\n\tstruct lsm_static_call bpf_map[3];\n\tstruct lsm_static_call bpf_prog[3];\n\tstruct lsm_static_call bpf_map_create[3];\n\tstruct lsm_static_call bpf_map_free[3];\n\tstruct lsm_static_call bpf_prog_load[3];\n\tstruct lsm_static_call bpf_prog_free[3];\n\tstruct lsm_static_call bpf_token_create[3];\n\tstruct lsm_static_call bpf_token_free[3];\n\tstruct lsm_static_call bpf_token_cmd[3];\n\tstruct lsm_static_call bpf_token_capable[3];\n\tstruct lsm_static_call locked_down[3];\n\tstruct lsm_static_call perf_event_open[3];\n\tstruct lsm_static_call perf_event_alloc[3];\n\tstruct lsm_static_call perf_event_read[3];\n\tstruct lsm_static_call perf_event_write[3];\n\tstruct lsm_static_call uring_override_creds[3];\n\tstruct lsm_static_call uring_sqpoll[3];\n\tstruct lsm_static_call uring_cmd[3];\n\tstruct lsm_static_call uring_allowed[3];\n\tstruct lsm_static_call initramfs_populated[3];\n\tstruct lsm_static_call bdev_alloc_security[3];\n\tstruct lsm_static_call bdev_free_security[3];\n\tstruct lsm_static_call bdev_setintegrity[3];\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwq_node {\n\tstruct llist_node node;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct mac_addr {\n\tunsigned char addr[6];\n};\n\ntypedef struct mac_addr mac_addr;\n\nstruct queue_stats {\n\tunion {\n\t\tlong unsigned int first;\n\t\tlong unsigned int rx_packets;\n\t};\n\tlong unsigned int rx_bytes;\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_packets;\n\tlong unsigned int tx_bytes;\n\tlong unsigned int tx_dropped;\n};\n\nstruct macb;\n\nstruct macb_dma_desc;\n\nstruct macb_tx_skb;\n\nstruct macb_queue {\n\tstruct macb *bp;\n\tint irq;\n\tunsigned int ISR;\n\tunsigned int IER;\n\tunsigned int IDR;\n\tunsigned int IMR;\n\tunsigned int TBQP;\n\tunsigned int RBQS;\n\tunsigned int RBQP;\n\tunsigned int ENST_START_TIME;\n\tunsigned int ENST_ON_TIME;\n\tunsigned int ENST_OFF_TIME;\n\tspinlock_t tx_ptr_lock;\n\tunsigned int tx_head;\n\tunsigned int tx_tail;\n\tstruct macb_dma_desc *tx_ring;\n\tstruct macb_tx_skb *tx_skb;\n\tdma_addr_t tx_ring_dma;\n\tstruct work_struct tx_error_task;\n\tbool txubr_pending;\n\tstruct napi_struct napi_tx;\n\tdma_addr_t rx_ring_dma;\n\tdma_addr_t rx_buffers_dma;\n\tunsigned int rx_tail;\n\tunsigned int rx_prepared_head;\n\tstruct macb_dma_desc *rx_ring;\n\tstruct sk_buff **rx_skbuff;\n\tvoid *rx_buffers;\n\tstruct napi_struct napi_rx;\n\tstruct queue_stats stats;\n};\n\nstruct macb_stats {\n\tu64 rx_pause_frames;\n\tu64 tx_ok;\n\tu64 tx_single_cols;\n\tu64 tx_multiple_cols;\n\tu64 rx_ok;\n\tu64 rx_fcs_errors;\n\tu64 rx_align_errors;\n\tu64 tx_deferred;\n\tu64 tx_late_cols;\n\tu64 tx_excessive_cols;\n\tu64 tx_underruns;\n\tu64 tx_carrier_errors;\n\tu64 rx_resource_errors;\n\tu64 rx_overruns;\n\tu64 rx_symbol_errors;\n\tu64 rx_oversize_pkts;\n\tu64 rx_jabbers;\n\tu64 rx_undersize_pkts;\n\tu64 sqe_test_errors;\n\tu64 rx_length_mismatch;\n\tu64 tx_pause_frames;\n};\n\nstruct macb_or_gem_ops {\n\tint (*mog_alloc_rx_buffers)(struct macb *);\n\tvoid (*mog_free_rx_buffers)(struct macb *);\n\tvoid (*mog_init_rings)(struct macb *);\n\tint (*mog_rx)(struct macb_queue *, struct napi_struct *, int);\n};\n\nstruct phylink_link_state;\n\nstruct phylink_config {\n\tstruct device *dev;\n\tenum phylink_op_type type;\n\tbool poll_fixed_state;\n\tbool mac_managed_pm;\n\tbool mac_requires_rxc;\n\tbool default_an_inband;\n\tbool eee_rx_clk_stop_enable;\n\tvoid (*get_fixed_state)(struct phylink_config *, struct phylink_link_state *);\n\tlong unsigned int supported_interfaces[1];\n\tlong unsigned int lpi_interfaces[1];\n\tlong unsigned int mac_capabilities;\n\tlong unsigned int lpi_capabilities;\n\tu32 lpi_timer_default;\n\tbool eee_enabled_default;\n\tbool wol_phy_legacy;\n\tbool wol_phy_speed_ctrl;\n\tu32 wol_mac_support;\n};\n\nstruct phylink_pcs_ops;\n\nstruct phylink;\n\nstruct phylink_pcs {\n\tlong unsigned int supported_interfaces[1];\n\tconst struct phylink_pcs_ops *ops;\n\tstruct phylink *phylink;\n\tbool poll;\n\tbool rxc_always_on;\n};\n\nstruct macb_tx_skb {\n\tstruct sk_buff *skb;\n\tdma_addr_t mapping;\n\tsize_t size;\n\tbool mapped_as_page;\n};\n\nstruct tsu_incr {\n\tu32 sub_ns;\n\tu32 ns;\n};\n\nstruct macb_pm_data {\n\tu32 scrt2;\n\tu32 usrio;\n};\n\nstruct mii_bus;\n\nstruct macb_ptp_info;\n\nstruct macb_usrio_config;\n\nstruct macb {\n\tvoid *regs;\n\tbool native_io;\n\tu32 (*macb_reg_readl)(struct macb *, int);\n\tvoid (*macb_reg_writel)(struct macb *, int, u32);\n\tstruct macb_dma_desc *rx_ring_tieoff;\n\tdma_addr_t rx_ring_tieoff_dma;\n\tsize_t rx_buffer_size;\n\tunsigned int rx_ring_size;\n\tunsigned int tx_ring_size;\n\tunsigned int num_queues;\n\tstruct macb_queue queues[8];\n\tspinlock_t lock;\n\tstruct platform_device *pdev;\n\tstruct clk *pclk;\n\tstruct clk *hclk;\n\tstruct clk *tx_clk;\n\tstruct clk *rx_clk;\n\tstruct clk *tsu_clk;\n\tstruct net_device *dev;\n\tspinlock_t stats_lock;\n\tunion {\n\t\tstruct macb_stats macb;\n\t\tstruct gem_stats gem;\n\t} hw_stats;\n\tstruct macb_or_gem_ops macbgem_ops;\n\tstruct mii_bus *mii_bus;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tstruct phylink_pcs phylink_usx_pcs;\n\tstruct phylink_pcs phylink_sgmii_pcs;\n\tu32 caps;\n\tunsigned int dma_burst_length;\n\tphy_interface_t phy_interface;\n\tstruct macb_tx_skb rm9200_txq[2];\n\tunsigned int max_tx_length;\n\tu64 ethtool_stats[91];\n\tunsigned int rx_frm_len_mask;\n\tunsigned int jumbo_max_len;\n\tu32 wol;\n\tu32 wolopts;\n\tu32 rx_watermark;\n\tstruct macb_ptp_info *ptp_info;\n\tstruct phy *phy;\n\tspinlock_t tsu_clk_lock;\n\tunsigned int tsu_rate;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct tsu_incr tsu_incr;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tstruct ethtool_rx_fs_list rx_fs_list;\n\tspinlock_t rx_fs_lock;\n\tunsigned int max_tuples;\n\tstruct work_struct hresp_err_bh_work;\n\tint rx_bd_rd_prefetch;\n\tint tx_bd_rd_prefetch;\n\tu32 rx_intr_mask;\n\tstruct macb_pm_data pm_data;\n\tconst struct macb_usrio_config *usrio;\n};\n\nstruct macb_config {\n\tu32 caps;\n\tunsigned int dma_burst_length;\n\tint (*clk_init)(struct platform_device *, struct clk **, struct clk **, struct clk **, struct clk **, struct clk **);\n\tint (*init)(struct platform_device *);\n\tunsigned int max_tx_length;\n\tint jumbo_max_len;\n\tconst struct macb_usrio_config *usrio;\n};\n\nstruct macb_dma_desc {\n\tu32 addr;\n\tu32 ctrl;\n};\n\nstruct macb_dma_desc_64 {\n\tu32 addrh;\n\tu32 resvd;\n};\n\nstruct macb_platform_data {\n\tstruct clk *pclk;\n\tstruct clk *hclk;\n};\n\nstruct macb_ptp_info {\n\tvoid (*ptp_init)(struct net_device *);\n\tvoid (*ptp_remove)(struct net_device *);\n\ts32 (*get_ptp_max_adj)(void);\n\tunsigned int (*get_tsu_rate)(struct macb *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tint (*get_hwtst)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*set_hwtst)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct macb_queue_enst_config {\n\tu32 start_time_mask;\n\tu32 on_time_bytes;\n\tu32 off_time_bytes;\n\tu8 queue_id;\n};\n\nstruct macb_usrio_config {\n\tu32 mii;\n\tu32 rmii;\n\tu32 rgmii;\n\tu32 refclk;\n\tu32 hdfctlen;\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct mafield {\n\tconst char *prefix;\n\tint field;\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct map_info___2 {\n\tstruct map_info___2 *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct mtd_chip_driver;\n\nstruct map_info {\n\tconst char *name;\n\tlong unsigned int size;\n\tresource_size_t phys;\n\tvoid *virt;\n\tvoid *cached;\n\tint swap;\n\tint bankwidth;\n\tvoid (*inval_cache)(struct map_info *, long unsigned int, ssize_t);\n\tvoid (*set_vpp)(struct map_info *, int);\n\tlong unsigned int pfow_base;\n\tlong unsigned int map_priv_1;\n\tlong unsigned int map_priv_2;\n\tstruct device_node *device_node;\n\tvoid *fldrv_priv;\n\tstruct mtd_chip_driver *fldrv;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[9];\n\tvoid *slot[10];\n\tlong unsigned int gap[10];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[33];\n\tunion {\n\t\tstruct maple_enode *slot[34];\n\t\tstruct {\n\t\t\tlong unsigned int padding[21];\n\t\t\tlong unsigned int gap[21];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[15];\n\tunion {\n\t\tvoid *slot[16];\n\t\tstruct {\n\t\t\tvoid *pad[15];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[31];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct match {\n\tu32 mode;\n\tu32 area;\n\tu8 depth;\n};\n\nstruct match_ids_walk_data {\n\tstruct acpi_device_id *ids;\n\tstruct acpi_device *adev;\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct match_workbuf {\n\tunsigned int pos;\n\tunsigned int len;\n\tunsigned int history[32];\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker *c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tlong unsigned int e_flags;\n\tu64 e_value;\n};\n\nstruct mbox_controller;\n\nstruct mbox_client;\n\nstruct mbox_chan {\n\tstruct mbox_controller *mbox;\n\tunsigned int txdone_method;\n\tstruct mbox_client *cl;\n\tstruct completion tx_complete;\n\tvoid *active_req;\n\tunsigned int msg_count;\n\tunsigned int msg_free;\n\tvoid *msg_data[20];\n\tspinlock_t lock;\n\tvoid *con_priv;\n};\n\nstruct mbox_chan_ops {\n\tint (*send_data)(struct mbox_chan *, void *);\n\tint (*flush)(struct mbox_chan *, long unsigned int);\n\tint (*startup)(struct mbox_chan *);\n\tvoid (*shutdown)(struct mbox_chan *);\n\tbool (*last_tx_done)(struct mbox_chan *);\n\tbool (*peek_data)(struct mbox_chan *);\n};\n\nstruct mbox_client {\n\tstruct device *dev;\n\tbool tx_block;\n\tlong unsigned int tx_tout;\n\tbool knows_txdone;\n\tvoid (*rx_callback)(struct mbox_client *, void *);\n\tvoid (*tx_prepare)(struct mbox_client *, void *);\n\tvoid (*tx_done)(struct mbox_client *, void *, int);\n};\n\nstruct mbox_controller {\n\tstruct device *dev;\n\tconst struct mbox_chan_ops *ops;\n\tstruct mbox_chan *chans;\n\tint num_chans;\n\tbool txdone_irq;\n\tbool txdone_poll;\n\tunsigned int txpoll_period;\n\tstruct mbox_chan * (*fw_xlate)(struct mbox_controller *, const struct fwnode_reference_args *);\n\tstruct mbox_chan * (*of_xlate)(struct mbox_controller *, const struct of_phandle_args *);\n\tstruct hrtimer poll_hrt;\n\tspinlock_t poll_hrt_lock;\n\tstruct list_head node;\n};\n\nstruct mcfg_entry {\n\tstruct list_head list;\n\tphys_addr_t addr;\n\tu16 segment;\n\tu8 bus_start;\n\tu8 bus_end;\n};\n\nstruct pci_ecam_ops;\n\nstruct mcfg_fixup {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n\tu16 segment;\n\tstruct resource bus_range;\n\tconst struct pci_ecam_ops *ops;\n\tstruct resource cfgres;\n};\n\nstruct mcs_spinlock {\n\tstruct mcs_spinlock *next;\n\tint locked;\n\tint count;\n};\n\nstruct mctrl_gpios {\n\tstruct uart_port *port;\n\tstruct gpio_desc *gpio[6];\n\tint irq[6];\n\tunsigned int mctrl_prev;\n\tbool mctrl_on;\n};\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n\tvoid (*shutdown)(struct mdio_device *);\n};\n\nstruct mdiobus_devres {\n\tstruct mii_bus *mii;\n};\n\nstruct media_event_desc {\n\t__u8 media_event_code: 4;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 media_present: 1;\n\t__u8 reserved2: 6;\n\t__u8 start_slot;\n\t__u8 end_slot;\n};\n\nstruct mem_cgroup_private_id {\n\tint id;\n\trefcount_t ref;\n};\n\nstruct vmpressure {\n\tlong unsigned int scanned;\n\tlong unsigned int reclaimed;\n\tlong unsigned int tree_scanned;\n\tlong unsigned int tree_reclaimed;\n\tspinlock_t sr_lock;\n\tstruct list_head events;\n\tstruct mutex events_lock;\n\tstruct work_struct work;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct memcg_cgwb_frn {\n\tu64 bdi_id;\n\tint memcg_id;\n\tu64 at;\n\tstruct wb_completion done;\n};\n\nstruct memcg_vmstats;\n\nstruct memcg_vmstats_percpu;\n\nstruct mem_cgroup_per_node;\n\nstruct mem_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct mem_cgroup_private_id id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter memory;\n\tunion {\n\t\tstruct page_counter swap;\n\t\tstruct page_counter memsw;\n\t};\n\tstruct list_head memory_peaks;\n\tstruct list_head swap_peaks;\n\tspinlock_t peaks_lock;\n\tstruct work_struct high_work;\n\tstruct vmpressure vmpressure;\n\tbool oom_group;\n\tint swappiness;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct cgroup_file swap_events_file;\n\tstruct memcg_vmstats *vmstats;\n\tatomic_long_t memory_events[10];\n\tatomic_long_t memory_events_local[10];\n\tu64 socket_pressure;\n\tint kmemcg_id;\n\tstruct obj_cgroup *objcg;\n\tstruct obj_cgroup *orig_objcg;\n\tstruct list_head objcg_list;\n\tstruct memcg_vmstats_percpu *vmstats_percpu;\n\tstruct list_head cgwb_list;\n\tstruct wb_domain cgwb_domain;\n\tstruct memcg_cgwb_frn cgwb_frn[4];\n\tstruct mem_cgroup_per_node *nodeinfo[0];\n\tlong: 64;\n};\n\nstruct mem_cgroup_reclaim_iter {\n\tstruct mem_cgroup *position;\n\tatomic_t generation;\n};\n\nstruct shrinker_info;\n\nstruct mem_cgroup_per_node {\n\tstruct mem_cgroup *memcg;\n\tstruct lruvec_stats_percpu *lruvec_stats_percpu;\n\tstruct lruvec_stats *lruvec_stats;\n\tstruct shrinker_info *shrinker_info;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct lruvec lruvec;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int lru_zone_size[15];\n\tstruct mem_cgroup_reclaim_iter iter;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n};\n\nstruct mem_section_usage;\n\nstruct mem_section {\n\tlong unsigned int section_mem_map;\n\tstruct mem_section_usage *usage;\n};\n\nstruct mem_section_usage {\n\tstruct callback_head rcu;\n\tlong unsigned int subsection_map[1];\n\tlong unsigned int pageblock_flags[0];\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n\tint nid;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memcg_stock_pcp {\n\tlocal_trylock_t lock;\n\tuint8_t nr_pages[7];\n\tstruct mem_cgroup *cached[7];\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct memcg_vmstats {\n\tlong int state[40];\n\tlong unsigned int events[22];\n\tlong int state_local[40];\n\tlong unsigned int events_local[22];\n\tlong int state_pending[40];\n\tlong unsigned int events_pending[22];\n\tatomic_t stats_updates;\n};\n\nstruct memcg_vmstats_percpu {\n\tunsigned int stats_updates;\n\tstruct memcg_vmstats_percpu *parent_pcpu;\n\tstruct memcg_vmstats *vmstats;\n\tlong int state[40];\n\tlong unsigned int events[22];\n\tlong int state_prev[40];\n\tlong unsigned int events_prev[22];\n\tlong: 64;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct memory_dev_type {\n\tstruct list_head tier_sibling;\n\tstruct list_head list;\n\tint adistance;\n\tnodemask_t nodes;\n\tstruct kref kref;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct memory_stat {\n\tconst char *name;\n\tunsigned int idx;\n};\n\nstruct memory_tier {\n\tstruct list_head list;\n\tstruct list_head memory_types;\n\tint adistance_start;\n\tstruct device dev;\n\tnodemask_t lower_tier_mask;\n};\n\nstruct mempolicy {\n\tatomic_t refcnt;\n\tshort unsigned int mode;\n\tshort unsigned int flags;\n\tnodemask_t nodes;\n\tint home_node;\n\tunion {\n\t\tnodemask_t cpuset_mems_allowed;\n\t\tnodemask_t user_nodemask;\n\t} w;\n};\n\nstruct mempolicy_operations {\n\tint (*create)(struct mempolicy *, const nodemask_t *);\n\tvoid (*rebind)(struct mempolicy *, const nodemask_t *);\n};\n\nstruct menu_device {\n\tint needs_update;\n\tint tick_wakeup;\n\tu64 next_timer_ns;\n\tunsigned int bucket;\n\tunsigned int correction_factor[6];\n\tunsigned int intervals[8];\n\tint interval_ptr;\n};\n\nstruct merge_sched_data {\n\tint can_add_hw;\n\tenum event_type_t event_type;\n};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mext_data {\n\tstruct inode *orig_inode;\n\tstruct inode *donor_inode;\n\tstruct ext4_map_blocks orig_map;\n\text4_lblk_t donor_lblk;\n};\n\nstruct mfd_cell_acpi_match;\n\nstruct mfd_cell {\n\tconst char *name;\n\tint id;\n\tint level;\n\tint (*suspend)(struct platform_device *);\n\tint (*resume)(struct platform_device *);\n\tconst void *platform_data;\n\tsize_t pdata_size;\n\tconst struct mfd_cell_acpi_match *acpi_match;\n\tconst struct software_node *swnode;\n\tconst char *of_compatible;\n\tu64 of_reg;\n\tbool use_of_reg;\n\tint num_resources;\n\tconst struct resource *resources;\n\tbool ignore_resource_conflicts;\n\tbool pm_runtime_no_callbacks;\n\tint num_parent_supplies;\n\tconst char * const *parent_supplies;\n};\n\nstruct mfd_cell_acpi_match {\n\tconst char *pnpid;\n\tconst long long unsigned int adr;\n};\n\nstruct mfd_of_node_entry {\n\tstruct list_head list;\n\tstruct device *dev;\n\tstruct device_node *np;\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_mpol {\n\tstruct mempolicy *pol;\n\tlong unsigned int ilx;\n};\n\nstruct migration_swap_arg {\n\tstruct task_struct *src_task;\n\tstruct task_struct *dst_task;\n\tint src_cpu;\n\tint dst_cpu;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct phy_package_shared;\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n\tstruct phy_package_shared *shared[32];\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct min_heap_callbacks {\n\tbool (*less)(const void *, const void *, void *);\n\tvoid (*swp)(void *, void *, void *);\n};\n\nstruct min_heap_char {\n\tsize_t nr;\n\tsize_t size;\n\tchar *data;\n\tchar preallocated[0];\n};\n\ntypedef struct min_heap_char min_heap_char;\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nstruct tcf_proto;\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct mipi_dsi_host;\n\nstruct mipi_dsi_device {\n\tstruct mipi_dsi_host *host;\n\tstruct device dev;\n\tbool attached;\n\tchar name[20];\n\tunsigned int channel;\n\tunsigned int lanes;\n\tenum mipi_dsi_pixel_format format;\n\tlong unsigned int mode_flags;\n\tlong unsigned int hs_rate;\n\tlong unsigned int lp_rate;\n\tstruct drm_dsc_config *dsc;\n};\n\nstruct mipi_dsi_device_info {\n\tchar type[20];\n\tu32 channel;\n\tstruct device_node *node;\n};\n\nstruct mipi_dsi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct mipi_dsi_device *);\n\tvoid (*remove)(struct mipi_dsi_device *);\n\tvoid (*shutdown)(struct mipi_dsi_device *);\n};\n\nstruct mipi_dsi_host_ops;\n\nstruct mipi_dsi_host {\n\tstruct device *dev;\n\tconst struct mipi_dsi_host_ops *ops;\n\tstruct list_head list;\n};\n\nstruct mipi_dsi_msg;\n\nstruct mipi_dsi_host_ops {\n\tint (*attach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tint (*detach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tssize_t (*transfer)(struct mipi_dsi_host *, const struct mipi_dsi_msg *);\n};\n\nstruct mipi_dsi_msg {\n\tu8 channel;\n\tu8 type;\n\tu16 flags;\n\tsize_t tx_len;\n\tconst void *tx_buf;\n\tsize_t rx_len;\n\tvoid *rx_buf;\n};\n\nstruct mipi_dsi_multi_context {\n\tstruct mipi_dsi_device *dsi;\n\tint accum_err;\n};\n\nstruct mipi_dsi_packet {\n\tsize_t size;\n\tu8 header[4];\n\tsize_t payload_length;\n\tconst u8 *payload;\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct ml_effect_state {\n\tstruct ff_effect *effect;\n\tlong unsigned int flags;\n\tint count;\n\tlong unsigned int play_at;\n\tlong unsigned int stop_at;\n\tlong unsigned int adj_at;\n};\n\nstruct ml_device {\n\tvoid *private;\n\tstruct ml_effect_state states[16];\n\tint gain;\n\tstruct timer_list timer;\n\tstruct input_dev *dev;\n\tint (*play_effect)(struct input_dev *, void *, struct ff_effect *);\n};\n\nstruct mld2_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\tstruct in6_addr grec_mca;\n\tstruct in6_addr grec_src[0];\n};\n\nstruct mld2_query {\n\tstruct icmp6hdr mld2q_hdr;\n\tstruct in6_addr mld2q_mca;\n\t__u8 mld2q_qrv: 3;\n\t__u8 mld2q_suppress: 1;\n\t__u8 mld2q_resv2: 4;\n\t__u8 mld2q_qqic;\n\t__be16 mld2q_nsrcs;\n\tstruct in6_addr mld2q_srcs[0];\n};\n\nstruct mld2_report {\n\tstruct icmp6hdr mld2r_hdr;\n\tstruct mld2_grec mld2r_grec[0];\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tstruct ethtool_mm_stats stats;\n};\n\ntypedef struct mm_struct *class_mmap_read_lock_t;\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n};\n\nstruct mmu_notifier_subscriptions;\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 64;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct rcuwait vma_writer_wait;\n\t\tseqcount_t mm_lock_seq;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[66];\n\t\tlong unsigned int saved_e_flags;\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct task_struct *owner;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tstruct mmu_notifier_subscriptions *notifier_subscriptions;\n\t\tlong unsigned int numa_next_scan;\n\t\tlong unsigned int numa_scan_offset;\n\t\tint numa_scan_seq;\n\t\tatomic_t tlb_flush_pending;\n\t\tatomic_t tlb_flush_batched;\n\t\tstruct uprobes_state uprobes_state;\n\t\tatomic_long_t hugetlb_usage;\n\t\tstruct work_struct async_put_work;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n\tstruct task_struct *owner;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mmc_blk_busy_data {\n\tstruct mmc_card *card;\n\tu32 status;\n};\n\nstruct mmc_ctx {\n\tstruct task_struct *task;\n};\n\nstruct mmc_blk_data;\n\nstruct mmc_queue {\n\tstruct mmc_card *card;\n\tstruct mmc_ctx ctx;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct mmc_blk_data *blkdata;\n\tstruct request_queue *queue;\n\tspinlock_t lock;\n\tint in_flight[3];\n\tunsigned int cqe_busy;\n\tbool busy;\n\tbool recovery_needed;\n\tbool in_recovery;\n\tbool rw_wait;\n\tbool waiting;\n\tstruct work_struct recovery_work;\n\twait_queue_head_t wait;\n\tstruct request *recovery_req;\n\tstruct request *complete_req;\n\tstruct mutex complete_lock;\n\tstruct work_struct complete_work;\n};\n\nstruct mmc_blk_data {\n\tstruct device *parent;\n\tstruct gendisk *disk;\n\tstruct mmc_queue queue;\n\tstruct list_head part;\n\tstruct list_head rpmbs;\n\tunsigned int flags;\n\tstruct kref kref;\n\tunsigned int read_only;\n\tunsigned int part_type;\n\tunsigned int reset_done;\n\tunsigned int part_curr;\n\tint area_type;\n\tstruct dentry *status_dentry;\n\tstruct dentry *ext_csd_dentry;\n};\n\nstruct mmc_ioc_cmd {\n\tint write_flag;\n\tint is_acmd;\n\t__u32 opcode;\n\t__u32 arg;\n\t__u32 response[4];\n\tunsigned int flags;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int postsleep_min_us;\n\tunsigned int postsleep_max_us;\n\tunsigned int data_timeout_ns;\n\tunsigned int cmd_timeout_ms;\n\t__u32 __pad;\n\t__u64 data_ptr;\n};\n\nstruct mmc_rpmb_data;\n\nstruct mmc_blk_ioc_data {\n\tstruct mmc_ioc_cmd ic;\n\tunsigned char *buf;\n\tu64 buf_bytes;\n\tunsigned int flags;\n\tstruct mmc_rpmb_data *rpmb;\n};\n\nstruct uhs2_command {\n\tu16 header;\n\tu16 arg;\n\t__be32 payload[2];\n\tu8 payload_len;\n\tu8 packet_len;\n\tu8 tmode_half_duplex;\n\tu8 uhs2_resp[20];\n\tu8 uhs2_resp_len;\n};\n\nstruct mmc_request {\n\tstruct mmc_command *sbc;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command *stop;\n\tstruct completion completion;\n\tstruct completion cmd_completion;\n\tvoid (*done)(struct mmc_request *);\n\tvoid (*recovery_notifier)(struct mmc_request *);\n\tstruct mmc_host *host;\n\tbool cap_cmd_during_tfr;\n\tint tag;\n\tstruct uhs2_command uhs2_cmd;\n};\n\nstruct mmc_data {\n\tunsigned int timeout_ns;\n\tunsigned int timeout_clks;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int blk_addr;\n\tint error;\n\tunsigned int flags;\n\tunsigned int bytes_xfered;\n\tstruct mmc_command *stop;\n\tstruct mmc_request *mrq;\n\tunsigned int sg_len;\n\tint sg_count;\n\tstruct scatterlist *sg;\n\ts32 host_cookie;\n};\n\nstruct mmc_blk_request {\n\tstruct mmc_request mrq;\n\tstruct mmc_command sbc;\n\tstruct mmc_command cmd;\n\tstruct mmc_command stop;\n\tstruct mmc_data data;\n};\n\nstruct mmc_bus_ops {\n\tvoid (*remove)(struct mmc_host *);\n\tvoid (*detect)(struct mmc_host *);\n\tint (*pre_suspend)(struct mmc_host *);\n\tint (*suspend)(struct mmc_host *);\n\tint (*resume)(struct mmc_host *);\n\tint (*runtime_suspend)(struct mmc_host *);\n\tint (*runtime_resume)(struct mmc_host *);\n\tint (*alive)(struct mmc_host *);\n\tint (*shutdown)(struct mmc_host *);\n\tint (*hw_reset)(struct mmc_host *);\n\tint (*sw_reset)(struct mmc_host *);\n\tbool (*cache_enabled)(struct mmc_host *);\n\tint (*flush_cache)(struct mmc_host *);\n\tint (*handle_undervoltage)(struct mmc_host *);\n};\n\nstruct mmc_busy_data {\n\tstruct mmc_card *card;\n\tbool retry_crc_err;\n\tenum mmc_busy_cmd busy_cmd;\n};\n\nstruct mmc_cid {\n\tunsigned int manfid;\n\tchar prod_name[8];\n\tunsigned char prv;\n\tunsigned int serial;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char hwrev;\n\tunsigned char fwrev;\n\tunsigned char month;\n};\n\nstruct mmc_csd {\n\tunsigned char structure;\n\tunsigned char mmca_vsn;\n\tshort unsigned int cmdclass;\n\tshort unsigned int taac_clks;\n\tunsigned int taac_ns;\n\tunsigned int c_size;\n\tunsigned int r2w_factor;\n\tunsigned int max_dtr;\n\tunsigned int erase_size;\n\tunsigned int wp_grp_size;\n\tunsigned int read_blkbits;\n\tunsigned int write_blkbits;\n\tsector_t capacity;\n\tunsigned int read_partial: 1;\n\tunsigned int read_misalign: 1;\n\tunsigned int write_partial: 1;\n\tunsigned int write_misalign: 1;\n\tunsigned int dsr_imp: 1;\n};\n\nstruct mmc_ext_csd {\n\tu8 rev;\n\tu8 erase_group_def;\n\tu8 sec_feature_support;\n\tu8 rel_sectors;\n\tu8 rel_param;\n\tbool enhanced_rpmb_supported;\n\tu8 part_config;\n\tu8 cache_ctrl;\n\tu8 rst_n_function;\n\tunsigned int part_time;\n\tunsigned int sa_timeout;\n\tunsigned int generic_cmd6_time;\n\tunsigned int power_off_longtime;\n\tu8 power_off_notification;\n\tunsigned int hs_max_dtr;\n\tunsigned int hs200_max_dtr;\n\tunsigned int sectors;\n\tunsigned int hc_erase_size;\n\tunsigned int hc_erase_timeout;\n\tunsigned int sec_trim_mult;\n\tunsigned int sec_erase_mult;\n\tunsigned int trim_timeout;\n\tbool partition_setting_completed;\n\tlong long unsigned int enhanced_area_offset;\n\tunsigned int enhanced_area_size;\n\tunsigned int cache_size;\n\tbool hpi_en;\n\tbool hpi;\n\tunsigned int hpi_cmd;\n\tbool bkops;\n\tbool man_bkops_en;\n\tbool auto_bkops_en;\n\tunsigned int data_sector_size;\n\tunsigned int data_tag_unit_size;\n\tunsigned int boot_ro_lock;\n\tbool boot_ro_lockable;\n\tbool ffu_capable;\n\tbool cmdq_en;\n\tbool cmdq_support;\n\tunsigned int cmdq_depth;\n\tu8 fwrev[8];\n\tu8 raw_exception_status;\n\tu8 raw_partition_support;\n\tu8 raw_rpmb_size_mult;\n\tu8 raw_erased_mem_count;\n\tu8 strobe_support;\n\tu8 raw_ext_csd_structure;\n\tu8 raw_card_type;\n\tu8 raw_driver_strength;\n\tu8 out_of_int_time;\n\tu8 raw_pwr_cl_52_195;\n\tu8 raw_pwr_cl_26_195;\n\tu8 raw_pwr_cl_52_360;\n\tu8 raw_pwr_cl_26_360;\n\tu8 raw_s_a_timeout;\n\tu8 raw_hc_erase_gap_size;\n\tu8 raw_erase_timeout_mult;\n\tu8 raw_hc_erase_grp_size;\n\tu8 raw_boot_mult;\n\tu8 raw_sec_trim_mult;\n\tu8 raw_sec_erase_mult;\n\tu8 raw_sec_feature_support;\n\tu8 raw_trim_mult;\n\tu8 raw_pwr_cl_200_195;\n\tu8 raw_pwr_cl_200_360;\n\tu8 raw_pwr_cl_ddr_52_195;\n\tu8 raw_pwr_cl_ddr_52_360;\n\tu8 raw_pwr_cl_ddr_200_360;\n\tu8 raw_bkops_status;\n\tu8 raw_sectors[4];\n\tu8 pre_eol_info;\n\tu8 device_life_time_est_typ_a;\n\tu8 device_life_time_est_typ_b;\n\tunsigned int feature_support;\n};\n\nstruct sd_scr {\n\tunsigned char sda_vsn;\n\tunsigned char sda_spec3;\n\tunsigned char sda_spec4;\n\tunsigned char sda_specx;\n\tunsigned char bus_widths;\n\tunsigned char cmds;\n};\n\nstruct sd_ssr {\n\tunsigned int au;\n\tunsigned int erase_timeout;\n\tunsigned int erase_offset;\n};\n\nstruct sd_switch_caps {\n\tunsigned int hs_max_dtr;\n\tunsigned int uhs_max_dtr;\n\tunsigned int sd3_bus_mode;\n\tunsigned int sd3_drv_type;\n\tunsigned int sd3_curr_limit;\n};\n\nstruct sd_ext_reg {\n\tu8 fno;\n\tu8 page;\n\tu16 offset;\n\tu8 rev;\n\tu8 feature_enabled;\n\tu8 feature_support;\n};\n\nstruct sd_uhs2_config {\n\tu32 node_id;\n\tu32 n_fcu;\n\tu32 maxblk_len;\n\tu8 n_lanes;\n\tu8 dadr_len;\n\tu8 app_type;\n\tu8 phy_minor_rev;\n\tu8 phy_major_rev;\n\tu8 can_hibernate;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_minor_rev;\n\tu8 link_major_rev;\n\tu8 dev_type;\n\tu8 n_data_gap;\n\tu32 n_fcu_set;\n\tu32 maxblk_len_set;\n\tu8 n_lanes_set;\n\tu8 speed_range_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct sdio_cccr {\n\tunsigned int sdio_vsn;\n\tunsigned int sd_vsn;\n\tunsigned int multi_block: 1;\n\tunsigned int low_speed: 1;\n\tunsigned int wide_bus: 1;\n\tunsigned int high_power: 1;\n\tunsigned int high_speed: 1;\n\tunsigned int disable_cd: 1;\n\tunsigned int enable_async_irq: 1;\n};\n\nstruct sdio_cis {\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int blksize;\n\tunsigned int max_dtr;\n};\n\nstruct mmc_part {\n\tu64 size;\n\tunsigned int part_cfg;\n\tchar name[20];\n\tbool force_ro;\n\tunsigned int area_type;\n};\n\nstruct sdio_func_tuple;\n\nstruct mmc_card {\n\tstruct mmc_host *host;\n\tstruct device dev;\n\tu32 ocr;\n\tunsigned int rca;\n\tunsigned int type;\n\tunsigned int state;\n\tunsigned int quirks;\n\tunsigned int quirk_max_rate;\n\tbool written_flag;\n\tbool reenable_cmdq;\n\tunsigned int erase_size;\n\tunsigned int erase_shift;\n\tunsigned int pref_erase;\n\tunsigned int eg_boundary;\n\tunsigned int erase_arg;\n\tu8 erased_byte;\n\tunsigned int wp_grp_size;\n\tu32 raw_cid[4];\n\tu32 raw_csd[4];\n\tu32 raw_scr[2];\n\tu32 raw_ssr[16];\n\tstruct mmc_cid cid;\n\tstruct mmc_csd csd;\n\tstruct mmc_ext_csd ext_csd;\n\tstruct sd_scr scr;\n\tstruct sd_ssr ssr;\n\tstruct sd_switch_caps sw_caps;\n\tstruct sd_ext_reg ext_power;\n\tstruct sd_ext_reg ext_perf;\n\tstruct sd_uhs2_config uhs2_config;\n\tunsigned int sdio_funcs;\n\tatomic_t sdio_funcs_probed;\n\tstruct sdio_cccr cccr;\n\tstruct sdio_cis cis;\n\tstruct sdio_func *sdio_func[7];\n\tstruct sdio_func *sdio_single_irq;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n\tunsigned int sd_bus_speed;\n\tunsigned int mmc_avail_type;\n\tunsigned int drive_strength;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_part part[7];\n\tunsigned int nr_parts;\n\tstruct workqueue_struct *complete_wq;\n};\n\nstruct mmc_clk_phase {\n\tbool valid;\n\tu16 in_deg;\n\tu16 out_deg;\n};\n\nstruct mmc_clk_phase_map {\n\tstruct mmc_clk_phase phase[11];\n};\n\nstruct mmc_cqe_ops {\n\tint (*cqe_enable)(struct mmc_host *, struct mmc_card *);\n\tvoid (*cqe_disable)(struct mmc_host *);\n\tint (*cqe_request)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_post_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_off)(struct mmc_host *);\n\tint (*cqe_wait_for_idle)(struct mmc_host *);\n\tbool (*cqe_timeout)(struct mmc_host *, struct mmc_request *, bool *);\n\tvoid (*cqe_recovery_start)(struct mmc_host *);\n\tvoid (*cqe_recovery_finish)(struct mmc_host *);\n};\n\nstruct mmc_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct mmc_card *);\n\tvoid (*remove)(struct mmc_card *);\n\tvoid (*shutdown)(struct mmc_card *);\n};\n\nstruct mmc_fixup {\n\tconst char *name;\n\tu64 rev_start;\n\tu64 rev_end;\n\tunsigned int manfid;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char month;\n\tu16 cis_vendor;\n\tu16 cis_device;\n\tunsigned int ext_csd_rev;\n\tconst char *of_compatible;\n\tvoid (*vendor_fixup)(struct mmc_card *, int);\n\tint data;\n};\n\nstruct mmc_gpio {\n\tstruct gpio_desc *ro_gpio;\n\tstruct gpio_desc *cd_gpio;\n\tirq_handler_t cd_gpio_isr;\n\tchar *ro_label;\n\tchar *cd_label;\n\tu32 cd_debounce_delay_ms;\n\tint cd_irq;\n};\n\nstruct sd_uhs2_caps {\n\tu32 dap;\n\tu32 gap;\n\tu32 group_desc;\n\tu32 maxblk_len;\n\tu32 n_fcu;\n\tu8 n_lanes;\n\tu8 addr64;\n\tu8 card_type;\n\tu8 phy_rev;\n\tu8 speed_range;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_rev;\n\tu8 host_type;\n\tu8 n_data_gap;\n\tu32 maxblk_len_set;\n\tu32 n_fcu_set;\n\tu8 n_lanes_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct mmc_ios {\n\tunsigned int clock;\n\tshort unsigned int vdd;\n\tunsigned int power_delay_ms;\n\tunsigned char bus_mode;\n\tunsigned char chip_select;\n\tunsigned char power_mode;\n\tunsigned char bus_width;\n\tunsigned char timing;\n\tunsigned char signal_voltage;\n\tunsigned char vqmmc2_voltage;\n\tunsigned char drv_type;\n\tbool enhanced_strobe;\n};\n\nstruct mmc_slot {\n\tint cd_irq;\n\tbool cd_wake_enabled;\n\tvoid *handler_priv;\n};\n\nstruct mmc_supply {\n\tstruct regulator *vmmc;\n\tstruct regulator *vqmmc;\n\tstruct regulator *vqmmc2;\n\tstruct notifier_block vmmc_nb;\n\tstruct work_struct uv_work;\n};\n\nstruct mmc_host_ops;\n\nstruct mmc_pwrseq;\n\nstruct mmc_host {\n\tstruct device *parent;\n\tstruct device class_dev;\n\tint index;\n\tconst struct mmc_host_ops *ops;\n\tstruct mmc_pwrseq *pwrseq;\n\tunsigned int f_min;\n\tunsigned int f_max;\n\tunsigned int f_init;\n\tu32 ocr_avail;\n\tu32 ocr_avail_sdio;\n\tu32 ocr_avail_sd;\n\tu32 ocr_avail_mmc;\n\tstruct wakeup_source *ws;\n\tu32 max_current_330;\n\tu32 max_current_300;\n\tu32 max_current_180;\n\tu32 caps;\n\tu32 caps2;\n\tbool uhs2_sd_tran;\n\tbool uhs2_app_cmd;\n\tstruct sd_uhs2_caps uhs2_caps;\n\tint fixed_drv_type;\n\tmmc_pm_flag_t pm_caps;\n\tunsigned int max_seg_size;\n\tshort unsigned int max_segs;\n\tshort unsigned int unused;\n\tunsigned int max_req_size;\n\tunsigned int max_blk_size;\n\tunsigned int max_blk_count;\n\tunsigned int max_busy_timeout;\n\tspinlock_t lock;\n\tstruct mmc_ios ios;\n\tbool claimed;\n\tunsigned int use_spi_crc: 1;\n\tunsigned int doing_init_tune: 1;\n\tunsigned int doing_retune: 1;\n\tunsigned int retune_crc_disable: 1;\n\tunsigned int can_dma_map_merge: 1;\n\tunsigned int vqmmc_enabled: 1;\n\tunsigned int undervoltage: 1;\n\tint rescan_disable;\n\tint rescan_entered;\n\tbool can_retune;\n\tbool retune_now;\n\tbool retune_paused;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct timer_list retune_timer;\n\tbool trigger_card_event;\n\tstruct mmc_card *card;\n\twait_queue_head_t wq;\n\tstruct mmc_ctx *claimer;\n\tint claim_cnt;\n\tstruct mmc_ctx default_ctx;\n\tstruct delayed_work detect;\n\tint detect_change;\n\tstruct mmc_slot slot;\n\tconst struct mmc_bus_ops *bus_ops;\n\tunsigned int sdio_irqs;\n\tstruct task_struct *sdio_irq_thread;\n\tstruct work_struct sdio_irq_work;\n\tbool sdio_irq_pending;\n\tatomic_t sdio_irq_thread_abort;\n\tmmc_pm_flag_t pm_flags;\n\tstruct led_trigger *led;\n\tbool regulator_enabled;\n\tstruct mmc_supply supply;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_request *ongoing_mrq;\n\tunsigned int actual_clock;\n\tunsigned int slotno;\n\tint dsr_req;\n\tu32 dsr;\n\tconst struct mmc_cqe_ops *cqe_ops;\n\tvoid *cqe_private;\n\tint cqe_qdepth;\n\tbool cqe_enabled;\n\tbool cqe_on;\n\tbool hsq_enabled;\n\tint hsq_depth;\n\tu32 err_stats[15];\n\tu32 max_sd_hs_hz;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct mmc_host_ops {\n\tvoid (*post_req)(struct mmc_host *, struct mmc_request *, int);\n\tvoid (*pre_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*request)(struct mmc_host *, struct mmc_request *);\n\tint (*request_atomic)(struct mmc_host *, struct mmc_request *);\n\tvoid (*set_ios)(struct mmc_host *, struct mmc_ios *);\n\tint (*get_ro)(struct mmc_host *);\n\tint (*get_cd)(struct mmc_host *);\n\tvoid (*enable_sdio_irq)(struct mmc_host *, int);\n\tvoid (*ack_sdio_irq)(struct mmc_host *);\n\tvoid (*init_card)(struct mmc_host *, struct mmc_card *);\n\tint (*start_signal_voltage_switch)(struct mmc_host *, struct mmc_ios *);\n\tint (*card_busy)(struct mmc_host *);\n\tint (*execute_tuning)(struct mmc_host *, u32);\n\tint (*prepare_hs400_tuning)(struct mmc_host *, struct mmc_ios *);\n\tint (*execute_hs400_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*prepare_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*execute_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*hs400_prepare_ddr)(struct mmc_host *);\n\tvoid (*hs400_downgrade)(struct mmc_host *);\n\tvoid (*hs400_complete)(struct mmc_host *);\n\tvoid (*hs400_enhanced_strobe)(struct mmc_host *, struct mmc_ios *);\n\tint (*select_drive_strength)(struct mmc_card *, unsigned int, int, int, int *);\n\tvoid (*card_hw_reset)(struct mmc_host *);\n\tvoid (*card_event)(struct mmc_host *);\n\tint (*multi_io_quirk)(struct mmc_card *, unsigned int, int);\n\tint (*init_sd_express)(struct mmc_host *, struct mmc_ios *);\n\tint (*uhs2_control)(struct mmc_host *, enum sd_uhs2_operation);\n};\n\nstruct mmc_ioc_multi_cmd {\n\t__u64 num_of_cmds;\n\tstruct mmc_ioc_cmd cmds[0];\n};\n\nstruct mmc_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct mmc_pwrseq_ops;\n\nstruct mmc_pwrseq {\n\tconst struct mmc_pwrseq_ops *ops;\n\tstruct device *dev;\n\tstruct list_head pwrseq_node;\n\tstruct module *owner;\n};\n\nstruct mmc_pwrseq_emmc {\n\tstruct mmc_pwrseq pwrseq;\n\tstruct notifier_block reset_nb;\n\tstruct gpio_desc *reset_gpio;\n};\n\nstruct mmc_pwrseq_ops {\n\tvoid (*pre_power_on)(struct mmc_host *);\n\tvoid (*post_power_on)(struct mmc_host *);\n\tvoid (*power_off)(struct mmc_host *);\n\tvoid (*reset)(struct mmc_host *);\n};\n\nstruct mmc_pwrseq_simple {\n\tstruct mmc_pwrseq pwrseq;\n\tbool clk_enabled;\n\tu32 post_power_on_delay_ms;\n\tu32 power_off_delay_us;\n\tstruct clk *ext_clk;\n\tstruct gpio_descs *reset_gpios;\n\tstruct reset_control *reset_ctrl;\n};\n\nstruct mmc_queue_req {\n\tstruct mmc_blk_request brq;\n\tstruct scatterlist *sg;\n\tenum mmc_drv_op drv_op;\n\tint drv_op_result;\n\tvoid *drv_op_data;\n\tunsigned int ioc_count;\n\tint retries;\n};\n\nstruct rpmb_dev;\n\nstruct mmc_rpmb_data {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tunsigned int part_index;\n\tstruct mmc_blk_data *md;\n\tstruct rpmb_dev *rdev;\n\tstruct list_head node;\n};\n\nstruct spi_delay {\n\tu16 value;\n\tu8 unit;\n};\n\nstruct spi_transfer {\n\tconst void *tx_buf;\n\tvoid *rx_buf;\n\tunsigned int len;\n\tu16 error;\n\tbool tx_sg_mapped;\n\tbool rx_sg_mapped;\n\tstruct sg_table tx_sg;\n\tstruct sg_table rx_sg;\n\tdma_addr_t tx_dma;\n\tdma_addr_t rx_dma;\n\tunsigned int dummy_data: 1;\n\tunsigned int cs_off: 1;\n\tunsigned int cs_change: 1;\n\tunsigned int tx_nbits: 4;\n\tunsigned int rx_nbits: 4;\n\tunsigned int multi_lane_mode: 2;\n\tunsigned int timestamped: 1;\n\tbool dtr_mode;\n\tu8 bits_per_word;\n\tstruct spi_delay delay;\n\tstruct spi_delay cs_change_delay;\n\tstruct spi_delay word_delay;\n\tu32 speed_hz;\n\tu32 effective_speed_hz;\n\tunsigned int offload_flags;\n\tunsigned int ptp_sts_word_pre;\n\tunsigned int ptp_sts_word_post;\n\tstruct ptp_system_timestamp *ptp_sts;\n\tstruct list_head transfer_list;\n};\n\nstruct spi_device;\n\nstruct spi_offload;\n\nstruct spi_message {\n\tstruct list_head transfers;\n\tstruct spi_device *spi;\n\tbool pre_optimized;\n\tbool optimized;\n\tbool prepared;\n\tint status;\n\tvoid (*complete)(void *);\n\tvoid *context;\n\tunsigned int frame_length;\n\tunsigned int actual_length;\n\tstruct list_head queue;\n\tvoid *state;\n\tvoid *opt_state;\n\tstruct spi_offload *offload;\n\tstruct list_head resources;\n};\n\nstruct mmc_spi_platform_data;\n\nstruct scratch;\n\nstruct mmc_spi_host {\n\tstruct mmc_host *mmc;\n\tstruct spi_device *spi;\n\tunsigned char power_mode;\n\tu16 powerup_msecs;\n\tstruct mmc_spi_platform_data *pdata;\n\tstruct spi_transfer token;\n\tstruct spi_transfer t;\n\tstruct spi_transfer crc;\n\tstruct spi_transfer early_status;\n\tstruct spi_message m;\n\tstruct spi_transfer status;\n\tstruct spi_message readback;\n\tstruct scratch *data;\n\tvoid *ones;\n};\n\nstruct mmc_spi_platform_data {\n\tint (*init)(struct device *, irqreturn_t (*)(int, void *), void *);\n\tvoid (*exit)(struct device *, void *);\n\tlong unsigned int caps;\n\tlong unsigned int caps2;\n\tu16 detect_delay;\n\tu16 powerup_msecs;\n\tu32 ocr_mask;\n\tvoid (*setpower)(struct device *, unsigned int);\n};\n\nstruct mminit_pfnnid_cache {\n\tlong unsigned int last_start;\n\tlong unsigned int last_end;\n\tint last_nid;\n};\n\nstruct mmiowb_state {\n\tu16 nesting_count;\n\tu16 mmiowb_pending;\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct encoded_page;\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct encoded_page *encoded_pages[0];\n};\n\nstruct mmu_table_batch;\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tstruct mmu_table_batch *batch;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n};\n\nstruct mmu_interval_notifier_ops;\n\nstruct mmu_interval_notifier {\n\tstruct interval_tree_node interval_tree;\n\tconst struct mmu_interval_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct hlist_node deferred_item;\n\tlong unsigned int invalidate_seq;\n};\n\nstruct mmu_notifier_range;\n\nstruct mmu_interval_notifier_ops {\n\tbool (*invalidate)(struct mmu_interval_notifier *, const struct mmu_notifier_range *, long unsigned int);\n};\n\nstruct mmu_notifier_ops;\n\nstruct mmu_notifier {\n\tstruct hlist_node hlist;\n\tconst struct mmu_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct callback_head rcu;\n\tunsigned int users;\n};\n\nstruct mmu_notifier_ops {\n\tvoid (*release)(struct mmu_notifier *, struct mm_struct *);\n\tint (*clear_flush_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*clear_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*test_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int);\n\tint (*invalidate_range_start)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range_end)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*arch_invalidate_secondary_tlbs)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tstruct mmu_notifier * (*alloc_notifier)(struct mm_struct *);\n\tvoid (*free_notifier)(struct mmu_notifier *);\n};\n\nstruct mmu_notifier_range {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int flags;\n\tenum mmu_notifier_event event;\n\tvoid *owner;\n};\n\nstruct mmu_notifier_subscriptions {\n\tstruct hlist_head list;\n\tbool has_itree;\n\tspinlock_t lock;\n\tlong unsigned int invalidate_seq;\n\tlong unsigned int active_invalidate_ranges;\n\tstruct rb_root_cached itree;\n\twait_queue_head_t wq;\n\tstruct hlist_head deferred_list;\n};\n\nstruct mmu_table_batch {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tvoid *tables[0];\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 64;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct mod_arch_specific {};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf64_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct mode_page_header {\n\t__be16 mode_data_length;\n\t__u8 medium_type;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 reserved3;\n\t__be16 desc_length;\n};\n\nstruct modesel_head {\n\t__u8 reserved1;\n\t__u8 medium;\n\t__u8 reserved2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_of_blocks_hi;\n\t__u8 number_of_blocks_med;\n\t__u8 number_of_blocks_lo;\n\t__u8 reserved3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n\tstruct mod_tree_node mtn;\n};\n\ntypedef struct tracepoint * const tracepoint_ptr_t;\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_event_call;\n\nstruct trace_eval_map;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[56];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_string {\n\tstruct list_head next;\n\tstruct module *module;\n\tchar *str;\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct mountres {\n\tint errno;\n\tstruct nfs_fh *fh;\n\tunsigned int *auth_count;\n\trpc_authflavor_t *auth_flavors;\n};\n\nstruct mousedev_hw_data {\n\tint dx;\n\tint dy;\n\tint dz;\n\tint x;\n\tint y;\n\tint abs_event;\n\tlong unsigned int buttons;\n};\n\nstruct mousedev {\n\tint open;\n\tstruct input_handle handle;\n\twait_queue_head_t wait;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n\tstruct list_head mixdev_node;\n\tbool opened_by_mixdev;\n\tstruct mousedev_hw_data packet;\n\tunsigned int pkt_count;\n\tint old_x[4];\n\tint old_y[4];\n\tint frac_dx;\n\tint frac_dy;\n\tlong unsigned int touch;\n\tint (*open_device)(struct mousedev *);\n\tvoid (*close_device)(struct mousedev *);\n};\n\nstruct mousedev_motion {\n\tint dx;\n\tint dy;\n\tint dz;\n\tlong unsigned int buttons;\n};\n\nstruct mousedev_client {\n\tstruct fasync_struct *fasync;\n\tstruct mousedev *mousedev;\n\tstruct list_head node;\n\tstruct mousedev_motion packets[16];\n\tunsigned int head;\n\tunsigned int tail;\n\tspinlock_t packet_lock;\n\tint pos_x;\n\tint pos_y;\n\tu8 ps2[6];\n\tunsigned char ready;\n\tunsigned char buffer;\n\tunsigned char bufsiz;\n\tunsigned char imexseq;\n\tunsigned char impsseq;\n\tenum mousedev_emul mode;\n\tlong unsigned int last_buttons;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tunsigned int can_map: 1;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tloff_t end_pos;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n\tunsigned int journalled_more_data: 1;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpfs_ccc_data {\n\tvoid **pll_base;\n\tstruct device *dev;\n\tstruct clk_hw_onecell_data hw_data;\n};\n\nstruct mpfs_ccc_out_hw_clock {\n\tstruct clk_divider divider;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n};\n\nstruct mpfs_ccc_pll_hw_clock {\n\tvoid *base;\n\tconst char *name;\n\tconst struct clk_parent_data *parents;\n\tunsigned int id;\n\tu32 reg_offset;\n\tu32 shift;\n\tu32 width;\n\tu32 flags;\n\tstruct clk_hw hw;\n\tstruct clk_init_data init;\n};\n\nstruct mpfs_cfg_clock {\n\tstruct regmap *map;\n\tconst struct clk_div_table *table;\n\tu8 map_offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n};\n\nstruct mpfs_cfg_hw_clock {\n\tstruct clk_hw hw;\n\tstruct mpfs_cfg_clock cfg;\n\tunsigned int id;\n};\n\nstruct mpfs_clock_data {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tvoid *base;\n\tvoid *msspll_base;\n\tstruct clk_hw_onecell_data hw_data;\n};\n\nstruct mpfs_msspll_hw_clock {\n\tvoid *base;\n\tstruct clk_hw hw;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n\tu32 shift;\n\tu32 width;\n\tu32 flags;\n};\n\nstruct mpfs_msspll_out_hw_clock {\n\tvoid *base;\n\tstruct clk_divider output;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n};\n\nstruct mpfs_periph_clock {\n\tstruct regmap *map;\n\tu8 map_offset;\n\tu8 shift;\n};\n\nstruct mpfs_periph_hw_clock {\n\tstruct clk_hw hw;\n\tstruct mpfs_periph_clock periph;\n\tunsigned int id;\n};\n\nstruct mpfs_reset {\n\tstruct regmap *regmap;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mptcp_out_options {};\n\nstruct mptcp_sock {};\n\nstruct mpxy_local {\n\tvoid *shmem;\n\tphys_addr_t shmem_phys_addr;\n\tbool shmem_active;\n};\n\nstruct mpxy_mbox_channel;\n\nstruct mpxy_mbox {\n\tstruct device *dev;\n\tu32 channel_count;\n\tstruct mpxy_mbox_channel *channels;\n\tu32 msi_count;\n\tstruct mpxy_mbox_channel **msi_index_to_channel;\n\tstruct mbox_controller controller;\n};\n\nstruct sbi_mpxy_msi_info {\n\tu32 msi_addr_lo;\n\tu32 msi_addr_hi;\n\tu32 msi_data;\n};\n\nstruct sbi_mpxy_channel_attrs {\n\tu32 msg_proto_id;\n\tu32 msg_proto_version;\n\tu32 msg_max_len;\n\tu32 msg_send_timeout;\n\tu32 msg_completion_timeout;\n\tu32 capability;\n\tu32 sse_event_id;\n\tu32 msi_control;\n\tstruct sbi_mpxy_msi_info msi_info;\n\tu32 events_state_ctrl;\n};\n\nstruct sbi_mpxy_rpmi_channel_attrs {\n\tu32 servicegroup_id;\n\tu32 servicegroup_version;\n\tu32 impl_id;\n\tu32 impl_version;\n};\n\nstruct sbi_mpxy_notification_data;\n\nstruct mpxy_mbox_channel {\n\tstruct mpxy_mbox *mbox;\n\tu32 channel_id;\n\tstruct sbi_mpxy_channel_attrs attrs;\n\tstruct sbi_mpxy_rpmi_channel_attrs rpmi_attrs;\n\tstruct sbi_mpxy_notification_data *notif;\n\tu32 max_xfer_len;\n\tbool have_events_state;\n\tu32 msi_index;\n\tu32 msi_irq;\n\tbool started;\n};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct mqueue_fs_context {\n\tstruct ipc_namespace *ipc_ns;\n\tbool newns;\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[12];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct posix_msg_tree_node;\n\nstruct mqueue_inode_info {\n\tspinlock_t lock;\n\tstruct inode vfs_inode;\n\twait_queue_head_t wait_q;\n\tstruct rb_root msg_tree;\n\tstruct rb_node *msg_tree_rightmost;\n\tstruct posix_msg_tree_node *node_cache;\n\tstruct mq_attr attr;\n\tstruct sigevent notify;\n\tstruct pid *notify_owner;\n\tu32 notify_self_exec_id;\n\tstruct user_namespace *notify_user_ns;\n\tstruct ucounts *ucounts;\n\tstruct sock *notify_sock;\n\tstruct sk_buff *notify_cookie;\n\tstruct ext_wait_queue e_wait_q[2];\n\tlong unsigned int qsize;\n};\n\nstruct mrw_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u8 write: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n\t__u8 reserved4;\n\t__u8 reserved5;\n};\n\nstruct ms_data {\n\tlong unsigned int quirks;\n\tstruct hid_device *hdev;\n\tstruct work_struct ff_worker;\n\t__u8 strong;\n\t__u8 weak;\n\tvoid *output_report_dmabuf;\n};\n\nstruct msdos_dir_entry {\n\t__u8 name[11];\n\t__u8 attr;\n\t__u8 lcase;\n\t__u8 ctime_cs;\n\t__le16 ctime;\n\t__le16 cdate;\n\t__le16 adate;\n\t__le16 starthi;\n\t__le16 time;\n\t__le16 date;\n\t__le16 start;\n\t__le32 size;\n};\n\nstruct msdos_dir_slot {\n\t__u8 id;\n\t__u8 name0_4[10];\n\t__u8 attr;\n\t__u8 reserved;\n\t__u8 alias_checksum;\n\t__u8 name5_10[12];\n\t__le16 start;\n\t__u8 name11_12[4];\n};\n\nstruct msdos_inode_info {\n\tspinlock_t cache_lru_lock;\n\tstruct list_head cache_lru;\n\tint nr_caches;\n\tunsigned int cache_valid_id;\n\tloff_t mmu_private;\n\tint i_start;\n\tint i_logstart;\n\tint i_attrs;\n\tloff_t i_pos;\n\tstruct hlist_node i_fat_hash;\n\tstruct hlist_node i_dir_hash;\n\tstruct rw_semaphore truncate_lock;\n\tstruct timespec64 i_crtime;\n\tstruct inode vfs_inode;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct msdos_sb_info {\n\tshort unsigned int sec_per_clus;\n\tshort unsigned int cluster_bits;\n\tunsigned int cluster_size;\n\tunsigned char fats;\n\tunsigned char fat_bits;\n\tshort unsigned int fat_start;\n\tlong unsigned int fat_length;\n\tlong unsigned int dir_start;\n\tshort unsigned int dir_entries;\n\tlong unsigned int data_start;\n\tlong unsigned int max_cluster;\n\tlong unsigned int root_cluster;\n\tlong unsigned int fsinfo_sector;\n\tstruct mutex fat_lock;\n\tstruct mutex nfs_build_inode_lock;\n\tstruct mutex s_lock;\n\tunsigned int prev_free;\n\tunsigned int free_clusters;\n\tunsigned int free_clus_valid;\n\tstruct fat_mount_options options;\n\tstruct nls_table *nls_disk;\n\tstruct nls_table *nls_io;\n\tconst void *dir_ops;\n\tint dir_per_block;\n\tint dir_per_block_bits;\n\tunsigned int vol_id;\n\tint fatent_shift;\n\tconst struct fatent_operations *fatent_ops;\n\tstruct inode *fat_inode;\n\tstruct inode *fsinfo_inode;\n\tstruct ratelimit_state ratelimit;\n\tspinlock_t inode_hash_lock;\n\tstruct hlist_head inode_hashtable[256];\n\tspinlock_t dir_hash_lock;\n\tstruct hlist_head dir_hashtable[256];\n\tunsigned int dirty;\n\tstruct callback_head rcu;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_security_struct {\n\tu32 sid;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong int msg_stime;\n\tlong int msg_rtime;\n\tlong int msg_ctime;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct mtd_blktrans_ops;\n\nstruct mtd_blktrans_dev {\n\tstruct mtd_blktrans_ops *tr;\n\tstruct list_head list;\n\tstruct mtd_info *mtd;\n\tstruct mutex lock;\n\tint devnum;\n\tbool bg_stop;\n\tlong unsigned int size;\n\tint readonly;\n\tint open;\n\tstruct kref ref;\n\tstruct gendisk *disk;\n\tstruct attribute_group *disk_attributes;\n\tstruct request_queue *rq;\n\tstruct list_head rq_list;\n\tstruct blk_mq_tag_set *tag_set;\n\tspinlock_t queue_lock;\n\tvoid *priv;\n\tbool writable;\n};\n\nstruct mtd_blktrans_ops {\n\tchar *name;\n\tint major;\n\tint part_bits;\n\tint blksize;\n\tint blkshift;\n\tint (*readsect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*writesect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*discard)(struct mtd_blktrans_dev *, long unsigned int, unsigned int);\n\tvoid (*background)(struct mtd_blktrans_dev *);\n\tint (*getgeo)(struct mtd_blktrans_dev *, struct hd_geometry *);\n\tint (*flush)(struct mtd_blktrans_dev *);\n\tint (*open)(struct mtd_blktrans_dev *);\n\tvoid (*release)(struct mtd_blktrans_dev *);\n\tvoid (*add_mtd)(struct mtd_blktrans_ops *, struct mtd_info *);\n\tvoid (*remove_dev)(struct mtd_blktrans_dev *);\n\tstruct list_head devs;\n\tstruct list_head list;\n\tstruct module *owner;\n};\n\nstruct mtd_chip_driver {\n\tstruct mtd_info * (*probe)(struct map_info *);\n\tvoid (*destroy)(struct mtd_info *);\n\tstruct module *module;\n\tchar *name;\n\tstruct list_head list;\n};\n\nstruct mtd_ecc_stats {\n\t__u32 corrected;\n\t__u32 failed;\n\t__u32 badblocks;\n\t__u32 bbtblocks;\n};\n\nstruct mtd_debug_info {\n\tstruct dentry *dfs_dir;\n};\n\nstruct mtd_part {\n\tstruct list_head node;\n\tu64 offset;\n\tu64 size;\n\tu32 flags;\n};\n\nstruct mtd_master {\n\tstruct mutex partitions_lock;\n\tstruct mutex chrdev_lock;\n\tunsigned int suspended: 1;\n};\n\nstruct mtd_ooblayout_ops;\n\nstruct mtd_pairing_scheme;\n\nstruct mtd_erase_region_info;\n\nstruct mtd_oob_ops;\n\nstruct otp_info;\n\nstruct nvmem_device;\n\nstruct mtd_info {\n\tu_char type;\n\tuint32_t flags;\n\tuint64_t size;\n\tuint32_t erasesize;\n\tuint32_t writesize;\n\tuint32_t writebufsize;\n\tuint32_t oobsize;\n\tuint32_t oobavail;\n\tunsigned int erasesize_shift;\n\tunsigned int writesize_shift;\n\tunsigned int erasesize_mask;\n\tunsigned int writesize_mask;\n\tunsigned int bitflip_threshold;\n\tconst char *name;\n\tint index;\n\tconst struct mtd_ooblayout_ops *ooblayout;\n\tconst struct mtd_pairing_scheme *pairing;\n\tunsigned int ecc_step_size;\n\tunsigned int ecc_strength;\n\tint numeraseregions;\n\tstruct mtd_erase_region_info *eraseregions;\n\tint (*_erase)(struct mtd_info *, struct erase_info *);\n\tint (*_point)(struct mtd_info *, loff_t, size_t, size_t *, void **, resource_size_t *);\n\tint (*_unpoint)(struct mtd_info *, loff_t, size_t);\n\tint (*_read)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_panic_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_read_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_write_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_get_fact_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_fact_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_get_user_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_lock_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_erase_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_writev)(struct mtd_info *, const struct kvec *, long unsigned int, loff_t, size_t *);\n\tvoid (*_sync)(struct mtd_info *);\n\tint (*_lock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_unlock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_is_locked)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_block_isreserved)(struct mtd_info *, loff_t);\n\tint (*_block_isbad)(struct mtd_info *, loff_t);\n\tint (*_block_markbad)(struct mtd_info *, loff_t);\n\tint (*_max_bad_blocks)(struct mtd_info *, loff_t, size_t);\n\tint (*_suspend)(struct mtd_info *);\n\tvoid (*_resume)(struct mtd_info *);\n\tvoid (*_reboot)(struct mtd_info *);\n\tint (*_get_device)(struct mtd_info *);\n\tvoid (*_put_device)(struct mtd_info *);\n\tbool oops_panic_write;\n\tstruct notifier_block reboot_notifier;\n\tstruct mtd_ecc_stats ecc_stats;\n\tint subpage_sft;\n\tvoid *priv;\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct kref refcnt;\n\tstruct mtd_debug_info dbg;\n\tstruct nvmem_device *nvmem;\n\tstruct nvmem_device *otp_user_nvmem;\n\tstruct nvmem_device *otp_factory_nvmem;\n\tstruct mtd_info *parent;\n\tstruct list_head partitions;\n\tstruct mtd_part part;\n\tstruct mtd_master master;\n};\n\nstruct mtd_concat {\n\tstruct mtd_info mtd;\n\tint num_subdev;\n\tstruct mtd_info **subdev;\n};\n\nstruct mtd_erase_region_info {\n\tuint64_t offset;\n\tuint32_t erasesize;\n\tuint32_t numblocks;\n\tlong unsigned int *lockmap;\n};\n\nstruct mtd_file_info {\n\tstruct mtd_info *mtd;\n\tenum mtd_file_modes mode;\n};\n\nstruct mtd_info_user {\n\t__u8 type;\n\t__u32 flags;\n\t__u32 size;\n\t__u32 erasesize;\n\t__u32 writesize;\n\t__u32 oobsize;\n\t__u64 padding;\n};\n\nstruct mtd_notifier {\n\tvoid (*add)(struct mtd_info *);\n\tvoid (*remove)(struct mtd_info *);\n\tstruct list_head list;\n};\n\nstruct mtd_oob_buf {\n\t__u32 start;\n\t__u32 length;\n\tunsigned char *ptr;\n};\n\nstruct mtd_oob_buf32 {\n\tu_int32_t start;\n\tu_int32_t length;\n\tcompat_caddr_t ptr;\n};\n\nstruct mtd_oob_buf64 {\n\t__u64 start;\n\t__u32 pad;\n\t__u32 length;\n\t__u64 usr_ptr;\n};\n\nstruct mtd_req_stats;\n\nstruct mtd_oob_ops {\n\tunsigned int mode;\n\tsize_t len;\n\tsize_t retlen;\n\tsize_t ooblen;\n\tsize_t oobretlen;\n\tuint32_t ooboffs;\n\tuint8_t *datbuf;\n\tuint8_t *oobbuf;\n\tstruct mtd_req_stats *stats;\n};\n\nstruct mtd_oob_region {\n\tu32 offset;\n\tu32 length;\n};\n\nstruct mtd_ooblayout_ops {\n\tint (*ecc)(struct mtd_info *, int, struct mtd_oob_region *);\n\tint (*free)(struct mtd_info *, int, struct mtd_oob_region *);\n};\n\nstruct mtd_pairing_info {\n\tint pair;\n\tint group;\n};\n\nstruct mtd_pairing_scheme {\n\tint ngroups;\n\tint (*get_info)(struct mtd_info *, int, struct mtd_pairing_info *);\n\tint (*get_wunit)(struct mtd_info *, const struct mtd_pairing_info *);\n};\n\nstruct mtd_part_parser_data;\n\nstruct mtd_part_parser {\n\tstruct list_head list;\n\tstruct module *owner;\n\tconst char *name;\n\tconst struct of_device_id *of_match_table;\n\tint (*parse_fn)(struct mtd_info *, const struct mtd_partition **, struct mtd_part_parser_data *);\n\tvoid (*cleanup)(const struct mtd_partition *, int);\n};\n\nstruct mtd_part_parser_data {\n\tlong unsigned int origin;\n};\n\nstruct mtd_partition {\n\tconst char *name;\n\tconst char * const *types;\n\tuint64_t size;\n\tuint64_t offset;\n\tuint32_t mask_flags;\n\tuint32_t add_flags;\n\tstruct device_node *of_node;\n};\n\nstruct mtd_partitions {\n\tconst struct mtd_partition *parts;\n\tint nr_parts;\n\tconst struct mtd_part_parser *parser;\n};\n\nstruct mtd_read_req_ecc_stats {\n\t__u32 uncorrectable_errors;\n\t__u32 corrected_bitflips;\n\t__u32 max_bitflips;\n};\n\nstruct mtd_read_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n\tstruct mtd_read_req_ecc_stats ecc_stats;\n};\n\nstruct mtd_req_stats {\n\tunsigned int uncorrectable_errors;\n\tunsigned int corrected_bitflips;\n\tunsigned int max_bitflips;\n};\n\nstruct mtd_write_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n};\n\nstruct mtdblk_dev {\n\tstruct mtd_blktrans_dev mbd;\n\tint count;\n\tstruct mutex cache_mutex;\n\tunsigned char *cache_data;\n\tlong unsigned int cache_offset;\n\tunsigned int cache_size;\n\tenum {\n\t\tSTATE_EMPTY = 0,\n\t\tSTATE_CLEAN = 1,\n\t\tSTATE_DIRTY = 2,\n\t} cache_state;\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multi_transaction {\n\tstruct kref count;\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\nstruct my_u0 {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u1 {\n\t__le64 a;\n\t__le64 b;\n\t__le64 c;\n\t__le64 d;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[4];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[64];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct nand_oobfree {\n\t__u32 offset;\n\t__u32 length;\n};\n\nstruct nand_ecclayout_user {\n\t__u32 eccbytes;\n\t__u32 eccpos[64];\n\t__u32 oobavail;\n\tstruct nand_oobfree oobfree[8];\n};\n\nstruct nand_oobinfo {\n\t__u32 useecc;\n\t__u32 eccbytes;\n\t__u32 oobfree[16];\n\t__u32 eccpos[32];\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u32 offset;\n\t__u32 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct nat_keepalive {\n\tstruct net *net;\n\tu16 family;\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\t__u32 smark;\n};\n\nstruct nat_keepalive_work_ctx {\n\ttime64_t next_run;\n\ttime64_t now;\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n};\n\nstruct nd_namespace_common;\n\nstruct nd_btt {\n\tstruct device dev;\n\tstruct nd_namespace_common *ndns;\n\tstruct btt *btt;\n\tlong unsigned int lbasize;\n\tu64 size;\n\tuuid_t *uuid;\n\tint id;\n\tint initial_offset;\n\tu16 version_major;\n\tu16 version_minor;\n};\n\nstruct nd_cmd_ars_cap {\n\t__u64 address;\n\t__u64 length;\n\t__u32 status;\n\t__u32 max_ars_out;\n\t__u32 clear_err_unit;\n\t__u16 flags;\n\t__u16 reserved;\n};\n\nstruct nd_cmd_clear_error {\n\t__u64 address;\n\t__u64 length;\n\t__u32 status;\n\t__u8 reserved[4];\n\t__u64 cleared;\n};\n\nstruct nd_cmd_desc {\n\tint in_num;\n\tint out_num;\n\tu32 in_sizes[5];\n\tint out_sizes[5];\n};\n\nstruct nd_cmd_get_config_data_hdr {\n\t__u32 in_offset;\n\t__u32 in_length;\n\t__u32 status;\n\t__u8 out_buf[0];\n};\n\nstruct nd_cmd_get_config_size {\n\t__u32 status;\n\t__u32 config_size;\n\t__u32 max_xfer;\n};\n\nstruct nd_cmd_pkg {\n\t__u64 nd_family;\n\t__u64 nd_command;\n\t__u32 nd_size_in;\n\t__u32 nd_size_out;\n\t__u32 nd_reserved2[9];\n\t__u32 nd_fw_size;\n\tunsigned char nd_payload[0];\n};\n\nstruct nd_cmd_set_config_hdr {\n\t__u32 in_offset;\n\t__u32 in_length;\n\t__u8 in_buf[0];\n};\n\nstruct nd_cmd_vendor_hdr {\n\t__u32 opcode;\n\t__u32 in_length;\n\t__u8 in_buf[0];\n};\n\nstruct nd_pfn_sb;\n\nstruct nd_pfn {\n\tint id;\n\tuuid_t *uuid;\n\tstruct device dev;\n\tlong unsigned int align;\n\tlong unsigned int npfns;\n\tenum nd_pfn_mode mode;\n\tstruct nd_pfn_sb *pfn_sb;\n\tstruct nd_namespace_common *ndns;\n};\n\nstruct nd_dax {\n\tstruct nd_pfn nd_pfn;\n};\n\nstruct nd_device_driver {\n\tstruct device_driver drv;\n\tlong unsigned int type;\n\tint (*probe)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tvoid (*notify)(struct device *, enum nvdimm_event);\n};\n\nstruct nd_gen_sb {\n\tchar reserved[4088];\n\t__le64 checksum;\n};\n\nstruct nd_interleave_set {\n\tu64 cookie1;\n\tu64 cookie2;\n\tu64 altcookie;\n\tguid_t type_guid;\n};\n\nstruct nd_namespace_label;\n\nstruct nd_label_ent {\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tstruct nd_namespace_label *label;\n};\n\nstruct nd_label_id {\n\tchar id[50];\n};\n\nstruct nvdimm;\n\nstruct nvdimm_drvdata;\n\nstruct nd_mapping {\n\tstruct nvdimm *nvdimm;\n\tu64 start;\n\tu64 size;\n\tint position;\n\tstruct list_head labels;\n\tstruct mutex lock;\n\tstruct nvdimm_drvdata *ndd;\n};\n\nstruct nd_mapping_desc {\n\tstruct nvdimm *nvdimm;\n\tu64 start;\n\tu64 size;\n\tint position;\n};\n\nstruct nd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\t__u8 opt[0];\n};\n\nstruct nd_namespace_common {\n\tint force_raw;\n\tstruct device dev;\n\tstruct device *claim;\n\tenum nvdimm_claim_class claim_class;\n\tint (*rw_bytes)(struct nd_namespace_common *, resource_size_t, void *, size_t, int, long unsigned int);\n};\n\nstruct nd_namespace_index {\n\tu8 sig[16];\n\tu8 flags[3];\n\tu8 labelsize;\n\t__le32 seq;\n\t__le64 myoff;\n\t__le64 mysize;\n\t__le64 otheroff;\n\t__le64 labeloff;\n\t__le32 nslot;\n\t__le16 major;\n\t__le16 minor;\n\t__le64 checksum;\n\tu8 free[0];\n};\n\nstruct nd_namespace_io {\n\tstruct nd_namespace_common common;\n\tstruct resource res;\n\tresource_size_t size;\n\tvoid *addr;\n\tstruct badblocks bb;\n};\n\nstruct nvdimm_cxl_label {\n\tu8 type[16];\n\tu8 uuid[16];\n\tu8 name[64];\n\t__le32 flags;\n\t__le16 nrange;\n\t__le16 position;\n\t__le64 dpa;\n\t__le64 rawsize;\n\t__le32 slot;\n\t__le32 align;\n\tu8 region_uuid[16];\n\tu8 abstraction_uuid[16];\n\t__le16 lbasize;\n\tu8 reserved[86];\n\t__le64 checksum;\n};\n\nstruct nvdimm_efi_label {\n\tu8 uuid[16];\n\tu8 name[64];\n\t__le32 flags;\n\t__le16 nlabel;\n\t__le16 position;\n\t__le64 isetcookie;\n\t__le64 lbasize;\n\t__le64 dpa;\n\t__le64 rawsize;\n\t__le32 slot;\n\tu8 align;\n\tu8 reserved[3];\n\tguid_t type_guid;\n\tguid_t abstraction_guid;\n\tu8 reserved2[88];\n\t__le64 checksum;\n};\n\nstruct nd_namespace_label {\n\tunion {\n\t\tstruct nvdimm_cxl_label cxl;\n\t\tstruct nvdimm_efi_label efi;\n\t};\n};\n\nstruct nd_namespace_pmem {\n\tstruct nd_namespace_io nsio;\n\tlong unsigned int lbasize;\n\tchar *alt_name;\n\tuuid_t *uuid;\n\tint id;\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct nd_percpu_lane {\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct nd_pfn_sb {\n\tu8 signature[16];\n\tu8 uuid[16];\n\tu8 parent_uuid[16];\n\t__le32 flags;\n\t__le16 version_major;\n\t__le16 version_minor;\n\t__le64 dataoff;\n\t__le64 npfns;\n\t__le32 mode;\n\t__le32 start_pad;\n\t__le32 end_trunc;\n\t__le32 align;\n\t__le32 page_size;\n\t__le16 page_struct_size;\n\tu8 padding[3994];\n\t__le64 checksum;\n};\n\nstruct nd_region {\n\tstruct device dev;\n\tstruct ida ns_ida;\n\tstruct ida btt_ida;\n\tstruct ida pfn_ida;\n\tstruct ida dax_ida;\n\tlong unsigned int flags;\n\tstruct device *ns_seed;\n\tstruct device *btt_seed;\n\tstruct device *pfn_seed;\n\tstruct device *dax_seed;\n\tlong unsigned int align;\n\tu16 ndr_mappings;\n\tu64 ndr_size;\n\tu64 ndr_start;\n\tint id;\n\tint num_lanes;\n\tint ro;\n\tint numa_node;\n\tint target_node;\n\tvoid *provider_data;\n\tstruct kernfs_node *bb_state;\n\tstruct badblocks bb;\n\tstruct nd_interleave_set *nd_set;\n\tstruct nd_percpu_lane *lane;\n\tint (*flush)(struct nd_region *, struct bio *);\n\tstruct nd_mapping mapping[0];\n};\n\nstruct nd_region_data {\n\tint ns_count;\n\tint ns_active;\n\tunsigned int hints_shift;\n\tvoid *flush_wpq[0];\n};\n\nstruct nd_region_desc {\n\tstruct resource *res;\n\tstruct nd_mapping_desc *mapping;\n\tu16 num_mappings;\n\tconst struct attribute_group **attr_groups;\n\tstruct nd_interleave_set *nd_set;\n\tvoid *provider_data;\n\tint num_lanes;\n\tint numa_node;\n\tint target_node;\n\tlong unsigned int flags;\n\tint memregion;\n\tstruct device_node *of_node;\n\tint (*flush)(struct nd_region *, struct bio *);\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct nduseroptmsg {\n\tunsigned char nduseropt_family;\n\tunsigned char nduseropt_pad1;\n\tshort unsigned int nduseropt_opts_len;\n\tint nduseropt_ifindex;\n\t__u8 nduseropt_icmp_type;\n\t__u8 nduseropt_icmp_code;\n\tshort unsigned int nduseropt_pad2;\n\tunsigned int nduseropt_pad3;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tlong: 0;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct ref_tracker_dir {};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct udp_mib *udplite_statistics;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct udp_tunnel_gro {\n\tstruct sock *sk;\n\tstruct hlist_head list;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 0;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct udp_tunnel_gro udp_tunnel_gro[2];\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_raw_l3mdev_accept;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_udp_l3mdev_accept;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tu32 multipath_hash_fields;\n\tu8 multipath_hash_policy;\n\t__u8 __cacheline_group_begin__sysctl_ipv6_flowlabel[0];\n\tu8 flowlabel_consistency;\n\tu8 auto_flowlabels;\n\tu8 flowlabel_state_ranges;\n\t__u8 __cacheline_group_end__sysctl_ipv6_flowlabel[0];\n\tu8 icmpv6_echo_ignore_all;\n\tu8 icmpv6_echo_ignore_multicast;\n\tu8 icmpv6_echo_ignore_anycast;\n\tint icmpv6_time;\n\tlong unsigned int icmpv6_ratemask[4];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tu8 anycast_src_echo_reply;\n\tu8 bindv6only;\n\tu8 ip_nonlocal_bind;\n\tu8 fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tu32 ioam6_id;\n\tu64 ioam6_id_wide;\n\tu8 skip_notify_on_dev_down;\n\tu8 fib_notify_on_flag_change;\n\tu8 icmpv6_error_anycast_as_unicast;\n\tu8 icmpv6_errors_extension_mask;\n};\n\nstruct rt6_statistics;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct dst_ops ip6_dst_ops;\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tspinlock_t fib_table_hash_lock;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tatomic_t ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned char flowlabel_has_excl;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct hlist_head *inet6_addr_lst;\n\tspinlock_t addrconf_hash_lock;\n\tstruct delayed_work addr_chk_work;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tstruct ioam6_pernet_data *ioam6_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nf_logger;\n\nstruct nf_hook_entries;\n\nstruct netns_nf {\n\tstruct proc_dir_entry *proc_netfilter;\n\tconst struct nf_logger *nf_loggers[11];\n\tstruct ctl_table_header *nf_log_dir_header;\n\tstruct nf_hook_entries *hooks_ipv4[5];\n\tstruct nf_hook_entries *hooks_ipv6[5];\n\tstruct nf_hook_entries *hooks_bridge[5];\n\tunsigned int defrag_ipv4_users;\n\tunsigned int defrag_ipv6_users;\n};\n\nstruct nf_ct_event_notifier;\n\nstruct nf_generic_net {\n\tunsigned int timeout;\n};\n\nstruct nf_tcp_net {\n\tunsigned int timeouts[14];\n\tu8 tcp_loose;\n\tu8 tcp_be_liberal;\n\tu8 tcp_max_retrans;\n\tu8 tcp_ignore_invalid_rst;\n};\n\nstruct nf_udp_net {\n\tunsigned int timeouts[2];\n};\n\nstruct nf_icmp_net {\n\tunsigned int timeout;\n};\n\nstruct nf_sctp_net {\n\tunsigned int timeouts[10];\n};\n\nstruct nf_ip_net {\n\tstruct nf_generic_net generic;\n\tstruct nf_tcp_net tcp;\n\tstruct nf_udp_net udp;\n\tstruct nf_icmp_net icmp;\n\tstruct nf_icmp_net icmpv6;\n\tstruct nf_sctp_net sctp;\n};\n\nstruct netns_ct {\n\tu8 sysctl_log_invalid;\n\tu8 sysctl_events;\n\tu8 sysctl_acct;\n\tu8 sysctl_tstamp;\n\tu8 sysctl_checksum;\n\tstruct ip_conntrack_stat *stat;\n\tstruct nf_ct_event_notifier *nf_conntrack_event_cb;\n\tstruct nf_ip_net nf_ct_proto;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct xfrm_policy_hash {\n\tstruct hlist_head *table;\n\tunsigned int hmask;\n\tu8 dbits4;\n\tu8 sbits4;\n\tu8 dbits6;\n\tu8 sbits6;\n};\n\nstruct xfrm_policy_hthresh {\n\tstruct work_struct work;\n\tseqlock_t lock;\n\tu8 lbits4;\n\tu8 rbits4;\n\tu8 lbits6;\n\tu8 rbits6;\n};\n\nstruct netns_xfrm {\n\tstruct list_head state_all;\n\tstruct hlist_head *state_bydst;\n\tstruct hlist_head *state_bysrc;\n\tstruct hlist_head *state_byspi;\n\tstruct hlist_head *state_byseq;\n\tstruct hlist_head *state_cache_input;\n\tunsigned int state_hmask;\n\tunsigned int state_num;\n\tstruct work_struct state_hash_work;\n\tstruct list_head policy_all;\n\tstruct hlist_head *policy_byidx;\n\tunsigned int policy_idx_hmask;\n\tunsigned int idx_generator;\n\tstruct xfrm_policy_hash policy_bydst[3];\n\tunsigned int policy_count[6];\n\tstruct work_struct policy_hash_work;\n\tstruct xfrm_policy_hthresh policy_hthresh;\n\tstruct list_head inexact_bins;\n\tstruct sock *nlsk;\n\tstruct sock *nlsk_stash;\n\tu32 sysctl_aevent_etime;\n\tu32 sysctl_aevent_rseqth;\n\tint sysctl_larval_drop;\n\tu32 sysctl_acq_expires;\n\tu8 policy_default[3];\n\tstruct ctl_table_header *sysctl_hdr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct dst_ops xfrm4_dst_ops;\n\tstruct dst_ops xfrm6_dst_ops;\n\tspinlock_t xfrm_state_lock;\n\tseqcount_spinlock_t xfrm_state_hash_generation;\n\tseqcount_spinlock_t xfrm_policy_hash_generation;\n\tspinlock_t xfrm_policy_lock;\n\tstruct mutex xfrm_cfg_mutex;\n\tstruct delayed_work nat_keepalive_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_ipvs;\n\nstruct can_dev_rcv_lists;\n\nstruct can_pkg_stats;\n\nstruct can_rcv_lists_stats;\n\nstruct netns_can {\n\tstruct proc_dir_entry *proc_dir;\n\tstruct proc_dir_entry *pde_stats;\n\tstruct proc_dir_entry *pde_reset_stats;\n\tstruct proc_dir_entry *pde_rcvlist_all;\n\tstruct proc_dir_entry *pde_rcvlist_fil;\n\tstruct proc_dir_entry *pde_rcvlist_inv;\n\tstruct proc_dir_entry *pde_rcvlist_sff;\n\tstruct proc_dir_entry *pde_rcvlist_eff;\n\tstruct proc_dir_entry *pde_rcvlist_err;\n\tstruct proc_dir_entry *bcmproc_dir;\n\tstruct can_dev_rcv_lists *rx_alldev_list;\n\tspinlock_t rcvlists_lock;\n\tstruct timer_list stattimer;\n\tstruct can_pkg_stats *pkg_stats;\n\tstruct can_rcv_lists_stats *rcv_lists_stats;\n\tstruct hlist_head cgw_list;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct netns_nf nf;\n\tstruct netns_ct ct;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tstruct netns_xfrm xfrm;\n\tu64 net_cookie;\n\tstruct netns_ipvs *ipvs;\n\tstruct netns_can can;\n\tstruct sock *diag_nlsk;\n\tlong: 64;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct net_bridge;\n\nstruct net_bridge_vlan;\n\nstruct net_bridge_mcast {\n\tstruct net_bridge *br;\n\tstruct net_bridge_vlan *vlan;\n\tu32 multicast_last_member_count;\n\tu32 multicast_startup_query_count;\n\tu8 multicast_querier;\n\tu8 multicast_igmp_version;\n\tu8 multicast_router;\n\tu8 multicast_mld_version;\n\tlong unsigned int multicast_last_member_interval;\n\tlong unsigned int multicast_membership_interval;\n\tlong unsigned int multicast_querier_interval;\n\tlong unsigned int multicast_query_interval;\n\tlong unsigned int multicast_query_response_interval;\n\tlong unsigned int multicast_startup_query_interval;\n\tstruct hlist_head ip4_mc_router_list;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct bridge_mcast_other_query ip4_other_query;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct bridge_mcast_querier ip4_querier;\n\tstruct hlist_head ip6_mc_router_list;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct bridge_mcast_other_query ip6_other_query;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct bridge_mcast_querier ip6_querier;\n};\n\nstruct net_bridge_vlan_group;\n\nstruct net_bridge {\n\tspinlock_t lock;\n\tspinlock_t hash_lock;\n\tstruct hlist_head frame_type_list;\n\tstruct net_device *dev;\n\tlong unsigned int options;\n\t__be16 vlan_proto;\n\tu16 default_pvid;\n\tstruct net_bridge_vlan_group *vlgrp;\n\tstruct rhashtable fdb_hash_tbl;\n\tstruct list_head port_list;\n\tunion {\n\t\tstruct rtable fake_rtable;\n\t\tstruct rt6_info fake_rt6_info;\n\t};\n\tu32 metrics[17];\n\tu16 group_fwd_mask;\n\tu16 group_fwd_mask_required;\n\tbridge_id designated_root;\n\tbridge_id bridge_id;\n\tunsigned char topology_change;\n\tunsigned char topology_change_detected;\n\tu16 root_port;\n\tlong unsigned int max_age;\n\tlong unsigned int hello_time;\n\tlong unsigned int forward_delay;\n\tlong unsigned int ageing_time;\n\tlong unsigned int bridge_max_age;\n\tlong unsigned int bridge_hello_time;\n\tlong unsigned int bridge_forward_delay;\n\tlong unsigned int bridge_ageing_time;\n\tu32 root_path_cost;\n\tu8 group_addr[6];\n\tenum {\n\t\tBR_NO_STP = 0,\n\t\tBR_KERNEL_STP = 1,\n\t\tBR_USER_STP = 2,\n\t} stp_enabled;\n\tstruct net_bridge_mcast multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 hash_max;\n\tspinlock_t multicast_lock;\n\tstruct rhashtable mdb_hash_tbl;\n\tstruct rhashtable sg_port_tbl;\n\tstruct hlist_head mcast_gc_list;\n\tstruct hlist_head mdb_list;\n\tstruct work_struct mcast_gc_work;\n\tstruct timer_list hello_timer;\n\tstruct timer_list tcn_timer;\n\tstruct timer_list topology_change_timer;\n\tstruct delayed_work gc_work;\n\tstruct kobject *ifobj;\n\tu32 auto_cnt;\n\tatomic_t fdb_n_learned;\n\tu32 fdb_max_learned;\n\tstruct hlist_head fdb_list;\n};\n\nstruct net_bridge_fdb_key {\n\tmac_addr addr;\n\tu16 vlan_id;\n};\n\nstruct net_bridge_port;\n\nstruct net_bridge_fdb_entry {\n\tstruct rhash_head rhnode;\n\tstruct net_bridge_port *dst;\n\tstruct net_bridge_fdb_key key;\n\tstruct hlist_node fdb_node;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_bridge_mcast_port {\n\tstruct net_bridge_port *port;\n\tstruct net_bridge_vlan *vlan;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct hlist_node ip4_rlist;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct hlist_node ip6_rlist;\n\tunsigned char multicast_router;\n\tu32 mdb_n_entries;\n\tu32 mdb_max_entries;\n};\n\nstruct net_bridge_port {\n\tstruct net_bridge *br;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tstruct net_bridge_vlan_group *vlgrp;\n\tstruct net_bridge_port *backup_port;\n\tu32 backup_nhid;\n\tu8 priority;\n\tu8 state;\n\tu16 port_no;\n\tunsigned char topology_change_ack;\n\tunsigned char config_pending;\n\tport_id port_id;\n\tport_id designated_port;\n\tbridge_id designated_root;\n\tbridge_id designated_bridge;\n\tu32 path_cost;\n\tu32 designated_cost;\n\tlong unsigned int designated_age;\n\tstruct timer_list forward_delay_timer;\n\tstruct timer_list hold_timer;\n\tstruct timer_list message_age_timer;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n\tstruct net_bridge_mcast_port multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 multicast_eht_hosts_limit;\n\tu32 multicast_eht_hosts_cnt;\n\tstruct hlist_head mglist;\n\tchar sysfs_name[16];\n\tu16 group_fwd_mask;\n\tu16 backup_redirected_cnt;\n\tstruct bridge_stp_xstats stp_xstats;\n};\n\nstruct pcpu_sw_netstats;\n\nstruct net_bridge_vlan {\n\tstruct rhash_head vnode;\n\tstruct rhash_head tnode;\n\tu16 vid;\n\tu16 flags;\n\tu16 priv_flags;\n\tu8 state;\n\tstruct pcpu_sw_netstats *stats;\n\tunion {\n\t\tstruct net_bridge *br;\n\t\tstruct net_bridge_port *port;\n\t};\n\tunion {\n\t\trefcount_t refcnt;\n\t\tstruct net_bridge_vlan *brvlan;\n\t};\n\tstruct br_tunnel_info tinfo;\n\tunion {\n\t\tstruct net_bridge_mcast br_mcast_ctx;\n\t\tstruct net_bridge_mcast_port port_mcast_ctx;\n\t};\n\tu16 msti;\n\tstruct list_head vlist;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_vlan_group {\n\tstruct rhashtable vlan_hash;\n\tstruct rhashtable tunnel_hash;\n\tstruct list_head vlan_list;\n\tu16 num_vlans;\n\tu16 pvid;\n\tu8 pvid_state;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_dstats;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct vlan_info;\n\nstruct xdp_dev_bulk_queue;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct netprio_map;\n\nstruct phy_link_topology;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct nf_hook_entries *nf_hooks_egress;\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct l3mdev_ops *l3mdev_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tstruct vlan_info *vlan_info;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tstruct nf_hook_entries *nf_hooks_ingress;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct hlist_head qdisc_hash[16];\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct netprio_map *priomap;\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct rtnl_link_stats64;\n\nstruct netdev_bpf;\n\nstruct xdp_frame;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct net_failover_info {\n\tstruct net_device *primary_dev;\n\tstruct net_device *standby_dev;\n\tstruct rtnl_link_stats64 primary_stats;\n\tstruct rtnl_link_stats64 standby_stats;\n\tstruct rtnl_link_stats64 failover_stats;\n\tspinlock_t stats_lock;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct inet6_protocol tcpv6_protocol;\n\tstruct inet6_protocol udpv6_protocol;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_packet_attrs {\n\tconst unsigned char *src;\n\tconst unsigned char *dst;\n\tu32 ip_src;\n\tu32 ip_dst;\n\tbool tcp;\n\tu16 sport;\n\tu16 dport;\n\tint timeout;\n\tint size;\n\tint max_size;\n\tu8 id;\n\tu16 queue_mapping;\n\tbool bad_csum;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct net_test {\n\tchar name[32];\n\tint (*fn)(struct net_device *);\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct net_test_priv {\n\tstruct net_packet_attrs *packet;\n\tstruct packet_type pt;\n\tstruct completion comp;\n\tint double_vlan;\n\tint vlan_id;\n\tint ok;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct xsk_buff_pool;\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_lag_lower_state_info {\n\tu8 link_up: 1;\n\tu8 tx_enabled: 1;\n};\n\nstruct netdev_lag_upper_info {\n\tenum netdev_lag_tx_type tx_type;\n\tenum netdev_lag_hash hash_type;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tlong: 64;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tint numa_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n};\n\nstruct netevent_redirect {\n\tstruct dst_entry *old;\n\tstruct dst_entry *new;\n\tstruct neighbour *neigh;\n\tconst void *daddr;\n};\n\ntypedef void (*netfs_io_terminated_t)(void *, ssize_t);\n\nstruct netfs_io_subrequest;\n\nstruct netfs_cache_ops {\n\tvoid (*end_operation)(struct netfs_cache_resources *);\n\tint (*read)(struct netfs_cache_resources *, loff_t, struct iov_iter *, enum netfs_read_from_hole, netfs_io_terminated_t, void *);\n\tint (*write)(struct netfs_cache_resources *, loff_t, struct iov_iter *, netfs_io_terminated_t, void *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_cache_resources *, long long unsigned int *, long long unsigned int *, long long unsigned int);\n\tenum netfs_io_source (*prepare_read)(struct netfs_io_subrequest *, long long unsigned int);\n\tvoid (*prepare_write_subreq)(struct netfs_io_subrequest *);\n\tint (*prepare_write)(struct netfs_cache_resources *, loff_t *, size_t *, size_t, loff_t, bool);\n\tenum netfs_io_source (*prepare_ondemand_read)(struct netfs_cache_resources *, loff_t, size_t *, loff_t, long unsigned int *, ino_t);\n\tint (*query_occupancy)(struct netfs_cache_resources *, loff_t, size_t, size_t, loff_t *, size_t *);\n};\n\nstruct netfs_cache_resources {\n\tconst struct netfs_cache_ops *ops;\n\tvoid *cache_priv;\n\tvoid *cache_priv2;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n};\n\nstruct netfs_group;\n\nstruct netfs_folio {\n\tstruct netfs_group *netfs_group;\n\tunsigned int dirty_offset;\n\tunsigned int dirty_len;\n};\n\nstruct netfs_group {\n\trefcount_t ref;\n\tvoid (*free)(struct netfs_group *);\n};\n\nstruct netfs_request_ops;\n\nstruct netfs_inode {\n\tstruct inode inode;\n\tconst struct netfs_request_ops *ops;\n\tstruct mutex wb_lock;\n\tloff_t remote_i_size;\n\tloff_t zero_point;\n\tatomic_t io_count;\n\tlong unsigned int flags;\n};\n\nstruct netfs_io_stream {\n\tstruct netfs_io_subrequest *construct;\n\tsize_t sreq_max_len;\n\tunsigned int sreq_max_segs;\n\tunsigned int submit_off;\n\tunsigned int submit_len;\n\tunsigned int submit_extendable_to;\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tstruct list_head subrequests;\n\tstruct netfs_io_subrequest *front;\n\tlong long unsigned int collected_to;\n\tsize_t transferred;\n\tshort unsigned int error;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tbool avail;\n\tbool active;\n\tbool need_retry;\n\tbool failed;\n\tbool transferred_valid;\n};\n\nstruct rolling_buffer {\n\tstruct folio_queue *head;\n\tstruct folio_queue *tail;\n\tstruct iov_iter iter;\n\tu8 next_head_slot;\n\tu8 first_tail_slot;\n};\n\nstruct netfs_io_request {\n\tunion {\n\t\tstruct work_struct cleanup_work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct work_struct work;\n\tstruct inode *inode;\n\tstruct address_space *mapping;\n\tstruct kiocb *iocb;\n\tstruct netfs_cache_resources cache_resources;\n\tstruct netfs_io_request *copy_to_cache;\n\tstruct list_head proc_link;\n\tstruct netfs_io_stream io_streams[2];\n\tstruct netfs_group *group;\n\tstruct rolling_buffer buffer;\n\twait_queue_head_t waitq;\n\tvoid *netfs_priv;\n\tvoid *netfs_priv2;\n\tstruct bio_vec *direct_bv;\n\tlong long unsigned int submitted;\n\tlong long unsigned int len;\n\tsize_t transferred;\n\tlong int error;\n\tlong long unsigned int i_size;\n\tlong long unsigned int start;\n\tatomic64_t issued_to;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int abandon_to;\n\tlong unsigned int no_unlock_folio;\n\tunsigned int direct_bv_count;\n\tunsigned int debug_id;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tatomic_t subreq_counter;\n\tunsigned int nr_group_rel;\n\tspinlock_t lock;\n\tunsigned char front_folio_order;\n\tenum netfs_io_origin origin;\n\tbool direct_bv_unpin;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tconst struct netfs_request_ops *netfs_ops;\n};\n\nstruct netfs_io_subrequest {\n\tstruct netfs_io_request *rreq;\n\tstruct work_struct work;\n\tstruct list_head rreq_link;\n\tstruct iov_iter io_iter;\n\tlong long unsigned int start;\n\tsize_t len;\n\tsize_t transferred;\n\trefcount_t ref;\n\tshort int error;\n\tshort unsigned int debug_index;\n\tunsigned int nr_segs;\n\tu8 retry_count;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tlong unsigned int flags;\n};\n\nstruct netfs_request_ops {\n\tmempool_t *request_pool;\n\tmempool_t *subrequest_pool;\n\tint (*init_request)(struct netfs_io_request *, struct file *);\n\tvoid (*free_request)(struct netfs_io_request *);\n\tvoid (*free_subrequest)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_io_request *);\n\tint (*prepare_read)(struct netfs_io_subrequest *);\n\tvoid (*issue_read)(struct netfs_io_subrequest *);\n\tbool (*is_still_valid)(struct netfs_io_request *);\n\tint (*check_write_begin)(struct file *, loff_t, unsigned int, struct folio **, void **);\n\tvoid (*done)(struct netfs_io_request *);\n\tvoid (*update_i_size)(struct inode *, loff_t);\n\tvoid (*post_modify)(struct inode *);\n\tvoid (*begin_writeback)(struct netfs_io_request *);\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*retry_request)(struct netfs_io_request *, struct netfs_io_stream *);\n\tvoid (*invalidate_cache)(struct netfs_io_request *);\n};\n\nstruct netif_security_struct {\n\tconst struct net *ns;\n\tint ifindex;\n\tu32 sid;\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_diag_msg {\n\t__u8 ndiag_family;\n\t__u8 ndiag_type;\n\t__u8 ndiag_protocol;\n\t__u8 ndiag_state;\n\t__u32 ndiag_portid;\n\t__u32 ndiag_dst_portid;\n\t__u32 ndiag_dst_group;\n\t__u32 ndiag_ino;\n\t__u32 ndiag_cookie[2];\n};\n\nstruct netlink_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u16 pad;\n\t__u32 ndiag_ino;\n\t__u32 ndiag_show;\n\t__u32 ndiag_cookie[2];\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netnode_security_struct {\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} addr;\n\tu32 sid;\n\tu16 family;\n};\n\nstruct netport_security_struct {\n\tu32 sid;\n\tu16 port;\n\tu8 protocol;\n};\n\nstruct netprio_map {\n\tstruct callback_head rcu;\n\tu32 priomap_len;\n\tu32 priomap[0];\n};\n\nstruct netsfhdr {\n\t__be32 version;\n\t__be64 magic;\n\tu8 id;\n} __attribute__((packed));\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_bridge_info {\n\tenum {\n\t\tBRNF_PROTO_UNCHANGED = 0,\n\t\tBRNF_PROTO_8021Q = 1,\n\t\tBRNF_PROTO_PPPOE = 2,\n\t} orig_proto: 8;\n\tu8 pkt_otherhost: 1;\n\tu8 in_prerouting: 1;\n\tu8 bridged_dnat: 1;\n\tu8 sabotage_in_done: 1;\n\t__u16 frag_max_size;\n\tint physinif;\n\tstruct net_device *physoutdev;\n\tunion {\n\t\t__be32 ipv4_daddr;\n\t\tstruct in6_addr ipv6_daddr;\n\t\tchar neigh_header[8];\n\t};\n};\n\nstruct nf_conntrack {\n\trefcount_t use;\n};\n\nunion nf_inet_addr {\n\t__u32 all[4];\n\t__be32 ip;\n\t__be32 ip6[4];\n\tstruct in_addr in;\n\tstruct in6_addr in6;\n};\n\nunion nf_conntrack_man_proto {\n\t__be16 all;\n\tstruct {\n\t\t__be16 port;\n\t} tcp;\n\tstruct {\n\t\t__be16 port;\n\t} udp;\n\tstruct {\n\t\t__be16 id;\n\t} icmp;\n\tstruct {\n\t\t__be16 port;\n\t} dccp;\n\tstruct {\n\t\t__be16 port;\n\t} sctp;\n\tstruct {\n\t\t__be16 key;\n\t} gre;\n};\n\nstruct nf_conntrack_man {\n\tunion nf_inet_addr u3;\n\tunion nf_conntrack_man_proto u;\n\tu_int16_t l3num;\n};\n\nstruct nf_conntrack_tuple {\n\tstruct nf_conntrack_man src;\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion {\n\t\t\t__be16 all;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} tcp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} udp;\n\t\t\tstruct {\n\t\t\t\tu_int8_t type;\n\t\t\t\tu_int8_t code;\n\t\t\t} icmp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} dccp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} sctp;\n\t\t\tstruct {\n\t\t\t\t__be16 key;\n\t\t\t} gre;\n\t\t} u;\n\t\tu_int8_t protonum;\n\t\tstruct {} __nfct_hash_offsetend;\n\t\tu_int8_t dir;\n\t} dst;\n};\n\nstruct nf_conntrack_tuple_hash {\n\tstruct hlist_nulls_node hnnode;\n\tstruct nf_conntrack_tuple tuple;\n};\n\nstruct nf_ct_udp {\n\tlong unsigned int stream_ts;\n};\n\nstruct nf_ct_gre {\n\tunsigned int stream_timeout;\n\tunsigned int timeout;\n};\n\nunion nf_conntrack_proto {\n\tstruct ip_ct_sctp sctp;\n\tstruct ip_ct_tcp tcp;\n\tstruct nf_ct_udp udp;\n\tstruct nf_ct_gre gre;\n\tunsigned int tmpl_padto;\n};\n\nstruct nf_ct_ext;\n\nstruct nf_conn {\n\tstruct nf_conntrack ct_general;\n\tspinlock_t lock;\n\tu32 timeout;\n\tstruct nf_conntrack_tuple_hash tuplehash[2];\n\tlong unsigned int status;\n\tpossible_net_t ct_net;\n\tstruct {} __nfct_init_offset;\n\tstruct nf_conn *master;\n\tstruct nf_ct_ext *ext;\n\tunion nf_conntrack_proto proto;\n};\n\nstruct nf_conn___init {\n\tstruct nf_conn ct;\n};\n\nstruct nf_conn_labels {\n\tlong unsigned int bits[2];\n};\n\nstruct nf_conntrack_zone {\n\tu16 id;\n\tu8 flags;\n\tu8 dir;\n};\n\nstruct nf_ct_ext {\n\tu8 offset[3];\n\tu8 len;\n\tunsigned int gen_id;\n\tchar data[0];\n};\n\nstruct nf_ct_hook {\n\tint (*update)(struct net *, struct sk_buff *);\n\tvoid (*destroy)(struct nf_conntrack *);\n\tbool (*get_tuple_skb)(struct nf_conntrack_tuple *, const struct sk_buff *);\n\tvoid (*attach)(struct sk_buff *, const struct sk_buff *);\n\tvoid (*set_closing)(struct nf_conntrack *);\n\tint (*confirm)(struct sk_buff *);\n\tu32 (*get_id)(const struct nf_conntrack *);\n};\n\nstruct nf_defrag_hook {\n\tstruct module *owner;\n\tint (*enable)(struct net *);\n\tvoid (*disable)(struct net *);\n};\n\nstruct nf_hook_entry {\n\tnf_hookfn *hook;\n\tvoid *priv;\n};\n\nstruct nf_hook_entries {\n\tu16 num_hook_entries;\n\tstruct nf_hook_entry hooks[0];\n};\n\nstruct nf_hook_entries_rcu_head {\n\tstruct callback_head head;\n\tvoid *allocation;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nf_queue_entry;\n\nstruct nf_ipv6_ops {\n\tvoid (*route_input)(struct sk_buff *);\n\tint (*fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tint (*reroute)(struct sk_buff *, const struct nf_queue_entry *);\n};\n\nstruct nf_log_buf {\n\tunsigned int count;\n\tchar buf[1020];\n};\n\nstruct nf_loginfo;\n\ntypedef void nf_logfn(struct net *, u_int8_t, unsigned int, const struct sk_buff *, const struct net_device *, const struct net_device *, const struct nf_loginfo *, const char *);\n\nstruct nf_logger {\n\tchar *name;\n\tenum nf_log_type type;\n\tnf_logfn *logfn;\n\tstruct module *me;\n};\n\nstruct nf_loginfo {\n\tu_int8_t type;\n\tunion {\n\t\tstruct {\n\t\t\tu_int32_t copy_len;\n\t\t\tu_int16_t group;\n\t\t\tu_int16_t qthreshold;\n\t\t\tu_int16_t flags;\n\t\t} ulog;\n\t\tstruct {\n\t\t\tu_int8_t level;\n\t\t\tu_int8_t logflags;\n\t\t} log;\n\t} u;\n};\n\nstruct nf_nat_hook {\n\tint (*parse_nat_setup)(struct nf_conn *, enum nf_nat_manip_type, const struct nlattr *);\n\tvoid (*decode_session)(struct sk_buff *, struct flowi *);\n\tvoid (*remove_nat_bysrc)(struct nf_conn *);\n};\n\nstruct nf_queue_entry {\n\tstruct list_head list;\n\tstruct rhash_head hash_node;\n\tstruct sk_buff *skb;\n\tunsigned int id;\n\tunsigned int hook_index;\n\tstruct net_device *physin;\n\tstruct net_device *physout;\n\tstruct nf_hook_state state;\n\tbool nf_ct_is_unconfirmed;\n\tu16 size;\n\tu16 queue_num;\n};\n\nstruct nf_queue_handler {\n\tint (*outfn)(struct nf_queue_entry *, unsigned int);\n\tvoid (*nf_hook_drop)(struct net *);\n};\n\nstruct nf_sockopt_ops {\n\tstruct list_head list;\n\tu_int8_t pf;\n\tint set_optmin;\n\tint set_optmax;\n\tint (*set)(struct sock *, int, sockptr_t, unsigned int);\n\tint get_optmin;\n\tint get_optmax;\n\tint (*get)(struct sock *, int, void *, int *);\n\tstruct module *owner;\n};\n\nstruct nfnl_ct_hook {\n\tsize_t (*build_size)(const struct nf_conn *);\n\tint (*build)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, u_int16_t, u_int16_t);\n\tint (*parse)(const struct nlattr *, struct nf_conn *);\n\tint (*attach_expect)(const struct nlattr *, struct nf_conn *, u32, u32);\n\tvoid (*seq_adjust)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, s32);\n};\n\nstruct nfs2_fh {\n\tchar data[32];\n};\n\nstruct nfs3_accessargs {\n\tstruct nfs_fh *fh;\n\t__u32 access;\n};\n\nstruct nfs_fattr;\n\nstruct nfs3_accessres {\n\tstruct nfs_fattr *fattr;\n\t__u32 access;\n};\n\nstruct nfs3_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n\tenum nfs3_createmode createmode;\n\t__be32 verifier[2];\n};\n\nstruct rpc_procinfo;\n\nstruct rpc_message {\n\tconst struct rpc_procinfo *rpc_proc;\n\tvoid *rpc_argp;\n\tvoid *rpc_resp;\n\tconst struct cred *rpc_cred;\n};\n\nstruct nfs3_mkdirargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_mknodargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tenum nfs3_ftype type;\n\tstruct iattr *sattr;\n\tdev_t rdev;\n};\n\nstruct nfs3_diropres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs4_string;\n\nstruct nfs4_threshold;\n\nstruct nfs4_label;\n\nstruct nfs_fattr {\n\t__u64 valid;\n\tumode_t mode;\n\t__u32 nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\t__u64 size;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 blocksize;\n\t\t\t__u32 blocks;\n\t\t} nfs2;\n\t\tstruct {\n\t\t\t__u64 used;\n\t\t} nfs3;\n\t} du;\n\tstruct nfs_fsid fsid;\n\t__u64 fileid;\n\t__u64 mounted_on_fileid;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\t__u64 change_attr;\n\t__u64 pre_change_attr;\n\t__u64 pre_size;\n\tstruct timespec64 pre_mtime;\n\tstruct timespec64 pre_ctime;\n\tlong unsigned int time_start;\n\tlong unsigned int gencount;\n\tstruct nfs4_string *owner_name;\n\tstruct nfs4_string *group_name;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs3_createdata {\n\tstruct rpc_message msg;\n\tunion {\n\t\tstruct nfs3_createargs create;\n\t\tstruct nfs3_mkdirargs mkdir;\n\t\tstruct nfs3_symlinkargs symlink;\n\t\tstruct nfs3_mknodargs mknod;\n\t} arg;\n\tstruct nfs3_diropres res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_fattr dir_attr;\n};\n\nstruct nfs3_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs3_fh {\n\tshort unsigned int size;\n\tunsigned char data[64];\n};\n\nstruct nfs3_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs3_linkres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_readdirargs {\n\tstruct nfs_fh *fh;\n\t__u64 cookie;\n\t__be32 verf[2];\n\tbool plus;\n\tunsigned int count;\n\tstruct page **pages;\n};\n\nstruct nfs3_readdirres {\n\tstruct nfs_fattr *dir_attr;\n\t__be32 *verf;\n\tbool plus;\n};\n\nstruct nfs3_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs3_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n\tunsigned int guard;\n\tstruct timespec64 guardtime;\n};\n\nstruct nfs41_bind_conn_to_session_args {\n\tstruct nfs_client *client;\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n\tint retries;\n};\n\nstruct nfs41_bind_conn_to_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n};\n\nstruct nfs4_channel_attrs {\n\tu32 max_rqst_sz;\n\tu32 max_resp_sz;\n\tu32 max_resp_sz_cached;\n\tu32 max_ops;\n\tu32 max_reqs;\n};\n\nstruct nfs41_create_session_args {\n\tstruct nfs_client *client;\n\tu64 clientid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tuint32_t cb_program;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs41_create_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs4_op_map {\n\tunion {\n\t\tlong unsigned int longs[2];\n\t\tu32 words[4];\n\t} u;\n};\n\nstruct nfs41_state_protection {\n\tu32 how;\n\tstruct nfs4_op_map enforce;\n\tstruct nfs4_op_map allow;\n};\n\nstruct nfs41_exchange_id_args {\n\tstruct nfs_client *client;\n\tnfs4_verifier verifier;\n\tu32 flags;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_server_owner;\n\nstruct nfs41_server_scope;\n\nstruct nfs41_impl_id;\n\nstruct nfs41_exchange_id_res {\n\tu64 clientid;\n\tu32 seqid;\n\tu32 flags;\n\tstruct nfs41_server_owner *server_owner;\n\tstruct nfs41_server_scope *server_scope;\n\tstruct nfs41_impl_id *impl_id;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_exchange_id_data {\n\tstruct nfs41_exchange_id_res res;\n\tstruct nfs41_exchange_id_args args;\n};\n\nstruct nfs4_sequence_args {\n\tstruct nfs4_slot *sa_slot;\n\tu8 sa_cache_this: 1;\n\tu8 sa_privileged: 1;\n};\n\nstruct nfs41_free_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_sequence_slot_ops;\n\nstruct nfs4_sequence_res {\n\tconst struct nfs4_sequence_slot_ops *sr_slot_ops;\n\tstruct nfs4_slot *sr_slot;\n\tlong unsigned int sr_timestamp;\n\tint sr_status;\n\tu32 sr_status_flags;\n\tu32 sr_highest_slotid;\n\tu32 sr_target_highest_slotid;\n};\n\nstruct nfs41_free_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfstime4 {\n\tint64_t seconds;\n\tuint32_t nseconds;\n};\n\nstruct nfs41_impl_id {\n\tchar domain[1025];\n\tchar name[1025];\n\tstruct nfstime4 date;\n};\n\nstruct nfs41_reclaim_complete_args {\n\tstruct nfs4_sequence_args seq_args;\n\tunsigned char one_fs: 1;\n};\n\nstruct nfs41_reclaim_complete_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs41_secinfo_no_name_args {\n\tstruct nfs4_sequence_args seq_args;\n\tint style;\n};\n\nstruct nfs41_server_owner {\n\tuint64_t minor_id;\n\tuint32_t major_id_sz;\n\tchar major_id[1024];\n};\n\nstruct nfs41_server_scope {\n\tuint32_t server_scope_sz;\n\tchar server_scope[1024];\n};\n\nstruct nfs41_test_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs41_test_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfs42_clone_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid src_stateid;\n\tnfs4_stateid dst_stateid;\n\t__u64 src_offset;\n\t__u64 dst_offset;\n\t__u64 count;\n\tconst u32 *dst_bitmask;\n};\n\nstruct nfs_server;\n\nstruct nfs42_clone_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int rpc_status;\n\tstruct nfs_fattr *dst_fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nl4_server;\n\nstruct nfs42_copy_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tnfs4_stateid src_stateid;\n\tu64 src_pos;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid dst_stateid;\n\tu64 dst_pos;\n\tu64 count;\n\tbool sync;\n\tstruct nl4_server *cp_src;\n};\n\nstruct nfs42_netaddr {\n\tchar netid[5];\n\tchar addr[58];\n\tu32 netid_len;\n\tu32 addr_len;\n};\n\nstruct nl4_server {\n\tenum netloc_type4 nl4_type;\n\tunion {\n\t\tstruct {\n\t\t\tint nl4_str_sz;\n\t\t\tchar nl4_str[1025];\n\t\t};\n\t\tstruct nfs42_netaddr nl4_addr;\n\t} u;\n};\n\nstruct nfs42_copy_notify_args {\n\tstruct nfs4_sequence_args cna_seq_args;\n\tstruct nfs_fh *cna_src_fh;\n\tnfs4_stateid cna_src_stateid;\n\tstruct nl4_server cna_dst;\n};\n\nstruct nfs42_copy_notify_res {\n\tstruct nfs4_sequence_res cnr_seq_res;\n\tstruct nfstime4 cnr_lease_time;\n\tnfs4_stateid cnr_stateid;\n\tstruct nl4_server cnr_src;\n};\n\nstruct nfs42_write_res {\n\tnfs4_stateid stateid;\n\tu64 count;\n\tstruct nfs_writeverf verifier;\n};\n\nstruct nfs_commitres {\n\tstruct nfs4_sequence_res seq_res;\n\t__u32 op_status;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_writeverf *verf;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs42_copy_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs42_write_res write_res;\n\tbool consecutive;\n\tbool synchronous;\n\tstruct nfs_commitres commit_res;\n};\n\nstruct nfs42_device_error {\n\tstruct nfs4_deviceid dev_id;\n\tint status;\n\tenum nfs_opnum4 opnum;\n};\n\nstruct nfs42_falloc_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *falloc_fh;\n\tnfs4_stateid falloc_stateid;\n\tu64 falloc_offset;\n\tu64 falloc_length;\n\tconst u32 *falloc_bitmask;\n};\n\nstruct nfs42_falloc_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tstruct nfs_fattr *falloc_fattr;\n\tconst struct nfs_server *falloc_server;\n};\n\nstruct nfs42_getxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_getxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tsize_t xattr_len;\n};\n\nstruct nfs42_layout_error {\n\t__u64 offset;\n\t__u64 length;\n\tnfs4_stateid stateid;\n\tstruct nfs42_device_error errors[1];\n};\n\nstruct nfs42_layouterror_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct inode *inode;\n\tunsigned int num_errors;\n\tstruct nfs42_layout_error errors[5];\n};\n\nstruct nfs42_layouterror_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int num_errors;\n\tint rpc_status;\n};\n\nstruct pnfs_layout_segment;\n\nstruct nfs42_layouterror_data {\n\tstruct nfs42_layouterror_args args;\n\tstruct nfs42_layouterror_res res;\n\tstruct inode *inode;\n\tstruct pnfs_layout_segment *lseg;\n};\n\nstruct nfs42_layoutstat_devinfo;\n\nstruct nfs42_layoutstat_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tint num_dev;\n\tstruct nfs42_layoutstat_devinfo *devinfo;\n};\n\nstruct nfs42_layoutstat_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint num_dev;\n\tint rpc_status;\n};\n\nstruct nfs42_layoutstat_data {\n\tstruct inode *inode;\n\tstruct nfs42_layoutstat_args args;\n\tstruct nfs42_layoutstat_res res;\n};\n\nstruct nfs4_xdr_opaque_ops;\n\nstruct nfs4_xdr_opaque_data {\n\tconst struct nfs4_xdr_opaque_ops *ops;\n\tvoid *data;\n};\n\nstruct nfs42_layoutstat_devinfo {\n\tstruct nfs4_deviceid dev_id;\n\t__u64 offset;\n\t__u64 length;\n\t__u64 read_count;\n\t__u64 read_bytes;\n\t__u64 write_count;\n\t__u64 write_bytes;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs42_listxattrsargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tu32 count;\n\tu64 cookie;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_listxattrsres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct folio *scratch;\n\tvoid *xattr_buf;\n\tsize_t xattr_len;\n\tu64 cookie;\n\tbool eof;\n\tsize_t copied;\n};\n\nstruct nfs42_offload_status_args {\n\tstruct nfs4_sequence_args osa_seq_args;\n\tstruct nfs_fh *osa_src_fh;\n\tnfs4_stateid osa_stateid;\n};\n\nstruct nfs42_offload_status_res {\n\tstruct nfs4_sequence_res osr_seq_res;\n\tu64 osr_count;\n\tint complete_count;\n\tu32 osr_complete;\n};\n\nstruct nfs42_offload_data {\n\tstruct nfs_server *seq_server;\n\tstruct nfs42_offload_status_args args;\n\tstruct nfs42_offload_status_res res;\n};\n\nstruct nfs42_removexattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n};\n\nstruct nfs4_change_info {\n\tu32 atomic;\n\tu64 before;\n\tu64 after;\n};\n\nstruct nfs42_removexattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs42_seek_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *sa_fh;\n\tnfs4_stateid sa_stateid;\n\tu64 sa_offset;\n\tu32 sa_what;\n};\n\nstruct nfs42_seek_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tu32 sr_eof;\n\tu64 sr_offset;\n};\n\nstruct nfs42_setxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tconst char *xattr_name;\n\tu32 xattr_flags;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_setxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs4_accessargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tu32 access;\n};\n\nstruct nfs4_accessres {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tu32 supported;\n\tu32 access;\n};\n\nstruct nfs4_add_xprt_data {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct nfs4_cached_acl {\n\tenum nfs4_acl_type type;\n\tint cached;\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct nfs4_call_sync_data {\n\tconst struct nfs_server *seq_server;\n\tstruct nfs4_sequence_args *seq_args;\n\tstruct nfs4_sequence_res *seq_res;\n};\n\nstruct nfs_seqid;\n\nstruct nfs4_layoutreturn_args;\n\nstruct nfs_closeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n\tfmode_t fmode;\n\tu32 share_access;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs4_layoutreturn_res;\n\nstruct nfs_closeres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct pnfs_layout_hdr;\n\nstruct nfs4_layoutreturn_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_layout_hdr *layout;\n\tstruct inode *inode;\n\tstruct pnfs_layout_range range;\n\tnfs4_stateid stateid;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data *ld_private;\n};\n\nstruct nfs4_layoutreturn_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 lrs_present;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_state;\n\nstruct nfs4_closedata {\n\tstruct inode *inode;\n\tstruct nfs4_state *state;\n\tstruct nfs_closeargs arg;\n\tstruct nfs_closeres res;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_copy_state {\n\tstruct list_head copies;\n\tstruct list_head src_copies;\n\tnfs4_stateid stateid;\n\tstruct completion completion;\n\tuint64_t count;\n\tstruct nfs_writeverf verf;\n\tint error;\n\tint flags;\n\tstruct nfs4_state *parent_src_state;\n\tstruct nfs4_state *parent_dst_state;\n};\n\nstruct nfs4_create_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tu32 ftype;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page **pages;\n\t\t\tunsigned int len;\n\t\t} symlink;\n\t\tstruct {\n\t\t\tu32 specdata1;\n\t\t\tu32 specdata2;\n\t\t} device;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst struct iattr *attrs;\n\tconst struct nfs_fh *dir_fh;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n};\n\nstruct nfs4_create_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info dir_cinfo;\n};\n\nstruct nfs4_createdata {\n\tstruct rpc_message msg;\n\tstruct nfs4_create_arg arg;\n\tstruct nfs4_create_res res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n};\n\nstruct nfs4_delegattr {\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tbool atime_set;\n\tbool mtime_set;\n};\n\nstruct nfs4_delegreturnargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fhandle;\n\tconst nfs4_stateid *stateid;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n\tstruct nfs4_delegattr *sattr_args;\n};\n\nstruct nfs4_delegreturnres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n\tbool sattr_res;\n\tint sattr_ret;\n};\n\nstruct nfs4_delegreturndata {\n\tstruct nfs4_delegreturnargs args;\n\tstruct nfs4_delegreturnres res;\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs4_delegattr sattr;\n\tstruct nfs_fattr fattr;\n\tint rpc_status;\n\tstruct inode *inode;\n};\n\nstruct pnfs_layoutdriver_type;\n\nstruct nfs4_deviceid_node {\n\tstruct hlist_node node;\n\tstruct hlist_node tmpnode;\n\tconst struct pnfs_layoutdriver_type *ld;\n\tconst struct nfs_client *nfs_client;\n\tlong unsigned int flags;\n\tlong unsigned int timestamp_unavailable;\n\tstruct nfs4_deviceid deviceid;\n\tstruct callback_head rcu;\n\tatomic_t ref;\n};\n\nstruct rpc_clnt;\n\nstruct nfs4_ds_server {\n\tstruct list_head list;\n\tstruct rpc_clnt *rpc_clnt;\n};\n\nstruct nfs4_exception {\n\tstruct nfs4_state *state;\n\tstruct inode *inode;\n\tnfs4_stateid *stateid;\n\tlong int timeout;\n\tshort unsigned int retrans;\n\tunsigned char task_is_privileged: 1;\n\tunsigned char delay: 1;\n\tunsigned char recovering: 1;\n\tunsigned char retry: 1;\n\tbool interruptible;\n};\n\nstruct nfs4_ff_busy_timer {\n\tktime_t start_time;\n\tatomic_t n_ops;\n};\n\nstruct nfs4_ff_ds_version {\n\tu32 version;\n\tu32 minor_version;\n\tu32 rsize;\n\tu32 wsize;\n\tbool tightly_coupled;\n};\n\nstruct nfs4_ff_io_stat {\n\t__u64 ops_requested;\n\t__u64 bytes_requested;\n\t__u64 ops_completed;\n\t__u64 bytes_completed;\n\t__u64 bytes_not_delivered;\n\tktime_t total_busy_time;\n\tktime_t aggregate_completion_time;\n};\n\nstruct nfs4_pnfs_ds;\n\nstruct nfs4_ff_layout_ds {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 ds_versions_cnt;\n\tstruct nfs4_ff_ds_version *ds_versions;\n\tstruct nfs4_pnfs_ds *ds;\n};\n\nstruct nfs4_ff_layout_ds_err {\n\tstruct list_head list;\n\tu64 offset;\n\tu64 length;\n\tint status;\n\tenum nfs_opnum4 opnum;\n\tnfs4_stateid stateid;\n\tstruct nfs4_deviceid deviceid;\n};\n\nstruct nfsd_file;\n\nstruct nfs_file_localio {\n\tstruct nfsd_file *ro_file;\n\tstruct nfsd_file *rw_file;\n\tstruct list_head list;\n\tvoid *nfs_uuid;\n};\n\nstruct nfs4_ff_layoutstat {\n\tstruct nfs4_ff_io_stat io_stat;\n\tstruct nfs4_ff_busy_timer busy_timer;\n};\n\nstruct nfs4_ff_layout_mirror;\n\nstruct nfs4_ff_layout_ds_stripe {\n\tstruct nfs4_ff_layout_mirror *mirror;\n\tstruct nfs4_deviceid devid;\n\tu32 efficiency;\n\tstruct nfs4_ff_layout_ds *mirror_ds;\n\tu32 fh_versions_cnt;\n\tstruct nfs_fh *fh_versions;\n\tnfs4_stateid stateid;\n\tconst struct cred *ro_cred;\n\tconst struct cred *rw_cred;\n\tstruct nfs_file_localio nfl;\n\tstruct nfs4_ff_layoutstat read_stat;\n\tstruct nfs4_ff_layoutstat write_stat;\n\tktime_t start_time;\n};\n\nstruct nfs4_ff_layout_mirror {\n\tstruct pnfs_layout_hdr *layout;\n\tstruct list_head mirrors;\n\tu32 dss_count;\n\tstruct nfs4_ff_layout_ds_stripe *dss;\n\trefcount_t ref;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu32 report_interval;\n};\n\nstruct pnfs_layout_segment {\n\tstruct list_head pls_list;\n\tstruct list_head pls_lc_list;\n\tstruct list_head pls_commits;\n\tstruct pnfs_layout_range pls_range;\n\trefcount_t pls_refcount;\n\tu32 pls_seq;\n\tlong unsigned int pls_flags;\n\tstruct pnfs_layout_hdr *pls_layout;\n};\n\nstruct nfs4_ff_layout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu64 stripe_unit;\n\tu32 flags;\n\tu32 mirror_array_cnt;\n\tstruct nfs4_ff_layout_mirror *mirror_array[0];\n};\n\nstruct nfs4_file_layout_dsaddr {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 stripe_count;\n\tu8 *stripe_indices;\n\tu32 ds_num;\n\tstruct nfs4_pnfs_ds *ds_list[0];\n};\n\nstruct pnfs_layout_hdr {\n\trefcount_t plh_refcount;\n\tatomic_t plh_outstanding;\n\tstruct list_head plh_layouts;\n\tstruct list_head plh_bulk_destroy;\n\tstruct list_head plh_segs;\n\tstruct list_head plh_return_segs;\n\tlong unsigned int plh_block_lgets;\n\tlong unsigned int plh_retry_timestamp;\n\tlong unsigned int plh_flags;\n\tnfs4_stateid plh_stateid;\n\tu32 plh_barrier;\n\tu32 plh_return_seq;\n\tenum pnfs_iomode plh_return_iomode;\n\tloff_t plh_lwb;\n\tconst struct cred *plh_lc_cred;\n\tstruct inode *plh_inode;\n\tstruct callback_head plh_rcu;\n};\n\nstruct pnfs_commit_ops;\n\nstruct pnfs_ds_commit_info {\n\tstruct list_head commits;\n\tunsigned int nwritten;\n\tunsigned int ncommitting;\n\tconst struct pnfs_commit_ops *ops;\n};\n\nstruct nfs4_filelayout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n};\n\nstruct nfs4_filelayout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu32 stripe_type;\n\tu32 commit_through_mds;\n\tu32 stripe_unit;\n\tu32 first_stripe_index;\n\tu64 pattern_offset;\n\tstruct nfs4_deviceid deviceid;\n\tstruct nfs4_file_layout_dsaddr *dsaddr;\n\tunsigned int num_fh;\n\tstruct nfs_fh **fh_array;\n};\n\nstruct nfs4_flexfile_layout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tstruct list_head mirrors;\n\tstruct list_head error_list;\n\tktime_t last_report_time;\n};\n\nstruct nfs4_flexfile_layoutreturn_args {\n\tstruct list_head errors;\n\tstruct nfs42_layoutstat_devinfo devinfo[4];\n\tunsigned int num_errors;\n\tunsigned int num_dev;\n\tstruct page *pages[1];\n};\n\nstruct nfs4_string {\n\tunsigned int len;\n\tchar *data;\n};\n\nstruct nfs4_pathname {\n\tunsigned int ncomponents;\n\tstruct nfs4_string components[512];\n};\n\nstruct nfs4_fs_location {\n\tunsigned int nservers;\n\tstruct nfs4_string servers[10];\n\tstruct nfs4_pathname rootpath;\n};\n\nstruct nfs4_fs_locations {\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tstruct nfs4_pathname fs_path;\n\tint nlocations;\n\tstruct nfs4_fs_location locations[10];\n};\n\nstruct nfs4_fs_locations_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct nfs_fh *fh;\n\tconst struct qstr *name;\n\tstruct page *page;\n\tconst u32 *bitmask;\n\tclientid4 clientid;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fs_locations_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_fs_locations *fs_locations;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tclientid4 clientid;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fh *fh;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsinfo;\n\nstruct nfs4_fsinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsinfo *fsinfo;\n};\n\nstruct nfs4_gdd_res {\n\tu32 status;\n\tnfs4_stateid deleg;\n};\n\nstruct nfs4_get_lease_time_args {\n\tstruct nfs4_sequence_args la_seq_args;\n};\n\nstruct nfs4_get_lease_time_res;\n\nstruct nfs4_get_lease_time_data {\n\tstruct nfs4_get_lease_time_args *args;\n\tstruct nfs4_get_lease_time_res *res;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_get_lease_time_res {\n\tstruct nfs4_sequence_res lr_seq_res;\n\tstruct nfs_fsinfo *lr_fsinfo;\n};\n\nstruct nfs4_getattr_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tbool get_dir_deleg;\n};\n\nstruct nfs4_getattr_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_gdd_res *gdd_res;\n};\n\nstruct pnfs_device;\n\nstruct nfs4_getdeviceinfo_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_device *pdev;\n\t__u32 notify_types;\n};\n\nstruct nfs4_getdeviceinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct pnfs_device *pdev;\n\t__u32 notification;\n};\n\nstruct nfs4_label {\n\tuint32_t lfs;\n\tuint32_t pi;\n\tu32 lsmid;\n\tu32 len;\n\tchar *label;\n};\n\nstruct nfs4_layoutcommit_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n\t__u64 lastbytewritten;\n\tstruct inode *inode;\n\tconst u32 *bitmask;\n\tsize_t layoutupdate_len;\n\tstruct page *layoutupdate_page;\n\tstruct page **layoutupdate_pages;\n\t__be32 *start_p;\n};\n\nstruct rpc_wait {\n\tstruct list_head list;\n\tstruct list_head links;\n\tstruct list_head timer_list;\n};\n\nstruct rpc_wait_queue;\n\nstruct rpc_call_ops;\n\nstruct rpc_xprt;\n\nstruct rpc_cred;\n\nstruct rpc_rqst;\n\nstruct rpc_task {\n\tatomic_t tk_count;\n\tint tk_status;\n\tstruct list_head tk_task;\n\tvoid (*tk_callback)(struct rpc_task *);\n\tvoid (*tk_action)(struct rpc_task *);\n\tlong unsigned int tk_timeout;\n\tlong unsigned int tk_runstate;\n\tstruct rpc_wait_queue *tk_waitqueue;\n\tunion {\n\t\tstruct work_struct tk_work;\n\t\tstruct rpc_wait tk_wait;\n\t} u;\n\tstruct rpc_message tk_msg;\n\tvoid *tk_calldata;\n\tconst struct rpc_call_ops *tk_ops;\n\tstruct rpc_clnt *tk_client;\n\tstruct rpc_xprt *tk_xprt;\n\tstruct rpc_cred *tk_op_cred;\n\tstruct rpc_rqst *tk_rqstp;\n\tstruct workqueue_struct *tk_workqueue;\n\tktime_t tk_start;\n\tpid_t tk_owner;\n\tint tk_rpc_status;\n\tshort unsigned int tk_flags;\n\tshort unsigned int tk_timeouts;\n\tshort unsigned int tk_pid;\n\tunsigned char tk_priority: 2;\n\tunsigned char tk_garb_retry: 2;\n\tunsigned char tk_cred_retry: 2;\n};\n\nstruct nfs4_layoutcommit_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tint status;\n};\n\nstruct nfs4_layoutcommit_data {\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct list_head lseg_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tstruct nfs4_layoutcommit_args args;\n\tstruct nfs4_layoutcommit_res res;\n};\n\nstruct nfs4_layoutdriver_data {\n\tstruct page **pages;\n\t__u32 pglen;\n\t__u32 len;\n};\n\nstruct nfs_open_context;\n\nstruct nfs4_layoutget_args {\n\tstruct nfs4_sequence_args seq_args;\n\t__u32 type;\n\tstruct pnfs_layout_range range;\n\t__u64 minlength;\n\t__u32 maxcount;\n\tstruct inode *inode;\n\tstruct nfs_open_context *ctx;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data layout;\n};\n\nstruct nfs4_layoutget_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint status;\n\t__u32 return_on_close;\n\tstruct pnfs_layout_range range;\n\t__u32 type;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data *layoutp;\n};\n\nstruct nfs4_layoutget {\n\tstruct nfs4_layoutget_args args;\n\tstruct nfs4_layoutget_res res;\n\tconst struct cred *cred;\n\tstruct pnfs_layout_hdr *lo;\n\tgfp_t gfp_flags;\n};\n\nstruct nfs4_layoutreturn {\n\tstruct nfs4_layoutreturn_args args;\n\tstruct nfs4_layoutreturn_res res;\n\tconst struct cred *cred;\n\tstruct nfs_client *clp;\n\tstruct inode *inode;\n\tint rpc_status;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs4_link_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_link_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *dir_attr;\n};\n\nstruct rpc_timer {\n\tstruct list_head list;\n\tlong unsigned int expires;\n\tstruct delayed_work dwork;\n};\n\nstruct rpc_wait_queue {\n\tspinlock_t lock;\n\tstruct list_head tasks[4];\n\tunsigned char maxpriority;\n\tunsigned char priority;\n\tunsigned char nr;\n\tunsigned int qlen;\n\tstruct rpc_timer timer_list;\n\tconst char *name;\n};\n\nstruct nfs_seqid_counter {\n\tktime_t create_time;\n\tu64 owner_id;\n\tint flags;\n\tu32 counter;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct rpc_wait_queue wait;\n};\n\nstruct nfs4_lock_state {\n\tstruct list_head ls_locks;\n\tstruct nfs4_state *ls_state;\n\tlong unsigned int ls_flags;\n\tstruct nfs_seqid_counter ls_seqid;\n\tnfs4_stateid ls_stateid;\n\trefcount_t ls_count;\n\tfl_owner_t ls_owner;\n};\n\nstruct nfs4_lock_waiter {\n\tstruct inode *inode;\n\tstruct nfs_lowner owner;\n\twait_queue_entry_t wait;\n};\n\nstruct nfs_lock_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *lock_seqid;\n\tnfs4_stateid lock_stateid;\n\tstruct nfs_seqid *open_seqid;\n\tnfs4_stateid open_stateid;\n\tstruct nfs_lowner lock_owner;\n\tunsigned char block: 1;\n\tunsigned char reclaim: 1;\n\tunsigned char new_lock: 1;\n\tunsigned char new_lock_owner: 1;\n};\n\nstruct nfs_lock_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *lock_seqid;\n\tstruct nfs_seqid *open_seqid;\n};\n\nstruct nfs4_lockdata {\n\tstruct nfs_lock_args arg;\n\tstruct nfs_lock_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct file_lock fl;\n\tlong unsigned int timestamp;\n\tint rpc_status;\n\tint cancelled;\n\tstruct nfs_server *server;\n};\n\nstruct nfs4_lookup_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookup_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_lookup_root_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_mig_recovery_ops {\n\tint (*get_locations)(struct nfs_server *, struct nfs_fh *, struct nfs4_fs_locations *, struct page *, const struct cred *);\n\tint (*fsid_present)(struct inode *, const struct cred *);\n};\n\nstruct nfs4_state_recovery_ops;\n\nstruct nfs4_state_maintenance_ops;\n\nstruct nfs4_minor_version_ops {\n\tu32 minor_version;\n\tunsigned int init_caps;\n\tint (*init_client)(struct nfs_client *);\n\tvoid (*shutdown_client)(struct nfs_client *);\n\tbool (*match_stateid)(const nfs4_stateid *, const nfs4_stateid *);\n\tint (*find_root_sec)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *);\n\tvoid (*free_lock_state)(struct nfs_server *, struct nfs4_lock_state *);\n\tint (*test_and_free_expired)(struct nfs_server *, nfs4_stateid *, const struct cred *);\n\tstruct nfs_seqid * (*alloc_seqid)(struct nfs_seqid_counter *, gfp_t);\n\tvoid (*session_trunk)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tconst struct rpc_call_ops *call_sync_ops;\n\tconst struct nfs4_sequence_slot_ops *sequence_slot_ops;\n\tconst struct nfs4_state_recovery_ops *reboot_recovery_ops;\n\tconst struct nfs4_state_recovery_ops *nograce_recovery_ops;\n\tconst struct nfs4_state_maintenance_ops *state_renewal_ops;\n\tconst struct nfs4_mig_recovery_ops *mig_recovery_ops;\n};\n\nstruct nfs_string {\n\tunsigned int len;\n\tconst char *data;\n};\n\nstruct nfs4_mount_data {\n\tint version;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct nfs_string client_addr;\n\tstruct nfs_string mnt_path;\n\tstruct nfs_string hostname;\n\tunsigned int host_addrlen;\n\tstruct sockaddr *host_addr;\n\tint proto;\n\tint auth_flavourlen;\n\tint *auth_flavours;\n};\n\nstruct nfs4_open_caps {\n\tu32 oa_share_access[1];\n\tu32 oa_share_deny[1];\n\tu32 oa_share_access_want[1];\n\tu32 oa_open_claim[1];\n\tu32 oa_createmode[1];\n};\n\nstruct nfs4_open_createattrs {\n\tstruct nfs4_label *label;\n\tstruct iattr *sattr;\n\tconst __u32 verf[2];\n};\n\nstruct nfs4_open_delegation {\n\t__u32 open_delegation_type;\n\tunion {\n\t\tstruct {\n\t\t\tfmode_t type;\n\t\t\t__u32 do_recall;\n\t\t\tnfs4_stateid stateid;\n\t\t\tlong unsigned int pagemod_limit;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 why_no_delegation;\n\t\t\t__u32 will_notify;\n\t\t};\n\t};\n};\n\nstruct stateowner_id {\n\t__u64 create_time;\n\t__u64 uniquifier;\n};\n\nstruct nfs_openargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct nfs_seqid *seqid;\n\tint open_flags;\n\tfmode_t fmode;\n\tu32 share_access;\n\tu32 access;\n\t__u64 clientid;\n\tstruct stateowner_id id;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iattr *attrs;\n\t\t\tnfs4_verifier verifier;\n\t\t};\n\t\tnfs4_stateid delegation;\n\t\t__u32 delegation_type;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst u32 *open_bitmap;\n\tenum open_claim_type4 claim;\n\tenum createmode4 createmode;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n\tstruct nfs4_layoutget_args *lg_args;\n};\n\nstruct nfs_openres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fh fh;\n\tstruct nfs4_change_info cinfo;\n\t__u32 rflags;\n\tstruct nfs_fattr *f_attr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\t__u32 attrset[3];\n\tstruct nfs4_string *owner;\n\tstruct nfs4_string *group_owner;\n\tstruct nfs4_open_delegation delegation;\n\t__u32 access_request;\n\t__u32 access_supported;\n\t__u32 access_result;\n\tstruct nfs4_layoutget_res *lg_res;\n};\n\nstruct nfs_open_confirmargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tnfs4_stateid *stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_open_confirmres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs4_state_owner;\n\nstruct nfs4_opendata {\n\tstruct kref kref;\n\tstruct nfs_openargs o_arg;\n\tstruct nfs_openres o_res;\n\tstruct nfs_open_confirmargs c_arg;\n\tstruct nfs_open_confirmres c_res;\n\tstruct nfs4_string owner_name;\n\tstruct nfs4_string group_name;\n\tstruct nfs4_label *a_label;\n\tstruct nfs_fattr f_attr;\n\tstruct dentry *dir;\n\tstruct dentry *dentry;\n\tstruct nfs4_state_owner *owner;\n\tstruct nfs4_state *state;\n\tstruct iattr attrs;\n\tstruct nfs4_layoutget *lgp;\n\tlong unsigned int timestamp;\n\tbool rpc_done;\n\tbool file_created;\n\tbool is_recover;\n\tbool cancelled;\n\tint rpc_status;\n};\n\nstruct nfs4_pathconf_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_pathconf;\n\nstruct nfs4_pathconf_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_pathconf *pathconf;\n};\n\nstruct nfs4_pnfs_ds {\n\tstruct list_head ds_node;\n\tchar *ds_remotestr;\n\tstruct list_head ds_addrs;\n\tconst struct net *ds_net;\n\tstruct nfs_client *ds_clp;\n\trefcount_t ds_count;\n\tlong unsigned int ds_state;\n};\n\nstruct nfs4_pnfs_ds_addr {\n\tstruct __kernel_sockaddr_storage da_addr;\n\tsize_t da_addrlen;\n\tstruct list_head da_node;\n\tchar *da_remotestr;\n\tconst char *da_netid;\n\tint da_transport;\n};\n\nstruct nfs4_readdir_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tu64 cookie;\n\tnfs4_verifier verifier;\n\tu32 count;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tconst u32 *bitmask;\n\tbool plus;\n};\n\nstruct nfs4_readdir_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_verifier verifier;\n\tunsigned int pgbase;\n};\n\nstruct nfs4_readlink {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs4_readlink_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_reclaim_complete_data {\n\tstruct nfs_client *clp;\n\tstruct nfs41_reclaim_complete_args arg;\n\tstruct nfs41_reclaim_complete_res res;\n};\n\nstruct rpcsec_gss_info {\n\tstruct rpcsec_gss_oid oid;\n\tu32 qop;\n\tu32 service;\n};\n\nstruct nfs4_secinfo4 {\n\tu32 flavor;\n\tstruct rpcsec_gss_info flavor_info;\n};\n\nstruct nfs4_secinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n};\n\nstruct nfs4_secinfo_flavors {\n\tunsigned int num_flavors;\n\tstruct nfs4_secinfo4 flavors[0];\n};\n\nstruct nfs4_secinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_secinfo_flavors *flavors;\n};\n\nstruct nfs4_sequence_data {\n\tstruct nfs_client *clp;\n\tstruct nfs4_sequence_args args;\n\tstruct nfs4_sequence_res res;\n};\n\nstruct nfs4_sequence_slot_ops {\n\tint (*process)(struct rpc_task *, struct nfs4_sequence_res *);\n\tint (*done)(struct rpc_task *, struct nfs4_sequence_res *);\n\tvoid (*free_slot)(struct nfs4_sequence_res *);\n};\n\nstruct nfs4_server_caps_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fhandle;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_server_caps_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 attr_bitmask[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 has_links;\n\tu32 has_symlinks;\n\tu32 fh_expire_type;\n\tu32 case_insensitive;\n\tu32 case_preserving;\n\tstruct nfs4_open_caps open_caps;\n};\n\nstruct nfs4_session;\n\nstruct nfs4_slot_table {\n\tstruct nfs4_session *session;\n\tstruct nfs4_slot *slots;\n\tlong unsigned int used_slots[16];\n\tspinlock_t slot_tbl_lock;\n\tstruct rpc_wait_queue slot_tbl_waitq;\n\twait_queue_head_t slot_waitq;\n\tu32 max_slots;\n\tu32 max_slotid;\n\tu32 highest_used_slotid;\n\tu32 target_highest_slotid;\n\tu32 server_highest_slotid;\n\ts32 d_target_highest_slotid;\n\ts32 d2_target_highest_slotid;\n\tlong unsigned int generation;\n\tstruct completion complete;\n\tlong unsigned int slot_tbl_state;\n};\n\nstruct nfs4_session {\n\tstruct nfs4_sessionid sess_id;\n\tu32 flags;\n\tlong unsigned int session_state;\n\tu32 hash_alg;\n\tu32 ssv_len;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_slot_table fc_slot_table;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tstruct nfs4_slot_table bc_slot_table;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_setclientid {\n\tconst nfs4_verifier *sc_verifier;\n\tu32 sc_prog;\n\tunsigned int sc_netid_len;\n\tchar sc_netid[6];\n\tunsigned int sc_uaddr_len;\n\tchar sc_uaddr[58];\n\tstruct nfs_client *sc_clnt;\n\tstruct rpc_cred *sc_cred;\n};\n\nstruct nfs4_setclientid_res {\n\tu64 clientid;\n\tnfs4_verifier confirm;\n};\n\nstruct nfs4_slot {\n\tstruct nfs4_slot_table *table;\n\tstruct nfs4_slot *next;\n\tlong unsigned int generation;\n\tu32 slot_nr;\n\tu32 seq_nr;\n\tu32 seq_nr_last_acked;\n\tu32 seq_nr_highest_sent;\n\tunsigned int privileged: 1;\n\tunsigned int seq_done: 1;\n};\n\nstruct nfs4_ssc_client_ops {\n\tstruct file * (*sco_open)(struct vfsmount *, struct nfs_fh *, nfs4_stateid *);\n\tvoid (*sco_close)(struct file *);\n};\n\nstruct nfs4_state {\n\tstruct list_head open_states;\n\tstruct list_head inode_states;\n\tstruct list_head lock_states;\n\tstruct nfs4_state_owner *owner;\n\tstruct inode *inode;\n\tlong unsigned int flags;\n\tspinlock_t state_lock;\n\tseqlock_t seqlock;\n\tnfs4_stateid stateid;\n\tnfs4_stateid open_stateid;\n\tunsigned int n_rdonly;\n\tunsigned int n_wronly;\n\tunsigned int n_rdwr;\n\tfmode_t state;\n\trefcount_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs4_state_maintenance_ops {\n\tint (*sched_state_renewal)(struct nfs_client *, const struct cred *, unsigned int);\n\tconst struct cred * (*get_state_renewal_cred)(struct nfs_client *);\n\tint (*renew_lease)(struct nfs_client *, const struct cred *);\n};\n\nstruct nfs4_state_owner {\n\tstruct nfs_server *so_server;\n\tstruct list_head so_lru;\n\tlong unsigned int so_expires;\n\tstruct rb_node so_server_node;\n\tconst struct cred *so_cred;\n\tspinlock_t so_lock;\n\tatomic_t so_count;\n\tlong unsigned int so_flags;\n\tstruct list_head so_states;\n\tstruct nfs_seqid_counter so_seqid;\n\tstruct mutex so_delegreturn_mutex;\n};\n\nstruct nfs4_state_recovery_ops {\n\tint owner_flag_bit;\n\tint state_flag_bit;\n\tint (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);\n\tint (*recover_lock)(struct nfs4_state *, struct file_lock *);\n\tint (*establish_clid)(struct nfs_client *, const struct cred *);\n\tint (*reclaim_complete)(struct nfs_client *, const struct cred *);\n\tint (*detect_trunking)(struct nfs_client *, struct nfs_client **, const struct cred *);\n};\n\nstruct nfs4_statfs_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsstat;\n\nstruct nfs4_statfs_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsstat *fsstat;\n};\n\nstruct nfs4_threshold {\n\t__u32 bm;\n\t__u32 l_type;\n\t__u64 rd_sz;\n\t__u64 wr_sz;\n\t__u64 rd_io_sz;\n\t__u64 wr_io_sz;\n};\n\nstruct nfs_locku_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *seqid;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs_locku_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_lock_context;\n\nstruct nfs4_unlockdata {\n\tstruct nfs_locku_args arg;\n\tstruct nfs_locku_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct file_lock fl;\n\tstruct nfs_server *server;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_xattr_cache;\n\nstruct nfs4_xattr_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n\tstruct nfs4_xattr_cache *cache;\n\tbool draining;\n};\n\nstruct nfs4_xattr_entry;\n\nstruct nfs4_xattr_cache {\n\tstruct kref ref;\n\tstruct nfs4_xattr_bucket buckets[64];\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tatomic_long_t nent;\n\tspinlock_t listxattr_lock;\n\tstruct inode *inode;\n\tstruct nfs4_xattr_entry *listxattr;\n};\n\nstruct nfs4_xattr_entry {\n\tstruct kref ref;\n\tstruct hlist_node hnode;\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tchar *xattr_name;\n\tvoid *xattr_value;\n\tsize_t xattr_size;\n\tstruct nfs4_xattr_bucket *bucket;\n\tuint32_t flags;\n};\n\nstruct nfs4_xdr_opaque_ops {\n\tvoid (*encode)(struct xdr_stream *, const void *, const struct nfs4_xdr_opaque_data *);\n\tvoid (*free)(struct nfs4_xdr_opaque_data *);\n};\n\nstruct nfs_access_entry {\n\tstruct rb_node rb_node;\n\tstruct list_head lru;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tstruct group_info *group_info;\n\tu64 timestamp;\n\t__u32 mask;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_auth_info {\n\tunsigned int flavor_len;\n\trpc_authflavor_t flavors[12];\n};\n\nstruct nfs_cache_array_entry {\n\tu64 cookie;\n\tu64 ino;\n\tconst char *name;\n\tunsigned int name_len;\n\tunsigned char d_type;\n};\n\nstruct nfs_cache_array {\n\tu64 change_attr;\n\tu64 last_cookie;\n\tunsigned int size;\n\tunsigned char folio_full: 1;\n\tunsigned char folio_is_eof: 1;\n\tunsigned char cookies_are_ordered: 1;\n\tstruct nfs_cache_array_entry array[0];\n};\n\nstruct svc_serv;\n\nstruct nfs_callback_data {\n\tunsigned int users;\n\tstruct svc_serv *serv;\n};\n\nstruct xprtsec_parms {\n\tenum xprtsec_policies policy;\n\tkey_serial_t cert_serial;\n\tkey_serial_t privkey_serial;\n};\n\nstruct nfs_rpc_ops;\n\nstruct nfs_subversion;\n\nstruct nfs_client {\n\trefcount_t cl_count;\n\tatomic_t cl_mds_count;\n\tint cl_cons_state;\n\tlong unsigned int cl_res_state;\n\tlong unsigned int cl_flags;\n\tstruct __kernel_sockaddr_storage cl_addr;\n\tsize_t cl_addrlen;\n\tchar *cl_hostname;\n\tchar *cl_acceptor;\n\tstruct list_head cl_share_link;\n\tstruct list_head cl_superblocks;\n\tstruct rpc_clnt *cl_rpcclient;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tint cl_proto;\n\tstruct nfs_subversion *cl_nfs_mod;\n\tu32 cl_minorversion;\n\tunsigned int cl_nconnect;\n\tunsigned int cl_max_connect;\n\tconst char *cl_principal;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct list_head cl_ds_clients;\n\tu64 cl_clientid;\n\tnfs4_verifier cl_confirm;\n\tlong unsigned int cl_state;\n\tspinlock_t cl_lock;\n\tlong unsigned int cl_lease_time;\n\tlong unsigned int cl_last_renewal;\n\tstruct delayed_work cl_renewd;\n\tstruct rpc_wait_queue cl_rpcwaitq;\n\tstruct idmap *cl_idmap;\n\tconst char *cl_owner_id;\n\tu32 cl_cb_ident;\n\tconst struct nfs4_minor_version_ops *cl_mvops;\n\tlong unsigned int cl_mig_gen;\n\tstruct nfs4_slot_table *cl_slot_tbl;\n\tu32 cl_seqid;\n\tu32 cl_exchange_flags;\n\tstruct nfs4_session *cl_session;\n\tbool cl_preserve_clid;\n\tstruct nfs41_server_owner *cl_serverowner;\n\tstruct nfs41_server_scope *cl_serverscope;\n\tstruct nfs41_impl_id *cl_implid;\n\tlong unsigned int cl_sp4_flags;\n\twait_queue_head_t cl_lock_waitq;\n\tchar cl_ipaddr[48];\n\tstruct net *cl_net;\n\tnetns_tracker cl_ns_tracker;\n\tstruct list_head pending_cb_stateids;\n\tstruct callback_head rcu;\n};\n\nstruct rpc_timeout;\n\nstruct nfs_client_initdata {\n\tlong unsigned int init_flags;\n\tconst char *hostname;\n\tconst struct __kernel_sockaddr_storage *addr;\n\tconst char *nodename;\n\tconst char *ip_addr;\n\tsize_t addrlen;\n\tstruct nfs_subversion *nfs_mod;\n\tint proto;\n\tu32 minorversion;\n\tunsigned int nconnect;\n\tunsigned int max_connect;\n\tstruct net *net;\n\tconst struct rpc_timeout *timeparms;\n\tconst struct cred *cred;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct nfs_clone_mount {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_commit_data;\n\nstruct nfs_commit_info;\n\nstruct nfs_page;\n\nstruct nfs_commit_completion_ops {\n\tvoid (*completion)(struct nfs_commit_data *);\n\tvoid (*resched_write)(struct nfs_commit_info *, struct nfs_page *);\n};\n\nstruct nfs_commitargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\t__u64 offset;\n\t__u32 count;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_direct_req;\n\nstruct nfs_commit_data {\n\tstruct rpc_task task;\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_writeverf verf;\n\tstruct list_head pages;\n\tstruct list_head list;\n\tstruct nfs_direct_req *dreq;\n\tstruct nfs_commitargs args;\n\tstruct nfs_commitres res;\n\tstruct nfs_open_context *context;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_index;\n\tloff_t lwb;\n\tconst struct rpc_call_ops *mds_ops;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n\tint (*commit_done_cb)(struct rpc_task *, struct nfs_commit_data *);\n\tlong unsigned int flags;\n};\n\nstruct nfs_mds_commit_info;\n\nstruct nfs_commit_info {\n\tstruct inode *inode;\n\tstruct nfs_mds_commit_info *mds;\n\tstruct pnfs_ds_commit_info *ds;\n\tstruct nfs_direct_req *dreq;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n};\n\nstruct nfs_delegation {\n\tstruct hlist_node hash;\n\tstruct list_head super_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tfmode_t type;\n\tlong unsigned int pagemod_limit;\n\t__u64 change_attr;\n\tlong unsigned int test_gen;\n\tlong unsigned int flags;\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_mds_commit_info {\n\tatomic_t rpcs_out;\n\tatomic_long_t ncommit;\n\tstruct list_head list;\n};\n\nstruct nfs_direct_req {\n\tstruct kref kref;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct kiocb *iocb;\n\tstruct inode *inode;\n\tatomic_t io_count;\n\tspinlock_t lock;\n\tloff_t io_start;\n\tssize_t count;\n\tssize_t max_count;\n\tssize_t error;\n\tstruct completion completion;\n\tstruct nfs_mds_commit_info mds_cinfo;\n\tstruct pnfs_ds_commit_info ds_cinfo;\n\tstruct work_struct work;\n\tint flags;\n};\n\nstruct nfs_entry {\n\t__u64 ino;\n\t__u64 cookie;\n\tconst char *name;\n\tunsigned int len;\n\tint eof;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tunsigned char d_type;\n\tstruct nfs_server *server;\n};\n\nstruct nfs_find_desc {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_free_stateid_data {\n\tstruct nfs_server *server;\n\tstruct nfs41_free_stateid_args args;\n\tstruct nfs41_free_stateid_res res;\n};\n\nstruct nfs_fs_context {\n\tbool internal;\n\tbool skip_reconfig_option_check;\n\tbool need_mount;\n\tbool sloppy;\n\tunsigned int flags;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tunsigned int timeo;\n\tunsigned int retrans;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namlen;\n\tunsigned int options;\n\tunsigned int bsize;\n\tstruct nfs_auth_info auth_info;\n\trpc_authflavor_t selected_flavor;\n\tstruct xprtsec_parms xprtsec;\n\tchar *client_address;\n\tunsigned int version;\n\tunsigned int minorversion;\n\tchar *fscache_uniq;\n\tshort unsigned int protofamily;\n\tshort unsigned int mountfamily;\n\tbool has_sec_mnt_opts;\n\tint lock_status;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tu32 version;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t} mount_server;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tchar *export_path;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t\tshort unsigned int nconnect;\n\t\tshort unsigned int max_connect;\n\t\tshort unsigned int export_path_len;\n\t} nfs_server;\n\tstruct nfs_fh *mntfh;\n\tstruct nfs_server *server;\n\tstruct nfs_subversion *nfs_mod;\n\tstruct nfs_clone_mount clone_data;\n};\n\nstruct nfs_fsinfo {\n\tstruct nfs_fattr *fattr;\n\t__u32 rtmax;\n\t__u32 rtpref;\n\t__u32 rtmult;\n\t__u32 wtmax;\n\t__u32 wtpref;\n\t__u32 wtmult;\n\t__u32 dtpref;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\t__u32 lease_time;\n\t__u32 nlayouttypes;\n\t__u32 layouttype[8];\n\t__u32 blksize;\n\t__u32 clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\t__u32 xattr_support;\n};\n\nstruct nfs_fsstat {\n\tstruct nfs_fattr *fattr;\n\t__u64 tbytes;\n\t__u64 fbytes;\n\t__u64 abytes;\n\t__u64 tfiles;\n\t__u64 ffiles;\n\t__u64 afiles;\n};\n\nstruct nfs_getaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_getaclres {\n\tstruct nfs4_sequence_res seq_res;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tsize_t acl_data_offset;\n\tint acl_flags;\n\tstruct folio *acl_scratch;\n};\n\nstruct nfs_inode {\n\t__u64 fileid;\n\tstruct nfs_fh fh;\n\tlong unsigned int flags;\n\tlong unsigned int cache_validity;\n\tstruct timespec64 btime;\n\tlong unsigned int read_cache_jiffies;\n\tlong unsigned int attrtimeo;\n\tlong unsigned int attrtimeo_timestamp;\n\tlong unsigned int attr_gencount;\n\tstruct rb_root access_cache;\n\tstruct list_head access_cache_entry_lru;\n\tstruct list_head access_cache_inode_lru;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int cache_change_attribute;\n\t\t\t__be32 cookieverf[2];\n\t\t\tstruct rw_semaphore rmdir_sem;\n\t\t};\n\t\tstruct {\n\t\t\tatomic_long_t nrequests;\n\t\t\tatomic_long_t redirtied_pages;\n\t\t\tstruct nfs_mds_commit_info commit_info;\n\t\t\tstruct mutex commit_mutex;\n\t\t};\n\t};\n\tstruct list_head open_files;\n\tstruct {\n\t\tint cnt;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 end;\n\t\t} gap[16];\n\t} *ooo;\n\tstruct nfs4_cached_acl *nfs4_acl;\n\tstruct list_head open_states;\n\tstruct nfs_delegation *delegation;\n\tstruct rw_semaphore rwsem;\n\tstruct pnfs_layout_hdr *layout;\n\t__u64 write_io;\n\t__u64 read_io;\n\tstruct nfs4_xattr_cache *xattr_cache;\n\tunion {\n\t\tstruct inode vfs_inode;\n\t};\n};\n\nstruct nfs_io_completion {\n\tvoid (*complete)(void *);\n\tvoid *data;\n\tstruct kref refcount;\n};\n\nstruct nfs_iostats {\n\tlong long unsigned int bytes[8];\n\tlong unsigned int events[27];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nfs_lock_context {\n\trefcount_t count;\n\tstruct list_head list;\n\tstruct nfs_open_context *open_context;\n\tfl_owner_t lockowner;\n\tatomic_t io_count;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_lockt_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_lockt_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct file_lock *denied;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct nfs_mount_data {\n\tint version;\n\tint fd;\n\tstruct nfs2_fh old_root;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct sockaddr_in addr;\n\tchar hostname[256];\n\tint namlen;\n\tunsigned int bsize;\n\tstruct nfs3_fh root;\n\tint pseudoflavor;\n\tchar context[257];\n};\n\nstruct nfs_mount_request {\n\tstruct __kernel_sockaddr_storage *sap;\n\tsize_t salen;\n\tchar *hostname;\n\tchar *dirpath;\n\tu32 version;\n\tshort unsigned int protocol;\n\tstruct nfs_fh *fh;\n\tint noresvport;\n\tunsigned int *auth_flav_len;\n\trpc_authflavor_t *auth_flavs;\n\tstruct net *net;\n};\n\nstruct rpc_program;\n\nstruct rpc_stat {\n\tconst struct rpc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int netreconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcretrans;\n\tunsigned int rpcauthrefresh;\n\tunsigned int rpcgarbage;\n};\n\nstruct nfs_netns_client;\n\nstruct nfs_net {\n\tstruct cache_detail *nfs_dns_resolve;\n\tstruct rpc_pipe *bl_device_pipe;\n\tstruct bl_dev_msg bl_mount_reply;\n\twait_queue_head_t bl_wq;\n\tstruct mutex bl_mutex;\n\tstruct list_head nfs_client_list;\n\tstruct list_head nfs_volume_list;\n\tstruct idr cb_ident_idr;\n\tshort unsigned int nfs_callback_tcpport;\n\tshort unsigned int nfs_callback_tcpport6;\n\tint cb_users[3];\n\tstruct list_head nfs4_data_server_cache;\n\tspinlock_t nfs4_data_server_lock;\n\tstruct nfs_netns_client *nfs_client;\n\tspinlock_t nfs_client_lock;\n\tktime_t boot_time;\n\tstruct rpc_stat rpcstats;\n\tstruct proc_dir_entry *proc_nfsfs;\n};\n\nstruct nfs_netns_client {\n\tstruct kobject kobject;\n\tstruct kobject nfs_net_kobj;\n\tstruct net *net;\n\tconst char *identifier;\n};\n\nstruct nfs_open_context {\n\tstruct nfs_lock_context lock_context;\n\tfl_owner_t flock_owner;\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\tstruct rpc_cred *ll_cred;\n\tstruct nfs4_state *state;\n\tfmode_t mode;\n\tint error;\n\tlong unsigned int flags;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tstruct nfs_file_localio nfl;\n};\n\nstruct nfs_open_dir_context {\n\tstruct list_head list;\n\tatomic_t cache_hits;\n\tatomic_t cache_misses;\n\tlong unsigned int attr_gencount;\n\t__be32 verf[2];\n\t__u64 dir_cookie;\n\t__u64 last_cookie;\n\tlong unsigned int page_index;\n\tunsigned int dtsize;\n\tbool force_clear;\n\tbool eof;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_page {\n\tstruct list_head wb_list;\n\tunion {\n\t\tstruct page *wb_page;\n\t\tstruct folio *wb_folio;\n\t};\n\tstruct nfs_lock_context *wb_lock_context;\n\tlong unsigned int wb_index;\n\tunsigned int wb_offset;\n\tunsigned int wb_pgbase;\n\tunsigned int wb_bytes;\n\tstruct kref wb_kref;\n\tlong unsigned int wb_flags;\n\tstruct nfs_write_verifier wb_verf;\n\tstruct nfs_page *wb_this_page;\n\tstruct nfs_page *wb_head;\n\tshort unsigned int wb_nio;\n};\n\nstruct nfs_page_array {\n\tstruct page **pagevec;\n\tunsigned int npages;\n\tstruct page *page_array[8];\n};\n\nstruct nfs_page_iter_page {\n\tconst struct nfs_page *req;\n\tsize_t count;\n};\n\nstruct nfs_pgio_mirror {\n\tstruct list_head pg_list;\n\tlong unsigned int pg_bytes_written;\n\tsize_t pg_count;\n\tsize_t pg_bsize;\n\tunsigned int pg_base;\n\tunsigned char pg_recoalesce: 1;\n};\n\nstruct nfs_pageio_ops;\n\nstruct nfs_rw_ops;\n\nstruct nfs_pgio_completion_ops;\n\nstruct nfs_pageio_descriptor {\n\tstruct inode *pg_inode;\n\tconst struct nfs_pageio_ops *pg_ops;\n\tconst struct nfs_rw_ops *pg_rw_ops;\n\tint pg_ioflags;\n\tint pg_error;\n\tconst struct rpc_call_ops *pg_rpc_callops;\n\tconst struct nfs_pgio_completion_ops *pg_completion_ops;\n\tstruct pnfs_layout_segment *pg_lseg;\n\tstruct nfs_io_completion *pg_io_completion;\n\tstruct nfs_direct_req *pg_dreq;\n\tunsigned int pg_bsize;\n\tu32 pg_mirror_count;\n\tstruct nfs_pgio_mirror *pg_mirrors;\n\tstruct nfs_pgio_mirror pg_mirrors_static[1];\n\tstruct nfs_pgio_mirror *pg_mirrors_dynamic;\n\tu32 pg_mirror_idx;\n\tshort unsigned int pg_maxretrans;\n\tunsigned char pg_moreio: 1;\n};\n\nstruct nfs_pageio_ops {\n\tvoid (*pg_init)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tsize_t (*pg_test)(struct nfs_pageio_descriptor *, struct nfs_page *, struct nfs_page *);\n\tint (*pg_doio)(struct nfs_pageio_descriptor *);\n\tunsigned int (*pg_get_mirror_count)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tvoid (*pg_cleanup)(struct nfs_pageio_descriptor *);\n\tstruct nfs_pgio_mirror * (*pg_get_mirror)(struct nfs_pageio_descriptor *, u32);\n\tu32 (*pg_set_mirror)(struct nfs_pageio_descriptor *, u32);\n};\n\nstruct nfs_pathconf {\n\tstruct nfs_fattr *fattr;\n\t__u32 max_link;\n\t__u32 max_namelen;\n};\n\nstruct nfs_pgio_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct nfs_open_context *context;\n\tstruct nfs_lock_context *lock_context;\n\tnfs4_stateid stateid;\n\t__u64 offset;\n\t__u32 count;\n\tunsigned int pgbase;\n\tstruct page **pages;\n\tunion {\n\t\tunsigned int replen;\n\t\tstruct {\n\t\t\tconst u32 *bitmask;\n\t\t\tu32 bitmask_store[3];\n\t\t\tenum nfs3_stable_how stable;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header;\n\nstruct nfs_pgio_completion_ops {\n\tvoid (*error_cleanup)(struct list_head *, int);\n\tvoid (*init_hdr)(struct nfs_pgio_header *);\n\tvoid (*completion)(struct nfs_pgio_header *);\n\tvoid (*reschedule_io)(struct nfs_pgio_header *);\n};\n\nstruct nfs_pgio_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\t__u64 count;\n\t__u32 op_status;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int replen;\n\t\t\tint eof;\n\t\t\tvoid *scratch;\n\t\t};\n\t\tstruct {\n\t\t\tstruct nfs_writeverf *verf;\n\t\t\tconst struct nfs_server *server;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header {\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct list_head pages;\n\tstruct nfs_page *req;\n\tstruct nfs_writeverf verf;\n\tfmode_t rw_mode;\n\tstruct pnfs_layout_segment *lseg;\n\tloff_t io_start;\n\tconst struct rpc_call_ops *mds_ops;\n\tvoid (*release)(struct nfs_pgio_header *);\n\tconst struct nfs_pgio_completion_ops *completion_ops;\n\tconst struct nfs_rw_ops *rw_ops;\n\tstruct nfs_io_completion *io_completion;\n\tstruct nfs_direct_req *dreq;\n\tshort unsigned int retrans;\n\tint pnfs_error;\n\tint error;\n\tunsigned int good_bytes;\n\tlong unsigned int flags;\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_pgio_args args;\n\tstruct nfs_pgio_res res;\n\tlong unsigned int timestamp;\n\tint (*pgio_done_cb)(struct rpc_task *, struct nfs_pgio_header *);\n\t__u64 mds_offset;\n\tstruct nfs_page_array page_array;\n\tstruct nfs_client *ds_clp;\n\tu32 ds_commit_idx;\n\tu32 pgio_mirror_idx;\n};\n\nstruct nfs_readdir_arg {\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\t__be32 *verf;\n\tu64 cookie;\n\tstruct page **pages;\n\tunsigned int page_len;\n\tbool plus;\n};\n\nstruct nfs_readdir_descriptor {\n\tstruct file *file;\n\tstruct folio *folio;\n\tstruct dir_context *ctx;\n\tlong unsigned int folio_index;\n\tlong unsigned int folio_index_max;\n\tu64 dir_cookie;\n\tu64 last_cookie;\n\tloff_t current_index;\n\t__be32 verf[2];\n\tlong unsigned int dir_verifier;\n\tlong unsigned int timestamp;\n\tlong unsigned int gencount;\n\tlong unsigned int attr_gencount;\n\tunsigned int cache_entry_index;\n\tunsigned int buffer_fills;\n\tunsigned int dtsize;\n\tbool clear_cache;\n\tbool plus;\n\tbool eob;\n\tbool eof;\n};\n\nstruct nfs_readdir_res {\n\t__be32 *verf;\n};\n\nstruct nfs_referral_count {\n\tstruct list_head list;\n\tconst struct task_struct *task;\n\tunsigned int referral_count;\n};\n\nstruct nfs_removeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct qstr name;\n};\n\nstruct nfs_removeres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs_renameargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *old_dir;\n\tconst struct nfs_fh *new_dir;\n\tconst struct qstr *old_name;\n\tconst struct qstr *new_name;\n};\n\nstruct nfs_renameres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs4_change_info old_cinfo;\n\tstruct nfs_fattr *old_fattr;\n\tstruct nfs4_change_info new_cinfo;\n\tstruct nfs_fattr *new_fattr;\n};\n\nstruct nfs_renamedata {\n\tstruct nfs_renameargs args;\n\tstruct nfs_renameres res;\n\tstruct rpc_task task;\n\tconst struct cred *cred;\n\tstruct inode *old_dir;\n\tstruct dentry *old_dentry;\n\tstruct nfs_fattr old_fattr;\n\tstruct inode *new_dir;\n\tstruct dentry *new_dentry;\n\tstruct nfs_fattr new_fattr;\n\tvoid (*complete)(struct rpc_task *, struct nfs_renamedata *);\n\tlong int timeout;\n\tbool cancelled;\n};\n\nstruct nlmclnt_operations;\n\nstruct nfs_unlinkdata;\n\nstruct nfs_rpc_ops {\n\tu32 version;\n\tconst struct dentry_operations *dentry_ops;\n\tconst struct inode_operations *dir_inode_ops;\n\tconst struct inode_operations *file_inode_ops;\n\tconst struct file_operations *file_ops;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tint (*getroot)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*submount)(struct fs_context *, struct nfs_server *);\n\tint (*try_get_tree)(struct fs_context *);\n\tint (*getattr)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, struct inode *);\n\tint (*setattr)(struct dentry *, struct nfs_fattr *, struct iattr *);\n\tint (*lookup)(struct inode *, struct dentry *, const struct qstr *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*lookupp)(struct inode *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*access)(struct inode *, struct nfs_access_entry *, const struct cred *);\n\tint (*readlink)(struct inode *, struct page *, unsigned int, unsigned int);\n\tint (*create)(struct inode *, struct dentry *, struct iattr *, int);\n\tint (*remove)(struct inode *, struct dentry *);\n\tvoid (*unlink_setup)(struct rpc_message *, struct dentry *, struct inode *);\n\tvoid (*unlink_rpc_prepare)(struct rpc_task *, struct nfs_unlinkdata *);\n\tint (*unlink_done)(struct rpc_task *, struct inode *);\n\tvoid (*rename_setup)(struct rpc_message *, struct dentry *, struct dentry *, struct inode *);\n\tvoid (*rename_rpc_prepare)(struct rpc_task *, struct nfs_renamedata *);\n\tint (*rename_done)(struct rpc_task *, struct inode *, struct inode *);\n\tint (*link)(struct inode *, struct inode *, const struct qstr *);\n\tint (*symlink)(struct inode *, struct dentry *, struct folio *, unsigned int, struct iattr *);\n\tstruct dentry * (*mkdir)(struct inode *, struct dentry *, struct iattr *);\n\tint (*rmdir)(struct inode *, const struct qstr *);\n\tint (*readdir)(struct nfs_readdir_arg *, struct nfs_readdir_res *);\n\tint (*mknod)(struct inode *, struct dentry *, struct iattr *, dev_t);\n\tint (*statfs)(struct nfs_server *, struct nfs_fh *, struct nfs_fsstat *);\n\tint (*fsinfo)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*pathconf)(struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *);\n\tint (*set_capabilities)(struct nfs_server *, struct nfs_fh *);\n\tint (*decode_dirent)(struct xdr_stream *, struct nfs_entry *, bool);\n\tint (*pgio_rpc_prepare)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*read_setup)(struct nfs_pgio_header *, struct rpc_message *);\n\tint (*read_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*write_setup)(struct nfs_pgio_header *, struct rpc_message *, struct rpc_clnt **);\n\tint (*write_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*commit_setup)(struct nfs_commit_data *, struct rpc_message *, struct rpc_clnt **);\n\tvoid (*commit_rpc_prepare)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*commit_done)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tint (*lock_check_bounds)(const struct file_lock *);\n\tvoid (*clear_acl_cache)(struct inode *);\n\tvoid (*close_context)(struct nfs_open_context *, int);\n\tstruct inode * (*open_context)(struct inode *, struct nfs_open_context *, int, struct iattr *, int *);\n\tint (*have_delegation)(struct inode *, fmode_t, int);\n\tvoid (*return_delegation)(struct inode *);\n\tstruct nfs_client * (*alloc_client)(const struct nfs_client_initdata *);\n\tstruct nfs_client * (*init_client)(struct nfs_client *, const struct nfs_client_initdata *);\n\tvoid (*free_client)(struct nfs_client *);\n\tstruct nfs_server * (*create_server)(struct fs_context *);\n\tstruct nfs_server * (*clone_server)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, rpc_authflavor_t);\n\tint (*discover_trunking)(struct nfs_server *, struct nfs_fh *);\n\tvoid (*enable_swap)(struct inode *);\n\tvoid (*disable_swap)(struct inode *);\n};\n\nstruct rpc_task_setup;\n\nstruct nfs_rw_ops {\n\tstruct nfs_pgio_header * (*rw_alloc_header)(void);\n\tvoid (*rw_free_header)(struct nfs_pgio_header *);\n\tint (*rw_done)(struct rpc_task *, struct nfs_pgio_header *, struct inode *);\n\tvoid (*rw_result)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*rw_initiate)(struct nfs_pgio_header *, struct rpc_message *, const struct nfs_rpc_ops *, struct rpc_task_setup *, int);\n};\n\nstruct nfs_seqid {\n\tstruct nfs_seqid_counter *sequence;\n\tstruct list_head list;\n\tstruct rpc_task *task;\n};\n\nstruct nlm_host;\n\nstruct nfs_server {\n\tstruct nfs_client *nfs_client;\n\tstruct list_head client_link;\n\tstruct list_head master_link;\n\tstruct rpc_clnt *client;\n\tstruct rpc_clnt *client_acl;\n\tstruct nlm_host *nlm_host;\n\tstruct nfs_iostats *io_stats;\n\twait_queue_head_t write_congestion_wait;\n\tatomic_long_t writeback;\n\tunsigned int write_congested;\n\tunsigned int flags;\n\tunsigned int automount_inherit;\n\tunsigned int caps;\n\t__u64 fattr_valid;\n\tunsigned int rsize;\n\tunsigned int rpages;\n\tunsigned int wsize;\n\tunsigned int wtmult;\n\tunsigned int dtsize;\n\tshort unsigned int port;\n\tunsigned int bsize;\n\tunsigned int gxasize;\n\tunsigned int sxasize;\n\tunsigned int lxasize;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namelen;\n\tunsigned int options;\n\tunsigned int clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\tstruct nfs_fsid fsid;\n\tint s_sysfs_id;\n\t__u64 maxfilesize;\n\tlong unsigned int mount_time;\n\tstruct super_block *super;\n\tdev_t s_dev;\n\tstruct nfs_auth_info auth_info;\n\tu32 fh_expire_type;\n\tu32 pnfs_blksize;\n\tu32 attr_bitmask[3];\n\tu32 attr_bitmask_nl[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 cache_consistency_bitmask[3];\n\tu32 acl_bitmask;\n\tstruct pnfs_layoutdriver_type *pnfs_curr_ld;\n\tstruct rpc_wait_queue roc_rpcwaitq;\n\tstruct rb_root state_owners;\n\tatomic64_t owner_ctr;\n\tstruct list_head state_owners_lru;\n\tstruct list_head layouts;\n\tstruct list_head delegations;\n\tspinlock_t delegations_lock;\n\tstruct list_head delegations_return;\n\tstruct list_head delegations_lru;\n\tstruct list_head delegations_delayed;\n\tatomic_long_t nr_active_delegations;\n\tunsigned int delegation_hash_mask;\n\tstruct hlist_head *delegation_hash_table;\n\tstruct list_head ss_copies;\n\tstruct list_head ss_src_copies;\n\tlong unsigned int delegation_flags;\n\tlong unsigned int delegation_gen;\n\tlong unsigned int mig_gen;\n\tlong unsigned int mig_status;\n\tvoid (*destroy)(struct nfs_server *);\n\tatomic_t active;\n\tstruct __kernel_sockaddr_storage mountd_address;\n\tsize_t mountd_addrlen;\n\tu32 mountd_version;\n\tshort unsigned int mountd_port;\n\tshort unsigned int mountd_protocol;\n\tstruct rpc_wait_queue uoc_rpcwaitq;\n\tunsigned int read_hdrsize;\n\tconst struct cred *cred;\n\tbool has_sec_mnt_opts;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_setaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_setaclres {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs_setattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct iattr *iap;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n};\n\nstruct nfs_setattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs_ssc_client_ops {\n\tvoid (*sco_sb_deactive)(struct super_block *);\n};\n\nstruct nfs_ssc_client_ops_tbl {\n\tconst struct nfs4_ssc_client_ops *ssc_nfs4_ops;\n\tconst struct nfs_ssc_client_ops *ssc_nfs_ops;\n};\n\nstruct rpc_version;\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct nfs_subversion {\n\tstruct module *owner;\n\tstruct file_system_type *nfs_fs;\n\tconst struct rpc_version *rpc_vers;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tconst struct super_operations *sops;\n\tconst struct xattr_handler * const *xattr;\n};\n\nstruct nfs_unlinkdata {\n\tstruct nfs_removeargs args;\n\tstruct nfs_removeres res;\n\tstruct dentry *dentry;\n\twait_queue_head_t wq;\n\tconst struct cred *cred;\n\tstruct nfs_fattr dir_attr;\n\tlong int timeout;\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhlist_head;\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlm_cookie {\n\tunsigned char data[32];\n\tunsigned int len;\n};\n\nstruct xdr_netobj {\n\tunsigned int len;\n\tu8 *data;\n};\n\nstruct nlm_lock {\n\tchar *caller;\n\tunsigned int len;\n\tstruct nfs_fh fh;\n\tstruct xdr_netobj oh;\n\tu32 svid;\n\tu64 lock_start;\n\tu64 lock_len;\n\tstruct file_lock fl;\n};\n\nstruct nlm_args {\n\tstruct nlm_cookie cookie;\n\tstruct nlm_lock lock;\n\tu32 block;\n\tu32 reclaim;\n\tu32 state;\n\tu32 monitor;\n\tu32 fsm_access;\n\tu32 fsm_mode;\n};\n\nstruct nlm_rqst;\n\nstruct nlm_file;\n\nstruct nlm_block {\n\tstruct kref b_count;\n\tstruct list_head b_list;\n\tstruct list_head b_flist;\n\tstruct nlm_rqst *b_call;\n\tstruct svc_serv *b_daemon;\n\tstruct nlm_host *b_host;\n\tlong unsigned int b_when;\n\tunsigned int b_id;\n\tunsigned char b_granted;\n\tstruct nlm_file *b_file;\n\tstruct cache_req *b_cache_req;\n\tstruct cache_deferred_req *b_deferred_req;\n\tunsigned int b_flags;\n};\n\nstruct nlm_share;\n\nstruct nlm_file {\n\tstruct hlist_node f_list;\n\tstruct nfs_fh f_handle;\n\tstruct file *f_file[2];\n\tstruct nlm_share *f_shares;\n\tstruct list_head f_blocks;\n\tunsigned int f_locks;\n\tunsigned int f_count;\n\tstruct mutex f_mutex;\n};\n\nstruct nsm_handle;\n\nstruct nlm_host {\n\tstruct hlist_node h_hash;\n\tstruct __kernel_sockaddr_storage h_addr;\n\tsize_t h_addrlen;\n\tstruct __kernel_sockaddr_storage h_srcaddr;\n\tsize_t h_srcaddrlen;\n\tstruct rpc_clnt *h_rpcclnt;\n\tchar *h_name;\n\tu32 h_version;\n\tshort unsigned int h_proto;\n\tshort unsigned int h_reclaiming: 1;\n\tshort unsigned int h_server: 1;\n\tshort unsigned int h_noresvport: 1;\n\tshort unsigned int h_inuse: 1;\n\twait_queue_head_t h_gracewait;\n\tstruct rw_semaphore h_rwsem;\n\tu32 h_state;\n\tu32 h_nsmstate;\n\tu32 h_pidcount;\n\trefcount_t h_count;\n\tstruct mutex h_mutex;\n\tlong unsigned int h_nextrebind;\n\tlong unsigned int h_expires;\n\tstruct list_head h_lockowners;\n\tspinlock_t h_lock;\n\tstruct list_head h_granted;\n\tstruct list_head h_reclaim;\n\tstruct nsm_handle *h_nsmhandle;\n\tchar *h_addrbuf;\n\tstruct net *net;\n\tconst struct cred *h_cred;\n\tchar nodename[65];\n\tconst struct nlmclnt_operations *h_nlmclnt_ops;\n};\n\nstruct nlm_lockowner {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct nlm_host *host;\n\tfl_owner_t owner;\n\tuint32_t pid;\n};\n\nstruct nlm_lookup_host_info {\n\tconst int server;\n\tconst struct sockaddr *sap;\n\tconst size_t salen;\n\tconst short unsigned int protocol;\n\tconst u32 version;\n\tconst char *hostname;\n\tconst size_t hostname_len;\n\tconst int noresvport;\n\tstruct net *net;\n\tconst struct cred *cred;\n};\n\nstruct nsm_private {\n\tunsigned char data[16];\n};\n\nstruct nlm_reboot {\n\tchar *mon;\n\tunsigned int len;\n\tu32 state;\n\tstruct nsm_private priv;\n};\n\nstruct nlm_res {\n\tstruct nlm_cookie cookie;\n\t__be32 status;\n\tstruct nlm_lock lock;\n};\n\nstruct nlm_rqst {\n\trefcount_t a_count;\n\tunsigned int a_flags;\n\tstruct nlm_host *a_host;\n\tstruct nlm_args a_args;\n\tstruct nlm_res a_res;\n\tstruct nlm_block *a_block;\n\tunsigned int a_retries;\n\tu8 a_owner[74];\n\tvoid *a_callback_data;\n};\n\nstruct nlm_share {\n\tstruct nlm_share *s_next;\n\tstruct nlm_host *s_host;\n\tstruct nlm_file *s_file;\n\tstruct xdr_netobj s_owner;\n\tu32 s_access;\n\tu32 s_mode;\n};\n\nstruct nlm_wait {\n\tstruct list_head b_list;\n\twait_queue_head_t b_wait;\n\tstruct nlm_host *b_host;\n\tstruct file_lock *b_lock;\n\t__be32 b_status;\n};\n\nstruct nlmclnt_initdata {\n\tconst char *hostname;\n\tconst struct sockaddr *address;\n\tsize_t addrlen;\n\tshort unsigned int protocol;\n\tu32 nfs_version;\n\tint noresvport;\n\tstruct net *net;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tconst struct cred *cred;\n};\n\nstruct nlmclnt_operations {\n\tvoid (*nlmclnt_alloc_call)(void *);\n\tbool (*nlmclnt_unlock_prepare)(struct rpc_task *, void *);\n\tvoid (*nlmclnt_release_call)(void *);\n};\n\nstruct nlmsg_perm {\n\tu16 nlmsg_type;\n\tu32 perm;\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nlmsvc_binding {\n\t__be32 (*fopen)(struct svc_rqst *, struct nfs_fh *, struct file **, int);\n\tvoid (*fclose)(struct file *);\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\nstruct node {\n\tstruct device dev;\n\tstruct list_head access_list;\n};\n\nstruct node_access_nodes {\n\tstruct device dev;\n\tstruct list_head list_node;\n\tunsigned int access;\n};\n\nstruct node_attr {\n\tstruct device_attribute attr;\n\tenum node_states state;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_hstate {\n\tstruct kobject *hugepages_kobj;\n\tstruct kobject *hstate_kobjs[3];\n};\n\nstruct node_memory_type_map {\n\tstruct memory_dev_type *memtype;\n\tint map_count;\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct nodemask_scratch {\n\tnodemask_t mask1;\n\tnodemask_t mask2;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct nsm_args {\n\tstruct nsm_private *priv;\n\tu32 prog;\n\tu32 vers;\n\tu32 proc;\n\tchar *mon_name;\n\tconst char *nodename;\n};\n\nstruct nsm_handle {\n\tstruct list_head sm_link;\n\trefcount_t sm_count;\n\tchar *sm_mon_name;\n\tchar *sm_name;\n\tstruct __kernel_sockaddr_storage sm_addr;\n\tsize_t sm_addrlen;\n\tunsigned int sm_monitored: 1;\n\tunsigned int sm_sticky: 1;\n\tstruct nsm_private sm_priv;\n\tchar sm_addrbuf[51];\n};\n\nstruct nsm_res {\n\tu32 status;\n\tu32 state;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n} __attribute__((packed));\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t drops1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct numa_group {\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tint nr_tasks;\n\tpid_t gid;\n\tint active_nodes;\n\tstruct callback_head rcu;\n\tlong unsigned int total_faults;\n\tlong unsigned int max_faults_cpu;\n\tlong unsigned int faults[0];\n};\n\nstruct numa_maps {\n\tlong unsigned int pages;\n\tlong unsigned int anon;\n\tlong unsigned int active;\n\tlong unsigned int writeback;\n\tlong unsigned int mapcount_max;\n\tlong unsigned int dirty;\n\tlong unsigned int swapcache;\n\tlong unsigned int node[4];\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n\tbool mmap_locked;\n\tstruct vm_area_struct *locked_vma;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tstruct mempolicy *task_mempolicy;\n};\n\nstruct numa_maps_private {\n\tstruct proc_maps_private proc_maps;\n\tstruct numa_maps md;\n};\n\nstruct numa_memblk {\n\tu64 start;\n\tu64 end;\n\tint nid;\n};\n\nstruct numa_meminfo {\n\tint nr_blks;\n\tstruct numa_memblk blk[8];\n};\n\nstruct numa_stats {\n\tlong unsigned int load;\n\tlong unsigned int runnable;\n\tlong unsigned int util;\n\tlong unsigned int compute_capacity;\n\tunsigned int nr_running;\n\tunsigned int weight;\n\tenum numa_type node_type;\n\tint idle_cpu;\n};\n\nstruct nvdimm_security_ops;\n\nstruct nvdimm_fw_ops;\n\nstruct nvdimm {\n\tlong unsigned int flags;\n\tvoid *provider_data;\n\tlong unsigned int cmd_mask;\n\tstruct device dev;\n\tatomic_t busy;\n\tint id;\n\tint num_flush;\n\tstruct resource *flush_wpq;\n\tconst char *dimm_id;\n\tstruct {\n\t\tconst struct nvdimm_security_ops *ops;\n\t\tlong unsigned int flags;\n\t\tlong unsigned int ext_flags;\n\t\tunsigned int overwrite_tmo;\n\t\tstruct kernfs_node *overwrite_state;\n\t} sec;\n\tstruct delayed_work dwork;\n\tconst struct nvdimm_fw_ops *fw_ops;\n};\n\nstruct nvdimm_bus_descriptor;\n\nstruct nvdimm_bus {\n\tstruct nvdimm_bus_descriptor *nd_desc;\n\twait_queue_head_t wait;\n\tstruct list_head list;\n\tstruct device dev;\n\tint id;\n\tint probe_active;\n\tatomic_t ioctl_active;\n\tstruct list_head mapping_list;\n\tstruct mutex reconfig_mutex;\n\tstruct badrange badrange;\n};\n\ntypedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *, struct nvdimm *, unsigned int, void *, unsigned int, int *);\n\nstruct nvdimm_bus_fw_ops;\n\nstruct nvdimm_bus_descriptor {\n\tconst struct attribute_group **attr_groups;\n\tlong unsigned int cmd_mask;\n\tlong unsigned int dimm_family_mask;\n\tlong unsigned int bus_family_mask;\n\tstruct module *module;\n\tchar *provider_name;\n\tstruct device_node *of_node;\n\tndctl_fn ndctl;\n\tint (*flush_probe)(struct nvdimm_bus_descriptor *);\n\tint (*clear_to_send)(struct nvdimm_bus_descriptor *, struct nvdimm *, unsigned int, void *);\n\tconst struct nvdimm_bus_fw_ops *fw_ops;\n};\n\nstruct nvdimm_bus_fw_ops {\n\tenum nvdimm_fwa_state (*activate_state)(struct nvdimm_bus_descriptor *);\n\tenum nvdimm_fwa_capability (*capability)(struct nvdimm_bus_descriptor *);\n\tint (*activate)(struct nvdimm_bus_descriptor *);\n};\n\nstruct nvdimm_drvdata {\n\tstruct device *dev;\n\tint nslabel_size;\n\tstruct nd_cmd_get_config_size nsarea;\n\tvoid *data;\n\tbool cxl;\n\tint ns_current;\n\tint ns_next;\n\tstruct resource dpa;\n\tstruct kref kref;\n};\n\nstruct nvdimm_fw_ops {\n\tenum nvdimm_fwa_state (*activate_state)(struct nvdimm *);\n\tenum nvdimm_fwa_result (*activate_result)(struct nvdimm *);\n\tint (*arm)(struct nvdimm *, enum nvdimm_fwa_trigger);\n};\n\nstruct nvdimm_key_data {\n\tu8 data[32];\n};\n\nstruct nvdimm_map {\n\tstruct nvdimm_bus *nvdimm_bus;\n\tstruct list_head list;\n\tresource_size_t offset;\n\tlong unsigned int flags;\n\tsize_t size;\n\tunion {\n\t\tvoid *mem;\n\t\tvoid *iomem;\n\t};\n\tstruct kref kref;\n};\n\nstruct perf_cpu_pmu_context;\n\nstruct perf_event_pmu_context;\n\nstruct perf_output_handle;\n\nstruct pmu {\n\tstruct list_head entry;\n\tspinlock_t events_lock;\n\tstruct list_head events;\n\tstruct module *module;\n\tstruct device *dev;\n\tstruct device *parent;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tunsigned int scope;\n\tstruct perf_cpu_pmu_context **cpu_pmu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tstruct kmem_cache *task_ctx_cache;\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tbool (*filter)(struct pmu *, int);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\nstruct nvdimm_pmu {\n\tstruct pmu pmu;\n\tstruct device *dev;\n\tint cpu;\n\tstruct hlist_node node;\n\tenum cpuhp_state cpuhp_state;\n\tstruct cpumask arch_cpumask;\n};\n\nstruct nvdimm_security_ops {\n\tlong unsigned int (*get_flags)(struct nvdimm *, enum nvdimm_passphrase_type);\n\tint (*freeze)(struct nvdimm *);\n\tint (*change_key)(struct nvdimm *, const struct nvdimm_key_data *, const struct nvdimm_key_data *, enum nvdimm_passphrase_type);\n\tint (*unlock)(struct nvdimm *, const struct nvdimm_key_data *);\n\tint (*disable)(struct nvdimm *, const struct nvdimm_key_data *);\n\tint (*erase)(struct nvdimm *, const struct nvdimm_key_data *, enum nvdimm_passphrase_type);\n\tint (*overwrite)(struct nvdimm *, const struct nvdimm_key_data *);\n\tint (*query_overwrite)(struct nvdimm *);\n\tint (*disable_master)(struct nvdimm *, const struct nvdimm_key_data *);\n};\n\nstruct nvmem_cell_entry;\n\nstruct nvmem_cell {\n\tstruct nvmem_cell_entry *entry;\n\tconst char *id;\n\tint index;\n};\n\ntypedef int (*nvmem_cell_post_process_t)(void *, const char *, int, unsigned int, void *, size_t);\n\nstruct nvmem_cell_entry {\n\tconst char *name;\n\tint offset;\n\tsize_t raw_len;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n\tstruct device_node *np;\n\tstruct nvmem_device *nvmem;\n\tstruct list_head node;\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tsize_t raw_len;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n\tstruct device_node *np;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n};\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nstruct nvmem_keepout;\n\nstruct nvmem_layout;\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tbool add_legacy_fixed_of_cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool ignore_wp;\n\tstruct nvmem_layout *layout;\n\tstruct device_node *of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device {\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct list_head node;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tstruct nvmem_layout *layout;\n\tvoid *priv;\n\tbool sysfs_cells_populated;\n};\n\nstruct nvmem_keepout {\n\tunsigned int start;\n\tunsigned int end;\n\tunsigned char value;\n};\n\nstruct nvmem_layout {\n\tstruct device dev;\n\tstruct nvmem_device *nvmem;\n\tint (*add_cells)(struct nvmem_layout *);\n};\n\nstruct nvmem_layout_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct nvmem_layout *);\n\tvoid (*remove)(struct nvmem_layout *);\n};\n\nstruct nvs_region {\n\t__u64 phys_start;\n\t__u64 size;\n\tstruct list_head node;\n};\n\nstruct obj_cgroup {\n\tstruct percpu_ref refcnt;\n\tstruct mem_cgroup *memcg;\n\tatomic_t nr_charged_bytes;\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct obj_stock_pcp {\n\tlocal_trylock_t lock;\n\tunsigned int nr_bytes;\n\tstruct obj_cgroup *cached_objcg;\n\tstruct pglist_data *cached_pgdat;\n\tint nr_slab_reclaimable_b;\n\tint nr_slab_unreclaimable_b;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct ocontext {\n\tunion {\n\t\tchar *name;\n\t\tstruct {\n\t\t\tu8 protocol;\n\t\t\tu16 low_port;\n\t\t\tu16 high_port;\n\t\t} port;\n\t\tstruct {\n\t\t\tu32 addr;\n\t\t\tu32 mask;\n\t\t} node;\n\t\tstruct {\n\t\t\tu32 addr[4];\n\t\t\tu32 mask[4];\n\t\t} node6;\n\t\tstruct {\n\t\t\tu64 subnet_prefix;\n\t\t\tu16 low_pkey;\n\t\t\tu16 high_pkey;\n\t\t} ibpkey;\n\t\tstruct {\n\t\t\tchar *dev_name;\n\t\t\tu8 port;\n\t\t} ibendport;\n\t} u;\n\tunion {\n\t\tu32 sclass;\n\t\tu32 behavior;\n\t} v;\n\tstruct context context[2];\n\tu32 sid[2];\n\tstruct ocontext *next;\n};\n\nstruct od_dbs_tuners {\n\tunsigned int powersave_bias;\n};\n\nstruct od_ops {\n\tunsigned int (*powersave_bias_target)(struct cpufreq_policy *, unsigned int, unsigned int);\n};\n\nstruct policy_dbs_info {\n\tstruct cpufreq_policy *policy;\n\tstruct mutex update_mutex;\n\tu64 last_sample_time;\n\ts64 sample_delay_ns;\n\tatomic_t work_count;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\tstruct dbs_data *dbs_data;\n\tstruct list_head list;\n\tunsigned int rate_mult;\n\tunsigned int idle_periods;\n\tbool is_shared;\n\tbool work_in_progress;\n};\n\nstruct od_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int freq_lo;\n\tunsigned int freq_lo_delay_us;\n\tunsigned int freq_hi_delay_us;\n\tunsigned int sample_type: 1;\n};\n\nstruct of_bus {\n\tvoid (*count_cells)(const void *, int, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n};\n\nstruct of_bus___2 {\n\tconst char *name;\n\tconst char *addresses;\n\tint (*match)(struct device_node *);\n\tvoid (*count_cells)(struct device_node *, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n\tint flag_cells;\n\tunsigned int (*get_flags)(const __be32 *);\n};\n\nstruct of_clk_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n\tstruct clk * (*get)(struct of_phandle_args *, void *);\n\tstruct clk_hw * (*get_hw)(struct of_phandle_args *, void *);\n\tvoid *data;\n};\n\nstruct of_dev_auxdata {\n\tchar *compatible;\n\tresource_size_t phys_addr;\n\tchar *name;\n\tvoid *platform_data;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_dma {\n\tstruct list_head of_dma_controllers;\n\tstruct device_node *of_node;\n\tstruct dma_chan * (*of_dma_xlate)(struct of_phandle_args *, struct of_dma *);\n\tvoid * (*of_dma_route_allocate)(struct of_phandle_args *, struct of_dma *);\n\tstruct dma_router *dma_router;\n\tvoid *of_dma_data;\n};\n\nstruct of_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct of_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct device_node *local_node;\n};\n\nstruct of_genpd_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n\tgenpd_xlate_t xlate;\n\tvoid *data;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct of_imap_item {\n\tstruct of_phandle_args parent_args;\n\tu32 child_imap_count;\n\tu32 child_imap[16];\n};\n\nstruct of_imap_parser {\n\tstruct device_node *node;\n\tconst __be32 *imap;\n\tconst __be32 *imap_end;\n\tu32 parent_offset;\n};\n\ntypedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *);\n\nstruct of_intc_desc {\n\tstruct list_head list;\n\tof_irq_init_cb_t irq_init_cb;\n\tstruct device_node *dev;\n\tstruct device_node *interrupt_parent;\n};\n\nstruct of_mmc_spi {\n\tstruct mmc_spi_platform_data pdata;\n\tint detect_irq;\n};\n\nstruct of_pci_iommu_alias_info {\n\tstruct device *dev;\n\tstruct device_node *np;\n};\n\nstruct of_pci_range {\n\tunion {\n\t\tu64 pci_addr;\n\t\tu64 bus_addr;\n\t};\n\tu64 cpu_addr;\n\tu64 parent_bus_addr;\n\tu64 size;\n\tu32 flags;\n};\n\nstruct of_pci_range_parser {\n\tstruct device_node *node;\n\tconst struct of_bus___2 *bus;\n\tconst __be32 *range;\n\tconst __be32 *end;\n\tint na;\n\tint ns;\n\tint pna;\n\tbool dma;\n};\n\nstruct of_phandle_iterator {\n\tconst char *cells_name;\n\tint cell_count;\n\tconst struct device_node *parent;\n\tconst __be32 *list_end;\n\tconst __be32 *phandle_end;\n\tconst __be32 *cur;\n\tuint32_t cur_count;\n\tphandle phandle;\n\tstruct device_node *node;\n};\n\nstruct of_pmem_private {\n\tstruct nvdimm_bus_descriptor bus_desc;\n\tstruct nvdimm_bus *bus;\n};\n\nstruct of_regulator_match {\n\tconst char *name;\n\tvoid *driver_data;\n\tstruct regulator_init_data *init_data;\n\tstruct device_node *of_node;\n\tconst struct regulator_desc *desc;\n};\n\nstruct of_rename_gpio {\n\tconst char *con_id;\n\tconst char *legacy_id;\n\tconst char *compatible;\n};\n\nstruct of_serial_info {\n\tstruct clk *clk;\n\tstruct clk *bus_clk;\n\tstruct reset_control *rst;\n\tint type;\n\tint line;\n\tstruct notifier_block clk_notifier;\n};\n\nstruct of_timer_base {\n\tvoid *base;\n\tconst char *name;\n\tint index;\n};\n\nstruct of_timer_clk {\n\tstruct clk *clk;\n\tconst char *name;\n\tint index;\n\tlong unsigned int rate;\n\tlong unsigned int period;\n};\n\nstruct of_timer_irq {\n\tint irq;\n\tint index;\n\tconst char *name;\n\tlong unsigned int flags;\n\tirq_handler_t handler;\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nstruct ohci_driver_overrides {\n\tconst char *product_desc;\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n};\n\nstruct ohci_hcca {\n\t__hc32 int_table[32];\n\t__hc32 frame_no;\n\t__hc32 done_head;\n\tu8 reserved_for_hc[116];\n\tu8 what[4];\n};\n\nstruct ohci_regs;\n\nstruct ohci_hcd {\n\tspinlock_t lock;\n\tstruct ohci_regs *regs;\n\tstruct ohci_hcca *hcca;\n\tdma_addr_t hcca_dma;\n\tstruct ed *ed_rm_list;\n\tstruct ed *ed_bulktail;\n\tstruct ed *ed_controltail;\n\tstruct ed *periodic[32];\n\tvoid (*start_hnp)(struct ohci_hcd *);\n\tstruct dma_pool *td_cache;\n\tstruct dma_pool *ed_cache;\n\tstruct td *td_hash[64];\n\tstruct td *dl_start;\n\tstruct td *dl_end;\n\tstruct list_head pending;\n\tstruct list_head eds_in_use;\n\tenum ohci_rh_state rh_state;\n\tint num_ports;\n\tint load[32];\n\tu32 hc_control;\n\tlong unsigned int next_statechange;\n\tu32 fminterval;\n\tunsigned int autostop: 1;\n\tunsigned int working: 1;\n\tunsigned int restart_work: 1;\n\tlong unsigned int flags;\n\tunsigned int prev_frame_no;\n\tunsigned int wdh_cnt;\n\tunsigned int prev_wdh_cnt;\n\tu32 prev_donehead;\n\tstruct timer_list io_watchdog;\n\tstruct work_struct nec_work;\n\tstruct dentry *debug_dir;\n\tlong unsigned int priv[0];\n};\n\nstruct ohci_platform_priv {\n\tstruct clk *clks[4];\n\tstruct reset_control *resets;\n};\n\nstruct ohci_roothub_regs {\n\t__hc32 a;\n\t__hc32 b;\n\t__hc32 status;\n\t__hc32 portstatus[15];\n};\n\nstruct ohci_regs {\n\t__hc32 revision;\n\t__hc32 control;\n\t__hc32 cmdstatus;\n\t__hc32 intrstatus;\n\t__hc32 intrenable;\n\t__hc32 intrdisable;\n\t__hc32 hcca;\n\t__hc32 ed_periodcurrent;\n\t__hc32 ed_controlhead;\n\t__hc32 ed_controlcurrent;\n\t__hc32 ed_bulkhead;\n\t__hc32 ed_bulkcurrent;\n\t__hc32 donehead;\n\t__hc32 fminterval;\n\t__hc32 fmremaining;\n\t__hc32 fmnumber;\n\t__hc32 periodicstart;\n\t__hc32 lsthresh;\n\tstruct ohci_roothub_regs roothub;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_itimerval32 {\n\tstruct old_timeval32 it_interval;\n\tstruct old_timeval32 it_value;\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n};\n\nstruct old_timex32 {\n\tu32 modes;\n\ts32 offset;\n\ts32 freq;\n\ts32 maxerror;\n\ts32 esterror;\n\ts32 status;\n\ts32 constant;\n\ts32 precision;\n\ts32 tolerance;\n\tstruct old_timeval32 time;\n\ts32 tick;\n\ts32 ppsfreq;\n\ts32 jitter;\n\ts32 shift;\n\ts32 stabil;\n\ts32 jitcnt;\n\ts32 calcnt;\n\ts32 errcnt;\n\ts32 stbcnt;\n\ts32 tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct static_key_true;\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct opp_config_data {\n\tstruct opp_table *opp_table;\n\tunsigned int flags;\n\tunsigned int required_dev_index;\n};\n\nstruct opp_device {\n\tstruct list_head node;\n\tconst struct device *dev;\n\tstruct dentry *dentry;\n};\n\nstruct icc_path;\n\nstruct opp_table {\n\tstruct list_head node;\n\tstruct list_head lazy;\n\tstruct blocking_notifier_head head;\n\tstruct list_head dev_list;\n\tstruct list_head opp_list;\n\tstruct kref kref;\n\tstruct mutex lock;\n\tstruct device_node *np;\n\tlong unsigned int clock_latency_ns_max;\n\tunsigned int voltage_tolerance_v1;\n\tunsigned int parsed_static_opps;\n\tenum opp_table_access shared_opp;\n\tlong unsigned int current_rate_single_clk;\n\tstruct dev_pm_opp *current_opp;\n\tstruct dev_pm_opp *suspend_opp;\n\tstruct opp_table **required_opp_tables;\n\tstruct device **required_devs;\n\tunsigned int required_opp_count;\n\tunsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char *prop_name;\n\tconfig_clks_t config_clks;\n\tstruct clk **clks;\n\tstruct clk *clk;\n\tint clk_count;\n\tconfig_regulators_t config_regulators;\n\tstruct regulator **regulators;\n\tint regulator_count;\n\tstruct icc_path **paths;\n\tunsigned int path_count;\n\tbool enabled;\n\tbool is_genpd;\n\tstruct dentry *dentry;\n\tchar dentry_name[255];\n};\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\nstruct osnoise_entry {\n\tstruct trace_entry ent;\n\tu64 noise;\n\tu64 runtime;\n\tu64 max_sample;\n\tunsigned int hw_count;\n\tunsigned int nmi_count;\n\tunsigned int irq_count;\n\tunsigned int softirq_count;\n\tunsigned int thread_count;\n};\n\nstruct otp_info {\n\t__u32 start;\n\t__u32 length;\n\t__u32 locked;\n};\n\nstruct p1_rtc {\n\tstruct regmap *regmap;\n\tstruct rtc_device *rtc;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tu64 bus_offset;\n};\n\nstruct p9_trans_module;\n\nstruct p9_client {\n\tspinlock_t lock;\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n\tenum p9_trans_status status;\n\tvoid *trans;\n\tstruct kmem_cache *fcall_cache;\n\tunion {\n\t\tstruct {\n\t\t\tint rfd;\n\t\t\tint wfd;\n\t\t} fd;\n\t\tstruct {\n\t\t\tu16 port;\n\t\t\tbool privport;\n\t\t} tcp;\n\t} trans_opts;\n\tstruct idr fids;\n\tstruct idr reqs;\n\tchar name[65];\n};\n\nstruct p9_client_opts {\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n};\n\nstruct p9_fcall {\n\tu32 size;\n\tu8 id;\n\tu16 tag;\n\tsize_t offset;\n\tsize_t capacity;\n\tstruct kmem_cache *cache;\n\tu8 *sdata;\n\tbool zc;\n};\n\nstruct p9_conn;\n\nstruct p9_poll_wait {\n\tstruct p9_conn *conn;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_addr;\n};\n\nstruct p9_req_t;\n\nstruct p9_conn {\n\tstruct list_head mux_list;\n\tstruct p9_client *client;\n\tint err;\n\tspinlock_t req_lock;\n\tstruct list_head req_list;\n\tstruct list_head unsent_req_list;\n\tstruct p9_req_t *rreq;\n\tstruct p9_req_t *wreq;\n\tchar tmp_buf[7];\n\tstruct p9_fcall rc;\n\tint wpos;\n\tint wsize;\n\tchar *wbuf;\n\tstruct list_head poll_pending_link;\n\tstruct p9_poll_wait poll_wait[2];\n\tpoll_table pt;\n\tstruct work_struct rq;\n\tstruct work_struct wq;\n\tlong unsigned int wsched;\n};\n\nstruct p9_qid {\n\tu8 type;\n\tu32 version;\n\tu64 path;\n};\n\nstruct p9_dirent {\n\tstruct p9_qid qid;\n\tu64 d_off;\n\tunsigned char d_type;\n\tchar d_name[256];\n};\n\nstruct p9_fd_opts {\n\tint rfd;\n\tint wfd;\n\tu16 port;\n\tbool privport;\n};\n\nstruct p9_fid {\n\tstruct p9_client *clnt;\n\tu32 fid;\n\trefcount_t count;\n\tint mode;\n\tstruct p9_qid qid;\n\tu32 iounit;\n\tkuid_t uid;\n\tvoid *rdir;\n\tstruct hlist_node dlist;\n\tstruct hlist_node ilist;\n};\n\nstruct p9_flock {\n\tu8 type;\n\tu32 flags;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_getlock {\n\tu8 type;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_iattr_dotl {\n\tu32 valid;\n\tu32 mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tu64 size;\n\tu64 atime_sec;\n\tu64 atime_nsec;\n\tu64 mtime_sec;\n\tu64 mtime_nsec;\n};\n\nstruct p9_rdir {\n\tint head;\n\tint tail;\n\tuint8_t buf[0];\n};\n\nstruct p9_rdma_opts {\n\tshort int port;\n\tbool privport;\n\tint sq_depth;\n\tint rq_depth;\n\tlong int timeout;\n};\n\nstruct p9_req_t {\n\tint status;\n\tint t_err;\n\trefcount_t refcount;\n\twait_queue_head_t wq;\n\tstruct p9_fcall tc;\n\tstruct p9_fcall rc;\n\tstruct list_head req_list;\n};\n\nstruct p9_rstatfs {\n\tu32 type;\n\tu32 bsize;\n\tu64 blocks;\n\tu64 bfree;\n\tu64 bavail;\n\tu64 files;\n\tu64 ffree;\n\tu64 fsid;\n\tu32 namelen;\n};\n\nstruct p9_session_opts {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tlong int session_lock_timeout;\n};\n\nstruct p9_stat_dotl {\n\tu64 st_result_mask;\n\tstruct p9_qid qid;\n\tu32 st_mode;\n\tkuid_t st_uid;\n\tkgid_t st_gid;\n\tu64 st_nlink;\n\tu64 st_rdev;\n\tu64 st_size;\n\tu64 st_blksize;\n\tu64 st_blocks;\n\tu64 st_atime_sec;\n\tu64 st_atime_nsec;\n\tu64 st_mtime_sec;\n\tu64 st_mtime_nsec;\n\tu64 st_ctime_sec;\n\tu64 st_ctime_nsec;\n\tu64 st_btime_sec;\n\tu64 st_btime_nsec;\n\tu64 st_gen;\n\tu64 st_data_version;\n};\n\nstruct p9_trans_fd {\n\tstruct file *rd;\n\tstruct file *wr;\n\tstruct p9_conn conn;\n};\n\nstruct p9_trans_module {\n\tstruct list_head list;\n\tchar *name;\n\tint maxsize;\n\tbool pooled_rbuffers;\n\tbool def;\n\tbool supports_vmalloc;\n\tstruct module *owner;\n\tint (*create)(struct p9_client *, struct fs_context *);\n\tvoid (*close)(struct p9_client *);\n\tint (*request)(struct p9_client *, struct p9_req_t *);\n\tint (*cancel)(struct p9_client *, struct p9_req_t *);\n\tint (*cancelled)(struct p9_client *, struct p9_req_t *);\n\tint (*zc_request)(struct p9_client *, struct p9_req_t *, struct iov_iter *, struct iov_iter *, int, int, int);\n\tint (*show_options)(struct seq_file *, struct p9_client *);\n};\n\nstruct p9_wstat {\n\tu16 size;\n\tu16 type;\n\tu32 dev;\n\tstruct p9_qid qid;\n\tu32 mode;\n\tu32 atime;\n\tu32 mtime;\n\tu64 length;\n\tconst char *name;\n\tconst char *uid;\n\tconst char *gid;\n\tconst char *muid;\n\tchar *extension;\n\tkuid_t n_uid;\n\tkgid_t n_gid;\n\tkuid_t n_muid;\n};\n\nstruct scsi_sense_hdr;\n\nstruct packet_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct scsi_sense_hdr *sshdr;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 history[16];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t tp_drops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct padata_cpumask {\n\tcpumask_var_t pcpu;\n\tcpumask_var_t cbcpu;\n};\n\nstruct padata_instance {\n\tstruct hlist_node cpu_online_node;\n\tstruct hlist_node cpu_dead_node;\n\tstruct workqueue_struct *parallel_wq;\n\tstruct workqueue_struct *serial_wq;\n\tstruct list_head pslist;\n\tstruct padata_cpumask cpumask;\n\tstruct kobject kobj;\n\tstruct mutex lock;\n\tu8 flags;\n};\n\nstruct padata_list {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct padata_mt_job {\n\tvoid (*thread_fn)(long unsigned int, long unsigned int, void *);\n\tvoid *fn_arg;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int min_chunk;\n\tint max_threads;\n\tbool numa_aware;\n};\n\nstruct padata_mt_job_state {\n\tspinlock_t lock;\n\tstruct completion completion;\n\tstruct padata_mt_job *job;\n\tint nworks;\n\tint nworks_fini;\n\tlong unsigned int chunk_size;\n};\n\nstruct parallel_data;\n\nstruct padata_priv {\n\tstruct list_head list;\n\tstruct parallel_data *pd;\n\tint cb_cpu;\n\tunsigned int seq_nr;\n\tint info;\n\tvoid (*parallel)(struct padata_priv *);\n\tvoid (*serial)(struct padata_priv *);\n};\n\nstruct padata_serial_queue {\n\tstruct padata_list serial;\n\tstruct work_struct work;\n\tstruct parallel_data *pd;\n};\n\nstruct padata_shell {\n\tstruct padata_instance *pinst;\n\tstruct parallel_data *pd;\n\tstruct parallel_data *opd;\n\tstruct list_head list;\n};\n\nstruct padata_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct padata_instance *, const struct attribute *, char *);\n\tssize_t (*store)(struct padata_instance *, const struct attribute *, const char *, size_t);\n};\n\nstruct padata_work {\n\tstruct work_struct pw_work;\n\tstruct list_head pw_list;\n\tvoid *pw_data;\n};\n\ntypedef struct page *pgtable_t;\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tlong: 0;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\tlong: 0;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tu32 xdp_mem_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pp_alloc_cache alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t} user;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_reporting_dev_info {\n\tint (*report)(struct page_reporting_dev_info *, struct scatterlist *, unsigned int);\n\tstruct delayed_work work;\n\tatomic_t state;\n\tunsigned int order;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n\tlong: 64;\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pageattr_masks {\n\tpgprot_t set_mask;\n\tpgprot_t clear_mask;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct parallel_data {\n\tstruct padata_shell *ps;\n\tstruct padata_list *reorder_list;\n\tstruct padata_serial_queue *squeue;\n\trefcount_t refcnt;\n\tunsigned int seq_nr;\n\tunsigned int processed;\n\tint cpu;\n\tstruct padata_cpumask cpumask;\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct patch_insn {\n\tvoid *addr;\n\tu32 *insns;\n\tsize_t len;\n\tatomic_t cpu_count;\n};\n\nstruct path_cond {\n\tkuid_t uid;\n\tumode_t mode;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct pcc_mbox_chan {\n\tstruct mbox_chan *mchan;\n\tu64 shmem_base_addr;\n\tvoid *shmem;\n\tu64 shmem_size;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n};\n\nstruct pcc_chan_reg {\n\tvoid *vaddr;\n\tstruct acpi_generic_address *gas;\n\tu64 preserve_mask;\n\tu64 set_mask;\n\tu64 status_mask;\n};\n\nstruct pcc_chan_info {\n\tstruct pcc_mbox_chan chan;\n\tstruct pcc_chan_reg db;\n\tstruct pcc_chan_reg plat_irq_ack;\n\tstruct pcc_chan_reg cmd_complete;\n\tstruct pcc_chan_reg cmd_update;\n\tstruct pcc_chan_reg error;\n\tint plat_irq;\n\tu8 type;\n\tunsigned int plat_irq_flags;\n\tbool chan_in_use;\n};\n\nstruct pcc_data {\n\tstruct pcc_mbox_chan *pcc_chan;\n\tstruct completion done;\n\tstruct mbox_client cl;\n\tstruct acpi_pcc_info ctx;\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tint domain_nr;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_config_window {\n\tstruct resource res;\n\tstruct resource busr;\n\tunsigned int bus_shift;\n\tvoid *priv;\n\tconst struct pci_ecam_ops *ops;\n\tunion {\n\t\tvoid *win;\n\t\tvoid **winp;\n\t};\n\tstruct device *parent;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct rcec_ea;\n\nstruct pcie_link_state;\n\nstruct pcie_bwctrl_data;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tstruct rcec_ea *rcec_ea;\n\tstruct pci_dev *rcec;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tstruct pcie_link_state *link_state;\n\tunsigned int aspm_l0s_support: 1;\n\tunsigned int aspm_l1_support: 1;\n\tunsigned int ltr_path: 1;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[11];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[11];\n\tstruct bin_attribute *res_attr_wc[11];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_ecam_ops {\n\tunsigned int bus_shift;\n\tstruct pci_ops pci_ops;\n\tint (*init)(struct pci_config_window *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n};\n\nstruct pci_epc_ops;\n\nstruct pci_epc_mem;\n\nstruct pci_epc {\n\tstruct device dev;\n\tstruct list_head pci_epf;\n\tstruct mutex list_lock;\n\tconst struct pci_epc_ops *ops;\n\tstruct pci_epc_mem **windows;\n\tstruct pci_epc_mem *mem;\n\tunsigned int num_windows;\n\tu8 max_functions;\n\tu8 *max_vfs;\n\tstruct config_group *group;\n\tstruct mutex lock;\n\tlong unsigned int function_num_map;\n\tint domain_nr;\n\tbool init_complete;\n};\n\nstruct pci_epc_bar_desc {\n\tenum pci_epc_bar_type type;\n\tu64 fixed_size;\n\tbool only_64bit;\n};\n\nstruct pci_epc_features {\n\tunsigned int linkup_notifier: 1;\n\tunsigned int dynamic_inbound_mapping: 1;\n\tunsigned int subrange_mapping: 1;\n\tunsigned int msi_capable: 1;\n\tunsigned int msix_capable: 1;\n\tunsigned int intx_capable: 1;\n\tstruct pci_epc_bar_desc bar[6];\n\tsize_t align;\n};\n\nstruct pci_epc_mem_window {\n\tphys_addr_t phys_base;\n\tsize_t size;\n\tsize_t page_size;\n};\n\nstruct pci_epc_mem {\n\tstruct pci_epc_mem_window window;\n\tlong unsigned int *bitmap;\n\tint pages;\n\tstruct mutex lock;\n};\n\nstruct pci_epf_header;\n\nstruct pci_epf_bar;\n\nstruct pci_epc_ops {\n\tint (*write_header)(struct pci_epc *, u8, u8, struct pci_epf_header *);\n\tint (*set_bar)(struct pci_epc *, u8, u8, struct pci_epf_bar *);\n\tvoid (*clear_bar)(struct pci_epc *, u8, u8, struct pci_epf_bar *);\n\tu64 (*align_addr)(struct pci_epc *, u64, size_t *, size_t *);\n\tint (*map_addr)(struct pci_epc *, u8, u8, phys_addr_t, u64, size_t);\n\tvoid (*unmap_addr)(struct pci_epc *, u8, u8, phys_addr_t);\n\tint (*set_msi)(struct pci_epc *, u8, u8, u8);\n\tint (*get_msi)(struct pci_epc *, u8, u8);\n\tint (*set_msix)(struct pci_epc *, u8, u8, u16, enum pci_barno, u32);\n\tint (*get_msix)(struct pci_epc *, u8, u8);\n\tint (*raise_irq)(struct pci_epc *, u8, u8, unsigned int, u16);\n\tint (*map_msi_irq)(struct pci_epc *, u8, u8, phys_addr_t, u8, u32, u32 *, u32 *);\n\tint (*start)(struct pci_epc *);\n\tvoid (*stop)(struct pci_epc *);\n\tconst struct pci_epc_features * (*get_features)(struct pci_epc *, u8, u8);\n\tstruct module *owner;\n};\n\nstruct pci_epf_bar_submap;\n\nstruct pci_epf_bar {\n\tdma_addr_t phys_addr;\n\tvoid *addr;\n\tsize_t size;\n\tsize_t mem_size;\n\tenum pci_barno barno;\n\tint flags;\n\tunsigned int num_submap;\n\tstruct pci_epf_bar_submap *submap;\n};\n\nstruct pci_epf_bar_submap {\n\tdma_addr_t phys_addr;\n\tsize_t size;\n};\n\nstruct pci_epf_header {\n\tu16 vendorid;\n\tu16 deviceid;\n\tu8 revid;\n\tu8 progif_code;\n\tu8 subclass_code;\n\tu8 baseclass_code;\n\tu8 cache_line_size;\n\tu16 subsys_vendor_id;\n\tu16 subsys_id;\n\tenum pci_interrupt_pin interrupt_pin;\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tvoid (*hook)(struct pci_dev *);\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct pci_osc_bit_struct {\n\tu32 bit;\n\tchar *desc;\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pcie_ptm_ops;\n\nstruct pci_ptm_debugfs {\n\tstruct dentry *debugfs;\n\tconst struct pcie_ptm_ops *ops;\n\tstruct mutex lock;\n\tvoid *pdata;\n};\n\nstruct pci_pwrctrl {\n\tstruct device *dev;\n\tint (*power_on)(struct pci_pwrctrl *);\n\tint (*power_off)(struct pci_pwrctrl *);\n\tstruct notifier_block nb;\n\tstruct device_link *link;\n\tstruct work_struct work;\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct serial_private;\n\nstruct pciserial_board;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pcie_bwctrl_data {\n\tstruct mutex set_speed_mutex;\n\tstruct thermal_cooling_device *cdev;\n};\n\nstruct pcie_device {\n\tint irq;\n\tstruct pci_dev *port;\n\tu32 service;\n\tvoid *priv_data;\n\tstruct device device;\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tint: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n};\n\nstruct pcie_pme_service_data {\n\tspinlock_t lock;\n\tstruct pcie_device *srv;\n\tstruct work_struct work;\n\tbool noirq;\n};\n\nstruct pcie_port_service_driver {\n\tconst char *name;\n\tint (*probe)(struct pcie_device *);\n\tvoid (*remove)(struct pcie_device *);\n\tint (*suspend)(struct pcie_device *);\n\tint (*resume_noirq)(struct pcie_device *);\n\tint (*resume)(struct pcie_device *);\n\tint (*runtime_suspend)(struct pcie_device *);\n\tint (*runtime_resume)(struct pcie_device *);\n\tint (*slot_reset)(struct pcie_device *);\n\tint port_type;\n\tu32 service;\n\tstruct device_driver driver;\n};\n\nstruct pcie_ptm_ops {\n\tint (*check_capability)(void *);\n\tint (*context_update_write)(void *, u8);\n\tint (*context_update_read)(void *, u8 *);\n\tint (*context_valid_write)(void *, bool);\n\tint (*context_valid_read)(void *, bool *);\n\tint (*local_clock_read)(void *, u64 *);\n\tint (*master_clock_read)(void *, u64 *);\n\tint (*t1_read)(void *, u64 *);\n\tint (*t2_read)(void *, u64 *);\n\tint (*t3_read)(void *, u64 *);\n\tint (*t4_read)(void *, u64 *);\n\tbool (*context_update_visible)(void *);\n\tbool (*context_valid_visible)(void *);\n\tbool (*local_clock_visible)(void *);\n\tbool (*master_clock_visible)(void *);\n\tbool (*t1_visible)(void *);\n\tbool (*t2_visible)(void *);\n\tbool (*t3_visible)(void *);\n\tbool (*t4_visible)(void *);\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[11];\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct pcm_format_data {\n\tunsigned char width;\n\tunsigned char phys;\n\tsigned char le;\n\tsigned char signd;\n\tunsigned char silence[8];\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpuobj_ext;\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tstruct pcpuobj_ext *obj_exts;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpuobj_ext {\n\tstruct obj_cgroup *cgroup;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[51];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tu8 expire;\n\tshort int free_count;\n\tstruct list_head lists[12];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[10];\n\ts8 stat_threshold;\n\tlong unsigned int vm_numa_event[6];\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\nstruct percpu_free_defer {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\ntypedef struct percpu_rw_semaphore *class_percpu_read_t;\n\ntypedef struct percpu_rw_semaphore *class_percpu_write_t;\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[1];\n\tlong unsigned int offset[1];\n\tlocal_lock_t lock;\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu64 hw_id;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___3 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 spec: 2;\n\t__u64 new_type: 4;\n\t__u64 priv: 3;\n\t__u64 reserved: 31;\n};\n\nstruct perf_branch_stack {\n\tu64 nr;\n\tu64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct perf_event_mmap_page;\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\trefcount_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tstruct mutex aux_mutex;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\trefcount_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tint aux_in_pause_resume;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct unwind_stacktrace;\n\nstruct perf_callchain_deferred_event {\n\tstruct unwind_stacktrace *trace;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 cookie;\n\t\tu64 nr;\n\t\tu64 ips[0];\n\t} event;\n};\n\nstruct perf_callchain_entry {\n\tu64 nr;\n\tu64 ip[0];\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nstruct perf_cgroup_info;\n\nstruct perf_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct perf_cgroup_info *info;\n};\n\nstruct perf_cgroup_event {\n\tchar *path;\n\tint path_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 id;\n\t\tchar path[0];\n\t} event_id;\n};\n\nstruct perf_time_ctx {\n\tu64 time;\n\tu64 stamp;\n\tu64 offset;\n};\n\nstruct perf_cgroup_info {\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tint active;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tu64 index;\n};\n\nstruct perf_event_context {\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head pmu_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tint nr_events;\n\tint nr_user;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tstruct perf_event_context *parent_ctx;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tint nr_cgroups;\n\tstruct callback_head callback_head;\n\tlocal_t nr_no_switch_fast;\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint online;\n\tstruct perf_cgroup *cgrp;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_event_pmu_context {\n\tstruct pmu *pmu;\n\tstruct perf_event_context *ctx;\n\tstruct list_head pmu_ctx_entry;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tunsigned int embedded: 1;\n\tunsigned int nr_events;\n\tunsigned int nr_cgroups;\n\tunsigned int nr_freq;\n\tatomic_t refcount;\n\tstruct callback_head callback_head;\n\tint rotate_necessary;\n};\n\nstruct perf_cpu_pmu_context {\n\tstruct perf_event_pmu_context epc;\n\tstruct perf_event_pmu_context *task_epc;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint active_oncpu;\n\tint exclusive;\n\tint pmu_disable_count;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n};\n\nstruct perf_ctx_data {\n\tstruct callback_head callback_head;\n\trefcount_t refcount;\n\tint global;\n\tstruct kmem_cache *ctx_cache;\n\tvoid *data;\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 text_poke: 1;\n\t__u64 build_id: 1;\n\t__u64 inherit_thread: 1;\n\t__u64 remove_on_exec: 1;\n\t__u64 sigtrap: 1;\n\t__u64 defer_callchain: 1;\n\t__u64 defer_output: 1;\n\t__u64 __reserved_1: 24;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\tunion {\n\t\t__u32 aux_action;\n\t\tstruct {\n\t\t\t__u32 aux_start_paused: 1;\n\t\t\t__u32 aux_pause: 1;\n\t\t\t__u32 aux_resume: 1;\n\t\t\t__u32 __reserved_3: 29;\n\t\t};\n\t};\n\t__u64 sig_data;\n\t__u64 config3;\n\t__u64 config4;\n};\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tunsigned int group_generation;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tstruct perf_event_pmu_context *pmu_ctx;\n\tatomic_long_t refcount;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\trefcount_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tunsigned int pending_wakeup;\n\tunsigned int pending_kill;\n\tunsigned int pending_disable;\n\tlong unsigned int pending_addr;\n\tstruct irq_work pending_irq;\n\tstruct irq_work pending_disable_irq;\n\tstruct callback_head pending_task;\n\tunsigned int pending_work;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tu64 id;\n\tatomic64_t lost_samples;\n\tu64 (*clock)(void);\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tstruct bpf_prog *prog;\n\tu64 bpf_cookie;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tstruct perf_cgroup *cgrp;\n\tvoid *security;\n\tstruct list_head sb_list;\n\tstruct list_head pmu_list;\n\tu32 orig_type;\n};\n\nstruct perf_event_min_heap {\n\tsize_t nr;\n\tsize_t size;\n\tstruct perf_event **data;\n\tstruct perf_event *preallocated[0];\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_user_time_short: 1;\n\t\t\t__u64 cap_____res: 58;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u32 __reserved_1;\n\t__u64 time_cycles;\n\t__u64 time_mask;\n\t__u8 __reserved[928];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct perf_event_security_struct {\n\tu32 sid;\n};\n\nstruct perf_guest_info_callbacks {\n\tunsigned int (*state)(void);\n\tlong unsigned int (*get_ip)(void);\n\tunsigned int (*handle_intel_pt_intr)(void);\n\tvoid (*handle_mediated_pmi)(void);\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tu8 build_id[20];\n\tu32 build_id_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tunion {\n\t\tu64 flags;\n\t\tu64 aux_flags;\n\t\tstruct {\n\t\t\tu64 skip_read: 1;\n\t\t};\n\t};\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n} __attribute__((packed));\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_text_poke_event {\n\tconst void *old_bytes;\n\tconst void *new_bytes;\n\tsize_t pad;\n\tu16 old_len;\n\tu16 new_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t} event_id;\n};\n\nstruct pericom8250 {\n\tvoid *virt;\n\tunsigned int nr;\n\tint line[0];\n};\n\nstruct perm_datum {\n\tu32 value;\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct pf_desc {\n\tu32 pseudoflavor;\n\tu32 qop;\n\tu32 service;\n\tchar *name;\n\tchar *auth_domain_name;\n\tstruct auth_domain *domain;\n\tbool datatouch;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[3];\n\tint node;\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tconst char *name;\n\tint initialized;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[11];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 0;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[10];\n\tatomic_long_t vm_numa_event[6];\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[13];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[3];\n\tstruct zonelist node_zonelists[2];\n\tint nr_zones;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tlong unsigned int min_unmapped_pages;\n\tlong unsigned int min_slab_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tunsigned int nbp_rl_start;\n\tlong unsigned int nbp_rl_nr_cand;\n\tunsigned int nbp_threshold;\n\tunsigned int nbp_th_start;\n\tlong unsigned int nbp_th_nr_cand;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[51];\n\tstruct memory_tier *memtier;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tu32 max_link_rate;\n\tenum phy_mode mode;\n};\n\nstruct phy_ops;\n\nstruct phy {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tstruct lock_class_key lockdep_key;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n\tstruct dentry *debugfs;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_lvds {\n\tunsigned int bits_per_lane_and_dclk_cycle;\n\tlong unsigned int differential_clk_rate;\n\tunsigned int lanes;\n\tbool is_slave;\n};\n\nstruct phy_configure_opts_hdmi {\n\tunsigned int bpc;\n\tunion {\n\t\tlong long unsigned int tmds_char_rate;\n\t\tstruct {\n\t\t\tu8 rate_per_lane;\n\t\t\tu8 lanes;\n\t\t} frl;\n\t};\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n\tstruct phy_configure_opts_lvds lvds;\n\tstruct phy_configure_opts_hdmi hdmi;\n};\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[1];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tlong unsigned int adv_old[2];\n\tlong unsigned int supported_eee[2];\n\tlong unsigned int advertising_eee[2];\n\tlong unsigned int eee_disabled_modes[2];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[1];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct phy_package_shared *shared;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct usb_phy;\n\nstruct phy_devm {\n\tstruct usb_phy *phy;\n\tstruct notifier_block *nb;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nstruct phy_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct phy *phy;\n};\n\nunion phy_notify {\n\tenum phy_ufs_state ufs_state;\n};\n\nstruct phy_ops {\n\tint (*init)(struct phy *);\n\tint (*exit)(struct phy *);\n\tint (*power_on)(struct phy *);\n\tint (*power_off)(struct phy *);\n\tint (*set_mode)(struct phy *, enum phy_mode, int);\n\tint (*set_media)(struct phy *, enum phy_media);\n\tint (*set_speed)(struct phy *, int);\n\tint (*configure)(struct phy *, union phy_configure_opts *);\n\tint (*validate)(struct phy *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy *);\n\tint (*calibrate)(struct phy *);\n\tint (*connect)(struct phy *, int);\n\tint (*disconnect)(struct phy *, int);\n\tint (*notify_phystate)(struct phy *, union phy_notify);\n\tvoid (*release)(struct phy *);\n\tstruct module *owner;\n};\n\nstruct phy_package_shared {\n\tu8 base_addr;\n\tstruct device_node *np;\n\trefcount_t refcnt;\n\tlong unsigned int flags;\n\tsize_t priv_size;\n\tvoid *priv;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_port_ops;\n\nstruct phy_port {\n\tstruct list_head head;\n\tenum phy_port_parent parent_type;\n\tunion {\n\t\tstruct phy_device *phy;\n\t};\n\tconst struct phy_port_ops *ops;\n\tint pairs;\n\tlong unsigned int mediums;\n\tlong unsigned int supported[2];\n\tlong unsigned int interfaces[1];\n\tunsigned int not_described: 1;\n\tunsigned int active: 1;\n\tunsigned int is_mii: 1;\n\tunsigned int is_sfp: 1;\n};\n\nstruct phy_port_ops {\n\tvoid (*link_up)(struct phy_port *);\n\tvoid (*link_down)(struct phy_port *);\n\tint (*configure_mii)(struct phy_port *, bool, phy_interface_t);\n};\n\nstruct phy_provider {\n\tstruct device *dev;\n\tstruct device_node *children;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct phy * (*of_xlate)(struct device *, const struct of_phandle_args *);\n};\n\nstruct phy_reg {\n\tu16 reg;\n\tu16 val;\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phylib_stubs {\n\tint (*hwtstamp_get)(struct phy_device *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct phy_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_ext_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n};\n\nstruct phylink_link_state {\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tphy_interface_t interface;\n\tint speed;\n\tint duplex;\n\tint pause;\n\tint rate_matching;\n\tunsigned int link: 1;\n\tunsigned int an_complete: 1;\n};\n\nstruct phylink_mac_ops;\n\nstruct phylink {\n\tstruct net_device *netdev;\n\tconst struct phylink_mac_ops *mac_ops;\n\tstruct phylink_config *config;\n\tstruct phylink_pcs *pcs;\n\tstruct device *dev;\n\tunsigned int old_link_state: 1;\n\tlong unsigned int phylink_disable_state;\n\tstruct phy_device *phydev;\n\tphy_interface_t link_interface;\n\tu8 cfg_link_an_mode;\n\tu8 req_link_an_mode;\n\tu8 act_link_an_mode;\n\tu8 link_port;\n\tlong unsigned int supported[2];\n\tlong unsigned int supported_lpi[2];\n\tstruct phylink_link_state link_config;\n\tphy_interface_t cur_interface;\n\tstruct gpio_desc *link_gpio;\n\tunsigned int link_irq;\n\tstruct timer_list link_poll;\n\tstruct mutex state_mutex;\n\tstruct mutex phydev_mutex;\n\tstruct phylink_link_state phy_state;\n\tunsigned int phy_ib_mode;\n\tstruct work_struct resolve;\n\tunsigned int pcs_neg_mode;\n\tunsigned int pcs_state;\n\tbool link_failed;\n\tbool suspend_link_up;\n\tbool force_major_config;\n\tbool major_config_failed;\n\tbool mac_supports_eee_ops;\n\tbool mac_supports_eee;\n\tbool phy_enable_tx_lpi;\n\tbool mac_enable_tx_lpi;\n\tbool mac_tx_clk_stop;\n\tu32 mac_tx_lpi_timer;\n\tu8 mac_rx_clk_stop_blocked;\n\tstruct sfp_bus *sfp_bus;\n\tbool sfp_may_have_phy;\n\tlong unsigned int sfp_interfaces[1];\n\tlong unsigned int sfp_support[2];\n\tu8 sfp_port;\n\tstruct eee_config eee_cfg;\n\tu32 wolopts_mac;\n\tu8 wol_sopass[6];\n};\n\nstruct phylink_mac_ops {\n\tlong unsigned int (*mac_get_caps)(struct phylink_config *, phy_interface_t);\n\tstruct phylink_pcs * (*mac_select_pcs)(struct phylink_config *, phy_interface_t);\n\tint (*mac_prepare)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_config)(struct phylink_config *, unsigned int, const struct phylink_link_state *);\n\tint (*mac_finish)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_down)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_up)(struct phylink_config *, struct phy_device *, unsigned int, phy_interface_t, int, int, bool, bool);\n\tvoid (*mac_disable_tx_lpi)(struct phylink_config *);\n\tint (*mac_enable_tx_lpi)(struct phylink_config *, u32, bool);\n\tint (*mac_wol_set)(struct phylink_config *, u32, const u8 *);\n};\n\nstruct phylink_pcs_ops {\n\tint (*pcs_validate)(struct phylink_pcs *, long unsigned int *, const struct phylink_link_state *);\n\tunsigned int (*pcs_inband_caps)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_enable)(struct phylink_pcs *);\n\tvoid (*pcs_disable)(struct phylink_pcs *);\n\tvoid (*pcs_pre_config)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_post_config)(struct phylink_pcs *, phy_interface_t);\n\tvoid (*pcs_get_state)(struct phylink_pcs *, unsigned int, struct phylink_link_state *);\n\tint (*pcs_config)(struct phylink_pcs *, unsigned int, phy_interface_t, const long unsigned int *, bool);\n\tvoid (*pcs_an_restart)(struct phylink_pcs *);\n\tvoid (*pcs_link_up)(struct phylink_pcs *, unsigned int, phy_interface_t, int, int);\n\tvoid (*pcs_disable_eee)(struct phylink_pcs *);\n\tvoid (*pcs_enable_eee)(struct phylink_pcs *);\n\tint (*pcs_pre_init)(struct phylink_pcs *);\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pids_cgroup {\n\tstruct cgroup_subsys_state css;\n\tatomic64_t counter;\n\tatomic64_t limit;\n\tint64_t watermark;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tatomic64_t events[2];\n\tatomic64_t events_local[2];\n};\n\nstruct pin_config_item {\n\tconst enum pin_config_param param;\n\tconst char * const display;\n\tconst char * const format;\n\tbool has_arg;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinctrl_setting_mux;\n\nstruct pin_desc {\n\tstruct pinctrl_dev *pctldev;\n\tconst char *name;\n\tbool dynamic_name;\n\tvoid *drv_data;\n\tunsigned int mux_usecount;\n\tconst char *mux_owner;\n\tconst struct pinctrl_setting_mux *mux_setting;\n\tconst char *gpio_owner;\n\tstruct mutex mux_lock;\n};\n\nstruct pinconf_generic_params {\n\tconst char * const property;\n\tenum pin_config_param param;\n\tu32 default_value;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinconf_ops {\n\tbool is_generic;\n\tint (*pin_config_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tint (*pin_config_group_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_group_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tvoid (*pin_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_group_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, long unsigned int);\n};\n\nstruct pinctrl {\n\tstruct list_head node;\n\tstruct device *dev;\n\tstruct list_head states;\n\tstruct pinctrl_state *state;\n\tstruct list_head dt_maps;\n\tstruct kref users;\n};\n\nstruct pinctrl_ops;\n\nstruct pinmux_ops;\n\nstruct pinctrl_desc {\n\tconst char *name;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct pinctrl_ops *pctlops;\n\tconst struct pinmux_ops *pmxops;\n\tconst struct pinconf_ops *confops;\n\tstruct module *owner;\n\tunsigned int num_custom_params;\n\tconst struct pinconf_generic_params *custom_params;\n\tconst struct pin_config_item *custom_conf_items;\n\tbool link_consumers;\n};\n\nstruct pinctrl_dev {\n\tstruct list_head node;\n\tconst struct pinctrl_desc *desc;\n\tstruct xarray pin_desc_tree;\n\tstruct xarray pin_group_tree;\n\tunsigned int num_groups;\n\tstruct xarray pin_function_tree;\n\tunsigned int num_functions;\n\tstruct list_head gpio_ranges;\n\tstruct device *dev;\n\tstruct module *owner;\n\tvoid *driver_data;\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *hog_default;\n\tstruct pinctrl_state *hog_sleep;\n\tstruct mutex mutex;\n\tstruct dentry *device_root;\n};\n\nstruct pinctrl_map;\n\nstruct pinctrl_dt_map {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_map *map;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_map_mux {\n\tconst char *group;\n\tconst char *function;\n};\n\nstruct pinctrl_map_configs {\n\tconst char *group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_map {\n\tconst char *dev_name;\n\tconst char *name;\n\tenum pinctrl_map_type type;\n\tconst char *ctrl_dev_name;\n\tunion {\n\t\tstruct pinctrl_map_mux mux;\n\t\tstruct pinctrl_map_configs configs;\n\t} data;\n};\n\nstruct pinctrl_maps {\n\tstruct list_head node;\n\tconst struct pinctrl_map *maps;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_ops {\n\tint (*get_groups_count)(struct pinctrl_dev *);\n\tconst char * (*get_group_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_group_pins)(struct pinctrl_dev *, unsigned int, const unsigned int **, unsigned int *);\n\tvoid (*pin_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tint (*dt_node_to_map)(struct pinctrl_dev *, struct device_node *, struct pinctrl_map **, unsigned int *);\n\tvoid (*dt_free_map)(struct pinctrl_dev *, struct pinctrl_map *, unsigned int);\n};\n\nstruct pinctrl_pin_desc {\n\tunsigned int number;\n\tconst char *name;\n\tvoid *drv_data;\n};\n\nstruct pinctrl_setting_mux {\n\tunsigned int group;\n\tunsigned int func;\n};\n\nstruct pinctrl_setting_configs {\n\tunsigned int group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_setting {\n\tstruct list_head node;\n\tenum pinctrl_map_type type;\n\tstruct pinctrl_dev *pctldev;\n\tconst char *dev_name;\n\tunion {\n\t\tstruct pinctrl_setting_mux mux;\n\t\tstruct pinctrl_setting_configs configs;\n\t} data;\n};\n\nstruct pinctrl_state {\n\tstruct list_head node;\n\tconst char *name;\n\tstruct list_head settings;\n};\n\nstruct pinfunction {\n\tconst char *name;\n\tconst char * const *groups;\n\tsize_t ngroups;\n\tlong unsigned int flags;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinmux_ops {\n\tint (*request)(struct pinctrl_dev *, unsigned int);\n\tint (*free)(struct pinctrl_dev *, unsigned int);\n\tint (*get_functions_count)(struct pinctrl_dev *);\n\tconst char * (*get_function_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_function_groups)(struct pinctrl_dev *, unsigned int, const char * const **, unsigned int *);\n\tbool (*function_is_gpio)(struct pinctrl_dev *, unsigned int);\n\tint (*set_mux)(struct pinctrl_dev *, unsigned int, unsigned int);\n\tint (*gpio_request_enable)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tvoid (*gpio_disable_free)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tint (*gpio_set_direction)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int, bool);\n\tbool strict;\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe_buffer;\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct pipe_wait {\n\tstruct trace_iterator *iter;\n\tint wait_index;\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tunsigned int uartclk;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tunsigned int type;\n\tupf_t flags;\n\tu16 bugs;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)(void);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tvoid (*check)(void);\n\tbool (*wake)(void);\n\tvoid (*restore_early)(void);\n\tvoid (*restore)(void);\n\tvoid (*end)(void);\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)(void);\n\tvoid (*finish)(void);\n\tbool (*suspend_again)(void);\n\tvoid (*end)(void);\n\tvoid (*recover)(void);\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct plda_pcie_rp;\n\nstruct plda_event {\n\tint (*request_event_irq)(struct plda_pcie_rp *, int, int);\n\tint intx_event;\n\tint msi_event;\n};\n\nstruct plda_event_ops {\n\tu32 (*get_events)(struct plda_pcie_rp *);\n};\n\nstruct plda_msi {\n\tstruct mutex lock;\n\tstruct irq_domain *dev_domain;\n\tu32 num_vectors;\n\tu64 vector_phy;\n\tlong unsigned int used[1];\n};\n\nstruct plda_pcie_host_ops {\n\tint (*host_init)(struct plda_pcie_rp *);\n\tvoid (*host_deinit)(struct plda_pcie_rp *);\n};\n\nstruct plda_pcie_rp {\n\tstruct device *dev;\n\tstruct pci_host_bridge *bridge;\n\tstruct irq_domain *intx_domain;\n\tstruct irq_domain *event_domain;\n\traw_spinlock_t lock;\n\tstruct plda_msi msi;\n\tconst struct plda_event_ops *event_ops;\n\tconst struct irq_chip *event_irq_chip;\n\tconst struct plda_pcie_host_ops *host_ops;\n\tvoid *bridge_addr;\n\tvoid *config_base;\n\tlong unsigned int events_bitmap;\n\tint irq;\n\tint msi_irq;\n\tint intx_irq;\n\tint num_events;\n};\n\nstruct plic_priv;\n\nstruct plic_handler {\n\tbool present;\n\tvoid *hart_base;\n\traw_spinlock_t enable_lock;\n\tvoid *enable_base;\n\tu32 *enable_save;\n\tstruct plic_priv *priv;\n};\n\nstruct plic_priv {\n\tstruct fwnode_handle *fwnode;\n\tstruct cpumask lmask;\n\tstruct irq_domain *irqdomain;\n\tvoid *regs;\n\tlong unsigned int plic_quirks;\n\tunsigned int total_irqs;\n\tunsigned int irq_groups;\n\tlong unsigned int *prio_save;\n\tu32 gsi_base;\n\tint acpi_plic_id;\n};\n\nstruct pm_clk_notifier_block {\n\tstruct notifier_block nb;\n\tstruct dev_pm_domain *pm_domain;\n\tchar *con_ids[0];\n};\n\nstruct pm_clock_entry {\n\tstruct list_head node;\n\tchar *con_id;\n\tstruct clk *clk;\n\tenum pce_status status;\n\tbool enabled_when_prepared;\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n\tunsigned int clock_op_might_sleep;\n\tstruct mutex clock_mutex;\n\tstruct list_head clock_list;\n\tstruct pm_domain_data *domain_data;\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct pmem_device {\n\tphys_addr_t phys_addr;\n\tphys_addr_t data_offset;\n\tvoid *virt_addr;\n\tsize_t size;\n\tu32 pfn_pad;\n\tstruct kernfs_node *bb_state;\n\tstruct badblocks bb;\n\tstruct dax_device *dax_dev;\n\tstruct gendisk *disk;\n\tstruct dev_pagemap pgmap;\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct pnfs_commit_bucket {\n\tstruct list_head written;\n\tstruct list_head committing;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_writeverf direct_verf;\n};\n\nstruct pnfs_commit_array {\n\tstruct list_head cinfo_list;\n\tstruct list_head lseg_list;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tunsigned int nbuckets;\n\tstruct pnfs_commit_bucket buckets[0];\n};\n\nstruct pnfs_commit_ops {\n\tvoid (*setup_ds_info)(struct pnfs_ds_commit_info *, struct pnfs_layout_segment *);\n\tvoid (*release_ds_info)(struct pnfs_ds_commit_info *, struct inode *);\n\tint (*commit_pagelist)(struct inode *, struct list_head *, int, struct nfs_commit_info *);\n\tvoid (*mark_request_commit)(struct nfs_page *, struct pnfs_layout_segment *, struct nfs_commit_info *, u32);\n\tvoid (*clear_request_commit)(struct nfs_page *, struct nfs_commit_info *);\n\tint (*scan_commit_lists)(struct nfs_commit_info *, int);\n\tvoid (*recover_commit_reqs)(struct list_head *, struct nfs_commit_info *);\n};\n\nstruct pnfs_device {\n\tstruct nfs4_deviceid dev_id;\n\tunsigned int layout_type;\n\tunsigned int mincount;\n\tunsigned int maxcount;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tunsigned char nocache: 1;\n};\n\nstruct pnfs_layoutdriver_type {\n\tstruct list_head pnfs_tblid;\n\tconst u32 id;\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int flags;\n\tunsigned int max_layoutget_response;\n\tint (*set_layoutdriver)(struct nfs_server *, const struct nfs_fh *);\n\tint (*clear_layoutdriver)(struct nfs_server *);\n\tstruct pnfs_layout_hdr * (*alloc_layout_hdr)(struct inode *, gfp_t);\n\tvoid (*free_layout_hdr)(struct pnfs_layout_hdr *);\n\tstruct pnfs_layout_segment * (*alloc_lseg)(struct pnfs_layout_hdr *, struct nfs4_layoutget_res *, gfp_t);\n\tvoid (*free_lseg)(struct pnfs_layout_segment *);\n\tvoid (*add_lseg)(struct pnfs_layout_hdr *, struct pnfs_layout_segment *, struct list_head *);\n\tvoid (*return_range)(struct pnfs_layout_hdr *, struct pnfs_layout_range *);\n\tconst struct nfs_pageio_ops *pg_read_ops;\n\tconst struct nfs_pageio_ops *pg_write_ops;\n\tstruct pnfs_ds_commit_info * (*get_ds_info)(struct inode *);\n\tint (*sync)(struct inode *, bool);\n\tenum pnfs_try_status (*read_pagelist)(struct nfs_pgio_header *);\n\tenum pnfs_try_status (*write_pagelist)(struct nfs_pgio_header *, int);\n\tvoid (*free_deviceid_node)(struct nfs4_deviceid_node *);\n\tstruct nfs4_deviceid_node * (*alloc_deviceid_node)(struct nfs_server *, struct pnfs_device *, gfp_t);\n\tint (*prepare_layoutreturn)(struct nfs4_layoutreturn_args *);\n\tvoid (*cleanup_layoutcommit)(struct nfs4_layoutcommit_data *);\n\tint (*prepare_layoutcommit)(struct nfs4_layoutcommit_args *);\n\tint (*prepare_layoutstats)(struct nfs42_layoutstat_args *);\n\tvoid (*cancel_io)(struct pnfs_layout_segment *);\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_device_id;\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_link;\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_dma {\n\tunsigned char map;\n\tunsigned char flags;\n};\n\nstruct pnp_fixup {\n\tchar id[8];\n\tvoid (*quirk_function)(struct pnp_dev *);\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_info_buffer {\n\tchar *buffer;\n\tchar *curr;\n\tlong unsigned int size;\n\tlong unsigned int len;\n\tint stop;\n\tint error;\n};\n\ntypedef struct pnp_info_buffer pnp_info_buffer_t;\n\nstruct pnp_irq {\n\tpnp_irq_mask_t map;\n\tunsigned char flags;\n};\n\nstruct pnp_mem {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_port {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_option {\n\tstruct list_head list;\n\tunsigned int flags;\n\tlong unsigned int type;\n\tunion {\n\t\tstruct pnp_port port;\n\t\tstruct pnp_irq irq;\n\t\tstruct pnp_dma dma;\n\t\tstruct pnp_mem mem;\n\t} u;\n};\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pnp_resource {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct policy_file;\n\nstruct policy_data {\n\tstruct policydb *p;\n\tstruct policy_file *fp;\n};\n\nstruct policy_file {\n\tchar *data;\n\tsize_t len;\n};\n\nstruct policy_load_memory {\n\tsize_t len;\n\tvoid *data;\n};\n\nstruct role_datum;\n\nstruct user_datum;\n\nstruct type_datum;\n\nstruct role_allow;\n\nstruct policydb {\n\tint mls_enabled;\n\tstruct symtab symtab[8];\n\tchar **sym_val_to_name[8];\n\tstruct class_datum **class_val_to_struct;\n\tstruct role_datum **role_val_to_struct;\n\tstruct user_datum **user_val_to_struct;\n\tstruct type_datum **type_val_to_struct;\n\tstruct avtab te_avtab;\n\tstruct hashtab role_tr;\n\tstruct ebitmap filename_trans_ttypes;\n\tstruct hashtab filename_trans;\n\tu32 compat_filename_trans_count;\n\tstruct cond_bool_datum **bool_val_to_struct;\n\tstruct avtab te_cond_avtab;\n\tstruct cond_node *cond_list;\n\tu32 cond_list_len;\n\tstruct role_allow *role_allow;\n\tstruct ocontext *ocontexts[9];\n\tstruct genfs *genfs;\n\tstruct hashtab range_tr;\n\tstruct ebitmap *type_attr_map_array;\n\tstruct ebitmap policycaps;\n\tstruct ebitmap permissive_map;\n\tstruct ebitmap neveraudit_map;\n\tsize_t len;\n\tunsigned int policyvers;\n\tunsigned int reject_unknown: 1;\n\tunsigned int allow_unknown: 1;\n\tu16 process_class;\n\tu32 process_trans_perms;\n};\n\nstruct policydb_compat_info {\n\tunsigned int version;\n\tunsigned int sym_num;\n\tunsigned int ocon_num;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[9];\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct port_stats {\n\tlong unsigned int bytes_sent;\n\tlong unsigned int bytes_received;\n\tlong unsigned int bytes_discarded;\n};\n\nstruct ports_device;\n\nstruct port_buffer;\n\nstruct virtqueue;\n\nstruct port {\n\tstruct list_head list;\n\tstruct ports_device *portdev;\n\tstruct port_buffer *inbuf;\n\tspinlock_t inbuf_lock;\n\tspinlock_t outvq_lock;\n\tstruct virtqueue *in_vq;\n\tstruct virtqueue *out_vq;\n\tstruct dentry *debugfs_file;\n\tstruct port_stats stats;\n\tstruct console___2 cons;\n\tstruct cdev *cdev;\n\tstruct device *dev;\n\tstruct kref kref;\n\twait_queue_head_t waitqueue;\n\tchar *name;\n\tstruct fasync_struct *async_queue;\n\tu32 id;\n\tbool outvq_full;\n\tbool host_connected;\n\tbool guest_connected;\n};\n\nstruct port_buffer {\n\tchar *buf;\n\tsize_t size;\n\tsize_t len;\n\tsize_t offset;\n\tdma_addr_t dma;\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int sgpages;\n\tstruct scatterlist sg[0];\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct portdrv_service_data {\n\tstruct pcie_port_service_driver *drv;\n\tstruct device *dev;\n\tu32 service;\n};\n\nstruct virtio_console_control {\n\t__virtio32 id;\n\t__virtio16 event;\n\t__virtio16 value;\n};\n\nstruct virtio_device;\n\nstruct ports_device {\n\tstruct list_head list;\n\tstruct work_struct control_work;\n\tstruct work_struct config_work;\n\tstruct list_head ports;\n\tspinlock_t ports_lock;\n\tspinlock_t c_ivq_lock;\n\tspinlock_t c_ovq_lock;\n\tu32 max_nr_ports;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *c_ivq;\n\tstruct virtqueue *c_ovq;\n\tstruct virtio_console_control cpkt;\n\tstruct virtqueue **in_vqs;\n\tstruct virtqueue **out_vqs;\n\tint chr_major;\n};\n\nstruct ports_driver_data {\n\tstruct dentry *debugfs_dir;\n\tstruct list_head portdevs;\n\tstruct list_head consoles;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct posix_cputimers_work {\n\tstruct callback_head work;\n\tstruct mutex mutex;\n\tunsigned int scheduled;\n};\n\nstruct posix_msg_tree_node {\n\tstruct rb_node rb_node;\n\tstruct list_head msg_list;\n\tint priority;\n};\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct power_supply_battery_info;\n\nstruct power_supply {\n\tconst struct power_supply_desc *desc;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tchar **supplied_from;\n\tsize_t num_supplies;\n\tvoid *drv_data;\n\tstruct device dev;\n\tstruct work_struct changed_work;\n\tstruct delayed_work deferred_register_work;\n\tspinlock_t changed_lock;\n\tbool changed;\n\tbool update_groups;\n\tbool initialized;\n\tbool removing;\n\tatomic_t use_cnt;\n\tstruct power_supply_battery_info *battery_info;\n\tstruct rw_semaphore extensions_sem;\n\tstruct list_head extensions;\n\tstruct thermal_zone_device *tzd;\n\tstruct thermal_cooling_device *tcd;\n};\n\nstruct power_supply_attr {\n\tconst char *prop_name;\n\tchar attr_name[31];\n\tstruct device_attribute dev_attr;\n\tconst char * const *text_values;\n\tint text_values_len;\n};\n\nstruct power_supply_maintenance_charge_table;\n\nstruct power_supply_battery_ocv_table;\n\nstruct power_supply_resistance_temp_table;\n\nstruct power_supply_vbat_ri_table;\n\nstruct power_supply_battery_info {\n\tunsigned int technology;\n\tint energy_full_design_uwh;\n\tint charge_full_design_uah;\n\tint voltage_min_design_uv;\n\tint voltage_max_design_uv;\n\tint tricklecharge_current_ua;\n\tint precharge_current_ua;\n\tint precharge_voltage_max_uv;\n\tint charge_term_current_ua;\n\tint charge_restart_voltage_uv;\n\tint overvoltage_limit_uv;\n\tint constant_charge_current_max_ua;\n\tint constant_charge_voltage_max_uv;\n\tconst struct power_supply_maintenance_charge_table *maintenance_charge;\n\tint maintenance_charge_size;\n\tint alert_low_temp_charge_current_ua;\n\tint alert_low_temp_charge_voltage_uv;\n\tint alert_high_temp_charge_current_ua;\n\tint alert_high_temp_charge_voltage_uv;\n\tint factory_internal_resistance_uohm;\n\tint factory_internal_resistance_charging_uohm;\n\tint ocv_temp[20];\n\tint temp_ambient_alert_min;\n\tint temp_ambient_alert_max;\n\tint temp_alert_min;\n\tint temp_alert_max;\n\tint temp_min;\n\tint temp_max;\n\tconst struct power_supply_battery_ocv_table *ocv_table[20];\n\tint ocv_table_size[20];\n\tconst struct power_supply_resistance_temp_table *resist_table;\n\tint resist_table_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_discharging;\n\tint vbat2ri_discharging_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_charging;\n\tint vbat2ri_charging_size;\n\tint bti_resistance_ohm;\n\tint bti_resistance_tolerance;\n};\n\nstruct power_supply_battery_ocv_table {\n\tint ocv;\n\tint capacity;\n};\n\nstruct power_supply_config {\n\tstruct fwnode_handle *fwnode;\n\tvoid *drv_data;\n\tconst struct attribute_group **attr_grp;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tbool no_wakeup_source;\n};\n\nstruct power_supply_ext {\n\tconst char * const name;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property);\n};\n\nstruct power_supply_ext_registration {\n\tstruct list_head list_head;\n\tconst struct power_supply_ext *ext;\n\tstruct device *dev;\n\tvoid *data;\n};\n\nstruct power_supply_hwmon {\n\tstruct power_supply *psy;\n\tlong unsigned int *props;\n};\n\nstruct power_supply_maintenance_charge_table {\n\tint charge_current_max_ua;\n\tint charge_voltage_max_uv;\n\tint charge_safety_timer_minutes;\n};\n\nunion power_supply_propval {\n\tint intval;\n\tconst char *strval;\n};\n\nstruct power_supply_resistance_temp_table {\n\tint temp;\n\tint resistance;\n};\n\nstruct power_supply_vbat_ri_table {\n\tint vbat_uv;\n\tint ri_uohm;\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prci_clk_desc {\n\tstruct __prci_clock *clks;\n\tsize_t num_clks;\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n};\n\nstruct pre_voltage_change_data {\n\tlong unsigned int old_uV;\n\tlong unsigned int min_uV;\n\tlong unsigned int max_uV;\n};\n\nstruct preempt_ops;\n\nstruct preempt_notifier {\n\tstruct hlist_node link;\n\tstruct preempt_ops *ops;\n};\n\nstruct preempt_ops {\n\tvoid (*sched_in)(struct preempt_notifier *, int);\n\tvoid (*sched_out)(struct preempt_notifier *, struct task_struct *);\n};\n\nstruct prefix_cacheinfo {\n\t__u32 preferred_time;\n\t__u32 valid_time;\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\tunion {\n\t\t__u8 flags;\n\t\tstruct {\n\t\t\t__u8 reserved: 4;\n\t\t\t__u8 preferpd: 1;\n\t\t\t__u8 routeraddr: 1;\n\t\t\t__u8 autoconf: 1;\n\t\t\t__u8 onlink: 1;\n\t\t};\n\t};\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct prefixmsg {\n\tunsigned char prefix_family;\n\tunsigned char prefix_pad1;\n\tshort unsigned int prefix_pad2;\n\tint prefix_ifindex;\n\tunsigned char prefix_type;\n\tunsigned char prefix_len;\n\tunsigned char prefix_flags;\n\tunsigned char prefix_pad3;\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct private_data {\n\tstruct list_head node;\n\tcpumask_var_t cpus;\n\tstruct device *cpu_dev;\n\tstruct cpufreq_frequency_table *freq_table;\n\tbool have_static_opps;\n\tint opp_token;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct probe_entry_arg {\n\tstruct fetch_insn *code;\n\tunsigned int size;\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_nfs_info {\n\tint flag;\n\tconst char *str;\n\tconst char *nostr;\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*proc_compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tstruct timespec64 val;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n\tstruct bin_attribute attr;\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*compat_ioctl)(struct sock *, unsigned int, long unsigned int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct prt_quirk {\n\tconst struct dmi_system_id *system;\n\tunsigned int segment;\n\tunsigned int bus;\n\tunsigned int device;\n\tunsigned char pin;\n\tconst char *source;\n\tconst char *actual_source;\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct psample_group {\n\tstruct list_head list;\n\tstruct net *net;\n\tu32 group_num;\n\tu32 refcount;\n\tu32 seq;\n\tstruct callback_head rcu;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psi_group {};\n\nstruct psmouse_protocol;\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct psy_am_i_supplied_data {\n\tstruct power_supply *psy;\n\tunsigned int count;\n};\n\nstruct psy_for_each_psy_cb_data {\n\tint (*fn)(struct power_supply *, void *);\n\tvoid *data;\n};\n\nstruct psy_get_supplier_prop_data {\n\tstruct power_supply *psy;\n\tenum power_supply_property psp;\n\tunion power_supply_propval *val;\n};\n\nstruct pt_alloc_ops {\n\tpte_t * (*get_pte_virt)(phys_addr_t);\n\tphys_addr_t (*alloc_pte)(uintptr_t);\n\tpmd_t * (*get_pmd_virt)(phys_addr_t);\n\tphys_addr_t (*alloc_pmd)(uintptr_t);\n\tpud_t * (*get_pud_virt)(phys_addr_t);\n\tphys_addr_t (*alloc_pud)(uintptr_t);\n\tp4d_t * (*get_p4d_virt)(phys_addr_t);\n\tphys_addr_t (*alloc_p4d)(uintptr_t);\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t\tatomic_t pt_share_count;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int pt_memcg_data;\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\ts64 offset;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_perout_request {\n\tunion {\n\t\tstruct ptp_clock_time start;\n\t\tstruct ptp_clock_time phase;\n\t};\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunion {\n\t\tstruct ptp_clock_time on;\n\t\tunsigned int rsv[4];\n\t};\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n\tclockid_t clockid;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_sud_config {\n\t__u64 mode;\n\t__u64 selector;\n\t__u64 offset;\n\t__u64 len;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct pwm_args {\n\tu64 period;\n\tenum pwm_polarity polarity;\n};\n\nstruct pwm_capture {\n\tunsigned int period;\n\tunsigned int duty_cycle;\n};\n\nstruct pwm_chip;\n\nstruct pwm_device;\n\nstruct pwm_cdev_data {\n\tstruct pwm_chip *chip;\n\tstruct pwm_device *pwm[0];\n};\n\ntypedef struct pwm_chip *class_pwmchip_t;\n\nstruct pwm_state {\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tbool usage_power;\n};\n\nstruct pwm_device {\n\tconst char *label;\n\tlong unsigned int flags;\n\tunsigned int hwpwm;\n\tstruct pwm_chip *chip;\n\tstruct pwm_args args;\n\tstruct pwm_state state;\n\tstruct pwm_state last;\n};\n\nstruct pwm_ops;\n\nstruct pwm_chip {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tconst struct pwm_ops *ops;\n\tstruct module *owner;\n\tunsigned int id;\n\tunsigned int npwm;\n\tstruct pwm_device * (*of_xlate)(struct pwm_chip *, const struct of_phandle_args *);\n\tbool atomic;\n\tstruct gpio_chip gpio;\n\tbool uses_pwmchip_alloc;\n\tbool operational;\n\tunion {\n\t\tstruct mutex nonatomic_lock;\n\t\tspinlock_t atomic_lock;\n\t};\n\tstruct pwm_device pwms[0];\n};\n\nstruct pwm_export {\n\tstruct device pwm_dev;\n\tstruct pwm_device *pwm;\n\tstruct mutex lock;\n\tstruct pwm_state suspend;\n};\n\nstruct pwm_lookup {\n\tstruct list_head list;\n\tconst char *provider;\n\tunsigned int index;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tunsigned int period;\n\tenum pwm_polarity polarity;\n\tconst char *module;\n};\n\nstruct pwm_waveform;\n\nstruct pwm_ops {\n\tint (*request)(struct pwm_chip *, struct pwm_device *);\n\tvoid (*free)(struct pwm_chip *, struct pwm_device *);\n\tint (*capture)(struct pwm_chip *, struct pwm_device *, struct pwm_capture *, long unsigned int);\n\tsize_t sizeof_wfhw;\n\tint (*round_waveform_tohw)(struct pwm_chip *, struct pwm_device *, const struct pwm_waveform *, void *);\n\tint (*round_waveform_fromhw)(struct pwm_chip *, struct pwm_device *, const void *, struct pwm_waveform *);\n\tint (*read_waveform)(struct pwm_chip *, struct pwm_device *, void *);\n\tint (*write_waveform)(struct pwm_chip *, struct pwm_device *, const void *);\n\tint (*apply)(struct pwm_chip *, struct pwm_device *, const struct pwm_state *);\n\tint (*get_state)(struct pwm_chip *, struct pwm_device *, struct pwm_state *);\n};\n\nstruct pwm_waveform {\n\tu64 period_length_ns;\n\tu64 duty_length_ns;\n\tu64 duty_offset_ns;\n};\n\nstruct pwmchip_waveform {\n\t__u32 hwpwm;\n\t__u32 __pad;\n\t__u64 period_length_ns;\n\t__u64 duty_length_ns;\n\t__u64 duty_offset_ns;\n};\n\nstruct pwrseq_device;\n\ntypedef int (*pwrseq_match_func)(struct pwrseq_device *, struct device *);\n\nstruct pwrseq_target_data;\n\nstruct pwrseq_config {\n\tstruct device *parent;\n\tstruct module *owner;\n\tvoid *drvdata;\n\tpwrseq_match_func match;\n\tconst struct pwrseq_target_data **targets;\n};\n\nstruct pwrseq_debugfs_count_ctx {\n\tstruct device *dev;\n\tloff_t index;\n};\n\nstruct pwrseq_target;\n\nstruct pwrseq_desc {\n\tstruct pwrseq_device *pwrseq;\n\tstruct pwrseq_target *target;\n\tbool powered_on;\n};\n\nstruct pwrseq_device {\n\tstruct device dev;\n\tint id;\n\tstruct module *owner;\n\tstruct rw_semaphore rw_lock;\n\tstruct mutex state_lock;\n\tpwrseq_match_func match;\n\tstruct list_head targets;\n\tstruct list_head units;\n};\n\nstruct pwrseq_match_data {\n\tstruct pwrseq_desc *desc;\n\tstruct device *dev;\n\tconst char *target;\n};\n\ntypedef int (*pwrseq_power_state_func)(struct pwrseq_device *);\n\nstruct pwrseq_unit;\n\nstruct pwrseq_target {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct pwrseq_unit *unit;\n\tpwrseq_power_state_func post_enable;\n};\n\nstruct pwrseq_unit_data;\n\nstruct pwrseq_target_data {\n\tconst char *name;\n\tconst struct pwrseq_unit_data *unit;\n\tpwrseq_power_state_func post_enable;\n};\n\nstruct pwrseq_unit {\n\tstruct kref ref;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct list_head deps;\n\tpwrseq_power_state_func enable;\n\tpwrseq_power_state_func disable;\n\tunsigned int enable_count;\n};\n\nstruct pwrseq_unit_data {\n\tconst char *name;\n\tconst struct pwrseq_unit_data **deps;\n\tpwrseq_power_state_func enable;\n\tpwrseq_power_state_func disable;\n};\n\nstruct pwrseq_unit_dep {\n\tstruct list_head list;\n\tstruct pwrseq_unit *unit;\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qdisc_dump_args {\n\tstruct qdisc_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct qdisc_rate_table {\n\tstruct tc_ratespec rate;\n\tu32 data[256];\n\tstruct qdisc_rate_table *next;\n\tint refcnt;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_watchdog {\n\tstruct hrtimer timer;\n\tstruct Qdisc *qdisc;\n};\n\nstruct qnode {\n\tstruct mcs_spinlock mcs;\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct queue_pages {\n\tstruct list_head *pagelist;\n\tlong unsigned int flags;\n\tnodemask_t *nmask;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct vm_area_struct *first;\n\tstruct folio *large;\n\tlong int nr_failed;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quirk_entry {\n\tu16 vid;\n\tu16 pid;\n\tu32 flags;\n};\n\nstruct quirks_list_struct {\n\tstruct hid_device_id hid_bl_item;\n\tstruct list_head node;\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct ra_msg {\n\tstruct icmp6hdr icmph;\n\t__be32 reachable_time;\n\t__be32 retrans_timer;\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct ramdax_dimm {\n\tstruct nvdimm *nvdimm;\n\tvoid *label_area;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct range_node {\n\tstruct rb_node rn_rbnode;\n\tstruct rb_node rb_range_size;\n\tu32 rn_start;\n\tu32 rn_last;\n\tu32 __rn_subtree_last;\n};\n\nstruct range_trans {\n\tu32 source_type;\n\tu32 target_type;\n\tu32 target_class;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n};\n\nstruct raw6_frag_vec {\n\tstruct msghdr *msg;\n\tint hlen;\n\tchar c[4];\n};\n\nstruct raw6_sock {\n\tstruct inet_sock inet;\n\t__u32 checksum;\n\t__u32 offset;\n\tstruct icmp6_filter filter;\n\t__u32 ip6mr_table;\n\tlong: 0;\n\tstruct numa_drop_counters drop_counters;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct rawdata_f_data {\n\tstruct aa_loaddata *loaddata;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tu64 before;\n\tu64 after;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tatomic_t seq;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rb_time_struct {\n\tlocal64_t time;\n};\n\ntypedef struct rb_time_struct rb_time_t;\n\nstruct rb_wait_data {\n\tstruct rb_irq_work *irq_work;\n\tint seq;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct rcec_ea {\n\tu8 nextbusn;\n\tu8 lastbusn;\n\tu32 bitmap;\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t fqslock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[5];\n\tstruct rcu_node *level[3];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rcu_tasks;\n\ntypedef void (*rcu_tasks_gp_func_t)(struct rcu_tasks *);\n\ntypedef void (*pregp_func_t)(struct list_head *);\n\ntypedef void (*pertask_func_t)(struct task_struct *, struct list_head *);\n\ntypedef void (*postscan_func_t)(struct list_head *);\n\ntypedef void (*holdouts_func_t)(struct list_head *, bool, bool *);\n\ntypedef void (*postgp_func_t)(struct rcu_tasks *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\nstruct rcu_tasks_percpu;\n\nstruct rcu_tasks {\n\tstruct rcuwait cbs_wait;\n\traw_spinlock_t cbs_gbl_lock;\n\tstruct mutex tasks_gp_mutex;\n\tint gp_state;\n\tint gp_sleep;\n\tint init_fract;\n\tlong unsigned int gp_jiffies;\n\tlong unsigned int gp_start;\n\tlong unsigned int tasks_gp_seq;\n\tlong unsigned int n_ipis;\n\tlong unsigned int n_ipis_fails;\n\tstruct task_struct *kthread_ptr;\n\tlong unsigned int lazy_jiffies;\n\trcu_tasks_gp_func_t gp_func;\n\tpregp_func_t pregp_func;\n\tpertask_func_t pertask_func;\n\tpostscan_func_t postscan_func;\n\tholdouts_func_t holdouts_func;\n\tpostgp_func_t postgp_func;\n\tcall_rcu_func_t call_func;\n\tunsigned int wait_state;\n\tstruct rcu_tasks_percpu *rtpcpu;\n\tstruct rcu_tasks_percpu **rtpcp_array;\n\tint percpu_enqueue_shift;\n\tint percpu_enqueue_lim;\n\tint percpu_dequeue_lim;\n\tlong unsigned int percpu_dequeue_gpseq;\n\tstruct mutex barrier_q_mutex;\n\tatomic_t barrier_q_count;\n\tstruct completion barrier_q_completion;\n\tlong unsigned int barrier_q_seq;\n\tlong unsigned int barrier_q_start;\n\tchar *name;\n\tchar *kname;\n};\n\nstruct rcu_tasks_percpu {\n\tstruct rcu_segcblist cblist;\n\traw_spinlock_t lock;\n\tlong unsigned int rtp_jiffies;\n\tlong unsigned int rtp_n_lock_retries;\n\tstruct timer_list lazy_timer;\n\tunsigned int urgent_gp;\n\tstruct work_struct rtp_work;\n\tstruct irq_work rtp_irq_work;\n\tstruct callback_head barrier_q_head;\n\tstruct list_head rtp_blkd_tasks;\n\tstruct list_head rtp_exit_list;\n\tint cpu;\n\tint index;\n\tstruct rcu_tasks *rtpp;\n};\n\nstruct rd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\tstruct in6_addr dest;\n\t__u8 opt[0];\n};\n\nstruct rdma_ah_init_attr {\n\tstruct rdma_ah_attr *ah_attr;\n\tu32 flags;\n\tstruct net_device *xmit_slave;\n};\n\nstruct rdma_counter {\n\tstruct rdma_restrack_entry res;\n\tstruct ib_device *device;\n\tuint32_t id;\n\tstruct kref kref;\n\tstruct rdma_counter_mode mode;\n\tstruct mutex lock;\n\tstruct rdma_hw_stats *stats;\n\tu32 port;\n};\n\nstruct rdma_stat_desc;\n\nstruct rdma_hw_stats {\n\tstruct mutex lock;\n\tlong unsigned int timestamp;\n\tlong unsigned int lifespan;\n\tconst struct rdma_stat_desc *descs;\n\tlong unsigned int *is_disabled;\n\tint num_counters;\n\tu64 value[0];\n};\n\nstruct rdma_link_ops {\n\tstruct list_head list;\n\tconst char *type;\n\tint (*newlink)(const char *, struct net_device *);\n};\n\nstruct rdma_netdev_alloc_params {\n\tsize_t sizeof_priv;\n\tunsigned int txqs;\n\tunsigned int rxqs;\n\tvoid *param;\n\tint (*initialize_rdma_netdev)(struct ib_device *, u32, struct net_device *, void *);\n};\n\nstruct rdma_stat_desc {\n\tconst char *name;\n\tunsigned int flags;\n\tconst void *priv;\n};\n\nstruct rdma_user_mmap_entry {\n\tstruct kref ref;\n\tstruct ib_ucontext *ucontext;\n\tlong unsigned int start_pgoff;\n\tsize_t npages;\n\tbool driver_removed;\n\tstruct mutex dmabufs_lock;\n\tstruct list_head dmabufs;\n};\n\nstruct read_plus_segment {\n\tenum data_content4 type;\n\tuint64_t offset;\n\tunion {\n\t\tstruct {\n\t\t\tuint64_t length;\n\t\t} hole;\n\t\tstruct {\n\t\t\tuint32_t length;\n\t\t\tunsigned int from;\n\t\t} data;\n\t};\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct reboot_mode_bits {\n\tu32 offset;\n\tu32 mask;\n\tu32 value;\n\tbool valid;\n};\n\nstruct reboot_data {\n\tstruct reboot_mode_bits mode_bits[4];\n\tstruct reboot_mode_bits catchall;\n};\n\nstruct virtnet_rq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t drops;\n\tu64_stats_t xdp_packets;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_redirects;\n\tu64_stats_t xdp_drops;\n\tu64_stats_t kicks;\n};\n\nstruct virtnet_interrupt_coalesce {\n\tu32 max_packets;\n\tu32 max_usecs;\n};\n\nstruct virtnet_rq_dma;\n\nstruct receive_queue {\n\tstruct virtqueue *vq;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tstruct virtnet_rq_stats stats;\n\tu16 calls;\n\tbool dim_enabled;\n\tstruct mutex dim_lock;\n\tstruct dim dim;\n\tu32 packets_in_napi;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct page *pages;\n\tstruct ewma_pkt_len mrg_avg_pkt_len;\n\tstruct page_frag alloc_frag;\n\tstruct scatterlist sg[19];\n\tunsigned int min_buf_len;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct virtnet_rq_dma *last_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xsk_rxq_info;\n\tstruct xdp_buff **xsk_buffs;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tlong unsigned int head_block;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\nstruct referring_call {\n\tuint32_t rc_sequenceid;\n\tuint32_t rc_slotid;\n};\n\nstruct referring_call_list {\n\tstruct nfs4_sessionid rcl_sessionid;\n\tuint32_t rcl_nrefcalls;\n\tstruct referring_call *rcl_refcalls;\n};\n\nunion reg_data {\n\tu8 data_bytes[8];\n\tulong data_ulong;\n\tu64 data_u64;\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nstruct reg_val {\n\tu16 reg;\n\tu32 val;\n};\n\nstruct regcache_flat_data {\n\tlong unsigned int *valid;\n\tunsigned int data[0];\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tint (*populate)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regcache_rbtree_node;\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong unsigned int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\nstruct region_info_user {\n\t__u32 offset;\n\t__u32 erasesize;\n\t__u32 numblocks;\n\t__u32 regionindex;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\ts8 reg_shift;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct hwspinlock;\n\nstruct regmap_bus;\n\nstruct regmap_access_table;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_spinlock;\n\t\t\tlong unsigned int raw_spinlock_flags;\n\t\t};\n\t};\n\tstruct lock_class_key *lock_key;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tunsigned int reg_base;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool async;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool max_register_is_set;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tbool defer_caching;\n\tbool force_write_field;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool can_sleep;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regmap_range;\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\nstruct regmap_async_spi {\n\tstruct regmap_async core;\n\tstruct spi_message m;\n\tstruct spi_transfer t[2];\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_noinc_write)(void *, unsigned int, const void *, size_t);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_noinc_read)(void *, unsigned int, void *, size_t);\n\ntypedef void (*regmap_hw_free_context)(void *);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)(void);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tbool free_on_exit;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_noinc_write reg_noinc_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_reg_noinc_read reg_noinc_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint reg_shift;\n\tunsigned int reg_base;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tbool can_sleep;\n\tbool fast_io;\n\tbool io_port;\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tunsigned int max_register;\n\tbool max_register_is_0;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool use_relaxed_mmio;\n\tbool can_multi_write;\n\tbool use_hwlock;\n\tbool use_raw_spinlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tstruct list_head link;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_irq_type {\n\tunsigned int type_reg_offset;\n\tunsigned int type_reg_mask;\n\tunsigned int type_rising_val;\n\tunsigned int type_falling_val;\n\tunsigned int type_level_low_val;\n\tunsigned int type_level_high_val;\n\tunsigned int types_supported;\n};\n\nstruct regmap_irq {\n\tunsigned int reg_offset;\n\tunsigned int mask;\n\tstruct regmap_irq_type type;\n};\n\nstruct regmap_irq_sub_irq_map;\n\nstruct regmap_irq_chip {\n\tconst char *name;\n\tconst char *domain_suffix;\n\tunsigned int main_status;\n\tunsigned int num_main_status_bits;\n\tconst struct regmap_irq_sub_irq_map *sub_reg_offsets;\n\tint num_main_regs;\n\tunsigned int status_base;\n\tunsigned int mask_base;\n\tunsigned int unmask_base;\n\tunsigned int ack_base;\n\tunsigned int wake_base;\n\tconst unsigned int *config_base;\n\tunsigned int irq_reg_stride;\n\tunsigned int init_ack_masked: 1;\n\tunsigned int mask_unmask_non_inverted: 1;\n\tunsigned int use_ack: 1;\n\tunsigned int ack_invert: 1;\n\tunsigned int clear_ack: 1;\n\tunsigned int status_invert: 1;\n\tunsigned int status_is_level: 1;\n\tunsigned int wake_invert: 1;\n\tunsigned int type_in_mask: 1;\n\tunsigned int clear_on_unmask: 1;\n\tunsigned int runtime_pm: 1;\n\tunsigned int no_status: 1;\n\tint num_regs;\n\tconst struct regmap_irq *irqs;\n\tint num_irqs;\n\tint num_config_bases;\n\tint num_config_regs;\n\tint (*handle_pre_irq)(void *);\n\tint (*handle_post_irq)(void *);\n\tint (*handle_mask_sync)(int, unsigned int, unsigned int, void *);\n\tint (*set_type_config)(unsigned int **, unsigned int, const struct regmap_irq *, int, void *);\n\tunsigned int (*get_irq_reg)(struct regmap_irq_chip_data *, unsigned int, int);\n\tvoid *irq_drv_data;\n};\n\nstruct regmap_irq_chip_data {\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tstruct irq_chip irq_chip;\n\tstruct regmap *map;\n\tconst struct regmap_irq_chip *chip;\n\tint irq_base;\n\tstruct irq_domain *domain;\n\tint irq;\n\tint wake_count;\n\tvoid *status_reg_buf;\n\tunsigned int *main_status_buf;\n\tunsigned int *status_buf;\n\tunsigned int *prev_status_buf;\n\tunsigned int *mask_buf;\n\tunsigned int *mask_buf_def;\n\tunsigned int *wake_buf;\n\tunsigned int *type_buf;\n\tunsigned int *type_buf_def;\n\tunsigned int **config_buf;\n\tunsigned int irq_reg_stride;\n\tunsigned int (*get_irq_reg)(struct regmap_irq_chip_data *, unsigned int, int);\n\tunsigned int clear_status: 1;\n};\n\nstruct regmap_irq_sub_irq_map {\n\tunsigned int num_regs;\n\tunsigned int *offset;\n};\n\nstruct regmap_mmio_context {\n\tvoid *regs;\n\tunsigned int val_bytes;\n\tbool big_endian;\n\tbool attached_clk;\n\tstruct clk *clk;\n\tvoid (*reg_write)(struct regmap_mmio_context *, unsigned int, unsigned int);\n\tunsigned int (*reg_read)(struct regmap_mmio_context *, unsigned int);\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regulator_voltage {\n\tint min_uV;\n\tint max_uV;\n};\n\nstruct regulator {\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int always_on: 1;\n\tunsigned int bypass: 1;\n\tunsigned int device_link: 1;\n\tint uA_load;\n\tunsigned int enable_count;\n\tunsigned int deferred_disables;\n\tstruct regulator_voltage voltage[5];\n\tconst char *supply_name;\n\tstruct device_attribute dev_attr;\n\tstruct regulator_dev *rdev;\n\tstruct dentry *debugfs;\n};\n\nstruct regulator_bulk_data {\n\tconst char *supply;\n\tstruct regulator *consumer;\n\tint init_load_uA;\n\tint ret;\n};\n\nstruct regulator_bulk_devres {\n\tstruct regulator_bulk_data *consumers;\n\tint num_consumers;\n};\n\nstruct regulator_config {\n\tstruct device *dev;\n\tconst struct regulator_init_data *init_data;\n\tvoid *driver_data;\n\tstruct device_node *of_node;\n\tstruct regmap *regmap;\n\tstruct gpio_desc *ena_gpiod;\n};\n\nstruct regulator_consumer_supply {\n\tconst char *dev_name;\n\tconst char *supply;\n};\n\nstruct regulator_coupler {\n\tstruct list_head list;\n\tint (*attach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*detach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*balance_voltage)(struct regulator_coupler *, struct regulator_dev *, suspend_state_t);\n};\n\nstruct regulator_enable_gpio;\n\nstruct regulator_dev {\n\tconst struct regulator_desc *desc;\n\tint exclusive;\n\tu32 use_count;\n\tu32 open_count;\n\tu32 bypass_count;\n\tstruct list_head list;\n\tstruct list_head consumer_list;\n\tstruct coupling_desc coupling_desc;\n\tstruct blocking_notifier_head notifier;\n\tstruct ww_mutex mutex;\n\tstruct task_struct *mutex_owner;\n\tint ref_cnt;\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct device bdev;\n\tstruct regulation_constraints *constraints;\n\tstruct regulator *supply;\n\tconst char *supply_name;\n\tstruct regmap *regmap;\n\tstruct delayed_work disable_work;\n\tvoid *reg_data;\n\tstruct dentry *debugfs;\n\tstruct regulator_enable_gpio *ena_pin;\n\tunsigned int ena_gpio_state: 1;\n\tunsigned int constraints_pending: 1;\n\tunsigned int is_switch: 1;\n\tktime_t last_off;\n\tint cached_err;\n\tbool use_cached_err;\n\tspinlock_t err_lock;\n\tint pw_requested_mW;\n\tstruct notifier_block supply_fwd_nb;\n};\n\nstruct regulator_enable_gpio {\n\tstruct list_head list;\n\tstruct gpio_desc *gpiod;\n\tu32 enable_count;\n\tu32 request_count;\n};\n\nstruct regulator_err_state {\n\tstruct regulator_dev *rdev;\n\tlong unsigned int notifs;\n\tlong unsigned int errors;\n\tint possible_errs;\n};\n\nstruct regulator_event_work {\n\tstruct work_struct work;\n\tstruct regulator_dev *rdev;\n\tlong unsigned int event;\n};\n\nstruct regulator_irq_data {\n\tstruct regulator_err_state *states;\n\tint num_states;\n\tvoid *data;\n\tlong int opaque;\n};\n\nstruct regulator_irq_desc {\n\tconst char *name;\n\tint fatal_cnt;\n\tint reread_ms;\n\tint irq_off_ms;\n\tbool skip_off;\n\tbool high_prio;\n\tvoid *data;\n\tint (*die)(struct regulator_irq_data *);\n\tint (*map_event)(int, struct regulator_irq_data *, long unsigned int *);\n\tint (*renable)(struct regulator_irq_data *);\n};\n\nstruct regulator_irq {\n\tstruct regulator_irq_data rdata;\n\tstruct regulator_irq_desc desc;\n\tint irq;\n\tint retry_cnt;\n\tstruct delayed_work isr_work;\n};\n\nstruct regulator_map {\n\tstruct list_head list;\n\tconst char *dev_name;\n\tconst char *supply;\n\tstruct regulator_dev *regulator;\n};\n\nstruct regulator_notifier_match {\n\tstruct regulator *regulator;\n\tstruct notifier_block *nb;\n};\n\nstruct regulator_ops {\n\tint (*list_voltage)(struct regulator_dev *, unsigned int);\n\tint (*set_voltage)(struct regulator_dev *, int, int, unsigned int *);\n\tint (*map_voltage)(struct regulator_dev *, int, int);\n\tint (*set_voltage_sel)(struct regulator_dev *, unsigned int);\n\tint (*get_voltage)(struct regulator_dev *);\n\tint (*get_voltage_sel)(struct regulator_dev *);\n\tint (*set_current_limit)(struct regulator_dev *, int, int);\n\tint (*get_current_limit)(struct regulator_dev *);\n\tint (*set_input_current_limit)(struct regulator_dev *, int);\n\tint (*set_over_current_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_over_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_under_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_thermal_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_active_discharge)(struct regulator_dev *, bool);\n\tint (*enable)(struct regulator_dev *);\n\tint (*disable)(struct regulator_dev *);\n\tint (*is_enabled)(struct regulator_dev *);\n\tint (*set_mode)(struct regulator_dev *, unsigned int);\n\tunsigned int (*get_mode)(struct regulator_dev *);\n\tint (*get_error_flags)(struct regulator_dev *, unsigned int *);\n\tint (*enable_time)(struct regulator_dev *);\n\tint (*set_ramp_delay)(struct regulator_dev *, int);\n\tint (*set_voltage_time)(struct regulator_dev *, int, int);\n\tint (*set_voltage_time_sel)(struct regulator_dev *, unsigned int, unsigned int);\n\tint (*set_soft_start)(struct regulator_dev *);\n\tint (*get_status)(struct regulator_dev *);\n\tunsigned int (*get_optimum_mode)(struct regulator_dev *, int, int, int);\n\tint (*set_load)(struct regulator_dev *, int);\n\tint (*set_bypass)(struct regulator_dev *, bool);\n\tint (*get_bypass)(struct regulator_dev *, bool *);\n\tint (*set_suspend_voltage)(struct regulator_dev *, int);\n\tint (*set_suspend_enable)(struct regulator_dev *);\n\tint (*set_suspend_disable)(struct regulator_dev *);\n\tint (*set_suspend_mode)(struct regulator_dev *, unsigned int);\n\tint (*resume)(struct regulator_dev *);\n\tint (*set_pull_down)(struct regulator_dev *);\n};\n\nstruct regulator_supply_alias {\n\tstruct list_head list;\n\tstruct device *src_dev;\n\tconst char *src_supply;\n\tstruct device *alias_dev;\n\tconst char *alias_supply;\n};\n\nstruct regulator_supply_alias_match {\n\tstruct device *dev;\n\tconst char *id;\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\nstruct relocation_entry {\n\tstruct list_head head;\n\tElf64_Addr value;\n\tunsigned int type;\n};\n\nstruct relocation_handlers {\n\tint (*reloc_handler)(struct module *, void *, Elf64_Addr);\n\tint (*accumulate_handler)(struct module *, void *, long int);\n};\n\nstruct relocation_head {\n\tstruct hlist_node node;\n\tstruct list_head rel_entry;\n\tvoid *location;\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct repcodes_s {\n\tU32 rep[3];\n};\n\ntypedef struct repcodes_s Repcodes_t;\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct rq_qos;\n\nstruct throtl_data;\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tstruct device *dev;\n\tenum rpm_status rpm_status;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tlong unsigned int blkcg_pols[1];\n\tstruct blkcg_gq *root_blkg;\n\tstruct list_head blkg_list;\n\tstruct mutex blkcg_mutex;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct throtl_data *td;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct res_proc_context {\n\tstruct list_head *list;\n\tint (*preproc)(struct acpi_resource *, void *);\n\tvoid *preproc_data;\n\tint count;\n\tint error;\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\nstruct reserved_mem_ops;\n\nstruct reserved_mem {\n\tconst char *name;\n\tlong unsigned int fdt_node;\n\tconst struct reserved_mem_ops *ops;\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tvoid *priv;\n};\n\nstruct reserved_mem_ops {\n\tint (*device_init)(struct reserved_mem *, struct device *);\n\tvoid (*device_release)(struct reserved_mem *, struct device *);\n};\n\nstruct reset_control {\n\tstruct reset_controller_dev *rcdev;\n\tstruct list_head list;\n\tunsigned int id;\n\tstruct kref refcnt;\n\tbool acquired;\n\tbool shared;\n\tbool array;\n\tatomic_t deassert_count;\n\tatomic_t triggered_count;\n};\n\nstruct reset_control_array {\n\tstruct reset_control base;\n\tunsigned int num_rstcs;\n\tstruct reset_control *rstc[0];\n};\n\nstruct reset_control_bulk_devres {\n\tint num_rstcs;\n\tstruct reset_control_bulk_data *rstcs;\n};\n\nstruct reset_control_ops {\n\tint (*reset)(struct reset_controller_dev *, long unsigned int);\n\tint (*assert)(struct reset_controller_dev *, long unsigned int);\n\tint (*deassert)(struct reset_controller_dev *, long unsigned int);\n\tint (*status)(struct reset_controller_dev *, long unsigned int);\n};\n\nstruct reset_simple_devdata {\n\tu32 reg_offset;\n\tu32 nr_resets;\n\tbool active_low;\n\tbool status_active_low;\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct resource_win {\n\tstruct resource res;\n\tresource_size_t offset;\n};\n\nstruct response_iu {\n\t__u8 iu_id;\n\t__u8 rsvd1;\n\t__be16 tag;\n\t__u8 add_response_info[3];\n\t__u8 response_code;\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct resv_map {\n\tstruct kref refs;\n\tspinlock_t lock;\n\tstruct list_head regions;\n\tlong int adds_in_progress;\n\tstruct list_head region_cache;\n\tlong int region_cache_count;\n\tstruct rw_semaphore rw_sema;\n\tstruct page_counter *reservation_counter;\n\tlong unsigned int pages_per_hpage;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct return_address_data {\n\tunsigned int level;\n\tvoid *addr;\n};\n\nstruct return_consumer {\n\t__u64 cookie;\n\t__u64 id;\n};\n\nstruct return_instance {\n\tstruct hprobe hprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tint cons_cnt;\n\tstruct return_instance *next;\n\tstruct callback_head rcu;\n\tstruct return_consumer consumer;\n\tstruct return_consumer *extra_consumers;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct rimt_fwnode {\n\tstruct list_head list;\n\tstruct acpi_rimt_node *rimt_node;\n\tstruct fwnode_handle *fwnode;\n};\n\nstruct rimt_pci_alias_info {\n\tstruct device *dev;\n\tstruct acpi_rimt_node *node;\n\tconst struct iommu_ops *ops;\n};\n\nstruct ring_buffer_cpu_meta {\n\tlong unsigned int first_buffer;\n\tlong unsigned int head_buffer;\n\tlong unsigned int commit_buffer;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tint buffers[0];\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tlong unsigned int cache_pages_removed;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tsize_t event_size;\n\tint missed_events;\n};\n\nstruct ring_buffer_meta {\n\tint magic;\n\tint struct_sizes;\n\tlong unsigned int total_size;\n\tlong unsigned int buffers_offset;\n};\n\nstruct trace_buffer_meta;\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tlong unsigned int cnt;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_lost;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\trb_time_t write_stamp;\n\trb_time_t before_stamp;\n\tu64 event_stamp[5];\n\tu64 read_stamp;\n\tlong unsigned int pages_removed;\n\tunsigned int mapped;\n\tunsigned int user_mapped;\n\tstruct mutex mapping_lock;\n\tlong unsigned int *subbuf_ids;\n\tstruct trace_buffer_meta *meta_page;\n\tstruct ring_buffer_cpu_meta *ring_meta;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct ring_info {\n\tstruct sk_buff *skb;\n\tu32 len;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rintc_data {\n\tunion {\n\t\tu32 ext_intc_id;\n\t\tstruct {\n\t\t\tu32 context_id: 16;\n\t\t\tu32 reserved: 8;\n\t\t\tu32 aplic_plic_id: 8;\n\t\t};\n\t};\n\tlong unsigned int hart_id;\n\tu64 imsic_addr;\n\tu32 imsic_size;\n};\n\nstruct riscv_cacheinfo_ops {\n\tconst struct attribute_group * (*get_priv_group)(struct cacheinfo *);\n};\n\nstruct riscv_cpuinfo {\n\tlong unsigned int mvendorid;\n\tlong unsigned int marchid;\n\tlong unsigned int mimpid;\n};\n\nstruct riscv_efi_boot_protocol {\n\tu64 revision;\n\tefi_status_t (*get_boot_hartid)(struct riscv_efi_boot_protocol *, long unsigned int *);\n};\n\nstruct riscv_ext_intc_list {\n\tacpi_handle handle;\n\tu32 gsi_base;\n\tu32 nr_irqs;\n\tu32 nr_idcs;\n\tu32 id;\n\tu32 type;\n\tu32 flag;\n\tstruct list_head list;\n};\n\nstruct riscv_hwprobe {\n\t__s64 key;\n\t__u64 value;\n};\n\nstruct riscv_iommu_bond {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n};\n\nstruct riscv_iommu_command {\n\tu64 dword0;\n\tu64 dword1;\n};\n\nstruct riscv_iommu_dc {\n\tu64 tc;\n\tu64 iohgatp;\n\tu64 ta;\n\tu64 fsc;\n\tu64 msiptp;\n\tu64 msi_addr_mask;\n\tu64 msi_addr_pattern;\n\tu64 _reserved;\n};\n\nstruct riscv_iommu_device;\n\nstruct riscv_iommu_queue {\n\tatomic_t prod;\n\tatomic_t head;\n\tatomic_t tail;\n\tunsigned int mask;\n\tunsigned int irq;\n\tstruct riscv_iommu_device *iommu;\n\tvoid *base;\n\tdma_addr_t phys;\n\tu16 qbr;\n\tu16 qcr;\n\tu8 qid;\n};\n\nstruct riscv_iommu_device {\n\tstruct iommu_device iommu;\n\tstruct device *dev;\n\tvoid *reg;\n\tu64 caps;\n\tu32 fctl;\n\tunsigned int irqs[4];\n\tunsigned int irqs_count;\n\tunsigned int icvec;\n\tstruct riscv_iommu_queue cmdq;\n\tstruct riscv_iommu_queue fltq;\n\tunsigned int ddt_mode;\n\tdma_addr_t ddt_phys;\n\tu64 *ddt_root;\n};\n\nstruct riscv_iommu_devres {\n\tvoid *addr;\n};\n\nstruct riscv_iommu_domain {\n\tstruct iommu_domain domain;\n\tstruct list_head bonds;\n\tspinlock_t lock;\n\tint pscid;\n\tbool amo_enabled;\n\tint numa_node;\n\tunsigned int pgd_mode;\n\tlong unsigned int *pgd_root;\n};\n\nstruct riscv_iommu_fq_record {\n\tu64 hdr;\n\tu64 _reserved;\n\tu64 iotval;\n\tu64 iotval2;\n};\n\nstruct riscv_iommu_info {\n\tstruct riscv_iommu_domain *domain;\n};\n\nstruct riscv_isa_ext_data {\n\tconst unsigned int id;\n\tconst char *name;\n\tconst char *property;\n\tconst unsigned int *subset_ext_ids;\n\tconst unsigned int subset_ext_size;\n\tint (*validate)(const struct riscv_isa_ext_data *, const long unsigned int *);\n};\n\nstruct riscv_isavendorinfo {\n\tlong unsigned int isa[1];\n};\n\nstruct riscv_isa_vendor_ext_data_list {\n\tbool is_initialized;\n\tconst size_t ext_data_count;\n\tconst struct riscv_isa_ext_data *ext_data;\n\tstruct riscv_isavendorinfo per_hart_isa_bitmap[64];\n\tstruct riscv_isavendorinfo all_harts_isa_bitmap;\n};\n\nstruct riscv_isainfo {\n\tlong unsigned int isa[2];\n};\n\nstruct riscv_nonstd_cache_ops {\n\tvoid (*wback)(phys_addr_t, size_t);\n\tvoid (*inv)(phys_addr_t, size_t);\n\tvoid (*wback_inv)(phys_addr_t, size_t);\n};\n\nstruct riscv_pmu {\n\tstruct pmu pmu;\n\tchar *name;\n\tirqreturn_t (*handle_irq)(int, void *);\n\tlong unsigned int cmask;\n\tu64 (*ctr_read)(struct perf_event *);\n\tint (*ctr_get_idx)(struct perf_event *);\n\tint (*ctr_get_width)(int);\n\tvoid (*ctr_clear_idx)(struct perf_event *);\n\tvoid (*ctr_start)(struct perf_event *, u64);\n\tvoid (*ctr_stop)(struct perf_event *, long unsigned int);\n\tint (*event_map)(struct perf_event *, u64 *);\n\tvoid (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tuint8_t (*csr_index)(struct perf_event *);\n\tstruct cpu_hw_events *hw_events;\n\tstruct hlist_node node;\n\tstruct notifier_block riscv_pm_nb;\n};\n\nstruct riscv_pmu_event_info {\n\tu32 event_idx;\n\tu32 output;\n\tu64 event_data;\n};\n\nstruct riscv_pmu_snapshot_data {\n\tu64 ctr_overflow_mask;\n\tu64 ctr_values[64];\n\tu64 reserved[447];\n};\n\nstruct rk35xx_priv {\n\tstruct reset_control *reset;\n\tenum dwcmshc_rk_type devtype;\n\tu8 txclk_tapnum;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rmem_assigned_device {\n\tstruct device *dev;\n\tstruct reserved_mem *rmem;\n\tstruct list_head list;\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_gpio_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_gpio_data gpio_data;\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct rock_ridge {\n\t__u8 signature[2];\n\t__u8 len;\n\t__u8 version;\n\tunion {\n\t\tstruct SU_SP_s SP;\n\t\tstruct SU_CE_s CE;\n\t\tstruct SU_ER_s ER;\n\t\tstruct RR_RR_s RR;\n\t\tstruct RR_PX_s PX;\n\t\tstruct RR_PN_s PN;\n\t\tstruct RR_SL_s SL;\n\t\tstruct RR_NM_s NM;\n\t\tstruct RR_CL_s CL;\n\t\tstruct RR_PL_s PL;\n\t\tstruct RR_TF_s TF;\n\t\tstruct RR_ZF_s ZF;\n\t} u;\n};\n\nstruct rock_state {\n\tvoid *buffer;\n\tunsigned char *chr;\n\tint len;\n\tint cont_size;\n\tint cont_extent;\n\tint cont_offset;\n\tint cont_loops;\n\tstruct inode *inode;\n};\n\nstruct role_allow {\n\tu32 role;\n\tu32 new_role;\n\tstruct role_allow *next;\n};\n\nstruct role_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap dominates;\n\tstruct ebitmap types;\n};\n\nstruct role_trans_datum {\n\tu32 new_role;\n};\n\nstruct role_trans_key {\n\tu32 role;\n\tu32 type;\n\tu32 tclass;\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct rpc_add_xprt_test {\n\tvoid (*add_xprt_test)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tvoid *data;\n};\n\nstruct rpc_authops;\n\nstruct rpc_cred_cache;\n\nstruct rpc_auth {\n\tunsigned int au_cslack;\n\tunsigned int au_rslack;\n\tunsigned int au_verfsize;\n\tunsigned int au_ralign;\n\tlong unsigned int au_flags;\n\tconst struct rpc_authops *au_ops;\n\trpc_authflavor_t au_flavor;\n\trefcount_t au_count;\n\tstruct rpc_cred_cache *au_credcache;\n};\n\nstruct rpc_auth_create_args {\n\trpc_authflavor_t pseudoflavor;\n\tconst char *target_name;\n};\n\nstruct rpc_authops {\n\tstruct module *owner;\n\trpc_authflavor_t au_flavor;\n\tchar *au_name;\n\tstruct rpc_auth * (*create)(const struct rpc_auth_create_args *, struct rpc_clnt *);\n\tvoid (*destroy)(struct rpc_auth *);\n\tint (*hash_cred)(struct auth_cred *, unsigned int);\n\tstruct rpc_cred * (*lookup_cred)(struct rpc_auth *, struct auth_cred *, int);\n\tstruct rpc_cred * (*crcreate)(struct rpc_auth *, struct auth_cred *, int, gfp_t);\n\trpc_authflavor_t (*info2flavor)(struct rpcsec_gss_info *);\n\tint (*flavor2info)(rpc_authflavor_t, struct rpcsec_gss_info *);\n\tint (*key_timeout)(struct rpc_auth *, struct rpc_cred *);\n\tint (*ping)(struct rpc_clnt *);\n};\n\nstruct rpc_bind_conn_calldata {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct rpc_buffer {\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct rpc_call_ops {\n\tvoid (*rpc_call_prepare)(struct rpc_task *, void *);\n\tvoid (*rpc_call_done)(struct rpc_task *, void *);\n\tvoid (*rpc_count_stats)(struct rpc_task *, void *);\n\tvoid (*rpc_release)(void *);\n};\n\nstruct rpc_xprt_switch;\n\nstruct rpc_cb_add_xprt_calldata {\n\tstruct rpc_xprt_switch *xps;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_pipe_dir_head {\n\tstruct list_head pdh_entries;\n\tstruct dentry *pdh_dentry;\n};\n\nstruct rpc_rtt {\n\tlong unsigned int timeo;\n\tlong unsigned int srtt[5];\n\tlong unsigned int sdrtt[5];\n\tint ntimeouts[5];\n};\n\nstruct rpc_timeout {\n\tlong unsigned int to_initval;\n\tlong unsigned int to_maxval;\n\tlong unsigned int to_increment;\n\tunsigned int to_retries;\n\tunsigned char to_exponential;\n};\n\nstruct rpc_xprt_iter_ops;\n\nstruct rpc_xprt_iter {\n\tstruct rpc_xprt_switch *xpi_xpswitch;\n\tstruct rpc_xprt *xpi_cursor;\n\tconst struct rpc_xprt_iter_ops *xpi_ops;\n};\n\nstruct rpc_iostats;\n\nstruct rpc_sysfs_client;\n\nstruct rpc_clnt {\n\trefcount_t cl_count;\n\tunsigned int cl_clid;\n\tstruct list_head cl_clients;\n\tstruct list_head cl_tasks;\n\tatomic_t cl_pid;\n\tspinlock_t cl_lock;\n\tstruct rpc_xprt *cl_xprt;\n\tconst struct rpc_procinfo *cl_procinfo;\n\tu32 cl_prog;\n\tu32 cl_vers;\n\tu32 cl_maxproc;\n\tstruct rpc_auth *cl_auth;\n\tstruct rpc_stat *cl_stats;\n\tstruct rpc_iostats *cl_metrics;\n\tunsigned int cl_softrtry: 1;\n\tunsigned int cl_softerr: 1;\n\tunsigned int cl_discrtry: 1;\n\tunsigned int cl_noretranstimeo: 1;\n\tunsigned int cl_autobind: 1;\n\tunsigned int cl_chatty: 1;\n\tunsigned int cl_shutdown: 1;\n\tunsigned int cl_netunreach_fatal: 1;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct rpc_rtt *cl_rtt;\n\tconst struct rpc_timeout *cl_timeout;\n\tatomic_t cl_swapper;\n\tint cl_nodelen;\n\tchar cl_nodename[65];\n\tstruct rpc_pipe_dir_head cl_pipedir_objects;\n\tstruct rpc_clnt *cl_parent;\n\tstruct rpc_rtt cl_rtt_default;\n\tstruct rpc_timeout cl_timeout_default;\n\tconst struct rpc_program *cl_program;\n\tconst char *cl_principal;\n\tstruct rpc_sysfs_client *cl_sysfs;\n\tunion {\n\t\tstruct rpc_xprt_iter cl_xpi;\n\t\tstruct work_struct cl_work;\n\t};\n\tconst struct cred *cl_cred;\n\tunsigned int cl_max_connect;\n\tstruct super_block *pipefs_sb;\n\tatomic_t cl_task_count;\n};\n\nstruct svc_xprt;\n\nstruct rpc_create_args {\n\tstruct net *net;\n\tint protocol;\n\tstruct sockaddr *address;\n\tsize_t addrsize;\n\tstruct sockaddr *saddress;\n\tconst struct rpc_timeout *timeout;\n\tconst char *servername;\n\tconst char *nodename;\n\tconst struct rpc_program *program;\n\tstruct rpc_stat *stats;\n\tu32 prognumber;\n\tu32 version;\n\trpc_authflavor_t authflavor;\n\tu32 nconnect;\n\tlong unsigned int flags;\n\tchar *client_name;\n\tstruct svc_xprt *bc_xprt;\n\tconst struct cred *cred;\n\tunsigned int max_connect;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct rpc_credops;\n\nstruct rpc_cred {\n\tstruct hlist_node cr_hash;\n\tstruct list_head cr_lru;\n\tstruct callback_head cr_rcu;\n\tstruct rpc_auth *cr_auth;\n\tconst struct rpc_credops *cr_ops;\n\tlong unsigned int cr_expire;\n\tlong unsigned int cr_flags;\n\trefcount_t cr_count;\n\tconst struct cred *cr_cred;\n};\n\nstruct rpc_cred_cache {\n\tstruct hlist_head *hashtable;\n\tunsigned int hashbits;\n\tspinlock_t lock;\n};\n\nstruct rpc_credops {\n\tconst char *cr_name;\n\tint (*cr_init)(struct rpc_auth *, struct rpc_cred *);\n\tvoid (*crdestroy)(struct rpc_cred *);\n\tint (*crmatch)(struct auth_cred *, struct rpc_cred *, int);\n\tint (*crmarshal)(struct rpc_task *, struct xdr_stream *);\n\tint (*crrefresh)(struct rpc_task *);\n\tint (*crvalidate)(struct rpc_task *, struct xdr_stream *);\n\tint (*crwrap_req)(struct rpc_task *, struct xdr_stream *);\n\tint (*crunwrap_resp)(struct rpc_task *, struct xdr_stream *);\n\tint (*crkey_timeout)(struct rpc_cred *);\n\tchar * (*crstringify_acceptor)(struct rpc_cred *);\n\tbool (*crneed_reencode)(struct rpc_task *);\n};\n\nstruct rpc_filelist {\n\tconst char *name;\n\tconst struct file_operations *i_fop;\n\tumode_t mode;\n};\n\nstruct rpc_inode {\n\tstruct inode vfs_inode;\n\tvoid *private;\n\tstruct rpc_pipe *pipe;\n\twait_queue_head_t waitq;\n};\n\nstruct rpc_iostats {\n\tspinlock_t om_lock;\n\tlong unsigned int om_ops;\n\tlong unsigned int om_ntrans;\n\tlong unsigned int om_timeouts;\n\tlong long unsigned int om_bytes_sent;\n\tlong long unsigned int om_bytes_recv;\n\tktime_t om_queue;\n\tktime_t om_rtt;\n\tktime_t om_execute;\n\tlong unsigned int om_error_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rpc_pipe_ops;\n\nstruct rpc_pipe {\n\tstruct list_head pipe;\n\tstruct list_head in_upcall;\n\tstruct list_head in_downcall;\n\tint pipelen;\n\tint nreaders;\n\tint nwriters;\n\tint flags;\n\tstruct delayed_work queue_timeout;\n\tconst struct rpc_pipe_ops *ops;\n\tspinlock_t lock;\n\tstruct dentry *dentry;\n};\n\nstruct rpc_pipe_dir_object_ops {\n\tint (*create)(struct dentry *, struct rpc_pipe_dir_object *);\n\tvoid (*destroy)(struct dentry *, struct rpc_pipe_dir_object *);\n};\n\nstruct rpc_pipe_ops {\n\tssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char *, size_t);\n\tssize_t (*downcall)(struct file *, const char *, size_t);\n\tvoid (*release_pipe)(struct inode *);\n\tint (*open_pipe)(struct inode *);\n\tvoid (*destroy_msg)(struct rpc_pipe_msg *);\n};\n\ntypedef void (*kxdreproc_t)(struct rpc_rqst *, struct xdr_stream *, const void *);\n\ntypedef int (*kxdrdproc_t)(struct rpc_rqst *, struct xdr_stream *, void *);\n\nstruct rpc_procinfo {\n\tu32 p_proc;\n\tkxdreproc_t p_encode;\n\tkxdrdproc_t p_decode;\n\tunsigned int p_arglen;\n\tunsigned int p_replen;\n\tunsigned int p_timer;\n\tu32 p_statidx;\n\tconst char *p_name;\n};\n\nstruct rpc_program {\n\tconst char *name;\n\tu32 number;\n\tunsigned int nrvers;\n\tconst struct rpc_version **version;\n\tstruct rpc_stat *stats;\n\tconst char *pipe_dir_name;\n};\n\nstruct xdr_buf {\n\tstruct kvec head[1];\n\tstruct kvec tail[1];\n\tstruct bio_vec *bvec;\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int flags;\n\tunsigned int buflen;\n\tunsigned int len;\n};\n\nstruct rpc_rqst {\n\tstruct rpc_xprt *rq_xprt;\n\tstruct xdr_buf rq_snd_buf;\n\tstruct xdr_buf rq_rcv_buf;\n\tstruct rpc_task *rq_task;\n\tstruct rpc_cred *rq_cred;\n\t__be32 rq_xid;\n\tint rq_cong;\n\tu32 rq_seqnos[3];\n\tunsigned int rq_seqno_count;\n\tint rq_enc_pages_num;\n\tstruct page **rq_enc_pages;\n\tvoid (*rq_release_snd_buf)(struct rpc_rqst *);\n\tunion {\n\t\tstruct list_head rq_list;\n\t\tstruct rb_node rq_recv;\n\t};\n\tstruct list_head rq_xmit;\n\tstruct list_head rq_xmit2;\n\tvoid *rq_buffer;\n\tsize_t rq_callsize;\n\tvoid *rq_rbuffer;\n\tsize_t rq_rcvsize;\n\tsize_t rq_xmit_bytes_sent;\n\tsize_t rq_reply_bytes_recvd;\n\tstruct xdr_buf rq_private_buf;\n\tlong unsigned int rq_majortimeo;\n\tlong unsigned int rq_minortimeo;\n\tlong unsigned int rq_timeout;\n\tktime_t rq_rtt;\n\tunsigned int rq_retries;\n\tunsigned int rq_connect_cookie;\n\tatomic_t rq_pin;\n\tu32 rq_bytes_sent;\n\tktime_t rq_xtime;\n\tint rq_ntrans;\n\tstruct lwq_node rq_bc_list;\n\tlong unsigned int rq_bc_pa_state;\n\tstruct list_head rq_bc_pa_list;\n};\n\nstruct rpc_sysfs_client {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_clnt *clnt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt {\n\tstruct kobject kobject;\n\tstruct rpc_xprt *xprt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt_switch {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_xprt_switch *xprt_switch;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_task_setup {\n\tstruct rpc_task *task;\n\tstruct rpc_clnt *rpc_client;\n\tstruct rpc_xprt *rpc_xprt;\n\tstruct rpc_cred *rpc_op_cred;\n\tconst struct rpc_message *rpc_message;\n\tconst struct rpc_call_ops *callback_ops;\n\tvoid *callback_data;\n\tstruct workqueue_struct *workqueue;\n\tshort unsigned int flags;\n\tsigned char priority;\n};\n\nstruct rpc_version {\n\tu32 number;\n\tunsigned int nrprocs;\n\tconst struct rpc_procinfo *procs;\n\tunsigned int *counts;\n};\n\nstruct rpc_xprt_ops;\n\nstruct xprt_class;\n\nstruct rpc_xprt {\n\tstruct kref kref;\n\tconst struct rpc_xprt_ops *ops;\n\tunsigned int id;\n\tconst struct rpc_timeout *timeout;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tint prot;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tsize_t max_payload;\n\tstruct rpc_wait_queue binding;\n\tstruct rpc_wait_queue sending;\n\tstruct rpc_wait_queue pending;\n\tstruct rpc_wait_queue backlog;\n\tstruct list_head free;\n\tunsigned int max_reqs;\n\tunsigned int min_reqs;\n\tunsigned int num_reqs;\n\tlong unsigned int state;\n\tunsigned char resvport: 1;\n\tunsigned char reuseport: 1;\n\tatomic_t swapper;\n\tunsigned int bind_index;\n\tstruct list_head xprt_switch;\n\tlong unsigned int bind_timeout;\n\tlong unsigned int reestablish_timeout;\n\tstruct xprtsec_parms xprtsec;\n\tunsigned int connect_cookie;\n\tstruct work_struct task_cleanup;\n\tstruct timer_list timer;\n\tlong unsigned int last_used;\n\tlong unsigned int idle_timeout;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int max_reconnect_timeout;\n\tatomic_long_t queuelen;\n\tspinlock_t transport_lock;\n\tspinlock_t reserve_lock;\n\tspinlock_t queue_lock;\n\tu32 xid;\n\tstruct rpc_task *snd_task;\n\tstruct list_head xmit_queue;\n\tatomic_long_t xmit_queuelen;\n\tstruct svc_xprt *bc_xprt;\n\tstruct svc_serv *bc_serv;\n\tunsigned int bc_alloc_max;\n\tunsigned int bc_alloc_count;\n\tatomic_t bc_slot_count;\n\tspinlock_t bc_pa_lock;\n\tstruct list_head bc_pa_list;\n\tstruct rb_root recv_queue;\n\tstruct {\n\t\tlong unsigned int bind_count;\n\t\tlong unsigned int connect_count;\n\t\tlong unsigned int connect_start;\n\t\tlong unsigned int connect_time;\n\t\tlong unsigned int sends;\n\t\tlong unsigned int recvs;\n\t\tlong unsigned int bad_xids;\n\t\tlong unsigned int max_slots;\n\t\tlong long unsigned int req_u;\n\t\tlong long unsigned int bklog_u;\n\t\tlong long unsigned int sending_u;\n\t\tlong long unsigned int pending_u;\n\t} stat;\n\tstruct net *xprt_net;\n\tnetns_tracker ns_tracker;\n\tconst char *servername;\n\tconst char *address_strings[6];\n\tstruct callback_head rcu;\n\tconst struct xprt_class *xprt_class;\n\tstruct rpc_sysfs_xprt *xprt_sysfs;\n\tbool main;\n};\n\nstruct rpc_xprt_iter_ops {\n\tvoid (*xpi_rewind)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_xprt)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_next)(struct rpc_xprt_iter *);\n};\n\nstruct rpc_xprt_ops {\n\tvoid (*set_buffer_size)(struct rpc_xprt *, size_t, size_t);\n\tint (*reserve_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*alloc_slot)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*free_slot)(struct rpc_xprt *, struct rpc_rqst *);\n\tvoid (*rpcbind)(struct rpc_task *);\n\tvoid (*set_port)(struct rpc_xprt *, short unsigned int);\n\tvoid (*connect)(struct rpc_xprt *, struct rpc_task *);\n\tint (*get_srcaddr)(struct rpc_xprt *, char *, size_t);\n\tshort unsigned int (*get_srcport)(struct rpc_xprt *);\n\tint (*buf_alloc)(struct rpc_task *);\n\tvoid (*buf_free)(struct rpc_task *);\n\tint (*prepare_request)(struct rpc_rqst *, struct xdr_buf *);\n\tint (*send_request)(struct rpc_rqst *);\n\tvoid (*abort_send_request)(struct rpc_rqst *);\n\tvoid (*wait_for_reply_request)(struct rpc_task *);\n\tvoid (*timer)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_request)(struct rpc_task *);\n\tvoid (*close)(struct rpc_xprt *);\n\tvoid (*destroy)(struct rpc_xprt *);\n\tvoid (*set_connect_timeout)(struct rpc_xprt *, long unsigned int, long unsigned int);\n\tvoid (*print_stats)(struct rpc_xprt *, struct seq_file *);\n\tint (*enable_swap)(struct rpc_xprt *);\n\tvoid (*disable_swap)(struct rpc_xprt *);\n\tvoid (*inject_disconnect)(struct rpc_xprt *);\n\tint (*bc_setup)(struct rpc_xprt *, unsigned int);\n\tsize_t (*bc_maxpayload)(struct rpc_xprt *);\n\tunsigned int (*bc_num_slots)(struct rpc_xprt *);\n\tvoid (*bc_free_rqst)(struct rpc_rqst *);\n\tvoid (*bc_destroy)(struct rpc_xprt *, unsigned int);\n};\n\nstruct rpc_xprt_switch {\n\tspinlock_t xps_lock;\n\tstruct kref xps_kref;\n\tunsigned int xps_id;\n\tunsigned int xps_nxprts;\n\tunsigned int xps_nactive;\n\tunsigned int xps_nunique_destaddr_xprts;\n\tatomic_long_t xps_queuelen;\n\tstruct list_head xps_xprt_list;\n\tstruct net *xps_net;\n\tconst struct rpc_xprt_iter_ops *xps_iter_ops;\n\tstruct rpc_sysfs_xprt_switch *xps_sysfs;\n\tstruct callback_head xps_rcu;\n};\n\nstruct rpcb_info {\n\tu32 rpc_vers;\n\tconst struct rpc_procinfo *rpc_proc;\n};\n\nstruct rpcbind_args {\n\tstruct rpc_xprt *r_xprt;\n\tu32 r_prog;\n\tu32 r_vers;\n\tu32 r_prot;\n\tshort unsigned int r_port;\n\tconst char *r_netid;\n\tconst char *r_addr;\n\tconst char *r_owner;\n\tint r_status;\n};\n\nstruct rpmb_descr {\n\tenum rpmb_type type;\n\tint (*route_frames)(struct device *, u8 *, unsigned int, u8 *, unsigned int);\n\tu8 *dev_id;\n\tsize_t dev_id_len;\n\tu16 reliable_wr_count;\n\tu16 capacity;\n};\n\nstruct rpmb_dev {\n\tstruct device dev;\n\tint id;\n\tstruct list_head list_node;\n\tstruct rpmb_descr descr;\n};\n\nstruct rpmb_frame {\n\tu8 stuff[196];\n\tu8 key_mac[32];\n\tu8 data[256];\n\tu8 nonce[16];\n\t__be32 write_counter;\n\t__be16 addr;\n\t__be16 block_count;\n\t__be16 result;\n\t__be16 req_resp;\n};\n\nstruct rpmi_clk_context;\n\nunion rpmi_clk_rates;\n\nstruct rpmi_clk {\n\tstruct rpmi_clk_context *context;\n\tu32 id;\n\tu32 num_rates;\n\tu32 transition_latency;\n\tenum rpmi_clk_type type;\n\tunion rpmi_clk_rates *rates;\n\tchar name[16];\n\tstruct clk_hw hw;\n};\n\nstruct rpmi_clk_context {\n\tstruct device *dev;\n\tstruct mbox_chan *chan;\n\tstruct mbox_client client;\n\tu32 max_msg_data_size;\n};\n\nstruct rpmi_clk_rate_discrete {\n\t__le32 lo;\n\t__le32 hi;\n};\n\nstruct rpmi_clk_rate_linear {\n\t__le32 min_lo;\n\t__le32 min_hi;\n\t__le32 max_lo;\n\t__le32 max_hi;\n\t__le32 step_lo;\n\t__le32 step_hi;\n};\n\nunion rpmi_clk_rates {\n\tu64 discrete[16];\n\tstruct {\n\t\tu64 min;\n\t\tu64 max;\n\t\tu64 step;\n\t} linear;\n};\n\nstruct rpmi_get_attrs_rx {\n\t__le32 status;\n\t__le32 flags;\n\t__le32 num_rates;\n\t__le32 transition_latency;\n\tchar name[16];\n};\n\nstruct rpmi_get_attrs_tx {\n\t__le32 clkid;\n};\n\nstruct rpmi_get_num_clocks_rx {\n\t__le32 status;\n\t__le32 num_clocks;\n};\n\nstruct rpmi_get_rate_rx {\n\t__le32 status;\n\t__le32 lo;\n\t__le32 hi;\n};\n\nstruct rpmi_get_rate_tx {\n\t__le32 clkid;\n};\n\nstruct rpmi_get_supp_rates_rx {\n\t__le32 status;\n\t__le32 flags;\n\t__le32 remaining;\n\t__le32 returned;\n\t__le32 rates[0];\n};\n\nstruct rpmi_get_supp_rates_tx {\n\t__le32 clkid;\n\t__le32 clk_rate_idx;\n};\n\nstruct rpmi_mbox_message {\n\tenum rpmi_mbox_message_type type;\n\tunion {\n\t\tstruct {\n\t\t\tenum rpmi_mbox_attribute_id id;\n\t\t\tu32 value;\n\t\t} attr;\n\t\tstruct {\n\t\t\tu32 service_id;\n\t\t\tvoid *request;\n\t\t\tlong unsigned int request_len;\n\t\t\tvoid *response;\n\t\t\tlong unsigned int max_response_len;\n\t\t\tlong unsigned int out_response_len;\n\t\t} data;\n\t\tstruct {\n\t\t\tu16 event_datalen;\n\t\t\tu8 event_id;\n\t\t\tu8 *event_data;\n\t\t} notif;\n\t};\n\tint error;\n};\n\nstruct rpmi_notification_event {\n\t__le16 event_datalen;\n\tu8 event_id;\n\tu8 reserved;\n\tu8 event_data[0];\n};\n\nstruct rpmi_set_config_rx {\n\t__le32 status;\n};\n\nstruct rpmi_set_config_tx {\n\t__le32 clkid;\n\t__le32 config;\n};\n\nstruct rpmi_set_rate_rx {\n\t__le32 status;\n};\n\nstruct rpmi_set_rate_tx {\n\t__le32 clkid;\n\t__le32 flags;\n\t__le32 lo;\n\t__le32 hi;\n};\n\nstruct rpmi_sysmsi_get_attrs_rx {\n\t__le32 status;\n\t__le32 sys_num_msi;\n\t__le32 flag0;\n\t__le32 flag1;\n};\n\nstruct rpmi_sysmsi_priv {\n\tstruct device *dev;\n\tstruct mbox_client client;\n\tstruct mbox_chan *chan;\n\tu32 nr_irqs;\n\tu32 gsi_base;\n};\n\nstruct rpmi_sysmsi_set_msi_state_rx {\n\t__le32 status;\n};\n\nstruct rpmi_sysmsi_set_msi_state_tx {\n\t__le32 sys_msi_index;\n\t__le32 sys_msi_state;\n};\n\nstruct rpmi_sysmsi_set_msi_target_rx {\n\t__le32 status;\n};\n\nstruct rpmi_sysmsi_set_msi_target_tx {\n\t__le32 sys_msi_index;\n\t__le32 sys_msi_address_low;\n\t__le32 sys_msi_address_high;\n\t__le32 sys_msi_data;\n};\n\nstruct rpmsg_channel_info {\n\tchar name[32];\n\tu32 src;\n\tu32 dst;\n};\n\nstruct rpmsg_device;\n\nstruct rpmsg_ctrldev {\n\tstruct rpmsg_device *rpdev;\n\tstruct cdev cdev;\n\tstruct device dev;\n\tstruct mutex ctrl_lock;\n};\n\nstruct rpmsg_device_id {\n\tchar name[32];\n\tkernel_ulong_t driver_data;\n};\n\nstruct rpmsg_endpoint;\n\nstruct rpmsg_device_ops;\n\nstruct rpmsg_device {\n\tstruct device dev;\n\tstruct rpmsg_device_id id;\n\tconst char *driver_override;\n\tu32 src;\n\tu32 dst;\n\tstruct rpmsg_endpoint *ept;\n\tbool announce;\n\tbool little_endian;\n\tconst struct rpmsg_device_ops *ops;\n};\n\ntypedef int (*rpmsg_rx_cb_t)(struct rpmsg_device *, void *, int, void *, u32);\n\nstruct rpmsg_device_ops {\n\tstruct rpmsg_device * (*create_channel)(struct rpmsg_device *, struct rpmsg_channel_info *);\n\tint (*release_channel)(struct rpmsg_device *, struct rpmsg_channel_info *);\n\tstruct rpmsg_endpoint * (*create_ept)(struct rpmsg_device *, rpmsg_rx_cb_t, void *, struct rpmsg_channel_info);\n\tint (*announce_create)(struct rpmsg_device *);\n\tint (*announce_destroy)(struct rpmsg_device *);\n};\n\nstruct rpmsg_driver {\n\tstruct device_driver drv;\n\tconst struct rpmsg_device_id *id_table;\n\tint (*probe)(struct rpmsg_device *);\n\tvoid (*remove)(struct rpmsg_device *);\n\tint (*callback)(struct rpmsg_device *, void *, int, void *, u32);\n\tint (*flowcontrol)(struct rpmsg_device *, void *, bool);\n};\n\ntypedef int (*rpmsg_flowcontrol_cb_t)(struct rpmsg_device *, void *, bool);\n\nstruct rpmsg_endpoint_ops;\n\nstruct rpmsg_endpoint {\n\tstruct rpmsg_device *rpdev;\n\tstruct kref refcount;\n\trpmsg_rx_cb_t cb;\n\trpmsg_flowcontrol_cb_t flow_cb;\n\tstruct mutex cb_lock;\n\tu32 addr;\n\tvoid *priv;\n\tconst struct rpmsg_endpoint_ops *ops;\n};\n\nstruct rpmsg_endpoint_info {\n\tchar name[32];\n\t__u32 src;\n\t__u32 dst;\n};\n\nstruct rpmsg_endpoint_ops {\n\tvoid (*destroy_ept)(struct rpmsg_endpoint *);\n\tint (*send)(struct rpmsg_endpoint *, void *, int);\n\tint (*sendto)(struct rpmsg_endpoint *, void *, int, u32);\n\tint (*trysend)(struct rpmsg_endpoint *, void *, int);\n\tint (*trysendto)(struct rpmsg_endpoint *, void *, int, u32);\n\t__poll_t (*poll)(struct rpmsg_endpoint *, struct file *, poll_table *);\n\tint (*set_flow_control)(struct rpmsg_endpoint *, bool, u32);\n\tssize_t (*get_mtu)(struct rpmsg_endpoint *);\n};\n\nstruct rpmsg_eptdev {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct rpmsg_device *rpdev;\n\tstruct rpmsg_channel_info chinfo;\n\tstruct mutex ept_lock;\n\tstruct rpmsg_endpoint *ept;\n\tstruct rpmsg_endpoint *default_ept;\n\tspinlock_t queue_lock;\n\tstruct sk_buff_head queue;\n\twait_queue_head_t readq;\n\tbool remote_flow_restricted;\n\tbool remote_flow_updated;\n};\n\nstruct rpmsg_hdr {\n\t__rpmsg32 src;\n\t__rpmsg32 dst;\n\t__rpmsg32 reserved;\n\t__rpmsg16 len;\n\t__rpmsg16 flags;\n\tu8 data[0];\n};\n\nstruct rpmsg_ns_msg {\n\tchar name[32];\n\t__rpmsg32 addr;\n\t__rpmsg32 flags;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[2];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tcall_single_data_t nohz_csd;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tunsigned int numa_migrate_on;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 64;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tktime_t hrtick_time;\n\tstruct cpuidle_state *idle_state;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tcpumask_var_t scratch_mask;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t cfsb_csd;\n\tstruct list_head cfsb_csd_list;\n\tatomic_t nr_iowait;\n\tlong: 64;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\nstruct rq_wait;\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n};\n\nstruct rs_msg {\n\tstruct icmp6hdr icmph;\n\t__u8 opt[0];\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rsvd_count {\n\tint ndelayed;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct rt0_hdr {\n\tstruct ipv6_rt_hdr rt_hdr;\n\t__u32 reserved;\n\tstruct in6_addr addr[0];\n};\n\nstruct rt6_exception {\n\tstruct hlist_node hlist;\n\tstruct rt6_info *rt6i;\n\tlong unsigned int stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_mtu_change_arg {\n\tstruct net_device *dev;\n\tunsigned int mtu;\n\tstruct fib6_info *f6i;\n};\n\nstruct rt6_nh {\n\tstruct fib6_info *fib6_info;\n\tstruct fib6_config r_cfg;\n\tstruct list_head list;\n};\n\nstruct rt6_rtnl_dump_arg {\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct net *net;\n\tstruct fib_dump_filter filter;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\t__kernel_size_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct sigcontext {\n\tstruct user_regs_struct sc_regs;\n\tunion {\n\t\tunion __riscv_fp_state sc_fpregs;\n\t\tstruct __riscv_extra_ext_header sc_extdesc;\n\t};\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tsigset_t uc_sigmask;\n\t__u8 __unused[120];\n\tlong: 64;\n\tstruct sigcontext uc_mcontext;\n};\n\nstruct rt_sigframe {\n\tstruct siginfo info;\n\tstruct ucontext uc;\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rtc_time;\n\nstruct rtc_wkalrm;\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtl8169_counters {\n\t__le64 tx_packets;\n\t__le64 rx_packets;\n\t__le64 tx_errors;\n\t__le32 rx_errors;\n\t__le16 rx_missed;\n\t__le16 align_errors;\n\t__le32 tx_one_collision;\n\t__le32 tx_multi_collision;\n\t__le64 rx_unicast;\n\t__le64 rx_broadcast;\n\t__le32 rx_multicast;\n\t__le16 tx_aborted;\n\t__le16 tx_underrun;\n\t__le64 tx_octets;\n\t__le64 rx_octets;\n\t__le64 rx_multicast64;\n\t__le64 tx_unicast64;\n\t__le64 tx_broadcast64;\n\t__le64 tx_multicast64;\n\t__le32 tx_pause_on;\n\t__le32 tx_pause_off;\n\t__le32 tx_pause_all;\n\t__le32 tx_deferred;\n\t__le32 tx_late_collision;\n\t__le32 tx_all_collision;\n\t__le32 tx_aborted32;\n\t__le32 align_errors32;\n\t__le32 rx_frame_too_long;\n\t__le32 rx_runt;\n\t__le32 rx_pause_on;\n\t__le32 rx_pause_off;\n\t__le32 rx_pause_all;\n\t__le32 rx_unknown_opcode;\n\t__le32 rx_mac_error;\n\t__le32 tx_underrun32;\n\t__le32 rx_mac_missed;\n\t__le32 rx_tcam_dropped;\n\t__le32 tdu;\n\t__le32 rdu;\n};\n\nstruct rtl8169_tc_offsets {\n\tbool inited;\n\t__le64 tx_errors;\n\t__le32 tx_multi_collision;\n\t__le16 tx_aborted;\n\t__le16 rx_missed;\n};\n\nstruct r8169_led_classdev;\n\nstruct rtl_fw;\n\nstruct rtl8169_private {\n\tvoid *mmio_addr;\n\tstruct pci_dev *pci_dev;\n\tstruct net_device *dev;\n\tstruct phy_device *phydev;\n\tstruct napi_struct napi;\n\tenum mac_version mac_version;\n\tenum rtl_dash_type dash_type;\n\tu32 cur_rx;\n\tu32 cur_tx;\n\tu32 dirty_tx;\n\tstruct TxDesc *TxDescArray;\n\tstruct RxDesc *RxDescArray;\n\tdma_addr_t TxPhyAddr;\n\tdma_addr_t RxPhyAddr;\n\tstruct page *Rx_databuff[256];\n\tstruct ring_info tx_skb[256];\n\tu16 cp_cmd;\n\tu16 tx_lpi_timer;\n\tu32 irq_mask;\n\tint irq;\n\tstruct clk *clk;\n\tstruct {\n\t\tlong unsigned int flags[1];\n\t\tstruct work_struct work;\n\t} wk;\n\traw_spinlock_t mac_ocp_lock;\n\tstruct mutex led_lock;\n\tunsigned int supports_gmii: 1;\n\tunsigned int aspm_manageable: 1;\n\tunsigned int dash_enabled: 1;\n\tbool sfp_mode: 1;\n\tdma_addr_t counters_phys_addr;\n\tstruct rtl8169_counters *counters;\n\tstruct rtl8169_tc_offsets tc_offset;\n\tu32 saved_wolopts;\n\tconst char *fw_name;\n\tstruct rtl_fw *rtl_fw;\n\tstruct r8169_led_classdev *leds;\n\tu32 ocp_base;\n};\n\nstruct rtl821x_priv {\n\tbool enable_aldps;\n\tbool disable_clk_out;\n\tstruct clk *clk;\n\tu16 iner;\n};\n\nstruct rtl_chip_info {\n\tu32 mask;\n\tu32 val;\n\tenum mac_version mac_version;\n\tconst char *name;\n\tconst char *fw_name;\n};\n\nstruct rtl_coalesce_info {\n\tu32 speed;\n\tu32 scale_nsecs[4];\n};\n\nstruct rtl_cond {\n\tbool (*check)(struct rtl8169_private *);\n\tconst char *msg;\n};\n\ntypedef void (*rtl_fw_write_t)(struct rtl8169_private *, int, int);\n\ntypedef int (*rtl_fw_read_t)(struct rtl8169_private *, int);\n\nstruct rtl_fw_phy_action {\n\t__le32 *code;\n\tsize_t size;\n};\n\nstruct rtl_fw {\n\trtl_fw_write_t phy_write;\n\trtl_fw_read_t phy_read;\n\trtl_fw_write_t mac_mcu_write;\n\trtl_fw_read_t mac_mcu_read;\n\tconst struct firmware *fw;\n\tconst char *fw_name;\n\tstruct device *dev;\n\tchar version[32];\n\tstruct rtl_fw_phy_action phy_action;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rv_jit_context {\n\tstruct bpf_prog *prog;\n\tu16 *insns;\n\tu16 *ro_insns;\n\tint ninsns;\n\tint prologue_len;\n\tint epilogue_offset;\n\tint *offset;\n\tint nexentries;\n\tint ex_insn_off;\n\tint ex_jmp_off;\n\tlong unsigned int flags;\n\tint stack_size;\n\tu64 arena_vm_start;\n\tu64 user_vm_start;\n};\n\nstruct rv_jit_data {\n\tstruct bpf_binary_header *header;\n\tstruct bpf_binary_header *ro_header;\n\tu8 *image;\n\tu8 *ro_image;\n\tstruct rv_jit_context ctx;\n};\n\nstruct rwrt_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u32 last_lba;\n\t__u32 block_size;\n\t__u16 blocking;\n\t__u8 page_present: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct s3_save {\n\tu32 command;\n\tu32 dev_nt;\n\tu64 dcbaa_ptr;\n\tu32 config_reg;\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar saved_cmdlines[0];\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbiret {\n\tlong int error;\n\tlong int value;\n};\n\nstruct sbi_cppc_data {\n\tu64 val;\n\tu32 reg;\n\tstruct sbiret ret;\n};\n\nstruct sbi_cpuidle_data {\n\tu32 *states;\n\tstruct device *dev;\n};\n\nstruct sbi_domain_state {\n\tbool available;\n\tu32 state;\n};\n\nstruct sbi_hart_boot_data {\n\tvoid *task_ptr;\n\tvoid *stack_ptr;\n};\n\nstruct sbi_mpxy_channel_ids_data {\n\t__le32 remaining;\n\t__le32 returned;\n\t__le32 channel_array[0];\n};\n\nstruct sbi_mpxy_notification_data {\n\t__le32 remaining;\n\t__le32 returned;\n\t__le32 lost;\n\t__le32 reserved;\n\tu8 events_data[0];\n};\n\nstruct sbi_pd_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n};\n\nunion sbi_pmu_ctr_info {\n\tlong unsigned int value;\n\tstruct {\n\t\tlong unsigned int csr: 12;\n\t\tlong unsigned int width: 6;\n\t\tlong unsigned int reserved: 45;\n\t\tlong unsigned int type: 1;\n\t};\n};\n\nstruct sbi_pmu_event_data {\n\tunion {\n\t\tunion {\n\t\t\tstruct hw_gen_event hw_gen_event;\n\t\t\tstruct hw_cache_event hw_cache_event;\n\t\t};\n\t\tuint32_t event_idx;\n\t};\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct scale_freq_data {\n\tenum scale_freq_source source;\n\tvoid (*set_freq_scale)(void);\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_info {\n\tlong unsigned int pcount;\n\tlong long unsigned int run_delay;\n\tlong long unsigned int max_run_delay;\n\tlong long unsigned int min_run_delay;\n\tlong long unsigned int last_arrival;\n\tlong long unsigned int last_queued;\n\tstruct timespec64 max_run_delay_ts;\n};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct sched_statistics {};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n\tu32 secid;\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scratch {\n\tu8 status[29];\n\tu8 data_token;\n\t__be16 crc_val;\n};\n\nstruct screen_info {\n\t__u8 orig_x;\n\t__u8 orig_y;\n\t__u16 ext_mem_k;\n\t__u16 orig_video_page;\n\t__u8 orig_video_mode;\n\t__u8 orig_video_cols;\n\t__u8 flags;\n\t__u8 unused2;\n\t__u16 orig_video_ega_bx;\n\t__u16 unused3;\n\t__u8 orig_video_lines;\n\t__u8 orig_video_isVGA;\n\t__u16 orig_video_points;\n\t__u16 lfb_width;\n\t__u16 lfb_height;\n\t__u16 lfb_depth;\n\t__u32 lfb_base;\n\t__u32 lfb_size;\n\t__u16 cl_magic;\n\t__u16 cl_offset;\n\t__u16 lfb_linelength;\n\t__u8 red_size;\n\t__u8 red_pos;\n\t__u8 green_size;\n\t__u8 green_pos;\n\t__u8 blue_size;\n\t__u8 blue_pos;\n\t__u8 rsvd_size;\n\t__u8 rsvd_pos;\n\t__u16 vesapm_seg;\n\t__u16 vesapm_off;\n\t__u16 pages;\n\t__u16 vesa_attributes;\n\t__u32 capabilities;\n\t__u32 ext_lfb_base;\n\t__u8 _reserved[2];\n} __attribute__((packed));\n\nstruct scsi_cd {\n\tunsigned int capacity;\n\tstruct scsi_device *device;\n\tunsigned int vendor;\n\tlong unsigned int ms_offset;\n\tunsigned int writeable: 1;\n\tunsigned int use: 1;\n\tunsigned int xa_flag: 1;\n\tunsigned int readcd_known: 1;\n\tunsigned int readcd_cdda: 1;\n\tunsigned int media_present: 1;\n\tint tur_mismatch;\n\tbool tur_changed: 1;\n\tbool get_event_changed: 1;\n\tbool ignore_get_event: 1;\n\tstruct cdrom_device_info cdi;\n\tstruct mutex lock;\n\tstruct gendisk *disk;\n};\n\ntypedef struct scsi_cd Scsi_CD;\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*compat_ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 ic_enable: 1;\n\tu8 cs_enble: 1;\n\tu8 st_enble: 1;\n\tu8 reserved1: 3;\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved2[3];\n\tu8 lbm_descriptor_type: 4;\n\tu8 rlbsr: 2;\n\tu8 reserved3: 1;\n\tu8 acdlu: 1;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_proc_entry {\n\tstruct list_head entry;\n\tconst struct scsi_host_template *sht;\n\tstruct proc_dir_entry *proc_dir;\n\tunsigned int present;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 reserved1: 7;\n\tu8 perm: 1;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 rel_lifetime: 6;\n\tu8 reserved3: 2;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct sctp_paramhdr {\n\t__be16 type;\n\t__be16 length;\n};\n\nstruct sctp_adaptation_ind_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 adaptation_ind;\n};\n\nstruct sctp_addip_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 crr_id;\n};\n\nstruct sctp_addiphdr {\n\t__be32 serial;\n};\n\nstruct sockaddr_inet {\n\tshort unsigned int sa_family;\n\tchar sa_data[26];\n};\n\nunion sctp_addr {\n\tstruct sockaddr_inet sa;\n\tstruct sockaddr_in v4;\n\tstruct sockaddr_in6 v6;\n};\n\nstruct sctp_ipv4addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in_addr addr;\n};\n\nstruct sctp_ipv6addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in6_addr addr;\n};\n\nunion sctp_addr_param {\n\tstruct sctp_paramhdr p;\n\tstruct sctp_ipv4addr_param v4;\n\tstruct sctp_ipv6addr_param v6;\n};\n\nstruct sctp_transport;\n\nstruct sctp_sock;\n\nstruct sctp_af {\n\tint (*sctp_xmit)(struct sk_buff *, struct sctp_transport *);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*get_dst)(struct sctp_transport *, union sctp_addr *, struct flowi *, struct sock *);\n\tvoid (*get_saddr)(struct sctp_sock *, struct sctp_transport *, struct flowi *);\n\tvoid (*copy_addrlist)(struct list_head *, struct net_device *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *);\n\tvoid (*addr_copy)(union sctp_addr *, union sctp_addr *);\n\tvoid (*from_skb)(union sctp_addr *, struct sk_buff *, int);\n\tvoid (*from_sk)(union sctp_addr *, struct sock *);\n\tbool (*from_addr_param)(union sctp_addr *, union sctp_addr_param *, __be16, int);\n\tint (*to_addr_param)(const union sctp_addr *, union sctp_addr_param *);\n\tint (*addr_valid)(union sctp_addr *, struct sctp_sock *, const struct sk_buff *);\n\tenum sctp_scope (*scope)(union sctp_addr *);\n\tvoid (*inaddr_any)(union sctp_addr *, __be16);\n\tint (*is_any)(const union sctp_addr *);\n\tint (*available)(union sctp_addr *, struct sctp_sock *);\n\tint (*skb_iif)(const struct sk_buff *);\n\tint (*skb_sdif)(const struct sk_buff *);\n\tint (*is_ce)(const struct sk_buff *);\n\tvoid (*seq_dump_addr)(struct seq_file *, union sctp_addr *);\n\tvoid (*ecn_capable)(struct sock *);\n\t__u16 net_header_len;\n\tint sockaddr_len;\n\tint (*ip_options_len)(struct sock *);\n\tsa_family_t sa_family;\n\tstruct list_head list;\n};\n\nstruct sctp_chunk;\n\nstruct sctp_inq {\n\tstruct list_head in_chunk_list;\n\tstruct sctp_chunk *in_progress;\n\tstruct work_struct immediate;\n};\n\nstruct sctp_bind_addr {\n\t__u16 port;\n\tstruct list_head address_list;\n};\n\nstruct sctp_ep_common {\n\tenum sctp_endpoint_type type;\n\trefcount_t refcnt;\n\tbool dead;\n\tstruct sock *sk;\n\tstruct net *net;\n\tstruct sctp_inq inqueue;\n\tstruct sctp_bind_addr bind_addr;\n};\n\nstruct sctp_cookie {\n\t__u32 my_vtag;\n\t__u32 peer_vtag;\n\t__u32 my_ttag;\n\t__u32 peer_ttag;\n\tktime_t expiration;\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u32 initial_tsn;\n\tunion sctp_addr peer_addr;\n\t__u16 my_port;\n\t__u8 prsctp_capable;\n\t__u8 padding;\n\t__u32 adaptation_ind;\n\t__u8 auth_random[36];\n\t__u8 auth_hmacs[10];\n\t__u8 auth_chunks[20];\n\t__u32 raw_addr_list_len;\n};\n\nstruct sctp_tsnmap {\n\tlong unsigned int *tsn_map;\n\t__u32 base_tsn;\n\t__u32 cumulative_tsn_ack_point;\n\t__u32 max_tsn_seen;\n\t__u16 len;\n\t__u16 pending_data;\n\t__u16 num_dup_tsns;\n\t__be32 dup_tsns[16];\n};\n\nstruct sctp_inithdr_host {\n\t__u32 init_tag;\n\t__u32 a_rwnd;\n\t__u16 num_outbound_streams;\n\t__u16 num_inbound_streams;\n\t__u32 initial_tsn;\n};\n\nstruct sctp_stream_out_ext;\n\nstruct sctp_stream_out {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\tstruct sctp_stream_out_ext *ext;\n\t__u8 state;\n};\n\nstruct sctp_stream_in {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\t__u32 fsn;\n\t__u32 fsn_uo;\n\tchar pd_mode;\n\tchar pd_mode_uo;\n};\n\nstruct sctp_stream_interleave;\n\nstruct sctp_stream {\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_out type[0];\n\t} out;\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_in type[0];\n\t} in;\n\t__u16 outcnt;\n\t__u16 incnt;\n\tstruct sctp_stream_out *out_curr;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t\tstruct sctp_stream_out_ext *rr_next;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t};\n\t};\n\tstruct sctp_stream_interleave *si;\n};\n\nstruct sctp_sched_ops;\n\nstruct sctp_association;\n\nstruct sctp_outq {\n\tstruct sctp_association *asoc;\n\tstruct list_head out_chunk_list;\n\tconst struct sctp_sched_ops *sched;\n\tunsigned int out_qlen;\n\tunsigned int error;\n\tstruct list_head control_chunk_list;\n\tstruct list_head sacked;\n\tstruct list_head retransmit;\n\tstruct list_head abandoned;\n\t__u32 outstanding_bytes;\n\tchar fast_rtx;\n\tchar cork;\n};\n\nstruct sctp_ulpq {\n\tchar pd_mode;\n\tstruct sctp_association *asoc;\n\tstruct sk_buff_head reasm;\n\tstruct sk_buff_head reasm_uo;\n\tstruct sk_buff_head lobby;\n};\n\nstruct sctp_priv_assoc_stats {\n\tstruct __kernel_sockaddr_storage obs_rto_ipaddr;\n\t__u64 max_obs_rto;\n\t__u64 isacks;\n\t__u64 osacks;\n\t__u64 opackets;\n\t__u64 ipackets;\n\t__u64 rtxchunks;\n\t__u64 outofseqtsns;\n\t__u64 idupchunks;\n\t__u64 gapcnt;\n\t__u64 ouodchunks;\n\t__u64 iuodchunks;\n\t__u64 oodchunks;\n\t__u64 iodchunks;\n\t__u64 octrlchunks;\n\t__u64 ictrlchunks;\n};\n\nstruct sctp_endpoint;\n\nstruct sctp_random_param;\n\nstruct sctp_chunks_param;\n\nstruct sctp_hmac_algo_param;\n\nstruct sctp_auth_bytes;\n\nstruct sctp_shared_key;\n\nstruct sctp_association {\n\tstruct sctp_ep_common base;\n\tstruct list_head asocs;\n\tsctp_assoc_t assoc_id;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_cookie c;\n\tstruct {\n\t\tstruct list_head transport_addr_list;\n\t\t__u32 rwnd;\n\t\t__u16 transport_count;\n\t\t__u16 port;\n\t\tstruct sctp_transport *primary_path;\n\t\tunion sctp_addr primary_addr;\n\t\tstruct sctp_transport *active_path;\n\t\tstruct sctp_transport *retran_path;\n\t\tstruct sctp_transport *last_sent_to;\n\t\tstruct sctp_transport *last_data_from;\n\t\tstruct sctp_tsnmap tsn_map;\n\t\t__be16 addip_disabled_mask;\n\t\t__u16 ecn_capable: 1;\n\t\t__u16 ipv4_address: 1;\n\t\t__u16 ipv6_address: 1;\n\t\t__u16 asconf_capable: 1;\n\t\t__u16 prsctp_capable: 1;\n\t\t__u16 reconf_capable: 1;\n\t\t__u16 intl_capable: 1;\n\t\t__u16 auth_capable: 1;\n\t\t__u16 sack_needed: 1;\n\t\t__u16 sack_generation: 1;\n\t\t__u16 zero_window_announced: 1;\n\t\t__u32 sack_cnt;\n\t\t__u32 adaptation_ind;\n\t\tstruct sctp_inithdr_host i;\n\t\tvoid *cookie;\n\t\tint cookie_len;\n\t\t__u32 addip_serial;\n\t\tstruct sctp_random_param *peer_random;\n\t\tstruct sctp_chunks_param *peer_chunks;\n\t\tstruct sctp_hmac_algo_param *peer_hmacs;\n\t} peer;\n\tenum sctp_state state;\n\tint overall_error_count;\n\tktime_t cookie_life;\n\tlong unsigned int rto_initial;\n\tlong unsigned int rto_max;\n\tlong unsigned int rto_min;\n\tint max_burst;\n\tint max_retrans;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u16 max_init_attempts;\n\t__u16 init_retries;\n\tlong unsigned int max_init_timeo;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u8 pmtu_pending;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\t__u32 sackfreq;\n\tlong unsigned int sackdelay;\n\tlong unsigned int timeouts[12];\n\tstruct timer_list timers[12];\n\tstruct sctp_transport *shutdown_last_sent_to;\n\tstruct sctp_transport *init_last_sent_to;\n\tint shutdown_retries;\n\t__u32 next_tsn;\n\t__u32 ctsn_ack_point;\n\t__u32 adv_peer_ack_point;\n\t__u32 highest_sacked;\n\t__u32 fast_recovery_exit;\n\t__u8 fast_recovery;\n\t__u16 unack_data;\n\t__u32 rtx_data_chunks;\n\t__u32 rwnd;\n\t__u32 a_rwnd;\n\t__u32 rwnd_over;\n\t__u32 rwnd_press;\n\tint sndbuf_used;\n\tatomic_t rmem_alloc;\n\twait_queue_head_t wait;\n\t__u32 frag_point;\n\t__u32 user_frag;\n\tint init_err_counter;\n\tint init_cycle;\n\t__u16 default_stream;\n\t__u16 default_flags;\n\t__u32 default_ppid;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tstruct sctp_stream stream;\n\tstruct sctp_outq outqueue;\n\tstruct sctp_ulpq ulpq;\n\t__u32 last_ecne_tsn;\n\t__u32 last_cwr_tsn;\n\tint numduptsns;\n\tstruct sctp_chunk *addip_last_asconf;\n\tstruct list_head asconf_ack_list;\n\tstruct list_head addip_chunk_list;\n\t__u32 addip_serial;\n\tint src_out_of_asoc_ok;\n\tunion sctp_addr *asconf_addr_del_pending;\n\tstruct sctp_transport *new_transport;\n\tstruct list_head endpoint_shared_keys;\n\tstruct sctp_auth_bytes *asoc_shared_key;\n\tstruct sctp_shared_key *shkey;\n\t__u16 default_hmac_id;\n\t__u16 active_key_id;\n\t__u8 need_ecne: 1;\n\t__u8 temp: 1;\n\t__u8 pf_expose: 2;\n\t__u8 force_delay: 1;\n\t__u8 strreset_enable;\n\t__u8 strreset_outstanding;\n\t__u32 strreset_outseq;\n\t__u32 strreset_inseq;\n\t__u32 strreset_result[2];\n\tstruct sctp_chunk *strreset_chunk;\n\tstruct sctp_priv_assoc_stats stats;\n\tint sent_cnt_removable;\n\t__u16 subscribe;\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tu32 secid;\n\tu32 peer_secid;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_assocparams {\n\tsctp_assoc_t sasoc_assoc_id;\n\t__u16 sasoc_asocmaxrxt;\n\t__u16 sasoc_number_peer_destinations;\n\t__u32 sasoc_peer_rwnd;\n\t__u32 sasoc_local_rwnd;\n\t__u32 sasoc_cookie_life;\n};\n\nstruct sctp_auth_bytes {\n\trefcount_t refcnt;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct sctp_authhdr {\n\t__be16 shkey_id;\n\t__be16 hmac_id;\n};\n\nstruct sctp_bind_bucket {\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct hlist_node node;\n\tstruct hlist_head owner;\n\tstruct net *net;\n};\n\nstruct sctp_cookie_preserve_param;\n\nstruct sctp_hostname_param;\n\nstruct sctp_cookie_param;\n\nstruct sctp_supported_addrs_param;\n\nstruct sctp_supported_ext_param;\n\nunion sctp_params {\n\tvoid *v;\n\tstruct sctp_paramhdr *p;\n\tstruct sctp_cookie_preserve_param *life;\n\tstruct sctp_hostname_param *dns;\n\tstruct sctp_cookie_param *cookie;\n\tstruct sctp_supported_addrs_param *sat;\n\tstruct sctp_ipv4addr_param *v4;\n\tstruct sctp_ipv6addr_param *v6;\n\tunion sctp_addr_param *addr;\n\tstruct sctp_adaptation_ind_param *aind;\n\tstruct sctp_supported_ext_param *ext;\n\tstruct sctp_random_param *random;\n\tstruct sctp_chunks_param *chunks;\n\tstruct sctp_hmac_algo_param *hmac_algo;\n\tstruct sctp_addip_param *addip;\n};\n\nstruct sctp_sndrcvinfo {\n\t__u16 sinfo_stream;\n\t__u16 sinfo_ssn;\n\t__u16 sinfo_flags;\n\t__u32 sinfo_ppid;\n\t__u32 sinfo_context;\n\t__u32 sinfo_timetolive;\n\t__u32 sinfo_tsn;\n\t__u32 sinfo_cumtsn;\n\tsctp_assoc_t sinfo_assoc_id;\n};\n\nstruct sctp_datahdr;\n\nstruct sctp_inithdr;\n\nstruct sctp_sackhdr;\n\nstruct sctp_heartbeathdr;\n\nstruct sctp_sender_hb_info;\n\nstruct sctp_shutdownhdr;\n\nstruct sctp_signed_cookie;\n\nstruct sctp_ecnehdr;\n\nstruct sctp_cwrhdr;\n\nstruct sctp_errhdr;\n\nstruct sctp_fwdtsn_hdr;\n\nstruct sctp_idatahdr;\n\nstruct sctp_ifwdtsn_hdr;\n\nstruct sctp_chunkhdr;\n\nstruct sctphdr;\n\nstruct sctp_datamsg;\n\nstruct sctp_chunk {\n\tstruct list_head list;\n\trefcount_t refcnt;\n\tint sent_count;\n\tunion {\n\t\tstruct list_head transmitted_list;\n\t\tstruct list_head stream_list;\n\t};\n\tstruct list_head frag_list;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct sk_buff *head_skb;\n\t\tstruct sctp_shared_key *shkey;\n\t};\n\tunion sctp_params param_hdr;\n\tunion {\n\t\t__u8 *v;\n\t\tstruct sctp_datahdr *data_hdr;\n\t\tstruct sctp_inithdr *init_hdr;\n\t\tstruct sctp_sackhdr *sack_hdr;\n\t\tstruct sctp_heartbeathdr *hb_hdr;\n\t\tstruct sctp_sender_hb_info *hbs_hdr;\n\t\tstruct sctp_shutdownhdr *shutdown_hdr;\n\t\tstruct sctp_signed_cookie *cookie_hdr;\n\t\tstruct sctp_ecnehdr *ecne_hdr;\n\t\tstruct sctp_cwrhdr *ecn_cwr_hdr;\n\t\tstruct sctp_errhdr *err_hdr;\n\t\tstruct sctp_addiphdr *addip_hdr;\n\t\tstruct sctp_fwdtsn_hdr *fwdtsn_hdr;\n\t\tstruct sctp_authhdr *auth_hdr;\n\t\tstruct sctp_idatahdr *idata_hdr;\n\t\tstruct sctp_ifwdtsn_hdr *ifwdtsn_hdr;\n\t} subh;\n\t__u8 *chunk_end;\n\tstruct sctp_chunkhdr *chunk_hdr;\n\tstruct sctphdr *sctp_hdr;\n\tstruct sctp_sndrcvinfo sinfo;\n\tstruct sctp_association *asoc;\n\tstruct sctp_ep_common *rcvr;\n\tlong unsigned int sent_at;\n\tunion sctp_addr source;\n\tunion sctp_addr dest;\n\tstruct sctp_datamsg *msg;\n\tstruct sctp_transport *transport;\n\tstruct sk_buff *auth_chunk;\n\t__u16 rtt_in_progress: 1;\n\t__u16 has_tsn: 1;\n\t__u16 has_ssn: 1;\n\t__u16 singleton: 1;\n\t__u16 end_of_packet: 1;\n\t__u16 ecn_ce_done: 1;\n\t__u16 pdiscard: 1;\n\t__u16 tsn_gap_acked: 1;\n\t__u16 data_accepted: 1;\n\t__u16 auth: 1;\n\t__u16 has_asconf: 1;\n\t__u16 pmtu_probe: 1;\n\t__u16 tsn_missing_report: 2;\n\t__u16 fast_retransmit: 2;\n};\n\nstruct sctp_chunkhdr {\n\t__u8 type;\n\t__u8 flags;\n\t__be16 length;\n};\n\nstruct sctp_chunks_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_cookie_param {\n\tstruct sctp_paramhdr p;\n\t__u8 body[0];\n};\n\nstruct sctp_cookie_preserve_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 lifespan_increment;\n};\n\nstruct sctp_cwrhdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_datahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 ssn;\n\t__u32 ppid;\n};\n\nstruct sctp_datamsg {\n\tstruct list_head chunks;\n\trefcount_t refcnt;\n\tlong unsigned int expires_at;\n\tint send_error;\n\tu8 send_failed: 1;\n\tu8 can_delay: 1;\n\tu8 abandoned: 1;\n};\n\nstruct sctp_ecnehdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_endpoint {\n\tstruct sctp_ep_common base;\n\tstruct hlist_node node;\n\tint hashent;\n\tstruct list_head asocs;\n\tstruct hmac_sha256_key cookie_auth_key;\n\t__u32 sndbuf_policy;\n\t__u32 rcvbuf_policy;\n\tstruct sctp_hmac_algo_param *auth_hmacs_list;\n\tstruct sctp_chunks_param *auth_chunk_list;\n\tstruct list_head endpoint_shared_keys;\n\t__u16 active_key_id;\n\t__u8 ecn_enable: 1;\n\t__u8 auth_enable: 1;\n\t__u8 intl_enable: 1;\n\t__u8 prsctp_enable: 1;\n\t__u8 asconf_enable: 1;\n\t__u8 reconf_enable: 1;\n\t__u8 strreset_enable;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_errhdr {\n\t__be16 cause;\n\t__be16 length;\n};\n\nstruct sctp_fwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_heartbeathdr {\n\tstruct sctp_paramhdr info;\n};\n\nstruct sctp_hmac_algo_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 hmac_ids[0];\n};\n\nstruct sctp_hostname_param {\n\tstruct sctp_paramhdr param_hdr;\n\tuint8_t hostname[0];\n};\n\nstruct sctp_idatahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 reserved;\n\t__be32 mid;\n\tunion {\n\t\t__u32 ppid;\n\t\t__be32 fsn;\n\t};\n};\n\nstruct sctp_ifwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_inithdr {\n\t__be32 init_tag;\n\t__be32 a_rwnd;\n\t__be16 num_outbound_streams;\n\t__be16 num_inbound_streams;\n\t__be32 initial_tsn;\n};\n\nstruct sctp_initmsg {\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u16 sinit_max_attempts;\n\t__u16 sinit_max_init_timeo;\n};\n\nstruct sctp_packet {\n\t__u16 source_port;\n\t__u16 destination_port;\n\t__u32 vtag;\n\tstruct list_head chunk_list;\n\tsize_t overhead;\n\tsize_t size;\n\tsize_t max_size;\n\tstruct sctp_transport *transport;\n\tstruct sctp_chunk *auth;\n\tu8 has_cookie_echo: 1;\n\tu8 has_sack: 1;\n\tu8 has_auth: 1;\n\tu8 has_data: 1;\n\tu8 ipfragok: 1;\n};\n\nstruct sctp_paddrparams {\n\tsctp_assoc_t spp_assoc_id;\n\tstruct __kernel_sockaddr_storage spp_address;\n\t__u32 spp_hbinterval;\n\t__u16 spp_pathmaxrxt;\n\t__u32 spp_pathmtu;\n\t__u32 spp_sackdelay;\n\t__u32 spp_flags;\n\t__u32 spp_ipv6_flowlabel;\n\t__u8 spp_dscp;\n\tint: 0;\n} __attribute__((packed));\n\nstruct sctp_ulpevent;\n\nstruct sctp_pf {\n\tvoid (*event_msgname)(struct sctp_ulpevent *, char *, int *);\n\tvoid (*skb_msgname)(struct sk_buff *, char *, int *);\n\tint (*af_supported)(sa_family_t, struct sctp_sock *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *, struct sctp_sock *);\n\tint (*bind_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*send_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*supported_addrs)(const struct sctp_sock *, __be16 *);\n\tint (*addr_to_user)(struct sctp_sock *, union sctp_addr *);\n\tvoid (*to_sk_saddr)(union sctp_addr *, struct sock *);\n\tvoid (*to_sk_daddr)(union sctp_addr *, struct sock *);\n\tvoid (*copy_ip_options)(struct sock *, struct sock *);\n\tstruct sctp_af *af;\n};\n\nstruct sctp_random_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 random_val[0];\n};\n\nstruct sctp_rtoinfo {\n\tsctp_assoc_t srto_assoc_id;\n\t__u32 srto_initial;\n\t__u32 srto_max;\n\t__u32 srto_min;\n};\n\nstruct sctp_sackhdr {\n\t__be32 cum_tsn_ack;\n\t__be32 a_rwnd;\n\t__be16 num_gap_ack_blocks;\n\t__be16 num_dup_tsns;\n};\n\nstruct sctp_sender_hb_info {\n\tstruct sctp_paramhdr param_hdr;\n\tunion sctp_addr daddr;\n\tlong unsigned int sent_at;\n\t__u64 hb_nonce;\n\t__u32 probe_size;\n};\n\nstruct sctp_shared_key {\n\tstruct list_head key_list;\n\tstruct sctp_auth_bytes *key;\n\trefcount_t refcnt;\n\t__u16 key_id;\n\t__u8 deactivated;\n};\n\nstruct sctp_shutdownhdr {\n\t__be32 cum_tsn_ack;\n};\n\nstruct sctp_signed_cookie {\n\t__u8 mac[32];\n\t__u32 __pad;\n\tstruct sctp_cookie c;\n} __attribute__((packed));\n\nstruct sctp_sock {\n\tstruct inet_sock inet;\n\tenum sctp_socket_type type;\n\tstruct sctp_pf *pf;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_bind_bucket *bind_hash;\n\t__u16 default_stream;\n\t__u32 default_ppid;\n\t__u16 default_flags;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tint max_burst;\n\t__u32 hbinterval;\n\t__u32 probe_interval;\n\t__be16 udp_port;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 sackdelay;\n\t__u32 sackfreq;\n\t__u32 param_flags;\n\t__u32 default_ss;\n\tstruct sctp_rtoinfo rtoinfo;\n\tstruct sctp_paddrparams paddrparam;\n\tstruct sctp_assocparams assocparams;\n\t__u16 subscribe;\n\tstruct sctp_initmsg initmsg;\n\tint user_frag;\n\t__u32 autoclose;\n\t__u32 adaptation_ind;\n\t__u32 pd_point;\n\t__u16 nodelay: 1;\n\t__u16 pf_expose: 2;\n\t__u16 reuse: 1;\n\t__u16 disable_fragments: 1;\n\t__u16 v4mapped: 1;\n\t__u16 frag_interleave: 1;\n\t__u16 recvrcvinfo: 1;\n\t__u16 recvnxtinfo: 1;\n\t__u16 data_ready_signalled: 1;\n\t__u16 cookie_auth_enable: 1;\n\tatomic_t pd_mode;\n\tstruct sk_buff_head pd_lobby;\n\tstruct list_head auto_asconf_list;\n\tint do_auto_asconf;\n};\n\nstruct sctp_stream_interleave {\n\t__u16 data_chunk_len;\n\t__u16 ftsn_chunk_len;\n\tstruct sctp_chunk * (*make_datafrag)(const struct sctp_association *, const struct sctp_sndrcvinfo *, int, __u8, gfp_t);\n\tvoid (*assign_number)(struct sctp_chunk *);\n\tbool (*validate_data)(struct sctp_chunk *);\n\tint (*ulpevent_data)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tint (*enqueue_event)(struct sctp_ulpq *, struct sctp_ulpevent *);\n\tvoid (*renege_events)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tvoid (*start_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*abort_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*generate_ftsn)(struct sctp_outq *, __u32);\n\tbool (*validate_ftsn)(struct sctp_chunk *);\n\tvoid (*report_ftsn)(struct sctp_ulpq *, __u32);\n\tvoid (*handle_ftsn)(struct sctp_ulpq *, struct sctp_chunk *);\n};\n\nstruct sctp_stream_priorities;\n\nstruct sctp_stream_out_ext {\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tstruct list_head outq;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t\tstruct sctp_stream_priorities *prio_head;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t\t__u32 fc_length;\n\t\t\t__u16 fc_weight;\n\t\t};\n\t};\n};\n\nstruct sctp_stream_priorities {\n\tstruct list_head prio_sched;\n\tstruct list_head active;\n\tstruct sctp_stream_out_ext *next;\n\t__u16 prio;\n\t__u16 users;\n};\n\nstruct sctp_supported_addrs_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 types[0];\n};\n\nstruct sctp_supported_ext_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_transport {\n\tstruct list_head transports;\n\tstruct rhlist_head node;\n\trefcount_t refcnt;\n\t__u32 dead: 1;\n\t__u32 rto_pending: 1;\n\t__u32 hb_sent: 1;\n\t__u32 pmtu_pending: 1;\n\t__u32 dst_pending_confirm: 1;\n\t__u32 sack_generation: 1;\n\tu32 dst_cookie;\n\tstruct flowi fl;\n\tunion sctp_addr ipaddr;\n\tstruct sctp_af *af_specific;\n\tstruct sctp_association *asoc;\n\tlong unsigned int rto;\n\t__u32 rtt;\n\t__u32 rttvar;\n\t__u32 srtt;\n\t__u32 cwnd;\n\t__u32 ssthresh;\n\t__u32 partial_bytes_acked;\n\t__u32 flight_size;\n\t__u32 burst_limited;\n\tstruct dst_entry *dst;\n\tunion sctp_addr saddr;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\tlong unsigned int sackdelay;\n\t__u32 sackfreq;\n\tatomic_t mtu_info;\n\tktime_t last_time_heard;\n\tlong unsigned int last_time_sent;\n\tlong unsigned int last_time_ecne_reduced;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\tint init_sent_count;\n\tint state;\n\tshort unsigned int error_count;\n\tstruct timer_list T3_rtx_timer;\n\tstruct timer_list hb_timer;\n\tstruct timer_list proto_unreach_timer;\n\tstruct timer_list reconf_timer;\n\tstruct timer_list probe_timer;\n\tstruct list_head transmitted;\n\tstruct sctp_packet packet;\n\tstruct list_head send_ready;\n\tstruct {\n\t\t__u32 next_tsn_at_change;\n\t\tchar changeover_active;\n\t\tchar cycling_changeover;\n\t\tchar cacc_saw_newack;\n\t} cacc;\n\tstruct {\n\t\t__u16 pmtu;\n\t\t__u16 probe_size;\n\t\t__u16 probe_high;\n\t\t__u8 probe_count;\n\t\t__u8 state;\n\t} pl;\n\t__u64 hb_nonce;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_ulpevent {\n\tstruct sctp_association *asoc;\n\tstruct sctp_chunk *chunk;\n\tunsigned int rmem_len;\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\tunion {\n\t\t__u32 ppid;\n\t\t__u32 fsn;\n\t};\n\t__u32 tsn;\n\t__u32 cumtsn;\n\t__u16 stream;\n\t__u16 flags;\n\t__u16 msg_flags;\n} __attribute__((packed));\n\nstruct sctphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 vtag;\n\t__le32 checksum;\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tconst char *reason;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[1];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work error_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n};\n\nstruct sd_app_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct sd_busy_data {\n\tstruct mmc_card *card;\n\tu8 *reg_buf;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct sd_uhs2_wait_active_state_data {\n\tstruct mmc_host *host;\n\tstruct mmc_command *cmd;\n};\n\nstruct sdhci_adma2_64_desc {\n\t__le16 cmd;\n\t__le16 len;\n\t__le32 addr_lo;\n\t__le32 addr_hi;\n};\n\nstruct sdhci_cdns_drv_data {\n\tint (*init)(struct platform_device *);\n\tconst struct sdhci_pltfm_data pltfm_data;\n};\n\nstruct sdhci_cdns_phy_cfg {\n\tconst char *property;\n\tu8 addr;\n};\n\nstruct sdhci_cdns_phy_param {\n\tu8 addr;\n\tu8 data;\n};\n\nstruct sdhci_cdns_priv {\n\tvoid *hrs_addr;\n\tvoid *ctl_addr;\n\tspinlock_t wrlock;\n\tbool enhanced_strobe;\n\tvoid (*priv_writel)(struct sdhci_cdns_priv *, u32, void *);\n\tstruct reset_control *rst_hw;\n\tunsigned int nr_phy_params;\n\tstruct sdhci_cdns_phy_param phy_params[0];\n};\n\nstruct sdhci_host {\n\tconst char *hw_name;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tint irq;\n\tvoid *ioaddr;\n\tphys_addr_t mapbase;\n\tchar *bounce_buffer;\n\tdma_addr_t bounce_addr;\n\tunsigned int bounce_buffer_size;\n\tconst struct sdhci_ops *ops;\n\tstruct mmc_host *mmc;\n\tstruct mmc_host_ops mmc_host_ops;\n\tu64 dma_mask;\n\tspinlock_t lock;\n\tint flags;\n\tunsigned int version;\n\tunsigned int max_clk;\n\tunsigned int timeout_clk;\n\tu8 max_timeout_count;\n\tunsigned int clk_mul;\n\tunsigned int clock;\n\tu8 pwr;\n\tu8 drv_type;\n\tbool reinit_uhs;\n\tbool runtime_suspended;\n\tbool bus_on;\n\tbool preset_enabled;\n\tbool pending_reset;\n\tbool irq_wake_enabled;\n\tbool v4_mode;\n\tbool use_external_dma;\n\tbool always_defer_done;\n\tstruct mmc_request *mrqs_done[2];\n\tstruct mmc_command *cmd;\n\tstruct mmc_command *data_cmd;\n\tstruct mmc_command *deferred_cmd;\n\tstruct mmc_data *data;\n\tunsigned int data_early: 1;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int blocks;\n\tint sg_count;\n\tint max_adma;\n\tvoid *adma_table;\n\tvoid *align_buffer;\n\tsize_t adma_table_sz;\n\tsize_t align_buffer_sz;\n\tdma_addr_t adma_addr;\n\tdma_addr_t align_addr;\n\tunsigned int desc_sz;\n\tunsigned int alloc_desc_sz;\n\tstruct workqueue_struct *complete_wq;\n\tstruct work_struct complete_work;\n\tstruct timer_list timer;\n\tstruct timer_list data_timer;\n\tvoid (*complete_work_fn)(struct work_struct *);\n\tirqreturn_t (*thread_irq_fn)(int, void *);\n\tu32 caps;\n\tu32 caps1;\n\tbool read_caps;\n\tbool sdhci_core_to_disable_vqmmc;\n\tunsigned int ocr_avail_sdio;\n\tunsigned int ocr_avail_sd;\n\tunsigned int ocr_avail_mmc;\n\tu32 ocr_mask;\n\tunsigned int timing;\n\tu32 thread_isr;\n\tu32 ier;\n\tbool cqe_on;\n\tu32 cqe_ier;\n\tu32 cqe_err_ier;\n\twait_queue_head_t buf_ready_int;\n\tunsigned int tuning_done;\n\tunsigned int tuning_count;\n\tunsigned int tuning_mode;\n\tunsigned int tuning_err;\n\tint tuning_delay;\n\tint tuning_loop_count;\n\tu32 sdma_boundary;\n\tu32 adma_table_cnt;\n\tu64 data_timeout;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct sdhci_ops {\n\tu32 (*read_l)(struct sdhci_host *, int);\n\tu16 (*read_w)(struct sdhci_host *, int);\n\tu8 (*read_b)(struct sdhci_host *, int);\n\tvoid (*write_l)(struct sdhci_host *, u32, int);\n\tvoid (*write_w)(struct sdhci_host *, u16, int);\n\tvoid (*write_b)(struct sdhci_host *, u8, int);\n\tvoid (*set_clock)(struct sdhci_host *, unsigned int);\n\tvoid (*set_power)(struct sdhci_host *, unsigned char, short unsigned int);\n\tu32 (*irq)(struct sdhci_host *, u32);\n\tint (*set_dma_mask)(struct sdhci_host *);\n\tint (*enable_dma)(struct sdhci_host *);\n\tunsigned int (*get_max_clock)(struct sdhci_host *);\n\tunsigned int (*get_min_clock)(struct sdhci_host *);\n\tunsigned int (*get_timeout_clock)(struct sdhci_host *);\n\tunsigned int (*get_max_timeout_count)(struct sdhci_host *);\n\tvoid (*set_timeout)(struct sdhci_host *, struct mmc_command *);\n\tvoid (*set_bus_width)(struct sdhci_host *, int);\n\tvoid (*platform_send_init_74_clocks)(struct sdhci_host *, u8);\n\tunsigned int (*get_ro)(struct sdhci_host *);\n\tvoid (*reset)(struct sdhci_host *, u8);\n\tint (*platform_execute_tuning)(struct sdhci_host *, u32);\n\tvoid (*set_uhs_signaling)(struct sdhci_host *, unsigned int);\n\tvoid (*hw_reset)(struct sdhci_host *);\n\tvoid (*adma_workaround)(struct sdhci_host *, u32);\n\tvoid (*card_event)(struct sdhci_host *);\n\tvoid (*voltage_switch)(struct sdhci_host *);\n\tvoid (*adma_write_desc)(struct sdhci_host *, void **, dma_addr_t, int, unsigned int);\n\tvoid (*copy_to_bounce_buffer)(struct sdhci_host *, struct mmc_data *, unsigned int);\n\tvoid (*request_done)(struct sdhci_host *, struct mmc_request *);\n\tvoid (*dump_vendor_regs)(struct sdhci_host *);\n\tvoid (*dump_uhs2_regs)(struct sdhci_host *);\n\tvoid (*uhs2_pre_detect_init)(struct sdhci_host *);\n};\n\nstruct sdhci_pltfm_host {\n\tstruct clk *clk;\n\tunsigned int clock;\n\tu16 xfer_mode_shadow;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct sdio_device_id {\n\t__u8 class;\n\t__u16 vendor;\n\t__u16 device;\n\tkernel_ulong_t driver_data;\n};\n\nstruct sdio_driver {\n\tchar *name;\n\tconst struct sdio_device_id *id_table;\n\tint (*probe)(struct sdio_func *, const struct sdio_device_id *);\n\tvoid (*remove)(struct sdio_func *);\n\tvoid (*shutdown)(struct sdio_func *);\n\tstruct device_driver drv;\n};\n\ntypedef void sdio_irq_handler_t(struct sdio_func *);\n\nstruct sdio_func {\n\tstruct mmc_card *card;\n\tstruct device dev;\n\tsdio_irq_handler_t *irq_handler;\n\tunsigned int num;\n\tunsigned char class;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tunsigned int max_blksize;\n\tunsigned int cur_blksize;\n\tunsigned int enable_timeout;\n\tunsigned int state;\n\tu8 *tmpbuf;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n};\n\nstruct sdio_func_tuple {\n\tstruct sdio_func_tuple *next;\n\tunsigned char code;\n\tunsigned char size;\n\tunsigned char data[0];\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_metadata {\n\t__u64 filter_off;\n\t__u64 flags;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct security_class_mapping {\n\tconst char *name;\n\tconst char *perms[33];\n};\n\nstruct timezone;\n\nstruct xattr;\n\nstruct sembuf;\n\nunion security_list_options {\n\tint (*binder_set_context_mgr)(const struct cred *);\n\tint (*binder_transaction)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_binder)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_file)(const struct cred *, const struct cred *, const struct file *);\n\tint (*ptrace_access_check)(struct task_struct *, unsigned int);\n\tint (*ptrace_traceme)(struct task_struct *);\n\tint (*capget)(const struct task_struct *, kernel_cap_t *, kernel_cap_t *, kernel_cap_t *);\n\tint (*capset)(struct cred *, const struct cred *, const kernel_cap_t *, const kernel_cap_t *, const kernel_cap_t *);\n\tint (*capable)(const struct cred *, struct user_namespace *, int, unsigned int);\n\tint (*quotactl)(int, int, int, const struct super_block *);\n\tint (*quota_on)(struct dentry *);\n\tint (*syslog)(int);\n\tint (*settime)(const struct timespec64 *, const struct timezone *);\n\tint (*vm_enough_memory)(struct mm_struct *, long int);\n\tint (*bprm_creds_for_exec)(struct linux_binprm *);\n\tint (*bprm_creds_from_file)(struct linux_binprm *, const struct file *);\n\tint (*bprm_check_security)(struct linux_binprm *);\n\tvoid (*bprm_committing_creds)(const struct linux_binprm *);\n\tvoid (*bprm_committed_creds)(const struct linux_binprm *);\n\tint (*fs_context_submount)(struct fs_context *, struct super_block *);\n\tint (*fs_context_dup)(struct fs_context *, struct fs_context *);\n\tint (*fs_context_parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*sb_alloc_security)(struct super_block *);\n\tvoid (*sb_delete)(struct super_block *);\n\tvoid (*sb_free_security)(struct super_block *);\n\tvoid (*sb_free_mnt_opts)(void *);\n\tint (*sb_eat_lsm_opts)(char *, void **);\n\tint (*sb_mnt_opts_compat)(struct super_block *, void *);\n\tint (*sb_remount)(struct super_block *, void *);\n\tint (*sb_kern_mount)(const struct super_block *);\n\tint (*sb_show_options)(struct seq_file *, struct super_block *);\n\tint (*sb_statfs)(struct dentry *);\n\tint (*sb_mount)(const char *, const struct path *, const char *, long unsigned int, void *);\n\tint (*sb_umount)(struct vfsmount *, int);\n\tint (*sb_pivotroot)(const struct path *, const struct path *);\n\tint (*sb_set_mnt_opts)(struct super_block *, void *, long unsigned int, long unsigned int *);\n\tint (*sb_clone_mnt_opts)(const struct super_block *, struct super_block *, long unsigned int, long unsigned int *);\n\tint (*move_mount)(const struct path *, const struct path *);\n\tint (*dentry_init_security)(struct dentry *, int, const struct qstr *, const char **, struct lsm_context *);\n\tint (*dentry_create_files_as)(struct dentry *, int, const struct qstr *, const struct cred *, struct cred *);\n\tint (*path_unlink)(const struct path *, struct dentry *);\n\tint (*path_mkdir)(const struct path *, struct dentry *, umode_t);\n\tint (*path_rmdir)(const struct path *, struct dentry *);\n\tint (*path_mknod)(const struct path *, struct dentry *, umode_t, unsigned int);\n\tvoid (*path_post_mknod)(struct mnt_idmap *, struct dentry *);\n\tint (*path_truncate)(const struct path *);\n\tint (*path_symlink)(const struct path *, struct dentry *, const char *);\n\tint (*path_link)(struct dentry *, const struct path *, struct dentry *);\n\tint (*path_rename)(const struct path *, struct dentry *, const struct path *, struct dentry *, unsigned int);\n\tint (*path_chmod)(const struct path *, umode_t);\n\tint (*path_chown)(const struct path *, kuid_t, kgid_t);\n\tint (*path_chroot)(const struct path *);\n\tint (*path_notify)(const struct path *, u64, unsigned int);\n\tint (*inode_alloc_security)(struct inode *);\n\tvoid (*inode_free_security)(struct inode *);\n\tvoid (*inode_free_security_rcu)(void *);\n\tint (*inode_init_security)(struct inode *, struct inode *, const struct qstr *, struct xattr *, int *);\n\tint (*inode_init_security_anon)(struct inode *, const struct qstr *, const struct inode *);\n\tint (*inode_create)(struct inode *, struct dentry *, umode_t);\n\tvoid (*inode_post_create_tmpfile)(struct mnt_idmap *, struct inode *);\n\tint (*inode_link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_unlink)(struct inode *, struct dentry *);\n\tint (*inode_symlink)(struct inode *, struct dentry *, const char *);\n\tint (*inode_mkdir)(struct inode *, struct dentry *, umode_t);\n\tint (*inode_rmdir)(struct inode *, struct dentry *);\n\tint (*inode_mknod)(struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*inode_rename)(struct inode *, struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_readlink)(struct dentry *);\n\tint (*inode_follow_link)(struct dentry *, struct inode *, bool);\n\tint (*inode_permission)(struct inode *, int);\n\tint (*inode_setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tvoid (*inode_post_setattr)(struct mnt_idmap *, struct dentry *, int);\n\tint (*inode_getattr)(const struct path *);\n\tint (*inode_xattr_skipcap)(const char *);\n\tint (*inode_setxattr)(struct mnt_idmap *, struct dentry *, const char *, const void *, size_t, int);\n\tvoid (*inode_post_setxattr)(struct dentry *, const char *, const void *, size_t, int);\n\tint (*inode_getxattr)(struct dentry *, const char *);\n\tint (*inode_listxattr)(struct dentry *);\n\tint (*inode_removexattr)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_removexattr)(struct dentry *, const char *);\n\tint (*inode_file_setattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_file_getattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_set_acl)(struct mnt_idmap *, struct dentry *, const char *, struct posix_acl *);\n\tvoid (*inode_post_set_acl)(struct dentry *, const char *, struct posix_acl *);\n\tint (*inode_get_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_need_killpriv)(struct dentry *);\n\tint (*inode_killpriv)(struct mnt_idmap *, struct dentry *);\n\tint (*inode_getsecurity)(struct mnt_idmap *, struct inode *, const char *, void **, bool);\n\tint (*inode_setsecurity)(struct inode *, const char *, const void *, size_t, int);\n\tint (*inode_listsecurity)(struct inode *, char *, size_t);\n\tvoid (*inode_getlsmprop)(struct inode *, struct lsm_prop *);\n\tint (*inode_copy_up)(struct dentry *, struct cred **);\n\tint (*inode_copy_up_xattr)(struct dentry *, const char *);\n\tint (*inode_setintegrity)(const struct inode *, enum lsm_integrity_type, const void *, size_t);\n\tint (*kernfs_init_security)(struct kernfs_node *, struct kernfs_node *);\n\tint (*file_permission)(struct file *, int);\n\tint (*file_alloc_security)(struct file *);\n\tvoid (*file_release)(struct file *);\n\tvoid (*file_free_security)(struct file *);\n\tint (*file_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*file_ioctl_compat)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap_addr)(long unsigned int);\n\tint (*mmap_file)(struct file *, long unsigned int, long unsigned int, long unsigned int);\n\tint (*file_mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int);\n\tint (*file_lock)(struct file *, unsigned int);\n\tint (*file_fcntl)(struct file *, unsigned int, long unsigned int);\n\tvoid (*file_set_fowner)(struct file *);\n\tint (*file_send_sigiotask)(struct task_struct *, struct fown_struct *, int);\n\tint (*file_receive)(struct file *);\n\tint (*file_open)(struct file *);\n\tint (*file_post_open)(struct file *, int);\n\tint (*file_truncate)(struct file *);\n\tint (*task_alloc)(struct task_struct *, u64);\n\tvoid (*task_free)(struct task_struct *);\n\tint (*cred_alloc_blank)(struct cred *, gfp_t);\n\tvoid (*cred_free)(struct cred *);\n\tint (*cred_prepare)(struct cred *, const struct cred *, gfp_t);\n\tvoid (*cred_transfer)(struct cred *, const struct cred *);\n\tvoid (*cred_getsecid)(const struct cred *, u32 *);\n\tvoid (*cred_getlsmprop)(const struct cred *, struct lsm_prop *);\n\tint (*kernel_act_as)(struct cred *, u32);\n\tint (*kernel_create_files_as)(struct cred *, struct inode *);\n\tint (*kernel_module_request)(char *);\n\tint (*kernel_load_data)(enum kernel_load_data_id, bool);\n\tint (*kernel_post_load_data)(char *, loff_t, enum kernel_load_data_id, char *);\n\tint (*kernel_read_file)(struct file *, enum kernel_read_file_id, bool);\n\tint (*kernel_post_read_file)(struct file *, char *, loff_t, enum kernel_read_file_id);\n\tint (*task_fix_setuid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgroups)(struct cred *, const struct cred *);\n\tint (*task_setpgid)(struct task_struct *, pid_t);\n\tint (*task_getpgid)(struct task_struct *);\n\tint (*task_getsid)(struct task_struct *);\n\tvoid (*current_getlsmprop_subj)(struct lsm_prop *);\n\tvoid (*task_getlsmprop_obj)(struct task_struct *, struct lsm_prop *);\n\tint (*task_setnice)(struct task_struct *, int);\n\tint (*task_setioprio)(struct task_struct *, int);\n\tint (*task_getioprio)(struct task_struct *);\n\tint (*task_prlimit)(const struct cred *, const struct cred *, unsigned int);\n\tint (*task_setrlimit)(struct task_struct *, unsigned int, struct rlimit *);\n\tint (*task_setscheduler)(struct task_struct *);\n\tint (*task_getscheduler)(struct task_struct *);\n\tint (*task_movememory)(struct task_struct *);\n\tint (*task_kill)(struct task_struct *, struct kernel_siginfo *, int, const struct cred *);\n\tint (*task_prctl)(int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tvoid (*task_to_inode)(struct task_struct *, struct inode *);\n\tint (*userns_create)(const struct cred *);\n\tint (*ipc_permission)(struct kern_ipc_perm *, short int);\n\tvoid (*ipc_getlsmprop)(struct kern_ipc_perm *, struct lsm_prop *);\n\tint (*msg_msg_alloc_security)(struct msg_msg *);\n\tvoid (*msg_msg_free_security)(struct msg_msg *);\n\tint (*msg_queue_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*msg_queue_free_security)(struct kern_ipc_perm *);\n\tint (*msg_queue_associate)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgctl)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgsnd)(struct kern_ipc_perm *, struct msg_msg *, int);\n\tint (*msg_queue_msgrcv)(struct kern_ipc_perm *, struct msg_msg *, struct task_struct *, long int, int);\n\tint (*shm_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*shm_free_security)(struct kern_ipc_perm *);\n\tint (*shm_associate)(struct kern_ipc_perm *, int);\n\tint (*shm_shmctl)(struct kern_ipc_perm *, int);\n\tint (*shm_shmat)(struct kern_ipc_perm *, char *, int);\n\tint (*sem_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*sem_free_security)(struct kern_ipc_perm *);\n\tint (*sem_associate)(struct kern_ipc_perm *, int);\n\tint (*sem_semctl)(struct kern_ipc_perm *, int);\n\tint (*sem_semop)(struct kern_ipc_perm *, struct sembuf *, unsigned int, int);\n\tint (*netlink_send)(struct sock *, struct sk_buff *);\n\tvoid (*d_instantiate)(struct dentry *, struct inode *);\n\tint (*getselfattr)(unsigned int, struct lsm_ctx *, u32 *, u32);\n\tint (*setselfattr)(unsigned int, struct lsm_ctx *, u32, u32);\n\tint (*getprocattr)(struct task_struct *, const char *, char **);\n\tint (*setprocattr)(const char *, void *, size_t);\n\tint (*ismaclabel)(const char *);\n\tint (*secid_to_secctx)(u32, struct lsm_context *);\n\tint (*lsmprop_to_secctx)(struct lsm_prop *, struct lsm_context *);\n\tint (*secctx_to_secid)(const char *, u32, u32 *);\n\tvoid (*release_secctx)(struct lsm_context *);\n\tvoid (*inode_invalidate_secctx)(struct inode *);\n\tint (*inode_notifysecctx)(struct inode *, void *, u32);\n\tint (*inode_setsecctx)(struct dentry *, void *, u32);\n\tint (*inode_getsecctx)(struct inode *, struct lsm_context *);\n\tint (*unix_stream_connect)(struct sock *, struct sock *, struct sock *);\n\tint (*unix_may_send)(struct socket *, struct socket *);\n\tint (*socket_create)(int, int, int, int);\n\tint (*socket_post_create)(struct socket *, int, int, int, int);\n\tint (*socket_socketpair)(struct socket *, struct socket *);\n\tint (*socket_bind)(struct socket *, struct sockaddr *, int);\n\tint (*socket_connect)(struct socket *, struct sockaddr *, int);\n\tint (*socket_listen)(struct socket *, int);\n\tint (*socket_accept)(struct socket *, struct socket *);\n\tint (*socket_sendmsg)(struct socket *, struct msghdr *, int);\n\tint (*socket_recvmsg)(struct socket *, struct msghdr *, int, int);\n\tint (*socket_getsockname)(struct socket *);\n\tint (*socket_getpeername)(struct socket *);\n\tint (*socket_getsockopt)(struct socket *, int, int);\n\tint (*socket_setsockopt)(struct socket *, int, int);\n\tint (*socket_shutdown)(struct socket *, int);\n\tint (*socket_sock_rcv_skb)(struct sock *, struct sk_buff *);\n\tint (*socket_getpeersec_stream)(struct socket *, sockptr_t, sockptr_t, unsigned int);\n\tint (*socket_getpeersec_dgram)(struct socket *, struct sk_buff *, u32 *);\n\tint (*sk_alloc_security)(struct sock *, int, gfp_t);\n\tvoid (*sk_free_security)(struct sock *);\n\tvoid (*sk_clone_security)(const struct sock *, struct sock *);\n\tvoid (*sk_getsecid)(const struct sock *, u32 *);\n\tvoid (*sock_graft)(struct sock *, struct socket *);\n\tint (*inet_conn_request)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*inet_csk_clone)(struct sock *, const struct request_sock *);\n\tvoid (*inet_conn_established)(struct sock *, struct sk_buff *);\n\tint (*secmark_relabel_packet)(u32);\n\tvoid (*secmark_refcount_inc)(void);\n\tvoid (*secmark_refcount_dec)(void);\n\tvoid (*req_classify_flow)(const struct request_sock *, struct flowi_common *);\n\tint (*tun_dev_alloc_security)(void *);\n\tint (*tun_dev_create)(void);\n\tint (*tun_dev_attach_queue)(void *);\n\tint (*tun_dev_attach)(struct sock *, void *);\n\tint (*tun_dev_open)(void *);\n\tint (*sctp_assoc_request)(struct sctp_association *, struct sk_buff *);\n\tint (*sctp_bind_connect)(struct sock *, int, struct sockaddr *, int);\n\tvoid (*sctp_sk_clone)(struct sctp_association *, struct sock *, struct sock *);\n\tint (*sctp_assoc_established)(struct sctp_association *, struct sk_buff *);\n\tint (*mptcp_add_subflow)(struct sock *, struct sock *);\n\tint (*key_alloc)(struct key *, const struct cred *, long unsigned int);\n\tint (*key_permission)(key_ref_t, const struct cred *, enum key_need_perm);\n\tint (*key_getsecurity)(struct key *, char **);\n\tvoid (*key_post_create_or_update)(struct key *, struct key *, const void *, size_t, long unsigned int, bool);\n\tint (*audit_rule_init)(u32, u32, char *, void **, gfp_t);\n\tint (*audit_rule_known)(struct audit_krule *);\n\tint (*audit_rule_match)(struct lsm_prop *, u32, u32, void *);\n\tvoid (*audit_rule_free)(void *);\n\tint (*bpf)(int, union bpf_attr *, unsigned int, bool);\n\tint (*bpf_map)(struct bpf_map *, fmode_t);\n\tint (*bpf_prog)(struct bpf_prog *);\n\tint (*bpf_map_create)(struct bpf_map *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_map_free)(struct bpf_map *);\n\tint (*bpf_prog_load)(struct bpf_prog *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_prog_free)(struct bpf_prog *);\n\tint (*bpf_token_create)(struct bpf_token *, union bpf_attr *, const struct path *);\n\tvoid (*bpf_token_free)(struct bpf_token *);\n\tint (*bpf_token_cmd)(const struct bpf_token *, enum bpf_cmd);\n\tint (*bpf_token_capable)(const struct bpf_token *, int);\n\tint (*locked_down)(enum lockdown_reason);\n\tint (*perf_event_open)(int);\n\tint (*perf_event_alloc)(struct perf_event *);\n\tint (*perf_event_read)(struct perf_event *);\n\tint (*perf_event_write)(struct perf_event *);\n\tint (*uring_override_creds)(const struct cred *);\n\tint (*uring_sqpoll)(void);\n\tint (*uring_cmd)(struct io_uring_cmd *);\n\tint (*uring_allowed)(void);\n\tvoid (*initramfs_populated)(void);\n\tint (*bdev_alloc_security)(struct block_device *);\n\tvoid (*bdev_free_security)(struct block_device *);\n\tint (*bdev_setintegrity)(struct block_device *, enum lsm_integrity_type, const void *, size_t);\n\tvoid *lsm_func_addr;\n};\n\nstruct security_hook_list {\n\tstruct lsm_static_call *scalls;\n\tunion security_list_options hook;\n\tconst struct lsm_id *lsmid;\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nstruct sel_netif {\n\tstruct list_head list;\n\tstruct netif_security_struct nsec;\n\tstruct callback_head callback_head;\n};\n\nstruct sel_netnode {\n\tstruct netnode_security_struct nsec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netnode_bkt {\n\tunsigned int size;\n\tstruct list_head list;\n};\n\nstruct sel_netport {\n\tstruct netport_security_struct psec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netport_bkt {\n\tint size;\n\tstruct list_head list;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct selinux_audit_data {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tu32 requested;\n\tu32 audited;\n\tu32 denied;\n\tint result;\n};\n\nstruct selinux_audit_rule {\n\tu32 au_seqno;\n\tstruct context au_ctxt;\n};\n\nstruct selinux_avc {\n\tunsigned int avc_cache_threshold;\n\tstruct avc_cache avc_cache;\n};\n\nstruct selinux_fs_info {\n\tstruct dentry *bool_dir;\n\tunsigned int bool_num;\n\tchar **bool_pending_names;\n\tint *bool_pending_values;\n\tstruct dentry *class_dir;\n\tlong unsigned int last_class_ino;\n\tbool policy_opened;\n\tlong unsigned int last_ino;\n\tstruct super_block *sb;\n};\n\nstruct selinux_kernel_status {\n\tu32 version;\n\tu32 sequence;\n\tu32 enforcing;\n\tu32 policyload;\n\tu32 deny_unknown;\n};\n\nstruct selinux_policy;\n\nstruct selinux_policy_convert_data;\n\nstruct selinux_load_state {\n\tstruct selinux_policy *policy;\n\tstruct selinux_policy_convert_data *convert_data;\n};\n\nstruct selinux_mapping;\n\nstruct selinux_map {\n\tstruct selinux_mapping *mapping;\n\tu16 size;\n};\n\nstruct selinux_mapping {\n\tu16 value;\n\tu16 num_perms;\n\tu32 perms[32];\n};\n\nstruct selinux_mnt_opts {\n\tu32 fscontext_sid;\n\tu32 context_sid;\n\tu32 rootcontext_sid;\n\tu32 defcontext_sid;\n};\n\nstruct sidtab;\n\nstruct selinux_policy {\n\tstruct sidtab *sidtab;\n\tstruct policydb policydb;\n\tstruct selinux_map map;\n\tu32 latest_granting;\n};\n\nstruct sidtab_convert_params {\n\tstruct convert_context_args *args;\n\tstruct sidtab *target;\n};\n\nstruct selinux_policy_convert_data {\n\tstruct convert_context_args args;\n\tstruct sidtab_convert_params sidtab_params;\n};\n\nstruct selinux_state {\n\tbool enforcing;\n\tbool initialized;\n\tbool policycap[15];\n\tstruct page *status_page;\n\tstruct mutex status_lock;\n\tstruct selinux_policy *policy;\n\tstruct mutex policy_mutex;\n};\n\nstruct selnl_msg_policyload {\n\t__u32 seqno;\n};\n\nstruct selnl_msg_setenforce {\n\t__s32 val;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\ttime64_t sem_otime;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\tlong int sem_otime;\n\tlong int sem_ctime;\n\tlong unsigned int sem_nsems;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct virtnet_sq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_tx_drops;\n\tu64_stats_t kicks;\n\tu64_stats_t tx_timeouts;\n\tu64_stats_t stop;\n\tu64_stats_t wake;\n};\n\nstruct send_queue {\n\tstruct virtqueue *vq;\n\tstruct scatterlist sg[19];\n\tchar name[16];\n\tstruct virtnet_sq_stats stats;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct napi_struct napi;\n\tbool reset;\n\tstruct xsk_buff_pool *xsk_pool;\n\tdma_addr_t xsk_hdr_dma_addr;\n};\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n\tbool has_siginfo;\n\tstruct kernel_siginfo info;\n};\n\nstruct sense_iu {\n\t__u8 iu_id;\n\t__u8 rsvd1;\n\t__be16 tag;\n\t__be16 status_qual;\n\t__u8 status;\n\t__u8 rsvd7[7];\n\t__be16 len;\n\t__u8 sense[96];\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct seqcount_rwlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_rwlock seqcount_rwlock_t;\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct serial_ctrl_device {\n\tstruct device dev;\n\tstruct ida port_ida;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_port_device {\n\tstruct device dev;\n\tstruct uart_port *port;\n\tunsigned int tx_enabled: 1;\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\nstruct serial_struct32 {\n\tcompat_int_t type;\n\tcompat_int_t line;\n\tcompat_uint_t port;\n\tcompat_int_t irq;\n\tcompat_int_t flags;\n\tcompat_int_t xmit_fifo_size;\n\tcompat_int_t custom_divisor;\n\tcompat_int_t baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char;\n\tcompat_int_t hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tcompat_uint_t iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tcompat_int_t reserved;\n};\n\ntypedef struct serio *class_serio_pause_rx_t;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nstruct serport {\n\tstruct tty_struct *tty;\n\twait_queue_head_t wait;\n\tstruct serio *serio;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_config_request {\n\tstruct usb_device *udev;\n\tint config;\n\tstruct work_struct work;\n\tstruct list_head node;\n};\n\nstruct set_event_iter {\n\tenum set_event_iter_type type;\n\tunion {\n\t\tstruct trace_event_file *file;\n\t\tstruct event_mod_load *event_mod;\n\t};\n};\n\nstruct sfdp {\n\tsize_t num_dwords;\n\tu32 *dwords;\n};\n\nstruct sfdp_4bait {\n\tu32 hwcaps;\n\tu32 supported_bit;\n};\n\nstruct sfdp_bfpt {\n\tu32 dwords[20];\n};\n\nstruct sfdp_bfpt_erase {\n\tu32 dword;\n\tu32 shift;\n};\n\nstruct sfdp_bfpt_read {\n\tu32 hwcaps;\n\tu32 supported_dword;\n\tu32 supported_bit;\n\tu32 settings_dword;\n\tu32 settings_shift;\n\tenum spi_nor_protocol proto;\n};\n\nstruct sfdp_parameter_header {\n\tu8 id_lsb;\n\tu8 minor;\n\tu8 major;\n\tu8 length;\n\tu8 parameter_table_pointer[3];\n\tu8 id_msb;\n};\n\nstruct sfdp_header {\n\tu32 signature;\n\tu8 minor;\n\tu8 major;\n\tu8 nph;\n\tu8 unused;\n\tstruct sfdp_parameter_header bfpt_header;\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_module_caps {\n\tlong unsigned int interfaces[1];\n\tlong unsigned int link_modes[2];\n\tbool may_have_phy;\n\tu8 port;\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *, struct phy_device *);\n};\n\nstruct sg2042_clk_data {\n\tvoid *iobase;\n\tstruct clk_hw_onecell_data onecell_data;\n};\n\nstruct sg2042_divider_clock {\n\tstruct clk_hw hw;\n\tunsigned int id;\n\tvoid *reg;\n\tspinlock_t *lock;\n\tu32 offset_ctrl;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tu32 initval;\n};\n\nstruct sg2042_gate_clock {\n\tstruct clk_hw hw;\n\tunsigned int id;\n\tu32 offset_enable;\n\tu8 bit_idx;\n};\n\nstruct sg2042_mux_clock {\n\tstruct clk_hw hw;\n\tunsigned int id;\n\tu32 offset_select;\n\tu8 shift;\n\tu8 width;\n\tstruct notifier_block clk_nb;\n\tu8 original_index;\n};\n\nstruct sg2042_pll_clock {\n\tstruct clk_hw hw;\n\tunsigned int id;\n\tvoid *base;\n\tspinlock_t *lock;\n\tu32 offset_ctrl;\n\tu8 shift_status_lock;\n\tu8 shift_status_updating;\n\tu8 shift_enable;\n};\n\nstruct sg2042_pll_ctrl {\n\tlong unsigned int freq;\n\tunsigned int fbdiv;\n\tunsigned int postdiv1;\n\tunsigned int postdiv2;\n\tunsigned int refdiv;\n};\n\nstruct sg2042_rpgate_clock {\n\tstruct clk_hw hw;\n\tunsigned int id;\n\tu32 offset_enable;\n\tu8 bit_idx;\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_list {\n\tunsigned int n;\n\tunsigned int size;\n\tsize_t len;\n\tstruct scatterlist *sg;\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct shared_policy {\n\tstruct rb_root root;\n\trwlock_t lock;\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\t__kernel_size_t shm_segsz;\n\tlong int shm_atime;\n\tlong int shm_dtime;\n\tlong int shm_ctime;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct shortname_info {\n\tunsigned char lower: 1;\n\tunsigned char upper: 1;\n\tunsigned char valid: 1;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tint id;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct shrinker_info_unit;\n\nstruct shrinker_info {\n\tstruct callback_head rcu;\n\tint map_nr_max;\n\tstruct shrinker_info_unit *unit[0];\n};\n\nstruct shrinker_info_unit {\n\tatomic_long_t nr_deferred[64];\n\tlong unsigned int map[1];\n};\n\nstruct sidtab_node_inner;\n\nstruct sidtab_node_leaf;\n\nunion sidtab_entry_inner {\n\tstruct sidtab_node_inner *ptr_inner;\n\tstruct sidtab_node_leaf *ptr_leaf;\n};\n\nstruct sidtab_str_cache;\n\nstruct sidtab_entry {\n\tu32 sid;\n\tu32 hash;\n\tstruct context context;\n\tstruct sidtab_str_cache *cache;\n\tstruct hlist_node list;\n};\n\nstruct sidtab_isid_entry {\n\tint set;\n\tstruct sidtab_entry entry;\n};\n\nstruct sidtab {\n\tunion sidtab_entry_inner roots[4];\n\tu32 count;\n\tstruct sidtab_convert_params *convert;\n\tbool frozen;\n\tspinlock_t lock;\n\tu32 cache_free_slots;\n\tstruct list_head cache_lru_list;\n\tspinlock_t cache_lock;\n\tstruct sidtab_isid_entry isids[27];\n\tstruct hlist_head context_to_sid[512];\n};\n\nstruct sidtab_node_inner {\n\tunion sidtab_entry_inner entries[512];\n};\n\nstruct sidtab_node_leaf {\n\tstruct sidtab_entry entries[39];\n};\n\nstruct sidtab_str_cache {\n\tstruct callback_head rcu_member;\n\tstruct list_head lru_member;\n\tstruct sidtab_entry *parent;\n\tu32 len;\n\tchar str[0];\n};\n\nstruct sifive_fu540_macb_mgmt {\n\tvoid *reg;\n\tlong unsigned int rate;\n\tstruct clk_hw hw;\n};\n\nstruct sifive_gpio {\n\tvoid *base;\n\tstruct gpio_generic_chip gen_gc;\n\tstruct regmap *regs;\n\tlong unsigned int irq_state;\n\tunsigned int trigger[32];\n\tunsigned int irq_number[32];\n};\n\nstruct sifive_serial_port {\n\tstruct uart_port port;\n\tstruct device *dev;\n\tunsigned char ier;\n\tlong unsigned int baud_rate;\n\tstruct clk *clk;\n\tstruct notifier_block clk_notifier;\n\tbool console_line_ended;\n};\n\nstruct sifive_spi {\n\tvoid *regs;\n\tstruct clk *clk;\n\tunsigned int fifo_depth;\n\tu32 cs_inactive;\n\tstruct completion done;\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {};\n\nstruct tty_audit_buf;\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tunsigned int audit_tty;\n\tstruct tty_audit_buf *tty_audit_buf;\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_mfd_data {\n\tconst struct regmap_config *regmap_config;\n\tconst struct mfd_cell *mfd_cell;\n\tsize_t mfd_cell_size;\n};\n\nstruct simple_pm_bus {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct sit_net {\n\tstruct ip_tunnel *tunnels_r_l[16];\n\tstruct ip_tunnel *tunnels_r[16];\n\tstruct ip_tunnel *tunnels_l[16];\n\tstruct ip_tunnel *tunnels_wc[1];\n\tstruct ip_tunnel **tunnels[4];\n\tstruct net_device *fb_tunnel_dev;\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct sk_security_struct {\n\tu32 sid;\n\tu32 peer_sid;\n\tu16 sclass;\n\tenum {\n\t\tSCTP_ASSOC_UNSET = 0,\n\t\tSCTP_ASSOC_SET = 1,\n\t} sctp_assoc_state;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct skb_ext {\n\trefcount_t refcnt;\n\tu8 offset[3];\n\tu8 chunks;\n\tchar data[0];\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int obj_exts;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct slabobj_ext {\n\tstruct obj_cgroup *objcg;\n};\n\nstruct slot_pwrctrl {\n\tstruct pci_pwrctrl pwrctrl;\n\tstruct regulator_bulk_data *supplies;\n\tint num_supplies;\n\tstruct clk *clk;\n\tstruct pwrseq_desc *pwrseq;\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct snd_aes_iec958 {\n\tunsigned char status[24];\n\tunsigned char subcode[147];\n\tunsigned char pad;\n\tunsigned char dig_subframe[4];\n};\n\nstruct snd_shutdown_f_ops;\n\nstruct snd_info_entry;\n\nstruct snd_card {\n\tint number;\n\tchar id[16];\n\tchar driver[16];\n\tchar shortname[32];\n\tchar longname[80];\n\tchar irq_descr[32];\n\tchar mixername[80];\n\tchar components[128];\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_card *);\n\tstruct list_head devices;\n\tstruct device *ctl_dev;\n\tunsigned int last_numid;\n\tstruct rw_semaphore controls_rwsem;\n\trwlock_t controls_rwlock;\n\tint controls_count;\n\tsize_t user_ctl_alloc_size;\n\tstruct list_head controls;\n\tstruct list_head ctl_files;\n\tstruct xarray ctl_numids;\n\tstruct xarray ctl_hash;\n\tbool ctl_hash_collision;\n\tstruct snd_info_entry *proc_root;\n\tstruct proc_dir_entry *proc_root_link;\n\tstruct list_head files_list;\n\tstruct snd_shutdown_f_ops *s_f_ops;\n\tspinlock_t files_lock;\n\tint shutdown;\n\tstruct completion *release_completion;\n\tstruct device *dev;\n\tstruct device card_dev;\n\tconst struct attribute_group *dev_groups[4];\n\tbool registered;\n\tbool managed;\n\tbool releasing;\n\tint sync_irq;\n\twait_queue_head_t remove_sleep;\n\tsize_t total_pcm_alloc_bytes;\n\tstruct mutex memory_mutex;\n\tunsigned int power_state;\n\tatomic_t power_ref;\n\twait_queue_head_t power_sleep;\n\twait_queue_head_t power_ref_sleep;\n};\n\nstruct snd_enc_wma {\n\t__u32 super_block_align;\n};\n\nstruct snd_enc_vorbis {\n\t__s32 quality;\n\t__u32 managed;\n\t__u32 max_bit_rate;\n\t__u32 min_bit_rate;\n\t__u32 downmix;\n};\n\nstruct snd_enc_real {\n\t__u32 quant_bits;\n\t__u32 start_region;\n\t__u32 num_regions;\n};\n\nstruct snd_enc_flac {\n\t__u32 num;\n\t__u32 gain;\n};\n\nstruct snd_enc_generic {\n\t__u32 bw;\n\t__s32 reserved[15];\n};\n\nstruct snd_dec_flac {\n\t__u16 sample_size;\n\t__u16 min_blk_size;\n\t__u16 max_blk_size;\n\t__u16 min_frame_size;\n\t__u16 max_frame_size;\n\t__u16 reserved;\n};\n\nstruct snd_dec_wma {\n\t__u32 encoder_option;\n\t__u32 adv_encoder_option;\n\t__u32 adv_encoder_option2;\n\t__u32 reserved;\n};\n\nstruct snd_dec_alac {\n\t__u32 frame_length;\n\t__u8 compatible_version;\n\t__u8 pb;\n\t__u8 mb;\n\t__u8 kb;\n\t__u32 max_run;\n\t__u32 max_frame_bytes;\n};\n\nstruct snd_dec_ape {\n\t__u16 compatible_version;\n\t__u16 compression_level;\n\t__u32 format_flags;\n\t__u32 blocks_per_frame;\n\t__u32 final_frame_blocks;\n\t__u32 total_frames;\n\t__u32 seek_table_present;\n};\n\nstruct snd_dec_opus_ch_map {\n\t__u8 stream_count;\n\t__u8 coupled_count;\n\t__u8 channel_map[8];\n};\n\nstruct snd_dec_opus {\n\t__u8 version;\n\t__u8 num_channels;\n\t__u16 pre_skip;\n\t__u32 sample_rate;\n\t__u16 output_gain;\n\t__u8 mapping_family;\n\tstruct snd_dec_opus_ch_map chan_map;\n};\n\nunion snd_codec_options {\n\tstruct snd_enc_wma wma;\n\tstruct snd_enc_vorbis vorbis;\n\tstruct snd_enc_real real;\n\tstruct snd_enc_flac flac;\n\tstruct snd_enc_generic generic;\n\tstruct snd_dec_flac flac_d;\n\tstruct snd_dec_wma wma_d;\n\tstruct snd_dec_alac alac_d;\n\tstruct snd_dec_ape ape_d;\n\tstruct snd_dec_opus opus_d;\n\tstruct {\n\t\t__u32 out_sample_rate;\n\t} src_d;\n};\n\nstruct snd_codec {\n\t__u32 id;\n\t__u32 ch_in;\n\t__u32 ch_out;\n\t__u32 sample_rate;\n\t__u32 bit_rate;\n\t__u32 rate_control;\n\t__u32 profile;\n\t__u32 level;\n\t__u32 ch_mode;\n\t__u32 format;\n\t__u32 align;\n\tunion snd_codec_options options;\n\t__u32 pcm_format;\n\t__u32 reserved[2];\n};\n\nstruct snd_codec_desc_src {\n\t__u32 out_sample_rate_min;\n\t__u32 out_sample_rate_max;\n};\n\nstruct snd_codec_desc {\n\t__u32 max_ch;\n\t__u32 sample_rates[32];\n\t__u32 num_sample_rates;\n\t__u32 bit_rate[32];\n\t__u32 num_bitrates;\n\t__u32 rate_control;\n\t__u32 profiles;\n\t__u32 modes;\n\t__u32 formats;\n\t__u32 min_buffer;\n\t__u32 pcm_formats;\n\tunion {\n\t\t__u32 u_space[6];\n\t\tstruct snd_codec_desc_src src;\n\t};\n\t__u32 reserved[8];\n};\n\nstruct snd_compr_ops;\n\nstruct snd_compr {\n\tconst char *name;\n\tstruct device *dev;\n\tstruct snd_compr_ops *ops;\n\tvoid *private_data;\n\tstruct snd_card *card;\n\tunsigned int direction;\n\tstruct mutex lock;\n\tint device;\n\tbool use_pause_in_draining;\n\tchar id[64];\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_info_entry *proc_info_entry;\n};\n\nstruct snd_compr_caps {\n\t__u32 num_codecs;\n\t__u32 direction;\n\t__u32 min_fragment_size;\n\t__u32 max_fragment_size;\n\t__u32 min_fragments;\n\t__u32 max_fragments;\n\t__u32 codecs[32];\n\t__u32 reserved[11];\n};\n\nstruct snd_compr_codec_caps {\n\t__u32 codec;\n\t__u32 num_descriptors;\n\tstruct snd_codec_desc descriptor[32];\n};\n\nstruct snd_compr_metadata {\n\t__u32 key;\n\t__u32 value[8];\n};\n\nstruct snd_compr_params;\n\nstruct snd_compr_tstamp64;\n\nstruct snd_compr_ops {\n\tint (*open)(struct snd_compr_stream *);\n\tint (*free)(struct snd_compr_stream *);\n\tint (*set_params)(struct snd_compr_stream *, struct snd_compr_params *);\n\tint (*get_params)(struct snd_compr_stream *, struct snd_codec *);\n\tint (*set_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*get_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*trigger)(struct snd_compr_stream *, int);\n\tint (*pointer)(struct snd_compr_stream *, struct snd_compr_tstamp64 *);\n\tint (*copy)(struct snd_compr_stream *, char *, size_t);\n\tint (*mmap)(struct snd_compr_stream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_compr_stream *, size_t);\n\tint (*get_caps)(struct snd_compr_stream *, struct snd_compr_caps *);\n\tint (*get_codec_caps)(struct snd_compr_stream *, struct snd_compr_codec_caps *);\n};\n\nstruct snd_compressed_buffer {\n\t__u32 fragment_size;\n\t__u32 fragments;\n};\n\nstruct snd_compr_params {\n\tstruct snd_compressed_buffer buffer;\n\tstruct snd_codec codec;\n\t__u8 no_wake_mode;\n};\n\nstruct snd_dma_buffer;\n\nstruct snd_compr_runtime {\n\tsnd_pcm_state_t state;\n\tstruct snd_compr_ops *ops;\n\tvoid *buffer;\n\tu64 buffer_size;\n\tu32 fragment_size;\n\tu32 fragments;\n\tu64 total_bytes_available;\n\tu64 total_bytes_transferred;\n\twait_queue_head_t sleep;\n\tvoid *private_data;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n};\n\nstruct snd_dma_device {\n\tint type;\n\tenum dma_data_direction dir;\n\tbool need_sync;\n\tstruct device *dev;\n};\n\nstruct snd_dma_buffer {\n\tstruct snd_dma_device dev;\n\tunsigned char *area;\n\tdma_addr_t addr;\n\tsize_t bytes;\n\tvoid *private_data;\n};\n\nstruct snd_compr_stream {\n\tconst char *name;\n\tstruct snd_compr_ops *ops;\n\tstruct snd_compr_runtime *runtime;\n\tstruct snd_compr *device;\n\tstruct delayed_work error_work;\n\tenum snd_compr_direction direction;\n\tbool metadata_set;\n\tbool next_track;\n\tbool partial_drain;\n\tbool pause_in_draining;\n\tvoid *private_data;\n\tstruct snd_dma_buffer dma_buffer;\n};\n\nstruct snd_compr_tstamp64 {\n\t__u32 byte_offset;\n\t__u64 copied_total;\n\t__u64 pcm_frames;\n\t__u64 pcm_io_frames;\n\t__u32 sampling_rate;\n} __attribute__((packed));\n\nstruct snd_compress_ops {\n\tint (*open)(struct snd_soc_component *, struct snd_compr_stream *);\n\tint (*free)(struct snd_soc_component *, struct snd_compr_stream *);\n\tint (*set_params)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_params *);\n\tint (*get_params)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_codec *);\n\tint (*set_metadata)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*get_metadata)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*trigger)(struct snd_soc_component *, struct snd_compr_stream *, int);\n\tint (*pointer)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_tstamp64 *);\n\tint (*copy)(struct snd_soc_component *, struct snd_compr_stream *, char *, size_t);\n\tint (*mmap)(struct snd_soc_component *, struct snd_compr_stream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_soc_component *, struct snd_compr_stream *, size_t);\n\tint (*get_caps)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_caps *);\n\tint (*get_codec_caps)(struct snd_soc_component *, struct snd_compr_stream *, struct snd_compr_codec_caps *);\n};\n\nstruct snd_ctl_card_info {\n\tint card;\n\tint pad;\n\tunsigned char id[16];\n\tunsigned char driver[16];\n\tunsigned char name[32];\n\tunsigned char longname[80];\n\tunsigned char reserved_[16];\n\tunsigned char mixername[80];\n\tunsigned char components[128];\n};\n\nstruct snd_ctl_elem_id {\n\tunsigned int numid;\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tunsigned char name[44];\n\tunsigned int index;\n};\n\nstruct snd_ctl_elem_info {\n\tstruct snd_ctl_elem_id id;\n\tsnd_ctl_elem_type_t type;\n\tunsigned int access;\n\tunsigned int count;\n\t__kernel_pid_t owner;\n\tunion {\n\t\tstruct {\n\t\t\tlong int min;\n\t\t\tlong int max;\n\t\t\tlong int step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tlong long int min;\n\t\t\tlong long int max;\n\t\t\tlong long int step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tunsigned int items;\n\t\t\tunsigned int item;\n\t\t\tchar name[64];\n\t\t\t__u64 names_ptr;\n\t\t\tunsigned int names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_info32 {\n\tstruct snd_ctl_elem_id id;\n\ts32 type;\n\tu32 access;\n\tu32 count;\n\ts32 owner;\n\tunion {\n\t\tstruct {\n\t\t\ts32 min;\n\t\t\ts32 max;\n\t\t\ts32 step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tu64 min;\n\t\t\tu64 max;\n\t\t\tu64 step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tu32 items;\n\t\t\tu32 item;\n\t\t\tchar name[64];\n\t\t\tu64 names_ptr;\n\t\t\tu32 names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_list {\n\tunsigned int offset;\n\tunsigned int space;\n\tunsigned int used;\n\tunsigned int count;\n\tstruct snd_ctl_elem_id *pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_list32 {\n\tu32 offset;\n\tu32 space;\n\tu32 used;\n\tu32 count;\n\tu32 pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_value {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect: 1;\n\tunion {\n\t\tunion {\n\t\t\tlong int value[128];\n\t\t\tlong int *value_ptr;\n\t\t} integer;\n\t\tunion {\n\t\t\tlong long int value[64];\n\t\t\tlong long int *value_ptr;\n\t\t} integer64;\n\t\tunion {\n\t\t\tunsigned int item[128];\n\t\t\tunsigned int *item_ptr;\n\t\t} enumerated;\n\t\tunion {\n\t\t\tunsigned char data[512];\n\t\t\tunsigned char *data_ptr;\n\t\t} bytes;\n\t\tstruct snd_aes_iec958 iec958;\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_ctl_elem_value32 {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect;\n\tunion {\n\t\ts32 integer[128];\n\t\tunsigned char data[512];\n\t\ts64 integer64[64];\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_ctl_event {\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int mask;\n\t\t\tstruct snd_ctl_elem_id id;\n\t\t} elem;\n\t\tunsigned char data8[60];\n\t} data;\n};\n\nstruct snd_fasync;\n\nstruct snd_ctl_file {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tstruct pid *pid;\n\tint preferred_subdevice[2];\n\twait_queue_head_t change_sleep;\n\tspinlock_t read_lock;\n\tstruct snd_fasync *fasync;\n\tint subscribed;\n\tstruct list_head events;\n};\n\nstruct snd_kcontrol;\n\nstruct snd_ctl_layer_ops {\n\tstruct snd_ctl_layer_ops *next;\n\tconst char *module_name;\n\tvoid (*lregister)(struct snd_card *);\n\tvoid (*ldisconnect)(struct snd_card *);\n\tvoid (*lnotify)(struct snd_card *, unsigned int, struct snd_kcontrol *, unsigned int);\n};\n\nstruct snd_ctl_tlv {\n\tunsigned int numid;\n\tunsigned int length;\n\tunsigned int tlv[0];\n};\n\nstruct snd_device_ops;\n\nstruct snd_device {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tenum snd_device_state state;\n\tenum snd_device_type type;\n\tvoid *device_data;\n\tconst struct snd_device_ops *ops;\n};\n\nstruct snd_device_ops {\n\tint (*dev_free)(struct snd_device *);\n\tint (*dev_register)(struct snd_device *);\n\tint (*dev_disconnect)(struct snd_device *);\n};\n\nstruct snd_dmaengine_dai_dma_data {\n\tdma_addr_t addr;\n\tenum dma_slave_buswidth addr_width;\n\tu32 maxburst;\n\tvoid *filter_data;\n\tconst char *chan_name;\n\tunsigned int fifo_size;\n\tunsigned int flags;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n\tu32 port_window_size;\n};\n\nstruct snd_pcm_hw_params;\n\nstruct snd_soc_pcm_runtime;\n\nstruct snd_pcm_hardware;\n\nstruct snd_dmaengine_pcm_config {\n\tint (*prepare_slave_config)(struct snd_pcm_substream *, struct snd_pcm_hw_params *, struct dma_slave_config *);\n\tstruct dma_chan * (*compat_request_channel)(struct snd_soc_pcm_runtime *, struct snd_pcm_substream *);\n\tint (*process)(struct snd_pcm_substream *, int, long unsigned int, long unsigned int);\n\tconst char *name;\n\tdma_filter_fn compat_filter_fn;\n\tstruct device *dma_dev;\n\tconst char *chan_names[2];\n\tconst struct snd_pcm_hardware *pcm_hardware;\n\tunsigned int prealloc_buffer_size;\n};\n\nstruct snd_fasync {\n\tstruct fasync_struct *fasync;\n\tint signal;\n\tint poll;\n\tint on;\n\tstruct list_head list;\n};\n\nstruct snd_info_buffer {\n\tchar *buffer;\n\tunsigned int curr;\n\tunsigned int size;\n\tunsigned int len;\n\tint stop;\n\tint error;\n};\n\nstruct snd_info_entry_text {\n\tvoid (*read)(struct snd_info_entry *, struct snd_info_buffer *);\n\tvoid (*write)(struct snd_info_entry *, struct snd_info_buffer *);\n};\n\nstruct snd_info_entry_ops;\n\nstruct snd_info_entry {\n\tconst char *name;\n\tumode_t mode;\n\tlong int size;\n\tshort unsigned int content;\n\tunion {\n\t\tstruct snd_info_entry_text text;\n\t\tconst struct snd_info_entry_ops *ops;\n\t} c;\n\tstruct snd_info_entry *parent;\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_info_entry *);\n\tstruct proc_dir_entry *p;\n\tstruct mutex access;\n\tstruct list_head children;\n\tstruct list_head list;\n};\n\nstruct snd_info_entry_ops {\n\tint (*open)(struct snd_info_entry *, short unsigned int, void **);\n\tint (*release)(struct snd_info_entry *, short unsigned int, void *);\n\tssize_t (*read)(struct snd_info_entry *, void *, struct file *, char *, size_t, loff_t);\n\tssize_t (*write)(struct snd_info_entry *, void *, struct file *, const char *, size_t, loff_t);\n\tloff_t (*llseek)(struct snd_info_entry *, void *, struct file *, loff_t, int);\n\t__poll_t (*poll)(struct snd_info_entry *, void *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_info_entry *, void *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_info_entry *, void *, struct inode *, struct file *, struct vm_area_struct *);\n};\n\nstruct snd_info_private_data {\n\tstruct snd_info_buffer *rbuffer;\n\tstruct snd_info_buffer *wbuffer;\n\tstruct snd_info_entry *entry;\n\tvoid *file_private_data;\n};\n\nstruct snd_interval {\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int openmin: 1;\n\tunsigned int openmax: 1;\n\tunsigned int integer: 1;\n\tunsigned int empty: 1;\n};\n\nstruct snd_jack {\n\tstruct list_head kctl_list;\n\tstruct snd_card *card;\n\tconst char *id;\n\tstruct input_dev *input_dev;\n\tstruct mutex input_dev_lock;\n\tint registered;\n\tint type;\n\tchar name[100];\n\tunsigned int key[6];\n\tint hw_status_cache;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_jack *);\n};\n\nstruct snd_jack_kctl {\n\tstruct snd_kcontrol *kctl;\n\tstruct list_head list;\n\tunsigned int mask_bits;\n\tstruct snd_jack *jack;\n\tbool sw_inject_enable;\n};\n\ntypedef int snd_kcontrol_info_t(struct snd_kcontrol *, struct snd_ctl_elem_info *);\n\ntypedef int snd_kcontrol_get_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_put_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_tlv_rw_t(struct snd_kcontrol *, int, unsigned int, unsigned int *);\n\nstruct snd_kcontrol_volatile {\n\tstruct snd_ctl_file *owner;\n\tunsigned int access;\n};\n\nstruct snd_kcontrol {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_kcontrol *);\n\tstruct snd_kcontrol_volatile vd[0];\n};\n\nstruct snd_kcontrol_new {\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tconst char *name;\n\tunsigned int index;\n\tunsigned int access;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n};\n\nstruct snd_kctl_event {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int mask;\n};\n\ntypedef int (*snd_kctl_ioctl_func_t)(struct snd_card *, struct snd_ctl_file *, unsigned int, long unsigned int);\n\nstruct snd_kctl_ioctl {\n\tstruct list_head list;\n\tsnd_kctl_ioctl_func_t fioctl;\n};\n\nstruct snd_malloc_ops {\n\tvoid * (*alloc)(struct snd_dma_buffer *, size_t);\n\tvoid (*free)(struct snd_dma_buffer *);\n\tdma_addr_t (*get_addr)(struct snd_dma_buffer *, size_t);\n\tstruct page * (*get_page)(struct snd_dma_buffer *, size_t);\n\tunsigned int (*get_chunk_size)(struct snd_dma_buffer *, unsigned int, unsigned int);\n\tint (*mmap)(struct snd_dma_buffer *, struct vm_area_struct *);\n\tvoid (*sync)(struct snd_dma_buffer *, enum snd_dma_sync_mode);\n};\n\nstruct snd_mask {\n\t__u32 bits[8];\n};\n\nstruct snd_minor {\n\tint type;\n\tint card;\n\tint device;\n\tconst struct file_operations *f_ops;\n\tvoid *private_data;\n\tstruct device *dev;\n\tstruct snd_card *card_ptr;\n};\n\nstruct snd_monitor_file {\n\tstruct file *file;\n\tconst struct file_operations *disconnected_f_op;\n\tstruct list_head shutdown_list;\n\tstruct list_head list;\n};\n\nstruct snd_pci_quirk {\n\tshort unsigned int subvendor;\n\tshort unsigned int subdevice;\n\tshort unsigned int subdevice_mask;\n\tint value;\n};\n\nstruct snd_pcm;\n\nstruct snd_pcm_str {\n\tint stream;\n\tstruct snd_pcm *pcm;\n\tunsigned int substream_count;\n\tunsigned int substream_opened;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_kcontrol *chmap_kctl;\n\tstruct device *dev;\n};\n\nstruct snd_pcm {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tunsigned int info_flags;\n\tshort unsigned int dev_class;\n\tshort unsigned int dev_subclass;\n\tchar id[64];\n\tchar name[80];\n\tstruct snd_pcm_str streams[2];\n\tstruct mutex open_mutex;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm *);\n\tbool internal;\n\tbool nonatomic;\n\tbool no_device_suspend;\n};\n\nstruct snd_pcm_audio_tstamp_config {\n\tu32 type_requested: 4;\n\tu32 report_delay: 1;\n};\n\nstruct snd_pcm_audio_tstamp_report {\n\tu32 valid: 1;\n\tu32 actual_type: 4;\n\tu32 accuracy_report: 1;\n\tu32 accuracy;\n};\n\nstruct snd_pcm_channel_info {\n\tunsigned int channel;\n\t__kernel_off_t offset;\n\tunsigned int first;\n\tunsigned int step;\n};\n\nstruct snd_pcm_channel_info32 {\n\tu32 channel;\n\tu32 offset;\n\tu32 first;\n\tu32 step;\n};\n\nstruct snd_pcm_chmap_elem;\n\nstruct snd_pcm_chmap {\n\tstruct snd_pcm *pcm;\n\tint stream;\n\tstruct snd_kcontrol *kctl;\n\tconst struct snd_pcm_chmap_elem *chmap;\n\tunsigned int max_channels;\n\tunsigned int channel_mask;\n\tvoid *private_data;\n};\n\nstruct snd_pcm_chmap_elem {\n\tunsigned char channels;\n\tunsigned char map[15];\n};\n\nstruct snd_pcm_file {\n\tstruct snd_pcm_substream *substream;\n\tint no_compat_mmap;\n\tunsigned int user_pversion;\n};\n\nstruct snd_pcm_group {\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head substreams;\n\trefcount_t refs;\n};\n\nstruct snd_pcm_hardware {\n\tunsigned int info;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int rates;\n\tunsigned int rate_min;\n\tunsigned int rate_max;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\tsize_t buffer_bytes_max;\n\tsize_t period_bytes_min;\n\tsize_t period_bytes_max;\n\tunsigned int periods_min;\n\tunsigned int periods_max;\n\tsize_t fifo_size;\n};\n\nstruct snd_pcm_hw_constraint_list {\n\tconst unsigned int *list;\n\tunsigned int count;\n\tunsigned int mask;\n};\n\nstruct snd_pcm_hw_constraint_ranges {\n\tunsigned int count;\n\tconst struct snd_interval *ranges;\n\tunsigned int mask;\n};\n\nstruct snd_ratden;\n\nstruct snd_pcm_hw_constraint_ratdens {\n\tint nrats;\n\tconst struct snd_ratden *rats;\n};\n\nstruct snd_ratnum;\n\nstruct snd_pcm_hw_constraint_ratnums {\n\tint nrats;\n\tconst struct snd_ratnum *rats;\n};\n\nstruct snd_pcm_hw_rule;\n\nstruct snd_pcm_hw_constraints {\n\tstruct snd_mask masks[3];\n\tstruct snd_interval intervals[12];\n\tunsigned int rules_num;\n\tunsigned int rules_all;\n\tstruct snd_pcm_hw_rule *rules;\n};\n\nstruct snd_pcm_hw_params {\n\tunsigned int flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tunsigned int rmask;\n\tunsigned int cmask;\n\tunsigned int info;\n\tunsigned int msbits;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tsnd_pcm_uframes_t fifo_size;\n\tunsigned char sync[16];\n\tunsigned char reserved[48];\n};\n\nstruct snd_pcm_hw_params32 {\n\tu32 flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tu32 rmask;\n\tu32 cmask;\n\tu32 info;\n\tu32 msbits;\n\tu32 rate_num;\n\tu32 rate_den;\n\tu32 fifo_size;\n\tunsigned char reserved[64];\n};\n\ntypedef int (*snd_pcm_hw_rule_func_t)(struct snd_pcm_hw_params *, struct snd_pcm_hw_rule *);\n\nstruct snd_pcm_hw_rule {\n\tunsigned int cond;\n\tint var;\n\tint deps[5];\n\tsnd_pcm_hw_rule_func_t func;\n\tvoid *private;\n};\n\nstruct snd_pcm_info {\n\tunsigned int device;\n\tunsigned int subdevice;\n\tint stream;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tunsigned char subname[32];\n\tint dev_class;\n\tint dev_subclass;\n\tunsigned int subdevices_count;\n\tunsigned int subdevices_avail;\n\tunsigned char pad1[16];\n\tunsigned char reserved[64];\n};\n\nstruct snd_pcm_mmap_control {\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t appl_ptr;\n\t__pad_before_uframe __pad2;\n\t__pad_before_uframe __pad3;\n\tsnd_pcm_uframes_t avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct snd_pcm_mmap_control32 {\n\tu32 appl_ptr;\n\tu32 avail_min;\n};\n\nstruct snd_pcm_mmap_status {\n\tsnd_pcm_state_t state;\n\t__u32 pad1;\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t hw_ptr;\n\t__pad_after_uframe __pad2;\n\tstruct __kernel_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 pad3;\n\tstruct __kernel_timespec audio_tstamp;\n};\n\nstruct snd_pcm_mmap_status32 {\n\tsnd_pcm_state_t state;\n\ts32 pad1;\n\tu32 hw_ptr;\n\tstruct __snd_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\tstruct __snd_timespec audio_tstamp;\n};\n\nstruct snd_pcm_ops {\n\tint (*open)(struct snd_pcm_substream *);\n\tint (*close)(struct snd_pcm_substream *);\n\tint (*ioctl)(struct snd_pcm_substream *, unsigned int, void *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_pcm_substream *, int);\n\tint (*sync_stop)(struct snd_pcm_substream *);\n\tsnd_pcm_uframes_t (*pointer)(struct snd_pcm_substream *);\n\tint (*get_time_info)(struct snd_pcm_substream *, struct timespec64 *, struct timespec64 *, struct snd_pcm_audio_tstamp_config *, struct snd_pcm_audio_tstamp_report *);\n\tint (*fill_silence)(struct snd_pcm_substream *, int, long unsigned int, long unsigned int);\n\tint (*copy)(struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\tstruct page * (*page)(struct snd_pcm_substream *, long unsigned int);\n\tint (*mmap)(struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_pcm_substream *);\n};\n\nstruct snd_pcm_runtime {\n\tsnd_pcm_state_t state;\n\tsnd_pcm_state_t suspended_state;\n\tstruct snd_pcm_substream *trigger_master;\n\tstruct timespec64 trigger_tstamp;\n\tbool trigger_tstamp_latched;\n\tint overrange;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t hw_ptr_base;\n\tsnd_pcm_uframes_t hw_ptr_interrupt;\n\tlong unsigned int hw_ptr_jiffies;\n\tlong unsigned int hw_ptr_buffer_jiffies;\n\tsnd_pcm_sframes_t delay;\n\tu64 hw_ptr_wrap;\n\tsnd_pcm_access_t access;\n\tsnd_pcm_format_t format;\n\tsnd_pcm_subformat_t subformat;\n\tunsigned int rate;\n\tunsigned int channels;\n\tsnd_pcm_uframes_t period_size;\n\tunsigned int periods;\n\tsnd_pcm_uframes_t buffer_size;\n\tsnd_pcm_uframes_t min_align;\n\tsize_t byte_align;\n\tunsigned int frame_bits;\n\tunsigned int sample_bits;\n\tunsigned int info;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tunsigned int no_period_wakeup: 1;\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tsnd_pcm_uframes_t silence_start;\n\tsnd_pcm_uframes_t silence_filled;\n\tbool std_sync_id;\n\tstruct snd_pcm_mmap_status *status;\n\tstruct snd_pcm_mmap_control *control;\n\tsnd_pcm_uframes_t twake;\n\twait_queue_head_t sleep;\n\twait_queue_head_t tsleep;\n\tstruct snd_fasync *fasync;\n\tbool stop_operating;\n\tstruct mutex buffer_mutex;\n\tatomic_t buffer_accessing;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm_runtime *);\n\tstruct snd_pcm_hardware hw;\n\tstruct snd_pcm_hw_constraints hw_constraints;\n\tunsigned int timer_resolution;\n\tint tstamp_type;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n\tunsigned int buffer_changed: 1;\n\tstruct snd_pcm_audio_tstamp_config audio_tstamp_config;\n\tstruct snd_pcm_audio_tstamp_report audio_tstamp_report;\n\tstruct timespec64 driver_tstamp;\n};\n\nstruct snd_pcm_status32 {\n\tsnd_pcm_state_t state;\n\ts32 trigger_tstamp_sec;\n\ts32 trigger_tstamp_nsec;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts32 audio_tstamp_sec;\n\ts32 audio_tstamp_nsec;\n\ts32 driver_tstamp_sec;\n\ts32 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[36];\n};\n\nstruct snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tsnd_pcm_uframes_t appl_ptr;\n\tsnd_pcm_uframes_t hw_ptr;\n\tsnd_pcm_sframes_t delay;\n\tsnd_pcm_uframes_t avail;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t overrange;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\t__u32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nstruct snd_timer;\n\nstruct snd_pcm_substream {\n\tstruct snd_pcm *pcm;\n\tstruct snd_pcm_str *pstr;\n\tvoid *private_data;\n\tint number;\n\tchar name[32];\n\tint stream;\n\tstruct pm_qos_request latency_pm_qos_req;\n\tsize_t buffer_bytes_max;\n\tstruct snd_dma_buffer dma_buffer;\n\tsize_t dma_max;\n\tconst struct snd_pcm_ops *ops;\n\tstruct snd_pcm_runtime *runtime;\n\tstruct snd_timer *timer;\n\tunsigned int timer_running: 1;\n\tlong int wait_time;\n\tstruct snd_pcm_substream *next;\n\tstruct list_head link_list;\n\tstruct snd_pcm_group self_group;\n\tstruct snd_pcm_group *group;\n\tint ref_count;\n\tatomic_t mmap_count;\n\tunsigned int f_flags;\n\tvoid (*pcm_release)(struct snd_pcm_substream *);\n\tstruct pid *pid;\n\tstruct snd_info_entry *proc_root;\n\tunsigned int hw_opened: 1;\n\tunsigned int managed_buffer_alloc: 1;\n};\n\nstruct snd_pcm_sw_params {\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tunsigned int sleep_min;\n\tsnd_pcm_uframes_t avail_min;\n\tsnd_pcm_uframes_t xfer_align;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tunsigned int proto;\n\tunsigned int tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_sw_params32 {\n\ts32 tstamp_mode;\n\tu32 period_step;\n\tu32 sleep_min;\n\tu32 avail_min;\n\tu32 xfer_align;\n\tu32 start_threshold;\n\tu32 stop_threshold;\n\tu32 silence_threshold;\n\tu32 silence_size;\n\tu32 boundary;\n\tu32 proto;\n\tu32 tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_sync_ptr {\n\t__u32 flags;\n\t__u32 pad1;\n\tunion {\n\t\tstruct snd_pcm_mmap_status status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_pcm_sync_ptr32 {\n\tu32 flags;\n\tunion {\n\t\tstruct snd_pcm_mmap_status32 status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control32 control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_ratden {\n\tunsigned int num_min;\n\tunsigned int num_max;\n\tunsigned int num_step;\n\tunsigned int den;\n};\n\nstruct snd_ratnum {\n\tunsigned int num;\n\tunsigned int den_min;\n\tunsigned int den_max;\n\tunsigned int den_step;\n};\n\nstruct snd_soc_dai_link_component {\n\tconst char *name;\n\tstruct device_node *of_node;\n\tconst char *dai_name;\n\tconst struct of_phandle_args *dai_args;\n\tunsigned int ext_fmt;\n};\n\nstruct snd_soc_aux_dev {\n\tstruct snd_soc_dai_link_component dlc;\n\tint (*init)(struct snd_soc_component *);\n};\n\nstruct snd_soc_dapm_stats {\n\tint power_checks;\n\tint path_checks;\n\tint neighbour_checks;\n};\n\nstruct snd_soc_dai_link;\n\nstruct snd_soc_codec_conf;\n\nstruct snd_soc_dapm_route;\n\nstruct snd_soc_card {\n\tconst char *name;\n\tconst char *long_name;\n\tconst char *driver_name;\n\tconst char *components;\n\tchar dmi_longname[80];\n\tshort unsigned int pci_subsystem_vendor;\n\tshort unsigned int pci_subsystem_device;\n\tbool pci_subsystem_set;\n\tchar topology_shortname[32];\n\tstruct device *dev;\n\tstruct snd_card *snd_card;\n\tstruct module *owner;\n\tstruct mutex mutex;\n\tstruct mutex dapm_mutex;\n\tstruct mutex pcm_mutex;\n\tenum snd_soc_pcm_subclass pcm_subclass;\n\tint (*probe)(struct snd_soc_card *);\n\tint (*late_probe)(struct snd_soc_card *);\n\tvoid (*fixup_controls)(struct snd_soc_card *);\n\tint (*remove)(struct snd_soc_card *);\n\tint (*suspend_pre)(struct snd_soc_card *);\n\tint (*suspend_post)(struct snd_soc_card *);\n\tint (*resume_pre)(struct snd_soc_card *);\n\tint (*resume_post)(struct snd_soc_card *);\n\tint (*set_bias_level)(struct snd_soc_card *, struct snd_soc_dapm_context *, enum snd_soc_bias_level);\n\tint (*set_bias_level_post)(struct snd_soc_card *, struct snd_soc_dapm_context *, enum snd_soc_bias_level);\n\tint (*add_dai_link)(struct snd_soc_card *, struct snd_soc_dai_link *);\n\tvoid (*remove_dai_link)(struct snd_soc_card *, struct snd_soc_dai_link *);\n\tlong int pmdown_time;\n\tstruct snd_soc_dai_link *dai_link;\n\tint num_links;\n\tstruct list_head rtd_list;\n\tint num_rtd;\n\tstruct snd_soc_codec_conf *codec_conf;\n\tint num_configs;\n\tstruct snd_soc_aux_dev *aux_dev;\n\tint num_aux_devs;\n\tstruct list_head aux_comp_list;\n\tconst struct snd_kcontrol_new *controls;\n\tint num_controls;\n\tconst struct snd_soc_dapm_widget *dapm_widgets;\n\tint num_dapm_widgets;\n\tconst struct snd_soc_dapm_route *dapm_routes;\n\tint num_dapm_routes;\n\tconst struct snd_soc_dapm_widget *of_dapm_widgets;\n\tint num_of_dapm_widgets;\n\tconst struct snd_soc_dapm_route *of_dapm_routes;\n\tint num_of_dapm_routes;\n\tstruct list_head component_dev_list;\n\tstruct list_head list;\n\tstruct list_head widgets;\n\tstruct list_head paths;\n\tstruct list_head dapm_list;\n\tstruct list_head dapm_dirty;\n\tstruct list_head dobj_list;\n\tstruct snd_soc_dapm_context *dapm;\n\tstruct snd_soc_dapm_stats dapm_stats;\n\tstruct dentry *debugfs_card_root;\n\tstruct work_struct deferred_resume_work;\n\tu32 pop_time;\n\tunsigned int instantiated: 1;\n\tunsigned int topology_shortname_created: 1;\n\tunsigned int fully_routed: 1;\n\tunsigned int probed: 1;\n\tunsigned int component_chaining: 1;\n\tstruct device *devres_dev;\n\tvoid *drvdata;\n};\n\nstruct snd_soc_dai;\n\nstruct snd_soc_cdai_ops {\n\tint (*startup)(struct snd_compr_stream *, struct snd_soc_dai *);\n\tint (*shutdown)(struct snd_compr_stream *, struct snd_soc_dai *);\n\tint (*set_params)(struct snd_compr_stream *, struct snd_compr_params *, struct snd_soc_dai *);\n\tint (*get_params)(struct snd_compr_stream *, struct snd_codec *, struct snd_soc_dai *);\n\tint (*set_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *, struct snd_soc_dai *);\n\tint (*get_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *, struct snd_soc_dai *);\n\tint (*trigger)(struct snd_compr_stream *, int, struct snd_soc_dai *);\n\tint (*pointer)(struct snd_compr_stream *, struct snd_compr_tstamp64 *, struct snd_soc_dai *);\n\tint (*ack)(struct snd_compr_stream *, size_t, struct snd_soc_dai *);\n};\n\nstruct snd_soc_codec_conf {\n\tstruct snd_soc_dai_link_component dlc;\n\tconst char *name_prefix;\n};\n\nstruct snd_soc_component_driver {\n\tconst char *name;\n\tconst struct snd_kcontrol_new *controls;\n\tunsigned int num_controls;\n\tconst struct snd_soc_dapm_widget *dapm_widgets;\n\tunsigned int num_dapm_widgets;\n\tconst struct snd_soc_dapm_route *dapm_routes;\n\tunsigned int num_dapm_routes;\n\tint (*probe)(struct snd_soc_component *);\n\tvoid (*remove)(struct snd_soc_component *);\n\tint (*suspend)(struct snd_soc_component *);\n\tint (*resume)(struct snd_soc_component *);\n\tunsigned int (*read)(struct snd_soc_component *, unsigned int);\n\tint (*write)(struct snd_soc_component *, unsigned int, unsigned int);\n\tint (*pcm_construct)(struct snd_soc_component *, struct snd_soc_pcm_runtime *);\n\tvoid (*pcm_destruct)(struct snd_soc_component *, struct snd_pcm *);\n\tint (*set_sysclk)(struct snd_soc_component *, int, int, unsigned int, int);\n\tint (*set_pll)(struct snd_soc_component *, int, int, unsigned int, unsigned int);\n\tint (*set_jack)(struct snd_soc_component *, struct snd_soc_jack *, void *);\n\tint (*get_jack_type)(struct snd_soc_component *);\n\tint (*of_xlate_dai_name)(struct snd_soc_component *, const struct of_phandle_args *, const char **);\n\tint (*of_xlate_dai_id)(struct snd_soc_component *, struct device_node *);\n\tvoid (*seq_notifier)(struct snd_soc_component *, enum snd_soc_dapm_type, int);\n\tint (*stream_event)(struct snd_soc_component *, int);\n\tint (*set_bias_level)(struct snd_soc_component *, enum snd_soc_bias_level);\n\tint (*open)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*close)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*ioctl)(struct snd_soc_component *, struct snd_pcm_substream *, unsigned int, void *);\n\tint (*hw_params)(struct snd_soc_component *, struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_soc_component *, struct snd_pcm_substream *, int);\n\tint (*sync_stop)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tsnd_pcm_uframes_t (*pointer)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tint (*get_time_info)(struct snd_soc_component *, struct snd_pcm_substream *, struct timespec64 *, struct timespec64 *, struct snd_pcm_audio_tstamp_config *, struct snd_pcm_audio_tstamp_report *);\n\tint (*copy)(struct snd_soc_component *, struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\tstruct page * (*page)(struct snd_soc_component *, struct snd_pcm_substream *, long unsigned int);\n\tint (*mmap)(struct snd_soc_component *, struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tsnd_pcm_sframes_t (*delay)(struct snd_soc_component *, struct snd_pcm_substream *);\n\tconst struct snd_compress_ops *compress_ops;\n\tint probe_order;\n\tint remove_order;\n\tenum snd_soc_trigger_order trigger_start;\n\tenum snd_soc_trigger_order trigger_stop;\n\tunsigned int module_get_upon_open: 1;\n\tunsigned int idle_bias_on: 1;\n\tunsigned int suspend_bias_off: 1;\n\tunsigned int use_pmdown_time: 1;\n\tunsigned int endianness: 1;\n\tunsigned int legacy_dai_naming: 1;\n\tconst char *ignore_machine;\n\tconst char *topology_name_prefix;\n\tint (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *, struct snd_pcm_hw_params *);\n\tbool use_dai_pcm_id;\n\tint be_pcm_base;\n\tconst char *debugfs_prefix;\n};\n\nstruct snd_soc_compr_ops {\n\tint (*startup)(struct snd_compr_stream *);\n\tvoid (*shutdown)(struct snd_compr_stream *);\n\tint (*set_params)(struct snd_compr_stream *);\n};\n\nstruct snd_soc_dai_stream {\n\tstruct snd_soc_dapm_widget *widget;\n\tunsigned int active;\n\tunsigned int tdm_mask;\n\tvoid *dma_data;\n};\n\nstruct snd_soc_dai_driver;\n\nstruct snd_soc_dai {\n\tconst char *name;\n\tint id;\n\tstruct device *dev;\n\tstruct snd_soc_dai_driver *driver;\n\tstruct snd_soc_dai_stream stream[2];\n\tunsigned int symmetric_rate;\n\tunsigned int symmetric_channels;\n\tunsigned int symmetric_sample_bits;\n\tstruct snd_soc_component *component;\n\tstruct list_head list;\n\tstruct snd_pcm_substream *mark_startup;\n\tstruct snd_pcm_substream *mark_hw_params;\n\tstruct snd_pcm_substream *mark_trigger;\n\tstruct snd_compr_stream *mark_compr_startup;\n\tunsigned int probed: 1;\n\tvoid *priv;\n};\n\nstruct snd_soc_dobj_control {\n\tstruct snd_kcontrol *kcontrol;\n\tchar **dtexts;\n\tlong unsigned int *dvalues;\n};\n\nstruct snd_soc_dobj_widget {\n\tunsigned int *kcontrol_type;\n};\n\nstruct snd_soc_dobj {\n\tenum snd_soc_dobj_type type;\n\tunsigned int index;\n\tstruct list_head list;\n\tint (*unload)(struct snd_soc_component *, struct snd_soc_dobj *);\n\tunion {\n\t\tstruct snd_soc_dobj_control control;\n\t\tstruct snd_soc_dobj_widget widget;\n\t};\n\tvoid *private;\n};\n\nstruct snd_soc_pcm_stream {\n\tconst char *stream_name;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int rates;\n\tunsigned int rate_min;\n\tunsigned int rate_max;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\tunsigned int sig_bits;\n};\n\nstruct snd_soc_dai_ops;\n\nstruct snd_soc_dai_driver {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int base;\n\tstruct snd_soc_dobj dobj;\n\tconst struct of_phandle_args *dai_args;\n\tconst struct snd_soc_dai_ops *ops;\n\tconst struct snd_soc_cdai_ops *cops;\n\tstruct snd_soc_pcm_stream capture;\n\tstruct snd_soc_pcm_stream playback;\n\tunsigned int symmetric_rate: 1;\n\tunsigned int symmetric_channels: 1;\n\tunsigned int symmetric_sample_bits: 1;\n};\n\nstruct snd_soc_dai_link_ch_map;\n\nstruct snd_soc_ops;\n\nstruct snd_soc_dai_link {\n\tconst char *name;\n\tconst char *stream_name;\n\tstruct snd_soc_dai_link_component *cpus;\n\tunsigned int num_cpus;\n\tstruct snd_soc_dai_link_component *codecs;\n\tunsigned int num_codecs;\n\tstruct snd_soc_dai_link_ch_map *ch_maps;\n\tstruct snd_soc_dai_link_component *platforms;\n\tunsigned int num_platforms;\n\tint id;\n\tconst struct snd_soc_pcm_stream *c2c_params;\n\tunsigned int num_c2c_params;\n\tunsigned int dai_fmt;\n\tenum snd_soc_dpcm_trigger trigger[2];\n\tint (*init)(struct snd_soc_pcm_runtime *);\n\tvoid (*exit)(struct snd_soc_pcm_runtime *);\n\tint (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *, struct snd_pcm_hw_params *);\n\tconst struct snd_soc_ops *ops;\n\tconst struct snd_soc_compr_ops *compr_ops;\n\tenum snd_soc_trigger_order trigger_start;\n\tenum snd_soc_trigger_order trigger_stop;\n\tunsigned int nonatomic: 1;\n\tunsigned int playback_only: 1;\n\tunsigned int capture_only: 1;\n\tunsigned int ignore_suspend: 1;\n\tunsigned int symmetric_rate: 1;\n\tunsigned int symmetric_channels: 1;\n\tunsigned int symmetric_sample_bits: 1;\n\tunsigned int no_pcm: 1;\n\tunsigned int dynamic: 1;\n\tunsigned int dpcm_merged_format: 1;\n\tunsigned int dpcm_merged_chan: 1;\n\tunsigned int dpcm_merged_rate: 1;\n\tunsigned int ignore_pmdown_time: 1;\n\tunsigned int ignore: 1;\n};\n\nstruct snd_soc_dai_link_ch_map {\n\tunsigned int cpu;\n\tunsigned int codec;\n\tunsigned int ch_mask;\n};\n\nstruct snd_soc_dai_ops {\n\tint (*probe)(struct snd_soc_dai *);\n\tint (*remove)(struct snd_soc_dai *);\n\tint (*compress_new)(struct snd_soc_pcm_runtime *);\n\tint (*pcm_new)(struct snd_soc_pcm_runtime *, struct snd_soc_dai *);\n\tint (*set_sysclk)(struct snd_soc_dai *, int, unsigned int, int);\n\tint (*set_pll)(struct snd_soc_dai *, int, int, unsigned int, unsigned int);\n\tint (*set_clkdiv)(struct snd_soc_dai *, int, int);\n\tint (*set_bclk_ratio)(struct snd_soc_dai *, unsigned int);\n\tint (*set_fmt)(struct snd_soc_dai *, unsigned int);\n\tint (*xlate_tdm_slot_mask)(unsigned int, unsigned int *, unsigned int *);\n\tint (*set_tdm_slot)(struct snd_soc_dai *, unsigned int, unsigned int, int, int);\n\tint (*set_channel_map)(struct snd_soc_dai *, unsigned int, const unsigned int *, unsigned int, const unsigned int *);\n\tint (*get_channel_map)(const struct snd_soc_dai *, unsigned int *, unsigned int *, unsigned int *, unsigned int *);\n\tint (*set_tristate)(struct snd_soc_dai *, int);\n\tint (*set_stream)(struct snd_soc_dai *, void *, int);\n\tvoid * (*get_stream)(struct snd_soc_dai *, int);\n\tint (*mute_stream)(struct snd_soc_dai *, int, int);\n\tint (*startup)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tvoid (*shutdown)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *, struct snd_soc_dai *);\n\tint (*hw_free)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tint (*prepare)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tint (*trigger)(struct snd_pcm_substream *, int, struct snd_soc_dai *);\n\tsnd_pcm_sframes_t (*delay)(struct snd_pcm_substream *, struct snd_soc_dai *);\n\tconst u64 *auto_selectable_formats;\n\tint num_auto_selectable_formats;\n\tint probe_order;\n\tint remove_order;\n\tunsigned int no_capture_mute: 1;\n\tunsigned int mute_unmute_on_trigger: 1;\n};\n\nstruct snd_soc_dapm_context {\n\tenum snd_soc_bias_level bias_level;\n\tbool idle_bias;\n\tstruct snd_soc_component *component;\n\tstruct snd_soc_card *card;\n\tenum snd_soc_bias_level target_bias_level;\n\tstruct list_head list;\n\tstruct snd_soc_dapm_widget *wcache_sink;\n\tstruct snd_soc_dapm_widget *wcache_source;\n\tstruct dentry *debugfs_dapm;\n};\n\nstruct snd_soc_dapm_path {\n\tconst char *name;\n\tunion {\n\t\tstruct {\n\t\t\tstruct snd_soc_dapm_widget *source;\n\t\t\tstruct snd_soc_dapm_widget *sink;\n\t\t};\n\t\tstruct snd_soc_dapm_widget *node[2];\n\t};\n\tu32 connect: 1;\n\tu32 walking: 1;\n\tu32 is_supply: 1;\n\tint (*connected)(struct snd_soc_dapm_widget *, struct snd_soc_dapm_widget *);\n\tstruct list_head list_node[2];\n\tstruct list_head list_kcontrol;\n\tstruct list_head list;\n};\n\nstruct snd_soc_dapm_pinctrl_priv {\n\tconst char *active_state;\n\tconst char *sleep_state;\n};\n\nstruct snd_soc_dapm_route {\n\tconst char *sink;\n\tconst char *control;\n\tconst char *source;\n\tint (*connected)(struct snd_soc_dapm_widget *, struct snd_soc_dapm_widget *);\n\tstruct snd_soc_dobj dobj;\n};\n\nstruct snd_soc_dapm_update {\n\tstruct snd_kcontrol *kcontrol;\n\tint reg;\n\tint mask;\n\tint val;\n\tint reg2;\n\tint mask2;\n\tint val2;\n\tbool has_second_set;\n};\n\nstruct snd_soc_dapm_widget {\n\tenum snd_soc_dapm_type id;\n\tconst char *name;\n\tconst char *sname;\n\tstruct list_head list;\n\tstruct snd_soc_dapm_context *dapm;\n\tvoid *priv;\n\tstruct regulator *regulator;\n\tstruct pinctrl *pinctrl;\n\tint reg;\n\tunsigned char shift;\n\tunsigned int mask;\n\tunsigned int on_val;\n\tunsigned int off_val;\n\tunsigned char power: 1;\n\tunsigned char active: 1;\n\tunsigned char connected: 1;\n\tunsigned char new: 1;\n\tunsigned char force: 1;\n\tunsigned char ignore_suspend: 1;\n\tunsigned char new_power: 1;\n\tunsigned char power_checked: 1;\n\tunsigned char is_supply: 1;\n\tunsigned char is_ep: 2;\n\tunsigned char no_wname_in_kcontrol_name: 1;\n\tint subseq;\n\tint (*power_check)(struct snd_soc_dapm_widget *);\n\tshort unsigned int event_flags;\n\tint (*event)(struct snd_soc_dapm_widget *, struct snd_kcontrol *, int);\n\tint num_kcontrols;\n\tconst struct snd_kcontrol_new *kcontrol_news;\n\tstruct snd_kcontrol **kcontrols;\n\tstruct snd_soc_dobj dobj;\n\tstruct list_head edges[2];\n\tstruct list_head work_list;\n\tstruct list_head power_list;\n\tstruct list_head dirty;\n\tint endpoints[2];\n\tstruct clk *clk;\n\tint channel;\n};\n\nstruct snd_soc_dapm_widget_list {\n\tint num_widgets;\n\tstruct snd_soc_dapm_widget *widgets[0];\n};\n\nstruct snd_soc_dpcm {\n\tstruct snd_soc_pcm_runtime *be;\n\tstruct snd_soc_pcm_runtime *fe;\n\tenum snd_soc_dpcm_link_state state;\n\tstruct list_head list_be;\n\tstruct list_head list_fe;\n\tstruct dentry *debugfs_state;\n};\n\nstruct snd_soc_dpcm_runtime {\n\tstruct list_head be_clients;\n\tstruct list_head fe_clients;\n\tint users;\n\tstruct snd_pcm_hw_params hw_params;\n\tenum snd_soc_dpcm_update runtime_update;\n\tenum snd_soc_dpcm_state state;\n\tint trigger_pending;\n\tint be_start;\n\tint be_pause;\n\tbool fe_pause;\n};\n\nstruct snd_soc_jack {\n\tstruct mutex mutex;\n\tstruct snd_jack *jack;\n\tstruct snd_soc_card *card;\n\tstruct list_head pins;\n\tint status;\n\tstruct blocking_notifier_head notifier;\n\tstruct list_head jack_zones;\n};\n\nstruct snd_soc_jack_gpio {\n\tunsigned int idx;\n\tstruct device *gpiod_dev;\n\tconst char *name;\n\tint report;\n\tint invert;\n\tint debounce_time;\n\tbool wake;\n\tstruct snd_soc_jack *jack;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notifier;\n\tstruct gpio_desc *desc;\n\tvoid *data;\n\tint (*jack_status_check)(void *);\n};\n\nstruct snd_soc_jack_pin {\n\tstruct list_head list;\n\tconst char *pin;\n\tint mask;\n\tbool invert;\n};\n\nstruct snd_soc_jack_zone {\n\tunsigned int min_mv;\n\tunsigned int max_mv;\n\tunsigned int jack_type;\n\tunsigned int debounce_time;\n\tstruct list_head list;\n};\n\nstruct snd_soc_ops {\n\tint (*startup)(struct snd_pcm_substream *);\n\tvoid (*shutdown)(struct snd_pcm_substream *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_pcm_substream *, int);\n};\n\nstruct snd_soc_pcm_runtime {\n\tstruct device *dev;\n\tstruct snd_soc_card *card;\n\tstruct snd_soc_dai_link *dai_link;\n\tstruct snd_pcm_ops ops;\n\tunsigned int c2c_params_select;\n\tstruct snd_soc_dpcm_runtime dpcm[2];\n\tstruct snd_soc_dapm_widget *c2c_widget[2];\n\tlong int pmdown_time;\n\tstruct snd_pcm *pcm;\n\tstruct snd_compr *compr;\n\tstruct snd_soc_dai **dais;\n\tstruct delayed_work delayed_work;\n\tvoid (*close_delayed_work_func)(struct snd_soc_pcm_runtime *);\n\tstruct dentry *debugfs_dpcm_root;\n\tunsigned int id;\n\tstruct list_head list;\n\tstruct snd_pcm_substream *mark_startup;\n\tstruct snd_pcm_substream *mark_hw_params;\n\tstruct snd_pcm_substream *mark_trigger;\n\tstruct snd_compr_stream *mark_compr_startup;\n\tunsigned int pop_wait: 1;\n\tunsigned int fe_compr: 1;\n\tunsigned int initialized: 1;\n\tint num_components;\n\tstruct snd_soc_component *components[0];\n};\n\nstruct snd_timer_hardware {\n\tunsigned int flags;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tlong unsigned int ticks;\n\tint (*open)(struct snd_timer *);\n\tint (*close)(struct snd_timer *);\n\tlong unsigned int (*c_resolution)(struct snd_timer *);\n\tint (*start)(struct snd_timer *);\n\tint (*stop)(struct snd_timer *);\n\tint (*set_period)(struct snd_timer *, long unsigned int, long unsigned int);\n\tint (*precise_resolution)(struct snd_timer *, long unsigned int *, long unsigned int *);\n};\n\nstruct snd_timer {\n\tint tmr_class;\n\tstruct snd_card *card;\n\tstruct module *module;\n\tint tmr_device;\n\tint tmr_subdevice;\n\tchar id[64];\n\tchar name[80];\n\tunsigned int flags;\n\tint running;\n\tlong unsigned int sticks;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer *);\n\tstruct snd_timer_hardware hw;\n\tspinlock_t lock;\n\tstruct list_head device_list;\n\tstruct list_head open_list_head;\n\tstruct list_head active_list_head;\n\tstruct list_head ack_list_head;\n\tstruct list_head sack_list_head;\n\tstruct work_struct task_work;\n\tint max_instances;\n\tint num_instances;\n};\n\nstruct snd_timer_id {\n\tint dev_class;\n\tint dev_sclass;\n\tint card;\n\tint device;\n\tint subdevice;\n};\n\nstruct snd_timer_ginfo {\n\tstruct snd_timer_id tid;\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tunsigned int clients;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gparams {\n\tstruct snd_timer_id tid;\n\tlong unsigned int period_num;\n\tlong unsigned int period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gparams32 {\n\tstruct snd_timer_id tid;\n\tu32 period_num;\n\tu32 period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gstatus {\n\tstruct snd_timer_id tid;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_num;\n\tlong unsigned int resolution_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_info {\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_info32 {\n\tu32 flags;\n\ts32 card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tu32 reserved0;\n\tu32 resolution;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_instance {\n\tstruct snd_timer *timer;\n\tchar *owner;\n\tunsigned int flags;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer_instance *);\n\tvoid (*callback)(struct snd_timer_instance *, long unsigned int, long unsigned int);\n\tvoid (*ccallback)(struct snd_timer_instance *, int, struct timespec64 *, long unsigned int);\n\tvoid (*disconnect)(struct snd_timer_instance *);\n\tvoid *callback_data;\n\tlong unsigned int ticks;\n\tlong unsigned int cticks;\n\tlong unsigned int pticks;\n\tlong unsigned int resolution;\n\tlong unsigned int lost;\n\tint slave_class;\n\tunsigned int slave_id;\n\tstruct list_head open_list;\n\tstruct list_head active_list;\n\tstruct list_head ack_list;\n\tstruct list_head slave_list_head;\n\tstruct list_head slave_active_head;\n\tstruct snd_timer_instance *master;\n};\n\nstruct snd_timer_params {\n\tunsigned int flags;\n\tunsigned int ticks;\n\tunsigned int queue_size;\n\tunsigned int reserved0;\n\tunsigned int filter;\n\tunsigned char reserved[60];\n};\n\nstruct snd_timer_read {\n\tunsigned int resolution;\n\tunsigned int ticks;\n};\n\nstruct snd_timer_select {\n\tstruct snd_timer_id id;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_status32 {\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_status64 {\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_system_private {\n\tstruct timer_list tlist;\n\tstruct snd_timer *snd_timer;\n\tlong unsigned int last_expires;\n\tlong unsigned int last_jiffies;\n\tlong unsigned int correction;\n};\n\nstruct snd_timer_tread32 {\n\tint event;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int val;\n};\n\nstruct snd_timer_tread64 {\n\tint event;\n\tu8 pad1[4];\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int val;\n\tu8 pad2[4];\n};\n\nstruct snd_timer_uinfo {\n\t__u64 resolution;\n\tint fd;\n\tunsigned int id;\n\tunsigned char reserved[16];\n};\n\nstruct snd_timer_user {\n\tstruct snd_timer_instance *timeri;\n\tint tread;\n\tlong unsigned int ticks;\n\tlong unsigned int overrun;\n\tint qhead;\n\tint qtail;\n\tint qused;\n\tint queue_size;\n\tbool disconnected;\n\tstruct snd_timer_read *queue;\n\tstruct snd_timer_tread64 *tqueue;\n\tspinlock_t qlock;\n\tlong unsigned int last_resolution;\n\tunsigned int filter;\n\tstruct timespec64 tstamp;\n\twait_queue_head_t qchange_sleep;\n\tstruct snd_fasync *fasync;\n\tstruct mutex ioctl_lock;\n};\n\nstruct snd_xferi {\n\tsnd_pcm_sframes_t result;\n\tvoid *buf;\n\tsnd_pcm_uframes_t frames;\n};\n\nstruct snd_xferi32 {\n\ts32 result;\n\tu32 buf;\n\tu32 frames;\n};\n\nstruct snd_xfern {\n\tsnd_pcm_sframes_t result;\n\tvoid **bufs;\n\tsnd_pcm_uframes_t frames;\n};\n\nstruct snd_xfern32 {\n\ts32 result;\n\tu32 bufs;\n\tu32 frames;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct soc_bytes {\n\tint base;\n\tint num_regs;\n\tu32 mask;\n};\n\nstruct soc_bytes_ext {\n\tint max;\n\tint (*get)(struct snd_kcontrol *, unsigned int *, unsigned int);\n\tint (*put)(struct snd_kcontrol *, const unsigned int *, unsigned int);\n};\n\nstruct soc_device_attribute {\n\tconst char *machine;\n\tconst char *family;\n\tconst char *revision;\n\tconst char *serial_number;\n\tconst char *soc_id;\n\tconst void *data;\n\tconst struct attribute_group *custom_attr_group;\n};\n\nstruct soc_enum {\n\tint reg;\n\tunsigned char shift_l;\n\tunsigned char shift_r;\n\tunsigned int items;\n\tunsigned int mask;\n\tconst char * const *texts;\n\tconst unsigned int *values;\n\tunsigned int autodisable: 1;\n};\n\nstruct soc_mixer_control {\n\tint min;\n\tint max;\n\tint platform_max;\n\tint reg;\n\tint rreg;\n\tunsigned int shift;\n\tunsigned int rshift;\n\tu32 num_channels;\n\tunsigned int sign_bit;\n\tunsigned int invert: 1;\n\tunsigned int autodisable: 1;\n\tunsigned int sdca_q78: 1;\n};\n\nstruct soc_mreg_control {\n\tlong int min;\n\tlong int max;\n\tunsigned int regbase;\n\tunsigned int regcount;\n\tunsigned int nbits;\n\tunsigned int invert;\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sock_xprt {\n\tstruct rpc_xprt xprt;\n\tstruct socket *sock;\n\tstruct sock *inet;\n\tstruct file *file;\n\tstruct {\n\t\tstruct {\n\t\t\t__be32 fraghdr;\n\t\t\t__be32 xid;\n\t\t\t__be32 calldir;\n\t\t};\n\t\tu32 offset;\n\t\tu32 len;\n\t\tlong unsigned int copied;\n\t} recv;\n\tstruct {\n\t\tu32 offset;\n\t} xmit;\n\tlong unsigned int sock_state;\n\tstruct delayed_work connect_worker;\n\tstruct work_struct error_worker;\n\tstruct work_struct recv_worker;\n\tstruct mutex recv_mutex;\n\tstruct completion handshake_done;\n\tstruct __kernel_sockaddr_storage srcaddr;\n\tshort unsigned int srcport;\n\tint xprt_err;\n\tstruct rpc_clnt *clnt;\n\tsize_t rcvsize;\n\tsize_t sndsize;\n\tstruct rpc_timeout tcp_timeout;\n\tvoid (*old_data_ready)(struct sock *);\n\tvoid (*old_state_change)(struct sock *);\n\tvoid (*old_write_space)(struct sock *);\n\tvoid (*old_error_report)(struct sock *);\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 64;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int input_queue_head;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t defer_csd;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct sophgo_pinctrl;\n\nstruct sophgo_pin_mux_config;\n\nstruct sophgo_cfg_ops {\n\tint (*pctrl_init)(struct platform_device *, struct sophgo_pinctrl *);\n\tint (*verify_pinmux_config)(const struct sophgo_pin_mux_config *);\n\tint (*verify_pin_group)(const struct sophgo_pin_mux_config *, unsigned int);\n\tint (*dt_node_to_map_post)(struct device_node *, struct sophgo_pinctrl *, struct sophgo_pin_mux_config *, unsigned int);\n\tint (*compute_pinconf_config)(struct sophgo_pinctrl *, const struct sophgo_pin *, long unsigned int *, unsigned int, u32 *, u32 *);\n\tint (*set_pinconf_config)(struct sophgo_pinctrl *, const struct sophgo_pin *, u32, u32);\n\tvoid (*set_pinmux_config)(struct sophgo_pinctrl *, const struct sophgo_pin *, u32);\n};\n\nstruct sophgo_pin_mux_config {\n\tconst struct sophgo_pin *pin;\n\tu32 config;\n};\n\nstruct sophgo_pinctrl_data;\n\nstruct sophgo_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctrl_dev;\n\tconst struct sophgo_pinctrl_data *data;\n\tstruct pinctrl_desc pdesc;\n\tstruct mutex mutex;\n\traw_spinlock_t lock;\n\tvoid *priv_ctrl;\n};\n\nstruct sophgo_vddio_cfg_ops;\n\nstruct sophgo_pinctrl_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tconst void *pindata;\n\tconst char * const *pdnames;\n\tconst struct sophgo_vddio_cfg_ops *vddio_ops;\n\tconst struct sophgo_cfg_ops *cfg_ops;\n\tconst struct pinctrl_ops *pctl_ops;\n\tconst struct pinmux_ops *pmx_ops;\n\tconst struct pinconf_ops *pconf_ops;\n\tu16 npins;\n\tu16 npds;\n\tu16 pinsize;\n};\n\nstruct sophgo_vddio_cfg_ops {\n\tint (*get_pull_up)(const struct sophgo_pin *, const u32 *);\n\tint (*get_pull_down)(const struct sophgo_pin *, const u32 *);\n\tint (*get_oc_map)(const struct sophgo_pin *, const u32 *, const u32 **);\n\tint (*get_schmitt_map)(const struct sophgo_pin *, const u32 *, const u32 **);\n};\n\nstruct sp_node {\n\tstruct rb_node nd;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct mempolicy *policy;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct spacemit_ccu_adev {\n\tstruct auxiliary_device adev;\n\tstruct regmap *regmap;\n};\n\nstruct spacemit_ccu_data {\n\tconst char *reset_name;\n\tstruct clk_hw **hws;\n\tsize_t num;\n};\n\nstruct spacemit_gpio;\n\nstruct spacemit_gpio_bank {\n\tstruct gpio_generic_chip chip;\n\tstruct spacemit_gpio *sg;\n\tvoid *base;\n\tu32 irq_mask;\n\tu32 irq_rising_edge;\n\tu32 irq_falling_edge;\n};\n\nstruct spacemit_gpio_data;\n\nstruct spacemit_gpio {\n\tstruct device *dev;\n\tconst struct spacemit_gpio_data *data;\n\tstruct spacemit_gpio_bank sgb[4];\n};\n\nstruct spacemit_gpio_data {\n\tconst unsigned int *offsets;\n\tu32 bank_offsets[4];\n};\n\nstruct spacemit_pin {\n\tu16 pin;\n\tu16 flags;\n\tu8 gpiofunc;\n};\n\nstruct spacemit_pin_drv_strength {\n\tu8 val;\n\tu32 mA;\n};\n\nstruct spacemit_pin_mux_config {\n\tconst struct spacemit_pin *pin;\n\tu32 config;\n};\n\nstruct spacemit_pinctrl_data;\n\nstruct spacemit_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl_dev;\n\tconst struct spacemit_pinctrl_data *data;\n\tstruct pinctrl_desc pdesc;\n\tstruct mutex mutex;\n\traw_spinlock_t lock;\n\tvoid *regs;\n\tstruct regmap *regmap_apbc;\n};\n\nstruct spacemit_pinctrl_dconf;\n\nstruct spacemit_pinctrl_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tconst struct spacemit_pin *data;\n\tu16 npins;\n\tunsigned int (*pin_to_offset)(unsigned int);\n\tunsigned int (*pin_to_io_pd_offset)(unsigned int);\n\tconst struct spacemit_pinctrl_dconf *dconf;\n};\n\nstruct spacemit_pinctrl_dconf {\n\tu64 schmitt_mask;\n\tu64 drive_mask;\n\tstruct spacemit_pin_drv_strength *ds_1v8_tbl;\n\tsize_t ds_1v8_tbl_num;\n\tstruct spacemit_pin_drv_strength *ds_3v3_tbl;\n\tsize_t ds_3v3_tbl_num;\n};\n\nstruct spacemit_sdhci_host {\n\tstruct clk *clk_core;\n\tstruct clk *clk_io;\n};\n\nstruct spansion_nor_params {\n\tu8 clsr;\n};\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n};\n\nstruct spi_controller_mem_ops;\n\nstruct spi_controller_mem_caps;\n\nstruct spi_offload_config;\n\nstruct spi_statistics;\n\nstruct spi_controller {\n\tstruct device dev;\n\tstruct list_head list;\n\ts16 bus_num;\n\tu16 num_chipselect;\n\tu16 num_data_lanes;\n\tu16 dma_alignment;\n\tu32 mode_bits;\n\tu32 buswidth_override_bits;\n\tu32 bits_per_word_mask;\n\tu32 min_speed_hz;\n\tu32 max_speed_hz;\n\tu16 flags;\n\tbool devm_allocated;\n\tunion {\n\t\tbool slave;\n\t\tbool target;\n\t};\n\tsize_t (*max_transfer_size)(struct spi_device *);\n\tsize_t (*max_message_size)(struct spi_device *);\n\tstruct mutex io_mutex;\n\tstruct mutex add_lock;\n\tspinlock_t bus_lock_spinlock;\n\tstruct mutex bus_lock_mutex;\n\tbool bus_lock_flag;\n\tint (*setup)(struct spi_device *);\n\tint (*set_cs_timing)(struct spi_device *);\n\tint (*transfer)(struct spi_device *, struct spi_message *);\n\tvoid (*cleanup)(struct spi_device *);\n\tbool (*can_dma)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tstruct device *dma_map_dev;\n\tstruct device *cur_rx_dma_dev;\n\tstruct device *cur_tx_dma_dev;\n\tbool queued;\n\tstruct kthread_worker *kworker;\n\tstruct kthread_work pump_messages;\n\tspinlock_t queue_lock;\n\tstruct list_head queue;\n\tstruct spi_message *cur_msg;\n\tstruct completion cur_msg_completion;\n\tbool cur_msg_incomplete;\n\tbool cur_msg_need_completion;\n\tbool busy;\n\tbool running;\n\tbool rt;\n\tbool auto_runtime_pm;\n\tbool fallback;\n\tbool last_cs_mode_high;\n\ts8 last_cs[4];\n\tu32 last_cs_index_mask: 4;\n\tstruct completion xfer_completion;\n\tsize_t max_dma_len;\n\tint (*optimize_message)(struct spi_message *);\n\tint (*unoptimize_message)(struct spi_message *);\n\tint (*prepare_transfer_hardware)(struct spi_controller *);\n\tint (*transfer_one_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_transfer_hardware)(struct spi_controller *);\n\tint (*prepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*target_abort)(struct spi_controller *);\n\tvoid (*set_cs)(struct spi_device *, bool);\n\tint (*transfer_one)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tvoid (*handle_err)(struct spi_controller *, struct spi_message *);\n\tconst struct spi_controller_mem_ops *mem_ops;\n\tconst struct spi_controller_mem_caps *mem_caps;\n\tbool dtr_caps;\n\tstruct spi_offload * (*get_offload)(struct spi_device *, const struct spi_offload_config *);\n\tvoid (*put_offload)(struct spi_offload *);\n\tstruct gpio_desc **cs_gpiods;\n\tbool use_gpio_descriptors;\n\ts8 unused_native_cs;\n\ts8 max_native_cs;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tvoid *dummy_rx;\n\tvoid *dummy_tx;\n\tint (*fw_translate_cs)(struct spi_controller *, unsigned int);\n\tbool ptp_sts_supported;\n\tlong unsigned int irq_flags;\n\tbool queue_empty;\n\tbool must_async;\n\tbool defer_optimize_message;\n};\n\nstruct spi_controller_mem_caps {\n\tbool dtr;\n\tbool ecc;\n\tbool swap16;\n\tbool per_op_freq;\n};\n\nstruct spi_mem;\n\nstruct spi_mem_op;\n\nstruct spi_mem_dirmap_desc;\n\nstruct spi_controller_mem_ops {\n\tint (*adjust_op_size)(struct spi_mem *, struct spi_mem_op *);\n\tbool (*supports_op)(struct spi_mem *, const struct spi_mem_op *);\n\tint (*exec_op)(struct spi_mem *, const struct spi_mem_op *);\n\tconst char * (*get_name)(struct spi_mem *);\n\tint (*dirmap_create)(struct spi_mem_dirmap_desc *);\n\tvoid (*dirmap_destroy)(struct spi_mem_dirmap_desc *);\n\tssize_t (*dirmap_read)(struct spi_mem_dirmap_desc *, u64, size_t, void *);\n\tssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *, u64, size_t, const void *);\n\tint (*poll_status)(struct spi_mem *, const struct spi_mem_op *, u16, u16, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct spi_device {\n\tstruct device dev;\n\tstruct spi_controller *controller;\n\tu32 max_speed_hz;\n\tu8 bits_per_word;\n\tbool rt;\n\tu32 mode;\n\tint irq;\n\tvoid *controller_state;\n\tvoid *controller_data;\n\tchar modalias[32];\n\tconst char *driver_override;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct spi_delay word_delay;\n\tstruct spi_delay cs_setup;\n\tstruct spi_delay cs_hold;\n\tstruct spi_delay cs_inactive;\n\tu8 chip_select[4];\n\tu8 num_chipselect;\n\tu32 cs_index_mask: 4;\n\tstruct gpio_desc *cs_gpiod[4];\n\tu8 tx_lane_map[8];\n\tu8 num_tx_lanes;\n\tu8 rx_lane_map[8];\n\tu8 num_rx_lanes;\n};\n\nstruct spi_device_id {\n\tchar name[32];\n\tkernel_ulong_t driver_data;\n};\n\nstruct spi_driver {\n\tconst struct spi_device_id *id_table;\n\tint (*probe)(struct spi_device *);\n\tvoid (*remove)(struct spi_device *);\n\tvoid (*shutdown)(struct spi_device *);\n\tstruct device_driver driver;\n};\n\nstruct spi_mem {\n\tstruct spi_device *spi;\n\tvoid *drvpriv;\n\tconst char *name;\n};\n\nstruct spi_mem_op {\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tu16 opcode;\n\t} cmd;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tu64 val;\n\t} addr;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t} dummy;\n\tstruct {\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 ecc: 1;\n\t\tu8 swap16: 1;\n\t\tu8 __pad: 5;\n\t\tenum spi_mem_data_dir dir;\n\t\tunsigned int nbytes;\n\t\tunion {\n\t\t\tvoid *in;\n\t\t\tconst void *out;\n\t\t} buf;\n\t} data;\n\tunsigned int max_freq;\n};\n\nstruct spi_mem_dirmap_info {\n\tstruct spi_mem_op op_tmpl;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct spi_mem_dirmap_desc {\n\tstruct spi_mem *mem;\n\tstruct spi_mem_dirmap_info info;\n\tunsigned int nodirmap;\n\tvoid *priv;\n};\n\nstruct spi_mem_driver {\n\tstruct spi_driver spidrv;\n\tint (*probe)(struct spi_mem *);\n\tint (*remove)(struct spi_mem *);\n\tvoid (*shutdown)(struct spi_mem *);\n};\n\nstruct spi_nor_rww {\n\twait_queue_head_t wait;\n\tbool ongoing_io;\n\tbool ongoing_rd;\n\tbool ongoing_pe;\n\tunsigned int used_banks;\n};\n\nstruct spi_nor_manufacturer;\n\nstruct spi_nor_controller_ops;\n\nstruct spi_nor_flash_parameter;\n\nstruct spi_nor {\n\tstruct mtd_info mtd;\n\tstruct mutex lock;\n\tstruct spi_nor_rww rww;\n\tstruct device *dev;\n\tstruct spi_mem *spimem;\n\tu8 *bouncebuf;\n\tsize_t bouncebuf_size;\n\tu8 *id;\n\tconst struct flash_info *info;\n\tconst struct spi_nor_manufacturer *manufacturer;\n\tu8 addr_nbytes;\n\tu8 erase_opcode;\n\tu8 read_opcode;\n\tu8 read_dummy;\n\tu8 program_opcode;\n\tenum spi_nor_protocol read_proto;\n\tenum spi_nor_protocol write_proto;\n\tenum spi_nor_protocol reg_proto;\n\tbool sst_write_second;\n\tu32 flags;\n\tenum spi_nor_cmd_ext cmd_ext_type;\n\tstruct sfdp *sfdp;\n\tstruct dentry *debugfs_root;\n\tconst struct spi_nor_controller_ops *controller_ops;\n\tstruct spi_nor_flash_parameter *params;\n\tstruct {\n\t\tstruct spi_mem_dirmap_desc *rdesc;\n\t\tstruct spi_mem_dirmap_desc *wdesc;\n\t} dirmap;\n\tvoid *priv;\n};\n\nstruct spi_nor_controller_ops {\n\tint (*prepare)(struct spi_nor *);\n\tvoid (*unprepare)(struct spi_nor *);\n\tint (*read_reg)(struct spi_nor *, u8, u8 *, size_t);\n\tint (*write_reg)(struct spi_nor *, u8, const u8 *, size_t);\n\tssize_t (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tssize_t (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*erase)(struct spi_nor *, loff_t);\n};\n\nstruct spi_nor_erase_command {\n\tstruct list_head list;\n\tu32 count;\n\tu32 size;\n\tu8 opcode;\n};\n\nstruct spi_nor_erase_region {\n\tu64 offset;\n\tu64 size;\n\tu8 erase_mask;\n\tbool overlaid;\n};\n\nstruct spi_nor_erase_type {\n\tu32 size;\n\tu32 size_shift;\n\tu32 size_mask;\n\tu8 opcode;\n\tu8 idx;\n};\n\nstruct spi_nor_erase_map {\n\tstruct spi_nor_erase_region *regions;\n\tstruct spi_nor_erase_region uniform_region;\n\tstruct spi_nor_erase_type erase_type[4];\n\tunsigned int n_regions;\n};\n\nstruct spi_nor_fixups {\n\tvoid (*default_init)(struct spi_nor *);\n\tint (*post_bfpt)(struct spi_nor *, const struct sfdp_parameter_header *, const struct sfdp_bfpt *);\n\tvoid (*smpt_read_dummy)(const struct spi_nor *, u8 *);\n\tvoid (*smpt_map_id)(const struct spi_nor *, u8 *);\n\tint (*post_sfdp)(struct spi_nor *);\n\tint (*late_init)(struct spi_nor *);\n};\n\nstruct spi_nor_hwcaps {\n\tu32 mask;\n};\n\nstruct spi_nor_read_command {\n\tu8 num_mode_clocks;\n\tu8 num_wait_states;\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_pp_command {\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_otp_ops;\n\nstruct spi_nor_otp {\n\tconst struct spi_nor_otp_organization *org;\n\tconst struct spi_nor_otp_ops *ops;\n};\n\nstruct spi_nor_locking_ops;\n\nstruct spi_nor_flash_parameter {\n\tu64 bank_size;\n\tu64 size;\n\tu32 writesize;\n\tu32 page_size;\n\tu8 addr_nbytes;\n\tu8 addr_mode_nbytes;\n\tu8 rdsr_dummy;\n\tu8 rdsr_addr_nbytes;\n\tu8 n_banks;\n\tu8 n_dice;\n\tu8 die_erase_opcode;\n\tu32 *vreg_offset;\n\tstruct spi_nor_hwcaps hwcaps;\n\tstruct spi_nor_read_command reads[16];\n\tstruct spi_nor_pp_command page_programs[8];\n\tstruct spi_nor_erase_map erase_map;\n\tstruct spi_nor_otp otp;\n\tint (*set_octal_dtr)(struct spi_nor *, bool);\n\tint (*quad_enable)(struct spi_nor *);\n\tint (*set_4byte_addr_mode)(struct spi_nor *, bool);\n\tint (*ready)(struct spi_nor *);\n\tconst struct spi_nor_locking_ops *locking_ops;\n\tvoid *priv;\n};\n\nstruct spi_nor_id {\n\tconst u8 *bytes;\n\tu8 len;\n};\n\nstruct spi_nor_locking_ops {\n\tint (*lock)(struct spi_nor *, loff_t, u64);\n\tint (*unlock)(struct spi_nor *, loff_t, u64);\n\tint (*is_locked)(struct spi_nor *, loff_t, u64);\n};\n\nstruct spi_nor_manufacturer {\n\tconst char *name;\n\tconst struct flash_info *parts;\n\tunsigned int nparts;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct spi_nor_otp_ops {\n\tint (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tint (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*lock)(struct spi_nor *, unsigned int);\n\tint (*erase)(struct spi_nor *, loff_t);\n\tint (*is_locked)(struct spi_nor *, unsigned int);\n};\n\nstruct spi_nor_otp_organization {\n\tsize_t len;\n\tloff_t base;\n\tloff_t offset;\n\tunsigned int n_regions;\n};\n\nstruct spi_offload_ops;\n\nstruct spi_offload {\n\tstruct device *provider_dev;\n\tvoid *priv;\n\tconst struct spi_offload_ops *ops;\n\tu32 xfer_flags;\n};\n\nstruct spi_offload_config {\n\tu32 capability_flags;\n};\n\nstruct spi_offload_ops {\n\tint (*trigger_enable)(struct spi_offload *);\n\tvoid (*trigger_disable)(struct spi_offload *);\n\tstruct dma_chan * (*tx_stream_request_dma_chan)(struct spi_offload *);\n\tstruct dma_chan * (*rx_stream_request_dma_chan)(struct spi_offload *);\n};\n\nstruct spi_replaced_transfers;\n\ntypedef void (*spi_replaced_release_t)(struct spi_controller *, struct spi_message *, struct spi_replaced_transfers *);\n\nstruct spi_replaced_transfers {\n\tspi_replaced_release_t release;\n\tvoid *extradata;\n\tstruct list_head replaced_transfers;\n\tstruct list_head *replaced_after;\n\tsize_t inserted;\n\tstruct spi_transfer inserted_transfers[0];\n};\n\ntypedef void (*spi_res_release_t)(struct spi_controller *, struct spi_message *, void *);\n\nstruct spi_res {\n\tstruct list_head entry;\n\tspi_res_release_t release;\n\tlong long unsigned int data[0];\n};\n\nstruct spi_statistics {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t messages;\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t timedout;\n\tu64_stats_t spi_sync;\n\tu64_stats_t spi_sync_immediate;\n\tu64_stats_t spi_async;\n\tu64_stats_t bytes;\n\tu64_stats_t bytes_rx;\n\tu64_stats_t bytes_tx;\n\tu64_stats_t transfer_bytes_histo[17];\n\tu64_stats_t transfers_split_maxsize;\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct sr6_tlv {\n\t__u8 type;\n\t__u8 len;\n\t__u8 data[0];\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[0];\n};\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tu64 data[0];\n};\n\nstruct stack_record {\n\tstruct list_head hash_list;\n\tu32 hash;\n\tu32 size;\n\tunion handle_parts handle;\n\trefcount_t count;\n\tunion {\n\t\tlong unsigned int entries[64];\n\t\tstruct {\n\t\t\tstruct list_head free_list;\n\t\t\tlong unsigned int rcu_state;\n\t\t};\n\t};\n};\n\nstruct stackframe {\n\tlong unsigned int fp;\n\tlong unsigned int ra;\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\nstruct starfive_irq_chip {\n\tvoid *base;\n\tstruct irq_domain *domain;\n\traw_spinlock_t lock;\n};\n\nstruct starfive_pinctrl {\n\tstruct gpio_chip gc;\n\tstruct pinctrl_gpio_range gpios;\n\traw_spinlock_t lock;\n\tvoid *base;\n\tvoid *padctl;\n\tstruct pinctrl_dev *pctl;\n\tstruct mutex mutex;\n};\n\nstruct watchdog_info;\n\nstruct watchdog_ops;\n\nstruct watchdog_governor;\n\nstruct watchdog_core_data;\n\nstruct watchdog_device {\n\tint id;\n\tstruct device *parent;\n\tconst struct attribute_group **groups;\n\tconst struct watchdog_info *info;\n\tconst struct watchdog_ops *ops;\n\tconst struct watchdog_governor *gov;\n\tunsigned int bootstatus;\n\tunsigned int timeout;\n\tunsigned int pretimeout;\n\tunsigned int min_timeout;\n\tunsigned int max_timeout;\n\tunsigned int min_hw_heartbeat_ms;\n\tunsigned int max_hw_heartbeat_ms;\n\tstruct notifier_block reboot_nb;\n\tstruct notifier_block restart_nb;\n\tstruct notifier_block pm_nb;\n\tvoid *driver_data;\n\tstruct watchdog_core_data *wd_data;\n\tlong unsigned int status;\n\tstruct list_head deferred;\n};\n\nstruct starfive_wdt_variant;\n\nstruct starfive_wdt {\n\tstruct watchdog_device wdd;\n\tspinlock_t lock;\n\tvoid *base;\n\tstruct clk *core_clk;\n\tstruct clk *apb_clk;\n\tconst struct starfive_wdt_variant *variant;\n\tlong unsigned int freq;\n\tu32 count;\n\tu32 reload;\n};\n\nstruct starfive_wdt_variant {\n\tunsigned int control;\n\tunsigned int load;\n\tunsigned int reload;\n\tunsigned int enable;\n\tunsigned int value;\n\tunsigned int int_clr;\n\tunsigned int unlock;\n\tunsigned int int_status;\n\tu32 unlock_key;\n\tchar enrst_shift;\n\tchar en_shift;\n\tbool intclr_check;\n\tchar intclr_ava_shift;\n\tbool double_timeout;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\tlong unsigned int st_dev;\n\tlong unsigned int st_ino;\n\tunsigned int st_mode;\n\tunsigned int st_nlink;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tlong unsigned int st_rdev;\n\tlong unsigned int __pad1;\n\tlong int st_size;\n\tint st_blksize;\n\tint __pad2;\n\tlong int st_blocks;\n\tlong int st_atime;\n\tlong unsigned int st_atime_nsec;\n\tlong int st_mtime;\n\tlong unsigned int st_mtime_nsec;\n\tlong int st_ctime;\n\tlong unsigned int st_ctime_nsec;\n\tunsigned int __unused4;\n\tunsigned int __unused5;\n};\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct tracer_stat;\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct statfs {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__kernel_long_t f_blocks;\n\t__kernel_long_t f_bfree;\n\t__kernel_long_t f_bavail;\n\t__kernel_long_t f_files;\n\t__kernel_long_t f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct statfs64 {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct static_call_key {\n\tvoid *func;\n};\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\nstruct summary_data {\n\tstruct seq_file *s;\n\tstruct regulator_dev *parent;\n\tint level;\n};\n\nstruct summary_lock_data {\n\tstruct ww_acquire_ctx *ww_ctx;\n\tstruct regulator_dev **new_contended_rdev;\n\tstruct regulator_dev **old_contended_rdev;\n};\n\nstruct sun20i_ppu_desc {\n\tconst char * const *names;\n\tunsigned int num_domains;\n};\n\nstruct sun20i_ppu_pd {\n\tstruct generic_pm_domain genpd;\n\tvoid *base;\n};\n\nstruct sun20i_regulator_data {\n\tconst struct regulator_desc *descs;\n\tunsigned int ndescs;\n};\n\nstruct sun50i_iommu {\n\tstruct iommu_device iommu;\n\tspinlock_t iommu_lock;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct reset_control *reset;\n\tstruct clk *clk;\n\tstruct iommu_domain *domain;\n\tstruct kmem_cache *pt_pool;\n};\n\nstruct sun50i_iommu_domain {\n\tstruct iommu_domain domain;\n\trefcount_t refcnt;\n\tu32 *dt;\n\tdma_addr_t dt_dma;\n\tstruct sun50i_iommu *iommu;\n};\n\nstruct sun6i_msgbox {\n\tstruct mbox_controller controller;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tvoid *regs;\n};\n\nstruct sun6i_rtc_clk_data {\n\tlong unsigned int rc_osc_rate;\n\tunsigned int fixed_prescaler: 16;\n\tunsigned int has_prescaler: 1;\n\tunsigned int has_out_clk: 1;\n\tunsigned int has_losc_en: 1;\n\tunsigned int has_auto_swt: 1;\n};\n\nstruct sun6i_rtc_dev {\n\tstruct rtc_device *rtc;\n\tconst struct sun6i_rtc_clk_data *data;\n\tvoid *base;\n\tint irq;\n\ttime64_t alarm;\n\tlong unsigned int flags;\n\tstruct clk_hw hw;\n\tstruct clk_hw *int_osc;\n\tstruct clk *losc;\n\tstruct clk *ext_losc;\n\tspinlock_t lock;\n};\n\nstruct sun6i_rtc_match_data {\n\tbool have_ext_osc32k: 1;\n\tbool have_iosc_calibration: 1;\n\tbool rtc_32k_single_parent: 1;\n\tconst struct clk_parent_data *osc32k_fanout_parents;\n\tu8 osc32k_fanout_nparents;\n};\n\nstruct sun6i_spi_cfg;\n\nstruct sun6i_spi {\n\tstruct spi_controller *host;\n\tvoid *base_addr;\n\tdma_addr_t dma_addr_rx;\n\tdma_addr_t dma_addr_tx;\n\tstruct clk *hclk;\n\tstruct clk *mclk;\n\tstruct reset_control *rstc;\n\tstruct completion done;\n\tstruct completion dma_rx_done;\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tint len;\n\tconst struct sun6i_spi_cfg *cfg;\n};\n\nstruct sun6i_spi_cfg {\n\tlong unsigned int fifo_depth;\n\tbool has_clk_ctl;\n\tu32 mode_bits;\n};\n\nstruct sunrpc_net {\n\tstruct proc_dir_entry *proc_net_rpc;\n\tstruct cache_detail *ip_map_cache;\n\tstruct cache_detail *unix_gid_cache;\n\tstruct cache_detail *rsc_cache;\n\tstruct cache_detail *rsi_cache;\n\tstruct super_block *pipefs_sb;\n\tstruct rpc_pipe *gssd_dummy;\n\tstruct mutex pipefs_sb_lock;\n\tstruct list_head all_clients;\n\tspinlock_t rpc_client_lock;\n\tstruct rpc_clnt *rpcb_local_clnt;\n\tstruct rpc_clnt *rpcb_local_clnt4;\n\tspinlock_t rpcb_clnt_lock;\n\tunsigned int rpcb_users;\n\tunsigned int rpcb_is_af_local: 1;\n\tstruct mutex gssp_lock;\n\tstruct rpc_clnt *gssp_clnt;\n\tint use_gss_proxy;\n\tint pipe_version;\n\tatomic_t pipe_users;\n\tstruct proc_dir_entry *use_gssp_proc;\n\tstruct proc_dir_entry *gss_krb5_enctypes;\n};\n\nstruct sunxi_ccu_desc;\n\nstruct sunxi_ccu {\n\tconst struct sunxi_ccu_desc *desc;\n\tspinlock_t lock;\n\tstruct ccu_reset reset;\n};\n\nstruct sunxi_ccu_desc {\n\tstruct ccu_common___2 **ccu_clks;\n\tlong unsigned int num_ccu_clks;\n\tstruct clk_hw_onecell_data *hw_clks;\n\tconst struct ccu_reset_map *resets;\n\tlong unsigned int num_resets;\n};\n\nstruct sunxi_desc_function {\n\tlong unsigned int variant;\n\tconst char *name;\n\tu8 muxval;\n\tu8 irqbank;\n\tu8 irqnum;\n};\n\nstruct sunxi_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tlong unsigned int variant;\n\tstruct sunxi_desc_function *functions;\n};\n\nstruct sunxi_idma_des {\n\t__le32 config;\n\t__le32 buf_size;\n\t__le32 buf_addr_ptr1;\n\t__le32 buf_addr_ptr2;\n};\n\nstruct sunxi_mmc_clk_delay;\n\nstruct sunxi_mmc_cfg {\n\tu32 idma_des_size_bits;\n\tu32 idma_des_shift;\n\tconst struct sunxi_mmc_clk_delay *clk_delays;\n\tbool can_calibrate;\n\tbool mask_data0;\n\tbool needs_new_timings;\n\tbool ccu_has_timings_switch;\n};\n\nstruct sunxi_mmc_clk_delay {\n\tu32 output;\n\tu32 sample;\n};\n\nstruct sunxi_mmc_host {\n\tstruct device *dev;\n\tstruct mmc_host *mmc;\n\tstruct reset_control *reset;\n\tconst struct sunxi_mmc_cfg *cfg;\n\tvoid *reg_base;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_mmc;\n\tstruct clk *clk_sample;\n\tstruct clk *clk_output;\n\tspinlock_t lock;\n\tint irq;\n\tu32 int_sum;\n\tu32 sdio_imask;\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tbool wait_dma;\n\tstruct mmc_request *mrq;\n\tstruct mmc_request *manual_stop_mrq;\n\tint ferror;\n\tbool vqmmc_enabled;\n\tbool use_new_timings;\n};\n\nstruct sunxi_pck600;\n\nstruct sunxi_pck600_pd {\n\tstruct generic_pm_domain genpd;\n\tstruct sunxi_pck600 *pck;\n\tvoid *base;\n};\n\nstruct sunxi_pck600 {\n\tstruct device *dev;\n\tstruct genpd_onecell_data genpd_data;\n\tstruct sunxi_pck600_pd pds[0];\n};\n\nstruct sunxi_pck600_desc {\n\tconst char * const *pd_names;\n\tunsigned int num_domains;\n\tu32 logic_power_switch0_delay_offset;\n\tu32 logic_power_switch1_delay_offset;\n\tu32 off2on_delay_offset;\n\tu32 device_ctrl0_delay;\n\tu32 device_ctrl1_delay;\n\tu32 logic_power_switch0_delay;\n\tu32 logic_power_switch1_delay;\n\tu32 off2on_delay;\n};\n\nstruct sunxi_pinctrl_regulator {\n\tstruct regulator *regulator;\n\trefcount_t refcount;\n};\n\nstruct sunxi_pinctrl_desc;\n\nstruct sunxi_pinctrl_function;\n\nstruct sunxi_pinctrl_group;\n\nstruct sunxi_pinctrl {\n\tvoid *membase;\n\tstruct gpio_chip *chip;\n\tconst struct sunxi_pinctrl_desc *desc;\n\tstruct device *dev;\n\tstruct sunxi_pinctrl_regulator regulators[11];\n\tstruct irq_domain *domain;\n\tstruct sunxi_pinctrl_function *functions;\n\tunsigned int nfunctions;\n\tstruct sunxi_pinctrl_group *groups;\n\tunsigned int ngroups;\n\tint *irq;\n\tunsigned int *irq_array;\n\traw_spinlock_t lock;\n\tstruct pinctrl_dev *pctl_dev;\n\tlong unsigned int variant;\n\tu32 bank_mem_size;\n\tu32 pull_regs_offset;\n\tu32 dlevel_field_width;\n\tu32 pow_mod_sel_offset;\n};\n\nstruct sunxi_pinctrl_desc {\n\tconst struct sunxi_desc_pin *pins;\n\tint npins;\n\tunsigned int pin_base;\n\tunsigned int irq_banks;\n\tconst unsigned int *irq_bank_map;\n\tbool irq_read_needs_mux;\n\tbool disable_strict_mode;\n\tenum sunxi_desc_bias_voltage io_bias_cfg_variant;\n};\n\nstruct sunxi_pinctrl_function {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct sunxi_pinctrl_group {\n\tconst char *name;\n\tunsigned int pin;\n};\n\nstruct sunxi_sid {\n\tvoid *base;\n\tu32 value_offset;\n};\n\nstruct sunxi_sid_cfg {\n\tu32 value_offset;\n\tu32 size;\n\tbool need_register_readout;\n};\n\nstruct sunxi_sram_func;\n\nstruct sunxi_sram_data {\n\tchar *name;\n\tu8 reg;\n\tu8 offset;\n\tu8 width;\n\tstruct sunxi_sram_func *func;\n};\n\nstruct sunxi_sram_desc {\n\tstruct sunxi_sram_data data;\n\tbool claimed;\n};\n\nstruct sunxi_sram_func {\n\tchar *func;\n\tu8 val;\n\tu32 reg_val;\n};\n\nstruct sunxi_sramc_variant {\n\tint num_emac_clocks;\n\tbool has_ldo_ctrl;\n\tbool has_ths_offset;\n};\n\nstruct sunxi_wdt_reg;\n\nstruct sunxi_wdt_dev {\n\tstruct watchdog_device wdt_dev;\n\tvoid *wdt_base;\n\tconst struct sunxi_wdt_reg *wdt_regs;\n};\n\nstruct sunxi_wdt_reg {\n\tu8 wdt_ctrl;\n\tu8 wdt_cfg;\n\tu8 wdt_mode;\n\tu8 wdt_timeout_shift;\n\tu8 wdt_reset_mask;\n\tu8 wdt_reset_val;\n\tu32 wdt_key_val;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tvoid *s_security;\n\tconst struct xattr_handler * const *s_xattr;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct superblock_security_struct {\n\tu32 sid;\n\tu32 def_sid;\n\tu32 mntpoint_sid;\n\tu32 creator_sid;\n\tshort unsigned int behavior;\n\tshort unsigned int flags;\n\tstruct mutex lock;\n\tstruct list_head isec_head;\n\tspinlock_t isec_lock;\n};\n\nstruct supplier_bindings {\n\tstruct device_node * (*parse_prop)(struct device_node *, const char *, int);\n\tstruct device_node * (*get_con_dev)(struct device_node *);\n\tbool optional;\n\tu8 fwlink_flags;\n};\n\nstruct suspend_context {\n\tstruct pt_regs regs;\n\tlong unsigned int envcfg;\n\tlong unsigned int tvec;\n\tlong unsigned int ie;\n\tlong unsigned int satp;\n\tlong unsigned int stimecmp;\n};\n\nstruct suspend_stats {\n\tunsigned int step_failures[8];\n\tunsigned int success;\n\tunsigned int fail;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tu64 last_hw_sleep;\n\tu64 total_hw_sleep;\n\tu64 max_hw_sleep;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nstruct svc_cred {\n\tkuid_t cr_uid;\n\tkgid_t cr_gid;\n\tstruct group_info *cr_group_info;\n\tu32 cr_flavor;\n\tchar *cr_raw_principal;\n\tchar *cr_principal;\n\tchar *cr_targ_princ;\n\tstruct gss_api_mech *cr_gss_mech;\n};\n\nstruct svc_deferred_req {\n\tu32 prot;\n\tstruct svc_xprt *xprt;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tstruct __kernel_sockaddr_storage daddr;\n\tsize_t daddrlen;\n\tvoid *xprt_ctxt;\n\tstruct cache_deferred_req handle;\n\tint argslen;\n\t__be32 args[0];\n};\n\nstruct svc_info {\n\tstruct svc_serv *serv;\n\tstruct mutex *mutex;\n};\n\nstruct svc_pool {\n\tunsigned int sp_id;\n\tunsigned int sp_nrthreads;\n\tunsigned int sp_nrthrmin;\n\tunsigned int sp_nrthrmax;\n\tstruct lwq sp_xprts;\n\tstruct list_head sp_all_threads;\n\tstruct llist_head sp_idle_threads;\n\tstruct percpu_counter sp_messages_arrived;\n\tstruct percpu_counter sp_sockets_queued;\n\tstruct percpu_counter sp_threads_woken;\n\tlong unsigned int sp_flags;\n};\n\nstruct svc_pool_map {\n\tint count;\n\tint mode;\n\tunsigned int npools;\n\tunsigned int *pool_to;\n\tunsigned int *to_pool;\n};\n\nstruct svc_procedure {\n\t__be32 (*pc_func)(struct svc_rqst *);\n\tbool (*pc_decode)(struct svc_rqst *, struct xdr_stream *);\n\tbool (*pc_encode)(struct svc_rqst *, struct xdr_stream *);\n\tvoid (*pc_release)(struct svc_rqst *);\n\tunsigned int pc_argsize;\n\tunsigned int pc_argzero;\n\tunsigned int pc_ressize;\n\tunsigned int pc_cachetype;\n\tunsigned int pc_xdrressize;\n\tconst char *pc_name;\n};\n\nstruct svc_process_info {\n\tunion {\n\t\tint (*dispatch)(struct svc_rqst *);\n\t\tstruct {\n\t\t\tunsigned int lovers;\n\t\t\tunsigned int hivers;\n\t\t} mismatch;\n\t};\n};\n\nstruct svc_version;\n\nstruct svc_program {\n\tu32 pg_prog;\n\tunsigned int pg_lovers;\n\tunsigned int pg_hivers;\n\tunsigned int pg_nvers;\n\tconst struct svc_version **pg_vers;\n\tchar *pg_name;\n\tchar *pg_class;\n\tenum svc_auth_status (*pg_authenticate)(struct svc_rqst *);\n\t__be32 (*pg_init_request)(struct svc_rqst *, const struct svc_program *, struct svc_process_info *);\n\tint (*pg_rpcbind_set)(struct net *, const struct svc_program *, u32, int, short unsigned int, short unsigned int);\n};\n\nstruct xdr_stream {\n\t__be32 *p;\n\tstruct xdr_buf *buf;\n\t__be32 *end;\n\tstruct kvec *iov;\n\tstruct kvec scratch;\n\tstruct page **page_ptr;\n\tvoid *page_kaddr;\n\tunsigned int nwords;\n\tstruct rpc_rqst *rqst;\n};\n\nstruct svc_rqst {\n\tstruct list_head rq_all;\n\tstruct llist_node rq_idle;\n\tstruct callback_head rq_rcu_head;\n\tstruct svc_xprt *rq_xprt;\n\tstruct __kernel_sockaddr_storage rq_addr;\n\tsize_t rq_addrlen;\n\tstruct __kernel_sockaddr_storage rq_daddr;\n\tsize_t rq_daddrlen;\n\tstruct svc_serv *rq_server;\n\tstruct svc_pool *rq_pool;\n\tconst struct svc_procedure *rq_procinfo;\n\tstruct auth_ops *rq_authop;\n\tstruct svc_cred rq_cred;\n\tvoid *rq_xprt_ctxt;\n\tstruct svc_deferred_req *rq_deferred;\n\tstruct xdr_buf rq_arg;\n\tstruct xdr_stream rq_arg_stream;\n\tstruct xdr_stream rq_res_stream;\n\tstruct folio *rq_scratch_folio;\n\tstruct xdr_buf rq_res;\n\tlong unsigned int rq_maxpages;\n\tstruct page **rq_pages;\n\tstruct page **rq_respages;\n\tstruct page **rq_next_page;\n\tstruct page **rq_page_end;\n\tstruct folio_batch rq_fbatch;\n\tstruct bio_vec *rq_bvec;\n\t__be32 rq_xid;\n\tu32 rq_prog;\n\tu32 rq_vers;\n\tu32 rq_proc;\n\tu32 rq_prot;\n\tint rq_cachetype;\n\tlong unsigned int rq_flags;\n\tktime_t rq_qtime;\n\tvoid *rq_argp;\n\tvoid *rq_resp;\n\t__be32 *rq_accept_statp;\n\tvoid *rq_auth_data;\n\t__be32 rq_auth_stat;\n\tint rq_auth_slack;\n\tint rq_reserved;\n\tktime_t rq_stime;\n\tstruct cache_req rq_chandle;\n\tstruct auth_domain *rq_client;\n\tstruct auth_domain *rq_gssclient;\n\tstruct task_struct *rq_task;\n\tstruct net *rq_bc_net;\n\tint rq_err;\n\tlong unsigned int bc_to_initval;\n\tunsigned int bc_to_retries;\n\tunsigned int rq_status_counter;\n\tvoid **rq_lease_breaker;\n};\n\nstruct svc_stat;\n\nstruct svc_serv {\n\tstruct svc_program *sv_programs;\n\tstruct svc_stat *sv_stats;\n\tspinlock_t sv_lock;\n\tunsigned int sv_nprogs;\n\tunsigned int sv_nrthreads;\n\tunsigned int sv_max_payload;\n\tunsigned int sv_max_mesg;\n\tunsigned int sv_xdrsize;\n\tstruct list_head sv_permsocks;\n\tstruct list_head sv_tempsocks;\n\tint sv_tmpcnt;\n\tstruct timer_list sv_temptimer;\n\tchar *sv_name;\n\tunsigned int sv_nrpools;\n\tbool sv_is_pooled;\n\tstruct svc_pool *sv_pools;\n\tint (*sv_threadfn)(void *);\n\tstruct lwq sv_cb_list;\n\tbool sv_bc_enabled;\n};\n\nstruct svc_xprt_class;\n\nstruct svc_xprt_ops;\n\nstruct svc_xprt {\n\tstruct svc_xprt_class *xpt_class;\n\tconst struct svc_xprt_ops *xpt_ops;\n\tstruct kref xpt_ref;\n\tktime_t xpt_qtime;\n\tstruct list_head xpt_list;\n\tstruct lwq_node xpt_ready;\n\tlong unsigned int xpt_flags;\n\tstruct svc_serv *xpt_server;\n\tatomic_t xpt_reserved;\n\tatomic_t xpt_nr_rqsts;\n\tstruct mutex xpt_mutex;\n\tspinlock_t xpt_lock;\n\tvoid *xpt_auth_cache;\n\tstruct list_head xpt_deferred;\n\tstruct __kernel_sockaddr_storage xpt_local;\n\tsize_t xpt_locallen;\n\tstruct __kernel_sockaddr_storage xpt_remote;\n\tsize_t xpt_remotelen;\n\tchar xpt_remotebuf[58];\n\tstruct list_head xpt_users;\n\tstruct net *xpt_net;\n\tnetns_tracker ns_tracker;\n\tconst struct cred *xpt_cred;\n\tstruct rpc_xprt *xpt_bc_xprt;\n\tstruct rpc_xprt_switch *xpt_bc_xps;\n};\n\nstruct svc_sock {\n\tstruct svc_xprt sk_xprt;\n\tstruct socket *sk_sock;\n\tstruct sock *sk_sk;\n\tvoid (*sk_ostate)(struct sock *);\n\tvoid (*sk_odata)(struct sock *);\n\tvoid (*sk_owspace)(struct sock *);\n\tstruct bio_vec *sk_bvec;\n\t__be32 sk_marker;\n\tu32 sk_tcplen;\n\tu32 sk_datalen;\n\tstruct page_frag_cache sk_frag_cache;\n\tstruct completion sk_handshake_done;\n\tlong unsigned int sk_maxpages;\n\tstruct page *sk_pages[0];\n};\n\nstruct svc_stat {\n\tstruct svc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcbadfmt;\n\tunsigned int rpcbadauth;\n\tunsigned int rpcbadclnt;\n};\n\nstruct svc_version {\n\tu32 vs_vers;\n\tu32 vs_nproc;\n\tconst struct svc_procedure *vs_proc;\n\tlong unsigned int *vs_count;\n\tu32 vs_xdrsize;\n\tbool vs_hidden;\n\tbool vs_rpcb_optnl;\n\tbool vs_need_cong_ctrl;\n\tint (*vs_dispatch)(struct svc_rqst *);\n};\n\nstruct svc_xprt_class {\n\tconst char *xcl_name;\n\tstruct module *xcl_owner;\n\tconst struct svc_xprt_ops *xcl_ops;\n\tstruct list_head xcl_list;\n\tu32 xcl_max_payload;\n\tint xcl_ident;\n};\n\nstruct svc_xprt_ops {\n\tstruct svc_xprt * (*xpo_create)(struct svc_serv *, struct net *, struct sockaddr *, int, int);\n\tstruct svc_xprt * (*xpo_accept)(struct svc_xprt *);\n\tint (*xpo_has_wspace)(struct svc_xprt *);\n\tint (*xpo_recvfrom)(struct svc_rqst *);\n\tint (*xpo_sendto)(struct svc_rqst *);\n\tint (*xpo_result_payload)(struct svc_rqst *, unsigned int, unsigned int);\n\tvoid (*xpo_release_ctxt)(struct svc_xprt *, void *);\n\tvoid (*xpo_detach)(struct svc_xprt *);\n\tvoid (*xpo_free)(struct svc_xprt *);\n\tvoid (*xpo_kill_temp_xprt)(struct svc_xprt *);\n\tvoid (*xpo_handshake)(struct svc_xprt *);\n};\n\nstruct svc_xpt_user {\n\tstruct list_head list;\n\tvoid (*callback)(struct svc_xpt_user *);\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cgroup {\n\tatomic_t ids;\n};\n\nstruct swap_cgroup_ctrl {\n\tstruct swap_cgroup *map;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[1];\n\tstruct list_head frag_clusters[1];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[1];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[256];\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n};\n\nstruct swmii_regs {\n\tu16 bmsr;\n\tu16 lpa;\n\tu16 lpagb;\n\tu16 estat;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct swoc_info {\n\t__u8 rev;\n\t__u8 reserved[8];\n\t__u16 LinuxSKU;\n\t__u16 LinuxVer;\n\t__u8 reserved2[47];\n} __attribute__((packed));\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tbool pt_port_open;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct sync_fence_info {\n\tchar obj_name[32];\n\tchar driver_name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u64 timestamp_ns;\n};\n\nstruct sync_file {\n\tstruct file *file;\n\tchar user_name[32];\n\tstruct list_head sync_file_list;\n\twait_queue_head_t wq;\n\tlong unsigned int flags;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct sync_file_info {\n\tchar name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u32 num_fences;\n\t__u32 pad;\n\t__u64 sync_fence_info;\n};\n\nstruct sync_merge_data {\n\tchar name[32];\n\t__s32 fd2;\n\t__s32 fence;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct sync_set_deadline {\n\t__u64 deadline_ns;\n\t__u64 pad;\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_user_dispatch {\n\tchar *selector;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tbool on_dispatch;\n};\n\nstruct syscon {\n\tstruct device_node *np;\n\tstruct regmap *regmap;\n\tstruct reset_control *reset;\n\tstruct list_head list;\n};\n\nstruct syscon_poweroff_data {\n\tstruct regmap *map;\n\tu32 offset;\n\tu32 value;\n\tu32 mask;\n};\n\nstruct syscon_reboot_context {\n\tstruct regmap *map;\n\tconst struct reboot_data *rd;\n\tstruct reboot_mode_bits catchall;\n\tstruct notifier_block restart_handler;\n};\n\nstruct syscore_ops;\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysfb_display_info {\n\tstruct screen_info screen;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysfs_wi_group {\n\tstruct kobject wi_kobj;\n\tstruct mutex kobj_lock;\n\tstruct iw_node_attr *nattrs[0];\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[0];\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct table_header {\n\tu16 td_id;\n\tu16 td_flags;\n\tu32 td_hilen;\n\tu32 td_lolen;\n\tchar td_data[0];\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t load_avg;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_numa_env {\n\tstruct task_struct *p;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tint imb_numa_nr;\n\tstruct numa_stats src_stats;\n\tstruct numa_stats dst_stats;\n\tint imbalance_pct;\n\tint dist;\n\tstruct task_struct *best_task;\n\tlong int best_imp;\n\tint best_cpu;\n};\n\nstruct task_security_struct {\n\tstruct {\n\t\tu32 sid;\n\t\tu32 seqno;\n\t\tunsigned int dir_spot;\n\t\tstruct avdc_entry dir[4];\n\t\tbool permissive_neveraudit;\n\t} avdcache;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct thread_info {\n\tlong unsigned int flags;\n\tint preempt_count;\n\tlong int kernel_sp;\n\tlong int user_sp;\n\tint cpu;\n\tlong unsigned int syscall_work;\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {\n\tstruct arch_tlbflush_unmap_batch arch;\n\tbool flush_required;\n\tbool writable;\n};\n\nstruct thread_struct {\n\tlong unsigned int ra;\n\tlong unsigned int sp;\n\tlong unsigned int s[12];\n\tstruct __riscv_d_ext_state fstate;\n\tlong unsigned int bad_cause;\n\tlong unsigned int envcfg;\n\tlong unsigned int sum;\n\tu32 riscv_v_flags;\n\tu32 vstate_ctrl;\n\tstruct __riscv_v_ext_state vstate;\n\tlong unsigned int align_ctl;\n\tstruct __riscv_v_ext_state kernel_vstate;\n\tbool force_icache_flush;\n\tunsigned int prev_cpu;\n};\n\nstruct uprobe_task;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct task_group *sched_task_group;\n\tstruct callback_head sched_throttle_work;\n\tstruct list_head throttle_node;\n\tbool throttled;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_statistics stats;\n\tstruct hlist_head preempt_notifiers;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tlong unsigned int rcu_tasks_nvcsw;\n\tu8 rcu_tasks_holdout;\n\tu8 rcu_tasks_idx;\n\tint rcu_tasks_idle_cpu;\n\tstruct list_head rcu_tasks_holdout_list;\n\tint rcu_tasks_exit_cpu;\n\tstruct list_head rcu_tasks_exit_list;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int brk_randomized: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int use_memdelay: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct posix_cputimers_work posix_cputimers_work;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct audit_context *audit_context;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct compat_robust_list_head *compat_robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tu8 perf_recursion[4];\n\tstruct perf_event_context *perf_event_ctxp;\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct perf_ctx_data *perf_ctx_data;\n\tstruct mempolicy *mempolicy;\n\tshort int il_prev;\n\tu8 il_weight;\n\tshort int pref_node_fork;\n\tint numa_scan_seq;\n\tunsigned int numa_scan_period;\n\tunsigned int numa_scan_period_max;\n\tint numa_preferred_nid;\n\tlong unsigned int numa_migrate_retry;\n\tu64 node_stamp;\n\tu64 last_task_numa_placement;\n\tu64 last_sum_exec_runtime;\n\tstruct callback_head numa_work;\n\tstruct numa_group *numa_group;\n\tlong unsigned int *numa_faults;\n\tlong unsigned int total_numa_faults;\n\tlong unsigned int numa_faults_locality[3];\n\tlong unsigned int numa_pages_migrated;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tlong unsigned int trace_recursion;\n\tunsigned int memcg_nr_pages_over_high;\n\tstruct mem_cgroup *active_memcg;\n\tstruct obj_cgroup *objcg;\n\tstruct gendisk *throttle_disk;\n\tstruct uprobe_task *utask;\n\tstruct kmap_ctrl kmap_ctrl;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\tstruct vm_struct *stack_vm_area;\n\trefcount_t stack_refcount;\n\tvoid *security;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tstruct thread_struct thread;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tstruct tcf_t tcfa_tm;\n\tlong: 64;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_bind_class_args {\n\tstruct qdisc_walker w;\n\tlong unsigned int new_cl;\n\tu32 portid;\n\tu32 clid;\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_fifo_qopt {\n\t__u32 limit;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_fifo_qopt_offload {\n\tenum tc_fifo_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t};\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_mqprio_qopt {\n\t__u8 num_tc;\n\t__u8 prio_tc_map[16];\n\t__u8 hw;\n\t__u16 count[16];\n\t__u16 offset[16];\n};\n\nstruct tc_mqprio_qopt_offload {\n\tstruct tc_mqprio_qopt qopt;\n\tstruct netlink_ext_ack *extack;\n\tu16 mode;\n\tu16 shaper;\n\tu32 flags;\n\tu64 min_rate[16];\n\tu64 max_rate[16];\n\tlong unsigned int preemptible_tcs;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_root_qopt_offload {\n\tenum tc_root_command command;\n\tu32 handle;\n\tbool ingress;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tc_taprio_qopt_stats {\n\tu64 window_drops;\n\tu64 tx_overruns;\n};\n\nstruct tc_taprio_qopt_queue_stats {\n\tint queue;\n\tstruct tc_taprio_qopt_stats stats;\n};\n\nstruct tc_taprio_sched_entry {\n\tu8 command;\n\tu32 gate_mask;\n\tu32 interval;\n};\n\nstruct tc_taprio_qopt_offload {\n\tenum tc_taprio_qopt_cmd cmd;\n\tunion {\n\t\tstruct tc_taprio_qopt_stats stats;\n\t\tstruct tc_taprio_qopt_queue_stats queue_stats;\n\t\tstruct {\n\t\t\tstruct tc_mqprio_qopt_offload mqprio;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t\tktime_t base_time;\n\t\t\tu64 cycle_time;\n\t\t\tu64 cycle_time_extension;\n\t\t\tu32 max_sdu[16];\n\t\t\tsize_t num_entries;\n\t\t\tstruct tc_taprio_sched_entry entries[0];\n\t\t};\n\t};\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcf_bind_args {\n\tstruct tcf_walker w;\n\tlong unsigned int base;\n\tlong unsigned int cl;\n\tu32 classid;\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\ntypedef void tcf_chain_head_change_t(struct tcf_proto *, void *);\n\nstruct tcf_block_ext_info {\n\tenum flow_block_binder_type binder_type;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n\tu32 block_index;\n};\n\nstruct tcf_block_owner_item {\n\tstruct list_head list;\n\tstruct Qdisc *q;\n\tenum flow_block_binder_type binder_type;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_chain_info {\n\tstruct tcf_proto **pprev;\n\tstruct tcf_proto *next;\n};\n\nstruct tcf_dump_args {\n\tstruct tcf_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct tcf_block *block;\n\tstruct Qdisc *q;\n\tu32 parent;\n\tbool terse_dump;\n};\n\nstruct tcf_exts {\n\tint action;\n\tint police;\n};\n\nunion tcf_exts_miss_cookie {\n\tstruct {\n\t\tu32 miss_cookie_base;\n\t\tu32 act_index;\n\t};\n\tu64 miss_cookie;\n};\n\nstruct tcf_exts_miss_cookie_node {\n\tconst struct tcf_chain *chain;\n\tconst struct tcf_proto *tp;\n\tconst struct tcf_exts *exts;\n\tu32 chain_index;\n\tu32 tp_prio;\n\tu32 handle;\n\tu32 miss_cookie_base;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_filter_chain_list_item {\n\tstruct list_head list;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_net {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t};\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 ae: 1;\n\t__u16 res1: 3;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpa_event {\n\tu32 pcr_index;\n\tu32 event_type;\n\tu8 pcr_value[20];\n\tu32 event_size;\n\tu8 event_data[0];\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n};\n\nstruct td {\n\t__hc32 hwINFO;\n\t__hc32 hwCBP;\n\t__hc32 hwNextTD;\n\t__hc32 hwBE;\n\t__hc16 hwPSW[2];\n\t__u8 index;\n\tstruct ed *ed;\n\tstruct td *td_hash;\n\tstruct td *next_dl_td;\n\tstruct urb *urb;\n\tdma_addr_t td_dma;\n\tdma_addr_t data_dma;\n\tstruct list_head td_list;\n\tlong: 64;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[8];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct th1520_pad_group {\n\tconst char *name;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n};\n\nstruct th1520_pinctrl {\n\tstruct pinctrl_desc desc;\n\tstruct mutex mutex;\n\traw_spinlock_t lock;\n\tvoid *base;\n\tstruct pinctrl_dev *pctl;\n};\n\nstruct th1520_plat_data {\n\tstruct ccu_common___3 **th1520_pll_clks;\n\tstruct ccu_common___3 **th1520_div_clks;\n\tstruct ccu_mux___2 **th1520_mux_clks;\n\tstruct ccu_gate **th1520_gate_clks;\n\tint nr_clks;\n\tint nr_pll_clks;\n\tint nr_div_clks;\n\tint nr_mux_clks;\n\tint nr_gate_clks;\n};\n\nstruct thermal_attr {\n\tstruct device_attribute attr;\n\tchar name[20];\n};\n\ntypedef struct thermal_cooling_device *class_cooling_dev_t;\n\nstruct thermal_cooling_device {\n\tint id;\n\tconst char *type;\n\tlong unsigned int max_state;\n\tstruct device device;\n\tstruct device_node *np;\n\tvoid *devdata;\n\tvoid *stats;\n\tconst struct thermal_cooling_device_ops *ops;\n\tbool updated;\n\tstruct mutex lock;\n\tstruct list_head thermal_instances;\n\tstruct list_head node;\n};\n\nstruct thermal_trip;\n\nstruct thermal_governor {\n\tconst char *name;\n\tint (*bind_to_tz)(struct thermal_zone_device *);\n\tvoid (*unbind_from_tz)(struct thermal_zone_device *);\n\tvoid (*trip_crossed)(struct thermal_zone_device *, const struct thermal_trip *, bool);\n\tvoid (*manage)(struct thermal_zone_device *);\n\tvoid (*update_tz)(struct thermal_zone_device *, enum thermal_notify_event);\n\tstruct list_head governor_list;\n};\n\nstruct thermal_hwmon_attr {\n\tstruct device_attribute attr;\n\tchar name[16];\n};\n\nstruct thermal_hwmon_device {\n\tchar type[20];\n\tstruct device *device;\n\tint count;\n\tstruct list_head tz_list;\n\tstruct list_head node;\n};\n\nstruct thermal_hwmon_temp {\n\tstruct list_head hwmon_node;\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_hwmon_attr temp_input;\n\tstruct thermal_hwmon_attr temp_crit;\n};\n\nstruct thermal_instance {\n\tint id;\n\tchar name[20];\n\tstruct thermal_cooling_device *cdev;\n\tconst struct thermal_trip *trip;\n\tbool initialized;\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tlong unsigned int target;\n\tchar attr_name[20];\n\tstruct device_attribute attr;\n\tchar weight_attr_name[20];\n\tstruct device_attribute weight_attr;\n\tstruct list_head trip_node;\n\tstruct list_head cdev_node;\n\tunsigned int weight;\n\tbool upper_no_limit;\n};\n\nstruct thermal_trip {\n\tint temperature;\n\tint hysteresis;\n\tenum thermal_trip_type type;\n\tu8 flags;\n\tvoid *priv;\n};\n\nstruct thermal_trip_attrs {\n\tstruct thermal_attr type;\n\tstruct thermal_attr temp;\n\tstruct thermal_attr hyst;\n};\n\nstruct thermal_trip_desc {\n\tstruct thermal_trip trip;\n\tstruct thermal_trip_attrs trip_attrs;\n\tstruct list_head list_node;\n\tstruct list_head thermal_instances;\n\tint threshold;\n};\n\ntypedef struct thermal_zone_device *class_thermal_zone_reverse_t;\n\ntypedef struct thermal_zone_device *class_thermal_zone_t;\n\nstruct thermal_zone_device_ops {\n\tbool (*should_bind)(struct thermal_zone_device *, const struct thermal_trip *, struct thermal_cooling_device *, struct cooling_spec *);\n\tint (*get_temp)(struct thermal_zone_device *, int *);\n\tint (*set_trips)(struct thermal_zone_device *, int, int);\n\tint (*change_mode)(struct thermal_zone_device *, enum thermal_device_mode);\n\tint (*set_trip_temp)(struct thermal_zone_device *, const struct thermal_trip *, int);\n\tint (*get_crit_temp)(struct thermal_zone_device *, int *);\n\tint (*set_emul_temp)(struct thermal_zone_device *, int);\n\tint (*get_trend)(struct thermal_zone_device *, const struct thermal_trip *, enum thermal_trend *);\n\tvoid (*hot)(struct thermal_zone_device *);\n\tvoid (*critical)(struct thermal_zone_device *);\n};\n\nstruct thermal_zone_params;\n\nstruct thermal_zone_device {\n\tint id;\n\tchar type[20];\n\tstruct device device;\n\tstruct completion removal;\n\tstruct completion resume;\n\tstruct attribute_group trips_attribute_group;\n\tstruct list_head trips_high;\n\tstruct list_head trips_reached;\n\tstruct list_head trips_invalid;\n\tenum thermal_device_mode mode;\n\tvoid *devdata;\n\tint num_trips;\n\tlong unsigned int passive_delay_jiffies;\n\tlong unsigned int polling_delay_jiffies;\n\tlong unsigned int recheck_delay_jiffies;\n\tint temperature;\n\tint last_temperature;\n\tint emul_temperature;\n\tint passive;\n\tint prev_low_trip;\n\tint prev_high_trip;\n\tstruct thermal_zone_device_ops ops;\n\tstruct thermal_zone_params *tzp;\n\tstruct thermal_governor *governor;\n\tvoid *governor_data;\n\tstruct ida ida;\n\tstruct mutex lock;\n\tstruct list_head node;\n\tstruct delayed_work poll_queue;\n\tenum thermal_notify_event notify_event;\n\tu8 state;\n\tstruct list_head user_thresholds;\n\tstruct thermal_trip_desc trips[0];\n};\n\nstruct thermal_zone_params {\n\tconst char *governor_name;\n\tbool no_hwmon;\n\tu32 sustainable_power;\n\ts32 k_po;\n\ts32 k_pu;\n\ts32 k_i;\n\ts32 k_d;\n\ts32 integral_cutoff;\n\tint slope;\n\tint offset;\n};\n\nstruct thread_deferred_req {\n\tstruct cache_deferred_req handle;\n\tstruct completion completion;\n};\n\nstruct throtl_service_queue {\n\tstruct throtl_service_queue *parent_sq;\n\tstruct list_head queued[2];\n\tunsigned int nr_queued_bps[2];\n\tunsigned int nr_queued_iops[2];\n\tstruct rb_root_cached pending_tree;\n\tunsigned int nr_pending;\n\tlong unsigned int first_pending_disptime;\n\tstruct timer_list pending_timer;\n};\n\nstruct throtl_data {\n\tstruct throtl_service_queue service_queue;\n\tstruct request_queue *queue;\n\tunsigned int nr_queued[2];\n\tstruct work_struct dispatch_work;\n};\n\nstruct throtl_grp;\n\nstruct throtl_qnode {\n\tstruct list_head node;\n\tstruct bio_list bios_bps;\n\tstruct bio_list bios_iops;\n\tstruct throtl_grp *tg;\n};\n\nstruct throtl_grp {\n\tstruct blkg_policy_data pd;\n\tstruct rb_node rb_node;\n\tstruct throtl_data *td;\n\tstruct throtl_service_queue service_queue;\n\tstruct throtl_qnode qnode_on_self[2];\n\tstruct throtl_qnode qnode_on_parent[2];\n\tlong unsigned int disptime;\n\tunsigned int flags;\n\tbool has_rules_bps[2];\n\tbool has_rules_iops[2];\n\tuint64_t bps[2];\n\tunsigned int iops[2];\n\tint64_t bytes_disp[2];\n\tint io_disp[2];\n\tlong unsigned int last_check_time;\n\tlong unsigned int slice_start[2];\n\tlong unsigned int slice_end[2];\n\tstruct blkg_rwstat stat_bytes;\n\tstruct blkg_rwstat stat_ios;\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[9];\n\tstruct hlist_head vectors[576];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_of {\n\tunsigned int flags;\n\tstruct device_node *np;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct clock_event_device clkevt;\n\tstruct of_timer_base of_base;\n\tstruct of_timer_irq of_irq;\n\tstruct of_timer_clk of_clk;\n\tvoid *private_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timerlat_entry {\n\tstruct trace_entry ent;\n\tunsigned int seqnum;\n\tint context;\n\tu64 timer_latency;\n};\n\nstruct timers_private {\n\tstruct pid *pid;\n\tstruct task_struct *task;\n\tstruct pid_namespace *ns;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tstruct tk_read_base base[2];\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\ntypedef void (*tls_done_func_t)(void *, int, key_serial_t);\n\nstruct tls_handshake_args {\n\tstruct socket *ta_sock;\n\ttls_done_func_t ta_done;\n\tvoid *ta_data;\n\tconst char *ta_peername;\n\tunsigned int ta_timeout_ms;\n\tkey_serial_t ta_keyring;\n\tkey_serial_t ta_my_cert;\n\tkey_serial_t ta_my_privkey;\n\tunsigned int ta_num_peerids;\n\tkey_serial_t ta_my_peerids[5];\n};\n\nstruct tls_handshake_req {\n\tvoid (*th_consumer_done)(void *, int, key_serial_t);\n\tvoid *th_consumer_data;\n\tint th_type;\n\tunsigned int th_timeout_ms;\n\tint th_auth_mode;\n\tconst char *th_peername;\n\tkey_serial_t th_keyring;\n\tkey_serial_t th_certificate;\n\tkey_serial_t th_privkey;\n\tunsigned int th_num_peerids;\n\tkey_serial_t th_peerid[5];\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tu64 now;\n\tbool check;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnl_ptk_info {\n\tlong unsigned int flags[1];\n\t__be16 proto;\n\t__be32 key;\n\t__be32 seq;\n\tint hdr_len;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nstruct tp_transition_snapshot {\n\tlong unsigned int rcu;\n\tlong unsigned int srcu_gp;\n\tbool ongoing;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct trace_module_delta;\n\nstruct trace_pid_list;\n\nstruct tracer_flags;\n\nstruct trace_options;\n\nstruct trace_func_repeats;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tstruct array_buffer array_buffer;\n\tunsigned int mapped;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_size;\n\tchar *range_name;\n\tlong int text_delta;\n\tstruct trace_module_delta *module_delta;\n\tvoid *scratch;\n\tint scratch_size;\n\tint buffer_disabled;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tstruct tracer_flags *current_trace_flags;\n\tu64 trace_flags;\n\tunsigned char trace_flags_index[64];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tconst char *system_names;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct eventfs_inode *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct list_head marker_list;\n\tstruct list_head tracers;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tcpumask_var_t pipe_cpumask;\n\tint ref;\n\tint trace_ref;\n\tstruct list_head mod_events;\n\tint no_filter_buffering_ref;\n\tunsigned int syscall_buf_sz;\n\tstruct list_head hist_vars;\n\tstruct trace_func_repeats *last_func_repeats;\n\tbool ring_buffer_expanded;\n};\n\nstruct trace_array_cpu {\n\tlocal_t disabled;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tbool ignore_pid;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\ntypedef struct trace_buffer *class_ring_buffer_nest_t;\n\nstruct trace_buffer {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tatomic_t resizing;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)(void);\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_end;\n\tstruct ring_buffer_meta *meta;\n\tunsigned int subbuf_size;\n\tunsigned int subbuf_order;\n\tunsigned int max_data_size;\n};\n\nstruct trace_buffer_meta {\n\t__u32 meta_page_size;\n\t__u32 meta_struct_len;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tstruct {\n\t\t__u64 lost_events;\n\t\t__u32 id;\n\t\t__u32 read;\n\t} reader;\n\t__u64 flags;\n\t__u64 entries;\n\t__u64 overrun;\n\t__u64 read;\n\t__u64 Reserved1;\n\t__u64 Reserved2;\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct trace_probe_event;\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_entry_arg *entry_arg;\n\tstruct probe_arg args[0];\n};\n\nstruct trace_eprobe {\n\tconst char *event_system;\n\tconst char *event_name;\n\tchar *filter_str;\n\tstruct trace_event_call *event;\n\tstruct dyn_event devent;\n\tstruct trace_probe tp;\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tunsigned int trace_ctx;\n\tstruct pt_regs *regs;\n};\n\nstruct trace_event_class;\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tconst char *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tunion {\n\t\tvoid *module;\n\t\tatomic_t refcnt;\n\t};\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct trace_event_fields;\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_event_data_offsets_9p_client_req {};\n\nstruct trace_event_data_offsets_9p_client_res {};\n\nstruct trace_event_data_offsets_9p_fid_ref {};\n\nstruct trace_event_data_offsets_9p_protocol_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_alarm_class {};\n\nstruct trace_event_data_offsets_alarmtimer_suspend {};\n\nstruct trace_event_data_offsets_alloc_vmap_area {};\n\nstruct trace_event_data_offsets_ata_bmdma_status {};\n\nstruct trace_event_data_offsets_ata_eh_action_template {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy_qc {};\n\nstruct trace_event_data_offsets_ata_exec_command_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_begin_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_end_template {};\n\nstruct trace_event_data_offsets_ata_port_eh_begin_template {};\n\nstruct trace_event_data_offsets_ata_qc_complete_template {};\n\nstruct trace_event_data_offsets_ata_qc_issue_template {};\n\nstruct trace_event_data_offsets_ata_sff_hsm_template {};\n\nstruct trace_event_data_offsets_ata_sff_template {};\n\nstruct trace_event_data_offsets_ata_tf_load {};\n\nstruct trace_event_data_offsets_ata_transfer_data_template {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_bl_ext_tree_prepare_commit {};\n\nstruct trace_event_data_offsets_blkdev_zone_mgmt {};\n\nstruct trace_event_data_offsets_block_bio {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_completion {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_zwplug {};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\nstruct trace_event_data_offsets_bpf_trace_printk {\n\tu32 bpf_string;\n\tconst void *bpf_string_ptr_;\n};\n\nstruct trace_event_data_offsets_bpf_trigger_tp {};\n\nstruct trace_event_data_offsets_bpf_xdp_link_attach_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_add {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_external_learn_add {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_update {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_mdb_full {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cap_capable {};\n\nstruct trace_event_data_offsets_cdev_update {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tconst void *dst_path_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_rstat {};\n\nstruct trace_event_data_offsets_clk {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_duty_cycle {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_parent {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 pname;\n\tconst void *pname_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_phase {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate_range {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate_request {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 pname;\n\tconst void *pname_ptr_;\n};\n\nstruct trace_event_data_offsets_compact_retry {};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_contention_begin {};\n\nstruct trace_event_data_offsets_contention_end {};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_cpu_idle_miss {};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_csd_function {};\n\nstruct trace_event_data_offsets_csd_queue_cpu {};\n\nstruct trace_event_data_offsets_ctime {};\n\nstruct trace_event_data_offsets_ctime_ns_xchg {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_devfreq_frequency {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devfreq_monitor {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_end {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_start {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 parent;\n\tconst void *parent_ptr_;\n\tu32 pm_ops;\n\tconst void *pm_ops_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_recover_aborted {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_reporter_state_update {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwerr {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwmsg {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_trap_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 trap_name;\n\tconst void *trap_name_ptr_;\n\tu32 trap_group_name;\n\tconst void *trap_group_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devres {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_attach_dev {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_fd {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence_unsignaled {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg_err {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_single {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 addrs;\n\tconst void *addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dql_stall_detected {};\n\nstruct trace_event_data_offsets_e1000e_trace_mac_register {};\n\nstruct trace_event_data_offsets_error_report_template {};\n\nstruct trace_event_data_offsets_exceptions {};\n\nstruct trace_event_data_offsets_exit_mmap {};\n\nstruct trace_event_data_offsets_ext4__bitmap_load {};\n\nstruct trace_event_data_offsets_ext4__es_extent {};\n\nstruct trace_event_data_offsets_ext4__es_shrink_enter {};\n\nstruct trace_event_data_offsets_ext4__fallocate_mode {};\n\nstruct trace_event_data_offsets_ext4__folio_op {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_enter {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_exit {};\n\nstruct trace_event_data_offsets_ext4__mb_new_pa {};\n\nstruct trace_event_data_offsets_ext4__mballoc {};\n\nstruct trace_event_data_offsets_ext4__trim {};\n\nstruct trace_event_data_offsets_ext4__truncate {};\n\nstruct trace_event_data_offsets_ext4__write_begin {};\n\nstruct trace_event_data_offsets_ext4__write_end {};\n\nstruct trace_event_data_offsets_ext4_alloc_da_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_inode {};\n\nstruct trace_event_data_offsets_ext4_begin_ordered_truncate {};\n\nstruct trace_event_data_offsets_ext4_collapse_range {};\n\nstruct trace_event_data_offsets_ext4_da_release_space {};\n\nstruct trace_event_data_offsets_ext4_da_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_update_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_end {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_start {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages_extent {};\n\nstruct trace_event_data_offsets_ext4_discard_blocks {};\n\nstruct trace_event_data_offsets_ext4_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_drop_inode {};\n\nstruct trace_event_data_offsets_ext4_error {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_enter {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_exit {};\n\nstruct trace_event_data_offsets_ext4_es_insert_delayed_extent {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_es_remove_extent {};\n\nstruct trace_event_data_offsets_ext4_es_shrink {};\n\nstruct trace_event_data_offsets_ext4_es_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_ext4_evict_inode {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_enter {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_fastpath {};\n\nstruct trace_event_data_offsets_ext4_ext_handle_unwritten_extents {};\n\nstruct trace_event_data_offsets_ext4_ext_load_extent {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space_done {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_idx {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_leaf {};\n\nstruct trace_event_data_offsets_ext4_ext_show_extent {};\n\nstruct trace_event_data_offsets_ext4_fallocate_exit {};\n\nstruct trace_event_data_offsets_ext4_fc_cleanup {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_start {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_stop {};\n\nstruct trace_event_data_offsets_ext4_fc_replay {};\n\nstruct trace_event_data_offsets_ext4_fc_replay_scan {};\n\nstruct trace_event_data_offsets_ext4_fc_stats {};\n\nstruct trace_event_data_offsets_ext4_fc_track_dentry {};\n\nstruct trace_event_data_offsets_ext4_fc_track_inode {};\n\nstruct trace_event_data_offsets_ext4_fc_track_range {};\n\nstruct trace_event_data_offsets_ext4_forget {};\n\nstruct trace_event_data_offsets_ext4_free_blocks {};\n\nstruct trace_event_data_offsets_ext4_free_inode {};\n\nstruct trace_event_data_offsets_ext4_fsmap_class {};\n\nstruct trace_event_data_offsets_ext4_get_implied_cluster_alloc_exit {};\n\nstruct trace_event_data_offsets_ext4_getfsmap_class {};\n\nstruct trace_event_data_offsets_ext4_insert_range {};\n\nstruct trace_event_data_offsets_ext4_invalidate_folio_op {};\n\nstruct trace_event_data_offsets_ext4_journal_start_inode {};\n\nstruct trace_event_data_offsets_ext4_journal_start_reserved {};\n\nstruct trace_event_data_offsets_ext4_journal_start_sb {};\n\nstruct trace_event_data_offsets_ext4_lazy_itable_init {};\n\nstruct trace_event_data_offsets_ext4_load_inode {};\n\nstruct trace_event_data_offsets_ext4_mark_inode_dirty {};\n\nstruct trace_event_data_offsets_ext4_mb_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_mb_release_group_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_inode_pa {};\n\nstruct trace_event_data_offsets_ext4_mballoc_alloc {};\n\nstruct trace_event_data_offsets_ext4_mballoc_prealloc {};\n\nstruct trace_event_data_offsets_ext4_move_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_move_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_nfs_commit_metadata {};\n\nstruct trace_event_data_offsets_ext4_other_inode_update_time {};\n\nstruct trace_event_data_offsets_ext4_prefetch_bitmaps {};\n\nstruct trace_event_data_offsets_ext4_read_block_bitmap_load {};\n\nstruct trace_event_data_offsets_ext4_remove_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_inode {};\n\nstruct trace_event_data_offsets_ext4_shutdown {};\n\nstruct trace_event_data_offsets_ext4_sync_file_enter {};\n\nstruct trace_event_data_offsets_ext4_sync_file_exit {};\n\nstruct trace_event_data_offsets_ext4_sync_fs {};\n\nstruct trace_event_data_offsets_ext4_unlink_enter {};\n\nstruct trace_event_data_offsets_ext4_unlink_exit {};\n\nstruct trace_event_data_offsets_ext4_update_sb {};\n\nstruct trace_event_data_offsets_ext4_writepages {};\n\nstruct trace_event_data_offsets_ext4_writepages_result {};\n\nstruct trace_event_data_offsets_fdb_delete {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_ff_layout_commit_error {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_fib6_table_lookup {};\n\nstruct trace_event_data_offsets_fib_table_lookup {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_fill_mg_cmtime {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_fl_getdevinfo {\n\tu32 mds_addr;\n\tconst void *mds_addr_ptr_;\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_flush_foreign {};\n\nstruct trace_event_data_offsets_free_vmap_area_noflush {};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_gpio_direction {};\n\nstruct trace_event_data_offsets_gpio_value {};\n\nstruct trace_event_data_offsets_guest_halt_poll_ns {};\n\nstruct trace_event_data_offsets_handshake_alert_class {};\n\nstruct trace_event_data_offsets_handshake_complete {};\n\nstruct trace_event_data_offsets_handshake_error_class {};\n\nstruct trace_event_data_offsets_handshake_event_class {};\n\nstruct trace_event_data_offsets_handshake_fd_class {};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_setup {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hugetlbfs__inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_alloc_inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_fallocate {};\n\nstruct trace_event_data_offsets_hugetlbfs_setattr {\n\tu32 d_name;\n\tconst void *d_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hw_pressure_update {};\n\nstruct trace_event_data_offsets_hwmon_attr_class {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_show_string {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_read {};\n\nstruct trace_event_data_offsets_i2c_reply {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_result {};\n\nstruct trace_event_data_offsets_i2c_write {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_icmp_send {};\n\nstruct trace_event_data_offsets_inet_sk_error_report {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n\tconst void *level_ptr_;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_inode_foreign_history {};\n\nstruct trace_event_data_offsets_inode_switch_wbs {};\n\nstruct trace_event_data_offsets_inode_switch_wbs_queue {};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_cqe_overflow {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_defer {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_fail_link {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_local_work_run {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_req_failed {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_short_write {};\n\nstruct trace_event_data_offsets_io_uring_submit_req {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_add {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_work_run {};\n\nstruct trace_event_data_offsets_iomap_add_to_ioend {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_dio_complete {};\n\nstruct trace_event_data_offsets_iomap_dio_rw_begin {};\n\nstruct trace_event_data_offsets_iomap_iter {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_send_cpu {};\n\nstruct trace_event_data_offsets_ipi_send_cpumask {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_irq_matrix_cpu {};\n\nstruct trace_event_data_offsets_irq_matrix_global {};\n\nstruct trace_event_data_offsets_irq_matrix_global_update {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint_stats {};\n\nstruct trace_event_data_offsets_jbd2_commit {};\n\nstruct trace_event_data_offsets_jbd2_end_commit {};\n\nstruct trace_event_data_offsets_jbd2_handle_extend {};\n\nstruct trace_event_data_offsets_jbd2_handle_start_class {};\n\nstruct trace_event_data_offsets_jbd2_handle_stats {};\n\nstruct trace_event_data_offsets_jbd2_journal_shrink {};\n\nstruct trace_event_data_offsets_jbd2_lock_buffer_stall {};\n\nstruct trace_event_data_offsets_jbd2_run_stats {};\n\nstruct trace_event_data_offsets_jbd2_shrink_checkpoint_list {};\n\nstruct trace_event_data_offsets_jbd2_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_jbd2_submit_inode_data {};\n\nstruct trace_event_data_offsets_jbd2_update_log_tail {};\n\nstruct trace_event_data_offsets_jbd2_write_superblock {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\nstruct trace_event_data_offsets_kfree {};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_kmalloc {};\n\nstruct trace_event_data_offsets_kmem_cache_alloc {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kmem_cache_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_ma_op {};\n\nstruct trace_event_data_offsets_ma_read {};\n\nstruct trace_event_data_offsets_ma_write {};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_mark_victim {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_mdio_access {};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_memcg_flush_stats {};\n\nstruct trace_event_data_offsets_memcg_rstat_events {};\n\nstruct trace_event_data_offsets_memcg_rstat_stats {};\n\nstruct trace_event_data_offsets_migration_pte {};\n\nstruct trace_event_data_offsets_mm_calculate_totalreserve_pages {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_filemap_fault {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache_range {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\nstruct trace_event_data_offsets_mm_migrate_pages_start {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_lowmem_reserve {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 upper_name;\n\tconst void *upper_name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_wmarks {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_clear_hopeless {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_reclaim_fail {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\nstruct trace_event_data_offsets_mm_vmscan_reclaim_pages {};\n\nstruct trace_event_data_offsets_mm_vmscan_throttled {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_write_folio {};\n\nstruct trace_event_data_offsets_mmap_lock {};\n\nstruct trace_event_data_offsets_mmap_lock_acquire_returned {};\n\nstruct trace_event_data_offsets_mmc_request_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mmc_request_start {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_netfs_collect {};\n\nstruct trace_event_data_offsets_netfs_collect_folio {};\n\nstruct trace_event_data_offsets_netfs_collect_gap {};\n\nstruct trace_event_data_offsets_netfs_collect_sreq {};\n\nstruct trace_event_data_offsets_netfs_collect_state {};\n\nstruct trace_event_data_offsets_netfs_collect_stream {};\n\nstruct trace_event_data_offsets_netfs_copy2cache {};\n\nstruct trace_event_data_offsets_netfs_failure {};\n\nstruct trace_event_data_offsets_netfs_folio {};\n\nstruct trace_event_data_offsets_netfs_folioq {};\n\nstruct trace_event_data_offsets_netfs_read {};\n\nstruct trace_event_data_offsets_netfs_rreq {};\n\nstruct trace_event_data_offsets_netfs_rreq_ref {};\n\nstruct trace_event_data_offsets_netfs_sreq {};\n\nstruct trace_event_data_offsets_netfs_sreq_ref {};\n\nstruct trace_event_data_offsets_netfs_write {};\n\nstruct trace_event_data_offsets_netfs_write_iter {};\n\nstruct trace_event_data_offsets_netlink_extack {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_cached_open {};\n\nstruct trace_event_data_offsets_nfs4_cb_error_class {};\n\nstruct trace_event_data_offsets_nfs4_cb_offload {};\n\nstruct trace_event_data_offsets_nfs4_cb_seqid_err {};\n\nstruct trace_event_data_offsets_nfs4_cb_sequence {};\n\nstruct trace_event_data_offsets_nfs4_clientid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_clone {};\n\nstruct trace_event_data_offsets_nfs4_close {};\n\nstruct trace_event_data_offsets_nfs4_commit_event {};\n\nstruct trace_event_data_offsets_nfs4_copy {};\n\nstruct trace_event_data_offsets_nfs4_copy_notify {};\n\nstruct trace_event_data_offsets_nfs4_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_delegreturn_exit {};\n\nstruct trace_event_data_offsets_nfs4_deviceid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_deviceid_status {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_flexfiles_io_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_getattr_event {};\n\nstruct trace_event_data_offsets_nfs4_idmap_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_event {};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_layoutget {};\n\nstruct trace_event_data_offsets_nfs4_llseek {};\n\nstruct trace_event_data_offsets_nfs4_lock_event {};\n\nstruct trace_event_data_offsets_nfs4_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_lookupp {};\n\nstruct trace_event_data_offsets_nfs4_match_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_offload_class {};\n\nstruct trace_event_data_offsets_nfs4_open_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_read_event {};\n\nstruct trace_event_data_offsets_nfs4_rename {\n\tu32 oldname;\n\tconst void *oldname_ptr_;\n\tu32 newname;\n\tconst void *newname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_sequence_done {};\n\nstruct trace_event_data_offsets_nfs4_set_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_set_lock {};\n\nstruct trace_event_data_offsets_nfs4_setup_sequence {};\n\nstruct trace_event_data_offsets_nfs4_sparse_event {};\n\nstruct trace_event_data_offsets_nfs4_state_lock_reclaim {};\n\nstruct trace_event_data_offsets_nfs4_state_mgr {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_state_mgr_failed {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n\tu32 section;\n\tconst void *section_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_test_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_trunked_exchange_id {\n\tu32 main_addr;\n\tconst void *main_addr_ptr_;\n\tu32 trunk_addr;\n\tconst void *trunk_addr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_write_event {};\n\nstruct trace_event_data_offsets_nfs4_xattr_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_xdr_bad_operation {};\n\nstruct trace_event_data_offsets_nfs4_xdr_event {};\n\nstruct trace_event_data_offsets_nfs_access_exit {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead_done {};\n\nstruct trace_event_data_offsets_nfs_atomic_open_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_atomic_open_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_commit_done {};\n\nstruct trace_event_data_offsets_nfs_create_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_create_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_direct_req_class {};\n\nstruct trace_event_data_offsets_nfs_directory_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_directory_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_fh_to_dentry {};\n\nstruct trace_event_data_offsets_nfs_folio_event {};\n\nstruct trace_event_data_offsets_nfs_folio_event_done {};\n\nstruct trace_event_data_offsets_nfs_initiate_commit {};\n\nstruct trace_event_data_offsets_nfs_initiate_read {};\n\nstruct trace_event_data_offsets_nfs_initiate_write {};\n\nstruct trace_event_data_offsets_nfs_inode_event {};\n\nstruct trace_event_data_offsets_nfs_inode_event_done {};\n\nstruct trace_event_data_offsets_nfs_inode_range_event {};\n\nstruct trace_event_data_offsets_nfs_kiocb_event {};\n\nstruct trace_event_data_offsets_nfs_link_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_link_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_local_open_fh {};\n\nstruct trace_event_data_offsets_nfs_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_lookup_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_assign {\n\tu32 option;\n\tconst void *option_ptr_;\n\tu32 value;\n\tconst void *value_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_option {\n\tu32 option;\n\tconst void *option_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_path {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_page_class {};\n\nstruct trace_event_data_offsets_nfs_page_error_class {};\n\nstruct trace_event_data_offsets_nfs_pgio_error {};\n\nstruct trace_event_data_offsets_nfs_readdir_event {};\n\nstruct trace_event_data_offsets_nfs_readpage_done {};\n\nstruct trace_event_data_offsets_nfs_readpage_short {};\n\nstruct trace_event_data_offsets_nfs_rename_event {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_rename_event_done {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_sillyrename_unlink {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_update_size_class {};\n\nstruct trace_event_data_offsets_nfs_writeback_done {};\n\nstruct trace_event_data_offsets_nfs_xdr_event {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_nlmclnt_lock_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_notifier_info {};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_page_cache_ra_op {};\n\nstruct trace_event_data_offsets_page_cache_ra_order {};\n\nstruct trace_event_data_offsets_page_cache_ra_unbounded {};\n\nstruct trace_event_data_offsets_page_pool_release {};\n\nstruct trace_event_data_offsets_page_pool_state_hold {};\n\nstruct trace_event_data_offsets_page_pool_state_release {};\n\nstruct trace_event_data_offsets_page_pool_update_nid {};\n\nstruct trace_event_data_offsets_pci_hp_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n\tu32 slot;\n\tconst void *slot_ptr_;\n};\n\nstruct trace_event_data_offsets_pcie_link_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_pmap_register {};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_err_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_ds_connect {\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_layout_event {};\n\nstruct trace_event_data_offsets_pnfs_update_layout {};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_purge_vmap_area_lazy {};\n\nstruct trace_event_data_offsets_pwm {};\n\nstruct trace_event_data_offsets_pwm_read_waveform {};\n\nstruct trace_event_data_offsets_pwm_round_waveform_fromhw {};\n\nstruct trace_event_data_offsets_pwm_round_waveform_tohw {};\n\nstruct trace_event_data_offsets_pwm_write_waveform {};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_enqueue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kvfree_callback {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_segcb_stats {};\n\nstruct trace_event_data_offsets_rcu_sr_normal {};\n\nstruct trace_event_data_offsets_rcu_stall_warning {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_watching {};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_regcache_drop_region {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regcache_sync {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 status;\n\tconst void *status_ptr_;\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_register_class {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_async {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bool {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bulk {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_reg {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_basic {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_range {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_value {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_buf_alloc {};\n\nstruct trace_event_data_offsets_rpc_call_rpcerror {};\n\nstruct trace_event_data_offsets_rpc_clnt_class {};\n\nstruct trace_event_data_offsets_rpc_clnt_clone_err {};\n\nstruct trace_event_data_offsets_rpc_clnt_new {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_clnt_new_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_failure {};\n\nstruct trace_event_data_offsets_rpc_reply_event {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_request {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_socket_nospace {};\n\nstruct trace_event_data_offsets_rpc_stats_latency {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_queued {\n\tu32 q_name;\n\tconst void *q_name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_running {};\n\nstruct trace_event_data_offsets_rpc_task_status {};\n\nstruct trace_event_data_offsets_rpc_tls_class {\n\tu32 servername;\n\tconst void *servername_ptr_;\n\tu32 progname;\n\tconst void *progname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_alignment {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_rpc_xdr_overflow {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_lifetime_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_getport {\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_register {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_setport {};\n\nstruct trace_event_data_offsets_rpcb_unregister {\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_internal {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_return_int {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_status {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\nstruct trace_event_data_offsets_rtc_alarm_irq_enable {};\n\nstruct trace_event_data_offsets_rtc_irq_set_freq {};\n\nstruct trace_event_data_offsets_rtc_irq_set_state {};\n\nstruct trace_event_data_offsets_rtc_offset_class {};\n\nstruct trace_event_data_offsets_rtc_time_alarm_class {};\n\nstruct trace_event_data_offsets_rtc_timer_class {};\n\nstruct trace_event_data_offsets_sbi_call {};\n\nstruct trace_event_data_offsets_sbi_return {};\n\nstruct trace_event_data_offsets_sched_ext_bypass_lb {};\n\nstruct trace_event_data_offsets_sched_ext_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_ext_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_end {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_start {};\n\nstruct trace_event_data_offsets_sched_kthread_work_queue_work {};\n\nstruct trace_event_data_offsets_sched_migrate_task {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_move_numa {};\n\nstruct trace_event_data_offsets_sched_numa_pair_template {};\n\nstruct trace_event_data_offsets_sched_pi_setprio {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_prepare_exec {\n\tu32 interp;\n\tconst void *interp_ptr_;\n\tu32 filename;\n\tconst void *filename_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exit {};\n\nstruct trace_event_data_offsets_sched_process_fork {\n\tu32 parent_comm;\n\tconst void *parent_comm_ptr_;\n\tu32 child_comm;\n\tconst void *child_comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_wait {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_skip_cpuset_numa {};\n\nstruct trace_event_data_offsets_sched_skip_vma_numa {};\n\nstruct trace_event_data_offsets_sched_stat_runtime {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\nstruct trace_event_data_offsets_selinux_audited {\n\tu32 scontext;\n\tconst void *scontext_ptr_;\n\tu32 tcontext;\n\tconst void *tcontext_ptr_;\n\tu32 tclass;\n\tconst void *tclass_ptr_;\n};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_sk_data_ready {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_smbus_read {};\n\nstruct trace_event_data_offsets_smbus_reply {};\n\nstruct trace_event_data_offsets_smbus_result {};\n\nstruct trace_event_data_offsets_smbus_write {};\n\nstruct trace_event_data_offsets_snd_soc_dapm {\n\tu32 card_name;\n\tconst void *card_name_ptr_;\n\tu32 comp_name;\n\tconst void *comp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_snd_soc_dapm_basic {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_snd_soc_dapm_connected {};\n\nstruct trace_event_data_offsets_snd_soc_dapm_path {\n\tu32 wname;\n\tconst void *wname_ptr_;\n\tu32 pname;\n\tconst void *pname_ptr_;\n\tu32 pnname;\n\tconst void *pnname_ptr_;\n};\n\nstruct trace_event_data_offsets_snd_soc_dapm_walk_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_snd_soc_dapm_widget {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_snd_soc_jack_irq {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_snd_soc_jack_notify {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_snd_soc_jack_report {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_sock_msg_length {};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_softirq {};\n\nstruct trace_event_data_offsets_spi_controller {};\n\nstruct trace_event_data_offsets_spi_mem_start_op {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 op;\n\tconst void *op_ptr_;\n\tu32 data;\n\tconst void *data_ptr_;\n};\n\nstruct trace_event_data_offsets_spi_mem_stop_op {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 data;\n\tconst void *data_ptr_;\n};\n\nstruct trace_event_data_offsets_spi_message {};\n\nstruct trace_event_data_offsets_spi_message_done {};\n\nstruct trace_event_data_offsets_spi_set_cs {};\n\nstruct trace_event_data_offsets_spi_setup {};\n\nstruct trace_event_data_offsets_spi_transfer {\n\tu32 rx_buf;\n\tconst void *rx_buf_ptr_;\n\tu32 tx_buf;\n\tconst void *tx_buf_ptr_;\n};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_svc_alloc_arg_err {};\n\nstruct trace_event_data_offsets_svc_authenticate {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_deferred_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_pool_thread_event {};\n\nstruct trace_event_data_offsets_svc_process {\n\tu32 service;\n\tconst void *service_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_replace_page_err {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_status {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_stats_latency {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_unregister {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_svc_xdr_msg_class {};\n\nstruct trace_event_data_offsets_svc_xprt_accept {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_create_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_dequeue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_enqueue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_accept_class {\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_lifetime_class {};\n\nstruct trace_event_data_offsets_svcsock_marker {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_recv_short {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_state {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_swiotlb_bounced {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_prctl_unknown {};\n\nstruct trace_event_data_offsets_task_rename {};\n\nstruct trace_event_data_offsets_tasklet {};\n\nstruct trace_event_data_offsets_tcp_ao_event {};\n\nstruct trace_event_data_offsets_tcp_cong_state_set {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_event_skb {};\n\nstruct trace_event_data_offsets_tcp_hash_event {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\nstruct trace_event_data_offsets_tcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_tcp_retransmit_skb {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_send_reset {};\n\nstruct trace_event_data_offsets_tcp_sendmsg_locked {};\n\nstruct trace_event_data_offsets_thermal_power_cpu_get_power_simple {};\n\nstruct trace_event_data_offsets_thermal_power_cpu_limit {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_power_devfreq_get_power {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_power_devfreq_limit {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_temperature {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_zone_trip {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_tick_stop {};\n\nstruct trace_event_data_offsets_timer_base_idle {};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_tls_contenttype {};\n\nstruct trace_event_data_offsets_tmigr_connect_child_parent {};\n\nstruct trace_event_data_offsets_tmigr_connect_cpu_parent {};\n\nstruct trace_event_data_offsets_tmigr_cpugroup {};\n\nstruct trace_event_data_offsets_tmigr_group_and_cpu {};\n\nstruct trace_event_data_offsets_tmigr_group_set {};\n\nstruct trace_event_data_offsets_tmigr_handle_remote {};\n\nstruct trace_event_data_offsets_tmigr_idle {};\n\nstruct trace_event_data_offsets_tmigr_update_events {};\n\nstruct trace_event_data_offsets_track_foreign_dirty {};\n\nstruct trace_event_data_offsets_udc_log_ep {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_udc_log_gadget {};\n\nstruct trace_event_data_offsets_udc_log_req {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_usb_core_log_usb_device {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_watchdog_set_timeout {};\n\nstruct trace_event_data_offsets_watchdog_template {};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_queue_work {\n\tu32 workqueue;\n\tconst void *workqueue_ptr_;\n};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_folio_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_data_offsets_xhci_dbc_log_request {};\n\nstruct trace_event_data_offsets_xhci_log_ctrl_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_doorbell {};\n\nstruct trace_event_data_offsets_xhci_log_ep_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_free_virt_dev {};\n\nstruct trace_event_data_offsets_xhci_log_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_portsc {};\n\nstruct trace_event_data_offsets_xhci_log_ring {};\n\nstruct trace_event_data_offsets_xhci_log_slot_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_stream_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_trb {};\n\nstruct trace_event_data_offsets_xhci_log_urb {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_virt_dev {};\n\nstruct trace_event_data_offsets_xprt_cong_event {};\n\nstruct trace_event_data_offsets_xprt_ping {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_reserve {};\n\nstruct trace_event_data_offsets_xprt_retransmit {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_transmit {};\n\nstruct trace_event_data_offsets_xprt_writelock_event {};\n\nstruct trace_event_data_offsets_xs_data_ready {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_socket_event {};\n\nstruct trace_event_data_offsets_xs_socket_event_done {};\n\nstruct trace_event_data_offsets_xs_stream_read_data {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_stream_read_request {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst unsigned int is_signed: 1;\n\t\t\tunsigned int needs_test: 1;\n\t\t\tconst int filter_type;\n\t\t\tconst int len;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct eventfs_inode *ei;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\trefcount_t ref;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nstruct trace_event_raw_9p_client_req {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_client_res {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\t__u32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_fid_ref {\n\tstruct trace_entry ent;\n\tint fid;\n\tint refcount;\n\t__u8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_protocol_dump {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u16 tag;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarmtimer_suspend {\n\tstruct trace_entry ent;\n\ts64 expires;\n\tunsigned char alarm_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alloc_vmap_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int vstart;\n\tlong unsigned int vend;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_bmdma_status {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char host_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_action_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy_qc {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_exec_command_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char feature;\n\tunsigned char hob_nsect;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tlong unsigned int deadline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_end_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tint rc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_port_eh_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_complete_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char status;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char error;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_issue_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tunsigned char proto;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_hsm_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int protocol;\n\tunsigned int hsm_state;\n\tunsigned char dev_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char hsm_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_tf_load {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_transfer_data_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int flags;\n\tunsigned int offset;\n\tunsigned int bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int wb_setpoint;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bl_ext_tree_prepare_commit {\n\tstruct trace_entry ent;\n\tint ret;\n\tsize_t count;\n\tu64 lwb;\n\tbool not_all_ranges;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_blkdev_zone_mgmt {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t nr_sectors;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_completion {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_zwplug {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int zno;\n\tsector_t sector;\n\tunsigned int nr_sectors;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trace_printk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bpf_string;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trigger_tp {\n\tstruct trace_entry ent;\n\tint nonce;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_xdp_link_attach_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_add {\n\tstruct trace_entry ent;\n\tu8 ndm_flags;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tu16 nlh_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_external_learn_add {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_mdb_full {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tint af;\n\tu16 vid;\n\t__u8 src[16];\n\t__u8 grp[16];\n\t__u8 grpmac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_event {\n\tstruct trace_entry ent;\n\tconst struct cache_head *h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cap_capable {\n\tstruct trace_entry ent;\n\tconst struct cred *cred;\n\tstruct user_namespace *target_ns;\n\tconst struct user_namespace *capable_ns;\n\tint cap;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cdev_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int target;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_level;\n\tu64 dst_id;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu32 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_rstat {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tint cpu;\n\tbool contended;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_duty_cycle {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int num;\n\tunsigned int den;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_parent {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_pname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_phase {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint phase;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int rate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate_range {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_pname;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int prate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_begin {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_end {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_idle_miss {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool below;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_function {\n\tstruct trace_entry ent;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_queue_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\tu32 ctime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime_ns_xchg {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tu32 gen;\n\tu32 old;\n\tu32 new;\n\tu32 cur;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devfreq_frequency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tlong unsigned int freq;\n\tlong unsigned int prev_freq;\n\tlong unsigned int busy_time;\n\tlong unsigned int total_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devfreq_monitor {\n\tstruct trace_entry ent;\n\tlong unsigned int freq;\n\tlong unsigned int busy_time;\n\tlong unsigned int total_time;\n\tunsigned int polling_ms;\n\tu32 __data_loc_dev_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_parent;\n\tu32 __data_loc_pm_ops;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_recover_aborted {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tbool health_state;\n\tu64 time_since_last_recover;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_reporter_state_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu8 new_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwerr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tint err;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwmsg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tbool incoming;\n\tlong unsigned int type;\n\tu32 __data_loc_buf;\n\tsize_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_trap_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_trap_name;\n\tu32 __data_loc_trap_group_name;\n\tchar input_dev_name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devres {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tstruct device *dev;\n\tconst char *op;\n\tvoid *node;\n\tu32 __data_loc_name;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tgfp_t flags;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tgfp_t flags;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_attach_dev {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tstruct dma_buf_attachment *attach;\n\tbool is_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_fd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence_unsignaled {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 phys_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tint full_nents;\n\tint full_ents;\n\tbool truncated;\n\tu32 __data_loc_phys_addrs;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tint err;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_single {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_addrs;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dql_stall_detected {\n\tstruct trace_entry ent;\n\tshort unsigned int thrs;\n\tunsigned int len;\n\tlong unsigned int last_reap;\n\tlong unsigned int hist_head;\n\tlong unsigned int now;\n\tlong unsigned int hist[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_e1000e_trace_mac_register {\n\tstruct trace_entry ent;\n\tuint32_t reg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_error_report_template {\n\tstruct trace_entry ent;\n\tenum error_detector error_detector;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exceptions {\n\tstruct trace_entry ent;\n\tlong unsigned int address;\n\tlong unsigned int ip;\n\tlong unsigned int error_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exit_mmap {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tstruct maple_tree *mt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_shrink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_to_scan;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__fallocate_mode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tint mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int flags;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int mflags;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mb_new_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 pa_pstart;\n\t__u64 pa_lstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mballoc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__trim {\n\tstruct trace_entry ent;\n\tint dev_major;\n\tint dev_minor;\n\t__u32 group;\n\tint start;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int copied;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_alloc_da_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int data_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_begin_ordered_truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_collapse_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_release_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint freed_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint reserve_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_update_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint used_blocks;\n\tint reserved_data_blocks;\n\tint quota_claim;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 lblk;\n\t__u32 len;\n\t__u32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 blk;\n\t__u64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_drop_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint drop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tconst char *function;\n\tunsigned int line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_insert_delayed_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tbool lclu_allocated;\n\tbool end_allocated;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tint found;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_remove_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t lblk;\n\tloff_t len;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tlong long unsigned int scan_time;\n\tint nr_skipped;\n\tint retried;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_evict_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_fastpath {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\text4_lblk_t i_lblk;\n\tunsigned int i_len;\n\text4_fsblk_t i_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_handle_unwritten_extents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tunsigned int allocated;\n\text4_fsblk_t newblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_load_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tshort unsigned int eh_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_idx {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_leaf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t ee_lblk;\n\text4_fsblk_t ee_pblk;\n\tshort int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_show_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tshort unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fallocate_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int blocks;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_cleanup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint j_fc_off;\n\tint full;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_stop {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nblks;\n\tint reason;\n\tint num_fc;\n\tint num_fc_ineligible;\n\tint nblks_agg;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint tag;\n\tint ino;\n\tint priv1;\n\tint priv2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint error;\n\tint off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int fc_ineligible_rc[13];\n\tlong unsigned int fc_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_numblks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_dentry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tlong int start;\n\tlong int end;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_forget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tint is_metadata;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tlong unsigned int count;\n\tint flags;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u64 blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu32 agno;\n\tu64 bno;\n\tu64 len;\n\tu64 owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_implied_cluster_alloc_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu64 block;\n\tu64 len;\n\tu64 owner;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_insert_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_invalidate_folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tsize_t offset;\n\tsize_t length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_inode {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_reserved {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_lazy_itable_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_load_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mark_inode_dirty {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint needed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_group_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 pa_pstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_inode_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\t__u32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 goal_logical;\n\tint goal_start;\n\t__u32 goal_group;\n\tint goal_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\t__u16 found;\n\t__u16 groups;\n\t__u16 buddy;\n\t__u16 flags;\n\t__u16 tail;\n\t__u8 cr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_prealloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tunsigned int orig_flags;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int m_len;\n\tu64 move_len;\n\tint move_type;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_nfs_commit_metadata {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_other_inode_update_time {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t orig_ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_prefetch_bitmaps {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\t__u32 next;\n\t__u32 ios;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_read_block_bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tbool prefetch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_remove_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\text4_fsblk_t ee_pblk;\n\text4_lblk_t ee_lblk;\n\tshort unsigned int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tint datasync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_update_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\text4_fsblk_t fsblk;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages_result {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tint pages_written;\n\tlong int pages_skipped;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fdb_delete {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ff_layout_commit_error {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib6_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu32 flowlabel;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[16];\n\t__u8 dst[16];\n\tu16 sport;\n\tu16 dport;\n\tu8 proto;\n\tu8 rt_type;\n\tchar name[16];\n\t__u8 gw[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tchar name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lease *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tlong unsigned int break_time;\n\tlong unsigned int downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int pid;\n\tunsigned int flags;\n\tunsigned char type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fill_mg_cmtime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\ttime64_t mtime_s;\n\tu32 ctime_ns;\n\tu32 mtime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fl_getdevinfo {\n\tstruct trace_entry ent;\n\tu32 __data_loc_mds_addr;\n\tunsigned char deviceid[16];\n\tu32 __data_loc_ds_ips;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_flush_foreign {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tunsigned int frn_bdi_id;\n\tunsigned int frn_memcg_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_free_vmap_area_noflush {\n\tstruct trace_entry ent;\n\tlong unsigned int va_start;\n\tlong unsigned int nr_lazy;\n\tlong unsigned int nr_lazy_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpio_direction {\n\tstruct trace_entry ent;\n\tunsigned int gpio;\n\tint in;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpio_value {\n\tstruct trace_entry ent;\n\tunsigned int gpio;\n\tint get;\n\tint value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_guest_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_alert_class {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int level;\n\tlong unsigned int description;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_complete {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint status;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_error_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint err;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_event_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_fd_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint fd;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_setup {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs__inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u16 mode;\n\tloff_t size;\n\tunsigned int nlink;\n\tunsigned int seals;\n\tblkcnt_t blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_alloc_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_fallocate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint mode;\n\tloff_t offset;\n\tloff_t len;\n\tloff_t size;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_setattr {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int d_len;\n\tu32 __data_loc_d_name;\n\tunsigned int ia_valid;\n\tunsigned int ia_mode;\n\tloff_t old_size;\n\tloff_t ia_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hw_pressure_update {\n\tstruct trace_entry ent;\n\tlong unsigned int hw_pressure;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_class {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tlong long int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_show_string {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tu32 __data_loc_label;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 nr_msgs;\n\t__s16 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icmp_send {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint type;\n\tint code;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u16 sport;\n\t__u16 dport;\n\tshort unsigned int ulen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sk_error_report {\n\tstruct trace_entry ent;\n\tint error;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\ntypedef int (*initcall_t)(void);\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_foreign_history {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t cgroup_ino;\n\tunsigned int history;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs_queue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint res;\n\tunsigned int cflags;\n\tu64 extra1;\n\tu64 extra2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqe_overflow {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong long unsigned int user_data;\n\ts32 res;\n\tu32 cflags;\n\tvoid *ocqe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tu8 opcode;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tvoid *link;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_local_work_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint count;\n\tunsigned int loops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tint events;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tstruct io_wq_work *work;\n\tbool hashed;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_req_failed {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tu8 flags;\n\tu8 ioprio;\n\tu64 off;\n\tu64 addr;\n\tu32 len;\n\tu32 op_flags;\n\tu16 buf_index;\n\tu16 personality;\n\tu32 file_index;\n\tu64 pad1;\n\tu64 addr3;\n\tint error;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_short_write {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu64 fpos;\n\tu64 wanted;\n\tu64 got;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_req {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tbool sq_thread;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_work_run {\n\tstruct trace_entry ent;\n\tvoid *tctx;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_add_to_ioend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 pos;\n\tu64 dirty_len;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tint ki_flags;\n\tbool aio;\n\tint error;\n\tssize_t ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_rw_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tsize_t count;\n\tsize_t done_before;\n\tint ki_flags;\n\tunsigned int dio_flags;\n\tbool aio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_iter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t pos;\n\tu64 length;\n\tint status;\n\tunsigned int flags;\n\tconst void *ops;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t size;\n\tloff_t offset;\n\tu64 length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpumask {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_cpu {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int cpu;\n\tbool online;\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_global {\n\tstruct trace_entry ent;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_global_update {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int chp_time;\n\t__u32 forced_to_close;\n\t__u32 written;\n\t__u32 dropped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_end_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\ttid_t head;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_extend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint buffer_credits;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_start_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint interval;\n\tint sync;\n\tint requested_blocks;\n\tint dirtied_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_journal_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_lock_buffer_stall {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int stall_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_run_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int wait;\n\tlong unsigned int request_delay;\n\tlong unsigned int running;\n\tlong unsigned int locked;\n\tlong unsigned int flushing;\n\tlong unsigned int logging;\n\t__u32 handle_count;\n\t__u32 blocks;\n\t__u32 blocks_logged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_checkpoint_list {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t first_tid;\n\ttid_t tid;\n\ttid_t last_tid;\n\tlong unsigned int nr_freed;\n\ttid_t next_tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_shrunk;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_submit_inode_data {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_update_log_tail {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tail_sequence;\n\ttid_t first_tid;\n\tlong unsigned int block_nr;\n\tlong unsigned int freed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_write_superblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tblk_opf_t write_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tvoid *rx_sk;\n\tshort unsigned int protocol;\n\tenum skb_drop_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmalloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tbool accounted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_op {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_read {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_write {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tlong unsigned int piv;\n\tvoid *val;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tu32 __data_loc_comm;\n\tlong unsigned int total_vm;\n\tlong unsigned int anon_rss;\n\tlong unsigned int file_rss;\n\tlong unsigned int shmem_rss;\n\tuid_t uid;\n\tlong unsigned int pgtables;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mdio_access {\n\tstruct trace_entry ent;\n\tchar busid[61];\n\tchar read;\n\tu8 addr;\n\tu16 val;\n\tunsigned int regnum;\n\tchar __data[0];\n};\n\nstruct xdp_mem_allocator;\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_flush_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\ts64 stats_updates;\n\tbool force;\n\tbool needs_flush;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_events {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tlong unsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pte {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_calculate_totalreserve_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int totalreserve_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tunsigned char order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache_range {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int last_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tenum lru_list lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tlong unsigned int thp_succeeded;\n\tlong unsigned int thp_failed;\n\tlong unsigned int thp_split;\n\tlong unsigned int large_folio_split;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages_start {\n\tstruct trace_entry ent;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tint percpu_refill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tlong unsigned int gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_lowmem_reserve {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tu32 __data_loc_upper_name;\n\tlong int lowmem_reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_wmarks {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tlong unsigned int watermark_min;\n\tlong unsigned int watermark_low;\n\tlong unsigned int watermark_high;\n\tlong unsigned int watermark_promo;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tlong unsigned int gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_clear_hopeless {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_reclaim_fail {\n\tstruct trace_entry ent;\n\tint nid;\n\tint failures;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_reclaim_pages {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_throttled {\n\tstruct trace_entry ent;\n\tint nid;\n\tint usec_timeout;\n\tint usec_delayed;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_write_folio {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock_acquire_returned {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tbool success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmc_request_done {\n\tstruct trace_entry ent;\n\tu32 cmd_opcode;\n\tint cmd_err;\n\tu32 cmd_resp[4];\n\tunsigned int cmd_retries;\n\tu32 stop_opcode;\n\tint stop_err;\n\tu32 stop_resp[4];\n\tunsigned int stop_retries;\n\tu32 sbc_opcode;\n\tint sbc_err;\n\tu32 sbc_resp[4];\n\tunsigned int sbc_retries;\n\tunsigned int bytes_xfered;\n\tint data_err;\n\tint tag;\n\tunsigned int can_retune;\n\tunsigned int doing_retune;\n\tunsigned int retune_now;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct mmc_request *mrq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmc_request_start {\n\tstruct trace_entry ent;\n\tu32 cmd_opcode;\n\tu32 cmd_arg;\n\tunsigned int cmd_flags;\n\tunsigned int cmd_retries;\n\tu32 stop_opcode;\n\tu32 stop_arg;\n\tunsigned int stop_flags;\n\tunsigned int stop_retries;\n\tu32 sbc_opcode;\n\tu32 sbc_arg;\n\tunsigned int sbc_flags;\n\tunsigned int sbc_retries;\n\tunsigned int blocks;\n\tunsigned int blk_addr;\n\tunsigned int blksz;\n\tunsigned int data_flags;\n\tint tag;\n\tunsigned int can_retune;\n\tunsigned int doing_retune;\n\tunsigned int retune_now;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct mmc_request *mrq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int len;\n\tlong long unsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_folio {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tlong unsigned int index;\n\tlong long unsigned int fend;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int collected_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_gap {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tunsigned char type;\n\tlong long unsigned int from;\n\tlong long unsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_sreq {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int subreq;\n\tunsigned int stream;\n\tunsigned int len;\n\tunsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_state {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int notes;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_stream {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int front;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_copy2cache {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int creq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_failure {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_failure what;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folio {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tlong unsigned int index;\n\tunsigned int nr;\n\tenum netfs_folio_trace why;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folioq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int id;\n\tenum netfs_folioq_trace trace;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_read {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int cookie;\n\tloff_t i_size;\n\tloff_t start;\n\tsize_t len;\n\tenum netfs_read_trace what;\n\tunsigned int netfs_inode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int flags;\n\tenum netfs_io_origin origin;\n\tenum netfs_rreq_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tint ref;\n\tenum netfs_rreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort unsigned int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_sreq_trace what;\n\tu8 slot;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int subreq;\n\tint ref;\n\tenum netfs_sreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tenum netfs_write_trace what;\n\tlong long unsigned int start;\n\tlong long unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write_iter {\n\tstruct trace_entry ent;\n\tlong long unsigned int start;\n\tsize_t len;\n\tunsigned int flags;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netlink_extack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cached_open {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_error_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 cbident;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_offload {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tloff_t cb_count;\n\tint cb_how;\n\tint cb_stateid_seq;\n\tu32 cb_stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_seqid_err {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clientid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clone {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 src_fhandle;\n\tu32 src_fileid;\n\tu32 dst_fhandle;\n\tu32 dst_fileid;\n\tdev_t src_dev;\n\tdev_t dst_dev;\n\tloff_t src_offset;\n\tloff_t dst_offset;\n\tint src_stateid_seq;\n\tu32 src_stateid_hash;\n\tint dst_stateid_seq;\n\tu32 dst_stateid_hash;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_close {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_commit_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tloff_t offset;\n\tu32 count;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_copy {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 src_fhandle;\n\tu32 src_fileid;\n\tu32 dst_fhandle;\n\tu32 dst_fileid;\n\tdev_t src_dev;\n\tdev_t dst_dev;\n\tint src_stateid_seq;\n\tu32 src_stateid_hash;\n\tint dst_stateid_seq;\n\tu32 dst_stateid_hash;\n\tloff_t src_offset;\n\tloff_t dst_offset;\n\tbool sync;\n\tloff_t len;\n\tint res_stateid_seq;\n\tu32 res_stateid_hash;\n\tloff_t res_count;\n\tbool res_sync;\n\tbool res_cons;\n\tbool intra;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_copy_notify {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tu32 fileid;\n\tdev_t dev;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint res_stateid_seq;\n\tu32 res_stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegation_event {\n\tstruct trace_entry ent;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegreturn_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_status {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint status;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_flexfiles_io_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_getattr_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int valid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_idmap_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 id;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_layoutget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 iomode;\n\tu64 offset;\n\tu64 count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_llseek {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tu32 fileid;\n\tdev_t dev;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tloff_t offset_s;\n\tu32 what;\n\tloff_t offset_r;\n\tu32 eof;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lock_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookup_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookupp {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_match_stateid_event {\n\tstruct trace_entry ent;\n\tint s1_seq;\n\tint s2_seq;\n\tu32 s1_hash;\n\tu32 s2_hash;\n\tint s1_type;\n\tint s2_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_offload_class {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_open_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint openstateid_seq;\n\tu32 openstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_read_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 olddir;\n\tu32 __data_loc_oldname;\n\tu64 newdir;\n\tu32 __data_loc_newname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_sequence_done {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int target_highest_slotid;\n\tlong unsigned int status_flags;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_delegation_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_lock {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint lockstateid_seq;\n\tu32 lockstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_setup_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_used_slotid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_sparse_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tloff_t offset;\n\tloff_t len;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_lock_reclaim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int state_flags;\n\tlong unsigned int lock_flags;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr_failed {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tu32 __data_loc_section;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_test_stateid_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_trunked_exchange_id {\n\tstruct trace_entry ent;\n\tu32 __data_loc_main_addr;\n\tu32 __data_loc_trunk_addr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_write_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xattr_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_bad_operation {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tu32 expected;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_access_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tunsigned int mask;\n\tunsigned int permitted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_commit_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_direct_req_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t offset;\n\tssize_t count;\n\tssize_t error;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_fh_to_dentry {\n\tstruct trace_entry ent;\n\tint error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_read {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_write {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tlong unsigned int stable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_range_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t range_start;\n\tloff_t range_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_kiocb_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_local_open_fh {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_assign {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tu32 __data_loc_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_option {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_path {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tconst struct nfs_page *req;\n\tloff_t offset;\n\tunsigned int count;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tunsigned int count;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_pgio_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tloff_t pos;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readdir_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tchar verifier[8];\n\tu64 cookie;\n\tlong unsigned int index;\n\tunsigned int dtsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_short {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 old_dir;\n\tu64 new_dir;\n\tu32 __data_loc_old_name;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 old_dir;\n\tu32 __data_loc_old_name;\n\tu64 new_dir;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_sillyrename_unlink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_update_size_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t cur_size;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_writeback_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tlong unsigned int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nlmclnt_lock_event {\n\tstruct trace_entry ent;\n\tu32 oh;\n\tu32 svid;\n\tu32 fh;\n\tlong unsigned int status;\n\tu64 start;\n\tu64 len;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_notifier_info {\n\tstruct trace_entry ent;\n\tvoid *cb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_op {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n\tlong unsigned int req_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_order {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_unbounded {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int nr_to_read;\n\tlong unsigned int lookahead_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\ts32 inflight;\n\tu32 hold;\n\tu32 release;\n\tu64 cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_hold {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 hold;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 release;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_update_nid {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tint pool_nid;\n\tint new_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pci_hp_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tu32 __data_loc_slot;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pcie_link_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tunsigned int type;\n\tunsigned int reason;\n\tunsigned int cur_bus_speed;\n\tunsigned int max_bus_speed;\n\tunsigned int width;\n\tunsigned int flit_mode;\n\tunsigned int link_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pmap_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_err_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tlong unsigned int status;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_ds_connect {\n\tstruct trace_entry ent;\n\tu32 __data_loc_ds_ips;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_layout_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_update_layout {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tenum pnfs_update_layout_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_purge_vmap_area_lazy {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int npurged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_read_waveform {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tvoid *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_round_waveform_fromhw {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tconst void *wfhw;\n\tu64 wf_period_length_ns;\n\tu64 wf_duty_length_ns;\n\tu64 wf_duty_offset_ns;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_round_waveform_tohw {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tu64 wf_period_length_ns;\n\tu64 wf_duty_length_ns;\n\tu64 wf_duty_offset_ns;\n\tvoid *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_write_waveform {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tconst void *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_enqueue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kvfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_segcb_stats {\n\tstruct trace_entry ent;\n\tconst char *ctx;\n\tlong unsigned int gp_seq[4];\n\tlong int seglen[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_sr_normal {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tconst char *srevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_stall_warning {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_watching {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint counter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_drop_region {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int from;\n\tunsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_sync {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_status;\n\tu32 __data_loc_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_register_class {\n\tstruct trace_entry ent;\n\tu32 version;\n\tlong unsigned int family;\n\tshort unsigned int protocol;\n\tshort unsigned int port;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_async {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_block {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bool {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bulk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tu32 __data_loc_buf;\n\tint val_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_reg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_basic {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_range {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint min;\n\tint max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_value {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_buf_alloc {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tsize_t callsize;\n\tsize_t recvsize;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_call_rpcerror {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint tk_status;\n\tint rpc_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_class {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_clone_err {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tlong unsigned int xprtsec;\n\tlong unsigned int flags;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new_err {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_failure {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_reply_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 __data_loc_progname;\n\tu32 version;\n\tu32 __data_loc_procname;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_request {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tbool async;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_socket_nospace {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int total;\n\tunsigned int remaining;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_stats_latency {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tlong unsigned int backlog;\n\tlong unsigned int rtt;\n\tlong unsigned int execute;\n\tu32 xprt_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_queued {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tlong unsigned int timeout;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tu32 __data_loc_q_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_running {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *action;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_tls_class {\n\tstruct trace_entry ent;\n\tlong unsigned int requested_policy;\n\tu32 version;\n\tu32 __data_loc_servername;\n\tu32 __data_loc_progname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_alignment {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t offset;\n\tunsigned int copied;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_overflow {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t requested;\n\tconst void *end;\n\tconst void *p;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_lifetime_class {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_getport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int bind_version;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_setport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tshort unsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_unregister {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_internal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flags;\n\tint usage_count;\n\tint disable_depth;\n\tint runtime_auto;\n\tint request_pending;\n\tint irq_safe;\n\tint child_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_return_int {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int ip;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\ts32 node_id;\n\ts32 mm_cid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_alarm_irq_enable {\n\tstruct trace_entry ent;\n\tunsigned int enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_freq {\n\tstruct trace_entry ent;\n\tint freq;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_state {\n\tstruct trace_entry ent;\n\tint enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_offset_class {\n\tstruct trace_entry ent;\n\tlong int offset;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_time_alarm_class {\n\tstruct trace_entry ent;\n\ttime64_t secs;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_timer_class {\n\tstruct trace_entry ent;\n\tstruct rtc_timer *timer;\n\tktime_t expires;\n\tktime_t period;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sbi_call {\n\tstruct trace_entry ent;\n\tint ext;\n\tint fid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sbi_return {\n\tstruct trace_entry ent;\n\tlong int error;\n\tlong int value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_bypass_lb {\n\tstruct trace_entry ent;\n\t__u32 node;\n\t__u32 nr_cpus;\n\t__u32 nr_tasks;\n\t__u32 nr_balanced;\n\t__u32 before_min;\n\t__u32 before_max;\n\t__u32 after_min;\n\t__u32 after_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_dump {\n\tstruct trace_entry ent;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\t__s64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *worker;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_move_numa {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_numa_pair_template {\n\tstruct trace_entry ent;\n\tpid_t src_pid;\n\tpid_t src_tgid;\n\tpid_t src_ngid;\n\tint src_cpu;\n\tint src_nid;\n\tpid_t dst_pid;\n\tpid_t dst_tgid;\n\tpid_t dst_ngid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_prepare_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_interp;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exit {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tbool group_dead;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tu32 __data_loc_parent_comm;\n\tpid_t parent_pid;\n\tu32 __data_loc_child_comm;\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_cpuset_numa {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tlong unsigned int mem_allowed[1];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_vma_numa {\n\tstruct trace_entry ent;\n\tlong unsigned int numa_scan_offset;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tenum numa_vmaskip_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 runtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_selinux_audited {\n\tstruct trace_entry ent;\n\tu32 requested;\n\tu32 denied;\n\tu32 audited;\n\tint result;\n\tu32 __data_loc_scontext;\n\tu32 __data_loc_tcontext;\n\tu32 __data_loc_tclass;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sk_data_ready {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 family;\n\t__u16 protocol;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 flags;\n\t__u16 addr;\n\t__u8 command;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 read_write;\n\t__u8 command;\n\t__s16 res;\n\t__u32 protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_dapm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_card_name;\n\tu32 __data_loc_comp_name;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_dapm_basic {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_dapm_connected {\n\tstruct trace_entry ent;\n\tint paths;\n\tint stream;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_dapm_path {\n\tstruct trace_entry ent;\n\tu32 __data_loc_wname;\n\tu32 __data_loc_pname;\n\tu32 __data_loc_pnname;\n\tint path_node;\n\tint path_connect;\n\tint path_dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_dapm_walk_done {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint power_checks;\n\tint path_checks;\n\tint neighbour_checks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_dapm_widget {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_jack_irq {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_jack_notify {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_snd_soc_jack_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint mask;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int sysctl_mem[3];\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_msg_length {\n\tstruct trace_entry ent;\n\tvoid *sk;\n\t__u16 family;\n\t__u16 protocol;\n\tint ret;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_controller {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_mem_start_op {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_op;\n\tu32 __data_loc_data;\n\tu32 data_len;\n\tu32 max_freq;\n\tu8 cmd_buswidth;\n\tbool cmd_dtr;\n\tu8 addr_buswidth;\n\tbool addr_dtr;\n\tu8 dummy_nbytes;\n\tu8 data_buswidth;\n\tbool data_dtr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_mem_stop_op {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_data;\n\tu32 data_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_message {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_message *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_message_done {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_message *msg;\n\tunsigned int frame;\n\tunsigned int actual;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_set_cs {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tlong unsigned int mode;\n\tbool enable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_setup {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tlong unsigned int mode;\n\tunsigned int bits_per_word;\n\tunsigned int max_speed_hz;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_transfer {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_transfer *xfer;\n\tint len;\n\tu32 __data_loc_rx_buf;\n\tu32 __data_loc_tx_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_alloc_arg_err {\n\tstruct trace_entry ent;\n\tunsigned int requested;\n\tunsigned int allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int svc_status;\n\tlong unsigned int auth_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_deferred_event {\n\tstruct trace_entry ent;\n\tconst void *dr;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_pool_thread_event {\n\tstruct trace_entry ent;\n\tunsigned int pool_id;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_process {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 vers;\n\tu32 proc;\n\tu32 __data_loc_service;\n\tu32 __data_loc_procedure;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_replace_page_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tconst void *begin;\n\tconst void *respages;\n\tconst void *nextpage;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tint status;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_stats_latency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int execute;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_unregister {\n\tstruct trace_entry ent;\n\tu32 version;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_msg_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_accept {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_service;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_create_err {\n\tstruct trace_entry ent;\n\tlong int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_dequeue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tlong unsigned int wakeup;\n\tlong unsigned int qtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_enqueue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_accept_class {\n\tstruct trace_entry ent;\n\tlong int status;\n\tu32 __data_loc_service;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_class {\n\tstruct trace_entry ent;\n\tssize_t result;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_lifetime_class {\n\tstruct trace_entry ent;\n\tunsigned int netns_ino;\n\tconst void *svsk;\n\tconst void *sk;\n\tlong unsigned int type;\n\tlong unsigned int family;\n\tlong unsigned int state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_marker {\n\tstruct trace_entry ent;\n\tunsigned int length;\n\tbool last;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_recv_short {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_state {\n\tstruct trace_entry ent;\n\tlong unsigned int socket_state;\n\tlong unsigned int sock_state;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_swiotlb_bounced {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu64 dma_mask;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tbool force;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tu64 clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_prctl_unknown {\n\tstruct trace_entry ent;\n\tint option;\n\tlong unsigned int arg2;\n\tlong unsigned int arg3;\n\tlong unsigned int arg4;\n\tlong unsigned int arg5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tasklet {\n\tstruct trace_entry ent;\n\tvoid *tasklet;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_ao_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\t__u8 keyid;\n\t__u8 rnext;\n\t__u8 maclen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_cong_state_set {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u8 cong_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_hash_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\t__u64 sock_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_ssthresh;\n\t__u32 window_clamp;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_send_reset {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\tenum sk_rst_reason reason;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_sendmsg_locked {\n\tstruct trace_entry ent;\n\tconst void *skb_addr;\n\tint skb_len;\n\tint msg_left;\n\tint size_goal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_cpu_get_power_simple {\n\tstruct trace_entry ent;\n\tint cpu;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_cpu_limit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tunsigned int freq;\n\tlong unsigned int cdev_state;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_devfreq_get_power {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int freq;\n\tu32 busy_time;\n\tu32 total_time;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_devfreq_limit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tunsigned int freq;\n\tlong unsigned int cdev_state;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_temperature {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint temp_prev;\n\tint temp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_zone_trip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint trip;\n\tenum thermal_trip_type trip_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_base_idle {\n\tstruct trace_entry ent;\n\tbool is_idle;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int bucket_expiry;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tls_contenttype {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_child_parent {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_cpu_parent {\n\tstruct trace_entry ent;\n\tvoid *parent;\n\tunsigned int cpu;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_cpugroup {\n\tstruct trace_entry ent;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_and_cpu {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tu32 childmask;\n\tu8 active;\n\tu8 migrator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_set {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_handle_remote {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_idle {\n\tstruct trace_entry ent;\n\tu64 nextevt;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_update_events {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *group;\n\tu64 nextevt;\n\tu64 group_next_expiry;\n\tu64 child_evt_expiry;\n\tunsigned int group_lvl;\n\tunsigned int child_evtcpu;\n\tu8 child_active;\n\tu8 group_active;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_track_foreign_dirty {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tu64 bdi_id;\n\tino_t ino;\n\tunsigned int memcg_id;\n\tino_t cgroup_ino;\n\tino_t page_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udc_log_ep {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int maxpacket;\n\tunsigned int maxpacket_limit;\n\tunsigned int max_streams;\n\tunsigned int mult;\n\tunsigned int maxburst;\n\tu8 address;\n\tbool claimed;\n\tbool enabled;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udc_log_gadget {\n\tstruct trace_entry ent;\n\tenum usb_device_speed speed;\n\tenum usb_device_speed max_speed;\n\tenum usb_device_state state;\n\tunsigned int mA;\n\tunsigned int sg_supported;\n\tunsigned int is_otg;\n\tunsigned int is_a_peripheral;\n\tunsigned int b_hnp_enable;\n\tunsigned int a_hnp_support;\n\tunsigned int hnp_polling_support;\n\tunsigned int host_request_flag;\n\tunsigned int quirk_ep_out_aligned_size;\n\tunsigned int quirk_altset_not_supp;\n\tunsigned int quirk_stall_not_supp;\n\tunsigned int quirk_zlp_not_supp;\n\tunsigned int is_selfpowered;\n\tunsigned int deactivated;\n\tunsigned int connected;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct usb_request;\n\nstruct trace_event_raw_udc_log_req {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int length;\n\tunsigned int actual;\n\tunsigned int num_sgs;\n\tunsigned int num_mapped_sgs;\n\tunsigned int stream_id;\n\tunsigned int no_interrupt;\n\tunsigned int zero;\n\tunsigned int short_not_ok;\n\tint status;\n\tint ret;\n\tstruct usb_request *req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_usb_core_log_usb_device {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum usb_device_speed speed;\n\tenum usb_device_state state;\n\tshort unsigned int bus_mA;\n\tunsigned int authorized;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_set_timeout {\n\tstruct trace_entry ent;\n\tint id;\n\tunsigned int timeout;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_template {\n\tstruct trace_entry ent;\n\tint id;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tu32 __data_loc_workqueue;\n\tint req_cpu;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_folio_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tunsigned int xdp_pass;\n\tunsigned int xdp_drop;\n\tunsigned int xdp_redirect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_dbc_log_request {\n\tstruct trace_entry ent;\n\tstruct dbc_request *req;\n\tbool dir;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctrl_ctx {\n\tstruct trace_entry ent;\n\tu32 drop;\n\tu32 add;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctx {\n\tstruct trace_entry ent;\n\tint ctx_64;\n\tunsigned int ctx_type;\n\tdma_addr_t ctx_dma;\n\tu8 *ctx_va;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_doorbell {\n\tstruct trace_entry ent;\n\tu32 slot;\n\tu32 doorbell;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ep_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu64 deq;\n\tu32 tx_info;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_free_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint slot_id;\n\tu16 current_mel;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_portsc {\n\tstruct trace_entry ent;\n\tu32 busnum;\n\tu32 portnum;\n\tu32 portsc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ring {\n\tstruct trace_entry ent;\n\tu32 type;\n\tvoid *ring;\n\tdma_addr_t enq;\n\tdma_addr_t deq;\n\tunsigned int num_segs;\n\tunsigned int stream_id;\n\tunsigned int cycle_state;\n\tunsigned int bounce_buf_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_slot_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu32 tt_info;\n\tu32 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_stream_ctx {\n\tstruct trace_entry ent;\n\tunsigned int stream_id;\n\tu64 stream_ring;\n\tdma_addr_t ctx_array_dma;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_trb {\n\tstruct trace_entry ent;\n\tdma_addr_t dma;\n\tu32 type;\n\tu32 field0;\n\tu32 field1;\n\tu32 field2;\n\tu32 field3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_urb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tvoid *urb;\n\tunsigned int pipe;\n\tunsigned int stream;\n\tint status;\n\tunsigned int flags;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tint length;\n\tint actual;\n\tint epnum;\n\tint dir_in;\n\tint type;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint devnum;\n\tint state;\n\tint speed;\n\tu8 portnum;\n\tu8 level;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_cong_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tbool wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_ping {\n\tstruct trace_entry ent;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_reserve {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_retransmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint ntrans;\n\tint version;\n\tlong unsigned int timeout;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_transmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_writelock_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_data_ready {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event {\n\tstruct trace_entry ent;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event_done {\n\tstruct trace_entry ent;\n\tint error;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_data {\n\tstruct trace_entry ent;\n\tssize_t err;\n\tsize_t total;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tu32 xid;\n\tlong unsigned int copied;\n\tunsigned int reclen;\n\tunsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n\tint flags;\n};\n\nstruct trace_func_repeats {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int count;\n\tu64 ts_last_call;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n};\n\nstruct trace_min_max_param {\n\tstruct mutex *lock;\n\tu64 *val;\n\tu64 *min;\n\tu64 *max;\n};\n\nstruct trace_mod_entry {\n\tlong unsigned int mod_addr;\n\tchar mod_name[56];\n};\n\nstruct trace_module_delta {\n\tstruct callback_head rcu;\n\tlong int delta[0];\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tbool fail;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nunion upper_chunk;\n\nstruct trace_pid_list {\n\tseqcount_raw_spinlock_t seqcount;\n\traw_spinlock_t lock;\n\tstruct irq_work refill_irqwork;\n\tunion upper_chunk *upper[256];\n\tunion upper_chunk *upper_list;\n\tunion lower_chunk *lower_list;\n\tint free_upper_chunks;\n\tint free_lower_chunks;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nstruct trace_scratch {\n\tunsigned int clock_id;\n\tlong unsigned int text_addr;\n\tlong unsigned int nr_entries;\n\tstruct trace_mod_entry entries[0];\n};\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct eventfs_inode *ei;\n\tint ref_count;\n\tint nr_events;\n};\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tchar *filename;\n\tstruct uprobe *uprobe;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int *nhits;\n\tstruct trace_probe tp;\n};\n\nstruct trace_user_buf {\n\tchar *buf;\n};\n\nstruct trace_user_buf_info {\n\tstruct trace_user_buf *tbuf;\n\tsize_t size;\n\tint ref;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct tracefs_inode {\n\tstruct inode vfs_inode;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tvoid *private;\n};\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct traceprobe_parse_context {\n\tstruct trace_event_call *event;\n\tconst char *funcname;\n\tconst struct btf_type *proto;\n\tconst struct btf_param *params;\n\ts32 nr_params;\n\tstruct btf *btf;\n\tconst struct btf_type *last_type;\n\tu32 last_bitoffs;\n\tu32 last_bitsize;\n\tstruct trace_probe *tp;\n\tunsigned int flags;\n\tint offset;\n};\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u64, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tstruct tracer_flags *default_flags;\n\tint enabled;\n\tbool print_max;\n\tbool allow_instances;\n\tbool noboot;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct tracers {\n\tstruct list_head list;\n\tstruct tracer *tracer;\n\tstruct tracer_flags *flags;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar *cmd;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tdepot_stack_handle_t handle;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n};\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct tty_audit_buf {\n\tstruct mutex mutex;\n\tdev_t dev;\n\tbool icanon;\n\tsize_t valid;\n\tu8 *data;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct tun_security_struct {\n\tu32 sid;\n};\n\nstruct type_datum {\n\tu32 value;\n\tu32 bounds;\n\tunsigned char primary;\n\tunsigned char attribute;\n};\n\nstruct type_set {\n\tstruct ebitmap types;\n\tstruct ebitmap negset;\n\tu32 flags;\n};\n\nstruct typec_connector {\n\tvoid (*attach)(struct typec_connector *, struct device *);\n\tvoid (*deattach)(struct typec_connector *, struct device *);\n};\n\nstruct u32_fract {\n\t__u32 numerator;\n\t__u32 denominator;\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n};\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n\tvoid (*setup_timer)(struct uart_8250_port *);\n};\n\ntypedef struct uart_8250_port *class_serial8250_rpm_t;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tu16 bugs;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tu16 lsr_saved_flags;\n\tu16 lsr_save_mask;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *, bool);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *, bool);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*start_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\ntypedef struct uart_port *class_uart_port_lock_irq_t;\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct uas_cmd_info {\n\tunsigned int state;\n\tunsigned int uas_tag;\n\tstruct urb *cmd_urb;\n\tstruct urb *data_in_urb;\n\tstruct urb *data_out_urb;\n};\n\nstruct usb_anchor {\n\tstruct list_head urb_list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tatomic_t suspend_wakeups;\n\tunsigned int poisoned: 1;\n};\n\nstruct usb_interface;\n\nstruct uas_dev_info {\n\tstruct usb_interface *intf;\n\tstruct usb_device *udev;\n\tstruct usb_anchor cmd_urbs;\n\tstruct usb_anchor sense_urbs;\n\tstruct usb_anchor data_urbs;\n\tu64 flags;\n\tint qdepth;\n\tint resetting;\n\tunsigned int cmd_pipe;\n\tunsigned int status_pipe;\n\tunsigned int data_in_pipe;\n\tunsigned int data_out_pipe;\n\tunsigned int use_streams: 1;\n\tunsigned int shutdown: 1;\n\tstruct scsi_cmnd *cmnd[256];\n\tspinlock_t lock;\n\tstruct work_struct work;\n\tstruct work_struct scan_work;\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[10];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 64;\n\tlong: 64;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n\tu16 len;\n\tbool is_linear;\n\tbool csum_unnecessary;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 64;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\ntypedef struct sk_buff * (*udp_tunnel_gro_rcv_t)(struct sock *, struct list_head *, struct sk_buff *);\n\nstruct udp_tunnel_type_entry {\n\tudp_tunnel_gro_rcv_t gro_receive;\n\trefcount_t count;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct uncharge_gather {\n\tstruct mem_cgroup *memcg;\n\tlong unsigned int nr_memory;\n\tlong unsigned int pgpgout;\n\tlong unsigned int nr_kmem;\n\tint nid;\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_domain {\n\tstruct auth_domain h;\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_gid {\n\tstruct cache_head h;\n\tkuid_t uid;\n\tstruct group_info *gi;\n\tstruct callback_head rcu;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 secid;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\nstruct unwind_stacktrace {\n\tunsigned int nr;\n\tlong unsigned int *entries;\n};\n\nstruct unwind_work;\n\ntypedef void (*unwind_callback_t)(struct unwind_work *, struct unwind_stacktrace *, u64);\n\nstruct unwind_work {\n\tstruct list_head list;\n\tunwind_callback_t func;\n\tint bit;\n};\n\nstruct update_classid_context {\n\tu32 classid;\n\tunsigned int batch;\n};\n\nunion upper_chunk {\n\tunion upper_chunk *next;\n\tunion lower_chunk *data[256];\n};\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct list_head consumers;\n\tstruct inode *inode;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n\tint dsize;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunsigned int depth;\n\tstruct return_instance *return_instances;\n\tstruct return_instance *ri_pool;\n\tstruct timer_list ri_timer;\n\tseqcount_t ri_seqcount;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tbool signal_denied;\n\tstruct arch_uprobe *auprobe;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\ntypedef void (*usb_complete_t)(struct urb *);\n\nstruct usb_iso_packet_descriptor {\n\tunsigned int offset;\n\tunsigned int length;\n\tunsigned int actual_length;\n\tint status;\n};\n\nstruct urb {\n\tstruct kref kref;\n\tint unlinked;\n\tvoid *hcpriv;\n\tatomic_t use_count;\n\tatomic_t reject;\n\tstruct list_head urb_list;\n\tstruct list_head anchor_list;\n\tstruct usb_anchor *anchor;\n\tstruct usb_device *dev;\n\tstruct usb_host_endpoint *ep;\n\tunsigned int pipe;\n\tunsigned int stream_id;\n\tint status;\n\tunsigned int transfer_flags;\n\tvoid *transfer_buffer;\n\tdma_addr_t transfer_dma;\n\tstruct scatterlist *sg;\n\tstruct sg_table *sgt;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tu32 transfer_buffer_length;\n\tu32 actual_length;\n\tunsigned char *setup_packet;\n\tdma_addr_t setup_dma;\n\tint start_frame;\n\tint number_of_packets;\n\tint interval;\n\tint error_count;\n\tvoid *context;\n\tusb_complete_t complete;\n\tstruct usb_iso_packet_descriptor iso_frame_desc[0];\n};\n\nstruct urb_priv {\n\tstruct ed *ed;\n\tu16 length;\n\tu16 td_cnt;\n\tstruct list_head pending;\n\tstruct td *td[0];\n};\n\nstruct xhci_segment;\n\nstruct xhci_td {\n\tstruct list_head td_list;\n\tstruct list_head cancelled_td_list;\n\tint status;\n\tenum xhci_cancelled_td_status cancel_status;\n\tstruct urb *urb;\n\tstruct xhci_segment *start_seg;\n\tunion xhci_trb *start_trb;\n\tstruct xhci_segment *end_seg;\n\tunion xhci_trb *end_trb;\n\tstruct xhci_segment *bounce_seg;\n\tbool urb_length_set;\n\tbool error_mid_td;\n};\n\nstruct urb_priv___2 {\n\tint num_tds;\n\tint num_tds_done;\n\tstruct xhci_td td[0];\n};\n\ntypedef struct urb_priv urb_priv_t;\n\nstruct us_data;\n\ntypedef int (*trans_cmnd)(struct scsi_cmnd *, struct us_data *);\n\ntypedef int (*trans_reset)(struct us_data *);\n\ntypedef void (*proto_cmnd)(struct scsi_cmnd *, struct us_data *);\n\nstruct usb_sg_request {\n\tint status;\n\tsize_t bytes;\n\tspinlock_t lock;\n\tstruct usb_device *dev;\n\tint pipe;\n\tint entries;\n\tstruct urb **urbs;\n\tint count;\n\tstruct completion complete;\n};\n\ntypedef void (*extra_data_destructor)(void *);\n\ntypedef void (*pm_hook)(struct us_data *, int);\n\nstruct us_unusual_dev;\n\nstruct usb_ctrlrequest;\n\nstruct us_data {\n\tstruct mutex dev_mutex;\n\tstruct usb_device *pusb_dev;\n\tstruct usb_interface *pusb_intf;\n\tconst struct us_unusual_dev *unusual_dev;\n\tu64 fflags;\n\tlong unsigned int dflags;\n\tunsigned int send_bulk_pipe;\n\tunsigned int recv_bulk_pipe;\n\tunsigned int send_ctrl_pipe;\n\tunsigned int recv_ctrl_pipe;\n\tunsigned int recv_intr_pipe;\n\tchar *transport_name;\n\tchar *protocol_name;\n\t__le32 bcs_signature;\n\tu8 subclass;\n\tu8 protocol;\n\tu8 max_lun;\n\tu8 ifnum;\n\tu8 ep_bInterval;\n\ttrans_cmnd transport;\n\ttrans_reset transport_reset;\n\tproto_cmnd proto_handler;\n\tstruct scsi_cmnd *srb;\n\tunsigned int tag;\n\tchar scsi_name[32];\n\tstruct urb *current_urb;\n\tstruct usb_ctrlrequest *cr;\n\tstruct usb_sg_request current_sg;\n\tunsigned char *iobuf;\n\tdma_addr_t iobuf_dma;\n\tstruct task_struct *ctl_thread;\n\tstruct completion cmnd_ready;\n\tstruct completion notify;\n\twait_queue_head_t delay_wait;\n\tstruct delayed_work scan_dwork;\n\tvoid *extra;\n\textra_data_destructor extra_destructor;\n\tpm_hook suspend_resume_hook;\n\tint use_last_sector_hacks;\n\tint last_sector_retries;\n};\n\nstruct us_unusual_dev {\n\tconst char *vendorName;\n\tconst char *productName;\n\t__u8 useProtocol;\n\t__u8 useTransport;\n\tint (*initFunction)(struct us_data *);\n};\n\nstruct usage_priority {\n\t__u32 usage;\n\tbool global;\n\tunsigned int slot_overwrite;\n};\n\nstruct usb2_lpm_parameters {\n\tunsigned int besl;\n\tint timeout;\n};\n\nstruct usb3_lpm_parameters {\n\tunsigned int mel;\n\tunsigned int pel;\n\tunsigned int sel;\n\tint timeout;\n};\n\nstruct usb_bos_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumDeviceCaps;\n} __attribute__((packed));\n\nstruct usb_bus {\n\tstruct device *controller;\n\tstruct device *sysdev;\n\tint busnum;\n\tconst char *bus_name;\n\tu8 uses_pio_for_control;\n\tu8 otg_port;\n\tunsigned int is_b_host: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int no_stop_on_short: 1;\n\tunsigned int no_sg_constraint: 1;\n\tunsigned int sg_tablesize;\n\tint devnum_next;\n\tstruct mutex devnum_next_mutex;\n\tlong unsigned int devmap[2];\n\tstruct usb_device *root_hub;\n\tstruct usb_bus *hs_companion;\n\tint bandwidth_allocated;\n\tint bandwidth_int_reqs;\n\tint bandwidth_isoc_reqs;\n\tunsigned int resuming_ports;\n};\n\nstruct usb_cdc_acm_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n};\n\nstruct usb_cdc_call_mgmt_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n\t__u8 bDataInterface;\n};\n\nstruct usb_cdc_country_functional_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iCountryCodeRelDate;\n\tunion {\n\t\t__le16 wCountryCode0;\n\t\tstruct {\n\t\t\tstruct {} __empty_wCountryCodes;\n\t\t\t__le16 wCountryCodes[0];\n\t\t};\n\t};\n};\n\nstruct usb_cdc_dmm_desc {\n\t__u8 bFunctionLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubtype;\n\t__u16 bcdVersion;\n\t__le16 wMaxCommand;\n} __attribute__((packed));\n\nstruct usb_cdc_ether_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iMACAddress;\n\t__le32 bmEthernetStatistics;\n\t__le16 wMaxSegmentSize;\n\t__le16 wNumberMCFilters;\n\t__u8 bNumberPowerFilters;\n} __attribute__((packed));\n\nstruct usb_cdc_header_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdCDC;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMVersion;\n\t__le16 wMaxControlMessage;\n\t__u8 bNumberFilters;\n\t__u8 bMaxFilterSize;\n\t__le16 wMaxSegmentSize;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_extended_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMExtendedVersion;\n\t__u8 bMaxOutstandingCommandMessages;\n\t__le16 wMTU;\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n\t__u8 bGUID[16];\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_detail_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bGuidDescriptorType;\n\t__u8 bDetailData[0];\n};\n\nstruct usb_cdc_ncm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdNcmVersion;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_network_terminal_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bEntityId;\n\t__u8 iName;\n\t__u8 bChannelIndex;\n\t__u8 bPhysicalInterface;\n};\n\nstruct usb_cdc_obex_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n} __attribute__((packed));\n\nstruct usb_cdc_union_desc;\n\nstruct usb_cdc_parsed_header {\n\tstruct usb_cdc_union_desc *usb_cdc_union_desc;\n\tstruct usb_cdc_header_desc *usb_cdc_header_desc;\n\tstruct usb_cdc_call_mgmt_descriptor *usb_cdc_call_mgmt_descriptor;\n\tstruct usb_cdc_acm_descriptor *usb_cdc_acm_descriptor;\n\tstruct usb_cdc_country_functional_desc *usb_cdc_country_functional_desc;\n\tstruct usb_cdc_network_terminal_desc *usb_cdc_network_terminal_desc;\n\tstruct usb_cdc_ether_desc *usb_cdc_ether_desc;\n\tstruct usb_cdc_dmm_desc *usb_cdc_dmm_desc;\n\tstruct usb_cdc_mdlm_desc *usb_cdc_mdlm_desc;\n\tstruct usb_cdc_mdlm_detail_desc *usb_cdc_mdlm_detail_desc;\n\tstruct usb_cdc_obex_desc *usb_cdc_obex_desc;\n\tstruct usb_cdc_ncm_desc *usb_cdc_ncm_desc;\n\tstruct usb_cdc_mbim_desc *usb_cdc_mbim_desc;\n\tstruct usb_cdc_mbim_extended_desc *usb_cdc_mbim_extended_desc;\n\tbool phonet_magic_present;\n};\n\nstruct usb_cdc_union_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bMasterInterface0;\n\tunion {\n\t\t__u8 bSlaveInterface0;\n\t\tstruct {\n\t\t\tstruct {} __empty_bSlaveInterfaces;\n\t\t\t__u8 bSlaveInterfaces[0];\n\t\t};\n\t};\n};\n\nstruct usb_charger_current {\n\tunsigned int sdp_min;\n\tunsigned int sdp_max;\n\tunsigned int dcp_min;\n\tunsigned int dcp_max;\n\tunsigned int cdp_min;\n\tunsigned int cdp_max;\n\tunsigned int aca_min;\n\tunsigned int aca_max;\n};\n\nstruct usb_class_driver {\n\tchar *name;\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tconst struct file_operations *fops;\n\tint minor_base;\n};\n\nstruct usb_config_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumInterfaces;\n\t__u8 bConfigurationValue;\n\t__u8 iConfiguration;\n\t__u8 bmAttributes;\n\t__u8 bMaxPower;\n} __attribute__((packed));\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_dcd_config_params {\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n\t__u8 besl_baseline;\n\t__u8 besl_deep;\n};\n\nstruct usb_descriptor_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n};\n\nstruct usb_dev_cap_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_dev_state {\n\tstruct list_head list;\n\tstruct usb_device *dev;\n\tstruct file *file;\n\tspinlock_t lock;\n\tstruct list_head async_pending;\n\tstruct list_head async_completed;\n\tstruct list_head memory_list;\n\twait_queue_head_t wait;\n\twait_queue_head_t wait_for_resume;\n\tunsigned int discsignr;\n\tstruct pid *disc_pid;\n\tconst struct cred *cred;\n\tsigval_t disccontext;\n\tlong unsigned int ifclaimed;\n\tu32 disabled_bulk_eps;\n\tlong unsigned int interface_allowed_mask;\n\tint not_yet_resumed;\n\tbool suspend_allowed;\n\tbool privileges_dropped;\n};\n\nstruct usb_endpoint_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bEndpointAddress;\n\t__u8 bmAttributes;\n\t__le16 wMaxPacketSize;\n\t__u8 bInterval;\n\t__u8 bRefresh;\n\t__u8 bSynchAddress;\n} __attribute__((packed));\n\nstruct usb_ss_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bMaxBurst;\n\t__u8 bmAttributes;\n\t__le16 wBytesPerInterval;\n};\n\nstruct usb_ssp_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wReseved;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_eusb2_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wMaxPacketSize;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_host_endpoint {\n\tstruct usb_endpoint_descriptor desc;\n\tstruct usb_ss_ep_comp_descriptor ss_ep_comp;\n\tstruct usb_ssp_isoc_ep_comp_descriptor ssp_isoc_ep_comp;\n\tstruct usb_eusb2_isoc_ep_comp_descriptor eusb2_isoc_ep_comp;\n\tlong: 0;\n\tstruct list_head urb_list;\n\tvoid *hcpriv;\n\tstruct ep_device *ep_dev;\n\tunsigned char *extra;\n\tint extralen;\n\tint enabled;\n\tint streams;\n\tlong: 0;\n} __attribute__((packed));\n\nstruct usb_device_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__le16 idVendor;\n\t__le16 idProduct;\n\t__le16 bcdDevice;\n\t__u8 iManufacturer;\n\t__u8 iProduct;\n\t__u8 iSerialNumber;\n\t__u8 bNumConfigurations;\n};\n\nstruct usb_host_bos;\n\nstruct usb_host_config;\n\nstruct usb_device {\n\tint devnum;\n\tchar devpath[16];\n\tu32 route;\n\tenum usb_device_state state;\n\tenum usb_device_speed speed;\n\tunsigned int rx_lanes;\n\tunsigned int tx_lanes;\n\tenum usb_ssp_rate ssp_rate;\n\tstruct usb_tt *tt;\n\tint ttport;\n\tunsigned int toggle[2];\n\tstruct usb_device *parent;\n\tstruct usb_bus *bus;\n\tstruct usb_host_endpoint ep0;\n\tstruct device dev;\n\tstruct usb_device_descriptor descriptor;\n\tstruct usb_host_bos *bos;\n\tstruct usb_host_config *config;\n\tstruct usb_host_config *actconfig;\n\tstruct usb_host_endpoint *ep_in[16];\n\tstruct usb_host_endpoint *ep_out[16];\n\tchar **rawdescriptors;\n\tshort unsigned int bus_mA;\n\tu8 portnum;\n\tu8 level;\n\tu8 devaddr;\n\tunsigned int can_submit: 1;\n\tunsigned int persist_enabled: 1;\n\tunsigned int reset_in_progress: 1;\n\tunsigned int have_langid: 1;\n\tunsigned int authorized: 1;\n\tunsigned int authenticated: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int lpm_devinit_allow: 1;\n\tunsigned int usb2_hw_lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_besl_capable: 1;\n\tunsigned int usb2_hw_lpm_enabled: 1;\n\tunsigned int usb2_hw_lpm_allowed: 1;\n\tunsigned int usb3_lpm_u1_enabled: 1;\n\tunsigned int usb3_lpm_u2_enabled: 1;\n\tint string_langid;\n\tchar *product;\n\tchar *manufacturer;\n\tchar *serial;\n\tstruct list_head filelist;\n\tint maxchild;\n\tu32 quirks;\n\tatomic_t urbnum;\n\tlong unsigned int active_duration;\n\tlong unsigned int connect_time;\n\tunsigned int do_remote_wakeup: 1;\n\tunsigned int reset_resume: 1;\n\tunsigned int port_is_suspended: 1;\n\tunsigned int offload_at_suspend: 1;\n\tint offload_usage;\n\tenum usb_link_tunnel_mode tunnel_mode;\n\tstruct device_link *usb4_link;\n\tint slot_id;\n\tstruct usb2_lpm_parameters l1_params;\n\tstruct usb3_lpm_parameters u1_params;\n\tstruct usb3_lpm_parameters u2_params;\n\tunsigned int lpm_disable_count;\n\tu16 hub_delay;\n\tunsigned int use_generic_driver: 1;\n};\n\nstruct usb_device_id;\n\nstruct usb_device_driver {\n\tconst char *name;\n\tbool (*match)(struct usb_device *);\n\tint (*probe)(struct usb_device *);\n\tvoid (*disconnect)(struct usb_device *);\n\tint (*suspend)(struct usb_device *, pm_message_t);\n\tint (*resume)(struct usb_device *, pm_message_t);\n\tint (*choose_configuration)(struct usb_device *);\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tconst struct usb_device_id *id_table;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int generic_subclass: 1;\n};\n\nstruct usb_device_id {\n\t__u16 match_flags;\n\t__u16 idVendor;\n\t__u16 idProduct;\n\t__u16 bcdDevice_lo;\n\t__u16 bcdDevice_hi;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 bInterfaceNumber;\n\tkernel_ulong_t driver_info;\n};\n\nstruct usb_dynids {\n\tstruct list_head list;\n};\n\nstruct usb_driver {\n\tconst char *name;\n\tint (*probe)(struct usb_interface *, const struct usb_device_id *);\n\tvoid (*disconnect)(struct usb_interface *);\n\tint (*unlocked_ioctl)(struct usb_interface *, unsigned int, void *);\n\tint (*suspend)(struct usb_interface *, pm_message_t);\n\tint (*resume)(struct usb_interface *);\n\tint (*reset_resume)(struct usb_interface *);\n\tint (*pre_reset)(struct usb_interface *);\n\tint (*post_reset)(struct usb_interface *);\n\tvoid (*shutdown)(struct usb_interface *);\n\tconst struct usb_device_id *id_table;\n\tconst struct attribute_group **dev_groups;\n\tstruct usb_dynids dynids;\n\tstruct device_driver driver;\n\tunsigned int no_dynamic_id: 1;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int disable_hub_initiated_lpm: 1;\n\tunsigned int soft_unbind: 1;\n};\n\nstruct usb_dynid {\n\tstruct list_head node;\n\tstruct usb_device_id id;\n};\n\nstruct usb_ehci_pdata {\n\tint caps_offset;\n\tunsigned int has_tt: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int no_io_watchdog: 1;\n\tunsigned int reset_on_resume: 1;\n\tunsigned int dma_mask_64: 1;\n\tunsigned int spurious_oc: 1;\n\tint (*power_on)(struct platform_device *);\n\tvoid (*power_off)(struct platform_device *);\n\tvoid (*power_suspend)(struct platform_device *);\n\tint (*pre_setup)(struct usb_hcd *);\n};\n\nstruct usb_ep_caps {\n\tunsigned int type_control: 1;\n\tunsigned int type_iso: 1;\n\tunsigned int type_bulk: 1;\n\tunsigned int type_int: 1;\n\tunsigned int dir_in: 1;\n\tunsigned int dir_out: 1;\n};\n\nstruct usb_ep_ops;\n\nstruct usb_ep {\n\tvoid *driver_data;\n\tconst char *name;\n\tconst struct usb_ep_ops *ops;\n\tconst struct usb_endpoint_descriptor *desc;\n\tconst struct usb_ss_ep_comp_descriptor *comp_desc;\n\tstruct list_head ep_list;\n\tstruct usb_ep_caps caps;\n\tbool claimed;\n\tbool enabled;\n\tunsigned int mult: 2;\n\tunsigned int maxburst: 5;\n\tu8 address;\n\tu16 maxpacket;\n\tu16 maxpacket_limit;\n\tu16 max_streams;\n};\n\nstruct usb_ep_ops {\n\tint (*enable)(struct usb_ep *, const struct usb_endpoint_descriptor *);\n\tint (*disable)(struct usb_ep *);\n\tvoid (*dispose)(struct usb_ep *);\n\tstruct usb_request * (*alloc_request)(struct usb_ep *, gfp_t);\n\tvoid (*free_request)(struct usb_ep *, struct usb_request *);\n\tint (*queue)(struct usb_ep *, struct usb_request *, gfp_t);\n\tint (*dequeue)(struct usb_ep *, struct usb_request *);\n\tint (*set_halt)(struct usb_ep *, int);\n\tint (*set_wedge)(struct usb_ep *);\n\tint (*fifo_status)(struct usb_ep *);\n\tvoid (*fifo_flush)(struct usb_ep *);\n};\n\nstruct usb_ext_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__le32 bmAttributes;\n} __attribute__((packed));\n\nstruct usb_udc;\n\nstruct usb_gadget_ops;\n\nstruct usb_otg_caps;\n\nstruct usb_gadget {\n\tstruct work_struct work;\n\tstruct usb_udc *udc;\n\tconst struct usb_gadget_ops *ops;\n\tstruct usb_ep *ep0;\n\tstruct list_head ep_list;\n\tenum usb_device_speed speed;\n\tenum usb_device_speed max_speed;\n\tenum usb_ssp_rate ssp_rate;\n\tenum usb_ssp_rate max_ssp_rate;\n\tenum usb_device_state state;\n\tspinlock_t state_lock;\n\tbool teardown;\n\tconst char *name;\n\tstruct device dev;\n\tunsigned int isoch_delay;\n\tunsigned int out_epnum;\n\tunsigned int in_epnum;\n\tunsigned int mA;\n\tstruct usb_otg_caps *otg_caps;\n\tunsigned int sg_supported: 1;\n\tunsigned int is_otg: 1;\n\tunsigned int is_a_peripheral: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int a_hnp_support: 1;\n\tunsigned int a_alt_hnp_support: 1;\n\tunsigned int hnp_polling_support: 1;\n\tunsigned int host_request_flag: 1;\n\tunsigned int quirk_ep_out_aligned_size: 1;\n\tunsigned int quirk_altset_not_supp: 1;\n\tunsigned int quirk_stall_not_supp: 1;\n\tunsigned int quirk_zlp_not_supp: 1;\n\tunsigned int quirk_avoids_skb_reserve: 1;\n\tunsigned int is_selfpowered: 1;\n\tunsigned int deactivated: 1;\n\tunsigned int connected: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int wakeup_capable: 1;\n\tunsigned int wakeup_armed: 1;\n\tint irq;\n\tint id_number;\n};\n\nstruct usb_gadget_driver {\n\tchar *function;\n\tenum usb_device_speed max_speed;\n\tint (*bind)(struct usb_gadget *, struct usb_gadget_driver *);\n\tvoid (*unbind)(struct usb_gadget *);\n\tint (*setup)(struct usb_gadget *, const struct usb_ctrlrequest *);\n\tvoid (*disconnect)(struct usb_gadget *);\n\tvoid (*suspend)(struct usb_gadget *);\n\tvoid (*resume)(struct usb_gadget *);\n\tvoid (*reset)(struct usb_gadget *);\n\tstruct device_driver driver;\n\tchar *udc_name;\n\tunsigned int match_existing_only: 1;\n\tbool is_bound: 1;\n};\n\nstruct usb_gadget_ops {\n\tint (*get_frame)(struct usb_gadget *);\n\tint (*wakeup)(struct usb_gadget *);\n\tint (*func_wakeup)(struct usb_gadget *, int);\n\tint (*set_remote_wakeup)(struct usb_gadget *, int);\n\tint (*set_selfpowered)(struct usb_gadget *, int);\n\tint (*vbus_session)(struct usb_gadget *, int);\n\tint (*vbus_draw)(struct usb_gadget *, unsigned int);\n\tint (*pullup)(struct usb_gadget *, int);\n\tint (*ioctl)(struct usb_gadget *, unsigned int, long unsigned int);\n\tvoid (*get_config_params)(struct usb_gadget *, struct usb_dcd_config_params *);\n\tint (*udc_start)(struct usb_gadget *, struct usb_gadget_driver *);\n\tint (*udc_stop)(struct usb_gadget *);\n\tvoid (*udc_set_speed)(struct usb_gadget *, enum usb_device_speed);\n\tvoid (*udc_set_ssp_rate)(struct usb_gadget *, enum usb_ssp_rate);\n\tvoid (*udc_async_callbacks)(struct usb_gadget *, bool);\n\tstruct usb_ep * (*match_ep)(struct usb_gadget *, struct usb_endpoint_descriptor *, struct usb_ss_ep_comp_descriptor *);\n\tint (*check_config)(struct usb_gadget *);\n};\n\nstruct usb_phy_roothub;\n\nstruct usb_hcd {\n\tstruct usb_bus self;\n\tstruct kref kref;\n\tconst char *product_desc;\n\tint speed;\n\tchar irq_descr[24];\n\tstruct timer_list rh_timer;\n\tstruct urb *status_urb;\n\tstruct work_struct wakeup_work;\n\tstruct work_struct died_work;\n\tconst struct hc_driver *driver;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_phy_roothub *phy_roothub;\n\tlong unsigned int flags;\n\tenum usb_dev_authorize_policy dev_policy;\n\tunsigned int rh_registered: 1;\n\tunsigned int rh_pollable: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int msi_enabled: 1;\n\tunsigned int skip_phy_initialization: 1;\n\tunsigned int uses_new_polling: 1;\n\tunsigned int has_tt: 1;\n\tunsigned int amd_resume_bug: 1;\n\tunsigned int can_do_streams: 1;\n\tunsigned int tpl_support: 1;\n\tunsigned int cant_recv_wakeups: 1;\n\tunsigned int irq;\n\tvoid *regs;\n\tresource_size_t rsrc_start;\n\tresource_size_t rsrc_len;\n\tunsigned int power_budget;\n\tstruct giveback_urb_bh high_prio_bh;\n\tstruct giveback_urb_bh low_prio_bh;\n\tstruct mutex *address0_mutex;\n\tstruct mutex *bandwidth_mutex;\n\tstruct usb_hcd *shared_hcd;\n\tstruct usb_hcd *primary_hcd;\n\tstruct dma_pool *pool[4];\n\tint state;\n\tstruct gen_pool *localmem_pool;\n\tlong unsigned int hcd_priv[0];\n};\n\nstruct usb_ss_cap_descriptor;\n\nstruct usb_ssp_cap_descriptor;\n\nstruct usb_ss_container_id_descriptor;\n\nstruct usb_ptm_cap_descriptor;\n\nstruct usb_host_bos {\n\tstruct usb_bos_descriptor *desc;\n\tstruct usb_ext_cap_descriptor *ext_cap;\n\tstruct usb_ss_cap_descriptor *ss_cap;\n\tstruct usb_ssp_cap_descriptor *ssp_cap;\n\tstruct usb_ss_container_id_descriptor *ss_id;\n\tstruct usb_ptm_cap_descriptor *ptm_cap;\n};\n\nstruct usb_interface_assoc_descriptor;\n\nstruct usb_interface_cache;\n\nstruct usb_host_config {\n\tstruct usb_config_descriptor desc;\n\tchar *string;\n\tstruct usb_interface_assoc_descriptor *intf_assoc[16];\n\tstruct usb_interface *interface[32];\n\tstruct usb_interface_cache *intf_cache[32];\n\tunsigned char *extra;\n\tint extralen;\n};\n\nstruct usb_interface_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bInterfaceNumber;\n\t__u8 bAlternateSetting;\n\t__u8 bNumEndpoints;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 iInterface;\n};\n\nstruct usb_host_interface {\n\tstruct usb_interface_descriptor desc;\n\tint extralen;\n\tunsigned char *extra;\n\tstruct usb_host_endpoint *endpoint;\n\tchar *string;\n};\n\nstruct usb_hub_status {\n\t__le16 wHubStatus;\n\t__le16 wHubChange;\n};\n\nstruct usb_port_status {\n\t__le16 wPortStatus;\n\t__le16 wPortChange;\n\t__le32 dwExtPortStatus;\n};\n\nstruct usb_tt {\n\tstruct usb_device *hub;\n\tint multi;\n\tunsigned int think_time;\n\tvoid *hcpriv;\n\tspinlock_t lock;\n\tstruct list_head clear_list;\n\tstruct work_struct clear_work;\n};\n\nstruct usb_hub_descriptor;\n\nstruct usb_port;\n\nstruct usb_hub {\n\tstruct device *intfdev;\n\tstruct usb_device *hdev;\n\tstruct kref kref;\n\tstruct urb *urb;\n\tu8 (*buffer)[8];\n\tunion {\n\t\tstruct usb_hub_status hub;\n\t\tstruct usb_port_status port;\n\t} *status;\n\tstruct mutex status_mutex;\n\tint error;\n\tint nerrors;\n\tlong unsigned int event_bits[1];\n\tlong unsigned int change_bits[1];\n\tlong unsigned int removed_bits[1];\n\tlong unsigned int wakeup_bits[1];\n\tlong unsigned int power_bits[1];\n\tlong unsigned int child_usage_bits[1];\n\tlong unsigned int warm_reset_bits[1];\n\tstruct usb_hub_descriptor *descriptor;\n\tstruct usb_tt tt;\n\tunsigned int mA_per_port;\n\tunsigned int wakeup_enabled_descendants;\n\tunsigned int limited_power: 1;\n\tunsigned int quiescing: 1;\n\tunsigned int disconnected: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int quirk_disable_autosuspend: 1;\n\tunsigned int quirk_check_port_auto_suspend: 1;\n\tunsigned int has_indicators: 1;\n\tu8 indicator[31];\n\tstruct delayed_work leds;\n\tstruct delayed_work init_work;\n\tstruct delayed_work post_resume_work;\n\tstruct work_struct events;\n\tspinlock_t irq_urb_lock;\n\tstruct timer_list irq_urb_retry;\n\tstruct usb_port **ports;\n\tstruct list_head onboard_devs;\n};\n\nstruct usb_hub_descriptor {\n\t__u8 bDescLength;\n\t__u8 bDescriptorType;\n\t__u8 bNbrPorts;\n\t__le16 wHubCharacteristics;\n\t__u8 bPwrOn2PwrGood;\n\t__u8 bHubContrCurrent;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 DeviceRemovable[4];\n\t\t\t__u8 PortPwrCtrlMask[4];\n\t\t} hs;\n\t\tstruct {\n\t\t\t__u8 bHubHdrDecLat;\n\t\t\t__le16 wHubDelay;\n\t\t\t__le16 DeviceRemovable;\n\t\t} __attribute__((packed)) ss;\n\t} u;\n} __attribute__((packed));\n\nstruct usb_interface {\n\tstruct usb_host_interface *altsetting;\n\tstruct usb_host_interface *cur_altsetting;\n\tunsigned int num_altsetting;\n\tstruct usb_interface_assoc_descriptor *intf_assoc;\n\tint minor;\n\tenum usb_interface_condition condition;\n\tunsigned int sysfs_files_created: 1;\n\tunsigned int ep_devs_created: 1;\n\tunsigned int unregistering: 1;\n\tunsigned int needs_remote_wakeup: 1;\n\tunsigned int needs_altsetting0: 1;\n\tunsigned int needs_binding: 1;\n\tunsigned int resetting_device: 1;\n\tunsigned int authorized: 1;\n\tenum usb_wireless_status wireless_status;\n\tstruct work_struct wireless_status_work;\n\tstruct device dev;\n\tstruct device *usb_dev;\n\tstruct work_struct reset_ws;\n};\n\nstruct usb_interface_assoc_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bFirstInterface;\n\t__u8 bInterfaceCount;\n\t__u8 bFunctionClass;\n\t__u8 bFunctionSubClass;\n\t__u8 bFunctionProtocol;\n\t__u8 iFunction;\n};\n\nstruct usb_interface_cache {\n\tunsigned int num_altsetting;\n\tstruct kref ref;\n\tstruct usb_host_interface altsetting[0];\n};\n\nstruct usb_memory {\n\tstruct list_head memlist;\n\tint vma_use_count;\n\tint urb_use_count;\n\tu32 size;\n\tvoid *mem;\n\tdma_addr_t dma_handle;\n\tlong unsigned int vm_start;\n\tstruct usb_dev_state *ps;\n};\n\nstruct usb_ohci_pdata {\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int no_big_frame_no: 1;\n\tunsigned int num_ports;\n\tint (*power_on)(struct platform_device *);\n\tvoid (*power_off)(struct platform_device *);\n\tvoid (*power_suspend)(struct platform_device *);\n};\n\nstruct usb_otg {\n\tu8 default_a;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_bus *host;\n\tstruct usb_gadget *gadget;\n\tenum usb_otg_state state;\n\tint (*set_host)(struct usb_otg *, struct usb_bus *);\n\tint (*set_peripheral)(struct usb_otg *, struct usb_gadget *);\n\tint (*set_vbus)(struct usb_otg *, bool);\n\tint (*start_srp)(struct usb_otg *);\n\tint (*start_hnp)(struct usb_otg *);\n};\n\nstruct usb_otg_caps {\n\tu16 otg_rev;\n\tbool hnp_support;\n\tbool srp_support;\n\tbool adp_support;\n};\n\nstruct usb_otg_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bmAttributes;\n};\n\nstruct usb_phy_io_ops;\n\nstruct usb_phy {\n\tstruct device *dev;\n\tconst char *label;\n\tunsigned int flags;\n\tenum usb_phy_type type;\n\tenum usb_phy_events last_event;\n\tstruct usb_otg *otg;\n\tstruct device *io_dev;\n\tstruct usb_phy_io_ops *io_ops;\n\tvoid *io_priv;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *id_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct notifier_block type_nb;\n\tenum usb_charger_type chg_type;\n\tenum usb_charger_state chg_state;\n\tstruct usb_charger_current chg_cur;\n\tstruct work_struct chg_work;\n\tstruct atomic_notifier_head notifier;\n\tu16 port_status;\n\tu16 port_change;\n\tstruct list_head head;\n\tint (*init)(struct usb_phy *);\n\tvoid (*shutdown)(struct usb_phy *);\n\tint (*set_vbus)(struct usb_phy *, int);\n\tint (*set_power)(struct usb_phy *, unsigned int);\n\tint (*set_suspend)(struct usb_phy *, int);\n\tint (*set_wakeup)(struct usb_phy *, bool);\n\tint (*notify_connect)(struct usb_phy *, enum usb_device_speed);\n\tint (*notify_disconnect)(struct usb_phy *, enum usb_device_speed);\n\tenum usb_charger_type (*charger_detect)(struct usb_phy *);\n};\n\nstruct usb_phy_io_ops {\n\tint (*read)(struct usb_phy *, u32);\n\tint (*write)(struct usb_phy *, u32, u32);\n};\n\nstruct usb_phy_roothub {\n\tstruct phy *phy;\n\tstruct list_head list;\n};\n\nstruct usb_port {\n\tstruct usb_device *child;\n\tstruct device dev;\n\tstruct usb_dev_state *port_owner;\n\tstruct usb_port *peer;\n\tstruct typec_connector *connector;\n\tstruct dev_pm_qos_request *req;\n\tenum usb_port_connect_type connect_type;\n\tenum usb_device_state state;\n\tstruct kernfs_node *state_kn;\n\tusb_port_location_t location;\n\tstruct mutex status_lock;\n\tu32 over_current_count;\n\tu8 portnum;\n\tu32 quirks;\n\tunsigned int early_stop: 1;\n\tunsigned int ignore_event: 1;\n\tunsigned int is_superspeed: 1;\n\tunsigned int usb3_lpm_u1_permit: 1;\n\tunsigned int usb3_lpm_u2_permit: 1;\n};\n\nstruct usb_ptm_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_qualifier_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__u8 bNumConfigurations;\n\t__u8 bRESERVED;\n};\n\nstruct usb_request {\n\tstruct usb_ep *ep;\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tstruct scatterlist *sg;\n\tunsigned int num_sgs;\n\tunsigned int num_mapped_sgs;\n\tunsigned int stream_id: 16;\n\tunsigned int is_last: 1;\n\tunsigned int no_interrupt: 1;\n\tunsigned int zero: 1;\n\tunsigned int short_not_ok: 1;\n\tunsigned int dma_mapped: 1;\n\tunsigned int sg_was_mapped: 1;\n\tvoid (*complete)(struct usb_ep *, struct usb_request *);\n\tvoid *context;\n\tstruct list_head list;\n\tunsigned int frame_number;\n\tint status;\n\tunsigned int actual;\n};\n\nstruct usb_set_sel_req {\n\t__u8 u1_sel;\n\t__u8 u1_pel;\n\t__le16 u2_sel;\n\t__le16 u2_pel;\n};\n\nstruct usb_ss_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bmAttributes;\n\t__le16 wSpeedSupported;\n\t__u8 bFunctionalitySupport;\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n};\n\nstruct usb_ss_container_id_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__u8 ContainerID[16];\n};\n\nstruct usb_ssp_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__le32 bmAttributes;\n\t__le16 wFunctionalitySupport;\n\t__le16 wReserved;\n\tunion {\n\t\t__le32 legacy_padding;\n\t\tstruct {\n\t\t\tstruct {} __empty_bmSublinkSpeedAttr;\n\t\t\t__le32 bmSublinkSpeedAttr[0];\n\t\t};\n\t};\n};\n\nstruct usb_tt_clear {\n\tstruct list_head clear_list;\n\tunsigned int tt;\n\tu16 devinfo;\n\tstruct usb_hcd *hcd;\n\tstruct usb_host_endpoint *ep;\n};\n\nstruct usb_udc {\n\tstruct usb_gadget_driver *driver;\n\tstruct usb_gadget *gadget;\n\tstruct device dev;\n\tstruct list_head list;\n\tbool vbus;\n\tbool started;\n\tbool allow_connect;\n\tstruct work_struct vbus_work;\n\tstruct mutex connect_lock;\n};\n\nstruct usbdevfs_bulktransfer {\n\tunsigned int ep;\n\tunsigned int len;\n\tunsigned int timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_bulktransfer32 {\n\tcompat_uint_t ep;\n\tcompat_uint_t len;\n\tcompat_uint_t timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_connectinfo {\n\tunsigned int devnum;\n\tunsigned char slow;\n};\n\nstruct usbdevfs_conninfo_ex {\n\t__u32 size;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 speed;\n\t__u8 num_ports;\n\t__u8 ports[7];\n};\n\nstruct usbdevfs_ctrltransfer {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\t__u32 timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_ctrltransfer32 {\n\tu8 bRequestType;\n\tu8 bRequest;\n\tu16 wValue;\n\tu16 wIndex;\n\tu16 wLength;\n\tu32 timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_disconnect_claim {\n\tunsigned int interface;\n\tunsigned int flags;\n\tchar driver[256];\n};\n\nstruct usbdevfs_disconnectsignal {\n\tunsigned int signr;\n\tvoid *context;\n};\n\nstruct usbdevfs_disconnectsignal32 {\n\tcompat_int_t signr;\n\tcompat_caddr_t context;\n};\n\nstruct usbdevfs_getdriver {\n\tunsigned int interface;\n\tchar driver[256];\n};\n\nstruct usbdevfs_hub_portinfo {\n\tchar nports;\n\tchar port[127];\n};\n\nstruct usbdevfs_ioctl {\n\tint ifno;\n\tint ioctl_code;\n\tvoid *data;\n};\n\nstruct usbdevfs_ioctl32 {\n\ts32 ifno;\n\ts32 ioctl_code;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_iso_packet_desc {\n\tunsigned int length;\n\tunsigned int actual_length;\n\tunsigned int status;\n};\n\nstruct usbdevfs_setinterface {\n\tunsigned int interface;\n\tunsigned int altsetting;\n};\n\nstruct usbdevfs_streams {\n\tunsigned int num_streams;\n\tunsigned int num_eps;\n\tunsigned char eps[0];\n};\n\nstruct usbdevfs_urb {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tint status;\n\tunsigned int flags;\n\tvoid *buffer;\n\tint buffer_length;\n\tint actual_length;\n\tint start_frame;\n\tunion {\n\t\tint number_of_packets;\n\t\tunsigned int stream_id;\n\t};\n\tint error_count;\n\tunsigned int signr;\n\tvoid *usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbdevfs_urb32 {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tcompat_int_t status;\n\tcompat_uint_t flags;\n\tcompat_caddr_t buffer;\n\tcompat_int_t buffer_length;\n\tcompat_int_t actual_length;\n\tcompat_int_t start_frame;\n\tcompat_int_t number_of_packets;\n\tcompat_int_t error_count;\n\tcompat_uint_t signr;\n\tcompat_caddr_t usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbhid_device {\n\tstruct hid_device *hid;\n\tstruct usb_interface *intf;\n\tint ifnum;\n\tunsigned int bufsize;\n\tstruct urb *urbin;\n\tchar *inbuf;\n\tdma_addr_t inbuf_dma;\n\tstruct urb *urbctrl;\n\tstruct usb_ctrlrequest *cr;\n\tstruct hid_control_fifo ctrl[256];\n\tunsigned char ctrlhead;\n\tunsigned char ctrltail;\n\tchar *ctrlbuf;\n\tdma_addr_t ctrlbuf_dma;\n\tlong unsigned int last_ctrl;\n\tstruct urb *urbout;\n\tstruct hid_output_fifo out[256];\n\tunsigned char outhead;\n\tunsigned char outtail;\n\tchar *outbuf;\n\tdma_addr_t outbuf_dma;\n\tlong unsigned int last_out;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tlong unsigned int iofl;\n\tstruct timer_list io_retry;\n\tlong unsigned int stop_retry;\n\tunsigned int retry_delay;\n\tstruct work_struct reset_work;\n\twait_queue_head_t wait;\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct used_bucket {\n\tstruct list_head head;\n\tstruct hlist_head *bucket;\n};\n\nstruct used_entry {\n\tu32 id;\n\tu32 len;\n};\n\nstruct user_arg_ptr {\n\tbool is_compat;\n\tunion {\n\t\tconst char * const *native;\n\t\tconst compat_uptr_t *compat;\n\t} ptr;\n};\n\nstruct user_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap roles;\n\tstruct mls_range range;\n\tstruct mls_level dfltlevel;\n};\n\nstruct user_element {\n\tstruct snd_ctl_elem_info info;\n\tstruct snd_card *card;\n\tchar *elem_data;\n\tlong unsigned int elem_data_size;\n\tvoid *tlv_data;\n\tlong unsigned int tlv_data_size;\n\tvoid *priv_data;\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[10];\n\tlong int rlimit_max[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n};\n\nstruct user_threshold {\n\tstruct list_head list_node;\n\tint temperature;\n\tint direction;\n};\n\nstruct userspace_policy {\n\tunsigned int is_managed;\n\tunsigned int setspeed;\n\tstruct mutex mutex;\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tlong unsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct ustring_buffer {\n\tchar buffer[1024];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct v9fs_context {\n\tstruct p9_client_opts client_opts;\n\tstruct p9_fd_opts fd_opts;\n\tstruct p9_rdma_opts rdma_opts;\n\tstruct p9_session_opts session_opts;\n};\n\nstruct v9fs_inode {\n\tstruct netfs_inode netfs;\n\tstruct p9_qid qid;\n\tunsigned int cache_validity;\n\tstruct mutex v_mutex;\n};\n\nstruct v9fs_session_info {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tunsigned int maxdata;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tstruct p9_client *clnt;\n\tstruct list_head slist;\n\tstruct rw_semaphore rename_sem;\n\tlong int session_lock_timeout;\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct val_table_ent {\n\tconst char *str;\n\tint value;\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[4];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vdso_arch_data {\n\t__u64 all_cpu_hwprobe_values[17];\n\t__u8 homogeneous_cpus;\n\t__u8 ready;\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_rng_data {\n\tu64 generation;\n\tu8 is_ready;\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tbool is_firmware_default;\n\tunsigned int (*set_decode)(struct pci_dev *, bool);\n};\n\nstruct videomode {\n\tlong unsigned int pixelclock;\n\tu32 hactive;\n\tu32 hfront_porch;\n\tu32 hback_porch;\n\tu32 hsync_len;\n\tu32 vactive;\n\tu32 vfront_porch;\n\tu32 vback_porch;\n\tu32 vsync_len;\n\tenum display_flags flags;\n};\n\nstruct virtio_blk_outhdr {\n\t__virtio32 type;\n\t__virtio32 ioprio;\n\t__virtio64 sector;\n};\n\nstruct virtblk_req {\n\tstruct virtio_blk_outhdr out_hdr;\n\tunion {\n\t\tu8 status;\n\t\tstruct {\n\t\t\t__virtio64 sector;\n\t\t\tu8 status;\n\t\t} zone_append;\n\t} in_hdr;\n\tsize_t in_hdr_len;\n\tstruct sg_table sg_table;\n\tstruct scatterlist sg[0];\n};\n\nstruct virtio_9p_config {\n\t__virtio16 tag_len;\n\t__u8 tag[0];\n};\n\nstruct virtio_admin_cmd {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__le64 group_member_id;\n\tstruct scatterlist *data_sg;\n\tstruct scatterlist *result_sg;\n\tstruct completion completion;\n\tu32 result_sg_size;\n\tint ret;\n};\n\nstruct virtio_admin_cmd_cap_get_data {\n\t__le16 id;\n\t__u8 reserved[6];\n};\n\nstruct virtio_admin_cmd_cap_set_data {\n\t__le16 id;\n\t__u8 reserved[6];\n\t__u8 cap_specific_data[0];\n};\n\nstruct virtio_admin_cmd_dev_mode_set_data {\n\t__u8 flags;\n};\n\nstruct virtio_admin_cmd_resource_obj_cmd_hdr {\n\t__le16 type;\n\t__u8 reserved[2];\n\t__le32 id;\n};\n\nstruct virtio_dev_part_hdr {\n\t__le16 part_type;\n\t__u8 flags;\n\t__u8 reserved;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 offset;\n\t\t\t__le32 reserved;\n\t\t} pci_common_cfg;\n\t\tstruct {\n\t\t\t__le16 index;\n\t\t\t__u8 reserved[6];\n\t\t} vq_index;\n\t} selector;\n\t__le32 length;\n};\n\nstruct virtio_admin_cmd_dev_parts_get_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n\tstruct virtio_dev_part_hdr hdr_list[0];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_result {\n\tunion {\n\t\tstruct {\n\t\t\t__le32 size;\n\t\t\t__le32 reserved;\n\t\t} parts_size;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t} hdr_list_count;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t\tstruct virtio_dev_part_hdr hdrs[0];\n\t\t} hdr_list;\n\t};\n};\n\nstruct virtio_admin_cmd_hdr {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__u8 reserved1[12];\n\t__le64 group_member_id;\n};\n\nstruct virtio_admin_cmd_query_cap_id_result {\n\t__le64 supported_caps[1];\n};\n\nstruct virtio_admin_cmd_resource_obj_create_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__le64 flags;\n\t__u8 resource_obj_specific_data[0];\n};\n\nstruct virtio_admin_cmd_status {\n\t__le16 status;\n\t__le16 status_qualifier;\n\t__u8 reserved2[4];\n};\n\nstruct virtio_balloon_stat {\n\t__virtio16 tag;\n\t__virtio64 val;\n} __attribute__((packed));\n\nstruct virtio_balloon {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *inflate_vq;\n\tstruct virtqueue *deflate_vq;\n\tstruct virtqueue *stats_vq;\n\tstruct virtqueue *free_page_vq;\n\tstruct workqueue_struct *balloon_wq;\n\tstruct work_struct report_free_page_work;\n\tstruct work_struct update_balloon_stats_work;\n\tstruct work_struct update_balloon_size_work;\n\tspinlock_t stop_update_lock;\n\tbool stop_update;\n\tlong unsigned int config_read_bitmap;\n\tstruct list_head free_page_list;\n\tspinlock_t free_page_list_lock;\n\tlong unsigned int num_free_page_blocks;\n\tu32 cmd_id_received_cache;\n\t__virtio32 cmd_id_active;\n\t__virtio32 cmd_id_stop;\n\twait_queue_head_t acked;\n\tunsigned int num_pages;\n\tstruct balloon_dev_info vb_dev_info;\n\tstruct mutex balloon_lock;\n\tunsigned int num_pfns;\n\t__virtio32 pfns[256];\n\tstruct virtio_balloon_stat stats[16];\n\tstruct shrinker *shrinker;\n\tstruct notifier_block oom_nb;\n\tstruct virtqueue *reporting_vq;\n\tstruct page_reporting_dev_info pr_dev_info;\n\tspinlock_t wakeup_lock;\n\tbool processing_wakeup_event;\n\tu32 wakeup_signal_mask;\n};\n\nstruct virtio_balloon_config {\n\t__le32 num_pages;\n\t__le32 actual;\n\tunion {\n\t\t__le32 free_page_hint_cmd_id;\n\t\t__le32 free_page_report_cmd_id;\n\t};\n\t__le32 poison_val;\n};\n\nstruct virtio_blk_vq;\n\nstruct virtio_blk {\n\tstruct mutex vdev_mutex;\n\tstruct virtio_device *vdev;\n\tstruct gendisk *disk;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct work_struct config_work;\n\tint index;\n\tint num_vqs;\n\tint io_queues[3];\n\tstruct virtio_blk_vq *vqs;\n\tunsigned int zone_sectors;\n};\n\nstruct virtio_blk_geometry {\n\t__virtio16 cylinders;\n\t__u8 heads;\n\t__u8 sectors;\n};\n\nstruct virtio_blk_zoned_characteristics {\n\t__virtio32 zone_sectors;\n\t__virtio32 max_open_zones;\n\t__virtio32 max_active_zones;\n\t__virtio32 max_append_sectors;\n\t__virtio32 write_granularity;\n\t__u8 model;\n\t__u8 unused2[3];\n};\n\nstruct virtio_blk_config {\n\t__virtio64 capacity;\n\t__virtio32 size_max;\n\t__virtio32 seg_max;\n\tstruct virtio_blk_geometry geometry;\n\t__virtio32 blk_size;\n\t__u8 physical_block_exp;\n\t__u8 alignment_offset;\n\t__virtio16 min_io_size;\n\t__virtio32 opt_io_size;\n\t__u8 wce;\n\t__u8 unused;\n\t__virtio16 num_queues;\n\t__virtio32 max_discard_sectors;\n\t__virtio32 max_discard_seg;\n\t__virtio32 discard_sector_alignment;\n\t__virtio32 max_write_zeroes_sectors;\n\t__virtio32 max_write_zeroes_seg;\n\t__u8 write_zeroes_may_unmap;\n\t__u8 unused1[3];\n\t__virtio32 max_secure_erase_sectors;\n\t__virtio32 max_secure_erase_seg;\n\t__virtio32 secure_erase_sector_alignment;\n\tstruct virtio_blk_zoned_characteristics zoned;\n};\n\nstruct virtio_blk_discard_write_zeroes {\n\t__le64 sector;\n\t__le32 num_sectors;\n\t__le32 flags;\n};\n\nstruct virtio_blk_vq {\n\tstruct virtqueue *vq;\n\tspinlock_t lock;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct virtio_chan {\n\tbool inuse;\n\tspinlock_t lock;\n\tstruct p9_client *client;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *vq;\n\tint ring_bufs_avail;\n\twait_queue_head_t *vc_wq;\n\tlong unsigned int p9_max_pages;\n\tstruct scatterlist sg[128];\n\tchar *tag;\n\tstruct list_head chan_list;\n};\n\nstruct virtqueue_info;\n\nstruct virtio_shm_region;\n\nstruct virtio_config_ops {\n\tvoid (*get)(struct virtio_device *, unsigned int, void *, unsigned int);\n\tvoid (*set)(struct virtio_device *, unsigned int, const void *, unsigned int);\n\tu32 (*generation)(struct virtio_device *);\n\tu8 (*get_status)(struct virtio_device *);\n\tvoid (*set_status)(struct virtio_device *, u8);\n\tvoid (*reset)(struct virtio_device *);\n\tint (*find_vqs)(struct virtio_device *, unsigned int, struct virtqueue **, struct virtqueue_info *, struct irq_affinity *);\n\tvoid (*del_vqs)(struct virtio_device *);\n\tvoid (*synchronize_cbs)(struct virtio_device *);\n\tu64 (*get_features)(struct virtio_device *);\n\tvoid (*get_extended_features)(struct virtio_device *, u64 *);\n\tint (*finalize_features)(struct virtio_device *);\n\tconst char * (*bus_name)(struct virtio_device *);\n\tint (*set_vq_affinity)(struct virtqueue *, const struct cpumask *);\n\tconst struct cpumask * (*get_vq_affinity)(struct virtio_device *, int);\n\tbool (*get_shm_region)(struct virtio_device *, struct virtio_shm_region *, u8);\n\tint (*disable_vq_and_reset)(struct virtqueue *);\n\tint (*enable_vq_after_reset)(struct virtqueue *);\n};\n\nstruct virtio_console_config {\n\t__virtio16 cols;\n\t__virtio16 rows;\n\t__virtio32 max_nr_ports;\n\t__virtio32 emerg_wr;\n};\n\nstruct virtio_dev_parts_cap {\n\t__u8 get_parts_resource_objects_limit;\n\t__u8 set_parts_resource_objects_limit;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct vringh_config_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_map_ops;\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_driver {\n\tstruct device_driver driver;\n\tconst struct virtio_device_id *id_table;\n\tconst unsigned int *feature_table;\n\tunsigned int feature_table_size;\n\tconst unsigned int *feature_table_legacy;\n\tunsigned int feature_table_size_legacy;\n\tint (*validate)(struct virtio_device *);\n\tint (*probe)(struct virtio_device *);\n\tvoid (*scan)(struct virtio_device *);\n\tvoid (*remove)(struct virtio_device *);\n\tvoid (*config_changed)(struct virtio_device *);\n\tint (*freeze)(struct virtio_device *);\n\tint (*restore)(struct virtio_device *);\n\tint (*reset_prepare)(struct virtio_device *);\n\tint (*reset_done)(struct virtio_device *);\n\tvoid (*shutdown)(struct virtio_device *);\n};\n\nstruct virtio_input_event {\n\t__le16 type;\n\t__le16 code;\n\t__le32 value;\n};\n\nstruct virtio_input {\n\tstruct virtio_device *vdev;\n\tstruct input_dev *idev;\n\tchar name[64];\n\tchar serial[64];\n\tchar phys[64];\n\tstruct virtqueue *evt;\n\tstruct virtqueue *sts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_input_event evts[64];\n\t__u8 __cacheline_group_end__[0];\n\tspinlock_t lock;\n\tbool ready;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct virtio_input_absinfo {\n\t__le32 min;\n\t__le32 max;\n\t__le32 fuzz;\n\t__le32 flat;\n\t__le32 res;\n};\n\nstruct virtio_input_devids {\n\t__le16 bustype;\n\t__le16 vendor;\n\t__le16 product;\n\t__le16 version;\n};\n\nstruct virtio_input_config {\n\t__u8 select;\n\t__u8 subsel;\n\t__u8 size;\n\t__u8 reserved[5];\n\tunion {\n\t\tchar string[128];\n\t\t__u8 bitmap[128];\n\t\tstruct virtio_input_absinfo abs;\n\t\tstruct virtio_input_devids ids;\n\t} u;\n};\n\nstruct virtio_map_ops {\n\tdma_addr_t (*map_page)(union virtio_map, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid * (*alloc)(union virtio_map, size_t, dma_addr_t *, gfp_t);\n\tvoid (*free)(union virtio_map, size_t, void *, dma_addr_t, long unsigned int);\n\tbool (*need_sync)(union virtio_map, dma_addr_t);\n\tint (*mapping_error)(union virtio_map, dma_addr_t);\n\tsize_t (*max_mapping_size)(union virtio_map);\n};\n\nstruct virtio_mmio_device {\n\tstruct virtio_device vdev;\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tlong unsigned int version;\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1 {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\tunion {\n\t\tstruct {\n\t\t\t__virtio16 csum_start;\n\t\t\t__virtio16 csum_offset;\n\t\t};\n\t\tstruct {\n\t\t\t__virtio16 start;\n\t\t\t__virtio16 offset;\n\t\t} csum;\n\t\tstruct {\n\t\t\t__le16 segments;\n\t\t\t__le16 dup_acks;\n\t\t} rsc;\n\t};\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1_hash {\n\tstruct virtio_net_hdr_v1 hdr;\n\t__le16 hash_value_lo;\n\t__le16 hash_value_hi;\n\t__le16 hash_report;\n\t__le16 padding;\n};\n\nstruct virtio_net_hdr_v1_hash_tunnel {\n\tstruct virtio_net_hdr_v1_hash hash_hdr;\n\t__le16 outer_th_offset;\n\t__le16 inner_nh_offset;\n};\n\nstruct virtio_net_common_hdr {\n\tunion {\n\t\tstruct virtio_net_hdr hdr;\n\t\tstruct virtio_net_hdr_mrg_rxbuf mrg_hdr;\n\t\tstruct virtio_net_hdr_v1_hash hash_v1_hdr;\n\t\tstruct virtio_net_hdr_v1_hash_tunnel tnl_hdr;\n\t};\n};\n\nstruct virtio_net_config {\n\t__u8 mac[6];\n\t__virtio16 status;\n\t__virtio16 max_virtqueue_pairs;\n\t__virtio16 mtu;\n\t__le32 speed;\n\t__u8 duplex;\n\t__u8 rss_max_key_size;\n\t__le16 rss_max_indirection_table_length;\n\t__le32 supported_hash_types;\n};\n\nstruct virtio_net_ctrl_coal {\n\t__le32 max_packets;\n\t__le32 max_usecs;\n};\n\nstruct virtio_net_ctrl_coal_rx {\n\t__le32 rx_max_packets;\n\t__le32 rx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_tx {\n\t__le32 tx_max_packets;\n\t__le32 tx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_vq {\n\t__le16 vqn;\n\t__le16 reserved;\n\tstruct virtio_net_ctrl_coal coal;\n};\n\nstruct virtio_net_ctrl_mac {\n\t__virtio32 entries;\n\t__u8 macs[0];\n};\n\nstruct virtio_net_ctrl_mq {\n\t__virtio16 virtqueue_pairs;\n};\n\nstruct virtio_net_ctrl_queue_stats {\n\tstruct {\n\t\t__le16 vq_index;\n\t\t__le16 reserved[3];\n\t\t__le64 types_bitmap[1];\n\t} stats[1];\n};\n\nstruct virtio_net_rss_config_hdr {\n\t__le32 hash_types;\n\t__le16 indirection_table_mask;\n\t__le16 unclassified_queue;\n\t__le16 indirection_table[0];\n};\n\nstruct virtio_net_rss_config_trailer {\n\t__le16 max_tx_vq;\n\t__u8 hash_key_length;\n\t__u8 hash_key_data[0];\n};\n\nstruct virtio_net_stats_capabilities {\n\t__le64 supported_stats_types[1];\n};\n\nstruct virtio_net_stats_reply_hdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__le16 vq_index;\n\t__le16 reserved1;\n\t__le16 size;\n};\n\nstruct virtio_pci_vq_info;\n\nstruct virtio_pci_admin_vq {\n\tstruct virtio_pci_vq_info *info;\n\tspinlock_t lock;\n\tu64 supported_cmds;\n\tu64 supported_caps;\n\tu8 max_dev_parts_objects;\n\tstruct ida dev_parts_ida;\n\tchar name[10];\n\tu16 vq_index;\n};\n\nstruct virtio_pci_common_cfg {\n\t__le32 device_feature_select;\n\t__le32 device_feature;\n\t__le32 guest_feature_select;\n\t__le32 guest_feature;\n\t__le16 msix_config;\n\t__le16 num_queues;\n\t__u8 device_status;\n\t__u8 config_generation;\n\t__le16 queue_select;\n\t__le16 queue_size;\n\t__le16 queue_msix_vector;\n\t__le16 queue_enable;\n\t__le16 queue_notify_off;\n\t__le32 queue_desc_lo;\n\t__le32 queue_desc_hi;\n\t__le32 queue_avail_lo;\n\t__le32 queue_avail_hi;\n\t__le32 queue_used_lo;\n\t__le32 queue_used_hi;\n};\n\nstruct virtio_pci_legacy_device {\n\tstruct pci_dev *pci_dev;\n\tu8 *isr;\n\tvoid *ioaddr;\n\tstruct virtio_device_id id;\n};\n\nstruct virtio_pci_modern_device {\n\tstruct pci_dev *pci_dev;\n\tstruct virtio_pci_common_cfg *common;\n\tvoid *device;\n\tvoid *notify_base;\n\tresource_size_t notify_pa;\n\tu8 *isr;\n\tsize_t notify_len;\n\tsize_t device_len;\n\tsize_t common_len;\n\tint notify_map_cap;\n\tu32 notify_offset_multiplier;\n\tint modern_bars;\n\tstruct virtio_device_id id;\n\tint (*device_id_check)(struct pci_dev *);\n\tu64 dma_mask;\n};\n\nstruct virtio_pci_device {\n\tstruct virtio_device vdev;\n\tstruct pci_dev *pci_dev;\n\tunion {\n\t\tstruct virtio_pci_legacy_device ldev;\n\t\tstruct virtio_pci_modern_device mdev;\n\t};\n\tbool is_legacy;\n\tu8 *isr;\n\tspinlock_t lock;\n\tstruct list_head virtqueues;\n\tstruct list_head slow_virtqueues;\n\tstruct virtio_pci_vq_info **vqs;\n\tstruct virtio_pci_admin_vq admin_vq;\n\tint msix_enabled;\n\tint intx_enabled;\n\tcpumask_var_t *msix_affinity_masks;\n\tchar (*msix_names)[256];\n\tunsigned int msix_vectors;\n\tunsigned int msix_used_vectors;\n\tbool per_vq_vectors;\n\tstruct virtqueue * (*setup_vq)(struct virtio_pci_device *, struct virtio_pci_vq_info *, unsigned int, void (*)(struct virtqueue *), const char *, bool, u16);\n\tvoid (*del_vq)(struct virtio_pci_vq_info *);\n\tu16 (*config_vector)(struct virtio_pci_device *, u16);\n\tint (*avq_index)(struct virtio_device *, u16 *, u16 *);\n};\n\nstruct virtio_pci_modern_common_cfg {\n\tstruct virtio_pci_common_cfg cfg;\n\t__le16 queue_notify_data;\n\t__le16 queue_reset;\n\t__le16 admin_queue_index;\n\t__le16 admin_queue_num;\n};\n\nstruct virtio_pci_vq_info {\n\tstruct virtqueue *vq;\n\tstruct list_head node;\n\tunsigned int msix_vector;\n};\n\nstruct virtio_resource_obj_dev_parts {\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtproc_info;\n\nstruct virtio_rpmsg_channel {\n\tstruct rpmsg_device rpdev;\n\tstruct virtproc_info *vrp;\n};\n\nstruct virtio_scsi;\n\nstruct virtio_scsi_event;\n\nstruct virtio_scsi_event_node {\n\tstruct virtio_scsi *vscsi;\n\tstruct virtio_scsi_event *event;\n\tstruct work_struct work;\n};\n\nstruct virtio_scsi_vq {\n\tspinlock_t vq_lock;\n\tstruct virtqueue *vq;\n};\n\nstruct virtio_scsi_event {\n\t__virtio32 event;\n\t__u8 lun[8];\n\t__virtio32 reason;\n};\n\nstruct virtio_scsi {\n\tstruct virtio_device *vdev;\n\tstruct virtio_scsi_event_node event_list[8];\n\tu32 num_queues;\n\tint io_queues[3];\n\tstruct hlist_node node;\n\tbool stop_events;\n\tstruct virtio_scsi_vq ctrl_vq;\n\tstruct virtio_scsi_vq event_vq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_scsi_event events[8];\n\t__u8 __cacheline_group_end__[0];\n\tstruct virtio_scsi_vq req_vqs[0];\n};\n\nstruct virtio_scsi_cmd_req {\n\t__u8 lun[8];\n\t__virtio64 tag;\n\t__u8 task_attr;\n\t__u8 prio;\n\t__u8 crn;\n\t__u8 cdb[32];\n} __attribute__((packed));\n\nstruct virtio_scsi_cmd_req_pi {\n\t__u8 lun[8];\n\t__virtio64 tag;\n\t__u8 task_attr;\n\t__u8 prio;\n\t__u8 crn;\n\t__virtio32 pi_bytesout;\n\t__virtio32 pi_bytesin;\n\t__u8 cdb[32];\n} __attribute__((packed));\n\nstruct virtio_scsi_ctrl_tmf_req {\n\t__virtio32 type;\n\t__virtio32 subtype;\n\t__u8 lun[8];\n\t__virtio64 tag;\n};\n\nstruct virtio_scsi_ctrl_an_req {\n\t__virtio32 type;\n\t__u8 lun[8];\n\t__virtio32 event_requested;\n};\n\nstruct virtio_scsi_cmd_resp {\n\t__virtio32 sense_len;\n\t__virtio32 resid;\n\t__virtio16 status_qualifier;\n\t__u8 status;\n\t__u8 response;\n\t__u8 sense[96];\n};\n\nstruct virtio_scsi_ctrl_tmf_resp {\n\t__u8 response;\n};\n\nstruct virtio_scsi_ctrl_an_resp {\n\t__virtio32 event_actual;\n\t__u8 response;\n} __attribute__((packed));\n\nstruct virtio_scsi_cmd {\n\tstruct scsi_cmnd *sc;\n\tstruct completion *comp;\n\tunion {\n\t\tstruct virtio_scsi_cmd_req cmd;\n\t\tstruct virtio_scsi_cmd_req_pi cmd_pi;\n\t\tstruct virtio_scsi_ctrl_tmf_req tmf;\n\t\tstruct virtio_scsi_ctrl_an_req an;\n\t} req;\n\tunion {\n\t\tstruct virtio_scsi_cmd_resp cmd;\n\t\tstruct virtio_scsi_ctrl_tmf_resp tmf;\n\t\tstruct virtio_scsi_ctrl_an_resp an;\n\t\tstruct virtio_scsi_event evt;\n\t} resp;\n\tlong: 64;\n} __attribute__((packed));\n\nstruct virtio_scsi_config {\n\t__virtio32 num_queues;\n\t__virtio32 seg_max;\n\t__virtio32 max_sectors;\n\t__virtio32 cmd_per_lun;\n\t__virtio32 event_info_size;\n\t__virtio32 sense_size;\n\t__virtio32 cdb_size;\n\t__virtio16 max_channel;\n\t__virtio16 max_target;\n\t__virtio32 max_lun;\n};\n\nstruct virtio_shm_region {\n\tu64 addr;\n\tu64 len;\n};\n\nstruct virtnet_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *cvq;\n\tstruct net_device *dev;\n\tstruct send_queue *sq;\n\tstruct receive_queue *rq;\n\tunsigned int status;\n\tu16 max_queue_pairs;\n\tu16 curr_queue_pairs;\n\tu16 xdp_queue_pairs;\n\tbool xdp_enabled;\n\tbool big_packets;\n\tunsigned int big_packets_num_skbfrags;\n\tbool mergeable_rx_bufs;\n\tbool has_rss;\n\tbool has_rss_hash_report;\n\tu8 rss_key_size;\n\tu16 rss_indir_table_size;\n\tu32 rss_hash_types_supported;\n\tu32 rss_hash_types_saved;\n\tbool has_cvq;\n\tstruct mutex cvq_lock;\n\tbool any_header_sg;\n\tu8 hdr_len;\n\tbool tx_tnl;\n\tbool rx_tnl;\n\tbool rx_tnl_csum;\n\tstruct work_struct config_work;\n\tstruct work_struct rx_mode_work;\n\tbool rx_mode_work_enabled;\n\tbool affinity_hint_set;\n\tstruct hlist_node node;\n\tstruct hlist_node node_dead;\n\tstruct control_buf *ctrl;\n\tu8 duplex;\n\tu32 speed;\n\tbool rx_dim_enabled;\n\tstruct virtnet_interrupt_coalesce intr_coal_tx;\n\tstruct virtnet_interrupt_coalesce intr_coal_rx;\n\tlong unsigned int guest_offloads;\n\tlong unsigned int guest_offloads_capable;\n\tstruct failover *failover;\n\tu64 device_stats_cap;\n\tstruct virtio_net_rss_config_hdr *rss_hdr;\n\tunion {\n\t\tstruct virtio_net_rss_config_trailer rss_trailer;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[3];\n\t\t\tu8 rss_hash_key_data[40];\n\t\t};\n\t};\n};\n\nstruct virtnet_rq_dma {\n\tdma_addr_t addr;\n\tu32 ref;\n\tu16 len;\n\tu16 need_sync;\n};\n\nstruct virtnet_sq_free_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 napi_packets;\n\tu64 napi_bytes;\n\tu64 xsk;\n};\n\nstruct virtnet_stat_desc {\n\tchar desc[32];\n\tsize_t offset;\n\tsize_t qstat_offset;\n};\n\nstruct virtnet_stats_ctx {\n\tbool to_qstat;\n\tu32 desc_num[3];\n\tu64 bitmap[3];\n\tu32 size[3];\n\tu64 *data;\n};\n\nstruct virtproc_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *rvq;\n\tstruct virtqueue *svq;\n\tvoid *rbufs;\n\tvoid *sbufs;\n\tunsigned int num_bufs;\n\tunsigned int buf_size;\n\tint last_sbuf;\n\tdma_addr_t bufs_dma;\n\tstruct mutex tx_lock;\n\tstruct idr endpoints;\n\tstruct mutex endpoints_lock;\n\twait_queue_head_t sendq;\n};\n\nstruct virtqueue {\n\tstruct list_head list;\n\tvoid (*callback)(struct virtqueue *);\n\tconst char *name;\n\tstruct virtio_device *vdev;\n\tunsigned int index;\n\tunsigned int num_free;\n\tunsigned int num_max;\n\tbool reset;\n\tvoid *priv;\n};\n\ntypedef void vq_callback_t(struct virtqueue *);\n\nstruct virtqueue_info {\n\tconst char *name;\n\tvq_callback_t *callback;\n\tbool ctx;\n};\n\nstruct vring_virtqueue;\n\nstruct virtqueue_ops {\n\tint (*add)(struct vring_virtqueue *, struct scatterlist **, unsigned int, unsigned int, unsigned int, void *, void *, bool, gfp_t, long unsigned int);\n\tvoid * (*get)(struct vring_virtqueue *, unsigned int *, void **);\n\tbool (*kick_prepare)(struct vring_virtqueue *);\n\tvoid (*disable_cb)(struct vring_virtqueue *);\n\tbool (*enable_cb_delayed)(struct vring_virtqueue *);\n\tunsigned int (*enable_cb_prepare)(struct vring_virtqueue *);\n\tbool (*poll)(const struct vring_virtqueue *, unsigned int);\n\tvoid * (*detach_unused_buf)(struct vring_virtqueue *);\n\tbool (*more_used)(const struct vring_virtqueue *);\n\tint (*resize)(struct vring_virtqueue *, u32);\n\tvoid (*reset)(struct vring_virtqueue *);\n};\n\nstruct virtrng_info {\n\tstruct hwrng hwrng;\n\tstruct virtqueue *vq;\n\tchar name[25];\n\tint index;\n\tbool hwrng_register_done;\n\tbool hwrng_removed;\n\tstruct completion have_data;\n\tunsigned int data_avail;\n\tunsigned int data_idx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__[0];\n\tu8 data[64];\n\t__u8 __cacheline_group_end__[0];\n};\n\nstruct vlan_priority_tci_mapping;\n\nstruct vlan_pcpu_stats;\n\nstruct vlan_dev_priv {\n\tunsigned int nr_ingress_mappings;\n\tu32 ingress_priority_map[8];\n\tunsigned int nr_egress_mappings;\n\tstruct vlan_priority_tci_mapping *egress_priority_map[16];\n\t__be16 vlan_proto;\n\tu16 vlan_id;\n\tu16 flags;\n\tstruct net_device *real_dev;\n\tnetdevice_tracker dev_tracker;\n\tunsigned char real_dev_addr[6];\n\tstruct proc_dir_entry *dent;\n\tstruct vlan_pcpu_stats *vlan_pcpu_stats;\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_group {\n\tunsigned int nr_vlan_devs;\n\tstruct hlist_node hlist;\n\tstruct net_device **vlan_devices_arrays[16];\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_info {\n\tstruct net_device *real_dev;\n\tstruct vlan_group grp;\n\tstruct list_head vid_list;\n\tunsigned int nr_vids;\n\tbool auto_vid0;\n\tstruct callback_head rcu;\n};\n\nstruct vlan_pcpu_stats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_multicast;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n\tu32 rx_errors;\n\tu32 tx_dropped;\n};\n\nstruct vlan_priority_tci_mapping {\n\tu32 priority;\n\tu16 vlan_qos;\n\tstruct vlan_priority_tci_mapping *next;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vlan_vid_info {\n\tstruct list_head list;\n\t__be16 proto;\n\tu16 vid;\n\tint refcount;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {};\n\nstruct vma_numab_state;\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tunsigned int vm_lock_seq;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct mempolicy *vm_policy;\n\tstruct vma_numab_state *numab_state;\n\trefcount_t vm_refcnt;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[82];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n\tint (*set_policy)(struct vm_area_struct *, struct mempolicy *);\n\tstruct mempolicy * (*get_policy)(struct vm_area_struct *, long unsigned int, long unsigned int *);\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct vm_stack {\n\tstruct callback_head rcu;\n\tstruct vm_struct *stack_vm_area;\n};\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int page_order;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_exclude_readers_state {\n\tstruct vm_area_struct *vma;\n\tint state;\n\tbool detaching;\n\tbool detached;\n\tbool exclusive;\n};\n\nstruct vma_list {\n\tstruct vm_area_struct *vma;\n\tstruct list_head head;\n\trefcount_t mmap_count;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_numab_state {\n\tlong unsigned int next_scan;\n\tlong unsigned int pids_active_reset;\n\tlong unsigned int pids_active[2];\n\tint start_scan_seq;\n\tint prev_scan_seq;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[16];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmemmap_remap_walk {\n\tvoid (*remap_pte)(pte_t *, long unsigned int, struct vmemmap_remap_walk *);\n\tlong unsigned int nr_walked;\n\tstruct page *reuse_page;\n\tlong unsigned int reuse_addr;\n\tstruct list_head *vmemmap_pages;\n\tlong unsigned int flags;\n};\n\nstruct vmpressure_event {\n\tstruct eventfd_ctx *efd;\n\tenum vmpressure_levels level;\n\tenum vmpressure_modes mode;\n\tstruct list_head node;\n};\n\nstruct vring_desc;\n\ntypedef struct vring_desc vring_desc_t;\n\nstruct vring_avail;\n\ntypedef struct vring_avail vring_avail_t;\n\nstruct vring_used;\n\ntypedef struct vring_used vring_used_t;\n\nstruct vring {\n\tunsigned int num;\n\tvring_desc_t *desc;\n\tvring_avail_t *avail;\n\tvring_used_t *used;\n};\n\nstruct vring_avail {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\t__virtio16 ring[0];\n};\n\nstruct vring_desc {\n\t__virtio64 addr;\n\t__virtio32 len;\n\t__virtio16 flags;\n\t__virtio16 next;\n};\n\nstruct vring_desc_extra {\n\tdma_addr_t addr;\n\tu32 len;\n\tu16 flags;\n\tu16 next;\n};\n\nstruct vring_packed_desc;\n\nstruct vring_desc_state_packed {\n\tvoid *data;\n\tstruct vring_packed_desc *indir_desc;\n\tu16 num;\n\tu16 last;\n\tu32 total_in_len;\n};\n\nstruct vring_desc_state_split {\n\tvoid *data;\n\tstruct vring_desc *indir_desc;\n\tu32 total_in_len;\n};\n\nstruct vring_packed_desc {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 id;\n\t__le16 flags;\n};\n\nstruct vring_packed_desc_event {\n\t__le16 off_wrap;\n\t__le16 flags;\n};\n\nstruct vring_used_elem {\n\t__virtio32 id;\n\t__virtio32 len;\n};\n\ntypedef struct vring_used_elem vring_used_elem_t;\n\nstruct vring_used {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\tvring_used_elem_t ring[0];\n};\n\nstruct vring_virtqueue_split {\n\tstruct vring vring;\n\tu16 avail_flags_shadow;\n\tu16 avail_idx_shadow;\n\tstruct vring_desc_state_split *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t queue_dma_addr;\n\tsize_t queue_size_in_bytes;\n\tu32 vring_align;\n\tbool may_reduce_num;\n};\n\nstruct vring_virtqueue_packed {\n\tstruct {\n\t\tunsigned int num;\n\t\tstruct vring_packed_desc *desc;\n\t\tstruct vring_packed_desc_event *driver;\n\t\tstruct vring_packed_desc_event *device;\n\t} vring;\n\tbool avail_wrap_counter;\n\tu16 avail_used_flags;\n\tu16 next_avail_idx;\n\tu16 event_flags_shadow;\n\tstruct vring_desc_state_packed *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t ring_dma_addr;\n\tdma_addr_t driver_event_dma_addr;\n\tdma_addr_t device_event_dma_addr;\n\tsize_t ring_size_in_bytes;\n\tsize_t event_size_in_bytes;\n};\n\nstruct vring_virtqueue {\n\tstruct virtqueue vq;\n\tbool use_map_api;\n\tbool weak_barriers;\n\tbool broken;\n\tbool indirect;\n\tbool event;\n\tenum vq_layout layout;\n\tunsigned int free_head;\n\tstruct used_entry batch_last;\n\tunsigned int num_added;\n\tu16 last_used_idx;\n\tu16 last_used;\n\tbool event_triggered;\n\tunion {\n\t\tstruct vring_virtqueue_split split;\n\t\tstruct vring_virtqueue_packed packed;\n\t};\n\tbool (*notify)(struct virtqueue *);\n\tbool we_own_ring;\n\tunion virtio_map map;\n};\n\nstruct vsc8531_edge_rate_table {\n\tu32 vddmac;\n\tu32 slowdown[8];\n};\n\nstruct vsc85xx_ptp;\n\nstruct vsc85xx_hw_stat;\n\nstruct vsc8531_private {\n\tint rate_magic;\n\tu16 supp_led_modes;\n\tu32 leds_mode[4];\n\tu8 nleds;\n\tconst struct vsc85xx_hw_stat *hw_stats;\n\tu64 *stats;\n\tint nstats;\n\tu8 addr;\n\tunsigned int base_addr;\n\tstruct mii_timestamper mii_ts;\n\tbool input_clk_init;\n\tstruct vsc85xx_ptp *ptp;\n\tstruct gpio_desc *load_save;\n\tunsigned int ts_base_addr;\n\tu8 ts_base_phy;\n\tstruct mutex ts_lock;\n\tstruct mutex phc_lock;\n\tstruct sk_buff_head rx_skbs_list;\n};\n\nstruct vsc85xx_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu16 page;\n\tu16 mask;\n};\n\nstruct vsc85xx_probe_config {\n\tconst struct vsc85xx_hw_stat *hw_stats;\n\tsize_t shared_size;\n\tsize_t nstats;\n\tu16 supp_led_modes;\n\tu8 nleds;\n\tbool check_rate_magic;\n\tbool use_package;\n\tbool has_ptp;\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n};\n\nstruct walk_rcec_data {\n\tstruct pci_dev *rcec;\n\tint (*user_callback)(struct pci_dev *, void *);\n\tvoid *user_data;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct watchdog_core_data {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct watchdog_device *wdd;\n\tstruct mutex lock;\n\tktime_t last_keepalive;\n\tktime_t last_hw_keepalive;\n\tktime_t open_deadline;\n\tstruct hrtimer timer;\n\tstruct kthread_work work;\n\tlong unsigned int status;\n};\n\nstruct watchdog_governor {\n\tconst char name[20];\n\tvoid (*pretimeout)(struct watchdog_device *);\n};\n\nstruct watchdog_info {\n\t__u32 options;\n\t__u32 firmware_version;\n\t__u8 identity[32];\n};\n\nstruct watchdog_ops {\n\tstruct module *owner;\n\tint (*start)(struct watchdog_device *);\n\tint (*stop)(struct watchdog_device *);\n\tint (*ping)(struct watchdog_device *);\n\tunsigned int (*status)(struct watchdog_device *);\n\tint (*set_timeout)(struct watchdog_device *, unsigned int);\n\tint (*set_pretimeout)(struct watchdog_device *, unsigned int);\n\tunsigned int (*get_timeleft)(struct watchdog_device *);\n\tint (*restart)(struct watchdog_device *, long unsigned int, void *);\n\tlong int (*ioctl)(struct watchdog_device *, unsigned int, long unsigned int);\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct weighted_interleave_state {\n\tbool mode_auto;\n\tu8 iw_table[0];\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int one_bits;\n\tconst long unsigned int high_bits;\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n\tstruct bdi_writeback *wb;\n\tstruct inode *inode;\n\tint wb_id;\n\tint wb_lcand_id;\n\tint wb_tcand_id;\n\tsize_t wb_bytes;\n\tsize_t wb_lcand_bytes;\n\tsize_t wb_tcand_bytes;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[3];\n\t\tlong unsigned int marks[3];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xb1s_ff_report {\n\t__u8 report_id;\n\t__u8 enable;\n\t__u8 magnitude[4];\n\t__u8 duration_10ms;\n\t__u8 start_delay_10ms;\n\t__u8 loop_count;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n\tlong: 64;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 64;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n};\n\nstruct xdr_array2_desc;\n\ntypedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *, void *);\n\nstruct xdr_array2_desc {\n\tunsigned int elem_size;\n\tunsigned int array_len;\n\tunsigned int array_maxlen;\n\txdr_xcode_elem_t xcode;\n};\n\nstruct xdr_skb_reader {\n\tstruct sk_buff *skb;\n\tunsigned int offset;\n\tbool need_checksum;\n\tsize_t count;\n\t__wsum csum;\n};\n\nstruct xfrm4_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm4_protocol *next;\n\tint priority;\n};\n\nstruct xfrm6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tstruct xfrm6_protocol *next;\n\tint priority;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_dst {\n\tunion {\n\t\tstruct dst_entry dst;\n\t\tstruct rtable rt;\n\t\tstruct rt6_info rt6;\n\t} u;\n\tstruct dst_entry *route;\n\tstruct dst_entry *child;\n\tstruct dst_entry *path;\n\tstruct xfrm_policy *pols[2];\n\tint num_pols;\n\tint num_xfrms;\n\tu32 xfrm_genid;\n\tu32 policy_genid;\n\tu32 route_mtu_cached;\n\tu32 child_mtu_cached;\n\tu32 route_cookie;\n\tu32 path_cookie;\n};\n\nstruct xfrm_dst_lookup_params {\n\tstruct net *net;\n\tdscp_t dscp;\n\tint oif;\n\txfrm_address_t *saddr;\n\txfrm_address_t *daddr;\n\tu32 mark;\n\t__u8 ipproto;\n\tunion flowi_uli uli;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_flo {\n\tstruct dst_entry *dst_orig;\n\tu8 flags;\n};\n\nstruct xfrm_flow_keys {\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_control control;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t} addrs;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_keyid gre;\n};\n\nstruct xfrm_hash_state_ptrs {\n\tconst struct hlist_head *bydst;\n\tconst struct hlist_head *bysrc;\n\tconst struct hlist_head *byspi;\n\tunsigned int hmask;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_if_decode_session_result;\n\nstruct xfrm_if_cb {\n\tbool (*decode_session)(struct sk_buff *, short unsigned int, struct xfrm_if_decode_session_result *);\n};\n\nstruct xfrm_if_decode_session_result {\n\tstruct net *net;\n\tu32 if_id;\n};\n\nstruct xfrm_input_afinfo {\n\tu8 family;\n\tbool is_ipip;\n\tint (*callback)(struct sk_buff *, u8, int);\n};\n\nstruct xfrm_kmaddress {\n\txfrm_address_t local;\n\txfrm_address_t remote;\n\tu32 reserved;\n\tu16 family;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_tmpl;\n\nstruct xfrm_selector;\n\nstruct xfrm_migrate;\n\nstruct xfrm_mgr {\n\tstruct list_head list;\n\tint (*notify)(struct xfrm_state *, const struct km_event *);\n\tint (*acquire)(struct xfrm_state *, struct xfrm_tmpl *, struct xfrm_policy *);\n\tstruct xfrm_policy * (*compile_policy)(struct sock *, int, u8 *, int, int *);\n\tint (*new_mapping)(struct xfrm_state *, xfrm_address_t *, __be16);\n\tint (*notify_policy)(struct xfrm_policy *, int, const struct km_event *);\n\tint (*report)(struct net *, u8, struct xfrm_selector *, xfrm_address_t *);\n\tint (*migrate)(const struct xfrm_selector *, u8, u8, const struct xfrm_migrate *, int, const struct xfrm_kmaddress *, const struct xfrm_encap_tmpl *);\n\tbool (*is_alive)(const struct km_event *);\n};\n\nstruct xfrm_migrate {\n\txfrm_address_t old_daddr;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_daddr;\n\txfrm_address_t new_saddr;\n\tu8 proto;\n\tu8 mode;\n\tu16 reserved;\n\tu32 reqid;\n\tu16 old_family;\n\tu16 new_family;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_tunnel_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tunion {\n\t\tstruct ip_tunnel *ip4;\n\t\tstruct ip6_tnl *ip6;\n\t} tunnel;\n};\n\nstruct xfrm_mode_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\t__be16 id;\n\t__be16 frag_off;\n\tu8 ihl;\n\tu8 tos;\n\tu8 ttl;\n\tu8 protocol;\n\tu8 optlen;\n\tu8 flow_lbl[3];\n};\n\nstruct xfrm_pol_inexact_key {\n\tpossible_net_t net;\n\tu32 if_id;\n\tu16 family;\n\tu8 dir;\n\tu8 type;\n};\n\nstruct xfrm_pol_inexact_bin {\n\tstruct xfrm_pol_inexact_key k;\n\tstruct rhash_head head;\n\tstruct hlist_head hhead;\n\tseqcount_spinlock_t count;\n\tstruct rb_root root_d;\n\tstruct rb_root root_s;\n\tstruct list_head inexact_bins;\n\tstruct callback_head rcu;\n};\n\nstruct xfrm_pol_inexact_candidates {\n\tstruct hlist_head *res[4];\n};\n\nstruct xfrm_pol_inexact_node {\n\tstruct rb_node node;\n\tunion {\n\t\txfrm_address_t addr;\n\t\tstruct callback_head rcu;\n\t};\n\tu8 prefixlen;\n\tstruct rb_root root;\n\tstruct hlist_head hhead;\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_policy_walk_entry {\n\tstruct list_head all;\n\tu8 dead;\n};\n\nstruct xfrm_policy_queue {\n\tstruct sk_buff_head hold_queue;\n\tstruct timer_list hold_timer;\n\tlong unsigned int timeout;\n};\n\nstruct xfrm_tmpl {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tshort unsigned int encap_family;\n\tu32 reqid;\n\tu8 mode;\n\tu8 share;\n\tu8 optional;\n\tu8 allalgs;\n\tu32 aalgos;\n\tu32 ealgos;\n\tu32 calgos;\n};\n\nstruct xfrm_sec_ctx;\n\nstruct xfrm_policy {\n\tpossible_net_t xp_net;\n\tstruct hlist_node bydst;\n\tstruct hlist_node byidx;\n\tstruct hlist_head state_cache_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tu32 pos;\n\tstruct timer_list timer;\n\tatomic_t genid;\n\tu32 priority;\n\tu32 index;\n\tu32 if_id;\n\tstruct xfrm_mark mark;\n\tstruct xfrm_selector selector;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_policy_walk_entry walk;\n\tstruct xfrm_policy_queue polq;\n\tbool bydst_reinsert;\n\tu8 type;\n\tu8 action;\n\tu8 flags;\n\tu8 xfrm_nr;\n\tu16 family;\n\tstruct xfrm_sec_ctx *security;\n\tstruct xfrm_tmpl xfrm_vec[6];\n\tstruct callback_head rcu;\n\tstruct xfrm_dev_offload xdo;\n};\n\nstruct xfrm_policy_afinfo {\n\tstruct dst_ops *dst_ops;\n\tstruct dst_entry * (*dst_lookup)(const struct xfrm_dst_lookup_params *);\n\tint (*get_saddr)(xfrm_address_t *, const struct xfrm_dst_lookup_params *);\n\tint (*fill_dst)(struct xfrm_dst *, struct net_device *, const struct flowi *);\n\tstruct dst_entry * (*blackhole_route)(struct net *, struct dst_entry *);\n};\n\nstruct xfrm_policy_walk {\n\tstruct xfrm_policy_walk_entry walk;\n\tu8 type;\n\tu32 seq;\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 low;\n\t\t\t__u32 hi;\n\t\t} output;\n\t\tstruct {\n\t\t\t__be32 low;\n\t\t\t__be32 hi;\n\t\t} input;\n\t} seq;\n};\n\nstruct xfrm_spi_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunsigned int daddroff;\n\tunsigned int family;\n\t__be32 seq;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_state_afinfo {\n\tu8 family;\n\tu8 proto;\n\tconst struct xfrm_type_offload *type_offload_esp;\n\tconst struct xfrm_type *type_esp;\n\tconst struct xfrm_type *type_ipip;\n\tconst struct xfrm_type *type_ipip6;\n\tconst struct xfrm_type *type_comp;\n\tconst struct xfrm_type *type_ah;\n\tconst struct xfrm_type *type_routing;\n\tconst struct xfrm_type *type_dstopts;\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*transport_finish)(struct sk_buff *, int);\n\tvoid (*local_error)(struct sk_buff *, u32);\n};\n\nstruct xfrm_trans_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tint (*finish)(struct net *, struct sock *, struct sk_buff *);\n\tstruct net *net;\n};\n\nstruct xfrm_trans_tasklet {\n\tstruct work_struct work;\n\tspinlock_t queue_lock;\n\tstruct sk_buff_head queue;\n};\n\nstruct xfrm_translator {\n\tint (*alloc_compat)(struct sk_buff *, const struct nlmsghdr *);\n\tstruct nlmsghdr * (*rcv_msg_compat)(const struct nlmsghdr *, int, const struct nla_policy *, struct netlink_ext_ack *);\n\tint (*xlate_user_policy_sockptr)(u8 **, int);\n\tstruct module *owner;\n};\n\nstruct xfrm_tunnel {\n\tint (*handler)(struct sk_buff *);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm_tunnel *next;\n\tint priority;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xfrmk_sadinfo {\n\tu32 sadhcnt;\n\tu32 sadhmcnt;\n\tu32 sadcnt;\n};\n\nstruct xfrmk_spdinfo {\n\tu32 incnt;\n\tu32 outcnt;\n\tu32 fwdcnt;\n\tu32 inscnt;\n\tu32 outscnt;\n\tu32 fwdscnt;\n\tu32 spdhcnt;\n\tu32 spdhmcnt;\n};\n\nstruct xhci_bus_state {\n\tlong unsigned int bus_suspended;\n\tlong unsigned int next_statechange;\n\tu32 port_c_suspend;\n\tu32 suspended_ports;\n\tu32 port_remote_wakeup;\n\tlong unsigned int resuming_ports;\n};\n\nstruct xhci_bw_info {\n\tunsigned int ep_interval;\n\tunsigned int mult;\n\tunsigned int num_packets;\n\tunsigned int max_packet_size;\n\tunsigned int max_esit_payload;\n\tunsigned int type;\n};\n\nstruct xhci_cap_regs {\n\t__le32 hc_capbase;\n\t__le32 hcs_params1;\n\t__le32 hcs_params2;\n\t__le32 hcs_params3;\n\t__le32 hcc_params;\n\t__le32 db_off;\n\t__le32 run_regs_off;\n\t__le32 hcc_params2;\n};\n\nstruct xhci_container_ctx;\n\nstruct xhci_command {\n\tstruct xhci_container_ctx *in_ctx;\n\tu32 status;\n\tu32 comp_param;\n\tint slot_id;\n\tstruct completion *completion;\n\tunion xhci_trb *command_trb;\n\tstruct list_head cmd_list;\n\tunsigned int timeout_ms;\n};\n\nstruct xhci_container_ctx {\n\tunsigned int type;\n\tint size;\n\tu8 *bytes;\n\tdma_addr_t dma;\n};\n\nstruct xhci_erst_entry;\n\nstruct xhci_erst {\n\tstruct xhci_erst_entry *entries;\n\tunsigned int num_entries;\n\tdma_addr_t erst_dma_addr;\n};\n\nstruct xhci_hcd;\n\nstruct xhci_dbc {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tstruct xhci_hcd *xhci;\n\tstruct dbc_regs *regs;\n\tstruct xhci_ring *ring_evt;\n\tstruct xhci_ring *ring_in;\n\tstruct xhci_ring *ring_out;\n\tstruct xhci_erst erst;\n\tstruct xhci_container_ctx *ctx;\n\tstruct dbc_str_descs *str_descs;\n\tdma_addr_t str_descs_dma;\n\tsize_t str_descs_size;\n\tstruct dbc_str str;\n\tu16 idVendor;\n\tu16 idProduct;\n\tu16 bcdDevice;\n\tu8 bInterfaceProtocol;\n\tenum dbc_state state;\n\tstruct delayed_work event_work;\n\tunsigned int poll_interval;\n\tlong unsigned int xfer_timestamp;\n\tunsigned int resume_required: 1;\n\tstruct dbc_ep eps[2];\n\tconst struct dbc_driver *driver;\n\tvoid *priv;\n};\n\nstruct xhci_device_context_array {\n\t__le64 dev_context_ptrs[256];\n\tdma_addr_t dma;\n};\n\nstruct xhci_doorbell_array {\n\t__le32 doorbell[256];\n};\n\nstruct xhci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n};\n\nstruct xhci_ep_ctx {\n\t__le32 ep_info;\n\t__le32 ep_info2;\n\t__le64 deq;\n\t__le32 tx_info;\n\t__le32 reserved[3];\n};\n\nstruct xhci_stream_info;\n\nstruct xhci_ep_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *show_ring;\n\tunsigned int stream_id;\n};\n\nstruct xhci_erst_entry {\n\t__le64 seg_addr;\n\t__le32 seg_size;\n\t__le32 rsvd;\n};\n\nstruct xhci_event_cmd {\n\t__le64 cmd_trb;\n\t__le32 status;\n\t__le32 flags;\n};\n\nstruct xhci_file_map {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct xhci_generic_trb {\n\t__le32 field[4];\n};\n\nstruct xhci_port;\n\nstruct xhci_hub {\n\tstruct xhci_port **ports;\n\tunsigned int num_ports;\n\tstruct usb_hcd *hcd;\n\tstruct xhci_bus_state bus_state;\n\tu8 maj_rev;\n\tu8 min_rev;\n};\n\nstruct xhci_op_regs;\n\nstruct xhci_run_regs;\n\nstruct xhci_interrupter;\n\nstruct xhci_scratchpad;\n\nstruct xhci_virt_device;\n\nstruct xhci_root_port_bw_info;\n\nstruct xhci_port_cap;\n\nstruct xhci_hcd {\n\tstruct usb_hcd *main_hcd;\n\tstruct usb_hcd *shared_hcd;\n\tstruct xhci_cap_regs *cap_regs;\n\tstruct xhci_op_regs *op_regs;\n\tstruct xhci_run_regs *run_regs;\n\tstruct xhci_doorbell_array *dba;\n\t__u32 hcs_params2;\n\t__u32 hcs_params3;\n\t__u32 hcc_params;\n\t__u32 hcc_params2;\n\tspinlock_t lock;\n\tu16 hci_version;\n\tu16 max_interrupters;\n\tu8 max_slots;\n\tu8 max_ports;\n\tu32 imod_interval;\n\tu32 page_size;\n\tint nvecs;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\tstruct reset_control *reset;\n\tstruct xhci_device_context_array *dcbaa;\n\tstruct xhci_interrupter **interrupters;\n\tstruct xhci_ring *cmd_ring;\n\tunsigned int cmd_ring_state;\n\tstruct list_head cmd_list;\n\tunsigned int cmd_ring_reserved_trbs;\n\tstruct delayed_work cmd_timer;\n\tstruct completion cmd_ring_stop_completion;\n\tstruct xhci_command *current_cmd;\n\tstruct xhci_scratchpad *scratchpad;\n\tstruct mutex mutex;\n\tstruct xhci_virt_device *devs[256];\n\tstruct xhci_root_port_bw_info *rh_bw;\n\tstruct dma_pool *device_pool;\n\tstruct dma_pool *segment_pool;\n\tstruct dma_pool *small_streams_pool;\n\tstruct dma_pool *port_bw_pool;\n\tstruct dma_pool *medium_streams_pool;\n\tunsigned int xhc_state;\n\tlong unsigned int run_graceperiod;\n\tstruct s3_save s3;\n\tlong long unsigned int quirks;\n\tunsigned int num_active_eps;\n\tunsigned int limit_active_eps;\n\tstruct xhci_port *hw_ports;\n\tstruct xhci_hub usb2_rhub;\n\tstruct xhci_hub usb3_rhub;\n\tunsigned int hw_lpm_support: 1;\n\tunsigned int broken_suspend: 1;\n\tunsigned int allow_single_roothub: 1;\n\tstruct xhci_port_cap *port_caps;\n\tunsigned int num_port_caps;\n\tstruct timer_list comp_mode_recovery_timer;\n\tu32 port_status_u0;\n\tu16 test_mode;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_slots;\n\tstruct list_head regset_list;\n\tvoid *dbc;\n\tlong unsigned int priv[0];\n};\n\nstruct xhci_input_control_ctx {\n\t__le32 drop_flags;\n\t__le32 add_flags;\n\t__le32 rsvd2[6];\n};\n\nstruct xhci_intr_reg;\n\nstruct xhci_interrupter {\n\tstruct xhci_ring *event_ring;\n\tstruct xhci_erst erst;\n\tstruct xhci_intr_reg *ir_set;\n\tunsigned int intr_num;\n\tbool ip_autoclear;\n\tu32 isoc_bei_interval;\n\tu32 s3_iman;\n\tu32 s3_imod;\n\tu32 s3_erst_size;\n\tu64 s3_erst_base;\n\tu64 s3_erst_dequeue;\n};\n\nstruct xhci_interval_bw {\n\tunsigned int num_packets;\n\tstruct list_head endpoints;\n\tunsigned int overhead[3];\n};\n\nstruct xhci_interval_bw_table {\n\tunsigned int interval0_esit_payload;\n\tstruct xhci_interval_bw interval_bw[16];\n\tunsigned int bw_used;\n\tunsigned int ss_bw_in;\n\tunsigned int ss_bw_out;\n};\n\nstruct xhci_intr_reg {\n\t__le32 iman;\n\t__le32 imod;\n\t__le32 erst_size;\n\t__le32 rsvd;\n\t__le64 erst_base;\n\t__le64 erst_dequeue;\n};\n\nstruct xhci_link_trb {\n\t__le64 segment_ptr;\n\t__le32 intr_target;\n\t__le32 control;\n};\n\nstruct xhci_port_regs {\n\t__le32 portsc;\n\t__le32 portpmsc;\n\t__le32 portli;\n\t__le32 porthlmpc;\n};\n\nstruct xhci_op_regs {\n\t__le32 command;\n\t__le32 status;\n\t__le32 page_size;\n\t__le32 reserved1;\n\t__le32 reserved2;\n\t__le32 dev_notification;\n\t__le64 cmd_ring;\n\t__le32 reserved3[4];\n\t__le64 dcbaa_ptr;\n\t__le32 config_reg;\n\t__le32 reserved4[241];\n\tstruct xhci_port_regs port_regs[0];\n};\n\nstruct xhci_plat_priv {\n\tconst char *firmware_name;\n\tlong long unsigned int quirks;\n\tbool power_lost;\n\tunsigned int sideband_at_suspend: 1;\n\tvoid (*plat_start)(struct usb_hcd *);\n\tint (*init_quirk)(struct usb_hcd *);\n\tint (*suspend_quirk)(struct usb_hcd *);\n\tint (*resume_quirk)(struct usb_hcd *);\n\tint (*post_resume_quirk)(struct usb_hcd *);\n};\n\nstruct xhci_port {\n\tstruct xhci_port_regs *port_reg;\n\tint hw_portnum;\n\tint hcd_portnum;\n\tstruct xhci_hub *rhub;\n\tstruct xhci_port_cap *port_cap;\n\tunsigned int lpm_incapable: 1;\n\tlong unsigned int resume_timestamp;\n\tbool rexit_active;\n\tint slot_id;\n\tstruct completion rexit_done;\n\tstruct completion u3exit_done;\n};\n\nstruct xhci_port_cap {\n\tu32 *psi;\n\tu8 psi_count;\n\tu8 psi_uid_count;\n\tu8 maj_rev;\n\tu8 min_rev;\n\tu32 protocol_caps;\n};\n\nstruct xhci_regset {\n\tchar name[32];\n\tstruct debugfs_regset32 regset;\n\tsize_t nregs;\n\tstruct list_head list;\n};\n\nstruct xhci_ring {\n\tstruct xhci_segment *first_seg;\n\tstruct xhci_segment *last_seg;\n\tunion xhci_trb *enqueue;\n\tstruct xhci_segment *enq_seg;\n\tunion xhci_trb *dequeue;\n\tstruct xhci_segment *deq_seg;\n\tstruct list_head td_list;\n\tu32 cycle_state;\n\tunsigned int stream_id;\n\tunsigned int num_segs;\n\tunsigned int num_trbs_free;\n\tunsigned int bounce_buf_len;\n\tenum xhci_ring_type type;\n\tu32 old_trb_comp_code;\n\tstruct xarray *trb_address_map;\n};\n\nstruct xhci_root_port_bw_info {\n\tstruct list_head tts;\n\tunsigned int num_active_tts;\n\tstruct xhci_interval_bw_table bw_table;\n};\n\nstruct xhci_run_regs {\n\t__le32 microframe_index;\n\t__le32 rsvd[7];\n\tstruct xhci_intr_reg ir_set[1024];\n};\n\nstruct xhci_scratchpad {\n\tu64 *sp_array;\n\tdma_addr_t sp_dma;\n\tvoid **sp_buffers;\n};\n\nstruct xhci_segment {\n\tunion xhci_trb *trbs;\n\tstruct xhci_segment *next;\n\tunsigned int num;\n\tdma_addr_t dma;\n\tdma_addr_t bounce_dma;\n\tvoid *bounce_buf;\n\tunsigned int bounce_offs;\n\tunsigned int bounce_len;\n};\n\nstruct xhci_virt_ep;\n\nstruct xhci_sideband_event;\n\nstruct xhci_sideband {\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_virt_device *vdev;\n\tstruct xhci_virt_ep *eps[31];\n\tstruct xhci_interrupter *ir;\n\tenum xhci_sideband_type type;\n\tstruct mutex mutex;\n\tstruct usb_interface *intf;\n\tint (*notify_client)(struct usb_interface *, struct xhci_sideband_event *);\n};\n\nstruct xhci_sideband_event {\n\tenum xhci_sideband_notify_type type;\n\tvoid *evt_data;\n};\n\nstruct xhci_slot_ctx {\n\t__le32 dev_info;\n\t__le32 dev_info2;\n\t__le32 tt_info;\n\t__le32 dev_state;\n\t__le32 reserved[4];\n};\n\nstruct xhci_slot_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_ep_priv *eps[31];\n\tstruct xhci_virt_device *dev;\n};\n\nstruct xhci_stream_ctx {\n\t__le64 stream_ring;\n\t__le32 reserved[2];\n};\n\nstruct xhci_stream_info {\n\tstruct xhci_ring **stream_rings;\n\tunsigned int num_streams;\n\tstruct xhci_stream_ctx *stream_ctx_array;\n\tunsigned int num_stream_ctxs;\n\tdma_addr_t ctx_array_dma;\n\tstruct xarray trb_address_map;\n\tstruct xhci_command *free_streams_command;\n};\n\nstruct xhci_transfer_event {\n\t__le64 buffer;\n\t__le32 transfer_len;\n\t__le32 flags;\n};\n\nunion xhci_trb {\n\tstruct xhci_link_trb link;\n\tstruct xhci_transfer_event trans_event;\n\tstruct xhci_event_cmd event_cmd;\n\tstruct xhci_generic_trb generic;\n};\n\nstruct xhci_tt_bw_info {\n\tstruct list_head tt_list;\n\tint slot_id;\n\tint ttport;\n\tstruct xhci_interval_bw_table bw_table;\n\tint active_eps;\n};\n\nstruct xhci_virt_ep {\n\tstruct xhci_virt_device *vdev;\n\tunsigned int ep_index;\n\tstruct xhci_ring *ring;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *new_ring;\n\tunsigned int err_count;\n\tunsigned int ep_state;\n\tstruct list_head cancelled_td_list;\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_segment *queued_deq_seg;\n\tunion xhci_trb *queued_deq_ptr;\n\tbool skip;\n\tstruct xhci_bw_info bw_info;\n\tstruct list_head bw_endpoint_list;\n\tlong unsigned int stop_time;\n\tint next_frame_id;\n\tbool use_extended_tbc;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xhci_virt_device {\n\tint slot_id;\n\tstruct usb_device *udev;\n\tstruct xhci_container_ctx *out_ctx;\n\tstruct xhci_container_ctx *in_ctx;\n\tstruct xhci_virt_ep eps[31];\n\tstruct xhci_port *rhub_port;\n\tstruct xhci_interval_bw_table *bw_table;\n\tstruct xhci_tt_bw_info *tt_info;\n\tlong unsigned int flags;\n\tu16 current_mel;\n\tvoid *debugfs_private;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xilinx_pcie {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tlong unsigned int msi_map[2];\n\tstruct mutex map_lock;\n\tstruct irq_domain *msi_domain;\n\tstruct irq_domain *leg_domain;\n\tstruct list_head resources;\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tlong unsigned int *bitmap;\n\tstruct page *page;\n\tlong unsigned int vaddr;\n};\n\nstruct xprt_addr {\n\tconst char *addr;\n\tstruct callback_head rcu;\n};\n\nstruct xprt_create;\n\nstruct xprt_class {\n\tstruct list_head list;\n\tint ident;\n\tstruct rpc_xprt * (*setup)(struct xprt_create *);\n\tstruct module *owner;\n\tchar name[32];\n\tconst char *netid[0];\n};\n\nstruct xprt_create {\n\tint ident;\n\tstruct net *net;\n\tstruct sockaddr *srcaddr;\n\tstruct sockaddr *dstaddr;\n\tsize_t addrlen;\n\tconst char *servername;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rpc_xprt_switch *bc_xps;\n\tunsigned int flags;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct yt8521_priv {\n\tlong unsigned int combo_advertising[2];\n\tu8 polling_mode;\n\tu8 strap_mode;\n\tu8 reg_page;\n};\n\nstruct ytphy_cfg_reg_map {\n\tu32 cfg;\n\tu32 reg;\n};\n\nstruct ytphy_ldo_vol_map {\n\tu32 vol;\n\tu32 ds;\n\tu32 cur;\n};\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef void (*RecordEvents_f)(Fingerprint *, const void *, size_t);\n\ntypedef size_t (*ZSTD_BlockCompressor_f)(ZSTD_MatchState_t *, SeqStore_t *, U32 *, const void *, size_t);\n\ntypedef size_t (*ZSTD_SequenceCopier_f)(ZSTD_CCtx *, ZSTD_SequencePosition *, const ZSTD_Sequence * const, size_t, const void *, size_t, ZSTD_ParamSwitch_e);\n\ntypedef U32 (*ZSTD_getAllMatchesFn)(ZSTD_match_t *, ZSTD_MatchState_t *, U32 *, const BYTE *, const BYTE *, const U32 *, const U32, const U32);\n\ntypedef int (*ZSTD_match4Found)(const BYTE *, const BYTE *, U32, U32);\n\ntypedef u32 (*acpi_event_handler)(void *);\n\ntypedef acpi_status (*acpi_exception_handler)(acpi_status, acpi_name, u16, u32, void *);\n\ntypedef acpi_status (*acpi_execute_op)(struct acpi_walk_state *);\n\ntypedef void (*acpi_gbl_event_handler)(u32, acpi_handle, u32, void *);\n\ntypedef struct fwnode_handle * (*acpi_gsi_domain_disp_fn)(u32);\n\ntypedef acpi_status (*acpi_init_handler)(acpi_handle, u32);\n\ntypedef u32 (*acpi_interface_handler)(acpi_string, u32);\n\ntypedef u32 (*acpi_osd_handler)(void *);\n\ntypedef acpi_status (*acpi_pkg_callback)(u8, union acpi_operand_object *, union acpi_generic_state *, void *);\n\ntypedef acpi_status (*acpi_table_handler)(u32, void *, void *);\n\ntypedef acpi_status (*acpi_walk_aml_callback)(u8 *, u32, u32, u8, void **);\n\ntypedef acpi_status (*acpi_walk_resource_callback)(struct acpi_resource *, void *);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u32 (*bpf_prog_run_fn)(const struct bpf_prog *, const void *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_d_path)(const struct path *, char *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_pe)(struct bpf_perf_event_data_kern *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_trace)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_branch_snapshot)(void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid_curr)(void);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_task)(void);\n\ntypedef u64 (*btf_bpf_get_current_task_btf)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_func_ip_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_local_storage)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sockopt)(struct bpf_sockopt_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_retval)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_pe)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_sleepable)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_pe)(struct bpf_perf_event_data_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack_sleepable)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_probe_read_compat)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_printf_btf)(struct seq_file *, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_set_retval)(int);\n\ntypedef u64 (*btf_bpf_sk_ancestor_cgroup_id)(struct sock *, int);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_cgroup_id)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_ancestor_cgroup_id)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_cgroup_id)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_get_xfrm_state)(struct sk_buff *, u32, struct bpf_xfrm_state *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_snprintf_btf)(char *, u32, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_sysctl_get_current_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_get_name)(struct bpf_sysctl_kern *, char *, size_t, u64);\n\ntypedef u64 (*btf_bpf_sysctl_get_new_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_set_new_value)(struct bpf_sysctl_kern *, const char *, size_t);\n\ntypedef u64 (*btf_bpf_task_pt_regs)(struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_vprintk)(char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_get_func_arg)(void *, u32, u64 *);\n\ntypedef u64 (*btf_get_func_arg_cnt)(void *);\n\ntypedef u64 (*btf_get_func_ret)(void *, u64 *);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*btf_trace_9p_client_req)(void *, struct p9_client *, int8_t, int);\n\ntypedef void (*btf_trace_9p_client_res)(void *, struct p9_client *, int8_t, int, int);\n\ntypedef void (*btf_trace_9p_fid_ref)(void *, struct p9_fid *, __u8);\n\ntypedef void (*btf_trace_9p_protocol_dump)(void *, struct p9_client *, struct p9_fcall *);\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_suspend)(void *, ktime_t, int);\n\ntypedef void (*btf_trace_alloc_vmap_area)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_ata_bmdma_setup)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_start)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_status)(void *, struct ata_port *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_stop)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_about_to_do)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_done)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy)(void *, struct ata_device *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy_qc)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_exec_command)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_softreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_softreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_port_freeze)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_port_thaw)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_qc_complete_done)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_failed)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_internal)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_issue)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_prep)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_sff_flush_pio_task)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_sff_hsm_command_complete)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_hsm_state)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_sff_port_intr)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_slave_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_slave_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_slave_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_std_sched_eh)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_tf_load)(void *, struct ata_port *, const struct ata_taskfile *);\n\ntypedef void (*btf_trace_atapi_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_atapi_send_cdb)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, struct dirty_throttle_control *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_bl_ext_tree_prepare_commit)(void *, int, size_t, u64, bool);\n\ntypedef void (*btf_trace_bl_pr_key_reg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_reg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_bl_pr_key_unreg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_unreg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_blk_zone_append_update_request_bio)(void *, struct request *);\n\ntypedef void (*btf_trace_blk_zone_wplug_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_blkdev_zone_mgmt)(void *, struct bio *, sector_t);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_io_done)(void *, struct request *);\n\ntypedef void (*btf_trace_block_io_start)(void *, struct request *);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_error)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_merge)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_split)(void *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\ntypedef void (*btf_trace_bpf_trace_printk)(void *, const char *);\n\ntypedef void (*btf_trace_bpf_trigger_tp)(void *, int);\n\ntypedef void (*btf_trace_bpf_xdp_link_attach_failed)(void *, const char *);\n\ntypedef void (*btf_trace_br_fdb_add)(void *, struct ndmsg *, struct net_device *, const unsigned char *, u16, u16);\n\ntypedef void (*btf_trace_br_fdb_external_learn_add)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16);\n\ntypedef void (*btf_trace_br_fdb_update)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16, long unsigned int);\n\ntypedef void (*btf_trace_br_mdb_full)(void *, const struct net_device *, const struct br_ip *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_cache_entry_expired)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_make_negative)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_no_listener)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_upcall)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_update)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cap_capable)(void *, const struct cred *, struct user_namespace *, const struct user_namespace *, int, int);\n\ntypedef void (*btf_trace_cdev_update)(void *, struct thermal_cooling_device *, long unsigned int);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rstat_lock_contended)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_locked)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_unlock)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_clk_disable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_disable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_enable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_enable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_rate_request_done)(void *, struct clk_rate_request *);\n\ntypedef void (*btf_trace_clk_rate_request_start)(void *, struct clk_rate_request *);\n\ntypedef void (*btf_trace_clk_set_duty_cycle)(void *, struct clk_core *, struct clk_duty *);\n\ntypedef void (*btf_trace_clk_set_duty_cycle_complete)(void *, struct clk_core *, struct clk_duty *);\n\ntypedef void (*btf_trace_clk_set_max_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_min_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_parent)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_parent_complete)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_phase)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_phase_complete)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_rate_complete)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_rate_range)(void *, struct clk_core *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_clk_unprepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_unprepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_contention_begin)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_contention_end)(void *, void *, int);\n\ntypedef void (*btf_trace_count_memcg_events)(void *, struct mem_cgroup *, int, long unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_idle_miss)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_csd_function_entry)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_function_exit)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_queue_cpu)(void *, const unsigned int, long unsigned int, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_ctime_ns_xchg)(void *, struct inode *, u32, u32, u32);\n\ntypedef void (*btf_trace_ctime_xchg_skip)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_devfreq_frequency)(void *, struct devfreq *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_devfreq_monitor)(void *, struct devfreq *);\n\ntypedef void (*btf_trace_device_pm_callback_end)(void *, struct device *, int);\n\ntypedef void (*btf_trace_device_pm_callback_start)(void *, struct device *, const char *, int);\n\ntypedef void (*btf_trace_devlink_health_recover_aborted)(void *, const struct devlink *, const char *, bool, u64);\n\ntypedef void (*btf_trace_devlink_health_report)(void *, const struct devlink *, const char *, const char *);\n\ntypedef void (*btf_trace_devlink_health_reporter_state_update)(void *, const struct devlink *, const char *, bool);\n\ntypedef void (*btf_trace_devlink_hwerr)(void *, const struct devlink *, int, const char *);\n\ntypedef void (*btf_trace_devlink_hwmsg)(void *, const struct devlink *, bool, long unsigned int, const u8 *, size_t);\n\ntypedef void (*btf_trace_devlink_trap_report)(void *, const struct devlink *, struct sk_buff *, const struct devlink_trap_metadata *);\n\ntypedef void (*btf_trace_devres_log)(void *, struct device *, const char *, void *, const char *, size_t);\n\ntypedef void (*btf_trace_disk_zone_wplug_add_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_dma_alloc)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt_err)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_buf_detach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_dynamic_attach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_export)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_fd)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_get)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_mmap)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_mmap_internal)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_put)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_free)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_map_phys)(void *, struct device *, phys_addr_t, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg_err)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_sync_sg_for_cpu)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_sg_for_device)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_cpu)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_device)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_unmap_phys)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_unmap_sg)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dql_stall_detected)(void *, short unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_e1000e_trace_mac_register)(void *, uint32_t);\n\ntypedef void (*btf_trace_error_report_end)(void *, enum error_detector, long unsigned int);\n\ntypedef void (*btf_trace_exit_mmap)(void *, struct mm_struct *);\n\ntypedef void (*btf_trace_ext4_alloc_da_blocks)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_allocate_blocks)(void *, struct ext4_allocation_request *, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_allocate_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_begin_ordered_truncate)(void *, struct inode *, loff_t);\n\ntypedef void (*btf_trace_ext4_collapse_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_da_release_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_reserve_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_update_reserve_space)(void *, struct inode *, int, int);\n\ntypedef void (*btf_trace_ext4_da_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_end)(void *, struct inode *, loff_t, loff_t, struct writeback_control *, int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_start)(void *, struct inode *, loff_t, loff_t, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages_extent)(void *, struct inode *, struct ext4_map_blocks *);\n\ntypedef void (*btf_trace_ext4_discard_blocks)(void *, struct super_block *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_discard_preallocations)(void *, struct inode *, unsigned int);\n\ntypedef void (*btf_trace_ext4_drop_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_error)(void *, struct super_block *, const char *, unsigned int);\n\ntypedef void (*btf_trace_ext4_es_cache_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_exit)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_insert_delayed_extent)(void *, struct inode *, struct extent_status *, bool, bool);\n\ntypedef void (*btf_trace_ext4_es_insert_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_exit)(void *, struct inode *, struct extent_status *, int);\n\ntypedef void (*btf_trace_ext4_es_remove_extent)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_shrink)(void *, struct super_block *, int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_count)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_enter)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_exit)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_enter)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_fastpath)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_handle_unwritten_extents)(void *, struct inode *, struct ext4_map_blocks *, int, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_load_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space_done)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, struct partial_cluster *, __le16);\n\ntypedef void (*btf_trace_ext4_ext_rm_idx)(void *, struct inode *, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_rm_leaf)(void *, struct inode *, ext4_lblk_t, struct ext4_extent *, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_show_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t, short unsigned int);\n\ntypedef void (*btf_trace_ext4_fallocate_enter)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_fallocate_exit)(void *, struct inode *, loff_t, unsigned int, int);\n\ntypedef void (*btf_trace_ext4_fc_cleanup)(void *, journal_t *, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_start)(void *, struct super_block *, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_stop)(void *, struct super_block *, int, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_replay)(void *, struct super_block *, int, int, int, int);\n\ntypedef void (*btf_trace_ext4_fc_replay_scan)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_fc_stats)(void *, struct super_block *);\n\ntypedef void (*btf_trace_ext4_fc_track_create)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_inode)(void *, handle_t *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_link)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_range)(void *, handle_t *, struct inode *, long int, long int, int);\n\ntypedef void (*btf_trace_ext4_fc_track_unlink)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_forget)(void *, struct inode *, int, __u64);\n\ntypedef void (*btf_trace_ext4_free_blocks)(void *, struct inode *, __u64, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_fsmap_high_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_low_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_mapping)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_get_implied_cluster_alloc_exit)(void *, struct super_block *, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_getfsmap_high_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_low_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_mapping)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_insert_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journal_start_inode)(void *, struct inode *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_reserved)(void *, struct super_block *, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_sb)(void *, struct super_block *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journalled_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_lazy_itable_init)(void *, struct super_block *, ext4_group_t);\n\ntypedef void (*btf_trace_ext4_load_inode)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_load_inode_bitmap)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mark_inode_dirty)(void *, struct inode *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_buddy_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_discard_preallocations)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_mb_new_group_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_new_inode_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_group_pa)(void *, struct super_block *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_inode_pa)(void *, struct ext4_prealloc_space *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_mballoc_alloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_discard)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_free)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_prealloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_move_extent_enter)(void *, struct inode *, struct ext4_map_blocks *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_move_extent_exit)(void *, struct inode *, ext4_lblk_t, struct inode *, ext4_lblk_t, unsigned int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_nfs_commit_metadata)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_other_inode_update_time)(void *, struct inode *, ino_t);\n\ntypedef void (*btf_trace_ext4_prefetch_bitmaps)(void *, struct super_block *, ext4_group_t, ext4_group_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_punch_hole)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_read_block_bitmap_load)(void *, struct super_block *, long unsigned int, bool);\n\ntypedef void (*btf_trace_ext4_read_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_release_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_remove_blocks)(void *, struct inode *, struct ext4_extent *, ext4_lblk_t, ext4_fsblk_t, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_request_blocks)(void *, struct ext4_allocation_request *);\n\ntypedef void (*btf_trace_ext4_request_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_shutdown)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_sync_file_enter)(void *, struct file *, int);\n\ntypedef void (*btf_trace_ext4_sync_file_exit)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_sync_fs)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_trim_all_free)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_trim_extent)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_truncate_enter)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_truncate_exit)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_unlink_enter)(void *, struct inode *, struct dentry *);\n\ntypedef void (*btf_trace_ext4_unlink_exit)(void *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_update_sb)(void *, struct super_block *, ext4_fsblk_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_writepages)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_writepages_result)(void *, struct inode *, struct writeback_control *, int, int);\n\ntypedef void (*btf_trace_ext4_zero_range)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_fdb_delete)(void *, struct net_bridge *, struct net_bridge_fdb_entry *);\n\ntypedef void (*btf_trace_ff_layout_commit_error)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_ff_layout_read_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_ff_layout_write_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_fib6_table_lookup)(void *, const struct net *, const struct fib6_result *, struct fib6_table *, const struct flowi6 *);\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_fill_mg_cmtime)(void *, struct inode *, struct timespec64 *, struct timespec64 *);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_fl_getdevinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, char *);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_flush_foreign)(void *, struct bdi_writeback *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_folio_wait_writeback)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_free_vmap_area_noflush)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_gpio_direction)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_gpio_value)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_guest_halt_poll_ns)(void *, bool, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_handshake_cancel)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_busy)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_none)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cmd_accept)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_accept_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_complete)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_destruct)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_notify_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_submit)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_submit_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_setup)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hugetlbfs_alloc_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_hugetlbfs_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_fallocate)(void *, struct inode *, int, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_hugetlbfs_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_setattr)(void *, struct inode *, struct dentry *, struct iattr *);\n\ntypedef void (*btf_trace_hw_pressure_update)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_hwmon_attr_show)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_hwmon_attr_show_string)(void *, int, const char *, const char *);\n\ntypedef void (*btf_trace_hwmon_attr_store)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_i2c_read)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_reply)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_result)(void *, const struct i2c_adapter *, int, int);\n\ntypedef void (*btf_trace_i2c_write)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_icmp_send)(void *, const struct sk_buff *, int, int);\n\ntypedef void (*btf_trace_inet_sk_error_report)(void *, const struct sock *);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_inode_foreign_history)(void *, struct inode *, struct writeback_control *, unsigned int);\n\ntypedef void (*btf_trace_inode_set_ctime_to_ts)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_inode_switch_wbs)(void *, struct inode *, struct bdi_writeback *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_inode_switch_wbs_queue)(void *, struct bdi_writeback *, struct bdi_writeback *, unsigned int);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, struct io_ring_ctx *, void *, struct io_uring_cqe *);\n\ntypedef void (*btf_trace_io_uring_cqe_overflow)(void *, void *, long long unsigned int, s32, u32, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_local_work_run)(void *, void *, int, unsigned int);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, struct io_kiocb *, int, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, struct io_kiocb *, bool);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, long int);\n\ntypedef void (*btf_trace_io_uring_req_failed)(void *, const struct io_uring_sqe *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_short_write)(void *, void *, u64, u64, u64);\n\ntypedef void (*btf_trace_io_uring_submit_req)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_task_work_run)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_iomap_add_to_ioend)(void *, struct inode *, u64, unsigned int, struct iomap *);\n\ntypedef void (*btf_trace_iomap_dio_complete)(void *, struct kiocb *, int, ssize_t);\n\ntypedef void (*btf_trace_iomap_dio_invalidate_fail)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_dio_rw_begin)(void *, struct kiocb *, struct iov_iter *, unsigned int, size_t);\n\ntypedef void (*btf_trace_iomap_dio_rw_queued)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_invalidate_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_iter)(void *, struct iomap_iter *, const void *, long unsigned int);\n\ntypedef void (*btf_trace_iomap_iter_dstmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_iter_srcmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_release_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_writeback_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_zero_iter)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_ipi_send_cpu)(void *, const unsigned int, long unsigned int, void *);\n\ntypedef void (*btf_trace_ipi_send_cpumask)(void *, const struct cpumask *, long unsigned int, void *);\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_irq_matrix_alloc)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_alloc_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_assign)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_assign_system)(void *, int, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_free)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_offline)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_online)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_remove_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_remove_reserved)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_reserve)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_reserve_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_jbd2_checkpoint)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_checkpoint_stats)(void *, dev_t, tid_t, struct transaction_chp_stats_s *);\n\ntypedef void (*btf_trace_jbd2_commit_flushing)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_locking)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_logging)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_drop_transaction)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_end_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_handle_extend)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int);\n\ntypedef void (*btf_trace_jbd2_handle_restart)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_start)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_stats)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int, int, int);\n\ntypedef void (*btf_trace_jbd2_lock_buffer_stall)(void *, dev_t, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_run_stats)(void *, dev_t, tid_t, struct transaction_run_stats_s *);\n\ntypedef void (*btf_trace_jbd2_shrink_checkpoint_list)(void *, journal_t *, tid_t, tid_t, tid_t, long unsigned int, tid_t);\n\ntypedef void (*btf_trace_jbd2_shrink_count)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_enter)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_exit)(void *, journal_t *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_start_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_submit_inode_data)(void *, struct inode *);\n\ntypedef void (*btf_trace_jbd2_update_log_tail)(void *, journal_t *, tid_t, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_write_superblock)(void *, journal_t *, blk_opf_t);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *, enum skb_drop_reason, struct sock *);\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, struct kmem_cache *, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *, const struct kmem_cache *);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, dev_t, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_latency)(void *, dev_t, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, dev_t, const char *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lease *, struct file_lease *);\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ma_op)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_read)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_write)(void *, const char *, struct ma_state *, long unsigned int, void *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_mark_victim)(void *, struct task_struct *, uid_t);\n\ntypedef void (*btf_trace_mdio_access)(void *, struct mii_bus *, char, u8, unsigned int, u16, int);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_memcg_flush_stats)(void *, struct mem_cgroup *, s64, bool, bool);\n\ntypedef void (*btf_trace_mm_calculate_totalreserve_pages)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, struct compact_control *, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, struct compact_control *, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_fast_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_fault)(void *, struct address_space *, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_get_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_map_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_migrate_pages_start)(void *, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_lowmem_reserve)(void *, struct zone *, struct zone *, long int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_wmarks)(void *, struct zone *);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_clear_hopeless)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_reclaim_fail)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_reclaim_pages)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *);\n\ntypedef void (*btf_trace_mm_vmscan_throttled)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_write_folio)(void *, struct folio *);\n\ntypedef void (*btf_trace_mmap_lock_acquire_returned)(void *, struct mm_struct *, bool, bool);\n\ntypedef void (*btf_trace_mmap_lock_released)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmap_lock_start_locking)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmc_request_done)(void *, struct mmc_host *, struct mmc_request *);\n\ntypedef void (*btf_trace_mmc_request_start)(void *, struct mmc_host *, struct mmc_request *);\n\ntypedef void (*btf_trace_mod_memcg_lruvec_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_mod_memcg_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_netfs_collect)(void *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_collect_folio)(void *, const struct netfs_io_request *, const struct folio *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_gap)(void *, const struct netfs_io_request *, const struct netfs_io_stream *, long long unsigned int, char);\n\ntypedef void (*btf_trace_netfs_collect_sreq)(void *, const struct netfs_io_request *, const struct netfs_io_subrequest *);\n\ntypedef void (*btf_trace_netfs_collect_state)(void *, const struct netfs_io_request *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_stream)(void *, const struct netfs_io_request *, const struct netfs_io_stream *);\n\ntypedef void (*btf_trace_netfs_copy2cache)(void *, const struct netfs_io_request *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_failure)(void *, struct netfs_io_request *, struct netfs_io_subrequest *, int, enum netfs_failure);\n\ntypedef void (*btf_trace_netfs_folio)(void *, struct folio *, enum netfs_folio_trace);\n\ntypedef void (*btf_trace_netfs_folioq)(void *, const struct folio_queue *, enum netfs_folioq_trace);\n\ntypedef void (*btf_trace_netfs_read)(void *, struct netfs_io_request *, loff_t, size_t, enum netfs_read_trace);\n\ntypedef void (*btf_trace_netfs_rreq)(void *, struct netfs_io_request *, enum netfs_rreq_trace);\n\ntypedef void (*btf_trace_netfs_rreq_ref)(void *, unsigned int, int, enum netfs_rreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_sreq)(void *, struct netfs_io_subrequest *, enum netfs_sreq_trace);\n\ntypedef void (*btf_trace_netfs_sreq_ref)(void *, unsigned int, unsigned int, int, enum netfs_sreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_write)(void *, const struct netfs_io_request *, enum netfs_write_trace);\n\ntypedef void (*btf_trace_netfs_write_iter)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netlink_extack)(void *, const char *);\n\ntypedef void (*btf_trace_nfs41_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_access)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_bind_conn_to_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_cached_open)(void *, const struct nfs4_state *);\n\ntypedef void (*btf_trace_nfs4_cb_getattr)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_cb_layoutrecall_file)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_offload)(void *, const struct nfs_fh *, const nfs4_stateid *, uint64_t, int, int);\n\ntypedef void (*btf_trace_nfs4_cb_recall)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_seqid_err)(void *, const struct cb_sequenceargs *, __be32);\n\ntypedef void (*btf_trace_nfs4_cb_sequence)(void *, const struct cb_sequenceargs *, const struct cb_sequenceres *, __be32);\n\ntypedef void (*btf_trace_nfs4_clone)(void *, const struct inode *, const struct inode *, const struct nfs42_clone_args *, int);\n\ntypedef void (*btf_trace_nfs4_close)(void *, const struct nfs4_state *, const struct nfs_closeargs *, const struct nfs_closeres *, int);\n\ntypedef void (*btf_trace_nfs4_close_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_commit)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_copy)(void *, const struct inode *, const struct inode *, const struct nfs42_copy_args *, const struct nfs42_copy_res *, const struct nl4_server *, int);\n\ntypedef void (*btf_trace_nfs4_copy_notify)(void *, const struct inode *, const struct nfs42_copy_notify_args *, const struct nfs42_copy_notify_res *, int);\n\ntypedef void (*btf_trace_nfs4_create_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_deallocate)(void *, const struct inode *, const struct nfs42_falloc_args *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn_exit)(void *, const struct nfs4_delegreturnargs *, const struct nfs4_delegreturnres *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_clientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_detach_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_deviceid_free)(void *, const struct nfs_client *, const struct nfs4_deviceid *);\n\ntypedef void (*btf_trace_nfs4_exchange_id)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_fallocate)(void *, const struct inode *, const struct nfs42_falloc_args *, int);\n\ntypedef void (*btf_trace_nfs4_find_deviceid)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_fsinfo)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_get_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_get_fs_locations)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_get_lock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_get_security_label)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_getattr)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_getdeviceinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_getxattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_layoutcommit)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layouterror)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutget)(void *, const struct nfs_open_context *, const struct pnfs_layout_range *, const struct pnfs_layout_range *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn_on_close)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutstats)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_listxattr)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_llseek)(void *, const struct inode *, const struct nfs42_seek_args *, const struct nfs42_seek_res *, int);\n\ntypedef void (*btf_trace_nfs4_lookup)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_lookup_root)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_lookupp)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_map_gid_to_group)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_group_to_gid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_name_to_uid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_uid_to_name)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_mkdir)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_mknod)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_offload_cancel)(void *, const struct nfs42_offload_status_args *, int);\n\ntypedef void (*btf_trace_nfs4_offload_status)(void *, const struct nfs42_offload_status_args *, int);\n\ntypedef void (*btf_trace_nfs4_open_expired)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_file)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_reclaim)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_skip)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_commit_ds)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_readdir)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_readlink)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_complete)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_remove)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_removexattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_rename)(void *, const struct inode *, const struct qstr *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_renew)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_renew_async)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_secinfo)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_sequence)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_sequence_done)(void *, const struct nfs4_session *, const struct nfs4_sequence_res *);\n\ntypedef void (*btf_trace_nfs4_set_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_set_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_set_lock)(void *, const struct file_lock *, const struct nfs4_state *, const nfs4_stateid *, int, int);\n\ntypedef void (*btf_trace_nfs4_set_security_label)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_setattr)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid_confirm)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setup_sequence)(void *, const struct nfs4_session *, const struct nfs4_sequence_args *);\n\ntypedef void (*btf_trace_nfs4_setxattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_state_lock_reclaim)(void *, const struct nfs4_state *, const struct nfs4_lock_state *);\n\ntypedef void (*btf_trace_nfs4_state_mgr)(void *, const struct nfs_client *);\n\ntypedef void (*btf_trace_nfs4_state_mgr_failed)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_symlink)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_test_delegation_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_lock_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_open_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_trunked_exchange_id)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_unlock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_filehandle)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_operation)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_status)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs_access_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_access_exit)(void *, const struct inode *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readahead)(void *, const struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_nfs_aop_readahead_done)(void *, const struct inode *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readpage)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_aop_readpage_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_async_rename_done)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_atomic_open_enter)(void *, const struct inode *, const struct nfs_open_context *, unsigned int);\n\ntypedef void (*btf_trace_nfs_atomic_open_exit)(void *, const struct inode *, const struct nfs_open_context *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_cb_badprinc)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_cb_no_clp)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_commit_done)(void *, const struct rpc_task *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_commit_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_comp_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_create_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_create_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_delegation_need_return)(void *, const struct nfs_delegation *);\n\ntypedef void (*btf_trace_nfs_direct_commit_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_resched_write)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_completion)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_reschedule_io)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_schedule_iovec)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_do_writepage)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_fh_to_dentry)(void *, const struct super_block *, const struct nfs_fh *, u64, int);\n\ntypedef void (*btf_trace_nfs_file_read)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_file_write)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_fsync_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_fsync_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_getattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_getattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_initiate_commit)(void *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_initiate_read)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_initiate_write)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_invalidate_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_launder_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_link_enter)(void *, const struct inode *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_link_exit)(void *, const struct inode *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_local_open_fh)(void *, const struct nfs_fh *, fmode_t, int);\n\ntypedef void (*btf_trace_nfs_lookup_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_mkdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mkdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mknod_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mknod_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mount_assign)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_nfs_mount_option)(void *, const struct fs_parameter *);\n\ntypedef void (*btf_trace_nfs_mount_path)(void *, const char *);\n\ntypedef void (*btf_trace_nfs_pgio_error)(void *, const struct nfs_pgio_header *, int, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readdir_force_readdirplus)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_readdir_invalidate_cache_range)(void *, const struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_lookup)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate_failed)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readpage_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_readpage_short)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_remove_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_remove_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_rename_enter)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rename_exit)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_rmdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rmdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_set_cache_invalid)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_set_inode_stale)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_sillyrename_unlink)(void *, const struct nfs_unlinkdata *, int);\n\ntypedef void (*btf_trace_nfs_size_grow)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate_folio)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_update)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_wcc)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_symlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_symlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_try_to_update_request)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_try_to_update_request_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_unlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_unlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_update_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_update_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_begin)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_begin_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_end)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_end_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_writeback_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_writeback_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_writeback_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_writepage_setup)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_writepages)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writepages_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_xdr_bad_filehandle)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nfs_xdr_status)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nlmclnt_grant)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_lock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_test)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_unlock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_notifier_register)(void *, void *);\n\ntypedef void (*btf_trace_notifier_run)(void *, void *);\n\ntypedef void (*btf_trace_notifier_unregister)(void *, void *);\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_page_cache_async_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_ra_order)(void *, struct inode *, long unsigned int, struct file_ra_state *);\n\ntypedef void (*btf_trace_page_cache_ra_unbounded)(void *, struct inode *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_sync_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_fault_kernel)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\ntypedef void (*btf_trace_page_fault_user)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\ntypedef void (*btf_trace_page_pool_release)(void *, const struct page_pool *, s32, u32, u32);\n\ntypedef void (*btf_trace_page_pool_state_hold)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_state_release)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_update_nid)(void *, const struct page_pool *, int);\n\ntypedef void (*btf_trace_pci_hp_event)(void *, const char *, const char *, const int);\n\ntypedef void (*btf_trace_pcie_link_event)(void *, struct pci_bus *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pelt_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_pelt_dl_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_hw_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_irq_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_rt_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, long unsigned int, bool, bool, size_t, size_t, void *, int, void *, size_t, gfp_t);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pmap_register)(void *, u32, u32, int, short unsigned int);\n\ntypedef void (*btf_trace_pnfs_ds_connect)(void *, char *, int);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_get_mirror_count)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_read)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_write)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_update_layout)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *, enum pnfs_update_layout_reason);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_purge_vmap_area_lazy)(void *, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pwm_apply)(void *, struct pwm_device *, const struct pwm_state *, int);\n\ntypedef void (*btf_trace_pwm_get)(void *, struct pwm_device *, const struct pwm_state *, int);\n\ntypedef void (*btf_trace_pwm_read_waveform)(void *, struct pwm_device *, void *, int);\n\ntypedef void (*btf_trace_pwm_round_waveform_fromhw)(void *, struct pwm_device *, const void *, struct pwm_waveform *, int);\n\ntypedef void (*btf_trace_pwm_round_waveform_tohw)(void *, struct pwm_device *, const struct pwm_waveform *, void *, int);\n\ntypedef void (*btf_trace_pwm_write_waveform)(void *, struct pwm_device *, const void *, int);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_enqueue)(void *, struct Qdisc *, const struct netdev_queue *, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_invoke_kvfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_segcb_stats)(void *, struct rcu_segcblist *, const char *);\n\ntypedef void (*btf_trace_rcu_sr_normal)(void *, const char *, struct callback_head *, const char *);\n\ntypedef void (*btf_trace_rcu_stall_warning)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_watching)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_regcache_drop_region)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regcache_sync)(void *, struct regmap *, const char *, const char *);\n\ntypedef void (*btf_trace_regmap_async_complete_done)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_start)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_io_complete)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_bulk_read)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_bulk_write)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_cache_bypass)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_cache_only)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_hw_read_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_read_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_reg_read)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read_cache)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_write)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regulator_bypass_disable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_disable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_enable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_enable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_disable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_disable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable_delay)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_set_voltage)(void *, const char *, int, int);\n\ntypedef void (*btf_trace_regulator_set_voltage_complete)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_rpc__auth_tooweak)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__bad_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__garbage_args)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__proc_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__stale_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__unparsable)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_callhdr)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_verifier)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_buf_alloc)(void *, const struct rpc_task *, int);\n\ntypedef void (*btf_trace_rpc_call_rpcerror)(void *, const struct rpc_task *, int, int);\n\ntypedef void (*btf_trace_rpc_call_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_clnt_clone_err)(void *, const struct rpc_clnt *, int);\n\ntypedef void (*btf_trace_rpc_clnt_free)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_killall)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_new)(void *, const struct rpc_clnt *, const struct rpc_xprt *, const struct rpc_create_args *);\n\ntypedef void (*btf_trace_rpc_clnt_new_err)(void *, const char *, const char *, int);\n\ntypedef void (*btf_trace_rpc_clnt_release)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt_err)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_shutdown)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_connect_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_request)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_retry_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_socket_close)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_connect)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_error)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_nospace)(void *, const struct rpc_rqst *, const struct sock_xprt *);\n\ntypedef void (*btf_trace_rpc_socket_reset_connection)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_shutdown)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_state_change)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_stats_latency)(void *, const struct rpc_task *, ktime_t, ktime_t, ktime_t);\n\ntypedef void (*btf_trace_rpc_task_begin)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_call_done)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_complete)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_end)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_run_action)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_signalled)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sleep)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_task_sync_sleep)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sync_wake)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_timeout)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_wakeup)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_timeout_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_tls_not_started)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_tls_unavailable)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_xdr_alignment)(void *, const struct xdr_stream *, size_t, unsigned int);\n\ntypedef void (*btf_trace_rpc_xdr_overflow)(void *, const struct xdr_stream *, size_t);\n\ntypedef void (*btf_trace_rpc_xdr_recvfrom)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_reply_pages)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_sendto)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpcb_bind_version_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_getport)(void *, const struct rpc_clnt *, const struct rpc_task *, unsigned int);\n\ntypedef void (*btf_trace_rpcb_prog_unavail_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_register)(void *, u32, u32, const char *, const char *);\n\ntypedef void (*btf_trace_rpcb_setport)(void *, const struct rpc_task *, int, short unsigned int);\n\ntypedef void (*btf_trace_rpcb_timeout_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unreachable_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unrecognized_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unregister)(void *, u32, u32, const char *);\n\ntypedef void (*btf_trace_rpm_idle)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_resume)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_return_int)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_rpm_status)(void *, struct device *, enum rpm_status);\n\ntypedef void (*btf_trace_rpm_suspend)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_usage)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int);\n\ntypedef void (*btf_trace_rtc_alarm_irq_enable)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_freq)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_state)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_read_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_read_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_set_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_timer_dequeue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_enqueue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_fired)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sbi_call)(void *, int, int);\n\ntypedef void (*btf_trace_sbi_return)(void *, int, long int, long int);\n\ntypedef void (*btf_trace_sched_compute_energy_tp)(void *, struct task_struct *, int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_sched_cpu_capacity_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_sched_entry_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_exit_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_ext_bypass_lb)(void *, __u32, __u32, __u32, __u32, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_sched_ext_dump)(void *, const char *);\n\ntypedef void (*btf_trace_sched_ext_event)(void *, const char *, __s64);\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_end)(void *, struct kthread_work *, kthread_work_func_t);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_start)(void *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_kthread_work_queue_work)(void *, struct kthread_worker *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_move_numa)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_overutilized_tp)(void *, struct root_domain *, bool);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_prepare_exec)(void *, struct task_struct *, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_set_need_resched_tp)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_skip_cpuset_numa)(void *, struct task_struct *, nodemask_t *);\n\ntypedef void (*btf_trace_sched_skip_vma_numa)(void *, struct mm_struct *, struct vm_area_struct *, enum numa_vmaskip_reason);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stick_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_swap_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *, unsigned int);\n\ntypedef void (*btf_trace_sched_update_nr_running_tp)(void *, struct rq *, int);\n\ntypedef void (*btf_trace_sched_util_est_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_sched_util_est_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\ntypedef void (*btf_trace_selinux_audited)(void *, struct selinux_audit_data *, char *, char *, const char *);\n\ntypedef void (*btf_trace_set_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sk_data_ready)(void *, const struct sock *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_smbus_read)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int);\n\ntypedef void (*btf_trace_smbus_reply)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *, int);\n\ntypedef void (*btf_trace_smbus_result)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, int);\n\ntypedef void (*btf_trace_smbus_write)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *);\n\ntypedef void (*btf_trace_snd_soc_bias_level_done)(void *, struct snd_soc_dapm_context *, int);\n\ntypedef void (*btf_trace_snd_soc_bias_level_start)(void *, struct snd_soc_dapm_context *, int);\n\ntypedef void (*btf_trace_snd_soc_dapm_connected)(void *, int, int);\n\ntypedef void (*btf_trace_snd_soc_dapm_done)(void *, struct snd_soc_card *, int);\n\ntypedef void (*btf_trace_snd_soc_dapm_path)(void *, struct snd_soc_dapm_widget *, enum snd_soc_dapm_direction, struct snd_soc_dapm_path *);\n\ntypedef void (*btf_trace_snd_soc_dapm_start)(void *, struct snd_soc_card *, int);\n\ntypedef void (*btf_trace_snd_soc_dapm_walk_done)(void *, struct snd_soc_card *);\n\ntypedef void (*btf_trace_snd_soc_dapm_widget_event_done)(void *, struct snd_soc_dapm_widget *, int);\n\ntypedef void (*btf_trace_snd_soc_dapm_widget_event_start)(void *, struct snd_soc_dapm_widget *, int);\n\ntypedef void (*btf_trace_snd_soc_dapm_widget_power)(void *, struct snd_soc_dapm_widget *, int);\n\ntypedef void (*btf_trace_snd_soc_jack_irq)(void *, const char *);\n\ntypedef void (*btf_trace_snd_soc_jack_notify)(void *, struct snd_soc_jack *, int);\n\ntypedef void (*btf_trace_snd_soc_jack_report)(void *, struct snd_soc_jack *, int, int);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_recv_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_sock_send_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\ntypedef void (*btf_trace_spi_controller_busy)(void *, struct spi_controller *);\n\ntypedef void (*btf_trace_spi_controller_idle)(void *, struct spi_controller *);\n\ntypedef void (*btf_trace_spi_mem_start_op)(void *, struct spi_mem *, const struct spi_mem_op *);\n\ntypedef void (*btf_trace_spi_mem_stop_op)(void *, struct spi_mem *, const struct spi_mem_op *);\n\ntypedef void (*btf_trace_spi_message_done)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_message_start)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_message_submit)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_set_cs)(void *, struct spi_device *, bool);\n\ntypedef void (*btf_trace_spi_setup)(void *, struct spi_device *, int);\n\ntypedef void (*btf_trace_spi_transfer_start)(void *, struct spi_message *, struct spi_transfer *);\n\ntypedef void (*btf_trace_spi_transfer_stop)(void *, struct spi_message *, struct spi_transfer *);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_svc_alloc_arg_err)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_svc_authenticate)(void *, const struct svc_rqst *, enum svc_auth_status);\n\ntypedef void (*btf_trace_svc_defer)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_defer_drop)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_queue)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_recv)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_drop)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_noregister)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_pool_thread_noidle)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_running)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_wake)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_process)(void *, const struct svc_rqst *, const char *);\n\ntypedef void (*btf_trace_svc_register)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_replace_page_err)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_send)(void *, const struct svc_rqst *, int);\n\ntypedef void (*btf_trace_svc_stats_latency)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_tls_not_started)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_start)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_timed_out)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_unavailable)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_upcall)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_unregister)(void *, const char *, const u32, int);\n\ntypedef void (*btf_trace_svc_xdr_recvfrom)(void *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xdr_sendto)(void *, __be32, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xprt_accept)(void *, const struct svc_xprt *, const char *);\n\ntypedef void (*btf_trace_svc_xprt_close)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_create_err)(void *, const char *, const char *, struct sockaddr *, size_t, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_dequeue)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_xprt_detach)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_enqueue)(void *, const struct svc_xprt *, long unsigned int);\n\ntypedef void (*btf_trace_svc_xprt_free)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_no_write_space)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svcsock_accept_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_data_ready)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_free)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_getpeername_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_marker)(void *, const struct svc_xprt *, __be32);\n\ntypedef void (*btf_trace_svcsock_new)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_tcp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_eagain)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_short)(void *, const struct svc_xprt *, u32, u32);\n\ntypedef void (*btf_trace_svcsock_tcp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_state)(void *, const struct svc_xprt *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_udp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_write_space)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_swiotlb_bounced)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_task_prctl_unknown)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef void (*btf_trace_tasklet_entry)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tasklet_exit)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tcp_ao_handshake_failure)(void *, const struct sock *, const struct sk_buff *, const __u8, const __u8, const __u8);\n\ntypedef void (*btf_trace_tcp_bad_csum)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_cong_state_set)(void *, struct sock *, const u8);\n\ntypedef void (*btf_trace_tcp_cwnd_reduction_tp)(void *, const struct sock *, int, int, int);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_hash_ao_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_bad_header)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_mismatch)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_unexpected)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *, const enum sk_rst_reason);\n\ntypedef void (*btf_trace_tcp_sendmsg_locked)(void *, const struct sock *, const struct msghdr *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_thermal_power_cpu_get_power_simple)(void *, int, u32);\n\ntypedef void (*btf_trace_thermal_power_cpu_limit)(void *, const struct cpumask *, unsigned int, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_power_devfreq_get_power)(void *, struct thermal_cooling_device *, struct devfreq_dev_status *, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_power_devfreq_limit)(void *, struct thermal_cooling_device *, long unsigned int, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_temperature)(void *, struct thermal_zone_device *);\n\ntypedef void (*btf_trace_thermal_zone_trip)(void *, struct thermal_zone_device *, int, enum thermal_trip_type);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_timer_base_idle)(void *, bool, unsigned int);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_tls_alert_recv)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_alert_send)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_contenttype)(void *, const struct sock *, unsigned char);\n\ntypedef void (*btf_trace_tmigr_connect_child_parent)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_connect_cpu_parent)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_active)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_available)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_unavailable)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_group_set)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_active)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_inactive)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_handle_remote)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_handle_remote_cpu)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_update_events)(void *, struct tmigr_group *, struct tmigr_group *, union tmigr_state, union tmigr_state, u64);\n\ntypedef void (*btf_trace_track_foreign_dirty)(void *, struct folio *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_usb_alloc_dev)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_usb_ep_alloc_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_clear_halt)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_dequeue)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_disable)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_enable)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_fifo_flush)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_fifo_status)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_free_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_queue)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_set_halt)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_set_maxpacket_limit)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_set_wedge)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_gadget_activate)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_clear_selfpowered)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_connect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_deactivate)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_disconnect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_frame_number)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_giveback_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_remote_wakeup)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_selfpowered)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_state)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_connect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_disconnect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_draw)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_wakeup)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_set_device_state)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_watchdog_ping)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_set_timeout)(void *, struct watchdog_device *, unsigned int, int);\n\ntypedef void (*btf_trace_watchdog_start)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_stop)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_dirty_folio)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, long unsigned int, int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int, struct xdp_cpumap_stats *);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xhci_add_endpoint)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctx)(void *, struct xhci_hcd *, struct xhci_container_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_stream_info_ctx)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_alloc_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_dbc_alloc_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_free_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_gadget_ep_queue)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_giveback_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_queue_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbg_address)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_cancel_urb)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_context_change)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_init)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_quirks)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_reset_ep)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_ring_expansion)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_discover_or_reset_device)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_get_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_cmd_addr_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_config_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_disable_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_stream)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_handle_cmd_stop_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_command)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_hub_status_data)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_inc_deq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_inc_enq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_portsc_writel)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_queue_trb)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_ring_alloc)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_ep_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_ring_expansion)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_free)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_host_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_setup_addressable_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_stop_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_urb_dequeue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_enqueue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_giveback)(void *, struct urb *);\n\ntypedef void (*btf_trace_xprt_connect)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_create)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_destroy)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_auto)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_done)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_force)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_get_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_lookup_rqst)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_ping)(void *, const struct rpc_xprt *, int);\n\ntypedef void (*btf_trace_xprt_put_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_reserve_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_retransmit)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_timer)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_transmit)(void *, const struct rpc_rqst *, int);\n\ntypedef void (*btf_trace_xs_data_ready)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xs_stream_read_data)(void *, struct rpc_xprt *, ssize_t, size_t);\n\ntypedef void (*btf_trace_xs_stream_read_request)(void *, struct sock_xprt *);\n\ntypedef struct mtd_info *cfi_cmdset_fn_t(struct map_info *, int);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef void (*companion_fn)(struct pci_dev *, struct usb_hcd *, struct pci_dev *, struct usb_hcd *);\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\ntypedef int (*copy_fn_t)(void *, const void *, u32, struct task_struct *);\n\ntypedef long unsigned int (*count_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int devlink_chunk_fill_t(void *, u8 *, u32, u64, struct netlink_ext_ack *);\n\ntypedef int devlink_nl_dump_one_func_t(struct sk_buff *, struct devlink *, struct netlink_callback *, int);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\ntypedef efi_status_t (*efi_exit_boot_map_processing)(struct efi_boot_memmap *, void *);\n\ntypedef int (*efi_memattr_perm_setter)(struct mm_struct *, efi_memory_desc_t *, bool);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\ntypedef void ext4_update_sb_callback(struct ext4_sb_info *, struct ext4_super_block *, const void *);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, struct mm_struct *);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef bool (*hid_usage_cmp_t)(struct hid_usage *, unsigned int, unsigned int);\n\ntypedef size_t (*huf_compress_f)(void *, size_t, const void *, size_t, unsigned int, unsigned int, void *, size_t, HUF_CElt *, HUF_repeat *, int);\n\ntypedef const struct iio_mount_matrix *iio_get_mount_matrix_t(const struct iio_dev *, const struct iio_chan_spec *);\n\ntypedef u32 inet6_ehashfn_t(const struct net *, const struct in6_addr *, const u16, const struct in6_addr *, const __be16);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef initcall_t initcall_entry_t;\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef int (*ioctl_fn)(struct file *, struct autofs_sb_info *, struct autofs_dev_ioctl *);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *, const struct inet6_skb_parm *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef void (*jump_kernel_func)(long unsigned int, long unsigned int);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef void (*mapped_f)(struct perf_event *, struct mm_struct *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*nlm_host_match_fn_t)(void *, struct nlm_host *);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef struct gpio_desc * (*of_find_gpio_quirk)(struct device_node *, const char *, unsigned int, enum of_gpio_flags *);\n\ntypedef void (*of_init_fn_1)(struct device_node *);\n\ntypedef int (*of_init_fn_1_ret)(struct device_node *);\n\ntypedef int (*of_init_fn_2)(struct device_node *, struct device_node *);\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef int (*pcie_callback_t)(struct pcie_device *);\n\ntypedef int (*pcm_transfer_f)(struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\ntypedef int (*pcm_copy_f)(struct snd_pcm_substream *, snd_pcm_uframes_t, void *, snd_pcm_uframes_t, snd_pcm_uframes_t, pcm_transfer_f, bool);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\ntypedef int perf_snapshot_branch_stack_t(struct perf_branch_entry *, unsigned int);\n\ntypedef int (*platform_irq_probe_t)(struct platform_device *, struct device_node *);\n\ntypedef int (*pm_callback_t)(struct device *);\n\ntypedef struct rt6_info * (*pol_lookup_t)(struct net *, struct fib6_table *, struct flowi6 *, const struct sk_buff *, int);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*reservedmem_of_init_fn)(struct reserved_mem *);\n\ntypedef bool (*ring_buffer_cond_fn)(void *);\n\ntypedef void (*rpc_action)(struct rpc_task *);\n\ntypedef void (*rtl_generic_fct)(struct rtl8169_private *);\n\ntypedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *, struct phy_device *);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef long unsigned int (*scan_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef long int (*syscall_t)(const struct pt_regs *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef int (*trace_user_buf_copy)(char *, const char *, size_t, void *);\n\ntypedef struct sk_buff * (*udp_gro_receive_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*uprobe_write_verify_t)(struct page *, long unsigned int, uprobe_opcode_t *, int, void *);\n\ntypedef int (*varsize_frob_t)(struct map_info *, struct flchip *, long unsigned int, int, void *);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);\n\ntypedef struct rpc_xprt * (*xprt_switch_find_xprt_t)(struct rpc_xprt_switch *, const struct rpc_xprt *);\n\ntypedef ZSTD_sequenceProducer_F zstd_sequence_producer_f;\n\nstruct nf_bridge_frag_data;\n\nstruct ftrace_regs;\n\nstruct bpf_iter;\n\nstruct fscrypt_inode_info;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern void __attribute__((address_space(1))) *bpf_arena_alloc_pages(void *p__map, void __attribute__((address_space(1))) *addr__ign, u32 page_cnt, int node_id, u64 flags) __weak __ksym;\nextern void bpf_arena_free_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern int bpf_arena_reserve_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern struct cgroup *bpf_cgroup_from_id(u64 cgid) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_task_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_dynptr_adjust(const struct bpf_dynptr *p, u64 start, u64 end) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_copy(struct bpf_dynptr *dst_ptr, u64 dst_off, struct bpf_dynptr *src_ptr, u64 src_off, u64 size) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb(struct __sk_buff *s, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb_meta(struct __sk_buff *skb_, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_xdp(struct xdp_md *x, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_dynptr_memset(struct bpf_dynptr *p, u64 offset, u64 size, u8 val) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern void *bpf_dynptr_slice(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern void *bpf_dynptr_slice_rdwr(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern struct kmem_cache *bpf_get_kmem_cache(u64 addr) __weak __ksym;\nextern struct mem_cgroup *bpf_get_mem_cgroup(struct cgroup_subsys_state *css) __weak __ksym;\nextern struct mem_cgroup *bpf_get_root_mem_cgroup(void) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern int bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it, struct task_struct *task, u64 addr) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern struct bpf_key *bpf_lookup_system_key(u64 id) __weak __ksym;\nextern struct bpf_key *bpf_lookup_user_key(s32 serial, u64 flags) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern void bpf_mem_cgroup_flush_stats(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_memory_events(struct mem_cgroup *memcg, enum memcg_memory_event event) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_page_state(struct mem_cgroup *memcg, int idx) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_usage(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_vm_events(struct mem_cgroup *memcg, enum vm_event_item event) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_percpu_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern int bpf_probe_read_kernel_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_kernel_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern void bpf_put_mem_cgroup(struct mem_cgroup *memcg) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_send_signal_task(struct task_struct *task, int sig, enum pid_type type, u64 value) __weak __ksym;\nextern __u64 *bpf_session_cookie(void *ctx) __weak __ksym;\nextern bool bpf_session_is_return(void *ctx) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_sock_ops_enable_tx_tstamp(struct bpf_sock_ops_kern *skops, u64 flags) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern void bpf_throw(u64 cookie) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern struct xfrm_state *bpf_xdp_get_xfrm_state(struct xdp_md *ctx, struct bpf_xfrm_state_opts *opts, u32 opts__sz) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void bpf_xdp_xfrm_state_release(struct xfrm_state *x) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __weak __ksym;\nextern void scx_bpf_destroy_dsq(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_insert___v2(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local(u64 dsq_id) __weak __ksym;\nextern bool scx_bpf_dsq_move_vtime(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __weak __ksym;\nextern struct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern void scx_bpf_exit_bstr(s64 exit_code, char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern void scx_bpf_kick_cpu(s32 cpu, u64 flags) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern s32 scx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags, const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __weak __ksym;\nextern bool scx_bpf_sub_dispatch(u64 cgroup_id) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime) __weak __ksym;\nextern bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n#pragma clang diagnostic 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00arch/x86/vmlinux-v6.9-rc6-g618a9db0158b.h\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000100600\x000001751\x000001751\x0000012645156\x0000000000001\x000015527\x000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00ustar \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tAC97_TUNE_DEFAULT = -1,\n\tAC97_TUNE_NONE = 0,\n\tAC97_TUNE_HP_ONLY = 1,\n\tAC97_TUNE_SWAP_HP = 2,\n\tAC97_TUNE_SWAP_SURROUND = 3,\n\tAC97_TUNE_AD_SHARING = 4,\n\tAC97_TUNE_ALC_JACK = 5,\n\tAC97_TUNE_INV_EAPD = 6,\n\tAC97_TUNE_MUTE_LED = 7,\n\tAC97_TUNE_HP_MUTE_LED = 8,\n};\n\nenum {\n\tACOMP_WALK_SLEEP = 1,\n\tACOMP_WALK_SRC_LINEAR = 2,\n\tACOMP_WALK_DST_LINEAR = 4,\n};\n\nenum {\n\tACPI_BATTERY_ALARM_PRESENT = 0,\n\tACPI_BATTERY_XINFO_PRESENT = 1,\n\tACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY = 2,\n\tACPI_BATTERY_QUIRK_THINKPAD_MAH = 3,\n\tACPI_BATTERY_QUIRK_DEGRADED_FULL_CHARGE = 4,\n};\n\nenum {\n\tACPI_BUTTON_LID_INIT_IGNORE = 0,\n\tACPI_BUTTON_LID_INIT_OPEN = 1,\n\tACPI_BUTTON_LID_INIT_METHOD = 2,\n\tACPI_BUTTON_LID_INIT_DISABLED = 3,\n};\n\nenum {\n\tACPI_GENL_ATTR_UNSPEC = 0,\n\tACPI_GENL_ATTR_EVENT = 1,\n\t__ACPI_GENL_ATTR_MAX = 2,\n};\n\nenum {\n\tACPI_GENL_CMD_UNSPEC = 0,\n\tACPI_GENL_CMD_EVENT = 1,\n\t__ACPI_GENL_CMD_MAX = 2,\n};\n\nenum {\n\tACPI_REFCLASS_LOCAL = 0,\n\tACPI_REFCLASS_ARG = 1,\n\tACPI_REFCLASS_REFOF = 2,\n\tACPI_REFCLASS_INDEX = 3,\n\tACPI_REFCLASS_TABLE = 4,\n\tACPI_REFCLASS_NAME = 5,\n\tACPI_REFCLASS_DEBUG = 6,\n\tACPI_REFCLASS_MAX = 6,\n};\n\nenum {\n\tACPI_RSC_INITGET = 0,\n\tACPI_RSC_INITSET = 1,\n\tACPI_RSC_FLAGINIT = 2,\n\tACPI_RSC_1BITFLAG = 3,\n\tACPI_RSC_2BITFLAG = 4,\n\tACPI_RSC_3BITFLAG = 5,\n\tACPI_RSC_6BITFLAG = 6,\n\tACPI_RSC_ADDRESS = 7,\n\tACPI_RSC_BITMASK = 8,\n\tACPI_RSC_BITMASK16 = 9,\n\tACPI_RSC_COUNT = 10,\n\tACPI_RSC_COUNT16 = 11,\n\tACPI_RSC_COUNT_GPIO_PIN = 12,\n\tACPI_RSC_COUNT_GPIO_RES = 13,\n\tACPI_RSC_COUNT_GPIO_VEN = 14,\n\tACPI_RSC_COUNT_SERIAL_RES = 15,\n\tACPI_RSC_COUNT_SERIAL_VEN = 16,\n\tACPI_RSC_DATA8 = 17,\n\tACPI_RSC_EXIT_EQ = 18,\n\tACPI_RSC_EXIT_LE = 19,\n\tACPI_RSC_EXIT_NE = 20,\n\tACPI_RSC_LENGTH = 21,\n\tACPI_RSC_MOVE_GPIO_PIN = 22,\n\tACPI_RSC_MOVE_GPIO_RES = 23,\n\tACPI_RSC_MOVE_SERIAL_RES = 24,\n\tACPI_RSC_MOVE_SERIAL_VEN = 25,\n\tACPI_RSC_MOVE8 = 26,\n\tACPI_RSC_MOVE16 = 27,\n\tACPI_RSC_MOVE32 = 28,\n\tACPI_RSC_MOVE64 = 29,\n\tACPI_RSC_SET8 = 30,\n\tACPI_RSC_SOURCE = 31,\n\tACPI_RSC_SOURCEX = 32,\n};\n\nenum {\n\tACPI_RSD_TITLE = 0,\n\tACPI_RSD_1BITFLAG = 1,\n\tACPI_RSD_2BITFLAG = 2,\n\tACPI_RSD_3BITFLAG = 3,\n\tACPI_RSD_6BITFLAG = 4,\n\tACPI_RSD_ADDRESS = 5,\n\tACPI_RSD_DWORDLIST = 6,\n\tACPI_RSD_LITERAL = 7,\n\tACPI_RSD_LONGLIST = 8,\n\tACPI_RSD_SHORTLIST = 9,\n\tACPI_RSD_SHORTLISTX = 10,\n\tACPI_RSD_SOURCE = 11,\n\tACPI_RSD_STRING = 12,\n\tACPI_RSD_UINT8 = 13,\n\tACPI_RSD_UINT16 = 14,\n\tACPI_RSD_UINT32 = 15,\n\tACPI_RSD_UINT64 = 16,\n\tACPI_RSD_WORDLIST = 17,\n\tACPI_RSD_LABEL = 18,\n\tACPI_RSD_SOURCE_LABEL = 19,\n};\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAC_GRP_AUDIO_FUNCTION = 1,\n\tAC_GRP_MODEM_FUNCTION = 2,\n};\n\nenum {\n\tAC_JACK_LINE_OUT = 0,\n\tAC_JACK_SPEAKER = 1,\n\tAC_JACK_HP_OUT = 2,\n\tAC_JACK_CD = 3,\n\tAC_JACK_SPDIF_OUT = 4,\n\tAC_JACK_DIG_OTHER_OUT = 5,\n\tAC_JACK_MODEM_LINE_SIDE = 6,\n\tAC_JACK_MODEM_HAND_SIDE = 7,\n\tAC_JACK_LINE_IN = 8,\n\tAC_JACK_AUX = 9,\n\tAC_JACK_MIC_IN = 10,\n\tAC_JACK_TELEPHONY = 11,\n\tAC_JACK_SPDIF_IN = 12,\n\tAC_JACK_DIG_OTHER_IN = 13,\n\tAC_JACK_OTHER = 15,\n};\n\nenum {\n\tAC_JACK_LOC_EXTERNAL = 0,\n\tAC_JACK_LOC_INTERNAL = 16,\n\tAC_JACK_LOC_SEPARATE = 32,\n\tAC_JACK_LOC_OTHER = 48,\n};\n\nenum {\n\tAC_JACK_LOC_NONE = 0,\n\tAC_JACK_LOC_REAR = 1,\n\tAC_JACK_LOC_FRONT = 2,\n\tAC_JACK_LOC_LEFT = 3,\n\tAC_JACK_LOC_RIGHT = 4,\n\tAC_JACK_LOC_TOP = 5,\n\tAC_JACK_LOC_BOTTOM = 6,\n};\n\nenum {\n\tAC_JACK_LOC_REAR_PANEL = 7,\n\tAC_JACK_LOC_DRIVE_BAY = 8,\n\tAC_JACK_LOC_RISER = 23,\n\tAC_JACK_LOC_HDMI = 24,\n\tAC_JACK_LOC_ATAPI = 25,\n\tAC_JACK_LOC_MOBILE_IN = 55,\n\tAC_JACK_LOC_MOBILE_OUT = 56,\n};\n\nenum {\n\tAC_JACK_PORT_COMPLEX = 0,\n\tAC_JACK_PORT_NONE = 1,\n\tAC_JACK_PORT_FIXED = 2,\n\tAC_JACK_PORT_BOTH = 3,\n};\n\nenum {\n\tAC_WID_AUD_OUT = 0,\n\tAC_WID_AUD_IN = 1,\n\tAC_WID_AUD_MIX = 2,\n\tAC_WID_AUD_SEL = 3,\n\tAC_WID_PIN = 4,\n\tAC_WID_POWER = 5,\n\tAC_WID_VOL_KNB = 6,\n\tAC_WID_BEEP = 7,\n\tAC_WID_VENDOR = 15,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DMPS = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_CPD = 1048576,\n\tPORT_CMD_MPSP = 524288,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_CMD_CAP = 8126464,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_SUSPEND_PHYS = 33554432,\n\tAHCI_HFLAG_NO_SXS = 67108864,\n\tAHCI_HFLAG_43BIT_ONLY = 134217728,\n\tAHCI_HFLAG_INTEL_PCS_QUIRK = 268435456,\n\tAHCI_HFLAG_ATAPI_DMA_QUIRK = 536870912,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 15,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum {\n\tALC260_FIXUP_HP_DC5750 = 0,\n\tALC260_FIXUP_HP_PIN_0F = 1,\n\tALC260_FIXUP_COEF = 2,\n\tALC260_FIXUP_GPIO1 = 3,\n\tALC260_FIXUP_GPIO1_TOGGLE = 4,\n\tALC260_FIXUP_REPLACER = 5,\n\tALC260_FIXUP_HP_B1900 = 6,\n\tALC260_FIXUP_KN1 = 7,\n\tALC260_FIXUP_FSC_S7020 = 8,\n\tALC260_FIXUP_FSC_S7020_JWSE = 9,\n\tALC260_FIXUP_VAIO_PINS = 10,\n};\n\nenum {\n\tALC262_FIXUP_FSC_H270 = 0,\n\tALC262_FIXUP_FSC_S7110 = 1,\n\tALC262_FIXUP_HP_Z200 = 2,\n\tALC262_FIXUP_TYAN = 3,\n\tALC262_FIXUP_LENOVO_3000 = 4,\n\tALC262_FIXUP_BENQ = 5,\n\tALC262_FIXUP_BENQ_T31 = 6,\n\tALC262_FIXUP_INV_DMIC = 7,\n\tALC262_FIXUP_INTEL_BAYLEYBAY = 8,\n};\n\nenum {\n\tALC268_FIXUP_INV_DMIC = 0,\n\tALC268_FIXUP_HP_EAPD = 1,\n\tALC268_FIXUP_SPDIF = 2,\n};\n\nenum {\n\tALC269_FIXUP_GPIO2 = 0,\n\tALC269_FIXUP_SONY_VAIO = 1,\n\tALC275_FIXUP_SONY_VAIO_GPIO2 = 2,\n\tALC269_FIXUP_DELL_M101Z = 3,\n\tALC269_FIXUP_SKU_IGNORE = 4,\n\tALC269_FIXUP_ASUS_G73JW = 5,\n\tALC269_FIXUP_ASUS_N7601ZM_PINS = 6,\n\tALC269_FIXUP_ASUS_N7601ZM = 7,\n\tALC269_FIXUP_LENOVO_EAPD = 8,\n\tALC275_FIXUP_SONY_HWEQ = 9,\n\tALC275_FIXUP_SONY_DISABLE_AAMIX = 10,\n\tALC271_FIXUP_DMIC = 11,\n\tALC269_FIXUP_PCM_44K = 12,\n\tALC269_FIXUP_STEREO_DMIC = 13,\n\tALC269_FIXUP_HEADSET_MIC = 14,\n\tALC269_FIXUP_QUANTA_MUTE = 15,\n\tALC269_FIXUP_LIFEBOOK = 16,\n\tALC269_FIXUP_LIFEBOOK_EXTMIC = 17,\n\tALC269_FIXUP_LIFEBOOK_HP_PIN = 18,\n\tALC269_FIXUP_LIFEBOOK_NO_HP_TO_LINEOUT = 19,\n\tALC255_FIXUP_LIFEBOOK_U7x7_HEADSET_MIC = 20,\n\tALC269_FIXUP_AMIC = 21,\n\tALC269_FIXUP_DMIC = 22,\n\tALC269VB_FIXUP_AMIC = 23,\n\tALC269VB_FIXUP_DMIC = 24,\n\tALC269_FIXUP_HP_MUTE_LED = 25,\n\tALC269_FIXUP_HP_MUTE_LED_MIC1 = 26,\n\tALC269_FIXUP_HP_MUTE_LED_MIC2 = 27,\n\tALC269_FIXUP_HP_MUTE_LED_MIC3 = 28,\n\tALC269_FIXUP_HP_GPIO_LED = 29,\n\tALC269_FIXUP_HP_GPIO_MIC1_LED = 30,\n\tALC269_FIXUP_HP_LINE1_MIC1_LED = 31,\n\tALC269_FIXUP_INV_DMIC = 32,\n\tALC269_FIXUP_LENOVO_DOCK = 33,\n\tALC269_FIXUP_LENOVO_DOCK_LIMIT_BOOST = 34,\n\tALC269_FIXUP_NO_SHUTUP = 35,\n\tALC286_FIXUP_SONY_MIC_NO_PRESENCE = 36,\n\tALC269_FIXUP_PINCFG_NO_HP_TO_LINEOUT = 37,\n\tALC269_FIXUP_DELL1_MIC_NO_PRESENCE = 38,\n\tALC269_FIXUP_DELL1_LIMIT_INT_MIC_BOOST = 39,\n\tALC269_FIXUP_DELL2_MIC_NO_PRESENCE = 40,\n\tALC269_FIXUP_DELL3_MIC_NO_PRESENCE = 41,\n\tALC269_FIXUP_DELL4_MIC_NO_PRESENCE = 42,\n\tALC269_FIXUP_DELL4_MIC_NO_PRESENCE_QUIET = 43,\n\tALC269_FIXUP_HEADSET_MODE = 44,\n\tALC269_FIXUP_HEADSET_MODE_NO_HP_MIC = 45,\n\tALC269_FIXUP_ASPIRE_HEADSET_MIC = 46,\n\tALC269_FIXUP_ASUS_X101_FUNC = 47,\n\tALC269_FIXUP_ASUS_X101_VERB = 48,\n\tALC269_FIXUP_ASUS_X101 = 49,\n\tALC271_FIXUP_AMIC_MIC2 = 50,\n\tALC271_FIXUP_HP_GATE_MIC_JACK = 51,\n\tALC271_FIXUP_HP_GATE_MIC_JACK_E1_572 = 52,\n\tALC269_FIXUP_ACER_AC700 = 53,\n\tALC269_FIXUP_LIMIT_INT_MIC_BOOST = 54,\n\tALC269VB_FIXUP_ASUS_ZENBOOK = 55,\n\tALC269VB_FIXUP_ASUS_ZENBOOK_UX31A = 56,\n\tALC269VB_FIXUP_ASUS_MIC_NO_PRESENCE = 57,\n\tALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED = 58,\n\tALC269VB_FIXUP_ORDISSIMO_EVE2 = 59,\n\tALC283_FIXUP_CHROME_BOOK = 60,\n\tALC283_FIXUP_SENSE_COMBO_JACK = 61,\n\tALC282_FIXUP_ASUS_TX300 = 62,\n\tALC283_FIXUP_INT_MIC = 63,\n\tALC290_FIXUP_MONO_SPEAKERS = 64,\n\tALC290_FIXUP_MONO_SPEAKERS_HSJACK = 65,\n\tALC290_FIXUP_SUBWOOFER = 66,\n\tALC290_FIXUP_SUBWOOFER_HSJACK = 67,\n\tALC295_FIXUP_HP_MUTE_LED_COEFBIT11 = 68,\n\tALC269_FIXUP_THINKPAD_ACPI = 69,\n\tALC269_FIXUP_LENOVO_XPAD_ACPI = 70,\n\tALC269_FIXUP_DMIC_THINKPAD_ACPI = 71,\n\tALC269VB_FIXUP_INFINIX_ZERO_BOOK_13 = 72,\n\tALC269VC_FIXUP_INFINIX_Y4_MAX = 73,\n\tALC269VB_FIXUP_CHUWI_COREBOOK_XPRO = 74,\n\tALC255_FIXUP_ACER_MIC_NO_PRESENCE = 75,\n\tALC255_FIXUP_ASUS_MIC_NO_PRESENCE = 76,\n\tALC255_FIXUP_DELL1_MIC_NO_PRESENCE = 77,\n\tALC255_FIXUP_DELL1_LIMIT_INT_MIC_BOOST = 78,\n\tALC255_FIXUP_DELL2_MIC_NO_PRESENCE = 79,\n\tALC255_FIXUP_HEADSET_MODE = 80,\n\tALC255_FIXUP_HEADSET_MODE_NO_HP_MIC = 81,\n\tALC293_FIXUP_DELL1_MIC_NO_PRESENCE = 82,\n\tALC292_FIXUP_TPT440_DOCK = 83,\n\tALC292_FIXUP_TPT440 = 84,\n\tALC283_FIXUP_HEADSET_MIC = 85,\n\tALC255_FIXUP_MIC_MUTE_LED = 86,\n\tALC282_FIXUP_ASPIRE_V5_PINS = 87,\n\tALC269VB_FIXUP_ASPIRE_E1_COEF = 88,\n\tALC280_FIXUP_HP_GPIO4 = 89,\n\tALC286_FIXUP_HP_GPIO_LED = 90,\n\tALC280_FIXUP_HP_GPIO2_MIC_HOTKEY = 91,\n\tALC280_FIXUP_HP_DOCK_PINS = 92,\n\tALC269_FIXUP_HP_DOCK_GPIO_MIC1_LED = 93,\n\tALC280_FIXUP_HP_9480M = 94,\n\tALC245_FIXUP_HP_X360_AMP = 95,\n\tALC285_FIXUP_HP_SPECTRE_X360_EB1 = 96,\n\tALC285_FIXUP_HP_SPECTRE_X360_DF1 = 97,\n\tALC285_FIXUP_HP_ENVY_X360 = 98,\n\tALC288_FIXUP_DELL_HEADSET_MODE = 99,\n\tALC288_FIXUP_DELL1_MIC_NO_PRESENCE = 100,\n\tALC288_FIXUP_DELL_XPS_13 = 101,\n\tALC288_FIXUP_DISABLE_AAMIX = 102,\n\tALC292_FIXUP_DELL_E7X_AAMIX = 103,\n\tALC292_FIXUP_DELL_E7X = 104,\n\tALC292_FIXUP_DISABLE_AAMIX = 105,\n\tALC293_FIXUP_DISABLE_AAMIX_MULTIJACK = 106,\n\tALC298_FIXUP_ALIENWARE_MIC_NO_PRESENCE = 107,\n\tALC298_FIXUP_DELL1_MIC_NO_PRESENCE = 108,\n\tALC298_FIXUP_DELL_AIO_MIC_NO_PRESENCE = 109,\n\tALC275_FIXUP_DELL_XPS = 110,\n\tALC293_FIXUP_LENOVO_SPK_NOISE = 111,\n\tALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY = 112,\n\tALC233_FIXUP_LENOVO_L2MH_LOW_ENLED = 113,\n\tALC255_FIXUP_DELL_SPK_NOISE = 114,\n\tALC225_FIXUP_DISABLE_MIC_VREF = 115,\n\tALC225_FIXUP_DELL1_MIC_NO_PRESENCE = 116,\n\tALC295_FIXUP_DISABLE_DAC3 = 117,\n\tALC285_FIXUP_SPEAKER2_TO_DAC1 = 118,\n\tALC285_FIXUP_ASUS_SPEAKER2_TO_DAC1 = 119,\n\tALC285_FIXUP_ASUS_HEADSET_MIC = 120,\n\tALC285_FIXUP_ASUS_SPI_REAR_SPEAKERS = 121,\n\tALC285_FIXUP_ASUS_I2C_SPEAKER2_TO_DAC1 = 122,\n\tALC285_FIXUP_ASUS_I2C_HEADSET_MIC = 123,\n\tALC280_FIXUP_HP_HEADSET_MIC = 124,\n\tALC221_FIXUP_HP_FRONT_MIC = 125,\n\tALC292_FIXUP_TPT460 = 126,\n\tALC298_FIXUP_SPK_VOLUME = 127,\n\tALC298_FIXUP_LENOVO_SPK_VOLUME = 128,\n\tALC256_FIXUP_DELL_INSPIRON_7559_SUBWOOFER = 129,\n\tALC269_FIXUP_ATIV_BOOK_8 = 130,\n\tALC221_FIXUP_HP_288PRO_MIC_NO_PRESENCE = 131,\n\tALC221_FIXUP_HP_MIC_NO_PRESENCE = 132,\n\tALC256_FIXUP_ASUS_HEADSET_MODE = 133,\n\tALC256_FIXUP_ASUS_MIC = 134,\n\tALC256_FIXUP_ASUS_AIO_GPIO2 = 135,\n\tALC233_FIXUP_ASUS_MIC_NO_PRESENCE = 136,\n\tALC233_FIXUP_EAPD_COEF_AND_MIC_NO_PRESENCE = 137,\n\tALC233_FIXUP_LENOVO_MULTI_CODECS = 138,\n\tALC233_FIXUP_ACER_HEADSET_MIC = 139,\n\tALC294_FIXUP_LENOVO_MIC_LOCATION = 140,\n\tALC225_FIXUP_DELL_WYSE_MIC_NO_PRESENCE = 141,\n\tALC225_FIXUP_S3_POP_NOISE = 142,\n\tALC700_FIXUP_INTEL_REFERENCE = 143,\n\tALC274_FIXUP_DELL_BIND_DACS = 144,\n\tALC274_FIXUP_DELL_AIO_LINEOUT_VERB = 145,\n\tALC298_FIXUP_TPT470_DOCK_FIX = 146,\n\tALC298_FIXUP_TPT470_DOCK = 147,\n\tALC255_FIXUP_DUMMY_LINEOUT_VERB = 148,\n\tALC255_FIXUP_DELL_HEADSET_MIC = 149,\n\tALC256_FIXUP_HUAWEI_MACH_WX9_PINS = 150,\n\tALC298_FIXUP_HUAWEI_MBX_STEREO = 151,\n\tALC295_FIXUP_HP_X360 = 152,\n\tALC221_FIXUP_HP_HEADSET_MIC = 153,\n\tALC285_FIXUP_LENOVO_HEADPHONE_NOISE = 154,\n\tALC295_FIXUP_HP_AUTO_MUTE = 155,\n\tALC286_FIXUP_ACER_AIO_MIC_NO_PRESENCE = 156,\n\tALC294_FIXUP_ASUS_MIC = 157,\n\tALC294_FIXUP_ASUS_HEADSET_MIC = 158,\n\tALC294_FIXUP_ASUS_I2C_HEADSET_MIC = 159,\n\tALC294_FIXUP_ASUS_SPI_HEADSET_MIC = 160,\n\tALC294_FIXUP_ASUS_SPK = 161,\n\tALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE = 162,\n\tALC285_FIXUP_LENOVO_PC_BEEP_IN_NOISE = 163,\n\tALC255_FIXUP_ACER_HEADSET_MIC = 164,\n\tALC295_FIXUP_CHROME_BOOK = 165,\n\tALC225_FIXUP_HEADSET_JACK = 166,\n\tALC225_FIXUP_DELL_WYSE_AIO_MIC_NO_PRESENCE = 167,\n\tALC225_FIXUP_WYSE_AUTO_MUTE = 168,\n\tALC225_FIXUP_WYSE_DISABLE_MIC_VREF = 169,\n\tALC286_FIXUP_ACER_AIO_HEADSET_MIC = 170,\n\tALC256_FIXUP_ASUS_HEADSET_MIC = 171,\n\tALC256_FIXUP_ASUS_MIC_NO_PRESENCE = 172,\n\tALC255_FIXUP_PREDATOR_SUBWOOFER = 173,\n\tALC299_FIXUP_PREDATOR_SPK = 174,\n\tALC256_FIXUP_MEDION_HEADSET_NO_PRESENCE = 175,\n\tALC289_FIXUP_DELL_SPK1 = 176,\n\tALC289_FIXUP_DELL_SPK2 = 177,\n\tALC289_FIXUP_DUAL_SPK = 178,\n\tALC289_FIXUP_RTK_AMP_DUAL_SPK = 179,\n\tALC294_FIXUP_SPK2_TO_DAC1 = 180,\n\tALC294_FIXUP_ASUS_DUAL_SPK = 181,\n\tALC285_FIXUP_THINKPAD_X1_GEN7 = 182,\n\tALC285_FIXUP_THINKPAD_HEADSET_JACK = 183,\n\tALC294_FIXUP_ASUS_ALLY = 184,\n\tALC294_FIXUP_ASUS_ALLY_PINS = 185,\n\tALC294_FIXUP_ASUS_ALLY_VERBS = 186,\n\tALC294_FIXUP_ASUS_ALLY_SPEAKER = 187,\n\tALC294_FIXUP_ASUS_HPE = 188,\n\tALC294_FIXUP_ASUS_COEF_1B = 189,\n\tALC294_FIXUP_ASUS_GX502_HP = 190,\n\tALC294_FIXUP_ASUS_GX502_PINS = 191,\n\tALC294_FIXUP_ASUS_GX502_VERBS = 192,\n\tALC294_FIXUP_ASUS_GU502_HP = 193,\n\tALC294_FIXUP_ASUS_GU502_PINS = 194,\n\tALC294_FIXUP_ASUS_GU502_VERBS = 195,\n\tALC294_FIXUP_ASUS_G513_PINS = 196,\n\tALC285_FIXUP_ASUS_G533Z_PINS = 197,\n\tALC285_FIXUP_HP_GPIO_LED = 198,\n\tALC285_FIXUP_HP_MUTE_LED = 199,\n\tALC285_FIXUP_HP_SPECTRE_X360_MUTE_LED = 200,\n\tALC245_FIXUP_HP_ENVY_X360_MUTE_LED = 201,\n\tALC285_FIXUP_HP_BEEP_MICMUTE_LED = 202,\n\tALC236_FIXUP_HP_MUTE_LED_COEFBIT2 = 203,\n\tALC236_FIXUP_HP_GPIO_LED = 204,\n\tALC236_FIXUP_HP_MUTE_LED = 205,\n\tALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF = 206,\n\tALC236_FIXUP_LENOVO_INV_DMIC = 207,\n\tALC298_FIXUP_SAMSUNG_AMP = 208,\n\tALC298_FIXUP_SAMSUNG_AMP_V2_2_AMPS = 209,\n\tALC298_FIXUP_SAMSUNG_AMP_V2_4_AMPS = 210,\n\tALC298_FIXUP_LG_GRAM_STYLE_14 = 211,\n\tALC298_FIXUP_SAMSUNG_HEADPHONE_VERY_QUIET = 212,\n\tALC256_FIXUP_SAMSUNG_HEADPHONE_VERY_QUIET = 213,\n\tALC295_FIXUP_ASUS_MIC_NO_PRESENCE = 214,\n\tALC269VC_FIXUP_ACER_VCOPPERBOX_PINS = 215,\n\tALC269VC_FIXUP_ACER_HEADSET_MIC = 216,\n\tALC269VC_FIXUP_ACER_MIC_NO_PRESENCE = 217,\n\tALC289_FIXUP_ASUS_GA401 = 218,\n\tALC289_FIXUP_ASUS_GA502 = 219,\n\tALC256_FIXUP_ACER_MIC_NO_PRESENCE = 220,\n\tALC285_FIXUP_HP_GPIO_AMP_INIT = 221,\n\tALC269_FIXUP_CZC_B20 = 222,\n\tALC269_FIXUP_CZC_TMI = 223,\n\tALC269_FIXUP_CZC_L101 = 224,\n\tALC269_FIXUP_LEMOTE_A1802 = 225,\n\tALC269_FIXUP_LEMOTE_A190X = 226,\n\tALC256_FIXUP_INTEL_NUC8_RUGGED = 227,\n\tALC233_FIXUP_INTEL_NUC8_DMIC = 228,\n\tALC233_FIXUP_INTEL_NUC8_BOOST = 229,\n\tALC256_FIXUP_INTEL_NUC10 = 230,\n\tALC255_FIXUP_XIAOMI_HEADSET_MIC = 231,\n\tALC274_FIXUP_HP_MIC = 232,\n\tALC274_FIXUP_HP_HEADSET_MIC = 233,\n\tALC274_FIXUP_HP_ENVY_GPIO = 234,\n\tALC274_FIXUP_ASUS_ZEN_AIO_27 = 235,\n\tALC256_FIXUP_ASUS_HPE = 236,\n\tALC285_FIXUP_THINKPAD_NO_BASS_SPK_HEADSET_JACK = 237,\n\tALC287_FIXUP_HP_GPIO_LED = 238,\n\tALC256_FIXUP_HP_HEADSET_MIC = 239,\n\tALC245_FIXUP_HP_GPIO_LED = 240,\n\tALC236_FIXUP_DELL_AIO_HEADSET_MIC = 241,\n\tALC282_FIXUP_ACER_DISABLE_LINEOUT = 242,\n\tALC255_FIXUP_ACER_LIMIT_INT_MIC_BOOST = 243,\n\tALC256_FIXUP_ACER_HEADSET_MIC = 244,\n\tALC285_FIXUP_IDEAPAD_S740_COEF = 245,\n\tALC285_FIXUP_HP_LIMIT_INT_MIC_BOOST = 246,\n\tALC295_FIXUP_ASUS_DACS = 247,\n\tALC295_FIXUP_HP_OMEN = 248,\n\tALC285_FIXUP_HP_SPECTRE_X360 = 249,\n\tALC287_FIXUP_IDEAPAD_BASS_SPK_AMP = 250,\n\tALC623_FIXUP_LENOVO_THINKSTATION_P340 = 251,\n\tALC255_FIXUP_ACER_HEADPHONE_AND_MIC = 252,\n\tALC236_FIXUP_HP_LIMIT_INT_MIC_BOOST = 253,\n\tALC287_FIXUP_LEGION_15IMHG05_SPEAKERS = 254,\n\tALC287_FIXUP_LEGION_15IMHG05_AUTOMUTE = 255,\n\tALC287_FIXUP_YOGA7_14ITL_SPEAKERS = 256,\n\tALC298_FIXUP_LENOVO_C940_DUET7 = 257,\n\tALC287_FIXUP_LENOVO_YOGA_BOOK_9I = 258,\n\tALC287_FIXUP_13S_GEN2_SPEAKERS = 259,\n\tALC256_FIXUP_SET_COEF_DEFAULTS = 260,\n\tALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE = 261,\n\tALC233_FIXUP_NO_AUDIO_JACK = 262,\n\tALC256_FIXUP_MIC_NO_PRESENCE_AND_RESUME = 263,\n\tALC285_FIXUP_LEGION_Y9000X_SPEAKERS = 264,\n\tALC285_FIXUP_LEGION_Y9000X_AUTOMUTE = 265,\n\tALC287_FIXUP_LEGION_16ACHG6 = 266,\n\tALC287_FIXUP_CS35L41_I2C_2 = 267,\n\tALC287_FIXUP_CS35L41_I2C_2_HP_GPIO_LED = 268,\n\tALC287_FIXUP_CS35L41_I2C_4 = 269,\n\tALC245_FIXUP_CS35L41_SPI_1 = 270,\n\tALC245_FIXUP_CS35L41_SPI_2 = 271,\n\tALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED = 272,\n\tALC245_FIXUP_CS35L41_SPI_4 = 273,\n\tALC245_FIXUP_CS35L41_SPI_4_HP_GPIO_LED = 274,\n\tALC285_FIXUP_HP_SPEAKERS_MICMUTE_LED = 275,\n\tALC295_FIXUP_FRAMEWORK_LAPTOP_MIC_NO_PRESENCE = 276,\n\tALC287_FIXUP_LEGION_16ITHG6 = 277,\n\tALC287_FIXUP_YOGA9_14IAP7_BASS_SPK = 278,\n\tALC287_FIXUP_YOGA9_14IAP7_BASS_SPK_PIN = 279,\n\tALC287_FIXUP_YOGA9_14IMH9_BASS_SPK_PIN = 280,\n\tALC295_FIXUP_DELL_INSPIRON_TOP_SPEAKERS = 281,\n\tALC236_FIXUP_DELL_DUAL_CODECS = 282,\n\tALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI = 283,\n\tALC287_FIXUP_TAS2781_I2C = 284,\n\tALC295_FIXUP_DELL_TAS2781_I2C = 285,\n\tALC245_FIXUP_TAS2781_SPI_2 = 286,\n\tALC287_FIXUP_TXNW2781_I2C = 287,\n\tALC287_FIXUP_TXNW2781_I2C_ASUS = 288,\n\tALC287_FIXUP_YOGA7_14ARB7_I2C = 289,\n\tALC245_FIXUP_HP_MUTE_LED_COEFBIT = 290,\n\tALC245_FIXUP_HP_MUTE_LED_V1_COEFBIT = 291,\n\tALC245_FIXUP_HP_MUTE_LED_V2_COEFBIT = 292,\n\tALC245_FIXUP_HP_X360_MUTE_LEDS = 293,\n\tALC287_FIXUP_THINKPAD_I2S_SPK = 294,\n\tALC287_FIXUP_MG_RTKC_CSAMP_CS35L41_I2C_THINKPAD = 295,\n\tALC2XX_FIXUP_HEADSET_MIC = 296,\n\tALC289_FIXUP_DELL_CS35L41_SPI_2 = 297,\n\tALC294_FIXUP_CS35L41_I2C_2 = 298,\n\tALC256_FIXUP_ACER_SFG16_MICMUTE_LED = 299,\n\tALC256_FIXUP_HEADPHONE_AMP_VOL = 300,\n\tALC245_FIXUP_HP_SPECTRE_X360_EU0XXX = 301,\n\tALC245_FIXUP_HP_SPECTRE_X360_16_AA0XXX = 302,\n\tALC245_FIXUP_HP_ZBOOK_FIREFLY_G12A = 303,\n\tALC285_FIXUP_ASUS_GA403U = 304,\n\tALC285_FIXUP_ASUS_GA403U_HEADSET_MIC = 305,\n\tALC285_FIXUP_ASUS_GA403U_I2C_SPEAKER2_TO_DAC1 = 306,\n\tALC285_FIXUP_ASUS_GU605_SPI_2_HEADSET_MIC = 307,\n\tALC285_FIXUP_ASUS_GU605_SPI_SPEAKER2_TO_DAC1 = 308,\n\tALC287_FIXUP_LENOVO_THKPAD_WH_ALC1318 = 309,\n\tALC256_FIXUP_CHROME_BOOK = 310,\n\tALC245_FIXUP_CLEVO_NOISY_MIC = 311,\n\tALC269_FIXUP_VAIO_VJFH52_MIC_NO_PRESENCE = 312,\n\tALC233_FIXUP_MEDION_MTL_SPK = 313,\n\tALC233_FIXUP_STARLABS_STARFIGHTER = 314,\n\tALC294_FIXUP_BASS_SPEAKER_15 = 315,\n\tALC283_FIXUP_DELL_HP_RESUME = 316,\n\tALC294_FIXUP_ASUS_CS35L41_SPI_2 = 317,\n\tALC274_FIXUP_HP_AIO_BIND_DACS = 318,\n\tALC287_FIXUP_PREDATOR_SPK_CS35L41_I2C_2 = 319,\n\tALC285_FIXUP_ASUS_GA605K_HEADSET_MIC = 320,\n\tALC285_FIXUP_ASUS_GA605K_I2C_SPEAKER2_TO_DAC1 = 321,\n\tALC269_FIXUP_POSITIVO_P15X_HEADSET_MIC = 322,\n\tALC289_FIXUP_ASUS_ZEPHYRUS_DUAL_SPK = 323,\n\tALC256_FIXUP_VAIO_RPL_MIC_NO_PRESENCE = 324,\n\tALC245_FIXUP_HP_TAS2781_SPI_MUTE_LED = 325,\n\tALC245_FIXUP_HP_TAS2781_I2C_MUTE_LED = 326,\n\tALC288_FIXUP_SURFACE_SWAP_DACS = 327,\n\tALC236_FIXUP_HP_MUTE_LED_MICMUTE_GPIO = 328,\n\tALC233_FIXUP_LENOVO_GPIO2_MIC_HOTKEY = 329,\n\tALC245_FIXUP_BASS_HP_DAC = 330,\n\tALC245_FIXUP_ACER_MICMUTE_LED = 331,\n};\n\nenum {\n\tALC269_TYPE_ALC269VA = 0,\n\tALC269_TYPE_ALC269VB = 1,\n\tALC269_TYPE_ALC269VC = 2,\n\tALC269_TYPE_ALC269VD = 3,\n\tALC269_TYPE_ALC280 = 4,\n\tALC269_TYPE_ALC282 = 5,\n\tALC269_TYPE_ALC283 = 6,\n\tALC269_TYPE_ALC284 = 7,\n\tALC269_TYPE_ALC293 = 8,\n\tALC269_TYPE_ALC286 = 9,\n\tALC269_TYPE_ALC298 = 10,\n\tALC269_TYPE_ALC255 = 11,\n\tALC269_TYPE_ALC256 = 12,\n\tALC269_TYPE_ALC257 = 13,\n\tALC269_TYPE_ALC215 = 14,\n\tALC269_TYPE_ALC225 = 15,\n\tALC269_TYPE_ALC245 = 16,\n\tALC269_TYPE_ALC287 = 17,\n\tALC269_TYPE_ALC294 = 18,\n\tALC269_TYPE_ALC300 = 19,\n\tALC269_TYPE_ALC623 = 20,\n\tALC269_TYPE_ALC700 = 21,\n};\n\nenum {\n\tALC660VD_FIX_ASUS_GPIO1 = 0,\n\tALC861VD_FIX_DALLAS = 1,\n};\n\nenum {\n\tALC662_FIXUP_ASPIRE = 0,\n\tALC662_FIXUP_LED_GPIO1 = 1,\n\tALC662_FIXUP_IDEAPAD = 2,\n\tALC272_FIXUP_MARIO = 3,\n\tALC662_FIXUP_CZC_ET26 = 4,\n\tALC662_FIXUP_CZC_P10T = 5,\n\tALC662_FIXUP_SKU_IGNORE = 6,\n\tALC662_FIXUP_HP_RP5800 = 7,\n\tALC662_FIXUP_ASUS_MODE1 = 8,\n\tALC662_FIXUP_ASUS_MODE2 = 9,\n\tALC662_FIXUP_ASUS_MODE3 = 10,\n\tALC662_FIXUP_ASUS_MODE4 = 11,\n\tALC662_FIXUP_ASUS_MODE5 = 12,\n\tALC662_FIXUP_ASUS_MODE6 = 13,\n\tALC662_FIXUP_ASUS_MODE7 = 14,\n\tALC662_FIXUP_ASUS_MODE8 = 15,\n\tALC662_FIXUP_NO_JACK_DETECT = 16,\n\tALC662_FIXUP_ZOTAC_Z68 = 17,\n\tALC662_FIXUP_INV_DMIC = 18,\n\tALC662_FIXUP_DELL_MIC_NO_PRESENCE = 19,\n\tALC668_FIXUP_DELL_MIC_NO_PRESENCE = 20,\n\tALC662_FIXUP_HEADSET_MODE = 21,\n\tALC668_FIXUP_HEADSET_MODE = 22,\n\tALC662_FIXUP_BASS_MODE4_CHMAP = 23,\n\tALC662_FIXUP_BASS_16 = 24,\n\tALC662_FIXUP_BASS_1A = 25,\n\tALC662_FIXUP_BASS_CHMAP = 26,\n\tALC668_FIXUP_AUTO_MUTE = 27,\n\tALC668_FIXUP_DELL_DISABLE_AAMIX = 28,\n\tALC668_FIXUP_DELL_XPS13 = 29,\n\tALC662_FIXUP_ASUS_Nx50 = 30,\n\tALC668_FIXUP_ASUS_Nx51_HEADSET_MODE = 31,\n\tALC668_FIXUP_ASUS_Nx51 = 32,\n\tALC668_FIXUP_MIC_COEF = 33,\n\tALC668_FIXUP_ASUS_G751 = 34,\n\tALC891_FIXUP_HEADSET_MODE = 35,\n\tALC891_FIXUP_DELL_MIC_NO_PRESENCE = 36,\n\tALC662_FIXUP_ACER_VERITON = 37,\n\tALC892_FIXUP_ASROCK_MOBO = 38,\n\tALC662_FIXUP_USI_FUNC = 39,\n\tALC662_FIXUP_USI_HEADSET_MODE = 40,\n\tALC662_FIXUP_LENOVO_MULTI_CODECS = 41,\n\tALC669_FIXUP_ACER_ASPIRE_ETHOS = 42,\n\tALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET = 43,\n\tALC671_FIXUP_HP_HEADSET_MIC2 = 44,\n\tALC662_FIXUP_ACER_X2660G_HEADSET_MODE = 45,\n\tALC662_FIXUP_ACER_NITRO_HEADSET_MODE = 46,\n\tALC668_FIXUP_ASUS_NO_HEADSET_MIC = 47,\n\tALC668_FIXUP_HEADSET_MIC = 48,\n\tALC668_FIXUP_MIC_DET_COEF = 49,\n\tALC897_FIXUP_LENOVO_HEADSET_MIC = 50,\n\tALC897_FIXUP_HEADSET_MIC_PIN = 51,\n\tALC897_FIXUP_HP_HSMIC_VERB = 52,\n\tALC897_FIXUP_LENOVO_HEADSET_MODE = 53,\n\tALC897_FIXUP_HEADSET_MIC_PIN2 = 54,\n\tALC897_FIXUP_UNIS_H3C_X500S = 55,\n\tALC897_FIXUP_HEADSET_MIC_PIN3 = 56,\n};\n\nenum {\n\tALC861_FIXUP_FSC_AMILO_PI1505 = 0,\n\tALC861_FIXUP_AMP_VREF_0F = 1,\n\tALC861_FIXUP_NO_JACK_DETECT = 2,\n\tALC861_FIXUP_ASUS_A6RP = 3,\n\tALC660_FIXUP_ASUS_W7J = 4,\n};\n\nenum {\n\tALC880_FIXUP_GPIO1 = 0,\n\tALC880_FIXUP_GPIO2 = 1,\n\tALC880_FIXUP_MEDION_RIM = 2,\n\tALC880_FIXUP_LG = 3,\n\tALC880_FIXUP_LG_LW25 = 4,\n\tALC880_FIXUP_W810 = 5,\n\tALC880_FIXUP_EAPD_COEF = 6,\n\tALC880_FIXUP_TCL_S700 = 7,\n\tALC880_FIXUP_VOL_KNOB = 8,\n\tALC880_FIXUP_FUJITSU = 9,\n\tALC880_FIXUP_F1734 = 10,\n\tALC880_FIXUP_UNIWILL = 11,\n\tALC880_FIXUP_UNIWILL_DIG = 12,\n\tALC880_FIXUP_Z71V = 13,\n\tALC880_FIXUP_ASUS_W5A = 14,\n\tALC880_FIXUP_3ST_BASE = 15,\n\tALC880_FIXUP_3ST = 16,\n\tALC880_FIXUP_3ST_DIG = 17,\n\tALC880_FIXUP_5ST_BASE = 18,\n\tALC880_FIXUP_5ST = 19,\n\tALC880_FIXUP_5ST_DIG = 20,\n\tALC880_FIXUP_6ST_BASE = 21,\n\tALC880_FIXUP_6ST = 22,\n\tALC880_FIXUP_6ST_DIG = 23,\n\tALC880_FIXUP_6ST_AUTOMUTE = 24,\n};\n\nenum {\n\tALC882_FIXUP_ABIT_AW9D_MAX = 0,\n\tALC882_FIXUP_LENOVO_Y530 = 1,\n\tALC882_FIXUP_PB_M5210 = 2,\n\tALC882_FIXUP_ACER_ASPIRE_7736 = 3,\n\tALC882_FIXUP_ASUS_W90V = 4,\n\tALC889_FIXUP_CD = 5,\n\tALC889_FIXUP_FRONT_HP_NO_PRESENCE = 6,\n\tALC889_FIXUP_VAIO_TT = 7,\n\tALC888_FIXUP_EEE1601 = 8,\n\tALC886_FIXUP_EAPD = 9,\n\tALC882_FIXUP_EAPD = 10,\n\tALC883_FIXUP_EAPD = 11,\n\tALC883_FIXUP_ACER_EAPD = 12,\n\tALC882_FIXUP_GPIO1 = 13,\n\tALC882_FIXUP_GPIO2 = 14,\n\tALC882_FIXUP_GPIO3 = 15,\n\tALC889_FIXUP_COEF = 16,\n\tALC882_FIXUP_ASUS_W2JC = 17,\n\tALC882_FIXUP_ACER_ASPIRE_4930G = 18,\n\tALC882_FIXUP_ACER_ASPIRE_8930G = 19,\n\tALC882_FIXUP_ASPIRE_8930G_VERBS = 20,\n\tALC885_FIXUP_MACPRO_GPIO = 21,\n\tALC889_FIXUP_DAC_ROUTE = 22,\n\tALC889_FIXUP_MBP_VREF = 23,\n\tALC889_FIXUP_IMAC91_VREF = 24,\n\tALC889_FIXUP_MBA11_VREF = 25,\n\tALC889_FIXUP_MBA21_VREF = 26,\n\tALC889_FIXUP_MP11_VREF = 27,\n\tALC889_FIXUP_MP41_VREF = 28,\n\tALC882_FIXUP_INV_DMIC = 29,\n\tALC882_FIXUP_NO_PRIMARY_HP = 30,\n\tALC887_FIXUP_ASUS_BASS = 31,\n\tALC887_FIXUP_BASS_CHMAP = 32,\n\tALC1220_FIXUP_GB_DUAL_CODECS = 33,\n\tALC1220_FIXUP_GB_X570 = 34,\n\tALC1220_FIXUP_CLEVO_P950 = 35,\n\tALC1220_FIXUP_CLEVO_PB51ED = 36,\n\tALC1220_FIXUP_CLEVO_PB51ED_PINS = 37,\n\tALC887_FIXUP_ASUS_AUDIO = 38,\n\tALC887_FIXUP_ASUS_HMIC = 39,\n\tALCS1200A_FIXUP_MIC_VREF = 40,\n\tALC888VD_FIXUP_MIC_100VREF = 41,\n};\n\nenum {\n\tALC_HEADSET_MODE_UNKNOWN = 0,\n\tALC_HEADSET_MODE_UNPLUGGED = 1,\n\tALC_HEADSET_MODE_HEADSET = 2,\n\tALC_HEADSET_MODE_MIC = 3,\n\tALC_HEADSET_MODE_HEADPHONE = 4,\n};\n\nenum {\n\tALC_HEADSET_TYPE_UNKNOWN = 0,\n\tALC_HEADSET_TYPE_CTIA = 1,\n\tALC_HEADSET_TYPE_OMTP = 2,\n};\n\nenum {\n\tALC_INIT_UNDEFINED = 0,\n\tALC_INIT_NONE = 1,\n\tALC_INIT_DEFAULT = 2,\n};\n\nenum {\n\tALC_KEY_MICMUTE_INDEX = 0,\n};\n\nenum {\n\tALID_PCMIN = 0,\n\tALID_PCMOUT = 1,\n\tALID_MIC = 2,\n\tALID_AC97SPDIFOUT = 3,\n\tALID_SPDIFIN = 4,\n\tALID_SPDIFOUT = 5,\n\tALID_LAST = 5,\n};\n\nenum {\n\tAMDV1PT_FMT_PR = 1ULL,\n\tAMDV1PT_FMT_D = 64ULL,\n\tAMDV1PT_FMT_NEXT_LEVEL = 3584ULL,\n\tAMDV1PT_FMT_OA = 4503599627366400ULL,\n\tAMDV1PT_FMT_FC = 1152921504606846976ULL,\n\tAMDV1PT_FMT_IR = 2305843009213693952ULL,\n\tAMDV1PT_FMT_IW = 4611686018427387904ULL,\n};\n\nenum {\n\tAML_FIELD_ACCESS_ANY = 0,\n\tAML_FIELD_ACCESS_BYTE = 1,\n\tAML_FIELD_ACCESS_WORD = 2,\n\tAML_FIELD_ACCESS_DWORD = 3,\n\tAML_FIELD_ACCESS_QWORD = 4,\n\tAML_FIELD_ACCESS_BUFFER = 5,\n};\n\nenum {\n\tAML_FIELD_ATTRIB_QUICK = 2,\n\tAML_FIELD_ATTRIB_SEND_RECEIVE = 4,\n\tAML_FIELD_ATTRIB_BYTE = 6,\n\tAML_FIELD_ATTRIB_WORD = 8,\n\tAML_FIELD_ATTRIB_BLOCK = 10,\n\tAML_FIELD_ATTRIB_BYTES = 11,\n\tAML_FIELD_ATTRIB_PROCESS_CALL = 12,\n\tAML_FIELD_ATTRIB_BLOCK_PROCESS_CALL = 13,\n\tAML_FIELD_ATTRIB_RAW_BYTES = 14,\n\tAML_FIELD_ATTRIB_RAW_PROCESS_BYTES = 15,\n};\n\nenum {\n\tAML_FIELD_UPDATE_PRESERVE = 0,\n\tAML_FIELD_UPDATE_WRITE_AS_ONES = 32,\n\tAML_FIELD_UPDATE_WRITE_AS_ZEROS = 64,\n};\n\nenum {\n\tARCH_LBR_BR_TYPE_JCC = 0,\n\tARCH_LBR_BR_TYPE_NEAR_IND_JMP = 1,\n\tARCH_LBR_BR_TYPE_NEAR_REL_JMP = 2,\n\tARCH_LBR_BR_TYPE_NEAR_IND_CALL = 3,\n\tARCH_LBR_BR_TYPE_NEAR_REL_CALL = 4,\n\tARCH_LBR_BR_TYPE_NEAR_RET = 5,\n\tARCH_LBR_BR_TYPE_KNOWN_MAX = 5,\n\tARCH_LBR_BR_TYPE_MAP_MAX = 16,\n};\n\nenum {\n\tARCH_UPROBE_FLAG_CAN_OPTIMIZE = 0,\n\tARCH_UPROBE_FLAG_OPTIMIZE_FAIL = 1,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = -2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = -2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_CDL = 24,\n\tATA_LOG_CDL_SIZE = 512,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SENSE_NCQ = 15,\n\tATA_LOG_SENSE_NCQ_SIZE = 1024,\n\tATA_LOG_CONCURRENT_POSITIONING_RANGES = 71,\n\tATA_LOG_SUPPORTED_CAPABILITIES = 3,\n\tATA_LOG_CURRENT_SETTINGS = 4,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSETFEATURES_CDL = 13,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tSETFEATURE_SENSE_DATA_SUCC_NCQ = 196,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum {\n\tATA_QUIRK_DIAGNOSTIC = 1,\n\tATA_QUIRK_NODMA = 2,\n\tATA_QUIRK_NONCQ = 4,\n\tATA_QUIRK_BROKEN_HPA = 8,\n\tATA_QUIRK_DISABLE = 16,\n\tATA_QUIRK_HPA_SIZE = 32,\n\tATA_QUIRK_IVB = 64,\n\tATA_QUIRK_STUCK_ERR = 128,\n\tATA_QUIRK_BRIDGE_OK = 256,\n\tATA_QUIRK_ATAPI_MOD16_DMA = 512,\n\tATA_QUIRK_FIRMWARE_WARN = 1024,\n\tATA_QUIRK_1_5_GBPS = 2048,\n\tATA_QUIRK_NOSETXFER = 4096,\n\tATA_QUIRK_BROKEN_FPDMA_AA = 8192,\n\tATA_QUIRK_DUMP_ID = 16384,\n\tATA_QUIRK_MAX_SEC_LBA48 = 32768,\n\tATA_QUIRK_ATAPI_DMADIR = 65536,\n\tATA_QUIRK_NO_NCQ_TRIM = 131072,\n\tATA_QUIRK_NOLPM = 262144,\n\tATA_QUIRK_WD_BROKEN_LPM = 524288,\n\tATA_QUIRK_ZERO_AFTER_TRIM = 1048576,\n\tATA_QUIRK_NO_DMA_LOG = 2097152,\n\tATA_QUIRK_NOTRIM = 4194304,\n\tATA_QUIRK_MAX_SEC = 8388608,\n\tATA_QUIRK_MAX_TRIM_128M = 16777216,\n\tATA_QUIRK_NO_NCQ_ON_ATI = 33554432,\n\tATA_QUIRK_NO_LPM_ON_ATI = 67108864,\n\tATA_QUIRK_NO_ID_DEV_LOG = 134217728,\n\tATA_QUIRK_NO_LOG_DIR = 268435456,\n\tATA_QUIRK_NO_FUA = 536870912,\n};\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = -2147483648,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAUTOP_INVALID = 0,\n\tAUTOP_HDD = 1,\n\tAUTOP_SSD_QD1 = 2,\n\tAUTOP_SSD_DFL = 3,\n\tAUTOP_SSD_FAST = 4,\n};\n\nenum {\n\tAUTO_PIN_LINE_OUT = 0,\n\tAUTO_PIN_SPEAKER_OUT = 1,\n\tAUTO_PIN_HP_OUT = 2,\n};\n\nenum {\n\tAUTO_PIN_MIC = 0,\n\tAUTO_PIN_LINE_IN = 1,\n\tAUTO_PIN_CD = 2,\n\tAUTO_PIN_AUX = 3,\n\tAUTO_PIN_LAST = 4,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tAZX_DRIVER_ICH = 0,\n\tAZX_DRIVER_PCH = 1,\n\tAZX_DRIVER_SCH = 2,\n\tAZX_DRIVER_SKL = 3,\n\tAZX_DRIVER_HDMI = 4,\n\tAZX_DRIVER_ATI = 5,\n\tAZX_DRIVER_ATIHDMI = 6,\n\tAZX_DRIVER_ATIHDMI_NS = 7,\n\tAZX_DRIVER_GFHDMI = 8,\n\tAZX_DRIVER_VIA = 9,\n\tAZX_DRIVER_SIS = 10,\n\tAZX_DRIVER_ULI = 11,\n\tAZX_DRIVER_NVIDIA = 12,\n\tAZX_DRIVER_TERA = 13,\n\tAZX_DRIVER_CTX = 14,\n\tAZX_DRIVER_CTHDA = 15,\n\tAZX_DRIVER_CMEDIA = 16,\n\tAZX_DRIVER_ZHAOXIN = 17,\n\tAZX_DRIVER_ZHAOXINHDMI = 18,\n\tAZX_DRIVER_LOONGSON = 19,\n\tAZX_DRIVER_GENERIC = 20,\n\tAZX_NUM_DRIVERS = 21,\n};\n\nenum {\n\tAZX_SNOOP_TYPE_NONE = 0,\n\tAZX_SNOOP_TYPE_SCH = 1,\n\tAZX_SNOOP_TYPE_ATI = 2,\n\tAZX_SNOOP_TYPE_NVIDIA = 3,\n};\n\nenum {\n\tBAD_NO_PRIMARY_DAC = 65536,\n\tBAD_NO_DAC = 16384,\n\tBAD_MULTI_IO = 288,\n\tBAD_NO_EXTRA_DAC = 258,\n\tBAD_NO_EXTRA_SURR_DAC = 257,\n\tBAD_SHARED_SURROUND = 256,\n\tBAD_NO_INDEP_HP = 16,\n\tBAD_SHARED_CLFE = 16,\n\tBAD_SHARED_EXTRA_SURROUND = 16,\n\tBAD_SHARED_VOL = 16,\n};\n\nenum {\n\tBDX_PCI_UNCORE_HA = 0,\n\tBDX_PCI_UNCORE_IMC = 1,\n\tBDX_PCI_UNCORE_IRP = 2,\n\tBDX_PCI_UNCORE_QPI = 3,\n\tBDX_PCI_UNCORE_R2PCIE = 4,\n\tBDX_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\nenum {\n\tBPF_F_SYSCTL_BASE_NAME = 1,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 38,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBPF_WRITE_HDR_TCP_CURRENT_MSS = 1,\n\tBPF_WRITE_HDR_TCP_SYNACK_COOKIE = 2,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tBTS_STATE_STOPPED = 0,\n\tBTS_STATE_INACTIVE = 1,\n\tBTS_STATE_ACTIVE = 2,\n};\n\nenum {\n\tBlktrace_setup = 1,\n\tBlktrace_running = 2,\n\tBlktrace_stopped = 3,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGROUPSTATS_CMD_ATTR_UNSPEC = 0,\n\tCGROUPSTATS_CMD_ATTR_FD = 1,\n\t__CGROUPSTATS_CMD_ATTR_MAX = 2,\n};\n\nenum {\n\tCGROUPSTATS_CMD_UNSPEC = 3,\n\tCGROUPSTATS_CMD_GET = 4,\n\tCGROUPSTATS_CMD_NEW = 5,\n\t__CGROUPSTATS_CMD_MAX = 6,\n};\n\nenum {\n\tCGROUPSTATS_TYPE_UNSPEC = 0,\n\tCGROUPSTATS_TYPE_CGROUP_STATS = 1,\n\t__CGROUPSTATS_TYPE_MAX = 2,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCLEAN = 0,\n\tUPDATE_IN_PROGRESS = 1,\n\tDIRTY = 2,\n};\n\nenum {\n\tCLEAR_RESIDUALS = 0,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCM_ASL_WLAN = 0,\n\tCM_ASL_BLUETOOTH = 1,\n\tCM_ASL_IRDA = 2,\n\tCM_ASL_1394 = 3,\n\tCM_ASL_CAMERA = 4,\n\tCM_ASL_TV = 5,\n\tCM_ASL_GPS = 6,\n\tCM_ASL_DVDROM = 7,\n\tCM_ASL_DISPLAYSWITCH = 8,\n\tCM_ASL_PANELBRIGHT = 9,\n\tCM_ASL_BIOSFLASH = 10,\n\tCM_ASL_ACPIFLASH = 11,\n\tCM_ASL_CPUFV = 12,\n\tCM_ASL_CPUTEMPERATURE = 13,\n\tCM_ASL_FANCPU = 14,\n\tCM_ASL_FANCHASSIS = 15,\n\tCM_ASL_USBPORT1 = 16,\n\tCM_ASL_USBPORT2 = 17,\n\tCM_ASL_USBPORT3 = 18,\n\tCM_ASL_MODEM = 19,\n\tCM_ASL_CARDREADER = 20,\n\tCM_ASL_3G = 21,\n\tCM_ASL_WIMAX = 22,\n\tCM_ASL_HWCF = 23,\n\tCM_ASL_LID = 24,\n\tCM_ASL_TYPE = 25,\n\tCM_ASL_PANELPOWER = 26,\n\tCM_ASL_TPD = 27,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCOST_CTRL = 0,\n\tCOST_MODEL = 1,\n\tNR_COST_CTRL_PARAMS = 2,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 1000,\n\tCRNG_RESEED_INTERVAL = 60000,\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\t__CRYPTOA_MAX = 3,\n};\n\nenum {\n\tCRYPTO_AUTHENC_KEYA_UNSPEC = 0,\n\tCRYPTO_AUTHENC_KEYA_PARAM = 1,\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tD0TIM = 128,\n\tD1TIM = 132,\n\tPM = 7,\n\tMDM = 768,\n\tUDM = 458752,\n\tPPE = 1073741824,\n\tUSD = -2147483648,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEBUG_FENCE_IDLE = 0,\n\tDEBUG_FENCE_NOTIFY = 1,\n};\n\nenum {\n\tDELL_INSPIRON_7375 = 0,\n\tDELL_LATITUDE_5495 = 1,\n\tLENOVO_IDEAPAD_330S_15ARR = 2,\n};\n\nenum {\n\tDESC_TSS = 9,\n\tDESC_LDT = 2,\n\tDESCTYPE_S = 16,\n};\n\nenum {\n\tDEVICE_INTEL = 0,\n\tDEVICE_INTEL_ICH4 = 1,\n\tDEVICE_SIS = 2,\n\tDEVICE_ALI = 3,\n\tDEVICE_NFORCE = 4,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISABLE_ASL_WLAN = 1,\n\tDISABLE_ASL_BLUETOOTH = 2,\n\tDISABLE_ASL_IRDA = 4,\n\tDISABLE_ASL_CAMERA = 8,\n\tDISABLE_ASL_TV = 16,\n\tDISABLE_ASL_GPS = 32,\n\tDISABLE_ASL_DISPLAYSWITCH = 64,\n\tDISABLE_ASL_MODEM = 128,\n\tDISABLE_ASL_CARDREADER = 256,\n\tDISABLE_ASL_3G = 512,\n\tDISABLE_ASL_WIMAX = 1024,\n\tDISABLE_ASL_HWCF = 2048,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDMA_DSCR_HOST = 0,\n\tDMA_DSCR_DEVICE = 1,\n\tDMA_DSCR_CTRL = 2,\n\tDMA_DSCR_NUM = 3,\n};\n\nenum {\n\tDMA_FENCE_WORK_IMM = 4,\n};\n\nenum {\n\tDM_IO_ACCOUNTED = 0,\n\tDM_IO_WAS_SPLIT = 1,\n\tDM_IO_BLK_STAT = 2,\n};\n\nenum {\n\tDM_TIO_INSIDE_DM_IO = 0,\n\tDM_TIO_IS_DUPLICATE_BIO = 1,\n};\n\nenum {\n\tDM_VERSION_CMD = 0,\n\tDM_REMOVE_ALL_CMD = 1,\n\tDM_LIST_DEVICES_CMD = 2,\n\tDM_DEV_CREATE_CMD = 3,\n\tDM_DEV_REMOVE_CMD = 4,\n\tDM_DEV_RENAME_CMD = 5,\n\tDM_DEV_SUSPEND_CMD = 6,\n\tDM_DEV_STATUS_CMD = 7,\n\tDM_DEV_WAIT_CMD = 8,\n\tDM_TABLE_LOAD_CMD = 9,\n\tDM_TABLE_CLEAR_CMD = 10,\n\tDM_TABLE_DEPS_CMD = 11,\n\tDM_TABLE_STATUS_CMD = 12,\n\tDM_LIST_VERSIONS_CMD = 13,\n\tDM_TARGET_MSG_CMD = 14,\n\tDM_DEV_SET_GEOMETRY_CMD = 15,\n\tDM_DEV_ARM_POLL_CMD = 16,\n\tDM_GET_TARGET_VERSION_CMD = 17,\n\tDM_MPATH_PROBE_PATHS_CMD = 18,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDQF_INFO_DIRTY_B = 17,\n};\n\nenum {\n\tDQF_ROOT_SQUASH_B = 0,\n\tDQF_SYS_FILE_B = 16,\n\tDQF_PRIVATE = 17,\n};\n\nenum {\n\tDQST_LOOKUPS = 0,\n\tDQST_DROPS = 1,\n\tDQST_READS = 2,\n\tDQST_WRITES = 3,\n\tDQST_CACHE_HITS = 4,\n\tDQST_ALLOC_DQUOTS = 5,\n\tDQST_FREE_DQUOTS = 6,\n\tDQST_SYNCS = 7,\n\t_DQST_DQSTAT_LAST = 8,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tEC_FLAGS_QUERY_ENABLED = 0,\n\tEC_FLAGS_EVENT_HANDLER_INSTALLED = 1,\n\tEC_FLAGS_EC_HANDLER_INSTALLED = 2,\n\tEC_FLAGS_EC_REG_CALLED = 3,\n\tEC_FLAGS_QUERY_METHODS_INSTALLED = 4,\n\tEC_FLAGS_STARTED = 5,\n\tEC_FLAGS_STOPPED = 6,\n\tEC_FLAGS_EVENTS_MASKED = 7,\n};\n\nenum {\n\tEMULATE = 0,\n\tXONLY = 1,\n\tNONE = 2,\n};\n\nenum {\n\tENABLE_DMC_WL_DISABLED = 0,\n\tENABLE_DMC_WL_ENABLED = 1,\n\tENABLE_DMC_WL_ANY_REGISTER = 2,\n\tENABLE_DMC_WL_ALWAYS_LOCKED = 3,\n\tENABLE_DMC_WL_MAX = 4,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_CODE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_CODE_OK = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE_OPEN = 2,\n\tETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT = 3,\n\tETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT = 4,\n\tETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH = 5,\n\tETHTOOL_A_CABLE_RESULT_CODE_NOISE = 6,\n\tETHTOOL_A_CABLE_RESULT_CODE_RESOLUTION_NOT_POSSIBLE = 7,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENTFS_SAVE_MODE = 65536,\n\tEVENTFS_SAVE_UID = 131072,\n\tEVENTFS_SAVE_GID = 262144,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_DISABLED = 32,\n\tEVENT_FILE_FL_TRIGGER_MODE = 64,\n\tEVENT_FILE_FL_TRIGGER_COND = 128,\n\tEVENT_FILE_FL_PID_FILTER = 256,\n\tEVENT_FILE_FL_WAS_ENABLED = 512,\n\tEVENT_FILE_FL_FREED = 1024,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEVENT_TRIGGER_FL_PROBE = 1,\n\tEVENT_TRIGGER_FL_COUNT = 2,\n};\n\nenum {\n\tEXPECT_SWBP = 0,\n\tEXPECT_CALL = 1,\n};\n\nenum {\n\tEXTRA_REG_NHMEX_M_FILTER = 0,\n\tEXTRA_REG_NHMEX_M_DSP = 1,\n\tEXTRA_REG_NHMEX_M_ISS = 2,\n\tEXTRA_REG_NHMEX_M_MAP = 3,\n\tEXTRA_REG_NHMEX_M_MSC_THR = 4,\n\tEXTRA_REG_NHMEX_M_PGT = 5,\n\tEXTRA_REG_NHMEX_M_PLD = 6,\n\tEXTRA_REG_NHMEX_M_ZDP_CTL_FVC = 7,\n};\n\nenum {\n\tEnabled = 0,\n\tMagic = 1,\n};\n\nenum {\n\tFBCON_LOGO_CANSHOW = -1,\n\tFBCON_LOGO_DRAW = -2,\n\tFBCON_LOGO_DONTSHOW = -3,\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nenum {\n\tFGRAPH_TYPE_RESERVED = 0,\n\tFGRAPH_TYPE_BITMAP = 1,\n\tFGRAPH_TYPE_DATA = 2,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_RDYN_STRING = 3,\n\tFILTER_PTR_STRING = 4,\n\tFILTER_TRACE_FN = 5,\n\tFILTER_CPUMASK = 6,\n\tFILTER_COMM = 7,\n\tFILTER_CPU = 8,\n\tFILTER_STACKTRACE = 9,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_MISSING_BRACE_OPEN = 5,\n\tFILT_ERR_MISSING_BRACE_CLOSE = 6,\n\tFILT_ERR_OPERAND_TOO_LONG = 7,\n\tFILT_ERR_EXPECT_STRING = 8,\n\tFILT_ERR_EXPECT_DIGIT = 9,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 10,\n\tFILT_ERR_FIELD_NOT_FOUND = 11,\n\tFILT_ERR_ILLEGAL_INTVAL = 12,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 13,\n\tFILT_ERR_TOO_MANY_PREDS = 14,\n\tFILT_ERR_INVALID_FILTER = 15,\n\tFILT_ERR_INVALID_CPULIST = 16,\n\tFILT_ERR_IP_FIELD_ONLY = 17,\n\tFILT_ERR_INVALID_VALUE = 18,\n\tFILT_ERR_NO_FUNCTION = 19,\n\tFILT_ERR_ERRNO = 20,\n\tFILT_ERR_NO_FILTER = 21,\n};\n\nenum {\n\tFLAGS_FILL_FULL = 268435456,\n\tFLAGS_FILL_START = 536870912,\n\tFLAGS_FILL_END = 805306368,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFORCE_CPU_RELOC = 1,\n\tFORCE_GTT_RELOC = 2,\n\tFORCE_GPU_RELOC = 3,\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\nenum {\n\tFRA_UNSPEC = 0,\n\tFRA_DST = 1,\n\tFRA_SRC = 2,\n\tFRA_IIFNAME = 3,\n\tFRA_GOTO = 4,\n\tFRA_UNUSED2 = 5,\n\tFRA_PRIORITY = 6,\n\tFRA_UNUSED3 = 7,\n\tFRA_UNUSED4 = 8,\n\tFRA_UNUSED5 = 9,\n\tFRA_FWMARK = 10,\n\tFRA_FLOW = 11,\n\tFRA_TUN_ID = 12,\n\tFRA_SUPPRESS_IFGROUP = 13,\n\tFRA_SUPPRESS_PREFIXLEN = 14,\n\tFRA_TABLE = 15,\n\tFRA_FWMASK = 16,\n\tFRA_OIFNAME = 17,\n\tFRA_PAD = 18,\n\tFRA_L3MDEV = 19,\n\tFRA_UID_RANGE = 20,\n\tFRA_PROTOCOL = 21,\n\tFRA_IP_PROTO = 22,\n\tFRA_SPORT_RANGE = 23,\n\tFRA_DPORT_RANGE = 24,\n\tFRA_DSCP = 25,\n\tFRA_FLOWLABEL = 26,\n\tFRA_FLOWLABEL_MASK = 27,\n\tFRA_SPORT_MASK = 28,\n\tFRA_DPORT_MASK = 29,\n\tFRA_DSCP_MASK = 30,\n\t__FRA_MAX = 31,\n};\n\nenum {\n\tFR_ACT_UNSPEC = 0,\n\tFR_ACT_TO_TBL = 1,\n\tFR_ACT_GOTO = 2,\n\tFR_ACT_NOP = 3,\n\tFR_ACT_RES3 = 4,\n\tFR_ACT_RES4 = 5,\n\tFR_ACT_BLACKHOLE = 6,\n\tFR_ACT_UNREACHABLE = 7,\n\tFR_ACT_PROHIBIT = 8,\n\t__FR_ACT_MAX = 9,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFTRACE_FL_ENABLED = 2147483648,\n\tFTRACE_FL_REGS = 1073741824,\n\tFTRACE_FL_REGS_EN = 536870912,\n\tFTRACE_FL_TRAMP = 268435456,\n\tFTRACE_FL_TRAMP_EN = 134217728,\n\tFTRACE_FL_IPMODIFY = 67108864,\n\tFTRACE_FL_DISABLED = 33554432,\n\tFTRACE_FL_DIRECT = 16777216,\n\tFTRACE_FL_DIRECT_EN = 8388608,\n\tFTRACE_FL_CALL_OPS = 4194304,\n\tFTRACE_FL_CALL_OPS_EN = 2097152,\n\tFTRACE_FL_TOUCHED = 1048576,\n\tFTRACE_FL_MODIFIED = 524288,\n};\n\nenum {\n\tFTRACE_HASH_FL_MOD = 1,\n};\n\nenum {\n\tFTRACE_ITER_FILTER = 1,\n\tFTRACE_ITER_NOTRACE = 2,\n\tFTRACE_ITER_PRINTALL = 4,\n\tFTRACE_ITER_DO_PROBES = 8,\n\tFTRACE_ITER_PROBE = 16,\n\tFTRACE_ITER_MOD = 32,\n\tFTRACE_ITER_ENABLED = 64,\n\tFTRACE_ITER_TOUCHED = 128,\n\tFTRACE_ITER_ADDRS = 256,\n};\n\nenum {\n\tFTRACE_MODIFY_ENABLE_FL = 1,\n\tFTRACE_MODIFY_MAY_SLEEP_FL = 2,\n};\n\nenum {\n\tFTRACE_OPS_FL_ENABLED = 1,\n\tFTRACE_OPS_FL_DYNAMIC = 2,\n\tFTRACE_OPS_FL_SAVE_REGS = 4,\n\tFTRACE_OPS_FL_SAVE_REGS_IF_SUPPORTED = 8,\n\tFTRACE_OPS_FL_RECURSION = 16,\n\tFTRACE_OPS_FL_STUB = 32,\n\tFTRACE_OPS_FL_INITIALIZED = 64,\n\tFTRACE_OPS_FL_DELETED = 128,\n\tFTRACE_OPS_FL_ADDING = 256,\n\tFTRACE_OPS_FL_REMOVING = 512,\n\tFTRACE_OPS_FL_MODIFYING = 1024,\n\tFTRACE_OPS_FL_ALLOC_TRAMP = 2048,\n\tFTRACE_OPS_FL_IPMODIFY = 4096,\n\tFTRACE_OPS_FL_PID = 8192,\n\tFTRACE_OPS_FL_RCU = 16384,\n\tFTRACE_OPS_FL_TRACE_ARRAY = 32768,\n\tFTRACE_OPS_FL_PERMANENT = 65536,\n\tFTRACE_OPS_FL_DIRECT = 131072,\n\tFTRACE_OPS_FL_SUBOP = 262144,\n\tFTRACE_OPS_FL_GRAPH = 524288,\n};\n\nenum {\n\tFTRACE_UPDATE_CALLS = 1,\n\tFTRACE_DISABLE_CALLS = 2,\n\tFTRACE_UPDATE_TRACE_FUNC = 4,\n\tFTRACE_START_FUNC_RET = 8,\n\tFTRACE_STOP_FUNC_RET = 16,\n\tFTRACE_MAY_SLEEP = 32,\n};\n\nenum {\n\tFTRACE_UPDATE_IGNORE = 0,\n\tFTRACE_UPDATE_MAKE_CALL = 1,\n\tFTRACE_UPDATE_MODIFY_CALL = 2,\n\tFTRACE_UPDATE_MAKE_NOP = 3,\n};\n\nenum {\n\tFUSE_I_ADVISE_RDPLUS = 0,\n\tFUSE_I_INIT_RDPLUS = 1,\n\tFUSE_I_SIZE_UNSTABLE = 2,\n\tFUSE_I_BAD = 3,\n\tFUSE_I_BTIME = 4,\n\tFUSE_I_CACHE_IO_MODE = 5,\n\tFUSE_I_EXCLUSIVE = 6,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tGATE_INTERRUPT = 14,\n\tGATE_TRAP = 15,\n\tGATE_CALL = 12,\n\tGATE_TASK = 5,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tGUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0,\n\tGUC_CAPTURE_LIST_CLASS_VIDEO = 1,\n\tGUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2,\n\tGUC_CAPTURE_LIST_CLASS_BLITTER = 3,\n\tGUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4,\n};\n\nenum {\n\tGUC_CAPTURE_LIST_INDEX_PF = 0,\n\tGUC_CAPTURE_LIST_INDEX_VF = 1,\n\tGUC_CAPTURE_LIST_INDEX_MAX = 2,\n};\n\nenum {\n\tGUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 8193,\n\tGUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 8194,\n\tGUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 8195,\n\tGUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 8196,\n\tGUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 8197,\n\tGUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,\n};\n\nenum {\n\tGUC_LOG_SECTIONS_CRASH = 0,\n\tGUC_LOG_SECTIONS_DEBUG = 1,\n\tGUC_LOG_SECTIONS_CAPTURE = 2,\n\tGUC_LOG_SECTIONS_LIMIT = 3,\n};\n\nenum {\n\tGUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD = 4097,\n};\n\nenum {\n\tGUC_WORKAROUND_KLV_SERIALIZED_RA_MODE = 36865,\n\tGUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED = 36866,\n\tGUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 36870,\n};\n\nenum {\n\tHAS_GLOBAL_MOCS = 1,\n\tHAS_ENGINE_MOCS = 2,\n\tHAS_RENDER_L3CC = 4,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHDA_CTL_WIDGET_VOL = 0,\n\tHDA_CTL_WIDGET_MUTE = 1,\n\tHDA_CTL_BIND_MUTE = 2,\n};\n\nenum {\n\tHDA_DEV_CORE = 0,\n\tHDA_DEV_LEGACY = 1,\n\tHDA_DEV_ASOC = 2,\n};\n\nenum {\n\tHDA_DIG_NONE = 0,\n\tHDA_DIG_EXCLUSIVE = 1,\n\tHDA_DIG_ANALOG_DUP = 2,\n};\n\nenum {\n\tHDA_FIXUP_ACT_PRE_PROBE = 0,\n\tHDA_FIXUP_ACT_PROBE = 1,\n\tHDA_FIXUP_ACT_INIT = 2,\n\tHDA_FIXUP_ACT_BUILD = 3,\n\tHDA_FIXUP_ACT_FREE = 4,\n};\n\nenum {\n\tHDA_FIXUP_INVALID = 0,\n\tHDA_FIXUP_PINS = 1,\n\tHDA_FIXUP_VERBS = 2,\n\tHDA_FIXUP_FUNC = 3,\n\tHDA_FIXUP_PINCTLS = 4,\n};\n\nenum {\n\tHDA_FRONT = 0,\n\tHDA_REAR = 1,\n\tHDA_CLFE = 2,\n\tHDA_SIDE = 3,\n};\n\nenum {\n\tHDA_GEN_PCM_ACT_OPEN = 0,\n\tHDA_GEN_PCM_ACT_PREPARE = 1,\n\tHDA_GEN_PCM_ACT_CLEANUP = 2,\n\tHDA_GEN_PCM_ACT_CLOSE = 3,\n};\n\nenum {\n\tHDA_HINT_STEREO_MIX_DISABLE = 0,\n\tHDA_HINT_STEREO_MIX_ENABLE = 1,\n\tHDA_HINT_STEREO_MIX_AUTO = 2,\n};\n\nenum {\n\tHDA_INPUT = 0,\n\tHDA_OUTPUT = 1,\n};\n\nenum {\n\tHDA_JACK_NOT_PRESENT = 0,\n\tHDA_JACK_PRESENT = 1,\n\tHDA_JACK_PHANTOM = 2,\n};\n\nenum {\n\tHDA_PCM_TYPE_AUDIO = 0,\n\tHDA_PCM_TYPE_SPDIF = 1,\n\tHDA_PCM_TYPE_HDMI = 2,\n\tHDA_PCM_TYPE_MODEM = 3,\n\tHDA_PCM_NTYPES = 4,\n};\n\nenum {\n\tHIBERNATION_INVALID = 0,\n\tHIBERNATION_PLATFORM = 1,\n\tHIBERNATION_SHUTDOWN = 2,\n\tHIBERNATION_REBOOT = 3,\n\tHIBERNATION_SUSPEND = 4,\n\tHIBERNATION_TEST_RESUME = 5,\n\t__HIBERNATION_AFTER_LAST = 6,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHSWEP_PCI_UNCORE_HA = 0,\n\tHSWEP_PCI_UNCORE_IMC = 1,\n\tHSWEP_PCI_UNCORE_IRP = 2,\n\tHSWEP_PCI_UNCORE_QPI = 3,\n\tHSWEP_PCI_UNCORE_R2PCIE = 4,\n\tHSWEP_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tHW_BREAKPOINT_EMPTY = 0,\n\tHW_BREAKPOINT_R = 1,\n\tHW_BREAKPOINT_W = 2,\n\tHW_BREAKPOINT_RW = 3,\n\tHW_BREAKPOINT_X = 4,\n\tHW_BREAKPOINT_INVALID = 7,\n};\n\nenum {\n\tHW_BREAKPOINT_LEN_1 = 1,\n\tHW_BREAKPOINT_LEN_2 = 2,\n\tHW_BREAKPOINT_LEN_3 = 3,\n\tHW_BREAKPOINT_LEN_4 = 4,\n\tHW_BREAKPOINT_LEN_5 = 5,\n\tHW_BREAKPOINT_LEN_6 = 6,\n\tHW_BREAKPOINT_LEN_7 = 7,\n\tHW_BREAKPOINT_LEN_8 = 8,\n};\n\nenum {\n\tI915_FENCE_FLAG_ACTIVE = 4,\n\tI915_FENCE_FLAG_PQUEUE = 5,\n\tI915_FENCE_FLAG_HOLD = 6,\n\tI915_FENCE_FLAG_INITIAL_BREADCRUMB = 7,\n\tI915_FENCE_FLAG_SIGNAL = 8,\n\tI915_FENCE_FLAG_NOPREEMPT = 9,\n\tI915_FENCE_FLAG_SENTINEL = 10,\n\tI915_FENCE_FLAG_BOOST = 11,\n\tI915_FENCE_FLAG_SUBMIT_PARALLEL = 12,\n\tI915_FENCE_FLAG_SKIP_PARALLEL = 13,\n\tI915_FENCE_FLAG_COMPOSITE = 14,\n};\n\nenum {\n\tI915_PRIORITY_MIN = -1024,\n\tI915_PRIORITY_NORMAL = 0,\n\tI915_PRIORITY_MAX = 1024,\n\tI915_PRIORITY_HEARTBEAT = 1025,\n\tI915_PRIORITY_DISPLAY = 1026,\n};\n\nenum {\n\tICHD_PCMIN = 0,\n\tICHD_PCMOUT = 1,\n\tICHD_MIC = 2,\n\tICHD_MIC2 = 3,\n\tICHD_PCM2IN = 4,\n\tICHD_SPBAR = 5,\n\tICHD_LAST = 5,\n};\n\nenum {\n\tICH_REG_ALI_SCR = 0,\n\tICH_REG_ALI_SSR = 4,\n\tICH_REG_ALI_DMACR = 8,\n\tICH_REG_ALI_FIFOCR1 = 12,\n\tICH_REG_ALI_INTERFACECR = 16,\n\tICH_REG_ALI_INTERRUPTCR = 20,\n\tICH_REG_ALI_INTERRUPTSR = 24,\n\tICH_REG_ALI_FIFOCR2 = 28,\n\tICH_REG_ALI_CPR = 32,\n\tICH_REG_ALI_CPR_ADDR = 34,\n\tICH_REG_ALI_SPR = 36,\n\tICH_REG_ALI_SPR_ADDR = 38,\n\tICH_REG_ALI_FIFOCR3 = 44,\n\tICH_REG_ALI_TTSR = 48,\n\tICH_REG_ALI_RTSR = 52,\n\tICH_REG_ALI_CSPSR = 56,\n\tICH_REG_ALI_CAS = 60,\n\tICH_REG_ALI_HWVOL = 240,\n\tICH_REG_ALI_I2SCR = 244,\n\tICH_REG_ALI_SPDIFCSR = 248,\n\tICH_REG_ALI_SPDIFICS = 252,\n};\n\nenum {\n\tICH_REG_OFF_BDBAR = 0,\n\tICH_REG_OFF_CIV = 4,\n\tICH_REG_OFF_LVI = 5,\n\tICH_REG_OFF_SR = 6,\n\tICH_REG_OFF_PICB = 8,\n\tICH_REG_OFF_PIV = 10,\n\tICH_REG_OFF_CR = 11,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tICX_PCIE1_PMON_ID = 0,\n\tICX_PCIE2_PMON_ID = 1,\n\tICX_PCIE3_PMON_ID = 2,\n\tICX_PCIE4_PMON_ID = 3,\n\tICX_PCIE5_PMON_ID = 4,\n\tICX_CBDMA_DMI_PMON_ID = 5,\n};\n\nenum {\n\tICX_PCI_UNCORE_M2M = 0,\n\tICX_PCI_UNCORE_UPI = 1,\n\tICX_PCI_UNCORE_M3UPI = 2,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_ACT_NONE = -1,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nenum {\n\tIIO_TOPOLOGY_TYPE = 0,\n\tUPI_TOPOLOGY_TYPE = 1,\n\tTOPOLOGY_MAX = 2,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINPUT_PIN_ATTR_UNUSED = 0,\n\tINPUT_PIN_ATTR_INT = 1,\n\tINPUT_PIN_ATTR_DOCK = 2,\n\tINPUT_PIN_ATTR_NORMAL = 3,\n\tINPUT_PIN_ATTR_REAR = 4,\n\tINPUT_PIN_ATTR_FRONT = 5,\n\tINPUT_PIN_ATTR_LAST = 5,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINTEL_ADVANCED_CONTEXT = 0,\n\tINTEL_LEGACY_32B_CONTEXT = 1,\n\tINTEL_ADVANCED_AD_CONTEXT = 2,\n\tINTEL_LEGACY_64B_CONTEXT = 3,\n};\n\nenum {\n\tINTEL_CONTEXT_SCHEDULE_IN = 0,\n\tINTEL_CONTEXT_SCHEDULE_OUT = 1,\n\tINTEL_CONTEXT_SCHEDULE_PREEMPTED = 2,\n};\n\nenum {\n\tINTEL_RPS_ENABLED = 0,\n\tINTEL_RPS_ACTIVE = 1,\n\tINTEL_RPS_INTERRUPTS = 2,\n\tINTEL_RPS_TIMER = 3,\n};\n\nenum {\n\tINTERCEPT_CR0_READ = 0,\n\tINTERCEPT_CR3_READ = 3,\n\tINTERCEPT_CR4_READ = 4,\n\tINTERCEPT_CR8_READ = 8,\n\tINTERCEPT_CR0_WRITE = 16,\n\tINTERCEPT_CR3_WRITE = 19,\n\tINTERCEPT_CR4_WRITE = 20,\n\tINTERCEPT_CR8_WRITE = 24,\n\tINTERCEPT_DR0_READ = 32,\n\tINTERCEPT_DR1_READ = 33,\n\tINTERCEPT_DR2_READ = 34,\n\tINTERCEPT_DR3_READ = 35,\n\tINTERCEPT_DR4_READ = 36,\n\tINTERCEPT_DR5_READ = 37,\n\tINTERCEPT_DR6_READ = 38,\n\tINTERCEPT_DR7_READ = 39,\n\tINTERCEPT_DR0_WRITE = 48,\n\tINTERCEPT_DR1_WRITE = 49,\n\tINTERCEPT_DR2_WRITE = 50,\n\tINTERCEPT_DR3_WRITE = 51,\n\tINTERCEPT_DR4_WRITE = 52,\n\tINTERCEPT_DR5_WRITE = 53,\n\tINTERCEPT_DR6_WRITE = 54,\n\tINTERCEPT_DR7_WRITE = 55,\n\tINTERCEPT_EXCEPTION_OFFSET = 64,\n\tINTERCEPT_INTR = 96,\n\tINTERCEPT_NMI = 97,\n\tINTERCEPT_SMI = 98,\n\tINTERCEPT_INIT = 99,\n\tINTERCEPT_VINTR = 100,\n\tINTERCEPT_SELECTIVE_CR0 = 101,\n\tINTERCEPT_STORE_IDTR = 102,\n\tINTERCEPT_STORE_GDTR = 103,\n\tINTERCEPT_STORE_LDTR = 104,\n\tINTERCEPT_STORE_TR = 105,\n\tINTERCEPT_LOAD_IDTR = 106,\n\tINTERCEPT_LOAD_GDTR = 107,\n\tINTERCEPT_LOAD_LDTR = 108,\n\tINTERCEPT_LOAD_TR = 109,\n\tINTERCEPT_RDTSC = 110,\n\tINTERCEPT_RDPMC = 111,\n\tINTERCEPT_PUSHF = 112,\n\tINTERCEPT_POPF = 113,\n\tINTERCEPT_CPUID = 114,\n\tINTERCEPT_RSM = 115,\n\tINTERCEPT_IRET = 116,\n\tINTERCEPT_INTn = 117,\n\tINTERCEPT_INVD = 118,\n\tINTERCEPT_PAUSE = 119,\n\tINTERCEPT_HLT = 120,\n\tINTERCEPT_INVLPG = 121,\n\tINTERCEPT_INVLPGA = 122,\n\tINTERCEPT_IOIO_PROT = 123,\n\tINTERCEPT_MSR_PROT = 124,\n\tINTERCEPT_TASK_SWITCH = 125,\n\tINTERCEPT_FERR_FREEZE = 126,\n\tINTERCEPT_SHUTDOWN = 127,\n\tINTERCEPT_VMRUN = 128,\n\tINTERCEPT_VMMCALL = 129,\n\tINTERCEPT_VMLOAD = 130,\n\tINTERCEPT_VMSAVE = 131,\n\tINTERCEPT_STGI = 132,\n\tINTERCEPT_CLGI = 133,\n\tINTERCEPT_SKINIT = 134,\n\tINTERCEPT_RDTSCP = 135,\n\tINTERCEPT_ICEBP = 136,\n\tINTERCEPT_WBINVD = 137,\n\tINTERCEPT_MONITOR = 138,\n\tINTERCEPT_MWAIT = 139,\n\tINTERCEPT_MWAIT_COND = 140,\n\tINTERCEPT_XSETBV = 141,\n\tINTERCEPT_RDPRU = 142,\n\tTRAP_EFER_WRITE = 143,\n\tTRAP_CR0_WRITE = 144,\n\tTRAP_CR1_WRITE = 145,\n\tTRAP_CR2_WRITE = 146,\n\tTRAP_CR3_WRITE = 147,\n\tTRAP_CR4_WRITE = 148,\n\tTRAP_CR5_WRITE = 149,\n\tTRAP_CR6_WRITE = 150,\n\tTRAP_CR7_WRITE = 151,\n\tTRAP_CR8_WRITE = 152,\n\tINTERCEPT_INVLPGB = 160,\n\tINTERCEPT_INVLPGB_ILLEGAL = 161,\n\tINTERCEPT_INVPCID = 162,\n\tINTERCEPT_MCOMMIT = 163,\n\tINTERCEPT_TLBSYNC = 164,\n\tINTERCEPT_BUSLOCK = 165,\n\tINTERCEPT_IDLE_HLT = 166,\n};\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOMMU_PASID_ARRAY_DOMAIN = 0,\n\tIOMMU_PASID_ARRAY_HANDLE = 1,\n};\n\nenum {\n\tIOMMU_SET_DOMAIN_MUST_SUCCEED = 1,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORES_MAP_SYSTEM_RAM = 1,\n\tIORES_MAP_ENCRYPTED = 2,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPMRA_CREPORT_UNSPEC = 0,\n\tIPMRA_CREPORT_MSGTYPE = 1,\n\tIPMRA_CREPORT_VIF_ID = 2,\n\tIPMRA_CREPORT_SRC_ADDR = 3,\n\tIPMRA_CREPORT_DST_ADDR = 4,\n\tIPMRA_CREPORT_PKT = 5,\n\tIPMRA_CREPORT_TABLE = 6,\n\t__IPMRA_CREPORT_MAX = 7,\n};\n\nenum {\n\tIPMRA_TABLE_UNSPEC = 0,\n\tIPMRA_TABLE_ID = 1,\n\tIPMRA_TABLE_CACHE_RES_QUEUE_LEN = 2,\n\tIPMRA_TABLE_MROUTE_REG_VIF_NUM = 3,\n\tIPMRA_TABLE_MROUTE_DO_ASSERT = 4,\n\tIPMRA_TABLE_MROUTE_DO_PIM = 5,\n\tIPMRA_TABLE_VIFS = 6,\n\tIPMRA_TABLE_MROUTE_DO_WRVIFWHOLE = 7,\n\t__IPMRA_TABLE_MAX = 8,\n};\n\nenum {\n\tIPMRA_VIFA_UNSPEC = 0,\n\tIPMRA_VIFA_IFINDEX = 1,\n\tIPMRA_VIFA_VIF_ID = 2,\n\tIPMRA_VIFA_FLAGS = 3,\n\tIPMRA_VIFA_BYTES_IN = 4,\n\tIPMRA_VIFA_BYTES_OUT = 5,\n\tIPMRA_VIFA_PACKETS_IN = 6,\n\tIPMRA_VIFA_PACKETS_OUT = 7,\n\tIPMRA_VIFA_LOCAL_ADDR = 8,\n\tIPMRA_VIFA_REMOTE_ADDR = 9,\n\tIPMRA_VIFA_PAD = 10,\n\t__IPMRA_VIFA_MAX = 11,\n};\n\nenum {\n\tIPMRA_VIF_UNSPEC = 0,\n\tIPMRA_VIF = 1,\n\t__IPMRA_VIF_MAX = 2,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_REMAP_XAPIC_MODE = 0,\n\tIRQ_REMAP_X2APIC_MODE = 1,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tIVBEP_PCI_UNCORE_HA = 0,\n\tIVBEP_PCI_UNCORE_IMC = 1,\n\tIVBEP_PCI_UNCORE_IRP = 2,\n\tIVBEP_PCI_UNCORE_QPI = 3,\n\tIVBEP_PCI_UNCORE_R2PCIE = 4,\n\tIVBEP_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tI_LCOEF_RBPS = 0,\n\tI_LCOEF_RSEQIOPS = 1,\n\tI_LCOEF_RRANDIOPS = 2,\n\tI_LCOEF_WBPS = 3,\n\tI_LCOEF_WSEQIOPS = 4,\n\tI_LCOEF_WRANDIOPS = 5,\n\tNR_I_LCOEFS = 6,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKNL_PCI_UNCORE_MC_UCLK = 0,\n\tKNL_PCI_UNCORE_MC_DCLK = 1,\n\tKNL_PCI_UNCORE_EDC_UCLK = 2,\n\tKNL_PCI_UNCORE_EDC_ECLK = 3,\n\tKNL_PCI_UNCORE_M2PCIE = 4,\n\tKNL_PCI_UNCORE_IRP = 5,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKVM_DEBUGREG_BP_ENABLED = 1,\n\tKVM_DEBUGREG_WONT_EXIT = 2,\n\tKVM_DEBUGREG_AUTO_SWITCH = 4,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLBR_FORMAT_32 = 0,\n\tLBR_FORMAT_LIP = 1,\n\tLBR_FORMAT_EIP = 2,\n\tLBR_FORMAT_EIP_FLAGS = 3,\n\tLBR_FORMAT_EIP_FLAGS2 = 4,\n\tLBR_FORMAT_INFO = 5,\n\tLBR_FORMAT_TIME = 6,\n\tLBR_FORMAT_INFO2 = 7,\n\tLBR_FORMAT_MAX_KNOWN = 7,\n};\n\nenum {\n\tLBR_NONE = 0,\n\tLBR_VALID = 1,\n};\n\nenum {\n\tLCOEF_RPAGE = 0,\n\tLCOEF_RSEQIO = 1,\n\tLCOEF_RRANDIO = 2,\n\tLCOEF_WPAGE = 3,\n\tLCOEF_WSEQIO = 4,\n\tLCOEF_WRANDIO = 5,\n\tNR_LCOEFS = 6,\n};\n\nenum {\n\tLDISC_SEM_NORMAL = 0,\n\tLDISC_SEM_OTHER = 1,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = -1,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_FUA = 512,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_NCQ_SEND_RECV = 2048,\n\tATA_DFLAG_NCQ_PRIO = 4096,\n\tATA_DFLAG_CDL = 8192,\n\tATA_DFLAG_CFG_MASK = 16383,\n\tATA_DFLAG_PIO = 16384,\n\tATA_DFLAG_NCQ_OFF = 32768,\n\tATA_DFLAG_SLEEPING = 65536,\n\tATA_DFLAG_DUBIOUS_XFER = 131072,\n\tATA_DFLAG_NO_UNLOAD = 262144,\n\tATA_DFLAG_UNLOCK_HPA = 524288,\n\tATA_DFLAG_INIT_MASK = 1048575,\n\tATA_DFLAG_NCQ_PRIO_ENABLED = 1048576,\n\tATA_DFLAG_CDL_ENABLED = 2097152,\n\tATA_DFLAG_RESUMING = 4194304,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_FEATURES_MASK = 201341696,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DEBOUNCE_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_RESUMING = 65536,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_RTF_FILLED = 4,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_HAS_CDL = 256,\n\tATA_QCFLAG_EH = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_QCFLAG_EH_SUCCESS_CMD = 524288,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_HOST_NO_PART = 16,\n\tATA_HOST_NO_SSC = 32,\n\tATA_HOST_NO_DEVSLP = 64,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 10000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_GET_SUCCESS_SENSE = 64,\n\tATA_EH_SET_ACTIVE = 128,\n\tATA_EH_PERDEV_MASK = 225,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_PRINT_QUIRKS = 2097152,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum {\n\tLINK_CAPA_10HD = 0,\n\tLINK_CAPA_10FD = 1,\n\tLINK_CAPA_100HD = 2,\n\tLINK_CAPA_100FD = 3,\n\tLINK_CAPA_1000HD = 4,\n\tLINK_CAPA_1000FD = 5,\n\tLINK_CAPA_2500FD = 6,\n\tLINK_CAPA_5000FD = 7,\n\tLINK_CAPA_10000FD = 8,\n\tLINK_CAPA_20000FD = 9,\n\tLINK_CAPA_25000FD = 10,\n\tLINK_CAPA_40000FD = 11,\n\tLINK_CAPA_50000FD = 12,\n\tLINK_CAPA_56000FD = 13,\n\tLINK_CAPA_80000FD = 14,\n\tLINK_CAPA_100000FD = 15,\n\tLINK_CAPA_200000FD = 16,\n\tLINK_CAPA_400000FD = 17,\n\tLINK_CAPA_800000FD = 18,\n\tLINK_CAPA_1600000FD = 19,\n\t__LINK_CAPA_MAX = 20,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLOCKF_ENABLED_IRQ = 68,\n\tLOCKF_USED_IN_IRQ = 17,\n\tLOCKF_ENABLED_IRQ_READ = 136,\n\tLOCKF_USED_IN_IRQ_READ = 34,\n};\n\nenum {\n\tLOCKF_USED_IN_HARDIRQ = 1,\n\tLOCKF_USED_IN_HARDIRQ_READ = 2,\n\tLOCKF_ENABLED_HARDIRQ = 4,\n\tLOCKF_ENABLED_HARDIRQ_READ = 8,\n\tLOCKF_USED_IN_SOFTIRQ = 16,\n\tLOCKF_USED_IN_SOFTIRQ_READ = 32,\n\tLOCKF_ENABLED_SOFTIRQ = 64,\n\tLOCKF_ENABLED_SOFTIRQ_READ = 128,\n\tLOCKF_USED = 256,\n\tLOCKF_USED_READ = 512,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n\tLo_deleting = 3,\n};\n\nenum {\n\tMATCH_MTR = 0,\n\tMATCH_MEQ = 1,\n\tMATCH_MLE = 2,\n\tMATCH_MLT = 3,\n\tMATCH_MGE = 4,\n\tMATCH_MGT = 5,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMD_RESYNC_NONE = 0,\n\tMD_RESYNC_YIELDED = 1,\n\tMD_RESYNC_DELAYED = 2,\n\tMD_RESYNC_ACTIVE = 3,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMMAP_ON_MEMORY_DISABLE = 0,\n\tMEMMAP_ON_MEMORY_ENABLE = 1,\n\tMEMMAP_ON_MEMORY_FORCE = 2,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMFC_STATIC = 1,\n\tMFC_OFFLOAD = 2,\n};\n\nenum {\n\tMILLION = 1000000,\n\tMIN_PERIOD = 1000,\n\tMAX_PERIOD = 1000000,\n\tMARGIN_MIN_PCT = 10,\n\tMARGIN_LOW_PCT = 20,\n\tMARGIN_TARGET_PCT = 50,\n\tINUSE_ADJ_STEP_PCT = 25,\n\tTIMER_SLACK_PCT = 1,\n\tWEIGHT_ONE = 65536,\n};\n\nenum {\n\tMIPI_DCS_NOP = 0,\n\tMIPI_DCS_SOFT_RESET = 1,\n\tMIPI_DCS_GET_COMPRESSION_MODE = 3,\n\tMIPI_DCS_GET_DISPLAY_ID = 4,\n\tMIPI_DCS_GET_ERROR_COUNT_ON_DSI = 5,\n\tMIPI_DCS_GET_RED_CHANNEL = 6,\n\tMIPI_DCS_GET_GREEN_CHANNEL = 7,\n\tMIPI_DCS_GET_BLUE_CHANNEL = 8,\n\tMIPI_DCS_GET_DISPLAY_STATUS = 9,\n\tMIPI_DCS_GET_POWER_MODE = 10,\n\tMIPI_DCS_GET_ADDRESS_MODE = 11,\n\tMIPI_DCS_GET_PIXEL_FORMAT = 12,\n\tMIPI_DCS_GET_DISPLAY_MODE = 13,\n\tMIPI_DCS_GET_SIGNAL_MODE = 14,\n\tMIPI_DCS_GET_DIAGNOSTIC_RESULT = 15,\n\tMIPI_DCS_ENTER_SLEEP_MODE = 16,\n\tMIPI_DCS_EXIT_SLEEP_MODE = 17,\n\tMIPI_DCS_ENTER_PARTIAL_MODE = 18,\n\tMIPI_DCS_ENTER_NORMAL_MODE = 19,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 20,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_CT = 21,\n\tMIPI_DCS_EXIT_INVERT_MODE = 32,\n\tMIPI_DCS_ENTER_INVERT_MODE = 33,\n\tMIPI_DCS_SET_GAMMA_CURVE = 38,\n\tMIPI_DCS_SET_DISPLAY_OFF = 40,\n\tMIPI_DCS_SET_DISPLAY_ON = 41,\n\tMIPI_DCS_SET_COLUMN_ADDRESS = 42,\n\tMIPI_DCS_SET_PAGE_ADDRESS = 43,\n\tMIPI_DCS_WRITE_MEMORY_START = 44,\n\tMIPI_DCS_WRITE_LUT = 45,\n\tMIPI_DCS_READ_MEMORY_START = 46,\n\tMIPI_DCS_SET_PARTIAL_ROWS = 48,\n\tMIPI_DCS_SET_PARTIAL_COLUMNS = 49,\n\tMIPI_DCS_SET_SCROLL_AREA = 51,\n\tMIPI_DCS_SET_TEAR_OFF = 52,\n\tMIPI_DCS_SET_TEAR_ON = 53,\n\tMIPI_DCS_SET_ADDRESS_MODE = 54,\n\tMIPI_DCS_SET_SCROLL_START = 55,\n\tMIPI_DCS_EXIT_IDLE_MODE = 56,\n\tMIPI_DCS_ENTER_IDLE_MODE = 57,\n\tMIPI_DCS_SET_PIXEL_FORMAT = 58,\n\tMIPI_DCS_WRITE_MEMORY_CONTINUE = 60,\n\tMIPI_DCS_SET_3D_CONTROL = 61,\n\tMIPI_DCS_READ_MEMORY_CONTINUE = 62,\n\tMIPI_DCS_GET_3D_CONTROL = 63,\n\tMIPI_DCS_SET_VSYNC_TIMING = 64,\n\tMIPI_DCS_SET_TEAR_SCANLINE = 68,\n\tMIPI_DCS_GET_SCANLINE = 69,\n\tMIPI_DCS_SET_DISPLAY_BRIGHTNESS = 81,\n\tMIPI_DCS_GET_DISPLAY_BRIGHTNESS = 82,\n\tMIPI_DCS_WRITE_CONTROL_DISPLAY = 83,\n\tMIPI_DCS_GET_CONTROL_DISPLAY = 84,\n\tMIPI_DCS_WRITE_POWER_SAVE = 85,\n\tMIPI_DCS_GET_POWER_SAVE = 86,\n\tMIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 94,\n\tMIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 95,\n\tMIPI_DCS_READ_DDB_START = 161,\n\tMIPI_DCS_READ_PPS_START = 162,\n\tMIPI_DCS_READ_DDB_CONTINUE = 168,\n\tMIPI_DCS_READ_PPS_CONTINUE = 169,\n};\n\nenum {\n\tMIPI_DSI_V_SYNC_START = 1,\n\tMIPI_DSI_V_SYNC_END = 17,\n\tMIPI_DSI_H_SYNC_START = 33,\n\tMIPI_DSI_H_SYNC_END = 49,\n\tMIPI_DSI_COMPRESSION_MODE = 7,\n\tMIPI_DSI_END_OF_TRANSMISSION = 8,\n\tMIPI_DSI_COLOR_MODE_OFF = 2,\n\tMIPI_DSI_COLOR_MODE_ON = 18,\n\tMIPI_DSI_SHUTDOWN_PERIPHERAL = 34,\n\tMIPI_DSI_TURN_ON_PERIPHERAL = 50,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 3,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 19,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 35,\n\tMIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 4,\n\tMIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 20,\n\tMIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 36,\n\tMIPI_DSI_DCS_SHORT_WRITE = 5,\n\tMIPI_DSI_DCS_SHORT_WRITE_PARAM = 21,\n\tMIPI_DSI_DCS_READ = 6,\n\tMIPI_DSI_EXECUTE_QUEUE = 22,\n\tMIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 55,\n\tMIPI_DSI_NULL_PACKET = 9,\n\tMIPI_DSI_BLANKING_PACKET = 25,\n\tMIPI_DSI_GENERIC_LONG_WRITE = 41,\n\tMIPI_DSI_DCS_LONG_WRITE = 57,\n\tMIPI_DSI_PICTURE_PARAMETER_SET = 10,\n\tMIPI_DSI_COMPRESSED_PIXEL_STREAM = 11,\n\tMIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 12,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 28,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 44,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_30 = 13,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_36 = 29,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 61,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_16 = 14,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_18 = 30,\n\tMIPI_DSI_PIXEL_STREAM_3BYTE_18 = 46,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_24 = 62,\n};\n\nenum {\n\tMIPI_RESET_1 = 0,\n\tMIPI_AVDD_EN_1 = 1,\n\tMIPI_BKLT_EN_1 = 2,\n\tMIPI_AVEE_EN_1 = 3,\n\tMIPI_VIO_EN_1 = 4,\n\tMIPI_RESET_2 = 5,\n\tMIPI_AVDD_EN_2 = 6,\n\tMIPI_BKLT_EN_2 = 7,\n\tMIPI_AVEE_EN_2 = 8,\n\tMIPI_VIO_EN_2 = 9,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMMOP_OFFLINE = 0,\n\tMMOP_ONLINE = 1,\n\tMMOP_ONLINE_KERNEL = 2,\n\tMMOP_ONLINE_MOVABLE = 3,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMODE_640x480 = 0,\n\tMODE_800x600 = 1,\n\tMODE_1024x768 = 2,\n};\n\nenum {\n\tMOXA_SUPP_RS232 = 1,\n\tMOXA_SUPP_RS422 = 2,\n\tMOXA_SUPP_RS485 = 4,\n};\n\nenum {\n\tMPOL_DEFAULT = 0,\n\tMPOL_PREFERRED = 1,\n\tMPOL_BIND = 2,\n\tMPOL_INTERLEAVE = 3,\n\tMPOL_LOCAL = 4,\n\tMPOL_PREFERRED_MANY = 5,\n\tMPOL_WEIGHTED_INTERLEAVE = 6,\n\tMPOL_MAX = 7,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tM_I17 = 0,\n\tM_I20 = 1,\n\tM_I20_SR = 2,\n\tM_I24 = 3,\n\tM_I24_8_1 = 4,\n\tM_I24_10_1 = 5,\n\tM_I27_11_1 = 6,\n\tM_MINI = 7,\n\tM_MINI_3_1 = 8,\n\tM_MINI_4_1 = 9,\n\tM_MB = 10,\n\tM_MB_2 = 11,\n\tM_MB_3 = 12,\n\tM_MB_5_1 = 13,\n\tM_MB_6_1 = 14,\n\tM_MB_7_1 = 15,\n\tM_MB_SR = 16,\n\tM_MBA = 17,\n\tM_MBA_3 = 18,\n\tM_MBP = 19,\n\tM_MBP_2 = 20,\n\tM_MBP_2_2 = 21,\n\tM_MBP_SR = 22,\n\tM_MBP_4 = 23,\n\tM_MBP_5_1 = 24,\n\tM_MBP_5_2 = 25,\n\tM_MBP_5_3 = 26,\n\tM_MBP_6_1 = 27,\n\tM_MBP_6_2 = 28,\n\tM_MBP_7_1 = 29,\n\tM_MBP_8_2 = 30,\n\tM_UNKNOWN = 31,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDD_UNARMED = 1,\n\tNDD_LOCKED = 2,\n\tNDD_SECURITY_OVERWRITE = 3,\n\tNDD_WORK_PENDING = 4,\n\tNDD_LABELING = 6,\n\tNDD_INCOHERENT = 7,\n\tNDD_REGISTER_SYNC = 8,\n\tND_IOCTL_MAX_BUFLEN = 4194304,\n\tND_CMD_MAX_ELEM = 5,\n\tND_CMD_MAX_ENVELOPE = 256,\n\tND_MAX_MAPPINGS = 32,\n\tND_REGION_PAGEMAP = 0,\n\tND_REGION_PERSIST_CACHE = 1,\n\tND_REGION_PERSIST_MEMCTRL = 2,\n\tND_REGION_ASYNC = 3,\n\tND_REGION_CXL = 4,\n\tDPA_RESOURCE_ADJUSTED = 1,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNHLT_CONFIG_TYPE_GENERIC = 0,\n\tNHLT_CONFIG_TYPE_MIC_ARRAY = 1,\n};\n\nenum {\n\tNHLT_MIC_ARRAY_2CH_SMALL = 10,\n\tNHLT_MIC_ARRAY_2CH_BIG = 11,\n\tNHLT_MIC_ARRAY_4CH_1ST_GEOM = 12,\n\tNHLT_MIC_ARRAY_4CH_L_SHAPED = 13,\n\tNHLT_MIC_ARRAY_4CH_2ND_GEOM = 14,\n\tNHLT_MIC_ARRAY_VENDOR_DEFINED = 15,\n};\n\nenum {\n\tNID_PATH_VOL_CTL = 0,\n\tNID_PATH_MUTE_CTL = 1,\n\tNID_PATH_BOOST_CTL = 2,\n\tNID_PATH_NUM_CTLS = 3,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNMI_LOCAL = 0,\n\tNMI_UNKNOWN = 1,\n\tNMI_SERR = 2,\n\tNMI_IO_CHECK = 3,\n\tNMI_MAX = 4,\n};\n\nenum {\n\tNONE_FORCE_HPET_RESUME = 0,\n\tOLD_ICH_FORCE_HPET_RESUME = 1,\n\tICH_FORCE_HPET_RESUME = 2,\n\tVT8237_FORCE_HPET_RESUME = 3,\n\tNVIDIA_FORCE_HPET_RESUME = 4,\n\tATI_FORCE_HPET_RESUME = 5,\n};\n\nenum {\n\tNONE_SVM_INSTR = 0,\n\tSVM_INSTR_VMRUN = 1,\n\tSVM_INSTR_VMLOAD = 2,\n\tSVM_INSTR_VMSAVE = 3,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 66,\n};\n\nenum {\n\tNVD_PCMIN = 0,\n\tNVD_PCMOUT = 1,\n\tNVD_MIC = 2,\n\tNVD_SPBAR = 3,\n\tNVD_LAST = 3,\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n\tNVMEM_LAYOUT_ADD = 5,\n\tNVMEM_LAYOUT_REMOVE = 6,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tOD_NORMAL_SAMPLE = 0,\n\tOD_SUB_SAMPLE = 1,\n};\n\nenum {\n\tONLINE_POLICY_CONTIG_ZONES = 0,\n\tONLINE_POLICY_AUTO_MOVABLE = 1,\n};\n\nenum {\n\tOPTIMIZER_ST_IDLE = 0,\n\tOPTIMIZER_ST_KICKED = 1,\n\tOPTIMIZER_ST_FLUSHING = 2,\n};\n\nenum {\n\tOPT_DAX = 0,\n\tOPT_DAX_ENUM = 1,\n};\n\nenum {\n\tOPT_SOURCE = 0,\n\tOPT_SUBTYPE = 1,\n\tOPT_FD = 2,\n\tOPT_ROOTMODE = 3,\n\tOPT_USER_ID = 4,\n\tOPT_GROUP_ID = 5,\n\tOPT_DEFAULT_PERMISSIONS = 6,\n\tOPT_ALLOW_OTHER = 7,\n\tOPT_MAX_READ = 8,\n\tOPT_BLKSIZE = 9,\n\tOPT_ERR = 10,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOUTSIDE_GUEST_MODE = 0,\n\tIN_GUEST_MODE = 1,\n\tEXITING_GUEST_MODE = 2,\n\tREADING_SHADOW_PAGE_TABLES = 3,\n};\n\nenum {\n\tOVERRIDE_NONE = 0,\n\tOVERRIDE_BASE = 1,\n\tOVERRIDE_STRIDE = 2,\n\tOVERRIDE_HEIGHT = 4,\n\tOVERRIDE_WIDTH = 8,\n};\n\nenum {\n\tOVL_REDIRECT_OFF = 0,\n\tOVL_REDIRECT_FOLLOW = 1,\n\tOVL_REDIRECT_NOFOLLOW = 2,\n\tOVL_REDIRECT_ON = 3,\n};\n\nenum {\n\tOVL_UUID_OFF = 0,\n\tOVL_UUID_NULL = 1,\n\tOVL_UUID_AUTO = 2,\n\tOVL_UUID_ON = 3,\n};\n\nenum {\n\tOVL_VERITY_OFF = 0,\n\tOVL_VERITY_ON = 1,\n\tOVL_VERITY_REQUIRE = 2,\n};\n\nenum {\n\tOVL_XINO_OFF = 0,\n\tOVL_XINO_AUTO = 1,\n\tOVL_XINO_ON = 2,\n};\n\nenum {\n\tOpt_block = 0,\n\tOpt_check = 1,\n\tOpt_cruft = 2,\n\tOpt_gid = 3,\n\tOpt_ignore = 4,\n\tOpt_iocharset = 5,\n\tOpt_map = 6,\n\tOpt_mode = 7,\n\tOpt_nojoliet = 8,\n\tOpt_norock = 9,\n\tOpt_sb = 10,\n\tOpt_session = 11,\n\tOpt_uid = 12,\n\tOpt_unhide = 13,\n\tOpt_utf8 = 14,\n\tOpt_err = 15,\n\tOpt_nocompress = 16,\n\tOpt_hide = 17,\n\tOpt_showassoc = 18,\n\tOpt_dmode = 19,\n\tOpt_overriderockperm = 20,\n};\n\nenum {\n\tOpt_err___2 = 0,\n\tOpt_enc = 1,\n\tOpt_hash = 2,\n};\n\nenum {\n\tOpt_source = 0,\n\tOpt_debug = 1,\n\tOpt_dfltuid = 2,\n\tOpt_dfltgid = 3,\n\tOpt_afid = 4,\n\tOpt_uname = 5,\n\tOpt_remotename = 6,\n\tOpt_cache = 7,\n\tOpt_cachetag = 8,\n\tOpt_nodevmap = 9,\n\tOpt_noxattr = 10,\n\tOpt_directio = 11,\n\tOpt_ignoreqv = 12,\n\tOpt_access = 13,\n\tOpt_posixacl = 14,\n\tOpt_locktimeout = 15,\n\tOpt_msize = 16,\n\tOpt_trans = 17,\n\tOpt_legacy = 18,\n\tOpt_version = 19,\n\tOpt_rfdno = 20,\n\tOpt_wfdno = 21,\n\tOpt_rq_depth = 22,\n\tOpt_sq_depth = 23,\n\tOpt_timeout = 24,\n\tOpt_port = 25,\n\tOpt_privport = 26,\n};\n\nenum {\n\tOpt_uid___2 = 0,\n\tOpt_gid___2 = 1,\n\tOpt_mode___2 = 2,\n};\n\nenum {\n\tOpt_uid___3 = 0,\n\tOpt_gid___3 = 1,\n\tOpt_mode___3 = 2,\n\tOpt_source___2 = 3,\n};\n\nenum {\n\tOpt_uid___4 = 0,\n\tOpt_gid___4 = 1,\n\tOpt_mode___4 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___3 = 6,\n};\n\nenum {\n\tPAGE_REPORTING_IDLE = 0,\n\tPAGE_REPORTING_REQUESTED = 1,\n\tPAGE_REPORTING_ACTIVE = 2,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_BRIDGE_RESOURCES = 7,\n\tPCI_BRIDGE_RESOURCE_END = 10,\n\tPCI_NUM_RESOURCES = 11,\n\tDEVICE_COUNT_RESOURCE = 11,\n};\n\nenum {\n\tPCMCIA_IOPORT_0 = 0,\n\tPCMCIA_IOPORT_1 = 1,\n\tPCMCIA_IOMEM_0 = 2,\n\tPCMCIA_IOMEM_1 = 3,\n\tPCMCIA_IOMEM_2 = 4,\n\tPCMCIA_IOMEM_3 = 5,\n\tPCMCIA_NUM_RESOURCES = 6,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPERF_BR_SPEC_NA = 0,\n\tPERF_BR_SPEC_WRONG_PATH = 1,\n\tPERF_BR_NON_SPEC_CORRECT_PATH = 2,\n\tPERF_BR_SPEC_CORRECT_PATH = 3,\n\tPERF_BR_SPEC_MAX = 4,\n};\n\nenum {\n\tPERF_BR_UNKNOWN = 0,\n\tPERF_BR_COND = 1,\n\tPERF_BR_UNCOND = 2,\n\tPERF_BR_IND = 3,\n\tPERF_BR_CALL = 4,\n\tPERF_BR_IND_CALL = 5,\n\tPERF_BR_RET = 6,\n\tPERF_BR_SYSCALL = 7,\n\tPERF_BR_SYSRET = 8,\n\tPERF_BR_COND_CALL = 9,\n\tPERF_BR_COND_RET = 10,\n\tPERF_BR_ERET = 11,\n\tPERF_BR_IRQ = 12,\n\tPERF_BR_SERROR = 13,\n\tPERF_BR_NO_TX = 14,\n\tPERF_BR_EXTEND_ABI = 15,\n\tPERF_BR_MAX = 16,\n};\n\nenum {\n\tPERF_GROUP_OAG = 0,\n\tPERF_GROUP_OAM_SAMEDIA_0 = 0,\n\tPERF_GROUP_MAX = 1,\n\tPERF_GROUP_INVALID = 4294967295,\n};\n\nenum {\n\tPERF_TXN_ELISION = 1ULL,\n\tPERF_TXN_TRANSACTION = 2ULL,\n\tPERF_TXN_SYNC = 4ULL,\n\tPERF_TXN_ASYNC = 8ULL,\n\tPERF_TXN_RETRY = 16ULL,\n\tPERF_TXN_CONFLICT = 32ULL,\n\tPERF_TXN_CAPACITY_WRITE = 64ULL,\n\tPERF_TXN_CAPACITY_READ = 128ULL,\n\tPERF_TXN_MAX = 256ULL,\n\tPERF_TXN_ABORT_MASK = 18446744069414584320ULL,\n\tPERF_TXN_ABORT_SHIFT = 32ULL,\n};\n\nenum {\n\tPERF_X86_EVENT_PEBS_LDLAT = 1,\n\tPERF_X86_EVENT_PEBS_ST = 2,\n\tPERF_X86_EVENT_PEBS_ST_HSW = 4,\n\tPERF_X86_EVENT_PEBS_LD_HSW = 8,\n\tPERF_X86_EVENT_PEBS_NA_HSW = 16,\n\tPERF_X86_EVENT_EXCL = 32,\n\tPERF_X86_EVENT_DYNAMIC = 64,\n\tPERF_X86_EVENT_PEBS_CNTR = 128,\n\tPERF_X86_EVENT_EXCL_ACCT = 256,\n\tPERF_X86_EVENT_AUTO_RELOAD = 512,\n\tPERF_X86_EVENT_LARGE_PEBS = 1024,\n\tPERF_X86_EVENT_PEBS_VIA_PT = 2048,\n\tPERF_X86_EVENT_PAIR = 4096,\n\tPERF_X86_EVENT_LBR_SELECT = 8192,\n\tPERF_X86_EVENT_TOPDOWN = 16384,\n\tPERF_X86_EVENT_PEBS_STLAT = 32768,\n\tPERF_X86_EVENT_AMD_BRS = 65536,\n\tPERF_X86_EVENT_PEBS_LAT_HYBRID = 131072,\n\tPERF_X86_EVENT_NEEDS_BRANCH_STACK = 262144,\n\tPERF_X86_EVENT_BRANCH_COUNTERS = 524288,\n\tPERF_X86_EVENT_ACR = 1048576,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPIIX_IOCFG = 84,\n\tICH5_PMR = 144,\n\tICH5_PCS = 146,\n\tPIIX_SIDPR_BAR = 5,\n\tPIIX_SIDPR_LEN = 16,\n\tPIIX_SIDPR_IDX = 0,\n\tPIIX_SIDPR_DATA = 4,\n\tPIIX_FLAG_CHECKINTR = 268435456,\n\tPIIX_FLAG_SIDPR = 536870912,\n\tPIIX_PATA_FLAGS = 1,\n\tPIIX_SATA_FLAGS = 268435458,\n\tPIIX_FLAG_PIO16 = 1073741824,\n\tPIIX_80C_PRI = 48,\n\tPIIX_80C_SEC = 192,\n\tP0 = 0,\n\tP1 = 1,\n\tP2 = 2,\n\tP3 = 3,\n\tIDE = -1,\n\tNA = -2,\n\tRV = -3,\n\tPIIX_AHCI_DEVICE = 6,\n\tPIIX_HOST_BROKEN_SUSPEND = 16777216,\n};\n\nenum {\n\tPIM_TYPE_HELLO = 0,\n\tPIM_TYPE_REGISTER = 1,\n\tPIM_TYPE_REGISTER_STOP = 2,\n\tPIM_TYPE_JOIN_PRUNE = 3,\n\tPIM_TYPE_BOOTSTRAP = 4,\n\tPIM_TYPE_ASSERT = 5,\n\tPIM_TYPE_GRAFT = 6,\n\tPIM_TYPE_GRAFT_ACK = 7,\n\tPIM_TYPE_CANDIDATE_RP_ADV = 8,\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = -1,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPOS_FIX_AUTO = 0,\n\tPOS_FIX_LPIB = 1,\n\tPOS_FIX_POSBUF = 2,\n\tPOS_FIX_VIACOMBO = 3,\n\tPOS_FIX_COMBO = 4,\n\tPOS_FIX_SKL = 5,\n\tPOS_FIX_FIFO = 6,\n};\n\nenum {\n\tPOWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_LOW = 2,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_FULL = 5,\n};\n\nenum {\n\tPOWER_SUPPLY_HEALTH_UNKNOWN = 0,\n\tPOWER_SUPPLY_HEALTH_GOOD = 1,\n\tPOWER_SUPPLY_HEALTH_OVERHEAT = 2,\n\tPOWER_SUPPLY_HEALTH_DEAD = 3,\n\tPOWER_SUPPLY_HEALTH_OVERVOLTAGE = 4,\n\tPOWER_SUPPLY_HEALTH_UNDERVOLTAGE = 5,\n\tPOWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 6,\n\tPOWER_SUPPLY_HEALTH_COLD = 7,\n\tPOWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 8,\n\tPOWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 9,\n\tPOWER_SUPPLY_HEALTH_OVERCURRENT = 10,\n\tPOWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 11,\n\tPOWER_SUPPLY_HEALTH_WARM = 12,\n\tPOWER_SUPPLY_HEALTH_COOL = 13,\n\tPOWER_SUPPLY_HEALTH_HOT = 14,\n\tPOWER_SUPPLY_HEALTH_NO_BATTERY = 15,\n\tPOWER_SUPPLY_HEALTH_BLOWN_FUSE = 16,\n\tPOWER_SUPPLY_HEALTH_CELL_IMBALANCE = 17,\n};\n\nenum {\n\tPOWER_SUPPLY_SCOPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_SCOPE_SYSTEM = 1,\n\tPOWER_SUPPLY_SCOPE_DEVICE = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_STATUS_UNKNOWN = 0,\n\tPOWER_SUPPLY_STATUS_CHARGING = 1,\n\tPOWER_SUPPLY_STATUS_DISCHARGING = 2,\n\tPOWER_SUPPLY_STATUS_NOT_CHARGING = 3,\n\tPOWER_SUPPLY_STATUS_FULL = 4,\n};\n\nenum {\n\tPOWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,\n\tPOWER_SUPPLY_TECHNOLOGY_NiMH = 1,\n\tPOWER_SUPPLY_TECHNOLOGY_LION = 2,\n\tPOWER_SUPPLY_TECHNOLOGY_LIPO = 3,\n\tPOWER_SUPPLY_TECHNOLOGY_LiFe = 4,\n\tPOWER_SUPPLY_TECHNOLOGY_NiCd = 5,\n\tPOWER_SUPPLY_TECHNOLOGY_LiMn = 6,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROCMON_0_85V_DOT_0 = 0,\n\tPROCMON_0_95V_DOT_0 = 1,\n\tPROCMON_0_95V_DOT_1 = 2,\n\tPROCMON_1_05V_DOT_0 = 3,\n\tPROCMON_1_05V_DOT_1 = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tPSS = 0,\n\tPPC = 1,\n};\n\nenum {\n\tPTP_LOCK_PHYSICAL = 0,\n\tPTP_LOCK_VIRTUAL = 1,\n};\n\nenum {\n\tPT_FEAT_AMDV1_ENCRYPT_TABLES = 6,\n\tPT_FEAT_AMDV1_FORCE_COHERENCE = 7,\n};\n\nenum {\n\tPT_FEAT_VTDSS_FORCE_COHERENCE = 6,\n\tPT_FEAT_VTDSS_FORCE_WRITEABLE = 7,\n};\n\nenum {\n\tPT_FEAT_X86_64_AMD_ENCRYPT_TABLES = 6,\n};\n\nenum {\n\tPT_ITEM_WORD_SIZE = 8ULL,\n\tPT_MAX_VA_ADDRESS_LG2 = 64ULL,\n\tPT_MAX_OUTPUT_ADDRESS_LG2 = 52ULL,\n\tPT_MAX_TOP_LEVEL = 5ULL,\n\tPT_GRANULE_LG2SZ = 12ULL,\n\tPT_TABLEMEM_LG2SZ = 12ULL,\n\tPT_TOP_PHYS_MASK = 4503599627366400ULL,\n};\n\nenum {\n\tPT_MAX_OUTPUT_ADDRESS_LG2___2 = 52ULL,\n\tPT_MAX_VA_ADDRESS_LG2___2 = 57ULL,\n\tPT_ITEM_WORD_SIZE___2 = 8ULL,\n\tPT_MAX_TOP_LEVEL___2 = 4ULL,\n\tPT_GRANULE_LG2SZ___2 = 12ULL,\n\tPT_TABLEMEM_LG2SZ___2 = 12ULL,\n\tPT_TOP_PHYS_MASK___2 = 18446744073709547520ULL,\n};\n\nenum {\n\tPT_MAX_OUTPUT_ADDRESS_LG2___3 = 52ULL,\n\tPT_MAX_VA_ADDRESS_LG2___3 = 57ULL,\n\tPT_ITEM_WORD_SIZE___3 = 8ULL,\n\tPT_MAX_TOP_LEVEL___3 = 4ULL,\n\tPT_GRANULE_LG2SZ___3 = 12ULL,\n\tPT_TABLEMEM_LG2SZ___3 = 12ULL,\n\tPT_TOP_PHYS_MASK___3 = 4503599627366400ULL,\n};\n\nenum {\n\tPT_TOP_LEVEL_BITS = 3,\n\tPT_TOP_LEVEL_MASK = 7,\n};\n\nenum {\n\tPT_VADDR_MAX = 18446744073709551615ULL,\n\tPT_VADDR_MAX_LG2 = 64ULL,\n\tPT_OADDR_MAX = 18446744073709551615ULL,\n\tPT_OADDR_MAX_LG2 = 64ULL,\n};\n\nenum {\n\tPWIDX_ADC = 0,\n\tPWIDX_FRONT = 1,\n\tPWIDX_CLFE = 2,\n\tPWIDX_SURR = 3,\n\tPWIDX_MIC = 4,\n\tPWIDX_SIZE = 5,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQIF_BLIMITS_B = 0,\n\tQIF_SPACE_B = 1,\n\tQIF_ILIMITS_B = 2,\n\tQIF_INODES_B = 3,\n\tQIF_BTIME_B = 4,\n\tQIF_ITIME_B = 5,\n};\n\nenum {\n\tQI_FREE = 0,\n\tQI_IN_USE = 1,\n\tQI_DONE = 2,\n\tQI_ABORT = 3,\n};\n\nenum {\n\tQOS_ENABLE = 0,\n\tQOS_CTRL = 1,\n\tNR_QOS_CTRL_PARAMS = 2,\n};\n\nenum {\n\tQOS_RPPM = 0,\n\tQOS_RLAT = 1,\n\tQOS_WPPM = 2,\n\tQOS_WLAT = 3,\n\tQOS_MIN = 4,\n\tQOS_MAX = 5,\n\tNR_QOS_PARAMS = 6,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQUIRK_IGNORE_CHECKSUM = 0,\n};\n\nenum {\n\tQUOTA_NL_A_UNSPEC = 0,\n\tQUOTA_NL_A_QTYPE = 1,\n\tQUOTA_NL_A_EXCESS_ID = 2,\n\tQUOTA_NL_A_WARNING = 3,\n\tQUOTA_NL_A_DEV_MAJOR = 4,\n\tQUOTA_NL_A_DEV_MINOR = 5,\n\tQUOTA_NL_A_CAUSED_ID = 6,\n\tQUOTA_NL_A_PAD = 7,\n\t__QUOTA_NL_A_MAX = 8,\n};\n\nenum {\n\tQUOTA_NL_C_UNSPEC = 0,\n\tQUOTA_NL_C_WARNING = 1,\n\t__QUOTA_NL_C_MAX = 2,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tRB_ADD_STAMP_NONE = 0,\n\tRB_ADD_STAMP_EXTEND = 2,\n\tRB_ADD_STAMP_ABSOLUTE = 4,\n\tRB_ADD_STAMP_FORCE = 8,\n};\n\nenum {\n\tRB_CTX_TRANSITION = 0,\n\tRB_CTX_NMI = 1,\n\tRB_CTX_IRQ = 2,\n\tRB_CTX_SOFTIRQ = 3,\n\tRB_CTX_NORMAL = 4,\n\tRB_CTX_MAX = 5,\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tRELAY_STATS_BUF_FULL = 1,\n\tRELAY_STATS_WRT_BIG = 2,\n\tRELAY_STATS_LAST = 2,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 5000,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRES_USAGE = 0,\n\tRES_RSVD_USAGE = 1,\n\tRES_LIMIT = 2,\n\tRES_RSVD_LIMIT = 3,\n\tRES_MAX_USAGE = 4,\n\tRES_RSVD_MAX_USAGE = 5,\n\tRES_FAILCNT = 6,\n\tRES_RSVD_FAILCNT = 7,\n};\n\nenum {\n\tRET_PF_CONTINUE = 0,\n\tRET_PF_RETRY = 1,\n\tRET_PF_EMULATE = 2,\n\tRET_PF_WRITE_PROTECTED = 3,\n\tRET_PF_INVALID = 4,\n\tRET_PF_FIXED = 5,\n\tRET_PF_SPURIOUS = 6,\n};\n\nenum {\n\tRQ_WAIT_BUSY_PCT = 5,\n\tUNBUSY_THR_PCT = 75,\n\tMIN_DELAY_THR_PCT = 500,\n\tMAX_DELAY_THR_PCT = 25000,\n\tMIN_DELAY = 250,\n\tMAX_DELAY = 250000,\n\tDFGV_USAGE_PCT = 50,\n\tDFGV_PERIOD = 100000,\n\tMAX_LAGGING_PERIODS = 10,\n\tIOC_PAGE_SHIFT = 12,\n\tIOC_PAGE_SIZE = 4096,\n\tIOC_SECT_TO_PAGE_SHIFT = 3,\n\tLCOEF_RANDIO_PAGES = 4096,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tRworksched = 1,\n\tRpending = 2,\n\tWworksched = 4,\n\tWpending = 8,\n};\n\nenum {\n\tSAMPLES = 8,\n\tMIN_CHANGE = 5,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSECTION_MARKED_PRESENT_BIT = 0,\n\tSECTION_HAS_MEM_MAP_BIT = 1,\n\tSECTION_IS_ONLINE_BIT = 2,\n\tSECTION_IS_EARLY_BIT = 3,\n\tSECTION_TAINT_ZONE_DEVICE_BIT = 4,\n\tSECTION_IS_VMEMMAP_PREINIT_BIT = 5,\n\tSECTION_MAP_LAST_BIT = 6,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSKCIPHER_WALK_SLOW = 1,\n\tSKCIPHER_WALK_COPY = 2,\n\tSKCIPHER_WALK_DIFF = 4,\n\tSKCIPHER_WALK_SLEEP = 8,\n};\n\nenum {\n\tSKX_PCI_UNCORE_IMC = 0,\n\tSKX_PCI_UNCORE_M2M = 1,\n\tSKX_PCI_UNCORE_UPI = 2,\n\tSKX_PCI_UNCORE_M2PCIE = 3,\n\tSKX_PCI_UNCORE_M3UPI = 4,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSNBEP_PCI_QPI_PORT0_FILTER = 0,\n\tSNBEP_PCI_QPI_PORT1_FILTER = 1,\n\tBDX_PCI_QPI_PORT2_FILTER = 2,\n};\n\nenum {\n\tSNBEP_PCI_UNCORE_HA = 0,\n\tSNBEP_PCI_UNCORE_IMC = 1,\n\tSNBEP_PCI_UNCORE_QPI = 2,\n\tSNBEP_PCI_UNCORE_R2PCIE = 3,\n\tSNBEP_PCI_UNCORE_R3QPI = 4,\n};\n\nenum {\n\tSNB_PCI_UNCORE_IMC = 0,\n};\n\nenum {\n\tSNDRV_CHMAP_UNKNOWN = 0,\n\tSNDRV_CHMAP_NA = 1,\n\tSNDRV_CHMAP_MONO = 2,\n\tSNDRV_CHMAP_FL = 3,\n\tSNDRV_CHMAP_FR = 4,\n\tSNDRV_CHMAP_RL = 5,\n\tSNDRV_CHMAP_RR = 6,\n\tSNDRV_CHMAP_FC = 7,\n\tSNDRV_CHMAP_LFE = 8,\n\tSNDRV_CHMAP_SL = 9,\n\tSNDRV_CHMAP_SR = 10,\n\tSNDRV_CHMAP_RC = 11,\n\tSNDRV_CHMAP_FLC = 12,\n\tSNDRV_CHMAP_FRC = 13,\n\tSNDRV_CHMAP_RLC = 14,\n\tSNDRV_CHMAP_RRC = 15,\n\tSNDRV_CHMAP_FLW = 16,\n\tSNDRV_CHMAP_FRW = 17,\n\tSNDRV_CHMAP_FLH = 18,\n\tSNDRV_CHMAP_FCH = 19,\n\tSNDRV_CHMAP_FRH = 20,\n\tSNDRV_CHMAP_TC = 21,\n\tSNDRV_CHMAP_TFL = 22,\n\tSNDRV_CHMAP_TFR = 23,\n\tSNDRV_CHMAP_TFC = 24,\n\tSNDRV_CHMAP_TRL = 25,\n\tSNDRV_CHMAP_TRR = 26,\n\tSNDRV_CHMAP_TRC = 27,\n\tSNDRV_CHMAP_TFLC = 28,\n\tSNDRV_CHMAP_TFRC = 29,\n\tSNDRV_CHMAP_TSL = 30,\n\tSNDRV_CHMAP_TSR = 31,\n\tSNDRV_CHMAP_LLFE = 32,\n\tSNDRV_CHMAP_RLFE = 33,\n\tSNDRV_CHMAP_BC = 34,\n\tSNDRV_CHMAP_BLC = 35,\n\tSNDRV_CHMAP_BRC = 36,\n\tSNDRV_CHMAP_LAST = 36,\n};\n\nenum {\n\tSNDRV_CTL_IOCTL_ELEM_LIST32 = 3225965840,\n\tSNDRV_CTL_IOCTL_ELEM_INFO32 = 3239073041,\n\tSNDRV_CTL_IOCTL_ELEM_READ32 = 3267646738,\n\tSNDRV_CTL_IOCTL_ELEM_WRITE32 = 3267646739,\n\tSNDRV_CTL_IOCTL_ELEM_ADD32 = 3239073047,\n\tSNDRV_CTL_IOCTL_ELEM_REPLACE32 = 3239073048,\n};\n\nenum {\n\tSNDRV_CTL_TLV_OP_READ = 0,\n\tSNDRV_CTL_TLV_OP_WRITE = 1,\n\tSNDRV_CTL_TLV_OP_CMD = -1,\n};\n\nenum {\n\tSNDRV_HWDEP_IFACE_OPL2 = 0,\n\tSNDRV_HWDEP_IFACE_OPL3 = 1,\n\tSNDRV_HWDEP_IFACE_OPL4 = 2,\n\tSNDRV_HWDEP_IFACE_SB16CSP = 3,\n\tSNDRV_HWDEP_IFACE_EMU10K1 = 4,\n\tSNDRV_HWDEP_IFACE_YSS225 = 5,\n\tSNDRV_HWDEP_IFACE_ICS2115 = 6,\n\tSNDRV_HWDEP_IFACE_SSCAPE = 7,\n\tSNDRV_HWDEP_IFACE_VX = 8,\n\tSNDRV_HWDEP_IFACE_MIXART = 9,\n\tSNDRV_HWDEP_IFACE_USX2Y = 10,\n\tSNDRV_HWDEP_IFACE_EMUX_WAVETABLE = 11,\n\tSNDRV_HWDEP_IFACE_BLUETOOTH = 12,\n\tSNDRV_HWDEP_IFACE_USX2Y_PCM = 13,\n\tSNDRV_HWDEP_IFACE_PCXHR = 14,\n\tSNDRV_HWDEP_IFACE_SB_RC = 15,\n\tSNDRV_HWDEP_IFACE_HDA = 16,\n\tSNDRV_HWDEP_IFACE_USB_STREAM = 17,\n\tSNDRV_HWDEP_IFACE_FW_DICE = 18,\n\tSNDRV_HWDEP_IFACE_FW_FIREWORKS = 19,\n\tSNDRV_HWDEP_IFACE_FW_BEBOB = 20,\n\tSNDRV_HWDEP_IFACE_FW_OXFW = 21,\n\tSNDRV_HWDEP_IFACE_FW_DIGI00X = 22,\n\tSNDRV_HWDEP_IFACE_FW_TASCAM = 23,\n\tSNDRV_HWDEP_IFACE_LINE6 = 24,\n\tSNDRV_HWDEP_IFACE_FW_MOTU = 25,\n\tSNDRV_HWDEP_IFACE_FW_FIREFACE = 26,\n\tSNDRV_HWDEP_IFACE_LAST = 26,\n};\n\nenum {\n\tSNDRV_HWDEP_IOCTL_DSP_LOAD32 = 1079003139,\n};\n\nenum {\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = 5,\n};\n\nenum {\n\tSNDRV_PCM_CLASS_GENERIC = 0,\n\tSNDRV_PCM_CLASS_MULTI = 1,\n\tSNDRV_PCM_CLASS_MODEM = 2,\n\tSNDRV_PCM_CLASS_DIGITIZER = 3,\n\tSNDRV_PCM_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_PCM_IOCTL_HW_REFINE32 = 3260825872,\n\tSNDRV_PCM_IOCTL_HW_PARAMS32 = 3260825873,\n\tSNDRV_PCM_IOCTL_SW_PARAMS32 = 3228057875,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT32 = 2154578208,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT32 = 3228320036,\n\tSNDRV_PCM_IOCTL_DELAY32 = 2147762465,\n\tSNDRV_PCM_IOCTL_CHANNEL_INFO32 = 2148548914,\n\tSNDRV_PCM_IOCTL_REWIND32 = 1074020678,\n\tSNDRV_PCM_IOCTL_FORWARD32 = 1074020681,\n\tSNDRV_PCM_IOCTL_WRITEI_FRAMES32 = 1074544976,\n\tSNDRV_PCM_IOCTL_READI_FRAMES32 = 2148286801,\n\tSNDRV_PCM_IOCTL_WRITEN_FRAMES32 = 1074544978,\n\tSNDRV_PCM_IOCTL_READN_FRAMES32 = 2148286803,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT64 = 2155888928,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT64 = 3229630756,\n};\n\nenum {\n\tSNDRV_PCM_MMAP_OFFSET_DATA = 0,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_OLD = 2147483648,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_OLD = 2164260864,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_NEW = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_NEW = 2197815296,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL = 2197815296,\n};\n\nenum {\n\tSNDRV_PCM_STREAM_PLAYBACK = 0,\n\tSNDRV_PCM_STREAM_CAPTURE = 1,\n\tSNDRV_PCM_STREAM_LAST = 1,\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_NONE = 0,\n\tSNDRV_PCM_TSTAMP_ENABLE = 1,\n\tSNDRV_PCM_TSTAMP_LAST = 1,\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC = 1,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW = 2,\n\tSNDRV_PCM_TSTAMP_TYPE_LAST = 2,\n};\n\nenum {\n\tSNDRV_SEQ_IOCTL_CREATE_PORT32 = 3231994656,\n\tSNDRV_SEQ_IOCTL_DELETE_PORT32 = 1084511009,\n\tSNDRV_SEQ_IOCTL_GET_PORT_INFO32 = 3231994658,\n\tSNDRV_SEQ_IOCTL_SET_PORT_INFO32 = 1084511011,\n\tSNDRV_SEQ_IOCTL_QUERY_NEXT_PORT32 = 3231994706,\n};\n\nenum {\n\tSNDRV_TIMER_CLASS_NONE = -1,\n\tSNDRV_TIMER_CLASS_SLAVE = 0,\n\tSNDRV_TIMER_CLASS_GLOBAL = 1,\n\tSNDRV_TIMER_CLASS_CARD = 2,\n\tSNDRV_TIMER_CLASS_PCM = 3,\n\tSNDRV_TIMER_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_TIMER_EVENT_RESOLUTION = 0,\n\tSNDRV_TIMER_EVENT_TICK = 1,\n\tSNDRV_TIMER_EVENT_START = 2,\n\tSNDRV_TIMER_EVENT_STOP = 3,\n\tSNDRV_TIMER_EVENT_CONTINUE = 4,\n\tSNDRV_TIMER_EVENT_PAUSE = 5,\n\tSNDRV_TIMER_EVENT_EARLY = 6,\n\tSNDRV_TIMER_EVENT_SUSPEND = 7,\n\tSNDRV_TIMER_EVENT_RESUME = 8,\n\tSNDRV_TIMER_EVENT_MSTART = 12,\n\tSNDRV_TIMER_EVENT_MSTOP = 13,\n\tSNDRV_TIMER_EVENT_MCONTINUE = 14,\n\tSNDRV_TIMER_EVENT_MPAUSE = 15,\n\tSNDRV_TIMER_EVENT_MSUSPEND = 17,\n\tSNDRV_TIMER_EVENT_MRESUME = 18,\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_GPARAMS32 = 1077695492,\n\tSNDRV_TIMER_IOCTL_INFO32 = 2162185233,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT32 = 1079530516,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT64 = 1080054804,\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_START_OLD = 21536,\n\tSNDRV_TIMER_IOCTL_STOP_OLD = 21537,\n\tSNDRV_TIMER_IOCTL_CONTINUE_OLD = 21538,\n\tSNDRV_TIMER_IOCTL_PAUSE_OLD = 21539,\n};\n\nenum {\n\tSNDRV_TIMER_SCLASS_NONE = 0,\n\tSNDRV_TIMER_SCLASS_APPLICATION = 1,\n\tSNDRV_TIMER_SCLASS_SEQUENCER = 2,\n\tSNDRV_TIMER_SCLASS_OSS_SEQUENCER = 3,\n\tSNDRV_TIMER_SCLASS_LAST = 3,\n};\n\nenum {\n\tSND_CTL_SUBDEV_PCM = 0,\n\tSND_CTL_SUBDEV_RAWMIDI = 1,\n\tSND_CTL_SUBDEV_ITEMS = 2,\n};\n\nenum {\n\tSND_INTEL_DSP_DRIVER_ANY = 0,\n\tSND_INTEL_DSP_DRIVER_LEGACY = 1,\n\tSND_INTEL_DSP_DRIVER_SST = 2,\n\tSND_INTEL_DSP_DRIVER_SOF = 3,\n\tSND_INTEL_DSP_DRIVER_AVS = 4,\n\tSND_INTEL_DSP_DRIVER_LAST = 4,\n};\n\nenum {\n\tSNR_PCI_UNCORE_M2M = 0,\n\tSNR_PCI_UNCORE_PCIE3 = 1,\n};\n\nenum {\n\tSNR_QAT_PMON_ID = 0,\n\tSNR_CBDMA_DMI_PMON_ID = 1,\n\tSNR_NIS_PMON_ID = 2,\n\tSNR_DLB_PMON_ID = 3,\n\tSNR_PCIE_GEN3_PMON_ID = 4,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSPI_BLIST_NOIUS = 1,\n};\n\nenum {\n\tSR_DMAR_FECTL_REG = 0,\n\tSR_DMAR_FEDATA_REG = 1,\n\tSR_DMAR_FEADDR_REG = 2,\n\tSR_DMAR_FEUADDR_REG = 3,\n\tMAX_SR_DMAR_REGS = 4,\n};\n\nenum {\n\tSTART_TS = 0,\n\tNOW_TS = 1,\n\tDELTA_TS = 2,\n\tJUMP_PREDICATE = 3,\n\tDELTA_TARGET = 4,\n\tN_CS_GPR = 5,\n};\n\nenum {\n\tSTREAM_MULTI_OUT = 0,\n\tSTREAM_INDEP_HP = 1,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWMII_SPEED_10 = 0,\n\tSWMII_SPEED_100 = 1,\n\tSWMII_SPEED_1000 = 2,\n\tSWMII_DUPLEX_HALF = 0,\n\tSWMII_DUPLEX_FULL = 1,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSW_BIT_CACHE_FLUSH_DONE = 0,\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = -1,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_ATTR_UNSPEC = 0,\n\tTASKSTATS_CMD_ATTR_PID = 1,\n\tTASKSTATS_CMD_ATTR_TGID = 2,\n\tTASKSTATS_CMD_ATTR_REGISTER_CPUMASK = 3,\n\tTASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK = 4,\n\t__TASKSTATS_CMD_ATTR_MAX = 5,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASKSTATS_TYPE_UNSPEC = 0,\n\tTASKSTATS_TYPE_PID = 1,\n\tTASKSTATS_TYPE_TGID = 2,\n\tTASKSTATS_TYPE_STATS = 3,\n\tTASKSTATS_TYPE_AGGR_PID = 4,\n\tTASKSTATS_TYPE_AGGR_TGID = 5,\n\tTASKSTATS_TYPE_NULL = 6,\n\t__TASKSTATS_TYPE_MAX = 7,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTASK_SWITCH_CALL = 0,\n\tTASK_SWITCH_IRET = 1,\n\tTASK_SWITCH_JMP = 2,\n\tTASK_SWITCH_GATE = 3,\n};\n\nenum {\n\tTCA_ACT_UNSPEC = 0,\n\tTCA_ACT_KIND = 1,\n\tTCA_ACT_OPTIONS = 2,\n\tTCA_ACT_INDEX = 3,\n\tTCA_ACT_STATS = 4,\n\tTCA_ACT_PAD = 5,\n\tTCA_ACT_COOKIE = 6,\n\tTCA_ACT_FLAGS = 7,\n\tTCA_ACT_HW_STATS = 8,\n\tTCA_ACT_USED_HW_STATS = 9,\n\tTCA_ACT_IN_HW_COUNT = 10,\n\t__TCA_ACT_MAX = 11,\n};\n\nenum {\n\tTCA_CGROUP_UNSPEC = 0,\n\tTCA_CGROUP_ACT = 1,\n\tTCA_CGROUP_POLICE = 2,\n\tTCA_CGROUP_EMATCHES = 3,\n\t__TCA_CGROUP_MAX = 4,\n};\n\nenum {\n\tTCA_EMATCH_TREE_UNSPEC = 0,\n\tTCA_EMATCH_TREE_HDR = 1,\n\tTCA_EMATCH_TREE_LIST = 2,\n\t__TCA_EMATCH_TREE_MAX = 3,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_ROOT_UNSPEC = 0,\n\tTCA_ROOT_TAB = 1,\n\tTCA_ROOT_FLAGS = 2,\n\tTCA_ROOT_COUNT = 3,\n\tTCA_ROOT_TIME_DELTA = 4,\n\tTCA_ROOT_EXT_WARN_MSG = 5,\n\t__TCA_ROOT_MAX = 6,\n};\n\nenum {\n\tTCA_STAB_UNSPEC = 0,\n\tTCA_STAB_BASE = 1,\n\tTCA_STAB_DATA = 2,\n\t__TCA_STAB_MAX = 3,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 1,\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 14,\n\tTCP_DATA_OFFSET = 240,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nenum {\n\tTOO_MANY_CLOSE = -1,\n\tTOO_MANY_OPEN = -2,\n\tMISSING_QUOTE = -3,\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_BAD_MAXACT_TYPE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_NON_UNIQ_SYMBOL = 10,\n\tTP_ERR_BAD_RETPROBE = 11,\n\tTP_ERR_NO_TRACEPOINT = 12,\n\tTP_ERR_BAD_TP_NAME = 13,\n\tTP_ERR_BAD_ADDR_SUFFIX = 14,\n\tTP_ERR_NO_GROUP_NAME = 15,\n\tTP_ERR_GROUP_TOO_LONG = 16,\n\tTP_ERR_BAD_GROUP_NAME = 17,\n\tTP_ERR_NO_EVENT_NAME = 18,\n\tTP_ERR_EVENT_TOO_LONG = 19,\n\tTP_ERR_BAD_EVENT_NAME = 20,\n\tTP_ERR_EVENT_EXIST = 21,\n\tTP_ERR_RETVAL_ON_PROBE = 22,\n\tTP_ERR_NO_RETVAL = 23,\n\tTP_ERR_BAD_STACK_NUM = 24,\n\tTP_ERR_BAD_ARG_NUM = 25,\n\tTP_ERR_BAD_VAR = 26,\n\tTP_ERR_BAD_REG_NAME = 27,\n\tTP_ERR_BAD_MEM_ADDR = 28,\n\tTP_ERR_BAD_IMM = 29,\n\tTP_ERR_IMMSTR_NO_CLOSE = 30,\n\tTP_ERR_FILE_ON_KPROBE = 31,\n\tTP_ERR_BAD_FILE_OFFS = 32,\n\tTP_ERR_SYM_ON_UPROBE = 33,\n\tTP_ERR_TOO_MANY_OPS = 34,\n\tTP_ERR_DEREF_NEED_BRACE = 35,\n\tTP_ERR_BAD_DEREF_OFFS = 36,\n\tTP_ERR_DEREF_OPEN_BRACE = 37,\n\tTP_ERR_COMM_CANT_DEREF = 38,\n\tTP_ERR_BAD_FETCH_ARG = 39,\n\tTP_ERR_ARRAY_NO_CLOSE = 40,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 41,\n\tTP_ERR_BAD_ARRAY_NUM = 42,\n\tTP_ERR_ARRAY_TOO_BIG = 43,\n\tTP_ERR_BAD_TYPE = 44,\n\tTP_ERR_BAD_STRING = 45,\n\tTP_ERR_BAD_SYMSTRING = 46,\n\tTP_ERR_BAD_BITFIELD = 47,\n\tTP_ERR_ARG_NAME_TOO_LONG = 48,\n\tTP_ERR_NO_ARG_NAME = 49,\n\tTP_ERR_BAD_ARG_NAME = 50,\n\tTP_ERR_USED_ARG_NAME = 51,\n\tTP_ERR_ARG_TOO_LONG = 52,\n\tTP_ERR_NO_ARG_BODY = 53,\n\tTP_ERR_BAD_INSN_BNDRY = 54,\n\tTP_ERR_FAIL_REG_PROBE = 55,\n\tTP_ERR_DIFF_PROBE_TYPE = 56,\n\tTP_ERR_DIFF_ARG_TYPE = 57,\n\tTP_ERR_SAME_PROBE = 58,\n\tTP_ERR_NO_EVENT_INFO = 59,\n\tTP_ERR_BAD_ATTACH_EVENT = 60,\n\tTP_ERR_BAD_ATTACH_ARG = 61,\n\tTP_ERR_NO_EP_FILTER = 62,\n\tTP_ERR_NOSUP_BTFARG = 63,\n\tTP_ERR_NO_BTFARG = 64,\n\tTP_ERR_NO_BTF_ENTRY = 65,\n\tTP_ERR_BAD_VAR_ARGS = 66,\n\tTP_ERR_NOFENTRY_ARGS = 67,\n\tTP_ERR_DOUBLE_ARGS = 68,\n\tTP_ERR_ARGS_2LONG = 69,\n\tTP_ERR_ARGIDX_2BIG = 70,\n\tTP_ERR_NO_PTR_STRCT = 71,\n\tTP_ERR_NOSUP_DAT_ARG = 72,\n\tTP_ERR_BAD_HYPHEN = 73,\n\tTP_ERR_NO_BTF_FIELD = 74,\n\tTP_ERR_BAD_BTF_TID = 75,\n\tTP_ERR_BAD_TYPE4STR = 76,\n\tTP_ERR_NEED_STRING_TYPE = 77,\n\tTP_ERR_TOO_MANY_ARGS = 78,\n\tTP_ERR_TOO_MANY_EARGS = 79,\n};\n\nenum {\n\tTRACEFS_EVENT_INODE = 2,\n\tTRACEFS_GID_PERM_SET = 4,\n\tTRACEFS_UID_PERM_SET = 8,\n\tTRACEFS_INSTANCE_INODE = 16,\n};\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n\tTRACE_ARRAY_FL_BOOT = 2,\n\tTRACE_ARRAY_FL_LAST_BOOT = 4,\n\tTRACE_ARRAY_FL_MOD_INIT = 8,\n\tTRACE_ARRAY_FL_MEMMAP = 16,\n\tTRACE_ARRAY_FL_VMALLOC = 32,\n};\n\nenum {\n\tTRACE_CTX_NMI = 0,\n\tTRACE_CTX_IRQ = 1,\n\tTRACE_CTX_SOFTIRQ = 2,\n\tTRACE_CTX_NORMAL = 3,\n\tTRACE_CTX_TRANSITION = 4,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 4,\n\tTRACE_EVENT_FL_TRACEPOINT = 8,\n\tTRACE_EVENT_FL_DYNAMIC = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n\tTRACE_EVENT_FL_EPROBE = 128,\n\tTRACE_EVENT_FL_FPROBE = 256,\n\tTRACE_EVENT_FL_CUSTOM = 512,\n\tTRACE_EVENT_FL_TEST_STR = 1024,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_FTRACE_BIT = 0,\n\tTRACE_FTRACE_NMI_BIT = 1,\n\tTRACE_FTRACE_IRQ_BIT = 2,\n\tTRACE_FTRACE_SIRQ_BIT = 3,\n\tTRACE_FTRACE_TRANSITION_BIT = 4,\n\tTRACE_INTERNAL_BIT = 5,\n\tTRACE_INTERNAL_NMI_BIT = 6,\n\tTRACE_INTERNAL_IRQ_BIT = 7,\n\tTRACE_INTERNAL_SIRQ_BIT = 8,\n\tTRACE_INTERNAL_TRANSITION_BIT = 9,\n\tTRACE_INTERNAL_EVENT_BIT = 10,\n\tTRACE_INTERNAL_EVENT_NMI_BIT = 11,\n\tTRACE_INTERNAL_EVENT_IRQ_BIT = 12,\n\tTRACE_INTERNAL_EVENT_SIRQ_BIT = 13,\n\tTRACE_INTERNAL_EVENT_TRANSITION_BIT = 14,\n\tTRACE_BRANCH_BIT = 15,\n\tTRACE_IRQ_BIT = 16,\n\tTRACE_RECORD_RECURSION_BIT = 17,\n};\n\nenum {\n\tTRACE_FUNC_NO_OPTS = 0,\n\tTRACE_FUNC_OPT_STACK = 1,\n\tTRACE_FUNC_OPT_NO_REPEATS = 2,\n\tTRACE_FUNC_OPT_ARGS = 4,\n\tTRACE_FUNC_OPT_HIGHEST_BIT = 8,\n};\n\nenum {\n\tTRACE_GRAPH_FL = 1,\n\tTRACE_GRAPH_DEPTH_START_BIT = 2,\n\tTRACE_GRAPH_DEPTH_END_BIT = 3,\n\tTRACE_GRAPH_NOTRACE_BIT = 4,\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tTTY_LOCK_NORMAL = 0,\n\tTTY_LOCK_SLAVE = 1,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNCORE_TYPE_DF = 0,\n\tUNCORE_TYPE_L3 = 1,\n\tUNCORE_TYPE_UMC = 2,\n\tUNCORE_TYPE_MAX = 3,\n};\n\nenum {\n\tUNDEFINED_CAPABLE = 0,\n\tSYSTEM_INTEL_MSR_CAPABLE = 1,\n\tSYSTEM_AMD_MSR_CAPABLE = 2,\n\tSYSTEM_IO_CAPABLE = 3,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tUNWIND_PENDING = 1,\n\tUNWIND_USED = 2,\n};\n\nenum {\n\tUNWIND_PENDING_BIT = 0,\n\tUNWIND_USED_BIT = 1,\n};\n\nenum {\n\tVCPU_SREG_ES = 0,\n\tVCPU_SREG_CS = 1,\n\tVCPU_SREG_SS = 2,\n\tVCPU_SREG_DS = 3,\n\tVCPU_SREG_FS = 4,\n\tVCPU_SREG_GS = 5,\n\tVCPU_SREG_TR = 6,\n\tVCPU_SREG_LDTR = 7,\n};\n\nenum {\n\tVERBOSE_STATUS = 1,\n};\n\nenum {\n\tVIA_STRFILT_CNT_SHIFT = 16,\n\tVIA_STRFILT_FAIL = 32768,\n\tVIA_STRFILT_ENABLE = 16384,\n\tVIA_RAWBITS_ENABLE = 8192,\n\tVIA_RNG_ENABLE = 64,\n\tVIA_NOISESRC1 = 256,\n\tVIA_NOISESRC2 = 512,\n\tVIA_XSTORE_CNT_MASK = 15,\n\tVIA_RNG_CHUNK_8 = 0,\n\tVIA_RNG_CHUNK_4 = 1,\n\tVIA_RNG_CHUNK_4_MASK = 4294967295,\n\tVIA_RNG_CHUNK_2 = 2,\n\tVIA_RNG_CHUNK_2_MASK = 65535,\n\tVIA_RNG_CHUNK_1 = 3,\n\tVIA_RNG_CHUNK_1_MASK = 255,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tVMCB_INTERCEPTS = 0,\n\tVMCB_PERM_MAP = 1,\n\tVMCB_ASID = 2,\n\tVMCB_INTR = 3,\n\tVMCB_NPT = 4,\n\tVMCB_CR = 5,\n\tVMCB_DR = 6,\n\tVMCB_DT = 7,\n\tVMCB_SEG = 8,\n\tVMCB_CR2 = 9,\n\tVMCB_LBR = 10,\n\tVMCB_AVIC = 11,\n\tVMCB_CET = 12,\n\tVMCB_SW = 31,\n};\n\nenum {\n\tVMX_VMREAD_BITMAP = 0,\n\tVMX_VMWRITE_BITMAP = 1,\n\tVMX_BITMAP_NR = 2,\n};\n\nenum {\n\tVP_MSIX_CONFIG_VECTOR = 0,\n\tVP_MSIX_VQ_VECTOR = 1,\n};\n\nenum {\n\tVQ_HIPRIO = 0,\n\tVQ_REQUEST = 1,\n};\n\nenum {\n\tVSOCK_VQ_RX = 0,\n\tVSOCK_VQ_TX = 1,\n\tVSOCK_VQ_EVENT = 2,\n\tVSOCK_VQ_MAX = 3,\n};\n\nenum {\n\tVTDSS_FMT_PS = 128,\n};\n\nenum {\n\tVTDSS_FMT_R = 1ULL,\n\tVTDSS_FMT_W = 2ULL,\n\tVTDSS_FMT_A = 256ULL,\n\tVTDSS_FMT_D = 512ULL,\n\tVTDSS_FMT_SNP = 2048ULL,\n\tVTDSS_FMT_OA = 4503599627366400ULL,\n};\n\nenum {\n\tVTIME_PER_SEC_SHIFT = 37ULL,\n\tVTIME_PER_SEC = 137438953472ULL,\n\tVTIME_PER_USEC = 137438ULL,\n\tVTIME_PER_NSEC = 137ULL,\n\tVRATE_MIN_PPM = 10000ULL,\n\tVRATE_MAX_PPM = 100000000ULL,\n\tVRATE_MIN = 1374ULL,\n\tVRATE_CLAMP_ADJ_PCT = 4ULL,\n\tAUTOP_CYCLE_NSEC = 10000000000ULL,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tWMI_READ_TAKES_NO_ARGS = 0,\n\tWMI_GUID_DUPLICATED = 1,\n\tWMI_NO_EVENT_DATA = 2,\n};\n\nenum {\n\tX2APIC_OFF = 0,\n\tX2APIC_DISABLED = 1,\n\tX2APIC_ON = 2,\n\tX2APIC_ON_LOCKED = 3,\n};\n\nenum {\n\tX86_64_FMT_P = 1ULL,\n\tX86_64_FMT_RW = 2ULL,\n\tX86_64_FMT_U = 4ULL,\n\tX86_64_FMT_A = 32ULL,\n\tX86_64_FMT_D = 64ULL,\n\tX86_64_FMT_OA = 4503599627366400ULL,\n\tX86_64_FMT_XD = 9223372036854775808ULL,\n};\n\nenum {\n\tX86_64_FMT_PS = 128,\n};\n\nenum {\n\tX86_BR_NONE = 0,\n\tX86_BR_USER = 1,\n\tX86_BR_KERNEL = 2,\n\tX86_BR_CALL = 4,\n\tX86_BR_RET = 8,\n\tX86_BR_SYSCALL = 16,\n\tX86_BR_SYSRET = 32,\n\tX86_BR_INT = 64,\n\tX86_BR_IRET = 128,\n\tX86_BR_JCC = 256,\n\tX86_BR_JMP = 512,\n\tX86_BR_IRQ = 1024,\n\tX86_BR_IND_CALL = 2048,\n\tX86_BR_ABORT = 4096,\n\tX86_BR_IN_TX = 8192,\n\tX86_BR_NO_TX = 16384,\n\tX86_BR_ZERO_CALL = 32768,\n\tX86_BR_CALL_STACK = 65536,\n\tX86_BR_IND_JMP = 131072,\n\tX86_BR_TYPE_SAVE = 262144,\n};\n\nenum {\n\tX86_IRQ_ALLOC_LEGACY = 1,\n};\n\nenum {\n\tX86_PERF_KFREE_SHARED = 0,\n\tX86_PERF_KFREE_EXCL = 1,\n\tX86_PERF_KFREE_MAX = 2,\n};\n\nenum {\n\tX86_USER_RDPMC_NEVER_ENABLE = 0,\n\tX86_USER_RDPMC_CONDITIONAL_ENABLE = 1,\n\tX86_USER_RDPMC_ALWAYS_ENABLE = 2,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tZONELIST_NOFALLBACK = 1,\n\tMAX_ZONELISTS = 2,\n};\n\nenum {\n\t_DQUOT_USAGE_ENABLED = 0,\n\t_DQUOT_LIMITS_ENABLED = 1,\n\t_DQUOT_SUSPENDED = 2,\n\t_DQUOT_STATE_FLAGS = 3,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 0,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t__I915_SAMPLE_FREQ_ACT = 0,\n\t__I915_SAMPLE_FREQ_REQ = 1,\n\t__I915_SAMPLE_RC6 = 2,\n\t__I915_SAMPLE_RC6_LAST_REPORTED = 3,\n\t__I915_NUM_PMU_SAMPLERS = 4,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_PARANOID_AVG = 10,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 11,\n\t__SCHED_FEAT_HRTICK = 12,\n\t__SCHED_FEAT_HRTICK_DL = 13,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 14,\n\t__SCHED_FEAT_TTWU_QUEUE = 15,\n\t__SCHED_FEAT_SIS_UTIL = 16,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 17,\n\t__SCHED_FEAT_RT_PUSH_IPI = 18,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 19,\n\t__SCHED_FEAT_LB_MIN = 20,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 21,\n\t__SCHED_FEAT_WA_IDLE = 22,\n\t__SCHED_FEAT_WA_WEIGHT = 23,\n\t__SCHED_FEAT_WA_BIAS = 24,\n\t__SCHED_FEAT_UTIL_EST = 25,\n\t__SCHED_FEAT_LATENCY_WARN = 26,\n\t__SCHED_FEAT_NI_RANDOM = 27,\n\t__SCHED_FEAT_NI_RATE = 28,\n\t__SCHED_FEAT_NR = 29,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NOLOCKDEP_BIT = 24,\n\t___GFP_NO_OBJ_EXT_BIT = 25,\n\t___GFP_LAST_BIT = 26,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SKB = 4,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK = 5,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 7,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 8,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 9,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 10,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 11,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 12,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 13,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 14,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 15,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 16,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 17,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 18,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 19,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 20,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_DEVICE = 21,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SYSCTL = 22,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCKOPT = 23,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 24,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 25,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 26,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 27,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 28,\n\t__ctx_convert_unused = 29,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\tkvm_ioeventfd_flag_nr_datamatch = 0,\n\tkvm_ioeventfd_flag_nr_pio = 1,\n\tkvm_ioeventfd_flag_nr_deassign = 2,\n\tkvm_ioeventfd_flag_nr_virtio_ccw_notify = 3,\n\tkvm_ioeventfd_flag_nr_fast_mmio = 4,\n\tkvm_ioeventfd_flag_nr_max = 5,\n};\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tpreempt_dynamic_undefined = -1,\n\tpreempt_dynamic_none = 0,\n\tpreempt_dynamic_voluntary = 1,\n\tpreempt_dynamic_full = 2,\n\tpreempt_dynamic_lazy = 3,\n};\n\nenum {\n\tst_wordstart = 0,\n\tst_wordcmp = 1,\n\tst_wordskip = 2,\n\tst_bufcpy = 3,\n};\n\nenum {\n\tst_wordstart___2 = 0,\n\tst_wordcmp___2 = 1,\n\tst_wordskip___2 = 2,\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\nenum {\n\tx86_lbr_exclusive_lbr = 0,\n\tx86_lbr_exclusive_bts = 1,\n\tx86_lbr_exclusive_pt = 2,\n\tx86_lbr_exclusive_max = 3,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tOSL_GLOBAL_LOCK_HANDLER = 0,\n\tOSL_NOTIFY_HANDLER = 1,\n\tOSL_GPE_HANDLER = 2,\n\tOSL_DEBUGGER_MAIN_THREAD = 3,\n\tOSL_DEBUGGER_EXEC_THREAD = 4,\n\tOSL_EC_POLL_HANDLER = 5,\n\tOSL_EC_BURST_HANDLER = 6,\n} acpi_execute_type;\n\ntypedef enum {\n\tACPI_IMODE_LOAD_PASS1 = 1,\n\tACPI_IMODE_LOAD_PASS2 = 2,\n\tACPI_IMODE_EXECUTE = 3,\n} acpi_interpreter_mode;\n\ntypedef enum {\n\tACPI_TRACE_AML_METHOD = 0,\n\tACPI_TRACE_AML_OPCODE = 1,\n\tACPI_TRACE_AML_REGION = 2,\n} acpi_trace_event_type;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tneed_more = 0,\n\tblock_done = 1,\n\tfinish_started = 2,\n\tfinish_done = 3,\n} block_state;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tMAP_CHG_REUSE = 0,\n\tMAP_CHG_NEEDED = 1,\n\tMAP_CHG_ENFORCED = 2,\n} map_chg_state;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tSTATUSTYPE_INFO = 0,\n\tSTATUSTYPE_TABLE = 1,\n\tSTATUSTYPE_IMA = 2,\n} status_type_t;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecPublicKey = 2,\n\tOID_id_prime192v1 = 3,\n\tOID_id_prime256v1 = 4,\n\tOID_id_ecdsa_with_sha1 = 5,\n\tOID_id_ecdsa_with_sha224 = 6,\n\tOID_id_ecdsa_with_sha256 = 7,\n\tOID_id_ecdsa_with_sha384 = 8,\n\tOID_id_ecdsa_with_sha512 = 9,\n\tOID_rsaEncryption = 10,\n\tOID_sha1WithRSAEncryption = 11,\n\tOID_sha256WithRSAEncryption = 12,\n\tOID_sha384WithRSAEncryption = 13,\n\tOID_sha512WithRSAEncryption = 14,\n\tOID_sha224WithRSAEncryption = 15,\n\tOID_data = 16,\n\tOID_signed_data = 17,\n\tOID_email_address = 18,\n\tOID_contentType = 19,\n\tOID_messageDigest = 20,\n\tOID_signingTime = 21,\n\tOID_smimeCapabilites = 22,\n\tOID_smimeAuthenticatedAttrs = 23,\n\tOID_mskrb5 = 24,\n\tOID_krb5 = 25,\n\tOID_krb5u2u = 26,\n\tOID_msIndirectData = 27,\n\tOID_msStatementType = 28,\n\tOID_msSpOpusInfo = 29,\n\tOID_msPeImageDataObjId = 30,\n\tOID_msIndividualSPKeyPurpose = 31,\n\tOID_msOutlookExpress = 32,\n\tOID_ntlmssp = 33,\n\tOID_negoex = 34,\n\tOID_spnego = 35,\n\tOID_IAKerb = 36,\n\tOID_PKU2U = 37,\n\tOID_Scram = 38,\n\tOID_certAuthInfoAccess = 39,\n\tOID_sha1 = 40,\n\tOID_id_ansip384r1 = 41,\n\tOID_id_ansip521r1 = 42,\n\tOID_sha256 = 43,\n\tOID_sha384 = 44,\n\tOID_sha512 = 45,\n\tOID_sha224 = 46,\n\tOID_commonName = 47,\n\tOID_surname = 48,\n\tOID_countryName = 49,\n\tOID_locality = 50,\n\tOID_stateOrProvinceName = 51,\n\tOID_organizationName = 52,\n\tOID_organizationUnitName = 53,\n\tOID_title = 54,\n\tOID_description = 55,\n\tOID_name = 56,\n\tOID_givenName = 57,\n\tOID_initials = 58,\n\tOID_generationalQualifier = 59,\n\tOID_subjectKeyIdentifier = 60,\n\tOID_keyUsage = 61,\n\tOID_subjectAltName = 62,\n\tOID_issuerAltName = 63,\n\tOID_basicConstraints = 64,\n\tOID_crlDistributionPoints = 65,\n\tOID_certPolicies = 66,\n\tOID_authorityKeyIdentifier = 67,\n\tOID_extKeyUsage = 68,\n\tOID_NetlogonMechanism = 69,\n\tOID_appleLocalKdcSupported = 70,\n\tOID_gostCPSignA = 71,\n\tOID_gostCPSignB = 72,\n\tOID_gostCPSignC = 73,\n\tOID_gost2012PKey256 = 74,\n\tOID_gost2012PKey512 = 75,\n\tOID_gost2012Digest256 = 76,\n\tOID_gost2012Digest512 = 77,\n\tOID_gost2012Signature256 = 78,\n\tOID_gost2012Signature512 = 79,\n\tOID_gostTC26Sign256A = 80,\n\tOID_gostTC26Sign256B = 81,\n\tOID_gostTC26Sign256C = 82,\n\tOID_gostTC26Sign256D = 83,\n\tOID_gostTC26Sign512A = 84,\n\tOID_gostTC26Sign512B = 85,\n\tOID_gostTC26Sign512C = 86,\n\tOID_sm2 = 87,\n\tOID_sm3 = 88,\n\tOID_SM2_with_SM3 = 89,\n\tOID_sm3WithRSAEncryption = 90,\n\tOID_TPMLoadableKey = 91,\n\tOID_TPMImportableKey = 92,\n\tOID_TPMSealedData = 93,\n\tOID_sha3_256 = 94,\n\tOID_sha3_384 = 95,\n\tOID_sha3_512 = 96,\n\tOID_id_ecdsa_with_sha3_256 = 97,\n\tOID_id_ecdsa_with_sha3_384 = 98,\n\tOID_id_ecdsa_with_sha3_512 = 99,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102,\n\tOID_id_ml_dsa_44 = 103,\n\tOID_id_ml_dsa_65 = 104,\n\tOID_id_ml_dsa_87 = 105,\n\tOID__NR = 106,\n};\n\nenum Opt_errors {\n\tOpt_errors_continue = 0,\n\tOpt_errors_panic = 1,\n};\n\nenum P4_ESCR_EMASKS {\n\tP4_EVENT_TC_DELIVER_MODE__DD = 512,\n\tP4_EVENT_TC_DELIVER_MODE__DB = 1024,\n\tP4_EVENT_TC_DELIVER_MODE__DI = 2048,\n\tP4_EVENT_TC_DELIVER_MODE__BD = 4096,\n\tP4_EVENT_TC_DELIVER_MODE__BB = 8192,\n\tP4_EVENT_TC_DELIVER_MODE__BI = 16384,\n\tP4_EVENT_TC_DELIVER_MODE__ID = 32768,\n\tP4_EVENT_BPU_FETCH_REQUEST__TCMISS = 512,\n\tP4_EVENT_ITLB_REFERENCE__HIT = 512,\n\tP4_EVENT_ITLB_REFERENCE__MISS = 1024,\n\tP4_EVENT_ITLB_REFERENCE__HIT_UK = 2048,\n\tP4_EVENT_MEMORY_CANCEL__ST_RB_FULL = 2048,\n\tP4_EVENT_MEMORY_CANCEL__64K_CONF = 4096,\n\tP4_EVENT_MEMORY_COMPLETE__LSC = 512,\n\tP4_EVENT_MEMORY_COMPLETE__SSC = 1024,\n\tP4_EVENT_LOAD_PORT_REPLAY__SPLIT_LD = 1024,\n\tP4_EVENT_STORE_PORT_REPLAY__SPLIT_ST = 1024,\n\tP4_EVENT_MOB_LOAD_REPLAY__NO_STA = 1024,\n\tP4_EVENT_MOB_LOAD_REPLAY__NO_STD = 4096,\n\tP4_EVENT_MOB_LOAD_REPLAY__PARTIAL_DATA = 8192,\n\tP4_EVENT_MOB_LOAD_REPLAY__UNALGN_ADDR = 16384,\n\tP4_EVENT_PAGE_WALK_TYPE__DTMISS = 512,\n\tP4_EVENT_PAGE_WALK_TYPE__ITMISS = 1024,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITS = 512,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITE = 1024,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITM = 2048,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITS = 4096,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITE = 8192,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITM = 16384,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_MISS = 131072,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_MISS = 262144,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__WR_2ndL_MISS = 524288,\n\tP4_EVENT_IOQ_ALLOCATION__DEFAULT = 512,\n\tP4_EVENT_IOQ_ALLOCATION__ALL_READ = 16384,\n\tP4_EVENT_IOQ_ALLOCATION__ALL_WRITE = 32768,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_UC = 65536,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WC = 131072,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WT = 262144,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WP = 524288,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WB = 1048576,\n\tP4_EVENT_IOQ_ALLOCATION__OWN = 4194304,\n\tP4_EVENT_IOQ_ALLOCATION__OTHER = 8388608,\n\tP4_EVENT_IOQ_ALLOCATION__PREFETCH = 16777216,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__DEFAULT = 512,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_READ = 16384,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_WRITE = 32768,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_UC = 65536,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WC = 131072,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WT = 262144,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WP = 524288,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WB = 1048576,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__OWN = 4194304,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__OTHER = 8388608,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__PREFETCH = 16777216,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_DRV = 512,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_OWN = 1024,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_OTHER = 2048,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_DRV = 4096,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_OWN = 8192,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_OTHER = 16384,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_TYPE0 = 512,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_TYPE1 = 1024,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LEN0 = 2048,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LEN1 = 4096,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_IO_TYPE = 16384,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LOCK_TYPE = 32768,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_CACHE_TYPE = 65536,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_SPLIT_TYPE = 131072,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_DEM_TYPE = 262144,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_ORD_TYPE = 524288,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE0 = 1048576,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE1 = 2097152,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE2 = 4194304,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE0 = 512,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE1 = 1024,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN0 = 2048,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN1 = 4096,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_IO_TYPE = 16384,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LOCK_TYPE = 32768,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_CACHE_TYPE = 65536,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_SPLIT_TYPE = 131072,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_DEM_TYPE = 262144,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_ORD_TYPE = 524288,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE0 = 1048576,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE1 = 2097152,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE2 = 4194304,\n\tP4_EVENT_SSE_INPUT_ASSIST__ALL = 16777216,\n\tP4_EVENT_PACKED_SP_UOP__ALL = 16777216,\n\tP4_EVENT_PACKED_DP_UOP__ALL = 16777216,\n\tP4_EVENT_SCALAR_SP_UOP__ALL = 16777216,\n\tP4_EVENT_SCALAR_DP_UOP__ALL = 16777216,\n\tP4_EVENT_64BIT_MMX_UOP__ALL = 16777216,\n\tP4_EVENT_128BIT_MMX_UOP__ALL = 16777216,\n\tP4_EVENT_X87_FP_UOP__ALL = 16777216,\n\tP4_EVENT_TC_MISC__FLUSH = 8192,\n\tP4_EVENT_GLOBAL_POWER_EVENTS__RUNNING = 512,\n\tP4_EVENT_TC_MS_XFER__CISC = 512,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_TC_BUILD = 512,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_TC_DELIVER = 1024,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_ROM = 2048,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CONDITIONAL = 1024,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CALL = 2048,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__RETURN = 4096,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__INDIRECT = 8192,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__CONDITIONAL = 1024,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__CALL = 2048,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__RETURN = 4096,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__INDIRECT = 8192,\n\tP4_EVENT_RESOURCE_STALL__SBFULL = 16384,\n\tP4_EVENT_WC_BUFFER__WCB_EVICTS = 512,\n\tP4_EVENT_WC_BUFFER__WCB_FULL_EVICTS = 1024,\n\tP4_EVENT_FRONT_END_EVENT__NBOGUS = 512,\n\tP4_EVENT_FRONT_END_EVENT__BOGUS = 1024,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS0 = 512,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS1 = 1024,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS2 = 2048,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS3 = 4096,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS0 = 8192,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS1 = 16384,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS2 = 32768,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS3 = 65536,\n\tP4_EVENT_REPLAY_EVENT__NBOGUS = 512,\n\tP4_EVENT_REPLAY_EVENT__BOGUS = 1024,\n\tP4_EVENT_INSTR_RETIRED__NBOGUSNTAG = 512,\n\tP4_EVENT_INSTR_RETIRED__NBOGUSTAG = 1024,\n\tP4_EVENT_INSTR_RETIRED__BOGUSNTAG = 2048,\n\tP4_EVENT_INSTR_RETIRED__BOGUSTAG = 4096,\n\tP4_EVENT_UOPS_RETIRED__NBOGUS = 512,\n\tP4_EVENT_UOPS_RETIRED__BOGUS = 1024,\n\tP4_EVENT_UOP_TYPE__TAGLOADS = 1024,\n\tP4_EVENT_UOP_TYPE__TAGSTORES = 2048,\n\tP4_EVENT_BRANCH_RETIRED__MMNP = 512,\n\tP4_EVENT_BRANCH_RETIRED__MMNM = 1024,\n\tP4_EVENT_BRANCH_RETIRED__MMTP = 2048,\n\tP4_EVENT_BRANCH_RETIRED__MMTM = 4096,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED__NBOGUS = 512,\n\tP4_EVENT_X87_ASSIST__FPSU = 512,\n\tP4_EVENT_X87_ASSIST__FPSO = 1024,\n\tP4_EVENT_X87_ASSIST__POAO = 2048,\n\tP4_EVENT_X87_ASSIST__POAU = 4096,\n\tP4_EVENT_X87_ASSIST__PREA = 8192,\n\tP4_EVENT_MACHINE_CLEAR__CLEAR = 512,\n\tP4_EVENT_MACHINE_CLEAR__MOCLEAR = 1024,\n\tP4_EVENT_MACHINE_CLEAR__SMCLEAR = 2048,\n\tP4_EVENT_INSTR_COMPLETED__NBOGUS = 512,\n\tP4_EVENT_INSTR_COMPLETED__BOGUS = 1024,\n};\n\nenum P4_EVENTS {\n\tP4_EVENT_TC_DELIVER_MODE = 0,\n\tP4_EVENT_BPU_FETCH_REQUEST = 1,\n\tP4_EVENT_ITLB_REFERENCE = 2,\n\tP4_EVENT_MEMORY_CANCEL = 3,\n\tP4_EVENT_MEMORY_COMPLETE = 4,\n\tP4_EVENT_LOAD_PORT_REPLAY = 5,\n\tP4_EVENT_STORE_PORT_REPLAY = 6,\n\tP4_EVENT_MOB_LOAD_REPLAY = 7,\n\tP4_EVENT_PAGE_WALK_TYPE = 8,\n\tP4_EVENT_BSQ_CACHE_REFERENCE = 9,\n\tP4_EVENT_IOQ_ALLOCATION = 10,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES = 11,\n\tP4_EVENT_FSB_DATA_ACTIVITY = 12,\n\tP4_EVENT_BSQ_ALLOCATION = 13,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES = 14,\n\tP4_EVENT_SSE_INPUT_ASSIST = 15,\n\tP4_EVENT_PACKED_SP_UOP = 16,\n\tP4_EVENT_PACKED_DP_UOP = 17,\n\tP4_EVENT_SCALAR_SP_UOP = 18,\n\tP4_EVENT_SCALAR_DP_UOP = 19,\n\tP4_EVENT_64BIT_MMX_UOP = 20,\n\tP4_EVENT_128BIT_MMX_UOP = 21,\n\tP4_EVENT_X87_FP_UOP = 22,\n\tP4_EVENT_TC_MISC = 23,\n\tP4_EVENT_GLOBAL_POWER_EVENTS = 24,\n\tP4_EVENT_TC_MS_XFER = 25,\n\tP4_EVENT_UOP_QUEUE_WRITES = 26,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE = 27,\n\tP4_EVENT_RETIRED_BRANCH_TYPE = 28,\n\tP4_EVENT_RESOURCE_STALL = 29,\n\tP4_EVENT_WC_BUFFER = 30,\n\tP4_EVENT_B2B_CYCLES = 31,\n\tP4_EVENT_BNR = 32,\n\tP4_EVENT_SNOOP = 33,\n\tP4_EVENT_RESPONSE = 34,\n\tP4_EVENT_FRONT_END_EVENT = 35,\n\tP4_EVENT_EXECUTION_EVENT = 36,\n\tP4_EVENT_REPLAY_EVENT = 37,\n\tP4_EVENT_INSTR_RETIRED = 38,\n\tP4_EVENT_UOPS_RETIRED = 39,\n\tP4_EVENT_UOP_TYPE = 40,\n\tP4_EVENT_BRANCH_RETIRED = 41,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED = 42,\n\tP4_EVENT_X87_ASSIST = 43,\n\tP4_EVENT_MACHINE_CLEAR = 44,\n\tP4_EVENT_INSTR_COMPLETED = 45,\n};\n\nenum P4_EVENT_OPCODES {\n\tP4_EVENT_TC_DELIVER_MODE_OPCODE = 257,\n\tP4_EVENT_BPU_FETCH_REQUEST_OPCODE = 768,\n\tP4_EVENT_ITLB_REFERENCE_OPCODE = 6147,\n\tP4_EVENT_MEMORY_CANCEL_OPCODE = 517,\n\tP4_EVENT_MEMORY_COMPLETE_OPCODE = 2050,\n\tP4_EVENT_LOAD_PORT_REPLAY_OPCODE = 1026,\n\tP4_EVENT_STORE_PORT_REPLAY_OPCODE = 1282,\n\tP4_EVENT_MOB_LOAD_REPLAY_OPCODE = 770,\n\tP4_EVENT_PAGE_WALK_TYPE_OPCODE = 260,\n\tP4_EVENT_BSQ_CACHE_REFERENCE_OPCODE = 3079,\n\tP4_EVENT_IOQ_ALLOCATION_OPCODE = 774,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES_OPCODE = 6662,\n\tP4_EVENT_FSB_DATA_ACTIVITY_OPCODE = 5894,\n\tP4_EVENT_BSQ_ALLOCATION_OPCODE = 1287,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES_OPCODE = 1543,\n\tP4_EVENT_SSE_INPUT_ASSIST_OPCODE = 13313,\n\tP4_EVENT_PACKED_SP_UOP_OPCODE = 2049,\n\tP4_EVENT_PACKED_DP_UOP_OPCODE = 3073,\n\tP4_EVENT_SCALAR_SP_UOP_OPCODE = 2561,\n\tP4_EVENT_SCALAR_DP_UOP_OPCODE = 3585,\n\tP4_EVENT_64BIT_MMX_UOP_OPCODE = 513,\n\tP4_EVENT_128BIT_MMX_UOP_OPCODE = 6657,\n\tP4_EVENT_X87_FP_UOP_OPCODE = 1025,\n\tP4_EVENT_TC_MISC_OPCODE = 1537,\n\tP4_EVENT_GLOBAL_POWER_EVENTS_OPCODE = 4870,\n\tP4_EVENT_TC_MS_XFER_OPCODE = 1280,\n\tP4_EVENT_UOP_QUEUE_WRITES_OPCODE = 2304,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE_OPCODE = 1282,\n\tP4_EVENT_RETIRED_BRANCH_TYPE_OPCODE = 1026,\n\tP4_EVENT_RESOURCE_STALL_OPCODE = 257,\n\tP4_EVENT_WC_BUFFER_OPCODE = 1285,\n\tP4_EVENT_B2B_CYCLES_OPCODE = 5635,\n\tP4_EVENT_BNR_OPCODE = 2051,\n\tP4_EVENT_SNOOP_OPCODE = 1539,\n\tP4_EVENT_RESPONSE_OPCODE = 1027,\n\tP4_EVENT_FRONT_END_EVENT_OPCODE = 2053,\n\tP4_EVENT_EXECUTION_EVENT_OPCODE = 3077,\n\tP4_EVENT_REPLAY_EVENT_OPCODE = 2309,\n\tP4_EVENT_INSTR_RETIRED_OPCODE = 516,\n\tP4_EVENT_UOPS_RETIRED_OPCODE = 260,\n\tP4_EVENT_UOP_TYPE_OPCODE = 514,\n\tP4_EVENT_BRANCH_RETIRED_OPCODE = 1541,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED_OPCODE = 772,\n\tP4_EVENT_X87_ASSIST_OPCODE = 773,\n\tP4_EVENT_MACHINE_CLEAR_OPCODE = 517,\n\tP4_EVENT_INSTR_COMPLETED_OPCODE = 1796,\n};\n\nenum P4_PEBS_METRIC {\n\tP4_PEBS_METRIC__none = 0,\n\tP4_PEBS_METRIC__1stl_cache_load_miss_retired = 1,\n\tP4_PEBS_METRIC__2ndl_cache_load_miss_retired = 2,\n\tP4_PEBS_METRIC__dtlb_load_miss_retired = 3,\n\tP4_PEBS_METRIC__dtlb_store_miss_retired = 4,\n\tP4_PEBS_METRIC__dtlb_all_miss_retired = 5,\n\tP4_PEBS_METRIC__tagged_mispred_branch = 6,\n\tP4_PEBS_METRIC__mob_load_replay_retired = 7,\n\tP4_PEBS_METRIC__split_load_retired = 8,\n\tP4_PEBS_METRIC__split_store_retired = 9,\n\tP4_PEBS_METRIC__max = 10,\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _cache_table_type {\n\tCACHE_L1_INST = 1,\n\tCACHE_L1_DATA = 2,\n\tCACHE_L2 = 3,\n\tCACHE_L3 = 4,\n} __attribute__((mode(byte)));\n\nenum _cache_type {\n\tCTYPE_NULL = 0,\n\tCTYPE_DATA = 1,\n\tCTYPE_INST = 2,\n\tCTYPE_UNIFIED = 3,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_NO_USER_FLAGS = 13,\n\t_SLAB_RECLAIM_ACCOUNT = 14,\n\t_SLAB_OBJECT_POISON = 15,\n\t_SLAB_CMPXCHG_DOUBLE = 16,\n\t_SLAB_NO_OBJ_EXT = 17,\n\t_SLAB_FLAGS_LAST_BIT = 18,\n};\n\nenum _tlb_table_type {\n\tTLB_INST_4K = 5,\n\tTLB_INST_4M = 6,\n\tTLB_INST_2M_4M = 7,\n\tTLB_INST_ALL = 8,\n\tTLB_DATA_4K = 9,\n\tTLB_DATA_4M = 10,\n\tTLB_DATA_2M_4M = 11,\n\tTLB_DATA_4K_4M = 12,\n\tTLB_DATA_1G = 13,\n\tTLB_DATA_1G_2M_4M = 14,\n\tTLB_DATA0_4K = 15,\n\tTLB_DATA0_4M = 16,\n\tTLB_DATA0_2M_4M = 17,\n\tSTLB_4K = 18,\n\tSTLB_4K_2M = 19,\n} __attribute__((mode(byte)));\n\nenum ac97_pcm_cfg {\n\tAC97_PCM_CFG_FRONT = 2,\n\tAC97_PCM_CFG_REAR = 10,\n\tAC97_PCM_CFG_LFE = 11,\n\tAC97_PCM_CFG_40 = 4,\n\tAC97_PCM_CFG_51 = 6,\n\tAC97_PCM_CFG_SPDIF = 20,\n};\n\nenum access_coordinate_class {\n\tACCESS_COORDINATE_LOCAL = 0,\n\tACCESS_COORDINATE_CPU = 1,\n\tACCESS_COORDINATE_MAX = 2,\n};\n\nenum ack_type {\n\tACK_CLEAR = 0,\n\tACK_SET = 1,\n};\n\nenum acpi_attr_enum {\n\tACPI_ATTR_LABEL_SHOW = 0,\n\tACPI_ATTR_INDEX_SHOW = 1,\n};\n\nenum acpi_backlight_type {\n\tacpi_backlight_undef = -1,\n\tacpi_backlight_none = 0,\n\tacpi_backlight_video = 1,\n\tacpi_backlight_vendor = 2,\n\tacpi_backlight_native = 3,\n\tacpi_backlight_nvidia_wmi_ec = 4,\n\tacpi_backlight_apple_gmux = 5,\n\tacpi_backlight_dell_uart = 6,\n};\n\nenum acpi_bridge_type {\n\tACPI_BRIDGE_TYPE_PCIE = 1,\n\tACPI_BRIDGE_TYPE_CXL = 2,\n};\n\nenum acpi_bus_device_type {\n\tACPI_BUS_TYPE_DEVICE = 0,\n\tACPI_BUS_TYPE_POWER = 1,\n\tACPI_BUS_TYPE_PROCESSOR = 2,\n\tACPI_BUS_TYPE_THERMAL = 3,\n\tACPI_BUS_TYPE_POWER_BUTTON = 4,\n\tACPI_BUS_TYPE_SLEEP_BUTTON = 5,\n\tACPI_BUS_TYPE_ECDT_EC = 6,\n\tACPI_BUS_DEVICE_TYPE_COUNT = 7,\n};\n\nenum acpi_cdat_type {\n\tACPI_CDAT_TYPE_DSMAS = 0,\n\tACPI_CDAT_TYPE_DSLBIS = 1,\n\tACPI_CDAT_TYPE_DSMSCIS = 2,\n\tACPI_CDAT_TYPE_DSIS = 3,\n\tACPI_CDAT_TYPE_DSEMTS = 4,\n\tACPI_CDAT_TYPE_SSLBIS = 5,\n\tACPI_CDAT_TYPE_RESERVED = 6,\n};\n\nenum acpi_cedt_type {\n\tACPI_CEDT_TYPE_CHBS = 0,\n\tACPI_CEDT_TYPE_CFMWS = 1,\n\tACPI_CEDT_TYPE_CXIMS = 2,\n\tACPI_CEDT_TYPE_RDPAS = 3,\n\tACPI_CEDT_TYPE_RESERVED = 4,\n};\n\nenum acpi_device_swnode_dev_props {\n\tACPI_DEVICE_SWNODE_DEV_ROTATION = 0,\n\tACPI_DEVICE_SWNODE_DEV_CLOCK_FREQUENCY = 1,\n\tACPI_DEVICE_SWNODE_DEV_LED_MAX_MICROAMP = 2,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_MICROAMP = 3,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_TIMEOUT_US = 4,\n\tACPI_DEVICE_SWNODE_DEV_NUM_OF = 5,\n\tACPI_DEVICE_SWNODE_DEV_NUM_ENTRIES = 6,\n};\n\nenum acpi_device_swnode_ep_props {\n\tACPI_DEVICE_SWNODE_EP_REMOTE_EP = 0,\n\tACPI_DEVICE_SWNODE_EP_BUS_TYPE = 1,\n\tACPI_DEVICE_SWNODE_EP_REG = 2,\n\tACPI_DEVICE_SWNODE_EP_CLOCK_LANES = 3,\n\tACPI_DEVICE_SWNODE_EP_DATA_LANES = 4,\n\tACPI_DEVICE_SWNODE_EP_LANE_POLARITIES = 5,\n\tACPI_DEVICE_SWNODE_EP_LINK_FREQUENCIES = 6,\n\tACPI_DEVICE_SWNODE_EP_NUM_OF = 7,\n\tACPI_DEVICE_SWNODE_EP_NUM_ENTRIES = 8,\n};\n\nenum acpi_device_swnode_port_props {\n\tACPI_DEVICE_SWNODE_PORT_REG = 0,\n\tACPI_DEVICE_SWNODE_PORT_NUM_OF = 1,\n\tACPI_DEVICE_SWNODE_PORT_NUM_ENTRIES = 2,\n};\n\nenum acpi_dmar_scope_type {\n\tACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,\n\tACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,\n\tACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,\n\tACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,\n\tACPI_DMAR_SCOPE_TYPE_HPET = 4,\n\tACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,\n\tACPI_DMAR_SCOPE_TYPE_RESERVED = 6,\n};\n\nenum acpi_dmar_type {\n\tACPI_DMAR_TYPE_HARDWARE_UNIT = 0,\n\tACPI_DMAR_TYPE_RESERVED_MEMORY = 1,\n\tACPI_DMAR_TYPE_ROOT_ATS = 2,\n\tACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,\n\tACPI_DMAR_TYPE_NAMESPACE = 4,\n\tACPI_DMAR_TYPE_SATC = 5,\n\tACPI_DMAR_TYPE_SIDP = 6,\n\tACPI_DMAR_TYPE_RESERVED = 7,\n};\n\nenum acpi_ec_event_state {\n\tEC_EVENT_READY = 0,\n\tEC_EVENT_IN_PROGRESS = 1,\n\tEC_EVENT_COMPLETE = 2,\n};\n\nenum acpi_irq_model_id {\n\tACPI_IRQ_MODEL_PIC = 0,\n\tACPI_IRQ_MODEL_IOAPIC = 1,\n\tACPI_IRQ_MODEL_IOSAPIC = 2,\n\tACPI_IRQ_MODEL_PLATFORM = 3,\n\tACPI_IRQ_MODEL_GIC = 4,\n\tACPI_IRQ_MODEL_GIC_V5 = 5,\n\tACPI_IRQ_MODEL_LPIC = 6,\n\tACPI_IRQ_MODEL_RINTC = 7,\n\tACPI_IRQ_MODEL_COUNT = 8,\n};\n\nenum acpi_madt_multiproc_wakeup_version {\n\tACPI_MADT_MP_WAKEUP_VERSION_NONE = 0,\n\tACPI_MADT_MP_WAKEUP_VERSION_V1 = 1,\n\tACPI_MADT_MP_WAKEUP_VERSION_RESERVED = 2,\n};\n\nenum acpi_madt_type {\n\tACPI_MADT_TYPE_LOCAL_APIC = 0,\n\tACPI_MADT_TYPE_IO_APIC = 1,\n\tACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,\n\tACPI_MADT_TYPE_NMI_SOURCE = 3,\n\tACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,\n\tACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,\n\tACPI_MADT_TYPE_IO_SAPIC = 6,\n\tACPI_MADT_TYPE_LOCAL_SAPIC = 7,\n\tACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,\n\tACPI_MADT_TYPE_LOCAL_X2APIC = 9,\n\tACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,\n\tACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,\n\tACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,\n\tACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,\n\tACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,\n\tACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,\n\tACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,\n\tACPI_MADT_TYPE_CORE_PIC = 17,\n\tACPI_MADT_TYPE_LIO_PIC = 18,\n\tACPI_MADT_TYPE_HT_PIC = 19,\n\tACPI_MADT_TYPE_EIO_PIC = 20,\n\tACPI_MADT_TYPE_MSI_PIC = 21,\n\tACPI_MADT_TYPE_BIO_PIC = 22,\n\tACPI_MADT_TYPE_LPC_PIC = 23,\n\tACPI_MADT_TYPE_RINTC = 24,\n\tACPI_MADT_TYPE_IMSIC = 25,\n\tACPI_MADT_TYPE_APLIC = 26,\n\tACPI_MADT_TYPE_PLIC = 27,\n\tACPI_MADT_TYPE_GICV5_IRS = 28,\n\tACPI_MADT_TYPE_GICV5_ITS = 29,\n\tACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,\n\tACPI_MADT_TYPE_RESERVED = 31,\n\tACPI_MADT_TYPE_OEM_RESERVED = 128,\n};\n\nenum acpi_pcct_type {\n\tACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2,\n\tACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3,\n\tACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4,\n\tACPI_PCCT_TYPE_HW_REG_COMM_SUBSPACE = 5,\n\tACPI_PCCT_TYPE_RESERVED = 6,\n};\n\nenum acpi_predicate {\n\tall_versions = 0,\n\tless_than_or_equal = 1,\n\tequal = 2,\n\tgreater_than_or_equal = 3,\n};\n\nenum acpi_preferred_pm_profiles {\n\tPM_UNSPECIFIED = 0,\n\tPM_DESKTOP = 1,\n\tPM_MOBILE = 2,\n\tPM_WORKSTATION = 3,\n\tPM_ENTERPRISE_SERVER = 4,\n\tPM_SOHO_SERVER = 5,\n\tPM_APPLIANCE_PC = 6,\n\tPM_PERFORMANCE_SERVER = 7,\n\tPM_TABLET = 8,\n\tNR_PM_PROFILES = 9,\n};\n\nenum acpi_reconfig_event {\n\tACPI_RECONFIG_DEVICE_ADD = 0,\n\tACPI_RECONFIG_DEVICE_REMOVE = 1,\n};\n\nenum acpi_return_package_types {\n\tACPI_PTYPE1_FIXED = 1,\n\tACPI_PTYPE1_VAR = 2,\n\tACPI_PTYPE1_OPTION = 3,\n\tACPI_PTYPE2 = 4,\n\tACPI_PTYPE2_COUNT = 5,\n\tACPI_PTYPE2_PKG_COUNT = 6,\n\tACPI_PTYPE2_FIXED = 7,\n\tACPI_PTYPE2_MIN = 8,\n\tACPI_PTYPE2_REV_FIXED = 9,\n\tACPI_PTYPE2_FIX_VAR = 10,\n\tACPI_PTYPE2_VAR_VAR = 11,\n\tACPI_PTYPE2_UUID_PAIR = 12,\n\tACPI_PTYPE_CUSTOM = 13,\n};\n\nenum acpi_srat_type {\n\tACPI_SRAT_TYPE_CPU_AFFINITY = 0,\n\tACPI_SRAT_TYPE_MEMORY_AFFINITY = 1,\n\tACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2,\n\tACPI_SRAT_TYPE_GICC_AFFINITY = 3,\n\tACPI_SRAT_TYPE_GIC_ITS_AFFINITY = 4,\n\tACPI_SRAT_TYPE_GENERIC_AFFINITY = 5,\n\tACPI_SRAT_TYPE_GENERIC_PORT_AFFINITY = 6,\n\tACPI_SRAT_TYPE_RINTC_AFFINITY = 7,\n\tACPI_SRAT_TYPE_RESERVED = 8,\n};\n\nenum acpi_subtable_type {\n\tACPI_SUBTABLE_COMMON = 0,\n\tACPI_SUBTABLE_HMAT = 1,\n\tACPI_SUBTABLE_PRMT = 2,\n\tACPI_SUBTABLE_CEDT = 3,\n\tCDAT_SUBTABLE = 4,\n};\n\nenum acpi_video_level_idx {\n\tACPI_VIDEO_AC_LEVEL = 0,\n\tACPI_VIDEO_BATTERY_LEVEL = 1,\n\tACPI_VIDEO_FIRST_LEVEL = 2,\n};\n\nenum acpi_viot_node_type {\n\tACPI_VIOT_NODE_PCI_RANGE = 1,\n\tACPI_VIOT_NODE_MMIO = 2,\n\tACPI_VIOT_NODE_VIRTIO_IOMMU_PCI = 3,\n\tACPI_VIOT_NODE_VIRTIO_IOMMU_MMIO = 4,\n\tACPI_VIOT_RESERVED = 5,\n};\n\nenum actions {\n\tREGISTER = 0,\n\tDEREGISTER = 1,\n\tCPU_DONT_CARE = 2,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum addr_stride {\n\tPTE_STRIDE = 0,\n\tPMD_STRIDE = 1,\n};\n\nenum address_markers_idx {\n\tUSER_SPACE_NR = 0,\n\tKERNEL_SPACE_NR = 1,\n\tLDT_NR = 2,\n\tLOW_KERNEL_NR = 3,\n\tVMALLOC_START_NR = 4,\n\tVMEMMAP_START_NR = 5,\n\tCPU_ENTRY_AREA_NR = 6,\n\tESPFIX_START_NR = 7,\n\tEFI_END_NR = 8,\n\tHIGH_KERNEL_NR = 9,\n\tMODULES_VADDR_NR = 10,\n\tMODULES_END_NR = 11,\n\tFIXADDR_START_NR = 12,\n\tEND_OF_SPACE_NR = 13,\n};\n\nenum af_vsockmon_op {\n\tAF_VSOCK_OP_UNKNOWN = 0,\n\tAF_VSOCK_OP_CONNECT = 1,\n\tAF_VSOCK_OP_DISCONNECT = 2,\n\tAF_VSOCK_OP_CONTROL = 3,\n\tAF_VSOCK_OP_PAYLOAD = 4,\n};\n\nenum af_vsockmon_transport {\n\tAF_VSOCK_TRANSPORT_UNKNOWN = 0,\n\tAF_VSOCK_TRANSPORT_NO_INFO = 1,\n\tAF_VSOCK_TRANSPORT_VIRTIO = 2,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum align_flags {\n\tALIGN_VA_32 = 1,\n\tALIGN_VA_64 = 2,\n};\n\nenum alloc_mode {\n\tALLOC_NORMAL = 0,\n\tALLOC_DEFER_COHERENT_FLUSH = 1,\n};\n\nenum allow_write_msrs {\n\tMSR_WRITES_ON = 0,\n\tMSR_WRITES_OFF = 1,\n\tMSR_WRITES_DEFAULT = 2,\n};\n\nenum amd_chipset_gen {\n\tNOT_AMD_CHIPSET = 0,\n\tAMD_CHIPSET_SB600 = 1,\n\tAMD_CHIPSET_SB700 = 2,\n\tAMD_CHIPSET_SB800 = 3,\n\tAMD_CHIPSET_HUDSON2 = 4,\n\tAMD_CHIPSET_BOLTON = 5,\n\tAMD_CHIPSET_YANGTZE = 6,\n\tAMD_CHIPSET_TAISHAN = 7,\n\tAMD_CHIPSET_UNKNOWN = 8,\n};\n\nenum amd_iommu_intr_mode_type {\n\tAMD_IOMMU_GUEST_IR_LEGACY = 0,\n\tAMD_IOMMU_GUEST_IR_LEGACY_GA = 1,\n\tAMD_IOMMU_GUEST_IR_VAPIC = 2,\n};\n\nenum amd_pref_core {\n\tAMD_PREF_CORE_UNKNOWN = 0,\n\tAMD_PREF_CORE_SUPPORTED = 1,\n\tAMD_PREF_CORE_UNSUPPORTED = 2,\n};\n\nenum amd_pstate_mode {\n\tAMD_PSTATE_UNDEFINED = 0,\n\tAMD_PSTATE_DISABLE = 1,\n\tAMD_PSTATE_PASSIVE = 2,\n\tAMD_PSTATE_ACTIVE = 3,\n\tAMD_PSTATE_GUIDED = 4,\n\tAMD_PSTATE_MAX = 5,\n};\n\nenum aper_size_type {\n\tU8_APER_SIZE = 0,\n\tU16_APER_SIZE = 1,\n\tU32_APER_SIZE = 2,\n\tLVL2_APER_SIZE = 3,\n\tFIXED_APER_SIZE = 4,\n};\n\nenum apic_intr_mode_id {\n\tAPIC_PIC = 0,\n\tAPIC_VIRTUAL_WIRE = 1,\n\tAPIC_VIRTUAL_WIRE_NO_CONFIG = 2,\n\tAPIC_SYMMETRIC_IO = 3,\n\tAPIC_SYMMETRIC_IO_NO_ROUTING = 4,\n};\n\nenum array_state {\n\tclear = 0,\n\tinactive = 1,\n\tsuspended = 2,\n\treadonly = 3,\n\tread_auto = 4,\n\tclean = 5,\n\tactive = 6,\n\twrite_pending = 7,\n\tactive_idle = 8,\n\tbroken = 9,\n\tbad_word = 10,\n};\n\nenum asn1_class {\n\tASN1_UNIV = 0,\n\tASN1_APPL = 1,\n\tASN1_CONT = 2,\n\tASN1_PRIV = 3,\n};\n\nenum asn1_method {\n\tASN1_PRIM = 0,\n\tASN1_CONS = 1,\n};\n\nenum asn1_opcode {\n\tASN1_OP_MATCH = 0,\n\tASN1_OP_MATCH_OR_SKIP = 1,\n\tASN1_OP_MATCH_ACT = 2,\n\tASN1_OP_MATCH_ACT_OR_SKIP = 3,\n\tASN1_OP_MATCH_JUMP = 4,\n\tASN1_OP_MATCH_JUMP_OR_SKIP = 5,\n\tASN1_OP_MATCH_ANY = 8,\n\tASN1_OP_MATCH_ANY_OR_SKIP = 9,\n\tASN1_OP_MATCH_ANY_ACT = 10,\n\tASN1_OP_MATCH_ANY_ACT_OR_SKIP = 11,\n\tASN1_OP_COND_MATCH_OR_SKIP = 17,\n\tASN1_OP_COND_MATCH_ACT_OR_SKIP = 19,\n\tASN1_OP_COND_MATCH_JUMP_OR_SKIP = 21,\n\tASN1_OP_COND_MATCH_ANY = 24,\n\tASN1_OP_COND_MATCH_ANY_OR_SKIP = 25,\n\tASN1_OP_COND_MATCH_ANY_ACT = 26,\n\tASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 27,\n\tASN1_OP_COND_FAIL = 28,\n\tASN1_OP_COMPLETE = 29,\n\tASN1_OP_ACT = 30,\n\tASN1_OP_MAYBE_ACT = 31,\n\tASN1_OP_END_SEQ = 32,\n\tASN1_OP_END_SET = 33,\n\tASN1_OP_END_SEQ_OF = 34,\n\tASN1_OP_END_SET_OF = 35,\n\tASN1_OP_END_SEQ_ACT = 36,\n\tASN1_OP_END_SET_ACT = 37,\n\tASN1_OP_END_SEQ_OF_ACT = 38,\n\tASN1_OP_END_SET_OF_ACT = 39,\n\tASN1_OP_RETURN = 40,\n\tASN1_OP__NR = 41,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum asymmetric_payload_bits {\n\tasym_crypto = 0,\n\tasym_subtype = 1,\n\tasym_key_ids = 2,\n\tasym_auth = 3,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nenum ata_quirks {\n\t__ATA_QUIRK_DIAGNOSTIC = 0,\n\t__ATA_QUIRK_NODMA = 1,\n\t__ATA_QUIRK_NONCQ = 2,\n\t__ATA_QUIRK_BROKEN_HPA = 3,\n\t__ATA_QUIRK_DISABLE = 4,\n\t__ATA_QUIRK_HPA_SIZE = 5,\n\t__ATA_QUIRK_IVB = 6,\n\t__ATA_QUIRK_STUCK_ERR = 7,\n\t__ATA_QUIRK_BRIDGE_OK = 8,\n\t__ATA_QUIRK_ATAPI_MOD16_DMA = 9,\n\t__ATA_QUIRK_FIRMWARE_WARN = 10,\n\t__ATA_QUIRK_1_5_GBPS = 11,\n\t__ATA_QUIRK_NOSETXFER = 12,\n\t__ATA_QUIRK_BROKEN_FPDMA_AA = 13,\n\t__ATA_QUIRK_DUMP_ID = 14,\n\t__ATA_QUIRK_MAX_SEC_LBA48 = 15,\n\t__ATA_QUIRK_ATAPI_DMADIR = 16,\n\t__ATA_QUIRK_NO_NCQ_TRIM = 17,\n\t__ATA_QUIRK_NOLPM = 18,\n\t__ATA_QUIRK_WD_BROKEN_LPM = 19,\n\t__ATA_QUIRK_ZERO_AFTER_TRIM = 20,\n\t__ATA_QUIRK_NO_DMA_LOG = 21,\n\t__ATA_QUIRK_NOTRIM = 22,\n\t__ATA_QUIRK_MAX_SEC = 23,\n\t__ATA_QUIRK_MAX_TRIM_128M = 24,\n\t__ATA_QUIRK_NO_NCQ_ON_ATI = 25,\n\t__ATA_QUIRK_NO_LPM_ON_ATI = 26,\n\t__ATA_QUIRK_NO_ID_DEV_LOG = 27,\n\t__ATA_QUIRK_NO_LOG_DIR = 28,\n\t__ATA_QUIRK_NO_FUA = 29,\n\t__ATA_QUIRK_MAX = 30,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum aux_ch {\n\tAUX_CH_NONE = -1,\n\tAUX_CH_A = 0,\n\tAUX_CH_B = 1,\n\tAUX_CH_C = 2,\n\tAUX_CH_D = 3,\n\tAUX_CH_E = 4,\n\tAUX_CH_F = 5,\n\tAUX_CH_G = 6,\n\tAUX_CH_H = 7,\n\tAUX_CH_I = 8,\n\tAUX_CH_USBC1 = 3,\n\tAUX_CH_USBC2 = 4,\n\tAUX_CH_USBC3 = 5,\n\tAUX_CH_USBC4 = 6,\n\tAUX_CH_USBC5 = 7,\n\tAUX_CH_USBC6 = 8,\n\tAUX_CH_D_XELPD = 7,\n\tAUX_CH_E_XELPD = 8,\n};\n\nenum avic_ipi_failure_cause {\n\tAVIC_IPI_FAILURE_INVALID_INT_TYPE = 0,\n\tAVIC_IPI_FAILURE_TARGET_NOT_RUNNING = 1,\n\tAVIC_IPI_FAILURE_INVALID_TARGET = 2,\n\tAVIC_IPI_FAILURE_INVALID_BACKING_PAGE = 3,\n\tAVIC_IPI_FAILURE_INVALID_IPI_VECTOR = 4,\n};\n\nenum avic_vcpu_action {\n\tAVIC_TOGGLE_ON_OFF = 1,\n\tAVIC_ACTIVATE = 1,\n\tAVIC_DEACTIVATE = 1,\n\tAVIC_START_RUNNING = 0,\n\tAVIC_STOP_RUNNING = 0,\n\tAVIC_START_BLOCKING = 2,\n};\n\nenum backlight_scale {\n\tBACKLIGHT_SCALE_UNKNOWN = 0,\n\tBACKLIGHT_SCALE_LINEAR = 1,\n\tBACKLIGHT_SCALE_NON_LINEAR = 2,\n};\n\nenum backlight_type {\n\tBACKLIGHT_RAW = 1,\n\tBACKLIGHT_PLATFORM = 2,\n\tBACKLIGHT_FIRMWARE = 3,\n\tBACKLIGHT_TYPE_MAX = 4,\n};\n\nenum backlight_update_reason {\n\tBACKLIGHT_UPDATE_HOTKEY = 0,\n\tBACKLIGHT_UPDATE_SYSFS = 1,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum bdb_block_id {\n\tBDB_GENERAL_FEATURES = 1,\n\tBDB_GENERAL_DEFINITIONS = 2,\n\tBDB_DISPLAY_TOGGLE = 3,\n\tBDB_MODE_SUPPORT_LIST = 4,\n\tBDB_GENERIC_MODE_TABLE = 5,\n\tBDB_EXT_MMIO_REGS = 6,\n\tBDB_SWF_IO = 7,\n\tBDB_SWF_MMIO = 8,\n\tBDB_DOT_CLOCK_OVERRIDE_ALM = 9,\n\tBDB_PSR = 9,\n\tBDB_MODE_REMOVAL_TABLE = 10,\n\tBDB_CHILD_DEVICE_TABLE = 11,\n\tBDB_DRIVER_FEATURES = 12,\n\tBDB_DRIVER_PERSISTENCE = 13,\n\tBDB_EXT_TABLE_PTRS = 14,\n\tBDB_DOT_CLOCK_OVERRIDE = 15,\n\tBDB_DISPLAY_SELECT_OLD = 16,\n\tBDB_SV_TEST_FUNCTIONS = 17,\n\tBDB_DRIVER_ROTATION = 18,\n\tBDB_DISPLAY_REMOVE_OLD = 19,\n\tBDB_OEM_CUSTOM = 20,\n\tBDB_EFP_LIST = 21,\n\tBDB_SDVO_LVDS_OPTIONS = 22,\n\tBDB_SDVO_LVDS_DTD = 23,\n\tBDB_SDVO_LVDS_PNP_ID = 24,\n\tBDB_SDVO_LVDS_PPS = 25,\n\tBDB_TV_OPTIONS = 26,\n\tBDB_EDP = 27,\n\tBDB_EFP_DTD = 28,\n\tBDB_DISPLAY_SELECT_IVB = 29,\n\tBDB_DISPLAY_REMOVE_IVB = 30,\n\tBDB_DISPLAY_SELECT_HSW = 31,\n\tBDB_DISPLAY_REMOVE_HSW = 32,\n\tBDB_LFP_OPTIONS = 40,\n\tBDB_LFP_DATA_PTRS = 41,\n\tBDB_LFP_DATA = 42,\n\tBDB_LFP_BACKLIGHT = 43,\n\tBDB_LFP_POWER = 44,\n\tBDB_EDP_BFI = 45,\n\tBDB_CHROMATICITY = 46,\n\tBDB_MIPI = 50,\n\tBDB_FIXED_SET_MODE = 51,\n\tBDB_MIPI_CONFIG = 52,\n\tBDB_MIPI_SEQUENCE = 53,\n\tBDB_RGB_PALETTE = 54,\n\tBDB_COMPRESSION_PARAMETERS_OLD = 55,\n\tBDB_COMPRESSION_PARAMETERS = 56,\n\tBDB_VSWING_PREEMPH = 57,\n\tBDB_GENERIC_DTD = 58,\n\tBDB_INT15_HOOK = 252,\n\tBDB_PRD_TABLE = 253,\n\tBDB_SKIP = 254,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bfs_result {\n\tBFS_EINVALIDNODE = -2,\n\tBFS_EQUEUEFULL = -1,\n\tBFS_RMATCH = 0,\n\tBFS_RNOMATCH = 1,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bhi_mitigations {\n\tBHI_MITIGATION_OFF = 0,\n\tBHI_MITIGATION_AUTO = 1,\n\tBHI_MITIGATION_ON = 2,\n\tBHI_MITIGATION_VMEXIT_ONLY = 3,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum bitmap_page_attr {\n\tBITMAP_PAGE_DIRTY = 0,\n\tBITMAP_PAGE_PENDING = 1,\n\tBITMAP_PAGE_NEEDWRITE = 2,\n};\n\nenum bitmap_state {\n\tBITMAP_STALE = 1,\n\tBITMAP_WRITE_ERROR = 2,\n\tBITMAP_FIRST_USE = 3,\n\tBITMAP_CLEAN = 4,\n\tBITMAP_DAEMON_BUSY = 5,\n\tBITMAP_HOSTENDIAN = 15,\n};\n\nenum blacklist_hash_type {\n\tBLACKLIST_HASH_X509_TBS = 1,\n\tBLACKLIST_HASH_BINARY = 2,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blkg_iostat_type {\n\tBLKG_IOSTAT_READ = 0,\n\tBLKG_IOSTAT_WRITE = 1,\n\tBLKG_IOSTAT_DISCARD = 2,\n\tBLKG_IOSTAT_NR = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum blktrace_cat {\n\tBLK_TC_READ = 1,\n\tBLK_TC_WRITE = 2,\n\tBLK_TC_FLUSH = 4,\n\tBLK_TC_SYNC = 8,\n\tBLK_TC_SYNCIO = 8,\n\tBLK_TC_QUEUE = 16,\n\tBLK_TC_REQUEUE = 32,\n\tBLK_TC_ISSUE = 64,\n\tBLK_TC_COMPLETE = 128,\n\tBLK_TC_FS = 256,\n\tBLK_TC_PC = 512,\n\tBLK_TC_NOTIFY = 1024,\n\tBLK_TC_AHEAD = 2048,\n\tBLK_TC_META = 4096,\n\tBLK_TC_DISCARD = 8192,\n\tBLK_TC_DRV_DATA = 16384,\n\tBLK_TC_FUA = 32768,\n\tBLK_TC_END_V1 = 32768,\n\tBLK_TC_ZONE_APPEND = 65536,\n\tBLK_TC_ZONE_RESET = 131072,\n\tBLK_TC_ZONE_RESET_ALL = 262144,\n\tBLK_TC_ZONE_FINISH = 524288,\n\tBLK_TC_ZONE_OPEN = 1048576,\n\tBLK_TC_ZONE_CLOSE = 2097152,\n\tBLK_TC_WRITE_ZEROES = 4194304,\n\tBLK_TC_END_V2 = 4194304,\n};\n\nenum blktrace_notify {\n\t__BLK_TN_PROCESS = 0,\n\t__BLK_TN_TIMESTAMP = 1,\n\t__BLK_TN_MESSAGE = 2,\n\t__BLK_TN_CGROUP = 256,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_43bit_dma = 1,\n\tboard_ahci_ign_iferr = 2,\n\tboard_ahci_no_debounce_delay = 3,\n\tboard_ahci_no_msi = 4,\n\tboard_ahci_pcs_quirk = 5,\n\tboard_ahci_pcs_quirk_no_devslp = 6,\n\tboard_ahci_pcs_quirk_no_sntf = 7,\n\tboard_ahci_yes_fbs = 8,\n\tboard_ahci_yes_fbs_atapi_dma = 9,\n\tboard_ahci_al = 10,\n\tboard_ahci_avn = 11,\n\tboard_ahci_mcp65 = 12,\n\tboard_ahci_mcp77 = 13,\n\tboard_ahci_mcp89 = 14,\n\tboard_ahci_mv = 15,\n\tboard_ahci_sb600 = 16,\n\tboard_ahci_sb700 = 17,\n\tboard_ahci_vt8251 = 18,\n\tboard_ahci_mcp_linux = 12,\n\tboard_ahci_mcp67 = 12,\n\tboard_ahci_mcp73 = 12,\n\tboard_ahci_mcp79 = 13,\n};\n\nenum bochs_types {\n\tBOCHS_QEMU_STDVGA = 0,\n\tBOCHS_SIMICS = 1,\n\tBOCHS_UNKNOWN = 2,\n};\n\nenum bootmem_type {\n\tMEMORY_HOTPLUG_MIN_BOOTMEM_TYPE = 1,\n\tSECTION_INFO = 1,\n\tMIX_SECTION_INFO = 2,\n\tNODE_INFO = 3,\n\tMEMORY_HOTPLUG_MAX_BOOTMEM_TYPE = 3,\n};\n\nenum bp_type_idx {\n\tTYPE_INST = 0,\n\tTYPE_DATA = 0,\n\tTYPE_MAX = 1,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_perf_event_type {\n\tBPF_PERF_EVENT_UNSPEC = 0,\n\tBPF_PERF_EVENT_UPROBE = 1,\n\tBPF_PERF_EVENT_URETPROBE = 2,\n\tBPF_PERF_EVENT_KPROBE = 3,\n\tBPF_PERF_EVENT_KRETPROBE = 4,\n\tBPF_PERF_EVENT_TRACEPOINT = 5,\n\tBPF_PERF_EVENT_EVENT = 6,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum cache_tag_type {\n\tCACHE_TAG_IOTLB = 0,\n\tCACHE_TAG_DEVTLB = 1,\n\tCACHE_TAG_NESTING_IOTLB = 2,\n\tCACHE_TAG_NESTING_DEVTLB = 3,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum cc_attr {\n\tCC_ATTR_MEM_ENCRYPT = 0,\n\tCC_ATTR_HOST_MEM_ENCRYPT = 1,\n\tCC_ATTR_GUEST_MEM_ENCRYPT = 2,\n\tCC_ATTR_GUEST_STATE_ENCRYPT = 3,\n\tCC_ATTR_GUEST_UNROLL_STRING_IO = 4,\n\tCC_ATTR_GUEST_SEV_SNP = 5,\n\tCC_ATTR_GUEST_SNP_SECURE_TSC = 6,\n\tCC_ATTR_HOST_SEV_SNP = 7,\n\tCC_ATTR_SNP_SECURE_AVIC = 8,\n};\n\nenum cc_vendor {\n\tCC_VENDOR_NONE = 0,\n\tCC_VENDOR_AMD = 1,\n\tCC_VENDOR_INTEL = 2,\n};\n\nenum cea_speaker_placement {\n\tFL = 1,\n\tFC = 2,\n\tFR = 4,\n\tFLC = 8,\n\tFRC = 16,\n\tRL = 32,\n\tRC = 64,\n\tRR = 128,\n\tRLC = 256,\n\tRRC = 512,\n\tLFE = 1024,\n\tFLW = 2048,\n\tFRW = 4096,\n\tFLH = 8192,\n\tFCH = 16384,\n\tFRH = 32768,\n\tTC = 65536,\n};\n\nenum cfi_mode {\n\tCFI_AUTO = 0,\n\tCFI_OFF = 1,\n\tCFI_KCFI = 2,\n\tCFI_FINEIBT = 3,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_bpf_attach_type {\n\tCGROUP_BPF_ATTACH_TYPE_INVALID = -1,\n\tCGROUP_INET_INGRESS = 0,\n\tCGROUP_INET_EGRESS = 1,\n\tCGROUP_INET_SOCK_CREATE = 2,\n\tCGROUP_SOCK_OPS = 3,\n\tCGROUP_DEVICE = 4,\n\tCGROUP_INET4_BIND = 5,\n\tCGROUP_INET6_BIND = 6,\n\tCGROUP_INET4_CONNECT = 7,\n\tCGROUP_INET6_CONNECT = 8,\n\tCGROUP_UNIX_CONNECT = 9,\n\tCGROUP_INET4_POST_BIND = 10,\n\tCGROUP_INET6_POST_BIND = 11,\n\tCGROUP_UDP4_SENDMSG = 12,\n\tCGROUP_UDP6_SENDMSG = 13,\n\tCGROUP_UNIX_SENDMSG = 14,\n\tCGROUP_SYSCTL = 15,\n\tCGROUP_UDP4_RECVMSG = 16,\n\tCGROUP_UDP6_RECVMSG = 17,\n\tCGROUP_UNIX_RECVMSG = 18,\n\tCGROUP_GETSOCKOPT = 19,\n\tCGROUP_SETSOCKOPT = 20,\n\tCGROUP_INET4_GETPEERNAME = 21,\n\tCGROUP_INET6_GETPEERNAME = 22,\n\tCGROUP_UNIX_GETPEERNAME = 23,\n\tCGROUP_INET4_GETSOCKNAME = 24,\n\tCGROUP_INET6_GETSOCKNAME = 25,\n\tCGROUP_UNIX_GETSOCKNAME = 26,\n\tCGROUP_INET_SOCK_RELEASE = 27,\n\tCGROUP_LSM_START = 28,\n\tCGROUP_LSM_END = 27,\n\tMAX_CGROUP_BPF_ATTACH_TYPE = 28,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_COUNT = 0,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tio_cgrp_id = 3,\n\tdevices_cgrp_id = 4,\n\tfreezer_cgrp_id = 5,\n\tnet_cls_cgrp_id = 6,\n\tperf_event_cgrp_id = 7,\n\tnet_prio_cgrp_id = 8,\n\thugetlb_cgrp_id = 9,\n\tpids_cgrp_id = 10,\n\trdma_cgrp_id = 11,\n\tmisc_cgrp_id = 12,\n\tdebug_cgrp_id = 13,\n\tCGROUP_SUBSYS_COUNT = 14,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum check_link_response {\n\tHDCP_LINK_PROTECTED = 0,\n\tHDCP_TOPOLOGY_CHANGE = 1,\n\tHDCP_LINK_INTEGRITY_FAILURE = 2,\n\tHDCP_REAUTH_REQUEST = 3,\n};\n\nenum chipset_type {\n\tNOT_SUPPORTED = 0,\n\tSUPPORTED = 1,\n};\n\nenum class_map_type {\n\tDD_CLASS_TYPE_DISJOINT_BITS = 0,\n\tDD_CLASS_TYPE_LEVEL_NUM = 1,\n\tDD_CLASS_TYPE_DISJOINT_NAMES = 2,\n\tDD_CLASS_TYPE_LEVEL_NAMES = 3,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum console_type {\n\tCONS_BASIC = 1,\n\tCONS_EXTENDED = 2,\n};\n\nenum context {\n\tIN_KERNEL = 1,\n\tIN_USER = 2,\n\tIN_KERNEL_RECOV = 3,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cp_error_code {\n\tCP_EC = 32767,\n\tCP_RET = 1,\n\tCP_IRET = 2,\n\tCP_ENDBR = 3,\n\tCP_RSTRORSSP = 4,\n\tCP_SETSSBSY = 5,\n\tCP_ENCL = 32768,\n};\n\nenum cpa_warn {\n\tCPA_CONFLICT = 0,\n\tCPA_PROTECT = 1,\n\tCPA_DETECT = 2,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cppc_regs {\n\tHIGHEST_PERF = 0,\n\tNOMINAL_PERF = 1,\n\tLOW_NON_LINEAR_PERF = 2,\n\tLOWEST_PERF = 3,\n\tGUARANTEED_PERF = 4,\n\tDESIRED_PERF = 5,\n\tMIN_PERF = 6,\n\tMAX_PERF = 7,\n\tPERF_REDUC_TOLERANCE = 8,\n\tTIME_WINDOW = 9,\n\tCTR_WRAP_TIME = 10,\n\tREFERENCE_CTR = 11,\n\tDELIVERED_CTR = 12,\n\tPERF_LIMITED = 13,\n\tENABLE = 14,\n\tAUTO_SEL_ENABLE = 15,\n\tAUTO_ACT_WINDOW = 16,\n\tENERGY_PERF = 17,\n\tREFERENCE_PERF = 18,\n\tLOWEST_FREQ = 19,\n\tNOMINAL_FREQ = 20,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tCPUTIME_FORCEIDLE = 10,\n\tNR_STATS = 11,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum cpuid_leafs {\n\tCPUID_1_EDX = 0,\n\tCPUID_8000_0001_EDX = 1,\n\tCPUID_8086_0001_EDX = 2,\n\tCPUID_LNX_1 = 3,\n\tCPUID_1_ECX = 4,\n\tCPUID_C000_0001_EDX = 5,\n\tCPUID_8000_0001_ECX = 6,\n\tCPUID_LNX_2 = 7,\n\tCPUID_LNX_3 = 8,\n\tCPUID_7_0_EBX = 9,\n\tCPUID_D_1_EAX = 10,\n\tCPUID_LNX_4 = 11,\n\tCPUID_7_1_EAX = 12,\n\tCPUID_8000_0008_EBX = 13,\n\tCPUID_6_EAX = 14,\n\tCPUID_8000_000A_EDX = 15,\n\tCPUID_7_ECX = 16,\n\tCPUID_LNX_6 = 17,\n\tCPUID_7_EDX = 18,\n\tCPUID_8000_001F_EAX = 19,\n\tCPUID_8000_0021_EAX = 20,\n\tCPUID_LNX_5 = 21,\n\tNR_CPUID_WORDS = 22,\n};\n\nenum cpuid_regs_idx {\n\tCPUID_EAX = 0,\n\tCPUID_EBX = 1,\n\tCPUID_ECX = 2,\n\tCPUID_EDX = 3,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum cti_port_type {\n\tCTI_PORT_TYPE_NONE = 0,\n\tCTI_PORT_TYPE_RS232 = 1,\n\tCTI_PORT_TYPE_RS422_485 = 2,\n\tCTI_PORT_TYPE_RS232_422_485_HW = 3,\n\tCTI_PORT_TYPE_RS232_422_485_SW = 4,\n\tCTI_PORT_TYPE_RS232_422_485_4B = 5,\n\tCTI_PORT_TYPE_RS232_422_485_2B = 6,\n\tCTI_PORT_TYPE_MAX = 7,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum dax_access_mode {\n\tDAX_ACCESS = 0,\n\tDAX_RECOVERY_WRITE = 1,\n};\n\nenum dax_device_flags {\n\tDAXDEV_ALIVE = 0,\n\tDAXDEV_WRITE_CACHE = 1,\n\tDAXDEV_SYNC = 2,\n\tDAXDEV_NOCACHE = 3,\n\tDAXDEV_NOMC = 4,\n};\n\nenum dax_driver_type {\n\tDAXDRV_KMEM_TYPE = 0,\n\tDAXDRV_DEVICE_TYPE = 1,\n};\n\nenum dax_wake_mode {\n\tWAKE_ALL = 0,\n\tWAKE_NEXT = 1,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dbuf_slice {\n\tDBUF_S1 = 0,\n\tDBUF_S2 = 1,\n\tDBUF_S3 = 2,\n\tDBUF_S4 = 3,\n\tI915_MAX_DBUF_SLICES = 4,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum depot_counter_id {\n\tDEPOT_COUNTER_REFD_ALLOCS = 0,\n\tDEPOT_COUNTER_REFD_FREES = 1,\n\tDEPOT_COUNTER_REFD_INUSE = 2,\n\tDEPOT_COUNTER_FREELIST_SIZE = 3,\n\tDEPOT_COUNTER_PERSIST_COUNT = 4,\n\tDEPOT_COUNTER_PERSIST_BYTES = 5,\n\tDEPOT_COUNTER_COUNT = 6,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum devcg_behavior {\n\tDEVCG_DEFAULT_NONE = 0,\n\tDEVCG_DEFAULT_ALLOW = 1,\n\tDEVCG_DEFAULT_DENY = 2,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum die_val {\n\tDIE_OOPS = 1,\n\tDIE_INT3 = 2,\n\tDIE_DEBUG = 3,\n\tDIE_PANIC = 4,\n\tDIE_NMI = 5,\n\tDIE_DIE = 6,\n\tDIE_KERNELDEBUG = 7,\n\tDIE_TRAP = 8,\n\tDIE_GPF = 9,\n\tDIE_CALL = 10,\n\tDIE_PAGE_FAULT = 11,\n\tDIE_NMIUNKNOWN = 12,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dm_io_mem_type {\n\tDM_IO_PAGE_LIST = 0,\n\tDM_IO_BIO = 1,\n\tDM_IO_VMA = 2,\n\tDM_IO_KMEM = 3,\n};\n\nenum dm_queue_mode {\n\tDM_TYPE_NONE = 0,\n\tDM_TYPE_BIO_BASED = 1,\n\tDM_TYPE_REQUEST_BASED = 2,\n\tDM_TYPE_DAX_BIO_BASED = 3,\n};\n\nenum dm_raid1_error {\n\tDM_RAID1_WRITE_ERROR = 0,\n\tDM_RAID1_FLUSH_ERROR = 1,\n\tDM_RAID1_SYNC_ERROR = 2,\n\tDM_RAID1_READ_ERROR = 3,\n};\n\nenum dm_rh_region_states {\n\tDM_RH_CLEAN = 1,\n\tDM_RH_DIRTY = 2,\n\tDM_RH_NOSYNC = 4,\n\tDM_RH_RECOVERING = 8,\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n\tDMA_PREP_REPEAT = 256,\n\tDMA_PREP_LOAD_EOT = 512,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SEQNO64_BIT = 0,\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 1,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 2,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 3,\n\tDMA_FENCE_FLAG_USER_BITS = 4,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nenum dma_resv_usage {\n\tDMA_RESV_USAGE_KERNEL = 0,\n\tDMA_RESV_USAGE_WRITE = 1,\n\tDMA_RESV_USAGE_READ = 2,\n\tDMA_RESV_USAGE_BOOKKEEP = 3,\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n\tDMA_SLAVE_BUSWIDTH_128_BYTES = 128,\n};\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n\tDMA_OUT_OF_ORDER = 4,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_COMPLETION_NO_ORDER = 13,\n\tDMA_REPEAT = 14,\n\tDMA_LOAD_EOT = 15,\n\tDMA_TX_TYPE_END = 16,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n\tDMAENGINE_ALIGN_128_BYTES = 7,\n\tDMAENGINE_ALIGN_256_BYTES = 8,\n};\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nenum dmc_event_id {\n\tDMC_EVENT_TRUE = 0,\n\tDMC_EVENT_FALSE = 1,\n};\n\nenum dmi_device_type {\n\tDMI_DEV_TYPE_ANY = 0,\n\tDMI_DEV_TYPE_OTHER = 1,\n\tDMI_DEV_TYPE_UNKNOWN = 2,\n\tDMI_DEV_TYPE_VIDEO = 3,\n\tDMI_DEV_TYPE_SCSI = 4,\n\tDMI_DEV_TYPE_ETHERNET = 5,\n\tDMI_DEV_TYPE_TOKENRING = 6,\n\tDMI_DEV_TYPE_SOUND = 7,\n\tDMI_DEV_TYPE_PATA = 8,\n\tDMI_DEV_TYPE_SATA = 9,\n\tDMI_DEV_TYPE_SAS = 10,\n\tDMI_DEV_TYPE_IPMI = -1,\n\tDMI_DEV_TYPE_OEM_STRING = -2,\n\tDMI_DEV_TYPE_DEV_ONBOARD = -3,\n\tDMI_DEV_TYPE_DEV_SLOT = -4,\n};\n\nenum dmi_entry_type {\n\tDMI_ENTRY_BIOS = 0,\n\tDMI_ENTRY_SYSTEM = 1,\n\tDMI_ENTRY_BASEBOARD = 2,\n\tDMI_ENTRY_CHASSIS = 3,\n\tDMI_ENTRY_PROCESSOR = 4,\n\tDMI_ENTRY_MEM_CONTROLLER = 5,\n\tDMI_ENTRY_MEM_MODULE = 6,\n\tDMI_ENTRY_CACHE = 7,\n\tDMI_ENTRY_PORT_CONNECTOR = 8,\n\tDMI_ENTRY_SYSTEM_SLOT = 9,\n\tDMI_ENTRY_ONBOARD_DEVICE = 10,\n\tDMI_ENTRY_OEMSTRINGS = 11,\n\tDMI_ENTRY_SYSCONF = 12,\n\tDMI_ENTRY_BIOS_LANG = 13,\n\tDMI_ENTRY_GROUP_ASSOC = 14,\n\tDMI_ENTRY_SYSTEM_EVENT_LOG = 15,\n\tDMI_ENTRY_PHYS_MEM_ARRAY = 16,\n\tDMI_ENTRY_MEM_DEVICE = 17,\n\tDMI_ENTRY_32_MEM_ERROR = 18,\n\tDMI_ENTRY_MEM_ARRAY_MAPPED_ADDR = 19,\n\tDMI_ENTRY_MEM_DEV_MAPPED_ADDR = 20,\n\tDMI_ENTRY_BUILTIN_POINTING_DEV = 21,\n\tDMI_ENTRY_PORTABLE_BATTERY = 22,\n\tDMI_ENTRY_SYSTEM_RESET = 23,\n\tDMI_ENTRY_HW_SECURITY = 24,\n\tDMI_ENTRY_SYSTEM_POWER_CONTROLS = 25,\n\tDMI_ENTRY_VOLTAGE_PROBE = 26,\n\tDMI_ENTRY_COOLING_DEV = 27,\n\tDMI_ENTRY_TEMP_PROBE = 28,\n\tDMI_ENTRY_ELECTRICAL_CURRENT_PROBE = 29,\n\tDMI_ENTRY_OOB_REMOTE_ACCESS = 30,\n\tDMI_ENTRY_BIS_ENTRY = 31,\n\tDMI_ENTRY_SYSTEM_BOOT = 32,\n\tDMI_ENTRY_MGMT_DEV = 33,\n\tDMI_ENTRY_MGMT_DEV_COMPONENT = 34,\n\tDMI_ENTRY_MGMT_DEV_THRES = 35,\n\tDMI_ENTRY_MEM_CHANNEL = 36,\n\tDMI_ENTRY_IPMI_DEV = 37,\n\tDMI_ENTRY_SYS_POWER_SUPPLY = 38,\n\tDMI_ENTRY_ADDITIONAL = 39,\n\tDMI_ENTRY_ONBOARD_DEV_EXT = 40,\n\tDMI_ENTRY_MGMT_CONTROLLER_HOST = 41,\n\tDMI_ENTRY_INACTIVE = 126,\n\tDMI_ENTRY_END_OF_TABLE = 127,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dock_callback_type {\n\tDOCK_CALL_HANDLER = 0,\n\tDOCK_CALL_FIXUP = 1,\n\tDOCK_CALL_UEVENT = 2,\n};\n\nenum dp_colorimetry {\n\tDP_COLORIMETRY_DEFAULT = 0,\n\tDP_COLORIMETRY_RGB_WIDE_FIXED = 1,\n\tDP_COLORIMETRY_BT709_YCC = 1,\n\tDP_COLORIMETRY_RGB_WIDE_FLOAT = 2,\n\tDP_COLORIMETRY_XVYCC_601 = 2,\n\tDP_COLORIMETRY_OPRGB = 3,\n\tDP_COLORIMETRY_XVYCC_709 = 3,\n\tDP_COLORIMETRY_DCI_P3_RGB = 4,\n\tDP_COLORIMETRY_SYCC_601 = 4,\n\tDP_COLORIMETRY_RGB_CUSTOM = 5,\n\tDP_COLORIMETRY_OPYCC_601 = 5,\n\tDP_COLORIMETRY_BT2020_RGB = 6,\n\tDP_COLORIMETRY_BT2020_CYCC = 6,\n\tDP_COLORIMETRY_BT2020_YCC = 7,\n};\n\nenum dp_content_type {\n\tDP_CONTENT_TYPE_NOT_DEFINED = 0,\n\tDP_CONTENT_TYPE_GRAPHICS = 1,\n\tDP_CONTENT_TYPE_PHOTO = 2,\n\tDP_CONTENT_TYPE_VIDEO = 3,\n\tDP_CONTENT_TYPE_GAME = 4,\n};\n\nenum dp_dynamic_range {\n\tDP_DYNAMIC_RANGE_VESA = 0,\n\tDP_DYNAMIC_RANGE_CTA = 1,\n};\n\nenum dp_pixelformat {\n\tDP_PIXELFORMAT_RGB = 0,\n\tDP_PIXELFORMAT_YUV444 = 1,\n\tDP_PIXELFORMAT_YUV422 = 2,\n\tDP_PIXELFORMAT_YUV420 = 3,\n\tDP_PIXELFORMAT_Y_ONLY = 4,\n\tDP_PIXELFORMAT_RAW = 5,\n\tDP_PIXELFORMAT_RESERVED = 6,\n};\n\nenum dpio_channel {\n\tDPIO_CH0 = 0,\n\tDPIO_CH1 = 1,\n};\n\nenum dpio_phy {\n\tDPIO_PHY0 = 0,\n\tDPIO_PHY1 = 1,\n\tDPIO_PHY2 = 2,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum drbg_prefixes {\n\tDRBG_PREFIX0 = 0,\n\tDRBG_PREFIX1 = 1,\n\tDRBG_PREFIX2 = 2,\n\tDRBG_PREFIX3 = 3,\n};\n\nenum drbg_seed_state {\n\tDRBG_SEED_STATE_UNSEEDED = 0,\n\tDRBG_SEED_STATE_PARTIAL = 1,\n\tDRBG_SEED_STATE_FULL = 2,\n};\n\nenum drm_bridge_attach_flags {\n\tDRM_BRIDGE_ATTACH_NO_CONNECTOR = 1,\n};\n\nenum drm_bridge_ops {\n\tDRM_BRIDGE_OP_DETECT = 1,\n\tDRM_BRIDGE_OP_EDID = 2,\n\tDRM_BRIDGE_OP_HPD = 4,\n\tDRM_BRIDGE_OP_MODES = 8,\n\tDRM_BRIDGE_OP_HDMI = 16,\n\tDRM_BRIDGE_OP_HDMI_AUDIO = 32,\n\tDRM_BRIDGE_OP_DP_AUDIO = 64,\n\tDRM_BRIDGE_OP_HDMI_CEC_NOTIFIER = 128,\n\tDRM_BRIDGE_OP_HDMI_CEC_ADAPTER = 256,\n\tDRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME = 512,\n\tDRM_BRIDGE_OP_HDMI_SPD_INFOFRAME = 1024,\n};\n\nenum drm_buddy_free_tree {\n\tDRM_BUDDY_CLEAR_TREE = 0,\n\tDRM_BUDDY_DIRTY_TREE = 1,\n\tDRM_BUDDY_MAX_FREE_TREES = 2,\n};\n\nenum drm_color_encoding {\n\tDRM_COLOR_YCBCR_BT601 = 0,\n\tDRM_COLOR_YCBCR_BT709 = 1,\n\tDRM_COLOR_YCBCR_BT2020 = 2,\n\tDRM_COLOR_ENCODING_MAX = 3,\n};\n\nenum drm_color_lut_tests {\n\tDRM_COLOR_LUT_EQUAL_CHANNELS = 1,\n\tDRM_COLOR_LUT_NON_DECREASING = 2,\n};\n\nenum drm_color_range {\n\tDRM_COLOR_YCBCR_LIMITED_RANGE = 0,\n\tDRM_COLOR_YCBCR_FULL_RANGE = 1,\n\tDRM_COLOR_RANGE_MAX = 2,\n};\n\nenum drm_colorop_curve_1d_type {\n\tDRM_COLOROP_1D_CURVE_SRGB_EOTF = 0,\n\tDRM_COLOROP_1D_CURVE_SRGB_INV_EOTF = 1,\n\tDRM_COLOROP_1D_CURVE_PQ_125_EOTF = 2,\n\tDRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF = 3,\n\tDRM_COLOROP_1D_CURVE_BT2020_INV_OETF = 4,\n\tDRM_COLOROP_1D_CURVE_BT2020_OETF = 5,\n\tDRM_COLOROP_1D_CURVE_GAMMA22 = 6,\n\tDRM_COLOROP_1D_CURVE_GAMMA22_INV = 7,\n\tDRM_COLOROP_1D_CURVE_COUNT = 8,\n};\n\nenum drm_colorop_lut1d_interpolation_type {\n\tDRM_COLOROP_LUT1D_INTERPOLATION_LINEAR = 0,\n};\n\nenum drm_colorop_lut3d_interpolation_type {\n\tDRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL = 0,\n};\n\nenum drm_colorop_type {\n\tDRM_COLOROP_1D_CURVE = 0,\n\tDRM_COLOROP_1D_LUT = 1,\n\tDRM_COLOROP_CTM_3X4 = 2,\n\tDRM_COLOROP_MULTIPLIER = 3,\n\tDRM_COLOROP_3D_LUT = 4,\n};\n\nenum drm_colorspace {\n\tDRM_MODE_COLORIMETRY_DEFAULT = 0,\n\tDRM_MODE_COLORIMETRY_NO_DATA = 0,\n\tDRM_MODE_COLORIMETRY_SMPTE_170M_YCC = 1,\n\tDRM_MODE_COLORIMETRY_BT709_YCC = 2,\n\tDRM_MODE_COLORIMETRY_XVYCC_601 = 3,\n\tDRM_MODE_COLORIMETRY_XVYCC_709 = 4,\n\tDRM_MODE_COLORIMETRY_SYCC_601 = 5,\n\tDRM_MODE_COLORIMETRY_OPYCC_601 = 6,\n\tDRM_MODE_COLORIMETRY_OPRGB = 7,\n\tDRM_MODE_COLORIMETRY_BT2020_CYCC = 8,\n\tDRM_MODE_COLORIMETRY_BT2020_RGB = 9,\n\tDRM_MODE_COLORIMETRY_BT2020_YCC = 10,\n\tDRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 = 11,\n\tDRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER = 12,\n\tDRM_MODE_COLORIMETRY_RGB_WIDE_FIXED = 13,\n\tDRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT = 14,\n\tDRM_MODE_COLORIMETRY_BT601_YCC = 15,\n\tDRM_MODE_COLORIMETRY_COUNT = 16,\n};\n\nenum drm_connector_force {\n\tDRM_FORCE_UNSPECIFIED = 0,\n\tDRM_FORCE_OFF = 1,\n\tDRM_FORCE_ON = 2,\n\tDRM_FORCE_ON_DIGITAL = 3,\n};\n\nenum drm_connector_registration_state {\n\tDRM_CONNECTOR_INITIALIZING = 0,\n\tDRM_CONNECTOR_REGISTERED = 1,\n\tDRM_CONNECTOR_UNREGISTERED = 2,\n};\n\nenum drm_connector_status {\n\tconnector_status_connected = 1,\n\tconnector_status_disconnected = 2,\n\tconnector_status_unknown = 3,\n};\n\nenum drm_connector_tv_mode {\n\tDRM_MODE_TV_MODE_NTSC = 0,\n\tDRM_MODE_TV_MODE_NTSC_443 = 1,\n\tDRM_MODE_TV_MODE_NTSC_J = 2,\n\tDRM_MODE_TV_MODE_PAL = 3,\n\tDRM_MODE_TV_MODE_PAL_M = 4,\n\tDRM_MODE_TV_MODE_PAL_N = 5,\n\tDRM_MODE_TV_MODE_SECAM = 6,\n\tDRM_MODE_TV_MODE_MONOCHROME = 7,\n\tDRM_MODE_TV_MODE_MAX = 8,\n};\n\nenum drm_debug_category {\n\tDRM_UT_CORE = 0,\n\tDRM_UT_DRIVER = 1,\n\tDRM_UT_KMS = 2,\n\tDRM_UT_PRIME = 3,\n\tDRM_UT_ATOMIC = 4,\n\tDRM_UT_VBL = 5,\n\tDRM_UT_STATE = 6,\n\tDRM_UT_LEASE = 7,\n\tDRM_UT_DP = 8,\n\tDRM_UT_DRMRES = 9,\n};\n\nenum drm_dp_dual_mode_type {\n\tDRM_DP_DUAL_MODE_NONE = 0,\n\tDRM_DP_DUAL_MODE_UNKNOWN = 1,\n\tDRM_DP_DUAL_MODE_TYPE1_DVI = 2,\n\tDRM_DP_DUAL_MODE_TYPE1_HDMI = 3,\n\tDRM_DP_DUAL_MODE_TYPE2_DVI = 4,\n\tDRM_DP_DUAL_MODE_TYPE2_HDMI = 5,\n\tDRM_DP_DUAL_MODE_LSPCON = 6,\n};\n\nenum drm_dp_mst_mode {\n\tDRM_DP_SST = 0,\n\tDRM_DP_MST = 1,\n\tDRM_DP_SST_SIDEBAND_MSG = 2,\n};\n\nenum drm_dp_mst_payload_allocation {\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_NONE = 0,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_LOCAL = 1,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_DFP = 2,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_REMOTE = 3,\n};\n\nenum drm_dp_phy {\n\tDP_PHY_DPRX = 0,\n\tDP_PHY_LTTPR1 = 1,\n\tDP_PHY_LTTPR2 = 2,\n\tDP_PHY_LTTPR3 = 3,\n\tDP_PHY_LTTPR4 = 4,\n\tDP_PHY_LTTPR5 = 5,\n\tDP_PHY_LTTPR6 = 6,\n\tDP_PHY_LTTPR7 = 7,\n\tDP_PHY_LTTPR8 = 8,\n\tDP_MAX_LTTPR_COUNT = 8,\n};\n\nenum drm_dp_quirk {\n\tDP_DPCD_QUIRK_CONSTANT_N = 0,\n\tDP_DPCD_QUIRK_NO_PSR = 1,\n\tDP_DPCD_QUIRK_NO_SINK_COUNT = 2,\n\tDP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD = 3,\n\tDP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS = 4,\n\tDP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC = 5,\n\tDP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT = 6,\n};\n\nenum drm_driver_feature {\n\tDRIVER_GEM = 1,\n\tDRIVER_MODESET = 2,\n\tDRIVER_RENDER = 8,\n\tDRIVER_ATOMIC = 16,\n\tDRIVER_SYNCOBJ = 32,\n\tDRIVER_SYNCOBJ_TIMELINE = 64,\n\tDRIVER_COMPUTE_ACCEL = 128,\n\tDRIVER_GEM_GPUVA = 256,\n\tDRIVER_CURSOR_HOTSPOT = 512,\n\tDRIVER_USE_AGP = 33554432,\n\tDRIVER_LEGACY = 67108864,\n\tDRIVER_PCI_DMA = 134217728,\n\tDRIVER_SG = 268435456,\n\tDRIVER_HAVE_DMA = 536870912,\n\tDRIVER_HAVE_IRQ = 1073741824,\n};\n\nenum drm_dsc_params_type {\n\tDRM_DSC_1_2_444 = 0,\n\tDRM_DSC_1_1_PRE_SCR = 1,\n\tDRM_DSC_1_2_422 = 2,\n\tDRM_DSC_1_2_420 = 3,\n};\n\nenum drm_edid_internal_quirk {\n\tEDID_QUIRK_PREFER_LARGE_60 = 1,\n\tEDID_QUIRK_135_CLOCK_TOO_HIGH = 2,\n\tEDID_QUIRK_PREFER_LARGE_75 = 3,\n\tEDID_QUIRK_DETAILED_IN_CM = 4,\n\tEDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 5,\n\tEDID_QUIRK_DETAILED_SYNC_PP = 6,\n\tEDID_QUIRK_FORCE_REDUCED_BLANKING = 7,\n\tEDID_QUIRK_FORCE_8BPC = 8,\n\tEDID_QUIRK_FORCE_12BPC = 9,\n\tEDID_QUIRK_FORCE_6BPC = 10,\n\tEDID_QUIRK_FORCE_10BPC = 11,\n\tEDID_QUIRK_NON_DESKTOP = 12,\n\tEDID_QUIRK_CAP_DSC_15BPP = 13,\n};\n\nenum drm_edid_quirk {\n\tDRM_EDID_QUIRK_DP_DPCD_PROBE = 0,\n\tDRM_EDID_QUIRK_NUM = 1,\n};\n\nenum drm_gem_object_status {\n\tDRM_GEM_OBJECT_RESIDENT = 1,\n\tDRM_GEM_OBJECT_PURGEABLE = 2,\n\tDRM_GEM_OBJECT_ACTIVE = 4,\n};\n\nenum drm_gpuva_flags {\n\tDRM_GPUVA_INVALIDATED = 1,\n\tDRM_GPUVA_SPARSE = 2,\n\tDRM_GPUVA_USERBITS = 4,\n};\n\nenum drm_gpuva_op_type {\n\tDRM_GPUVA_OP_MAP = 0,\n\tDRM_GPUVA_OP_REMAP = 1,\n\tDRM_GPUVA_OP_UNMAP = 2,\n\tDRM_GPUVA_OP_PREFETCH = 3,\n\tDRM_GPUVA_OP_DRIVER = 4,\n};\n\nenum drm_gpuvm_flags {\n\tDRM_GPUVM_RESV_PROTECTED = 1,\n\tDRM_GPUVM_IMMEDIATE_MODE = 2,\n\tDRM_GPUVM_USERBITS = 4,\n};\n\nenum drm_hdmi_broadcast_rgb {\n\tDRM_HDMI_BROADCAST_RGB_AUTO = 0,\n\tDRM_HDMI_BROADCAST_RGB_FULL = 1,\n\tDRM_HDMI_BROADCAST_RGB_LIMITED = 2,\n};\n\nenum drm_i915_gem_engine_class {\n\tI915_ENGINE_CLASS_RENDER = 0,\n\tI915_ENGINE_CLASS_COPY = 1,\n\tI915_ENGINE_CLASS_VIDEO = 2,\n\tI915_ENGINE_CLASS_VIDEO_ENHANCE = 3,\n\tI915_ENGINE_CLASS_COMPUTE = 4,\n\tI915_ENGINE_CLASS_INVALID = -1,\n};\n\nenum drm_i915_gem_memory_class {\n\tI915_MEMORY_CLASS_SYSTEM = 0,\n\tI915_MEMORY_CLASS_DEVICE = 1,\n};\n\nenum drm_i915_oa_format {\n\tI915_OA_FORMAT_A13 = 1,\n\tI915_OA_FORMAT_A29 = 2,\n\tI915_OA_FORMAT_A13_B8_C8 = 3,\n\tI915_OA_FORMAT_B4_C8 = 4,\n\tI915_OA_FORMAT_A45_B8_C8 = 5,\n\tI915_OA_FORMAT_B4_C8_A16 = 6,\n\tI915_OA_FORMAT_C4_B8 = 7,\n\tI915_OA_FORMAT_A12 = 8,\n\tI915_OA_FORMAT_A12_B8_C8 = 9,\n\tI915_OA_FORMAT_A32u40_A4u32_B8_C8 = 10,\n\tI915_OAR_FORMAT_A32u40_A4u32_B8_C8 = 11,\n\tI915_OA_FORMAT_A24u40_A14u32_B8_C8 = 12,\n\tI915_OAM_FORMAT_MPEC8u64_B8_C8 = 13,\n\tI915_OAM_FORMAT_MPEC8u32_B8_C8 = 14,\n\tI915_OA_FORMAT_MAX = 15,\n};\n\nenum drm_i915_perf_property_id {\n\tDRM_I915_PERF_PROP_CTX_HANDLE = 1,\n\tDRM_I915_PERF_PROP_SAMPLE_OA = 2,\n\tDRM_I915_PERF_PROP_OA_METRICS_SET = 3,\n\tDRM_I915_PERF_PROP_OA_FORMAT = 4,\n\tDRM_I915_PERF_PROP_OA_EXPONENT = 5,\n\tDRM_I915_PERF_PROP_HOLD_PREEMPTION = 6,\n\tDRM_I915_PERF_PROP_GLOBAL_SSEU = 7,\n\tDRM_I915_PERF_PROP_POLL_OA_PERIOD = 8,\n\tDRM_I915_PERF_PROP_OA_ENGINE_CLASS = 9,\n\tDRM_I915_PERF_PROP_OA_ENGINE_INSTANCE = 10,\n\tDRM_I915_PERF_PROP_MAX = 11,\n};\n\nenum drm_i915_perf_record_type {\n\tDRM_I915_PERF_RECORD_SAMPLE = 1,\n\tDRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,\n\tDRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,\n\tDRM_I915_PERF_RECORD_MAX = 4,\n};\n\nenum drm_i915_pmu_engine_sample {\n\tI915_SAMPLE_BUSY = 0,\n\tI915_SAMPLE_WAIT = 1,\n\tI915_SAMPLE_SEMA = 2,\n};\n\nenum drm_ioctl_flags {\n\tDRM_AUTH = 1,\n\tDRM_MASTER = 2,\n\tDRM_ROOT_ONLY = 4,\n\tDRM_RENDER_ALLOW = 32,\n};\n\nenum drm_link_status {\n\tDRM_LINK_STATUS_GOOD = 0,\n\tDRM_LINK_STATUS_BAD = 1,\n};\n\nenum drm_lspcon_mode {\n\tDRM_LSPCON_MODE_INVALID = 0,\n\tDRM_LSPCON_MODE_LS = 1,\n\tDRM_LSPCON_MODE_PCON = 2,\n};\n\nenum drm_minor_type {\n\tDRM_MINOR_PRIMARY = 0,\n\tDRM_MINOR_CONTROL = 1,\n\tDRM_MINOR_RENDER = 2,\n\tDRM_MINOR_ACCEL = 32,\n};\n\nenum drm_mm_insert_mode {\n\tDRM_MM_INSERT_BEST = 0,\n\tDRM_MM_INSERT_LOW = 1,\n\tDRM_MM_INSERT_HIGH = 2,\n\tDRM_MM_INSERT_EVICT = 3,\n\tDRM_MM_INSERT_ONCE = 2147483648,\n\tDRM_MM_INSERT_HIGHEST = 2147483650,\n\tDRM_MM_INSERT_LOWEST = 2147483649,\n};\n\nenum drm_mode_analog {\n\tDRM_MODE_ANALOG_NTSC = 0,\n\tDRM_MODE_ANALOG_PAL = 1,\n};\n\nenum drm_mode_status {\n\tMODE_OK = 0,\n\tMODE_HSYNC = 1,\n\tMODE_VSYNC = 2,\n\tMODE_H_ILLEGAL = 3,\n\tMODE_V_ILLEGAL = 4,\n\tMODE_BAD_WIDTH = 5,\n\tMODE_NOMODE = 6,\n\tMODE_NO_INTERLACE = 7,\n\tMODE_NO_DBLESCAN = 8,\n\tMODE_NO_VSCAN = 9,\n\tMODE_MEM = 10,\n\tMODE_VIRTUAL_X = 11,\n\tMODE_VIRTUAL_Y = 12,\n\tMODE_MEM_VIRT = 13,\n\tMODE_NOCLOCK = 14,\n\tMODE_CLOCK_HIGH = 15,\n\tMODE_CLOCK_LOW = 16,\n\tMODE_CLOCK_RANGE = 17,\n\tMODE_BAD_HVALUE = 18,\n\tMODE_BAD_VVALUE = 19,\n\tMODE_BAD_VSCAN = 20,\n\tMODE_HSYNC_NARROW = 21,\n\tMODE_HSYNC_WIDE = 22,\n\tMODE_HBLANK_NARROW = 23,\n\tMODE_HBLANK_WIDE = 24,\n\tMODE_VSYNC_NARROW = 25,\n\tMODE_VSYNC_WIDE = 26,\n\tMODE_VBLANK_NARROW = 27,\n\tMODE_VBLANK_WIDE = 28,\n\tMODE_PANEL = 29,\n\tMODE_INTERLACE_WIDTH = 30,\n\tMODE_ONE_WIDTH = 31,\n\tMODE_ONE_HEIGHT = 32,\n\tMODE_ONE_SIZE = 33,\n\tMODE_NO_REDUCED = 34,\n\tMODE_NO_STEREO = 35,\n\tMODE_NO_420 = 36,\n\tMODE_STALE = -3,\n\tMODE_BAD = -2,\n\tMODE_ERROR = -1,\n};\n\nenum drm_mode_subconnector {\n\tDRM_MODE_SUBCONNECTOR_Automatic = 0,\n\tDRM_MODE_SUBCONNECTOR_Unknown = 0,\n\tDRM_MODE_SUBCONNECTOR_VGA = 1,\n\tDRM_MODE_SUBCONNECTOR_DVID = 3,\n\tDRM_MODE_SUBCONNECTOR_DVIA = 4,\n\tDRM_MODE_SUBCONNECTOR_Composite = 5,\n\tDRM_MODE_SUBCONNECTOR_SVIDEO = 6,\n\tDRM_MODE_SUBCONNECTOR_Component = 8,\n\tDRM_MODE_SUBCONNECTOR_SCART = 9,\n\tDRM_MODE_SUBCONNECTOR_DisplayPort = 10,\n\tDRM_MODE_SUBCONNECTOR_HDMIA = 11,\n\tDRM_MODE_SUBCONNECTOR_Native = 15,\n\tDRM_MODE_SUBCONNECTOR_Wireless = 18,\n};\n\nenum drm_panel_orientation {\n\tDRM_MODE_PANEL_ORIENTATION_UNKNOWN = -1,\n\tDRM_MODE_PANEL_ORIENTATION_NORMAL = 0,\n\tDRM_MODE_PANEL_ORIENTATION_BOTTOM_UP = 1,\n\tDRM_MODE_PANEL_ORIENTATION_LEFT_UP = 2,\n\tDRM_MODE_PANEL_ORIENTATION_RIGHT_UP = 3,\n};\n\nenum drm_plane_type {\n\tDRM_PLANE_TYPE_OVERLAY = 0,\n\tDRM_PLANE_TYPE_PRIMARY = 1,\n\tDRM_PLANE_TYPE_CURSOR = 2,\n};\n\nenum drm_privacy_screen_status {\n\tPRIVACY_SCREEN_DISABLED = 0,\n\tPRIVACY_SCREEN_ENABLED = 1,\n\tPRIVACY_SCREEN_DISABLED_LOCKED = 2,\n\tPRIVACY_SCREEN_ENABLED_LOCKED = 3,\n};\n\nenum drm_scaling_filter {\n\tDRM_SCALING_FILTER_DEFAULT = 0,\n\tDRM_SCALING_FILTER_NEAREST_NEIGHBOR = 1,\n};\n\nenum drm_stat_type {\n\t_DRM_STAT_LOCK = 0,\n\t_DRM_STAT_OPENS = 1,\n\t_DRM_STAT_CLOSES = 2,\n\t_DRM_STAT_IOCTLS = 3,\n\t_DRM_STAT_LOCKS = 4,\n\t_DRM_STAT_UNLOCKS = 5,\n\t_DRM_STAT_VALUE = 6,\n\t_DRM_STAT_BYTE = 7,\n\t_DRM_STAT_COUNT = 8,\n\t_DRM_STAT_IRQ = 9,\n\t_DRM_STAT_PRIMARY = 10,\n\t_DRM_STAT_SECONDARY = 11,\n\t_DRM_STAT_DMA = 12,\n\t_DRM_STAT_SPECIAL = 13,\n\t_DRM_STAT_MISSED = 14,\n};\n\nenum drm_vblank_seq_type {\n\t_DRM_VBLANK_ABSOLUTE = 0,\n\t_DRM_VBLANK_RELATIVE = 1,\n\t_DRM_VBLANK_HIGH_CRTC_MASK = 62,\n\t_DRM_VBLANK_EVENT = 67108864,\n\t_DRM_VBLANK_FLIP = 134217728,\n\t_DRM_VBLANK_NEXTONMISS = 268435456,\n\t_DRM_VBLANK_SECONDARY = 536870912,\n\t_DRM_VBLANK_SIGNAL = 1073741824,\n};\n\nenum drrs_refresh_rate {\n\tDRRS_REFRESH_RATE_HIGH = 0,\n\tDRRS_REFRESH_RATE_LOW = 1,\n};\n\nenum drrs_type {\n\tDRRS_TYPE_NONE = 0,\n\tDRRS_TYPE_STATIC = 1,\n\tDRRS_TYPE_SEAMLESS = 2,\n};\n\nenum dw_dma_fc {\n\tDW_DMA_FC_D_M2M = 0,\n\tDW_DMA_FC_D_M2P = 1,\n\tDW_DMA_FC_D_P2M = 2,\n\tDW_DMA_FC_D_P2P = 3,\n\tDW_DMA_FC_P_P2M = 4,\n\tDW_DMA_FC_SP_P2P = 5,\n\tDW_DMA_FC_P_M2P = 6,\n\tDW_DMA_FC_DP_P2P = 7,\n};\n\nenum dw_dmac_flags {\n\tDW_DMA_IS_CYCLIC = 0,\n\tDW_DMA_IS_SOFT_LLP = 1,\n\tDW_DMA_IS_PAUSED = 2,\n\tDW_DMA_IS_INITIALIZED = 3,\n};\n\nenum dyn_constr_type {\n\tDYN_CONSTR_NONE = 0,\n\tDYN_CONSTR_BR_CNTR = 1,\n\tDYN_CONSTR_ACR_CNTR = 2,\n\tDYN_CONSTR_ACR_CAUSE = 3,\n\tDYN_CONSTR_PEBS = 4,\n\tDYN_CONSTR_PDIST = 5,\n\tDYN_CONSTR_MAX = 6,\n};\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nenum e820_type {\n\tE820_TYPE_RAM = 1,\n\tE820_TYPE_RESERVED = 2,\n\tE820_TYPE_ACPI = 3,\n\tE820_TYPE_NVS = 4,\n\tE820_TYPE_UNUSABLE = 5,\n\tE820_TYPE_PMEM = 7,\n\tE820_TYPE_PRAM = 12,\n\tE820_TYPE_SOFT_RESERVED = 4026531839,\n};\n\nenum ec_command {\n\tACPI_EC_COMMAND_READ = 128,\n\tACPI_EC_COMMAND_WRITE = 129,\n\tACPI_EC_BURST_ENABLE = 130,\n\tACPI_EC_BURST_DISABLE = 131,\n\tACPI_EC_COMMAND_QUERY = 132,\n};\n\nenum edid_block_status {\n\tEDID_BLOCK_OK = 0,\n\tEDID_BLOCK_READ_FAIL = 1,\n\tEDID_BLOCK_NULL = 2,\n\tEDID_BLOCK_ZERO = 3,\n\tEDID_BLOCK_HEADER_CORRUPT = 4,\n\tEDID_BLOCK_HEADER_REPAIR = 5,\n\tEDID_BLOCK_HEADER_FIXED = 6,\n\tEDID_BLOCK_CHECKSUM = 7,\n\tEDID_BLOCK_VERSION = 8,\n};\n\nenum efi_rts_ids {\n\tEFI_NONE = 0,\n\tEFI_GET_TIME = 1,\n\tEFI_SET_TIME = 2,\n\tEFI_GET_WAKEUP_TIME = 3,\n\tEFI_SET_WAKEUP_TIME = 4,\n\tEFI_GET_VARIABLE = 5,\n\tEFI_GET_NEXT_VARIABLE = 6,\n\tEFI_SET_VARIABLE = 7,\n\tEFI_QUERY_VARIABLE_INFO = 8,\n\tEFI_GET_NEXT_HIGH_MONO_COUNT = 9,\n\tEFI_RESET_SYSTEM = 10,\n\tEFI_UPDATE_CAPSULE = 11,\n\tEFI_QUERY_CAPSULE_CAPS = 12,\n\tEFI_ACPI_PRM_HANDLER = 13,\n};\n\nenum efi_secureboot_mode {\n\tefi_secureboot_mode_unset = 0,\n\tefi_secureboot_mode_unknown = 1,\n\tefi_secureboot_mode_disabled = 2,\n\tefi_secureboot_mode_enabled = 3,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum energy_perf_value_index {\n\tEPB_INDEX_PERFORMANCE = 0,\n\tEPB_INDEX_BALANCE_PERFORMANCE = 1,\n\tEPB_INDEX_NORMAL = 2,\n\tEPB_INDEX_BALANCE_POWERSAVE = 3,\n\tEPB_INDEX_POWERSAVE = 4,\n};\n\nenum energy_perf_value_index___2 {\n\tEPP_INDEX_DEFAULT = 0,\n\tEPP_INDEX_PERFORMANCE = 1,\n\tEPP_INDEX_BALANCE_PERFORMANCE = 2,\n\tEPP_INDEX_BALANCE_POWERSAVE = 3,\n\tEPP_INDEX_POWERSAVE = 4,\n};\n\nenum energy_perf_value_index___3 {\n\tEPP_INDEX_DEFAULT___2 = 0,\n\tEPP_INDEX_PERFORMANCE___2 = 1,\n\tEPP_INDEX_BALANCE_PERFORMANCE___2 = 2,\n\tEPP_INDEX_BALANCE_POWERSAVE___2 = 3,\n\tEPP_INDEX_POWERSAVE___2 = 4,\n\tEPP_INDEX_MAX = 5,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n\tETT_EVENT_EPROBE = 64,\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_FROZEN = 8,\n\tEVENT_CPU = 16,\n\tEVENT_CGROUP = 32,\n\tEVENT_GUEST = 64,\n\tEVENT_FLAGS = 96,\n\tEVENT_ALL = 3,\n\tEVENT_TIME_FROZEN = 12,\n};\n\nenum evmcs_ctrl_type {\n\tEVMCS_EXIT_CTRLS = 0,\n\tEVMCS_ENTRY_CTRLS = 1,\n\tEVMCS_EXEC_CTRL = 2,\n\tEVMCS_2NDEXEC = 3,\n\tEVMCS_3RDEXEC = 4,\n\tEVMCS_PINCTRL = 5,\n\tEVMCS_VMFUNC = 6,\n\tNR_EVMCS_CTRLS = 7,\n};\n\nenum evmcs_revision {\n\tEVMCSv1_LEGACY = 0,\n\tNR_EVMCS_REVISIONS = 1,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum exception {\n\tEXCP_CONTEXT = 1,\n\tNO_EXCP = 2,\n};\n\nenum exception_stack_ordering {\n\tESTACK_DF = 0,\n\tESTACK_NMI = 1,\n\tESTACK_DB = 2,\n\tESTACK_MCE = 3,\n\tESTACK_VC = 4,\n\tESTACK_VC2 = 5,\n\tN_EXCEPTION_STACKS = 6,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum exit_fastpath_completion {\n\tEXIT_FASTPATH_NONE = 0,\n\tEXIT_FASTPATH_REENTER_GUEST = 1,\n\tEXIT_FASTPATH_EXIT_HANDLED = 2,\n\tEXIT_FASTPATH_EXIT_USERSPACE = 3,\n};\n\ntypedef enum exit_fastpath_completion fastpath_t;\n\nenum extra_reg_type {\n\tEXTRA_REG_NONE = -1,\n\tEXTRA_REG_RSP_0 = 0,\n\tEXTRA_REG_RSP_1 = 1,\n\tEXTRA_REG_LBR = 2,\n\tEXTRA_REG_LDLAT = 3,\n\tEXTRA_REG_FE = 4,\n\tEXTRA_REG_SNOOP_0 = 5,\n\tEXTRA_REG_SNOOP_1 = 6,\n\tEXTRA_REG_OMR_0 = 7,\n\tEXTRA_REG_OMR_1 = 8,\n\tEXTRA_REG_OMR_2 = 9,\n\tEXTRA_REG_OMR_3 = 10,\n\tEXTRA_REG_MAX = 11,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum faulttype {\n\tDMA_REMAP = 0,\n\tINTR_REMAP = 1,\n\tUNKNOWN = 2,\n};\n\nenum fb_op_origin {\n\tORIGIN_CPU = 0,\n\tORIGIN_CS = 1,\n\tORIGIN_FLIP = 2,\n\tORIGIN_DIRTYFB = 3,\n\tORIGIN_CURSOR_UPDATE = 4,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_EDATA = 10,\n\tFETCH_OP_DEREF = 11,\n\tFETCH_OP_UDEREF = 12,\n\tFETCH_OP_ST_RAW = 13,\n\tFETCH_OP_ST_MEM = 14,\n\tFETCH_OP_ST_UMEM = 15,\n\tFETCH_OP_ST_STRING = 16,\n\tFETCH_OP_ST_USTRING = 17,\n\tFETCH_OP_ST_SYMSTR = 18,\n\tFETCH_OP_ST_EDATA = 19,\n\tFETCH_OP_MOD_BF = 20,\n\tFETCH_OP_LP_ARRAY = 21,\n\tFETCH_OP_TP_ARG = 22,\n\tFETCH_OP_END = 23,\n\tFETCH_NOP_SYMBOL = 24,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum file_state {\n\tMEI_FILE_UNINITIALIZED = 0,\n\tMEI_FILE_INITIALIZING = 1,\n\tMEI_FILE_CONNECTING = 2,\n\tMEI_FILE_CONNECTED = 3,\n\tMEI_FILE_DISCONNECTING = 4,\n\tMEI_FILE_DISCONNECT_REPLY = 5,\n\tMEI_FILE_DISCONNECT_REQUIRED = 6,\n\tMEI_FILE_DISCONNECTED = 7,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum filter_pred_fn {\n\tFILTER_PRED_FN_NOP = 0,\n\tFILTER_PRED_FN_64 = 1,\n\tFILTER_PRED_FN_64_CPUMASK = 2,\n\tFILTER_PRED_FN_S64 = 3,\n\tFILTER_PRED_FN_U64 = 4,\n\tFILTER_PRED_FN_32 = 5,\n\tFILTER_PRED_FN_32_CPUMASK = 6,\n\tFILTER_PRED_FN_S32 = 7,\n\tFILTER_PRED_FN_U32 = 8,\n\tFILTER_PRED_FN_16 = 9,\n\tFILTER_PRED_FN_16_CPUMASK = 10,\n\tFILTER_PRED_FN_S16 = 11,\n\tFILTER_PRED_FN_U16 = 12,\n\tFILTER_PRED_FN_8 = 13,\n\tFILTER_PRED_FN_8_CPUMASK = 14,\n\tFILTER_PRED_FN_S8 = 15,\n\tFILTER_PRED_FN_U8 = 16,\n\tFILTER_PRED_FN_COMM = 17,\n\tFILTER_PRED_FN_STRING = 18,\n\tFILTER_PRED_FN_STRLOC = 19,\n\tFILTER_PRED_FN_STRRELLOC = 20,\n\tFILTER_PRED_FN_PCHAR_USER = 21,\n\tFILTER_PRED_FN_PCHAR = 22,\n\tFILTER_PRED_FN_CPU = 23,\n\tFILTER_PRED_FN_CPU_CPUMASK = 24,\n\tFILTER_PRED_FN_CPUMASK = 25,\n\tFILTER_PRED_FN_CPUMASK_CPU = 26,\n\tFILTER_PRED_FN_FUNCTION = 27,\n\tFILTER_PRED_FN_ = 28,\n\tFILTER_PRED_TEST_VISITED = 29,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum fixed_addresses {\n\tVSYSCALL_PAGE = 511,\n\tFIX_DBGP_BASE = 512,\n\tFIX_EARLYCON_MEM_BASE = 513,\n\tFIX_OHCI1394_BASE = 514,\n\tFIX_APIC_BASE = 515,\n\tFIX_IO_APIC_BASE_0 = 516,\n\tFIX_IO_APIC_BASE_END = 643,\n\t__end_of_permanent_fixed_addresses = 644,\n\tFIX_BTMAP_END = 1024,\n\tFIX_BTMAP_BEGIN = 1535,\n\t__end_of_fixed_addresses = 1536,\n};\n\nenum flag_bits {\n\tFaulty = 0,\n\tIn_sync = 1,\n\tBitmap_sync = 2,\n\tWriteMostly = 3,\n\tAutoDetected = 4,\n\tBlocked = 5,\n\tWriteErrorSeen = 6,\n\tFaultRecorded = 7,\n\tBlockedBadBlocks = 8,\n\tWantReplacement = 9,\n\tReplacement = 10,\n\tCandidate = 11,\n\tJournal = 12,\n\tClusterRemove = 13,\n\tExternalBbl = 14,\n\tFailFast = 15,\n\tLastDev = 16,\n\tCollisionCheck = 17,\n\tNonrot = 18,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum forcewake_domain_id {\n\tFW_DOMAIN_ID_RENDER = 0,\n\tFW_DOMAIN_ID_GT = 1,\n\tFW_DOMAIN_ID_MEDIA = 2,\n\tFW_DOMAIN_ID_MEDIA_VDBOX0 = 3,\n\tFW_DOMAIN_ID_MEDIA_VDBOX1 = 4,\n\tFW_DOMAIN_ID_MEDIA_VDBOX2 = 5,\n\tFW_DOMAIN_ID_MEDIA_VDBOX3 = 6,\n\tFW_DOMAIN_ID_MEDIA_VDBOX4 = 7,\n\tFW_DOMAIN_ID_MEDIA_VDBOX5 = 8,\n\tFW_DOMAIN_ID_MEDIA_VDBOX6 = 9,\n\tFW_DOMAIN_ID_MEDIA_VDBOX7 = 10,\n\tFW_DOMAIN_ID_MEDIA_VEBOX0 = 11,\n\tFW_DOMAIN_ID_MEDIA_VEBOX1 = 12,\n\tFW_DOMAIN_ID_MEDIA_VEBOX2 = 13,\n\tFW_DOMAIN_ID_MEDIA_VEBOX3 = 14,\n\tFW_DOMAIN_ID_GSC = 15,\n\tFW_DOMAIN_ID_COUNT = 16,\n};\n\nenum forcewake_domains {\n\tFORCEWAKE_RENDER = 1,\n\tFORCEWAKE_GT = 2,\n\tFORCEWAKE_MEDIA = 4,\n\tFORCEWAKE_MEDIA_VDBOX0 = 8,\n\tFORCEWAKE_MEDIA_VDBOX1 = 16,\n\tFORCEWAKE_MEDIA_VDBOX2 = 32,\n\tFORCEWAKE_MEDIA_VDBOX3 = 64,\n\tFORCEWAKE_MEDIA_VDBOX4 = 128,\n\tFORCEWAKE_MEDIA_VDBOX5 = 256,\n\tFORCEWAKE_MEDIA_VDBOX6 = 512,\n\tFORCEWAKE_MEDIA_VDBOX7 = 1024,\n\tFORCEWAKE_MEDIA_VEBOX0 = 2048,\n\tFORCEWAKE_MEDIA_VEBOX1 = 4096,\n\tFORCEWAKE_MEDIA_VEBOX2 = 8192,\n\tFORCEWAKE_MEDIA_VEBOX3 = 16384,\n\tFORCEWAKE_GSC = 32768,\n\tFORCEWAKE_ALL = 65535,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fscache_cache_state {\n\tFSCACHE_CACHE_IS_NOT_PRESENT = 0,\n\tFSCACHE_CACHE_IS_PREPARING = 1,\n\tFSCACHE_CACHE_IS_ACTIVE = 2,\n\tFSCACHE_CACHE_GOT_IOERROR = 3,\n\tFSCACHE_CACHE_IS_WITHDRAWN = 4,\n};\n\nenum fscache_cookie_state {\n\tFSCACHE_COOKIE_STATE_QUIESCENT = 0,\n\tFSCACHE_COOKIE_STATE_LOOKING_UP = 1,\n\tFSCACHE_COOKIE_STATE_CREATING = 2,\n\tFSCACHE_COOKIE_STATE_ACTIVE = 3,\n\tFSCACHE_COOKIE_STATE_INVALIDATING = 4,\n\tFSCACHE_COOKIE_STATE_FAILED = 5,\n\tFSCACHE_COOKIE_STATE_LRU_DISCARDING = 6,\n\tFSCACHE_COOKIE_STATE_WITHDRAWING = 7,\n\tFSCACHE_COOKIE_STATE_RELINQUISHING = 8,\n\tFSCACHE_COOKIE_STATE_DROPPED = 9,\n} __attribute__((mode(byte)));\n\nenum fscache_want_state {\n\tFSCACHE_WANT_PARAMS = 0,\n\tFSCACHE_WANT_WRITE = 1,\n\tFSCACHE_WANT_READ = 2,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftrace_bug_type {\n\tFTRACE_BUG_UNKNOWN = 0,\n\tFTRACE_BUG_INIT = 1,\n\tFTRACE_BUG_NOP = 2,\n\tFTRACE_BUG_CALL = 3,\n\tFTRACE_BUG_UPDATE = 4,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum ftrace_ops_cmd {\n\tFTRACE_OPS_CMD_ENABLE_SHARE_IPMODIFY_SELF = 0,\n\tFTRACE_OPS_CMD_ENABLE_SHARE_IPMODIFY_PEER = 1,\n\tFTRACE_OPS_CMD_DISABLE_SHARE_IPMODIFY_PEER = 2,\n};\n\nenum fuse_dax_mode {\n\tFUSE_DAX_INODE_DEFAULT = 0,\n\tFUSE_DAX_ALWAYS = 1,\n\tFUSE_DAX_NEVER = 2,\n\tFUSE_DAX_INODE_USER = 3,\n};\n\nenum fuse_ext_type {\n\tFUSE_MAX_NR_SECCTX = 31,\n\tFUSE_EXT_GROUPS = 32,\n};\n\nenum fuse_notify_code {\n\tFUSE_NOTIFY_POLL = 1,\n\tFUSE_NOTIFY_INVAL_INODE = 2,\n\tFUSE_NOTIFY_INVAL_ENTRY = 3,\n\tFUSE_NOTIFY_STORE = 4,\n\tFUSE_NOTIFY_RETRIEVE = 5,\n\tFUSE_NOTIFY_DELETE = 6,\n\tFUSE_NOTIFY_RESEND = 7,\n\tFUSE_NOTIFY_INC_EPOCH = 8,\n\tFUSE_NOTIFY_PRUNE = 9,\n};\n\nenum fuse_opcode {\n\tFUSE_LOOKUP = 1,\n\tFUSE_FORGET = 2,\n\tFUSE_GETATTR = 3,\n\tFUSE_SETATTR = 4,\n\tFUSE_READLINK = 5,\n\tFUSE_SYMLINK = 6,\n\tFUSE_MKNOD = 8,\n\tFUSE_MKDIR = 9,\n\tFUSE_UNLINK = 10,\n\tFUSE_RMDIR = 11,\n\tFUSE_RENAME = 12,\n\tFUSE_LINK = 13,\n\tFUSE_OPEN = 14,\n\tFUSE_READ = 15,\n\tFUSE_WRITE = 16,\n\tFUSE_STATFS = 17,\n\tFUSE_RELEASE = 18,\n\tFUSE_FSYNC = 20,\n\tFUSE_SETXATTR = 21,\n\tFUSE_GETXATTR = 22,\n\tFUSE_LISTXATTR = 23,\n\tFUSE_REMOVEXATTR = 24,\n\tFUSE_FLUSH = 25,\n\tFUSE_INIT = 26,\n\tFUSE_OPENDIR = 27,\n\tFUSE_READDIR = 28,\n\tFUSE_RELEASEDIR = 29,\n\tFUSE_FSYNCDIR = 30,\n\tFUSE_GETLK = 31,\n\tFUSE_SETLK = 32,\n\tFUSE_SETLKW = 33,\n\tFUSE_ACCESS = 34,\n\tFUSE_CREATE = 35,\n\tFUSE_INTERRUPT = 36,\n\tFUSE_BMAP = 37,\n\tFUSE_DESTROY = 38,\n\tFUSE_IOCTL = 39,\n\tFUSE_POLL = 40,\n\tFUSE_NOTIFY_REPLY = 41,\n\tFUSE_BATCH_FORGET = 42,\n\tFUSE_FALLOCATE = 43,\n\tFUSE_READDIRPLUS = 44,\n\tFUSE_RENAME2 = 45,\n\tFUSE_LSEEK = 46,\n\tFUSE_COPY_FILE_RANGE = 47,\n\tFUSE_SETUPMAPPING = 48,\n\tFUSE_REMOVEMAPPING = 49,\n\tFUSE_SYNCFS = 50,\n\tFUSE_TMPFILE = 51,\n\tFUSE_STATX = 52,\n\tFUSE_COPY_FILE_RANGE_64 = 53,\n\tCUSE_INIT = 4096,\n\tCUSE_INIT_BSWAP_RESERVED = 1048576,\n\tFUSE_INIT_BSWAP_RESERVED = 436207616,\n};\n\nenum fuse_parse_result {\n\tFOUND_ERR = -1,\n\tFOUND_NONE = 0,\n\tFOUND_SOME = 1,\n\tFOUND_ALL = 2,\n};\n\nenum fuse_req_flag {\n\tFR_ISREPLY = 0,\n\tFR_FORCE = 1,\n\tFR_BACKGROUND = 2,\n\tFR_WAITING = 3,\n\tFR_ABORTED = 4,\n\tFR_INTERRUPTED = 5,\n\tFR_LOCKED = 6,\n\tFR_PENDING = 7,\n\tFR_SENT = 8,\n\tFR_FINISHED = 9,\n\tFR_PRIVATE = 10,\n\tFR_ASYNC = 11,\n\tFR_URING = 12,\n};\n\nenum fuse_ring_req_state {\n\tFRRS_INVALID = 0,\n\tFRRS_COMMIT = 1,\n\tFRRS_AVAILABLE = 2,\n\tFRRS_FUSE_REQ = 3,\n\tFRRS_USERSPACE = 4,\n\tFRRS_TEARDOWN = 5,\n\tFRRS_RELEASED = 6,\n};\n\nenum fuse_uring_cmd {\n\tFUSE_IO_URING_CMD_INVALID = 0,\n\tFUSE_IO_URING_CMD_REGISTER = 1,\n\tFUSE_IO_URING_CMD_COMMIT_AND_FETCH = 2,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum fw_hdcp_status {\n\tFW_HDCP_STATUS_SUCCESS = 0,\n\tFW_HDCP_STATUS_INTERNAL_ERROR = 4096,\n\tFW_HDCP_STATUS_UNKNOWN_ERROR = 4097,\n\tFW_HDCP_STATUS_INCORRECT_API_VERSION = 4098,\n\tFW_HDCP_STATUS_INVALID_FUNCTION = 4099,\n\tFW_HDCP_STATUS_INVALID_BUFFER_LENGTH = 4100,\n\tFW_HDCP_STATUS_INVALID_PARAMS = 4101,\n\tFW_HDCP_STATUS_AUTHENTICATION_FAILED = 4102,\n\tFW_HDCP_INVALID_SESSION_STATE = 24576,\n\tFW_HDCP_SRM_FRAGMENT_UNEXPECTED = 24577,\n\tFW_HDCP_SRM_INVALID_LENGTH = 24578,\n\tFW_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 24579,\n\tFW_HDCP_SRM_VERIFICATION_FAILED = 24580,\n\tFW_HDCP_SRM_VERSION_TOO_OLD = 24581,\n\tFW_HDCP_RX_CERT_VERIFICATION_FAILED = 24582,\n\tFW_HDCP_RX_REVOKED = 24583,\n\tFW_HDCP_H_VERIFICATION_FAILED = 24584,\n\tFW_HDCP_REPEATER_CHECK_UNEXPECTED = 24585,\n\tFW_HDCP_TOPOLOGY_MAX_EXCEEDED = 24586,\n\tFW_HDCP_V_VERIFICATION_FAILED = 24587,\n\tFW_HDCP_L_VERIFICATION_FAILED = 24588,\n\tFW_HDCP_STREAM_KEY_ALLOC_FAILED = 24589,\n\tFW_HDCP_BASE_KEY_RESET_FAILED = 24590,\n\tFW_HDCP_NONCE_GENERATION_FAILED = 24591,\n\tFW_HDCP_STATUS_INVALID_E_KEY_STATE = 24592,\n\tFW_HDCP_STATUS_INVALID_CS_ICV = 24593,\n\tFW_HDCP_STATUS_INVALID_KB_KEY_STATE = 24594,\n\tFW_HDCP_STATUS_INVALID_PAVP_MODE_ICV = 24595,\n\tFW_HDCP_STATUS_INVALID_PAVP_MODE = 24596,\n\tFW_HDCP_STATUS_LC_MAX_ATTEMPTS = 24597,\n\tFW_HDCP_STATUS_MISMATCH_IN_M = 24598,\n\tFW_HDCP_STATUS_RX_PROV_NOT_ALLOWED = 24599,\n\tFW_HDCP_STATUS_RX_PROV_WRONG_SUBJECT = 24600,\n\tFW_HDCP_RX_NEEDS_PROVISIONING = 24601,\n\tFW_HDCP_BKSV_ICV_AUTH_FAILED = 24608,\n\tFW_HDCP_STATUS_INVALID_STREAM_ID = 24609,\n\tFW_HDCP_STATUS_CHAIN_NOT_INITIALIZED = 24610,\n\tFW_HDCP_FAIL_NOT_EXPECTED = 24611,\n\tFW_HDCP_FAIL_HDCP_OFF = 24612,\n\tFW_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE = 24613,\n\tFW_HDCP_FAIL_AES_ECB_FAILURE = 24614,\n\tFW_HDCP_FEATURE_NOT_SUPPORTED = 24615,\n\tFW_HDCP_DMA_READ_ERROR = 24616,\n\tFW_HDCP_DMA_WRITE_ERROR = 24617,\n\tFW_HDCP_FAIL_INVALID_PACKET_SIZE = 24624,\n\tFW_HDCP_H264_PARSING_ERROR = 24625,\n\tFW_HDCP_HDCP2_ERRATA_VIDEO_VIOLATION = 24626,\n\tFW_HDCP_HDCP2_ERRATA_AUDIO_VIOLATION = 24627,\n\tFW_HDCP_TX_ACTIVE_ERROR = 24628,\n\tFW_HDCP_MODE_CHANGE_ERROR = 24629,\n\tFW_HDCP_STREAM_TYPE_ERROR = 24630,\n\tFW_HDCP_STREAM_MANAGE_NOT_POSSIBLE = 24631,\n\tFW_HDCP_STATUS_PORT_INVALID_COMMAND = 24632,\n\tFW_HDCP_STATUS_UNSUPPORTED_PROTOCOL = 24633,\n\tFW_HDCP_STATUS_INVALID_PORT_INDEX = 24634,\n\tFW_HDCP_STATUS_TX_AUTH_NEEDED = 24635,\n\tFW_HDCP_STATUS_NOT_INTEGRATED_PORT = 24636,\n\tFW_HDCP_STATUS_SESSION_MAX_REACHED = 24637,\n\tFW_HDCP_STATUS_NOT_HDCP_CAPABLE = 24641,\n\tFW_HDCP_STATUS_INVALID_STREAM_COUNT = 24642,\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n\tFW_OPT_PARTIAL = 128,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nenum g4x_wm_level {\n\tG4X_WM_LEVEL_NORMAL = 0,\n\tG4X_WM_LEVEL_SR = 1,\n\tG4X_WM_LEVEL_HPLL = 2,\n\tNUM_G4X_WM_LEVELS = 3,\n};\n\nenum gds_mitigations {\n\tGDS_MITIGATION_OFF = 0,\n\tGDS_MITIGATION_AUTO = 1,\n\tGDS_MITIGATION_UCODE_NEEDED = 2,\n\tGDS_MITIGATION_FORCE = 3,\n\tGDS_MITIGATION_FULL = 4,\n\tGDS_MITIGATION_FULL_LOCKED = 5,\n\tGDS_MITIGATION_HYPERVISOR = 6,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum gmbus_gpio {\n\tGPIOA = 0,\n\tGPIOB = 1,\n\tGPIOC = 2,\n\tGPIOD = 3,\n\tGPIOE = 4,\n\tGPIOF = 5,\n\tGPIOG = 6,\n\tGPIOH = 7,\n\t__GPIOI_UNUSED = 8,\n\tGPIOJ = 9,\n\tGPIOK = 10,\n\tGPIOL = 11,\n\tGPIOM = 12,\n\tGPION = 13,\n\tGPIOO = 14,\n};\n\nenum gpio_lookup_flags {\n\tGPIO_ACTIVE_HIGH = 0,\n\tGPIO_ACTIVE_LOW = 1,\n\tGPIO_OPEN_DRAIN = 2,\n\tGPIO_OPEN_SOURCE = 4,\n\tGPIO_PERSISTENT = 0,\n\tGPIO_TRANSITORY = 8,\n\tGPIO_PULL_UP = 16,\n\tGPIO_PULL_DOWN = 32,\n\tGPIO_PULL_DISABLE = 64,\n\tGPIO_LOOKUP_FLAGS_DEFAULT = 0,\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nenum graph_filter_type {\n\tGRAPH_FILTER_NOTRACE = 0,\n\tGRAPH_FILTER_FUNCTION = 1,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum guc_capture_group_types {\n\tGUC_STATE_CAPTURE_GROUP_TYPE_FULL = 0,\n\tGUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL = 1,\n\tGUC_STATE_CAPTURE_GROUP_TYPE_MAX = 2,\n};\n\nenum guc_capture_type {\n\tGUC_CAPTURE_LIST_TYPE_GLOBAL = 0,\n\tGUC_CAPTURE_LIST_TYPE_ENGINE_CLASS = 1,\n\tGUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE = 2,\n\tGUC_CAPTURE_LIST_TYPE_MAX = 3,\n};\n\nenum guc_log_buffer_type {\n\tGUC_DEBUG_LOG_BUFFER = 0,\n\tGUC_CRASH_DUMP_LOG_BUFFER = 1,\n\tGUC_CAPTURE_LOG_BUFFER = 2,\n\tGUC_MAX_LOG_BUFFER = 3,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hbm_host_enum_flags {\n\tMEI_HBM_ENUM_F_ALLOW_ADD = 1,\n\tMEI_HBM_ENUM_F_IMMEDIATE_ENUM = 2,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum hdcp_command_id {\n\t_WIDI_COMMAND_BASE = 196608,\n\tWIDI_INITIATE_HDCP2_SESSION = 196608,\n\tHDCP_GET_SRM_STATUS = 196609,\n\tHDCP_SEND_SRM_FRAGMENT = 196610,\n\t_WIRED_COMMAND_BASE = 200704,\n\tWIRED_INITIATE_HDCP2_SESSION = 200704,\n\tWIRED_VERIFY_RECEIVER_CERT = 200705,\n\tWIRED_AKE_SEND_HPRIME = 200706,\n\tWIRED_AKE_SEND_PAIRING_INFO = 200707,\n\tWIRED_INIT_LOCALITY_CHECK = 200708,\n\tWIRED_VALIDATE_LOCALITY = 200709,\n\tWIRED_GET_SESSION_KEY = 200710,\n\tWIRED_ENABLE_AUTH = 200711,\n\tWIRED_VERIFY_REPEATER = 200712,\n\tWIRED_REPEATER_AUTH_STREAM_REQ = 200713,\n\tWIRED_CLOSE_SESSION = 200714,\n\t_WIRED_COMMANDS_COUNT = 200715,\n};\n\nenum hdcp_ddi {\n\tHDCP_DDI_INVALID_PORT = 0,\n\tHDCP_DDI_B = 1,\n\tHDCP_DDI_C = 2,\n\tHDCP_DDI_D = 3,\n\tHDCP_DDI_E = 4,\n\tHDCP_DDI_F = 5,\n\tHDCP_DDI_A = 7,\n\tHDCP_DDI_RANGE_END = 7,\n};\n\nenum hdcp_port_type {\n\tHDCP_PORT_TYPE_INVALID = 0,\n\tHDCP_PORT_TYPE_INTEGRATED = 1,\n\tHDCP_PORT_TYPE_LSPCON = 2,\n\tHDCP_PORT_TYPE_CPDP = 3,\n};\n\nenum hdcp_transcoder {\n\tHDCP_INVALID_TRANSCODER = 0,\n\tHDCP_TRANSCODER_EDP = 1,\n\tHDCP_TRANSCODER_DSI0 = 2,\n\tHDCP_TRANSCODER_DSI1 = 3,\n\tHDCP_TRANSCODER_A = 16,\n\tHDCP_TRANSCODER_B = 17,\n\tHDCP_TRANSCODER_C = 18,\n\tHDCP_TRANSCODER_D = 19,\n};\n\nenum hdcp_wired_protocol {\n\tHDCP_PROTOCOL_INVALID = 0,\n\tHDCP_PROTOCOL_HDMI = 1,\n\tHDCP_PROTOCOL_DP = 2,\n};\n\nenum hdmi_3d_structure {\n\tHDMI_3D_STRUCTURE_INVALID = -1,\n\tHDMI_3D_STRUCTURE_FRAME_PACKING = 0,\n\tHDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1,\n\tHDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3,\n\tHDMI_3D_STRUCTURE_L_DEPTH = 4,\n\tHDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5,\n\tHDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8,\n};\n\nenum hdmi_active_aspect {\n\tHDMI_ACTIVE_ASPECT_16_9_TOP = 2,\n\tHDMI_ACTIVE_ASPECT_14_9_TOP = 3,\n\tHDMI_ACTIVE_ASPECT_16_9_CENTER = 4,\n\tHDMI_ACTIVE_ASPECT_PICTURE = 8,\n\tHDMI_ACTIVE_ASPECT_4_3 = 9,\n\tHDMI_ACTIVE_ASPECT_16_9 = 10,\n\tHDMI_ACTIVE_ASPECT_14_9 = 11,\n\tHDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15,\n};\n\nenum hdmi_audio_coding_type {\n\tHDMI_AUDIO_CODING_TYPE_STREAM = 0,\n\tHDMI_AUDIO_CODING_TYPE_PCM = 1,\n\tHDMI_AUDIO_CODING_TYPE_AC3 = 2,\n\tHDMI_AUDIO_CODING_TYPE_MPEG1 = 3,\n\tHDMI_AUDIO_CODING_TYPE_MP3 = 4,\n\tHDMI_AUDIO_CODING_TYPE_MPEG2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_DTS = 7,\n\tHDMI_AUDIO_CODING_TYPE_ATRAC = 8,\n\tHDMI_AUDIO_CODING_TYPE_DSD = 9,\n\tHDMI_AUDIO_CODING_TYPE_EAC3 = 10,\n\tHDMI_AUDIO_CODING_TYPE_DTS_HD = 11,\n\tHDMI_AUDIO_CODING_TYPE_MLP = 12,\n\tHDMI_AUDIO_CODING_TYPE_DST = 13,\n\tHDMI_AUDIO_CODING_TYPE_WMA_PRO = 14,\n\tHDMI_AUDIO_CODING_TYPE_CXT = 15,\n};\n\nenum hdmi_audio_coding_type_ext {\n\tHDMI_AUDIO_CODING_TYPE_EXT_CT = 0,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_EXT_DRA = 7,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10,\n};\n\nenum hdmi_audio_sample_frequency {\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7,\n};\n\nenum hdmi_audio_sample_size {\n\tHDMI_AUDIO_SAMPLE_SIZE_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_SIZE_16 = 1,\n\tHDMI_AUDIO_SAMPLE_SIZE_20 = 2,\n\tHDMI_AUDIO_SAMPLE_SIZE_24 = 3,\n};\n\nenum hdmi_colorimetry {\n\tHDMI_COLORIMETRY_NONE = 0,\n\tHDMI_COLORIMETRY_ITU_601 = 1,\n\tHDMI_COLORIMETRY_ITU_709 = 2,\n\tHDMI_COLORIMETRY_EXTENDED = 3,\n};\n\nenum hdmi_colorspace {\n\tHDMI_COLORSPACE_RGB = 0,\n\tHDMI_COLORSPACE_YUV422 = 1,\n\tHDMI_COLORSPACE_YUV444 = 2,\n\tHDMI_COLORSPACE_YUV420 = 3,\n\tHDMI_COLORSPACE_RESERVED4 = 4,\n\tHDMI_COLORSPACE_RESERVED5 = 5,\n\tHDMI_COLORSPACE_RESERVED6 = 6,\n\tHDMI_COLORSPACE_IDO_DEFINED = 7,\n};\n\nenum hdmi_content_type {\n\tHDMI_CONTENT_TYPE_GRAPHICS = 0,\n\tHDMI_CONTENT_TYPE_PHOTO = 1,\n\tHDMI_CONTENT_TYPE_CINEMA = 2,\n\tHDMI_CONTENT_TYPE_GAME = 3,\n};\n\nenum hdmi_eotf {\n\tHDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0,\n\tHDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1,\n\tHDMI_EOTF_SMPTE_ST2084 = 2,\n\tHDMI_EOTF_BT_2100_HLG = 3,\n};\n\nenum hdmi_extended_colorimetry {\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0,\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1,\n\tHDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2,\n\tHDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3,\n\tHDMI_EXTENDED_COLORIMETRY_OPRGB = 4,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020 = 6,\n\tHDMI_EXTENDED_COLORIMETRY_RESERVED = 7,\n};\n\nenum hdmi_force_audio {\n\tHDMI_AUDIO_OFF_DVI = -2,\n\tHDMI_AUDIO_OFF = -1,\n\tHDMI_AUDIO_AUTO = 0,\n\tHDMI_AUDIO_ON = 1,\n};\n\nenum hdmi_infoframe_type {\n\tHDMI_INFOFRAME_TYPE_VENDOR = 129,\n\tHDMI_INFOFRAME_TYPE_AVI = 130,\n\tHDMI_INFOFRAME_TYPE_SPD = 131,\n\tHDMI_INFOFRAME_TYPE_AUDIO = 132,\n\tHDMI_INFOFRAME_TYPE_DRM = 135,\n};\n\nenum hdmi_metadata_type {\n\tHDMI_STATIC_METADATA_TYPE1 = 0,\n};\n\nenum hdmi_nups {\n\tHDMI_NUPS_UNKNOWN = 0,\n\tHDMI_NUPS_HORIZONTAL = 1,\n\tHDMI_NUPS_VERTICAL = 2,\n\tHDMI_NUPS_BOTH = 3,\n};\n\nenum hdmi_packet_type {\n\tHDMI_PACKET_TYPE_NULL = 0,\n\tHDMI_PACKET_TYPE_AUDIO_CLOCK_REGEN = 1,\n\tHDMI_PACKET_TYPE_AUDIO_SAMPLE = 2,\n\tHDMI_PACKET_TYPE_GENERAL_CONTROL = 3,\n\tHDMI_PACKET_TYPE_ACP = 4,\n\tHDMI_PACKET_TYPE_ISRC1 = 5,\n\tHDMI_PACKET_TYPE_ISRC2 = 6,\n\tHDMI_PACKET_TYPE_ONE_BIT_AUDIO_SAMPLE = 7,\n\tHDMI_PACKET_TYPE_DST_AUDIO = 8,\n\tHDMI_PACKET_TYPE_HBR_AUDIO_STREAM = 9,\n\tHDMI_PACKET_TYPE_GAMUT_METADATA = 10,\n};\n\nenum hdmi_picture_aspect {\n\tHDMI_PICTURE_ASPECT_NONE = 0,\n\tHDMI_PICTURE_ASPECT_4_3 = 1,\n\tHDMI_PICTURE_ASPECT_16_9 = 2,\n\tHDMI_PICTURE_ASPECT_64_27 = 3,\n\tHDMI_PICTURE_ASPECT_256_135 = 4,\n\tHDMI_PICTURE_ASPECT_RESERVED = 5,\n};\n\nenum hdmi_quantization_range {\n\tHDMI_QUANTIZATION_RANGE_DEFAULT = 0,\n\tHDMI_QUANTIZATION_RANGE_LIMITED = 1,\n\tHDMI_QUANTIZATION_RANGE_FULL = 2,\n\tHDMI_QUANTIZATION_RANGE_RESERVED = 3,\n};\n\nenum hdmi_scan_mode {\n\tHDMI_SCAN_MODE_NONE = 0,\n\tHDMI_SCAN_MODE_OVERSCAN = 1,\n\tHDMI_SCAN_MODE_UNDERSCAN = 2,\n\tHDMI_SCAN_MODE_RESERVED = 3,\n};\n\nenum hdmi_spd_sdi {\n\tHDMI_SPD_SDI_UNKNOWN = 0,\n\tHDMI_SPD_SDI_DSTB = 1,\n\tHDMI_SPD_SDI_DVDP = 2,\n\tHDMI_SPD_SDI_DVHS = 3,\n\tHDMI_SPD_SDI_HDDVR = 4,\n\tHDMI_SPD_SDI_DVC = 5,\n\tHDMI_SPD_SDI_DSC = 6,\n\tHDMI_SPD_SDI_VCD = 7,\n\tHDMI_SPD_SDI_GAME = 8,\n\tHDMI_SPD_SDI_PC = 9,\n\tHDMI_SPD_SDI_BD = 10,\n\tHDMI_SPD_SDI_SACD = 11,\n\tHDMI_SPD_SDI_HDDVD = 12,\n\tHDMI_SPD_SDI_PMP = 13,\n};\n\nenum hdmi_ycc_quantization_range {\n\tHDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0,\n\tHDMI_YCC_QUANTIZATION_RANGE_FULL = 1,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hpd_pin {\n\tHPD_NONE = 0,\n\tHPD_TV = 0,\n\tHPD_CRT = 1,\n\tHPD_SDVO_B = 2,\n\tHPD_SDVO_C = 3,\n\tHPD_PORT_A = 4,\n\tHPD_PORT_B = 5,\n\tHPD_PORT_C = 6,\n\tHPD_PORT_D = 7,\n\tHPD_PORT_E = 8,\n\tHPD_PORT_TC1 = 9,\n\tHPD_PORT_TC2 = 10,\n\tHPD_PORT_TC3 = 11,\n\tHPD_PORT_TC4 = 12,\n\tHPD_PORT_TC5 = 13,\n\tHPD_PORT_TC6 = 14,\n\tHPD_NUM_PINS = 15,\n};\n\nenum hpet_mode {\n\tHPET_MODE_UNUSED = 0,\n\tHPET_MODE_LEGACY = 1,\n\tHPET_MODE_CLOCKEVT = 2,\n\tHPET_MODE_DEVICE = 3,\n};\n\nenum hprobe_state {\n\tHPROBE_LEASED = 0,\n\tHPROBE_STABLE = 1,\n\tHPROBE_GONE = 2,\n\tHPROBE_CONSUMED = 3,\n};\n\nenum hpx_type3_cfg_loc {\n\tHPX_CFG_PCICFG = 0,\n\tHPX_CFG_PCIE_CAP = 1,\n\tHPX_CFG_PCIE_CAP_EXT = 2,\n\tHPX_CFG_VEND_CAP = 3,\n\tHPX_CFG_DVSEC = 4,\n\tHPX_CFG_MAX = 5,\n};\n\nenum hpx_type3_dev_type {\n\tHPX_TYPE_ENDPOINT = 1,\n\tHPX_TYPE_LEG_END = 2,\n\tHPX_TYPE_RC_END = 4,\n\tHPX_TYPE_RC_EC = 8,\n\tHPX_TYPE_ROOT_PORT = 16,\n\tHPX_TYPE_UPSTREAM = 32,\n\tHPX_TYPE_DOWNSTREAM = 64,\n\tHPX_TYPE_PCI_BRIDGE = 128,\n\tHPX_TYPE_PCIE_BRIDGE = 256,\n};\n\nenum hpx_type3_fn_type {\n\tHPX_FN_NORMAL = 1,\n\tHPX_FN_SRIOV_PHYS = 2,\n\tHPX_FN_SRIOV_VIRT = 4,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nenum hugetlb_memory_event {\n\tHUGETLB_MAX = 0,\n\tHUGETLB_NR_MEMORY_EVENTS = 1,\n};\n\nenum hugetlb_page_flags {\n\tHPG_restore_reserve = 0,\n\tHPG_migratable = 1,\n\tHPG_temporary = 2,\n\tHPG_freed = 3,\n\tHPG_vmemmap_optimized = 4,\n\tHPG_raw_hwp_unreliable = 5,\n\tHPG_cma = 6,\n\t__NR_HPAGEFLAGS = 7,\n};\n\nenum hugetlb_param {\n\tOpt_gid___5 = 0,\n\tOpt_min_size = 1,\n\tOpt_mode___5 = 2,\n\tOpt_nr_inodes = 3,\n\tOpt_pagesize = 4,\n\tOpt_size = 5,\n\tOpt_uid___5 = 6,\n};\n\nenum hugetlbfs_size_type {\n\tNO_SIZE = 0,\n\tSIZE_STD = 1,\n\tSIZE_PERCENT = 2,\n};\n\nenum hv_generic_set_format {\n\tHV_GENERIC_SET_SPARSE_4K = 0,\n\tHV_GENERIC_SET_ALL = 1,\n};\n\nenum hv_isolation_type {\n\tHV_ISOLATION_TYPE_NONE = 0,\n\tHV_ISOLATION_TYPE_VBS = 1,\n\tHV_ISOLATION_TYPE_SNP = 2,\n\tHV_ISOLATION_TYPE_TDX = 3,\n};\n\nenum hv_message_type {\n\tHVMSG_NONE = 0,\n\tHVMSG_UNMAPPED_GPA = 2147483648,\n\tHVMSG_GPA_INTERCEPT = 2147483649,\n\tHVMSG_TIMER_EXPIRED = 2147483664,\n\tHVMSG_INVALID_VP_REGISTER_VALUE = 2147483680,\n\tHVMSG_UNRECOVERABLE_EXCEPTION = 2147483681,\n\tHVMSG_UNSUPPORTED_FEATURE = 2147483682,\n\tHVMSG_OPAQUE_INTERCEPT = 2147483711,\n\tHVMSG_EVENTLOG_BUFFERCOMPLETE = 2147483712,\n\tHVMSG_HYPERCALL_INTERCEPT = 2147483728,\n\tHVMSG_SYNIC_EVENT_INTERCEPT = 2147483744,\n\tHVMSG_SYNIC_SINT_INTERCEPT = 2147483745,\n\tHVMSG_SYNIC_SINT_DELIVERABLE = 2147483746,\n\tHVMSG_ASYNC_CALL_COMPLETION = 2147483760,\n\tHVMSG_SCHEDULER_VP_SIGNAL_BITSET = 2147483904,\n\tHVMSG_SCHEDULER_VP_SIGNAL_PAIR = 2147483905,\n\tHVMSG_X64_IO_PORT_INTERCEPT = 2147549184,\n\tHVMSG_X64_MSR_INTERCEPT = 2147549185,\n\tHVMSG_X64_CPUID_INTERCEPT = 2147549186,\n\tHVMSG_X64_EXCEPTION_INTERCEPT = 2147549187,\n\tHVMSG_X64_APIC_EOI = 2147549188,\n\tHVMSG_X64_LEGACY_FP_ERROR = 2147549189,\n\tHVMSG_X64_IOMMU_PRQ = 2147549190,\n\tHVMSG_X64_HALT = 2147549191,\n\tHVMSG_X64_INTERRUPTION_DELIVERABLE = 2147549192,\n\tHVMSG_X64_SIPI_INTERCEPT = 2147549193,\n};\n\nenum hv_tlb_flush_fifos {\n\tHV_L1_TLB_FLUSH_FIFO = 0,\n\tHV_L2_TLB_FLUSH_FIFO = 1,\n\tHV_NR_TLB_FLUSH_FIFOS = 2,\n};\n\nenum hv_tsc_page_status {\n\tHV_TSC_PAGE_UNSET = 0,\n\tHV_TSC_PAGE_GUEST_CHANGED = 1,\n\tHV_TSC_PAGE_HOST_CHANGED = 2,\n\tHV_TSC_PAGE_SET = 3,\n\tHV_TSC_PAGE_BROKEN = 4,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwerr_error_type {\n\tHWERR_RECOV_CPU = 0,\n\tHWERR_RECOV_MEMORY = 1,\n\tHWERR_RECOV_PCI = 2,\n\tHWERR_RECOV_CXL = 3,\n\tHWERR_RECOV_OTHERS = 4,\n\tHWERR_RECOV_MAX = 5,\n};\n\nenum hwmon_chip_attributes {\n\thwmon_chip_temp_reset_history = 0,\n\thwmon_chip_in_reset_history = 1,\n\thwmon_chip_curr_reset_history = 2,\n\thwmon_chip_power_reset_history = 3,\n\thwmon_chip_register_tz = 4,\n\thwmon_chip_update_interval = 5,\n\thwmon_chip_alarms = 6,\n\thwmon_chip_samples = 7,\n\thwmon_chip_curr_samples = 8,\n\thwmon_chip_in_samples = 9,\n\thwmon_chip_power_samples = 10,\n\thwmon_chip_temp_samples = 11,\n\thwmon_chip_beep_enable = 12,\n\thwmon_chip_pec = 13,\n};\n\nenum hwmon_curr_attributes {\n\thwmon_curr_enable = 0,\n\thwmon_curr_input = 1,\n\thwmon_curr_min = 2,\n\thwmon_curr_max = 3,\n\thwmon_curr_lcrit = 4,\n\thwmon_curr_crit = 5,\n\thwmon_curr_average = 6,\n\thwmon_curr_lowest = 7,\n\thwmon_curr_highest = 8,\n\thwmon_curr_reset_history = 9,\n\thwmon_curr_label = 10,\n\thwmon_curr_alarm = 11,\n\thwmon_curr_min_alarm = 12,\n\thwmon_curr_max_alarm = 13,\n\thwmon_curr_lcrit_alarm = 14,\n\thwmon_curr_crit_alarm = 15,\n\thwmon_curr_rated_min = 16,\n\thwmon_curr_rated_max = 17,\n\thwmon_curr_beep = 18,\n};\n\nenum hwmon_energy_attributes {\n\thwmon_energy_enable = 0,\n\thwmon_energy_input = 1,\n\thwmon_energy_label = 2,\n};\n\nenum hwmon_fan_attributes {\n\thwmon_fan_enable = 0,\n\thwmon_fan_input = 1,\n\thwmon_fan_label = 2,\n\thwmon_fan_min = 3,\n\thwmon_fan_max = 4,\n\thwmon_fan_div = 5,\n\thwmon_fan_pulses = 6,\n\thwmon_fan_target = 7,\n\thwmon_fan_alarm = 8,\n\thwmon_fan_min_alarm = 9,\n\thwmon_fan_max_alarm = 10,\n\thwmon_fan_fault = 11,\n\thwmon_fan_beep = 12,\n};\n\nenum hwmon_humidity_attributes {\n\thwmon_humidity_enable = 0,\n\thwmon_humidity_input = 1,\n\thwmon_humidity_label = 2,\n\thwmon_humidity_min = 3,\n\thwmon_humidity_min_hyst = 4,\n\thwmon_humidity_max = 5,\n\thwmon_humidity_max_hyst = 6,\n\thwmon_humidity_alarm = 7,\n\thwmon_humidity_fault = 8,\n\thwmon_humidity_rated_min = 9,\n\thwmon_humidity_rated_max = 10,\n\thwmon_humidity_min_alarm = 11,\n\thwmon_humidity_max_alarm = 12,\n};\n\nenum hwmon_in_attributes {\n\thwmon_in_enable = 0,\n\thwmon_in_input = 1,\n\thwmon_in_min = 2,\n\thwmon_in_max = 3,\n\thwmon_in_lcrit = 4,\n\thwmon_in_crit = 5,\n\thwmon_in_average = 6,\n\thwmon_in_lowest = 7,\n\thwmon_in_highest = 8,\n\thwmon_in_reset_history = 9,\n\thwmon_in_label = 10,\n\thwmon_in_alarm = 11,\n\thwmon_in_min_alarm = 12,\n\thwmon_in_max_alarm = 13,\n\thwmon_in_lcrit_alarm = 14,\n\thwmon_in_crit_alarm = 15,\n\thwmon_in_rated_min = 16,\n\thwmon_in_rated_max = 17,\n\thwmon_in_beep = 18,\n\thwmon_in_fault = 19,\n};\n\nenum hwmon_intrusion_attributes {\n\thwmon_intrusion_alarm = 0,\n\thwmon_intrusion_beep = 1,\n};\n\nenum hwmon_power_attributes {\n\thwmon_power_enable = 0,\n\thwmon_power_average = 1,\n\thwmon_power_average_interval = 2,\n\thwmon_power_average_interval_max = 3,\n\thwmon_power_average_interval_min = 4,\n\thwmon_power_average_highest = 5,\n\thwmon_power_average_lowest = 6,\n\thwmon_power_average_max = 7,\n\thwmon_power_average_min = 8,\n\thwmon_power_input = 9,\n\thwmon_power_input_highest = 10,\n\thwmon_power_input_lowest = 11,\n\thwmon_power_reset_history = 12,\n\thwmon_power_accuracy = 13,\n\thwmon_power_cap = 14,\n\thwmon_power_cap_hyst = 15,\n\thwmon_power_cap_max = 16,\n\thwmon_power_cap_min = 17,\n\thwmon_power_min = 18,\n\thwmon_power_max = 19,\n\thwmon_power_crit = 20,\n\thwmon_power_lcrit = 21,\n\thwmon_power_label = 22,\n\thwmon_power_alarm = 23,\n\thwmon_power_cap_alarm = 24,\n\thwmon_power_min_alarm = 25,\n\thwmon_power_max_alarm = 26,\n\thwmon_power_lcrit_alarm = 27,\n\thwmon_power_crit_alarm = 28,\n\thwmon_power_rated_min = 29,\n\thwmon_power_rated_max = 30,\n};\n\nenum hwmon_pwm_attributes {\n\thwmon_pwm_input = 0,\n\thwmon_pwm_enable = 1,\n\thwmon_pwm_mode = 2,\n\thwmon_pwm_freq = 3,\n\thwmon_pwm_auto_channels_temp = 4,\n};\n\nenum hwmon_sensor_types {\n\thwmon_chip = 0,\n\thwmon_temp = 1,\n\thwmon_in = 2,\n\thwmon_curr = 3,\n\thwmon_power = 4,\n\thwmon_energy = 5,\n\thwmon_energy64 = 6,\n\thwmon_humidity = 7,\n\thwmon_fan = 8,\n\thwmon_pwm = 9,\n\thwmon_intrusion = 10,\n\thwmon_max = 11,\n};\n\nenum hwmon_temp_attributes {\n\thwmon_temp_enable = 0,\n\thwmon_temp_input = 1,\n\thwmon_temp_type = 2,\n\thwmon_temp_lcrit = 3,\n\thwmon_temp_lcrit_hyst = 4,\n\thwmon_temp_min = 5,\n\thwmon_temp_min_hyst = 6,\n\thwmon_temp_max = 7,\n\thwmon_temp_max_hyst = 8,\n\thwmon_temp_crit = 9,\n\thwmon_temp_crit_hyst = 10,\n\thwmon_temp_emergency = 11,\n\thwmon_temp_emergency_hyst = 12,\n\thwmon_temp_alarm = 13,\n\thwmon_temp_lcrit_alarm = 14,\n\thwmon_temp_min_alarm = 15,\n\thwmon_temp_max_alarm = 16,\n\thwmon_temp_crit_alarm = 17,\n\thwmon_temp_emergency_alarm = 18,\n\thwmon_temp_fault = 19,\n\thwmon_temp_offset = 20,\n\thwmon_temp_label = 21,\n\thwmon_temp_lowest = 22,\n\thwmon_temp_highest = 23,\n\thwmon_temp_reset_history = 24,\n\thwmon_temp_rated_min = 25,\n\thwmon_temp_rated_max = 26,\n\thwmon_temp_beep = 27,\n};\n\nenum hwp_cpufreq_attr_index {\n\tHWP_BASE_FREQUENCY_INDEX = 0,\n\tHWP_PERFORMANCE_PREFERENCE_INDEX = 1,\n\tHWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX = 2,\n\tHWP_CPUFREQ_ATTR_COUNT = 3,\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum hybrid_pmu_type {\n\tnot_hybrid = 0,\n\thybrid_small = 1,\n\thybrid_big = 2,\n\thybrid_tiny = 4,\n\thybrid_big_small = 3,\n\thybrid_small_tiny = 5,\n\thybrid_big_small_tiny = 7,\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nenum i2c_driver_flags {\n\tI2C_DRV_ACPI_WAIVE_D0_PROBE = 1,\n};\n\nenum i8042_controller_reset_mode {\n\tI8042_RESET_NEVER = 0,\n\tI8042_RESET_ALWAYS = 1,\n\tI8042_RESET_ON_S2RAM = 2,\n};\n\nenum i915_cache_level {\n\tI915_CACHE_NONE = 0,\n\tI915_CACHE_LLC = 1,\n\tI915_CACHE_L3_LLC = 2,\n\tI915_CACHE_WT = 3,\n\tI915_MAX_CACHE_LEVEL = 4,\n};\n\nenum i915_component_type {\n\tI915_COMPONENT_AUDIO = 1,\n\tI915_COMPONENT_HDCP = 2,\n\tI915_COMPONENT_PXP = 3,\n\tI915_COMPONENT_GSC_PROXY = 4,\n\tINTEL_COMPONENT_LB = 5,\n};\n\nenum i915_gem_engine_type {\n\tI915_GEM_ENGINE_TYPE_INVALID = 0,\n\tI915_GEM_ENGINE_TYPE_PHYSICAL = 1,\n\tI915_GEM_ENGINE_TYPE_BALANCED = 2,\n\tI915_GEM_ENGINE_TYPE_PARALLEL = 3,\n};\n\nenum i915_gtt_view_type {\n\tI915_GTT_VIEW_NORMAL = 0,\n\tI915_GTT_VIEW_ROTATED = 24,\n\tI915_GTT_VIEW_PARTIAL = 12,\n\tI915_GTT_VIEW_REMAPPED = 52,\n};\n\nenum i915_map_type {\n\tI915_MAP_WB = 0,\n\tI915_MAP_WC = 1,\n\tI915_MAP_FORCE_WB = 2147483648,\n\tI915_MAP_FORCE_WC = 2147483649,\n};\n\nenum i915_mmap_type {\n\tI915_MMAP_TYPE_GTT = 0,\n\tI915_MMAP_TYPE_WC = 1,\n\tI915_MMAP_TYPE_WB = 2,\n\tI915_MMAP_TYPE_UC = 3,\n\tI915_MMAP_TYPE_FIXED = 4,\n};\n\nenum i915_mocs_table_index {\n\tI915_MOCS_UNCACHED = 0,\n\tI915_MOCS_PTE = 1,\n\tI915_MOCS_CACHED = 2,\n};\n\nenum i915_pmu_tracked_events {\n\t__I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0,\n\t__I915_PMU_REQUESTED_FREQUENCY_ENABLED = 1,\n\t__I915_PMU_RC6_RESIDENCY_ENABLED = 2,\n\t__I915_PMU_TRACKED_EVENT_COUNT = 3,\n};\n\nenum i915_power_well_id {\n\tDISP_PW_ID_NONE = 0,\n\tVLV_DISP_PW_DISP2D = 1,\n\tBXT_DISP_PW_DPIO_CMN_A = 2,\n\tVLV_DISP_PW_DPIO_CMN_BC = 3,\n\tGLK_DISP_PW_DPIO_CMN_C = 4,\n\tCHV_DISP_PW_DPIO_CMN_D = 5,\n\tHSW_DISP_PW_GLOBAL = 6,\n\tSKL_DISP_PW_MISC_IO = 7,\n\tSKL_DISP_PW_1 = 8,\n\tSKL_DISP_PW_2 = 9,\n\tICL_DISP_PW_3 = 10,\n\tSKL_DISP_DC_OFF = 11,\n\tTGL_DISP_PW_TC_COLD_OFF = 12,\n};\n\nenum i915_request_state {\n\tI915_REQUEST_UNKNOWN = 0,\n\tI915_REQUEST_COMPLETE = 1,\n\tI915_REQUEST_PENDING = 2,\n\tI915_REQUEST_QUEUED = 3,\n\tI915_REQUEST_ACTIVE = 4,\n};\n\nenum i915_sw_fence_notify {\n\tFENCE_COMPLETE = 0,\n\tFENCE_FREE = 1,\n};\n\nenum i9xx_plane_id {\n\tPLANE_A = 0,\n\tPLANE_B = 1,\n\tPLANE_C = 2,\n};\n\nenum ibs_states {\n\tIBS_ENABLED = 0,\n\tIBS_STARTED = 1,\n\tIBS_STOPPING = 2,\n\tIBS_STOPPED = 3,\n\tIBS_MAX_STATES = 4,\n};\n\nenum icl_port_dpll_id {\n\tICL_PORT_DPLL_DEFAULT = 0,\n\tICL_PORT_DPLL_MG_PHY = 1,\n\tICL_PORT_DPLL_COUNT = 2,\n};\n\nenum id_action {\n\tID_REMOVE = 0,\n\tID_ADD = 1,\n};\n\nenum idle_boot_override {\n\tIDLE_NO_OVERRIDE = 0,\n\tIDLE_HALT = 1,\n\tIDLE_NOMWAIT = 2,\n\tIDLE_POLL = 3,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum insn_mmio_type {\n\tINSN_MMIO_DECODE_FAILED = 0,\n\tINSN_MMIO_WRITE = 1,\n\tINSN_MMIO_WRITE_IMM = 2,\n\tINSN_MMIO_READ = 3,\n\tINSN_MMIO_READ_ZERO_EXTEND = 4,\n\tINSN_MMIO_READ_SIGN_EXTEND = 5,\n\tINSN_MMIO_MOVS = 6,\n};\n\nenum insn_mode {\n\tINSN_MODE_32 = 0,\n\tINSN_MODE_64 = 1,\n\tINSN_MODE_KERN = 2,\n\tINSN_NUM_MODES = 3,\n};\n\nenum insn_type {\n\tCALL = 0,\n\tNOP = 1,\n\tJMP = 2,\n\tRET = 3,\n\tJCC = 4,\n};\n\nenum intel_backlight_type {\n\tINTEL_BACKLIGHT_PMIC = 0,\n\tINTEL_BACKLIGHT_LPSS = 1,\n\tINTEL_BACKLIGHT_DISPLAY_DDI = 2,\n\tINTEL_BACKLIGHT_DSI_DCS = 3,\n\tINTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE = 4,\n\tINTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE = 5,\n};\n\nenum intel_bootrom_load_status {\n\tINTEL_BOOTROM_STATUS_NO_KEY_FOUND = 19,\n\tINTEL_BOOTROM_STATUS_AES_PROD_KEY_FOUND = 26,\n\tINTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE = 43,\n\tINTEL_BOOTROM_STATUS_RSA_FAILED = 80,\n\tINTEL_BOOTROM_STATUS_PAVPC_FAILED = 115,\n\tINTEL_BOOTROM_STATUS_WOPCM_FAILED = 116,\n\tINTEL_BOOTROM_STATUS_LOADLOC_FAILED = 117,\n\tINTEL_BOOTROM_STATUS_JUMP_PASSED = 118,\n\tINTEL_BOOTROM_STATUS_JUMP_FAILED = 119,\n\tINTEL_BOOTROM_STATUS_RC6CTXCONFIG_FAILED = 121,\n\tINTEL_BOOTROM_STATUS_MPUMAP_INCORRECT = 122,\n\tINTEL_BOOTROM_STATUS_EXCEPTION = 126,\n};\n\nenum intel_broadcast_rgb {\n\tINTEL_BROADCAST_RGB_AUTO = 0,\n\tINTEL_BROADCAST_RGB_FULL = 1,\n\tINTEL_BROADCAST_RGB_LIMITED = 2,\n};\n\nenum intel_color_block {\n\tINTEL_PLANE_CB_PRE_CSC_LUT = 0,\n\tINTEL_PLANE_CB_CSC = 1,\n\tINTEL_PLANE_CB_POST_CSC_LUT = 2,\n\tINTEL_PLANE_CB_3DLUT = 3,\n\tINTEL_CB_MAX = 4,\n};\n\nenum intel_cpu_type {\n\tINTEL_CPU_TYPE_UNKNOWN = 0,\n\tINTEL_CPU_TYPE_ATOM = 32,\n\tINTEL_CPU_TYPE_CORE = 64,\n};\n\nenum intel_ddb_partitioning {\n\tINTEL_DDB_PART_1_2 = 0,\n\tINTEL_DDB_PART_5_6 = 1,\n};\n\nenum intel_display_power_domain {\n\tPOWER_DOMAIN_DISPLAY_CORE = 0,\n\tPOWER_DOMAIN_PIPE_A = 1,\n\tPOWER_DOMAIN_PIPE_B = 2,\n\tPOWER_DOMAIN_PIPE_C = 3,\n\tPOWER_DOMAIN_PIPE_D = 4,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_A = 5,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_B = 6,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_C = 7,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_D = 8,\n\tPOWER_DOMAIN_TRANSCODER_A = 9,\n\tPOWER_DOMAIN_TRANSCODER_B = 10,\n\tPOWER_DOMAIN_TRANSCODER_C = 11,\n\tPOWER_DOMAIN_TRANSCODER_D = 12,\n\tPOWER_DOMAIN_TRANSCODER_EDP = 13,\n\tPOWER_DOMAIN_TRANSCODER_DSI_A = 14,\n\tPOWER_DOMAIN_TRANSCODER_DSI_C = 15,\n\tPOWER_DOMAIN_TRANSCODER_VDSC_PW2 = 16,\n\tPOWER_DOMAIN_PORT_DDI_LANES_A = 17,\n\tPOWER_DOMAIN_PORT_DDI_LANES_B = 18,\n\tPOWER_DOMAIN_PORT_DDI_LANES_C = 19,\n\tPOWER_DOMAIN_PORT_DDI_LANES_D = 20,\n\tPOWER_DOMAIN_PORT_DDI_LANES_E = 21,\n\tPOWER_DOMAIN_PORT_DDI_LANES_F = 22,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC1 = 23,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC2 = 24,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC3 = 25,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC4 = 26,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC5 = 27,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC6 = 28,\n\tPOWER_DOMAIN_PORT_DDI_IO_A = 29,\n\tPOWER_DOMAIN_PORT_DDI_IO_B = 30,\n\tPOWER_DOMAIN_PORT_DDI_IO_C = 31,\n\tPOWER_DOMAIN_PORT_DDI_IO_D = 32,\n\tPOWER_DOMAIN_PORT_DDI_IO_E = 33,\n\tPOWER_DOMAIN_PORT_DDI_IO_F = 34,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC1 = 35,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC2 = 36,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC3 = 37,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC4 = 38,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC5 = 39,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC6 = 40,\n\tPOWER_DOMAIN_PORT_DSI = 41,\n\tPOWER_DOMAIN_PORT_CRT = 42,\n\tPOWER_DOMAIN_PORT_OTHER = 43,\n\tPOWER_DOMAIN_VGA = 44,\n\tPOWER_DOMAIN_AUDIO_MMIO = 45,\n\tPOWER_DOMAIN_AUDIO_PLAYBACK = 46,\n\tPOWER_DOMAIN_AUX_IO_A = 47,\n\tPOWER_DOMAIN_AUX_IO_B = 48,\n\tPOWER_DOMAIN_AUX_IO_C = 49,\n\tPOWER_DOMAIN_AUX_IO_D = 50,\n\tPOWER_DOMAIN_AUX_IO_E = 51,\n\tPOWER_DOMAIN_AUX_IO_F = 52,\n\tPOWER_DOMAIN_AUX_A = 53,\n\tPOWER_DOMAIN_AUX_B = 54,\n\tPOWER_DOMAIN_AUX_C = 55,\n\tPOWER_DOMAIN_AUX_D = 56,\n\tPOWER_DOMAIN_AUX_E = 57,\n\tPOWER_DOMAIN_AUX_F = 58,\n\tPOWER_DOMAIN_AUX_USBC1 = 59,\n\tPOWER_DOMAIN_AUX_USBC2 = 60,\n\tPOWER_DOMAIN_AUX_USBC3 = 61,\n\tPOWER_DOMAIN_AUX_USBC4 = 62,\n\tPOWER_DOMAIN_AUX_USBC5 = 63,\n\tPOWER_DOMAIN_AUX_USBC6 = 64,\n\tPOWER_DOMAIN_AUX_TBT1 = 65,\n\tPOWER_DOMAIN_AUX_TBT2 = 66,\n\tPOWER_DOMAIN_AUX_TBT3 = 67,\n\tPOWER_DOMAIN_AUX_TBT4 = 68,\n\tPOWER_DOMAIN_AUX_TBT5 = 69,\n\tPOWER_DOMAIN_AUX_TBT6 = 70,\n\tPOWER_DOMAIN_GMBUS = 71,\n\tPOWER_DOMAIN_GT_IRQ = 72,\n\tPOWER_DOMAIN_DC_OFF = 73,\n\tPOWER_DOMAIN_TC_COLD_OFF = 74,\n\tPOWER_DOMAIN_INIT = 75,\n\tPOWER_DOMAIN_NUM = 76,\n\tPOWER_DOMAIN_INVALID = 76,\n};\n\nenum intel_display_wa {\n\tINTEL_DISPLAY_WA_13012396614 = 0,\n\tINTEL_DISPLAY_WA_14011503117 = 1,\n\tINTEL_DISPLAY_WA_14025769978 = 2,\n\tINTEL_DISPLAY_WA_15018326506 = 3,\n\tINTEL_DISPLAY_WA_16023588340 = 4,\n\tINTEL_DISPLAY_WA_16025573575 = 5,\n\tINTEL_DISPLAY_WA_22014263786 = 6,\n};\n\nenum intel_dmc_id {\n\tDMC_FW_MAIN = 0,\n\tDMC_FW_PIPEA = 1,\n\tDMC_FW_PIPEB = 2,\n\tDMC_FW_PIPEC = 3,\n\tDMC_FW_PIPED = 4,\n\tDMC_FW_MAX = 5,\n};\n\nenum intel_dp_aux_backlight_modparam {\n\tINTEL_DP_AUX_BACKLIGHT_AUTO = -1,\n\tINTEL_DP_AUX_BACKLIGHT_OFF = 0,\n\tINTEL_DP_AUX_BACKLIGHT_ON = 1,\n\tINTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,\n\tINTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,\n};\n\nenum intel_dpll_id {\n\tDPLL_ID_PRIVATE = -1,\n\tDPLL_ID_PCH_PLL_A = 0,\n\tDPLL_ID_PCH_PLL_B = 1,\n\tDPLL_ID_WRPLL1 = 0,\n\tDPLL_ID_WRPLL2 = 1,\n\tDPLL_ID_SPLL = 2,\n\tDPLL_ID_LCPLL_810 = 3,\n\tDPLL_ID_LCPLL_1350 = 4,\n\tDPLL_ID_LCPLL_2700 = 5,\n\tDPLL_ID_SKL_DPLL0 = 0,\n\tDPLL_ID_SKL_DPLL1 = 1,\n\tDPLL_ID_SKL_DPLL2 = 2,\n\tDPLL_ID_SKL_DPLL3 = 3,\n\tDPLL_ID_ICL_DPLL0 = 0,\n\tDPLL_ID_ICL_DPLL1 = 1,\n\tDPLL_ID_EHL_DPLL4 = 2,\n\tDPLL_ID_ICL_TBTPLL = 2,\n\tDPLL_ID_ICL_MGPLL1 = 3,\n\tDPLL_ID_ICL_MGPLL2 = 4,\n\tDPLL_ID_ICL_MGPLL3 = 5,\n\tDPLL_ID_ICL_MGPLL4 = 6,\n\tDPLL_ID_TGL_MGPLL5 = 7,\n\tDPLL_ID_TGL_MGPLL6 = 8,\n\tDPLL_ID_DG1_DPLL0 = 0,\n\tDPLL_ID_DG1_DPLL1 = 1,\n\tDPLL_ID_DG1_DPLL2 = 2,\n\tDPLL_ID_DG1_DPLL3 = 3,\n};\n\nenum intel_dram_type {\n\tINTEL_DRAM_UNKNOWN = 0,\n\tINTEL_DRAM_DDR2 = 1,\n\tINTEL_DRAM_DDR3 = 2,\n\tINTEL_DRAM_DDR4 = 3,\n\tINTEL_DRAM_LPDDR3 = 4,\n\tINTEL_DRAM_LPDDR4 = 5,\n\tINTEL_DRAM_DDR5 = 6,\n\tINTEL_DRAM_LPDDR5 = 7,\n\tINTEL_DRAM_GDDR = 8,\n\tINTEL_DRAM_GDDR_ECC = 9,\n\t__INTEL_DRAM_TYPE_MAX = 10,\n};\n\nenum intel_dsb_id {\n\tINTEL_DSB_0 = 0,\n\tINTEL_DSB_1 = 1,\n\tINTEL_DSB_2 = 2,\n\tI915_MAX_DSBS = 3,\n};\n\nenum intel_engine_id {\n\tRCS0 = 0,\n\tBCS0 = 1,\n\tBCS1 = 2,\n\tBCS2 = 3,\n\tBCS3 = 4,\n\tBCS4 = 5,\n\tBCS5 = 6,\n\tBCS6 = 7,\n\tBCS7 = 8,\n\tBCS8 = 9,\n\tVCS0 = 10,\n\tVCS1 = 11,\n\tVCS2 = 12,\n\tVCS3 = 13,\n\tVCS4 = 14,\n\tVCS5 = 15,\n\tVCS6 = 16,\n\tVCS7 = 17,\n\tVECS0 = 18,\n\tVECS1 = 19,\n\tVECS2 = 20,\n\tVECS3 = 21,\n\tCCS0 = 22,\n\tCCS1 = 23,\n\tCCS2 = 24,\n\tCCS3 = 25,\n\tGSC0 = 26,\n\tI915_NUM_ENGINES = 27,\n};\n\nenum intel_excl_state_type {\n\tINTEL_EXCL_UNUSED = 0,\n\tINTEL_EXCL_SHARED = 1,\n\tINTEL_EXCL_EXCLUSIVE = 2,\n};\n\nenum intel_fbc_id {\n\tINTEL_FBC_A = 0,\n\tINTEL_FBC_B = 1,\n\tINTEL_FBC_C = 2,\n\tINTEL_FBC_D = 3,\n\tI915_MAX_FBCS = 4,\n};\n\nenum intel_flipq_id {\n\tINTEL_FLIPQ_PLANE_1 = 0,\n\tINTEL_FLIPQ_PLANE_2 = 1,\n\tINTEL_FLIPQ_PLANE_3 = 2,\n\tINTEL_FLIPQ_GENERAL = 3,\n\tINTEL_FLIPQ_FAST = 4,\n\tMAX_INTEL_FLIPQ = 5,\n};\n\nenum intel_gsc_proxy_type {\n\tGSC_PROXY_MSG_TYPE_PROXY_INVALID = 0,\n\tGSC_PROXY_MSG_TYPE_PROXY_QUERY = 1,\n\tGSC_PROXY_MSG_TYPE_PROXY_PAYLOAD = 2,\n\tGSC_PROXY_MSG_TYPE_PROXY_END = 3,\n\tGSC_PROXY_MSG_TYPE_PROXY_NOTIFICATION = 4,\n};\n\nenum intel_gt_scratch_field {\n\tINTEL_GT_SCRATCH_FIELD_DEFAULT = 0,\n\tINTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,\n\tINTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,\n};\n\nenum intel_gt_sysfs_op {\n\tINTEL_GT_SYSFS_MIN = 0,\n\tINTEL_GT_SYSFS_MAX = 1,\n};\n\nenum intel_gt_type {\n\tGT_PRIMARY = 0,\n\tGT_TILE = 1,\n\tGT_MEDIA = 2,\n};\n\nenum intel_guc_action {\n\tINTEL_GUC_ACTION_DEFAULT = 0,\n\tINTEL_GUC_ACTION_REQUEST_PREEMPTION = 2,\n\tINTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 3,\n\tINTEL_GUC_ACTION_ALLOCATE_DOORBELL = 16,\n\tINTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 32,\n\tINTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 48,\n\tINTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 64,\n\tINTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 770,\n\tINTEL_GUC_ACTION_ENTER_S_STATE = 1281,\n\tINTEL_GUC_ACTION_EXIT_S_STATE = 1282,\n\tINTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 1286,\n\tINTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV = 1289,\n\tINTEL_GUC_ACTION_SCHED_CONTEXT = 4096,\n\tINTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 4097,\n\tINTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 4098,\n\tINTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 4099,\n\tINTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 4100,\n\tINTEL_GUC_ACTION_V69_SET_CONTEXT_PRIORITY = 4101,\n\tINTEL_GUC_ACTION_V69_SET_CONTEXT_EXECUTION_QUANTUM = 4102,\n\tINTEL_GUC_ACTION_V69_SET_CONTEXT_PREEMPTION_TIMEOUT = 4103,\n\tINTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 4104,\n\tINTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 4105,\n\tINTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 4107,\n\tINTEL_GUC_ACTION_SETUP_PC_GUCRC = 12292,\n\tINTEL_GUC_ACTION_AUTHENTICATE_HUC = 16384,\n\tINTEL_GUC_ACTION_GET_HWCONFIG = 16640,\n\tINTEL_GUC_ACTION_REGISTER_CONTEXT = 17666,\n\tINTEL_GUC_ACTION_DEREGISTER_CONTEXT = 17667,\n\tINTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 17920,\n\tINTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 17921,\n\tINTEL_GUC_ACTION_CLIENT_SOFT_RESET = 21767,\n\tINTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 21770,\n\tINTEL_GUC_ACTION_TLB_INVALIDATION = 28672,\n\tINTEL_GUC_ACTION_TLB_INVALIDATION_DONE = 28673,\n\tINTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 32770,\n\tINTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 32771,\n\tINTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 32772,\n\tINTEL_GUC_ACTION_NOTIFY_EXCEPTION = 32773,\n\tINTEL_GUC_ACTION_LIMIT = 32774,\n};\n\nenum intel_guc_load_status {\n\tINTEL_GUC_LOAD_STATUS_DEFAULT = 0,\n\tINTEL_GUC_LOAD_STATUS_START = 1,\n\tINTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH = 2,\n\tINTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH = 3,\n\tINTEL_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE = 4,\n\tINTEL_GUC_LOAD_STATUS_HWCONFIG_START = 5,\n\tINTEL_GUC_LOAD_STATUS_HWCONFIG_DONE = 6,\n\tINTEL_GUC_LOAD_STATUS_HWCONFIG_ERROR = 7,\n\tINTEL_GUC_LOAD_STATUS_GDT_DONE = 16,\n\tINTEL_GUC_LOAD_STATUS_IDT_DONE = 32,\n\tINTEL_GUC_LOAD_STATUS_LAPIC_DONE = 48,\n\tINTEL_GUC_LOAD_STATUS_GUCINT_DONE = 64,\n\tINTEL_GUC_LOAD_STATUS_DPC_READY = 80,\n\tINTEL_GUC_LOAD_STATUS_DPC_ERROR = 96,\n\tINTEL_GUC_LOAD_STATUS_EXCEPTION = 112,\n\tINTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID = 113,\n\tINTEL_GUC_LOAD_STATUS_PXP_TEARDOWN_CTRL_ENABLED = 114,\n\tINTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_START = 115,\n\tINTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID = 115,\n\tINTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID = 116,\n\tINTEL_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR = 117,\n\tINTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_END = 118,\n\tINTEL_GUC_LOAD_STATUS_READY = 240,\n};\n\nenum intel_guc_rc_options {\n\tINTEL_GUCRC_HOST_CONTROL = 0,\n\tINTEL_GUCRC_FIRMWARE_CONTROL = 1,\n};\n\nenum intel_guc_recv_message {\n\tINTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = 2,\n\tINTEL_GUC_RECV_MSG_EXCEPTION = 1073741824,\n};\n\nenum intel_guc_state_capture_event_status {\n\tINTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0,\n\tINTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 1,\n};\n\nenum intel_guc_tlb_inval_mode {\n\tINTEL_GUC_TLB_INVAL_MODE_HEAVY = 0,\n\tINTEL_GUC_TLB_INVAL_MODE_LITE = 1,\n};\n\nenum intel_guc_tlb_invalidation_type {\n\tINTEL_GUC_TLB_INVAL_ENGINES = 0,\n\tINTEL_GUC_TLB_INVAL_GUC = 3,\n};\n\nenum intel_hotplug_state {\n\tINTEL_HOTPLUG_UNCHANGED = 0,\n\tINTEL_HOTPLUG_CHANGED = 1,\n\tINTEL_HOTPLUG_RETRY = 2,\n};\n\nenum intel_huc_authentication_type {\n\tINTEL_HUC_AUTH_BY_GUC = 0,\n\tINTEL_HUC_AUTH_BY_GSC = 1,\n\tINTEL_HUC_AUTH_MAX_MODES = 2,\n};\n\nenum intel_huc_delayed_load_status {\n\tINTEL_HUC_WAITING_ON_GSC = 0,\n\tINTEL_HUC_WAITING_ON_PXP = 1,\n\tINTEL_HUC_DELAYED_LOAD_ERROR = 2,\n};\n\nenum intel_memory_type {\n\tINTEL_MEMORY_SYSTEM = 0,\n\tINTEL_MEMORY_LOCAL = 1,\n\tINTEL_MEMORY_STOLEN_SYSTEM = 2,\n\tINTEL_MEMORY_STOLEN_LOCAL = 3,\n\tINTEL_MEMORY_MOCK = 4,\n};\n\nenum intel_native_id {\n\tINTEL_ATOM_CMT_NATIVE_ID = 2,\n\tINTEL_ATOM_SKT_NATIVE_ID = 3,\n};\n\nenum intel_output_format {\n\tINTEL_OUTPUT_FORMAT_RGB = 0,\n\tINTEL_OUTPUT_FORMAT_YCBCR420 = 1,\n\tINTEL_OUTPUT_FORMAT_YCBCR444 = 2,\n};\n\nenum intel_output_type {\n\tINTEL_OUTPUT_UNUSED = 0,\n\tINTEL_OUTPUT_ANALOG = 1,\n\tINTEL_OUTPUT_DVO = 2,\n\tINTEL_OUTPUT_SDVO = 3,\n\tINTEL_OUTPUT_LVDS = 4,\n\tINTEL_OUTPUT_TVOUT = 5,\n\tINTEL_OUTPUT_HDMI = 6,\n\tINTEL_OUTPUT_DP = 7,\n\tINTEL_OUTPUT_EDP = 8,\n\tINTEL_OUTPUT_DSI = 9,\n\tINTEL_OUTPUT_DDI = 10,\n\tINTEL_OUTPUT_DP_MST = 11,\n};\n\nenum intel_panel_replay_dsc_support {\n\tINTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED = 0,\n\tINTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY = 1,\n\tINTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE = 2,\n};\n\nenum intel_pch {\n\tPCH_NOP = -1,\n\tPCH_NONE = 0,\n\tPCH_IBX = 1,\n\tPCH_CPT = 2,\n\tPCH_LPT_H = 3,\n\tPCH_LPT_LP = 4,\n\tPCH_SPT = 5,\n\tPCH_CNP = 6,\n\tPCH_ICP = 7,\n\tPCH_TGP = 8,\n\tPCH_ADP = 9,\n\tPCH_DG1 = 1024,\n\tPCH_DG2 = 1025,\n\tPCH_MTL = 1026,\n\tPCH_LNL = 1027,\n};\n\nenum intel_pipe_crc_source {\n\tINTEL_PIPE_CRC_SOURCE_NONE = 0,\n\tINTEL_PIPE_CRC_SOURCE_PLANE1 = 1,\n\tINTEL_PIPE_CRC_SOURCE_PLANE2 = 2,\n\tINTEL_PIPE_CRC_SOURCE_PLANE3 = 3,\n\tINTEL_PIPE_CRC_SOURCE_PLANE4 = 4,\n\tINTEL_PIPE_CRC_SOURCE_PLANE5 = 5,\n\tINTEL_PIPE_CRC_SOURCE_PLANE6 = 6,\n\tINTEL_PIPE_CRC_SOURCE_PLANE7 = 7,\n\tINTEL_PIPE_CRC_SOURCE_PIPE = 8,\n\tINTEL_PIPE_CRC_SOURCE_TV = 9,\n\tINTEL_PIPE_CRC_SOURCE_DP_B = 10,\n\tINTEL_PIPE_CRC_SOURCE_DP_C = 11,\n\tINTEL_PIPE_CRC_SOURCE_DP_D = 12,\n\tINTEL_PIPE_CRC_SOURCE_AUTO = 13,\n\tINTEL_PIPE_CRC_SOURCE_MAX = 14,\n};\n\nenum intel_platform {\n\tINTEL_PLATFORM_UNINITIALIZED = 0,\n\tINTEL_I830 = 1,\n\tINTEL_I845G = 2,\n\tINTEL_I85X = 3,\n\tINTEL_I865G = 4,\n\tINTEL_I915G = 5,\n\tINTEL_I915GM = 6,\n\tINTEL_I945G = 7,\n\tINTEL_I945GM = 8,\n\tINTEL_G33 = 9,\n\tINTEL_PINEVIEW = 10,\n\tINTEL_I965G = 11,\n\tINTEL_I965GM = 12,\n\tINTEL_G45 = 13,\n\tINTEL_GM45 = 14,\n\tINTEL_IRONLAKE = 15,\n\tINTEL_SANDYBRIDGE = 16,\n\tINTEL_IVYBRIDGE = 17,\n\tINTEL_VALLEYVIEW = 18,\n\tINTEL_HASWELL = 19,\n\tINTEL_BROADWELL = 20,\n\tINTEL_CHERRYVIEW = 21,\n\tINTEL_SKYLAKE = 22,\n\tINTEL_BROXTON = 23,\n\tINTEL_KABYLAKE = 24,\n\tINTEL_GEMINILAKE = 25,\n\tINTEL_COFFEELAKE = 26,\n\tINTEL_COMETLAKE = 27,\n\tINTEL_ICELAKE = 28,\n\tINTEL_ELKHARTLAKE = 29,\n\tINTEL_JASPERLAKE = 30,\n\tINTEL_TIGERLAKE = 31,\n\tINTEL_ROCKETLAKE = 32,\n\tINTEL_DG1 = 33,\n\tINTEL_ALDERLAKE_S = 34,\n\tINTEL_ALDERLAKE_P = 35,\n\tINTEL_DG2 = 36,\n\tINTEL_METEORLAKE = 37,\n\tINTEL_MAX_PLATFORMS = 38,\n};\n\nenum intel_ppgtt_type {\n\tINTEL_PPGTT_NONE = 0,\n\tINTEL_PPGTT_ALIASING = 1,\n\tINTEL_PPGTT_FULL = 2,\n};\n\nenum intel_quirk_id {\n\tQUIRK_BACKLIGHT_PRESENT = 0,\n\tQUIRK_INCREASE_DDI_DISABLED_TIME = 1,\n\tQUIRK_INCREASE_T12_DELAY = 2,\n\tQUIRK_INVERT_BRIGHTNESS = 3,\n\tQUIRK_LVDS_SSC_DISABLE = 4,\n\tQUIRK_NO_PPS_BACKLIGHT_POWER_HOOK = 5,\n\tQUIRK_FW_SYNC_LEN = 6,\n\tQUIRK_EDP_LIMIT_RATE_HBR2 = 7,\n};\n\nenum intel_rc6_res_type {\n\tINTEL_RC6_RES_RC6_LOCKED = 0,\n\tINTEL_RC6_RES_RC6 = 1,\n\tINTEL_RC6_RES_RC6p = 2,\n\tINTEL_RC6_RES_RC6pp = 3,\n\tINTEL_RC6_RES_MAX = 4,\n\tINTEL_RC6_RES_VLV_MEDIA = 2,\n};\n\nenum intel_region_id {\n\tINTEL_REGION_SMEM = 0,\n\tINTEL_REGION_LMEM_0 = 1,\n\tINTEL_REGION_LMEM_1 = 2,\n\tINTEL_REGION_LMEM_2 = 3,\n\tINTEL_REGION_LMEM_3 = 4,\n\tINTEL_REGION_STOLEN_SMEM = 5,\n\tINTEL_REGION_STOLEN_LMEM = 6,\n\tINTEL_REGION_UNKNOWN = 7,\n};\n\nenum intel_sbi_destination {\n\tSBI_ICLK = 0,\n\tSBI_MPHY = 1,\n};\n\nenum intel_steering_type {\n\tL3BANK = 0,\n\tMSLICE = 1,\n\tLNCF = 2,\n\tGAM = 3,\n\tDSS = 4,\n\tOADDRM = 5,\n\tINSTANCE0 = 6,\n\tNUM_STEERING_TYPES = 7,\n};\n\nenum intel_step {\n\tSTEP_NONE = 0,\n\tSTEP_A0 = 1,\n\tSTEP_A1 = 2,\n\tSTEP_A2 = 3,\n\tSTEP_A3 = 4,\n\tSTEP_B0 = 5,\n\tSTEP_B1 = 6,\n\tSTEP_B2 = 7,\n\tSTEP_B3 = 8,\n\tSTEP_C0 = 9,\n\tSTEP_C1 = 10,\n\tSTEP_C2 = 11,\n\tSTEP_C3 = 12,\n\tSTEP_D0 = 13,\n\tSTEP_D1 = 14,\n\tSTEP_D2 = 15,\n\tSTEP_D3 = 16,\n\tSTEP_E0 = 17,\n\tSTEP_E1 = 18,\n\tSTEP_E2 = 19,\n\tSTEP_E3 = 20,\n\tSTEP_F0 = 21,\n\tSTEP_F1 = 22,\n\tSTEP_F2 = 23,\n\tSTEP_F3 = 24,\n\tSTEP_G0 = 25,\n\tSTEP_G1 = 26,\n\tSTEP_G2 = 27,\n\tSTEP_G3 = 28,\n\tSTEP_H0 = 29,\n\tSTEP_H1 = 30,\n\tSTEP_H2 = 31,\n\tSTEP_H3 = 32,\n\tSTEP_I0 = 33,\n\tSTEP_I1 = 34,\n\tSTEP_I2 = 35,\n\tSTEP_I3 = 36,\n\tSTEP_J0 = 37,\n\tSTEP_J1 = 38,\n\tSTEP_J2 = 39,\n\tSTEP_J3 = 40,\n\tSTEP_FUTURE = 41,\n\tSTEP_FOREVER = 42,\n};\n\nenum intel_submission_method {\n\tINTEL_SUBMISSION_RING = 0,\n\tINTEL_SUBMISSION_ELSP = 1,\n\tINTEL_SUBMISSION_GUC = 2,\n};\n\nenum intel_tc_pin_assignment {\n\tINTEL_TC_PIN_ASSIGNMENT_NONE = 0,\n\tINTEL_TC_PIN_ASSIGNMENT_A = 1,\n\tINTEL_TC_PIN_ASSIGNMENT_B = 2,\n\tINTEL_TC_PIN_ASSIGNMENT_C = 3,\n\tINTEL_TC_PIN_ASSIGNMENT_D = 4,\n\tINTEL_TC_PIN_ASSIGNMENT_E = 5,\n\tINTEL_TC_PIN_ASSIGNMENT_F = 6,\n};\n\nenum intel_uc_fw_status {\n\tINTEL_UC_FIRMWARE_NOT_SUPPORTED = -1,\n\tINTEL_UC_FIRMWARE_UNINITIALIZED = 0,\n\tINTEL_UC_FIRMWARE_DISABLED = 1,\n\tINTEL_UC_FIRMWARE_SELECTED = 2,\n\tINTEL_UC_FIRMWARE_MISSING = 3,\n\tINTEL_UC_FIRMWARE_ERROR = 4,\n\tINTEL_UC_FIRMWARE_AVAILABLE = 5,\n\tINTEL_UC_FIRMWARE_INIT_FAIL = 6,\n\tINTEL_UC_FIRMWARE_LOADABLE = 7,\n\tINTEL_UC_FIRMWARE_LOAD_FAIL = 8,\n\tINTEL_UC_FIRMWARE_TRANSFERRED = 9,\n\tINTEL_UC_FIRMWARE_RUNNING = 10,\n};\n\nenum intel_uc_fw_type {\n\tINTEL_UC_FW_TYPE_GUC = 0,\n\tINTEL_UC_FW_TYPE_HUC = 1,\n\tINTEL_UC_FW_TYPE_GSC = 2,\n};\n\nenum intercept_words {\n\tINTERCEPT_CR = 0,\n\tINTERCEPT_DR = 1,\n\tINTERCEPT_EXCEPTION = 2,\n\tINTERCEPT_WORD3 = 3,\n\tINTERCEPT_WORD4 = 4,\n\tINTERCEPT_WORD5 = 5,\n\tMAX_INTERCEPT = 6,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioapic_domain_type {\n\tIOAPIC_DOMAIN_INVALID = 0,\n\tIOAPIC_DOMAIN_LEGACY = 1,\n\tIOAPIC_DOMAIN_STRICT = 2,\n\tIOAPIC_DOMAIN_DYNAMIC = 3,\n};\n\nenum ioc_running {\n\tIOC_IDLE = 0,\n\tIOC_RUNNING = 1,\n\tIOC_STOP = 2,\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_NOEXEC = 1,\n\tIOMMU_CAP_PRE_BOOT_PROTECTION = 2,\n\tIOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3,\n\tIOMMU_CAP_DEFERRED_FLUSH = 4,\n\tIOMMU_CAP_DIRTY_TRACKING = 5,\n};\n\nenum iommu_dma_queue_type {\n\tIOMMU_DMA_OPTS_PER_CPU_QUEUE = 0,\n\tIOMMU_DMA_OPTS_SINGLE_QUEUE = 1,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum iommu_fault_type {\n\tIOMMU_FAULT_PAGE_REQ = 1,\n};\n\nenum iommu_hw_info_type {\n\tIOMMU_HW_INFO_TYPE_NONE = 0,\n\tIOMMU_HW_INFO_TYPE_DEFAULT = 0,\n\tIOMMU_HW_INFO_TYPE_INTEL_VTD = 1,\n\tIOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,\n\tIOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,\n\tIOMMU_HW_INFO_TYPE_AMD = 4,\n};\n\nenum iommu_hw_info_vtd_flags {\n\tIOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1,\n};\n\nenum iommu_hw_queue_type {\n\tIOMMU_HW_QUEUE_TYPE_DEFAULT = 0,\n\tIOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,\n};\n\nenum iommu_hwpt_data_type {\n\tIOMMU_HWPT_DATA_NONE = 0,\n\tIOMMU_HWPT_DATA_VTD_S1 = 1,\n\tIOMMU_HWPT_DATA_ARM_SMMUV3 = 2,\n\tIOMMU_HWPT_DATA_AMD_GUEST = 3,\n};\n\nenum iommu_hwpt_invalidate_data_type {\n\tIOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0,\n\tIOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1,\n};\n\nenum iommu_hwpt_vtd_s1_flags {\n\tIOMMU_VTD_S1_SRE = 1,\n\tIOMMU_VTD_S1_EAFE = 2,\n\tIOMMU_VTD_S1_WPE = 4,\n};\n\nenum iommu_hwpt_vtd_s1_invalidate_flags {\n\tIOMMU_VTD_INV_FLAGS_LEAF = 1,\n};\n\nenum iommu_init_state {\n\tIOMMU_START_STATE = 0,\n\tIOMMU_IVRS_DETECTED = 1,\n\tIOMMU_ACPI_FINISHED = 2,\n\tIOMMU_ENABLED = 3,\n\tIOMMU_PCI_INIT = 4,\n\tIOMMU_INTERRUPTS_EN = 5,\n\tIOMMU_INITIALIZED = 6,\n\tIOMMU_NOT_FOUND = 7,\n\tIOMMU_INIT_ERROR = 8,\n\tIOMMU_CMDLINE_DISABLED = 9,\n};\n\nenum iommu_page_response_code {\n\tIOMMU_PAGE_RESP_SUCCESS = 0,\n\tIOMMU_PAGE_RESP_INVALID = 1,\n\tIOMMU_PAGE_RESP_FAILURE = 2,\n};\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nenum iommu_viommu_type {\n\tIOMMU_VIOMMU_TYPE_DEFAULT = 0,\n\tIOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,\n\tIOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,\n};\n\nenum iommufd_hwpt_alloc_flags {\n\tIOMMU_HWPT_ALLOC_NEST_PARENT = 1,\n\tIOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2,\n\tIOMMU_HWPT_FAULT_ID_VALID = 4,\n\tIOMMU_HWPT_ALLOC_PASID = 8,\n};\n\nenum iommufd_object_type {\n\tIOMMUFD_OBJ_NONE = 0,\n\tIOMMUFD_OBJ_ANY = 0,\n\tIOMMUFD_OBJ_DEVICE = 1,\n\tIOMMUFD_OBJ_HWPT_PAGING = 2,\n\tIOMMUFD_OBJ_HWPT_NESTED = 3,\n\tIOMMUFD_OBJ_IOAS = 4,\n\tIOMMUFD_OBJ_ACCESS = 5,\n\tIOMMUFD_OBJ_FAULT = 6,\n\tIOMMUFD_OBJ_VIOMMU = 7,\n\tIOMMUFD_OBJ_VDEVICE = 8,\n\tIOMMUFD_OBJ_VEVENTQ = 9,\n\tIOMMUFD_OBJ_HW_QUEUE = 10,\n\tIOMMUFD_OBJ_MAX = 11,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum irq_alloc_type {\n\tX86_IRQ_ALLOC_TYPE_IOAPIC = 1,\n\tX86_IRQ_ALLOC_TYPE_HPET = 2,\n\tX86_IRQ_ALLOC_TYPE_PCI_MSI = 3,\n\tX86_IRQ_ALLOC_TYPE_PCI_MSIX = 4,\n\tX86_IRQ_ALLOC_TYPE_DMAR = 5,\n\tX86_IRQ_ALLOC_TYPE_AMDVI = 6,\n\tX86_IRQ_ALLOC_TYPE_UV = 7,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irq_remap_cap {\n\tIRQ_POSTING_CAP = 0,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum isofs_file_format {\n\tisofs_file_normal = 0,\n\tisofs_file_sparse = 1,\n\tisofs_file_compressed = 2,\n};\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum its_mitigation {\n\tITS_MITIGATION_OFF = 0,\n\tITS_MITIGATION_AUTO = 1,\n\tITS_MITIGATION_VMEXIT_ONLY = 2,\n\tITS_MITIGATION_ALIGNED_THUNKS = 3,\n\tITS_MITIGATION_RETPOLINE_STUFF = 4,\n};\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nenum kcmp_type {\n\tKCMP_FILE = 0,\n\tKCMP_VM = 1,\n\tKCMP_FILES = 2,\n\tKCMP_FS = 3,\n\tKCMP_SIGHAND = 4,\n\tKCMP_IO = 5,\n\tKCMP_SYSVSEM = 6,\n\tKCMP_EPOLL_TFD = 7,\n\tKCMP_TYPES = 8,\n};\n\nenum kcore_type {\n\tKCORE_TEXT = 0,\n\tKCORE_VMALLOC = 1,\n\tKCORE_RAM = 2,\n\tKCORE_VMEMMAP = 3,\n\tKCORE_USER = 4,\n};\n\nenum kernel_gp_hint {\n\tGP_NO_HINT = 0,\n\tGP_NON_CANONICAL = 1,\n\tGP_CANONICAL = 2,\n\tGP_LASS_VIOLATION = 3,\n\tGP_NULL_POINTER = 4,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_being_used_for {\n\tVERIFYING_MODULE_SIGNATURE = 0,\n\tVERIFYING_FIRMWARE_SIGNATURE = 1,\n\tVERIFYING_KEXEC_PE_SIGNATURE = 2,\n\tVERIFYING_KEY_SIGNATURE = 3,\n\tVERIFYING_KEY_SELF_SIGNATURE = 4,\n\tVERIFYING_UNSPECIFIED_SIGNATURE = 5,\n\tVERIFYING_BPF_SIGNATURE = 6,\n\tNR__KEY_BEING_USED_FOR = 7,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_CGROUP = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_DMA = 2,\n\tNR_KMALLOC_TYPES = 3,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum kprobe_slot_state {\n\tSLOT_CLEAN = 0,\n\tSLOT_DIRTY = 1,\n\tSLOT_USED = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum kvm_apic_logical_mode {\n\tKVM_APIC_MODE_SW_DISABLED = 0,\n\tKVM_APIC_MODE_XAPIC_CLUSTER = 1,\n\tKVM_APIC_MODE_XAPIC_FLAT = 2,\n\tKVM_APIC_MODE_X2APIC = 3,\n\tKVM_APIC_MODE_MAP_DISABLED = 4,\n};\n\nenum kvm_apicv_inhibit {\n\tAPICV_INHIBIT_REASON_DISABLED = 0,\n\tAPICV_INHIBIT_REASON_HYPERV = 1,\n\tAPICV_INHIBIT_REASON_ABSENT = 2,\n\tAPICV_INHIBIT_REASON_BLOCKIRQ = 3,\n\tAPICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED = 4,\n\tAPICV_INHIBIT_REASON_APIC_ID_MODIFIED = 5,\n\tAPICV_INHIBIT_REASON_APIC_BASE_MODIFIED = 6,\n\tAPICV_INHIBIT_REASON_NESTED = 7,\n\tAPICV_INHIBIT_REASON_IRQWIN = 8,\n\tAPICV_INHIBIT_REASON_PIT_REINJ = 9,\n\tAPICV_INHIBIT_REASON_SEV = 10,\n\tAPICV_INHIBIT_REASON_LOGICAL_ID_ALIASED = 11,\n\tAPICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG = 12,\n\tNR_APICV_INHIBIT_REASONS = 13,\n};\n\nenum kvm_bus {\n\tKVM_MMIO_BUS = 0,\n\tKVM_PIO_BUS = 1,\n\tKVM_VIRTIO_CCW_NOTIFY_BUS = 2,\n\tKVM_FAST_MMIO_BUS = 3,\n\tKVM_IOCSR_BUS = 4,\n\tKVM_NR_BUSES = 5,\n};\n\nenum kvm_device_type {\n\tKVM_DEV_TYPE_FSL_MPIC_20 = 1,\n\tKVM_DEV_TYPE_FSL_MPIC_42 = 2,\n\tKVM_DEV_TYPE_XICS = 3,\n\tKVM_DEV_TYPE_VFIO = 4,\n\tKVM_DEV_TYPE_ARM_VGIC_V2 = 5,\n\tKVM_DEV_TYPE_FLIC = 6,\n\tKVM_DEV_TYPE_ARM_VGIC_V3 = 7,\n\tKVM_DEV_TYPE_ARM_VGIC_ITS = 8,\n\tKVM_DEV_TYPE_XIVE = 9,\n\tKVM_DEV_TYPE_ARM_PV_TIME = 10,\n\tKVM_DEV_TYPE_RISCV_AIA = 11,\n\tKVM_DEV_TYPE_LOONGARCH_IPI = 12,\n\tKVM_DEV_TYPE_LOONGARCH_EIOINTC = 13,\n\tKVM_DEV_TYPE_LOONGARCH_PCHPIC = 14,\n\tKVM_DEV_TYPE_MAX = 15,\n};\n\nenum kvm_gfn_range_filter {\n\tKVM_FILTER_SHARED = 1,\n\tKVM_FILTER_PRIVATE = 2,\n};\n\nenum kvm_intr_type {\n\tKVM_HANDLING_IRQ = 1,\n\tKVM_HANDLING_NMI = 2,\n};\n\nenum kvm_irqchip_mode {\n\tKVM_IRQCHIP_NONE = 0,\n\tKVM_IRQCHIP_KERNEL = 1,\n\tKVM_IRQCHIP_SPLIT = 2,\n};\n\nenum kvm_mmu_type {\n\tKVM_SHADOW_MMU = 0,\n\tKVM_TDP_MMU = 1,\n\tKVM_NR_MMU_TYPES = 2,\n};\n\nenum kvm_mr_change {\n\tKVM_MR_CREATE = 0,\n\tKVM_MR_DELETE = 1,\n\tKVM_MR_MOVE = 2,\n\tKVM_MR_FLAGS_ONLY = 3,\n};\n\nenum kvm_msr_access {\n\tMSR_TYPE_R = 1,\n\tMSR_TYPE_W = 2,\n\tMSR_TYPE_RW = 3,\n};\n\nenum kvm_only_cpuid_leafs {\n\tCPUID_12_EAX = 22,\n\tCPUID_7_1_EDX = 23,\n\tCPUID_8000_0007_EDX = 24,\n\tCPUID_8000_0022_EAX = 25,\n\tCPUID_7_2_EDX = 26,\n\tCPUID_24_0_EBX = 27,\n\tCPUID_8000_0021_ECX = 28,\n\tCPUID_7_1_ECX = 29,\n\tCPUID_1E_1_EAX = 30,\n\tCPUID_24_1_ECX = 31,\n\tNR_KVM_CPU_CAPS = 32,\n\tNKVMCAPINTS = 10,\n};\n\nenum kvm_reg {\n\tVCPU_REGS_RAX = 0,\n\tVCPU_REGS_RCX = 1,\n\tVCPU_REGS_RDX = 2,\n\tVCPU_REGS_RBX = 3,\n\tVCPU_REGS_RSP = 4,\n\tVCPU_REGS_RBP = 5,\n\tVCPU_REGS_RSI = 6,\n\tVCPU_REGS_RDI = 7,\n\tVCPU_REGS_R8 = 8,\n\tVCPU_REGS_R9 = 9,\n\tVCPU_REGS_R10 = 10,\n\tVCPU_REGS_R11 = 11,\n\tVCPU_REGS_R12 = 12,\n\tVCPU_REGS_R13 = 13,\n\tVCPU_REGS_R14 = 14,\n\tVCPU_REGS_R15 = 15,\n\tVCPU_REGS_RIP = 16,\n\tNR_VCPU_REGS = 17,\n\tVCPU_EXREG_PDPTR = 17,\n\tVCPU_EXREG_CR0 = 18,\n\tVCPU_EXREG_CR3 = 19,\n\tVCPU_EXREG_ERAPS = 19,\n\tVCPU_EXREG_CR4 = 20,\n\tVCPU_EXREG_RFLAGS = 21,\n\tVCPU_EXREG_SEGMENTS = 22,\n\tVCPU_EXREG_EXIT_INFO_1 = 23,\n\tVCPU_EXREG_EXIT_INFO_2 = 24,\n};\n\nenum kvm_stat_kind {\n\tKVM_STAT_VM = 0,\n\tKVM_STAT_VCPU = 1,\n};\n\nenum kvm_suppress_eoi_broadcast_mode {\n\tKVM_SUPPRESS_EOI_BROADCAST_QUIRKED = 0,\n\tKVM_SUPPRESS_EOI_BROADCAST_ENABLED = 1,\n\tKVM_SUPPRESS_EOI_BROADCAST_DISABLED = 2,\n};\n\nenum kvm_tdp_mmu_root_types {\n\tKVM_INVALID_ROOTS = 1,\n\tKVM_DIRECT_ROOTS = 2,\n\tKVM_MIRROR_ROOTS = 4,\n\tKVM_VALID_ROOTS = 6,\n\tKVM_ALL_ROOTS = 7,\n};\n\nenum kvm_x86_run_flags {\n\tKVM_RUN_FORCE_IMMEDIATE_EXIT = 1,\n\tKVM_RUN_LOAD_GUEST_DR6 = 2,\n\tKVM_RUN_LOAD_DEBUGCTL = 4,\n};\n\nenum l1d_flush_mitigations {\n\tL1D_FLUSH_OFF = 0,\n\tL1D_FLUSH_ON = 1,\n};\n\nenum l1tf_mitigations {\n\tL1TF_MITIGATION_OFF = 0,\n\tL1TF_MITIGATION_AUTO = 1,\n\tL1TF_MITIGATION_FLUSH_NOWARN = 2,\n\tL1TF_MITIGATION_FLUSH = 3,\n\tL1TF_MITIGATION_FLUSH_NOSMT = 4,\n\tL1TF_MITIGATION_FULL = 5,\n\tL1TF_MITIGATION_FULL_FORCE = 6,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum lapic_lvt_entry {\n\tLVT_TIMER = 0,\n\tLVT_THERMAL_MONITOR = 1,\n\tLVT_PERFORMANCE_COUNTER = 2,\n\tLVT_LINT0 = 3,\n\tLVT_LINT1 = 4,\n\tLVT_ERROR = 5,\n\tLVT_CMCI = 6,\n\tKVM_APIC_MAX_NR_LVT_ENTRIES = 7,\n};\n\nenum lapic_mode {\n\tLAPIC_MODE_DISABLED = 0,\n\tLAPIC_MODE_INVALID = 1024,\n\tLAPIC_MODE_XAPIC = 2048,\n\tLAPIC_MODE_X2APIC = 3072,\n};\n\nenum latency_count {\n\tCOUNTS_10e2 = 0,\n\tCOUNTS_10e3 = 1,\n\tCOUNTS_10e4 = 2,\n\tCOUNTS_10e5 = 3,\n\tCOUNTS_10e6 = 4,\n\tCOUNTS_10e7 = 5,\n\tCOUNTS_10e8_plus = 6,\n\tCOUNTS_MIN = 7,\n\tCOUNTS_MAX = 8,\n\tCOUNTS_SUM = 9,\n\tCOUNTS_NUM = 10,\n};\n\nenum latency_type {\n\tDMAR_LATENCY_INV_IOTLB = 0,\n\tDMAR_LATENCY_INV_DEVTLB = 1,\n\tDMAR_LATENCY_INV_IEC = 2,\n\tDMAR_LATENCY_NUM = 3,\n};\n\nenum led_audio {\n\tLED_AUDIO_MUTE = 0,\n\tLED_AUDIO_MICMUTE = 1,\n\tNUM_AUDIO_LEDS = 2,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum led_default_state {\n\tLEDS_DEFSTATE_OFF = 0,\n\tLEDS_DEFSTATE_ON = 1,\n\tLEDS_DEFSTATE_KEEP = 2,\n};\n\nenum led_trigger_netdev_modes {\n\tTRIGGER_NETDEV_LINK = 0,\n\tTRIGGER_NETDEV_LINK_10 = 1,\n\tTRIGGER_NETDEV_LINK_100 = 2,\n\tTRIGGER_NETDEV_LINK_1000 = 3,\n\tTRIGGER_NETDEV_LINK_2500 = 4,\n\tTRIGGER_NETDEV_LINK_5000 = 5,\n\tTRIGGER_NETDEV_LINK_10000 = 6,\n\tTRIGGER_NETDEV_HALF_DUPLEX = 7,\n\tTRIGGER_NETDEV_FULL_DUPLEX = 8,\n\tTRIGGER_NETDEV_TX = 9,\n\tTRIGGER_NETDEV_RX = 10,\n\tTRIGGER_NETDEV_TX_ERR = 11,\n\tTRIGGER_NETDEV_RX_ERR = 12,\n\t__TRIGGER_NETDEV_MAX = 13,\n};\n\nenum link_inband_signalling {\n\tLINK_INBAND_DISABLE = 1,\n\tLINK_INBAND_ENABLE = 2,\n\tLINK_INBAND_BYPASS = 4,\n};\n\nenum lock_usage_bit {\n\tLOCK_USED_IN_HARDIRQ = 0,\n\tLOCK_USED_IN_HARDIRQ_READ = 1,\n\tLOCK_ENABLED_HARDIRQ = 2,\n\tLOCK_ENABLED_HARDIRQ_READ = 3,\n\tLOCK_USED_IN_SOFTIRQ = 4,\n\tLOCK_USED_IN_SOFTIRQ_READ = 5,\n\tLOCK_ENABLED_SOFTIRQ = 6,\n\tLOCK_ENABLED_SOFTIRQ_READ = 7,\n\tLOCK_USED = 8,\n\tLOCK_USED_READ = 9,\n\tLOCK_USAGE_STATES = 10,\n};\n\nenum lockdep_lock_type {\n\tLD_LOCK_NORMAL = 0,\n\tLD_LOCK_PERCPU = 1,\n\tLD_LOCK_WAIT_OVERRIDE = 2,\n\tLD_LOCK_MAX = 3,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdep_wait_type {\n\tLD_WAIT_INV = 0,\n\tLD_WAIT_FREE = 1,\n\tLD_WAIT_SPIN = 2,\n\tLD_WAIT_CONFIG = 3,\n\tLD_WAIT_SLEEP = 4,\n\tLD_WAIT_MAX = 5,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lspcon_vendor {\n\tLSPCON_VENDOR_MCA = 0,\n\tLSPCON_VENDOR_PARADE = 1,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum maindmc_event_id {\n\tMAINDMC_EVENT_CMP_ZERO = 8,\n\tMAINDMC_EVENT_CMP_ODD = 9,\n\tMAINDMC_EVENT_CMP_NEG = 10,\n\tMAINDMC_EVENT_CMP_CARRY = 11,\n\tMAINDMC_EVENT_TMR0_DONE = 20,\n\tMAINDMC_EVENT_TMR1_DONE = 21,\n\tMAINDMC_EVENT_TMR2_DONE = 22,\n\tMAINDMC_EVENT_COUNT0_DONE = 23,\n\tMAINDMC_EVENT_COUNT1_DONE = 24,\n\tMAINDMC_EVENT_PERF_CNTR_DARBF = 25,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_A_TRIGGER = 34,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_B_TRIGGER = 35,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_C_TRIGGER = 36,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_D_TRIGGER = 37,\n\tMAINDMC_EVENT_1KHZ_FQ_A_TRIGGER = 38,\n\tMAINDMC_EVENT_1KHZ_FQ_B_TRIGGER = 39,\n\tMAINDMC_EVENT_1KHZ_FQ_C_TRIGGER = 40,\n\tMAINDMC_EVENT_1KHZ_FQ_D_TRIGGER = 41,\n\tMAINDMC_EVENT_SCANLINE_COMP_A = 42,\n\tMAINDMC_EVENT_SCANLINE_COMP_B = 43,\n\tMAINDMC_EVENT_SCANLINE_COMP_C = 44,\n\tMAINDMC_EVENT_SCANLINE_COMP_D = 45,\n\tMAINDMC_EVENT_VBLANK_DELAYED_A = 46,\n\tMAINDMC_EVENT_VBLANK_DELAYED_B = 47,\n\tMAINDMC_EVENT_VBLANK_DELAYED_C = 48,\n\tMAINDMC_EVENT_VBLANK_DELAYED_D = 49,\n\tMAINDMC_EVENT_VBLANK_A = 50,\n\tMAINDMC_EVENT_VBLANK_B = 51,\n\tMAINDMC_EVENT_VBLANK_C = 52,\n\tMAINDMC_EVENT_VBLANK_D = 53,\n\tMAINDMC_EVENT_HBLANK_A = 54,\n\tMAINDMC_EVENT_HBLANK_B = 55,\n\tMAINDMC_EVENT_HBLANK_C = 56,\n\tMAINDMC_EVENT_HBLANK_D = 57,\n\tMAINDMC_EVENT_VSYNC_A = 58,\n\tMAINDMC_EVENT_VSYNC_B = 59,\n\tMAINDMC_EVENT_VSYNC_C = 60,\n\tMAINDMC_EVENT_VSYNC_D = 61,\n\tMAINDMC_EVENT_SCANLINE_A = 62,\n\tMAINDMC_EVENT_SCANLINE_B = 63,\n\tMAINDMC_EVENT_SCANLINE_C = 64,\n\tMAINDMC_EVENT_SCANLINE_D = 65,\n\tMAINDMC_EVENT_PLANE1_FLIP_A = 66,\n\tMAINDMC_EVENT_PLANE2_FLIP_A = 67,\n\tMAINDMC_EVENT_PLANE3_FLIP_A = 68,\n\tMAINDMC_EVENT_PLANE4_FLIP_A = 69,\n\tMAINDMC_EVENT_PLANE5_FLIP_A = 70,\n\tMAINDMC_EVENT_PLANE6_FLIP_A = 71,\n\tMAINDMC_EVENT_PLANE7_FLIP_A = 72,\n\tMAINDMC_EVENT_PLANE1_FLIP_B = 73,\n\tMAINDMC_EVENT_PLANE2_FLIP_B = 74,\n\tMAINDMC_EVENT_PLANE3_FLIP_B = 75,\n\tMAINDMC_EVENT_PLANE4_FLIP_B = 76,\n\tMAINDMC_EVENT_PLANE5_FLIP_B = 77,\n\tMAINDMC_EVENT_PLANE6_FLIP_B = 78,\n\tMAINDMC_EVENT_PLANE7_FLIP_B = 79,\n\tMAINDMC_EVENT_PLANE1_FLIP_C = 80,\n\tMAINDMC_EVENT_PLANE2_FLIP_C = 81,\n\tMAINDMC_EVENT_PLANE3_FLIP_C = 82,\n\tMAINDMC_EVENT_PLANE4_FLIP_C = 83,\n\tMAINDMC_EVENT_PLANE5_FLIP_C = 84,\n\tMAINDMC_EVENT_PLANE6_FLIP_C = 85,\n\tMAINDMC_EVENT_PLANE7_FLIP_C = 86,\n\tMAINDMC_EVENT_PLANE1_FLIP_D = 87,\n\tMAINDMC_EVENT_PLANE2_FLIP_D = 88,\n\tMAINDMC_EVENT_PLANE3_FLIP_D = 89,\n\tMAINDMC_EVENT_PLANE4_FLIP_D = 90,\n\tMAINDMC_EVENT_PLANE5_FLIP_D = 91,\n\tMAINDMC_EVENT_PLANE6_FLIP_D = 92,\n\tMAINDMC_EVENT_PLANE7_FLIP_D = 93,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_A = 94,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_A = 95,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_A = 96,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_A = 97,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_A = 98,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_A = 99,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_A = 100,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_B = 101,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_B = 102,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_B = 103,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_B = 104,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_B = 105,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_B = 106,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_B = 107,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_C = 108,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_C = 109,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_C = 110,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_C = 111,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_C = 112,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_C = 113,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_C = 114,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_D = 115,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_D = 116,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_D = 117,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_D = 118,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_D = 119,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_D = 120,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_D = 121,\n\tMAINDMC_EVENT_WIDI_GTT_FAULT_SL1 = 125,\n\tMAINDMC_EVENT_WIDI_GTT_FAULT_SL2 = 126,\n\tMAINDMC_EVENT_WIDI_CAP_ACTIVE_SL1 = 127,\n\tMAINDMC_EVENT_WIDI_CAP_ACTIVE_SL2 = 128,\n\tMAINDMC_EVENT_RENUKE_A = 133,\n\tMAINDMC_EVENT_RENUKE_B = 134,\n\tMAINDMC_EVENT_RENUKE_C = 135,\n\tMAINDMC_EVENT_RENUKE_D = 136,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_A = 137,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_B = 138,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_C = 139,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_D = 140,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_A = 141,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_B = 142,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_C = 143,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_D = 144,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_A = 145,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_B = 146,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_C = 147,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_D = 148,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_A = 149,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_B = 150,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_C = 151,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_D = 152,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_A = 153,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_B = 154,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_C = 155,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_D = 156,\n\tMAINDMC_EVENT_DISP_PCH_INT = 157,\n\tMAINDMC_EVENT_GTT_ERR = 158,\n\tMAINDMC_EVENT_VTD_ERR = 159,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_A = 160,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_B = 161,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_C = 162,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_D = 163,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_A = 164,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_B = 165,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_C = 166,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_D = 167,\n\tMAINDMC_EVENT_DC_CLOCK_OFF_START_EDP = 178,\n\tMAINDMC_EVENT_DC_CLOCK_OFF_START_DSI = 179,\n\tMAINDMC_EVENT_DCPR_DMC_CSR_START = 180,\n\tMAINDMC_EVENT_IN_PSR = 181,\n\tMAINDMC_EVENT_IN_MEMUP = 183,\n\tMAINDMC_EVENT_IN_VGA = 184,\n\tMAINDMC_EVENT_IN_KVM_SESSION = 186,\n\tMAINDMC_EVENT_DEWAKE = 187,\n\tMAINDMC_EVENT_TRAP_HIT = 189,\n\tMAINDMC_EVENT_CLK_USEC = 190,\n\tMAINDMC_EVENT_CLK_MSEC = 191,\n\tMAINDMC_EVENT_CHICKEN1 = 200,\n\tMAINDMC_EVENT_CHICKEN2 = 201,\n\tMAINDMC_EVENT_CHICKEN3 = 202,\n\tMAINDMC_EVENT_DDT_UBP = 203,\n\tMAINDMC_EVENT_HP_LATENCY = 205,\n\tMAINDMC_EVENT_LP_LATENCY = 206,\n\tMAINDMC_EVENT_WIDI_LP_REQ_SL1 = 207,\n\tMAINDMC_EVENT_WIDI_LP_REQ_SL2 = 208,\n\tMAINDMC_EVENT_DG_DMC_EVT_0 = 211,\n\tMAINDMC_EVENT_DG_DMC_EVT_1 = 212,\n\tMAINDMC_EVENT_DG_DMC_EVT_2 = 213,\n\tMAINDMC_EVENT_DG_DMC_EVT_3 = 214,\n\tMAINDMC_EVENT_DG_DMC_EVT_4 = 215,\n\tMAINDMC_EVENT_DACFE_CLK_STOP = 216,\n\tMAINDMC_EVENT_DACFE_AZILIA_SDI_WAKE = 217,\n\tMAINDMC_EVENT_AUDIO_DOUBLE_FUNC_GRP_RST = 218,\n\tMAINDMC_EVENT_AUDIO_CMD_VALID = 219,\n\tMAINDMC_EVENT_AUDIO_FRM_SYNC_BCLK = 220,\n\tMAINDMC_EVENT_AUDIO_FRM_SYNC_CDCLK = 221,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_A = 222,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_B = 223,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_C = 224,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_E = 225,\n\tMAINDMC_EVENT_CMTG_SCANLINE_IN_GB_DC6v = 226,\n\tMAINDMC_EVENT_DCPR_CMTG_SCANLINE_OUTSIDE_GB = 227,\n\tMAINDMC_EVENT_DC6v_BACKWARD_COMPAT = 228,\n\tMAINDMC_EVENT_DPMA_PM_ABORT = 229,\n\tMAINDMC_EVENT_STACK_OVF = 252,\n\tMAINDMC_EVENT_NO_CLAIM = 253,\n\tMAINDMC_EVENT_UNK_CMD = 254,\n\tMAINDMC_EVENT_HTP_MOD = 255,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum mca_msr {\n\tMCA_CTL = 0,\n\tMCA_STATUS = 1,\n\tMCA_ADDR = 2,\n\tMCA_MISC = 3,\n};\n\nenum mce_notifier_prios {\n\tMCE_PRIO_LOWEST = 0,\n\tMCE_PRIO_MCELOG = 1,\n\tMCE_PRIO_EDAC = 2,\n\tMCE_PRIO_NFIT = 3,\n\tMCE_PRIO_EXTLOG = 4,\n\tMCE_PRIO_UC = 5,\n\tMCE_PRIO_EARLY = 6,\n\tMCE_PRIO_CEC = 7,\n\tMCE_PRIO_HIGHEST = 7,\n};\n\nenum mcp_flags {\n\tMCP_TIMESTAMP = 1,\n\tMCP_UC = 2,\n\tMCP_QUEUE_LOG = 4,\n};\n\nenum md_ro_state {\n\tMD_RDWR = 0,\n\tMD_RDONLY = 1,\n\tMD_AUTO_READ = 2,\n\tMD_MAX_STATE = 3,\n};\n\nenum md_submodule_id {\n\tID_LINEAR = -1,\n\tID_RAID0 = 0,\n\tID_RAID1 = 1,\n\tID_RAID4 = 4,\n\tID_RAID5 = 5,\n\tID_RAID6 = 6,\n\tID_RAID10 = 10,\n\tID_CLUSTER = 11,\n\tID_BITMAP = 12,\n\tID_LLBITMAP = 13,\n\tID_BITMAP_NONE = 14,\n};\n\nenum md_submodule_type {\n\tMD_PERSONALITY = 0,\n\tMD_CLUSTER = 1,\n\tMD_BITMAP = 2,\n};\n\nenum mddev_flags {\n\tMD_ARRAY_FIRST_USE = 0,\n\tMD_CLOSING = 1,\n\tMD_JOURNAL_CLEAN = 2,\n\tMD_HAS_JOURNAL = 3,\n\tMD_CLUSTER_RESYNC_LOCKED = 4,\n\tMD_FAILFAST_SUPPORTED = 5,\n\tMD_HAS_PPL = 6,\n\tMD_HAS_MULTIPLE_PPLS = 7,\n\tMD_NOT_READY = 8,\n\tMD_BROKEN = 9,\n\tMD_DO_DELETE = 10,\n\tMD_DELETED = 11,\n\tMD_HAS_SUPERBLOCK = 12,\n\tMD_FAILLAST_DEV = 13,\n\tMD_SERIALIZE_POLICY = 14,\n};\n\nenum mddev_sb_flags {\n\tMD_SB_CHANGE_DEVS = 0,\n\tMD_SB_CHANGE_CLEAN = 1,\n\tMD_SB_CHANGE_PENDING = 2,\n\tMD_SB_NEED_REWRITE = 3,\n};\n\nenum mdio_mutex_lock_class {\n\tMDIO_MUTEX_NORMAL = 0,\n\tMDIO_MUTEX_MUX = 1,\n\tMDIO_MUTEX_NESTED = 2,\n};\n\nenum mds_mitigations {\n\tMDS_MITIGATION_OFF = 0,\n\tMDS_MITIGATION_AUTO = 1,\n\tMDS_MITIGATION_FULL = 2,\n\tMDS_MITIGATION_VMWERV = 3,\n};\n\nenum mei_cb_file_ops {\n\tMEI_FOP_READ = 0,\n\tMEI_FOP_WRITE = 1,\n\tMEI_FOP_CONNECT = 2,\n\tMEI_FOP_DISCONNECT = 3,\n\tMEI_FOP_DISCONNECT_RSP = 4,\n\tMEI_FOP_NOTIFY_START = 5,\n\tMEI_FOP_NOTIFY_STOP = 6,\n\tMEI_FOP_DMA_MAP = 7,\n\tMEI_FOP_DMA_UNMAP = 8,\n};\n\nenum mei_cfg_idx {\n\tMEI_ME_UNDEF_CFG = 0,\n\tMEI_ME_ICH_CFG = 1,\n\tMEI_ME_ICH10_CFG = 2,\n\tMEI_ME_PCH6_CFG = 3,\n\tMEI_ME_PCH7_CFG = 4,\n\tMEI_ME_PCH_CPT_PBG_CFG = 5,\n\tMEI_ME_PCH8_CFG = 6,\n\tMEI_ME_PCH8_ITOUCH_CFG = 7,\n\tMEI_ME_PCH8_SPS_4_CFG = 8,\n\tMEI_ME_PCH12_CFG = 9,\n\tMEI_ME_PCH12_SPS_4_CFG = 10,\n\tMEI_ME_PCH12_SPS_CFG = 11,\n\tMEI_ME_PCH12_SPS_ITOUCH_CFG = 12,\n\tMEI_ME_PCH15_CFG = 13,\n\tMEI_ME_PCH15_SPS_CFG = 14,\n\tMEI_ME_GSC_CFG = 15,\n\tMEI_ME_GSCFI_CFG = 16,\n\tMEI_ME_NUM_CFG = 17,\n};\n\nenum mei_cl_connect_status {\n\tMEI_CL_CONN_SUCCESS = 0,\n\tMEI_CL_CONN_NOT_FOUND = 1,\n\tMEI_CL_CONN_ALREADY_STARTED = 2,\n\tMEI_CL_CONN_OUT_OF_RESOURCES = 3,\n\tMEI_CL_CONN_MESSAGE_SMALL = 4,\n\tMEI_CL_CONN_NOT_ALLOWED = 5,\n};\n\nenum mei_cl_disconnect_status {\n\tMEI_CL_DISCONN_SUCCESS = 0,\n};\n\nenum mei_cl_io_mode {\n\tMEI_CL_IO_TX_BLOCKING = 1,\n\tMEI_CL_IO_TX_INTERNAL = 2,\n\tMEI_CL_IO_RX_NONBLOCK = 4,\n\tMEI_CL_IO_SGL = 8,\n};\n\nenum mei_dev_pxp_mode {\n\tMEI_DEV_PXP_DEFAULT = 0,\n\tMEI_DEV_PXP_INIT = 1,\n\tMEI_DEV_PXP_SETUP = 2,\n\tMEI_DEV_PXP_READY = 3,\n};\n\nenum mei_dev_reset_to_pxp {\n\tMEI_DEV_RESET_TO_PXP_DEFAULT = 0,\n\tMEI_DEV_RESET_TO_PXP_PERFORMED = 1,\n\tMEI_DEV_RESET_TO_PXP_DONE = 2,\n};\n\nenum mei_dev_state {\n\tMEI_DEV_UNINITIALIZED = 0,\n\tMEI_DEV_INITIALIZING = 1,\n\tMEI_DEV_INIT_CLIENTS = 2,\n\tMEI_DEV_ENABLED = 3,\n\tMEI_DEV_RESETTING = 4,\n\tMEI_DEV_DISABLED = 5,\n\tMEI_DEV_POWERING_DOWN = 6,\n\tMEI_DEV_POWER_DOWN = 7,\n\tMEI_DEV_POWER_UP = 8,\n};\n\nenum mei_ext_hdr_type {\n\tMEI_EXT_HDR_NONE = 0,\n\tMEI_EXT_HDR_VTAG = 1,\n\tMEI_EXT_HDR_GSC = 2,\n};\n\nenum mei_file_transaction_states {\n\tMEI_IDLE = 0,\n\tMEI_WRITING = 1,\n\tMEI_WRITE_COMPLETE = 2,\n};\n\nenum mei_hbm_state {\n\tMEI_HBM_IDLE = 0,\n\tMEI_HBM_STARTING = 1,\n\tMEI_HBM_CAP_SETUP = 2,\n\tMEI_HBM_DR_SETUP = 3,\n\tMEI_HBM_ENUM_CLIENTS = 4,\n\tMEI_HBM_CLIENT_PROPERTIES = 5,\n\tMEI_HBM_STARTED = 6,\n\tMEI_HBM_STOPPED = 7,\n};\n\nenum mei_hbm_status {\n\tMEI_HBMS_SUCCESS = 0,\n\tMEI_HBMS_CLIENT_NOT_FOUND = 1,\n\tMEI_HBMS_ALREADY_EXISTS = 2,\n\tMEI_HBMS_REJECTED = 3,\n\tMEI_HBMS_INVALID_PARAMETER = 4,\n\tMEI_HBMS_NOT_ALLOWED = 5,\n\tMEI_HBMS_ALREADY_STARTED = 6,\n\tMEI_HBMS_NOT_STARTED = 7,\n\tMEI_HBMS_MAX = 8,\n};\n\nenum mei_pg_event {\n\tMEI_PG_EVENT_IDLE = 0,\n\tMEI_PG_EVENT_WAIT = 1,\n\tMEI_PG_EVENT_RECEIVED = 2,\n\tMEI_PG_EVENT_INTR_WAIT = 3,\n\tMEI_PG_EVENT_INTR_RECEIVED = 4,\n};\n\nenum mei_pg_state {\n\tMEI_PG_OFF = 0,\n\tMEI_PG_ON = 1,\n};\n\nenum mei_stop_reason_types {\n\tDRIVER_STOP_REQUEST = 0,\n\tDEVICE_D1_ENTRY = 1,\n\tDEVICE_D2_ENTRY = 2,\n\tDEVICE_D3_ENTRY = 3,\n\tSYSTEM_S1_ENTRY = 4,\n\tSYSTEM_S2_ENTRY = 5,\n\tSYSTEM_S3_ENTRY = 6,\n\tSYSTEM_S4_ENTRY = 7,\n\tSYSTEM_S5_ENTRY = 8,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 51,\n\tMEMCG_SOCK = 52,\n\tMEMCG_PERCPU_B = 53,\n\tMEMCG_VMALLOC = 54,\n\tMEMCG_KMEM = 55,\n\tMEMCG_ZSWAP_B = 56,\n\tMEMCG_ZSWAPPED = 57,\n\tMEMCG_NR_STAT = 58,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mf_flags {\n\tMF_COUNT_INCREASED = 1,\n\tMF_ACTION_REQUIRED = 2,\n\tMF_MUST_KILL = 4,\n\tMF_SOFT_OFFLINE = 8,\n\tMF_UNPOISON = 16,\n\tMF_SW_SIMULATED = 32,\n\tMF_NO_RETRY = 64,\n\tMF_MEM_PRE_REMOVE = 128,\n};\n\nenum mf_result {\n\tMF_IGNORED = 0,\n\tMF_FAILED = 1,\n\tMF_DELAYED = 2,\n\tMF_RECOVERED = 3,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migrate_vma_direction {\n\tMIGRATE_VMA_SELECT_SYSTEM = 1,\n\tMIGRATE_VMA_SELECT_DEVICE_PRIVATE = 2,\n\tMIGRATE_VMA_SELECT_DEVICE_COHERENT = 4,\n\tMIGRATE_VMA_SELECT_COMPOUND = 8,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\t__MIGRATE_TYPE_END = 3,\n\tMIGRATE_ISOLATE = 4,\n\tMIGRATE_TYPES = 5,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum mipi_dsi_compression_algo {\n\tMIPI_DSI_COMPRESSION_DSC = 0,\n\tMIPI_DSI_COMPRESSION_VENDOR = 3,\n};\n\nenum mipi_dsi_dcs_tear_mode {\n\tMIPI_DSI_DCS_TEAR_MODE_VBLANK = 0,\n\tMIPI_DSI_DCS_TEAR_MODE_VHBLANK = 1,\n};\n\nenum mipi_dsi_pixel_format {\n\tMIPI_DSI_FMT_RGB888 = 0,\n\tMIPI_DSI_FMT_RGB666 = 1,\n\tMIPI_DSI_FMT_RGB666_PACKED = 2,\n\tMIPI_DSI_FMT_RGB565 = 3,\n};\n\nenum mipi_seq {\n\tMIPI_SEQ_END = 0,\n\tMIPI_SEQ_DEASSERT_RESET = 1,\n\tMIPI_SEQ_INIT_OTP = 2,\n\tMIPI_SEQ_DISPLAY_ON = 3,\n\tMIPI_SEQ_DISPLAY_OFF = 4,\n\tMIPI_SEQ_ASSERT_RESET = 5,\n\tMIPI_SEQ_BACKLIGHT_ON = 6,\n\tMIPI_SEQ_BACKLIGHT_OFF = 7,\n\tMIPI_SEQ_TEAR_ON = 8,\n\tMIPI_SEQ_TEAR_OFF = 9,\n\tMIPI_SEQ_POWER_ON = 10,\n\tMIPI_SEQ_POWER_OFF = 11,\n\tMIPI_SEQ_MAX = 12,\n};\n\nenum mipi_seq_element {\n\tMIPI_SEQ_ELEM_END = 0,\n\tMIPI_SEQ_ELEM_SEND_PKT = 1,\n\tMIPI_SEQ_ELEM_DELAY = 2,\n\tMIPI_SEQ_ELEM_GPIO = 3,\n\tMIPI_SEQ_ELEM_I2C = 4,\n\tMIPI_SEQ_ELEM_SPI = 5,\n\tMIPI_SEQ_ELEM_PMIC = 6,\n\tMIPI_SEQ_ELEM_MAX = 7,\n};\n\nenum misc_res_type {\n\tMISC_CG_RES_TYPES = 0,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mmio_mitigations {\n\tMMIO_MITIGATION_OFF = 0,\n\tMMIO_MITIGATION_AUTO = 1,\n\tMMIO_MITIGATION_UCODE_NEEDED = 2,\n\tMMIO_MITIGATION_VERW = 3,\n};\n\nenum mmu_notifier_event {\n\tMMU_NOTIFY_UNMAP = 0,\n\tMMU_NOTIFY_CLEAR = 1,\n\tMMU_NOTIFY_PROTECTION_VMA = 2,\n\tMMU_NOTIFY_PROTECTION_PAGE = 3,\n\tMMU_NOTIFY_SOFT_DIRTY = 4,\n\tMMU_NOTIFY_RELEASE = 5,\n\tMMU_NOTIFY_MIGRATE = 6,\n\tMMU_NOTIFY_EXCLUSIVE = 7,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mp_irq_source_types {\n\tmp_INT = 0,\n\tmp_NMI = 1,\n\tmp_SMI = 2,\n\tmp_ExtINT = 3,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum nested_evmptrld_status {\n\tEVMPTRLD_DISABLED = 0,\n\tEVMPTRLD_SUCCEEDED = 1,\n\tEVMPTRLD_VMFAIL = 2,\n\tEVMPTRLD_ERROR = 3,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum net_xmit_qdisc_t {\n\t__NET_XMIT_STOLEN = 65536,\n\t__NET_XMIT_BYPASS = 131072,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_lag_hash {\n\tNETDEV_LAG_HASH_NONE = 0,\n\tNETDEV_LAG_HASH_L2 = 1,\n\tNETDEV_LAG_HASH_L34 = 2,\n\tNETDEV_LAG_HASH_L23 = 3,\n\tNETDEV_LAG_HASH_E23 = 4,\n\tNETDEV_LAG_HASH_E34 = 5,\n\tNETDEV_LAG_HASH_VLAN_SRCMAC = 6,\n\tNETDEV_LAG_HASH_UNKNOWN = 7,\n};\n\nenum netdev_lag_tx_type {\n\tNETDEV_LAG_TX_TYPE_UNKNOWN = 0,\n\tNETDEV_LAG_TX_TYPE_RANDOM = 1,\n\tNETDEV_LAG_TX_TYPE_BROADCAST = 2,\n\tNETDEV_LAG_TX_TYPE_ROUNDROBIN = 3,\n\tNETDEV_LAG_TX_TYPE_ACTIVEBACKUP = 4,\n\tNETDEV_LAG_TX_TYPE_HASH = 5,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netfs_collect_contig_trace {\n\tnetfs_contig_trace_collect = 0,\n\tnetfs_contig_trace_jump = 1,\n\tnetfs_contig_trace_unlock = 2,\n} __attribute__((mode(byte)));\n\nenum netfs_donate_trace {\n\tnetfs_trace_donate_tail_to_prev = 0,\n\tnetfs_trace_donate_to_prev = 1,\n\tnetfs_trace_donate_to_next = 2,\n\tnetfs_trace_donate_to_deferred_next = 3,\n} __attribute__((mode(byte)));\n\nenum netfs_failure {\n\tnetfs_fail_check_write_begin = 0,\n\tnetfs_fail_copy_to_cache = 1,\n\tnetfs_fail_dio_read_short = 2,\n\tnetfs_fail_dio_read_zero = 3,\n\tnetfs_fail_read = 4,\n\tnetfs_fail_short_read = 5,\n\tnetfs_fail_prepare_write = 6,\n\tnetfs_fail_write = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_folio_trace {\n\tnetfs_folio_is_uptodate = 0,\n\tnetfs_just_prefetch = 1,\n\tnetfs_whole_folio_modify = 2,\n\tnetfs_modify_and_clear = 3,\n\tnetfs_streaming_write = 4,\n\tnetfs_streaming_write_cont = 5,\n\tnetfs_flush_content = 6,\n\tnetfs_streaming_filled_page = 7,\n\tnetfs_streaming_cont_filled_page = 8,\n\tnetfs_folio_trace_abandon = 9,\n\tnetfs_folio_trace_alloc_buffer = 10,\n\tnetfs_folio_trace_cancel_copy = 11,\n\tnetfs_folio_trace_cancel_store = 12,\n\tnetfs_folio_trace_clear = 13,\n\tnetfs_folio_trace_clear_cc = 14,\n\tnetfs_folio_trace_clear_g = 15,\n\tnetfs_folio_trace_clear_s = 16,\n\tnetfs_folio_trace_copy_to_cache = 17,\n\tnetfs_folio_trace_end_copy = 18,\n\tnetfs_folio_trace_filled_gaps = 19,\n\tnetfs_folio_trace_kill = 20,\n\tnetfs_folio_trace_kill_cc = 21,\n\tnetfs_folio_trace_kill_g = 22,\n\tnetfs_folio_trace_kill_s = 23,\n\tnetfs_folio_trace_mkwrite = 24,\n\tnetfs_folio_trace_mkwrite_plus = 25,\n\tnetfs_folio_trace_not_under_wback = 26,\n\tnetfs_folio_trace_not_locked = 27,\n\tnetfs_folio_trace_put = 28,\n\tnetfs_folio_trace_read = 29,\n\tnetfs_folio_trace_read_done = 30,\n\tnetfs_folio_trace_read_gaps = 31,\n\tnetfs_folio_trace_read_unlock = 32,\n\tnetfs_folio_trace_redirtied = 33,\n\tnetfs_folio_trace_store = 34,\n\tnetfs_folio_trace_store_copy = 35,\n\tnetfs_folio_trace_store_plus = 36,\n\tnetfs_folio_trace_wthru = 37,\n\tnetfs_folio_trace_wthru_plus = 38,\n} __attribute__((mode(byte)));\n\nenum netfs_folioq_trace {\n\tnetfs_trace_folioq_alloc_buffer = 0,\n\tnetfs_trace_folioq_clear = 1,\n\tnetfs_trace_folioq_delete = 2,\n\tnetfs_trace_folioq_make_space = 3,\n\tnetfs_trace_folioq_rollbuf_init = 4,\n\tnetfs_trace_folioq_read_progress = 5,\n} __attribute__((mode(byte)));\n\nenum netfs_io_origin {\n\tNETFS_READAHEAD = 0,\n\tNETFS_READPAGE = 1,\n\tNETFS_READ_GAPS = 2,\n\tNETFS_READ_SINGLE = 3,\n\tNETFS_READ_FOR_WRITE = 4,\n\tNETFS_UNBUFFERED_READ = 5,\n\tNETFS_DIO_READ = 6,\n\tNETFS_WRITEBACK = 7,\n\tNETFS_WRITEBACK_SINGLE = 8,\n\tNETFS_WRITETHROUGH = 9,\n\tNETFS_UNBUFFERED_WRITE = 10,\n\tNETFS_DIO_WRITE = 11,\n\tNETFS_PGPRIV2_COPY_TO_CACHE = 12,\n\tnr__netfs_io_origin = 13,\n} __attribute__((mode(byte)));\n\nenum netfs_io_source {\n\tNETFS_SOURCE_UNKNOWN = 0,\n\tNETFS_FILL_WITH_ZEROES = 1,\n\tNETFS_DOWNLOAD_FROM_SERVER = 2,\n\tNETFS_READ_FROM_CACHE = 3,\n\tNETFS_INVALID_READ = 4,\n\tNETFS_UPLOAD_TO_SERVER = 5,\n\tNETFS_WRITE_TO_CACHE = 6,\n} __attribute__((mode(byte)));\n\nenum netfs_read_from_hole {\n\tNETFS_READ_HOLE_IGNORE = 0,\n\tNETFS_READ_HOLE_FAIL = 1,\n};\n\nenum netfs_read_trace {\n\tnetfs_read_trace_dio_read = 0,\n\tnetfs_read_trace_expanded = 1,\n\tnetfs_read_trace_readahead = 2,\n\tnetfs_read_trace_readpage = 3,\n\tnetfs_read_trace_read_gaps = 4,\n\tnetfs_read_trace_read_single = 5,\n\tnetfs_read_trace_prefetch_for_write = 6,\n\tnetfs_read_trace_write_begin = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_ref_trace {\n\tnetfs_rreq_trace_get_for_outstanding = 0,\n\tnetfs_rreq_trace_get_subreq = 1,\n\tnetfs_rreq_trace_put_complete = 2,\n\tnetfs_rreq_trace_put_discard = 3,\n\tnetfs_rreq_trace_put_failed = 4,\n\tnetfs_rreq_trace_put_no_submit = 5,\n\tnetfs_rreq_trace_put_return = 6,\n\tnetfs_rreq_trace_put_subreq = 7,\n\tnetfs_rreq_trace_put_work_ip = 8,\n\tnetfs_rreq_trace_see_work = 9,\n\tnetfs_rreq_trace_see_work_complete = 10,\n\tnetfs_rreq_trace_new = 11,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_trace {\n\tnetfs_rreq_trace_assess = 0,\n\tnetfs_rreq_trace_collect = 1,\n\tnetfs_rreq_trace_complete = 2,\n\tnetfs_rreq_trace_copy = 3,\n\tnetfs_rreq_trace_dirty = 4,\n\tnetfs_rreq_trace_done = 5,\n\tnetfs_rreq_trace_end_copy_to_cache = 6,\n\tnetfs_rreq_trace_free = 7,\n\tnetfs_rreq_trace_intr = 8,\n\tnetfs_rreq_trace_ki_complete = 9,\n\tnetfs_rreq_trace_recollect = 10,\n\tnetfs_rreq_trace_redirty = 11,\n\tnetfs_rreq_trace_resubmit = 12,\n\tnetfs_rreq_trace_set_abandon = 13,\n\tnetfs_rreq_trace_set_pause = 14,\n\tnetfs_rreq_trace_unlock = 15,\n\tnetfs_rreq_trace_unlock_pgpriv2 = 16,\n\tnetfs_rreq_trace_unmark = 17,\n\tnetfs_rreq_trace_unpause = 18,\n\tnetfs_rreq_trace_wait_ip = 19,\n\tnetfs_rreq_trace_wait_pause = 20,\n\tnetfs_rreq_trace_wait_quiesce = 21,\n\tnetfs_rreq_trace_waited_ip = 22,\n\tnetfs_rreq_trace_waited_pause = 23,\n\tnetfs_rreq_trace_waited_quiesce = 24,\n\tnetfs_rreq_trace_wake_ip = 25,\n\tnetfs_rreq_trace_wake_queue = 26,\n\tnetfs_rreq_trace_write_done = 27,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_ref_trace {\n\tnetfs_sreq_trace_get_copy_to_cache = 0,\n\tnetfs_sreq_trace_get_resubmit = 1,\n\tnetfs_sreq_trace_get_submit = 2,\n\tnetfs_sreq_trace_get_short_read = 3,\n\tnetfs_sreq_trace_new = 4,\n\tnetfs_sreq_trace_put_abandon = 5,\n\tnetfs_sreq_trace_put_cancel = 6,\n\tnetfs_sreq_trace_put_clear = 7,\n\tnetfs_sreq_trace_put_consumed = 8,\n\tnetfs_sreq_trace_put_done = 9,\n\tnetfs_sreq_trace_put_failed = 10,\n\tnetfs_sreq_trace_put_merged = 11,\n\tnetfs_sreq_trace_put_no_copy = 12,\n\tnetfs_sreq_trace_put_oom = 13,\n\tnetfs_sreq_trace_put_wip = 14,\n\tnetfs_sreq_trace_put_work = 15,\n\tnetfs_sreq_trace_put_terminated = 16,\n\tnetfs_sreq_trace_see_failed = 17,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_trace {\n\tnetfs_sreq_trace_abandoned = 0,\n\tnetfs_sreq_trace_add_donations = 1,\n\tnetfs_sreq_trace_added = 2,\n\tnetfs_sreq_trace_cache_nowrite = 3,\n\tnetfs_sreq_trace_cache_prepare = 4,\n\tnetfs_sreq_trace_cache_write = 5,\n\tnetfs_sreq_trace_cancel = 6,\n\tnetfs_sreq_trace_clear = 7,\n\tnetfs_sreq_trace_consumed = 8,\n\tnetfs_sreq_trace_discard = 9,\n\tnetfs_sreq_trace_donate_to_prev = 10,\n\tnetfs_sreq_trace_donate_to_next = 11,\n\tnetfs_sreq_trace_download_instead = 12,\n\tnetfs_sreq_trace_fail = 13,\n\tnetfs_sreq_trace_free = 14,\n\tnetfs_sreq_trace_hit_eof = 15,\n\tnetfs_sreq_trace_io_bad = 16,\n\tnetfs_sreq_trace_io_malformed = 17,\n\tnetfs_sreq_trace_io_unknown = 18,\n\tnetfs_sreq_trace_io_progress = 19,\n\tnetfs_sreq_trace_io_req_submitted = 20,\n\tnetfs_sreq_trace_io_retry_needed = 21,\n\tnetfs_sreq_trace_limited = 22,\n\tnetfs_sreq_trace_need_clear = 23,\n\tnetfs_sreq_trace_partial_read = 24,\n\tnetfs_sreq_trace_need_retry = 25,\n\tnetfs_sreq_trace_prepare = 26,\n\tnetfs_sreq_trace_prep_failed = 27,\n\tnetfs_sreq_trace_progress = 28,\n\tnetfs_sreq_trace_reprep_failed = 29,\n\tnetfs_sreq_trace_retry = 30,\n\tnetfs_sreq_trace_short = 31,\n\tnetfs_sreq_trace_split = 32,\n\tnetfs_sreq_trace_submit = 33,\n\tnetfs_sreq_trace_superfluous = 34,\n\tnetfs_sreq_trace_terminated = 35,\n\tnetfs_sreq_trace_wait_for = 36,\n\tnetfs_sreq_trace_write = 37,\n\tnetfs_sreq_trace_write_skip = 38,\n\tnetfs_sreq_trace_write_term = 39,\n} __attribute__((mode(byte)));\n\nenum netfs_write_trace {\n\tnetfs_write_trace_copy_to_cache = 0,\n\tnetfs_write_trace_dio_write = 1,\n\tnetfs_write_trace_unbuffered_write = 2,\n\tnetfs_write_trace_writeback = 3,\n\tnetfs_write_trace_writeback_single = 4,\n\tnetfs_write_trace_writethrough = 5,\n} __attribute__((mode(byte)));\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nhlt_device_type {\n\tNHLT_DEVICE_BT = 0,\n\tNHLT_DEVICE_DMIC = 1,\n\tNHLT_DEVICE_I2S = 4,\n\tNHLT_DEVICE_INVALID = 5,\n};\n\nenum nhlt_link_type {\n\tNHLT_LINK_HDA = 0,\n\tNHLT_LINK_DSP = 1,\n\tNHLT_LINK_DMIC = 2,\n\tNHLT_LINK_SSP = 3,\n\tNHLT_LINK_INVALID = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum nmi_states {\n\tNMI_NOT_RUNNING = 0,\n\tNMI_EXECUTING = 1,\n\tNMI_LATCHED = 2,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_IOMMU_PAGES = 39,\n\tNR_SWAPCACHE = 40,\n\tPGPROMOTE_SUCCESS = 41,\n\tPGPROMOTE_CANDIDATE = 42,\n\tPGPROMOTE_CANDIDATE_NRL = 43,\n\tPGDEMOTE_KSWAPD = 44,\n\tPGDEMOTE_DIRECT = 45,\n\tPGDEMOTE_KHUGEPAGED = 46,\n\tPGDEMOTE_PROACTIVE = 47,\n\tNR_HUGETLB = 48,\n\tNR_BALLOON_PAGES = 49,\n\tNR_KERNEL_FILE_PAGES = 50,\n\tNR_VM_NODE_STAT_ITEMS = 51,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 2,\n\tN_MEMORY = 3,\n\tN_CPU = 4,\n\tN_GENERIC_INITIATOR = 5,\n\tNR_NODE_STATES = 6,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum numa_faults_stats {\n\tNUMA_MEM = 0,\n\tNUMA_CPU = 1,\n\tNUMA_MEMBUF = 2,\n\tNUMA_CPUBUF = 3,\n};\n\nenum numa_stat_item {\n\tNUMA_HIT = 0,\n\tNUMA_MISS = 1,\n\tNUMA_FOREIGN = 2,\n\tNUMA_INTERLEAVE_HIT = 3,\n\tNUMA_LOCAL = 4,\n\tNUMA_OTHER = 5,\n\tNR_VM_NUMA_EVENT_ITEMS = 6,\n};\n\nenum numa_topology_type {\n\tNUMA_DIRECT = 0,\n\tNUMA_GLUELESS_MESH = 1,\n\tNUMA_BACKPLANE = 2,\n};\n\nenum numa_type {\n\tnode_has_spare = 0,\n\tnode_fully_busy = 1,\n\tnode_overloaded = 2,\n};\n\nenum numa_vmaskip_reason {\n\tNUMAB_SKIP_UNSUITABLE = 0,\n\tNUMAB_SKIP_SHARED_RO = 1,\n\tNUMAB_SKIP_INACCESSIBLE = 2,\n\tNUMAB_SKIP_SCAN_DELAY = 3,\n\tNUMAB_SKIP_PID_INACTIVE = 4,\n\tNUMAB_SKIP_IGNORE_PID = 5,\n\tNUMAB_SKIP_SEQ_COMPLETED = 6,\n};\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n\tNVMEM_TYPE_FRAM = 4,\n};\n\nenum nvmx_vmentry_status {\n\tNVMX_VMENTRY_SUCCESS = 0,\n\tNVMX_VMENTRY_VMFAIL = 1,\n\tNVMX_VMENTRY_VMEXIT = 2,\n\tNVMX_VMENTRY_KVM_INTERNAL_ERROR = 3,\n};\n\nenum oa_type {\n\tTYPE_OAG = 0,\n\tTYPE_OAM = 1,\n};\n\nenum oatc14_hdd_status {\n\tOATC14_HDD_STATUS_CABLE_OK = 0,\n\tOATC14_HDD_STATUS_OPEN = 1,\n\tOATC14_HDD_STATUS_SHORT = 2,\n\tOATC14_HDD_STATUS_NOT_DETECTABLE = 3,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum operation_mode {\n\tDP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0,\n\tDP_AS_SDP_AVT_FIXED_VTOTAL = 1,\n\tDP_AS_SDP_FAVT_TRR_NOT_REACHED = 2,\n\tDP_AS_SDP_FAVT_TRR_REACHED = 3,\n};\n\nenum ovl_copyop {\n\tOVL_COPY = 0,\n\tOVL_CLONE = 1,\n\tOVL_DEDUPE = 2,\n};\n\nenum ovl_entry_flag {\n\tOVL_E_UPPER_ALIAS = 0,\n\tOVL_E_OPAQUE = 1,\n\tOVL_E_CONNECTED = 2,\n\tOVL_E_XWHITEOUTS = 3,\n};\n\nenum ovl_inode_flag {\n\tOVL_IMPURE = 0,\n\tOVL_WHITEOUTS = 1,\n\tOVL_INDEX = 2,\n\tOVL_UPPERDATA = 3,\n\tOVL_CONST_INO = 4,\n\tOVL_HAS_DIGEST = 5,\n\tOVL_VERIFIED_DIGEST = 6,\n};\n\nenum ovl_opt {\n\tOpt_lowerdir = 0,\n\tOpt_lowerdir_add = 1,\n\tOpt_datadir_add = 2,\n\tOpt_upperdir = 3,\n\tOpt_workdir = 4,\n\tOpt_default_permissions = 5,\n\tOpt_redirect_dir = 6,\n\tOpt_index = 7,\n\tOpt_uuid = 8,\n\tOpt_nfs_export = 9,\n\tOpt_userxattr = 10,\n\tOpt_xino = 11,\n\tOpt_metacopy = 12,\n\tOpt_verity = 13,\n\tOpt_volatile = 14,\n\tOpt_override_creds = 15,\n};\n\nenum ovl_path_type {\n\t__OVL_PATH_UPPER = 1,\n\t__OVL_PATH_MERGE = 2,\n\t__OVL_PATH_ORIGIN = 4,\n};\n\nenum ovl_xattr {\n\tOVL_XATTR_OPAQUE = 0,\n\tOVL_XATTR_REDIRECT = 1,\n\tOVL_XATTR_ORIGIN = 2,\n\tOVL_XATTR_IMPURE = 3,\n\tOVL_XATTR_NLINK = 4,\n\tOVL_XATTR_UPPER = 5,\n\tOVL_XATTR_UUID = 6,\n\tOVL_XATTR_METACOPY = 7,\n\tOVL_XATTR_PROTATTR = 8,\n\tOVL_XATTR_XWHITEOUT = 9,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum p9_cache_bits {\n\tCACHE_NONE = 0,\n\tCACHE_FILE = 1,\n\tCACHE_META = 2,\n\tCACHE_WRITEBACK = 4,\n\tCACHE_LOOSE = 8,\n\tCACHE_FSCACHE = 128,\n};\n\nenum p9_cache_shortcuts {\n\tCACHE_SC_NONE = 0,\n\tCACHE_SC_READAHEAD = 1,\n\tCACHE_SC_MMAP = 5,\n\tCACHE_SC_LOOSE = 15,\n\tCACHE_SC_FSCACHE = 143,\n};\n\nenum p9_fid_reftype {\n\tP9_FID_REF_CREATE = 0,\n\tP9_FID_REF_GET = 1,\n\tP9_FID_REF_PUT = 2,\n\tP9_FID_REF_DESTROY = 3,\n} __attribute__((mode(byte)));\n\nenum p9_msg_t {\n\tP9_TLERROR = 6,\n\tP9_RLERROR = 7,\n\tP9_TSTATFS = 8,\n\tP9_RSTATFS = 9,\n\tP9_TLOPEN = 12,\n\tP9_RLOPEN = 13,\n\tP9_TLCREATE = 14,\n\tP9_RLCREATE = 15,\n\tP9_TSYMLINK = 16,\n\tP9_RSYMLINK = 17,\n\tP9_TMKNOD = 18,\n\tP9_RMKNOD = 19,\n\tP9_TRENAME = 20,\n\tP9_RRENAME = 21,\n\tP9_TREADLINK = 22,\n\tP9_RREADLINK = 23,\n\tP9_TGETATTR = 24,\n\tP9_RGETATTR = 25,\n\tP9_TSETATTR = 26,\n\tP9_RSETATTR = 27,\n\tP9_TXATTRWALK = 30,\n\tP9_RXATTRWALK = 31,\n\tP9_TXATTRCREATE = 32,\n\tP9_RXATTRCREATE = 33,\n\tP9_TREADDIR = 40,\n\tP9_RREADDIR = 41,\n\tP9_TFSYNC = 50,\n\tP9_RFSYNC = 51,\n\tP9_TLOCK = 52,\n\tP9_RLOCK = 53,\n\tP9_TGETLOCK = 54,\n\tP9_RGETLOCK = 55,\n\tP9_TLINK = 70,\n\tP9_RLINK = 71,\n\tP9_TMKDIR = 72,\n\tP9_RMKDIR = 73,\n\tP9_TRENAMEAT = 74,\n\tP9_RRENAMEAT = 75,\n\tP9_TUNLINKAT = 76,\n\tP9_RUNLINKAT = 77,\n\tP9_TVERSION = 100,\n\tP9_RVERSION = 101,\n\tP9_TAUTH = 102,\n\tP9_RAUTH = 103,\n\tP9_TATTACH = 104,\n\tP9_RATTACH = 105,\n\tP9_TERROR = 106,\n\tP9_RERROR = 107,\n\tP9_TFLUSH = 108,\n\tP9_RFLUSH = 109,\n\tP9_TWALK = 110,\n\tP9_RWALK = 111,\n\tP9_TOPEN = 112,\n\tP9_ROPEN = 113,\n\tP9_TCREATE = 114,\n\tP9_RCREATE = 115,\n\tP9_TREAD = 116,\n\tP9_RREAD = 117,\n\tP9_TWRITE = 118,\n\tP9_RWRITE = 119,\n\tP9_TCLUNK = 120,\n\tP9_RCLUNK = 121,\n\tP9_TREMOVE = 122,\n\tP9_RREMOVE = 123,\n\tP9_TSTAT = 124,\n\tP9_RSTAT = 125,\n\tP9_TWSTAT = 126,\n\tP9_RWSTAT = 127,\n};\n\nenum p9_open_mode_t {\n\tP9_OREAD = 0,\n\tP9_OWRITE = 1,\n\tP9_ORDWR = 2,\n\tP9_OEXEC = 3,\n\tP9_OTRUNC = 16,\n\tP9_OREXEC = 32,\n\tP9_ORCLOSE = 64,\n\tP9_OAPPEND = 128,\n\tP9_OEXCL = 4096,\n\tP9L_MODE_MASK = 8191,\n\tP9L_DIRECT = 8192,\n\tP9L_NOWRITECACHE = 16384,\n\tP9L_LOOSE = 32768,\n};\n\nenum p9_perm_t {\n\tP9_DMDIR = 2147483648,\n\tP9_DMAPPEND = 1073741824,\n\tP9_DMEXCL = 536870912,\n\tP9_DMMOUNT = 268435456,\n\tP9_DMAUTH = 134217728,\n\tP9_DMTMP = 67108864,\n\tP9_DMSYMLINK = 33554432,\n\tP9_DMLINK = 16777216,\n\tP9_DMDEVICE = 8388608,\n\tP9_DMNAMEDPIPE = 2097152,\n\tP9_DMSOCKET = 1048576,\n\tP9_DMSETUID = 524288,\n\tP9_DMSETGID = 262144,\n\tP9_DMSETVTX = 65536,\n};\n\nenum p9_proto_versions {\n\tp9_proto_legacy = 0,\n\tp9_proto_2000u = 1,\n\tp9_proto_2000L = 2,\n};\n\nenum p9_req_status_t {\n\tREQ_STATUS_ALLOC = 0,\n\tREQ_STATUS_UNSENT = 1,\n\tREQ_STATUS_SENT = 2,\n\tREQ_STATUS_RCVD = 3,\n\tREQ_STATUS_FLSHD = 4,\n\tREQ_STATUS_ERROR = 5,\n};\n\nenum p9_session_flags {\n\tV9FS_PROTO_2000U = 1,\n\tV9FS_PROTO_2000L = 2,\n\tV9FS_ACCESS_SINGLE = 4,\n\tV9FS_ACCESS_USER = 8,\n\tV9FS_ACCESS_CLIENT = 16,\n\tV9FS_POSIX_ACL = 32,\n\tV9FS_NO_XATTR = 64,\n\tV9FS_IGNORE_QV = 128,\n\tV9FS_DIRECT_IO = 256,\n\tV9FS_SYNC = 512,\n};\n\nenum p9_trans_status {\n\tConnected = 0,\n\tBeginDisconnect = 1,\n\tDisconnected = 2,\n\tHung = 3,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum page_cache_mode {\n\t_PAGE_CACHE_MODE_WB = 0,\n\t_PAGE_CACHE_MODE_WC = 1,\n\t_PAGE_CACHE_MODE_UC_MINUS = 2,\n\t_PAGE_CACHE_MODE_UC = 3,\n\t_PAGE_CACHE_MODE_WT = 4,\n\t_PAGE_CACHE_MODE_WP = 5,\n\t_PAGE_CACHE_MODE_NUM = 8,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 4096,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\tPB_migrate_isolate = 4,\n\t__NR_PAGEBLOCK_BITS = 5,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\tPG_arch_2 = 21,\n\t__NR_PAGEFLAGS = 22,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_vmemmap_self_hosted = 10,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum panel_type {\n\tPANEL_TYPE_OPREGION = 0,\n\tPANEL_TYPE_VBT = 1,\n\tPANEL_TYPE_PNPID = 2,\n\tPANEL_TYPE_FALLBACK = 3,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum pb_isolate_mode {\n\tPB_ISOLATE_MODE_MEM_OFFLINE = 0,\n\tPB_ISOLATE_MODE_CMA_ALLOC = 1,\n\tPB_ISOLATE_MODE_OTHER = 2,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_bf_sort_state {\n\tpci_bf_sort_default = 0,\n\tpci_force_nobf = 1,\n\tpci_force_bf = 2,\n\tpci_dmi_bf = 3,\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_15625000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_oxsemi = 71,\n\tpbn_oxsemi_1_15625000 = 72,\n\tpbn_oxsemi_2_15625000 = 73,\n\tpbn_oxsemi_4_15625000 = 74,\n\tpbn_oxsemi_8_15625000 = 75,\n\tpbn_intel_i960 = 76,\n\tpbn_sgi_ioc3 = 77,\n\tpbn_computone_4 = 78,\n\tpbn_computone_6 = 79,\n\tpbn_computone_8 = 80,\n\tpbn_sbsxrsio = 81,\n\tpbn_pasemi_1682M = 82,\n\tpbn_ni8430_2 = 83,\n\tpbn_ni8430_4 = 84,\n\tpbn_ni8430_8 = 85,\n\tpbn_ni8430_16 = 86,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 87,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 90,\n\tpbn_ce4100_1_115200 = 91,\n\tpbn_omegapci = 92,\n\tpbn_NETMOS9900_2s_115200 = 93,\n\tpbn_brcm_trumanage = 94,\n\tpbn_fintek_4 = 95,\n\tpbn_fintek_8 = 96,\n\tpbn_fintek_12 = 97,\n\tpbn_fintek_F81504A = 98,\n\tpbn_fintek_F81508A = 99,\n\tpbn_fintek_F81512A = 100,\n\tpbn_wch382_2 = 101,\n\tpbn_wch384_4 = 102,\n\tpbn_wch384_8 = 103,\n\tpbn_sunix_pci_1s = 104,\n\tpbn_sunix_pci_2s = 105,\n\tpbn_sunix_pci_4s = 106,\n\tpbn_sunix_pci_8s = 107,\n\tpbn_sunix_pci_16s = 108,\n\tpbn_titan_1_4000000 = 109,\n\tpbn_titan_2_4000000 = 110,\n\tpbn_titan_4_4000000 = 111,\n\tpbn_titan_8_4000000 = 112,\n\tpbn_moxa_2 = 113,\n\tpbn_moxa_4 = 114,\n\tpbn_moxa_8 = 115,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_hotplug_event {\n\tPCI_HOTPLUG_LINK_UP = 0,\n\tPCI_HOTPLUG_LINK_DOWN = 1,\n\tPCI_HOTPLUG_CARD_PRESENT = 2,\n\tPCI_HOTPLUG_CARD_NOT_PRESENT = 3,\n};\n\nenum pci_irq_reroute_variant {\n\tINTEL_IRQ_REROUTE_VARIANT = 1,\n\tMAX_IRQ_REROUTE_VARIANTS = 3,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum pedit_cmd {\n\tTCA_PEDIT_KEY_EX_CMD_SET = 0,\n\tTCA_PEDIT_KEY_EX_CMD_ADD = 1,\n\t__PEDIT_CMD_MAX = 2,\n};\n\nenum pedit_header_type {\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK = 0,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_ETH = 1,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP4 = 2,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP6 = 3,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_TCP = 4,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_UDP = 5,\n\t__PEDIT_HDR_TYPE_MAX = 6,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nenum perf_adl_uncore_imc_freerunning_types {\n\tADL_MMIO_UNCORE_IMC_DATA_TOTAL = 0,\n\tADL_MMIO_UNCORE_IMC_DATA_READ = 1,\n\tADL_MMIO_UNCORE_IMC_DATA_WRITE = 2,\n\tADL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE = 262144,\n\tPERF_SAMPLE_BRANCH_COUNTERS = 524288,\n\tPERF_SAMPLE_BRANCH_MAX = 1048576,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 18446744073709551584ULL,\n\tPERF_CONTEXT_KERNEL = 18446744073709551488ULL,\n\tPERF_CONTEXT_USER = 18446744073709551104ULL,\n\tPERF_CONTEXT_USER_DEFERRED = 18446744073709550976ULL,\n\tPERF_CONTEXT_GUEST = 18446744073709549568ULL,\n\tPERF_CONTEXT_GUEST_KERNEL = 18446744073709549440ULL,\n\tPERF_CONTEXT_GUEST_USER = 18446744073709549056ULL,\n\tPERF_CONTEXT_MAX = 18446744073709547521ULL,\n};\n\nenum perf_cstate_core_events {\n\tPERF_CSTATE_CORE_C1_RES = 0,\n\tPERF_CSTATE_CORE_C3_RES = 1,\n\tPERF_CSTATE_CORE_C6_RES = 2,\n\tPERF_CSTATE_CORE_C7_RES = 3,\n\tPERF_CSTATE_CORE_EVENT_MAX = 4,\n};\n\nenum perf_cstate_module_events {\n\tPERF_CSTATE_MODULE_C6_RES = 0,\n\tPERF_CSTATE_MODULE_EVENT_MAX = 1,\n};\n\nenum perf_cstate_pkg_events {\n\tPERF_CSTATE_PKG_C2_RES = 0,\n\tPERF_CSTATE_PKG_C3_RES = 1,\n\tPERF_CSTATE_PKG_C6_RES = 2,\n\tPERF_CSTATE_PKG_C7_RES = 3,\n\tPERF_CSTATE_PKG_C8_RES = 4,\n\tPERF_CSTATE_PKG_C9_RES = 5,\n\tPERF_CSTATE_PKG_C10_RES = 6,\n\tPERF_CSTATE_PKG_EVENT_MAX = 7,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_LOST = 16,\n\tPERF_FORMAT_MAX = 32,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_DATA_PAGE_SIZE = 4194304,\n\tPERF_SAMPLE_CODE_PAGE_SIZE = 8388608,\n\tPERF_SAMPLE_WEIGHT_STRUCT = 16777216,\n\tPERF_SAMPLE_MAX = 33554432,\n};\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = -5,\n\tPERF_EVENT_STATE_REVOKED = -4,\n\tPERF_EVENT_STATE_EXIT = -3,\n\tPERF_EVENT_STATE_ERROR = -2,\n\tPERF_EVENT_STATE_OFF = -1,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = -1,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_TEXT_POKE = 20,\n\tPERF_RECORD_AUX_OUTPUT_HW_ID = 21,\n\tPERF_RECORD_CALLCHAIN_DEFERRED = 22,\n\tPERF_RECORD_MAX = 23,\n};\n\nenum perf_event_x86_regs {\n\tPERF_REG_X86_AX = 0,\n\tPERF_REG_X86_BX = 1,\n\tPERF_REG_X86_CX = 2,\n\tPERF_REG_X86_DX = 3,\n\tPERF_REG_X86_SI = 4,\n\tPERF_REG_X86_DI = 5,\n\tPERF_REG_X86_BP = 6,\n\tPERF_REG_X86_SP = 7,\n\tPERF_REG_X86_IP = 8,\n\tPERF_REG_X86_FLAGS = 9,\n\tPERF_REG_X86_CS = 10,\n\tPERF_REG_X86_SS = 11,\n\tPERF_REG_X86_DS = 12,\n\tPERF_REG_X86_ES = 13,\n\tPERF_REG_X86_FS = 14,\n\tPERF_REG_X86_GS = 15,\n\tPERF_REG_X86_R8 = 16,\n\tPERF_REG_X86_R9 = 17,\n\tPERF_REG_X86_R10 = 18,\n\tPERF_REG_X86_R11 = 19,\n\tPERF_REG_X86_R12 = 20,\n\tPERF_REG_X86_R13 = 21,\n\tPERF_REG_X86_R14 = 22,\n\tPERF_REG_X86_R15 = 23,\n\tPERF_REG_X86_32_MAX = 16,\n\tPERF_REG_X86_64_MAX = 24,\n\tPERF_REG_X86_XMM0 = 32,\n\tPERF_REG_X86_XMM1 = 34,\n\tPERF_REG_X86_XMM2 = 36,\n\tPERF_REG_X86_XMM3 = 38,\n\tPERF_REG_X86_XMM4 = 40,\n\tPERF_REG_X86_XMM5 = 42,\n\tPERF_REG_X86_XMM6 = 44,\n\tPERF_REG_X86_XMM7 = 46,\n\tPERF_REG_X86_XMM8 = 48,\n\tPERF_REG_X86_XMM9 = 50,\n\tPERF_REG_X86_XMM10 = 52,\n\tPERF_REG_X86_XMM11 = 54,\n\tPERF_REG_X86_XMM12 = 56,\n\tPERF_REG_X86_XMM13 = 58,\n\tPERF_REG_X86_XMM14 = 60,\n\tPERF_REG_X86_XMM15 = 62,\n\tPERF_REG_X86_XMM_MAX = 64,\n};\n\nenum perf_hw_cache_id {\n\tPERF_COUNT_HW_CACHE_L1D = 0,\n\tPERF_COUNT_HW_CACHE_L1I = 1,\n\tPERF_COUNT_HW_CACHE_LL = 2,\n\tPERF_COUNT_HW_CACHE_DTLB = 3,\n\tPERF_COUNT_HW_CACHE_ITLB = 4,\n\tPERF_COUNT_HW_CACHE_BPU = 5,\n\tPERF_COUNT_HW_CACHE_NODE = 6,\n\tPERF_COUNT_HW_CACHE_MAX = 7,\n};\n\nenum perf_hw_cache_op_id {\n\tPERF_COUNT_HW_CACHE_OP_READ = 0,\n\tPERF_COUNT_HW_CACHE_OP_WRITE = 1,\n\tPERF_COUNT_HW_CACHE_OP_PREFETCH = 2,\n\tPERF_COUNT_HW_CACHE_OP_MAX = 3,\n};\n\nenum perf_hw_cache_op_result_id {\n\tPERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,\n\tPERF_COUNT_HW_CACHE_RESULT_MISS = 1,\n\tPERF_COUNT_HW_CACHE_RESULT_MAX = 2,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_msr_id {\n\tPERF_MSR_TSC = 0,\n\tPERF_MSR_APERF = 1,\n\tPERF_MSR_MPERF = 2,\n\tPERF_MSR_PPERF = 3,\n\tPERF_MSR_SMI = 4,\n\tPERF_MSR_PTSC = 5,\n\tPERF_MSR_IRPERF = 6,\n\tPERF_MSR_THERM = 7,\n\tPERF_MSR_EVENT_MAX = 8,\n};\n\nenum perf_pmu_scope {\n\tPERF_PMU_SCOPE_NONE = 0,\n\tPERF_PMU_SCOPE_CORE = 1,\n\tPERF_PMU_SCOPE_DIE = 2,\n\tPERF_PMU_SCOPE_CLUSTER = 3,\n\tPERF_PMU_SCOPE_PKG = 4,\n\tPERF_PMU_SCOPE_SYS_WIDE = 5,\n\tPERF_PMU_MAX_SCOPE = 6,\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum perf_rapl_pkg_events {\n\tPERF_RAPL_PP0 = 0,\n\tPERF_RAPL_PKG = 1,\n\tPERF_RAPL_RAM = 2,\n\tPERF_RAPL_PP1 = 3,\n\tPERF_RAPL_PSYS = 4,\n\tPERF_RAPL_PKG_EVENTS_MAX = 5,\n\tNR_RAPL_PKG_DOMAINS = 5,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nenum perf_snb_uncore_imc_freerunning_types {\n\tSNB_PCI_UNCORE_IMC_DATA_READS = 0,\n\tSNB_PCI_UNCORE_IMC_DATA_WRITES = 1,\n\tSNB_PCI_UNCORE_IMC_GT_REQUESTS = 2,\n\tSNB_PCI_UNCORE_IMC_IA_REQUESTS = 3,\n\tSNB_PCI_UNCORE_IMC_IO_REQUESTS = 4,\n\tSNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX = 5,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum perf_tgl_uncore_imc_freerunning_types {\n\tTGL_MMIO_UNCORE_IMC_DATA_TOTAL = 0,\n\tTGL_MMIO_UNCORE_IMC_DATA_READ = 1,\n\tTGL_MMIO_UNCORE_IMC_DATA_WRITE = 2,\n\tTGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum perf_uncore_dmr_iio_freerunning_type_id {\n\tDMR_ITC_INB_DATA_BW = 0,\n\tDMR_ITC_BW_IN = 1,\n\tDMR_OTC_BW_OUT = 2,\n\tDMR_OTC_CLOCK_TICKS = 3,\n\tDMR_IIO_FREERUNNING_TYPE_MAX = 4,\n};\n\nenum perf_uncore_icx_iio_freerunning_type_id {\n\tICX_IIO_MSR_IOCLK = 0,\n\tICX_IIO_MSR_BW_IN = 1,\n\tICX_IIO_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum perf_uncore_icx_imc_freerunning_type_id {\n\tICX_IMC_DCLK = 0,\n\tICX_IMC_DDR = 1,\n\tICX_IMC_DDRT = 2,\n\tICX_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_uncore_iio_freerunning_type_id {\n\tSKX_IIO_MSR_IOCLK = 0,\n\tSKX_IIO_MSR_BW = 1,\n\tSKX_IIO_MSR_UTIL = 2,\n\tSKX_IIO_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_uncore_snr_iio_freerunning_type_id {\n\tSNR_IIO_MSR_IOCLK = 0,\n\tSNR_IIO_MSR_BW_IN = 1,\n\tSNR_IIO_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum perf_uncore_snr_imc_freerunning_type_id {\n\tSNR_IMC_DCLK = 0,\n\tSNR_IMC_DDR = 1,\n\tSNR_IMC_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum perf_uncore_spr_iio_freerunning_type_id {\n\tSPR_IIO_MSR_IOCLK = 0,\n\tSPR_IIO_MSR_BW_IN = 1,\n\tSPR_IIO_MSR_BW_OUT = 2,\n\tSPR_IIO_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_uncore_spr_imc_freerunning_type_id {\n\tSPR_IMC_DCLK = 0,\n\tSPR_IMC_PQ_CYCLES = 1,\n\tSPR_IMC_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum pg_level {\n\tPG_LEVEL_NONE = 0,\n\tPG_LEVEL_4K = 1,\n\tPG_LEVEL_2M = 2,\n\tPG_LEVEL_1G = 3,\n\tPG_LEVEL_512G = 4,\n\tPG_LEVEL_256T = 5,\n\tPG_LEVEL_NUM = 6,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum phy {\n\tPHY_NONE = -1,\n\tPHY_A = 0,\n\tPHY_B = 1,\n\tPHY_C = 2,\n\tPHY_D = 3,\n\tPHY_E = 4,\n\tPHY_F = 5,\n\tPHY_G = 6,\n\tPHY_H = 7,\n\tPHY_I = 8,\n\tI915_MAX_PHYS = 9,\n};\n\nenum phy_fia {\n\tFIA1 = 0,\n\tFIA2 = 1,\n\tFIA3 = 2,\n};\n\nenum phy_media {\n\tPHY_MEDIA_DEFAULT = 0,\n\tPHY_MEDIA_SR = 1,\n\tPHY_MEDIA_DAC = 2,\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n\tPHY_MODE_HDMI = 20,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_port_parent {\n\tPHY_PORT_PHY = 0,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_state_work {\n\tPHY_STATE_WORK_NONE = 0,\n\tPHY_STATE_WORK_ANEG = 1,\n\tPHY_STATE_WORK_SUSPEND = 2,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_ufs_state {\n\tPHY_UFS_HIBERN8_ENTER = 0,\n\tPHY_UFS_HIBERN8_EXIT = 1,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidcg_event {\n\tPIDCG_MAX = 0,\n\tPIDCG_FORKFAIL = 1,\n\tNR_PIDCG_EVENTS = 2,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum piix_controller_ids {\n\tpiix_pata_mwdma = 0,\n\tpiix_pata_33 = 1,\n\tich_pata_33 = 2,\n\tich_pata_66 = 3,\n\tich_pata_100 = 4,\n\tich_pata_100_nomwdma1 = 5,\n\tich5_sata = 6,\n\tich6_sata = 7,\n\tich6m_sata = 8,\n\tich8_sata = 9,\n\tich8_2port_sata = 10,\n\tich8m_apple_sata = 11,\n\ttolapai_sata = 12,\n\tpiix_pata_vmw = 13,\n\tich8_sata_snb = 14,\n\tich8_2port_sata_snb = 15,\n\tich8_2port_sata_byt = 16,\n};\n\nenum pinctrl_map_type {\n\tPIN_MAP_TYPE_INVALID = 0,\n\tPIN_MAP_TYPE_DUMMY_STATE = 1,\n\tPIN_MAP_TYPE_MUX_GROUP = 2,\n\tPIN_MAP_TYPE_CONFIGS_PIN = 3,\n\tPIN_MAP_TYPE_CONFIGS_GROUP = 4,\n};\n\nenum pipe {\n\tINVALID_PIPE = -1,\n\tPIPE_A = 0,\n\tPIPE_B = 1,\n\tPIPE_C = 2,\n\tPIPE_D = 3,\n\t_PIPE_EDP = 4,\n\tI915_MAX_PIPES = 4,\n};\n\nenum pipedmc_event_id {\n\tPIPEDMC_EVENT_TMR0_DONE = 20,\n\tPIPEDMC_EVENT_TMR1_DONE = 21,\n\tPIPEDMC_EVENT_TMR2_DONE = 22,\n\tPIPEDMC_EVENT_COUNT0_DONE = 23,\n\tPIPEDMC_EVENT_COUNT1_DONE = 24,\n\tPIPEDMC_EVENT_PGA_PGB_RESTORE_DONE = 25,\n\tPIPEDMC_EVENT_PG1_PG2_RESTORE_DONE = 26,\n\tPIPEDMC_EVENT_PGA_PGB_SAVE_DONE = 27,\n\tPIPEDMC_EVENT_PG1_PG2_SAVE_DONE = 28,\n\tPIPEDMC_EVENT_FULL_FQ_WAKE_TRIGGER = 43,\n\tPIPEDMC_EVENT_1KHZ_FQ_TRIGGER = 44,\n\tPIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER = 45,\n\tPIPEDMC_EVENT_SCANLINE_INRANGE = 46,\n\tPIPEDMC_EVENT_SCANLINE_OUTRANGE = 47,\n\tPIPEDMC_EVENT_SCANLINE_EQUAL = 48,\n\tPIPEDMC_EVENT_DELAYED_VBLANK = 49,\n\tPIPEDMC_EVENT_VBLANK = 50,\n\tPIPEDMC_EVENT_HBLANK = 51,\n\tPIPEDMC_EVENT_VSYNC = 52,\n\tPIPEDMC_EVENT_SCANLINE_FROM_DMUX = 53,\n\tPIPEDMC_EVENT_PLANE1_FLIP = 54,\n\tPIPEDMC_EVENT_PLANE2_FLIP = 55,\n\tPIPEDMC_EVENT_PLANE3_FLIP = 56,\n\tPIPEDMC_EVENT_PLANE4_FLIP = 57,\n\tPIPEDMC_EVENT_PLANE5_FLIP = 58,\n\tPIPEDMC_EVENT_PLANE6_FLIP = 59,\n\tPIPEDMC_EVENT_PLANE7_FLIP = 60,\n\tPIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER = 61,\n\tPIPEDMC_EVENT_PLANE1_FLIP_DONE = 86,\n\tPIPEDMC_EVENT_PLANE2_FLIP_DONE = 87,\n\tPIPEDMC_EVENT_PLANE3_FLIP_DONE = 88,\n\tPIPEDMC_EVENT_PLANE4_FLIP_DONE = 89,\n\tPIPEDMC_EVENT_PLANE5_FLIP_DONE = 90,\n\tPIPEDMC_EVENT_PLANE6_FLIP_DONE = 91,\n\tPIPEDMC_EVENT_PLANE7_FLIP_DONE = 92,\n\tPIPEDMC_EVENT_GTT_ERR = 155,\n\tPIPEDMC_EVENT_IN_PSR = 181,\n\tPIPEDMC_EVENT_DSI_DMC_IDLE = 182,\n\tPIPEDMC_EVENT_PSR2_DMC_IDLE = 183,\n\tPIPEDMC_EVENT_IN_VGA = 184,\n\tPIPEDMC_EVENT_TRAP_HIT = 189,\n\tPIPEDMC_EVENT_CLK_USEC = 190,\n\tPIPEDMC_EVENT_CLK_MSEC = 191,\n\tPIPEDMC_EVENT_CHICKEN1 = 200,\n\tPIPEDMC_EVENT_CHICKEN2 = 201,\n\tPIPEDMC_EVENT_CHICKEN3 = 202,\n\tPIPEDMC_EVENT_DDT_UBP = 203,\n\tPIPEDMC_EVENT_LP_LATENCY = 206,\n\tPIPEDMC_EVENT_LACE_PART_A_HIST_TRIGGER = 223,\n\tPIPEDMC_EVENT_LACE_PART_B_HIST_TRIGGER = 224,\n\tPIPEDMC_EVENT_STACK_OVF = 252,\n\tPIPEDMC_EVENT_NO_CLAIM = 253,\n\tPIPEDMC_EVENT_UNK_CMD = 254,\n\tPIPEDMC_EVENT_HTP_MOD = 255,\n};\n\nenum pkcs7_actions {\n\tACT_pkcs7_check_content_type = 0,\n\tACT_pkcs7_extract_cert = 1,\n\tACT_pkcs7_note_OID = 2,\n\tACT_pkcs7_note_certificate_list = 3,\n\tACT_pkcs7_note_content = 4,\n\tACT_pkcs7_note_data = 5,\n\tACT_pkcs7_note_signed_info = 6,\n\tACT_pkcs7_note_signeddata_version = 7,\n\tACT_pkcs7_note_signerinfo_version = 8,\n\tACT_pkcs7_sig_note_authenticated_attr = 9,\n\tACT_pkcs7_sig_note_digest_algo = 10,\n\tACT_pkcs7_sig_note_issuer = 11,\n\tACT_pkcs7_sig_note_pkey_algo = 12,\n\tACT_pkcs7_sig_note_serial = 13,\n\tACT_pkcs7_sig_note_set_of_authattrs = 14,\n\tACT_pkcs7_sig_note_signature = 15,\n\tACT_pkcs7_sig_note_skid = 16,\n\tNR__pkcs7_actions = 17,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum plane_id {\n\tPLANE_1 = 0,\n\tPLANE_2 = 1,\n\tPLANE_3 = 2,\n\tPLANE_4 = 3,\n\tPLANE_5 = 4,\n\tPLANE_6 = 5,\n\tPLANE_7 = 6,\n\tPLANE_CURSOR = 7,\n\tI915_MAX_PLANES = 8,\n\tPLANE_PRIMARY = 0,\n\tPLANE_SPRITE0 = 1,\n\tPLANE_SPRITE1 = 2,\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = -1,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum pmc_type {\n\tKVM_PMC_GP = 0,\n\tKVM_PMC_FIXED = 1,\n};\n\nenum pmu_type {\n\tPMU_TYPE_COUNTER = 0,\n\tPMU_TYPE_EVNTSEL = 1,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port {\n\tPORT_NONE = -1,\n\tPORT_A = 0,\n\tPORT_B = 1,\n\tPORT_C = 2,\n\tPORT_D = 3,\n\tPORT_E = 4,\n\tPORT_F = 5,\n\tPORT_G = 6,\n\tPORT_H = 7,\n\tPORT_I = 8,\n\tPORT_TC1 = 3,\n\tPORT_TC2 = 4,\n\tPORT_TC3 = 5,\n\tPORT_TC4 = 6,\n\tPORT_TC5 = 7,\n\tPORT_TC6 = 8,\n\tPORT_D_XELPD = 7,\n\tPORT_E_XELPD = 8,\n\tI915_MAX_PORTS = 9,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum power_supply_charge_behaviour {\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO = 0,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE = 1,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE_AWAKE = 2,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE = 3,\n};\n\nenum power_supply_charge_type {\n\tPOWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_CHARGE_TYPE_NONE = 1,\n\tPOWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2,\n\tPOWER_SUPPLY_CHARGE_TYPE_FAST = 3,\n\tPOWER_SUPPLY_CHARGE_TYPE_STANDARD = 4,\n\tPOWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5,\n\tPOWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6,\n\tPOWER_SUPPLY_CHARGE_TYPE_LONGLIFE = 7,\n\tPOWER_SUPPLY_CHARGE_TYPE_BYPASS = 8,\n};\n\nenum power_supply_notifier_events {\n\tPSY_EVENT_PROP_CHANGED = 0,\n};\n\nenum power_supply_property {\n\tPOWER_SUPPLY_PROP_STATUS = 0,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPE = 1,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPES = 2,\n\tPOWER_SUPPLY_PROP_HEALTH = 3,\n\tPOWER_SUPPLY_PROP_PRESENT = 4,\n\tPOWER_SUPPLY_PROP_ONLINE = 5,\n\tPOWER_SUPPLY_PROP_AUTHENTIC = 6,\n\tPOWER_SUPPLY_PROP_TECHNOLOGY = 7,\n\tPOWER_SUPPLY_PROP_CYCLE_COUNT = 8,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX = 9,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN = 10,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN = 11,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN = 12,\n\tPOWER_SUPPLY_PROP_VOLTAGE_NOW = 13,\n\tPOWER_SUPPLY_PROP_VOLTAGE_AVG = 14,\n\tPOWER_SUPPLY_PROP_VOLTAGE_OCV = 15,\n\tPOWER_SUPPLY_PROP_VOLTAGE_BOOT = 16,\n\tPOWER_SUPPLY_PROP_CURRENT_MAX = 17,\n\tPOWER_SUPPLY_PROP_CURRENT_NOW = 18,\n\tPOWER_SUPPLY_PROP_CURRENT_AVG = 19,\n\tPOWER_SUPPLY_PROP_CURRENT_BOOT = 20,\n\tPOWER_SUPPLY_PROP_POWER_NOW = 21,\n\tPOWER_SUPPLY_PROP_POWER_AVG = 22,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL_DESIGN = 23,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN = 24,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL = 25,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY = 26,\n\tPOWER_SUPPLY_PROP_CHARGE_NOW = 27,\n\tPOWER_SUPPLY_PROP_CHARGE_AVG = 28,\n\tPOWER_SUPPLY_PROP_CHARGE_COUNTER = 29,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT = 30,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX = 31,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE = 32,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX = 33,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT = 34,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX = 35,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD = 36,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD = 37,\n\tPOWER_SUPPLY_PROP_CHARGE_BEHAVIOUR = 38,\n\tPOWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT = 39,\n\tPOWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT = 40,\n\tPOWER_SUPPLY_PROP_INPUT_POWER_LIMIT = 41,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL_DESIGN = 42,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN = 43,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL = 44,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY = 45,\n\tPOWER_SUPPLY_PROP_ENERGY_NOW = 46,\n\tPOWER_SUPPLY_PROP_ENERGY_AVG = 47,\n\tPOWER_SUPPLY_PROP_CAPACITY = 48,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MIN = 49,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MAX = 50,\n\tPOWER_SUPPLY_PROP_CAPACITY_ERROR_MARGIN = 51,\n\tPOWER_SUPPLY_PROP_CAPACITY_LEVEL = 52,\n\tPOWER_SUPPLY_PROP_TEMP = 53,\n\tPOWER_SUPPLY_PROP_TEMP_MAX = 54,\n\tPOWER_SUPPLY_PROP_TEMP_MIN = 55,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MIN = 56,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MAX = 57,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT = 58,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN = 59,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX = 60,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW = 61,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG = 62,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_NOW = 63,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_AVG = 64,\n\tPOWER_SUPPLY_PROP_TYPE = 65,\n\tPOWER_SUPPLY_PROP_USB_TYPE = 66,\n\tPOWER_SUPPLY_PROP_SCOPE = 67,\n\tPOWER_SUPPLY_PROP_PRECHARGE_CURRENT = 68,\n\tPOWER_SUPPLY_PROP_CHARGE_TERM_CURRENT = 69,\n\tPOWER_SUPPLY_PROP_CALIBRATE = 70,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_YEAR = 71,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_MONTH = 72,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_DAY = 73,\n\tPOWER_SUPPLY_PROP_INTERNAL_RESISTANCE = 74,\n\tPOWER_SUPPLY_PROP_STATE_OF_HEALTH = 75,\n\tPOWER_SUPPLY_PROP_MODEL_NAME = 76,\n\tPOWER_SUPPLY_PROP_MANUFACTURER = 77,\n\tPOWER_SUPPLY_PROP_SERIAL_NUMBER = 78,\n};\n\nenum power_supply_type {\n\tPOWER_SUPPLY_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_TYPE_BATTERY = 1,\n\tPOWER_SUPPLY_TYPE_UPS = 2,\n\tPOWER_SUPPLY_TYPE_MAINS = 3,\n\tPOWER_SUPPLY_TYPE_USB = 4,\n\tPOWER_SUPPLY_TYPE_USB_DCP = 5,\n\tPOWER_SUPPLY_TYPE_USB_CDP = 6,\n\tPOWER_SUPPLY_TYPE_USB_ACA = 7,\n\tPOWER_SUPPLY_TYPE_USB_TYPE_C = 8,\n\tPOWER_SUPPLY_TYPE_USB_PD = 9,\n\tPOWER_SUPPLY_TYPE_USB_PD_DRP = 10,\n\tPOWER_SUPPLY_TYPE_APPLE_BRICK_ID = 11,\n\tPOWER_SUPPLY_TYPE_WIRELESS = 12,\n};\n\nenum power_supply_usb_type {\n\tPOWER_SUPPLY_USB_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_USB_TYPE_SDP = 1,\n\tPOWER_SUPPLY_USB_TYPE_DCP = 2,\n\tPOWER_SUPPLY_USB_TYPE_CDP = 3,\n\tPOWER_SUPPLY_USB_TYPE_ACA = 4,\n\tPOWER_SUPPLY_USB_TYPE_C = 5,\n\tPOWER_SUPPLY_USB_TYPE_PD = 6,\n\tPOWER_SUPPLY_USB_TYPE_PD_DRP = 7,\n\tPOWER_SUPPLY_USB_TYPE_PD_PPS = 8,\n\tPOWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID = 9,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum prio_policy {\n\tPOLICY_NO_CHANGE = 0,\n\tPOLICY_PROMOTE_TO_RT = 1,\n\tPOLICY_RESTRICT_TO_BE = 2,\n\tPOLICY_ALL_TO_IDLE = 3,\n\tPOLICY_NONE_TO_RT = 4,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_print_type {\n\tPROBE_PRINT_NORMAL = 0,\n\tPROBE_PRINT_RETURN = 1,\n\tPROBE_PRINT_EVENT = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_cn_mcast_op {\n\tPROC_CN_MCAST_LISTEN = 1,\n\tPROC_CN_MCAST_IGNORE = 2,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___6 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum protection_domain_mode {\n\tPD_MODE_NONE = 0,\n\tPD_MODE_V1 = 1,\n\tPD_MODE_V2 = 2,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum ps2_disposition {\n\tPS2_PROCESS = 0,\n\tPS2_IGNORE = 1,\n\tPS2_ERROR = 2,\n};\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nenum pt_capabilities {\n\tPT_CAP_max_subleaf = 0,\n\tPT_CAP_cr3_filtering = 1,\n\tPT_CAP_psb_cyc = 2,\n\tPT_CAP_ip_filtering = 3,\n\tPT_CAP_mtc = 4,\n\tPT_CAP_ptwrite = 5,\n\tPT_CAP_power_event_trace = 6,\n\tPT_CAP_event_trace = 7,\n\tPT_CAP_tnt_disable = 8,\n\tPT_CAP_topa_output = 9,\n\tPT_CAP_topa_multiple_entries = 10,\n\tPT_CAP_single_range_output = 11,\n\tPT_CAP_output_subsys = 12,\n\tPT_CAP_payloads_lip = 13,\n\tPT_CAP_num_address_ranges = 14,\n\tPT_CAP_mtc_periods = 15,\n\tPT_CAP_cycle_thresholds = 16,\n\tPT_CAP_psb_periods = 17,\n};\n\nenum pt_entry_type {\n\tPT_ENTRY_EMPTY = 0,\n\tPT_ENTRY_TABLE = 1,\n\tPT_ENTRY_OA = 2,\n};\n\nenum pt_features {\n\tPT_FEAT_DMA_INCOHERENT = 0,\n\tPT_FEAT_FULL_VA = 1,\n\tPT_FEAT_DYNAMIC_TOP = 2,\n\tPT_FEAT_SIGN_EXTEND = 3,\n\tPT_FEAT_FLUSH_RANGE = 4,\n\tPT_FEAT_FLUSH_RANGE_NO_GAPS = 5,\n\tPT_FEAT_FMT_START = 6,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum pti_clone_level {\n\tPTI_CLONE_PMD = 0,\n\tPTI_CLONE_PTE = 1,\n};\n\nenum pti_mode {\n\tPTI_AUTO = 0,\n\tPTI_FORCE_OFF = 1,\n\tPTI_FORCE_ON = 2,\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_EXTOFF = 2,\n\tPTP_CLOCK_PPS = 3,\n\tPTP_CLOCK_PPSUSR = 4,\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nenum pwm_polarity {\n\tPWM_POLARITY_NORMAL = 0,\n\tPWM_POLARITY_INVERSED = 1,\n};\n\nenum pxp_status {\n\tPXP_STATUS_SUCCESS = 0,\n\tPXP_STATUS_ERROR_API_VERSION = 4098,\n\tPXP_STATUS_NOT_READY = 4110,\n\tPXP_STATUS_PLATFCONFIG_KF1_NOVERIF = 4122,\n\tPXP_STATUS_PLATFCONFIG_KF1_BAD = 4127,\n\tPXP_STATUS_OP_NOT_PERMITTED = 16403,\n};\n\nenum qdisc_class_ops_flags {\n\tQDISC_CLASS_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum ramfs_param {\n\tOpt_mode___6 = 0,\n};\n\nenum rapl_unit_quirk {\n\tRAPL_UNIT_QUIRK_NONE = 0,\n\tRAPL_UNIT_QUIRK_INTEL_HSW = 1,\n\tRAPL_UNIT_QUIRK_INTEL_SPR = 2,\n};\n\nenum rc_driver_type {\n\tRC_DRIVER_SCANCODE = 0,\n\tRC_DRIVER_IR_RAW = 1,\n\tRC_DRIVER_IR_RAW_TX = 2,\n};\n\nenum rc_proto {\n\tRC_PROTO_UNKNOWN = 0,\n\tRC_PROTO_OTHER = 1,\n\tRC_PROTO_RC5 = 2,\n\tRC_PROTO_RC5X_20 = 3,\n\tRC_PROTO_RC5_SZ = 4,\n\tRC_PROTO_JVC = 5,\n\tRC_PROTO_SONY12 = 6,\n\tRC_PROTO_SONY15 = 7,\n\tRC_PROTO_SONY20 = 8,\n\tRC_PROTO_NEC = 9,\n\tRC_PROTO_NECX = 10,\n\tRC_PROTO_NEC32 = 11,\n\tRC_PROTO_SANYO = 12,\n\tRC_PROTO_MCIR2_KBD = 13,\n\tRC_PROTO_MCIR2_MSE = 14,\n\tRC_PROTO_RC6_0 = 15,\n\tRC_PROTO_RC6_6A_20 = 16,\n\tRC_PROTO_RC6_6A_24 = 17,\n\tRC_PROTO_RC6_6A_32 = 18,\n\tRC_PROTO_RC6_MCE = 19,\n\tRC_PROTO_SHARP = 20,\n\tRC_PROTO_XMP = 21,\n\tRC_PROTO_CEC = 22,\n\tRC_PROTO_IMON = 23,\n\tRC_PROTO_RCMM12 = 24,\n\tRC_PROTO_RCMM24 = 25,\n\tRC_PROTO_RCMM32 = 26,\n\tRC_PROTO_XBOX_DVD = 27,\n\tRC_PROTO_MAX = 27,\n};\n\nenum rdmacg_file_type {\n\tRDMACG_RESOURCE_TYPE_MAX = 0,\n\tRDMACG_RESOURCE_TYPE_STAT = 1,\n};\n\nenum rdmacg_resource_type {\n\tRDMACG_RESOURCE_HCA_HANDLE = 0,\n\tRDMACG_RESOURCE_HCA_OBJECT = 1,\n\tRDMACG_RESOURCE_MAX = 2,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum recovery_flags {\n\tMD_RECOVERY_NEEDED = 0,\n\tMD_RECOVERY_RUNNING = 1,\n\tMD_RECOVERY_INTR = 2,\n\tMD_RECOVERY_DONE = 3,\n\tMD_RECOVERY_FROZEN = 4,\n\tMD_RECOVERY_WAIT = 5,\n\tMD_RECOVERY_SYNC = 6,\n\tMD_RECOVERY_REQUESTED = 7,\n\tMD_RECOVERY_CHECK = 8,\n\tMD_RECOVERY_RECOVER = 9,\n\tMD_RECOVERY_RESHAPE = 10,\n\tMD_RESYNCING_REMOTE = 11,\n\tMD_RECOVERY_LAZY_RECOVER = 12,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum reg_type {\n\tREG_TYPE_RM = 0,\n\tREG_TYPE_REG = 1,\n\tREG_TYPE_INDEX = 2,\n\tREG_TYPE_BASE = 3,\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_FLAT = 2,\n\tREGCACHE_MAPLE = 3,\n\tREGCACHE_FLAT_S = 4,\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum report_header {\n\tHDR_32_BIT = 0,\n\tHDR_64_BIT = 1,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reset_control_flags {\n\tRESET_CONTROL_EXCLUSIVE = 4,\n\tRESET_CONTROL_EXCLUSIVE_DEASSERTED = 12,\n\tRESET_CONTROL_EXCLUSIVE_RELEASED = 0,\n\tRESET_CONTROL_SHARED = 1,\n\tRESET_CONTROL_SHARED_DEASSERTED = 9,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE = 6,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_DEASSERTED = 14,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_RELEASED = 2,\n\tRESET_CONTROL_OPTIONAL_SHARED = 3,\n\tRESET_CONTROL_OPTIONAL_SHARED_DEASSERTED = 11,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum retbleed_mitigation {\n\tRETBLEED_MITIGATION_NONE = 0,\n\tRETBLEED_MITIGATION_AUTO = 1,\n\tRETBLEED_MITIGATION_UNRET = 2,\n\tRETBLEED_MITIGATION_IBPB = 3,\n\tRETBLEED_MITIGATION_IBRS = 4,\n\tRETBLEED_MITIGATION_EIBRS = 5,\n\tRETBLEED_MITIGATION_STUFF = 6,\n};\n\nenum rex_bits {\n\tREX_B = 1,\n\tREX_X = 2,\n\tREX_R = 4,\n\tREX_W = 8,\n};\n\nenum rex_type {\n\tREX_NONE = 0,\n\tREX_PREFIX = 1,\n};\n\nenum rfds_mitigations {\n\tRFDS_MITIGATION_OFF = 0,\n\tRFDS_MITIGATION_AUTO = 1,\n\tRFDS_MITIGATION_VERW = 2,\n\tRFDS_MITIGATION_UCODE_NEEDED = 3,\n};\n\nenum rfkill_type {\n\tRFKILL_TYPE_ALL = 0,\n\tRFKILL_TYPE_WLAN = 1,\n\tRFKILL_TYPE_BLUETOOTH = 2,\n\tRFKILL_TYPE_UWB = 3,\n\tRFKILL_TYPE_WIMAX = 4,\n\tRFKILL_TYPE_WWAN = 5,\n\tRFKILL_TYPE_GPS = 6,\n\tRFKILL_TYPE_FM = 7,\n\tRFKILL_TYPE_NFC = 8,\n\tNUM_RFKILL_TYPES = 9,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rsaprivkey_actions {\n\tACT_rsa_get_d = 0,\n\tACT_rsa_get_dp = 1,\n\tACT_rsa_get_dq = 2,\n\tACT_rsa_get_e = 3,\n\tACT_rsa_get_n = 4,\n\tACT_rsa_get_p = 5,\n\tACT_rsa_get_q = 6,\n\tACT_rsa_get_qinv = 7,\n\tNR__rsaprivkey_actions = 8,\n};\n\nenum rsapubkey_actions {\n\tACT_rsa_get_e___2 = 0,\n\tACT_rsa_get_n___2 = 1,\n\tNR__rsapubkey_actions = 2,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP___2 = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 10000,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 30000,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_REENQ_LOCAL_MAX_REPEAT = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_IMMED = 8589934592ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n\tSCX_ENQ_GDSQ_FALLBACK = 576460752303423488ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_IMMED = 32,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_REENQ_IMMED = 8192,\n\tSCX_TASK_REENQ_PREEMPTED = 12288,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_ALWAYS_ENQ_IMMED = 128ULL,\n\tSCX_OPS_ALL_FLAGS = 255ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1ULL,\n\t__SCX_REENQ_FILTER_MASK = 65535ULL,\n\t__SCX_REENQ_USER_MASK = 1ULL,\n\tSCX_REENQ_TSR_RQ_OPEN = 4294967296ULL,\n\tSCX_REENQ_TSR_NOT_FIRST = 8589934592ULL,\n\t__SCX_REENQ_TSR_MASK = 64424509440ULL,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum segment_cache_field {\n\tSEG_FIELD_SEL = 0,\n\tSEG_FIELD_BASE = 1,\n\tSEG_FIELD_LIMIT = 2,\n\tSEG_FIELD_AR = 3,\n\tSEG_FIELD_NR = 4,\n};\n\nenum ser {\n\tSER_REQUIRED = 1,\n\tNO_SER = 2,\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nenum set_event_iter_type {\n\tSET_EVENT_FILE = 0,\n\tSET_EVENT_MOD = 1,\n};\n\nenum severity_level {\n\tMCE_NO_SEVERITY = 0,\n\tMCE_DEFERRED_SEVERITY = 1,\n\tMCE_UCNA_SEVERITY = 1,\n\tMCE_KEEP_SEVERITY = 2,\n\tMCE_SOME_SEVERITY = 3,\n\tMCE_AO_SEVERITY = 4,\n\tMCE_UC_SEVERITY = 5,\n\tMCE_AR_SEVERITY = 6,\n\tMCE_PANIC_SEVERITY = 7,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum sgx_attribute {\n\tSGX_ATTR_INIT = 1,\n\tSGX_ATTR_DEBUG = 2,\n\tSGX_ATTR_MODE64BIT = 4,\n\tSGX_ATTR_PROVISIONKEY = 16,\n\tSGX_ATTR_EINITTOKENKEY = 32,\n\tSGX_ATTR_KSS = 128,\n\tSGX_ATTR_ASYNC_EXIT_NOTIFY = 1024,\n};\n\nenum sgx_miscselect {\n\tSGX_MISC_EXINFO = 1,\n};\n\nenum sgx_page_type {\n\tSGX_PAGE_TYPE_SECS = 0,\n\tSGX_PAGE_TYPE_TCS = 1,\n\tSGX_PAGE_TYPE_REG = 2,\n\tSGX_PAGE_TYPE_VA = 3,\n\tSGX_PAGE_TYPE_TRIM = 4,\n};\n\nenum shmem_param {\n\tOpt_gid___7 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___7 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes___2 = 5,\n\tOpt_size___2 = 6,\n\tOpt_uid___6 = 7,\n\tOpt_inode32 = 8,\n\tOpt_inode64 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota = 11,\n\tOpt_usrquota = 12,\n\tOpt_grpquota = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum show_regs_mode {\n\tSHOW_REGS_SHORT = 0,\n\tSHOW_REGS_USER = 1,\n\tSHOW_REGS_ALL = 2,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum skl_power_gate {\n\tSKL_PG0 = 0,\n\tSKL_PG1 = 1,\n\tSKL_PG2 = 2,\n\tICL_PG3 = 3,\n\tICL_PG4 = 4,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN = 0,\n\tPARTIAL = 1,\n\tUP = 2,\n\tFULL = 3,\n};\n\nenum slpc_event_id {\n\tSLPC_EVENT_RESET = 0,\n\tSLPC_EVENT_SHUTDOWN = 1,\n\tSLPC_EVENT_PLATFORM_INFO_CHANGE = 2,\n\tSLPC_EVENT_DISPLAY_MODE_CHANGE = 3,\n\tSLPC_EVENT_FLIP_COMPLETE = 4,\n\tSLPC_EVENT_QUERY_TASK_STATE = 5,\n\tSLPC_EVENT_PARAMETER_SET = 6,\n\tSLPC_EVENT_PARAMETER_UNSET = 7,\n};\n\nenum slpc_global_state {\n\tSLPC_GLOBAL_STATE_NOT_RUNNING = 0,\n\tSLPC_GLOBAL_STATE_INITIALIZING = 1,\n\tSLPC_GLOBAL_STATE_RESETTING = 2,\n\tSLPC_GLOBAL_STATE_RUNNING = 3,\n\tSLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,\n\tSLPC_GLOBAL_STATE_ERROR = 5,\n};\n\nenum slpc_media_ratio_mode {\n\tSLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL = 0,\n\tSLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE = 1,\n\tSLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,\n};\n\nenum slpc_param_id {\n\tSLPC_PARAM_TASK_ENABLE_GTPERF = 0,\n\tSLPC_PARAM_TASK_DISABLE_GTPERF = 1,\n\tSLPC_PARAM_TASK_ENABLE_BALANCER = 2,\n\tSLPC_PARAM_TASK_DISABLE_BALANCER = 3,\n\tSLPC_PARAM_TASK_ENABLE_DCC = 4,\n\tSLPC_PARAM_TASK_DISABLE_DCC = 5,\n\tSLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,\n\tSLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,\n\tSLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,\n\tSLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,\n\tSLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,\n\tSLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,\n\tSLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,\n\tSLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,\n\tSLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,\n\tSLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,\n\tSLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,\n\tSLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,\n\tSLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,\n\tSLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,\n\tSLPC_PARAM_GLOBAL_RT_MODE_TURBO_FREQ_DELTA_MHZ = 20,\n\tSLPC_PARAM_PWRGATE_RC_MODE = 21,\n\tSLPC_PARAM_EDR_MODE_COMPUTE_TIMEOUT_MS = 22,\n\tSLPC_PARAM_EDR_QOS_FREQ_MHZ = 23,\n\tSLPC_PARAM_MEDIA_FF_RATIO_MODE = 24,\n\tSLPC_PARAM_ENABLE_IA_FREQ_LIMITING = 25,\n\tSLPC_PARAM_STRATEGIES = 26,\n\tSLPC_PARAM_POWER_PROFILE = 27,\n\tSLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY = 28,\n\tSLPC_MAX_PARAM = 32,\n};\n\nenum slpc_power_profiles {\n\tSLPC_POWER_PROFILES_BASE = 0,\n\tSLPC_POWER_PROFILES_POWER_SAVING = 1,\n};\n\nenum smbios_attr_enum {\n\tSMBIOS_ATTR_NONE = 0,\n\tSMBIOS_ATTR_LABEL_SHOW = 1,\n\tSMBIOS_ATTR_INSTANCE_SHOW = 2,\n};\n\nenum smca_bank_types {\n\tSMCA_LS = 0,\n\tSMCA_LS_V2 = 1,\n\tSMCA_IF = 2,\n\tSMCA_L2_CACHE = 3,\n\tSMCA_DE = 4,\n\tSMCA_RESERVED = 5,\n\tSMCA_EX = 6,\n\tSMCA_FP = 7,\n\tSMCA_L3_CACHE = 8,\n\tSMCA_CS = 9,\n\tSMCA_CS_V2 = 10,\n\tSMCA_PIE = 11,\n\tSMCA_UMC = 12,\n\tSMCA_UMC_V2 = 13,\n\tSMCA_MA_LLC = 14,\n\tSMCA_PB = 15,\n\tSMCA_PSP = 16,\n\tSMCA_PSP_V2 = 17,\n\tSMCA_SMU = 18,\n\tSMCA_SMU_V2 = 19,\n\tSMCA_MP5 = 20,\n\tSMCA_MPDMA = 21,\n\tSMCA_NBIO = 22,\n\tSMCA_PCIE = 23,\n\tSMCA_PCIE_V2 = 24,\n\tSMCA_XGMI_PCS = 25,\n\tSMCA_NBIF = 26,\n\tSMCA_SHUB = 27,\n\tSMCA_SATA = 28,\n\tSMCA_USB = 29,\n\tSMCA_USR_DP = 30,\n\tSMCA_USR_CP = 31,\n\tSMCA_GMI_PCS = 32,\n\tSMCA_XGMI_PHY = 33,\n\tSMCA_WAFL_PHY = 34,\n\tSMCA_GMI_PHY = 35,\n\tN_SMCA_BANK_TYPES = 36,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum snd_compr_direction {\n\tSND_COMPRESS_PLAYBACK = 0,\n\tSND_COMPRESS_CAPTURE = 1,\n\tSND_COMPRESS_ACCEL = 2,\n};\n\nenum snd_ctl_add_mode {\n\tCTL_ADD_EXCLUSIVE = 0,\n\tCTL_REPLACE = 1,\n\tCTL_ADD_ON_REPLACE = 2,\n};\n\nenum snd_ctl_led_mode {\n\tMODE_FOLLOW_MUTE = 0,\n\tMODE_FOLLOW_ROUTE = 1,\n\tMODE_OFF = 2,\n\tMODE_ON = 3,\n};\n\nenum snd_device_state {\n\tSNDRV_DEV_BUILD = 0,\n\tSNDRV_DEV_REGISTERED = 1,\n\tSNDRV_DEV_DISCONNECTED = 2,\n};\n\nenum snd_device_type {\n\tSNDRV_DEV_LOWLEVEL = 0,\n\tSNDRV_DEV_INFO = 1,\n\tSNDRV_DEV_BUS = 2,\n\tSNDRV_DEV_CODEC = 3,\n\tSNDRV_DEV_PCM = 4,\n\tSNDRV_DEV_COMPRESS = 5,\n\tSNDRV_DEV_RAWMIDI = 6,\n\tSNDRV_DEV_TIMER = 7,\n\tSNDRV_DEV_SEQUENCER = 8,\n\tSNDRV_DEV_HWDEP = 9,\n\tSNDRV_DEV_JACK = 10,\n\tSNDRV_DEV_CONTROL = 11,\n};\n\nenum snd_dma_sync_mode {\n\tSNDRV_DMA_SYNC_CPU = 0,\n\tSNDRV_DMA_SYNC_DEVICE = 1,\n};\n\nenum snd_jack_types {\n\tSND_JACK_HEADPHONE = 1,\n\tSND_JACK_MICROPHONE = 2,\n\tSND_JACK_HEADSET = 3,\n\tSND_JACK_LINEOUT = 4,\n\tSND_JACK_MECHANICAL = 8,\n\tSND_JACK_VIDEOOUT = 16,\n\tSND_JACK_AVOUT = 20,\n\tSND_JACK_LINEIN = 32,\n\tSND_JACK_USB = 64,\n\tSND_JACK_BTN_0 = 16384,\n\tSND_JACK_BTN_1 = 8192,\n\tSND_JACK_BTN_2 = 4096,\n\tSND_JACK_BTN_3 = 2048,\n\tSND_JACK_BTN_4 = 1024,\n\tSND_JACK_BTN_5 = 512,\n};\n\nenum sndrv_ctl_event_type {\n\tSNDRV_CTL_EVENT_ELEM = 0,\n\tSNDRV_CTL_EVENT_LAST = 0,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum spectre_v1_mitigation {\n\tSPECTRE_V1_MITIGATION_NONE = 0,\n\tSPECTRE_V1_MITIGATION_AUTO = 1,\n};\n\nenum spectre_v2_mitigation {\n\tSPECTRE_V2_NONE = 0,\n\tSPECTRE_V2_RETPOLINE = 1,\n\tSPECTRE_V2_LFENCE = 2,\n\tSPECTRE_V2_EIBRS = 3,\n\tSPECTRE_V2_EIBRS_RETPOLINE = 4,\n\tSPECTRE_V2_EIBRS_LFENCE = 5,\n\tSPECTRE_V2_IBRS = 6,\n};\n\nenum spectre_v2_mitigation_cmd {\n\tSPECTRE_V2_CMD_NONE = 0,\n\tSPECTRE_V2_CMD_AUTO = 1,\n\tSPECTRE_V2_CMD_FORCE = 2,\n\tSPECTRE_V2_CMD_RETPOLINE = 3,\n\tSPECTRE_V2_CMD_RETPOLINE_GENERIC = 4,\n\tSPECTRE_V2_CMD_RETPOLINE_LFENCE = 5,\n\tSPECTRE_V2_CMD_EIBRS = 6,\n\tSPECTRE_V2_CMD_EIBRS_RETPOLINE = 7,\n\tSPECTRE_V2_CMD_EIBRS_LFENCE = 8,\n\tSPECTRE_V2_CMD_IBRS = 9,\n};\n\nenum spectre_v2_user_mitigation {\n\tSPECTRE_V2_USER_NONE = 0,\n\tSPECTRE_V2_USER_STRICT = 1,\n\tSPECTRE_V2_USER_STRICT_PREFERRED = 2,\n\tSPECTRE_V2_USER_PRCTL = 3,\n\tSPECTRE_V2_USER_SECCOMP = 4,\n};\n\nenum spectre_v2_user_mitigation_cmd {\n\tSPECTRE_V2_USER_CMD_NONE = 0,\n\tSPECTRE_V2_USER_CMD_AUTO = 1,\n\tSPECTRE_V2_USER_CMD_FORCE = 2,\n\tSPECTRE_V2_USER_CMD_PRCTL = 3,\n\tSPECTRE_V2_USER_CMD_PRCTL_IBPB = 4,\n\tSPECTRE_V2_USER_CMD_SECCOMP = 5,\n\tSPECTRE_V2_USER_CMD_SECCOMP_IBPB = 6,\n};\n\nenum spi_compare_returns {\n\tSPI_COMPARE_SUCCESS = 0,\n\tSPI_COMPARE_FAILURE = 1,\n\tSPI_COMPARE_SKIP_TEST = 2,\n};\n\nenum spi_signal_type {\n\tSPI_SIGNAL_UNKNOWN = 1,\n\tSPI_SIGNAL_SE = 2,\n\tSPI_SIGNAL_LVD = 3,\n\tSPI_SIGNAL_HVD = 4,\n};\n\nenum split_lock_detect_state {\n\tsld_off = 0,\n\tsld_warn = 1,\n\tsld_fatal = 2,\n\tsld_ratelimit = 3,\n};\n\nenum squashfs_param {\n\tOpt_errors = 0,\n\tOpt_threads = 1,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum srbds_mitigations {\n\tSRBDS_MITIGATION_OFF = 0,\n\tSRBDS_MITIGATION_AUTO = 1,\n\tSRBDS_MITIGATION_UCODE_NEEDED = 2,\n\tSRBDS_MITIGATION_FULL = 3,\n\tSRBDS_MITIGATION_TSX_OFF = 4,\n\tSRBDS_MITIGATION_HYPERVISOR = 5,\n};\n\nenum srso_mitigation {\n\tSRSO_MITIGATION_NONE = 0,\n\tSRSO_MITIGATION_AUTO = 1,\n\tSRSO_MITIGATION_UCODE_NEEDED = 2,\n\tSRSO_MITIGATION_SAFE_RET_UCODE_NEEDED = 3,\n\tSRSO_MITIGATION_MICROCODE = 4,\n\tSRSO_MITIGATION_NOSMT = 5,\n\tSRSO_MITIGATION_SAFE_RET = 6,\n\tSRSO_MITIGATION_IBPB = 7,\n\tSRSO_MITIGATION_IBPB_ON_VMEXIT = 8,\n\tSRSO_MITIGATION_BP_SPEC_REDUCE = 9,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum ssb_mitigation {\n\tSPEC_STORE_BYPASS_NONE = 0,\n\tSPEC_STORE_BYPASS_AUTO = 1,\n\tSPEC_STORE_BYPASS_DISABLE = 2,\n\tSPEC_STORE_BYPASS_PRCTL = 3,\n\tSPEC_STORE_BYPASS_SECCOMP = 4,\n};\n\nenum stack_type {\n\tSTACK_TYPE_UNKNOWN = 0,\n\tSTACK_TYPE_TASK = 1,\n\tSTACK_TYPE_IRQ = 2,\n\tSTACK_TYPE_SOFTIRQ = 3,\n\tSTACK_TYPE_ENTRY = 4,\n\tSTACK_TYPE_EXCEPTION = 5,\n\tSTACK_TYPE_EXCEPTION_LAST = 10,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum subpixel_order {\n\tSubPixelUnknown = 0,\n\tSubPixelHorizontalRGB = 1,\n\tSubPixelHorizontalBGR = 2,\n\tSubPixelVerticalRGB = 3,\n\tSubPixelVerticalBGR = 4,\n\tSubPixelNone = 5,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum suspend_mode {\n\tPRESUSPEND = 0,\n\tPRESUSPEND_UNDO = 1,\n\tPOSTSUSPEND = 2,\n};\n\nenum suspend_stat_step {\n\tSUSPEND_WORKING = 0,\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nenum sw_activity {\n\tOFF = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum switch_power_state {\n\tDRM_SWITCH_POWER_ON = 0,\n\tDRM_SWITCH_POWER_OFF = 1,\n\tDRM_SWITCH_POWER_CHANGING = 2,\n\tDRM_SWITCH_POWER_DYNAMIC_OFF = 3,\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nenum sync {\n\tDEFAULTSYNC = 0,\n\tNOSYNC = 1,\n\tFORCESYNC = 2,\n};\n\nenum sync_action {\n\tACTION_RESYNC = 0,\n\tACTION_RECOVER = 1,\n\tACTION_CHECK = 2,\n\tACTION_REPAIR = 3,\n\tACTION_RESHAPE = 4,\n\tACTION_FROZEN = 5,\n\tACTION_IDLE = 6,\n\tNR_SYNC_ACTIONS = 7,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum syscall_work_bit {\n\tSYSCALL_WORK_BIT_SECCOMP = 0,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACEPOINT = 1,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACE = 2,\n\tSYSCALL_WORK_BIT_SYSCALL_EMU = 3,\n\tSYSCALL_WORK_BIT_SYSCALL_AUDIT = 4,\n\tSYSCALL_WORK_BIT_SYSCALL_USER_DISPATCH = 5,\n\tSYSCALL_WORK_BIT_SYSCALL_EXIT_TRAP = 6,\n\tSYSCALL_WORK_BIT_SYSCALL_RSEQ_SLICE = 7,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum taa_mitigations {\n\tTAA_MITIGATION_OFF = 0,\n\tTAA_MITIGATION_AUTO = 1,\n\tTAA_MITIGATION_UCODE_NEEDED = 2,\n\tTAA_MITIGATION_VERW = 3,\n\tTAA_MITIGATION_TSX_DISABLED = 4,\n};\n\nenum target_state {\n\tSTATE_DISABLED = 0,\n\tSTATE_ENABLED = 1,\n\tSTATE_DEACTIVATED = 2,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_fifo_command {\n\tTC_FIFO_REPLACE = 0,\n\tTC_FIFO_DESTROY = 1,\n\tTC_FIFO_STATS = 2,\n};\n\nenum tc_link_layer {\n\tTC_LINKLAYER_UNAWARE = 0,\n\tTC_LINKLAYER_ETHERNET = 1,\n\tTC_LINKLAYER_ATM = 2,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_port {\n\tTC_PORT_NONE = -1,\n\tTC_PORT_1 = 0,\n\tTC_PORT_2 = 1,\n\tTC_PORT_3 = 2,\n\tTC_PORT_4 = 3,\n\tTC_PORT_5 = 4,\n\tTC_PORT_6 = 5,\n\tI915_MAX_TC_PORTS = 6,\n};\n\nenum tc_port_mode {\n\tTC_PORT_DISCONNECTED = 0,\n\tTC_PORT_TBT_ALT = 1,\n\tTC_PORT_DP_ALT = 2,\n\tTC_PORT_LEGACY = 3,\n};\n\nenum tc_root_command {\n\tTC_ROOT_GRAFT = 0,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcf_proto_ops_flags {\n\tTCF_PROTO_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum thermal_device_mode {\n\tTHERMAL_DEVICE_DISABLED = 0,\n\tTHERMAL_DEVICE_ENABLED = 1,\n};\n\nenum thermal_genl_attr {\n\tTHERMAL_GENL_ATTR_UNSPEC = 0,\n\tTHERMAL_GENL_ATTR_TZ = 1,\n\tTHERMAL_GENL_ATTR_TZ_ID = 2,\n\tTHERMAL_GENL_ATTR_TZ_TEMP = 3,\n\tTHERMAL_GENL_ATTR_TZ_TRIP = 4,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_ID = 5,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_TYPE = 6,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_TEMP = 7,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_HYST = 8,\n\tTHERMAL_GENL_ATTR_TZ_MODE = 9,\n\tTHERMAL_GENL_ATTR_TZ_NAME = 10,\n\tTHERMAL_GENL_ATTR_TZ_CDEV_WEIGHT = 11,\n\tTHERMAL_GENL_ATTR_TZ_GOV = 12,\n\tTHERMAL_GENL_ATTR_TZ_GOV_NAME = 13,\n\tTHERMAL_GENL_ATTR_CDEV = 14,\n\tTHERMAL_GENL_ATTR_CDEV_ID = 15,\n\tTHERMAL_GENL_ATTR_CDEV_CUR_STATE = 16,\n\tTHERMAL_GENL_ATTR_CDEV_MAX_STATE = 17,\n\tTHERMAL_GENL_ATTR_CDEV_NAME = 18,\n\tTHERMAL_GENL_ATTR_GOV_NAME = 19,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY = 20,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY_ID = 21,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY_PERFORMANCE = 22,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY_EFFICIENCY = 23,\n\tTHERMAL_GENL_ATTR_THRESHOLD = 24,\n\tTHERMAL_GENL_ATTR_THRESHOLD_TEMP = 25,\n\tTHERMAL_GENL_ATTR_THRESHOLD_DIRECTION = 26,\n\tTHERMAL_GENL_ATTR_TZ_PREV_TEMP = 27,\n\t__THERMAL_GENL_ATTR_MAX = 28,\n};\n\nenum thermal_genl_cmd {\n\tTHERMAL_GENL_CMD_UNSPEC = 0,\n\tTHERMAL_GENL_CMD_TZ_GET_ID = 1,\n\tTHERMAL_GENL_CMD_TZ_GET_TRIP = 2,\n\tTHERMAL_GENL_CMD_TZ_GET_TEMP = 3,\n\tTHERMAL_GENL_CMD_TZ_GET_GOV = 4,\n\tTHERMAL_GENL_CMD_TZ_GET_MODE = 5,\n\tTHERMAL_GENL_CMD_CDEV_GET = 6,\n\tTHERMAL_GENL_CMD_THRESHOLD_GET = 7,\n\tTHERMAL_GENL_CMD_THRESHOLD_ADD = 8,\n\tTHERMAL_GENL_CMD_THRESHOLD_DELETE = 9,\n\tTHERMAL_GENL_CMD_THRESHOLD_FLUSH = 10,\n\t__THERMAL_GENL_CMD_MAX = 11,\n};\n\nenum thermal_genl_event {\n\tTHERMAL_GENL_EVENT_UNSPEC = 0,\n\tTHERMAL_GENL_EVENT_TZ_CREATE = 1,\n\tTHERMAL_GENL_EVENT_TZ_DELETE = 2,\n\tTHERMAL_GENL_EVENT_TZ_DISABLE = 3,\n\tTHERMAL_GENL_EVENT_TZ_ENABLE = 4,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_UP = 5,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_DOWN = 6,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_CHANGE = 7,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_ADD = 8,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_DELETE = 9,\n\tTHERMAL_GENL_EVENT_CDEV_ADD = 10,\n\tTHERMAL_GENL_EVENT_CDEV_DELETE = 11,\n\tTHERMAL_GENL_EVENT_CDEV_STATE_UPDATE = 12,\n\tTHERMAL_GENL_EVENT_TZ_GOV_CHANGE = 13,\n\tTHERMAL_GENL_EVENT_CPU_CAPABILITY_CHANGE = 14,\n\tTHERMAL_GENL_EVENT_THRESHOLD_ADD = 15,\n\tTHERMAL_GENL_EVENT_THRESHOLD_DELETE = 16,\n\tTHERMAL_GENL_EVENT_THRESHOLD_FLUSH = 17,\n\tTHERMAL_GENL_EVENT_THRESHOLD_UP = 18,\n\tTHERMAL_GENL_EVENT_THRESHOLD_DOWN = 19,\n\t__THERMAL_GENL_EVENT_MAX = 20,\n};\n\nenum thermal_genl_multicast_groups {\n\tTHERMAL_GENL_SAMPLING_GROUP = 0,\n\tTHERMAL_GENL_EVENT_GROUP = 1,\n\tTHERMAL_GENL_MAX_GROUP = 1,\n};\n\nenum thermal_genl_sampling {\n\tTHERMAL_GENL_SAMPLING_TEMP = 0,\n\t__THERMAL_GENL_SAMPLING_MAX = 1,\n};\n\nenum thermal_notify_event {\n\tTHERMAL_EVENT_UNSPECIFIED = 0,\n\tTHERMAL_EVENT_TEMP_SAMPLE = 1,\n\tTHERMAL_TRIP_VIOLATED = 2,\n\tTHERMAL_TRIP_CHANGED = 3,\n\tTHERMAL_DEVICE_DOWN = 4,\n\tTHERMAL_DEVICE_UP = 5,\n\tTHERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6,\n\tTHERMAL_TABLE_CHANGED = 7,\n\tTHERMAL_EVENT_KEEP_ALIVE = 8,\n\tTHERMAL_TZ_BIND_CDEV = 9,\n\tTHERMAL_TZ_UNBIND_CDEV = 10,\n\tTHERMAL_INSTANCE_WEIGHT_CHANGED = 11,\n\tTHERMAL_TZ_RESUME = 12,\n\tTHERMAL_TZ_ADD_THRESHOLD = 13,\n\tTHERMAL_TZ_DEL_THRESHOLD = 14,\n\tTHERMAL_TZ_FLUSH_THRESHOLDS = 15,\n};\n\nenum thermal_trend {\n\tTHERMAL_TREND_STABLE = 0,\n\tTHERMAL_TREND_RAISING = 1,\n\tTHERMAL_TREND_DROPPING = 2,\n};\n\nenum thermal_trip_type {\n\tTHERMAL_TRIP_ACTIVE = 0,\n\tTHERMAL_TRIP_PASSIVE = 1,\n\tTHERMAL_TRIP_HOT = 2,\n\tTHERMAL_TRIP_CRITICAL = 3,\n};\n\nenum tick_broadcast_mode {\n\tTICK_BROADCAST_OFF = 0,\n\tTICK_BROADCAST_ON = 1,\n\tTICK_BROADCAST_FORCE = 2,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPERS_MAX = 1,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timer_tread_format {\n\tTREAD_FORMAT_NONE = 0,\n\tTREAD_FORMAT_TIME64 = 1,\n\tTREAD_FORMAT_TIME32 = 2,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum tlb_flush_reason {\n\tTLB_FLUSH_ON_TASK_SWITCH = 0,\n\tTLB_REMOTE_SHOOTDOWN = 1,\n\tTLB_LOCAL_SHOOTDOWN = 2,\n\tTLB_LOCAL_MM_SHOOTDOWN = 3,\n\tTLB_REMOTE_SEND_IPI = 4,\n\tTLB_REMOTE_WRONG_CPU = 5,\n};\n\nenum topo_types {\n\tINVALID_TYPE = 0,\n\tSMT_TYPE = 1,\n\tCORE_TYPE = 2,\n\tMAX_TYPE_0B = 3,\n\tMODULE_TYPE = 3,\n\tAMD_CCD_TYPE = 3,\n\tTILE_TYPE = 4,\n\tAMD_SOCKET_TYPE = 4,\n\tMAX_TYPE_80000026 = 5,\n\tDIE_TYPE = 5,\n\tDIEGRP_TYPE = 6,\n\tMAX_TYPE_1F = 7,\n};\n\nenum tp_func_state {\n\tTP_FUNC_0 = 0,\n\tTP_FUNC_1 = 1,\n\tTP_FUNC_2 = 2,\n\tTP_FUNC_N = 3,\n};\n\nenum tp_transition_sync {\n\tTP_TRANSITION_SYNC_1_0_1 = 0,\n\tTP_TRANSITION_SYNC_N_2_1 = 1,\n\t_NR_TP_TRANSITION_SYNC = 2,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_NEED_RESCHED_LAZY = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n\tTRACE_FLAG_BH_OFF = 128,\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n\tTRACE_FILE_PAUSE = 8,\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_FIELDS_BIT = 8,\n\tTRACE_ITER_PRINTK_BIT = 9,\n\tTRACE_ITER_ANNOTATE_BIT = 10,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 11,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 12,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 13,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 14,\n\tTRACE_ITER_LATENCY_FMT_BIT = 15,\n\tTRACE_ITER_RECORD_CMD_BIT = 16,\n\tTRACE_ITER_RECORD_TGID_BIT = 17,\n\tTRACE_ITER_OVERWRITE_BIT = 18,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 19,\n\tTRACE_ITER_IRQ_INFO_BIT = 20,\n\tTRACE_ITER_MARKERS_BIT = 21,\n\tTRACE_ITER_EVENT_FORK_BIT = 22,\n\tTRACE_ITER_TRACE_PRINTK_BIT = 23,\n\tTRACE_ITER_COPY_MARKER_BIT = 24,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 25,\n\tTRACE_ITER_HASH_PTR_BIT = 26,\n\tTRACE_ITER_BITMASK_LIST_BIT = 27,\n\tTRACE_ITER_FUNCTION_BIT = 28,\n\tTRACE_ITER_FUNC_FORK_BIT = 29,\n\tTRACE_ITER_DISPLAY_GRAPH_BIT = 30,\n\tTRACE_ITER_STACKTRACE_BIT = 31,\n\tTRACE_ITER_LAST_BIT = 32,\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_GRAPH_RETADDR_ENT = 12,\n\tTRACE_USER_STACK = 13,\n\tTRACE_BLK = 14,\n\tTRACE_BPUTS = 15,\n\tTRACE_HWLAT = 16,\n\tTRACE_OSNOISE = 17,\n\tTRACE_TIMERLAT = 18,\n\tTRACE_RAW_DATA = 19,\n\tTRACE_FUNC_REPEATS = 20,\n\t__TRACE_LAST_TYPE = 21,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum transcoder {\n\tINVALID_TRANSCODER = -1,\n\tTRANSCODER_A = 0,\n\tTRANSCODER_B = 1,\n\tTRANSCODER_C = 2,\n\tTRANSCODER_D = 3,\n\tTRANSCODER_EDP = 4,\n\tTRANSCODER_DSI_0 = 5,\n\tTRANSCODER_DSI_1 = 6,\n\tTRANSCODER_DSI_A = 5,\n\tTRANSCODER_DSI_C = 6,\n\tI915_MAX_TRANSCODERS = 7,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum tsa_mitigations {\n\tTSA_MITIGATION_NONE = 0,\n\tTSA_MITIGATION_AUTO = 1,\n\tTSA_MITIGATION_UCODE_NEEDED = 2,\n\tTSA_MITIGATION_USER_KERNEL = 3,\n\tTSA_MITIGATION_VM = 4,\n\tTSA_MITIGATION_FULL = 5,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum tsx_ctrl_states {\n\tTSX_CTRL_AUTO = 0,\n\tTSX_CTRL_ENABLE = 1,\n\tTSX_CTRL_DISABLE = 2,\n\tTSX_CTRL_RTM_ALWAYS_ABORT = 3,\n\tTSX_CTRL_NOT_SUPPORTED = 4,\n};\n\nenum ttm_bo_type {\n\tttm_bo_type_device = 0,\n\tttm_bo_type_kernel = 1,\n\tttm_bo_type_sg = 2,\n};\n\nenum ttm_caching {\n\tttm_uncached = 0,\n\tttm_write_combined = 1,\n\tttm_cached = 2,\n};\n\nenum ttm_lru_item_type {\n\tTTM_LRU_RESOURCE = 0,\n\tTTM_LRU_HITCH = 1,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum uart_iotype {\n\tUPIO_UNKNOWN = -1,\n\tUPIO_PORT = 0,\n\tUPIO_HUB6 = 1,\n\tUPIO_MEM = 2,\n\tUPIO_MEM32 = 3,\n\tUPIO_AU = 4,\n\tUPIO_TSI = 5,\n\tUPIO_MEM32BE = 6,\n\tUPIO_MEM16 = 7,\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucode_state {\n\tUCODE_OK = 0,\n\tUCODE_NEW = 1,\n\tUCODE_NEW_SAFE = 2,\n\tUCODE_UPDATED = 3,\n\tUCODE_NFOUND = 4,\n\tUCODE_ERROR = 5,\n\tUCODE_TIMEOUT = 6,\n\tUCODE_OFFLINE = 7,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_COUNTS = 10,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum uncore_access_type {\n\tUNCORE_ACCESS_MSR = 0,\n\tUNCORE_ACCESS_MMIO = 1,\n\tUNCORE_ACCESS_PCI = 2,\n\tUNCORE_ACCESS_MAX = 3,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_user_type {\n\tUNWIND_USER_TYPE_NONE = 0,\n\tUNWIND_USER_TYPE_FP = 1,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum uv_system_type {\n\tUV_NONE = 0,\n\tUV_LEGACY_APIC = 1,\n\tUV_X2APIC = 2,\n};\n\nenum v4l2_av1_segment_feature {\n\tV4L2_AV1_SEG_LVL_ALT_Q = 0,\n\tV4L2_AV1_SEG_LVL_ALT_LF_Y_V = 1,\n\tV4L2_AV1_SEG_LVL_REF_FRAME = 5,\n\tV4L2_AV1_SEG_LVL_REF_SKIP = 6,\n\tV4L2_AV1_SEG_LVL_REF_GLOBALMV = 7,\n\tV4L2_AV1_SEG_LVL_MAX = 8,\n};\n\nenum v4l2_fwnode_bus_type {\n\tV4L2_FWNODE_BUS_TYPE_GUESS = 0,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_CPHY = 1,\n\tV4L2_FWNODE_BUS_TYPE_CSI1 = 2,\n\tV4L2_FWNODE_BUS_TYPE_CCP2 = 3,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_DPHY = 4,\n\tV4L2_FWNODE_BUS_TYPE_PARALLEL = 5,\n\tV4L2_FWNODE_BUS_TYPE_BT656 = 6,\n\tV4L2_FWNODE_BUS_TYPE_DPI = 7,\n\tNR_OF_V4L2_FWNODE_BUS_TYPE = 8,\n};\n\nenum v4l2_preemphasis {\n\tV4L2_PREEMPHASIS_DISABLED = 0,\n\tV4L2_PREEMPHASIS_50_uS = 1,\n\tV4L2_PREEMPHASIS_75_uS = 2,\n};\n\nenum vbt_gmbus_ddi {\n\tDDC_BUS_DDI_B = 1,\n\tDDC_BUS_DDI_C = 2,\n\tDDC_BUS_DDI_D = 3,\n\tDDC_BUS_DDI_F = 4,\n\tICL_DDC_BUS_DDI_A = 1,\n\tICL_DDC_BUS_DDI_B = 2,\n\tTGL_DDC_BUS_DDI_C = 3,\n\tRKL_DDC_BUS_DDI_D = 3,\n\tRKL_DDC_BUS_DDI_E = 4,\n\tICL_DDC_BUS_PORT_1 = 4,\n\tICL_DDC_BUS_PORT_2 = 5,\n\tICL_DDC_BUS_PORT_3 = 6,\n\tICL_DDC_BUS_PORT_4 = 7,\n\tTGL_DDC_BUS_PORT_5 = 8,\n\tTGL_DDC_BUS_PORT_6 = 9,\n\tADLS_DDC_BUS_PORT_TC1 = 2,\n\tADLS_DDC_BUS_PORT_TC2 = 3,\n\tADLS_DDC_BUS_PORT_TC3 = 4,\n\tADLS_DDC_BUS_PORT_TC4 = 5,\n\tADLP_DDC_BUS_PORT_TC1 = 3,\n\tADLP_DDC_BUS_PORT_TC2 = 4,\n\tADLP_DDC_BUS_PORT_TC3 = 5,\n\tADLP_DDC_BUS_PORT_TC4 = 6,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_TSC = 1,\n\tVDSO_CLOCKMODE_PVCLOCK = 2,\n\tVDSO_CLOCKMODE_HVCLOCK = 3,\n\tVDSO_CLOCKMODE_MAX = 4,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum vga_switcheroo_client_id {\n\tVGA_SWITCHEROO_UNKNOWN_ID = 4096,\n\tVGA_SWITCHEROO_IGD = 0,\n\tVGA_SWITCHEROO_DIS = 1,\n\tVGA_SWITCHEROO_MAX_CLIENTS = 2,\n};\n\nenum vga_switcheroo_handler_flags_t {\n\tVGA_SWITCHEROO_CAN_SWITCH_DDC = 1,\n\tVGA_SWITCHEROO_NEEDS_EDP_CONFIG = 2,\n};\n\nenum vga_switcheroo_state {\n\tVGA_SWITCHEROO_OFF = 0,\n\tVGA_SWITCHEROO_ON = 1,\n\tVGA_SWITCHEROO_NOT_FOUND = 2,\n};\n\nenum vgt_g2v_type {\n\tVGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,\n\tVGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY = 3,\n\tVGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE = 4,\n\tVGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY = 5,\n\tVGT_G2V_EXECLIST_CONTEXT_CREATE = 6,\n\tVGT_G2V_EXECLIST_CONTEXT_DESTROY = 7,\n\tVGT_G2V_MAX = 8,\n};\n\nenum vhost_task_flags {\n\tVHOST_TASK_FLAGS_STOP = 0,\n\tVHOST_TASK_FLAGS_KILLED = 1,\n};\n\nenum virtio_balloon_config_read {\n\tVIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0,\n};\n\nenum virtio_balloon_vq {\n\tVIRTIO_BALLOON_VQ_INFLATE = 0,\n\tVIRTIO_BALLOON_VQ_DEFLATE = 1,\n\tVIRTIO_BALLOON_VQ_STATS = 2,\n\tVIRTIO_BALLOON_VQ_FREE_PAGE = 3,\n\tVIRTIO_BALLOON_VQ_REPORTING = 4,\n\tVIRTIO_BALLOON_VQ_MAX = 5,\n};\n\nenum virtio_gpu_ctrl_type {\n\tVIRTIO_GPU_UNDEFINED = 0,\n\tVIRTIO_GPU_CMD_GET_DISPLAY_INFO = 256,\n\tVIRTIO_GPU_CMD_RESOURCE_CREATE_2D = 257,\n\tVIRTIO_GPU_CMD_RESOURCE_UNREF = 258,\n\tVIRTIO_GPU_CMD_SET_SCANOUT = 259,\n\tVIRTIO_GPU_CMD_RESOURCE_FLUSH = 260,\n\tVIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D = 261,\n\tVIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING = 262,\n\tVIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING = 263,\n\tVIRTIO_GPU_CMD_GET_CAPSET_INFO = 264,\n\tVIRTIO_GPU_CMD_GET_CAPSET = 265,\n\tVIRTIO_GPU_CMD_GET_EDID = 266,\n\tVIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID = 267,\n\tVIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB = 268,\n\tVIRTIO_GPU_CMD_SET_SCANOUT_BLOB = 269,\n\tVIRTIO_GPU_CMD_CTX_CREATE = 512,\n\tVIRTIO_GPU_CMD_CTX_DESTROY = 513,\n\tVIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE = 514,\n\tVIRTIO_GPU_CMD_CTX_DETACH_RESOURCE = 515,\n\tVIRTIO_GPU_CMD_RESOURCE_CREATE_3D = 516,\n\tVIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D = 517,\n\tVIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D = 518,\n\tVIRTIO_GPU_CMD_SUBMIT_3D = 519,\n\tVIRTIO_GPU_CMD_RESOURCE_MAP_BLOB = 520,\n\tVIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB = 521,\n\tVIRTIO_GPU_CMD_UPDATE_CURSOR = 768,\n\tVIRTIO_GPU_CMD_MOVE_CURSOR = 769,\n\tVIRTIO_GPU_RESP_OK_NODATA = 4352,\n\tVIRTIO_GPU_RESP_OK_DISPLAY_INFO = 4353,\n\tVIRTIO_GPU_RESP_OK_CAPSET_INFO = 4354,\n\tVIRTIO_GPU_RESP_OK_CAPSET = 4355,\n\tVIRTIO_GPU_RESP_OK_EDID = 4356,\n\tVIRTIO_GPU_RESP_OK_RESOURCE_UUID = 4357,\n\tVIRTIO_GPU_RESP_OK_MAP_INFO = 4358,\n\tVIRTIO_GPU_RESP_ERR_UNSPEC = 4608,\n\tVIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY = 4609,\n\tVIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID = 4610,\n\tVIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID = 4611,\n\tVIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID = 4612,\n\tVIRTIO_GPU_RESP_ERR_INVALID_PARAMETER = 4613,\n};\n\nenum virtio_gpu_formats {\n\tVIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,\n\tVIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,\n\tVIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,\n\tVIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,\n\tVIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,\n\tVIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,\n\tVIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,\n\tVIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,\n};\n\nenum virtio_gpu_shm_id {\n\tVIRTIO_GPU_SHM_ID_UNDEFINED = 0,\n\tVIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1,\n};\n\nenum virtio_input_config_select {\n\tVIRTIO_INPUT_CFG_UNSET = 0,\n\tVIRTIO_INPUT_CFG_ID_NAME = 1,\n\tVIRTIO_INPUT_CFG_ID_SERIAL = 2,\n\tVIRTIO_INPUT_CFG_ID_DEVIDS = 3,\n\tVIRTIO_INPUT_CFG_PROP_BITS = 16,\n\tVIRTIO_INPUT_CFG_EV_BITS = 17,\n\tVIRTIO_INPUT_CFG_ABS_INFO = 18,\n};\n\nenum virtio_vsock_event_id {\n\tVIRTIO_VSOCK_EVENT_TRANSPORT_RESET = 0,\n};\n\nenum virtio_vsock_op {\n\tVIRTIO_VSOCK_OP_INVALID = 0,\n\tVIRTIO_VSOCK_OP_REQUEST = 1,\n\tVIRTIO_VSOCK_OP_RESPONSE = 2,\n\tVIRTIO_VSOCK_OP_RST = 3,\n\tVIRTIO_VSOCK_OP_SHUTDOWN = 4,\n\tVIRTIO_VSOCK_OP_RW = 5,\n\tVIRTIO_VSOCK_OP_CREDIT_UPDATE = 6,\n\tVIRTIO_VSOCK_OP_CREDIT_REQUEST = 7,\n};\n\nenum virtio_vsock_rw {\n\tVIRTIO_VSOCK_SEQ_EOM = 1,\n\tVIRTIO_VSOCK_SEQ_EOR = 2,\n};\n\nenum virtio_vsock_shutdown {\n\tVIRTIO_VSOCK_SHUTDOWN_RCV = 1,\n\tVIRTIO_VSOCK_SHUTDOWN_SEND = 2,\n};\n\nenum virtio_vsock_type {\n\tVIRTIO_VSOCK_TYPE_STREAM = 1,\n\tVIRTIO_VSOCK_TYPE_SEQPACKET = 2,\n};\n\nenum virtnet_xmit_type {\n\tVIRTNET_XMIT_TYPE_SKB = 0,\n\tVIRTNET_XMIT_TYPE_SKB_ORPHAN = 1,\n\tVIRTNET_XMIT_TYPE_XDP = 2,\n\tVIRTNET_XMIT_TYPE_XSK = 3,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vlv_iosf_sb_unit {\n\tVLV_IOSF_SB_BUNIT = 0,\n\tVLV_IOSF_SB_CCK = 1,\n\tVLV_IOSF_SB_CCU = 2,\n\tVLV_IOSF_SB_DPIO = 3,\n\tVLV_IOSF_SB_DPIO_2 = 4,\n\tVLV_IOSF_SB_FLISDSI = 5,\n\tVLV_IOSF_SB_GPIO = 6,\n\tVLV_IOSF_SB_NC = 7,\n\tVLV_IOSF_SB_PUNIT = 8,\n};\n\nenum vlv_wm_level {\n\tVLV_WM_LEVEL_PM2 = 0,\n\tVLV_WM_LEVEL_PM5 = 1,\n\tVLV_WM_LEVEL_DDR_DVFS = 2,\n\tNUM_VLV_WM_LEVELS = 3,\n};\n\nenum vm_entry_failure_code {\n\tENTRY_FAIL_DEFAULT = 0,\n\tENTRY_FAIL_PDPTE = 2,\n\tENTRY_FAIL_NMI = 3,\n\tENTRY_FAIL_VMCS_LINK_PTR = 4,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_DMA = 4,\n\tPGALLOC_DMA32 = 5,\n\tPGALLOC_NORMAL = 6,\n\tPGALLOC_MOVABLE = 7,\n\tPGALLOC_DEVICE = 8,\n\tALLOCSTALL_DMA = 9,\n\tALLOCSTALL_DMA32 = 10,\n\tALLOCSTALL_NORMAL = 11,\n\tALLOCSTALL_MOVABLE = 12,\n\tALLOCSTALL_DEVICE = 13,\n\tPGSCAN_SKIP_DMA = 14,\n\tPGSCAN_SKIP_DMA32 = 15,\n\tPGSCAN_SKIP_NORMAL = 16,\n\tPGSCAN_SKIP_MOVABLE = 17,\n\tPGSCAN_SKIP_DEVICE = 18,\n\tPGFREE = 19,\n\tPGACTIVATE = 20,\n\tPGDEACTIVATE = 21,\n\tPGLAZYFREE = 22,\n\tPGFAULT = 23,\n\tPGMAJFAULT = 24,\n\tPGLAZYFREED = 25,\n\tPGREFILL = 26,\n\tPGREUSE = 27,\n\tPGSTEAL_KSWAPD = 28,\n\tPGSTEAL_DIRECT = 29,\n\tPGSTEAL_KHUGEPAGED = 30,\n\tPGSTEAL_PROACTIVE = 31,\n\tPGSCAN_KSWAPD = 32,\n\tPGSCAN_DIRECT = 33,\n\tPGSCAN_KHUGEPAGED = 34,\n\tPGSCAN_PROACTIVE = 35,\n\tPGSCAN_DIRECT_THROTTLE = 36,\n\tPGSCAN_ANON = 37,\n\tPGSCAN_FILE = 38,\n\tPGSTEAL_ANON = 39,\n\tPGSTEAL_FILE = 40,\n\tPGSCAN_ZONE_RECLAIM_SUCCESS = 41,\n\tPGSCAN_ZONE_RECLAIM_FAILED = 42,\n\tPGINODESTEAL = 43,\n\tSLABS_SCANNED = 44,\n\tKSWAPD_INODESTEAL = 45,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 46,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 47,\n\tPAGEOUTRUN = 48,\n\tPGROTATED = 49,\n\tDROP_PAGECACHE = 50,\n\tDROP_SLAB = 51,\n\tOOM_KILL = 52,\n\tNUMA_PTE_UPDATES = 53,\n\tNUMA_HUGE_PTE_UPDATES = 54,\n\tNUMA_HINT_FAULTS = 55,\n\tNUMA_HINT_FAULTS_LOCAL = 56,\n\tNUMA_PAGE_MIGRATE = 57,\n\tPGMIGRATE_SUCCESS = 58,\n\tPGMIGRATE_FAIL = 59,\n\tTHP_MIGRATION_SUCCESS = 60,\n\tTHP_MIGRATION_FAIL = 61,\n\tTHP_MIGRATION_SPLIT = 62,\n\tCOMPACTMIGRATE_SCANNED = 63,\n\tCOMPACTFREE_SCANNED = 64,\n\tCOMPACTISOLATED = 65,\n\tCOMPACTSTALL = 66,\n\tCOMPACTFAIL = 67,\n\tCOMPACTSUCCESS = 68,\n\tKCOMPACTD_WAKE = 69,\n\tKCOMPACTD_MIGRATE_SCANNED = 70,\n\tKCOMPACTD_FREE_SCANNED = 71,\n\tHTLB_BUDDY_PGALLOC = 72,\n\tHTLB_BUDDY_PGALLOC_FAIL = 73,\n\tUNEVICTABLE_PGCULLED = 74,\n\tUNEVICTABLE_PGSCANNED = 75,\n\tUNEVICTABLE_PGRESCUED = 76,\n\tUNEVICTABLE_PGMLOCKED = 77,\n\tUNEVICTABLE_PGMUNLOCKED = 78,\n\tUNEVICTABLE_PGCLEARED = 79,\n\tUNEVICTABLE_PGSTRANDED = 80,\n\tBALLOON_INFLATE = 81,\n\tBALLOON_DEFLATE = 82,\n\tBALLOON_MIGRATE = 83,\n\tSWAP_RA = 84,\n\tSWAP_RA_HIT = 85,\n\tSWPIN_ZERO = 86,\n\tSWPOUT_ZERO = 87,\n\tDIRECT_MAP_LEVEL2_SPLIT = 88,\n\tDIRECT_MAP_LEVEL3_SPLIT = 89,\n\tDIRECT_MAP_LEVEL2_COLLAPSE = 90,\n\tDIRECT_MAP_LEVEL3_COLLAPSE = 91,\n\tKSTACK_1K = 92,\n\tKSTACK_2K = 93,\n\tKSTACK_4K = 94,\n\tKSTACK_8K = 95,\n\tKSTACK_16K = 96,\n\tNR_VM_EVENT_ITEMS = 97,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_instruction_error_number {\n\tVMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,\n\tVMXERR_VMCLEAR_INVALID_ADDRESS = 2,\n\tVMXERR_VMCLEAR_VMXON_POINTER = 3,\n\tVMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,\n\tVMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,\n\tVMXERR_VMRESUME_AFTER_VMXOFF = 6,\n\tVMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,\n\tVMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,\n\tVMXERR_VMPTRLD_INVALID_ADDRESS = 9,\n\tVMXERR_VMPTRLD_VMXON_POINTER = 10,\n\tVMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,\n\tVMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,\n\tVMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,\n\tVMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,\n\tVMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,\n\tVMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,\n\tVMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,\n\tVMXERR_VMCALL_NONCLEAR_VMCS = 19,\n\tVMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,\n\tVMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,\n\tVMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,\n\tVMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,\n\tVMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,\n\tVMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,\n\tVMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vma_resv_mode {\n\tVMA_NEEDS_RESV = 0,\n\tVMA_COMMIT_RESV = 1,\n\tVMA_END_RESV = 2,\n\tVMA_ADD_RESV = 3,\n\tVMA_DEL_RESV = 4,\n};\n\nenum vmcs_field {\n\tVIRTUAL_PROCESSOR_ID = 0,\n\tPOSTED_INTR_NV = 2,\n\tLAST_PID_POINTER_INDEX = 8,\n\tGUEST_ES_SELECTOR = 2048,\n\tGUEST_CS_SELECTOR = 2050,\n\tGUEST_SS_SELECTOR = 2052,\n\tGUEST_DS_SELECTOR = 2054,\n\tGUEST_FS_SELECTOR = 2056,\n\tGUEST_GS_SELECTOR = 2058,\n\tGUEST_LDTR_SELECTOR = 2060,\n\tGUEST_TR_SELECTOR = 2062,\n\tGUEST_INTR_STATUS = 2064,\n\tGUEST_PML_INDEX = 2066,\n\tHOST_ES_SELECTOR = 3072,\n\tHOST_CS_SELECTOR = 3074,\n\tHOST_SS_SELECTOR = 3076,\n\tHOST_DS_SELECTOR = 3078,\n\tHOST_FS_SELECTOR = 3080,\n\tHOST_GS_SELECTOR = 3082,\n\tHOST_TR_SELECTOR = 3084,\n\tIO_BITMAP_A = 8192,\n\tIO_BITMAP_A_HIGH = 8193,\n\tIO_BITMAP_B = 8194,\n\tIO_BITMAP_B_HIGH = 8195,\n\tMSR_BITMAP = 8196,\n\tMSR_BITMAP_HIGH = 8197,\n\tVM_EXIT_MSR_STORE_ADDR = 8198,\n\tVM_EXIT_MSR_STORE_ADDR_HIGH = 8199,\n\tVM_EXIT_MSR_LOAD_ADDR = 8200,\n\tVM_EXIT_MSR_LOAD_ADDR_HIGH = 8201,\n\tVM_ENTRY_MSR_LOAD_ADDR = 8202,\n\tVM_ENTRY_MSR_LOAD_ADDR_HIGH = 8203,\n\tPML_ADDRESS = 8206,\n\tPML_ADDRESS_HIGH = 8207,\n\tTSC_OFFSET = 8208,\n\tTSC_OFFSET_HIGH = 8209,\n\tVIRTUAL_APIC_PAGE_ADDR = 8210,\n\tVIRTUAL_APIC_PAGE_ADDR_HIGH = 8211,\n\tAPIC_ACCESS_ADDR = 8212,\n\tAPIC_ACCESS_ADDR_HIGH = 8213,\n\tPOSTED_INTR_DESC_ADDR = 8214,\n\tPOSTED_INTR_DESC_ADDR_HIGH = 8215,\n\tVM_FUNCTION_CONTROL = 8216,\n\tVM_FUNCTION_CONTROL_HIGH = 8217,\n\tEPT_POINTER = 8218,\n\tEPT_POINTER_HIGH = 8219,\n\tEOI_EXIT_BITMAP0 = 8220,\n\tEOI_EXIT_BITMAP0_HIGH = 8221,\n\tEOI_EXIT_BITMAP1 = 8222,\n\tEOI_EXIT_BITMAP1_HIGH = 8223,\n\tEOI_EXIT_BITMAP2 = 8224,\n\tEOI_EXIT_BITMAP2_HIGH = 8225,\n\tEOI_EXIT_BITMAP3 = 8226,\n\tEOI_EXIT_BITMAP3_HIGH = 8227,\n\tEPTP_LIST_ADDRESS = 8228,\n\tEPTP_LIST_ADDRESS_HIGH = 8229,\n\tVMREAD_BITMAP = 8230,\n\tVMREAD_BITMAP_HIGH = 8231,\n\tVMWRITE_BITMAP = 8232,\n\tVMWRITE_BITMAP_HIGH = 8233,\n\tVE_INFORMATION_ADDRESS = 8234,\n\tVE_INFORMATION_ADDRESS_HIGH = 8235,\n\tXSS_EXIT_BITMAP = 8236,\n\tXSS_EXIT_BITMAP_HIGH = 8237,\n\tENCLS_EXITING_BITMAP = 8238,\n\tENCLS_EXITING_BITMAP_HIGH = 8239,\n\tTSC_MULTIPLIER = 8242,\n\tTSC_MULTIPLIER_HIGH = 8243,\n\tTERTIARY_VM_EXEC_CONTROL = 8244,\n\tTERTIARY_VM_EXEC_CONTROL_HIGH = 8245,\n\tSHARED_EPT_POINTER = 8252,\n\tPID_POINTER_TABLE = 8258,\n\tPID_POINTER_TABLE_HIGH = 8259,\n\tGUEST_PHYSICAL_ADDRESS = 9216,\n\tGUEST_PHYSICAL_ADDRESS_HIGH = 9217,\n\tVMCS_LINK_POINTER = 10240,\n\tVMCS_LINK_POINTER_HIGH = 10241,\n\tGUEST_IA32_DEBUGCTL = 10242,\n\tGUEST_IA32_DEBUGCTL_HIGH = 10243,\n\tGUEST_IA32_PAT = 10244,\n\tGUEST_IA32_PAT_HIGH = 10245,\n\tGUEST_IA32_EFER = 10246,\n\tGUEST_IA32_EFER_HIGH = 10247,\n\tGUEST_IA32_PERF_GLOBAL_CTRL = 10248,\n\tGUEST_IA32_PERF_GLOBAL_CTRL_HIGH = 10249,\n\tGUEST_PDPTR0 = 10250,\n\tGUEST_PDPTR0_HIGH = 10251,\n\tGUEST_PDPTR1 = 10252,\n\tGUEST_PDPTR1_HIGH = 10253,\n\tGUEST_PDPTR2 = 10254,\n\tGUEST_PDPTR2_HIGH = 10255,\n\tGUEST_PDPTR3 = 10256,\n\tGUEST_PDPTR3_HIGH = 10257,\n\tGUEST_BNDCFGS = 10258,\n\tGUEST_BNDCFGS_HIGH = 10259,\n\tGUEST_IA32_RTIT_CTL = 10260,\n\tGUEST_IA32_RTIT_CTL_HIGH = 10261,\n\tHOST_IA32_PAT = 11264,\n\tHOST_IA32_PAT_HIGH = 11265,\n\tHOST_IA32_EFER = 11266,\n\tHOST_IA32_EFER_HIGH = 11267,\n\tHOST_IA32_PERF_GLOBAL_CTRL = 11268,\n\tHOST_IA32_PERF_GLOBAL_CTRL_HIGH = 11269,\n\tPIN_BASED_VM_EXEC_CONTROL = 16384,\n\tCPU_BASED_VM_EXEC_CONTROL = 16386,\n\tEXCEPTION_BITMAP = 16388,\n\tPAGE_FAULT_ERROR_CODE_MASK = 16390,\n\tPAGE_FAULT_ERROR_CODE_MATCH = 16392,\n\tCR3_TARGET_COUNT = 16394,\n\tVM_EXIT_CONTROLS = 16396,\n\tVM_EXIT_MSR_STORE_COUNT = 16398,\n\tVM_EXIT_MSR_LOAD_COUNT = 16400,\n\tVM_ENTRY_CONTROLS = 16402,\n\tVM_ENTRY_MSR_LOAD_COUNT = 16404,\n\tVM_ENTRY_INTR_INFO_FIELD = 16406,\n\tVM_ENTRY_EXCEPTION_ERROR_CODE = 16408,\n\tVM_ENTRY_INSTRUCTION_LEN = 16410,\n\tTPR_THRESHOLD = 16412,\n\tSECONDARY_VM_EXEC_CONTROL = 16414,\n\tPLE_GAP = 16416,\n\tPLE_WINDOW = 16418,\n\tNOTIFY_WINDOW = 16420,\n\tVM_INSTRUCTION_ERROR = 17408,\n\tVM_EXIT_REASON = 17410,\n\tVM_EXIT_INTR_INFO = 17412,\n\tVM_EXIT_INTR_ERROR_CODE = 17414,\n\tIDT_VECTORING_INFO_FIELD = 17416,\n\tIDT_VECTORING_ERROR_CODE = 17418,\n\tVM_EXIT_INSTRUCTION_LEN = 17420,\n\tVMX_INSTRUCTION_INFO = 17422,\n\tGUEST_ES_LIMIT = 18432,\n\tGUEST_CS_LIMIT = 18434,\n\tGUEST_SS_LIMIT = 18436,\n\tGUEST_DS_LIMIT = 18438,\n\tGUEST_FS_LIMIT = 18440,\n\tGUEST_GS_LIMIT = 18442,\n\tGUEST_LDTR_LIMIT = 18444,\n\tGUEST_TR_LIMIT = 18446,\n\tGUEST_GDTR_LIMIT = 18448,\n\tGUEST_IDTR_LIMIT = 18450,\n\tGUEST_ES_AR_BYTES = 18452,\n\tGUEST_CS_AR_BYTES = 18454,\n\tGUEST_SS_AR_BYTES = 18456,\n\tGUEST_DS_AR_BYTES = 18458,\n\tGUEST_FS_AR_BYTES = 18460,\n\tGUEST_GS_AR_BYTES = 18462,\n\tGUEST_LDTR_AR_BYTES = 18464,\n\tGUEST_TR_AR_BYTES = 18466,\n\tGUEST_INTERRUPTIBILITY_INFO = 18468,\n\tGUEST_ACTIVITY_STATE = 18470,\n\tGUEST_SYSENTER_CS = 18474,\n\tVMX_PREEMPTION_TIMER_VALUE = 18478,\n\tHOST_IA32_SYSENTER_CS = 19456,\n\tCR0_GUEST_HOST_MASK = 24576,\n\tCR4_GUEST_HOST_MASK = 24578,\n\tCR0_READ_SHADOW = 24580,\n\tCR4_READ_SHADOW = 24582,\n\tCR3_TARGET_VALUE0 = 24584,\n\tCR3_TARGET_VALUE1 = 24586,\n\tCR3_TARGET_VALUE2 = 24588,\n\tCR3_TARGET_VALUE3 = 24590,\n\tEXIT_QUALIFICATION = 25600,\n\tGUEST_LINEAR_ADDRESS = 25610,\n\tGUEST_CR0 = 26624,\n\tGUEST_CR3 = 26626,\n\tGUEST_CR4 = 26628,\n\tGUEST_ES_BASE = 26630,\n\tGUEST_CS_BASE = 26632,\n\tGUEST_SS_BASE = 26634,\n\tGUEST_DS_BASE = 26636,\n\tGUEST_FS_BASE = 26638,\n\tGUEST_GS_BASE = 26640,\n\tGUEST_LDTR_BASE = 26642,\n\tGUEST_TR_BASE = 26644,\n\tGUEST_GDTR_BASE = 26646,\n\tGUEST_IDTR_BASE = 26648,\n\tGUEST_DR7 = 26650,\n\tGUEST_RSP = 26652,\n\tGUEST_RIP = 26654,\n\tGUEST_RFLAGS = 26656,\n\tGUEST_PENDING_DBG_EXCEPTIONS = 26658,\n\tGUEST_SYSENTER_ESP = 26660,\n\tGUEST_SYSENTER_EIP = 26662,\n\tGUEST_S_CET = 26664,\n\tGUEST_SSP = 26666,\n\tGUEST_INTR_SSP_TABLE = 26668,\n\tHOST_CR0 = 27648,\n\tHOST_CR3 = 27650,\n\tHOST_CR4 = 27652,\n\tHOST_FS_BASE = 27654,\n\tHOST_GS_BASE = 27656,\n\tHOST_TR_BASE = 27658,\n\tHOST_GDTR_BASE = 27660,\n\tHOST_IDTR_BASE = 27662,\n\tHOST_IA32_SYSENTER_ESP = 27664,\n\tHOST_IA32_SYSENTER_EIP = 27666,\n\tHOST_RSP = 27668,\n\tHOST_RIP = 27670,\n\tHOST_S_CET = 27672,\n\tHOST_SSP = 27674,\n\tHOST_INTR_SSP_TABLE = 27676,\n};\n\nenum vmcs_field_width {\n\tVMCS_FIELD_WIDTH_U16 = 0,\n\tVMCS_FIELD_WIDTH_U64 = 1,\n\tVMCS_FIELD_WIDTH_U32 = 2,\n\tVMCS_FIELD_WIDTH_NATURAL_WIDTH = 3,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum vmscape_mitigations {\n\tVMSCAPE_MITIGATION_NONE = 0,\n\tVMSCAPE_MITIGATION_AUTO = 1,\n\tVMSCAPE_MITIGATION_IBPB_EXIT_TO_USER = 2,\n\tVMSCAPE_MITIGATION_IBPB_ON_VMEXIT = 3,\n};\n\nenum vmx_feature_leafs {\n\tMISC_FEATURES = 0,\n\tPRIMARY_CTLS = 1,\n\tSECONDARY_CTLS = 2,\n\tTERTIARY_CTLS_LOW = 3,\n\tTERTIARY_CTLS_HIGH = 4,\n\tNR_VMX_FEATURE_WORDS = 5,\n};\n\nenum vmx_l1d_flush_state {\n\tVMENTER_L1D_FLUSH_AUTO = 0,\n\tVMENTER_L1D_FLUSH_NEVER = 1,\n\tVMENTER_L1D_FLUSH_COND = 2,\n\tVMENTER_L1D_FLUSH_ALWAYS = 3,\n\tVMENTER_L1D_FLUSH_EPT_DISABLED = 4,\n\tVMENTER_L1D_FLUSH_NOT_REQUIRED = 5,\n};\n\nenum vp_vq_vector_policy {\n\tVP_VQ_VECTOR_POLICY_EACH = 0,\n\tVP_VQ_VECTOR_POLICY_SHARED_SLOW = 1,\n\tVP_VQ_VECTOR_POLICY_SHARED = 2,\n};\n\nenum vq_layout {\n\tVQ_LAYOUT_SPLIT = 0,\n\tVQ_LAYOUT_PACKED = 1,\n\tVQ_LAYOUT_SPLIT_IN_ORDER = 2,\n\tVQ_LAYOUT_PACKED_IN_ORDER = 3,\n};\n\nenum vsock_net_mode {\n\tVSOCK_NET_MODE_GLOBAL = 0,\n\tVSOCK_NET_MODE_LOCAL = 1,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum wd_read_status {\n\tWD_READ_SUCCESS = 0,\n\tWD_READ_UNSTABLE = 1,\n\tWD_READ_SKIP = 2,\n};\n\nenum which_selector {\n\tFS = 0,\n\tGS = 1,\n};\n\nenum wmi_brightness_method {\n\tWMI_BRIGHTNESS_METHOD_LEVEL = 1,\n\tWMI_BRIGHTNESS_METHOD_SOURCE = 2,\n\tWMI_BRIGHTNESS_METHOD_MAX = 3,\n};\n\nenum wmi_brightness_mode {\n\tWMI_BRIGHTNESS_MODE_GET = 0,\n\tWMI_BRIGHTNESS_MODE_SET = 1,\n\tWMI_BRIGHTNESS_MODE_GET_MAX_LEVEL = 2,\n\tWMI_BRIGHTNESS_MODE_MAX = 3,\n};\n\nenum wmi_brightness_source {\n\tWMI_BRIGHTNESS_SOURCE_GPU = 1,\n\tWMI_BRIGHTNESS_SOURCE_EC = 2,\n\tWMI_BRIGHTNESS_SOURCE_AUX = 3,\n\tWMI_BRIGHTNESS_SOURCE_MAX = 4,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 43,\n\tWORK_OFFQ_POOL_BITS = 31,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 300000,\n\tMAYDAY_INITIAL_TIMEOUT = 10,\n\tMAYDAY_INTERVAL = 100,\n\tCREATE_COOLDOWN = 1000,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 64,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum x509_actions {\n\tACT_x509_extract_key_data = 0,\n\tACT_x509_extract_name_segment = 1,\n\tACT_x509_note_OID = 2,\n\tACT_x509_note_issuer = 3,\n\tACT_x509_note_not_after = 4,\n\tACT_x509_note_not_before = 5,\n\tACT_x509_note_params = 6,\n\tACT_x509_note_serial = 7,\n\tACT_x509_note_sig_algo = 8,\n\tACT_x509_note_signature = 9,\n\tACT_x509_note_subject = 10,\n\tACT_x509_note_tbs_certificate = 11,\n\tACT_x509_process_extension = 12,\n\tNR__x509_actions = 13,\n};\n\nenum x509_akid_actions {\n\tACT_x509_akid_note_kid = 0,\n\tACT_x509_akid_note_name = 1,\n\tACT_x509_akid_note_serial = 2,\n\tACT_x509_extract_name_segment___2 = 3,\n\tACT_x509_note_OID___2 = 4,\n\tNR__x509_akid_actions = 5,\n};\n\nenum x86_hardware_subarch {\n\tX86_SUBARCH_PC = 0,\n\tX86_SUBARCH_LGUEST = 1,\n\tX86_SUBARCH_XEN = 2,\n\tX86_SUBARCH_INTEL_MID = 3,\n\tX86_SUBARCH_CE4100 = 4,\n\tX86_NR_SUBARCHS = 5,\n};\n\nenum x86_hypervisor_type {\n\tX86_HYPER_NATIVE = 0,\n\tX86_HYPER_VMWARE = 1,\n\tX86_HYPER_MS_HYPERV = 2,\n\tX86_HYPER_XEN_PV = 3,\n\tX86_HYPER_XEN_HVM = 4,\n\tX86_HYPER_KVM = 5,\n\tX86_HYPER_JAILHOUSE = 6,\n\tX86_HYPER_ACRN = 7,\n\tX86_HYPER_BHYVE = 8,\n};\n\nenum x86_intercept {\n\tx86_intercept_none = 0,\n\tx86_intercept_cr_read = 1,\n\tx86_intercept_cr_write = 2,\n\tx86_intercept_clts = 3,\n\tx86_intercept_lmsw = 4,\n\tx86_intercept_smsw = 5,\n\tx86_intercept_dr_read = 6,\n\tx86_intercept_dr_write = 7,\n\tx86_intercept_lidt = 8,\n\tx86_intercept_sidt = 9,\n\tx86_intercept_lgdt = 10,\n\tx86_intercept_sgdt = 11,\n\tx86_intercept_lldt = 12,\n\tx86_intercept_sldt = 13,\n\tx86_intercept_ltr = 14,\n\tx86_intercept_str = 15,\n\tx86_intercept_rdtsc = 16,\n\tx86_intercept_rdpmc = 17,\n\tx86_intercept_pushf = 18,\n\tx86_intercept_popf = 19,\n\tx86_intercept_cpuid = 20,\n\tx86_intercept_rsm = 21,\n\tx86_intercept_iret = 22,\n\tx86_intercept_intn = 23,\n\tx86_intercept_invd = 24,\n\tx86_intercept_pause = 25,\n\tx86_intercept_hlt = 26,\n\tx86_intercept_invlpg = 27,\n\tx86_intercept_invlpga = 28,\n\tx86_intercept_vmrun = 29,\n\tx86_intercept_vmload = 30,\n\tx86_intercept_vmsave = 31,\n\tx86_intercept_vmmcall = 32,\n\tx86_intercept_stgi = 33,\n\tx86_intercept_clgi = 34,\n\tx86_intercept_skinit = 35,\n\tx86_intercept_rdtscp = 36,\n\tx86_intercept_rdpid = 37,\n\tx86_intercept_icebp = 38,\n\tx86_intercept_wbinvd = 39,\n\tx86_intercept_monitor = 40,\n\tx86_intercept_mwait = 41,\n\tx86_intercept_rdmsr = 42,\n\tx86_intercept_wrmsr = 43,\n\tx86_intercept_in = 44,\n\tx86_intercept_ins = 45,\n\tx86_intercept_out = 46,\n\tx86_intercept_outs = 47,\n\tx86_intercept_xsetbv = 48,\n\tnr_x86_intercepts = 49,\n};\n\nenum x86_intercept_stage {\n\tX86_ICTP_NONE = 0,\n\tX86_ICPT_PRE_EXCEPT = 1,\n\tX86_ICPT_POST_EXCEPT = 2,\n\tX86_ICPT_POST_MEMACCESS = 3,\n};\n\nenum x86_legacy_i8042_state {\n\tX86_LEGACY_I8042_PLATFORM_ABSENT = 0,\n\tX86_LEGACY_I8042_FIRMWARE_ABSENT = 1,\n\tX86_LEGACY_I8042_EXPECTED_PRESENT = 2,\n};\n\nenum x86_pf_error_code {\n\tX86_PF_PROT = 1,\n\tX86_PF_WRITE = 2,\n\tX86_PF_USER = 4,\n\tX86_PF_RSVD = 8,\n\tX86_PF_INSTR = 16,\n\tX86_PF_PK = 32,\n\tX86_PF_SHSTK = 64,\n\tX86_PF_SGX = 32768,\n\tX86_PF_RMP = 2147483648,\n};\n\nenum x86_regset_32 {\n\tREGSET32_GENERAL = 0,\n\tREGSET32_FP = 1,\n\tREGSET32_XFP = 2,\n\tREGSET32_XSTATE = 3,\n\tREGSET32_TLS = 4,\n\tREGSET32_IOPERM = 5,\n};\n\nenum x86_regset_64 {\n\tREGSET64_GENERAL = 0,\n\tREGSET64_FP = 1,\n\tREGSET64_IOPERM = 2,\n\tREGSET64_XSTATE = 3,\n\tREGSET64_SSP = 4,\n};\n\nenum x86_topology_cpu_type {\n\tTOPO_CPU_TYPE_PERFORMANCE = 0,\n\tTOPO_CPU_TYPE_EFFICIENCY = 1,\n\tTOPO_CPU_TYPE_UNKNOWN = 2,\n};\n\nenum x86_topology_domains {\n\tTOPO_SMT_DOMAIN = 0,\n\tTOPO_CORE_DOMAIN = 1,\n\tTOPO_MODULE_DOMAIN = 2,\n\tTOPO_TILE_DOMAIN = 3,\n\tTOPO_DIE_DOMAIN = 4,\n\tTOPO_DIEGRP_DOMAIN = 5,\n\tTOPO_PKG_DOMAIN = 6,\n\tTOPO_MAX_DOMAIN = 7,\n};\n\nenum x86_transfer_type {\n\tX86_TRANSFER_NONE = 0,\n\tX86_TRANSFER_CALL_JMP = 1,\n\tX86_TRANSFER_RET = 2,\n\tX86_TRANSFER_TASK_SWITCH = 3,\n};\n\nenum x86emul_mode {\n\tX86EMUL_MODE_REAL = 0,\n\tX86EMUL_MODE_VM86 = 1,\n\tX86EMUL_MODE_PROT16 = 2,\n\tX86EMUL_MODE_PROT32 = 3,\n\tX86EMUL_MODE_PROT64 = 4,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xfeature {\n\tXFEATURE_FP = 0,\n\tXFEATURE_SSE = 1,\n\tXFEATURE_YMM = 2,\n\tXFEATURE_BNDREGS = 3,\n\tXFEATURE_BNDCSR = 4,\n\tXFEATURE_OPMASK = 5,\n\tXFEATURE_ZMM_Hi256 = 6,\n\tXFEATURE_Hi16_ZMM = 7,\n\tXFEATURE_PT_UNIMPLEMENTED_SO_FAR = 8,\n\tXFEATURE_PKRU = 9,\n\tXFEATURE_PASID = 10,\n\tXFEATURE_CET_USER = 11,\n\tXFEATURE_CET_KERNEL = 12,\n\tXFEATURE_RSRVD_COMP_13 = 13,\n\tXFEATURE_RSRVD_COMP_14 = 14,\n\tXFEATURE_LBR = 15,\n\tXFEATURE_RSRVD_COMP_16 = 16,\n\tXFEATURE_XTILE_CFG = 17,\n\tXFEATURE_XTILE_DATA = 18,\n\tXFEATURE_APX = 19,\n\tXFEATURE_MAX = 20,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xstate_copy_mode {\n\tXSTATE_COPY_FP = 0,\n\tXSTATE_COPY_FX = 1,\n\tXSTATE_COPY_XSAVE = 2,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_FREE_CMA_PAGES = 9,\n\tNR_VM_ZONE_STAT_ITEMS = 10,\n};\n\nenum zone_type {\n\tZONE_DMA = 0,\n\tZONE_DMA32 = 1,\n\tZONE_NORMAL = 2,\n\tZONE_MOVABLE = 3,\n\tZONE_DEVICE = 4,\n\t__MAX_NR_ZONES = 5,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\ntypedef _Bool bool;\n\ntypedef __int128 unsigned __u128;\n\ntypedef __u128 u128;\n\ntypedef u128 freelist_full_t;\n\ntypedef char __pad_after_uframe[0];\n\ntypedef char __pad_before_u32[0];\n\ntypedef char __pad_before_uframe[0];\n\ntypedef char acpi_bus_id[8];\n\ntypedef char acpi_device_class[20];\n\ntypedef char acpi_device_name[40];\n\ntypedef char *acpi_string;\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_daddr_t;\n\ntypedef int __kernel_ipc_pid_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_mqd_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __s32;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef __s32 s32;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_daddr_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_key_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_off_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef s32 dma_cookie_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef int initcall_entry_t;\n\ntypedef int insn_value_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef int mhp_t;\n\ntypedef int mm_id_mapcount_t;\n\ntypedef int mpi_size_t;\n\ntypedef __kernel_mqd_t mqd_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef int snd_ctl_elem_iface_t;\n\ntypedef int snd_ctl_elem_type_t;\n\ntypedef int snd_pcm_access_t;\n\ntypedef int snd_pcm_format_t;\n\ntypedef int snd_pcm_hw_param_t;\n\ntypedef int snd_pcm_state_t;\n\ntypedef int snd_pcm_subformat_t;\n\ntypedef int snd_seq_client_type_t;\n\ntypedef int suspend_state_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef const int tracepoint_ptr_t;\n\ntypedef int vma_flag_t;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_long_t __kernel_ptrdiff_t;\n\ntypedef __kernel_long_t __kernel_ssize_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef long int mpi_limb_signed_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef long int snd_pcm_sframes_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 Elf64_Sxword;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef __s64 s64;\n\ntypedef s64 compat_loff_t;\n\ntypedef s64 int64_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef long long int qsize_t;\n\ntypedef __s64 time64_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef __u64 __virtio64;\n\ntypedef u64 acpi_bus_address;\n\ntypedef u64 acpi_integer;\n\ntypedef u64 acpi_io_address;\n\ntypedef u64 acpi_physical_address;\n\ntypedef u64 acpi_size;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 compat_u64;\n\ntypedef long long unsigned int cycles_t;\n\ntypedef u64 dma_addr_t;\n\ntypedef u64 gen8_pte_t;\n\ntypedef u64 gfn_t;\n\ntypedef u64 gpa_t;\n\ntypedef u64 hfn_t;\n\ntypedef u64 hpa_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef hfn_t kvm_pfn_t;\n\ntypedef u64 natural_width;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 pci_bus_addr_t;\n\ntypedef u64 phys_addr_t;\n\ntypedef u64 pt_oaddr_t;\n\ntypedef u64 pt_vaddr_t;\n\ntypedef u64 sector_t;\n\ntypedef sector_t region_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u64 sci_t;\n\ntypedef u64 *tdp_ptep_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef u64 u_int64_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef u64 upf_t;\n\ntypedef uint64_t vli_type;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef __kernel_ulong_t __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef long unsigned int mpi_limb_t;\n\ntypedef mpi_limb_t UWtype;\n\ntypedef long unsigned int __kernel_old_dev_t;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int dax_entry_t;\n\ntypedef long unsigned int efi_status_t;\n\ntypedef long unsigned int elf_greg_t;\n\ntypedef elf_greg_t elf_gregset_t[27];\n\ntypedef long unsigned int gva_t;\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int kimage_entry_t;\n\ntypedef long unsigned int mce_banks_t[1];\n\ntypedef mpi_limb_t *mpi_ptr_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int nsvm_msrpm_merge_t;\n\ntypedef long unsigned int old_sigset_t;\n\ntypedef long unsigned int p4dval_t;\n\ntypedef long unsigned int perf_trace_t[1024];\n\ntypedef long unsigned int pgdval_t;\n\ntypedef long unsigned int pgprotval_t;\n\ntypedef long unsigned int pmdval_t;\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int pteval_t;\n\ntypedef long unsigned int pudval_t;\n\ntypedef long unsigned int snd_pcm_uframes_t;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int u_long;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulg;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef short unsigned int ush;\n\ntypedef ush Pos;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef u16 __compat_gid_t;\n\ntypedef u16 __compat_uid_t;\n\ntypedef short unsigned int __kernel_old_gid_t;\n\ntypedef short unsigned int __kernel_old_uid_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef u16 acpi_owner_id;\n\ntypedef u16 acpi_rs_length;\n\ntypedef __u16 bitmap_counter_t;\n\ntypedef u16 blk_short_t;\n\ntypedef __u16 comp_t;\n\ntypedef u16 compat_dev_t;\n\ntypedef u16 compat_ipc_pid_t;\n\ntypedef u16 compat_mode_t;\n\ntypedef u16 compat_nlink_t;\n\ntypedef u16 compat_ushort_t;\n\ntypedef u16 efi_char16_t;\n\ntypedef u16 hda_nid_t;\n\ntypedef __kernel_old_gid_t old_gid_t;\n\ntypedef __kernel_old_uid_t old_uid_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef short unsigned int u_short;\n\ntypedef u16 ucs2_char_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef short unsigned int vifi_t;\n\ntypedef u16 wchar_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 acpi_adr_space_type;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef unsigned char cisdata_t;\n\ntypedef u8 dscp_t;\n\ntypedef u8 efi_bool_t;\n\ntypedef unsigned char insn_byte_t;\n\ntypedef u8 kprobe_opcode_t;\n\ntypedef __u8 mtrr_type;\n\ntypedef u8 retpoline_thunk_t[32];\n\ntypedef unsigned char snd_seq_event_type_t;\n\ntypedef unsigned char u8___2;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef unsigned char uch;\n\ntypedef u8 uprobe_opcode_t;\n\ntypedef __u8 virtio_net_ctrl_ack;\n\ntypedef unsigned int __u32;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef __u32 u32;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef unsigned int IPos;\n\ntypedef unsigned int UHWtype;\n\ntypedef __u32 __be32;\n\ntypedef u32 __compat_gid32_t;\n\ntypedef u32 __compat_uid32_t;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_gid_t;\n\ntypedef unsigned int __kernel_mode_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __virtio32;\n\ntypedef __u32 __wsum;\n\ntypedef u32 acpi_event_status;\n\ntypedef u32 acpi_mutex_handle;\n\ntypedef u32 acpi_name;\n\ntypedef u32 acpi_object_type;\n\ntypedef u32 acpi_rsdesc_size;\n\ntypedef u32 acpi_status;\n\ntypedef unsigned int acr_flags_t;\n\ntypedef unsigned int avx256_t[8];\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef __u32 comp2_t;\n\ntypedef u32 compat_aio_context_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_ino_t;\n\ntypedef u32 compat_old_sigset_t;\n\ntypedef u32 compat_sigset_word;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef u32 depot_flags_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef uint32_t drbg_flag_t;\n\ntypedef unsigned int drm_magic_t;\n\ntypedef u32 errseq_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef u32 gen6_pte_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef unsigned int insn_attr_t;\n\ntypedef u32 intel_engine_mask_t;\n\ntypedef unsigned int ioasid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef unsigned int mm_id_t;\n\ntypedef u32 nlink_t;\n\ntypedef u32 note_buf_t[92];\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef u32 phys_cpuid_t;\n\ntypedef unsigned int pipe_index_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef __kernel_uid32_t qid_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef unsigned int sk_buff_data_t;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int snd_seq_tick_time_t;\n\ntypedef unsigned int speed_t;\n\ntypedef unsigned int sse128_t[4];\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef u32 u_int32_t;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef unsigned int upstat_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct dentry;\n\nstruct file;\n\ntypedef struct {\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tint offset;\n\tint size;\n\tchar *magic;\n\tchar *mask;\n\tconst char *interpreter;\n\tchar *name;\n\tstruct dentry *dentry;\n\tstruct file *interp_file;\n\trefcount_t users;\n} Node;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef struct {\n\tU32 f1c;\n\tU32 f1d;\n\tU32 f7b;\n\tU32 f7c;\n} ZSTD_cpuid_t;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tlong unsigned int fds_bits[16];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef union {\n} aes_encrypt_arg;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef atomic64_t atomic_long_t;\n\ntypedef struct {\n\t__be64 a;\n\t__be64 b;\n} be128;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {\n\tunsigned int val;\n};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tint *lock;\n\tlong unsigned int flags;\n} class_core_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\traw_spinlock_t *lock2;\n} class_double_raw_spinlock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_jump_label_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_init_t;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\nstruct snd_pcm_substream;\n\ntypedef struct {\n\tstruct snd_pcm_substream *lock;\n} class_pcm_stream_lock_irq_t;\n\ntypedef struct {\n\tstruct snd_pcm_substream *lock;\n\tlong unsigned int flags;\n} class_pcm_stream_lock_irqsave_t;\n\nstruct perf_cpu_context;\n\nstruct perf_event_context;\n\ntypedef struct {\n\tstruct perf_cpu_context *cpuctx;\n\tstruct perf_event_context *ctx;\n} class_perf_ctx_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_notrace_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\nstruct srcu_ctr;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tstruct srcu_ctr *scp;\n} class_srcu_fast_notrace_t;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\nstruct uart_port;\n\ntypedef struct {\n\tstruct uart_port *lock;\n\tlong unsigned int flags;\n} class_uart_port_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_write_lock_irqsave_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef __kernel_fsid_t compat_fsid_t;\n\ntypedef struct {\n\tcompat_sigset_word sig[2];\n} compat_sigset_t;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 headersize;\n\tu32 flags;\n\tu32 imagesize;\n} efi_capsule_header_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 table;\n} efi_config_table_32_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu64 table;\n} efi_config_table_64_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_guid_t guid;\n\t\tvoid *table;\n\t};\n\tefi_config_table_32_t mixed_mode;\n} efi_config_table_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tlong unsigned int *ptr;\n\tconst char name[16];\n} efi_config_table_type_t;\n\ntypedef struct {\n\tu32 type;\n\tu32 pad;\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu64 num_pages;\n\tu64 attribute;\n} efi_memory_desc_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 num_entries;\n\tu32 desc_size;\n\tu32 flags;\n\tefi_memory_desc_t entry[0];\n} efi_memory_attributes_table_t;\n\ntypedef struct {\n\tu16 version;\n\tu16 length;\n\tu32 runtime_services_supported;\n} efi_rt_properties_table_t;\n\ntypedef struct {\n\tu64 signature;\n\tu32 revision;\n\tu32 headersize;\n\tu32 crc32;\n\tu32 reserved;\n} efi_table_hdr_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 get_time;\n\tu32 set_time;\n\tu32 get_wakeup_time;\n\tu32 set_wakeup_time;\n\tu32 set_virtual_address_map;\n\tu32 convert_pointer;\n\tu32 get_variable;\n\tu32 get_next_variable;\n\tu32 set_variable;\n\tu32 get_next_high_mono_count;\n\tu32 reset_system;\n\tu32 update_capsule;\n\tu32 query_capsule_caps;\n\tu32 query_variable_info;\n} efi_runtime_services_32_t;\n\ntypedef struct {\n\tu16 year;\n\tu8 month;\n\tu8 day;\n\tu8 hour;\n\tu8 minute;\n\tu8 second;\n\tu8 pad1;\n\tu32 nanosecond;\n\ts16 timezone;\n\tu8 daylight;\n\tu8 pad2;\n} efi_time_t;\n\ntypedef struct {\n\tu32 resolution;\n\tu32 accuracy;\n\tu8 sets_to_zero;\n} efi_time_cap_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tefi_status_t (*get_time)(efi_time_t *, efi_time_cap_t *);\n\t\tefi_status_t (*set_time)(efi_time_t *);\n\t\tefi_status_t (*get_wakeup_time)(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\t\tefi_status_t (*set_wakeup_time)(efi_bool_t, efi_time_t *);\n\t\tefi_status_t (*set_virtual_address_map)(long unsigned int, long unsigned int, u32, efi_memory_desc_t *);\n\t\tvoid *convert_pointer;\n\t\tefi_status_t (*get_variable)(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\t\tefi_status_t (*get_next_variable)(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\t\tefi_status_t (*set_variable)(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\t\tefi_status_t (*get_next_high_mono_count)(u32 *);\n\t\tvoid (*reset_system)(int, efi_status_t, long unsigned int, efi_char16_t *);\n\t\tefi_status_t (*update_capsule)(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\t\tefi_status_t (*query_capsule_caps)(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\t\tefi_status_t (*query_variable_info)(u32, u64 *, u64 *, u64 *);\n\t};\n\tefi_runtime_services_32_t mixed_mode;\n} efi_runtime_services_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 fw_vendor;\n\tu32 fw_revision;\n\tu32 con_in_handle;\n\tu32 con_in;\n\tu32 con_out_handle;\n\tu32 con_out;\n\tu32 stderr_handle;\n\tu32 stderr;\n\tu32 runtime;\n\tu32 boottime;\n\tu32 nr_tables;\n\tu32 tables;\n} efi_system_table_32_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu64 fw_vendor;\n\tu32 fw_revision;\n\tu32 __pad1;\n\tu64 con_in_handle;\n\tu64 con_in;\n\tu64 con_out_handle;\n\tu64 con_out;\n\tu64 stderr_handle;\n\tu64 stderr;\n\tu64 runtime;\n\tu64 boottime;\n\tu32 nr_tables;\n\tu32 __pad2;\n\tu64 tables;\n} efi_system_table_64_t;\n\nunion efi_simple_text_input_protocol;\n\ntypedef union efi_simple_text_input_protocol efi_simple_text_input_protocol_t;\n\nunion efi_simple_text_output_protocol;\n\ntypedef union efi_simple_text_output_protocol efi_simple_text_output_protocol_t;\n\nunion efi_boot_services;\n\ntypedef union efi_boot_services efi_boot_services_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tlong unsigned int fw_vendor;\n\t\tu32 fw_revision;\n\t\tlong unsigned int con_in_handle;\n\t\tefi_simple_text_input_protocol_t *con_in;\n\t\tlong unsigned int con_out_handle;\n\t\tefi_simple_text_output_protocol_t *con_out;\n\t\tlong unsigned int stderr_handle;\n\t\tlong unsigned int stderr;\n\t\tefi_runtime_services_t *runtime;\n\t\tefi_boot_services_t *boottime;\n\t\tlong unsigned int nr_tables;\n\t\tlong unsigned int tables;\n\t};\n\tefi_system_table_32_t mixed_mode;\n} efi_system_table_t;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic64_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tu32 reg;\n} i915_mcr_reg_t;\n\ntypedef struct {\n\tu32 reg;\n} i915_reg_t;\n\ntypedef union {\n\tu8 hsw[3];\n\tlong unsigned int xehp[1];\n} intel_sseu_ss_mask_t;\n\ntypedef struct {\n\tu8 kvm_cpu_l1tf_flush_l1d;\n\tunsigned int __nmi_count;\n\tunsigned int apic_timer_irqs;\n\tunsigned int irq_spurious_count;\n\tunsigned int icr_read_retry_count;\n\tunsigned int kvm_posted_intr_ipis;\n\tunsigned int kvm_posted_intr_wakeup_ipis;\n\tunsigned int kvm_posted_intr_nested_ipis;\n\tunsigned int perf_guest_mediated_pmis;\n\tunsigned int x86_platform_ipis;\n\tunsigned int apic_perf_irqs;\n\tunsigned int apic_irq_work_irqs;\n\tunsigned int irq_resched_count;\n\tunsigned int irq_call_count;\n\tunsigned int irq_tlb_count;\n\tunsigned int irq_thermal_count;\n\tunsigned int irq_threshold_count;\n\tunsigned int irq_deferred_error_count;\n\tunsigned int irq_hv_callback_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n} irq_cpustat_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\t__le64 b;\n\t__le64 a;\n} le128;\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef struct {\n\tlocal_t a;\n} local64_t;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct qspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tstruct {\n\t\t\tu8 locked;\n\t\t\tu8 pending;\n\t\t};\n\t\tstruct {\n\t\t\tu16 locked_pending;\n\t\t\tu16 tail;\n\t\t};\n\t};\n};\n\ntypedef struct qspinlock arch_spinlock_t;\n\nstruct lock_class_key;\n\nstruct lock_class;\n\nstruct lockdep_map {\n\tstruct lock_class_key *key;\n\tstruct lock_class *class_cache[2];\n\tconst char *name;\n\tu8 wait_type_outer;\n\tu8 wait_type_inner;\n\tu8 lock_type;\n};\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n\tunsigned int magic;\n\tunsigned int owner_cpu;\n\tvoid *owner;\n\tstruct lockdep_map dep_map;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n\tvoid *magic;\n\tstruct lockdep_map dep_map;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n\tvoid *magic;\n\tstruct lockdep_map dep_map;\n};\n\nstruct ldt_struct;\n\nstruct vdso_image;\n\ntypedef struct {\n\tu64 ctx_id;\n\tatomic64_t tlb_gen;\n\tlong unsigned int next_trim_cpumask;\n\tstruct rw_semaphore ldt_usr_sem;\n\tstruct ldt_struct *ldt;\n\tlong unsigned int flags;\n\tstruct mutex lock;\n\tvoid *vdso;\n\tconst struct vdso_image *vdso_image;\n\tatomic_t perf_rdpmc_allowed;\n\tu16 pkey_allocation_map;\n\ts16 execute_only_pkey;\n\tu16 global_asid;\n\tbool asid_transition;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[1];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\ntypedef struct {\n\tp4dval_t p4d;\n} p4d_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\ntypedef struct {\n\tpgdval_t pgd;\n} pgd_t;\n\ntypedef struct {\n\tpmdval_t pmd;\n} pmd_t;\n\ntypedef struct {\n\tlong unsigned int bits[4];\n} pnp_irq_mask_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tpteval_t pte;\n} pte_t;\n\ntypedef struct {\n\tpudval_t pud;\n} pud_t;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n\tstruct lockdep_map dep_map;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[1];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\ntypedef atomic_t snd_use_lock_t;\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t\tstruct {\n\t\t\tu8 __padding[24];\n\t\t\tstruct lockdep_map dep_map;\n\t\t};\n\t};\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n\tstruct lockdep_map dep_map;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\tlocal64_t v;\n} u64_stats_t;\n\ntypedef struct {\n\tu32 val;\n} uint_fixed_16_16_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_le;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\nunion IO_APIC_reg_00 {\n\tu32 raw;\n\tstruct {\n\t\tu32 __reserved_2: 14;\n\t\tu32 LTS: 1;\n\t\tu32 delivery_type: 1;\n\t\tu32 __reserved_1: 8;\n\t\tu32 ID: 8;\n\t} bits;\n};\n\nunion IO_APIC_reg_01 {\n\tu32 raw;\n\tstruct {\n\t\tu32 version: 8;\n\t\tu32 __reserved_2: 7;\n\t\tu32 PRQ: 1;\n\t\tu32 entries: 8;\n\t\tu32 __reserved_1: 8;\n\t} bits;\n};\n\nunion IO_APIC_reg_02 {\n\tu32 raw;\n\tstruct {\n\t\tu32 __reserved_2: 24;\n\t\tu32 arbitration: 4;\n\t\tu32 __reserved_1: 4;\n\t} bits;\n};\n\nunion IO_APIC_reg_03 {\n\tu32 raw;\n\tstruct {\n\t\tu32 boot_DT: 1;\n\t\tu32 __reserved_1: 31;\n\t} bits;\n};\n\nstruct IO_APIC_route_entry {\n\tunion {\n\t\tstruct {\n\t\t\tu64 vector: 8;\n\t\t\tu64 delivery_mode: 3;\n\t\t\tu64 dest_mode_logical: 1;\n\t\t\tu64 delivery_status: 1;\n\t\t\tu64 active_low: 1;\n\t\t\tu64 irr: 1;\n\t\t\tu64 is_level: 1;\n\t\t\tu64 masked: 1;\n\t\t\tu64 reserved_0: 15;\n\t\t\tu64 reserved_1: 17;\n\t\t\tu64 virt_destid_8_14: 7;\n\t\t\tu64 destid_0_7: 8;\n\t\t};\n\t\tstruct {\n\t\t\tu64 ir_shared_0: 8;\n\t\t\tu64 ir_zero: 3;\n\t\t\tu64 ir_index_15: 1;\n\t\t\tu64 ir_shared_1: 5;\n\t\t\tu64 ir_reserved_0: 31;\n\t\t\tu64 ir_format: 1;\n\t\t\tu64 ir_index_0_14: 15;\n\t\t};\n\t\tstruct {\n\t\t\tu64 w1: 32;\n\t\t\tu64 w2: 32;\n\t\t};\n\t};\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lockdep_subclass_key {\n\tchar __one_byte;\n};\n\nstruct lock_class_key {\n\tunion {\n\t\tstruct hlist_node hash_entry;\n\t\tstruct lockdep_subclass_key subkeys[8];\n\t};\n};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 64;\n\tlong: 64;\n\tlong int privdata[0];\n};\n\nstruct Qdisc_class_common {\n\tu32 classid;\n\tunsigned int filter_cnt;\n\tstruct hlist_node hnode;\n};\n\nstruct hlist_head;\n\nstruct Qdisc_class_hash {\n\tstruct hlist_head *hash;\n\tunsigned int hashsize;\n\tunsigned int hashmask;\n\tunsigned int hashelems;\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct RR_CL_s {\n\t__u8 location[8];\n};\n\nstruct RR_NM_s {\n\t__u8 flags;\n\tchar name[0];\n};\n\nstruct RR_PL_s {\n\t__u8 location[8];\n};\n\nstruct RR_PN_s {\n\t__u8 dev_high[8];\n\t__u8 dev_low[8];\n};\n\nstruct RR_PX_s {\n\t__u8 mode[8];\n\t__u8 n_links[8];\n\t__u8 uid[8];\n\t__u8 gid[8];\n};\n\nstruct RR_RR_s {\n\t__u8 flags[1];\n};\n\nstruct SL_component {\n\t__u8 flags;\n\t__u8 len;\n\t__u8 text[0];\n};\n\nstruct RR_SL_s {\n\t__u8 flags;\n\tstruct SL_component link;\n};\n\nstruct RR_TF_s {\n\t__u8 flags;\n\t__u8 data[0];\n};\n\nstruct RR_ZF_s {\n\t__u8 algorithm[2];\n\t__u8 parms[2];\n\t__u8 real_size[8];\n};\n\nstruct SU_CE_s {\n\t__u8 extent[8];\n\t__u8 offset[8];\n\t__u8 size[8];\n};\n\nstruct SU_ER_s {\n\t__u8 len_id;\n\t__u8 len_des;\n\t__u8 len_src;\n\t__u8 ext_ver;\n\t__u8 data[0];\n};\n\nstruct SU_SP_s {\n\t__u8 magic[2];\n\t__u8 skip;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n\tstruct lockdep_map lockdep_map;\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool work_in_progress;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tbool smart_suspend: 1;\n\tbool must_resume: 1;\n\tbool may_skip_resume: 1;\n\tbool out_band_wakeup: 1;\n\tbool strict_midlayer: 1;\n\tstruct hrtimer suspend_timer;\n\tu64 timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tbool idle_notification: 1;\n\tbool request_pending: 1;\n\tbool deferred_resume: 1;\n\tbool needs_force_resume: 1;\n\tbool runtime_auto: 1;\n\tbool ignore_children: 1;\n\tbool no_callbacks: 1;\n\tbool irq_safe: 1;\n\tbool use_autosuspend: 1;\n\tbool timer_autosuspends: 1;\n\tbool memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tenum rpm_status last_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct dev_archdata {};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct io_tlb_mem;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct dev_msi_info msi;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct io_tlb_mem *dma_io_tlb_mem;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tint numa_node;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_skip_sync: 1;\n\tbool dma_iommu: 1;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n};\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tint bmi2;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct fred_cs {\n\tu64 cs: 16;\n\tu64 sl: 2;\n\tu64 wfe: 1;\n};\n\nstruct fred_ss {\n\tu64 ss: 16;\n\tu64 sti: 1;\n\tu64 swevent: 1;\n\tu64 nmi: 1;\n\tint: 13;\n\tu64 vector: 8;\n\tshort: 8;\n\tu64 type: 4;\n\tchar: 4;\n\tu64 enclave: 1;\n\tu64 l: 1;\n\tu64 nested: 1;\n\tchar: 1;\n\tu64 insnlen: 4;\n};\n\nstruct pt_regs {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bp;\n\tlong unsigned int bx;\n\tlong unsigned int r11;\n\tlong unsigned int r10;\n\tlong unsigned int r9;\n\tlong unsigned int r8;\n\tlong unsigned int ax;\n\tlong unsigned int cx;\n\tlong unsigned int dx;\n\tlong unsigned int si;\n\tlong unsigned int di;\n\tlong unsigned int orig_ax;\n\tlong unsigned int ip;\n\tunion {\n\t\tu16 cs;\n\t\tu64 csx;\n\t\tstruct fred_cs fred_cs;\n\t};\n\tlong unsigned int flags;\n\tlong unsigned int sp;\n\tunion {\n\t\tu16 ss;\n\t\tu64 ssx;\n\t\tstruct fred_ss fred_ss;\n\t};\n};\n\nstruct __arch_ftrace_regs {\n\tstruct pt_regs regs;\n};\n\nstruct __arch_relative_insn {\n\tu8 op;\n\ts32 raddr;\n} __attribute__((packed));\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n\tu16 src;\n\tu16 dst;\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct idr;\n\nstruct __class_idr {\n\tstruct idr *idr;\n\tint id;\n};\n\ntypedef struct __class_idr class_idr_alloc_t;\n\nstruct cpumask;\n\nstruct __cmp_key {\n\tconst struct cpumask *cpus;\n\tstruct cpumask ***masks;\n\tint node;\n\tint cpu;\n\tint w;\n};\n\nstruct __compat_aio_sigset {\n\tcompat_uptr_t sigmask;\n\tcompat_size_t sigsetsize;\n};\n\nstruct drm_colorop;\n\nstruct drm_colorop_state;\n\nstruct __drm_colorops_state {\n\tstruct drm_colorop *ptr;\n\tstruct drm_colorop_state *state;\n\tstruct drm_colorop_state *old_state;\n\tstruct drm_colorop_state *new_state;\n};\n\nstruct drm_connector;\n\nstruct drm_connector_state;\n\nstruct __drm_connnectors_state {\n\tstruct drm_connector *ptr;\n\tstruct drm_connector_state *state_to_destroy;\n\tstruct drm_connector_state *old_state;\n\tstruct drm_connector_state *new_state;\n\ts32 *out_fence_ptr;\n};\n\nstruct drm_crtc;\n\nstruct drm_crtc_state;\n\nstruct drm_crtc_commit;\n\nstruct __drm_crtcs_state {\n\tstruct drm_crtc *ptr;\n\tstruct drm_crtc_state *state_to_destroy;\n\tstruct drm_crtc_state *old_state;\n\tstruct drm_crtc_state *new_state;\n\tstruct drm_crtc_commit *commit;\n\ts32 *out_fence_ptr;\n\tu64 last_vblank_count;\n};\n\nstruct drm_plane;\n\nstruct drm_plane_state;\n\nstruct __drm_planes_state {\n\tstruct drm_plane *ptr;\n\tstruct drm_plane_state *state_to_destroy;\n\tstruct drm_plane_state *old_state;\n\tstruct drm_plane_state *new_state;\n};\n\nstruct drm_private_obj;\n\nstruct drm_private_state;\n\nstruct __drm_private_objs_state {\n\tstruct drm_private_obj *ptr;\n\tstruct drm_private_state *state_to_destroy;\n\tstruct drm_private_state *old_state;\n\tstruct drm_private_state *new_state;\n};\n\nstruct __ext_steer_reg {\n\tconst char *name;\n\ti915_mcr_reg_t reg;\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct pmu;\n\nstruct cgroup;\n\nstruct __group_key {\n\tint cpu;\n\tstruct pmu *pmu;\n\tstruct cgroup *cgroup;\n};\n\nstruct guc_mmio_reg_set {\n\tu32 address;\n\tu16 count;\n\tu16 reserved;\n};\n\nstruct guc_ads {\n\tstruct guc_mmio_reg_set reg_state_list[512];\n\tu32 reserved0;\n\tu32 scheduler_policies;\n\tu32 gt_system_info;\n\tu32 reserved1;\n\tu32 control_data;\n\tu32 golden_context_lrca[16];\n\tu32 eng_state_size[16];\n\tu32 private_data;\n\tu32 reserved2;\n\tu32 capture_instance[32];\n\tu32 capture_class[32];\n\tu32 capture_global[2];\n\tu32 wa_klv_addr_lo;\n\tu32 wa_klv_addr_hi;\n\tu32 wa_klv_size;\n\tu32 reserved[11];\n};\n\nstruct guc_policies {\n\tu32 submission_queue_depth[16];\n\tu32 dpc_promote_time;\n\tu32 is_valid;\n\tu32 max_num_work_items;\n\tu32 global_flags;\n\tu32 reserved[4];\n};\n\nstruct guc_gt_system_info {\n\tu8 mapping_table[512];\n\tu32 engine_enabled_masks[16];\n\tu32 generic_gt_sysinfo[16];\n};\n\nstruct guc_engine_usage_record {\n\tu32 current_context_index;\n\tu32 last_switch_in_stamp;\n\tu32 reserved0;\n\tu32 total_runtime;\n\tu32 reserved1[4];\n};\n\nstruct guc_engine_usage {\n\tstruct guc_engine_usage_record engines[512];\n};\n\nstruct guc_mmio_reg {\n\tu32 offset;\n\tu32 value;\n\tu32 flags;\n\tu32 mask;\n};\n\nstruct __guc_ads_blob {\n\tstruct guc_ads ads;\n\tstruct guc_policies policies;\n\tstruct guc_gt_system_info system_info;\n\tstruct guc_engine_usage engine_usage;\n\tstruct guc_mmio_reg regset[0];\n};\n\nstruct __guc_capture_ads_cache {\n\tbool is_valid;\n\tvoid *ptr;\n\tsize_t size;\n\tint status;\n};\n\nstruct __guc_capture_bufstate {\n\tu32 size;\n\tvoid *data;\n\tu32 rd;\n\tu32 wr;\n};\n\nstruct gcap_reg_list_info {\n\tu32 vfid;\n\tu32 num_regs;\n\tstruct guc_mmio_reg *regs;\n};\n\nstruct __guc_capture_parsed_output {\n\tstruct list_head link;\n\tbool is_partial;\n\tu32 eng_class;\n\tu32 eng_inst;\n\tu32 guc_id;\n\tu32 lrca;\n\tstruct gcap_reg_list_info reginfo[3];\n};\n\nstruct __guc_mmio_reg_descr {\n\ti915_reg_t reg;\n\tu32 flags;\n\tu32 mask;\n\tconst char *regname;\n};\n\nstruct __guc_mmio_reg_descr_group {\n\tconst struct __guc_mmio_reg_descr *list;\n\tu32 num_regs;\n\tu32 owner;\n\tu32 type;\n\tu32 engine;\n\tstruct __guc_mmio_reg_descr *extlist;\n};\n\nstruct hda_codec;\n\nstruct __hda_power_obj {\n\tstruct hda_codec *codec;\n\tint err;\n};\n\ntypedef struct __hda_power_obj class_snd_hda_power_pm_t;\n\ntypedef struct __hda_power_obj class_snd_hda_power_t;\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct sha512_block_state {\n\tu64 h[8];\n};\n\nstruct __sha512_ctx {\n\tstruct sha512_block_state state;\n\tu64 bytecount_lo;\n\tu64 bytecount_hi;\n\tu8 buf[128];\n};\n\nstruct __hmac_sha512_ctx {\n\tstruct __sha512_ctx sha_ctx;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __hmac_sha512_key {\n\tstruct sha512_block_state istate;\n\tstruct sha512_block_state ostate;\n};\n\nstruct ww_acquire_ctx;\n\nstruct ww_class;\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n\tstruct ww_class *ww_class;\n};\n\nstruct drm_modeset_lock {\n\tstruct ww_mutex mutex;\n\tstruct list_head head;\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n\tstruct lockdep_map lockdep_map;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct drm_modeset_acquire_ctx;\n\nstruct drm_mode_config_funcs;\n\nstruct drm_property;\n\nstruct drm_atomic_state;\n\nstruct drm_mode_config_helper_funcs;\n\nstruct drm_mode_config {\n\tstruct mutex mutex;\n\tstruct drm_modeset_lock connection_mutex;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct mutex idr_mutex;\n\tstruct idr object_idr;\n\tstruct idr tile_idr;\n\tstruct mutex fb_lock;\n\tint num_fb;\n\tstruct list_head fb_list;\n\tspinlock_t connector_list_lock;\n\tint num_connector;\n\tstruct ida connector_ida;\n\tstruct list_head connector_list;\n\tstruct llist_head connector_free_list;\n\tstruct work_struct connector_free_work;\n\tint num_encoder;\n\tstruct list_head encoder_list;\n\tint num_total_plane;\n\tstruct list_head plane_list;\n\tstruct raw_spinlock panic_lock;\n\tint num_colorop;\n\tstruct list_head colorop_list;\n\tint num_crtc;\n\tstruct list_head crtc_list;\n\tstruct list_head property_list;\n\tstruct list_head privobj_list;\n\tunsigned int min_width;\n\tunsigned int min_height;\n\tunsigned int max_width;\n\tunsigned int max_height;\n\tconst struct drm_mode_config_funcs *funcs;\n\tbool poll_enabled;\n\tbool poll_running;\n\tbool delayed_event;\n\tstruct delayed_work output_poll_work;\n\tstruct mutex blob_lock;\n\tstruct list_head property_blob_list;\n\tstruct drm_property *edid_property;\n\tstruct drm_property *dpms_property;\n\tstruct drm_property *path_property;\n\tstruct drm_property *tile_property;\n\tstruct drm_property *link_status_property;\n\tstruct drm_property *plane_type_property;\n\tstruct drm_property *prop_src_x;\n\tstruct drm_property *prop_src_y;\n\tstruct drm_property *prop_src_w;\n\tstruct drm_property *prop_src_h;\n\tstruct drm_property *prop_crtc_x;\n\tstruct drm_property *prop_crtc_y;\n\tstruct drm_property *prop_crtc_w;\n\tstruct drm_property *prop_crtc_h;\n\tstruct drm_property *prop_fb_id;\n\tstruct drm_property *prop_in_fence_fd;\n\tstruct drm_property *prop_out_fence_ptr;\n\tstruct drm_property *prop_crtc_id;\n\tstruct drm_property *prop_fb_damage_clips;\n\tstruct drm_property *prop_active;\n\tstruct drm_property *prop_mode_id;\n\tstruct drm_property *prop_vrr_enabled;\n\tstruct drm_property *dvi_i_subconnector_property;\n\tstruct drm_property *dvi_i_select_subconnector_property;\n\tstruct drm_property *dp_subconnector_property;\n\tstruct drm_property *tv_subconnector_property;\n\tstruct drm_property *tv_select_subconnector_property;\n\tstruct drm_property *legacy_tv_mode_property;\n\tstruct drm_property *tv_mode_property;\n\tstruct drm_property *tv_left_margin_property;\n\tstruct drm_property *tv_right_margin_property;\n\tstruct drm_property *tv_top_margin_property;\n\tstruct drm_property *tv_bottom_margin_property;\n\tstruct drm_property *tv_brightness_property;\n\tstruct drm_property *tv_contrast_property;\n\tstruct drm_property *tv_flicker_reduction_property;\n\tstruct drm_property *tv_overscan_property;\n\tstruct drm_property *tv_saturation_property;\n\tstruct drm_property *tv_hue_property;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *aspect_ratio_property;\n\tstruct drm_property *content_type_property;\n\tstruct drm_property *degamma_lut_property;\n\tstruct drm_property *degamma_lut_size_property;\n\tstruct drm_property *ctm_property;\n\tstruct drm_property *gamma_lut_property;\n\tstruct drm_property *gamma_lut_size_property;\n\tstruct drm_property *suggested_x_property;\n\tstruct drm_property *suggested_y_property;\n\tstruct drm_property *non_desktop_property;\n\tstruct drm_property *panel_orientation_property;\n\tstruct drm_property *writeback_fb_id_property;\n\tstruct drm_property *writeback_pixel_formats_property;\n\tstruct drm_property *writeback_out_fence_ptr_property;\n\tstruct drm_property *hdr_output_metadata_property;\n\tstruct drm_property *content_protection_property;\n\tstruct drm_property *hdcp_content_type_property;\n\tuint32_t preferred_depth;\n\tuint32_t prefer_shadow;\n\tbool quirk_addfb_prefer_xbgr_30bpp;\n\tbool quirk_addfb_prefer_host_byte_order;\n\tbool async_page_flip;\n\tbool fb_modifiers_not_supported;\n\tbool normalize_zpos;\n\tstruct drm_property *modifiers_property;\n\tstruct drm_property *async_modifiers_property;\n\tstruct drm_property *size_hints_property;\n\tuint32_t cursor_width;\n\tuint32_t cursor_height;\n\tstruct drm_atomic_state *suspend_state;\n\tconst struct drm_mode_config_helper_funcs *helper_private;\n};\n\nstruct drm_vram_mm;\n\nstruct drm_fb_helper;\n\nstruct drm_driver;\n\nstruct drm_minor;\n\nstruct drm_master;\n\nstruct inode;\n\nstruct drm_vblank_crtc;\n\nstruct drm_vma_offset_manager;\n\nstruct drm_device {\n\tint if_version;\n\tstruct kref ref;\n\tstruct device *dev;\n\tstruct device *dma_dev;\n\tstruct {\n\t\tstruct list_head resources;\n\t\tvoid *final_kfree;\n\t\tspinlock_t lock;\n\t} managed;\n\tconst struct drm_driver *driver;\n\tvoid *dev_private;\n\tstruct drm_minor *primary;\n\tstruct drm_minor *render;\n\tstruct drm_minor *accel;\n\tbool registered;\n\tstruct drm_master *master;\n\tu32 driver_features;\n\tbool unplugged;\n\tstruct inode *anon_inode;\n\tchar *unique;\n\tstruct mutex master_mutex;\n\tatomic_t open_count;\n\tstruct mutex filelist_mutex;\n\tstruct list_head filelist;\n\tstruct list_head filelist_internal;\n\tstruct mutex clientlist_mutex;\n\tstruct list_head clientlist;\n\tstruct list_head client_sysrq_list;\n\tbool vblank_disable_immediate;\n\tstruct drm_vblank_crtc *vblank;\n\tspinlock_t vblank_time_lock;\n\tspinlock_t vbl_lock;\n\tu32 max_vblank_count;\n\tstruct list_head vblank_event_list;\n\tspinlock_t event_lock;\n\tunsigned int num_crtcs;\n\tstruct drm_mode_config mode_config;\n\tstruct mutex object_name_lock;\n\tstruct idr object_name_idr;\n\tstruct drm_vma_offset_manager *vma_offset_manager;\n\tstruct drm_vram_mm *vram_mm;\n\tenum switch_power_state switch_power_state;\n\tstruct drm_fb_helper *fb_helper;\n\tstruct dentry *debugfs_root;\n};\n\nstruct intel_display;\n\nstruct __intel_generic_device {\n\tstruct drm_device drm;\n\tstruct intel_display *display;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct __large_struct {\n\tlong unsigned int buf[100];\n};\n\nstruct __old_kernel_stat {\n\tshort unsigned int st_dev;\n\tshort unsigned int st_ino;\n\tshort unsigned int st_mode;\n\tshort unsigned int st_nlink;\n\tshort unsigned int st_uid;\n\tshort unsigned int st_gid;\n\tshort unsigned int st_rdev;\n\tunsigned int st_size;\n\tunsigned int st_atime;\n\tunsigned int st_mtime;\n\tunsigned int st_ctime;\n};\n\nstruct sha3_state {\n\tunion {\n\t\t__le64 words[25];\n\t\tu8 bytes[200];\n\t\tu64 native_words[25];\n\t};\n};\n\nstruct __sha3_ctx {\n\tstruct sha3_state state;\n\tu8 digest_size;\n\tu8 block_size;\n\tu8 absorb_offset;\n\tu8 squeeze_offset;\n};\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[8];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[8];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct __snd_pcm_mmap_control64_buggy {\n\t__pad_before_u32 __pad1;\n\t__u32 appl_ptr;\n\t__pad_before_u32 __pad2;\n\t__pad_before_u32 __pad3;\n\t__u32 avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct snd_seq_real_time {\n\tunsigned int tv_sec;\n\tunsigned int tv_nsec;\n};\n\nunion snd_seq_timestamp {\n\tsnd_seq_tick_time_t tick;\n\tstruct snd_seq_real_time time;\n};\n\nstruct snd_seq_addr {\n\tunsigned char client;\n\tunsigned char port;\n};\n\nstruct snd_seq_ev_note {\n\tunsigned char channel;\n\tunsigned char note;\n\tunsigned char velocity;\n\tunsigned char off_velocity;\n\tunsigned int duration;\n};\n\nstruct snd_seq_ev_ctrl {\n\tunsigned char channel;\n\tunsigned char unused1;\n\tunsigned char unused2;\n\tunsigned char unused3;\n\tunsigned int param;\n\tint value;\n};\n\nstruct snd_seq_ev_raw8 {\n\tunsigned char d[12];\n};\n\nstruct snd_seq_ev_raw32 {\n\tunsigned int d[3];\n};\n\nstruct snd_seq_ev_ext {\n\tunsigned int len;\n\tvoid *ptr;\n} __attribute__((packed));\n\nstruct snd_seq_queue_skew {\n\tunsigned int value;\n\tunsigned int base;\n};\n\nstruct snd_seq_ev_queue_control {\n\tunsigned char queue;\n\tunsigned char pad[3];\n\tunion {\n\t\tint value;\n\t\tunion snd_seq_timestamp time;\n\t\tunsigned int position;\n\t\tstruct snd_seq_queue_skew skew;\n\t\tunsigned int d32[2];\n\t\tunsigned char d8[8];\n\t} param;\n};\n\nstruct snd_seq_connect {\n\tstruct snd_seq_addr sender;\n\tstruct snd_seq_addr dest;\n};\n\nstruct snd_seq_result {\n\tint event;\n\tint result;\n};\n\nstruct snd_seq_event;\n\nstruct snd_seq_ev_quote {\n\tstruct snd_seq_addr origin;\n\tshort unsigned int value;\n\tstruct snd_seq_event *event;\n} __attribute__((packed));\n\nstruct snd_seq_ev_ump_notify {\n\tunsigned char client;\n\tunsigned char block;\n};\n\nunion snd_seq_event_data {\n\tstruct snd_seq_ev_note note;\n\tstruct snd_seq_ev_ctrl control;\n\tstruct snd_seq_ev_raw8 raw8;\n\tstruct snd_seq_ev_raw32 raw32;\n\tstruct snd_seq_ev_ext ext;\n\tstruct snd_seq_ev_queue_control queue;\n\tunion snd_seq_timestamp time;\n\tstruct snd_seq_addr addr;\n\tstruct snd_seq_connect connect;\n\tstruct snd_seq_result result;\n\tstruct snd_seq_ev_quote quote;\n\tstruct snd_seq_ev_ump_notify ump_notify;\n};\n\nstruct snd_seq_event {\n\tsnd_seq_event_type_t type;\n\tunsigned char flags;\n\tchar tag;\n\tunsigned char queue;\n\tunion snd_seq_timestamp time;\n\tstruct snd_seq_addr source;\n\tstruct snd_seq_addr dest;\n\tunion snd_seq_event_data data;\n};\n\nunion __snd_seq_event {\n\tstruct snd_seq_event legacy;\n\tstruct {\n\t\tstruct snd_seq_event event;\n\t} raw;\n};\n\nstruct __snd_timespec {\n\t__s32 tv_sec;\n\t__s32 tv_nsec;\n};\n\nunion __u128_halves {\n\tu128 full;\n\tstruct {\n\t\tu64 low;\n\t\tu64 high;\n\t};\n};\n\nstruct __uprobe_key {\n\tstruct inode *inode;\n\tloff_t offset;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct __va_list_tag {\n\tunsigned int gp_offset;\n\tunsigned int fp_offset;\n\tvoid *overflow_arg_area;\n\tvoid *reg_save_area;\n};\n\ntypedef __builtin_va_list va_list;\n\nstruct __x86_intercept {\n\tu32 exit_code;\n\tenum x86_intercept_stage stage;\n};\n\nstruct drm_mm;\n\nstruct drm_mm_node {\n\tlong unsigned int color;\n\tu64 start;\n\tu64 size;\n\tstruct drm_mm *mm;\n\tstruct list_head node_list;\n\tstruct list_head hole_stack;\n\tstruct rb_node rb;\n\tstruct rb_node rb_hole_size;\n\tstruct rb_node rb_hole_addr;\n\tu64 __subtree_last;\n\tu64 hole_size;\n\tu64 subtree_max_hole;\n\tlong unsigned int flags;\n};\n\nstruct _balloon_info_ {\n\tstruct drm_mm_node space[4];\n};\n\nstruct net_device;\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nunion _cpuid4_leaf_eax {\n\tstruct {\n\t\tenum _cache_type type: 5;\n\t\tunsigned int level: 3;\n\t\tunsigned int is_self_initializing: 1;\n\t\tunsigned int is_fully_associative: 1;\n\t\tunsigned int reserved: 4;\n\t\tunsigned int num_threads_sharing: 12;\n\t\tunsigned int num_cores_on_die: 6;\n\t} split;\n\tu32 full;\n};\n\nunion _cpuid4_leaf_ebx {\n\tstruct {\n\t\tunsigned int coherency_line_size: 12;\n\t\tunsigned int physical_line_partition: 10;\n\t\tunsigned int ways_of_associativity: 10;\n\t} split;\n\tu32 full;\n};\n\nunion _cpuid4_leaf_ecx {\n\tstruct {\n\t\tunsigned int number_of_sets: 32;\n\t} split;\n\tu32 full;\n};\n\nstruct _cpuid4_info {\n\tunion _cpuid4_leaf_eax eax;\n\tunion _cpuid4_leaf_ebx ebx;\n\tunion _cpuid4_leaf_ecx ecx;\n\tunsigned int id;\n\tlong unsigned int size;\n};\n\nstruct jump_entry;\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct _ddebug {\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n\tconst char *format;\n\tunsigned int lineno: 18;\n\tunsigned int class_id: 6;\n\tunsigned int flags: 8;\n\tunion {\n\t\tstruct static_key_true dd_key_true;\n\t\tstruct static_key_false dd_key_false;\n\t} key;\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _fpreg {\n\t__u16 significand[4];\n\t__u16 exponent;\n};\n\nstruct _fpxreg {\n\t__u16 significand[4];\n\t__u16 exponent;\n\t__u16 padding[3];\n};\n\nstruct _xmmreg {\n\t__u32 element[4];\n};\n\nstruct _fpx_sw_bytes {\n\t__u32 magic1;\n\t__u32 extended_size;\n\t__u64 xfeatures;\n\t__u32 xstate_size;\n\t__u32 padding[7];\n};\n\nstruct _fpstate_32 {\n\t__u32 cw;\n\t__u32 sw;\n\t__u32 tag;\n\t__u32 ipoff;\n\t__u32 cssel;\n\t__u32 dataoff;\n\t__u32 datasel;\n\tstruct _fpreg _st[8];\n\t__u16 status;\n\t__u16 magic;\n\t__u32 _fxsr_env[6];\n\t__u32 mxcsr;\n\t__u32 reserved;\n\tstruct _fpxreg _fxsr_st[8];\n\tstruct _xmmreg _xmm[8];\n\tunion {\n\t\t__u32 padding1[44];\n\t\t__u32 padding[44];\n\t};\n\tunion {\n\t\t__u32 padding2[12];\n\t\tstruct _fpx_sw_bytes sw_reserved;\n\t};\n};\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n} __attribute__((packed));\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct intel_gtt_driver;\n\nstruct pci_dev;\n\nstruct page;\n\nstruct _intel_private {\n\tconst struct intel_gtt_driver *driver;\n\tstruct pci_dev *pcidev;\n\tstruct pci_dev *bridge_dev;\n\tu8 *registers;\n\tphys_addr_t gtt_phys_addr;\n\tu32 PGETBL_save;\n\tu32 *gtt;\n\tbool clear_fake_agp;\n\tint num_dcache_entries;\n\tvoid *i9xx_flush_page;\n\tchar *i81x_gtt_table;\n\tstruct resource ifp_resource;\n\tint resource_valid;\n\tstruct page *scratch_page;\n\tphys_addr_t scratch_page_dma;\n\tint refcount;\n\tunsigned int needs_dmar: 1;\n\tphys_addr_t gma_bus_addr;\n\tresource_size_t stolen_size;\n\tunsigned int gtt_total_entries;\n\tunsigned int gtt_mappable_entries;\n};\n\nstruct kvm_io_device_ops;\n\nstruct kvm_io_device {\n\tconst struct kvm_io_device_ops *ops;\n};\n\nstruct eventfd_ctx;\n\nstruct _ioeventfd {\n\tstruct list_head list;\n\tu64 addr;\n\tint length;\n\tstruct eventfd_ctx *eventfd;\n\tu64 datamatch;\n\tstruct kvm_io_device dev;\n\tu8 bus_idx;\n\tbool wildcard;\n};\n\nstruct kvm_stats_desc {\n\t__u32 flags;\n\t__s16 exponent;\n\t__u16 size;\n\t__u32 offset;\n\t__u32 bucket_size;\n\tchar name[0];\n};\n\nstruct _kvm_stats_desc {\n\tstruct kvm_stats_desc desc;\n\tchar name[48];\n};\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct _thermal_state {\n\tu64 next_check;\n\tu64 last_interrupt_time;\n\tstruct delayed_work therm_work;\n\tlong unsigned int count;\n\tlong unsigned int last_count;\n\tlong unsigned int max_time_ms;\n\tlong unsigned int total_time_ms;\n\tbool rate_control_active;\n\tbool new_event;\n\tu8 level;\n\tu8 sample_index;\n\tu8 sample_count;\n\tu8 average;\n\tu8 baseline_temp;\n\tu8 temp_samples[3];\n};\n\nstruct snd_ac97;\n\nstruct ac97_codec_id {\n\tunsigned int id;\n\tunsigned int mask;\n\tconst char *name;\n\tint (*patch)(struct snd_ac97 *);\n\tint (*mpatch)(struct snd_ac97 *);\n\tunsigned int flags;\n};\n\nstruct ac97_enum {\n\tunsigned char reg;\n\tunsigned char shift_l;\n\tunsigned char shift_r;\n\tshort unsigned int mask;\n\tconst char * const *texts;\n};\n\nstruct snd_ac97_bus;\n\nstruct ac97_pcm {\n\tstruct snd_ac97_bus *bus;\n\tunsigned int stream: 1;\n\tunsigned int exclusive: 1;\n\tunsigned int copy_flag: 1;\n\tunsigned int spdif: 1;\n\tshort unsigned int aslots;\n\tshort unsigned int cur_dbl;\n\tunsigned int rates;\n\tstruct {\n\t\tshort unsigned int slots;\n\t\tshort unsigned int rslots[4];\n\t\tunsigned char rate_table[4];\n\t\tstruct snd_ac97 *codec[4];\n\t} r[2];\n\tlong unsigned int private_value;\n};\n\nstruct ac97_power_reg {\n\tshort unsigned int reg;\n\tshort unsigned int power_reg;\n\tshort unsigned int mask;\n};\n\nstruct ac97_quirk {\n\tshort unsigned int subvendor;\n\tshort unsigned int subdevice;\n\tshort unsigned int mask;\n\tunsigned int codec_id;\n\tconst char *name;\n\tint type;\n};\n\nstruct access_coordinate {\n\tunsigned int read_bandwidth;\n\tunsigned int write_bandwidth;\n\tunsigned int read_latency;\n\tunsigned int write_latency;\n};\n\nstruct acct {\n\tchar ac_flag;\n\tchar ac_version;\n\t__u16 ac_uid16;\n\t__u16 ac_gid16;\n\t__u16 ac_tty;\n\t__u32 ac_btime;\n\tcomp_t ac_utime;\n\tcomp_t ac_stime;\n\tcomp_t ac_etime;\n\tcomp_t ac_mem;\n\tcomp_t ac_io;\n\tcomp_t ac_rw;\n\tcomp_t ac_minflt;\n\tcomp_t ac_majflt;\n\tcomp_t ac_swaps;\n\t__u16 ac_ahz;\n\t__u32 ac_exitcode;\n\tchar ac_comm[17];\n\t__u8 ac_etime_hi;\n\t__u16 ac_etime_lo;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n};\n\ntypedef struct acct acct_t;\n\nstruct drm_dp_nak_reply {\n\tguid_t guid;\n\tu8 reason;\n\tu8 nak_data;\n};\n\nstruct drm_dp_link_addr_reply_port {\n\tbool input_port;\n\tu8 peer_device_type;\n\tu8 port_number;\n\tbool mcs;\n\tbool ddps;\n\tbool legacy_device_plug_status;\n\tu8 dpcd_revision;\n\tguid_t peer_guid;\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n};\n\nstruct drm_dp_link_address_ack_reply {\n\tguid_t guid;\n\tu8 nports;\n\tstruct drm_dp_link_addr_reply_port ports[16];\n};\n\nstruct drm_dp_port_number_rep {\n\tu8 port_number;\n};\n\nstruct drm_dp_enum_path_resources_ack_reply {\n\tu8 port_number;\n\tbool fec_capable;\n\tu16 full_payload_bw_number;\n\tu16 avail_payload_bw_number;\n};\n\nstruct drm_dp_allocate_payload_ack_reply {\n\tu8 port_number;\n\tu8 vcpi;\n\tu16 allocated_pbn;\n};\n\nstruct drm_dp_query_payload_ack_reply {\n\tu8 port_number;\n\tu16 allocated_pbn;\n};\n\nstruct drm_dp_remote_dpcd_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_dpcd_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_remote_dpcd_write_nak_reply {\n\tu8 port_number;\n\tu8 reason;\n\tu8 bytes_written_before_failure;\n};\n\nstruct drm_dp_remote_i2c_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_i2c_read_nak_reply {\n\tu8 port_number;\n\tu8 nak_reason;\n\tu8 i2c_nak_transaction;\n};\n\nstruct drm_dp_remote_i2c_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_query_stream_enc_status_ack_reply {\n\tu8 stream_id;\n\tbool reply_signed;\n\tbool unauthorizable_device_present;\n\tbool legacy_device_present;\n\tbool query_capable_device_present;\n\tbool hdcp_1x_device_present;\n\tbool hdcp_2x_device_present;\n\tbool auth_completed;\n\tbool encryption_enabled;\n\tbool repeater_present;\n\tu8 state;\n};\n\nunion ack_replies {\n\tstruct drm_dp_nak_reply nak;\n\tstruct drm_dp_link_address_ack_reply link_addr;\n\tstruct drm_dp_port_number_rep port_number;\n\tstruct drm_dp_enum_path_resources_ack_reply path_resources;\n\tstruct drm_dp_allocate_payload_ack_reply allocate_payload;\n\tstruct drm_dp_query_payload_ack_reply query_payload;\n\tstruct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack;\n\tstruct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack;\n\tstruct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack;\n\tstruct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack;\n\tstruct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack;\n\tstruct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;\n\tstruct drm_dp_query_stream_enc_status_ack_reply enc_status;\n};\n\nstruct drm_dp_connection_status_notify {\n\tguid_t guid;\n\tu8 port_number;\n\tbool legacy_device_plug_status;\n\tbool displayport_device_plug_status;\n\tbool message_capability_status;\n\tbool input_port;\n\tu8 peer_device_type;\n};\n\nstruct drm_dp_port_number_req {\n\tu8 port_number;\n};\n\nstruct drm_dp_resource_status_notify {\n\tu8 port_number;\n\tguid_t guid;\n\tu16 available_pbn;\n};\n\nstruct drm_dp_query_payload {\n\tu8 port_number;\n\tu8 vcpi;\n};\n\nstruct drm_dp_allocate_payload {\n\tu8 port_number;\n\tu8 number_sdp_streams;\n\tu8 vcpi;\n\tu16 pbn;\n\tu8 sdp_stream_sink[16];\n};\n\nstruct drm_dp_remote_dpcd_read {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n};\n\nstruct drm_dp_remote_dpcd_write {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_remote_i2c_read_tx {\n\tu8 i2c_dev_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n\tu8 no_stop_bit;\n\tu8 i2c_transaction_delay;\n};\n\nstruct drm_dp_remote_i2c_read {\n\tu8 num_transactions;\n\tu8 port_number;\n\tstruct drm_dp_remote_i2c_read_tx transactions[4];\n\tu8 read_i2c_device_id;\n\tu8 num_bytes_read;\n};\n\nstruct drm_dp_remote_i2c_write {\n\tu8 port_number;\n\tu8 write_i2c_device_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_query_stream_enc_status {\n\tu8 stream_id;\n\tu8 client_id[7];\n\tu8 stream_event;\n\tbool valid_stream_event;\n\tu8 stream_behavior;\n\tu8 valid_stream_behavior;\n};\n\nunion ack_req {\n\tstruct drm_dp_connection_status_notify conn_stat;\n\tstruct drm_dp_port_number_req port_num;\n\tstruct drm_dp_resource_status_notify resource_stat;\n\tstruct drm_dp_query_payload query_payload;\n\tstruct drm_dp_allocate_payload allocate_payload;\n\tstruct drm_dp_remote_dpcd_read dpcd_read;\n\tstruct drm_dp_remote_dpcd_write dpcd_write;\n\tstruct drm_dp_remote_i2c_read i2c_read;\n\tstruct drm_dp_remote_i2c_write i2c_write;\n\tstruct drm_dp_query_stream_enc_status enc_status;\n};\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n};\n\nstruct comp_alg_common {\n\tstruct crypto_alg base;\n};\n\nstruct acomp_req;\n\nstruct crypto_acomp;\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\ntypedef void (*crypto_completion_t)(void *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n\tunsigned int dma_length;\n\tunsigned int dma_flags;\n};\n\nstruct acomp_req_chain {\n\tcrypto_completion_t compl;\n\tvoid *data;\n\tstruct scatterlist ssg;\n\tstruct scatterlist dsg;\n\tunion {\n\t\tconst u8 *src;\n\t\tstruct folio *sfolio;\n\t};\n\tunion {\n\t\tu8 *dst;\n\t\tstruct folio *dfolio;\n\t};\n\tu32 flags;\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tunion {\n\t\tstruct scatterlist *dst;\n\t\tu8 *dvirt;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct acomp_req_chain chain;\n\tvoid *__ctx[0];\n};\n\nunion crypto_no_such_thing;\n\nstruct scatter_walk {\n\tunion {\n\t\tvoid * const addr;\n\t\tunion crypto_no_such_thing *__addr;\n\t};\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct acomp_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tint flags;\n};\n\nstruct power_supply;\n\nunion power_supply_propval;\n\nstruct power_supply_desc {\n\tconst char *name;\n\tenum power_supply_type type;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tu32 usb_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, enum power_supply_property);\n\tvoid (*external_power_changed)(struct power_supply *);\n\tbool no_thermal;\n\tint use_for_apm;\n};\n\nstruct notifier_block;\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct acpi_device;\n\nstruct acpi_ac {\n\tstruct power_supply *charger;\n\tstruct power_supply_desc charger_desc;\n\tstruct acpi_device *device;\n\tlong long unsigned int state;\n\tstruct notifier_block battery_nb;\n};\n\nstruct acpi_address16_attribute {\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n};\n\nstruct acpi_address32_attribute {\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n};\n\nstruct acpi_address64_attribute {\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n};\n\nstruct acpi_namespace_node;\n\nstruct acpi_address_range {\n\tstruct acpi_address_range *next;\n\tstruct acpi_namespace_node *region_node;\n\tacpi_physical_address start_address;\n\tacpi_physical_address end_address;\n};\n\nstruct acpi_battery {\n\tstruct mutex update_lock;\n\tstruct power_supply *bat;\n\tstruct power_supply_desc bat_desc;\n\tstruct acpi_device *device;\n\tstruct notifier_block pm_nb;\n\tstruct list_head list;\n\tlong unsigned int update_time;\n\tint revision;\n\tint rate_now;\n\tint capacity_now;\n\tint voltage_now;\n\tint design_capacity;\n\tint full_charge_capacity;\n\tint technology;\n\tint design_voltage;\n\tint design_capacity_warning;\n\tint design_capacity_low;\n\tint cycle_count;\n\tint measurement_accuracy;\n\tint max_sampling_time;\n\tint min_sampling_time;\n\tint max_averaging_interval;\n\tint min_averaging_interval;\n\tint capacity_granularity_1;\n\tint capacity_granularity_2;\n\tint alarm;\n\tchar model_number[64];\n\tchar serial_number[64];\n\tchar type[64];\n\tchar oem_info[64];\n\tint state;\n\tint power_unit;\n\tlong unsigned int flags;\n};\n\nstruct acpi_battery_hook {\n\tconst char *name;\n\tint (*add_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tint (*remove_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tstruct list_head list;\n};\n\nstruct acpi_bit_register_info {\n\tu8 parent_register;\n\tu8 bit_position;\n\tu16 access_bit_mask;\n};\n\nstruct acpi_buffer {\n\tacpi_size length;\n\tvoid *pointer;\n};\n\nstruct acpi_bus_event {\n\tstruct list_head node;\n\tacpi_device_class device_class;\n\tacpi_bus_id bus_id;\n\tu32 type;\n\tu32 data;\n};\n\nstruct acpi_bus_type {\n\tstruct list_head list;\n\tconst char *name;\n\tbool (*match)(struct device *);\n\tstruct acpi_device * (*find_companion)(struct device *);\n\tvoid (*setup)(struct device *);\n};\n\nstruct input_dev;\n\nstruct acpi_button {\n\tstruct acpi_device *adev;\n\tstruct device *dev;\n\tunsigned int type;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tlong unsigned int pushed;\n\tint last_state;\n\tktime_t last_time;\n\tbool suspended;\n\tbool lid_state_initialized;\n};\n\nstruct acpi_cdat_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_cfmws {\n\tstruct acpi_cedt_header header;\n\tu32 reserved1;\n\tu64 base_hpa;\n\tu64 window_size;\n\tu8 interleave_ways;\n\tu8 interleave_arithmetic;\n\tu16 reserved2;\n\tu32 granularity;\n\tu16 restrictions;\n\tu16 qtg_id;\n\tu32 interleave_targets[0];\n} __attribute__((packed));\n\nstruct acpi_comment_node {\n\tchar *comment;\n\tstruct acpi_comment_node *next;\n};\n\nstruct acpi_common_descriptor {\n\tvoid *common_pointer;\n\tu8 descriptor_type;\n};\n\nstruct acpi_common_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n};\n\nstruct acpi_connection_info {\n\tu8 *connection;\n\tu16 length;\n\tu8 access_length;\n};\n\nunion acpi_parse_object;\n\nstruct acpi_control_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu16 opcode;\n\tunion acpi_parse_object *predicate_op;\n\tu8 *aml_predicate_start;\n\tu8 *package_end;\n\tu64 loop_timeout;\n};\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct acpi_pct_register;\n\nstruct acpi_cpufreq_data {\n\tunsigned int resume;\n\tunsigned int cpu_feature;\n\tunsigned int acpi_perf_cpu;\n\tcpumask_var_t freqdomain_cpus;\n\tvoid (*cpu_freq_write)(struct acpi_pct_register *, u32);\n\tu32 (*cpu_freq_read)(struct acpi_pct_register *);\n};\n\nstruct acpi_create_field_info {\n\tstruct acpi_namespace_node *region_node;\n\tstruct acpi_namespace_node *field_node;\n\tstruct acpi_namespace_node *register_node;\n\tstruct acpi_namespace_node *data_register_node;\n\tstruct acpi_namespace_node *connection_node;\n\tu8 *resource_buffer;\n\tu32 bank_value;\n\tu32 field_bit_position;\n\tu32 field_bit_length;\n\tu16 resource_length;\n\tu16 pin_number_index;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 field_type;\n\tu8 access_length;\n};\n\nstruct acpi_csrt_group {\n\tu32 length;\n\tu32 vendor_id;\n\tu32 subvendor_id;\n\tu16 device_id;\n\tu16 subdevice_id;\n\tu16 revision;\n\tu16 reserved;\n\tu32 shared_info_length;\n};\n\nstruct acpi_csrt_shared_info {\n\tu16 major_version;\n\tu16 minor_version;\n\tu32 mmio_base_low;\n\tu32 mmio_base_high;\n\tu32 gsi_interrupt;\n\tu8 interrupt_polarity;\n\tu8 interrupt_mode;\n\tu8 num_channels;\n\tu8 dma_address_width;\n\tu16 base_request_line;\n\tu16 num_handshake_signals;\n\tu32 max_block_size;\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n\tbool ignore_lockdep: 1;\n\tstruct lock_class_key *key;\n\tstruct lock_class_key skey;\n};\n\nstruct address_space;\n\nstruct vm_area_struct;\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct acpi_data_attr {\n\tstruct bin_attribute attr;\n\tu64 addr;\n};\n\ntypedef void *acpi_handle;\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nunion acpi_object;\n\nstruct acpi_device_data {\n\tconst union acpi_object *pointer;\n\tstruct list_head properties;\n\tconst union acpi_object *of_compatible;\n\tstruct list_head subnodes;\n};\n\nstruct acpi_data_node {\n\tstruct list_head sibling;\n\tconst char *name;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tstruct acpi_device_data data;\n\tstruct kobject kobj;\n\tstruct completion kobj_done;\n};\n\nstruct acpi_data_node_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct acpi_data_node *, char *);\n\tssize_t (*store)(struct acpi_data_node *, const char *, size_t);\n};\n\nstruct acpi_data_obj {\n\tchar *name;\n\tint (*fn)(void *, struct acpi_data_attr *);\n};\n\nstruct acpi_data_table_mapping {\n\tvoid *pointer;\n};\n\nstruct acpi_dep_data {\n\tstruct list_head node;\n\tacpi_handle supplier;\n\tacpi_handle consumer;\n\tbool honor_dep;\n\tbool met;\n\tbool free_when_met;\n};\n\nunion acpi_operand_object;\n\nstruct acpi_object_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n};\n\nstruct acpi_object_integer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 fill[3];\n\tu64 value;\n};\n\nstruct acpi_object_string {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tchar *pointer;\n\tu32 length;\n};\n\nstruct acpi_object_buffer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 *pointer;\n\tu32 length;\n\tu32 aml_length;\n\tu8 *aml_start;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_object_package {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **elements;\n\tu8 *aml_start;\n\tu32 aml_length;\n\tu32 count;\n};\n\nstruct acpi_object_event {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tvoid *os_semaphore;\n};\n\nstruct acpi_walk_state;\n\ntypedef acpi_status (*acpi_internal_method)(struct acpi_walk_state *);\n\nstruct acpi_object_method {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 info_flags;\n\tu8 param_count;\n\tu8 sync_level;\n\tunion acpi_operand_object *mutex;\n\tunion acpi_operand_object *node;\n\tu8 *aml_start;\n\tunion {\n\t\tacpi_internal_method implementation;\n\t\tunion acpi_operand_object *handler;\n\t} dispatch;\n\tu32 aml_length;\n\tacpi_owner_id owner_id;\n\tu8 thread_count;\n};\n\nstruct acpi_thread_state;\n\nstruct acpi_object_mutex {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 sync_level;\n\tu16 acquisition_depth;\n\tvoid *os_mutex;\n\tu64 thread_id;\n\tstruct acpi_thread_state *owner_thread;\n\tunion acpi_operand_object *prev;\n\tunion acpi_operand_object *next;\n\tstruct acpi_namespace_node *node;\n\tu8 original_sync_level;\n};\n\nstruct acpi_object_region {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler;\n\tunion acpi_operand_object *next;\n\tacpi_physical_address address;\n\tu32 length;\n\tvoid *pointer;\n};\n\nstruct acpi_object_notify_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_gpe_block_info;\n\nstruct acpi_object_device {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tstruct acpi_gpe_block_info *gpe_block;\n};\n\nstruct acpi_object_power_resource {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tu32 system_level;\n\tu32 resource_order;\n};\n\nstruct acpi_object_processor {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 proc_id;\n\tu8 length;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tacpi_io_address address;\n};\n\nstruct acpi_object_thermal_zone {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_object_field_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n};\n\nstruct acpi_object_region_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu16 resource_length;\n\tunion acpi_operand_object *region_obj;\n\tu8 *resource_buffer;\n\tu16 pin_number_index;\n\tu8 *internal_pcc_buffer;\n};\n\nstruct acpi_object_buffer_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu8 is_create_field;\n\tunion acpi_operand_object *buffer_obj;\n};\n\nstruct acpi_object_bank_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n\tunion acpi_operand_object *bank_obj;\n};\n\nstruct acpi_object_index_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *index_obj;\n\tunion acpi_operand_object *data_obj;\n};\n\ntypedef void (*acpi_notify_handler)(acpi_handle, u32, void *);\n\nstruct acpi_object_notify_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tu32 handler_type;\n\tacpi_notify_handler handler;\n\tvoid *context;\n\tunion acpi_operand_object *next[2];\n};\n\ntypedef acpi_status (*acpi_adr_space_handler)(u32, acpi_physical_address, u32, u64 *, void *, void *);\n\ntypedef acpi_status (*acpi_adr_space_setup)(acpi_handle, u32, void *, void **);\n\nstruct acpi_object_addr_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tu8 handler_flags;\n\tacpi_adr_space_handler handler;\n\tstruct acpi_namespace_node *node;\n\tvoid *context;\n\tvoid *context_mutex;\n\tacpi_adr_space_setup setup;\n\tunion acpi_operand_object *region_list;\n\tunion acpi_operand_object *next;\n};\n\nstruct acpi_object_reference {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 class;\n\tu8 target_type;\n\tu8 resolved;\n\tvoid *object;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **where;\n\tu8 *index_pointer;\n\tu8 *aml;\n\tu32 value;\n};\n\nstruct acpi_object_extra {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *method_REG;\n\tstruct acpi_namespace_node *scope_node;\n\tvoid *region_context;\n\tu8 *aml_start;\n\tu32 aml_length;\n};\n\ntypedef void (*acpi_object_handler)(acpi_handle, void *);\n\nstruct acpi_object_data {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tacpi_object_handler handler;\n\tvoid *pointer;\n};\n\nstruct acpi_object_cache_list {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *next;\n};\n\nunion acpi_name_union {\n\tu32 integer;\n\tchar ascii[4];\n};\n\nstruct acpi_namespace_node {\n\tunion acpi_operand_object *object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 flags;\n\tunion acpi_name_union name;\n\tstruct acpi_namespace_node *parent;\n\tstruct acpi_namespace_node *child;\n\tstruct acpi_namespace_node *peer;\n\tacpi_owner_id owner_id;\n};\n\nunion acpi_operand_object {\n\tstruct acpi_object_common common;\n\tstruct acpi_object_integer integer;\n\tstruct acpi_object_string string;\n\tstruct acpi_object_buffer buffer;\n\tstruct acpi_object_package package;\n\tstruct acpi_object_event event;\n\tstruct acpi_object_method method;\n\tstruct acpi_object_mutex mutex;\n\tstruct acpi_object_region region;\n\tstruct acpi_object_notify_common common_notify;\n\tstruct acpi_object_device device;\n\tstruct acpi_object_power_resource power_resource;\n\tstruct acpi_object_processor processor;\n\tstruct acpi_object_thermal_zone thermal_zone;\n\tstruct acpi_object_field_common common_field;\n\tstruct acpi_object_region_field field;\n\tstruct acpi_object_buffer_field buffer_field;\n\tstruct acpi_object_bank_field bank_field;\n\tstruct acpi_object_index_field index_field;\n\tstruct acpi_object_notify_handler notify;\n\tstruct acpi_object_addr_handler address_space;\n\tstruct acpi_object_reference reference;\n\tstruct acpi_object_extra extra;\n\tstruct acpi_object_data data;\n\tstruct acpi_object_cache_list cache;\n\tstruct acpi_namespace_node node;\n};\n\nunion acpi_parse_value {\n\tu64 integer;\n\tu32 size;\n\tchar *string;\n\tu8 *buffer;\n\tchar *name;\n\tunion acpi_parse_object *arg;\n};\n\nstruct acpi_parse_obj_common {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n};\n\nstruct acpi_parse_obj_named {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tchar *path;\n\tu8 *data;\n\tu32 length;\n\tu32 name;\n};\n\nstruct acpi_parse_obj_asl {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tunion acpi_parse_object *child;\n\tunion acpi_parse_object *parent_method;\n\tchar *filename;\n\tu8 file_changed;\n\tchar *parent_filename;\n\tchar *external_name;\n\tchar *namepath;\n\tchar name_seg[4];\n\tu32 extra_value;\n\tu32 column;\n\tu32 line_number;\n\tu32 logical_line_number;\n\tu32 logical_byte_offset;\n\tu32 end_line;\n\tu32 end_logical_line;\n\tu32 acpi_btype;\n\tu32 aml_length;\n\tu32 aml_subtree_length;\n\tu32 final_aml_length;\n\tu32 final_aml_offset;\n\tu32 compile_flags;\n\tu16 parse_opcode;\n\tu8 aml_opcode_length;\n\tu8 aml_pkg_len_bytes;\n\tu8 extra;\n\tchar parse_op_name[20];\n};\n\nunion acpi_parse_object {\n\tstruct acpi_parse_obj_common common;\n\tstruct acpi_parse_obj_named named;\n\tstruct acpi_parse_obj_asl asl;\n};\n\nunion acpi_descriptor {\n\tstruct acpi_common_descriptor common;\n\tunion acpi_operand_object object;\n\tstruct acpi_namespace_node node;\n\tunion acpi_parse_object op;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct acpi_dev_match_info {\n\tstruct acpi_device_id hid[2];\n\tconst char *uid;\n\ts64 hrv;\n};\n\nstruct acpi_dev_walk_context {\n\tint (*fn)(struct acpi_device *, void *);\n\tvoid *data;\n};\n\nstruct acpi_device_status {\n\tu32 present: 1;\n\tu32 enabled: 1;\n\tu32 show_in_ui: 1;\n\tu32 functional: 1;\n\tu32 battery_present: 1;\n\tu32 reserved: 27;\n};\n\nstruct acpi_device_flags {\n\tu32 dynamic_status: 1;\n\tu32 removable: 1;\n\tu32 ejectable: 1;\n\tu32 power_manageable: 1;\n\tu32 match_driver: 1;\n\tu32 initialized: 1;\n\tu32 visited: 1;\n\tu32 hotplug_notify: 1;\n\tu32 is_dock_station: 1;\n\tu32 of_compatible_ok: 1;\n\tu32 coherent_dma: 1;\n\tu32 cca_seen: 1;\n\tu32 enumeration_by_parent: 1;\n\tu32 honor_deps: 1;\n\tu32 reserved: 18;\n};\n\nstruct acpi_pnp_type {\n\tu32 hardware_id: 1;\n\tu32 bus_address: 1;\n\tu32 platform_id: 1;\n\tu32 backlight: 1;\n\tu32 reserved: 28;\n};\n\nstruct acpi_device_pnp {\n\tacpi_bus_id bus_id;\n\tint instance_no;\n\tstruct acpi_pnp_type type;\n\tacpi_bus_address bus_address;\n\tchar *unique_id;\n\tstruct list_head ids;\n\tacpi_device_name device_name;\n\tacpi_device_class device_class;\n};\n\nstruct acpi_device_power_flags {\n\tu32 explicit_get: 1;\n\tu32 power_resources: 1;\n\tu32 inrush_current: 1;\n\tu32 power_removed: 1;\n\tu32 ignore_parent: 1;\n\tu32 dsw_present: 1;\n\tu32 reserved: 26;\n};\n\nstruct acpi_device_power_state {\n\tstruct list_head resources;\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 explicit_set: 1;\n\t\tu8 reserved: 6;\n\t} flags;\n\tint power;\n\tint latency;\n};\n\nstruct acpi_device_power {\n\tint state;\n\tstruct acpi_device_power_flags flags;\n\tstruct acpi_device_power_state states[5];\n\tu8 state_for_enumeration;\n};\n\nstruct acpi_device_wakeup_flags {\n\tu8 valid: 1;\n\tu8 notifier_present: 1;\n};\n\nstruct acpi_device_wakeup_context {\n\tvoid (*func)(struct acpi_device_wakeup_context *);\n\tstruct device *dev;\n};\n\nstruct acpi_device_wakeup {\n\tacpi_handle gpe_device;\n\tu64 gpe_number;\n\tu64 sleep_state;\n\tstruct list_head resources;\n\tstruct acpi_device_wakeup_flags flags;\n\tstruct acpi_device_wakeup_context context;\n\tstruct wakeup_source *ws;\n\tint prepare_count;\n\tint enable_count;\n};\n\nstruct acpi_device_perf_flags {\n\tu8 reserved: 8;\n};\n\nstruct acpi_device_perf_state;\n\nstruct acpi_device_perf {\n\tint state;\n\tstruct acpi_device_perf_flags flags;\n\tint state_count;\n\tstruct acpi_device_perf_state *states;\n};\n\nstruct proc_dir_entry;\n\nstruct acpi_device_dir {\n\tstruct proc_dir_entry *entry;\n};\n\nstruct acpi_scan_handler;\n\nstruct acpi_hotplug_context;\n\nstruct acpi_device_software_nodes;\n\nstruct acpi_gpio_mapping;\n\nstruct acpi_device {\n\tu32 pld_crc;\n\tint device_type;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct list_head wakeup_list;\n\tstruct list_head del_list;\n\tstruct acpi_device_status status;\n\tstruct acpi_device_flags flags;\n\tstruct acpi_device_pnp pnp;\n\tstruct acpi_device_power power;\n\tstruct acpi_device_wakeup wakeup;\n\tstruct acpi_device_perf performance;\n\tstruct acpi_device_dir dir;\n\tstruct acpi_device_data data;\n\tstruct acpi_scan_handler *handler;\n\tstruct acpi_hotplug_context *hp;\n\tstruct acpi_device_software_nodes *swnodes;\n\tconst struct acpi_gpio_mapping *driver_gpios;\n\tvoid *driver_data;\n\tstruct device dev;\n\tunsigned int physical_node_count;\n\tunsigned int dep_unmet;\n\tstruct list_head physical_node_list;\n\tstruct mutex physical_node_lock;\n\tvoid (*remove)(struct acpi_device *);\n};\n\nstruct acpi_device_bus_id {\n\tconst char *bus_id;\n\tstruct ida instance_ida;\n\tstruct list_head node;\n};\n\nstruct acpi_pnp_device_id {\n\tu32 length;\n\tchar *string;\n};\n\nstruct acpi_pnp_device_id_list {\n\tu32 count;\n\tu32 list_size;\n\tstruct acpi_pnp_device_id ids[0];\n};\n\nstruct acpi_device_info {\n\tu32 info_size;\n\tu32 name;\n\tacpi_object_type type;\n\tu8 param_count;\n\tu16 valid;\n\tu8 flags;\n\tu8 highest_dstates[4];\n\tu8 lowest_dstates[5];\n\tu64 address;\n\tstruct acpi_pnp_device_id hardware_id;\n\tstruct acpi_pnp_device_id unique_id;\n\tstruct acpi_pnp_device_id class_code;\n\tstruct acpi_pnp_device_id_list compatible_id_list;\n};\n\ntypedef int (*acpi_op_add)(struct acpi_device *);\n\ntypedef void (*acpi_op_remove)(struct acpi_device *);\n\ntypedef void (*acpi_op_notify)(struct acpi_device *, u32);\n\nstruct acpi_device_ops {\n\tacpi_op_add add;\n\tacpi_op_remove remove;\n\tacpi_op_notify notify;\n};\n\nstruct acpi_device_perf_state {\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 reserved: 7;\n\t} flags;\n\tu8 power;\n\tu8 performance;\n\tint latency;\n};\n\nstruct acpi_device_physical_node {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int node_id;\n\tbool put_online: 1;\n};\n\nstruct acpi_device_properties {\n\tstruct list_head list;\n\tconst guid_t *guid;\n\tunion acpi_object *properties;\n\tvoid **bufs;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[1];\n\t\t} value;\n\t};\n};\n\nstruct software_node;\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct acpi_device_software_node_port {\n\tchar port_name[9];\n\tu32 data_lanes[8];\n\tu32 lane_polarities[9];\n\tu64 link_frequencies[8];\n\tunsigned int port_nr;\n\tbool crs_csi2_local;\n\tstruct property_entry port_props[2];\n\tstruct property_entry ep_props[8];\n\tstruct software_node_ref_args remote_ep[1];\n};\n\nstruct acpi_device_software_nodes {\n\tstruct property_entry dev_props[6];\n\tstruct software_node *nodes;\n\tconst struct software_node **nodeptrs;\n\tstruct acpi_device_software_node_port *ports;\n\tunsigned int num_ports;\n};\n\nstruct acpi_table_desc;\n\nstruct acpi_evaluate_info;\n\nstruct acpi_device_walk_info {\n\tstruct acpi_table_desc *table_desc;\n\tstruct acpi_evaluate_info *evaluate_info;\n\tu32 device_count;\n\tu32 num_STA;\n\tu32 num_INI;\n};\n\nstruct acpi_dlayer {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct acpi_dlevel {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct dma_chan;\n\nstruct acpi_dma_spec;\n\nstruct acpi_dma {\n\tstruct list_head dma_controllers;\n\tstruct device *dev;\n\tstruct dma_chan * (*acpi_dma_xlate)(struct acpi_dma_spec *, struct acpi_dma *);\n\tvoid *data;\n\tshort unsigned int base_request_line;\n\tshort unsigned int end_request_line;\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan *, void *);\n\nstruct acpi_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct acpi_dma_spec {\n\tint chan_id;\n\tint slave_id;\n\tstruct device *dev;\n};\n\nstruct acpi_dma_parser_data {\n\tstruct acpi_dma_spec dma_spec;\n\tsize_t index;\n\tsize_t n;\n};\n\nstruct acpi_dmar_header {\n\tu16 type;\n\tu16 length;\n};\n\nstruct acpi_dmar_andd {\n\tstruct acpi_dmar_header header;\n\tu8 reserved[3];\n\tu8 device_number;\n\tunion {\n\t\tchar __pad;\n\t\tstruct {\n\t\t\tstruct {} __Empty_device_name;\n\t\t\tchar device_name[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct acpi_dmar_atsr {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu16 segment;\n};\n\nstruct acpi_dmar_device_scope {\n\tu8 entry_type;\n\tu8 length;\n\tu8 flags;\n\tu8 reserved;\n\tu8 enumeration_id;\n\tu8 bus;\n};\n\nstruct acpi_dmar_hardware_unit {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 size;\n\tu16 segment;\n\tu64 address;\n};\n\nstruct acpi_dmar_pci_path {\n\tu8 device;\n\tu8 function;\n};\n\nstruct acpi_dmar_reserved_memory {\n\tstruct acpi_dmar_header header;\n\tu16 reserved;\n\tu16 segment;\n\tu64 base_address;\n\tu64 end_address;\n};\n\nstruct acpi_dmar_rhsa {\n\tstruct acpi_dmar_header header;\n\tu32 reserved;\n\tu64 base_address;\n\tu32 proximity_domain;\n} __attribute__((packed));\n\nstruct acpi_dmar_satc {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu16 segment;\n};\n\nstruct of_device_id;\n\nstruct dev_pm_ops;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct acpi_driver {\n\tchar name[80];\n\tchar class[80];\n\tconst struct acpi_device_id *ids;\n\tunsigned int flags;\n\tstruct acpi_device_ops ops;\n\tstruct device_driver drv;\n};\n\nstruct transaction;\n\nstruct acpi_ec {\n\tacpi_handle handle;\n\tint gpe;\n\tint irq;\n\tlong unsigned int command_addr;\n\tlong unsigned int data_addr;\n\tbool global_lock;\n\tlong unsigned int flags;\n\tlong unsigned int reference_count;\n\tstruct mutex mutex;\n\twait_queue_head_t wait;\n\tstruct list_head list;\n\tstruct transaction *curr;\n\tspinlock_t lock;\n\tstruct work_struct work;\n\tlong unsigned int timestamp;\n\tenum acpi_ec_event_state event_state;\n\tunsigned int events_to_process;\n\tunsigned int events_in_progress;\n\tunsigned int queries_in_progress;\n\tbool busy_polling;\n\tunsigned int polling_guard;\n};\n\nstruct transaction {\n\tconst u8 *wdata;\n\tu8 *rdata;\n\tshort unsigned int irq_count;\n\tu8 command;\n\tu8 wi;\n\tu8 ri;\n\tu8 wlen;\n\tu8 rlen;\n\tu8 flags;\n};\n\nstruct acpi_ec_query_handler;\n\nstruct acpi_ec_query {\n\tstruct transaction transaction;\n\tstruct work_struct work;\n\tstruct acpi_ec_query_handler *handler;\n\tstruct acpi_ec *ec;\n};\n\ntypedef int (*acpi_ec_query_func)(void *);\n\nstruct acpi_ec_query_handler {\n\tstruct list_head node;\n\tacpi_ec_query_func func;\n\tacpi_handle handle;\n\tvoid *data;\n\tu8 query_bit;\n\tstruct kref kref;\n};\n\nunion acpi_predefined_info;\n\nstruct acpi_evaluate_info {\n\tstruct acpi_namespace_node *prefix_node;\n\tconst char *relative_pathname;\n\tunion acpi_operand_object **parameters;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *obj_desc;\n\tchar *full_pathname;\n\tconst union acpi_predefined_info *predefined;\n\tunion acpi_operand_object *return_object;\n\tunion acpi_operand_object *parent_package;\n\tu32 return_flags;\n\tu32 return_btype;\n\tu16 param_count;\n\tu16 node_flags;\n\tu8 pass_number;\n\tu8 return_object_type;\n\tu8 flags;\n};\n\nstruct acpi_exception_info {\n\tchar *name;\n};\n\nstruct acpi_exdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n} __attribute__((packed));\n\nstruct acpi_fadt_info {\n\tconst char *name;\n\tu16 address64;\n\tu16 address32;\n\tu16 length;\n\tu8 default_length;\n\tu8 flags;\n};\n\nstruct acpi_generic_address;\n\nstruct acpi_fadt_pm_info {\n\tstruct acpi_generic_address *target;\n\tu16 source;\n\tu8 register_num;\n};\n\nstruct acpi_fan_fif {\n\tu8 revision;\n\tu8 fine_grain_ctrl;\n\tu8 step_size;\n\tu8 low_speed_notification;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct acpi_fan_fps;\n\nstruct thermal_cooling_device;\n\nstruct acpi_fan {\n\tacpi_handle handle;\n\tbool acpi4;\n\tbool has_fst;\n\tstruct acpi_fan_fif fif;\n\tstruct acpi_fan_fps *fps;\n\tint fps_count;\n\tu32 fan_trip_granularity;\n\tstruct device *hdev;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device_attribute fst_speed;\n\tstruct device_attribute fine_grain_control;\n};\n\nstruct acpi_fan_fps {\n\tu64 control;\n\tu64 trip_point;\n\tu64 speed;\n\tu64 noise_level;\n\tu64 power;\n\tchar name[20];\n\tstruct device_attribute dev_attr;\n};\n\nstruct acpi_fan_fst {\n\tu64 revision;\n\tu64 control;\n\tu64 speed;\n};\n\nstruct acpi_ffh_info {\n\tu64 offset;\n\tu64 length;\n};\n\ntypedef u32 (*acpi_event_handler)(void *);\n\nstruct acpi_fixed_event_handler {\n\tacpi_event_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_fixed_event_info {\n\tu8 status_register_id;\n\tu8 enable_register_id;\n\tu16 status_bit_mask;\n\tu16 enable_bit_mask;\n};\n\nstruct acpi_ged_device {\n\tstruct device *dev;\n\tstruct list_head event_list;\n};\n\nstruct acpi_ged_event {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int gsi;\n\tunsigned int irq;\n\tacpi_handle handle;\n};\n\nstruct acpi_ged_handler_info {\n\tstruct acpi_ged_handler_info *next;\n\tu32 int_id;\n\tstruct acpi_namespace_node *evt_method;\n};\n\nstruct acpi_generic_address {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_update_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *object;\n};\n\nstruct acpi_scope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_pscope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 arg_count;\n\tunion acpi_parse_object *op;\n\tu8 *arg_end;\n\tu8 *pkg_end;\n\tu32 arg_list;\n};\n\nstruct acpi_pkg_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 index;\n\tunion acpi_operand_object *source_object;\n\tunion acpi_operand_object *dest_object;\n\tstruct acpi_walk_state *walk_state;\n\tvoid *this_target_obj;\n\tu32 num_packages;\n};\n\nstruct acpi_thread_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 current_sync_level;\n\tstruct acpi_walk_state *walk_state_list;\n\tunion acpi_operand_object *acquired_mutex_list;\n\tu64 thread_id;\n};\n\nstruct acpi_result_values {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *obj_desc[8];\n};\n\nstruct acpi_global_notify_handler;\n\nstruct acpi_notify_info {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 handler_list_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler_list_head;\n\tstruct acpi_global_notify_handler *global;\n};\n\nunion acpi_generic_state {\n\tstruct acpi_common_state common;\n\tstruct acpi_control_state control;\n\tstruct acpi_update_state update;\n\tstruct acpi_scope_state scope;\n\tstruct acpi_pscope_state parse_scope;\n\tstruct acpi_pkg_state pkg;\n\tstruct acpi_thread_state thread;\n\tstruct acpi_result_values results;\n\tstruct acpi_notify_info notify;\n};\n\nstruct acpi_genl_event {\n\tacpi_device_class device_class;\n\tchar bus_id[15];\n\tu32 type;\n\tu32 data;\n};\n\ntypedef acpi_status (*acpi_walk_callback)(acpi_handle, u32, void *, void **);\n\nstruct acpi_get_devices_info {\n\tacpi_walk_callback user_function;\n\tvoid *context;\n\tconst char *hid;\n};\n\nstruct acpi_global_notify_handler {\n\tacpi_notify_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_gpe_address {\n\tu8 space_id;\n\tu64 address;\n};\n\nstruct acpi_gpe_xrupt_info;\n\nstruct acpi_gpe_register_info;\n\nstruct acpi_gpe_event_info;\n\nstruct acpi_gpe_block_info {\n\tstruct acpi_namespace_node *node;\n\tstruct acpi_gpe_block_info *previous;\n\tstruct acpi_gpe_block_info *next;\n\tstruct acpi_gpe_xrupt_info *xrupt_block;\n\tstruct acpi_gpe_register_info *register_info;\n\tstruct acpi_gpe_event_info *event_info;\n\tu64 address;\n\tu32 register_count;\n\tu16 gpe_count;\n\tu16 block_base_number;\n\tu8 space_id;\n\tu8 initialized;\n};\n\nstruct acpi_gpe_block_status_context {\n\tstruct acpi_gpe_register_info *gpe_skip_register_info;\n\tu8 gpe_skip_mask;\n\tu8 retval;\n};\n\nstruct acpi_gpe_device_info {\n\tu32 index;\n\tu32 next_block_base_index;\n\tacpi_status status;\n\tstruct acpi_namespace_node *gpe_device;\n};\n\nstruct acpi_gpe_handler_info;\n\nstruct acpi_gpe_notify_info;\n\nunion acpi_gpe_dispatch_info {\n\tstruct acpi_namespace_node *method_node;\n\tstruct acpi_gpe_handler_info *handler;\n\tstruct acpi_gpe_notify_info *notify_list;\n};\n\nstruct acpi_gpe_event_info {\n\tunion acpi_gpe_dispatch_info dispatch;\n\tstruct acpi_gpe_register_info *register_info;\n\tu8 flags;\n\tu8 gpe_number;\n\tu8 runtime_count;\n\tu8 disable_for_dispatch;\n};\n\ntypedef u32 (*acpi_gpe_handler)(acpi_handle, u32, void *);\n\nstruct acpi_gpe_handler_info {\n\tacpi_gpe_handler address;\n\tvoid *context;\n\tstruct acpi_namespace_node *method_node;\n\tu8 original_flags;\n\tu8 originally_enabled;\n};\n\nstruct acpi_gpe_notify_info {\n\tstruct acpi_namespace_node *device_node;\n\tstruct acpi_gpe_notify_info *next;\n};\n\nstruct acpi_gpe_register_info {\n\tstruct acpi_gpe_address status_address;\n\tstruct acpi_gpe_address enable_address;\n\tu16 base_gpe_number;\n\tu8 enable_for_wake;\n\tu8 enable_for_run;\n\tu8 mask_for_run;\n\tu8 enable_mask;\n};\n\nstruct acpi_gpe_walk_info {\n\tstruct acpi_namespace_node *gpe_device;\n\tstruct acpi_gpe_block_info *gpe_block;\n\tu16 count;\n\tacpi_owner_id owner_id;\n\tu8 execute_by_owner_id;\n};\n\nstruct acpi_gpe_xrupt_info {\n\tstruct acpi_gpe_xrupt_info *previous;\n\tstruct acpi_gpe_xrupt_info *next;\n\tstruct acpi_gpe_block_info *gpe_block_list_head;\n\tu32 interrupt_number;\n};\n\nstruct acpi_gpio_params;\n\nstruct acpi_gpio_mapping {\n\tconst char *name;\n\tconst struct acpi_gpio_params *data;\n\tunsigned int size;\n\tunsigned int quirks;\n};\n\nstruct acpi_gpio_params {\n\tunsigned int crs_entry_index;\n\tshort unsigned int line_index;\n\tbool active_low;\n};\n\nstruct acpi_handle_list {\n\tu32 count;\n\tacpi_handle *handles;\n};\n\nstruct acpi_hardware_id {\n\tstruct list_head list;\n\tconst char *id;\n};\n\nstruct acpi_hmat_structure {\n\tu16 type;\n\tu16 reserved;\n\tu32 length;\n};\n\ntypedef int (*acpi_hp_notify)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_uevent)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_fixup)(struct acpi_device *);\n\nstruct acpi_hotplug_context {\n\tstruct acpi_device *self;\n\tacpi_hp_notify notify;\n\tacpi_hp_uevent uevent;\n\tacpi_hp_fixup fixup;\n};\n\nstruct acpi_hotplug_profile {\n\tstruct kobject kobj;\n\tint (*scan_dependent)(struct acpi_device *);\n\tvoid (*notify_online)(struct acpi_device *);\n\tbool enabled: 1;\n\tbool demand_offline: 1;\n};\n\nstruct acpi_hp_work {\n\tstruct work_struct work;\n\tstruct acpi_device *adev;\n\tu32 src;\n};\n\nstruct acpi_init_walk_info {\n\tu32 table_index;\n\tu32 object_count;\n\tu32 method_count;\n\tu32 serial_method_count;\n\tu32 non_serial_method_count;\n\tu32 serialized_method_count;\n\tu32 device_count;\n\tu32 op_region_count;\n\tu32 field_count;\n\tu32 buffer_count;\n\tu32 package_count;\n\tu32 op_region_init;\n\tu32 field_init;\n\tu32 buffer_init;\n\tu32 package_init;\n\tacpi_owner_id owner_id;\n};\n\nstruct acpi_interface_info {\n\tchar *name;\n\tstruct acpi_interface_info *next;\n\tu8 flags;\n\tu8 value;\n};\n\nstruct acpi_io_attribute {\n\tu8 range_type;\n\tu8 translation;\n\tu8 translation_type;\n\tu8 reserved1;\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct acpi_ioremap {\n\tstruct list_head list;\n\tvoid *virt;\n\tacpi_physical_address phys;\n\tacpi_size size;\n\tunion {\n\t\tlong unsigned int refcount;\n\t\tstruct rcu_work rwork;\n\t} track;\n};\n\nstruct acpi_lpat {\n\tint temp;\n\tint raw;\n};\n\nstruct acpi_lpat_conversion_table {\n\tstruct acpi_lpat *lpat;\n\tint lpat_count;\n};\n\nstruct acpi_lpi_state {\n\tu32 min_residency;\n\tu32 wake_latency;\n\tu32 flags;\n\tu32 arch_flags;\n\tu32 res_cnt_freq;\n\tu32 enable_parent_state;\n\tu64 address;\n\tu8 index;\n\tu8 entry_method;\n\tchar desc[32];\n};\n\nstruct acpi_lpi_states_array {\n\tunsigned int size;\n\tunsigned int composite_states_size;\n\tstruct acpi_lpi_state *entries;\n\tstruct acpi_lpi_state *composite_states[8];\n};\n\nstruct acpi_lpit_header {\n\tu32 type;\n\tu32 length;\n\tu16 unique_id;\n\tu16 reserved;\n\tu32 flags;\n};\n\nstruct acpi_lpit_native {\n\tstruct acpi_lpit_header header;\n\tstruct acpi_generic_address entry_trigger;\n\tu32 residency;\n\tu32 latency;\n\tstruct acpi_generic_address residency_counter;\n\tu64 counter_frequency;\n};\n\nstruct acpi_subtable_header {\n\tu8 type;\n\tu8 length;\n};\n\nstruct acpi_madt_core_pic {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu32 processor_id;\n\tu32 core_id;\n\tu32 flags;\n} __attribute__((packed));\n\nstruct acpi_madt_generic_distributor {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 gic_id;\n\tu64 base_address;\n\tu32 global_irq_base;\n\tu8 version;\n\tu8 reserved2[3];\n};\n\nstruct acpi_madt_generic_interrupt {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 cpu_interface_number;\n\tu32 uid;\n\tu32 flags;\n\tu32 parking_version;\n\tu32 performance_interrupt;\n\tu64 parked_address;\n\tu64 base_address;\n\tu64 gicv_base_address;\n\tu64 gich_base_address;\n\tu32 vgic_interrupt;\n\tu64 gicr_base_address;\n\tu64 arm_mpidr;\n\tu8 efficiency_class;\n\tu8 reserved2[1];\n\tu16 spe_interrupt;\n\tu16 trbe_interrupt;\n\tu16 iaffid;\n\tu32 irs_id;\n} __attribute__((packed));\n\nstruct acpi_madt_interrupt_override {\n\tstruct acpi_subtable_header header;\n\tu8 bus;\n\tu8 source_irq;\n\tu32 global_irq;\n\tu16 inti_flags;\n} __attribute__((packed));\n\nstruct acpi_madt_interrupt_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu8 type;\n\tu8 id;\n\tu8 eid;\n\tu8 io_sapic_vector;\n\tu32 global_irq;\n\tu32 flags;\n};\n\nstruct acpi_madt_io_apic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 address;\n\tu32 global_irq_base;\n};\n\nstruct acpi_madt_io_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 global_irq_base;\n\tu64 address;\n};\n\nstruct acpi_madt_local_apic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu32 lapic_flags;\n};\n\nstruct acpi_madt_local_apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu16 inti_flags;\n\tu8 lint;\n} __attribute__((packed));\n\nstruct acpi_madt_local_apic_override {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_madt_local_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu8 eid;\n\tu8 reserved[3];\n\tu32 lapic_flags;\n\tu32 uid;\n\tchar uid_string[0];\n};\n\nstruct acpi_madt_local_x2apic {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 local_apic_id;\n\tu32 lapic_flags;\n\tu32 uid;\n};\n\nstruct acpi_madt_local_x2apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 uid;\n\tu8 lint;\n\tu8 reserved[3];\n};\n\nstruct acpi_madt_multiproc_wakeup {\n\tstruct acpi_subtable_header header;\n\tu16 version;\n\tu32 reserved;\n\tu64 mailbox_address;\n\tu64 reset_vector;\n};\n\nstruct acpi_madt_multiproc_wakeup_mailbox {\n\tu16 command;\n\tu16 reserved;\n\tu32 apic_id;\n\tu64 wakeup_vector;\n\tu8 reserved_os[2032];\n\tu8 reserved_firmware[2048];\n};\n\nstruct acpi_madt_nmi_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 global_irq;\n};\n\nstruct acpi_madt_rintc {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 reserved;\n\tu32 flags;\n\tu64 hart_id;\n\tu32 uid;\n\tu32 ext_intc_id;\n\tu64 imsic_addr;\n\tu32 imsic_size;\n} __attribute__((packed));\n\nstruct acpi_mcfg_allocation {\n\tu64 address;\n\tu16 pci_segment;\n\tu8 start_bus_number;\n\tu8 end_bus_number;\n\tu32 reserved;\n};\n\nstruct acpi_mem_mapping {\n\tacpi_physical_address physical_address;\n\tu8 *logical_address;\n\tacpi_size length;\n\tstruct acpi_mem_mapping *next_mm;\n};\n\nstruct acpi_mem_space_context {\n\tu32 length;\n\tacpi_physical_address address;\n\tstruct acpi_mem_mapping *cur_mm;\n\tstruct acpi_mem_mapping *first_mm;\n};\n\nstruct acpi_memory_attribute {\n\tu8 write_protect;\n\tu8 caching;\n\tu8 range_type;\n\tu8 translation;\n};\n\nstruct acpi_subtbl_hdr_16 {\n\tu16 type;\n\tu16 length;\n};\n\nstruct acpi_mrrm_mem_range_entry {\n\tstruct acpi_subtbl_hdr_16 header;\n\tu32 reserved0;\n\tu64 addr_base;\n\tu64 addr_len;\n\tu16 region_id_flags;\n\tu8 local_region_id;\n\tu8 remote_region_id;\n\tu32 reserved1;\n};\n\nstruct acpi_mutex_info {\n\tvoid *mutex;\n\tu32 use_count;\n\tu64 thread_id;\n};\n\nstruct acpi_name_info {\n\tchar name[4];\n\tu16 argument_list;\n\tu8 expected_btypes;\n} __attribute__((packed));\n\nstruct acpi_namestring_info {\n\tconst char *external_name;\n\tconst char *next_external_char;\n\tchar *internal_name;\n\tu32 length;\n\tu32 num_segments;\n\tu32 num_carats;\n\tu8 fully_qualified;\n};\n\nstruct acpi_nhlt_config {\n\tu32 capabilities_size;\n\tu8 capabilities[0];\n};\n\nstruct acpi_nhlt_gendevice_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n};\n\nstruct acpi_nhlt_micdevice_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n\tu8 array_type;\n};\n\nstruct acpi_nhlt_vendor_mic_config {\n\tu8 type;\n\tu8 panel;\n\tu16 speaker_position_distance;\n\tu16 horizontal_offset;\n\tu16 vertical_offset;\n\tu8 frequency_low_band;\n\tu8 frequency_high_band;\n\tu16 direction_angle;\n\tu16 elevation_angle;\n\tu16 work_vertical_angle_begin;\n\tu16 work_vertical_angle_end;\n\tu16 work_horizontal_angle_begin;\n\tu16 work_horizontal_angle_end;\n};\n\nstruct acpi_nhlt_vendor_micdevice_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n\tu8 array_type;\n\tu8 mics_count;\n\tstruct acpi_nhlt_vendor_mic_config mics[0];\n};\n\nunion acpi_nhlt_device_config {\n\tu8 virtual_slot;\n\tstruct acpi_nhlt_gendevice_config gen;\n\tstruct acpi_nhlt_micdevice_config mic;\n\tstruct acpi_nhlt_vendor_micdevice_config vendor_mic;\n};\n\nstruct acpi_nhlt_endpoint {\n\tu32 length;\n\tu8 link_type;\n\tu8 instance_id;\n\tu16 vendor_id;\n\tu16 device_id;\n\tu16 revision_id;\n\tu32 subsystem_id;\n\tu8 device_type;\n\tu8 direction;\n\tu8 virtual_bus_id;\n} __attribute__((packed));\n\nstruct acpi_nhlt_wave_formatext {\n\tu16 format_tag;\n\tu16 channel_count;\n\tu32 samples_per_sec;\n\tu32 avg_bytes_per_sec;\n\tu16 block_align;\n\tu16 bits_per_sample;\n\tu16 extra_format_size;\n\tu16 valid_bits_per_sample;\n\tu32 channel_mask;\n\tu8 subformat[16];\n};\n\nstruct acpi_nhlt_format_config {\n\tstruct acpi_nhlt_wave_formatext format;\n\tstruct acpi_nhlt_config config;\n};\n\nstruct acpi_nhlt_formats_config {\n\tu8 formats_count;\n\tstruct acpi_nhlt_format_config formats[0];\n} __attribute__((packed));\n\nunion acpi_object {\n\tacpi_object_type type;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu64 value;\n\t} integer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tchar *pointer;\n\t} string;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tu8 *pointer;\n\t} buffer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 count;\n\t\tunion acpi_object *elements;\n\t} package;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tacpi_object_type actual_type;\n\t\tacpi_handle handle;\n\t} reference;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 proc_id;\n\t\tacpi_io_address pblk_address;\n\t\tu32 pblk_length;\n\t} processor;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 system_level;\n\t\tu32 resource_order;\n\t} power_resource;\n};\n\nstruct acpi_object_list {\n\tu32 count;\n\tunion acpi_object *pointer;\n};\n\nstruct acpi_offsets {\n\tsize_t offset;\n\tu8 mode;\n};\n\nstruct acpi_opcode_info {\n\tchar *name;\n\tu32 parse_args;\n\tu32 runtime_args;\n\tu16 flags;\n\tu8 object_type;\n\tu8 class;\n\tu8 type;\n};\n\ntypedef void (*acpi_osd_exec_callback)(void *);\n\nstruct acpi_os_dpc {\n\tacpi_osd_exec_callback function;\n\tvoid *context;\n\tstruct work_struct work;\n};\n\nstruct acpi_osc_context {\n\tchar *uuid_str;\n\tint rev;\n\tstruct acpi_buffer cap;\n\tstruct acpi_buffer ret;\n};\n\nstruct acpi_osi_config {\n\tu8 default_disabling;\n\tunsigned int linux_enable: 1;\n\tunsigned int linux_dmi: 1;\n\tunsigned int linux_cmdline: 1;\n\tunsigned int darwin_enable: 1;\n\tunsigned int darwin_dmi: 1;\n\tunsigned int darwin_cmdline: 1;\n};\n\nstruct acpi_osi_entry {\n\tchar string[64];\n\tbool enable;\n};\n\nstruct acpi_package_info {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 object_type2;\n\tu8 count2;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info2 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[4];\n\tu8 reserved;\n};\n\nstruct acpi_package_info3 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[2];\n\tu8 tail_object_type;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info4 {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 sub_object_types;\n\tu8 pkg_count;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_parse_state {\n\tu8 *aml_start;\n\tu8 *aml;\n\tu8 *aml_end;\n\tu8 *pkg_start;\n\tu8 *pkg_end;\n\tunion acpi_parse_object *start_op;\n\tstruct acpi_namespace_node *start_node;\n\tunion acpi_generic_state *scope;\n\tunion acpi_parse_object *start_scope;\n\tu32 aml_size;\n};\n\nstruct acpi_pcc_info {\n\tu8 subspace_id;\n\tu16 length;\n\tu8 *internal_buffer;\n};\n\nstruct acpi_pcct_ext_pcc_master {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved1;\n\tu64 base_address;\n\tu32 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu32 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_set_mask;\n\tu64 reserved2;\n\tstruct acpi_generic_address cmd_complete_register;\n\tu64 cmd_complete_mask;\n\tstruct acpi_generic_address cmd_update_register;\n\tu64 cmd_update_preserve_mask;\n\tu64 cmd_update_set_mask;\n\tstruct acpi_generic_address error_status_register;\n\tu64 error_status_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_ext_pcc_shared_memory {\n\tu32 signature;\n\tu32 flags;\n\tu32 length;\n\tu32 command;\n};\n\nstruct acpi_pcct_hw_reduced {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pcct_hw_reduced_type2 {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_write_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_shared_memory {\n\tu32 signature;\n\tu16 command;\n\tu16 status;\n};\n\nstruct acpi_pcct_subspace {\n\tstruct acpi_subtable_header header;\n\tu8 reserved[6];\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pci_device {\n\tacpi_handle device;\n\tstruct acpi_pci_device *next;\n};\n\nstruct acpi_pci_id {\n\tu16 segment;\n\tu16 bus;\n\tu16 device;\n\tu16 function;\n};\n\nstruct acpi_pci_ioapic {\n\tacpi_handle root_handle;\n\tacpi_handle handle;\n\tu32 gsi_base;\n\tstruct resource res;\n\tstruct pci_dev *pdev;\n\tstruct list_head list;\n};\n\nstruct acpi_pci_link_irq {\n\tu32 active;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 resource_type;\n\tu8 possible_count;\n\tu32 possible[16];\n\tu8 initialized: 1;\n\tu8 reserved: 7;\n};\n\nstruct acpi_pci_link {\n\tstruct list_head list;\n\tstruct acpi_device *device;\n\tstruct acpi_pci_link_irq irq;\n\tint refcnt;\n};\n\nstruct pci_bus;\n\nstruct acpi_pci_root {\n\tstruct acpi_device *device;\n\tstruct pci_bus *bus;\n\tu16 segment;\n\tint bridge_type;\n\tstruct resource secondary;\n\tu32 osc_support_set;\n\tu32 osc_control_set;\n\tu32 osc_ext_support_set;\n\tu32 osc_ext_control_set;\n\tphys_addr_t mcfg_addr;\n};\n\nstruct acpi_pci_root_ops;\n\nstruct acpi_pci_root_info {\n\tstruct acpi_pci_root *root;\n\tstruct acpi_device *bridge;\n\tstruct acpi_pci_root_ops *ops;\n\tstruct list_head resources;\n\tchar name[16];\n};\n\nstruct pci_ops;\n\nstruct acpi_pci_root_ops {\n\tstruct pci_ops *pci_ops;\n\tint (*init_info)(struct acpi_pci_root_info *);\n\tvoid (*release_info)(struct acpi_pci_root_info *);\n\tint (*prepare_resources)(struct acpi_pci_root_info *);\n};\n\nstruct acpi_pci_routing_table {\n\tu32 length;\n\tu32 pin;\n\tu64 address;\n\tu32 source_index;\n\tunion {\n\t\tchar pad[4];\n\t\tstruct {\n\t\t\tstruct {} __Empty_source;\n\t\t\tchar source[0];\n\t\t};\n\t};\n};\n\nstruct acpi_pct_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_pkg_info {\n\tu8 *free_space;\n\tacpi_size length;\n\tu32 object_space;\n\tu32 num_packages;\n};\n\nstruct acpi_platform_list {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n\tchar *table;\n\tenum acpi_predicate pred;\n\tchar *reason;\n\tu32 data;\n};\n\nstruct acpi_pld_info {\n\tu8 revision;\n\tu8 ignore_color;\n\tu8 red;\n\tu8 green;\n\tu8 blue;\n\tu16 width;\n\tu16 height;\n\tu8 user_visible;\n\tu8 dock;\n\tu8 lid;\n\tu8 panel;\n\tu8 vertical_position;\n\tu8 horizontal_position;\n\tu8 shape;\n\tu8 group_orientation;\n\tu8 group_token;\n\tu8 group_position;\n\tu8 bay;\n\tu8 ejectable;\n\tu8 ospm_eject_required;\n\tu8 cabinet_number;\n\tu8 card_cage_number;\n\tu8 reference;\n\tu8 rotation;\n\tu8 order;\n\tu8 reserved;\n\tu16 vertical_offset;\n\tu16 horizontal_offset;\n};\n\nstruct acpi_port_info {\n\tchar *name;\n\tu16 start;\n\tu16 end;\n\tu8 osi_dependency;\n};\n\nstruct acpi_power_dependent_device {\n\tstruct device *dev;\n\tstruct list_head node;\n};\n\nstruct acpi_power_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_power_resource {\n\tstruct acpi_device device;\n\tstruct list_head list_node;\n\tu32 system_level;\n\tu32 order;\n\tunsigned int ref_count;\n\tu8 state;\n\tstruct mutex resource_lock;\n\tstruct list_head dependents;\n};\n\nstruct acpi_power_resource_entry {\n\tstruct list_head node;\n\tstruct acpi_power_resource *resource;\n};\n\nunion acpi_predefined_info {\n\tstruct acpi_name_info info;\n\tstruct acpi_package_info ret_info;\n\tstruct acpi_package_info2 ret_info2;\n\tstruct acpi_package_info3 ret_info3;\n\tstruct acpi_package_info4 ret_info4;\n};\n\nstruct acpi_predefined_names {\n\tconst char *name;\n\tu8 type;\n\tchar *val;\n};\n\nstruct acpi_prmt_handler_info {\n\tu16 revision;\n\tu16 length;\n\tu8 handler_guid[16];\n\tu64 handler_address;\n\tu64 static_data_buffer_address;\n\tu64 acpi_param_buffer_address;\n} __attribute__((packed));\n\nstruct acpi_prmt_module_header {\n\tu16 revision;\n\tu16 length;\n};\n\nstruct acpi_prmt_module_info {\n\tu16 revision;\n\tu16 length;\n\tu8 module_guid[16];\n\tu16 major_rev;\n\tu16 minor_rev;\n\tu16 handler_info_count;\n\tu32 handler_info_offset;\n\tu64 mmio_list_pointer;\n} __attribute__((packed));\n\nstruct acpi_probe_entry;\n\ntypedef bool (*acpi_probe_entry_validate_subtbl)(struct acpi_subtable_header *, struct acpi_probe_entry *);\n\nstruct acpi_table_header;\n\ntypedef int (*acpi_tbl_table_handler)(struct acpi_table_header *);\n\nunion acpi_subtable_headers;\n\ntypedef int (*acpi_tbl_entry_handler)(union acpi_subtable_headers *, const long unsigned int);\n\nstruct acpi_probe_entry {\n\t__u8 id[5];\n\t__u8 type;\n\tacpi_probe_entry_validate_subtbl subtable_valid;\n\tunion {\n\t\tacpi_tbl_table_handler probe_table;\n\t\tacpi_tbl_entry_handler probe_subtbl;\n\t};\n\tkernel_ulong_t driver_data;\n};\n\nstruct acpi_processor_flags {\n\tu8 power: 1;\n\tu8 performance: 1;\n\tu8 throttling: 1;\n\tu8 limit: 1;\n\tu8 bm_control: 1;\n\tu8 bm_check: 1;\n\tu8 has_cst: 1;\n\tu8 has_lpi: 1;\n\tu8 power_setup_done: 1;\n\tu8 bm_rld_set: 1;\n\tu8 previously_online: 1;\n};\n\nstruct acpi_processor_cx {\n\tu8 valid;\n\tu8 type;\n\tu32 address;\n\tu8 entry_method;\n\tu8 index;\n\tu32 latency;\n\tu8 bm_sts_skip;\n\tchar desc[32];\n};\n\nstruct acpi_processor_power {\n\tint count;\n\tunion {\n\t\tstruct acpi_processor_cx states[8];\n\t\tstruct acpi_lpi_state lpi_states[8];\n\t};\n\tint timer_broadcast_on_state;\n};\n\nstruct acpi_tsd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_processor_tx {\n\tu16 power;\n\tu16 performance;\n};\n\nstruct acpi_processor_tx_tss;\n\nstruct acpi_processor;\n\nstruct acpi_processor_throttling {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_tx_tss *states_tss;\n\tstruct acpi_tsd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tint (*acpi_processor_get_throttling)(struct acpi_processor *);\n\tint (*acpi_processor_set_throttling)(struct acpi_processor *, int, bool);\n\tu32 address;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 tsd_valid_flag;\n\tunsigned int shared_type;\n\tstruct acpi_processor_tx states[16];\n};\n\nstruct acpi_processor_lx {\n\tint px;\n\tint tx;\n};\n\nstruct acpi_processor_limit {\n\tstruct acpi_processor_lx state;\n\tstruct acpi_processor_lx thermal;\n\tstruct acpi_processor_lx user;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct freq_constraints;\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct acpi_processor_performance;\n\nstruct acpi_processor {\n\tacpi_handle handle;\n\tu32 acpi_id;\n\tphys_cpuid_t phys_id;\n\tu32 id;\n\tu32 pblk;\n\tint performance_platform_limit;\n\tint throttling_platform_limit;\n\tstruct acpi_processor_flags flags;\n\tstruct acpi_processor_power power;\n\tstruct acpi_processor_performance *performance;\n\tstruct acpi_processor_throttling throttling;\n\tstruct acpi_processor_limit limit;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device *dev;\n\tstruct freq_qos_request perflib_req;\n\tstruct freq_qos_request thermal_req;\n};\n\nstruct acpi_processor_errata {\n\tu8 smp;\n\tstruct {\n\t\tu8 throttle: 1;\n\t\tu8 fdma: 1;\n\t\tu8 reserved: 6;\n\t\tu32 bmisx;\n\t} piix4;\n};\n\nstruct acpi_psd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_processor_px;\n\nstruct acpi_processor_performance {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_px *states;\n\tstruct acpi_psd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tunsigned int shared_type;\n};\n\nstruct acpi_processor_px {\n\tu64 core_frequency;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 bus_master_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_processor_throttling_arg {\n\tstruct acpi_processor *pr;\n\tint target_state;\n\tbool force;\n};\n\nstruct acpi_processor_tx_tss {\n\tu64 freqpercentage;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_prt_entry {\n\tstruct acpi_pci_id id;\n\tu8 pin;\n\tacpi_handle link;\n\tu32 index;\n};\n\nstruct acpi_reg_walk_info {\n\tu32 function;\n\tu32 reg_run_count;\n\tacpi_adr_space_type space_id;\n};\n\ntypedef acpi_status (*acpi_repair_function)(struct acpi_evaluate_info *, union acpi_operand_object **);\n\nstruct acpi_repair_info {\n\tchar name[4];\n\tacpi_repair_function repair_function;\n};\n\nstruct acpi_resource_irq {\n\tu8 descriptor_length;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tunion {\n\t\tu8 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu8 interrupts[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_dma {\n\tu8 type;\n\tu8 bus_master;\n\tu8 transfer;\n\tu8 channel_count;\n\tunion {\n\t\tu8 channel;\n\t\tstruct {\n\t\t\tstruct {} __Empty_channels;\n\t\t\tu8 channels[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_start_dependent {\n\tu8 descriptor_length;\n\tu8 compatibility_priority;\n\tu8 performance_robustness;\n};\n\nstruct acpi_resource_io {\n\tu8 io_decode;\n\tu8 alignment;\n\tu8 address_length;\n\tu16 minimum;\n\tu16 maximum;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_io {\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_dma {\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct acpi_resource_vendor {\n\tu16 byte_length;\n\tu8 byte_data[0];\n};\n\nstruct acpi_resource_vendor_typed {\n\tu16 byte_length;\n\tu8 uuid_subtype;\n\tu8 uuid[16];\n\tu8 byte_data[0];\n} __attribute__((packed));\n\nstruct acpi_resource_end_tag {\n\tu8 checksum;\n};\n\nstruct acpi_resource_memory24 {\n\tu8 write_protect;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_memory32 {\n\tu8 write_protect;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_memory32 {\n\tu8 write_protect;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nunion acpi_resource_attribute {\n\tstruct acpi_memory_attribute mem;\n\tstruct acpi_io_attribute io;\n\tu8 type_specific;\n};\n\nstruct acpi_resource_source {\n\tu8 index;\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_address16 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address16_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address32 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address32_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address64_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tu8 revision_ID;\n\tstruct acpi_address64_attribute address;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_irq {\n\tu8 producer_consumer;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tstruct acpi_resource_source resource_source;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct acpi_resource_generic_register {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_resource_gpio {\n\tu8 revision_id;\n\tu8 connection_type;\n\tu8 producer_consumer;\n\tu8 pin_config;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 io_restriction;\n\tu8 triggering;\n\tu8 polarity;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_i2c_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 access_mode;\n\tu16 slave_address;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_spi_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 wire_mode;\n\tu8 device_polarity;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_uart_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 endian;\n\tu8 data_bits;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 parity;\n\tu8 lines_enabled;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu32 default_baud_rate;\n} __attribute__((packed));\n\nstruct acpi_resource_csi2_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 local_port_instance;\n\tu8 phy_type;\n} __attribute__((packed));\n\nstruct acpi_resource_common_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_function {\n\tu8 revision_id;\n\tu8 pin_config;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_label {\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tu16 *pin_table;\n\tstruct acpi_resource_label resource_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_function {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_clock_input {\n\tu8 revision_id;\n\tu8 mode;\n\tu8 scale;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n};\n\nunion acpi_resource_data {\n\tstruct acpi_resource_irq irq;\n\tstruct acpi_resource_dma dma;\n\tstruct acpi_resource_start_dependent start_dpf;\n\tstruct acpi_resource_io io;\n\tstruct acpi_resource_fixed_io fixed_io;\n\tstruct acpi_resource_fixed_dma fixed_dma;\n\tstruct acpi_resource_vendor vendor;\n\tstruct acpi_resource_vendor_typed vendor_typed;\n\tstruct acpi_resource_end_tag end_tag;\n\tstruct acpi_resource_memory24 memory24;\n\tstruct acpi_resource_memory32 memory32;\n\tstruct acpi_resource_fixed_memory32 fixed_memory32;\n\tstruct acpi_resource_address16 address16;\n\tstruct acpi_resource_address32 address32;\n\tstruct acpi_resource_address64 address64;\n\tstruct acpi_resource_extended_address64 ext_address64;\n\tstruct acpi_resource_extended_irq extended_irq;\n\tstruct acpi_resource_generic_register generic_reg;\n\tstruct acpi_resource_gpio gpio;\n\tstruct acpi_resource_i2c_serialbus i2c_serial_bus;\n\tstruct acpi_resource_spi_serialbus spi_serial_bus;\n\tstruct acpi_resource_uart_serialbus uart_serial_bus;\n\tstruct acpi_resource_csi2_serialbus csi2_serial_bus;\n\tstruct acpi_resource_common_serialbus common_serial_bus;\n\tstruct acpi_resource_pin_function pin_function;\n\tstruct acpi_resource_pin_config pin_config;\n\tstruct acpi_resource_pin_group pin_group;\n\tstruct acpi_resource_pin_group_function pin_group_function;\n\tstruct acpi_resource_pin_group_config pin_group_config;\n\tstruct acpi_resource_clock_input clock_input;\n\tstruct acpi_resource_address address;\n};\n\nstruct acpi_resource {\n\tu32 type;\n\tu32 length;\n\tunion acpi_resource_data data;\n};\n\nstruct acpi_rsconvert_info {\n\tu8 opcode;\n\tu8 resource_offset;\n\tu8 aml_offset;\n\tu8 value;\n};\n\nstruct acpi_rsdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n\tconst char **pointer;\n} __attribute__((packed));\n\nstruct acpi_rw_lock {\n\tvoid *writer_mutex;\n\tvoid *reader_mutex;\n\tu32 num_readers;\n};\n\nstruct acpi_s2idle_dev_ops {\n\tstruct list_head list_node;\n\tvoid (*prepare)(void);\n\tvoid (*check)(void);\n\tvoid (*restore)(void);\n};\n\nstruct acpi_scan_handler {\n\tstruct list_head list_node;\n\tconst struct acpi_device_id *ids;\n\tbool (*match)(const char *, const struct acpi_device_id **);\n\tint (*attach)(struct acpi_device *, const struct acpi_device_id *);\n\tvoid (*detach)(struct acpi_device *);\n\tvoid (*post_eject)(struct acpi_device *);\n\tvoid (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n\tstruct acpi_hotplug_profile hotplug;\n};\n\nstruct acpi_scan_system_dev {\n\tstruct list_head node;\n\tstruct acpi_device *adev;\n};\n\ntypedef u32 (*acpi_sci_handler)(void *);\n\nstruct acpi_sci_handler_info {\n\tstruct acpi_sci_handler_info *next;\n\tacpi_sci_handler address;\n\tvoid *context;\n};\n\nstruct acpi_signal_fatal_info {\n\tu32 type;\n\tu32 code;\n\tu32 argument;\n};\n\ntypedef acpi_status (*acpi_object_converter)(struct acpi_namespace_node *, union acpi_operand_object *, union acpi_operand_object **);\n\nstruct acpi_simple_repair_info {\n\tchar name[4];\n\tu32 unexpected_btypes;\n\tu32 package_index;\n\tacpi_object_converter object_converter;\n};\n\nstruct acpi_srat_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 proximity_domain_lo;\n\tu8 apic_id;\n\tu32 flags;\n\tu8 local_sapic_eid;\n\tu8 proximity_domain_hi[3];\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_generic_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 reserved;\n\tu8 device_handle_type;\n\tu32 proximity_domain;\n\tu8 device_handle[16];\n\tu32 flags;\n\tu32 reserved1;\n};\n\nstruct acpi_srat_gicc_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n} __attribute__((packed));\n\nstruct acpi_srat_mem_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu16 reserved;\n\tu64 base_address;\n\tu64 length;\n\tu32 reserved1;\n\tu32 flags;\n\tu64 reserved2;\n} __attribute__((packed));\n\nstruct acpi_srat_rintc_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_x2apic_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 apic_id;\n\tu32 flags;\n\tu32 clock_domain;\n\tu32 reserved2;\n};\n\nstruct acpi_subtable_entry {\n\tunion acpi_subtable_headers *hdr;\n\tenum acpi_subtable_type type;\n};\n\nunion acpi_subtable_headers {\n\tstruct acpi_subtable_header common;\n\tstruct acpi_hmat_structure hmat;\n\tstruct acpi_prmt_module_header prmt;\n\tstruct acpi_cedt_header cedt;\n\tstruct acpi_cdat_header cdat;\n};\n\ntypedef int (*acpi_tbl_entry_handler_arg)(union acpi_subtable_headers *, void *, const long unsigned int);\n\nstruct acpi_subtable_proc {\n\tint id;\n\tacpi_tbl_entry_handler handler;\n\tacpi_tbl_entry_handler_arg handler_arg;\n\tvoid *arg;\n\tint count;\n};\n\nstruct acpi_table_attr {\n\tstruct bin_attribute attr;\n\tchar name[4];\n\tint instance;\n\tchar filename[8];\n\tstruct list_head node;\n};\n\nstruct acpi_table_header {\n\tchar signature[4];\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tchar oem_id[6];\n\tchar oem_table_id[8];\n\tu32 oem_revision;\n\tchar asl_compiler_id[4];\n\tu32 asl_compiler_revision;\n};\n\nstruct acpi_table_bert {\n\tstruct acpi_table_header header;\n\tu32 region_length;\n\tu64 address;\n};\n\nstruct acpi_table_bgrt {\n\tstruct acpi_table_header header;\n\tu16 version;\n\tu8 status;\n\tu8 image_type;\n\tu64 image_address;\n\tu32 image_offset_x;\n\tu32 image_offset_y;\n};\n\nstruct acpi_table_boot {\n\tstruct acpi_table_header header;\n\tu8 cmos_index;\n\tu8 reserved[3];\n};\n\nstruct acpi_table_ccel {\n\tstruct acpi_table_header header;\n\tu8 CCtype;\n\tu8 Ccsub_type;\n\tu16 reserved;\n\tu64 log_area_minimum_length;\n\tu64 log_area_start_address;\n};\n\nstruct acpi_table_cdat {\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tu8 reserved[6];\n\tu32 sequence;\n};\n\nstruct acpi_table_csrt {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_table_desc {\n\tacpi_physical_address address;\n\tstruct acpi_table_header *pointer;\n\tu32 length;\n\tunion acpi_name_union signature;\n\tacpi_owner_id owner_id;\n\tu8 flags;\n\tu16 validation_count;\n};\n\nstruct acpi_table_dmar {\n\tstruct acpi_table_header header;\n\tu8 width;\n\tu8 flags;\n\tu8 reserved[10];\n};\n\nstruct acpi_table_ecdt {\n\tstruct acpi_table_header header;\n\tstruct acpi_generic_address control;\n\tstruct acpi_generic_address data;\n\tu32 uid;\n\tu8 gpe;\n\tu8 id[0];\n} __attribute__((packed));\n\nstruct acpi_table_facs {\n\tchar signature[4];\n\tu32 length;\n\tu32 hardware_signature;\n\tu32 firmware_waking_vector;\n\tu32 global_lock;\n\tu32 flags;\n\tu64 xfirmware_waking_vector;\n\tu8 version;\n\tu8 reserved[3];\n\tu32 ospm_flags;\n\tu8 reserved1[24];\n};\n\nstruct acpi_table_fadt {\n\tstruct acpi_table_header header;\n\tu32 facs;\n\tu32 dsdt;\n\tu8 model;\n\tu8 preferred_profile;\n\tu16 sci_interrupt;\n\tu32 smi_command;\n\tu8 acpi_enable;\n\tu8 acpi_disable;\n\tu8 s4_bios_request;\n\tu8 pstate_control;\n\tu32 pm1a_event_block;\n\tu32 pm1b_event_block;\n\tu32 pm1a_control_block;\n\tu32 pm1b_control_block;\n\tu32 pm2_control_block;\n\tu32 pm_timer_block;\n\tu32 gpe0_block;\n\tu32 gpe1_block;\n\tu8 pm1_event_length;\n\tu8 pm1_control_length;\n\tu8 pm2_control_length;\n\tu8 pm_timer_length;\n\tu8 gpe0_block_length;\n\tu8 gpe1_block_length;\n\tu8 gpe1_base;\n\tu8 cst_control;\n\tu16 c2_latency;\n\tu16 c3_latency;\n\tu16 flush_size;\n\tu16 flush_stride;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 day_alarm;\n\tu8 month_alarm;\n\tu8 century;\n\tu16 boot_flags;\n\tu8 reserved;\n\tu32 flags;\n\tstruct acpi_generic_address reset_register;\n\tu8 reset_value;\n\tu16 arm_boot_flags;\n\tu8 minor_revision;\n\tu64 Xfacs;\n\tu64 Xdsdt;\n\tstruct acpi_generic_address xpm1a_event_block;\n\tstruct acpi_generic_address xpm1b_event_block;\n\tstruct acpi_generic_address xpm1a_control_block;\n\tstruct acpi_generic_address xpm1b_control_block;\n\tstruct acpi_generic_address xpm2_control_block;\n\tstruct acpi_generic_address xpm_timer_block;\n\tstruct acpi_generic_address xgpe0_block;\n\tstruct acpi_generic_address xgpe1_block;\n\tstruct acpi_generic_address sleep_control;\n\tstruct acpi_generic_address sleep_status;\n\tu64 hypervisor_id;\n} __attribute__((packed));\n\nstruct acpi_table_hpet {\n\tstruct acpi_table_header header;\n\tu32 id;\n\tstruct acpi_generic_address address;\n\tu8 sequence;\n\tu16 minimum_tick;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct acpi_table_list {\n\tstruct acpi_table_desc *tables;\n\tu32 current_table_count;\n\tu32 max_table_count;\n\tu8 flags;\n};\n\nstruct acpi_table_lpit {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_table_madt {\n\tstruct acpi_table_header header;\n\tu32 address;\n\tu32 flags;\n};\n\nstruct acpi_table_mcfg {\n\tstruct acpi_table_header header;\n\tu8 reserved[8];\n};\n\nstruct acpi_table_mrrm {\n\tstruct acpi_table_header header;\n\tu8 max_mem_region;\n\tu8 flags;\n\tu8 reserved[26];\n\tu8 memory_range_entry[0];\n};\n\nstruct acpi_table_nhlt {\n\tstruct acpi_table_header header;\n\tu8 endpoints_count;\n} __attribute__((packed));\n\nstruct acpi_table_pcct {\n\tstruct acpi_table_header header;\n\tu32 flags;\n\tu64 reserved;\n};\n\nstruct acpi_table_rsdp {\n\tchar signature[8];\n\tu8 checksum;\n\tchar oem_id[6];\n\tu8 revision;\n\tu32 rsdt_physical_address;\n\tu32 length;\n\tu64 xsdt_physical_address;\n\tu8 extended_checksum;\n\tu8 reserved[3];\n} __attribute__((packed));\n\nstruct acpi_table_slit {\n\tstruct acpi_table_header header;\n\tu64 locality_count;\n\tu8 entry[0];\n} __attribute__((packed));\n\nstruct acpi_table_spcr {\n\tstruct acpi_table_header header;\n\tu8 interface_type;\n\tu8 reserved[3];\n\tstruct acpi_generic_address serial_port;\n\tu8 interrupt_type;\n\tu8 pc_interrupt;\n\tu32 interrupt;\n\tu8 baud_rate;\n\tu8 parity;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 terminal_type;\n\tu8 language;\n\tu16 pci_device_id;\n\tu16 pci_vendor_id;\n\tu8 pci_bus;\n\tu8 pci_device;\n\tu8 pci_function;\n\tu32 pci_flags;\n\tu8 pci_segment;\n\tu32 uart_clk_freq;\n\tu32 precise_baudrate;\n\tu16 name_space_string_length;\n\tu16 name_space_string_offset;\n\tchar name_space_string[0];\n} __attribute__((packed));\n\nstruct acpi_table_srat {\n\tstruct acpi_table_header header;\n\tu32 table_revision;\n\tu64 reserved;\n};\n\nstruct acpi_table_stao {\n\tstruct acpi_table_header header;\n\tu8 ignore_uart;\n} __attribute__((packed));\n\nstruct acpi_table_viot {\n\tstruct acpi_table_header header;\n\tu16 node_count;\n\tu16 node_offset;\n\tu8 reserved[8];\n};\n\nstruct acpi_thermal_trip {\n\tlong unsigned int temp_dk;\n\tstruct acpi_handle_list devices;\n};\n\nstruct acpi_thermal_passive {\n\tstruct acpi_thermal_trip trip;\n\tlong unsigned int tc1;\n\tlong unsigned int tc2;\n\tlong unsigned int delay;\n};\n\nstruct acpi_thermal_active {\n\tstruct acpi_thermal_trip trip;\n};\n\nstruct acpi_thermal_trips {\n\tstruct acpi_thermal_passive passive;\n\tstruct acpi_thermal_active active[10];\n};\n\nstruct thermal_zone_device;\n\nstruct acpi_thermal {\n\tstruct acpi_device *device;\n\tacpi_bus_id name;\n\tlong unsigned int temp_dk;\n\tlong unsigned int last_temp_dk;\n\tlong unsigned int polling_frequency;\n\tvolatile u8 zombie;\n\tstruct acpi_thermal_trips trips;\n\tstruct thermal_zone_device *thermal_zone;\n\tint kelvin_offset;\n\tstruct work_struct thermal_check_work;\n\tstruct mutex thermal_check_lock;\n\trefcount_t thermal_check_count;\n};\n\nstruct acpi_vendor_uuid {\n\tu8 subtype;\n\tu8 data[16];\n};\n\nstruct acpi_vendor_walk_info {\n\tstruct acpi_vendor_uuid *uuid;\n\tstruct acpi_buffer *buffer;\n\tacpi_status status;\n};\n\nstruct acpi_video_brightness_flags {\n\tu8 _BCL_no_ac_battery_levels: 1;\n\tu8 _BCL_reversed: 1;\n\tu8 _BQC_use_index: 1;\n};\n\nstruct acpi_video_bus_cap {\n\tu8 _DOS: 1;\n\tu8 _DOD: 1;\n\tu8 _ROM: 1;\n\tu8 _GPD: 1;\n\tu8 _SPD: 1;\n\tu8 _VPO: 1;\n\tu8 reserved: 2;\n};\n\nstruct acpi_video_bus_flags {\n\tu8 multihead: 1;\n\tu8 rom: 1;\n\tu8 post: 1;\n\tu8 reserved: 5;\n};\n\nstruct acpi_video_enumerated_device;\n\nstruct acpi_video_bus {\n\tstruct acpi_device *device;\n\tbool backlight_registered;\n\tu8 dos_setting;\n\tstruct acpi_video_enumerated_device *attached_array;\n\tu8 attached_count;\n\tu8 child_count;\n\tstruct acpi_video_bus_cap cap;\n\tstruct acpi_video_bus_flags flags;\n\tstruct list_head video_device_list;\n\tstruct mutex device_list_lock;\n\tstruct list_head entry;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tstruct notifier_block pm_nb;\n};\n\nstruct acpi_video_device_flags {\n\tu8 crt: 1;\n\tu8 lcd: 1;\n\tu8 tvout: 1;\n\tu8 dvi: 1;\n\tu8 bios: 1;\n\tu8 unknown: 1;\n\tu8 notify: 1;\n\tu8 reserved: 1;\n};\n\nstruct acpi_video_device_cap {\n\tu8 _ADR: 1;\n\tu8 _BCL: 1;\n\tu8 _BCM: 1;\n\tu8 _BQC: 1;\n\tu8 _BCQ: 1;\n\tu8 _DDC: 1;\n};\n\nstruct acpi_video_device_brightness;\n\nstruct backlight_device;\n\nstruct acpi_video_device {\n\tlong unsigned int device_id;\n\tstruct acpi_video_device_flags flags;\n\tstruct acpi_video_device_cap cap;\n\tstruct list_head entry;\n\tstruct delayed_work switch_brightness_work;\n\tint switch_brightness_event;\n\tstruct acpi_video_bus *video;\n\tstruct acpi_device *dev;\n\tstruct acpi_video_device_brightness *brightness;\n\tstruct backlight_device *backlight;\n\tstruct thermal_cooling_device *cooling_dev;\n};\n\nstruct acpi_video_device_attrib {\n\tu32 display_index: 4;\n\tu32 display_port_attachment: 4;\n\tu32 display_type: 4;\n\tu32 vendor_specific: 4;\n\tu32 bios_can_detect: 1;\n\tu32 depend_on_vga: 1;\n\tu32 pipe_id: 3;\n\tu32 reserved: 10;\n\tu32 device_id_scheme: 1;\n};\n\nstruct acpi_video_device_brightness {\n\tint curr;\n\tint count;\n\tint *levels;\n\tstruct acpi_video_brightness_flags flags;\n};\n\nstruct acpi_video_enumerated_device {\n\tunion {\n\t\tu32 int_val;\n\t\tstruct acpi_video_device_attrib attrib;\n\t} value;\n\tstruct acpi_video_device *bind_info;\n};\n\nstruct acpi_viot_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_viot_mmio {\n\tstruct acpi_viot_header header;\n\tu32 endpoint;\n\tu64 base_address;\n\tu16 output_node;\n\tu8 reserved[6];\n};\n\nstruct acpi_viot_pci_range {\n\tstruct acpi_viot_header header;\n\tu32 endpoint_start;\n\tu16 segment_start;\n\tu16 segment_end;\n\tu16 bdf_start;\n\tu16 bdf_end;\n\tu16 output_node;\n\tu8 reserved[6];\n};\n\nstruct acpi_viot_virtio_iommu_mmio {\n\tstruct acpi_viot_header header;\n\tu8 reserved[4];\n\tu64 base_address;\n};\n\nstruct acpi_viot_virtio_iommu_pci {\n\tstruct acpi_viot_header header;\n\tu16 segment;\n\tu16 bdf;\n\tu8 reserved[8];\n};\n\nstruct acpi_wakeup_handler {\n\tstruct list_head list_node;\n\tbool (*wakeup)(void *);\n\tvoid *context;\n};\n\nstruct acpi_walk_info {\n\tu32 debug_level;\n\tu32 count;\n\tacpi_owner_id owner_id;\n\tu8 display_type;\n};\n\ntypedef acpi_status (*acpi_parse_downwards)(struct acpi_walk_state *, union acpi_parse_object **);\n\ntypedef acpi_status (*acpi_parse_upwards)(struct acpi_walk_state *);\n\nstruct acpi_walk_state {\n\tstruct acpi_walk_state *next;\n\tu8 descriptor_type;\n\tu8 walk_type;\n\tu16 opcode;\n\tu8 next_op_info;\n\tu8 num_operands;\n\tu8 operand_index;\n\tacpi_owner_id owner_id;\n\tu8 last_predicate;\n\tu8 current_result;\n\tu8 return_used;\n\tu8 scope_depth;\n\tu8 pass_number;\n\tu8 namespace_override;\n\tu8 result_size;\n\tu8 result_count;\n\tu8 *aml;\n\tu32 arg_types;\n\tu32 method_breakpoint;\n\tu32 user_breakpoint;\n\tu32 parse_flags;\n\tstruct acpi_parse_state parser_state;\n\tu32 prev_arg_types;\n\tu32 arg_count;\n\tu16 method_nesting_depth;\n\tu8 method_is_nested;\n\tstruct acpi_namespace_node arguments[7];\n\tstruct acpi_namespace_node local_variables[8];\n\tunion acpi_operand_object *operands[9];\n\tunion acpi_operand_object **params;\n\tu8 *aml_last_while;\n\tunion acpi_operand_object **caller_return_desc;\n\tunion acpi_generic_state *control_state;\n\tstruct acpi_namespace_node *deferred_node;\n\tunion acpi_operand_object *implicit_return_obj;\n\tstruct acpi_namespace_node *method_call_node;\n\tunion acpi_parse_object *method_call_op;\n\tunion acpi_operand_object *method_desc;\n\tstruct acpi_namespace_node *method_node;\n\tchar *method_pathname;\n\tunion acpi_parse_object *op;\n\tconst struct acpi_opcode_info *op_info;\n\tunion acpi_parse_object *origin;\n\tunion acpi_operand_object *result_obj;\n\tunion acpi_generic_state *results;\n\tunion acpi_operand_object *return_desc;\n\tunion acpi_generic_state *scope_info;\n\tunion acpi_parse_object *prev_op;\n\tunion acpi_parse_object *next_op;\n\tstruct acpi_thread_state *thread;\n\tacpi_parse_downwards descending_callback;\n\tacpi_parse_upwards ascending_callback;\n};\n\nstruct acpihid_map_entry {\n\tstruct list_head list;\n\tu8 uid[256];\n\tu8 hid[9];\n\tu32 devid;\n\tu32 root_devid;\n\tbool cmd_line;\n\tstruct iommu_group *group;\n};\n\nstruct pnp_dev;\n\nstruct acpipnp_parse_option_s {\n\tstruct pnp_dev *dev;\n\tunsigned int option_flags;\n};\n\nstruct action_cache {\n\tlong unsigned int allow_native[8];\n\tlong unsigned int allow_compat[8];\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct action_gate_entry {\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n};\n\nstruct action_ops {\n\tint (*pre_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tint (*do_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*undo_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*post_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n};\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct i915_active_fence {\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct i915_active;\n\nstruct active_node {\n\tstruct rb_node node;\n\tstruct i915_active_fence base;\n\tstruct i915_active *ref;\n\tu64 timeline;\n};\n\nstruct addr_marker {\n\tlong unsigned int start_address;\n\tconst char *name;\n\tlong unsigned int max_lines;\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct audit_ntp_data {};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n};\n\nstruct adjust_trip_data {\n\tstruct acpi_thermal *tz;\n\tu32 event;\n};\n\nstruct crypto_aead;\n\nstruct aead_request;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tstruct crypto_alg base;\n};\n\nstruct aead_geniv_ctx {\n\tspinlock_t lock;\n\tstruct crypto_aead *child;\n\tu8 salt[0];\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tvoid *__ctx[0];\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tvoid *__ctx[0];\n};\n\nunion aes_enckey_arch {\n\tu32 rndkeys[60];\n};\n\nstruct aes_enckey {\n\tu32 len;\n\tu32 nrounds;\n\tu32 padding[2];\n\tunion aes_enckey_arch k;\n};\n\nunion aes_invkey_arch {\n\tu32 inv_rndkeys[60];\n};\n\nstruct aes_key {\n\tstruct aes_enckey;\n\tunion aes_invkey_arch inv_k;\n};\n\nstruct af_vsockmon_hdr {\n\t__le64 src_cid;\n\t__le64 dst_cid;\n\t__le32 src_port;\n\t__le32 dst_port;\n\t__le16 op;\n\t__le16 transport;\n\t__le16 len;\n\t__u8 reserved[2];\n};\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct aggressiveness_profile2_entry {\n\tu8 opst_aggressiveness: 4;\n\tu8 elp_aggressiveness: 4;\n};\n\nstruct aggressiveness_profile3_entry {\n\tu8 apd_aggressiveness: 4;\n\tu8 pixoptix_aggressiveness: 4;\n};\n\nstruct aggressiveness_profile4_entry {\n\tu8 xpst_aggressiveness: 4;\n\tu8 tcon_aggressiveness: 4;\n};\n\nstruct aggressiveness_profile_entry {\n\tu8 dpst_aggressiveness: 4;\n\tu8 lace_aggressiveness: 4;\n};\n\nstruct agp_3_5_dev {\n\tstruct list_head list;\n\tu8 capndx;\n\tu32 maxbw;\n\tstruct pci_dev *dev;\n};\n\nstruct agp_version;\n\nstruct agp_bridge_driver;\n\nstruct vm_operations_struct;\n\nstruct agp_bridge_data {\n\tconst struct agp_version *version;\n\tconst struct agp_bridge_driver *driver;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *previous_size;\n\tvoid *current_size;\n\tvoid *dev_private_data;\n\tstruct pci_dev *dev;\n\tu32 *gatt_table;\n\tu32 *gatt_table_real;\n\tlong unsigned int scratch_page;\n\tstruct page *scratch_page_page;\n\tdma_addr_t scratch_page_dma;\n\tlong unsigned int gart_bus_addr;\n\tlong unsigned int gatt_bus_addr;\n\tu32 mode;\n\tlong unsigned int *key_list;\n\tatomic_t current_memory_agp;\n\tatomic_t agp_in_use;\n\tint max_memory_agp;\n\tint aperture_size_idx;\n\tint capndx;\n\tint flags;\n\tchar major_version;\n\tchar minor_version;\n\tstruct list_head list;\n\tu32 apbase_config;\n\tstruct list_head mapped_list;\n\tspinlock_t mapped_lock;\n};\n\nstruct gatt_mask;\n\nstruct agp_memory;\n\nstruct agp_bridge_driver {\n\tstruct module *owner;\n\tconst void *aperture_sizes;\n\tint num_aperture_sizes;\n\tenum aper_size_type size_type;\n\tbool cant_use_aperture;\n\tbool needs_scratch_page;\n\tconst struct gatt_mask *masks;\n\tint (*fetch_size)(void);\n\tint (*configure)(void);\n\tvoid (*agp_enable)(struct agp_bridge_data *, u32);\n\tvoid (*cleanup)(void);\n\tvoid (*tlb_flush)(struct agp_memory *);\n\tlong unsigned int (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int);\n\tvoid (*cache_flush)(void);\n\tint (*create_gatt_table)(struct agp_bridge_data *);\n\tint (*free_gatt_table)(struct agp_bridge_data *);\n\tint (*insert_memory)(struct agp_memory *, off_t, int);\n\tint (*remove_memory)(struct agp_memory *, off_t, int);\n\tstruct agp_memory * (*alloc_by_type)(size_t, int);\n\tvoid (*free_by_type)(struct agp_memory *);\n\tstruct page * (*agp_alloc_page)(struct agp_bridge_data *);\n\tint (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t);\n\tvoid (*agp_destroy_page)(struct page *, int);\n\tvoid (*agp_destroy_pages)(struct agp_memory *);\n\tint (*agp_type_to_mask_type)(struct agp_bridge_data *, int);\n};\n\nstruct agp_version {\n\tu16 major;\n\tu16 minor;\n};\n\nstruct agp_kern_info {\n\tstruct agp_version version;\n\tstruct pci_dev *device;\n\tenum chipset_type chipset;\n\tlong unsigned int mode;\n\tlong unsigned int aper_base;\n\tsize_t aper_size;\n\tint max_memory;\n\tint current_memory;\n\tbool cant_use_aperture;\n\tlong unsigned int page_mask;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct agp_memory {\n\tstruct agp_memory *next;\n\tstruct agp_memory *prev;\n\tstruct agp_bridge_data *bridge;\n\tstruct page **pages;\n\tsize_t page_count;\n\tint key;\n\tint num_scratch_pages;\n\toff_t pg_start;\n\tu32 type;\n\tu32 physical;\n\tbool is_bound;\n\tbool is_flushed;\n\tstruct list_head mapped_list;\n\tstruct scatterlist *sg_list;\n\tint num_sg;\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request;\n\nstruct crypto_ahash;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*export_core)(struct ahash_request *, void *);\n\tint (*import_core)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_ahash *);\n\tvoid (*exit_tfm)(struct crypto_ahash *);\n\tint (*clone_tfm)(struct crypto_ahash *, struct crypto_ahash *);\n\tstruct hash_alg_common halg;\n};\n\nstruct ahash_hmac_ctx {\n\tstruct crypto_ahash *hash;\n\tu8 pads[0];\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[112];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tu8 *result;\n\tstruct scatterlist sg_head[2];\n\tcrypto_completion_t saved_complete;\n\tvoid *saved_data;\n\tvoid *__ctx[0];\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct ata_link;\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct reset_control;\n\nstruct regulator;\n\nstruct clk_bulk_data;\n\nstruct phy___2;\n\nstruct ata_port;\n\nstruct ata_host;\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 mask_port_map;\n\tu32 mask_port_ext;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 saved_port_cap[32];\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tunsigned int n_clks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int f_rsts;\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy___2 **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[15];\n\tchar *irq_desc;\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct akcipher_request;\n\nstruct crypto_akcipher;\n\nstruct akcipher_alg {\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[56];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct alc298_lg_gram_style_seq;\n\nstruct alc298_lg_gram_style_amp_desc {\n\tunsigned char nid;\n\tconst struct alc298_lg_gram_style_seq *init_seq;\n\tint init_seq_size;\n};\n\nstruct alc298_lg_gram_style_seq {\n\tshort unsigned int verb;\n\tshort unsigned int idx;\n\tshort unsigned int val;\n};\n\nstruct alc298_samsung_amp_desc {\n\tunsigned char nid;\n\tshort unsigned int init_seq[4];\n};\n\nstruct alc298_samsung_v2_amp_desc {\n\tshort unsigned int nid;\n\tint init_seq_size;\n\tshort unsigned int init_seq[36];\n};\n\nstruct alc_codec_rename_pci_table {\n\tunsigned int codec_vendor_id;\n\tshort unsigned int pci_subvendor;\n\tshort unsigned int pci_subdevice;\n\tconst char *name;\n};\n\nstruct alc_codec_rename_table {\n\tunsigned int vendor_id;\n\tshort unsigned int coef_mask;\n\tshort unsigned int coef_bits;\n\tconst char *name;\n};\n\nstruct alc_coef_led {\n\tunsigned int idx;\n\tunsigned int mask;\n\tunsigned int on;\n\tunsigned int off;\n};\n\nstruct alc_customize_define {\n\tunsigned int sku_cfg;\n\tunsigned char port_connectivity;\n\tunsigned char check_sum;\n\tunsigned char customization;\n\tunsigned char external_amp;\n\tunsigned int enable_pcbeep: 1;\n\tunsigned int platform_type: 1;\n\tunsigned int swap: 1;\n\tunsigned int override: 1;\n\tunsigned int fixup: 1;\n};\n\nstruct hda_multi_out {\n\tint num_dacs;\n\tconst hda_nid_t *dac_nids;\n\thda_nid_t hp_nid;\n\thda_nid_t hp_out_nid[5];\n\thda_nid_t extra_out_nid[5];\n\thda_nid_t dig_out_nid;\n\tconst hda_nid_t *follower_dig_outs;\n\tint max_channels;\n\tint dig_out_used;\n\tint no_share_stream;\n\tint share_spdif;\n\tunsigned int analog_rates;\n\tunsigned int analog_maxbps;\n\tu64 analog_formats;\n\tunsigned int spdif_rates;\n\tunsigned int spdif_maxbps;\n\tu64 spdif_formats;\n};\n\nstruct hda_input_mux_item {\n\tchar label[32];\n\tunsigned int index;\n};\n\nstruct hda_input_mux {\n\tunsigned int num_items;\n\tstruct hda_input_mux_item items[36];\n};\n\nstruct auto_pin_cfg_item {\n\thda_nid_t pin;\n\tint type;\n\tunsigned int is_headset_mic: 1;\n\tunsigned int is_headphone_mic: 1;\n\tunsigned int has_boost_on_pin: 1;\n\tint order;\n};\n\nstruct auto_pin_cfg {\n\tint line_outs;\n\thda_nid_t line_out_pins[5];\n\tint speaker_outs;\n\thda_nid_t speaker_pins[5];\n\tint hp_outs;\n\tint line_out_type;\n\thda_nid_t hp_pins[5];\n\tint num_inputs;\n\tstruct auto_pin_cfg_item inputs[18];\n\tint dig_outs;\n\thda_nid_t dig_out_pins[2];\n\thda_nid_t dig_in_pin;\n\thda_nid_t mono_out_pin;\n\tint dig_out_type[2];\n\tint dig_in_type;\n};\n\nstruct snd_array {\n\tunsigned int used;\n\tunsigned int alloced;\n\tunsigned int elem_size;\n\tunsigned int alloc_align;\n\tvoid *list;\n};\n\nstruct automic_entry {\n\thda_nid_t pin;\n\tint idx;\n\tunsigned int attr;\n};\n\nstruct snd_kcontrol;\n\nstruct hda_vmaster_mute_hook {\n\tstruct snd_kcontrol *sw_kctl;\n\tvoid (*hook)(void *, int);\n\tstruct hda_codec *codec;\n};\n\nstruct hda_amp_list;\n\nstruct hda_loopback_check {\n\tconst struct hda_amp_list *amplist;\n\tint power_on;\n};\n\nstruct hda_multi_io {\n\thda_nid_t pin;\n\thda_nid_t dac;\n\tunsigned int ctl_in;\n};\n\nstruct hda_pcm_stream;\n\nstruct hda_pcm;\n\nstruct badness_table;\n\nstruct snd_ctl_elem_value;\n\nstruct hda_jack_callback;\n\nstruct led_classdev;\n\nstruct hda_gen_spec {\n\tchar stream_name_analog[32];\n\tconst struct hda_pcm_stream *stream_analog_playback;\n\tconst struct hda_pcm_stream *stream_analog_capture;\n\tchar stream_name_alt_analog[32];\n\tconst struct hda_pcm_stream *stream_analog_alt_playback;\n\tconst struct hda_pcm_stream *stream_analog_alt_capture;\n\tchar stream_name_digital[32];\n\tconst struct hda_pcm_stream *stream_digital_playback;\n\tconst struct hda_pcm_stream *stream_digital_capture;\n\tunsigned int active_streams;\n\tstruct mutex pcm_mutex;\n\tstruct hda_multi_out multiout;\n\thda_nid_t alt_dac_nid;\n\thda_nid_t follower_dig_outs[3];\n\tint dig_out_type;\n\tunsigned int num_adc_nids;\n\thda_nid_t adc_nids[18];\n\thda_nid_t dig_in_nid;\n\thda_nid_t mixer_nid;\n\thda_nid_t mixer_merge_nid;\n\tconst char *input_labels[36];\n\tint input_label_idxs[36];\n\thda_nid_t cur_adc;\n\tunsigned int cur_adc_stream_tag;\n\tunsigned int cur_adc_format;\n\tstruct hda_input_mux input_mux;\n\tunsigned int cur_mux[3];\n\tint min_channel_count;\n\tint ext_channel_count;\n\tint const_channel_count;\n\tstruct hda_pcm *pcm_rec[3];\n\tstruct auto_pin_cfg autocfg;\n\tstruct snd_array kctls;\n\thda_nid_t private_dac_nids[5];\n\thda_nid_t imux_pins[36];\n\tunsigned int dyn_adc_idx[36];\n\thda_nid_t shared_mic_vref_pin;\n\thda_nid_t hp_mic_pin;\n\tint hp_mic_mux_idx;\n\tint num_all_dacs;\n\thda_nid_t all_dacs[16];\n\tint num_all_adcs;\n\thda_nid_t all_adcs[18];\n\tstruct snd_array paths;\n\tint out_paths[5];\n\tint hp_paths[5];\n\tint speaker_paths[5];\n\tint aamix_out_paths[3];\n\tint digout_paths[5];\n\tint input_paths[648];\n\tint loopback_paths[36];\n\tint loopback_merge_path;\n\tint digin_path;\n\tint am_num_entries;\n\tstruct automic_entry am_entry[3];\n\tunsigned int hp_jack_present: 1;\n\tunsigned int line_jack_present: 1;\n\tunsigned int speaker_muted: 1;\n\tunsigned int line_out_muted: 1;\n\tunsigned int auto_mic: 1;\n\tunsigned int automute_speaker: 1;\n\tunsigned int automute_lo: 1;\n\tunsigned int detect_hp: 1;\n\tunsigned int detect_lo: 1;\n\tunsigned int automute_speaker_possible: 1;\n\tunsigned int automute_lo_possible: 1;\n\tunsigned int master_mute: 1;\n\tunsigned int keep_vref_in_automute: 1;\n\tunsigned int line_in_auto_switch: 1;\n\tunsigned int auto_mute_via_amp: 1;\n\tunsigned int suppress_auto_mute: 1;\n\tunsigned int suppress_auto_mic: 1;\n\tunsigned int need_dac_fix: 1;\n\tunsigned int hp_mic: 1;\n\tunsigned int suppress_hp_mic_detect: 1;\n\tunsigned int no_primary_hp: 1;\n\tunsigned int no_multi_io: 1;\n\tunsigned int multi_cap_vol: 1;\n\tunsigned int inv_dmic_split: 1;\n\tunsigned int own_eapd_ctl: 1;\n\tunsigned int keep_eapd_on: 1;\n\tunsigned int vmaster_mute_led: 1;\n\tunsigned int mic_mute_led: 1;\n\tunsigned int indep_hp: 1;\n\tunsigned int prefer_hp_amp: 1;\n\tunsigned int add_stereo_mix_input: 2;\n\tunsigned int add_jack_modes: 1;\n\tunsigned int power_down_unused: 1;\n\tunsigned int dac_min_mute: 1;\n\tunsigned int suppress_vmaster: 1;\n\tunsigned int no_analog: 1;\n\tunsigned int dyn_adc_switch: 1;\n\tunsigned int indep_hp_enabled: 1;\n\tunsigned int have_aamix_ctl: 1;\n\tunsigned int hp_mic_jack_modes: 1;\n\tunsigned int skip_verbs: 1;\n\tu64 mute_bits;\n\tu64 out_vol_mask;\n\tconst struct badness_table *main_out_badness;\n\tconst struct badness_table *extra_out_badness;\n\tconst hda_nid_t *preferred_dacs;\n\tbool aamix_mode;\n\thda_nid_t beep_nid;\n\thda_nid_t vmaster_nid;\n\tunsigned int vmaster_tlv[4];\n\tstruct hda_vmaster_mute_hook vmaster_mute;\n\tstruct hda_loopback_check loopback;\n\tstruct snd_array loopback_list;\n\tint multi_ios;\n\tstruct hda_multi_io multi_io[4];\n\tvoid (*init_hook)(struct hda_codec *);\n\tvoid (*automute_hook)(struct hda_codec *);\n\tvoid (*cap_sync_hook)(struct hda_codec *, struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\tvoid (*pcm_playback_hook)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *, int);\n\tvoid (*pcm_capture_hook)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *, int);\n\tvoid (*hp_automute_hook)(struct hda_codec *, struct hda_jack_callback *);\n\tvoid (*line_automute_hook)(struct hda_codec *, struct hda_jack_callback *);\n\tvoid (*mic_autoswitch_hook)(struct hda_codec *, struct hda_jack_callback *);\n\tstruct led_classdev *led_cdevs[2];\n};\n\nstruct hda_component {\n\tstruct device *dev;\n\tchar name[50];\n\tstruct acpi_device *adev;\n\tbool acpi_notifications_supported;\n\tvoid (*acpi_notify)(acpi_handle, u32, struct device *);\n\tvoid (*pre_playback_hook)(struct device *, int);\n\tvoid (*playback_hook)(struct device *, int);\n\tvoid (*post_playback_hook)(struct device *, int);\n};\n\nstruct hda_component_parent {\n\tstruct mutex mutex;\n\tstruct hda_codec *codec;\n\tstruct hda_component comps[4];\n};\n\nstruct alc_spec {\n\tstruct hda_gen_spec gen;\n\tstruct alc_customize_define cdefine;\n\tunsigned int parse_flags;\n\tunsigned int gpio_mask;\n\tunsigned int gpio_dir;\n\tunsigned int gpio_data;\n\tbool gpio_write_delay;\n\tint mute_led_polarity;\n\tint micmute_led_polarity;\n\thda_nid_t mute_led_nid;\n\thda_nid_t cap_mute_led_nid;\n\tunsigned int gpio_mute_led_mask;\n\tunsigned int gpio_mic_led_mask;\n\tstruct alc_coef_led mute_led_coef;\n\tstruct alc_coef_led mic_led_coef;\n\tstruct mutex coef_mutex;\n\thda_nid_t headset_mic_pin;\n\thda_nid_t headphone_mic_pin;\n\tint current_headset_mode;\n\tint current_headset_type;\n\tvoid (*init_hook)(struct hda_codec *);\n\tvoid (*power_hook)(struct hda_codec *);\n\tvoid (*shutup)(struct hda_codec *);\n\tint init_amp;\n\tint codec_variant;\n\tunsigned int has_alc5505_dsp: 1;\n\tunsigned int no_depop_delay: 1;\n\tunsigned int done_hp_init: 1;\n\tunsigned int no_shutup_pins: 1;\n\tunsigned int ultra_low_power: 1;\n\tunsigned int has_hs_key: 1;\n\tunsigned int no_internal_mic_pin: 1;\n\tunsigned int en_3kpull_low: 1;\n\tint num_speaker_amps;\n\thda_nid_t pll_nid;\n\tunsigned int pll_coef_idx;\n\tunsigned int pll_coef_bit;\n\tunsigned int coef0;\n\tstruct input_dev *kb_dev;\n\tu8 alc_mute_keycode_map[1];\n\tstruct hda_component_parent comps;\n};\n\nstruct alert_data {\n\tshort unsigned int addr;\n\tenum i2c_alert_protocol type;\n\tunsigned int data;\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct psmouse;\n\nstruct alps_nibble_commands;\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct als_data_entry {\n\tu16 backlight_adjust;\n\tu16 lux;\n};\n\nstruct alt_instr {\n\ts32 instr_offset;\n\ts32 repl_offset;\n\tunion {\n\t\tstruct {\n\t\t\tu32 cpuid: 16;\n\t\t\tu32 flags: 16;\n\t\t};\n\t\tu32 ft_flags;\n\t};\n\tu8 instrlen;\n\tu8 replacementlen;\n} __attribute__((packed));\n\nstruct amd_aperf_mperf {\n\tu64 aperf;\n\tu64 mperf;\n\tu64 tsc;\n};\n\nstruct amd_chipset_type {\n\tenum amd_chipset_gen gen;\n\tu8 rev;\n};\n\nstruct amd_chipset_info {\n\tstruct pci_dev *nb_dev;\n\tstruct pci_dev *smbus_dev;\n\tint nb_type;\n\tstruct amd_chipset_type sb_type;\n\tint isoc_reqs;\n\tint probe_count;\n\tbool need_pll_quirk;\n};\n\nunion perf_cached {\n\tstruct {\n\t\tu8 highest_perf;\n\t\tu8 nominal_perf;\n\t\tu8 lowest_nonlinear_perf;\n\t\tu8 lowest_perf;\n\t\tu8 min_limit_perf;\n\t\tu8 max_limit_perf;\n\t\tu8 bios_min_perf;\n\t};\n\tu64 val;\n};\n\nstruct amd_cpudata {\n\tint cpu;\n\tstruct freq_qos_request req[2];\n\tu64 cppc_req_cached;\n\tunion perf_cached perf;\n\tu8 prefcore_ranking;\n\tu32 min_limit_freq;\n\tu32 max_limit_freq;\n\tu32 nominal_freq;\n\tu32 lowest_nonlinear_freq;\n\tstruct amd_aperf_mperf cur;\n\tstruct amd_aperf_mperf prev;\n\tu64 freq;\n\tbool boost_supported;\n\tbool hw_prefcore;\n\tu32 policy;\n\tbool suspended;\n\tu8 epp_default;\n};\n\nstruct amd_hostbridge {\n\tu32 bus;\n\tu32 slot;\n\tu32 device;\n};\n\nstruct iommu_ops;\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n\tstruct iommu_group *singleton_group;\n\tu32 max_pasids;\n\tbool ready;\n};\n\nstruct amd_iommu_pci_seg;\n\nstruct iopf_queue;\n\nstruct amd_iommu {\n\tstruct list_head list;\n\tint index;\n\traw_spinlock_t lock;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *root_pdev;\n\tu64 mmio_phys;\n\tu64 mmio_phys_end;\n\tu8 *mmio_base;\n\tu32 cap;\n\tu8 acpi_flags;\n\tu64 features;\n\tu64 features2;\n\tu16 devid;\n\tu16 cap_ptr;\n\tstruct amd_iommu_pci_seg *pci_seg;\n\tu64 exclusion_start;\n\tu64 exclusion_length;\n\tu8 *cmd_buf;\n\tu32 cmd_buf_head;\n\tu32 cmd_buf_tail;\n\tu8 *evt_buf;\n\tunsigned char evt_irq_name[16];\n\tu8 *ppr_log;\n\tunsigned char ppr_irq_name[16];\n\tu8 *ga_log;\n\tunsigned char ga_irq_name[16];\n\tu8 *ga_log_tail;\n\tbool int_enabled;\n\tbool need_sync;\n\tbool irtcachedis_enabled;\n\tstruct iommu_device iommu;\n\tu32 stored_addr_lo;\n\tu32 stored_addr_hi;\n\tu32 stored_l1[108];\n\tu32 stored_l2[131];\n\tu8 max_banks;\n\tu8 max_counters;\n\tu32 flags;\n\tvolatile u64 *cmd_sem;\n\tu64 cmd_sem_val;\n\tu64 cmd_sem_paddr;\n\tstruct iopf_queue *iopf_queue;\n\tunsigned char iopfq_name[32];\n};\n\nstruct amd_iommu_event_desc {\n\tstruct device_attribute attr;\n\tconst char *event;\n};\n\nstruct dev_table_entry;\n\nstruct irq_remap_table;\n\nstruct amd_iommu_pci_seg {\n\tstruct list_head list;\n\tstruct llist_head dev_data_list;\n\tu16 id;\n\tu16 last_bdf;\n\tu32 dev_table_size;\n\tstruct dev_table_entry *dev_table;\n\tstruct amd_iommu **rlookup_table;\n\tstruct irq_remap_table **irq_lookup_table;\n\tstruct dev_table_entry *old_dev_tbl_cpy;\n\tu16 *alias_table;\n\tstruct list_head unity_map;\n};\n\nstruct amd_iommu_pi_data {\n\tu64 vapic_addr;\n\tu32 ga_tag;\n\tu32 vector;\n\tint cpu;\n\tbool ga_log_intr;\n\tbool is_guest_mode;\n\tvoid *ir_data;\n};\n\nstruct iommufd_object {\n\trefcount_t wait_cnt;\n\trefcount_t users;\n\tenum iommufd_object_type type;\n\tunsigned int id;\n};\n\nstruct iommufd_ctx;\n\nstruct iommufd_hwpt_paging;\n\nstruct iommufd_viommu_ops;\n\nstruct iommufd_viommu {\n\tstruct iommufd_object obj;\n\tstruct iommufd_ctx *ictx;\n\tstruct iommu_device *iommu_dev;\n\tstruct iommufd_hwpt_paging *hwpt;\n\tconst struct iommufd_viommu_ops *ops;\n\tstruct xarray vdevs;\n\tstruct list_head veventqs;\n\tstruct rw_semaphore veventqs_rwsem;\n\tenum iommu_viommu_type type;\n};\n\nstruct protection_domain;\n\nstruct amd_iommu_viommu {\n\tstruct iommufd_viommu core;\n\tstruct protection_domain *parent;\n\tstruct list_head pdom_list;\n\tstruct xarray gdomid_array;\n};\n\nstruct amd_l3_cache {\n\tunsigned int indices;\n\tu8 subcaches[4];\n};\n\nstruct amd_lps0_hid_device_data {\n\tconst bool check_off_by_one;\n};\n\nstruct event_constraint {\n\tunion {\n\t\tlong unsigned int idxmsk[1];\n\t\tu64 idxmsk64;\n\t};\n\tu64 code;\n\tu64 cmask;\n\tint weight;\n\tint overlap;\n\tint flags;\n\tunsigned int size;\n};\n\nstruct perf_event;\n\nstruct amd_nb {\n\tint nb_id;\n\tint refcnt;\n\tstruct perf_event *owners[64];\n\tstruct event_constraint event_constraints[64];\n};\n\nstruct amd_nb_bus_dev_range {\n\tu8 bus;\n\tu8 dev_base;\n\tu8 dev_limit;\n};\n\nstruct amd_northbridge {\n\tstruct pci_dev *misc;\n\tstruct pci_dev *link;\n\tstruct amd_l3_cache l3_cache;\n};\n\nstruct amd_northbridge_info {\n\tu16 num;\n\tu64 flags;\n\tstruct amd_northbridge *nb;\n};\n\nunion amd_uncore_info;\n\nstruct amd_uncore_pmu;\n\nstruct amd_uncore {\n\tunion amd_uncore_info *info;\n\tstruct amd_uncore_pmu *pmus;\n\tunsigned int num_pmus;\n\tbool init_done;\n\tvoid (*scan)(struct amd_uncore *, unsigned int);\n\tint (*init)(struct amd_uncore *, unsigned int);\n\tvoid (*move)(struct amd_uncore *, unsigned int);\n\tvoid (*free)(struct amd_uncore *, unsigned int);\n};\n\nstruct amd_uncore_ctx {\n\tint refcnt;\n\tint cpu;\n\tstruct perf_event **events;\n\tlong unsigned int active_mask[1];\n\tint nr_active;\n\tstruct hrtimer hrtimer;\n\tu64 hrtimer_duration;\n};\n\nunion amd_uncore_info {\n\tstruct {\n\t\tu64 aux_data: 32;\n\t\tu64 num_pmcs: 8;\n\t\tu64 gid: 8;\n\t\tu64 cid: 8;\n\t} split;\n\tu64 full;\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct perf_cpu_pmu_context;\n\nstruct mm_struct;\n\nstruct perf_event_pmu_context;\n\nstruct kmem_cache;\n\nstruct perf_output_handle;\n\nstruct pmu {\n\tstruct list_head entry;\n\tspinlock_t events_lock;\n\tstruct list_head events;\n\tstruct module *module;\n\tstruct device *dev;\n\tstruct device *parent;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tunsigned int scope;\n\tstruct perf_cpu_pmu_context **cpu_pmu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tstruct kmem_cache *task_ctx_cache;\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tbool (*filter)(struct pmu *, int);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\nstruct amd_uncore_pmu {\n\tchar name[16];\n\tint num_counters;\n\tint rdpmc_base;\n\tu32 msr_base;\n\tint group;\n\tcpumask_t active_mask;\n\tstruct pmu pmu;\n\tstruct amd_uncore_ctx **ctx;\n};\n\nstruct amdv1pt_write_attrs {\n\tu64 descriptor_bits;\n\tgfp_t gfp;\n};\n\nstruct aml_resource_small_header {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_large_header {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_irq {\n\tu8 descriptor_type;\n\tu16 irq_mask;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct aml_resource_dma {\n\tu8 descriptor_type;\n\tu8 dma_channel_mask;\n\tu8 flags;\n};\n\nstruct aml_resource_start_dependent {\n\tu8 descriptor_type;\n\tu8 flags;\n};\n\nstruct aml_resource_end_dependent {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_io {\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu8 alignment;\n\tu8 address_length;\n};\n\nstruct aml_resource_fixed_io {\n\tu8 descriptor_type;\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_dma {\n\tu8 descriptor_type;\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_small {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_end_tag {\n\tu8 descriptor_type;\n\tu8 checksum;\n};\n\nstruct aml_resource_memory24 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_generic_register {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 address_space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_large {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address16 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_extended_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu8 revision_ID;\n\tu8 reserved;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct aml_resource_extended_irq {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu8 interrupt_count;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct aml_resource_gpio {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 connection_type;\n\tu16 flags;\n\tu16 int_flags;\n\tu8 pin_config;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_i2c_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu16 slave_address;\n} __attribute__((packed));\n\nstruct aml_resource_spi_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n} __attribute__((packed));\n\nstruct aml_resource_uart_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 default_baud_rate;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu8 parity;\n\tu8 lines_enabled;\n} __attribute__((packed));\n\nstruct aml_resource_csi2_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_common_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config;\n\tu16 function_number;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 pin_table_offset;\n\tu16 label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 function_number;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_clock_input {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n} __attribute__((packed));\n\nstruct aml_resource_address {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n} __attribute__((packed));\n\nunion aml_resource {\n\tu8 descriptor_type;\n\tstruct aml_resource_small_header small_header;\n\tstruct aml_resource_large_header large_header;\n\tstruct aml_resource_irq irq;\n\tstruct aml_resource_dma dma;\n\tstruct aml_resource_start_dependent start_dpf;\n\tstruct aml_resource_end_dependent end_dpf;\n\tstruct aml_resource_io io;\n\tstruct aml_resource_fixed_io fixed_io;\n\tstruct aml_resource_fixed_dma fixed_dma;\n\tstruct aml_resource_vendor_small vendor_small;\n\tstruct aml_resource_end_tag end_tag;\n\tstruct aml_resource_memory24 memory24;\n\tstruct aml_resource_generic_register generic_reg;\n\tstruct aml_resource_vendor_large vendor_large;\n\tstruct aml_resource_memory32 memory32;\n\tstruct aml_resource_fixed_memory32 fixed_memory32;\n\tstruct aml_resource_address16 address16;\n\tstruct aml_resource_address32 address32;\n\tstruct aml_resource_address64 address64;\n\tstruct aml_resource_extended_address64 ext_address64;\n\tstruct aml_resource_extended_irq extended_irq;\n\tstruct aml_resource_gpio gpio;\n\tstruct aml_resource_i2c_serialbus i2c_serial_bus;\n\tstruct aml_resource_spi_serialbus spi_serial_bus;\n\tstruct aml_resource_uart_serialbus uart_serial_bus;\n\tstruct aml_resource_csi2_serialbus csi2_serial_bus;\n\tstruct aml_resource_common_serialbus common_serial_bus;\n\tstruct aml_resource_pin_function pin_function;\n\tstruct aml_resource_pin_config pin_config;\n\tstruct aml_resource_pin_group pin_group;\n\tstruct aml_resource_pin_group_function pin_group_function;\n\tstruct aml_resource_pin_group_config pin_group_config;\n\tstruct aml_resource_clock_input clock_input;\n\tstruct aml_resource_address address;\n\tu32 dword_item;\n\tu16 word_item;\n\tu8 byte_item;\n};\n\nstruct analog_param_field {\n\tunsigned int even;\n\tunsigned int odd;\n};\n\nstruct analog_param_range {\n\tunsigned int min;\n\tunsigned int typ;\n\tunsigned int max;\n};\n\nstruct analog_parameters {\n\tunsigned int num_lines;\n\tunsigned int line_duration_ns;\n\tstruct analog_param_range hact_ns;\n\tstruct analog_param_range hfp_ns;\n\tstruct analog_param_range hslen_ns;\n\tstruct analog_param_range hbp_ns;\n\tstruct analog_param_range hblk_ns;\n\tunsigned int bt601_hfp;\n\tstruct analog_param_field vfp_lines;\n\tstruct analog_param_field vslen_lines;\n\tstruct analog_param_field vbp_lines;\n};\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct apd_private_data;\n\nstruct apd_device_desc {\n\tunsigned int fixed_clk_rate;\n\tstruct property_entry *properties;\n\tint (*setup)(struct apd_private_data *);\n};\n\nstruct clk;\n\nstruct apd_private_data {\n\tstruct clk *clk;\n\tstruct acpi_device *adev;\n\tconst struct apd_device_desc *dev_desc;\n};\n\nstruct aper_size_info_16 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu16 size_value;\n};\n\nstruct aper_size_info_32 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu32 size_value;\n};\n\nstruct aper_size_info_8 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu8 size_value;\n};\n\nstruct aper_size_info_fixed {\n\tint size;\n\tint num_entries;\n\tint page_order;\n};\n\nstruct aper_size_info_lvl2 {\n\tint size;\n\tint num_entries;\n\tu32 size_value;\n};\n\nstruct aperfmperf {\n\tseqcount_t seq;\n\tlong unsigned int last_update;\n\tu64 acnt;\n\tu64 mcnt;\n\tu64 aperf;\n\tu64 mperf;\n};\n\nstruct aperture_range {\n\tstruct device *dev;\n\tresource_size_t base;\n\tresource_size_t size;\n\tstruct list_head lh;\n\tvoid (*detach)(struct device *);\n};\n\nstruct apic {\n\tvoid (*eoi)(void);\n\tvoid (*native_eoi)(void);\n\tvoid (*write)(u32, u32);\n\tu32 (*read)(u32);\n\tvoid (*wait_icr_idle)(void);\n\tu32 (*safe_wait_icr_idle)(void);\n\tvoid (*send_IPI)(int, int);\n\tvoid (*send_IPI_mask)(const struct cpumask *, int);\n\tvoid (*send_IPI_mask_allbutself)(const struct cpumask *, int);\n\tvoid (*send_IPI_allbutself)(int);\n\tvoid (*send_IPI_all)(int);\n\tvoid (*send_IPI_self)(int);\n\tu32 disable_esr: 1;\n\tu32 dest_mode_logical: 1;\n\tu32 x2apic_set_max_apicid: 1;\n\tu32 nmi_to_offline_cpu: 1;\n\tu32 (*calc_dest_apicid)(unsigned int);\n\tu64 (*icr_read)(void);\n\tvoid (*icr_write)(u32, u32);\n\tu32 max_apic_id;\n\tint (*probe)(void);\n\tvoid (*setup)(void);\n\tvoid (*teardown)(void);\n\tint (*acpi_madt_oem_check)(char *, char *);\n\tvoid (*init_apic_ldr)(void);\n\tu32 (*cpu_present_to_apicid)(int);\n\tu32 (*get_apic_id)(u32);\n\tint (*wakeup_secondary_cpu)(u32, long unsigned int, unsigned int);\n\tint (*wakeup_secondary_cpu_64)(u32, long unsigned int, unsigned int);\n\tvoid (*update_vector)(unsigned int, unsigned int, bool);\n\tchar *name;\n};\n\nstruct irq_cfg {\n\tunsigned int dest_apicid;\n\tunsigned int vector;\n};\n\nstruct apic_chip_data {\n\tstruct irq_cfg hw_irq_cfg;\n\tunsigned int vector;\n\tunsigned int prev_vector;\n\tunsigned int cpu;\n\tunsigned int prev_cpu;\n\tunsigned int irq;\n\tstruct hlist_node clist;\n\tunsigned int move_in_progress: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int can_reserve: 1;\n\tunsigned int has_reserved: 1;\n};\n\nunion apic_ir {\n\tlong unsigned int map[4];\n\tu32 regs[8];\n};\n\nstruct apic_override {\n\tvoid (*eoi)(void);\n\tvoid (*native_eoi)(void);\n\tvoid (*write)(u32, u32);\n\tu32 (*read)(u32);\n\tvoid (*send_IPI)(int, int);\n\tvoid (*send_IPI_mask)(const struct cpumask *, int);\n\tvoid (*send_IPI_mask_allbutself)(const struct cpumask *, int);\n\tvoid (*send_IPI_allbutself)(int);\n\tvoid (*send_IPI_all)(int);\n\tvoid (*send_IPI_self)(int);\n\tu64 (*icr_read)(void);\n\tvoid (*icr_write)(u32, u32);\n\tint (*wakeup_secondary_cpu)(u32, long unsigned int, unsigned int);\n\tint (*wakeup_secondary_cpu_64)(u32, long unsigned int, unsigned int);\n};\n\nstruct apm_bios_info {\n\t__u16 version;\n\t__u16 cseg;\n\t__u32 offset;\n\t__u16 cseg_16;\n\t__u16 dseg;\n\t__u16 flags;\n\t__u16 cseg_len;\n\t__u16 cseg_16_len;\n\t__u16 dseg_len;\n};\n\nstruct apply_range_data {\n\tstruct page **pages;\n\tint i;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct arch_elf_state {};\n\nstruct arch_hw_breakpoint {\n\tlong unsigned int address;\n\tlong unsigned int mask;\n\tu8 len;\n\tu8 type;\n};\n\nstruct arch_hybrid_cpu_scale {\n\tlong unsigned int capacity;\n\tlong unsigned int freq_ratio;\n};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct lbr_entry {\n\tu64 from;\n\tu64 to;\n\tu64 info;\n};\n\nstruct arch_lbr_state {\n\tu64 lbr_ctl;\n\tu64 lbr_depth;\n\tu64 ler_from;\n\tu64 ler_to;\n\tu64 ler_info;\n\tstruct lbr_entry entries[0];\n};\n\nstruct arch_optimized_insn {\n\tkprobe_opcode_t copied_insn[4];\n\tkprobe_opcode_t *insn;\n\tsize_t size;\n};\n\nstruct arch_pebs_aux {\n\tu64 address;\n\tu64 rsvd;\n\tu64 rsvd2;\n\tu64 rsvd3;\n\tu64 rsvd4;\n\tu64 aux;\n\tu64 instr_latency: 16;\n\tu64 pad2: 16;\n\tu64 cache_latency: 16;\n\tu64 pad3: 16;\n\tu64 tsx_tuning;\n};\n\nstruct arch_pebs_basic {\n\tu64 ip;\n\tu64 applicable_counters;\n\tu64 tsc;\n\tu64 retire: 16;\n\tu64 valid: 1;\n\tu64 rsvd: 47;\n\tu64 rsvd2;\n\tu64 rsvd3;\n};\n\nstruct arch_pebs_cap {\n\tu64 caps;\n\tu64 counters;\n\tu64 pdists;\n};\n\nstruct arch_pebs_cntr_header {\n\tu32 cntr;\n\tu32 fixed;\n\tu32 metrics;\n\tu32 reserved;\n};\n\nstruct arch_pebs_gprs {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 cx;\n\tu64 dx;\n\tu64 bx;\n\tu64 sp;\n\tu64 bp;\n\tu64 si;\n\tu64 di;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 ssp;\n\tu64 rsvd;\n};\n\nstruct arch_pebs_header {\n\tunion {\n\t\tu64 format;\n\t\tstruct {\n\t\t\tu64 size: 16;\n\t\t\tu64 rsvd: 14;\n\t\t\tu64 mode: 1;\n\t\t\tu64 cont: 1;\n\t\t\tu64 rsvd2: 3;\n\t\t\tu64 cntr: 5;\n\t\t\tu64 lbr: 2;\n\t\t\tu64 rsvd3: 7;\n\t\t\tu64 xmm: 1;\n\t\t\tu64 ymmh: 1;\n\t\t\tu64 rsvd4: 2;\n\t\t\tu64 opmask: 1;\n\t\t\tu64 zmmh: 1;\n\t\t\tu64 h16zmm: 1;\n\t\t\tu64 rsvd5: 5;\n\t\t\tu64 gpr: 1;\n\t\t\tu64 aux: 1;\n\t\t\tu64 basic: 1;\n\t\t};\n\t};\n\tu64 rsvd6;\n};\n\nunion arch_pebs_index {\n\tstruct {\n\t\tu64 rsvd: 4;\n\t\tu64 wr: 23;\n\t\tu64 rsvd2: 4;\n\t\tu64 full: 1;\n\t\tu64 en: 1;\n\t\tu64 rsvd3: 3;\n\t\tu64 thresh: 23;\n\t\tu64 rsvd4: 5;\n\t};\n\tu64 whole;\n};\n\nstruct arch_pebs_lbr_header {\n\tu64 rsvd;\n\tu64 ctl;\n\tu64 depth;\n\tu64 ler_from;\n\tu64 ler_to;\n\tu64 ler_info;\n};\n\nstruct kprobe;\n\nstruct arch_specific_insn {\n\tkprobe_opcode_t *insn;\n\tunsigned int boostable: 1;\n\tunsigned char size;\n\tunion {\n\t\tunsigned char opcode;\n\t\tstruct {\n\t\t\tunsigned char type;\n\t\t} jcc;\n\t\tstruct {\n\t\t\tunsigned char type;\n\t\t\tunsigned char asize;\n\t\t} loop;\n\t\tstruct {\n\t\t\tunsigned char reg;\n\t\t} indirect;\n\t};\n\ts32 rel32;\n\tvoid (*emulate_op)(struct kprobe *, struct pt_regs *);\n\tint tp_len;\n};\n\nstruct arch_tlbflush_unmap_batch {\n\tstruct cpumask cpumask;\n\tbool unmapped_pages;\n};\n\nstruct uprobe_xol_ops;\n\nstruct arch_uprobe {\n\tunion {\n\t\tu8 insn[16];\n\t\tu8 ixol[16];\n\t};\n\tconst struct uprobe_xol_ops *ops;\n\tunion {\n\t\tstruct {\n\t\t\ts32 offs;\n\t\t\tu8 ilen;\n\t\t\tu8 opc1;\n\t\t} branch;\n\t\tstruct {\n\t\t\tu8 fixups;\n\t\t\tu8 ilen;\n\t\t} defparam;\n\t\tstruct {\n\t\t\tu8 reg_offset;\n\t\t\tu8 ilen;\n\t\t} push;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct arch_uprobe_task {\n\tlong unsigned int saved_scratch_register;\n\tunsigned int saved_trap_nr;\n\tunsigned int saved_tf;\n};\n\nstruct sysv_va_list {\n\tunsigned int gp_offset;\n\tunsigned int fp_offset;\n\tvoid *overflow_arg_area;\n\tvoid *reg_save_area;\n};\n\nstruct arch_va_list {\n\tlong unsigned int regs[6];\n\tstruct sysv_va_list args;\n};\n\nstruct arch_vdso_time_data {};\n\nstruct arena_free_span {\n\tstruct llist_node node;\n\tlong unsigned int uaddr;\n\tu32 page_cnt;\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct trace_array;\n\nstruct trace_buffer;\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tu64 time_start;\n\tint cpu;\n};\n\ntypedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t);\n\nstruct asn1_decoder {\n\tconst unsigned char *machine;\n\tsize_t machlen;\n\tconst asn1_action_t *actions;\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct asymmetric_key_id {\n\tshort unsigned int len;\n\tunsigned char data[0];\n};\n\nstruct asymmetric_key_ids {\n\tvoid *id[3];\n};\n\nstruct key_preparsed_payload;\n\nstruct asymmetric_key_parser {\n\tstruct list_head link;\n\tstruct module *owner;\n\tconst char *name;\n\tint (*parse)(struct key_preparsed_payload *);\n};\n\nstruct key;\n\nstruct seq_file;\n\nstruct kernel_pkey_params;\n\nstruct kernel_pkey_query;\n\nstruct public_key_signature;\n\nstruct asymmetric_key_subtype {\n\tstruct module *owner;\n\tconst char *name;\n\tshort unsigned int name_len;\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tvoid (*destroy)(void *, void *);\n\tint (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*verify_signature)(const struct key *, const struct public_key_signature *);\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct ata_acpi_drive {\n\tu32 pio;\n\tu32 dma;\n};\n\nstruct ata_acpi_gtf {\n\tu8 tf[7];\n};\n\nstruct ata_acpi_gtm {\n\tstruct ata_acpi_drive drive[2];\n\tu32 flags;\n};\n\nstruct ata_device;\n\nstruct ata_acpi_hotplug_context {\n\tstruct acpi_hotplug_context hp;\n\tunion {\n\t\tstruct ata_port *ap;\n\t\tstruct ata_device *dev;\n\t} data;\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nstruct ata_cdl {\n\tu8 desc_log_buf[512];\n\tu8 ncq_sense_log_buf[1024];\n};\n\nstruct ata_cpr {\n\tu8 num;\n\tu8 num_storage_elements;\n\tu64 start_lba;\n\tu64 num_lbas;\n};\n\nstruct ata_cpr_log {\n\tu8 nr_cpr;\n\tstruct ata_cpr cpr[0];\n};\n\nstruct ata_dev_quirk_value {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 val;\n};\n\nstruct ata_dev_quirks_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 quirks;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tu64 quirks;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tunion acpi_object *gtf_cache;\n\tunsigned int gtf_filter;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 gp_log_dir[512];\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tstruct ata_cpr_log *cpr_log;\n\tstruct ata_cdl *cdl;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 sector_buf[512];\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst unsigned int *timeouts;\n};\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[16];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tu64 value;\n\tu8 cbl;\n\tu8 spd_limit;\n\tunsigned int xfer_mask;\n\tu64 quirk_on;\n\tu64 quirk_off;\n\tunsigned int pflags_on;\n\tu16 lflags_on;\n\tu16 lflags_off;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tunion {\n\t\tu8 error;\n\t\tu8 feature;\n\t};\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tunion {\n\t\tu8 status;\n\t\tu8 command;\n\t};\n\tu32 auxiliary;\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct scsi_cmnd;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tu64 qc_active;\n\tint nr_active_links;\n\tstruct work_struct deferred_qc_work;\n\tstruct ata_queued_cmd *deferred_qc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct delayed_work scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tunsigned int fastdrain_cnt;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tstruct ata_acpi_gtm __acpi_init_gtm;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nstruct ata_reset_operations {\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tvoid (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tvoid (*qc_ncq_fill_rtf)(struct ata_port *, u64);\n\tint (*cable_detect)(struct ata_port *);\n\tunsigned int (*mode_filter)(struct ata_device *, unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, __le16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tstruct ata_reset_operations reset;\n\tstruct ata_reset_operations pmp_reset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nstruct ata_timing {\n\tshort unsigned int mode;\n\tshort unsigned int setup;\n\tshort unsigned int act8b;\n\tshort unsigned int rec8b;\n\tshort unsigned int cyc8b;\n\tshort unsigned int active;\n\tshort unsigned int recover;\n\tshort unsigned int dmack_hold;\n\tshort unsigned int cycle;\n\tshort unsigned int udma;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ps2dev;\n\ntypedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int);\n\ntypedef void (*ps2_receive_handler_t)(struct ps2dev *, u8);\n\nstruct serio;\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n\tps2_pre_receive_handler_t pre_receive_handler;\n\tps2_receive_handler_t receive_handler;\n};\n\nstruct vivaldi_data {\n\tu32 function_row_physmap[24];\n\tunsigned int num_function_row_keys;\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[8];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tstruct vivaldi_data vdata;\n};\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct aud_ts_cdclk_m_n {\n\tu8 m;\n\tu16 n;\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct authenc_esn_instance_ctx {\n\tstruct crypto_ahash_spawn auth;\n\tstruct crypto_skcipher_spawn enc;\n};\n\nstruct authenc_esn_request_ctx {\n\tstruct scatterlist src[2];\n\tstruct scatterlist dst[2];\n\tchar tail[0];\n};\n\nstruct authenc_instance_ctx {\n\tstruct crypto_ahash_spawn auth;\n\tstruct crypto_skcipher_spawn enc;\n\tunsigned int reqoff;\n};\n\nstruct authenc_request_ctx {\n\tstruct scatterlist src[2];\n\tstruct scatterlist dst[2];\n\tchar tail[0];\n};\n\nstruct i915_active {\n\tatomic_t count;\n\tstruct mutex mutex;\n\tspinlock_t tree_lock;\n\tstruct active_node *cache;\n\tstruct rb_root tree;\n\tstruct i915_active_fence excl;\n\tlong unsigned int flags;\n\tint (*active)(struct i915_active *);\n\tvoid (*retire)(struct i915_active *);\n\tstruct work_struct work;\n\tstruct llist_head preallocated_barriers;\n};\n\nstruct auto_active {\n\tstruct i915_active base;\n\tstruct kref ref;\n};\n\nstruct auto_movable_group_stats {\n\tlong unsigned int movable_pages;\n\tlong unsigned int req_kernel_early_pages;\n};\n\nstruct auto_movable_stats {\n\tlong unsigned int kernel_early_pages;\n\tlong unsigned int movable_pages;\n};\n\nstruct auto_out_pin {\n\thda_nid_t pin;\n\tshort int seq;\n};\n\nstruct task_group;\n\nstruct autogroup {\n\tstruct kref kref;\n\tstruct task_group *tg;\n\tstruct rw_semaphore lock;\n\tlong unsigned int id;\n\tint nice;\n};\n\nstruct auxiliary_device {\n\tstruct device dev;\n\tconst char *name;\n\tu32 id;\n\tstruct {\n\t\tstruct xarray irqs;\n\t\tstruct mutex lock;\n\t\tbool irq_dir_exists;\n\t} sysfs;\n};\n\nstruct auxiliary_device_id {\n\tchar name[40];\n\tkernel_ulong_t driver_data;\n};\n\nstruct auxiliary_driver {\n\tint (*probe)(struct auxiliary_device *, const struct auxiliary_device_id *);\n\tvoid (*remove)(struct auxiliary_device *);\n\tvoid (*shutdown)(struct auxiliary_device *);\n\tint (*suspend)(struct auxiliary_device *, pm_message_t);\n\tint (*resume)(struct auxiliary_device *);\n\tconst char *name;\n\tstruct device_driver driver;\n\tconst struct auxiliary_device_id *id_table;\n};\n\nstruct auxiliary_irq_info {\n\tstruct device_attribute sysfs_attr;\n\tchar name[11];\n};\n\nstruct hdac_rb {\n\t__le32 *buf;\n\tdma_addr_t addr;\n\tshort unsigned int rp;\n\tshort unsigned int wp;\n\tint cmds[8];\n\tu32 res[8];\n};\n\nstruct snd_dma_device {\n\tint type;\n\tenum dma_data_direction dir;\n\tbool need_sync;\n\tstruct device *dev;\n};\n\nstruct snd_dma_buffer {\n\tstruct snd_dma_device dev;\n\tunsigned char *area;\n\tdma_addr_t addr;\n\tsize_t bytes;\n\tvoid *private_data;\n};\n\nstruct hdac_bus_ops;\n\nstruct hdac_ext_bus_ops;\n\nstruct hdac_device;\n\nstruct drm_audio_component;\n\nstruct hdac_bus {\n\tstruct device *dev;\n\tconst struct hdac_bus_ops *ops;\n\tconst struct hdac_ext_bus_ops *ext_ops;\n\tlong unsigned int addr;\n\tvoid *remap_addr;\n\tint irq;\n\tvoid *ppcap;\n\tvoid *spbcap;\n\tvoid *mlcap;\n\tvoid *gtscap;\n\tvoid *drsmcap;\n\tstruct list_head codec_list;\n\tunsigned int num_codecs;\n\tstruct hdac_device *caddr_tbl[16];\n\tu32 unsol_queue[128];\n\tunsigned int unsol_rp;\n\tunsigned int unsol_wp;\n\tstruct work_struct unsol_work;\n\tlong unsigned int codec_mask;\n\tlong unsigned int codec_powered;\n\tstruct hdac_rb corb;\n\tstruct hdac_rb rirb;\n\tunsigned int last_cmd[8];\n\twait_queue_head_t rirb_wq;\n\tstruct snd_dma_buffer rb;\n\tstruct snd_dma_buffer posbuf;\n\tint dma_type;\n\tstruct list_head stream_list;\n\tbool chip_init: 1;\n\tbool aligned_mmio: 1;\n\tbool sync_write: 1;\n\tbool use_posbuf: 1;\n\tbool snoop: 1;\n\tbool align_bdle_4k: 1;\n\tbool reverse_assign: 1;\n\tbool corbrp_self_clear: 1;\n\tbool polling_mode: 1;\n\tbool needs_damn_long_delay: 1;\n\tbool not_use_interrupts: 1;\n\tbool access_sdnctl_in_dword: 1;\n\tbool use_pio_for_commands: 1;\n\tint poll_count;\n\tint bdl_pos_adj;\n\tunsigned int dma_stop_delay;\n\tspinlock_t reg_lock;\n\tstruct mutex cmd_mutex;\n\tstruct mutex lock;\n\tstruct drm_audio_component *audio_component;\n\tlong int display_power_status;\n\tlong unsigned int display_power_active;\n\tint num_streams;\n\tint idx;\n\tstruct list_head hlink_list;\n\tbool cmd_dma_state;\n\tunsigned int sdo_limit;\n\tdma_addr_t addr_offset;\n};\n\nstruct snd_card;\n\nstruct hda_bus {\n\tstruct hdac_bus core;\n\tstruct snd_card *card;\n\tstruct pci_dev *pci;\n\tconst char *modelname;\n\tstruct mutex prepare_mutex;\n\tlong unsigned int pcm_dev_bits[1];\n\tunsigned int allow_bus_reset: 1;\n\tunsigned int shutdown: 1;\n\tunsigned int response_reset: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int no_response_fallback: 1;\n\tunsigned int bus_probing: 1;\n\tunsigned int keep_power: 1;\n\tunsigned int jackpoll_in_suspend: 1;\n\tint primary_dig_out_type;\n\tunsigned int mixer_assigned;\n};\n\nstruct azx;\n\nstruct azx_dev;\n\ntypedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);\n\ntypedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int);\n\nstruct hda_controller_ops;\n\nstruct azx {\n\tstruct hda_bus bus;\n\tstruct snd_card *card;\n\tstruct pci_dev *pci;\n\tint dev_index;\n\tint driver_type;\n\tunsigned int driver_caps;\n\tint playback_streams;\n\tint playback_index_offset;\n\tint capture_streams;\n\tint capture_index_offset;\n\tint num_streams;\n\tint jackpoll_interval;\n\tconst struct hda_controller_ops *ops;\n\tazx_get_pos_callback_t get_position[2];\n\tazx_get_delay_callback_t get_delay[2];\n\tstruct mutex open_mutex;\n\tstruct list_head pcm_list;\n\tint codec_probe_mask;\n\tunsigned int beep_mode;\n\tbool ctl_dev_id;\n\tint bdl_pos_adj;\n\tunsigned int running: 1;\n\tunsigned int fallback_to_single_cmd: 1;\n\tunsigned int single_cmd: 1;\n\tunsigned int msi: 1;\n\tunsigned int probing: 1;\n\tunsigned int snoop: 1;\n\tunsigned int uc_buffer: 1;\n\tunsigned int align_buffer_size: 1;\n\tunsigned int disabled: 1;\n\tunsigned int pm_prepared: 1;\n\tunsigned int gts_present: 1;\n};\n\nstruct cyclecounter;\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct snd_compr_stream;\n\nstruct hdac_stream {\n\tstruct hdac_bus *bus;\n\tstruct snd_dma_buffer bdl;\n\t__le32 *posbuf;\n\tint direction;\n\tunsigned int bufsize;\n\tunsigned int period_bytes;\n\tunsigned int frags;\n\tunsigned int fifo_size;\n\tvoid *sd_addr;\n\tvoid *spib_addr;\n\tvoid *fifo_addr;\n\tvoid *dpibr_addr;\n\tu32 dpib;\n\tu32 lpib;\n\tu32 sd_int_sta_mask;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_compr_stream *cstream;\n\tunsigned int format_val;\n\tunsigned char stream_tag;\n\tunsigned char index;\n\tint assigned_key;\n\tbool opened: 1;\n\tbool running: 1;\n\tbool prepared: 1;\n\tbool no_period_wakeup: 1;\n\tbool locked: 1;\n\tbool stripe: 1;\n\tu64 curr_pos;\n\tlong unsigned int start_wallclk;\n\tlong unsigned int period_wallclk;\n\tstruct timecounter tc;\n\tstruct cyclecounter cc;\n\tint delay_negative_threshold;\n\tstruct list_head list;\n};\n\nstruct azx_dev {\n\tstruct hdac_stream core;\n\tunsigned int irq_pending: 1;\n\tunsigned int insufficient: 1;\n};\n\nstruct snd_pcm;\n\nstruct azx_pcm {\n\tstruct azx *chip;\n\tstruct snd_pcm *pcm;\n\tstruct hda_codec *codec;\n\tstruct hda_pcm *info;\n\tstruct list_head list;\n};\n\nstruct backing_aio {\n\tstruct kiocb iocb;\n\trefcount_t ref;\n\tstruct kiocb *orig_iocb;\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n\tstruct work_struct work;\n\tlong int res;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct backing_dev_info;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tloff_t prev_pos;\n};\n\nstruct file_operations;\n\nstruct fown_struct;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backing_file_ctx {\n\tconst struct cred *cred;\n\tvoid (*accessed)(struct file *);\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n};\n\nstruct backlight_properties {\n\tint brightness;\n\tint max_brightness;\n\tint power;\n\tenum backlight_type type;\n\tunsigned int state;\n\tenum backlight_scale scale;\n};\n\nstruct backlight_ops;\n\nstruct backlight_device {\n\tstruct backlight_properties props;\n\tstruct mutex update_lock;\n\tstruct mutex ops_lock;\n\tconst struct backlight_ops *ops;\n\tstruct list_head entry;\n\tstruct device dev;\n\tint use_count;\n};\n\nstruct backlight_ops {\n\tunsigned int options;\n\tint (*update_status)(struct backlight_device *);\n\tint (*get_brightness)(struct backlight_device *);\n\tbool (*controls_device)(struct backlight_device *, struct device *);\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n\tspinlock_t *lock;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n};\n\nstruct badness_table {\n\tint no_primary_dac;\n\tint no_dac;\n\tint shared_primary;\n\tint shared_surr;\n\tint shared_clfe;\n\tint shared_surr_main;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct balloon_dev_info {\n\tlong unsigned int isolated_pages;\n\tstruct list_head pages;\n\tint (*migratepage)(struct balloon_dev_info *, struct page *, struct page *, enum migrate_mode);\n\tbool adjust_managed_page_count;\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct i915_vma;\n\nstruct batch_chunk {\n\tstruct i915_vma *vma;\n\tu32 offset;\n\tu32 *start;\n\tu32 *end;\n\tu32 max_items;\n};\n\nstruct local_lock {\n\tstruct lockdep_map dep_map;\n\tstruct task_struct *owner;\n};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_vals {\n\tu32 max_threads;\n\tu32 state_start;\n\tu32 surface_start;\n\tu32 surface_height;\n\tu32 surface_width;\n\tu32 size;\n};\n\nstruct bd_holder_disk {\n\tstruct list_head list;\n\tstruct kobject *holder_dir;\n\tint refcnt;\n};\n\nstruct bdb_block_entry {\n\tstruct list_head node;\n\tenum bdb_block_id section_id;\n\tu8 data[0];\n};\n\nstruct dsc_compression_parameters_entry {\n\tu8 version_major: 4;\n\tu8 version_minor: 4;\n\tu8 rc_buffer_block_size: 2;\n\tu8 reserved1: 6;\n\tu8 rc_buffer_size;\n\tu32 slices_per_line;\n\tu8 line_buffer_depth: 4;\n\tu8 reserved2: 4;\n\tu8 block_prediction_enable: 1;\n\tu8 reserved3: 7;\n\tu8 max_bpp;\n\tu8 reserved4: 1;\n\tu8 support_8bpc: 1;\n\tu8 support_10bpc: 1;\n\tu8 support_12bpc: 1;\n\tu8 reserved5: 4;\n\tu16 slice_height;\n} __attribute__((packed));\n\nstruct bdb_compression_parameters {\n\tu16 entry_size;\n\tstruct dsc_compression_parameters_entry data[16];\n};\n\nstruct bdb_driver_features {\n\tu8 boot_dev_algorithm: 1;\n\tu8 allow_display_switch_dvd: 1;\n\tu8 allow_display_switch_dos: 1;\n\tu8 hotplug_dvo: 1;\n\tu8 dual_view_zoom: 1;\n\tu8 int15h_hook: 1;\n\tu8 sprite_in_clone: 1;\n\tu8 primary_lfp_id: 1;\n\tu16 boot_mode_x;\n\tu16 boot_mode_y;\n\tu8 boot_mode_bpp;\n\tu8 boot_mode_refresh;\n\tu16 enable_lfp_primary: 1;\n\tu16 selective_mode_pruning: 1;\n\tu16 dual_frequency: 1;\n\tu16 render_clock_freq: 1;\n\tu16 nt_clone_support: 1;\n\tu16 power_scheme_ui: 1;\n\tu16 sprite_display_assign: 1;\n\tu16 cui_aspect_scaling: 1;\n\tu16 preserve_aspect_ratio: 1;\n\tu16 sdvo_device_power_down: 1;\n\tu16 crt_hotplug: 1;\n\tu16 lvds_config: 2;\n\tu16 tv_hotplug: 1;\n\tu16 hdmi_config: 2;\n\tu8 static_display: 1;\n\tu8 embedded_platform: 1;\n\tu8 display_subsystem_enable: 1;\n\tu8 reserved0: 5;\n\tu16 legacy_crt_max_x;\n\tu16 legacy_crt_max_y;\n\tu8 legacy_crt_max_refresh;\n\tu8 hdmi_termination: 1;\n\tu8 cea861d_hdmi_support: 1;\n\tu8 self_refresh_enable: 1;\n\tu8 reserved1: 5;\n\tu8 custom_vbt_version;\n\tu16 rmpm_enabled: 1;\n\tu16 s2ddt_enabled: 1;\n\tu16 dpst_enabled: 1;\n\tu16 bltclt_enabled: 1;\n\tu16 adb_enabled: 1;\n\tu16 drrs_enabled: 1;\n\tu16 grs_enabled: 1;\n\tu16 gpmt_enabled: 1;\n\tu16 tbt_enabled: 1;\n\tu16 psr_enabled: 1;\n\tu16 ips_enabled: 1;\n\tu16 dfps_enabled: 1;\n\tu16 dmrrs_enabled: 1;\n\tu16 adt_enabled: 1;\n\tu16 hpd_wake: 1;\n\tu16 pc_feature_valid: 1;\n} __attribute__((packed));\n\nstruct bdb_edid_dtd {\n\tu16 clock;\n\tu8 hactive_lo;\n\tu8 hblank_lo;\n\tu8 hblank_hi: 4;\n\tu8 hactive_hi: 4;\n\tu8 vactive_lo;\n\tu8 vblank_lo;\n\tu8 vblank_hi: 4;\n\tu8 vactive_hi: 4;\n\tu8 hsync_off_lo;\n\tu8 hsync_pulse_width_lo;\n\tu8 vsync_pulse_width_lo: 4;\n\tu8 vsync_off_lo: 4;\n\tu8 vsync_pulse_width_hi: 2;\n\tu8 vsync_off_hi: 2;\n\tu8 hsync_pulse_width_hi: 2;\n\tu8 hsync_off_hi: 2;\n\tu8 himage_lo;\n\tu8 vimage_lo;\n\tu8 vimage_hi: 4;\n\tu8 himage_hi: 4;\n\tu8 h_border;\n\tu8 v_border;\n\tu8 rsvd1: 3;\n\tu8 digital: 2;\n\tu8 vsync_positive: 1;\n\tu8 hsync_positive: 1;\n\tu8 non_interlaced: 1;\n};\n\nstruct bdb_edid_pnp_id {\n\tu16 mfg_name;\n\tu16 product_code;\n\tu32 serial;\n\tu8 mfg_week;\n\tu8 mfg_year;\n} __attribute__((packed));\n\nstruct bdb_edid_product_name {\n\tchar name[13];\n};\n\nstruct edp_power_seq {\n\tu16 t1_t3;\n\tu16 t8;\n\tu16 t9;\n\tu16 t10;\n\tu16 t11_t12;\n};\n\nstruct edp_fast_link_params {\n\tu8 rate: 4;\n\tu8 lanes: 4;\n\tu8 preemphasis: 4;\n\tu8 vswing: 4;\n};\n\nstruct edp_pwm_delays {\n\tu16 pwm_on_to_backlight_enable;\n\tu16 backlight_disable_to_pwm_off;\n};\n\nstruct edp_full_link_params {\n\tu8 preemphasis: 4;\n\tu8 vswing: 4;\n};\n\nstruct edp_apical_params {\n\tu32 panel_oui;\n\tu32 dpcd_base_address;\n\tu32 dpcd_idridix_control_0;\n\tu32 dpcd_option_select;\n\tu32 dpcd_backlight;\n\tu32 ambient_light;\n\tu32 backlight_scale;\n};\n\nstruct bdb_edp {\n\tstruct edp_power_seq power_seqs[16];\n\tu32 color_depth;\n\tstruct edp_fast_link_params fast_link_params[16];\n\tu32 sdrrs_msa_timing_delay;\n\tu16 edp_s3d_feature;\n\tu16 edp_t3_optimization;\n\tu64 edp_vswing_preemph;\n\tu16 fast_link_training;\n\tu16 dpcd_600h_write_required;\n\tstruct edp_pwm_delays pwm_delays[16];\n\tu16 full_link_params_provided;\n\tstruct edp_full_link_params full_link_params[16];\n\tu16 apical_enable;\n\tstruct edp_apical_params apical_params[16];\n\tu16 edp_fast_link_training_rate[16];\n\tu16 edp_max_port_link_rate[16];\n\tu16 edp_dsc_disable;\n\tu16 t6_delay_support;\n\tu16 link_idle_time[16];\n} __attribute__((packed));\n\nstruct bdb_general_definitions {\n\tu8 crt_ddc_gmbus_pin;\n\tu8 dpms_non_acpi: 1;\n\tu8 skip_boot_crt_detect: 1;\n\tu8 dpms_aim: 1;\n\tu8 rsvd1: 5;\n\tu8 boot_display[2];\n\tu8 child_dev_size;\n\tu8 devices[0];\n};\n\nstruct bdb_general_features {\n\tu8 panel_fitting: 2;\n\tu8 flexaim: 1;\n\tu8 msg_enable: 1;\n\tu8 clear_screen: 3;\n\tu8 color_flip: 1;\n\tu8 download_ext_vbt: 1;\n\tu8 enable_ssc: 1;\n\tu8 ssc_freq: 1;\n\tu8 enable_lfp_on_override: 1;\n\tu8 disable_ssc_ddt: 1;\n\tu8 underscan_vga_timings: 1;\n\tu8 display_clock_mode: 1;\n\tu8 vbios_hotplug_support: 1;\n\tu8 disable_smooth_vision: 1;\n\tu8 single_dvi: 1;\n\tu8 rotate_180: 1;\n\tu8 fdi_rx_polarity_inverted: 1;\n\tu8 vbios_extended_mode: 1;\n\tu8 copy_ilfp_dtd_to_sdvo_lvds_dtd: 1;\n\tu8 panel_best_fit_timing: 1;\n\tu8 ignore_strap_state: 1;\n\tu8 legacy_monitor_detect;\n\tu8 int_crt_support: 1;\n\tu8 int_tv_support: 1;\n\tu8 int_efp_support: 1;\n\tu8 dp_ssc_enable: 1;\n\tu8 dp_ssc_freq: 1;\n\tu8 dp_ssc_dongle_supported: 1;\n\tu8 rsvd11: 2;\n\tu8 tc_hpd_retry_timeout: 7;\n\tu8 rsvd12: 1;\n\tu8 afc_startup_config: 2;\n\tu8 rsvd13: 6;\n};\n\nstruct generic_dtd_entry {\n\tu32 pixel_clock;\n\tu16 hactive;\n\tu16 hblank;\n\tu16 hfront_porch;\n\tu16 hsync;\n\tu16 vactive;\n\tu16 vblank;\n\tu16 vfront_porch;\n\tu16 vsync;\n\tu16 width_mm;\n\tu16 height_mm;\n\tu8 rsvd_flags: 6;\n\tu8 vsync_positive_polarity: 1;\n\tu8 hsync_positive_polarity: 1;\n\tu8 rsvd[3];\n};\n\nstruct bdb_generic_dtd {\n\tu16 gdtd_size;\n\tstruct generic_dtd_entry dtd[0];\n} __attribute__((packed));\n\nstruct bdb_header {\n\tu8 signature[16];\n\tu16 version;\n\tu16 header_size;\n\tu16 bdb_size;\n};\n\nstruct lfp_backlight_data_entry {\n\tu8 type: 2;\n\tu8 active_low_pwm: 1;\n\tu8 i2c_pin: 3;\n\tu8 i2c_speed: 2;\n\tu16 pwm_freq_hz;\n\tu8 min_brightness;\n\tu8 i2c_address;\n\tu8 i2c_command;\n} __attribute__((packed));\n\nstruct lfp_backlight_control_method {\n\tu8 type: 4;\n\tu8 controller: 4;\n};\n\nstruct lfp_brightness_level {\n\tu16 level;\n\tu16 reserved;\n};\n\nstruct bdb_lfp_backlight {\n\tu8 entry_size;\n\tstruct lfp_backlight_data_entry data[16];\n\tu8 level[16];\n\tstruct lfp_backlight_control_method backlight_control[16];\n\tstruct lfp_brightness_level brightness_level[16];\n\tstruct lfp_brightness_level brightness_min_level[16];\n\tu8 brightness_precision_bits[16];\n\tu16 hdr_dpcd_refresh_timeout[16];\n} __attribute__((packed));\n\nstruct fp_timing {\n\tu16 x_res;\n\tu16 y_res;\n\tu32 lvds_reg;\n\tu32 lvds_reg_val;\n\tu32 pp_on_reg;\n\tu32 pp_on_reg_val;\n\tu32 pp_off_reg;\n\tu32 pp_off_reg_val;\n\tu32 pp_cycle_reg;\n\tu32 pp_cycle_reg_val;\n\tu32 pfit_reg;\n\tu32 pfit_reg_val;\n\tu16 terminator;\n} __attribute__((packed));\n\nstruct lfp_data_entry {\n\tstruct fp_timing fp_timing;\n\tstruct bdb_edid_dtd dvo_timing;\n\tstruct bdb_edid_pnp_id pnp_id;\n};\n\nstruct bdb_lfp_data {\n\tstruct lfp_data_entry data[16];\n};\n\nstruct lfp_data_ptr_table {\n\tu16 offset;\n\tu8 table_size;\n} __attribute__((packed));\n\nstruct lfp_data_ptr {\n\tstruct lfp_data_ptr_table fp_timing;\n\tstruct lfp_data_ptr_table dvo_timing;\n\tstruct lfp_data_ptr_table panel_pnp_id;\n};\n\nstruct bdb_lfp_data_ptrs {\n\tu8 num_entries;\n\tstruct lfp_data_ptr ptr[16];\n\tstruct lfp_data_ptr_table panel_name;\n};\n\nstruct lfp_black_border {\n\tu8 top;\n\tu8 bottom;\n\tu8 left;\n\tu8 right;\n};\n\nstruct bdb_lfp_data_tail {\n\tstruct bdb_edid_product_name panel_name[16];\n\tu16 scaling_enable;\n\tu8 seamless_drrs_min_refresh_rate[16];\n\tu8 pixel_overlap_count[16];\n\tstruct lfp_black_border black_border[16];\n\tu16 dual_lfp_port_sync_enable;\n\tu16 gpu_dithering_for_banding_artifacts;\n};\n\nstruct bdb_lfp_options {\n\tu8 panel_type;\n\tu8 panel_type2;\n\tu8 pfit_mode: 2;\n\tu8 pfit_text_mode_enhanced: 1;\n\tu8 pfit_gfx_mode_enhanced: 1;\n\tu8 pfit_ratio_auto: 1;\n\tu8 pixel_dither: 1;\n\tu8 lvds_edid: 1;\n\tu8 rsvd2: 1;\n\tu8 rsvd4;\n\tu32 lvds_panel_channel_bits;\n\tu16 ssc_bits;\n\tu16 ssc_freq;\n\tu16 ssc_ddt;\n\tu16 panel_color_depth;\n\tu32 dps_panel_type_bits;\n\tu32 blt_control_type_bits;\n\tu16 lcdvcc_s0_enable;\n\tu32 rotation;\n\tu32 position;\n} __attribute__((packed));\n\nstruct lfp_power_features {\n\tu8 dpst_support: 1;\n\tu8 power_conservation_pref: 3;\n\tu8 reserved2: 1;\n\tu8 lace_enabled_status: 1;\n\tu8 lace_support: 1;\n\tu8 als_enable: 1;\n};\n\nstruct panel_identification {\n\tu8 panel_technology: 4;\n\tu8 reserved: 4;\n};\n\nstruct bdb_lfp_power {\n\tstruct lfp_power_features features;\n\tstruct als_data_entry als[5];\n\tu8 lace_aggressiveness_profile: 3;\n\tu8 reserved1: 5;\n\tu16 dpst;\n\tu16 psr;\n\tu16 drrs;\n\tu16 lace_support;\n\tu16 adt;\n\tu16 dmrrs;\n\tu16 adb;\n\tu16 lace_enabled_status;\n\tstruct aggressiveness_profile_entry aggressiveness[16];\n\tu16 hobl;\n\tu16 vrr_feature_enabled;\n\tu16 elp;\n\tu16 opst;\n\tstruct aggressiveness_profile2_entry aggressiveness2[16];\n\tu16 apd;\n\tu16 pixoptix;\n\tstruct aggressiveness_profile3_entry aggressiveness3[16];\n\tstruct panel_identification panel_identification[16];\n\tu16 xpst_support;\n\tu16 tcon_based_backlight_optimization;\n\tstruct aggressiveness_profile4_entry aggressiveness4[16];\n\tu16 tcon_backlight_xpst_coexistence;\n} __attribute__((packed));\n\nstruct mipi_config {\n\tu16 panel_id;\n\tstruct {\n\t\tu32 enable_dithering: 1;\n\t\tu32 rsvd1: 1;\n\t\tu32 is_bridge: 1;\n\t\tu32 panel_arch_type: 2;\n\t\tu32 is_cmd_mode: 1;\n\t\tu32 video_transfer_mode: 2;\n\t\tu32 cabc_supported: 1;\n\t\tu32 pwm_blc: 1;\n\t\tu32 videomode_color_format: 4;\n\t\tu32 rotation: 2;\n\t\tu32 bta_disable: 1;\n\t\tu32 rsvd2: 15;\n\t};\n\tstruct {\n\t\tu16 dual_link: 2;\n\t\tu16 lane_cnt: 2;\n\t\tu16 pixel_overlap: 3;\n\t\tu16 rgb_flip: 1;\n\t\tu16 dl_dcs_cabc_ports: 2;\n\t\tu16 dl_dcs_backlight_ports: 2;\n\t\tu16 port_sync: 1;\n\t\tu16 rsvd3: 3;\n\t};\n\tstruct {\n\t\tu16 dsi_usage: 1;\n\t\tu16 rsvd4: 15;\n\t};\n\tu8 rsvd5;\n\tu32 target_burst_mode_freq;\n\tu32 dsi_ddr_clk;\n\tu32 bridge_ref_clk;\n\tstruct {\n\t\tu8 byte_clk_sel: 2;\n\t\tu8 rsvd6: 6;\n\t};\n\tstruct {\n\t\tu16 dphy_param_valid: 1;\n\t\tu16 eot_pkt_disabled: 1;\n\t\tu16 enable_clk_stop: 1;\n\t\tu16 blanking_packets_during_bllp: 1;\n\t\tu16 lp_clock_during_lpm: 1;\n\t\tu16 rsvd7: 11;\n\t};\n\tu32 hs_tx_timeout;\n\tu32 lp_rx_timeout;\n\tu32 turn_around_timeout;\n\tu32 device_reset_timer;\n\tu32 master_init_timer;\n\tu32 dbi_bw_timer;\n\tu32 lp_byte_clk_val;\n\tstruct {\n\t\tu32 prepare_cnt: 6;\n\t\tu32 rsvd8: 2;\n\t\tu32 clk_zero_cnt: 8;\n\t\tu32 trail_cnt: 5;\n\t\tu32 rsvd9: 3;\n\t\tu32 exit_zero_cnt: 6;\n\t\tu32 rsvd10: 2;\n\t};\n\tu32 clk_lane_switch_cnt;\n\tu32 hl_switch_cnt;\n\tu32 rsvd11[6];\n\tu8 tclk_miss;\n\tu8 tclk_post;\n\tu8 rsvd12;\n\tu8 tclk_pre;\n\tu8 tclk_prepare;\n\tu8 tclk_settle;\n\tu8 tclk_term_enable;\n\tu8 tclk_trail;\n\tu16 tclk_prepare_clkzero;\n\tu8 rsvd13;\n\tu8 td_term_enable;\n\tu8 teot;\n\tu8 ths_exit;\n\tu8 ths_prepare;\n\tu16 ths_prepare_hszero;\n\tu8 rsvd14;\n\tu8 ths_settle;\n\tu8 ths_skip;\n\tu8 ths_trail;\n\tu8 tinit;\n\tu8 tlpx;\n\tu8 rsvd15[3];\n\tu8 panel_enable;\n\tu8 bl_enable;\n\tu8 pwm_enable;\n\tu8 reset_r_n;\n\tu8 pwr_down_r;\n\tu8 stdby_r_n;\n} __attribute__((packed));\n\nstruct mipi_pps_data {\n\tu16 panel_on_delay;\n\tu16 bl_enable_delay;\n\tu16 bl_disable_delay;\n\tu16 panel_off_delay;\n\tu16 panel_power_cycle_delay;\n};\n\nstruct bdb_mipi_config {\n\tstruct mipi_config config[6];\n\tstruct mipi_pps_data pps[6];\n\tstruct edp_pwm_delays pwm_delays[6];\n\tu8 pmic_i2c_bus_number[6];\n};\n\nstruct bdb_mipi_sequence {\n\tu8 version;\n\tu8 data[0];\n};\n\nstruct psr_table {\n\tu8 full_link: 1;\n\tu8 require_aux_to_wakeup: 1;\n\tu8 feature_bits_rsvd: 6;\n\tu8 idle_frames: 4;\n\tu8 lines_to_wait: 3;\n\tu8 wait_times_rsvd: 1;\n\tu16 tp1_wakeup_time;\n\tu16 tp2_tp3_wakeup_time;\n};\n\nstruct bdb_psr {\n\tstruct psr_table psr_table[16];\n\tu32 psr2_tp2_tp3_wakeup_time;\n};\n\nstruct bdb_sdvo_lvds_dtd {\n\tstruct bdb_edid_dtd dtd[4];\n};\n\nstruct bdb_sdvo_lvds_options {\n\tu8 panel_backlight;\n\tu8 h40_set_panel_type;\n\tu8 panel_type;\n\tu8 ssc_clk_freq;\n\tu16 als_low_trip;\n\tu16 als_high_trip;\n\tu8 sclalarcoeff_tab_row_num;\n\tu8 sclalarcoeff_tab_row_size;\n\tu8 coefficient[8];\n\tu8 panel_misc_bits_1;\n\tu8 panel_misc_bits_2;\n\tu8 panel_misc_bits_3;\n\tu8 panel_misc_bits_4;\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct super_block;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct fsnotify_mark_connector;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct buffer_head;\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct qrwlock {\n\tunion {\n\t\tatomic_t cnts;\n\t\tstruct {\n\t\t\tu8 wlocked;\n\t\t\tu8 __lstate[3];\n\t\t};\n\t};\n\tarch_spinlock_t wait_lock;\n};\n\ntypedef struct qrwlock arch_rwlock_t;\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n\tunsigned int magic;\n\tunsigned int owner_cpu;\n\tvoid *owner;\n\tstruct lockdep_map dep_map;\n};\n\nstruct binfmt_misc {\n\tstruct list_head entries;\n\trwlock_t entries_lock;\n\tbool enabled;\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n} __attribute__((packed));\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct blkcg_gq;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tstruct blkcg_gq *bi_blkg;\n\tu64 issue_time_ns;\n\tu64 bi_iocost_cost;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tu64 bc_dun[4];\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec;\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bitmap_page;\n\nstruct bitmap_counts {\n\tspinlock_t lock;\n\tstruct bitmap_page *bp;\n\tlong unsigned int pages;\n\tlong unsigned int missing_pages;\n\tlong unsigned int chunkshift;\n\tlong unsigned int chunks;\n};\n\nstruct bitmap_storage {\n\tstruct file *file;\n\tstruct page *sb_page;\n\tlong unsigned int sb_index;\n\tstruct page **filemap;\n\tlong unsigned int *filemap_attr;\n\tlong unsigned int file_pages;\n\tlong unsigned int bytes;\n};\n\nstruct mddev;\n\nstruct bitmap {\n\tstruct bitmap_counts counts;\n\tstruct mddev *mddev;\n\t__u64 events_cleared;\n\tint need_sync;\n\tstruct bitmap_storage storage;\n\tlong unsigned int flags;\n\tint allclean;\n\tatomic_t behind_writes;\n\tlong unsigned int behind_writes_used;\n\tlong unsigned int daemon_lastrun;\n\tlong unsigned int last_end_sync;\n\tatomic_t pending_writes;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t overflow_wait;\n\twait_queue_head_t behind_wait;\n\tstruct kernfs_node *sysfs_can_clear;\n\tint cluster_slot;\n};\n\nstruct md_submodule_head {\n\tenum md_submodule_type type;\n\tenum md_submodule_id id;\n\tconst char *name;\n\tstruct module *owner;\n};\n\ntypedef void md_bitmap_fn(struct mddev *, sector_t, long unsigned int);\n\nstruct md_bitmap_stats;\n\nstruct bitmap_operations {\n\tstruct md_submodule_head head;\n\tbool (*enabled)(void *, bool);\n\tint (*create)(struct mddev *);\n\tint (*resize)(struct mddev *, sector_t, int);\n\tint (*load)(struct mddev *);\n\tvoid (*destroy)(struct mddev *);\n\tvoid (*flush)(struct mddev *);\n\tvoid (*write_all)(struct mddev *);\n\tvoid (*dirty_bits)(struct mddev *, long unsigned int, long unsigned int);\n\tvoid (*unplug)(struct mddev *, bool);\n\tvoid (*daemon_work)(struct mddev *);\n\tvoid (*start_behind_write)(struct mddev *);\n\tvoid (*end_behind_write)(struct mddev *);\n\tvoid (*wait_behind_writes)(struct mddev *);\n\tmd_bitmap_fn *start_write;\n\tmd_bitmap_fn *end_write;\n\tmd_bitmap_fn *start_discard;\n\tmd_bitmap_fn *end_discard;\n\tsector_t (*skip_sync_blocks)(struct mddev *, sector_t);\n\tbool (*blocks_synced)(struct mddev *, sector_t);\n\tbool (*start_sync)(struct mddev *, sector_t, sector_t *, bool);\n\tvoid (*end_sync)(struct mddev *, sector_t, sector_t *);\n\tvoid (*cond_end_sync)(struct mddev *, sector_t, bool);\n\tvoid (*close_sync)(struct mddev *);\n\tvoid (*update_sb)(void *);\n\tint (*get_stats)(void *, struct md_bitmap_stats *);\n\tvoid (*sync_with_cluster)(struct mddev *, sector_t, sector_t, sector_t, sector_t);\n\tvoid * (*get_from_slot)(struct mddev *, int);\n\tint (*copy_from_slot)(struct mddev *, int, sector_t *, sector_t *, bool);\n\tvoid (*set_pages)(void *, long unsigned int);\n\tvoid (*free)(void *);\n\tstruct attribute_group *group;\n};\n\nstruct bitmap_page {\n\tchar *map;\n\tunsigned int hijacked: 1;\n\tunsigned int pending: 1;\n\tunsigned int count: 30;\n};\n\nstruct bitmap_super_s {\n\t__le32 magic;\n\t__le32 version;\n\t__u8 uuid[16];\n\t__le64 events;\n\t__le64 events_cleared;\n\t__le64 sync_size;\n\t__le32 state;\n\t__le32 chunksize;\n\t__le32 daemon_sleep;\n\t__le32 write_behind;\n\t__le32 sectors_reserved;\n\t__le32 nodes;\n\t__u8 cluster_name[64];\n\t__u8 pad[120];\n};\n\ntypedef struct bitmap_super_s bitmap_super_t;\n\nstruct bitmap_unplug_work {\n\tstruct work_struct work;\n\tstruct bitmap *bitmap;\n\tstruct completion *done;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct blk_crypto_profile;\n\nstruct blk_crypto_ll_ops {\n\tint (*keyslot_program)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*keyslot_evict)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*derive_sw_secret)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*import_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*generate_key)(struct blk_crypto_profile *, u8 *);\n\tint (*prepare_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n};\n\nstruct blk_crypto_keyslot;\n\nstruct blk_crypto_profile {\n\tstruct blk_crypto_ll_ops ll_ops;\n\tunsigned int max_dun_bytes_supported;\n\tunsigned int key_types_supported;\n\tunsigned int modes_supported[5];\n\tstruct device *dev;\n\tunsigned int num_slots;\n\tstruct rw_semaphore lock;\n\tstruct lock_class_key lockdep_key;\n\twait_queue_head_t idle_slots_wait_queue;\n\tstruct list_head idle_slots;\n\tspinlock_t idle_slots_lock;\n\tstruct hlist_head *slot_hashtable;\n\tunsigned int log_slot_ht_size;\n\tstruct blk_crypto_keyslot *slots;\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct request;\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_independent_access_range;\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_io_trace {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 action;\n\t__u32 pid;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n};\n\nstruct blk_io_trace2 {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 pid;\n\t__u64 action;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n\t__u8 pad[12];\n};\n\nstruct blk_io_trace_remap {\n\t__be32 device_from;\n\t__be32 device_to;\n\t__be64 sector_from;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct blk_iolatency {\n\tstruct rq_qos rqos;\n\tstruct timer_list timer;\n\tbool enabled;\n\tatomic_t enable_cnt;\n\tstruct work_struct enable_work;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 64;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct rchan;\n\nstruct blk_trace {\n\tint version;\n\tint trace_state;\n\tstruct rchan *rchan;\n\tlong unsigned int *sequence;\n\tunsigned char *msg_data;\n\tu64 act_mask;\n\tu64 start_lba;\n\tu64 end_lba;\n\tu32 pid;\n\tu32 dev;\n\tstruct dentry *dir;\n\tstruct list_head running_list;\n\tatomic_t dropped;\n};\n\nstruct blk_user_trace_setup {\n\tchar name[32];\n\t__u16 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n};\n\nstruct blk_user_trace_setup2 {\n\tchar name[64];\n\t__u64 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n\t__u32 flags;\n\t__u64 reserved[11];\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct cgroup_subsys;\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n};\n\nstruct blkcg_policy_data;\n\nstruct blkcg {\n\tstruct cgroup_subsys_state css;\n\tspinlock_t lock;\n\trefcount_t online_pin;\n\tatomic_t congestion_count;\n\tstruct xarray blkg_tree;\n\tstruct blkcg_gq *blkg_hint;\n\tstruct hlist_head blkg_list;\n\tstruct blkcg_policy_data *cpd[6];\n\tstruct list_head all_blkcgs_node;\n\tstruct llist_head *lhead;\n};\n\nstruct blkg_iostat {\n\tu64 bytes[3];\n\tu64 ios[3];\n};\n\nstruct blkg_iostat_set {\n\tstruct u64_stats_sync sync;\n\tstruct blkcg_gq *blkg;\n\tstruct llist_node lnode;\n\tint lqueued;\n\tstruct blkg_iostat cur;\n\tstruct blkg_iostat last;\n};\n\nstruct blkg_policy_data;\n\nstruct blkcg_gq {\n\tstruct request_queue *q;\n\tstruct list_head q_node;\n\tstruct hlist_node blkcg_node;\n\tstruct blkcg *blkcg;\n\tstruct blkcg_gq *parent;\n\tstruct percpu_ref refcnt;\n\tbool online;\n\tstruct blkg_iostat_set *iostat_cpu;\n\tstruct blkg_iostat_set iostat;\n\tstruct blkg_policy_data *pd[6];\n\tunion {\n\t\tstruct work_struct async_bio_work;\n\t\tstruct work_struct free_work;\n\t};\n\tatomic_t use_delay;\n\tatomic64_t delay_nsec;\n\tatomic64_t delay_start;\n\tu64 last_delay;\n\tint last_use;\n\tstruct callback_head callback_head;\n};\n\ntypedef struct blkcg_policy_data *blkcg_pol_alloc_cpd_fn(gfp_t);\n\ntypedef void blkcg_pol_free_cpd_fn(struct blkcg_policy_data *);\n\ntypedef struct blkg_policy_data *blkcg_pol_alloc_pd_fn(struct gendisk *, struct blkcg *, gfp_t);\n\ntypedef void blkcg_pol_init_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_online_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_offline_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_free_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_reset_pd_stats_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_stat_pd_fn(struct blkg_policy_data *, struct seq_file *);\n\nstruct cftype;\n\nstruct blkcg_policy {\n\tint plid;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tblkcg_pol_alloc_cpd_fn *cpd_alloc_fn;\n\tblkcg_pol_free_cpd_fn *cpd_free_fn;\n\tblkcg_pol_alloc_pd_fn *pd_alloc_fn;\n\tblkcg_pol_init_pd_fn *pd_init_fn;\n\tblkcg_pol_online_pd_fn *pd_online_fn;\n\tblkcg_pol_offline_pd_fn *pd_offline_fn;\n\tblkcg_pol_free_pd_fn *pd_free_fn;\n\tblkcg_pol_reset_pd_stats_fn *pd_reset_stats_fn;\n\tblkcg_pol_stat_pd_fn *pd_stat_fn;\n};\n\nstruct blkcg_policy_data {\n\tstruct blkcg *blkcg;\n\tint plid;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bio bio;\n\tlong: 64;\n};\n\nstruct blkg_conf_ctx {\n\tchar *input;\n\tchar *body;\n\tstruct block_device *bdev;\n\tstruct blkcg_gq *blkg;\n};\n\nstruct blkg_policy_data {\n\tstruct blkcg_gq *blkg;\n\tint plid;\n\tbool online;\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct mem_zone_bm_rtree;\n\nstruct rtree_node;\n\nstruct bm_position {\n\tstruct mem_zone_bm_rtree *zone;\n\tstruct rtree_node *node;\n\tlong unsigned int node_pfn;\n\tlong unsigned int cur_pfn;\n\tint node_bit;\n};\n\nstruct bmp_header {\n\tu16 id;\n\tu32 size;\n} __attribute__((packed));\n\nstruct drm_object_properties;\n\nstruct drm_mode_object {\n\tuint32_t id;\n\tuint32_t type;\n\tstruct drm_object_properties *properties;\n\tstruct kref refcount;\n\tvoid (*free_cb)(struct kref *);\n};\n\nstruct drm_object_properties {\n\tint count;\n\tstruct drm_property *properties[64];\n\tuint64_t values[64];\n};\n\nstruct kmsg_dump_detail;\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct drm_framebuffer;\n\nstruct drm_plane_funcs;\n\nstruct drm_plane_helper_funcs;\n\nstruct drm_plane {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tuint32_t possible_crtcs;\n\tuint32_t *format_types;\n\tunsigned int format_count;\n\tbool format_default;\n\tuint64_t *modifiers;\n\tunsigned int modifier_count;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct drm_framebuffer *old_fb;\n\tconst struct drm_plane_funcs *funcs;\n\tstruct drm_object_properties properties;\n\tenum drm_plane_type type;\n\tunsigned int index;\n\tconst struct drm_plane_helper_funcs *helper_private;\n\tstruct drm_plane_state *state;\n\tstruct drm_property *alpha_property;\n\tstruct drm_property *zpos_property;\n\tstruct drm_property *rotation_property;\n\tstruct drm_property *blend_mode_property;\n\tstruct drm_property *color_encoding_property;\n\tstruct drm_property *color_range_property;\n\tstruct drm_property *color_pipeline_property;\n\tstruct drm_property *scaling_filter_property;\n\tstruct drm_property *hotspot_x_property;\n\tstruct drm_property *hotspot_y_property;\n\tstruct kmsg_dumper kmsg_panic;\n};\n\nstruct drm_display_mode {\n\tint clock;\n\tu16 hdisplay;\n\tu16 hsync_start;\n\tu16 hsync_end;\n\tu16 htotal;\n\tu16 hskew;\n\tu16 vdisplay;\n\tu16 vsync_start;\n\tu16 vsync_end;\n\tu16 vtotal;\n\tu16 vscan;\n\tu32 flags;\n\tint crtc_clock;\n\tu16 crtc_hdisplay;\n\tu16 crtc_hblank_start;\n\tu16 crtc_hblank_end;\n\tu16 crtc_hsync_start;\n\tu16 crtc_hsync_end;\n\tu16 crtc_htotal;\n\tu16 crtc_hskew;\n\tu16 crtc_vdisplay;\n\tu16 crtc_vblank_start;\n\tu16 crtc_vblank_end;\n\tu16 crtc_vsync_start;\n\tu16 crtc_vsync_end;\n\tu16 crtc_vtotal;\n\tu16 width_mm;\n\tu16 height_mm;\n\tu8 type;\n\tbool expose_to_userspace;\n\tstruct list_head head;\n\tchar name[32];\n\tenum drm_mode_status status;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n};\n\nstruct drm_crtc_crc_entry;\n\nstruct drm_crtc_crc {\n\tspinlock_t lock;\n\tconst char *source;\n\tbool opened;\n\tbool overflow;\n\tstruct drm_crtc_crc_entry *entries;\n\tint head;\n\tint tail;\n\tsize_t values_cnt;\n\twait_queue_head_t wq;\n};\n\nstruct drm_crtc_funcs;\n\nstruct drm_crtc_helper_funcs;\n\nstruct drm_self_refresh_data;\n\nstruct drm_crtc {\n\tstruct drm_device *dev;\n\tstruct device_node *port;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tstruct drm_plane *primary;\n\tstruct drm_plane *cursor;\n\tunsigned int index;\n\tint cursor_x;\n\tint cursor_y;\n\tbool enabled;\n\tstruct drm_display_mode mode;\n\tstruct drm_display_mode hwmode;\n\tint x;\n\tint y;\n\tconst struct drm_crtc_funcs *funcs;\n\tuint32_t gamma_size;\n\tuint16_t *gamma_store;\n\tconst struct drm_crtc_helper_funcs *helper_private;\n\tstruct drm_object_properties properties;\n\tstruct drm_property *scaling_filter_property;\n\tstruct drm_property *sharpness_strength_property;\n\tstruct drm_crtc_state *state;\n\tstruct list_head commit_list;\n\tspinlock_t commit_lock;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_crtc_crc crc;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n\tstruct drm_self_refresh_data *self_refresh_data;\n};\n\nstruct drm_encoder_funcs;\n\nstruct drm_encoder_helper_funcs;\n\nstruct drm_encoder {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tint encoder_type;\n\tunsigned int index;\n\tuint32_t possible_crtcs;\n\tuint32_t possible_clones;\n\tstruct drm_crtc *crtc;\n\tstruct list_head bridge_chain;\n\tconst struct drm_encoder_funcs *funcs;\n\tconst struct drm_encoder_helper_funcs *helper_private;\n\tstruct dentry *debugfs_entry;\n};\n\nstruct drm_scrambling {\n\tbool supported;\n\tbool low_rates;\n};\n\nstruct drm_scdc {\n\tbool supported;\n\tbool read_request;\n\tstruct drm_scrambling scrambling;\n};\n\nstruct drm_hdmi_dsc_cap {\n\tbool v_1p2;\n\tbool native_420;\n\tbool all_bpp;\n\tu8 bpc_supported;\n\tu8 max_slices;\n\tint clk_per_slice;\n\tu8 max_lanes;\n\tu8 max_frl_rate_per_lane;\n\tu8 total_chunk_kbytes;\n};\n\nstruct drm_hdmi_info {\n\tstruct drm_scdc scdc;\n\tlong unsigned int y420_vdb_modes[4];\n\tlong unsigned int y420_cmdb_modes[4];\n\tu8 y420_dc_modes;\n\tu8 max_frl_rate_per_lane;\n\tu8 max_lanes;\n\tstruct drm_hdmi_dsc_cap dsc_cap;\n};\n\nstruct hdr_static_metadata {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\t__u16 max_cll;\n\t__u16 max_fall;\n\t__u16 min_cll;\n};\n\nstruct hdr_sink_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_static_metadata hdmi_type1;\n\t};\n};\n\nstruct drm_monitor_range_info {\n\tu16 min_vfreq;\n\tu16 max_vfreq;\n};\n\nstruct drm_luminance_range_info {\n\tu32 min_luminance;\n\tu32 max_luminance;\n};\n\nstruct drm_display_info {\n\tunsigned int width_mm;\n\tunsigned int height_mm;\n\tunsigned int bpc;\n\tenum subpixel_order subpixel_order;\n\tint panel_orientation;\n\tu32 color_formats;\n\tconst u32 *bus_formats;\n\tunsigned int num_bus_formats;\n\tu32 bus_flags;\n\tint max_tmds_clock;\n\tbool dvi_dual;\n\tbool is_hdmi;\n\tbool has_audio;\n\tbool has_hdmi_infoframe;\n\tbool rgb_quant_range_selectable;\n\tu8 edid_hdmi_rgb444_dc_modes;\n\tu8 edid_hdmi_ycbcr444_dc_modes;\n\tu8 cea_rev;\n\tstruct drm_hdmi_info hdmi;\n\tstruct hdr_sink_metadata hdr_sink_metadata;\n\tbool non_desktop;\n\tstruct drm_monitor_range_info monitor_range;\n\tstruct drm_luminance_range_info luminance_range;\n\tu8 mso_stream_count;\n\tu8 mso_pixel_overlap;\n\tu32 max_dsc_bpp;\n\tu8 *vics;\n\tint vics_len;\n\tu32 quirks;\n\tu16 source_physical_address;\n};\n\nstruct drm_privacy_screen;\n\nstruct drm_connector_tv_margins {\n\tunsigned int bottom;\n\tunsigned int left;\n\tunsigned int right;\n\tunsigned int top;\n};\n\nstruct drm_cmdline_mode {\n\tchar name[32];\n\tbool specified;\n\tbool refresh_specified;\n\tbool bpp_specified;\n\tunsigned int pixel_clock;\n\tint xres;\n\tint yres;\n\tint bpp;\n\tint refresh;\n\tbool rb;\n\tbool interlace;\n\tbool cvt;\n\tbool margins;\n\tenum drm_connector_force force;\n\tunsigned int rotation_reflection;\n\tenum drm_panel_orientation panel_orientation;\n\tstruct drm_connector_tv_margins tv_margins;\n\tenum drm_connector_tv_mode tv_mode;\n\tbool tv_mode_specified;\n};\n\nstruct hdmi_any_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n};\n\nstruct hdmi_avi_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tbool itc;\n\tunsigned char pixel_repeat;\n\tenum hdmi_colorspace colorspace;\n\tenum hdmi_scan_mode scan_mode;\n\tenum hdmi_colorimetry colorimetry;\n\tenum hdmi_picture_aspect picture_aspect;\n\tenum hdmi_active_aspect active_aspect;\n\tenum hdmi_extended_colorimetry extended_colorimetry;\n\tenum hdmi_quantization_range quantization_range;\n\tenum hdmi_nups nups;\n\tunsigned char video_code;\n\tenum hdmi_ycc_quantization_range ycc_quantization_range;\n\tenum hdmi_content_type content_type;\n\tshort unsigned int top_bar;\n\tshort unsigned int bottom_bar;\n\tshort unsigned int left_bar;\n\tshort unsigned int right_bar;\n};\n\nstruct hdmi_spd_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tchar vendor[8];\n\tchar product[16];\n\tenum hdmi_spd_sdi sdi;\n};\n\nstruct hdmi_vendor_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned int oui;\n\tu8 vic;\n\tenum hdmi_3d_structure s3d_struct;\n\tunsigned int s3d_ext_data;\n};\n\nunion hdmi_vendor_any_infoframe {\n\tstruct {\n\t\tenum hdmi_infoframe_type type;\n\t\tunsigned char version;\n\t\tunsigned char length;\n\t\tunsigned int oui;\n\t} any;\n\tstruct hdmi_vendor_infoframe hdmi;\n};\n\nstruct hdmi_audio_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned char channels;\n\tenum hdmi_audio_coding_type coding_type;\n\tenum hdmi_audio_sample_size sample_size;\n\tenum hdmi_audio_sample_frequency sample_frequency;\n\tenum hdmi_audio_coding_type_ext coding_type_ext;\n\tunsigned char channel_allocation;\n\tunsigned char level_shift_value;\n\tbool downmix_inhibit;\n};\n\nstruct hdmi_drm_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_eotf eotf;\n\tenum hdmi_metadata_type metadata_type;\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} white_point;\n\tu16 max_display_mastering_luminance;\n\tu16 min_display_mastering_luminance;\n\tu16 max_cll;\n\tu16 max_fall;\n};\n\nunion hdmi_infoframe {\n\tstruct hdmi_any_infoframe any;\n\tstruct hdmi_avi_infoframe avi;\n\tstruct hdmi_spd_infoframe spd;\n\tunion hdmi_vendor_any_infoframe vendor;\n\tstruct hdmi_audio_infoframe audio;\n\tstruct hdmi_drm_infoframe drm;\n};\n\nstruct drm_connector_hdmi_infoframe {\n\tunion hdmi_infoframe data;\n\tbool set;\n};\n\nstruct drm_connector_hdmi_funcs;\n\nstruct drm_connector_hdmi {\n\tunsigned char vendor[8];\n\tunsigned char product[16];\n\tlong unsigned int supported_formats;\n\tconst struct drm_connector_hdmi_funcs *funcs;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct drm_connector_hdmi_infoframe audio;\n\t} infoframes;\n};\n\nstruct drm_connector_hdmi_audio_funcs;\n\nstruct platform_device;\n\nstruct drm_connector_hdmi_audio {\n\tconst struct drm_connector_hdmi_audio_funcs *funcs;\n\tstruct platform_device *codec_pdev;\n\tstruct mutex lock;\n\tvoid (*plugged_cb)(struct device *, bool);\n\tstruct device *plugged_cb_dev;\n\tbool last_state;\n\tint dai_port;\n};\n\nstruct drm_connector_cec_funcs;\n\nstruct drm_connector_cec {\n\tstruct mutex mutex;\n\tconst struct drm_connector_cec_funcs *funcs;\n\tvoid *data;\n};\n\nstruct drm_connector_funcs;\n\nstruct drm_property_blob;\n\nstruct drm_connector_helper_funcs;\n\nstruct drm_edid;\n\nstruct i2c_adapter;\n\nstruct drm_tile_group;\n\nstruct drm_connector {\n\tstruct drm_device *dev;\n\tstruct device *kdev;\n\tstruct device_attribute *attr;\n\tstruct fwnode_handle *fwnode;\n\tstruct list_head head;\n\tstruct list_head global_connector_list_entry;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tstruct mutex mutex;\n\tunsigned int index;\n\tint connector_type;\n\tint connector_type_id;\n\tbool interlace_allowed;\n\tbool doublescan_allowed;\n\tbool stereo_allowed;\n\tbool ycbcr_420_allowed;\n\tenum drm_connector_registration_state registration_state;\n\tstruct list_head modes;\n\tenum drm_connector_status status;\n\tstruct list_head probed_modes;\n\tstruct drm_display_info display_info;\n\tconst struct drm_connector_funcs *funcs;\n\tstruct drm_property_blob *edid_blob_ptr;\n\tstruct drm_object_properties properties;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *vrr_capable_property;\n\tstruct drm_property *colorspace_property;\n\tstruct drm_property_blob *path_blob_ptr;\n\tunsigned int max_bpc;\n\tstruct drm_property *max_bpc_property;\n\tstruct drm_privacy_screen *privacy_screen;\n\tstruct notifier_block privacy_screen_notifier;\n\tstruct drm_property *privacy_screen_sw_state_property;\n\tstruct drm_property *privacy_screen_hw_state_property;\n\tstruct drm_property *broadcast_rgb_property;\n\tuint8_t polled;\n\tint dpms;\n\tconst struct drm_connector_helper_funcs *helper_private;\n\tstruct drm_cmdline_mode cmdline_mode;\n\tenum drm_connector_force force;\n\tconst struct drm_edid *edid_override;\n\tstruct mutex edid_override_mutex;\n\tu64 epoch_counter;\n\tu32 possible_encoders;\n\tstruct drm_encoder *encoder;\n\tuint8_t eld[128];\n\tstruct mutex eld_mutex;\n\tbool latency_present[2];\n\tint video_latency[2];\n\tint audio_latency[2];\n\tstruct i2c_adapter *ddc;\n\tint null_edid_counter;\n\tunsigned int bad_edid_counter;\n\tbool edid_corrupt;\n\tu8 real_edid_checksum;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_connector_state *state;\n\tstruct drm_property_blob *tile_blob_ptr;\n\tbool has_tile;\n\tstruct drm_tile_group *tile_group;\n\tbool tile_is_single_monitor;\n\tuint8_t num_h_tile;\n\tuint8_t num_v_tile;\n\tuint8_t tile_h_loc;\n\tuint8_t tile_v_loc;\n\tuint16_t tile_h_size;\n\tuint16_t tile_v_size;\n\tstruct llist_node free_node;\n\tstruct drm_connector_hdmi hdmi;\n\tstruct drm_connector_hdmi_audio hdmi_audio;\n\tstruct drm_connector_cec cec;\n};\n\nstruct bochs_device {\n\tstruct drm_device dev;\n\tvoid *mmio;\n\tint ioports;\n\tvoid *fb_map;\n\tlong unsigned int fb_base;\n\tlong unsigned int fb_size;\n\tlong unsigned int qext_size;\n\tu16 xres;\n\tu16 yres;\n\tu16 yres_virtual;\n\tu32 stride;\n\tu32 bpp;\n\tstruct drm_plane primary_plane;\n\tstruct drm_crtc crtc;\n\tstruct drm_encoder encoder;\n\tstruct drm_connector connector;\n};\n\nstruct boot_e820_entry {\n\t__u64 addr;\n\t__u64 size;\n\t__u32 type;\n} __attribute__((packed));\n\nstruct screen_info {\n\t__u8 orig_x;\n\t__u8 orig_y;\n\t__u16 ext_mem_k;\n\t__u16 orig_video_page;\n\t__u8 orig_video_mode;\n\t__u8 orig_video_cols;\n\t__u8 flags;\n\t__u8 unused2;\n\t__u16 orig_video_ega_bx;\n\t__u16 unused3;\n\t__u8 orig_video_lines;\n\t__u8 orig_video_isVGA;\n\t__u16 orig_video_points;\n\t__u16 lfb_width;\n\t__u16 lfb_height;\n\t__u16 lfb_depth;\n\t__u32 lfb_base;\n\t__u32 lfb_size;\n\t__u16 cl_magic;\n\t__u16 cl_offset;\n\t__u16 lfb_linelength;\n\t__u8 red_size;\n\t__u8 red_pos;\n\t__u8 green_size;\n\t__u8 green_pos;\n\t__u8 blue_size;\n\t__u8 blue_pos;\n\t__u8 rsvd_size;\n\t__u8 rsvd_pos;\n\t__u16 vesapm_seg;\n\t__u16 vesapm_off;\n\t__u16 pages;\n\t__u16 vesa_attributes;\n\t__u32 capabilities;\n\t__u32 ext_lfb_base;\n\t__u8 _reserved[2];\n} __attribute__((packed));\n\nstruct ist_info {\n\t__u32 signature;\n\t__u32 command;\n\t__u32 event;\n\t__u32 perf_level;\n};\n\nstruct sys_desc_table {\n\t__u16 length;\n\t__u8 table[14];\n};\n\nstruct olpc_ofw_header {\n\t__u32 ofw_magic;\n\t__u32 ofw_version;\n\t__u32 cif_handler;\n\t__u32 irq_desc_table;\n};\n\nstruct edid_info {\n\tunsigned char dummy[128];\n};\n\nstruct efi_info {\n\t__u32 efi_loader_signature;\n\t__u32 efi_systab;\n\t__u32 efi_memdesc_size;\n\t__u32 efi_memdesc_version;\n\t__u32 efi_memmap;\n\t__u32 efi_memmap_size;\n\t__u32 efi_systab_hi;\n\t__u32 efi_memmap_hi;\n};\n\nstruct setup_header {\n\t__u8 setup_sects;\n\t__u16 root_flags;\n\t__u32 syssize;\n\t__u16 ram_size;\n\t__u16 vid_mode;\n\t__u16 root_dev;\n\t__u16 boot_flag;\n\t__u16 jump;\n\t__u32 header;\n\t__u16 version;\n\t__u32 realmode_swtch;\n\t__u16 start_sys_seg;\n\t__u16 kernel_version;\n\t__u8 type_of_loader;\n\t__u8 loadflags;\n\t__u16 setup_move_size;\n\t__u32 code32_start;\n\t__u32 ramdisk_image;\n\t__u32 ramdisk_size;\n\t__u32 bootsect_kludge;\n\t__u16 heap_end_ptr;\n\t__u8 ext_loader_ver;\n\t__u8 ext_loader_type;\n\t__u32 cmd_line_ptr;\n\t__u32 initrd_addr_max;\n\t__u32 kernel_alignment;\n\t__u8 relocatable_kernel;\n\t__u8 min_alignment;\n\t__u16 xloadflags;\n\t__u32 cmdline_size;\n\t__u32 hardware_subarch;\n\t__u64 hardware_subarch_data;\n\t__u32 payload_offset;\n\t__u32 payload_length;\n\t__u64 setup_data;\n\t__u64 pref_address;\n\t__u32 init_size;\n\t__u32 handover_offset;\n\t__u32 kernel_info_offset;\n} __attribute__((packed));\n\nstruct edd_device_params {\n\t__u16 length;\n\t__u16 info_flags;\n\t__u32 num_default_cylinders;\n\t__u32 num_default_heads;\n\t__u32 sectors_per_track;\n\t__u64 number_of_sectors;\n\t__u16 bytes_per_sector;\n\t__u32 dpte_ptr;\n\t__u16 key;\n\t__u8 device_path_info_length;\n\t__u8 reserved2;\n\t__u16 reserved3;\n\t__u8 host_bus_type[4];\n\t__u8 interface_type[8];\n\tunion {\n\t\tstruct {\n\t\t\t__u16 base_address;\n\t\t\t__u16 reserved1;\n\t\t\t__u32 reserved2;\n\t\t} isa;\n\t\tstruct {\n\t\t\t__u8 bus;\n\t\t\t__u8 slot;\n\t\t\t__u8 function;\n\t\t\t__u8 channel;\n\t\t\t__u32 reserved;\n\t\t} pci;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} ibnd;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} xprs;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} htpt;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} unknown;\n\t} interface_path;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 reserved1;\n\t\t\t__u16 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} ata;\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 lun;\n\t\t\t__u8 reserved1;\n\t\t\t__u8 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} atapi;\n\t\tstruct {\n\t\t\t__u16 id;\n\t\t\t__u64 lun;\n\t\t\t__u16 reserved1;\n\t\t\t__u32 reserved2;\n\t\t} __attribute__((packed)) scsi;\n\t\tstruct {\n\t\t\t__u64 serial_number;\n\t\t\t__u64 reserved;\n\t\t} usb;\n\t\tstruct {\n\t\t\t__u64 eui;\n\t\t\t__u64 reserved;\n\t\t} i1394;\n\t\tstruct {\n\t\t\t__u64 wwid;\n\t\t\t__u64 lun;\n\t\t} fibre;\n\t\tstruct {\n\t\t\t__u64 identity_tag;\n\t\t\t__u64 reserved;\n\t\t} i2o;\n\t\tstruct {\n\t\t\t__u32 array_number;\n\t\t\t__u32 reserved1;\n\t\t\t__u64 reserved2;\n\t\t} raid;\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 reserved1;\n\t\t\t__u16 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} sata;\n\t\tstruct {\n\t\t\t__u64 reserved1;\n\t\t\t__u64 reserved2;\n\t\t} unknown;\n\t} device_path;\n\t__u8 reserved4;\n\t__u8 checksum;\n} __attribute__((packed));\n\nstruct edd_info {\n\t__u8 device;\n\t__u8 version;\n\t__u16 interface_support;\n\t__u16 legacy_max_cylinder;\n\t__u8 legacy_max_head;\n\t__u8 legacy_sectors_per_track;\n\tstruct edd_device_params params;\n};\n\nstruct boot_params {\n\tstruct screen_info screen_info;\n\tstruct apm_bios_info apm_bios_info;\n\t__u8 _pad2[4];\n\t__u64 tboot_addr;\n\tstruct ist_info ist_info;\n\t__u64 acpi_rsdp_addr;\n\t__u8 _pad3[8];\n\t__u8 hd0_info[16];\n\t__u8 hd1_info[16];\n\tstruct sys_desc_table sys_desc_table;\n\tstruct olpc_ofw_header olpc_ofw_header;\n\t__u32 ext_ramdisk_image;\n\t__u32 ext_ramdisk_size;\n\t__u32 ext_cmd_line_ptr;\n\t__u8 _pad4[112];\n\t__u32 cc_blob_address;\n\tstruct edid_info edid_info;\n\tstruct efi_info efi_info;\n\t__u32 alt_mem_k;\n\t__u32 scratch;\n\t__u8 e820_entries;\n\t__u8 eddbuf_entries;\n\t__u8 edd_mbr_sig_buf_entries;\n\t__u8 kbd_status;\n\t__u8 secure_boot;\n\t__u8 _pad5[2];\n\t__u8 sentinel;\n\t__u8 _pad6[1];\n\tstruct setup_header hdr;\n\t__u8 _pad7[36];\n\t__u32 edd_mbr_sig_buffer[16];\n\tstruct boot_e820_entry e820_table[128];\n\t__u8 _pad8[48];\n\tstruct edd_info eddbuf[6];\n\t__u8 _pad9[276];\n};\n\nstruct boot_params_to_save {\n\tunsigned int start;\n\tunsigned int len;\n};\n\nstruct boot_triggers {\n\tconst char *event;\n\tchar *trigger;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct bp_slots_histogram {\n\tatomic_t count[4];\n};\n\nstruct bp_cpuinfo {\n\tunsigned int cpu_pinned;\n\tstruct bp_slots_histogram tsk_pinned;\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n};\n\nstruct range_tree {\n\tstruct rb_root_cached it_root;\n\tstruct rb_root_cached range_size_root;\n};\n\ntypedef struct qspinlock rqspinlock_t;\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct vm_struct;\n\nstruct bpf_arena {\n\tstruct bpf_map map;\n\tu64 user_vm_start;\n\tu64 user_vm_end;\n\tstruct vm_struct *kern_vm;\n\tstruct range_tree rt;\n\trqspinlock_t spinlock;\n\tstruct list_head vma_list;\n\tstruct mutex lock;\n\tstruct irq_work free_irq;\n\tstruct work_struct free_work;\n\tstruct llist_head free_spans;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct bpf_prog;\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 0;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_cgroup_dev_ctx {\n\t__u32 access_type;\n\t__u32 major;\n\t__u32 minor;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n};\n\nstruct bpf_cgroup_link {\n\tstruct bpf_link link;\n\tstruct cgroup *cgroup;\n};\n\nstruct bpf_cgroup_storage_key {\n\t__u64 cgroup_inode_id;\n\t__u32 attach_type;\n};\n\nstruct bpf_storage_buffer;\n\nstruct bpf_cgroup_storage_map;\n\nstruct bpf_cgroup_storage {\n\tunion {\n\t\tstruct bpf_storage_buffer *buf;\n\t\tvoid *percpu_buf;\n\t};\n\tstruct bpf_cgroup_storage_map *map;\n\tstruct bpf_cgroup_storage_key key;\n\tstruct list_head list_map;\n\tstruct list_head list_cg;\n\tstruct rb_node node;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_cgroup_storage_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tstruct rb_root root;\n\tstruct list_head list;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct sock;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_rxq_info;\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t\tu64 frame_sz_flags_init;\n\t};\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct sock_cgroup_data {\n\tstruct cgroup *cgroup;\n\tu32 classid;\n\tu16 prioidx;\n};\n\nstruct dst_entry;\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct socket;\n\nstruct pid;\n\nstruct sock_reuseport;\n\nstruct bpf_local_storage;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tnetdev_features_t sk_route_caps;\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tktime_t sk_stamp;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n\tstruct module *sk_owner;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\ntypedef struct pt_regs bpf_user_pt_regs_t;\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_sample_data;\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nstruct bpf_sysctl {\n\t__u32 write;\n\t__u32 file_pos;\n};\n\nstruct ctl_table_header;\n\nstruct ctl_table;\n\nstruct bpf_sysctl_kern {\n\tstruct ctl_table_header *head;\n\tconst struct ctl_table *table;\n\tvoid *cur_val;\n\tsize_t cur_len;\n\tvoid *new_val;\n\tsize_t new_len;\n\tint new_updated;\n\tint write;\n\tloff_t *ppos;\n\tu64 tmp_reg;\n};\n\nstruct bpf_sockopt {\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *optval;\n\t};\n\tunion {\n\t\tvoid *optval_end;\n\t};\n\t__s32 level;\n\t__s32 optname;\n\t__s32 optlen;\n\t__s32 retval;\n};\n\nstruct bpf_sockopt_kern {\n\tstruct sock *sk;\n\tu8 *optval;\n\tu8 *optval_end;\n\ts32 level;\n\ts32 optname;\n\ts32 optlen;\n\tstruct task_struct *current_task;\n\tu64 tmp_reg;\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_CGROUP_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_CGROUP_SKB_kern;\n\tstruct bpf_sock BPF_PROG_TYPE_CGROUP_SOCK_prog;\n\tstruct sock BPF_PROG_TYPE_CGROUP_SOCK_kern;\n\tstruct bpf_sock_addr BPF_PROG_TYPE_CGROUP_SOCK_ADDR_prog;\n\tstruct bpf_sock_addr_kern BPF_PROG_TYPE_CGROUP_SOCK_ADDR_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_prog;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_kern;\n\tstruct bpf_sysctl BPF_PROG_TYPE_CGROUP_SYSCTL_prog;\n\tstruct bpf_sysctl_kern BPF_PROG_TYPE_CGROUP_SYSCTL_kern;\n\tstruct bpf_sockopt BPF_PROG_TYPE_CGROUP_SOCKOPT_prog;\n\tstruct bpf_sockopt_kern BPF_PROG_TYPE_CGROUP_SOCKOPT_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct static_call_key;\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n\tstruct static_call_key *sc_key;\n\tvoid *sc_tramp;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n};\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n};\n\nstruct obj_cgroup;\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 0;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct dma_buf;\n\nstruct bpf_iter__dmabuf {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct dma_buf *dmabuf;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 0;\n\tint bucket;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n};\n\nstruct bpf_iter_dmabuf {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_dmabuf_kern {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 0;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n};\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tatomic64_t revision;\n\tu32 count;\n};\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_perf_link {\n\tstruct bpf_link link;\n\tstruct file *perf_file;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_list {\n\tstruct hlist_node node;\n\tstruct bpf_prog *prog;\n\tstruct bpf_cgroup_link *link;\n\tstruct bpf_cgroup_storage *storage[2];\n\tu32 flags;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct tracepoint;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 64;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\trqspinlock_t spinlock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t busy;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int consumer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct bpf_session_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tbool is_return;\n\tvoid *data;\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_sockopt_buf {\n\tu8 data[32];\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nstruct stack_map_bucket;\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_storage_buffer {\n\tstruct callback_head rcu;\n\tchar data[0];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_dummy_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_ext_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n};\n\nunion perf_sample_weight {\n\t__u64 full;\n\tstruct {\n\t\t__u32 var1_dw;\n\t\t__u16 var2_w;\n\t\t__u16 var3_w;\n\t};\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_op: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_blk: 3;\n\t\t__u64 mem_hops: 3;\n\t\t__u64 mem_region: 5;\n\t\t__u64 mem_rsvd: 13;\n\t};\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n};\n\nstruct perf_callchain_entry;\n\nstruct perf_raw_record;\n\nstruct perf_branch_stack;\n\nstruct perf_sample_data {\n\tu64 sample_flags;\n\tu64 period;\n\tu64 dyn_size;\n\tu64 type;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tu64 ip;\n\tstruct perf_callchain_entry *callchain;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 *br_stack_cntr;\n\tunion perf_sample_weight weight;\n\tunion perf_mem_data_src data_src;\n\tu64 txn;\n\tstruct perf_regs regs_user;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 stream_id;\n\tu64 cgroup;\n\tu64 addr;\n\tu64 phys_addr;\n\tu64 data_page_size;\n\tu64 code_page_size;\n\tu64 aux_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[38];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *, __u64 *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *, __u64 *);\n\tbool (*filter)(struct uprobe_consumer *, struct mm_struct *);\n\tstruct list_head cons_node;\n\t__u64 id;\n};\n\nstruct bpf_uprobe_multi_link;\n\nstruct uprobe;\n\nstruct bpf_uprobe {\n\tstruct bpf_uprobe_multi_link *link;\n\tloff_t offset;\n\tlong unsigned int ref_ctr_offset;\n\tu64 cookie;\n\tstruct uprobe *uprobe;\n\tstruct uprobe_consumer consumer;\n\tbool session;\n};\n\nstruct bpf_uprobe_multi_link {\n\tstruct path path;\n\tstruct bpf_link link;\n\tu32 cnt;\n\tstruct bpf_uprobe *uprobes;\n\tstruct task_struct *task;\n};\n\nstruct bpf_uprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tlong unsigned int entry_ip;\n\tstruct bpf_uprobe *uprobe;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct branch_entry {\n\tunion {\n\t\tstruct {\n\t\t\tu64 ip: 58;\n\t\t\tu64 ip_sign_ext: 5;\n\t\t\tu64 mispredict: 1;\n\t\t} split;\n\t\tu64 full;\n\t} from;\n\tunion {\n\t\tstruct {\n\t\t\tu64 ip: 58;\n\t\t\tu64 ip_sign_ext: 3;\n\t\t\tu64 reserved: 1;\n\t\t\tu64 spec: 1;\n\t\t\tu64 valid: 1;\n\t\t} split;\n\t\tu64 full;\n\t} to;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct bsd_acct_struct {\n\tstruct fs_pin pin;\n\tatomic_long_t count;\n\tstruct callback_head rcu;\n\tstruct mutex lock;\n\tbool active;\n\tbool check_space;\n\tlong unsigned int needcheck;\n\tstruct file *file;\n\tstruct pid_namespace *ns;\n\tstruct work_struct work;\n\tstruct completion done;\n\tacct_t ac;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[56];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_anon_stack {\n\tu32 tid;\n\tu32 offset;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_ptr {\n\tvoid *ptr;\n\t__u32 type_id;\n\t__u32 flags;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, struct __va_list_tag *);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct bts_phys {\n\tstruct page *page;\n\tlong unsigned int size;\n\tlong unsigned int offset;\n\tlong unsigned int displacement;\n};\n\nstruct bts_buffer {\n\tsize_t real_size;\n\tunsigned int nr_pages;\n\tunsigned int nr_bufs;\n\tunsigned int cur_buf;\n\tbool snapshot;\n\tlocal_t data_size;\n\tlocal_t head;\n\tlong unsigned int end;\n\tvoid **data_pages;\n\tstruct bts_phys buf[0];\n};\n\nstruct perf_buffer;\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tunion {\n\t\tu64 flags;\n\t\tu64 aux_flags;\n\t\tstruct {\n\t\t\tu64 skip_read: 1;\n\t\t};\n\t};\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct debug_store {\n\tu64 bts_buffer_base;\n\tu64 bts_index;\n\tu64 bts_absolute_maximum;\n\tu64 bts_interrupt_threshold;\n\tu64 pebs_buffer_base;\n\tu64 pebs_index;\n\tu64 pebs_absolute_maximum;\n\tu64 pebs_interrupt_threshold;\n\tu64 pebs_event_reset[48];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bts_ctx {\n\tstruct perf_output_handle handle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct debug_store ds_back;\n\tint state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bts_record {\n\tu64 from;\n\tu64 to;\n\tu64 flags;\n};\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct buddy_page_mask {\n\tu32 page_mask;\n\tu8 type;\n\tu8 num_channels;\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n};\n\nstruct buffer_data_read_page {\n\tunsigned int order;\n\tstruct buffer_data_page *data;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tunsigned int order;\n\tu32 id: 30;\n\tu32 range: 1;\n\tstruct buffer_data_page *page;\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct bug_entry {\n\tint bug_addr_disp;\n\tint format_disp;\n\tint file_disp;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct bxt_ddi_buf_trans {\n\tu8 margin;\n\tu8 scale;\n\tu8 enable;\n\tu8 deemphasis;\n};\n\nstruct bxt_dpio_phy_info {\n\tbool dual_channel;\n\tenum dpio_phy rcomp_phy;\n\tint reset_delay;\n\tu32 pwron_mask;\n\tstruct {\n\t\tenum port port;\n\t} channel[2];\n};\n\nstruct bxt_dpll_hw_state {\n\tu32 ebb0;\n\tu32 ebb4;\n\tu32 pll0;\n\tu32 pll1;\n\tu32 pll2;\n\tu32 pll3;\n\tu32 pll6;\n\tu32 pll8;\n\tu32 pll9;\n\tu32 pll10;\n\tu32 pcsdw12;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct cache_map {\n\tu64 start;\n\tu64 end;\n\tu64 flags;\n\tu64 type: 8;\n\tu64 fixed: 1;\n};\n\nstruct intel_iommu;\n\nstruct cache_tag {\n\tstruct list_head node;\n\tenum cache_tag_type type;\n\tstruct intel_iommu *iommu;\n\tstruct device *dev;\n\tu16 domain_id;\n\tioasid_t pasid;\n\tunsigned int users;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nstruct callthunk_sites {\n\ts32 *call_start;\n\ts32 *call_end;\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct cb_id {\n\t__u32 idx;\n\t__u32 val;\n};\n\nstruct cb_kernel {\n\tconst void *data;\n\tu32 size;\n};\n\nstruct crypto_cipher;\n\nstruct cbcmac_tfm_ctx {\n\tstruct crypto_cipher *child;\n};\n\nstruct ccm_instance_ctx {\n\tstruct crypto_skcipher_spawn ctr;\n\tstruct crypto_ahash_spawn mac;\n};\n\nstruct cdrom_msf0 {\n\t__u8 minute;\n\t__u8 second;\n\t__u8 frame;\n};\n\nunion cdrom_addr {\n\tstruct cdrom_msf0 msf;\n\tint lba;\n};\n\nstruct cdrom_device_ops;\n\nstruct cdrom_device_info {\n\tconst struct cdrom_device_ops *ops;\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tvoid *handle;\n\tint mask;\n\tint speed;\n\tint capacity;\n\tunsigned int options: 30;\n\tunsigned int mc_flags: 2;\n\tunsigned int vfs_events;\n\tunsigned int ioctl_events;\n\tint use_count;\n\tchar name[20];\n\t__u8 sanyo_slot: 2;\n\t__u8 keeplocked: 1;\n\t__u8 reserved: 5;\n\tint cdda_method;\n\t__u8 last_sense;\n\t__u8 media_written;\n\tshort unsigned int mmc3_profile;\n\tint mrw_mode_page;\n\tbool opened_for_data;\n\t__s64 last_media_change_ms;\n};\n\nstruct cdrom_multisession;\n\nstruct cdrom_mcn;\n\nstruct packet_command;\n\nstruct cdrom_device_ops {\n\tint (*open)(struct cdrom_device_info *, int);\n\tvoid (*release)(struct cdrom_device_info *);\n\tint (*drive_status)(struct cdrom_device_info *, int);\n\tunsigned int (*check_events)(struct cdrom_device_info *, unsigned int, int);\n\tint (*tray_move)(struct cdrom_device_info *, int);\n\tint (*lock_door)(struct cdrom_device_info *, int);\n\tint (*select_speed)(struct cdrom_device_info *, long unsigned int);\n\tint (*get_last_session)(struct cdrom_device_info *, struct cdrom_multisession *);\n\tint (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);\n\tint (*reset)(struct cdrom_device_info *);\n\tint (*audio_ioctl)(struct cdrom_device_info *, unsigned int, void *);\n\tint (*generic_packet)(struct cdrom_device_info *, struct packet_command *);\n\tint (*read_cdda_bpc)(struct cdrom_device_info *, void *, u32, u32, u8 *);\n\tconst int capability;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct cdrom_mcn {\n\t__u8 medium_catalog_number[14];\n};\n\nstruct cdrom_multisession {\n\tunion cdrom_addr addr;\n\t__u8 xa_flag;\n\t__u8 addr_format;\n};\n\nstruct cdrom_tocentry {\n\t__u8 cdte_track;\n\t__u8 cdte_adr: 4;\n\t__u8 cdte_ctrl: 4;\n\t__u8 cdte_format;\n\tunion cdrom_addr cdte_addr;\n\t__u8 cdte_datamode;\n};\n\nstruct clock_event_device;\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct cea_db {\n\tu8 tag_length;\n\tu8 data[0];\n};\n\nstruct drm_edid_iter {\n\tconst struct drm_edid *drm_edid;\n\tint index;\n};\n\nstruct displayid_iter {\n\tconst struct drm_edid *drm_edid;\n\tconst u8 *section;\n\tint length;\n\tint idx;\n\tint ext_index;\n\tu8 version;\n\tu8 primary_use;\n\tu8 quirks;\n};\n\nstruct cea_db_iter {\n\tstruct drm_edid_iter edid_iter;\n\tstruct displayid_iter displayid_iter;\n\tconst u8 *collection;\n\tint index;\n\tint end;\n};\n\nstruct cea_exception_stacks {\n\tchar DF_stack_guard[4096];\n\tchar DF_stack[8192];\n\tchar NMI_stack_guard[4096];\n\tchar NMI_stack[8192];\n\tchar DB_stack_guard[4096];\n\tchar DB_stack[8192];\n\tchar MCE_stack_guard[4096];\n\tchar MCE_stack[8192];\n\tchar VC_stack_guard[4096];\n\tchar VC_stack[8192];\n\tchar VC2_stack_guard[4096];\n\tchar VC2_stack[8192];\n\tchar IST_top_guard[4096];\n};\n\nstruct cea_sad {\n\tu8 format;\n\tu8 channels;\n\tu8 freq;\n\tu8 byte2;\n};\n\nstruct cec_adapter;\n\nstruct cec_msg;\n\nstruct cec_adap_ops {\n\tint (*adap_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_all_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_pin_enable)(struct cec_adapter *, bool);\n\tint (*adap_log_addr)(struct cec_adapter *, u8);\n\tvoid (*adap_unconfigured)(struct cec_adapter *);\n\tint (*adap_transmit)(struct cec_adapter *, u8, u32, struct cec_msg *);\n\tvoid (*adap_nb_transmit_canceled)(struct cec_adapter *, const struct cec_msg *);\n\tvoid (*adap_status)(struct cec_adapter *, struct seq_file *);\n\tvoid (*adap_free)(struct cec_adapter *);\n\tint (*error_inj_show)(struct cec_adapter *, struct seq_file *);\n\tbool (*error_inj_parse_line)(struct cec_adapter *, char *);\n\tvoid (*configured)(struct cec_adapter *);\n\tint (*received)(struct cec_adapter *, struct cec_msg *);\n};\n\nstruct cec_devnode {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tint minor;\n\tstruct mutex lock;\n\tbool registered;\n\tbool unregistered;\n\tstruct mutex lock_fhs;\n\tstruct list_head fhs;\n};\n\nstruct cec_log_addrs {\n\t__u8 log_addr[4];\n\t__u16 log_addr_mask;\n\t__u8 cec_version;\n\t__u8 num_log_addrs;\n\t__u32 vendor_id;\n\t__u32 flags;\n\tchar osd_name[15];\n\t__u8 primary_device_type[4];\n\t__u8 log_addr_type[4];\n\t__u8 all_device_types[4];\n\t__u8 features[48];\n};\n\nstruct cec_drm_connector_info {\n\t__u32 card_no;\n\t__u32 connector_id;\n};\n\nstruct cec_connector_info {\n\t__u32 type;\n\tunion {\n\t\tstruct cec_drm_connector_info drm;\n\t\t__u32 raw[16];\n\t};\n};\n\nstruct rc_dev;\n\nstruct cec_data;\n\nstruct cec_fh;\n\nstruct cec_adapter {\n\tstruct module *owner;\n\tchar name[32];\n\tstruct cec_devnode devnode;\n\tstruct mutex lock;\n\tstruct rc_dev *rc;\n\tstruct list_head transmit_queue;\n\tunsigned int transmit_queue_sz;\n\tstruct list_head wait_queue;\n\tstruct cec_data *transmitting;\n\tbool transmit_in_progress;\n\tbool transmit_in_progress_aborted;\n\tunsigned int xfer_timeout_ms;\n\tstruct task_struct *kthread_config;\n\tstruct completion config_completion;\n\tstruct task_struct *kthread;\n\twait_queue_head_t kthread_waitq;\n\tconst struct cec_adap_ops *ops;\n\tvoid *priv;\n\tu32 capabilities;\n\tu8 available_log_addrs;\n\tu16 phys_addr;\n\tbool needs_hpd;\n\tbool is_enabled;\n\tbool is_claiming_log_addrs;\n\tbool is_configuring;\n\tbool must_reconfigure;\n\tbool is_configured;\n\tbool cec_pin_is_high;\n\tbool adap_controls_phys_addr;\n\tu8 last_initiator;\n\tu32 monitor_all_cnt;\n\tu32 monitor_pin_cnt;\n\tu32 follower_cnt;\n\tstruct cec_fh *cec_follower;\n\tstruct cec_fh *cec_initiator;\n\tbool passthrough;\n\tstruct cec_log_addrs log_addrs;\n\tstruct cec_connector_info conn_info;\n\tu32 tx_timeout_cnt;\n\tu32 tx_low_drive_cnt;\n\tu32 tx_error_cnt;\n\tu32 tx_arb_lost_cnt;\n\tu32 tx_low_drive_log_cnt;\n\tu32 tx_error_log_cnt;\n\tstruct dentry *cec_dir;\n\tu32 sequence;\n\tchar input_phys[40];\n};\n\nstruct cec_msg {\n\t__u64 tx_ts;\n\t__u64 rx_ts;\n\t__u32 len;\n\t__u32 timeout;\n\t__u32 sequence;\n\t__u32 flags;\n\t__u8 msg[16];\n\t__u8 reply;\n\t__u8 rx_status;\n\t__u8 tx_status;\n\t__u8 tx_arb_lost_cnt;\n\t__u8 tx_nack_cnt;\n\t__u8 tx_low_drive_cnt;\n\t__u8 tx_error_cnt;\n};\n\nstruct cec_data {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tstruct cec_msg msg;\n\tu8 match_len;\n\tu8 match_reply[5];\n\tstruct cec_fh *fh;\n\tstruct delayed_work work;\n\tstruct completion c;\n\tu8 attempts;\n\tbool blocking;\n\tbool completed;\n};\n\nstruct cec_event_state_change {\n\t__u16 phys_addr;\n\t__u16 log_addr_mask;\n\t__u16 have_conn_info;\n};\n\nstruct cec_event_lost_msgs {\n\t__u32 lost_msgs;\n};\n\nstruct cec_event {\n\t__u64 ts;\n\t__u32 event;\n\t__u32 flags;\n\tunion {\n\t\tstruct cec_event_state_change state_change;\n\t\tstruct cec_event_lost_msgs lost_msgs;\n\t\t__u32 raw[16];\n\t};\n};\n\nstruct cec_event_entry {\n\tstruct list_head list;\n\tstruct cec_event ev;\n};\n\nstruct cec_fh {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tu8 mode_initiator;\n\tu8 mode_follower;\n\twait_queue_head_t wait;\n\tstruct mutex lock;\n\tstruct list_head events[8];\n\tu16 queued_events[8];\n\tunsigned int total_queued_events;\n\tstruct cec_event_entry core_events[2];\n\tstruct list_head msgs;\n\tunsigned int queued_msgs;\n};\n\nstruct cfs_bandwidth {};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n};\n\nstruct sched_entity;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tunsigned int sum_shift;\n\tunsigned int forceidle_seq;\n\tu64 zero_vruntime_fi;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 forceidle_sum;\n\tu64 ntime;\n};\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n};\n\nstruct cgroup_bpf {\n\tstruct bpf_prog_array *effective[28];\n\tstruct hlist_head progs[28];\n\tu8 flags[28];\n\tu64 revisions[28];\n\tstruct list_head storages;\n\tstruct bpf_prog_array *inactive;\n\tstruct percpu_ref refcnt;\n\tstruct work_struct release_work;\n};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[0];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[14];\n\tint nr_dying_subsys[14];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[14];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct cgroup_cls_state {\n\tstruct cgroup_subsys_state css;\n\tu32 classid;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 64;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct ch7017_priv {\n\tu8 dummy;\n};\n\nstruct ch7xxx_did_struct {\n\tu8 did;\n\tchar *name;\n};\n\nstruct ch7xxx_id_struct {\n\tu8 vid;\n\tchar *name;\n};\n\nstruct ch7xxx_priv {\n\tbool quiet;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct linked_page;\n\nstruct chain_allocator {\n\tstruct linked_page *chain;\n\tunsigned int used_space;\n\tgfp_t gfp_mask;\n\tint safe_needed;\n};\n\nstruct e820_entry;\n\nstruct change_member {\n\tstruct e820_entry *entry;\n\tu64 addr;\n};\n\nstruct channel_map_table {\n\tunsigned char map;\n\tint spk_mask;\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct check_loop_arg {\n\tstruct qdisc_walker w;\n\tstruct Qdisc *p;\n\tint depth;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct child_device_config {\n\tu16 handle;\n\tu16 device_type;\n\tunion {\n\t\tu8 device_id[10];\n\t\tstruct {\n\t\t\tu8 i2c_speed;\n\t\t\tu8 dp_onboard_redriver_preemph: 3;\n\t\t\tu8 dp_onboard_redriver_vswing: 3;\n\t\t\tu8 dp_onboard_redriver_present: 1;\n\t\t\tu8 reserved0: 1;\n\t\t\tu8 dp_ondock_redriver_preemph: 3;\n\t\t\tu8 dp_ondock_redriver_vswing: 3;\n\t\t\tu8 dp_ondock_redriver_present: 1;\n\t\t\tu8 reserved1: 1;\n\t\t\tu8 hdmi_level_shifter_value: 5;\n\t\t\tu8 hdmi_max_data_rate: 3;\n\t\t\tu16 dtd_buf_ptr;\n\t\t\tu8 edidless_efp: 1;\n\t\t\tu8 compression_enable: 1;\n\t\t\tu8 compression_method_cps: 1;\n\t\t\tu8 ganged_edp: 1;\n\t\t\tu8 lttpr_non_transparent: 1;\n\t\t\tu8 disable_compression_for_ext_disp: 1;\n\t\t\tu8 reserved2: 2;\n\t\t\tu8 compression_structure_index: 4;\n\t\t\tu8 reserved3: 4;\n\t\t\tu8 hdmi_max_frl_rate: 4;\n\t\t\tu8 hdmi_max_frl_rate_valid: 1;\n\t\t\tu8 reserved4: 3;\n\t\t\tu8 reserved5;\n\t\t};\n\t};\n\tu16 addin_offset;\n\tu8 dvo_port;\n\tu8 i2c_pin;\n\tu8 target_addr;\n\tu8 ddc_pin;\n\tu16 edid_ptr;\n\tu8 dvo_cfg;\n\tunion {\n\t\tstruct {\n\t\t\tu8 dvo2_port;\n\t\t\tu8 i2c2_pin;\n\t\t\tu8 target2_addr;\n\t\t\tu8 ddc2_pin;\n\t\t};\n\t\tstruct {\n\t\t\tu8 efp_routed: 1;\n\t\t\tu8 lane_reversal: 1;\n\t\t\tu8 lspcon: 1;\n\t\t\tu8 iboost: 1;\n\t\t\tu8 hpd_invert: 1;\n\t\t\tu8 use_vbt_vswing: 1;\n\t\t\tu8 dp_max_lane_count: 2;\n\t\t\tu8 hdmi_support: 1;\n\t\t\tu8 dp_support: 1;\n\t\t\tu8 tmds_support: 1;\n\t\t\tu8 support_reserved: 5;\n\t\t\tu8 aux_channel;\n\t\t\tu8 dongle_detect;\n\t\t};\n\t};\n\tu8 pipe_cap: 2;\n\tu8 sdvo_stall: 1;\n\tu8 hpd_status: 2;\n\tu8 integrated_encoder: 1;\n\tu8 capabilities_reserved: 2;\n\tu8 dvo_wiring;\n\tunion {\n\t\tu8 dvo2_wiring;\n\t\tu8 mipi_bridge_type;\n\t};\n\tu16 extended_type;\n\tu8 dvo_function;\n\tu8 dp_usb_type_c: 1;\n\tu8 tbt: 1;\n\tu8 dedicated_external: 1;\n\tu8 dyn_port_over_tc: 1;\n\tu8 dp_port_trace_length: 4;\n\tu8 dp_gpio_index;\n\tu16 dp_gpio_pin_num;\n\tu8 dp_iboost_level: 4;\n\tu8 hdmi_iboost_level: 4;\n\tu8 dp_max_link_rate: 3;\n\tu8 dp_max_link_rate_reserved: 5;\n\tu8 efp_index;\n\tu32 edp_data_rate_override: 12;\n\tu32 edp_data_rate_override_reserved: 20;\n} __attribute__((packed));\n\nstruct iolatency_grp;\n\nstruct child_latency_info {\n\tspinlock_t lock;\n\tu64 last_scale_event;\n\tu64 scale_lat;\n\tu64 nr_samples;\n\tstruct iolatency_grp *scale_grp;\n\tatomic_t scale_cookie;\n};\n\nstruct chipset {\n\tu32 vendor;\n\tu32 device;\n\tu32 class;\n\tu32 class_mask;\n\tu32 flags;\n\tvoid (*f)(int, int, int);\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct lock_list;\n\nstruct circular_queue {\n\tstruct lock_list *element[4096];\n\tunsigned int front;\n\tunsigned int rear;\n};\n\nstruct cis_cache_entry {\n\tstruct list_head node;\n\tunsigned int addr;\n\tunsigned int len;\n\tunsigned int attr;\n\tunsigned char cache[0];\n};\n\nstruct cistpl_device_t {\n\tu_char ndev;\n\tstruct {\n\t\tu_char type;\n\t\tu_char wp;\n\t\tu_int speed;\n\t\tu_int size;\n\t} dev[4];\n};\n\ntypedef struct cistpl_device_t cistpl_device_t;\n\nstruct cistpl_checksum_t {\n\tu_short addr;\n\tu_short len;\n\tu_char sum;\n};\n\ntypedef struct cistpl_checksum_t cistpl_checksum_t;\n\nstruct cistpl_longlink_t {\n\tu_int addr;\n};\n\ntypedef struct cistpl_longlink_t cistpl_longlink_t;\n\nstruct cistpl_longlink_mfc_t {\n\tu_char nfn;\n\tstruct {\n\t\tu_char space;\n\t\tu_int addr;\n\t} fn[8];\n};\n\ntypedef struct cistpl_longlink_mfc_t cistpl_longlink_mfc_t;\n\nstruct cistpl_vers_1_t {\n\tu_char major;\n\tu_char minor;\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_vers_1_t cistpl_vers_1_t;\n\nstruct cistpl_altstr_t {\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_altstr_t cistpl_altstr_t;\n\nstruct cistpl_jedec_t {\n\tu_char nid;\n\tstruct {\n\t\tu_char mfr;\n\t\tu_char info;\n\t} id[4];\n};\n\ntypedef struct cistpl_jedec_t cistpl_jedec_t;\n\nstruct cistpl_manfid_t {\n\tu_short manf;\n\tu_short card;\n};\n\ntypedef struct cistpl_manfid_t cistpl_manfid_t;\n\nstruct cistpl_funcid_t {\n\tu_char func;\n\tu_char sysinit;\n};\n\ntypedef struct cistpl_funcid_t cistpl_funcid_t;\n\nstruct cistpl_funce_t {\n\tu_char type;\n\tu_char data[0];\n};\n\ntypedef struct cistpl_funce_t cistpl_funce_t;\n\nstruct cistpl_bar_t {\n\tu_char attr;\n\tu_int size;\n};\n\ntypedef struct cistpl_bar_t cistpl_bar_t;\n\nstruct cistpl_config_t {\n\tu_char last_idx;\n\tu_int base;\n\tu_int rmask[4];\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_config_t cistpl_config_t;\n\nstruct cistpl_power_t {\n\tu_char present;\n\tu_char flags;\n\tu_int param[7];\n};\n\ntypedef struct cistpl_power_t cistpl_power_t;\n\nstruct cistpl_timing_t {\n\tu_int wait;\n\tu_int waitscale;\n\tu_int ready;\n\tu_int rdyscale;\n\tu_int reserved;\n\tu_int rsvscale;\n};\n\ntypedef struct cistpl_timing_t cistpl_timing_t;\n\nstruct cistpl_io_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int base;\n\t\tu_int len;\n\t} win[16];\n};\n\ntypedef struct cistpl_io_t cistpl_io_t;\n\nstruct cistpl_irq_t {\n\tu_int IRQInfo1;\n\tu_int IRQInfo2;\n};\n\ntypedef struct cistpl_irq_t cistpl_irq_t;\n\nstruct cistpl_mem_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int len;\n\t\tu_int card_addr;\n\t\tu_int host_addr;\n\t} win[8];\n};\n\ntypedef struct cistpl_mem_t cistpl_mem_t;\n\nstruct cistpl_cftable_entry_t {\n\tu_char index;\n\tu_short flags;\n\tu_char interface;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tcistpl_timing_t timing;\n\tcistpl_io_t io;\n\tcistpl_irq_t irq;\n\tcistpl_mem_t mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_t cistpl_cftable_entry_t;\n\nstruct cistpl_cftable_entry_cb_t {\n\tu_char index;\n\tu_int flags;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tu_char io;\n\tcistpl_irq_t irq;\n\tu_char mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_cb_t cistpl_cftable_entry_cb_t;\n\nstruct cistpl_device_geo_t {\n\tu_char ngeo;\n\tstruct {\n\t\tu_char buswidth;\n\t\tu_int erase_block;\n\t\tu_int read_block;\n\t\tu_int write_block;\n\t\tu_int partition;\n\t\tu_int interleave;\n\t} geo[4];\n};\n\ntypedef struct cistpl_device_geo_t cistpl_device_geo_t;\n\nstruct cistpl_vers_2_t {\n\tu_char vers;\n\tu_char comply;\n\tu_short dindex;\n\tu_char vspec8;\n\tu_char vspec9;\n\tu_char nhdr;\n\tu_char vendor;\n\tu_char info;\n\tchar str[244];\n};\n\ntypedef struct cistpl_vers_2_t cistpl_vers_2_t;\n\nstruct cistpl_org_t {\n\tu_char data_org;\n\tchar desc[30];\n};\n\ntypedef struct cistpl_org_t cistpl_org_t;\n\nstruct cistpl_format_t {\n\tu_char type;\n\tu_char edc;\n\tu_int offset;\n\tu_int length;\n};\n\ntypedef struct cistpl_format_t cistpl_format_t;\n\nunion cisparse_t {\n\tcistpl_device_t device;\n\tcistpl_checksum_t checksum;\n\tcistpl_longlink_t longlink;\n\tcistpl_longlink_mfc_t longlink_mfc;\n\tcistpl_vers_1_t version_1;\n\tcistpl_altstr_t altstr;\n\tcistpl_jedec_t jedec;\n\tcistpl_manfid_t manfid;\n\tcistpl_funcid_t funcid;\n\tcistpl_funce_t funce;\n\tcistpl_bar_t bar;\n\tcistpl_config_t config;\n\tcistpl_cftable_entry_t cftable_entry;\n\tcistpl_cftable_entry_cb_t cftable_entry_cb;\n\tcistpl_device_geo_t device_geo;\n\tcistpl_vers_2_t vers_2;\n\tcistpl_org_t org;\n\tcistpl_format_t format;\n};\n\ntypedef union cisparse_t cisparse_t;\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n};\n\nstruct i915_sw_fence;\n\ntypedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *, enum i915_sw_fence_notify);\n\nstruct i915_sw_fence {\n\twait_queue_head_t wait;\n\ti915_sw_fence_notify_t fn;\n\tatomic_t pending;\n\tint error;\n};\n\nstruct i915_sw_dma_fence_cb {\n\tstruct dma_fence_cb base;\n\tstruct i915_sw_fence *fence;\n};\n\nstruct dma_fence_work_ops;\n\nstruct dma_fence_work {\n\tstruct dma_fence dma;\n\tspinlock_t lock;\n\tstruct i915_sw_fence chain;\n\tstruct i915_sw_dma_fence_cb cb;\n\tstruct work_struct work;\n\tconst struct dma_fence_work_ops *ops;\n};\n\nstruct drm_i915_gem_object;\n\nstruct clflush {\n\tstruct dma_fence_work base;\n\tstruct drm_i915_gem_object *obj;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct list_head wd_list;\n\tu64 cs_last;\n\tu64 wd_last;\n\tstruct module *owner;\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct dm_table;\n\nstruct dm_io;\n\nstruct clone_info {\n\tstruct dm_table *map;\n\tstruct bio *bio;\n\tstruct dm_io *io;\n\tsector_t sector;\n\tunsigned int sector_count;\n\tbool is_abnormal_io: 1;\n\tbool submit_as_polled: 1;\n};\n\nstruct tc_action;\n\nstruct tcf_exts_miss_cookie_node;\n\nstruct tcf_exts {\n\t__u32 type;\n\tint nr_actions;\n\tstruct tc_action **actions;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct tcf_exts_miss_cookie_node *miss_cookie_node;\n\tint action;\n\tint police;\n};\n\nstruct tcf_ematch_tree_hdr {\n\t__u16 nmatches;\n\t__u16 progid;\n};\n\nstruct tcf_ematch;\n\nstruct tcf_ematch_tree {\n\tstruct tcf_ematch_tree_hdr hdr;\n\tstruct tcf_ematch *matches;\n};\n\nstruct tcf_proto;\n\nstruct cls_cgroup_head {\n\tu32 handle;\n\tstruct tcf_exts exts;\n\tstruct tcf_ematch_tree ematches;\n\tstruct tcf_proto *tp;\n\tstruct rcu_work rwork;\n};\n\nstruct cmac_tfm_ctx {\n\tstruct crypto_cipher *child;\n\t__be64 consts[0];\n};\n\nstruct drm_i915_cmd_descriptor;\n\nstruct cmd_node {\n\tconst struct drm_i915_cmd_descriptor *desc;\n\tstruct hlist_node node;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmos_rtc;\n\nstruct rtc_time;\n\nstruct cmos_read_alarm_callback_param {\n\tstruct cmos_rtc *cmos;\n\tstruct rtc_time *time;\n\tunsigned char rtc_control;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtc_device;\n\nstruct cmos_rtc {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tint irq;\n\tstruct resource *iomem;\n\ttime64_t alarm_expires;\n\tvoid (*wake_on)(struct device *);\n\tvoid (*wake_off)(struct device *);\n\tu8 enabled_wake;\n\tu8 suspend_ctrl;\n\tu8 day_alrm;\n\tu8 mon_alrm;\n\tu8 century;\n\tstruct rtc_wkalrm saved_wkalrm;\n};\n\nstruct cmos_rtc_board_info {\n\tvoid (*wake_on)(struct device *);\n\tvoid (*wake_off)(struct device *);\n\tu32 flags;\n\tint address_space;\n\tu8 rtc_day_alarm;\n\tu8 rtc_mon_alarm;\n\tu8 rtc_century;\n};\n\nstruct cmos_set_alarm_callback_param {\n\tstruct cmos_rtc *cmos;\n\tunsigned char mon;\n\tunsigned char mday;\n\tunsigned char hrs;\n\tunsigned char min;\n\tunsigned char sec;\n\tstruct rtc_wkalrm *t;\n};\n\nstruct cmp_data {\n\tstruct task_struct *thr;\n\tstruct crypto_acomp *cc;\n\tstruct acomp_req *cr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct cn_callback_id {\n\tunsigned char name[32];\n\tstruct cb_id id;\n};\n\nstruct cn_queue_dev;\n\nstruct cn_msg;\n\nstruct netlink_skb_parms;\n\nstruct cn_callback_entry {\n\tstruct list_head callback_entry;\n\trefcount_t refcnt;\n\tstruct cn_queue_dev *pdev;\n\tstruct cn_callback_id id;\n\tvoid (*callback)(struct cn_msg *, struct netlink_skb_parms *);\n\tu32 seq;\n\tu32 group;\n};\n\nstruct cn_dev {\n\tstruct cb_id id;\n\tu32 seq;\n\tu32 groups;\n\tstruct sock *nls;\n\tstruct cn_queue_dev *cbdev;\n};\n\nstruct cn_msg {\n\tstruct cb_id id;\n\t__u32 seq;\n\t__u32 ack;\n\t__u16 len;\n\t__u16 flags;\n\t__u8 data[0];\n};\n\nstruct cn_queue_dev {\n\tatomic_t refcnt;\n\tunsigned char name[32];\n\tstruct list_head queue_list;\n\tspinlock_t queue_lock;\n\tstruct sock *nls;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct coef_fw {\n\tunsigned char nid;\n\tunsigned char idx;\n\tshort unsigned int mask;\n\tshort unsigned int val;\n};\n\nstruct color_conversion {\n\tu16 ry;\n\tu16 gy;\n\tu16 by;\n\tu16 ay;\n\tu16 ru;\n\tu16 gu;\n\tu16 bu;\n\tu16 au;\n\tu16 rv;\n\tu16 gv;\n\tu16 bv;\n\tu16 av;\n};\n\nstruct comm_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tchar comm[16];\n};\n\nstruct comp_opts {\n\tint dict_size;\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[11];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_blk_user_trace_setup {\n\tchar name[32];\n\tu16 act_mask;\n\tint: 0;\n\tu32 buf_size;\n\tu32 buf_nr;\n\tcompat_u64 start_lba;\n\tcompat_u64 end_lba;\n\tu32 pid;\n} __attribute__((packed));\n\nstruct compat_blkpg_ioctl_arg {\n\tcompat_int_t op;\n\tcompat_int_t flags;\n\tcompat_int_t datalen;\n\tcompat_caddr_t data;\n};\n\nstruct compat_cdrom_generic_command {\n\tunsigned char cmd[12];\n\tcompat_caddr_t buffer;\n\tcompat_uint_t buflen;\n\tcompat_int_t stat;\n\tcompat_caddr_t sense;\n\tunsigned char data_direction;\n\tunsigned char pad[3];\n\tcompat_int_t quiet;\n\tcompat_int_t timeout;\n\tcompat_caddr_t unused;\n};\n\nstruct compat_cmsghdr {\n\tcompat_size_t cmsg_len;\n\tcompat_int_t cmsg_level;\n\tcompat_int_t cmsg_type;\n};\n\nstruct compat_console_font_op {\n\tcompat_uint_t op;\n\tcompat_uint_t flags;\n\tcompat_uint_t width;\n\tcompat_uint_t height;\n\tcompat_uint_t charcount;\n\tcompat_caddr_t data;\n};\n\nstruct compat_elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tcompat_ulong_t pr_flag;\n\t__compat_uid_t pr_uid;\n\t__compat_gid_t pr_gid;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct compat_elf_siginfo {\n\tcompat_int_t si_signo;\n\tcompat_int_t si_code;\n\tcompat_int_t si_errno;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct compat_elf_prstatus_common {\n\tstruct compat_elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tcompat_ulong_t pr_sigpend;\n\tcompat_ulong_t pr_sighold;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tstruct old_timeval32 pr_utime;\n\tstruct old_timeval32 pr_stime;\n\tstruct old_timeval32 pr_cutime;\n\tstruct old_timeval32 pr_cstime;\n};\n\nstruct user_regs_struct {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bp;\n\tlong unsigned int bx;\n\tlong unsigned int r11;\n\tlong unsigned int r10;\n\tlong unsigned int r9;\n\tlong unsigned int r8;\n\tlong unsigned int ax;\n\tlong unsigned int cx;\n\tlong unsigned int dx;\n\tlong unsigned int si;\n\tlong unsigned int di;\n\tlong unsigned int orig_ax;\n\tlong unsigned int ip;\n\tlong unsigned int cs;\n\tlong unsigned int flags;\n\tlong unsigned int sp;\n\tlong unsigned int ss;\n\tlong unsigned int fs_base;\n\tlong unsigned int gs_base;\n\tlong unsigned int ds;\n\tlong unsigned int es;\n\tlong unsigned int fs;\n\tlong unsigned int gs;\n};\n\ntypedef struct user_regs_struct compat_elf_gregset_t;\n\nstruct compat_elf_prstatus {\n\tstruct compat_elf_prstatus_common common;\n\tcompat_elf_gregset_t pr_reg;\n\tcompat_int_t pr_fpvalid;\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct compat_ethtool_rx_flow_spec {\n\tu32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\tcompat_u64 ring_cookie;\n\tu32 location;\n} __attribute__((packed));\n\nstruct compat_ethtool_rxnfc {\n\tu32 cmd;\n\tu32 flow_type;\n\tcompat_u64 data;\n\tstruct compat_ethtool_rx_flow_spec fs;\n\tu32 rule_cnt;\n\tu32 rule_locs[0];\n} __attribute__((packed));\n\nstruct compat_flock {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_off_t l_start;\n\tcompat_off_t l_len;\n\tcompat_pid_t l_pid;\n};\n\nstruct compat_flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_loff_t l_start;\n\tcompat_loff_t l_len;\n\tcompat_pid_t l_pid;\n} __attribute__((packed));\n\nstruct compat_fs_qfilestat {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 qfs_nblks;\n\tcompat_uint_t qfs_nextents;\n} __attribute__((packed));\n\nstruct compat_fs_quota_stat {\n\t__s8 qs_version;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tlong: 0;\n\tstruct compat_fs_qfilestat qs_uquota;\n\tstruct compat_fs_qfilestat qs_gquota;\n\tcompat_uint_t qs_incoredqs;\n\tcompat_int_t qs_btimelimit;\n\tcompat_int_t qs_itimelimit;\n\tcompat_int_t qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct compat_linux_dirent;\n\nstruct compat_getdents_callback {\n\tstruct dir_context ctx;\n\tstruct compat_linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t} __attribute__((packed));\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n} __attribute__((packed));\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n} __attribute__((packed));\n\nstruct compat_hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tu32 start;\n};\n\nstruct compat_hpet_info {\n\tcompat_ulong_t hi_ireqfreq;\n\tcompat_ulong_t hi_flags;\n\tshort unsigned int hi_hpet;\n\tshort unsigned int hi_timer;\n};\n\nstruct compat_if_dqblk {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 dqb_bsoftlimit;\n\tcompat_u64 dqb_curspace;\n\tcompat_u64 dqb_ihardlimit;\n\tcompat_u64 dqb_isoftlimit;\n\tcompat_u64 dqb_curinodes;\n\tcompat_u64 dqb_btime;\n\tcompat_u64 dqb_itime;\n\tcompat_uint_t dqb_valid;\n} __attribute__((packed));\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_ipc64_perm {\n\tcompat_key_t key;\n\t__compat_uid32_t uid;\n\t__compat_gid32_t gid;\n\t__compat_uid32_t cuid;\n\t__compat_gid32_t cgid;\n\tcompat_mode_t mode;\n\tunsigned char __pad1[2];\n\tcompat_ushort_t seq;\n\tcompat_ushort_t __pad2;\n\tcompat_ulong_t unused1;\n\tcompat_ulong_t unused2;\n};\n\nstruct compat_ipc_kludge {\n\tcompat_uptr_t msgp;\n\tcompat_long_t msgtyp;\n};\n\nstruct compat_ipc_perm {\n\tkey_t key;\n\t__compat_uid_t uid;\n\t__compat_gid_t gid;\n\t__compat_uid_t cuid;\n\t__compat_gid_t cgid;\n\tcompat_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct compat_kexec_segment {\n\tcompat_uptr_t buf;\n\tcompat_size_t bufsz;\n\tcompat_ulong_t mem;\n\tcompat_size_t memsz;\n};\n\nstruct compat_kvm_clear_dirty_log {\n\t__u32 slot;\n\t__u32 num_pages;\n\t__u64 first_page;\n\tunion {\n\t\tcompat_uptr_t dirty_bitmap;\n\t\t__u64 padding2;\n\t};\n};\n\nstruct compat_kvm_dirty_log {\n\t__u32 slot;\n\t__u32 padding1;\n\tunion {\n\t\tcompat_uptr_t dirty_bitmap;\n\t\t__u64 padding2;\n\t};\n};\n\nstruct compat_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct compat_loop_info {\n\tcompat_int_t lo_number;\n\tcompat_dev_t lo_device;\n\tcompat_ulong_t lo_inode;\n\tcompat_dev_t lo_rdevice;\n\tcompat_int_t lo_offset;\n\tcompat_int_t lo_encrypt_type;\n\tcompat_int_t lo_encrypt_key_size;\n\tcompat_int_t lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tcompat_ulong_t lo_init[2];\n\tchar reserved[4];\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_mq_attr {\n\tcompat_long_t mq_flags;\n\tcompat_long_t mq_maxmsg;\n\tcompat_long_t mq_msgsize;\n\tcompat_long_t mq_curmsgs;\n\tcompat_long_t __reserved[4];\n};\n\nstruct compat_msgbuf {\n\tcompat_long_t mtype;\n\tchar mtext[0];\n};\n\nstruct compat_msqid64_ds {\n\tstruct compat_ipc64_perm msg_perm;\n\tcompat_ulong_t msg_stime;\n\tcompat_ulong_t msg_stime_high;\n\tcompat_ulong_t msg_rtime;\n\tcompat_ulong_t msg_rtime_high;\n\tcompat_ulong_t msg_ctime;\n\tcompat_ulong_t msg_ctime_high;\n\tcompat_ulong_t msg_cbytes;\n\tcompat_ulong_t msg_qnum;\n\tcompat_ulong_t msg_qbytes;\n\tcompat_pid_t msg_lspid;\n\tcompat_pid_t msg_lrpid;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_msqid_ds {\n\tstruct compat_ipc_perm msg_perm;\n\tcompat_uptr_t msg_first;\n\tcompat_uptr_t msg_last;\n\told_time32_t msg_stime;\n\told_time32_t msg_rtime;\n\told_time32_t msg_ctime;\n\tcompat_ulong_t msg_lcbytes;\n\tcompat_ulong_t msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\tcompat_ipc_pid_t msg_lspid;\n\tcompat_ipc_pid_t msg_lrpid;\n};\n\nstruct compat_old_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct compat_old_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_old_sigset_t sa_mask;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n};\n\nstruct compat_readdir_callback {\n\tstruct dir_context ctx;\n\tstruct compat_old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct compat_resume_swap_area {\n\tcompat_loff_t offset;\n\tu32 dev;\n} __attribute__((packed));\n\nstruct compat_rlimit {\n\tcompat_ulong_t rlim_cur;\n\tcompat_ulong_t rlim_max;\n};\n\nstruct compat_robust_list {\n\tcompat_uptr_t next;\n};\n\nstruct compat_robust_list_head {\n\tstruct compat_robust_list list;\n\tcompat_long_t futex_offset;\n\tcompat_uptr_t list_op_pending;\n};\n\nstruct compat_rtentry {\n\tu32 rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tu32 rt_pad3;\n\tunsigned char rt_tos;\n\tunsigned char rt_class;\n\tshort int rt_pad4;\n\tshort int rt_metric;\n\tcompat_uptr_t rt_dev;\n\tu32 rt_mtu;\n\tu32 rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct compat_rusage {\n\tstruct old_timeval32 ru_utime;\n\tstruct old_timeval32 ru_stime;\n\tcompat_long_t ru_maxrss;\n\tcompat_long_t ru_ixrss;\n\tcompat_long_t ru_idrss;\n\tcompat_long_t ru_isrss;\n\tcompat_long_t ru_minflt;\n\tcompat_long_t ru_majflt;\n\tcompat_long_t ru_nswap;\n\tcompat_long_t ru_inblock;\n\tcompat_long_t ru_oublock;\n\tcompat_long_t ru_msgsnd;\n\tcompat_long_t ru_msgrcv;\n\tcompat_long_t ru_nsignals;\n\tcompat_long_t ru_nvcsw;\n\tcompat_long_t ru_nivcsw;\n};\n\nstruct compat_sel_arg_struct {\n\tcompat_ulong_t n;\n\tcompat_uptr_t inp;\n\tcompat_uptr_t outp;\n\tcompat_uptr_t exp;\n\tcompat_uptr_t tvp;\n};\n\nstruct compat_semid64_ds {\n\tstruct compat_ipc64_perm sem_perm;\n\tcompat_ulong_t sem_otime;\n\tcompat_ulong_t sem_otime_high;\n\tcompat_ulong_t sem_ctime;\n\tcompat_ulong_t sem_ctime_high;\n\tcompat_ulong_t sem_nsems;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_semid_ds {\n\tstruct compat_ipc_perm sem_perm;\n\told_time32_t sem_otime;\n\told_time32_t sem_ctime;\n\tcompat_uptr_t sem_base;\n\tcompat_uptr_t sem_pending;\n\tcompat_uptr_t sem_pending_last;\n\tcompat_uptr_t undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct compat_sg_io_hdr {\n\tcompat_int_t interface_id;\n\tcompat_int_t dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tcompat_uint_t dxfer_len;\n\tcompat_uint_t dxferp;\n\tcompat_uptr_t cmdp;\n\tcompat_uptr_t sbp;\n\tcompat_uint_t timeout;\n\tcompat_uint_t flags;\n\tcompat_int_t pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tcompat_int_t resid;\n\tcompat_uint_t duration;\n\tcompat_uint_t info;\n};\n\nstruct compat_sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\nstruct compat_shm_info {\n\tcompat_int_t used_ids;\n\tcompat_ulong_t shm_tot;\n\tcompat_ulong_t shm_rss;\n\tcompat_ulong_t shm_swp;\n\tcompat_ulong_t swap_attempts;\n\tcompat_ulong_t swap_successes;\n};\n\nstruct compat_shmid64_ds {\n\tstruct compat_ipc64_perm shm_perm;\n\tcompat_size_t shm_segsz;\n\tcompat_ulong_t shm_atime;\n\tcompat_ulong_t shm_atime_high;\n\tcompat_ulong_t shm_dtime;\n\tcompat_ulong_t shm_dtime_high;\n\tcompat_ulong_t shm_ctime;\n\tcompat_ulong_t shm_ctime_high;\n\tcompat_pid_t shm_cpid;\n\tcompat_pid_t shm_lpid;\n\tcompat_ulong_t shm_nattch;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_shmid_ds {\n\tstruct compat_ipc_perm shm_perm;\n\tint shm_segsz;\n\told_time32_t shm_atime;\n\told_time32_t shm_dtime;\n\told_time32_t shm_ctime;\n\tcompat_ipc_pid_t shm_cpid;\n\tcompat_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tcompat_uptr_t shm_unused2;\n\tcompat_uptr_t shm_unused3;\n};\n\nstruct compat_shminfo64 {\n\tcompat_ulong_t shmmax;\n\tcompat_ulong_t shmmin;\n\tcompat_ulong_t shmmni;\n\tcompat_ulong_t shmseg;\n\tcompat_ulong_t shmall;\n\tcompat_ulong_t __unused1;\n\tcompat_ulong_t __unused2;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n\tcompat_sigset_t sa_mask;\n};\n\nstruct compat_sigaltstack {\n\tcompat_uptr_t ss_sp;\n\tint ss_flags;\n\tcompat_size_t ss_size;\n};\n\ntypedef struct compat_sigaltstack compat_stack_t;\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_sigevent {\n\tcompat_sigval_t sigev_value;\n\tcompat_int_t sigev_signo;\n\tcompat_int_t sigev_notify;\n\tunion {\n\t\tcompat_int_t _pad[13];\n\t\tcompat_int_t _tid;\n\t\tstruct {\n\t\t\tcompat_uptr_t _function;\n\t\t\tcompat_uptr_t _attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\ntypedef struct compat_siginfo compat_siginfo_t;\n\nstruct compat_sigset_argpack {\n\tcompat_uptr_t p;\n\tcompat_size_t size;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct compat_sioc_sg_req {\n\tstruct in_addr src;\n\tstruct in_addr grp;\n\tcompat_ulong_t pktcnt;\n\tcompat_ulong_t bytecnt;\n\tcompat_ulong_t wrong_if;\n};\n\nstruct compat_sioc_vif_req {\n\tvifi_t vifi;\n\tcompat_ulong_t icount;\n\tcompat_ulong_t ocount;\n\tcompat_ulong_t ibytes;\n\tcompat_ulong_t obytes;\n};\n\nstruct compat_snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct compat_stat {\n\tu32 st_dev;\n\tcompat_ino_t st_ino;\n\tcompat_mode_t st_mode;\n\tcompat_nlink_t st_nlink;\n\t__compat_uid_t st_uid;\n\t__compat_gid_t st_gid;\n\tu32 st_rdev;\n\tu32 st_size;\n\tu32 st_blksize;\n\tu32 st_blocks;\n\tu32 st_atime;\n\tu32 st_atime_nsec;\n\tu32 st_mtime;\n\tu32 st_mtime_nsec;\n\tu32 st_ctime;\n\tu32 st_ctime_nsec;\n\tu32 __unused4;\n\tu32 __unused5;\n};\n\nstruct compat_statfs {\n\tint f_type;\n\tint f_bsize;\n\tint f_blocks;\n\tint f_bfree;\n\tint f_bavail;\n\tint f_files;\n\tint f_ffree;\n\tcompat_fsid_t f_fsid;\n\tint f_namelen;\n\tint f_frsize;\n\tint f_flags;\n\tint f_spare[4];\n};\n\nstruct compat_statfs64 {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_frsize;\n\t__u32 f_flags;\n\t__u32 f_spare[4];\n} __attribute__((packed));\n\nstruct compat_sysinfo {\n\ts32 uptime;\n\tu32 loads[3];\n\tu32 totalram;\n\tu32 freeram;\n\tu32 sharedram;\n\tu32 bufferram;\n\tu32 totalswap;\n\tu32 freeswap;\n\tu16 procs;\n\tu16 pad;\n\tu32 totalhigh;\n\tu32 freehigh;\n\tu32 mem_unit;\n\tchar _f[8];\n};\n\nstruct compat_tms {\n\tcompat_clock_t tms_utime;\n\tcompat_clock_t tms_stime;\n\tcompat_clock_t tms_cutime;\n\tcompat_clock_t tms_cstime;\n};\n\nstruct compat_unimapdesc {\n\tshort unsigned int entry_ct;\n\tcompat_caddr_t entries;\n};\n\nstruct compat_ustat {\n\tcompat_daddr_t f_tfree;\n\tcompat_ino_t f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct dmi_system_id;\n\nstruct snd_soc_acpi_codecs;\n\nstruct config_entry {\n\tu32 flags;\n\tu16 device;\n\tu8 acpi_hid[16];\n\tconst struct dmi_system_id *dmi_table;\n\tconst struct snd_soc_acpi_codecs *codec_hid;\n};\n\nstruct deflate_state;\n\ntypedef struct deflate_state deflate_state;\n\ntypedef block_state (*compress_func)(deflate_state *, int);\n\nstruct config_s {\n\tush good_length;\n\tush max_lazy;\n\tush nice_length;\n\tush max_chain;\n\tcompress_func func;\n};\n\ntypedef struct config_s config;\n\nstruct config_t {\n\tstruct kref ref;\n\tunsigned int state;\n\tstruct resource io[2];\n\tstruct resource mem[4];\n};\n\ntypedef struct config_t config_t;\n\nstruct console;\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct;\n\nstruct console___2 {\n\tstruct list_head list;\n\tstruct hvc_struct *hvc;\n\tstruct winsize ws;\n\tu32 vtermno;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct microcode_amd;\n\nstruct cont_desc {\n\tstruct microcode_amd *mc;\n\tu32 psize;\n\tu8 *data;\n\tsize_t size;\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n};\n\nstruct context_entry {\n\tu64 lo;\n\tu64 hi;\n};\n\nstruct guc_update_context_policy_header {\n\tu32 action;\n\tu32 ctx_id;\n};\n\nstruct guc_klv_generic_dw_t {\n\tu32 kl;\n\tu32 value;\n};\n\nstruct guc_update_context_policy {\n\tstruct guc_update_context_policy_header header;\n\tstruct guc_klv_generic_dw_t klv[5];\n};\n\nstruct context_policy {\n\tu32 count;\n\tstruct guc_update_context_policy h2g;\n};\n\nstruct context_tracking {\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct virtio_net_ctrl_hdr {\n\t__u8 class;\n\t__u8 cmd;\n};\n\nstruct control_buf {\n\tstruct virtio_net_ctrl_hdr hdr;\n\tvirtio_net_ctrl_ack status;\n};\n\nstruct cooling_spec {\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tunsigned int weight;\n};\n\nstruct copy_subpage_arg {\n\tstruct folio *dst;\n\tstruct folio *src;\n\tstruct vm_area_struct *vma;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_text {\n\tlong unsigned int base;\n\tlong unsigned int end;\n\tconst char *name;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct pgprot {\n\tpgprotval_t pgprot;\n};\n\ntypedef struct pgprot pgprot_t;\n\nstruct cpa_data {\n\tlong unsigned int *vaddr;\n\tpgd_t *pgd;\n\tpgprot_t mask_set;\n\tpgprot_t mask_clr;\n\tlong unsigned int numpages;\n\tlong unsigned int curpage;\n\tlong unsigned int pfn;\n\tunsigned int flags;\n\tunsigned int force_split: 1;\n\tunsigned int force_static_prot: 1;\n\tunsigned int force_flush_all: 1;\n\tstruct page **pages;\n};\n\nstruct cparams {\n\tu16 i;\n\tu16 t;\n\tu16 m;\n\tu16 c;\n};\n\nstruct cpc_reg {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct cpc_register_resource {\n\tacpi_object_type type;\n\tu64 *sys_mem_vaddr;\n\tunion {\n\t\tstruct cpc_reg reg;\n\t\tu64 int_value;\n\t} cpc_entry;\n};\n\nstruct cpc_desc {\n\tint num_entries;\n\tint version;\n\tint cpu_id;\n\tint write_cmd_status;\n\tint write_cmd_id;\n\traw_spinlock_t rmw_lock;\n\tstruct cpc_register_resource cpc_regs[21];\n\tstruct acpi_psd_package domain_info;\n\tstruct kobject kobj;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cppc_perf_caps {\n\tu32 guaranteed_perf;\n\tu32 highest_perf;\n\tu32 nominal_perf;\n\tu32 lowest_perf;\n\tu32 lowest_nonlinear_perf;\n\tu32 lowest_freq;\n\tu32 nominal_freq;\n};\n\nstruct cppc_perf_ctrls {\n\tu32 max_perf;\n\tu32 min_perf;\n\tu32 desired_perf;\n\tu32 energy_perf;\n\tbool auto_sel;\n};\n\nstruct cppc_perf_fb_ctrs {\n\tu64 reference;\n\tu64 delivered;\n\tu64 reference_perf;\n\tu64 wraparound_time;\n};\n\nstruct cppc_cpudata {\n\tstruct cppc_perf_caps perf_caps;\n\tstruct cppc_perf_ctrls perf_ctrls;\n\tstruct cppc_perf_fb_ctrs perf_fb_ctrs;\n\tunsigned int shared_type;\n\tcpumask_var_t shared_cpu_map;\n};\n\nstruct pcc_mbox_chan;\n\nstruct cppc_pcc_data {\n\tstruct pcc_mbox_chan *pcc_channel;\n\tbool pcc_channel_acquired;\n\tunsigned int deadline_us;\n\tunsigned int pcc_mpar;\n\tunsigned int pcc_mrtt;\n\tunsigned int pcc_nominal;\n\tbool pending_pcc_write_cmd;\n\tbool platform_owns_pcc;\n\tunsigned int pcc_write_cnt;\n\tstruct rw_semaphore pcc_lock;\n\twait_queue_head_t pcc_write_wait_q;\n\tktime_t last_cmd_cmpl_time;\n\tktime_t last_mpar_reset;\n\tint mpar_count;\n\tint refcount;\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct update_util_data {\n\tvoid (*func)(struct update_util_data *, u64, unsigned int);\n};\n\nstruct policy_dbs_info;\n\nstruct cpu_dbs_info {\n\tu64 prev_cpu_idle;\n\tu64 prev_update_time;\n\tu64 prev_cpu_nice;\n\tunsigned int prev_load;\n\tstruct update_util_data update_util;\n\tstruct policy_dbs_info *policy_dbs;\n};\n\nstruct cpuinfo_x86;\n\nstruct cpu_dev {\n\tconst char *c_vendor;\n\tconst char *c_ident[2];\n\tvoid (*c_early_init)(struct cpuinfo_x86 *);\n\tvoid (*c_bsp_init)(struct cpuinfo_x86 *);\n\tvoid (*c_init)(struct cpuinfo_x86 *);\n\tvoid (*c_identify)(struct cpuinfo_x86 *);\n\tvoid (*c_detect_tlb)(struct cpuinfo_x86 *);\n\tint c_x86_vendor;\n};\n\nstruct entry_stack {\n\tchar stack[4096];\n};\n\nstruct entry_stack_page {\n\tstruct entry_stack stack;\n};\n\nstruct x86_hw_tss {\n\tu32 reserved1;\n\tu64 sp0;\n\tu64 sp1;\n\tu64 sp2;\n\tu64 reserved2;\n\tu64 ist[7];\n\tu32 reserved3;\n\tu32 reserved4;\n\tu16 reserved5;\n\tu16 io_bitmap_base;\n} __attribute__((packed));\n\nstruct x86_io_bitmap {\n\tu64 prev_sequence;\n\tunsigned int prev_max;\n\tlong unsigned int bitmap[1025];\n\tlong unsigned int mapall[1025];\n};\n\nstruct tss_struct {\n\tstruct x86_hw_tss x86_tss;\n\tstruct x86_io_bitmap io_bitmap;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 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64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct debug_store_buffers {\n\tchar bts_buffer[65536];\n\tchar pebs_buffer[65536];\n};\n\nstruct cpu_entry_area {\n\tchar gdt[4096];\n\tstruct entry_stack_page entry_stack_page;\n\tstruct tss_struct tss;\n\tstruct cea_exception_stacks estacks;\n\tstruct debug_store cpu_debug_store;\n\tstruct debug_store_buffers cpu_debug_buffers;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 spec: 2;\n\t__u64 new_type: 4;\n\t__u64 priv: 3;\n\t__u64 reserved: 31;\n};\n\nstruct perf_branch_stack {\n\tu64 nr;\n\tu64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct perf_guest_switch_msr {\n\tunsigned int msr;\n\tu64 host;\n\tu64 guest;\n};\n\nstruct er_account;\n\nstruct intel_shared_regs;\n\nstruct intel_excl_cntrs;\n\nstruct cpu_hw_events {\n\tstruct perf_event *events[64];\n\tlong unsigned int active_mask[1];\n\tlong unsigned int dirty[1];\n\tint enabled;\n\tint n_events;\n\tint n_added;\n\tint n_txn;\n\tint n_txn_pair;\n\tint n_txn_metric;\n\tint assign[64];\n\tu64 tags[64];\n\tstruct perf_event *event_list[64];\n\tstruct event_constraint *event_constraint[64];\n\tint n_excl;\n\tint n_late_setup;\n\tunsigned int txn_flags;\n\tint is_fake;\n\tstruct debug_store *ds;\n\tvoid *ds_bts_vaddr;\n\tvoid *pebs_vaddr;\n\tu64 pebs_enabled;\n\tint n_pebs;\n\tint n_large_pebs;\n\tint n_pebs_via_pt;\n\tint pebs_output;\n\tu64 pebs_data_cfg;\n\tu64 active_pebs_data_cfg;\n\tint pebs_record_size;\n\tu64 fixed_ctrl_val;\n\tu64 active_fixed_ctrl_val;\n\tu64 acr_cfg_b[64];\n\tu64 acr_cfg_c[64];\n\tu64 cfg_c_val[64];\n\tint lbr_users;\n\tint lbr_pebs_users;\n\tstruct perf_branch_stack lbr_stack;\n\tstruct perf_branch_entry lbr_entries[32];\n\tu64 lbr_counters[32];\n\tunion {\n\t\tstruct er_account *lbr_sel;\n\t\tstruct er_account *lbr_ctl;\n\t};\n\tu64 br_sel;\n\tvoid *last_task_ctx;\n\tint last_log_id;\n\tint lbr_select;\n\tvoid *lbr_xsave;\n\tu64 intel_ctrl_guest_mask;\n\tu64 intel_ctrl_host_mask;\n\tstruct perf_guest_switch_msr guest_switch_msrs[64];\n\tu64 intel_cp_status;\n\tstruct intel_shared_regs *shared_regs;\n\tstruct event_constraint *constraint_list;\n\tstruct intel_excl_cntrs *excl_cntrs;\n\tint excl_thread_id;\n\tu64 tfa_shadow;\n\tint n_metric;\n\tstruct amd_nb *amd_nb;\n\tint brs_active;\n\tu64 perf_ctr_virt_mask;\n\tint n_pair;\n\tvoid *kfree_on_online[2];\n\tstruct pmu *pmu;\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_perf_ibs {\n\tstruct perf_event *event;\n\tlong unsigned int state[1];\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_signature {\n\tunsigned int sig;\n\tunsigned int pf;\n\tunsigned int rev;\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct kernel_cpustat;\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tu64 *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct pstate_data {\n\tint current_pstate;\n\tint min_pstate;\n\tint max_pstate;\n\tint max_pstate_physical;\n\tint perf_ctl_scaling;\n\tint scaling;\n\tint turbo_pstate;\n\tunsigned int min_freq;\n\tunsigned int max_freq;\n\tunsigned int turbo_freq;\n};\n\nstruct vid_data {\n\tint min;\n\tint max;\n\tint turbo;\n\tint32_t ratio;\n};\n\nstruct sample {\n\tint32_t core_avg_perf;\n\tint32_t busy_scaled;\n\tu64 aperf;\n\tu64 mperf;\n\tu64 tsc;\n\tu64 time;\n};\n\nstruct cpudata {\n\tint cpu;\n\tunsigned int policy;\n\tstruct update_util_data update_util;\n\tbool update_util_set;\n\tstruct pstate_data pstate;\n\tstruct vid_data vid;\n\tu64 last_update;\n\tu64 last_sample_time;\n\tu64 aperf_mperf_shift;\n\tu64 prev_aperf;\n\tu64 prev_mperf;\n\tu64 prev_tsc;\n\tstruct sample sample;\n\tint32_t min_perf_ratio;\n\tint32_t max_perf_ratio;\n\tstruct acpi_processor_performance acpi_perf_data;\n\tbool valid_pss_table;\n\tunsigned int iowait_boost;\n\ts16 epp_powersave;\n\ts16 epp_policy;\n\ts16 epp_default;\n\ts16 epp_cached;\n\tu64 hwp_req_cached;\n\tu64 hwp_cap_cached;\n\tu64 last_io_update;\n\tunsigned int capacity_perf;\n\tunsigned int sched_flags;\n\tu32 hwp_boost_min;\n\tbool suspended;\n\tstruct delayed_work hwp_notify_work;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_policy;\n\nstruct cpufreq_policy_data;\n\nstruct freq_attr;\n\nstruct cpufreq_driver {\n\tchar name[16];\n\tu16 flags;\n\tvoid *driver_data;\n\tint (*init)(struct cpufreq_policy *);\n\tint (*verify)(struct cpufreq_policy_data *);\n\tint (*setpolicy)(struct cpufreq_policy *);\n\tint (*target)(struct cpufreq_policy *, unsigned int, unsigned int);\n\tint (*target_index)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*fast_switch)(struct cpufreq_policy *, unsigned int);\n\tvoid (*adjust_perf)(unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get)(unsigned int);\n\tvoid (*update_limits)(struct cpufreq_policy *);\n\tint (*bios_limit)(int, unsigned int *);\n\tint (*online)(struct cpufreq_policy *);\n\tint (*offline)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n\tvoid (*ready)(struct cpufreq_policy *);\n\tstruct freq_attr **attr;\n\tbool boost_enabled;\n\tint (*set_boost)(struct cpufreq_policy *, int);\n\tvoid (*register_em)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_freqs {\n\tstruct cpufreq_policy *policy;\n\tunsigned int old;\n\tunsigned int new;\n\tu8 flags;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tstruct list_head governor_list;\n\tstruct module *owner;\n\tu8 flags;\n};\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_read_t;\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_write_t;\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct cpufreq_stats;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tbool strict_target;\n\tbool efficiencies_available;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tbool boost_enabled;\n\tbool boost_supported;\n\tunsigned int cached_target_freq;\n\tunsigned int cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpufreq_policy_data {\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tstruct cpufreq_frequency_table *freq_table;\n\tunsigned int cpu;\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nunion cpuid10_eax {\n\tstruct {\n\t\tunsigned int version_id: 8;\n\t\tunsigned int num_counters: 8;\n\t\tunsigned int bit_width: 8;\n\t\tunsigned int mask_length: 8;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid10_ebx {\n\tstruct {\n\t\tunsigned int no_unhalted_core_cycles: 1;\n\t\tunsigned int no_instructions_retired: 1;\n\t\tunsigned int no_unhalted_reference_cycles: 1;\n\t\tunsigned int no_llc_reference: 1;\n\t\tunsigned int no_llc_misses: 1;\n\t\tunsigned int no_branch_instruction_retired: 1;\n\t\tunsigned int no_branch_misses_retired: 1;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid10_edx {\n\tstruct {\n\t\tunsigned int num_counters_fixed: 5;\n\t\tunsigned int bit_width_fixed: 8;\n\t\tunsigned int reserved1: 2;\n\t\tunsigned int anythread_deprecated: 1;\n\t\tunsigned int reserved2: 16;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid28_eax {\n\tstruct {\n\t\tunsigned int lbr_depth_mask: 8;\n\t\tunsigned int reserved: 22;\n\t\tunsigned int lbr_deep_c_reset: 1;\n\t\tunsigned int lbr_lip: 1;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid28_ebx {\n\tstruct {\n\t\tunsigned int lbr_cpl: 1;\n\t\tunsigned int lbr_filter: 1;\n\t\tunsigned int lbr_call_stack: 1;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid28_ecx {\n\tstruct {\n\t\tunsigned int lbr_mispred: 1;\n\t\tunsigned int lbr_timed_lbr: 1;\n\t\tunsigned int lbr_br_type: 1;\n\t\tunsigned int reserved: 13;\n\t\tunsigned int lbr_counters: 4;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid35_eax {\n\tstruct {\n\t\tunsigned int leaf0: 1;\n\t\tunsigned int cntr_subleaf: 1;\n\t\tunsigned int acr_subleaf: 1;\n\t\tunsigned int events_subleaf: 1;\n\t\tunsigned int pebs_caps_subleaf: 1;\n\t\tunsigned int pebs_cnts_subleaf: 1;\n\t\tunsigned int reserved: 26;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid35_ebx {\n\tstruct {\n\t\tunsigned int umask2: 1;\n\t\tunsigned int eq: 1;\n\t\tunsigned int rdpmc_user_disable: 1;\n\t\tunsigned int reserved: 29;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid_0x80000022_ebx {\n\tstruct {\n\t\tunsigned int num_core_pmc: 4;\n\t\tunsigned int lbr_v2_stack_sz: 6;\n\t\tunsigned int num_df_pmc: 6;\n\t\tunsigned int num_umc_pmc: 6;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid_1_eax {\n\tstruct {\n\t\t__u32 stepping: 4;\n\t\t__u32 model: 4;\n\t\t__u32 family: 4;\n\t\t__u32 __reserved0: 4;\n\t\t__u32 ext_model: 4;\n\t\t__u32 ext_fam: 8;\n\t\t__u32 __reserved1: 4;\n\t};\n\t__u32 full;\n};\n\nstruct cpuid_bit {\n\tu16 feature;\n\tu8 reg;\n\tu8 bit;\n\tu32 level;\n\tu32 sub_leaf;\n};\n\nstruct cpuid_dep {\n\tunsigned int feature;\n\tunsigned int depends;\n};\n\nstruct cpuid_dependent_feature {\n\tu32 feature;\n\tu32 level;\n};\n\nstruct cpuid_reg {\n\tu32 function;\n\tu32 index;\n\tint reg;\n};\n\nstruct cpuid_regs {\n\tu32 eax;\n\tu32 ebx;\n\tu32 ecx;\n\tu32 edx;\n};\n\nstruct cpuid_regs_done {\n\tstruct cpuid_regs regs;\n\tstruct completion done;\n};\n\nstruct cpuid_xstate_sizes {\n\tu32 eax;\n\tu32 ebx;\n\tu32 ecx;\n};\n\nstruct cpuidle_device;\n\nstruct cpuidle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_device *, char *);\n\tssize_t (*store)(struct cpuidle_device *, const char *, size_t);\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct cpuidle_device_kobj {\n\tstruct cpuidle_device *dev;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct cpuidle_governor {\n\tchar name[16];\n\tstruct list_head governor_list;\n\tunsigned int rating;\n\tint (*enable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tvoid (*disable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tint (*select)(struct cpuidle_driver *, struct cpuidle_device *, bool *);\n\tvoid (*reflect)(struct cpuidle_device *, int);\n};\n\nstruct cpuidle_state_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_state *, struct cpuidle_state_usage *, char *);\n\tssize_t (*store)(struct cpuidle_state *, struct cpuidle_state_usage *, const char *, size_t);\n};\n\nstruct cpuidle_state_kobj {\n\tstruct cpuidle_state *state;\n\tstruct cpuidle_state_usage *state_usage;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n\tstruct cpuidle_device *device;\n};\n\nstruct cpuinfo_topology {\n\tu32 apicid;\n\tu32 initial_apicid;\n\tu32 pkg_id;\n\tu32 die_id;\n\tu32 cu_id;\n\tu32 core_id;\n\tu32 logical_pkg_id;\n\tu32 logical_die_id;\n\tu32 logical_core_id;\n\tu32 amd_node_id;\n\tu32 llc_id;\n\tu32 l2c_id;\n\tunion {\n\t\tu32 cpu_type;\n\t\tstruct {\n\t\t\tu32 intel_native_model_id: 24;\n\t\t\tu32 intel_type: 8;\n\t\t};\n\t\tstruct {\n\t\t\tu32 amd_num_processors: 16;\n\t\t\tu32 amd_power_eff_ranking: 8;\n\t\t\tu32 amd_native_model_id: 4;\n\t\t\tu32 amd_type: 4;\n\t\t};\n\t};\n};\n\nstruct cpuinfo_x86 {\n\tunion {\n\t\tstruct {\n\t\t\t__u8 x86_model;\n\t\t\t__u8 x86;\n\t\t\t__u8 x86_vendor;\n\t\t\t__u8 x86_reserved;\n\t\t};\n\t\t__u32 x86_vfm;\n\t};\n\t__u8 x86_stepping;\n\tint x86_tlbsize;\n\t__u32 vmx_capability[5];\n\t__u8 x86_virt_bits;\n\t__u8 x86_phys_bits;\n\t__u32 extended_cpuid_level;\n\tint cpuid_level;\n\tunion {\n\t\t__u32 x86_capability[24];\n\t\tlong unsigned int x86_capability_alignment;\n\t};\n\tchar x86_vendor_id[16];\n\tchar x86_model_id[64];\n\tstruct cpuinfo_topology topo;\n\tunsigned int x86_cache_size;\n\tint x86_cache_alignment;\n\tint x86_cache_max_rmid;\n\tint x86_cache_occ_scale;\n\tint x86_cache_mbm_width_offset;\n\tint x86_power;\n\tlong unsigned int loops_per_jiffy;\n\tu64 ppin;\n\tu16 x86_clflush_size;\n\tu16 booted_cores;\n\tu16 cpu_index;\n\tbool smt_active;\n\tu32 microcode;\n\tu8 x86_cache_bits;\n\tunsigned int initialized: 1;\n};\n\nstruct cpumap {\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int managed_allocated;\n\tbool initialized;\n\tbool online;\n\tlong unsigned int *managed_map;\n\tlong unsigned int alloc_map[0];\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct crash_mem {\n\tunsigned int max_nr_ranges;\n\tunsigned int nr_ranges;\n\tstruct range ranges[0];\n};\n\nstruct crc_data {\n\tstruct task_struct *thr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tunsigned int run_threads;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tu32 *crc32;\n\tsize_t **unc_len;\n\tunsigned char **unc;\n};\n\nstruct drm_i915_private;\n\nstruct intel_memory_region;\n\nstruct create_ext {\n\tstruct drm_i915_private *i915;\n\tstruct intel_memory_region *placements[7];\n\tunsigned int n_placements;\n\tunsigned int placement_mask;\n\tlong unsigned int flags;\n\tunsigned int pat_index;\n};\n\nstruct i915_gem_proto_context;\n\nstruct drm_i915_file_private;\n\nstruct create_ext___2 {\n\tstruct i915_gem_proto_context *pc;\n\tstruct drm_i915_file_private *fpriv;\n};\n\ntypedef const struct cred *class_copy_up_creds_t;\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef class_override_creds_t class_override_creds_ovl_t;\n\ntypedef const struct cred *class_ovl_override_creator_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct crs_csi2 {\n\tstruct list_head entry;\n\tacpi_handle handle;\n\tstruct acpi_device_software_nodes *swnodes;\n\tstruct list_head connections;\n\tu32 port_count;\n};\n\nstruct crs_csi2_connection {\n\tstruct list_head entry;\n\tstruct acpi_resource_csi2_serialbus csi2_data;\n\tacpi_handle remote_handle;\n\tchar remote_name[0];\n};\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_acomp_stream {\n\tspinlock_t lock;\n\tvoid *ctx;\n};\n\nstruct crypto_acomp_streams {\n\tvoid * (*alloc_ctx)(void);\n\tvoid (*free_ctx)(void *);\n\tstruct crypto_acomp_stream *streams;\n\tstruct work_struct stream_work;\n\tcpumask_t stream_want;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_aes_ctx {\n\tu32 key_enc[60];\n\tu32 key_dec[60];\n\tu32 key_length;\n};\n\nstruct crypto_ahash {\n\tbool using_shash;\n\tunsigned int statesize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_akcipher_sync_data {\n\tstruct crypto_akcipher *tfm;\n\tconst void *src;\n\tvoid *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct akcipher_request *req;\n\tstruct crypto_wait cwait;\n\tstruct scatterlist sg;\n\tu8 *buf;\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_skcipher;\n\nstruct crypto_authenc_ctx {\n\tstruct crypto_ahash *auth;\n\tstruct crypto_skcipher *enc;\n};\n\nstruct crypto_authenc_esn_ctx {\n\tunsigned int reqoff;\n\tstruct crypto_ahash *auth;\n\tstruct crypto_skcipher *enc;\n};\n\nstruct crypto_authenc_key_param {\n\t__be32 enckeylen;\n};\n\nstruct crypto_authenc_keys {\n\tconst u8 *authkey;\n\tconst u8 *enckey;\n\tunsigned int authkeylen;\n\tunsigned int enckeylen;\n};\n\nstruct crypto_ccm_ctx {\n\tstruct crypto_ahash *mac;\n\tstruct crypto_skcipher *ctr;\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_ccm_req_priv_ctx {\n\tu8 odata[16];\n\tu8 idata[16];\n\tu8 auth_tag[16];\n\tu32 flags;\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tunion {\n\t\tstruct ahash_request ahreq;\n\t\tstruct skcipher_request skreq;\n\t};\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_gcm_ctx {\n\tstruct crypto_skcipher *ctr;\n\tstruct crypto_ahash *ghash;\n};\n\nstruct crypto_gcm_ghash_ctx {\n\tunsigned int cryptlen;\n\tstruct scatterlist *src;\n\tint (*complete)(struct aead_request *, u32);\n};\n\nstruct crypto_gcm_req_priv_ctx {\n\tu8 iv[16];\n\tu8 auth_tag[16];\n\tu8 iauth_tag[16];\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct scatterlist sg;\n\tstruct crypto_gcm_ghash_ctx ghash_ctx;\n\tunion {\n\t\tstruct ahash_request ahreq;\n\t\tstruct skcipher_request skreq;\n\t} u;\n};\n\nstruct crypto_hash_walk {\n\tconst char *data;\n\tunsigned int offset;\n\tunsigned int flags;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n};\n\nstruct crypto_kpp {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_kpp_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n\tbool test_started;\n};\n\nstruct crypto_lskcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_lskcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct crypto_rfc3686_ctx {\n\tstruct crypto_skcipher *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc3686_req_ctx {\n\tu8 iv[16];\n\tstruct skcipher_request subreq;\n};\n\nstruct crypto_rfc4106_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4106_req_ctx {\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rfc4309_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[3];\n};\n\nstruct crypto_rfc4309_req_ctx {\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rfc4543_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4543_instance_ctx {\n\tstruct crypto_aead_spawn aead;\n};\n\nstruct crypto_rfc4543_req_ctx {\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sig {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sig_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sync_aead {\n\tstruct crypto_aead base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct hlist_head dead;\n\tstruct module *module;\n\tstruct work_struct free_work;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tvoid (*destroy)(struct crypto_alg *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n\tunsigned int algsize;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_alg data;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct csi2_resources_walk_data {\n\tacpi_handle handle;\n\tstruct list_head connections;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[14];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[14];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct cstate_entry {\n\tstruct {\n\t\tunsigned int eax;\n\t\tunsigned int ecx;\n\t} states[8];\n};\n\nstruct cstate_model {\n\tlong unsigned int core_events;\n\tlong unsigned int pkg_events;\n\tlong unsigned int module_events;\n\tlong unsigned int quirks;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ct_data_s {\n\tunion {\n\t\tush freq;\n\t\tush code;\n\t} fc;\n\tunion {\n\t\tush dad;\n\t\tush len;\n\t} dl;\n};\n\ntypedef struct ct_data_s ct_data;\n\nstruct ct_incoming_msg {\n\tstruct list_head link;\n\tu32 size;\n\tu32 msg[0];\n};\n\nstruct ct_request {\n\tstruct list_head link;\n\tu32 fence;\n\tu32 status;\n\tu32 response_len;\n\tu32 *response_buf;\n};\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct cvt_timing {\n\tu8 code[3];\n};\n\nstruct cxsr_latency {\n\tbool is_desktop: 1;\n\tbool is_ddr3: 1;\n\tu16 fsb_freq;\n\tu16 mem_freq;\n\tu16 display_sr;\n\tu16 display_hpll_disable;\n\tu16 cursor_sr;\n\tu16 cursor_hpll_disable;\n};\n\nstruct cyc2ns_data {\n\tu32 cyc2ns_mul;\n\tu32 cyc2ns_shift;\n\tu64 cyc2ns_offset;\n};\n\nstruct cyc2ns {\n\tstruct cyc2ns_data data[2];\n\tseqcount_latch_t seq;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct dax_operations;\n\nstruct dax_holder_operations;\n\nstruct dax_device {\n\tstruct inode inode;\n\tstruct cdev cdev;\n\tvoid *private;\n\tlong unsigned int flags;\n\tconst struct dax_operations *ops;\n\tvoid *holder_data;\n\tconst struct dax_holder_operations *holder_ops;\n};\n\nstruct dev_dax;\n\nstruct dax_device_driver {\n\tstruct device_driver drv;\n\tstruct list_head ids;\n\tenum dax_driver_type type;\n\tint (*probe)(struct dev_dax *);\n\tvoid (*remove)(struct dev_dax *);\n};\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct dax_id {\n\tstruct list_head list;\n\tchar dev_name[30];\n};\n\nstruct dax_mapping {\n\tstruct device dev;\n\tint range_id;\n\tint id;\n};\n\nstruct dax_operations {\n\tlong int (*direct_access)(struct dax_device *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\tint (*zero_page_range)(struct dax_device *, long unsigned int, size_t);\n\tsize_t (*recovery_write)(struct dax_device *, long unsigned int, void *, size_t, struct iov_iter *);\n};\n\nstruct dax_region {\n\tint id;\n\tint target_node;\n\tstruct kref kref;\n\tstruct device *dev;\n\tunsigned int align;\n\tstruct ida ida;\n\tstruct resource res;\n\tstruct device *seed;\n\tstruct device *youngest;\n};\n\nstruct gov_attr_set {\n\tstruct kobject kobj;\n\tstruct list_head policy_list;\n\tstruct mutex update_lock;\n\tint usage_count;\n};\n\nstruct dbs_governor;\n\nstruct dbs_data {\n\tstruct gov_attr_set attr_set;\n\tstruct dbs_governor *gov;\n\tvoid *tuners;\n\tunsigned int ignore_nice_load;\n\tunsigned int sampling_rate;\n\tunsigned int sampling_down_factor;\n\tunsigned int up_threshold;\n\tunsigned int io_is_busy;\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct dbs_governor {\n\tstruct cpufreq_governor gov;\n\tstruct kobj_type kobj_type;\n\tstruct dbs_data *gdbs_data;\n\tunsigned int (*gov_dbs_update)(struct cpufreq_policy *);\n\tstruct policy_dbs_info * (*alloc)(void);\n\tvoid (*free)(struct policy_dbs_info *);\n\tint (*init)(struct dbs_data *);\n\tvoid (*exit)(struct dbs_data *);\n\tvoid (*start)(struct cpufreq_policy *);\n};\n\nstruct dbuf_slice_conf_entry {\n\tu8 active_pipes;\n\tu8 dbuf_mask[4];\n\tbool join_mbus;\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct ddebug_class_map {\n\tstruct list_head link;\n\tstruct module *mod;\n\tconst char *mod_name;\n\tconst char **class_names;\n\tconst int length;\n\tconst int base;\n\tenum class_map_type map_type;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct dec_data {\n\tstruct task_struct *thr;\n\tstruct crypto_acomp *cc;\n\tstruct acomp_req *cr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n};\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct z_stream_s;\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct static_tree_desc_s;\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\nstruct tree_desc_s {\n\tct_data *dyn_tree;\n\tint max_code;\n\tstatic_tree_desc *stat_desc;\n};\n\nstruct deflate_state {\n\tz_streamp strm;\n\tint status;\n\tByte *pending_buf;\n\tulg pending_buf_size;\n\tByte *pending_out;\n\tint pending;\n\tint noheader;\n\tByte data_type;\n\tByte method;\n\tint last_flush;\n\tuInt w_size;\n\tuInt w_bits;\n\tuInt w_mask;\n\tByte *window;\n\tulg window_size;\n\tPos *prev;\n\tPos *head;\n\tuInt ins_h;\n\tuInt hash_size;\n\tuInt hash_bits;\n\tuInt hash_mask;\n\tuInt hash_shift;\n\tlong int block_start;\n\tuInt match_length;\n\tIPos prev_match;\n\tint match_available;\n\tuInt strstart;\n\tuInt match_start;\n\tuInt lookahead;\n\tuInt prev_length;\n\tuInt max_chain_length;\n\tuInt max_lazy_match;\n\tint level;\n\tint strategy;\n\tuInt good_match;\n\tint nice_match;\n\tstruct ct_data_s dyn_ltree[573];\n\tstruct ct_data_s dyn_dtree[61];\n\tstruct ct_data_s bl_tree[39];\n\tstruct tree_desc_s l_desc;\n\tstruct tree_desc_s d_desc;\n\tstruct tree_desc_s bl_desc;\n\tush bl_count[16];\n\tint heap[573];\n\tint heap_len;\n\tint heap_max;\n\tuch depth[573];\n\tuch *l_buf;\n\tuInt lit_bufsize;\n\tuInt last_lit;\n\tush *d_buf;\n\tulg opt_len;\n\tulg static_len;\n\tulg compressed_len;\n\tuInt matches;\n\tint last_eob_len;\n\tush bi_buf;\n\tint bi_valid;\n};\n\nstruct deflate_workspace {\n\tdeflate_state deflate_memory;\n\tByte *window_memory;\n\tPos *prev_memory;\n\tPos *head_memory;\n\tchar *overlay_memory;\n};\n\ntypedef struct deflate_workspace deflate_workspace;\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct filename;\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct pending_free {\n\tstruct list_head zapped;\n\tlong unsigned int lock_chains_being_freed[1024];\n};\n\nstruct delayed_free {\n\tstruct callback_head callback_head;\n\tint index;\n\tint scheduled;\n\tstruct pending_free pf[2];\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct demotion_nodes {\n\tnodemask_t preferred;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n};\n\nunion shortname_store {\n\tunsigned char string[40];\n\tlong unsigned int words[5];\n};\n\nstruct lockref {\n\tunion {\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_bucket {\n\tstruct rb_root tree;\n\tspinlock_t lock;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 64;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct desc_ptr {\n\tshort unsigned int size;\n\tlong unsigned int address;\n} __attribute__((packed));\n\nstruct desc_struct {\n\tu16 limit0;\n\tu16 base0;\n\tu16 base1: 8;\n\tu16 type: 4;\n\tu16 s: 1;\n\tu16 dpl: 2;\n\tu16 p: 1;\n\tu16 limit1: 4;\n\tu16 avl: 1;\n\tu16 l: 1;\n\tu16 d: 1;\n\tu16 g: 1;\n\tu16 base2: 8;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct detailed_data_monitor_range {\n\tu8 min_vfreq;\n\tu8 max_vfreq;\n\tu8 min_hfreq_khz;\n\tu8 max_hfreq_khz;\n\tu8 pixel_clock_mhz;\n\tu8 flags;\n\tunion {\n\t\tstruct {\n\t\t\tu8 reserved;\n\t\t\tu8 hfreq_start_khz;\n\t\t\tu8 c;\n\t\t\t__le16 m;\n\t\t\tu8 k;\n\t\t\tu8 j;\n\t\t} __attribute__((packed)) gtf2;\n\t\tstruct {\n\t\t\tu8 version;\n\t\t\tu8 data1;\n\t\t\tu8 data2;\n\t\t\tu8 supported_aspects;\n\t\t\tu8 flags;\n\t\t\tu8 supported_scalings;\n\t\t\tu8 preferred_refresh;\n\t\t} cvt;\n\t} formula;\n};\n\nstruct detailed_data_string {\n\tu8 str[13];\n};\n\nstruct detailed_data_wpindex {\n\tu8 white_yx_lo;\n\tu8 white_x_hi;\n\tu8 white_y_hi;\n\tu8 gamma;\n};\n\nstruct detailed_mode_closure {\n\tstruct drm_connector *connector;\n\tconst struct drm_edid *drm_edid;\n\tbool preferred;\n\tint modes;\n};\n\nstruct std_timing {\n\tu8 hsize;\n\tu8 vfreq_aspect;\n};\n\nstruct detailed_non_pixel {\n\tu8 pad1;\n\tu8 type;\n\tu8 pad2;\n\tunion {\n\t\tstruct detailed_data_string str;\n\t\tstruct detailed_data_monitor_range range;\n\t\tstruct detailed_data_wpindex color;\n\t\tstruct std_timing timings[6];\n\t\tstruct cvt_timing cvt[4];\n\t} data;\n};\n\nstruct detailed_pixel_timing {\n\tu8 hactive_lo;\n\tu8 hblank_lo;\n\tu8 hactive_hblank_hi;\n\tu8 vactive_lo;\n\tu8 vblank_lo;\n\tu8 vactive_vblank_hi;\n\tu8 hsync_offset_lo;\n\tu8 hsync_pulse_width_lo;\n\tu8 vsync_offset_pulse_width_lo;\n\tu8 hsync_vsync_offset_pulse_width_hi;\n\tu8 width_mm_lo;\n\tu8 height_mm_lo;\n\tu8 width_height_mm_hi;\n\tu8 hborder;\n\tu8 vborder;\n\tu8 misc;\n};\n\nstruct detailed_timing {\n\t__le16 pixel_clock;\n\tunion {\n\t\tstruct detailed_pixel_timing pixel_data;\n\t\tstruct detailed_non_pixel other_data;\n\t} data;\n};\n\nstruct detected_devices_node {\n\tstruct list_head list;\n\tdev_t dev;\n};\n\nstruct dev_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head exceptions;\n\tenum devcg_behavior behavior;\n};\n\nstruct dev_pagemap;\n\nstruct dev_dax_range;\n\nstruct dev_dax {\n\tstruct dax_region *region;\n\tstruct dax_device *dax_dev;\n\tunsigned int align;\n\tint target_node;\n\tbool dyn_id;\n\tint id;\n\tstruct ida ida;\n\tstruct device dev;\n\tstruct dev_pagemap *pgmap;\n\tbool memmap_on_memory;\n\tint nr_range;\n\tstruct dev_dax_range *ranges;\n};\n\nstruct dev_dax_data {\n\tstruct dax_region *dax_region;\n\tstruct dev_pagemap *pgmap;\n\tresource_size_t size;\n\tint id;\n\tbool memmap_on_memory;\n};\n\nstruct dev_dax_range {\n\tlong unsigned int pgoff;\n\tstruct range range;\n\tstruct dax_mapping *mapping;\n};\n\nstruct dev_exception_item {\n\tu32 major;\n\tu32 minor;\n\tshort int type;\n\tshort int access;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n\tu32 max_pasids;\n\tu32 attach_deferred: 1;\n\tu32 pci_32bit_workaround: 1;\n\tu32 require_direct: 1;\n\tu32 shadow_on_flush: 1;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct dev_pasid_info {\n\tstruct list_head link_domain;\n\tstruct device *dev;\n\tioasid_t pasid;\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct dev_pm_domain_attach_data {\n\tconst char * const *pd_names;\n\tconst u32 num_pd_names;\n\tconst u32 pd_flags;\n};\n\nstruct device_link;\n\nstruct dev_pm_domain_list {\n\tstruct device **pd_devs;\n\tstruct device_link **pd_links;\n\tu32 *opp_tokens;\n\tu32 num_pds;\n};\n\nstruct opp_table;\n\nstruct dev_pm_opp;\n\ntypedef int (*config_clks_t)(struct device *, struct opp_table *, struct dev_pm_opp *, void *, bool);\n\ntypedef int (*config_regulators_t)(struct device *, struct dev_pm_opp *, struct dev_pm_opp *, struct regulator **, unsigned int);\n\nstruct dev_pm_opp_config {\n\tconst char * const *clk_names;\n\tconfig_clks_t config_clks;\n\tconst char *prop_name;\n\tconfig_regulators_t config_regulators;\n\tconst unsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char * const *regulator_names;\n\tstruct device *required_dev;\n\tunsigned int required_dev_index;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\nstruct dev_table_entry {\n\tunion {\n\t\tu64 data[4];\n\t\tu128 data128[2];\n\t};\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct dmar_domain;\n\nstruct pasid_table;\n\nstruct device_domain_info {\n\tstruct list_head link;\n\tu32 segment;\n\tu8 bus;\n\tu8 devfn;\n\tu16 pfsid;\n\tu8 pasid_supported: 3;\n\tu8 pasid_enabled: 1;\n\tu8 pri_supported: 1;\n\tu8 pri_enabled: 1;\n\tu8 ats_supported: 1;\n\tu8 ats_enabled: 1;\n\tu8 dtlb_extra_inval: 1;\n\tu8 domain_attached: 1;\n\tu8 ats_qdep;\n\tunsigned int iopf_refcount;\n\tstruct device *dev;\n\tstruct intel_iommu *iommu;\n\tstruct dmar_domain *domain;\n\tstruct pasid_table *pasid_table;\n\tstruct rb_node node;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devid_map {\n\tstruct list_head list;\n\tu8 id;\n\tu32 devid;\n\tbool cmd_line;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n};\n\nstruct devlink;\n\nstruct ib_device;\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_linecard;\n\nstruct devlink_port_ops;\n\nstruct devlink_rate;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nunion dfixed {\n\tu32 full;\n};\n\ntypedef union dfixed fixed20_12;\n\nstruct dg2_snps_phy_buf_trans {\n\tu8 vswing;\n\tu8 pre_cursor;\n\tu8 post_cursor;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct dirty_throttle_control {\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct disk_comp_opts {\n\t__le32 dictionary_size;\n\t__le32 flags;\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct displayid_block {\n\tu8 tag;\n\tu8 rev;\n\tu8 num_bytes;\n};\n\nstruct displayid_detailed_timings_1 {\n\tu8 pixel_clock[3];\n\tu8 flags;\n\t__le16 hactive;\n\t__le16 hblank;\n\t__le16 hsync;\n\t__le16 hsw;\n\t__le16 vactive;\n\t__le16 vblank;\n\t__le16 vsync;\n\t__le16 vsw;\n};\n\nstruct displayid_detailed_timing_block {\n\tstruct displayid_block base;\n\tstruct displayid_detailed_timings_1 timings[0];\n} __attribute__((packed));\n\nstruct displayid_formula_timings_9 {\n\tu8 flags;\n\t__le16 hactive;\n\t__le16 vactive;\n\tu8 vrefresh;\n} __attribute__((packed));\n\nstruct displayid_formula_timing_block {\n\tstruct displayid_block base;\n\tstruct displayid_formula_timings_9 timings[0];\n};\n\nstruct displayid_header {\n\tu8 rev;\n\tu8 bytes;\n\tu8 prod_id;\n\tu8 ext_count;\n};\n\nstruct drm_edid_ident {\n\tu32 panel_id;\n\tconst char *name;\n};\n\nstruct displayid_quirk {\n\tconst struct drm_edid_ident ident;\n\tu8 quirks;\n};\n\nstruct displayid_tiled_block {\n\tstruct displayid_block base;\n\tu8 tile_cap;\n\tu8 topo[3];\n\tu8 tile_size[4];\n\tu8 tile_pixel_bezel[5];\n\tu8 topology_id[8];\n};\n\nstruct displayid_vesa_vendor_specific_block {\n\tstruct displayid_block base;\n\tu8 oui[3];\n\tu8 data_structure_type;\n\tu8 mso;\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\nstruct dm_arg {\n\tunsigned int min;\n\tunsigned int max;\n\tchar *error;\n};\n\nstruct dm_arg_set {\n\tunsigned int argc;\n\tchar **argv;\n};\n\nstruct dm_bio_details {\n\tstruct block_device *bi_bdev;\n\tint __bi_remaining;\n\tlong unsigned int bi_flags;\n\tstruct bvec_iter bi_iter;\n\tbio_end_io_t *bi_end_io;\n};\n\nstruct dm_blkdev_id {\n\tu8 *id;\n\tenum blk_unique_id type;\n};\n\nstruct dm_dev {\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct dax_device *dax_dev;\n\tblk_mode_t mode;\n\tchar name[16];\n};\n\nstruct dm_dev_internal {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev *dm_dev;\n};\n\nstruct dm_dirty_log_type;\n\nstruct dm_target;\n\nstruct dm_dirty_log {\n\tstruct dm_dirty_log_type *type;\n\tint (*flush_callback_fn)(struct dm_target *);\n\tvoid *context;\n};\n\nstruct dm_dirty_log_type {\n\tconst char *name;\n\tstruct module *module;\n\tstruct list_head list;\n\tint (*ctr)(struct dm_dirty_log *, struct dm_target *, unsigned int, char **);\n\tvoid (*dtr)(struct dm_dirty_log *);\n\tint (*presuspend)(struct dm_dirty_log *);\n\tint (*postsuspend)(struct dm_dirty_log *);\n\tint (*resume)(struct dm_dirty_log *);\n\tuint32_t (*get_region_size)(struct dm_dirty_log *);\n\tint (*is_clean)(struct dm_dirty_log *, region_t);\n\tint (*in_sync)(struct dm_dirty_log *, region_t, int);\n\tint (*flush)(struct dm_dirty_log *);\n\tvoid (*mark_region)(struct dm_dirty_log *, region_t);\n\tvoid (*clear_region)(struct dm_dirty_log *, region_t);\n\tint (*get_resync_work)(struct dm_dirty_log *, region_t *);\n\tvoid (*set_region_sync)(struct dm_dirty_log *, region_t, int);\n\tregion_t (*get_sync_count)(struct dm_dirty_log *);\n\tint (*status)(struct dm_dirty_log *, status_type_t, char *, unsigned int);\n\tint (*is_remote_recovering)(struct dm_dirty_log *, region_t);\n};\n\nstruct dm_file {\n\tvolatile unsigned int global_event_nr;\n};\n\nstruct dm_stats_aux {\n\tbool merged;\n\tlong long unsigned int duration_ns;\n};\n\nstruct dm_target_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tunsigned int target_bio_nr;\n\tstruct dm_io *io;\n\tstruct dm_target *ti;\n\tunsigned int *len_ptr;\n\tsector_t old_sector;\n\tstruct bio clone;\n};\n\nstruct mapped_device;\n\nstruct dm_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tspinlock_t lock;\n\tlong unsigned int start_time;\n\tvoid *data;\n\tstruct dm_io *next;\n\tstruct dm_stats_aux stats_aux;\n\tblk_status_t status;\n\tbool requeue_flush_with_data;\n\tatomic_t io_count;\n\tstruct mapped_device *md;\n\tstruct bio *orig_bio;\n\tunsigned int sector_offset;\n\tunsigned int sectors;\n\tstruct dm_target_io tio;\n};\n\nstruct dm_io_client {\n\tmempool_t pool;\n\tstruct bio_set bios;\n};\n\nstruct page_list;\n\nstruct dm_io_memory {\n\tenum dm_io_mem_type type;\n\tunsigned int offset;\n\tunion {\n\t\tstruct page_list *pl;\n\t\tstruct bio *bio;\n\t\tvoid *vma;\n\t\tvoid *addr;\n\t} ptr;\n};\n\ntypedef void (*io_notify_fn)(long unsigned int, void *);\n\nstruct dm_io_notify {\n\tio_notify_fn fn;\n\tvoid *context;\n};\n\nstruct dm_io_region {\n\tstruct block_device *bdev;\n\tsector_t sector;\n\tsector_t count;\n};\n\nstruct dm_io_request {\n\tblk_opf_t bi_opf;\n\tstruct dm_io_memory mem;\n\tstruct dm_io_notify notify;\n\tstruct dm_io_client *client;\n};\n\nstruct dm_ioctl {\n\t__u32 version[3];\n\t__u32 data_size;\n\t__u32 data_start;\n\t__u32 target_count;\n\t__s32 open_count;\n\t__u32 flags;\n\t__u32 event_nr;\n\t__u32 padding;\n\t__u64 dev;\n\tchar name[128];\n\tchar uuid[129];\n\tchar data[7];\n};\n\nstruct dm_kcopyd_throttle;\n\nstruct dm_kcopyd_client {\n\tstruct page_list *pages;\n\tunsigned int nr_reserved_pages;\n\tunsigned int nr_free_pages;\n\tunsigned int sub_job_size;\n\tstruct dm_io_client *io_client;\n\twait_queue_head_t destroyq;\n\tmempool_t job_pool;\n\tstruct workqueue_struct *kcopyd_wq;\n\tstruct work_struct kcopyd_work;\n\tstruct dm_kcopyd_throttle *throttle;\n\tatomic_t nr_jobs;\n\tspinlock_t job_lock;\n\tstruct list_head callback_jobs;\n\tstruct list_head complete_jobs;\n\tstruct list_head io_jobs;\n\tstruct list_head pages_jobs;\n};\n\nstruct dm_kcopyd_throttle {\n\tunsigned int throttle;\n\tunsigned int num_io_jobs;\n\tunsigned int io_period;\n\tunsigned int total_period;\n\tunsigned int last_jiffies;\n};\n\nstruct dm_kobject_holder {\n\tstruct kobject kobj;\n\tstruct completion completion;\n};\n\nstruct dm_md_mempools {\n\tstruct bio_set bs;\n\tstruct bio_set io_bs;\n};\n\nstruct dm_name_list {\n\t__u64 dev;\n\t__u32 next;\n\tchar name[0];\n};\n\nstruct pr_keys;\n\nstruct pr_held_reservation;\n\nstruct dm_pr {\n\tu64 old_key;\n\tu64 new_key;\n\tu32 flags;\n\tbool abort;\n\tbool fail_early;\n\tint ret;\n\tenum pr_type type;\n\tstruct pr_keys *read_keys;\n\tstruct pr_held_reservation *rsv;\n};\n\nstruct mirror;\n\nstruct dm_raid1_bio_record {\n\tstruct mirror *m;\n\tstruct dm_bio_details details;\n\tregion_t write_region;\n};\n\nstruct dm_region_hash;\n\nstruct dm_region {\n\tstruct dm_region_hash *rh;\n\tregion_t key;\n\tint state;\n\tstruct list_head hash_list;\n\tstruct list_head list;\n\tatomic_t pending;\n\tstruct bio_list delayed_bios;\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct dm_region_hash {\n\tuint32_t region_size;\n\tunsigned int region_shift;\n\tstruct dm_dirty_log *log;\n\trwlock_t hash_lock;\n\tunsigned int mask;\n\tunsigned int nr_buckets;\n\tunsigned int prime;\n\tunsigned int shift;\n\tstruct list_head *buckets;\n\tint flush_failure;\n\tunsigned int max_recovery;\n\tspinlock_t region_lock;\n\tatomic_t recovery_in_flight;\n\tstruct list_head clean_regions;\n\tstruct list_head quiesced_regions;\n\tstruct list_head recovered_regions;\n\tstruct list_head failed_recovered_regions;\n\tstruct semaphore recovery_count;\n\tmempool_t region_pool;\n\tvoid *context;\n\tsector_t target_begin;\n\tvoid (*dispatch_bios)(void *, struct bio_list *);\n\tvoid (*wakeup_workers)(void *);\n\tvoid (*wakeup_all_recovery_waiters)(void *);\n};\n\nstruct dm_rq_target_io;\n\nstruct dm_rq_clone_bio_info {\n\tstruct bio *orig;\n\tstruct dm_rq_target_io *tio;\n\tstruct bio clone;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_worker;\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nunion map_info {\n\tvoid *ptr;\n};\n\nstruct dm_rq_target_io {\n\tstruct mapped_device *md;\n\tstruct dm_target *ti;\n\tstruct request *orig;\n\tstruct request *clone;\n\tstruct kthread_work work;\n\tblk_status_t error;\n\tunion map_info info;\n\tstruct dm_stats_aux stats_aux;\n\tlong unsigned int duration_jiffies;\n\tunsigned int n_sectors;\n\tunsigned int completed;\n};\n\nstruct dm_stat_percpu {\n\tlong long unsigned int sectors[2];\n\tlong long unsigned int ios[2];\n\tlong long unsigned int merges[2];\n\tlong long unsigned int ticks[2];\n\tlong long unsigned int io_ticks[2];\n\tlong long unsigned int io_ticks_total;\n\tlong long unsigned int time_in_queue;\n\tlong long unsigned int *histogram;\n};\n\nstruct dm_stat_shared {\n\tatomic_t in_flight[2];\n\tlong long unsigned int stamp;\n\tstruct dm_stat_percpu tmp;\n};\n\nstruct dm_stat {\n\tstruct list_head list_entry;\n\tint id;\n\tunsigned int stat_flags;\n\tsize_t n_entries;\n\tsector_t start;\n\tsector_t end;\n\tsector_t step;\n\tunsigned int n_histogram_entries;\n\tlong long unsigned int *histogram_boundaries;\n\tconst char *program_id;\n\tconst char *aux_data;\n\tstruct callback_head callback_head;\n\tsize_t shared_alloc_size;\n\tsize_t percpu_alloc_size;\n\tsize_t histogram_alloc_size;\n\tstruct dm_stat_percpu *stat_percpu[64];\n\tstruct dm_stat_shared stat_shared[0];\n};\n\nstruct dm_stats_last_position;\n\nstruct dm_stats {\n\tstruct mutex mutex;\n\tstruct list_head list;\n\tstruct dm_stats_last_position *last;\n\tbool precise_timestamps;\n};\n\nstruct dm_stats_last_position {\n\tsector_t last_sector;\n\tunsigned int last_rw;\n};\n\nstruct dm_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mapped_device *, char *);\n\tssize_t (*store)(struct mapped_device *, const char *, size_t);\n};\n\nstruct target_type;\n\nstruct dm_table {\n\tstruct mapped_device *md;\n\tenum dm_queue_mode type;\n\tunsigned int depth;\n\tunsigned int counts[16];\n\tsector_t *index[16];\n\tunsigned int num_targets;\n\tunsigned int num_allocated;\n\tsector_t *highs;\n\tstruct dm_target *targets;\n\tstruct target_type *immutable_target_type;\n\tbool integrity_supported: 1;\n\tbool singleton: 1;\n\tbool flush_bypasses_map: 1;\n\tblk_mode_t mode;\n\tstruct list_head devices;\n\tvoid (*event_fn)(void *);\n\tvoid *event_context;\n\tstruct dm_md_mempools *mempools;\n};\n\nstruct dm_target {\n\tstruct dm_table *table;\n\tstruct target_type *type;\n\tsector_t begin;\n\tsector_t len;\n\tuint32_t max_io_len;\n\tunsigned int num_flush_bios;\n\tunsigned int num_discard_bios;\n\tunsigned int num_secure_erase_bios;\n\tunsigned int num_write_zeroes_bios;\n\tunsigned int per_io_data_size;\n\tvoid *private;\n\tchar *error;\n\tbool flush_supported: 1;\n\tbool discards_supported: 1;\n\tbool zone_reset_all_supported: 1;\n\tbool max_discard_granularity: 1;\n\tbool limit_swap_bios: 1;\n\tbool emulate_zone_append: 1;\n\tbool accounts_remapped_io: 1;\n\tbool needs_bio_set_dev: 1;\n\tbool flush_bypasses_map: 1;\n\tbool mempool_needs_integrity: 1;\n};\n\nstruct dm_target_deps {\n\t__u32 count;\n\t__u32 padding;\n\t__u64 dev[0];\n};\n\nstruct dm_target_msg {\n\t__u64 sector;\n\tchar message[0];\n};\n\nstruct dm_target_spec {\n\t__u64 sector_start;\n\t__u64 length;\n\t__s32 status;\n\t__u32 next;\n\tchar target_type[16];\n};\n\nstruct dm_target_versions {\n\t__u32 next;\n\t__u32 version[3];\n\tchar name[0];\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nstruct dmaengine_result;\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dmaengine_unmap_data;\n\nstruct dma_descriptor_metadata_ops;\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_resv;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct dma_iova_state;\n\nstruct dma_buf_dma {\n\tstruct sg_table sgt;\n\tstruct dma_iova_state *state;\n\tsize_t size;\n};\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct dma_buf_export_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_import_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_buf_sg_table_wrapper {\n\tstruct sg_table *original;\n\tstruct sg_table wrapper;\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_chan___2 {\n\tint lock;\n\tconst char *device_id;\n};\n\nstruct dma_device;\n\nstruct dma_chan_dev;\n\nstruct dma_chan_percpu;\n\nstruct dma_router;\n\nstruct dma_chan {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan *chan;\n\tstruct device device;\n\tint dev_id;\n\tbool chan_dma_dev;\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_chan_tbl_ent {\n\tstruct dma_chan *chan;\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nstruct dma_vec;\n\nstruct dma_interleaved_template;\n\nstruct dma_slave_caps;\n\nstruct dma_slave_config;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan *);\n\tint (*device_router_config)(struct dma_chan *);\n\tvoid (*device_free_chan_resources)(struct dma_chan *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_peripheral_dma_vec)(struct dma_chan *, const struct dma_vec *, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan *, struct dma_interleaved_template *, long unsigned int);\n\tvoid (*device_caps)(struct dma_chan *, struct dma_slave_caps *);\n\tint (*device_config)(struct dma_chan *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan *);\n\tint (*device_resume)(struct dma_chan *);\n\tint (*device_terminate_all)(struct dma_chan *);\n\tvoid (*device_synchronize)(struct dma_chan *);\n\tenum dma_status (*device_tx_status)(struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_fence_array;\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n\tstruct dma_fence_array_cb callbacks[0];\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tstruct dma_fence *prev;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tunion {\n\t\tstruct dma_fence_cb cb;\n\t\tstruct irq_work work;\n\t};\n\tspinlock_t lock;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_fence_unwrap {\n\tstruct dma_fence *chain;\n\tstruct dma_fence *array;\n\tunsigned int index;\n};\n\nstruct dma_fence_work_ops {\n\tconst char *name;\n\tvoid (*work)(struct dma_fence_work *);\n\tvoid (*release)(struct dma_fence_work *);\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tstruct dma_resv_list *fences;\n};\n\nstruct dma_resv_iter {\n\tstruct dma_resv *obj;\n\tenum dma_resv_usage usage;\n\tstruct dma_fence *fence;\n\tenum dma_resv_usage fence_usage;\n\tunsigned int index;\n\tstruct dma_resv_list *fences;\n\tunsigned int num_fences;\n\tbool is_restarted;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 num_fences;\n\tu32 max_fences;\n\tstruct dma_fence *table[0];\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_sgt_handle {\n\tstruct sg_table sgt;\n\tstruct page **pages;\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_vec {\n\tdma_addr_t addr;\n\tsize_t len;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct net_devmem_dmabuf_binding;\n\nstruct dmabuf_genpool_chunk_owner {\n\tstruct net_iov_area area;\n\tstruct net_devmem_dmabuf_binding *binding;\n\tdma_addr_t base_dma_addr;\n};\n\nstruct dmabuf_iter_priv {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmaengine_desc_callback {\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\nstruct dmaengine_unmap_data {\n\tu8 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dmaengine_unmap_pool {\n\tstruct kmem_cache *cache;\n\tconst char *name;\n\tmempool_t *pool;\n\tsize_t size;\n};\n\nstruct dmar_dev_scope;\n\nstruct dmar_atsr_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n\tu8 include_all: 1;\n};\n\nstruct dmar_dev_scope {\n\tstruct device *dev;\n\tu8 bus;\n\tu8 devfn;\n};\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommufd_hw_pagetable;\n\nstruct iommu_domain;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_ops;\n\nstruct iommu_dirty_ops;\n\nstruct iopf_group;\n\nstruct iommu_dma_cookie;\n\nstruct iommu_dma_msi_cookie;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct pt_iommu_ops;\n\nstruct pt_iommu_driver_ops;\n\nstruct pt_iommu {\n\tstruct iommu_domain domain;\n\tconst struct pt_iommu_ops *ops;\n\tconst struct pt_iommu_driver_ops *driver_ops;\n\tint nid;\n\tstruct device *iommu_device;\n};\n\nstruct pt_common {\n\tuintptr_t top_of_table;\n\tu8 max_oasz_lg2;\n\tu8 max_vasz_lg2;\n\tunsigned int features;\n};\n\nstruct pt_x86_64 {\n\tstruct pt_common common;\n};\n\nstruct pt_iommu_x86_64 {\n\tstruct pt_iommu iommu;\n\tstruct pt_x86_64 x86_64_pt;\n};\n\nstruct pt_vtdss {\n\tstruct pt_common common;\n};\n\nstruct pt_iommu_vtdss {\n\tstruct pt_iommu iommu;\n\tstruct pt_vtdss vtdss_pt;\n};\n\nstruct iommu_hwpt_vtd_s1 {\n\t__u64 flags;\n\t__u64 pgtbl_addr;\n\t__u32 addr_width;\n\t__u32 __reserved;\n};\n\nstruct mmu_notifier_ops;\n\nstruct mmu_notifier {\n\tstruct hlist_node hlist;\n\tconst struct mmu_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct callback_head rcu;\n\tunsigned int users;\n};\n\nstruct qi_batch;\n\nstruct dmar_domain {\n\tunion {\n\t\tstruct iommu_domain domain;\n\t\tstruct pt_iommu iommu;\n\t\tstruct pt_iommu_x86_64 fspt;\n\t\tstruct pt_iommu_vtdss sspt;\n\t};\n\tstruct xarray iommu_array;\n\tu8 force_snooping: 1;\n\tu8 dirty_tracking: 1;\n\tu8 nested_parent: 1;\n\tu8 iotlb_sync_map: 1;\n\tspinlock_t lock;\n\tstruct list_head devices;\n\tstruct list_head dev_pasids;\n\tspinlock_t cache_lock;\n\tstruct list_head cache_tags;\n\tstruct qi_batch *qi_batch;\n\tunion {\n\t\tstruct {\n\t\t\tspinlock_t s1_lock;\n\t\t\tstruct list_head s1_domains;\n\t\t};\n\t\tstruct {\n\t\t\tstruct dmar_domain *s2_domain;\n\t\t\tstruct iommu_hwpt_vtd_s1 s1_cfg;\n\t\t\tstruct list_head s2_link;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mmu_notifier notifier;\n\t\t};\n\t};\n};\n\nstruct dmar_drhd_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tu64 reg_base_addr;\n\tlong unsigned int reg_size;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n\tu16 segment;\n\tu8 ignored: 1;\n\tu8 include_all: 1;\n\tu8 gfx_dedicated: 1;\n\tstruct intel_iommu *iommu;\n};\n\nstruct dmar_pci_path {\n\tu8 bus;\n\tu8 device;\n\tu8 function;\n};\n\nstruct dmar_pci_notify_info {\n\tstruct pci_dev *dev;\n\tlong unsigned int event;\n\tint bus;\n\tu16 seg;\n\tu16 level;\n\tstruct dmar_pci_path path[0];\n};\n\ntypedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);\n\nstruct dmar_res_callback {\n\tdmar_res_handler_t cb[7];\n\tvoid *arg[7];\n\tbool ignore_unhandled;\n\tbool print_entry;\n};\n\nstruct dmar_rmrr_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tu64 base_address;\n\tu64 end_address;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n};\n\nstruct dmar_satc_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tstruct dmar_dev_scope *devices;\n\tstruct intel_iommu *iommu;\n\tint devices_cnt;\n\tu8 atc_required: 1;\n};\n\nstruct dmc_fw_info {\n\tu32 mmio_count;\n\ti915_reg_t mmioaddr[20];\n\tu32 mmiodata[20];\n\tu32 dmc_offset;\n\tu32 start_mmioaddr;\n\tu32 dmc_fw_size;\n\tu32 *payload;\n\tbool present;\n};\n\nstruct dmi_device {\n\tstruct list_head list;\n\tint type;\n\tconst char *name;\n\tvoid *device_data;\n};\n\nstruct dmi_dev_onboard {\n\tstruct dmi_device dev;\n\tint instance;\n\tint segment;\n\tint bus;\n\tint devfn;\n};\n\nstruct dmi_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint field;\n};\n\nstruct dmi_header {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n};\n\nstruct dmi_memdev_info {\n\tconst char *device;\n\tconst char *bank;\n\tu64 size;\n\tu16 handle;\n\tu8 type;\n};\n\nstruct dmi_onboard_device_info {\n\tconst char *name;\n\tu8 type;\n\tshort unsigned int i2c_addr;\n\tconst char *i2c_type;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct dock_dependent_device {\n\tstruct list_head list;\n\tstruct acpi_device *adev;\n};\n\nstruct dock_station {\n\tacpi_handle handle;\n\tlong unsigned int last_dock_time;\n\tu32 flags;\n\tstruct list_head dependent_devices;\n\tstruct list_head sibling;\n\tstruct platform_device *dock_device;\n};\n\nstruct dotl_iattr_map {\n\tint iattr_valid;\n\tint p9_iattr_valid;\n};\n\nstruct dotl_openflag_map {\n\tint open_flag;\n\tint dotl_flag;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct drm_edp_backlight_info {\n\tu8 pwmgen_bit_count;\n\tu8 pwm_freq_pre_divider;\n\tu32 max;\n\tbool lsb_reg_used: 1;\n\tbool aux_enable: 1;\n\tbool aux_set: 1;\n\tbool luminance_set: 1;\n};\n\nstruct drm_dp_aux;\n\nstruct dp_aux_backlight {\n\tstruct backlight_device *base;\n\tstruct drm_dp_aux *aux;\n\tstruct drm_edp_backlight_info info;\n\tbool enabled;\n};\n\nstruct dp_sdp_header {\n\tu8 HB0;\n\tu8 HB1;\n\tu8 HB2;\n\tu8 HB3;\n};\n\nstruct dp_sdp {\n\tstruct dp_sdp_header sdp_header;\n\tu8 db[32];\n};\n\nstruct dpages {\n\tvoid (*get_page)(struct dpages *, struct page **, long unsigned int *, unsigned int *);\n\tvoid (*next_page)(struct dpages *);\n\tunion {\n\t\tunsigned int context_u;\n\t\tstruct bvec_iter context_bi;\n\t};\n\tvoid *context_ptr;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n};\n\nstruct dpcd_quirk {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tbool is_branch;\n\tu32 quirks;\n};\n\nstruct dpll {\n\tint n;\n\tint m1;\n\tint m2;\n\tint p1;\n\tint p2;\n\tint dot;\n\tint vco;\n\tint m;\n\tint p;\n};\n\nstruct intel_dpll_funcs;\n\nstruct dpll_info {\n\tconst char *name;\n\tconst struct intel_dpll_funcs *funcs;\n\tenum intel_dpll_id id;\n\tenum intel_display_power_domain power_domain;\n\tbool always_on;\n\tbool is_alt_port_dpll;\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 64;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n};\n\nstruct dqstats {\n\tlong unsigned int stat[8];\n\tstruct percpu_counter counter[8];\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct dquot_warn {\n\tstruct super_block *w_sb;\n\tstruct kqid w_dq_id;\n\tshort int w_type;\n};\n\nstruct dram_dimm_info {\n\tu16 size;\n\tu8 width;\n\tu8 ranks;\n};\n\nstruct dram_channel_info {\n\tstruct dram_dimm_info dimm_l;\n\tstruct dram_dimm_info dimm_s;\n\tu8 ranks;\n\tbool is_16gb_dimm;\n};\n\nstruct dram_info {\n\tenum intel_dram_type type;\n\tunsigned int fsb_freq;\n\tunsigned int mem_freq;\n\tu8 num_channels;\n\tu8 num_qgv_points;\n\tu8 num_psf_gv_points;\n\tbool ecc_impacting_de_bw;\n\tbool symmetric_memory;\n\tbool has_16gb_dimms;\n};\n\nstruct drbg_core {\n\tdrbg_flag_t flags;\n\t__u8 statelen;\n\t__u8 blocklen_bytes;\n\tchar cra_name[128];\n\tchar backend_cra_name[128];\n};\n\nstruct drbg_string {\n\tconst unsigned char *buf;\n\tsize_t len;\n\tstruct list_head list;\n};\n\nstruct drbg_state_ops;\n\nstruct drbg_state {\n\tstruct mutex drbg_mutex;\n\tunsigned char *V;\n\tunsigned char *Vbuf;\n\tunsigned char *C;\n\tunsigned char *Cbuf;\n\tsize_t reseed_ctr;\n\tsize_t reseed_threshold;\n\tunsigned char *scratchpad;\n\tunsigned char *scratchpadbuf;\n\tvoid *priv_data;\n\tstruct crypto_skcipher *ctr_handle;\n\tstruct skcipher_request *ctr_req;\n\t__u8 *outscratchpadbuf;\n\t__u8 *outscratchpad;\n\tstruct crypto_wait ctr_wait;\n\tstruct scatterlist sg_in;\n\tstruct scatterlist sg_out;\n\tenum drbg_seed_state seeded;\n\tlong unsigned int last_seed_time;\n\tbool pr;\n\tbool fips_primed;\n\tunsigned char *prev;\n\tstruct crypto_rng *jent;\n\tconst struct drbg_state_ops *d_ops;\n\tconst struct drbg_core *core;\n\tstruct drbg_string test_data;\n};\n\nstruct drbg_state_ops {\n\tint (*update)(struct drbg_state *, struct list_head *, int);\n\tint (*generate)(struct drbg_state *, unsigned char *, unsigned int, struct list_head *);\n\tint (*crypto_init)(struct drbg_state *);\n\tint (*crypto_fini)(struct drbg_state *);\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drm_format_info;\n\nstruct drm_framebuffer_funcs;\n\nstruct drm_gem_object;\n\nstruct drm_framebuffer {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar comm[16];\n\tconst struct drm_format_info *format;\n\tconst struct drm_framebuffer_funcs *funcs;\n\tunsigned int pitches[4];\n\tunsigned int offsets[4];\n\tuint64_t modifier;\n\tunsigned int width;\n\tunsigned int height;\n\tint flags;\n\tunsigned int internal_flags;\n\tstruct list_head filp_head;\n\tstruct drm_gem_object *obj[4];\n};\n\nstruct drm_afbc_framebuffer {\n\tstruct drm_framebuffer base;\n\tu32 block_width;\n\tu32 block_height;\n\tu32 aligned_width;\n\tu32 aligned_height;\n\tu32 offset;\n\tu32 afbc_size;\n};\n\nstruct drm_rect {\n\tint x1;\n\tint y1;\n\tint x2;\n\tint y2;\n};\n\nstruct drm_atomic_helper_damage_iter {\n\tstruct drm_rect plane_src;\n\tconst struct drm_rect *clips;\n\tuint32_t num_clips;\n\tuint32_t curr_clip;\n\tbool full_update;\n};\n\nstruct drm_atomic_state {\n\tstruct kref ref;\n\tstruct drm_device *dev;\n\tbool allow_modeset: 1;\n\tbool legacy_cursor_update: 1;\n\tbool async_update: 1;\n\tbool duplicated: 1;\n\tbool checked: 1;\n\tbool plane_color_pipeline: 1;\n\tstruct __drm_colorops_state *colorops;\n\tstruct __drm_planes_state *planes;\n\tstruct __drm_crtcs_state *crtcs;\n\tint num_connector;\n\tstruct __drm_connnectors_state *connectors;\n\tint num_private_objs;\n\tstruct __drm_private_objs_state *private_objs;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct drm_crtc_commit *fake_commit;\n\tstruct work_struct commit_work;\n};\n\nstruct drm_audio_component_ops;\n\nstruct drm_audio_component_audio_ops;\n\nstruct drm_audio_component {\n\tstruct device *dev;\n\tconst struct drm_audio_component_ops *ops;\n\tconst struct drm_audio_component_audio_ops *audio_ops;\n\tstruct completion master_bind_complete;\n};\n\nstruct drm_audio_component_audio_ops {\n\tvoid *audio_ptr;\n\tvoid (*pin_eld_notify)(void *, int, int);\n\tint (*pin2port)(void *, int);\n\tint (*master_bind)(struct device *, struct drm_audio_component *);\n\tvoid (*master_unbind)(struct device *, struct drm_audio_component *);\n};\n\nstruct drm_audio_component_ops {\n\tstruct module *owner;\n\tlong unsigned int (*get_power)(struct device *);\n\tvoid (*put_power)(struct device *, long unsigned int);\n\tvoid (*codec_wake_override)(struct device *, bool);\n\tint (*get_cdclk_freq)(struct device *);\n\tint (*sync_audio_rate)(struct device *, int, int, int);\n\tint (*get_eld)(struct device *, int, int, bool *, unsigned char *, int);\n};\n\nstruct drm_auth {\n\tdrm_magic_t magic;\n};\n\nstruct drm_private_state_funcs;\n\nstruct drm_private_obj {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_modeset_lock lock;\n\tstruct drm_private_state *state;\n\tconst struct drm_private_state_funcs *funcs;\n};\n\nstruct drm_bridge_timings;\n\nstruct drm_bridge_funcs;\n\nstruct drm_bridge {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tstruct drm_encoder *encoder;\n\tstruct list_head chain_node;\n\tstruct device_node *of_node;\n\tstruct list_head list;\n\tconst struct drm_bridge_timings *timings;\n\tconst struct drm_bridge_funcs *funcs;\n\tvoid *container;\n\tstruct kref refcount;\n\tbool unplugged;\n\tvoid *driver_private;\n\tenum drm_bridge_ops ops;\n\tint type;\n\tbool interlace_allowed;\n\tbool ycbcr_420_allowed;\n\tbool pre_enable_prev_first;\n\tbool support_hdcp;\n\tstruct i2c_adapter *ddc;\n\tconst char *vendor;\n\tconst char *product;\n\tunsigned int supported_formats;\n\tunsigned int max_bpc;\n\tstruct device *hdmi_cec_dev;\n\tstruct device *hdmi_audio_dev;\n\tint hdmi_audio_max_i2s_playback_channels;\n\tu64 hdmi_audio_i2s_formats;\n\tunsigned int hdmi_audio_spdif_playback: 1;\n\tint hdmi_audio_dai_port;\n\tconst char *hdmi_cec_adapter_name;\n\tu8 hdmi_cec_available_las;\n\tstruct mutex hpd_mutex;\n\tvoid (*hpd_cb)(void *, enum drm_connector_status);\n\tvoid *hpd_data;\n\tstruct drm_bridge *next_bridge;\n};\n\nstruct hdmi_codec_daifmt;\n\nstruct hdmi_codec_params;\n\nstruct drm_bridge_state;\n\nstruct drm_bridge_funcs {\n\tint (*attach)(struct drm_bridge *, struct drm_encoder *, enum drm_bridge_attach_flags);\n\tvoid (*destroy)(struct drm_bridge *);\n\tvoid (*detach)(struct drm_bridge *);\n\tenum drm_mode_status (*mode_valid)(struct drm_bridge *, const struct drm_display_info *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_bridge *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*disable)(struct drm_bridge *);\n\tvoid (*post_disable)(struct drm_bridge *);\n\tvoid (*mode_set)(struct drm_bridge *, const struct drm_display_mode *, const struct drm_display_mode *);\n\tvoid (*pre_enable)(struct drm_bridge *);\n\tvoid (*enable)(struct drm_bridge *);\n\tvoid (*atomic_pre_enable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_post_disable)(struct drm_bridge *, struct drm_atomic_state *);\n\tstruct drm_bridge_state * (*atomic_duplicate_state)(struct drm_bridge *);\n\tvoid (*atomic_destroy_state)(struct drm_bridge *, struct drm_bridge_state *);\n\tu32 * (*atomic_get_output_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, unsigned int *);\n\tu32 * (*atomic_get_input_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, u32, unsigned int *);\n\tint (*atomic_check)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *);\n\tstruct drm_bridge_state * (*atomic_reset)(struct drm_bridge *);\n\tenum drm_connector_status (*detect)(struct drm_bridge *, struct drm_connector *);\n\tint (*get_modes)(struct drm_bridge *, struct drm_connector *);\n\tconst struct drm_edid * (*edid_read)(struct drm_bridge *, struct drm_connector *);\n\tvoid (*hpd_notify)(struct drm_bridge *, struct drm_connector *, enum drm_connector_status);\n\tvoid (*hpd_enable)(struct drm_bridge *);\n\tvoid (*hpd_disable)(struct drm_bridge *);\n\tenum drm_mode_status (*hdmi_tmds_char_rate_valid)(const struct drm_bridge *, const struct drm_display_mode *, long long unsigned int);\n\tint (*hdmi_clear_avi_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_avi_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_hdmi_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_hdmi_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_hdr_drm_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_hdr_drm_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_spd_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_spd_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_audio_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_audio_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_audio_startup)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_audio_prepare)(struct drm_bridge *, struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*hdmi_audio_shutdown)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_audio_mute_stream)(struct drm_bridge *, struct drm_connector *, bool, int);\n\tint (*hdmi_cec_init)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_cec_enable)(struct drm_bridge *, bool);\n\tint (*hdmi_cec_log_addr)(struct drm_bridge *, u8);\n\tint (*hdmi_cec_transmit)(struct drm_bridge *, u8, u32, struct cec_msg *);\n\tint (*dp_audio_startup)(struct drm_bridge *, struct drm_connector *);\n\tint (*dp_audio_prepare)(struct drm_bridge *, struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*dp_audio_shutdown)(struct drm_bridge *, struct drm_connector *);\n\tint (*dp_audio_mute_stream)(struct drm_bridge *, struct drm_connector *, bool, int);\n\tvoid (*debugfs_init)(struct drm_bridge *, struct dentry *);\n};\n\nstruct drm_private_state {\n\tstruct drm_atomic_state *state;\n\tstruct drm_private_obj *obj;\n};\n\nstruct drm_bus_cfg {\n\tu32 format;\n\tu32 flags;\n};\n\nstruct drm_bridge_state {\n\tstruct drm_private_state base;\n\tstruct drm_bridge *bridge;\n\tstruct drm_bus_cfg input_bus_cfg;\n\tstruct drm_bus_cfg output_bus_cfg;\n};\n\nstruct drm_bridge_timings {\n\tu32 input_bus_flags;\n\tu32 setup_time_ps;\n\tu32 hold_time_ps;\n\tbool dual_link;\n};\n\nstruct drm_buddy_block;\n\nstruct drm_buddy {\n\tstruct rb_root **free_trees;\n\tstruct drm_buddy_block **roots;\n\tunsigned int n_roots;\n\tunsigned int max_order;\n\tu64 chunk_size;\n\tu64 size;\n\tu64 avail;\n\tu64 clear_avail;\n};\n\nstruct drm_buddy_block {\n\tu64 header;\n\tstruct drm_buddy_block *left;\n\tstruct drm_buddy_block *right;\n\tstruct drm_buddy_block *parent;\n\tvoid *private;\n\tunion {\n\t\tstruct rb_node rb;\n\t\tstruct list_head link;\n\t};\n\tstruct list_head tmp_link;\n};\n\nstruct drm_client {\n\tint idx;\n\tint auth;\n\tlong unsigned int pid;\n\tlong unsigned int uid;\n\tlong unsigned int magic;\n\tlong unsigned int iocs;\n};\n\nstruct drm_client32 {\n\tint idx;\n\tint auth;\n\tu32 pid;\n\tu32 uid;\n\tu32 magic;\n\tu32 iocs;\n};\n\ntypedef struct drm_client32 drm_client32_t;\n\nstruct drm_clip_rect {\n\tshort unsigned int x1;\n\tshort unsigned int y1;\n\tshort unsigned int x2;\n\tshort unsigned int y2;\n};\n\nstruct drm_color_ctm {\n\t__u64 matrix[9];\n};\n\nstruct drm_color_ctm_3x4 {\n\t__u64 matrix[12];\n};\n\nstruct drm_color_lut {\n\t__u16 red;\n\t__u16 green;\n\t__u16 blue;\n\t__u16 reserved;\n};\n\nstruct drm_color_lut32 {\n\t__u32 red;\n\t__u32 green;\n\t__u32 blue;\n\t__u32 reserved;\n};\n\nstruct drm_colorop {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tunsigned int index;\n\tstruct drm_mode_object base;\n\tstruct drm_plane *plane;\n\tstruct drm_colorop_state *state;\n\tstruct drm_object_properties properties;\n\tenum drm_colorop_type type;\n\tstruct drm_colorop *next;\n\tstruct drm_property *type_property;\n\tstruct drm_property *bypass_property;\n\tuint32_t size;\n\tenum drm_colorop_lut1d_interpolation_type lut1d_interpolation;\n\tenum drm_colorop_lut3d_interpolation_type lut3d_interpolation;\n\tstruct drm_property *lut1d_interpolation_property;\n\tstruct drm_property *curve_1d_type_property;\n\tstruct drm_property *multiplier_property;\n\tstruct drm_property *size_property;\n\tstruct drm_property *lut3d_interpolation_property;\n\tstruct drm_property *data_property;\n\tstruct drm_property *next_property;\n};\n\nstruct drm_colorop_state {\n\tstruct drm_colorop *colorop;\n\tbool bypass;\n\tenum drm_colorop_curve_1d_type curve_1d_type;\n\tuint64_t multiplier;\n\tstruct drm_property_blob *data;\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_conn_prop_enum_list {\n\tint type;\n\tconst char *name;\n\tstruct ida ida;\n};\n\nstruct drm_connector_cec_funcs {\n\tvoid (*phys_addr_invalidate)(struct drm_connector *);\n\tvoid (*phys_addr_set)(struct drm_connector *, u16);\n};\n\nstruct drm_printer;\n\nstruct drm_connector_funcs {\n\tint (*dpms)(struct drm_connector *, int);\n\tvoid (*reset)(struct drm_connector *);\n\tenum drm_connector_status (*detect)(struct drm_connector *, bool);\n\tvoid (*force)(struct drm_connector *);\n\tint (*fill_modes)(struct drm_connector *, uint32_t, uint32_t);\n\tint (*set_property)(struct drm_connector *, struct drm_property *, uint64_t);\n\tint (*late_register)(struct drm_connector *);\n\tvoid (*early_unregister)(struct drm_connector *);\n\tvoid (*destroy)(struct drm_connector *);\n\tstruct drm_connector_state * (*atomic_duplicate_state)(struct drm_connector *);\n\tvoid (*atomic_destroy_state)(struct drm_connector *, struct drm_connector_state *);\n\tint (*atomic_set_property)(struct drm_connector *, struct drm_connector_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_connector *, const struct drm_connector_state *, struct drm_property *, uint64_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_connector_state *);\n\tvoid (*oob_hotplug_event)(struct drm_connector *, enum drm_connector_status);\n\tvoid (*debugfs_init)(struct drm_connector *, struct dentry *);\n};\n\nstruct drm_connector_hdmi_audio_funcs {\n\tint (*startup)(struct drm_connector *);\n\tint (*prepare)(struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*shutdown)(struct drm_connector *);\n\tint (*mute_stream)(struct drm_connector *, bool, int);\n};\n\nstruct drm_connector_infoframe_funcs {\n\tint (*clear_infoframe)(struct drm_connector *);\n\tint (*write_infoframe)(struct drm_connector *, const u8 *, size_t);\n};\n\nstruct drm_connector_hdmi_funcs {\n\tenum drm_mode_status (*tmds_char_rate_valid)(const struct drm_connector *, const struct drm_display_mode *, long long unsigned int);\n\tconst struct drm_edid * (*read_edid)(struct drm_connector *);\n\tstruct drm_connector_infoframe_funcs avi;\n\tstruct drm_connector_infoframe_funcs hdmi;\n\tstruct drm_connector_infoframe_funcs audio;\n\tstruct drm_connector_infoframe_funcs hdr_drm;\n\tstruct drm_connector_infoframe_funcs spd;\n};\n\nstruct drm_connector_hdmi_state {\n\tenum drm_hdmi_broadcast_rgb broadcast_rgb;\n\tstruct {\n\t\tstruct drm_connector_hdmi_infoframe avi;\n\t\tstruct drm_connector_hdmi_infoframe hdr_drm;\n\t\tstruct drm_connector_hdmi_infoframe spd;\n\t\tstruct drm_connector_hdmi_infoframe hdmi;\n\t} infoframes;\n\tbool is_limited_range;\n\tunsigned int output_bpc;\n\tenum hdmi_colorspace output_format;\n\tlong long unsigned int tmds_char_rate;\n};\n\nstruct drm_writeback_connector;\n\nstruct drm_writeback_job;\n\nstruct drm_connector_helper_funcs {\n\tint (*get_modes)(struct drm_connector *);\n\tint (*detect_ctx)(struct drm_connector *, struct drm_modeset_acquire_ctx *, bool);\n\tenum drm_mode_status (*mode_valid)(struct drm_connector *, const struct drm_display_mode *);\n\tint (*mode_valid_ctx)(struct drm_connector *, const struct drm_display_mode *, struct drm_modeset_acquire_ctx *, enum drm_mode_status *);\n\tstruct drm_encoder * (*best_encoder)(struct drm_connector *);\n\tstruct drm_encoder * (*atomic_best_encoder)(struct drm_connector *, struct drm_atomic_state *);\n\tint (*atomic_check)(struct drm_connector *, struct drm_atomic_state *);\n\tvoid (*atomic_commit)(struct drm_connector *, struct drm_atomic_state *);\n\tint (*prepare_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n\tvoid (*cleanup_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n\tvoid (*enable_hpd)(struct drm_connector *);\n\tvoid (*disable_hpd)(struct drm_connector *);\n};\n\nstruct drm_connector_list_iter {\n\tstruct drm_device *dev;\n\tstruct drm_connector *conn;\n};\n\nstruct drm_tv_connector_state {\n\tenum drm_mode_subconnector select_subconnector;\n\tenum drm_mode_subconnector subconnector;\n\tstruct drm_connector_tv_margins margins;\n\tunsigned int legacy_mode;\n\tunsigned int mode;\n\tunsigned int brightness;\n\tunsigned int contrast;\n\tunsigned int flicker_reduction;\n\tunsigned int overscan;\n\tunsigned int saturation;\n\tunsigned int hue;\n};\n\nstruct drm_connector_state {\n\tstruct drm_connector *connector;\n\tstruct drm_crtc *crtc;\n\tstruct drm_encoder *best_encoder;\n\tenum drm_link_status link_status;\n\tstruct drm_atomic_state *state;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_tv_connector_state tv;\n\tbool self_refresh_aware;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n\tunsigned int content_type;\n\tunsigned int hdcp_content_type;\n\tunsigned int scaling_mode;\n\tunsigned int content_protection;\n\tenum drm_colorspace colorspace;\n\tstruct drm_writeback_job *writeback_job;\n\tu8 max_requested_bpc;\n\tu8 max_bpc;\n\tenum drm_privacy_screen_status privacy_screen_sw_state;\n\tstruct drm_property_blob *hdr_output_metadata;\n\tstruct drm_connector_hdmi_state hdmi;\n};\n\nstruct drm_pending_vblank_event;\n\nstruct drm_crtc_commit {\n\tstruct drm_crtc *crtc;\n\tstruct kref ref;\n\tstruct completion flip_done;\n\tstruct completion hw_done;\n\tstruct completion cleanup_done;\n\tstruct list_head commit_entry;\n\tstruct drm_pending_vblank_event *event;\n\tbool abort_completion;\n};\n\nstruct drm_crtc_crc_entry {\n\tbool has_frame_counter;\n\tuint32_t frame;\n\tuint32_t crcs[10];\n};\n\nstruct drm_file;\n\nstruct drm_mode_set;\n\nstruct drm_crtc_funcs {\n\tvoid (*reset)(struct drm_crtc *);\n\tint (*cursor_set)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t);\n\tint (*cursor_set2)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t, int32_t, int32_t);\n\tint (*cursor_move)(struct drm_crtc *, int, int);\n\tint (*gamma_set)(struct drm_crtc *, u16 *, u16 *, u16 *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_crtc *);\n\tint (*set_config)(struct drm_mode_set *, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip_target)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*set_property)(struct drm_crtc *, struct drm_property *, uint64_t);\n\tstruct drm_crtc_state * (*atomic_duplicate_state)(struct drm_crtc *);\n\tvoid (*atomic_destroy_state)(struct drm_crtc *, struct drm_crtc_state *);\n\tint (*atomic_set_property)(struct drm_crtc *, struct drm_crtc_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_crtc *, const struct drm_crtc_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_crtc *);\n\tvoid (*early_unregister)(struct drm_crtc *);\n\tint (*set_crc_source)(struct drm_crtc *, const char *);\n\tint (*verify_crc_source)(struct drm_crtc *, const char *, size_t *);\n\tconst char * const * (*get_crc_sources)(struct drm_crtc *, size_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_crtc_state *);\n\tu32 (*get_vblank_counter)(struct drm_crtc *);\n\tint (*enable_vblank)(struct drm_crtc *);\n\tvoid (*disable_vblank)(struct drm_crtc *);\n\tbool (*get_vblank_timestamp)(struct drm_crtc *, int *, ktime_t *, bool);\n};\n\nstruct drm_crtc_get_sequence {\n\t__u32 crtc_id;\n\t__u32 active;\n\t__u64 sequence;\n\t__s64 sequence_ns;\n};\n\nstruct drm_crtc_helper_funcs {\n\tvoid (*dpms)(struct drm_crtc *, int);\n\tvoid (*prepare)(struct drm_crtc *);\n\tvoid (*commit)(struct drm_crtc *);\n\tenum drm_mode_status (*mode_valid)(struct drm_crtc *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_crtc *, const struct drm_display_mode *, struct drm_display_mode *);\n\tint (*mode_set)(struct drm_crtc *, struct drm_display_mode *, struct drm_display_mode *, int, int, struct drm_framebuffer *);\n\tvoid (*mode_set_nofb)(struct drm_crtc *);\n\tint (*mode_set_base)(struct drm_crtc *, int, int, struct drm_framebuffer *);\n\tvoid (*disable)(struct drm_crtc *);\n\tint (*atomic_check)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_begin)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_flush)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_crtc *, struct drm_atomic_state *);\n\tbool (*get_scanout_position)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n\tbool (*handle_vblank_timeout)(struct drm_crtc *);\n};\n\nstruct drm_crtc_queue_sequence {\n\t__u32 crtc_id;\n\t__u32 flags;\n\t__u64 sequence;\n\t__u64 user_data;\n};\n\nstruct drm_crtc_state {\n\tstruct drm_crtc *crtc;\n\tbool enable;\n\tbool active;\n\tbool planes_changed: 1;\n\tbool mode_changed: 1;\n\tbool active_changed: 1;\n\tbool connectors_changed: 1;\n\tbool zpos_changed: 1;\n\tbool color_mgmt_changed: 1;\n\tbool no_vblank;\n\tu32 plane_mask;\n\tu32 connector_mask;\n\tu32 encoder_mask;\n\tstruct drm_display_mode adjusted_mode;\n\tstruct drm_display_mode mode;\n\tstruct drm_property_blob *mode_blob;\n\tstruct drm_property_blob *degamma_lut;\n\tstruct drm_property_blob *ctm;\n\tstruct drm_property_blob *gamma_lut;\n\tu32 target_vblank;\n\tbool async_flip;\n\tbool vrr_enabled;\n\tbool self_refresh_active;\n\tenum drm_scaling_filter scaling_filter;\n\tu8 sharpness_strength;\n\tstruct drm_pending_vblank_event *event;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_debugfs_info {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n\tu32 driver_features;\n\tvoid *data;\n};\n\nstruct drm_debugfs_entry {\n\tstruct drm_device *dev;\n\tstruct drm_debugfs_info file;\n\tstruct list_head list;\n};\n\nstruct drm_dmi_panel_orientation_data {\n\tint width;\n\tint height;\n\tconst char * const *bios_dates;\n\tint orientation;\n};\n\nstruct drm_dp_as_sdp {\n\tunsigned char sdp_type;\n\tunsigned char revision;\n\tunsigned char length;\n\tint vtotal;\n\tint target_rr;\n\tint duration_incr_ms;\n\tint duration_decr_ms;\n\tbool target_rr_divider;\n\tenum operation_mode mode;\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n\tstruct lockdep_map dep_map;\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n\tstruct regulator *bus_regulator;\n\tstruct dentry *debugfs;\n\tlong unsigned int addrs_in_instantiation[2];\n};\n\nstruct drm_dp_aux_cec {\n\tstruct mutex lock;\n\tstruct cec_adapter *adap;\n\tstruct drm_connector *connector;\n\tstruct delayed_work unregister_work;\n};\n\nstruct drm_dp_aux_msg;\n\nstruct drm_dp_aux {\n\tconst char *name;\n\tstruct i2c_adapter ddc;\n\tstruct device *dev;\n\tstruct drm_device *drm_dev;\n\tstruct drm_crtc *crtc;\n\tstruct mutex hw_mutex;\n\tstruct work_struct crc_work;\n\tu8 crc_count;\n\tssize_t (*transfer)(struct drm_dp_aux *, struct drm_dp_aux_msg *);\n\tint (*wait_hpd_asserted)(struct drm_dp_aux *, long unsigned int);\n\tunsigned int i2c_nack_count;\n\tunsigned int i2c_defer_count;\n\tstruct drm_dp_aux_cec cec;\n\tbool is_remote;\n\tbool powered_down;\n\tbool no_zero_sized;\n\tbool dpcd_probe_disabled;\n};\n\nstruct drm_dp_aux_msg {\n\tunsigned int address;\n\tu8 request;\n\tu8 reply;\n\tvoid *buffer;\n\tsize_t size;\n};\n\nstruct drm_dp_dpcd_ident {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tu8 hw_rev;\n\tu8 sw_major_rev;\n\tu8 sw_minor_rev;\n};\n\nstruct drm_dp_desc {\n\tstruct drm_dp_dpcd_ident ident;\n\tu32 quirks;\n};\n\nstruct drm_dp_mst_port;\n\nstruct drm_dp_mst_atomic_payload {\n\tstruct drm_dp_mst_port *port;\n\ts8 vc_start_slot;\n\tu8 vcpi;\n\tint time_slots;\n\tint pbn;\n\tbool delete: 1;\n\tbool dsc_enabled: 1;\n\tenum drm_dp_mst_payload_allocation payload_allocation_status;\n\tstruct list_head next;\n};\n\nstruct drm_dp_mst_topology_mgr;\n\nstruct drm_dp_mst_branch {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tstruct list_head destroy_next;\n\tu8 rad[8];\n\tu8 lct;\n\tint num_ports;\n\tstruct list_head ports;\n\tstruct drm_dp_mst_port *port_parent;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tbool link_address_sent;\n\tguid_t guid;\n};\n\nstruct drm_dp_mst_port {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tu8 port_num;\n\tbool input;\n\tbool mcs;\n\tbool ddps;\n\tu8 pdt;\n\tbool ldps;\n\tu8 dpcd_rev;\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n\tuint16_t full_pbn;\n\tstruct list_head next;\n\tstruct drm_dp_mst_branch *mstb;\n\tstruct drm_dp_aux aux;\n\tstruct drm_dp_aux *passthrough_aux;\n\tstruct drm_dp_mst_branch *parent;\n\tstruct drm_connector *connector;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tconst struct drm_edid *cached_edid;\n\tbool fec_capable;\n};\n\nstruct drm_dp_mst_topology_cbs {\n\tstruct drm_connector * (*add_connector)(struct drm_dp_mst_topology_mgr *, struct drm_dp_mst_port *, const char *);\n\tvoid (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *);\n};\n\nstruct drm_dp_sideband_msg_hdr {\n\tu8 lct;\n\tu8 lcr;\n\tu8 rad[8];\n\tbool broadcast;\n\tbool path_msg;\n\tu8 msg_len;\n\tbool somt;\n\tbool eomt;\n\tbool seqno;\n};\n\nstruct drm_dp_sideband_msg_rx {\n\tu8 chunk[48];\n\tu8 msg[256];\n\tu8 curchunk_len;\n\tu8 curchunk_idx;\n\tu8 curchunk_hdrlen;\n\tu8 curlen;\n\tbool have_somt;\n\tbool have_eomt;\n\tstruct drm_dp_sideband_msg_hdr initial_hdr;\n};\n\nstruct drm_dp_mst_topology_mgr {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tconst struct drm_dp_mst_topology_cbs *cbs;\n\tint max_dpcd_transaction_bytes;\n\tstruct drm_dp_aux *aux;\n\tint max_payloads;\n\tint conn_base_id;\n\tstruct drm_dp_sideband_msg_rx up_req_recv;\n\tstruct drm_dp_sideband_msg_rx down_rep_recv;\n\tstruct mutex lock;\n\tstruct mutex probe_lock;\n\tbool mst_state: 1;\n\tbool payload_id_table_cleared: 1;\n\tbool reset_rx_state: 1;\n\tu8 payload_count;\n\tu8 next_start_slot;\n\tstruct drm_dp_mst_branch *mst_primary;\n\tu8 dpcd[15];\n\tu8 sink_count;\n\tconst struct drm_private_state_funcs *funcs;\n\tstruct mutex qlock;\n\tstruct list_head tx_msg_downq;\n\twait_queue_head_t tx_waitq;\n\tstruct work_struct work;\n\tstruct work_struct tx_work;\n\tstruct list_head destroy_port_list;\n\tstruct list_head destroy_branch_device_list;\n\tstruct mutex delayed_destroy_lock;\n\tstruct workqueue_struct *delayed_destroy_wq;\n\tstruct work_struct delayed_destroy_work;\n\tstruct list_head up_req_list;\n\tstruct mutex up_req_lock;\n\tstruct work_struct up_req_work;\n};\n\nstruct drm_dp_mst_topology_state {\n\tstruct drm_private_state base;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tu32 pending_crtc_mask;\n\tstruct drm_crtc_commit **commit_deps;\n\tsize_t num_commit_deps;\n\tu32 payload_mask;\n\tstruct list_head payloads;\n\tu8 total_avail_slots;\n\tu8 start_slot;\n\tfixed20_12 pbn_div;\n};\n\nstruct drm_dp_sideband_msg_req_body {\n\tu8 req_type;\n\tunion ack_req u;\n};\n\nstruct drm_dp_pending_up_req {\n\tstruct drm_dp_sideband_msg_hdr hdr;\n\tstruct drm_dp_sideband_msg_req_body msg;\n\tstruct list_head next;\n};\n\nstruct drm_dp_phy_test_params {\n\tint link_rate;\n\tu8 num_lanes;\n\tu8 phy_pattern;\n\tu8 hbr2_reset[2];\n\tu8 custom80[10];\n\tbool enhanced_frame_cap;\n};\n\nstruct drm_dp_sideband_msg_reply_body {\n\tu8 reply_type;\n\tu8 req_type;\n\tunion ack_replies u;\n};\n\nstruct drm_dp_sideband_msg_tx {\n\tu8 msg[256];\n\tu8 chunk[48];\n\tu8 cur_offset;\n\tu8 cur_len;\n\tstruct drm_dp_mst_branch *dst;\n\tstruct list_head next;\n\tint seqno;\n\tint state;\n\tbool path_msg;\n\tstruct drm_dp_sideband_msg_reply_body reply;\n};\n\nstruct drm_dp_tunnel;\n\nstruct ref_tracker;\n\nstruct drm_dp_tunnel_ref {\n\tstruct drm_dp_tunnel *tunnel;\n\tstruct ref_tracker *tracker;\n};\n\nstruct drm_dp_vsc_sdp {\n\tunsigned char sdp_type;\n\tunsigned char revision;\n\tunsigned char length;\n\tenum dp_pixelformat pixelformat;\n\tenum dp_colorimetry colorimetry;\n\tint bpc;\n\tenum dp_dynamic_range dynamic_range;\n\tenum dp_content_type content_type;\n};\n\nstruct drm_fb_helper_surface_size;\n\nstruct drm_mode_create_dumb;\n\nstruct drm_ioctl_desc;\n\nstruct drm_driver {\n\tint (*load)(struct drm_device *, long unsigned int);\n\tint (*open)(struct drm_device *, struct drm_file *);\n\tvoid (*postclose)(struct drm_device *, struct drm_file *);\n\tvoid (*unload)(struct drm_device *);\n\tvoid (*release)(struct drm_device *);\n\tvoid (*master_set)(struct drm_device *, struct drm_file *, bool);\n\tvoid (*master_drop)(struct drm_device *, struct drm_file *);\n\tvoid (*debugfs_init)(struct drm_minor *);\n\tstruct drm_gem_object * (*gem_create_object)(struct drm_device *, size_t);\n\tint (*prime_handle_to_fd)(struct drm_device *, struct drm_file *, uint32_t, uint32_t, int *);\n\tint (*prime_fd_to_handle)(struct drm_device *, struct drm_file *, int, uint32_t *);\n\tstruct drm_gem_object * (*gem_prime_import)(struct drm_device *, struct dma_buf *);\n\tstruct drm_gem_object * (*gem_prime_import_sg_table)(struct drm_device *, struct dma_buf_attachment *, struct sg_table *);\n\tint (*dumb_create)(struct drm_file *, struct drm_device *, struct drm_mode_create_dumb *);\n\tint (*dumb_map_offset)(struct drm_file *, struct drm_device *, uint32_t, uint64_t *);\n\tint (*fbdev_probe)(struct drm_fb_helper *, struct drm_fb_helper_surface_size *);\n\tvoid (*show_fdinfo)(struct drm_printer *, struct drm_file *);\n\tint major;\n\tint minor;\n\tint patchlevel;\n\tchar *name;\n\tchar *desc;\n\tu32 driver_features;\n\tconst struct drm_ioctl_desc *ioctls;\n\tint num_ioctls;\n\tconst struct file_operations *fops;\n};\n\nstruct drm_dsc_rc_range_parameters {\n\tu8 range_min_qp;\n\tu8 range_max_qp;\n\tu8 range_bpg_offset;\n};\n\nstruct drm_dsc_config {\n\tu8 line_buf_depth;\n\tu8 bits_per_component;\n\tbool convert_rgb;\n\tu8 slice_count;\n\tu16 slice_width;\n\tu16 slice_height;\n\tbool simple_422;\n\tu16 pic_width;\n\tu16 pic_height;\n\tu8 rc_tgt_offset_high;\n\tu8 rc_tgt_offset_low;\n\tu16 bits_per_pixel;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_quant_incr_limit0;\n\tu16 initial_xmit_delay;\n\tu16 initial_dec_delay;\n\tbool block_pred_enable;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu16 rc_buf_thresh[14];\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n\tu16 rc_model_size;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 initial_scale_value;\n\tu16 scale_decrement_interval;\n\tu16 scale_increment_interval;\n\tu16 nfl_bpg_offset;\n\tu16 slice_bpg_offset;\n\tu16 final_offset;\n\tbool vbr_enable;\n\tu8 mux_word_size;\n\tu16 slice_chunk_size;\n\tu16 rc_bits;\n\tu8 dsc_version_minor;\n\tu8 dsc_version_major;\n\tbool native_422;\n\tbool native_420;\n\tu8 second_line_bpg_offset;\n\tu16 nsl_bpg_offset;\n\tu16 second_line_offset_adj;\n};\n\nstruct drm_dsc_picture_parameter_set {\n\tu8 dsc_version;\n\tu8 pps_identifier;\n\tu8 pps_reserved;\n\tu8 pps_3;\n\tu8 pps_4;\n\tu8 bits_per_pixel_low;\n\t__be16 pic_height;\n\t__be16 pic_width;\n\t__be16 slice_height;\n\t__be16 slice_width;\n\t__be16 chunk_size;\n\tu8 initial_xmit_delay_high;\n\tu8 initial_xmit_delay_low;\n\t__be16 initial_dec_delay;\n\tu8 pps20_reserved;\n\tu8 initial_scale_value;\n\t__be16 scale_increment_interval;\n\tu8 scale_decrement_interval_high;\n\tu8 scale_decrement_interval_low;\n\tu8 pps26_reserved;\n\tu8 first_line_bpg_offset;\n\t__be16 nfl_bpg_offset;\n\t__be16 slice_bpg_offset;\n\t__be16 initial_offset;\n\t__be16 final_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\t__be16 rc_model_size;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_tgt_offset;\n\tu8 rc_buf_thresh[14];\n\t__be16 rc_range_parameters[15];\n\tu8 native_422_420;\n\tu8 second_line_bpg_offset;\n\t__be16 nsl_bpg_offset;\n\t__be16 second_line_offset_adj;\n\tu32 pps_long_94_reserved;\n\tu32 pps_long_98_reserved;\n\tu32 pps_long_102_reserved;\n\tu32 pps_long_106_reserved;\n\tu32 pps_long_110_reserved;\n\tu32 pps_long_114_reserved;\n\tu32 pps_long_118_reserved;\n\tu32 pps_long_122_reserved;\n\t__be16 pps_short_126_reserved;\n} __attribute__((packed));\n\nstruct drm_dsc_pps_infoframe {\n\tstruct dp_sdp_header pps_header;\n\tstruct drm_dsc_picture_parameter_set pps_payload;\n};\n\nstruct edid;\n\nstruct drm_edid {\n\tsize_t size;\n\tconst struct edid *edid;\n};\n\nstruct drm_edid_match_closure {\n\tconst struct drm_edid_ident *ident;\n\tbool matched;\n};\n\nstruct drm_edid_product_id {\n\t__be16 manufacturer_name;\n\t__le16 product_code;\n\t__le32 serial_number;\n\tu8 week_of_manufacture;\n\tu8 year_of_manufacture;\n} __attribute__((packed));\n\nstruct drm_encoder_funcs {\n\tvoid (*reset)(struct drm_encoder *);\n\tvoid (*destroy)(struct drm_encoder *);\n\tint (*late_register)(struct drm_encoder *);\n\tvoid (*early_unregister)(struct drm_encoder *);\n\tvoid (*debugfs_init)(struct drm_encoder *, struct dentry *);\n};\n\nstruct drm_encoder_helper_funcs {\n\tvoid (*dpms)(struct drm_encoder *, int);\n\tenum drm_mode_status (*mode_valid)(struct drm_encoder *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_encoder *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*prepare)(struct drm_encoder *);\n\tvoid (*commit)(struct drm_encoder *);\n\tvoid (*mode_set)(struct drm_encoder *, struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*atomic_mode_set)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n\tenum drm_connector_status (*detect)(struct drm_encoder *, struct drm_connector *);\n\tvoid (*atomic_disable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*disable)(struct drm_encoder *);\n\tvoid (*enable)(struct drm_encoder *);\n\tint (*atomic_check)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n};\n\nstruct drm_event {\n\t__u32 type;\n\t__u32 length;\n};\n\nstruct drm_event_crtc_sequence {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__s64 time_ns;\n\t__u64 sequence;\n};\n\nstruct drm_event_vblank {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__u32 tv_sec;\n\t__u32 tv_usec;\n\t__u32 sequence;\n\t__u32 crtc_id;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n\tunsigned int done_acquire;\n\tstruct ww_class *ww_class;\n\tvoid *contending_lock;\n\tstruct lockdep_map dep_map;\n\tstruct lockdep_map first_lock_dep_map;\n\tunsigned int deadlock_inject_interval;\n\tunsigned int deadlock_inject_countdown;\n};\n\nstruct drm_exec {\n\tu32 flags;\n\tstruct ww_acquire_ctx ticket;\n\tunsigned int num_objects;\n\tunsigned int max_objects;\n\tstruct drm_gem_object **objects;\n\tstruct drm_gem_object *contended;\n\tstruct drm_gem_object *prelocked;\n};\n\nstruct drm_prime_file_private {\n\tstruct mutex lock;\n\tstruct rb_root dmabufs;\n\tstruct rb_root handles;\n};\n\nstruct drm_file {\n\tbool authenticated;\n\tbool stereo_allowed;\n\tbool universal_planes;\n\tbool atomic;\n\tbool aspect_ratio_allowed;\n\tbool writeback_connectors;\n\tbool plane_color_pipeline;\n\tbool was_master;\n\tbool is_master;\n\tbool supports_virtualized_cursor_plane;\n\tstruct drm_master *master;\n\tspinlock_t master_lookup_lock;\n\tstruct pid *pid;\n\tu64 client_id;\n\tdrm_magic_t magic;\n\tstruct list_head lhead;\n\tstruct drm_minor *minor;\n\tstruct idr object_idr;\n\tspinlock_t table_lock;\n\tstruct xarray syncobj_xa;\n\tstruct file *filp;\n\tvoid *driver_priv;\n\tstruct list_head fbs;\n\tstruct mutex fbs_lock;\n\tstruct list_head blobs;\n\twait_queue_head_t event_wait;\n\tstruct list_head pending_event_list;\n\tstruct list_head event_list;\n\tint event_space;\n\tstruct mutex event_read_lock;\n\tstruct drm_prime_file_private prime;\n\tconst char *client_name;\n\tstruct mutex client_name_lock;\n\tstruct dentry *debugfs_client;\n};\n\nstruct drm_flip_task {\n\tstruct list_head node;\n\tvoid *data;\n};\n\nstruct drm_flip_work;\n\ntypedef void (*drm_flip_func_t)(struct drm_flip_work *, void *);\n\nstruct drm_flip_work {\n\tconst char *name;\n\tdrm_flip_func_t func;\n\tstruct work_struct worker;\n\tstruct list_head queued;\n\tstruct list_head commited;\n\tspinlock_t lock;\n};\n\nstruct drm_format_conv_state {\n\tstruct {\n\t\tvoid *mem;\n\t\tsize_t size;\n\t\tbool preallocated;\n\t} tmp;\n};\n\nstruct drm_format_info {\n\tu32 format;\n\tu8 depth;\n\tu8 num_planes;\n\tunion {\n\t\tu8 cpp[4];\n\t\tu8 char_per_block[4];\n\t};\n\tu8 block_w[4];\n\tu8 block_h[4];\n\tu8 hsub;\n\tu8 vsub;\n\tbool has_alpha;\n\tbool is_yuv;\n\tbool is_color_indexed;\n};\n\nstruct drm_format_modifier {\n\t__u64 formats;\n\t__u32 offset;\n\t__u32 pad;\n\t__u64 modifier;\n};\n\nstruct drm_format_modifier_blob {\n\t__u32 version;\n\t__u32 flags;\n\t__u32 count_formats;\n\t__u32 formats_offset;\n\t__u32 count_modifiers;\n\t__u32 modifiers_offset;\n};\n\nstruct drm_framebuffer_funcs {\n\tvoid (*destroy)(struct drm_framebuffer *);\n\tint (*create_handle)(struct drm_framebuffer *, struct drm_file *, unsigned int *);\n\tint (*dirty)(struct drm_framebuffer *, struct drm_file *, unsigned int, unsigned int, struct drm_clip_rect *, unsigned int);\n};\n\nstruct drm_gem_change_handle {\n\t__u32 handle;\n\t__u32 new_handle;\n};\n\nstruct drm_gem_close {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_gem_flink {\n\t__u32 handle;\n\t__u32 name;\n};\n\nstruct drm_gem_lru {\n\tstruct mutex *lock;\n\tlong int count;\n\tstruct list_head list;\n};\n\nstruct drm_vma_offset_node {\n\trwlock_t vm_lock;\n\tstruct drm_mm_node vm_node;\n\tstruct rb_root vm_files;\n\tvoid *driver_private;\n};\n\nstruct drm_gem_object_funcs;\n\nstruct drm_gem_object {\n\tstruct kref refcount;\n\tunsigned int handle_count;\n\tstruct drm_device *dev;\n\tstruct file *filp;\n\tstruct drm_vma_offset_node vma_node;\n\tsize_t size;\n\tint name;\n\tstruct dma_buf *dma_buf;\n\tstruct dma_buf_attachment *import_attach;\n\tstruct dma_resv *resv;\n\tstruct dma_resv _resv;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct mutex lock;\n\t} gpuva;\n\tconst struct drm_gem_object_funcs *funcs;\n\tstruct list_head lru_node;\n\tstruct drm_gem_lru *lru;\n};\n\nstruct drm_gem_object_funcs {\n\tvoid (*free)(struct drm_gem_object *);\n\tint (*open)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*close)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*print_info)(struct drm_printer *, unsigned int, const struct drm_gem_object *);\n\tstruct dma_buf * (*export)(struct drm_gem_object *, int);\n\tint (*pin)(struct drm_gem_object *);\n\tvoid (*unpin)(struct drm_gem_object *);\n\tstruct sg_table * (*get_sg_table)(struct drm_gem_object *);\n\tint (*vmap)(struct drm_gem_object *, struct iosys_map *);\n\tvoid (*vunmap)(struct drm_gem_object *, struct iosys_map *);\n\tint (*mmap)(struct drm_gem_object *, struct vm_area_struct *);\n\tint (*evict)(struct drm_gem_object *);\n\tenum drm_gem_object_status (*status)(struct drm_gem_object *);\n\tsize_t (*rss)(struct drm_gem_object *);\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct drm_gem_open {\n\t__u32 name;\n\t__u32 handle;\n\t__u64 size;\n};\n\nstruct drm_gem_shmem_object {\n\tstruct drm_gem_object base;\n\tstruct page **pages;\n\trefcount_t pages_use_count;\n\trefcount_t pages_pin_count;\n\tint madv;\n\tstruct list_head madv_list;\n\tstruct sg_table *sgt;\n\tvoid *vaddr;\n\trefcount_t vmap_use_count;\n\tbool pages_mark_dirty_on_put: 1;\n\tbool pages_mark_accessed_on_put: 1;\n\tbool map_wc: 1;\n};\n\nstruct drm_get_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_gpuvm;\n\nstruct drm_gpuvm_bo;\n\nstruct drm_gpuva {\n\tstruct drm_gpuvm *vm;\n\tstruct drm_gpuvm_bo *vm_bo;\n\tenum drm_gpuva_flags flags;\n\tstruct {\n\t\tu64 addr;\n\t\tu64 range;\n\t} va;\n\tstruct {\n\t\tu64 offset;\n\t\tstruct drm_gem_object *obj;\n\t\tstruct list_head entry;\n\t} gem;\n\tstruct {\n\t\tstruct rb_node node;\n\t\tstruct list_head entry;\n\t\tu64 __subtree_last;\n\t} rb;\n};\n\nstruct drm_gpuva_op_map {\n\tstruct {\n\t\tu64 addr;\n\t\tu64 range;\n\t} va;\n\tstruct {\n\t\tu64 offset;\n\t\tstruct drm_gem_object *obj;\n\t} gem;\n};\n\nstruct drm_gpuva_op_unmap;\n\nstruct drm_gpuva_op_remap {\n\tstruct drm_gpuva_op_map *prev;\n\tstruct drm_gpuva_op_map *next;\n\tstruct drm_gpuva_op_unmap *unmap;\n};\n\nstruct drm_gpuva_op_unmap {\n\tstruct drm_gpuva *va;\n\tbool keep;\n};\n\nstruct drm_gpuva_op_prefetch {\n\tstruct drm_gpuva *va;\n};\n\nstruct drm_gpuva_op {\n\tstruct list_head entry;\n\tenum drm_gpuva_op_type op;\n\tunion {\n\t\tstruct drm_gpuva_op_map map;\n\t\tstruct drm_gpuva_op_remap remap;\n\t\tstruct drm_gpuva_op_unmap unmap;\n\t\tstruct drm_gpuva_op_prefetch prefetch;\n\t};\n};\n\nstruct drm_gpuvm_ops;\n\nstruct drm_gpuvm {\n\tconst char *name;\n\tenum drm_gpuvm_flags flags;\n\tstruct drm_device *drm;\n\tu64 mm_start;\n\tu64 mm_range;\n\tstruct {\n\t\tstruct rb_root_cached tree;\n\t\tstruct list_head list;\n\t} rb;\n\tstruct kref kref;\n\tstruct drm_gpuva kernel_alloc_node;\n\tconst struct drm_gpuvm_ops *ops;\n\tstruct drm_gem_object *r_obj;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct list_head *local_list;\n\t\tspinlock_t lock;\n\t} extobj;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct list_head *local_list;\n\t\tspinlock_t lock;\n\t} evict;\n\tstruct llist_head bo_defer;\n};\n\nstruct drm_gpuvm_bo {\n\tstruct drm_gpuvm *vm;\n\tstruct drm_gem_object *obj;\n\tbool evicted;\n\tstruct kref kref;\n\tstruct {\n\t\tstruct list_head gpuva;\n\t\tstruct {\n\t\t\tstruct list_head gem;\n\t\t\tstruct list_head extobj;\n\t\t\tstruct list_head evict;\n\t\t\tstruct llist_node bo_defer;\n\t\t} entry;\n\t} list;\n};\n\nstruct drm_gpuvm_ops {\n\tvoid (*vm_free)(struct drm_gpuvm *);\n\tstruct drm_gpuva_op * (*op_alloc)(void);\n\tvoid (*op_free)(struct drm_gpuva_op *);\n\tstruct drm_gpuvm_bo * (*vm_bo_alloc)(void);\n\tvoid (*vm_bo_free)(struct drm_gpuvm_bo *);\n\tint (*vm_bo_validate)(struct drm_gpuvm_bo *, struct drm_exec *);\n\tint (*sm_step_map)(struct drm_gpuva_op *, void *);\n\tint (*sm_step_remap)(struct drm_gpuva_op *, void *);\n\tint (*sm_step_unmap)(struct drm_gpuva_op *, void *);\n};\n\nstruct drm_hdmi_acr_n_cts_entry {\n\tunsigned int n;\n\tunsigned int cts;\n};\n\nstruct drm_hdmi_acr_data {\n\tlong unsigned int tmds_clock_khz;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_32k;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_44k1;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_48k;\n};\n\nstruct drm_i915_clock_gating_funcs {\n\tvoid (*init_clock_gating)(struct drm_i915_private *);\n};\n\nstruct drm_i915_cmd_descriptor {\n\tu32 flags;\n\tstruct {\n\t\tu32 value;\n\t\tu32 mask;\n\t} cmd;\n\tunion {\n\t\tu32 fixed;\n\t\tu32 mask;\n\t} length;\n\tstruct {\n\t\tu32 offset;\n\t\tu32 mask;\n\t\tu32 step;\n\t} reg;\n\tstruct {\n\t\tu32 offset;\n\t\tu32 mask;\n\t\tu32 expected;\n\t\tu32 condition_offset;\n\t\tu32 condition_mask;\n\t} bits[3];\n};\n\nstruct drm_i915_cmd_table {\n\tconst struct drm_i915_cmd_descriptor *table;\n\tint count;\n};\n\nstruct i915_engine_class_instance {\n\t__u16 engine_class;\n\t__u16 engine_instance;\n};\n\nstruct drm_i915_engine_info {\n\tstruct i915_engine_class_instance engine;\n\t__u32 rsvd0;\n\t__u64 flags;\n\t__u64 capabilities;\n\t__u16 logical_instance;\n\t__u16 rsvd1[3];\n\t__u64 rsvd2[3];\n};\n\nstruct drm_i915_error_state_buf {\n\tstruct drm_i915_private *i915;\n\tstruct scatterlist *sgl;\n\tstruct scatterlist *cur;\n\tstruct scatterlist *end;\n\tchar *buf;\n\tsize_t bytes;\n\tsize_t size;\n\tloff_t iter;\n\tint err;\n};\n\nstruct i915_drm_client;\n\nstruct drm_i915_file_private {\n\tstruct drm_i915_private *i915;\n\tunion {\n\t\tstruct drm_file *file;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct mutex proto_context_lock;\n\tstruct xarray proto_context_xa;\n\tstruct xarray context_xa;\n\tstruct xarray vm_xa;\n\tunsigned int bsd_engine;\n\tatomic_t ban_score;\n\tlong unsigned int hang_timestamp;\n\tstruct i915_drm_client *client;\n};\n\nstruct drm_i915_gem_busy {\n\t__u32 handle;\n\t__u32 busy;\n};\n\nstruct drm_i915_gem_caching {\n\t__u32 handle;\n\t__u32 caching;\n};\n\nstruct drm_i915_gem_context_create_ext {\n\t__u32 ctx_id;\n\t__u32 flags;\n\t__u64 extensions;\n};\n\nstruct i915_user_extension {\n\t__u64 next_extension;\n\t__u32 name;\n\t__u32 flags;\n\t__u32 rsvd[4];\n};\n\nstruct drm_i915_gem_context_param {\n\t__u32 ctx_id;\n\t__u32 size;\n\t__u64 param;\n\t__u64 value;\n};\n\nstruct drm_i915_gem_context_create_ext_setparam {\n\tstruct i915_user_extension base;\n\tstruct drm_i915_gem_context_param param;\n};\n\nstruct drm_i915_gem_context_destroy {\n\t__u32 ctx_id;\n\t__u32 pad;\n};\n\nstruct drm_i915_gem_context_param_sseu {\n\tstruct i915_engine_class_instance engine;\n\t__u32 flags;\n\t__u64 slice_mask;\n\t__u64 subslice_mask;\n\t__u16 min_eus_per_subslice;\n\t__u16 max_eus_per_subslice;\n\t__u32 rsvd;\n};\n\nstruct drm_i915_gem_create {\n\t__u64 size;\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_i915_gem_create_ext {\n\t__u64 size;\n\t__u32 handle;\n\t__u32 flags;\n\t__u64 extensions;\n};\n\nstruct drm_i915_gem_create_ext_memory_regions {\n\tstruct i915_user_extension base;\n\t__u32 pad;\n\t__u32 num_regions;\n\t__u64 regions;\n};\n\nstruct drm_i915_gem_create_ext_protected_content {\n\tstruct i915_user_extension base;\n\t__u32 flags;\n};\n\nstruct drm_i915_gem_create_ext_set_pat {\n\tstruct i915_user_extension base;\n\t__u32 pat_index;\n\t__u32 rsvd;\n};\n\nstruct drm_i915_gem_exec_fence {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_i915_gem_exec_object2 {\n\t__u32 handle;\n\t__u32 relocation_count;\n\t__u64 relocs_ptr;\n\t__u64 alignment;\n\t__u64 offset;\n\t__u64 flags;\n\tunion {\n\t\t__u64 rsvd1;\n\t\t__u64 pad_to_size;\n\t};\n\t__u64 rsvd2;\n};\n\nstruct drm_i915_gem_execbuffer2 {\n\t__u64 buffers_ptr;\n\t__u32 buffer_count;\n\t__u32 batch_start_offset;\n\t__u32 batch_len;\n\t__u32 DR1;\n\t__u32 DR4;\n\t__u32 num_cliprects;\n\t__u64 cliprects_ptr;\n\t__u64 flags;\n\t__u64 rsvd1;\n\t__u64 rsvd2;\n};\n\nstruct drm_i915_gem_execbuffer_ext_timeline_fences {\n\tstruct i915_user_extension base;\n\t__u64 fence_count;\n\t__u64 handles_ptr;\n\t__u64 values_ptr;\n};\n\nstruct drm_i915_gem_get_aperture {\n\t__u64 aper_size;\n\t__u64 aper_available_size;\n};\n\nstruct drm_i915_gem_get_tiling {\n\t__u32 handle;\n\t__u32 tiling_mode;\n\t__u32 swizzle_mode;\n\t__u32 phys_swizzle_mode;\n};\n\nstruct drm_i915_gem_madvise {\n\t__u32 handle;\n\t__u32 madv;\n\t__u32 retained;\n};\n\nstruct drm_i915_gem_memory_class_instance {\n\t__u16 memory_class;\n\t__u16 memory_instance;\n};\n\nstruct drm_i915_gem_mmap {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 addr_ptr;\n\t__u64 flags;\n};\n\nstruct drm_i915_gem_mmap_offset {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 flags;\n\t__u64 extensions;\n};\n\nstruct ttm_device;\n\nstruct ttm_resource;\n\nstruct ttm_tt;\n\nstruct ttm_lru_bulk_move;\n\nstruct ttm_buffer_object {\n\tstruct drm_gem_object base;\n\tstruct ttm_device *bdev;\n\tenum ttm_bo_type type;\n\tuint32_t page_alignment;\n\tvoid (*destroy)(struct ttm_buffer_object *);\n\tstruct kref kref;\n\tstruct ttm_resource *resource;\n\tstruct ttm_tt *ttm;\n\tbool deleted;\n\tstruct ttm_lru_bulk_move *bulk_move;\n\tunsigned int priority;\n\tunsigned int pin_count;\n\tstruct work_struct delayed_delete;\n\tstruct sg_table *sg;\n};\n\nstruct i915_page_sizes {\n\tunsigned int phys;\n\tunsigned int sg;\n};\n\nstruct i915_gem_object_page_iter {\n\tstruct scatterlist *sg_pos;\n\tunsigned int sg_idx;\n\tstruct xarray radix;\n\tstruct mutex lock;\n};\n\nstruct interval_tree_node {\n\tstruct rb_node rb;\n\tlong unsigned int start;\n\tlong unsigned int last;\n\tlong unsigned int __subtree_last;\n};\n\nstruct mmu_interval_notifier_ops;\n\nstruct mmu_interval_notifier {\n\tstruct interval_tree_node interval_tree;\n\tconst struct mmu_interval_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct hlist_node deferred_item;\n\tlong unsigned int invalidate_seq;\n};\n\nstruct i915_gem_userptr {\n\tuintptr_t ptr;\n\tlong unsigned int notifier_seq;\n\tstruct mmu_interval_notifier notifier;\n\tstruct page **pvec;\n\tint page_ref;\n};\n\nstruct drm_i915_gem_object_ops;\n\nstruct i915_address_space;\n\nstruct i915_frontbuffer;\n\nstruct i915_refct_sgt;\n\nstruct drm_i915_gem_object {\n\tunion {\n\t\tstruct drm_gem_object base;\n\t\tstruct ttm_buffer_object __do_not_access;\n\t};\n\tconst struct drm_i915_gem_object_ops *ops;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head list;\n\t\tstruct rb_root tree;\n\t} vma;\n\tstruct list_head lut_list;\n\tspinlock_t lut_lock;\n\tstruct list_head obj_link;\n\tstruct i915_address_space *shares_resv_from;\n\tstruct i915_drm_client *client;\n\tstruct list_head client_link;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct llist_node freed;\n\t};\n\tunsigned int userfault_count;\n\tstruct list_head userfault_link;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct rb_root offsets;\n\t} mmo;\n\tlong unsigned int flags;\n\tunsigned int mem_flags;\n\tunsigned int pat_index: 6;\n\tunsigned int pat_set_by_user: 1;\n\tunsigned int cache_coherent: 2;\n\tunsigned int cache_dirty: 1;\n\tunsigned int is_dpt: 1;\n\tu16 read_domains;\n\tu16 write_domain;\n\tstruct i915_frontbuffer *frontbuffer;\n\tunsigned int tiling_and_stride;\n\tstruct {\n\t\tatomic_t pages_pin_count;\n\t\tatomic_t shrink_pin;\n\t\tbool ttm_shrinkable;\n\t\tbool unknown_state;\n\t\tstruct intel_memory_region **placements;\n\t\tint n_placements;\n\t\tstruct intel_memory_region *region;\n\t\tstruct ttm_resource *res;\n\t\tstruct list_head region_link;\n\t\tstruct i915_refct_sgt *rsgt;\n\t\tstruct sg_table *pages;\n\t\tvoid *mapping;\n\t\tstruct i915_page_sizes page_sizes;\n\t\tstruct i915_gem_object_page_iter get_page;\n\t\tstruct i915_gem_object_page_iter get_dma_page;\n\t\tstruct list_head link;\n\t\tunsigned int madv: 2;\n\t\tbool dirty: 1;\n\t\tu32 tlb[2];\n\t} mm;\n\tstruct {\n\t\tstruct i915_refct_sgt *cached_io_rsgt;\n\t\tstruct i915_gem_object_page_iter get_io_page;\n\t\tstruct drm_i915_gem_object *backup;\n\t\tbool created: 1;\n\t} ttm;\n\tu32 pxp_key_instance;\n\tlong unsigned int *bit_17;\n\tunion {\n\t\tstruct i915_gem_userptr userptr;\n\t\tstruct drm_mm_node *stolen;\n\t\tresource_size_t bo_offset;\n\t\tlong unsigned int scratch;\n\t\tu64 encode;\n\t\tvoid *gvt_info;\n\t};\n};\n\nstruct drm_i915_gem_pread;\n\nstruct drm_i915_gem_pwrite;\n\nstruct drm_i915_gem_object_ops {\n\tunsigned int flags;\n\tint (*get_pages)(struct drm_i915_gem_object *);\n\tvoid (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);\n\tint (*truncate)(struct drm_i915_gem_object *);\n\tint (*shrink)(struct drm_i915_gem_object *, unsigned int);\n\tint (*pread)(struct drm_i915_gem_object *, const struct drm_i915_gem_pread *);\n\tint (*pwrite)(struct drm_i915_gem_object *, const struct drm_i915_gem_pwrite *);\n\tu64 (*mmap_offset)(struct drm_i915_gem_object *);\n\tvoid (*unmap_virtual)(struct drm_i915_gem_object *);\n\tint (*dmabuf_export)(struct drm_i915_gem_object *);\n\tvoid (*adjust_lru)(struct drm_i915_gem_object *);\n\tvoid (*delayed_free)(struct drm_i915_gem_object *);\n\tint (*migrate)(struct drm_i915_gem_object *, struct intel_memory_region *, unsigned int);\n\tvoid (*release)(struct drm_i915_gem_object *);\n\tconst struct vm_operations_struct *mmap_ops;\n\tconst char *name;\n};\n\nstruct drm_i915_gem_pread {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_gem_pwrite {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_gem_relocation_entry {\n\t__u32 target_handle;\n\t__u32 delta;\n\t__u64 offset;\n\t__u64 presumed_offset;\n\t__u32 read_domains;\n\t__u32 write_domain;\n};\n\nstruct drm_i915_gem_set_domain {\n\t__u32 handle;\n\t__u32 read_domains;\n\t__u32 write_domain;\n};\n\nstruct drm_i915_gem_set_tiling {\n\t__u32 handle;\n\t__u32 tiling_mode;\n\t__u32 stride;\n\t__u32 swizzle_mode;\n};\n\nstruct drm_i915_gem_sw_finish {\n\t__u32 handle;\n};\n\nstruct drm_i915_gem_userptr {\n\t__u64 user_ptr;\n\t__u64 user_size;\n\t__u32 flags;\n\t__u32 handle;\n};\n\nstruct drm_i915_gem_vm_control {\n\t__u64 extensions;\n\t__u32 flags;\n\t__u32 vm_id;\n};\n\nstruct drm_i915_gem_wait {\n\t__u32 bo_handle;\n\t__u32 flags;\n\t__s64 timeout_ns;\n};\n\nstruct drm_i915_get_pipe_from_crtc_id {\n\t__u32 crtc_id;\n\t__u32 pipe;\n};\n\nstruct drm_i915_getparam {\n\t__s32 param;\n\tint *value;\n};\n\ntypedef struct drm_i915_getparam drm_i915_getparam_t;\n\nstruct drm_i915_getparam32 {\n\ts32 param;\n\tu32 value;\n};\n\nstruct drm_i915_memory_region_info {\n\tstruct drm_i915_gem_memory_class_instance region;\n\t__u32 rsvd0;\n\t__u64 probed_size;\n\t__u64 unallocated_size;\n\tunion {\n\t\t__u64 rsvd1[8];\n\t\tstruct {\n\t\t\t__u64 probed_cpu_visible_size;\n\t\t\t__u64 unallocated_cpu_visible_size;\n\t\t};\n\t};\n};\n\nstruct drm_i915_mocs_entry {\n\tu32 control_value;\n\tu16 l3cc_value;\n\tu16 used;\n};\n\nstruct drm_i915_mocs_table {\n\tunsigned int size;\n\tunsigned int n_entries;\n\tconst struct drm_i915_mocs_entry *table;\n\tu8 uc_index;\n\tu8 wb_index;\n\tu8 unused_entries_index;\n};\n\nstruct drm_i915_perf_oa_config {\n\tchar uuid[36];\n\t__u32 n_mux_regs;\n\t__u32 n_boolean_regs;\n\t__u32 n_flex_regs;\n\t__u64 mux_regs_ptr;\n\t__u64 boolean_regs_ptr;\n\t__u64 flex_regs_ptr;\n};\n\nstruct drm_i915_perf_open_param {\n\t__u32 flags;\n\t__u32 num_properties;\n\t__u64 properties_ptr;\n};\n\nstruct drm_i915_perf_record_header {\n\t__u32 type;\n\t__u16 pad;\n\t__u16 size;\n};\n\nstruct i915_params {\n\tint modeset;\n\tint enable_guc;\n\tint guc_log_level;\n\tchar *guc_firmware_path;\n\tchar *huc_firmware_path;\n\tchar *gsc_firmware_path;\n\tbool memtest;\n\tint mmio_debug;\n\tunsigned int reset;\n\tchar *force_probe;\n\tunsigned int request_timeout_ms;\n\tunsigned int lmem_size;\n\tunsigned int lmem_bar_size;\n\tbool enable_hangcheck;\n\tbool error_capture;\n\tbool enable_gvt;\n\tbool enable_debug_only_api;\n};\n\nstruct intel_ip_version {\n\tu8 ver;\n\tu8 rel;\n\tu8 step;\n};\n\nstruct intel_step_info {\n\tu8 graphics_step;\n\tu8 media_step;\n};\n\nstruct intel_runtime_info {\n\tstruct {\n\t\tstruct intel_ip_version ip;\n\t} graphics;\n\tstruct {\n\t\tstruct intel_ip_version ip;\n\t} media;\n\tu32 platform_mask[2];\n\tu16 device_id;\n\tstruct intel_step_info step;\n\tunsigned int page_sizes;\n\tenum intel_ppgtt_type ppgtt_type;\n\tunsigned int ppgtt_size;\n\tbool has_pooled_eu;\n};\n\nstruct intel_driver_caps {\n\tunsigned int scheduler;\n\tbool has_logical_contexts: 1;\n};\n\nstruct i915_dsm {\n\tstruct resource stolen;\n\tstruct resource reserved;\n\tresource_size_t usable_size;\n};\n\nstruct intel_uncore;\n\nstruct intel_uncore_funcs {\n\tenum forcewake_domains (*read_fw_domains)(struct intel_uncore *, i915_reg_t);\n\tenum forcewake_domains (*write_fw_domains)(struct intel_uncore *, i915_reg_t);\n\tu8 (*mmio_readb)(struct intel_uncore *, i915_reg_t, bool);\n\tu16 (*mmio_readw)(struct intel_uncore *, i915_reg_t, bool);\n\tu32 (*mmio_readl)(struct intel_uncore *, i915_reg_t, bool);\n\tu64 (*mmio_readq)(struct intel_uncore *, i915_reg_t, bool);\n\tvoid (*mmio_writeb)(struct intel_uncore *, i915_reg_t, u8, bool);\n\tvoid (*mmio_writew)(struct intel_uncore *, i915_reg_t, u16, bool);\n\tvoid (*mmio_writel)(struct intel_uncore *, i915_reg_t, u32, bool);\n};\n\nstruct intel_gt;\n\nstruct intel_runtime_pm;\n\nstruct intel_forcewake_range;\n\nstruct i915_mmio_range;\n\nstruct intel_uncore_fw_get;\n\nstruct intel_uncore_forcewake_domain;\n\nstruct intel_uncore_mmio_debug;\n\nstruct intel_uncore {\n\tvoid *regs;\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt *gt;\n\tstruct intel_runtime_pm *rpm;\n\tspinlock_t lock;\n\tu32 gsi_offset;\n\tunsigned int flags;\n\tconst struct intel_forcewake_range *fw_domains_table;\n\tunsigned int fw_domains_table_entries;\n\tconst struct i915_mmio_range *shadowed_reg_table;\n\tunsigned int shadowed_reg_table_entries;\n\tstruct notifier_block pmic_bus_access_nb;\n\tconst struct intel_uncore_fw_get *fw_get_funcs;\n\tstruct intel_uncore_funcs funcs;\n\tunsigned int fifo_count;\n\tenum forcewake_domains fw_domains;\n\tenum forcewake_domains fw_domains_active;\n\tenum forcewake_domains fw_domains_timer;\n\tenum forcewake_domains fw_domains_saved;\n\tstruct intel_uncore_forcewake_domain *fw_domain[16];\n\tunsigned int user_forcewake_count;\n\tstruct intel_uncore_mmio_debug *debug;\n};\n\nstruct intel_uncore_mmio_debug {\n\tspinlock_t lock;\n\tint unclaimed_mmio_check;\n\tint saved_mmio_check;\n\tu32 suspend_count;\n};\n\nstruct i915_virtual_gpu {\n\tstruct mutex lock;\n\tbool active;\n\tu32 caps;\n\tu32 *initial_mmio;\n\tu8 *initial_cfg_space;\n\tstruct list_head entry;\n};\n\nstruct intel_gvt;\n\nstruct pm_qos_request {\n\tstruct plist_node node;\n\tstruct pm_qos_constraints *qos;\n};\n\nstruct drm_mm {\n\tvoid (*color_adjust)(const struct drm_mm_node *, long unsigned int, u64 *, u64 *);\n\tstruct list_head hole_stack;\n\tstruct drm_mm_node head_node;\n\tstruct rb_root_cached interval_tree;\n\tstruct rb_root_cached holes_size;\n\tstruct rb_root holes_addr;\n\tlong unsigned int scan_active;\n};\n\nstruct shrinker;\n\nstruct i915_gem_mm {\n\tstruct intel_memory_region *stolen_region;\n\tstruct drm_mm stolen;\n\tstruct mutex stolen_lock;\n\tspinlock_t obj_lock;\n\tstruct list_head purge_list;\n\tstruct list_head shrink_list;\n\tstruct llist_head free_list;\n\tstruct work_struct free_work;\n\tatomic_t free_count;\n\tstruct intel_memory_region *regions[7];\n\tstruct notifier_block oom_notifier;\n\tstruct notifier_block vmap_notifier;\n\tstruct shrinker *shrinker;\n\tu64 shrink_memory;\n\tu32 shrink_count;\n};\n\nstruct intel_l3_parity {\n\tu32 *remap_info[2];\n\tstruct work_struct error_work;\n\tint which_slice;\n};\n\nstruct i915_gpu_coredump;\n\nstruct i915_gpu_error {\n\tspinlock_t lock;\n\tstruct i915_gpu_coredump *first_error;\n\tatomic_t reset_count;\n\tatomic_t reset_engine_count[5];\n};\n\ntypedef struct ref_tracker *intel_wakeref_t;\n\nstruct intel_wakeref_auto {\n\tstruct drm_i915_private *i915;\n\tstruct timer_list timer;\n\tintel_wakeref_t wakeref;\n\tspinlock_t lock;\n\trefcount_t count;\n};\n\nstruct intel_runtime_pm {\n\tatomic_t wakeref_count;\n\tstruct device *kdev;\n\tbool available;\n\tbool no_wakeref_tracking;\n\tspinlock_t lmem_userfault_lock;\n\tstruct list_head lmem_userfault_list;\n\tstruct intel_wakeref_auto userfault_wakeref;\n};\n\nstruct i915_perf;\n\nstruct i915_perf_stream;\n\nstruct i915_oa_ops {\n\tbool (*is_valid_b_counter_reg)(struct i915_perf *, u32);\n\tbool (*is_valid_mux_reg)(struct i915_perf *, u32);\n\tbool (*is_valid_flex_reg)(struct i915_perf *, u32);\n\tint (*enable_metric_set)(struct i915_perf_stream *, struct i915_active *);\n\tvoid (*disable_metric_set)(struct i915_perf_stream *);\n\tvoid (*oa_enable)(struct i915_perf_stream *);\n\tvoid (*oa_disable)(struct i915_perf_stream *);\n\tint (*read)(struct i915_perf_stream *, char *, size_t, size_t *);\n\tu32 (*oa_hw_tail_read)(struct i915_perf_stream *);\n};\n\nstruct i915_oa_format;\n\nstruct i915_perf {\n\tstruct drm_i915_private *i915;\n\tstruct kobject *metrics_kobj;\n\tstruct mutex metrics_lock;\n\tstruct idr metrics_idr;\n\tstruct ratelimit_state spurious_report_rs;\n\tstruct ratelimit_state tail_pointer_race;\n\tu32 gen7_latched_oastatus1;\n\tu32 ctx_oactxctrl_offset;\n\tu32 ctx_flexeu0_offset;\n\tu32 gen8_valid_ctx_bit;\n\tstruct i915_oa_ops ops;\n\tconst struct i915_oa_format *oa_formats;\n\tlong unsigned int format_mask[1];\n\tatomic64_t noa_programming_delay;\n};\n\nstruct i915_gem_contexts {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct i915_pmu_sample {\n\tu64 cur;\n};\n\nstruct i915_pmu {\n\tstruct pmu base;\n\tbool registered;\n\tconst char *name;\n\tspinlock_t lock;\n\tunsigned int unparked;\n\tstruct hrtimer timer;\n\tu32 enable;\n\tktime_t timer_last;\n\tunsigned int enable_count[9];\n\tbool timer_enabled;\n\tstruct i915_pmu_sample sample[8];\n\tktime_t sleep_last[2];\n\tlong unsigned int irq_count;\n\tstruct attribute_group events_attr_group;\n\tvoid *i915_attr;\n\tvoid *pmu_attr;\n};\n\nstruct dmem_cgroup_region;\n\nstruct ttm_resource_manager_func;\n\nstruct ttm_resource_manager {\n\tbool use_type;\n\tbool use_tt;\n\tstruct ttm_device *bdev;\n\tuint64_t size;\n\tconst struct ttm_resource_manager_func *func;\n\tspinlock_t eviction_lock;\n\tstruct dma_fence *eviction_fences[8];\n\tstruct list_head lru[4];\n\tuint64_t usage;\n\tstruct dmem_cgroup_region *cg;\n};\n\nstruct ttm_pool;\n\nstruct ttm_pool_type {\n\tstruct ttm_pool *pool;\n\tunsigned int order;\n\tenum ttm_caching caching;\n\tstruct list_head shrinker_list;\n\tspinlock_t lock;\n\tstruct list_head pages;\n};\n\nstruct ttm_pool {\n\tstruct device *dev;\n\tint nid;\n\tunsigned int alloc_flags;\n\tstruct {\n\t\tstruct ttm_pool_type orders[11];\n\t} caching[3];\n};\n\nstruct ttm_device_funcs;\n\nstruct ttm_device {\n\tstruct list_head device_list;\n\tunsigned int alloc_flags;\n\tconst struct ttm_device_funcs *funcs;\n\tstruct ttm_resource_manager sysman;\n\tstruct ttm_resource_manager *man_drv[9];\n\tstruct drm_vma_offset_manager *vma_manager;\n\tstruct ttm_pool pool;\n\tspinlock_t lru_lock;\n\tstruct list_head unevictable;\n\tstruct address_space *dev_mapping;\n\tstruct workqueue_struct *wq;\n};\n\nstruct intel_device_info;\n\nstruct vlv_s0ix_state;\n\nstruct i915_hwmon;\n\nstruct intel_pxp;\n\nstruct drm_i915_private {\n\tstruct drm_device drm;\n\tstruct intel_display *display;\n\tbool do_release;\n\tstruct i915_params params;\n\tconst struct intel_device_info *__info;\n\tstruct intel_runtime_info __runtime;\n\tstruct intel_driver_caps caps;\n\tstruct i915_dsm dsm;\n\tstruct intel_uncore uncore;\n\tstruct intel_uncore_mmio_debug mmio_debug;\n\tstruct i915_virtual_gpu vgpu;\n\tstruct intel_gvt *gvt;\n\tstruct {\n\t\tstruct pci_dev *pdev;\n\t\tstruct resource mch_res;\n\t\tbool mchbar_need_disable;\n\t} gmch;\n\tunion {\n\t\tstruct llist_head uabi_engines_llist;\n\t\tstruct list_head uabi_engines_list;\n\t\tstruct rb_root uabi_engines;\n\t};\n\tunsigned int engine_uabi_class_count[5];\n\tbool irqs_enabled;\n\tstruct mutex sbi_lock;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tlong unsigned int locked_unit_mask;\n\t\tstruct pm_qos_request qos;\n\t} vlv_iosf_sb;\n\tstruct mutex sb_lock;\n\tu32 gen2_imr_mask;\n\tbool preserve_bios_swizzle;\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_struct *unordered_wq;\n\tconst struct drm_i915_clock_gating_funcs *clock_gating_funcs;\n\tlong unsigned int gem_quirks;\n\tstruct i915_gem_mm mm;\n\tstruct intel_l3_parity l3_parity;\n\tu32 edram_size_mb;\n\tstruct i915_gpu_error gpu_error;\n\tu32 suspend_count;\n\tstruct vlv_s0ix_state *vlv_s0ix_state;\n\tstruct intel_runtime_pm runtime_pm;\n\tstruct i915_perf perf;\n\tstruct i915_hwmon *hwmon;\n\tstruct intel_gt *gt[2];\n\tstruct kobject *sysfs_gt;\n\tstruct intel_gt *media_gt;\n\tstruct {\n\t\tstruct i915_gem_contexts contexts;\n\t\tstruct file *mmap_singleton;\n\t} gem;\n\tspinlock_t frontbuffer_lock;\n\tstruct intel_pxp *pxp;\n\tstruct i915_pmu pmu;\n\tstruct ttm_device bdev;\n};\n\nstruct drm_i915_query {\n\t__u32 num_items;\n\t__u32 flags;\n\t__u64 items_ptr;\n};\n\nstruct drm_i915_query_engine_info {\n\t__u32 num_engines;\n\t__u32 rsvd[3];\n\tstruct drm_i915_engine_info engines[0];\n};\n\nstruct drm_i915_query_guc_submission_version {\n\t__u32 branch;\n\t__u32 major;\n\t__u32 minor;\n\t__u32 patch;\n};\n\nstruct drm_i915_query_item {\n\t__u64 query_id;\n\t__s32 length;\n\t__u32 flags;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_query_memory_regions {\n\t__u32 num_regions;\n\t__u32 rsvd[3];\n\tstruct drm_i915_memory_region_info regions[0];\n};\n\nstruct drm_i915_query_perf_config {\n\tunion {\n\t\t__u64 n_configs;\n\t\t__u64 config;\n\t\tchar uuid[36];\n\t};\n\t__u32 flags;\n\t__u8 data[0];\n};\n\nstruct drm_i915_query_topology_info {\n\t__u16 flags;\n\t__u16 max_slices;\n\t__u16 max_subslices;\n\t__u16 max_eus_per_subslice;\n\t__u16 subslice_offset;\n\t__u16 subslice_stride;\n\t__u16 eu_offset;\n\t__u16 eu_stride;\n\t__u8 data[0];\n};\n\nstruct drm_i915_reg_descriptor {\n\ti915_reg_t addr;\n\tu32 mask;\n\tu32 value;\n};\n\nstruct drm_i915_reg_read {\n\t__u64 offset;\n\t__u64 val;\n};\n\nstruct drm_i915_reg_table {\n\tconst struct drm_i915_reg_descriptor *regs;\n\tint num_regs;\n};\n\nstruct drm_i915_reset_stats {\n\t__u32 ctx_id;\n\t__u32 flags;\n\t__u32 reset_count;\n\t__u32 batch_active;\n\t__u32 batch_pending;\n\t__u32 pad;\n};\n\nstruct drm_info_list {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n\tu32 driver_features;\n\tvoid *data;\n};\n\nstruct drm_info_node {\n\tstruct drm_minor *minor;\n\tconst struct drm_info_list *info_ent;\n\tstruct list_head list;\n\tstruct dentry *dent;\n};\n\nstruct drm_intel_overlay_attrs {\n\t__u32 flags;\n\t__u32 color_key;\n\t__s32 brightness;\n\t__u32 contrast;\n\t__u32 saturation;\n\t__u32 gamma0;\n\t__u32 gamma1;\n\t__u32 gamma2;\n\t__u32 gamma3;\n\t__u32 gamma4;\n\t__u32 gamma5;\n};\n\nstruct drm_intel_overlay_put_image {\n\t__u32 flags;\n\t__u32 bo_handle;\n\t__u16 stride_Y;\n\t__u16 stride_UV;\n\t__u32 offset_Y;\n\t__u32 offset_U;\n\t__u32 offset_V;\n\t__u16 src_width;\n\t__u16 src_height;\n\t__u16 src_scan_width;\n\t__u16 src_scan_height;\n\t__u32 crtc_id;\n\t__u16 dst_x;\n\t__u16 dst_y;\n\t__u16 dst_width;\n\t__u16 dst_height;\n};\n\nstruct drm_intel_sprite_colorkey {\n\t__u32 plane_id;\n\t__u32 min_value;\n\t__u32 channel_mask;\n\t__u32 max_value;\n\t__u32 flags;\n};\n\ntypedef int drm_ioctl_t(struct drm_device *, void *, struct drm_file *);\n\nstruct drm_ioctl_desc {\n\tunsigned int cmd;\n\tenum drm_ioctl_flags flags;\n\tdrm_ioctl_t *func;\n\tconst char *name;\n};\n\nstruct drm_master {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tchar *unique;\n\tint unique_len;\n\tstruct idr magic_map;\n\tvoid *driver_priv;\n\tstruct drm_master *lessor;\n\tint lessee_id;\n\tstruct list_head lessee_list;\n\tstruct list_head lessees;\n\tstruct idr leases;\n\tstruct idr lessee_idr;\n};\n\nstruct drm_memory_stats {\n\tu64 shared;\n\tu64 private;\n\tu64 resident;\n\tu64 purgeable;\n\tu64 active;\n};\n\nstruct drm_minor {\n\tint index;\n\tint type;\n\tstruct device *kdev;\n\tstruct drm_device *dev;\n\tstruct dentry *debugfs_symlink;\n\tstruct dentry *debugfs_root;\n};\n\nstruct drm_mm_scan {\n\tstruct drm_mm *mm;\n\tu64 size;\n\tu64 alignment;\n\tu64 remainder_mask;\n\tu64 range_start;\n\tu64 range_end;\n\tu64 hit_start;\n\tu64 hit_end;\n\tlong unsigned int color;\n\tenum drm_mm_insert_mode mode;\n};\n\nstruct drm_mode_atomic {\n\t__u32 flags;\n\t__u32 count_objs;\n\t__u64 objs_ptr;\n\t__u64 count_props_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u64 reserved;\n\t__u64 user_data;\n};\n\nstruct drm_mode_card_res {\n\t__u64 fb_id_ptr;\n\t__u64 crtc_id_ptr;\n\t__u64 connector_id_ptr;\n\t__u64 encoder_id_ptr;\n\t__u32 count_fbs;\n\t__u32 count_crtcs;\n\t__u32 count_connectors;\n\t__u32 count_encoders;\n\t__u32 min_width;\n\t__u32 max_width;\n\t__u32 min_height;\n\t__u32 max_height;\n};\n\nstruct drm_mode_closefb {\n\t__u32 fb_id;\n\t__u32 pad;\n};\n\nstruct drm_mode_fb_cmd2;\n\nstruct drm_mode_config_funcs {\n\tstruct drm_framebuffer * (*fb_create)(struct drm_device *, struct drm_file *, const struct drm_format_info *, const struct drm_mode_fb_cmd2 *);\n\tconst struct drm_format_info * (*get_format_info)(u32, u64);\n\tenum drm_mode_status (*mode_valid)(struct drm_device *, const struct drm_display_mode *);\n\tint (*atomic_check)(struct drm_device *, struct drm_atomic_state *);\n\tint (*atomic_commit)(struct drm_device *, struct drm_atomic_state *, bool);\n\tstruct drm_atomic_state * (*atomic_state_alloc)(struct drm_device *);\n\tvoid (*atomic_state_clear)(struct drm_atomic_state *);\n\tvoid (*atomic_state_free)(struct drm_atomic_state *);\n};\n\nstruct drm_mode_config_helper_funcs {\n\tvoid (*atomic_commit_tail)(struct drm_atomic_state *);\n\tint (*atomic_commit_setup)(struct drm_atomic_state *);\n};\n\nstruct drm_mode_connector_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 connector_id;\n};\n\nstruct drm_mode_create_blob {\n\t__u64 data;\n\t__u32 length;\n\t__u32 blob_id;\n};\n\nstruct drm_mode_create_dumb {\n\t__u32 height;\n\t__u32 width;\n\t__u32 bpp;\n\t__u32 flags;\n\t__u32 handle;\n\t__u32 pitch;\n\t__u64 size;\n};\n\nstruct drm_mode_create_lease {\n\t__u64 object_ids;\n\t__u32 object_count;\n\t__u32 flags;\n\t__u32 lessee_id;\n\t__u32 fd;\n};\n\nstruct drm_mode_modeinfo {\n\t__u32 clock;\n\t__u16 hdisplay;\n\t__u16 hsync_start;\n\t__u16 hsync_end;\n\t__u16 htotal;\n\t__u16 hskew;\n\t__u16 vdisplay;\n\t__u16 vsync_start;\n\t__u16 vsync_end;\n\t__u16 vtotal;\n\t__u16 vscan;\n\t__u32 vrefresh;\n\t__u32 flags;\n\t__u32 type;\n\tchar name[32];\n};\n\nstruct drm_mode_crtc {\n\t__u64 set_connectors_ptr;\n\t__u32 count_connectors;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 x;\n\t__u32 y;\n\t__u32 gamma_size;\n\t__u32 mode_valid;\n\tstruct drm_mode_modeinfo mode;\n};\n\nstruct drm_mode_crtc_lut {\n\t__u32 crtc_id;\n\t__u32 gamma_size;\n\t__u64 red;\n\t__u64 green;\n\t__u64 blue;\n};\n\nstruct drm_mode_crtc_page_flip_target {\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 sequence;\n\t__u64 user_data;\n};\n\nstruct drm_mode_cursor {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n};\n\nstruct drm_mode_cursor2 {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n\t__s32 hot_x;\n\t__s32 hot_y;\n};\n\nstruct drm_mode_destroy_blob {\n\t__u32 blob_id;\n};\n\nstruct drm_mode_destroy_dumb {\n\t__u32 handle;\n};\n\nstruct drm_mode_fb_cmd {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pitch;\n\t__u32 bpp;\n\t__u32 depth;\n\t__u32 handle;\n};\n\nstruct drm_mode_fb_cmd2 {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pixel_format;\n\t__u32 flags;\n\t__u32 handles[4];\n\t__u32 pitches[4];\n\t__u32 offsets[4];\n\t__u64 modifier[4];\n};\n\nstruct drm_mode_fb_cmd232 {\n\tu32 fb_id;\n\tu32 width;\n\tu32 height;\n\tu32 pixel_format;\n\tu32 flags;\n\tu32 handles[4];\n\tu32 pitches[4];\n\tu32 offsets[4];\n\tu64 modifier[4];\n} __attribute__((packed));\n\nstruct drm_mode_fb_dirty_cmd {\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 color;\n\t__u32 num_clips;\n\t__u64 clips_ptr;\n};\n\nstruct drm_mode_get_blob {\n\t__u32 blob_id;\n\t__u32 length;\n\t__u64 data;\n};\n\nstruct drm_mode_get_connector {\n\t__u64 encoders_ptr;\n\t__u64 modes_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_modes;\n\t__u32 count_props;\n\t__u32 count_encoders;\n\t__u32 encoder_id;\n\t__u32 connector_id;\n\t__u32 connector_type;\n\t__u32 connector_type_id;\n\t__u32 connection;\n\t__u32 mm_width;\n\t__u32 mm_height;\n\t__u32 subpixel;\n\t__u32 pad;\n};\n\nstruct drm_mode_get_encoder {\n\t__u32 encoder_id;\n\t__u32 encoder_type;\n\t__u32 crtc_id;\n\t__u32 possible_crtcs;\n\t__u32 possible_clones;\n};\n\nstruct drm_mode_get_lease {\n\t__u32 count_objects;\n\t__u32 pad;\n\t__u64 objects_ptr;\n};\n\nstruct drm_mode_get_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 possible_crtcs;\n\t__u32 gamma_size;\n\t__u32 count_format_types;\n\t__u64 format_type_ptr;\n};\n\nstruct drm_mode_get_plane_res {\n\t__u64 plane_id_ptr;\n\t__u32 count_planes;\n};\n\nstruct drm_mode_get_property {\n\t__u64 values_ptr;\n\t__u64 enum_blob_ptr;\n\t__u32 prop_id;\n\t__u32 flags;\n\tchar name[32];\n\t__u32 count_values;\n\t__u32 count_enum_blobs;\n};\n\nstruct drm_mode_list_lessees {\n\t__u32 count_lessees;\n\t__u32 pad;\n\t__u64 lessees_ptr;\n};\n\nstruct drm_mode_map_dumb {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n};\n\nstruct drm_mode_obj_get_properties {\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_props;\n\t__u32 obj_id;\n\t__u32 obj_type;\n};\n\nstruct drm_mode_obj_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 obj_id;\n\t__u32 obj_type;\n};\n\nstruct drm_mode_property_enum {\n\t__u64 value;\n\tchar name[32];\n};\n\nstruct drm_mode_rect {\n\t__s32 x1;\n\t__s32 y1;\n\t__s32 x2;\n\t__s32 y2;\n};\n\nstruct drm_mode_revoke_lease {\n\t__u32 lessee_id;\n};\n\nstruct drm_mode_rmfb_work {\n\tstruct work_struct work;\n\tstruct list_head fbs;\n};\n\nstruct drm_mode_set {\n\tstruct drm_framebuffer *fb;\n\tstruct drm_crtc *crtc;\n\tstruct drm_display_mode *mode;\n\tuint32_t x;\n\tuint32_t y;\n\tstruct drm_connector **connectors;\n\tsize_t num_connectors;\n};\n\nstruct drm_mode_set_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__s32 crtc_x;\n\t__s32 crtc_y;\n\t__u32 crtc_w;\n\t__u32 crtc_h;\n\t__u32 src_x;\n\t__u32 src_y;\n\t__u32 src_h;\n\t__u32 src_w;\n};\n\nstruct drm_modeset_acquire_ctx {\n\tstruct ww_acquire_ctx ww_ctx;\n\tstruct drm_modeset_lock *contended;\n\tdepot_stack_handle_t stack_depot;\n\tstruct list_head locked;\n\tbool trylock_only;\n\tbool interruptible;\n};\n\nstruct drm_named_mode {\n\tconst char *name;\n\tunsigned int pixel_clock_khz;\n\tunsigned int xres;\n\tunsigned int yres;\n\tunsigned int flags;\n\tunsigned int tv_mode;\n};\n\nstruct sync_file;\n\nstruct drm_out_fence_state {\n\ts32 *out_fence_ptr;\n\tstruct sync_file *sync_file;\n\tint fd;\n};\n\nstruct drm_panel_funcs;\n\nstruct drm_panel {\n\tstruct device *dev;\n\tstruct backlight_device *backlight;\n\tconst struct drm_panel_funcs *funcs;\n\tint connector_type;\n\tstruct list_head list;\n\tstruct list_head followers;\n\tstruct mutex follower_lock;\n\tbool prepare_prev_first;\n\tbool prepared;\n\tbool enabled;\n\tvoid *container;\n\tstruct kref refcount;\n};\n\nstruct drm_panel_follower_funcs;\n\nstruct drm_panel_follower {\n\tconst struct drm_panel_follower_funcs *funcs;\n\tstruct list_head list;\n\tstruct drm_panel *panel;\n};\n\nstruct drm_panel_follower_funcs {\n\tint (*panel_prepared)(struct drm_panel_follower *);\n\tint (*panel_unpreparing)(struct drm_panel_follower *);\n\tint (*panel_enabled)(struct drm_panel_follower *);\n\tint (*panel_disabling)(struct drm_panel_follower *);\n};\n\nstruct display_timing;\n\nstruct drm_panel_funcs {\n\tint (*prepare)(struct drm_panel *);\n\tint (*enable)(struct drm_panel *);\n\tint (*disable)(struct drm_panel *);\n\tint (*unprepare)(struct drm_panel *);\n\tint (*get_modes)(struct drm_panel *, struct drm_connector *);\n\tenum drm_panel_orientation (*get_orientation)(struct drm_panel *);\n\tint (*get_timings)(struct drm_panel *, unsigned int, struct display_timing *);\n\tvoid (*debugfs_init)(struct drm_panel *, struct dentry *);\n};\n\nstruct drm_pending_event {\n\tstruct completion *completion;\n\tvoid (*completion_release)(struct completion *);\n\tstruct drm_event *event;\n\tstruct dma_fence *fence;\n\tstruct drm_file *file_priv;\n\tstruct list_head link;\n\tstruct list_head pending_link;\n};\n\nstruct drm_pending_vblank_event {\n\tstruct drm_pending_event base;\n\tunsigned int pipe;\n\tu64 sequence;\n\tunion {\n\t\tstruct drm_event base;\n\t\tstruct drm_event_vblank vbl;\n\t\tstruct drm_event_crtc_sequence seq;\n\t} event;\n};\n\nstruct drm_plane_funcs {\n\tint (*update_plane)(struct drm_plane *, struct drm_crtc *, struct drm_framebuffer *, int, int, unsigned int, unsigned int, uint32_t, uint32_t, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*disable_plane)(struct drm_plane *, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_plane *);\n\tvoid (*reset)(struct drm_plane *);\n\tint (*set_property)(struct drm_plane *, struct drm_property *, uint64_t);\n\tstruct drm_plane_state * (*atomic_duplicate_state)(struct drm_plane *);\n\tvoid (*atomic_destroy_state)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_set_property)(struct drm_plane *, struct drm_plane_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_plane *, const struct drm_plane_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_plane *);\n\tvoid (*early_unregister)(struct drm_plane *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_plane_state *);\n\tbool (*format_mod_supported)(struct drm_plane *, uint32_t, uint64_t);\n\tbool (*format_mod_supported_async)(struct drm_plane *, u32, u64);\n};\n\nstruct drm_scanout_buffer;\n\nstruct drm_plane_helper_funcs {\n\tint (*prepare_fb)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_plane *, struct drm_plane_state *);\n\tint (*begin_fb_access)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*end_fb_access)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_check)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_update)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_plane *, struct drm_atomic_state *);\n\tint (*atomic_async_check)(struct drm_plane *, struct drm_atomic_state *, bool);\n\tvoid (*atomic_async_update)(struct drm_plane *, struct drm_atomic_state *);\n\tint (*get_scanout_buffer)(struct drm_plane *, struct drm_scanout_buffer *);\n\tvoid (*panic_flush)(struct drm_plane *);\n};\n\nstruct drm_plane_size_hint {\n\t__u16 width;\n\t__u16 height;\n};\n\nstruct drm_plane_state {\n\tstruct drm_plane *plane;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *fence;\n\tint32_t crtc_x;\n\tint32_t crtc_y;\n\tuint32_t crtc_w;\n\tuint32_t crtc_h;\n\tuint32_t src_x;\n\tuint32_t src_y;\n\tuint32_t src_h;\n\tuint32_t src_w;\n\tint32_t hotspot_x;\n\tint32_t hotspot_y;\n\tu16 alpha;\n\tuint16_t pixel_blend_mode;\n\tunsigned int rotation;\n\tunsigned int zpos;\n\tunsigned int normalized_zpos;\n\tenum drm_color_encoding color_encoding;\n\tenum drm_color_range color_range;\n\tstruct drm_property_blob *fb_damage_clips;\n\tbool ignore_damage_clips;\n\tstruct drm_rect src;\n\tstruct drm_rect dst;\n\tbool visible;\n\tenum drm_scaling_filter scaling_filter;\n\tstruct drm_colorop *color_pipeline;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n\tbool color_mgmt_changed: 1;\n};\n\nstruct drm_prime_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct drm_prime_member {\n\tstruct dma_buf *dma_buf;\n\tuint32_t handle;\n\tstruct rb_node dmabuf_rb;\n\tstruct rb_node handle_rb;\n};\n\nstruct drm_print_iterator {\n\tvoid *data;\n\tssize_t start;\n\tssize_t remain;\n\tssize_t offset;\n};\n\nstruct va_format;\n\nstruct drm_printer {\n\tvoid (*printfn)(struct drm_printer *, struct va_format *);\n\tvoid (*puts)(struct drm_printer *, const char *);\n\tvoid *arg;\n\tconst void *origin;\n\tconst char *prefix;\n\tstruct {\n\t\tunsigned int series;\n\t\tunsigned int counter;\n\t} line;\n\tenum drm_debug_category category;\n};\n\nstruct drm_private_state_funcs {\n\tstruct drm_private_state * (*atomic_duplicate_state)(struct drm_private_obj *);\n\tvoid (*atomic_destroy_state)(struct drm_private_obj *, struct drm_private_state *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_private_state *);\n};\n\nstruct drm_prop_enum_list {\n\tint type;\n\tconst char *name;\n};\n\nstruct drm_property {\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tuint32_t flags;\n\tchar name[32];\n\tuint32_t num_values;\n\tuint64_t *values;\n\tstruct drm_device *dev;\n\tstruct list_head enum_list;\n};\n\nstruct drm_property_blob {\n\tstruct drm_mode_object base;\n\tstruct drm_device *dev;\n\tstruct list_head head_global;\n\tstruct list_head head_file;\n\tsize_t length;\n\tvoid *data;\n};\n\nstruct drm_property_enum {\n\tuint64_t value;\n\tstruct list_head head;\n\tchar name[32];\n};\n\nstruct drm_scanout_buffer {\n\tconst struct drm_format_info *format;\n\tstruct iosys_map map[4];\n\tstruct page **pages;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int pitch[4];\n\tvoid (*set_pixel)(struct drm_scanout_buffer *, unsigned int, unsigned int, u32);\n\tvoid *private;\n};\n\nstruct ewma_psr_time {\n\tlong unsigned int internal;\n};\n\nstruct drm_self_refresh_data {\n\tstruct drm_crtc *crtc;\n\tstruct delayed_work entry_work;\n\tstruct mutex avg_mutex;\n\tstruct ewma_psr_time entry_avg_ms;\n\tstruct ewma_psr_time exit_avg_ms;\n};\n\nstruct drm_set_client_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_set_client_name {\n\t__u64 name_len;\n\t__u64 name;\n};\n\nstruct drm_set_version {\n\tint drm_di_major;\n\tint drm_di_minor;\n\tint drm_dd_major;\n\tint drm_dd_minor;\n};\n\nstruct drm_shadow_plane_state {\n\tstruct drm_plane_state base;\n\tstruct drm_format_conv_state fmtcnv_state;\n\tstruct iosys_map map[4];\n\tstruct iosys_map data[4];\n};\n\nstruct drm_simple_display_pipe_funcs;\n\nstruct drm_simple_display_pipe {\n\tstruct drm_crtc crtc;\n\tstruct drm_plane plane;\n\tstruct drm_encoder encoder;\n\tstruct drm_connector *connector;\n\tconst struct drm_simple_display_pipe_funcs *funcs;\n};\n\nstruct drm_simple_display_pipe_funcs {\n\tenum drm_mode_status (*mode_valid)(struct drm_simple_display_pipe *, const struct drm_display_mode *);\n\tvoid (*enable)(struct drm_simple_display_pipe *, struct drm_crtc_state *, struct drm_plane_state *);\n\tvoid (*disable)(struct drm_simple_display_pipe *);\n\tint (*check)(struct drm_simple_display_pipe *, struct drm_plane_state *, struct drm_crtc_state *);\n\tvoid (*update)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*prepare_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*begin_fb_access)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tvoid (*end_fb_access)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*enable_vblank)(struct drm_simple_display_pipe *);\n\tvoid (*disable_vblank)(struct drm_simple_display_pipe *);\n\tvoid (*reset_crtc)(struct drm_simple_display_pipe *);\n\tstruct drm_crtc_state * (*duplicate_crtc_state)(struct drm_simple_display_pipe *);\n\tvoid (*destroy_crtc_state)(struct drm_simple_display_pipe *, struct drm_crtc_state *);\n\tvoid (*reset_plane)(struct drm_simple_display_pipe *);\n\tstruct drm_plane_state * (*duplicate_plane_state)(struct drm_simple_display_pipe *);\n\tvoid (*destroy_plane_state)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n};\n\nstruct drm_stats {\n\tlong unsigned int count;\n\tstruct {\n\t\tlong unsigned int value;\n\t\tenum drm_stat_type type;\n\t} data[15];\n};\n\nstruct drm_stats32 {\n\tu32 count;\n\tstruct {\n\t\tu32 value;\n\t\tenum drm_stat_type type;\n\t} data[15];\n};\n\ntypedef struct drm_stats32 drm_stats32_t;\n\nstruct drm_syncobj {\n\tstruct kref refcount;\n\tstruct dma_fence *fence;\n\tstruct list_head cb_list;\n\tstruct list_head ev_fd_list;\n\tspinlock_t lock;\n\tstruct file *file;\n};\n\nstruct drm_syncobj_array {\n\t__u64 handles;\n\t__u32 count_handles;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_create {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_syncobj_destroy {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_eventfd {\n\t__u32 handle;\n\t__u32 flags;\n\t__u64 point;\n\t__s32 fd;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n\t__u32 pad;\n\t__u64 point;\n};\n\nstruct drm_syncobj_timeline_array {\n\t__u64 handles;\n\t__u64 points;\n\t__u32 count_handles;\n\t__u32 flags;\n};\n\nstruct drm_syncobj_timeline_wait {\n\t__u64 handles;\n\t__u64 points;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n\t__u64 deadline_nsec;\n};\n\nstruct drm_syncobj_transfer {\n\t__u32 src_handle;\n\t__u32 dst_handle;\n\t__u64 src_point;\n\t__u64 dst_point;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_wait {\n\t__u64 handles;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n\t__u64 deadline_nsec;\n};\n\nstruct drm_tile_group {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tint id;\n\tu8 group_data[8];\n};\n\nstruct drm_unique {\n\t__kernel_size_t unique_len;\n\tchar *unique;\n};\n\nstruct drm_unique32 {\n\tu32 unique_len;\n\tu32 unique;\n};\n\ntypedef struct drm_unique32 drm_unique32_t;\n\nstruct drm_vblank_crtc_config {\n\tint offdelay_ms;\n\tbool disable_immediate;\n};\n\nstruct drm_vblank_crtc_timer {\n\tstruct hrtimer timer;\n\tspinlock_t interval_lock;\n\tktime_t interval;\n\tstruct drm_crtc *crtc;\n};\n\nstruct drm_vblank_crtc {\n\tstruct drm_device *dev;\n\twait_queue_head_t queue;\n\tstruct timer_list disable_timer;\n\tseqlock_t seqlock;\n\tatomic64_t count;\n\tktime_t time;\n\tatomic_t refcount;\n\tu32 last;\n\tu32 max_vblank_count;\n\tunsigned int inmodeset;\n\tunsigned int pipe;\n\tint framedur_ns;\n\tint linedur_ns;\n\tstruct drm_display_mode hwmode;\n\tstruct drm_vblank_crtc_config config;\n\tbool enabled;\n\tstruct kthread_worker *worker;\n\tstruct list_head pending_work;\n\twait_queue_head_t work_wait_queue;\n\tstruct drm_vblank_crtc_timer vblank_timer;\n};\n\nstruct drm_vblank_work {\n\tstruct kthread_work base;\n\tstruct drm_vblank_crtc *vblank;\n\tu64 count;\n\tint cancelling;\n\tstruct list_head node;\n};\n\nstruct drm_version {\n\tint version_major;\n\tint version_minor;\n\tint version_patchlevel;\n\t__kernel_size_t name_len;\n\tchar *name;\n\t__kernel_size_t date_len;\n\tchar *date;\n\t__kernel_size_t desc_len;\n\tchar *desc;\n};\n\nstruct drm_version_32 {\n\tint version_major;\n\tint version_minor;\n\tint version_patchlevel;\n\tu32 name_len;\n\tu32 name;\n\tu32 date_len;\n\tu32 date;\n\tu32 desc_len;\n\tu32 desc;\n};\n\ntypedef struct drm_version_32 drm_version32_t;\n\nstruct drm_virtgpu_3d_box {\n\t__u32 x;\n\t__u32 y;\n\t__u32 z;\n\t__u32 w;\n\t__u32 h;\n\t__u32 d;\n};\n\nstruct drm_virtgpu_3d_transfer_from_host {\n\t__u32 bo_handle;\n\tstruct drm_virtgpu_3d_box box;\n\t__u32 level;\n\t__u32 offset;\n\t__u32 stride;\n\t__u32 layer_stride;\n};\n\nstruct drm_virtgpu_3d_transfer_to_host {\n\t__u32 bo_handle;\n\tstruct drm_virtgpu_3d_box box;\n\t__u32 level;\n\t__u32 offset;\n\t__u32 stride;\n\t__u32 layer_stride;\n};\n\nstruct drm_virtgpu_3d_wait {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_virtgpu_context_init {\n\t__u32 num_params;\n\t__u32 pad;\n\t__u64 ctx_set_params;\n};\n\nstruct drm_virtgpu_context_set_param {\n\t__u64 param;\n\t__u64 value;\n};\n\nstruct drm_virtgpu_execbuffer {\n\t__u32 flags;\n\t__u32 size;\n\t__u64 command;\n\t__u64 bo_handles;\n\t__u32 num_bo_handles;\n\t__s32 fence_fd;\n\t__u32 ring_idx;\n\t__u32 syncobj_stride;\n\t__u32 num_in_syncobjs;\n\t__u32 num_out_syncobjs;\n\t__u64 in_syncobjs;\n\t__u64 out_syncobjs;\n};\n\nstruct drm_virtgpu_execbuffer_syncobj {\n\t__u32 handle;\n\t__u32 flags;\n\t__u64 point;\n};\n\nstruct drm_virtgpu_get_caps {\n\t__u32 cap_set_id;\n\t__u32 cap_set_ver;\n\t__u64 addr;\n\t__u32 size;\n\t__u32 pad;\n};\n\nstruct drm_virtgpu_getparam {\n\t__u64 param;\n\t__u64 value;\n};\n\nstruct drm_virtgpu_map {\n\t__u64 offset;\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_virtgpu_resource_create {\n\t__u32 target;\n\t__u32 format;\n\t__u32 bind;\n\t__u32 width;\n\t__u32 height;\n\t__u32 depth;\n\t__u32 array_size;\n\t__u32 last_level;\n\t__u32 nr_samples;\n\t__u32 flags;\n\t__u32 bo_handle;\n\t__u32 res_handle;\n\t__u32 size;\n\t__u32 stride;\n};\n\nstruct drm_virtgpu_resource_create_blob {\n\t__u32 blob_mem;\n\t__u32 blob_flags;\n\t__u32 bo_handle;\n\t__u32 res_handle;\n\t__u64 size;\n\t__u32 pad;\n\t__u32 cmd_size;\n\t__u64 cmd;\n\t__u64 blob_id;\n};\n\nstruct drm_virtgpu_resource_info {\n\t__u32 bo_handle;\n\t__u32 res_handle;\n\t__u32 size;\n\t__u32 blob_mem;\n};\n\nstruct drm_vma_offset_file {\n\tstruct rb_node vm_rb;\n\tstruct drm_file *vm_tag;\n\tlong unsigned int vm_count;\n};\n\nstruct drm_vma_offset_manager {\n\trwlock_t vm_lock;\n\tstruct drm_mm vm_addr_space_mm;\n};\n\nstruct drm_wait_vblank_request {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong unsigned int signal;\n};\n\nstruct drm_wait_vblank_reply {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong int tval_sec;\n\tlong int tval_usec;\n};\n\nunion drm_wait_vblank {\n\tstruct drm_wait_vblank_request request;\n\tstruct drm_wait_vblank_reply reply;\n};\n\nstruct drm_wait_vblank_request32 {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tu32 signal;\n};\n\nstruct drm_wait_vblank_reply32 {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\ts32 tval_sec;\n\ts32 tval_usec;\n};\n\nunion drm_wait_vblank32 {\n\tstruct drm_wait_vblank_request32 request;\n\tstruct drm_wait_vblank_reply32 reply;\n};\n\ntypedef union drm_wait_vblank32 drm_wait_vblank32_t;\n\nstruct drm_wedge_task_info {\n\tpid_t pid;\n\tchar comm[16];\n};\n\nstruct drm_writeback_connector {\n\tstruct drm_connector base;\n\tstruct drm_encoder encoder;\n\tstruct drm_property_blob *pixel_formats_blob_ptr;\n\tspinlock_t job_lock;\n\tstruct list_head job_queue;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n};\n\nstruct drm_writeback_job {\n\tstruct drm_writeback_connector *connector;\n\tbool prepared;\n\tstruct work_struct cleanup_work;\n\tstruct list_head list_entry;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *out_fence;\n\tvoid *priv;\n};\n\ntypedef void (*drmres_release_t)(struct drm_device *, void *);\n\nstruct drmres_node {\n\tstruct list_head entry;\n\tdrmres_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct drmres {\n\tstruct drmres_node node;\n\tu8 data[0];\n};\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct drv_cmd {\n\tstruct acpi_pct_register *reg;\n\tu32 val;\n\tunion {\n\t\tvoid (*write)(struct acpi_pct_register *, u32);\n\t\tu32 (*read)(struct acpi_pct_register *);\n\t} func;\n};\n\nstruct pci_driver;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct dst_ops;\n\nstruct uncached_list;\n\nstruct lwtunnel_state;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tvoid *__pad1;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\trcuref_t __rcuref;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n\tstruct lwtunnel_state *lwtstate;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct uart_8250_port;\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_tx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan *rxchan;\n\tstruct dma_chan *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct dw8250_port_data {\n\tint line;\n\tstruct uart_8250_dma dma;\n\tu32 cpr_value;\n\tu8 dlf_size;\n\tbool hw_rs485_support;\n};\n\nstruct dw_lli {\n\t__le32 sar;\n\t__le32 dar;\n\t__le32 llp;\n\t__le32 ctllo;\n\t__le32 ctlhi;\n\t__le32 sstat;\n\t__le32 dstat;\n};\n\nstruct dw_desc {\n\tstruct dw_lli lli;\n\tstruct list_head desc_node;\n\tstruct list_head tx_list;\n\tstruct dma_async_tx_descriptor txd;\n\tsize_t len;\n\tsize_t total_len;\n\tu32 residue;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct dw_dma_chan;\n\nstruct dw_dma_platform_data;\n\nstruct dw_dma {\n\tstruct dma_device dma;\n\tchar name[20];\n\tvoid *regs;\n\tstruct dma_pool *desc_pool;\n\tstruct tasklet_struct tasklet;\n\tstruct dw_dma_chan *chan;\n\tu8 all_chan_mask;\n\tu8 in_use;\n\tvoid (*initialize_chan)(struct dw_dma_chan *);\n\tvoid (*suspend_chan)(struct dw_dma_chan *, bool);\n\tvoid (*resume_chan)(struct dw_dma_chan *, bool);\n\tu32 (*prepare_ctllo)(struct dw_dma_chan *);\n\tu32 (*bytes2block)(struct dw_dma_chan *, size_t, unsigned int, size_t *);\n\tsize_t (*block2bytes)(struct dw_dma_chan *, u32, u32);\n\tvoid (*set_device_name)(struct dw_dma *, int);\n\tvoid (*disable)(struct dw_dma *);\n\tvoid (*enable)(struct dw_dma *);\n\tstruct dw_dma_platform_data *pdata;\n};\n\nstruct dw_dma_slave {\n\tstruct device *dma_dev;\n\tu8 src_id;\n\tu8 dst_id;\n\tu8 m_master;\n\tu8 p_master;\n\tu8 channels;\n\tbool hs_polarity;\n};\n\nstruct dw_dma_chan {\n\tstruct dma_chan chan;\n\tvoid *ch_regs;\n\tu8 mask;\n\tu8 priority;\n\tenum dma_transfer_direction direction;\n\tstruct list_head *tx_node_active;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tstruct list_head active_list;\n\tstruct list_head queue;\n\tunsigned int descs_allocated;\n\tunsigned int block_size;\n\tbool nollp;\n\tu32 max_burst;\n\tstruct dw_dma_slave dws;\n\tstruct dma_slave_config dma_sconfig;\n};\n\nstruct dw_dma_chan_regs {\n\tu32 SAR;\n\tu32 __pad_SAR;\n\tu32 DAR;\n\tu32 __pad_DAR;\n\tu32 LLP;\n\tu32 __pad_LLP;\n\tu32 CTL_LO;\n\tu32 CTL_HI;\n\tu32 SSTAT;\n\tu32 __pad_SSTAT;\n\tu32 DSTAT;\n\tu32 __pad_DSTAT;\n\tu32 SSTATAR;\n\tu32 __pad_SSTATAR;\n\tu32 DSTATAR;\n\tu32 __pad_DSTATAR;\n\tu32 CFG_LO;\n\tu32 CFG_HI;\n\tu32 SGR;\n\tu32 __pad_SGR;\n\tu32 DSR;\n\tu32 __pad_DSR;\n};\n\nstruct dw_dma_chip {\n\tstruct device *dev;\n\tint id;\n\tint irq;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct dw_dma *dw;\n\tconst struct dw_dma_platform_data *pdata;\n};\n\nstruct dw_dma_chip_pdata {\n\tconst struct dw_dma_platform_data *pdata;\n\tint (*probe)(struct dw_dma_chip *);\n\tint (*remove)(struct dw_dma_chip *);\n\tstruct dw_dma_chip *chip;\n\tu8 m_master;\n\tu8 p_master;\n};\n\nstruct dw_dma_irq_regs {\n\tu32 XFER;\n\tu32 __pad_XFER;\n\tu32 BLOCK;\n\tu32 __pad_BLOCK;\n\tu32 SRC_TRAN;\n\tu32 __pad_SRC_TRAN;\n\tu32 DST_TRAN;\n\tu32 __pad_DST_TRAN;\n\tu32 ERROR;\n\tu32 __pad_ERROR;\n};\n\nstruct dw_dma_platform_data {\n\tu32 nr_masters;\n\tu32 nr_channels;\n\tu32 chan_allocation_order;\n\tu32 chan_priority;\n\tu32 block_size;\n\tu32 data_width[4];\n\tu32 multi_block[8];\n\tu32 max_burst[8];\n\tu32 protctl;\n\tu32 quirks;\n};\n\nstruct dw_dma_regs {\n\tstruct dw_dma_chan_regs CHAN[8];\n\tstruct dw_dma_irq_regs RAW;\n\tstruct dw_dma_irq_regs STATUS;\n\tstruct dw_dma_irq_regs MASK;\n\tstruct dw_dma_irq_regs CLEAR;\n\tu32 STATUS_INT;\n\tu32 __pad_STATUS_INT;\n\tu32 REQ_SRC;\n\tu32 __pad_REQ_SRC;\n\tu32 REQ_DST;\n\tu32 __pad_REQ_DST;\n\tu32 SGL_REQ_SRC;\n\tu32 __pad_SGL_REQ_SRC;\n\tu32 SGL_REQ_DST;\n\tu32 __pad_SGL_REQ_DST;\n\tu32 LAST_SRC;\n\tu32 __pad_LAST_SRC;\n\tu32 LAST_DST;\n\tu32 __pad_LAST_DST;\n\tu32 CFG;\n\tu32 __pad_CFG;\n\tu32 CH_EN;\n\tu32 __pad_CH_EN;\n\tu32 ID;\n\tu32 __pad_ID;\n\tu32 TEST;\n\tu32 __pad_TEST;\n\tu32 CLASS_PRIORITY0;\n\tu32 __pad_CLASS_PRIORITY0;\n\tu32 CLASS_PRIORITY1;\n\tu32 __pad_CLASS_PRIORITY1;\n\tu32 __reserved;\n\tu32 DWC_PARAMS[8];\n\tu32 MULTI_BLK_TYPE;\n\tu32 MAX_BLK_SIZE;\n\tu32 DW_PARAMS;\n\tu32 COMP_TYPE;\n\tu32 COMP_VERSION;\n\tu32 FIFO_PARTITION0;\n\tu32 __pad_FIFO_PARTITION0;\n\tu32 FIFO_PARTITION1;\n\tu32 __pad_FIFO_PARTITION1;\n\tu32 SAI_ERR;\n\tu32 __pad_SAI_ERR;\n\tu32 GLOBAL_CFG;\n\tu32 __pad_GLOBAL_CFG;\n};\n\nstruct dyn_arch_ftrace {};\n\nstruct dyn_event_operations;\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(const char *);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dyn_ftrace {\n\tlong unsigned int ip;\n\tlong unsigned int flags;\n\tstruct dyn_arch_ftrace arch;\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct e820_entry {\n\tu64 addr;\n\tu64 size;\n\tenum e820_type type;\n} __attribute__((packed));\n\nstruct e820_table {\n\tu32 nr_entries;\n\tstruct e820_entry entries[320];\n};\n\nstruct early_boot_kfree_rcu {\n\tstruct callback_head rh;\n};\n\nstruct early_load_data {\n\tu32 old_rev;\n\tu32 new_rev;\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\tunion {\n\t\t__u32 padding[5];\n\t\tstruct {\n\t\t\t__u8 addr_recv;\n\t\t\t__u8 addr_dest;\n\t\t\t__u8 padding0[2];\n\t\t\t__u32 padding1[4];\n\t\t};\n\t};\n};\n\nstruct gpio_desc;\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct ktermios;\n\nstruct uart_state;\n\nstruct uart_ops;\n\nstruct serial_port_device;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int ctrl_id;\n\tunsigned int port_id;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char quirks;\n\tenum uart_iotype iotype;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tupf_t flags;\n\tupstat_t status;\n\tbool hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int frame_time;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tstruct serial_port_device *port_dev;\n\tlong unsigned int sysrq;\n\tu8 sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tunsigned char console_reinit;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct serial_rs485 rs485_supported;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct gpio_desc *rs485_rx_during_tx_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tstruct uart_port port;\n\tchar options[32];\n\tunsigned int baud;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nstruct eb_fence {\n\tstruct drm_syncobj *syncobj;\n\tstruct dma_fence *dma_fence;\n\tu64 value;\n\tstruct dma_fence_chain *chain_fence;\n};\n\nstruct eb_vma {\n\tstruct i915_vma *vma;\n\tunsigned int flags;\n\tstruct drm_i915_gem_exec_object2 *exec;\n\tstruct list_head bind_link;\n\tstruct list_head reloc_link;\n\tstruct hlist_node node;\n\tu32 handle;\n};\n\nstruct est_timings {\n\tu8 t1;\n\tu8 t2;\n\tu8 mfg_rsvd;\n};\n\nstruct edid {\n\tu8 header[8];\n\tunion {\n\t\tstruct drm_edid_product_id product_id;\n\t\tstruct {\n\t\t\tu8 mfg_id[2];\n\t\t\tu8 prod_code[2];\n\t\t\tu32 serial;\n\t\t\tu8 mfg_week;\n\t\t\tu8 mfg_year;\n\t\t} __attribute__((packed));\n\t};\n\tu8 version;\n\tu8 revision;\n\tu8 input;\n\tu8 width_cm;\n\tu8 height_cm;\n\tu8 gamma;\n\tu8 features;\n\tu8 red_green_lo;\n\tu8 blue_white_lo;\n\tu8 red_x;\n\tu8 red_y;\n\tu8 green_x;\n\tu8 green_y;\n\tu8 blue_x;\n\tu8 blue_y;\n\tu8 white_x;\n\tu8 white_y;\n\tstruct est_timings established_timings;\n\tstruct std_timing standard_timings[8];\n\tstruct detailed_timing detailed_timings[4];\n\tu8 extensions;\n\tu8 checksum;\n};\n\nstruct edid_quirk {\n\tconst struct drm_edid_ident ident;\n\tu32 quirks;\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[2];\n\tlong unsigned int advertised[2];\n\tlong unsigned int lp_advertised[2];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct eeepc_cpufv {\n\tint num;\n\tint cur;\n};\n\nstruct rfkill;\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct led_pattern;\n\nstruct led_trigger;\n\nstruct led_hw_trigger_type;\n\nstruct led_classdev {\n\tconst char *name;\n\tunsigned int brightness;\n\tunsigned int max_brightness;\n\tunsigned int color;\n\tint flags;\n\tlong unsigned int work_flags;\n\tvoid (*brightness_set)(struct led_classdev *, enum led_brightness);\n\tint (*brightness_set_blocking)(struct led_classdev *, enum led_brightness);\n\tenum led_brightness (*brightness_get)(struct led_classdev *);\n\tint (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *);\n\tint (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int);\n\tint (*pattern_clear)(struct led_classdev *);\n\tstruct device *dev;\n\tconst struct attribute_group **groups;\n\tstruct list_head node;\n\tconst char *default_trigger;\n\tlong unsigned int blink_delay_on;\n\tlong unsigned int blink_delay_off;\n\tstruct timer_list blink_timer;\n\tint blink_brightness;\n\tint new_blink_brightness;\n\tvoid (*flash_resume)(struct led_classdev *);\n\tstruct workqueue_struct *wq;\n\tstruct work_struct set_brightness_work;\n\tint delayed_set_value;\n\tlong unsigned int delayed_delay_on;\n\tlong unsigned int delayed_delay_off;\n\tstruct rw_semaphore trigger_lock;\n\tstruct led_trigger *trigger;\n\tstruct list_head trig_list;\n\tvoid *trigger_data;\n\tbool activated;\n\tstruct led_hw_trigger_type *trigger_type;\n\tconst char *hw_control_trigger;\n\tint (*hw_control_is_supported)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_set)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_get)(struct led_classdev *, long unsigned int *);\n\tstruct device * (*hw_control_get_device)(struct led_classdev *);\n\tstruct mutex led_access;\n};\n\nstruct eeepc_laptop {\n\tacpi_handle handle;\n\tu32 cm_supported;\n\tbool cpufv_disabled;\n\tbool hotplug_disabled;\n\tu16 event_count[128];\n\tstruct platform_device *platform_device;\n\tstruct acpi_device *device;\n\tstruct backlight_device *backlight_device;\n\tstruct input_dev *inputdev;\n\tstruct rfkill *wlan_rfkill;\n\tstruct rfkill *bluetooth_rfkill;\n\tstruct rfkill *wwan3g_rfkill;\n\tstruct rfkill *wimax_rfkill;\n\tstruct hotplug_slot hotplug_slot;\n\tstruct mutex hotplug_lock;\n\tstruct led_classdev tpd_led;\n\tint tpd_led_wk;\n\tstruct workqueue_struct *led_workqueue;\n\tstruct work_struct tpd_led_work;\n};\n\nstruct eeprom_93cx6 {\n\tvoid *data;\n\tvoid (*register_read)(struct eeprom_93cx6 *);\n\tvoid (*register_write)(struct eeprom_93cx6 *);\n\tint width;\n\tunsigned int quirks;\n\tchar drive_data;\n\tchar reg_data_in;\n\tchar reg_data_out;\n\tchar reg_data_clock;\n\tchar reg_chip_select;\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\ntypedef efi_status_t efi_get_time_t(efi_time_t *, efi_time_cap_t *);\n\ntypedef efi_status_t efi_set_time_t(efi_time_t *);\n\ntypedef efi_status_t efi_get_wakeup_time_t(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\ntypedef efi_status_t efi_set_wakeup_time_t(efi_bool_t, efi_time_t *);\n\ntypedef efi_status_t efi_get_variable_t(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\ntypedef efi_status_t efi_get_next_variable_t(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\ntypedef efi_status_t efi_set_variable_t(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\ntypedef efi_status_t efi_query_variable_info_t(u32, u64 *, u64 *, u64 *);\n\ntypedef efi_status_t efi_update_capsule_t(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\ntypedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\ntypedef efi_status_t efi_get_next_high_mono_count_t(u32 *);\n\ntypedef void efi_reset_system_t(int, efi_status_t, long unsigned int, efi_char16_t *);\n\nstruct efi_memory_map {\n\tphys_addr_t phys_map;\n\tvoid *map;\n\tvoid *map_end;\n\tint nr_map;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nstruct efi {\n\tconst efi_runtime_services_t *runtime;\n\tunsigned int runtime_version;\n\tunsigned int runtime_supported_mask;\n\tlong unsigned int acpi;\n\tlong unsigned int acpi20;\n\tlong unsigned int smbios;\n\tlong unsigned int smbios3;\n\tlong unsigned int esrt;\n\tlong unsigned int tpm_log;\n\tlong unsigned int tpm_final_log;\n\tlong unsigned int ovmf_debug_log;\n\tlong unsigned int mokvar_table;\n\tlong unsigned int coco_secret;\n\tlong unsigned int unaccepted;\n\tefi_get_time_t *get_time;\n\tefi_set_time_t *set_time;\n\tefi_get_wakeup_time_t *get_wakeup_time;\n\tefi_set_wakeup_time_t *set_wakeup_time;\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_info_t *query_variable_info;\n\tefi_query_variable_info_t *query_variable_info_nonblocking;\n\tefi_update_capsule_t *update_capsule;\n\tefi_query_capsule_caps_t *query_capsule_caps;\n\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\tefi_reset_system_t *reset_system;\n\tstruct efi_memory_map memmap;\n\tlong unsigned int flags;\n};\n\nstruct efi_mem_range {\n\tstruct range range;\n\tu64 attribute;\n};\n\nstruct efi_memory_map_data {\n\tphys_addr_t phys_map;\n\tlong unsigned int size;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nunion efi_rts_args {\n\tstruct {\n\t\tefi_time_t *time;\n\t\tefi_time_cap_t *capabilities;\n\t} GET_TIME;\n\tstruct {\n\t\tefi_time_t *time;\n\t} SET_TIME;\n\tstruct {\n\t\tefi_bool_t *enabled;\n\t\tefi_bool_t *pending;\n\t\tefi_time_t *time;\n\t} GET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_bool_t enable;\n\t\tefi_time_t *time;\n\t} SET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 *attr;\n\t\tlong unsigned int *data_size;\n\t\tvoid *data;\n\t} GET_VARIABLE;\n\tstruct {\n\t\tlong unsigned int *name_size;\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t} GET_NEXT_VARIABLE;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 attr;\n\t\tlong unsigned int data_size;\n\t\tvoid *data;\n\t} SET_VARIABLE;\n\tstruct {\n\t\tu32 attr;\n\t\tu64 *storage_space;\n\t\tu64 *remaining_space;\n\t\tu64 *max_variable_size;\n\t} QUERY_VARIABLE_INFO;\n\tstruct {\n\t\tu32 *high_count;\n\t} GET_NEXT_HIGH_MONO_COUNT;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tlong unsigned int sg_list;\n\t} UPDATE_CAPSULE;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tu64 *max_size;\n\t\tint *reset_type;\n\t} QUERY_CAPSULE_CAPS;\n\tstruct {\n\t\tefi_status_t (*acpi_prm_handler)(u64, void *);\n\t\tu64 param_buffer_addr;\n\t\tvoid *context;\n\t} ACPI_PRM_HANDLER;\n};\n\nstruct efi_runtime_map_entry {\n\tefi_memory_desc_t md;\n\tstruct kobject kobj;\n};\n\nstruct efi_runtime_work {\n\tunion efi_rts_args *args;\n\tefi_status_t status;\n\tstruct work_struct work;\n\tenum efi_rts_ids efi_rts_id;\n\tstruct completion efi_rts_comp;\n\tconst void *caller;\n};\n\nstruct efi_setup_data {\n\tu64 fw_vendor;\n\tu64 __unused;\n\tu64 tables;\n\tu64 smbios;\n\tu64 reserved[8];\n};\n\nstruct efi_system_resource_entry_v1 {\n\tefi_guid_t fw_class;\n\tu32 fw_type;\n\tu32 fw_version;\n\tu32 lowest_supported_fw_version;\n\tu32 capsule_flags;\n\tu32 last_attempt_version;\n\tu32 last_attempt_status;\n};\n\nstruct efi_system_resource_table {\n\tu32 fw_resource_count;\n\tu32 fw_resource_count_max;\n\tu64 fw_resource_version;\n\tu8 entries[0];\n};\n\nstruct efi_tcg2_final_events_table {\n\tu64 version;\n\tu64 nr_events;\n\tu8 events[0];\n};\n\nstruct efi_unaccepted_memory {\n\tu32 version;\n\tu32 unit_size;\n\tu64 phys_base;\n\tu64 size;\n\tlong unsigned int bitmap[0];\n};\n\nstruct efifb_dmi_info {\n\tchar *optname;\n\tlong unsigned int base;\n\tint stride;\n\tint width;\n\tint height;\n\tint flags;\n};\n\nstruct efifb_mode_fixup {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int linelength;\n};\n\ntypedef efi_status_t efi_query_variable_store_t(u32, long unsigned int, bool);\n\nstruct efivar_operations {\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_store_t *query_variable_store;\n\tefi_query_variable_info_t *query_variable_info;\n};\n\nstruct efivars {\n\tstruct kset *kset;\n\tconst struct efivar_operations *ops;\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct ehci_dev {\n\tu32 bus;\n\tu32 slot;\n\tu32 func;\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tunion {\n\t\tu32 port_status[15];\n\t\tstruct {\n\t\t\tu32 reserved3[9];\n\t\t\tu32 usbmode;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved4;\n\t\t\tu32 hostpc[15];\n\t\t};\n\t\tu32 brcm_insnreg[4];\n\t};\n\tu32 reserved5[2];\n\tu32 usbmode_ex;\n};\n\nstruct elevator_queue;\n\nstruct io_cq;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf32_shdr {\n\tElf32_Word sh_name;\n\tElf32_Word sh_type;\n\tElf32_Word sh_flags;\n\tElf32_Addr sh_addr;\n\tElf32_Off sh_offset;\n\tElf32_Word sh_size;\n\tElf32_Word sh_link;\n\tElf32_Word sh_info;\n\tElf32_Word sh_addralign;\n\tElf32_Word sh_entsize;\n};\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_note {\n\tElf64_Word n_namesz;\n\tElf64_Word n_descsz;\n\tElf64_Word n_type;\n};\n\ntypedef struct elf64_note Elf64_Nhdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct elf64_rela {\n\tElf64_Addr r_offset;\n\tElf64_Xword r_info;\n\tElf64_Sxword r_addend;\n};\n\ntypedef struct elf64_rela Elf64_Rela;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\ntypedef struct elf64_shdr Elf64_Shdr;\n\nstruct elf64_sym {\n\tElf64_Word st_name;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf64_Half st_shndx;\n\tElf64_Addr st_value;\n\tElf64_Xword st_size;\n};\n\ntypedef struct elf64_sym Elf64_Sym;\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tcompat_siginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info___2;\n\nstruct elf_note_info___2 {\n\tstruct elf_thread_core_info___2 *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info___2 {\n\tstruct elf_thread_core_info___2 *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct compat_elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct trace_event_file;\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nunion encrypted_buff {\n\tu8 e_kpub_km[128];\n\tu8 e_kh_km_m[32];\n\tstruct {\n\t\tu8 e_kh_km[16];\n\t\tu8 m[16];\n\t};\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct engine_mmio_base {\n\tu32 graphics_ver: 8;\n\tu32 base: 24;\n};\n\nstruct engine_info {\n\tu8 class;\n\tu8 instance;\n\tstruct engine_mmio_base mmio_bases[3];\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n} __attribute__((packed));\n\nstruct epoll_event {\n\t__poll_t events;\n\t__u64 data;\n} __attribute__((packed));\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct trace_eprobe;\n\nstruct eprobe_data {\n\tstruct trace_event_file *file;\n\tstruct trace_eprobe *ep;\n};\n\nstruct eprobe_trace_entry_head {\n\tstruct trace_entry ent;\n};\n\nstruct equiv_cpu_entry {\n\tu32 installed_cpu;\n\tu32 fixed_errata_mask;\n\tu32 fixed_errata_compare;\n\tu16 equiv_cpu;\n\tu16 res;\n};\n\nstruct equiv_cpu_table {\n\tunsigned int num_entries;\n\tstruct equiv_cpu_entry *entry;\n};\n\nstruct er_account {\n\traw_spinlock_t lock;\n\tu64 config;\n\tu64 reg;\n\tatomic_t ref;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu16 pos;\n\tu64 ts;\n};\n\nstruct error_info {\n\tshort unsigned int code12;\n\tshort unsigned int size;\n};\n\nstruct error_info2 {\n\tunsigned char code1;\n\tunsigned char code2_min;\n\tunsigned char code2_max;\n\tconst char *str;\n\tconst char *fmt;\n};\n\nstruct errormap {\n\tchar *name;\n\tint val;\n\tint namelen;\n\tstruct hlist_node list;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct watchdog_info;\n\nstruct watchdog_ops;\n\nstruct watchdog_governor;\n\nstruct watchdog_core_data;\n\nstruct watchdog_device {\n\tint id;\n\tstruct device *parent;\n\tconst struct attribute_group **groups;\n\tconst struct watchdog_info *info;\n\tconst struct watchdog_ops *ops;\n\tconst struct watchdog_governor *gov;\n\tunsigned int bootstatus;\n\tunsigned int timeout;\n\tunsigned int pretimeout;\n\tunsigned int min_timeout;\n\tunsigned int max_timeout;\n\tunsigned int min_hw_heartbeat_ms;\n\tunsigned int max_hw_heartbeat_ms;\n\tstruct notifier_block reboot_nb;\n\tstruct notifier_block restart_nb;\n\tstruct notifier_block pm_nb;\n\tvoid *driver_data;\n\tstruct watchdog_core_data *wd_data;\n\tlong unsigned int status;\n\tstruct list_head deferred;\n};\n\nstruct esb_dev {\n\tstruct watchdog_device wdd;\n\tvoid *base;\n\tstruct pci_dev *pdev;\n};\n\nstruct x86_emulate_ctxt;\n\nstruct group_dual;\n\nstruct gprefix;\n\nstruct escape;\n\nstruct instr_dual;\n\nstruct mode_dual;\n\nstruct opcode {\n\tu64 flags;\n\tu8 intercept;\n\tu8 pad[7];\n\tunion {\n\t\tint (*execute)(struct x86_emulate_ctxt *);\n\t\tconst struct opcode *group;\n\t\tconst struct group_dual *gdual;\n\t\tconst struct gprefix *gprefix;\n\t\tconst struct escape *esc;\n\t\tconst struct instr_dual *idual;\n\t\tconst struct mode_dual *mdual;\n\t} u;\n\tint (*check_perm)(struct x86_emulate_ctxt *);\n};\n\nstruct escape {\n\tstruct opcode op[8];\n\tstruct opcode high[64];\n};\n\nstruct esre_entry;\n\nstruct esre_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct esre_entry *, char *);\n};\n\nstruct esre_entry {\n\tunion {\n\t\tstruct efi_system_resource_entry_v1 *esre1;\n\t} esre;\n\tstruct kobject kobj;\n\tstruct list_head list;\n};\n\nstruct estack_pages {\n\tu32 offs;\n\tu16 size;\n\tu16 type;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct genl_info;\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct firmware;\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[2];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[2];\n\t\tlong unsigned int advertising[2];\n\t\tlong unsigned int lp_advertising[2];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_regs;\n\nstruct ethtool_wolinfo;\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_test;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxnfc;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_ts_stats;\n\nstruct ethtool_tunable;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_device;\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\t__u64 ring_cookie;\n\t__u32 location;\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct input_handler;\n\nstruct input_value;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct fasync_struct;\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct event_trigger_data;\n\nstruct ring_buffer_event;\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*parse)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*trigger)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tbool (*count_func)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_data *);\n};\n\nstruct event_counter {\n\tu32 count;\n\tu32 flags;\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nstruct event_mod_load {\n\tstruct list_head list;\n\tchar *module;\n\tchar *match;\n\tchar *system;\n\tchar *event;\n};\n\nstruct event_probe_data {\n\tstruct trace_event_file *file;\n\tlong unsigned int count;\n\tint ref;\n\tbool enable;\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tint flags;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n\tstruct llist_node llist;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventfs_attr {\n\tint mode;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\ntypedef int (*eventfs_callback)(const char *, umode_t *, void **, const struct file_operations **);\n\ntypedef void (*eventfs_release)(const char *, void *);\n\nstruct eventfs_entry {\n\tconst char *name;\n\teventfs_callback callback;\n\teventfs_release release;\n};\n\nstruct eventfs_inode {\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head children;\n\tconst struct eventfs_entry *entries;\n\tconst char *name;\n\tstruct eventfs_attr *entry_attrs;\n\tvoid *data;\n\tstruct eventfs_attr attr;\n\tstruct kref kref;\n\tunsigned int is_freed: 1;\n\tunsigned int is_events: 1;\n\tunsigned int nr_entries: 30;\n\tunsigned int ino;\n};\n\nstruct eventfs_root_inode {\n\tstruct eventfs_inode ei;\n\tstruct dentry *events_dir;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n\tu8 nests;\n};\n\nstruct evmcs_field {\n\tu16 offset;\n\tu16 clean_field;\n};\n\nstruct ewma__engine_latency {\n\tlong unsigned int internal;\n};\n\nstruct ewma_pkt_len {\n\tlong unsigned int internal;\n};\n\nstruct ewma_runtime {\n\tlong unsigned int internal;\n};\n\nstruct exar8250_board;\n\nstruct exar8250 {\n\tunsigned int nr;\n\tunsigned int osc_freq;\n\tstruct exar8250_board *board;\n\tstruct eeprom_93cx6 eeprom;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tconst struct serial_rs485 *rs485_supported;\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n\tvoid (*unregister_gpio)(struct uart_8250_port *);\n};\n\nstruct exception_stacks {\n\tchar DF_stack_guard[0];\n\tchar DF_stack[8192];\n\tchar NMI_stack_guard[0];\n\tchar NMI_stack[8192];\n\tchar DB_stack_guard[0];\n\tchar DB_stack[8192];\n\tchar MCE_stack_guard[0];\n\tchar MCE_stack[8192];\n\tchar VC_stack_guard[0];\n\tchar VC_stack[0];\n\tchar VC2_stack_guard[0];\n\tchar VC2_stack[0];\n\tchar IST_top_guard[0];\n};\n\nstruct exception_table_entry {\n\tint insn;\n\tint fixup;\n\tint data;\n};\n\nstruct exceptional_entry_key {\n\tstruct xarray *xa;\n\tlong unsigned int entry_start;\n};\n\nstruct exec_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct i915_request;\n\nstruct execlists_capture {\n\tstruct work_struct work;\n\tstruct i915_request *rq;\n\tstruct i915_gpu_coredump *error;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t\tstruct lockdep_map *ma_external_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct execmem_cache {\n\tstruct mutex mutex;\n\tstruct maple_tree busy_areas;\n\tstruct maple_tree free_areas;\n\tunsigned int pending_free_cnt;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_cb {\n\tstruct irq_work work;\n\tstruct i915_sw_fence *fence;\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct exit_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__u32 exit_code;\n\t__u32 exit_signal;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct iattr;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n};\n\nstruct msg_msg;\n\nstruct ext_wait_queue {\n\tstruct task_struct *task;\n\tstruct list_head list;\n\tstruct msg_msg *msg;\n\tint state;\n};\n\nstruct extended_signature {\n\tunsigned int sig;\n\tunsigned int pf;\n\tunsigned int cksum;\n};\n\nstruct extended_sigtable {\n\tunsigned int count;\n\tunsigned int cksum;\n\tunsigned int reserved[3];\n\tstruct extended_signature sigs[0];\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct extra_reg {\n\tunsigned int event;\n\tunsigned int msr;\n\tu64 config_mask;\n\tu64 valid_mask;\n\tint idx;\n\tbool extra_msr_access;\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct failover_ops;\n\nstruct failover {\n\tstruct list_head list;\n\tstruct net_device *failover_dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct failover_ops *ops;\n};\n\nstruct failover_ops {\n\tint (*slave_pre_register)(struct net_device *, struct net_device *);\n\tint (*slave_register)(struct net_device *, struct net_device *);\n\tint (*slave_pre_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_link_change)(struct net_device *, struct net_device *);\n\tint (*slave_name_change)(struct net_device *, struct net_device *);\n\trx_handler_result_t (*slave_handle_frame)(struct sk_buff **);\n};\n\nstruct fanout_args {\n\t__u16 id;\n\t__u16 type_flags;\n\t__u32 max_num_members;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fault_attr {};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_address {\n\tvoid *address;\n\tint bits;\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_bitmap4x_iter {\n\tconst u8 *data;\n\tu32 fgxcolor;\n\tu32 bgcolor;\n\tint width;\n\tint i;\n\tconst u32 *expand;\n\tint bpp;\n\tbool top;\n};\n\nstruct fb_bitmap_iter {\n\tconst u8 *data;\n\tlong unsigned int colors[2];\n\tint width;\n\tint i;\n};\n\nstruct fb_blit_caps {\n\tlong unsigned int x[1];\n\tlong unsigned int y[2];\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_cmap32 {\n\tu32 start;\n\tu32 len;\n\tcompat_caddr_t red;\n\tcompat_caddr_t green;\n\tcompat_caddr_t blue;\n\tcompat_caddr_t transp;\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_reverse {\n\tbool byte;\n\tbool pixel;\n};\n\nstruct fb_color_iter {\n\tconst u8 *data;\n\tconst u32 *palette;\n\tstruct fb_reverse reverse;\n\tint shift;\n\tint width;\n\tint i;\n};\n\nstruct fb_con2fbmap {\n\t__u32 console;\n\t__u32 framebuffer;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_fix_screeninfo32 {\n\tchar id[16];\n\tcompat_caddr_t smem_start;\n\tu32 smem_len;\n\tu32 type;\n\tu32 type_aux;\n\tu32 visual;\n\tu16 xpanstep;\n\tu16 ypanstep;\n\tu16 ywrapstep;\n\tu32 line_length;\n\tcompat_caddr_t mmio_start;\n\tu32 mmio_len;\n\tu32 accel;\n\tu16 reserved[3];\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_videomode;\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_info;\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tlong unsigned int blit_x[1];\n\tlong unsigned int blit_y[2];\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct lcd_device;\n\nstruct fb_ops;\n\nstruct fbcon_par;\n\nstruct fb_info {\n\trefcount_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tint blank;\n\tstruct lcd_device *lcd_dev;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tstruct device *dev;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tstruct fbcon_par *fbcon_par;\n\tvoid *par;\n\tbool skip_vt_switch;\n\tbool skip_panic;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n};\n\nstruct fb_pattern {\n\tlong unsigned int pixels;\n\tint left;\n\tint right;\n\tstruct fb_reverse reverse;\n};\n\nstruct fb_plane_view_dims {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int tile_width;\n\tunsigned int tile_height;\n};\n\nstruct fbcon_bitops {\n\tvoid (*bmove)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*clear)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*putcs)(struct vc_data *, struct fb_info *, const short unsigned int *, int, int, int, int, int);\n\tvoid (*clear_margins)(struct vc_data *, struct fb_info *, int, int);\n\tvoid (*cursor)(struct vc_data *, struct fb_info *, bool, int, int);\n\tint (*update_start)(struct fb_info *);\n\tint (*rotate_font)(struct fb_info *, struct vc_data *);\n};\n\nstruct fbcon_display {\n\tconst u_char *fontdata;\n\tint userfont;\n\tshort int yscroll;\n\tint vrows;\n\tint cursor_shape;\n\tint con_rotate;\n\tu32 xres_virtual;\n\tu32 yres_virtual;\n\tu32 height;\n\tu32 width;\n\tu32 bits_per_pixel;\n\tu32 grayscale;\n\tu32 nonstd;\n\tu32 accel_flags;\n\tu32 rotate;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tconst struct fb_videomode *mode;\n};\n\nstruct fbcon_par {\n\tstruct fb_var_screeninfo var;\n\tstruct delayed_work cursor_work;\n\tstruct fb_cursor cursor_state;\n\tstruct fbcon_display *p;\n\tstruct fb_info *info;\n\tint currcon;\n\tint cur_blink_jiffies;\n\tint cursor_flash;\n\tint cursor_reset;\n\tint blank_state;\n\tint graphics;\n\tbool initialized;\n\tint rotate;\n\tint cur_rotate;\n\tchar *cursor_data;\n\tu8 *fontbuffer;\n\tu8 *fontdata;\n\tu8 *cursor_src;\n\tu32 cursor_size;\n\tu32 fd_size;\n\tconst struct fbcon_bitops *bitops;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[2];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct fetch_cache {\n\tu8 data[15];\n\tu8 *ptr;\n\tu8 *end;\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct trace_seq;\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tbool is_signed;\n\tbool is_string;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[2];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct ff_periodic_effect_compat {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\tcompat_uptr_t custom_data;\n};\n\nstruct ff_effect_compat {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect_compat periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t} u;\n};\n\nstruct fgraph_cpu_data {\n\tpid_t last_pid;\n\tint depth;\n\tint depth_irq;\n\tint ignore;\n\tlong unsigned int enter_funcs[50];\n};\n\nstruct ftrace_graph_ent {\n\tlong unsigned int func;\n\tlong int depth;\n};\n\nstruct ftrace_graph_ent_entry {\n\tstruct trace_entry ent;\n\tstruct ftrace_graph_ent graph_ent;\n\tlong unsigned int args[0];\n};\n\nstruct fgraph_ent_args {\n\tstruct ftrace_graph_ent_entry ent;\n\tlong unsigned int args[6];\n};\n\nstruct fgraph_retaddr_ent_args {\n\tstruct ftrace_graph_ent_entry ent;\n\tlong unsigned int args[6];\n};\n\nstruct ftrace_graph_ret {\n\tlong unsigned int func;\n\tint depth;\n\tunsigned int overrun;\n};\n\nstruct ftrace_graph_ret_entry {\n\tstruct trace_entry ent;\n\tstruct ftrace_graph_ret ret;\n\tlong long unsigned int calltime;\n\tlong long unsigned int rettime;\n};\n\nstruct fgraph_data {\n\tstruct fgraph_cpu_data *cpu_data;\n\tunion {\n\t\tstruct fgraph_ent_args ent;\n\t\tstruct fgraph_retaddr_ent_args rent;\n\t};\n\tstruct ftrace_graph_ret_entry ret;\n\tint failed;\n\tint cpu;\n};\n\nstruct fgraph_ops;\n\nstruct ftrace_regs;\n\ntypedef int (*trace_func_graph_ent_t)(struct ftrace_graph_ent *, struct fgraph_ops *, struct ftrace_regs *);\n\ntypedef void (*trace_func_graph_ret_t)(struct ftrace_graph_ret *, struct fgraph_ops *, struct ftrace_regs *);\n\ntypedef void (*ftrace_func_t)(long unsigned int, long unsigned int, struct ftrace_ops *, struct ftrace_regs *);\n\nstruct ftrace_hash;\n\nstruct ftrace_ops_hash {\n\tstruct ftrace_hash *notrace_hash;\n\tstruct ftrace_hash *filter_hash;\n\tstruct mutex regex_lock;\n};\n\ntypedef int (*ftrace_ops_func_t)(struct ftrace_ops *, long unsigned int, enum ftrace_ops_cmd);\n\nstruct ftrace_ops {\n\tftrace_func_t func;\n\tstruct ftrace_ops *next;\n\tlong unsigned int flags;\n\tvoid *private;\n\tftrace_func_t saved_func;\n\tstruct ftrace_ops_hash local_hash;\n\tstruct ftrace_ops_hash *func_hash;\n\tstruct ftrace_ops_hash old_hash;\n\tlong unsigned int trampoline;\n\tlong unsigned int trampoline_size;\n\tstruct list_head list;\n\tstruct list_head subop_list;\n\tftrace_ops_func_t ops_func;\n\tstruct ftrace_ops *managed;\n\tlong unsigned int direct_call;\n};\n\nstruct fgraph_ops {\n\ttrace_func_graph_ent_t entryfunc;\n\ttrace_func_graph_ret_t retfunc;\n\tstruct ftrace_ops ops;\n\tvoid *private;\n\ttrace_func_graph_ent_t saved_func;\n\tint idx;\n};\n\nstruct fgraph_times {\n\tlong long unsigned int calltime;\n\tlong long unsigned int sleeptime;\n};\n\nstruct fib_kuid_range {\n\tkuid_t start;\n\tkuid_t end;\n};\n\nstruct fib_rule_port_range {\n\t__u16 start;\n\t__u16 end;\n};\n\nstruct fib_rule {\n\tstruct list_head list;\n\tint iifindex;\n\tint oifindex;\n\tu32 mark;\n\tu32 mark_mask;\n\tu32 flags;\n\tu32 table;\n\tu8 action;\n\tu8 l3mdev;\n\tu8 proto;\n\tu8 ip_proto;\n\tu32 target;\n\t__be64 tun_id;\n\tstruct fib_rule *ctarget;\n\tstruct net *fr_net;\n\trefcount_t refcnt;\n\tu32 pref;\n\tint suppress_ifgroup;\n\tint suppress_prefixlen;\n\tchar iifname[16];\n\tchar oifname[16];\n\tstruct fib_kuid_range uid_range;\n\tstruct fib_rule_port_range sport_range;\n\tstruct fib_rule_port_range dport_range;\n\tu16 sport_mask;\n\tu16 dport_mask;\n\tu8 iif_is_l3_master;\n\tu8 oif_is_l3_master;\n\tstruct callback_head rcu;\n};\n\nstruct fib4_rule {\n\tstruct fib_rule common;\n\tu8 dst_len;\n\tu8 src_len;\n\tdscp_t dscp;\n\tdscp_t dscp_mask;\n\tu8 dscp_full: 1;\n\t__be32 src;\n\t__be32 srcmask;\n\t__be32 dst;\n\t__be32 dstmask;\n};\n\nstruct nlmsghdr;\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct fib6_node;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_lookup_arg {\n\tvoid *lookup_ptr;\n\tconst void *lookup_data;\n\tvoid *result;\n\tstruct fib_rule *rule;\n\tu32 table;\n\tint flags;\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tloff_t pos;\n\tt_key key;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_rule_hdr {\n\t__u8 family;\n\t__u8 dst_len;\n\t__u8 src_len;\n\t__u8 tos;\n\t__u8 table;\n\t__u8 res1;\n\t__u8 res2;\n\t__u8 action;\n\t__u32 flags;\n};\n\nstruct fib_rule_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_rule *rule;\n};\n\nstruct fib_rule_uid_range {\n\t__u32 start;\n\t__u32 end;\n};\n\nstruct flowi;\n\nstruct fib_rules_ops {\n\tint family;\n\tstruct list_head list;\n\tint rule_size;\n\tint addr_size;\n\tint unresolved_rules;\n\tint nr_goto_rules;\n\tunsigned int fib_rules_seq;\n\tint (*action)(struct fib_rule *, struct flowi *, int, struct fib_lookup_arg *);\n\tbool (*suppress)(struct fib_rule *, int, struct fib_lookup_arg *);\n\tint (*match)(struct fib_rule *, struct flowi *, int);\n\tint (*configure)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*delete)(struct fib_rule *);\n\tint (*compare)(struct fib_rule *, struct fib_rule_hdr *, struct nlattr **);\n\tint (*fill)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *);\n\tsize_t (*nlmsg_payload)(struct fib_rule *);\n\tvoid (*flush_cache)(struct fib_rules_ops *);\n\tint nlgroup;\n\tstruct list_head rules_list;\n\tstruct module *owner;\n\tstruct net *fro_net;\n\tstruct callback_head rcu;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} __attribute__((packed)) i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\ntypedef struct file *class_gmem_get_file_t;\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct io_uring_cmd;\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct file_range {\n\tconst struct path *path;\n\tloff_t pos;\n\tsize_t count;\n};\n\nstruct page_counter;\n\nstruct file_region {\n\tstruct list_head link;\n\tlong int from;\n\tlong int to;\n\tstruct page_counter *reservation_counter;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[168];\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct filter_head {\n\tstruct list_head list;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rcu_work rwork;\n\t};\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\nstruct regex;\n\nstruct ftrace_event_field;\n\nstruct filter_pred {\n\tstruct regex *regex;\n\tstruct cpumask *mask;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tu64 val;\n\tu64 val2;\n\tenum filter_pred_fn fn_num;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nstruct find_child_walk_data {\n\tstruct acpi_device *adev;\n\tu64 address;\n\tint score;\n\tbool check_sta;\n\tbool check_children;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct firmware_map_entry {\n\tu64 start;\n\tu64 end;\n\tconst char *type;\n\tstruct list_head list;\n\tstruct kobject kobj;\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\nstruct fixed_phy_status {\n\tint speed;\n\tint duplex;\n\tbool link: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n};\n\nstruct fixed_phy {\n\tstruct phy_device *phydev;\n\tstruct fixed_phy_status status;\n\tint (*link_update)(struct net_device *, struct fixed_phy_status *);\n};\n\nstruct fixed_range_block {\n\tint base_msr;\n\tint ranges;\n};\n\nstruct flex {\n\ti915_reg_t reg;\n\tu32 offset;\n\tu32 value;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct flow_action_police {\n\tu32 burst;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n};\n\nstruct nf_flowtable;\n\nstruct ip_tunnel_info;\n\nstruct psample_group;\n\nstruct flow_action_cookie;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 0;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct flush_tlb_info {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tu64 new_tlb_gen;\n\tunsigned int initiating_cpu;\n\tu8 stride_shift;\n\tu8 freed_tables;\n\tu8 trim_cpumask;\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nstruct page_pool;\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n\tlong: 64;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tatomic_t _entire_mapcount;\n\t\t\t\t\tatomic_t _pincount;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct mem_cgroup;\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct follower_init_arg {\n\tstruct hda_codec *codec;\n\tint step;\n};\n\nstruct font_data {\n\tunsigned int extra[4];\n\tconst unsigned char data[0];\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tconst void *data;\n\tint pref;\n};\n\nstruct memory_block;\n\ntypedef int (*walk_memory_blocks_func_t)(struct memory_block *, void *);\n\nstruct for_each_memory_block_cb_data {\n\twalk_memory_blocks_func_t func;\n\tvoid *arg;\n};\n\nstruct inactive_task_frame {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bx;\n\tlong unsigned int bp;\n\tlong unsigned int ret_addr;\n};\n\nstruct fork_frame {\n\tstruct inactive_task_frame frame;\n\tstruct pt_regs regs;\n};\n\nstruct fork_proc_event {\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n\t__kernel_pid_t child_pid;\n\t__kernel_pid_t child_tgid;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fregs_state {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n\tu32 status;\n};\n\nstruct fxregs_state {\n\tu16 cwd;\n\tu16 swd;\n\tu16 twd;\n\tu16 fop;\n\tunion {\n\t\tstruct {\n\t\t\tu64 rip;\n\t\t\tu64 rdp;\n\t\t};\n\t\tstruct {\n\t\t\tu32 fip;\n\t\t\tu32 fcs;\n\t\t\tu32 foo;\n\t\t\tu32 fos;\n\t\t};\n\t};\n\tu32 mxcsr;\n\tu32 mxcsr_mask;\n\tu32 st_space[32];\n\tu32 xmm_space[64];\n\tu32 padding[12];\n\tunion {\n\t\tu32 padding1[12];\n\t\tu32 sw_reserved[12];\n\t};\n};\n\nstruct math_emu_info;\n\nstruct swregs_state {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n\tu8 ftop;\n\tu8 changed;\n\tu8 lookahead;\n\tu8 no_update;\n\tu8 rm;\n\tu8 alimit;\n\tstruct math_emu_info *info;\n\tu32 entry_eip;\n};\n\nstruct xstate_header {\n\tu64 xfeatures;\n\tu64 xcomp_bv;\n\tu64 reserved[6];\n};\n\nstruct xregs_state {\n\tstruct fxregs_state i387;\n\tstruct xstate_header header;\n\tu8 extended_state_area[0];\n};\n\nunion fpregs_state {\n\tstruct fregs_state fsave;\n\tstruct fxregs_state fxsave;\n\tstruct swregs_state soft;\n\tstruct xregs_state xsave;\n\tu8 __padding[4096];\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\nstruct fpstate {\n\tunsigned int size;\n\tunsigned int user_size;\n\tu64 xfeatures;\n\tu64 user_xfeatures;\n\tu64 xfd;\n\tunsigned int is_valloc: 1;\n\tunsigned int is_guest: 1;\n\tunsigned int is_confidential: 1;\n\tunsigned int in_use: 1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion fpregs_state regs;\n};\n\nstruct fpu_state_perm {\n\tu64 __state_perm;\n\tunsigned int __state_size;\n\tunsigned int __user_state_size;\n};\n\nstruct fpu {\n\tunsigned int last_cpu;\n\tlong unsigned int avx512_timestamp;\n\tstruct fpstate *fpstate;\n\tstruct fpstate *__task_fpstate;\n\tstruct fpu_state_perm perm;\n\tstruct fpu_state_perm guest_perm;\n\tstruct fpstate __fpstate;\n};\n\nstruct fpu_guest {\n\tu64 xfeatures;\n\tu64 xfd_err;\n\tunsigned int uabi_size;\n\tstruct fpstate *fpstate;\n};\n\nstruct fpu_state_config {\n\tunsigned int max_size;\n\tunsigned int default_size;\n\tu64 max_features;\n\tu64 default_features;\n\tu64 legacy_features;\n\tu64 independent_features;\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhashtable rhashtable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct fred_info {\n\tlong unsigned int edata;\n\tlong unsigned int resv;\n};\n\nstruct fred_frame {\n\tstruct pt_regs regs;\n\tstruct fred_info info;\n};\n\nstruct free_area {\n\tstruct list_head free_list[5];\n\tlong unsigned int nr_free;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t\tshort unsigned int stride;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tfreelist_full_t freelist_counters;\n\t};\n};\n\nstruct freerunning_counters {\n\tunsigned int counter_base;\n\tunsigned int counter_offset;\n\tunsigned int box_offset;\n\tunsigned int num_counters;\n\tunsigned int bits;\n\tunsigned int *box_offsets;\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n};\n\nstruct freq_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpufreq_policy *, char *);\n\tssize_t (*store)(struct cpufreq_policy *, const char *, size_t);\n};\n\nstruct muldiv {\n\tu32 multiplier;\n\tu32 divider;\n};\n\nstruct freq_desc {\n\tbool use_msr_plat;\n\tstruct muldiv muldiv[16];\n\tu32 freqs[16];\n\tu32 mask;\n};\n\nstruct intel_frontbuffer;\n\nstruct frontbuffer_fence_cb {\n\tstruct dma_fence_cb base;\n\tstruct intel_frontbuffer *front;\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_disk_quota {\n\t__s8 d_version;\n\t__s8 d_flags;\n\t__u16 d_fieldmask;\n\t__u32 d_id;\n\t__u64 d_blk_hardlimit;\n\t__u64 d_blk_softlimit;\n\t__u64 d_ino_hardlimit;\n\t__u64 d_ino_softlimit;\n\t__u64 d_bcount;\n\t__u64 d_icount;\n\t__s32 d_itimer;\n\t__s32 d_btimer;\n\t__u16 d_iwarns;\n\t__u16 d_bwarns;\n\t__s8 d_itimer_hi;\n\t__s8 d_btimer_hi;\n\t__s8 d_rtbtimer_hi;\n\t__s8 d_padding2;\n\t__u64 d_rtb_hardlimit;\n\t__u64 d_rtb_softlimit;\n\t__u64 d_rtbcount;\n\t__s32 d_rtbtimer;\n\t__u16 d_rtbwarns;\n\t__s16 d_padding3;\n\tchar d_padding4[8];\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_qfilestat {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n};\n\ntypedef struct fs_qfilestat fs_qfilestat_t;\n\nstruct fs_qfilestatv {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n\t__u32 qfs_pad;\n};\n\nstruct fs_quota_stat {\n\t__s8 qs_version;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tfs_qfilestat_t qs_uquota;\n\tfs_qfilestat_t qs_gquota;\n\t__u32 qs_incoredqs;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n};\n\nstruct fs_quota_statv {\n\t__s8 qs_version;\n\t__u8 qs_pad1;\n\t__u16 qs_flags;\n\t__u32 qs_incoredqs;\n\tstruct fs_qfilestatv qs_uquota;\n\tstruct fs_qfilestatv qs_gquota;\n\tstruct fs_qfilestatv qs_pquota;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n\t__u16 qs_rtbwarnlimit;\n\t__u16 qs_pad3;\n\t__u32 qs_pad4;\n\t__u64 qs_pad2[7];\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fscache_cache_ops;\n\nstruct fscache_cache {\n\tconst struct fscache_cache_ops *ops;\n\tstruct list_head cache_link;\n\tvoid *cache_priv;\n\trefcount_t ref;\n\tatomic_t n_volumes;\n\tatomic_t n_accesses;\n\tatomic_t object_count;\n\tunsigned int debug_id;\n\tenum fscache_cache_state state;\n\tchar *name;\n};\n\nstruct fscache_volume;\n\nstruct fscache_cookie;\n\nstruct netfs_cache_resources;\n\nstruct fscache_cache_ops {\n\tconst char *name;\n\tvoid (*acquire_volume)(struct fscache_volume *);\n\tvoid (*free_volume)(struct fscache_volume *);\n\tbool (*lookup_cookie)(struct fscache_cookie *);\n\tvoid (*withdraw_cookie)(struct fscache_cookie *);\n\tvoid (*resize_cookie)(struct netfs_cache_resources *, loff_t);\n\tbool (*invalidate_cookie)(struct fscache_cookie *);\n\tbool (*begin_operation)(struct netfs_cache_resources *, enum fscache_want_state);\n\tvoid (*prepare_to_write)(struct fscache_cookie *);\n};\n\nstruct fscache_cookie {\n\trefcount_t ref;\n\tatomic_t n_active;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n\tspinlock_t lock;\n\tstruct fscache_volume *volume;\n\tvoid *cache_priv;\n\tstruct hlist_bl_node hash_link;\n\tstruct list_head proc_link;\n\tstruct list_head commit_link;\n\tstruct work_struct work;\n\tloff_t object_size;\n\tlong unsigned int unused_at;\n\tlong unsigned int flags;\n\tenum fscache_cookie_state state;\n\tu8 advice;\n\tu8 key_len;\n\tu8 aux_len;\n\tu32 key_hash;\n\tunion {\n\t\tvoid *key;\n\t\tu8 inline_key[16];\n\t};\n\tunion {\n\t\tvoid *aux;\n\t\tu8 inline_aux[8];\n\t};\n};\n\nstruct fscache_volume {\n\trefcount_t ref;\n\tatomic_t n_cookies;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int key_hash;\n\tu8 *key;\n\tstruct list_head proc_link;\n\tstruct hlist_bl_node hash_link;\n\tstruct work_struct work;\n\tstruct fscache_cache *cache;\n\tvoid *cache_priv;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu8 coherency_len;\n\tu8 coherency[0];\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_io;\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu32 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n\tconst char *driver_override;\n};\n\nstruct fsl_mc_resource_pool;\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tunsigned int virq;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\traw_spinlock_t spinlock;\n\t};\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsverity_digest {\n\t__u16 digest_algorithm;\n\t__u16 digest_size;\n\t__u8 digest[0];\n};\n\nstruct fsverity_enable_arg {\n\t__u32 version;\n\t__u32 hash_algorithm;\n\t__u32 block_size;\n\t__u32 salt_size;\n\t__u64 salt_ptr;\n\t__u32 sig_size;\n\t__u32 __reserved1;\n\t__u64 sig_ptr;\n\t__u64 __reserved2[11];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8156];\n};\n\nstruct tracer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tchar *fmt;\n\tunsigned int fmt_size;\n\tatomic_t wait_index;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool closed;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int spare_size;\n\tunsigned int read;\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int args[0];\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tunsigned int is_signed: 1;\n\tunsigned int needs_test: 1;\n\tint len;\n};\n\nstruct ftrace_func_command {\n\tstruct list_head list;\n\tchar *name;\n\tint (*func)(struct trace_array *, struct ftrace_hash *, char *, char *, char *, int);\n};\n\nstruct ftrace_func_entry {\n\tstruct hlist_node hlist;\n\tlong unsigned int ip;\n\tlong unsigned int direct;\n};\n\nstruct ftrace_func_map {\n\tstruct ftrace_func_entry entry;\n\tvoid *data;\n};\n\nstruct ftrace_hash {\n\tlong unsigned int size_bits;\n\tstruct hlist_head *buckets;\n\tlong unsigned int count;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct ftrace_func_mapper {\n\tstruct ftrace_hash hash;\n};\n\nstruct ftrace_probe_ops;\n\nstruct ftrace_func_probe {\n\tstruct ftrace_probe_ops *probe_ops;\n\tstruct ftrace_ops ops;\n\tstruct trace_array *tr;\n\tstruct list_head list;\n\tvoid *data;\n\tint ref;\n};\n\nstruct ftrace_glob {\n\tchar *search;\n\tunsigned int len;\n\tint type;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tbool fail;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nstruct ftrace_graph_data {\n\tstruct ftrace_hash *hash;\n\tstruct ftrace_func_entry *entry;\n\tint idx;\n\tenum graph_filter_type type;\n\tstruct ftrace_hash *new_hash;\n\tconst struct seq_operations *seq_ops;\n\tstruct trace_parser parser;\n};\n\nstruct ftrace_init_func {\n\tstruct list_head list;\n\tlong unsigned int ip;\n};\n\nstruct ftrace_page;\n\nstruct ftrace_iterator {\n\tloff_t pos;\n\tloff_t func_pos;\n\tloff_t mod_pos;\n\tstruct ftrace_page *pg;\n\tstruct dyn_ftrace *func;\n\tstruct ftrace_func_probe *probe;\n\tstruct ftrace_func_entry *probe_entry;\n\tstruct trace_parser parser;\n\tstruct ftrace_hash *hash;\n\tstruct ftrace_ops *ops;\n\tstruct trace_array *tr;\n\tstruct list_head *mod_list;\n\tint pidx;\n\tint idx;\n\tunsigned int flags;\n};\n\nstruct ftrace_mod_func {\n\tstruct list_head list;\n\tchar *name;\n\tlong unsigned int ip;\n\tunsigned int size;\n};\n\nstruct ftrace_mod_load {\n\tstruct list_head list;\n\tchar *func;\n\tchar *module;\n\tint enable;\n};\n\nstruct ftrace_mod_map {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct module *mod;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tstruct list_head funcs;\n\tunsigned int num_funcs;\n};\n\nunion ftrace_op_code_union {\n\tchar code[7];\n\tstruct {\n\t\tchar op[3];\n\t\tint offset;\n\t} __attribute__((packed));\n};\n\nstruct ftrace_page {\n\tstruct ftrace_page *next;\n\tstruct dyn_ftrace *records;\n\tint index;\n\tint order;\n};\n\nstruct ftrace_probe_ops {\n\tvoid (*func)(long unsigned int, long unsigned int, struct trace_array *, struct ftrace_probe_ops *, void *);\n\tint (*init)(struct ftrace_probe_ops *, struct trace_array *, long unsigned int, void *, void **);\n\tvoid (*free)(struct ftrace_probe_ops *, struct trace_array *, long unsigned int, void *);\n\tint (*print)(struct seq_file *, long unsigned int, struct ftrace_probe_ops *, void *);\n};\n\nstruct ftrace_rec_iter {\n\tstruct ftrace_page *pg;\n\tint index;\n};\n\nstruct ftrace_regs {};\n\nstruct ftrace_ret_stack {\n\tlong unsigned int ret;\n\tlong unsigned int func;\n\tlong unsigned int *retp;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct func_repeats_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu16 count;\n\tu16 top_delta_ts;\n\tu32 bottom_delta_ts;\n};\n\nstruct function_filter_data {\n\tstruct ftrace_ops *ops;\n\tint first_filter;\n\tint first_notrace;\n};\n\nstruct fuse_access_in {\n\tuint32_t mask;\n\tuint32_t padding;\n};\n\nstruct fuse_arg {\n\tunsigned int size;\n\tvoid *value;\n};\n\nstruct fuse_in_arg {\n\tunsigned int size;\n\tconst void *value;\n};\n\nstruct fuse_mount;\n\nstruct fuse_args {\n\tuint64_t nodeid;\n\tuint32_t opcode;\n\tuint8_t in_numargs;\n\tuint8_t out_numargs;\n\tuint8_t ext_idx;\n\tbool force: 1;\n\tbool noreply: 1;\n\tbool nocreds: 1;\n\tbool in_pages: 1;\n\tbool out_pages: 1;\n\tbool user_pages: 1;\n\tbool out_argvar: 1;\n\tbool page_zeroing: 1;\n\tbool page_replace: 1;\n\tbool may_block: 1;\n\tbool is_ext: 1;\n\tbool is_pinned: 1;\n\tbool invalidate_vmap: 1;\n\tstruct fuse_in_arg in_args[4];\n\tstruct fuse_arg out_args[2];\n\tvoid (*end)(struct fuse_mount *, struct fuse_args *, int);\n\tvoid *vmap_base;\n};\n\nstruct fuse_folio_desc;\n\nstruct fuse_args_pages {\n\tstruct fuse_args args;\n\tstruct folio **folios;\n\tstruct fuse_folio_desc *descs;\n\tunsigned int num_folios;\n};\n\nstruct fuse_attr {\n\tuint64_t ino;\n\tuint64_t size;\n\tuint64_t blocks;\n\tuint64_t atime;\n\tuint64_t mtime;\n\tuint64_t ctime;\n\tuint32_t atimensec;\n\tuint32_t mtimensec;\n\tuint32_t ctimensec;\n\tuint32_t mode;\n\tuint32_t nlink;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t rdev;\n\tuint32_t blksize;\n\tuint32_t flags;\n};\n\nstruct fuse_attr_out {\n\tuint64_t attr_valid;\n\tuint32_t attr_valid_nsec;\n\tuint32_t dummy;\n\tstruct fuse_attr attr;\n};\n\nstruct fuse_backing {\n\tstruct file *file;\n\tstruct cred *cred;\n\trefcount_t count;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_backing_map {\n\tint32_t fd;\n\tuint32_t flags;\n\tuint64_t padding;\n};\n\nstruct fuse_batch_forget_in {\n\tuint32_t count;\n\tuint32_t dummy;\n};\n\nstruct fuse_bmap_in {\n\tuint64_t block;\n\tuint32_t blocksize;\n\tuint32_t padding;\n};\n\nstruct fuse_bmap_out {\n\tuint64_t block;\n};\n\nstruct fuse_forget_one {\n\tuint64_t nodeid;\n\tuint64_t nlookup;\n};\n\nstruct fuse_forget_link {\n\tstruct fuse_forget_one forget_one;\n\tstruct fuse_forget_link *next;\n};\n\nstruct fuse_iqueue_ops;\n\nstruct fuse_iqueue {\n\tunsigned int connected;\n\tspinlock_t lock;\n\twait_queue_head_t waitq;\n\tu64 reqctr;\n\tstruct list_head pending;\n\tstruct list_head interrupts;\n\tstruct fuse_forget_link forget_list_head;\n\tstruct fuse_forget_link *forget_list_tail;\n\tint forget_batch;\n\tstruct fasync_struct *fasync;\n\tconst struct fuse_iqueue_ops *ops;\n\tvoid *priv;\n};\n\nstruct fuse_conn_dax;\n\nstruct fuse_sync_bucket;\n\nstruct fuse_ring;\n\nstruct fuse_conn {\n\tspinlock_t lock;\n\trefcount_t count;\n\tatomic_t dev_count;\n\tatomic_t epoch;\n\tstruct work_struct epoch_work;\n\tstruct callback_head rcu;\n\tkuid_t user_id;\n\tkgid_t group_id;\n\tstruct pid_namespace *pid_ns;\n\tstruct user_namespace *user_ns;\n\tunsigned int max_read;\n\tunsigned int max_write;\n\tunsigned int max_pages;\n\tunsigned int max_pages_limit;\n\tstruct fuse_iqueue iq;\n\tatomic64_t khctr;\n\tstruct rb_root polled_files;\n\tunsigned int max_background;\n\tunsigned int congestion_threshold;\n\tunsigned int num_background;\n\tunsigned int active_background;\n\tstruct list_head bg_queue;\n\tspinlock_t bg_lock;\n\tint initialized;\n\tint blocked;\n\twait_queue_head_t blocked_waitq;\n\tunsigned int connected;\n\tbool aborted;\n\tunsigned int conn_error: 1;\n\tunsigned int conn_init: 1;\n\tunsigned int async_read: 1;\n\tunsigned int abort_err: 1;\n\tunsigned int atomic_o_trunc: 1;\n\tunsigned int export_support: 1;\n\tunsigned int writeback_cache: 1;\n\tunsigned int parallel_dirops: 1;\n\tunsigned int handle_killpriv: 1;\n\tunsigned int cache_symlinks: 1;\n\tunsigned int legacy_opts_show: 1;\n\tunsigned int handle_killpriv_v2: 1;\n\tunsigned int no_open: 1;\n\tunsigned int no_opendir: 1;\n\tunsigned int no_fsync: 1;\n\tunsigned int no_fsyncdir: 1;\n\tunsigned int no_flush: 1;\n\tunsigned int no_setxattr: 1;\n\tunsigned int setxattr_ext: 1;\n\tunsigned int no_getxattr: 1;\n\tunsigned int no_listxattr: 1;\n\tunsigned int no_removexattr: 1;\n\tunsigned int no_lock: 1;\n\tunsigned int no_access: 1;\n\tunsigned int no_create: 1;\n\tunsigned int no_interrupt: 1;\n\tunsigned int no_bmap: 1;\n\tunsigned int no_poll: 1;\n\tunsigned int big_writes: 1;\n\tunsigned int dont_mask: 1;\n\tunsigned int no_flock: 1;\n\tunsigned int no_fallocate: 1;\n\tunsigned int no_rename2: 1;\n\tunsigned int auto_inval_data: 1;\n\tunsigned int explicit_inval_data: 1;\n\tunsigned int do_readdirplus: 1;\n\tunsigned int readdirplus_auto: 1;\n\tunsigned int async_dio: 1;\n\tunsigned int no_lseek: 1;\n\tunsigned int posix_acl: 1;\n\tunsigned int default_permissions: 1;\n\tunsigned int allow_other: 1;\n\tunsigned int no_copy_file_range: 1;\n\tunsigned int no_copy_file_range_64: 1;\n\tunsigned int destroy: 1;\n\tunsigned int delete_stale: 1;\n\tunsigned int no_control: 1;\n\tunsigned int no_force_umount: 1;\n\tunsigned int auto_submounts: 1;\n\tunsigned int sync_fs: 1;\n\tunsigned int init_security: 1;\n\tunsigned int create_supp_group: 1;\n\tunsigned int inode_dax: 1;\n\tunsigned int no_tmpfile: 1;\n\tunsigned int direct_io_allow_mmap: 1;\n\tunsigned int no_statx: 1;\n\tunsigned int passthrough: 1;\n\tunsigned int use_pages_for_kvec_io: 1;\n\tunsigned int no_link: 1;\n\tunsigned int sync_init: 1;\n\tunsigned int io_uring;\n\tint max_stack_depth;\n\tatomic_t num_waiting;\n\tunsigned int minor;\n\tstruct list_head entry;\n\tdev_t dev;\n\tu32 scramble_key[4];\n\tatomic64_t attr_version;\n\tatomic64_t evict_ctr;\n\tu32 name_max;\n\tvoid (*release)(struct fuse_conn *);\n\tstruct rw_semaphore killsb;\n\tstruct list_head devices;\n\tenum fuse_dax_mode dax_mode;\n\tstruct fuse_conn_dax *dax;\n\tstruct list_head mounts;\n\tstruct fuse_sync_bucket *curr_bucket;\n\tstruct idr backing_files_map;\n\tstruct fuse_ring *ring;\n\tstruct {\n\t\tstruct delayed_work work;\n\t\tunsigned int req_timeout;\n\t} timeout;\n};\n\nstruct fuse_conn_dax {\n\tstruct dax_device *dev;\n\tspinlock_t lock;\n\tlong unsigned int nr_busy_ranges;\n\tstruct list_head busy_ranges;\n\tstruct delayed_work free_work;\n\twait_queue_head_t range_waitq;\n\tlong int nr_free_ranges;\n\tstruct list_head free_ranges;\n\tlong unsigned int nr_ranges;\n};\n\nstruct fuse_copy_file_range_in {\n\tuint64_t fh_in;\n\tuint64_t off_in;\n\tuint64_t nodeid_out;\n\tuint64_t fh_out;\n\tuint64_t off_out;\n\tuint64_t len;\n\tuint64_t flags;\n};\n\nstruct fuse_copy_file_range_out {\n\tuint64_t bytes_copied;\n};\n\nstruct fuse_req;\n\nstruct pipe_buffer;\n\nstruct fuse_copy_state {\n\tstruct fuse_req *req;\n\tstruct iov_iter *iter;\n\tstruct pipe_buffer *pipebufs;\n\tstruct pipe_buffer *currbuf;\n\tstruct pipe_inode_info *pipe;\n\tlong unsigned int nr_segs;\n\tstruct page *pg;\n\tunsigned int len;\n\tunsigned int offset;\n\tbool write: 1;\n\tbool move_folios: 1;\n\tbool is_uring: 1;\n\tstruct {\n\t\tunsigned int copied_sz;\n\t} ring;\n};\n\nstruct fuse_create_in {\n\tuint32_t flags;\n\tuint32_t mode;\n\tuint32_t umask;\n\tuint32_t open_flags;\n};\n\nstruct fuse_dax_mapping {\n\tstruct inode *inode;\n\tstruct list_head list;\n\tstruct interval_tree_node itn;\n\tstruct list_head busy_list;\n\tu64 window_offset;\n\tloff_t length;\n\tbool writable;\n\trefcount_t refcnt;\n};\n\nstruct fuse_dentry {\n\tu64 time;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rb_node node;\n\t};\n\tstruct dentry *dentry;\n};\n\nstruct fuse_pqueue {\n\tunsigned int connected;\n\tspinlock_t lock;\n\tstruct list_head *processing;\n\tstruct list_head io;\n};\n\nstruct fuse_dev {\n\tstruct fuse_conn *fc;\n\tstruct fuse_pqueue pq;\n\tstruct list_head entry;\n};\n\nstruct fuse_dirent {\n\tuint64_t ino;\n\tuint64_t off;\n\tuint32_t namelen;\n\tuint32_t type;\n\tchar name[0];\n};\n\nstruct fuse_entry_out {\n\tuint64_t nodeid;\n\tuint64_t generation;\n\tuint64_t entry_valid;\n\tuint64_t attr_valid;\n\tuint32_t entry_valid_nsec;\n\tuint32_t attr_valid_nsec;\n\tstruct fuse_attr attr;\n};\n\nstruct fuse_direntplus {\n\tstruct fuse_entry_out entry_out;\n\tstruct fuse_dirent dirent;\n};\n\nstruct fuse_ext_header {\n\tuint32_t size;\n\tuint32_t type;\n};\n\nstruct fuse_fallocate_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint64_t length;\n\tuint32_t mode;\n\tuint32_t padding;\n};\n\nunion fuse_file_args;\n\nstruct fuse_file {\n\tstruct fuse_mount *fm;\n\tunion fuse_file_args *args;\n\tu64 kh;\n\tu64 fh;\n\tu64 nodeid;\n\trefcount_t count;\n\tu32 open_flags;\n\tstruct list_head write_entry;\n\tstruct {\n\t\tloff_t pos;\n\t\tloff_t cache_off;\n\t\tu64 version;\n\t} readdir;\n\tstruct rb_node polled_node;\n\twait_queue_head_t poll_wait;\n\tenum {\n\t\tIOM_NONE = 0,\n\t\tIOM_CACHED = 1,\n\t\tIOM_UNCACHED = 2,\n\t} iomode;\n\tstruct file *passthrough;\n\tconst struct cred *cred;\n\tbool flock: 1;\n};\n\nstruct fuse_open_out {\n\tuint64_t fh;\n\tuint32_t open_flags;\n\tint32_t backing_id;\n};\n\nstruct fuse_release_in {\n\tuint64_t fh;\n\tuint32_t flags;\n\tuint32_t release_flags;\n\tuint64_t lock_owner;\n};\n\nstruct fuse_release_args {\n\tstruct fuse_args args;\n\tstruct fuse_release_in inarg;\n\tstruct inode *inode;\n};\n\nunion fuse_file_args {\n\tstruct fuse_open_out open_outarg;\n\tstruct fuse_release_args release_args;\n};\n\nstruct fuse_file_lock {\n\tuint64_t start;\n\tuint64_t end;\n\tuint32_t type;\n\tuint32_t pid;\n};\n\nstruct fuse_io_args;\n\nstruct fuse_fill_read_data {\n\tstruct file *file;\n\tstruct fuse_conn *fc;\n\tstruct fuse_io_args *ia;\n\tunsigned int nr_bytes;\n};\n\nstruct fuse_writepage_args;\n\nstruct fuse_fill_wb_data {\n\tstruct fuse_writepage_args *wpa;\n\tstruct fuse_file *ff;\n\tunsigned int max_folios;\n\tunsigned int nr_bytes;\n};\n\nstruct fuse_flush_in {\n\tuint64_t fh;\n\tuint32_t unused;\n\tuint32_t padding;\n\tuint64_t lock_owner;\n};\n\nstruct fuse_folio_desc {\n\tunsigned int length;\n\tunsigned int offset;\n};\n\nstruct fuse_forget_in {\n\tuint64_t nlookup;\n};\n\nstruct fuse_fs_context {\n\tint fd;\n\tstruct file *file;\n\tunsigned int rootmode;\n\tkuid_t user_id;\n\tkgid_t group_id;\n\tbool is_bdev: 1;\n\tbool fd_present: 1;\n\tbool rootmode_present: 1;\n\tbool user_id_present: 1;\n\tbool group_id_present: 1;\n\tbool default_permissions: 1;\n\tbool allow_other: 1;\n\tbool destroy: 1;\n\tbool no_control: 1;\n\tbool no_force_umount: 1;\n\tbool legacy_opts_show: 1;\n\tenum fuse_dax_mode dax_mode;\n\tunsigned int max_read;\n\tunsigned int blksize;\n\tconst char *subtype;\n\tstruct dax_device *dax_dev;\n\tvoid **fudptr;\n};\n\nstruct fuse_fsync_in {\n\tuint64_t fh;\n\tuint32_t fsync_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_getattr_in {\n\tuint32_t getattr_flags;\n\tuint32_t dummy;\n\tuint64_t fh;\n};\n\nstruct fuse_getxattr_in {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_getxattr_out {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_in_header {\n\tuint32_t len;\n\tuint32_t opcode;\n\tuint64_t unique;\n\tuint64_t nodeid;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t pid;\n\tuint16_t total_extlen;\n\tuint16_t padding;\n};\n\nstruct fuse_init_in {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t max_readahead;\n\tuint32_t flags;\n\tuint32_t flags2;\n\tuint32_t unused[11];\n};\n\nstruct fuse_init_out {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t max_readahead;\n\tuint32_t flags;\n\tuint16_t max_background;\n\tuint16_t congestion_threshold;\n\tuint32_t max_write;\n\tuint32_t time_gran;\n\tuint16_t max_pages;\n\tuint16_t map_alignment;\n\tuint32_t flags2;\n\tuint32_t max_stack_depth;\n\tuint16_t request_timeout;\n\tuint16_t unused[11];\n};\n\nstruct fuse_init_args {\n\tstruct fuse_args args;\n\tstruct fuse_init_in in;\n\tstruct fuse_init_out out;\n};\n\nstruct fuse_inode_dax;\n\nstruct fuse_submount_lookup;\n\nstruct fuse_inode {\n\tstruct inode inode;\n\tu64 nodeid;\n\tu64 nlookup;\n\tstruct fuse_forget_link *forget;\n\tu64 i_time;\n\tu32 inval_mask;\n\tumode_t orig_i_mode;\n\tstruct timespec64 i_btime;\n\tu64 orig_ino;\n\tu64 attr_version;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head write_files;\n\t\t\tstruct list_head queued_writes;\n\t\t\tint writectr;\n\t\t\tint iocachectr;\n\t\t\twait_queue_head_t page_waitq;\n\t\t\twait_queue_head_t direct_io_waitq;\n\t\t};\n\t\tstruct {\n\t\t\tbool cached;\n\t\t\tloff_t size;\n\t\t\tloff_t pos;\n\t\t\tu64 version;\n\t\t\tstruct timespec64 mtime;\n\t\t\tu64 iversion;\n\t\t\tspinlock_t lock;\n\t\t} rdc;\n\t};\n\tlong unsigned int state;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tstruct fuse_inode_dax *dax;\n\tstruct fuse_submount_lookup *submount_lookup;\n\tstruct fuse_backing *fb;\n\tu8 cached_i_blkbits;\n};\n\nstruct fuse_inode_dax {\n\tstruct rw_semaphore sem;\n\tstruct rb_root_cached tree;\n\tlong unsigned int nr;\n};\n\nstruct fuse_inode_handle {\n\tu64 nodeid;\n\tu32 generation;\n};\n\nstruct fuse_interrupt_in {\n\tuint64_t unique;\n};\n\nstruct fuse_read_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t read_flags;\n\tuint64_t lock_owner;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_write_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t write_flags;\n\tuint64_t lock_owner;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_write_out {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_io_priv;\n\nstruct fuse_io_args {\n\tunion {\n\t\tstruct {\n\t\t\tstruct fuse_read_in in;\n\t\t\tu64 attr_ver;\n\t\t} read;\n\t\tstruct {\n\t\t\tstruct fuse_write_in in;\n\t\t\tstruct fuse_write_out out;\n\t\t\tbool folio_locked;\n\t\t} write;\n\t};\n\tstruct fuse_args_pages ap;\n\tstruct fuse_io_priv *io;\n\tstruct fuse_file *ff;\n};\n\nstruct fuse_io_priv {\n\tstruct kref refcnt;\n\tint async;\n\tspinlock_t lock;\n\tunsigned int reqs;\n\tssize_t bytes;\n\tsize_t size;\n\t__u64 offset;\n\tbool write;\n\tbool should_dirty;\n\tint err;\n\tstruct kiocb *iocb;\n\tstruct completion *done;\n\tbool blocking;\n};\n\nstruct fuse_ioctl_in {\n\tuint64_t fh;\n\tuint32_t flags;\n\tuint32_t cmd;\n\tuint64_t arg;\n\tuint32_t in_size;\n\tuint32_t out_size;\n};\n\nstruct fuse_ioctl_iovec {\n\tuint64_t base;\n\tuint64_t len;\n};\n\nstruct fuse_ioctl_out {\n\tint32_t result;\n\tuint32_t flags;\n\tuint32_t in_iovs;\n\tuint32_t out_iovs;\n};\n\nstruct fuse_iqueue_ops {\n\tvoid (*send_forget)(struct fuse_iqueue *, struct fuse_forget_link *);\n\tvoid (*send_interrupt)(struct fuse_iqueue *, struct fuse_req *);\n\tvoid (*send_req)(struct fuse_iqueue *, struct fuse_req *);\n\tvoid (*release)(struct fuse_iqueue *);\n};\n\nstruct fuse_kstatfs {\n\tuint64_t blocks;\n\tuint64_t bfree;\n\tuint64_t bavail;\n\tuint64_t files;\n\tuint64_t ffree;\n\tuint32_t bsize;\n\tuint32_t namelen;\n\tuint32_t frsize;\n\tuint32_t padding;\n\tuint32_t spare[6];\n};\n\nstruct fuse_link_in {\n\tuint64_t oldnodeid;\n};\n\nstruct fuse_lk_in {\n\tuint64_t fh;\n\tuint64_t owner;\n\tstruct fuse_file_lock lk;\n\tuint32_t lk_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_lk_out {\n\tstruct fuse_file_lock lk;\n};\n\nstruct fuse_lseek_in {\n\tuint64_t fh;\n\tuint64_t offset;\n\tuint32_t whence;\n\tuint32_t padding;\n};\n\nstruct fuse_lseek_out {\n\tuint64_t offset;\n};\n\nstruct fuse_mkdir_in {\n\tuint32_t mode;\n\tuint32_t umask;\n};\n\nstruct fuse_mknod_in {\n\tuint32_t mode;\n\tuint32_t rdev;\n\tuint32_t umask;\n\tuint32_t padding;\n};\n\nstruct fuse_mount {\n\tstruct fuse_conn *fc;\n\tstruct super_block *sb;\n\tstruct list_head fc_entry;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_notify_delete_out {\n\tuint64_t parent;\n\tuint64_t child;\n\tuint32_t namelen;\n\tuint32_t padding;\n};\n\nstruct fuse_notify_inval_entry_out {\n\tuint64_t parent;\n\tuint32_t namelen;\n\tuint32_t flags;\n};\n\nstruct fuse_notify_inval_inode_out {\n\tuint64_t ino;\n\tint64_t off;\n\tint64_t len;\n};\n\nstruct fuse_notify_poll_wakeup_out {\n\tuint64_t kh;\n};\n\nstruct fuse_notify_prune_out {\n\tuint32_t count;\n\tuint32_t padding;\n\tuint64_t spare;\n};\n\nstruct fuse_notify_retrieve_in {\n\tuint64_t dummy1;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t dummy2;\n\tuint64_t dummy3;\n\tuint64_t dummy4;\n};\n\nstruct fuse_notify_retrieve_out {\n\tuint64_t notify_unique;\n\tuint64_t nodeid;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_notify_store_out {\n\tuint64_t nodeid;\n\tuint64_t offset;\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_open_in {\n\tuint32_t flags;\n\tuint32_t open_flags;\n};\n\nstruct fuse_out_header {\n\tuint32_t len;\n\tint32_t error;\n\tuint64_t unique;\n};\n\nstruct fuse_poll_in {\n\tuint64_t fh;\n\tuint64_t kh;\n\tuint32_t flags;\n\tuint32_t events;\n};\n\nstruct fuse_poll_out {\n\tuint32_t revents;\n\tuint32_t padding;\n};\n\nstruct fuse_removemapping_in {\n\tuint32_t count;\n};\n\nstruct fuse_removemapping_one {\n\tuint64_t moffset;\n\tuint64_t len;\n};\n\nstruct fuse_rename2_in {\n\tuint64_t newdir;\n\tuint32_t flags;\n\tuint32_t padding;\n};\n\nstruct fuse_req {\n\tstruct list_head list;\n\tstruct list_head intr_entry;\n\tstruct fuse_args *args;\n\trefcount_t count;\n\tlong unsigned int flags;\n\tstruct {\n\t\tstruct fuse_in_header h;\n\t} in;\n\tstruct {\n\t\tstruct fuse_out_header h;\n\t} out;\n\twait_queue_head_t waitq;\n\tvoid *argbuf;\n\tstruct fuse_mount *fm;\n\tvoid *ring_entry;\n\tvoid *ring_queue;\n\tlong unsigned int create_time;\n};\n\nstruct fuse_retrieve_args {\n\tstruct fuse_args_pages ap;\n\tstruct fuse_notify_retrieve_in inarg;\n};\n\nstruct fuse_ring_queue;\n\nstruct fuse_ring {\n\tstruct fuse_conn *fc;\n\tsize_t nr_queues;\n\tsize_t max_payload_sz;\n\tstruct fuse_ring_queue **queues;\n\tunsigned int stop_debug_log: 1;\n\twait_queue_head_t stop_waitq;\n\tstruct delayed_work async_teardown_work;\n\tlong unsigned int teardown_time;\n\tatomic_t queue_refs;\n\tbool ready;\n};\n\nstruct fuse_uring_req_header;\n\nstruct fuse_ring_ent {\n\tstruct fuse_uring_req_header *headers;\n\tvoid *payload;\n\tstruct fuse_ring_queue *queue;\n\tstruct io_uring_cmd *cmd;\n\tstruct list_head list;\n\tenum fuse_ring_req_state state;\n\tstruct fuse_req *fuse_req;\n};\n\nstruct fuse_ring_queue {\n\tstruct fuse_ring *ring;\n\tunsigned int qid;\n\tspinlock_t lock;\n\tstruct list_head ent_avail_queue;\n\tstruct list_head ent_w_req_queue;\n\tstruct list_head ent_commit_queue;\n\tstruct list_head ent_in_userspace;\n\tstruct list_head ent_released;\n\tstruct list_head fuse_req_queue;\n\tstruct list_head fuse_req_bg_queue;\n\tstruct fuse_pqueue fpq;\n\tunsigned int active_background;\n\tbool stopped;\n};\n\nstruct fuse_secctx {\n\tuint32_t size;\n\tuint32_t padding;\n};\n\nstruct fuse_secctx_header {\n\tuint32_t size;\n\tuint32_t nr_secctx;\n};\n\nstruct fuse_setattr_in {\n\tuint32_t valid;\n\tuint32_t padding;\n\tuint64_t fh;\n\tuint64_t size;\n\tuint64_t lock_owner;\n\tuint64_t atime;\n\tuint64_t mtime;\n\tuint64_t ctime;\n\tuint32_t atimensec;\n\tuint32_t mtimensec;\n\tuint32_t ctimensec;\n\tuint32_t mode;\n\tuint32_t unused4;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint32_t unused5;\n};\n\nstruct fuse_setupmapping_in {\n\tuint64_t fh;\n\tuint64_t foffset;\n\tuint64_t len;\n\tuint64_t flags;\n\tuint64_t moffset;\n};\n\nstruct fuse_setxattr_in {\n\tuint32_t size;\n\tuint32_t flags;\n\tuint32_t setxattr_flags;\n\tuint32_t padding;\n};\n\nstruct fuse_statfs_out {\n\tstruct fuse_kstatfs st;\n};\n\nstruct fuse_sx_time {\n\tint64_t tv_sec;\n\tuint32_t tv_nsec;\n\tint32_t __reserved;\n};\n\nstruct fuse_statx {\n\tuint32_t mask;\n\tuint32_t blksize;\n\tuint64_t attributes;\n\tuint32_t nlink;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint16_t mode;\n\tuint16_t __spare0[1];\n\tuint64_t ino;\n\tuint64_t size;\n\tuint64_t blocks;\n\tuint64_t attributes_mask;\n\tstruct fuse_sx_time atime;\n\tstruct fuse_sx_time btime;\n\tstruct fuse_sx_time ctime;\n\tstruct fuse_sx_time mtime;\n\tuint32_t rdev_major;\n\tuint32_t rdev_minor;\n\tuint32_t dev_major;\n\tuint32_t dev_minor;\n\tuint64_t __spare2[14];\n};\n\nstruct fuse_statx_in {\n\tuint32_t getattr_flags;\n\tuint32_t reserved;\n\tuint64_t fh;\n\tuint32_t sx_flags;\n\tuint32_t sx_mask;\n};\n\nstruct fuse_statx_out {\n\tuint64_t attr_valid;\n\tuint32_t attr_valid_nsec;\n\tuint32_t flags;\n\tuint64_t spare[2];\n\tstruct fuse_statx stat;\n};\n\nstruct fuse_submount_lookup {\n\trefcount_t count;\n\tu64 nodeid;\n\tstruct fuse_forget_link *forget;\n};\n\nstruct fuse_supp_groups {\n\tuint32_t nr_groups;\n\tuint32_t groups[0];\n};\n\nstruct fuse_sync_bucket {\n\tatomic_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head rcu;\n};\n\nstruct fuse_syncfs_in {\n\tuint64_t padding;\n};\n\nstruct fuse_uring_cmd_req {\n\tuint64_t flags;\n\tuint64_t commit_id;\n\tuint16_t qid;\n\tuint8_t padding[6];\n};\n\nstruct fuse_uring_ent_in_out {\n\tuint64_t flags;\n\tuint64_t commit_id;\n\tuint32_t payload_sz;\n\tuint32_t padding;\n\tuint64_t reserved;\n};\n\nstruct fuse_uring_pdu {\n\tstruct fuse_ring_ent *ent;\n};\n\nstruct fuse_uring_req_header {\n\tchar in_out[128];\n\tchar op_in[128];\n\tstruct fuse_uring_ent_in_out ring_ent_in_out;\n};\n\nstruct fuse_writepage_args {\n\tstruct fuse_io_args ia;\n\tstruct list_head queue_entry;\n\tstruct inode *inode;\n\tstruct fuse_sync_bucket *bucket;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nstruct uc_fw_platform_requirement;\n\nstruct fw_blobs_by_type {\n\tconst struct uc_fw_platform_requirement *blobs;\n\tu32 count;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_cfg_dma_access {\n\t__be32 control;\n\t__be32 length;\n\t__be64 address;\n};\n\nstruct fw_cfg_file {\n\t__be32 size;\n\t__be16 select;\n\t__u16 reserved;\n\tchar name[56];\n};\n\nstruct fw_cfg_sysfs_entry;\n\nstruct fw_cfg_sysfs_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct fw_cfg_sysfs_entry *, char *);\n};\n\nstruct fw_cfg_sysfs_entry {\n\tstruct kobject kobj;\n\tu32 size;\n\tu16 select;\n\tchar name[56];\n\tstruct list_head list;\n};\n\nstruct fw_cfg_vmcoreinfo {\n\t__le16 host_format;\n\t__le16 guest_format;\n\t__le32 size;\n\t__le64 paddr;\n};\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tsize_t offset;\n\tu32 opt_flags;\n\tconst char *fw_name;\n};\n\nunion fw_table_header {\n\tstruct acpi_table_header acpi;\n\tstruct acpi_table_cdat cdat;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_reference_args;\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct g4x_pipe_wm {\n\tu16 plane[8];\n\tu16 fbc;\n};\n\nstruct g4x_sr_wm {\n\tu16 plane;\n\tu16 cursor;\n\tu16 fbc;\n};\n\nstruct g4x_wm_state {\n\tstruct g4x_pipe_wm wm;\n\tstruct g4x_sr_wm sr;\n\tstruct g4x_sr_wm hpll;\n\tbool cxsr;\n\tbool hpll_en;\n\tbool fbc_en;\n};\n\nstruct g4x_wm_values {\n\tstruct g4x_pipe_wm pipe[2];\n\tstruct g4x_sr_wm sr;\n\tstruct g4x_sr_wm hpll;\n\tbool cxsr;\n\tbool hpll_en;\n\tbool fbc_en;\n};\n\nstruct idt_bits {\n\tu16 ist: 3;\n\tu16 zero: 5;\n\tu16 type: 5;\n\tu16 dpl: 2;\n\tu16 p: 1;\n};\n\nstruct gate_struct {\n\tu16 offset_low;\n\tu16 segment;\n\tstruct idt_bits bits;\n\tu16 offset_middle;\n\tu32 offset_high;\n\tu32 reserved;\n};\n\ntypedef struct gate_struct gate_desc;\n\nstruct gatt_mask {\n\tlong unsigned int mask;\n\tu32 type;\n};\n\nstruct gcm_instance_ctx {\n\tstruct crypto_skcipher_spawn ctr;\n\tstruct crypto_ahash_spawn ghash;\n};\n\nstruct gcr3_tbl_info {\n\tu64 *gcr3_tbl;\n\tint glx;\n\tu32 pasid_cnt;\n\tu16 domid;\n};\n\nstruct gcry_mpi;\n\ntypedef struct gcry_mpi *MPI;\n\nstruct gcry_mpi {\n\tint alloced;\n\tint nlimbs;\n\tint nbits;\n\tint sign;\n\tunsigned int flags;\n\tmpi_limb_t *d;\n};\n\nstruct gdt_page {\n\tstruct desc_struct gdt[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct i915_vm_pt_stash;\n\nstruct i915_vma_resource;\n\nstruct i915_vma_ops {\n\tvoid (*bind_vma)(struct i915_address_space *, struct i915_vm_pt_stash *, struct i915_vma_resource *, unsigned int, u32);\n\tvoid (*unbind_vma)(struct i915_address_space *, struct i915_vma_resource *);\n};\n\nstruct i915_page_table;\n\nstruct i915_address_space {\n\tstruct kref ref;\n\tstruct work_struct release_work;\n\tstruct drm_mm mm;\n\tstruct {\n\t\tstruct drm_i915_gem_object *obj;\n\t\tstruct i915_vma *vma;\n\t} rsvd;\n\tstruct intel_gt *gt;\n\tstruct drm_i915_private *i915;\n\tstruct drm_i915_file_private *fpriv;\n\tstruct device *dma;\n\tu64 total;\n\tu64 reserved;\n\tu64 min_alignment[4];\n\tunsigned int bind_async_flags;\n\tstruct mutex mutex;\n\tstruct kref resv_ref;\n\tstruct dma_resv _resv;\n\tstruct drm_i915_gem_object *scratch[4];\n\tstruct list_head bound_list;\n\tstruct list_head unbound_list;\n\tbool is_ggtt: 1;\n\tbool is_dpt: 1;\n\tbool has_read_only: 1;\n\tbool skip_pte_rewrite: 1;\n\tu8 top;\n\tu8 pd_shift;\n\tu8 scratch_order;\n\tlong unsigned int lmem_pt_obj_flags;\n\tstruct rb_root_cached pending_unbind;\n\tstruct drm_i915_gem_object * (*alloc_pt_dma)(struct i915_address_space *, int);\n\tstruct drm_i915_gem_object * (*alloc_scratch_dma)(struct i915_address_space *, int);\n\tu64 (*pte_encode)(dma_addr_t, unsigned int, u32);\n\tdma_addr_t (*pte_decode)(u64, bool *, bool *);\n\tvoid (*allocate_va_range)(struct i915_address_space *, struct i915_vm_pt_stash *, u64, u64);\n\tvoid (*clear_range)(struct i915_address_space *, u64, u64);\n\tvoid (*scratch_range)(struct i915_address_space *, u64, u64);\n\tvoid (*insert_page)(struct i915_address_space *, dma_addr_t, u64, unsigned int, u32);\n\tvoid (*insert_entries)(struct i915_address_space *, struct i915_vma_resource *, unsigned int, u32);\n\tvoid (*raw_insert_page)(struct i915_address_space *, dma_addr_t, u64, unsigned int, u32);\n\tvoid (*raw_insert_entries)(struct i915_address_space *, struct i915_vma_resource *, unsigned int, u32);\n\tdma_addr_t (*read_entry)(struct i915_address_space *, u64, bool *, bool *);\n\tvoid (*cleanup)(struct i915_address_space *);\n\tvoid (*foreach)(struct i915_address_space *, u64, u64, void (*)(struct i915_address_space *, struct i915_page_table *, void *), void *);\n\tstruct i915_vma_ops vma_ops;\n};\n\nstruct i915_page_directory;\n\nstruct i915_ppgtt {\n\tstruct i915_address_space vm;\n\tstruct i915_page_directory *pd;\n};\n\nstruct gen6_ppgtt {\n\tstruct i915_ppgtt base;\n\tstruct mutex flush;\n\tstruct i915_vma *vma;\n\tgen6_pte_t *pd_addr;\n\tu32 pp_dir;\n\tatomic_t pin_count;\n\tbool scan_for_unused_pt;\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct gen_pool;\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct list_head slave_bdevs;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct netlink_callback;\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[64];\n\t\tu8 data[512];\n\t};\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct gf128mul_4k {\n\tbe128 t[256];\n};\n\nstruct gf128mul_64k {\n\tstruct gf128mul_4k *t[16];\n};\n\nstruct kvm_memory_slot;\n\nstruct gfn_to_hva_cache {\n\tu64 generation;\n\tgpa_t gpa;\n\tlong unsigned int hva;\n\tlong unsigned int len;\n\tstruct kvm_memory_slot *memslot;\n};\n\nstruct kvm;\n\nstruct gfn_to_pfn_cache {\n\tu64 generation;\n\tgpa_t gpa;\n\tlong unsigned int uhva;\n\tstruct kvm_memory_slot *memslot;\n\tstruct kvm *kvm;\n\tstruct list_head list;\n\trwlock_t lock;\n\tstruct mutex refresh_lock;\n\tvoid *khva;\n\tkvm_pfn_t pfn;\n\tbool active;\n\tbool valid;\n};\n\nstruct ghash_ctx {\n\tstruct gf128mul_4k *gf128;\n};\n\nstruct ghash_desc_ctx {\n\tu8 buffer[16];\n};\n\nstruct ghcb_save_area {\n\tu8 reserved_0x0[203];\n\tu8 cpl;\n\tu8 reserved_0xcc[116];\n\tu64 xss;\n\tu8 reserved_0x148[24];\n\tu64 dr7;\n\tu8 reserved_0x168[16];\n\tu64 rip;\n\tu8 reserved_0x180[88];\n\tu64 rsp;\n\tu8 reserved_0x1e0[24];\n\tu64 rax;\n\tu8 reserved_0x200[264];\n\tu64 rcx;\n\tu64 rdx;\n\tu64 rbx;\n\tu8 reserved_0x320[8];\n\tu64 rbp;\n\tu64 rsi;\n\tu64 rdi;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu8 reserved_0x380[16];\n\tu64 sw_exit_code;\n\tu64 sw_exit_info_1;\n\tu64 sw_exit_info_2;\n\tu64 sw_scratch;\n\tu8 reserved_0x3b0[56];\n\tu64 xcr0;\n\tu8 valid_bitmap[16];\n\tu64 x87_state_gpa;\n};\n\nstruct ghcb {\n\tstruct ghcb_save_area save;\n\tu8 reserved_save[1016];\n\tu8 shared_buffer[2032];\n\tu8 reserved_0xff0[10];\n\tu16 protocol_version;\n\tu32 ghcb_usage;\n};\n\nstruct global_params {\n\tbool no_turbo;\n\tbool turbo_disabled;\n\tint max_perf_pct;\n\tint min_perf_pct;\n};\n\nstruct gmbus_pin {\n\tconst char *name;\n\tenum gmbus_gpio gpio;\n};\n\nstruct gmem_file {\n\tstruct kvm *kvm;\n\tstruct xarray bindings;\n\tstruct list_head entry;\n};\n\nstruct shared_policy {\n\tstruct rb_root root;\n\trwlock_t lock;\n};\n\nstruct gmem_inode {\n\tstruct shared_policy policy;\n\tstruct inode vfs_inode;\n\tu64 flags;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct governor_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gov_attr_set *, char *);\n\tssize_t (*store)(struct gov_attr_set *, const char *, size_t);\n};\n\nstruct gpio_device;\n\nstruct gpio_chip {\n\tconst char *label;\n\tstruct gpio_device *gpiodev;\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tstruct module *owner;\n\tint (*request)(struct gpio_chip *, unsigned int);\n\tvoid (*free)(struct gpio_chip *, unsigned int);\n\tint (*get_direction)(struct gpio_chip *, unsigned int);\n\tint (*direction_input)(struct gpio_chip *, unsigned int);\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tint (*get)(struct gpio_chip *, unsigned int);\n\tint (*get_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n\tint (*set_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set_config)(struct gpio_chip *, unsigned int, long unsigned int);\n\tint (*to_irq)(struct gpio_chip *, unsigned int);\n\tvoid (*dbg_show)(struct seq_file *, struct gpio_chip *);\n\tint (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tint (*add_pin_ranges)(struct gpio_chip *);\n\tint (*en_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint (*dis_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint base;\n\tu16 ngpio;\n\tu16 offset;\n\tconst char * const *names;\n\tbool can_sleep;\n};\n\nstruct gpiod_lookup {\n\tconst char *key;\n\tu16 chip_hwnum;\n\tconst char *con_id;\n\tunsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct gpiod_lookup_table {\n\tstruct list_head list;\n\tconst char *dev_id;\n\tstruct gpiod_lookup table[0];\n};\n\nstruct gprefix {\n\tstruct opcode pfx_no;\n\tstruct opcode pfx_66;\n\tstruct opcode pfx_f2;\n\tstruct opcode pfx_f3;\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct group_dual {\n\tstruct opcode mod012[8];\n\tstruct opcode mod3[8];\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct gsb_buffer {\n\tu8 status;\n\tu8 len;\n\tunion {\n\t\tu16 wdata;\n\t\tu8 bdata;\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct gsc_def {\n\tconst char *name;\n\tlong unsigned int bar;\n\tsize_t bar_size;\n\tbool use_polling;\n\tbool slow_firmware;\n\tsize_t lmem_size;\n};\n\nstruct gsc_heci_pkt {\n\tu64 addr_in;\n\tu32 size_in;\n\tu64 addr_out;\n\tu32 size_out;\n};\n\nstruct intel_gsc_mtl_header {\n\tu32 validity_marker;\n\tu8 heci_client_id;\n\tu8 reserved1;\n\tu16 header_version;\n\tu64 host_session_handle;\n\tu64 gsc_message_handle;\n\tu32 message_size;\n\tu32 flags;\n\tu32 status;\n} __attribute__((packed));\n\nstruct intel_gsc_proxy_header {\n\tu32 hdr;\n\tu32 source;\n\tu32 destination;\n\tu32 status;\n};\n\nstruct gsc_proxy_msg {\n\tstruct intel_gsc_mtl_header header;\n\tstruct intel_gsc_proxy_header proxy_header;\n};\n\nstruct intel_context;\n\nstruct gsccs_session_resources {\n\tu64 host_session_handle;\n\tstruct intel_context *ce;\n\tstruct i915_vma *pkt_vma;\n\tvoid *pkt_vaddr;\n\tstruct i915_vma *bb_vma;\n\tvoid *bb_vaddr;\n};\n\nstruct gt_defaults {\n\tu32 min_freq;\n\tu32 max_freq;\n\tu8 rps_up_threshold;\n\tu8 rps_down_threshold;\n};\n\nstruct guc_ct_buffer_desc {\n\tu32 head;\n\tu32 tail;\n\tu32 status;\n\tu32 reserved[13];\n};\n\nstruct guc_ctxt_registration_info {\n\tu32 flags;\n\tu32 context_idx;\n\tu32 engine_class;\n\tu32 engine_submit_mask;\n\tu32 wq_desc_lo;\n\tu32 wq_desc_hi;\n\tu32 wq_base_lo;\n\tu32 wq_base_hi;\n\tu32 wq_size;\n\tu32 hwlrca_lo;\n\tu32 hwlrca_hi;\n};\n\nstruct guc_debug_capture_list_header {\n\tu32 info;\n};\n\nstruct guc_debug_capture_list {\n\tstruct guc_debug_capture_list_header header;\n\tstruct guc_mmio_reg regs[0];\n};\n\nstruct guc_sched_wq_desc {\n\tu32 head;\n\tu32 tail;\n\tu32 error_offset;\n\tu32 wq_status;\n\tu32 reserved[28];\n};\n\nstruct guc_process_desc_v69 {\n\tu32 stage_id;\n\tu64 db_base_addr;\n\tu32 head;\n\tu32 tail;\n\tu32 error_offset;\n\tu64 wq_base_addr;\n\tu32 wq_size_bytes;\n\tu32 wq_status;\n\tu32 engine_presence;\n\tu32 priority;\n\tu32 reserved[36];\n} __attribute__((packed));\n\nunion guc_descs {\n\tstruct guc_sched_wq_desc wq_desc;\n\tstruct guc_process_desc_v69 pdesc;\n};\n\nstruct intel_ctb_coredump {\n\tu32 raw_head;\n\tu32 head;\n\tu32 raw_tail;\n\tu32 tail;\n\tu32 raw_status;\n\tu32 desc_offset;\n\tu32 cmds_offset;\n\tu32 size;\n};\n\nstruct i915_vma_coredump;\n\nstruct guc_info {\n\tstruct intel_ctb_coredump ctb[2];\n\tstruct i915_vma_coredump *vma_ctb;\n\tstruct i915_vma_coredump *vma_log;\n\tu32 *hw_state;\n\tu32 timestamp;\n\tu16 last_fence;\n\tbool is_guc_capture;\n};\n\nstruct guc_log_buffer_state {\n\tu32 marker[2];\n\tu32 read_ptr;\n\tu32 write_ptr;\n\tu32 size;\n\tu32 sampled_write_ptr;\n\tu32 wrap_offset;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flush_to_file: 1;\n\t\t\tu32 buffer_full_cnt: 4;\n\t\t\tu32 reserved: 27;\n\t\t};\n\t\tu32 flags;\n\t};\n\tu32 version;\n};\n\nstruct guc_log_section {\n\tu32 max;\n\tu32 flag;\n\tu32 default_val;\n\tconst char *name;\n};\n\nstruct guc_lrc_desc_v69 {\n\tu32 hw_context_desc;\n\tu32 slpm_perf_mode_hint;\n\tu32 slpm_freq_hint;\n\tu32 engine_submit_mask;\n\tu8 engine_class;\n\tu8 reserved0[3];\n\tu32 priority;\n\tu32 process_desc;\n\tu32 wq_addr;\n\tu32 wq_size;\n\tu32 context_flags;\n\tu32 execution_quantum;\n\tu32 preemption_timeout;\n\tu32 policy_flags;\n\tu32 reserved1[19];\n};\n\nstruct guc_state_capture_group_header_t {\n\tu32 owner;\n\tu32 info;\n};\n\nstruct guc_state_capture_header_t {\n\tu32 owner;\n\tu32 info;\n\tu32 lrca;\n\tu32 guc_id;\n\tu32 num_mmios;\n};\n\nstruct guc_update_scheduling_policy_header {\n\tu32 action;\n};\n\nstruct guc_update_scheduling_policy {\n\tstruct guc_update_scheduling_policy_header header;\n\tu32 data[3];\n};\n\nunion intel_engine_tlb_inv_reg {\n\ti915_reg_t reg;\n\ti915_mcr_reg_t mcr_reg;\n};\n\nstruct intel_engine_tlb_inv {\n\tbool mcr;\n\tunion intel_engine_tlb_inv_reg reg;\n\tu32 request;\n\tu32 done;\n};\n\nstruct intel_sseu {\n\tu8 slice_mask;\n\tu8 subslice_mask;\n\tu8 min_eus_per_subslice;\n\tu8 max_eus_per_subslice;\n};\n\nstruct intel_wakeref_ops;\n\nstruct intel_wakeref {\n\tatomic_t count;\n\tstruct mutex mutex;\n\tintel_wakeref_t wakeref;\n\tstruct drm_i915_private *i915;\n\tconst struct intel_wakeref_ops *ops;\n\tstruct delayed_work work;\n};\n\nstruct intel_engine_pmu {\n\tu32 enable;\n\tunsigned int enable_count[3];\n\tstruct i915_pmu_sample sample[3];\n};\n\nstruct intel_hw_status_page {\n\tstruct list_head timelines;\n\tstruct i915_vma *vma;\n\tu32 *addr;\n};\n\nstruct i915_wa_ctx_bb {\n\tu32 offset;\n\tu32 size;\n};\n\nstruct i915_ctx_workarounds {\n\tstruct i915_wa_ctx_bb indirect_ctx;\n\tstruct i915_wa_ctx_bb per_ctx;\n\tstruct i915_vma *vma;\n};\n\nstruct i915_wa;\n\nstruct i915_wa_list {\n\tstruct intel_gt *gt;\n\tconst char *name;\n\tconst char *engine_name;\n\tstruct i915_wa *list;\n\tunsigned int count;\n\tunsigned int wa_count;\n};\n\nstruct intel_engine_execlists {\n\tstruct timer_list timer;\n\tstruct timer_list preempt;\n\tconst struct i915_request *preempt_target;\n\tu32 ccid;\n\tu32 yield;\n\tu32 error_interrupt;\n\tu32 reset_ccid;\n\tu32 *submit_reg;\n\tu32 *ctrl_reg;\n\tstruct i915_request * const *active;\n\tstruct i915_request *inflight[3];\n\tstruct i915_request *pending[3];\n\tunsigned int port_mask;\n\tstruct rb_root_cached virtual;\n\tu32 *csb_write;\n\tu64 *csb_status;\n\tu8 csb_size;\n\tu8 csb_head;\n};\n\nstruct intel_engine_execlists_stats {\n\tunsigned int active;\n\tseqcount_t lock;\n\tktime_t total;\n\tktime_t start;\n};\n\nstruct intel_engine_guc_stats {\n\tbool running;\n\tu32 prev_total;\n\tu64 total_gt_clks;\n\tu64 start_gt_clk;\n\tu64 total;\n};\n\nstruct i915_sched_engine;\n\nstruct intel_ring;\n\nstruct intel_timeline;\n\nstruct intel_breadcrumbs;\n\nstruct intel_context_ops;\n\nstruct i915_perf_group;\n\nstruct intel_engine_cs {\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt *gt;\n\tstruct intel_uncore *uncore;\n\tchar name[8];\n\tenum intel_engine_id id;\n\tenum intel_engine_id legacy_idx;\n\tunsigned int guc_id;\n\tintel_engine_mask_t mask;\n\tu32 reset_domain;\n\tintel_engine_mask_t logical_mask;\n\tu8 class;\n\tu8 instance;\n\tu16 uabi_class;\n\tu16 uabi_instance;\n\tu32 uabi_capabilities;\n\tu32 context_size;\n\tu32 mmio_base;\n\tstruct intel_engine_tlb_inv tlb_inv;\n\tenum forcewake_domains fw_domain;\n\tunsigned int fw_active;\n\tlong unsigned int context_tag;\n\tunion {\n\t\tstruct llist_node uabi_llist;\n\t\tstruct list_head uabi_list;\n\t\tstruct rb_node uabi_node;\n\t};\n\tstruct intel_sseu sseu;\n\tstruct i915_sched_engine *sched_engine;\n\tstruct i915_request *request_pool;\n\tstruct intel_context *hung_ce;\n\tstruct llist_head barrier_tasks;\n\tstruct intel_context *kernel_context;\n\tstruct intel_context *bind_context;\n\tbool bind_context_ready;\n\tstruct list_head pinned_contexts_list;\n\tintel_engine_mask_t saturated;\n\tstruct {\n\t\tstruct delayed_work work;\n\t\tstruct i915_request *systole;\n\t\tlong unsigned int blocked;\n\t} heartbeat;\n\tlong unsigned int serial;\n\tlong unsigned int wakeref_serial;\n\tintel_wakeref_t wakeref_track;\n\tstruct intel_wakeref wakeref;\n\tstruct file *default_state;\n\tstruct {\n\t\tstruct intel_ring *ring;\n\t\tstruct intel_timeline *timeline;\n\t} legacy;\n\tstruct ewma__engine_latency latency;\n\tstruct intel_breadcrumbs *breadcrumbs;\n\tstruct intel_engine_pmu pmu;\n\tstruct intel_hw_status_page status_page;\n\tstruct i915_ctx_workarounds wa_ctx;\n\tstruct i915_wa_list ctx_wa_list;\n\tstruct i915_wa_list wa_list;\n\tstruct i915_wa_list whitelist;\n\tu32 irq_keep_mask;\n\tu32 irq_enable_mask;\n\tvoid (*irq_enable)(struct intel_engine_cs *);\n\tvoid (*irq_disable)(struct intel_engine_cs *);\n\tvoid (*irq_handler)(struct intel_engine_cs *, u16);\n\tvoid (*sanitize)(struct intel_engine_cs *);\n\tint (*resume)(struct intel_engine_cs *);\n\tstruct {\n\t\tvoid (*prepare)(struct intel_engine_cs *);\n\t\tvoid (*rewind)(struct intel_engine_cs *, bool);\n\t\tvoid (*cancel)(struct intel_engine_cs *);\n\t\tvoid (*finish)(struct intel_engine_cs *);\n\t} reset;\n\tvoid (*park)(struct intel_engine_cs *);\n\tvoid (*unpark)(struct intel_engine_cs *);\n\tvoid (*bump_serial)(struct intel_engine_cs *);\n\tvoid (*set_default_submission)(struct intel_engine_cs *);\n\tconst struct intel_context_ops *cops;\n\tint (*request_alloc)(struct i915_request *);\n\tint (*emit_flush)(struct i915_request *, u32);\n\tint (*emit_bb_start)(struct i915_request *, u64, u32, unsigned int);\n\tint (*emit_init_breadcrumb)(struct i915_request *);\n\tu32 * (*emit_fini_breadcrumb)(struct i915_request *, u32 *);\n\tunsigned int emit_fini_breadcrumb_dw;\n\tvoid (*submit_request)(struct i915_request *);\n\tvoid (*release)(struct intel_engine_cs *);\n\tvoid (*add_active_request)(struct i915_request *);\n\tvoid (*remove_active_request)(struct i915_request *);\n\tktime_t (*busyness)(struct intel_engine_cs *, ktime_t *);\n\tstruct intel_engine_execlists execlists;\n\tstruct intel_timeline *retire;\n\tstruct work_struct retire_work;\n\tstruct atomic_notifier_head context_status_notifier;\n\tunsigned int flags;\n\tstruct hlist_head cmd_hash[512];\n\tconst struct drm_i915_reg_table *reg_tables;\n\tint reg_table_count;\n\tu32 (*get_cmd_length_mask)(u32);\n\tstruct {\n\t\tunion {\n\t\t\tstruct intel_engine_execlists_stats execlists;\n\t\t\tstruct intel_engine_guc_stats guc;\n\t\t};\n\t\tktime_t rps;\n\t} stats;\n\tstruct {\n\t\tlong unsigned int heartbeat_interval_ms;\n\t\tlong unsigned int max_busywait_duration_ns;\n\t\tlong unsigned int preempt_timeout_ms;\n\t\tlong unsigned int stop_timeout_ms;\n\t\tlong unsigned int timeslice_duration_ms;\n\t} props;\n\tstruct {\n\t\tlong unsigned int heartbeat_interval_ms;\n\t\tlong unsigned int max_busywait_duration_ns;\n\t\tlong unsigned int preempt_timeout_ms;\n\t\tlong unsigned int stop_timeout_ms;\n\t\tlong unsigned int timeslice_duration_ms;\n\t} defaults;\n\tstruct i915_perf_group *oa_group;\n};\n\nstruct intel_context_stats {\n\tu64 active;\n\tstruct {\n\t\tstruct ewma_runtime avg;\n\t\tu64 total;\n\t\tu32 last;\n\t} runtime;\n};\n\nstruct i915_gem_context;\n\nstruct intel_context {\n\tunion {\n\t\tstruct kref ref;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct intel_engine_cs *engine;\n\tstruct intel_engine_cs *inflight;\n\tstruct i915_address_space *vm;\n\tstruct i915_gem_context *gem_context;\n\tstruct file *default_state;\n\tstruct list_head signal_link;\n\tstruct list_head signals;\n\tspinlock_t signal_lock;\n\tstruct i915_vma *state;\n\tu32 ring_size;\n\tstruct intel_ring *ring;\n\tstruct intel_timeline *timeline;\n\tintel_wakeref_t wakeref;\n\tlong unsigned int flags;\n\tstruct {\n\t\tu64 timeout_us;\n\t} watchdog;\n\tu32 *lrc_reg_state;\n\tunion {\n\t\tstruct {\n\t\t\tu32 lrca;\n\t\t\tu32 ccid;\n\t\t};\n\t\tu64 desc;\n\t} lrc;\n\tu32 tag;\n\tstruct intel_context_stats stats;\n\tunsigned int active_count;\n\tatomic_t pin_count;\n\tstruct mutex pin_mutex;\n\tstruct i915_active active;\n\tconst struct intel_context_ops *ops;\n\tstruct intel_sseu sseu;\n\tstruct list_head pinned_contexts_link;\n\tu8 wa_bb_page;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tu32 sched_state;\n\t\tstruct list_head fences;\n\t\tstruct i915_sw_fence blocked;\n\t\tstruct list_head requests;\n\t\tu8 prio;\n\t\tu32 prio_count[4];\n\t\tstruct delayed_work sched_disable_delay_work;\n\t} guc_state;\n\tstruct {\n\t\tu16 id;\n\t\tatomic_t ref;\n\t\tstruct list_head link;\n\t} guc_id;\n\tstruct list_head destroyed_link;\n\tstruct {\n\t\tunion {\n\t\t\tstruct list_head child_list;\n\t\t\tstruct list_head child_link;\n\t\t};\n\t\tstruct intel_context *parent;\n\t\tstruct i915_request *last_rq;\n\t\tu64 fence_context;\n\t\tu32 seqno;\n\t\tu8 number_children;\n\t\tu8 child_index;\n\t\tstruct {\n\t\t\tu16 wqi_head;\n\t\t\tu16 wqi_tail;\n\t\t\tu32 *wq_head;\n\t\t\tu32 *wq_tail;\n\t\t\tu32 *wq_status;\n\t\t\tu8 parent_page;\n\t\t} guc;\n\t} parallel;\n};\n\nstruct guc_virtual_engine {\n\tstruct intel_engine_cs base;\n\tstruct intel_context context;\n};\n\nstruct guest_domain_mapping_info {\n\trefcount_t users;\n\tu32 hdom_id;\n};\n\nstruct x86_exception {\n\tu8 vector;\n\tbool error_code_valid;\n\tu16 error_code;\n\tbool nested_page_fault;\n\tu64 address;\n\tu8 async_page_fault;\n\tlong unsigned int exit_qualification;\n};\n\nstruct guest_walker32 {\n\tint level;\n\tunsigned int max_level;\n\tgfn_t table_gfn[2];\n\tu32 ptes[2];\n\tu32 prefetch_ptes[8];\n\tgpa_t pte_gpa[2];\n\tu32 *ptep_user[2];\n\tbool pte_writable[2];\n\tunsigned int pt_access[2];\n\tunsigned int pte_access;\n\tgfn_t gfn;\n\tstruct x86_exception fault;\n};\n\nstruct guest_walker64 {\n\tint level;\n\tunsigned int max_level;\n\tgfn_t table_gfn[5];\n\tu64 ptes[5];\n\tu64 prefetch_ptes[8];\n\tgpa_t pte_gpa[5];\n\tu64 *ptep_user[5];\n\tbool pte_writable[5];\n\tunsigned int pt_access[5];\n\tunsigned int pte_access;\n\tgfn_t gfn;\n\tstruct x86_exception fault;\n};\n\nstruct guest_walkerEPT {\n\tint level;\n\tunsigned int max_level;\n\tgfn_t table_gfn[5];\n\tu64 ptes[5];\n\tu64 prefetch_ptes[8];\n\tgpa_t pte_gpa[5];\n\tu64 *ptep_user[5];\n\tbool pte_writable[5];\n\tunsigned int pt_access[5];\n\tunsigned int pte_access;\n\tgfn_t gfn;\n\tstruct x86_exception fault;\n};\n\nstruct guid_block {\n\tguid_t guid;\n\tunion {\n\t\tchar object_id[2];\n\t\tstruct {\n\t\t\tunsigned char notify_id;\n\t\t\tunsigned char reserved;\n\t\t};\n\t};\n\tu8 instance_count;\n\tu8 flags;\n};\n\nunion handle_parts {\n\tdepot_stack_handle_t handle;\n\tstruct {\n\t\tu32 pool_index_plus_1: 17;\n\t\tu32 offset: 10;\n\t\tu32 extra: 5;\n\t};\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hash_cell {\n\tstruct rb_node name_node;\n\tstruct rb_node uuid_node;\n\tbool name_set;\n\tbool uuid_set;\n\tchar *name;\n\tchar *uuid;\n\tstruct mapped_device *md;\n\tstruct dm_table *new_map;\n};\n\nstruct hash_prefix {\n\tconst char *name;\n\tconst u8 *data;\n\tsize_t size;\n};\n\nstruct mei_client_properties {\n\tuuid_le protocol_name;\n\tu8 protocol_version;\n\tu8 max_number_of_connections;\n\tu8 fixed_address;\n\tu8 single_recv_buf: 1;\n\tu8 vt_supported: 1;\n\tu8 reserved: 6;\n\tu32 max_msg_length;\n};\n\nstruct hbm_add_client_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 reserved[2];\n\tstruct mei_client_properties client_properties;\n};\n\nstruct hbm_add_client_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 status;\n\tu8 reserved;\n};\n\nstruct hbm_capability_request {\n\tu8 hbm_cmd;\n\tu8 capability_requested[3];\n};\n\nstruct hbm_capability_response {\n\tu8 hbm_cmd;\n\tu8 capability_granted[3];\n};\n\nstruct hbm_client_connect_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 reserved;\n};\n\nstruct hbm_client_connect_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 status;\n};\n\nstruct hbm_client_dma_map_request {\n\tu8 hbm_cmd;\n\tu8 client_buffer_id;\n\tu8 reserved[2];\n\tu32 address_lsb;\n\tu32 address_msb;\n\tu32 size;\n};\n\nstruct hbm_client_dma_response {\n\tu8 hbm_cmd;\n\tu8 status;\n};\n\nstruct hbm_client_dma_unmap_request {\n\tu8 hbm_cmd;\n\tu8 status;\n\tu8 client_buffer_id;\n\tu8 reserved;\n};\n\nstruct hbm_dma_mem_dscr {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 size;\n};\n\nstruct hbm_dma_ring_ctrl {\n\tu32 hbuf_wr_idx;\n\tu32 reserved1;\n\tu32 hbuf_rd_idx;\n\tu32 reserved2;\n\tu32 dbuf_wr_idx;\n\tu32 reserved3;\n\tu32 dbuf_rd_idx;\n\tu32 reserved4;\n};\n\nstruct hbm_dma_setup_request {\n\tu8 hbm_cmd;\n\tu8 reserved[3];\n\tstruct hbm_dma_mem_dscr dma_dscr[3];\n};\n\nstruct hbm_dma_setup_response {\n\tu8 hbm_cmd;\n\tu8 status;\n\tu8 reserved[2];\n};\n\nstruct hbm_flow_control {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 reserved[5];\n};\n\nstruct hbm_host_enum_request {\n\tu8 hbm_cmd;\n\tu8 flags;\n\tu8 reserved[2];\n};\n\nstruct hbm_host_enum_response {\n\tu8 hbm_cmd;\n\tu8 reserved[3];\n\tu8 valid_addresses[32];\n};\n\nstruct hbm_host_stop_request {\n\tu8 hbm_cmd;\n\tu8 reason;\n\tu8 reserved[2];\n};\n\nstruct hbm_version {\n\tu8 minor_version;\n\tu8 major_version;\n};\n\nstruct hbm_host_version_request {\n\tu8 hbm_cmd;\n\tu8 reserved;\n\tstruct hbm_version host_version;\n};\n\nstruct hbm_host_version_response {\n\tu8 hbm_cmd;\n\tu8 host_version_supported;\n\tstruct hbm_version me_max_version;\n};\n\nstruct hbm_notification_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 start;\n};\n\nstruct hbm_notification_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 status;\n\tu8 start;\n\tu8 reserved[3];\n};\n\nstruct hbm_power_gate {\n\tu8 hbm_cmd;\n\tu8 reserved[3];\n};\n\nstruct hbm_props_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 reserved[2];\n};\n\nstruct hbm_props_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 status;\n\tu8 reserved;\n\tstruct mei_client_properties client_properties;\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hda_alc298_mbxinit {\n\tunsigned char value_0x23;\n\tunsigned char value_0x25;\n};\n\nstruct hda_amp_list {\n\thda_nid_t nid;\n\tunsigned char dir;\n\tunsigned char idx;\n};\n\nstruct hda_beep {\n\tstruct input_dev *dev;\n\tstruct hda_codec *codec;\n\tchar phys[32];\n\tint tone;\n\thda_nid_t nid;\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int linear_tone: 1;\n\tunsigned int playing: 1;\n\tunsigned int keep_power_at_enable: 1;\n\tstruct work_struct beep_work;\n\tvoid (*power_hook)(struct hda_beep *, bool);\n};\n\ntypedef struct hda_codec *class_coef_mutex_t;\n\nstruct hdac_widget_tree;\n\nstruct regmap;\n\nstruct hdac_device {\n\tstruct device dev;\n\tint type;\n\tstruct hdac_bus *bus;\n\tunsigned int addr;\n\tstruct list_head list;\n\thda_nid_t afg;\n\thda_nid_t mfg;\n\tunsigned int vendor_id;\n\tunsigned int subsystem_id;\n\tunsigned int revision_id;\n\tunsigned int afg_function_id;\n\tunsigned int mfg_function_id;\n\tunsigned int afg_unsol: 1;\n\tunsigned int mfg_unsol: 1;\n\tunsigned int power_caps;\n\tconst char *vendor_name;\n\tconst char *chip_name;\n\tint (*exec_verb)(struct hdac_device *, unsigned int, unsigned int, unsigned int *);\n\tunsigned int num_nodes;\n\thda_nid_t start_nid;\n\thda_nid_t end_nid;\n\tatomic_t in_pm;\n\tstruct mutex widget_lock;\n\tstruct hdac_widget_tree *widgets;\n\tstruct regmap *regmap;\n\tstruct mutex regmap_lock;\n\tstruct snd_array vendor_verbs;\n\tbool lazy_cache: 1;\n\tbool caps_overwriting: 1;\n\tbool cache_coef: 1;\n\tunsigned int registered: 1;\n};\n\nstruct hda_device_id;\n\nstruct snd_hwdep;\n\nstruct snd_info_buffer;\n\nstruct hda_fixup;\n\nstruct hda_codec {\n\tstruct hdac_device core;\n\tstruct hda_bus *bus;\n\tstruct snd_card *card;\n\tunsigned int addr;\n\tu32 probe_id;\n\tconst struct hda_device_id *preset;\n\tconst char *modelname;\n\tstruct list_head pcm_list_head;\n\trefcount_t pcm_ref;\n\twait_queue_head_t remove_sleep;\n\tvoid *spec;\n\tstruct hda_beep *beep;\n\tunsigned int beep_mode;\n\tbool beep_just_power_on;\n\tu32 *wcaps;\n\tstruct snd_array mixers;\n\tstruct snd_array nids;\n\tstruct list_head conn_list;\n\tstruct mutex spdif_mutex;\n\tstruct mutex control_mutex;\n\tstruct snd_array spdif_out;\n\tunsigned int spdif_in_enable;\n\tconst hda_nid_t *follower_dig_outs;\n\tstruct snd_array init_pins;\n\tstruct snd_array driver_pins;\n\tstruct snd_array cvt_setups;\n\tstruct mutex user_mutex;\n\tstruct snd_hwdep *hwdep;\n\tunsigned int configured: 1;\n\tunsigned int in_freeing: 1;\n\tunsigned int display_power_control: 1;\n\tunsigned int spdif_status_reset: 1;\n\tunsigned int pin_amp_workaround: 1;\n\tunsigned int single_adc_amp: 1;\n\tunsigned int no_sticky_stream: 1;\n\tunsigned int pins_shutup: 1;\n\tunsigned int no_trigger_sense: 1;\n\tunsigned int no_jack_detect: 1;\n\tunsigned int inv_eapd: 1;\n\tunsigned int inv_jack_detect: 1;\n\tunsigned int pcm_format_first: 1;\n\tunsigned int cached_write: 1;\n\tunsigned int dp_mst: 1;\n\tunsigned int dump_coef: 1;\n\tunsigned int power_save_node: 1;\n\tunsigned int auto_runtime_pm: 1;\n\tunsigned int force_pin_prefix: 1;\n\tunsigned int link_down_at_suspend: 1;\n\tunsigned int relaxed_resume: 1;\n\tunsigned int forced_resume: 1;\n\tunsigned int no_stream_clean_at_suspend: 1;\n\tunsigned int ctl_dev_id: 1;\n\tlong unsigned int power_on_acct;\n\tlong unsigned int power_off_acct;\n\tlong unsigned int power_jiffies;\n\tunsigned int (*power_filter)(struct hda_codec *, hda_nid_t, unsigned int);\n\tvoid (*proc_widget_hook)(struct snd_info_buffer *, struct hda_codec *, hda_nid_t);\n\tstruct snd_array jacktbl;\n\tlong unsigned int jackpoll_interval;\n\tstruct delayed_work jackpoll_work;\n\tint depop_delay;\n\tint fixup_id;\n\tconst struct hda_fixup *fixup_list;\n\tconst char *fixup_name;\n\tstruct snd_array verbs;\n};\n\nstruct hdac_driver {\n\tstruct device_driver driver;\n\tint type;\n\tconst struct hda_device_id *id_table;\n\tint (*match)(struct hdac_device *, const struct hdac_driver *);\n\tvoid (*unsol_event)(struct hdac_device *, unsigned int);\n\tint (*probe)(struct hdac_device *);\n\tint (*remove)(struct hdac_device *);\n\tvoid (*shutdown)(struct hdac_device *);\n};\n\nstruct hda_codec_ops;\n\nstruct hda_codec_driver {\n\tstruct hdac_driver core;\n\tconst struct hda_device_id *id;\n\tconst struct hda_codec_ops *ops;\n};\n\nstruct hda_codec_ops {\n\tint (*probe)(struct hda_codec *, const struct hda_device_id *);\n\tvoid (*remove)(struct hda_codec *);\n\tint (*build_controls)(struct hda_codec *);\n\tint (*build_pcms)(struct hda_codec *);\n\tint (*init)(struct hda_codec *);\n\tvoid (*unsol_event)(struct hda_codec *, unsigned int);\n\tvoid (*set_power_state)(struct hda_codec *, hda_nid_t, unsigned int);\n\tint (*suspend)(struct hda_codec *);\n\tint (*resume)(struct hda_codec *);\n\tint (*check_power_status)(struct hda_codec *, hda_nid_t);\n\tvoid (*stream_pm)(struct hda_codec *, hda_nid_t, bool);\n};\n\nstruct hda_conn_list {\n\tstruct list_head list;\n\tint len;\n\thda_nid_t nid;\n\thda_nid_t conns[0];\n};\n\nstruct hda_controller_ops {\n\tint (*disable_msi_reset_irq)(struct azx *);\n\tint (*position_check)(struct azx *, struct azx_dev *);\n\tint (*link_power)(struct azx *, bool);\n};\n\nstruct hda_cvt_setup {\n\thda_nid_t nid;\n\tu8 stream_tag;\n\tu8 channel_id;\n\tu16 format_id;\n\tunsigned char active;\n\tunsigned char dirty;\n};\n\nstruct hda_device_id {\n\t__u32 vendor_id;\n\t__u32 rev_id;\n\t__u8 api_version;\n\tconst char *name;\n\tlong unsigned int driver_data;\n};\n\nstruct hda_pintbl;\n\nstruct hda_verb;\n\nstruct hda_fixup {\n\tint type;\n\tbool chained: 1;\n\tbool chained_before: 1;\n\tint chain_id;\n\tunion {\n\t\tconst struct hda_pintbl *pins;\n\t\tconst struct hda_verb *verbs;\n\t\tvoid (*func)(struct hda_codec *, const struct hda_fixup *, int);\n\t} v;\n};\n\nstruct hda_intel {\n\tstruct azx chip;\n\tstruct work_struct irq_pending_work;\n\tstruct completion probe_wait;\n\tstruct delayed_work probe_work;\n\tstruct list_head list;\n\tunsigned int irq_pending_warned: 1;\n\tunsigned int probe_continued: 1;\n\tunsigned int runtime_pm_disabled: 1;\n\tunsigned int use_vga_switcheroo: 1;\n\tunsigned int vga_switcheroo_registered: 1;\n\tunsigned int init_failed: 1;\n\tunsigned int freed: 1;\n\tbool need_i915_power: 1;\n\tint probe_retry;\n};\n\ntypedef void (*hda_jack_callback_fn)(struct hda_codec *, struct hda_jack_callback *);\n\nstruct hda_jack_tbl;\n\nstruct hda_jack_callback {\n\thda_nid_t nid;\n\tint dev_id;\n\thda_jack_callback_fn func;\n\tunsigned int private_data;\n\tunsigned int unsol_res;\n\tstruct hda_jack_tbl *jack;\n\tstruct hda_jack_callback *next;\n};\n\nstruct hda_jack_keymap {\n\tenum snd_jack_types type;\n\tint key;\n};\n\nstruct snd_jack;\n\nstruct hda_jack_tbl {\n\thda_nid_t nid;\n\tint dev_id;\n\tunsigned char tag;\n\tstruct hda_jack_callback *callback;\n\tunsigned int pin_sense;\n\tunsigned int jack_detect: 1;\n\tunsigned int jack_dirty: 1;\n\tunsigned int phantom_jack: 1;\n\tunsigned int block_report: 1;\n\thda_nid_t gating_jack;\n\thda_nid_t gated_jack;\n\thda_nid_t key_report_jack;\n\tint type;\n\tint button_state;\n\tstruct snd_jack *jack;\n};\n\nstruct hda_model_fixup {\n\tconst int id;\n\tconst char *name;\n};\n\nstruct hda_nid_item {\n\tstruct snd_kcontrol *kctl;\n\tunsigned int index;\n\thda_nid_t nid;\n\tshort unsigned int flags;\n};\n\nstruct hda_pcm_ops {\n\tint (*open)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tint (*close)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tint (*prepare)(struct hda_pcm_stream *, struct hda_codec *, unsigned int, unsigned int, struct snd_pcm_substream *);\n\tint (*cleanup)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tunsigned int (*get_delay)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n};\n\nstruct snd_pcm_chmap_elem;\n\nstruct hda_pcm_stream {\n\tunsigned int substreams;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\thda_nid_t nid;\n\tu32 rates;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int maxbps;\n\tconst struct snd_pcm_chmap_elem *chmap;\n\tstruct hda_pcm_ops ops;\n};\n\nstruct hda_pcm {\n\tchar *name;\n\tstruct hda_pcm_stream stream[2];\n\tunsigned int pcm_type;\n\tint device;\n\tstruct snd_pcm *pcm;\n\tbool own_chmap;\n\tstruct hda_codec *codec;\n\tstruct list_head list;\n\tunsigned int disconnected: 1;\n};\n\nstruct hda_pincfg {\n\thda_nid_t nid;\n\tunsigned char ctrl;\n\tunsigned char target;\n\tunsigned int cfg;\n};\n\nstruct hda_pintbl {\n\thda_nid_t nid;\n\tu32 val;\n};\n\nstruct hda_quirk {\n\tshort unsigned int subvendor;\n\tshort unsigned int subdevice;\n\tshort unsigned int subdevice_mask;\n\tbool match_codec_ssid;\n\tint value;\n};\n\nstruct hda_rate_tbl {\n\tunsigned int hz;\n\tunsigned int alsa_bits;\n\tunsigned int hda_fmt;\n};\n\nstruct hda_scodec_match {\n\tconst char *bus;\n\tconst char *hid;\n\tconst char *match_str;\n\tint index;\n};\n\nstruct hda_spdif_out {\n\thda_nid_t nid;\n\tunsigned int status;\n\tshort unsigned int ctls;\n};\n\nstruct hda_vendor_id {\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct hda_verb {\n\thda_nid_t nid;\n\tu32 verb;\n\tu32 param;\n};\n\nstruct hda_verb_ioctl {\n\tu32 verb;\n\tu32 res;\n};\n\nstruct hdac_bus_ops {\n\tint (*command)(struct hdac_bus *, unsigned int);\n\tint (*get_response)(struct hdac_bus *, unsigned int, unsigned int *);\n\tvoid (*link_power)(struct hdac_device *, bool);\n};\n\nstruct hdac_cea_channel_speaker_allocation {\n\tint ca_index;\n\tint speakers[8];\n\tint channels;\n\tint spk_mask;\n};\n\nstruct hdac_chmap;\n\nstruct hdac_chmap_ops {\n\tint (*chmap_cea_alloc_validate_get_type)(struct hdac_chmap *, struct hdac_cea_channel_speaker_allocation *, int);\n\tvoid (*cea_alloc_to_tlv_chmap)(struct hdac_chmap *, struct hdac_cea_channel_speaker_allocation *, unsigned int *, int);\n\tint (*chmap_validate)(struct hdac_chmap *, int, int, unsigned char *);\n\tint (*get_spk_alloc)(struct hdac_device *, int);\n\tvoid (*get_chmap)(struct hdac_device *, int, unsigned char *);\n\tvoid (*set_chmap)(struct hdac_device *, int, unsigned char *, int);\n\tbool (*is_pcm_attached)(struct hdac_device *, int);\n\tint (*pin_get_slot_channel)(struct hdac_device *, hda_nid_t, int);\n\tint (*pin_set_slot_channel)(struct hdac_device *, hda_nid_t, int, int);\n\tvoid (*set_channel_count)(struct hdac_device *, hda_nid_t, int);\n};\n\nstruct hdac_chmap {\n\tunsigned int channels_max;\n\tstruct hdac_chmap_ops ops;\n\tstruct hdac_device *hdac;\n};\n\nstruct hdac_ext_bus_ops {\n\tint (*hdev_attach)(struct hdac_device *);\n\tint (*hdev_detach)(struct hdac_device *);\n};\n\nstruct hdac_widget_tree {\n\tstruct kobject *root;\n\tstruct kobject *afg;\n\tstruct kobject **nodes;\n};\n\nstruct hdcp2_tx_caps {\n\tu8 version;\n\tu8 tx_cap_mask[2];\n};\n\nstruct hdcp2_ake_init {\n\tu8 msg_id;\n\tu8 r_tx[8];\n\tstruct hdcp2_tx_caps tx_caps;\n};\n\nstruct hdcp2_ake_no_stored_km {\n\tu8 msg_id;\n\tu8 e_kpub_km[128];\n};\n\nstruct hdcp2_cert_rx {\n\tu8 receiver_id[5];\n\tu8 kpub_rx[131];\n\tu8 reserved[2];\n\tu8 dcp_signature[384];\n};\n\nstruct hdcp2_ake_send_cert {\n\tu8 msg_id;\n\tstruct hdcp2_cert_rx cert_rx;\n\tu8 r_rx[8];\n\tu8 rx_caps[3];\n};\n\nstruct hdcp2_ake_send_hprime {\n\tu8 msg_id;\n\tu8 h_prime[32];\n};\n\nstruct hdcp2_ake_send_pairing_info {\n\tu8 msg_id;\n\tu8 e_kh_km[16];\n};\n\nstruct hdcp2_dp_errata_stream_type {\n\tu8 msg_id;\n\tu8 stream_type;\n};\n\nstruct hdcp2_dp_msg_data {\n\tu8 msg_id;\n\tu32 offset;\n\tbool msg_detectable;\n\tu32 timeout;\n\tu32 timeout2;\n\tu32 msg_read_timeout;\n};\n\nstruct hdcp2_hdmi_msg_timeout {\n\tu8 msg_id;\n\tu16 timeout;\n};\n\nstruct hdcp2_lc_init {\n\tu8 msg_id;\n\tu8 r_n[8];\n};\n\nstruct hdcp2_lc_send_lprime {\n\tu8 msg_id;\n\tu8 l_prime[32];\n};\n\nstruct hdcp2_rep_send_ack {\n\tu8 msg_id;\n\tu8 v[16];\n};\n\nstruct hdcp2_rep_send_receiverid_list {\n\tu8 msg_id;\n\tu8 rx_info[2];\n\tu8 seq_num_v[3];\n\tu8 v_prime[16];\n\tu8 receiver_ids[155];\n};\n\nstruct hdcp2_streamid_type {\n\tu8 stream_id;\n\tu8 stream_type;\n};\n\nstruct hdcp2_rep_stream_manage {\n\tu8 msg_id;\n\tu8 seq_num_m[3];\n\t__be16 k;\n\tstruct hdcp2_streamid_type streams[4];\n};\n\nstruct hdcp2_rep_stream_ready {\n\tu8 msg_id;\n\tu8 m_prime[32];\n};\n\nstruct hdcp2_ske_send_eks {\n\tu8 msg_id;\n\tu8 e_dkey_ks[16];\n\tu8 riv[8];\n};\n\nstruct hdcp_cmd_header {\n\tu32 api_version;\n\tu32 command_id;\n\tenum fw_hdcp_status status;\n\tu32 buffer_len;\n};\n\nstruct hdcp_port_data {\n\tenum hdcp_ddi hdcp_ddi;\n\tenum hdcp_transcoder hdcp_transcoder;\n\tu8 port_type;\n\tu8 protocol;\n\tu16 k;\n\tu32 seq_num_m;\n\tstruct hdcp2_streamid_type *streams;\n};\n\nstruct hdcp_port_id {\n\tu8 integrated_port_type;\n\tu8 physical_port;\n\tu8 attached_transcoder;\n\tu8 reserved;\n};\n\nstruct hdcp_srm_header {\n\tu8 srm_id;\n\tu8 reserved;\n\t__be16 srm_version;\n\tu8 srm_gen_no;\n} __attribute__((packed));\n\nstruct hdmi_aud_ncts {\n\tint sample_rate;\n\tint clock;\n\tint n;\n\tint cts;\n};\n\nstruct hdr_metadata_infoframe {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} white_point;\n\t__u16 max_display_mastering_luminance;\n\t__u16 min_display_mastering_luminance;\n\t__u16 max_cll;\n\t__u16 max_fall;\n};\n\nstruct hdr_output_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_metadata_infoframe hdmi_metadata_type1;\n\t};\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct held_lock {\n\tu64 prev_chain_key;\n\tlong unsigned int acquire_ip;\n\tstruct lockdep_map *instance;\n\tstruct lockdep_map *nest_lock;\n\tunsigned int class_idx: 13;\n\tunsigned int irq_context: 2;\n\tunsigned int trylock: 1;\n\tunsigned int read: 2;\n\tunsigned int check: 1;\n\tunsigned int hardirqs_off: 1;\n\tunsigned int sync: 1;\n\tunsigned int references: 11;\n\tunsigned int pin_count;\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[4];\n};\n\nstruct hib_bio_batch {\n\tatomic_t count;\n\twait_queue_head_t wait;\n\tblk_status_t error;\n\tstruct blk_plug plug;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct hmac_ctx {\n\tstruct crypto_shash *hash;\n\tu8 pads[0];\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha384_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha384_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hmac_sha512_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha512_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct hpet_timer {\n\tu64 hpet_config;\n\tunion {\n\t\tu64 _hpet_hc64;\n\t\tu32 _hpet_hc32;\n\t\tlong unsigned int _hpet_compare;\n\t} _u1;\n\tu64 hpet_fsb[2];\n};\n\nstruct hpet {\n\tu64 hpet_cap;\n\tu64 res0;\n\tu64 hpet_config;\n\tu64 res1;\n\tu64 hpet_isr;\n\tu64 res2[25];\n\tunion {\n\t\tu64 _hpet_mc64;\n\t\tu32 _hpet_mc32;\n\t\tlong unsigned int _hpet_mc;\n\t} _u0;\n\tu64 res3;\n\tstruct hpet_timer hpet_timers[0];\n};\n\nstruct hpet_channel;\n\nstruct hpet_base {\n\tunsigned int nr_channels;\n\tunsigned int nr_clockevents;\n\tunsigned int boot_cfg;\n\tstruct hpet_channel *channels;\n};\n\nstruct hpet_channel {\n\tstruct clock_event_device evt;\n\tunsigned int num;\n\tunsigned int cpu;\n\tunsigned int irq;\n\tunsigned int in_use;\n\tenum hpet_mode mode;\n\tunsigned int boot_cfg;\n\tchar name[10];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hpet_data {\n\tlong unsigned int hd_phys_address;\n\tvoid *hd_address;\n\tshort unsigned int hd_nirqs;\n\tunsigned int hd_state;\n\tunsigned int hd_irq[32];\n};\n\nstruct hpets;\n\nstruct hpet_dev {\n\tstruct hpets *hd_hpets;\n\tstruct hpet *hd_hpet;\n\tstruct hpet_timer *hd_timer;\n\tlong unsigned int hd_ireqfreq;\n\tlong unsigned int hd_irqdata;\n\twait_queue_head_t hd_waitqueue;\n\tstruct fasync_struct *hd_async_queue;\n\tunsigned int hd_flags;\n\tunsigned int hd_irq;\n\tunsigned int hd_hdwirq;\n\tchar hd_name[7];\n};\n\nstruct hpet_info {\n\tlong unsigned int hi_ireqfreq;\n\tlong unsigned int hi_flags;\n\tshort unsigned int hi_hpet;\n\tshort unsigned int hi_timer;\n};\n\nunion hpet_lock {\n\tstruct {\n\t\tarch_spinlock_t lock;\n\t\tu32 value;\n\t};\n\tu64 lockval;\n};\n\nstruct hpets {\n\tstruct hpets *hp_next;\n\tstruct hpet *hp_hpet;\n\tlong unsigned int hp_hpet_phys;\n\tlong long unsigned int hp_tick_freq;\n\tlong unsigned int hp_delta;\n\tunsigned int hp_ntimer;\n\tunsigned int hp_which;\n\tstruct hpet_dev hp_dev[0];\n};\n\nstruct hprobe {\n\tenum hprobe_state state;\n\tint srcu_idx;\n\tstruct uprobe *uprobe;\n};\n\nstruct hpx_type0 {\n\tu32 revision;\n\tu8 cache_line_size;\n\tu8 latency_timer;\n\tu8 enable_serr;\n\tu8 enable_perr;\n};\n\nstruct hpx_type1 {\n\tu32 revision;\n\tu8 max_mem_read;\n\tu8 avg_max_split;\n\tu16 tot_max_split;\n};\n\nstruct hpx_type2 {\n\tu32 revision;\n\tu32 unc_err_mask_and;\n\tu32 unc_err_mask_or;\n\tu32 unc_err_sever_and;\n\tu32 unc_err_sever_or;\n\tu32 cor_err_mask_and;\n\tu32 cor_err_mask_or;\n\tu32 adv_err_cap_and;\n\tu32 adv_err_cap_or;\n\tu16 pci_exp_devctl_and;\n\tu16 pci_exp_devctl_or;\n\tu16 pci_exp_lnkctl_and;\n\tu16 pci_exp_lnkctl_or;\n\tu32 sec_unc_err_sever_and;\n\tu32 sec_unc_err_sever_or;\n\tu32 sec_unc_err_mask_and;\n\tu32 sec_unc_err_mask_or;\n};\n\nstruct hpx_type3 {\n\tu16 device_type;\n\tu16 function_type;\n\tu16 config_space_location;\n\tu16 pci_exp_cap_id;\n\tu16 pci_exp_cap_ver;\n\tu16 pci_exp_vendor_id;\n\tu16 dvsec_id;\n\tu16 dvsec_rev;\n\tu16 match_offset;\n\tu32 match_mask_and;\n\tu32 match_value;\n\tu16 reg_offset;\n\tu32 reg_mask_and;\n\tu32 reg_mask_or;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n\traw_spinlock_t *lock;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tktime_t offset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tstruct hrtimer_clock_base clock_base[8];\n\tcall_single_data_t csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n};\n\nstruct hs_primary_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\t__u8 id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 unused4[28];\n\t__u8 root_directory_record[34];\n};\n\nstruct hs_volume_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2033];\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {\n\tstruct mutex resize_lock;\n\tstruct lock_class_key resize_key;\n\tint next_nid_to_alloc;\n\tint next_nid_to_free;\n\tunsigned int order;\n\tunsigned int demote_order;\n\tlong unsigned int mask;\n\tlong unsigned int max_huge_pages;\n\tlong unsigned int nr_huge_pages;\n\tlong unsigned int free_huge_pages;\n\tlong unsigned int resv_huge_pages;\n\tlong unsigned int surplus_huge_pages;\n\tlong unsigned int nr_overcommit_huge_pages;\n\tstruct list_head hugepage_activelist;\n\tstruct list_head hugepage_freelists[64];\n\tunsigned int max_huge_pages_node[64];\n\tunsigned int nr_huge_pages_node[64];\n\tunsigned int free_huge_pages_node[64];\n\tunsigned int surplus_huge_pages_node[64];\n\tchar name[32];\n};\n\nstruct hsu_dma_chan;\n\nstruct hsu_dma {\n\tstruct dma_device dma;\n\tstruct hsu_dma_chan *chan;\n\tshort unsigned int nr_channels;\n};\n\nstruct virt_dma_desc;\n\nstruct virt_dma_chan {\n\tstruct dma_chan chan;\n\tstruct tasklet_struct task;\n\tvoid (*desc_free)(struct virt_dma_desc *);\n\tspinlock_t lock;\n\tstruct list_head desc_allocated;\n\tstruct list_head desc_submitted;\n\tstruct list_head desc_issued;\n\tstruct list_head desc_completed;\n\tstruct list_head desc_terminated;\n\tstruct virt_dma_desc *cyclic;\n};\n\nstruct hsu_dma_desc;\n\nstruct hsu_dma_chan {\n\tstruct virt_dma_chan vchan;\n\tvoid *reg;\n\tenum dma_transfer_direction direction;\n\tstruct dma_slave_config config;\n\tstruct hsu_dma_desc *desc;\n};\n\nstruct hsu_dma_chip {\n\tstruct device *dev;\n\tint irq;\n\tvoid *regs;\n\tunsigned int length;\n\tunsigned int offset;\n\tstruct hsu_dma *hsu;\n};\n\nstruct virt_dma_desc {\n\tstruct dma_async_tx_descriptor tx;\n\tstruct dmaengine_result tx_result;\n\tstruct list_head node;\n};\n\nstruct hsu_dma_sg;\n\nstruct hsu_dma_desc {\n\tstruct virt_dma_desc vdesc;\n\tenum dma_transfer_direction direction;\n\tstruct hsu_dma_sg *sg;\n\tunsigned int nents;\n\tsize_t length;\n\tunsigned int active;\n\tenum dma_status status;\n};\n\nstruct hsu_dma_sg {\n\tdma_addr_t addr;\n\tunsigned int len;\n};\n\nstruct hsu_dma_slave {\n\tstruct device *dma_dev;\n\tint chan_id;\n};\n\nstruct hsw_ddi_buf_trans {\n\tu32 trans1;\n\tu32 trans2;\n\tu8 i_boost;\n};\n\nstruct hsw_dpll_hw_state {\n\tu32 wrpll;\n\tu32 spll;\n};\n\nunion hsw_tsx_tuning {\n\tstruct {\n\t\tu32 cycles_last_block: 32;\n\t\tu32 hle_abort: 1;\n\t\tu32 rtm_abort: 1;\n\t\tu32 instruction_abort: 1;\n\t\tu32 non_instruction_abort: 1;\n\t\tu32 retry: 1;\n\t\tu32 data_conflict: 1;\n\t\tu32 capacity_writes: 1;\n\t\tu32 capacity_reads: 1;\n\t};\n\tu64 value;\n};\n\nstruct hsw_wrpll_rnp {\n\tunsigned int p;\n\tunsigned int n2;\n\tunsigned int r2;\n};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tlong: 0;\n\tchar key[0];\n};\n\nstruct cma;\n\nstruct huge_bootmem_page {\n\tstruct list_head list;\n\tstruct hstate *hstate;\n\tlong unsigned int flags;\n\tstruct cma *cma;\n};\n\nstruct hugepage_subpool {\n\tspinlock_t lock;\n\tlong int count;\n\tlong int max_hpages;\n\tlong int used_hpages;\n\tstruct hstate *hstate;\n\tlong int min_hpages;\n\tlong int rsv_hpages;\n};\n\nstruct page_counter {\n\tatomic_long_t usage;\n\tlong unsigned int failcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int emin;\n\tatomic_long_t min_usage;\n\tatomic_long_t children_min_usage;\n\tlong unsigned int elow;\n\tatomic_long_t low_usage;\n\tatomic_long_t children_low_usage;\n\tlong unsigned int watermark;\n\tlong unsigned int local_watermark;\n\tstruct cacheline_padding _pad2_;\n\tbool protection_support;\n\tbool track_failcnt;\n\tlong unsigned int min;\n\tlong unsigned int low;\n\tlong unsigned int high;\n\tlong unsigned int max;\n\tstruct page_counter *parent;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hugetlb_cgroup_per_node;\n\nstruct hugetlb_cgroup {\n\tstruct cgroup_subsys_state css;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter hugepage[2];\n\tstruct page_counter rsvd_hugepage[2];\n\tatomic_long_t events[2];\n\tatomic_long_t events_local[2];\n\tstruct cgroup_file events_file[2];\n\tstruct cgroup_file events_local_file[2];\n\tstruct hugetlb_cgroup_per_node *nodeinfo[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hugetlb_cgroup_per_node {\n\tlong unsigned int usage[2];\n};\n\nstruct hugetlb_cmdline {\n\tchar *val;\n\tint (*setup)(char *);\n};\n\nstruct hugetlb_vma_lock {\n\tstruct kref refs;\n\tstruct rw_semaphore rw_sema;\n\tstruct vm_area_struct *vma;\n};\n\nstruct hugetlbfs_fs_context {\n\tstruct hstate *hstate;\n\tlong long unsigned int max_size_opt;\n\tlong long unsigned int min_size_opt;\n\tlong int max_hpages;\n\tlong int nr_inodes;\n\tlong int min_hpages;\n\tenum hugetlbfs_size_type max_val_type;\n\tenum hugetlbfs_size_type min_val_type;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hugetlbfs_inode_info {\n\tstruct inode vfs_inode;\n\tunsigned int seals;\n};\n\nstruct hugetlbfs_sb_info {\n\tlong int max_inodes;\n\tlong int free_inodes;\n\tspinlock_t stat_lock;\n\tstruct hstate *hstate;\n\tstruct hugepage_subpool *spool;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hv_enlightened_vmcs {\n\tu32 revision_id;\n\tu32 abort;\n\tu16 host_es_selector;\n\tu16 host_cs_selector;\n\tu16 host_ss_selector;\n\tu16 host_ds_selector;\n\tu16 host_fs_selector;\n\tu16 host_gs_selector;\n\tu16 host_tr_selector;\n\tu16 padding16_1;\n\tu64 host_ia32_pat;\n\tu64 host_ia32_efer;\n\tu64 host_cr0;\n\tu64 host_cr3;\n\tu64 host_cr4;\n\tu64 host_ia32_sysenter_esp;\n\tu64 host_ia32_sysenter_eip;\n\tu64 host_rip;\n\tu32 host_ia32_sysenter_cs;\n\tu32 pin_based_vm_exec_control;\n\tu32 vm_exit_controls;\n\tu32 secondary_vm_exec_control;\n\tu64 io_bitmap_a;\n\tu64 io_bitmap_b;\n\tu64 msr_bitmap;\n\tu16 guest_es_selector;\n\tu16 guest_cs_selector;\n\tu16 guest_ss_selector;\n\tu16 guest_ds_selector;\n\tu16 guest_fs_selector;\n\tu16 guest_gs_selector;\n\tu16 guest_ldtr_selector;\n\tu16 guest_tr_selector;\n\tu32 guest_es_limit;\n\tu32 guest_cs_limit;\n\tu32 guest_ss_limit;\n\tu32 guest_ds_limit;\n\tu32 guest_fs_limit;\n\tu32 guest_gs_limit;\n\tu32 guest_ldtr_limit;\n\tu32 guest_tr_limit;\n\tu32 guest_gdtr_limit;\n\tu32 guest_idtr_limit;\n\tu32 guest_es_ar_bytes;\n\tu32 guest_cs_ar_bytes;\n\tu32 guest_ss_ar_bytes;\n\tu32 guest_ds_ar_bytes;\n\tu32 guest_fs_ar_bytes;\n\tu32 guest_gs_ar_bytes;\n\tu32 guest_ldtr_ar_bytes;\n\tu32 guest_tr_ar_bytes;\n\tu64 guest_es_base;\n\tu64 guest_cs_base;\n\tu64 guest_ss_base;\n\tu64 guest_ds_base;\n\tu64 guest_fs_base;\n\tu64 guest_gs_base;\n\tu64 guest_ldtr_base;\n\tu64 guest_tr_base;\n\tu64 guest_gdtr_base;\n\tu64 guest_idtr_base;\n\tu64 padding64_1[3];\n\tu64 vm_exit_msr_store_addr;\n\tu64 vm_exit_msr_load_addr;\n\tu64 vm_entry_msr_load_addr;\n\tu64 cr3_target_value0;\n\tu64 cr3_target_value1;\n\tu64 cr3_target_value2;\n\tu64 cr3_target_value3;\n\tu32 page_fault_error_code_mask;\n\tu32 page_fault_error_code_match;\n\tu32 cr3_target_count;\n\tu32 vm_exit_msr_store_count;\n\tu32 vm_exit_msr_load_count;\n\tu32 vm_entry_msr_load_count;\n\tu64 tsc_offset;\n\tu64 virtual_apic_page_addr;\n\tu64 vmcs_link_pointer;\n\tu64 guest_ia32_debugctl;\n\tu64 guest_ia32_pat;\n\tu64 guest_ia32_efer;\n\tu64 guest_pdptr0;\n\tu64 guest_pdptr1;\n\tu64 guest_pdptr2;\n\tu64 guest_pdptr3;\n\tu64 guest_pending_dbg_exceptions;\n\tu64 guest_sysenter_esp;\n\tu64 guest_sysenter_eip;\n\tu32 guest_activity_state;\n\tu32 guest_sysenter_cs;\n\tu64 cr0_guest_host_mask;\n\tu64 cr4_guest_host_mask;\n\tu64 cr0_read_shadow;\n\tu64 cr4_read_shadow;\n\tu64 guest_cr0;\n\tu64 guest_cr3;\n\tu64 guest_cr4;\n\tu64 guest_dr7;\n\tu64 host_fs_base;\n\tu64 host_gs_base;\n\tu64 host_tr_base;\n\tu64 host_gdtr_base;\n\tu64 host_idtr_base;\n\tu64 host_rsp;\n\tu64 ept_pointer;\n\tu16 virtual_processor_id;\n\tu16 padding16_2[3];\n\tu64 padding64_2[5];\n\tu64 guest_physical_address;\n\tu32 vm_instruction_error;\n\tu32 vm_exit_reason;\n\tu32 vm_exit_intr_info;\n\tu32 vm_exit_intr_error_code;\n\tu32 idt_vectoring_info_field;\n\tu32 idt_vectoring_error_code;\n\tu32 vm_exit_instruction_len;\n\tu32 vmx_instruction_info;\n\tu64 exit_qualification;\n\tu64 exit_io_instruction_ecx;\n\tu64 exit_io_instruction_esi;\n\tu64 exit_io_instruction_edi;\n\tu64 exit_io_instruction_eip;\n\tu64 guest_linear_address;\n\tu64 guest_rsp;\n\tu64 guest_rflags;\n\tu32 guest_interruptibility_info;\n\tu32 cpu_based_vm_exec_control;\n\tu32 exception_bitmap;\n\tu32 vm_entry_controls;\n\tu32 vm_entry_intr_info_field;\n\tu32 vm_entry_exception_error_code;\n\tu32 vm_entry_instruction_len;\n\tu32 tpr_threshold;\n\tu64 guest_rip;\n\tu32 hv_clean_fields;\n\tu32 padding32_1;\n\tu32 hv_synthetic_controls;\n\tstruct {\n\t\tu32 nested_flush_hypercall: 1;\n\t\tu32 msr_bitmap: 1;\n\t\tu32 reserved: 30;\n\t} hv_enlightenments_control;\n\tu32 hv_vp_id;\n\tu32 padding32_2;\n\tu64 hv_vm_id;\n\tu64 partition_assist_page;\n\tu64 padding64_4[4];\n\tu64 guest_bndcfgs;\n\tu64 guest_ia32_perf_global_ctrl;\n\tu64 guest_ia32_s_cet;\n\tu64 guest_ssp;\n\tu64 guest_ia32_int_ssp_table_addr;\n\tu64 guest_ia32_lbr_ctl;\n\tu64 padding64_5[2];\n\tu64 xss_exit_bitmap;\n\tu64 encls_exiting_bitmap;\n\tu64 host_ia32_perf_global_ctrl;\n\tu64 tsc_multiplier;\n\tu64 host_ia32_s_cet;\n\tu64 host_ssp;\n\tu64 host_ia32_int_ssp_table_addr;\n\tu64 padding64_6;\n};\n\nstruct hv_enlightenments_control {\n\tu32 nested_flush_hypercall: 1;\n\tu32 msr_bitmap: 1;\n\tu32 enlightened_npt_tlb: 1;\n\tu32 reserved: 29;\n};\n\nunion hv_hypervisor_version_info {\n\tstruct {\n\t\tu32 build_number;\n\t\tu32 minor_version: 16;\n\t\tu32 major_version: 16;\n\t\tu32 service_pack;\n\t\tu32 service_number: 24;\n\t\tu32 service_branch: 8;\n\t};\n\tstruct {\n\t\tu32 eax;\n\t\tu32 ebx;\n\t\tu32 ecx;\n\t\tu32 edx;\n\t};\n};\n\nunion hv_message_flags {\n\tu8 asu8;\n\tstruct {\n\t\tu8 msg_pending: 1;\n\t\tu8 reserved: 7;\n\t};\n};\n\nunion hv_port_id {\n\tu32 asu32;\n\tstruct {\n\t\tu32 id: 24;\n\t\tu32 reserved: 8;\n\t} u;\n};\n\nstruct hv_message_header {\n\tu32 message_type;\n\tu8 payload_size;\n\tunion hv_message_flags message_flags;\n\tu8 reserved[2];\n\tunion {\n\t\tu64 sender;\n\t\tunion hv_port_id port;\n\t};\n};\n\nstruct hv_message {\n\tstruct hv_message_header header;\n\tunion {\n\t\tu64 payload[30];\n\t} u;\n};\n\nstruct hv_nested_enlightenments_control {\n\tstruct {\n\t\tu32 directhypercall: 1;\n\t\tu32 reserved: 31;\n\t} features;\n\tstruct {\n\t\tu32 inter_partition_comm: 1;\n\t\tu32 reserved: 31;\n\t} hypercall_controls;\n};\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct hv_send_ipi {\n\tu32 vector;\n\tu32 reserved;\n\tu64 cpu_mask;\n};\n\nstruct hv_vpset {\n\tu64 format;\n\tu64 valid_bank_mask;\n\tu64 bank_contents[0];\n};\n\nstruct hv_send_ipi_ex {\n\tu32 vector;\n\tu32 reserved;\n\tstruct hv_vpset vp_set;\n};\n\nunion hv_stimer_config {\n\tu64 as_uint64;\n\tstruct {\n\t\tu64 enable: 1;\n\t\tu64 periodic: 1;\n\t\tu64 lazy: 1;\n\t\tu64 auto_enable: 1;\n\t\tu64 apic_vector: 8;\n\t\tu64 direct_mode: 1;\n\t\tu64 reserved_z0: 3;\n\t\tu64 sintx: 4;\n\t\tu64 reserved_z1: 44;\n\t};\n};\n\nstruct hv_timer_message_payload {\n\tu32 timer_index;\n\tu32 reserved;\n\tu64 expiration_time;\n\tu64 delivery_time;\n};\n\nstruct hv_tlb_flush {\n\tu64 address_space;\n\tu64 flags;\n\tu64 processor_mask;\n\tu64 gva_list[0];\n};\n\nstruct hv_tlb_flush_ex {\n\tu64 address_space;\n\tu64 flags;\n\tunion {\n\t\tstruct hv_vpset hv_vp_set;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[16];\n\t\t\tu64 gva_list[0];\n\t\t};\n\t};\n};\n\nstruct hv_vmcb_enlightenments {\n\tstruct hv_enlightenments_control hv_enlightenments_control;\n\tu32 hv_vp_id;\n\tu64 hv_vm_id;\n\tu64 partition_assist_page;\n\tu64 reserved;\n};\n\nstruct hv_vp_assist_page {\n\tu32 apic_assist;\n\tu32 reserved1;\n\tu32 vtl_entry_reason;\n\tu32 vtl_reserved;\n\tu64 vtl_ret_x64rax;\n\tu64 vtl_ret_x64rcx;\n\tstruct hv_nested_enlightenments_control nested_control;\n\tu8 enlighten_vmentry;\n\tu8 reserved2[7];\n\tu64 current_nested_vmcs;\n\tu8 synthetic_time_unhalted_timer_expired;\n\tu8 reserved3[7];\n\tu8 virtualization_fault_information[40];\n\tu8 reserved4[8];\n\tu8 intercept_message[256];\n\tu8 vtl_ret_actions[256];\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 config1;\n\t\t\tu64 last_tag;\n\t\t\tu64 dyn_constraint;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tu64 aux_config;\n\t\t\tunsigned int aux_paused;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tstruct arch_hw_breakpoint info;\n\t\t\tstruct rhlist_head bp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tunion {\n\t\tstruct {\n\t\t\tu64 last_period;\n\t\t\tlocal64_t period_left;\n\t\t};\n\t\tstruct {\n\t\t\tu64 saved_metric;\n\t\t\tu64 saved_slots;\n\t\t};\n\t};\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hwerr_info {\n\tatomic_t count;\n\ttime64_t timestamp;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n};\n\nstruct hwm_energy_info {\n\tu32 reg_val_prev;\n\tlong int accum_energy;\n};\n\nstruct hwm_fan_info {\n\tu32 reg_val_prev;\n\tu64 time_prev;\n};\n\nstruct hwm_drvdata {\n\tstruct i915_hwmon *hwmon;\n\tstruct intel_uncore *uncore;\n\tstruct device *hwmon_dev;\n\tstruct hwm_energy_info ei;\n\tstruct hwm_fan_info fi;\n\tchar name[12];\n\tint gt_n;\n\tbool reset_in_progress;\n\twait_queue_head_t waitq;\n};\n\nstruct hwm_reg {\n\ti915_reg_t gt_perf_status;\n\ti915_reg_t pkg_temp;\n\ti915_reg_t pkg_power_sku_unit;\n\ti915_reg_t pkg_power_sku;\n\ti915_reg_t pkg_rapl_limit;\n\ti915_reg_t energy_status_all;\n\ti915_reg_t energy_status_tile;\n\ti915_reg_t fan_speed;\n};\n\nstruct hwmon_channel_info {\n\tenum hwmon_sensor_types type;\n\tconst u32 *config;\n};\n\nstruct hwmon_ops;\n\nstruct hwmon_chip_info {\n\tconst struct hwmon_ops *ops;\n\tconst struct hwmon_channel_info * const *info;\n};\n\nstruct hwmon_device {\n\tconst char *name;\n\tconst char *label;\n\tstruct device dev;\n\tconst struct hwmon_chip_info *chip;\n\tstruct mutex lock;\n\tstruct list_head tzdata;\n\tstruct attribute_group group;\n\tconst struct attribute_group **groups;\n};\n\nstruct hwmon_device_attribute {\n\tstruct device_attribute dev_attr;\n\tconst struct hwmon_ops *ops;\n\tenum hwmon_sensor_types type;\n\tu32 attr;\n\tint index;\n\tchar name[32];\n};\n\nstruct hwmon_ops {\n\tumode_t visible;\n\tumode_t (*is_visible)(const void *, enum hwmon_sensor_types, u32, int);\n\tint (*read)(struct device *, enum hwmon_sensor_types, u32, int, long int *);\n\tint (*read_string)(struct device *, enum hwmon_sensor_types, u32, int, const char **);\n\tint (*write)(struct device *, enum hwmon_sensor_types, u32, int, long int);\n};\n\nstruct hwmon_thermal_data {\n\tstruct list_head node;\n\tstruct device *dev;\n\tint index;\n\tstruct thermal_zone_device *tzd;\n};\n\nstruct hwmon_type_attr_list {\n\tconst u32 *attrs;\n\tsize_t n_attrs;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct x86_hyper_init {\n\tvoid (*init_platform)(void);\n\tvoid (*guest_late_init)(void);\n\tbool (*x2apic_available)(void);\n\tbool (*msi_ext_dest_id)(void);\n\tvoid (*init_mem_mapping)(void);\n\tvoid (*init_after_bootmem)(void);\n};\n\nstruct x86_hyper_runtime {\n\tvoid (*pin_vcpu)(int);\n\tvoid (*sev_es_hcall_prepare)(struct ghcb *, struct pt_regs *);\n\tbool (*sev_es_hcall_finish)(struct ghcb *, struct pt_regs *);\n\tbool (*is_private_mmio)(u64);\n};\n\nstruct hypervisor_x86 {\n\tconst char *name;\n\tuint32_t (*detect)(void);\n\tenum x86_hypervisor_type type;\n\tstruct x86_hyper_init init;\n\tstruct x86_hyper_runtime runtime;\n\tbool ignore_nopv;\n};\n\nstruct i2c_acpi_handler_data {\n\tstruct acpi_connection_info info;\n\tstruct i2c_adapter *adapter;\n};\n\nstruct i2c_acpi_irq_context {\n\tint irq;\n\tbool wake_capable;\n};\n\nstruct i2c_board_info;\n\nstruct i2c_acpi_lookup {\n\tstruct i2c_board_info *info;\n\tacpi_handle adapter_handle;\n\tacpi_handle device_handle;\n\tacpi_handle search_handle;\n\tint n;\n\tint index;\n\tu32 speed;\n\tu32 min_speed;\n\tu32 force_speed;\n};\n\nstruct intel_dsi;\n\nstruct i2c_adapter_lookup {\n\tu16 target_addr;\n\tstruct intel_dsi *intel_dsi;\n\tacpi_handle dev_handle;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n};\n\nstruct i2c_algo_bit_data {\n\tvoid *data;\n\tvoid (*setsda)(void *, int);\n\tvoid (*setscl)(void *, int);\n\tint (*getsda)(void *);\n\tint (*getscl)(void *);\n\tint (*pre_xfer)(struct i2c_adapter *);\n\tvoid (*post_xfer)(struct i2c_adapter *);\n\tint udelay;\n\tint timeout;\n\tbool can_do_atomic;\n};\n\nstruct i2c_msg;\n\nunion i2c_smbus_data;\n\nstruct i2c_algorithm {\n\tunion {\n\t\tint (*xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tunion {\n\t\tint (*xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n};\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_gpio;\n};\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n\tvoid *devres_group_id;\n\tstruct dentry *debugfs;\n};\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *);\n\tvoid (*remove)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tu32 flags;\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nstruct i2c_smbus_alert {\n\tstruct work_struct alert;\n\tstruct i2c_client *ara;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct user_regs_struct32 {\n\t__u32 ebx;\n\t__u32 ecx;\n\t__u32 edx;\n\t__u32 esi;\n\t__u32 edi;\n\t__u32 ebp;\n\t__u32 eax;\n\tshort unsigned int ds;\n\tshort unsigned int __ds;\n\tshort unsigned int es;\n\tshort unsigned int __es;\n\tshort unsigned int fs;\n\tshort unsigned int __fs;\n\tshort unsigned int gs;\n\tshort unsigned int __gs;\n\t__u32 orig_eax;\n\t__u32 eip;\n\tshort unsigned int cs;\n\tshort unsigned int __cs;\n\t__u32 eflags;\n\t__u32 esp;\n\tshort unsigned int ss;\n\tshort unsigned int __ss;\n};\n\nstruct i386_elf_prstatus {\n\tstruct compat_elf_prstatus_common common;\n\tstruct user_regs_struct32 pr_reg;\n\tcompat_int_t pr_fpvalid;\n};\n\nstruct i801_priv {\n\tstruct i2c_adapter adapter;\n\tvoid *smba;\n\tunsigned char original_hstcfg;\n\tunsigned char original_hstcnt;\n\tunsigned char original_slvcmd;\n\tstruct pci_dev *pci_dev;\n\tunsigned int features;\n\tstruct completion done;\n\tu8 status;\n\tu8 cmd;\n\tbool is_read;\n\tint count;\n\tint len;\n\tu8 *data;\n\tstruct platform_device *tco_pdev;\n\tbool acpi_reserved;\n};\n\nstruct i8042_port {\n\tstruct serio *serio;\n\tint irq;\n\tbool exists;\n\tbool driver_bound;\n\tsigned char mux;\n};\n\nstruct i915_audio_component {\n\tstruct drm_audio_component base;\n\tint aud_sample_rate[9];\n};\n\nstruct i915_capture_list {\n\tstruct i915_vma_resource *vma_res;\n\tstruct i915_capture_list *next;\n};\n\nstruct i915_color_plane_view {\n\tu32 offset;\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned int mapping_stride;\n\tunsigned int scanout_stride;\n};\n\nstruct i915_context_engines_bond {\n\tstruct i915_user_extension base;\n\tstruct i915_engine_class_instance master;\n\t__u16 virtual_index;\n\t__u16 num_bonds;\n\t__u64 flags;\n\t__u64 mbz64[4];\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_engines_load_balance {\n\tstruct i915_user_extension base;\n\t__u16 engine_index;\n\t__u16 num_siblings;\n\t__u32 flags;\n\t__u64 mbz64;\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_engines_parallel_submit {\n\tstruct i915_user_extension base;\n\t__u16 engine_index;\n\t__u16 width;\n\t__u16 num_siblings;\n\t__u16 mbz16;\n\t__u64 flags;\n\t__u64 mbz64[3];\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_param_engines {\n\t__u64 extensions;\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_debugfs_files {\n\tconst char *name;\n\tconst struct file_operations *fops;\n};\n\nstruct i915_sched_node;\n\nstruct i915_dependency {\n\tstruct i915_sched_node *signaler;\n\tstruct i915_sched_node *waiter;\n\tstruct list_head signal_link;\n\tstruct list_head wait_link;\n\tstruct list_head dfs_link;\n\tlong unsigned int flags;\n};\n\nstruct i915_deps {\n\tstruct dma_fence *single;\n\tstruct dma_fence **fences;\n\tunsigned int num_deps;\n\tunsigned int fences_size;\n\tgfp_t gfp;\n};\n\nstruct i915_dpt {\n\tstruct i915_address_space vm;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_vma *vma;\n\tvoid *iomem;\n};\n\nstruct i915_drm_client {\n\tstruct kref kref;\n\tspinlock_t ctx_lock;\n\tstruct list_head ctx_list;\n\tspinlock_t objects_lock;\n\tstruct list_head objects_list;\n\tatomic64_t past_runtime[5];\n};\n\nstruct i915_error_regs {\n\ti915_reg_t emr;\n\ti915_reg_t eir;\n};\n\nstruct i915_gem_ww_ctx {\n\tstruct ww_acquire_ctx ctx;\n\tstruct list_head obj_list;\n\tstruct drm_i915_gem_object *contended;\n\tbool intr;\n};\n\nstruct reloc_cache {\n\tstruct drm_mm_node node;\n\tlong unsigned int vaddr;\n\tlong unsigned int page;\n\tunsigned int graphics_ver;\n\tbool use_64bit_reloc: 1;\n\tbool has_llc: 1;\n\tbool has_fence: 1;\n\tbool needs_unfenced: 1;\n};\n\nstruct intel_gt_buffer_pool_node;\n\nstruct i915_execbuffer {\n\tstruct drm_i915_private *i915;\n\tstruct drm_file *file;\n\tstruct drm_i915_gem_execbuffer2 *args;\n\tstruct drm_i915_gem_exec_object2 *exec;\n\tstruct eb_vma *vma;\n\tstruct intel_gt *gt;\n\tstruct intel_context *context;\n\tstruct i915_gem_context *gem_context;\n\tintel_wakeref_t wakeref;\n\tintel_wakeref_t wakeref_gt0;\n\tstruct i915_request *requests[9];\n\tstruct eb_vma *batches[9];\n\tstruct i915_vma *trampoline;\n\tstruct dma_fence *composite_fence;\n\tunsigned int buffer_count;\n\tunsigned int num_batches;\n\tstruct list_head unbound;\n\tstruct list_head relocs;\n\tstruct i915_gem_ww_ctx ww;\n\tstruct reloc_cache reloc_cache;\n\tu64 invalid_flags;\n\tu64 batch_len[9];\n\tu32 batch_start_offset;\n\tu32 batch_flags;\n\tstruct intel_gt_buffer_pool_node *batch_pool;\n\tint lut_size;\n\tstruct hlist_head *buckets;\n\tstruct eb_fence *fences;\n\tlong unsigned int num_fences;\n\tstruct i915_capture_list *capture_lists[9];\n};\n\nstruct i915_ext_attribute {\n\tstruct device_attribute attr;\n\tlong unsigned int val;\n};\n\nstruct i915_ggtt;\n\nstruct i915_fence_reg {\n\tstruct list_head link;\n\tstruct i915_ggtt *ggtt;\n\tstruct i915_vma *vma;\n\tatomic_t pin_count;\n\tstruct i915_active active;\n\tint id;\n\tbool dirty;\n\tu32 start;\n\tu32 size;\n\tu32 tiling;\n\tu32 stride;\n};\n\nstruct intel_frontbuffer {\n\tstruct intel_display *display;\n\tatomic_t bits;\n\tstruct work_struct flush_work;\n};\n\nstruct i915_frontbuffer {\n\tstruct intel_frontbuffer base;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_active write;\n\tstruct callback_head rcu;\n\tstruct kref ref;\n};\n\nstruct i915_gem_apply_to_region_ops;\n\nstruct i915_gem_apply_to_region {\n\tconst struct i915_gem_apply_to_region_ops *ops;\n\tstruct i915_gem_ww_ctx *ww;\n\tu32 interruptible: 1;\n};\n\nstruct i915_gem_apply_to_region_ops {\n\tint (*process_obj)(struct i915_gem_apply_to_region *, struct drm_i915_gem_object *);\n};\n\nstruct i915_sched_attr {\n\tint priority;\n};\n\nstruct i915_gem_engines;\n\nstruct i915_gem_context {\n\tstruct drm_i915_private *i915;\n\tstruct drm_i915_file_private *file_priv;\n\tstruct i915_gem_engines *engines;\n\tstruct mutex engines_mutex;\n\tstruct drm_syncobj *syncobj;\n\tstruct i915_address_space *vm;\n\tstruct pid *pid;\n\tstruct list_head link;\n\tstruct i915_drm_client *client;\n\tstruct list_head client_link;\n\tstruct kref ref;\n\tstruct work_struct release_work;\n\tstruct callback_head rcu;\n\tlong unsigned int user_flags;\n\tlong unsigned int flags;\n\tbool uses_protected_content;\n\tintel_wakeref_t pxp_wakeref;\n\tstruct mutex mutex;\n\tstruct i915_sched_attr sched;\n\tatomic_t guilty_count;\n\tatomic_t active_count;\n\tlong unsigned int hang_timestamp[2];\n\tu8 remap_slice;\n\tstruct xarray handles_vma;\n\tstruct mutex lut_mutex;\n\tchar name[24];\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head engines;\n\t} stale;\n};\n\nstruct i915_gem_context_coredump {\n\tchar comm[16];\n\tu64 total_runtime;\n\tu64 avg_runtime;\n\tpid_t pid;\n\tint active;\n\tint guilty;\n\tstruct i915_sched_attr sched_attr;\n\tu32 hwsp_seqno;\n};\n\nstruct i915_gem_context_param_context_image {\n\tstruct i915_engine_class_instance engine;\n\t__u32 flags;\n\t__u32 size;\n\t__u32 mbz;\n\t__u64 image;\n};\n\nstruct i915_gem_engines {\n\tunion {\n\t\tstruct list_head link;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct i915_sw_fence fence;\n\tstruct i915_gem_context *ctx;\n\tunsigned int num_engines;\n\tstruct intel_context *engines[0];\n};\n\nstruct i915_gem_engines_iter {\n\tunsigned int idx;\n\tconst struct i915_gem_engines *engines;\n};\n\nstruct i915_gem_proto_engine;\n\nstruct i915_gem_proto_context {\n\tstruct drm_i915_file_private *fpriv;\n\tstruct i915_address_space *vm;\n\tlong unsigned int user_flags;\n\tstruct i915_sched_attr sched;\n\tint num_user_engines;\n\tstruct i915_gem_proto_engine *user_engines;\n\tstruct intel_sseu legacy_rcs_sseu;\n\tbool single_timeline;\n\tbool uses_protected_content;\n\tintel_wakeref_t pxp_wakeref;\n};\n\nstruct i915_gem_proto_engine {\n\tenum i915_gem_engine_type type;\n\tstruct intel_engine_cs *engine;\n\tunsigned int num_siblings;\n\tunsigned int width;\n\tstruct intel_engine_cs **siblings;\n\tstruct intel_sseu sseu;\n};\n\nstruct i915_gem_ttm_pm_apply {\n\tstruct i915_gem_apply_to_region base;\n\tbool allow_gpu: 1;\n\tbool backup_pinned: 1;\n};\n\nstruct io_mapping {\n\tresource_size_t base;\n\tlong unsigned int size;\n\tpgprot_t prot;\n\tvoid *iomem;\n};\n\nstruct i915_ggtt {\n\tstruct i915_address_space vm;\n\tstruct io_mapping iomap;\n\tstruct resource gmadr;\n\tresource_size_t mappable_end;\n\tvoid *gsm;\n\tvoid (*invalidate)(struct i915_ggtt *);\n\tstruct i915_ppgtt *alias;\n\tbool do_idle_maps;\n\tint mtrr;\n\tu32 bit_6_swizzle_x;\n\tu32 bit_6_swizzle_y;\n\tu32 pin_bias;\n\tunsigned int num_fences;\n\tstruct i915_fence_reg *fence_regs;\n\tstruct list_head fence_list;\n\tstruct list_head userfault_list;\n\tstruct mutex error_mutex;\n\tstruct drm_mm_node error_capture;\n\tstruct drm_mm_node uc_fw;\n\tstruct list_head gt_list;\n};\n\nstruct intel_gt_definition;\n\nstruct intel_device_info {\n\tenum intel_platform platform;\n\tunsigned int dma_mask_size;\n\tconst struct intel_gt_definition *extra_gt_list;\n\tu8 gt;\n\tintel_engine_mask_t platform_engine_mask;\n\tu32 memory_regions;\n\tu8 is_mobile: 1;\n\tu8 require_force_probe: 1;\n\tu8 is_dgfx: 1;\n\tu8 has_64bit_reloc: 1;\n\tu8 has_64k_pages: 1;\n\tu8 gpu_reset_clobbers_display: 1;\n\tu8 has_reset_engine: 1;\n\tu8 has_3d_pipeline: 1;\n\tu8 has_flat_ccs: 1;\n\tu8 has_global_mocs: 1;\n\tu8 has_gmd_id: 1;\n\tu8 has_gt_uc: 1;\n\tu8 has_heci_pxp: 1;\n\tu8 has_heci_gscfi: 1;\n\tu8 has_guc_deprivilege: 1;\n\tu8 has_guc_tlb_invalidation: 1;\n\tu8 has_l3_ccs_read: 1;\n\tu8 has_l3_dpf: 1;\n\tu8 has_llc: 1;\n\tu8 has_logical_ring_contexts: 1;\n\tu8 has_logical_ring_elsq: 1;\n\tu8 has_media_ratio_mode: 1;\n\tu8 has_mslice_steering: 1;\n\tu8 has_oa_bpc_reporting: 1;\n\tu8 has_oa_slice_contrib_limits: 1;\n\tu8 has_oam: 1;\n\tu8 has_one_eu_per_fuse_bit: 1;\n\tu8 has_pxp: 1;\n\tu8 has_rc6: 1;\n\tu8 has_rc6p: 1;\n\tu8 has_rps: 1;\n\tu8 has_runtime_pm: 1;\n\tu8 has_snoop: 1;\n\tu8 has_coherent_ggtt: 1;\n\tu8 tuning_thread_rr_after_dep: 1;\n\tu8 unfenced_needs_alignment: 1;\n\tu8 hws_needs_physical: 1;\n\tconst struct intel_runtime_info __runtime;\n\tu32 cachelevel_to_pat[4];\n\tu32 max_pat_index;\n};\n\nstruct intel_gt_coredump;\n\nstruct intel_display_snapshot;\n\nstruct i915_gpu_coredump {\n\tstruct kref ref;\n\tktime_t time;\n\tktime_t boottime;\n\tktime_t uptime;\n\tlong unsigned int capture;\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt_coredump *gt;\n\tchar error_msg[128];\n\tbool simulated;\n\tbool wakelock;\n\tbool suspended;\n\tint iommu;\n\tu32 reset_count;\n\tu32 suspend_count;\n\tstruct intel_device_info device_info;\n\tstruct intel_runtime_info runtime_info;\n\tstruct intel_driver_caps driver_caps;\n\tstruct i915_params params;\n\tstruct scatterlist *sgl;\n\tstruct scatterlist *fit;\n\tstruct intel_display_snapshot *display_snapshot;\n};\n\nstruct i915_gsc_proxy_component_ops;\n\nstruct i915_gsc_proxy_component {\n\tstruct device *mei_dev;\n\tconst struct i915_gsc_proxy_component_ops *ops;\n};\n\nstruct i915_gsc_proxy_component_ops {\n\tstruct module *owner;\n\tint (*send)(struct device *, const void *, size_t);\n\tint (*recv)(struct device *, void *, size_t);\n};\n\nstruct intel_partial_info {\n\tu64 offset;\n\tunsigned int size;\n} __attribute__((packed));\n\nstruct intel_remapped_plane_info {\n\tu32 offset: 31;\n\tu32 linear: 1;\n\tunion {\n\t\tstruct {\n\t\t\tu16 width;\n\t\t\tu16 height;\n\t\t\tu16 src_stride;\n\t\t\tu16 dst_stride;\n\t\t};\n\t\tu32 size;\n\t};\n};\n\nstruct intel_rotation_info {\n\tstruct intel_remapped_plane_info plane[2];\n};\n\nstruct intel_remapped_info {\n\tstruct intel_remapped_plane_info plane[4];\n\tu32 plane_alignment;\n};\n\nstruct i915_gtt_view {\n\tenum i915_gtt_view_type type;\n\tunion {\n\t\tstruct intel_partial_info partial;\n\t\tstruct intel_rotation_info rotated;\n\t\tstruct intel_remapped_info remapped;\n\t};\n};\n\nstruct i915_hdcp_ops;\n\nstruct i915_hdcp_arbiter {\n\tstruct device *hdcp_dev;\n\tconst struct i915_hdcp_ops *ops;\n\tstruct mutex mutex;\n};\n\nstruct i915_hdcp_ops {\n\tstruct module *owner;\n\tint (*initiate_hdcp2_session)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_init *);\n\tint (*verify_receiver_cert_prepare_km)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_cert *, bool *, struct hdcp2_ake_no_stored_km *, size_t *);\n\tint (*verify_hprime)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_hprime *);\n\tint (*store_pairing_info)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_pairing_info *);\n\tint (*initiate_locality_check)(struct device *, struct hdcp_port_data *, struct hdcp2_lc_init *);\n\tint (*verify_lprime)(struct device *, struct hdcp_port_data *, struct hdcp2_lc_send_lprime *);\n\tint (*get_session_key)(struct device *, struct hdcp_port_data *, struct hdcp2_ske_send_eks *);\n\tint (*repeater_check_flow_prepare_ack)(struct device *, struct hdcp_port_data *, struct hdcp2_rep_send_receiverid_list *, struct hdcp2_rep_send_ack *);\n\tint (*verify_mprime)(struct device *, struct hdcp_port_data *, struct hdcp2_rep_stream_ready *);\n\tint (*enable_hdcp_authentication)(struct device *, struct hdcp_port_data *);\n\tint (*close_hdcp_session)(struct device *, struct hdcp_port_data *);\n};\n\nstruct i915_hwmon {\n\tstruct hwm_drvdata ddat;\n\tstruct hwm_drvdata ddat_gt[2];\n\tstruct mutex hwmon_lock;\n\tstruct hwm_reg rg;\n\tint scl_shift_power;\n\tint scl_shift_energy;\n\tint scl_shift_time;\n};\n\nstruct i915_irq_regs {\n\ti915_reg_t imr;\n\ti915_reg_t ier;\n\ti915_reg_t iir;\n};\n\nstruct i915_lut_handle {\n\tstruct list_head obj_link;\n\tstruct i915_gem_context *ctx;\n\tu32 handle;\n};\n\nstruct i915_mmap_offset {\n\tstruct drm_vma_offset_node vma_node;\n\tstruct drm_i915_gem_object *obj;\n\tenum i915_mmap_type mmap_type;\n\tstruct rb_node offset;\n};\n\nstruct i915_mmio_range {\n\tu32 start;\n\tu32 end;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct i915_oa_reg;\n\nstruct i915_oa_config {\n\tstruct i915_perf *perf;\n\tchar uuid[37];\n\tint id;\n\tconst struct i915_oa_reg *mux_regs;\n\tu32 mux_regs_len;\n\tconst struct i915_oa_reg *b_counter_regs;\n\tu32 b_counter_regs_len;\n\tconst struct i915_oa_reg *flex_regs;\n\tu32 flex_regs_len;\n\tstruct attribute_group sysfs_metric;\n\tstruct attribute *attrs[2];\n\tstruct kobj_attribute sysfs_metric_id;\n\tstruct kref ref;\n\tstruct callback_head rcu;\n};\n\nstruct i915_oa_config_bo {\n\tstruct llist_node node;\n\tstruct i915_oa_config *oa_config;\n\tstruct i915_vma *vma;\n};\n\nstruct i915_oa_format {\n\tu32 format;\n\tint size;\n\tint type;\n\tenum report_header header;\n};\n\nstruct i915_oa_reg {\n\ti915_reg_t addr;\n\tu32 value;\n};\n\nstruct i915_page_table {\n\tstruct drm_i915_gem_object *base;\n\tunion {\n\t\tatomic_t used;\n\t\tstruct i915_page_table *stash;\n\t};\n\tbool is_compact;\n};\n\nstruct i915_page_directory {\n\tstruct i915_page_table pt;\n\tspinlock_t lock;\n\tvoid **entry;\n};\n\nstruct i915_perf_regs {\n\tu32 base;\n\ti915_reg_t oa_head_ptr;\n\ti915_reg_t oa_tail_ptr;\n\ti915_reg_t oa_buffer;\n\ti915_reg_t oa_ctx_ctrl;\n\ti915_reg_t oa_ctrl;\n\ti915_reg_t oa_debug;\n\ti915_reg_t oa_status;\n\tu32 oa_ctrl_counter_format_shift;\n};\n\nstruct i915_perf_group {\n\tstruct i915_perf_stream *exclusive_stream;\n\tu32 num_engines;\n\tstruct i915_perf_regs regs;\n\tenum oa_type type;\n};\n\nstruct i915_perf_gt {\n\tstruct mutex lock;\n\tstruct intel_sseu sseu;\n\tu32 num_perf_groups;\n\tstruct i915_perf_group *group;\n};\n\nstruct i915_perf_stream_ops;\n\nstruct i915_perf_stream {\n\tstruct i915_perf *perf;\n\tstruct intel_uncore *uncore;\n\tstruct intel_engine_cs *engine;\n\tstruct mutex lock;\n\tu32 sample_flags;\n\tint sample_size;\n\tstruct i915_gem_context *ctx;\n\tbool enabled;\n\tbool hold_preemption;\n\tconst struct i915_perf_stream_ops *ops;\n\tstruct i915_oa_config *oa_config;\n\tstruct llist_head oa_config_bos;\n\tstruct intel_context *pinned_ctx;\n\tu32 specific_ctx_id;\n\tu32 specific_ctx_id_mask;\n\tstruct hrtimer poll_check_timer;\n\twait_queue_head_t poll_wq;\n\tbool pollin;\n\tbool periodic;\n\tint period_exponent;\n\tstruct {\n\t\tconst struct i915_oa_format *format;\n\t\tstruct i915_vma *vma;\n\t\tu8 *vaddr;\n\t\tu32 last_ctx_id;\n\t\tspinlock_t ptr_lock;\n\t\tu32 head;\n\t\tu32 tail;\n\t} oa_buffer;\n\tstruct i915_vma *noa_wait;\n\tu64 poll_oa_period;\n};\n\nstruct i915_perf_stream_ops {\n\tvoid (*enable)(struct i915_perf_stream *);\n\tvoid (*disable)(struct i915_perf_stream *);\n\tvoid (*poll_wait)(struct i915_perf_stream *, struct file *, poll_table *);\n\tint (*wait_unlocked)(struct i915_perf_stream *);\n\tint (*read)(struct i915_perf_stream *, char *, size_t, size_t *);\n\tvoid (*destroy)(struct i915_perf_stream *);\n};\n\nstruct i915_power_domain_list {\n\tconst enum intel_display_power_domain *list;\n\tu8 count;\n};\n\nstruct intel_power_domain_mask {\n\tlong unsigned int bits[2];\n};\n\nstruct i915_power_well;\n\nstruct i915_power_domains {\n\tbool initializing;\n\tbool display_core_suspended;\n\tint power_well_count;\n\tu32 dc_state;\n\tu32 target_dc_state;\n\tu32 allowed_dc_mask;\n\tstruct ref_tracker *init_wakeref;\n\tstruct ref_tracker *disable_wakeref;\n\tstruct mutex lock;\n\tint domain_use_count[76];\n\tstruct delayed_work async_put_work;\n\tstruct ref_tracker *async_put_wakeref;\n\tstruct intel_power_domain_mask async_put_domains[2];\n\tint async_put_next_delay;\n\tstruct i915_power_well *power_wells;\n};\n\nstruct i915_power_well_desc;\n\nstruct i915_power_well {\n\tconst struct i915_power_well_desc *desc;\n\tstruct intel_power_domain_mask domains;\n\tint count;\n\tbool hw_enabled;\n\tu8 instance_idx;\n};\n\nstruct i915_power_well_ops;\n\nstruct i915_power_well_instance_list;\n\nstruct i915_power_well_desc {\n\tconst struct i915_power_well_ops *ops;\n\tconst struct i915_power_well_instance_list *instances;\n\tu16 irq_pipe_mask: 4;\n\tu16 always_on: 1;\n\tu16 fixed_enable_delay: 1;\n\tu16 has_vga: 1;\n\tu16 has_fuses: 1;\n\tu16 is_tc_tbt: 1;\n\tu16 enable_timeout;\n};\n\nstruct i915_power_well_desc_list {\n\tconst struct i915_power_well_desc *list;\n\tu8 count;\n};\n\nstruct i915_power_well_instance {\n\tconst char *name;\n\tconst struct i915_power_domain_list *domain_list;\n\tenum i915_power_well_id id;\n\tunion {\n\t\tstruct {\n\t\t\tu8 idx;\n\t\t} vlv;\n\t\tstruct {\n\t\t\tenum dpio_phy phy;\n\t\t} bxt;\n\t\tstruct {\n\t\t\tu8 idx;\n\t\t} hsw;\n\t\tstruct {\n\t\t\tu8 aux_ch;\n\t\t} xelpdp;\n\t};\n};\n\nstruct i915_power_well_instance_list {\n\tconst struct i915_power_well_instance *list;\n\tu8 count;\n};\n\nstruct i915_power_well_regs;\n\nstruct i915_power_well_ops {\n\tconst struct i915_power_well_regs *regs;\n\tvoid (*sync_hw)(struct intel_display *, struct i915_power_well *);\n\tvoid (*enable)(struct intel_display *, struct i915_power_well *);\n\tvoid (*disable)(struct intel_display *, struct i915_power_well *);\n\tbool (*is_enabled)(struct intel_display *, struct i915_power_well *);\n};\n\nstruct i915_power_well_regs {\n\ti915_reg_t bios;\n\ti915_reg_t driver;\n\ti915_reg_t kvmr;\n\ti915_reg_t debug;\n};\n\nstruct i915_priolist {\n\tstruct list_head requests;\n\tstruct rb_node node;\n\tint priority;\n};\n\nstruct i915_pxp_component_ops;\n\nstruct i915_pxp_component {\n\tstruct device *tee_dev;\n\tconst struct i915_pxp_component_ops *ops;\n\tstruct mutex mutex;\n};\n\nstruct i915_pxp_component_ops {\n\tstruct module *owner;\n\tint (*send)(struct device *, const void *, size_t, long unsigned int);\n\tint (*recv)(struct device *, void *, size_t, long unsigned int);\n\tssize_t (*gsc_command)(struct device *, u8, u32, struct scatterlist *, size_t, struct scatterlist *);\n};\n\nstruct i915_refct_sgt_ops;\n\nstruct i915_refct_sgt {\n\tstruct kref kref;\n\tstruct sg_table table;\n\tsize_t size;\n\tconst struct i915_refct_sgt_ops *ops;\n};\n\nstruct i915_refct_sgt_ops {\n\tvoid (*release)(struct kref *);\n};\n\nstruct i915_request_duration_cb {\n\tstruct dma_fence_cb cb;\n\tktime_t emitted;\n};\n\nstruct i915_sched_node {\n\tstruct list_head signalers_list;\n\tstruct list_head waiters_list;\n\tstruct list_head link;\n\tstruct i915_sched_attr attr;\n\tunsigned int flags;\n\tintel_engine_mask_t semaphores;\n};\n\nstruct i915_request_watchdog {\n\tstruct llist_node link;\n\tstruct hrtimer timer;\n};\n\nstruct i915_request {\n\tstruct dma_fence fence;\n\tspinlock_t lock;\n\tstruct drm_i915_private *i915;\n\tstruct intel_engine_cs *engine;\n\tstruct intel_context *context;\n\tstruct intel_ring *ring;\n\tstruct intel_timeline *timeline;\n\tstruct list_head signal_link;\n\tstruct llist_node signal_node;\n\tlong unsigned int rcustate;\n\tstruct pin_cookie cookie;\n\tstruct i915_sw_fence submit;\n\tunion {\n\t\twait_queue_entry_t submitq;\n\t\tstruct i915_sw_dma_fence_cb dmaq;\n\t\tstruct i915_request_duration_cb duration;\n\t};\n\tstruct llist_head execute_cb;\n\tstruct i915_sw_fence semaphore;\n\tstruct irq_work submit_work;\n\tstruct i915_sched_node sched;\n\tstruct i915_dependency dep;\n\tintel_engine_mask_t execution_mask;\n\tconst u32 *hwsp_seqno;\n\tu32 head;\n\tu32 infix;\n\tu32 postfix;\n\tu32 tail;\n\tu32 wa_tail;\n\tu32 reserved_space;\n\tstruct i915_vma_resource *batch_res;\n\tstruct i915_capture_list *capture_list;\n\tlong unsigned int emitted_jiffies;\n\tstruct list_head link;\n\tstruct i915_request_watchdog watchdog;\n\tstruct list_head guc_fence_link;\n\tu8 guc_prio;\n\twait_queue_entry_t hucq;\n};\n\nstruct i915_request_coredump {\n\tlong unsigned int flags;\n\tpid_t pid;\n\tu32 context;\n\tu32 seqno;\n\tu32 head;\n\tu32 tail;\n\tstruct i915_sched_attr sched_attr;\n};\n\nstruct i915_sched_engine {\n\tstruct kref ref;\n\tspinlock_t lock;\n\tstruct list_head requests;\n\tstruct list_head hold;\n\tstruct tasklet_struct tasklet;\n\tstruct i915_priolist default_priolist;\n\tint queue_priority_hint;\n\tstruct rb_root_cached queue;\n\tbool no_priolist;\n\tvoid *private_data;\n\tvoid (*destroy)(struct kref *);\n\tbool (*disabled)(struct i915_sched_engine *);\n\tvoid (*kick_backend)(const struct i915_request *, int);\n\tvoid (*bump_inflight_request_prio)(struct i915_request *, int);\n\tvoid (*retire_inflight_request_prio)(struct i915_request *);\n\tvoid (*schedule)(struct i915_request *, const struct i915_sched_attr *);\n};\n\nstruct i915_str_attribute {\n\tstruct device_attribute attr;\n\tconst char *str;\n};\n\nstruct i915_sw_dma_fence_cb_timer {\n\tstruct i915_sw_dma_fence_cb base;\n\tstruct dma_fence *dma;\n\tstruct timer_list timer;\n\tstruct irq_work work;\n\tstruct callback_head rcu;\n};\n\nstruct i915_syncmap {\n\tu64 prefix;\n\tunsigned int height;\n\tunsigned int bitmap;\n\tstruct i915_syncmap *parent;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_seqno;\n\t\t\tu32 seqno[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_child;\n\t\t\tstruct i915_syncmap *child[0];\n\t\t};\n\t};\n};\n\nstruct i915_ttm_buddy_manager {\n\tstruct ttm_resource_manager manager;\n\tstruct drm_buddy mm;\n\tstruct list_head reserved;\n\tstruct mutex lock;\n\tlong unsigned int visible_size;\n\tlong unsigned int visible_avail;\n\tlong unsigned int visible_reserved;\n\tu64 default_page_size;\n};\n\nstruct ttm_bus_placement {\n\tvoid *addr;\n\tphys_addr_t offset;\n\tbool is_iomem;\n\tenum ttm_caching caching;\n};\n\nstruct dmem_cgroup_pool_state;\n\nstruct ttm_lru_item {\n\tstruct list_head link;\n\tenum ttm_lru_item_type type;\n};\n\nstruct ttm_resource {\n\tlong unsigned int start;\n\tsize_t size;\n\tuint32_t mem_type;\n\tuint32_t placement;\n\tstruct ttm_bus_placement bus;\n\tstruct ttm_buffer_object *bo;\n\tstruct dmem_cgroup_pool_state *css;\n\tstruct ttm_lru_item lru;\n};\n\nstruct i915_ttm_buddy_resource {\n\tstruct ttm_resource base;\n\tstruct list_head blocks;\n\tlong unsigned int flags;\n\tlong unsigned int used_visible_size;\n\tstruct drm_buddy *mm;\n};\n\nstruct ttm_kmap_iter_ops;\n\nstruct ttm_kmap_iter {\n\tconst struct ttm_kmap_iter_ops *ops;\n};\n\nstruct ttm_kmap_iter_tt {\n\tstruct ttm_kmap_iter base;\n\tstruct ttm_tt *tt;\n\tpgprot_t prot;\n};\n\nstruct ttm_kmap_iter_iomap {\n\tstruct ttm_kmap_iter base;\n\tstruct io_mapping *iomap;\n\tstruct sg_table *st;\n\tresource_size_t start;\n\tstruct {\n\t\tstruct scatterlist *sg;\n\t\tlong unsigned int i;\n\t\tlong unsigned int end;\n\t\tlong unsigned int offs;\n\t} cache;\n};\n\nstruct i915_ttm_memcpy_arg {\n\tunion {\n\t\tstruct ttm_kmap_iter_tt tt;\n\t\tstruct ttm_kmap_iter_iomap io;\n\t} _dst_iter;\n\tunion {\n\t\tstruct ttm_kmap_iter_tt tt;\n\t\tstruct ttm_kmap_iter_iomap io;\n\t} _src_iter;\n\tstruct ttm_kmap_iter *dst_iter;\n\tstruct ttm_kmap_iter *src_iter;\n\tlong unsigned int num_pages;\n\tbool clear;\n\tstruct i915_refct_sgt *src_rsgt;\n\tstruct i915_refct_sgt *dst_rsgt;\n};\n\nstruct i915_ttm_memcpy_work {\n\tstruct dma_fence fence;\n\tstruct work_struct work;\n\tspinlock_t lock;\n\tstruct irq_work irq_work;\n\tstruct dma_fence_cb cb;\n\tstruct i915_ttm_memcpy_arg arg;\n\tstruct drm_i915_private *i915;\n\tstruct drm_i915_gem_object *obj;\n\tbool memcpy_allowed;\n};\n\nstruct ttm_pool_tt_restore;\n\nstruct ttm_tt {\n\tstruct page **pages;\n\tuint32_t page_flags;\n\tuint32_t num_pages;\n\tstruct sg_table *sg;\n\tdma_addr_t *dma_address;\n\tstruct file *swap_storage;\n\tstruct file *backup;\n\tenum ttm_caching caching;\n\tstruct ttm_pool_tt_restore *restore;\n};\n\nstruct i915_ttm_tt {\n\tstruct ttm_tt ttm;\n\tstruct device *dev;\n\tstruct i915_refct_sgt cached_rsgt;\n\tbool is_shmem;\n\tstruct file *filp;\n};\n\nstruct i915_vm_pt_stash {\n\tstruct i915_page_table *pt[2];\n\tint pt_sz;\n};\n\nstruct i915_vma {\n\tstruct drm_mm_node node;\n\tstruct i915_address_space *vm;\n\tconst struct i915_vma_ops *ops;\n\tstruct drm_i915_gem_object *obj;\n\tstruct sg_table *pages;\n\tvoid *iomap;\n\tvoid *private;\n\tstruct i915_fence_reg *fence;\n\tu64 size;\n\tstruct i915_page_sizes page_sizes;\n\tstruct i915_mmap_offset *mmo;\n\tu32 guard;\n\tu32 fence_size;\n\tu32 fence_alignment;\n\tu32 display_alignment;\n\tatomic_t open_count;\n\tatomic_t flags;\n\tstruct i915_active active;\n\tatomic_t pages_count;\n\tbool vm_ddestroy;\n\tstruct i915_gtt_view gtt_view;\n\tstruct list_head vm_link;\n\tstruct list_head obj_link;\n\tstruct rb_node obj_node;\n\tstruct list_head evict_link;\n\tstruct list_head closed_link;\n\tstruct i915_vma_resource *resource;\n};\n\nstruct i915_vma_bindinfo {\n\tstruct sg_table *pages;\n\tstruct i915_page_sizes page_sizes;\n\tstruct i915_refct_sgt *pages_rsgt;\n\tbool readonly: 1;\n\tbool lmem: 1;\n};\n\nstruct internal_state;\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\nstruct i915_vma_compress {\n\tstruct folio_batch pool;\n\tstruct z_stream_s zstream;\n\tvoid *tmp;\n};\n\nstruct i915_vma_coredump {\n\tstruct i915_vma_coredump *next;\n\tchar name[20];\n\tu64 gtt_offset;\n\tu64 gtt_size;\n\tu32 gtt_page_sizes;\n\tint unused;\n\tstruct list_head page_list;\n};\n\nstruct i915_vma_resource {\n\tstruct dma_fence unbind_fence;\n\tspinlock_t lock;\n\trefcount_t hold_count;\n\tstruct work_struct work;\n\tstruct i915_sw_fence chain;\n\tstruct rb_node rb;\n\tu64 __subtree_last;\n\tstruct i915_address_space *vm;\n\tintel_wakeref_t wakeref;\n\tstruct i915_vma_bindinfo bi;\n\tstruct intel_memory_region *mr;\n\tconst struct i915_vma_ops *ops;\n\tvoid *private;\n\tu64 start;\n\tu64 node_size;\n\tu64 vma_size;\n\tu32 guard;\n\tu32 page_sizes_gtt;\n\tu32 bound_flags;\n\tbool allocated: 1;\n\tbool immediate_unbind: 1;\n\tbool needs_wakeref: 1;\n\tbool skip_pte_rewrite: 1;\n\tu32 *tlb;\n};\n\nstruct i915_vma_work {\n\tstruct dma_fence_work base;\n\tstruct i915_address_space *vm;\n\tstruct i915_vm_pt_stash stash;\n\tstruct i915_vma_resource *vma_res;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_sw_dma_fence_cb cb;\n\tunsigned int pat_index;\n\tunsigned int flags;\n};\n\nstruct i915_wa {\n\tunion {\n\t\ti915_reg_t reg;\n\t\ti915_mcr_reg_t mcr_reg;\n\t};\n\tu32 clr;\n\tu32 set;\n\tu32 read;\n\tu32 masked_reg: 1;\n\tu32 is_mcr: 1;\n};\n\nstruct i9xx_dpll_hw_state {\n\tu32 dpll;\n\tu32 dpll_md;\n\tu32 fp0;\n\tu32 fp1;\n};\n\nstruct ia_constants {\n\tunsigned int min_gpu_freq;\n\tunsigned int max_gpu_freq;\n\tunsigned int min_ring_freq;\n\tunsigned int max_ia_freq;\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n};\n\nunion ibs_fetch_ctl {\n\t__u64 val;\n\tstruct {\n\t\t__u64 fetch_maxcnt: 16;\n\t\t__u64 fetch_cnt: 16;\n\t\t__u64 fetch_lat: 16;\n\t\t__u64 fetch_en: 1;\n\t\t__u64 fetch_val: 1;\n\t\t__u64 fetch_comp: 1;\n\t\t__u64 ic_miss: 1;\n\t\t__u64 phy_addr_valid: 1;\n\t\t__u64 l1tlb_pgsz: 2;\n\t\t__u64 l1tlb_miss: 1;\n\t\t__u64 l2tlb_miss: 1;\n\t\t__u64 rand_en: 1;\n\t\t__u64 fetch_l2_miss: 1;\n\t\t__u64 l3_miss_only: 1;\n\t\t__u64 fetch_oc_miss: 1;\n\t\t__u64 fetch_l3_miss: 1;\n\t\t__u64 reserved: 2;\n\t};\n};\n\nunion ibs_op_ctl {\n\t__u64 val;\n\tstruct {\n\t\t__u64 opmaxcnt: 16;\n\t\t__u64 l3_miss_only: 1;\n\t\t__u64 op_en: 1;\n\t\t__u64 op_val: 1;\n\t\t__u64 cnt_ctl: 1;\n\t\t__u64 opmaxcnt_ext: 7;\n\t\t__u64 reserved0: 5;\n\t\t__u64 opcurcnt: 27;\n\t\t__u64 ldlat_thrsh: 4;\n\t\t__u64 ldlat_en: 1;\n\t};\n};\n\nunion ibs_op_data {\n\t__u64 val;\n\tstruct {\n\t\t__u64 comp_to_ret_ctr: 16;\n\t\t__u64 tag_to_ret_ctr: 16;\n\t\t__u64 reserved1: 2;\n\t\t__u64 op_return: 1;\n\t\t__u64 op_brn_taken: 1;\n\t\t__u64 op_brn_misp: 1;\n\t\t__u64 op_brn_ret: 1;\n\t\t__u64 op_rip_invalid: 1;\n\t\t__u64 op_brn_fuse: 1;\n\t\t__u64 op_microcode: 1;\n\t\t__u64 reserved2: 23;\n\t};\n};\n\nunion ibs_op_data2 {\n\t__u64 val;\n\tstruct {\n\t\t__u64 data_src_lo: 3;\n\t\t__u64 reserved0: 1;\n\t\t__u64 rmt_node: 1;\n\t\t__u64 cache_hit_st: 1;\n\t\t__u64 data_src_hi: 2;\n\t\t__u64 reserved1: 56;\n\t};\n};\n\nunion ibs_op_data3 {\n\t__u64 val;\n\tstruct {\n\t\t__u64 ld_op: 1;\n\t\t__u64 st_op: 1;\n\t\t__u64 dc_l1tlb_miss: 1;\n\t\t__u64 dc_l2tlb_miss: 1;\n\t\t__u64 dc_l1tlb_hit_2m: 1;\n\t\t__u64 dc_l1tlb_hit_1g: 1;\n\t\t__u64 dc_l2tlb_hit_2m: 1;\n\t\t__u64 dc_miss: 1;\n\t\t__u64 dc_mis_acc: 1;\n\t\t__u64 reserved: 4;\n\t\t__u64 dc_wc_mem_acc: 1;\n\t\t__u64 dc_uc_mem_acc: 1;\n\t\t__u64 dc_locked_op: 1;\n\t\t__u64 dc_miss_no_mab_alloc: 1;\n\t\t__u64 dc_lin_addr_valid: 1;\n\t\t__u64 dc_phy_addr_valid: 1;\n\t\t__u64 dc_l2_tlb_hit_1g: 1;\n\t\t__u64 l2_miss: 1;\n\t\t__u64 sw_pf: 1;\n\t\t__u64 op_mem_width: 4;\n\t\t__u64 op_dc_miss_open_mem_reqs: 6;\n\t\t__u64 dc_miss_lat: 16;\n\t\t__u64 tlb_refill_lat: 16;\n\t};\n};\n\nstruct ibx_audio_regs {\n\ti915_reg_t hdmiw_hdmiedid;\n\ti915_reg_t aud_config;\n\ti915_reg_t aud_cntl_st;\n\ti915_reg_t aud_cntrl_st2;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct ich_laptop {\n\tu16 device;\n\tu16 subvendor;\n\tu16 subdevice;\n};\n\nstruct snd_pcm_ops;\n\nstruct ich_pcm_table {\n\tchar *suffix;\n\tconst struct snd_pcm_ops *playback_ops;\n\tconst struct snd_pcm_ops *capture_ops;\n\tsize_t prealloc_size;\n\tsize_t prealloc_max_size;\n\tint ac97_idx;\n};\n\nstruct ich_reg_info {\n\tunsigned int int_sta_mask;\n\tunsigned int offset;\n};\n\nstruct ichdev {\n\tunsigned int ichd;\n\tlong unsigned int reg_offset;\n\t__le32 *bdbar;\n\tunsigned int bdbar_addr;\n\tstruct snd_pcm_substream *substream;\n\tunsigned int physbuf;\n\tunsigned int size;\n\tunsigned int fragsize;\n\tunsigned int fragsize1;\n\tunsigned int position;\n\tunsigned int pos_shift;\n\tunsigned int last_pos;\n\tint frags;\n\tint lvi;\n\tint lvi_frag;\n\tint civ;\n\tint ack;\n\tint ack_reload;\n\tunsigned int ack_bit;\n\tunsigned int roff_sr;\n\tunsigned int roff_picb;\n\tunsigned int int_sta_mask;\n\tunsigned int ali_slot;\n\tstruct ac97_pcm *pcm;\n\tint pcm_open_flag;\n\tunsigned int prepared: 1;\n\tunsigned int suspended: 1;\n};\n\nstruct skl_wrpll_params {\n\tu32 dco_fraction;\n\tu32 dco_integer;\n\tu32 qdiv_ratio;\n\tu32 qdiv_mode;\n\tu32 kdiv;\n\tu32 pdiv;\n\tu32 central_freq;\n};\n\nstruct icl_combo_pll_params {\n\tint clock;\n\tstruct skl_wrpll_params wrpll;\n};\n\nstruct icl_ddi_buf_trans {\n\tu8 dw2_swing_sel;\n\tu8 dw7_n_scalar;\n\tu8 dw4_cursor_coeff;\n\tu8 dw4_post_cursor_2;\n\tu8 dw4_post_cursor_1;\n};\n\nstruct icl_dpll_hw_state {\n\tu32 cfgcr0;\n\tu32 cfgcr1;\n\tu32 div0;\n\tu32 mg_refclkin_ctl;\n\tu32 mg_clktop2_coreclkctl1;\n\tu32 mg_clktop2_hsclkctl;\n\tu32 mg_pll_div0;\n\tu32 mg_pll_div1;\n\tu32 mg_pll_lf;\n\tu32 mg_pll_frac_lock;\n\tu32 mg_pll_ssc;\n\tu32 mg_pll_bias;\n\tu32 mg_pll_tdc_coldst_bias;\n\tu32 mg_pll_bias_mask;\n\tu32 mg_pll_tdc_coldst_bias_mask;\n};\n\nstruct icl_mg_phy_ddi_buf_trans {\n\tu8 cri_txdeemph_override_11_6;\n\tu8 cri_txdeemph_override_5_0;\n\tu8 cri_txdeemph_override_17_12;\n};\n\nstruct skl_dpll_hw_state {\n\tu32 ctrl1;\n\tu32 cfgcr1;\n\tu32 cfgcr2;\n};\n\nstruct intel_mpllb_state {\n\tu32 clock;\n\tu32 ref_control;\n\tu32 mpllb_cp;\n\tu32 mpllb_div;\n\tu32 mpllb_div2;\n\tu32 mpllb_fracn1;\n\tu32 mpllb_fracn2;\n\tu32 mpllb_sscen;\n\tu32 mpllb_sscstep;\n};\n\nstruct intel_c10pll_state {\n\tu32 clock;\n\tu8 tx;\n\tu8 cmn;\n\tu8 pll[20];\n};\n\nstruct intel_c20pll_vdr_state {\n\tu8 custom_width;\n\tu8 serdes_rate;\n\tu8 hdmi_rate;\n};\n\nstruct intel_c20pll_state {\n\tu32 clock;\n\tu16 tx[3];\n\tu16 cmn[4];\n\tunion {\n\t\tu16 mplla[10];\n\t\tu16 mpllb[11];\n\t};\n\tstruct intel_c20pll_vdr_state vdr;\n};\n\nstruct intel_cx0pll_state {\n\tunion {\n\t\tstruct intel_c10pll_state c10;\n\t\tstruct intel_c20pll_state c20;\n\t};\n\tint lane_count;\n\tbool ssc_enabled;\n\tbool use_c10;\n\tbool tbt_mode;\n};\n\nstruct intel_lt_phy_pll_state {\n\tu32 clock;\n\tu8 addr_msb[13];\n\tu8 addr_lsb[13];\n\tu8 data[52];\n\tu8 config[3];\n\tbool ssc_enabled;\n\tbool tbt_mode;\n};\n\nstruct intel_dpll_hw_state {\n\tunion {\n\t\tstruct i9xx_dpll_hw_state i9xx;\n\t\tstruct hsw_dpll_hw_state hsw;\n\t\tstruct skl_dpll_hw_state skl;\n\t\tstruct bxt_dpll_hw_state bxt;\n\t\tstruct icl_dpll_hw_state icl;\n\t\tstruct intel_mpllb_state mpllb;\n\t\tstruct intel_cx0pll_state cx0pll;\n\t\tstruct intel_lt_phy_pll_state ltpll;\n\t};\n};\n\nstruct intel_dpll;\n\nstruct icl_port_dpll {\n\tstruct intel_dpll *pll;\n\tstruct intel_dpll_hw_state hw_state;\n};\n\nstruct icl_procmon {\n\tconst char *name;\n\tu32 dw1;\n\tu32 dw9;\n\tu32 dw10;\n};\n\nstruct iclkip_params {\n\tu32 iclk_virtual_root_freq;\n\tu32 iclk_pi_range;\n\tu32 divsel;\n\tu32 phaseinc;\n\tu32 auxdiv;\n\tu32 phasedir;\n\tu32 desired_divisor;\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 reserved1: 4;\n\t__u8 version: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct id_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tunion {\n\t\t__u32 ruid;\n\t\t__u32 rgid;\n\t} r;\n\tunion {\n\t\t__u32 euid;\n\t\t__u32 egid;\n\t} e;\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[16];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n};\n\nstruct idt_data {\n\tunsigned int vector;\n\tunsigned int segment;\n\tstruct idt_bits bits;\n\tconst void *addr;\n};\n\nstruct if_dqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n};\n\nstruct if_dqinfo {\n\t__u64 dqi_bgrace;\n\t__u64 dqi_igrace;\n\t__u32 dqi_flags;\n\t__u32 dqi_valid;\n};\n\nstruct if_nextdqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n\t__u32 dqb_id;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifreq;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct inet6_dev;\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpmsg {\n\t__u32 unused1;\n\t__u32 unused2;\n\tunsigned char im_msgtype;\n\tunsigned char im_mbz;\n\tunsigned char im_vif;\n\tunsigned char im_vif_hi;\n\tstruct in_addr im_src;\n\tstruct in_addr im_dst;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 qrv: 3;\n\t__u8 suppress: 1;\n\t__u8 resv: 4;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct ilk_wm_maximums {\n\tu16 pri;\n\tu16 spr;\n\tu16 cur;\n\tu16 fbc;\n};\n\nstruct ilk_wm_values {\n\tu32 wm_pipe[3];\n\tu32 wm_lp[3];\n\tu32 wm_lp_spr[3];\n\tbool enable_fbc_wm;\n\tenum intel_ddb_partitioning partitioning;\n};\n\nstruct imc_uncore_pci_dev {\n\t__u32 pci_id;\n\tstruct pci_driver *driver;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[1];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nunion inet_addr {\n\t__be32 ip;\n\tstruct in6_addr in6;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\t__be32 rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n};\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct proto_ops;\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t};\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\nstruct x86_mapping_info;\n\nstruct init_pgtable_data {\n\tstruct x86_mapping_info *info;\n\tpgd_t *level4p;\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[12];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[1];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[2];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[12];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[12];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[1];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[2];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_event_compat {\n\tcompat_ulong_t sec;\n\tcompat_ulong_t usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_led {\n\tstruct led_classdev cdev;\n\tstruct input_handle *handle;\n\tunsigned int code;\n};\n\nstruct input_leds {\n\tstruct input_handle handle;\n\tunsigned int num_leds;\n\tstruct input_led leds[0];\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_res {\n\tu16 w;\n\tu16 h;\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insert_entries {\n\tstruct i915_address_space *vm;\n\tstruct i915_vma_resource *vma_res;\n\tunsigned int pat_index;\n\tu32 flags;\n};\n\nstruct insert_page {\n\tstruct i915_address_space *vm;\n\tdma_addr_t addr;\n\tu64 offset;\n\tunsigned int pat_index;\n};\n\nstruct insert_pte_data {\n\tu64 offset;\n};\n\nstruct insn_field {\n\tunion {\n\t\tinsn_value_t value;\n\t\tinsn_byte_t bytes[4];\n\t};\n\tunsigned char got;\n\tunsigned char nbytes;\n};\n\nstruct insn {\n\tstruct insn_field prefixes;\n\tstruct insn_field rex_prefix;\n\tunion {\n\t\tstruct insn_field vex_prefix;\n\t\tstruct insn_field xop_prefix;\n\t};\n\tstruct insn_field opcode;\n\tstruct insn_field modrm;\n\tstruct insn_field sib;\n\tstruct insn_field displacement;\n\tunion {\n\t\tstruct insn_field immediate;\n\t\tstruct insn_field moffset1;\n\t\tstruct insn_field immediate1;\n\t};\n\tunion {\n\t\tstruct insn_field moffset2;\n\t\tstruct insn_field immediate2;\n\t};\n\tint emulate_prefix_size;\n\tinsn_attr_t attr;\n\tunsigned char opnd_bytes;\n\tunsigned char addr_bytes;\n\tunsigned char length;\n\tunsigned char x86_64;\n\tconst insn_byte_t *kaddr;\n\tconst insn_byte_t *end_kaddr;\n\tconst insn_byte_t *next_byte;\n};\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nstruct instr_dual {\n\tstruct opcode mod012;\n\tstruct opcode mod3;\n};\n\nunion intcapxt {\n\tu64 capxt;\n\tstruct {\n\t\tu64 reserved_0: 2;\n\t\tu64 dest_mode_logical: 1;\n\t\tu64 reserved_1: 5;\n\t\tu64 destid_0_23: 24;\n\t\tu64 vector: 8;\n\t\tu64 reserved_2: 16;\n\t\tu64 destid_24_31: 8;\n\t};\n};\n\nstruct intel8x0 {\n\tunsigned int device_type;\n\tint irq;\n\tvoid *addr;\n\tvoid *bmaddr;\n\tstruct pci_dev *pci;\n\tstruct snd_card *card;\n\tint pcm_devs;\n\tstruct snd_pcm *pcm[6];\n\tstruct ichdev ichd[6];\n\tunsigned int multi4: 1;\n\tunsigned int multi6: 1;\n\tunsigned int multi8: 1;\n\tunsigned int dra: 1;\n\tunsigned int smp20bit: 1;\n\tunsigned int in_ac97_init: 1;\n\tunsigned int in_sdin_init: 1;\n\tunsigned int in_measurement: 1;\n\tunsigned int fix_nocache: 1;\n\tunsigned int buggy_irq: 1;\n\tunsigned int xbox: 1;\n\tunsigned int buggy_semaphore: 1;\n\tunsigned int inside_vm: 1;\n\tint spdif_idx;\n\tunsigned int sdm_saved;\n\tstruct snd_ac97_bus *ac97_bus;\n\tstruct snd_ac97 *ac97[3];\n\tunsigned int ac97_sdin[3];\n\tunsigned int max_codecs;\n\tunsigned int ncodecs;\n\tconst unsigned int *codec_bit;\n\tunsigned int codec_isr_bits;\n\tunsigned int codec_ready_bits;\n\tspinlock_t reg_lock;\n\tu32 bdbars_count;\n\tstruct snd_dma_buffer *bdbars;\n\tu32 int_sta_reg;\n\tu32 int_sta_mask;\n};\n\nstruct intel_agp_driver_description {\n\tunsigned int chip_id;\n\tchar *name;\n\tconst struct agp_bridge_driver *driver;\n};\n\nstruct intel_dpll_state {\n\tu8 pipe_mask;\n\tstruct intel_dpll_hw_state hw_state;\n};\n\nstruct intel_dp_tunnel_inherited_state;\n\nstruct intel_global_objs_state;\n\nstruct intel_atomic_state {\n\tstruct drm_atomic_state base;\n\tstruct ref_tracker *wakeref;\n\tstruct intel_global_objs_state *global_objs;\n\tint num_global_objs;\n\tbool internal;\n\tbool dpll_set;\n\tbool modeset;\n\tstruct intel_dpll_state dpll_state[9];\n\tstruct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;\n\tbool skip_intermediate_wm;\n\tbool rps_interactive;\n\tstruct work_struct cleanup_work;\n};\n\nstruct intel_encoder;\n\nstruct intel_audio_state {\n\tstruct intel_encoder *encoder;\n\tu8 eld[128];\n};\n\nstruct intel_audio {\n\tstruct i915_audio_component *component;\n\tbool component_registered;\n\tstruct mutex mutex;\n\tint power_refcount;\n\tu32 freq_cntrl;\n\tstruct intel_audio_state state[7];\n\tstruct {\n\t\tstruct platform_device *platdev;\n\t\tint irq;\n\t} lpe;\n};\n\nstruct intel_crtc_state;\n\nstruct intel_audio_funcs {\n\tvoid (*audio_codec_enable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_codec_disable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_codec_get_config)(struct intel_encoder *, struct intel_crtc_state *);\n};\n\nstruct intel_bios_encoder_data {\n\tstruct intel_display *display;\n\tstruct child_device_config child;\n\tstruct dsc_compression_parameters_entry *dsc;\n\tstruct list_head node;\n};\n\nstruct intel_breadcrumbs {\n\tstruct kref ref;\n\tatomic_t active;\n\tspinlock_t signalers_lock;\n\tstruct list_head signalers;\n\tstruct llist_head signaled_requests;\n\tatomic_t signaler_active;\n\tspinlock_t irq_lock;\n\tstruct irq_work irq_work;\n\tunsigned int irq_enabled;\n\tintel_wakeref_t irq_armed;\n\tintel_engine_mask_t engine_mask;\n\tstruct intel_engine_cs *irq_engine;\n\tbool (*irq_enable)(struct intel_breadcrumbs *);\n\tvoid (*irq_disable)(struct intel_breadcrumbs *);\n};\n\nstruct intel_bw_info {\n\tunsigned int deratedbw[8];\n\tunsigned int psf_bw[3];\n\tunsigned int peakbw[8];\n\tu8 num_qgv_points;\n\tu8 num_psf_gv_points;\n\tu8 num_planes;\n};\n\nstruct intel_global_obj;\n\nstruct intel_global_commit;\n\nstruct intel_global_state {\n\tstruct intel_global_obj *obj;\n\tstruct intel_atomic_state *state;\n\tstruct intel_global_commit *commit;\n\tstruct kref ref;\n\tbool changed;\n\tbool serialized;\n};\n\nstruct intel_bw_state {\n\tstruct intel_global_state base;\n\tu8 pipe_sagv_reject;\n\tu8 active_pipes;\n\tu16 qgv_point_peakbw;\n\tu16 qgv_points_mask;\n\tunsigned int data_rate[4];\n\tu8 num_active_planes[4];\n};\n\nstruct scaler_filter_coeff {\n\tu16 sign;\n\tu16 exp;\n\tu16 mantissa;\n};\n\nstruct intel_casf {\n\tstruct scaler_filter_coeff coeff[7];\n\tu8 strength;\n\tu8 win_size;\n\tbool casf_enable;\n};\n\nstruct intel_cdclk_config {\n\tunsigned int cdclk;\n\tunsigned int vco;\n\tunsigned int ref;\n\tunsigned int bypass;\n\tu8 voltage_level;\n\tbool joined_mbus;\n};\n\nstruct intel_cdclk_funcs {\n\tvoid (*get_cdclk)(struct intel_display *, struct intel_cdclk_config *);\n\tvoid (*set_cdclk)(struct intel_display *, const struct intel_cdclk_config *, enum pipe);\n\tint (*modeset_calc_cdclk)(struct intel_atomic_state *);\n\tu8 (*calc_voltage_level)(int);\n};\n\nstruct intel_cdclk_state {\n\tstruct intel_global_state base;\n\tstruct intel_cdclk_config logical;\n\tstruct intel_cdclk_config actual;\n\tint dbuf_bw_min_cdclk;\n\tint min_cdclk[4];\n\tu8 min_voltage_level[4];\n\tenum pipe pipe;\n\tint force_min_cdclk;\n\tu8 enabled_pipes;\n\tu8 active_pipes;\n\tbool disable_pipes;\n};\n\nstruct intel_cdclk_vals {\n\tu32 cdclk;\n\tu16 refclk;\n\tu16 waveform;\n\tu8 ratio;\n};\n\nstruct intel_cmtg_config {\n\tbool cmtg_a_enable;\n\tbool cmtg_b_enable;\n\tbool trans_a_secondary;\n\tbool trans_b_secondary;\n};\n\nstruct intel_crtc;\n\nstruct intel_dsb;\n\nstruct intel_plane_state;\n\nstruct intel_color_funcs {\n\tint (*color_check)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*color_commit_noarm)(struct intel_dsb *, const struct intel_crtc_state *);\n\tvoid (*color_commit_arm)(struct intel_dsb *, const struct intel_crtc_state *);\n\tvoid (*color_post_update)(const struct intel_crtc_state *);\n\tvoid (*load_luts)(const struct intel_crtc_state *);\n\tvoid (*read_luts)(struct intel_crtc_state *);\n\tbool (*lut_equal)(const struct intel_crtc_state *, const struct drm_property_blob *, const struct drm_property_blob *, bool);\n\tvoid (*read_csc)(struct intel_crtc_state *);\n\tvoid (*get_config)(struct intel_crtc_state *);\n\tvoid (*load_plane_csc_matrix)(struct intel_dsb *, const struct intel_plane_state *);\n\tvoid (*load_plane_luts)(struct intel_dsb *, const struct intel_plane_state *);\n};\n\nstruct intel_colorop {\n\tstruct drm_colorop base;\n\tenum intel_color_block id;\n};\n\nstruct pwm_state {\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tbool usage_power;\n};\n\nstruct intel_pps_delays {\n\tu16 power_up;\n\tu16 backlight_on;\n\tu16 backlight_off;\n\tu16 power_down;\n\tu16 power_cycle;\n};\n\nstruct intel_vbt_panel_data {\n\tstruct drm_display_mode *lfp_vbt_mode;\n\tstruct drm_display_mode *sdvo_lvds_vbt_mode;\n\tint panel_type;\n\tunsigned int lvds_dither: 1;\n\tunsigned int bios_lvds_val;\n\tbool vrr;\n\tu8 seamless_drrs_min_refresh_rate;\n\tenum drrs_type drrs_type;\n\tstruct {\n\t\tint max_link_rate;\n\t\tint rate;\n\t\tint lanes;\n\t\tint preemphasis;\n\t\tint vswing;\n\t\tint bpp;\n\t\tstruct intel_pps_delays pps;\n\t\tu8 drrs_msa_timing_delay;\n\t\tbool low_vswing;\n\t\tbool hobl;\n\t\tbool dsc_disable;\n\t} edp;\n\tstruct {\n\t\tbool enable;\n\t\tbool full_link;\n\t\tbool require_aux_wakeup;\n\t\tint idle_frames;\n\t\tint tp1_wakeup_time_us;\n\t\tint tp2_tp3_wakeup_time_us;\n\t\tint psr2_tp2_tp3_wakeup_time_us;\n\t} psr;\n\tstruct {\n\t\tu16 pwm_freq_hz;\n\t\tu16 brightness_precision_bits;\n\t\tu16 hdr_dpcd_refresh_timeout;\n\t\tbool present;\n\t\tbool active_low_pwm;\n\t\tu8 min_brightness;\n\t\ts8 controller;\n\t\tenum intel_backlight_type type;\n\t} backlight;\n\tstruct {\n\t\tu16 panel_id;\n\t\tstruct mipi_config *config;\n\t\tstruct mipi_pps_data *pps;\n\t\tu16 bl_ports;\n\t\tu16 cabc_ports;\n\t\tu8 seq_version;\n\t\tu32 size;\n\t\tu8 *data;\n\t\tconst u8 *sequence[12];\n\t\tu8 *deassert_seq;\n\t\tenum drm_panel_orientation orientation;\n\t} dsi;\n};\n\nstruct pwm_device;\n\nstruct intel_panel_bl_funcs;\n\nstruct intel_connector;\n\nstruct intel_panel {\n\tstruct drm_panel *base;\n\tconst struct drm_edid *fixed_edid;\n\tstruct list_head fixed_modes;\n\tstruct {\n\t\tbool present;\n\t\tu32 level;\n\t\tu32 min;\n\t\tu32 max;\n\t\tbool enabled;\n\t\tbool combination_mode;\n\t\tbool active_low_pwm;\n\t\tbool alternate_pwm_increment;\n\t\tu32 pwm_level_min;\n\t\tu32 pwm_level_max;\n\t\tbool pwm_enabled;\n\t\tbool util_pin_active_low;\n\t\tu8 controller;\n\t\tstruct pwm_device *pwm;\n\t\tstruct pwm_state pwm_state;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct drm_edp_backlight_info info;\n\t\t\t\tbool luminance_control_support;\n\t\t\t} vesa;\n\t\t\tstruct {\n\t\t\t\tbool sdr_uses_aux;\n\t\t\t\tbool supports_2084_decode;\n\t\t\t\tbool supports_2020_gamut;\n\t\t\t\tbool supports_segmented_backlight;\n\t\t\t\tbool supports_sdp_colorimetry;\n\t\t\t\tbool supports_tone_mapping;\n\t\t\t} intel_cap;\n\t\t} edp;\n\t\tstruct backlight_device *device;\n\t\tconst struct intel_panel_bl_funcs *funcs;\n\t\tconst struct intel_panel_bl_funcs *pwm_funcs;\n\t\tvoid (*power)(struct intel_connector *, bool);\n\t} backlight;\n\tstruct intel_vbt_panel_data vbt;\n};\n\nstruct intel_hdcp_shim;\n\nstruct intel_hdcp {\n\tconst struct intel_hdcp_shim *shim;\n\tstruct mutex mutex;\n\tu64 value;\n\tstruct delayed_work check_work;\n\tstruct work_struct prop_work;\n\tbool hdcp_encrypted;\n\tbool hdcp2_supported;\n\tbool hdcp2_encrypted;\n\tu8 content_type;\n\tbool is_paired;\n\tbool is_repeater;\n\tu32 seq_num_v;\n\tu32 seq_num_m;\n\twait_queue_head_t cp_irq_queue;\n\tatomic_t cp_irq_count;\n\tint cp_irq_count_cached;\n\tenum transcoder cpu_transcoder;\n\tenum transcoder stream_transcoder;\n\tbool force_hdcp14;\n};\n\nstruct intel_dp;\n\nstruct intel_connector {\n\tstruct drm_connector base;\n\tstruct intel_encoder *encoder;\n\tu32 acpi_device_id;\n\tbool (*get_hw_state)(struct intel_connector *);\n\tvoid (*sync_state)(struct intel_connector *, const struct intel_crtc_state *);\n\tstruct intel_panel panel;\n\tconst struct drm_edid *detect_edid;\n\tint hotplug_retries;\n\tu8 polled;\n\tint force_joined_pipes;\n\tstruct {\n\t\tstruct drm_dp_aux *dsc_decompression_aux;\n\t\tu8 dsc_dpcd[16];\n\t\tu8 fec_capability;\n\t\tu8 dsc_hblank_expansion_quirk: 1;\n\t\tu8 dsc_throughput_quirk: 1;\n\t\tu8 dsc_decompression_enabled: 1;\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tint rgb_yuv444;\n\t\t\t\tint yuv422_420;\n\t\t\t} overall_throughput;\n\t\t\tint max_line_width;\n\t\t} dsc_branch_caps;\n\t\tstruct {\n\t\t\tu8 dpcd[7];\n\t\t\tbool support;\n\t\t\tbool su_support;\n\t\t\tenum intel_panel_replay_dsc_support dsc_support;\n\t\t\tu16 su_w_granularity;\n\t\t\tu16 su_y_granularity;\n\t\t} panel_replay_caps;\n\t\tstruct {\n\t\t\tu8 dpcd[2];\n\t\t\tbool support;\n\t\t\tbool su_support;\n\t\t\tu16 su_w_granularity;\n\t\t\tu16 su_y_granularity;\n\t\t\tu8 sync_latency;\n\t\t} psr_caps;\n\t} dp;\n\tstruct {\n\t\tstruct drm_dp_mst_port *port;\n\t\tstruct intel_dp *dp;\n\t} mst;\n\tstruct {\n\t\tint force_bpp_x16;\n\t} link;\n\tstruct work_struct modeset_retry_work;\n\tstruct intel_hdcp hdcp;\n};\n\nstruct intel_context_ops {\n\tlong unsigned int flags;\n\tint (*alloc)(struct intel_context *);\n\tvoid (*revoke)(struct intel_context *, struct i915_request *, unsigned int);\n\tvoid (*close)(struct intel_context *);\n\tint (*pre_pin)(struct intel_context *, struct i915_gem_ww_ctx *, void **);\n\tint (*pin)(struct intel_context *, void *);\n\tvoid (*unpin)(struct intel_context *);\n\tvoid (*post_unpin)(struct intel_context *);\n\tvoid (*cancel_request)(struct intel_context *, struct i915_request *);\n\tvoid (*enter)(struct intel_context *);\n\tvoid (*exit)(struct intel_context *);\n\tvoid (*sched_disable)(struct intel_context *);\n\tvoid (*update_stats)(struct intel_context *);\n\tvoid (*reset)(struct intel_context *);\n\tvoid (*destroy)(struct kref *);\n\tstruct intel_context * (*create_virtual)(struct intel_engine_cs **, unsigned int, long unsigned int);\n\tstruct intel_context * (*create_parallel)(struct intel_engine_cs **, unsigned int, unsigned int);\n\tstruct intel_engine_cs * (*get_sibling)(struct intel_engine_cs *, unsigned int);\n};\n\nstruct intel_ddi_buf_trans;\n\nstruct intel_encoder {\n\tstruct drm_encoder base;\n\tenum intel_output_type type;\n\tenum port port;\n\tu16 cloneable;\n\tu8 pipe_mask;\n\tstruct delayed_work link_check_work;\n\tvoid (*link_check)(struct intel_encoder *);\n\tenum intel_hotplug_state (*hotplug)(struct intel_encoder *, struct intel_connector *);\n\tenum intel_output_type (*compute_output_type)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tint (*compute_config)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tint (*compute_config_late)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tvoid (*pre_pll_enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*pre_enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*post_disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*post_pll_disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*update_pipe)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_enable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_disable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tbool (*get_hw_state)(struct intel_encoder *, enum pipe *);\n\tvoid (*get_config)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*sync_state)(struct intel_encoder *, const struct intel_crtc_state *);\n\tbool (*initial_fastset_check)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*get_power_domains)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*suspend)(struct intel_encoder *);\n\tvoid (*suspend_complete)(struct intel_encoder *);\n\tvoid (*shutdown)(struct intel_encoder *);\n\tvoid (*shutdown_complete)(struct intel_encoder *);\n\tvoid (*enable_clock)(struct intel_encoder *, const struct intel_crtc_state *);\n\tvoid (*disable_clock)(struct intel_encoder *);\n\tbool (*is_clock_enabled)(struct intel_encoder *);\n\tenum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *, const struct intel_crtc_state *);\n\tconst struct intel_ddi_buf_trans * (*get_buf_trans)(struct intel_encoder *, const struct intel_crtc_state *, int *);\n\tvoid (*set_signal_levels)(struct intel_encoder *, const struct intel_crtc_state *);\n\tenum hpd_pin hpd_pin;\n\tenum intel_display_power_domain power_domain;\n\tconst struct intel_bios_encoder_data *devdata;\n};\n\nstruct intel_crt {\n\tstruct intel_encoder base;\n\tbool force_hotplug_required;\n\ti915_reg_t adpa_reg;\n};\n\nstruct intel_display_power_domain_set {\n\tstruct intel_power_domain_mask mask;\n};\n\nstruct intel_flipq {\n\tu32 start_mmioaddr;\n\tenum intel_flipq_id flipq_id;\n\tu8 tail;\n};\n\nstruct intel_wm_level {\n\tbool enable;\n\tu32 pri_val;\n\tu32 spr_val;\n\tu32 cur_val;\n\tu32 fbc_val;\n};\n\nstruct intel_pipe_wm {\n\tstruct intel_wm_level wm[5];\n\tbool fbc_wm_enabled;\n\tbool pipe_enabled;\n\tbool sprites_enabled;\n\tbool sprites_scaled;\n};\n\nstruct vlv_wm_state {\n\tstruct g4x_pipe_wm wm[3];\n\tstruct g4x_sr_wm sr[3];\n\tu8 num_levels;\n\tbool cxsr;\n};\n\nstruct intel_link_m_n {\n\tu32 tu;\n\tu32 data_m;\n\tu32 data_n;\n\tu32 link_m;\n\tu32 link_n;\n};\n\nstruct intel_pipe_crc {\n\tspinlock_t lock;\n\tint skipped;\n\tenum intel_pipe_crc_source source;\n};\n\nstruct intel_overlay;\n\nstruct intel_crtc {\n\tstruct drm_crtc base;\n\tenum pipe pipe;\n\tbool active;\n\tu8 plane_ids_mask;\n\tu8 mode_flags;\n\tu16 vmax_vblank_start;\n\tstruct intel_display_power_domain_set enabled_power_domains;\n\tstruct intel_display_power_domain_set hw_readout_power_domains;\n\tstruct intel_overlay *overlay;\n\tstruct intel_crtc_state *config;\n\tstruct drm_pending_vblank_event *flip_done_event;\n\tstruct drm_pending_vblank_event *dsb_event;\n\tstruct drm_pending_vblank_event *flipq_event;\n\tbool cpu_fifo_underrun_disabled;\n\tbool pch_fifo_underrun_disabled;\n\tstruct intel_flipq flipq[5];\n\tstruct {\n\t\tunion {\n\t\t\tstruct intel_pipe_wm ilk;\n\t\t\tstruct vlv_wm_state vlv;\n\t\t\tstruct g4x_wm_state g4x;\n\t\t} active;\n\t} wm;\n\tstruct {\n\t\tstruct mutex mutex;\n\t\tstruct delayed_work work;\n\t\tenum drrs_refresh_rate refresh_rate;\n\t\tunsigned int frontbuffer_bits;\n\t\tunsigned int busy_frontbuffer_bits;\n\t\tenum transcoder cpu_transcoder;\n\t\tstruct intel_link_m_n m_n;\n\t\tstruct intel_link_m_n m2_n2;\n\t} drrs;\n\tstruct {\n\t\tu64 flip_count;\n\t} dc_balance;\n\tint scanline_offset;\n\tstruct {\n\t\tunsigned int start_vbl_count;\n\t\tktime_t start_vbl_time;\n\t\tint min_vbl;\n\t\tint max_vbl;\n\t\tint scanline_start;\n\t} debug;\n\tint num_scalers;\n\tstruct pm_qos_request vblank_pm_qos;\n\tstruct intel_pipe_crc pipe_crc;\n\tbool vblank_psr_notify;\n};\n\nstruct intel_scaler {\n\tu32 mode;\n\tbool in_use;\n\tint hscale;\n\tint vscale;\n};\n\nstruct intel_crtc_scaler_state {\n\tstruct intel_scaler scalers[2];\n\tunsigned int scaler_users;\n\tint scaler_id;\n};\n\nstruct intel_csc_matrix {\n\tu16 coeff[9];\n\tu16 preoff[3];\n\tu16 postoff[3];\n};\n\nstruct skl_wm_level {\n\tu16 min_ddb_alloc;\n\tu16 blocks;\n\tu8 lines;\n\tbool enable;\n\tbool ignore_lines;\n\tbool auto_min_alloc_wm_enable;\n\tbool can_sagv;\n};\n\nstruct skl_plane_wm {\n\tstruct skl_wm_level wm[8];\n\tstruct skl_wm_level uv_wm[8];\n\tstruct skl_wm_level trans_wm;\n\tstruct {\n\t\tstruct skl_wm_level wm0;\n\t\tstruct skl_wm_level trans_wm;\n\t} sagv;\n\tbool is_planar;\n};\n\nstruct skl_pipe_wm {\n\tstruct skl_plane_wm planes[8];\n\tbool use_sagv_wm;\n};\n\nstruct skl_ddb_entry {\n\tu16 start;\n\tu16 end;\n};\n\nstruct vlv_fifo_state {\n\tu16 plane[8];\n};\n\nstruct intel_crtc_wm_state {\n\tunion {\n\t\tstruct {\n\t\t\tstruct intel_pipe_wm intermediate;\n\t\t\tstruct intel_pipe_wm optimal;\n\t\t} ilk;\n\t\tstruct {\n\t\t\tstruct skl_pipe_wm raw;\n\t\t\tstruct skl_pipe_wm optimal;\n\t\t\tstruct skl_ddb_entry ddb;\n\t\t\tstruct skl_ddb_entry plane_ddb[8];\n\t\t\tstruct skl_ddb_entry plane_ddb_y[8];\n\t\t\tu16 plane_min_ddb[8];\n\t\t\tu16 plane_interim_ddb[8];\n\t\t} skl;\n\t\tstruct {\n\t\t\tstruct g4x_pipe_wm raw[3];\n\t\t\tstruct vlv_wm_state intermediate;\n\t\t\tstruct vlv_wm_state optimal;\n\t\t\tstruct vlv_fifo_state fifo_state;\n\t\t} vlv;\n\t\tstruct {\n\t\t\tstruct g4x_pipe_wm raw[3];\n\t\t\tstruct g4x_wm_state intermediate;\n\t\t\tstruct g4x_wm_state optimal;\n\t\t} g4x;\n\t};\n\tbool need_postvbl_update;\n};\n\nstruct intel_crtc_state {\n\tstruct drm_crtc_state uapi;\n\tstruct {\n\t\tbool active;\n\t\tbool enable;\n\t\tstruct drm_property_blob *degamma_lut;\n\t\tstruct drm_property_blob *gamma_lut;\n\t\tstruct drm_property_blob *ctm;\n\t\tstruct drm_display_mode mode;\n\t\tstruct drm_display_mode pipe_mode;\n\t\tstruct drm_display_mode adjusted_mode;\n\t\tenum drm_scaling_filter scaling_filter;\n\t\tstruct intel_casf casf_params;\n\t} hw;\n\tstruct drm_property_blob *pre_csc_lut;\n\tstruct drm_property_blob *post_csc_lut;\n\tstruct intel_csc_matrix csc;\n\tstruct intel_csc_matrix output_csc;\n\tlong unsigned int quirks;\n\tunsigned int fb_bits;\n\tbool update_pipe;\n\tbool update_m_n;\n\tbool update_lrr;\n\tbool disable_cxsr;\n\tbool update_wm_pre;\n\tbool update_wm_post;\n\tbool fifo_changed;\n\tbool preload_luts;\n\tbool inherited;\n\tbool do_async_flip;\n\tstruct drm_rect pipe_src;\n\tunsigned int pixel_rate;\n\tbool has_pch_encoder;\n\tbool has_infoframe;\n\tenum transcoder cpu_transcoder;\n\tbool limited_color_range;\n\tunsigned int output_types;\n\tbool has_hdmi_sink;\n\tbool has_audio;\n\tbool dither;\n\tbool dither_force_disable;\n\tbool clock_set;\n\tbool sdvo_tv_clock;\n\tbool bw_constrained;\n\tstruct dpll dpll;\n\tstruct intel_dpll *intel_dpll;\n\tstruct intel_dpll_hw_state dpll_hw_state;\n\tstruct icl_port_dpll icl_port_dplls[2];\n\tstruct {\n\t\tu32 ctrl;\n\t\tu32 div;\n\t} dsi_pll;\n\tint max_link_bpp_x16;\n\tint pipe_bpp;\n\tint min_hblank;\n\tstruct intel_link_m_n dp_m_n;\n\tstruct intel_link_m_n dp_m2_n2;\n\tbool has_drrs;\n\tbool has_psr;\n\tbool has_sel_update;\n\tbool enable_psr2_sel_fetch;\n\tbool enable_psr2_su_region_et;\n\tbool req_psr2_sdp_prior_scanline;\n\tbool has_panel_replay;\n\tbool link_off_after_as_sdp_when_pr_active;\n\tbool disable_as_sdp_when_pr_active;\n\tbool wm_level_disabled;\n\tbool pkg_c_latency_used;\n\tenum intel_panel_replay_dsc_support panel_replay_dsc_support;\n\tu32 dc3co_exitline;\n\tu16 su_y_granularity;\n\tu8 active_non_psr_pipes;\n\tconst char *no_psr_reason;\n\tint port_clock;\n\tunsigned int pixel_multiplier;\n\tu8 mode_flags;\n\tu8 lane_count;\n\tu8 lane_lat_optim_mask;\n\tu8 min_voltage_level;\n\tstruct {\n\t\tu32 control;\n\t\tu32 pgm_ratios;\n\t\tu32 lvds_border_bits;\n\t} gmch_pfit;\n\tstruct {\n\t\tstruct drm_rect dst;\n\t\tbool enabled;\n\t\tbool force_thru;\n\t} pch_pfit;\n\tint fdi_lanes;\n\tstruct intel_link_m_n fdi_m_n;\n\tbool ips_enabled;\n\tbool crc_enabled;\n\tbool double_wide;\n\tstruct intel_crtc_scaler_state scaler_state;\n\tenum pipe hsw_workaround_pipe;\n\tstruct intel_crtc_wm_state wm;\n\tint min_cdclk;\n\tint plane_min_cdclk[8];\n\tu32 data_rate[8];\n\tu32 data_rate_y[8];\n\tu64 rel_data_rate[8];\n\tu64 rel_data_rate_y[8];\n\tu32 gamma_mode;\n\tunion {\n\t\tu32 csc_mode;\n\t\tu32 cgm_mode;\n\t};\n\tu8 enabled_planes;\n\tu8 active_planes;\n\tu8 scaled_planes;\n\tu8 nv12_planes;\n\tu8 c8_planes;\n\tu8 update_planes;\n\tu8 async_flip_planes;\n\tu8 framestart_delay;\n\tu8 msa_timing_delay;\n\tstruct {\n\t\tu32 enable;\n\t\tu32 gcp;\n\t\tunion hdmi_infoframe avi;\n\t\tunion hdmi_infoframe spd;\n\t\tunion hdmi_infoframe hdmi;\n\t\tunion hdmi_infoframe drm;\n\t\tstruct drm_dp_vsc_sdp vsc;\n\t\tstruct drm_dp_as_sdp as_sdp;\n\t} infoframes;\n\tu8 eld[128];\n\tbool hdmi_scrambling;\n\tbool hdmi_high_tmds_clock_ratio;\n\tenum intel_output_format output_format;\n\tenum intel_output_format sink_format;\n\tbool gamma_enable;\n\tbool csc_enable;\n\tbool wgc_enable;\n\tu8 joiner_pipes;\n\tstruct {\n\t\tbool compression_enabled_on_link;\n\t\tbool compression_enable;\n\t\tint num_streams;\n\t\tu16 compressed_bpp_x16;\n\t\tu8 slice_count;\n\t\tstruct drm_dsc_config config;\n\t} dsc;\n\tstruct drm_dp_tunnel_ref dp_tunnel_ref;\n\tu16 linetime;\n\tu16 ips_linetime;\n\tbool enhanced_framing;\n\tbool fec_enable;\n\tbool sdp_split_enable;\n\tenum transcoder master_transcoder;\n\tu8 sync_mode_slaves_mask;\n\tenum transcoder mst_master_transcoder;\n\tstruct intel_dsb *dsb_color;\n\tstruct intel_dsb *dsb_commit;\n\tbool use_dsb;\n\tbool use_flipq;\n\tu32 psr2_man_track_ctl;\n\tu32 pipe_srcsz_early_tpt;\n\tstruct drm_rect psr2_su_area;\n\tstruct {\n\t\tbool enable;\n\t\tbool in_range;\n\t\tu8 pipeline_full;\n\t\tu16 flipline;\n\t\tu16 vmin;\n\t\tu16 vmax;\n\t\tu16 guardband;\n\t\tu32 vsync_end;\n\t\tu32 vsync_start;\n\t\tstruct {\n\t\t\tbool enable;\n\t\t\tu16 vmin;\n\t\t\tu16 vmax;\n\t\t\tu16 guardband;\n\t\t\tu16 slope;\n\t\t\tu16 max_increase;\n\t\t\tu16 max_decrease;\n\t\t\tu16 vblank_target;\n\t\t} dc_balance;\n\t} vrr;\n\tstruct {\n\t\tbool enable;\n\t\tu64 cmrr_n;\n\t\tu64 cmrr_m;\n\t} cmrr;\n\tstruct {\n\t\tbool enable;\n\t\tu8 link_count;\n\t\tu8 pixel_overlap;\n\t} splitter;\n\tstruct drm_vblank_work vblank_work;\n\tbool has_lobf;\n\tu16 set_context_latency;\n\tstruct {\n\t\tu8 io_wake_lines;\n\t\tu8 fast_wake_lines;\n\t\tu8 check_entry_lines;\n\t\tu8 aux_less_wake_lines;\n\t\tu8 silence_period_sym_clocks;\n\t\tu8 lfps_half_cycle_num_of_syms;\n\t} alpm_state;\n\tbool plane_color_changed;\n};\n\nstruct intel_css_header {\n\tu32 module_type;\n\tu32 header_len;\n\tu32 header_ver;\n\tu32 module_id;\n\tu32 module_vendor;\n\tu32 date;\n\tu32 size;\n\tu32 key_size;\n\tu32 modulus_size;\n\tu32 exponent_size;\n\tu32 reserved1[12];\n\tu32 version;\n\tu32 reserved2[8];\n\tu32 kernel_header_info;\n};\n\nstruct intel_dbuf_bw {\n\tunsigned int max_bw[4];\n\tu8 active_planes[4];\n};\n\nstruct intel_dbuf_bw_state {\n\tstruct intel_global_state base;\n\tstruct intel_dbuf_bw dbuf_bw[4];\n};\n\nstruct intel_dbuf_state {\n\tstruct intel_global_state base;\n\tstruct skl_ddb_entry ddb[4];\n\tunsigned int weight[4];\n\tu8 slices[4];\n\tu8 enabled_slices;\n\tu8 active_pipes;\n\tu8 mdclk_cdclk_ratio;\n\tbool joined_mbus;\n};\n\nunion intel_ddi_buf_trans_entry;\n\nstruct intel_ddi_buf_trans {\n\tconst union intel_ddi_buf_trans_entry *entries;\n\tu8 num_entries;\n\tu8 hdmi_default_entry;\n};\n\nstruct tgl_dkl_phy_ddi_buf_trans {\n\tu8 vswing;\n\tu8 preshoot;\n\tu8 de_emphasis;\n};\n\nstruct xe3plpd_lt_phy_buf_trans {\n\tu8 txswing;\n\tu8 txswing_level;\n\tu8 pre_cursor;\n\tu8 main_cursor;\n\tu8 post_cursor;\n};\n\nunion intel_ddi_buf_trans_entry {\n\tstruct hsw_ddi_buf_trans hsw;\n\tstruct bxt_ddi_buf_trans bxt;\n\tstruct icl_ddi_buf_trans icl;\n\tstruct icl_mg_phy_ddi_buf_trans mg;\n\tstruct tgl_dkl_phy_ddi_buf_trans dkl;\n\tstruct dg2_snps_phy_buf_trans snps;\n\tstruct xe3plpd_lt_phy_buf_trans lt;\n};\n\nstruct intel_ddi_port_domains {\n\tenum port port_start;\n\tenum port port_end;\n\tenum aux_ch aux_ch_start;\n\tenum aux_ch aux_ch_end;\n\tenum intel_display_power_domain ddi_lanes;\n\tenum intel_display_power_domain ddi_io;\n\tenum intel_display_power_domain aux_io;\n\tenum intel_display_power_domain aux_legacy_usbc;\n\tenum intel_display_power_domain aux_tbt;\n};\n\nstruct intel_digital_connector_state {\n\tstruct drm_connector_state base;\n\tenum hdmi_force_audio force_audio;\n\tint broadcast_rgb;\n};\n\nstruct intel_dp_link_config {\n\tu8 link_rate_idx: 6;\n\tu8 lane_count_exp: 2;\n};\n\nstruct intel_pps {\n\tint panel_power_up_delay;\n\tint panel_power_down_delay;\n\tint panel_power_cycle_delay;\n\tint backlight_on_delay;\n\tint backlight_off_delay;\n\tstruct delayed_work panel_vdd_work;\n\tbool want_panel_vdd;\n\tbool initializing;\n\tlong unsigned int last_power_on;\n\tlong unsigned int last_backlight_off;\n\tktime_t panel_power_off_time;\n\tstruct ref_tracker *vdd_wakeref;\n\tunion {\n\t\tenum pipe vlv_pps_pipe;\n\t\tint pps_idx;\n\t};\n\tenum pipe vlv_active_pipe;\n\tbool bxt_pps_reset;\n\tstruct intel_pps_delays pps_delays;\n\tstruct intel_pps_delays bios_pps_delays;\n};\n\nstruct intel_dp_compliance_data {\n\tlong unsigned int edid;\n\tu8 video_pattern;\n\tu16 hdisplay;\n\tu16 vdisplay;\n\tu8 bpc;\n\tstruct drm_dp_phy_test_params phytest;\n};\n\nstruct intel_dp_compliance {\n\tlong unsigned int test_type;\n\tstruct intel_dp_compliance_data test_data;\n\tbool test_active;\n\tint test_link_rate;\n\tu8 test_lane_count;\n};\n\nstruct intel_dp_pcon_frl {\n\tbool is_trained;\n\tint trained_rate_gbps;\n};\n\nstruct intel_psr {\n\tstruct mutex lock;\n\tu32 debug;\n\tbool sink_support;\n\tbool source_support;\n\tbool enabled;\n\tint pause_counter;\n\tenum pipe pipe;\n\tenum transcoder transcoder;\n\tbool active;\n\tstruct work_struct work;\n\tunsigned int busy_frontbuffer_bits;\n\tbool link_standby;\n\tbool sel_update_enabled;\n\tbool psr2_sel_fetch_enabled;\n\tbool psr2_sel_fetch_cff_enabled;\n\tbool su_region_et_enabled;\n\tbool req_psr2_sdp_prior_scanline;\n\tktime_t last_entry_attempt;\n\tktime_t last_exit;\n\tbool sink_not_reliable;\n\tbool irq_aux_error;\n\tu16 su_w_granularity;\n\tu16 su_y_granularity;\n\tbool source_panel_replay_support;\n\tbool sink_panel_replay_support;\n\tbool panel_replay_enabled;\n\tu32 dc3co_exitline;\n\tu32 dc3co_exit_delay;\n\tstruct delayed_work dc3co_work;\n\tu8 entry_setup_frames;\n\tu8 io_wake_lines;\n\tu8 fast_wake_lines;\n\tbool link_ok;\n\tbool pkg_c_latency_used;\n\tu8 active_non_psr_pipes;\n\tconst char *no_psr_reason;\n};\n\nstruct intel_dp_mst_encoder;\n\nstruct intel_dp {\n\ti915_reg_t output_reg;\n\tu32 DP;\n\tint link_rate;\n\tu8 lane_count;\n\tu8 sink_count;\n\tbool needs_modeset_retry;\n\tbool use_max_params;\n\tu8 dpcd[15];\n\tu8 downstream_ports[16];\n\tu8 edp_dpcd[5];\n\tu8 lttpr_common_caps[8];\n\tu8 lttpr_phy_caps[24];\n\tu8 pcon_dsc_dpcd[13];\n\tint num_source_rates;\n\tconst int *source_rates;\n\tint num_sink_rates;\n\tint sink_rates[8];\n\tbool use_rate_select;\n\tint max_sink_lane_count;\n\tint num_common_rates;\n\tint common_rates[8];\n\tstruct {\n\t\tbool active;\n\t\tint num_configs;\n\t\tstruct intel_dp_link_config configs[24];\n\t\tint max_lane_count;\n\t\tint max_rate;\n\t\tint mst_probed_lane_count;\n\t\tint mst_probed_rate;\n\t\tint force_lane_count;\n\t\tint force_rate;\n\t\tbool retrain_disabled;\n\t\tint seq_train_failures;\n\t\tint force_train_failure;\n\t\tbool force_retrain;\n\t} link;\n\tbool reset_link_params;\n\tint mso_link_count;\n\tint mso_pixel_overlap;\n\tstruct drm_dp_desc desc;\n\tstruct drm_dp_aux aux;\n\tu32 aux_busy_last_status;\n\tu8 train_set[4];\n\tstruct intel_pps pps;\n\tbool is_mst;\n\tenum drm_dp_mst_mode mst_detect;\n\tstruct intel_connector *attached_connector;\n\tbool as_sdp_supported;\n\tstruct drm_dp_tunnel *tunnel;\n\tbool tunnel_suspended: 1;\n\tstruct {\n\t\tstruct intel_dp_mst_encoder *stream_encoders[4];\n\t\tstruct drm_dp_mst_topology_mgr mgr;\n\t\tint active_streams;\n\t} mst;\n\tu32 (*get_aux_clock_divider)(struct intel_dp *, int);\n\tu32 (*get_aux_send_ctl)(struct intel_dp *, int, u32);\n\ti915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *);\n\ti915_reg_t (*aux_ch_data_reg)(struct intel_dp *, int);\n\tvoid (*prepare_link_retrain)(struct intel_dp *, const struct intel_crtc_state *);\n\tvoid (*set_link_train)(struct intel_dp *, const struct intel_crtc_state *, u8);\n\tvoid (*set_idle_link_train)(struct intel_dp *, const struct intel_crtc_state *);\n\tu8 (*preemph_max)(struct intel_dp *);\n\tu8 (*voltage_max)(struct intel_dp *, const struct intel_crtc_state *);\n\tstruct intel_dp_compliance compliance;\n\tstruct {\n\t\tint min_tmds_clock;\n\t\tint max_tmds_clock;\n\t\tint max_dotclock;\n\t\tint pcon_max_frl_bw;\n\t\tu8 max_bpc;\n\t\tbool ycbcr_444_to_420;\n\t\tbool ycbcr420_passthrough;\n\t\tbool rgb_to_ycbcr;\n\t} dfp;\n\tstruct pm_qos_request pm_qos;\n\tbool force_dsc_en;\n\tint force_dsc_output_format;\n\tbool force_dsc_fractional_bpp_en;\n\tint force_dsc_bpc;\n\tbool hobl_failed;\n\tbool hobl_active;\n\tstruct intel_dp_pcon_frl frl;\n\tstruct intel_psr psr;\n\tlong unsigned int last_oui_write;\n\tbool oui_valid;\n\tbool colorimetry_support;\n\tstruct {\n\t\tenum transcoder transcoder;\n\t\tstruct mutex lock;\n\t\tbool lobf_disable_debug;\n\t\tbool sink_alpm_error;\n\t} alpm;\n\tu8 alpm_dpcd;\n\tstruct {\n\t\tlong unsigned int mask;\n\t} quirks;\n};\n\nstruct cec_notifier;\n\nstruct intel_hdmi {\n\ti915_reg_t hdmi_reg;\n\tstruct {\n\t\tenum drm_dp_dual_mode_type type;\n\t\tint max_tmds_clock;\n\t} dp_dual_mode;\n\tstruct intel_connector *attached_connector;\n\tstruct cec_notifier *cec_notifier;\n};\n\nstruct intel_lspcon {\n\tbool active;\n\tbool hdr_supported;\n\tenum drm_lspcon_mode mode;\n\tenum lspcon_vendor vendor;\n};\n\nstruct intel_tc_port;\n\nstruct intel_digital_port {\n\tstruct intel_encoder base;\n\tstruct intel_dp dp;\n\tstruct intel_hdmi hdmi;\n\tstruct intel_lspcon lspcon;\n\tenum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);\n\tbool lane_reversal;\n\tbool ddi_a_4_lanes;\n\tbool release_cl2_override;\n\tbool dedicated_external;\n\tu8 max_lanes;\n\tenum aux_ch aux_ch;\n\tenum intel_display_power_domain ddi_io_power_domain;\n\tstruct ref_tracker *ddi_io_wakeref;\n\tstruct ref_tracker *aux_wakeref;\n\tstruct intel_tc_port *tc;\n\tstruct {\n\t\tstruct mutex mutex;\n\t\tunsigned int num_streams;\n\t\tbool auth_status;\n\t\tstruct hdcp_port_data port_data;\n\t\tbool mst_type1_capable;\n\t} hdcp;\n\tvoid (*write_infoframe)(struct intel_encoder *, const struct intel_crtc_state *, unsigned int, const void *, ssize_t);\n\tvoid (*read_infoframe)(struct intel_encoder *, const struct intel_crtc_state *, unsigned int, void *, ssize_t);\n\tvoid (*set_infoframes)(struct intel_encoder *, bool, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tu32 (*infoframes_enabled)(struct intel_encoder *, const struct intel_crtc_state *);\n\tbool (*connected)(struct intel_encoder *);\n\tvoid (*lock)(struct intel_digital_port *);\n\tvoid (*unlock)(struct intel_digital_port *);\n};\n\nstruct intel_display_platforms {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int g4x: 1;\n\t\t\tlong unsigned int mobile: 1;\n\t\t\tlong unsigned int dgfx: 1;\n\t\t\tlong unsigned int i830: 1;\n\t\t\tlong unsigned int i845g: 1;\n\t\t\tlong unsigned int i85x: 1;\n\t\t\tlong unsigned int i865g: 1;\n\t\t\tlong unsigned int i915g: 1;\n\t\t\tlong unsigned int i915gm: 1;\n\t\t\tlong unsigned int i945g: 1;\n\t\t\tlong unsigned int i945gm: 1;\n\t\t\tlong unsigned int g33: 1;\n\t\t\tlong unsigned int pineview: 1;\n\t\t\tlong unsigned int i965g: 1;\n\t\t\tlong unsigned int i965gm: 1;\n\t\t\tlong unsigned int g45: 1;\n\t\t\tlong unsigned int gm45: 1;\n\t\t\tlong unsigned int ironlake: 1;\n\t\t\tlong unsigned int sandybridge: 1;\n\t\t\tlong unsigned int ivybridge: 1;\n\t\t\tlong unsigned int valleyview: 1;\n\t\t\tlong unsigned int haswell: 1;\n\t\t\tlong unsigned int haswell_ult: 1;\n\t\t\tlong unsigned int haswell_ulx: 1;\n\t\t\tlong unsigned int broadwell: 1;\n\t\t\tlong unsigned int broadwell_ult: 1;\n\t\t\tlong unsigned int broadwell_ulx: 1;\n\t\t\tlong unsigned int cherryview: 1;\n\t\t\tlong unsigned int skylake: 1;\n\t\t\tlong unsigned int skylake_ult: 1;\n\t\t\tlong unsigned int skylake_ulx: 1;\n\t\t\tlong unsigned int broxton: 1;\n\t\t\tlong unsigned int kabylake: 1;\n\t\t\tlong unsigned int kabylake_ult: 1;\n\t\t\tlong unsigned int kabylake_ulx: 1;\n\t\t\tlong unsigned int geminilake: 1;\n\t\t\tlong unsigned int coffeelake: 1;\n\t\t\tlong unsigned int coffeelake_ult: 1;\n\t\t\tlong unsigned int coffeelake_ulx: 1;\n\t\t\tlong unsigned int cometlake: 1;\n\t\t\tlong unsigned int cometlake_ult: 1;\n\t\t\tlong unsigned int cometlake_ulx: 1;\n\t\t\tlong unsigned int icelake: 1;\n\t\t\tlong unsigned int icelake_port_f: 1;\n\t\t\tlong unsigned int jasperlake: 1;\n\t\t\tlong unsigned int elkhartlake: 1;\n\t\t\tlong unsigned int tigerlake: 1;\n\t\t\tlong unsigned int tigerlake_uy: 1;\n\t\t\tlong unsigned int rocketlake: 1;\n\t\t\tlong unsigned int dg1: 1;\n\t\t\tlong unsigned int alderlake_s: 1;\n\t\t\tlong unsigned int alderlake_s_raptorlake_s: 1;\n\t\t\tlong unsigned int alderlake_p: 1;\n\t\t\tlong unsigned int alderlake_p_alderlake_n: 1;\n\t\t\tlong unsigned int alderlake_p_raptorlake_p: 1;\n\t\t\tlong unsigned int alderlake_p_raptorlake_u: 1;\n\t\t\tlong unsigned int dg2: 1;\n\t\t\tlong unsigned int dg2_g10: 1;\n\t\t\tlong unsigned int dg2_g11: 1;\n\t\t\tlong unsigned int dg2_g12: 1;\n\t\t\tlong unsigned int meteorlake: 1;\n\t\t\tlong unsigned int meteorlake_u: 1;\n\t\t\tlong unsigned int lunarlake: 1;\n\t\t\tlong unsigned int battlemage: 1;\n\t\t\tlong unsigned int pantherlake: 1;\n\t\t\tlong unsigned int pantherlake_wildcatlake: 1;\n\t\t\tlong unsigned int novalake: 1;\n\t\t};\n\t\tlong unsigned int bitmap[2];\n\t};\n};\n\nstruct intel_global_state_funcs;\n\nstruct intel_global_obj {\n\tstruct list_head head;\n\tstruct intel_global_state *state;\n\tconst struct intel_global_state_funcs *funcs;\n};\n\nstruct sys_cache_cfg {\n\tstruct mutex lock;\n\tenum intel_fbc_id id;\n};\n\nstruct intel_fbdev;\n\nstruct intel_display_ip_ver {\n\tu16 ver;\n\tu16 rel;\n\tu16 step;\n};\n\nstruct intel_display_runtime_info {\n\tstruct intel_display_ip_ver ip;\n\tint step;\n\tu32 rawclk_freq;\n\tu8 pipe_mask;\n\tu8 cpu_transcoder_mask;\n\tu16 port_mask;\n\tu8 num_sprites[4];\n\tu8 num_scalers[4];\n\tu8 fbc_mask;\n\tbool has_hdcp;\n\tbool has_dmc;\n\tbool has_dsc;\n\tbool edp_typec_support;\n\tbool has_dbuf_overlap_detection;\n};\n\nstruct drm_dp_tunnel_mgr;\n\nstruct intel_dpll {\n\tstruct intel_dpll_state state;\n\tu8 index;\n\tu8 active_mask;\n\tbool on;\n\tconst struct dpll_info *info;\n\tstruct ref_tracker *wakeref;\n};\n\nstruct intel_dpll_mgr;\n\nstruct intel_dpll_global {\n\tstruct mutex lock;\n\tint num_dpll;\n\tstruct intel_dpll dplls[9];\n\tconst struct intel_dpll_mgr *mgr;\n\tstruct {\n\t\tint nssc;\n\t\tint ssc;\n\t} ref_clks;\n\tu8 pch_ssc_use;\n};\n\nstruct intel_frontbuffer_tracking {\n\tspinlock_t lock;\n\tunsigned int busy_bits;\n};\n\nstruct intel_hotplug {\n\tstruct delayed_work hotplug_work;\n\tconst u32 *hpd;\n\tconst u32 *pch_hpd;\n\tstruct {\n\t\tlong unsigned int last_jiffies;\n\t\tint count;\n\t\tint blocked_count;\n\t\tenum {\n\t\t\tHPD_ENABLED = 0,\n\t\t\tHPD_DISABLED = 1,\n\t\t\tHPD_MARK_DISABLED = 2,\n\t\t} state;\n\t} stats[15];\n\tu32 event_bits;\n\tu32 retry_bits;\n\tstruct delayed_work reenable_work;\n\tu32 long_hpd_pin_mask;\n\tu32 short_hpd_pin_mask;\n\tstruct work_struct dig_port_work;\n\tstruct work_struct poll_init_work;\n\tbool poll_enabled;\n\tbool detection_work_enabled;\n\tunsigned int hpd_storm_threshold;\n\tu8 hpd_short_storm_enabled;\n\tlong unsigned int oob_hotplug_last_state;\n\tstruct workqueue_struct *dp_wq;\n\tbool ignore_long_hpd;\n};\n\nstruct intel_display_params {\n\tchar *dmc_firmware_path;\n\tchar *vbt_firmware;\n\tint lvds_channel_mode;\n\tint panel_use_ssc;\n\tint vbt_sdvo_panel_type;\n\tint enable_dc;\n\tbool enable_dpt;\n\tbool enable_dsb;\n\tbool enable_flipq;\n\tbool enable_sagv;\n\tint disable_power_well;\n\tbool enable_ips;\n\tint invert_brightness;\n\tint edp_vswing;\n\tint enable_dpcd_backlight;\n\tbool load_detect_test;\n\tbool force_reset_modeset_test;\n\tbool disable_display;\n\tbool verbose_state_checks;\n\tbool nuclear_pageflip;\n\tbool enable_dp_mst;\n\tint enable_fbc;\n\tint enable_psr;\n\tint enable_panel_replay;\n\tbool psr_safest_params;\n\tbool enable_psr2_sel_fetch;\n\tint enable_dmc_wl;\n};\n\nstruct sdvo_device_mapping {\n\tu8 initialized;\n\tu8 dvo_port;\n\tu8 target_addr;\n\tu8 dvo_wiring;\n\tu8 i2c_pin;\n\tu8 ddc_pin;\n};\n\nstruct intel_vbt_data {\n\tu16 version;\n\tunsigned int int_tv_support: 1;\n\tunsigned int int_crt_support: 1;\n\tunsigned int lvds_use_ssc: 1;\n\tunsigned int int_lvds_support: 1;\n\tunsigned int display_clock_mode: 1;\n\tunsigned int fdi_rx_polarity_inverted: 1;\n\tint lvds_ssc_freq;\n\tenum drm_panel_orientation orientation;\n\tbool override_afc_startup;\n\tu8 override_afc_startup_val;\n\tint crt_ddc_pin;\n\tstruct list_head display_devices;\n\tstruct list_head bdb_blocks;\n\tstruct sdvo_device_mapping sdvo_mappings[2];\n};\n\nstruct intel_dmc_wl {\n\tspinlock_t lock;\n\tbool enabled;\n\tbool taken;\n\trefcount_t refcount;\n\tu32 dc_state;\n\tstruct delayed_work work;\n};\n\nstruct vlv_wm_ddl_values {\n\tu8 plane[8];\n};\n\nstruct vlv_wm_values {\n\tstruct g4x_pipe_wm pipe[3];\n\tstruct g4x_sr_wm sr;\n\tstruct vlv_wm_ddl_values ddl[3];\n\tu8 level;\n\tbool cxsr;\n};\n\nstruct intel_wm {\n\tu16 pri_latency[5];\n\tu16 spr_latency[5];\n\tu16 cur_latency[5];\n\tu16 skl_latency[8];\n\tunion {\n\t\tstruct ilk_wm_values hw;\n\t\tstruct vlv_wm_values vlv;\n\t\tstruct g4x_wm_values g4x;\n\t};\n\tu8 num_levels;\n\tstruct mutex wm_mutex;\n\tbool ipc_enabled;\n};\n\nstruct intel_display_parent_interface;\n\nstruct intel_display_funcs;\n\nstruct intel_dpll_global_funcs;\n\nstruct intel_hotplug_funcs;\n\nstruct intel_wm_funcs;\n\nstruct intel_fdi_funcs;\n\nstruct intel_dmc;\n\nstruct intel_fbc;\n\nstruct intel_gmbus;\n\nstruct intel_hdcp_gsc_context;\n\nstruct intel_display_device_info;\n\nstruct intel_opregion;\n\nstruct intel_display {\n\tstruct drm_device *drm;\n\tstruct intel_display_platforms platform;\n\tenum intel_pch pch_type;\n\tconst struct intel_display_parent_interface *parent;\n\tstruct {\n\t\tconst struct intel_display_funcs *display;\n\t\tconst struct intel_cdclk_funcs *cdclk;\n\t\tconst struct intel_dpll_global_funcs *dpll;\n\t\tconst struct intel_hotplug_funcs *hotplug;\n\t\tconst struct intel_wm_funcs *wm;\n\t\tconst struct intel_fdi_funcs *fdi;\n\t\tconst struct intel_color_funcs *color;\n\t\tconst struct intel_audio_funcs *audio;\n\t} funcs;\n\tstruct {\n\t\tbool any_task_allowed;\n\t\tstruct task_struct *allowed_task;\n\t} access;\n\tstruct {\n\t\tstruct mutex lock;\n\t} backlight;\n\tstruct {\n\t\tstruct intel_global_obj obj;\n\t\tstruct intel_bw_info max[6];\n\t} bw;\n\tstruct {\n\t\tstruct intel_cdclk_config hw;\n\t\tconst struct intel_cdclk_vals *table;\n\t\tstruct intel_global_obj obj;\n\t\tunsigned int max_cdclk_freq;\n\t\tunsigned int max_dotclk_freq;\n\t\tunsigned int skl_preferred_vco_freq;\n\t} cdclk;\n\tstruct {\n\t\tstruct drm_property_blob *glk_linear_degamma_lut;\n\t} color;\n\tstruct {\n\t\tu8 enabled_slices;\n\t\tstruct intel_global_obj obj;\n\t} dbuf;\n\tstruct {\n\t\tstruct intel_global_obj obj;\n\t} dbuf_bw;\n\tstruct {\n\t\tspinlock_t phy_lock;\n\t} dkl;\n\tstruct {\n\t\tstruct intel_dmc *dmc;\n\t\tstruct ref_tracker *wakeref;\n\t} dmc;\n\tstruct {\n\t\tu32 mmio_base;\n\t} dsi;\n\tstruct {\n\t\tconst struct dram_info *info;\n\t} dram;\n\tstruct {\n\t\tstruct intel_fbc *instances[4];\n\t\tstruct sys_cache_cfg sys_cache;\n\t} fbc;\n\tstruct {\n\t\tstruct intel_fbdev *fbdev;\n\t} fbdev;\n\tstruct {\n\t\tunsigned int pll_freq;\n\t\tu32 rx_config;\n\t} fdi;\n\tstruct {\n\t\tstruct list_head obj_list;\n\t} global;\n\tstruct {\n\t\tu32 mmio_base;\n\t\tstruct mutex mutex;\n\t\tstruct intel_gmbus *bus[15];\n\t\twait_queue_head_t wait_queue;\n\t} gmbus;\n\tstruct {\n\t\tstruct i915_hdcp_arbiter *arbiter;\n\t\tbool comp_added;\n\t\tstruct intel_hdcp_gsc_context *gsc_context;\n\t\tstruct mutex hdcp_mutex;\n\t} hdcp;\n\tstruct {\n\t\tu32 state;\n\t} hti;\n\tstruct {\n\t\tconst struct intel_display_device_info *__device_info;\n\t\tstruct intel_display_runtime_info __runtime_info;\n\t} info;\n\tstruct {\n\t\tbool false_color;\n\t} ips;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool vlv_display_irqs_enabled;\n\t\tu8 vblank_enabled;\n\t\tint vblank_enable_count;\n\t\tstruct work_struct vblank_notify_work;\n\t\tu32 vlv_imr_mask;\n\t\tu32 ilk_de_imr_mask;\n\t\tu32 de_pipe_imr_mask[4];\n\t\tu32 pipestat_irq_mask[4];\n\t} irq;\n\tstruct {\n\t\tu16 linetime[4];\n\t\tbool disable[4];\n\t} pkgc;\n\tstruct {\n\t\twait_queue_head_t waitqueue;\n\t\tstruct mutex lock;\n\t\tstruct intel_global_obj obj;\n\t} pmdemand;\n\tstruct {\n\t\tstruct i915_power_domains domains;\n\t\tu32 chv_phy_control;\n\t\tbool chv_phy_assert[2];\n\t} power;\n\tstruct {\n\t\tu32 mmio_base;\n\t\tstruct mutex mutex;\n\t} pps;\n\tstruct {\n\t\tstruct drm_property *broadcast_rgb;\n\t\tstruct drm_property *force_audio;\n\t} properties;\n\tstruct {\n\t\tlong unsigned int mask;\n\t} quirks;\n\tstruct {\n\t\tstruct drm_atomic_state *modeset_state;\n\t\tstruct drm_modeset_acquire_ctx reset_ctx;\n\t\tatomic_t pending_fb_pin;\n\t\tu32 saveDSPARB;\n\t\tu32 saveSWF0[16];\n\t\tu32 saveSWF1[16];\n\t\tu32 saveSWF3[3];\n\t\tu16 saveGCDGMBUS;\n\t} restore;\n\tstruct {\n\t\tenum {\n\t\t\tI915_SAGV_UNKNOWN = 0,\n\t\t\tI915_SAGV_DISABLED = 1,\n\t\t\tI915_SAGV_ENABLED = 2,\n\t\t\tI915_SAGV_NOT_CONTROLLED = 3,\n\t\t} status;\n\t\tu32 block_time_us;\n\t} sagv;\n\tstruct {\n\t\tstruct mutex lock;\n\t} sbi;\n\tstruct {\n\t\tu8 phy_failed_calibration;\n\t} snps;\n\tstruct {\n\t\tu32 chv_dpll_md[4];\n\t\tu32 bxt_phy_grc;\n\t} state;\n\tstruct {\n\t\tunsigned int hpll_freq;\n\t\tunsigned int czclk_freq;\n\t} vlv_clock;\n\tstruct {\n\t\tstruct workqueue_struct *modeset;\n\t\tstruct workqueue_struct *flip;\n\t\tstruct workqueue_struct *cleanup;\n\t\tstruct workqueue_struct *unordered;\n\t} wq;\n\tstruct drm_dp_tunnel_mgr *dp_tunnel_mgr;\n\tstruct intel_audio audio;\n\tstruct intel_dpll_global dpll;\n\tstruct intel_frontbuffer_tracking fb_tracking;\n\tstruct intel_hotplug hotplug;\n\tstruct intel_opregion *opregion;\n\tstruct intel_overlay *overlay;\n\tstruct intel_display_params params;\n\tstruct intel_vbt_data vbt;\n\tstruct intel_dmc_wl wl;\n\tstruct intel_wm wm;\n\tstruct work_struct psr_dc5_dc6_wa_work;\n};\n\nstruct intel_display_device_info {\n\tconst struct intel_display_runtime_info __runtime_defaults;\n\tu8 abox_mask;\n\tstruct {\n\t\tu16 size;\n\t\tu8 slice_mask;\n\t} dbuf;\n\tu8 cursor_needs_physical: 1;\n\tu8 has_cdclk_crawl: 1;\n\tu8 has_cdclk_squash: 1;\n\tu8 has_ddi: 1;\n\tu8 has_dp_mst: 1;\n\tu8 has_dsb: 1;\n\tu8 has_fpga_dbg: 1;\n\tu8 has_gmch: 1;\n\tu8 has_hotplug: 1;\n\tu8 has_hti: 1;\n\tu8 has_ipc: 1;\n\tu8 has_overlay: 1;\n\tu8 has_psr: 1;\n\tu8 has_psr_hw_tracking: 1;\n\tu8 overlay_needs_physical: 1;\n\tu8 supports_tv: 1;\n\tu32 mmio_offset;\n\tu32 pipe_offsets[7];\n\tu32 trans_offsets[7];\n\tu32 cursor_offsets[4];\n\tstruct {\n\t\tu32 degamma_lut_size;\n\t\tu32 gamma_lut_size;\n\t\tu32 degamma_lut_tests;\n\t\tu32 gamma_lut_tests;\n\t} color;\n};\n\nstruct intel_initial_plane_config;\n\nstruct intel_display_funcs {\n\tbool (*get_pipe_config)(struct intel_crtc *, struct intel_crtc_state *);\n\tvoid (*get_initial_plane_config)(struct intel_crtc *, struct intel_initial_plane_config *);\n\tbool (*fixup_initial_plane_config)(struct intel_crtc *, const struct intel_initial_plane_config *);\n\tvoid (*crtc_enable)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*crtc_disable)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*commit_modeset_enables)(struct intel_atomic_state *);\n};\n\nstruct intel_display_hdcp_interface {\n\tssize_t (*gsc_msg_send)(struct intel_hdcp_gsc_context *, void *, size_t, void *, size_t);\n\tbool (*gsc_check_status)(struct drm_device *);\n\tstruct intel_hdcp_gsc_context * (*gsc_context_alloc)(struct drm_device *);\n\tvoid (*gsc_context_free)(struct intel_hdcp_gsc_context *);\n};\n\nstruct intel_display_initial_plane_interface {\n\tvoid (*vblank_wait)(struct drm_crtc *);\n\tstruct drm_gem_object * (*alloc_obj)(struct drm_device *, struct intel_initial_plane_config *);\n\tint (*setup)(struct drm_plane_state *, struct intel_initial_plane_config *, struct drm_framebuffer *, struct i915_vma *);\n\tvoid (*config_fini)(struct intel_initial_plane_config *);\n};\n\nstruct intel_display_irq_interface {\n\tbool (*enabled)(struct drm_device *);\n\tvoid (*synchronize)(struct drm_device *);\n};\n\nstruct intel_display_irq_snapshot {\n\tu32 derrmr;\n};\n\nstruct intel_panic;\n\nstruct intel_display_panic_interface {\n\tstruct intel_panic * (*alloc)(void);\n\tint (*setup)(struct intel_panic *, struct drm_scanout_buffer *);\n\tvoid (*finish)(struct intel_panic *);\n};\n\nstruct intel_display_pc8_interface;\n\nstruct intel_display_rpm_interface;\n\nstruct intel_display_rps_interface;\n\nstruct intel_display_stolen_interface;\n\nstruct intel_display_parent_interface {\n\tconst struct intel_display_hdcp_interface *hdcp;\n\tconst struct intel_display_initial_plane_interface *initial_plane;\n\tconst struct intel_display_irq_interface *irq;\n\tconst struct intel_display_panic_interface *panic;\n\tconst struct intel_display_pc8_interface *pc8;\n\tconst struct intel_display_rpm_interface *rpm;\n\tconst struct intel_display_rps_interface *rps;\n\tconst struct intel_display_stolen_interface *stolen;\n\tstruct {\n\t\tvoid (*fence_priority_display)(struct dma_fence *);\n\t\tbool (*has_auxccs)(struct drm_device *);\n\t\tbool (*has_fenced_regions)(struct drm_device *);\n\t\tbool (*vgpu_active)(struct drm_device *);\n\t};\n};\n\nstruct intel_display_pc8_interface {\n\tvoid (*block)(struct drm_device *);\n\tvoid (*unblock)(struct drm_device *);\n};\n\nstruct intel_display_rpm_interface {\n\tstruct ref_tracker * (*get)(const struct drm_device *);\n\tstruct ref_tracker * (*get_raw)(const struct drm_device *);\n\tstruct ref_tracker * (*get_if_in_use)(const struct drm_device *);\n\tstruct ref_tracker * (*get_noresume)(const struct drm_device *);\n\tvoid (*put)(const struct drm_device *, struct ref_tracker *);\n\tvoid (*put_raw)(const struct drm_device *, struct ref_tracker *);\n\tvoid (*put_unchecked)(const struct drm_device *);\n\tbool (*suspended)(const struct drm_device *);\n\tvoid (*assert_held)(const struct drm_device *);\n\tvoid (*assert_block)(const struct drm_device *);\n\tvoid (*assert_unblock)(const struct drm_device *);\n};\n\nstruct intel_display_rps_interface {\n\tvoid (*boost_if_not_started)(struct dma_fence *);\n\tvoid (*mark_interactive)(struct drm_device *, bool);\n\tvoid (*ilk_irq_handler)(struct drm_device *);\n};\n\nstruct intel_overlay_snapshot;\n\nstruct intel_dmc_snapshot;\n\nstruct intel_display_snapshot {\n\tstruct intel_display *display;\n\tstruct intel_display_device_info info;\n\tstruct intel_display_runtime_info runtime_info;\n\tstruct intel_display_params params;\n\tstruct intel_overlay_snapshot *overlay;\n\tstruct intel_dmc_snapshot *dmc;\n\tstruct intel_display_irq_snapshot *irq;\n};\n\nstruct intel_stolen_node;\n\nstruct intel_display_stolen_interface {\n\tint (*insert_node_in_range)(struct intel_stolen_node *, u64, unsigned int, u64, u64);\n\tint (*insert_node)(struct intel_stolen_node *, u64, unsigned int);\n\tvoid (*remove_node)(struct intel_stolen_node *);\n\tbool (*initialized)(struct drm_device *);\n\tbool (*node_allocated)(const struct intel_stolen_node *);\n\tu64 (*node_offset)(const struct intel_stolen_node *);\n\tu64 (*area_address)(struct drm_device *);\n\tu64 (*area_size)(struct drm_device *);\n\tu64 (*node_address)(const struct intel_stolen_node *);\n\tu64 (*node_size)(const struct intel_stolen_node *);\n\tstruct intel_stolen_node * (*node_alloc)(struct drm_device *);\n\tvoid (*node_free)(const struct intel_stolen_node *);\n};\n\nstruct intel_dkl_phy_reg {\n\tu32 reg: 24;\n\tu32 bank_idx: 4;\n};\n\nstruct intel_dmc {\n\tstruct intel_display *display;\n\tstruct work_struct work;\n\tconst char *fw_path;\n\tu32 max_fw_size;\n\tu32 version;\n\tstruct {\n\t\tu32 dc5_start;\n\t\tu32 count;\n\t} dc6_allowed;\n\tstruct dmc_fw_info dmc_info[5];\n};\n\nstruct intel_dmc_header_base {\n\tu32 signature;\n\tu8 header_len;\n\tu8 header_ver;\n\tu16 dmcc_ver;\n\tu32 project;\n\tu32 fw_size;\n\tu32 fw_version;\n};\n\nstruct intel_dmc_header_v1 {\n\tstruct intel_dmc_header_base base;\n\tu32 mmio_count;\n\tu32 mmioaddr[8];\n\tu32 mmiodata[8];\n\tchar dfile[32];\n\tu32 reserved1[2];\n};\n\nstruct intel_dmc_header_v3 {\n\tstruct intel_dmc_header_base base;\n\tu32 start_mmioaddr;\n\tu32 reserved[9];\n\tchar dfile[32];\n\tu32 mmio_count;\n\tu32 mmioaddr[20];\n\tu32 mmiodata[20];\n};\n\nstruct intel_dmc_snapshot {\n\tbool initialized;\n\tbool loaded;\n\tu32 version;\n};\n\nstruct intel_dmc_wl_range {\n\tu32 start;\n\tu32 end;\n};\n\nstruct intel_dmi_quirk {\n\tvoid (*hook)(struct intel_display *);\n\tconst struct dmi_system_id (*dmi_id_list)[0];\n};\n\nstruct intel_dp_mst_encoder {\n\tstruct intel_encoder base;\n\tenum pipe pipe;\n\tstruct intel_digital_port *primary;\n\tstruct intel_connector *connector;\n};\n\nstruct intel_dpcd_quirk {\n\tint device;\n\tint subsystem_vendor;\n\tint subsystem_device;\n\tu8 sink_oui[3];\n\tu8 sink_device_id[6];\n\tvoid (*hook)(struct intel_dp *);\n};\n\nstruct intel_dpll_funcs {\n\tvoid (*enable)(struct intel_display *, struct intel_dpll *, const struct intel_dpll_hw_state *);\n\tvoid (*disable)(struct intel_display *, struct intel_dpll *);\n\tbool (*get_hw_state)(struct intel_display *, struct intel_dpll *, struct intel_dpll_hw_state *);\n\tint (*get_freq)(struct intel_display *, const struct intel_dpll *, const struct intel_dpll_hw_state *);\n};\n\nstruct intel_dpll_global_funcs {\n\tint (*crtc_compute_clock)(struct intel_atomic_state *, struct intel_crtc *);\n\tint (*crtc_get_dpll)(struct intel_atomic_state *, struct intel_crtc *);\n};\n\nstruct intel_dpll_mgr {\n\tconst struct dpll_info *dpll_info;\n\tint (*compute_dplls)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tint (*get_dplls)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tvoid (*put_dplls)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*update_active_dpll)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tvoid (*update_ref_clks)(struct intel_display *);\n\tvoid (*dump_hw_state)(struct drm_printer *, const struct intel_dpll_hw_state *);\n\tbool (*compare_hw_state)(const struct intel_dpll_hw_state *, const struct intel_dpll_hw_state *);\n};\n\nstruct intel_dsb_buffer;\n\nstruct intel_dsb {\n\tenum intel_dsb_id id;\n\tstruct intel_dsb_buffer *dsb_buf;\n\tstruct intel_crtc *crtc;\n\tunsigned int size;\n\tunsigned int free_pos;\n\tu32 ins[2];\n\tunsigned int ins_start_offset;\n\tu32 chicken;\n\tint hw_dewake_scanline;\n};\n\nstruct intel_dsb_buffer {\n\tu32 *cmd_buf;\n\tstruct i915_vma *vma;\n\tsize_t buf_size;\n};\n\nstruct intel_dsi_host;\n\nstruct intel_dsi {\n\tstruct intel_encoder base;\n\tstruct intel_dsi_host *dsi_hosts[9];\n\tstruct ref_tracker *io_wakeref[9];\n\tstruct gpio_desc *gpio_panel;\n\tstruct gpio_desc *gpio_backlight;\n\tstruct intel_connector *attached_connector;\n\tunion {\n\t\tu16 ports;\n\t\tu16 phys;\n\t};\n\tint channel;\n\tu16 operation_mode;\n\tunsigned int lane_count;\n\tint i2c_bus_num;\n\tenum mipi_dsi_pixel_format pixel_format;\n\tint video_mode;\n\tu8 eotp_pkt;\n\tu8 clock_stop;\n\tu8 escape_clk_div;\n\tu8 dual_link;\n\tbool bgr_enabled;\n\tu8 pixel_overlap;\n\tu32 bw_timer;\n\tu32 dphy_reg;\n\tu32 dphy_data_lane_reg;\n\tu32 video_frmt_cfg_bits;\n\tu16 lp_byte_clk;\n\tu16 hs_tx_timeout;\n\tu16 lp_rx_timeout;\n\tu16 turn_arnd_val;\n\tu16 rst_timer_val;\n\tu16 hs_to_lp_count;\n\tu16 clk_lp_to_hs_count;\n\tu16 clk_hs_to_lp_count;\n\tu16 init_count;\n\tu32 pclk;\n\tu16 burst_mode_ratio;\n\tu16 backlight_off_delay;\n\tu16 backlight_on_delay;\n\tu16 panel_on_delay;\n\tu16 panel_off_delay;\n\tu16 panel_pwr_cycle_delay;\n\tktime_t panel_power_off_time;\n};\n\nstruct mipi_dsi_host_ops;\n\nstruct mipi_dsi_host {\n\tstruct device *dev;\n\tconst struct mipi_dsi_host_ops *ops;\n\tstruct list_head list;\n};\n\nstruct mipi_dsi_device;\n\nstruct intel_dsi_host {\n\tstruct mipi_dsi_host base;\n\tstruct intel_dsi *intel_dsi;\n\tenum port port;\n\tstruct mipi_dsi_device *device;\n};\n\nstruct intel_dvo_dev_ops;\n\nstruct intel_dvo_device {\n\tconst char *name;\n\tint type;\n\tenum port port;\n\tu32 gpio;\n\tint target_addr;\n\tconst struct intel_dvo_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct i2c_adapter *i2c_bus;\n};\n\nstruct intel_dvo {\n\tstruct intel_encoder base;\n\tstruct intel_dvo_device dev;\n\tstruct intel_connector *attached_connector;\n};\n\nstruct intel_dvo_dev_ops {\n\tbool (*init)(struct intel_dvo_device *, struct i2c_adapter *);\n\tvoid (*dpms)(struct intel_dvo_device *, bool);\n\tenum drm_mode_status (*mode_valid)(struct intel_dvo_device *, const struct drm_display_mode *);\n\tvoid (*mode_set)(struct intel_dvo_device *, const struct drm_display_mode *, const struct drm_display_mode *);\n\tenum drm_connector_status (*detect)(struct intel_dvo_device *);\n\tbool (*get_hw_state)(struct intel_dvo_device *);\n\tvoid (*destroy)(struct intel_dvo_device *);\n\tvoid (*dump_regs)(struct intel_dvo_device *);\n};\n\nstruct intel_early_ops {\n\tresource_size_t (*stolen_size)(int, int, int);\n\tresource_size_t (*stolen_base)(int, int, int, resource_size_t);\n};\n\nstruct intel_engine_capture_vma {\n\tstruct intel_engine_capture_vma *next;\n\tstruct i915_vma_resource *vma_res;\n\tchar name[16];\n\tbool lockdep_cookie;\n};\n\nstruct intel_instdone {\n\tu32 instdone;\n\tu32 slice_common;\n\tu32 slice_common_extra[2];\n\tu32 sampler[128];\n\tu32 row[128];\n\tu32 geom_svg[128];\n};\n\nstruct intel_guc_state_capture;\n\nstruct intel_engine_coredump {\n\tconst struct intel_engine_cs *engine;\n\tbool hung;\n\tbool simulated;\n\tu32 reset_count;\n\tu32 rq_head;\n\tu32 rq_post;\n\tu32 rq_tail;\n\tu32 ccid;\n\tu32 start;\n\tu32 tail;\n\tu32 head;\n\tu32 ctl;\n\tu32 mode;\n\tu32 hws;\n\tu32 ipeir;\n\tu32 ipehr;\n\tu32 esr;\n\tu32 bbstate;\n\tu32 instpm;\n\tu32 instps;\n\tu64 bbaddr;\n\tu64 acthd;\n\tu32 fault_reg;\n\tu64 faddr;\n\tu32 rc_psmi;\n\tu32 nopid;\n\tu32 excc;\n\tu32 cmd_cctl;\n\tu32 cscmdop;\n\tu32 ctx_sr_ctl;\n\tu32 dma_faddr_hi;\n\tu32 dma_faddr_lo;\n\tstruct intel_instdone instdone;\n\tstruct intel_guc_state_capture *guc_capture;\n\tstruct __guc_capture_parsed_output *guc_capture_node;\n\tstruct i915_gem_context_coredump context;\n\tstruct i915_vma_coredump *vma;\n\tstruct i915_request_coredump execlist[2];\n\tunsigned int num_ports;\n\tstruct {\n\t\tu32 gfx_mode;\n\t\tunion {\n\t\t\tu64 pdp[4];\n\t\t\tu32 pp_dir_base;\n\t\t};\n\t} vm_info;\n\tstruct intel_engine_coredump *next;\n};\n\nstruct intel_excl_states {\n\tenum intel_excl_state_type state[64];\n\tbool sched_started;\n};\n\nstruct intel_excl_cntrs {\n\traw_spinlock_t lock;\n\tstruct intel_excl_states states[2];\n\tunion {\n\t\tu16 has_exclusive[2];\n\t\tu32 exclusive_present;\n\t};\n\tint refcnt;\n\tunsigned int core_id;\n};\n\nstruct intel_fb_view {\n\tstruct i915_gtt_view gtt;\n\tstruct i915_color_plane_view color_plane[4];\n};\n\nstruct intel_plane;\n\nstruct intel_fbc_state {\n\tstruct intel_plane *plane;\n\tunsigned int cfb_stride;\n\tunsigned int cfb_size;\n\tunsigned int fence_y_offset;\n\tu16 override_cfb_stride;\n\tu16 interval;\n\ts8 fence_id;\n\tstruct drm_rect dirty_rect;\n};\n\nstruct intel_fbc_funcs;\n\nstruct intel_fbc {\n\tstruct intel_display *display;\n\tconst struct intel_fbc_funcs *funcs;\n\tstruct mutex lock;\n\tunsigned int busy_bits;\n\tstruct intel_stolen_node *compressed_fb;\n\tstruct intel_stolen_node *compressed_llb;\n\tenum intel_fbc_id id;\n\tu8 limit;\n\tbool false_color;\n\tbool active;\n\tbool activated;\n\tbool flip_pending;\n\tbool underrun_detected;\n\tstruct work_struct underrun_work;\n\tstruct intel_fbc_state state;\n\tconst char *no_fbc_reason;\n};\n\nstruct intel_fbc_funcs {\n\tvoid (*activate)(struct intel_fbc *);\n\tvoid (*deactivate)(struct intel_fbc *);\n\tbool (*is_active)(struct intel_fbc *);\n\tbool (*is_compressing)(struct intel_fbc *);\n\tvoid (*nuke)(struct intel_fbc *);\n\tvoid (*program_cfb)(struct intel_fbc *);\n\tvoid (*set_false_color)(struct intel_fbc *, bool);\n};\n\nstruct intel_fdi_funcs {\n\tvoid (*fdi_link_train)(struct intel_crtc *, const struct intel_crtc_state *);\n};\n\nstruct intel_forcewake_range {\n\tu32 start;\n\tu32 end;\n\tenum forcewake_domains domains;\n};\n\nstruct intel_framebuffer {\n\tstruct drm_framebuffer base;\n\tstruct intel_frontbuffer *frontbuffer;\n\tstruct intel_fb_view normal_view;\n\tunion {\n\t\tstruct intel_fb_view rotated_view;\n\t\tstruct intel_fb_view remapped_view;\n\t};\n\tstruct i915_address_space *dpt_vm;\n\tunsigned int min_alignment;\n\tunsigned int vtd_guard;\n\tunsigned int (*panic_tiling)(unsigned int, unsigned int, unsigned int);\n\tstruct intel_panic *panic;\n};\n\nstruct intel_fw_info {\n\tu8 reserved1;\n\tu8 dmc_id;\n\tchar stepping;\n\tchar substepping;\n\tu32 offset;\n\tu32 reserved2;\n};\n\nstruct intel_global_commit {\n\tstruct kref ref;\n\tstruct completion done;\n};\n\nstruct intel_global_objs_state {\n\tstruct intel_global_obj *ptr;\n\tstruct intel_global_state *state;\n\tstruct intel_global_state *old_state;\n\tstruct intel_global_state *new_state;\n};\n\nstruct intel_global_state_funcs {\n\tstruct intel_global_state * (*atomic_duplicate_state)(struct intel_global_obj *);\n\tvoid (*atomic_destroy_state)(struct intel_global_obj *, struct intel_global_state *);\n};\n\nstruct intel_gmbus {\n\tstruct i2c_adapter adapter;\n\tu32 force_bit;\n\tu32 reg0;\n\ti915_reg_t gpio_reg;\n\tstruct i2c_algo_bit_data bit_algo;\n\tstruct intel_display *display;\n};\n\nstruct mei_aux_device;\n\nstruct intel_gsc_intf {\n\tstruct mei_aux_device *adev;\n\tstruct drm_i915_gem_object *gem_obj;\n\tint irq;\n\tunsigned int id;\n};\n\nstruct intel_gsc {\n\tstruct intel_gsc_intf intf[2];\n};\n\nstruct intel_gsc_bpdt_entry {\n\tu32 type;\n\tu32 sub_partition_offset;\n\tu32 sub_partition_size;\n};\n\nstruct intel_gsc_version {\n\tu16 major;\n\tu16 minor;\n\tu16 hotfix;\n\tu16 build;\n};\n\nstruct intel_gsc_bpdt_header {\n\tu32 signature;\n\tu16 descriptor_count;\n\tu8 version;\n\tu8 configuration;\n\tu32 crc32;\n\tu32 build_version;\n\tstruct intel_gsc_version tool_version;\n};\n\nstruct intel_gsc_cpd_entry {\n\tu8 name[12];\n\tu32 offset;\n\tu32 length;\n\tu8 reserved[4];\n};\n\nstruct intel_gsc_cpd_header_v2 {\n\tu32 header_marker;\n\tu32 num_of_entries;\n\tu8 header_version;\n\tu8 entry_version;\n\tu8 header_length;\n\tu8 flags;\n\tu32 partition_name;\n\tu32 crc32;\n};\n\nstruct intel_gsc_heci_non_priv_pkt {\n\tu64 addr_in;\n\tu32 size_in;\n\tu64 addr_out;\n\tu32 size_out;\n\tstruct i915_vma *heci_pkt_vma;\n\tstruct i915_vma *bb_vma;\n};\n\nstruct intel_gsc_partition {\n\tu32 offset;\n\tu32 size;\n};\n\nstruct intel_gsc_layout_pointers {\n\tu8 rom_bypass_vector[16];\n\tu16 size;\n\tu8 flags;\n\tu8 reserved;\n\tu32 crc32;\n\tstruct intel_gsc_partition datap;\n\tstruct intel_gsc_partition boot1;\n\tstruct intel_gsc_partition boot2;\n\tstruct intel_gsc_partition boot3;\n\tstruct intel_gsc_partition boot4;\n\tstruct intel_gsc_partition boot5;\n\tstruct intel_gsc_partition temp_pages;\n};\n\nstruct intel_gsc_manifest_header {\n\tu32 header_type;\n\tu32 header_length;\n\tu32 header_version;\n\tu32 flags;\n\tu32 vendor;\n\tu32 date;\n\tu32 size;\n\tu32 header_id;\n\tu32 internal_data;\n\tstruct intel_gsc_version fw_version;\n\tu32 security_version;\n\tstruct intel_gsc_version meu_kit_version;\n\tu32 meu_manifest_version;\n\tu8 general_data[4];\n\tu8 reserved3[56];\n\tu32 modulus_size;\n\tu32 exponent_size;\n};\n\nstruct intel_gsc_mkhi_header {\n\tu8 group_id;\n\tu8 command;\n\tu8 reserved;\n\tu8 result;\n};\n\nstruct intel_uc_fw_ver {\n\tu32 major;\n\tu32 minor;\n\tu32 patch;\n\tu32 build;\n};\n\nstruct intel_uc_fw_file {\n\tconst char *path;\n\tstruct intel_uc_fw_ver ver;\n};\n\nstruct intel_uc_fw {\n\tenum intel_uc_fw_type type;\n\tunion {\n\t\tconst enum intel_uc_fw_status status;\n\t\tenum intel_uc_fw_status __status;\n\t};\n\tstruct intel_uc_fw_file file_wanted;\n\tstruct intel_uc_fw_file file_selected;\n\tbool user_overridden;\n\tsize_t size;\n\tstruct drm_i915_gem_object *obj;\n\tbool needs_ggtt_mapping;\n\tstruct i915_vma_resource vma_res;\n\tstruct i915_vma *rsa_data;\n\tu32 rsa_size;\n\tu32 ucode_size;\n\tu32 private_data_size;\n\tu32 dma_start_offset;\n\tbool has_gsc_headers;\n};\n\nstruct intel_gsc_uc {\n\tstruct intel_uc_fw fw;\n\tstruct intel_uc_fw_ver release;\n\tu32 security_version;\n\tstruct i915_vma *local;\n\tvoid *local_vaddr;\n\tstruct intel_context *ce;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct work;\n\tu32 gsc_work_actions;\n\tstruct {\n\t\tstruct i915_gsc_proxy_component *component;\n\t\tbool component_added;\n\t\tstruct i915_vma *vma;\n\t\tvoid *to_gsc;\n\t\tvoid *to_csme;\n\t\tstruct mutex mutex;\n\t} proxy;\n};\n\nstruct intel_guc_log {\n\tu32 level;\n\tstruct mutex guc_lock;\n\tstruct {\n\t\ts32 bytes;\n\t\ts32 units;\n\t\ts32 count;\n\t\tu32 flag;\n\t} sizes[3];\n\tbool sizes_initialised;\n\tstruct i915_vma *vma;\n\tvoid *buf_addr;\n\tstruct {\n\t\tbool buf_in_use;\n\t\tbool started;\n\t\tstruct work_struct flush_work;\n\t\tstruct rchan *channel;\n\t\tstruct mutex lock;\n\t\tu32 full_count;\n\t} relay;\n\tstruct {\n\t\tu32 sampled_overflow;\n\t\tu32 overflow;\n\t\tu32 flush;\n\t} stats[3];\n};\n\nstruct intel_guc_ct_buffer {\n\tspinlock_t lock;\n\tstruct guc_ct_buffer_desc *desc;\n\tu32 *cmds;\n\tu32 size;\n\tu32 resv_space;\n\tu32 tail;\n\tu32 head;\n\tatomic_t space;\n\tbool broken;\n};\n\nstruct intel_guc_ct {\n\tstruct i915_vma *vma;\n\tbool enabled;\n\tstruct {\n\t\tstruct intel_guc_ct_buffer send;\n\t\tstruct intel_guc_ct_buffer recv;\n\t} ctbs;\n\tstruct tasklet_struct receive_tasklet;\n\twait_queue_head_t wq;\n\tstruct {\n\t\tu16 last_fence;\n\t\tspinlock_t lock;\n\t\tstruct list_head pending;\n\t\tstruct list_head incoming;\n\t\tstruct work_struct worker;\n\t} requests;\n\tktime_t stall_time;\n};\n\nstruct slpc_shared_data;\n\nstruct intel_guc_slpc {\n\tstruct i915_vma *vma;\n\tstruct slpc_shared_data *vaddr;\n\tbool supported;\n\tbool selected;\n\tbool min_is_rpmax;\n\tu32 min_freq;\n\tu32 rp0_freq;\n\tu32 rp1_freq;\n\tu32 boost_freq;\n\tu32 min_freq_softlimit;\n\tu32 max_freq_softlimit;\n\tbool ignore_eff_freq;\n\tu32 power_profile;\n\tu32 media_ratio_mode;\n\tstruct mutex lock;\n\tstruct work_struct boost_work;\n\tatomic_t num_waiters;\n\tu32 num_boosts;\n};\n\nstruct intel_guc {\n\tstruct intel_uc_fw fw;\n\tstruct intel_guc_log log;\n\tstruct intel_guc_ct ct;\n\tstruct intel_guc_slpc slpc;\n\tstruct intel_guc_state_capture *capture;\n\tstruct dentry *dbgfs_node;\n\tstruct i915_sched_engine *sched_engine;\n\tstruct i915_request *stalled_request;\n\tenum {\n\t\tSTALL_NONE = 0,\n\t\tSTALL_REGISTER_CONTEXT = 1,\n\t\tSTALL_MOVE_LRC_TAIL = 2,\n\t\tSTALL_ADD_REQUEST = 3,\n\t} submission_stall_reason;\n\tspinlock_t irq_lock;\n\tunsigned int msg_enabled_mask;\n\tatomic_t outstanding_submission_g2h;\n\tstruct xarray tlb_lookup;\n\tu32 serial_slot;\n\tu32 next_seqno;\n\tstruct {\n\t\tbool enabled;\n\t\tvoid (*reset)(struct intel_guc *);\n\t\tvoid (*enable)(struct intel_guc *);\n\t\tvoid (*disable)(struct intel_guc *);\n\t} interrupts;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct ida guc_ids;\n\t\tint num_guc_ids;\n\t\tlong unsigned int *guc_ids_bitmap;\n\t\tstruct list_head guc_id_list;\n\t\tunsigned int guc_ids_in_use;\n\t\tstruct list_head destroyed_contexts;\n\t\tstruct work_struct destroyed_worker;\n\t\tstruct work_struct reset_fail_worker;\n\t\tintel_engine_mask_t reset_fail_mask;\n\t\tunsigned int sched_disable_delay_ms;\n\t\tunsigned int sched_disable_gucid_threshold;\n\t} submission_state;\n\tbool submission_supported;\n\tbool submission_selected;\n\tbool submission_initialized;\n\tstruct intel_uc_fw_ver submission_version;\n\tbool rc_supported;\n\tbool rc_selected;\n\tstruct i915_vma *ads_vma;\n\tstruct iosys_map ads_map;\n\tu32 ads_regset_size;\n\tu32 ads_regset_count[27];\n\tstruct guc_mmio_reg *ads_regset;\n\tu32 ads_golden_ctxt_size;\n\tu32 ads_waklv_size;\n\tu32 ads_capture_size;\n\tstruct i915_vma *lrc_desc_pool_v69;\n\tvoid *lrc_desc_pool_vaddr_v69;\n\tstruct xarray context_lookup;\n\tu32 params[14];\n\tstruct {\n\t\tu32 base;\n\t\tunsigned int count;\n\t\tenum forcewake_domains fw_domains;\n\t} send_regs;\n\ti915_reg_t notify_reg;\n\tu32 mmio_msg;\n\tstruct mutex send_mutex;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tu64 gt_stamp;\n\t\tlong unsigned int ping_delay;\n\t\tstruct delayed_work work;\n\t\tu32 shift;\n\t\tlong unsigned int last_stat_jiffies;\n\t} timestamp;\n\tstruct work_struct dead_guc_worker;\n\tlong unsigned int last_dead_guc_jiffies;\n};\n\nstruct intel_huc {\n\tstruct intel_uc_fw fw;\n\tstruct {\n\t\ti915_reg_t reg;\n\t\tu32 mask;\n\t\tu32 value;\n\t} status[2];\n\tstruct {\n\t\tstruct i915_sw_fence fence;\n\t\tstruct hrtimer timer;\n\t\tstruct notifier_block nb;\n\t\tenum intel_huc_delayed_load_status status;\n\t} delayed_load;\n\tstruct i915_vma *heci_pkt;\n\tbool loaded_via_gsc;\n};\n\nstruct intel_uc_ops;\n\nstruct intel_uc {\n\tconst struct intel_uc_ops *ops;\n\tstruct intel_gsc_uc gsc;\n\tstruct intel_guc guc;\n\tstruct intel_huc huc;\n\tstruct drm_i915_gem_object *load_err_log;\n\tbool reset_in_progress;\n\tbool fw_table_invalid;\n};\n\nstruct intel_wopcm {\n\tu32 size;\n\tstruct {\n\t\tu32 base;\n\t\tu32 size;\n\t} guc;\n};\n\nstruct seqcount_mutex {\n\tseqcount_t seqcount;\n\tstruct mutex *lock;\n};\n\ntypedef struct seqcount_mutex seqcount_mutex_t;\n\nstruct intel_gt_timelines {\n\tspinlock_t lock;\n\tstruct list_head active_list;\n};\n\nstruct intel_gt_requests {\n\tstruct delayed_work retire_work;\n};\n\nstruct intel_reset {\n\tlong unsigned int flags;\n\tstruct mutex mutex;\n\twait_queue_head_t queue;\n\tstruct srcu_struct backoff_srcu;\n};\n\nstruct intel_llc {};\n\nstruct intel_rc6 {\n\ti915_reg_t res_reg[4];\n\tu64 prev_hw_residency[4];\n\tu64 cur_residency[4];\n\tu32 ctl_enable;\n\tu32 bios_rc_state;\n\tstruct drm_i915_gem_object *pctx;\n\tbool supported: 1;\n\tbool enabled: 1;\n\tbool manual: 1;\n\tbool wakeref: 1;\n\tbool bios_state_captured: 1;\n};\n\nstruct intel_rps_ei {\n\tktime_t ktime;\n\tu32 render_c0;\n\tu32 media_c0;\n};\n\nstruct intel_ips {\n\tu64 last_count1;\n\tlong unsigned int last_time1;\n\tlong unsigned int chipset_power;\n\tu64 last_count2;\n\tu64 last_time2;\n\tlong unsigned int gfx_power;\n\tu8 corr;\n\tint c;\n\tint m;\n};\n\nstruct intel_rps {\n\tstruct mutex lock;\n\tstruct timer_list timer;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n\tktime_t pm_timestamp;\n\tu32 pm_interval;\n\tu32 pm_iir;\n\tu32 pm_intrmsk_mbz;\n\tu32 pm_events;\n\tu8 cur_freq;\n\tu8 last_freq;\n\tu8 min_freq_softlimit;\n\tu8 max_freq_softlimit;\n\tu8 max_freq;\n\tu8 min_freq;\n\tu8 boost_freq;\n\tu8 idle_freq;\n\tu8 efficient_freq;\n\tu8 rp1_freq;\n\tu8 rp0_freq;\n\tu16 gpll_ref_freq;\n\tint last_adj;\n\tstruct {\n\t\tstruct mutex mutex;\n\t\tenum {\n\t\t\tLOW_POWER = 0,\n\t\t\tBETWEEN = 1,\n\t\t\tHIGH_POWER = 2,\n\t\t} mode;\n\t\tunsigned int interactive;\n\t\tu8 up_threshold;\n\t\tu8 down_threshold;\n\t} power;\n\tatomic_t num_waiters;\n\tunsigned int boosts;\n\tstruct intel_rps_ei ei;\n\tstruct intel_ips ips;\n};\n\nstruct intel_gt_buffer_pool {\n\tspinlock_t lock;\n\tstruct list_head cache_list[4];\n\tstruct delayed_work work;\n};\n\nstruct intel_migrate {\n\tstruct intel_context *context;\n};\n\nstruct sseu_dev_info {\n\tu8 slice_mask;\n\tintel_sseu_ss_mask_t subslice_mask;\n\tintel_sseu_ss_mask_t geometry_subslice_mask;\n\tintel_sseu_ss_mask_t compute_subslice_mask;\n\tunion {\n\t\tu16 hsw[24];\n\t\tu16 xehp[64];\n\t} eu_mask;\n\tu16 eu_total;\n\tu8 eu_per_subslice;\n\tu8 min_eu_in_pool;\n\tu8 subslice_7eu[3];\n\tu8 has_slice_pg: 1;\n\tu8 has_subslice_pg: 1;\n\tu8 has_eu_pg: 1;\n\tu8 has_xehp_dss: 1;\n\tu8 max_slices;\n\tu8 max_subslices;\n\tu8 max_eus_per_subslice;\n};\n\nstruct intel_hwconfig {\n\tu32 size;\n\tvoid *ptr;\n};\n\nstruct intel_gt_info {\n\tunsigned int id;\n\tintel_engine_mask_t engine_mask;\n\tu32 l3bank_mask;\n\tu8 num_engines;\n\tu8 sfc_mask;\n\tu8 vdbox_sfc_access;\n\tstruct sseu_dev_info sseu;\n\tlong unsigned int mslice_mask;\n\tstruct intel_hwconfig hwconfig;\n};\n\nstruct intel_mmio_range;\n\nstruct intel_gt {\n\tstruct drm_i915_private *i915;\n\tconst char *name;\n\tenum intel_gt_type type;\n\tstruct intel_uncore *uncore;\n\tstruct i915_ggtt *ggtt;\n\tstruct intel_uc uc;\n\tstruct intel_gsc gsc;\n\tstruct intel_wopcm wopcm;\n\tstruct {\n\t\tstruct mutex invalidate_lock;\n\t\tseqcount_mutex_t seqno;\n\t} tlb;\n\tstruct i915_wa_list wa_list;\n\tstruct intel_gt_timelines timelines;\n\tstruct intel_gt_requests requests;\n\tstruct {\n\t\tstruct llist_head list;\n\t\tstruct work_struct work;\n\t} watchdog;\n\tstruct intel_wakeref wakeref;\n\tatomic_t user_wakeref;\n\tstruct list_head closed_vma;\n\tspinlock_t closed_lock;\n\tktime_t last_init_time;\n\tstruct intel_reset reset;\n\tintel_wakeref_t awake;\n\tu32 clock_frequency;\n\tu32 clock_period_ns;\n\tstruct intel_llc llc;\n\tstruct intel_rc6 rc6;\n\tstruct intel_rps rps;\n\tspinlock_t *irq_lock;\n\tu32 gt_imr;\n\tu32 pm_ier;\n\tu32 pm_imr;\n\tu32 pm_guc_events;\n\tstruct {\n\t\tbool active;\n\t\tseqcount_mutex_t lock;\n\t\tktime_t total;\n\t\tktime_t start;\n\t} stats;\n\tstruct intel_engine_cs *engine[27];\n\tstruct intel_engine_cs *engine_class[54];\n\tenum intel_submission_method submission_method;\n\tstruct {\n\t\tintel_engine_mask_t cslices;\n\t} ccs;\n\tstruct i915_address_space *vm;\n\tstruct intel_gt_buffer_pool buffer_pool;\n\tstruct i915_vma *scratch;\n\tstruct intel_migrate migrate;\n\tconst struct intel_mmio_range *steering_table[7];\n\tstruct {\n\t\tu8 groupid;\n\t\tu8 instanceid;\n\t} default_steering;\n\tspinlock_t mcr_lock;\n\tphys_addr_t phys_addr;\n\tstruct intel_gt_info info;\n\tstruct {\n\t\tu8 uc_index;\n\t\tu8 wb_index;\n\t} mocs;\n\tstruct kobject sysfs_gt;\n\tstruct gt_defaults defaults;\n\tstruct kobject *sysfs_defaults;\n\tstruct work_struct wedge;\n\tstruct i915_perf_gt perf;\n\tstruct list_head ggtt_link;\n};\n\nstruct intel_gt_bool_throttle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\ti915_reg_t (*reg32)(struct intel_gt *);\n\tu32 mask;\n};\n\nstruct intel_gt_buffer_pool_node {\n\tstruct i915_active active;\n\tstruct drm_i915_gem_object *obj;\n\tstruct list_head link;\n\tunion {\n\t\tstruct intel_gt_buffer_pool *pool;\n\t\tstruct intel_gt_buffer_pool_node *free;\n\t\tstruct callback_head rcu;\n\t};\n\tlong unsigned int age;\n\tenum i915_map_type type;\n\tu32 pinned;\n};\n\nstruct intel_uc_coredump;\n\nstruct intel_gt_coredump {\n\tconst struct intel_gt *_gt;\n\tbool awake;\n\tbool simulated;\n\tstruct intel_gt_info info;\n\tu32 eir;\n\tu32 pgtbl_er;\n\tu32 gtier[6];\n\tu32 ngtier;\n\tu32 forcewake;\n\tu32 error;\n\tu32 err_int;\n\tu32 fault_data0;\n\tu32 fault_data1;\n\tu32 done_reg;\n\tu32 gac_eco;\n\tu32 gam_ecochk;\n\tu32 gab_ctl;\n\tu32 gfx_mode;\n\tu32 gtt_cache;\n\tu32 aux_err;\n\tu32 gam_done;\n\tu32 clock_frequency;\n\tu32 clock_period_ns;\n\tu32 sfc_done[4];\n\tu32 nfence;\n\tu64 fence[32];\n\tstruct intel_engine_coredump *engine;\n\tstruct intel_uc_coredump *uc;\n\tstruct intel_gt_coredump *next;\n};\n\nstruct intel_gt_debugfs_file {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tbool (*eval)(void *);\n};\n\nstruct intel_gt_definition {\n\tenum intel_gt_type type;\n\tchar *name;\n\tu32 mapping_base;\n\tu32 gsi_offset;\n\tintel_engine_mask_t engine_mask;\n};\n\nstruct intel_gtt_driver {\n\tunsigned int gen: 8;\n\tunsigned int is_g33: 1;\n\tunsigned int is_pineview: 1;\n\tunsigned int is_ironlake: 1;\n\tunsigned int has_pgtbl_enable: 1;\n\tunsigned int dma_mask_size: 8;\n\tint (*setup)(void);\n\tvoid (*cleanup)(void);\n\tvoid (*write_entry)(dma_addr_t, unsigned int, unsigned int);\n\tdma_addr_t (*read_entry)(unsigned int, bool *, bool *);\n\tbool (*check_flags)(unsigned int);\n\tvoid (*chipset_flush)(void);\n};\n\nstruct intel_gtt_driver_description {\n\tunsigned int gmch_chip_id;\n\tchar *name;\n\tconst struct intel_gtt_driver *gtt_driver;\n};\n\nstruct intel_guc_state_capture {\n\tconst struct __guc_mmio_reg_descr_group *reglists;\n\tstruct __guc_mmio_reg_descr_group *extlists;\n\tstruct __guc_capture_ads_cache ads_cache[96];\n\tvoid *ads_null_cache;\n\tstruct list_head cachelist;\n\tint max_mmio_per_node;\n\tstruct list_head outlist;\n};\n\nstruct intel_guc_tlb_wait {\n\tstruct wait_queue_head wq;\n\tbool busy;\n};\n\nstruct intel_hdcp_gsc_context {\n\tstruct drm_i915_private *i915;\n\tstruct i915_vma *vma;\n\tvoid *hdcp_cmd_in;\n\tvoid *hdcp_cmd_out;\n};\n\nstruct intel_hdcp_shim {\n\tint (*write_an_aksv)(struct intel_digital_port *, u8 *);\n\tint (*read_bksv)(struct intel_digital_port *, u8 *);\n\tint (*read_bstatus)(struct intel_digital_port *, u8 *);\n\tint (*repeater_present)(struct intel_digital_port *, bool *);\n\tint (*read_ri_prime)(struct intel_digital_port *, u8 *);\n\tint (*read_ksv_ready)(struct intel_digital_port *, bool *);\n\tint (*read_ksv_fifo)(struct intel_digital_port *, int, u8 *);\n\tint (*read_v_prime_part)(struct intel_digital_port *, int, u32 *);\n\tint (*toggle_signalling)(struct intel_digital_port *, enum transcoder, bool);\n\tint (*stream_encryption)(struct intel_connector *, bool);\n\tbool (*check_link)(struct intel_digital_port *, struct intel_connector *);\n\tint (*hdcp_get_capability)(struct intel_digital_port *, bool *);\n\tenum hdcp_wired_protocol protocol;\n\tint (*hdcp_2_2_get_capability)(struct intel_connector *, bool *);\n\tint (*write_2_2_msg)(struct intel_connector *, void *, size_t);\n\tint (*read_2_2_msg)(struct intel_connector *, u8, void *, size_t);\n\tint (*config_stream_type)(struct intel_connector *, bool, u8);\n\tint (*stream_2_2_encryption)(struct intel_connector *, bool);\n\tint (*check_2_2_link)(struct intel_digital_port *, struct intel_connector *);\n\tint (*get_remote_hdcp_capability)(struct intel_connector *, bool *, bool *);\n};\n\nstruct intel_hdmi_lpe_audio_port_pdata {\n\tu8 eld[128];\n\tint port;\n\tint pipe;\n\tint ls_clock;\n\tbool dp_output;\n};\n\nstruct intel_hdmi_lpe_audio_pdata {\n\tstruct intel_hdmi_lpe_audio_port_pdata port[3];\n\tint num_ports;\n\tint num_pipes;\n\tvoid (*notify_audio_lpe)(struct platform_device *, int);\n\tspinlock_t lpe_audio_slock;\n};\n\nstruct intel_hotplug_funcs {\n\tvoid (*hpd_irq_setup)(struct intel_display *);\n\tvoid (*hpd_enable_detection)(struct intel_encoder *);\n};\n\nstruct intel_initial_plane_config {\n\tstruct intel_framebuffer *fb;\n\tstruct intel_memory_region *mem;\n\tresource_size_t phys_base;\n\tstruct i915_vma *vma;\n\tint size;\n\tu32 base;\n\tu8 rotation;\n};\n\nstruct iommu_flush {\n\tvoid (*flush_context)(struct intel_iommu *, u16, u16, u8, u64);\n\tvoid (*flush_iotlb)(struct intel_iommu *, u16, u64, unsigned int, u64);\n};\n\nstruct root_entry;\n\nstruct page_req_dsc;\n\nstruct q_inval;\n\nstruct iommu_pmu;\n\nstruct intel_iommu {\n\tvoid *reg;\n\tu64 reg_phys;\n\tu64 reg_size;\n\tu64 cap;\n\tu64 ecap;\n\tu64 vccap;\n\tu64 ecmdcap[4];\n\tu32 gcmd;\n\traw_spinlock_t register_lock;\n\tint seq_id;\n\tint agaw;\n\tint msagaw;\n\tunsigned int irq;\n\tunsigned int pr_irq;\n\tunsigned int perf_irq;\n\tu16 segment;\n\tunsigned char name[16];\n\tstruct mutex did_lock;\n\tstruct ida domain_ida;\n\tlong unsigned int *copied_tables;\n\tspinlock_t lock;\n\tstruct root_entry *root_entry;\n\tstruct iommu_flush flush;\n\tstruct page_req_dsc *prq;\n\tunsigned char prq_name[16];\n\tlong unsigned int prq_seq_number;\n\tstruct completion prq_complete;\n\tstruct iopf_queue *iopf_queue;\n\tunsigned char iopfq_name[16];\n\tstruct mutex iopf_lock;\n\tstruct q_inval *qi;\n\tu32 iommu_state[4];\n\tstruct rb_root device_rbtree;\n\tspinlock_t device_rbtree_lock;\n\tstruct iommu_device iommu;\n\tint node;\n\tu32 flags;\n\tstruct dmar_drhd_unit *drhd;\n\tvoid *perf_statistic;\n\tstruct iommu_pmu *pmu;\n};\n\nstruct intel_iommu_pi_data {\n\tu64 pi_desc_addr;\n\tu32 vector;\n};\n\nstruct intel_limit {\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} dot;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} vco;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} n;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m1;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m2;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} p;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} p1;\n\tstruct {\n\t\tint dot_limit;\n\t\tint p2_slow;\n\t\tint p2_fast;\n\t} p2;\n};\n\nstruct intel_link_bw_limits {\n\tu8 link_dsc_pipes;\n\tu8 bpp_limit_reached_pipes;\n\tint max_bpp_x16[4];\n};\n\nstruct intel_lvds_pps {\n\tstruct intel_pps_delays delays;\n\tint divider;\n\tint port;\n\tbool powerdown_on_reset;\n};\n\nstruct intel_lvds_encoder {\n\tstruct intel_encoder base;\n\tbool is_dual_link;\n\ti915_reg_t reg;\n\tu32 a3_power;\n\tstruct intel_lvds_pps init_pps;\n\tu32 init_lvds_val;\n\tstruct intel_connector *attached_connector;\n};\n\nstruct intel_memory_region_ops;\n\nstruct intel_memory_region {\n\tstruct drm_i915_private *i915;\n\tconst struct intel_memory_region_ops *ops;\n\tstruct io_mapping iomap;\n\tstruct resource region;\n\tstruct resource io;\n\tresource_size_t min_page_size;\n\tresource_size_t total;\n\tu16 type;\n\tu16 instance;\n\tenum intel_region_id id;\n\tchar name[16];\n\tchar uabi_name[20];\n\tbool private;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct list_head list;\n\t} objects;\n\tbool is_range_manager;\n\tvoid *region_private;\n};\n\nstruct intel_memory_region_ops {\n\tint (*init)(struct intel_memory_region *);\n\tint (*release)(struct intel_memory_region *);\n\tint (*init_object)(struct intel_memory_region *, struct drm_i915_gem_object *, resource_size_t, resource_size_t, resource_size_t, unsigned int);\n};\n\nstruct intel_mmio_range {\n\tu32 start;\n\tu32 end;\n};\n\nstruct intel_modifier_desc {\n\tu64 modifier;\n\tstruct {\n\t\tu8 from;\n\t\tu8 until;\n\t} display_ver;\n\tconst struct drm_format_info *formats;\n\tint format_count;\n\tu8 plane_caps;\n\tstruct {\n\t\tu8 cc_planes: 3;\n\t\tu8 packed_aux_planes: 4;\n\t\tchar: 1;\n\t\tu8 planar_aux_planes: 4;\n\t} ccs;\n};\n\nstruct opregion_header;\n\nstruct opregion_acpi;\n\nstruct opregion_swsci;\n\nstruct opregion_asle;\n\nstruct opregion_asle_ext;\n\nstruct intel_opregion {\n\tstruct intel_display *display;\n\tstruct opregion_header *header;\n\tstruct opregion_acpi *acpi;\n\tstruct opregion_swsci *swsci;\n\tu32 swsci_gbda_sub_functions;\n\tu32 swsci_sbcb_sub_functions;\n\tstruct opregion_asle *asle;\n\tstruct opregion_asle_ext *asle_ext;\n\tvoid *rvda;\n\tconst void *vbt;\n\tu32 vbt_size;\n\tstruct work_struct asle_work;\n\tstruct notifier_block acpi_notifier;\n};\n\nstruct overlay_registers;\n\nstruct intel_overlay {\n\tstruct intel_display *display;\n\tstruct intel_context *context;\n\tstruct intel_crtc *crtc;\n\tstruct i915_vma *vma;\n\tstruct i915_vma *old_vma;\n\tstruct intel_frontbuffer *frontbuffer;\n\tbool active;\n\tbool pfit_active;\n\tu32 pfit_vscale_ratio;\n\tu32 color_key: 24;\n\tu32 color_key_enabled: 1;\n\tu32 brightness;\n\tu32 contrast;\n\tu32 saturation;\n\tu32 old_xscale;\n\tu32 old_yscale;\n\tstruct drm_i915_gem_object *reg_bo;\n\tstruct overlay_registers *regs;\n\tu32 flip_addr;\n\tstruct i915_active last_flip;\n\tvoid (*flip_complete)(struct intel_overlay *);\n};\n\nstruct overlay_registers {\n\tu32 OBUF_0Y;\n\tu32 OBUF_1Y;\n\tu32 OBUF_0U;\n\tu32 OBUF_0V;\n\tu32 OBUF_1U;\n\tu32 OBUF_1V;\n\tu32 OSTRIDE;\n\tu32 YRGB_VPH;\n\tu32 UV_VPH;\n\tu32 HORZ_PH;\n\tu32 INIT_PHS;\n\tu32 DWINPOS;\n\tu32 DWINSZ;\n\tu32 SWIDTH;\n\tu32 SWIDTHSW;\n\tu32 SHEIGHT;\n\tu32 YRGBSCALE;\n\tu32 UVSCALE;\n\tu32 OCLRC0;\n\tu32 OCLRC1;\n\tu32 DCLRKV;\n\tu32 DCLRKM;\n\tu32 SCLRKVH;\n\tu32 SCLRKVL;\n\tu32 SCLRKEN;\n\tu32 OCONFIG;\n\tu32 OCMD;\n\tu32 RESERVED1;\n\tu32 OSTART_0Y;\n\tu32 OSTART_1Y;\n\tu32 OSTART_0U;\n\tu32 OSTART_0V;\n\tu32 OSTART_1U;\n\tu32 OSTART_1V;\n\tu32 OTILEOFF_0Y;\n\tu32 OTILEOFF_1Y;\n\tu32 OTILEOFF_0U;\n\tu32 OTILEOFF_0V;\n\tu32 OTILEOFF_1U;\n\tu32 OTILEOFF_1V;\n\tu32 FASTHSCALE;\n\tu32 UVSCALEV;\n\tu32 RESERVEDC[86];\n\tu16 Y_VCOEFS[51];\n\tu16 RESERVEDD[77];\n\tu16 Y_HCOEFS[85];\n\tu16 RESERVEDE[171];\n\tu16 UV_VCOEFS[51];\n\tu16 RESERVEDF[77];\n\tu16 UV_HCOEFS[51];\n\tu16 RESERVEDG[77];\n};\n\nstruct intel_overlay_snapshot {\n\tstruct overlay_registers regs;\n\tlong unsigned int base;\n\tu32 dovsta;\n\tu32 isr;\n};\n\nstruct intel_package_header {\n\tu8 header_len;\n\tu8 header_ver;\n\tu8 reserved[10];\n\tu32 num_entries;\n};\n\nstruct intel_panel_bl_funcs {\n\tint (*setup)(struct intel_connector *, enum pipe);\n\tu32 (*get)(struct intel_connector *, enum pipe);\n\tvoid (*set)(const struct drm_connector_state *, u32);\n\tvoid (*disable)(const struct drm_connector_state *, u32);\n\tvoid (*enable)(const struct intel_crtc_state *, const struct drm_connector_state *, u32);\n\tu32 (*hz_to_pwm)(struct intel_connector *, u32);\n};\n\nstruct intel_panic {\n\tstruct page **pages;\n\tint page;\n\tvoid *vaddr;\n};\n\nstruct intel_plane_error;\n\nstruct intel_plane {\n\tstruct drm_plane base;\n\tenum i9xx_plane_id i9xx_plane;\n\tenum plane_id id;\n\tenum pipe pipe;\n\tbool need_async_flip_toggle_wa;\n\tu8 vtd_guard;\n\tu32 frontbuffer_bit;\n\tstruct {\n\t\tu32 base;\n\t\tu32 cntl;\n\t\tu32 size;\n\t} cursor;\n\tstruct intel_fbc *fbc;\n\tint (*min_width)(const struct drm_framebuffer *, int, unsigned int);\n\tint (*max_width)(const struct drm_framebuffer *, int, unsigned int);\n\tint (*max_height)(const struct drm_framebuffer *, int, unsigned int);\n\tunsigned int (*min_alignment)(struct intel_plane *, const struct drm_framebuffer *, int);\n\tunsigned int (*max_stride)(struct intel_plane *, const struct drm_format_info *, u64, unsigned int);\n\tbool (*can_async_flip)(u64);\n\tvoid (*update_noarm)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *, const struct intel_plane_state *);\n\tvoid (*update_arm)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *, const struct intel_plane_state *);\n\tvoid (*disable_arm)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *);\n\tvoid (*capture_error)(struct intel_crtc *, struct intel_plane *, struct intel_plane_error *);\n\tbool (*get_hw_state)(struct intel_plane *, enum pipe *);\n\tint (*check_plane)(struct intel_crtc_state *, struct intel_plane_state *);\n\tu32 (*surf_offset)(const struct intel_plane_state *);\n\tint (*min_cdclk)(const struct intel_crtc_state *, const struct intel_plane_state *);\n\tvoid (*async_flip)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *, const struct intel_plane_state *, bool);\n\tvoid (*enable_flip_done)(struct intel_plane *);\n\tvoid (*disable_flip_done)(struct intel_plane *);\n\tvoid (*disable_tiling)(struct intel_plane *);\n};\n\nstruct intel_plane_error {\n\tu32 ctl;\n\tu32 surf;\n\tu32 surflive;\n};\n\nstruct intel_plane_state {\n\tstruct drm_plane_state uapi;\n\tstruct {\n\t\tstruct drm_crtc *crtc;\n\t\tstruct drm_framebuffer *fb;\n\t\tu16 alpha;\n\t\tu16 pixel_blend_mode;\n\t\tunsigned int rotation;\n\t\tenum drm_color_encoding color_encoding;\n\t\tenum drm_color_range color_range;\n\t\tenum drm_scaling_filter scaling_filter;\n\t\tstruct drm_property_blob *ctm;\n\t\tstruct drm_property_blob *degamma_lut;\n\t\tstruct drm_property_blob *gamma_lut;\n\t\tstruct drm_property_blob *lut_3d;\n\t} hw;\n\tstruct i915_vma *ggtt_vma;\n\tstruct i915_vma *dpt_vma;\n\tlong unsigned int flags;\n\tstruct intel_fb_view view;\n\tstruct drm_vblank_work unpin_work;\n\tbool decrypt;\n\tbool force_black;\n\tbool is_y_plane;\n\tu32 ctl;\n\tu32 color_ctl;\n\tu32 cus_ctl;\n\tu32 surf;\n\tint scaler_id;\n\tstruct intel_plane *planar_linked_plane;\n\tstruct drm_intel_sprite_colorkey ckey;\n\tstruct drm_rect psr2_sel_fetch_area;\n\tu64 ccval;\n\tconst char *no_fbc_reason;\n\tstruct drm_rect damage;\n};\n\nstruct pmdemand_params {\n\tu16 qclk_gv_bw;\n\tu8 voltage_index;\n\tu8 qclk_gv_index;\n\tu8 active_pipes;\n\tu8 active_dbufs;\n\tu8 active_phys;\n\tu8 plls;\n\tu16 cdclk_freq_mhz;\n\tu16 ddiclk_max;\n\tu8 scalers;\n};\n\nstruct intel_pmdemand_state {\n\tstruct intel_global_state base;\n\tint ddi_clocks[4];\n\tu16 active_combo_phys_mask;\n\tstruct pmdemand_params params;\n};\n\nstruct intel_psf_gv_point {\n\tu8 clk;\n};\n\nstruct intel_pxp {\n\tstruct intel_gt *ctrl_gt;\n\tbool platform_cfg_is_bad;\n\tu32 kcr_base;\n\tstruct gsccs_session_resources gsccs_res;\n\tstruct i915_pxp_component *pxp_component;\n\tstruct device_link *dev_link;\n\tbool pxp_component_added;\n\tstruct intel_context *ce;\n\tstruct mutex arb_mutex;\n\tbool arb_is_valid;\n\tu32 key_instance;\n\tstruct mutex tee_mutex;\n\tstruct {\n\t\tstruct drm_i915_gem_object *obj;\n\t\tvoid *vaddr;\n\t} stream_cmd;\n\tbool hw_state_invalidated;\n\tbool irq_enabled;\n\tstruct completion termination;\n\tstruct work_struct session_work;\n\tu32 session_events;\n};\n\nstruct intel_qgv_point {\n\tu16 dclk;\n\tu16 t_rp;\n\tu16 t_rdpre;\n\tu16 t_rc;\n\tu16 t_ras;\n\tu16 t_rcd;\n};\n\nstruct intel_qgv_info {\n\tstruct intel_qgv_point points[8];\n\tstruct intel_psf_gv_point psf_points[3];\n\tu8 num_points;\n\tu8 num_psf_points;\n\tu8 t_bl;\n\tu8 max_numchannels;\n\tu8 channel_width;\n\tu8 deinterleave;\n};\n\nstruct intel_quirk {\n\tint device;\n\tint subsystem_vendor;\n\tint subsystem_device;\n\tvoid (*hook)(struct intel_display *);\n};\n\nstruct intel_renderstate_rodata;\n\nstruct intel_renderstate {\n\tstruct i915_gem_ww_ctx ww;\n\tconst struct intel_renderstate_rodata *rodata;\n\tstruct i915_vma *vma;\n\tu32 batch_offset;\n\tu32 batch_size;\n\tu32 aux_offset;\n\tu32 aux_size;\n};\n\nstruct intel_renderstate_rodata {\n\tconst u32 *reloc;\n\tconst u32 *batch;\n\tconst u32 batch_items;\n};\n\nstruct intel_ring {\n\tstruct kref ref;\n\tstruct i915_vma *vma;\n\tvoid *vaddr;\n\tatomic_t pin_count;\n\tu32 head;\n\tu32 tail;\n\tu32 emit;\n\tu32 space;\n\tu32 size;\n\tu32 wrap;\n\tu32 effective_size;\n};\n\nstruct intel_rom {\n\tstruct pci_dev *pdev;\n\tvoid *oprom;\n\tstruct intel_uncore *uncore;\n\tloff_t offset;\n\tsize_t size;\n\tu32 (*read32)(struct intel_rom *, loff_t);\n\tu16 (*read16)(struct intel_rom *, loff_t);\n\tvoid (*read_block)(struct intel_rom *, void *, loff_t, size_t);\n\tvoid (*free)(struct intel_rom *);\n};\n\nstruct intel_rps_freq_caps {\n\tu8 rp0_freq;\n\tu8 rp1_freq;\n\tu8 min_freq;\n};\n\nstruct intel_sa_info {\n\tu16 displayrtids;\n\tu8 deburst;\n\tu8 deprogbwlimit;\n\tu8 derating;\n};\n\nstruct intel_sdvo;\n\nstruct intel_sdvo_ddc {\n\tstruct i2c_adapter ddc;\n\tstruct intel_sdvo *sdvo;\n\tu8 ddc_bus;\n};\n\nstruct intel_sdvo_caps {\n\tu8 vendor_id;\n\tu8 device_id;\n\tu8 device_rev_id;\n\tu8 sdvo_version_major;\n\tu8 sdvo_version_minor;\n\tunsigned int sdvo_num_inputs: 2;\n\tunsigned int smooth_scaling: 1;\n\tunsigned int sharp_scaling: 1;\n\tunsigned int up_scaling: 1;\n\tunsigned int down_scaling: 1;\n\tunsigned int stall_support: 1;\n\tunsigned int pad: 1;\n\tu16 output_flags;\n};\n\nstruct intel_sdvo {\n\tstruct intel_encoder base;\n\tstruct i2c_adapter *i2c;\n\tu8 target_addr;\n\tstruct intel_sdvo_ddc ddc[3];\n\ti915_reg_t sdvo_reg;\n\tstruct intel_sdvo_caps caps;\n\tu8 colorimetry_cap;\n\tint pixel_clock_min;\n\tint pixel_clock_max;\n\tu16 hotplug_active;\n\tu8 dtd_sdvo_flags;\n};\n\nstruct intel_sdvo_connector {\n\tstruct intel_connector base;\n\tu16 output_flag;\n\tu8 tv_format_supported[19];\n\tint format_supported_num;\n\tstruct drm_property *tv_format;\n\tstruct drm_property *left;\n\tstruct drm_property *right;\n\tstruct drm_property *top;\n\tstruct drm_property *bottom;\n\tstruct drm_property *hpos;\n\tstruct drm_property *vpos;\n\tstruct drm_property *contrast;\n\tstruct drm_property *saturation;\n\tstruct drm_property *hue;\n\tstruct drm_property *sharpness;\n\tstruct drm_property *flicker_filter;\n\tstruct drm_property *flicker_filter_adaptive;\n\tstruct drm_property *flicker_filter_2d;\n\tstruct drm_property *tv_chroma_filter;\n\tstruct drm_property *tv_luma_filter;\n\tstruct drm_property *dot_crawl;\n\tstruct drm_property *brightness;\n\tu32 max_hscan;\n\tu32 max_vscan;\n\tbool is_hdmi;\n};\n\nstruct intel_sdvo_connector_state {\n\tstruct intel_digital_connector_state base;\n\tstruct {\n\t\tunsigned int overscan_h;\n\t\tunsigned int overscan_v;\n\t\tunsigned int hpos;\n\t\tunsigned int vpos;\n\t\tunsigned int sharpness;\n\t\tunsigned int flicker_filter;\n\t\tunsigned int flicker_filter_2d;\n\t\tunsigned int flicker_filter_adaptive;\n\t\tunsigned int chroma_filter;\n\t\tunsigned int luma_filter;\n\t\tunsigned int dot_crawl;\n\t} tv;\n};\n\nstruct intel_sdvo_dtd {\n\tstruct {\n\t\tu16 clock;\n\t\tu8 h_active;\n\t\tu8 h_blank;\n\t\tu8 h_high;\n\t\tu8 v_active;\n\t\tu8 v_blank;\n\t\tu8 v_high;\n\t} part1;\n\tstruct {\n\t\tu8 h_sync_off;\n\t\tu8 h_sync_width;\n\t\tu8 v_sync_off_width;\n\t\tu8 sync_off_width_high;\n\t\tu8 dtd_flags;\n\t\tu8 sdvo_flags;\n\t\tu8 v_sync_off_high;\n\t\tu8 reserved;\n\t} part2;\n};\n\nstruct intel_sdvo_encode {\n\tu8 dvi_rev;\n\tu8 hdmi_rev;\n};\n\nstruct intel_sdvo_enhancements_reply {\n\tunsigned int flicker_filter: 1;\n\tunsigned int flicker_filter_adaptive: 1;\n\tunsigned int flicker_filter_2d: 1;\n\tunsigned int saturation: 1;\n\tunsigned int hue: 1;\n\tunsigned int brightness: 1;\n\tunsigned int contrast: 1;\n\tunsigned int overscan_h: 1;\n\tunsigned int overscan_v: 1;\n\tunsigned int hpos: 1;\n\tunsigned int vpos: 1;\n\tunsigned int sharpness: 1;\n\tunsigned int dot_crawl: 1;\n\tunsigned int dither: 1;\n\tunsigned int tv_chroma_filter: 1;\n\tunsigned int tv_luma_filter: 1;\n} __attribute__((packed));\n\nstruct intel_sdvo_get_trained_inputs_response {\n\tunsigned int input0_trained: 1;\n\tunsigned int input1_trained: 1;\n\tunsigned int pad: 6;\n} __attribute__((packed));\n\nstruct intel_sdvo_in_out_map {\n\tu16 in0;\n\tu16 in1;\n};\n\nstruct intel_sdvo_pixel_clock_range {\n\tu16 min;\n\tu16 max;\n};\n\nstruct intel_sdvo_preferred_input_timing_args {\n\tu16 clock;\n\tu16 width;\n\tu16 height;\n\tu8 interlace: 1;\n\tu8 scaled: 1;\n\tu8 pad: 6;\n} __attribute__((packed));\n\nstruct intel_sdvo_sdtv_resolution_request {\n\tunsigned int ntsc_m: 1;\n\tunsigned int ntsc_j: 1;\n\tunsigned int ntsc_443: 1;\n\tunsigned int pal_b: 1;\n\tunsigned int pal_d: 1;\n\tunsigned int pal_g: 1;\n\tunsigned int pal_h: 1;\n\tunsigned int pal_i: 1;\n\tunsigned int pal_m: 1;\n\tunsigned int pal_n: 1;\n\tunsigned int pal_nc: 1;\n\tunsigned int pal_60: 1;\n\tunsigned int secam_b: 1;\n\tunsigned int secam_d: 1;\n\tunsigned int secam_g: 1;\n\tunsigned int secam_k: 1;\n\tunsigned int secam_k1: 1;\n\tunsigned int secam_l: 1;\n\tunsigned int secam_60: 1;\n\tunsigned int pad: 5;\n} __attribute__((packed));\n\nstruct intel_sdvo_set_target_input_args {\n\tunsigned int target_1: 1;\n\tunsigned int pad: 7;\n} __attribute__((packed));\n\nstruct intel_sdvo_tv_format {\n\tunsigned int ntsc_m: 1;\n\tunsigned int ntsc_j: 1;\n\tunsigned int ntsc_443: 1;\n\tunsigned int pal_b: 1;\n\tunsigned int pal_d: 1;\n\tunsigned int pal_g: 1;\n\tunsigned int pal_h: 1;\n\tunsigned int pal_i: 1;\n\tunsigned int pal_m: 1;\n\tunsigned int pal_n: 1;\n\tunsigned int pal_nc: 1;\n\tunsigned int pal_60: 1;\n\tunsigned int secam_b: 1;\n\tunsigned int secam_d: 1;\n\tunsigned int secam_g: 1;\n\tunsigned int secam_k: 1;\n\tunsigned int secam_k1: 1;\n\tunsigned int secam_l: 1;\n\tunsigned int secam_60: 1;\n\tunsigned int hdtv_std_smpte_240m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_240m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_260m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_260m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_50: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_23: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_24: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_25: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_29: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_30: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_50: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_59: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_60: 1;\n\tunsigned int hdtv_std_smpte_295m_1080i_50: 1;\n\tunsigned int hdtv_std_smpte_295m_1080p_50: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_59: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_60: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_50: 1;\n\tunsigned int hdtv_std_smpte_293m_480p_59: 1;\n\tunsigned int hdtv_std_smpte_170m_480i_59: 1;\n\tunsigned int hdtv_std_iturbt601_576i_50: 1;\n\tunsigned int hdtv_std_iturbt601_576p_50: 1;\n\tunsigned int hdtv_std_eia_7702a_480i_60: 1;\n\tunsigned int hdtv_std_eia_7702a_480p_60: 1;\n\tunsigned int pad: 3;\n} __attribute__((packed));\n\nstruct intel_shared_regs {\n\tstruct er_account regs[11];\n\tint refcnt;\n\tunsigned int core_id;\n};\n\nstruct intel_stolen_node {\n\tstruct drm_i915_private *i915;\n\tstruct drm_mm_node node;\n};\n\nstruct intel_tc_phy_ops {\n\tenum intel_display_power_domain (*cold_off_domain)(struct intel_tc_port *);\n\tu32 (*hpd_live_status)(struct intel_tc_port *);\n\tbool (*is_ready)(struct intel_tc_port *);\n\tbool (*is_owned)(struct intel_tc_port *);\n\tvoid (*get_hw_state)(struct intel_tc_port *);\n\tbool (*connect)(struct intel_tc_port *, int);\n\tvoid (*disconnect)(struct intel_tc_port *);\n\tvoid (*init)(struct intel_tc_port *);\n};\n\nstruct intel_tc_port {\n\tstruct intel_digital_port *dig_port;\n\tconst struct intel_tc_phy_ops *phy_ops;\n\tstruct mutex lock;\n\tstruct ref_tracker *lock_wakeref;\n\tstruct delayed_work disconnect_phy_work;\n\tstruct delayed_work link_reset_work;\n\tint link_refcount;\n\tbool legacy_port: 1;\n\tconst char *port_name;\n\tenum tc_port_mode mode;\n\tenum tc_port_mode init_mode;\n\tenum phy_fia phy_fia;\n\tenum intel_tc_pin_assignment pin_assignment;\n\tu8 phy_fia_idx;\n\tu8 max_lane_count;\n};\n\nstruct intel_timeline {\n\tu64 fence_context;\n\tu32 seqno;\n\tstruct mutex mutex;\n\tatomic_t pin_count;\n\tatomic_t active_count;\n\tvoid *hwsp_map;\n\tconst u32 *hwsp_seqno;\n\tstruct i915_vma *hwsp_ggtt;\n\tu32 hwsp_offset;\n\tbool has_initial_breadcrumb;\n\tstruct list_head requests;\n\tstruct i915_active_fence last_request;\n\tstruct i915_active active;\n\tstruct intel_timeline *retire;\n\tstruct i915_syncmap *sync;\n\tstruct list_head link;\n\tstruct intel_gt *gt;\n\tstruct list_head engine_link;\n\tstruct kref kref;\n\tstruct callback_head rcu;\n};\n\nstruct intel_tv {\n\tstruct intel_encoder base;\n\tint type;\n};\n\nstruct intel_tv_connector_state {\n\tstruct drm_connector_state base;\n\tstruct {\n\t\tu16 top;\n\t\tu16 bottom;\n\t} margins;\n\tbool bypass_vfilter;\n};\n\nstruct intel_uc_coredump {\n\tstruct intel_uc_fw guc_fw;\n\tstruct intel_uc_fw huc_fw;\n\tstruct guc_info guc;\n};\n\nstruct intel_uc_ops {\n\tint (*sanitize)(struct intel_uc *);\n\tvoid (*init_fw)(struct intel_uc *);\n\tvoid (*fini_fw)(struct intel_uc *);\n\tint (*init)(struct intel_uc *);\n\tvoid (*fini)(struct intel_uc *);\n\tint (*init_hw)(struct intel_uc *);\n\tvoid (*fini_hw)(struct intel_uc *);\n\tvoid (*resume_mappings)(struct intel_uc *);\n};\n\nstruct intel_uncore_extra_reg {\n\traw_spinlock_t lock;\n\tu64 config;\n\tu64 config1;\n\tu64 config2;\n\tatomic_t ref;\n};\n\nstruct intel_uncore_pmu;\n\nstruct intel_uncore_box {\n\tint dieid;\n\tint n_active;\n\tint n_events;\n\tint cpu;\n\tlong unsigned int flags;\n\tatomic_t refcnt;\n\tstruct perf_event *events[10];\n\tstruct perf_event *event_list[10];\n\tstruct event_constraint *event_constraint[10];\n\tlong unsigned int active_mask[1];\n\tu64 tags[10];\n\tstruct pci_dev *pci_dev;\n\tstruct intel_uncore_pmu *pmu;\n\tu64 hrtimer_duration;\n\tstruct hrtimer hrtimer;\n\tstruct list_head list;\n\tstruct list_head active_list;\n\tvoid *io_addr;\n\tstruct intel_uncore_extra_reg shared_regs[0];\n};\n\nstruct intel_uncore_discovery_type {\n\tstruct rb_node node;\n\tenum uncore_access_type access_type;\n\tstruct rb_root units;\n\tu16 type;\n\tu8 num_counters;\n\tu8 counter_width;\n\tu8 ctl_offset;\n\tu8 ctr_offset;\n\tu16 num_units;\n};\n\nstruct intel_uncore_discovery_unit {\n\tstruct rb_node node;\n\tunsigned int pmu_idx;\n\tunsigned int id;\n\tunsigned int die;\n\tu64 addr;\n};\n\nstruct intel_uncore_forcewake_domain {\n\tstruct intel_uncore *uncore;\n\tenum forcewake_domain_id id;\n\tenum forcewake_domains mask;\n\tunsigned int wake_count;\n\tbool active;\n\tstruct hrtimer timer;\n\tu32 *reg_set;\n\tu32 *reg_ack;\n};\n\nstruct intel_uncore_fw_get {\n\tvoid (*force_wake_get)(struct intel_uncore *, enum forcewake_domains);\n};\n\nstruct intel_uncore_ops {\n\tvoid (*init_box)(struct intel_uncore_box *);\n\tvoid (*exit_box)(struct intel_uncore_box *);\n\tvoid (*disable_box)(struct intel_uncore_box *);\n\tvoid (*enable_box)(struct intel_uncore_box *);\n\tvoid (*disable_event)(struct intel_uncore_box *, struct perf_event *);\n\tvoid (*enable_event)(struct intel_uncore_box *, struct perf_event *);\n\tu64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);\n\tint (*hw_config)(struct intel_uncore_box *, struct perf_event *);\n\tstruct event_constraint * (*get_constraint)(struct intel_uncore_box *, struct perf_event *);\n\tvoid (*put_constraint)(struct intel_uncore_box *, struct perf_event *);\n};\n\nstruct intel_uncore_type;\n\nstruct intel_uncore_pmu {\n\tstruct pmu pmu;\n\tchar name[32];\n\tint pmu_idx;\n\tbool registered;\n\tatomic_t activeboxes;\n\tcpumask_t cpu_mask;\n\tstruct intel_uncore_type *type;\n\tstruct intel_uncore_box **boxes;\n};\n\nstruct uncore_iio_topology;\n\nstruct uncore_upi_topology;\n\nstruct intel_uncore_topology {\n\tint pmu_idx;\n\tunion {\n\t\tvoid *untyped;\n\t\tstruct uncore_iio_topology *iio;\n\t\tstruct uncore_upi_topology *upi;\n\t};\n};\n\nstruct uncore_event_desc;\n\nstruct intel_uncore_type {\n\tconst char *name;\n\tint num_counters;\n\tint num_boxes;\n\tint perf_ctr_bits;\n\tint fixed_ctr_bits;\n\tint num_freerunning_types;\n\tint type_id;\n\tunsigned int perf_ctr;\n\tunsigned int event_ctl;\n\tunsigned int event_mask;\n\tunsigned int event_mask_ext;\n\tunsigned int fixed_ctr;\n\tunsigned int fixed_ctl;\n\tunsigned int box_ctl;\n\tunion {\n\t\tunsigned int msr_offset;\n\t\tunsigned int mmio_offset;\n\t};\n\tunsigned int mmio_map_size;\n\tunsigned int num_shared_regs: 8;\n\tunsigned int single_fixed: 1;\n\tunsigned int pair_ctr_ctl: 1;\n\tunion {\n\t\tu64 *msr_offsets;\n\t\tu64 *pci_offsets;\n\t\tu64 *mmio_offsets;\n\t};\n\tstruct event_constraint unconstrainted;\n\tstruct event_constraint *constraints;\n\tstruct intel_uncore_pmu *pmus;\n\tstruct intel_uncore_ops *ops;\n\tstruct uncore_event_desc *event_descs;\n\tstruct freerunning_counters *freerunning;\n\tconst struct attribute_group *attr_groups[4];\n\tconst struct attribute_group **attr_update;\n\tstruct pmu *pmu;\n\tstruct rb_root *boxes;\n\tstruct intel_uncore_topology **topology;\n\tint (*get_topology)(struct intel_uncore_type *);\n\tvoid (*set_mapping)(struct intel_uncore_type *);\n\tvoid (*cleanup_mapping)(struct intel_uncore_type *);\n\tvoid (*cleanup_extra_boxes)(struct intel_uncore_type *);\n};\n\nstruct intel_vblank_evade_ctx {\n\tstruct intel_crtc *crtc;\n\tint min;\n\tint max;\n\tint vblank_start;\n\tbool need_vlv_dsi_wa;\n};\n\nstruct intel_wakeref_lockclass {\n\tstruct lock_class_key mutex;\n\tstruct lock_class_key work;\n};\n\nstruct intel_wakeref_ops {\n\tint (*get)(struct intel_wakeref *);\n\tint (*put)(struct intel_wakeref *);\n};\n\nstruct intel_watermark_params {\n\tu16 fifo_size;\n\tu16 max_wm;\n\tu8 default_wm;\n\tu8 guard_size;\n\tu8 cacheline_size;\n};\n\nstruct intel_wedge_me {\n\tstruct delayed_work work;\n\tstruct intel_gt *gt;\n\tconst char *name;\n};\n\nstruct intel_wm_config {\n\tunsigned int num_pipes_active;\n\tbool sprites_enabled;\n\tbool sprites_scaled;\n};\n\nstruct intel_wm_funcs {\n\tvoid (*update_wm)(struct intel_display *);\n\tint (*compute_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*initial_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*atomic_update_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*optimize_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tint (*compute_global_watermarks)(struct intel_atomic_state *);\n\tvoid (*get_hw_state)(struct intel_display *);\n\tvoid (*sanitize)(struct intel_display *);\n};\n\nunion intel_x86_pebs_dse {\n\tu64 val;\n\tstruct {\n\t\tunsigned int ld_dse: 4;\n\t\tunsigned int ld_stlb_miss: 1;\n\t\tunsigned int ld_locked: 1;\n\t\tunsigned int ld_data_blk: 1;\n\t\tunsigned int ld_addr_blk: 1;\n\t\tunsigned int ld_reserved: 24;\n\t};\n\tstruct {\n\t\tunsigned int st_l1d_hit: 1;\n\t\tunsigned int st_reserved1: 3;\n\t\tunsigned int st_stlb_miss: 1;\n\t\tunsigned int st_locked: 1;\n\t\tunsigned int st_reserved2: 26;\n\t};\n\tstruct {\n\t\tunsigned int st_lat_dse: 4;\n\t\tunsigned int st_lat_stlb_miss: 1;\n\t\tunsigned int st_lat_locked: 1;\n\t\tunsigned int ld_reserved3: 26;\n\t};\n\tstruct {\n\t\tunsigned int mtl_dse: 5;\n\t\tunsigned int mtl_locked: 1;\n\t\tunsigned int mtl_stlb_miss: 1;\n\t\tunsigned int mtl_fwd_blk: 1;\n\t\tunsigned int ld_reserved4: 24;\n\t};\n\tstruct {\n\t\tunsigned int lnc_dse: 8;\n\t\tunsigned int ld_reserved5: 2;\n\t\tunsigned int lnc_stlb_miss: 1;\n\t\tunsigned int lnc_locked: 1;\n\t\tunsigned int lnc_data_blk: 1;\n\t\tunsigned int lnc_addr_blk: 1;\n\t\tunsigned int ld_reserved6: 18;\n\t};\n\tstruct {\n\t\tunsigned int pnc_dse: 8;\n\t\tunsigned int pnc_l2_miss: 1;\n\t\tunsigned int pnc_stlb_clean_hit: 1;\n\t\tunsigned int pnc_stlb_any_hit: 1;\n\t\tunsigned int pnc_stlb_miss: 1;\n\t\tunsigned int pnc_locked: 1;\n\t\tunsigned int pnc_data_blk: 1;\n\t\tunsigned int pnc_addr_blk: 1;\n\t\tunsigned int pnc_fb_full: 1;\n\t\tunsigned int ld_reserved8: 16;\n\t};\n\tstruct {\n\t\tunsigned int arw_dse: 8;\n\t\tunsigned int arw_l2_miss: 1;\n\t\tunsigned int arw_xq_promotion: 1;\n\t\tunsigned int arw_reissue: 1;\n\t\tunsigned int arw_stlb_miss: 1;\n\t\tunsigned int arw_locked: 1;\n\t\tunsigned int arw_data_blk: 1;\n\t\tunsigned int arw_addr_blk: 1;\n\t\tunsigned int arw_fb_full: 1;\n\t\tunsigned int ld_reserved9: 16;\n\t};\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct io {\n\tlong unsigned int error_bits;\n\tatomic_t count;\n\tstruct dm_io_client *client;\n\tio_notify_fn callback;\n\tvoid *context;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n\tlong: 64;\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct io_apic {\n\tunsigned int index;\n\tunsigned int unused[3];\n\tunsigned int data;\n\tunsigned int unused2[11];\n\tunsigned int eoi;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bitmap {\n\tu64 sequence;\n\trefcount_t refcnt;\n\tunsigned int max;\n\tlong unsigned int bitmap[1024];\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_err_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[1];\n\tlong unsigned int sqe_op[2];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 64;\n\tlong: 64;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tlb_area {\n\tlong unsigned int used;\n\tunsigned int index;\n\tspinlock_t lock;\n};\n\nstruct io_tlb_slot;\n\nstruct io_tlb_pool {\n\tphys_addr_t start;\n\tphys_addr_t end;\n\tvoid *vaddr;\n\tlong unsigned int nslabs;\n\tbool late_alloc;\n\tunsigned int nareas;\n\tunsigned int area_nslabs;\n\tstruct io_tlb_area *areas;\n\tstruct io_tlb_slot *slots;\n};\n\nstruct io_tlb_mem {\n\tstruct io_tlb_pool defpool;\n\tlong unsigned int nslabs;\n\tstruct dentry *debugfs;\n\tbool force_bounce;\n\tbool for_alloc;\n\tatomic_long_t total_used;\n\tatomic_long_t used_hiwater;\n\tatomic_long_t transient_nslabs;\n};\n\nstruct io_tlb_slot {\n\tphys_addr_t orig_addr;\n\tsize_t alloc_size;\n\tshort unsigned int list;\n\tshort unsigned int pad_slots;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_window_t {\n\tu_int InUse;\n\tu_int Config;\n\tstruct resource *res;\n};\n\ntypedef struct io_window_t io_window_t;\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[64];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mpc_ioapic {\n\tunsigned char type;\n\tunsigned char apicid;\n\tunsigned char apicver;\n\tunsigned char flags;\n\tunsigned int apicaddr;\n};\n\nstruct mp_ioapic_gsi {\n\tu32 gsi_base;\n\tu32 gsi_end;\n};\n\nstruct irq_domain_ops;\n\nstruct ioapic_domain_cfg {\n\tenum ioapic_domain_type type;\n\tconst struct irq_domain_ops *ops;\n\tstruct device_node *dev;\n};\n\nstruct ioapic {\n\tint nr_registers;\n\tstruct IO_APIC_route_entry *saved_registers;\n\tstruct mpc_ioapic mp_config;\n\tstruct mp_ioapic_gsi gsi_config;\n\tstruct ioapic_domain_cfg irqdomain_cfg;\n\tstruct irq_domain *irqdomain;\n\tstruct resource *iomem_res;\n};\n\nstruct ioapic_alloc_info {\n\tint pin;\n\tint node;\n\tu32 is_level: 1;\n\tu32 active_low: 1;\n\tu32 valid: 1;\n};\n\nstruct ioc_params {\n\tu32 qos[6];\n\tu64 i_lcoefs[6];\n\tu64 lcoefs[6];\n\tu32 too_fast_vrate_pct;\n\tu32 too_slow_vrate_pct;\n};\n\nstruct ioc_margins {\n\ts64 min;\n\ts64 low;\n\ts64 target;\n};\n\nstruct ioc_pcpu_stat;\n\nstruct ioc {\n\tstruct rq_qos rqos;\n\tbool enabled;\n\tstruct ioc_params params;\n\tstruct ioc_margins margins;\n\tu32 period_us;\n\tu32 timer_slack_ns;\n\tu64 vrate_min;\n\tu64 vrate_max;\n\tspinlock_t lock;\n\tstruct timer_list timer;\n\tstruct list_head active_iocgs;\n\tstruct ioc_pcpu_stat *pcpu_stat;\n\tenum ioc_running running;\n\tatomic64_t vtime_rate;\n\tu64 vtime_base_rate;\n\ts64 vtime_err;\n\tseqcount_spinlock_t period_seqcount;\n\tu64 period_at;\n\tu64 period_at_vtime;\n\tatomic64_t cur_period;\n\tint busy_level;\n\tbool weights_updated;\n\tatomic_t hweight_gen;\n\tu64 dfgv_period_at;\n\tu64 dfgv_period_rem;\n\tu64 dfgv_usage_us_sum;\n\tu64 autop_too_fast_at;\n\tu64 autop_too_slow_at;\n\tint autop_idx;\n\tbool user_qos_params: 1;\n\tbool user_cost_model: 1;\n};\n\nstruct ioc_cgrp {\n\tstruct blkcg_policy_data cpd;\n\tunsigned int dfl_weight;\n};\n\nstruct iocg_stat {\n\tu64 usage_us;\n\tu64 wait_us;\n\tu64 indebt_us;\n\tu64 indelay_us;\n};\n\nstruct iocg_pcpu_stat;\n\nstruct ioc_gq {\n\tstruct blkg_policy_data pd;\n\tstruct ioc *ioc;\n\tu32 cfg_weight;\n\tu32 weight;\n\tu32 active;\n\tu32 inuse;\n\tu32 last_inuse;\n\ts64 saved_margin;\n\tsector_t cursor;\n\tatomic64_t vtime;\n\tatomic64_t done_vtime;\n\tu64 abs_vdebt;\n\tu64 delay;\n\tu64 delay_at;\n\tatomic64_t active_period;\n\tstruct list_head active_list;\n\tu64 child_active_sum;\n\tu64 child_inuse_sum;\n\tu64 child_adjusted_sum;\n\tint hweight_gen;\n\tu32 hweight_active;\n\tu32 hweight_inuse;\n\tu32 hweight_donating;\n\tu32 hweight_after_donation;\n\tstruct list_head walk_list;\n\tstruct list_head surplus_list;\n\tstruct wait_queue_head waitq;\n\tstruct hrtimer waitq_timer;\n\tu64 activated_at;\n\tstruct iocg_pcpu_stat *pcpu_stat;\n\tstruct iocg_stat stat;\n\tstruct iocg_stat last_stat;\n\tu64 last_stat_abs_vusage;\n\tu64 usage_delta_us;\n\tu64 wait_since;\n\tu64 indebt_since;\n\tu64 indelay_since;\n\tint level;\n\tstruct ioc_gq *ancestors[0];\n};\n\nstruct ioc_missed {\n\tlocal_t nr_met;\n\tlocal_t nr_missed;\n\tu32 last_met;\n\tu32 last_missed;\n};\n\nstruct ioc_now {\n\tu64 now_ns;\n\tu64 now;\n\tu64 vnow;\n};\n\nstruct ioc_pcpu_stat {\n\tstruct ioc_missed missed[2];\n\tlocal64_t rq_wait_ns;\n\tu64 last_rq_wait_ns;\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct iocg_pcpu_stat {\n\tlocal64_t abs_vusage;\n};\n\nstruct iocg_wait {\n\tstruct wait_queue_entry wait;\n\tstruct bio *bio;\n\tu64 abs_cost;\n\tbool committed;\n};\n\nstruct iocg_wake_ctx {\n\tstruct ioc_gq *iocg;\n\tu32 hw_inuse;\n\ts64 vbudget;\n};\n\nstruct snd_seq_client;\n\nstruct ioctl_handler {\n\tunsigned int cmd;\n\tint (*func)(struct snd_seq_client *, void *);\n};\n\nstruct percentile_stats {\n\tu64 total;\n\tu64 missed;\n};\n\nstruct latency_stat {\n\tunion {\n\t\tstruct percentile_stats ps;\n\t\tstruct blk_rq_stat rqs;\n\t};\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct iolatency_grp {\n\tstruct blkg_policy_data pd;\n\tstruct latency_stat *stats;\n\tstruct latency_stat cur_stat;\n\tstruct blk_iolatency *blkiolat;\n\tunsigned int max_depth;\n\tstruct rq_wait rq_wait;\n\tatomic64_t window_start;\n\tatomic_t scale_cookie;\n\tu64 min_lat_nsec;\n\tu64 cur_win_nsec;\n\tu64 lat_avg;\n\tu64 nr_samples;\n\tbool ssd;\n\tstruct child_latency_info child_lat;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tstruct bio io_bio;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n};\n\nstruct iommu_attach_handle {\n\tstruct iommu_domain *domain;\n};\n\nstruct iommu_cmd {\n\tu32 data[4];\n};\n\nstruct iommu_dev_data {\n\tstruct mutex mutex;\n\tspinlock_t dte_lock;\n\tstruct list_head list;\n\tstruct llist_node dev_data_list;\n\tstruct protection_domain *domain;\n\tstruct gcr3_tbl_info gcr3_info;\n\tstruct device *dev;\n\tu16 devid;\n\tunsigned int max_irqs;\n\tu32 max_pasids;\n\tu32 flags;\n\tint ats_qdep;\n\tu8 ats_enabled: 1;\n\tu8 pri_enabled: 1;\n\tu8 pasid_enabled: 1;\n\tu8 pri_tlp: 1;\n\tu8 ppr: 1;\n\tbool use_vapic;\n\tbool defer_attach;\n\tstruct ratelimit_state rs;\n};\n\nstruct iova_bitmap;\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_dirty_bitmap {\n\tstruct iova_bitmap *bitmap;\n\tstruct iommu_iotlb_gather *gather;\n};\n\nstruct iommu_dirty_ops {\n\tint (*set_dirty_tracking)(struct iommu_domain *, bool);\n\tint (*read_and_clear_dirty)(struct iommu_domain *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct iova {\n\tstruct rb_node node;\n\tlong unsigned int pfn_hi;\n\tlong unsigned int pfn_lo;\n};\n\nstruct iova_rcache;\n\nstruct iova_domain {\n\tspinlock_t iova_rbtree_lock;\n\tstruct rb_root rbroot;\n\tstruct rb_node *cached_node;\n\tstruct rb_node *cached32_node;\n\tlong unsigned int granule;\n\tlong unsigned int start_pfn;\n\tlong unsigned int dma_32bit_pfn;\n\tlong unsigned int max32_alloc_size;\n\tstruct iova anchor;\n\tstruct iova_rcache *rcaches;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct iommu_dma_options {\n\tenum iommu_dma_queue_type qt;\n\tsize_t fq_size;\n\tunsigned int fq_timeout;\n};\n\nstruct iova_fq;\n\nstruct iommu_dma_cookie {\n\tstruct iova_domain iovad;\n\tstruct list_head msi_page_list;\n\tunion {\n\t\tstruct iova_fq *single_fq;\n\t\tstruct iova_fq *percpu_fq;\n\t};\n\tatomic64_t fq_flush_start_cnt;\n\tatomic64_t fq_flush_finish_cnt;\n\tstruct timer_list fq_timer;\n\tatomic_t fq_timer_on;\n\tstruct iommu_domain *fq_domain;\n\tstruct iommu_dma_options options;\n};\n\nstruct iommu_dma_msi_cookie {\n\tdma_addr_t msi_iova;\n\tstruct list_head msi_page_list;\n};\n\nstruct iommu_dma_msi_page {\n\tstruct list_head list;\n\tdma_addr_t iova;\n\tphys_addr_t phys;\n};\n\nstruct iommu_domain_info {\n\tstruct intel_iommu *iommu;\n\tunsigned int refcnt;\n\tu16 did;\n};\n\nstruct iommu_user_data_array;\n\nstruct iommu_domain_ops {\n\tint (*attach_dev)(struct iommu_domain *, struct device *, struct iommu_domain *);\n\tint (*set_dev_pasid)(struct iommu_domain *, struct device *, ioasid_t, struct iommu_domain *);\n\tint (*map_pages)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct iommu_domain *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tint (*iotlb_sync_map)(struct iommu_domain *, long unsigned int, size_t);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tint (*cache_invalidate_user)(struct iommu_domain *, struct iommu_user_data_array *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tbool (*enforce_cache_coherency)(struct iommu_domain *);\n\tint (*set_pgtable_quirks)(struct iommu_domain *, long unsigned int);\n\tvoid (*free)(struct iommu_domain *);\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iommu_fault_param {\n\tstruct mutex lock;\n\trefcount_t users;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n\tstruct iopf_queue *queue;\n\tstruct list_head queue_list;\n\tstruct list_head partial;\n\tstruct list_head faults;\n};\n\nstruct iommu_fwspec {\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct xarray pasid_array;\n\tstruct mutex mutex;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *blocking_domain;\n\tstruct iommu_domain *resetting_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n\tunsigned int owner_cnt;\n\tvoid *owner;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct iommu_hw_info_vtd {\n\t__u32 flags;\n\t__u32 __reserved;\n\t__u64 cap_reg;\n\t__u64 ecap_reg;\n};\n\nstruct iommu_hwpt_vtd_s1_invalidate {\n\t__u64 addr;\n\t__u64 npages;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct iommu_pages_list {\n\tstruct list_head pages;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n\tstruct iommu_pages_list freelist;\n\tbool queued;\n};\n\nstruct iommu_mm_data {\n\tu32 pasid;\n\tstruct mm_struct *mm;\n\tstruct list_head sva_domains;\n\tstruct list_head mm_list_elm;\n};\n\nstruct iommu_user_data;\n\nstruct of_phandle_args;\n\nstruct iopf_fault;\n\nstruct iommu_page_response;\n\nstruct iommu_ops {\n\tbool (*capable)(struct device *, enum iommu_cap);\n\tvoid * (*hw_info)(struct device *, u32 *, enum iommu_hw_info_type *);\n\tstruct iommu_domain * (*domain_alloc_identity)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_paging_flags)(struct device *, u32, const struct iommu_user_data *);\n\tstruct iommu_domain * (*domain_alloc_paging)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_sva)(struct device *, struct mm_struct *);\n\tstruct iommu_domain * (*domain_alloc_nested)(struct device *, struct iommu_domain *, u32, const struct iommu_user_data *);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tint (*of_xlate)(struct device *, const struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct device *);\n\tvoid (*page_response)(struct device *, struct iopf_fault *, struct iommu_page_response *);\n\tint (*def_domain_type)(struct device *);\n\tsize_t (*get_viommu_size)(struct device *, enum iommu_viommu_type);\n\tint (*viommu_init)(struct iommufd_viommu *, struct iommu_domain *, const struct iommu_user_data *);\n\tconst struct iommu_domain_ops *default_domain_ops;\n\tstruct module *owner;\n\tstruct iommu_domain *identity_domain;\n\tstruct iommu_domain *blocked_domain;\n\tstruct iommu_domain *release_domain;\n\tstruct iommu_domain *default_domain;\n\tu8 user_pasid_table: 1;\n};\n\nstruct iommu_page_response {\n\tu32 pasid;\n\tu32 grpid;\n\tu32 code;\n};\n\nstruct iommu_pmu {\n\tstruct intel_iommu *iommu;\n\tu32 num_cntr;\n\tu32 num_eg;\n\tu32 cntr_width;\n\tu32 cntr_stride;\n\tu32 filter;\n\tvoid *base;\n\tvoid *cfg_reg;\n\tvoid *cntr_reg;\n\tvoid *overflow;\n\tu64 *evcap;\n\tu32 **cntr_evcap;\n\tstruct pmu pmu;\n\tlong unsigned int used_mask[1];\n\tstruct perf_event *event_list[64];\n\tunsigned char irq_name[16];\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n\tvoid (*free)(struct device *, struct iommu_resv_region *);\n};\n\nstruct iommu_sva {\n\tstruct iommu_attach_handle handle;\n\tstruct device *dev;\n\trefcount_t users;\n};\n\nstruct iommu_user_data {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t len;\n};\n\nstruct iommu_user_data_array {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t entry_len;\n\tu32 entry_num;\n};\n\nstruct iommufd_access;\n\nstruct iommufd_hw_queue {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_access *access;\n\tu64 base_addr;\n\tsize_t length;\n\tenum iommu_hw_queue_type type;\n\tvoid (*destroy)(struct iommufd_hw_queue *);\n};\n\nstruct iommufd_device;\n\nstruct iommufd_vdevice {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_device *idev;\n\tu64 virt_id;\n\tvoid (*destroy)(struct iommufd_vdevice *);\n};\n\nstruct iommufd_viommu_ops {\n\tvoid (*destroy)(struct iommufd_viommu *);\n\tstruct iommu_domain * (*alloc_domain_nested)(struct iommufd_viommu *, u32, const struct iommu_user_data *);\n\tint (*cache_invalidate)(struct iommufd_viommu *, struct iommu_user_data_array *);\n\tconst size_t vdevice_size;\n\tint (*vdevice_init)(struct iommufd_vdevice *);\n\tsize_t (*get_hw_queue_size)(struct iommufd_viommu *, enum iommu_hw_queue_type);\n\tint (*hw_queue_init_phys)(struct iommufd_hw_queue *, u32, phys_addr_t);\n};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct iopf_queue {\n\tstruct workqueue_struct *wq;\n\tstruct list_head devices;\n\tstruct mutex lock;\n};\n\nstruct ioprio_blkcg {\n\tstruct blkcg_policy_data cpd;\n\tenum prio_policy prio_policy;\n};\n\nstruct ioptdesc {\n\tlong unsigned int __page_flags;\n\tstruct list_head iopt_freelist_elm;\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tu8 incoherent;\n\t\tlong unsigned int __index;\n\t};\n\tvoid *_private;\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n};\n\nstruct ioremap_desc {\n\tunsigned int flags;\n};\n\nstruct iova_magazine;\n\nstruct iova_cpu_rcache {\n\tspinlock_t lock;\n\tstruct iova_magazine *loaded;\n\tstruct iova_magazine *prev;\n};\n\nstruct iova_fq_entry {\n\tlong unsigned int iova_pfn;\n\tlong unsigned int pages;\n\tstruct iommu_pages_list freelist;\n\tu64 counter;\n};\n\nstruct iova_fq {\n\tspinlock_t lock;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int mod_mask;\n\tstruct iova_fq_entry entries[0];\n};\n\nstruct iova_magazine {\n\tunion {\n\t\tlong unsigned int size;\n\t\tstruct iova_magazine *next;\n\t};\n\tlong unsigned int pfns[127];\n};\n\nstruct iova_rcache {\n\tspinlock_t lock;\n\tunsigned int depot_size;\n\tstruct iova_magazine *depot;\n\tstruct iova_cpu_rcache *cpu_rcaches;\n\tstruct iova_domain *iovad;\n\tstruct delayed_work work;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap;\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 0;\n\tu8 options[0];\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned char __pad1[0];\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\t__kernel_ulong_t __unused1;\n\t__kernel_ulong_t __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tstruct rhashtable key_ht;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_txoptions;\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct uv_alloc_info {\n\tint limit;\n\tint blade;\n\tlong unsigned int offset;\n\tchar *name;\n};\n\nstruct msi_desc;\n\nstruct irq_alloc_info {\n\tenum irq_alloc_type type;\n\tu32 flags;\n\tu32 devid;\n\tirq_hw_number_t hwirq;\n\tconst struct cpumask *mask;\n\tstruct msi_desc *desc;\n\tvoid *data;\n\tunion {\n\t\tstruct ioapic_alloc_info ioapic;\n\t\tstruct uv_alloc_info uv;\n\t};\n};\n\ntypedef struct irq_alloc_info msi_alloc_info_t;\n\nstruct irq_bypass_producer;\n\nstruct irq_bypass_consumer {\n\tstruct eventfd_ctx *eventfd;\n\tstruct irq_bypass_producer *producer;\n\tint (*add_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tvoid (*del_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tvoid (*stop)(struct irq_bypass_consumer *);\n\tvoid (*start)(struct irq_bypass_consumer *);\n};\n\nstruct irq_bypass_producer {\n\tstruct eventfd_ctx *eventfd;\n\tstruct irq_bypass_consumer *consumer;\n\tint irq;\n\tint (*add_consumer)(struct irq_bypass_producer *, struct irq_bypass_consumer *);\n\tvoid (*del_consumer)(struct irq_bypass_producer *, struct irq_bypass_consumer *);\n\tvoid (*stop)(struct irq_bypass_producer *);\n\tvoid (*start)(struct irq_bypass_producer *);\n};\n\nstruct irq_data;\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tunsigned int node;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n\tcpumask_var_t effective_affinity;\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tcpumask_var_t pending_mask;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct hlist_node resend_node;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct irq_desc *vector_irq_t[256];\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec;\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_info {\n\tu8 bus;\n\tu8 devfn;\n\tstruct {\n\t\tu8 link;\n\t\tu16 bitmap;\n\t} __attribute__((packed)) irq[4];\n\tu8 slot;\n\tu8 rfu;\n};\n\nstruct irq_info___2 {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\nstruct irq_matrix {\n\tunsigned int matrix_bits;\n\tunsigned int alloc_start;\n\tunsigned int alloc_end;\n\tunsigned int alloc_size;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int systembits_inalloc;\n\tunsigned int total_allocated;\n\tunsigned int online_maps;\n\tstruct cpumap *maps;\n\tlong unsigned int *system_map;\n\tlong unsigned int scratch_map[0];\n};\n\nstruct irq_override_cmp {\n\tconst struct dmi_system_id *system;\n\tunsigned char irq;\n\tunsigned char triggering;\n\tunsigned char polarity;\n\tunsigned char shareable;\n\tbool override;\n};\n\nstruct irq_pin_list {\n\tstruct list_head list;\n\tint apic;\n\tint pin;\n};\n\nstruct irq_remap_table {\n\traw_spinlock_t lock;\n\tunsigned int min_index;\n\tu32 *table;\n};\n\nstruct irq_router {\n\tchar *name;\n\tu16 vendor;\n\tu16 device;\n\tint (*get)(struct pci_dev *, struct pci_dev *, int);\n\tint (*set)(struct pci_dev *, struct pci_dev *, int, int);\n\tint (*lvl)(struct pci_dev *, struct pci_dev *, int, int);\n};\n\nstruct irq_router_handler {\n\tu16 vendor;\n\tint (*probe)(struct irq_router *, struct pci_dev *, u16);\n};\n\nstruct irq_routing_table {\n\tu32 signature;\n\tu16 version;\n\tu16 size;\n\tu8 rtr_bus;\n\tu8 rtr_devfn;\n\tu16 exclusive_irqs;\n\tu16 rtr_vendor;\n\tu16 rtr_device;\n\tu32 miniport_data;\n\tu8 rfu[11];\n\tu8 checksum;\n\tstruct irq_info slots[0];\n};\n\nstruct irq_stack {\n\tchar stack[16384];\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqentry_state {\n\tunion {\n\t\tbool exit_rcu;\n\t\tbool lockdep;\n\t};\n};\n\ntypedef struct irqentry_state irqentry_state_t;\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct irqtrace_events {\n\tunsigned int irq_events;\n\tlong unsigned int hardirq_enable_ip;\n\tlong unsigned int hardirq_disable_ip;\n\tunsigned int hardirq_enable_event;\n\tunsigned int hardirq_disable_event;\n\tlong unsigned int softirq_disable_ip;\n\tlong unsigned int softirq_enable_ip;\n\tunsigned int softirq_disable_event;\n\tunsigned int softirq_enable_event;\n};\n\nstruct irt_routing_table {\n\tu32 signature;\n\tu8 size;\n\tu8 used;\n\tu16 exclusive_irqs;\n\tstruct irq_info slots[0];\n};\n\nstruct iso_directory_record {\n\t__u8 length[1];\n\t__u8 ext_attr_length[1];\n\t__u8 extent[8];\n\t__u8 size[8];\n\t__u8 date[7];\n\t__u8 flags[1];\n\t__u8 file_unit_size[1];\n\t__u8 interleave[1];\n\t__u8 volume_sequence_number[4];\n\t__u8 name_len[1];\n\tchar name[0];\n};\n\nstruct iso_inode_info {\n\tlong unsigned int i_iget5_block;\n\tlong unsigned int i_iget5_offset;\n\tunsigned int i_first_extent;\n\tunsigned char i_file_format;\n\tunsigned char i_format_parm[3];\n\tlong unsigned int i_next_section_block;\n\tlong unsigned int i_next_section_offset;\n\toff_t i_section_size;\n\tstruct inode vfs_inode;\n};\n\nstruct iso_primary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_supplementary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 flags[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 escape[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_volume_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2041];\n};\n\nstruct isoch_data {\n\tu32 maxbw;\n\tu32 n;\n\tu32 y;\n\tu32 l;\n\tu32 rq;\n\tstruct agp_3_5_dev *dev;\n};\n\nstruct isofs_fid {\n\tu32 block;\n\tu16 offset;\n\tu16 parent_offset;\n\tu32 generation;\n\tu32 parent_block;\n\tu32 parent_generation;\n};\n\nstruct isofs_iget5_callback_data {\n\tlong unsigned int block;\n\tlong unsigned int offset;\n};\n\nstruct isofs_options {\n\tunsigned int rock: 1;\n\tunsigned int joliet: 1;\n\tunsigned int cruft: 1;\n\tunsigned int hide: 1;\n\tunsigned int showassoc: 1;\n\tunsigned int nocompress: 1;\n\tunsigned int overriderockperm: 1;\n\tunsigned int uid_set: 1;\n\tunsigned int gid_set: 1;\n\tunsigned char map;\n\tunsigned char check;\n\tunsigned int blocksize;\n\tumode_t fmode;\n\tumode_t dmode;\n\tkgid_t gid;\n\tkuid_t uid;\n\tchar *iocharset;\n\ts32 session;\n\ts32 sbsector;\n};\n\nstruct nls_table;\n\nstruct isofs_sb_info {\n\tlong unsigned int s_ninodes;\n\tlong unsigned int s_nzones;\n\tlong unsigned int s_firstdatazone;\n\tlong unsigned int s_log_zone_size;\n\tlong unsigned int s_max_size;\n\tint s_rock_offset;\n\ts32 s_sbsector;\n\tunsigned char s_joliet_level;\n\tunsigned char s_mapping;\n\tunsigned char s_check;\n\tunsigned char s_session;\n\tunsigned int s_high_sierra: 1;\n\tunsigned int s_rock: 2;\n\tunsigned int s_cruft: 1;\n\tunsigned int s_nocompress: 1;\n\tunsigned int s_hide: 1;\n\tunsigned int s_showassoc: 1;\n\tunsigned int s_overriderockperm: 1;\n\tunsigned int s_uid_set: 1;\n\tunsigned int s_gid_set: 1;\n\tumode_t s_fmode;\n\tumode_t s_dmode;\n\tkgid_t s_gid;\n\tkuid_t s_uid;\n\tstruct nls_table *s_nls_iocharset;\n};\n\nstruct itco_wdt_platform_data {\n\tchar name[32];\n\tunsigned int version;\n\tbool no_reboot_use_pmc;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct its_array {\n\tvoid **pages;\n\tint num;\n};\n\nstruct ivch_priv {\n\tbool quiet;\n\tu16 width;\n\tu16 height;\n\tu16 reg_backup[24];\n};\n\nstruct ivhd_dte_flags {\n\tstruct list_head list;\n\tu16 segid;\n\tu16 devid_first;\n\tu16 devid_last;\n\tlong: 64;\n\tstruct dev_table_entry dte;\n};\n\nstruct ivhd_entry {\n\tu8 type;\n\tu16 devid;\n\tu8 flags;\n\tunion {\n\t\tstruct {\n\t\t\tu32 ext;\n\t\t\tu32 hidh;\n\t\t};\n\t\tstruct {\n\t\t\tu32 ext;\n\t\t\tu32 hidh;\n\t\t} ext_hid;\n\t};\n\tu64 cid;\n\tu8 uidf;\n\tu8 uidl;\n\tu8 uid;\n} __attribute__((packed));\n\nstruct ivhd_header {\n\tu8 type;\n\tu8 flags;\n\tu16 length;\n\tu16 devid;\n\tu16 cap_ptr;\n\tu64 mmio_phys;\n\tu16 pci_seg;\n\tu16 info;\n\tu32 efr_attr;\n\tu64 efr_reg;\n\tu64 efr_reg2;\n};\n\nstruct ivmd_header {\n\tu8 type;\n\tu8 flags;\n\tu16 length;\n\tu16 devid;\n\tu16 aux;\n\tu16 pci_seg;\n\tu8 resv[6];\n\tu64 range_start;\n\tu64 range_length;\n};\n\nstruct ivrs_quirk_entry {\n\tu8 id;\n\tu32 devid;\n};\n\nstruct iw_node_attr {\n\tstruct kobj_attribute kobj_attr;\n\tint nid;\n};\n\nstruct jit_context {\n\tint cleanup_addr;\n\tint tail_call_direct_label;\n\tint tail_call_indirect_label;\n};\n\nstruct rand_data;\n\nstruct shash_desc;\n\nstruct jitterentropy {\n\tspinlock_t jent_lock;\n\tstruct rand_data *entropy_collector;\n\tstruct crypto_shash *tfm;\n\tstruct shash_desc *sdesc;\n};\n\nstruct jump_entry {\n\ts32 code;\n\ts32 target;\n\tlong int key;\n};\n\nstruct jump_label_patch {\n\tconst void *code;\n\tint size;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\ntypedef void __restorefn_t(void);\n\ntypedef __restorefn_t *__sigrestore_t;\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[56];\n\tint exported;\n\tint show_value;\n};\n\nstruct kallsyms_data {\n\tlong unsigned int *addrs;\n\tconst char **syms;\n\tsize_t cnt;\n\tsize_t found;\n};\n\nstruct karatsuba_ctx {\n\tstruct karatsuba_ctx *next;\n\tmpi_ptr_t tspace;\n\tmpi_size_t tspace_size;\n\tmpi_ptr_t tp;\n\tmpi_size_t tp_size;\n};\n\nstruct kaslr_memory_region {\n\tlong unsigned int *base;\n\tlong unsigned int *end;\n\tlong unsigned int size_tb;\n};\n\nstruct led_trigger {\n\tconst char *name;\n\tint (*activate)(struct led_classdev *);\n\tvoid (*deactivate)(struct led_classdev *);\n\tenum led_brightness brightness;\n\tstruct led_hw_trigger_type *trigger_type;\n\tspinlock_t leddev_list_lock;\n\tstruct list_head led_cdevs;\n\tstruct list_head next_trig;\n\tconst struct attribute_group **groups;\n};\n\nstruct kbd_led_trigger {\n\tstruct led_trigger trigger;\n\tunsigned int mask;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tint: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcmp_epoll_slot {\n\t__u32 efd;\n\t__u32 tfd;\n\t__u32 toff;\n};\n\ntypedef void (*dm_kcopyd_notify_fn)(int, long unsigned int, void *);\n\nstruct kcopyd_job {\n\tstruct dm_kcopyd_client *kc;\n\tstruct list_head list;\n\tunsigned int flags;\n\tint read_err;\n\tlong unsigned int write_err;\n\tenum req_op op;\n\tstruct dm_io_region source;\n\tunsigned int num_dests;\n\tstruct dm_io_region dests[8];\n\tstruct page_list *pages;\n\tdm_kcopyd_notify_fn fn;\n\tvoid *context;\n\tstruct mutex lock;\n\tatomic_t sub_jobs;\n\tsector_t progress;\n\tsector_t write_offset;\n\tstruct kcopyd_job *master_job;\n};\n\nstruct kcore_list {\n\tstruct list_head list;\n\tlong unsigned int addr;\n\tsize_t size;\n\tint type;\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[11];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tint value_offset;\n\tint name_offset;\n\tint namespace_offset;\n};\n\nstruct kernel_vm86_regs {\n\tstruct pt_regs pt;\n\tshort unsigned int es;\n\tshort unsigned int __esh;\n\tshort unsigned int ds;\n\tshort unsigned int __dsh;\n\tshort unsigned int fs;\n\tshort unsigned int __fsh;\n\tshort unsigned int gs;\n\tshort unsigned int __gsh;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[1024];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct lockdep_map dep_map;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct kexec_link_entry {\n\tconst char *target;\n\tconst char *name;\n};\n\nstruct kexec_load_limit {\n\tstruct mutex mutex;\n\tint limit;\n};\n\nstruct kexec_segment {\n\tunion {\n\t\tvoid *buf;\n\t\tvoid *kbuf;\n\t};\n\tsize_t bufsz;\n\tlong unsigned int mem;\n\tsize_t memsz;\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[6];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_entry {\n\tint type;\n\tu32 code;\n\tunion {\n\t\tu16 keycode;\n\t\tstruct {\n\t\t\tu8 code;\n\t\t\tu8 value;\n\t\t} sw;\n\t};\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\ttime64_t now;\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct kho_data {\n\t__u64 fdt_addr;\n\t__u64 fdt_size;\n\t__u64 scratch_addr;\n\t__u64 scratch_size;\n};\n\nstruct kimage_arch {\n\tpgd_t *pgd;\n\tp4d_t *p4d;\n\tpud_t *pud;\n\tpmd_t *pmd;\n\tpte_t *pte;\n};\n\nstruct kimage {\n\tkimage_entry_t head;\n\tkimage_entry_t *entry;\n\tkimage_entry_t *last_entry;\n\tlong unsigned int start;\n\tstruct page *control_code_page;\n\tstruct page *swap_page;\n\tvoid *vmcoreinfo_data_copy;\n\tlong unsigned int nr_segments;\n\tstruct kexec_segment segment[16];\n\tstruct page *segment_cma[16];\n\tstruct list_head control_pages;\n\tstruct list_head dest_pages;\n\tstruct list_head unusable_pages;\n\tlong unsigned int control_page;\n\tunsigned int type: 1;\n\tunsigned int preserve_context: 1;\n\tunsigned int file_mode: 1;\n\tunsigned int hotplug_support: 1;\n\tunsigned int no_cma: 1;\n\tstruct kimage_arch arch;\n\tint hp_action;\n\tint elfcorehdr_index;\n\tbool elfcorehdr_updated;\n\tstruct {\n\t\tstruct kexec_segment *scratch;\n\t\tphys_addr_t fdt;\n\t} kho;\n\tvoid *elf_headers;\n\tlong unsigned int elf_headers_sz;\n\tlong unsigned int elf_load_addr;\n\tlong unsigned int dm_crypt_keys_addr;\n\tlong unsigned int dm_crypt_keys_sz;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[3];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {};\n\ntypedef struct kmem_cache *kmem_buckets[14];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tunsigned int remote_node_defrag_ratio;\n\tstruct kmem_cache_node *node[64];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct kobj_engine {\n\tstruct kobject base;\n\tstruct intel_engine_cs *engine;\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kpp_request;\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tstruct crypto_alg base;\n};\n\nstruct kpp_instance {\n\tvoid (*free)(struct kpp_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[48];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct kpp_alg alg;\n\t};\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct kprobe_blacklist_entry {\n\tstruct list_head list;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n};\n\nstruct prev_kprobe {\n\tstruct kprobe *kp;\n\tlong unsigned int status;\n\tlong unsigned int old_flags;\n\tlong unsigned int saved_flags;\n};\n\nstruct kprobe_ctlblk {\n\tlong unsigned int kprobe_status;\n\tlong unsigned int kprobe_old_flags;\n\tlong unsigned int kprobe_saved_flags;\n\tstruct prev_kprobe prev_kprobe;\n};\n\nstruct kprobe_insn_cache {\n\tstruct mutex mutex;\n\tvoid * (*alloc)(void);\n\tvoid (*free)(void *);\n\tconst char *sym;\n\tstruct list_head pages;\n\tsize_t insn_size;\n\tint nr_garbage;\n};\n\nstruct kprobe_insn_page {\n\tstruct list_head list;\n\tkprobe_opcode_t *insns;\n\tstruct kprobe_insn_cache *cache;\n\tint nused;\n\tint ngarbage;\n\tchar slot_used[0];\n};\n\nstruct kprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n};\n\nstruct kretprobe_instance;\n\ntypedef int (*kretprobe_handler_t)(struct kretprobe_instance *, struct pt_regs *);\n\nstruct rethook;\n\nstruct kretprobe {\n\tstruct kprobe kp;\n\tkretprobe_handler_t handler;\n\tkretprobe_handler_t entry_handler;\n\tint maxactive;\n\tint nmissed;\n\tsize_t data_size;\n\tstruct rethook *rh;\n};\n\nstruct kretprobe_blackpoint {\n\tconst char *name;\n\tvoid *addr;\n};\n\nstruct rethook_node {\n\tstruct callback_head rcu;\n\tstruct llist_node llist;\n\tstruct rethook *rethook;\n\tlong unsigned int ret_addr;\n\tlong unsigned int frame;\n};\n\nstruct kretprobe_instance {\n\tstruct rethook_node node;\n\tchar data[0];\n};\n\nstruct kretprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int func;\n\tlong unsigned int ret_ip;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kvm_memslots {\n\tu64 generation;\n\tatomic_long_t last_used_slot;\n\tstruct rb_root_cached hva_tree;\n\tstruct rb_root gfn_tree;\n\tstruct hlist_head id_hash[128];\n\tint node_idx;\n};\n\nstruct kvm_vm_stat_generic {\n\tu64 remote_tlb_flush;\n\tu64 remote_tlb_flush_requests;\n};\n\nstruct kvm_vm_stat {\n\tstruct kvm_vm_stat_generic generic;\n\tu64 mmu_shadow_zapped;\n\tu64 mmu_pte_write;\n\tu64 mmu_pde_zapped;\n\tu64 mmu_flooded;\n\tu64 mmu_recycled;\n\tu64 mmu_cache_miss;\n\tu64 mmu_unsync;\n\tunion {\n\t\tstruct {\n\t\t\tatomic64_t pages_4k;\n\t\t\tatomic64_t pages_2m;\n\t\t\tatomic64_t pages_1g;\n\t\t};\n\t\tatomic64_t pages[3];\n\t};\n\tu64 nx_lpage_splits;\n\tu64 max_mmu_page_hash_collisions;\n\tu64 max_mmu_rmap_size;\n};\n\nstruct kvm_possible_nx_huge_pages {\n\tstruct list_head pages;\n\tu64 nr_pages;\n};\n\nstruct ms_hyperv_tsc_page {\n\tvolatile u32 tsc_sequence;\n\tu32 reserved1;\n\tvolatile u64 tsc_scale;\n\tvolatile s64 tsc_offset;\n};\n\nstruct kvm_hv_syndbg {\n\tstruct {\n\t\tu64 control;\n\t\tu64 status;\n\t\tu64 send_page;\n\t\tu64 recv_page;\n\t\tu64 pending_page;\n\t} control;\n\tu64 options;\n};\n\nstruct kvm_hv {\n\tstruct mutex hv_lock;\n\tu64 hv_guest_os_id;\n\tu64 hv_hypercall;\n\tu64 hv_tsc_page;\n\tenum hv_tsc_page_status hv_tsc_page_status;\n\tu64 hv_crash_param[5];\n\tu64 hv_crash_ctl;\n\tstruct ms_hyperv_tsc_page tsc_ref;\n\tstruct idr conn_to_evt;\n\tu64 hv_reenlightenment_control;\n\tu64 hv_tsc_emulation_control;\n\tu64 hv_tsc_emulation_status;\n\tu64 hv_invtsc_control;\n\tatomic_t num_mismatched_vp_indexes;\n\tunsigned int synic_auto_eoi_used;\n\tstruct kvm_hv_syndbg hv_syndbg;\n\tbool xsaves_xsavec_checked;\n};\n\nstruct once {\n\tatomic_t state;\n\tstruct mutex lock;\n};\n\nstruct kvm_mmu_memory_cache {\n\tgfp_t gfp_zero;\n\tgfp_t gfp_custom;\n\tu64 init_value;\n\tstruct kmem_cache *kmem_cache;\n\tint capacity;\n\tint nobjs;\n\tvoid **objects;\n};\n\nstruct kvm_pic;\n\nstruct kvm_ioapic;\n\nstruct kvm_pit;\n\nstruct kvm_apic_map;\n\nstruct kvm_x86_msr_filter;\n\nstruct kvm_x86_pmu_event_filter;\n\nstruct vhost_task;\n\nstruct kvm_arch {\n\tlong unsigned int n_used_mmu_pages;\n\tlong unsigned int n_requested_mmu_pages;\n\tlong unsigned int n_max_mmu_pages;\n\tunsigned int indirect_shadow_pages;\n\tu8 mmu_valid_gen;\n\tu8 vm_type;\n\tbool has_private_mem;\n\tbool has_protected_state;\n\tbool has_protected_eoi;\n\tbool pre_fault_allowed;\n\tstruct hlist_head *mmu_page_hash;\n\tstruct list_head active_mmu_pages;\n\tstruct kvm_possible_nx_huge_pages possible_nx_huge_pages[2];\n\tspinlock_t mmu_unsync_pages_lock;\n\tu64 shadow_mmio_value;\n\tatomic_t noncoherent_dma_count;\n\tlong unsigned int nr_possible_bypass_irqs;\n\tstruct kvm_pic *vpic;\n\tstruct kvm_ioapic *vioapic;\n\tstruct kvm_pit *vpit;\n\tatomic_t vapics_in_nmi_mode;\n\tstruct mutex apic_map_lock;\n\tstruct kvm_apic_map *apic_map;\n\tatomic_t apic_map_dirty;\n\tbool apic_access_memslot_enabled;\n\tbool apic_access_memslot_inhibited;\n\tstruct rw_semaphore apicv_update_lock;\n\tlong unsigned int apicv_inhibit_reasons;\n\tgpa_t wall_clock;\n\tu64 disabled_exits;\n\ts64 kvmclock_offset;\n\traw_spinlock_t tsc_write_lock;\n\tu64 last_tsc_nsec;\n\tu64 last_tsc_write;\n\tu32 last_tsc_khz;\n\tu64 last_tsc_offset;\n\tu64 cur_tsc_nsec;\n\tu64 cur_tsc_write;\n\tu64 cur_tsc_offset;\n\tu64 cur_tsc_generation;\n\tint nr_vcpus_matched_tsc;\n\tu32 default_tsc_khz;\n\tbool user_set_tsc;\n\tu64 apic_bus_cycle_ns;\n\tseqcount_raw_spinlock_t pvclock_sc;\n\tbool use_master_clock;\n\tu64 master_kernel_ns;\n\tu64 master_cycle_now;\n\tstruct kvm_hv hyperv;\n\tbool backwards_tsc_observed;\n\tbool boot_vcpu_runs_old_kvmclock;\n\tu32 bsp_vcpu_id;\n\tu64 disabled_quirks;\n\tenum kvm_irqchip_mode irqchip_mode;\n\tu8 nr_reserved_ioapic_pins;\n\tbool disabled_lapic_found;\n\tbool x2apic_format;\n\tbool x2apic_broadcast_quirk_disabled;\n\tenum kvm_suppress_eoi_broadcast_mode suppress_eoi_broadcast_mode;\n\tbool has_mapped_host_mmio;\n\tbool guest_can_read_msr_platform_info;\n\tbool exception_payload_enabled;\n\tbool triple_fault_event;\n\tbool bus_lock_detection_enabled;\n\tbool enable_pmu;\n\tbool created_mediated_pmu;\n\tu32 notify_window;\n\tu32 notify_vmexit_flags;\n\tbool exit_on_emulation_error;\n\tu32 user_space_msr_mask;\n\tstruct kvm_x86_msr_filter *msr_filter;\n\tu32 hypercall_exit_enabled;\n\tbool sgx_provisioning_allowed;\n\tstruct kvm_x86_pmu_event_filter *pmu_event_filter;\n\tstruct vhost_task *nx_huge_page_recovery_thread;\n\tu64 nx_huge_page_last;\n\tstruct once nx_once;\n\tstruct list_head tdp_mmu_roots;\n\tspinlock_t tdp_mmu_pages_lock;\n\tbool shadow_root_allocated;\n\tu32 max_vcpu_ids;\n\tbool disable_nx_huge_pages;\n\tstruct kvm_mmu_memory_cache split_shadow_page_cache;\n\tstruct kvm_mmu_memory_cache split_page_header_cache;\n\tstruct kvm_mmu_memory_cache split_desc_cache;\n\tgfn_t gfn_direct_bits;\n\tint cpu_dirty_log_size;\n};\n\nstruct kvm_io_bus;\n\nstruct kvm_coalesced_mmio_ring;\n\nstruct kvm_irq_routing_table;\n\nstruct kvm_stat_data;\n\nstruct kvm {\n\trwlock_t mmu_lock;\n\tstruct mutex slots_lock;\n\tstruct mutex slots_arch_lock;\n\tstruct mm_struct *mm;\n\tlong unsigned int nr_memslot_pages;\n\tstruct kvm_memslots __memslots[4];\n\tstruct kvm_memslots *memslots[2];\n\tstruct xarray vcpu_array;\n\tatomic_t nr_memslots_dirty_logging;\n\tspinlock_t mn_invalidate_lock;\n\tlong unsigned int mn_active_invalidate_count;\n\tstruct rcuwait mn_memslots_update_rcuwait;\n\tspinlock_t gpc_lock;\n\tstruct list_head gpc_list;\n\tatomic_t online_vcpus;\n\tint max_vcpus;\n\tint created_vcpus;\n\tint last_boosted_vcpu;\n\tstruct list_head vm_list;\n\tstruct mutex lock;\n\tstruct kvm_io_bus *buses[5];\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head items;\n\t\tstruct list_head resampler_list;\n\t\tstruct mutex resampler_lock;\n\t} irqfds;\n\tstruct list_head ioeventfds;\n\tstruct kvm_vm_stat stat;\n\tstruct kvm_arch arch;\n\trefcount_t users_count;\n\tstruct kvm_coalesced_mmio_ring *coalesced_mmio_ring;\n\tspinlock_t ring_lock;\n\tstruct list_head coalesced_zones;\n\tstruct mutex irq_lock;\n\tstruct kvm_irq_routing_table *irq_routing;\n\tstruct hlist_head irq_ack_notifier_list;\n\tstruct mmu_notifier mmu_notifier;\n\tlong unsigned int mmu_invalidate_seq;\n\tlong int mmu_invalidate_in_progress;\n\tgfn_t mmu_invalidate_range_start;\n\tgfn_t mmu_invalidate_range_end;\n\tstruct list_head devices;\n\tu64 manual_dirty_log_protect;\n\tstruct dentry *debugfs_dentry;\n\tstruct kvm_stat_data **debugfs_stat_data;\n\tstruct srcu_struct srcu;\n\tstruct srcu_struct irq_srcu;\n\tpid_t userspace_pid;\n\tbool override_halt_poll_ns;\n\tunsigned int max_halt_poll_ns;\n\tu32 dirty_ring_size;\n\tbool dirty_ring_with_bitmap;\n\tbool vm_bugged;\n\tbool vm_dead;\n\tstruct notifier_block pm_notifier;\n\tchar stats_id[48];\n};\n\nstruct kvm_lapic;\n\nstruct kvm_apic_map {\n\tstruct callback_head rcu;\n\tenum kvm_apic_logical_mode logical_mode;\n\tu32 max_apic_id;\n\tunion {\n\t\tstruct kvm_lapic *xapic_flat_map[8];\n\t\tstruct kvm_lapic *xapic_cluster_map[64];\n\t};\n\tstruct kvm_lapic *phys_map[0];\n};\n\nstruct kvm_arch_async_pf {\n\tu32 token;\n\tgfn_t gfn;\n\tlong unsigned int cr3;\n\tbool direct_map;\n\tu64 error_code;\n};\n\nstruct kvm_rmap_head;\n\nstruct kvm_lpage_info;\n\nstruct kvm_arch_memory_slot {\n\tstruct kvm_rmap_head *rmap[3];\n\tstruct kvm_lpage_info *lpage_info[2];\n\tshort unsigned int *gfn_write_track;\n};\n\nstruct kvm_vcpu;\n\nstruct kvm_async_pf {\n\tstruct work_struct work;\n\tstruct list_head link;\n\tstruct list_head queue;\n\tstruct kvm_vcpu *vcpu;\n\tgpa_t cr2_or_gpa;\n\tlong unsigned int addr;\n\tstruct kvm_arch_async_pf arch;\n\tbool wakeup_all;\n\tbool notpresent_injected;\n};\n\nstruct kvm_caps {\n\tbool has_tsc_control;\n\tu32 max_guest_tsc_khz;\n\tu8 tsc_scaling_ratio_frac_bits;\n\tu64 max_tsc_scaling_ratio;\n\tu64 default_tsc_scaling_ratio;\n\tbool has_bus_lock_exit;\n\tbool has_notify_vmexit;\n\tu32 supported_vm_types;\n\tu64 supported_mce_cap;\n\tu64 supported_xcr0;\n\tu64 supported_xss;\n\tu64 supported_perf_cap;\n\tu64 supported_quirks;\n\tu64 inapplicable_quirks;\n};\n\nstruct kvm_clear_dirty_log {\n\t__u32 slot;\n\t__u32 num_pages;\n\t__u64 first_page;\n\tunion {\n\t\tvoid *dirty_bitmap;\n\t\t__u64 padding2;\n\t};\n};\n\nstruct kvm_clock_data {\n\t__u64 clock;\n\t__u32 flags;\n\t__u32 pad0;\n\t__u64 realtime;\n\t__u64 host_tsc;\n\t__u32 pad[4];\n};\n\nstruct kvm_clock_pairing {\n\t__s64 sec;\n\t__s64 nsec;\n\t__u64 tsc;\n\t__u32 flags;\n\t__u32 pad[9];\n};\n\nstruct kvm_coalesced_mmio {\n\t__u64 phys_addr;\n\t__u32 len;\n\tunion {\n\t\t__u32 pad;\n\t\t__u32 pio;\n\t};\n\t__u8 data[8];\n};\n\nstruct kvm_coalesced_mmio_zone {\n\t__u64 addr;\n\t__u32 size;\n\tunion {\n\t\t__u32 pad;\n\t\t__u32 pio;\n\t};\n};\n\nstruct kvm_coalesced_mmio_dev {\n\tstruct list_head list;\n\tstruct kvm_io_device dev;\n\tstruct kvm *kvm;\n\tstruct kvm_coalesced_mmio_zone zone;\n};\n\nstruct kvm_coalesced_mmio_ring {\n\t__u32 first;\n\t__u32 last;\n\tstruct kvm_coalesced_mmio coalesced_mmio[0];\n};\n\nunion kvm_mmu_page_role {\n\tu32 word;\n\tstruct {\n\t\tunsigned int level: 4;\n\t\tunsigned int has_4_byte_gpte: 1;\n\t\tunsigned int quadrant: 2;\n\t\tunsigned int direct: 1;\n\t\tunsigned int access: 3;\n\t\tunsigned int invalid: 1;\n\t\tunsigned int efer_nx: 1;\n\t\tunsigned int cr0_wp: 1;\n\t\tunsigned int smep_andnot_wp: 1;\n\t\tunsigned int smap_andnot_wp: 1;\n\t\tunsigned int ad_disabled: 1;\n\t\tunsigned int guest_mode: 1;\n\t\tunsigned int passthrough: 1;\n\t\tunsigned int is_mirror: 1;\n\t\tchar: 4;\n\t\tunsigned int smm: 8;\n\t};\n};\n\nunion kvm_mmu_extended_role {\n\tu32 word;\n\tstruct {\n\t\tunsigned int valid: 1;\n\t\tunsigned int execonly: 1;\n\t\tunsigned int cr4_pse: 1;\n\t\tunsigned int cr4_pke: 1;\n\t\tunsigned int cr4_smap: 1;\n\t\tunsigned int cr4_smep: 1;\n\t\tunsigned int cr4_la57: 1;\n\t\tunsigned int efer_lma: 1;\n\t};\n};\n\nunion kvm_cpu_role {\n\tu64 as_u64;\n\tstruct {\n\t\tunion kvm_mmu_page_role base;\n\t\tunion kvm_mmu_extended_role ext;\n\t};\n};\n\nstruct kvm_cpuid_entry {\n\t__u32 function;\n\t__u32 eax;\n\t__u32 ebx;\n\t__u32 ecx;\n\t__u32 edx;\n\t__u32 padding;\n};\n\nstruct kvm_cpuid {\n\t__u32 nent;\n\t__u32 padding;\n\tstruct kvm_cpuid_entry entries[0];\n};\n\nstruct kvm_cpuid_entry2 {\n\t__u32 function;\n\t__u32 index;\n\t__u32 flags;\n\t__u32 eax;\n\t__u32 ebx;\n\t__u32 ecx;\n\t__u32 edx;\n\t__u32 padding[3];\n};\n\nstruct kvm_cpuid2 {\n\t__u32 nent;\n\t__u32 padding;\n\tstruct kvm_cpuid_entry2 entries[0];\n};\n\nstruct kvm_cpuid_array {\n\tstruct kvm_cpuid_entry2 *entries;\n\tint maxnent;\n\tint nent;\n};\n\nstruct kvm_create_device {\n\t__u32 type;\n\t__u32 fd;\n\t__u32 flags;\n};\n\nstruct kvm_create_guest_memfd {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 reserved[6];\n};\n\nstruct kvm_debug_exit_arch {\n\t__u32 exception;\n\t__u32 pad;\n\t__u64 pc;\n\t__u64 dr6;\n\t__u64 dr7;\n};\n\nstruct kvm_debugregs {\n\t__u64 db[4];\n\t__u64 dr6;\n\t__u64 dr7;\n\t__u64 flags;\n\t__u64 reserved[9];\n};\n\nstruct kvm_device_ops;\n\nstruct kvm_device {\n\tconst struct kvm_device_ops *ops;\n\tstruct kvm *kvm;\n\tvoid *private;\n\tstruct list_head vm_node;\n};\n\nstruct kvm_device_attr {\n\t__u32 flags;\n\t__u32 group;\n\t__u64 attr;\n\t__u64 addr;\n};\n\nstruct kvm_device_ops {\n\tconst char *name;\n\tint (*create)(struct kvm_device *, u32);\n\tvoid (*init)(struct kvm_device *);\n\tvoid (*destroy)(struct kvm_device *);\n\tvoid (*release)(struct kvm_device *);\n\tint (*set_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*get_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*has_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tlong int (*ioctl)(struct kvm_device *, unsigned int, long unsigned int);\n\tint (*mmap)(struct kvm_device *, struct vm_area_struct *);\n};\n\nstruct kvm_dirty_gfn {\n\t__u32 flags;\n\t__u32 slot;\n\t__u64 offset;\n};\n\nstruct kvm_dirty_log {\n\t__u32 slot;\n\t__u32 padding1;\n\tunion {\n\t\tvoid *dirty_bitmap;\n\t\t__u64 padding2;\n\t};\n};\n\nstruct kvm_dirty_ring {\n\tu32 dirty_index;\n\tu32 reset_index;\n\tu32 size;\n\tu32 soft_limit;\n\tstruct kvm_dirty_gfn *dirty_gfns;\n\tint index;\n};\n\nstruct kvm_dtable {\n\t__u64 base;\n\t__u16 limit;\n\t__u16 padding[3];\n};\n\nstruct kvm_enable_cap {\n\t__u32 cap;\n\t__u32 flags;\n\t__u64 args[4];\n\t__u8 pad[64];\n};\n\nstruct kvm_enc_region {\n\t__u64 addr;\n\t__u64 size;\n};\n\nstruct kvm_exit_snp_req_certs {\n\t__u64 gpa;\n\t__u64 npages;\n\t__u64 ret;\n};\n\nstruct kvm_follow_pfn {\n\tconst struct kvm_memory_slot *slot;\n\tconst gfn_t gfn;\n\tlong unsigned int hva;\n\tunsigned int flags;\n\tbool pin;\n\tbool *map_writable;\n\tstruct page **refcounted_page;\n};\n\nstruct kvm_fpu {\n\t__u8 fpr[128];\n\t__u16 fcw;\n\t__u16 fsw;\n\t__u8 ftwx;\n\t__u8 pad1;\n\t__u16 last_opcode;\n\t__u64 last_ip;\n\t__u64 last_dp;\n\t__u8 xmm[256];\n\t__u32 mxcsr;\n\t__u32 pad2;\n};\n\nunion kvm_mmu_notifier_arg {\n\tlong unsigned int attributes;\n};\n\nstruct kvm_gfn_range {\n\tstruct kvm_memory_slot *slot;\n\tgfn_t start;\n\tgfn_t end;\n\tunion kvm_mmu_notifier_arg arg;\n\tenum kvm_gfn_range_filter attr_filter;\n\tbool may_block;\n\tbool lockless;\n};\n\nstruct kvm_guest_debug_arch {\n\t__u64 debugreg[8];\n};\n\nstruct kvm_guest_debug {\n\t__u32 control;\n\t__u32 pad;\n\tstruct kvm_guest_debug_arch arch;\n};\n\nstruct kvm_host_map {\n\tstruct page *pinned_page;\n\tstruct page *page;\n\tvoid *hva;\n\tkvm_pfn_t pfn;\n\tkvm_pfn_t gfn;\n\tbool writable;\n};\n\nstruct kvm_host_values {\n\tu8 maxphyaddr;\n\tu64 efer;\n\tu64 xcr0;\n\tu64 xss;\n\tu64 s_cet;\n\tu64 arch_capabilities;\n};\n\nstruct kvm_hv_hcall {\n\tu64 param;\n\tu64 ingpa;\n\tu64 outgpa;\n\tu16 code;\n\tu16 var_cnt;\n\tu16 rep_cnt;\n\tu16 rep_idx;\n\tbool fast;\n\tbool rep;\n\tlong: 64;\n\tsse128_t xmm[6];\n\tunion {\n\t\tgpa_t data_offset;\n\t\tint consumed_xmm_halves;\n\t};\n\tlong: 64;\n};\n\nstruct kvm_hv_sint {\n\tu32 vcpu;\n\tu32 sint;\n};\n\nstruct kvm_hyperv_eventfd {\n\t__u32 conn_id;\n\t__s32 fd;\n\t__u32 flags;\n\t__u32 padding[3];\n};\n\nstruct kvm_hyperv_exit {\n\t__u32 type;\n\t__u32 pad1;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 evt_page;\n\t\t\t__u64 msg_page;\n\t\t} synic;\n\t\tstruct {\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[2];\n\t\t} hcall;\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 status;\n\t\t\t__u64 send_page;\n\t\t\t__u64 recv_page;\n\t\t\t__u64 pending_page;\n\t\t} syndbg;\n\t} u;\n};\n\nstruct kvm_hypervisor_cpuid {\n\tu32 base;\n\tu32 limit;\n};\n\nstruct kvm_interrupt {\n\t__u32 irq;\n};\n\nstruct kvm_io_range {\n\tgpa_t addr;\n\tint len;\n\tstruct kvm_io_device *dev;\n};\n\nstruct kvm_io_bus {\n\tint dev_count;\n\tint ioeventfd_count;\n\tstruct callback_head rcu;\n\tstruct kvm_io_range range[0];\n};\n\nstruct kvm_io_device_ops {\n\tint (*read)(struct kvm_vcpu *, struct kvm_io_device *, gpa_t, int, void *);\n\tint (*write)(struct kvm_vcpu *, struct kvm_io_device *, gpa_t, int, const void *);\n\tvoid (*destructor)(struct kvm_io_device *);\n};\n\nunion kvm_ioapic_redirect_entry {\n\tu64 bits;\n\tstruct {\n\t\tu8 vector;\n\t\tu8 delivery_mode: 3;\n\t\tu8 dest_mode: 1;\n\t\tu8 delivery_status: 1;\n\t\tu8 polarity: 1;\n\t\tu8 remote_irr: 1;\n\t\tu8 trig_mode: 1;\n\t\tu8 mask: 1;\n\t\tu8 reserve: 7;\n\t\tu8 reserved[4];\n\t\tu8 dest_id;\n\t} fields;\n};\n\nstruct rtc_status {\n\tint pending_eoi;\n\tlong unsigned int map[64];\n\tu8 vectors[4096];\n};\n\nstruct kvm_ioapic {\n\tu64 base_address;\n\tu32 ioregsel;\n\tu32 id;\n\tu32 irr;\n\tu32 pad;\n\tunion kvm_ioapic_redirect_entry redirtbl[24];\n\tlong unsigned int irq_states[24];\n\tstruct kvm_io_device dev;\n\tstruct kvm *kvm;\n\tspinlock_t lock;\n\tstruct rtc_status rtc_status;\n\tstruct delayed_work eoi_inject;\n\tu32 irq_eoi[24];\n\tu32 irr_delivered;\n\tstruct hlist_head mask_notifier_list;\n};\n\nstruct kvm_ioapic_state {\n\t__u64 base_address;\n\t__u32 ioregsel;\n\t__u32 id;\n\t__u32 irr;\n\t__u32 pad;\n\tunion {\n\t\t__u64 bits;\n\t\tstruct {\n\t\t\t__u8 vector;\n\t\t\t__u8 delivery_mode: 3;\n\t\t\t__u8 dest_mode: 1;\n\t\t\t__u8 delivery_status: 1;\n\t\t\t__u8 polarity: 1;\n\t\t\t__u8 remote_irr: 1;\n\t\t\t__u8 trig_mode: 1;\n\t\t\t__u8 mask: 1;\n\t\t\t__u8 reserve: 7;\n\t\t\t__u8 reserved[4];\n\t\t\t__u8 dest_id;\n\t\t} fields;\n\t} redirtbl[24];\n};\n\nstruct kvm_ioeventfd {\n\t__u64 datamatch;\n\t__u64 addr;\n\t__u32 len;\n\t__s32 fd;\n\t__u32 flags;\n\t__u8 pad[36];\n};\n\nstruct kvm_irq_ack_notifier {\n\tstruct hlist_node link;\n\tunsigned int gsi;\n\tvoid (*irq_acked)(struct kvm_irq_ack_notifier *);\n};\n\nstruct kvm_irq_level {\n\tunion {\n\t\t__u32 irq;\n\t\t__s32 status;\n\t};\n\t__u32 level;\n};\n\nstruct kvm_irq_mask_notifier {\n\tvoid (*func)(struct kvm_irq_mask_notifier *, bool);\n\tint irq;\n\tstruct hlist_node link;\n};\n\nstruct kvm_irq_routing_irqchip {\n\t__u32 irqchip;\n\t__u32 pin;\n};\n\nstruct kvm_irq_routing_msi {\n\t__u32 address_lo;\n\t__u32 address_hi;\n\t__u32 data;\n\tunion {\n\t\t__u32 pad;\n\t\t__u32 devid;\n\t};\n};\n\nstruct kvm_irq_routing_s390_adapter {\n\t__u64 ind_addr;\n\t__u64 summary_addr;\n\t__u64 ind_offset;\n\t__u32 summary_offset;\n\t__u32 adapter_id;\n};\n\nstruct kvm_irq_routing_hv_sint {\n\t__u32 vcpu;\n\t__u32 sint;\n};\n\nstruct kvm_irq_routing_xen_evtchn {\n\t__u32 port;\n\t__u32 vcpu;\n\t__u32 priority;\n};\n\nstruct kvm_irq_routing_entry {\n\t__u32 gsi;\n\t__u32 type;\n\t__u32 flags;\n\t__u32 pad;\n\tunion {\n\t\tstruct kvm_irq_routing_irqchip irqchip;\n\t\tstruct kvm_irq_routing_msi msi;\n\t\tstruct kvm_irq_routing_s390_adapter adapter;\n\t\tstruct kvm_irq_routing_hv_sint hv_sint;\n\t\tstruct kvm_irq_routing_xen_evtchn xen_evtchn;\n\t\t__u32 pad[8];\n\t} u;\n};\n\nstruct kvm_irq_routing {\n\t__u32 nr;\n\t__u32 flags;\n\tstruct kvm_irq_routing_entry entries[0];\n};\n\nstruct kvm_irq_routing_table {\n\tint chip[72];\n\tu32 nr_rt_entries;\n\tstruct hlist_head map[0];\n};\n\nstruct kvm_pic_state {\n\t__u8 last_irr;\n\t__u8 irr;\n\t__u8 imr;\n\t__u8 isr;\n\t__u8 priority_add;\n\t__u8 irq_base;\n\t__u8 read_reg_select;\n\t__u8 poll;\n\t__u8 special_mask;\n\t__u8 init_state;\n\t__u8 auto_eoi;\n\t__u8 rotate_on_auto_eoi;\n\t__u8 special_fully_nested_mode;\n\t__u8 init4;\n\t__u8 elcr;\n\t__u8 elcr_mask;\n};\n\nstruct kvm_irqchip {\n\t__u32 chip_id;\n\t__u32 pad;\n\tunion {\n\t\tchar dummy[512];\n\t\tstruct kvm_pic_state pic;\n\t\tstruct kvm_ioapic_state ioapic;\n\t} chip;\n};\n\nstruct kvm_irqfd {\n\t__u32 fd;\n\t__u32 gsi;\n\t__u32 flags;\n\t__u32 resamplefd;\n\t__u8 pad[16];\n};\n\nstruct kvm_kernel_irqfd;\n\nstruct kvm_irqfd_pt {\n\tstruct kvm_kernel_irqfd *irqfd;\n\tstruct kvm *kvm;\n\tpoll_table pt;\n\tint ret;\n};\n\nstruct kvm_s390_adapter_int {\n\tu64 ind_addr;\n\tu64 ind_gaddr;\n\tu64 summary_addr;\n\tu64 summary_gaddr;\n\tu64 ind_offset;\n\tu32 summary_offset;\n\tu32 adapter_id;\n};\n\nstruct kvm_xen_evtchn {\n\tu32 port;\n\tu32 vcpu_id;\n\tint vcpu_idx;\n\tu32 priority;\n};\n\nstruct kvm_kernel_irq_routing_entry {\n\tu32 gsi;\n\tu32 type;\n\tint (*set)(struct kvm_kernel_irq_routing_entry *, struct kvm *, int, int, bool);\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int irqchip;\n\t\t\tunsigned int pin;\n\t\t} irqchip;\n\t\tstruct {\n\t\t\tu32 address_lo;\n\t\t\tu32 address_hi;\n\t\t\tu32 data;\n\t\t\tu32 flags;\n\t\t\tu32 devid;\n\t\t} msi;\n\t\tstruct kvm_s390_adapter_int adapter;\n\t\tstruct kvm_hv_sint hv_sint;\n\t\tstruct kvm_xen_evtchn xen_evtchn;\n\t};\n\tstruct hlist_node link;\n};\n\nstruct kvm_kernel_irqfd_resampler;\n\nstruct kvm_kernel_irqfd {\n\tstruct kvm *kvm;\n\twait_queue_entry_t wait;\n\tstruct kvm_kernel_irq_routing_entry irq_entry;\n\tseqcount_spinlock_t irq_entry_sc;\n\tint gsi;\n\tstruct work_struct inject;\n\tstruct kvm_kernel_irqfd_resampler *resampler;\n\tstruct eventfd_ctx *resamplefd;\n\tstruct list_head resampler_link;\n\tstruct eventfd_ctx *eventfd;\n\tstruct list_head list;\n\tstruct work_struct shutdown;\n\tstruct irq_bypass_consumer consumer;\n\tstruct irq_bypass_producer *producer;\n\tstruct kvm_vcpu *irq_bypass_vcpu;\n\tstruct list_head vcpu_list;\n\tvoid *irq_bypass_data;\n};\n\nstruct kvm_kernel_irqfd_resampler {\n\tstruct kvm *kvm;\n\tstruct list_head list;\n\tstruct kvm_irq_ack_notifier notifier;\n\tstruct list_head link;\n};\n\nstruct kvm_kpic_state {\n\tu8 last_irr;\n\tu8 irr;\n\tu8 imr;\n\tu8 isr;\n\tu8 priority_add;\n\tu8 irq_base;\n\tu8 read_reg_select;\n\tu8 poll;\n\tu8 special_mask;\n\tu8 init_state;\n\tu8 auto_eoi;\n\tu8 rotate_on_auto_eoi;\n\tu8 special_fully_nested_mode;\n\tu8 init4;\n\tu8 elcr;\n\tu8 elcr_mask;\n\tu8 isr_ack;\n\tstruct kvm_pic *pics_state;\n};\n\nstruct kvm_kpit_channel_state {\n\tu32 count;\n\tu16 latched_count;\n\tu8 count_latched;\n\tu8 status_latched;\n\tu8 status;\n\tu8 read_state;\n\tu8 write_state;\n\tu8 write_latch;\n\tu8 rw_mode;\n\tu8 mode;\n\tu8 bcd;\n\tu8 gate;\n\tktime_t count_load_time;\n};\n\nstruct kvm_kpit_state {\n\tstruct kvm_kpit_channel_state channels[3];\n\tu32 flags;\n\tbool is_periodic;\n\ts64 period;\n\tstruct hrtimer timer;\n\tstruct mutex lock;\n\tatomic_t reinject;\n\tatomic_t pending;\n\tatomic_t irq_ack;\n\tstruct kvm_irq_ack_notifier irq_ack_notifier;\n};\n\nstruct kvm_timer {\n\tstruct hrtimer timer;\n\ts64 period;\n\tktime_t target_expiration;\n\tu32 timer_mode;\n\tu32 timer_mode_mask;\n\tu64 tscdeadline;\n\tu64 expired_tscdeadline;\n\tu32 timer_advance_ns;\n\tatomic_t pending;\n\tbool hv_timer_in_use;\n};\n\nstruct kvm_lapic {\n\tlong unsigned int base_address;\n\tstruct kvm_io_device dev;\n\tstruct kvm_timer lapic_timer;\n\tu32 divide_count;\n\tstruct kvm_vcpu *vcpu;\n\tbool apicv_active;\n\tbool sw_enabled;\n\tbool irr_pending;\n\tbool lvt0_in_nmi_mode;\n\tbool guest_apic_protected;\n\ts16 isr_count;\n\tint highest_isr_cache;\n\tvoid *regs;\n\tgpa_t vapic_addr;\n\tstruct gfn_to_hva_cache vapic_cache;\n\tlong unsigned int pending_events;\n\tunsigned int sipi_vector;\n\tint nr_lvt_entries;\n};\n\nstruct kvm_lapic_irq {\n\tu32 vector;\n\tu16 delivery_mode;\n\tu16 dest_mode;\n\tbool level;\n\tu16 trig_mode;\n\tu32 shorthand;\n\tu32 dest_id;\n\tbool msi_redir_hint;\n};\n\nstruct kvm_lapic_state {\n\tchar regs[1024];\n};\n\nstruct kvm_lpage_info {\n\tint disallow_lpage;\n};\n\nstruct kvm_memory_slot {\n\tstruct hlist_node id_node[2];\n\tstruct interval_tree_node hva_node[2];\n\tstruct rb_node gfn_node[2];\n\tgfn_t base_gfn;\n\tlong unsigned int npages;\n\tlong unsigned int *dirty_bitmap;\n\tstruct kvm_arch_memory_slot arch;\n\tlong unsigned int userspace_addr;\n\tu32 flags;\n\tshort int id;\n\tu16 as_id;\n\tstruct {\n\t\tstruct file *file;\n\t\tlong unsigned int pgoff;\n\t} gmem;\n};\n\nstruct kvm_memslot_iter {\n\tstruct kvm_memslots *slots;\n\tstruct rb_node *node;\n\tstruct kvm_memory_slot *slot;\n};\n\nstruct kvm_mmio_fragment {\n\tgpa_t gpa;\n\tvoid *data;\n\tunsigned int len;\n};\n\nstruct kvm_mmu_root_info {\n\tgpa_t pgd;\n\thpa_t hpa;\n};\n\nstruct rsvd_bits_validate {\n\tu64 rsvd_bits_mask[10];\n\tu64 bad_mt_xwr;\n};\n\nstruct kvm_page_fault;\n\nstruct kvm_mmu_page;\n\nstruct kvm_mmu {\n\tlong unsigned int (*get_guest_pgd)(struct kvm_vcpu *);\n\tu64 (*get_pdptr)(struct kvm_vcpu *, int);\n\tint (*page_fault)(struct kvm_vcpu *, struct kvm_page_fault *);\n\tvoid (*inject_page_fault)(struct kvm_vcpu *, struct x86_exception *);\n\tgpa_t (*gva_to_gpa)(struct kvm_vcpu *, struct kvm_mmu *, gpa_t, u64, struct x86_exception *);\n\tint (*sync_spte)(struct kvm_vcpu *, struct kvm_mmu_page *, int);\n\tstruct kvm_mmu_root_info root;\n\thpa_t mirror_root_hpa;\n\tunion kvm_cpu_role cpu_role;\n\tunion kvm_mmu_page_role root_role;\n\tu32 pkru_mask;\n\tstruct kvm_mmu_root_info prev_roots[3];\n\tu8 permissions[16];\n\tu64 *pae_root;\n\tu64 *pml4_root;\n\tu64 *pml5_root;\n\tstruct rsvd_bits_validate shadow_zero_check;\n\tstruct rsvd_bits_validate guest_rsvd_check;\n\tu64 pdptrs[4];\n};\n\ntypedef bool (*gfn_handler_t)(struct kvm *, struct kvm_gfn_range *);\n\ntypedef void (*on_lock_fn_t)(struct kvm *);\n\nstruct kvm_mmu_notifier_range {\n\tu64 start;\n\tu64 end;\n\tunion kvm_mmu_notifier_arg arg;\n\tgfn_handler_t handler;\n\ton_lock_fn_t on_lock;\n\tbool flush_on_ret;\n\tbool may_block;\n\tbool lockless;\n};\n\nstruct kvm_mmu_notifier_return {\n\tbool ret;\n\tbool found_memslot;\n};\n\ntypedef struct kvm_mmu_notifier_return kvm_mn_ret_t;\n\nstruct kvm_rmap_head {\n\tatomic_long_t val;\n};\n\nstruct kvm_mmu_page {\n\tstruct list_head link;\n\tstruct hlist_node hash_link;\n\tbool tdp_mmu_page;\n\tbool unsync;\n\tunion {\n\t\tu8 mmu_valid_gen;\n\t\tbool tdp_mmu_scheduled_root_to_zap;\n\t};\n\tbool nx_huge_page_disallowed;\n\tunion kvm_mmu_page_role role;\n\tgfn_t gfn;\n\tu64 *spt;\n\tu64 *shadowed_translation;\n\tunion {\n\t\tint root_count;\n\t\trefcount_t tdp_mmu_root_count;\n\t};\n\tbool has_mapped_host_mmio;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int unsync_children;\n\t\t\tatomic_t write_flooding_count;\n\t\t};\n\t\tvoid *external_spt;\n\t};\n\tunion {\n\t\tstruct kvm_rmap_head parent_ptes;\n\t\ttdp_ptep_t ptep;\n\t};\n\tlong unsigned int unsync_child_bitmap[8];\n\tstruct list_head possible_nx_huge_page_link;\n\tstruct callback_head callback_head;\n};\n\nstruct mmu_page_and_offset {\n\tstruct kvm_mmu_page *sp;\n\tunsigned int idx;\n};\n\nstruct kvm_mmu_pages {\n\tstruct mmu_page_and_offset page[16];\n\tunsigned int nr;\n};\n\nstruct kvm_mmu_role_regs {\n\tconst long unsigned int cr0;\n\tconst long unsigned int cr4;\n\tconst u64 efer;\n};\n\nstruct kvm_mp_state {\n\t__u32 mp_state;\n};\n\nstruct kvm_msi {\n\t__u32 address_lo;\n\t__u32 address_hi;\n\t__u32 data;\n\t__u32 flags;\n\t__u32 devid;\n\t__u8 pad[12];\n};\n\nstruct kvm_msr_entry {\n\t__u32 index;\n\t__u32 reserved;\n\t__u64 data;\n};\n\nstruct kvm_msr_filter_range {\n\t__u32 flags;\n\t__u32 nmsrs;\n\t__u32 base;\n\t__u8 *bitmap;\n};\n\nstruct kvm_msr_filter {\n\t__u32 flags;\n\tstruct kvm_msr_filter_range ranges[16];\n};\n\nstruct kvm_msr_filter_range_compat {\n\t__u32 flags;\n\t__u32 nmsrs;\n\t__u32 base;\n\t__u32 bitmap;\n};\n\nstruct kvm_msr_filter_compat {\n\t__u32 flags;\n\tstruct kvm_msr_filter_range_compat ranges[16];\n};\n\nstruct kvm_msr_list {\n\t__u32 nmsrs;\n\t__u32 indices[0];\n};\n\nstruct kvm_msrs {\n\t__u32 nmsrs;\n\t__u32 pad;\n\tstruct kvm_msr_entry entries[0];\n};\n\nstruct kvm_mtrr {\n\tu64 var[16];\n\tu64 fixed_64k;\n\tu64 fixed_16k[2];\n\tu64 fixed_4k[8];\n\tu64 deftype;\n};\n\nstruct kvm_vmx_nested_state_hdr {\n\t__u64 vmxon_pa;\n\t__u64 vmcs12_pa;\n\tstruct {\n\t\t__u16 flags;\n\t} smm;\n\t__u16 pad;\n\t__u32 flags;\n\t__u64 preemption_timer_deadline;\n};\n\nstruct kvm_svm_nested_state_hdr {\n\t__u64 vmcb_pa;\n};\n\nstruct kvm_vmx_nested_state_data {\n\t__u8 vmcs12[4096];\n\t__u8 shadow_vmcs12[4096];\n};\n\nstruct kvm_svm_nested_state_data {\n\t__u8 vmcb12[4096];\n};\n\nstruct kvm_nested_state {\n\t__u16 flags;\n\t__u16 format;\n\t__u32 size;\n\tunion {\n\t\tstruct kvm_vmx_nested_state_hdr vmx;\n\t\tstruct kvm_svm_nested_state_hdr svm;\n\t\t__u8 pad[120];\n\t} hdr;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_vmx;\n\t\t\tstruct kvm_vmx_nested_state_data vmx[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_svm;\n\t\t\tstruct kvm_svm_nested_state_data svm[0];\n\t\t};\n\t} data;\n};\n\nstruct kvm_one_reg {\n\t__u64 id;\n\t__u64 addr;\n};\n\nstruct kvm_page_fault {\n\tconst gpa_t addr;\n\tconst u64 error_code;\n\tconst bool prefetch;\n\tconst bool exec;\n\tconst bool write;\n\tconst bool present;\n\tconst bool rsvd;\n\tconst bool user;\n\tconst bool is_tdp;\n\tconst bool is_private;\n\tconst bool nx_huge_page_workaround_enabled;\n\tbool huge_page_disallowed;\n\tu8 max_level;\n\tu8 req_level;\n\tu8 goal_level;\n\tgfn_t gfn;\n\tstruct kvm_memory_slot *slot;\n\tlong unsigned int mmu_seq;\n\tkvm_pfn_t pfn;\n\tstruct page *refcounted_page;\n\tbool map_writable;\n\tbool write_fault_to_shadow_pgtable;\n};\n\nstruct kvm_pic {\n\tspinlock_t lock;\n\tbool wakeup_needed;\n\tunsigned int pending_acks;\n\tstruct kvm *kvm;\n\tstruct kvm_kpic_state pics[2];\n\tint output;\n\tstruct kvm_io_device dev_master;\n\tstruct kvm_io_device dev_slave;\n\tstruct kvm_io_device dev_elcr;\n\tlong unsigned int irq_states[16];\n};\n\nstruct kvm_pio_request {\n\tlong unsigned int count;\n\tint in;\n\tint port;\n\tint size;\n};\n\nstruct kvm_pit {\n\tstruct kvm_io_device dev;\n\tstruct kvm_io_device speaker_dev;\n\tstruct kvm *kvm;\n\tstruct kvm_kpit_state pit_state;\n\tstruct kvm_irq_mask_notifier mask_notifier;\n\tstruct kthread_worker *worker;\n\tstruct kthread_work expired;\n};\n\nstruct kvm_pit_channel_state {\n\t__u32 count;\n\t__u16 latched_count;\n\t__u8 count_latched;\n\t__u8 status_latched;\n\t__u8 status;\n\t__u8 read_state;\n\t__u8 write_state;\n\t__u8 write_latch;\n\t__u8 rw_mode;\n\t__u8 mode;\n\t__u8 bcd;\n\t__u8 gate;\n\t__s64 count_load_time;\n};\n\nstruct kvm_pit_config {\n\t__u32 flags;\n\t__u32 pad[15];\n};\n\nstruct kvm_pit_state {\n\tstruct kvm_pit_channel_state channels[3];\n};\n\nstruct kvm_pit_state2 {\n\tstruct kvm_pit_channel_state channels[3];\n\t__u32 flags;\n\t__u32 reserved[9];\n};\n\nstruct kvm_pmc {\n\tenum pmc_type type;\n\tu8 idx;\n\tbool is_paused;\n\tbool intr;\n\tu64 counter;\n\tu64 emulated_counter;\n\tu64 eventsel;\n\tu64 eventsel_hw;\n\tstruct perf_event *perf_event;\n\tstruct kvm_vcpu *vcpu;\n\tu64 current_config;\n};\n\nstruct kvm_pmu {\n\tu8 version;\n\tunsigned int nr_arch_gp_counters;\n\tunsigned int nr_arch_fixed_counters;\n\tunsigned int available_event_types;\n\tu64 fixed_ctr_ctrl;\n\tu64 fixed_ctr_ctrl_hw;\n\tu64 fixed_ctr_ctrl_rsvd;\n\tu64 global_ctrl;\n\tu64 global_status;\n\tu64 counter_bitmask[2];\n\tu64 global_ctrl_rsvd;\n\tu64 global_status_rsvd;\n\tu64 reserved_bits;\n\tu64 raw_event_mask;\n\tstruct kvm_pmc gp_counters[8];\n\tstruct kvm_pmc fixed_counters[3];\n\tunion {\n\t\tlong unsigned int reprogram_pmi[1];\n\t\tatomic64_t __reprogram_pmi;\n\t};\n\tlong unsigned int all_valid_pmc_idx[1];\n\tlong unsigned int pmc_in_use[1];\n\tlong unsigned int pmc_counting_instructions[1];\n\tlong unsigned int pmc_counting_branches[1];\n\tu64 ds_area;\n\tu64 pebs_enable;\n\tu64 pebs_enable_rsvd;\n\tu64 pebs_data_cfg;\n\tu64 pebs_data_cfg_rsvd;\n\tu64 host_cross_mapped_mask;\n\tbool need_cleanup;\n\tu8 event_count;\n};\n\nstruct kvm_pmu_emulated_event_selectors {\n\tu64 INSTRUCTIONS_RETIRED;\n\tu64 BRANCH_INSTRUCTIONS_RETIRED;\n};\n\nstruct kvm_pmu_event_filter {\n\t__u32 action;\n\t__u32 nevents;\n\t__u32 fixed_counter_bitmap;\n\t__u32 flags;\n\t__u32 pad[4];\n\t__u64 events[0];\n};\n\nstruct msr_data;\n\nstruct x86_pmu_capability;\n\nstruct kvm_pmu_ops {\n\tstruct kvm_pmc * (*rdpmc_ecx_to_pmc)(struct kvm_vcpu *, unsigned int, u64 *);\n\tstruct kvm_pmc * (*msr_idx_to_pmc)(struct kvm_vcpu *, u32);\n\tint (*check_rdpmc_early)(struct kvm_vcpu *, unsigned int);\n\tbool (*is_valid_msr)(struct kvm_vcpu *, u32);\n\tint (*get_msr)(struct kvm_vcpu *, struct msr_data *);\n\tint (*set_msr)(struct kvm_vcpu *, struct msr_data *);\n\tvoid (*refresh)(struct kvm_vcpu *);\n\tvoid (*init)(struct kvm_vcpu *);\n\tvoid (*reset)(struct kvm_vcpu *);\n\tvoid (*deliver_pmi)(struct kvm_vcpu *);\n\tvoid (*cleanup)(struct kvm_vcpu *);\n\tbool (*is_mediated_pmu_supported)(struct x86_pmu_capability *);\n\tvoid (*mediated_load)(struct kvm_vcpu *);\n\tvoid (*mediated_put)(struct kvm_vcpu *);\n\tvoid (*write_global_ctrl)(u64);\n\tconst u64 EVENTSEL_EVENT;\n\tconst int MAX_NR_GP_COUNTERS;\n\tconst int MIN_NR_GP_COUNTERS;\n\tconst u32 PERF_GLOBAL_CTRL;\n\tconst u32 GP_EVENTSEL_BASE;\n\tconst u32 GP_COUNTER_BASE;\n\tconst u32 FIXED_COUNTER_BASE;\n\tconst u32 MSR_STRIDE;\n};\n\nstruct kvm_pre_fault_memory {\n\t__u64 gpa;\n\t__u64 size;\n\t__u64 flags;\n\t__u64 padding[5];\n};\n\nstruct ptp_pin_desc;\n\nstruct ptp_system_timestamp;\n\nstruct system_device_crosststamp;\n\nstruct ptp_clock_request;\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[32];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint n_per_lp;\n\tint pps;\n\tunsigned int supported_perout_flags;\n\tunsigned int supported_extts_flags;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\ts32 (*getmaxphase)(struct ptp_clock_info *);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*getcycles64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n\tint (*perout_loopback)(struct ptp_clock_info *, unsigned int, int);\n};\n\nstruct ptp_clock;\n\nstruct kvm_ptp_clock {\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info caps;\n};\n\nstruct kvm_queued_exception {\n\tbool pending;\n\tbool injected;\n\tbool has_error_code;\n\tu8 vector;\n\tu32 error_code;\n\tlong unsigned int payload;\n\tbool has_payload;\n};\n\nstruct kvm_queued_interrupt {\n\tbool injected;\n\tbool soft;\n\tu8 nr;\n};\n\nstruct kvm_reg_list {\n\t__u64 n;\n\t__u64 reg[0];\n};\n\nstruct kvm_regs {\n\t__u64 rax;\n\t__u64 rbx;\n\t__u64 rcx;\n\t__u64 rdx;\n\t__u64 rsi;\n\t__u64 rdi;\n\t__u64 rsp;\n\t__u64 rbp;\n\t__u64 r8;\n\t__u64 r9;\n\t__u64 r10;\n\t__u64 r11;\n\t__u64 r12;\n\t__u64 r13;\n\t__u64 r14;\n\t__u64 r15;\n\t__u64 rip;\n\t__u64 rflags;\n};\n\nstruct kvm_reinject_control {\n\t__u8 pit_reinject;\n\t__u8 reserved[31];\n};\n\nstruct kvm_xen_exit {\n\t__u32 type;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 longmode;\n\t\t\t__u32 cpl;\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[6];\n\t\t} hcall;\n\t} u;\n};\n\nstruct kvm_segment {\n\t__u64 base;\n\t__u32 limit;\n\t__u16 selector;\n\t__u8 type;\n\t__u8 present;\n\t__u8 dpl;\n\t__u8 db;\n\t__u8 s;\n\t__u8 l;\n\t__u8 g;\n\t__u8 avl;\n\t__u8 unusable;\n\t__u8 padding;\n};\n\nstruct kvm_sregs {\n\tstruct kvm_segment cs;\n\tstruct kvm_segment ds;\n\tstruct kvm_segment es;\n\tstruct kvm_segment fs;\n\tstruct kvm_segment gs;\n\tstruct kvm_segment ss;\n\tstruct kvm_segment tr;\n\tstruct kvm_segment ldt;\n\tstruct kvm_dtable gdt;\n\tstruct kvm_dtable idt;\n\t__u64 cr0;\n\t__u64 cr2;\n\t__u64 cr3;\n\t__u64 cr4;\n\t__u64 cr8;\n\t__u64 efer;\n\t__u64 apic_base;\n\t__u64 interrupt_bitmap[4];\n};\n\nstruct kvm_vcpu_events {\n\tstruct {\n\t\t__u8 injected;\n\t\t__u8 nr;\n\t\t__u8 has_error_code;\n\t\t__u8 pending;\n\t\t__u32 error_code;\n\t} exception;\n\tstruct {\n\t\t__u8 injected;\n\t\t__u8 nr;\n\t\t__u8 soft;\n\t\t__u8 shadow;\n\t} interrupt;\n\tstruct {\n\t\t__u8 injected;\n\t\t__u8 pending;\n\t\t__u8 masked;\n\t\t__u8 pad;\n\t} nmi;\n\t__u32 sipi_vector;\n\t__u32 flags;\n\tstruct {\n\t\t__u8 smm;\n\t\t__u8 pending;\n\t\t__u8 smm_inside_nmi;\n\t\t__u8 latched_init;\n\t} smi;\n\tstruct {\n\t\t__u8 pending;\n\t} triple_fault;\n\t__u8 reserved[26];\n\t__u8 exception_has_payload;\n\t__u64 exception_payload;\n};\n\nstruct kvm_sync_regs {\n\tstruct kvm_regs regs;\n\tstruct kvm_sregs sregs;\n\tstruct kvm_vcpu_events events;\n};\n\nstruct kvm_run {\n\t__u8 request_interrupt_window;\n\t__u8 immediate_exit__unsafe;\n\t__u8 padding1[6];\n\t__u32 exit_reason;\n\t__u8 ready_for_interrupt_injection;\n\t__u8 if_flag;\n\t__u16 flags;\n\t__u64 cr8;\n\t__u64 apic_base;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 hardware_exit_reason;\n\t\t} hw;\n\t\tstruct {\n\t\t\t__u64 hardware_entry_failure_reason;\n\t\t\t__u32 cpu;\n\t\t} fail_entry;\n\t\tstruct {\n\t\t\t__u32 exception;\n\t\t\t__u32 error_code;\n\t\t} ex;\n\t\tstruct {\n\t\t\t__u8 direction;\n\t\t\t__u8 size;\n\t\t\t__u16 port;\n\t\t\t__u32 count;\n\t\t\t__u64 data_offset;\n\t\t} io;\n\t\tstruct {\n\t\t\tstruct kvm_debug_exit_arch arch;\n\t\t} debug;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} mmio;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} iocsr_io;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u64 ret;\n\t\t\tunion {\n\t\t\t\t__u64 flags;\n\t\t\t};\n\t\t} hypercall;\n\t\tstruct {\n\t\t\t__u64 rip;\n\t\t\t__u32 is_write;\n\t\t\t__u32 pad;\n\t\t} tpr_access;\n\t\tstruct {\n\t\t\t__u8 icptcode;\n\t\t\t__u16 ipa;\n\t\t\t__u32 ipb;\n\t\t} s390_sieic;\n\t\t__u64 s390_reset_flags;\n\t\tstruct {\n\t\t\t__u64 trans_exc_code;\n\t\t\t__u32 pgm_code;\n\t\t} s390_ucontrol;\n\t\tstruct {\n\t\t\t__u32 dcrn;\n\t\t\t__u32 data;\n\t\t\t__u8 is_write;\n\t\t} dcr;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 data[16];\n\t\t} internal;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 flags;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 insn_size;\n\t\t\t\t\t__u8 insn_bytes[15];\n\t\t\t\t};\n\t\t\t};\n\t\t} emulation_failure;\n\t\tstruct {\n\t\t\t__u64 gprs[32];\n\t\t} osi;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 ret;\n\t\t\t__u64 args[9];\n\t\t} papr_hcall;\n\t\tstruct {\n\t\t\t__u16 subchannel_id;\n\t\t\t__u16 subchannel_nr;\n\t\t\t__u32 io_int_parm;\n\t\t\t__u32 io_int_word;\n\t\t\t__u32 ipb;\n\t\t\t__u8 dequeued;\n\t\t} s390_tsch;\n\t\tstruct {\n\t\t\t__u32 epr;\n\t\t} epr;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\t__u32 ndata;\n\t\t\tunion {\n\t\t\t\t__u64 data[16];\n\t\t\t};\n\t\t} system_event;\n\t\tstruct {\n\t\t\t__u64 addr;\n\t\t\t__u8 ar;\n\t\t\t__u8 reserved;\n\t\t\t__u8 fc;\n\t\t\t__u8 sel1;\n\t\t\t__u16 sel2;\n\t\t} s390_stsi;\n\t\tstruct {\n\t\t\t__u8 vector;\n\t\t} eoi;\n\t\tstruct kvm_hyperv_exit hyperv;\n\t\tstruct {\n\t\t\t__u64 esr_iss;\n\t\t\t__u64 fault_ipa;\n\t\t} arm_nisv;\n\t\tstruct {\n\t\t\t__u8 error;\n\t\t\t__u8 pad[7];\n\t\t\t__u32 reason;\n\t\t\t__u32 index;\n\t\t\t__u64 data;\n\t\t} msr;\n\t\tstruct kvm_xen_exit xen;\n\t\tstruct {\n\t\t\tlong unsigned int extension_id;\n\t\t\tlong unsigned int function_id;\n\t\t\tlong unsigned int args[6];\n\t\t\tlong unsigned int ret[2];\n\t\t} riscv_sbi;\n\t\tstruct {\n\t\t\tlong unsigned int csr_num;\n\t\t\tlong unsigned int new_value;\n\t\t\tlong unsigned int write_mask;\n\t\t\tlong unsigned int ret_value;\n\t\t} riscv_csr;\n\t\tstruct {\n\t\t\t__u32 flags;\n\t\t} notify;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 gpa;\n\t\t\t__u64 size;\n\t\t} memory_fault;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 nr;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 data[5];\n\t\t\t\t} unknown;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 gpa;\n\t\t\t\t\t__u64 size;\n\t\t\t\t} get_quote;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 leaf;\n\t\t\t\t\t__u64 r11;\n\t\t\t\t\t__u64 r12;\n\t\t\t\t\t__u64 r13;\n\t\t\t\t\t__u64 r14;\n\t\t\t\t} get_tdvmcall_info;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 vector;\n\t\t\t\t} setup_event_notify;\n\t\t\t};\n\t\t} tdx;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 esr;\n\t\t\t__u64 gva;\n\t\t\t__u64 gpa;\n\t\t} arm_sea;\n\t\tstruct kvm_exit_snp_req_certs snp_req_certs;\n\t\tchar padding[256];\n\t};\n\t__u64 kvm_valid_regs;\n\t__u64 kvm_dirty_regs;\n\tunion {\n\t\tstruct kvm_sync_regs regs;\n\t\tchar padding[2048];\n\t} s;\n};\n\nstruct kvm_save_segment {\n\tu16 selector;\n\tlong unsigned int base;\n\tu32 limit;\n\tu32 ar;\n};\n\nstruct misc_cg;\n\nstruct kvm_sev_info {\n\tbool active;\n\tbool es_active;\n\tbool need_init;\n\tunsigned int asid;\n\tunsigned int handle;\n\tint fd;\n\tlong unsigned int policy;\n\tlong unsigned int pages_locked;\n\tstruct list_head regions_list;\n\tu64 ap_jump_table;\n\tu64 vmsa_features;\n\tu16 ghcb_version;\n\tstruct kvm *enc_context_owner;\n\tstruct list_head mirror_vms;\n\tstruct list_head mirror_entry;\n\tstruct misc_cg *misc_cg;\n\tatomic_t migration_in_progress;\n\tvoid *snp_context;\n\tvoid *guest_req_buf;\n\tvoid *guest_resp_buf;\n\tstruct mutex guest_req_mutex;\n\tcpumask_var_t have_run_cpus;\n\tbool snp_certs_enabled;\n};\n\nstruct kvm_shadow_walk_iterator {\n\tu64 addr;\n\thpa_t shadow_addr;\n\tu64 *sptep;\n\tint level;\n\tunsigned int index;\n};\n\nstruct kvm_signal_mask {\n\t__u32 len;\n\t__u8 sigset[0];\n};\n\nstruct kvm_smm_seg_state_32 {\n\tu32 flags;\n\tu32 limit;\n\tu32 base;\n};\n\nstruct kvm_smm_seg_state_64 {\n\tu16 selector;\n\tu16 attributes;\n\tu32 limit;\n\tu64 base;\n};\n\nstruct kvm_smram_state_64 {\n\tstruct kvm_smm_seg_state_64 es;\n\tstruct kvm_smm_seg_state_64 cs;\n\tstruct kvm_smm_seg_state_64 ss;\n\tstruct kvm_smm_seg_state_64 ds;\n\tstruct kvm_smm_seg_state_64 fs;\n\tstruct kvm_smm_seg_state_64 gs;\n\tstruct kvm_smm_seg_state_64 gdtr;\n\tstruct kvm_smm_seg_state_64 ldtr;\n\tstruct kvm_smm_seg_state_64 idtr;\n\tstruct kvm_smm_seg_state_64 tr;\n\tu64 io_restart_rip;\n\tu64 io_restart_rcx;\n\tu64 io_restart_rsi;\n\tu64 io_restart_rdi;\n\tu32 io_restart_dword;\n\tu32 reserved1;\n\tu8 io_inst_restart;\n\tu8 auto_hlt_restart;\n\tu8 amd_nmi_mask;\n\tu8 int_shadow;\n\tu32 reserved2;\n\tu64 efer;\n\tu64 svm_guest_flag;\n\tu64 svm_guest_vmcb_gpa;\n\tu64 svm_guest_virtual_int;\n\tu32 reserved3[3];\n\tu32 smm_revison;\n\tu32 smbase;\n\tu32 reserved4[5];\n\tu64 ssp;\n\tu64 svm_guest_pat;\n\tu64 svm_host_efer;\n\tu64 svm_host_cr4;\n\tu64 svm_host_cr3;\n\tu64 svm_host_cr0;\n\tu64 cr4;\n\tu64 cr3;\n\tu64 cr0;\n\tu64 dr7;\n\tu64 dr6;\n\tu64 rflags;\n\tu64 rip;\n\tu64 gprs[16];\n};\n\nstruct kvm_smram_state_32 {\n\tu32 reserved1[62];\n\tu32 smbase;\n\tu32 smm_revision;\n\tu16 io_inst_restart;\n\tu16 auto_hlt_restart;\n\tu32 io_restart_rdi;\n\tu32 io_restart_rcx;\n\tu32 io_restart_rsi;\n\tu32 io_restart_rip;\n\tu32 cr4;\n\tu16 reserved2;\n\tu8 int_shadow;\n\tu8 reserved3[17];\n\tstruct kvm_smm_seg_state_32 ds;\n\tstruct kvm_smm_seg_state_32 fs;\n\tstruct kvm_smm_seg_state_32 gs;\n\tstruct kvm_smm_seg_state_32 idtr;\n\tstruct kvm_smm_seg_state_32 tr;\n\tu32 reserved;\n\tstruct kvm_smm_seg_state_32 gdtr;\n\tstruct kvm_smm_seg_state_32 ldtr;\n\tstruct kvm_smm_seg_state_32 es;\n\tstruct kvm_smm_seg_state_32 cs;\n\tstruct kvm_smm_seg_state_32 ss;\n\tu32 es_sel;\n\tu32 cs_sel;\n\tu32 ss_sel;\n\tu32 ds_sel;\n\tu32 fs_sel;\n\tu32 gs_sel;\n\tu32 ldtr_sel;\n\tu32 tr_sel;\n\tu32 dr7;\n\tu32 dr6;\n\tu32 gprs[8];\n\tu32 eip;\n\tu32 eflags;\n\tu32 cr3;\n\tu32 cr0;\n};\n\nunion kvm_smram {\n\tstruct kvm_smram_state_64 smram64;\n\tstruct kvm_smram_state_32 smram32;\n\tu8 bytes[512];\n};\n\nstruct kvm_sregs2 {\n\tstruct kvm_segment cs;\n\tstruct kvm_segment ds;\n\tstruct kvm_segment es;\n\tstruct kvm_segment fs;\n\tstruct kvm_segment gs;\n\tstruct kvm_segment ss;\n\tstruct kvm_segment tr;\n\tstruct kvm_segment ldt;\n\tstruct kvm_dtable gdt;\n\tstruct kvm_dtable idt;\n\t__u64 cr0;\n\t__u64 cr2;\n\t__u64 cr3;\n\t__u64 cr4;\n\t__u64 cr8;\n\t__u64 efer;\n\t__u64 apic_base;\n\t__u64 flags;\n\t__u64 pdptrs[4];\n};\n\nstruct kvm_stat_data {\n\tstruct kvm *kvm;\n\tconst struct _kvm_stats_desc *desc;\n\tenum kvm_stat_kind kind;\n};\n\nstruct kvm_stats_header {\n\t__u32 flags;\n\t__u32 name_size;\n\t__u32 num_desc;\n\t__u32 id_offset;\n\t__u32 desc_offset;\n\t__u32 data_offset;\n};\n\nstruct kvm_steal_time {\n\t__u64 steal;\n\t__u32 version;\n\t__u32 flags;\n\t__u8 preempted;\n\t__u8 u8_pad[3];\n\t__u32 pad[11];\n};\n\nstruct kvm_svm {\n\tstruct kvm kvm;\n\tu32 avic_vm_id;\n\tu32 *avic_logical_id_table;\n\tu64 *avic_physical_id_table;\n\tstruct hlist_node hnode;\n\tstruct kvm_sev_info sev_info;\n};\n\nstruct kvm_task_sleep_head {\n\traw_spinlock_t lock;\n\tstruct hlist_head list;\n};\n\nstruct kvm_task_sleep_node {\n\tstruct hlist_node link;\n\tstruct swait_queue_head wq;\n\tu32 token;\n\tint cpu;\n\tbool dummy;\n};\n\nstruct kvm_tpr_access_ctl {\n\t__u32 enabled;\n\t__u32 flags;\n\t__u32 reserved[8];\n};\n\nstruct kvm_translation {\n\t__u64 linear_address;\n\t__u64 physical_address;\n\t__u8 valid;\n\t__u8 writeable;\n\t__u8 usermode;\n\t__u8 pad[5];\n};\n\nstruct kvm_user_return_msr_values {\n\tu64 host;\n\tu64 curr;\n};\n\nstruct user_return_notifier {\n\tvoid (*on_user_return)(struct user_return_notifier *);\n\tstruct hlist_node link;\n};\n\nstruct kvm_user_return_msrs {\n\tstruct user_return_notifier urn;\n\tbool registered;\n\tstruct kvm_user_return_msr_values values[16];\n};\n\nstruct kvm_userspace_memory_region {\n\t__u32 slot;\n\t__u32 flags;\n\t__u64 guest_phys_addr;\n\t__u64 memory_size;\n\t__u64 userspace_addr;\n};\n\nstruct kvm_userspace_memory_region2 {\n\t__u32 slot;\n\t__u32 flags;\n\t__u64 guest_phys_addr;\n\t__u64 memory_size;\n\t__u64 userspace_addr;\n\t__u64 guest_memfd_offset;\n\t__u32 guest_memfd;\n\t__u32 pad1;\n\t__u64 pad2[14];\n};\n\nstruct kvm_vapic_addr {\n\t__u64 vapic_addr;\n};\n\ntypedef struct kvm_vcpu *class_vmx_vmcs01_t;\n\nstruct preempt_ops;\n\nstruct preempt_notifier {\n\tstruct hlist_node link;\n\tstruct preempt_ops *ops;\n};\n\nstruct kvm_vcpu_hv;\n\nstruct kvm_vcpu_arch {\n\tlong unsigned int regs[17];\n\tu32 regs_avail;\n\tu32 regs_dirty;\n\tlong unsigned int cr0;\n\tlong unsigned int cr0_guest_owned_bits;\n\tlong unsigned int cr2;\n\tlong unsigned int cr3;\n\tlong unsigned int cr4;\n\tlong unsigned int cr4_guest_owned_bits;\n\tlong unsigned int cr4_guest_rsvd_bits;\n\tlong unsigned int cr8;\n\tu32 host_pkru;\n\tu32 pkru;\n\tu32 hflags;\n\tu64 efer;\n\tu64 host_debugctl;\n\tu64 apic_base;\n\tstruct kvm_lapic *apic;\n\tbool load_eoi_exitmap_pending;\n\tlong unsigned int ioapic_handled_vectors[4];\n\tlong unsigned int apic_attention;\n\tint32_t apic_arb_prio;\n\tint mp_state;\n\tu64 ia32_misc_enable_msr;\n\tu64 smbase;\n\tu64 smi_count;\n\tbool at_instruction_boundary;\n\tbool tpr_access_reporting;\n\tbool xfd_no_write_intercept;\n\tu64 microcode_version;\n\tu64 arch_capabilities;\n\tu64 perf_capabilities;\n\tstruct kvm_mmu *mmu;\n\tstruct kvm_mmu root_mmu;\n\tstruct kvm_mmu guest_mmu;\n\tstruct kvm_mmu nested_mmu;\n\tstruct kvm_mmu *walk_mmu;\n\tstruct kvm_mmu_memory_cache mmu_pte_list_desc_cache;\n\tstruct kvm_mmu_memory_cache mmu_shadow_page_cache;\n\tstruct kvm_mmu_memory_cache mmu_shadowed_info_cache;\n\tstruct kvm_mmu_memory_cache mmu_page_header_cache;\n\tstruct kvm_mmu_memory_cache mmu_external_spt_cache;\n\tstruct fpu_guest guest_fpu;\n\tu64 xcr0;\n\tu64 guest_supported_xcr0;\n\tu64 ia32_xss;\n\tu64 guest_supported_xss;\n\tstruct kvm_pio_request pio;\n\tvoid *pio_data;\n\tvoid *sev_pio_data;\n\tunsigned int sev_pio_count;\n\tu8 event_exit_inst_len;\n\tbool exception_from_userspace;\n\tstruct kvm_queued_exception exception;\n\tstruct kvm_queued_exception exception_vmexit;\n\tstruct kvm_queued_interrupt interrupt;\n\tint halt_request;\n\tint cpuid_nent;\n\tstruct kvm_cpuid_entry2 *cpuid_entries;\n\tbool cpuid_dynamic_bits_dirty;\n\tbool is_amd_compatible;\n\tu32 cpu_caps[32];\n\tu64 reserved_gpa_bits;\n\tint maxphyaddr;\n\tstruct x86_emulate_ctxt *emulate_ctxt;\n\tbool emulate_regs_need_sync_to_vcpu;\n\tbool emulate_regs_need_sync_from_vcpu;\n\tint (*complete_userspace_io)(struct kvm_vcpu *);\n\tlong unsigned int cui_linear_rip;\n\tint cui_rdmsr_imm_reg;\n\tgpa_t time;\n\ts8 pvclock_tsc_shift;\n\tu32 pvclock_tsc_mul;\n\tunsigned int hw_tsc_khz;\n\tstruct gfn_to_pfn_cache pv_time;\n\tbool pvclock_set_guest_stopped_request;\n\tstruct {\n\t\tu8 preempted;\n\t\tu64 msr_val;\n\t\tu64 last_steal;\n\t\tstruct gfn_to_hva_cache cache;\n\t} st;\n\tu64 l1_tsc_offset;\n\tu64 tsc_offset;\n\tu64 last_guest_tsc;\n\tu64 last_host_tsc;\n\tu64 tsc_offset_adjustment;\n\tu64 this_tsc_nsec;\n\tu64 this_tsc_write;\n\tu64 this_tsc_generation;\n\tbool tsc_catchup;\n\tbool tsc_always_catchup;\n\ts8 virtual_tsc_shift;\n\tu32 virtual_tsc_mult;\n\tu32 virtual_tsc_khz;\n\ts64 ia32_tsc_adjust_msr;\n\tu64 msr_ia32_power_ctl;\n\tu64 l1_tsc_scaling_ratio;\n\tu64 tsc_scaling_ratio;\n\tatomic_t nmi_queued;\n\tunsigned int nmi_pending;\n\tbool nmi_injected;\n\tbool smi_pending;\n\tu8 handling_intr_from_guest;\n\tstruct kvm_mtrr mtrr_state;\n\tu64 pat;\n\tunsigned int switch_db_regs;\n\tlong unsigned int db[4];\n\tlong unsigned int dr6;\n\tlong unsigned int dr7;\n\tlong unsigned int eff_db[4];\n\tlong unsigned int guest_debug_dr7;\n\tu64 msr_platform_info;\n\tu64 msr_misc_features_enables;\n\tu64 mcg_cap;\n\tu64 mcg_status;\n\tu64 mcg_ctl;\n\tu64 mcg_ext_ctl;\n\tu64 *mce_banks;\n\tu64 *mci_ctl2_banks;\n\tu64 mmio_gva;\n\tunsigned int mmio_access;\n\tgfn_t mmio_gfn;\n\tu64 mmio_gen;\n\tstruct kvm_pmu pmu;\n\tlong unsigned int singlestep_rip;\n\tbool hyperv_enabled;\n\tstruct kvm_vcpu_hv *hyperv;\n\tcpumask_var_t wbinvd_dirty_mask;\n\tlong unsigned int last_retry_eip;\n\tlong unsigned int last_retry_addr;\n\tstruct {\n\t\tbool halted;\n\t\tgfn_t gfns[64];\n\t\tstruct gfn_to_hva_cache data;\n\t\tu64 msr_en_val;\n\t\tu64 msr_int_val;\n\t\tu16 vec;\n\t\tu32 id;\n\t\tu32 host_apf_flags;\n\t\tbool send_always;\n\t\tbool delivery_as_pf_vmexit;\n\t\tbool pageready_pending;\n\t} apf;\n\tstruct {\n\t\tu64 length;\n\t\tu64 status;\n\t} osvw;\n\tstruct {\n\t\tu64 msr_val;\n\t\tstruct gfn_to_hva_cache data;\n\t} pv_eoi;\n\tu64 msr_kvm_poll_control;\n\tstruct {\n\t\tbool pv_unhalted;\n\t} pv;\n\tint pending_ioapic_eoi;\n\tint pending_external_vector;\n\tint highest_stale_pending_ioapic_eoi;\n\tbool preempted_in_kernel;\n\tint last_vmentry_cpu;\n\tu64 msr_hwcr;\n\tstruct {\n\t\tu32 features;\n\t\tbool enforce;\n\t} pv_cpuid;\n\tbool guest_state_protected;\n\tbool guest_tsc_protected;\n\tbool pdptrs_from_userspace;\n};\n\nstruct kvm_vcpu_stat_generic {\n\tu64 halt_successful_poll;\n\tu64 halt_attempted_poll;\n\tu64 halt_poll_invalid;\n\tu64 halt_wakeup;\n\tu64 halt_poll_success_ns;\n\tu64 halt_poll_fail_ns;\n\tu64 halt_wait_ns;\n\tu64 halt_poll_success_hist[32];\n\tu64 halt_poll_fail_hist[32];\n\tu64 halt_wait_hist[32];\n\tu64 blocking;\n};\n\nstruct kvm_vcpu_stat {\n\tstruct kvm_vcpu_stat_generic generic;\n\tu64 pf_taken;\n\tu64 pf_fixed;\n\tu64 pf_emulate;\n\tu64 pf_spurious;\n\tu64 pf_fast;\n\tu64 pf_mmio_spte_created;\n\tu64 pf_guest;\n\tu64 tlb_flush;\n\tu64 invlpg;\n\tu64 exits;\n\tu64 io_exits;\n\tu64 mmio_exits;\n\tu64 signal_exits;\n\tu64 irq_window_exits;\n\tu64 nmi_window_exits;\n\tu64 l1d_flush;\n\tu64 halt_exits;\n\tu64 request_irq_exits;\n\tu64 irq_exits;\n\tu64 host_state_reload;\n\tu64 fpu_reload;\n\tu64 insn_emulation;\n\tu64 insn_emulation_fail;\n\tu64 hypercalls;\n\tu64 irq_injections;\n\tu64 nmi_injections;\n\tu64 req_event;\n\tu64 nested_run;\n\tu64 directed_yield_attempted;\n\tu64 directed_yield_successful;\n\tu64 preemption_reported;\n\tu64 preemption_other;\n\tu64 guest_mode;\n\tu64 notify_window_exits;\n};\n\nstruct kvm_vcpu {\n\tstruct kvm *kvm;\n\tstruct preempt_notifier preempt_notifier;\n\tint cpu;\n\tint vcpu_id;\n\tint vcpu_idx;\n\tint ____srcu_idx;\n\tint srcu_depth;\n\tint mode;\n\tu64 requests;\n\tlong unsigned int guest_debug;\n\tstruct mutex mutex;\n\tstruct kvm_run *run;\n\tstruct rcuwait wait;\n\tstruct pid *pid;\n\trwlock_t pid_lock;\n\tint sigset_active;\n\tsigset_t sigset;\n\tunsigned int halt_poll_ns;\n\tbool valid_wakeup;\n\tint mmio_needed;\n\tint mmio_read_completed;\n\tint mmio_is_write;\n\tint mmio_cur_fragment;\n\tint mmio_nr_fragments;\n\tstruct kvm_mmio_fragment mmio_fragments[2];\n\tstruct {\n\t\tu32 queued;\n\t\tstruct list_head queue;\n\t\tstruct list_head done;\n\t\tspinlock_t lock;\n\t} async_pf;\n\tstruct {\n\t\tbool in_spin_loop;\n\t\tbool dy_eligible;\n\t} spin_loop;\n\tbool wants_to_run;\n\tbool preempted;\n\tbool ready;\n\tbool scheduled_out;\n\tstruct kvm_vcpu_arch arch;\n\tstruct kvm_vcpu_stat stat;\n\tchar stats_id[48];\n\tstruct kvm_dirty_ring dirty_ring;\n\tstruct kvm_memory_slot *last_used_slot;\n\tu64 last_used_slot_gen;\n};\n\nstruct kvm_vcpu_hv_synic {\n\tu64 version;\n\tu64 control;\n\tu64 msg_page;\n\tu64 evt_page;\n\tatomic64_t sint[16];\n\tatomic_t sint_to_gsi[16];\n\tlong unsigned int auto_eoi_bitmap[4];\n\tlong unsigned int vec_bitmap[4];\n\tbool active;\n\tbool dont_zero_synic_pages;\n};\n\nstruct kvm_vcpu_hv_stimer {\n\tstruct hrtimer timer;\n\tint index;\n\tunion hv_stimer_config config;\n\tu64 count;\n\tu64 exp_time;\n\tstruct hv_message msg;\n\tbool msg_pending;\n};\n\nstruct kvm_vcpu_hv_tlb_flush_fifo {\n\tspinlock_t write_lock;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu64 *type;\n\t\t\tconst u64 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu64 *ptr;\n\t\t\tconst u64 *ptr_const;\n\t\t};\n\t\tu64 buf[16];\n\t} entries;\n};\n\nstruct kvm_vcpu_hv {\n\tstruct kvm_vcpu *vcpu;\n\tu32 vp_index;\n\tu64 hv_vapic;\n\ts64 runtime_offset;\n\tstruct kvm_vcpu_hv_synic synic;\n\tstruct kvm_hyperv_exit exit;\n\tstruct kvm_vcpu_hv_stimer stimer[4];\n\tlong unsigned int stimer_pending_bitmap[1];\n\tbool enforce_cpuid;\n\tstruct {\n\t\tu32 features_eax;\n\t\tu32 features_ebx;\n\t\tu32 features_edx;\n\t\tu32 enlightenments_eax;\n\t\tu32 enlightenments_ebx;\n\t\tu32 syndbg_cap_eax;\n\t\tu32 nested_eax;\n\t\tu32 nested_ebx;\n\t} cpuid_cache;\n\tstruct kvm_vcpu_hv_tlb_flush_fifo tlb_flush_fifo[2];\n\tu64 sparse_banks[64];\n\tlong unsigned int vcpu_mask[16];\n\tstruct hv_vp_assist_page vp_assist_page;\n\tstruct {\n\t\tu64 pa_page_gpa;\n\t\tu64 vm_id;\n\t\tu32 vp_id;\n\t} nested;\n};\n\nstruct kvm_vcpu_pv_apf_data {\n\t__u32 flags;\n\t__u32 token;\n\t__u8 pad[56];\n};\n\nstruct kvm_vfio {\n\tstruct list_head file_list;\n\tstruct mutex lock;\n\tbool noncoherent;\n};\n\nstruct kvm_vfio_file {\n\tstruct list_head node;\n\tstruct file *file;\n};\n\nstruct vmcb;\n\nstruct kvm_vmcb_info {\n\tstruct vmcb *ptr;\n\tlong unsigned int pa;\n\tint cpu;\n\tuint64_t asid_generation;\n};\n\nstruct kvm_vmx {\n\tstruct kvm kvm;\n\tunsigned int tss_addr;\n\tbool ept_identity_pagetable_done;\n\tgpa_t ept_identity_map_addr;\n\tu64 *pid_table;\n};\n\nstruct kvm_vmx_segment_field {\n\tunsigned int selector;\n\tunsigned int base;\n\tunsigned int limit;\n\tunsigned int ar_bytes;\n};\n\nstruct kvm_x86_ops;\n\nstruct kvm_x86_init_ops {\n\tint (*hardware_setup)(void);\n\tunsigned int (*handle_intel_pt_intr)(void);\n\tstruct kvm_x86_ops *runtime_ops;\n\tstruct kvm_pmu_ops *pmu_ops;\n};\n\nstruct kvm_x86_mce {\n\t__u64 status;\n\t__u64 addr;\n\t__u64 misc;\n\t__u64 mcg_status;\n\t__u8 bank;\n\t__u8 pad1[7];\n\t__u64 pad2[3];\n};\n\nstruct msr_bitmap_range {\n\tu32 flags;\n\tu32 nmsrs;\n\tu32 base;\n\tlong unsigned int *bitmap;\n};\n\nstruct kvm_x86_msr_filter {\n\tu8 count;\n\tbool default_allow: 1;\n\tstruct msr_bitmap_range ranges[16];\n};\n\nstruct kvm_x86_nested_ops {\n\tvoid (*leave_nested)(struct kvm_vcpu *);\n\tbool (*is_exception_vmexit)(struct kvm_vcpu *, u8, u32);\n\tint (*check_events)(struct kvm_vcpu *);\n\tbool (*has_events)(struct kvm_vcpu *, bool);\n\tvoid (*triple_fault)(struct kvm_vcpu *);\n\tint (*get_state)(struct kvm_vcpu *, struct kvm_nested_state *, unsigned int);\n\tint (*set_state)(struct kvm_vcpu *, struct kvm_nested_state *, struct kvm_nested_state *);\n\tbool (*get_nested_state_pages)(struct kvm_vcpu *);\n\tint (*write_log_dirty)(struct kvm_vcpu *, gpa_t);\n\tint (*enable_evmcs)(struct kvm_vcpu *, uint16_t *);\n\tuint16_t (*get_evmcs_version)(struct kvm_vcpu *);\n\tvoid (*hv_inject_synthetic_vmexit_post_tlb_flush)(struct kvm_vcpu *);\n};\n\ntypedef void cpu_emergency_virt_cb(void);\n\nstruct x86_instruction_info;\n\nstruct kvm_x86_ops {\n\tconst char *name;\n\tint (*check_processor_compatibility)(void);\n\tint (*enable_virtualization_cpu)(void);\n\tvoid (*disable_virtualization_cpu)(void);\n\tcpu_emergency_virt_cb *emergency_disable_virtualization_cpu;\n\tvoid (*hardware_unsetup)(void);\n\tbool (*has_emulated_msr)(struct kvm *, u32);\n\tvoid (*vcpu_after_set_cpuid)(struct kvm_vcpu *);\n\tunsigned int vm_size;\n\tint (*vm_init)(struct kvm *);\n\tvoid (*vm_destroy)(struct kvm *);\n\tvoid (*vm_pre_destroy)(struct kvm *);\n\tint (*vcpu_precreate)(struct kvm *);\n\tint (*vcpu_create)(struct kvm_vcpu *);\n\tvoid (*vcpu_free)(struct kvm_vcpu *);\n\tvoid (*vcpu_reset)(struct kvm_vcpu *, bool);\n\tvoid (*prepare_switch_to_guest)(struct kvm_vcpu *);\n\tvoid (*vcpu_load)(struct kvm_vcpu *, int);\n\tvoid (*vcpu_put)(struct kvm_vcpu *);\n\tconst u64 HOST_OWNED_DEBUGCTL;\n\tvoid (*update_exception_bitmap)(struct kvm_vcpu *);\n\tint (*get_msr)(struct kvm_vcpu *, struct msr_data *);\n\tint (*set_msr)(struct kvm_vcpu *, struct msr_data *);\n\tu64 (*get_segment_base)(struct kvm_vcpu *, int);\n\tvoid (*get_segment)(struct kvm_vcpu *, struct kvm_segment *, int);\n\tint (*get_cpl)(struct kvm_vcpu *);\n\tint (*get_cpl_no_cache)(struct kvm_vcpu *);\n\tvoid (*set_segment)(struct kvm_vcpu *, struct kvm_segment *, int);\n\tvoid (*get_cs_db_l_bits)(struct kvm_vcpu *, int *, int *);\n\tbool (*is_valid_cr0)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*set_cr0)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*post_set_cr3)(struct kvm_vcpu *, long unsigned int);\n\tbool (*is_valid_cr4)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*set_cr4)(struct kvm_vcpu *, long unsigned int);\n\tint (*set_efer)(struct kvm_vcpu *, u64);\n\tvoid (*get_idt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*set_idt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*get_gdt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*set_gdt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*sync_dirty_debug_regs)(struct kvm_vcpu *);\n\tvoid (*set_dr7)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*cache_reg)(struct kvm_vcpu *, enum kvm_reg);\n\tlong unsigned int (*get_rflags)(struct kvm_vcpu *);\n\tvoid (*set_rflags)(struct kvm_vcpu *, long unsigned int);\n\tbool (*get_if_flag)(struct kvm_vcpu *);\n\tvoid (*flush_tlb_all)(struct kvm_vcpu *);\n\tvoid (*flush_tlb_current)(struct kvm_vcpu *);\n\tvoid (*flush_tlb_gva)(struct kvm_vcpu *, gva_t);\n\tvoid (*flush_tlb_guest)(struct kvm_vcpu *);\n\tint (*vcpu_pre_run)(struct kvm_vcpu *);\n\tenum exit_fastpath_completion (*vcpu_run)(struct kvm_vcpu *, u64);\n\tint (*handle_exit)(struct kvm_vcpu *, enum exit_fastpath_completion);\n\tint (*skip_emulated_instruction)(struct kvm_vcpu *);\n\tvoid (*update_emulated_instruction)(struct kvm_vcpu *);\n\tvoid (*set_interrupt_shadow)(struct kvm_vcpu *, int);\n\tu32 (*get_interrupt_shadow)(struct kvm_vcpu *);\n\tvoid (*patch_hypercall)(struct kvm_vcpu *, unsigned char *);\n\tvoid (*inject_irq)(struct kvm_vcpu *, bool);\n\tvoid (*inject_nmi)(struct kvm_vcpu *);\n\tvoid (*inject_exception)(struct kvm_vcpu *);\n\tvoid (*cancel_injection)(struct kvm_vcpu *);\n\tint (*interrupt_allowed)(struct kvm_vcpu *, bool);\n\tint (*nmi_allowed)(struct kvm_vcpu *, bool);\n\tbool (*get_nmi_mask)(struct kvm_vcpu *);\n\tvoid (*set_nmi_mask)(struct kvm_vcpu *, bool);\n\tbool (*is_vnmi_pending)(struct kvm_vcpu *);\n\tbool (*set_vnmi_pending)(struct kvm_vcpu *);\n\tvoid (*enable_nmi_window)(struct kvm_vcpu *);\n\tvoid (*enable_irq_window)(struct kvm_vcpu *);\n\tvoid (*update_cr8_intercept)(struct kvm_vcpu *, int, int);\n\tconst bool x2apic_icr_is_split;\n\tconst long unsigned int required_apicv_inhibits;\n\tbool allow_apicv_in_x2apic_without_x2apic_virtualization;\n\tvoid (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *);\n\tvoid (*hwapic_isr_update)(struct kvm_vcpu *, int);\n\tvoid (*load_eoi_exitmap)(struct kvm_vcpu *, u64 *);\n\tvoid (*set_virtual_apic_mode)(struct kvm_vcpu *);\n\tvoid (*set_apic_access_page_addr)(struct kvm_vcpu *);\n\tvoid (*deliver_interrupt)(struct kvm_lapic *, int, int, int);\n\tint (*sync_pir_to_irr)(struct kvm_vcpu *);\n\tint (*set_tss_addr)(struct kvm *, unsigned int);\n\tint (*set_identity_map_addr)(struct kvm *, u64);\n\tu8 (*get_mt_mask)(struct kvm_vcpu *, gfn_t, bool);\n\tvoid (*load_mmu_pgd)(struct kvm_vcpu *, hpa_t, int);\n\tint (*link_external_spt)(struct kvm *, gfn_t, enum pg_level, void *);\n\tint (*set_external_spte)(struct kvm *, gfn_t, enum pg_level, u64);\n\tint (*free_external_spt)(struct kvm *, gfn_t, enum pg_level, void *);\n\tvoid (*remove_external_spte)(struct kvm *, gfn_t, enum pg_level, u64);\n\tbool (*has_wbinvd_exit)(void);\n\tu64 (*get_l2_tsc_offset)(struct kvm_vcpu *);\n\tu64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *);\n\tvoid (*write_tsc_offset)(struct kvm_vcpu *);\n\tvoid (*write_tsc_multiplier)(struct kvm_vcpu *);\n\tvoid (*get_exit_info)(struct kvm_vcpu *, u32 *, u64 *, u64 *, u32 *, u32 *);\n\tvoid (*get_entry_info)(struct kvm_vcpu *, u32 *, u32 *);\n\tint (*check_intercept)(struct kvm_vcpu *, struct x86_instruction_info *, enum x86_intercept_stage, struct x86_exception *);\n\tvoid (*handle_exit_irqoff)(struct kvm_vcpu *);\n\tvoid (*update_cpu_dirty_logging)(struct kvm_vcpu *);\n\tconst struct kvm_x86_nested_ops *nested_ops;\n\tvoid (*vcpu_blocking)(struct kvm_vcpu *);\n\tvoid (*vcpu_unblocking)(struct kvm_vcpu *);\n\tint (*pi_update_irte)(struct kvm_kernel_irqfd *, struct kvm *, unsigned int, uint32_t, struct kvm_vcpu *, u32);\n\tvoid (*pi_start_bypass)(struct kvm *);\n\tvoid (*apicv_pre_state_restore)(struct kvm_vcpu *);\n\tvoid (*apicv_post_state_restore)(struct kvm_vcpu *);\n\tbool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *);\n\tbool (*protected_apic_has_interrupt)(struct kvm_vcpu *);\n\tint (*set_hv_timer)(struct kvm_vcpu *, u64, bool *);\n\tvoid (*cancel_hv_timer)(struct kvm_vcpu *);\n\tvoid (*setup_mce)(struct kvm_vcpu *);\n\tint (*smi_allowed)(struct kvm_vcpu *, bool);\n\tint (*enter_smm)(struct kvm_vcpu *, union kvm_smram *);\n\tint (*leave_smm)(struct kvm_vcpu *, const union kvm_smram *);\n\tvoid (*enable_smi_window)(struct kvm_vcpu *);\n\tint (*dev_get_attr)(u32, u64, u64 *);\n\tint (*mem_enc_ioctl)(struct kvm *, void *);\n\tint (*vcpu_mem_enc_ioctl)(struct kvm_vcpu *, void *);\n\tint (*vcpu_mem_enc_unlocked_ioctl)(struct kvm_vcpu *, void *);\n\tint (*mem_enc_register_region)(struct kvm *, struct kvm_enc_region *);\n\tint (*mem_enc_unregister_region)(struct kvm *, struct kvm_enc_region *);\n\tint (*vm_copy_enc_context_from)(struct kvm *, unsigned int);\n\tint (*vm_move_enc_context_from)(struct kvm *, unsigned int);\n\tvoid (*guest_memory_reclaimed)(struct kvm *);\n\tint (*get_feature_msr)(u32, u64 *);\n\tint (*check_emulate_instruction)(struct kvm_vcpu *, int, void *, int);\n\tbool (*apic_init_signal_blocked)(struct kvm_vcpu *);\n\tint (*enable_l2_tlb_flush)(struct kvm_vcpu *);\n\tvoid (*migrate_timers)(struct kvm_vcpu *);\n\tvoid (*recalc_intercepts)(struct kvm_vcpu *);\n\tint (*complete_emulated_msr)(struct kvm_vcpu *, int);\n\tvoid (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *, u8);\n\tlong unsigned int (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *);\n\tgva_t (*get_untagged_addr)(struct kvm_vcpu *, gva_t, unsigned int);\n\tvoid * (*alloc_apic_backing_page)(struct kvm_vcpu *);\n\tint (*gmem_prepare)(struct kvm *, kvm_pfn_t, gfn_t, int);\n\tvoid (*gmem_invalidate)(kvm_pfn_t, kvm_pfn_t);\n\tint (*gmem_max_mapping_level)(struct kvm *, kvm_pfn_t, bool);\n};\n\nstruct kvm_x86_pmu_event_filter {\n\t__u32 action;\n\t__u32 nevents;\n\t__u32 fixed_counter_bitmap;\n\t__u32 flags;\n\t__u32 nr_includes;\n\t__u32 nr_excludes;\n\t__u64 *includes;\n\t__u64 *excludes;\n\t__u64 events[0];\n};\n\nstruct kvm_x86_reg_id {\n\t__u32 index;\n\t__u8 type;\n\t__u8 rsvd1;\n\t__u8 rsvd2: 4;\n\t__u8 size: 4;\n\t__u8 x86;\n};\n\nstruct kvm_xcr {\n\t__u32 xcr;\n\t__u32 reserved;\n\t__u64 value;\n};\n\nstruct kvm_xcrs {\n\t__u32 nr_xcrs;\n\t__u32 flags;\n\tstruct kvm_xcr xcrs[16];\n\t__u64 padding[16];\n};\n\nstruct kvm_xsave {\n\t__u32 region[1024];\n\t__u32 extra[0];\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nunion l1_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 8;\n\t\tunsigned int assoc: 8;\n\t\tunsigned int size_in_kb: 8;\n\t};\n\tunsigned int val;\n};\n\nunion l2_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 4;\n\t\tunsigned int assoc: 4;\n\t\tunsigned int size_in_kb: 16;\n\t};\n\tunsigned int val;\n};\n\nunion l3_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 4;\n\t\tunsigned int assoc: 4;\n\t\tunsigned int res: 2;\n\t\tunsigned int size_encoded: 14;\n\t};\n\tunsigned int val;\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tu64 val[2];\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct x86_pmu_lbr {\n\tunsigned int nr;\n\tunsigned int from;\n\tunsigned int to;\n\tunsigned int info;\n\tbool has_callstack;\n};\n\nstruct lbr_desc {\n\tstruct x86_pmu_lbr records;\n\tstruct perf_event *event;\n\tbool msr_passthrough;\n};\n\nstruct lcd_properties {\n\tint max_contrast;\n};\n\nstruct lcd_ops;\n\nstruct lcd_device {\n\tstruct lcd_properties props;\n\tstruct mutex ops_lock;\n\tconst struct lcd_ops *ops;\n\tstruct mutex update_lock;\n\tstruct list_head entry;\n\tstruct device dev;\n};\n\nstruct lcd_ops {\n\tint (*get_power)(struct lcd_device *);\n\tint (*set_power)(struct lcd_device *, int);\n\tint (*get_contrast)(struct lcd_device *);\n\tint (*set_contrast)(struct lcd_device *, int);\n\tint (*set_mode)(struct lcd_device *, u32, u32);\n\tbool (*controls_device)(struct lcd_device *, struct device *);\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n\tstruct lockdep_map dep_map;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct ldt_struct {\n\tstruct desc_struct *entries;\n\tunsigned int nr_entries;\n\tint slot;\n};\n\nstruct ldttss_desc {\n\tu16 limit0;\n\tu16 base0;\n\tu16 base1: 8;\n\tu16 type: 5;\n\tu16 dpl: 2;\n\tu16 p: 1;\n\tu16 limit1: 4;\n\tu16 zero0: 3;\n\tu16 g: 1;\n\tu16 base2: 8;\n\tu32 base3;\n\tu32 zero1;\n};\n\ntypedef struct ldttss_desc ldt_desc;\n\ntypedef struct ldttss_desc tss_desc;\n\nstruct leaf_0x2_reg {\n\tint: 31;\n\tu32 invalid: 1;\n};\n\nunion leaf_0x2_regs {\n\tstruct leaf_0x2_reg reg[4];\n\tu32 regv[4];\n\tu8 desc[16];\n};\n\nstruct leaf_0x2_table {\n\tunion {\n\t\tenum _cache_table_type c_type;\n\t\tenum _tlb_table_type t_type;\n\t};\n\tunion {\n\t\tshort int c_size;\n\t\tshort int entries;\n\t};\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct mc_subled;\n\nstruct led_classdev_mc {\n\tstruct led_classdev led_cdev;\n\tunsigned int num_colors;\n\tstruct mc_subled *subled_info;\n};\n\nstruct led_hw_trigger_type {\n\tint dummy;\n};\n\nstruct led_init_data {\n\tstruct fwnode_handle *fwnode;\n\tconst char *default_label;\n\tconst char *devicename;\n\tbool devname_mandatory;\n};\n\nstruct led_lookup_data {\n\tstruct list_head list;\n\tconst char *provider;\n\tconst char *dev_id;\n\tconst char *con_id;\n};\n\nstruct led_pattern {\n\tu32 delta_t;\n\tint brightness;\n};\n\nstruct led_properties {\n\tu32 color;\n\tbool color_present;\n\tconst char *function;\n\tu32 func_enum;\n\tbool func_enum_present;\n\tconst char *label;\n};\n\nstruct legacy_pic {\n\tint nr_legacy_irqs;\n\tstruct irq_chip *chip;\n\tvoid (*mask)(unsigned int);\n\tvoid (*unmask)(unsigned int);\n\tvoid (*mask_all)(void);\n\tvoid (*restore_mask)(void);\n\tvoid (*init)(int);\n\tint (*probe)(void);\n\tint (*irq_pending)(unsigned int);\n\tvoid (*make_irq)(unsigned int);\n};\n\nstruct legacy_ring {\n\tstruct intel_gt *gt;\n\tu8 class;\n\tu8 instance;\n};\n\nstruct lifebook_data {\n\tstruct input_dev *dev2;\n\tchar phys[32];\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linear_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_capabilities {\n\tint speed;\n\tunsigned int duplex;\n\tlong unsigned int linkmodes[2];\n};\n\nstruct link_config_limits {\n\tint min_rate;\n\tint max_rate;\n\tint min_lane_count;\n\tint max_lane_count;\n\tstruct {\n\t\tint min_bpp;\n\t\tint max_bpp;\n\t} pipe;\n\tstruct {\n\t\tint min_bpp_x16;\n\t\tint max_bpp_x16;\n\t} link;\n};\n\nstruct link_ctl_info {\n\tsnd_ctl_elem_type_t type;\n\tint count;\n\tint min_val;\n\tint max_val;\n};\n\nstruct snd_ctl_elem_id {\n\tunsigned int numid;\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tunsigned char name[44];\n\tunsigned int index;\n};\n\nstruct snd_ctl_elem_info;\n\ntypedef int snd_kcontrol_info_t(struct snd_kcontrol *, struct snd_ctl_elem_info *);\n\ntypedef int snd_kcontrol_get_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_put_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_tlv_rw_t(struct snd_kcontrol *, int, unsigned int, unsigned int *);\n\nstruct snd_ctl_file;\n\nstruct snd_kcontrol_volatile {\n\tstruct snd_ctl_file *owner;\n\tunsigned int access;\n};\n\nstruct snd_kcontrol {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_kcontrol *);\n\tstruct snd_kcontrol_volatile vd[0];\n};\n\nstruct link_master;\n\nstruct link_follower {\n\tstruct list_head list;\n\tstruct link_master *master;\n\tstruct link_ctl_info info;\n\tint vals[2];\n\tunsigned int flags;\n\tstruct snd_kcontrol *kctl;\n\tstruct snd_kcontrol follower;\n};\n\nstruct link_master {\n\tstruct list_head followers;\n\tstruct link_ctl_info info;\n\tint val;\n\tunsigned int tlv[4];\n\tvoid (*hook)(void *, int);\n\tvoid *hook_private_data;\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct linked_page {\n\tstruct linked_page *next;\n\tchar data[4088];\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n};\n\nstruct linux_efi_initrd {\n\tlong unsigned int base;\n\tlong unsigned int size;\n};\n\nstruct linux_efi_memreserve {\n\tint size;\n\tatomic_t count;\n\tphys_addr_t next;\n\tstruct {\n\t\tphys_addr_t base;\n\t\tphys_addr_t size;\n\t} entry[0];\n};\n\nstruct linux_efi_random_seed {\n\tu32 size;\n\tu8 bits[0];\n};\n\nstruct linux_efi_tpm_eventlog {\n\tu32 size;\n\tu32 final_events_preboot_size;\n\tu8 version;\n\tu8 log[0];\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n\tstruct lock_class_key *key;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct listener {\n\tstruct list_head list;\n\tpid_t pid;\n\tchar valid;\n};\n\nstruct listener_list {\n\tstruct rw_semaphore sem;\n\tstruct list_head list;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf64_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct vmcs_host_state {\n\tlong unsigned int cr3;\n\tlong unsigned int cr4;\n\tlong unsigned int gs_base;\n\tlong unsigned int fs_base;\n\tlong unsigned int rsp;\n\tu16 fs_sel;\n\tu16 gs_sel;\n\tu16 ldt_sel;\n\tu16 ds_sel;\n\tu16 es_sel;\n};\n\nstruct vmcs_controls_shadow {\n\tu32 vm_entry;\n\tu32 vm_exit;\n\tu32 pin;\n\tu32 exec;\n\tu32 secondary_exec;\n\tu64 tertiary_exec;\n};\n\nstruct vmcs;\n\nstruct loaded_vmcs {\n\tstruct vmcs *vmcs;\n\tstruct vmcs *shadow_vmcs;\n\tint cpu;\n\tbool launched;\n\tbool nmi_known_unmasked;\n\tbool hv_timer_soft_disabled;\n\tint soft_vnmi_blocked;\n\tktime_t entry_time;\n\ts64 vnmi_blocked_time;\n\tlong unsigned int *msr_bitmap;\n\tstruct list_head loaded_vmcss_on_cpu_link;\n\tstruct vmcs_host_state host_state;\n\tstruct vmcs_controls_shadow controls_shadow;\n};\n\nstruct location;\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n\tloff_t idx;\n};\n\nstruct local_event {\n\tlocal_lock_t lock;\n\t__u32 count;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tstruct lockdep_map dep_map;\n\tstruct task_struct *owner;\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct location {\n\tdepot_stack_handle_t handle;\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong unsigned int waste;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[1];\n\tnodemask_t nodes;\n};\n\nstruct lock_chain {\n\tunsigned int irq_context: 2;\n\tunsigned int depth: 6;\n\tunsigned int base: 24;\n\tstruct hlist_node entry;\n\tu64 chain_key;\n};\n\ntypedef int (*lock_cmp_fn)(const struct lockdep_map *, const struct lockdep_map *);\n\ntypedef void (*lock_print_fn)(const struct lockdep_map *);\n\nstruct lock_trace;\n\nstruct lock_class {\n\tstruct hlist_node hash_entry;\n\tstruct list_head lock_entry;\n\tstruct list_head locks_after;\n\tstruct list_head locks_before;\n\tconst struct lockdep_subclass_key *key;\n\tlock_cmp_fn cmp_fn;\n\tlock_print_fn print_fn;\n\tunsigned int subclass;\n\tunsigned int dep_gen_id;\n\tlong unsigned int usage_mask;\n\tconst struct lock_trace *usage_traces[10];\n\tconst char *name;\n\tint name_version;\n\tu8 wait_type_inner;\n\tu8 wait_type_outer;\n\tu8 lock_type;\n};\n\nstruct lock_list {\n\tstruct list_head entry;\n\tstruct lock_class *class;\n\tstruct lock_class *links_to;\n\tconst struct lock_trace *trace;\n\tu16 distance;\n\tu8 dep;\n\tu8 only_xr;\n\tstruct lock_list *parent;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct lock_trace {\n\tstruct hlist_node hash_entry;\n\tu32 hash;\n\tu32 nr_entries;\n\tlong unsigned int entries[0];\n};\n\nstruct lockdep_stats {\n\tlong unsigned int chain_lookup_hits;\n\tunsigned int chain_lookup_misses;\n\tlong unsigned int hardirqs_on_events;\n\tlong unsigned int hardirqs_off_events;\n\tlong unsigned int redundant_hardirqs_on;\n\tlong unsigned int redundant_hardirqs_off;\n\tlong unsigned int softirqs_on_events;\n\tlong unsigned int softirqs_off_events;\n\tlong unsigned int redundant_softirqs_on;\n\tlong unsigned int redundant_softirqs_off;\n\tint nr_unused_locks;\n\tunsigned int nr_redundant_checks;\n\tunsigned int nr_redundant;\n\tunsigned int nr_cyclic_checks;\n\tunsigned int nr_find_usage_forwards_checks;\n\tunsigned int nr_find_usage_backwards_checks;\n\tlong unsigned int lock_class_ops[8192];\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tloff_t li_pos;\n};\n\nstruct log_header_core {\n\tuint32_t magic;\n\tuint32_t version;\n\tuint64_t nr_regions;\n};\n\nstruct log_header_disk;\n\nstruct log_c {\n\tstruct dm_target *ti;\n\tint touched_dirtied;\n\tint touched_cleaned;\n\tint flush_failed;\n\tuint32_t region_size;\n\tunsigned int region_count;\n\tregion_t sync_count;\n\tunsigned int bitset_uint32_count;\n\tuint32_t *clean_bits;\n\tuint32_t *sync_bits;\n\tuint32_t *recovering_bits;\n\tint sync_search;\n\tenum sync sync;\n\tstruct dm_io_request io_req;\n\tint log_dev_failed;\n\tint log_dev_flush_failed;\n\tstruct dm_dev *log_dev;\n\tstruct log_header_core header;\n\tstruct dm_io_region header_location;\n\tstruct log_header_disk *disk_header;\n};\n\nstruct log_header_disk {\n\t__le32 magic;\n\t__le32 version;\n\t__le64 nr_regions;\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct loop_cmd {\n\tstruct list_head list_entry;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct cgroup_subsys_state *memcg_css;\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nstruct loop_device {\n\tint lo_number;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tchar lo_file_name[64];\n\tstruct file *lo_backing_file;\n\tunsigned int lo_min_dio_size;\n\tstruct block_device *lo_device;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tspinlock_t lo_work_lock;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rootcg_work;\n\tstruct list_head rootcg_cmd_list;\n\tstruct list_head idle_worker_list;\n\tstruct rb_root worker_tree;\n\tstruct timer_list timer;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n\tstruct mutex lo_mutex;\n\tbool idr_visible;\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_worker {\n\tstruct rb_node rb_node;\n\tstruct work_struct work;\n\tstruct list_head cmd_list;\n\tstruct list_head idle_list;\n\tstruct loop_device *lo;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tlong unsigned int last_ran_at;\n};\n\nunion lower_chunk {\n\tunion lower_chunk *next;\n\tlong unsigned int data[256];\n};\n\nstruct lpi_constraints {\n\tacpi_handle handle;\n\tint min_dstate;\n};\n\nstruct lpi_device_constraint {\n\tint uid;\n\tint min_dstate;\n\tint function_states;\n};\n\nstruct lpi_device_constraint_amd {\n\tchar *name;\n\tint enabled;\n\tint function_states;\n\tint min_dstate;\n};\n\nstruct lpi_device_info {\n\tchar *name;\n\tint enabled;\n\tunion acpi_object *package;\n};\n\nstruct lpit_residency_info {\n\tstruct acpi_generic_address gaddr;\n\tu64 frequency;\n\tvoid *iomem_addr;\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct lpss8250_board;\n\nstruct lpss8250 {\n\tstruct dw8250_port_data data;\n\tstruct lpss8250_board *board;\n\tstruct dw_dma_chip dma_chip;\n\tstruct dw_dma_slave dma_param;\n\tu8 dma_maxburst;\n};\n\nstruct lpss8250_board {\n\tlong unsigned int freq;\n\tunsigned int base_baud;\n\tint (*setup)(struct lpss8250 *, struct uart_port *);\n\tvoid (*exit)(struct lpss8250 *);\n};\n\nstruct lri {\n\ti915_reg_t reg;\n\tu32 value;\n};\n\nstruct zswap_lruvec_state {};\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct skcipher_alg_common {\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct lskcipher_alg {\n\tint (*setkey)(struct crypto_lskcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*decrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*init)(struct crypto_lskcipher *);\n\tvoid (*exit)(struct crypto_lskcipher *);\n\tstruct skcipher_alg_common co;\n};\n\nstruct lskcipher_instance {\n\tvoid (*free)(struct lskcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct lskcipher_alg alg;\n\t};\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct phy_param_t {\n\tu32 val;\n\tu32 addr;\n};\n\nstruct lt_phy_params {\n\tstruct phy_param_t pll_reg4;\n\tstruct phy_param_t pll_reg3;\n\tstruct phy_param_t pll_reg5;\n\tstruct phy_param_t pll_reg57;\n\tstruct phy_param_t lf;\n\tstruct phy_param_t tdc;\n\tstruct phy_param_t ssc;\n\tstruct phy_param_t bias2;\n\tstruct phy_param_t bias_trim;\n\tstruct phy_param_t dco_med;\n\tstruct phy_param_t dco_fine;\n\tstruct phy_param_t ssc_inj;\n\tstruct phy_param_t surv_bonus;\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct machine_ops {\n\tvoid (*restart)(char *);\n\tvoid (*halt)(void);\n\tvoid (*power_off)(void);\n\tvoid (*shutdown)(void);\n\tvoid (*crash_shutdown)(struct pt_regs *);\n\tvoid (*emergency_restart)(void);\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct mafield {\n\tconst char *prefix;\n\tint field;\n};\n\nstruct map_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct efi_runtime_map_entry *, char *);\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct map_info___2 {\n\tstruct map_info___2 *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct map_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int page_size_mask;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[9];\n\tvoid *slot[10];\n\tlong unsigned int gap[10];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[33];\n\tunion {\n\t\tstruct maple_enode *slot[34];\n\t\tstruct {\n\t\t\tlong unsigned int padding[21];\n\t\t\tlong unsigned int gap[21];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[15];\n\tunion {\n\t\tvoid *slot[16];\n\t\tstruct {\n\t\t\tvoid *pad[15];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[31];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct mapped_device {\n\tstruct mutex suspend_lock;\n\tstruct mutex table_devices_lock;\n\tstruct list_head table_devices;\n\tvoid *map;\n\tlong unsigned int flags;\n\tstruct mutex type_lock;\n\tenum dm_queue_mode type;\n\tint numa_node_id;\n\tstruct request_queue *queue;\n\tatomic_t holders;\n\tatomic_t open_count;\n\tstruct dm_target *immutable_target;\n\tstruct target_type *immutable_target_type;\n\tchar name[16];\n\tstruct gendisk *disk;\n\tstruct dax_device *dax_dev;\n\twait_queue_head_t wait;\n\tlong unsigned int *pending_io;\n\tstruct hd_geometry geometry;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct work;\n\tspinlock_t deferred_lock;\n\tstruct bio_list deferred;\n\tstruct work_struct requeue_work;\n\tstruct dm_io *requeue_list;\n\tvoid *interface_ptr;\n\twait_queue_head_t eventq;\n\tatomic_t event_nr;\n\tatomic_t uevent_seq;\n\tstruct list_head uevent_list;\n\tspinlock_t uevent_lock;\n\tbool init_tio_pdu: 1;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct dm_stats stats;\n\tunsigned int internal_suspend_count;\n\tint swap_bios;\n\tstruct semaphore swap_bios_semaphore;\n\tstruct mutex swap_bios_lock;\n\tstruct dm_md_mempools *mempools;\n\tstruct dm_kobject_holder kobj_holder;\n\tstruct srcu_struct io_barrier;\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct math_emu_info {\n\tlong int ___orig_eip;\n\tstruct pt_regs *regs;\n};\n\nstruct mbox_controller;\n\nstruct mbox_client;\n\nstruct mbox_chan {\n\tstruct mbox_controller *mbox;\n\tunsigned int txdone_method;\n\tstruct mbox_client *cl;\n\tstruct completion tx_complete;\n\tvoid *active_req;\n\tunsigned int msg_count;\n\tunsigned int msg_free;\n\tvoid *msg_data[20];\n\tspinlock_t lock;\n\tvoid *con_priv;\n};\n\nstruct mbox_chan_ops {\n\tint (*send_data)(struct mbox_chan *, void *);\n\tint (*flush)(struct mbox_chan *, long unsigned int);\n\tint (*startup)(struct mbox_chan *);\n\tvoid (*shutdown)(struct mbox_chan *);\n\tbool (*last_tx_done)(struct mbox_chan *);\n\tbool (*peek_data)(struct mbox_chan *);\n};\n\nstruct mbox_client {\n\tstruct device *dev;\n\tbool tx_block;\n\tlong unsigned int tx_tout;\n\tbool knows_txdone;\n\tvoid (*rx_callback)(struct mbox_client *, void *);\n\tvoid (*tx_prepare)(struct mbox_client *, void *);\n\tvoid (*tx_done)(struct mbox_client *, void *, int);\n};\n\nstruct mbox_controller {\n\tstruct device *dev;\n\tconst struct mbox_chan_ops *ops;\n\tstruct mbox_chan *chans;\n\tint num_chans;\n\tbool txdone_irq;\n\tbool txdone_poll;\n\tunsigned int txpoll_period;\n\tstruct mbox_chan * (*fw_xlate)(struct mbox_controller *, const struct fwnode_reference_args *);\n\tstruct mbox_chan * (*of_xlate)(struct mbox_controller *, const struct of_phandle_args *);\n\tstruct hrtimer poll_hrt;\n\tspinlock_t poll_hrt_lock;\n\tstruct list_head node;\n};\n\nstruct mc146818_get_time_callback_param {\n\tstruct rtc_time *time;\n\tunsigned char ctrl;\n\tunsigned char century;\n};\n\nstruct mc_subled {\n\tunsigned int color_index;\n\tunsigned int brightness;\n\tunsigned int intensity;\n\tunsigned int channel;\n};\n\nstruct mca_config {\n\t__u64 lmce_disabled: 1;\n\t__u64 disabled: 1;\n\t__u64 ser: 1;\n\t__u64 recovery: 1;\n\t__u64 bios_cmci_threshold: 1;\n\t__u64 initialized: 1;\n\t__u64 __reserved: 58;\n\tbool dont_log_ce;\n\tbool cmci_disabled;\n\tbool ignore_ce;\n\tbool print_all;\n\tint monarch_timeout;\n\tint panic_timeout;\n\tu32 rip_msr;\n\ts8 bootlog;\n};\n\nstruct storm_bank {\n\tu64 history;\n\tu64 timestamp;\n\tbool in_storm_mode;\n\tbool poll_only;\n};\n\nstruct mca_storm_desc {\n\tstruct storm_bank banks[64];\n\tu8 stormy_bank_count;\n\tbool poll_mode;\n};\n\nstruct mce {\n\t__u64 status;\n\t__u64 misc;\n\t__u64 addr;\n\t__u64 mcgstatus;\n\t__u64 ip;\n\t__u64 tsc;\n\t__u64 time;\n\t__u8 cpuvendor;\n\t__u8 inject_flags;\n\t__u8 severity;\n\t__u8 pad;\n\t__u32 cpuid;\n\t__u8 cs;\n\t__u8 bank;\n\t__u8 cpu;\n\t__u8 finished;\n\t__u32 extcpu;\n\t__u32 socketid;\n\t__u32 apicid;\n\t__u64 mcgcap;\n\t__u64 synd;\n\t__u64 ipid;\n\t__u64 ppin;\n\t__u32 microcode;\n\t__u64 kflags;\n};\n\nstruct mce_amd_cpu_data {\n\tmce_banks_t thr_intr_banks;\n\tmce_banks_t dfr_intr_banks;\n\tu32 thr_intr_en: 1;\n\tu32 dfr_intr_en: 1;\n\tu32 __resv: 30;\n};\n\nstruct mce_bank {\n\tu64 ctl;\n\t__u64 init: 1;\n\t__u64 lsb_in_status: 1;\n\t__u64 __reserved_1: 62;\n};\n\nstruct mce_bank_dev {\n\tstruct device_attribute attr;\n\tchar attrname[16];\n\tu8 bank;\n};\n\nunion vendor_info {\n\tstruct {\n\t\tu64 synd1;\n\t\tu64 synd2;\n\t} amd;\n};\n\nstruct mce_hw_err {\n\tstruct mce m;\n\tunion vendor_info vendor;\n};\n\nstruct mce_evt_llist {\n\tstruct llist_node llnode;\n\tstruct mce_hw_err err;\n};\n\nstruct mce_vendor_flags {\n\t__u64 overflow_recov: 1;\n\t__u64 succor: 1;\n\t__u64 smca: 1;\n\t__u64 zen_ifu_quirk: 1;\n\t__u64 amd_threshold: 1;\n\t__u64 p5: 1;\n\t__u64 winchip: 1;\n\t__u64 snb_ifu_quirk: 1;\n\t__u64 skx_repmov_quirk: 1;\n\t__u64 __reserved_0: 55;\n};\n\nstruct mcs_spinlock {\n\tstruct mcs_spinlock *next;\n\tint locked;\n\tint count;\n};\n\nstruct md_bitmap_stats {\n\tu64 events_cleared;\n\tint behind_writes;\n\tbool behind_wait;\n\tlong unsigned int missing_pages;\n\tlong unsigned int file_pages;\n\tlong unsigned int sync_size;\n\tlong unsigned int pages;\n\tstruct file *file;\n};\n\nstruct md_rdev;\n\nstruct md_cluster_operations {\n\tstruct md_submodule_head head;\n\tint (*join)(struct mddev *, int);\n\tint (*leave)(struct mddev *);\n\tint (*slot_number)(struct mddev *);\n\tint (*resync_info_update)(struct mddev *, sector_t, sector_t);\n\tint (*resync_start_notify)(struct mddev *);\n\tint (*resync_status_get)(struct mddev *);\n\tvoid (*resync_info_get)(struct mddev *, sector_t *, sector_t *);\n\tint (*metadata_update_start)(struct mddev *);\n\tint (*metadata_update_finish)(struct mddev *);\n\tvoid (*metadata_update_cancel)(struct mddev *);\n\tint (*resync_start)(struct mddev *);\n\tint (*resync_finish)(struct mddev *);\n\tint (*area_resyncing)(struct mddev *, int, sector_t, sector_t);\n\tint (*add_new_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*add_new_disk_cancel)(struct mddev *);\n\tint (*new_disk_ack)(struct mddev *, bool);\n\tint (*remove_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*load_bitmaps)(struct mddev *, int);\n\tint (*gather_bitmaps)(struct md_rdev *);\n\tint (*resize_bitmaps)(struct mddev *, sector_t, sector_t);\n\tint (*lock_all_bitmaps)(struct mddev *);\n\tvoid (*unlock_all_bitmaps)(struct mddev *);\n\tvoid (*update_size)(struct mddev *, sector_t);\n};\n\nstruct md_io_clone {\n\tstruct mddev *mddev;\n\tstruct bio *orig_bio;\n\tlong unsigned int start_time;\n\tsector_t offset;\n\tlong unsigned int sectors;\n\tenum stat_group rw;\n\tstruct bio bio_clone;\n};\n\nstruct md_personality {\n\tstruct md_submodule_head head;\n\tbool (*make_request)(struct mddev *, struct bio *);\n\tint (*run)(struct mddev *);\n\tint (*start)(struct mddev *);\n\tvoid (*free)(struct mddev *, void *);\n\tvoid (*status)(struct seq_file *, struct mddev *);\n\tvoid (*error_handler)(struct mddev *, struct md_rdev *);\n\tint (*hot_add_disk)(struct mddev *, struct md_rdev *);\n\tint (*hot_remove_disk)(struct mddev *, struct md_rdev *);\n\tint (*spare_active)(struct mddev *);\n\tsector_t (*sync_request)(struct mddev *, sector_t, sector_t, int *);\n\tint (*resize)(struct mddev *, sector_t);\n\tsector_t (*size)(struct mddev *, sector_t, int);\n\tint (*check_reshape)(struct mddev *);\n\tint (*start_reshape)(struct mddev *);\n\tvoid (*finish_reshape)(struct mddev *);\n\tvoid (*update_reshape_pos)(struct mddev *);\n\tvoid (*prepare_suspend)(struct mddev *);\n\tvoid (*quiesce)(struct mddev *, int);\n\tvoid * (*takeover)(struct mddev *);\n\tint (*change_consistency_policy)(struct mddev *, const char *);\n\tvoid (*bitmap_sector)(struct mddev *, sector_t *, long unsigned int *);\n};\n\nstruct serial_in_rdev;\n\nstruct md_rdev {\n\tstruct list_head same_set;\n\tsector_t sectors;\n\tstruct mddev *mddev;\n\tlong unsigned int last_events;\n\tstruct block_device *meta_bdev;\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct page *sb_page;\n\tstruct page *bb_page;\n\tint sb_loaded;\n\t__u64 sb_events;\n\tsector_t data_offset;\n\tsector_t new_data_offset;\n\tsector_t sb_start;\n\tint sb_size;\n\tint preferred_minor;\n\tstruct kobject kobj;\n\tlong unsigned int flags;\n\twait_queue_head_t blocked_wait;\n\tint desc_nr;\n\tint raid_disk;\n\tint new_raid_disk;\n\tint saved_raid_disk;\n\tunion {\n\t\tsector_t recovery_offset;\n\t\tsector_t journal_tail;\n\t};\n\tatomic_t nr_pending;\n\tatomic_t read_errors;\n\ttime64_t last_read_error;\n\tatomic_t corrected_errors;\n\tstruct serial_in_rdev *serial;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_unack_badblocks;\n\tstruct kernfs_node *sysfs_badblocks;\n\tstruct badblocks badblocks;\n\tstruct {\n\t\tshort int offset;\n\t\tunsigned int size;\n\t\tsector_t sector;\n\t} ppl;\n};\n\nstruct md_setup_args {\n\tint minor;\n\tint partitioned;\n\tint level;\n\tint chunk;\n\tchar *device_names;\n};\n\nstruct md_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mddev *, char *);\n\tssize_t (*store)(struct mddev *, const char *, size_t);\n};\n\nstruct md_thread {\n\tvoid (*run)(struct md_thread *);\n\tstruct mddev *mddev;\n\twait_queue_head_t wqueue;\n\tlong unsigned int flags;\n\tstruct task_struct *tsk;\n\tlong unsigned int timeout;\n\tvoid *private;\n};\n\nstruct md_cluster_info;\n\nstruct mddev {\n\tvoid *private;\n\tstruct md_personality *pers;\n\tdev_t unit;\n\tint md_minor;\n\tstruct list_head disks;\n\tlong unsigned int flags;\n\tlong unsigned int sb_flags;\n\tint suspended;\n\tstruct mutex suspend_mutex;\n\tstruct percpu_ref active_io;\n\tint ro;\n\tint sysfs_active;\n\tstruct gendisk *gendisk;\n\tstruct gendisk *dm_gendisk;\n\tstruct kobject kobj;\n\tint hold_active;\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tint persistent;\n\tint external;\n\tchar metadata_type[17];\n\tint chunk_sectors;\n\ttime64_t ctime;\n\ttime64_t utime;\n\tint level;\n\tint layout;\n\tchar clevel[16];\n\tint raid_disks;\n\tint max_disks;\n\tsector_t dev_sectors;\n\tsector_t array_sectors;\n\tint external_size;\n\tunsigned int logical_block_size;\n\t__u64 events;\n\tint can_decrease_events;\n\tchar uuid[16];\n\tsector_t reshape_position;\n\tint delta_disks;\n\tint new_level;\n\tint new_layout;\n\tint new_chunk_sectors;\n\tint reshape_backwards;\n\tstruct md_thread *thread;\n\tstruct md_thread *sync_thread;\n\tenum sync_action last_sync_action;\n\tsector_t curr_resync;\n\tsector_t curr_resync_completed;\n\tlong unsigned int resync_mark;\n\tsector_t resync_mark_cnt;\n\tsector_t curr_mark_cnt;\n\tsector_t resync_max_sectors;\n\tatomic64_t resync_mismatches;\n\tsector_t suspend_lo;\n\tsector_t suspend_hi;\n\tint sync_speed_min;\n\tint sync_speed_max;\n\tint sync_io_depth;\n\tint parallel_resync;\n\tint ok_start_degraded;\n\tlong unsigned int recovery;\n\tint in_sync;\n\tstruct mutex open_mutex;\n\tstruct mutex reconfig_mutex;\n\tatomic_t active;\n\tatomic_t openers;\n\tint changed;\n\tint degraded;\n\tlong unsigned int normal_io_events;\n\tatomic_t recovery_active;\n\twait_queue_head_t recovery_wait;\n\tsector_t resync_offset;\n\tsector_t resync_min;\n\tsector_t resync_max;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_action;\n\tstruct kernfs_node *sysfs_completed;\n\tstruct kernfs_node *sysfs_degraded;\n\tstruct kernfs_node *sysfs_level;\n\tstruct work_struct del_work;\n\tstruct work_struct sync_work;\n\tspinlock_t lock;\n\twait_queue_head_t sb_wait;\n\tatomic_t pending_writes;\n\tunsigned int safemode;\n\tunsigned int safemode_delay;\n\tstruct timer_list safemode_timer;\n\tstruct percpu_ref writes_pending;\n\tint sync_checkers;\n\tenum md_submodule_id bitmap_id;\n\tvoid *bitmap;\n\tstruct bitmap_operations *bitmap_ops;\n\tstruct {\n\t\tstruct file *file;\n\t\tloff_t offset;\n\t\tlong unsigned int space;\n\t\tloff_t default_offset;\n\t\tlong unsigned int default_space;\n\t\tstruct mutex mutex;\n\t\tlong unsigned int chunksize;\n\t\tlong unsigned int daemon_sleep;\n\t\tlong unsigned int max_write_behind;\n\t\tint external;\n\t\tint nodes;\n\t\tchar cluster_name[64];\n\t} bitmap_info;\n\tatomic_t max_corr_read_errors;\n\tstruct list_head all_mddevs;\n\tconst struct attribute_group *to_remove;\n\tstruct bio_set bio_set;\n\tstruct bio_set sync_set;\n\tstruct bio_set io_clone_set;\n\tstruct work_struct event_work;\n\tmempool_t *serial_info_pool;\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tstruct md_cluster_info *cluster_info;\n\tstruct md_cluster_operations *cluster_ops;\n\tunsigned int good_device_nr;\n\tunsigned int noio_flag;\n\tstruct list_head deleting;\n\tatomic_t sync_seq;\n};\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct mii_bus;\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n\tvoid (*shutdown)(struct mdio_device *);\n};\n\nstruct mdiobus_devres {\n\tstruct mii_bus *mii;\n};\n\nstruct mdp_device_descriptor_s {\n\t__u32 number;\n\t__u32 major;\n\t__u32 minor;\n\t__u32 raid_disk;\n\t__u32 state;\n\t__u32 reserved[27];\n};\n\ntypedef struct mdp_device_descriptor_s mdp_disk_t;\n\nstruct mdp_superblock_1 {\n\t__le32 magic;\n\t__le32 major_version;\n\t__le32 feature_map;\n\t__le32 pad0;\n\t__u8 set_uuid[16];\n\tchar set_name[32];\n\t__le64 ctime;\n\t__le32 level;\n\t__le32 layout;\n\t__le64 size;\n\t__le32 chunksize;\n\t__le32 raid_disks;\n\tunion {\n\t\t__le32 bitmap_offset;\n\t\tstruct {\n\t\t\t__le16 offset;\n\t\t\t__le16 size;\n\t\t} ppl;\n\t};\n\t__le32 new_level;\n\t__le64 reshape_position;\n\t__le32 delta_disks;\n\t__le32 new_layout;\n\t__le32 new_chunk;\n\t__le32 new_offset;\n\t__le64 data_offset;\n\t__le64 data_size;\n\t__le64 super_offset;\n\tunion {\n\t\t__le64 recovery_offset;\n\t\t__le64 journal_tail;\n\t};\n\t__le32 dev_number;\n\t__le32 cnt_corrected_read;\n\t__u8 device_uuid[16];\n\t__u8 devflags;\n\t__u8 bblog_shift;\n\t__le16 bblog_size;\n\t__le32 bblog_offset;\n\t__le64 utime;\n\t__le64 events;\n\t__le64 resync_offset;\n\t__le32 sb_csum;\n\t__le32 max_dev;\n\t__le32 logical_block_size;\n\t__u8 pad3[28];\n\t__le16 dev_roles[0];\n};\n\nstruct mdp_superblock_s {\n\t__u32 md_magic;\n\t__u32 major_version;\n\t__u32 minor_version;\n\t__u32 patch_version;\n\t__u32 gvalid_words;\n\t__u32 set_uuid0;\n\t__u32 ctime;\n\t__u32 level;\n\t__u32 size;\n\t__u32 nr_disks;\n\t__u32 raid_disks;\n\t__u32 md_minor;\n\t__u32 not_persistent;\n\t__u32 set_uuid1;\n\t__u32 set_uuid2;\n\t__u32 set_uuid3;\n\t__u32 gstate_creserved[16];\n\t__u32 utime;\n\t__u32 state;\n\t__u32 active_disks;\n\t__u32 working_disks;\n\t__u32 failed_disks;\n\t__u32 spare_disks;\n\t__u32 sb_csum;\n\t__u32 events_lo;\n\t__u32 events_hi;\n\t__u32 cp_events_lo;\n\t__u32 cp_events_hi;\n\t__u32 recovery_cp;\n\t__u64 reshape_position;\n\t__u32 new_level;\n\t__u32 delta_disks;\n\t__u32 new_layout;\n\t__u32 new_chunk;\n\t__u32 gstate_sreserved[14];\n\t__u32 layout;\n\t__u32 chunk_size;\n\t__u32 root_pv;\n\t__u32 root_block;\n\t__u32 pstate_reserved[60];\n\tmdp_disk_t disks[27];\n\t__u32 reserved[0];\n\tmdp_disk_t this_disk;\n};\n\ntypedef struct mdp_superblock_s mdp_super_t;\n\nstruct mdu_array_info_s {\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tunsigned int ctime;\n\tint level;\n\tint size;\n\tint nr_disks;\n\tint raid_disks;\n\tint md_minor;\n\tint not_persistent;\n\tunsigned int utime;\n\tint state;\n\tint active_disks;\n\tint working_disks;\n\tint failed_disks;\n\tint spare_disks;\n\tint layout;\n\tint chunk_size;\n};\n\ntypedef struct mdu_array_info_s mdu_array_info_t;\n\nstruct mdu_bitmap_file_s {\n\tchar pathname[4096];\n};\n\ntypedef struct mdu_bitmap_file_s mdu_bitmap_file_t;\n\nstruct mdu_disk_info_s {\n\tint number;\n\tint major;\n\tint minor;\n\tint raid_disk;\n\tint state;\n};\n\ntypedef struct mdu_disk_info_s mdu_disk_info_t;\n\nstruct mdu_version_s {\n\tint major;\n\tint minor;\n\tint patchlevel;\n};\n\ntypedef struct mdu_version_s mdu_version_t;\n\nstruct measure_breadcrumb {\n\tstruct i915_request rq;\n\tstruct intel_ring ring;\n\tu32 cs[2048];\n};\n\nstruct mei_aux_device {\n\tstruct auxiliary_device aux_dev;\n\tint irq;\n\tstruct resource bar;\n\tstruct resource ext_op_mem;\n\tbool slow_firmware;\n};\n\nstruct mei_bus_message {\n\tu8 hbm_cmd;\n\tu8 data[0];\n};\n\nstruct mei_fw_status {\n\tint count;\n\tu32 status[6];\n};\n\nstruct mei_cfg {\n\tconst struct mei_fw_status fw_status;\n\tbool (*quirk_probe)(const struct pci_dev *);\n\tconst char *kind;\n\tsize_t dma_size[3];\n\tu32 fw_ver_supported: 1;\n\tu32 hw_trc_supported: 1;\n};\n\nstruct mei_dma_data {\n\tu8 buffer_id;\n\tvoid *vaddr;\n\tdma_addr_t daddr;\n\tsize_t size;\n};\n\nstruct mei_device;\n\nstruct mei_me_client;\n\nstruct mei_cl_device;\n\nstruct mei_cl {\n\tstruct list_head link;\n\tstruct mei_device *dev;\n\tenum file_state state;\n\twait_queue_head_t tx_wait;\n\twait_queue_head_t rx_wait;\n\twait_queue_head_t wait;\n\twait_queue_head_t ev_wait;\n\tstruct fasync_struct *ev_async;\n\tint status;\n\tstruct mei_me_client *me_cl;\n\tconst struct file *fp;\n\tu8 host_client_id;\n\tstruct list_head vtag_map;\n\tu8 tx_flow_ctrl_creds;\n\tu8 rx_flow_ctrl_creds;\n\tu8 timer_count;\n\tu8 notify_en;\n\tu8 notify_ev;\n\tu8 tx_cb_queued;\n\tenum mei_file_transaction_states writing_state;\n\tstruct list_head rd_pending;\n\tspinlock_t rd_completed_lock;\n\tstruct list_head rd_completed;\n\tstruct mei_dma_data dma;\n\tu8 dma_mapped;\n\tstruct mei_cl_device *cldev;\n};\n\nstruct mei_msg_data {\n\tsize_t size;\n\tunsigned char *data;\n};\n\nstruct mei_ext_hdr;\n\nstruct mei_cl_cb {\n\tstruct list_head list;\n\tstruct mei_cl *cl;\n\tenum mei_cb_file_ops fop_type;\n\tstruct mei_msg_data buf;\n\tsize_t buf_idx;\n\tu8 vtag;\n\tconst struct file *fp;\n\tint status;\n\tu32 internal: 1;\n\tu32 blocking: 1;\n\tstruct mei_ext_hdr *ext_hdr;\n};\n\ntypedef void (*mei_cldev_cb_t)(struct mei_cl_device *);\n\nstruct mei_cl_device {\n\tstruct list_head bus_list;\n\tstruct mei_device *bus;\n\tstruct device dev;\n\tstruct mei_me_client *me_cl;\n\tstruct mei_cl *cl;\n\tchar name[32];\n\tstruct work_struct rx_work;\n\tmei_cldev_cb_t rx_cb;\n\tstruct work_struct notif_work;\n\tmei_cldev_cb_t notif_cb;\n\tunsigned int do_match: 1;\n\tunsigned int is_added: 1;\n\tvoid *priv_data;\n};\n\nstruct mei_cl_device_id {\n\tchar name[32];\n\tuuid_le uuid;\n\t__u8 version;\n\tkernel_ulong_t driver_info;\n};\n\nstruct mei_cl_driver {\n\tstruct device_driver driver;\n\tconst char *name;\n\tconst struct mei_cl_device_id *id_table;\n\tint (*probe)(struct mei_cl_device *, const struct mei_cl_device_id *);\n\tvoid (*remove)(struct mei_cl_device *);\n};\n\nstruct mei_cl_vtag {\n\tstruct list_head list;\n\tconst struct file *fp;\n\tu8 vtag;\n\tu8 pending_read: 1;\n};\n\nstruct mei_client {\n\t__u32 max_msg_length;\n\t__u8 protocol_version;\n\t__u8 reserved[3];\n};\n\nstruct mei_connect_client_data {\n\tunion {\n\t\tuuid_le in_client_uuid;\n\t\tstruct mei_client out_client_properties;\n\t};\n};\n\nstruct mei_connect_client_vtag {\n\tuuid_le in_client_uuid;\n\t__u8 vtag;\n\t__u8 reserved[3];\n};\n\nstruct mei_connect_client_data_vtag {\n\tunion {\n\t\tstruct mei_connect_client_vtag connect;\n\t\tstruct mei_client out_client_properties;\n\t};\n};\n\nstruct mei_dev_timeouts {\n\tlong unsigned int hw_ready;\n\tint connect;\n\tlong unsigned int cl_connect;\n\tint client_init;\n\tlong unsigned int pgi;\n\tunsigned int d0i3;\n\tlong unsigned int hbm;\n\tlong unsigned int mkhi_recv;\n\tlong unsigned int link_reset_wait;\n};\n\nstruct mei_dma_dscr {\n\tvoid *vaddr;\n\tdma_addr_t daddr;\n\tsize_t size;\n};\n\nstruct mei_fw_version {\n\tu8 platform;\n\tu8 major;\n\tu16 minor;\n\tu16 buildno;\n\tu16 hotfix;\n};\n\nstruct mei_hw_ops;\n\nstruct mei_device {\n\tstruct device *parent;\n\tstruct device dev;\n\tstruct cdev *cdev;\n\tint minor;\n\tstruct list_head write_list;\n\tstruct list_head write_waiting_list;\n\tstruct list_head ctrl_wr_list;\n\tstruct list_head ctrl_rd_list;\n\tu8 tx_queue_limit;\n\tstruct list_head file_list;\n\tlong int open_handle_count;\n\tstruct mutex device_lock;\n\tstruct delayed_work timer_work;\n\tbool recvd_hw_ready;\n\twait_queue_head_t wait_hw_ready;\n\twait_queue_head_t wait_pg;\n\twait_queue_head_t wait_hbm_start;\n\tlong unsigned int reset_count;\n\tenum mei_dev_state dev_state;\n\twait_queue_head_t wait_dev_state;\n\tenum mei_hbm_state hbm_state;\n\tenum mei_dev_pxp_mode pxp_mode;\n\tu16 init_clients_timer;\n\tenum mei_pg_event pg_event;\n\tstruct dev_pm_domain pg_domain;\n\tunsigned char rd_msg_buf[512];\n\tu32 rd_msg_hdr[512];\n\tint rd_msg_hdr_count;\n\tbool hbuf_is_ready;\n\tstruct mei_dma_dscr dr_dscr[3];\n\tstruct hbm_version version;\n\tunsigned int hbm_f_pg_supported: 1;\n\tunsigned int hbm_f_dc_supported: 1;\n\tunsigned int hbm_f_dot_supported: 1;\n\tunsigned int hbm_f_ev_supported: 1;\n\tunsigned int hbm_f_fa_supported: 1;\n\tunsigned int hbm_f_ie_supported: 1;\n\tunsigned int hbm_f_os_supported: 1;\n\tunsigned int hbm_f_dr_supported: 1;\n\tunsigned int hbm_f_vt_supported: 1;\n\tunsigned int hbm_f_cap_supported: 1;\n\tunsigned int hbm_f_cd_supported: 1;\n\tunsigned int hbm_f_gsc_supported: 1;\n\tstruct mei_fw_version fw_ver[3];\n\tunsigned int fw_f_fw_ver_supported: 1;\n\tunsigned int fw_ver_received: 1;\n\tstruct rw_semaphore me_clients_rwsem;\n\tstruct list_head me_clients;\n\tlong unsigned int me_clients_map[4];\n\tlong unsigned int host_clients_map[4];\n\tbool allow_fixed_address;\n\tbool override_fixed_address;\n\tstruct mei_dev_timeouts timeouts;\n\tstruct work_struct reset_work;\n\tstruct work_struct bus_rescan_work;\n\tstruct list_head device_list;\n\tstruct mutex cl_bus_lock;\n\tconst char *kind;\n\tstruct dentry *dbgfs_dir;\n\tenum mei_dev_reset_to_pxp gsc_reset_to_pxp;\n\tconst struct mei_hw_ops *ops;\n\tchar hw[0];\n};\n\nstruct mei_ext_hdr {\n\tu8 type;\n\tu8 length;\n};\n\nstruct mei_ext_hdr_gsc_f2h {\n\tstruct mei_ext_hdr hdr;\n\tu8 client_id;\n\tu8 reserved;\n\tu32 fence_id;\n\tu32 written;\n};\n\nstruct mei_gsc_sgl {\n\tu32 low;\n\tu32 high;\n\tu32 length;\n};\n\nstruct mei_ext_hdr_gsc_h2f {\n\tstruct mei_ext_hdr hdr;\n\tu8 client_id;\n\tu8 addr_type;\n\tu32 fence_id;\n\tu8 input_address_count;\n\tu8 output_address_count;\n\tu8 reserved[2];\n\tstruct mei_gsc_sgl sgl[0];\n};\n\nstruct mei_ext_hdr_vtag {\n\tstruct mei_ext_hdr hdr;\n\tu8 vtag;\n\tu8 reserved;\n};\n\nstruct mei_ext_meta_hdr {\n\tu8 count;\n\tu8 size;\n\tu8 reserved[2];\n\tu8 hdrs[0];\n};\n\nstruct mei_fixup {\n\tconst uuid_le uuid;\n\tvoid (*hook)(struct mei_cl_device *);\n};\n\nstruct mei_hbm_cl_cmd {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 data;\n};\n\nstruct mei_hw_ops {\n\tbool (*host_is_ready)(struct mei_device *);\n\tbool (*hw_is_ready)(struct mei_device *);\n\tint (*hw_reset)(struct mei_device *, bool);\n\tint (*hw_start)(struct mei_device *);\n\tint (*hw_config)(struct mei_device *);\n\tint (*fw_status)(struct mei_device *, struct mei_fw_status *);\n\tint (*trc_status)(struct mei_device *, u32 *);\n\tenum mei_pg_state (*pg_state)(struct mei_device *);\n\tbool (*pg_in_transition)(struct mei_device *);\n\tbool (*pg_is_enabled)(struct mei_device *);\n\tvoid (*intr_clear)(struct mei_device *);\n\tvoid (*intr_enable)(struct mei_device *);\n\tvoid (*intr_disable)(struct mei_device *);\n\tvoid (*synchronize_irq)(struct mei_device *);\n\tint (*hbuf_free_slots)(struct mei_device *);\n\tbool (*hbuf_is_ready)(struct mei_device *);\n\tu32 (*hbuf_depth)(const struct mei_device *);\n\tint (*write)(struct mei_device *, const void *, size_t, const void *, size_t);\n\tint (*rdbuf_full_slots)(struct mei_device *);\n\tu32 (*read_hdr)(const struct mei_device *);\n\tint (*read)(struct mei_device *, unsigned char *, long unsigned int);\n};\n\nstruct mei_me_client {\n\tstruct list_head list;\n\tstruct kref refcnt;\n\tstruct mei_client_properties props;\n\tu8 client_id;\n\tu8 tx_flow_ctrl_creds;\n\tu8 connect_count;\n\tu8 bus_added;\n};\n\nstruct mei_me_hw {\n\tconst struct mei_cfg *cfg;\n\tvoid *mem_addr;\n\tint irq;\n\tenum mei_pg_state pg_state;\n\tbool d0i3_supported;\n\tu8 hbuf_depth;\n\tint (*read_fws)(const struct mei_device *, int, u32 *);\n\tstruct task_struct *polling_thread;\n\twait_queue_head_t wait_active;\n\tbool is_active;\n};\n\nstruct mei_msg_hdr {\n\tu32 me_addr: 8;\n\tu32 host_addr: 8;\n\tu32 length: 9;\n\tu32 reserved: 3;\n\tu32 extended: 1;\n\tu32 dma_ring: 1;\n\tu32 internal: 1;\n\tu32 msg_complete: 1;\n\tu32 extension[0];\n};\n\nstruct mei_nfc_cmd {\n\tu8 command;\n\tu8 status;\n\tu16 req_id;\n\tu32 reserved;\n\tu16 data_size;\n\tu8 sub_command;\n\tu8 data[0];\n} __attribute__((packed));\n\nstruct mei_nfc_if_version {\n\tu8 radio_version_sw[3];\n\tu8 reserved[3];\n\tu8 radio_version_hw[3];\n\tu8 i2c_addr;\n\tu8 fw_ivn;\n\tu8 vendor_id;\n\tu8 radio_type;\n};\n\nstruct mei_nfc_reply {\n\tu8 command;\n\tu8 status;\n\tu16 req_id;\n\tu32 reserved;\n\tu16 data_size;\n\tu8 sub_command;\n\tu8 reply_status;\n\tu8 data[0];\n};\n\nstruct mei_os_ver {\n\t__le16 build;\n\t__le16 reserved1;\n\tu8 os_type;\n\tu8 major;\n\tu8 minor;\n\tu8 reserved2;\n};\n\nstruct pglist_data;\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n};\n\nstruct mem_extent {\n\tstruct list_head hook;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mem_section_usage;\n\nstruct mem_section {\n\tlong unsigned int section_mem_map;\n\tstruct mem_section_usage *usage;\n};\n\nstruct mem_section_usage {\n\tstruct callback_head rcu;\n\tlong unsigned int subsection_map[1];\n\tlong unsigned int pageblock_flags[0];\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct mem_zone_bm_rtree {\n\tstruct list_head list;\n\tstruct list_head nodes;\n\tstruct list_head leaves;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tstruct rtree_node *rtree;\n\tint levels;\n\tunsigned int blocks;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n\tint nid;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct memmap_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct firmware_map_entry *, char *);\n};\n\nstruct memory_bitmap {\n\tstruct list_head zones;\n\tstruct linked_page *p_list;\n\tstruct bm_position cur;\n};\n\nstruct memory_group;\n\nstruct memory_block {\n\tlong unsigned int start_section_nr;\n\tenum memory_block_state state;\n\tint online_type;\n\tint nid;\n\tstruct zone *zone;\n\tstruct device dev;\n\tstruct vmem_altmap *altmap;\n\tstruct memory_group *group;\n\tstruct list_head group_next;\n};\n\nstruct memory_dev_type {\n\tstruct list_head tier_sibling;\n\tstruct list_head list;\n\tint adistance;\n\tnodemask_t nodes;\n\tstruct kref kref;\n};\n\nstruct memory_group {\n\tint nid;\n\tstruct list_head memory_blocks;\n\tlong unsigned int present_kernel_pages;\n\tlong unsigned int present_movable_pages;\n\tbool is_dynamic;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int max_pages;\n\t\t} s;\n\t\tstruct {\n\t\t\tlong unsigned int unit_pages;\n\t\t} d;\n\t};\n};\n\nstruct memory_notify {\n\tlong unsigned int start_pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct memory_tier {\n\tstruct list_head list;\n\tstruct list_head memory_types;\n\tint adistance_start;\n\tstruct device dev;\n\tnodemask_t lower_tier_mask;\n};\n\nstruct mempolicy {\n\tatomic_t refcnt;\n\tshort unsigned int mode;\n\tshort unsigned int flags;\n\tnodemask_t nodes;\n\tint home_node;\n\tunion {\n\t\tnodemask_t cpuset_mems_allowed;\n\t\tnodemask_t user_nodemask;\n\t} w;\n};\n\nstruct mempolicy_operations {\n\tint (*create)(struct mempolicy *, const nodemask_t *);\n\tvoid (*rebind)(struct mempolicy *, const nodemask_t *);\n};\n\nstruct memtype {\n\tu64 start;\n\tu64 end;\n\tu64 subtree_max_end;\n\tenum page_cache_mode type;\n\tstruct rb_node rb;\n};\n\nstruct menu_device {\n\tint needs_update;\n\tint tick_wakeup;\n\tu64 next_timer_ns;\n\tunsigned int bucket;\n\tunsigned int correction_factor[6];\n\tunsigned int intervals[8];\n\tint interval_ptr;\n};\n\nstruct merge_sched_data {\n\tint can_add_hw;\n\tenum event_type_t event_type;\n};\n\nstruct meta_entry {\n\tu64 data_block;\n\tunsigned int index_block;\n\tshort unsigned int offset;\n\tshort unsigned int pad;\n};\n\nstruct meta_index {\n\tunsigned int inode_number;\n\tunsigned int offset;\n\tshort unsigned int entries;\n\tshort unsigned int skip;\n\tshort unsigned int locked;\n\tshort unsigned int pad;\n\tstruct meta_entry meta_entry[127];\n};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mr_mfc {\n\tstruct rhlist_head mnode;\n\tshort unsigned int mfc_parent;\n\tint mfc_flags;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int expires;\n\t\t\tstruct sk_buff_head unresolved;\n\t\t} unres;\n\t\tstruct {\n\t\t\tlong unsigned int last_assert;\n\t\t\tint minvif;\n\t\t\tint maxvif;\n\t\t\tatomic_long_t bytes;\n\t\t\tatomic_long_t pkt;\n\t\t\tatomic_long_t wrong_if;\n\t\t\tlong unsigned int lastuse;\n\t\t\tunsigned char ttls[32];\n\t\t\trefcount_t refcount;\n\t\t} res;\n\t} mfc_un;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tvoid (*free)(struct callback_head *);\n};\n\nstruct mfc_cache_cmp_arg {\n\t__be32 mfc_mcastgrp;\n\t__be32 mfc_origin;\n};\n\nstruct mfc_cache {\n\tstruct mr_mfc _c;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 mfc_mcastgrp;\n\t\t\t__be32 mfc_origin;\n\t\t};\n\t\tstruct mfc_cache_cmp_arg cmparg;\n\t};\n};\n\nstruct mfc_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct mr_mfc *mfc;\n\tu32 tb_id;\n};\n\nstruct mfcctl {\n\tstruct in_addr mfcc_origin;\n\tstruct in_addr mfcc_mcastgrp;\n\tvifi_t mfcc_parent;\n\tunsigned char mfcc_ttls[32];\n\tunsigned int mfcc_pkt_cnt;\n\tunsigned int mfcc_byte_cnt;\n\tunsigned int mfcc_wrong_if;\n\tint mfcc_expire;\n};\n\nstruct mhp_params {\n\tstruct vmem_altmap *altmap;\n\tpgprot_t pgprot;\n\tstruct dev_pagemap *pgmap;\n};\n\nstruct microcode_header_amd {\n\tu32 data_code;\n\tu32 patch_id;\n\tu16 mc_patch_data_id;\n\tu8 mc_patch_data_len;\n\tu8 init_flag;\n\tu32 mc_patch_data_checksum;\n\tu32 nb_dev_id;\n\tu32 sb_dev_id;\n\tu16 processor_rev_id;\n\tu8 nb_rev_id;\n\tu8 sb_rev_id;\n\tu8 bios_api_rev;\n\tu8 reserved1[3];\n\tu32 match_reg[8];\n};\n\nstruct microcode_amd {\n\tstruct microcode_header_amd hdr;\n\tunsigned int mpb[0];\n};\n\nstruct microcode_header_intel {\n\tunsigned int hdrver;\n\tunsigned int rev;\n\tunsigned int date;\n\tunsigned int sig;\n\tunsigned int cksum;\n\tunsigned int ldrver;\n\tunsigned int pf;\n\tunsigned int datasize;\n\tunsigned int totalsize;\n\tunsigned int metasize;\n\tunsigned int min_req_ver;\n\tunsigned int reserved;\n};\n\nstruct microcode_intel {\n\tstruct microcode_header_intel hdr;\n\tunsigned int bits[0];\n};\n\nstruct microcode_ops {\n\tenum ucode_state (*request_microcode_fw)(int, struct device *);\n\tvoid (*microcode_fini_cpu)(int);\n\tenum ucode_state (*apply_microcode)(int);\n\tvoid (*stage_microcode)(void);\n\tint (*collect_cpu_info)(int, struct cpu_signature *);\n\tvoid (*finalize_late_load)(int);\n\tunsigned int nmi_safe: 1;\n\tunsigned int use_nmi: 1;\n\tunsigned int use_staging: 1;\n};\n\nstruct mid8250_board;\n\nstruct mid8250 {\n\tint line;\n\tint dma_index;\n\tstruct pci_dev *dma_dev;\n\tstruct uart_8250_dma dma;\n\tstruct mid8250_board *board;\n\tstruct hsu_dma_chip dma_chip;\n};\n\nstruct mid8250_board {\n\tlong unsigned int freq;\n\tunsigned int base_baud;\n\tunsigned int bar;\n\tint (*setup)(struct mid8250 *, struct uart_port *);\n\tvoid (*exit)(struct mid8250 *);\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_vma {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int *dst;\n\tlong unsigned int *src;\n\tlong unsigned int cpages;\n\tlong unsigned int npages;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvoid *pgmap_owner;\n\tlong unsigned int flags;\n\tstruct page *fault_page;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_mpol {\n\tstruct mempolicy *pol;\n\tlong unsigned int ilx;\n};\n\nstruct migration_swap_arg {\n\tstruct task_struct *src_task;\n\tstruct task_struct *dst_task;\n\tint src_cpu;\n\tint dst_cpu;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct min_heap_callbacks {\n\tbool (*less)(const void *, const void *, void *);\n\tvoid (*swp)(void *, void *, void *);\n};\n\nstruct min_heap_char {\n\tsize_t nr;\n\tsize_t size;\n\tchar *data;\n\tchar preallocated[0];\n};\n\ntypedef struct min_heap_char min_heap_char;\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minimode {\n\tshort int w;\n\tshort int h;\n\tshort int r;\n\tshort int rb;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct mipi_dsi_device {\n\tstruct mipi_dsi_host *host;\n\tstruct device dev;\n\tbool attached;\n\tchar name[20];\n\tunsigned int channel;\n\tunsigned int lanes;\n\tenum mipi_dsi_pixel_format format;\n\tlong unsigned int mode_flags;\n\tlong unsigned int hs_rate;\n\tlong unsigned int lp_rate;\n\tstruct drm_dsc_config *dsc;\n};\n\nstruct mipi_dsi_device_info {\n\tchar type[20];\n\tu32 channel;\n\tstruct device_node *node;\n};\n\nstruct mipi_dsi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct mipi_dsi_device *);\n\tvoid (*remove)(struct mipi_dsi_device *);\n\tvoid (*shutdown)(struct mipi_dsi_device *);\n};\n\nstruct mipi_dsi_msg;\n\nstruct mipi_dsi_host_ops {\n\tint (*attach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tint (*detach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tssize_t (*transfer)(struct mipi_dsi_host *, const struct mipi_dsi_msg *);\n};\n\nstruct mipi_dsi_msg {\n\tu8 channel;\n\tu8 type;\n\tu16 flags;\n\tsize_t tx_len;\n\tconst void *tx_buf;\n\tsize_t rx_len;\n\tvoid *rx_buf;\n};\n\nstruct mipi_dsi_multi_context {\n\tstruct mipi_dsi_device *dsi;\n\tint accum_err;\n};\n\nstruct mipi_dsi_packet {\n\tsize_t size;\n\tu8 header[4];\n\tsize_t payload_length;\n\tconst u8 *payload;\n};\n\nstruct mirror_set;\n\nstruct mirror {\n\tstruct mirror_set *ms;\n\tatomic_t error_count;\n\tlong unsigned int error_type;\n\tstruct dm_dev *dev;\n\tsector_t offset;\n};\n\nstruct mirror_set {\n\tstruct dm_target *ti;\n\tstruct list_head list;\n\tuint64_t features;\n\tspinlock_t lock;\n\tstruct bio_list reads;\n\tstruct bio_list writes;\n\tstruct bio_list failures;\n\tstruct bio_list holds;\n\tstruct dm_region_hash *rh;\n\tstruct dm_kcopyd_client *kcopyd_client;\n\tstruct dm_io_client *io_client;\n\tregion_t nr_regions;\n\tint in_sync;\n\tint log_failure;\n\tint leg_failure;\n\tatomic_t suspend;\n\tatomic_t default_mirror;\n\tstruct workqueue_struct *kmirrord_wq;\n\tstruct work_struct kmirrord_work;\n\tstruct timer_list timer;\n\tlong unsigned int timer_pending;\n\tstruct work_struct trigger_event;\n\tunsigned int nr_mirrors;\n\tstruct mirror mirror[0];\n};\n\nstruct misc_res {\n\tu64 max;\n\tatomic64_t watermark;\n\tatomic64_t usage;\n\tatomic64_t events;\n\tatomic64_t events_local;\n};\n\nstruct misc_cg {\n\tstruct cgroup_subsys_state css;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct misc_res res[0];\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct mkhi_fw_ver_block {\n\tu16 minor;\n\tu8 major;\n\tu8 platform;\n\tu16 buildno;\n\tu16 hotfix;\n};\n\nstruct mkhi_fw_ver {\n\tstruct mkhi_fw_ver_block ver[3];\n};\n\nstruct mkhi_rule_id {\n\t__le16 rule_type;\n\tu8 feature_id;\n\tu8 reserved;\n};\n\nstruct mkhi_fwcaps {\n\tstruct mkhi_rule_id id;\n\tu8 len;\n\tu8 data[0];\n} __attribute__((packed));\n\nstruct mkhi_msg_hdr {\n\tu8 group_id;\n\tu8 command;\n\tu8 reserved;\n\tu8 result;\n};\n\nstruct mkhi_gfx_mem_ready {\n\tstruct mkhi_msg_hdr hdr;\n\tu32 flags;\n};\n\nstruct mkhi_msg {\n\tstruct mkhi_msg_hdr hdr;\n\tu8 data[0];\n};\n\nstruct ml_effect_state {\n\tstruct ff_effect *effect;\n\tlong unsigned int flags;\n\tint count;\n\tlong unsigned int play_at;\n\tlong unsigned int stop_at;\n\tlong unsigned int adj_at;\n};\n\nstruct ml_device {\n\tvoid *private;\n\tstruct ml_effect_state states[16];\n\tint gain;\n\tstruct timer_list timer;\n\tstruct input_dev *dev;\n\tint (*play_effect)(struct input_dev *, void *, struct ff_effect *);\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tstruct ethtool_mm_stats stats;\n};\n\ntypedef struct mm_struct *class_mmap_read_lock_t;\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n\tstruct hlist_head head_tramps;\n};\n\nstruct mmu_notifier_subscriptions;\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int mmap_compat_base;\n\t\tlong unsigned int mmap_compat_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct rcuwait vma_writer_wait;\n\t\tseqcount_t mm_lock_seq;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[52];\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tstruct mmu_notifier_subscriptions *notifier_subscriptions;\n\t\tlong unsigned int numa_next_scan;\n\t\tlong unsigned int numa_scan_offset;\n\t\tint numa_scan_seq;\n\t\tatomic_t tlb_flush_pending;\n\t\tatomic_t tlb_flush_batched;\n\t\tstruct uprobes_state uprobes_state;\n\t\tatomic_long_t hugetlb_usage;\n\t\tstruct work_struct async_put_work;\n\t\tstruct iommu_mm_data *iommu_mm;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct mmap_arg_struct32 {\n\tunsigned int addr;\n\tunsigned int len;\n\tunsigned int prot;\n\tunsigned int flags;\n\tunsigned int fd;\n\tunsigned int offset;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mminit_pfnnid_cache {\n\tlong unsigned int last_start;\n\tlong unsigned int last_end;\n\tint last_nid;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct encoded_page;\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct encoded_page *encoded_pages[0];\n};\n\nstruct mmu_table_batch;\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tstruct mmu_table_batch *batch;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n};\n\nstruct mmu_notifier_range;\n\nstruct mmu_interval_notifier_ops {\n\tbool (*invalidate)(struct mmu_interval_notifier *, const struct mmu_notifier_range *, long unsigned int);\n};\n\nstruct mmu_notifier_ops {\n\tvoid (*release)(struct mmu_notifier *, struct mm_struct *);\n\tint (*clear_flush_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*clear_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*test_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int);\n\tint (*invalidate_range_start)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range_end)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*arch_invalidate_secondary_tlbs)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tstruct mmu_notifier * (*alloc_notifier)(struct mm_struct *);\n\tvoid (*free_notifier)(struct mmu_notifier *);\n};\n\nstruct mmu_notifier_range {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int flags;\n\tenum mmu_notifier_event event;\n\tvoid *owner;\n};\n\nstruct mmu_notifier_subscriptions {\n\tstruct hlist_head list;\n\tbool has_itree;\n\tspinlock_t lock;\n\tlong unsigned int invalidate_seq;\n\tlong unsigned int active_invalidate_ranges;\n\tstruct rb_root_cached itree;\n\twait_queue_head_t wq;\n\tstruct hlist_head deferred_list;\n};\n\nstruct mmu_page_path {\n\tstruct kvm_mmu_page *parent[5];\n\tunsigned int idx[5];\n};\n\nstruct mmu_table_batch {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tvoid *tables[0];\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct orc_entry;\n\nstruct mod_arch_specific {\n\tunsigned int num_orcs;\n\tint *orc_unwind_ip;\n\tstruct orc_entry *orc_unwind;\n\tstruct its_array its_pages;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf64_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct mode_dual {\n\tstruct opcode mode32;\n\tstruct opcode mode64;\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n\tstruct mod_tree_node mtn;\n};\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_event_call;\n\nstruct trace_eval_map;\n\nstruct static_call_site;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[56];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tlong: 64;\n\tlong: 64;\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tunsigned int num_ftrace_callsites;\n\tlong unsigned int *ftrace_callsites;\n\tvoid *kprobes_text_start;\n\tunsigned int kprobes_text_size;\n\tlong unsigned int *kprobe_blacklist;\n\tunsigned int num_kprobe_blacklist;\n\tint num_static_call_sites;\n\tstruct static_call_site *static_call_sites;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_string {\n\tstruct list_head next;\n\tstruct module *module;\n\tchar *str;\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct mp_chip_data {\n\tstruct list_head irq_2_pin;\n\tstruct IO_APIC_route_entry entry;\n\tbool is_level;\n\tbool active_low;\n\tbool isa_irq;\n\tu32 count;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpc_bus {\n\tunsigned char type;\n\tunsigned char busid;\n\tunsigned char bustype[6];\n};\n\nstruct mpc_cpu {\n\tunsigned char type;\n\tunsigned char apicid;\n\tunsigned char apicver;\n\tunsigned char cpuflag;\n\tunsigned int cpufeature;\n\tunsigned int featureflag;\n\tunsigned int reserved[2];\n};\n\nstruct mpc_intsrc {\n\tunsigned char type;\n\tunsigned char irqtype;\n\tshort unsigned int irqflag;\n\tunsigned char srcbus;\n\tunsigned char srcbusirq;\n\tunsigned char dstapic;\n\tunsigned char dstirq;\n};\n\nstruct mpc_lintsrc {\n\tunsigned char type;\n\tunsigned char irqtype;\n\tshort unsigned int irqflag;\n\tunsigned char srcbusid;\n\tunsigned char srcbusirq;\n\tunsigned char destapic;\n\tunsigned char destapiclint;\n};\n\nstruct mpc_table {\n\tchar signature[4];\n\tshort unsigned int length;\n\tchar spec;\n\tchar checksum;\n\tchar oem[8];\n\tchar productid[12];\n\tunsigned int oemptr;\n\tshort unsigned int oemsize;\n\tshort unsigned int oemcount;\n\tunsigned int lapic;\n\tunsigned int reserved;\n};\n\nstruct mpf_intel {\n\tchar signature[4];\n\tunsigned int physptr;\n\tunsigned char length;\n\tunsigned char specification;\n\tunsigned char checksum;\n\tunsigned char feature1;\n\tunsigned char feature2;\n\tunsigned char feature3;\n\tunsigned char feature4;\n\tunsigned char feature5;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mptcp_out_options {};\n\nstruct mptcp_sock {};\n\nstruct mq_attr {\n\t__kernel_long_t mq_flags;\n\t__kernel_long_t mq_maxmsg;\n\t__kernel_long_t mq_msgsize;\n\t__kernel_long_t mq_curmsgs;\n\t__kernel_long_t __reserved[4];\n};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct mqueue_fs_context {\n\tstruct ipc_namespace *ipc_ns;\n\tbool newns;\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[12];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct posix_msg_tree_node;\n\nstruct mqueue_inode_info {\n\tspinlock_t lock;\n\tstruct inode vfs_inode;\n\twait_queue_head_t wait_q;\n\tstruct rb_root msg_tree;\n\tstruct rb_node *msg_tree_rightmost;\n\tstruct posix_msg_tree_node *node_cache;\n\tstruct mq_attr attr;\n\tstruct sigevent notify;\n\tstruct pid *notify_owner;\n\tu32 notify_self_exec_id;\n\tstruct user_namespace *notify_user_ns;\n\tstruct ucounts *ucounts;\n\tstruct sock *notify_sock;\n\tstruct sk_buff *notify_cookie;\n\tstruct ext_wait_queue e_wait_q[2];\n\tlong unsigned int qsize;\n};\n\nstruct mr_table;\n\nstruct mr_mfc_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tstruct list_head *cache;\n\tspinlock_t *lock;\n};\n\nstruct mr_table_ops {\n\tconst struct rhashtable_params *rht_params;\n\tvoid *cmparg_any;\n};\n\nstruct vif_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tlong unsigned int bytes_in;\n\tlong unsigned int bytes_out;\n\tlong unsigned int pkt_in;\n\tlong unsigned int pkt_out;\n\tlong unsigned int rate_limit;\n\tunsigned char threshold;\n\tshort unsigned int flags;\n\tint link;\n\tstruct netdev_phys_item_id dev_parent_id;\n\t__be32 local;\n\t__be32 remote;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct mr_table {\n\tstruct list_head list;\n\tpossible_net_t net;\n\tstruct mr_table_ops ops;\n\tu32 id;\n\tstruct sock *mroute_sk;\n\tstruct timer_list ipmr_expire_timer;\n\tstruct list_head mfc_unres_queue;\n\tstruct vif_device vif_table[32];\n\tstruct rhltable mfc_hash;\n\tstruct list_head mfc_cache_list;\n\tint maxvif;\n\tatomic_t cache_resolve_queue_len;\n\tbool mroute_do_assert;\n\tbool mroute_do_pim;\n\tbool mroute_do_wrvifwhole;\n\tint mroute_reg_vif_num;\n};\n\nstruct mr_vif_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tint ct;\n};\n\nstruct mrrm_mem_range_entry {\n\tu64 base;\n\tu64 length;\n\tint node;\n\tu8 local_region_id;\n\tu8 remote_region_id;\n};\n\nstruct ms_hyperv_info {\n\tu32 features;\n\tu32 priv_high;\n\tu32 ext_features;\n\tu32 misc_features;\n\tu32 hints;\n\tu32 nested_features;\n\tu32 max_vp_index;\n\tu32 max_lp_index;\n\tu8 vtl;\n\tunion {\n\t\tu32 isolation_config_a;\n\t\tstruct {\n\t\t\tu32 paravisor_present: 1;\n\t\t\tu32 reserved_a1: 31;\n\t\t};\n\t};\n\tunion {\n\t\tu32 isolation_config_b;\n\t\tstruct {\n\t\t\tu32 cvm_type: 4;\n\t\t\tu32 reserved_b1: 1;\n\t\t\tu32 shared_gpa_boundary_active: 1;\n\t\t\tu32 shared_gpa_boundary_bits: 6;\n\t\t\tu32 reserved_b2: 20;\n\t\t};\n\t};\n\tu64 shared_gpa_boundary;\n\tbool msi_ext_dest_id;\n\tbool confidential_vmbus_available;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct x86_msi_addr_lo {\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved_0: 2;\n\t\t\tu32 dest_mode_logical: 1;\n\t\t\tu32 redirect_hint: 1;\n\t\t\tu32 reserved_1: 1;\n\t\t\tu32 virt_destid_8_14: 7;\n\t\t\tu32 destid_0_7: 8;\n\t\t\tu32 base_address: 12;\n\t\t};\n\t\tstruct {\n\t\t\tu32 dmar_reserved_0: 2;\n\t\t\tu32 dmar_index_15: 1;\n\t\t\tu32 dmar_subhandle_valid: 1;\n\t\t\tu32 dmar_format: 1;\n\t\t\tu32 dmar_index_0_14: 15;\n\t\t\tu32 dmar_base_address: 12;\n\t\t};\n\t};\n};\n\ntypedef struct x86_msi_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct x86_msi_addr_hi {\n\tu32 reserved: 8;\n\tu32 destid_8_31: 24;\n};\n\ntypedef struct x86_msi_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct x86_msi_data {\n\tunion {\n\t\tstruct {\n\t\t\tu32 vector: 8;\n\t\t\tu32 delivery_mode: 3;\n\t\t\tu32 dest_mode_logical: 1;\n\t\t\tu32 reserved: 2;\n\t\t\tu32 active_low: 1;\n\t\t\tu32 is_level: 1;\n\t\t};\n\t\tu32 dmar_subhandle;\n\t};\n};\n\ntypedef struct x86_msi_data arch_msi_msg_data_t;\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong int msg_stime;\n\tlong int msg_rtime;\n\tlong int msg_ctime;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct msr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 l;\n\t\t\tu32 h;\n\t\t};\n\t\tu64 q;\n\t};\n};\n\nstruct vmx_msr_entry {\n\tu32 index;\n\tu32 reserved;\n\tu64 value;\n};\n\nstruct vmx_msrs {\n\tunsigned int nr;\n\tlong: 64;\n\tstruct vmx_msr_entry val[8];\n};\n\nstruct msr_autoload {\n\tstruct vmx_msrs guest;\n\tstruct vmx_msrs host;\n};\n\nstruct msr_data {\n\tbool host_initiated;\n\tu32 index;\n\tu64 data;\n};\n\nstruct msr_enumeration {\n\tu32 msr_no;\n\tu32 feature;\n};\n\nstruct msr_info {\n\tu32 msr_no;\n\tstruct msr reg;\n\tstruct msr *msrs;\n\tint err;\n};\n\nstruct msr_info_completion {\n\tstruct msr_info msr;\n\tstruct completion done;\n};\n\nstruct msr_regs_info {\n\tu32 *regs;\n\tint err;\n};\n\nstruct mtl_gsc_ver_msg_in {\n\tstruct intel_gsc_mtl_header header;\n\tstruct intel_gsc_mkhi_header mkhi;\n};\n\nstruct mtl_gsc_ver_msg_out {\n\tstruct intel_gsc_mtl_header header;\n\tstruct intel_gsc_mkhi_header mkhi;\n\tu16 proj_major;\n\tu16 compat_major;\n\tu16 compat_minor;\n\tu16 reserved[5];\n};\n\nstruct pxp_cmd_header {\n\tu32 api_version;\n\tu32 command_id;\n\tunion {\n\t\tu32 status;\n\t\tu32 stream_id;\n\t};\n\tu32 buffer_len;\n};\n\nstruct pxp43_new_huc_auth_in {\n\tstruct pxp_cmd_header header;\n\tu64 huc_base_address;\n\tu32 huc_size;\n} __attribute__((packed));\n\nstruct mtl_huc_auth_msg_in {\n\tstruct intel_gsc_mtl_header header;\n\tstruct pxp43_new_huc_auth_in huc_in;\n};\n\nstruct pxp43_huc_auth_out {\n\tstruct pxp_cmd_header header;\n};\n\nstruct mtl_huc_auth_msg_out {\n\tstruct intel_gsc_mtl_header header;\n\tstruct pxp43_huc_auth_out huc_out;\n};\n\nstruct mtrr_gentry {\n\t__u64 base;\n\t__u32 size;\n\t__u32 regnum;\n\t__u32 type;\n\t__u32 _pad;\n};\n\nstruct mtrr_gentry32 {\n\tcompat_ulong_t regnum;\n\tcompat_uint_t base;\n\tcompat_uint_t size;\n\tcompat_uint_t type;\n};\n\nstruct mtrr_ops {\n\tu32 var_regs;\n\tvoid (*set)(unsigned int, long unsigned int, long unsigned int, mtrr_type);\n\tvoid (*get)(unsigned int, long unsigned int *, long unsigned int *, mtrr_type *);\n\tint (*get_free_region)(long unsigned int, long unsigned int, int);\n\tint (*validate_add_page)(long unsigned int, long unsigned int, unsigned int);\n\tint (*have_wrcomb)(void);\n};\n\nstruct mtrr_sentry {\n\t__u64 base;\n\t__u32 size;\n\t__u32 type;\n};\n\nstruct mtrr_sentry32 {\n\tcompat_ulong_t base;\n\tcompat_uint_t size;\n\tcompat_uint_t type;\n};\n\nstruct mtrr_var_range {\n\t__u32 base_lo;\n\t__u32 base_hi;\n\t__u32 mask_lo;\n\t__u32 mask_hi;\n};\n\nstruct mtrr_state_type {\n\tstruct mtrr_var_range var_ranges[256];\n\tmtrr_type fixed_ranges[88];\n\tunsigned char enabled;\n\tbool have_fixed;\n\tmtrr_type def_type;\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n\tvoid *magic;\n};\n\nstruct mwait_cpu_dead {\n\tunsigned int control;\n\tunsigned int status;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[4];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[64];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u32 offset;\n\t__u32 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint poll_owner;\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct nested_vmx_msrs {\n\tu32 procbased_ctls_low;\n\tu32 procbased_ctls_high;\n\tu32 secondary_ctls_low;\n\tu32 secondary_ctls_high;\n\tu32 pinbased_ctls_low;\n\tu32 pinbased_ctls_high;\n\tu32 exit_ctls_low;\n\tu32 exit_ctls_high;\n\tu32 entry_ctls_low;\n\tu32 entry_ctls_high;\n\tu32 misc_low;\n\tu32 misc_high;\n\tu32 ept_caps;\n\tu32 vpid_caps;\n\tu64 basic;\n\tu64 cr0_fixed0;\n\tu64 cr0_fixed1;\n\tu64 cr4_fixed0;\n\tu64 cr4_fixed1;\n\tu64 vmcs_enum;\n\tu64 vmfunc_controls;\n};\n\nstruct vmcs12;\n\nstruct pi_desc;\n\nstruct nested_vmx {\n\tbool vmxon;\n\tgpa_t vmxon_ptr;\n\tbool pml_full;\n\tgpa_t current_vmptr;\n\tstruct vmcs12 *cached_vmcs12;\n\tstruct vmcs12 *cached_shadow_vmcs12;\n\tstruct gfn_to_hva_cache shadow_vmcs12_cache;\n\tstruct gfn_to_hva_cache vmcs12_cache;\n\tbool need_vmcs12_to_shadow_sync;\n\tbool dirty_vmcs12;\n\tbool force_msr_bitmap_recalc;\n\tbool need_sync_vmcs02_to_vmcs12_rare;\n\tbool vmcs02_initialized;\n\tbool enlightened_vmcs_enabled;\n\tbool nested_run_pending;\n\tbool mtf_pending;\n\tstruct loaded_vmcs vmcs02;\n\tstruct kvm_host_map apic_access_page_map;\n\tstruct kvm_host_map virtual_apic_map;\n\tstruct kvm_host_map pi_desc_map;\n\tstruct pi_desc *pi_desc;\n\tbool pi_pending;\n\tu16 posted_intr_nv;\n\tstruct hrtimer preemption_timer;\n\tu64 preemption_timer_deadline;\n\tbool has_preemption_timer_deadline;\n\tbool preemption_timer_expired;\n\tu64 pre_vmenter_debugctl;\n\tu64 pre_vmenter_bndcfgs;\n\tu64 pre_vmenter_s_cet;\n\tu64 pre_vmenter_ssp;\n\tu64 pre_vmenter_ssp_tbl;\n\tu16 vpid02;\n\tu16 last_vpid;\n\tint tsc_autostore_slot;\n\tstruct nested_vmx_msrs msrs;\n\tstruct {\n\t\tbool vmxon;\n\t\tbool guest_mode;\n\t} smm;\n\tgpa_t hv_evmcs_vmptr;\n\tstruct kvm_host_map hv_evmcs_map;\n\tstruct hv_enlightened_vmcs *hv_evmcs;\n};\n\nstruct ref_tracker_dir {};\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udplite_statistics;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct sysctl_fib_multipath_hash_seed {\n\tu32 user_seed;\n\tu32 mp_seed;\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 0;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tstruct fib_rules_ops *rules_ops;\n\tstruct fib_table *fib_main;\n\tstruct fib_table *fib_default;\n\tunsigned int fib_rules_require_fldissect;\n\tbool fib_has_custom_rules;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct mr_table *mrt;\n\tstruct sysctl_fib_multipath_hash_seed sysctl_fib_multipath_hash_seed;\n\tu32 sysctl_fib_multipath_hash_fields;\n\tu8 sysctl_fib_multipath_use_neigh;\n\tu8 sysctl_fib_multipath_hash_policy;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct netns_vsock {\n\tstruct ctl_table_header *sysctl_hdr;\n\tu32 port;\n\tenum vsock_net_mode mode;\n\tenum vsock_net_mode child_ns_mode;\n\tint child_ns_mode_locked;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 64;\n\tstruct netns_ipv4 ipv4;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tu64 net_cookie;\n\tstruct sock *diag_nlsk;\n\tstruct netns_vsock vsock;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_sw_netstats;\n\nstruct pcpu_dstats;\n\nstruct netpoll_info;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct xdp_dev_bulk_queue;\n\nstruct rtnl_link_ops;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct netprio_map;\n\nstruct phy_link_topology;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct netpoll_info *npinfo;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tstruct list_head unlink_list;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tunsigned char nested_level;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct hlist_head qdisc_hash[16];\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct netprio_map *priomap;\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct rtnl_link_stats64;\n\nstruct netdev_bpf;\n\nstruct xdp_frame;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tvoid (*ndo_poll_controller)(struct net_device *);\n\tint (*ndo_netpoll_setup)(struct net_device *);\n\tvoid (*ndo_netpoll_cleanup)(struct net_device *);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct net_failover_info {\n\tstruct net_device *primary_dev;\n\tstruct net_device *standby_dev;\n\tstruct rtnl_link_stats64 primary_stats;\n\tstruct rtnl_link_stats64 standby_stats;\n\tstruct rtnl_link_stats64 failover_stats;\n\tspinlock_t stats_lock;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_packet_attrs {\n\tconst unsigned char *src;\n\tconst unsigned char *dst;\n\tu32 ip_src;\n\tu32 ip_dst;\n\tbool tcp;\n\tu16 sport;\n\tu16 dport;\n\tint timeout;\n\tint size;\n\tint max_size;\n\tu8 id;\n\tu16 queue_mapping;\n\tbool bad_csum;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct net_test {\n\tchar name[32];\n\tint (*fn)(struct net_device *);\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct net_test_priv {\n\tstruct net_packet_attrs *packet;\n\tstruct packet_type pt;\n\tstruct completion comp;\n\tint double_vlan;\n\tint vlan_id;\n\tint ok;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netconsole_target_stats {\n\tu64_stats_t xmit_drop_count;\n\tu64_stats_t enomem_count;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct netpoll {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tchar dev_name[16];\n\tu8 dev_mac[6];\n\tconst char *name;\n\tunion inet_addr local_ip;\n\tunion inet_addr remote_ip;\n\tbool ipv6;\n\tu16 local_port;\n\tu16 remote_port;\n\tu8 remote_mac[6];\n\tstruct sk_buff_head skb_pool;\n\tstruct work_struct refill_wq;\n};\n\nstruct netconsole_target {\n\tstruct list_head list;\n\tstruct netconsole_target_stats stats;\n\tenum target_state state;\n\tbool extended;\n\tbool release;\n\tstruct netpoll np;\n\tchar buf[1000];\n\tstruct work_struct resume_wq;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct xsk_buff_pool;\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_lag_lower_state_info {\n\tu8 link_up: 1;\n\tu8 tx_enabled: 1;\n};\n\nstruct netdev_lag_upper_info {\n\tenum netdev_lag_tx_type tx_type;\n\tenum netdev_lag_hash hash_type;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tlong: 64;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tint numa_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n};\n\ntypedef void (*netfs_io_terminated_t)(void *, ssize_t);\n\nstruct netfs_io_subrequest;\n\nstruct netfs_cache_ops {\n\tvoid (*end_operation)(struct netfs_cache_resources *);\n\tint (*read)(struct netfs_cache_resources *, loff_t, struct iov_iter *, enum netfs_read_from_hole, netfs_io_terminated_t, void *);\n\tint (*write)(struct netfs_cache_resources *, loff_t, struct iov_iter *, netfs_io_terminated_t, void *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_cache_resources *, long long unsigned int *, long long unsigned int *, long long unsigned int);\n\tenum netfs_io_source (*prepare_read)(struct netfs_io_subrequest *, long long unsigned int);\n\tvoid (*prepare_write_subreq)(struct netfs_io_subrequest *);\n\tint (*prepare_write)(struct netfs_cache_resources *, loff_t *, size_t *, size_t, loff_t, bool);\n\tenum netfs_io_source (*prepare_ondemand_read)(struct netfs_cache_resources *, loff_t, size_t *, loff_t, long unsigned int *, ino_t);\n\tint (*query_occupancy)(struct netfs_cache_resources *, loff_t, size_t, size_t, loff_t *, size_t *);\n};\n\nstruct netfs_cache_resources {\n\tconst struct netfs_cache_ops *ops;\n\tvoid *cache_priv;\n\tvoid *cache_priv2;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n};\n\nstruct netfs_group;\n\nstruct netfs_folio {\n\tstruct netfs_group *netfs_group;\n\tunsigned int dirty_offset;\n\tunsigned int dirty_len;\n};\n\nstruct netfs_group {\n\trefcount_t ref;\n\tvoid (*free)(struct netfs_group *);\n};\n\nstruct netfs_request_ops;\n\nstruct netfs_inode {\n\tstruct inode inode;\n\tconst struct netfs_request_ops *ops;\n\tstruct mutex wb_lock;\n\tloff_t remote_i_size;\n\tloff_t zero_point;\n\tatomic_t io_count;\n\tlong unsigned int flags;\n};\n\nstruct netfs_io_stream {\n\tstruct netfs_io_subrequest *construct;\n\tsize_t sreq_max_len;\n\tunsigned int sreq_max_segs;\n\tunsigned int submit_off;\n\tunsigned int submit_len;\n\tunsigned int submit_extendable_to;\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tstruct list_head subrequests;\n\tstruct netfs_io_subrequest *front;\n\tlong long unsigned int collected_to;\n\tsize_t transferred;\n\tshort unsigned int error;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tbool avail;\n\tbool active;\n\tbool need_retry;\n\tbool failed;\n\tbool transferred_valid;\n};\n\nstruct rolling_buffer {\n\tstruct folio_queue *head;\n\tstruct folio_queue *tail;\n\tstruct iov_iter iter;\n\tu8 next_head_slot;\n\tu8 first_tail_slot;\n};\n\nstruct netfs_io_request {\n\tunion {\n\t\tstruct work_struct cleanup_work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct work_struct work;\n\tstruct inode *inode;\n\tstruct address_space *mapping;\n\tstruct kiocb *iocb;\n\tstruct netfs_cache_resources cache_resources;\n\tstruct netfs_io_request *copy_to_cache;\n\tstruct list_head proc_link;\n\tstruct netfs_io_stream io_streams[2];\n\tstruct netfs_group *group;\n\tstruct rolling_buffer buffer;\n\twait_queue_head_t waitq;\n\tvoid *netfs_priv;\n\tvoid *netfs_priv2;\n\tstruct bio_vec *direct_bv;\n\tlong long unsigned int submitted;\n\tlong long unsigned int len;\n\tsize_t transferred;\n\tlong int error;\n\tlong long unsigned int i_size;\n\tlong long unsigned int start;\n\tatomic64_t issued_to;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int abandon_to;\n\tlong unsigned int no_unlock_folio;\n\tunsigned int direct_bv_count;\n\tunsigned int debug_id;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tatomic_t subreq_counter;\n\tunsigned int nr_group_rel;\n\tspinlock_t lock;\n\tunsigned char front_folio_order;\n\tenum netfs_io_origin origin;\n\tbool direct_bv_unpin;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tconst struct netfs_request_ops *netfs_ops;\n};\n\nstruct netfs_io_subrequest {\n\tstruct netfs_io_request *rreq;\n\tstruct work_struct work;\n\tstruct list_head rreq_link;\n\tstruct iov_iter io_iter;\n\tlong long unsigned int start;\n\tsize_t len;\n\tsize_t transferred;\n\trefcount_t ref;\n\tshort int error;\n\tshort unsigned int debug_index;\n\tunsigned int nr_segs;\n\tu8 retry_count;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tlong unsigned int flags;\n};\n\nstruct netfs_request_ops {\n\tmempool_t *request_pool;\n\tmempool_t *subrequest_pool;\n\tint (*init_request)(struct netfs_io_request *, struct file *);\n\tvoid (*free_request)(struct netfs_io_request *);\n\tvoid (*free_subrequest)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_io_request *);\n\tint (*prepare_read)(struct netfs_io_subrequest *);\n\tvoid (*issue_read)(struct netfs_io_subrequest *);\n\tbool (*is_still_valid)(struct netfs_io_request *);\n\tint (*check_write_begin)(struct file *, loff_t, unsigned int, struct folio **, void **);\n\tvoid (*done)(struct netfs_io_request *);\n\tvoid (*update_i_size)(struct inode *, loff_t);\n\tvoid (*post_modify)(struct inode *);\n\tvoid (*begin_writeback)(struct netfs_io_request *);\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*retry_request)(struct netfs_io_request *, struct netfs_io_stream *);\n\tvoid (*invalidate_cache)(struct netfs_io_request *);\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netpoll_info {\n\trefcount_t refcnt;\n\tstruct semaphore dev_lock;\n\tstruct sk_buff_head txq;\n\tstruct delayed_work tx_work;\n\tstruct callback_head rcu;\n};\n\nstruct netprio_map {\n\tstruct callback_head rcu;\n\tu32 priomap_len;\n\tu32 priomap[0];\n};\n\nstruct netsfhdr {\n\t__be32 version;\n\t__be64 magic;\n\tu8 id;\n} __attribute__((packed));\n\nstruct new_asid {\n\tunsigned int asid: 16;\n\tunsigned int need_flush: 1;\n};\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhlt_specific_cfg {\n\tu32 size;\n\tu8 caps[0];\n};\n\nstruct nhlt_endpoint {\n\tu32 length;\n\tu8 linktype;\n\tu8 instance_id;\n\tu16 vendor_id;\n\tu16 device_id;\n\tu16 revision_id;\n\tu32 subsystem_id;\n\tu8 device_type;\n\tu8 direction;\n\tu8 virtual_bus_id;\n\tstruct nhlt_specific_cfg config;\n} __attribute__((packed));\n\nstruct nhlt_acpi_table {\n\tstruct acpi_table_header header;\n\tu8 endpoint_count;\n\tstruct nhlt_endpoint desc[0];\n} __attribute__((packed));\n\nstruct nhlt_device_specific_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n};\n\nstruct nhlt_dmic_array_config {\n\tstruct nhlt_device_specific_config device_config;\n\tu8 array_type;\n};\n\nstruct wav_fmt {\n\tu16 fmt_tag;\n\tu16 channels;\n\tu32 samples_per_sec;\n\tu32 avg_bytes_per_sec;\n\tu16 block_align;\n\tu16 bits_per_sample;\n\tu16 cb_size;\n} __attribute__((packed));\n\nunion samples {\n\tu16 valid_bits_per_sample;\n\tu16 samples_per_block;\n\tu16 reserved;\n};\n\nstruct wav_fmt_ext {\n\tstruct wav_fmt fmt;\n\tunion samples sample;\n\tu32 channel_mask;\n\tu8 sub_fmt[16];\n};\n\nstruct nhlt_fmt_cfg {\n\tstruct wav_fmt_ext fmt_ext;\n\tstruct nhlt_specific_cfg config;\n};\n\nstruct nhlt_fmt {\n\tu8 fmt_count;\n\tstruct nhlt_fmt_cfg fmt_config[0];\n} __attribute__((packed));\n\nstruct nhlt_vendor_dmic_array_config {\n\tstruct nhlt_dmic_array_config dmic_config;\n\tu8 nb_mics;\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct nid_path {\n\tint depth;\n\thda_nid_t path[10];\n\tunsigned char idx[10];\n\tunsigned char multi[10];\n\tunsigned int ctls[3];\n\tbool active: 1;\n\tbool pin_enabled: 1;\n\tbool pin_fixed: 1;\n\tbool stream_enabled: 1;\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\ntypedef int (*nmi_handler_t)(unsigned int, struct pt_regs *);\n\nstruct nmi_desc {\n\traw_spinlock_t lock;\n\tnmi_handler_t emerg_handler;\n\tstruct list_head head;\n};\n\nstruct nmi_stats {\n\tunsigned int normal;\n\tunsigned int unknown;\n\tunsigned int external;\n\tunsigned int swallow;\n\tlong unsigned int recv_jiffies;\n\tlong unsigned int idt_seq;\n\tlong unsigned int idt_nmi_seq;\n\tlong unsigned int idt_ignored;\n\tatomic_long_t idt_calls;\n\tlong unsigned int idt_seq_snap;\n\tlong unsigned int idt_nmi_seq_snap;\n\tlong unsigned int idt_ignored_snap;\n\tlong int idt_calls_snap;\n};\n\nstruct nmiaction {\n\tstruct list_head list;\n\tnmi_handler_t handler;\n\tu64 max_duration;\n\tlong unsigned int flags;\n\tconst char *name;\n};\n\nstruct node {\n\tstruct device dev;\n\tstruct list_head access_list;\n};\n\nstruct node_access_nodes {\n\tstruct device dev;\n\tstruct list_head list_node;\n\tunsigned int access;\n};\n\nstruct node_attr {\n\tstruct device_attribute attr;\n\tenum node_states state;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_hstate {\n\tstruct kobject *hugepages_kobj;\n\tstruct kobject *hstate_kobjs[2];\n};\n\nstruct node_memory_type_map {\n\tstruct memory_dev_type *memtype;\n\tint map_count;\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct nodemask_scratch {\n\tnodemask_t mask1;\n\tnodemask_t mask2;\n};\n\nstruct nosave_region {\n\tstruct list_head list;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct ns2501_configuration {\n\tu8 sync;\n\tu8 conf;\n\tu8 syncb;\n\tu8 dither;\n\tu8 pll_a;\n\tu16 pll_b;\n\tu16 hstart;\n\tu16 hstop;\n\tu16 vstart;\n\tu16 vstop;\n\tu16 vsync;\n\tu16 vtotal;\n\tu16 hpos;\n\tu16 vpos;\n\tu16 voffs;\n\tu16 hscale;\n\tu16 vscale;\n};\n\nstruct ns2501_priv {\n\tbool quiet;\n\tconst struct ns2501_configuration *conf;\n};\n\nstruct ns2501_reg {\n\tu8 offset;\n\tu8 value;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n} __attribute__((packed));\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t drops1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct numa_group {\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tint nr_tasks;\n\tpid_t gid;\n\tint active_nodes;\n\tstruct callback_head rcu;\n\tlong unsigned int total_faults;\n\tlong unsigned int max_faults_cpu;\n\tlong unsigned int faults[0];\n};\n\nstruct numa_maps {\n\tlong unsigned int pages;\n\tlong unsigned int anon;\n\tlong unsigned int active;\n\tlong unsigned int writeback;\n\tlong unsigned int mapcount_max;\n\tlong unsigned int dirty;\n\tlong unsigned int swapcache;\n\tlong unsigned int node[64];\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n\tbool mmap_locked;\n\tstruct vm_area_struct *locked_vma;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tstruct mempolicy *task_mempolicy;\n};\n\nstruct numa_maps_private {\n\tstruct proc_maps_private proc_maps;\n\tstruct numa_maps md;\n};\n\nstruct numa_memblk {\n\tu64 start;\n\tu64 end;\n\tint nid;\n};\n\nstruct numa_meminfo {\n\tint nr_blks;\n\tstruct numa_memblk blk[128];\n};\n\nstruct numa_stats {\n\tlong unsigned int load;\n\tlong unsigned int runnable;\n\tlong unsigned int util;\n\tlong unsigned int compute_capacity;\n\tunsigned int nr_running;\n\tunsigned int weight;\n\tenum numa_type node_type;\n\tint idle_cpu;\n};\n\nstruct nvmem_cell_entry;\n\nstruct nvmem_cell {\n\tstruct nvmem_cell_entry *entry;\n\tconst char *id;\n\tint index;\n};\n\ntypedef int (*nvmem_cell_post_process_t)(void *, const char *, int, unsigned int, void *, size_t);\n\nstruct nvmem_device;\n\nstruct nvmem_cell_entry {\n\tconst char *name;\n\tint offset;\n\tsize_t raw_len;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n\tstruct device_node *np;\n\tstruct nvmem_device *nvmem;\n\tstruct list_head node;\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tsize_t raw_len;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n\tstruct device_node *np;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n};\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nstruct nvmem_keepout;\n\nstruct nvmem_layout;\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tbool add_legacy_fixed_of_cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool ignore_wp;\n\tstruct nvmem_layout *layout;\n\tstruct device_node *of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device {\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct list_head node;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tstruct nvmem_layout *layout;\n\tvoid *priv;\n\tbool sysfs_cells_populated;\n};\n\nstruct nvmem_keepout {\n\tunsigned int start;\n\tunsigned int end;\n\tunsigned char value;\n};\n\nstruct nvmem_layout {\n\tstruct device dev;\n\tstruct nvmem_device *nvmem;\n\tint (*add_cells)(struct nvmem_layout *);\n};\n\nstruct nvs_page {\n\tlong unsigned int phys_start;\n\tunsigned int size;\n\tvoid *kaddr;\n\tvoid *data;\n\tbool unmap;\n\tstruct list_head node;\n};\n\nstruct nvs_region {\n\t__u64 phys_start;\n\t__u64 size;\n\tstruct list_head node;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct od_dbs_tuners {\n\tunsigned int powersave_bias;\n};\n\nstruct od_ops {\n\tunsigned int (*powersave_bias_target)(struct cpufreq_policy *, unsigned int, unsigned int);\n};\n\nstruct policy_dbs_info {\n\tstruct cpufreq_policy *policy;\n\tstruct mutex update_mutex;\n\tu64 last_sample_time;\n\ts64 sample_delay_ns;\n\tatomic_t work_count;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\tstruct dbs_data *dbs_data;\n\tstruct list_head list;\n\tunsigned int rate_mult;\n\tunsigned int idle_periods;\n\tbool is_shared;\n\tbool work_in_progress;\n};\n\nstruct od_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int freq_lo;\n\tunsigned int freq_lo_delay_us;\n\tunsigned int freq_hi_delay_us;\n\tunsigned int sample_type: 1;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_pci_range {\n\tunion {\n\t\tu64 pci_addr;\n\t\tu64 bus_addr;\n\t};\n\tu64 cpu_addr;\n\tu64 parent_bus_addr;\n\tu64 size;\n\tu32 flags;\n};\n\nstruct of_bus;\n\nstruct of_pci_range_parser {\n\tstruct device_node *node;\n\tconst struct of_bus *bus;\n\tconst __be32 *range;\n\tconst __be32 *end;\n\tint na;\n\tint ns;\n\tint pna;\n\tbool dma;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nstruct ohci {\n\tvoid *registers;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_itimerval32 {\n\tstruct old_timeval32 it_interval;\n\tstruct old_timeval32 it_value;\n};\n\nstruct old_linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n};\n\nstruct old_timex32 {\n\tu32 modes;\n\ts32 offset;\n\ts32 freq;\n\ts32 maxerror;\n\ts32 esterror;\n\ts32 status;\n\ts32 constant;\n\ts32 precision;\n\ts32 tolerance;\n\tstruct old_timeval32 time;\n\ts32 tick;\n\ts32 ppsfreq;\n\ts32 jitter;\n\ts32 shift;\n\ts32 stabil;\n\ts32 jitcnt;\n\ts32 calcnt;\n\ts32 errcnt;\n\ts32 stbcnt;\n\ts32 tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct old_utimbuf32 {\n\told_time32_t actime;\n\told_time32_t modtime;\n};\n\nstruct old_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n};\n\nstruct oldold_utsname {\n\tchar sysname[9];\n\tchar nodename[9];\n\tchar release[9];\n\tchar version[9];\n\tchar machine[9];\n};\n\nunion omr_encoding {\n\tstruct {\n\t\tu8 omr_source: 4;\n\t\tu8 omr_remote: 1;\n\t\tu8 omr_hitm: 1;\n\t\tu8 omr_snoop: 1;\n\t\tu8 omr_promoted: 1;\n\t};\n\tu8 omr_full;\n};\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct segmented_address {\n\tulong ea;\n\tunsigned int seg;\n};\n\nstruct operand {\n\tenum {\n\t\tOP_REG = 0,\n\t\tOP_MEM = 1,\n\t\tOP_MEM_STR = 2,\n\t\tOP_IMM = 3,\n\t\tOP_XMM = 4,\n\t\tOP_YMM = 5,\n\t\tOP_MM = 6,\n\t\tOP_NONE = 7,\n\t} type;\n\tunsigned int bytes;\n\tunsigned int count;\n\tunion {\n\t\tlong unsigned int orig_val;\n\t\tu64 orig_val64;\n\t};\n\tunion {\n\t\tlong unsigned int *reg;\n\t\tstruct segmented_address mem;\n\t\tunsigned int xmm;\n\t\tunsigned int mm;\n\t} addr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tlong unsigned int val;\n\t\tu64 val64;\n\t\tchar valptr[32];\n\t\tsse128_t vec_val;\n\t\tavx256_t vec_val2;\n\t\tu64 mm_val;\n\t\tvoid *data;\n\t};\n};\n\nstruct opregion_acpi {\n\tu32 drdy;\n\tu32 csts;\n\tu32 cevt;\n\tu8 rsvd1[20];\n\tu32 didl[8];\n\tu32 cpdl[8];\n\tu32 cadl[8];\n\tu32 nadl[8];\n\tu32 aslp;\n\tu32 tidx;\n\tu32 chpd;\n\tu32 clid;\n\tu32 cdck;\n\tu32 sxsw;\n\tu32 evts;\n\tu32 cnot;\n\tu32 nrdy;\n\tu32 did2[7];\n\tu32 cpd2[7];\n\tu8 rsvd2[4];\n};\n\nstruct opregion_asle {\n\tu32 ardy;\n\tu32 aslc;\n\tu32 tche;\n\tu32 alsi;\n\tu32 bclp;\n\tu32 pfit;\n\tu32 cblv;\n\tu16 bclm[20];\n\tu32 cpfm;\n\tu32 epfm;\n\tu8 plut[74];\n\tu32 pfmb;\n\tu32 cddv;\n\tu32 pcft;\n\tu32 srot;\n\tu32 iuer;\n\tu64 fdss;\n\tu32 fdsp;\n\tu32 stat;\n\tu64 rvda;\n\tu32 rvds;\n\tu8 rsvd[58];\n} __attribute__((packed));\n\nstruct opregion_asle_ext {\n\tu32 phed;\n\tu8 bddc[256];\n\tu8 rsvd[764];\n};\n\nstruct opregion_header {\n\tu8 signature[16];\n\tu32 size;\n\tstruct {\n\t\tu8 rsvd;\n\t\tu8 revision;\n\t\tu8 minor;\n\t\tu8 major;\n\t} over;\n\tu8 bios_ver[32];\n\tu8 vbios_ver[16];\n\tu8 driver_ver[16];\n\tu32 mboxes;\n\tu32 driver_model;\n\tu32 pcon;\n\tu8 dver[32];\n\tu8 rsvd[124];\n};\n\nstruct opregion_swsci {\n\tu32 scic;\n\tu32 parm;\n\tu32 dslp;\n\tu8 rsvd[244];\n};\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct optimized_kprobe {\n\tstruct kprobe kp;\n\tstruct list_head list;\n\tstruct arch_optimized_insn optinsn;\n};\n\nstruct orc_entry {\n\ts16 sp_offset;\n\ts16 bp_offset;\n\tunsigned int sp_reg: 4;\n\tunsigned int bp_reg: 4;\n\tunsigned int type: 3;\n\tunsigned int signal: 1;\n} __attribute__((packed));\n\nstruct osnoise_entry {\n\tstruct trace_entry ent;\n\tu64 noise;\n\tu64 runtime;\n\tu64 max_sample;\n\tunsigned int hw_count;\n\tunsigned int nmi_count;\n\tunsigned int irq_count;\n\tunsigned int softirq_count;\n\tunsigned int thread_count;\n};\n\nstruct x86_cpu_id {\n\t__u16 vendor;\n\t__u16 family;\n\t__u16 model;\n\t__u16 steppings;\n\t__u16 feature;\n\t__u16 flags;\n\t__u8 type;\n\tkernel_ulong_t driver_data;\n};\n\nstruct override_status_id {\n\tstruct acpi_device_id hid[2];\n\tstruct x86_cpu_id cpu_ids[2];\n\tstruct dmi_system_id dmi_ids[2];\n\tconst char *uid;\n\tconst char *path;\n\tlong long unsigned int status;\n};\n\nstruct ovl_cache_entry {\n\tunsigned int len;\n\tunsigned int type;\n\tu64 real_ino;\n\tu64 ino;\n\tstruct list_head l_node;\n\tstruct rb_node node;\n\tstruct ovl_cache_entry *next_maybe_whiteout;\n\tbool is_upper;\n\tbool is_whiteout;\n\tbool check_xwhiteout;\n\tconst char *c_name;\n\tint c_len;\n\tchar name[0];\n};\n\nstruct ovl_cattr {\n\tdev_t rdev;\n\tumode_t mode;\n\tconst char *link;\n\tstruct dentry *hardlink;\n};\n\nstruct ovl_config {\n\tchar *upperdir;\n\tchar *workdir;\n\tchar **lowerdirs;\n\tbool default_permissions;\n\tint redirect_mode;\n\tint verity_mode;\n\tbool index;\n\tint uuid;\n\tbool nfs_export;\n\tint xino;\n\tbool metacopy;\n\tbool userxattr;\n\tbool ovl_volatile;\n};\n\nstruct ovl_fh;\n\nstruct ovl_copy_up_ctx {\n\tstruct dentry *parent;\n\tstruct dentry *dentry;\n\tstruct path lowerpath;\n\tstruct kstat stat;\n\tstruct kstat pstat;\n\tconst char *link;\n\tstruct dentry *destdir;\n\tstruct qstr destname;\n\tstruct dentry *workdir;\n\tconst struct ovl_fh *origin_fh;\n\tbool origin;\n\tbool indexed;\n\tbool metacopy;\n\tbool metacopy_digest;\n\tbool metadata_fsync;\n};\n\nstruct ovl_dir_cache {\n\tlong int refcount;\n\tu64 version;\n\tstruct list_head entries;\n\tstruct rb_root root;\n};\n\nstruct ovl_dir_file {\n\tbool is_real;\n\tbool is_upper;\n\tstruct ovl_dir_cache *cache;\n\tstruct list_head *cursor;\n\tstruct file *realfile;\n\tstruct file *upperfile;\n};\n\nstruct ovl_layer;\n\nstruct ovl_path {\n\tconst struct ovl_layer *layer;\n\tstruct dentry *dentry;\n};\n\nstruct ovl_entry {\n\tunsigned int __numlower;\n\tstruct ovl_path __lowerstack[0];\n};\n\nstruct ovl_fb {\n\tu8 version;\n\tu8 magic;\n\tu8 len;\n\tu8 flags;\n\tu8 type;\n\tuuid_t uuid;\n\tu32 fid[0];\n} __attribute__((packed));\n\nstruct ovl_fh {\n\tu8 padding[3];\n\tunion {\n\t\tstruct ovl_fb fb;\n\t\tstruct {\n\t\t\tstruct {} __empty_buf;\n\t\t\tu8 buf[0];\n\t\t};\n\t};\n};\n\nstruct ovl_file {\n\tstruct file *realfile;\n\tstruct file *upperfile;\n};\n\nstruct ovl_sb;\n\nstruct ovl_fs {\n\tunsigned int numlayer;\n\tunsigned int numfs;\n\tunsigned int numdatalayer;\n\tstruct ovl_layer *layers;\n\tstruct ovl_sb *fs;\n\tstruct dentry *workbasedir;\n\tstruct dentry *workdir;\n\tlong int namelen;\n\tstruct ovl_config config;\n\tconst struct cred *creator_cred;\n\tbool tmpfile;\n\tbool noxattr;\n\tbool nofh;\n\tbool upperdir_locked;\n\tbool workdir_locked;\n\tstruct inode *workbasedir_trap;\n\tstruct inode *workdir_trap;\n\tint xino_mode;\n\tatomic_long_t last_ino;\n\tstruct dentry *whiteout;\n\tbool no_shared_whiteout;\n\tstruct mutex whiteout_lock;\n\terrseq_t errseq;\n\tbool casefold;\n};\n\nstruct ovl_opt_set {\n\tbool metacopy;\n\tbool redirect;\n\tbool nfs_export;\n\tbool index;\n};\n\nstruct ovl_fs_context_layer;\n\nstruct ovl_fs_context {\n\tstruct path upper;\n\tstruct path work;\n\tsize_t capacity;\n\tsize_t nr;\n\tsize_t nr_data;\n\tstruct ovl_opt_set set;\n\tstruct ovl_fs_context_layer *lower;\n\tchar *lowerdir_all;\n\tbool casefold_set;\n};\n\nstruct ovl_fs_context_layer {\n\tchar *name;\n\tstruct path path;\n};\n\nstruct ovl_inode {\n\tunion {\n\t\tstruct ovl_dir_cache *cache;\n\t\tconst char *lowerdata_redirect;\n\t};\n\tconst char *redirect;\n\tu64 version;\n\tlong unsigned int flags;\n\tstruct inode vfs_inode;\n\tstruct dentry *__upperdentry;\n\tstruct ovl_entry *oe;\n\tstruct mutex lock;\n};\n\nstruct ovl_inode_params {\n\tstruct inode *newinode;\n\tstruct dentry *upperdentry;\n\tstruct ovl_entry *oe;\n\tbool index;\n\tchar *redirect;\n\tchar *lowerdata_redirect;\n};\n\nstruct ovl_layer {\n\tstruct vfsmount *mnt;\n\tstruct inode *trap;\n\tstruct ovl_sb *fs;\n\tint idx;\n\tint fsid;\n\tbool has_xwhiteouts;\n};\n\nstruct ovl_lookup_ctx {\n\tstruct dentry *dentry;\n\tstruct ovl_entry *oe;\n\tstruct ovl_path *stack;\n\tstruct ovl_path *origin_path;\n\tstruct dentry *upperdentry;\n\tstruct dentry *index;\n\tstruct inode *inode;\n\tunsigned int ctr;\n};\n\nstruct ovl_lookup_data {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tconst struct ovl_layer *layer;\n\tstruct qstr name;\n\tbool is_dir;\n\tbool opaque;\n\tbool xwhiteouts;\n\tbool stop;\n\tbool last;\n\tchar *redirect;\n\tchar *upperredirect;\n\tint metacopy;\n\tbool absolute_redirect;\n};\n\nstruct ovl_metacopy {\n\tu8 version;\n\tu8 len;\n\tu8 flags;\n\tu8 digest_algo;\n\tu8 digest[64];\n};\n\nstruct unicode_map;\n\nstruct ovl_readdir_data {\n\tstruct dir_context ctx;\n\tstruct dentry *dentry;\n\tbool is_lowest;\n\tstruct rb_root *root;\n\tstruct list_head *list;\n\tstruct list_head middle;\n\tstruct ovl_cache_entry *first_maybe_whiteout;\n\tstruct unicode_map *map;\n\tint count;\n\tint err;\n\tbool is_upper;\n\tbool d_type_supported;\n\tbool in_xwhiteouts_dir;\n};\n\nstruct ovl_readdir_translate {\n\tstruct dir_context *orig_ctx;\n\tstruct ovl_dir_cache *cache;\n\tstruct dir_context ctx;\n\tu64 parent_ino;\n\tint fsid;\n\tint xinobits;\n\tbool xinowarn;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct ovl_renamedata {\n\tstruct renamedata;\n\tstruct dentry *opaquedir;\n\tbool cleanup_whiteout;\n\tbool update_nlink;\n\tbool overwrite;\n};\n\nstruct ovl_sb {\n\tstruct super_block *sb;\n\tdev_t pseudo_dev;\n\tbool bad_uuid;\n\tbool is_lower;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tu64 bus_offset;\n};\n\nstruct p2sb_res_cache {\n\tu32 bus_dev_id;\n\tstruct resource res;\n};\n\nstruct p4_event_alias {\n\tu64 original;\n\tu64 alternative;\n};\n\nstruct p4_event_bind {\n\tunsigned int opcode;\n\tunsigned int escr_msr[2];\n\tunsigned int escr_emask;\n\tunsigned int shared;\n\tsigned char cntr[6];\n};\n\nstruct p4_pebs_bind {\n\tunsigned int metric_pebs;\n\tunsigned int metric_vert;\n};\n\nstruct p9_trans_module;\n\nstruct p9_client {\n\tspinlock_t lock;\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n\tenum p9_trans_status status;\n\tvoid *trans;\n\tstruct kmem_cache *fcall_cache;\n\tunion {\n\t\tstruct {\n\t\t\tint rfd;\n\t\t\tint wfd;\n\t\t} fd;\n\t\tstruct {\n\t\t\tu16 port;\n\t\t\tbool privport;\n\t\t} tcp;\n\t} trans_opts;\n\tstruct idr fids;\n\tstruct idr reqs;\n\tchar name[65];\n};\n\nstruct p9_client_opts {\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n};\n\nstruct p9_fcall {\n\tu32 size;\n\tu8 id;\n\tu16 tag;\n\tsize_t offset;\n\tsize_t capacity;\n\tstruct kmem_cache *cache;\n\tu8 *sdata;\n\tbool zc;\n};\n\nstruct p9_conn;\n\nstruct p9_poll_wait {\n\tstruct p9_conn *conn;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_addr;\n};\n\nstruct p9_req_t;\n\nstruct p9_conn {\n\tstruct list_head mux_list;\n\tstruct p9_client *client;\n\tint err;\n\tspinlock_t req_lock;\n\tstruct list_head req_list;\n\tstruct list_head unsent_req_list;\n\tstruct p9_req_t *rreq;\n\tstruct p9_req_t *wreq;\n\tchar tmp_buf[7];\n\tstruct p9_fcall rc;\n\tint wpos;\n\tint wsize;\n\tchar *wbuf;\n\tstruct list_head poll_pending_link;\n\tstruct p9_poll_wait poll_wait[2];\n\tpoll_table pt;\n\tstruct work_struct rq;\n\tstruct work_struct wq;\n\tlong unsigned int wsched;\n};\n\nstruct p9_qid {\n\tu8 type;\n\tu32 version;\n\tu64 path;\n};\n\nstruct p9_dirent {\n\tstruct p9_qid qid;\n\tu64 d_off;\n\tunsigned char d_type;\n\tchar d_name[256];\n};\n\nstruct p9_fd_opts {\n\tint rfd;\n\tint wfd;\n\tu16 port;\n\tbool privport;\n};\n\nstruct p9_fid {\n\tstruct p9_client *clnt;\n\tu32 fid;\n\trefcount_t count;\n\tint mode;\n\tstruct p9_qid qid;\n\tu32 iounit;\n\tkuid_t uid;\n\tvoid *rdir;\n\tstruct hlist_node dlist;\n\tstruct hlist_node ilist;\n};\n\nstruct p9_flock {\n\tu8 type;\n\tu32 flags;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_getlock {\n\tu8 type;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_iattr_dotl {\n\tu32 valid;\n\tu32 mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tu64 size;\n\tu64 atime_sec;\n\tu64 atime_nsec;\n\tu64 mtime_sec;\n\tu64 mtime_nsec;\n};\n\nstruct p9_rdir {\n\tint head;\n\tint tail;\n\tuint8_t buf[0];\n};\n\nstruct p9_rdma_opts {\n\tshort int port;\n\tbool privport;\n\tint sq_depth;\n\tint rq_depth;\n\tlong int timeout;\n};\n\nstruct p9_req_t {\n\tint status;\n\tint t_err;\n\trefcount_t refcount;\n\twait_queue_head_t wq;\n\tstruct p9_fcall tc;\n\tstruct p9_fcall rc;\n\tstruct list_head req_list;\n};\n\nstruct p9_rstatfs {\n\tu32 type;\n\tu32 bsize;\n\tu64 blocks;\n\tu64 bfree;\n\tu64 bavail;\n\tu64 files;\n\tu64 ffree;\n\tu64 fsid;\n\tu32 namelen;\n};\n\nstruct p9_session_opts {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tlong int session_lock_timeout;\n};\n\nstruct p9_stat_dotl {\n\tu64 st_result_mask;\n\tstruct p9_qid qid;\n\tu32 st_mode;\n\tkuid_t st_uid;\n\tkgid_t st_gid;\n\tu64 st_nlink;\n\tu64 st_rdev;\n\tu64 st_size;\n\tu64 st_blksize;\n\tu64 st_blocks;\n\tu64 st_atime_sec;\n\tu64 st_atime_nsec;\n\tu64 st_mtime_sec;\n\tu64 st_mtime_nsec;\n\tu64 st_ctime_sec;\n\tu64 st_ctime_nsec;\n\tu64 st_btime_sec;\n\tu64 st_btime_nsec;\n\tu64 st_gen;\n\tu64 st_data_version;\n};\n\nstruct p9_trans_fd {\n\tstruct file *rd;\n\tstruct file *wr;\n\tstruct p9_conn conn;\n};\n\nstruct p9_trans_module {\n\tstruct list_head list;\n\tchar *name;\n\tint maxsize;\n\tbool pooled_rbuffers;\n\tbool def;\n\tbool supports_vmalloc;\n\tstruct module *owner;\n\tint (*create)(struct p9_client *, struct fs_context *);\n\tvoid (*close)(struct p9_client *);\n\tint (*request)(struct p9_client *, struct p9_req_t *);\n\tint (*cancel)(struct p9_client *, struct p9_req_t *);\n\tint (*cancelled)(struct p9_client *, struct p9_req_t *);\n\tint (*zc_request)(struct p9_client *, struct p9_req_t *, struct iov_iter *, struct iov_iter *, int, int, int);\n\tint (*show_options)(struct seq_file *, struct p9_client *);\n};\n\nstruct p9_wstat {\n\tu16 size;\n\tu16 type;\n\tu32 dev;\n\tstruct p9_qid qid;\n\tu32 mode;\n\tu32 atime;\n\tu32 mtime;\n\tu64 length;\n\tconst char *name;\n\tconst char *uid;\n\tconst char *gid;\n\tconst char *muid;\n\tchar *extension;\n\tkuid_t n_uid;\n\tkgid_t n_gid;\n\tkuid_t n_muid;\n};\n\nstruct pacct_struct {\n\tint ac_flag;\n\tlong int ac_exitcode;\n\tlong unsigned int ac_mem;\n\tu64 ac_utime;\n\tu64 ac_stime;\n\tlong unsigned int ac_minflt;\n\tlong unsigned int ac_majflt;\n};\n\nstruct scsi_sense_hdr;\n\nstruct packet_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct scsi_sense_hdr *sshdr;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 history[16];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t tp_drops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct padata_cpumask {\n\tcpumask_var_t pcpu;\n\tcpumask_var_t cbcpu;\n};\n\nstruct padata_instance {\n\tstruct hlist_node cpu_online_node;\n\tstruct hlist_node cpu_dead_node;\n\tstruct workqueue_struct *parallel_wq;\n\tstruct workqueue_struct *serial_wq;\n\tstruct list_head pslist;\n\tstruct padata_cpumask cpumask;\n\tstruct kobject kobj;\n\tstruct mutex lock;\n\tu8 flags;\n};\n\nstruct padata_list {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct padata_mt_job {\n\tvoid (*thread_fn)(long unsigned int, long unsigned int, void *);\n\tvoid *fn_arg;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int min_chunk;\n\tint max_threads;\n\tbool numa_aware;\n};\n\nstruct padata_mt_job_state {\n\tspinlock_t lock;\n\tstruct completion completion;\n\tstruct padata_mt_job *job;\n\tint nworks;\n\tint nworks_fini;\n\tlong unsigned int chunk_size;\n};\n\nstruct parallel_data;\n\nstruct padata_priv {\n\tstruct list_head list;\n\tstruct parallel_data *pd;\n\tint cb_cpu;\n\tunsigned int seq_nr;\n\tint info;\n\tvoid (*parallel)(struct padata_priv *);\n\tvoid (*serial)(struct padata_priv *);\n};\n\nstruct padata_serial_queue {\n\tstruct padata_list serial;\n\tstruct work_struct work;\n\tstruct parallel_data *pd;\n};\n\nstruct padata_shell {\n\tstruct padata_instance *pinst;\n\tstruct parallel_data *pd;\n\tstruct parallel_data *opd;\n\tstruct list_head list;\n};\n\nstruct padata_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct padata_instance *, const struct attribute *, char *);\n\tssize_t (*store)(struct padata_instance *, const struct attribute *, const char *, size_t);\n};\n\nstruct padata_work {\n\tstruct work_struct pw_work;\n\tstruct list_head pw_list;\n\tvoid *pw_data;\n};\n\ntypedef struct page *pgtable_t;\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_list {\n\tstruct page_list *next;\n\tstruct page *page;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tlong: 0;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\tlong: 0;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tu32 xdp_mem_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pp_alloc_cache alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t} user;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_reporting_dev_info {\n\tint (*report)(struct page_reporting_dev_info *, struct scatterlist *, unsigned int);\n\tstruct delayed_work work;\n\tatomic_t state;\n\tunsigned int order;\n};\n\nstruct page_req_dsc {\n\tunion {\n\t\tstruct {\n\t\t\tu64 type: 8;\n\t\t\tu64 pasid_present: 1;\n\t\t\tu64 rsvd: 7;\n\t\t\tu64 rid: 16;\n\t\t\tu64 pasid: 20;\n\t\t\tu64 exe_req: 1;\n\t\t\tu64 pm_req: 1;\n\t\t\tu64 rsvd2: 10;\n\t\t};\n\t\tu64 qw_0;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu64 rd_req: 1;\n\t\t\tu64 wr_req: 1;\n\t\t\tu64 lpig: 1;\n\t\t\tu64 prg_index: 9;\n\t\t\tu64 addr: 52;\n\t\t};\n\t\tu64 qw_1;\n\t};\n\tu64 qw_2;\n\tu64 qw_3;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n\tlong: 64;\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pagerange_state {\n\tlong unsigned int cur_pfn;\n\tint ram;\n\tint not_ram;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct panel_bridge {\n\tstruct drm_bridge bridge;\n\tstruct drm_connector connector;\n\tstruct drm_panel *panel;\n\tu32 connector_type;\n};\n\nstruct parallel_data {\n\tstruct padata_shell *ps;\n\tstruct padata_list *reorder_list;\n\tstruct padata_serial_queue *squeue;\n\trefcount_t refcnt;\n\tunsigned int seq_nr;\n\tunsigned int processed;\n\tint cpu;\n\tstruct padata_cpumask cpumask;\n};\n\nstruct thermal_genl_cpu_caps;\n\nstruct param {\n\tstruct nlattr **attrs;\n\tstruct sk_buff *msg;\n\tconst char *name;\n\tint tz_id;\n\tint cdev_id;\n\tint trip_id;\n\tint trip_temp;\n\tint trip_type;\n\tint trip_hyst;\n\tint temp;\n\tint prev_temp;\n\tint direction;\n\tint cdev_state;\n\tint cdev_max_state;\n\tstruct thermal_genl_cpu_caps *cpu_capabilities;\n\tint cpu_capabilities_count;\n};\n\nstruct pv_cpu_ops {\n\tvoid (*io_delay)(void);\n};\n\nstruct pv_irq_ops {\n\tvoid (*safe_halt)(void);\n\tvoid (*halt)(void);\n};\n\nstruct pv_mmu_ops {\n\tvoid (*flush_tlb_user)(void);\n\tvoid (*flush_tlb_kernel)(void);\n\tvoid (*flush_tlb_one_user)(long unsigned int);\n\tvoid (*flush_tlb_multi)(const struct cpumask *, const struct flush_tlb_info *);\n\tvoid (*exit_mmap)(struct mm_struct *);\n\tvoid (*notify_page_enc_status_changed)(long unsigned int, int, bool);\n};\n\nstruct paravirt_patch_template {\n\tstruct pv_cpu_ops cpu;\n\tstruct pv_irq_ops irq;\n\tstruct pv_mmu_ops mmu;\n};\n\nstruct sync_semaphore {\n\tu32 semaphore;\n\tu8 unused[60];\n};\n\nstruct parent_scratch {\n\tunion guc_descs descs;\n\tstruct sync_semaphore go;\n\tstruct sync_semaphore join[9];\n\tu8 unused[1216];\n\tu32 wq[512];\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct pasid_dir_entry {\n\tu64 val;\n};\n\nstruct pasid_entry {\n\tu64 val[8];\n};\n\nstruct pasid_table {\n\tvoid *table;\n\tu32 max_pasid;\n};\n\nstruct patch_digest {\n\tu32 patch_id;\n\tu8 sha256[32];\n};\n\nstruct patch_site {\n\tu8 *instr;\n\tstruct alt_instr *alt;\n\tu8 buff[254];\n\tu8 len;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct pbe {\n\tvoid *address;\n\tvoid *orig_address;\n\tstruct pbe *next;\n};\n\nstruct pcc_mbox_chan {\n\tstruct mbox_chan *mchan;\n\tu64 shmem_base_addr;\n\tvoid *shmem;\n\tu64 shmem_size;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n};\n\nstruct pcc_chan_reg {\n\tvoid *vaddr;\n\tstruct acpi_generic_address *gas;\n\tu64 preserve_mask;\n\tu64 set_mask;\n\tu64 status_mask;\n};\n\nstruct pcc_chan_info {\n\tstruct pcc_mbox_chan chan;\n\tstruct pcc_chan_reg db;\n\tstruct pcc_chan_reg plat_irq_ack;\n\tstruct pcc_chan_reg cmd_complete;\n\tstruct pcc_chan_reg cmd_update;\n\tstruct pcc_chan_reg error;\n\tint plat_irq;\n\tu8 type;\n\tunsigned int plat_irq_flags;\n\tbool chan_in_use;\n};\n\nstruct pcc_data {\n\tstruct pcc_mbox_chan *pcc_chan;\n\tstruct completion done;\n\tstruct mbox_client cl;\n\tstruct acpi_pcc_info ctx;\n};\n\nstruct pccard_io_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t start;\n\tphys_addr_t stop;\n};\n\ntypedef struct pccard_io_map pccard_io_map;\n\nstruct pccard_mem_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t static_start;\n\tu_int card_start;\n\tstruct resource *res;\n};\n\ntypedef struct pccard_mem_map pccard_mem_map;\n\nstruct pcmcia_socket;\n\nstruct socket_state_t;\n\ntypedef struct socket_state_t socket_state_t;\n\nstruct pccard_operations {\n\tint (*init)(struct pcmcia_socket *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*get_status)(struct pcmcia_socket *, u_int *);\n\tint (*set_socket)(struct pcmcia_socket *, socket_state_t *);\n\tint (*set_io_map)(struct pcmcia_socket *, struct pccard_io_map *);\n\tint (*set_mem_map)(struct pcmcia_socket *, struct pccard_mem_map *);\n};\n\nstruct pccard_resource_ops {\n\tint (*validate_mem)(struct pcmcia_socket *);\n\tint (*find_io)(struct pcmcia_socket *, unsigned int, unsigned int *, unsigned int, unsigned int, struct resource **);\n\tstruct resource * (*find_mem)(long unsigned int, long unsigned int, long unsigned int, int, struct pcmcia_socket *);\n\tint (*init)(struct pcmcia_socket *);\n\tvoid (*exit)(struct pcmcia_socket *);\n};\n\nstruct pci2phy_map {\n\tstruct list_head list;\n\tint segment;\n\tint pbus_to_dieid[256];\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_check_idx_range {\n\tint start;\n\tint end;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct rcec_ea;\n\nstruct pcie_link_state;\n\nstruct pcie_bwctrl_data;\n\nstruct pci_sriov;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tstruct rcec_ea *rcec_ea;\n\tstruct pci_dev *rcec;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tstruct pcie_link_state *link_state;\n\tunsigned int aspm_l0s_support: 1;\n\tunsigned int aspm_l1_support: 1;\n\tunsigned int ltr_path: 1;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[11];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[11];\n\tstruct bin_attribute *res_attr_wc[11];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tunion {\n\t\tstruct pci_sriov *sriov;\n\t\tstruct pci_dev *physfn;\n\t};\n\tu16 ats_cap;\n\tu8 ats_stu;\n\tu16 pri_cap;\n\tu32 pri_reqs_alloc;\n\tunsigned int pasid_required: 1;\n\tu16 pasid_cap;\n\tu16 pasid_features;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_extra_dev {\n\tstruct pci_dev *dev[4];\n};\n\nstruct pci_filp_private {\n\tenum pci_mmap_state mmap_state;\n\tint write_combine;\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tint hook_offset;\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct pci_hostbridge_probe {\n\tu32 bus;\n\tu32 slot;\n\tu32 vendor;\n\tu32 device;\n};\n\nstruct pci_mmcfg_hostbridge_probe {\n\tu32 bus;\n\tu32 devfn;\n\tu32 vendor;\n\tu32 device;\n\tconst char * (*probe)(void);\n};\n\nstruct pci_mmcfg_region {\n\tstruct list_head list;\n\tstruct resource res;\n\tu64 address;\n\tchar *virt;\n\tu16 segment;\n\tu8 start_bus;\n\tu8 end_bus;\n\tchar name[30];\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_osc_bit_struct {\n\tu32 bit;\n\tchar *desc;\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pci_raw_ops {\n\tint (*read)(unsigned int, unsigned int, unsigned int, int, int, u32 *);\n\tint (*write)(unsigned int, unsigned int, unsigned int, int, int, u32);\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_root_info {\n\tstruct list_head list;\n\tchar name[12];\n\tstruct list_head resources;\n\tstruct resource busn;\n\tint node;\n\tint link;\n};\n\nstruct pci_sysdata {\n\tint domain;\n\tint node;\n\tstruct acpi_device *companion;\n\tvoid *iommu;\n\tvoid *fwnode;\n};\n\nstruct pci_root_info___2 {\n\tstruct acpi_pci_root_info common;\n\tstruct pci_sysdata sd;\n\tbool mcfg_added;\n\tu8 start_bus;\n\tu8 end_bus;\n};\n\nstruct pci_root_res {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct serial_private;\n\nstruct pciserial_board;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct setup_data {\n\t__u64 next;\n\t__u32 type;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct pci_setup_rom {\n\tstruct setup_data data;\n\tuint16_t vendor;\n\tuint16_t devid;\n\tuint64_t pcilen;\n\tlong unsigned int segment;\n\tlong unsigned int bus;\n\tlong unsigned int device;\n\tlong unsigned int function;\n\tuint8_t romdata[0];\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pci_sriov {\n\tint pos;\n\tint nres;\n\tu32 cap;\n\tu16 ctrl;\n\tu16 total_VFs;\n\tu16 initial_VFs;\n\tu16 num_VFs;\n\tu16 offset;\n\tu16 stride;\n\tu16 vf_device;\n\tu32 pgsz;\n\tu8 link;\n\tu8 max_VF_buses;\n\tu16 driver_max_VFs;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *self;\n\tu32 class;\n\tu8 hdr_type;\n\tu16 subsystem_vendor;\n\tu16 subsystem_device;\n\tresource_size_t barsz[6];\n\tu16 vf_rebar_cap;\n\tbool drivers_autoprobe;\n};\n\nstruct pcibios_fwaddrmap {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n\tresource_size_t fw_addr[11];\n};\n\nstruct pcie_bwctrl_data {\n\tstruct mutex set_speed_mutex;\n\tstruct thermal_cooling_device *cdev;\n};\n\nstruct pcie_device {\n\tint irq;\n\tstruct pci_dev *port;\n\tu32 service;\n\tvoid *priv_data;\n\tstruct device device;\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tint: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n};\n\nstruct pcie_pme_service_data {\n\tspinlock_t lock;\n\tstruct pcie_device *srv;\n\tstruct work_struct work;\n\tbool noirq;\n};\n\nstruct pcie_port_service_driver {\n\tconst char *name;\n\tint (*probe)(struct pcie_device *);\n\tvoid (*remove)(struct pcie_device *);\n\tint (*suspend)(struct pcie_device *);\n\tint (*resume_noirq)(struct pcie_device *);\n\tint (*resume)(struct pcie_device *);\n\tint (*runtime_suspend)(struct pcie_device *);\n\tint (*runtime_resume)(struct pcie_device *);\n\tint (*slot_reset)(struct pcie_device *);\n\tint port_type;\n\tu32 service;\n\tstruct device_driver driver;\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[11];\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct pcm_format_data {\n\tunsigned char width;\n\tunsigned char phys;\n\tsigned char le;\n\tsigned char signd;\n\tunsigned char silence[8];\n};\n\nstruct pcmcia_callback {\n\tstruct module *owner;\n\tint (*add)(struct pcmcia_socket *);\n\tint (*remove)(struct pcmcia_socket *);\n\tvoid (*requery)(struct pcmcia_socket *);\n\tint (*validate)(struct pcmcia_socket *, unsigned int *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*early_resume)(struct pcmcia_socket *);\n\tint (*resume)(struct pcmcia_socket *);\n};\n\nstruct pcmcia_device;\n\nstruct pcmcia_cfg_mem {\n\tstruct pcmcia_device *p_dev;\n\tint (*conf_check)(struct pcmcia_device *, void *);\n\tvoid *priv_data;\n\tcisparse_t parse;\n\tcistpl_cftable_entry_t dflt;\n};\n\nstruct pcmcia_device {\n\tstruct pcmcia_socket *socket;\n\tchar *devname;\n\tu8 device_no;\n\tu8 func;\n\tstruct config_t *function_config;\n\tstruct list_head socket_device_list;\n\tunsigned int irq;\n\tstruct resource *resource[6];\n\tresource_size_t card_addr;\n\tunsigned int vpp;\n\tunsigned int config_flags;\n\tunsigned int config_base;\n\tunsigned int config_index;\n\tunsigned int config_regs;\n\tunsigned int io_lines;\n\tu16 suspended: 1;\n\tu16 _irq: 1;\n\tu16 _io: 1;\n\tu16 _win: 4;\n\tu16 _locked: 1;\n\tu16 allow_func_id_match: 1;\n\tu16 has_manf_id: 1;\n\tu16 has_card_id: 1;\n\tu16 has_func_id: 1;\n\tu16 reserved: 4;\n\tu8 func_id;\n\tu16 manf_id;\n\tu16 card_id;\n\tchar *prod_id[4];\n\tu64 dma_mask;\n\tstruct device dev;\n\tvoid *priv;\n\tunsigned int open;\n};\n\nstruct pcmcia_device_id {\n\t__u16 match_flags;\n\t__u16 manf_id;\n\t__u16 card_id;\n\t__u8 func_id;\n\t__u8 function;\n\t__u8 device_no;\n\t__u32 prod_id_hash[4];\n\tconst char *prod_id[4];\n\tkernel_ulong_t driver_info;\n\tchar *cisfile;\n};\n\nstruct pcmcia_dynids {\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct pcmcia_driver {\n\tconst char *name;\n\tint (*probe)(struct pcmcia_device *);\n\tvoid (*remove)(struct pcmcia_device *);\n\tint (*suspend)(struct pcmcia_device *);\n\tint (*resume)(struct pcmcia_device *);\n\tstruct module *owner;\n\tconst struct pcmcia_device_id *id_table;\n\tstruct device_driver drv;\n\tstruct pcmcia_dynids dynids;\n};\n\nstruct pcmcia_dynid {\n\tstruct list_head node;\n\tstruct pcmcia_device_id id;\n};\n\nstruct pcmcia_loop_get {\n\tsize_t len;\n\tcisdata_t **buf;\n};\n\nstruct tuple_t;\n\ntypedef struct tuple_t tuple_t;\n\nstruct pcmcia_loop_mem {\n\tstruct pcmcia_device *p_dev;\n\tvoid *priv_data;\n\tint (*loop_tuple)(struct pcmcia_device *, tuple_t *, void *);\n};\n\nstruct socket_state_t {\n\tu_int flags;\n\tu_int csc_mask;\n\tu_char Vcc;\n\tu_char Vpp;\n\tu_char io_irq;\n};\n\nstruct pcmcia_socket {\n\tstruct module *owner;\n\tsocket_state_t socket;\n\tu_int state;\n\tu_int suspended_state;\n\tu_short functions;\n\tu_short lock_count;\n\tpccard_mem_map cis_mem;\n\tvoid *cis_virt;\n\tio_window_t io[2];\n\tpccard_mem_map win[4];\n\tstruct list_head cis_cache;\n\tsize_t fake_cis_len;\n\tu8 *fake_cis;\n\tstruct list_head socket_list;\n\tstruct completion socket_released;\n\tunsigned int sock;\n\tu_int features;\n\tu_int irq_mask;\n\tu_int map_size;\n\tu_int io_offset;\n\tu_int pci_irq;\n\tstruct pci_dev *cb_dev;\n\tu8 resource_setup_done;\n\tstruct pccard_operations *ops;\n\tstruct pccard_resource_ops *resource_ops;\n\tvoid *resource_data;\n\tvoid (*zoom_video)(struct pcmcia_socket *, int);\n\tint (*power_hook)(struct pcmcia_socket *, int);\n\tvoid (*tune_bridge)(struct pcmcia_socket *, struct pci_bus *);\n\tstruct task_struct *thread;\n\tstruct completion thread_done;\n\tunsigned int thread_events;\n\tunsigned int sysfs_events;\n\tstruct mutex skt_mutex;\n\tstruct mutex ops_mutex;\n\tspinlock_t thread_lock;\n\tstruct pcmcia_callback *callback;\n\tstruct list_head devices_list;\n\tu8 device_count;\n\tu8 pcmcia_pfc;\n\tatomic_t present;\n\tunsigned int pcmcia_irq;\n\tstruct device dev;\n\tvoid *driver_data;\n\tint resume_status;\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 64;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pdev_archdata {};\n\nstruct pdom_dev_data {\n\tstruct iommu_dev_data *dev_data;\n\tioasid_t pasid;\n\tstruct list_head list;\n};\n\nstruct pdom_iommu_info {\n\tstruct amd_iommu *iommu;\n\tu32 refcnt;\n};\n\nstruct pebs_basic {\n\tu64 format_group: 32;\n\tu64 retire_latency: 16;\n\tu64 format_size: 16;\n\tu64 ip;\n\tu64 applicable_counters;\n\tu64 tsc;\n};\n\nstruct pebs_cntr_header {\n\tu32 cntr;\n\tu32 fixed;\n\tu32 metrics;\n\tu32 reserved;\n};\n\nstruct pebs_gprs {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 cx;\n\tu64 dx;\n\tu64 bx;\n\tu64 sp;\n\tu64 bp;\n\tu64 si;\n\tu64 di;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n};\n\nstruct pebs_meminfo {\n\tu64 address;\n\tu64 aux;\n\tunion {\n\t\tu64 mem_latency;\n\t\tstruct {\n\t\t\tu64 instr_latency: 16;\n\t\t\tu64 pad2: 16;\n\t\t\tu64 cache_latency: 16;\n\t\t\tu64 pad3: 16;\n\t\t};\n\t};\n\tu64 tsx_tuning;\n};\n\nstruct pebs_record_core {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n};\n\nstruct pebs_record_nhm {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 status;\n\tu64 dla;\n\tu64 dse;\n\tu64 lat;\n};\n\nstruct pebs_record_skl {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 status;\n\tu64 dla;\n\tu64 dse;\n\tu64 lat;\n\tu64 real_ip;\n\tu64 tsx_tuning;\n\tu64 tsc;\n};\n\nstruct pebs_xmm {\n\tu64 xmm[32];\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[51];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tu8 expire;\n\tshort int free_count;\n\tstruct list_head lists[12];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[10];\n\ts8 stat_threshold;\n\tlong unsigned int vm_numa_event[6];\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\nstruct percpu_rw_semaphore;\n\ntypedef struct percpu_rw_semaphore *class_percpu_read_t;\n\ntypedef struct percpu_rw_semaphore *class_percpu_write_t;\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n\tstruct lockdep_map dep_map;\n};\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[1];\n\tlong unsigned int offset[1];\n\tlocal_lock_t lock;\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_amd_iommu {\n\tstruct list_head list;\n\tstruct pmu pmu;\n\tstruct amd_iommu *iommu;\n\tchar name[24];\n\tu8 max_banks;\n\tu8 max_counters;\n\tu64 cntr_assign_mask;\n\traw_spinlock_t lock;\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu64 hw_id;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___3 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct perf_event_mmap_page;\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\trefcount_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tstruct mutex aux_mutex;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\trefcount_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tint aux_in_pause_resume;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct unwind_stacktrace;\n\nstruct perf_callchain_deferred_event {\n\tstruct unwind_stacktrace *trace;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 cookie;\n\t\tu64 nr;\n\t\tu64 ips[0];\n\t} event;\n};\n\nstruct perf_callchain_entry {\n\tu64 nr;\n\tu64 ip[0];\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nunion perf_capabilities {\n\tstruct {\n\t\tu64 lbr_format: 6;\n\t\tu64 pebs_trap: 1;\n\t\tu64 pebs_arch_reg: 1;\n\t\tu64 pebs_format: 4;\n\t\tu64 smm_freeze: 1;\n\t\tu64 full_width_write: 1;\n\t\tu64 pebs_baseline: 1;\n\t\tu64 perf_metrics: 1;\n\t\tu64 pebs_output_pt_available: 1;\n\t\tu64 pebs_timing_info: 1;\n\t\tu64 anythread_deprecated: 1;\n\t\tu64 rdpmc_metrics_clear: 1;\n\t};\n\tu64 capabilities;\n};\n\nstruct perf_cgroup_info;\n\nstruct perf_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct perf_cgroup_info *info;\n};\n\nstruct perf_cgroup_event {\n\tchar *path;\n\tint path_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 id;\n\t\tchar path[0];\n\t} event_id;\n};\n\nstruct perf_time_ctx {\n\tu64 time;\n\tu64 stamp;\n\tu64 offset;\n};\n\nstruct perf_cgroup_info {\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tint active;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tu64 index;\n};\n\nstruct perf_event_context {\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head pmu_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tint nr_events;\n\tint nr_user;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tstruct perf_event_context *parent_ctx;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tint nr_cgroups;\n\tstruct callback_head callback_head;\n\tlocal_t nr_no_switch_fast;\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint online;\n\tstruct perf_cgroup *cgrp;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_event_pmu_context {\n\tstruct pmu *pmu;\n\tstruct perf_event_context *ctx;\n\tstruct list_head pmu_ctx_entry;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tunsigned int embedded: 1;\n\tunsigned int nr_events;\n\tunsigned int nr_cgroups;\n\tunsigned int nr_freq;\n\tatomic_t refcount;\n\tstruct callback_head callback_head;\n\tint rotate_necessary;\n};\n\nstruct perf_cpu_pmu_context {\n\tstruct perf_event_pmu_context epc;\n\tstruct perf_event_pmu_context *task_epc;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint active_oncpu;\n\tint exclusive;\n\tint pmu_disable_count;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n};\n\nstruct perf_ctx_data {\n\tstruct callback_head callback_head;\n\trefcount_t refcount;\n\tint global;\n\tstruct kmem_cache *ctx_cache;\n\tvoid *data;\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 text_poke: 1;\n\t__u64 build_id: 1;\n\t__u64 inherit_thread: 1;\n\t__u64 remove_on_exec: 1;\n\t__u64 sigtrap: 1;\n\t__u64 defer_callchain: 1;\n\t__u64 defer_output: 1;\n\t__u64 __reserved_1: 24;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\tunion {\n\t\t__u32 aux_action;\n\t\tstruct {\n\t\t\t__u32 aux_start_paused: 1;\n\t\t\t__u32 aux_pause: 1;\n\t\t\t__u32 aux_resume: 1;\n\t\t\t__u32 __reserved_3: 29;\n\t\t};\n\t};\n\t__u64 sig_data;\n\t__u64 config3;\n\t__u64 config4;\n};\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tunsigned int group_generation;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tstruct perf_event_pmu_context *pmu_ctx;\n\tatomic_long_t refcount;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\trefcount_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tunsigned int pending_wakeup;\n\tunsigned int pending_kill;\n\tunsigned int pending_disable;\n\tlong unsigned int pending_addr;\n\tstruct irq_work pending_irq;\n\tstruct irq_work pending_disable_irq;\n\tstruct callback_head pending_task;\n\tunsigned int pending_work;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tu64 id;\n\tatomic64_t lost_samples;\n\tu64 (*clock)(void);\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tstruct bpf_prog *prog;\n\tu64 bpf_cookie;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tstruct ftrace_ops ftrace_ops;\n\tstruct perf_cgroup *cgrp;\n\tstruct list_head sb_list;\n\tstruct list_head pmu_list;\n\tu32 orig_type;\n};\n\nstruct perf_event_min_heap {\n\tsize_t nr;\n\tsize_t size;\n\tstruct perf_event **data;\n\tstruct perf_event *preallocated[0];\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_user_time_short: 1;\n\t\t\t__u64 cap_____res: 58;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u32 __reserved_1;\n\t__u64 time_cycles;\n\t__u64 time_mask;\n\t__u8 __reserved[928];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct perf_guest_info_callbacks {\n\tunsigned int (*state)(void);\n\tlong unsigned int (*get_ip)(void);\n\tunsigned int (*handle_intel_pt_intr)(void);\n\tvoid (*handle_mediated_pmi)(void);\n};\n\nstruct perf_ibs {\n\tstruct pmu pmu;\n\tunsigned int msr;\n\tu64 config_mask;\n\tu64 cnt_mask;\n\tu64 enable_mask;\n\tu64 valid_mask;\n\tu16 min_period;\n\tu64 max_period;\n\tlong unsigned int offset_mask[1];\n\tint offset_max;\n\tunsigned int fetch_count_reset_broken: 1;\n\tunsigned int fetch_ignore_if_zero_rip: 1;\n\tstruct cpu_perf_ibs *pcpu;\n\tu64 (*get_count)(u64);\n};\n\nstruct perf_ibs_data {\n\tu32 size;\n\tunion {\n\t\tu32 data[0];\n\t\tu32 caps;\n\t};\n\tu64 regs[8];\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tu8 build_id[20];\n\tu32 build_id_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_msr {\n\tu64 msr;\n\tstruct attribute_group *grp;\n\tbool (*test)(int, void *);\n\tbool no_check;\n\tu64 mask;\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_open_properties {\n\tu32 sample_flags;\n\tu64 single_context: 1;\n\tu64 hold_preemption: 1;\n\tu64 ctx_handle;\n\tint metrics_set;\n\tint oa_format;\n\tbool oa_periodic;\n\tint oa_period_exponent;\n\tstruct intel_engine_cs *engine;\n\tbool has_sseu;\n\tstruct intel_sseu sseu;\n\tu64 poll_oa_period;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n};\n\nstruct perf_pmu_events_ht_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str_ht;\n\tconst char *event_str_noht;\n};\n\nstruct perf_pmu_events_hybrid_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n\tu64 pmu_type;\n};\n\nstruct perf_pmu_format_hybrid_attr {\n\tstruct device_attribute attr;\n\tu64 pmu_type;\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n} __attribute__((packed));\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct sched_state {\n\tint weight;\n\tint event;\n\tint counter;\n\tint unassigned;\n\tint nr_gp;\n\tu64 used;\n};\n\nstruct perf_sched {\n\tint max_weight;\n\tint max_events;\n\tint max_gp;\n\tint saved_states;\n\tstruct event_constraint **constraints;\n\tstruct sched_state state;\n\tstruct sched_state saved[2];\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_text_poke_event {\n\tconst void *old_bytes;\n\tconst void *new_bytes;\n\tsize_t pad;\n\tu16 old_len;\n\tu16 new_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t} event_id;\n};\n\nstruct pericom8250 {\n\tvoid *virt;\n\tunsigned int nr;\n\tint line[0];\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct pfnmap_track_ctx {\n\tstruct kref kref;\n\tlong unsigned int pfn;\n\tlong unsigned int size;\n};\n\nstruct ptdump_range;\n\nstruct ptdump_state {\n\tvoid (*note_page_pte)(struct ptdump_state *, long unsigned int, pte_t);\n\tvoid (*note_page_pmd)(struct ptdump_state *, long unsigned int, pmd_t);\n\tvoid (*note_page_pud)(struct ptdump_state *, long unsigned int, pud_t);\n\tvoid (*note_page_p4d)(struct ptdump_state *, long unsigned int, p4d_t);\n\tvoid (*note_page_pgd)(struct ptdump_state *, long unsigned int, pgd_t);\n\tvoid (*note_page_flush)(struct ptdump_state *);\n\tvoid (*effective_prot_pte)(struct ptdump_state *, pte_t);\n\tvoid (*effective_prot_pmd)(struct ptdump_state *, pmd_t);\n\tvoid (*effective_prot_pud)(struct ptdump_state *, pud_t);\n\tvoid (*effective_prot_p4d)(struct ptdump_state *, p4d_t);\n\tvoid (*effective_prot_pgd)(struct ptdump_state *, pgd_t);\n\tconst struct ptdump_range *range;\n};\n\nstruct pg_state {\n\tstruct ptdump_state ptdump;\n\tint level;\n\tpgprotval_t current_prot;\n\tpgprotval_t effective_prot;\n\tpgprotval_t prot_levels[5];\n\tlong unsigned int start_address;\n\tconst struct addr_marker *marker;\n\tlong unsigned int lines;\n\tbool to_dmesg;\n\tbool check_wx;\n\tlong unsigned int wx_pages;\n\tstruct seq_file *seq;\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[5];\n\tint node;\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tlong unsigned int present_early_pages;\n\tconst char *name;\n\tlong unsigned int nr_isolate_pageblock;\n\tseqlock_t span_seqlock;\n\tint initialized;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[11];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 0;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[10];\n\tatomic_long_t vm_numa_event[6];\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[321];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[5];\n\tstruct zonelist node_zonelists[2];\n\tint nr_zones;\n\tspinlock_t node_size_lock;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct mutex kswapd_lock;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tlong unsigned int min_unmapped_pages;\n\tlong unsigned int min_slab_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tunsigned int nbp_rl_start;\n\tlong unsigned int nbp_rl_nr_cand;\n\tunsigned int nbp_threshold;\n\tunsigned int nbp_th_start;\n\tlong unsigned int nbp_th_nr_cand;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[51];\n\tstruct memory_tier *memtier;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tu32 max_link_rate;\n\tenum phy_mode mode;\n};\n\nstruct phy_ops;\n\nstruct phy___2 {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tstruct lock_class_key lockdep_key;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n\tstruct dentry *debugfs;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_lvds {\n\tunsigned int bits_per_lane_and_dclk_cycle;\n\tlong unsigned int differential_clk_rate;\n\tunsigned int lanes;\n\tbool is_slave;\n};\n\nstruct phy_configure_opts_hdmi {\n\tunsigned int bpc;\n\tunion {\n\t\tlong long unsigned int tmds_char_rate;\n\t\tstruct {\n\t\t\tu8 rate_per_lane;\n\t\t\tu8 lanes;\n\t\t} frl;\n\t};\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n\tstruct phy_configure_opts_lvds lvds;\n\tstruct phy_configure_opts_hdmi hdmi;\n};\n\nstruct phylink;\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[1];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tlong unsigned int adv_old[2];\n\tlong unsigned int supported_eee[2];\n\tlong unsigned int advertising_eee[2];\n\tlong unsigned int eee_disabled_modes[2];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[1];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nunion phy_notify {\n\tenum phy_ufs_state ufs_state;\n};\n\nstruct phy_ops {\n\tint (*init)(struct phy___2 *);\n\tint (*exit)(struct phy___2 *);\n\tint (*power_on)(struct phy___2 *);\n\tint (*power_off)(struct phy___2 *);\n\tint (*set_mode)(struct phy___2 *, enum phy_mode, int);\n\tint (*set_media)(struct phy___2 *, enum phy_media);\n\tint (*set_speed)(struct phy___2 *, int);\n\tint (*configure)(struct phy___2 *, union phy_configure_opts *);\n\tint (*validate)(struct phy___2 *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy___2 *);\n\tint (*calibrate)(struct phy___2 *);\n\tint (*connect)(struct phy___2 *, int);\n\tint (*disconnect)(struct phy___2 *, int);\n\tint (*notify_phystate)(struct phy___2 *, union phy_notify);\n\tvoid (*release)(struct phy___2 *);\n\tstruct module *owner;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_port_ops;\n\nstruct phy_port {\n\tstruct list_head head;\n\tenum phy_port_parent parent_type;\n\tunion {\n\t\tstruct phy_device *phy;\n\t};\n\tconst struct phy_port_ops *ops;\n\tint pairs;\n\tlong unsigned int mediums;\n\tlong unsigned int supported[2];\n\tlong unsigned int interfaces[1];\n\tunsigned int not_described: 1;\n\tunsigned int active: 1;\n\tunsigned int is_mii: 1;\n\tunsigned int is_sfp: 1;\n};\n\nstruct phy_port_ops {\n\tvoid (*link_up)(struct phy_port *);\n\tvoid (*link_down)(struct phy_port *);\n\tint (*configure_mii)(struct phy_port *, bool, phy_interface_t);\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phylib_stubs {\n\tint (*hwtstamp_get)(struct phy_device *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct phy_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_ext_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct pi_desc {\n\tlong unsigned int pir[4];\n\tunion {\n\t\tstruct {\n\t\t\tu16 notifications;\n\t\t\tu8 nv;\n\t\t\tu8 rsvd_2;\n\t\t\tu32 ndst;\n\t\t};\n\t\tu64 control;\n\t};\n\tu32 rsvd[6];\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct fs_pin *bacct;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pids_cgroup {\n\tstruct cgroup_subsys_state css;\n\tatomic64_t counter;\n\tatomic64_t limit;\n\tint64_t watermark;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tatomic64_t events[2];\n\tatomic64_t events_local[2];\n};\n\nstruct piix_host_priv {\n\tconst int *map;\n\tu32 saved_iocfg;\n\tvoid *sidpr;\n};\n\nstruct piix_map_db {\n\tconst u32 mask;\n\tconst u16 port_enable;\n\tconst int map[0];\n};\n\nstruct pimreghdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__be16 csum;\n\t__be32 flags;\n};\n\nstruct pinctrl_map_mux {\n\tconst char *group;\n\tconst char *function;\n};\n\nstruct pinctrl_map_configs {\n\tconst char *group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_map {\n\tconst char *dev_name;\n\tconst char *name;\n\tenum pinctrl_map_type type;\n\tconst char *ctrl_dev_name;\n\tunion {\n\t\tstruct pinctrl_map_mux mux;\n\t\tstruct pinctrl_map_configs configs;\n\t} data;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nstruct pipe_fault_handler {\n\tbool (*handle)(struct intel_crtc *, enum plane_id);\n\tu32 fault;\n\tenum plane_id plane_id;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct pipe_wait {\n\tstruct trace_iterator *iter;\n\tint wait_index;\n};\n\nstruct pixel_format {\n\tunsigned char bits_per_pixel;\n\tbool indexed;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} alpha;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} red;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} green;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} blue;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char offset;\n\t\t\tunsigned char length;\n\t\t} index;\n\t};\n};\n\nstruct pkcs1pad_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct pkcs1pad_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n};\n\nstruct pkcs1pad_request {\n\tstruct scatterlist in_sg[2];\n\tstruct scatterlist out_sg[1];\n\tuint8_t *in_buf;\n\tuint8_t *out_buf;\n\tstruct akcipher_request child_req;\n};\n\nstruct x509_certificate;\n\nstruct pkcs7_signed_info;\n\nstruct pkcs7_message {\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate *crl;\n\tstruct pkcs7_signed_info *signed_infos;\n\tu8 version;\n\tbool have_authattrs;\n\tenum OID data_type;\n\tsize_t data_len;\n\tsize_t data_hdrlen;\n\tconst void *data;\n};\n\nstruct pkcs7_parse_context {\n\tstruct pkcs7_message *msg;\n\tstruct pkcs7_signed_info *sinfo;\n\tstruct pkcs7_signed_info **ppsinfo;\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate **ppcerts;\n\tlong unsigned int data;\n\tenum OID last_oid;\n\tunsigned int x509_index;\n\tunsigned int sinfo_index;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_skid;\n\tunsigned int raw_skid_size;\n\tbool expect_skid;\n};\n\nstruct pkcs7_signed_info {\n\tstruct pkcs7_signed_info *next;\n\tstruct x509_certificate *signer;\n\tunsigned int index;\n\tbool unsupported_crypto;\n\tbool blacklisted;\n\tconst void *msgdigest;\n\tunsigned int msgdigest_len;\n\tunsigned int authattrs_len;\n\tconst void *authattrs;\n\tlong unsigned int aa_set;\n\ttime64_t signing_time;\n\tstruct public_key_signature *sig;\n};\n\nstruct pkru_state {\n\tu32 pkru;\n\tu32 pad;\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tunsigned int uartclk;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tunsigned int type;\n\tupf_t flags;\n\tu16 bugs;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n};\n\nstruct stepping_desc {\n\tconst enum intel_step *map;\n\tsize_t size;\n};\n\nstruct subplatform_desc;\n\nstruct platform_desc {\n\tstruct intel_display_platforms platforms;\n\tconst char *name;\n\tconst struct subplatform_desc *subplatforms;\n\tconst struct intel_display_device_info *info;\n\tstruct stepping_desc step_info;\n};\n\nstruct mfd_cell;\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_hibernation_ops {\n\tint (*begin)(pm_message_t);\n\tvoid (*end)(void);\n\tint (*pre_snapshot)(void);\n\tvoid (*finish)(void);\n\tint (*prepare)(void);\n\tint (*enter)(void);\n\tvoid (*leave)(void);\n\tint (*pre_restore)(void);\n\tvoid (*restore_cleanup)(void);\n\tvoid (*recover)(void);\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)(void);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tvoid (*check)(void);\n\tbool (*wake)(void);\n\tvoid (*restore_early)(void);\n\tvoid (*restore)(void);\n\tvoid (*end)(void);\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)(void);\n\tvoid (*finish)(void);\n\tbool (*suspend_again)(void);\n\tvoid (*end)(void);\n\tvoid (*recover)(void);\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct pll_output_params {\n\tu32 ssc_up_spread;\n\tu32 mpll_div5_en;\n\tu32 hdmi_div;\n\tu32 ana_cp_int;\n\tu32 ana_cp_prop;\n\tu32 refclk_postscalar;\n\tu32 tx_clk_div;\n\tu32 fracn_quot;\n\tu32 fracn_rem;\n\tu32 fracn_den;\n\tu32 fracn_en;\n\tu32 pmix_en;\n\tu32 multiplier;\n\tint mpll_ana_v2i;\n\tint ana_freq_vco;\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct pmap {\n\tsize_t offset;\n\tconst char *name;\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_device_id;\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_link;\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_dma {\n\tunsigned char map;\n\tunsigned char flags;\n};\n\nstruct pnp_fixup {\n\tchar id[8];\n\tvoid (*quirk_function)(struct pnp_dev *);\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_info_buffer {\n\tchar *buffer;\n\tchar *curr;\n\tlong unsigned int size;\n\tlong unsigned int len;\n\tint stop;\n\tint error;\n};\n\ntypedef struct pnp_info_buffer pnp_info_buffer_t;\n\nstruct pnp_irq {\n\tpnp_irq_mask_t map;\n\tunsigned char flags;\n};\n\nstruct pnp_mem {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_port {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_option {\n\tstruct list_head list;\n\tunsigned int flags;\n\tlong unsigned int type;\n\tunion {\n\t\tstruct pnp_port port;\n\t\tstruct pnp_irq irq;\n\t\tstruct pnp_dma dma;\n\t\tstruct pnp_mem mem;\n\t} u;\n};\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pnp_resource {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[9];\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct port_stats {\n\tlong unsigned int bytes_sent;\n\tlong unsigned int bytes_received;\n\tlong unsigned int bytes_discarded;\n};\n\nstruct ports_device;\n\nstruct port_buffer;\n\nstruct virtqueue;\n\nstruct port___2 {\n\tstruct list_head list;\n\tstruct ports_device *portdev;\n\tstruct port_buffer *inbuf;\n\tspinlock_t inbuf_lock;\n\tspinlock_t outvq_lock;\n\tstruct virtqueue *in_vq;\n\tstruct virtqueue *out_vq;\n\tstruct dentry *debugfs_file;\n\tstruct port_stats stats;\n\tstruct console___2 cons;\n\tstruct cdev *cdev;\n\tstruct device *dev;\n\tstruct kref kref;\n\twait_queue_head_t waitqueue;\n\tchar *name;\n\tstruct fasync_struct *async_queue;\n\tu32 id;\n\tbool outvq_full;\n\tbool host_connected;\n\tbool guest_connected;\n};\n\nstruct port_buffer {\n\tchar *buf;\n\tsize_t size;\n\tsize_t len;\n\tsize_t offset;\n\tdma_addr_t dma;\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int sgpages;\n\tstruct scatterlist sg[0];\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct portdrv_service_data {\n\tstruct pcie_port_service_driver *drv;\n\tstruct device *dev;\n\tu32 service;\n};\n\nstruct virtio_console_control {\n\t__virtio32 id;\n\t__virtio16 event;\n\t__virtio16 value;\n};\n\nstruct virtio_device;\n\nstruct ports_device {\n\tstruct list_head list;\n\tstruct work_struct control_work;\n\tstruct work_struct config_work;\n\tstruct list_head ports;\n\tspinlock_t ports_lock;\n\tspinlock_t c_ivq_lock;\n\tspinlock_t c_ovq_lock;\n\tu32 max_nr_ports;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *c_ivq;\n\tstruct virtqueue *c_ovq;\n\tstruct virtio_console_control cpkt;\n\tstruct virtqueue **in_vqs;\n\tstruct virtqueue **out_vqs;\n\tint chr_major;\n};\n\nstruct ports_driver_data {\n\tstruct dentry *debugfs_dir;\n\tstruct list_head portdevs;\n\tstruct list_head consoles;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct posix_cputimers_work {\n\tstruct callback_head work;\n\tstruct mutex mutex;\n\tunsigned int scheduled;\n};\n\nstruct posix_msg_tree_node {\n\tstruct rb_node rb_node;\n\tstruct list_head msg_list;\n\tint priority;\n};\n\nstruct fsverity_info;\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct power_supply_battery_info;\n\nstruct power_supply {\n\tconst struct power_supply_desc *desc;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tchar **supplied_from;\n\tsize_t num_supplies;\n\tvoid *drv_data;\n\tstruct device dev;\n\tstruct work_struct changed_work;\n\tstruct delayed_work deferred_register_work;\n\tspinlock_t changed_lock;\n\tbool changed;\n\tbool update_groups;\n\tbool initialized;\n\tbool removing;\n\tatomic_t use_cnt;\n\tstruct power_supply_battery_info *battery_info;\n\tstruct rw_semaphore extensions_sem;\n\tstruct list_head extensions;\n\tstruct thermal_zone_device *tzd;\n\tstruct thermal_cooling_device *tcd;\n\tstruct led_trigger *trig;\n\tstruct led_trigger *charging_trig;\n\tstruct led_trigger *full_trig;\n\tstruct led_trigger *charging_blink_full_solid_trig;\n\tstruct led_trigger *charging_orange_full_green_trig;\n};\n\nstruct power_supply_attr {\n\tconst char *prop_name;\n\tchar attr_name[31];\n\tstruct device_attribute dev_attr;\n\tconst char * const *text_values;\n\tint text_values_len;\n};\n\nstruct power_supply_maintenance_charge_table;\n\nstruct power_supply_battery_ocv_table;\n\nstruct power_supply_resistance_temp_table;\n\nstruct power_supply_vbat_ri_table;\n\nstruct power_supply_battery_info {\n\tunsigned int technology;\n\tint energy_full_design_uwh;\n\tint charge_full_design_uah;\n\tint voltage_min_design_uv;\n\tint voltage_max_design_uv;\n\tint tricklecharge_current_ua;\n\tint precharge_current_ua;\n\tint precharge_voltage_max_uv;\n\tint charge_term_current_ua;\n\tint charge_restart_voltage_uv;\n\tint overvoltage_limit_uv;\n\tint constant_charge_current_max_ua;\n\tint constant_charge_voltage_max_uv;\n\tconst struct power_supply_maintenance_charge_table *maintenance_charge;\n\tint maintenance_charge_size;\n\tint alert_low_temp_charge_current_ua;\n\tint alert_low_temp_charge_voltage_uv;\n\tint alert_high_temp_charge_current_ua;\n\tint alert_high_temp_charge_voltage_uv;\n\tint factory_internal_resistance_uohm;\n\tint factory_internal_resistance_charging_uohm;\n\tint ocv_temp[20];\n\tint temp_ambient_alert_min;\n\tint temp_ambient_alert_max;\n\tint temp_alert_min;\n\tint temp_alert_max;\n\tint temp_min;\n\tint temp_max;\n\tconst struct power_supply_battery_ocv_table *ocv_table[20];\n\tint ocv_table_size[20];\n\tconst struct power_supply_resistance_temp_table *resist_table;\n\tint resist_table_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_discharging;\n\tint vbat2ri_discharging_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_charging;\n\tint vbat2ri_charging_size;\n\tint bti_resistance_ohm;\n\tint bti_resistance_tolerance;\n};\n\nstruct power_supply_battery_ocv_table {\n\tint ocv;\n\tint capacity;\n};\n\nstruct power_supply_config {\n\tstruct fwnode_handle *fwnode;\n\tvoid *drv_data;\n\tconst struct attribute_group **attr_grp;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tbool no_wakeup_source;\n};\n\nstruct power_supply_ext {\n\tconst char * const name;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property);\n};\n\nstruct power_supply_ext_registration {\n\tstruct list_head list_head;\n\tconst struct power_supply_ext *ext;\n\tstruct device *dev;\n\tvoid *data;\n};\n\nstruct power_supply_hwmon {\n\tstruct power_supply *psy;\n\tlong unsigned int *props;\n};\n\nstruct power_supply_led_trigger {\n\tstruct led_trigger trig;\n\tstruct power_supply *psy;\n};\n\nstruct power_supply_maintenance_charge_table {\n\tint charge_current_max_ua;\n\tint charge_voltage_max_uv;\n\tint charge_safety_timer_minutes;\n};\n\nunion power_supply_propval {\n\tint intval;\n\tconst char *strval;\n};\n\nstruct power_supply_resistance_temp_table {\n\tint temp;\n\tint resistance;\n};\n\nstruct power_supply_vbat_ri_table {\n\tint vbat_uv;\n\tint ri_uohm;\n};\n\nstruct ppin_info {\n\tint feature;\n\tint msr_ppin_ctl;\n\tint msr_ppin;\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pps_bind_args {\n\tint tsformat;\n\tint edge;\n\tint consumer;\n};\n\nstruct pps_device;\n\nstruct pps_source_info {\n\tchar name[32];\n\tchar path[32];\n\tint mode;\n\tvoid (*echo)(struct pps_device *, int, void *);\n\tstruct module *owner;\n\tstruct device *dev;\n};\n\nstruct pps_ktime {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kparams {\n\tint api_version;\n\tint mode;\n\tstruct pps_ktime assert_off_tu;\n\tstruct pps_ktime clear_off_tu;\n};\n\nstruct pps_device {\n\tstruct pps_source_info info;\n\tstruct pps_kparams params;\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tunsigned int last_ev;\n\tunsigned int last_fetched_ev;\n\twait_queue_head_t queue;\n\tunsigned int id;\n\tconst void *lookup_cookie;\n\tstruct device dev;\n\tstruct fasync_struct *async_queue;\n\tspinlock_t lock;\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct pps_kinfo {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n};\n\nstruct pps_fdata {\n\tstruct pps_kinfo info;\n\tstruct pps_ktime timeout;\n};\n\nstruct pps_ktime_compat {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kinfo_compat {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime_compat assert_tu;\n\tstruct pps_ktime_compat clear_tu;\n\tint current_mode;\n} __attribute__((packed));\n\nstruct pps_fdata_compat {\n\tstruct pps_kinfo_compat info;\n\tstruct pps_ktime_compat timeout;\n} __attribute__((packed));\n\nstruct pps_registers {\n\ti915_reg_t pp_ctrl;\n\ti915_reg_t pp_stat;\n\ti915_reg_t pp_on;\n\ti915_reg_t pp_off;\n\ti915_reg_t pp_div;\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n};\n\nstruct preempt_ops {\n\tvoid (*sched_in)(struct preempt_notifier *, int);\n\tvoid (*sched_out)(struct preempt_notifier *, struct task_struct *);\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct prioq_match_arg {\n\tint client;\n\tint timestamp;\n};\n\nstruct snd_seq_remove_events;\n\nstruct prioq_remove_match_arg {\n\tint client;\n\tstruct snd_seq_remove_events *info;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\nstruct prm_buffer {\n\tu8 prm_status;\n\tu64 efi_status;\n\tu8 prm_cmd;\n\tguid_t handler_guid;\n} __attribute__((packed));\n\nstruct prm_mmio_info;\n\nstruct prm_context_buffer {\n\tchar signature[4];\n\tu16 revision;\n\tu16 reserved;\n\tguid_t identifier;\n\tu64 static_data_buffer;\n\tstruct prm_mmio_info *mmio_ranges;\n};\n\nstruct prm_handler_info {\n\tefi_guid_t guid;\n\tefi_status_t (*handler_addr)(u64, void *);\n\tu64 static_data_buffer_addr;\n\tu64 acpi_param_buffer_addr;\n\tstruct list_head handler_list;\n};\n\nstruct prm_mmio_addr_range {\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu32 length;\n} __attribute__((packed));\n\nstruct prm_mmio_info {\n\tu64 mmio_count;\n\tstruct prm_mmio_addr_range addr_ranges[0];\n};\n\nstruct prm_module_info {\n\tguid_t guid;\n\tu16 major_rev;\n\tu16 minor_rev;\n\tu16 handler_count;\n\tstruct prm_mmio_info *mmio_info;\n\tbool updatable;\n\tstruct list_head module_list;\n\tstruct prm_handler_info handlers[0];\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct probe_entry_arg {\n\tstruct fetch_insn *code;\n\tunsigned int size;\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n};\n\nstruct sid_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct ptrace_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t tracer_pid;\n\t__kernel_pid_t tracer_tgid;\n};\n\nstruct proc_event {\n\tenum proc_cn_event what;\n\t__u32 cpu;\n\t__u64 timestamp_ns;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 err;\n\t\t} ack;\n\t\tstruct fork_proc_event fork;\n\t\tstruct exec_proc_event exec;\n\t\tstruct id_proc_event id;\n\t\tstruct sid_proc_event sid;\n\t\tstruct ptrace_proc_event ptrace;\n\t\tstruct comm_proc_event comm;\n\t\tstruct coredump_proc_event coredump;\n\t\tstruct exit_proc_event exit;\n\t} event_data;\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_input {\n\tenum proc_cn_mcast_op mcast_op;\n\tenum proc_cn_event event_type;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*proc_compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tstruct timespec64 val;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct pt_amdv1 {\n\tstruct pt_common common;\n};\n\nstruct pt_iommu_amdv1 {\n\tstruct pt_iommu iommu;\n\tstruct pt_amdv1 amdpt;\n};\n\nstruct protection_domain {\n\tunion {\n\t\tstruct iommu_domain domain;\n\t\tstruct pt_iommu iommu;\n\t\tstruct pt_iommu_amdv1 amdv1;\n\t\tstruct pt_iommu_x86_64 amdv2;\n\t};\n\tstruct list_head dev_list;\n\tspinlock_t lock;\n\tu16 id;\n\tenum protection_domain_mode pd_mode;\n\tbool dirty_tracking;\n\tstruct xarray iommu_array;\n\tstruct mmu_notifier mn;\n\tstruct list_head dev_data_list;\n\tstruct list_head viommu_list;\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*compat_ioctl)(struct sock *, unsigned int, long unsigned int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct prt_quirk {\n\tconst struct dmi_system_id *system;\n\tunsigned int segment;\n\tunsigned int bus;\n\tunsigned int device;\n\tunsigned char pin;\n\tconst char *source;\n\tconst char *actual_source;\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct psample_group {\n\tstruct list_head list;\n\tstruct net *net;\n\tu32 group_num;\n\tu32 refcount;\n\tu32 seq;\n\tstruct callback_head rcu;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psi_group {};\n\nstruct psmouse_protocol;\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct pstate_funcs {\n\tint (*get_max)(int);\n\tint (*get_max_physical)(int);\n\tint (*get_min)(int);\n\tint (*get_turbo)(int);\n\tint (*get_scaling)(void);\n\tint (*get_cpu_scaling)(int);\n\tint (*get_aperf_mperf_shift)(void);\n\tu64 (*get_val)(struct cpudata *, int);\n\tvoid (*get_vid)(struct cpudata *);\n};\n\nstruct psy_am_i_supplied_data {\n\tstruct power_supply *psy;\n\tunsigned int count;\n};\n\nstruct psy_for_each_psy_cb_data {\n\tint (*fn)(struct power_supply *, void *);\n\tvoid *data;\n};\n\nstruct psy_get_supplier_prop_data {\n\tstruct power_supply *psy;\n\tenum power_supply_property psp;\n\tunion power_supply_propval *val;\n};\n\nstruct pt_filter {\n\tlong unsigned int msr_a;\n\tlong unsigned int msr_b;\n\tlong unsigned int config;\n};\n\nstruct pt_filters {\n\tstruct pt_filter filter[4];\n\tunsigned int nr_filters;\n};\n\nstruct pt {\n\tstruct perf_output_handle handle;\n\tstruct pt_filters filters;\n\tint handle_nmi;\n\tint vmx_on;\n\tint pause_allowed;\n\tint resume_allowed;\n\tu64 output_base;\n\tu64 output_mask;\n};\n\nstruct pt_address_range {\n\tlong unsigned int msr_a;\n\tlong unsigned int msr_b;\n\tunsigned int reg_off;\n};\n\nstruct topa;\n\nstruct topa_entry;\n\nstruct pt_buffer {\n\tstruct list_head tables;\n\tstruct topa *first;\n\tstruct topa *last;\n\tstruct topa *cur;\n\tunsigned int cur_idx;\n\tsize_t output_off;\n\tlong unsigned int nr_pages;\n\tlocal_t data_size;\n\tlocal64_t head;\n\tbool snapshot;\n\tbool single;\n\tbool wrapped;\n\tlong int stop_pos;\n\tlong int intr_pos;\n\tstruct topa_entry *stop_te;\n\tstruct topa_entry *intr_te;\n\tvoid **data_pages;\n};\n\nstruct pt_cap_desc {\n\tconst char *name;\n\tu32 leaf;\n\tu8 reg;\n\tu32 mask;\n};\n\nstruct pt_ctx {\n\tu64 ctl;\n\tu64 status;\n\tu64 output_base;\n\tu64 output_mask;\n\tu64 cr3_match;\n\tu64 addr_a[4];\n\tu64 addr_b[4];\n};\n\nstruct pt_desc {\n\tu64 ctl_bitmask;\n\tu32 num_address_ranges;\n\tu32 caps[8];\n\tstruct pt_ctx host;\n\tstruct pt_ctx guest;\n};\n\nstruct pt_iommu_cfg {\n\tunsigned int features;\n\tu8 hw_max_vasz_lg2;\n\tu8 hw_max_oasz_lg2;\n};\n\nstruct pt_iommu_amdv1_cfg {\n\tstruct pt_iommu_cfg common;\n\tunsigned int starting_level;\n};\n\nstruct pt_iommu_amdv1_hw_info {\n\tu64 host_pt_root;\n\tu8 mode;\n};\n\nstruct pt_iommu_collect_args {\n\tstruct iommu_pages_list free_list;\n\tu8 check_mapped: 1;\n};\n\nstruct pt_iommu_dirty_args {\n\tstruct iommu_dirty_bitmap *dirty;\n\tunsigned int flags;\n};\n\nstruct pt_iommu_driver_ops {\n\tvoid (*change_top)(struct pt_iommu *, phys_addr_t, unsigned int);\n\tspinlock_t * (*get_top_lock)(struct pt_iommu *);\n};\n\nstruct pt_iommu_info {\n\tu64 pgsize_bitmap;\n};\n\nstruct vtdss_pt_write_attrs {\n\tu64 descriptor_bits;\n\tgfp_t gfp;\n};\n\nstruct pt_iommu_map_args {\n\tstruct iommu_iotlb_gather *iotlb_gather;\n\tstruct vtdss_pt_write_attrs attrs;\n\tpt_oaddr_t oa;\n\tunsigned int leaf_pgsize_lg2;\n\tunsigned int leaf_level;\n};\n\nstruct x86_64_pt_write_attrs {\n\tu64 descriptor_bits;\n\tgfp_t gfp;\n};\n\nstruct pt_iommu_map_args___2 {\n\tstruct iommu_iotlb_gather *iotlb_gather;\n\tstruct x86_64_pt_write_attrs attrs;\n\tpt_oaddr_t oa;\n\tunsigned int leaf_pgsize_lg2;\n\tunsigned int leaf_level;\n};\n\nstruct pt_iommu_map_args___3 {\n\tstruct iommu_iotlb_gather *iotlb_gather;\n\tstruct amdv1pt_write_attrs attrs;\n\tpt_oaddr_t oa;\n\tunsigned int leaf_pgsize_lg2;\n\tunsigned int leaf_level;\n};\n\nstruct pt_iommu_ops {\n\tint (*set_dirty)(struct pt_iommu *, dma_addr_t);\n\tvoid (*get_info)(struct pt_iommu *, struct pt_iommu_info *);\n\tvoid (*deinit)(struct pt_iommu *);\n};\n\nstruct pt_iommu_vtdss_cfg {\n\tstruct pt_iommu_cfg common;\n\tunsigned int top_level;\n};\n\nstruct pt_iommu_vtdss_hw_info {\n\tu64 ssptptr;\n\tu8 aw;\n};\n\nstruct pt_iommu_x86_64_cfg {\n\tstruct pt_iommu_cfg common;\n\tunsigned int top_level;\n};\n\nstruct pt_iommu_x86_64_hw_info {\n\tu64 gcr3_pt;\n\tu8 levels;\n};\n\nstruct pt_pmu {\n\tstruct pmu pmu;\n\tu32 caps[8];\n\tbool vmx;\n\tbool branch_en_always_on;\n\tlong unsigned int max_nonturbo_ratio;\n\tunsigned int tsc_art_num;\n\tunsigned int tsc_art_den;\n};\n\nstruct pt_table_p;\n\nstruct pt_range {\n\tstruct pt_common *common;\n\tstruct pt_table_p *top_table;\n\tpt_vaddr_t va;\n\tpt_vaddr_t last_va;\n\tu8 top_level;\n\tu8 max_vasz_lg2;\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\nstruct pt_state {\n\tstruct pt_range *range;\n\tstruct pt_table_p *table;\n\tstruct pt_table_p *table_lower;\n\tu64 entry;\n\tenum pt_entry_type type;\n\tshort unsigned int index;\n\tshort unsigned int end_index;\n\tu8 level;\n};\n\nstruct pt_unmap_args {\n\tstruct iommu_pages_list free_list;\n\tpt_vaddr_t unmapped;\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t\tatomic_t pt_share_count;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t *ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n};\n\nstruct ptdump_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct pte_list_desc {\n\tstruct pte_list_desc *more;\n\tu32 spte_count;\n\tu32 tail_count;\n\tu64 *sptes[14];\n};\n\nstruct ptp_clock {\n\tstruct posix_clock clock;\n\tstruct device dev;\n\tstruct ptp_clock_info *info;\n\tdev_t devid;\n\tint index;\n\tstruct pps_device *pps_source;\n\tlong int dialed_frequency;\n\tstruct list_head tsevqs;\n\tspinlock_t tsevqs_lock;\n\tstruct mutex pincfg_mux;\n\twait_queue_head_t tsev_wq;\n\tint defunct;\n\tstruct device_attribute *pin_dev_attr;\n\tstruct attribute **pin_attr;\n\tstruct attribute_group pin_attr_group;\n\tconst struct attribute_group *pin_attr_groups[2];\n\tstruct kthread_worker *kworker;\n\tstruct kthread_delayed_work aux_work;\n\tunsigned int max_vclocks;\n\tunsigned int n_vclocks;\n\tint *vclock_index;\n\tstruct mutex n_vclocks_mux;\n\tbool is_virtual_clock;\n\tbool has_cycles;\n\tstruct dentry *debugfs_root;\n};\n\nstruct ptp_clock_caps {\n\tint max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint pps;\n\tint n_pins;\n\tint cross_timestamping;\n\tint adjust_phase;\n\tint max_phase_adj;\n\tint rsv[11];\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\ts64 offset;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_perout_request {\n\tunion {\n\t\tstruct ptp_clock_time start;\n\t\tstruct ptp_clock_time phase;\n\t};\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunion {\n\t\tstruct ptp_clock_time on;\n\t\tunsigned int rsv[4];\n\t};\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_extts_event {\n\tstruct ptp_clock_time t;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct ptp_sys_offset {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[51];\n};\n\nstruct ptp_sys_offset_extended {\n\tunsigned int n_samples;\n\t__kernel_clockid_t clockid;\n\tunsigned int rsv[2];\n\tstruct ptp_clock_time ts[75];\n};\n\nstruct ptp_sys_offset_precise {\n\tstruct ptp_clock_time device;\n\tstruct ptp_clock_time sys_realtime;\n\tstruct ptp_clock_time sys_monoraw;\n\tunsigned int rsv[4];\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n\tclockid_t clockid;\n};\n\nstruct ptp_vclock {\n\tstruct ptp_clock *pclock;\n\tstruct ptp_clock_info info;\n\tstruct ptp_clock *clock;\n\tstruct hlist_node vclock_hash_node;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct mutex lock;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_sud_config {\n\t__u64 mode;\n\t__u64 selector;\n\t__u64 offset;\n\t__u64 len;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct public_key {\n\tvoid *key;\n\tu32 keylen;\n\tenum OID algo;\n\tvoid *params;\n\tu32 paramlen;\n\tbool key_is_private;\n\tconst char *id_type;\n\tconst char *pkey_algo;\n\tlong unsigned int key_eflags;\n};\n\nstruct public_key_signature {\n\tstruct asymmetric_key_id *auth_ids[3];\n\tu8 *s;\n\tu8 *m;\n\tu32 s_size;\n\tu32 m_size;\n\tbool m_free;\n\tbool algo_takes_data;\n\tconst char *pkey_algo;\n\tconst char *hash_algo;\n\tconst char *encoding;\n};\n\nstruct pv_info {\n\tconst char *name;\n};\n\nstruct pvclock_clock {\n\tint vclock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 base_cycles;\n\tu64 offset;\n};\n\nstruct pvclock_gtod_data {\n\tseqcount_t seq;\n\tstruct pvclock_clock clock;\n\tstruct pvclock_clock raw_clock;\n\tktime_t offs_boot;\n\tu64 wall_time_sec;\n};\n\nstruct pvclock_vcpu_time_info {\n\tu32 version;\n\tu32 pad0;\n\tu64 tsc_timestamp;\n\tu64 system_time;\n\tu32 tsc_to_system_mul;\n\ts8 tsc_shift;\n\tu8 flags;\n\tu8 pad[2];\n};\n\nstruct pvclock_vsyscall_time_info {\n\tstruct pvclock_vcpu_time_info pvti;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pvclock_wall_clock {\n\tu32 version;\n\tu32 sec;\n\tu32 nsec;\n};\n\nstruct pwm_args {\n\tu64 period;\n\tenum pwm_polarity polarity;\n};\n\nstruct pwm_capture {\n\tunsigned int period;\n\tunsigned int duty_cycle;\n};\n\nstruct pwm_chip;\n\nstruct pwm_device {\n\tconst char *label;\n\tlong unsigned int flags;\n\tunsigned int hwpwm;\n\tstruct pwm_chip *chip;\n\tstruct pwm_args args;\n\tstruct pwm_state state;\n\tstruct pwm_state last;\n};\n\nstruct pwm_ops;\n\nstruct pwm_chip {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tconst struct pwm_ops *ops;\n\tstruct module *owner;\n\tunsigned int id;\n\tunsigned int npwm;\n\tstruct pwm_device * (*of_xlate)(struct pwm_chip *, const struct of_phandle_args *);\n\tbool atomic;\n\tstruct gpio_chip gpio;\n\tbool uses_pwmchip_alloc;\n\tbool operational;\n\tunion {\n\t\tstruct mutex nonatomic_lock;\n\t\tspinlock_t atomic_lock;\n\t};\n\tstruct pwm_device pwms[0];\n};\n\nstruct pwm_waveform;\n\nstruct pwm_ops {\n\tint (*request)(struct pwm_chip *, struct pwm_device *);\n\tvoid (*free)(struct pwm_chip *, struct pwm_device *);\n\tint (*capture)(struct pwm_chip *, struct pwm_device *, struct pwm_capture *, long unsigned int);\n\tsize_t sizeof_wfhw;\n\tint (*round_waveform_tohw)(struct pwm_chip *, struct pwm_device *, const struct pwm_waveform *, void *);\n\tint (*round_waveform_fromhw)(struct pwm_chip *, struct pwm_device *, const void *, struct pwm_waveform *);\n\tint (*read_waveform)(struct pwm_chip *, struct pwm_device *, void *);\n\tint (*write_waveform)(struct pwm_chip *, struct pwm_device *, const void *);\n\tint (*apply)(struct pwm_chip *, struct pwm_device *, const struct pwm_state *);\n\tint (*get_state)(struct pwm_chip *, struct pwm_device *, struct pwm_state *);\n};\n\nstruct pwm_waveform {\n\tu64 period_length_ns;\n\tu64 duty_length_ns;\n\tu64 duty_offset_ns;\n};\n\nstruct pxp42_create_arb_in {\n\tstruct pxp_cmd_header header;\n\tu32 protection_mode;\n\tu32 session_id;\n};\n\nstruct pxp42_create_arb_out {\n\tstruct pxp_cmd_header header;\n};\n\nstruct pxp42_inv_stream_key_in {\n\tstruct pxp_cmd_header header;\n\tu32 rsvd[3];\n};\n\nstruct pxp42_inv_stream_key_out {\n\tstruct pxp_cmd_header header;\n\tu32 rsvd;\n};\n\nstruct pxp43_start_huc_auth_in {\n\tstruct pxp_cmd_header header;\n\t__le64 huc_base_address;\n};\n\nstruct q_inval {\n\traw_spinlock_t q_lock;\n\tvoid *desc;\n\tint *desc_status;\n\tint free_head;\n\tint free_tail;\n\tint free_cnt;\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qdisc_dump_args {\n\tstruct qdisc_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct qdisc_rate_table {\n\tstruct tc_ratespec rate;\n\tu32 data[256];\n\tstruct qdisc_rate_table *next;\n\tint refcnt;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_watchdog {\n\tstruct hrtimer timer;\n\tstruct Qdisc *qdisc;\n};\n\nstruct qi_desc {\n\tu64 qw0;\n\tu64 qw1;\n\tu64 qw2;\n\tu64 qw3;\n};\n\nstruct qi_batch {\n\tstruct qi_desc descs[16];\n\tunsigned int index;\n};\n\nstruct qnode {\n\tstruct mcs_spinlock mcs;\n};\n\nstruct qt_disk_dqdbheader {\n\t__le32 dqdh_next_free;\n\t__le32 dqdh_prev_free;\n\t__le16 dqdh_entries;\n\t__le16 dqdh_pad1;\n\t__le32 dqdh_pad2;\n};\n\nstruct qtree_fmt_operations {\n\tvoid (*mem2disk_dqblk)(void *, struct dquot *);\n\tvoid (*disk2mem_dqblk)(struct dquot *, void *);\n\tint (*is_id)(void *, struct dquot *);\n};\n\nstruct qtree_mem_dqinfo {\n\tstruct super_block *dqi_sb;\n\tint dqi_type;\n\tunsigned int dqi_blocks;\n\tunsigned int dqi_free_blk;\n\tunsigned int dqi_free_entry;\n\tunsigned int dqi_blocksize_bits;\n\tunsigned int dqi_entry_size;\n\tunsigned int dqi_usable_bs;\n\tunsigned int dqi_qtree_depth;\n\tconst struct qtree_fmt_operations *dqi_ops;\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct queue_pages {\n\tstruct list_head *pagelist;\n\tlong unsigned int flags;\n\tnodemask_t *nmask;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct vm_area_struct *first;\n\tstruct folio *large;\n\tlong int nr_failed;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quirk_entry {\n\tu32 nominal_freq;\n\tu32 lowest_freq;\n};\n\nstruct quirk_table {\n\tconst char *name;\n\tint (*func)(struct snd_ac97 *);\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n};\n\nstruct quota_module_name {\n\tint qm_fmt_id;\n\tchar *qm_mod_name;\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct rand_data {\n\tvoid *hash_state;\n\t__u64 prev_time;\n\t__u64 last_delta;\n\t__s64 last_delta2;\n\tunsigned int flags;\n\tunsigned int osr;\n\tunsigned char *mem;\n\tunsigned int memlocation;\n\tunsigned int memblocks;\n\tunsigned int memblocksize;\n\tunsigned int memaccessloops;\n\tunsigned int rct_count;\n\tunsigned int apt_cutoff;\n\tunsigned int apt_cutoff_permanent;\n\tunsigned int apt_observations;\n\tunsigned int apt_count;\n\tunsigned int apt_base;\n\tunsigned int health_failure;\n\tunsigned int apt_base_set: 1;\n};\n\nstruct range_node {\n\tstruct rb_node rn_rbnode;\n\tstruct rb_node rb_range_size;\n\tu32 rn_start;\n\tu32 rn_last;\n\tu32 __rn_subtree_last;\n};\n\nstruct rapl_model {\n\tstruct perf_msr *rapl_pkg_msrs;\n\tstruct perf_msr *rapl_core_msrs;\n\tlong unsigned int pkg_events;\n\tlong unsigned int core_events;\n\tunsigned int msr_power_unit;\n\tenum rapl_unit_quirk unit_quirk;\n};\n\nstruct rapl_pmu {\n\traw_spinlock_t lock;\n\tint n_active;\n\tint cpu;\n\tstruct list_head active_list;\n\tstruct pmu *pmu;\n\tktime_t timer_interval;\n\tstruct hrtimer hrtimer;\n};\n\nstruct rapl_pmus {\n\tstruct pmu pmu;\n\tunsigned int nr_rapl_pmu;\n\tunsigned int cntr_mask;\n\tstruct rapl_pmu *rapl_pmu[0];\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tu64 before;\n\tu64 after;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tatomic_t seq;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rb_time_struct {\n\tlocal64_t time;\n};\n\ntypedef struct rb_time_struct rb_time_t;\n\nstruct rb_wait_data {\n\tstruct rb_irq_work *irq_work;\n\tint seq;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct rc_map_table;\n\nstruct rc_map {\n\tstruct rc_map_table *scan;\n\tunsigned int size;\n\tunsigned int len;\n\tunsigned int alloc;\n\tenum rc_proto rc_proto;\n\tconst char *name;\n\tspinlock_t lock;\n};\n\nstruct ir_raw_event_ctrl;\n\nstruct rc_scancode_filter {\n\tu32 data;\n\tu32 mask;\n};\n\nstruct rc_dev {\n\tstruct device dev;\n\tbool managed_alloc;\n\tbool registered;\n\tbool idle;\n\tbool encode_wakeup;\n\tunsigned int minor;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst char *device_name;\n\tconst char *input_phys;\n\tstruct input_id input_id;\n\tconst char *driver_name;\n\tconst char *map_name;\n\tstruct rc_map rc_map;\n\tstruct mutex lock;\n\tstruct ir_raw_event_ctrl *raw;\n\tstruct input_dev *input_dev;\n\tenum rc_driver_type driver_type;\n\tu32 users;\n\tu64 allowed_protocols;\n\tu64 enabled_protocols;\n\tu64 allowed_wakeup_protocols;\n\tenum rc_proto wakeup_protocol;\n\tstruct rc_scancode_filter scancode_filter;\n\tstruct rc_scancode_filter scancode_wakeup_filter;\n\tu32 scancode_mask;\n\tvoid *priv;\n\tspinlock_t keylock;\n\tbool keypressed;\n\tu8 last_toggle;\n\tu32 last_keycode;\n\tenum rc_proto last_protocol;\n\tu64 last_scancode;\n\tlong unsigned int keyup_jiffies;\n\tstruct timer_list timer_keyup;\n\tstruct timer_list timer_repeat;\n\tu32 timeout;\n\tu32 min_timeout;\n\tu32 max_timeout;\n\tu32 rx_resolution;\n\tint (*change_protocol)(struct rc_dev *, u64 *);\n\tint (*open)(struct rc_dev *);\n\tvoid (*close)(struct rc_dev *);\n\tint (*s_tx_mask)(struct rc_dev *, u32);\n\tint (*s_tx_carrier)(struct rc_dev *, u32);\n\tint (*s_tx_duty_cycle)(struct rc_dev *, u32);\n\tint (*s_rx_carrier_range)(struct rc_dev *, u32, u32);\n\tint (*tx_ir)(struct rc_dev *, unsigned int *, unsigned int);\n\tvoid (*s_idle)(struct rc_dev *, bool);\n\tint (*s_wideband_receiver)(struct rc_dev *, int);\n\tint (*s_carrier_report)(struct rc_dev *, int);\n\tint (*s_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_wakeup_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_timeout)(struct rc_dev *, unsigned int);\n};\n\nstruct rc_map_table {\n\tu64 scancode;\n\tu32 keycode;\n};\n\nstruct rc_parameters {\n\tu16 initial_xmit_delay;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n};\n\nstruct rc_parameters_data {\n\tu8 bpp;\n\tu8 bpc;\n\tstruct rc_parameters params;\n};\n\nstruct rcec_ea {\n\tu8 nextbusn;\n\tu8 lastbusn;\n\tu32 bitmap;\n};\n\nstruct rchan_callbacks;\n\nstruct rchan_buf;\n\nstruct rchan {\n\tu32 version;\n\tsize_t subbuf_size;\n\tsize_t n_subbufs;\n\tsize_t alloc_size;\n\tconst struct rchan_callbacks *cb;\n\tstruct kref kref;\n\tvoid *private_data;\n\tstruct rchan_buf **buf;\n\tint is_global;\n\tstruct list_head list;\n\tstruct dentry *parent;\n\tint has_base_filename;\n\tchar base_filename[255];\n};\n\nstruct rchan_buf_stats {\n\tunsigned int full_count;\n\tunsigned int big_count;\n};\n\nstruct rchan_buf {\n\tvoid *start;\n\tvoid *data;\n\tsize_t offset;\n\tsize_t subbufs_produced;\n\tsize_t subbufs_consumed;\n\tstruct rchan *chan;\n\twait_queue_head_t read_wait;\n\tstruct irq_work wakeup_work;\n\tstruct dentry *dentry;\n\tstruct kref kref;\n\tstruct rchan_buf_stats stats;\n\tstruct page **page_array;\n\tunsigned int page_count;\n\tunsigned int finalized;\n\tsize_t *padding;\n\tsize_t bytes_consumed;\n\tsize_t early_bytes;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rchan_callbacks {\n\tint (*subbuf_start)(struct rchan_buf *, void *, void *);\n\tstruct dentry * (*create_buf_file)(const char *, struct dentry *, umode_t, struct rchan_buf *, int *);\n\tint (*remove_buf_file)(struct dentry *);\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t fqslock;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion rcu_special {\n\tstruct {\n\t\tu8 blocked;\n\t\tu8 need_qs;\n\t\tu8 exp_hint;\n\t\tu8 need_mb;\n\t} b;\n\tu32 s;\n};\n\nstruct rcu_stall_chk_rdr {\n\tint nesting;\n\tunion rcu_special rs;\n\tbool on_blkd_list;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[5];\n\tstruct rcu_node *level[3];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 0;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rcu_tasks;\n\ntypedef void (*rcu_tasks_gp_func_t)(struct rcu_tasks *);\n\ntypedef void (*pregp_func_t)(struct list_head *);\n\ntypedef void (*pertask_func_t)(struct task_struct *, struct list_head *);\n\ntypedef void (*postscan_func_t)(struct list_head *);\n\ntypedef void (*holdouts_func_t)(struct list_head *, bool, bool *);\n\ntypedef void (*postgp_func_t)(struct rcu_tasks *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\nstruct rcu_tasks_percpu;\n\nstruct rcu_tasks {\n\tstruct rcuwait cbs_wait;\n\traw_spinlock_t cbs_gbl_lock;\n\tstruct mutex tasks_gp_mutex;\n\tint gp_state;\n\tint gp_sleep;\n\tint init_fract;\n\tlong unsigned int gp_jiffies;\n\tlong unsigned int gp_start;\n\tlong unsigned int tasks_gp_seq;\n\tlong unsigned int n_ipis;\n\tlong unsigned int n_ipis_fails;\n\tstruct task_struct *kthread_ptr;\n\tlong unsigned int lazy_jiffies;\n\trcu_tasks_gp_func_t gp_func;\n\tpregp_func_t pregp_func;\n\tpertask_func_t pertask_func;\n\tpostscan_func_t postscan_func;\n\tholdouts_func_t holdouts_func;\n\tpostgp_func_t postgp_func;\n\tcall_rcu_func_t call_func;\n\tunsigned int wait_state;\n\tstruct rcu_tasks_percpu *rtpcpu;\n\tstruct rcu_tasks_percpu **rtpcp_array;\n\tint percpu_enqueue_shift;\n\tint percpu_enqueue_lim;\n\tint percpu_dequeue_lim;\n\tlong unsigned int percpu_dequeue_gpseq;\n\tstruct mutex barrier_q_mutex;\n\tatomic_t barrier_q_count;\n\tstruct completion barrier_q_completion;\n\tlong unsigned int barrier_q_seq;\n\tlong unsigned int barrier_q_start;\n\tchar *name;\n\tchar *kname;\n};\n\nstruct rcu_tasks_percpu {\n\tstruct rcu_segcblist cblist;\n\traw_spinlock_t lock;\n\tlong unsigned int rtp_jiffies;\n\tlong unsigned int rtp_n_lock_retries;\n\tstruct timer_list lazy_timer;\n\tunsigned int urgent_gp;\n\tstruct work_struct rtp_work;\n\tstruct irq_work rtp_irq_work;\n\tstruct callback_head barrier_q_head;\n\tstruct list_head rtp_blkd_tasks;\n\tstruct list_head rtp_exit_list;\n\tint cpu;\n\tint index;\n\tstruct rcu_tasks *rtpp;\n};\n\nstruct rcu_tasks_test_desc {\n\tstruct callback_head rh;\n\tconst char *name;\n\tbool notrun;\n\tlong unsigned int runstart;\n};\n\nstruct rdev_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct md_rdev *, char *);\n\tssize_t (*store)(struct md_rdev *, const char *, size_t);\n};\n\nstruct rdma_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head rpools;\n};\n\nstruct rdmacg_device {\n\tstruct list_head dev_node;\n\tstruct list_head rpools;\n\tchar *name;\n};\n\nstruct rdmacg_resource {\n\tint max;\n\tint usage;\n};\n\nstruct rdmacg_resource_pool {\n\tstruct rdmacg_device *device;\n\tstruct rdmacg_resource resources[2];\n\tstruct list_head cg_node;\n\tstruct list_head dev_node;\n\tu64 usage_sum;\n\tint num_max_cnt;\n};\n\nstruct read_cache {\n\tu8 data[1024];\n\tlong unsigned int pos;\n\tlong unsigned int end;\n};\n\nstruct read_write_emulator_ops {\n\tint (*read_write_prepare)(struct kvm_vcpu *, void *, int);\n\tint (*read_write_emulate)(struct kvm_vcpu *, gpa_t, void *, int);\n\tint (*read_write_mmio)(struct kvm_vcpu *, gpa_t, int, void *);\n\tint (*read_write_exit_mmio)(struct kvm_vcpu *, gpa_t, void *, int);\n\tbool write;\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct readdir_callback {\n\tstruct dir_context ctx;\n\tstruct old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct real_mode_header {\n\tu32 text_start;\n\tu32 ro_end;\n\tu32 trampoline_start;\n\tu32 trampoline_header;\n\tu32 trampoline_start64;\n\tu32 trampoline_pgd;\n\tu32 wakeup_start;\n\tu32 wakeup_header;\n\tu32 machine_real_restart_asm;\n\tu32 machine_real_restart_seg;\n};\n\nstruct virtnet_rq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t drops;\n\tu64_stats_t xdp_packets;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_redirects;\n\tu64_stats_t xdp_drops;\n\tu64_stats_t kicks;\n};\n\nstruct virtnet_interrupt_coalesce {\n\tu32 max_packets;\n\tu32 max_usecs;\n};\n\nstruct virtnet_rq_dma;\n\nstruct receive_queue {\n\tstruct virtqueue *vq;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tstruct virtnet_rq_stats stats;\n\tu16 calls;\n\tbool dim_enabled;\n\tstruct mutex dim_lock;\n\tstruct dim dim;\n\tu32 packets_in_napi;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct page *pages;\n\tstruct ewma_pkt_len mrg_avg_pkt_len;\n\tstruct page_frag alloc_frag;\n\tstruct scatterlist sg[19];\n\tunsigned int min_buf_len;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct virtnet_rq_dma *last_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xsk_rxq_info;\n\tstruct xdp_buff **xsk_buffs;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nstruct reg_whitelist {\n\ti915_reg_t offset_ldw;\n\ti915_reg_t offset_udw;\n\tu8 min_graphics_ver;\n\tu8 max_graphics_ver;\n\tu8 size;\n};\n\nstruct regcache_flat_data {\n\tlong unsigned int *valid;\n\tunsigned int data[0];\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tint (*populate)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regcache_rbtree_node;\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong unsigned int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\ts8 reg_shift;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct hwspinlock;\n\nstruct regmap_bus;\n\nstruct regmap_access_table;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_spinlock;\n\t\t\tlong unsigned int raw_spinlock_flags;\n\t\t};\n\t};\n\tstruct lock_class_key *lock_key;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tunsigned int reg_base;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool async;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool max_register_is_set;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tbool defer_caching;\n\tbool force_write_field;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool can_sleep;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regmap_range;\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_noinc_write)(void *, unsigned int, const void *, size_t);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_noinc_read)(void *, unsigned int, void *, size_t);\n\ntypedef void (*regmap_hw_free_context)(void *);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)(void);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tbool free_on_exit;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_noinc_write reg_noinc_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_reg_noinc_read reg_noinc_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint reg_shift;\n\tunsigned int reg_base;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tbool can_sleep;\n\tbool fast_io;\n\tbool io_port;\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tunsigned int max_register;\n\tbool max_register_is_0;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool use_relaxed_mmio;\n\tbool can_multi_write;\n\tbool use_hwlock;\n\tbool use_raw_spinlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tstruct list_head link;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\nstruct sgt_iter {\n\tstruct scatterlist *sgp;\n\tunion {\n\t\tlong unsigned int pfn;\n\t\tdma_addr_t dma;\n\t};\n\tunsigned int curr;\n\tunsigned int max;\n};\n\nstruct remap_pfn {\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tpgprot_t prot;\n\tstruct sgt_iter sgt;\n\tresource_size_t iobase;\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tu64 alloc_time_ns;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tstruct device *dev;\n\tenum rpm_status rpm_status;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tlong unsigned int blkcg_pols[1];\n\tstruct blkcg_gq *root_blkg;\n\tstruct list_head blkg_list;\n\tstruct mutex blkcg_mutex;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_trace *blk_trace;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct callback_head callback_head;\n\tstruct task_struct *mq_freeze_owner;\n\tint mq_freeze_owner_depth;\n\tbool mq_freeze_disk_dead;\n\tbool mq_freeze_queue_dying;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct request_wait {\n\tstruct dma_fence_cb cb;\n\tstruct task_struct *tsk;\n};\n\nstruct res_proc_context {\n\tstruct list_head *list;\n\tint (*preproc)(struct acpi_resource *, void *);\n\tvoid *preproc_data;\n\tint count;\n\tint error;\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct resource_win {\n\tstruct resource res;\n\tresource_size_t offset;\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct restore_data_record {\n\tlong unsigned int jump_address;\n\tlong unsigned int jump_address_phys;\n\tlong unsigned int cr3;\n\tlong unsigned int magic;\n\tlong unsigned int e820_checksum;\n};\n\nstruct resume_swap_area {\n\t__kernel_loff_t offset;\n\t__u32 dev;\n} __attribute__((packed));\n\nstruct resv_map {\n\tstruct kref refs;\n\tspinlock_t lock;\n\tstruct list_head regions;\n\tlong int adds_in_progress;\n\tstruct list_head region_cache;\n\tlong int region_cache_count;\n\tstruct rw_semaphore rw_sema;\n\tstruct page_counter *reservation_counter;\n\tlong unsigned int pages_per_hpage;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct rethook {\n\tvoid *data;\n\tvoid (*handler)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\tstruct objpool_head pool;\n\tstruct callback_head rcu;\n};\n\nstruct return_consumer {\n\t__u64 cookie;\n\t__u64 id;\n};\n\nstruct return_instance {\n\tstruct hprobe hprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tint cons_cnt;\n\tstruct return_instance *next;\n\tstruct callback_head rcu;\n\tstruct return_consumer consumer;\n\tstruct return_consumer *extra_consumers;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct rfkill_ops {\n\tvoid (*poll)(struct rfkill *, void *);\n\tvoid (*query)(struct rfkill *, void *);\n\tint (*set_block)(void *, bool);\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct ring_buffer_cpu_meta {\n\tlong unsigned int first_buffer;\n\tlong unsigned int head_buffer;\n\tlong unsigned int commit_buffer;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tint buffers[0];\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tlong unsigned int cache_pages_removed;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tsize_t event_size;\n\tint missed_events;\n};\n\nstruct ring_buffer_meta {\n\tint magic;\n\tint struct_sizes;\n\tlong unsigned int total_size;\n\tlong unsigned int buffers_offset;\n};\n\nstruct trace_buffer_meta;\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tlong unsigned int cnt;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_lost;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\trb_time_t write_stamp;\n\trb_time_t before_stamp;\n\tu64 event_stamp[5];\n\tu64 read_stamp;\n\tlong unsigned int pages_removed;\n\tunsigned int mapped;\n\tunsigned int user_mapped;\n\tstruct mutex mapping_lock;\n\tlong unsigned int *subbuf_ids;\n\tstruct trace_buffer_meta *meta_page;\n\tstruct ring_buffer_cpu_meta *ring_meta;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_head;\n\nstruct rmap_iterator {\n\tstruct rmap_head *head;\n\tstruct pte_list_desc *desc;\n\tint pos;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_gpio_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_gpio_data gpio_data;\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tstruct crypto_alg base;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct rock_ridge {\n\t__u8 signature[2];\n\t__u8 len;\n\t__u8 version;\n\tunion {\n\t\tstruct SU_SP_s SP;\n\t\tstruct SU_CE_s CE;\n\t\tstruct SU_ER_s ER;\n\t\tstruct RR_RR_s RR;\n\t\tstruct RR_PX_s PX;\n\t\tstruct RR_PN_s PN;\n\t\tstruct RR_SL_s SL;\n\t\tstruct RR_NM_s NM;\n\t\tstruct RR_CL_s CL;\n\t\tstruct RR_PL_s PL;\n\t\tstruct RR_TF_s TF;\n\t\tstruct RR_ZF_s ZF;\n\t} u;\n};\n\nstruct rock_state {\n\tvoid *buffer;\n\tunsigned char *chr;\n\tint len;\n\tint cont_size;\n\tint cont_extent;\n\tint cont_offset;\n\tint cont_loops;\n\tstruct inode *inode;\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct root_entry {\n\tu64 lo;\n\tu64 hi;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[2];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu32 nr_immed;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tu64 deferred_reenq_locals_seq;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n};\n\nstruct sched_info {\n\tlong unsigned int pcount;\n\tlong long unsigned int run_delay;\n\tlong long unsigned int max_run_delay;\n\tlong long unsigned int min_run_delay;\n\tlong long unsigned int last_arrival;\n\tlong long unsigned int last_queued;\n\tstruct timespec64 max_run_delay_ts;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tcall_single_data_t nohz_csd;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tunsigned int numa_migrate_on;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 64;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tu64 prev_steal_time;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tlong: 64;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tktime_t hrtick_time;\n\tstruct sched_info rq_sched_info;\n\tlong long unsigned int rq_cpu_time;\n\tunsigned int yld_count;\n\tunsigned int sched_count;\n\tunsigned int sched_goidle;\n\tunsigned int ttwu_count;\n\tunsigned int ttwu_local;\n\tstruct cpuidle_state *idle_state;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tstruct rq *core;\n\tstruct task_struct *core_pick;\n\tstruct sched_dl_entity *core_dl_server;\n\tunsigned int core_enabled;\n\tunsigned int core_sched_seq;\n\tstruct rb_root core_tree;\n\tunsigned int core_task_seq;\n\tunsigned int core_pick_seq;\n\tlong unsigned int core_cookie;\n\tunsigned int core_forceidle_count;\n\tunsigned int core_forceidle_seq;\n\tunsigned int core_forceidle_occupation;\n\tu64 core_forceidle_start;\n\tcpumask_var_t scratch_mask;\n\tatomic_t nr_iowait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n};\n\nstruct rsa_key {\n\tconst u8 *n;\n\tconst u8 *e;\n\tconst u8 *d;\n\tconst u8 *p;\n\tconst u8 *q;\n\tconst u8 *dp;\n\tconst u8 *dq;\n\tconst u8 *qinv;\n\tsize_t n_sz;\n\tsize_t e_sz;\n\tsize_t d_sz;\n\tsize_t p_sz;\n\tsize_t q_sz;\n\tsize_t dp_sz;\n\tsize_t dq_sz;\n\tsize_t qinv_sz;\n};\n\nstruct rsa_mpi_key {\n\tMPI n;\n\tMPI e;\n\tMPI d;\n\tMPI p;\n\tMPI q;\n\tMPI dp;\n\tMPI dq;\n\tMPI qinv;\n};\n\nstruct rsassa_pkcs1_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct rsassa_pkcs1_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n\tconst struct hash_prefix *hash_prefix;\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\t__kernel_size_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct sigcontext_64 {\n\t__u64 r8;\n\t__u64 r9;\n\t__u64 r10;\n\t__u64 r11;\n\t__u64 r12;\n\t__u64 r13;\n\t__u64 r14;\n\t__u64 r15;\n\t__u64 di;\n\t__u64 si;\n\t__u64 bp;\n\t__u64 bx;\n\t__u64 dx;\n\t__u64 ax;\n\t__u64 cx;\n\t__u64 sp;\n\t__u64 ip;\n\t__u64 flags;\n\t__u16 cs;\n\t__u16 gs;\n\t__u16 fs;\n\t__u16 ss;\n\t__u64 err;\n\t__u64 trapno;\n\t__u64 oldmask;\n\t__u64 cr2;\n\t__u64 fpstate;\n\t__u64 reserved1[8];\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tstruct sigcontext_64 uc_mcontext;\n\tsigset_t uc_sigmask;\n};\n\nstruct rt_sigframe {\n\tchar *pretcode;\n\tstruct ucontext uc;\n\tstruct siginfo info;\n};\n\nstruct sigcontext_32 {\n\t__u16 gs;\n\t__u16 __gsh;\n\t__u16 fs;\n\t__u16 __fsh;\n\t__u16 es;\n\t__u16 __esh;\n\t__u16 ds;\n\t__u16 __dsh;\n\t__u32 di;\n\t__u32 si;\n\t__u32 bp;\n\t__u32 sp;\n\t__u32 bx;\n\t__u32 dx;\n\t__u32 cx;\n\t__u32 ax;\n\t__u32 trapno;\n\t__u32 err;\n\t__u32 ip;\n\t__u16 cs;\n\t__u16 __csh;\n\t__u32 flags;\n\t__u32 sp_at_signal;\n\t__u16 ss;\n\t__u16 __ssh;\n\t__u32 fpstate;\n\t__u32 oldmask;\n\t__u32 cr2;\n};\n\nstruct ucontext_ia32 {\n\tunsigned int uc_flags;\n\tunsigned int uc_link;\n\tcompat_stack_t uc_stack;\n\tstruct sigcontext_32 uc_mcontext;\n\tcompat_sigset_t uc_sigmask;\n};\n\nstruct rt_sigframe_ia32 {\n\tu32 pretcode;\n\tint sig;\n\tu32 pinfo;\n\tu32 puc;\n\tcompat_siginfo_t info;\n\tstruct ucontext_ia32 uc;\n\tchar retcode[8];\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rta_mfc_stats {\n\t__u64 mfcs_packets;\n\t__u64 mfcs_bytes;\n\t__u64 mfcs_wrong_if;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtl821x_priv {\n\tbool enable_aldps;\n\tbool disable_clk_out;\n\tstruct clk *clk;\n\tu16 iner;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtree_node {\n\tstruct list_head list;\n\tlong unsigned int *data;\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct value_name_pair;\n\nstruct sa_name_list {\n\tint opcode;\n\tconst struct value_name_pair *arr;\n\tint arr_sz;\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar saved_cmdlines[0];\n};\n\nstruct saved_msr;\n\nstruct saved_msrs {\n\tunsigned int num;\n\tstruct saved_msr *array;\n};\n\nstruct saved_context {\n\tstruct pt_regs regs;\n\tu16 ds;\n\tu16 es;\n\tu16 fs;\n\tu16 gs;\n\tlong unsigned int kernelmode_gs_base;\n\tlong unsigned int usermode_gs_base;\n\tlong unsigned int fs_base;\n\tlong unsigned int cr0;\n\tlong unsigned int cr2;\n\tlong unsigned int cr3;\n\tlong unsigned int cr4;\n\tu64 misc_enable;\n\tstruct saved_msrs saved_msrs;\n\tlong unsigned int efer;\n\tu16 gdt_pad;\n\tstruct desc_ptr gdt_desc;\n\tu16 idt_pad;\n\tstruct desc_ptr idt;\n\tu16 ldt;\n\tu16 tss;\n\tlong unsigned int tr;\n\tlong unsigned int safety;\n\tlong unsigned int return_address;\n\tbool misc_enable_saved;\n} __attribute__((packed));\n\nstruct saved_msr {\n\tbool valid;\n\tstruct msr_info info;\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct scan_area {\n\tu64 addr;\n\tu64 size;\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_cache {\n\tstruct list_head *priolist;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n\tint (*task_is_throttled)(struct task_struct *, int);\n};\n\nstruct sched_clock_data {\n\tu64 tick_raw;\n\tu64 tick_gtod;\n\tu64 clock;\n};\n\nstruct sched_core_cookie {\n\trefcount_t refcnt;\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 newidle_stamp;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tunsigned int lb_count[3];\n\tunsigned int lb_failed[3];\n\tunsigned int lb_balanced[3];\n\tunsigned int lb_imbalance_load[3];\n\tunsigned int lb_imbalance_util[3];\n\tunsigned int lb_imbalance_task[3];\n\tunsigned int lb_imbalance_misfit[3];\n\tunsigned int lb_gained[3];\n\tunsigned int lb_hot_gained[3];\n\tunsigned int lb_nobusyg[3];\n\tunsigned int lb_nobusyq[3];\n\tunsigned int alb_count;\n\tunsigned int alb_failed;\n\tunsigned int alb_pushed;\n\tunsigned int sbe_count;\n\tunsigned int sbe_balanced;\n\tunsigned int sbe_pushed;\n\tunsigned int sbf_count;\n\tunsigned int sbf_balanced;\n\tunsigned int sbf_pushed;\n\tunsigned int ttwu_wake_remote;\n\tunsigned int ttwu_move_affine;\n\tunsigned int ttwu_move_balance;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n};\n\nstruct sched_statistics {\n\tu64 wait_start;\n\tu64 wait_max;\n\tu64 wait_count;\n\tu64 wait_sum;\n\tu64 iowait_count;\n\tu64 iowait_sum;\n\tu64 sleep_start;\n\tu64 sleep_max;\n\ts64 sum_sleep_runtime;\n\tu64 block_start;\n\tu64 block_max;\n\ts64 sum_block_runtime;\n\ts64 exec_max;\n\tu64 slice_max;\n\tu64 nr_migrations_cold;\n\tu64 nr_failed_migrations_affine;\n\tu64 nr_failed_migrations_running;\n\tu64 nr_failed_migrations_hot;\n\tu64 nr_forced_migrations;\n\tu64 nr_wakeups;\n\tu64 nr_wakeups_sync;\n\tu64 nr_wakeups_migrate;\n\tu64 nr_wakeups_local;\n\tu64 nr_wakeups_remote;\n\tu64 nr_wakeups_affine;\n\tu64 nr_wakeups_affine_attempts;\n\tu64 nr_wakeups_passive;\n\tu64 nr_wakeups_idle;\n\tu64 core_forceidle_sum;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sched_entity_stats {\n\tstruct sched_entity se;\n\tstruct sched_statistics stats;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 core_sched_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct scheduling_policy {\n\tu32 max_words;\n\tu32 num_words;\n\tu32 count;\n\tstruct guc_update_scheduling_policy h2g;\n};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scomp_alg {\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_acomp_streams streams;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tunion {\n\t\tvoid *src;\n\t\tlong unsigned int saddr;\n\t};\n};\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*compat_ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 ic_enable: 1;\n\tu8 cs_enble: 1;\n\tu8 st_enble: 1;\n\tu8 reserved1: 3;\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved2[3];\n\tu8 lbm_descriptor_type: 4;\n\tu8 rlbsr: 2;\n\tu8 reserved3: 1;\n\tu8 acdlu: 1;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_proc_entry {\n\tstruct list_head entry;\n\tconst struct scsi_host_template *sht;\n\tstruct proc_dir_entry *proc_dir;\n\tunsigned int present;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 reserved1: 7;\n\tu8 perm: 1;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 rel_lifetime: 6;\n\tu8 reserved3: 2;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n\tu64 seq;\n\tu32 cnt;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tconst char *reason;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REENQ_IMMED;\n\ts64 SCX_EV_REENQ_LOCAL_REPEAT;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[1];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tbool dump_disabled;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work disable_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n\tunsigned int group_overutilized;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tvoid *__ctx[0];\n};\n\nstruct sdesc {\n\tstruct shash_desc shash;\n};\n\nstruct sdw_intel_acpi_info {\n\tacpi_handle handle;\n\tint count;\n\tu32 link_mask;\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct xfrm_state;\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\ttime64_t sem_otime;\n\tlong: 64;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sembuf;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\t__kernel_long_t sem_otime;\n\t__kernel_ulong_t __unused1;\n\t__kernel_long_t sem_ctime;\n\t__kernel_ulong_t __unused2;\n\t__kernel_ulong_t sem_nsems;\n\t__kernel_ulong_t __unused3;\n\t__kernel_ulong_t __unused4;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct virtnet_sq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_tx_drops;\n\tu64_stats_t kicks;\n\tu64_stats_t tx_timeouts;\n\tu64_stats_t stop;\n\tu64_stats_t wake;\n};\n\nstruct send_queue {\n\tstruct virtqueue *vq;\n\tstruct scatterlist sg[19];\n\tchar name[16];\n\tstruct virtnet_sq_stats stats;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct napi_struct napi;\n\tbool reset;\n\tstruct xsk_buff_pool *xsk_pool;\n\tdma_addr_t xsk_hdr_dma_addr;\n};\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n\tbool has_siginfo;\n\tstruct kernel_siginfo info;\n};\n\nstruct sensor_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint index;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct seqcount_rwlock {\n\tseqcount_t seqcount;\n\trwlock_t *lock;\n};\n\ntypedef struct seqcount_rwlock seqcount_rwlock_t;\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct serial_ctrl_device {\n\tstruct device dev;\n\tstruct ida port_ida;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_in_rdev {\n\tstruct rb_root_cached serial_rb;\n\tspinlock_t serial_lock;\n\twait_queue_head_t serial_io_wait;\n};\n\nstruct serial_port_device {\n\tstruct device dev;\n\tstruct uart_port *port;\n\tunsigned int tx_enabled: 1;\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\nstruct serial_struct32 {\n\tcompat_int_t type;\n\tcompat_int_t line;\n\tcompat_uint_t port;\n\tcompat_int_t irq;\n\tcompat_int_t flags;\n\tcompat_int_t xmit_fifo_size;\n\tcompat_int_t custom_divisor;\n\tcompat_int_t baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char;\n\tcompat_int_t hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tcompat_uint_t iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tcompat_int_t reserved;\n};\n\ntypedef struct serio *class_serio_pause_rx_t;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nstruct serport {\n\tstruct tty_struct *tty;\n\twait_queue_head_t wait;\n\tstruct serio *serio;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_event_iter {\n\tenum set_event_iter_type type;\n\tunion {\n\t\tstruct trace_event_file *file;\n\t\tstruct event_mod_load *event_mod;\n\t};\n};\n\nstruct set_mtrr_data {\n\tlong unsigned int smp_base;\n\tlong unsigned int smp_size;\n\tunsigned int smp_reg;\n\tmtrr_type smp_type;\n};\n\nstruct set_proto_ctx_engines {\n\tstruct drm_i915_private *i915;\n\tunsigned int num_engines;\n\tstruct i915_gem_proto_engine *engines;\n};\n\nstruct setup_data_node {\n\tu64 paddr;\n\tu32 type;\n\tu32 len;\n};\n\nstruct setup_indirect {\n\t__u32 type;\n\t__u32 reserved;\n\t__u64 len;\n\t__u64 addr;\n};\n\nstruct sev_config {\n\t__u64 debug: 1;\n\t__u64 ghcbs_initialized: 1;\n\t__u64 use_cas: 1;\n\t__u64 __reserved: 61;\n};\n\nstruct vmcb_seg {\n\tu16 selector;\n\tu16 attrib;\n\tu32 limit;\n\tu64 base;\n};\n\nstruct sev_es_save_area {\n\tstruct vmcb_seg es;\n\tstruct vmcb_seg cs;\n\tstruct vmcb_seg ss;\n\tstruct vmcb_seg ds;\n\tstruct vmcb_seg fs;\n\tstruct vmcb_seg gs;\n\tstruct vmcb_seg gdtr;\n\tstruct vmcb_seg ldtr;\n\tstruct vmcb_seg idtr;\n\tstruct vmcb_seg tr;\n\tu64 pl0_ssp;\n\tu64 pl1_ssp;\n\tu64 pl2_ssp;\n\tu64 pl3_ssp;\n\tu64 u_cet;\n\tu8 reserved_0xc8[2];\n\tu8 vmpl;\n\tu8 cpl;\n\tu8 reserved_0xcc[4];\n\tu64 efer;\n\tu8 reserved_0xd8[104];\n\tu64 xss;\n\tu64 cr4;\n\tu64 cr3;\n\tu64 cr0;\n\tu64 dr7;\n\tu64 dr6;\n\tu64 rflags;\n\tu64 rip;\n\tu64 dr0;\n\tu64 dr1;\n\tu64 dr2;\n\tu64 dr3;\n\tu64 dr0_addr_mask;\n\tu64 dr1_addr_mask;\n\tu64 dr2_addr_mask;\n\tu64 dr3_addr_mask;\n\tu8 reserved_0x1c0[24];\n\tu64 rsp;\n\tu64 s_cet;\n\tu64 ssp;\n\tu64 isst_addr;\n\tu64 rax;\n\tu64 star;\n\tu64 lstar;\n\tu64 cstar;\n\tu64 sfmask;\n\tu64 kernel_gs_base;\n\tu64 sysenter_cs;\n\tu64 sysenter_esp;\n\tu64 sysenter_eip;\n\tu64 cr2;\n\tu8 reserved_0x248[32];\n\tu64 g_pat;\n\tu64 dbgctl;\n\tu64 br_from;\n\tu64 br_to;\n\tu64 last_excp_from;\n\tu64 last_excp_to;\n\tu8 reserved_0x298[80];\n\tu32 pkru;\n\tu32 tsc_aux;\n\tu64 tsc_scale;\n\tu64 tsc_offset;\n\tu8 reserved_0x300[8];\n\tu64 rcx;\n\tu64 rdx;\n\tu64 rbx;\n\tu64 reserved_0x320;\n\tu64 rbp;\n\tu64 rsi;\n\tu64 rdi;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu8 reserved_0x380[16];\n\tu64 guest_exit_info_1;\n\tu64 guest_exit_info_2;\n\tu64 guest_exit_int_info;\n\tu64 guest_nrip;\n\tu64 sev_features;\n\tu64 vintr_ctrl;\n\tu64 guest_exit_code;\n\tu64 virtual_tom;\n\tu64 tlb_id;\n\tu64 pcpu_id;\n\tu64 event_inj;\n\tu64 xcr0;\n\tu8 reserved_0x3f0[16];\n\tu64 x87_dp;\n\tu32 mxcsr;\n\tu16 x87_ftw;\n\tu16 x87_fsw;\n\tu16 x87_fcw;\n\tu16 x87_fop;\n\tu16 x87_ds;\n\tu16 x87_cs;\n\tu64 x87_rip;\n\tu8 fpreg_x87[80];\n\tu8 fpreg_xmm[256];\n\tu8 fpreg_ymm[256];\n};\n\nstruct severity {\n\tu64 mask;\n\tu64 result;\n\tunsigned char sev;\n\tshort unsigned int mcgmask;\n\tshort unsigned int mcgres;\n\tunsigned char ser;\n\tunsigned char context;\n\tunsigned char excp;\n\tunsigned char covered;\n\tunsigned int cpu_vfm;\n\tunsigned char cpu_minstepping;\n\tunsigned char bank_lo;\n\tunsigned char bank_hi;\n\tchar *msg;\n};\n\nstruct sfc_lock_data {\n\ti915_reg_t lock_reg;\n\ti915_reg_t ack_reg;\n\ti915_reg_t usage_reg;\n\tu32 lock_bit;\n\tu32 ack_bit;\n\tu32 usage_bit;\n\tu32 reset_bit;\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_module_caps {\n\tlong unsigned int interfaces[1];\n\tlong unsigned int link_modes[2];\n\tbool may_have_phy;\n\tu8 port;\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *, struct phy_device *);\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_device {\n\tstruct scsi_device *device;\n\twait_queue_head_t open_wait;\n\tstruct mutex open_rel_lock;\n\tint sg_tablesize;\n\tu32 index;\n\tstruct list_head sfds;\n\trwlock_t sfd_lock;\n\tatomic_t detaching;\n\tbool exclude;\n\tint open_cnt;\n\tchar sgdebug;\n\tchar name[32];\n\tstruct cdev *cdev;\n\tstruct kref d_ref;\n};\n\ntypedef struct sg_device Sg_device;\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_scatter_hold {\n\tshort unsigned int k_use_sg;\n\tunsigned int sglist_len;\n\tunsigned int bufflen;\n\tstruct page **pages;\n\tint page_order;\n\tchar dio_in_use;\n\tunsigned char cmd_opcode;\n};\n\ntypedef struct sg_scatter_hold Sg_scatter_hold;\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\ntypedef struct sg_io_hdr sg_io_hdr_t;\n\nstruct sg_fd;\n\nstruct sg_request {\n\tstruct list_head entry;\n\tstruct sg_fd *parentfp;\n\tSg_scatter_hold data;\n\tsg_io_hdr_t header;\n\tunsigned char sense_b[96];\n\tchar res_used;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar done;\n\tstruct request *rq;\n\tstruct bio *bio;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_request Sg_request;\n\nstruct sg_fd {\n\tstruct list_head sfd_siblings;\n\tstruct sg_device *parentdp;\n\twait_queue_head_t read_wait;\n\trwlock_t rq_list_lock;\n\tstruct mutex f_mutex;\n\tint timeout;\n\tint timeout_user;\n\tSg_scatter_hold reserve;\n\tstruct list_head rq_list;\n\tstruct fasync_struct *async_qp;\n\tSg_request req_arr[16];\n\tchar force_packid;\n\tchar cmd_q;\n\tunsigned char next_cmd_len;\n\tchar keep_orphan;\n\tchar mmap_called;\n\tchar res_in_use;\n\tstruct kref f_ref;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_fd Sg_fd;\n\nstruct sg_header {\n\tint pack_len;\n\tint reply_len;\n\tint pack_id;\n\tint result;\n\tunsigned int twelve_byte: 1;\n\tunsigned int target_status: 5;\n\tunsigned int host_status: 8;\n\tunsigned int driver_status: 8;\n\tunsigned int other_flags: 10;\n\tunsigned char sense_buffer[16];\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_list {\n\tunsigned int n;\n\tunsigned int size;\n\tsize_t len;\n\tstruct scatterlist *sg;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sg_proc_deviter {\n\tloff_t index;\n\tsize_t max;\n};\n\nstruct sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\ntypedef struct sg_req_info sg_req_info_t;\n\nstruct sg_scsi_id {\n\tint host_no;\n\tint channel;\n\tint scsi_id;\n\tint lun;\n\tint scsi_type;\n\tshort int h_cmd_per_lun;\n\tshort int d_queue_depth;\n\tint unused[2];\n};\n\ntypedef struct sg_scsi_id sg_scsi_id_t;\n\nstruct sgt_dma {\n\tstruct scatterlist *sg;\n\tdma_addr_t dma;\n\tdma_addr_t max;\n};\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha384_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct sha3_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct sha512_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct shadow_page_caches {\n\tstruct kvm_mmu_memory_cache *page_header_cache;\n\tstruct kvm_mmu_memory_cache *shadow_page_cache;\n\tstruct kvm_mmu_memory_cache *shadowed_info_cache;\n};\n\nstruct shadow_vmcs_field {\n\tu16 encoding;\n\tu16 offset;\n};\n\nstruct shake_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*export_core)(struct shash_desc *, void *);\n\tint (*import_core)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tint (*clone_tfm)(struct crypto_shash *, struct crypto_shash *);\n\tunsigned int descsize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int digestsize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct hash_alg_common halg;\n\t};\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[120];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\t__kernel_size_t shm_segsz;\n\tlong int shm_atime;\n\tlong int shm_dtime;\n\tlong int shm_ctime;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct shortname_table {\n\tunsigned int id;\n\tconst char *s;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct sig_alg {\n\tint (*sign)(struct crypto_sig *, const void *, unsigned int, void *, unsigned int);\n\tint (*verify)(struct crypto_sig *, const void *, unsigned int, const void *, unsigned int);\n\tint (*set_pub_key)(struct crypto_sig *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_sig *, const void *, unsigned int);\n\tunsigned int (*key_size)(struct crypto_sig *);\n\tunsigned int (*digest_size)(struct crypto_sig *);\n\tunsigned int (*max_size)(struct crypto_sig *);\n\tint (*init)(struct crypto_sig *);\n\tvoid (*exit)(struct crypto_sig *);\n\tstruct crypto_alg base;\n};\n\nstruct sig_instance {\n\tvoid (*free)(struct sig_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[72];\n\t\t\tstruct crypto_instance base;\n\t\t};\n\t\tstruct sig_alg alg;\n\t};\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sigframe_ia32 {\n\tu32 pretcode;\n\tint sig;\n\tstruct sigcontext_32 sc;\n\tstruct _fpstate_32 fpstate_unused;\n\tunsigned int extramask[1];\n\tchar retcode[8];\n};\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {\n\tu64 rchar;\n\tu64 wchar;\n\tu64 syscr;\n\tu64 syscw;\n\tu64 read_bytes;\n\tu64 write_bytes;\n\tu64 cancelled_write_bytes;\n};\n\nstruct taskstats;\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tstruct autogroup *autogroup;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct pacct_struct pacct;\n\tstruct taskstats *stats;\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct sil164_priv {\n\tbool quiet;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct simplefb_platform_data {\n\tu32 width;\n\tu32 height;\n\tu32 stride;\n\tconst char *format;\n};\n\nstruct sioc_sg_req {\n\tstruct in_addr src;\n\tstruct in_addr grp;\n\tlong unsigned int pktcnt;\n\tlong unsigned int bytecnt;\n\tlong unsigned int wrong_if;\n};\n\nstruct sioc_vif_req {\n\tvifi_t vifi;\n\tlong unsigned int icount;\n\tlong unsigned int ocount;\n\tlong unsigned int ibytes;\n\tlong unsigned int obytes;\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*export)(struct skcipher_request *, void *);\n\tint (*import)(struct skcipher_request *, const void *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int walksize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int min_keysize;\n\t\t\tunsigned int max_keysize;\n\t\t\tunsigned int ivsize;\n\t\t\tunsigned int chunksize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct skcipher_alg_common co;\n\t};\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[88];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int nbytes;\n\tunsigned int total;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct skl_dpll_regs {\n\ti915_reg_t ctl;\n\ti915_reg_t cfgcr1;\n\ti915_reg_t cfgcr2;\n};\n\nstruct skl_hw_state {\n\tstruct skl_ddb_entry ddb[8];\n\tstruct skl_ddb_entry ddb_y[8];\n\tu16 min_ddb[8];\n\tu16 interim_ddb[8];\n\tstruct skl_pipe_wm wm;\n};\n\nstruct skl_plane_ddb_iter {\n\tu64 data_rate;\n\tu16 start;\n\tu16 size;\n};\n\nstruct skl_prefill_ctx {\n\tstruct {\n\t\tunsigned int fixed;\n\t\tunsigned int wm0;\n\t\tunsigned int scaler_1st;\n\t\tunsigned int scaler_2nd;\n\t\tunsigned int dsc;\n\t\tunsigned int full;\n\t} prefill;\n\tstruct {\n\t\tunsigned int cdclk;\n\t\tunsigned int scaler_1st;\n\t\tunsigned int scaler_2nd;\n\t} adj;\n};\n\nstruct skl_wm_params {\n\tbool x_tiled;\n\tbool y_tiled;\n\tbool rc_surface;\n\tbool is_planar;\n\tu32 width;\n\tu8 cpp;\n\tu32 plane_pixel_rate;\n\tu32 y_min_scanlines;\n\tu32 plane_bytes_per_line;\n\tuint_fixed_16_16_t plane_blocks_per_line;\n\tuint_fixed_16_16_t y_tile_minimum;\n\tu32 linetime_us;\n\tu32 dbuf_block_size;\n};\n\nstruct skl_wrpll_context {\n\tu64 min_deviation;\n\tu64 central_freq;\n\tu64 dco_freq;\n\tunsigned int p;\n};\n\nstruct sku_microcode {\n\tu32 vfm;\n\tu8 stepping;\n\tu32 microcode;\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong: 64;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct slot_rmap_walk_iterator {\n\tconst struct kvm_memory_slot *slot;\n\tgfn_t start_gfn;\n\tgfn_t end_gfn;\n\tint start_level;\n\tint end_level;\n\tgfn_t gfn;\n\tstruct kvm_rmap_head *rmap;\n\tint level;\n\tstruct kvm_rmap_head *end_rmap;\n};\n\nstruct slpc_override_params {\n\tu32 bits[8];\n\tu32 values[256];\n};\n\nstruct slpc_shared_data_header {\n\tu32 size;\n\tu32 global_state;\n\tu32 display_data_addr;\n};\n\nstruct slpc_task_state_data {\n\tunion {\n\t\tu32 task_status_padding;\n\t\tstruct {\n\t\t\tu32 status;\n\t\t};\n\t};\n\tunion {\n\t\tu32 freq_padding;\n\t\tstruct {\n\t\t\tu32 freq;\n\t\t};\n\t};\n};\n\nstruct slpc_shared_data {\n\tstruct slpc_shared_data_header header;\n\tu8 shared_data_header_pad[52];\n\tu8 platform_info_pad[64];\n\tstruct slpc_task_state_data task_state_data;\n\tu8 task_state_data_pad[56];\n\tstruct slpc_override_params override_params;\n\tu8 override_params_pad[32];\n\tu8 shared_data_pad[2816];\n\tu8 reserved_mode_definition[4096];\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct smca_hwid;\n\nstruct smca_bank {\n\tconst struct smca_hwid *hwid;\n\tu32 id;\n\tu8 sysfs_id;\n\tu64 paddrv: 1;\n\tlong: 23;\n\tu64 __reserved: 63;\n};\n\nstruct smca_hwid {\n\tunsigned int bank_type;\n\tu32 hwid_mcatype;\n};\n\nstruct smp_alt_module {\n\tstruct module *mod;\n\tchar *name;\n\tconst s32 *locks;\n\tconst s32 *locks_end;\n\tu8 *text;\n\tu8 *text_end;\n\tstruct list_head next;\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smp_ops {\n\tvoid (*smp_prepare_boot_cpu)(void);\n\tvoid (*smp_prepare_cpus)(unsigned int);\n\tvoid (*smp_cpus_done)(unsigned int);\n\tvoid (*stop_other_cpus)(int);\n\tvoid (*crash_stop_other_cpus)(void);\n\tvoid (*smp_send_reschedule)(int);\n\tvoid (*cleanup_dead_cpu)(unsigned int);\n\tvoid (*poll_sync_state)(void);\n\tint (*kick_ap_alive)(unsigned int, struct task_struct *);\n\tint (*cpu_disable)(void);\n\tvoid (*cpu_die)(unsigned int);\n\tvoid (*play_dead)(void);\n\tvoid (*stop_this_cpu)(void);\n\tvoid (*send_call_func_ipi)(const struct cpumask *);\n\tvoid (*send_call_func_single_ipi)(int);\n};\n\nstruct smp_text_poke_loc {\n\ts32 rel_addr;\n\ts32 disp;\n\tu8 len;\n\tu8 opcode;\n\tconst u8 text[5];\n\tu8 old;\n};\n\nstruct smp_text_poke_array {\n\tstruct smp_text_poke_loc vec[256];\n\tint nr_entries;\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct snapshot_handle {\n\tunsigned int cur;\n\tvoid *buffer;\n\tint sync_read;\n};\n\nstruct snapshot_data {\n\tstruct snapshot_handle handle;\n\tint swap;\n\tint mode;\n\tbool frozen;\n\tbool ready;\n\tbool platform_support;\n\tbool free_bitmaps;\n\tdev_t dev;\n};\n\nstruct snd_ac97_gpio_priv;\n\nstruct snd_ac97_build_ops;\n\nstruct snd_info_entry;\n\nstruct snd_ac97_res_table;\n\nstruct snd_pcm_chmap;\n\nstruct snd_ac97 {\n\tconst struct snd_ac97_build_ops *build_ops;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_ac97 *);\n\tstruct snd_ac97_bus *bus;\n\tstruct pci_dev *pci;\n\tstruct snd_info_entry *proc;\n\tstruct snd_info_entry *proc_regs;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tstruct mutex reg_mutex;\n\tstruct mutex page_mutex;\n\tshort unsigned int num;\n\tshort unsigned int addr;\n\tunsigned int id;\n\tshort unsigned int caps;\n\tshort unsigned int ext_id;\n\tshort unsigned int ext_mid;\n\tconst struct snd_ac97_res_table *res_table;\n\tunsigned int scaps;\n\tunsigned int flags;\n\tunsigned int rates[6];\n\tunsigned int spdif_status;\n\tshort unsigned int regs[128];\n\tlong unsigned int reg_accessed[2];\n\tunion {\n\t\tstruct {\n\t\t\tshort unsigned int unchained[3];\n\t\t\tshort unsigned int chained[3];\n\t\t\tshort unsigned int id[3];\n\t\t\tshort unsigned int pcmreg[3];\n\t\t\tshort unsigned int codec_cfg[3];\n\t\t\tunsigned char swap_mic_linein;\n\t\t\tunsigned char lo_as_master;\n\t\t} ad18xx;\n\t\tunsigned int dev_flags;\n\t} spec;\n\tunsigned char indep_surround;\n\tunsigned char channel_mode;\n\tstruct device dev;\n\tstruct snd_ac97_gpio_priv *gpio_priv;\n\tstruct snd_pcm_chmap *chmaps[2];\n};\n\nstruct snd_ac97_build_ops {\n\tint (*build_3d)(struct snd_ac97 *);\n\tint (*build_specific)(struct snd_ac97 *);\n\tint (*build_spdif)(struct snd_ac97 *);\n\tint (*build_post_spdif)(struct snd_ac97 *);\n\tvoid (*suspend)(struct snd_ac97 *);\n\tvoid (*resume)(struct snd_ac97 *);\n\tvoid (*update_jacks)(struct snd_ac97 *);\n};\n\nstruct snd_ac97_bus_ops;\n\nstruct snd_ac97_bus {\n\tconst struct snd_ac97_bus_ops *ops;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_ac97_bus *);\n\tstruct snd_card *card;\n\tshort unsigned int num;\n\tshort unsigned int no_vra: 1;\n\tshort unsigned int dra: 1;\n\tshort unsigned int isdin: 1;\n\tunsigned int clock;\n\tspinlock_t bus_lock;\n\tshort unsigned int used_slots[8];\n\tshort unsigned int pcms_count;\n\tstruct ac97_pcm *pcms;\n\tstruct snd_ac97 *codec[4];\n\tstruct snd_info_entry *proc;\n};\n\nstruct snd_ac97_bus_ops {\n\tvoid (*reset)(struct snd_ac97 *);\n\tvoid (*warm_reset)(struct snd_ac97 *);\n\tvoid (*write)(struct snd_ac97 *, short unsigned int, short unsigned int);\n\tshort unsigned int (*read)(struct snd_ac97 *, short unsigned int);\n\tvoid (*wait)(struct snd_ac97 *);\n\tvoid (*init)(struct snd_ac97 *);\n};\n\nstruct snd_ac97_res_table {\n\tshort unsigned int reg;\n\tshort unsigned int bits;\n};\n\nstruct snd_ac97_template {\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_ac97 *);\n\tstruct pci_dev *pci;\n\tshort unsigned int num;\n\tshort unsigned int addr;\n\tunsigned int scaps;\n\tconst struct snd_ac97_res_table *res_table;\n};\n\nstruct snd_aes_iec958 {\n\tunsigned char status[24];\n\tunsigned char subcode[147];\n\tunsigned char pad;\n\tunsigned char dig_subframe[4];\n};\n\nstruct snd_shutdown_f_ops;\n\nstruct snd_card {\n\tint number;\n\tchar id[16];\n\tchar driver[16];\n\tchar shortname[32];\n\tchar longname[80];\n\tchar irq_descr[32];\n\tchar mixername[80];\n\tchar components[128];\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_card *);\n\tstruct list_head devices;\n\tstruct device *ctl_dev;\n\tunsigned int last_numid;\n\tstruct rw_semaphore controls_rwsem;\n\trwlock_t controls_rwlock;\n\tint controls_count;\n\tsize_t user_ctl_alloc_size;\n\tstruct list_head controls;\n\tstruct list_head ctl_files;\n\tstruct xarray ctl_numids;\n\tstruct xarray ctl_hash;\n\tbool ctl_hash_collision;\n\tstruct snd_info_entry *proc_root;\n\tstruct proc_dir_entry *proc_root_link;\n\tstruct list_head files_list;\n\tstruct snd_shutdown_f_ops *s_f_ops;\n\tspinlock_t files_lock;\n\tint shutdown;\n\tstruct completion *release_completion;\n\tstruct device *dev;\n\tstruct device card_dev;\n\tconst struct attribute_group *dev_groups[4];\n\tbool registered;\n\tbool managed;\n\tbool releasing;\n\tint sync_irq;\n\twait_queue_head_t remove_sleep;\n\tsize_t total_pcm_alloc_bytes;\n\tstruct mutex memory_mutex;\n\tunsigned int power_state;\n\tatomic_t power_ref;\n\twait_queue_head_t power_sleep;\n\twait_queue_head_t power_ref_sleep;\n};\n\nstruct snd_enc_wma {\n\t__u32 super_block_align;\n};\n\nstruct snd_enc_vorbis {\n\t__s32 quality;\n\t__u32 managed;\n\t__u32 max_bit_rate;\n\t__u32 min_bit_rate;\n\t__u32 downmix;\n};\n\nstruct snd_enc_real {\n\t__u32 quant_bits;\n\t__u32 start_region;\n\t__u32 num_regions;\n};\n\nstruct snd_enc_flac {\n\t__u32 num;\n\t__u32 gain;\n};\n\nstruct snd_enc_generic {\n\t__u32 bw;\n\t__s32 reserved[15];\n};\n\nstruct snd_dec_flac {\n\t__u16 sample_size;\n\t__u16 min_blk_size;\n\t__u16 max_blk_size;\n\t__u16 min_frame_size;\n\t__u16 max_frame_size;\n\t__u16 reserved;\n};\n\nstruct snd_dec_wma {\n\t__u32 encoder_option;\n\t__u32 adv_encoder_option;\n\t__u32 adv_encoder_option2;\n\t__u32 reserved;\n};\n\nstruct snd_dec_alac {\n\t__u32 frame_length;\n\t__u8 compatible_version;\n\t__u8 pb;\n\t__u8 mb;\n\t__u8 kb;\n\t__u32 max_run;\n\t__u32 max_frame_bytes;\n};\n\nstruct snd_dec_ape {\n\t__u16 compatible_version;\n\t__u16 compression_level;\n\t__u32 format_flags;\n\t__u32 blocks_per_frame;\n\t__u32 final_frame_blocks;\n\t__u32 total_frames;\n\t__u32 seek_table_present;\n};\n\nstruct snd_dec_opus_ch_map {\n\t__u8 stream_count;\n\t__u8 coupled_count;\n\t__u8 channel_map[8];\n};\n\nstruct snd_dec_opus {\n\t__u8 version;\n\t__u8 num_channels;\n\t__u16 pre_skip;\n\t__u32 sample_rate;\n\t__u16 output_gain;\n\t__u8 mapping_family;\n\tstruct snd_dec_opus_ch_map chan_map;\n};\n\nunion snd_codec_options {\n\tstruct snd_enc_wma wma;\n\tstruct snd_enc_vorbis vorbis;\n\tstruct snd_enc_real real;\n\tstruct snd_enc_flac flac;\n\tstruct snd_enc_generic generic;\n\tstruct snd_dec_flac flac_d;\n\tstruct snd_dec_wma wma_d;\n\tstruct snd_dec_alac alac_d;\n\tstruct snd_dec_ape ape_d;\n\tstruct snd_dec_opus opus_d;\n\tstruct {\n\t\t__u32 out_sample_rate;\n\t} src_d;\n};\n\nstruct snd_codec {\n\t__u32 id;\n\t__u32 ch_in;\n\t__u32 ch_out;\n\t__u32 sample_rate;\n\t__u32 bit_rate;\n\t__u32 rate_control;\n\t__u32 profile;\n\t__u32 level;\n\t__u32 ch_mode;\n\t__u32 format;\n\t__u32 align;\n\tunion snd_codec_options options;\n\t__u32 pcm_format;\n\t__u32 reserved[2];\n};\n\nstruct snd_codec_desc_src {\n\t__u32 out_sample_rate_min;\n\t__u32 out_sample_rate_max;\n};\n\nstruct snd_codec_desc {\n\t__u32 max_ch;\n\t__u32 sample_rates[32];\n\t__u32 num_sample_rates;\n\t__u32 bit_rate[32];\n\t__u32 num_bitrates;\n\t__u32 rate_control;\n\t__u32 profiles;\n\t__u32 modes;\n\t__u32 formats;\n\t__u32 min_buffer;\n\t__u32 pcm_formats;\n\tunion {\n\t\t__u32 u_space[6];\n\t\tstruct snd_codec_desc_src src;\n\t};\n\t__u32 reserved[8];\n};\n\nstruct snd_compr_ops;\n\nstruct snd_compr {\n\tconst char *name;\n\tstruct device *dev;\n\tstruct snd_compr_ops *ops;\n\tvoid *private_data;\n\tstruct snd_card *card;\n\tunsigned int direction;\n\tstruct mutex lock;\n\tint device;\n\tbool use_pause_in_draining;\n\tchar id[64];\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_info_entry *proc_info_entry;\n};\n\nstruct snd_compr_caps {\n\t__u32 num_codecs;\n\t__u32 direction;\n\t__u32 min_fragment_size;\n\t__u32 max_fragment_size;\n\t__u32 min_fragments;\n\t__u32 max_fragments;\n\t__u32 codecs[32];\n\t__u32 reserved[11];\n};\n\nstruct snd_compr_codec_caps {\n\t__u32 codec;\n\t__u32 num_descriptors;\n\tstruct snd_codec_desc descriptor[32];\n};\n\nstruct snd_compr_metadata {\n\t__u32 key;\n\t__u32 value[8];\n};\n\nstruct snd_compr_params;\n\nstruct snd_compr_tstamp64;\n\nstruct snd_compr_ops {\n\tint (*open)(struct snd_compr_stream *);\n\tint (*free)(struct snd_compr_stream *);\n\tint (*set_params)(struct snd_compr_stream *, struct snd_compr_params *);\n\tint (*get_params)(struct snd_compr_stream *, struct snd_codec *);\n\tint (*set_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*get_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*trigger)(struct snd_compr_stream *, int);\n\tint (*pointer)(struct snd_compr_stream *, struct snd_compr_tstamp64 *);\n\tint (*copy)(struct snd_compr_stream *, char *, size_t);\n\tint (*mmap)(struct snd_compr_stream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_compr_stream *, size_t);\n\tint (*get_caps)(struct snd_compr_stream *, struct snd_compr_caps *);\n\tint (*get_codec_caps)(struct snd_compr_stream *, struct snd_compr_codec_caps *);\n};\n\nstruct snd_compressed_buffer {\n\t__u32 fragment_size;\n\t__u32 fragments;\n};\n\nstruct snd_compr_params {\n\tstruct snd_compressed_buffer buffer;\n\tstruct snd_codec codec;\n\t__u8 no_wake_mode;\n};\n\nstruct snd_compr_runtime {\n\tsnd_pcm_state_t state;\n\tstruct snd_compr_ops *ops;\n\tvoid *buffer;\n\tu64 buffer_size;\n\tu32 fragment_size;\n\tu32 fragments;\n\tu64 total_bytes_available;\n\tu64 total_bytes_transferred;\n\twait_queue_head_t sleep;\n\tvoid *private_data;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n};\n\nstruct snd_compr_stream {\n\tconst char *name;\n\tstruct snd_compr_ops *ops;\n\tstruct snd_compr_runtime *runtime;\n\tstruct snd_compr *device;\n\tstruct delayed_work error_work;\n\tenum snd_compr_direction direction;\n\tbool metadata_set;\n\tbool next_track;\n\tbool partial_drain;\n\tbool pause_in_draining;\n\tvoid *private_data;\n\tstruct snd_dma_buffer dma_buffer;\n};\n\nstruct snd_compr_tstamp64 {\n\t__u32 byte_offset;\n\t__u64 copied_total;\n\t__u64 pcm_frames;\n\t__u64 pcm_io_frames;\n\t__u32 sampling_rate;\n} __attribute__((packed));\n\nstruct snd_ctl_card_info {\n\tint card;\n\tint pad;\n\tunsigned char id[16];\n\tunsigned char driver[16];\n\tunsigned char name[32];\n\tunsigned char longname[80];\n\tunsigned char reserved_[16];\n\tunsigned char mixername[80];\n\tunsigned char components[128];\n};\n\nstruct snd_ctl_elem_info {\n\tstruct snd_ctl_elem_id id;\n\tsnd_ctl_elem_type_t type;\n\tunsigned int access;\n\tunsigned int count;\n\t__kernel_pid_t owner;\n\tunion {\n\t\tstruct {\n\t\t\tlong int min;\n\t\t\tlong int max;\n\t\t\tlong int step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tlong long int min;\n\t\t\tlong long int max;\n\t\t\tlong long int step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tunsigned int items;\n\t\t\tunsigned int item;\n\t\t\tchar name[64];\n\t\t\t__u64 names_ptr;\n\t\t\tunsigned int names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_info32 {\n\tstruct snd_ctl_elem_id id;\n\ts32 type;\n\tu32 access;\n\tu32 count;\n\ts32 owner;\n\tunion {\n\t\tstruct {\n\t\t\ts32 min;\n\t\t\ts32 max;\n\t\t\ts32 step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tu64 min;\n\t\t\tu64 max;\n\t\t\tu64 step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tu32 items;\n\t\t\tu32 item;\n\t\t\tchar name[64];\n\t\t\tu64 names_ptr;\n\t\t\tu32 names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_list {\n\tunsigned int offset;\n\tunsigned int space;\n\tunsigned int used;\n\tunsigned int count;\n\tstruct snd_ctl_elem_id *pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_list32 {\n\tu32 offset;\n\tu32 space;\n\tu32 used;\n\tu32 count;\n\tu32 pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_value {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect: 1;\n\tunion {\n\t\tunion {\n\t\t\tlong int value[128];\n\t\t\tlong int *value_ptr;\n\t\t} integer;\n\t\tunion {\n\t\t\tlong long int value[64];\n\t\t\tlong long int *value_ptr;\n\t\t} integer64;\n\t\tunion {\n\t\t\tunsigned int item[128];\n\t\t\tunsigned int *item_ptr;\n\t\t} enumerated;\n\t\tunion {\n\t\t\tunsigned char data[512];\n\t\t\tunsigned char *data_ptr;\n\t\t} bytes;\n\t\tstruct snd_aes_iec958 iec958;\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_ctl_elem_value32 {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect;\n\tunion {\n\t\ts32 integer[128];\n\t\tunsigned char data[512];\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_ctl_event {\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int mask;\n\t\t\tstruct snd_ctl_elem_id id;\n\t\t} elem;\n\t\tunsigned char data8[60];\n\t} data;\n};\n\nstruct snd_fasync;\n\nstruct snd_ctl_file {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tstruct pid *pid;\n\tint preferred_subdevice[2];\n\twait_queue_head_t change_sleep;\n\tspinlock_t read_lock;\n\tstruct snd_fasync *fasync;\n\tint subscribed;\n\tstruct list_head events;\n};\n\nstruct snd_ctl_layer_ops {\n\tstruct snd_ctl_layer_ops *next;\n\tconst char *module_name;\n\tvoid (*lregister)(struct snd_card *);\n\tvoid (*ldisconnect)(struct snd_card *);\n\tvoid (*lnotify)(struct snd_card *, unsigned int, struct snd_kcontrol *, unsigned int);\n};\n\nstruct snd_ctl_led_card;\n\nstruct snd_ctl_led {\n\tstruct device dev;\n\tstruct list_head controls;\n\tconst char *name;\n\tunsigned int group;\n\tenum led_audio trigger_type;\n\tenum snd_ctl_led_mode mode;\n\tstruct snd_ctl_led_card *cards[8];\n};\n\nstruct snd_ctl_led_card {\n\tstruct device dev;\n\tint number;\n\tstruct snd_ctl_led *led;\n};\n\nstruct snd_ctl_led_ctl {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tunsigned int access;\n\tstruct snd_kcontrol *kctl;\n\tunsigned int index_offset;\n};\n\nstruct snd_ctl_tlv {\n\tunsigned int numid;\n\tunsigned int length;\n\tunsigned int tlv[0];\n};\n\nstruct snd_device_ops;\n\nstruct snd_device {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tenum snd_device_state state;\n\tenum snd_device_type type;\n\tvoid *device_data;\n\tconst struct snd_device_ops *ops;\n};\n\nstruct snd_device_ops {\n\tint (*dev_free)(struct snd_device *);\n\tint (*dev_register)(struct snd_device *);\n\tint (*dev_disconnect)(struct snd_device *);\n};\n\nstruct snd_dma_data {\n\tint dma;\n};\n\nstruct snd_dma_sg_fallback {\n\tstruct sg_table sgt;\n\tsize_t count;\n\tstruct page **pages;\n\tunsigned int *npages;\n};\n\nstruct snd_fasync {\n\tstruct fasync_struct *fasync;\n\tint signal;\n\tint poll;\n\tint on;\n\tstruct list_head list;\n};\n\nstruct snd_hda_pin_quirk {\n\tunsigned int codec;\n\tshort unsigned int subvendor;\n\tconst struct hda_pintbl *pins;\n\tint value;\n};\n\nstruct snd_timer;\n\nstruct snd_hrtimer {\n\tstruct snd_timer *timer;\n\tstruct hrtimer hrt;\n\tbool in_callback;\n};\n\nstruct snd_hwdep_dsp_status;\n\nstruct snd_hwdep_dsp_image;\n\nstruct snd_hwdep_ops {\n\tlong long int (*llseek)(struct snd_hwdep *, struct file *, long long int, int);\n\tlong int (*read)(struct snd_hwdep *, char *, long int, loff_t *);\n\tlong int (*write)(struct snd_hwdep *, const char *, long int, loff_t *);\n\tint (*open)(struct snd_hwdep *, struct file *);\n\tint (*release)(struct snd_hwdep *, struct file *);\n\t__poll_t (*poll)(struct snd_hwdep *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_hwdep *, struct file *, unsigned int, long unsigned int);\n\tint (*ioctl_compat)(struct snd_hwdep *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_hwdep *, struct file *, struct vm_area_struct *);\n\tint (*dsp_status)(struct snd_hwdep *, struct snd_hwdep_dsp_status *);\n\tint (*dsp_load)(struct snd_hwdep *, struct snd_hwdep_dsp_image *);\n};\n\nstruct snd_hwdep {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tchar id[32];\n\tchar name[80];\n\tint iface;\n\tstruct snd_hwdep_ops ops;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_hwdep *);\n\tstruct device *dev;\n\tstruct mutex open_mutex;\n\tint used;\n\tunsigned int dsp_loaded;\n\tunsigned int exclusive: 1;\n};\n\nstruct snd_hwdep_dsp_image {\n\tunsigned int index;\n\tunsigned char name[64];\n\tunsigned char *image;\n\tsize_t length;\n\tlong unsigned int driver_data;\n};\n\nstruct snd_hwdep_dsp_image32 {\n\tu32 index;\n\tunsigned char name[64];\n\tu32 image;\n\tu32 length;\n\tu32 driver_data;\n};\n\nstruct snd_hwdep_dsp_status {\n\tunsigned int version;\n\tunsigned char id[32];\n\tunsigned int num_dsps;\n\tunsigned int dsp_loaded;\n\tunsigned int chip_ready;\n\tunsigned char reserved[16];\n};\n\nstruct snd_hwdep_info {\n\tunsigned int device;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tint iface;\n\tunsigned char reserved[64];\n};\n\nstruct snd_info_buffer {\n\tchar *buffer;\n\tunsigned int curr;\n\tunsigned int size;\n\tunsigned int len;\n\tint stop;\n\tint error;\n};\n\nstruct snd_info_entry_text {\n\tvoid (*read)(struct snd_info_entry *, struct snd_info_buffer *);\n\tvoid (*write)(struct snd_info_entry *, struct snd_info_buffer *);\n};\n\nstruct snd_info_entry_ops;\n\nstruct snd_info_entry {\n\tconst char *name;\n\tumode_t mode;\n\tlong int size;\n\tshort unsigned int content;\n\tunion {\n\t\tstruct snd_info_entry_text text;\n\t\tconst struct snd_info_entry_ops *ops;\n\t} c;\n\tstruct snd_info_entry *parent;\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_info_entry *);\n\tstruct proc_dir_entry *p;\n\tstruct mutex access;\n\tstruct list_head children;\n\tstruct list_head list;\n};\n\nstruct snd_info_entry_ops {\n\tint (*open)(struct snd_info_entry *, short unsigned int, void **);\n\tint (*release)(struct snd_info_entry *, short unsigned int, void *);\n\tssize_t (*read)(struct snd_info_entry *, void *, struct file *, char *, size_t, loff_t);\n\tssize_t (*write)(struct snd_info_entry *, void *, struct file *, const char *, size_t, loff_t);\n\tloff_t (*llseek)(struct snd_info_entry *, void *, struct file *, loff_t, int);\n\t__poll_t (*poll)(struct snd_info_entry *, void *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_info_entry *, void *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_info_entry *, void *, struct inode *, struct file *, struct vm_area_struct *);\n};\n\nstruct snd_info_private_data {\n\tstruct snd_info_buffer *rbuffer;\n\tstruct snd_info_buffer *wbuffer;\n\tstruct snd_info_entry *entry;\n\tvoid *file_private_data;\n};\n\nstruct snd_interval {\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int openmin: 1;\n\tunsigned int openmax: 1;\n\tunsigned int integer: 1;\n\tunsigned int empty: 1;\n};\n\nstruct snd_jack {\n\tstruct list_head kctl_list;\n\tstruct snd_card *card;\n\tconst char *id;\n\tstruct input_dev *input_dev;\n\tstruct mutex input_dev_lock;\n\tint registered;\n\tint type;\n\tchar name[100];\n\tunsigned int key[6];\n\tint hw_status_cache;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_jack *);\n};\n\nstruct snd_jack_kctl {\n\tstruct snd_kcontrol *kctl;\n\tstruct list_head list;\n\tunsigned int mask_bits;\n\tstruct snd_jack *jack;\n\tbool sw_inject_enable;\n};\n\nstruct snd_kcontrol_new {\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tconst char *name;\n\tunsigned int index;\n\tunsigned int access;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n};\n\nstruct snd_kctl_event {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int mask;\n};\n\ntypedef int (*snd_kctl_ioctl_func_t)(struct snd_card *, struct snd_ctl_file *, unsigned int, long unsigned int);\n\nstruct snd_kctl_ioctl {\n\tstruct list_head list;\n\tsnd_kctl_ioctl_func_t fioctl;\n};\n\nstruct snd_malloc_ops {\n\tvoid * (*alloc)(struct snd_dma_buffer *, size_t);\n\tvoid (*free)(struct snd_dma_buffer *);\n\tdma_addr_t (*get_addr)(struct snd_dma_buffer *, size_t);\n\tstruct page * (*get_page)(struct snd_dma_buffer *, size_t);\n\tunsigned int (*get_chunk_size)(struct snd_dma_buffer *, unsigned int, unsigned int);\n\tint (*mmap)(struct snd_dma_buffer *, struct vm_area_struct *);\n\tvoid (*sync)(struct snd_dma_buffer *, enum snd_dma_sync_mode);\n};\n\nstruct snd_mask {\n\t__u32 bits[8];\n};\n\nstruct snd_minor {\n\tint type;\n\tint card;\n\tint device;\n\tconst struct file_operations *f_ops;\n\tvoid *private_data;\n\tstruct device *dev;\n\tstruct snd_card *card_ptr;\n};\n\nstruct snd_monitor_file {\n\tstruct file *file;\n\tconst struct file_operations *disconnected_f_op;\n\tstruct list_head shutdown_list;\n\tstruct list_head list;\n};\n\nstruct snd_pci_quirk {\n\tshort unsigned int subvendor;\n\tshort unsigned int subdevice;\n\tshort unsigned int subdevice_mask;\n\tint value;\n};\n\nstruct snd_pcm_str {\n\tint stream;\n\tstruct snd_pcm *pcm;\n\tunsigned int substream_count;\n\tunsigned int substream_opened;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_kcontrol *chmap_kctl;\n\tstruct device *dev;\n};\n\nstruct snd_pcm {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tunsigned int info_flags;\n\tshort unsigned int dev_class;\n\tshort unsigned int dev_subclass;\n\tchar id[64];\n\tchar name[80];\n\tstruct snd_pcm_str streams[2];\n\tstruct mutex open_mutex;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm *);\n\tbool internal;\n\tbool nonatomic;\n\tbool no_device_suspend;\n};\n\nstruct snd_pcm_audio_tstamp_config {\n\tu32 type_requested: 4;\n\tu32 report_delay: 1;\n};\n\nstruct snd_pcm_audio_tstamp_report {\n\tu32 valid: 1;\n\tu32 actual_type: 4;\n\tu32 accuracy_report: 1;\n\tu32 accuracy;\n};\n\nstruct snd_pcm_channel_info {\n\tunsigned int channel;\n\t__kernel_off_t offset;\n\tunsigned int first;\n\tunsigned int step;\n};\n\nstruct snd_pcm_channel_info32 {\n\tu32 channel;\n\tu32 offset;\n\tu32 first;\n\tu32 step;\n};\n\nstruct snd_pcm_chmap {\n\tstruct snd_pcm *pcm;\n\tint stream;\n\tstruct snd_kcontrol *kctl;\n\tconst struct snd_pcm_chmap_elem *chmap;\n\tunsigned int max_channels;\n\tunsigned int channel_mask;\n\tvoid *private_data;\n};\n\nstruct snd_pcm_chmap_elem {\n\tunsigned char channels;\n\tunsigned char map[15];\n};\n\nstruct snd_pcm_file {\n\tstruct snd_pcm_substream *substream;\n\tint no_compat_mmap;\n\tunsigned int user_pversion;\n};\n\nstruct snd_pcm_group {\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head substreams;\n\trefcount_t refs;\n};\n\nstruct snd_pcm_hardware {\n\tunsigned int info;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int rates;\n\tunsigned int rate_min;\n\tunsigned int rate_max;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\tsize_t buffer_bytes_max;\n\tsize_t period_bytes_min;\n\tsize_t period_bytes_max;\n\tunsigned int periods_min;\n\tunsigned int periods_max;\n\tsize_t fifo_size;\n};\n\nstruct snd_pcm_hw_constraint_list {\n\tconst unsigned int *list;\n\tunsigned int count;\n\tunsigned int mask;\n};\n\nstruct snd_pcm_hw_constraint_ranges {\n\tunsigned int count;\n\tconst struct snd_interval *ranges;\n\tunsigned int mask;\n};\n\nstruct snd_ratden;\n\nstruct snd_pcm_hw_constraint_ratdens {\n\tint nrats;\n\tconst struct snd_ratden *rats;\n};\n\nstruct snd_ratnum;\n\nstruct snd_pcm_hw_constraint_ratnums {\n\tint nrats;\n\tconst struct snd_ratnum *rats;\n};\n\nstruct snd_pcm_hw_rule;\n\nstruct snd_pcm_hw_constraints {\n\tstruct snd_mask masks[3];\n\tstruct snd_interval intervals[12];\n\tunsigned int rules_num;\n\tunsigned int rules_all;\n\tstruct snd_pcm_hw_rule *rules;\n};\n\nstruct snd_pcm_hw_params {\n\tunsigned int flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tunsigned int rmask;\n\tunsigned int cmask;\n\tunsigned int info;\n\tunsigned int msbits;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tsnd_pcm_uframes_t fifo_size;\n\tunsigned char sync[16];\n\tunsigned char reserved[48];\n};\n\nstruct snd_pcm_hw_params32 {\n\tu32 flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tu32 rmask;\n\tu32 cmask;\n\tu32 info;\n\tu32 msbits;\n\tu32 rate_num;\n\tu32 rate_den;\n\tu32 fifo_size;\n\tunsigned char reserved[64];\n};\n\ntypedef int (*snd_pcm_hw_rule_func_t)(struct snd_pcm_hw_params *, struct snd_pcm_hw_rule *);\n\nstruct snd_pcm_hw_rule {\n\tunsigned int cond;\n\tint var;\n\tint deps[5];\n\tsnd_pcm_hw_rule_func_t func;\n\tvoid *private;\n};\n\nstruct snd_pcm_info {\n\tunsigned int device;\n\tunsigned int subdevice;\n\tint stream;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tunsigned char subname[32];\n\tint dev_class;\n\tint dev_subclass;\n\tunsigned int subdevices_count;\n\tunsigned int subdevices_avail;\n\tunsigned char pad1[16];\n\tunsigned char reserved[64];\n};\n\nstruct snd_pcm_mmap_control {\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t appl_ptr;\n\t__pad_before_uframe __pad2;\n\t__pad_before_uframe __pad3;\n\tsnd_pcm_uframes_t avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct snd_pcm_mmap_control32 {\n\tu32 appl_ptr;\n\tu32 avail_min;\n};\n\nstruct snd_pcm_mmap_status {\n\tsnd_pcm_state_t state;\n\t__u32 pad1;\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t hw_ptr;\n\t__pad_after_uframe __pad2;\n\tstruct __kernel_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 pad3;\n\tstruct __kernel_timespec audio_tstamp;\n};\n\nstruct snd_pcm_mmap_status32 {\n\tsnd_pcm_state_t state;\n\ts32 pad1;\n\tu32 hw_ptr;\n\tstruct __snd_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\tstruct __snd_timespec audio_tstamp;\n};\n\nstruct snd_pcm_ops {\n\tint (*open)(struct snd_pcm_substream *);\n\tint (*close)(struct snd_pcm_substream *);\n\tint (*ioctl)(struct snd_pcm_substream *, unsigned int, void *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_pcm_substream *, int);\n\tint (*sync_stop)(struct snd_pcm_substream *);\n\tsnd_pcm_uframes_t (*pointer)(struct snd_pcm_substream *);\n\tint (*get_time_info)(struct snd_pcm_substream *, struct timespec64 *, struct timespec64 *, struct snd_pcm_audio_tstamp_config *, struct snd_pcm_audio_tstamp_report *);\n\tint (*fill_silence)(struct snd_pcm_substream *, int, long unsigned int, long unsigned int);\n\tint (*copy)(struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\tstruct page * (*page)(struct snd_pcm_substream *, long unsigned int);\n\tint (*mmap)(struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_pcm_substream *);\n};\n\nstruct snd_pcm_runtime {\n\tsnd_pcm_state_t state;\n\tsnd_pcm_state_t suspended_state;\n\tstruct snd_pcm_substream *trigger_master;\n\tstruct timespec64 trigger_tstamp;\n\tbool trigger_tstamp_latched;\n\tint overrange;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t hw_ptr_base;\n\tsnd_pcm_uframes_t hw_ptr_interrupt;\n\tlong unsigned int hw_ptr_jiffies;\n\tlong unsigned int hw_ptr_buffer_jiffies;\n\tsnd_pcm_sframes_t delay;\n\tu64 hw_ptr_wrap;\n\tsnd_pcm_access_t access;\n\tsnd_pcm_format_t format;\n\tsnd_pcm_subformat_t subformat;\n\tunsigned int rate;\n\tunsigned int channels;\n\tsnd_pcm_uframes_t period_size;\n\tunsigned int periods;\n\tsnd_pcm_uframes_t buffer_size;\n\tsnd_pcm_uframes_t min_align;\n\tsize_t byte_align;\n\tunsigned int frame_bits;\n\tunsigned int sample_bits;\n\tunsigned int info;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tunsigned int no_period_wakeup: 1;\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tsnd_pcm_uframes_t silence_start;\n\tsnd_pcm_uframes_t silence_filled;\n\tbool std_sync_id;\n\tstruct snd_pcm_mmap_status *status;\n\tstruct snd_pcm_mmap_control *control;\n\tsnd_pcm_uframes_t twake;\n\twait_queue_head_t sleep;\n\twait_queue_head_t tsleep;\n\tstruct snd_fasync *fasync;\n\tbool stop_operating;\n\tstruct mutex buffer_mutex;\n\tatomic_t buffer_accessing;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm_runtime *);\n\tstruct snd_pcm_hardware hw;\n\tstruct snd_pcm_hw_constraints hw_constraints;\n\tunsigned int timer_resolution;\n\tint tstamp_type;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n\tunsigned int buffer_changed: 1;\n\tstruct snd_pcm_audio_tstamp_config audio_tstamp_config;\n\tstruct snd_pcm_audio_tstamp_report audio_tstamp_report;\n\tstruct timespec64 driver_tstamp;\n};\n\nstruct snd_pcm_status32 {\n\tsnd_pcm_state_t state;\n\ts32 trigger_tstamp_sec;\n\ts32 trigger_tstamp_nsec;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts32 audio_tstamp_sec;\n\ts32 audio_tstamp_nsec;\n\ts32 driver_tstamp_sec;\n\ts32 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[36];\n};\n\nstruct snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tsnd_pcm_uframes_t appl_ptr;\n\tsnd_pcm_uframes_t hw_ptr;\n\tsnd_pcm_sframes_t delay;\n\tsnd_pcm_uframes_t avail;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t overrange;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\t__u32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nstruct snd_pcm_substream {\n\tstruct snd_pcm *pcm;\n\tstruct snd_pcm_str *pstr;\n\tvoid *private_data;\n\tint number;\n\tchar name[32];\n\tint stream;\n\tstruct pm_qos_request latency_pm_qos_req;\n\tsize_t buffer_bytes_max;\n\tstruct snd_dma_buffer dma_buffer;\n\tsize_t dma_max;\n\tconst struct snd_pcm_ops *ops;\n\tstruct snd_pcm_runtime *runtime;\n\tstruct snd_timer *timer;\n\tunsigned int timer_running: 1;\n\tlong int wait_time;\n\tstruct snd_pcm_substream *next;\n\tstruct list_head link_list;\n\tstruct snd_pcm_group self_group;\n\tstruct snd_pcm_group *group;\n\tint ref_count;\n\tatomic_t mmap_count;\n\tunsigned int f_flags;\n\tvoid (*pcm_release)(struct snd_pcm_substream *);\n\tstruct pid *pid;\n\tstruct snd_info_entry *proc_root;\n\tunsigned int hw_opened: 1;\n\tunsigned int managed_buffer_alloc: 1;\n};\n\nstruct snd_pcm_sw_params {\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tunsigned int sleep_min;\n\tsnd_pcm_uframes_t avail_min;\n\tsnd_pcm_uframes_t xfer_align;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tunsigned int proto;\n\tunsigned int tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_sw_params32 {\n\ts32 tstamp_mode;\n\tu32 period_step;\n\tu32 sleep_min;\n\tu32 avail_min;\n\tu32 xfer_align;\n\tu32 start_threshold;\n\tu32 stop_threshold;\n\tu32 silence_threshold;\n\tu32 silence_size;\n\tu32 boundary;\n\tu32 proto;\n\tu32 tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_sync_ptr {\n\t__u32 flags;\n\t__u32 pad1;\n\tunion {\n\t\tstruct snd_pcm_mmap_status status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_pcm_sync_ptr32 {\n\tu32 flags;\n\tunion {\n\t\tstruct snd_pcm_mmap_status32 status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control32 control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_ratden {\n\tunsigned int num_min;\n\tunsigned int num_max;\n\tunsigned int num_step;\n\tunsigned int den;\n};\n\nstruct snd_ratnum {\n\tunsigned int num;\n\tunsigned int den_min;\n\tunsigned int den_max;\n\tunsigned int den_step;\n};\n\nstruct snd_seq_fifo;\n\nstruct snd_seq_user_client {\n\tstruct file *file;\n\tstruct pid *owner;\n\tstruct snd_seq_fifo *fifo;\n\tint fifo_pool_size;\n};\n\nstruct snd_seq_kernel_client {\n\tstruct snd_card *card;\n};\n\nstruct snd_seq_pool;\n\nstruct snd_seq_client {\n\tsnd_seq_client_type_t type;\n\tunsigned int accept_input: 1;\n\tunsigned int accept_output: 1;\n\tunsigned int midi_version;\n\tunsigned int user_pversion;\n\tchar name[64];\n\tint number;\n\tunsigned int filter;\n\tlong unsigned int event_filter[4];\n\tshort unsigned int group_filter;\n\tsnd_use_lock_t use_lock;\n\tint event_lost;\n\tint num_ports;\n\tstruct list_head ports_list_head;\n\trwlock_t ports_lock;\n\tstruct mutex ports_mutex;\n\tstruct mutex ioctl_mutex;\n\tint convert32;\n\tint ump_endpoint_port;\n\tstruct snd_seq_pool *pool;\n\tunion {\n\t\tstruct snd_seq_user_client user;\n\t\tstruct snd_seq_kernel_client kernel;\n\t} data;\n\tvoid **ump_info;\n};\n\nstruct snd_seq_client_info {\n\tint client;\n\tsnd_seq_client_type_t type;\n\tchar name[64];\n\tunsigned int filter;\n\tunsigned char multicast_filter[8];\n\tunsigned char event_filter[32];\n\tint num_ports;\n\tint event_lost;\n\tint card;\n\tint pid;\n\tunsigned int midi_version;\n\tunsigned int group_filter;\n\tchar reserved[48];\n};\n\nstruct snd_seq_client_pool {\n\tint client;\n\tint output_pool;\n\tint input_pool;\n\tint output_room;\n\tint output_free;\n\tint input_free;\n\tchar reserved[64];\n};\n\nstruct snd_seq_port_subscribe;\n\nstruct snd_seq_port_subs_info {\n\tstruct list_head list_head;\n\tunsigned int count;\n\tunsigned int exclusive: 1;\n\tstruct rw_semaphore list_mutex;\n\trwlock_t list_lock;\n\tint (*open)(void *, struct snd_seq_port_subscribe *);\n\tint (*close)(void *, struct snd_seq_port_subscribe *);\n};\n\nstruct snd_seq_client_port {\n\tstruct snd_seq_addr addr;\n\tstruct module *owner;\n\tchar name[64];\n\tstruct list_head list;\n\tsnd_use_lock_t use_lock;\n\tstruct snd_seq_port_subs_info c_src;\n\tstruct snd_seq_port_subs_info c_dest;\n\tint (*event_input)(struct snd_seq_event *, int, void *, int, int);\n\tvoid (*private_free)(void *);\n\tvoid *private_data;\n\tunsigned int closing: 1;\n\tunsigned int timestamping: 1;\n\tunsigned int time_real: 1;\n\tint time_queue;\n\tunsigned int capability;\n\tunsigned int type;\n\tint midi_channels;\n\tint midi_voices;\n\tint synth_voices;\n\tunsigned char direction;\n\tunsigned char ump_group;\n\tbool is_midi1;\n};\n\nstruct snd_seq_device {\n\tstruct snd_card *card;\n\tint device;\n\tconst char *id;\n\tchar name[80];\n\tint argsize;\n\tvoid *driver_data;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_seq_device *);\n\tstruct device dev;\n};\n\nstruct snd_seq_driver {\n\tint (*probe)(struct snd_seq_device *);\n\tvoid (*remove)(struct snd_seq_device *);\n\tstruct device_driver driver;\n\tchar *id;\n\tint argsize;\n};\n\nstruct snd_seq_dummy_port {\n\tint client;\n\tint port;\n\tint duplex;\n\tint connect;\n};\n\nstruct snd_seq_event_cell {\n\tunion {\n\t\tstruct snd_seq_event event;\n\t\tunion __snd_seq_event ump;\n\t};\n\tstruct snd_seq_pool *pool;\n\tstruct snd_seq_event_cell *next;\n};\n\ntypedef struct snd_seq_fifo *class_snd_seq_fifo_t;\n\nstruct snd_seq_fifo {\n\tstruct snd_seq_pool *pool;\n\tstruct snd_seq_event_cell *head;\n\tstruct snd_seq_event_cell *tail;\n\tint cells;\n\tspinlock_t lock;\n\tsnd_use_lock_t use_lock;\n\twait_queue_head_t input_sleep;\n\tatomic_t overflow;\n};\n\nstruct snd_seq_pool {\n\tstruct snd_seq_event_cell *ptr;\n\tstruct snd_seq_event_cell *free;\n\tint total_elements;\n\tatomic_t counter;\n\tint size;\n\tint room;\n\tint closing;\n\tint max_used;\n\tint event_alloc_nopool;\n\tint event_alloc_failures;\n\tint event_alloc_success;\n\twait_queue_head_t output_sleep;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_port_callback {\n\tstruct module *owner;\n\tvoid *private_data;\n\tint (*subscribe)(void *, struct snd_seq_port_subscribe *);\n\tint (*unsubscribe)(void *, struct snd_seq_port_subscribe *);\n\tint (*use)(void *, struct snd_seq_port_subscribe *);\n\tint (*unuse)(void *, struct snd_seq_port_subscribe *);\n\tint (*event_input)(struct snd_seq_event *, int, void *, int, int);\n\tvoid (*private_free)(void *);\n};\n\nstruct snd_seq_port_info {\n\tstruct snd_seq_addr addr;\n\tchar name[64];\n\tunsigned int capability;\n\tunsigned int type;\n\tint midi_channels;\n\tint midi_voices;\n\tint synth_voices;\n\tint read_use;\n\tint write_use;\n\tvoid *kernel;\n\tunsigned int flags;\n\tunsigned char time_queue;\n\tunsigned char direction;\n\tunsigned char ump_group;\n\tchar reserved[57];\n};\n\nstruct snd_seq_port_info32 {\n\tstruct snd_seq_addr addr;\n\tchar name[64];\n\tu32 capability;\n\tu32 type;\n\ts32 midi_channels;\n\ts32 midi_voices;\n\ts32 synth_voices;\n\ts32 read_use;\n\ts32 write_use;\n\tu32 kernel;\n\tu32 flags;\n\tunsigned char time_queue;\n\tchar reserved[59];\n};\n\nstruct snd_seq_port_subscribe {\n\tstruct snd_seq_addr sender;\n\tstruct snd_seq_addr dest;\n\tunsigned int voices;\n\tunsigned int flags;\n\tunsigned char queue;\n\tunsigned char pad[3];\n\tchar reserved[64];\n};\n\nstruct snd_seq_prioq {\n\tstruct snd_seq_event_cell *head;\n\tstruct snd_seq_event_cell *tail;\n\tint cells;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_query_subs {\n\tstruct snd_seq_addr root;\n\tint type;\n\tint index;\n\tint num_subs;\n\tstruct snd_seq_addr addr;\n\tunsigned char queue;\n\tunsigned int flags;\n\tchar reserved[64];\n};\n\nstruct snd_seq_timer;\n\nstruct snd_seq_queue {\n\tint queue;\n\tchar name[64];\n\tstruct snd_seq_prioq *tickq;\n\tstruct snd_seq_prioq *timeq;\n\tstruct snd_seq_timer *timer;\n\tint owner;\n\tbool locked;\n\tbool klocked;\n\tbool check_again;\n\tbool check_blocked;\n\tunsigned int flags;\n\tunsigned int info_flags;\n\tspinlock_t owner_lock;\n\tspinlock_t check_lock;\n\tlong unsigned int clients_bitmap[3];\n\tunsigned int clients;\n\tstruct mutex timer_mutex;\n\tsnd_use_lock_t use_lock;\n};\n\nstruct snd_seq_queue_client {\n\tint queue;\n\tint client;\n\tint used;\n\tchar reserved[64];\n};\n\nstruct snd_seq_queue_info {\n\tint queue;\n\tint owner;\n\tunsigned int locked: 1;\n\tchar name[64];\n\tunsigned int flags;\n\tchar reserved[60];\n};\n\nstruct snd_seq_queue_status {\n\tint queue;\n\tint events;\n\tsnd_seq_tick_time_t tick;\n\tstruct snd_seq_real_time time;\n\tint running;\n\tint flags;\n\tchar reserved[64];\n};\n\nstruct snd_seq_queue_tempo {\n\tint queue;\n\tunsigned int tempo;\n\tint ppq;\n\tunsigned int skew_value;\n\tunsigned int skew_base;\n\tshort unsigned int tempo_base;\n\tchar reserved[22];\n};\n\nstruct snd_timer_id {\n\tint dev_class;\n\tint dev_sclass;\n\tint card;\n\tint device;\n\tint subdevice;\n};\n\nstruct snd_seq_queue_timer {\n\tint queue;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct snd_timer_id id;\n\t\t\tunsigned int resolution;\n\t\t} alsa;\n\t} u;\n\tchar reserved[64];\n};\n\ntypedef struct snd_seq_real_time snd_seq_real_time_t;\n\nstruct snd_seq_remove_events {\n\tunsigned int remove_mode;\n\tunion snd_seq_timestamp time;\n\tunsigned char queue;\n\tstruct snd_seq_addr dest;\n\tunsigned char channel;\n\tint type;\n\tchar tag;\n\tint reserved[10];\n};\n\nstruct snd_seq_running_info {\n\tunsigned char client;\n\tunsigned char big_endian;\n\tunsigned char cpu_mode;\n\tunsigned char pad;\n\tunsigned char reserved[12];\n};\n\nstruct snd_seq_subscribers {\n\tstruct snd_seq_port_subscribe info;\n\tstruct list_head src_list;\n\tstruct list_head dest_list;\n\tatomic_t ref_count;\n};\n\nstruct snd_seq_system_info {\n\tint queues;\n\tint clients;\n\tint ports;\n\tint channels;\n\tint cur_clients;\n\tint cur_queues;\n\tchar reserved[24];\n};\n\nstruct snd_seq_timer_tick {\n\tsnd_seq_tick_time_t cur_tick;\n\tlong unsigned int resolution;\n\tlong unsigned int fraction;\n};\n\nstruct snd_timer_instance;\n\nstruct snd_seq_timer {\n\tunsigned int running: 1;\n\tunsigned int initialized: 1;\n\tunsigned int tempo;\n\tint ppq;\n\tsnd_seq_real_time_t cur_time;\n\tstruct snd_seq_timer_tick tick;\n\tint tick_updated;\n\tint type;\n\tstruct snd_timer_id alsa_id;\n\tstruct snd_timer_instance *timeri;\n\tunsigned int ticks;\n\tlong unsigned int preferred_resolution;\n\tunsigned int skew;\n\tunsigned int skew_base;\n\tunsigned int tempo_base;\n\tstruct timespec64 last_update;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_ump_event {\n\tsnd_seq_event_type_t type;\n\tunsigned char flags;\n\tchar tag;\n\tunsigned char queue;\n\tunion snd_seq_timestamp time;\n\tstruct snd_seq_addr source;\n\tstruct snd_seq_addr dest;\n\tunion {\n\t\tunion snd_seq_event_data data;\n\t\tunsigned int ump[4];\n\t};\n};\n\nstruct snd_seq_usage {\n\tint cur;\n\tint peak;\n};\n\nstruct snd_soc_acpi_codecs {\n\tint num_codecs;\n\tu8 codecs[48];\n};\n\nstruct snd_timer_hardware {\n\tunsigned int flags;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tlong unsigned int ticks;\n\tint (*open)(struct snd_timer *);\n\tint (*close)(struct snd_timer *);\n\tlong unsigned int (*c_resolution)(struct snd_timer *);\n\tint (*start)(struct snd_timer *);\n\tint (*stop)(struct snd_timer *);\n\tint (*set_period)(struct snd_timer *, long unsigned int, long unsigned int);\n\tint (*precise_resolution)(struct snd_timer *, long unsigned int *, long unsigned int *);\n};\n\nstruct snd_timer {\n\tint tmr_class;\n\tstruct snd_card *card;\n\tstruct module *module;\n\tint tmr_device;\n\tint tmr_subdevice;\n\tchar id[64];\n\tchar name[80];\n\tunsigned int flags;\n\tint running;\n\tlong unsigned int sticks;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer *);\n\tstruct snd_timer_hardware hw;\n\tspinlock_t lock;\n\tstruct list_head device_list;\n\tstruct list_head open_list_head;\n\tstruct list_head active_list_head;\n\tstruct list_head ack_list_head;\n\tstruct list_head sack_list_head;\n\tstruct work_struct task_work;\n\tint max_instances;\n\tint num_instances;\n};\n\nstruct snd_timer_ginfo {\n\tstruct snd_timer_id tid;\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tunsigned int clients;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gparams {\n\tstruct snd_timer_id tid;\n\tlong unsigned int period_num;\n\tlong unsigned int period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gparams32 {\n\tstruct snd_timer_id tid;\n\tu32 period_num;\n\tu32 period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gstatus {\n\tstruct snd_timer_id tid;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_num;\n\tlong unsigned int resolution_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_info {\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_info32 {\n\tu32 flags;\n\ts32 card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tu32 reserved0;\n\tu32 resolution;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_instance {\n\tstruct snd_timer *timer;\n\tchar *owner;\n\tunsigned int flags;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer_instance *);\n\tvoid (*callback)(struct snd_timer_instance *, long unsigned int, long unsigned int);\n\tvoid (*ccallback)(struct snd_timer_instance *, int, struct timespec64 *, long unsigned int);\n\tvoid (*disconnect)(struct snd_timer_instance *);\n\tvoid *callback_data;\n\tlong unsigned int ticks;\n\tlong unsigned int cticks;\n\tlong unsigned int pticks;\n\tlong unsigned int resolution;\n\tlong unsigned int lost;\n\tint slave_class;\n\tunsigned int slave_id;\n\tstruct list_head open_list;\n\tstruct list_head active_list;\n\tstruct list_head ack_list;\n\tstruct list_head slave_list_head;\n\tstruct list_head slave_active_head;\n\tstruct snd_timer_instance *master;\n};\n\nstruct snd_timer_params {\n\tunsigned int flags;\n\tunsigned int ticks;\n\tunsigned int queue_size;\n\tunsigned int reserved0;\n\tunsigned int filter;\n\tunsigned char reserved[60];\n};\n\nstruct snd_timer_read {\n\tunsigned int resolution;\n\tunsigned int ticks;\n};\n\nstruct snd_timer_select {\n\tstruct snd_timer_id id;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_status32 {\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_status64 {\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_system_private {\n\tstruct timer_list tlist;\n\tstruct snd_timer *snd_timer;\n\tlong unsigned int last_expires;\n\tlong unsigned int last_jiffies;\n\tlong unsigned int correction;\n};\n\nstruct snd_timer_tread32 {\n\tint event;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int val;\n};\n\nstruct snd_timer_tread64 {\n\tint event;\n\tu8 pad1[4];\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int val;\n\tu8 pad2[4];\n};\n\nstruct snd_timer_uinfo {\n\t__u64 resolution;\n\tint fd;\n\tunsigned int id;\n\tunsigned char reserved[16];\n};\n\nstruct snd_timer_user {\n\tstruct snd_timer_instance *timeri;\n\tint tread;\n\tlong unsigned int ticks;\n\tlong unsigned int overrun;\n\tint qhead;\n\tint qtail;\n\tint qused;\n\tint queue_size;\n\tbool disconnected;\n\tstruct snd_timer_read *queue;\n\tstruct snd_timer_tread64 *tqueue;\n\tspinlock_t qlock;\n\tlong unsigned int last_resolution;\n\tunsigned int filter;\n\tstruct timespec64 tstamp;\n\twait_queue_head_t qchange_sleep;\n\tstruct snd_fasync *fasync;\n\tstruct mutex ioctl_lock;\n};\n\nstruct snd_xferi {\n\tsnd_pcm_sframes_t result;\n\tvoid *buf;\n\tsnd_pcm_uframes_t frames;\n};\n\nstruct snd_xferi32 {\n\ts32 result;\n\tu32 buf;\n\tu32 frames;\n};\n\nstruct snd_xfern {\n\tsnd_pcm_sframes_t result;\n\tvoid **bufs;\n\tsnd_pcm_uframes_t frames;\n};\n\nstruct snd_xfern32 {\n\ts32 result;\n\tu32 bufs;\n\tu32 frames;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct sockaddr_vm {\n\t__kernel_sa_family_t svm_family;\n\tshort unsigned int svm_reserved1;\n\tunsigned int svm_port;\n\tunsigned int svm_cid;\n\t__u8 svm_flags;\n\tunsigned char svm_zero[3];\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int input_queue_head;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t defer_csd;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct sp_node {\n\tstruct rb_node nd;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct mempolicy *policy;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct space_resv_32 {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n} __attribute__((packed));\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n};\n\nstruct spi_function_template {\n\tvoid (*get_period)(struct scsi_target *);\n\tvoid (*set_period)(struct scsi_target *, int);\n\tvoid (*get_offset)(struct scsi_target *);\n\tvoid (*set_offset)(struct scsi_target *, int);\n\tvoid (*get_width)(struct scsi_target *);\n\tvoid (*set_width)(struct scsi_target *, int);\n\tvoid (*get_iu)(struct scsi_target *);\n\tvoid (*set_iu)(struct scsi_target *, int);\n\tvoid (*get_dt)(struct scsi_target *);\n\tvoid (*set_dt)(struct scsi_target *, int);\n\tvoid (*get_qas)(struct scsi_target *);\n\tvoid (*set_qas)(struct scsi_target *, int);\n\tvoid (*get_wr_flow)(struct scsi_target *);\n\tvoid (*set_wr_flow)(struct scsi_target *, int);\n\tvoid (*get_rd_strm)(struct scsi_target *);\n\tvoid (*set_rd_strm)(struct scsi_target *, int);\n\tvoid (*get_rti)(struct scsi_target *);\n\tvoid (*set_rti)(struct scsi_target *, int);\n\tvoid (*get_pcomp_en)(struct scsi_target *);\n\tvoid (*set_pcomp_en)(struct scsi_target *, int);\n\tvoid (*get_hold_mcs)(struct scsi_target *);\n\tvoid (*set_hold_mcs)(struct scsi_target *, int);\n\tvoid (*get_signalling)(struct Scsi_Host *);\n\tvoid (*set_signalling)(struct Scsi_Host *, enum spi_signal_type);\n\tint (*deny_binding)(struct scsi_target *);\n\tlong unsigned int show_period: 1;\n\tlong unsigned int show_offset: 1;\n\tlong unsigned int show_width: 1;\n\tlong unsigned int show_iu: 1;\n\tlong unsigned int show_dt: 1;\n\tlong unsigned int show_qas: 1;\n\tlong unsigned int show_wr_flow: 1;\n\tlong unsigned int show_rd_strm: 1;\n\tlong unsigned int show_rti: 1;\n\tlong unsigned int show_pcomp_en: 1;\n\tlong unsigned int show_hold_mcs: 1;\n};\n\nstruct spi_host_attrs {\n\tenum spi_signal_type signalling;\n};\n\nstruct spi_internal {\n\tstruct scsi_transport_template t;\n\tstruct spi_function_template *f;\n};\n\nstruct spi_transport_attrs {\n\tint period;\n\tint min_period;\n\tint offset;\n\tint max_offset;\n\tunsigned int width: 1;\n\tunsigned int max_width: 1;\n\tunsigned int iu: 1;\n\tunsigned int max_iu: 1;\n\tunsigned int dt: 1;\n\tunsigned int qas: 1;\n\tunsigned int max_qas: 1;\n\tunsigned int wr_flow: 1;\n\tunsigned int rd_strm: 1;\n\tunsigned int rti: 1;\n\tunsigned int pcomp_en: 1;\n\tunsigned int hold_mcs: 1;\n\tunsigned int initial_dv: 1;\n\tlong unsigned int flags;\n\tunsigned int support_sync: 1;\n\tunsigned int support_wide: 1;\n\tunsigned int support_dt: 1;\n\tunsigned int support_dt_only;\n\tunsigned int support_ius;\n\tunsigned int support_qas;\n\tunsigned int dv_pending: 1;\n\tunsigned int dv_in_progress: 1;\n\tstruct mutex dv_mutex;\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct squashfs_base_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n};\n\nstruct squashfs_cache_entry;\n\nstruct squashfs_cache {\n\tchar *name;\n\tint entries;\n\tint curr_blk;\n\tint next_blk;\n\tint num_waiters;\n\tint unused;\n\tint block_size;\n\tint pages;\n\tspinlock_t lock;\n\twait_queue_head_t wait_queue;\n\tstruct squashfs_cache_entry *entry;\n};\n\nstruct squashfs_page_actor;\n\nstruct squashfs_cache_entry {\n\tu64 block;\n\tint length;\n\tint refcount;\n\tu64 next_index;\n\tint pending;\n\tint error;\n\tint num_waiters;\n\twait_queue_head_t wait_queue;\n\tstruct squashfs_cache *cache;\n\tvoid **data;\n\tstruct squashfs_page_actor *actor;\n};\n\nstruct squashfs_sb_info;\n\nstruct squashfs_decompressor {\n\tvoid * (*init)(struct squashfs_sb_info *, void *);\n\tvoid * (*comp_opts)(struct squashfs_sb_info *, void *, int);\n\tvoid (*free)(void *);\n\tint (*decompress)(struct squashfs_sb_info *, void *, struct bio *, int, int, struct squashfs_page_actor *);\n\tint id;\n\tchar *name;\n\tint alloc_buffer;\n\tint supported;\n};\n\nstruct squashfs_decompressor_thread_ops {\n\tvoid * (*create)(struct squashfs_sb_info *, void *);\n\tvoid (*destroy)(struct squashfs_sb_info *);\n\tint (*decompress)(struct squashfs_sb_info *, struct bio *, int, int, struct squashfs_page_actor *);\n\tint (*max_decompressors)(void);\n};\n\nstruct squashfs_dev_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 rdev;\n};\n\nstruct squashfs_dir_entry {\n\t__le16 offset;\n\t__le16 inode_number;\n\t__le16 type;\n\t__le16 size;\n\tchar name[0];\n};\n\nstruct squashfs_dir_header {\n\t__le32 count;\n\t__le32 start_block;\n\t__le32 inode_number;\n};\n\nstruct squashfs_dir_index {\n\t__le32 index;\n\t__le32 start_block;\n\t__le32 size;\n\tunsigned char name[0];\n};\n\nstruct squashfs_dir_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 start_block;\n\t__le32 nlink;\n\t__le16 file_size;\n\t__le16 offset;\n\t__le32 parent_inode;\n};\n\nstruct squashfs_fragment_entry {\n\t__le64 start_block;\n\t__le32 size;\n\tunsigned int unused;\n};\n\nstruct squashfs_ldev_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 rdev;\n\t__le32 xattr;\n};\n\nstruct squashfs_symlink_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 symlink_size;\n\tchar symlink[0];\n};\n\nstruct squashfs_reg_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 start_block;\n\t__le32 fragment;\n\t__le32 offset;\n\t__le32 file_size;\n\t__le16 block_list[0];\n};\n\nstruct squashfs_lreg_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le64 start_block;\n\t__le64 file_size;\n\t__le64 sparse;\n\t__le32 nlink;\n\t__le32 fragment;\n\t__le32 offset;\n\t__le32 xattr;\n\t__le16 block_list[0];\n};\n\nstruct squashfs_ldir_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 file_size;\n\t__le32 start_block;\n\t__le32 parent_inode;\n\t__le16 i_count;\n\t__le16 offset;\n\t__le32 xattr;\n\tstruct squashfs_dir_index index[0];\n};\n\nstruct squashfs_ipc_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n};\n\nstruct squashfs_lipc_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 xattr;\n};\n\nunion squashfs_inode {\n\tstruct squashfs_base_inode base;\n\tstruct squashfs_dev_inode dev;\n\tstruct squashfs_ldev_inode ldev;\n\tstruct squashfs_symlink_inode symlink;\n\tstruct squashfs_reg_inode reg;\n\tstruct squashfs_lreg_inode lreg;\n\tstruct squashfs_dir_inode dir;\n\tstruct squashfs_ldir_inode ldir;\n\tstruct squashfs_ipc_inode ipc;\n\tstruct squashfs_lipc_inode lipc;\n};\n\nstruct squashfs_inode_info {\n\tu64 start;\n\tint offset;\n\tu64 xattr;\n\tunsigned int xattr_size;\n\tint xattr_count;\n\tint parent;\n\tunion {\n\t\tstruct {\n\t\t\tu64 fragment_block;\n\t\t\tint fragment_size;\n\t\t\tint fragment_offset;\n\t\t\tu64 block_list_start;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dir_idx_start;\n\t\t\tint dir_idx_offset;\n\t\t\tint dir_idx_cnt;\n\t\t};\n\t};\n\tstruct inode vfs_inode;\n};\n\nstruct squashfs_mount_opts {\n\tenum Opt_errors errors;\n\tconst struct squashfs_decompressor_thread_ops *thread_ops;\n\tint thread_num;\n};\n\nstruct squashfs_page_actor {\n\tunion {\n\t\tvoid **buffer;\n\t\tstruct page **page;\n\t};\n\tvoid *pageaddr;\n\tvoid *tmp_buffer;\n\tvoid * (*squashfs_first_page)(struct squashfs_page_actor *);\n\tvoid * (*squashfs_next_page)(struct squashfs_page_actor *);\n\tvoid (*squashfs_finish_page)(struct squashfs_page_actor *);\n\tstruct page *last_page;\n\tint pages;\n\tint length;\n\tint next_page;\n\tint alloc_buffer;\n\tint returned_pages;\n\tlong unsigned int next_index;\n};\n\nstruct squashfs_sb_info {\n\tconst struct squashfs_decompressor *decompressor;\n\tint devblksize;\n\tint devblksize_log2;\n\tstruct squashfs_cache *block_cache;\n\tstruct squashfs_cache *fragment_cache;\n\tstruct squashfs_cache *read_page;\n\tstruct address_space *cache_mapping;\n\tint next_meta_index;\n\t__le64 *id_table;\n\t__le64 *fragment_index;\n\t__le64 *xattr_id_table;\n\tstruct mutex meta_index_mutex;\n\tstruct meta_index *meta_index;\n\tvoid *stream;\n\t__le64 *inode_lookup_table;\n\tu64 inode_table;\n\tu64 directory_table;\n\tu64 xattr_table;\n\tunsigned int block_size;\n\tshort unsigned int block_log;\n\tlong long int bytes_used;\n\tunsigned int inodes;\n\tunsigned int fragments;\n\tunsigned int xattr_ids;\n\tunsigned int ids;\n\tbool panic_on_errors;\n\tconst struct squashfs_decompressor_thread_ops *thread_ops;\n\tint max_thread_num;\n};\n\nstruct squashfs_stream {\n\tvoid *stream;\n\tstruct mutex mutex;\n};\n\nstruct squashfs_super_block {\n\t__le32 s_magic;\n\t__le32 inodes;\n\t__le32 mkfs_time;\n\t__le32 block_size;\n\t__le32 fragments;\n\t__le16 compression;\n\t__le16 block_log;\n\t__le16 flags;\n\t__le16 no_ids;\n\t__le16 s_major;\n\t__le16 s_minor;\n\t__le64 root_inode;\n\t__le64 bytes_used;\n\t__le64 id_table_start;\n\t__le64 xattr_id_table_start;\n\t__le64 inode_table_start;\n\t__le64 directory_table_start;\n\t__le64 fragment_table_start;\n\t__le64 lookup_table_start;\n};\n\nstruct squashfs_xattr_id_table {\n\t__le64 xattr_table_start;\n\t__le32 xattr_ids;\n\t__le32 unused;\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec;\n\nstruct squashfs_xz {\n\tstruct xz_dec *state;\n\tstruct xz_buf buf;\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_node;\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[3];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct ssb_state {\n\tstruct ssb_state *shared_state;\n\traw_spinlock_t lock;\n\tunsigned int disable_state;\n\tlong unsigned int local_state;\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[0];\n};\n\nstruct stack_frame {\n\tstruct stack_frame *next_frame;\n\tlong unsigned int return_address;\n};\n\nstruct stack_frame_ia32 {\n\tu32 next_frame;\n\tu32 return_address;\n};\n\nstruct stack_frame_user {\n\tconst void *next_fp;\n\tlong unsigned int ret_addr;\n};\n\nstruct stack_info {\n\tenum stack_type type;\n\tlong unsigned int *begin;\n\tlong unsigned int *end;\n\tlong unsigned int *next_sp;\n};\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tu64 data[0];\n};\n\nstruct stack_record {\n\tstruct list_head hash_list;\n\tu32 hash;\n\tu32 size;\n\tunion handle_parts handle;\n\trefcount_t count;\n\tunion {\n\t\tlong unsigned int entries[64];\n\t\tstruct {\n\t\t\tstruct list_head free_list;\n\t\t\tlong unsigned int rcu_state;\n\t\t};\n\t};\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\nstruct staging_state {\n\tvoid *mmio_base;\n\tunsigned int ucode_len;\n\tunsigned int chunk_size;\n\tunsigned int bytes_sent;\n\tunsigned int offset;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\t__kernel_ulong_t st_dev;\n\t__kernel_ulong_t st_ino;\n\t__kernel_ulong_t st_nlink;\n\tunsigned int st_mode;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tunsigned int __pad0;\n\t__kernel_ulong_t st_rdev;\n\t__kernel_long_t st_size;\n\t__kernel_long_t st_blksize;\n\t__kernel_long_t st_blocks;\n\t__kernel_ulong_t st_atime;\n\t__kernel_ulong_t st_atime_nsec;\n\t__kernel_ulong_t st_mtime;\n\t__kernel_ulong_t st_mtime_nsec;\n\t__kernel_ulong_t st_ctime;\n\t__kernel_ulong_t st_ctime_nsec;\n\t__kernel_long_t __unused[3];\n};\n\nstruct stat64 {\n\tlong long unsigned int st_dev;\n\tunsigned char __pad0[4];\n\tunsigned int __st_ino;\n\tunsigned int st_mode;\n\tunsigned int st_nlink;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tlong long unsigned int st_rdev;\n\tunsigned char __pad3[4];\n\tlong long int st_size;\n\tunsigned int st_blksize;\n\tlong long int st_blocks;\n\tunsigned int st_atime;\n\tunsigned int st_atime_nsec;\n\tunsigned int st_mtime;\n\tunsigned int st_mtime_nsec;\n\tunsigned int st_ctime;\n\tunsigned int st_ctime_nsec;\n\tlong long unsigned int st_ino;\n} __attribute__((packed));\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct tracer_stat;\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct statfs {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__kernel_long_t f_blocks;\n\t__kernel_long_t f_bfree;\n\t__kernel_long_t f_bavail;\n\t__kernel_long_t f_files;\n\t__kernel_long_t f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct statfs64 {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct static_call_mod;\n\nstruct static_call_key {\n\tvoid *func;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct static_call_mod *mods;\n\t\tstruct static_call_site *sites;\n\t};\n};\n\nstruct static_call_mod {\n\tstruct static_call_mod *next;\n\tstruct module *mod;\n\tstruct static_call_site *sites;\n};\n\nstruct static_call_site {\n\ts32 addr;\n\ts32 key;\n};\n\nstruct static_call_tramp_key {\n\ts32 tramp;\n\ts32 key;\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_tree_desc_s {\n\tconst ct_data *static_tree;\n\tconst int *extra_bits;\n\tint extra_base;\n\tint elems;\n\tint max_length;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct stepping_info {\n\tchar stepping;\n\tchar substepping;\n};\n\nstruct stereo_mandatory_mode {\n\tint width;\n\tint height;\n\tint vrefresh;\n\tunsigned int flags;\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct stripe {\n\tstruct dm_dev *dev;\n\tsector_t physical_start;\n\tatomic_t error_count;\n};\n\nstruct stripe_c {\n\tuint32_t stripes;\n\tint stripes_shift;\n\tsector_t stripe_width;\n\tuint32_t chunk_size;\n\tint chunk_size_shift;\n\tstruct dm_target *ti;\n\tstruct work_struct trigger_event;\n\tstruct stripe stripe[0];\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct subplatform_desc {\n\tstruct intel_display_platforms platforms;\n\tconst char *name;\n\tconst u16 *pciidlist;\n\tstruct stepping_desc step_info;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\nstruct sugov_policy;\n\nstruct sugov_cpu {\n\tstruct update_util_data update_util;\n\tstruct sugov_policy *sg_policy;\n\tunsigned int cpu;\n\tbool iowait_boost_pending;\n\tunsigned int iowait_boost;\n\tu64 last_update;\n\tlong unsigned int util;\n\tlong unsigned int bw_min;\n\tlong unsigned int saved_idle_calls;\n};\n\nstruct sugov_tunables;\n\nstruct sugov_policy {\n\tstruct cpufreq_policy *policy;\n\tstruct sugov_tunables *tunables;\n\tstruct list_head tunables_hook;\n\traw_spinlock_t update_lock;\n\tu64 last_freq_update_time;\n\ts64 freq_update_delay_ns;\n\tunsigned int next_freq;\n\tunsigned int cached_raw_freq;\n\tstruct irq_work irq_work;\n\tstruct kthread_work work;\n\tstruct mutex work_lock;\n\tstruct kthread_worker worker;\n\tstruct task_struct *thread;\n\tbool work_in_progress;\n\tbool limits_changed;\n\tbool need_freq_update;\n};\n\nstruct sugov_tunables {\n\tstruct gov_attr_set attr_set;\n\tunsigned int rate_limit_us;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct mtd_info;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tconst struct xattr_handler * const *s_xattr;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 64;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t);\n\tssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t);\n\tstruct dquot ** (*get_dquots)(struct inode *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct super_type {\n\tchar *name;\n\tstruct module *owner;\n\tint (*load_super)(struct md_rdev *, struct md_rdev *, int);\n\tint (*validate_super)(struct mddev *, struct md_rdev *, struct md_rdev *);\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tlong long unsigned int (*rdev_size_change)(struct md_rdev *, sector_t);\n\tint (*allow_new_offset)(struct md_rdev *, long long unsigned int);\n};\n\nstruct suspend_stats {\n\tunsigned int step_failures[8];\n\tunsigned int success;\n\tunsigned int fail;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tu64 last_hw_sleep;\n\tu64 total_hw_sleep;\n\tu64 max_hw_sleep;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nstruct svm_cpu_data {\n\tu64 asid_generation;\n\tu32 max_asid;\n\tu32 next_asid;\n\tu32 min_asid;\n\tbool bp_spec_reduce_set;\n\tstruct vmcb *save_area;\n\tlong unsigned int save_area_pa;\n\tstruct vmcb **sev_vmcbs;\n};\n\nstruct vmcb_ctrl_area_cached {\n\tu32 intercepts[6];\n\tu16 pause_filter_thresh;\n\tu16 pause_filter_count;\n\tu64 iopm_base_pa;\n\tu64 msrpm_base_pa;\n\tu64 tsc_offset;\n\tu32 asid;\n\tu8 tlb_ctl;\n\tu8 erap_ctl;\n\tu32 int_ctl;\n\tu32 int_vector;\n\tu32 int_state;\n\tu64 exit_code;\n\tu64 exit_info_1;\n\tu64 exit_info_2;\n\tu32 exit_int_info;\n\tu32 exit_int_info_err;\n\tu64 nested_ctl;\n\tu32 event_inj;\n\tu32 event_inj_err;\n\tu64 next_rip;\n\tu64 nested_cr3;\n\tu64 virt_ext;\n\tu32 clean;\n\tu64 bus_lock_rip;\n\tunion {\n\t\tstruct hv_vmcb_enlightenments hv_enlightenments;\n\t\tu8 reserved_sw[32];\n\t};\n};\n\nstruct vmcb_save_area_cached {\n\tu64 efer;\n\tu64 cr4;\n\tu64 cr3;\n\tu64 cr0;\n\tu64 dr7;\n\tu64 dr6;\n};\n\nstruct svm_nested_state {\n\tstruct kvm_vmcb_info vmcb02;\n\tu64 hsave_msr;\n\tu64 vm_cr_msr;\n\tu64 vmcb12_gpa;\n\tu64 last_vmcb12_gpa;\n\tvoid *msrpm;\n\tbool nested_run_pending;\n\tstruct vmcb_ctrl_area_cached ctl;\n\tstruct vmcb_save_area_cached save;\n\tbool initialized;\n\tbool force_msr_bitmap_recalc;\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[1];\n\tstruct list_head frag_clusters[1];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_map_page;\n\nstruct swap_map_page_list;\n\nstruct swap_map_handle {\n\tstruct swap_map_page *cur;\n\tstruct swap_map_page_list *maps;\n\tsector_t cur_swap;\n\tsector_t first_sector;\n\tunsigned int k;\n\tlong unsigned int reqd_free_pages;\n\tu32 crc32;\n};\n\nstruct swap_map_page {\n\tsector_t entries[511];\n\tsector_t next_swap;\n};\n\nstruct swap_map_page_list {\n\tstruct swap_map_page *map;\n\tstruct swap_map_page_list *next;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[1];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[256];\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n};\n\nstruct swmii_regs {\n\tu16 bmsr;\n\tu16 lpa;\n\tu16 lpagb;\n\tu16 estat;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct swsusp_extent {\n\tstruct rb_node node;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct swsusp_header {\n\tchar reserved[4056];\n\tu32 hw_sig;\n\tu32 crc32;\n\tsector_t image;\n\tunsigned int flags;\n\tchar orig_sig[10];\n\tchar sig[10];\n};\n\nstruct swsusp_info {\n\tstruct new_utsname uts;\n\tu32 version_code;\n\tlong unsigned int num_physpages;\n\tint cpus;\n\tlong unsigned int image_pages;\n\tlong unsigned int pages;\n\tlong unsigned int size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sym_count_ctx {\n\tunsigned int count;\n\tconst char *name;\n};\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tbool pt_port_open;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct sync_fence_info {\n\tchar obj_name[32];\n\tchar driver_name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u64 timestamp_ns;\n};\n\nstruct sync_file {\n\tstruct file *file;\n\tchar user_name[32];\n\tstruct list_head sync_file_list;\n\twait_queue_head_t wq;\n\tlong unsigned int flags;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct sync_file_info {\n\tchar name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u32 num_fences;\n\t__u32 pad;\n\t__u64 sync_fence_info;\n};\n\nstruct sync_io {\n\tlong unsigned int error_bits;\n\tstruct completion wait;\n};\n\nstruct sync_merge_data {\n\tchar name[32];\n\t__s32 fd2;\n\t__s32 fence;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct sync_set_deadline {\n\t__u64 deadline_ns;\n\t__u64 pad;\n};\n\nstruct syncobj_eventfd_entry {\n\tstruct list_head node;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tstruct drm_syncobj *syncobj;\n\tstruct eventfd_ctx *ev_fd_ctx;\n\tu64 point;\n\tu32 flags;\n};\n\nstruct syncobj_wait_entry {\n\tstruct list_head node;\n\tstruct task_struct *task;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tu64 point;\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct syscall_args {\n\tchar *ptr_array[3];\n\tint read[3];\n\tint uargs;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_metadata {\n\tconst char *name;\n\tint syscall_nr;\n\tu8 nb_args: 7;\n\tu8 user_arg_is_str: 1;\n\ts8 user_arg_size;\n\tshort int user_mask;\n\tconst char **types;\n\tconst char **args;\n\tstruct list_head enter_fields;\n\tstruct trace_event_call *enter_event;\n\tstruct trace_event_call *exit_event;\n};\n\nstruct syscall_tp_t {\n\tstruct trace_entry ent;\n\tint syscall_nr;\n\tlong unsigned int ret;\n};\n\nstruct syscall_tp_t___2 {\n\tstruct trace_entry ent;\n\tint syscall_nr;\n\tlong unsigned int args[6];\n};\n\nstruct syscall_trace_enter {\n\tstruct trace_entry ent;\n\tint nr;\n\tlong unsigned int args[0];\n};\n\nstruct syscall_trace_exit {\n\tstruct trace_entry ent;\n\tint nr;\n\tlong int ret;\n};\n\nstruct trace_user_buf;\n\nstruct trace_user_buf_info {\n\tstruct trace_user_buf *tbuf;\n\tsize_t size;\n\tint ref;\n};\n\nstruct syscall_user_buffer {\n\tstruct trace_user_buf_info buf;\n\tstruct callback_head rcu;\n};\n\nstruct syscall_user_dispatch {\n\tchar *selector;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tbool on_dispatch;\n};\n\nstruct syscore_ops;\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysfb_display_info {\n\tstruct screen_info screen;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysfs_wi_group {\n\tstruct kobject wi_kobj;\n\tstruct mutex kobj_lock;\n\tstruct iw_node_attr *nattrs[0];\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[0];\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[12];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tunsigned int shift;\n\tunsigned int shift_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[12];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct table_device {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev dm_dev;\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\ntypedef int (*dm_ctr_fn)(struct dm_target *, unsigned int, char **);\n\ntypedef void (*dm_dtr_fn)(struct dm_target *);\n\ntypedef int (*dm_map_fn)(struct dm_target *, struct bio *);\n\ntypedef int (*dm_clone_and_map_request_fn)(struct dm_target *, struct request *, union map_info *, struct request **);\n\ntypedef void (*dm_release_clone_request_fn)(struct request *, union map_info *);\n\ntypedef int (*dm_endio_fn)(struct dm_target *, struct bio *, blk_status_t *);\n\ntypedef int (*dm_request_endio_fn)(struct dm_target *, struct request *, blk_status_t, union map_info *);\n\ntypedef void (*dm_presuspend_fn)(struct dm_target *);\n\ntypedef void (*dm_presuspend_undo_fn)(struct dm_target *);\n\ntypedef void (*dm_postsuspend_fn)(struct dm_target *);\n\ntypedef int (*dm_preresume_fn)(struct dm_target *);\n\ntypedef void (*dm_resume_fn)(struct dm_target *);\n\ntypedef void (*dm_status_fn)(struct dm_target *, status_type_t, unsigned int, char *, unsigned int);\n\ntypedef int (*dm_message_fn)(struct dm_target *, unsigned int, char **, char *, unsigned int);\n\ntypedef int (*dm_prepare_ioctl_fn)(struct dm_target *, struct block_device **, unsigned int, long unsigned int, bool *);\n\ntypedef int (*dm_report_zones_fn)(struct dm_target *);\n\ntypedef int (*dm_busy_fn)(struct dm_target *);\n\ntypedef int (*iterate_devices_callout_fn)(struct dm_target *, struct dm_dev *, sector_t, sector_t, void *);\n\ntypedef int (*dm_iterate_devices_fn)(struct dm_target *, iterate_devices_callout_fn, void *);\n\ntypedef void (*dm_io_hints_fn)(struct dm_target *, struct queue_limits *);\n\ntypedef long int (*dm_dax_direct_access_fn)(struct dm_target *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\ntypedef int (*dm_dax_zero_page_range_fn)(struct dm_target *, long unsigned int, size_t);\n\ntypedef size_t (*dm_dax_recovery_write_fn)(struct dm_target *, long unsigned int, void *, size_t, struct iov_iter *);\n\nstruct target_type {\n\tuint64_t features;\n\tconst char *name;\n\tstruct module *module;\n\tunsigned int version[3];\n\tdm_ctr_fn ctr;\n\tdm_dtr_fn dtr;\n\tdm_map_fn map;\n\tdm_clone_and_map_request_fn clone_and_map_rq;\n\tdm_release_clone_request_fn release_clone_rq;\n\tdm_endio_fn end_io;\n\tdm_request_endio_fn rq_end_io;\n\tdm_presuspend_fn presuspend;\n\tdm_presuspend_undo_fn presuspend_undo;\n\tdm_postsuspend_fn postsuspend;\n\tdm_preresume_fn preresume;\n\tdm_resume_fn resume;\n\tdm_status_fn status;\n\tdm_message_fn message;\n\tdm_prepare_ioctl_fn prepare_ioctl;\n\tdm_report_zones_fn report_zones;\n\tdm_busy_fn busy;\n\tdm_iterate_devices_fn iterate_devices;\n\tdm_io_hints_fn io_hints;\n\tdm_dax_direct_access_fn direct_access;\n\tdm_dax_zero_page_range_fn dax_zero_page_range;\n\tdm_dax_recovery_write_fn dax_recovery_write;\n\tstruct list_head list;\n};\n\nstruct task_delay_info {\n\traw_spinlock_t lock;\n\tu64 blkio_start;\n\tu64 blkio_delay_max;\n\tu64 blkio_delay_min;\n\tu64 blkio_delay;\n\tu64 swapin_start;\n\tu64 swapin_delay_max;\n\tu64 swapin_delay_min;\n\tu64 swapin_delay;\n\tu32 blkio_count;\n\tu32 swapin_count;\n\tu64 freepages_start;\n\tu64 freepages_delay_max;\n\tu64 freepages_delay_min;\n\tu64 freepages_delay;\n\tu64 thrashing_start;\n\tu64 thrashing_delay_max;\n\tu64 thrashing_delay_min;\n\tu64 thrashing_delay;\n\tu64 compact_start;\n\tu64 compact_delay_max;\n\tu64 compact_delay_min;\n\tu64 compact_delay;\n\tu64 wpcopy_start;\n\tu64 wpcopy_delay_max;\n\tu64 wpcopy_delay_min;\n\tu64 wpcopy_delay;\n\tu64 irq_delay_max;\n\tu64 irq_delay_min;\n\tu64 irq_delay;\n\tu32 freepages_count;\n\tu32 thrashing_count;\n\tu32 compact_count;\n\tu32 wpcopy_count;\n\tu32 irq_count;\n\tstruct timespec64 blkio_delay_max_ts;\n\tstruct timespec64 swapin_delay_max_ts;\n\tstruct timespec64 freepages_delay_max_ts;\n\tstruct timespec64 thrashing_delay_max_ts;\n\tstruct timespec64 compact_delay_max_ts;\n\tstruct timespec64 wpcopy_delay_max_ts;\n\tstruct timespec64 irq_delay_max_ts;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tatomic_long_t load_avg;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct autogroup *autogroup;\n\tstruct cfs_bandwidth cfs_bandwidth;\n};\n\nstruct task_numa_env {\n\tstruct task_struct *p;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tint imb_numa_nr;\n\tstruct numa_stats src_stats;\n\tstruct numa_stats dst_stats;\n\tint imbalance_pct;\n\tint dist;\n\tstruct task_struct *best_task;\n\tlong int best_imp;\n\tint best_cpu;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct thread_info {\n\tlong unsigned int flags;\n\tlong unsigned int syscall_work;\n\tu32 status;\n\tu32 cpu;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {\n\tstruct arch_tlbflush_unmap_batch arch;\n\tbool flush_required;\n\tbool writable;\n};\n\nunion unwind_task_id {\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 cnt;\n\t};\n\tu64 id;\n};\n\nstruct unwind_cache;\n\nstruct unwind_task_info {\n\tatomic_long_t unwind_mask;\n\tstruct unwind_cache *cache;\n\tstruct callback_head work;\n\tunion unwind_task_id id;\n};\n\nstruct thread_struct {\n\tstruct desc_struct tls_array[3];\n\tlong unsigned int sp;\n\tshort unsigned int es;\n\tshort unsigned int ds;\n\tshort unsigned int fsindex;\n\tshort unsigned int gsindex;\n\tlong unsigned int fsbase;\n\tlong unsigned int gsbase;\n\tstruct perf_event *ptrace_bps[4];\n\tlong unsigned int virtual_dr6;\n\tlong unsigned int ptrace_dr7;\n\tlong unsigned int cr2;\n\tlong unsigned int trap_nr;\n\tlong unsigned int error_code;\n\tstruct io_bitmap *io_bitmap;\n\tlong unsigned int iopl_emul;\n\tunsigned int iopl_warn: 1;\n\tu32 pkru;\n};\n\nstruct uprobe_task;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct rb_node core_node;\n\tlong unsigned int core_cookie;\n\tunsigned int core_occupation;\n\tstruct task_group *sched_task_group;\n\tlong: 64;\n\tstruct sched_statistics stats;\n\tstruct hlist_head preempt_notifiers;\n\tunsigned int btrace_seq;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tint rcu_read_lock_nesting;\n\tunion rcu_special rcu_read_unlock_special;\n\tstruct list_head rcu_node_entry;\n\tstruct rcu_node *rcu_blocked_node;\n\tlong unsigned int rcu_tasks_nvcsw;\n\tu8 rcu_tasks_holdout;\n\tu8 rcu_tasks_idx;\n\tint rcu_tasks_idle_cpu;\n\tstruct list_head rcu_tasks_holdout_list;\n\tint rcu_tasks_exit_cpu;\n\tstruct list_head rcu_tasks_exit_list;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int restore_sigmask: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int use_memdelay: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int pasid_activated: 1;\n\tunsigned int reported_split_lock: 1;\n\tunsigned int in_thrashing: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct posix_cputimers_work posix_cputimers_work;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tint non_block_count;\n\tstruct irqtrace_events irqtrace;\n\tunsigned int hardirq_threaded;\n\tu64 hardirq_chain_key;\n\tint softirqs_enabled;\n\tint softirq_context;\n\tint irq_config;\n\tu64 curr_chain_key;\n\tint lockdep_depth;\n\tunsigned int lockdep_recursion;\n\tstruct held_lock held_locks[48];\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tu64 acct_rss_mem1;\n\tu64 acct_vm_mem1;\n\tu64 acct_timexpd;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct compat_robust_list_head *compat_robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tu8 perf_recursion[4];\n\tstruct perf_event_context *perf_event_ctxp;\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct perf_ctx_data *perf_ctx_data;\n\tstruct mempolicy *mempolicy;\n\tshort int il_prev;\n\tu8 il_weight;\n\tshort int pref_node_fork;\n\tint numa_scan_seq;\n\tunsigned int numa_scan_period;\n\tunsigned int numa_scan_period_max;\n\tint numa_preferred_nid;\n\tlong unsigned int numa_migrate_retry;\n\tu64 node_stamp;\n\tu64 last_task_numa_placement;\n\tu64 last_sum_exec_runtime;\n\tstruct callback_head numa_work;\n\tstruct numa_group *numa_group;\n\tlong unsigned int *numa_faults;\n\tlong unsigned int total_numa_faults;\n\tlong unsigned int numa_faults_locality[3];\n\tlong unsigned int numa_pages_migrated;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tstruct task_delay_info *delays;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tint curr_ret_stack;\n\tint curr_ret_depth;\n\tlong unsigned int *ret_stack;\n\tlong long unsigned int ftrace_timestamp;\n\tlong long unsigned int ftrace_sleeptime;\n\tatomic_t trace_overrun;\n\tatomic_t tracing_graph_pause;\n\tlong unsigned int trace_recursion;\n\tstruct gendisk *throttle_disk;\n\tstruct uprobe_task *utask;\n\tstruct kmap_ctrl kmap_ctrl;\n\tlong unsigned int task_state_change;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\tstruct vm_struct *stack_vm_area;\n\trefcount_t stack_refcount;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tvoid *mce_vaddr;\n\t__u64 mce_kflags;\n\tu64 mce_addr;\n\t__u64 mce_ripv: 1;\n\t__u64 mce_whole_page: 1;\n\t__u64 __mce_reserved: 62;\n\tstruct callback_head mce_kill_me;\n\tint mce_count;\n\tstruct llist_head kretprobe_instances;\n\tstruct llist_head rethooks;\n\tstruct callback_head l1d_flush_kill;\n\tstruct unwind_task_info unwind_info;\n\tstruct thread_struct thread;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct taskstats {\n\t__u16 version;\n\t__u32 ac_exitcode;\n\t__u8 ac_flag;\n\t__u8 ac_nice;\n\t__u64 cpu_count;\n\t__u64 cpu_delay_total;\n\t__u64 blkio_count;\n\t__u64 blkio_delay_total;\n\t__u64 swapin_count;\n\t__u64 swapin_delay_total;\n\t__u64 cpu_run_real_total;\n\t__u64 cpu_run_virtual_total;\n\tchar ac_comm[32];\n\t__u8 ac_sched;\n\t__u8 ac_pad[3];\n\tlong: 0;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u64 ac_etime;\n\t__u64 ac_utime;\n\t__u64 ac_stime;\n\t__u64 ac_minflt;\n\t__u64 ac_majflt;\n\t__u64 coremem;\n\t__u64 virtmem;\n\t__u64 hiwater_rss;\n\t__u64 hiwater_vm;\n\t__u64 read_char;\n\t__u64 write_char;\n\t__u64 read_syscalls;\n\t__u64 write_syscalls;\n\t__u64 read_bytes;\n\t__u64 write_bytes;\n\t__u64 cancelled_write_bytes;\n\t__u64 nvcsw;\n\t__u64 nivcsw;\n\t__u64 ac_utimescaled;\n\t__u64 ac_stimescaled;\n\t__u64 cpu_scaled_run_real_total;\n\t__u64 freepages_count;\n\t__u64 freepages_delay_total;\n\t__u64 thrashing_count;\n\t__u64 thrashing_delay_total;\n\t__u64 ac_btime64;\n\t__u64 compact_count;\n\t__u64 compact_delay_total;\n\t__u32 ac_tgid;\n\t__u64 ac_tgetime;\n\t__u64 ac_exe_dev;\n\t__u64 ac_exe_inode;\n\t__u64 wpcopy_count;\n\t__u64 wpcopy_delay_total;\n\t__u64 irq_count;\n\t__u64 irq_delay_total;\n\t__u64 cpu_delay_max;\n\t__u64 cpu_delay_min;\n\t__u64 blkio_delay_max;\n\t__u64 blkio_delay_min;\n\t__u64 swapin_delay_max;\n\t__u64 swapin_delay_min;\n\t__u64 freepages_delay_max;\n\t__u64 freepages_delay_min;\n\t__u64 thrashing_delay_max;\n\t__u64 thrashing_delay_min;\n\t__u64 compact_delay_max;\n\t__u64 compact_delay_min;\n\t__u64 wpcopy_delay_max;\n\t__u64 wpcopy_delay_min;\n\t__u64 irq_delay_max;\n\t__u64 irq_delay_min;\n\tstruct __kernel_timespec cpu_delay_max_ts;\n\tstruct __kernel_timespec blkio_delay_max_ts;\n\tstruct __kernel_timespec swapin_delay_max_ts;\n\tstruct __kernel_timespec freepages_delay_max_ts;\n\tstruct __kernel_timespec thrashing_delay_max_ts;\n\tstruct __kernel_timespec compact_delay_max_ts;\n\tstruct __kernel_timespec wpcopy_delay_max_ts;\n\tstruct __kernel_timespec irq_delay_max_ts;\n};\n\nstruct tc_act_pernet_id {\n\tstruct list_head list;\n\tunsigned int id;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tstruct tcf_t tcfa_tm;\n\tlong: 64;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n\tlong: 64;\n};\n\nstruct tc_action_net {\n\tstruct tcf_idrinfo *idrinfo;\n\tconst struct tc_action_ops *ops;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_bind_class_args {\n\tstruct qdisc_walker w;\n\tlong unsigned int new_cl;\n\tu32 portid;\n\tu32 clid;\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_fifo_qopt {\n\t__u32 limit;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_fifo_qopt_offload {\n\tenum tc_fifo_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t};\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_pedit_key {\n\t__u32 mask;\n\t__u32 val;\n\t__u32 off;\n\t__u32 at;\n\t__u32 offmask;\n\t__u32 shift;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_root_qopt_offload {\n\tenum tc_root_command command;\n\tu32 handle;\n\tbool ingress;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tcamsg {\n\tunsigned char tca_family;\n\tunsigned char tca__pad1;\n\tshort unsigned int tca__pad2;\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcf_bind_args {\n\tstruct tcf_walker w;\n\tlong unsigned int base;\n\tlong unsigned int cl;\n\tu32 classid;\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\ntypedef void tcf_chain_head_change_t(struct tcf_proto *, void *);\n\nstruct tcf_block_ext_info {\n\tenum flow_block_binder_type binder_type;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n\tu32 block_index;\n};\n\nstruct tcf_block_owner_item {\n\tstruct list_head list;\n\tstruct Qdisc *q;\n\tenum flow_block_binder_type binder_type;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_chain_info {\n\tstruct tcf_proto **pprev;\n\tstruct tcf_proto *next;\n};\n\nstruct tcf_dump_args {\n\tstruct tcf_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct tcf_block *block;\n\tstruct Qdisc *q;\n\tu32 parent;\n\tbool terse_dump;\n};\n\nstruct tcf_ematch_ops;\n\nstruct tcf_ematch {\n\tstruct tcf_ematch_ops *ops;\n\tlong unsigned int data;\n\tunsigned int datalen;\n\tu16 matchid;\n\tu16 flags;\n\tstruct net *net;\n};\n\nstruct tcf_ematch_hdr {\n\t__u16 matchid;\n\t__u16 kind;\n\t__u16 flags;\n\t__u16 pad;\n};\n\nstruct tcf_pkt_info;\n\nstruct tcf_ematch_ops {\n\tint kind;\n\tint datalen;\n\tint (*change)(struct net *, void *, int, struct tcf_ematch *);\n\tint (*match)(struct sk_buff *, struct tcf_ematch *, struct tcf_pkt_info *);\n\tvoid (*destroy)(struct tcf_ematch *);\n\tint (*dump)(struct sk_buff *, struct tcf_ematch *);\n\tstruct module *owner;\n\tstruct list_head link;\n};\n\nunion tcf_exts_miss_cookie {\n\tstruct {\n\t\tu32 miss_cookie_base;\n\t\tu32 act_index;\n\t};\n\tu64 miss_cookie;\n};\n\nstruct tcf_exts_miss_cookie_node {\n\tconst struct tcf_chain *chain;\n\tconst struct tcf_proto *tp;\n\tconst struct tcf_exts *exts;\n\tu32 chain_index;\n\tu32 tp_prio;\n\tu32 handle;\n\tu32 miss_cookie_base;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_filter_chain_list_item {\n\tstruct list_head list;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_net {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n};\n\nstruct tcf_pedit_parms;\n\nstruct tcf_pedit {\n\tstruct tc_action common;\n\tstruct tcf_pedit_parms *parms;\n\tlong: 64;\n};\n\nstruct tcf_pedit_key_ex {\n\tenum pedit_header_type htype;\n\tenum pedit_cmd cmd;\n};\n\nstruct tcf_pedit_parms {\n\tstruct tc_pedit_key *tcfp_keys;\n\tstruct tcf_pedit_key_ex *tcfp_keys_ex;\n\tint action;\n\tu32 tcfp_off_max_hint;\n\tunsigned char tcfp_nkeys;\n\tunsigned char tcfp_flags;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_pkt_info {\n\tunsigned char *ptr;\n\tint nexthdr;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_qevent {\n\tstruct tcf_block *block;\n\tstruct tcf_block_ext_info info;\n\tstruct tcf_proto *filter_chain;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\t__u32 (*cookie_init_seq)(const struct sk_buff *, __u16 *);\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t} header;\n\t};\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 ae: 1;\n\t__u16 res1: 3;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n};\n\nstruct tdp_iter {\n\tgfn_t next_last_level_gfn;\n\tgfn_t yielded_gfn;\n\ttdp_ptep_t pt_path[5];\n\ttdp_ptep_t sptep;\n\tgfn_t gfn;\n\tgfn_t gfn_bits;\n\tint root_level;\n\tint min_level;\n\tint level;\n\tint as_id;\n\tu64 old_spte;\n\tbool valid;\n\tbool yielded;\n};\n\nstruct temp_masks {\n\tu32 tcc_offset;\n\tu32 digital_readout;\n\tu32 pkg_digital_readout;\n};\n\nstruct temp_regset {\n\tstruct guc_mmio_reg *registers;\n\tstruct guc_mmio_reg *storage;\n\tu32 storage_used;\n\tu32 storage_max;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[8];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nunion text_poke_insn {\n\tu8 text[5];\n\tstruct {\n\t\tu8 opcode;\n\t\ts32 disp;\n\t} __attribute__((packed));\n};\n\nstruct tfp410_priv {\n\tbool quiet;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct thermal_attr {\n\tstruct device_attribute attr;\n\tchar name[20];\n};\n\ntypedef struct thermal_cooling_device *class_cooling_dev_t;\n\nstruct thermal_cooling_device_ops;\n\nstruct thermal_cooling_device {\n\tint id;\n\tconst char *type;\n\tlong unsigned int max_state;\n\tstruct device device;\n\tstruct device_node *np;\n\tvoid *devdata;\n\tvoid *stats;\n\tconst struct thermal_cooling_device_ops *ops;\n\tbool updated;\n\tstruct mutex lock;\n\tstruct list_head thermal_instances;\n\tstruct list_head node;\n};\n\nstruct thermal_cooling_device_ops {\n\tint (*get_max_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*get_cur_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*set_cur_state)(struct thermal_cooling_device *, long unsigned int);\n\tint (*get_requested_power)(struct thermal_cooling_device *, u32 *);\n\tint (*state2power)(struct thermal_cooling_device *, long unsigned int, u32 *);\n\tint (*power2state)(struct thermal_cooling_device *, u32, long unsigned int *);\n};\n\nstruct thermal_genl_cpu_caps {\n\tint cpu;\n\tint performance;\n\tint efficiency;\n};\n\nstruct thermal_genl_notify {\n\tint mcgrp;\n};\n\nstruct thermal_trip;\n\nstruct thermal_governor {\n\tconst char *name;\n\tint (*bind_to_tz)(struct thermal_zone_device *);\n\tvoid (*unbind_from_tz)(struct thermal_zone_device *);\n\tvoid (*trip_crossed)(struct thermal_zone_device *, const struct thermal_trip *, bool);\n\tvoid (*manage)(struct thermal_zone_device *);\n\tvoid (*update_tz)(struct thermal_zone_device *, enum thermal_notify_event);\n\tstruct list_head governor_list;\n};\n\nstruct thermal_hwmon_attr {\n\tstruct device_attribute attr;\n\tchar name[16];\n};\n\nstruct thermal_hwmon_device {\n\tchar type[20];\n\tstruct device *device;\n\tint count;\n\tstruct list_head tz_list;\n\tstruct list_head node;\n};\n\nstruct thermal_hwmon_temp {\n\tstruct list_head hwmon_node;\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_hwmon_attr temp_input;\n\tstruct thermal_hwmon_attr temp_crit;\n};\n\nstruct thermal_instance {\n\tint id;\n\tchar name[20];\n\tstruct thermal_cooling_device *cdev;\n\tconst struct thermal_trip *trip;\n\tbool initialized;\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tlong unsigned int target;\n\tchar attr_name[20];\n\tstruct device_attribute attr;\n\tchar weight_attr_name[20];\n\tstruct device_attribute weight_attr;\n\tstruct list_head trip_node;\n\tstruct list_head cdev_node;\n\tunsigned int weight;\n\tbool upper_no_limit;\n};\n\nstruct thermal_state {\n\tstruct _thermal_state core_throttle;\n\tstruct _thermal_state core_power_limit;\n\tstruct _thermal_state package_throttle;\n\tstruct _thermal_state package_power_limit;\n\tstruct _thermal_state core_thresh0;\n\tstruct _thermal_state core_thresh1;\n\tstruct _thermal_state pkg_thresh0;\n\tstruct _thermal_state pkg_thresh1;\n};\n\nstruct thermal_trip {\n\tint temperature;\n\tint hysteresis;\n\tenum thermal_trip_type type;\n\tu8 flags;\n\tvoid *priv;\n};\n\nstruct thermal_trip_attrs {\n\tstruct thermal_attr type;\n\tstruct thermal_attr temp;\n\tstruct thermal_attr hyst;\n};\n\nstruct thermal_trip_desc {\n\tstruct thermal_trip trip;\n\tstruct thermal_trip_attrs trip_attrs;\n\tstruct list_head list_node;\n\tstruct list_head thermal_instances;\n\tint threshold;\n};\n\ntypedef struct thermal_zone_device *class_thermal_zone_get_by_id_t;\n\ntypedef struct thermal_zone_device *class_thermal_zone_reverse_t;\n\ntypedef struct thermal_zone_device *class_thermal_zone_t;\n\nstruct thermal_zone_device_ops {\n\tbool (*should_bind)(struct thermal_zone_device *, const struct thermal_trip *, struct thermal_cooling_device *, struct cooling_spec *);\n\tint (*get_temp)(struct thermal_zone_device *, int *);\n\tint (*set_trips)(struct thermal_zone_device *, int, int);\n\tint (*change_mode)(struct thermal_zone_device *, enum thermal_device_mode);\n\tint (*set_trip_temp)(struct thermal_zone_device *, const struct thermal_trip *, int);\n\tint (*get_crit_temp)(struct thermal_zone_device *, int *);\n\tint (*set_emul_temp)(struct thermal_zone_device *, int);\n\tint (*get_trend)(struct thermal_zone_device *, const struct thermal_trip *, enum thermal_trend *);\n\tvoid (*hot)(struct thermal_zone_device *);\n\tvoid (*critical)(struct thermal_zone_device *);\n};\n\nstruct thermal_zone_params;\n\nstruct thermal_zone_device {\n\tint id;\n\tchar type[20];\n\tstruct device device;\n\tstruct completion removal;\n\tstruct completion resume;\n\tstruct attribute_group trips_attribute_group;\n\tstruct list_head trips_high;\n\tstruct list_head trips_reached;\n\tstruct list_head trips_invalid;\n\tenum thermal_device_mode mode;\n\tvoid *devdata;\n\tint num_trips;\n\tlong unsigned int passive_delay_jiffies;\n\tlong unsigned int polling_delay_jiffies;\n\tlong unsigned int recheck_delay_jiffies;\n\tint temperature;\n\tint last_temperature;\n\tint emul_temperature;\n\tint passive;\n\tint prev_low_trip;\n\tint prev_high_trip;\n\tstruct thermal_zone_device_ops ops;\n\tstruct thermal_zone_params *tzp;\n\tstruct thermal_governor *governor;\n\tvoid *governor_data;\n\tstruct ida ida;\n\tstruct mutex lock;\n\tstruct list_head node;\n\tstruct delayed_work poll_queue;\n\tenum thermal_notify_event notify_event;\n\tu8 state;\n\tstruct list_head user_thresholds;\n\tstruct thermal_trip_desc trips[0];\n};\n\nstruct thermal_zone_params {\n\tconst char *governor_name;\n\tbool no_hwmon;\n\tu32 sustainable_power;\n\ts32 k_po;\n\ts32 k_pu;\n\ts32 k_i;\n\ts32 k_d;\n\ts32 integral_cutoff;\n\tint slope;\n\tint offset;\n};\n\nstruct threshold_block;\n\nstruct thresh_restart {\n\tstruct threshold_block *b;\n\tint set_lvt_off;\n\tint lvt_off;\n\tu16 old_limit;\n};\n\nstruct threshold_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct threshold_block *, char *);\n\tssize_t (*store)(struct threshold_block *, const char *, size_t);\n};\n\nstruct threshold_bank {\n\tstruct kobject *kobj;\n\tstruct list_head miscj;\n};\n\nstruct threshold_block {\n\tunsigned int block;\n\tunsigned int bank;\n\tunsigned int cpu;\n\tu32 address;\n\tbool interrupt_enable;\n\tbool interrupt_capable;\n\tu16 threshold_limit;\n\tstruct kobject kobj;\n\tstruct list_head miscj;\n};\n\nstruct throttling_tstate {\n\tunsigned int cpu;\n\tint target_state;\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[9];\n\tstruct hlist_head vectors[576];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timerlat_entry {\n\tstruct trace_entry ent;\n\tunsigned int seqnum;\n\tint context;\n\tu64 timer_latency;\n};\n\nstruct timestamp_event_queue {\n\tstruct ptp_extts_event buf[128];\n\tint head;\n\tint tail;\n\tspinlock_t lock;\n\tstruct list_head qlist;\n\tlong unsigned int *mask;\n\tstruct dentry *debugfs_instance;\n\tstruct debugfs_u32_array dfs_bitmap;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tstruct tk_read_base base[2];\n};\n\nstruct tlb_context {\n\tu64 ctx_id;\n\tu64 tlb_gen;\n};\n\nstruct tlb_state {\n\tstruct mm_struct *loaded_mm;\n\tunion {\n\t\tstruct mm_struct *last_user_mm;\n\t\tlong unsigned int last_user_mm_spec;\n\t};\n\tu16 loaded_mm_asid;\n\tu16 next_asid;\n\tbool invalidate_other;\n\tshort unsigned int user_pcid_flush_mask;\n\tlong unsigned int cr4;\n\tstruct tlb_context ctxs[6];\n};\n\nstruct tlb_state_shared {\n\tbool is_lazy;\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tu64 now;\n\tbool check;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct topa {\n\tstruct list_head list;\n\tu64 offset;\n\tsize_t size;\n\tint last;\n\tunsigned int z_count;\n};\n\nstruct topa_entry {\n\tu64 end: 1;\n\tu64 rsvd0: 1;\n\tu64 intr: 1;\n\tu64 rsvd1: 1;\n\tu64 stop: 1;\n\tu64 rsvd2: 1;\n\tu64 size: 4;\n\tu64 rsvd3: 2;\n\tu64 base: 40;\n\tu64 rsvd4: 12;\n};\n\nstruct topa_page {\n\tstruct topa_entry table[507];\n\tstruct topa topa;\n};\n\nstruct topo_scan {\n\tstruct cpuinfo_x86 *c;\n\tunsigned int dom_shifts[7];\n\tunsigned int dom_ncpus[7];\n\tunsigned int ebx1_nproc_shift;\n\tu16 amd_nodes_per_pkg;\n\tu16 amd_node_id;\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nstruct tp_transition_snapshot {\n\tlong unsigned int rcu;\n\tlong unsigned int srcu_gp;\n\tbool ongoing;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct trace_module_delta;\n\nstruct trace_pid_list;\n\nstruct tracer_flags;\n\nstruct trace_options;\n\nstruct trace_func_repeats;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tstruct array_buffer array_buffer;\n\tunsigned int mapped;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_size;\n\tchar *range_name;\n\tlong int text_delta;\n\tstruct trace_module_delta *module_delta;\n\tvoid *scratch;\n\tint scratch_size;\n\tint buffer_disabled;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint sys_refcount_enter;\n\tint sys_refcount_exit;\n\tstruct trace_event_file *enter_syscall_files[472];\n\tstruct trace_event_file *exit_syscall_files[472];\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tstruct tracer_flags *current_trace_flags;\n\tu64 trace_flags;\n\tunsigned char trace_flags_index[64];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tconst char *system_names;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct eventfs_inode *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct list_head marker_list;\n\tstruct list_head tracers;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tcpumask_var_t pipe_cpumask;\n\tint ref;\n\tint trace_ref;\n\tstruct list_head mod_events;\n\tstruct ftrace_ops *ops;\n\tstruct trace_pid_list *function_pids;\n\tstruct trace_pid_list *function_no_pids;\n\tstruct fgraph_ops *gops;\n\tstruct list_head func_probes;\n\tstruct list_head mod_trace;\n\tstruct list_head mod_notrace;\n\tint function_enabled;\n\tint no_filter_buffering_ref;\n\tunsigned int syscall_buf_sz;\n\tstruct list_head hist_vars;\n\tstruct trace_func_repeats *last_func_repeats;\n\tbool ring_buffer_expanded;\n};\n\nstruct trace_array_cpu {\n\tlocal_t disabled;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tint ftrace_ignore_pid;\n\tbool ignore_pid;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\ntypedef struct trace_buffer *class_ring_buffer_nest_t;\n\nstruct trace_buffer {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tatomic_t resizing;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)(void);\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_end;\n\tstruct ring_buffer_meta *meta;\n\tunsigned int subbuf_size;\n\tunsigned int subbuf_order;\n\tunsigned int max_data_size;\n};\n\nstruct trace_buffer_meta {\n\t__u32 meta_page_size;\n\t__u32 meta_struct_len;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tstruct {\n\t\t__u64 lost_events;\n\t\t__u32 id;\n\t\t__u32 read;\n\t} reader;\n\t__u64 flags;\n\t__u64 entries;\n\t__u64 overrun;\n\t__u64 read;\n\t__u64 Reserved1;\n\t__u64 Reserved2;\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct trace_probe_event;\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_entry_arg *entry_arg;\n\tstruct probe_arg args[0];\n};\n\nstruct trace_eprobe {\n\tconst char *event_system;\n\tconst char *event_name;\n\tchar *filter_str;\n\tstruct trace_event_call *event;\n\tstruct dyn_event devent;\n\tstruct trace_probe tp;\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tunsigned int trace_ctx;\n\tstruct pt_regs *regs;\n};\n\nstruct trace_event_class;\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tconst char *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tunion {\n\t\tvoid *module;\n\t\tatomic_t refcnt;\n\t};\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct trace_event_fields;\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_event_data_offsets_9p_client_req {};\n\nstruct trace_event_data_offsets_9p_client_res {};\n\nstruct trace_event_data_offsets_9p_fid_ref {};\n\nstruct trace_event_data_offsets_9p_protocol_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_alarm_class {};\n\nstruct trace_event_data_offsets_alarmtimer_suspend {};\n\nstruct trace_event_data_offsets_alloc_vmap_area {};\n\nstruct trace_event_data_offsets_amd_pstate_epp_perf {};\n\nstruct trace_event_data_offsets_amd_pstate_perf {};\n\nstruct trace_event_data_offsets_ata_bmdma_status {};\n\nstruct trace_event_data_offsets_ata_eh_action_template {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy_qc {};\n\nstruct trace_event_data_offsets_ata_exec_command_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_begin_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_end_template {};\n\nstruct trace_event_data_offsets_ata_port_eh_begin_template {};\n\nstruct trace_event_data_offsets_ata_qc_complete_template {};\n\nstruct trace_event_data_offsets_ata_qc_issue_template {};\n\nstruct trace_event_data_offsets_ata_sff_hsm_template {};\n\nstruct trace_event_data_offsets_ata_sff_template {};\n\nstruct trace_event_data_offsets_ata_tf_load {};\n\nstruct trace_event_data_offsets_ata_transfer_data_template {};\n\nstruct trace_event_data_offsets_azx_get_position {};\n\nstruct trace_event_data_offsets_azx_pcm {};\n\nstruct trace_event_data_offsets_azx_pcm_trigger {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_blkdev_zone_mgmt {};\n\nstruct trace_event_data_offsets_block_bio {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_completion {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_zwplug {};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\nstruct trace_event_data_offsets_bpf_trace_printk {\n\tu32 bpf_string;\n\tconst void *bpf_string_ptr_;\n};\n\nstruct trace_event_data_offsets_bpf_trigger_tp {};\n\nstruct trace_event_data_offsets_bpf_xdp_link_attach_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_tag_flush {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_tag_log {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_cap_capable {};\n\nstruct trace_event_data_offsets_cdev_update {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tconst void *dst_path_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_rstat {};\n\nstruct trace_event_data_offsets_check_mmio_spte {};\n\nstruct trace_event_data_offsets_compact_retry {};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_contention_begin {};\n\nstruct trace_event_data_offsets_contention_end {};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_cpu_idle_miss {};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_csd_function {};\n\nstruct trace_event_data_offsets_csd_queue_cpu {};\n\nstruct trace_event_data_offsets_ctime {};\n\nstruct trace_event_data_offsets_ctime_ns_xchg {};\n\nstruct trace_event_data_offsets_dax_pmd_fault_class {};\n\nstruct trace_event_data_offsets_dax_pmd_load_hole_class {};\n\nstruct trace_event_data_offsets_dax_pte_fault_class {};\n\nstruct trace_event_data_offsets_dax_writeback_one {};\n\nstruct trace_event_data_offsets_dax_writeback_range_class {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_end {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_start {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 parent;\n\tconst void *parent_ptr_;\n\tu32 pm_ops;\n\tconst void *pm_ops_ptr_;\n};\n\nstruct trace_event_data_offsets_devres {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_attach_dev {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_fd {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence_unsignaled {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg_err {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_single {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 addrs;\n\tconst void *addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dql_stall_detected {};\n\nstruct trace_event_data_offsets_drm_vblank_event {};\n\nstruct trace_event_data_offsets_drm_vblank_event_delivered {};\n\nstruct trace_event_data_offsets_drm_vblank_event_queued {};\n\nstruct trace_event_data_offsets_emulate_vsyscall {};\n\nstruct trace_event_data_offsets_error_report_template {};\n\nstruct trace_event_data_offsets_exceptions {};\n\nstruct trace_event_data_offsets_exit_mmap {};\n\nstruct trace_event_data_offsets_fast_page_fault {};\n\nstruct trace_event_data_offsets_fib_table_lookup {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_fill_mg_cmtime {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_free_vmap_area_noflush {};\n\nstruct trace_event_data_offsets_fuse_request_end {};\n\nstruct trace_event_data_offsets_fuse_request_send {};\n\nstruct trace_event_data_offsets_g4x_wm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_guest_halt_poll_ns {};\n\nstruct trace_event_data_offsets_handle_mmio_page_fault {};\n\nstruct trace_event_data_offsets_hda_get_response {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_hda_pm {};\n\nstruct trace_event_data_offsets_hda_send_cmd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_hda_unsol_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_hdac_stream {};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_setup {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hugetlbfs__inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_alloc_inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_fallocate {};\n\nstruct trace_event_data_offsets_hugetlbfs_setattr {\n\tu32 d_name;\n\tconst void *d_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_class {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_show_string {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_read {};\n\nstruct trace_event_data_offsets_i2c_reply {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_result {};\n\nstruct trace_event_data_offsets_i2c_write {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i915_context {};\n\nstruct trace_event_data_offsets_i915_gem_evict {};\n\nstruct trace_event_data_offsets_i915_gem_evict_node {};\n\nstruct trace_event_data_offsets_i915_gem_evict_vm {};\n\nstruct trace_event_data_offsets_i915_gem_object {};\n\nstruct trace_event_data_offsets_i915_gem_object_create {};\n\nstruct trace_event_data_offsets_i915_gem_object_fault {};\n\nstruct trace_event_data_offsets_i915_gem_object_pread {};\n\nstruct trace_event_data_offsets_i915_gem_object_pwrite {};\n\nstruct trace_event_data_offsets_i915_gem_shrink {};\n\nstruct trace_event_data_offsets_i915_ppgtt {};\n\nstruct trace_event_data_offsets_i915_reg_rw {};\n\nstruct trace_event_data_offsets_i915_request {};\n\nstruct trace_event_data_offsets_i915_request_queue {};\n\nstruct trace_event_data_offsets_i915_request_wait_begin {};\n\nstruct trace_event_data_offsets_i915_vma_bind {};\n\nstruct trace_event_data_offsets_i915_vma_unbind {};\n\nstruct trace_event_data_offsets_icmp_send {};\n\nstruct trace_event_data_offsets_inet_sk_error_report {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n\tconst void *level_ptr_;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_intel_cpu_fifo_underrun {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_crtc_flip_done {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_crtc_vblank_work_end {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_crtc_vblank_work_start {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_fbc_activate {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_fbc_deactivate {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_fbc_nuke {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_frontbuffer_flush {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_frontbuffer_invalidate {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_memory_cxsr {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pch_fifo_underrun {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_crc {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_disable {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_enable {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_scaler_update_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_update_end {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_update_start {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_update_vblank_evaded {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_async_flip {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_disable_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_scaler_update_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_update_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_update_noarm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_scaler_disable_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_cqe_overflow {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_defer {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_fail_link {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_local_work_run {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_req_failed {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_short_write {};\n\nstruct trace_event_data_offsets_io_uring_submit_req {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_add {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_work_run {};\n\nstruct trace_event_data_offsets_iocg_inuse_update {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_ioc_vrate_adj {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_iocg_forgive_debt {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_iocg_state {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iomap_add_to_ioend {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_dio_complete {};\n\nstruct trace_event_data_offsets_iomap_dio_rw_begin {};\n\nstruct trace_event_data_offsets_iomap_iter {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_send_cpu {};\n\nstruct trace_event_data_offsets_ipi_send_cpumask {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_irq_matrix_cpu {};\n\nstruct trace_event_data_offsets_irq_matrix_global {};\n\nstruct trace_event_data_offsets_irq_matrix_global_update {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\nstruct trace_event_data_offsets_kfree {};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_kmalloc {};\n\nstruct trace_event_data_offsets_kmem_cache_alloc {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kmem_cache_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kvm_ack_irq {};\n\nstruct trace_event_data_offsets_kvm_age_hva {};\n\nstruct trace_event_data_offsets_kvm_apic {};\n\nstruct trace_event_data_offsets_kvm_apic_accept_irq {};\n\nstruct trace_event_data_offsets_kvm_apic_ipi {};\n\nstruct trace_event_data_offsets_kvm_apicv_accept_irq {};\n\nstruct trace_event_data_offsets_kvm_apicv_inhibit_changed {};\n\nstruct trace_event_data_offsets_kvm_async_get_page_class {};\n\nstruct trace_event_data_offsets_kvm_async_pf_completed {};\n\nstruct trace_event_data_offsets_kvm_async_pf_nopresent_ready {};\n\nstruct trace_event_data_offsets_kvm_avic_doorbell {};\n\nstruct trace_event_data_offsets_kvm_avic_ga_log {};\n\nstruct trace_event_data_offsets_kvm_avic_incomplete_ipi {};\n\nstruct trace_event_data_offsets_kvm_avic_kick_vcpu_slowpath {};\n\nstruct trace_event_data_offsets_kvm_avic_unaccelerated_access {};\n\nstruct trace_event_data_offsets_kvm_cpuid {};\n\nstruct trace_event_data_offsets_kvm_cr {};\n\nstruct trace_event_data_offsets_kvm_dirty_ring_exit {};\n\nstruct trace_event_data_offsets_kvm_dirty_ring_push {};\n\nstruct trace_event_data_offsets_kvm_dirty_ring_reset {};\n\nstruct trace_event_data_offsets_kvm_emulate_insn {};\n\nstruct trace_event_data_offsets_kvm_entry {};\n\nstruct trace_event_data_offsets_kvm_eoi {};\n\nstruct trace_event_data_offsets_kvm_exit {};\n\nstruct trace_event_data_offsets_kvm_fast_mmio {};\n\nstruct trace_event_data_offsets_kvm_fpu {};\n\nstruct trace_event_data_offsets_kvm_halt_poll_ns {};\n\nstruct trace_event_data_offsets_kvm_hv_flush_tlb {};\n\nstruct trace_event_data_offsets_kvm_hv_flush_tlb_ex {};\n\nstruct trace_event_data_offsets_kvm_hv_hypercall {};\n\nstruct trace_event_data_offsets_kvm_hv_hypercall_done {};\n\nstruct trace_event_data_offsets_kvm_hv_notify_acked_sint {};\n\nstruct trace_event_data_offsets_kvm_hv_send_ipi {};\n\nstruct trace_event_data_offsets_kvm_hv_send_ipi_ex {};\n\nstruct trace_event_data_offsets_kvm_hv_stimer_callback {};\n\nstruct trace_event_data_offsets_kvm_hv_stimer_cleanup {};\n\nstruct trace_event_data_offsets_kvm_hv_stimer_expiration {};\n\nstruct trace_event_data_offsets_kvm_hv_stimer_set_config {};\n\nstruct trace_event_data_offsets_kvm_hv_stimer_set_count {};\n\nstruct trace_event_data_offsets_kvm_hv_stimer_start_one_shot {};\n\nstruct trace_event_data_offsets_kvm_hv_stimer_start_periodic {};\n\nstruct trace_event_data_offsets_kvm_hv_syndbg_get_msr {};\n\nstruct trace_event_data_offsets_kvm_hv_syndbg_set_msr {};\n\nstruct trace_event_data_offsets_kvm_hv_synic_send_eoi {};\n\nstruct trace_event_data_offsets_kvm_hv_synic_set_irq {};\n\nstruct trace_event_data_offsets_kvm_hv_synic_set_msr {};\n\nstruct trace_event_data_offsets_kvm_hv_timer_state {};\n\nstruct trace_event_data_offsets_kvm_hypercall {};\n\nstruct trace_event_data_offsets_kvm_inj_exception {};\n\nstruct trace_event_data_offsets_kvm_inj_virq {};\n\nstruct trace_event_data_offsets_kvm_invlpga {};\n\nstruct trace_event_data_offsets_kvm_ioapic_delayed_eoi_inj {};\n\nstruct trace_event_data_offsets_kvm_ioapic_set_irq {};\n\nstruct trace_event_data_offsets_kvm_mmio {};\n\nstruct trace_event_data_offsets_kvm_mmu_get_page {};\n\nstruct trace_event_data_offsets_kvm_mmu_page_class {};\n\nstruct trace_event_data_offsets_kvm_mmu_pagetable_walk {};\n\nstruct trace_event_data_offsets_kvm_mmu_paging_element {};\n\nstruct trace_event_data_offsets_kvm_mmu_set_bit_class {};\n\nstruct trace_event_data_offsets_kvm_mmu_set_spte {};\n\nstruct trace_event_data_offsets_kvm_mmu_split_huge_page {};\n\nstruct trace_event_data_offsets_kvm_mmu_spte_requested {};\n\nstruct trace_event_data_offsets_kvm_mmu_walker_error {};\n\nstruct trace_event_data_offsets_kvm_mmu_zap_all_fast {};\n\nstruct trace_event_data_offsets_kvm_msi_set_irq {};\n\nstruct trace_event_data_offsets_kvm_msr {};\n\nstruct trace_event_data_offsets_kvm_nested_intercepts {};\n\nstruct trace_event_data_offsets_kvm_nested_intr_vmexit {};\n\nstruct trace_event_data_offsets_kvm_nested_vmenter {};\n\nstruct trace_event_data_offsets_kvm_nested_vmenter_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_kvm_nested_vmexit {};\n\nstruct trace_event_data_offsets_kvm_nested_vmexit_inject {};\n\nstruct trace_event_data_offsets_kvm_page_fault {};\n\nstruct trace_event_data_offsets_kvm_pi_irte_update {};\n\nstruct trace_event_data_offsets_kvm_pic_set_irq {};\n\nstruct trace_event_data_offsets_kvm_pio {};\n\nstruct trace_event_data_offsets_kvm_ple_window_update {};\n\nstruct trace_event_data_offsets_kvm_pml_full {};\n\nstruct trace_event_data_offsets_kvm_pv_eoi {};\n\nstruct trace_event_data_offsets_kvm_pv_tlb_flush {};\n\nstruct trace_event_data_offsets_kvm_pvclock_update {};\n\nstruct trace_event_data_offsets_kvm_rmp_fault {};\n\nstruct trace_event_data_offsets_kvm_set_irq {};\n\nstruct trace_event_data_offsets_kvm_skinit {};\n\nstruct trace_event_data_offsets_kvm_smm_transition {};\n\nstruct trace_event_data_offsets_kvm_tdp_mmu_spte_changed {};\n\nstruct trace_event_data_offsets_kvm_test_age_hva {};\n\nstruct trace_event_data_offsets_kvm_track_tsc {};\n\nstruct trace_event_data_offsets_kvm_unmap_hva_range {};\n\nstruct trace_event_data_offsets_kvm_update_master_clock {};\n\nstruct trace_event_data_offsets_kvm_userspace_exit {};\n\nstruct trace_event_data_offsets_kvm_vcpu_wakeup {};\n\nstruct trace_event_data_offsets_kvm_vmgexit_enter {};\n\nstruct trace_event_data_offsets_kvm_vmgexit_exit {};\n\nstruct trace_event_data_offsets_kvm_vmgexit_msr_protocol_enter {};\n\nstruct trace_event_data_offsets_kvm_vmgexit_msr_protocol_exit {};\n\nstruct trace_event_data_offsets_kvm_wait_lapic_expire {};\n\nstruct trace_event_data_offsets_kvm_write_tsc_offset {};\n\nstruct trace_event_data_offsets_kvm_xen_hypercall {};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\nstruct trace_event_data_offsets_lock {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_lock_acquire {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_ma_op {};\n\nstruct trace_event_data_offsets_ma_read {};\n\nstruct trace_event_data_offsets_ma_write {};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_mark_mmio_spte {};\n\nstruct trace_event_data_offsets_mark_victim {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_mce_record {\n\tu32 v_data;\n\tconst void *v_data_ptr_;\n};\n\nstruct trace_event_data_offsets_mdio_access {};\n\nstruct trace_event_data_offsets_mei_pci_cfg_read {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 reg;\n\tconst void *reg_ptr_;\n};\n\nstruct trace_event_data_offsets_mei_reg_read {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 reg;\n\tconst void *reg_ptr_;\n};\n\nstruct trace_event_data_offsets_mei_reg_write {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 reg;\n\tconst void *reg_ptr_;\n};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_migration_pte {};\n\nstruct trace_event_data_offsets_mm_calculate_totalreserve_pages {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_filemap_fault {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache_range {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\nstruct trace_event_data_offsets_mm_migrate_pages_start {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_lowmem_reserve {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 upper_name;\n\tconst void *upper_name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_wmarks {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_clear_hopeless {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_reclaim_fail {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\nstruct trace_event_data_offsets_mm_vmscan_reclaim_pages {};\n\nstruct trace_event_data_offsets_mm_vmscan_throttled {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_write_folio {};\n\nstruct trace_event_data_offsets_mmap_lock {};\n\nstruct trace_event_data_offsets_mmap_lock_acquire_returned {};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_msr_trace_class {};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_netfs_collect {};\n\nstruct trace_event_data_offsets_netfs_collect_folio {};\n\nstruct trace_event_data_offsets_netfs_collect_gap {};\n\nstruct trace_event_data_offsets_netfs_collect_sreq {};\n\nstruct trace_event_data_offsets_netfs_collect_state {};\n\nstruct trace_event_data_offsets_netfs_collect_stream {};\n\nstruct trace_event_data_offsets_netfs_copy2cache {};\n\nstruct trace_event_data_offsets_netfs_failure {};\n\nstruct trace_event_data_offsets_netfs_folio {};\n\nstruct trace_event_data_offsets_netfs_folioq {};\n\nstruct trace_event_data_offsets_netfs_read {};\n\nstruct trace_event_data_offsets_netfs_rreq {};\n\nstruct trace_event_data_offsets_netfs_rreq_ref {};\n\nstruct trace_event_data_offsets_netfs_sreq {};\n\nstruct trace_event_data_offsets_netfs_sreq_ref {};\n\nstruct trace_event_data_offsets_netfs_write {};\n\nstruct trace_event_data_offsets_netfs_write_iter {};\n\nstruct trace_event_data_offsets_netlink_extack {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_nmi_handler {};\n\nstruct trace_event_data_offsets_notifier_info {};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_page_cache_ra_op {};\n\nstruct trace_event_data_offsets_page_cache_ra_order {};\n\nstruct trace_event_data_offsets_page_cache_ra_unbounded {};\n\nstruct trace_event_data_offsets_page_pool_release {};\n\nstruct trace_event_data_offsets_page_pool_state_hold {};\n\nstruct trace_event_data_offsets_page_pool_state_release {};\n\nstruct trace_event_data_offsets_page_pool_update_nid {};\n\nstruct trace_event_data_offsets_pci_hp_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n\tu32 slot;\n\tconst void *slot_ptr_;\n};\n\nstruct trace_event_data_offsets_pcie_link_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_preemptirq_template {};\n\nstruct trace_event_data_offsets_prq_report {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 buff;\n\tconst void *buff_ptr_;\n};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_purge_vmap_area_lazy {};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_enqueue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qi_submit {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kvfree_callback {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_segcb_stats {};\n\nstruct trace_event_data_offsets_rcu_sr_normal {};\n\nstruct trace_event_data_offsets_rcu_stall_warning {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_watching {};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_regcache_drop_region {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regcache_sync {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 status;\n\tconst void *status_ptr_;\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_async {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bool {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bulk {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_reg {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_internal {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_return_int {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_status {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\nstruct trace_event_data_offsets_rtc_alarm_irq_enable {};\n\nstruct trace_event_data_offsets_rtc_irq_set_freq {};\n\nstruct trace_event_data_offsets_rtc_irq_set_state {};\n\nstruct trace_event_data_offsets_rtc_offset_class {};\n\nstruct trace_event_data_offsets_rtc_time_alarm_class {};\n\nstruct trace_event_data_offsets_rtc_timer_class {};\n\nstruct trace_event_data_offsets_sched_ext_bypass_lb {};\n\nstruct trace_event_data_offsets_sched_ext_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_ext_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_end {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_start {};\n\nstruct trace_event_data_offsets_sched_kthread_work_queue_work {};\n\nstruct trace_event_data_offsets_sched_migrate_task {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_move_numa {};\n\nstruct trace_event_data_offsets_sched_numa_pair_template {};\n\nstruct trace_event_data_offsets_sched_pi_setprio {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_prepare_exec {\n\tu32 interp;\n\tconst void *interp_ptr_;\n\tu32 filename;\n\tconst void *filename_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exit {};\n\nstruct trace_event_data_offsets_sched_process_fork {\n\tu32 parent_comm;\n\tconst void *parent_comm_ptr_;\n\tu32 child_comm;\n\tconst void *child_comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_wait {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_skip_cpuset_numa {};\n\nstruct trace_event_data_offsets_sched_skip_vma_numa {};\n\nstruct trace_event_data_offsets_sched_stat_runtime {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_stat_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_sk_data_ready {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_smbus_read {};\n\nstruct trace_event_data_offsets_smbus_reply {};\n\nstruct trace_event_data_offsets_smbus_result {};\n\nstruct trace_event_data_offsets_smbus_write {};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_sock_msg_length {};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_softirq {};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_swiotlb_bounced {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_prctl_unknown {};\n\nstruct trace_event_data_offsets_task_rename {};\n\nstruct trace_event_data_offsets_tasklet {};\n\nstruct trace_event_data_offsets_tcp_ao_event {};\n\nstruct trace_event_data_offsets_tcp_cong_state_set {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_event_skb {};\n\nstruct trace_event_data_offsets_tcp_hash_event {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\nstruct trace_event_data_offsets_tcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_tcp_retransmit_skb {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_send_reset {};\n\nstruct trace_event_data_offsets_tcp_sendmsg_locked {};\n\nstruct trace_event_data_offsets_test_pages_isolated {};\n\nstruct trace_event_data_offsets_thermal_temperature {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_zone_trip {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_tick_stop {};\n\nstruct trace_event_data_offsets_timer_base_idle {};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_tlb_flush {};\n\nstruct trace_event_data_offsets_tmigr_connect_child_parent {};\n\nstruct trace_event_data_offsets_tmigr_connect_cpu_parent {};\n\nstruct trace_event_data_offsets_tmigr_cpugroup {};\n\nstruct trace_event_data_offsets_tmigr_group_and_cpu {};\n\nstruct trace_event_data_offsets_tmigr_group_set {};\n\nstruct trace_event_data_offsets_tmigr_handle_remote {};\n\nstruct trace_event_data_offsets_tmigr_idle {};\n\nstruct trace_event_data_offsets_tmigr_update_events {};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_vcpu_match_mmio {};\n\nstruct trace_event_data_offsets_vector_activate {};\n\nstruct trace_event_data_offsets_vector_alloc {};\n\nstruct trace_event_data_offsets_vector_alloc_managed {};\n\nstruct trace_event_data_offsets_vector_config {};\n\nstruct trace_event_data_offsets_vector_free_moved {};\n\nstruct trace_event_data_offsets_vector_mod {};\n\nstruct trace_event_data_offsets_vector_reserve {};\n\nstruct trace_event_data_offsets_vector_setup {};\n\nstruct trace_event_data_offsets_vector_teardown {};\n\nstruct trace_event_data_offsets_virtio_gpu_cmd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_virtio_transport_alloc_pkt {};\n\nstruct trace_event_data_offsets_virtio_transport_recv_pkt {};\n\nstruct trace_event_data_offsets_vlv_fifo_size {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_vlv_wm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_watchdog_set_timeout {};\n\nstruct trace_event_data_offsets_watchdog_template {};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_queue_work {\n\tu32 workqueue;\n\tconst void *workqueue_ptr_;\n};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_folio_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_x86_fpu {};\n\nstruct trace_event_data_offsets_x86_irq_vector {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst unsigned int is_signed: 1;\n\t\t\tunsigned int needs_test: 1;\n\t\t\tconst int filter_type;\n\t\t\tconst int len;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct eventfs_inode *ei;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\trefcount_t ref;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nstruct trace_event_raw_9p_client_req {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_client_res {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\t__u32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_fid_ref {\n\tstruct trace_entry ent;\n\tint fid;\n\tint refcount;\n\t__u8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_protocol_dump {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u16 tag;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarmtimer_suspend {\n\tstruct trace_entry ent;\n\ts64 expires;\n\tunsigned char alarm_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alloc_vmap_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int vstart;\n\tlong unsigned int vend;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_amd_pstate_epp_perf {\n\tstruct trace_entry ent;\n\tunsigned int cpu_id;\n\tu8 highest_perf;\n\tu8 epp;\n\tu8 min_perf;\n\tu8 max_perf;\n\tbool boost;\n\tbool changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_amd_pstate_perf {\n\tstruct trace_entry ent;\n\tu8 min_perf;\n\tu8 target_perf;\n\tu8 capacity;\n\tlong long unsigned int freq;\n\tlong long unsigned int mperf;\n\tlong long unsigned int aperf;\n\tlong long unsigned int tsc;\n\tunsigned int cpu_id;\n\tbool fast_switch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_bmdma_status {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char host_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_action_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy_qc {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_exec_command_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char feature;\n\tunsigned char hob_nsect;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tlong unsigned int deadline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_end_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tint rc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_port_eh_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_complete_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char status;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char error;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_issue_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tunsigned char proto;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_hsm_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int protocol;\n\tunsigned int hsm_state;\n\tunsigned char dev_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char hsm_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_tf_load {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_transfer_data_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int flags;\n\tunsigned int offset;\n\tunsigned int bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_get_position {\n\tstruct trace_entry ent;\n\tint card;\n\tint idx;\n\tunsigned int pos;\n\tunsigned int delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_pcm {\n\tstruct trace_entry ent;\n\tunsigned char stream_tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_pcm_trigger {\n\tstruct trace_entry ent;\n\tint card;\n\tint idx;\n\tint cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int wb_setpoint;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_blkdev_zone_mgmt {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t nr_sectors;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_completion {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_zwplug {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int zno;\n\tsector_t sector;\n\tunsigned int nr_sectors;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trace_printk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bpf_string;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trigger_tp {\n\tstruct trace_entry ent;\n\tint nonce;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_xdp_link_attach_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_tag_flush {\n\tstruct trace_entry ent;\n\tu32 __data_loc_iommu;\n\tu32 __data_loc_dev;\n\tu16 type;\n\tu16 domain_id;\n\tu32 pasid;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int addr;\n\tlong unsigned int pages;\n\tlong unsigned int mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_tag_log {\n\tstruct trace_entry ent;\n\tu32 __data_loc_iommu;\n\tu32 __data_loc_dev;\n\tu16 type;\n\tu16 domain_id;\n\tu32 pasid;\n\tu32 users;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cap_capable {\n\tstruct trace_entry ent;\n\tconst struct cred *cred;\n\tstruct user_namespace *target_ns;\n\tconst struct user_namespace *capable_ns;\n\tint cap;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cdev_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int target;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_level;\n\tu64 dst_id;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu32 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_rstat {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tint cpu;\n\tbool contended;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_check_mmio_spte {\n\tstruct trace_entry ent;\n\tunsigned int kvm_gen;\n\tunsigned int spte_gen;\n\tu64 spte;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_begin {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_end {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_idle_miss {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool below;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_function {\n\tstruct trace_entry ent;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_queue_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\tu32 ctime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime_ns_xchg {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tu32 gen;\n\tu32 old;\n\tu32 new;\n\tu32 cur;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pmd_fault_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tlong unsigned int pgoff;\n\tlong unsigned int max_pgoff;\n\tdev_t dev;\n\tunsigned int flags;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pmd_load_hole_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tstruct folio *zero_folio;\n\tvoid *radix_entry;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pte_fault_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tlong unsigned int pgoff;\n\tdev_t dev;\n\tunsigned int flags;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_writeback_one {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_writeback_range_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int start_index;\n\tlong unsigned int end_index;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_parent;\n\tu32 __data_loc_pm_ops;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devres {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tstruct device *dev;\n\tconst char *op;\n\tvoid *node;\n\tu32 __data_loc_name;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tgfp_t flags;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tgfp_t flags;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_attach_dev {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tstruct dma_buf_attachment *attach;\n\tbool is_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_fd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence_unsignaled {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 phys_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tint full_nents;\n\tint full_ents;\n\tbool truncated;\n\tu32 __data_loc_phys_addrs;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tint err;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_single {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_addrs;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dql_stall_detected {\n\tstruct trace_entry ent;\n\tshort unsigned int thrs;\n\tunsigned int len;\n\tlong unsigned int last_reap;\n\tlong unsigned int hist_head;\n\tlong unsigned int now;\n\tlong unsigned int hist[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event {\n\tstruct trace_entry ent;\n\tint crtc;\n\tunsigned int seq;\n\tktime_t time;\n\tbool high_prec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event_delivered {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event_queued {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_emulate_vsyscall {\n\tstruct trace_entry ent;\n\tint nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_error_report_template {\n\tstruct trace_entry ent;\n\tenum error_detector error_detector;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exceptions {\n\tstruct trace_entry ent;\n\tlong unsigned int address;\n\tlong unsigned int ip;\n\tlong unsigned int error_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exit_mmap {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tstruct maple_tree *mt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fast_page_fault {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tgpa_t cr2_or_gpa;\n\tu64 error_code;\n\tu64 *sptep;\n\tu64 old_spte;\n\tu64 new_spte;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tchar name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lease *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tlong unsigned int break_time;\n\tlong unsigned int downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int pid;\n\tunsigned int flags;\n\tunsigned char type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fill_mg_cmtime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\ttime64_t mtime_s;\n\tu32 ctime_ns;\n\tu32 mtime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_free_vmap_area_noflush {\n\tstruct trace_entry ent;\n\tlong unsigned int va_start;\n\tlong unsigned int nr_lazy;\n\tlong unsigned int nr_lazy_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fuse_request_end {\n\tstruct trace_entry ent;\n\tdev_t connection;\n\tuint64_t unique;\n\tuint32_t len;\n\tint32_t error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fuse_request_send {\n\tstruct trace_entry ent;\n\tdev_t connection;\n\tuint64_t unique;\n\tenum fuse_opcode opcode;\n\tuint32_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_g4x_wm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu16 primary;\n\tu16 sprite;\n\tu16 cursor;\n\tu16 sr_plane;\n\tu16 sr_cursor;\n\tu16 sr_fbc;\n\tu16 hpll_plane;\n\tu16 hpll_cursor;\n\tu16 hpll_fbc;\n\tbool cxsr;\n\tbool hpll;\n\tbool fbc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_guest_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handle_mmio_page_fault {\n\tstruct trace_entry ent;\n\tu64 addr;\n\tgfn_t gfn;\n\tunsigned int access;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_get_response {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 addr;\n\tu32 res;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_pm {\n\tstruct trace_entry ent;\n\tint dev_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_send_cmd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_unsol_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 res;\n\tu32 res_ex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hdac_stream {\n\tstruct trace_entry ent;\n\tunsigned char stream_tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_setup {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs__inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u16 mode;\n\tloff_t size;\n\tunsigned int nlink;\n\tunsigned int seals;\n\tblkcnt_t blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_alloc_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_fallocate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint mode;\n\tloff_t offset;\n\tloff_t len;\n\tloff_t size;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_setattr {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int d_len;\n\tu32 __data_loc_d_name;\n\tunsigned int ia_valid;\n\tunsigned int ia_mode;\n\tloff_t old_size;\n\tloff_t ia_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_class {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tlong long int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_show_string {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tu32 __data_loc_label;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 nr_msgs;\n\t__s16 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_context {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_gem_context *ctx;\n\tstruct i915_address_space *vm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tu64 size;\n\tu64 align;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict_node {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tu64 start;\n\tu64 size;\n\tlong unsigned int color;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict_vm {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_create {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_fault {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 index;\n\tbool gtt;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_pread {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 offset;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_pwrite {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 offset;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_shrink {\n\tstruct trace_entry ent;\n\tint dev;\n\tlong unsigned int target;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_ppgtt {\n\tstruct trace_entry ent;\n\tstruct i915_address_space *vm;\n\tu32 dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_reg_rw {\n\tstruct trace_entry ent;\n\tu64 val;\n\tu32 reg;\n\tu16 write;\n\tu16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tu32 tail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request_queue {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request_wait_begin {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_vma_bind {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_address_space *vm;\n\tu64 offset;\n\tu64 size;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_vma_unbind {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_address_space *vm;\n\tu64 offset;\n\tu64 size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icmp_send {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint type;\n\tint code;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u16 sport;\n\t__u16 dport;\n\tshort unsigned int ulen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sk_error_report {\n\tstruct trace_entry ent;\n\tint error;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\ntypedef int (*initcall_t)(void);\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_cpu_fifo_underrun {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_crtc_flip_done {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_crtc_vblank_work_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_crtc_vblank_work_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_activate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_name;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_deactivate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_name;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_nuke {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_name;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_frontbuffer_flush {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tunsigned int frontbuffer_bits;\n\tunsigned int origin;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_frontbuffer_invalidate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tunsigned int frontbuffer_bits;\n\tunsigned int origin;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_memory_cxsr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 frame[4];\n\tu32 scanline[4];\n\tbool old;\n\tbool new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pch_fifo_underrun {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_crc {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 crcs[5];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_disable {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 frame[4];\n\tu32 scanline[4];\n\tchar pipe_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_enable {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 frame[4];\n\tu32 scanline[4];\n\tchar pipe_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_scaler_update_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tint scaler_id;\n\tu32 frame;\n\tu32 scanline;\n\tint x;\n\tint y;\n\tint w;\n\tint h;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_vblank_evaded {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_async_flip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tbool async_flip;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_disable_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_scaler_update_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tint scaler_id;\n\tu32 frame;\n\tu32 scanline;\n\tint x;\n\tint y;\n\tint w;\n\tint h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_update_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 format;\n\tint src[4];\n\tint dst[4];\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_update_noarm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 format;\n\tint src[4];\n\tint dst[4];\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_scaler_disable_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tint scaler_id;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint res;\n\tunsigned int cflags;\n\tu64 extra1;\n\tu64 extra2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqe_overflow {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong long unsigned int user_data;\n\ts32 res;\n\tu32 cflags;\n\tvoid *ocqe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tu8 opcode;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tvoid *link;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_local_work_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint count;\n\tunsigned int loops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tint events;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tstruct io_wq_work *work;\n\tbool hashed;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_req_failed {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tu8 flags;\n\tu8 ioprio;\n\tu64 off;\n\tu64 addr;\n\tu32 len;\n\tu32 op_flags;\n\tu16 buf_index;\n\tu16 personality;\n\tu32 file_index;\n\tu64 pad1;\n\tu64 addr3;\n\tint error;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_short_write {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu64 fpos;\n\tu64 wanted;\n\tu64 got;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_req {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tbool sq_thread;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_work_run {\n\tstruct trace_entry ent;\n\tvoid *tctx;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocg_inuse_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu32 old_inuse;\n\tu32 new_inuse;\n\tu64 old_hweight_inuse;\n\tu64 new_hweight_inuse;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_ioc_vrate_adj {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu64 old_vrate;\n\tu64 new_vrate;\n\tint busy_level;\n\tu32 read_missed_ppm;\n\tu32 write_missed_ppm;\n\tu32 rq_wait_pct;\n\tint nr_lagging;\n\tint nr_shortages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_iocg_forgive_debt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu64 vnow;\n\tu32 usage_pct;\n\tu64 old_debt;\n\tu64 new_debt;\n\tu64 old_delay;\n\tu64 new_delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_iocg_state {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu64 vnow;\n\tu64 vrate;\n\tu64 last_period;\n\tu64 cur_period;\n\tu64 vtime;\n\tu32 weight;\n\tu32 inuse;\n\tu64 hweight_active;\n\tu64 hweight_inuse;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_add_to_ioend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 pos;\n\tu64 dirty_len;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tint ki_flags;\n\tbool aio;\n\tint error;\n\tssize_t ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_rw_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tsize_t count;\n\tsize_t done_before;\n\tint ki_flags;\n\tunsigned int dio_flags;\n\tbool aio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_iter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t pos;\n\tu64 length;\n\tint status;\n\tunsigned int flags;\n\tconst void *ops;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t size;\n\tloff_t offset;\n\tu64 length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpumask {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_cpu {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int cpu;\n\tbool online;\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_global {\n\tstruct trace_entry ent;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_global_update {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tvoid *rx_sk;\n\tshort unsigned int protocol;\n\tenum skb_drop_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmalloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tbool accounted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_ack_irq {\n\tstruct trace_entry ent;\n\tunsigned int irqchip;\n\tunsigned int pin;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_age_hva {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_apic {\n\tstruct trace_entry ent;\n\tunsigned int rw;\n\tunsigned int reg;\n\tu64 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_apic_accept_irq {\n\tstruct trace_entry ent;\n\t__u32 apicid;\n\t__u16 dm;\n\t__u16 tm;\n\t__u8 vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_apic_ipi {\n\tstruct trace_entry ent;\n\t__u32 icr_low;\n\t__u32 dest_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_apicv_accept_irq {\n\tstruct trace_entry ent;\n\t__u32 apicid;\n\t__u16 dm;\n\t__u16 tm;\n\t__u8 vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_apicv_inhibit_changed {\n\tstruct trace_entry ent;\n\tint reason;\n\tbool set;\n\tlong unsigned int inhibits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_async_get_page_class {\n\tstruct trace_entry ent;\n\t__u64 gva;\n\tu64 gfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_async_pf_completed {\n\tstruct trace_entry ent;\n\tlong unsigned int address;\n\tu64 gva;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_async_pf_nopresent_ready {\n\tstruct trace_entry ent;\n\t__u64 token;\n\t__u64 gva;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_avic_doorbell {\n\tstruct trace_entry ent;\n\tu32 vcpuid;\n\tu32 apicid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_avic_ga_log {\n\tstruct trace_entry ent;\n\tu32 vmid;\n\tu32 vcpuid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_avic_incomplete_ipi {\n\tstruct trace_entry ent;\n\tu32 vcpu;\n\tu32 icrh;\n\tu32 icrl;\n\tu32 id;\n\tu32 index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_avic_kick_vcpu_slowpath {\n\tstruct trace_entry ent;\n\tu32 icrh;\n\tu32 icrl;\n\tu32 index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_avic_unaccelerated_access {\n\tstruct trace_entry ent;\n\tu32 vcpu;\n\tu32 offset;\n\tbool ft;\n\tbool rw;\n\tu32 vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_cpuid {\n\tstruct trace_entry ent;\n\tunsigned int function;\n\tunsigned int index;\n\tlong unsigned int rax;\n\tlong unsigned int rbx;\n\tlong unsigned int rcx;\n\tlong unsigned int rdx;\n\tbool found;\n\tbool used_max_basic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_cr {\n\tstruct trace_entry ent;\n\tunsigned int rw;\n\tunsigned int cr;\n\tlong unsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_dirty_ring_exit {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_dirty_ring_push {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 dirty_index;\n\tu32 reset_index;\n\tu32 slot;\n\tu64 offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_dirty_ring_reset {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 dirty_index;\n\tu32 reset_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_emulate_insn {\n\tstruct trace_entry ent;\n\t__u64 rip;\n\t__u32 csbase;\n\t__u8 len;\n\t__u8 insn[15];\n\t__u8 flags;\n\t__u8 failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_entry {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tlong unsigned int rip;\n\tbool immediate_exit;\n\tu32 intr_info;\n\tu32 error_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_eoi {\n\tstruct trace_entry ent;\n\t__u32 apicid;\n\tint vector;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_exit {\n\tstruct trace_entry ent;\n\tunsigned int exit_reason;\n\tlong unsigned int guest_rip;\n\tu32 isa;\n\tu64 info1;\n\tu64 info2;\n\tu32 intr_info;\n\tu32 error_code;\n\tunsigned int vcpu_id;\n\tu64 requests;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_fast_mmio {\n\tstruct trace_entry ent;\n\tu64 gpa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_fpu {\n\tstruct trace_entry ent;\n\tu32 load;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int vcpu_id;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_flush_tlb {\n\tstruct trace_entry ent;\n\tu64 processor_mask;\n\tu64 address_space;\n\tu64 flags;\n\tbool guest_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_flush_tlb_ex {\n\tstruct trace_entry ent;\n\tu64 valid_bank_mask;\n\tu64 format;\n\tu64 address_space;\n\tu64 flags;\n\tbool guest_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_hypercall {\n\tstruct trace_entry ent;\n\t__u16 rep_cnt;\n\t__u16 rep_idx;\n\t__u64 ingpa;\n\t__u64 outgpa;\n\t__u16 code;\n\t__u16 var_cnt;\n\tbool fast;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_hypercall_done {\n\tstruct trace_entry ent;\n\t__u64 result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_notify_acked_sint {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tu32 sint;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_send_ipi {\n\tstruct trace_entry ent;\n\tu32 vector;\n\tu64 processor_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_send_ipi_ex {\n\tstruct trace_entry ent;\n\tu32 vector;\n\tu64 format;\n\tu64 valid_bank_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_stimer_callback {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tint timer_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_stimer_cleanup {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tint timer_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_stimer_expiration {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tint timer_index;\n\tint direct;\n\tint msg_send_result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_stimer_set_config {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tint timer_index;\n\tu64 config;\n\tbool host;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_stimer_set_count {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tint timer_index;\n\tu64 count;\n\tbool host;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_stimer_start_one_shot {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tint timer_index;\n\tu64 time_now;\n\tu64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_stimer_start_periodic {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tint timer_index;\n\tu64 time_now;\n\tu64 exp_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_syndbg_get_msr {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tu32 vp_index;\n\tu32 msr;\n\tu64 data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_syndbg_set_msr {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tu32 vp_index;\n\tu32 msr;\n\tu64 data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_synic_send_eoi {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tu32 sint;\n\tint vector;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_synic_set_irq {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tu32 sint;\n\tint vector;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_synic_set_msr {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tu32 msr;\n\tu64 data;\n\tbool host;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hv_timer_state {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tunsigned int hv_timer_in_use;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hypercall {\n\tstruct trace_entry ent;\n\tlong unsigned int nr;\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n\tlong unsigned int a3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_inj_exception {\n\tstruct trace_entry ent;\n\tu8 exception;\n\tu8 has_error;\n\tu32 error_code;\n\tbool reinjected;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_inj_virq {\n\tstruct trace_entry ent;\n\tunsigned int vector;\n\tbool soft;\n\tbool reinjected;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_invlpga {\n\tstruct trace_entry ent;\n\t__u64 rip;\n\tunsigned int asid;\n\t__u64 address;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_ioapic_delayed_eoi_inj {\n\tstruct trace_entry ent;\n\t__u64 e;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_ioapic_set_irq {\n\tstruct trace_entry ent;\n\t__u64 e;\n\tint pin;\n\tbool coalesced;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmio {\n\tstruct trace_entry ent;\n\tu32 type;\n\tu32 len;\n\tu64 gpa;\n\tu64 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_get_page {\n\tstruct trace_entry ent;\n\t__u8 mmu_valid_gen;\n\t__u64 gfn;\n\t__u32 role;\n\t__u32 root_count;\n\tbool unsync;\n\tbool created;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_page_class {\n\tstruct trace_entry ent;\n\t__u8 mmu_valid_gen;\n\t__u64 gfn;\n\t__u32 role;\n\t__u32 root_count;\n\tbool unsync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_pagetable_walk {\n\tstruct trace_entry ent;\n\t__u64 addr;\n\t__u32 pferr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_paging_element {\n\tstruct trace_entry ent;\n\t__u64 pte;\n\t__u32 level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_set_bit_class {\n\tstruct trace_entry ent;\n\t__u64 gpa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_set_spte {\n\tstruct trace_entry ent;\n\tu64 gfn;\n\tu64 spte;\n\tu64 sptep;\n\tu8 level;\n\tbool r;\n\tbool x;\n\tsigned char u;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_split_huge_page {\n\tstruct trace_entry ent;\n\tu64 gfn;\n\tu64 spte;\n\tint level;\n\tint errno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_spte_requested {\n\tstruct trace_entry ent;\n\tu64 gfn;\n\tu64 pfn;\n\tu8 level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_walker_error {\n\tstruct trace_entry ent;\n\t__u32 pferr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmu_zap_all_fast {\n\tstruct trace_entry ent;\n\t__u8 mmu_valid_gen;\n\tunsigned int mmu_used_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_msi_set_irq {\n\tstruct trace_entry ent;\n\t__u64 address;\n\t__u64 data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_msr {\n\tstruct trace_entry ent;\n\tunsigned int write;\n\tu32 ecx;\n\tu64 data;\n\tu8 exception;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_nested_intercepts {\n\tstruct trace_entry ent;\n\t__u16 cr_read;\n\t__u16 cr_write;\n\t__u32 exceptions;\n\t__u32 intercept1;\n\t__u32 intercept2;\n\t__u32 intercept3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_nested_intr_vmexit {\n\tstruct trace_entry ent;\n\t__u64 rip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_nested_vmenter {\n\tstruct trace_entry ent;\n\t__u64 rip;\n\t__u64 vmcb;\n\t__u64 nested_rip;\n\t__u32 int_ctl;\n\t__u32 event_inj;\n\tbool tdp_enabled;\n\t__u64 guest_pgd;\n\t__u32 isa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_nested_vmenter_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_nested_vmexit {\n\tstruct trace_entry ent;\n\tunsigned int exit_reason;\n\tlong unsigned int guest_rip;\n\tu32 isa;\n\tu64 info1;\n\tu64 info2;\n\tu32 intr_info;\n\tu32 error_code;\n\tunsigned int vcpu_id;\n\tu64 requests;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_nested_vmexit_inject {\n\tstruct trace_entry ent;\n\t__u32 exit_code;\n\t__u64 exit_info1;\n\t__u64 exit_info2;\n\t__u32 exit_int_info;\n\t__u32 exit_int_info_err;\n\t__u32 isa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_page_fault {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tlong unsigned int guest_rip;\n\tu64 fault_address;\n\tu64 error_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_pi_irte_update {\n\tstruct trace_entry ent;\n\tunsigned int host_irq;\n\tint vcpu_id;\n\tunsigned int gsi;\n\tunsigned int gvec;\n\tbool set;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_pic_set_irq {\n\tstruct trace_entry ent;\n\t__u8 chip;\n\t__u8 pin;\n\t__u8 elcr;\n\t__u8 imr;\n\tbool coalesced;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_pio {\n\tstruct trace_entry ent;\n\tunsigned int rw;\n\tunsigned int port;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_ple_window_update {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_pml_full {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_pv_eoi {\n\tstruct trace_entry ent;\n\t__u32 apicid;\n\tint vector;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_pv_tlb_flush {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tbool need_flush_tlb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_pvclock_update {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\t__u32 version;\n\t__u64 tsc_timestamp;\n\t__u64 system_time;\n\t__u32 tsc_to_system_mul;\n\t__s8 tsc_shift;\n\t__u8 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_rmp_fault {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tu64 gpa;\n\tu64 pfn;\n\tu64 error_code;\n\tint rmp_level;\n\tint psmash_ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_set_irq {\n\tstruct trace_entry ent;\n\tunsigned int gsi;\n\tint level;\n\tint irq_source_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_skinit {\n\tstruct trace_entry ent;\n\t__u64 rip;\n\t__u32 slb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_smm_transition {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tu64 smbase;\n\tbool entering;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_tdp_mmu_spte_changed {\n\tstruct trace_entry ent;\n\tu64 gfn;\n\tu64 old_spte;\n\tu64 new_spte;\n\tu8 level;\n\tu8 as_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_test_age_hva {\n\tstruct trace_entry ent;\n\tlong unsigned int hva;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_track_tsc {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tunsigned int nr_vcpus_matched_tsc;\n\tunsigned int online_vcpus;\n\tbool use_master_clock;\n\tunsigned int host_clock;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_unmap_hva_range {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_update_master_clock {\n\tstruct trace_entry ent;\n\tbool use_master_clock;\n\tunsigned int host_clock;\n\tbool offset_matched;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_userspace_exit {\n\tstruct trace_entry ent;\n\t__u32 reason;\n\tint errno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_vcpu_wakeup {\n\tstruct trace_entry ent;\n\t__u64 ns;\n\tbool waited;\n\tbool valid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_vmgexit_enter {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tu64 exit_reason;\n\tu64 info1;\n\tu64 info2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_vmgexit_exit {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tu64 exit_reason;\n\tu64 info1;\n\tu64 info2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_vmgexit_msr_protocol_enter {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tu64 ghcb_gpa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_vmgexit_msr_protocol_exit {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\tu64 ghcb_gpa;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_wait_lapic_expire {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\ts64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_write_tsc_offset {\n\tstruct trace_entry ent;\n\tunsigned int vcpu_id;\n\t__u64 previous_tsc_offset;\n\t__u64 next_tsc_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_xen_hypercall {\n\tstruct trace_entry ent;\n\tu8 cpl;\n\tlong unsigned int nr;\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n\tlong unsigned int a3;\n\tlong unsigned int a4;\n\tlong unsigned int a5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_lock {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tvoid *lockdep_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_lock_acquire {\n\tstruct trace_entry ent;\n\tunsigned int flags;\n\tu32 __data_loc_name;\n\tvoid *lockdep_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_op {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_read {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_write {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tlong unsigned int piv;\n\tvoid *val;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_mmio_spte {\n\tstruct trace_entry ent;\n\tvoid *sptep;\n\tgfn_t gfn;\n\tunsigned int access;\n\tunsigned int gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tu32 __data_loc_comm;\n\tlong unsigned int total_vm;\n\tlong unsigned int anon_rss;\n\tlong unsigned int file_rss;\n\tlong unsigned int shmem_rss;\n\tuid_t uid;\n\tlong unsigned int pgtables;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mce_record {\n\tstruct trace_entry ent;\n\tu64 mcgcap;\n\tu64 mcgstatus;\n\tu64 status;\n\tu64 addr;\n\tu64 misc;\n\tu64 synd;\n\tu64 ipid;\n\tu64 ip;\n\tu64 tsc;\n\tu64 ppin;\n\tu64 walltime;\n\tu32 cpu;\n\tu32 cpuid;\n\tu32 apicid;\n\tu32 socketid;\n\tu8 cs;\n\tu8 bank;\n\tu8 cpuvendor;\n\tu32 microcode;\n\tu32 __data_loc_v_data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mdio_access {\n\tstruct trace_entry ent;\n\tchar busid[61];\n\tchar read;\n\tu8 addr;\n\tu16 val;\n\tunsigned int regnum;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mei_pci_cfg_read {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_reg;\n\tu32 offs;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mei_reg_read {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_reg;\n\tu32 offs;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mei_reg_write {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_reg;\n\tu32 offs;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct xdp_mem_allocator;\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pte {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_calculate_totalreserve_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int totalreserve_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tunsigned char order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache_range {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int last_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tenum lru_list lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tlong unsigned int thp_succeeded;\n\tlong unsigned int thp_failed;\n\tlong unsigned int thp_split;\n\tlong unsigned int large_folio_split;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages_start {\n\tstruct trace_entry ent;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tint percpu_refill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tlong unsigned int gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_lowmem_reserve {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tu32 __data_loc_upper_name;\n\tlong int lowmem_reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_wmarks {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tlong unsigned int watermark_min;\n\tlong unsigned int watermark_low;\n\tlong unsigned int watermark_high;\n\tlong unsigned int watermark_promo;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tlong unsigned int gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_clear_hopeless {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_reclaim_fail {\n\tstruct trace_entry ent;\n\tint nid;\n\tint failures;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_reclaim_pages {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_throttled {\n\tstruct trace_entry ent;\n\tint nid;\n\tint usec_timeout;\n\tint usec_delayed;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_write_folio {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock_acquire_returned {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tbool success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_msr_trace_class {\n\tstruct trace_entry ent;\n\tunsigned int msr;\n\tu64 val;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int len;\n\tlong long unsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_folio {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tlong unsigned int index;\n\tlong long unsigned int fend;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int collected_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_gap {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tunsigned char type;\n\tlong long unsigned int from;\n\tlong long unsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_sreq {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int subreq;\n\tunsigned int stream;\n\tunsigned int len;\n\tunsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_state {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int notes;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_stream {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int front;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_copy2cache {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int creq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_failure {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_failure what;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folio {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tlong unsigned int index;\n\tunsigned int nr;\n\tenum netfs_folio_trace why;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folioq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int id;\n\tenum netfs_folioq_trace trace;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_read {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int cookie;\n\tloff_t i_size;\n\tloff_t start;\n\tsize_t len;\n\tenum netfs_read_trace what;\n\tunsigned int netfs_inode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int flags;\n\tenum netfs_io_origin origin;\n\tenum netfs_rreq_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tint ref;\n\tenum netfs_rreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort unsigned int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_sreq_trace what;\n\tu8 slot;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int subreq;\n\tint ref;\n\tenum netfs_sreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tenum netfs_write_trace what;\n\tlong long unsigned int start;\n\tlong long unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write_iter {\n\tstruct trace_entry ent;\n\tlong long unsigned int start;\n\tsize_t len;\n\tunsigned int flags;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netlink_extack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nmi_handler {\n\tstruct trace_entry ent;\n\tvoid *handler;\n\ts64 delta_ns;\n\tint handled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_notifier_info {\n\tstruct trace_entry ent;\n\tvoid *cb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_op {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n\tlong unsigned int req_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_order {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_unbounded {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int nr_to_read;\n\tlong unsigned int lookahead_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\ts32 inflight;\n\tu32 hold;\n\tu32 release;\n\tu64 cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_hold {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 hold;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 release;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_update_nid {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tint pool_nid;\n\tint new_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pci_hp_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tu32 __data_loc_slot;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pcie_link_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tunsigned int type;\n\tunsigned int reason;\n\tunsigned int cur_bus_speed;\n\tunsigned int max_bus_speed;\n\tunsigned int width;\n\tunsigned int flit_mode;\n\tunsigned int link_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_preemptirq_template {\n\tstruct trace_entry ent;\n\ts32 caller_offs;\n\ts32 parent_offs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_prq_report {\n\tstruct trace_entry ent;\n\tu64 dw0;\n\tu64 dw1;\n\tu64 dw2;\n\tu64 dw3;\n\tlong unsigned int seq;\n\tu32 __data_loc_iommu;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_buff;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_purge_vmap_area_lazy {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int npurged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_enqueue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qi_submit {\n\tstruct trace_entry ent;\n\tu64 qw0;\n\tu64 qw1;\n\tu64 qw2;\n\tu64 qw3;\n\tu32 __data_loc_iommu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kvfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_segcb_stats {\n\tstruct trace_entry ent;\n\tconst char *ctx;\n\tlong unsigned int gp_seq[4];\n\tlong int seglen[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_sr_normal {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tconst char *srevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_stall_warning {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_watching {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint counter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_drop_region {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int from;\n\tunsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_sync {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_status;\n\tu32 __data_loc_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_async {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_block {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bool {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bulk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tu32 __data_loc_buf;\n\tint val_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_reg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_internal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flags;\n\tint usage_count;\n\tint disable_depth;\n\tint runtime_auto;\n\tint request_pending;\n\tint irq_safe;\n\tint child_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_return_int {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int ip;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\ts32 node_id;\n\ts32 mm_cid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_alarm_irq_enable {\n\tstruct trace_entry ent;\n\tunsigned int enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_freq {\n\tstruct trace_entry ent;\n\tint freq;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_state {\n\tstruct trace_entry ent;\n\tint enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_offset_class {\n\tstruct trace_entry ent;\n\tlong int offset;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_time_alarm_class {\n\tstruct trace_entry ent;\n\ttime64_t secs;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_timer_class {\n\tstruct trace_entry ent;\n\tstruct rtc_timer *timer;\n\tktime_t expires;\n\tktime_t period;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_bypass_lb {\n\tstruct trace_entry ent;\n\t__u32 node;\n\t__u32 nr_cpus;\n\t__u32 nr_tasks;\n\t__u32 nr_balanced;\n\t__u32 before_min;\n\t__u32 before_max;\n\t__u32 after_min;\n\t__u32 after_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_dump {\n\tstruct trace_entry ent;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\t__s64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *worker;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_move_numa {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_numa_pair_template {\n\tstruct trace_entry ent;\n\tpid_t src_pid;\n\tpid_t src_tgid;\n\tpid_t src_ngid;\n\tint src_cpu;\n\tint src_nid;\n\tpid_t dst_pid;\n\tpid_t dst_tgid;\n\tpid_t dst_ngid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_prepare_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_interp;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exit {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tbool group_dead;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tu32 __data_loc_parent_comm;\n\tpid_t parent_pid;\n\tu32 __data_loc_child_comm;\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_cpuset_numa {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tlong unsigned int mem_allowed[1];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_vma_numa {\n\tstruct trace_entry ent;\n\tlong unsigned int numa_scan_offset;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tenum numa_vmaskip_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 runtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sk_data_ready {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 family;\n\t__u16 protocol;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 flags;\n\t__u16 addr;\n\t__u8 command;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 read_write;\n\t__u8 command;\n\t__s16 res;\n\t__u32 protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int sysctl_mem[3];\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_msg_length {\n\tstruct trace_entry ent;\n\tvoid *sk;\n\t__u16 family;\n\t__u16 protocol;\n\tint ret;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_swiotlb_bounced {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu64 dma_mask;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tbool force;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tu64 clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_prctl_unknown {\n\tstruct trace_entry ent;\n\tint option;\n\tlong unsigned int arg2;\n\tlong unsigned int arg3;\n\tlong unsigned int arg4;\n\tlong unsigned int arg5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tasklet {\n\tstruct trace_entry ent;\n\tvoid *tasklet;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_ao_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\t__u8 keyid;\n\t__u8 rnext;\n\t__u8 maclen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_cong_state_set {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u8 cong_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_hash_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\t__u64 sock_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_ssthresh;\n\t__u32 window_clamp;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_send_reset {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\tenum sk_rst_reason reason;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_sendmsg_locked {\n\tstruct trace_entry ent;\n\tconst void *skb_addr;\n\tint skb_len;\n\tint msg_left;\n\tint size_goal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_test_pages_isolated {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int fin_pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_temperature {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint temp_prev;\n\tint temp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_zone_trip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint trip;\n\tenum thermal_trip_type trip_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_base_idle {\n\tstruct trace_entry ent;\n\tbool is_idle;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int bucket_expiry;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tlb_flush {\n\tstruct trace_entry ent;\n\tint reason;\n\tlong unsigned int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_child_parent {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_cpu_parent {\n\tstruct trace_entry ent;\n\tvoid *parent;\n\tunsigned int cpu;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_cpugroup {\n\tstruct trace_entry ent;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_and_cpu {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tu32 childmask;\n\tu8 active;\n\tu8 migrator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_set {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_handle_remote {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_idle {\n\tstruct trace_entry ent;\n\tu64 nextevt;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_update_events {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *group;\n\tu64 nextevt;\n\tu64 group_next_expiry;\n\tu64 child_evt_expiry;\n\tunsigned int group_lvl;\n\tunsigned int child_evtcpu;\n\tu8 child_active;\n\tu8 group_active;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vcpu_match_mmio {\n\tstruct trace_entry ent;\n\tgva_t gva;\n\tgpa_t gpa;\n\tbool write;\n\tbool gpa_match;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_activate {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_managed;\n\tbool can_reserve;\n\tbool reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_alloc {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tbool reserved;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_alloc_managed {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_config {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tunsigned int cpu;\n\tunsigned int apicdest;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_free_moved {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int cpu;\n\tunsigned int vector;\n\tbool is_managed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_mod {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tunsigned int cpu;\n\tunsigned int prev_vector;\n\tunsigned int prev_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_reserve {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_setup {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_legacy;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_teardown {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_managed;\n\tbool has_reserved;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_virtio_gpu_cmd {\n\tstruct trace_entry ent;\n\tint dev;\n\tunsigned int vq;\n\tu32 __data_loc_name;\n\tu32 type;\n\tu32 flags;\n\tu64 fence_id;\n\tu32 ctx_id;\n\tu32 num_free;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_virtio_transport_alloc_pkt {\n\tstruct trace_entry ent;\n\t__u32 src_cid;\n\t__u32 src_port;\n\t__u32 dst_cid;\n\t__u32 dst_port;\n\t__u32 len;\n\t__u16 type;\n\t__u16 op;\n\t__u32 flags;\n\tbool zcopy;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_virtio_transport_recv_pkt {\n\tstruct trace_entry ent;\n\t__u32 src_cid;\n\t__u32 src_port;\n\t__u32 dst_cid;\n\t__u32 dst_port;\n\t__u32 len;\n\t__u16 type;\n\t__u16 op;\n\t__u32 flags;\n\t__u32 buf_alloc;\n\t__u32 fwd_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vlv_fifo_size {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 sprite0_start;\n\tu32 sprite1_start;\n\tu32 fifo_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vlv_wm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 level;\n\tu32 cxsr;\n\tu32 primary;\n\tu32 sprite0;\n\tu32 sprite1;\n\tu32 cursor;\n\tu32 sr_plane;\n\tu32 sr_cursor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_set_timeout {\n\tstruct trace_entry ent;\n\tint id;\n\tunsigned int timeout;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_template {\n\tstruct trace_entry ent;\n\tint id;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tu32 __data_loc_workqueue;\n\tint req_cpu;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_folio_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_x86_fpu {\n\tstruct trace_entry ent;\n\tstruct fpu *fpu;\n\tbool load_fpu;\n\tu64 xfeatures;\n\tu64 xcomp_bv;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_x86_irq_vector {\n\tstruct trace_entry ent;\n\tint vector;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tunsigned int xdp_pass;\n\tunsigned int xdp_drop;\n\tunsigned int xdp_redirect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n\tint flags;\n};\n\nstruct trace_func_repeats {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int count;\n\tu64 ts_last_call;\n};\n\nstruct trace_kprobe {\n\tstruct dyn_event devent;\n\tstruct kretprobe rp;\n\tlong unsigned int *nhit;\n\tconst char *symbol;\n\tstruct trace_probe tp;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n};\n\nstruct trace_min_max_param {\n\tstruct mutex *lock;\n\tu64 *val;\n\tu64 *min;\n\tu64 *max;\n};\n\nstruct trace_mod_entry {\n\tlong unsigned int mod_addr;\n\tchar mod_name[56];\n};\n\nstruct trace_module_delta {\n\tstruct callback_head rcu;\n\tlong int delta[0];\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nunion upper_chunk;\n\nstruct trace_pid_list {\n\tseqcount_raw_spinlock_t seqcount;\n\traw_spinlock_t lock;\n\tstruct irq_work refill_irqwork;\n\tunion upper_chunk *upper[256];\n\tunion upper_chunk *upper_list;\n\tunion lower_chunk *lower_list;\n\tint free_upper_chunks;\n\tint free_lower_chunks;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nstruct trace_scratch {\n\tunsigned int clock_id;\n\tlong unsigned int text_addr;\n\tlong unsigned int nr_entries;\n\tstruct trace_mod_entry entries[0];\n};\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct eventfs_inode *ei;\n\tint ref_count;\n\tint nr_events;\n};\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tchar *filename;\n\tstruct uprobe *uprobe;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int *nhits;\n\tstruct trace_probe tp;\n};\n\nstruct trace_user_buf {\n\tchar *buf;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct tracefs_inode {\n\tstruct inode vfs_inode;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tvoid *private;\n};\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct traceprobe_parse_context {\n\tstruct trace_event_call *event;\n\tconst char *funcname;\n\tconst struct btf_type *proto;\n\tconst struct btf_param *params;\n\ts32 nr_params;\n\tstruct btf *btf;\n\tconst struct btf_type *last_type;\n\tu32 last_bitoffs;\n\tu32 last_bitsize;\n\tstruct trace_probe *tp;\n\tunsigned int flags;\n\tint offset;\n};\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u64, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tstruct tracer_flags *default_flags;\n\tint enabled;\n\tbool print_max;\n\tbool allow_instances;\n\tbool noboot;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct tracers {\n\tstruct list_head list;\n\tstruct tracer *tracer;\n\tstruct tracer_flags *flags;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar *cmd;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tdepot_stack_handle_t handle;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct trampoline_header {\n\tu64 start;\n\tu64 efer;\n\tu32 cr4;\n\tu32 flags;\n\tu32 lock;\n};\n\ntypedef struct tree_desc_s tree_desc;\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsc_adjust {\n\ts64 bootval;\n\ts64 adjusted;\n\tlong unsigned int nextcheck;\n\tbool warned;\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct tss_segment_16 {\n\tu16 prev_task_link;\n\tu16 sp0;\n\tu16 ss0;\n\tu16 sp1;\n\tu16 ss1;\n\tu16 sp2;\n\tu16 ss2;\n\tu16 ip;\n\tu16 flag;\n\tu16 ax;\n\tu16 cx;\n\tu16 dx;\n\tu16 bx;\n\tu16 sp;\n\tu16 bp;\n\tu16 si;\n\tu16 di;\n\tu16 es;\n\tu16 cs;\n\tu16 ss;\n\tu16 ds;\n\tu16 ldt;\n};\n\nstruct tss_segment_32 {\n\tu32 prev_task_link;\n\tu32 esp0;\n\tu32 ss0;\n\tu32 esp1;\n\tu32 ss1;\n\tu32 esp2;\n\tu32 ss2;\n\tu32 cr3;\n\tu32 eip;\n\tu32 eflags;\n\tu32 eax;\n\tu32 ecx;\n\tu32 edx;\n\tu32 ebx;\n\tu32 esp;\n\tu32 ebp;\n\tu32 esi;\n\tu32 edi;\n\tu32 es;\n\tu32 cs;\n\tu32 ss;\n\tu32 ds;\n\tu32 fs;\n\tu32 gs;\n\tu32 ldt_selector;\n\tu16 t;\n\tu16 io_map;\n};\n\nstruct ttm_agp_backend {\n\tstruct ttm_tt ttm;\n\tstruct agp_memory *mem;\n\tstruct agp_bridge_data *bridge;\n};\n\nstruct ttm_backup_flags {\n\tu32 purge: 1;\n\tu32 writeback: 1;\n};\n\nstruct ttm_operation_ctx;\n\nstruct ttm_lru_walk_arg {\n\tstruct ttm_operation_ctx *ctx;\n\tstruct ww_acquire_ctx *ticket;\n\tbool trylock_only;\n};\n\nstruct ttm_lru_walk_ops;\n\nstruct ttm_lru_walk {\n\tconst struct ttm_lru_walk_ops *ops;\n\tstruct ttm_lru_walk_arg arg;\n};\n\nstruct ttm_place;\n\nstruct ttm_bo_evict_walk {\n\tstruct ttm_lru_walk walk;\n\tconst struct ttm_place *place;\n\tstruct ttm_buffer_object *evictor;\n\tstruct ttm_resource **res;\n\tlong unsigned int evicted;\n\tstruct dmem_cgroup_pool_state *limit_pool;\n\tbool try_low;\n\tbool hit_low;\n};\n\nstruct ttm_bo_kmap_obj {\n\tvoid *virtual;\n\tstruct page *page;\n\tenum {\n\t\tttm_bo_map_iomap = 129,\n\t\tttm_bo_map_vmap = 2,\n\t\tttm_bo_map_kmap = 3,\n\t\tttm_bo_map_premapped = 132,\n\t} bo_kmap_type;\n\tstruct ttm_buffer_object *bo;\n};\n\nstruct ttm_bo_lru_cursor;\n\ntypedef struct ttm_bo_lru_cursor *class_ttm_bo_lru_cursor_t;\n\nstruct ttm_resource_cursor {\n\tstruct ttm_resource_manager *man;\n\tstruct ttm_lru_item hitch;\n\tstruct list_head bulk_link;\n\tstruct ttm_lru_bulk_move *bulk;\n\tunsigned int mem_type;\n\tunsigned int priority;\n};\n\nstruct ttm_bo_lru_cursor {\n\tstruct ttm_resource_cursor res_curs;\n\tstruct ttm_buffer_object *bo;\n\tbool needs_unlock;\n\tstruct ttm_lru_walk_arg *arg;\n};\n\nstruct ttm_bo_shrink_flags {\n\tu32 purge: 1;\n\tu32 writeback: 1;\n\tu32 allow_move: 1;\n};\n\nstruct ttm_bo_swapout_walk {\n\tstruct ttm_lru_walk walk;\n\tgfp_t gfp_flags;\n\tbool hit_low;\n\tbool evict_low;\n};\n\nstruct ttm_placement;\n\nstruct ttm_device_funcs {\n\tstruct ttm_tt * (*ttm_tt_create)(struct ttm_buffer_object *, uint32_t);\n\tint (*ttm_tt_populate)(struct ttm_device *, struct ttm_tt *, struct ttm_operation_ctx *);\n\tvoid (*ttm_tt_unpopulate)(struct ttm_device *, struct ttm_tt *);\n\tvoid (*ttm_tt_destroy)(struct ttm_device *, struct ttm_tt *);\n\tbool (*eviction_valuable)(struct ttm_buffer_object *, const struct ttm_place *);\n\tvoid (*evict_flags)(struct ttm_buffer_object *, struct ttm_placement *);\n\tint (*move)(struct ttm_buffer_object *, bool, struct ttm_operation_ctx *, struct ttm_resource *, struct ttm_place *);\n\tvoid (*delete_mem_notify)(struct ttm_buffer_object *);\n\tvoid (*swap_notify)(struct ttm_buffer_object *);\n\tint (*io_mem_reserve)(struct ttm_device *, struct ttm_resource *);\n\tvoid (*io_mem_free)(struct ttm_device *, struct ttm_resource *);\n\tlong unsigned int (*io_mem_pfn)(struct ttm_buffer_object *, long unsigned int);\n\tint (*access_memory)(struct ttm_buffer_object *, long unsigned int, void *, int, int);\n\tvoid (*release_notify)(struct ttm_buffer_object *);\n};\n\nstruct ttm_global {\n\tstruct page *dummy_read_page;\n\tstruct list_head device_list;\n\tatomic_t bo_count;\n};\n\nstruct ttm_kmap_iter_linear_io {\n\tstruct ttm_kmap_iter base;\n\tstruct iosys_map dmap;\n\tbool needs_unmap;\n};\n\nstruct ttm_kmap_iter_ops {\n\tvoid (*map_local)(struct ttm_kmap_iter *, struct iosys_map *, long unsigned int);\n\tvoid (*unmap_local)(struct ttm_kmap_iter *, struct iosys_map *);\n\tbool maps_tt;\n};\n\nstruct ttm_lru_bulk_move_pos {\n\tstruct ttm_resource *first;\n\tstruct ttm_resource *last;\n};\n\nstruct ttm_lru_bulk_move {\n\tstruct ttm_lru_bulk_move_pos pos[36];\n\tstruct list_head cursor_list;\n};\n\nstruct ttm_lru_walk_ops {\n\ts64 (*process_bo)(struct ttm_lru_walk *, struct ttm_buffer_object *);\n};\n\nstruct ttm_operation_ctx {\n\tbool interruptible;\n\tbool no_wait_gpu;\n\tbool gfp_retry_mayfail;\n\tbool allow_res_evict;\n\tstruct dma_resv *resv;\n\tuint64_t bytes_moved;\n};\n\nstruct ttm_place {\n\tunsigned int fpfn;\n\tunsigned int lpfn;\n\tuint32_t mem_type;\n\tuint32_t flags;\n};\n\nstruct ttm_placement {\n\tunsigned int num_placement;\n\tconst struct ttm_place *placement;\n};\n\nstruct ttm_pool_alloc_state {\n\tstruct page **pages;\n\tstruct page **caching_divide;\n\tdma_addr_t *dma_addr;\n\tlong unsigned int remaining_pages;\n\tenum ttm_caching tt_caching;\n};\n\nstruct ttm_pool_dma {\n\tdma_addr_t addr;\n\tlong unsigned int vaddr;\n};\n\nstruct ttm_pool_tt_restore {\n\tstruct ttm_pool *pool;\n\tstruct ttm_pool_alloc_state snapshot_alloc;\n\tstruct page *alloced_page;\n\tdma_addr_t first_dma;\n\tlong unsigned int alloced_pages;\n\tlong unsigned int restored_pages;\n\tenum ttm_caching page_caching;\n\tunsigned int order;\n};\n\nstruct ttm_range_manager {\n\tstruct ttm_resource_manager manager;\n\tstruct drm_mm mm;\n\tspinlock_t lock;\n};\n\nstruct ttm_range_mgr_node {\n\tstruct ttm_resource base;\n\tstruct drm_mm_node mm_nodes[0];\n};\n\nstruct ttm_resource_manager_func {\n\tint (*alloc)(struct ttm_resource_manager *, struct ttm_buffer_object *, const struct ttm_place *, struct ttm_resource **);\n\tvoid (*free)(struct ttm_resource_manager *, struct ttm_resource *);\n\tbool (*intersects)(struct ttm_resource_manager *, struct ttm_resource *, const struct ttm_place *, size_t);\n\tbool (*compatible)(struct ttm_resource_manager *, struct ttm_resource *, const struct ttm_place *, size_t);\n\tvoid (*debug)(struct ttm_resource_manager *, struct drm_printer *);\n};\n\nstruct ttm_transfer_obj {\n\tstruct ttm_buffer_object base;\n\tstruct ttm_buffer_object *bo;\n};\n\nstruct ttm_validate_buffer {\n\tstruct list_head head;\n\tstruct ttm_buffer_object *bo;\n\tunsigned int num_shared;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct tuple_flags {\n\tu_int link_space: 4;\n\tu_int has_link: 1;\n\tu_int mfc_fn: 3;\n\tu_int space: 4;\n};\n\nstruct tuple_t {\n\tu_int Attributes;\n\tcisdata_t DesiredTuple;\n\tu_int Flags;\n\tu_int LinkOffset;\n\tu_int CISOffset;\n\tcisdata_t TupleCode;\n\tcisdata_t TupleLink;\n\tcisdata_t TupleOffset;\n\tcisdata_t TupleDataMax;\n\tcisdata_t TupleDataLen;\n\tcisdata_t *TupleData;\n};\n\nstruct video_levels;\n\nstruct tv_mode {\n\tconst char *name;\n\tu32 clock;\n\tu16 refresh;\n\tu8 oversample;\n\tu8 hsync_end;\n\tu16 hblank_start;\n\tu16 hblank_end;\n\tu16 htotal;\n\tbool progressive: 1;\n\tbool trilevel_sync: 1;\n\tbool component_only: 1;\n\tu8 vsync_start_f1;\n\tu8 vsync_start_f2;\n\tu8 vsync_len;\n\tbool veq_ena: 1;\n\tu8 veq_start_f1;\n\tu8 veq_start_f2;\n\tu8 veq_len;\n\tu8 vi_end_f1;\n\tu8 vi_end_f2;\n\tu16 nbr_end;\n\tbool burst_ena: 1;\n\tu8 hburst_start;\n\tu8 hburst_len;\n\tu8 vburst_start_f1;\n\tu16 vburst_end_f1;\n\tu8 vburst_start_f2;\n\tu16 vburst_end_f2;\n\tu8 vburst_start_f3;\n\tu16 vburst_end_f3;\n\tu8 vburst_start_f4;\n\tu16 vburst_end_f4;\n\tu16 dda2_size;\n\tu16 dda3_size;\n\tu8 dda1_inc;\n\tu16 dda2_inc;\n\tu16 dda3_inc;\n\tu32 sc_reset;\n\tbool pal_burst: 1;\n\tconst struct video_levels *composite_levels;\n\tconst struct video_levels *svideo_levels;\n\tconst struct color_conversion *composite_color;\n\tconst struct color_conversion *svideo_color;\n\tconst u32 *filter_table;\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n};\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n\tvoid (*setup_timer)(struct uart_8250_port *);\n};\n\ntypedef struct uart_8250_port *class_serial8250_rpm_t;\n\nstruct mctrl_gpios;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tu16 bugs;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tu16 lsr_saved_flags;\n\tu16 lsr_save_mask;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *, bool);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *, bool);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*start_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\ntypedef struct uart_port *class_uart_port_lock_irq_t;\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct uc_css_header {\n\tu32 module_type;\n\tu32 header_size_dw;\n\tu32 header_version;\n\tu32 module_id;\n\tu32 module_vendor;\n\tu32 date;\n\tu32 size_dw;\n\tu32 key_size_dw;\n\tu32 modulus_size_dw;\n\tu32 exponent_size_dw;\n\tu32 time;\n\tchar username[8];\n\tchar buildnumber[12];\n\tu32 sw_version;\n\tu32 vf_version;\n\tu32 reserved0[12];\n\tunion {\n\t\tu32 private_data_size;\n\t\tu32 reserved1;\n\t};\n\tu32 header_info;\n};\n\nstruct uc_fw_blob {\n\tconst char *path;\n\tbool legacy;\n\tu8 major;\n\tu8 minor;\n\tu8 patch;\n\tbool has_gsc_headers;\n} __attribute__((packed));\n\nstruct uc_fw_platform_requirement {\n\tenum intel_platform p;\n\tu8 rev;\n\tconst struct uc_fw_blob blob;\n} __attribute__((packed));\n\nstruct ucode_cpu_info {\n\tstruct cpu_signature cpu_sig;\n\tvoid *mc;\n};\n\nstruct ucode_patch {\n\tstruct list_head plist;\n\tvoid *data;\n\tunsigned int size;\n\tu32 patch_id;\n\tu16 equiv_cpu;\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[10];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n\tu16 len;\n\tbool is_linear;\n\tbool csum_unnecessary;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 64;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct uncore_discovery_domain {\n\tu32 discovery_base;\n\tbool base_is_pci;\n\tint (*global_init)(u64);\n\tint *units_ignore;\n};\n\nstruct uncore_event_desc {\n\tstruct device_attribute attr;\n\tconst char *config;\n};\n\nstruct uncore_global_discovery {\n\tunion {\n\t\tu64 table1;\n\t\tstruct {\n\t\t\tu64 type: 8;\n\t\t\tu64 stride: 8;\n\t\t\tu64 max_units: 10;\n\t\t\tu64 __reserved_1: 36;\n\t\t\tu64 access_type: 2;\n\t\t};\n\t};\n\tu64 ctl;\n\tunion {\n\t\tu64 table3;\n\t\tstruct {\n\t\t\tu64 status_offset: 8;\n\t\t\tu64 num_status: 16;\n\t\t\tu64 __reserved_2: 40;\n\t\t};\n\t};\n};\n\nstruct uncore_iio_topology {\n\tint pci_bus_no;\n\tint segment;\n};\n\nstruct uncore_plat_init {\n\tvoid (*cpu_init)(void);\n\tint (*pci_init)(void);\n\tvoid (*mmio_init)(void);\n\tstruct uncore_discovery_domain domain[2];\n};\n\nstruct uncore_unit_discovery {\n\tunion {\n\t\tu64 table1;\n\t\tstruct {\n\t\t\tu64 num_regs: 8;\n\t\t\tu64 ctl_offset: 8;\n\t\t\tu64 bit_width: 8;\n\t\t\tu64 ctr_offset: 8;\n\t\t\tu64 status_offset: 8;\n\t\t\tu64 __reserved_1: 22;\n\t\t\tu64 access_type: 2;\n\t\t};\n\t};\n\tu64 ctl;\n\tunion {\n\t\tu64 table3;\n\t\tstruct {\n\t\t\tu64 box_type: 16;\n\t\t\tu64 box_id: 16;\n\t\t\tu64 __reserved_2: 32;\n\t\t};\n\t};\n};\n\nstruct uncore_upi_topology {\n\tint die_to;\n\tint pmu_idx_to;\n\tint enabled;\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct utf8data;\n\nstruct utf8data_table;\n\nstruct unicode_map {\n\tunsigned int version;\n\tconst struct utf8data *ntab[2];\n\tconst struct utf8data_table *tables;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct unity_map_entry {\n\tstruct list_head list;\n\tu16 devid_start;\n\tu16 devid_end;\n\tu64 address_start;\n\tu64 address_end;\n\tint prot;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\nstruct unwind_cache {\n\tlong unsigned int unwind_completed;\n\tunsigned int nr_entries;\n\tlong unsigned int entries[0];\n};\n\nstruct unwind_stacktrace {\n\tunsigned int nr;\n\tlong unsigned int *entries;\n};\n\nstruct unwind_state {\n\tstruct stack_info stack_info;\n\tlong unsigned int stack_mask;\n\tstruct task_struct *task;\n\tint graph_idx;\n\tstruct llist_node *kr_cur;\n\tbool error;\n\tbool signal;\n\tbool full_regs;\n\tlong unsigned int sp;\n\tlong unsigned int bp;\n\tlong unsigned int ip;\n\tstruct pt_regs *regs;\n\tstruct pt_regs *prev_regs;\n};\n\nstruct unwind_user_frame {\n\ts32 cfa_off;\n\ts32 ra_off;\n\ts32 fp_off;\n\tbool use_fp;\n};\n\nstruct unwind_user_state {\n\tlong unsigned int ip;\n\tlong unsigned int sp;\n\tlong unsigned int fp;\n\tunsigned int ws;\n\tenum unwind_user_type current_type;\n\tunsigned int available_types;\n\tbool topmost;\n\tbool done;\n};\n\nstruct unwind_work;\n\ntypedef void (*unwind_callback_t)(struct unwind_work *, struct unwind_stacktrace *, u64);\n\nstruct unwind_work {\n\tstruct list_head list;\n\tunwind_callback_t func;\n\tint bit;\n};\n\nstruct update_classid_context {\n\tu32 classid;\n\tunsigned int batch;\n};\n\nunion upper_chunk {\n\tunion upper_chunk *next;\n\tunion lower_chunk *data[256];\n};\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct list_head consumers;\n\tstruct inode *inode;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n\tint dsize;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_syscall_args {\n\tlong unsigned int ax;\n\tlong unsigned int r11;\n\tlong unsigned int cx;\n\tlong unsigned int retaddr;\n};\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunsigned int depth;\n\tstruct return_instance *return_instances;\n\tstruct return_instance *ri_pool;\n\tstruct timer_list ri_timer;\n\tseqcount_t ri_seqcount;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tbool signal_denied;\n\tstruct arch_uprobe *auprobe;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\nstruct uprobe_trampoline {\n\tstruct hlist_node node;\n\tlong unsigned int vaddr;\n};\n\nstruct uprobe_xol_ops {\n\tbool (*emulate)(struct arch_uprobe *, struct pt_regs *);\n\tint (*pre_xol)(struct arch_uprobe *, struct pt_regs *);\n\tint (*post_xol)(struct arch_uprobe *, struct pt_regs *);\n\tvoid (*abort)(struct arch_uprobe *, struct pt_regs *);\n};\n\nstruct uretprobe_syscall_args {\n\tlong unsigned int r11;\n\tlong unsigned int cx;\n\tlong unsigned int ax;\n};\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_debug_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDebugInEndpoint;\n\t__u8 bDebugOutEndpoint;\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct used_entry {\n\tu32 id;\n\tu32 len;\n};\n\nstruct user_arg_ptr {\n\tbool is_compat;\n\tunion {\n\t\tconst char * const *native;\n\t\tconst compat_uptr_t *compat;\n\t} ptr;\n};\n\nstruct user_desc {\n\tunsigned int entry_number;\n\tunsigned int base_addr;\n\tunsigned int limit;\n\tunsigned int seg_32bit: 1;\n\tunsigned int contents: 2;\n\tunsigned int read_exec_only: 1;\n\tunsigned int limit_in_pages: 1;\n\tunsigned int seg_not_present: 1;\n\tunsigned int useable: 1;\n\tunsigned int lm: 1;\n};\n\nstruct user_element {\n\tstruct snd_ctl_elem_info info;\n\tstruct snd_card *card;\n\tchar *elem_data;\n\tlong unsigned int elem_data_size;\n\tvoid *tlv_data;\n\tlong unsigned int tlv_data_size;\n\tvoid *priv_data;\n};\n\nstruct user_i387_ia32_struct {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[10];\n\tlong int rlimit_max[4];\n\tstruct binfmt_misc *binfmt_misc;\n\tlong: 64;\n};\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n};\n\nstruct user_threshold {\n\tstruct list_head list_node;\n\tint temperature;\n\tint direction;\n};\n\nstruct userspace_policy {\n\tunsigned int is_managed;\n\tunsigned int setspeed;\n\tstruct mutex mutex;\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tlong unsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct ustring_buffer {\n\tchar buffer[1024];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct utimbuf {\n\t__kernel_old_time_t actime;\n\t__kernel_old_time_t modtime;\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct v2_disk_dqheader {\n\t__le32 dqh_magic;\n\t__le32 dqh_version;\n};\n\nstruct v2_disk_dqinfo {\n\t__le32 dqi_bgrace;\n\t__le32 dqi_igrace;\n\t__le32 dqi_flags;\n\t__le32 dqi_blocks;\n\t__le32 dqi_free_blk;\n\t__le32 dqi_free_entry;\n};\n\nstruct v2r0_disk_dqblk {\n\t__le32 dqb_id;\n\t__le32 dqb_ihardlimit;\n\t__le32 dqb_isoftlimit;\n\t__le32 dqb_curinodes;\n\t__le32 dqb_bhardlimit;\n\t__le32 dqb_bsoftlimit;\n\t__le64 dqb_curspace;\n\t__le64 dqb_btime;\n\t__le64 dqb_itime;\n};\n\nstruct v2r1_disk_dqblk {\n\t__le32 dqb_id;\n\t__le32 dqb_pad;\n\t__le64 dqb_ihardlimit;\n\t__le64 dqb_isoftlimit;\n\t__le64 dqb_curinodes;\n\t__le64 dqb_bhardlimit;\n\t__le64 dqb_bsoftlimit;\n\t__le64 dqb_curspace;\n\t__le64 dqb_btime;\n\t__le64 dqb_itime;\n};\n\nstruct v9fs_context {\n\tstruct p9_client_opts client_opts;\n\tstruct p9_fd_opts fd_opts;\n\tstruct p9_rdma_opts rdma_opts;\n\tstruct p9_session_opts session_opts;\n};\n\nstruct v9fs_inode {\n\tstruct netfs_inode netfs;\n\tstruct p9_qid qid;\n\tunsigned int cache_validity;\n\tstruct mutex v_mutex;\n};\n\nstruct v9fs_session_info {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tunsigned int maxdata;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tstruct p9_client *clnt;\n\tstruct list_head slist;\n\tstruct rw_semaphore rename_sem;\n\tlong int session_lock_timeout;\n};\n\nstruct va_alignment {\n\tint flags;\n\tlong unsigned int mask;\n\tlong unsigned int bits;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct value_name_pair {\n\tint value;\n\tconst char *name;\n};\n\nstruct var_mtrr_range_state {\n\tlong unsigned int base_pfn;\n\tlong unsigned int size_pfn;\n\tmtrr_type type;\n};\n\nstruct vbt_header {\n\tu8 signature[20];\n\tu16 version;\n\tu16 header_size;\n\tu16 vbt_size;\n\tu8 vbt_checksum;\n\tu8 reserved0;\n\tu32 bdb_offset;\n\tu32 aim_offset[4];\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[4];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcpu_fpu_config {\n\tunsigned int size;\n\tu64 features;\n};\n\nstruct vcpu_sev_es_state {\n\tstruct sev_es_save_area *vmsa;\n\tstruct ghcb *ghcb;\n\tu8 valid_bitmap[16];\n\tstruct kvm_host_map ghcb_map;\n\tbool received_first_sipi;\n\tunsigned int ap_reset_hold_type;\n\tu64 sw_scratch;\n\tvoid *ghcb_sa;\n\tu32 ghcb_sa_len;\n\tbool ghcb_sa_sync;\n\tbool ghcb_sa_free;\n\tu16 psc_idx;\n\tu16 psc_inflight;\n\tbool psc_2m;\n\tu64 ghcb_registered_gpa;\n\tstruct mutex snp_vmsa_mutex;\n\tgpa_t snp_vmsa_gpa;\n\tbool snp_ap_waiting_for_reset;\n\tbool snp_has_guest_vmsa;\n};\n\nstruct vcpu_svm {\n\tstruct kvm_vcpu vcpu;\n\tstruct vmcb *vmcb;\n\tstruct kvm_vmcb_info vmcb01;\n\tstruct kvm_vmcb_info *current_vmcb;\n\tu32 asid;\n\tu32 sysenter_esp_hi;\n\tu32 sysenter_eip_hi;\n\tuint64_t tsc_aux;\n\tu64 msr_decfg;\n\tu64 next_rip;\n\tu64 spec_ctrl;\n\tu64 tsc_ratio_msr;\n\tu64 virt_spec_ctrl;\n\tvoid *msrpm;\n\tulong nmi_iret_rip;\n\tstruct svm_nested_state nested;\n\tbool nmi_masked;\n\tbool awaiting_iret_completion;\n\tbool nmi_singlestep;\n\tu64 nmi_singlestep_guest_rflags;\n\tbool nmi_l1_to_l2;\n\tlong unsigned int soft_int_csbase;\n\tlong unsigned int soft_int_old_rip;\n\tlong unsigned int soft_int_next_rip;\n\tbool soft_int_injected;\n\tu32 ldr_reg;\n\tu32 dfr_reg;\n\tu64 avic_physical_id_entry;\n\tstruct list_head ir_list;\n\traw_spinlock_t ir_list_lock;\n\tstruct vcpu_sev_es_state sev_es;\n\tbool guest_state_loaded;\n\tbool x2avic_msrs_intercepted;\n\tbool lbr_msrs_intercepted;\n\tbool guest_gif;\n};\n\nunion vmx_exit_reason {\n\tstruct {\n\t\tu32 basic: 16;\n\t\tu32 reserved16: 1;\n\t\tu32 reserved17: 1;\n\t\tu32 reserved18: 1;\n\t\tu32 reserved19: 1;\n\t\tu32 reserved20: 1;\n\t\tu32 reserved21: 1;\n\t\tu32 reserved22: 1;\n\t\tu32 reserved23: 1;\n\t\tu32 reserved24: 1;\n\t\tu32 reserved25: 1;\n\t\tu32 bus_lock_detected: 1;\n\t\tu32 enclave_mode: 1;\n\t\tu32 smi_pending_mtf: 1;\n\t\tu32 smi_from_vmx_root: 1;\n\t\tu32 reserved30: 1;\n\t\tu32 failed_vmentry: 1;\n\t};\n\tu32 full;\n};\n\nstruct vcpu_vt {\n\tstruct pi_desc pi_desc;\n\tstruct list_head pi_wakeup_list;\n\tunion vmx_exit_reason exit_reason;\n\tlong unsigned int exit_qualification;\n\tu32 exit_intr_info;\n\tbool guest_state_loaded;\n\tbool emulation_required;\n\tu64 msr_host_kernel_gs_base;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vmx_uret_msr {\n\tbool load_into_hardware;\n\tu64 data;\n\tu64 mask;\n};\n\nstruct vmx_ve_information;\n\nstruct vcpu_vmx {\n\tstruct kvm_vcpu vcpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct vcpu_vt vt;\n\tu8 fail;\n\tu8 x2apic_msr_bitmap_mode;\n\tu32 idt_vectoring_info;\n\tulong rflags;\n\tstruct vmx_uret_msr guest_uret_msrs[7];\n\tbool guest_uret_msrs_loaded;\n\tu64 msr_guest_kernel_gs_base;\n\tu64 spec_ctrl;\n\tu32 msr_ia32_umwait_control;\n\tstruct loaded_vmcs vmcs01;\n\tstruct loaded_vmcs *loaded_vmcs;\n\tstruct msr_autoload msr_autoload;\n\tstruct vmx_msrs msr_autostore;\n\tstruct {\n\t\tint vm86_active;\n\t\tulong save_rflags;\n\t\tstruct kvm_segment segs[8];\n\t} rmode;\n\tstruct {\n\t\tu32 bitmask;\n\t\tstruct kvm_save_segment seg[8];\n\t} segment_cache;\n\tint vpid;\n\tstruct nested_vmx nested;\n\tunsigned int ple_window;\n\tbool ple_window_dirty;\n\tstruct page *pml_pg;\n\tu64 hv_deadline_tsc;\n\tu64 msr_ia32_feature_control;\n\tu64 msr_ia32_feature_control_valid_bits;\n\tu64 msr_ia32_sgxlepubkeyhash[4];\n\tu64 msr_ia32_mcu_opt_ctrl;\n\tbool disable_fb_clear;\n\tstruct pt_desc pt_desc;\n\tstruct lbr_desc lbr_desc;\n\tstruct vmx_ve_information *ve_info;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 max_cycles;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_exception_table_entry {\n\tint insn;\n\tint fixup;\n};\n\nstruct vdso_image {\n\tvoid *data;\n\tlong unsigned int size;\n\tlong unsigned int alt;\n\tlong unsigned int alt_len;\n\tlong unsigned int extable_base;\n\tlong unsigned int extable_len;\n\tconst void *extable;\n\tlong int sym_VDSO32_NOTE_MASK;\n\tlong int sym___kernel_sigreturn;\n\tlong int sym___kernel_rt_sigreturn;\n\tlong int sym___kernel_vsyscall;\n\tlong int sym_int80_landing_pad;\n\tlong int sym_vdso32_sigreturn_landing_pad;\n\tlong int sym_vdso32_rt_sigreturn_landing_pad;\n};\n\nstruct vdso_rng_data {\n\tu64 generation;\n\tu8 is_ready;\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ve_node {\n\tstruct rb_node rb;\n\tint prio;\n};\n\nstruct vector_cleanup {\n\tstruct hlist_head head;\n\tstruct timer_list timer;\n};\n\nstruct vers_iter {\n\tsize_t param_size;\n\tstruct dm_target_versions *vers;\n\tstruct dm_target_versions *old_vers;\n\tchar *end;\n\tuint32_t flags;\n};\n\nstruct vesafb_par {\n\tu32 pseudo_palette[256];\n\tresource_size_t base;\n\tresource_size_t size;\n\tint wc_cookie;\n\tstruct resource *region;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tbool is_firmware_default;\n\tunsigned int (*set_decode)(struct pci_dev *, bool);\n};\n\nstruct vga_switcheroo_client_ops {\n\tvoid (*set_gpu_state)(struct pci_dev *, enum vga_switcheroo_state);\n\tvoid (*reprobe)(struct pci_dev *);\n\tbool (*can_switch)(struct pci_dev *);\n\tvoid (*gpu_bound)(struct pci_dev *, enum vga_switcheroo_client_id);\n};\n\nstruct vgastate {\n\tvoid *vgabase;\n\tlong unsigned int membase;\n\t__u32 memsize;\n\t__u32 flags;\n\t__u32 depth;\n\t__u32 num_attr;\n\t__u32 num_crtc;\n\t__u32 num_gfx;\n\t__u32 num_seq;\n\tvoid *vidstate;\n};\n\nstruct vhost_task {\n\tbool (*fn)(void *);\n\tvoid (*handle_sigkill)(void *);\n\tvoid *data;\n\tstruct completion exited;\n\tlong unsigned int flags;\n\tstruct task_struct *task;\n\tstruct mutex exit_mutex;\n};\n\nstruct video_levels {\n\tu16 blank;\n\tu16 black;\n\tu8 burst;\n};\n\nstruct vif_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct net_device *dev;\n\tshort unsigned int vif_index;\n\tshort unsigned int vif_flags;\n\tu32 tb_id;\n};\n\nstruct vifctl {\n\tvifi_t vifc_vifi;\n\tunsigned char vifc_flags;\n\tunsigned char vifc_threshold;\n\tunsigned int vifc_rate_limit;\n\tunion {\n\t\tstruct in_addr vifc_lcl_addr;\n\t\tint vifc_lcl_ifindex;\n\t};\n\tstruct in_addr vifc_rmt_addr;\n};\n\nstruct viommu_dev {\n\tstruct iommu_device iommu;\n\tstruct device *dev;\n\tstruct virtio_device *vdev;\n\tstruct ida domain_ids;\n\tstruct virtqueue *vqs[2];\n\tspinlock_t request_lock;\n\tstruct list_head requests;\n\tvoid *evts;\n\tstruct iommu_domain_geometry geometry;\n\tu64 pgsize_bitmap;\n\tu32 first_domain;\n\tu32 last_domain;\n\tu32 identity_domain_id;\n\tu32 map_flags;\n\tu32 probe_size;\n};\n\nstruct viommu_domain {\n\tstruct iommu_domain domain;\n\tstruct viommu_dev *viommu;\n\tunsigned int id;\n\tu32 map_flags;\n\tspinlock_t mappings_lock;\n\tstruct rb_root_cached mappings;\n\tlong unsigned int nr_endpoints;\n};\n\nstruct viommu_endpoint {\n\tstruct device *dev;\n\tstruct viommu_dev *viommu;\n\tstruct viommu_domain *vdomain;\n\tstruct list_head resv_regions;\n};\n\nstruct virtio_iommu_fault {\n\t__u8 reason;\n\t__u8 reserved[3];\n\t__le32 flags;\n\t__le32 endpoint;\n\t__u8 reserved2[4];\n\t__le64 address;\n};\n\nstruct viommu_event {\n\tunion {\n\t\tu32 head;\n\t\tstruct virtio_iommu_fault fault;\n\t};\n};\n\nstruct viommu_mapping {\n\tphys_addr_t paddr;\n\tstruct interval_tree_node iova;\n\tu32 flags;\n};\n\nstruct viommu_request {\n\tstruct list_head list;\n\tvoid *writeback;\n\tunsigned int write_offset;\n\tunsigned int len;\n\tchar buf[0];\n};\n\nstruct viot_iommu;\n\nstruct viot_endpoint {\n\tunion {\n\t\tstruct {\n\t\t\tu16 segment_start;\n\t\t\tu16 segment_end;\n\t\t\tu16 bdf_start;\n\t\t\tu16 bdf_end;\n\t\t};\n\t\tu64 address;\n\t};\n\tu32 endpoint_id;\n\tstruct viot_iommu *viommu;\n\tstruct list_head list;\n};\n\nstruct viot_iommu {\n\tunsigned int offset;\n\tstruct fwnode_handle *fwnode;\n\tstruct list_head list;\n};\n\nstruct virtio_blk_outhdr {\n\t__virtio32 type;\n\t__virtio32 ioprio;\n\t__virtio64 sector;\n};\n\nstruct virtblk_req {\n\tstruct virtio_blk_outhdr out_hdr;\n\tunion {\n\t\tu8 status;\n\t\tstruct {\n\t\t\t__virtio64 sector;\n\t\t\tu8 status;\n\t\t} zone_append;\n\t} in_hdr;\n\tsize_t in_hdr_len;\n\tstruct sg_table sg_table;\n\tstruct scatterlist sg[0];\n};\n\nstruct virtio_9p_config {\n\t__virtio16 tag_len;\n\t__u8 tag[0];\n};\n\nstruct virtio_admin_cmd {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__le64 group_member_id;\n\tstruct scatterlist *data_sg;\n\tstruct scatterlist *result_sg;\n\tstruct completion completion;\n\tu32 result_sg_size;\n\tint ret;\n};\n\nstruct virtio_admin_cmd_cap_get_data {\n\t__le16 id;\n\t__u8 reserved[6];\n};\n\nstruct virtio_admin_cmd_cap_set_data {\n\t__le16 id;\n\t__u8 reserved[6];\n\t__u8 cap_specific_data[0];\n};\n\nstruct virtio_admin_cmd_dev_mode_set_data {\n\t__u8 flags;\n};\n\nstruct virtio_admin_cmd_resource_obj_cmd_hdr {\n\t__le16 type;\n\t__u8 reserved[2];\n\t__le32 id;\n};\n\nstruct virtio_dev_part_hdr {\n\t__le16 part_type;\n\t__u8 flags;\n\t__u8 reserved;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 offset;\n\t\t\t__le32 reserved;\n\t\t} pci_common_cfg;\n\t\tstruct {\n\t\t\t__le16 index;\n\t\t\t__u8 reserved[6];\n\t\t} vq_index;\n\t} selector;\n\t__le32 length;\n};\n\nstruct virtio_admin_cmd_dev_parts_get_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n\tstruct virtio_dev_part_hdr hdr_list[0];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_result {\n\tunion {\n\t\tstruct {\n\t\t\t__le32 size;\n\t\t\t__le32 reserved;\n\t\t} parts_size;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t} hdr_list_count;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t\tstruct virtio_dev_part_hdr hdrs[0];\n\t\t} hdr_list;\n\t};\n};\n\nstruct virtio_admin_cmd_hdr {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__u8 reserved1[12];\n\t__le64 group_member_id;\n};\n\nstruct virtio_admin_cmd_legacy_rd_data {\n\t__u8 offset;\n};\n\nstruct virtio_admin_cmd_legacy_wr_data {\n\t__u8 offset;\n\t__u8 reserved[7];\n\t__u8 registers[0];\n};\n\nstruct virtio_admin_cmd_notify_info_data {\n\t__u8 flags;\n\t__u8 bar;\n\t__u8 padding[6];\n\t__le64 offset;\n};\n\nstruct virtio_admin_cmd_notify_info_result {\n\tstruct virtio_admin_cmd_notify_info_data entries[4];\n};\n\nstruct virtio_admin_cmd_query_cap_id_result {\n\t__le64 supported_caps[1];\n};\n\nstruct virtio_admin_cmd_resource_obj_create_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__le64 flags;\n\t__u8 resource_obj_specific_data[0];\n};\n\nstruct virtio_admin_cmd_status {\n\t__le16 status;\n\t__le16 status_qualifier;\n\t__u8 reserved2[4];\n};\n\nstruct virtio_balloon_stat {\n\t__virtio16 tag;\n\t__virtio64 val;\n} __attribute__((packed));\n\nstruct virtio_balloon {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *inflate_vq;\n\tstruct virtqueue *deflate_vq;\n\tstruct virtqueue *stats_vq;\n\tstruct virtqueue *free_page_vq;\n\tstruct workqueue_struct *balloon_wq;\n\tstruct work_struct report_free_page_work;\n\tstruct work_struct update_balloon_stats_work;\n\tstruct work_struct update_balloon_size_work;\n\tspinlock_t stop_update_lock;\n\tbool stop_update;\n\tlong unsigned int config_read_bitmap;\n\tstruct list_head free_page_list;\n\tspinlock_t free_page_list_lock;\n\tlong unsigned int num_free_page_blocks;\n\tu32 cmd_id_received_cache;\n\t__virtio32 cmd_id_active;\n\t__virtio32 cmd_id_stop;\n\twait_queue_head_t acked;\n\tunsigned int num_pages;\n\tstruct balloon_dev_info vb_dev_info;\n\tstruct mutex balloon_lock;\n\tunsigned int num_pfns;\n\t__virtio32 pfns[256];\n\tstruct virtio_balloon_stat stats[16];\n\tstruct shrinker *shrinker;\n\tstruct notifier_block oom_nb;\n\tstruct virtqueue *reporting_vq;\n\tstruct page_reporting_dev_info pr_dev_info;\n\tspinlock_t wakeup_lock;\n\tbool processing_wakeup_event;\n\tu32 wakeup_signal_mask;\n};\n\nstruct virtio_balloon_config {\n\t__le32 num_pages;\n\t__le32 actual;\n\tunion {\n\t\t__le32 free_page_hint_cmd_id;\n\t\t__le32 free_page_report_cmd_id;\n\t};\n\t__le32 poison_val;\n};\n\nstruct virtio_blk_vq;\n\nstruct virtio_blk {\n\tstruct mutex vdev_mutex;\n\tstruct virtio_device *vdev;\n\tstruct gendisk *disk;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct work_struct config_work;\n\tint index;\n\tint num_vqs;\n\tint io_queues[3];\n\tstruct virtio_blk_vq *vqs;\n\tunsigned int zone_sectors;\n};\n\nstruct virtio_blk_geometry {\n\t__virtio16 cylinders;\n\t__u8 heads;\n\t__u8 sectors;\n};\n\nstruct virtio_blk_zoned_characteristics {\n\t__virtio32 zone_sectors;\n\t__virtio32 max_open_zones;\n\t__virtio32 max_active_zones;\n\t__virtio32 max_append_sectors;\n\t__virtio32 write_granularity;\n\t__u8 model;\n\t__u8 unused2[3];\n};\n\nstruct virtio_blk_config {\n\t__virtio64 capacity;\n\t__virtio32 size_max;\n\t__virtio32 seg_max;\n\tstruct virtio_blk_geometry geometry;\n\t__virtio32 blk_size;\n\t__u8 physical_block_exp;\n\t__u8 alignment_offset;\n\t__virtio16 min_io_size;\n\t__virtio32 opt_io_size;\n\t__u8 wce;\n\t__u8 unused;\n\t__virtio16 num_queues;\n\t__virtio32 max_discard_sectors;\n\t__virtio32 max_discard_seg;\n\t__virtio32 discard_sector_alignment;\n\t__virtio32 max_write_zeroes_sectors;\n\t__virtio32 max_write_zeroes_seg;\n\t__u8 write_zeroes_may_unmap;\n\t__u8 unused1[3];\n\t__virtio32 max_secure_erase_sectors;\n\t__virtio32 max_secure_erase_seg;\n\t__virtio32 secure_erase_sector_alignment;\n\tstruct virtio_blk_zoned_characteristics zoned;\n};\n\nstruct virtio_blk_discard_write_zeroes {\n\t__le64 sector;\n\t__le32 num_sectors;\n\t__le32 flags;\n};\n\nstruct virtio_blk_vq {\n\tstruct virtqueue *vq;\n\tspinlock_t lock;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct virtio_chan {\n\tbool inuse;\n\tspinlock_t lock;\n\tstruct p9_client *client;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *vq;\n\tint ring_bufs_avail;\n\twait_queue_head_t *vc_wq;\n\tlong unsigned int p9_max_pages;\n\tstruct scatterlist sg[128];\n\tchar *tag;\n\tstruct list_head chan_list;\n};\n\nstruct virtqueue_info;\n\nstruct virtio_shm_region;\n\nstruct virtio_config_ops {\n\tvoid (*get)(struct virtio_device *, unsigned int, void *, unsigned int);\n\tvoid (*set)(struct virtio_device *, unsigned int, const void *, unsigned int);\n\tu32 (*generation)(struct virtio_device *);\n\tu8 (*get_status)(struct virtio_device *);\n\tvoid (*set_status)(struct virtio_device *, u8);\n\tvoid (*reset)(struct virtio_device *);\n\tint (*find_vqs)(struct virtio_device *, unsigned int, struct virtqueue **, struct virtqueue_info *, struct irq_affinity *);\n\tvoid (*del_vqs)(struct virtio_device *);\n\tvoid (*synchronize_cbs)(struct virtio_device *);\n\tu64 (*get_features)(struct virtio_device *);\n\tvoid (*get_extended_features)(struct virtio_device *, u64 *);\n\tint (*finalize_features)(struct virtio_device *);\n\tconst char * (*bus_name)(struct virtio_device *);\n\tint (*set_vq_affinity)(struct virtqueue *, const struct cpumask *);\n\tconst struct cpumask * (*get_vq_affinity)(struct virtio_device *, int);\n\tbool (*get_shm_region)(struct virtio_device *, struct virtio_shm_region *, u8);\n\tint (*disable_vq_and_reset)(struct virtqueue *);\n\tint (*enable_vq_after_reset)(struct virtqueue *);\n};\n\nstruct virtio_console_config {\n\t__virtio16 cols;\n\t__virtio16 rows;\n\t__virtio32 max_nr_ports;\n\t__virtio32 emerg_wr;\n};\n\nstruct virtio_dev_parts_cap {\n\t__u8 get_parts_resource_objects_limit;\n\t__u8 set_parts_resource_objects_limit;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct vringh_config_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_map_ops;\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_dma_buf_ops {\n\tstruct dma_buf_ops ops;\n\tint (*device_attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*get_uuid)(struct dma_buf *, uuid_t *);\n};\n\nstruct virtio_driver {\n\tstruct device_driver driver;\n\tconst struct virtio_device_id *id_table;\n\tconst unsigned int *feature_table;\n\tunsigned int feature_table_size;\n\tconst unsigned int *feature_table_legacy;\n\tunsigned int feature_table_size_legacy;\n\tint (*validate)(struct virtio_device *);\n\tint (*probe)(struct virtio_device *);\n\tvoid (*scan)(struct virtio_device *);\n\tvoid (*remove)(struct virtio_device *);\n\tvoid (*config_changed)(struct virtio_device *);\n\tint (*freeze)(struct virtio_device *);\n\tint (*restore)(struct virtio_device *);\n\tint (*reset_prepare)(struct virtio_device *);\n\tint (*reset_done)(struct virtio_device *);\n\tvoid (*shutdown)(struct virtio_device *);\n};\n\nstruct virtio_fs_vq;\n\nstruct virtio_fs {\n\tstruct kobject kobj;\n\tstruct kobject *mqs_kobj;\n\tstruct list_head list;\n\tchar *tag;\n\tstruct virtio_fs_vq *vqs;\n\tunsigned int nvqs;\n\tunsigned int num_request_queues;\n\tstruct dax_device *dax_dev;\n\tunsigned int *mq_map;\n\tvoid *window_kaddr;\n\tphys_addr_t window_phys_addr;\n\tsize_t window_len;\n};\n\nstruct virtio_fs_config {\n\t__u8 tag[36];\n\t__le32 num_request_queues;\n};\n\nstruct virtio_fs_forget_req {\n\tstruct fuse_in_header ih;\n\tstruct fuse_forget_in arg;\n};\n\nstruct virtio_fs_forget {\n\tstruct list_head list;\n\tstruct virtio_fs_forget_req req;\n};\n\nstruct virtio_fs_req_work {\n\tstruct fuse_req *req;\n\tstruct virtio_fs_vq *fsvq;\n\tstruct work_struct done_work;\n};\n\nstruct virtio_fs_vq {\n\tspinlock_t lock;\n\tstruct virtqueue *vq;\n\tstruct work_struct done_work;\n\tstruct list_head queued_reqs;\n\tstruct list_head end_reqs;\n\tstruct work_struct dispatch_work;\n\tstruct fuse_dev *fud;\n\tbool connected;\n\tlong int in_flight;\n\tstruct completion in_flight_zero;\n\tstruct kobject *kobj;\n\tchar name[24];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct virtio_gpu_box {\n\t__le32 x;\n\t__le32 y;\n\t__le32 z;\n\t__le32 w;\n\t__le32 h;\n\t__le32 d;\n};\n\nstruct virtio_gpu_ctrl_hdr {\n\t__le32 type;\n\t__le32 flags;\n\t__le64 fence_id;\n\t__le32 ctx_id;\n\t__u8 ring_idx;\n\t__u8 padding[3];\n};\n\nstruct virtio_gpu_cmd_get_edid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 scanout;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_cmd_submit {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 size;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_config {\n\t__le32 events_read;\n\t__le32 events_clear;\n\t__le32 num_scanouts;\n\t__le32 num_capsets;\n};\n\nstruct virtio_gpu_ctx_create {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 nlen;\n\t__le32 context_init;\n\tchar debug_name[64];\n};\n\nstruct virtio_gpu_ctx_destroy {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n};\n\nstruct virtio_gpu_ctx_resource {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_cursor_pos {\n\t__le32 scanout_id;\n\t__le32 x;\n\t__le32 y;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_rect {\n\t__le32 x;\n\t__le32 y;\n\t__le32 width;\n\t__le32 height;\n};\n\nstruct virtio_gpu_display_one {\n\tstruct virtio_gpu_rect r;\n\t__le32 enabled;\n\t__le32 flags;\n};\n\nstruct virtio_gpu_update_cursor {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_cursor_pos pos;\n\t__le32 resource_id;\n\t__le32 hot_x;\n\t__le32 hot_y;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_output {\n\tint index;\n\tstruct drm_crtc crtc;\n\tstruct drm_connector conn;\n\tstruct drm_encoder enc;\n\tstruct virtio_gpu_display_one info;\n\tstruct virtio_gpu_update_cursor cursor;\n\tconst struct drm_edid *drm_edid;\n\tint cur_x;\n\tint cur_y;\n\tbool needs_modeset;\n};\n\nstruct virtio_gpu_queue {\n\tstruct virtqueue *vq;\n\tspinlock_t qlock;\n\twait_queue_head_t ack_queue;\n\tstruct work_struct dequeue_work;\n\tuint32_t seqno;\n};\n\nstruct virtio_gpu_fence_driver {\n\tatomic64_t last_fence_id;\n\tuint64_t current_fence_id;\n\tuint64_t context;\n\tstruct list_head fences;\n\tspinlock_t lock;\n};\n\nstruct virtio_shm_region {\n\tu64 addr;\n\tu64 len;\n};\n\nstruct virtio_gpu_drv_capset;\n\nstruct virtio_gpu_device {\n\tstruct drm_device *ddev;\n\tstruct virtio_device *vdev;\n\tstruct virtio_gpu_output outputs[16];\n\tuint32_t num_scanouts;\n\tstruct virtio_gpu_queue ctrlq;\n\tstruct virtio_gpu_queue cursorq;\n\tstruct kmem_cache *vbufs;\n\tatomic_t pending_commands;\n\tstruct ida resource_ida;\n\twait_queue_head_t resp_wq;\n\tspinlock_t display_info_lock;\n\tbool display_info_pending;\n\tstruct virtio_gpu_fence_driver fence_drv;\n\tstruct ida ctx_id_ida;\n\tbool has_virgl_3d;\n\tbool has_edid;\n\tbool has_indirect;\n\tbool has_resource_assign_uuid;\n\tbool has_resource_blob;\n\tbool has_host_visible;\n\tbool has_context_init;\n\tstruct virtio_shm_region host_visible_region;\n\tstruct drm_mm host_visible_mm;\n\tstruct work_struct config_changed_work;\n\tstruct work_struct obj_free_work;\n\tspinlock_t obj_free_lock;\n\tstruct list_head obj_free_list;\n\tstruct virtio_gpu_drv_capset *capsets;\n\tuint32_t num_capsets;\n\tuint64_t capset_id_mask;\n\tstruct list_head cap_cache;\n\tspinlock_t resource_export_lock;\n\tspinlock_t host_visible_lock;\n};\n\nstruct virtio_gpu_drv_cap_cache {\n\tstruct list_head head;\n\tvoid *caps_cache;\n\tuint32_t id;\n\tuint32_t version;\n\tuint32_t size;\n\tatomic_t is_valid;\n};\n\nstruct virtio_gpu_drv_capset {\n\tuint32_t id;\n\tuint32_t max_version;\n\tuint32_t max_size;\n};\n\nstruct virtio_gpu_fence_event;\n\nstruct virtio_gpu_fence {\n\tstruct dma_fence f;\n\tuint32_t ring_idx;\n\tuint64_t fence_id;\n\tbool emit_fence_info;\n\tstruct virtio_gpu_fence_event *e;\n\tstruct virtio_gpu_fence_driver *drv;\n\tstruct list_head node;\n};\n\nstruct virtio_gpu_fence_event {\n\tstruct drm_pending_event base;\n\tstruct drm_event event;\n};\n\nstruct virtio_gpu_fpriv {\n\tuint32_t ctx_id;\n\tuint32_t context_init;\n\tbool context_created;\n\tuint32_t num_rings;\n\tuint64_t base_fence_ctx;\n\tuint64_t ring_idx_mask;\n\tstruct mutex context_lock;\n\tchar debug_name[65];\n\tbool explicit_debug_name;\n};\n\nstruct virtio_gpu_framebuffer {\n\tstruct drm_framebuffer base;\n\tstruct virtio_gpu_fence *fence;\n};\n\nstruct virtio_gpu_get_capset {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 capset_id;\n\t__le32 capset_version;\n};\n\nstruct virtio_gpu_get_capset_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 capset_index;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_mem_entry {\n\t__le64 addr;\n\t__le32 length;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_object {\n\tstruct drm_gem_shmem_object base;\n\tstruct sg_table *sgt;\n\tuint32_t hw_res_handle;\n\tbool dumb;\n\tbool created;\n\tbool attached;\n\tbool host3d_blob;\n\tbool guest_blob;\n\tuint32_t blob_mem;\n\tuint32_t blob_flags;\n\tint uuid_state;\n\tuuid_t uuid;\n};\n\nstruct virtio_gpu_object_array {\n\tstruct ww_acquire_ctx ticket;\n\tstruct list_head next;\n\tu32 nents;\n\tu32 total;\n\tstruct drm_gem_object *objs[0];\n};\n\nstruct virtio_gpu_object_params {\n\tlong unsigned int size;\n\tbool dumb;\n\tbool virgl;\n\tbool blob;\n\tuint32_t format;\n\tuint32_t width;\n\tuint32_t height;\n\tuint32_t target;\n\tuint32_t bind;\n\tuint32_t depth;\n\tuint32_t array_size;\n\tuint32_t last_level;\n\tuint32_t nr_samples;\n\tuint32_t flags;\n\tuint32_t ctx_id;\n\tuint32_t blob_mem;\n\tuint32_t blob_flags;\n\tuint64_t blob_id;\n};\n\nstruct virtio_gpu_object_shmem {\n\tstruct virtio_gpu_object base;\n};\n\nstruct virtio_gpu_object_vram {\n\tstruct virtio_gpu_object base;\n\tuint32_t map_state;\n\tuint32_t map_info;\n\tstruct drm_mm_node vram_node;\n};\n\nstruct virtio_gpu_plane_state {\n\tstruct drm_plane_state base;\n\tstruct virtio_gpu_fence *fence;\n};\n\nstruct virtio_gpu_resource_assign_uuid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_attach_backing {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 nr_entries;\n};\n\nstruct virtio_gpu_resource_create_2d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 format;\n\t__le32 width;\n\t__le32 height;\n};\n\nstruct virtio_gpu_resource_create_3d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 target;\n\t__le32 format;\n\t__le32 bind;\n\t__le32 width;\n\t__le32 height;\n\t__le32 depth;\n\t__le32 array_size;\n\t__le32 last_level;\n\t__le32 nr_samples;\n\t__le32 flags;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_create_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 blob_mem;\n\t__le32 blob_flags;\n\t__le32 nr_entries;\n\t__le64 blob_id;\n\t__le64 size;\n};\n\nstruct virtio_gpu_resource_detach_backing {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_flush {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_map_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n\t__le64 offset;\n};\n\nstruct virtio_gpu_resource_unmap_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_unref {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resp_capset {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__u8 capset_data[0];\n};\n\nstruct virtio_gpu_resp_capset_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 capset_id;\n\t__le32 capset_max_version;\n\t__le32 capset_max_size;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resp_display_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_display_one pmodes[16];\n};\n\nstruct virtio_gpu_resp_edid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 size;\n\t__le32 padding;\n\t__u8 edid[1024];\n};\n\nstruct virtio_gpu_resp_map_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__u32 map_info;\n\t__u32 padding;\n};\n\nstruct virtio_gpu_resp_resource_uuid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__u8 uuid[16];\n};\n\nstruct virtio_gpu_set_scanout {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le32 scanout_id;\n\t__le32 resource_id;\n};\n\nstruct virtio_gpu_set_scanout_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le32 scanout_id;\n\t__le32 resource_id;\n\t__le32 width;\n\t__le32 height;\n\t__le32 format;\n\t__le32 padding;\n\t__le32 strides[4];\n\t__le32 offsets[4];\n};\n\nstruct virtio_gpu_submit_post_dep;\n\nstruct virtio_gpu_submit {\n\tstruct virtio_gpu_submit_post_dep *post_deps;\n\tunsigned int num_out_syncobjs;\n\tstruct drm_syncobj **in_syncobjs;\n\tunsigned int num_in_syncobjs;\n\tstruct virtio_gpu_object_array *buflist;\n\tstruct drm_virtgpu_execbuffer *exbuf;\n\tstruct virtio_gpu_fence *out_fence;\n\tstruct virtio_gpu_fpriv *vfpriv;\n\tstruct virtio_gpu_device *vgdev;\n\tstruct sync_file *sync_file;\n\tstruct drm_file *file;\n\tint out_fence_fd;\n\tu64 fence_ctx;\n\tu32 ring_idx;\n\tvoid *buf;\n};\n\nstruct virtio_gpu_submit_post_dep {\n\tstruct drm_syncobj *syncobj;\n\tstruct dma_fence_chain *chain;\n\tu64 point;\n};\n\nstruct virtio_gpu_transfer_host_3d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_box box;\n\t__le64 offset;\n\t__le32 resource_id;\n\t__le32 level;\n\t__le32 stride;\n\t__le32 layer_stride;\n};\n\nstruct virtio_gpu_transfer_to_host_2d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le64 offset;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_vbuffer;\n\ntypedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *, struct virtio_gpu_vbuffer *);\n\nstruct virtio_gpu_vbuffer {\n\tchar *buf;\n\tint size;\n\tvoid *data_buf;\n\tuint32_t data_size;\n\tchar *resp_buf;\n\tint resp_size;\n\tvirtio_gpu_resp_cb resp_cb;\n\tvoid *resp_cb_data;\n\tstruct virtio_gpu_object_array *objs;\n\tstruct list_head list;\n\tuint32_t seqno;\n};\n\nstruct virtio_input_event {\n\t__le16 type;\n\t__le16 code;\n\t__le32 value;\n};\n\nstruct virtio_input {\n\tstruct virtio_device *vdev;\n\tstruct input_dev *idev;\n\tchar name[64];\n\tchar serial[64];\n\tchar phys[64];\n\tstruct virtqueue *evt;\n\tstruct virtqueue *sts;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_input_event evts[64];\n\t__u8 __cacheline_group_end__[0];\n\tspinlock_t lock;\n\tbool ready;\n};\n\nstruct virtio_input_absinfo {\n\t__le32 min;\n\t__le32 max;\n\t__le32 fuzz;\n\t__le32 flat;\n\t__le32 res;\n};\n\nstruct virtio_input_devids {\n\t__le16 bustype;\n\t__le16 vendor;\n\t__le16 product;\n\t__le16 version;\n};\n\nstruct virtio_input_config {\n\t__u8 select;\n\t__u8 subsel;\n\t__u8 size;\n\t__u8 reserved[5];\n\tunion {\n\t\tchar string[128];\n\t\t__u8 bitmap[128];\n\t\tstruct virtio_input_absinfo abs;\n\t\tstruct virtio_input_devids ids;\n\t} u;\n};\n\nstruct virtio_iommu_range_64 {\n\t__le64 start;\n\t__le64 end;\n};\n\nstruct virtio_iommu_range_32 {\n\t__le32 start;\n\t__le32 end;\n};\n\nstruct virtio_iommu_config {\n\t__le64 page_size_mask;\n\tstruct virtio_iommu_range_64 input_range;\n\tstruct virtio_iommu_range_32 domain_range;\n\t__le32 probe_size;\n\t__u8 bypass;\n\t__u8 reserved[3];\n};\n\nstruct virtio_iommu_probe_property {\n\t__le16 type;\n\t__le16 length;\n};\n\nstruct virtio_iommu_probe_resv_mem {\n\tstruct virtio_iommu_probe_property head;\n\t__u8 subtype;\n\t__u8 reserved[3];\n\t__le64 start;\n\t__le64 end;\n};\n\nstruct virtio_iommu_req_head {\n\t__u8 type;\n\t__u8 reserved[3];\n};\n\nstruct virtio_iommu_req_tail {\n\t__u8 status;\n\t__u8 reserved[3];\n};\n\nstruct virtio_iommu_req_attach {\n\tstruct virtio_iommu_req_head head;\n\t__le32 domain;\n\t__le32 endpoint;\n\t__le32 flags;\n\t__u8 reserved[4];\n\tstruct virtio_iommu_req_tail tail;\n};\n\nstruct virtio_iommu_req_detach {\n\tstruct virtio_iommu_req_head head;\n\t__le32 domain;\n\t__le32 endpoint;\n\t__u8 reserved[8];\n\tstruct virtio_iommu_req_tail tail;\n};\n\nstruct virtio_iommu_req_map {\n\tstruct virtio_iommu_req_head head;\n\t__le32 domain;\n\t__le64 virt_start;\n\t__le64 virt_end;\n\t__le64 phys_start;\n\t__le32 flags;\n\tstruct virtio_iommu_req_tail tail;\n};\n\nstruct virtio_iommu_req_probe {\n\tstruct virtio_iommu_req_head head;\n\t__le32 endpoint;\n\t__u8 reserved[64];\n\t__u8 properties[0];\n};\n\nstruct virtio_iommu_req_unmap {\n\tstruct virtio_iommu_req_head head;\n\t__le32 domain;\n\t__le64 virt_start;\n\t__le64 virt_end;\n\t__u8 reserved[4];\n\tstruct virtio_iommu_req_tail tail;\n};\n\nstruct virtio_map_ops {\n\tdma_addr_t (*map_page)(union virtio_map, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid * (*alloc)(union virtio_map, size_t, dma_addr_t *, gfp_t);\n\tvoid (*free)(union virtio_map, size_t, void *, dma_addr_t, long unsigned int);\n\tbool (*need_sync)(union virtio_map, dma_addr_t);\n\tint (*mapping_error)(union virtio_map, dma_addr_t);\n\tsize_t (*max_mapping_size)(union virtio_map);\n};\n\nstruct virtio_mmio_device {\n\tstruct virtio_device vdev;\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tlong unsigned int version;\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1 {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\tunion {\n\t\tstruct {\n\t\t\t__virtio16 csum_start;\n\t\t\t__virtio16 csum_offset;\n\t\t};\n\t\tstruct {\n\t\t\t__virtio16 start;\n\t\t\t__virtio16 offset;\n\t\t} csum;\n\t\tstruct {\n\t\t\t__le16 segments;\n\t\t\t__le16 dup_acks;\n\t\t} rsc;\n\t};\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1_hash {\n\tstruct virtio_net_hdr_v1 hdr;\n\t__le16 hash_value_lo;\n\t__le16 hash_value_hi;\n\t__le16 hash_report;\n\t__le16 padding;\n};\n\nstruct virtio_net_hdr_v1_hash_tunnel {\n\tstruct virtio_net_hdr_v1_hash hash_hdr;\n\t__le16 outer_th_offset;\n\t__le16 inner_nh_offset;\n};\n\nstruct virtio_net_common_hdr {\n\tunion {\n\t\tstruct virtio_net_hdr hdr;\n\t\tstruct virtio_net_hdr_mrg_rxbuf mrg_hdr;\n\t\tstruct virtio_net_hdr_v1_hash hash_v1_hdr;\n\t\tstruct virtio_net_hdr_v1_hash_tunnel tnl_hdr;\n\t};\n};\n\nstruct virtio_net_config {\n\t__u8 mac[6];\n\t__virtio16 status;\n\t__virtio16 max_virtqueue_pairs;\n\t__virtio16 mtu;\n\t__le32 speed;\n\t__u8 duplex;\n\t__u8 rss_max_key_size;\n\t__le16 rss_max_indirection_table_length;\n\t__le32 supported_hash_types;\n};\n\nstruct virtio_net_ctrl_coal {\n\t__le32 max_packets;\n\t__le32 max_usecs;\n};\n\nstruct virtio_net_ctrl_coal_rx {\n\t__le32 rx_max_packets;\n\t__le32 rx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_tx {\n\t__le32 tx_max_packets;\n\t__le32 tx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_vq {\n\t__le16 vqn;\n\t__le16 reserved;\n\tstruct virtio_net_ctrl_coal coal;\n};\n\nstruct virtio_net_ctrl_mac {\n\t__virtio32 entries;\n\t__u8 macs[0];\n};\n\nstruct virtio_net_ctrl_mq {\n\t__virtio16 virtqueue_pairs;\n};\n\nstruct virtio_net_ctrl_queue_stats {\n\tstruct {\n\t\t__le16 vq_index;\n\t\t__le16 reserved[3];\n\t\t__le64 types_bitmap[1];\n\t} stats[1];\n};\n\nstruct virtio_net_rss_config_hdr {\n\t__le32 hash_types;\n\t__le16 indirection_table_mask;\n\t__le16 unclassified_queue;\n\t__le16 indirection_table[0];\n};\n\nstruct virtio_net_rss_config_trailer {\n\t__le16 max_tx_vq;\n\t__u8 hash_key_length;\n\t__u8 hash_key_data[0];\n};\n\nstruct virtio_net_stats_capabilities {\n\t__le64 supported_stats_types[1];\n};\n\nstruct virtio_net_stats_reply_hdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__le16 vq_index;\n\t__le16 reserved1;\n\t__le16 size;\n};\n\nstruct virtio_pci_vq_info;\n\nstruct virtio_pci_admin_vq {\n\tstruct virtio_pci_vq_info *info;\n\tspinlock_t lock;\n\tu64 supported_cmds;\n\tu64 supported_caps;\n\tu8 max_dev_parts_objects;\n\tstruct ida dev_parts_ida;\n\tchar name[10];\n\tu16 vq_index;\n};\n\nstruct virtio_pci_common_cfg {\n\t__le32 device_feature_select;\n\t__le32 device_feature;\n\t__le32 guest_feature_select;\n\t__le32 guest_feature;\n\t__le16 msix_config;\n\t__le16 num_queues;\n\t__u8 device_status;\n\t__u8 config_generation;\n\t__le16 queue_select;\n\t__le16 queue_size;\n\t__le16 queue_msix_vector;\n\t__le16 queue_enable;\n\t__le16 queue_notify_off;\n\t__le32 queue_desc_lo;\n\t__le32 queue_desc_hi;\n\t__le32 queue_avail_lo;\n\t__le32 queue_avail_hi;\n\t__le32 queue_used_lo;\n\t__le32 queue_used_hi;\n};\n\nstruct virtio_pci_legacy_device {\n\tstruct pci_dev *pci_dev;\n\tu8 *isr;\n\tvoid *ioaddr;\n\tstruct virtio_device_id id;\n};\n\nstruct virtio_pci_modern_device {\n\tstruct pci_dev *pci_dev;\n\tstruct virtio_pci_common_cfg *common;\n\tvoid *device;\n\tvoid *notify_base;\n\tresource_size_t notify_pa;\n\tu8 *isr;\n\tsize_t notify_len;\n\tsize_t device_len;\n\tsize_t common_len;\n\tint notify_map_cap;\n\tu32 notify_offset_multiplier;\n\tint modern_bars;\n\tstruct virtio_device_id id;\n\tint (*device_id_check)(struct pci_dev *);\n\tu64 dma_mask;\n};\n\nstruct virtio_pci_device {\n\tstruct virtio_device vdev;\n\tstruct pci_dev *pci_dev;\n\tunion {\n\t\tstruct virtio_pci_legacy_device ldev;\n\t\tstruct virtio_pci_modern_device mdev;\n\t};\n\tbool is_legacy;\n\tu8 *isr;\n\tspinlock_t lock;\n\tstruct list_head virtqueues;\n\tstruct list_head slow_virtqueues;\n\tstruct virtio_pci_vq_info **vqs;\n\tstruct virtio_pci_admin_vq admin_vq;\n\tint msix_enabled;\n\tint intx_enabled;\n\tcpumask_var_t *msix_affinity_masks;\n\tchar (*msix_names)[256];\n\tunsigned int msix_vectors;\n\tunsigned int msix_used_vectors;\n\tbool per_vq_vectors;\n\tstruct virtqueue * (*setup_vq)(struct virtio_pci_device *, struct virtio_pci_vq_info *, unsigned int, void (*)(struct virtqueue *), const char *, bool, u16);\n\tvoid (*del_vq)(struct virtio_pci_vq_info *);\n\tu16 (*config_vector)(struct virtio_pci_device *, u16);\n\tint (*avq_index)(struct virtio_device *, u16 *, u16 *);\n};\n\nstruct virtio_pci_modern_common_cfg {\n\tstruct virtio_pci_common_cfg cfg;\n\t__le16 queue_notify_data;\n\t__le16 queue_reset;\n\t__le16 admin_queue_index;\n\t__le16 admin_queue_num;\n};\n\nstruct virtio_pci_vq_info {\n\tstruct virtqueue *vq;\n\tstruct list_head node;\n\tunsigned int msix_vector;\n};\n\nstruct virtio_resource_obj_dev_parts {\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_scsi;\n\nstruct virtio_scsi_event;\n\nstruct virtio_scsi_event_node {\n\tstruct virtio_scsi *vscsi;\n\tstruct virtio_scsi_event *event;\n\tstruct work_struct work;\n};\n\nstruct virtio_scsi_vq {\n\tspinlock_t vq_lock;\n\tstruct virtqueue *vq;\n};\n\nstruct virtio_scsi_event {\n\t__virtio32 event;\n\t__u8 lun[8];\n\t__virtio32 reason;\n};\n\nstruct virtio_scsi {\n\tstruct virtio_device *vdev;\n\tstruct virtio_scsi_event_node event_list[8];\n\tu32 num_queues;\n\tint io_queues[3];\n\tstruct hlist_node node;\n\tbool stop_events;\n\tstruct virtio_scsi_vq ctrl_vq;\n\tstruct virtio_scsi_vq event_vq;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_scsi_event events[8];\n\t__u8 __cacheline_group_end__[0];\n\tstruct virtio_scsi_vq req_vqs[0];\n};\n\nstruct virtio_scsi_cmd_req {\n\t__u8 lun[8];\n\t__virtio64 tag;\n\t__u8 task_attr;\n\t__u8 prio;\n\t__u8 crn;\n\t__u8 cdb[32];\n} __attribute__((packed));\n\nstruct virtio_scsi_cmd_req_pi {\n\t__u8 lun[8];\n\t__virtio64 tag;\n\t__u8 task_attr;\n\t__u8 prio;\n\t__u8 crn;\n\t__virtio32 pi_bytesout;\n\t__virtio32 pi_bytesin;\n\t__u8 cdb[32];\n} __attribute__((packed));\n\nstruct virtio_scsi_ctrl_tmf_req {\n\t__virtio32 type;\n\t__virtio32 subtype;\n\t__u8 lun[8];\n\t__virtio64 tag;\n};\n\nstruct virtio_scsi_ctrl_an_req {\n\t__virtio32 type;\n\t__u8 lun[8];\n\t__virtio32 event_requested;\n};\n\nstruct virtio_scsi_cmd_resp {\n\t__virtio32 sense_len;\n\t__virtio32 resid;\n\t__virtio16 status_qualifier;\n\t__u8 status;\n\t__u8 response;\n\t__u8 sense[96];\n};\n\nstruct virtio_scsi_ctrl_tmf_resp {\n\t__u8 response;\n};\n\nstruct virtio_scsi_ctrl_an_resp {\n\t__virtio32 event_actual;\n\t__u8 response;\n} __attribute__((packed));\n\nstruct virtio_scsi_cmd {\n\tstruct scsi_cmnd *sc;\n\tstruct completion *comp;\n\tunion {\n\t\tstruct virtio_scsi_cmd_req cmd;\n\t\tstruct virtio_scsi_cmd_req_pi cmd_pi;\n\t\tstruct virtio_scsi_ctrl_tmf_req tmf;\n\t\tstruct virtio_scsi_ctrl_an_req an;\n\t} req;\n\tunion {\n\t\tstruct virtio_scsi_cmd_resp cmd;\n\t\tstruct virtio_scsi_ctrl_tmf_resp tmf;\n\t\tstruct virtio_scsi_ctrl_an_resp an;\n\t\tstruct virtio_scsi_event evt;\n\t} resp;\n\tlong: 64;\n} __attribute__((packed));\n\nstruct virtio_scsi_config {\n\t__virtio32 num_queues;\n\t__virtio32 seg_max;\n\t__virtio32 max_sectors;\n\t__virtio32 cmd_per_lun;\n\t__virtio32 event_info_size;\n\t__virtio32 sense_size;\n\t__virtio32 cdb_size;\n\t__virtio16 max_channel;\n\t__virtio16 max_target;\n\t__virtio32 max_lun;\n};\n\nstruct vsock_sock;\n\nstruct vsock_transport_recv_notify_data;\n\nstruct vsock_transport_send_notify_data;\n\nstruct vsock_transport {\n\tstruct module *module;\n\tint (*init)(struct vsock_sock *, struct vsock_sock *);\n\tvoid (*destruct)(struct vsock_sock *);\n\tvoid (*release)(struct vsock_sock *);\n\tint (*cancel_pkt)(struct vsock_sock *);\n\tint (*connect)(struct vsock_sock *);\n\tint (*dgram_bind)(struct vsock_sock *, struct sockaddr_vm *);\n\tint (*dgram_dequeue)(struct vsock_sock *, struct msghdr *, size_t, int);\n\tint (*dgram_enqueue)(struct vsock_sock *, struct sockaddr_vm *, struct msghdr *, size_t);\n\tbool (*dgram_allow)(struct vsock_sock *, u32, u32);\n\tssize_t (*stream_dequeue)(struct vsock_sock *, struct msghdr *, size_t, int);\n\tssize_t (*stream_enqueue)(struct vsock_sock *, struct msghdr *, size_t);\n\ts64 (*stream_has_data)(struct vsock_sock *);\n\ts64 (*stream_has_space)(struct vsock_sock *);\n\tu64 (*stream_rcvhiwat)(struct vsock_sock *);\n\tbool (*stream_is_active)(struct vsock_sock *);\n\tbool (*stream_allow)(struct vsock_sock *, u32, u32);\n\tssize_t (*seqpacket_dequeue)(struct vsock_sock *, struct msghdr *, int);\n\tint (*seqpacket_enqueue)(struct vsock_sock *, struct msghdr *, size_t);\n\tbool (*seqpacket_allow)(struct vsock_sock *, u32);\n\tu32 (*seqpacket_has_data)(struct vsock_sock *);\n\tint (*notify_poll_in)(struct vsock_sock *, size_t, bool *);\n\tint (*notify_poll_out)(struct vsock_sock *, size_t, bool *);\n\tint (*notify_recv_init)(struct vsock_sock *, size_t, struct vsock_transport_recv_notify_data *);\n\tint (*notify_recv_pre_block)(struct vsock_sock *, size_t, struct vsock_transport_recv_notify_data *);\n\tint (*notify_recv_pre_dequeue)(struct vsock_sock *, size_t, struct vsock_transport_recv_notify_data *);\n\tint (*notify_recv_post_dequeue)(struct vsock_sock *, size_t, ssize_t, bool, struct vsock_transport_recv_notify_data *);\n\tint (*notify_send_init)(struct vsock_sock *, struct vsock_transport_send_notify_data *);\n\tint (*notify_send_pre_block)(struct vsock_sock *, struct vsock_transport_send_notify_data *);\n\tint (*notify_send_pre_enqueue)(struct vsock_sock *, struct vsock_transport_send_notify_data *);\n\tint (*notify_send_post_enqueue)(struct vsock_sock *, ssize_t, struct vsock_transport_send_notify_data *);\n\tvoid (*notify_buffer_size)(struct vsock_sock *, u64 *);\n\tint (*notify_set_rcvlowat)(struct vsock_sock *, int);\n\tssize_t (*unsent_bytes)(struct vsock_sock *);\n\tint (*shutdown)(struct vsock_sock *, int);\n\tu32 (*get_local_cid)(void);\n\tint (*read_skb)(struct vsock_sock *, skb_read_actor_t);\n\tbool (*msgzerocopy_allow)(void);\n};\n\nstruct virtio_transport {\n\tstruct vsock_transport transport;\n\tint (*send_pkt)(struct sk_buff *, struct net *);\n\tbool (*can_msgzerocopy)(int);\n};\n\nstruct virtio_vsock_event {\n\t__le32 id;\n};\n\nstruct virtio_vsock {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *vqs[3];\n\tstruct work_struct tx_work;\n\tstruct work_struct rx_work;\n\tstruct work_struct event_work;\n\tstruct mutex tx_lock;\n\tbool tx_run;\n\tlong: 0;\n\tstruct work_struct send_pkt_work;\n\tstruct sk_buff_head send_pkt_queue;\n\tatomic_t queued_replies;\n\tlong: 0;\n\tstruct mutex rx_lock;\n\tbool rx_run;\n\tint: 0;\n\tint rx_buf_nr;\n\tint rx_buf_max_nr;\n\tu32 guest_cid;\n\tbool seqpacket_allow;\n\tlong: 0;\n\tstruct scatterlist *out_sgs[18];\n\tstruct scatterlist out_bufs[18];\n\tstruct mutex event_lock;\n\tbool event_run;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_vsock_event event_list[8];\n\t__u8 __cacheline_group_end__[0];\n\tlong: 0;\n} __attribute__((packed));\n\nstruct virtio_vsock_hdr {\n\t__le64 src_cid;\n\t__le64 dst_cid;\n\t__le32 src_port;\n\t__le32 dst_port;\n\t__le32 len;\n\t__le16 type;\n\t__le16 op;\n\t__le32 flags;\n\t__le32 buf_alloc;\n\t__le32 fwd_cnt;\n} __attribute__((packed));\n\nstruct virtio_vsock_pkt_info {\n\tu32 remote_cid;\n\tu32 remote_port;\n\tstruct vsock_sock *vsk;\n\tstruct msghdr *msg;\n\tstruct net *net;\n\tu32 pkt_len;\n\tu16 type;\n\tu16 op;\n\tu32 flags;\n\tbool reply;\n};\n\nstruct virtio_vsock_skb_cb {\n\tbool reply;\n\tbool tap_delivered;\n\tu32 offset;\n};\n\nstruct virtio_vsock_sock {\n\tstruct vsock_sock *vsk;\n\tspinlock_t tx_lock;\n\tspinlock_t rx_lock;\n\tu32 tx_cnt;\n\tu32 peer_fwd_cnt;\n\tu32 peer_buf_alloc;\n\tsize_t bytes_unsent;\n\tu32 fwd_cnt;\n\tu32 last_fwd_cnt;\n\tu32 rx_bytes;\n\tu32 buf_alloc;\n\tu32 buf_used;\n\tstruct sk_buff_head rx_queue;\n\tu32 msg_count;\n};\n\nstruct virtnet_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *cvq;\n\tstruct net_device *dev;\n\tstruct send_queue *sq;\n\tstruct receive_queue *rq;\n\tunsigned int status;\n\tu16 max_queue_pairs;\n\tu16 curr_queue_pairs;\n\tu16 xdp_queue_pairs;\n\tbool xdp_enabled;\n\tbool big_packets;\n\tunsigned int big_packets_num_skbfrags;\n\tbool mergeable_rx_bufs;\n\tbool has_rss;\n\tbool has_rss_hash_report;\n\tu8 rss_key_size;\n\tu16 rss_indir_table_size;\n\tu32 rss_hash_types_supported;\n\tu32 rss_hash_types_saved;\n\tbool has_cvq;\n\tstruct mutex cvq_lock;\n\tbool any_header_sg;\n\tu8 hdr_len;\n\tbool tx_tnl;\n\tbool rx_tnl;\n\tbool rx_tnl_csum;\n\tstruct work_struct config_work;\n\tstruct work_struct rx_mode_work;\n\tbool rx_mode_work_enabled;\n\tbool affinity_hint_set;\n\tstruct hlist_node node;\n\tstruct hlist_node node_dead;\n\tstruct control_buf *ctrl;\n\tu8 duplex;\n\tu32 speed;\n\tbool rx_dim_enabled;\n\tstruct virtnet_interrupt_coalesce intr_coal_tx;\n\tstruct virtnet_interrupt_coalesce intr_coal_rx;\n\tlong unsigned int guest_offloads;\n\tlong unsigned int guest_offloads_capable;\n\tstruct failover *failover;\n\tu64 device_stats_cap;\n\tstruct virtio_net_rss_config_hdr *rss_hdr;\n\tunion {\n\t\tstruct virtio_net_rss_config_trailer rss_trailer;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[3];\n\t\t\tu8 rss_hash_key_data[40];\n\t\t};\n\t};\n};\n\nstruct virtnet_rq_dma {\n\tdma_addr_t addr;\n\tu32 ref;\n\tu16 len;\n\tu16 need_sync;\n};\n\nstruct virtnet_sq_free_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 napi_packets;\n\tu64 napi_bytes;\n\tu64 xsk;\n};\n\nstruct virtnet_stat_desc {\n\tchar desc[32];\n\tsize_t offset;\n\tsize_t qstat_offset;\n};\n\nstruct virtnet_stats_ctx {\n\tbool to_qstat;\n\tu32 desc_num[3];\n\tu64 bitmap[3];\n\tu32 size[3];\n\tu64 *data;\n};\n\nstruct virtqueue {\n\tstruct list_head list;\n\tvoid (*callback)(struct virtqueue *);\n\tconst char *name;\n\tstruct virtio_device *vdev;\n\tunsigned int index;\n\tunsigned int num_free;\n\tunsigned int num_max;\n\tbool reset;\n\tvoid *priv;\n};\n\ntypedef void vq_callback_t(struct virtqueue *);\n\nstruct virtqueue_info {\n\tconst char *name;\n\tvq_callback_t *callback;\n\tbool ctx;\n};\n\nstruct vring_virtqueue;\n\nstruct virtqueue_ops {\n\tint (*add)(struct vring_virtqueue *, struct scatterlist **, unsigned int, unsigned int, unsigned int, void *, void *, bool, gfp_t, long unsigned int);\n\tvoid * (*get)(struct vring_virtqueue *, unsigned int *, void **);\n\tbool (*kick_prepare)(struct vring_virtqueue *);\n\tvoid (*disable_cb)(struct vring_virtqueue *);\n\tbool (*enable_cb_delayed)(struct vring_virtqueue *);\n\tunsigned int (*enable_cb_prepare)(struct vring_virtqueue *);\n\tbool (*poll)(const struct vring_virtqueue *, unsigned int);\n\tvoid * (*detach_unused_buf)(struct vring_virtqueue *);\n\tbool (*more_used)(const struct vring_virtqueue *);\n\tint (*resize)(struct vring_virtqueue *, u32);\n\tvoid (*reset)(struct vring_virtqueue *);\n};\n\nstruct virtual_engine {\n\tstruct intel_engine_cs base;\n\tstruct intel_context context;\n\tstruct rcu_work rcu;\n\tstruct i915_request *request;\n\tstruct ve_node nodes[27];\n\tunsigned int num_siblings;\n\tstruct intel_engine_cs *siblings[0];\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vlv_s0ix_state {\n\tu32 wr_watermark;\n\tu32 gfx_prio_ctrl;\n\tu32 arb_mode;\n\tu32 gfx_pend_tlb0;\n\tu32 gfx_pend_tlb1;\n\tu32 lra_limits[13];\n\tu32 media_max_req_count;\n\tu32 gfx_max_req_count;\n\tu32 render_hwsp;\n\tu32 ecochk;\n\tu32 bsd_hwsp;\n\tu32 blt_hwsp;\n\tu32 tlb_rd_addr;\n\tu32 g3dctl;\n\tu32 gsckgctl;\n\tu32 mbctl;\n\tu32 ucgctl1;\n\tu32 ucgctl3;\n\tu32 rcgctl1;\n\tu32 rcgctl2;\n\tu32 rstctl;\n\tu32 misccpctl;\n\tu32 gfxpause;\n\tu32 rpdeuhwtc;\n\tu32 rpdeuc;\n\tu32 ecobus;\n\tu32 pwrdwnupctl;\n\tu32 rp_down_timeout;\n\tu32 rp_deucsw;\n\tu32 rcubmabdtmr;\n\tu32 rcedata;\n\tu32 spare2gh;\n\tu32 gt_imr;\n\tu32 gt_ier;\n\tu32 pm_imr;\n\tu32 pm_ier;\n\tu32 gt_scratch[8];\n\tu32 tilectl;\n\tu32 gt_fifoctl;\n\tu32 gtlc_wake_ctrl;\n\tu32 gtlc_survive;\n\tu32 pmwgicz;\n\tu32 gu_ctl0;\n\tu32 gu_ctl1;\n\tu32 pcbr;\n\tu32 clock_gate_dis2;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {};\n\nstruct vma_numab_state;\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tunsigned int vm_lock_seq;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct mempolicy *vm_policy;\n\tstruct vma_numab_state *numab_state;\n\trefcount_t vm_refcnt;\n\tstruct lockdep_map vmlock_dep_map;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n\tstruct pfnmap_track_ctx *pfnmap_track_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[97];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n\tint (*set_policy)(struct vm_area_struct *, struct mempolicy *);\n\tstruct mempolicy * (*get_policy)(struct vm_area_struct *, long unsigned int, long unsigned int *);\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct vm_stack {\n\tstruct callback_head rcu;\n\tstruct vm_struct *stack_vm_area;\n};\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int page_order;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_exclude_readers_state {\n\tstruct vm_area_struct *vma;\n\tint state;\n\tbool detaching;\n\tbool detached;\n\tbool exclusive;\n};\n\nstruct vma_list {\n\tstruct vm_area_struct *vma;\n\tstruct list_head head;\n\trefcount_t mmap_count;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_numab_state {\n\tlong unsigned int next_scan;\n\tlong unsigned int pids_active_reset;\n\tlong unsigned int pids_active[2];\n\tint start_scan_seq;\n\tint prev_scan_seq;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[16];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmap_pfn_data {\n\tlong unsigned int *pfns;\n\tpgprot_t prot;\n\tunsigned int idx;\n};\n\nstruct vmcb_control_area {\n\tu32 intercepts[6];\n\tu32 reserved_1[9];\n\tu16 pause_filter_thresh;\n\tu16 pause_filter_count;\n\tu64 iopm_base_pa;\n\tu64 msrpm_base_pa;\n\tu64 tsc_offset;\n\tu32 asid;\n\tu8 tlb_ctl;\n\tu8 erap_ctl;\n\tu8 reserved_2[2];\n\tu32 int_ctl;\n\tu32 int_vector;\n\tu32 int_state;\n\tu8 reserved_3[4];\n\tu64 exit_code;\n\tu64 exit_info_1;\n\tu64 exit_info_2;\n\tu32 exit_int_info;\n\tu32 exit_int_info_err;\n\tu64 nested_ctl;\n\tu64 avic_vapic_bar;\n\tu64 ghcb_gpa;\n\tu32 event_inj;\n\tu32 event_inj_err;\n\tu64 nested_cr3;\n\tu64 virt_ext;\n\tu32 clean;\n\tu32 reserved_5;\n\tu64 next_rip;\n\tu8 insn_len;\n\tu8 insn_bytes[15];\n\tu64 avic_backing_page;\n\tu8 reserved_6[8];\n\tu64 avic_logical_id;\n\tu64 avic_physical_id;\n\tu8 reserved_7[8];\n\tu64 vmsa_pa;\n\tu8 reserved_8[16];\n\tu16 bus_lock_counter;\n\tu8 reserved_9[22];\n\tu64 allowed_sev_features;\n\tu64 guest_sev_features;\n\tu8 reserved_10[664];\n\tunion {\n\t\tstruct hv_vmcb_enlightenments hv_enlightenments;\n\t\tu8 reserved_sw[32];\n\t};\n};\n\nstruct vmcb_save_area {\n\tstruct vmcb_seg es;\n\tstruct vmcb_seg cs;\n\tstruct vmcb_seg ss;\n\tstruct vmcb_seg ds;\n\tstruct vmcb_seg fs;\n\tstruct vmcb_seg gs;\n\tstruct vmcb_seg gdtr;\n\tstruct vmcb_seg ldtr;\n\tstruct vmcb_seg idtr;\n\tstruct vmcb_seg tr;\n\tu8 reserved_0xa0[42];\n\tu8 vmpl;\n\tu8 cpl;\n\tu8 reserved_0xcc[4];\n\tu64 efer;\n\tu8 reserved_0xd8[112];\n\tu64 cr4;\n\tu64 cr3;\n\tu64 cr0;\n\tu64 dr7;\n\tu64 dr6;\n\tu64 rflags;\n\tu64 rip;\n\tu8 reserved_0x180[88];\n\tu64 rsp;\n\tu64 s_cet;\n\tu64 ssp;\n\tu64 isst_addr;\n\tu64 rax;\n\tu64 star;\n\tu64 lstar;\n\tu64 cstar;\n\tu64 sfmask;\n\tu64 kernel_gs_base;\n\tu64 sysenter_cs;\n\tu64 sysenter_esp;\n\tu64 sysenter_eip;\n\tu64 cr2;\n\tu8 reserved_0x248[32];\n\tu64 g_pat;\n\tu64 dbgctl;\n\tu64 br_from;\n\tu64 br_to;\n\tu64 last_excp_from;\n\tu64 last_excp_to;\n\tu8 reserved_0x298[72];\n\tu64 spec_ctrl;\n};\n\nstruct vmcb {\n\tstruct vmcb_control_area control;\n\tunion {\n\t\tstruct vmcb_save_area save;\n\t\tstruct sev_es_save_area host_sev_es_save;\n\t};\n};\n\nstruct vmclock_abi {\n\t__le32 magic;\n\t__le32 size;\n\t__le16 version;\n\t__u8 counter_id;\n\t__u8 time_type;\n\t__le32 seq_count;\n\t__le64 disruption_marker;\n\t__le64 flags;\n\t__u8 pad[2];\n\t__u8 clock_status;\n\t__u8 leap_second_smearing_hint;\n\t__le16 tai_offset_sec;\n\t__u8 leap_indicator;\n\t__u8 counter_period_shift;\n\t__le64 counter_value;\n\t__le64 counter_period_frac_sec;\n\t__le64 counter_period_esterror_rate_frac_sec;\n\t__le64 counter_period_maxerror_rate_frac_sec;\n\t__le64 time_sec;\n\t__le64 time_frac_sec;\n\t__le64 time_esterror_nanosec;\n\t__le64 time_maxerror_nanosec;\n\t__le64 vm_generation_counter;\n};\n\nstruct vmclock_state;\n\nstruct vmclock_file_state {\n\tstruct vmclock_state *st;\n\tatomic_t seq;\n};\n\nstruct vmclock_state {\n\tstruct resource res;\n\tstruct vmclock_abi *clk;\n\tstruct miscdevice miscdev;\n\twait_queue_head_t disrupt_wait;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct ptp_clock *ptp_clock;\n\tenum clocksource_ids cs_id;\n\tenum clocksource_ids sys_cs_id;\n\tint index;\n\tchar *name;\n};\n\nstruct vmcore_cb {\n\tbool (*pfn_is_ram)(struct vmcore_cb *, long unsigned int);\n\tint (*get_device_ram)(struct vmcore_cb *, struct list_head *);\n\tstruct list_head next;\n};\n\nstruct vmcore_range {\n\tstruct list_head list;\n\tlong long unsigned int paddr;\n\tlong long unsigned int size;\n\tloff_t offset;\n};\n\nstruct vmcs_hdr {\n\tu32 revision_id: 31;\n\tu32 shadow_vmcs: 1;\n};\n\nstruct vmcs {\n\tstruct vmcs_hdr hdr;\n\tu32 abort;\n\tchar data[0];\n};\n\nstruct vmcs12 {\n\tstruct vmcs_hdr hdr;\n\tu32 abort;\n\tu32 launch_state;\n\tu32 padding[7];\n\tu64 io_bitmap_a;\n\tu64 io_bitmap_b;\n\tu64 msr_bitmap;\n\tu64 vm_exit_msr_store_addr;\n\tu64 vm_exit_msr_load_addr;\n\tu64 vm_entry_msr_load_addr;\n\tu64 tsc_offset;\n\tu64 virtual_apic_page_addr;\n\tu64 apic_access_addr;\n\tu64 posted_intr_desc_addr;\n\tu64 ept_pointer;\n\tu64 eoi_exit_bitmap0;\n\tu64 eoi_exit_bitmap1;\n\tu64 eoi_exit_bitmap2;\n\tu64 eoi_exit_bitmap3;\n\tu64 xss_exit_bitmap;\n\tu64 guest_physical_address;\n\tu64 vmcs_link_pointer;\n\tu64 guest_ia32_debugctl;\n\tu64 guest_ia32_pat;\n\tu64 guest_ia32_efer;\n\tu64 guest_ia32_perf_global_ctrl;\n\tu64 guest_pdptr0;\n\tu64 guest_pdptr1;\n\tu64 guest_pdptr2;\n\tu64 guest_pdptr3;\n\tu64 guest_bndcfgs;\n\tu64 host_ia32_pat;\n\tu64 host_ia32_efer;\n\tu64 host_ia32_perf_global_ctrl;\n\tu64 vmread_bitmap;\n\tu64 vmwrite_bitmap;\n\tu64 vm_function_control;\n\tu64 eptp_list_address;\n\tu64 pml_address;\n\tu64 encls_exiting_bitmap;\n\tu64 tsc_multiplier;\n\tu64 padding64[1];\n\tnatural_width cr0_guest_host_mask;\n\tnatural_width cr4_guest_host_mask;\n\tnatural_width cr0_read_shadow;\n\tnatural_width cr4_read_shadow;\n\tnatural_width dead_space[4];\n\tnatural_width exit_qualification;\n\tnatural_width guest_linear_address;\n\tnatural_width guest_cr0;\n\tnatural_width guest_cr3;\n\tnatural_width guest_cr4;\n\tnatural_width guest_es_base;\n\tnatural_width guest_cs_base;\n\tnatural_width guest_ss_base;\n\tnatural_width guest_ds_base;\n\tnatural_width guest_fs_base;\n\tnatural_width guest_gs_base;\n\tnatural_width guest_ldtr_base;\n\tnatural_width guest_tr_base;\n\tnatural_width guest_gdtr_base;\n\tnatural_width guest_idtr_base;\n\tnatural_width guest_dr7;\n\tnatural_width guest_rsp;\n\tnatural_width guest_rip;\n\tnatural_width guest_rflags;\n\tnatural_width guest_pending_dbg_exceptions;\n\tnatural_width guest_sysenter_esp;\n\tnatural_width guest_sysenter_eip;\n\tnatural_width host_cr0;\n\tnatural_width host_cr3;\n\tnatural_width host_cr4;\n\tnatural_width host_fs_base;\n\tnatural_width host_gs_base;\n\tnatural_width host_tr_base;\n\tnatural_width host_gdtr_base;\n\tnatural_width host_idtr_base;\n\tnatural_width host_ia32_sysenter_esp;\n\tnatural_width host_ia32_sysenter_eip;\n\tnatural_width host_rsp;\n\tnatural_width host_rip;\n\tnatural_width host_s_cet;\n\tnatural_width host_ssp;\n\tnatural_width host_ssp_tbl;\n\tnatural_width guest_s_cet;\n\tnatural_width guest_ssp;\n\tnatural_width guest_ssp_tbl;\n\tnatural_width paddingl[2];\n\tu32 pin_based_vm_exec_control;\n\tu32 cpu_based_vm_exec_control;\n\tu32 exception_bitmap;\n\tu32 page_fault_error_code_mask;\n\tu32 page_fault_error_code_match;\n\tu32 cr3_target_count;\n\tu32 vm_exit_controls;\n\tu32 vm_exit_msr_store_count;\n\tu32 vm_exit_msr_load_count;\n\tu32 vm_entry_controls;\n\tu32 vm_entry_msr_load_count;\n\tu32 vm_entry_intr_info_field;\n\tu32 vm_entry_exception_error_code;\n\tu32 vm_entry_instruction_len;\n\tu32 tpr_threshold;\n\tu32 secondary_vm_exec_control;\n\tu32 vm_instruction_error;\n\tu32 vm_exit_reason;\n\tu32 vm_exit_intr_info;\n\tu32 vm_exit_intr_error_code;\n\tu32 idt_vectoring_info_field;\n\tu32 idt_vectoring_error_code;\n\tu32 vm_exit_instruction_len;\n\tu32 vmx_instruction_info;\n\tu32 guest_es_limit;\n\tu32 guest_cs_limit;\n\tu32 guest_ss_limit;\n\tu32 guest_ds_limit;\n\tu32 guest_fs_limit;\n\tu32 guest_gs_limit;\n\tu32 guest_ldtr_limit;\n\tu32 guest_tr_limit;\n\tu32 guest_gdtr_limit;\n\tu32 guest_idtr_limit;\n\tu32 guest_es_ar_bytes;\n\tu32 guest_cs_ar_bytes;\n\tu32 guest_ss_ar_bytes;\n\tu32 guest_ds_ar_bytes;\n\tu32 guest_fs_ar_bytes;\n\tu32 guest_gs_ar_bytes;\n\tu32 guest_ldtr_ar_bytes;\n\tu32 guest_tr_ar_bytes;\n\tu32 guest_interruptibility_info;\n\tu32 guest_activity_state;\n\tu32 guest_sysenter_cs;\n\tu32 host_ia32_sysenter_cs;\n\tu32 vmx_preemption_timer_value;\n\tu32 padding32[7];\n\tu16 virtual_processor_id;\n\tu16 posted_intr_nv;\n\tu16 guest_es_selector;\n\tu16 guest_cs_selector;\n\tu16 guest_ss_selector;\n\tu16 guest_ds_selector;\n\tu16 guest_fs_selector;\n\tu16 guest_gs_selector;\n\tu16 guest_ldtr_selector;\n\tu16 guest_tr_selector;\n\tu16 guest_intr_status;\n\tu16 host_es_selector;\n\tu16 host_cs_selector;\n\tu16 host_ss_selector;\n\tu16 host_ds_selector;\n\tu16 host_fs_selector;\n\tu16 host_gs_selector;\n\tu16 host_tr_selector;\n\tu16 guest_pml_index;\n} __attribute__((packed));\n\nstruct vmcs_config {\n\tu64 basic;\n\tu32 pin_based_exec_ctrl;\n\tu32 cpu_based_exec_ctrl;\n\tu32 cpu_based_2nd_exec_ctrl;\n\tu64 cpu_based_3rd_exec_ctrl;\n\tu32 vmexit_ctrl;\n\tu32 vmentry_ctrl;\n\tu64 misc;\n\tstruct nested_vmx_msrs nested;\n};\n\nstruct vmemmap_remap_walk {\n\tvoid (*remap_pte)(pte_t *, long unsigned int, struct vmemmap_remap_walk *);\n\tlong unsigned int nr_walked;\n\tstruct page *reuse_page;\n\tlong unsigned int reuse_addr;\n\tstruct list_head *vmemmap_pages;\n\tlong unsigned int flags;\n};\n\nstruct vmware_steal_time {\n\tunion {\n\t\tu64 clock;\n\t\tstruct {\n\t\t\tu32 clock_low;\n\t\t\tu32 clock_high;\n\t\t};\n\t};\n\tu64 reserved[7];\n};\n\nstruct vmx_capability {\n\tu32 ept;\n\tu32 vpid;\n};\n\nstruct vmx_ve_information {\n\tu32 exit_reason;\n\tu32 delivery;\n\tu64 exit_qualification;\n\tu64 guest_linear_address;\n\tu64 guest_physical_address;\n\tu16 eptp_index;\n};\n\nstruct vring_desc;\n\ntypedef struct vring_desc vring_desc_t;\n\nstruct vring_avail;\n\ntypedef struct vring_avail vring_avail_t;\n\nstruct vring_used;\n\ntypedef struct vring_used vring_used_t;\n\nstruct vring {\n\tunsigned int num;\n\tvring_desc_t *desc;\n\tvring_avail_t *avail;\n\tvring_used_t *used;\n};\n\nstruct vring_avail {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\t__virtio16 ring[0];\n};\n\nstruct vring_desc {\n\t__virtio64 addr;\n\t__virtio32 len;\n\t__virtio16 flags;\n\t__virtio16 next;\n};\n\nstruct vring_desc_extra {\n\tdma_addr_t addr;\n\tu32 len;\n\tu16 flags;\n\tu16 next;\n};\n\nstruct vring_packed_desc;\n\nstruct vring_desc_state_packed {\n\tvoid *data;\n\tstruct vring_packed_desc *indir_desc;\n\tu16 num;\n\tu16 last;\n\tu32 total_in_len;\n};\n\nstruct vring_desc_state_split {\n\tvoid *data;\n\tstruct vring_desc *indir_desc;\n\tu32 total_in_len;\n};\n\nstruct vring_packed_desc {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 id;\n\t__le16 flags;\n};\n\nstruct vring_packed_desc_event {\n\t__le16 off_wrap;\n\t__le16 flags;\n};\n\nstruct vring_used_elem {\n\t__virtio32 id;\n\t__virtio32 len;\n};\n\ntypedef struct vring_used_elem vring_used_elem_t;\n\nstruct vring_used {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\tvring_used_elem_t ring[0];\n};\n\nstruct vring_virtqueue_split {\n\tstruct vring vring;\n\tu16 avail_flags_shadow;\n\tu16 avail_idx_shadow;\n\tstruct vring_desc_state_split *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t queue_dma_addr;\n\tsize_t queue_size_in_bytes;\n\tu32 vring_align;\n\tbool may_reduce_num;\n};\n\nstruct vring_virtqueue_packed {\n\tstruct {\n\t\tunsigned int num;\n\t\tstruct vring_packed_desc *desc;\n\t\tstruct vring_packed_desc_event *driver;\n\t\tstruct vring_packed_desc_event *device;\n\t} vring;\n\tbool avail_wrap_counter;\n\tu16 avail_used_flags;\n\tu16 next_avail_idx;\n\tu16 event_flags_shadow;\n\tstruct vring_desc_state_packed *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t ring_dma_addr;\n\tdma_addr_t driver_event_dma_addr;\n\tdma_addr_t device_event_dma_addr;\n\tsize_t ring_size_in_bytes;\n\tsize_t event_size_in_bytes;\n};\n\nstruct vring_virtqueue {\n\tstruct virtqueue vq;\n\tbool use_map_api;\n\tbool weak_barriers;\n\tbool broken;\n\tbool indirect;\n\tbool event;\n\tenum vq_layout layout;\n\tunsigned int free_head;\n\tstruct used_entry batch_last;\n\tunsigned int num_added;\n\tu16 last_used_idx;\n\tu16 last_used;\n\tbool event_triggered;\n\tunion {\n\t\tstruct vring_virtqueue_split split;\n\t\tstruct vring_virtqueue_packed packed;\n\t};\n\tbool (*notify)(struct virtqueue *);\n\tbool we_own_ring;\n\tunion virtio_map map;\n};\n\nstruct vsock_diag_msg {\n\t__u8 vdiag_family;\n\t__u8 vdiag_type;\n\t__u8 vdiag_state;\n\t__u8 vdiag_shutdown;\n\t__u32 vdiag_src_cid;\n\t__u32 vdiag_src_port;\n\t__u32 vdiag_dst_cid;\n\t__u32 vdiag_dst_port;\n\t__u32 vdiag_ino;\n\t__u32 vdiag_cookie[2];\n};\n\nstruct vsock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u16 pad;\n\t__u32 vdiag_states;\n\t__u32 vdiag_ino;\n\t__u32 vdiag_show;\n\t__u32 vdiag_cookie[2];\n};\n\nstruct vsock_loopback {\n\tstruct workqueue_struct *workqueue;\n\tstruct sk_buff_head pkt_queue;\n\tstruct work_struct pkt_work;\n};\n\nstruct vsock_sock {\n\tstruct sock sk;\n\tconst struct vsock_transport *transport;\n\tstruct sockaddr_vm local_addr;\n\tstruct sockaddr_vm remote_addr;\n\tstruct list_head bound_table;\n\tstruct list_head connected_table;\n\tbool trusted;\n\tbool cached_peer_allow_dgram;\n\tu32 cached_peer;\n\tconst struct cred *owner;\n\tlong int connect_timeout;\n\tstruct sock *listener;\n\tstruct list_head pending_links;\n\tstruct list_head accept_queue;\n\tbool rejected;\n\tstruct delayed_work connect_work;\n\tstruct delayed_work pending_work;\n\tstruct delayed_work close_work;\n\tbool close_work_scheduled;\n\tu32 peer_shutdown;\n\tbool sent_request;\n\tbool ignore_connecting_rst;\n\tu64 buffer_size;\n\tu64 buffer_min_size;\n\tu64 buffer_max_size;\n\tvoid *trans;\n};\n\nstruct vsock_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct vsock_transport_recv_notify_data {\n\tu64 data1;\n\tu64 data2;\n\tbool notify_on_block;\n};\n\nstruct vsock_transport_send_notify_data {\n\tu64 data1;\n\tu64 data2;\n};\n\nstruct vt1618_uaj_item {\n\tshort unsigned int mask;\n\tshort unsigned int shift;\n\tconst char * const items[4];\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_barrier {\n\tstruct wait_queue_entry base;\n\tstruct i915_active *ref;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_exceptional_entry_queue {\n\twait_queue_entry_t wait;\n\tstruct exceptional_entry_key key;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wait_rps_boost {\n\tstruct wait_queue_entry wait;\n\tstruct drm_crtc *crtc;\n\tstruct dma_fence *fence;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nstruct wakeup_header {\n\tu16 video_mode;\n\tu32 pmode_entry;\n\tu16 pmode_cs;\n\tu32 pmode_cr0;\n\tu32 pmode_cr3;\n\tu32 pmode_cr4;\n\tu32 pmode_efer_low;\n\tu32 pmode_efer_high;\n\tu64 pmode_gdt;\n\tu32 pmode_misc_en_low;\n\tu32 pmode_misc_en_high;\n\tu32 pmode_behavior;\n\tu32 realmode_flags;\n\tu32 real_magic;\n\tu32 signature;\n} __attribute__((packed));\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n};\n\nstruct walk_rcec_data {\n\tstruct pci_dev *rcec;\n\tint (*user_callback)(struct pci_dev *, void *);\n\tvoid *user_data;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct watchdog_core_data {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct watchdog_device *wdd;\n\tstruct mutex lock;\n\tktime_t last_keepalive;\n\tktime_t last_hw_keepalive;\n\tktime_t open_deadline;\n\tstruct hrtimer timer;\n\tstruct kthread_work work;\n\tlong unsigned int status;\n};\n\nstruct watchdog_governor {\n\tconst char name[20];\n\tvoid (*pretimeout)(struct watchdog_device *);\n};\n\nstruct watchdog_info {\n\t__u32 options;\n\t__u32 firmware_version;\n\t__u8 identity[32];\n};\n\nstruct watchdog_ops {\n\tstruct module *owner;\n\tint (*start)(struct watchdog_device *);\n\tint (*stop)(struct watchdog_device *);\n\tint (*ping)(struct watchdog_device *);\n\tunsigned int (*status)(struct watchdog_device *);\n\tint (*set_timeout)(struct watchdog_device *, unsigned int);\n\tint (*set_pretimeout)(struct watchdog_device *, unsigned int);\n\tunsigned int (*get_timeleft)(struct watchdog_device *);\n\tint (*restart)(struct watchdog_device *, long unsigned int, void *);\n\tlong int (*ioctl)(struct watchdog_device *, unsigned int, long unsigned int);\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct weighted_interleave_state {\n\tbool mode_auto;\n\tu8 iw_table[0];\n};\n\nstruct widget_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct hdac_device *, hda_nid_t, struct widget_attribute *, char *);\n\tssize_t (*store)(struct hdac_device *, hda_nid_t, struct widget_attribute *, const char *, size_t);\n};\n\nstruct wired_cmd_ake_send_hprime_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 h_prime[32];\n};\n\nstruct wired_cmd_ake_send_hprime_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_ake_send_pairing_info_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 e_kh_km[16];\n};\n\nstruct wired_cmd_ake_send_pairing_info_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_close_session_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_close_session_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_enable_auth_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 stream_type;\n} __attribute__((packed));\n\nstruct wired_cmd_enable_auth_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_get_session_key_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_get_session_key_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 e_dkey_ks[16];\n\tu8 r_iv[8];\n};\n\nstruct wired_cmd_init_locality_check_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_init_locality_check_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 r_n[8];\n};\n\nstruct wired_cmd_initiate_hdcp2_session_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 protocol;\n} __attribute__((packed));\n\nstruct wired_cmd_initiate_hdcp2_session_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 r_tx[8];\n\tstruct hdcp2_tx_caps tx_caps;\n} __attribute__((packed));\n\nstruct wired_cmd_repeater_auth_stream_req_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 seq_num_m[3];\n\tu8 m_prime[32];\n\t__be16 k;\n\tstruct hdcp2_streamid_type streams[0];\n} __attribute__((packed));\n\nstruct wired_cmd_repeater_auth_stream_req_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_validate_locality_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 l_prime[32];\n};\n\nstruct wired_cmd_validate_locality_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_verify_receiver_cert_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tstruct hdcp2_cert_rx cert_rx;\n\tu8 r_rx[8];\n\tu8 rx_caps[3];\n} __attribute__((packed));\n\nstruct wired_cmd_verify_receiver_cert_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 km_stored;\n\tu8 reserved[3];\n\tunion encrypted_buff ekm_buff;\n};\n\nstruct wired_cmd_verify_repeater_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 rx_info[2];\n\tu8 seq_num_v[3];\n\tu8 v_prime[16];\n\tu8 receiver_ids[155];\n};\n\nstruct wired_cmd_verify_repeater_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 content_type_supported;\n\tu8 v[16];\n} __attribute__((packed));\n\nstruct wmi_device {\n\tstruct device dev;\n\tbool setable;\n\tconst char *driver_override;\n};\n\ntypedef void (*wmi_notify_handler)(union acpi_object *, void *);\n\nstruct wmi_block {\n\tstruct wmi_device dev;\n\tstruct guid_block gblock;\n\tstruct acpi_device *acpi_device;\n\tstruct rw_semaphore notify_lock;\n\twmi_notify_handler handler;\n\tvoid *handler_data;\n\tbool driver_ready;\n\tlong unsigned int flags;\n};\n\nstruct wmi_brightness_args {\n\tu32 mode;\n\tu32 val;\n\tu32 ret;\n\tu32 ignored[3];\n};\n\nstruct wmi_buffer {\n\tsize_t length;\n\tvoid *data;\n};\n\nstruct wmi_device_id {\n\tconst char guid_string[37];\n\tconst void *context;\n};\n\nstruct wmi_driver {\n\tstruct device_driver driver;\n\tconst struct wmi_device_id *id_table;\n\tbool no_notify_data;\n\tbool no_singleton;\n\tint (*probe)(struct wmi_device *, const void *);\n\tvoid (*remove)(struct wmi_device *);\n\tvoid (*shutdown)(struct wmi_device *);\n\tvoid (*notify)(struct wmi_device *, union acpi_object *);\n\tvoid (*notify_new)(struct wmi_device *, const struct wmi_buffer *);\n};\n\nstruct wmi_guid_count_context {\n\tconst guid_t *guid;\n\tint count;\n};\n\nstruct wmi_string {\n\t__le16 length;\n\t__le16 chars[0];\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int one_bits;\n\tconst long unsigned int high_bits;\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct work_queue_wrapper {\n\tstruct work_struct work;\n\tstruct scsi_device *sdev;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar *lock_name;\n\tstruct lock_class_key key;\n\tstruct lockdep_map __lockdep_map;\n\tstruct lockdep_map *lockdep_map;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct workspace {\n\tvoid *mem;\n\tsize_t mem_size;\n\tsize_t window_size;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct write_opcode_ctx {\n\tlong unsigned int base;\n\tint expect;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct x509_certificate {\n\tstruct x509_certificate *next;\n\tstruct x509_certificate *signer;\n\tstruct public_key *pub;\n\tstruct public_key_signature *sig;\n\tu8 sha256[32];\n\tchar *issuer;\n\tchar *subject;\n\tstruct asymmetric_key_id *id;\n\tstruct asymmetric_key_id *skid;\n\ttime64_t valid_from;\n\ttime64_t valid_to;\n\tconst void *tbs;\n\tunsigned int tbs_size;\n\tunsigned int raw_sig_size;\n\tconst void *raw_sig;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_subject;\n\tunsigned int raw_subject_size;\n\tunsigned int raw_skid_size;\n\tconst void *raw_skid;\n\tunsigned int index;\n\tbool seen;\n\tbool verified;\n\tbool self_signed;\n\tbool unsupported_sig;\n\tbool blacklisted;\n};\n\nstruct x509_parse_context {\n\tstruct x509_certificate *cert;\n\tlong unsigned int data;\n\tconst void *key;\n\tsize_t key_size;\n\tconst void *params;\n\tsize_t params_size;\n\tenum OID key_algo;\n\tenum OID last_oid;\n\tenum OID sig_algo;\n\tu8 o_size;\n\tu8 cn_size;\n\tu8 email_size;\n\tu16 o_offset;\n\tu16 cn_offset;\n\tu16 email_offset;\n\tunsigned int raw_akid_size;\n\tconst void *raw_akid;\n\tconst void *akid_raw_issuer;\n\tunsigned int akid_raw_issuer_size;\n};\n\nstruct x64_jit_data {\n\tstruct bpf_binary_header *rw_header;\n\tstruct bpf_binary_header *header;\n\tint *addrs;\n\tu8 *image;\n\tint proglen;\n\tstruct jit_context ctx;\n};\n\nstruct x86_apic_ops {\n\tunsigned int (*io_apic_read)(unsigned int, unsigned int);\n\tvoid (*restore)(void);\n};\n\nstruct x86_cpuinit_ops {\n\tvoid (*setup_percpu_clockev)(void);\n\tvoid (*early_percpu_clock_init)(void);\n\tvoid (*fixup_cpu_id)(struct cpuinfo_x86 *, int);\n\tbool parallel_bringup;\n};\n\nstruct fastop;\n\ntypedef void (*fastop_t)(struct fastop *);\n\nstruct x86_emulate_ops;\n\nstruct x86_emulate_ctxt {\n\tvoid *vcpu;\n\tconst struct x86_emulate_ops *ops;\n\tlong unsigned int eflags;\n\tlong unsigned int eip;\n\tenum x86emul_mode mode;\n\tint interruptibility;\n\tbool perm_ok;\n\tbool tf;\n\tbool have_exception;\n\tstruct x86_exception exception;\n\tbool gpa_available;\n\tgpa_t gpa_val;\n\tu8 opcode_len;\n\tu8 b;\n\tu8 intercept;\n\tbool op_prefix;\n\tu8 op_bytes;\n\tu8 ad_bytes;\n\tunion {\n\t\tint (*execute)(struct x86_emulate_ctxt *);\n\t\tfastop_t fop;\n\t};\n\tint (*check_perm)(struct x86_emulate_ctxt *);\n\tbool rip_relative;\n\tenum rex_type rex_prefix;\n\tu8 rex_bits;\n\tu8 lock_prefix;\n\tu8 rep_prefix;\n\tu16 regs_valid;\n\tu16 regs_dirty;\n\tu8 modrm;\n\tu8 modrm_mod;\n\tu8 modrm_reg;\n\tu8 modrm_rm;\n\tu8 modrm_seg;\n\tu8 seg_override;\n\tu64 d;\n\tlong unsigned int _eip;\n\tstruct operand src;\n\tstruct operand src2;\n\tstruct operand dst;\n\tstruct operand memop;\n\tlong unsigned int _regs[16];\n\tstruct operand *memopp;\n\tstruct fetch_cache fetch;\n\tstruct read_cache io_read;\n\tstruct read_cache mem_read;\n\tbool is_branch;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct x86_emulate_ops {\n\tvoid (*vm_bugged)(struct x86_emulate_ctxt *);\n\tulong (*read_gpr)(struct x86_emulate_ctxt *, unsigned int);\n\tvoid (*write_gpr)(struct x86_emulate_ctxt *, unsigned int, ulong);\n\tint (*read_std)(struct x86_emulate_ctxt *, long unsigned int, void *, unsigned int, struct x86_exception *, bool);\n\tint (*write_std)(struct x86_emulate_ctxt *, long unsigned int, void *, unsigned int, struct x86_exception *, bool);\n\tint (*fetch)(struct x86_emulate_ctxt *, long unsigned int, void *, unsigned int, struct x86_exception *);\n\tint (*read_emulated)(struct x86_emulate_ctxt *, long unsigned int, void *, unsigned int, struct x86_exception *);\n\tint (*write_emulated)(struct x86_emulate_ctxt *, long unsigned int, const void *, unsigned int, struct x86_exception *);\n\tint (*cmpxchg_emulated)(struct x86_emulate_ctxt *, long unsigned int, const void *, const void *, unsigned int, struct x86_exception *);\n\tvoid (*invlpg)(struct x86_emulate_ctxt *, ulong);\n\tint (*pio_in_emulated)(struct x86_emulate_ctxt *, int, short unsigned int, void *, unsigned int);\n\tint (*pio_out_emulated)(struct x86_emulate_ctxt *, int, short unsigned int, const void *, unsigned int);\n\tbool (*get_segment)(struct x86_emulate_ctxt *, u16 *, struct desc_struct *, u32 *, int);\n\tvoid (*set_segment)(struct x86_emulate_ctxt *, u16, struct desc_struct *, u32, int);\n\tlong unsigned int (*get_cached_segment_base)(struct x86_emulate_ctxt *, int);\n\tvoid (*get_gdt)(struct x86_emulate_ctxt *, struct desc_ptr *);\n\tvoid (*get_idt)(struct x86_emulate_ctxt *, struct desc_ptr *);\n\tvoid (*set_gdt)(struct x86_emulate_ctxt *, struct desc_ptr *);\n\tvoid (*set_idt)(struct x86_emulate_ctxt *, struct desc_ptr *);\n\tulong (*get_cr)(struct x86_emulate_ctxt *, int);\n\tint (*set_cr)(struct x86_emulate_ctxt *, int, ulong);\n\tint (*cpl)(struct x86_emulate_ctxt *);\n\tulong (*get_dr)(struct x86_emulate_ctxt *, int);\n\tint (*set_dr)(struct x86_emulate_ctxt *, int, ulong);\n\tint (*set_msr_with_filter)(struct x86_emulate_ctxt *, u32, u64);\n\tint (*get_msr_with_filter)(struct x86_emulate_ctxt *, u32, u64 *);\n\tint (*get_msr)(struct x86_emulate_ctxt *, u32, u64 *);\n\tint (*check_rdpmc_early)(struct x86_emulate_ctxt *, u32);\n\tint (*read_pmc)(struct x86_emulate_ctxt *, u32, u64 *);\n\tvoid (*halt)(struct x86_emulate_ctxt *);\n\tvoid (*wbinvd)(struct x86_emulate_ctxt *);\n\tint (*fix_hypercall)(struct x86_emulate_ctxt *);\n\tint (*intercept)(struct x86_emulate_ctxt *, struct x86_instruction_info *, enum x86_intercept_stage);\n\tbool (*get_cpuid)(struct x86_emulate_ctxt *, u32 *, u32 *, u32 *, u32 *, bool);\n\tbool (*guest_has_movbe)(struct x86_emulate_ctxt *);\n\tbool (*guest_has_fxsr)(struct x86_emulate_ctxt *);\n\tbool (*guest_has_rdpid)(struct x86_emulate_ctxt *);\n\tbool (*guest_cpuid_is_intel_compatible)(struct x86_emulate_ctxt *);\n\tvoid (*set_nmi_mask)(struct x86_emulate_ctxt *, bool);\n\tbool (*is_smm)(struct x86_emulate_ctxt *);\n\tint (*leave_smm)(struct x86_emulate_ctxt *);\n\tvoid (*triple_fault)(struct x86_emulate_ctxt *);\n\tint (*get_xcr)(struct x86_emulate_ctxt *, u32, u64 *);\n\tint (*set_xcr)(struct x86_emulate_ctxt *, u32, u64);\n\tgva_t (*get_untagged_addr)(struct x86_emulate_ctxt *, gva_t, unsigned int);\n\tbool (*is_canonical_addr)(struct x86_emulate_ctxt *, gva_t, unsigned int);\n};\n\nstruct x86_guest {\n\tint (*enc_status_change_prepare)(long unsigned int, int, bool);\n\tint (*enc_status_change_finish)(long unsigned int, int, bool);\n\tbool (*enc_tlb_flush_required)(bool);\n\tbool (*enc_cache_flush_required)(void);\n\tvoid (*enc_kexec_begin)(void);\n\tvoid (*enc_kexec_finish)(void);\n};\n\nstruct x86_hybrid_pmu {\n\tstruct pmu pmu;\n\tconst char *name;\n\tenum hybrid_pmu_type pmu_type;\n\tcpumask_t supported_cpus;\n\tunion perf_capabilities intel_cap;\n\tu64 intel_ctrl;\n\tu64 pebs_events_mask;\n\tu64 config_mask;\n\tunion {\n\t\tu64 cntr_mask64;\n\t\tlong unsigned int cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 fixed_cntr_mask64;\n\t\tlong unsigned int fixed_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cntr_mask64;\n\t\tlong unsigned int acr_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cause_mask64;\n\t\tlong unsigned int acr_cause_mask[1];\n\t};\n\tstruct event_constraint unconstrained;\n\tu64 hw_cache_event_ids[42];\n\tu64 hw_cache_extra_regs[42];\n\tstruct event_constraint *event_constraints;\n\tstruct event_constraint *pebs_constraints;\n\tstruct extra_reg *extra_regs;\n\tunsigned int late_ack: 1;\n\tunsigned int mid_ack: 1;\n\tunsigned int enabled_ack: 1;\n\tstruct arch_pebs_cap arch_pebs_cap;\n\tu64 pebs_data_source[256];\n};\n\nstruct x86_init_acpi {\n\tvoid (*set_root_pointer)(u64);\n\tu64 (*get_root_pointer)(void);\n\tvoid (*reduced_hw_early_init)(void);\n};\n\nstruct x86_init_iommu {\n\tint (*iommu_init)(void);\n};\n\nstruct x86_init_irqs {\n\tvoid (*pre_vector_init)(void);\n\tvoid (*intr_init)(void);\n\tvoid (*intr_mode_select)(void);\n\tvoid (*intr_mode_init)(void);\n\tstruct irq_domain * (*create_pci_msi_domain)(void);\n};\n\nstruct x86_init_mpparse {\n\tvoid (*setup_ioapic_ids)(void);\n\tvoid (*find_mptable)(void);\n\tvoid (*early_parse_smp_cfg)(void);\n\tvoid (*parse_smp_cfg)(void);\n};\n\nstruct x86_init_oem {\n\tvoid (*arch_setup)(void);\n\tvoid (*banner)(void);\n};\n\nstruct x86_init_resources {\n\tvoid (*probe_roms)(void);\n\tvoid (*reserve_resources)(void);\n\tchar * (*memory_setup)(void);\n\tvoid (*dmi_setup)(void);\n};\n\nstruct x86_init_paging {\n\tvoid (*pagetable_init)(void);\n};\n\nstruct x86_init_timers {\n\tvoid (*setup_percpu_clockev)(void);\n\tvoid (*timer_init)(void);\n\tvoid (*wallclock_init)(void);\n};\n\nstruct x86_init_pci {\n\tint (*arch_init)(void);\n\tint (*init)(void);\n\tvoid (*init_irq)(void);\n\tvoid (*fixup_irqs)(void);\n};\n\nstruct x86_init_ops {\n\tstruct x86_init_resources resources;\n\tstruct x86_init_mpparse mpparse;\n\tstruct x86_init_irqs irqs;\n\tstruct x86_init_oem oem;\n\tstruct x86_init_paging paging;\n\tstruct x86_init_timers timers;\n\tstruct x86_init_iommu iommu;\n\tstruct x86_init_pci pci;\n\tstruct x86_hyper_init hyper;\n\tstruct x86_init_acpi acpi;\n};\n\nstruct x86_instruction_info {\n\tu8 intercept;\n\tu8 rep_prefix;\n\tu8 modrm_mod;\n\tu8 modrm_reg;\n\tu8 modrm_rm;\n\tu64 src_val;\n\tu64 dst_val;\n\tu8 src_bytes;\n\tu8 dst_bytes;\n\tu8 src_type;\n\tu8 dst_type;\n\tu8 ad_bytes;\n\tu64 rip;\n\tu64 next_rip;\n};\n\nstruct x86_legacy_devices {\n\tint pnpbios;\n};\n\nstruct x86_legacy_features {\n\tenum x86_legacy_i8042_state i8042;\n\tint rtc;\n\tint warm_reset;\n\tint no_vga;\n\tint reserve_bios_regions;\n\tstruct x86_legacy_devices devices;\n};\n\nstruct x86_mapping_info {\n\tvoid * (*alloc_pgt_page)(void *);\n\tvoid (*free_pgt_page)(void *, void *);\n\tvoid *context;\n\tlong unsigned int page_flag;\n\tlong unsigned int offset;\n\tbool direct_gbpages;\n\tlong unsigned int kernpg_flag;\n};\n\nstruct x86_perf_regs {\n\tstruct pt_regs regs;\n\tu64 *xmm_regs;\n};\n\nstruct x86_perf_task_context_opt {\n\tint lbr_callstack_users;\n\tint lbr_stack_state;\n\tint log_id;\n};\n\nstruct x86_perf_task_context {\n\tu64 lbr_sel;\n\tint tos;\n\tint valid_lbrs;\n\tstruct x86_perf_task_context_opt opt;\n\tstruct lbr_entry lbr[32];\n};\n\nstruct x86_perf_task_context_arch_lbr {\n\tstruct x86_perf_task_context_opt opt;\n\tstruct lbr_entry entries[0];\n};\n\nstruct x86_perf_task_context_arch_lbr_xsave {\n\tstruct x86_perf_task_context_opt opt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct xregs_state xsave;\n\t\tstruct {\n\t\t\tstruct fxregs_state i387;\n\t\t\tstruct xstate_header header;\n\t\t\tstruct arch_lbr_state lbr;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t};\n};\n\nstruct x86_platform_ops {\n\tlong unsigned int (*calibrate_cpu)(void);\n\tlong unsigned int (*calibrate_tsc)(void);\n\tvoid (*get_wallclock)(struct timespec64 *);\n\tint (*set_wallclock)(const struct timespec64 *);\n\tvoid (*iommu_shutdown)(void);\n\tbool (*is_untracked_pat_range)(u64, u64);\n\tvoid (*nmi_init)(void);\n\tunsigned char (*get_nmi_reason)(void);\n\tvoid (*save_sched_clock_state)(void);\n\tvoid (*restore_sched_clock_state)(void);\n\tvoid (*apic_post_init)(void);\n\tstruct x86_legacy_features legacy;\n\tvoid (*set_legacy_features)(void);\n\tvoid (*realmode_reserve)(void);\n\tvoid (*realmode_init)(void);\n\tstruct x86_hyper_runtime hyper;\n\tstruct x86_guest guest;\n};\n\nstruct x86_pmu_quirk;\n\nstruct x86_pmu {\n\tconst char *name;\n\tint version;\n\tint (*handle_irq)(struct pt_regs *);\n\tvoid (*disable_all)(void);\n\tvoid (*enable_all)(int);\n\tvoid (*enable)(struct perf_event *);\n\tvoid (*disable)(struct perf_event *);\n\tvoid (*assign)(struct perf_event *, int);\n\tvoid (*add)(struct perf_event *);\n\tvoid (*del)(struct perf_event *);\n\tvoid (*read)(struct perf_event *);\n\tint (*set_period)(struct perf_event *);\n\tu64 (*update)(struct perf_event *);\n\tint (*hw_config)(struct perf_event *);\n\tint (*schedule_events)(struct cpu_hw_events *, int, int *);\n\tvoid (*late_setup)(void);\n\tvoid (*pebs_enable)(struct perf_event *);\n\tvoid (*pebs_disable)(struct perf_event *);\n\tvoid (*pebs_enable_all)(void);\n\tvoid (*pebs_disable_all)(void);\n\tunsigned int eventsel;\n\tunsigned int perfctr;\n\tunsigned int fixedctr;\n\tint (*addr_offset)(int, bool);\n\tint (*rdpmc_index)(int);\n\tu64 (*event_map)(int);\n\tint max_events;\n\tu64 config_mask;\n\tunion {\n\t\tu64 cntr_mask64;\n\t\tlong unsigned int cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 fixed_cntr_mask64;\n\t\tlong unsigned int fixed_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cntr_mask64;\n\t\tlong unsigned int acr_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cause_mask64;\n\t\tlong unsigned int acr_cause_mask[1];\n\t};\n\tint cntval_bits;\n\tu64 cntval_mask;\n\tunion {\n\t\tlong unsigned int events_maskl;\n\t\tlong unsigned int events_mask[1];\n\t};\n\tint events_mask_len;\n\tint apic;\n\tu64 max_period;\n\tstruct event_constraint * (*get_event_constraints)(struct cpu_hw_events *, int, struct perf_event *);\n\tvoid (*put_event_constraints)(struct cpu_hw_events *, struct perf_event *);\n\tvoid (*start_scheduling)(struct cpu_hw_events *);\n\tvoid (*commit_scheduling)(struct cpu_hw_events *, int, int);\n\tvoid (*stop_scheduling)(struct cpu_hw_events *);\n\tstruct event_constraint *event_constraints;\n\tstruct x86_pmu_quirk *quirks;\n\tvoid (*limit_period)(struct perf_event *, s64 *);\n\tunsigned int late_ack: 1;\n\tunsigned int mid_ack: 1;\n\tunsigned int enabled_ack: 1;\n\tint attr_rdpmc_broken;\n\tint attr_rdpmc;\n\tstruct attribute **format_attrs;\n\tssize_t (*events_sysfs_show)(char *, u64);\n\tconst struct attribute_group **attr_update;\n\tlong unsigned int attr_freeze_on_smi;\n\tint (*cpu_prepare)(int);\n\tvoid (*cpu_starting)(int);\n\tvoid (*cpu_dying)(int);\n\tvoid (*cpu_dead)(int);\n\tvoid (*check_microcode)(void);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tu64 intel_ctrl;\n\tunion perf_capabilities intel_cap;\n\tunsigned int bts: 1;\n\tunsigned int bts_active: 1;\n\tunsigned int ds_pebs: 1;\n\tunsigned int pebs_active: 1;\n\tunsigned int pebs_broken: 1;\n\tunsigned int pebs_prec_dist: 1;\n\tunsigned int pebs_no_tlb: 1;\n\tunsigned int pebs_no_isolation: 1;\n\tunsigned int pebs_block: 1;\n\tunsigned int pebs_ept: 1;\n\tunsigned int arch_pebs: 1;\n\tint pebs_record_size;\n\tint pebs_buffer_size;\n\tu64 pebs_events_mask;\n\tvoid (*drain_pebs)(struct pt_regs *, struct perf_sample_data *);\n\tstruct event_constraint *pebs_constraints;\n\tvoid (*pebs_aliases)(struct perf_event *);\n\tu64 (*pebs_latency_data)(struct perf_event *, u64);\n\tlong unsigned int large_pebs_flags;\n\tu64 rtm_abort_event;\n\tu64 pebs_capable;\n\tstruct arch_pebs_cap arch_pebs_cap;\n\tunsigned int lbr_tos;\n\tunsigned int lbr_from;\n\tunsigned int lbr_to;\n\tunsigned int lbr_info;\n\tunsigned int lbr_nr;\n\tunion {\n\t\tu64 lbr_sel_mask;\n\t\tu64 lbr_ctl_mask;\n\t};\n\tunion {\n\t\tconst int *lbr_sel_map;\n\t\tint *lbr_ctl_map;\n\t};\n\tu64 lbr_callstack_users;\n\tbool lbr_double_abort;\n\tbool lbr_pt_coexist;\n\tunsigned int lbr_has_info: 1;\n\tunsigned int lbr_has_tsx: 1;\n\tunsigned int lbr_from_flags: 1;\n\tunsigned int lbr_to_cycles: 1;\n\tunsigned int lbr_depth_mask: 8;\n\tunsigned int lbr_deep_c_reset: 1;\n\tunsigned int lbr_lip: 1;\n\tunsigned int lbr_cpl: 1;\n\tunsigned int lbr_filter: 1;\n\tunsigned int lbr_call_stack: 1;\n\tunsigned int lbr_mispred: 1;\n\tunsigned int lbr_timed_lbr: 1;\n\tunsigned int lbr_br_type: 1;\n\tunsigned int lbr_counters: 4;\n\tvoid (*lbr_reset)(void);\n\tvoid (*lbr_read)(struct cpu_hw_events *);\n\tvoid (*lbr_save)(void *);\n\tvoid (*lbr_restore)(void *);\n\tatomic_t lbr_exclusive[3];\n\tint num_topdown_events;\n\tunsigned int amd_nb_constraints: 1;\n\tu64 perf_ctr_pair_en;\n\tstruct extra_reg *extra_regs;\n\tunsigned int flags;\n\tstruct perf_guest_switch_msr * (*guest_get_msrs)(int *, void *);\n\tint (*check_period)(struct perf_event *, u64);\n\tint (*aux_output_match)(struct perf_event *);\n\tvoid (*filter)(struct pmu *, int, bool *);\n\tint num_hybrid_pmus;\n\tstruct x86_hybrid_pmu *hybrid_pmu;\n\tenum intel_cpu_type (*get_hybrid_cpu_type)(void);\n};\n\nstruct x86_pmu_capability {\n\tint version;\n\tint num_counters_gp;\n\tint num_counters_fixed;\n\tint bit_width_gp;\n\tint bit_width_fixed;\n\tunsigned int events_mask;\n\tint events_mask_len;\n\tunsigned int pebs_ept: 1;\n\tunsigned int mediated: 1;\n};\n\nunion x86_pmu_config {\n\tstruct {\n\t\tu64 event: 8;\n\t\tu64 umask: 8;\n\t\tu64 usr: 1;\n\t\tu64 os: 1;\n\t\tu64 edge: 1;\n\t\tu64 pc: 1;\n\t\tu64 interrupt: 1;\n\t\tu64 __reserved1: 1;\n\t\tu64 en: 1;\n\t\tu64 inv: 1;\n\t\tu64 cmask: 8;\n\t\tu64 event2: 4;\n\t\tu64 __reserved2: 4;\n\t\tu64 go: 1;\n\t\tu64 ho: 1;\n\t} bits;\n\tu64 value;\n};\n\nstruct x86_pmu_quirk {\n\tstruct x86_pmu_quirk *next;\n\tvoid (*func)(void);\n};\n\nstruct x86_topology_system {\n\tunsigned int dom_shifts[7];\n\tunsigned int dom_size[7];\n};\n\nstruct x86_xfeat_component {\n\t__u32 type;\n\t__u32 size;\n\t__u32 offset;\n\t__u32 flags;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[3];\n\t\tlong unsigned int marks[3];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n\tlong: 64;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 64;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tlong unsigned int *bitmap;\n\tstruct page *page;\n\tlong unsigned int vaddr;\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\nunion zen_patch_rev {\n\tstruct {\n\t\t__u32 rev: 8;\n\t\t__u32 stepping: 4;\n\t\t__u32 model: 4;\n\t\t__u32 __reserved: 4;\n\t\t__u32 ext_model: 4;\n\t\t__u32 ext_fam: 8;\n\t};\n\t__u32 ucode_rev;\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef acpi_status (*acpi_exception_handler)(acpi_status, acpi_name, u16, u32, void *);\n\ntypedef acpi_status (*acpi_execute_op)(struct acpi_walk_state *);\n\ntypedef void (*acpi_gbl_event_handler)(u32, acpi_handle, u32, void *);\n\ntypedef acpi_status (*acpi_gpe_callback)(struct acpi_gpe_xrupt_info *, struct acpi_gpe_block_info *, void *);\n\ntypedef acpi_status (*acpi_init_handler)(acpi_handle, u32);\n\ntypedef u32 (*acpi_interface_handler)(acpi_string, u32);\n\ntypedef u32 (*acpi_osd_handler)(void *);\n\ntypedef acpi_status (*acpi_pkg_callback)(u8, union acpi_operand_object *, union acpi_generic_state *, void *);\n\ntypedef acpi_status (*acpi_table_handler)(u32, void *, void *);\n\ntypedef acpi_status (*acpi_walk_aml_callback)(u8 *, u32, u32, u8, void **);\n\ntypedef acpi_status (*acpi_walk_resource_callback)(struct acpi_resource *, void *);\n\ntypedef void amd_pmu_branch_reset_t(void);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\ntypedef void blk_log_action_t(struct trace_iterator *, const char *, bool);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u32 (*bpf_prog_run_fn)(const struct bpf_prog *, const void *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_d_path)(const struct path *, char *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_pe)(struct bpf_perf_event_data_kern *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_trace)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_branch_snapshot)(void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid_curr)(void);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_task)(void);\n\ntypedef u64 (*btf_bpf_get_current_task_btf)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_func_ip_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_local_storage)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sockopt)(struct bpf_sockopt_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_retval)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_pe)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_sleepable)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_pe)(struct bpf_perf_event_data_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack_sleepable)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_probe_read_compat)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_printf_btf)(struct seq_file *, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_set_retval)(int);\n\ntypedef u64 (*btf_bpf_sk_ancestor_cgroup_id)(struct sock *, int);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_cgroup_id)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_ancestor_cgroup_id)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_cgroup_id)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_snprintf_btf)(char *, u32, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_sysctl_get_current_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_get_name)(struct bpf_sysctl_kern *, char *, size_t, u64);\n\ntypedef u64 (*btf_bpf_sysctl_get_new_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_set_new_value)(struct bpf_sysctl_kern *, const char *, size_t);\n\ntypedef u64 (*btf_bpf_task_pt_regs)(struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv4)(struct iphdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv4)(struct iphdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_vprintk)(char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_get_func_arg)(void *, u32, u64 *);\n\ntypedef u64 (*btf_get_func_arg_cnt)(void *);\n\ntypedef u64 (*btf_get_func_ret)(void *, u64 *);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*btf_trace_9p_client_req)(void *, struct p9_client *, int8_t, int);\n\ntypedef void (*btf_trace_9p_client_res)(void *, struct p9_client *, int8_t, int, int);\n\ntypedef void (*btf_trace_9p_fid_ref)(void *, struct p9_fid *, __u8);\n\ntypedef void (*btf_trace_9p_protocol_dump)(void *, struct p9_client *, struct p9_fcall *);\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_suspend)(void *, ktime_t, int);\n\ntypedef void (*btf_trace_alloc_vmap_area)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_amd_pstate_epp_perf)(void *, unsigned int, u8, u8, u8, u8, bool, bool);\n\ntypedef void (*btf_trace_amd_pstate_perf)(void *, u8, u8, u8, u64, u64, u64, u64, unsigned int, bool);\n\ntypedef void (*btf_trace_ata_bmdma_setup)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_start)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_status)(void *, struct ata_port *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_stop)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_about_to_do)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_done)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy)(void *, struct ata_device *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy_qc)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_exec_command)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_softreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_softreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_port_freeze)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_port_thaw)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_qc_complete_done)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_failed)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_internal)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_issue)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_prep)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_sff_flush_pio_task)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_sff_hsm_command_complete)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_hsm_state)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_sff_port_intr)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_slave_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_slave_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_slave_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_std_sched_eh)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_tf_load)(void *, struct ata_port *, const struct ata_taskfile *);\n\ntypedef void (*btf_trace_atapi_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_atapi_send_cdb)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_azx_get_position)(void *, struct azx *, struct azx_dev *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_azx_pcm_close)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_hw_params)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_open)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_prepare)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_trigger)(void *, struct azx *, struct azx_dev *, int);\n\ntypedef void (*btf_trace_azx_resume)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_runtime_resume)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_runtime_suspend)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_suspend)(void *, struct azx *);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, struct dirty_throttle_control *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_blk_zone_append_update_request_bio)(void *, struct request *);\n\ntypedef void (*btf_trace_blk_zone_wplug_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_blkdev_zone_mgmt)(void *, struct bio *, sector_t);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_io_done)(void *, struct request *);\n\ntypedef void (*btf_trace_block_io_start)(void *, struct request *);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_error)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_merge)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_split)(void *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\ntypedef void (*btf_trace_bpf_trace_printk)(void *, const char *);\n\ntypedef void (*btf_trace_bpf_trigger_tp)(void *, int);\n\ntypedef void (*btf_trace_bpf_xdp_link_attach_failed)(void *, const char *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_cache_tag_assign)(void *, struct cache_tag *);\n\ntypedef void (*btf_trace_cache_tag_flush_range)(void *, struct cache_tag *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_cache_tag_flush_range_np)(void *, struct cache_tag *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_cache_tag_unassign)(void *, struct cache_tag *);\n\ntypedef void (*btf_trace_call_function_entry)(void *, int);\n\ntypedef void (*btf_trace_call_function_exit)(void *, int);\n\ntypedef void (*btf_trace_call_function_single_entry)(void *, int);\n\ntypedef void (*btf_trace_call_function_single_exit)(void *, int);\n\ntypedef void (*btf_trace_cap_capable)(void *, const struct cred *, struct user_namespace *, const struct user_namespace *, int, int);\n\ntypedef void (*btf_trace_cdev_update)(void *, struct thermal_cooling_device *, long unsigned int);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rstat_lock_contended)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_locked)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_unlock)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_check_mmio_spte)(void *, u64, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_contention_begin)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_contention_end)(void *, void *, int);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_idle_miss)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_csd_function_entry)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_function_exit)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_queue_cpu)(void *, const unsigned int, long unsigned int, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_ctime_ns_xchg)(void *, struct inode *, u32, u32, u32);\n\ntypedef void (*btf_trace_ctime_xchg_skip)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_dax_insert_pfn_mkwrite)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_insert_pfn_mkwrite_no_entry)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_load_hole)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_pmd_fault)(void *, struct inode *, struct vm_fault *, long unsigned int, int);\n\ntypedef void (*btf_trace_dax_pmd_fault_done)(void *, struct inode *, struct vm_fault *, long unsigned int, int);\n\ntypedef void (*btf_trace_dax_pmd_load_hole)(void *, struct inode *, struct vm_fault *, struct folio *, void *);\n\ntypedef void (*btf_trace_dax_pmd_load_hole_fallback)(void *, struct inode *, struct vm_fault *, struct folio *, void *);\n\ntypedef void (*btf_trace_dax_pte_fault)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_pte_fault_done)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_writeback_one)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dax_writeback_range)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dax_writeback_range_done)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_deferred_error_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_deferred_error_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_device_pm_callback_end)(void *, struct device *, int);\n\ntypedef void (*btf_trace_device_pm_callback_start)(void *, struct device *, const char *, int);\n\ntypedef void (*btf_trace_devres_log)(void *, struct device *, const char *, void *, const char *, size_t);\n\ntypedef void (*btf_trace_disk_zone_wplug_add_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_dma_alloc)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt_err)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_buf_detach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_dynamic_attach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_export)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_fd)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_get)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_mmap)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_mmap_internal)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_put)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_free)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_map_phys)(void *, struct device *, phys_addr_t, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg_err)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_sync_sg_for_cpu)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_sg_for_device)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_cpu)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_device)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_unmap_phys)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_unmap_sg)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dql_stall_detected)(void *, short unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_drm_vblank_event)(void *, int, unsigned int, ktime_t, bool);\n\ntypedef void (*btf_trace_drm_vblank_event_delivered)(void *, struct drm_file *, int, unsigned int);\n\ntypedef void (*btf_trace_drm_vblank_event_queued)(void *, struct drm_file *, int, unsigned int);\n\ntypedef void (*btf_trace_emulate_vsyscall)(void *, int);\n\ntypedef void (*btf_trace_error_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_error_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_error_report_end)(void *, enum error_detector, long unsigned int);\n\ntypedef void (*btf_trace_exit_mmap)(void *, struct mm_struct *);\n\ntypedef void (*btf_trace_fast_page_fault)(void *, struct kvm_vcpu *, struct kvm_page_fault *, u64 *, u64, int);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_fill_mg_cmtime)(void *, struct inode *, struct timespec64 *, struct timespec64 *);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_folio_wait_writeback)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_free_vmap_area_noflush)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_fuse_request_end)(void *, const struct fuse_req *);\n\ntypedef void (*btf_trace_fuse_request_send)(void *, const struct fuse_req *);\n\ntypedef void (*btf_trace_g4x_wm)(void *, struct intel_crtc *, const struct g4x_wm_values *);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_guest_halt_poll_ns)(void *, bool, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_handle_mmio_page_fault)(void *, u64, gfn_t, unsigned int);\n\ntypedef void (*btf_trace_hda_get_response)(void *, struct hdac_bus *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_hda_send_cmd)(void *, struct hdac_bus *, unsigned int);\n\ntypedef void (*btf_trace_hda_unsol_event)(void *, struct hdac_bus *, u32, u32);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_setup)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hugetlbfs_alloc_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_hugetlbfs_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_fallocate)(void *, struct inode *, int, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_hugetlbfs_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_setattr)(void *, struct inode *, struct dentry *, struct iattr *);\n\ntypedef void (*btf_trace_hwmon_attr_show)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_hwmon_attr_show_string)(void *, int, const char *, const char *);\n\ntypedef void (*btf_trace_hwmon_attr_store)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_i2c_read)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_reply)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_result)(void *, const struct i2c_adapter *, int, int);\n\ntypedef void (*btf_trace_i2c_write)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i915_context_create)(void *, struct i915_gem_context *);\n\ntypedef void (*btf_trace_i915_context_free)(void *, struct i915_gem_context *);\n\ntypedef void (*btf_trace_i915_gem_evict)(void *, struct i915_address_space *, u64, u64, unsigned int);\n\ntypedef void (*btf_trace_i915_gem_evict_node)(void *, struct i915_address_space *, struct drm_mm_node *, unsigned int);\n\ntypedef void (*btf_trace_i915_gem_evict_vm)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_gem_object_clflush)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_object_create)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_object_destroy)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_object_fault)(void *, struct drm_i915_gem_object *, u64, bool, bool);\n\ntypedef void (*btf_trace_i915_gem_object_pread)(void *, struct drm_i915_gem_object *, u64, u64);\n\ntypedef void (*btf_trace_i915_gem_object_pwrite)(void *, struct drm_i915_gem_object *, u64, u64);\n\ntypedef void (*btf_trace_i915_gem_shrink)(void *, struct drm_i915_private *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_i915_ppgtt_create)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_ppgtt_release)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_reg_rw)(void *, bool, i915_reg_t, u64, int, bool);\n\ntypedef void (*btf_trace_i915_request_add)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_request_queue)(void *, struct i915_request *, u32);\n\ntypedef void (*btf_trace_i915_request_retire)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_request_wait_begin)(void *, struct i915_request *, unsigned int);\n\ntypedef void (*btf_trace_i915_request_wait_end)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_vma_bind)(void *, struct i915_vma *, unsigned int);\n\ntypedef void (*btf_trace_i915_vma_unbind)(void *, struct i915_vma *);\n\ntypedef void (*btf_trace_icmp_send)(void *, const struct sk_buff *, int, int);\n\ntypedef void (*btf_trace_inet_sk_error_report)(void *, const struct sock *);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_inode_set_ctime_to_ts)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_intel_cpu_fifo_underrun)(void *, struct intel_display *, enum pipe);\n\ntypedef void (*btf_trace_intel_crtc_flip_done)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_crtc_vblank_work_end)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_crtc_vblank_work_start)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_fbc_activate)(void *, struct intel_plane *);\n\ntypedef void (*btf_trace_intel_fbc_deactivate)(void *, struct intel_plane *);\n\ntypedef void (*btf_trace_intel_fbc_nuke)(void *, struct intel_plane *);\n\ntypedef void (*btf_trace_intel_frontbuffer_flush)(void *, struct intel_display *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_intel_frontbuffer_invalidate)(void *, struct intel_display *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_intel_memory_cxsr)(void *, struct intel_display *, bool, bool);\n\ntypedef void (*btf_trace_intel_pch_fifo_underrun)(void *, struct intel_display *, enum pipe);\n\ntypedef void (*btf_trace_intel_pipe_crc)(void *, struct intel_crtc *, const u32 *);\n\ntypedef void (*btf_trace_intel_pipe_disable)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_enable)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_scaler_update_arm)(void *, struct intel_crtc *, int, int, int, int, int);\n\ntypedef void (*btf_trace_intel_pipe_update_end)(void *, struct intel_crtc *, u32, int);\n\ntypedef void (*btf_trace_intel_pipe_update_start)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_update_vblank_evaded)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_plane_async_flip)(void *, struct intel_plane *, struct intel_crtc *, bool);\n\ntypedef void (*btf_trace_intel_plane_disable_arm)(void *, struct intel_plane *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_plane_scaler_update_arm)(void *, struct intel_plane *, int, int, int, int, int);\n\ntypedef void (*btf_trace_intel_plane_update_arm)(void *, const struct intel_plane_state *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_plane_update_noarm)(void *, const struct intel_plane_state *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_scaler_disable_arm)(void *, struct intel_crtc *, int);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, struct io_ring_ctx *, void *, struct io_uring_cqe *);\n\ntypedef void (*btf_trace_io_uring_cqe_overflow)(void *, void *, long long unsigned int, s32, u32, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_local_work_run)(void *, void *, int, unsigned int);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, struct io_kiocb *, int, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, struct io_kiocb *, bool);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, long int);\n\ntypedef void (*btf_trace_io_uring_req_failed)(void *, const struct io_uring_sqe *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_short_write)(void *, void *, u64, u64, u64);\n\ntypedef void (*btf_trace_io_uring_submit_req)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_task_work_run)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_iocost_inuse_adjust)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_inuse_shortage)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_inuse_transfer)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_ioc_vrate_adj)(void *, struct ioc *, u64, u32 *, u32, int, int);\n\ntypedef void (*btf_trace_iocost_iocg_activate)(void *, struct ioc_gq *, const char *, struct ioc_now *, u64, u64, u64);\n\ntypedef void (*btf_trace_iocost_iocg_forgive_debt)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_iocost_iocg_idle)(void *, struct ioc_gq *, const char *, struct ioc_now *, u64, u64, u64);\n\ntypedef void (*btf_trace_iomap_add_to_ioend)(void *, struct inode *, u64, unsigned int, struct iomap *);\n\ntypedef void (*btf_trace_iomap_dio_complete)(void *, struct kiocb *, int, ssize_t);\n\ntypedef void (*btf_trace_iomap_dio_invalidate_fail)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_dio_rw_begin)(void *, struct kiocb *, struct iov_iter *, unsigned int, size_t);\n\ntypedef void (*btf_trace_iomap_dio_rw_queued)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_invalidate_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_iter)(void *, struct iomap_iter *, const void *, long unsigned int);\n\ntypedef void (*btf_trace_iomap_iter_dstmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_iter_srcmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_release_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_writeback_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_zero_iter)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_ipi_send_cpu)(void *, const unsigned int, long unsigned int, void *);\n\ntypedef void (*btf_trace_ipi_send_cpumask)(void *, const struct cpumask *, long unsigned int, void *);\n\ntypedef void (*btf_trace_irq_disable)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_irq_enable)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_irq_matrix_alloc)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_alloc_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_assign)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_assign_system)(void *, int, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_free)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_offline)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_online)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_remove_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_remove_reserved)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_reserve)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_reserve_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_work_entry)(void *, int);\n\ntypedef void (*btf_trace_irq_work_exit)(void *, int);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *, enum skb_drop_reason, struct sock *);\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, struct kmem_cache *, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *, const struct kmem_cache *);\n\ntypedef void (*btf_trace_kvm_ack_irq)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_age_hva)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_apic)(void *, unsigned int, unsigned int, u64);\n\ntypedef void (*btf_trace_kvm_apic_accept_irq)(void *, __u32, __u16, __u16, __u8);\n\ntypedef void (*btf_trace_kvm_apic_ipi)(void *, __u32, __u32);\n\ntypedef void (*btf_trace_kvm_apicv_accept_irq)(void *, __u32, __u16, __u16, __u8);\n\ntypedef void (*btf_trace_kvm_apicv_inhibit_changed)(void *, int, bool, long unsigned int);\n\ntypedef void (*btf_trace_kvm_async_pf_completed)(void *, long unsigned int, u64);\n\ntypedef void (*btf_trace_kvm_async_pf_not_present)(void *, u64, u64);\n\ntypedef void (*btf_trace_kvm_async_pf_ready)(void *, u64, u64);\n\ntypedef void (*btf_trace_kvm_async_pf_repeated_fault)(void *, u64, u64);\n\ntypedef void (*btf_trace_kvm_avic_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_kvm_avic_ga_log)(void *, u32, u32);\n\ntypedef void (*btf_trace_kvm_avic_incomplete_ipi)(void *, u32, u32, u32, u32, u32);\n\ntypedef void (*btf_trace_kvm_avic_kick_vcpu_slowpath)(void *, u32, u32, u32);\n\ntypedef void (*btf_trace_kvm_avic_unaccelerated_access)(void *, u32, u32, bool, bool, u32);\n\ntypedef void (*btf_trace_kvm_cpuid)(void *, unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, bool, bool);\n\ntypedef void (*btf_trace_kvm_cr)(void *, unsigned int, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_dirty_ring_exit)(void *, struct kvm_vcpu *);\n\ntypedef void (*btf_trace_kvm_dirty_ring_push)(void *, struct kvm_dirty_ring *, u32, u64);\n\ntypedef void (*btf_trace_kvm_dirty_ring_reset)(void *, struct kvm_dirty_ring *);\n\ntypedef void (*btf_trace_kvm_emulate_insn)(void *, struct kvm_vcpu *, __u8);\n\ntypedef void (*btf_trace_kvm_entry)(void *, struct kvm_vcpu *, bool);\n\ntypedef void (*btf_trace_kvm_eoi)(void *, struct kvm_lapic *, int);\n\ntypedef void (*btf_trace_kvm_exit)(void *, struct kvm_vcpu *, u32);\n\ntypedef void (*btf_trace_kvm_fast_mmio)(void *, u64);\n\ntypedef void (*btf_trace_kvm_fpu)(void *, int);\n\ntypedef void (*btf_trace_kvm_halt_poll_ns)(void *, bool, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_hv_flush_tlb)(void *, u64, u64, u64, bool);\n\ntypedef void (*btf_trace_kvm_hv_flush_tlb_ex)(void *, u64, u64, u64, u64, bool);\n\ntypedef void (*btf_trace_kvm_hv_hypercall)(void *, __u16, bool, __u16, __u16, __u16, __u64, __u64);\n\ntypedef void (*btf_trace_kvm_hv_hypercall_done)(void *, u64);\n\ntypedef void (*btf_trace_kvm_hv_notify_acked_sint)(void *, int, u32);\n\ntypedef void (*btf_trace_kvm_hv_send_ipi)(void *, u32, u64);\n\ntypedef void (*btf_trace_kvm_hv_send_ipi_ex)(void *, u32, u64, u64);\n\ntypedef void (*btf_trace_kvm_hv_stimer_callback)(void *, int, int);\n\ntypedef void (*btf_trace_kvm_hv_stimer_cleanup)(void *, int, int);\n\ntypedef void (*btf_trace_kvm_hv_stimer_expiration)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_kvm_hv_stimer_set_config)(void *, int, int, u64, bool);\n\ntypedef void (*btf_trace_kvm_hv_stimer_set_count)(void *, int, int, u64, bool);\n\ntypedef void (*btf_trace_kvm_hv_stimer_start_one_shot)(void *, int, int, u64, u64);\n\ntypedef void (*btf_trace_kvm_hv_stimer_start_periodic)(void *, int, int, u64, u64);\n\ntypedef void (*btf_trace_kvm_hv_syndbg_get_msr)(void *, int, u32, u32, u64);\n\ntypedef void (*btf_trace_kvm_hv_syndbg_set_msr)(void *, int, u32, u32, u64);\n\ntypedef void (*btf_trace_kvm_hv_synic_send_eoi)(void *, int, int);\n\ntypedef void (*btf_trace_kvm_hv_synic_set_irq)(void *, int, u32, int, int);\n\ntypedef void (*btf_trace_kvm_hv_synic_set_msr)(void *, int, u32, u64, bool);\n\ntypedef void (*btf_trace_kvm_hv_timer_state)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_hypercall)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_inj_exception)(void *, unsigned int, bool, unsigned int, bool);\n\ntypedef void (*btf_trace_kvm_inj_virq)(void *, unsigned int, bool, bool);\n\ntypedef void (*btf_trace_kvm_invlpga)(void *, __u64, unsigned int, u64);\n\ntypedef void (*btf_trace_kvm_ioapic_delayed_eoi_inj)(void *, __u64);\n\ntypedef void (*btf_trace_kvm_ioapic_set_irq)(void *, __u64, int, bool);\n\ntypedef void (*btf_trace_kvm_mmio)(void *, int, int, u64, void *);\n\ntypedef void (*btf_trace_kvm_mmu_get_page)(void *, struct kvm_mmu_page *, bool);\n\ntypedef void (*btf_trace_kvm_mmu_pagetable_walk)(void *, u64, u32);\n\ntypedef void (*btf_trace_kvm_mmu_paging_element)(void *, u64, int);\n\ntypedef void (*btf_trace_kvm_mmu_prepare_zap_page)(void *, struct kvm_mmu_page *);\n\ntypedef void (*btf_trace_kvm_mmu_set_accessed_bit)(void *, long unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_mmu_set_dirty_bit)(void *, long unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_mmu_set_spte)(void *, int, gfn_t, u64 *);\n\ntypedef void (*btf_trace_kvm_mmu_split_huge_page)(void *, u64, u64, int, int);\n\ntypedef void (*btf_trace_kvm_mmu_spte_requested)(void *, struct kvm_page_fault *);\n\ntypedef void (*btf_trace_kvm_mmu_sync_page)(void *, struct kvm_mmu_page *);\n\ntypedef void (*btf_trace_kvm_mmu_unsync_page)(void *, struct kvm_mmu_page *);\n\ntypedef void (*btf_trace_kvm_mmu_walker_error)(void *, u32);\n\ntypedef void (*btf_trace_kvm_mmu_zap_all_fast)(void *, struct kvm *);\n\ntypedef void (*btf_trace_kvm_msi_set_irq)(void *, __u64, __u64);\n\ntypedef void (*btf_trace_kvm_msr)(void *, unsigned int, u32, u64, bool);\n\ntypedef void (*btf_trace_kvm_nested_intercepts)(void *, __u16, __u16, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_kvm_nested_intr_vmexit)(void *, __u64);\n\ntypedef void (*btf_trace_kvm_nested_vmenter)(void *, __u64, __u64, __u64, __u32, __u32, bool, __u64, __u64, __u32);\n\ntypedef void (*btf_trace_kvm_nested_vmenter_failed)(void *, const char *, u32);\n\ntypedef void (*btf_trace_kvm_nested_vmexit)(void *, struct kvm_vcpu *, u32);\n\ntypedef void (*btf_trace_kvm_nested_vmexit_inject)(void *, __u64, __u64, __u64, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_kvm_page_fault)(void *, struct kvm_vcpu *, u64, u64);\n\ntypedef void (*btf_trace_kvm_pi_irte_update)(void *, unsigned int, struct kvm_vcpu *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_kvm_pic_set_irq)(void *, __u8, __u8, __u8, __u8, bool);\n\ntypedef void (*btf_trace_kvm_pio)(void *, unsigned int, unsigned int, unsigned int, unsigned int, const void *);\n\ntypedef void (*btf_trace_kvm_ple_window_update)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_pml_full)(void *, unsigned int);\n\ntypedef void (*btf_trace_kvm_pv_eoi)(void *, struct kvm_lapic *, int);\n\ntypedef void (*btf_trace_kvm_pv_tlb_flush)(void *, unsigned int, bool);\n\ntypedef void (*btf_trace_kvm_pvclock_update)(void *, unsigned int, struct pvclock_vcpu_time_info *);\n\ntypedef void (*btf_trace_kvm_rmp_fault)(void *, struct kvm_vcpu *, u64, u64, u64, int, int);\n\ntypedef void (*btf_trace_kvm_set_irq)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_kvm_skinit)(void *, __u64, __u32);\n\ntypedef void (*btf_trace_kvm_smm_transition)(void *, unsigned int, u64, bool);\n\ntypedef void (*btf_trace_kvm_tdp_mmu_spte_changed)(void *, int, gfn_t, int, u64, u64);\n\ntypedef void (*btf_trace_kvm_test_age_hva)(void *, long unsigned int);\n\ntypedef void (*btf_trace_kvm_track_tsc)(void *, unsigned int, unsigned int, unsigned int, bool, unsigned int);\n\ntypedef void (*btf_trace_kvm_try_async_get_page)(void *, u64, u64);\n\ntypedef void (*btf_trace_kvm_unmap_hva_range)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_update_master_clock)(void *, bool, unsigned int, bool);\n\ntypedef void (*btf_trace_kvm_userspace_exit)(void *, __u32, int);\n\ntypedef void (*btf_trace_kvm_vcpu_wakeup)(void *, __u64, bool, bool);\n\ntypedef void (*btf_trace_kvm_vmgexit_enter)(void *, unsigned int, struct ghcb *);\n\ntypedef void (*btf_trace_kvm_vmgexit_exit)(void *, unsigned int, struct ghcb *);\n\ntypedef void (*btf_trace_kvm_vmgexit_msr_protocol_enter)(void *, unsigned int, u64);\n\ntypedef void (*btf_trace_kvm_vmgexit_msr_protocol_exit)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_kvm_wait_lapic_expire)(void *, unsigned int, s64);\n\ntypedef void (*btf_trace_kvm_write_tsc_offset)(void *, unsigned int, __u64, __u64);\n\ntypedef void (*btf_trace_kvm_xen_hypercall)(void *, u8, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, dev_t, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_latency)(void *, dev_t, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, dev_t, const char *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lease *, struct file_lease *);\n\ntypedef void (*btf_trace_local_timer_entry)(void *, int);\n\ntypedef void (*btf_trace_local_timer_exit)(void *, int);\n\ntypedef void (*btf_trace_lock_acquire)(void *, struct lockdep_map *, unsigned int, int, int, int, struct lockdep_map *, long unsigned int);\n\ntypedef void (*btf_trace_lock_release)(void *, struct lockdep_map *, long unsigned int);\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ma_op)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_read)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_write)(void *, const char *, struct ma_state *, long unsigned int, void *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_mark_mmio_spte)(void *, u64 *, gfn_t, u64);\n\ntypedef void (*btf_trace_mark_victim)(void *, struct task_struct *, uid_t);\n\ntypedef void (*btf_trace_mce_record)(void *, struct mce_hw_err *);\n\ntypedef void (*btf_trace_mdio_access)(void *, struct mii_bus *, char, u8, unsigned int, u16, int);\n\ntypedef void (*btf_trace_mei_pci_cfg_read)(void *, const struct device *, const char *, u32, u32);\n\ntypedef void (*btf_trace_mei_reg_read)(void *, const struct device *, const char *, u32, u32);\n\ntypedef void (*btf_trace_mei_reg_write)(void *, const struct device *, const char *, u32, u32);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_mm_calculate_totalreserve_pages)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, struct compact_control *, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, struct compact_control *, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_fast_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_fault)(void *, struct address_space *, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_get_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_map_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_migrate_pages_start)(void *, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_lowmem_reserve)(void *, struct zone *, struct zone *, long int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_wmarks)(void *, struct zone *);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_clear_hopeless)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_reclaim_fail)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_reclaim_pages)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *);\n\ntypedef void (*btf_trace_mm_vmscan_throttled)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_write_folio)(void *, struct folio *);\n\ntypedef void (*btf_trace_mmap_lock_acquire_returned)(void *, struct mm_struct *, bool, bool);\n\ntypedef void (*btf_trace_mmap_lock_released)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmap_lock_start_locking)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_netfs_collect)(void *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_collect_folio)(void *, const struct netfs_io_request *, const struct folio *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_gap)(void *, const struct netfs_io_request *, const struct netfs_io_stream *, long long unsigned int, char);\n\ntypedef void (*btf_trace_netfs_collect_sreq)(void *, const struct netfs_io_request *, const struct netfs_io_subrequest *);\n\ntypedef void (*btf_trace_netfs_collect_state)(void *, const struct netfs_io_request *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_stream)(void *, const struct netfs_io_request *, const struct netfs_io_stream *);\n\ntypedef void (*btf_trace_netfs_copy2cache)(void *, const struct netfs_io_request *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_failure)(void *, struct netfs_io_request *, struct netfs_io_subrequest *, int, enum netfs_failure);\n\ntypedef void (*btf_trace_netfs_folio)(void *, struct folio *, enum netfs_folio_trace);\n\ntypedef void (*btf_trace_netfs_folioq)(void *, const struct folio_queue *, enum netfs_folioq_trace);\n\ntypedef void (*btf_trace_netfs_read)(void *, struct netfs_io_request *, loff_t, size_t, enum netfs_read_trace);\n\ntypedef void (*btf_trace_netfs_rreq)(void *, struct netfs_io_request *, enum netfs_rreq_trace);\n\ntypedef void (*btf_trace_netfs_rreq_ref)(void *, unsigned int, int, enum netfs_rreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_sreq)(void *, struct netfs_io_subrequest *, enum netfs_sreq_trace);\n\ntypedef void (*btf_trace_netfs_sreq_ref)(void *, unsigned int, unsigned int, int, enum netfs_sreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_write)(void *, const struct netfs_io_request *, enum netfs_write_trace);\n\ntypedef void (*btf_trace_netfs_write_iter)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netlink_extack)(void *, const char *);\n\ntypedef void (*btf_trace_nmi_handler)(void *, void *, s64, int);\n\ntypedef void (*btf_trace_notifier_register)(void *, void *);\n\ntypedef void (*btf_trace_notifier_run)(void *, void *);\n\ntypedef void (*btf_trace_notifier_unregister)(void *, void *);\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_page_cache_async_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_ra_order)(void *, struct inode *, long unsigned int, struct file_ra_state *);\n\ntypedef void (*btf_trace_page_cache_ra_unbounded)(void *, struct inode *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_sync_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_fault_kernel)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\ntypedef void (*btf_trace_page_fault_user)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\ntypedef void (*btf_trace_page_pool_release)(void *, const struct page_pool *, s32, u32, u32);\n\ntypedef void (*btf_trace_page_pool_state_hold)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_state_release)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_update_nid)(void *, const struct page_pool *, int);\n\ntypedef void (*btf_trace_pci_hp_event)(void *, const char *, const char *, const int);\n\ntypedef void (*btf_trace_pcie_link_event)(void *, struct pci_bus *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pelt_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_pelt_dl_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_hw_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_irq_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_rt_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, long unsigned int, bool, bool, size_t, size_t, void *, int, void *, size_t, gfp_t);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_prq_report)(void *, struct intel_iommu *, struct device *, u64, u64, u64, u64, long unsigned int);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_purge_vmap_area_lazy)(void *, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_enqueue)(void *, struct Qdisc *, const struct netdev_queue *, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qi_submit)(void *, struct intel_iommu *, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_invoke_kvfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_segcb_stats)(void *, struct rcu_segcblist *, const char *);\n\ntypedef void (*btf_trace_rcu_sr_normal)(void *, const char *, struct callback_head *, const char *);\n\ntypedef void (*btf_trace_rcu_stall_warning)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_watching)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_rdpmc)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_read_msr)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_regcache_drop_region)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regcache_sync)(void *, struct regmap *, const char *, const char *);\n\ntypedef void (*btf_trace_regmap_async_complete_done)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_start)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_io_complete)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_bulk_read)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_bulk_write)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_cache_bypass)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_cache_only)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_hw_read_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_read_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_reg_read)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read_cache)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_write)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_reschedule_entry)(void *, int);\n\ntypedef void (*btf_trace_reschedule_exit)(void *, int);\n\ntypedef void (*btf_trace_rpm_idle)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_resume)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_return_int)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_rpm_status)(void *, struct device *, enum rpm_status);\n\ntypedef void (*btf_trace_rpm_suspend)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_usage)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int);\n\ntypedef void (*btf_trace_rtc_alarm_irq_enable)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_freq)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_state)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_read_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_read_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_set_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_timer_dequeue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_enqueue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_fired)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sched_compute_energy_tp)(void *, struct task_struct *, int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_sched_cpu_capacity_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_sched_entry_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_exit_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_ext_bypass_lb)(void *, __u32, __u32, __u32, __u32, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_sched_ext_dump)(void *, const char *);\n\ntypedef void (*btf_trace_sched_ext_event)(void *, const char *, __s64);\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_end)(void *, struct kthread_work *, kthread_work_func_t);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_start)(void *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_kthread_work_queue_work)(void *, struct kthread_worker *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_move_numa)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_overutilized_tp)(void *, struct root_domain *, bool);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_prepare_exec)(void *, struct task_struct *, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_set_need_resched_tp)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_skip_cpuset_numa)(void *, struct task_struct *, nodemask_t *);\n\ntypedef void (*btf_trace_sched_skip_vma_numa)(void *, struct mm_struct *, struct vm_area_struct *, enum numa_vmaskip_reason);\n\ntypedef void (*btf_trace_sched_stat_blocked)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_iowait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_sleep)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_wait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stick_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_swap_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *, unsigned int);\n\ntypedef void (*btf_trace_sched_update_nr_running_tp)(void *, struct rq *, int);\n\ntypedef void (*btf_trace_sched_util_est_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_sched_util_est_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\ntypedef void (*btf_trace_set_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sk_data_ready)(void *, const struct sock *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_smbus_read)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int);\n\ntypedef void (*btf_trace_smbus_reply)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *, int);\n\ntypedef void (*btf_trace_smbus_result)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, int);\n\ntypedef void (*btf_trace_smbus_write)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *);\n\ntypedef void (*btf_trace_snd_hdac_stream_start)(void *, struct hdac_bus *, struct hdac_stream *);\n\ntypedef void (*btf_trace_snd_hdac_stream_stop)(void *, struct hdac_bus *, struct hdac_stream *);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_recv_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_sock_send_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\ntypedef void (*btf_trace_spurious_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_spurious_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_swiotlb_bounced)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_task_prctl_unknown)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef void (*btf_trace_tasklet_entry)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tasklet_exit)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tcp_ao_handshake_failure)(void *, const struct sock *, const struct sk_buff *, const __u8, const __u8, const __u8);\n\ntypedef void (*btf_trace_tcp_bad_csum)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_cong_state_set)(void *, struct sock *, const u8);\n\ntypedef void (*btf_trace_tcp_cwnd_reduction_tp)(void *, const struct sock *, int, int, int);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_hash_ao_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_bad_header)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_mismatch)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_unexpected)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *, const enum sk_rst_reason);\n\ntypedef void (*btf_trace_tcp_sendmsg_locked)(void *, const struct sock *, const struct msghdr *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_test_pages_isolated)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_thermal_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_thermal_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_thermal_temperature)(void *, struct thermal_zone_device *);\n\ntypedef void (*btf_trace_thermal_zone_trip)(void *, struct thermal_zone_device *, int, enum thermal_trip_type);\n\ntypedef void (*btf_trace_threshold_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_threshold_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_timer_base_idle)(void *, bool, unsigned int);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_tlb_flush)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_tmigr_connect_child_parent)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_connect_cpu_parent)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_active)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_available)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_unavailable)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_group_set)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_active)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_inactive)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_handle_remote)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_handle_remote_cpu)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_update_events)(void *, struct tmigr_group *, struct tmigr_group *, union tmigr_state, union tmigr_state, u64);\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_vcpu_match_mmio)(void *, gva_t, gpa_t, bool, bool);\n\ntypedef void (*btf_trace_vector_activate)(void *, unsigned int, bool, bool, bool);\n\ntypedef void (*btf_trace_vector_alloc)(void *, unsigned int, unsigned int, bool, int);\n\ntypedef void (*btf_trace_vector_alloc_managed)(void *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_vector_clear)(void *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_vector_config)(void *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_vector_deactivate)(void *, unsigned int, bool, bool, bool);\n\ntypedef void (*btf_trace_vector_free_moved)(void *, unsigned int, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_vector_reserve)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_vector_reserve_managed)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_vector_setup)(void *, unsigned int, bool, int);\n\ntypedef void (*btf_trace_vector_teardown)(void *, unsigned int, bool, bool);\n\ntypedef void (*btf_trace_vector_update)(void *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_virtio_gpu_cmd_queue)(void *, struct virtqueue *, struct virtio_gpu_ctrl_hdr *, u32);\n\ntypedef void (*btf_trace_virtio_gpu_cmd_response)(void *, struct virtqueue *, struct virtio_gpu_ctrl_hdr *, u32);\n\ntypedef void (*btf_trace_virtio_transport_alloc_pkt)(void *, __u32, __u32, __u32, __u32, __u32, __u16, __u16, __u32, bool);\n\ntypedef void (*btf_trace_virtio_transport_recv_pkt)(void *, __u32, __u32, __u32, __u32, __u32, __u16, __u16, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_vlv_fifo_size)(void *, struct intel_crtc *, u32, u32, u32);\n\ntypedef void (*btf_trace_vlv_wm)(void *, struct intel_crtc *, const struct vlv_wm_values *);\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_watchdog_ping)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_set_timeout)(void *, struct watchdog_device *, unsigned int, int);\n\ntypedef void (*btf_trace_watchdog_start)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_stop)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_write_msr)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_dirty_folio)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, long unsigned int, int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_x86_fpu_after_save)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_before_save)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_copy_dst)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_dropped)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_regs_activated)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_regs_deactivated)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_xstate_check_failed)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_platform_ipi_entry)(void *, int);\n\ntypedef void (*btf_trace_x86_platform_ipi_exit)(void *, int);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int, struct xdp_cpumap_stats *);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef int (*cb_t)(struct param *);\n\ntypedef bool (*check_reserved_t)(u64, u64, enum e820_type);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\ntypedef int (*copy_fn_t)(void *, const void *, u32, struct task_struct *);\n\ntypedef int (*cppc_mode_transition_fn)(int);\n\ntypedef void detailed_cb(const struct detailed_timing *, void *);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef void (*drm_crtc_set_lut_func)(struct drm_crtc *, unsigned int, u16, u16, u16);\n\ntypedef int drm_ioctl_compat_t(struct file *, unsigned int, long unsigned int);\n\ntypedef bool (*drm_vblank_get_scanout_position_func)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\ntypedef int (*efi_memattr_perm_setter)(struct mm_struct *, efi_memory_desc_t *, bool);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, struct mm_struct *);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\ntypedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *, const u8 *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*ftrace_mapper_func)(void *);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef u32 (*hotplug_enables_func)(struct intel_encoder *);\n\ntypedef u32 (*hotplug_mask_func)(enum hpd_pin);\n\ntypedef bool (*i8042_filter_t)(unsigned char, unsigned char, struct serio *, void *);\n\ntypedef int (*i915_user_extension_fn)(struct i915_user_extension *, void *);\n\ntypedef void (*idtentry_t)(struct pt_regs *);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef int (*ioctl_fn)(struct file *, struct dm_ioctl *, size_t);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef int (*map_follower_func_t)(struct hda_codec *, void *, struct snd_kcontrol *);\n\ntypedef void (*mapped_f)(struct perf_event *, struct mm_struct *);\n\ntypedef void modeset_stuck_fn(void *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*msr_access_t)(struct kvm_vcpu *, u32, u64 *, bool);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef void (*nmi_shootdown_cb)(int, struct pt_regs *);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef void (*online_page_callback_t)(struct page *, unsigned int);\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef int (*pcie_callback_t)(struct pcie_device *);\n\ntypedef int (*pcm_transfer_f)(struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\ntypedef int (*pcm_copy_f)(struct snd_pcm_substream *, snd_pcm_uframes_t, void *, snd_pcm_uframes_t, snd_pcm_uframes_t, pcm_transfer_f, bool);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\ntypedef int perf_snapshot_branch_stack_t(struct perf_branch_entry *, unsigned int);\n\ntypedef int (*pm_callback_t)(struct device *);\n\ntypedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef bool (*pps_check)(struct intel_display *, int);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef int (*pt_level_fn_t)(struct pt_range *, void *, unsigned int, struct pt_table_p *);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\ntypedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\ntypedef int (*put_call_t)(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int read_block_fn(void *, u8 *, unsigned int, size_t);\n\ntypedef long unsigned int relocate_kernel_fn(long unsigned int, long unsigned int, long unsigned int, unsigned int);\n\ntypedef int (*reset_func)(struct intel_gt *, intel_engine_mask_t, unsigned int);\n\ntypedef void (*rethook_handler_t)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\ntypedef bool (*ring_buffer_cond_fn)(void *);\n\ntypedef irqreturn_t (*rtc_irq_handler)(int, void *);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef void (*set_debug_port_t)(int);\n\ntypedef void (*setup_fn)(struct perf_event *, struct pt_regs *, void *, struct perf_sample_data *, struct pt_regs *);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*slot_rmaps_handler)(struct kvm *, struct kvm_rmap_head *, const struct kvm_memory_slot *);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int (*snd_seq_dump_func_t)(void *, void *, int);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef long int (*sys_call_ptr_t)(const struct pt_regs *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef void text_poke_f(void *, const void *, size_t);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef int (*trace_user_buf_copy)(char *, const char *, size_t, void *);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*uprobe_write_verify_t)(struct page *, long unsigned int, uprobe_opcode_t *, int, void *);\n\ntypedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *);\n\ntypedef u32 * (*wa_bb_func_t)(struct intel_engine_cs *, u32 *);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef int (*walk_memory_groups_func_t)(struct memory_group *, void *);\n\nstruct audit_buffer;\n\nstruct audit_context;\n\nstruct bpf_iter;\n\nstruct dax_dev;\n\nstruct nf_conntrack;\n\nstruct virtio_gpu_command;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern void *bpf_arena_alloc_pages(void *p__map, void *addr__ign, u32 page_cnt, int node_id, u64 flags) __weak __ksym;\nextern void bpf_arena_free_pages(void *p__map, void *ptr__ign, u32 page_cnt) __weak __ksym;\nextern int bpf_arena_reserve_pages(void *p__map, void *ptr__ign, u32 page_cnt) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern struct cgroup *bpf_cgroup_from_id(u64 cgid) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_task_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_dynptr_adjust(const struct bpf_dynptr *p, u64 start, u64 end) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_copy(struct bpf_dynptr *dst_ptr, u64 dst_off, struct bpf_dynptr *src_ptr, u64 src_off, u64 size) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb(struct __sk_buff *s, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb_meta(struct __sk_buff *skb_, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_xdp(struct xdp_md *x, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_dynptr_memset(struct bpf_dynptr *p, u64 offset, u64 size, u8 val) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern void *bpf_dynptr_slice(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern void *bpf_dynptr_slice_rdwr(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern struct kmem_cache *bpf_get_kmem_cache(u64 addr) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern int bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it, struct task_struct *task, u64 addr) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern struct bpf_key *bpf_lookup_system_key(u64 id) __weak __ksym;\nextern struct bpf_key *bpf_lookup_user_key(s32 serial, u64 flags) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_percpu_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern int bpf_probe_read_kernel_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_kernel_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_send_signal_task(struct task_struct *task, int sig, enum pid_type type, u64 value) __weak __ksym;\nextern __u64 *bpf_session_cookie(void *ctx) __weak __ksym;\nextern bool bpf_session_is_return(void *ctx) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_sock_ops_enable_tx_tstamp(struct bpf_sock_ops_kern *skops, u64 flags) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern void bpf_throw(u64 cookie) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void crash_kexec(struct pt_regs *regs) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __weak __ksym;\nextern void scx_bpf_destroy_dsq(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_insert___v2(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local(u64 dsq_id) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local___v2(u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move_vtime(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __weak __ksym;\nextern struct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern void scx_bpf_exit_bstr(s64 exit_code, char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern void scx_bpf_kick_cpu(s32 cpu, u64 flags) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern s32 scx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags, const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __weak __ksym;\nextern bool scx_bpf_sub_dispatch(u64 cgroup_id) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime) __weak __ksym;\nextern bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wmissing-declarations\"\n#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tACPI_BATTERY_ALARM_PRESENT = 0,\n\tACPI_BATTERY_XINFO_PRESENT = 1,\n\tACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY = 2,\n\tACPI_BATTERY_QUIRK_THINKPAD_MAH = 3,\n\tACPI_BATTERY_QUIRK_DEGRADED_FULL_CHARGE = 4,\n};\n\nenum {\n\tACPI_BUTTON_LID_INIT_IGNORE = 0,\n\tACPI_BUTTON_LID_INIT_OPEN = 1,\n\tACPI_BUTTON_LID_INIT_METHOD = 2,\n\tACPI_BUTTON_LID_INIT_DISABLED = 3,\n};\n\nenum {\n\tACPI_GENL_ATTR_UNSPEC = 0,\n\tACPI_GENL_ATTR_EVENT = 1,\n\t__ACPI_GENL_ATTR_MAX = 2,\n};\n\nenum {\n\tACPI_GENL_CMD_UNSPEC = 0,\n\tACPI_GENL_CMD_EVENT = 1,\n\t__ACPI_GENL_CMD_MAX = 2,\n};\n\nenum {\n\tACPI_REFCLASS_LOCAL = 0,\n\tACPI_REFCLASS_ARG = 1,\n\tACPI_REFCLASS_REFOF = 2,\n\tACPI_REFCLASS_INDEX = 3,\n\tACPI_REFCLASS_TABLE = 4,\n\tACPI_REFCLASS_NAME = 5,\n\tACPI_REFCLASS_DEBUG = 6,\n\tACPI_REFCLASS_MAX = 6,\n};\n\nenum {\n\tACPI_RSC_INITGET = 0,\n\tACPI_RSC_INITSET = 1,\n\tACPI_RSC_FLAGINIT = 2,\n\tACPI_RSC_1BITFLAG = 3,\n\tACPI_RSC_2BITFLAG = 4,\n\tACPI_RSC_3BITFLAG = 5,\n\tACPI_RSC_6BITFLAG = 6,\n\tACPI_RSC_ADDRESS = 7,\n\tACPI_RSC_BITMASK = 8,\n\tACPI_RSC_BITMASK16 = 9,\n\tACPI_RSC_COUNT = 10,\n\tACPI_RSC_COUNT16 = 11,\n\tACPI_RSC_COUNT_GPIO_PIN = 12,\n\tACPI_RSC_COUNT_GPIO_RES = 13,\n\tACPI_RSC_COUNT_GPIO_VEN = 14,\n\tACPI_RSC_COUNT_SERIAL_RES = 15,\n\tACPI_RSC_COUNT_SERIAL_VEN = 16,\n\tACPI_RSC_DATA8 = 17,\n\tACPI_RSC_EXIT_EQ = 18,\n\tACPI_RSC_EXIT_LE = 19,\n\tACPI_RSC_EXIT_NE = 20,\n\tACPI_RSC_LENGTH = 21,\n\tACPI_RSC_MOVE_GPIO_PIN = 22,\n\tACPI_RSC_MOVE_GPIO_RES = 23,\n\tACPI_RSC_MOVE_SERIAL_RES = 24,\n\tACPI_RSC_MOVE_SERIAL_VEN = 25,\n\tACPI_RSC_MOVE8 = 26,\n\tACPI_RSC_MOVE16 = 27,\n\tACPI_RSC_MOVE32 = 28,\n\tACPI_RSC_MOVE64 = 29,\n\tACPI_RSC_SET8 = 30,\n\tACPI_RSC_SOURCE = 31,\n\tACPI_RSC_SOURCEX = 32,\n};\n\nenum {\n\tACPI_RSD_TITLE = 0,\n\tACPI_RSD_1BITFLAG = 1,\n\tACPI_RSD_2BITFLAG = 2,\n\tACPI_RSD_3BITFLAG = 3,\n\tACPI_RSD_6BITFLAG = 4,\n\tACPI_RSD_ADDRESS = 5,\n\tACPI_RSD_DWORDLIST = 6,\n\tACPI_RSD_LITERAL = 7,\n\tACPI_RSD_LONGLIST = 8,\n\tACPI_RSD_SHORTLIST = 9,\n\tACPI_RSD_SHORTLISTX = 10,\n\tACPI_RSD_SOURCE = 11,\n\tACPI_RSD_STRING = 12,\n\tACPI_RSD_UINT8 = 13,\n\tACPI_RSD_UINT16 = 14,\n\tACPI_RSD_UINT32 = 15,\n\tACPI_RSD_UINT64 = 16,\n\tACPI_RSD_WORDLIST = 17,\n\tACPI_RSD_LABEL = 18,\n\tACPI_RSD_SOURCE_LABEL = 19,\n};\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAC_GRP_AUDIO_FUNCTION = 1,\n\tAC_GRP_MODEM_FUNCTION = 2,\n};\n\nenum {\n\tAC_JACK_LINE_OUT = 0,\n\tAC_JACK_SPEAKER = 1,\n\tAC_JACK_HP_OUT = 2,\n\tAC_JACK_CD = 3,\n\tAC_JACK_SPDIF_OUT = 4,\n\tAC_JACK_DIG_OTHER_OUT = 5,\n\tAC_JACK_MODEM_LINE_SIDE = 6,\n\tAC_JACK_MODEM_HAND_SIDE = 7,\n\tAC_JACK_LINE_IN = 8,\n\tAC_JACK_AUX = 9,\n\tAC_JACK_MIC_IN = 10,\n\tAC_JACK_TELEPHONY = 11,\n\tAC_JACK_SPDIF_IN = 12,\n\tAC_JACK_DIG_OTHER_IN = 13,\n\tAC_JACK_OTHER = 15,\n};\n\nenum {\n\tAC_JACK_LOC_EXTERNAL = 0,\n\tAC_JACK_LOC_INTERNAL = 16,\n\tAC_JACK_LOC_SEPARATE = 32,\n\tAC_JACK_LOC_OTHER = 48,\n};\n\nenum {\n\tAC_JACK_LOC_NONE = 0,\n\tAC_JACK_LOC_REAR = 1,\n\tAC_JACK_LOC_FRONT = 2,\n\tAC_JACK_LOC_LEFT = 3,\n\tAC_JACK_LOC_RIGHT = 4,\n\tAC_JACK_LOC_TOP = 5,\n\tAC_JACK_LOC_BOTTOM = 6,\n};\n\nenum {\n\tAC_JACK_LOC_REAR_PANEL = 7,\n\tAC_JACK_LOC_DRIVE_BAY = 8,\n\tAC_JACK_LOC_RISER = 23,\n\tAC_JACK_LOC_HDMI = 24,\n\tAC_JACK_LOC_ATAPI = 25,\n\tAC_JACK_LOC_MOBILE_IN = 55,\n\tAC_JACK_LOC_MOBILE_OUT = 56,\n};\n\nenum {\n\tAC_JACK_PORT_COMPLEX = 0,\n\tAC_JACK_PORT_NONE = 1,\n\tAC_JACK_PORT_FIXED = 2,\n\tAC_JACK_PORT_BOTH = 3,\n};\n\nenum {\n\tAC_WID_AUD_OUT = 0,\n\tAC_WID_AUD_IN = 1,\n\tAC_WID_AUD_MIX = 2,\n\tAC_WID_AUD_SEL = 3,\n\tAC_WID_PIN = 4,\n\tAC_WID_POWER = 5,\n\tAC_WID_VOL_KNB = 6,\n\tAC_WID_BEEP = 7,\n\tAC_WID_VENDOR = 15,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DMPS = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_CPD = 1048576,\n\tPORT_CMD_MPSP = 524288,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_CMD_CAP = 8126464,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_SUSPEND_PHYS = 33554432,\n\tAHCI_HFLAG_NO_SXS = 67108864,\n\tAHCI_HFLAG_43BIT_ONLY = 134217728,\n\tAHCI_HFLAG_INTEL_PCS_QUIRK = 268435456,\n\tAHCI_HFLAG_ATAPI_DMA_QUIRK = 536870912,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 15,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum {\n\tAMDV1PT_FMT_PR = 1ULL,\n\tAMDV1PT_FMT_D = 64ULL,\n\tAMDV1PT_FMT_NEXT_LEVEL = 3584ULL,\n\tAMDV1PT_FMT_OA = 4503599627366400ULL,\n\tAMDV1PT_FMT_FC = 1152921504606846976ULL,\n\tAMDV1PT_FMT_IR = 2305843009213693952ULL,\n\tAMDV1PT_FMT_IW = 4611686018427387904ULL,\n};\n\nenum {\n\tAML_FIELD_ACCESS_ANY = 0,\n\tAML_FIELD_ACCESS_BYTE = 1,\n\tAML_FIELD_ACCESS_WORD = 2,\n\tAML_FIELD_ACCESS_DWORD = 3,\n\tAML_FIELD_ACCESS_QWORD = 4,\n\tAML_FIELD_ACCESS_BUFFER = 5,\n};\n\nenum {\n\tAML_FIELD_ATTRIB_QUICK = 2,\n\tAML_FIELD_ATTRIB_SEND_RECEIVE = 4,\n\tAML_FIELD_ATTRIB_BYTE = 6,\n\tAML_FIELD_ATTRIB_WORD = 8,\n\tAML_FIELD_ATTRIB_BLOCK = 10,\n\tAML_FIELD_ATTRIB_BYTES = 11,\n\tAML_FIELD_ATTRIB_PROCESS_CALL = 12,\n\tAML_FIELD_ATTRIB_BLOCK_PROCESS_CALL = 13,\n\tAML_FIELD_ATTRIB_RAW_BYTES = 14,\n\tAML_FIELD_ATTRIB_RAW_PROCESS_BYTES = 15,\n};\n\nenum {\n\tAML_FIELD_UPDATE_PRESERVE = 0,\n\tAML_FIELD_UPDATE_WRITE_AS_ONES = 32,\n\tAML_FIELD_UPDATE_WRITE_AS_ZEROS = 64,\n};\n\nenum {\n\tARCH_LBR_BR_TYPE_JCC = 0,\n\tARCH_LBR_BR_TYPE_NEAR_IND_JMP = 1,\n\tARCH_LBR_BR_TYPE_NEAR_REL_JMP = 2,\n\tARCH_LBR_BR_TYPE_NEAR_IND_CALL = 3,\n\tARCH_LBR_BR_TYPE_NEAR_REL_CALL = 4,\n\tARCH_LBR_BR_TYPE_NEAR_RET = 5,\n\tARCH_LBR_BR_TYPE_KNOWN_MAX = 5,\n\tARCH_LBR_BR_TYPE_MAP_MAX = 16,\n};\n\nenum {\n\tARCH_UPROBE_FLAG_CAN_OPTIMIZE = 0,\n\tARCH_UPROBE_FLAG_OPTIMIZE_FAIL = 1,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = -2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = -2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_CDL = 24,\n\tATA_LOG_CDL_SIZE = 512,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SENSE_NCQ = 15,\n\tATA_LOG_SENSE_NCQ_SIZE = 1024,\n\tATA_LOG_CONCURRENT_POSITIONING_RANGES = 71,\n\tATA_LOG_SUPPORTED_CAPABILITIES = 3,\n\tATA_LOG_CURRENT_SETTINGS = 4,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSETFEATURES_CDL = 13,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tSETFEATURE_SENSE_DATA_SUCC_NCQ = 196,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum {\n\tATA_QUIRK_DIAGNOSTIC = 1,\n\tATA_QUIRK_NODMA = 2,\n\tATA_QUIRK_NONCQ = 4,\n\tATA_QUIRK_BROKEN_HPA = 8,\n\tATA_QUIRK_DISABLE = 16,\n\tATA_QUIRK_HPA_SIZE = 32,\n\tATA_QUIRK_IVB = 64,\n\tATA_QUIRK_STUCK_ERR = 128,\n\tATA_QUIRK_BRIDGE_OK = 256,\n\tATA_QUIRK_ATAPI_MOD16_DMA = 512,\n\tATA_QUIRK_FIRMWARE_WARN = 1024,\n\tATA_QUIRK_1_5_GBPS = 2048,\n\tATA_QUIRK_NOSETXFER = 4096,\n\tATA_QUIRK_BROKEN_FPDMA_AA = 8192,\n\tATA_QUIRK_DUMP_ID = 16384,\n\tATA_QUIRK_MAX_SEC_LBA48 = 32768,\n\tATA_QUIRK_ATAPI_DMADIR = 65536,\n\tATA_QUIRK_NO_NCQ_TRIM = 131072,\n\tATA_QUIRK_NOLPM = 262144,\n\tATA_QUIRK_WD_BROKEN_LPM = 524288,\n\tATA_QUIRK_ZERO_AFTER_TRIM = 1048576,\n\tATA_QUIRK_NO_DMA_LOG = 2097152,\n\tATA_QUIRK_NOTRIM = 4194304,\n\tATA_QUIRK_MAX_SEC = 8388608,\n\tATA_QUIRK_MAX_TRIM_128M = 16777216,\n\tATA_QUIRK_NO_NCQ_ON_ATI = 33554432,\n\tATA_QUIRK_NO_LPM_ON_ATI = 67108864,\n\tATA_QUIRK_NO_ID_DEV_LOG = 134217728,\n\tATA_QUIRK_NO_LOG_DIR = 268435456,\n\tATA_QUIRK_NO_FUA = 536870912,\n};\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = -2147483648,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAUTOFS_DEV_IOCTL_VERSION_CMD = 113,\n\tAUTOFS_DEV_IOCTL_PROTOVER_CMD = 114,\n\tAUTOFS_DEV_IOCTL_PROTOSUBVER_CMD = 115,\n\tAUTOFS_DEV_IOCTL_OPENMOUNT_CMD = 116,\n\tAUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD = 117,\n\tAUTOFS_DEV_IOCTL_READY_CMD = 118,\n\tAUTOFS_DEV_IOCTL_FAIL_CMD = 119,\n\tAUTOFS_DEV_IOCTL_SETPIPEFD_CMD = 120,\n\tAUTOFS_DEV_IOCTL_CATATONIC_CMD = 121,\n\tAUTOFS_DEV_IOCTL_TIMEOUT_CMD = 122,\n\tAUTOFS_DEV_IOCTL_REQUESTER_CMD = 123,\n\tAUTOFS_DEV_IOCTL_EXPIRE_CMD = 124,\n\tAUTOFS_DEV_IOCTL_ASKUMOUNT_CMD = 125,\n\tAUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD = 126,\n};\n\nenum {\n\tAUTOFS_IOC_EXPIRE_MULTI_CMD = 102,\n\tAUTOFS_IOC_PROTOSUBVER_CMD = 103,\n\tAUTOFS_IOC_ASKUMOUNT_CMD = 112,\n};\n\nenum {\n\tAUTOFS_IOC_READY_CMD = 96,\n\tAUTOFS_IOC_FAIL_CMD = 97,\n\tAUTOFS_IOC_CATATONIC_CMD = 98,\n\tAUTOFS_IOC_PROTOVER_CMD = 99,\n\tAUTOFS_IOC_SETTIMEOUT_CMD = 100,\n\tAUTOFS_IOC_EXPIRE_CMD = 101,\n};\n\nenum {\n\tAUTOP_INVALID = 0,\n\tAUTOP_HDD = 1,\n\tAUTOP_SSD_QD1 = 2,\n\tAUTOP_SSD_DFL = 3,\n\tAUTOP_SSD_FAST = 4,\n};\n\nenum {\n\tAUTO_PIN_LINE_OUT = 0,\n\tAUTO_PIN_SPEAKER_OUT = 1,\n\tAUTO_PIN_HP_OUT = 2,\n};\n\nenum {\n\tAUTO_PIN_MIC = 0,\n\tAUTO_PIN_LINE_IN = 1,\n\tAUTO_PIN_CD = 2,\n\tAUTO_PIN_AUX = 3,\n\tAUTO_PIN_LAST = 4,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tAZX_DRIVER_ICH = 0,\n\tAZX_DRIVER_PCH = 1,\n\tAZX_DRIVER_SCH = 2,\n\tAZX_DRIVER_SKL = 3,\n\tAZX_DRIVER_HDMI = 4,\n\tAZX_DRIVER_ATI = 5,\n\tAZX_DRIVER_ATIHDMI = 6,\n\tAZX_DRIVER_ATIHDMI_NS = 7,\n\tAZX_DRIVER_GFHDMI = 8,\n\tAZX_DRIVER_VIA = 9,\n\tAZX_DRIVER_SIS = 10,\n\tAZX_DRIVER_ULI = 11,\n\tAZX_DRIVER_NVIDIA = 12,\n\tAZX_DRIVER_TERA = 13,\n\tAZX_DRIVER_CTX = 14,\n\tAZX_DRIVER_CTHDA = 15,\n\tAZX_DRIVER_CMEDIA = 16,\n\tAZX_DRIVER_ZHAOXIN = 17,\n\tAZX_DRIVER_ZHAOXINHDMI = 18,\n\tAZX_DRIVER_LOONGSON = 19,\n\tAZX_DRIVER_GENERIC = 20,\n\tAZX_NUM_DRIVERS = 21,\n};\n\nenum {\n\tAZX_SNOOP_TYPE_NONE = 0,\n\tAZX_SNOOP_TYPE_SCH = 1,\n\tAZX_SNOOP_TYPE_ATI = 2,\n\tAZX_SNOOP_TYPE_NVIDIA = 3,\n};\n\nenum {\n\tAudit_equal = 0,\n\tAudit_not_equal = 1,\n\tAudit_bitmask = 2,\n\tAudit_bittest = 3,\n\tAudit_lt = 4,\n\tAudit_gt = 5,\n\tAudit_le = 6,\n\tAudit_ge = 7,\n\tAudit_bad = 8,\n};\n\nenum {\n\tB28_DPT_INI = 3584,\n\tB28_DPT_VAL = 3588,\n\tB28_DPT_CTRL = 3592,\n\tB28_DPT_TST = 3594,\n};\n\nenum {\n\tB28_Y2_SMB_CONFIG = 3648,\n\tB28_Y2_SMB_CSD_REG = 3652,\n\tB28_Y2_ASF_IRQ_V_BASE = 3680,\n\tB28_Y2_ASF_STAT_CMD = 3688,\n\tB28_Y2_ASF_HOST_COM = 3692,\n\tB28_Y2_DATA_REG_1 = 3696,\n\tB28_Y2_DATA_REG_2 = 3700,\n\tB28_Y2_DATA_REG_3 = 3704,\n\tB28_Y2_DATA_REG_4 = 3708,\n};\n\nenum {\n\tB6_EXT_REG = 768,\n\tB7_CFG_SPC = 896,\n\tB8_RQ1_REGS = 1024,\n\tB8_RQ2_REGS = 1152,\n\tB8_TS1_REGS = 1536,\n\tB8_TA1_REGS = 1664,\n\tB8_TS2_REGS = 1792,\n\tB8_TA2_REGS = 1920,\n\tB16_RAM_REGS = 2048,\n};\n\nenum {\n\tB8_Q_REGS = 1024,\n\tQ_D = 0,\n\tQ_VLAN = 32,\n\tQ_DONE = 36,\n\tQ_AC_L = 40,\n\tQ_AC_H = 44,\n\tQ_BC = 48,\n\tQ_CSR = 52,\n\tQ_TEST = 56,\n\tQ_WM = 64,\n\tQ_AL = 66,\n\tQ_RSP = 68,\n\tQ_RSL = 70,\n\tQ_RP = 72,\n\tQ_RL = 74,\n\tQ_WP = 76,\n\tQ_WSP = 77,\n\tQ_WL = 78,\n\tQ_WSL = 79,\n};\n\nenum {\n\tBASE_GMAC_1 = 10240,\n\tBASE_GMAC_2 = 14336,\n};\n\nenum {\n\tBDX_PCI_UNCORE_HA = 0,\n\tBDX_PCI_UNCORE_IMC = 1,\n\tBDX_PCI_UNCORE_IRP = 2,\n\tBDX_PCI_UNCORE_QPI = 3,\n\tBDX_PCI_UNCORE_R2PCIE = 4,\n\tBDX_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLINK_42MS = 0,\n\tBLINK_84MS = 1,\n\tBLINK_170MS = 2,\n\tBLINK_340MS = 3,\n\tBLINK_670MS = 4,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nenum {\n\tBMU_IDLE = -2147483648,\n\tBMU_RX_TCP_PKT = 1073741824,\n\tBMU_RX_IP_PKT = 536870912,\n\tBMU_ENA_RX_RSS_HASH = 32768,\n\tBMU_DIS_RX_RSS_HASH = 16384,\n\tBMU_ENA_RX_CHKSUM = 8192,\n\tBMU_DIS_RX_CHKSUM = 4096,\n\tBMU_CLR_IRQ_PAR = 2048,\n\tBMU_CLR_IRQ_TCP = 2048,\n\tBMU_CLR_IRQ_CHK = 1024,\n\tBMU_STOP = 512,\n\tBMU_START = 256,\n\tBMU_FIFO_OP_ON = 128,\n\tBMU_FIFO_OP_OFF = 64,\n\tBMU_FIFO_ENA = 32,\n\tBMU_FIFO_RST = 16,\n\tBMU_OP_ON = 8,\n\tBMU_OP_OFF = 4,\n\tBMU_RST_CLR = 2,\n\tBMU_RST_SET = 1,\n\tBMU_CLR_RESET = 22,\n\tBMU_OPER_INIT = 3368,\n\tBMU_WM_DEFAULT = 1536,\n\tBMU_WM_PEX = 128,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_CURRENT_NETNS = -1,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 38,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBPF_XFRM_STATE_OPTS_SZ = 36,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tBTS_STATE_STOPPED = 0,\n\tBTS_STATE_INACTIVE = 1,\n\tBTS_STATE_ACTIVE = 2,\n};\n\nenum {\n\tBlktrace_setup = 1,\n\tBlktrace_running = 2,\n\tBlktrace_stopped = 3,\n};\n\nenum {\n\tCACHE_VALID = 0,\n\tCACHE_NEGATIVE = 1,\n\tCACHE_PENDING = 2,\n\tCACHE_CLEANED = 3,\n};\n\nenum {\n\tCARDBUS_TYPE_DEFAULT = -1,\n\tCARDBUS_TYPE_TI = 0,\n\tCARDBUS_TYPE_TI113X = 1,\n\tCARDBUS_TYPE_TI12XX = 2,\n\tCARDBUS_TYPE_TI1250 = 3,\n\tCARDBUS_TYPE_RICOH = 4,\n\tCARDBUS_TYPE_TOPIC95 = 5,\n\tCARDBUS_TYPE_TOPIC97 = 6,\n\tCARDBUS_TYPE_O2MICRO = 7,\n\tCARDBUS_TYPE_ENE = 8,\n};\n\nenum {\n\tCFG_CHIP_R_MSK = 240,\n\tCFG_DIS_M2_CLK = 2,\n\tCFG_SNG_MAC = 1,\n};\n\nenum {\n\tCFG_LED_MODE_MSK = 28,\n\tCFG_LINK_2_AVAIL = 2,\n\tCFG_LINK_1_AVAIL = 1,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGROUPSTATS_CMD_ATTR_UNSPEC = 0,\n\tCGROUPSTATS_CMD_ATTR_FD = 1,\n\t__CGROUPSTATS_CMD_ATTR_MAX = 2,\n};\n\nenum {\n\tCGROUPSTATS_CMD_UNSPEC = 3,\n\tCGROUPSTATS_CMD_GET = 4,\n\tCGROUPSTATS_CMD_NEW = 5,\n\t__CGROUPSTATS_CMD_MAX = 6,\n};\n\nenum {\n\tCGROUPSTATS_TYPE_UNSPEC = 0,\n\tCGROUPSTATS_TYPE_CGROUP_STATS = 1,\n\t__CGROUPSTATS_TYPE_MAX = 2,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCHIP_ID_YUKON_XL = 179,\n\tCHIP_ID_YUKON_EC_U = 180,\n\tCHIP_ID_YUKON_EX = 181,\n\tCHIP_ID_YUKON_EC = 182,\n\tCHIP_ID_YUKON_FE = 183,\n\tCHIP_ID_YUKON_FE_P = 184,\n\tCHIP_ID_YUKON_SUPR = 185,\n\tCHIP_ID_YUKON_UL_2 = 186,\n\tCHIP_ID_YUKON_OPT = 188,\n\tCHIP_ID_YUKON_PRM = 189,\n\tCHIP_ID_YUKON_OP_2 = 190,\n};\n\nenum {\n\tCLEAR_RESIDUALS = 0,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCM_ASL_WLAN = 0,\n\tCM_ASL_BLUETOOTH = 1,\n\tCM_ASL_IRDA = 2,\n\tCM_ASL_1394 = 3,\n\tCM_ASL_CAMERA = 4,\n\tCM_ASL_TV = 5,\n\tCM_ASL_GPS = 6,\n\tCM_ASL_DVDROM = 7,\n\tCM_ASL_DISPLAYSWITCH = 8,\n\tCM_ASL_PANELBRIGHT = 9,\n\tCM_ASL_BIOSFLASH = 10,\n\tCM_ASL_ACPIFLASH = 11,\n\tCM_ASL_CPUFV = 12,\n\tCM_ASL_CPUTEMPERATURE = 13,\n\tCM_ASL_FANCPU = 14,\n\tCM_ASL_FANCHASSIS = 15,\n\tCM_ASL_USBPORT1 = 16,\n\tCM_ASL_USBPORT2 = 17,\n\tCM_ASL_USBPORT3 = 18,\n\tCM_ASL_MODEM = 19,\n\tCM_ASL_CARDREADER = 20,\n\tCM_ASL_3G = 21,\n\tCM_ASL_WIMAX = 22,\n\tCM_ASL_HWCF = 23,\n\tCM_ASL_LID = 24,\n\tCM_ASL_TYPE = 25,\n\tCM_ASL_PANELPOWER = 26,\n\tCM_ASL_TPD = 27,\n};\n\nenum {\n\tCONNSECMARK_SAVE = 1,\n\tCONNSECMARK_RESTORE = 2,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCOST_CTRL = 0,\n\tCOST_MODEL = 1,\n\tNR_COST_CTRL_PARAMS = 2,\n};\n\nenum {\n\tCPU_WDOG = 3656,\n\tCPU_CNTR = 3660,\n\tCPU_TIM = 3664,\n\tCPU_AHB_ADDR = 3668,\n\tCPU_AHB_WDATA = 3672,\n\tCPU_AHB_RDATA = 3676,\n\tHCU_MAP_BASE = 3680,\n\tCPU_AHB_CTRL = 3684,\n\tHCU_CCSR = 3688,\n\tHCU_HCSR = 3692,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 1000,\n\tCRNG_RESEED_INTERVAL = 60000,\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\t__CRYPTOA_MAX = 3,\n};\n\nenum {\n\tCRYPTO_AUTHENC_KEYA_UNSPEC = 0,\n\tCRYPTO_AUTHENC_KEYA_PARAM = 1,\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tD0TIM = 128,\n\tD1TIM = 132,\n\tPM = 7,\n\tMDM = 768,\n\tUDM = 458752,\n\tPPE = 1073741824,\n\tUSD = -2147483648,\n};\n\nenum {\n\tDAD_PROCESS = 0,\n\tDAD_BEGIN = 1,\n\tDAD_ABORT = 2,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEBUG_FENCE_IDLE = 0,\n\tDEBUG_FENCE_NOTIFY = 1,\n};\n\nenum {\n\tDELL_INSPIRON_7375 = 0,\n\tDELL_LATITUDE_5495 = 1,\n\tLENOVO_IDEAPAD_330S_15ARR = 2,\n};\n\nenum {\n\tDESC_TSS = 9,\n\tDESC_LDT = 2,\n\tDESCTYPE_S = 16,\n};\n\nenum {\n\tDEVCONF_FORWARDING = 0,\n\tDEVCONF_HOPLIMIT = 1,\n\tDEVCONF_MTU6 = 2,\n\tDEVCONF_ACCEPT_RA = 3,\n\tDEVCONF_ACCEPT_REDIRECTS = 4,\n\tDEVCONF_AUTOCONF = 5,\n\tDEVCONF_DAD_TRANSMITS = 6,\n\tDEVCONF_RTR_SOLICITS = 7,\n\tDEVCONF_RTR_SOLICIT_INTERVAL = 8,\n\tDEVCONF_RTR_SOLICIT_DELAY = 9,\n\tDEVCONF_USE_TEMPADDR = 10,\n\tDEVCONF_TEMP_VALID_LFT = 11,\n\tDEVCONF_TEMP_PREFERED_LFT = 12,\n\tDEVCONF_REGEN_MAX_RETRY = 13,\n\tDEVCONF_MAX_DESYNC_FACTOR = 14,\n\tDEVCONF_MAX_ADDRESSES = 15,\n\tDEVCONF_FORCE_MLD_VERSION = 16,\n\tDEVCONF_ACCEPT_RA_DEFRTR = 17,\n\tDEVCONF_ACCEPT_RA_PINFO = 18,\n\tDEVCONF_ACCEPT_RA_RTR_PREF = 19,\n\tDEVCONF_RTR_PROBE_INTERVAL = 20,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN = 21,\n\tDEVCONF_PROXY_NDP = 22,\n\tDEVCONF_OPTIMISTIC_DAD = 23,\n\tDEVCONF_ACCEPT_SOURCE_ROUTE = 24,\n\tDEVCONF_MC_FORWARDING = 25,\n\tDEVCONF_DISABLE_IPV6 = 26,\n\tDEVCONF_ACCEPT_DAD = 27,\n\tDEVCONF_FORCE_TLLAO = 28,\n\tDEVCONF_NDISC_NOTIFY = 29,\n\tDEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL = 30,\n\tDEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL = 31,\n\tDEVCONF_SUPPRESS_FRAG_NDISC = 32,\n\tDEVCONF_ACCEPT_RA_FROM_LOCAL = 33,\n\tDEVCONF_USE_OPTIMISTIC = 34,\n\tDEVCONF_ACCEPT_RA_MTU = 35,\n\tDEVCONF_STABLE_SECRET = 36,\n\tDEVCONF_USE_OIF_ADDRS_ONLY = 37,\n\tDEVCONF_ACCEPT_RA_MIN_HOP_LIMIT = 38,\n\tDEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 39,\n\tDEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 40,\n\tDEVCONF_DROP_UNSOLICITED_NA = 41,\n\tDEVCONF_KEEP_ADDR_ON_DOWN = 42,\n\tDEVCONF_RTR_SOLICIT_MAX_INTERVAL = 43,\n\tDEVCONF_SEG6_ENABLED = 44,\n\tDEVCONF_SEG6_REQUIRE_HMAC = 45,\n\tDEVCONF_ENHANCED_DAD = 46,\n\tDEVCONF_ADDR_GEN_MODE = 47,\n\tDEVCONF_DISABLE_POLICY = 48,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN = 49,\n\tDEVCONF_NDISC_TCLASS = 50,\n\tDEVCONF_RPL_SEG_ENABLED = 51,\n\tDEVCONF_RA_DEFRTR_METRIC = 52,\n\tDEVCONF_IOAM6_ENABLED = 53,\n\tDEVCONF_IOAM6_ID = 54,\n\tDEVCONF_IOAM6_ID_WIDE = 55,\n\tDEVCONF_NDISC_EVICT_NOCARRIER = 56,\n\tDEVCONF_ACCEPT_UNTRACKED_NA = 57,\n\tDEVCONF_ACCEPT_RA_MIN_LFT = 58,\n\tDEVCONF_FORCE_FORWARDING = 59,\n\tDEVCONF_MAX = 60,\n};\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISABLE_ASL_WLAN = 1,\n\tDISABLE_ASL_BLUETOOTH = 2,\n\tDISABLE_ASL_IRDA = 4,\n\tDISABLE_ASL_CAMERA = 8,\n\tDISABLE_ASL_TV = 16,\n\tDISABLE_ASL_GPS = 32,\n\tDISABLE_ASL_DISPLAYSWITCH = 64,\n\tDISABLE_ASL_MODEM = 128,\n\tDISABLE_ASL_CARDREADER = 256,\n\tDISABLE_ASL_3G = 512,\n\tDISABLE_ASL_WIMAX = 1024,\n\tDISABLE_ASL_HWCF = 2048,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDMA_DSCR_HOST = 0,\n\tDMA_DSCR_DEVICE = 1,\n\tDMA_DSCR_CTRL = 2,\n\tDMA_DSCR_NUM = 3,\n};\n\nenum {\n\tDMA_FENCE_WORK_IMM = 4,\n};\n\nenum {\n\tDM_IO_ACCOUNTED = 0,\n\tDM_IO_WAS_SPLIT = 1,\n\tDM_IO_BLK_STAT = 2,\n};\n\nenum {\n\tDM_TIO_INSIDE_DM_IO = 0,\n\tDM_TIO_IS_DUPLICATE_BIO = 1,\n};\n\nenum {\n\tDM_VERSION_CMD = 0,\n\tDM_REMOVE_ALL_CMD = 1,\n\tDM_LIST_DEVICES_CMD = 2,\n\tDM_DEV_CREATE_CMD = 3,\n\tDM_DEV_REMOVE_CMD = 4,\n\tDM_DEV_RENAME_CMD = 5,\n\tDM_DEV_SUSPEND_CMD = 6,\n\tDM_DEV_STATUS_CMD = 7,\n\tDM_DEV_WAIT_CMD = 8,\n\tDM_TABLE_LOAD_CMD = 9,\n\tDM_TABLE_CLEAR_CMD = 10,\n\tDM_TABLE_DEPS_CMD = 11,\n\tDM_TABLE_STATUS_CMD = 12,\n\tDM_LIST_VERSIONS_CMD = 13,\n\tDM_TARGET_MSG_CMD = 14,\n\tDM_DEV_SET_GEOMETRY_CMD = 15,\n\tDM_DEV_ARM_POLL_CMD = 16,\n\tDM_GET_TARGET_VERSION_CMD = 17,\n\tDM_MPATH_PROBE_PATHS_CMD = 18,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDPT_START = 2,\n\tDPT_STOP = 1,\n};\n\nenum {\n\tDQF_INFO_DIRTY_B = 17,\n};\n\nenum {\n\tDQF_ROOT_SQUASH_B = 0,\n\tDQF_SYS_FILE_B = 16,\n\tDQF_PRIVATE = 17,\n};\n\nenum {\n\tDQST_LOOKUPS = 0,\n\tDQST_DROPS = 1,\n\tDQST_READS = 2,\n\tDQST_WRITES = 3,\n\tDQST_CACHE_HITS = 4,\n\tDQST_ALLOC_DQUOTS = 5,\n\tDQST_FREE_DQUOTS = 6,\n\tDQST_SYNCS = 7,\n\t_DQST_DQSTAT_LAST = 8,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tEC_FLAGS_QUERY_ENABLED = 0,\n\tEC_FLAGS_EVENT_HANDLER_INSTALLED = 1,\n\tEC_FLAGS_EC_HANDLER_INSTALLED = 2,\n\tEC_FLAGS_EC_REG_CALLED = 3,\n\tEC_FLAGS_QUERY_METHODS_INSTALLED = 4,\n\tEC_FLAGS_STARTED = 5,\n\tEC_FLAGS_STOPPED = 6,\n\tEC_FLAGS_EVENTS_MASKED = 7,\n};\n\nenum {\n\tEMULATE = 0,\n\tXONLY = 1,\n\tNONE = 2,\n};\n\nenum {\n\tENABLE_DMC_WL_DISABLED = 0,\n\tENABLE_DMC_WL_ENABLED = 1,\n\tENABLE_DMC_WL_ANY_REGISTER = 2,\n\tENABLE_DMC_WL_ALWAYS_LOCKED = 3,\n\tENABLE_DMC_WL_MAX = 4,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_CODE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_CODE_OK = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE_OPEN = 2,\n\tETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT = 3,\n\tETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT = 4,\n\tETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH = 5,\n\tETHTOOL_A_CABLE_RESULT_CODE_NOISE = 6,\n\tETHTOOL_A_CABLE_RESULT_CODE_RESOLUTION_NOT_POSSIBLE = 7,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENTFS_SAVE_MODE = 65536,\n\tEVENTFS_SAVE_UID = 131072,\n\tEVENTFS_SAVE_GID = 262144,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_DISABLED = 32,\n\tEVENT_FILE_FL_TRIGGER_MODE = 64,\n\tEVENT_FILE_FL_TRIGGER_COND = 128,\n\tEVENT_FILE_FL_PID_FILTER = 256,\n\tEVENT_FILE_FL_WAS_ENABLED = 512,\n\tEVENT_FILE_FL_FREED = 1024,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEVENT_TRIGGER_FL_PROBE = 1,\n\tEVENT_TRIGGER_FL_COUNT = 2,\n};\n\nenum {\n\tEXPECT_SWBP = 0,\n\tEXPECT_CALL = 1,\n};\n\nenum {\n\tEXT4_FC_REASON_XATTR = 0,\n\tEXT4_FC_REASON_CROSS_RENAME = 1,\n\tEXT4_FC_REASON_JOURNAL_FLAG_CHANGE = 2,\n\tEXT4_FC_REASON_NOMEM = 3,\n\tEXT4_FC_REASON_SWAP_BOOT = 4,\n\tEXT4_FC_REASON_RESIZE = 5,\n\tEXT4_FC_REASON_RENAME_DIR = 6,\n\tEXT4_FC_REASON_FALLOC_RANGE = 7,\n\tEXT4_FC_REASON_INODE_JOURNAL_DATA = 8,\n\tEXT4_FC_REASON_ENCRYPTED_FILENAME = 9,\n\tEXT4_FC_REASON_MIGRATE = 10,\n\tEXT4_FC_REASON_VERITY = 11,\n\tEXT4_FC_REASON_MOVE_EXT = 12,\n\tEXT4_FC_REASON_MAX = 13,\n};\n\nenum {\n\tEXT4_FC_STATUS_OK = 0,\n\tEXT4_FC_STATUS_INELIGIBLE = 1,\n\tEXT4_FC_STATUS_SKIPPED = 2,\n\tEXT4_FC_STATUS_FAILED = 3,\n};\n\nenum {\n\tEXT4_FLAGS_RESIZING = 0,\n\tEXT4_FLAGS_SHUTDOWN = 1,\n\tEXT4_FLAGS_BDEV_IS_DAX = 2,\n\tEXT4_FLAGS_EMERGENCY_RO = 3,\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nenum {\n\tEXT4_MF_MNTDIR_SAMPLED = 0,\n\tEXT4_MF_FC_INELIGIBLE = 1,\n\tEXT4_MF_JOURNAL_DESTROY = 2,\n};\n\nenum {\n\tEXT4_STATE_NEW = 0,\n\tEXT4_STATE_XATTR = 1,\n\tEXT4_STATE_NO_EXPAND = 2,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 3,\n\tEXT4_STATE_EXT_MIGRATE = 4,\n\tEXT4_STATE_NEWENTRY = 5,\n\tEXT4_STATE_MAY_INLINE_DATA = 6,\n\tEXT4_STATE_EXT_PRECACHED = 7,\n\tEXT4_STATE_LUSTRE_EA_INODE = 8,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 9,\n\tEXT4_STATE_FC_COMMITTING = 10,\n\tEXT4_STATE_FC_FLUSHING_DATA = 11,\n\tEXT4_STATE_ORPHAN_FILE = 12,\n};\n\nenum {\n\tEXTRA_REG_NHMEX_M_FILTER = 0,\n\tEXTRA_REG_NHMEX_M_DSP = 1,\n\tEXTRA_REG_NHMEX_M_ISS = 2,\n\tEXTRA_REG_NHMEX_M_MAP = 3,\n\tEXTRA_REG_NHMEX_M_MSC_THR = 4,\n\tEXTRA_REG_NHMEX_M_PGT = 5,\n\tEXTRA_REG_NHMEX_M_PLD = 6,\n\tEXTRA_REG_NHMEX_M_ZDP_CTL_FVC = 7,\n};\n\nenum {\n\tEnabled = 0,\n\tMagic = 1,\n};\n\nenum {\n\tFATTR4_CLONE_BLKSIZE = 77,\n\tFATTR4_SPACE_FREED = 78,\n\tFATTR4_CHANGE_ATTR_TYPE = 79,\n\tFATTR4_SEC_LABEL = 80,\n};\n\nenum {\n\tFATTR4_DIR_NOTIF_DELAY = 56,\n\tFATTR4_DIRENT_NOTIF_DELAY = 57,\n\tFATTR4_DACL = 58,\n\tFATTR4_SACL = 59,\n\tFATTR4_CHANGE_POLICY = 60,\n\tFATTR4_FS_STATUS = 61,\n\tFATTR4_FS_LAYOUT_TYPES = 62,\n\tFATTR4_LAYOUT_HINT = 63,\n\tFATTR4_LAYOUT_TYPES = 64,\n\tFATTR4_LAYOUT_BLKSIZE = 65,\n\tFATTR4_LAYOUT_ALIGNMENT = 66,\n\tFATTR4_FS_LOCATIONS_INFO = 67,\n\tFATTR4_MDSTHRESHOLD = 68,\n\tFATTR4_RETENTION_GET = 69,\n\tFATTR4_RETENTION_SET = 70,\n\tFATTR4_RETENTEVT_GET = 71,\n\tFATTR4_RETENTEVT_SET = 72,\n\tFATTR4_RETENTION_HOLD = 73,\n\tFATTR4_MODE_SET_MASKED = 74,\n\tFATTR4_SUPPATTR_EXCLCREAT = 75,\n\tFATTR4_FS_CHARSET_CAP = 76,\n};\n\nenum {\n\tFATTR4_MODE_UMASK = 81,\n};\n\nenum {\n\tFATTR4_OPEN_ARGUMENTS = 86,\n};\n\nenum {\n\tFATTR4_SUPPORTED_ATTRS = 0,\n\tFATTR4_TYPE = 1,\n\tFATTR4_FH_EXPIRE_TYPE = 2,\n\tFATTR4_CHANGE = 3,\n\tFATTR4_SIZE = 4,\n\tFATTR4_LINK_SUPPORT = 5,\n\tFATTR4_SYMLINK_SUPPORT = 6,\n\tFATTR4_NAMED_ATTR = 7,\n\tFATTR4_FSID = 8,\n\tFATTR4_UNIQUE_HANDLES = 9,\n\tFATTR4_LEASE_TIME = 10,\n\tFATTR4_RDATTR_ERROR = 11,\n\tFATTR4_ACL = 12,\n\tFATTR4_ACLSUPPORT = 13,\n\tFATTR4_ARCHIVE = 14,\n\tFATTR4_CANSETTIME = 15,\n\tFATTR4_CASE_INSENSITIVE = 16,\n\tFATTR4_CASE_PRESERVING = 17,\n\tFATTR4_CHOWN_RESTRICTED = 18,\n\tFATTR4_FILEHANDLE = 19,\n\tFATTR4_FILEID = 20,\n\tFATTR4_FILES_AVAIL = 21,\n\tFATTR4_FILES_FREE = 22,\n\tFATTR4_FILES_TOTAL = 23,\n\tFATTR4_FS_LOCATIONS = 24,\n\tFATTR4_HIDDEN = 25,\n\tFATTR4_HOMOGENEOUS = 26,\n\tFATTR4_MAXFILESIZE = 27,\n\tFATTR4_MAXLINK = 28,\n\tFATTR4_MAXNAME = 29,\n\tFATTR4_MAXREAD = 30,\n\tFATTR4_MAXWRITE = 31,\n\tFATTR4_MIMETYPE = 32,\n\tFATTR4_MODE = 33,\n\tFATTR4_NO_TRUNC = 34,\n\tFATTR4_NUMLINKS = 35,\n\tFATTR4_OWNER = 36,\n\tFATTR4_OWNER_GROUP = 37,\n\tFATTR4_QUOTA_AVAIL_HARD = 38,\n\tFATTR4_QUOTA_AVAIL_SOFT = 39,\n\tFATTR4_QUOTA_USED = 40,\n\tFATTR4_RAWDEV = 41,\n\tFATTR4_SPACE_AVAIL = 42,\n\tFATTR4_SPACE_FREE = 43,\n\tFATTR4_SPACE_TOTAL = 44,\n\tFATTR4_SPACE_USED = 45,\n\tFATTR4_SYSTEM = 46,\n\tFATTR4_TIME_ACCESS = 47,\n\tFATTR4_TIME_ACCESS_SET = 48,\n\tFATTR4_TIME_BACKUP = 49,\n\tFATTR4_TIME_CREATE = 50,\n\tFATTR4_TIME_DELTA = 51,\n\tFATTR4_TIME_METADATA = 52,\n\tFATTR4_TIME_MODIFY = 53,\n\tFATTR4_TIME_MODIFY_SET = 54,\n\tFATTR4_MOUNTED_ON_FILEID = 55,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_ACCESS = 84,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_MODIFY = 85,\n};\n\nenum {\n\tFATTR4_XATTR_SUPPORT = 82,\n};\n\nenum {\n\tFIB6_NO_SERNUM_CHANGE = 0,\n};\n\nenum {\n\tFILEID_HIGH_OFF = 0,\n\tFILEID_LOW_OFF = 1,\n\tFILE_I_TYPE_OFF = 2,\n\tEMBED_FH_OFF = 3,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_RDYN_STRING = 3,\n\tFILTER_PTR_STRING = 4,\n\tFILTER_TRACE_FN = 5,\n\tFILTER_CPUMASK = 6,\n\tFILTER_COMM = 7,\n\tFILTER_CPU = 8,\n\tFILTER_STACKTRACE = 9,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_MISSING_BRACE_OPEN = 5,\n\tFILT_ERR_MISSING_BRACE_CLOSE = 6,\n\tFILT_ERR_OPERAND_TOO_LONG = 7,\n\tFILT_ERR_EXPECT_STRING = 8,\n\tFILT_ERR_EXPECT_DIGIT = 9,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 10,\n\tFILT_ERR_FIELD_NOT_FOUND = 11,\n\tFILT_ERR_ILLEGAL_INTVAL = 12,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 13,\n\tFILT_ERR_TOO_MANY_PREDS = 14,\n\tFILT_ERR_INVALID_FILTER = 15,\n\tFILT_ERR_INVALID_CPULIST = 16,\n\tFILT_ERR_IP_FIELD_ONLY = 17,\n\tFILT_ERR_INVALID_VALUE = 18,\n\tFILT_ERR_NO_FUNCTION = 19,\n\tFILT_ERR_ERRNO = 20,\n\tFILT_ERR_NO_FILTER = 21,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFORCE_CPU_RELOC = 1,\n\tFORCE_GTT_RELOC = 2,\n\tFORCE_GPU_RELOC = 3,\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\nenum {\n\tFRA_UNSPEC = 0,\n\tFRA_DST = 1,\n\tFRA_SRC = 2,\n\tFRA_IIFNAME = 3,\n\tFRA_GOTO = 4,\n\tFRA_UNUSED2 = 5,\n\tFRA_PRIORITY = 6,\n\tFRA_UNUSED3 = 7,\n\tFRA_UNUSED4 = 8,\n\tFRA_UNUSED5 = 9,\n\tFRA_FWMARK = 10,\n\tFRA_FLOW = 11,\n\tFRA_TUN_ID = 12,\n\tFRA_SUPPRESS_IFGROUP = 13,\n\tFRA_SUPPRESS_PREFIXLEN = 14,\n\tFRA_TABLE = 15,\n\tFRA_FWMASK = 16,\n\tFRA_OIFNAME = 17,\n\tFRA_PAD = 18,\n\tFRA_L3MDEV = 19,\n\tFRA_UID_RANGE = 20,\n\tFRA_PROTOCOL = 21,\n\tFRA_IP_PROTO = 22,\n\tFRA_SPORT_RANGE = 23,\n\tFRA_DPORT_RANGE = 24,\n\tFRA_DSCP = 25,\n\tFRA_FLOWLABEL = 26,\n\tFRA_FLOWLABEL_MASK = 27,\n\tFRA_SPORT_MASK = 28,\n\tFRA_DPORT_MASK = 29,\n\tFRA_DSCP_MASK = 30,\n\t__FRA_MAX = 31,\n};\n\nenum {\n\tFR_ACT_UNSPEC = 0,\n\tFR_ACT_TO_TBL = 1,\n\tFR_ACT_GOTO = 2,\n\tFR_ACT_NOP = 3,\n\tFR_ACT_RES3 = 4,\n\tFR_ACT_RES4 = 5,\n\tFR_ACT_BLACKHOLE = 6,\n\tFR_ACT_UNREACHABLE = 7,\n\tFR_ACT_PROHIBIT = 8,\n\t__FR_ACT_MAX = 9,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tF_TX_CHK_AUTO_OFF = -2147483648,\n\tF_TX_CHK_AUTO_ON = 1073741824,\n\tF_M_RX_RAM_DIS = 16777216,\n};\n\nenum {\n\tGATE_INTERRUPT = 14,\n\tGATE_TRAP = 15,\n\tGATE_CALL = 12,\n\tGATE_TASK = 5,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGLB_GPIO_CLK_DEB_ENA = -2147483648,\n\tGLB_GPIO_CLK_DBG_MSK = 1006632960,\n\tGLB_GPIO_INT_RST_D3_DIS = 32768,\n\tGLB_GPIO_LED_PAD_SPEED_UP = 16384,\n\tGLB_GPIO_STAT_RACE_DIS = 8192,\n\tGLB_GPIO_TEST_SEL_MSK = 6144,\n\tGLB_GPIO_TEST_SEL_BASE = 2048,\n\tGLB_GPIO_RAND_ENA = 1024,\n\tGLB_GPIO_RAND_BIT_1 = 512,\n};\n\nenum {\n\tGMAC_CTRL = 3840,\n\tGPHY_CTRL = 3844,\n\tGMAC_IRQ_SRC = 3848,\n\tGMAC_IRQ_MSK = 3852,\n\tGMAC_LINK_CTRL = 3856,\n\tWOL_CTRL_STAT = 3872,\n\tWOL_MATCH_CTL = 3874,\n\tWOL_MATCH_RES = 3875,\n\tWOL_MAC_ADDR = 3876,\n\tWOL_PATT_RPTR = 3884,\n\tWOL_PATT_LEN_LO = 3888,\n\tWOL_PATT_LEN_HI = 3892,\n\tWOL_PATT_CNT_0 = 3896,\n\tWOL_PATT_CNT_4 = 3900,\n};\n\nenum {\n\tGMAC_TI_ST_VAL = 3604,\n\tGMAC_TI_ST_CTRL = 3608,\n\tGMAC_TI_ST_TST = 3610,\n};\n\nenum {\n\tGMC_SET_RST = 32768,\n\tGMC_SEC_RST_OFF = 16384,\n\tGMC_BYP_MACSECRX_ON = 8192,\n\tGMC_BYP_MACSECRX_OFF = 4096,\n\tGMC_BYP_MACSECTX_ON = 2048,\n\tGMC_BYP_MACSECTX_OFF = 1024,\n\tGMC_BYP_RETR_ON = 512,\n\tGMC_BYP_RETR_OFF = 256,\n\tGMC_H_BURST_ON = 128,\n\tGMC_H_BURST_OFF = 64,\n\tGMC_F_LOOPB_ON = 32,\n\tGMC_F_LOOPB_OFF = 16,\n\tGMC_PAUSE_ON = 8,\n\tGMC_PAUSE_OFF = 4,\n\tGMC_RST_CLR = 2,\n\tGMC_RST_SET = 1,\n};\n\nenum {\n\tGMLC_RST_CLR = 2,\n\tGMLC_RST_SET = 1,\n};\n\nenum {\n\tGMR_FS_LEN = 2147418112,\n\tGMR_FS_VLAN = 8192,\n\tGMR_FS_JABBER = 4096,\n\tGMR_FS_UN_SIZE = 2048,\n\tGMR_FS_MC = 1024,\n\tGMR_FS_BC = 512,\n\tGMR_FS_RX_OK = 256,\n\tGMR_FS_GOOD_FC = 128,\n\tGMR_FS_BAD_FC = 64,\n\tGMR_FS_MII_ERR = 32,\n\tGMR_FS_LONG_ERR = 16,\n\tGMR_FS_FRAGMENT = 8,\n\tGMR_FS_CRC_ERR = 2,\n\tGMR_FS_RX_FF_OV = 1,\n\tGMR_FS_ANY_ERR = 6267,\n};\n\nenum {\n\tGMT_ST_START = 4,\n\tGMT_ST_STOP = 2,\n\tGMT_ST_CLR_IRQ = 1,\n};\n\nenum {\n\tGM_GPCR_PROM_ENA = 16384,\n\tGM_GPCR_FC_TX_DIS = 8192,\n\tGM_GPCR_TX_ENA = 4096,\n\tGM_GPCR_RX_ENA = 2048,\n\tGM_GPCR_BURST_ENA = 1024,\n\tGM_GPCR_LOOP_ENA = 512,\n\tGM_GPCR_PART_ENA = 256,\n\tGM_GPCR_GIGS_ENA = 128,\n\tGM_GPCR_FL_PASS = 64,\n\tGM_GPCR_DUP_FULL = 32,\n\tGM_GPCR_FC_RX_DIS = 16,\n\tGM_GPCR_SPEED_100 = 8,\n\tGM_GPCR_AU_DUP_DIS = 4,\n\tGM_GPCR_AU_FCT_DIS = 2,\n\tGM_GPCR_AU_SPD_DIS = 1,\n};\n\nenum {\n\tGM_GP_STAT = 0,\n\tGM_GP_CTRL = 4,\n\tGM_TX_CTRL = 8,\n\tGM_RX_CTRL = 12,\n\tGM_TX_FLOW_CTRL = 16,\n\tGM_TX_PARAM = 20,\n\tGM_SERIAL_MODE = 24,\n\tGM_SRC_ADDR_1L = 28,\n\tGM_SRC_ADDR_1M = 32,\n\tGM_SRC_ADDR_1H = 36,\n\tGM_SRC_ADDR_2L = 40,\n\tGM_SRC_ADDR_2M = 44,\n\tGM_SRC_ADDR_2H = 48,\n\tGM_MC_ADDR_H1 = 52,\n\tGM_MC_ADDR_H2 = 56,\n\tGM_MC_ADDR_H3 = 60,\n\tGM_MC_ADDR_H4 = 64,\n\tGM_TX_IRQ_SRC = 68,\n\tGM_RX_IRQ_SRC = 72,\n\tGM_TR_IRQ_SRC = 76,\n\tGM_TX_IRQ_MSK = 80,\n\tGM_RX_IRQ_MSK = 84,\n\tGM_TR_IRQ_MSK = 88,\n\tGM_SMI_CTRL = 128,\n\tGM_SMI_DATA = 132,\n\tGM_PHY_ADDR = 136,\n\tGM_MIB_CNT_BASE = 256,\n\tGM_MIB_CNT_END = 604,\n};\n\nenum {\n\tGM_IS_TX_CO_OV = 32,\n\tGM_IS_RX_CO_OV = 16,\n\tGM_IS_TX_FF_UR = 8,\n\tGM_IS_TX_COMPL = 4,\n\tGM_IS_RX_FF_OR = 2,\n\tGM_IS_RX_COMPL = 1,\n};\n\nenum {\n\tGM_PAR_MIB_CLR = 32,\n\tGM_PAR_MIB_TST = 16,\n};\n\nenum {\n\tGM_RXCR_UCF_ENA = 32768,\n\tGM_RXCR_MCF_ENA = 16384,\n\tGM_RXCR_CRC_DIS = 8192,\n\tGM_RXCR_PASS_FC = 4096,\n};\n\nenum {\n\tGM_RXF_UC_OK = 256,\n\tGM_RXF_BC_OK = 264,\n\tGM_RXF_MPAUSE = 272,\n\tGM_RXF_MC_OK = 280,\n\tGM_RXF_FCS_ERR = 288,\n\tGM_RXO_OK_LO = 304,\n\tGM_RXO_OK_HI = 312,\n\tGM_RXO_ERR_LO = 320,\n\tGM_RXO_ERR_HI = 328,\n\tGM_RXF_SHT = 336,\n\tGM_RXE_FRAG = 344,\n\tGM_RXF_64B = 352,\n\tGM_RXF_127B = 360,\n\tGM_RXF_255B = 368,\n\tGM_RXF_511B = 376,\n\tGM_RXF_1023B = 384,\n\tGM_RXF_1518B = 392,\n\tGM_RXF_MAX_SZ = 400,\n\tGM_RXF_LNG_ERR = 408,\n\tGM_RXF_JAB_PKT = 416,\n\tGM_RXE_FIFO_OV = 432,\n\tGM_TXF_UC_OK = 448,\n\tGM_TXF_BC_OK = 456,\n\tGM_TXF_MPAUSE = 464,\n\tGM_TXF_MC_OK = 472,\n\tGM_TXO_OK_LO = 480,\n\tGM_TXO_OK_HI = 488,\n\tGM_TXF_64B = 496,\n\tGM_TXF_127B = 504,\n\tGM_TXF_255B = 512,\n\tGM_TXF_511B = 520,\n\tGM_TXF_1023B = 528,\n\tGM_TXF_1518B = 536,\n\tGM_TXF_MAX_SZ = 544,\n\tGM_TXF_COL = 560,\n\tGM_TXF_LAT_COL = 568,\n\tGM_TXF_ABO_COL = 576,\n\tGM_TXF_MUL_COL = 584,\n\tGM_TXF_SNG_COL = 592,\n\tGM_TXE_FIFO_UR = 600,\n};\n\nenum {\n\tGM_SMI_CT_PHY_A_MSK = 63488,\n\tGM_SMI_CT_REG_A_MSK = 1984,\n\tGM_SMI_CT_OP_RD = 32,\n\tGM_SMI_CT_RD_VAL = 16,\n\tGM_SMI_CT_BUSY = 8,\n};\n\nenum {\n\tGM_SMOD_DATABL_MSK = 63488,\n\tGM_SMOD_LIMIT_4 = 1024,\n\tGM_SMOD_VLAN_ENA = 512,\n\tGM_SMOD_JUMBO_ENA = 256,\n\tGM_NEW_FLOW_CTRL = 64,\n\tGM_SMOD_IPG_MSK = 31,\n};\n\nenum {\n\tGM_TXCR_FORCE_JAM = 32768,\n\tGM_TXCR_CRC_DIS = 16384,\n\tGM_TXCR_PAD_DIS = 8192,\n\tGM_TXCR_COL_THR_MSK = 7168,\n};\n\nenum {\n\tGM_TXPA_JAMLEN_MSK = 49152,\n\tGM_TXPA_JAMIPG_MSK = 15872,\n\tGM_TXPA_JAMDAT_MSK = 496,\n\tGM_TXPA_BO_LIM_MSK = 15,\n\tTX_JAM_LEN_DEF = 3,\n\tTX_JAM_IPG_DEF = 11,\n\tTX_IPG_JAM_DEF = 28,\n\tTX_BOF_LIM_DEF = 4,\n};\n\nenum {\n\tGPC_TX_PAUSE = 1073741824,\n\tGPC_RX_PAUSE = 536870912,\n\tGPC_SPEED = 402653184,\n\tGPC_LINK = 67108864,\n\tGPC_DUPLEX = 33554432,\n\tGPC_CLOCK = 16777216,\n\tGPC_PDOWN = 8388608,\n\tGPC_TSTMODE = 4194304,\n\tGPC_REG18 = 2097152,\n\tGPC_REG12SEL = 1572864,\n\tGPC_REG18SEL = 393216,\n\tGPC_SPILOCK = 65536,\n\tGPC_LEDMUX = 49152,\n\tGPC_INTPOL = 8192,\n\tGPC_DETECT = 4096,\n\tGPC_1000HD = 2048,\n\tGPC_SLAVE = 1024,\n\tGPC_PAUSE = 512,\n\tGPC_LEDCTL = 192,\n\tGPC_RST_CLR = 2,\n\tGPC_RST_SET = 1,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tGSSX_NULL = 0,\n\tGSSX_INDICATE_MECHS = 1,\n\tGSSX_GET_CALL_CONTEXT = 2,\n\tGSSX_IMPORT_AND_CANON_NAME = 3,\n\tGSSX_EXPORT_CRED = 4,\n\tGSSX_IMPORT_CRED = 5,\n\tGSSX_ACQUIRE_CRED = 6,\n\tGSSX_STORE_CRED = 7,\n\tGSSX_INIT_SEC_CONTEXT = 8,\n\tGSSX_ACCEPT_SEC_CONTEXT = 9,\n\tGSSX_RELEASE_HANDLE = 10,\n\tGSSX_GET_MIC = 11,\n\tGSSX_VERIFY = 12,\n\tGSSX_WRAP = 13,\n\tGSSX_UNWRAP = 14,\n\tGSSX_WRAP_SIZE_LIMIT = 15,\n};\n\nenum {\n\tGUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0,\n\tGUC_CAPTURE_LIST_CLASS_VIDEO = 1,\n\tGUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2,\n\tGUC_CAPTURE_LIST_CLASS_BLITTER = 3,\n\tGUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4,\n};\n\nenum {\n\tGUC_CAPTURE_LIST_INDEX_PF = 0,\n\tGUC_CAPTURE_LIST_INDEX_VF = 1,\n\tGUC_CAPTURE_LIST_INDEX_MAX = 2,\n};\n\nenum {\n\tGUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 8193,\n\tGUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 8194,\n\tGUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 8195,\n\tGUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 8196,\n\tGUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 8197,\n\tGUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,\n};\n\nenum {\n\tGUC_LOG_SECTIONS_CRASH = 0,\n\tGUC_LOG_SECTIONS_DEBUG = 1,\n\tGUC_LOG_SECTIONS_CAPTURE = 2,\n\tGUC_LOG_SECTIONS_LIMIT = 3,\n};\n\nenum {\n\tGUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD = 4097,\n};\n\nenum {\n\tGUC_WORKAROUND_KLV_SERIALIZED_RA_MODE = 36865,\n\tGUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED = 36866,\n\tGUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 36870,\n};\n\nenum {\n\tHANDSHAKE_A_ACCEPT_SOCKFD = 1,\n\tHANDSHAKE_A_ACCEPT_HANDLER_CLASS = 2,\n\tHANDSHAKE_A_ACCEPT_MESSAGE_TYPE = 3,\n\tHANDSHAKE_A_ACCEPT_TIMEOUT = 4,\n\tHANDSHAKE_A_ACCEPT_AUTH_MODE = 5,\n\tHANDSHAKE_A_ACCEPT_PEER_IDENTITY = 6,\n\tHANDSHAKE_A_ACCEPT_CERTIFICATE = 7,\n\tHANDSHAKE_A_ACCEPT_PEERNAME = 8,\n\tHANDSHAKE_A_ACCEPT_KEYRING = 9,\n\t__HANDSHAKE_A_ACCEPT_MAX = 10,\n\tHANDSHAKE_A_ACCEPT_MAX = 9,\n};\n\nenum {\n\tHANDSHAKE_A_DONE_STATUS = 1,\n\tHANDSHAKE_A_DONE_SOCKFD = 2,\n\tHANDSHAKE_A_DONE_REMOTE_AUTH = 3,\n\t__HANDSHAKE_A_DONE_MAX = 4,\n\tHANDSHAKE_A_DONE_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_A_X509_CERT = 1,\n\tHANDSHAKE_A_X509_PRIVKEY = 2,\n\t__HANDSHAKE_A_X509_MAX = 3,\n\tHANDSHAKE_A_X509_MAX = 2,\n};\n\nenum {\n\tHANDSHAKE_CMD_READY = 1,\n\tHANDSHAKE_CMD_ACCEPT = 2,\n\tHANDSHAKE_CMD_DONE = 3,\n\t__HANDSHAKE_CMD_MAX = 4,\n\tHANDSHAKE_CMD_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_NLGRP_NONE = 0,\n\tHANDSHAKE_NLGRP_TLSHD = 1,\n};\n\nenum {\n\tHASH_SIZE = 128,\n};\n\nenum {\n\tHASH_TCP_IPV6_EX_CTRL = 32,\n\tHASH_IPV6_EX_CTRL = 16,\n\tHASH_TCP_IPV6_CTRL = 8,\n\tHASH_IPV6_CTRL = 4,\n\tHASH_TCP_IPV4_CTRL = 2,\n\tHASH_IPV4_CTRL = 1,\n\tHASH_ALL = 63,\n};\n\nenum {\n\tHAS_GLOBAL_MOCS = 1,\n\tHAS_ENGINE_MOCS = 2,\n\tHAS_RENDER_L3CC = 4,\n};\n\nenum {\n\tHAS_MII_XCVR = 65536,\n\tHAS_CHIP_XCVR = 131072,\n\tHAS_LNK_CHNG = 262144,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHCU_CCSR_SMBALERT_MONITOR = 134217728,\n\tHCU_CCSR_CPU_SLEEP = 67108864,\n\tHCU_CCSR_CS_TO = 33554432,\n\tHCU_CCSR_WDOG = 16777216,\n\tHCU_CCSR_CLR_IRQ_HOST = 131072,\n\tHCU_CCSR_SET_IRQ_HCU = 65536,\n\tHCU_CCSR_AHB_RST = 512,\n\tHCU_CCSR_CPU_RST_MODE = 256,\n\tHCU_CCSR_SET_SYNC_CPU = 32,\n\tHCU_CCSR_CPU_CLK_DIVIDE_MSK = 24,\n\tHCU_CCSR_CPU_CLK_DIVIDE_BASE = 8,\n\tHCU_CCSR_OS_PRSNT = 4,\n\tHCU_CCSR_UC_STATE_MSK = 3,\n\tHCU_CCSR_UC_STATE_BASE = 1,\n\tHCU_CCSR_ASF_RESET = 0,\n\tHCU_CCSR_ASF_HALTED = 2,\n\tHCU_CCSR_ASF_RUNNING = 1,\n};\n\nenum {\n\tHDA_DEV_CORE = 0,\n\tHDA_DEV_LEGACY = 1,\n\tHDA_DEV_ASOC = 2,\n};\n\nenum {\n\tHDA_DIG_NONE = 0,\n\tHDA_DIG_EXCLUSIVE = 1,\n\tHDA_DIG_ANALOG_DUP = 2,\n};\n\nenum {\n\tHDA_FIXUP_ACT_PRE_PROBE = 0,\n\tHDA_FIXUP_ACT_PROBE = 1,\n\tHDA_FIXUP_ACT_INIT = 2,\n\tHDA_FIXUP_ACT_BUILD = 3,\n\tHDA_FIXUP_ACT_FREE = 4,\n};\n\nenum {\n\tHDA_FIXUP_INVALID = 0,\n\tHDA_FIXUP_PINS = 1,\n\tHDA_FIXUP_VERBS = 2,\n\tHDA_FIXUP_FUNC = 3,\n\tHDA_FIXUP_PINCTLS = 4,\n};\n\nenum {\n\tHDA_FRONT = 0,\n\tHDA_REAR = 1,\n\tHDA_CLFE = 2,\n\tHDA_SIDE = 3,\n};\n\nenum {\n\tHDA_INPUT = 0,\n\tHDA_OUTPUT = 1,\n};\n\nenum {\n\tHDA_JACK_NOT_PRESENT = 0,\n\tHDA_JACK_PRESENT = 1,\n\tHDA_JACK_PHANTOM = 2,\n};\n\nenum {\n\tHDA_PCM_TYPE_AUDIO = 0,\n\tHDA_PCM_TYPE_SPDIF = 1,\n\tHDA_PCM_TYPE_HDMI = 2,\n\tHDA_PCM_TYPE_MODEM = 3,\n\tHDA_PCM_NTYPES = 4,\n};\n\nenum {\n\tHIBERNATION_INVALID = 0,\n\tHIBERNATION_PLATFORM = 1,\n\tHIBERNATION_SHUTDOWN = 2,\n\tHIBERNATION_REBOOT = 3,\n\tHIBERNATION_SUSPEND = 4,\n\tHIBERNATION_TEST_RESUME = 5,\n\t__HIBERNATION_AFTER_LAST = 6,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHSWEP_PCI_UNCORE_HA = 0,\n\tHSWEP_PCI_UNCORE_IMC = 1,\n\tHSWEP_PCI_UNCORE_IRP = 2,\n\tHSWEP_PCI_UNCORE_QPI = 3,\n\tHSWEP_PCI_UNCORE_R2PCIE = 4,\n\tHSWEP_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tHW_BREAKPOINT_EMPTY = 0,\n\tHW_BREAKPOINT_R = 1,\n\tHW_BREAKPOINT_W = 2,\n\tHW_BREAKPOINT_RW = 3,\n\tHW_BREAKPOINT_X = 4,\n\tHW_BREAKPOINT_INVALID = 7,\n};\n\nenum {\n\tHW_BREAKPOINT_LEN_1 = 1,\n\tHW_BREAKPOINT_LEN_2 = 2,\n\tHW_BREAKPOINT_LEN_3 = 3,\n\tHW_BREAKPOINT_LEN_4 = 4,\n\tHW_BREAKPOINT_LEN_5 = 5,\n\tHW_BREAKPOINT_LEN_6 = 6,\n\tHW_BREAKPOINT_LEN_7 = 7,\n\tHW_BREAKPOINT_LEN_8 = 8,\n};\n\nenum {\n\tHW_OWNER = 128,\n\tOP_TCPWRITE = 17,\n\tOP_TCPSTART = 18,\n\tOP_TCPINIT = 20,\n\tOP_TCPLCK = 24,\n\tOP_TCPCHKSUM = 18,\n\tOP_TCPIS = 22,\n\tOP_TCPLW = 25,\n\tOP_TCPLSW = 27,\n\tOP_TCPLISW = 31,\n\tOP_ADDR64 = 33,\n\tOP_VLAN = 34,\n\tOP_ADDR64VLAN = 35,\n\tOP_LRGLEN = 36,\n\tOP_LRGLENVLAN = 38,\n\tOP_MSS = 40,\n\tOP_MSSVLAN = 42,\n\tOP_BUFFER = 64,\n\tOP_PACKET = 65,\n\tOP_LARGESEND = 67,\n\tOP_LSOV2 = 69,\n\tOP_RXSTAT = 96,\n\tOP_RXTIMESTAMP = 97,\n\tOP_RXVLAN = 98,\n\tOP_RXCHKS = 100,\n\tOP_RXCHKSVLAN = 102,\n\tOP_RXTIMEVLAN = 99,\n\tOP_RSS_HASH = 101,\n\tOP_TXINDEXLE = 104,\n\tOP_MACSEC = 108,\n\tOP_PUTIDX = 112,\n};\n\nenum {\n\tI915_FENCE_FLAG_ACTIVE = 4,\n\tI915_FENCE_FLAG_PQUEUE = 5,\n\tI915_FENCE_FLAG_HOLD = 6,\n\tI915_FENCE_FLAG_INITIAL_BREADCRUMB = 7,\n\tI915_FENCE_FLAG_SIGNAL = 8,\n\tI915_FENCE_FLAG_NOPREEMPT = 9,\n\tI915_FENCE_FLAG_SENTINEL = 10,\n\tI915_FENCE_FLAG_BOOST = 11,\n\tI915_FENCE_FLAG_SUBMIT_PARALLEL = 12,\n\tI915_FENCE_FLAG_SKIP_PARALLEL = 13,\n\tI915_FENCE_FLAG_COMPOSITE = 14,\n};\n\nenum {\n\tI915_PRIORITY_MIN = -1024,\n\tI915_PRIORITY_NORMAL = 0,\n\tI915_PRIORITY_MAX = 1024,\n\tI915_PRIORITY_HEARTBEAT = 1025,\n\tI915_PRIORITY_DISPLAY = 1026,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tICX_PCIE1_PMON_ID = 0,\n\tICX_PCIE2_PMON_ID = 1,\n\tICX_PCIE3_PMON_ID = 2,\n\tICX_PCIE4_PMON_ID = 3,\n\tICX_PCIE5_PMON_ID = 4,\n\tICX_CBDMA_DMI_PMON_ID = 5,\n};\n\nenum {\n\tICX_PCI_UNCORE_M2M = 0,\n\tICX_PCI_UNCORE_UPI = 1,\n\tICX_PCI_UNCORE_M3UPI = 2,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIEEE80211_PROBE_FLAG_DIRECTED = 1,\n\tIEEE80211_PROBE_FLAG_MIN_CONTENT = 2,\n\tIEEE80211_PROBE_FLAG_RANDOM_SN = 4,\n};\n\nenum {\n\tIEEE80211_RX_MSG = 1,\n\tIEEE80211_TX_STATUS_MSG = 2,\n};\n\nenum {\n\tIFAL_ADDRESS = 1,\n\tIFAL_LABEL = 2,\n\t__IFAL_MAX = 3,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET6_UNSPEC = 0,\n\tIFLA_INET6_FLAGS = 1,\n\tIFLA_INET6_CONF = 2,\n\tIFLA_INET6_STATS = 3,\n\tIFLA_INET6_MCAST = 4,\n\tIFLA_INET6_CACHEINFO = 5,\n\tIFLA_INET6_ICMP6STATS = 6,\n\tIFLA_INET6_TOKEN = 7,\n\tIFLA_INET6_ADDR_GEN_MODE = 8,\n\tIFLA_INET6_RA_MTU = 9,\n\t__IFLA_INET6_MAX = 10,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_ACT_NONE = -1,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nenum {\n\tIIO_TOPOLOGY_TYPE = 0,\n\tUPI_TOPOLOGY_TYPE = 1,\n\tTOPOLOGY_MAX = 2,\n};\n\nenum {\n\tINET6_IFADDR_STATE_PREDAD = 0,\n\tINET6_IFADDR_STATE_DAD = 1,\n\tINET6_IFADDR_STATE_POSTDAD = 2,\n\tINET6_IFADDR_STATE_ERRDAD = 3,\n\tINET6_IFADDR_STATE_DEAD = 4,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINPUT_PIN_ATTR_UNUSED = 0,\n\tINPUT_PIN_ATTR_INT = 1,\n\tINPUT_PIN_ATTR_DOCK = 2,\n\tINPUT_PIN_ATTR_NORMAL = 3,\n\tINPUT_PIN_ATTR_REAR = 4,\n\tINPUT_PIN_ATTR_FRONT = 5,\n\tINPUT_PIN_ATTR_LAST = 5,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINTEL_ADVANCED_CONTEXT = 0,\n\tINTEL_LEGACY_32B_CONTEXT = 1,\n\tINTEL_ADVANCED_AD_CONTEXT = 2,\n\tINTEL_LEGACY_64B_CONTEXT = 3,\n};\n\nenum {\n\tINTEL_CONTEXT_SCHEDULE_IN = 0,\n\tINTEL_CONTEXT_SCHEDULE_OUT = 1,\n\tINTEL_CONTEXT_SCHEDULE_PREEMPTED = 2,\n};\n\nenum {\n\tINTEL_RPS_ENABLED = 0,\n\tINTEL_RPS_ACTIVE = 1,\n\tINTEL_RPS_INTERRUPTS = 2,\n\tINTEL_RPS_TIMER = 3,\n};\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tIOAM6_ATTR_UNSPEC = 0,\n\tIOAM6_ATTR_NS_ID = 1,\n\tIOAM6_ATTR_NS_DATA = 2,\n\tIOAM6_ATTR_NS_DATA_WIDE = 3,\n\tIOAM6_ATTR_SC_ID = 4,\n\tIOAM6_ATTR_SC_DATA = 5,\n\tIOAM6_ATTR_SC_NONE = 6,\n\tIOAM6_ATTR_PAD = 7,\n\t__IOAM6_ATTR_MAX = 8,\n};\n\nenum {\n\tIOAM6_CMD_UNSPEC = 0,\n\tIOAM6_CMD_ADD_NAMESPACE = 1,\n\tIOAM6_CMD_DEL_NAMESPACE = 2,\n\tIOAM6_CMD_DUMP_NAMESPACES = 3,\n\tIOAM6_CMD_ADD_SCHEMA = 4,\n\tIOAM6_CMD_DEL_SCHEMA = 5,\n\tIOAM6_CMD_DUMP_SCHEMAS = 6,\n\tIOAM6_CMD_NS_SET_SCHEMA = 7,\n\t__IOAM6_CMD_MAX = 8,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOMMU_PASID_ARRAY_DOMAIN = 0,\n\tIOMMU_PASID_ARRAY_HANDLE = 1,\n};\n\nenum {\n\tIOMMU_SET_DOMAIN_MUST_SUCCEED = 1,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORES_MAP_SYSTEM_RAM = 1,\n\tIORES_MAP_ENCRYPTED = 2,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPMRA_CREPORT_UNSPEC = 0,\n\tIPMRA_CREPORT_MSGTYPE = 1,\n\tIPMRA_CREPORT_VIF_ID = 2,\n\tIPMRA_CREPORT_SRC_ADDR = 3,\n\tIPMRA_CREPORT_DST_ADDR = 4,\n\tIPMRA_CREPORT_PKT = 5,\n\tIPMRA_CREPORT_TABLE = 6,\n\t__IPMRA_CREPORT_MAX = 7,\n};\n\nenum {\n\tIPMRA_TABLE_UNSPEC = 0,\n\tIPMRA_TABLE_ID = 1,\n\tIPMRA_TABLE_CACHE_RES_QUEUE_LEN = 2,\n\tIPMRA_TABLE_MROUTE_REG_VIF_NUM = 3,\n\tIPMRA_TABLE_MROUTE_DO_ASSERT = 4,\n\tIPMRA_TABLE_MROUTE_DO_PIM = 5,\n\tIPMRA_TABLE_VIFS = 6,\n\tIPMRA_TABLE_MROUTE_DO_WRVIFWHOLE = 7,\n\t__IPMRA_TABLE_MAX = 8,\n};\n\nenum {\n\tIPMRA_VIFA_UNSPEC = 0,\n\tIPMRA_VIFA_IFINDEX = 1,\n\tIPMRA_VIFA_VIF_ID = 2,\n\tIPMRA_VIFA_FLAGS = 3,\n\tIPMRA_VIFA_BYTES_IN = 4,\n\tIPMRA_VIFA_BYTES_OUT = 5,\n\tIPMRA_VIFA_PACKETS_IN = 6,\n\tIPMRA_VIFA_PACKETS_OUT = 7,\n\tIPMRA_VIFA_LOCAL_ADDR = 8,\n\tIPMRA_VIFA_REMOTE_ADDR = 9,\n\tIPMRA_VIFA_PAD = 10,\n\t__IPMRA_VIFA_MAX = 11,\n};\n\nenum {\n\tIPMRA_VIF_UNSPEC = 0,\n\tIPMRA_VIF = 1,\n\t__IPMRA_VIF_MAX = 2,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIPV6_SADDR_RULE_INIT = 0,\n\tIPV6_SADDR_RULE_LOCAL = 1,\n\tIPV6_SADDR_RULE_SCOPE = 2,\n\tIPV6_SADDR_RULE_PREFERRED = 3,\n\tIPV6_SADDR_RULE_OIF = 4,\n\tIPV6_SADDR_RULE_LABEL = 5,\n\tIPV6_SADDR_RULE_PRIVACY = 6,\n\tIPV6_SADDR_RULE_ORCHID = 7,\n\tIPV6_SADDR_RULE_PREFIX = 8,\n\tIPV6_SADDR_RULE_MAX = 9,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_REMAP_XAPIC_MODE = 0,\n\tIRQ_REMAP_X2APIC_MODE = 1,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tIVBEP_PCI_UNCORE_HA = 0,\n\tIVBEP_PCI_UNCORE_IMC = 1,\n\tIVBEP_PCI_UNCORE_IRP = 2,\n\tIVBEP_PCI_UNCORE_QPI = 3,\n\tIVBEP_PCI_UNCORE_R2PCIE = 4,\n\tIVBEP_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tI_DATA_SEM_NORMAL = 0,\n\tI_DATA_SEM_OTHER = 1,\n\tI_DATA_SEM_QUOTA = 2,\n\tI_DATA_SEM_EA = 3,\n};\n\nenum {\n\tI_LCOEF_RBPS = 0,\n\tI_LCOEF_RSEQIOPS = 1,\n\tI_LCOEF_RRANDIOPS = 2,\n\tI_LCOEF_WBPS = 3,\n\tI_LCOEF_WSEQIOPS = 4,\n\tI_LCOEF_WRANDIOPS = 5,\n\tNR_I_LCOEFS = 6,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKNL_PCI_UNCORE_MC_UCLK = 0,\n\tKNL_PCI_UNCORE_MC_DCLK = 1,\n\tKNL_PCI_UNCORE_EDC_UCLK = 2,\n\tKNL_PCI_UNCORE_EDC_ECLK = 3,\n\tKNL_PCI_UNCORE_M2PCIE = 4,\n\tKNL_PCI_UNCORE_IRP = 5,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLBR_FORMAT_32 = 0,\n\tLBR_FORMAT_LIP = 1,\n\tLBR_FORMAT_EIP = 2,\n\tLBR_FORMAT_EIP_FLAGS = 3,\n\tLBR_FORMAT_EIP_FLAGS2 = 4,\n\tLBR_FORMAT_INFO = 5,\n\tLBR_FORMAT_TIME = 6,\n\tLBR_FORMAT_INFO2 = 7,\n\tLBR_FORMAT_MAX_KNOWN = 7,\n};\n\nenum {\n\tLBR_NONE = 0,\n\tLBR_VALID = 1,\n};\n\nenum {\n\tLCOEF_RPAGE = 0,\n\tLCOEF_RSEQIO = 1,\n\tLCOEF_RRANDIO = 2,\n\tLCOEF_WPAGE = 3,\n\tLCOEF_WSEQIO = 4,\n\tLCOEF_WRANDIO = 5,\n\tNR_LCOEFS = 6,\n};\n\nenum {\n\tLED_PAR_CTRL_COLX = 0,\n\tLED_PAR_CTRL_ERROR = 1,\n\tLED_PAR_CTRL_DUPLEX = 2,\n\tLED_PAR_CTRL_DP_COL = 3,\n\tLED_PAR_CTRL_SPEED = 4,\n\tLED_PAR_CTRL_LINK = 5,\n\tLED_PAR_CTRL_TX = 6,\n\tLED_PAR_CTRL_RX = 7,\n\tLED_PAR_CTRL_ACT = 8,\n\tLED_PAR_CTRL_LNK_RX = 9,\n\tLED_PAR_CTRL_LNK_AC = 10,\n\tLED_PAR_CTRL_ACT_BL = 11,\n\tLED_PAR_CTRL_TX_BL = 12,\n\tLED_PAR_CTRL_RX_BL = 13,\n\tLED_PAR_CTRL_COL_BL = 14,\n\tLED_PAR_CTRL_INACT = 15,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = -1,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_FUA = 512,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_NCQ_SEND_RECV = 2048,\n\tATA_DFLAG_NCQ_PRIO = 4096,\n\tATA_DFLAG_CDL = 8192,\n\tATA_DFLAG_CFG_MASK = 16383,\n\tATA_DFLAG_PIO = 16384,\n\tATA_DFLAG_NCQ_OFF = 32768,\n\tATA_DFLAG_SLEEPING = 65536,\n\tATA_DFLAG_DUBIOUS_XFER = 131072,\n\tATA_DFLAG_NO_UNLOAD = 262144,\n\tATA_DFLAG_UNLOCK_HPA = 524288,\n\tATA_DFLAG_INIT_MASK = 1048575,\n\tATA_DFLAG_NCQ_PRIO_ENABLED = 1048576,\n\tATA_DFLAG_CDL_ENABLED = 2097152,\n\tATA_DFLAG_RESUMING = 4194304,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_FEATURES_MASK = 201341696,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DEBOUNCE_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_RESUMING = 65536,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_RTF_FILLED = 4,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_HAS_CDL = 256,\n\tATA_QCFLAG_EH = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_QCFLAG_EH_SUCCESS_CMD = 524288,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_HOST_NO_PART = 16,\n\tATA_HOST_NO_SSC = 32,\n\tATA_HOST_NO_DEVSLP = 64,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 10000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_GET_SUCCESS_SENSE = 64,\n\tATA_EH_SET_ACTIVE = 128,\n\tATA_EH_PERDEV_MASK = 225,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_PRINT_QUIRKS = 2097152,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum {\n\tLINKLED_OFF = 1,\n\tLINKLED_ON = 2,\n\tLINKLED_LINKSYNC_OFF = 4,\n\tLINKLED_LINKSYNC_ON = 8,\n\tLINKLED_BLINK_OFF = 16,\n\tLINKLED_BLINK_ON = 32,\n};\n\nenum {\n\tLINK_CAPA_10HD = 0,\n\tLINK_CAPA_10FD = 1,\n\tLINK_CAPA_100HD = 2,\n\tLINK_CAPA_100FD = 3,\n\tLINK_CAPA_1000HD = 4,\n\tLINK_CAPA_1000FD = 5,\n\tLINK_CAPA_2500FD = 6,\n\tLINK_CAPA_5000FD = 7,\n\tLINK_CAPA_10000FD = 8,\n\tLINK_CAPA_20000FD = 9,\n\tLINK_CAPA_25000FD = 10,\n\tLINK_CAPA_40000FD = 11,\n\tLINK_CAPA_50000FD = 12,\n\tLINK_CAPA_56000FD = 13,\n\tLINK_CAPA_80000FD = 14,\n\tLINK_CAPA_100000FD = 15,\n\tLINK_CAPA_200000FD = 16,\n\tLINK_CAPA_400000FD = 17,\n\tLINK_CAPA_800000FD = 18,\n\tLINK_CAPA_1600000FD = 19,\n\t__LINK_CAPA_MAX = 20,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLK_STATE_IN_USE = 0,\n\tNFS_DELEGATED_STATE = 1,\n\tNFS_OPEN_STATE = 2,\n\tNFS_O_RDONLY_STATE = 3,\n\tNFS_O_WRONLY_STATE = 4,\n\tNFS_O_RDWR_STATE = 5,\n\tNFS_STATE_RECLAIM_REBOOT = 6,\n\tNFS_STATE_RECLAIM_NOGRACE = 7,\n\tNFS_STATE_POSIX_LOCKS = 8,\n\tNFS_STATE_RECOVERY_FAILED = 9,\n\tNFS_STATE_MAY_NOTIFY_LOCK = 10,\n\tNFS_STATE_CHANGE_WAIT = 11,\n\tNFS_CLNT_DST_SSC_COPY_STATE = 12,\n\tNFS_CLNT_SRC_SSC_COPY_STATE = 13,\n\tNFS_SRV_SSC_COPY_STATE = 14,\n};\n\nenum {\n\tLNK_SYNC_INI = 3120,\n\tLNK_SYNC_VAL = 3124,\n\tLNK_SYNC_CTRL = 3128,\n\tLNK_SYNC_TST = 3129,\n\tLNK_LED_REG = 3132,\n\tRX_GMF_EA = 3136,\n\tRX_GMF_AF_THR = 3140,\n\tRX_GMF_CTRL_T = 3144,\n\tRX_GMF_FL_MSK = 3148,\n\tRX_GMF_FL_THR = 3152,\n\tRX_GMF_FL_CTRL = 3154,\n\tRX_GMF_TR_THR = 3156,\n\tRX_GMF_UP_THR = 3160,\n\tRX_GMF_LP_THR = 3162,\n\tRX_GMF_VLAN = 3164,\n\tRX_GMF_WP = 3168,\n\tRX_GMF_WLEV = 3176,\n\tRX_GMF_RP = 3184,\n\tRX_GMF_RLEV = 3192,\n};\n\nenum {\n\tLOCKD_A_SERVER_GRACETIME = 1,\n\tLOCKD_A_SERVER_TCP_PORT = 2,\n\tLOCKD_A_SERVER_UDP_PORT = 3,\n\t__LOCKD_A_SERVER_MAX = 4,\n\tLOCKD_A_SERVER_MAX = 3,\n};\n\nenum {\n\tLOCKD_CMD_SERVER_SET = 1,\n\tLOCKD_CMD_SERVER_GET = 2,\n\t__LOCKD_CMD_MAX = 3,\n\tLOCKD_CMD_MAX = 2,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n\tLo_deleting = 3,\n};\n\nenum {\n\tMAC_TX_CLK_0_MHZ = 2,\n\tMAC_TX_CLK_2_5_MHZ = 6,\n\tMAC_TX_CLK_25_MHZ = 7,\n};\n\nenum {\n\tMAGNITUDE_STRONG = 2,\n\tMAGNITUDE_WEAK = 3,\n\tMAGNITUDE_NUM = 4,\n};\n\nenum {\n\tMATCH_MTR = 0,\n\tMATCH_MEQ = 1,\n\tMATCH_MLE = 2,\n\tMATCH_MLT = 3,\n\tMATCH_MGE = 4,\n\tMATCH_MGT = 5,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMBE_REFERENCED_B = 0,\n\tMBE_REUSABLE_B = 1,\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMD_RESYNC_NONE = 0,\n\tMD_RESYNC_YIELDED = 1,\n\tMD_RESYNC_DELAYED = 2,\n\tMD_RESYNC_ACTIVE = 3,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMFC_STATIC = 1,\n\tMFC_OFFLOAD = 2,\n};\n\nenum {\n\tMILLION = 1000000,\n\tMIN_PERIOD = 1000,\n\tMAX_PERIOD = 1000000,\n\tMARGIN_MIN_PCT = 10,\n\tMARGIN_LOW_PCT = 20,\n\tMARGIN_TARGET_PCT = 50,\n\tINUSE_ADJ_STEP_PCT = 25,\n\tTIMER_SLACK_PCT = 1,\n\tWEIGHT_ONE = 65536,\n};\n\nenum {\n\tMIPI_DCS_NOP = 0,\n\tMIPI_DCS_SOFT_RESET = 1,\n\tMIPI_DCS_GET_COMPRESSION_MODE = 3,\n\tMIPI_DCS_GET_DISPLAY_ID = 4,\n\tMIPI_DCS_GET_ERROR_COUNT_ON_DSI = 5,\n\tMIPI_DCS_GET_RED_CHANNEL = 6,\n\tMIPI_DCS_GET_GREEN_CHANNEL = 7,\n\tMIPI_DCS_GET_BLUE_CHANNEL = 8,\n\tMIPI_DCS_GET_DISPLAY_STATUS = 9,\n\tMIPI_DCS_GET_POWER_MODE = 10,\n\tMIPI_DCS_GET_ADDRESS_MODE = 11,\n\tMIPI_DCS_GET_PIXEL_FORMAT = 12,\n\tMIPI_DCS_GET_DISPLAY_MODE = 13,\n\tMIPI_DCS_GET_SIGNAL_MODE = 14,\n\tMIPI_DCS_GET_DIAGNOSTIC_RESULT = 15,\n\tMIPI_DCS_ENTER_SLEEP_MODE = 16,\n\tMIPI_DCS_EXIT_SLEEP_MODE = 17,\n\tMIPI_DCS_ENTER_PARTIAL_MODE = 18,\n\tMIPI_DCS_ENTER_NORMAL_MODE = 19,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 20,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_CT = 21,\n\tMIPI_DCS_EXIT_INVERT_MODE = 32,\n\tMIPI_DCS_ENTER_INVERT_MODE = 33,\n\tMIPI_DCS_SET_GAMMA_CURVE = 38,\n\tMIPI_DCS_SET_DISPLAY_OFF = 40,\n\tMIPI_DCS_SET_DISPLAY_ON = 41,\n\tMIPI_DCS_SET_COLUMN_ADDRESS = 42,\n\tMIPI_DCS_SET_PAGE_ADDRESS = 43,\n\tMIPI_DCS_WRITE_MEMORY_START = 44,\n\tMIPI_DCS_WRITE_LUT = 45,\n\tMIPI_DCS_READ_MEMORY_START = 46,\n\tMIPI_DCS_SET_PARTIAL_ROWS = 48,\n\tMIPI_DCS_SET_PARTIAL_COLUMNS = 49,\n\tMIPI_DCS_SET_SCROLL_AREA = 51,\n\tMIPI_DCS_SET_TEAR_OFF = 52,\n\tMIPI_DCS_SET_TEAR_ON = 53,\n\tMIPI_DCS_SET_ADDRESS_MODE = 54,\n\tMIPI_DCS_SET_SCROLL_START = 55,\n\tMIPI_DCS_EXIT_IDLE_MODE = 56,\n\tMIPI_DCS_ENTER_IDLE_MODE = 57,\n\tMIPI_DCS_SET_PIXEL_FORMAT = 58,\n\tMIPI_DCS_WRITE_MEMORY_CONTINUE = 60,\n\tMIPI_DCS_SET_3D_CONTROL = 61,\n\tMIPI_DCS_READ_MEMORY_CONTINUE = 62,\n\tMIPI_DCS_GET_3D_CONTROL = 63,\n\tMIPI_DCS_SET_VSYNC_TIMING = 64,\n\tMIPI_DCS_SET_TEAR_SCANLINE = 68,\n\tMIPI_DCS_GET_SCANLINE = 69,\n\tMIPI_DCS_SET_DISPLAY_BRIGHTNESS = 81,\n\tMIPI_DCS_GET_DISPLAY_BRIGHTNESS = 82,\n\tMIPI_DCS_WRITE_CONTROL_DISPLAY = 83,\n\tMIPI_DCS_GET_CONTROL_DISPLAY = 84,\n\tMIPI_DCS_WRITE_POWER_SAVE = 85,\n\tMIPI_DCS_GET_POWER_SAVE = 86,\n\tMIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 94,\n\tMIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 95,\n\tMIPI_DCS_READ_DDB_START = 161,\n\tMIPI_DCS_READ_PPS_START = 162,\n\tMIPI_DCS_READ_DDB_CONTINUE = 168,\n\tMIPI_DCS_READ_PPS_CONTINUE = 169,\n};\n\nenum {\n\tMIPI_DSI_V_SYNC_START = 1,\n\tMIPI_DSI_V_SYNC_END = 17,\n\tMIPI_DSI_H_SYNC_START = 33,\n\tMIPI_DSI_H_SYNC_END = 49,\n\tMIPI_DSI_COMPRESSION_MODE = 7,\n\tMIPI_DSI_END_OF_TRANSMISSION = 8,\n\tMIPI_DSI_COLOR_MODE_OFF = 2,\n\tMIPI_DSI_COLOR_MODE_ON = 18,\n\tMIPI_DSI_SHUTDOWN_PERIPHERAL = 34,\n\tMIPI_DSI_TURN_ON_PERIPHERAL = 50,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 3,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 19,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 35,\n\tMIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 4,\n\tMIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 20,\n\tMIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 36,\n\tMIPI_DSI_DCS_SHORT_WRITE = 5,\n\tMIPI_DSI_DCS_SHORT_WRITE_PARAM = 21,\n\tMIPI_DSI_DCS_READ = 6,\n\tMIPI_DSI_EXECUTE_QUEUE = 22,\n\tMIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 55,\n\tMIPI_DSI_NULL_PACKET = 9,\n\tMIPI_DSI_BLANKING_PACKET = 25,\n\tMIPI_DSI_GENERIC_LONG_WRITE = 41,\n\tMIPI_DSI_DCS_LONG_WRITE = 57,\n\tMIPI_DSI_PICTURE_PARAMETER_SET = 10,\n\tMIPI_DSI_COMPRESSED_PIXEL_STREAM = 11,\n\tMIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 12,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 28,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 44,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_30 = 13,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_36 = 29,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 61,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_16 = 14,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_18 = 30,\n\tMIPI_DSI_PIXEL_STREAM_3BYTE_18 = 46,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_24 = 62,\n};\n\nenum {\n\tMIPI_RESET_1 = 0,\n\tMIPI_AVDD_EN_1 = 1,\n\tMIPI_BKLT_EN_1 = 2,\n\tMIPI_AVEE_EN_1 = 3,\n\tMIPI_VIO_EN_1 = 4,\n\tMIPI_RESET_2 = 5,\n\tMIPI_AVDD_EN_2 = 6,\n\tMIPI_BKLT_EN_2 = 7,\n\tMIPI_AVEE_EN_2 = 8,\n\tMIPI_VIO_EN_2 = 9,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMODE_640x480 = 0,\n\tMODE_800x600 = 1,\n\tMODE_1024x768 = 2,\n};\n\nenum {\n\tMOUNTPROC3_NULL = 0,\n\tMOUNTPROC3_MNT = 1,\n\tMOUNTPROC3_DUMP = 2,\n\tMOUNTPROC3_UMNT = 3,\n\tMOUNTPROC3_UMNTALL = 4,\n\tMOUNTPROC3_EXPORT = 5,\n};\n\nenum {\n\tMOUNTPROC_NULL = 0,\n\tMOUNTPROC_MNT = 1,\n\tMOUNTPROC_DUMP = 2,\n\tMOUNTPROC_UMNT = 3,\n\tMOUNTPROC_UMNTALL = 4,\n\tMOUNTPROC_EXPORT = 5,\n};\n\nenum {\n\tMOXA_SUPP_RS232 = 1,\n\tMOXA_SUPP_RS422 = 2,\n\tMOXA_SUPP_RS485 = 4,\n};\n\nenum {\n\tMPOL_DEFAULT = 0,\n\tMPOL_PREFERRED = 1,\n\tMPOL_BIND = 2,\n\tMPOL_INTERLEAVE = 3,\n\tMPOL_LOCAL = 4,\n\tMPOL_PREFERRED_MANY = 5,\n\tMPOL_WEIGHTED_INTERLEAVE = 6,\n\tMPOL_MAX = 7,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tMTTG_TRAV_INIT = 0,\n\tMTTG_TRAV_NFP_UNSPEC = 1,\n\tMTTG_TRAV_NFP_SPEC = 2,\n\tMTTG_TRAV_DONE = 3,\n};\n\nenum {\n\tNAMESZ = 12,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDD_UNARMED = 1,\n\tNDD_LOCKED = 2,\n\tNDD_SECURITY_OVERWRITE = 3,\n\tNDD_WORK_PENDING = 4,\n\tNDD_LABELING = 6,\n\tNDD_INCOHERENT = 7,\n\tNDD_REGISTER_SYNC = 8,\n\tND_IOCTL_MAX_BUFLEN = 4194304,\n\tND_CMD_MAX_ELEM = 5,\n\tND_CMD_MAX_ENVELOPE = 256,\n\tND_MAX_MAPPINGS = 32,\n\tND_REGION_PAGEMAP = 0,\n\tND_REGION_PERSIST_CACHE = 1,\n\tND_REGION_PERSIST_MEMCTRL = 2,\n\tND_REGION_ASYNC = 3,\n\tND_REGION_CXL = 4,\n\tDPA_RESOURCE_ADJUSTED = 1,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNDUSEROPT_UNSPEC = 0,\n\tNDUSEROPT_SRCADDR = 1,\n\t__NDUSEROPT_MAX = 2,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETDEV_STATS = 0,\n\tE1000_STATS = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFNL_BATCH_FAILURE = 1,\n\tNFNL_BATCH_DONE = 2,\n\tNFNL_BATCH_REPLAY = 4,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNFSPROC4_CLNT_NULL = 0,\n\tNFSPROC4_CLNT_READ = 1,\n\tNFSPROC4_CLNT_WRITE = 2,\n\tNFSPROC4_CLNT_COMMIT = 3,\n\tNFSPROC4_CLNT_OPEN = 4,\n\tNFSPROC4_CLNT_OPEN_CONFIRM = 5,\n\tNFSPROC4_CLNT_OPEN_NOATTR = 6,\n\tNFSPROC4_CLNT_OPEN_DOWNGRADE = 7,\n\tNFSPROC4_CLNT_CLOSE = 8,\n\tNFSPROC4_CLNT_SETATTR = 9,\n\tNFSPROC4_CLNT_FSINFO = 10,\n\tNFSPROC4_CLNT_RENEW = 11,\n\tNFSPROC4_CLNT_SETCLIENTID = 12,\n\tNFSPROC4_CLNT_SETCLIENTID_CONFIRM = 13,\n\tNFSPROC4_CLNT_LOCK = 14,\n\tNFSPROC4_CLNT_LOCKT = 15,\n\tNFSPROC4_CLNT_LOCKU = 16,\n\tNFSPROC4_CLNT_ACCESS = 17,\n\tNFSPROC4_CLNT_GETATTR = 18,\n\tNFSPROC4_CLNT_LOOKUP = 19,\n\tNFSPROC4_CLNT_LOOKUP_ROOT = 20,\n\tNFSPROC4_CLNT_REMOVE = 21,\n\tNFSPROC4_CLNT_RENAME = 22,\n\tNFSPROC4_CLNT_LINK = 23,\n\tNFSPROC4_CLNT_SYMLINK = 24,\n\tNFSPROC4_CLNT_CREATE = 25,\n\tNFSPROC4_CLNT_PATHCONF = 26,\n\tNFSPROC4_CLNT_STATFS = 27,\n\tNFSPROC4_CLNT_READLINK = 28,\n\tNFSPROC4_CLNT_READDIR = 29,\n\tNFSPROC4_CLNT_SERVER_CAPS = 30,\n\tNFSPROC4_CLNT_DELEGRETURN = 31,\n\tNFSPROC4_CLNT_GETACL = 32,\n\tNFSPROC4_CLNT_SETACL = 33,\n\tNFSPROC4_CLNT_FS_LOCATIONS = 34,\n\tNFSPROC4_CLNT_RELEASE_LOCKOWNER = 35,\n\tNFSPROC4_CLNT_SECINFO = 36,\n\tNFSPROC4_CLNT_FSID_PRESENT = 37,\n\tNFSPROC4_CLNT_EXCHANGE_ID = 38,\n\tNFSPROC4_CLNT_CREATE_SESSION = 39,\n\tNFSPROC4_CLNT_DESTROY_SESSION = 40,\n\tNFSPROC4_CLNT_SEQUENCE = 41,\n\tNFSPROC4_CLNT_GET_LEASE_TIME = 42,\n\tNFSPROC4_CLNT_RECLAIM_COMPLETE = 43,\n\tNFSPROC4_CLNT_LAYOUTGET = 44,\n\tNFSPROC4_CLNT_GETDEVICEINFO = 45,\n\tNFSPROC4_CLNT_LAYOUTCOMMIT = 46,\n\tNFSPROC4_CLNT_LAYOUTRETURN = 47,\n\tNFSPROC4_CLNT_SECINFO_NO_NAME = 48,\n\tNFSPROC4_CLNT_TEST_STATEID = 49,\n\tNFSPROC4_CLNT_FREE_STATEID = 50,\n\tNFSPROC4_CLNT_GETDEVICELIST = 51,\n\tNFSPROC4_CLNT_BIND_CONN_TO_SESSION = 52,\n\tNFSPROC4_CLNT_DESTROY_CLIENTID = 53,\n\tNFSPROC4_CLNT_SEEK = 54,\n\tNFSPROC4_CLNT_ALLOCATE = 55,\n\tNFSPROC4_CLNT_DEALLOCATE = 56,\n\tNFSPROC4_CLNT_ZERO_RANGE = 57,\n\tNFSPROC4_CLNT_LAYOUTSTATS = 58,\n\tNFSPROC4_CLNT_CLONE = 59,\n\tNFSPROC4_CLNT_COPY = 60,\n\tNFSPROC4_CLNT_OFFLOAD_CANCEL = 61,\n\tNFSPROC4_CLNT_LOOKUPP = 62,\n\tNFSPROC4_CLNT_LAYOUTERROR = 63,\n\tNFSPROC4_CLNT_COPY_NOTIFY = 64,\n\tNFSPROC4_CLNT_GETXATTR = 65,\n\tNFSPROC4_CLNT_SETXATTR = 66,\n\tNFSPROC4_CLNT_LISTXATTRS = 67,\n\tNFSPROC4_CLNT_REMOVEXATTR = 68,\n\tNFSPROC4_CLNT_READ_PLUS = 69,\n\tNFSPROC4_CLNT_OFFLOAD_STATUS = 70,\n};\n\nenum {\n\tNFS_DELEGATION_NEED_RECLAIM = 0,\n\tNFS_DELEGATION_RETURN_IF_CLOSED = 1,\n\tNFS_DELEGATION_REFERENCED = 2,\n\tNFS_DELEGATION_RETURNING = 3,\n\tNFS_DELEGATION_REVOKED = 4,\n\tNFS_DELEGATION_TEST_EXPIRED = 5,\n\tNFS_DELEGATION_DELEGTIME = 6,\n};\n\nenum {\n\tNFS_DEVICEID_INVALID = 0,\n\tNFS_DEVICEID_UNAVAILABLE = 1,\n\tNFS_DEVICEID_NOCACHE = 2,\n};\n\nenum {\n\tNFS_IOHDR_ERROR = 0,\n\tNFS_IOHDR_EOF = 1,\n\tNFS_IOHDR_REDO = 2,\n\tNFS_IOHDR_STAT = 3,\n\tNFS_IOHDR_RESEND_PNFS = 4,\n\tNFS_IOHDR_RESEND_MDS = 5,\n\tNFS_IOHDR_UNSTABLE_WRITES = 6,\n\tNFS_IOHDR_ODIRECT = 7,\n};\n\nenum {\n\tNFS_LAYOUT_RO_FAILED = 0,\n\tNFS_LAYOUT_RW_FAILED = 1,\n\tNFS_LAYOUT_BULK_RECALL = 2,\n\tNFS_LAYOUT_RETURN = 3,\n\tNFS_LAYOUT_RETURN_LOCK = 4,\n\tNFS_LAYOUT_RETURN_REQUESTED = 5,\n\tNFS_LAYOUT_INVALID_STID = 6,\n\tNFS_LAYOUT_FIRST_LAYOUTGET = 7,\n\tNFS_LAYOUT_INODE_FREEING = 8,\n\tNFS_LAYOUT_HASHED = 9,\n\tNFS_LAYOUT_DRAIN = 10,\n};\n\nenum {\n\tNFS_LSEG_VALID = 0,\n\tNFS_LSEG_ROC = 1,\n\tNFS_LSEG_LAYOUTCOMMIT = 2,\n\tNFS_LSEG_LAYOUTRETURN = 3,\n\tNFS_LSEG_UNAVAILABLE = 4,\n};\n\nenum {\n\tNFS_OWNER_RECLAIM_REBOOT = 0,\n\tNFS_OWNER_RECLAIM_NOGRACE = 1,\n};\n\nenum {\n\tNF_BPF_CT_OPTS_SZ = 16,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNHLT_CONFIG_TYPE_GENERIC = 0,\n\tNHLT_CONFIG_TYPE_MIC_ARRAY = 1,\n};\n\nenum {\n\tNHLT_MIC_ARRAY_2CH_SMALL = 10,\n\tNHLT_MIC_ARRAY_2CH_BIG = 11,\n\tNHLT_MIC_ARRAY_4CH_1ST_GEOM = 12,\n\tNHLT_MIC_ARRAY_4CH_L_SHAPED = 13,\n\tNHLT_MIC_ARRAY_4CH_2ND_GEOM = 14,\n\tNHLT_MIC_ARRAY_VENDOR_DEFINED = 15,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNLBL_CALIPSO_A_UNSPEC = 0,\n\tNLBL_CALIPSO_A_DOI = 1,\n\tNLBL_CALIPSO_A_MTYPE = 2,\n\t__NLBL_CALIPSO_A_MAX = 3,\n};\n\nenum {\n\tNLBL_CALIPSO_C_UNSPEC = 0,\n\tNLBL_CALIPSO_C_ADD = 1,\n\tNLBL_CALIPSO_C_REMOVE = 2,\n\tNLBL_CALIPSO_C_LIST = 3,\n\tNLBL_CALIPSO_C_LISTALL = 4,\n\t__NLBL_CALIPSO_C_MAX = 5,\n};\n\nenum {\n\tNLBL_CIPSOV4_A_UNSPEC = 0,\n\tNLBL_CIPSOV4_A_DOI = 1,\n\tNLBL_CIPSOV4_A_MTYPE = 2,\n\tNLBL_CIPSOV4_A_TAG = 3,\n\tNLBL_CIPSOV4_A_TAGLST = 4,\n\tNLBL_CIPSOV4_A_MLSLVLLOC = 5,\n\tNLBL_CIPSOV4_A_MLSLVLREM = 6,\n\tNLBL_CIPSOV4_A_MLSLVL = 7,\n\tNLBL_CIPSOV4_A_MLSLVLLST = 8,\n\tNLBL_CIPSOV4_A_MLSCATLOC = 9,\n\tNLBL_CIPSOV4_A_MLSCATREM = 10,\n\tNLBL_CIPSOV4_A_MLSCAT = 11,\n\tNLBL_CIPSOV4_A_MLSCATLST = 12,\n\t__NLBL_CIPSOV4_A_MAX = 13,\n};\n\nenum {\n\tNLBL_CIPSOV4_C_UNSPEC = 0,\n\tNLBL_CIPSOV4_C_ADD = 1,\n\tNLBL_CIPSOV4_C_REMOVE = 2,\n\tNLBL_CIPSOV4_C_LIST = 3,\n\tNLBL_CIPSOV4_C_LISTALL = 4,\n\t__NLBL_CIPSOV4_C_MAX = 5,\n};\n\nenum {\n\tNLBL_MGMT_A_UNSPEC = 0,\n\tNLBL_MGMT_A_DOMAIN = 1,\n\tNLBL_MGMT_A_PROTOCOL = 2,\n\tNLBL_MGMT_A_VERSION = 3,\n\tNLBL_MGMT_A_CV4DOI = 4,\n\tNLBL_MGMT_A_IPV6ADDR = 5,\n\tNLBL_MGMT_A_IPV6MASK = 6,\n\tNLBL_MGMT_A_IPV4ADDR = 7,\n\tNLBL_MGMT_A_IPV4MASK = 8,\n\tNLBL_MGMT_A_ADDRSELECTOR = 9,\n\tNLBL_MGMT_A_SELECTORLIST = 10,\n\tNLBL_MGMT_A_FAMILY = 11,\n\tNLBL_MGMT_A_CLPDOI = 12,\n\t__NLBL_MGMT_A_MAX = 13,\n};\n\nenum {\n\tNLBL_MGMT_C_UNSPEC = 0,\n\tNLBL_MGMT_C_ADD = 1,\n\tNLBL_MGMT_C_REMOVE = 2,\n\tNLBL_MGMT_C_LISTALL = 3,\n\tNLBL_MGMT_C_ADDDEF = 4,\n\tNLBL_MGMT_C_REMOVEDEF = 5,\n\tNLBL_MGMT_C_LISTDEF = 6,\n\tNLBL_MGMT_C_PROTOCOLS = 7,\n\tNLBL_MGMT_C_VERSION = 8,\n\t__NLBL_MGMT_C_MAX = 9,\n};\n\nenum {\n\tNLBL_UNLABEL_A_UNSPEC = 0,\n\tNLBL_UNLABEL_A_ACPTFLG = 1,\n\tNLBL_UNLABEL_A_IPV6ADDR = 2,\n\tNLBL_UNLABEL_A_IPV6MASK = 3,\n\tNLBL_UNLABEL_A_IPV4ADDR = 4,\n\tNLBL_UNLABEL_A_IPV4MASK = 5,\n\tNLBL_UNLABEL_A_IFACE = 6,\n\tNLBL_UNLABEL_A_SECCTX = 7,\n\t__NLBL_UNLABEL_A_MAX = 8,\n};\n\nenum {\n\tNLBL_UNLABEL_C_UNSPEC = 0,\n\tNLBL_UNLABEL_C_ACCEPT = 1,\n\tNLBL_UNLABEL_C_LIST = 2,\n\tNLBL_UNLABEL_C_STATICADD = 3,\n\tNLBL_UNLABEL_C_STATICREMOVE = 4,\n\tNLBL_UNLABEL_C_STATICLIST = 5,\n\tNLBL_UNLABEL_C_STATICADDDEF = 6,\n\tNLBL_UNLABEL_C_STATICREMOVEDEF = 7,\n\tNLBL_UNLABEL_C_STATICLISTDEF = 8,\n\t__NLBL_UNLABEL_C_MAX = 9,\n};\n\nenum {\n\tNLM_LCK_GRANTED = 0,\n\tNLM_LCK_DENIED = 1,\n\tNLM_LCK_DENIED_NOLOCKS = 2,\n\tNLM_LCK_BLOCKED = 3,\n\tNLM_LCK_DENIED_GRACE_PERIOD = 4,\n\tNLM_DEADLCK = 5,\n\tNLM_ROFS = 6,\n\tNLM_STALE_FH = 7,\n\tNLM_FBIG = 8,\n\tNLM_FAILED = 9,\n};\n\nenum {\n\tNMI_LOCAL = 0,\n\tNMI_UNKNOWN = 1,\n\tNMI_SERR = 2,\n\tNMI_IO_CHECK = 3,\n\tNMI_MAX = 4,\n};\n\nenum {\n\tNONE_FORCE_HPET_RESUME = 0,\n\tOLD_ICH_FORCE_HPET_RESUME = 1,\n\tICH_FORCE_HPET_RESUME = 2,\n\tVT8237_FORCE_HPET_RESUME = 3,\n\tNVIDIA_FORCE_HPET_RESUME = 4,\n\tATI_FORCE_HPET_RESUME = 5,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNSMPROC_NULL = 0,\n\tNSMPROC_STAT = 1,\n\tNSMPROC_MON = 2,\n\tNSMPROC_UNMON = 3,\n\tNSMPROC_UNMON_ALL = 4,\n\tNSMPROC_SIMU_CRASH = 5,\n\tNSMPROC_NOTIFY = 6,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 66,\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n\tNVMEM_LAYOUT_ADD = 5,\n\tNVMEM_LAYOUT_REMOVE = 6,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tNV_CROSSOVER_DETECTION_DISABLED = 0,\n\tNV_CROSSOVER_DETECTION_ENABLED = 1,\n};\n\nenum {\n\tNV_DMA_64BIT_DISABLED = 0,\n\tNV_DMA_64BIT_ENABLED = 1,\n};\n\nenum {\n\tNV_MSIX_INT_DISABLED = 0,\n\tNV_MSIX_INT_ENABLED = 1,\n};\n\nenum {\n\tNV_MSI_INT_DISABLED = 0,\n\tNV_MSI_INT_ENABLED = 1,\n};\n\nenum {\n\tNV_OPTIMIZATION_MODE_THROUGHPUT = 0,\n\tNV_OPTIMIZATION_MODE_CPU = 1,\n\tNV_OPTIMIZATION_MODE_DYNAMIC = 2,\n};\n\nenum {\n\tNvRegIrqStatus = 0,\n\tNvRegIrqMask = 4,\n\tNvRegUnknownSetupReg6 = 8,\n\tNvRegPollingInterval = 12,\n\tNvRegMSIMap0 = 32,\n\tNvRegMSIMap1 = 36,\n\tNvRegMSIIrqMask = 48,\n\tNvRegMisc1 = 128,\n\tNvRegMacReset = 52,\n\tNvRegTransmitterControl = 132,\n\tNvRegTransmitterStatus = 136,\n\tNvRegPacketFilterFlags = 140,\n\tNvRegOffloadConfig = 144,\n\tNvRegReceiverControl = 148,\n\tNvRegReceiverStatus = 152,\n\tNvRegSlotTime = 156,\n\tNvRegTxDeferral = 160,\n\tNvRegRxDeferral = 164,\n\tNvRegMacAddrA = 168,\n\tNvRegMacAddrB = 172,\n\tNvRegMulticastAddrA = 176,\n\tNvRegMulticastAddrB = 180,\n\tNvRegMulticastMaskA = 184,\n\tNvRegMulticastMaskB = 188,\n\tNvRegPhyInterface = 192,\n\tNvRegBackOffControl = 196,\n\tNvRegTxRingPhysAddr = 256,\n\tNvRegRxRingPhysAddr = 260,\n\tNvRegRingSizes = 264,\n\tNvRegTransmitPoll = 268,\n\tNvRegLinkSpeed = 272,\n\tNvRegUnknownSetupReg5 = 304,\n\tNvRegTxWatermark = 316,\n\tNvRegTxRxControl = 324,\n\tNvRegTxRingPhysAddrHigh = 328,\n\tNvRegRxRingPhysAddrHigh = 332,\n\tNvRegTxPauseFrame = 368,\n\tNvRegTxPauseFrameLimit = 372,\n\tNvRegMIIStatus = 384,\n\tNvRegMIIMask = 388,\n\tNvRegAdapterControl = 392,\n\tNvRegMIISpeed = 396,\n\tNvRegMIIControl = 400,\n\tNvRegMIIData = 404,\n\tNvRegTxUnicast = 416,\n\tNvRegTxMulticast = 420,\n\tNvRegTxBroadcast = 424,\n\tNvRegWakeUpFlags = 512,\n\tNvRegMgmtUnitGetVersion = 516,\n\tNvRegMgmtUnitVersion = 520,\n\tNvRegPowerCap = 616,\n\tNvRegPowerState = 620,\n\tNvRegMgmtUnitControl = 632,\n\tNvRegTxCnt = 640,\n\tNvRegTxZeroReXmt = 644,\n\tNvRegTxOneReXmt = 648,\n\tNvRegTxManyReXmt = 652,\n\tNvRegTxLateCol = 656,\n\tNvRegTxUnderflow = 660,\n\tNvRegTxLossCarrier = 664,\n\tNvRegTxExcessDef = 668,\n\tNvRegTxRetryErr = 672,\n\tNvRegRxFrameErr = 676,\n\tNvRegRxExtraByte = 680,\n\tNvRegRxLateCol = 684,\n\tNvRegRxRunt = 688,\n\tNvRegRxFrameTooLong = 692,\n\tNvRegRxOverflow = 696,\n\tNvRegRxFCSErr = 700,\n\tNvRegRxFrameAlignErr = 704,\n\tNvRegRxLenErr = 708,\n\tNvRegRxUnicast = 712,\n\tNvRegRxMulticast = 716,\n\tNvRegRxBroadcast = 720,\n\tNvRegTxDef = 724,\n\tNvRegTxFrame = 728,\n\tNvRegRxCnt = 732,\n\tNvRegTxPause = 736,\n\tNvRegRxPause = 740,\n\tNvRegRxDropFrame = 744,\n\tNvRegVlanControl = 768,\n\tNvRegMSIXMap0 = 992,\n\tNvRegMSIXMap1 = 996,\n\tNvRegMSIXIrqStatus = 1008,\n\tNvRegPowerState2 = 1536,\n};\n\nenum {\n\tOD_NORMAL_SAMPLE = 0,\n\tOD_SUB_SAMPLE = 1,\n};\n\nenum {\n\tOPTIMIZER_ST_IDLE = 0,\n\tOPTIMIZER_ST_KICKED = 1,\n\tOPTIMIZER_ST_FLUSHING = 2,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOpt_block = 0,\n\tOpt_check = 1,\n\tOpt_cruft = 2,\n\tOpt_gid = 3,\n\tOpt_ignore = 4,\n\tOpt_iocharset = 5,\n\tOpt_map = 6,\n\tOpt_mode = 7,\n\tOpt_nojoliet = 8,\n\tOpt_norock = 9,\n\tOpt_sb = 10,\n\tOpt_session = 11,\n\tOpt_uid = 12,\n\tOpt_unhide = 13,\n\tOpt_utf8 = 14,\n\tOpt_err = 15,\n\tOpt_nocompress = 16,\n\tOpt_hide = 17,\n\tOpt_showassoc = 18,\n\tOpt_dmode = 19,\n\tOpt_overriderockperm = 20,\n};\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid = 2,\n\tOpt_nogrpid = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb___2 = 6,\n\tOpt_nouid32 = 7,\n\tOpt_debug = 8,\n\tOpt_removed = 9,\n\tOpt_user_xattr = 10,\n\tOpt_acl = 11,\n\tOpt_auto_da_alloc = 12,\n\tOpt_noauto_da_alloc = 13,\n\tOpt_noload = 14,\n\tOpt_commit = 15,\n\tOpt_min_batch_time = 16,\n\tOpt_max_batch_time = 17,\n\tOpt_journal_dev = 18,\n\tOpt_journal_path = 19,\n\tOpt_journal_checksum = 20,\n\tOpt_journal_async_commit = 21,\n\tOpt_abort = 22,\n\tOpt_data_journal = 23,\n\tOpt_data_ordered = 24,\n\tOpt_data_writeback = 25,\n\tOpt_data_err_abort = 26,\n\tOpt_data_err_ignore = 27,\n\tOpt_test_dummy_encryption = 28,\n\tOpt_inlinecrypt = 29,\n\tOpt_usrjquota = 30,\n\tOpt_grpjquota = 31,\n\tOpt_quota = 32,\n\tOpt_noquota = 33,\n\tOpt_barrier = 34,\n\tOpt_nobarrier = 35,\n\tOpt_err___2 = 36,\n\tOpt_usrquota = 37,\n\tOpt_grpquota = 38,\n\tOpt_prjquota = 39,\n\tOpt_dax = 40,\n\tOpt_dax_always = 41,\n\tOpt_dax_inode = 42,\n\tOpt_dax_never = 43,\n\tOpt_stripe = 44,\n\tOpt_delalloc = 45,\n\tOpt_nodelalloc = 46,\n\tOpt_warn_on_error = 47,\n\tOpt_nowarn_on_error = 48,\n\tOpt_mblk_io_submit = 49,\n\tOpt_debug_want_extra_isize = 50,\n\tOpt_nomblk_io_submit = 51,\n\tOpt_block_validity = 52,\n\tOpt_noblock_validity = 53,\n\tOpt_inode_readahead_blks = 54,\n\tOpt_journal_ioprio = 55,\n\tOpt_dioread_nolock = 56,\n\tOpt_dioread_lock = 57,\n\tOpt_discard = 58,\n\tOpt_nodiscard = 59,\n\tOpt_init_itable = 60,\n\tOpt_noinit_itable = 61,\n\tOpt_max_dir_size_kb = 62,\n\tOpt_nojournal_checksum = 63,\n\tOpt_nombcache = 64,\n\tOpt_no_prefetch_block_bitmaps = 65,\n\tOpt_mb_optimize_scan = 66,\n\tOpt_errors = 67,\n\tOpt_data = 68,\n\tOpt_data_err = 69,\n\tOpt_jqfmt = 70,\n\tOpt_dax_type = 71,\n};\n\nenum {\n\tOpt_check___2 = 0,\n\tOpt_uid___2 = 1,\n\tOpt_gid___2 = 2,\n\tOpt_umask = 3,\n\tOpt_dmask = 4,\n\tOpt_fmask = 5,\n\tOpt_allow_utime = 6,\n\tOpt_codepage = 7,\n\tOpt_usefree = 8,\n\tOpt_nocase = 9,\n\tOpt_quiet = 10,\n\tOpt_showexec = 11,\n\tOpt_debug___2 = 12,\n\tOpt_immutable = 13,\n\tOpt_dots = 14,\n\tOpt_dotsOK = 15,\n\tOpt_charset = 16,\n\tOpt_shortname = 17,\n\tOpt_utf8___2 = 18,\n\tOpt_utf8_bool = 19,\n\tOpt_uni_xl = 20,\n\tOpt_uni_xl_bool = 21,\n\tOpt_nonumtail = 22,\n\tOpt_nonumtail_bool = 23,\n\tOpt_obsolete = 24,\n\tOpt_flush = 25,\n\tOpt_tz = 26,\n\tOpt_rodir = 27,\n\tOpt_errors___2 = 28,\n\tOpt_discard___2 = 29,\n\tOpt_nfs = 30,\n\tOpt_nfs_enum = 31,\n\tOpt_time_offset = 32,\n\tOpt_dos1xfloppy = 33,\n};\n\nenum {\n\tOpt_direct = 0,\n\tOpt_fd = 1,\n\tOpt_gid___3 = 2,\n\tOpt_ignore___2 = 3,\n\tOpt_indirect = 4,\n\tOpt_maxproto = 5,\n\tOpt_minproto = 6,\n\tOpt_offset = 7,\n\tOpt_pgrp = 8,\n\tOpt_strictexpire = 9,\n\tOpt_uid___3 = 10,\n};\n\nenum {\n\tOpt_err___3 = 0,\n\tOpt_enc = 1,\n\tOpt_hash = 2,\n};\n\nenum {\n\tOpt_error = -1,\n\tOpt_context = 0,\n\tOpt_defcontext = 1,\n\tOpt_fscontext = 2,\n\tOpt_rootcontext = 3,\n\tOpt_seclabel = 4,\n};\n\nenum {\n\tOpt_fatal_neterrors_default = 0,\n\tOpt_fatal_neterrors_enetunreach = 1,\n\tOpt_fatal_neterrors_none = 2,\n};\n\nenum {\n\tOpt_find_uid = 0,\n\tOpt_find_gid = 1,\n\tOpt_find_user = 2,\n\tOpt_find_group = 3,\n\tOpt_find_err = 4,\n};\n\nenum {\n\tOpt_local_lock_all = 0,\n\tOpt_local_lock_flock = 1,\n\tOpt_local_lock_none = 2,\n\tOpt_local_lock_posix = 3,\n};\n\nenum {\n\tOpt_lookupcache_all = 0,\n\tOpt_lookupcache_none = 1,\n\tOpt_lookupcache_positive = 2,\n};\n\nenum {\n\tOpt_sec_krb5 = 0,\n\tOpt_sec_krb5i = 1,\n\tOpt_sec_krb5p = 2,\n\tOpt_sec_lkey = 3,\n\tOpt_sec_lkeyi = 4,\n\tOpt_sec_lkeyp = 5,\n\tOpt_sec_none = 6,\n\tOpt_sec_spkm = 7,\n\tOpt_sec_spkmi = 8,\n\tOpt_sec_spkmp = 9,\n\tOpt_sec_sys = 10,\n\tnr__Opt_sec = 11,\n};\n\nenum {\n\tOpt_source = 0,\n\tOpt_debug___3 = 1,\n\tOpt_dfltuid = 2,\n\tOpt_dfltgid = 3,\n\tOpt_afid = 4,\n\tOpt_uname = 5,\n\tOpt_remotename = 6,\n\tOpt_cache = 7,\n\tOpt_cachetag = 8,\n\tOpt_nodevmap = 9,\n\tOpt_noxattr = 10,\n\tOpt_directio = 11,\n\tOpt_ignoreqv = 12,\n\tOpt_access = 13,\n\tOpt_posixacl = 14,\n\tOpt_locktimeout = 15,\n\tOpt_msize = 16,\n\tOpt_trans = 17,\n\tOpt_legacy = 18,\n\tOpt_version = 19,\n\tOpt_rfdno = 20,\n\tOpt_wfdno = 21,\n\tOpt_rq_depth = 22,\n\tOpt_sq_depth = 23,\n\tOpt_timeout = 24,\n\tOpt_port = 25,\n\tOpt_privport = 26,\n};\n\nenum {\n\tOpt_uid___4 = 0,\n\tOpt_gid___4 = 1,\n\tOpt_mode___2 = 2,\n};\n\nenum {\n\tOpt_uid___5 = 0,\n\tOpt_gid___5 = 1,\n\tOpt_mode___3 = 2,\n\tOpt_source___2 = 3,\n};\n\nenum {\n\tOpt_uid___6 = 0,\n\tOpt_gid___6 = 1,\n\tOpt_mode___4 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___4 = 6,\n};\n\nenum {\n\tOpt_vers_2 = 0,\n\tOpt_vers_3 = 1,\n\tOpt_vers_4 = 2,\n\tOpt_vers_4_0 = 3,\n\tOpt_vers_4_1 = 4,\n\tOpt_vers_4_2 = 5,\n};\n\nenum {\n\tOpt_write_lazy = 0,\n\tOpt_write_eager = 1,\n\tOpt_write_wait = 2,\n};\n\nenum {\n\tOpt_xprt_rdma = 0,\n\tOpt_xprt_rdma6 = 1,\n\tOpt_xprt_tcp = 2,\n\tOpt_xprt_tcp6 = 3,\n\tOpt_xprt_udp = 4,\n\tOpt_xprt_udp6 = 5,\n\tnr__Opt_xprt = 6,\n};\n\nenum {\n\tOpt_xprtsec_none = 0,\n\tOpt_xprtsec_tls = 1,\n\tOpt_xprtsec_mtls = 2,\n\tnr__Opt_xprtsec = 3,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPARSE_INVALID = 1,\n\tPARSE_NOT_LONGNAME = 2,\n\tPARSE_EOF = 3,\n};\n\nenum {\n\tPCI_DEV_REG1 = 64,\n\tPCI_DEV_REG2 = 68,\n\tPCI_DEV_STATUS = 124,\n\tPCI_DEV_REG3 = 128,\n\tPCI_DEV_REG4 = 132,\n\tPCI_DEV_REG5 = 136,\n\tPCI_CFG_REG_0 = 144,\n\tPCI_CFG_REG_1 = 148,\n\tPSM_CONFIG_REG0 = 152,\n\tPSM_CONFIG_REG1 = 156,\n\tPSM_CONFIG_REG2 = 352,\n\tPSM_CONFIG_REG3 = 356,\n\tPSM_CONFIG_REG4 = 360,\n\tPCI_LDO_CTRL = 188,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_BRIDGE_RESOURCES = 7,\n\tPCI_BRIDGE_RESOURCE_END = 10,\n\tPCI_NUM_RESOURCES = 11,\n\tDEVICE_COUNT_RESOURCE = 11,\n};\n\nenum {\n\tPCMCIA_IOPORT_0 = 0,\n\tPCMCIA_IOPORT_1 = 1,\n\tPCMCIA_IOMEM_0 = 2,\n\tPCMCIA_IOMEM_1 = 3,\n\tPCMCIA_IOMEM_2 = 4,\n\tPCMCIA_IOMEM_3 = 5,\n\tPCMCIA_NUM_RESOURCES = 6,\n};\n\nenum {\n\tPC_VAUX_ENA = 128,\n\tPC_VAUX_DIS = 64,\n\tPC_VCC_ENA = 32,\n\tPC_VCC_DIS = 16,\n\tPC_VAUX_ON = 8,\n\tPC_VAUX_OFF = 4,\n\tPC_VCC_ON = 2,\n\tPC_VCC_OFF = 1,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPERF_BR_SPEC_NA = 0,\n\tPERF_BR_SPEC_WRONG_PATH = 1,\n\tPERF_BR_NON_SPEC_CORRECT_PATH = 2,\n\tPERF_BR_SPEC_CORRECT_PATH = 3,\n\tPERF_BR_SPEC_MAX = 4,\n};\n\nenum {\n\tPERF_BR_UNKNOWN = 0,\n\tPERF_BR_COND = 1,\n\tPERF_BR_UNCOND = 2,\n\tPERF_BR_IND = 3,\n\tPERF_BR_CALL = 4,\n\tPERF_BR_IND_CALL = 5,\n\tPERF_BR_RET = 6,\n\tPERF_BR_SYSCALL = 7,\n\tPERF_BR_SYSRET = 8,\n\tPERF_BR_COND_CALL = 9,\n\tPERF_BR_COND_RET = 10,\n\tPERF_BR_ERET = 11,\n\tPERF_BR_IRQ = 12,\n\tPERF_BR_SERROR = 13,\n\tPERF_BR_NO_TX = 14,\n\tPERF_BR_EXTEND_ABI = 15,\n\tPERF_BR_MAX = 16,\n};\n\nenum {\n\tPERF_GROUP_OAG = 0,\n\tPERF_GROUP_OAM_SAMEDIA_0 = 0,\n\tPERF_GROUP_MAX = 1,\n\tPERF_GROUP_INVALID = 4294967295,\n};\n\nenum {\n\tPERF_TXN_ELISION = 1ULL,\n\tPERF_TXN_TRANSACTION = 2ULL,\n\tPERF_TXN_SYNC = 4ULL,\n\tPERF_TXN_ASYNC = 8ULL,\n\tPERF_TXN_RETRY = 16ULL,\n\tPERF_TXN_CONFLICT = 32ULL,\n\tPERF_TXN_CAPACITY_WRITE = 64ULL,\n\tPERF_TXN_CAPACITY_READ = 128ULL,\n\tPERF_TXN_MAX = 256ULL,\n\tPERF_TXN_ABORT_MASK = 18446744069414584320ULL,\n\tPERF_TXN_ABORT_SHIFT = 32ULL,\n};\n\nenum {\n\tPERF_X86_EVENT_PEBS_LDLAT = 1,\n\tPERF_X86_EVENT_PEBS_ST = 2,\n\tPERF_X86_EVENT_PEBS_ST_HSW = 4,\n\tPERF_X86_EVENT_PEBS_LD_HSW = 8,\n\tPERF_X86_EVENT_PEBS_NA_HSW = 16,\n\tPERF_X86_EVENT_EXCL = 32,\n\tPERF_X86_EVENT_DYNAMIC = 64,\n\tPERF_X86_EVENT_PEBS_CNTR = 128,\n\tPERF_X86_EVENT_EXCL_ACCT = 256,\n\tPERF_X86_EVENT_AUTO_RELOAD = 512,\n\tPERF_X86_EVENT_LARGE_PEBS = 1024,\n\tPERF_X86_EVENT_PEBS_VIA_PT = 2048,\n\tPERF_X86_EVENT_PAIR = 4096,\n\tPERF_X86_EVENT_LBR_SELECT = 8192,\n\tPERF_X86_EVENT_TOPDOWN = 16384,\n\tPERF_X86_EVENT_PEBS_STLAT = 32768,\n\tPERF_X86_EVENT_AMD_BRS = 65536,\n\tPERF_X86_EVENT_PEBS_LAT_HYBRID = 131072,\n\tPERF_X86_EVENT_NEEDS_BRANCH_STACK = 262144,\n\tPERF_X86_EVENT_BRANCH_COUNTERS = 524288,\n\tPERF_X86_EVENT_ACR = 1048576,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPEX_RD_ACCESS = -2147483648,\n\tPEX_DB_ACCESS = 1073741824,\n};\n\nenum {\n\tPG_BUSY = 0,\n\tPG_MAPPED = 1,\n\tPG_FOLIO = 2,\n\tPG_CLEAN = 3,\n\tPG_COMMIT_TO_DS = 4,\n\tPG_INODE_REF = 5,\n\tPG_HEADLOCK = 6,\n\tPG_TEARDOWN = 7,\n\tPG_UNLOCKPAGE = 8,\n\tPG_UPTODATE = 9,\n\tPG_WB_END = 10,\n\tPG_REMOVE = 11,\n\tPG_CONTENDED1 = 12,\n\tPG_CONTENDED2 = 13,\n};\n\nenum {\n\tPHY_ADDR_MARV = 0,\n};\n\nenum {\n\tPHY_AN_NXT_PG = 32768,\n\tPHY_AN_ACK = 16384,\n\tPHY_AN_RF = 8192,\n\tPHY_AN_PAUSE_ASYM = 2048,\n\tPHY_AN_PAUSE_CAP = 1024,\n\tPHY_AN_100BASE4 = 512,\n\tPHY_AN_100FULL = 256,\n\tPHY_AN_100HALF = 128,\n\tPHY_AN_10FULL = 64,\n\tPHY_AN_10HALF = 32,\n\tPHY_AN_CSMA = 1,\n\tPHY_AN_SEL = 31,\n\tPHY_AN_FULL = 321,\n\tPHY_AN_ALL = 480,\n};\n\nenum {\n\tPHY_CT_RESET = 32768,\n\tPHY_CT_LOOP = 16384,\n\tPHY_CT_SPS_LSB = 8192,\n\tPHY_CT_ANE = 4096,\n\tPHY_CT_PDOWN = 2048,\n\tPHY_CT_ISOL = 1024,\n\tPHY_CT_RE_CFG = 512,\n\tPHY_CT_DUP_MD = 256,\n\tPHY_CT_COL_TST = 128,\n\tPHY_CT_SPS_MSB = 64,\n};\n\nenum {\n\tPHY_CT_SP1000 = 64,\n\tPHY_CT_SP100 = 8192,\n\tPHY_CT_SP10 = 0,\n};\n\nenum {\n\tPHY_MARV_CTRL = 0,\n\tPHY_MARV_STAT = 1,\n\tPHY_MARV_ID0 = 2,\n\tPHY_MARV_ID1 = 3,\n\tPHY_MARV_AUNE_ADV = 4,\n\tPHY_MARV_AUNE_LP = 5,\n\tPHY_MARV_AUNE_EXP = 6,\n\tPHY_MARV_NEPG = 7,\n\tPHY_MARV_NEPG_LP = 8,\n\tPHY_MARV_1000T_CTRL = 9,\n\tPHY_MARV_1000T_STAT = 10,\n\tPHY_MARV_EXT_STAT = 15,\n\tPHY_MARV_PHY_CTRL = 16,\n\tPHY_MARV_PHY_STAT = 17,\n\tPHY_MARV_INT_MASK = 18,\n\tPHY_MARV_INT_STAT = 19,\n\tPHY_MARV_EXT_CTRL = 20,\n\tPHY_MARV_RXE_CNT = 21,\n\tPHY_MARV_EXT_ADR = 22,\n\tPHY_MARV_PORT_IRQ = 23,\n\tPHY_MARV_LED_CTRL = 24,\n\tPHY_MARV_LED_OVER = 25,\n\tPHY_MARV_EXT_CTRL_2 = 26,\n\tPHY_MARV_EXT_P_STAT = 27,\n\tPHY_MARV_CABLE_DIAG = 28,\n\tPHY_MARV_PAGE_ADDR = 29,\n\tPHY_MARV_PAGE_DATA = 30,\n\tPHY_MARV_FE_LED_PAR = 22,\n\tPHY_MARV_FE_LED_SER = 23,\n\tPHY_MARV_FE_VCT_TX = 26,\n\tPHY_MARV_FE_VCT_RX = 27,\n\tPHY_MARV_FE_SPEC_2 = 28,\n};\n\nenum {\n\tPHY_MARV_ID0_VAL = 321,\n\tPHY_BCOM_ID1_A1 = 24641,\n\tPHY_BCOM_ID1_B2 = 24643,\n\tPHY_BCOM_ID1_C0 = 24644,\n\tPHY_BCOM_ID1_C5 = 24647,\n\tPHY_MARV_ID1_B0 = 3107,\n\tPHY_MARV_ID1_B2 = 3109,\n\tPHY_MARV_ID1_C2 = 3266,\n\tPHY_MARV_ID1_Y2 = 3217,\n\tPHY_MARV_ID1_FE = 3203,\n\tPHY_MARV_ID1_ECU = 3248,\n};\n\nenum {\n\tPHY_M_1000C_TEST = 57344,\n\tPHY_M_1000C_MSE = 4096,\n\tPHY_M_1000C_MSC = 2048,\n\tPHY_M_1000C_MPD = 1024,\n\tPHY_M_1000C_AFD = 512,\n\tPHY_M_1000C_AHD = 256,\n};\n\nenum {\n\tPHY_M_AN_ASP_X = 256,\n\tPHY_M_AN_PC_X = 128,\n\tPHY_M_AN_1000X_AHD = 64,\n\tPHY_M_AN_1000X_AFD = 32,\n};\n\nenum {\n\tPHY_M_AN_NXT_PG = 32768,\n\tPHY_M_AN_ACK = 16384,\n\tPHY_M_AN_RF = 8192,\n\tPHY_M_AN_ASP = 2048,\n\tPHY_M_AN_PC = 1024,\n\tPHY_M_AN_100_T4 = 512,\n\tPHY_M_AN_100_FD = 256,\n\tPHY_M_AN_100_HD = 128,\n\tPHY_M_AN_10_FD = 64,\n\tPHY_M_AN_10_HD = 32,\n\tPHY_M_AN_SEL_MSK = 496,\n};\n\nenum {\n\tPHY_M_EC_ENA_BC_EXT = 32768,\n\tPHY_M_EC_ENA_LIN_LB = 16384,\n\tPHY_M_EC_DIS_LINK_P = 4096,\n\tPHY_M_EC_M_DSC_MSK = 3072,\n\tPHY_M_EC_S_DSC_MSK = 768,\n\tPHY_M_EC_M_DSC_MSK2 = 3584,\n\tPHY_M_EC_DOWN_S_ENA = 256,\n\tPHY_M_EC_RX_TIM_CT = 128,\n\tPHY_M_EC_MAC_S_MSK = 112,\n\tPHY_M_EC_FIB_AN_ENA = 8,\n\tPHY_M_EC_DTE_D_ENA = 4,\n\tPHY_M_EC_TX_TIM_CT = 2,\n\tPHY_M_EC_TRANS_DIS = 1,\n\tPHY_M_10B_TE_ENABLE = 128,\n};\n\nenum {\n\tPHY_M_FC_AUTO_SEL = 32768,\n\tPHY_M_FC_AN_REG_ACC = 16384,\n\tPHY_M_FC_RESOLUTION = 8192,\n\tPHY_M_SER_IF_AN_BP = 4096,\n\tPHY_M_SER_IF_BP_ST = 2048,\n\tPHY_M_IRQ_POLARITY = 1024,\n\tPHY_M_DIS_AUT_MED = 512,\n\tPHY_M_UNDOC1 = 128,\n\tPHY_M_DTE_POW_STAT = 16,\n\tPHY_M_MODE_MASK = 15,\n};\n\nenum {\n\tPHY_M_FELP_LED2_MSK = 3840,\n\tPHY_M_FELP_LED1_MSK = 240,\n\tPHY_M_FELP_LED0_MSK = 15,\n};\n\nenum {\n\tPHY_M_FESC_DIS_WAIT = 4,\n\tPHY_M_FESC_ENA_MCLK = 2,\n\tPHY_M_FESC_SEL_CL_A = 1,\n};\n\nenum {\n\tPHY_M_FIB_FORCE_LNK = 1024,\n\tPHY_M_FIB_SIGD_POL = 512,\n\tPHY_M_FIB_TX_DIS = 8,\n};\n\nenum {\n\tPHY_M_IS_AN_ERROR = 32768,\n\tPHY_M_IS_LSP_CHANGE = 16384,\n\tPHY_M_IS_DUP_CHANGE = 8192,\n\tPHY_M_IS_AN_PR = 4096,\n\tPHY_M_IS_AN_COMPL = 2048,\n\tPHY_M_IS_LST_CHANGE = 1024,\n\tPHY_M_IS_SYMB_ERROR = 512,\n\tPHY_M_IS_FALSE_CARR = 256,\n\tPHY_M_IS_FIFO_ERROR = 128,\n\tPHY_M_IS_MDI_CHANGE = 64,\n\tPHY_M_IS_DOWNSH_DET = 32,\n\tPHY_M_IS_END_CHANGE = 16,\n\tPHY_M_IS_DTE_CHANGE = 4,\n\tPHY_M_IS_POL_CHANGE = 2,\n\tPHY_M_IS_JABBER = 1,\n\tPHY_M_DEF_MSK = 25600,\n\tPHY_M_AN_MSK = 34816,\n};\n\nenum {\n\tPHY_M_LEDC_DIS_LED = 32768,\n\tPHY_M_LEDC_PULS_MSK = 28672,\n\tPHY_M_LEDC_F_INT = 2048,\n\tPHY_M_LEDC_BL_R_MSK = 1792,\n\tPHY_M_LEDC_DP_C_LSB = 128,\n\tPHY_M_LEDC_TX_C_LSB = 64,\n\tPHY_M_LEDC_LK_C_MSK = 56,\n};\n\nenum {\n\tPHY_M_LEDC_LINK_MSK = 24,\n\tPHY_M_LEDC_DP_CTRL = 4,\n\tPHY_M_LEDC_DP_C_MSB = 4,\n\tPHY_M_LEDC_RX_CTRL = 2,\n\tPHY_M_LEDC_TX_CTRL = 1,\n\tPHY_M_LEDC_TX_C_MSB = 1,\n};\n\nenum {\n\tPHY_M_LEDC_LOS_MSK = 61440,\n\tPHY_M_LEDC_INIT_MSK = 3840,\n\tPHY_M_LEDC_STA1_MSK = 240,\n\tPHY_M_LEDC_STA0_MSK = 15,\n};\n\nenum {\n\tPHY_M_MAC_MD_MSK = 896,\n\tPHY_M_MAC_GMIF_PUP = 8,\n\tPHY_M_MAC_MD_AUTO = 3,\n\tPHY_M_MAC_MD_COPPER = 5,\n\tPHY_M_MAC_MD_1000BX = 7,\n};\n\nenum {\n\tPHY_M_PC_COP_TX_DIS = 8,\n\tPHY_M_PC_POW_D_ENA = 4,\n};\n\nenum {\n\tPHY_M_PC_DIS_LINK_Pa = 32768,\n\tPHY_M_PC_DSC_MSK = 28672,\n\tPHY_M_PC_DOWN_S_ENA = 2048,\n};\n\nenum {\n\tPHY_M_PC_ENA_DTE_DT = 32768,\n\tPHY_M_PC_ENA_ENE_DT = 16384,\n\tPHY_M_PC_DIS_NLP_CK = 8192,\n\tPHY_M_PC_ENA_LIP_NP = 4096,\n\tPHY_M_PC_DIS_NLP_GN = 2048,\n\tPHY_M_PC_DIS_SCRAMB = 512,\n\tPHY_M_PC_DIS_FEFI = 256,\n\tPHY_M_PC_SH_TP_SEL = 64,\n\tPHY_M_PC_RX_FD_MSK = 12,\n};\n\nenum {\n\tPHY_M_PC_MAN_MDI = 0,\n\tPHY_M_PC_MAN_MDIX = 1,\n\tPHY_M_PC_ENA_AUTO = 3,\n};\n\nenum {\n\tPHY_M_PC_TX_FFD_MSK = 49152,\n\tPHY_M_PC_RX_FFD_MSK = 12288,\n\tPHY_M_PC_ASS_CRS_TX = 2048,\n\tPHY_M_PC_FL_GOOD = 1024,\n\tPHY_M_PC_EN_DET_MSK = 768,\n\tPHY_M_PC_ENA_EXT_D = 128,\n\tPHY_M_PC_MDIX_MSK = 96,\n\tPHY_M_PC_DIS_125CLK = 16,\n\tPHY_M_PC_MAC_POW_UP = 8,\n\tPHY_M_PC_SQE_T_ENA = 4,\n\tPHY_M_PC_POL_R_DIS = 2,\n\tPHY_M_PC_DIS_JABBER = 1,\n};\n\nenum {\n\tPHY_M_POLC_LS1M_MSK = 61440,\n\tPHY_M_POLC_IS0M_MSK = 3840,\n\tPHY_M_POLC_LOS_MSK = 192,\n\tPHY_M_POLC_INIT_MSK = 48,\n\tPHY_M_POLC_STA1_MSK = 12,\n\tPHY_M_POLC_STA0_MSK = 3,\n};\n\nenum {\n\tPHY_M_PS_SPEED_MSK = 49152,\n\tPHY_M_PS_SPEED_1000 = 32768,\n\tPHY_M_PS_SPEED_100 = 16384,\n\tPHY_M_PS_SPEED_10 = 0,\n\tPHY_M_PS_FULL_DUP = 8192,\n\tPHY_M_PS_PAGE_REC = 4096,\n\tPHY_M_PS_SPDUP_RES = 2048,\n\tPHY_M_PS_LINK_UP = 1024,\n\tPHY_M_PS_CABLE_MSK = 896,\n\tPHY_M_PS_MDI_X_STAT = 64,\n\tPHY_M_PS_DOWNS_STAT = 32,\n\tPHY_M_PS_ENDET_STAT = 16,\n\tPHY_M_PS_TX_P_EN = 8,\n\tPHY_M_PS_RX_P_EN = 4,\n\tPHY_M_PS_POL_REV = 2,\n\tPHY_M_PS_JABBER = 1,\n};\n\nenum {\n\tPHY_M_P_NO_PAUSE_X = 0,\n\tPHY_M_P_SYM_MD_X = 128,\n\tPHY_M_P_ASYM_MD_X = 256,\n\tPHY_M_P_BOTH_MD_X = 384,\n};\n\nenum {\n\tPIIX_IOCFG = 84,\n\tICH5_PMR = 144,\n\tICH5_PCS = 146,\n\tPIIX_SIDPR_BAR = 5,\n\tPIIX_SIDPR_LEN = 16,\n\tPIIX_SIDPR_IDX = 0,\n\tPIIX_SIDPR_DATA = 4,\n\tPIIX_FLAG_CHECKINTR = 268435456,\n\tPIIX_FLAG_SIDPR = 536870912,\n\tPIIX_PATA_FLAGS = 1,\n\tPIIX_SATA_FLAGS = 268435458,\n\tPIIX_FLAG_PIO16 = 1073741824,\n\tPIIX_80C_PRI = 48,\n\tPIIX_80C_SEC = 192,\n\tP0 = 0,\n\tP1 = 1,\n\tP2 = 2,\n\tP3 = 3,\n\tIDE = -1,\n\tNA = -2,\n\tRV = -3,\n\tPIIX_AHCI_DEVICE = 6,\n\tPIIX_HOST_BROKEN_SUSPEND = 16777216,\n};\n\nenum {\n\tPIM_TYPE_HELLO = 0,\n\tPIM_TYPE_REGISTER = 1,\n\tPIM_TYPE_REGISTER_STOP = 2,\n\tPIM_TYPE_JOIN_PRUNE = 3,\n\tPIM_TYPE_BOOTSTRAP = 4,\n\tPIM_TYPE_ASSERT = 5,\n\tPIM_TYPE_GRAFT = 6,\n\tPIM_TYPE_GRAFT_ACK = 7,\n\tPIM_TYPE_CANDIDATE_RP_ADV = 8,\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = -1,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nenum {\n\tPNFS_BDEV_REGISTERED = 0,\n};\n\nenum {\n\tPOLICYDB_CAP_NETPEER = 0,\n\tPOLICYDB_CAP_OPENPERM = 1,\n\tPOLICYDB_CAP_EXTSOCKCLASS = 2,\n\tPOLICYDB_CAP_ALWAYSNETWORK = 3,\n\tPOLICYDB_CAP_CGROUPSECLABEL = 4,\n\tPOLICYDB_CAP_NNP_NOSUID_TRANSITION = 5,\n\tPOLICYDB_CAP_GENFS_SECLABEL_SYMLINKS = 6,\n\tPOLICYDB_CAP_IOCTL_SKIP_CLOEXEC = 7,\n\tPOLICYDB_CAP_USERSPACE_INITIAL_CONTEXT = 8,\n\tPOLICYDB_CAP_NETLINK_XPERM = 9,\n\tPOLICYDB_CAP_NETIF_WILDCARD = 10,\n\tPOLICYDB_CAP_GENFS_SECLABEL_WILDCARD = 11,\n\tPOLICYDB_CAP_FUNCTIONFS_SECLABEL = 12,\n\tPOLICYDB_CAP_MEMFD_CLASS = 13,\n\tPOLICYDB_CAP_BPF_TOKEN_PERMS = 14,\n\t__POLICYDB_CAP_MAX = 15,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPOS_FIX_AUTO = 0,\n\tPOS_FIX_LPIB = 1,\n\tPOS_FIX_POSBUF = 2,\n\tPOS_FIX_VIACOMBO = 3,\n\tPOS_FIX_COMBO = 4,\n\tPOS_FIX_SKL = 5,\n\tPOS_FIX_FIFO = 6,\n};\n\nenum {\n\tPOWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_LOW = 2,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_FULL = 5,\n};\n\nenum {\n\tPOWER_SUPPLY_HEALTH_UNKNOWN = 0,\n\tPOWER_SUPPLY_HEALTH_GOOD = 1,\n\tPOWER_SUPPLY_HEALTH_OVERHEAT = 2,\n\tPOWER_SUPPLY_HEALTH_DEAD = 3,\n\tPOWER_SUPPLY_HEALTH_OVERVOLTAGE = 4,\n\tPOWER_SUPPLY_HEALTH_UNDERVOLTAGE = 5,\n\tPOWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 6,\n\tPOWER_SUPPLY_HEALTH_COLD = 7,\n\tPOWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 8,\n\tPOWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 9,\n\tPOWER_SUPPLY_HEALTH_OVERCURRENT = 10,\n\tPOWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 11,\n\tPOWER_SUPPLY_HEALTH_WARM = 12,\n\tPOWER_SUPPLY_HEALTH_COOL = 13,\n\tPOWER_SUPPLY_HEALTH_HOT = 14,\n\tPOWER_SUPPLY_HEALTH_NO_BATTERY = 15,\n\tPOWER_SUPPLY_HEALTH_BLOWN_FUSE = 16,\n\tPOWER_SUPPLY_HEALTH_CELL_IMBALANCE = 17,\n};\n\nenum {\n\tPOWER_SUPPLY_SCOPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_SCOPE_SYSTEM = 1,\n\tPOWER_SUPPLY_SCOPE_DEVICE = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_STATUS_UNKNOWN = 0,\n\tPOWER_SUPPLY_STATUS_CHARGING = 1,\n\tPOWER_SUPPLY_STATUS_DISCHARGING = 2,\n\tPOWER_SUPPLY_STATUS_NOT_CHARGING = 3,\n\tPOWER_SUPPLY_STATUS_FULL = 4,\n};\n\nenum {\n\tPOWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,\n\tPOWER_SUPPLY_TECHNOLOGY_NiMH = 1,\n\tPOWER_SUPPLY_TECHNOLOGY_LION = 2,\n\tPOWER_SUPPLY_TECHNOLOGY_LIPO = 3,\n\tPOWER_SUPPLY_TECHNOLOGY_LiFe = 4,\n\tPOWER_SUPPLY_TECHNOLOGY_NiCd = 5,\n\tPOWER_SUPPLY_TECHNOLOGY_LiMn = 6,\n};\n\nenum {\n\tPREFIX_UNSPEC = 0,\n\tPREFIX_ADDRESS = 1,\n\tPREFIX_CACHEINFO = 2,\n\t__PREFIX_MAX = 3,\n};\n\nenum {\n\tPREF_UNIT_OP_ON = 8,\n\tPREF_UNIT_OP_OFF = 4,\n\tPREF_UNIT_RST_CLR = 2,\n\tPREF_UNIT_RST_SET = 1,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROCMON_0_85V_DOT_0 = 0,\n\tPROCMON_0_95V_DOT_0 = 1,\n\tPROCMON_0_95V_DOT_1 = 2,\n\tPROCMON_1_05V_DOT_0 = 3,\n\tPROCMON_1_05V_DOT_1 = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tPSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 240,\n\tPSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4,\n\tPSM_CONFIG_REG4_DEBUG_TIMER = 2,\n\tPSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1,\n};\n\nenum {\n\tPSS = 0,\n\tPPC = 1,\n};\n\nenum {\n\tPT_FEAT_AMDV1_ENCRYPT_TABLES = 6,\n\tPT_FEAT_AMDV1_FORCE_COHERENCE = 7,\n};\n\nenum {\n\tPT_FEAT_VTDSS_FORCE_COHERENCE = 6,\n\tPT_FEAT_VTDSS_FORCE_WRITEABLE = 7,\n};\n\nenum {\n\tPT_FEAT_X86_64_AMD_ENCRYPT_TABLES = 6,\n};\n\nenum {\n\tPT_ITEM_WORD_SIZE = 8ULL,\n\tPT_MAX_VA_ADDRESS_LG2 = 64ULL,\n\tPT_MAX_OUTPUT_ADDRESS_LG2 = 52ULL,\n\tPT_MAX_TOP_LEVEL = 5ULL,\n\tPT_GRANULE_LG2SZ = 12ULL,\n\tPT_TABLEMEM_LG2SZ = 12ULL,\n\tPT_TOP_PHYS_MASK = 4503599627366400ULL,\n};\n\nenum {\n\tPT_MAX_OUTPUT_ADDRESS_LG2___2 = 52ULL,\n\tPT_MAX_VA_ADDRESS_LG2___2 = 57ULL,\n\tPT_ITEM_WORD_SIZE___2 = 8ULL,\n\tPT_MAX_TOP_LEVEL___2 = 4ULL,\n\tPT_GRANULE_LG2SZ___2 = 12ULL,\n\tPT_TABLEMEM_LG2SZ___2 = 12ULL,\n\tPT_TOP_PHYS_MASK___2 = 18446744073709547520ULL,\n};\n\nenum {\n\tPT_MAX_OUTPUT_ADDRESS_LG2___3 = 52ULL,\n\tPT_MAX_VA_ADDRESS_LG2___3 = 57ULL,\n\tPT_ITEM_WORD_SIZE___3 = 8ULL,\n\tPT_MAX_TOP_LEVEL___3 = 4ULL,\n\tPT_GRANULE_LG2SZ___3 = 12ULL,\n\tPT_TABLEMEM_LG2SZ___3 = 12ULL,\n\tPT_TOP_PHYS_MASK___3 = 4503599627366400ULL,\n};\n\nenum {\n\tPT_TOP_LEVEL_BITS = 3,\n\tPT_TOP_LEVEL_MASK = 7,\n};\n\nenum {\n\tPT_VADDR_MAX = 18446744073709551615ULL,\n\tPT_VADDR_MAX_LG2 = 64ULL,\n\tPT_OADDR_MAX = 18446744073709551615ULL,\n\tPT_OADDR_MAX_LG2 = 64ULL,\n};\n\nenum {\n\tPULS_NO_STR = 0,\n\tPULS_21MS = 1,\n\tPULS_42MS = 2,\n\tPULS_84MS = 3,\n\tPULS_170MS = 4,\n\tPULS_340MS = 5,\n\tPULS_670MS = 6,\n\tPULS_1300MS = 7,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQIF_BLIMITS_B = 0,\n\tQIF_SPACE_B = 1,\n\tQIF_ILIMITS_B = 2,\n\tQIF_INODES_B = 3,\n\tQIF_BTIME_B = 4,\n\tQIF_ITIME_B = 5,\n};\n\nenum {\n\tQI_FREE = 0,\n\tQI_IN_USE = 1,\n\tQI_DONE = 2,\n\tQI_ABORT = 3,\n};\n\nenum {\n\tQOS_ENABLE = 0,\n\tQOS_CTRL = 1,\n\tNR_QOS_CTRL_PARAMS = 2,\n};\n\nenum {\n\tQOS_RPPM = 0,\n\tQOS_RLAT = 1,\n\tQOS_WPPM = 2,\n\tQOS_WLAT = 3,\n\tQOS_MIN = 4,\n\tQOS_MAX = 5,\n\tNR_QOS_PARAMS = 6,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQUIRK_IGNORE_CHECKSUM = 0,\n};\n\nenum {\n\tQUOTA_NL_A_UNSPEC = 0,\n\tQUOTA_NL_A_QTYPE = 1,\n\tQUOTA_NL_A_EXCESS_ID = 2,\n\tQUOTA_NL_A_WARNING = 3,\n\tQUOTA_NL_A_DEV_MAJOR = 4,\n\tQUOTA_NL_A_DEV_MINOR = 5,\n\tQUOTA_NL_A_CAUSED_ID = 6,\n\tQUOTA_NL_A_PAD = 7,\n\t__QUOTA_NL_A_MAX = 8,\n};\n\nenum {\n\tQUOTA_NL_C_UNSPEC = 0,\n\tQUOTA_NL_C_WARNING = 1,\n\t__QUOTA_NL_C_MAX = 2,\n};\n\nenum {\n\tQ_R1 = 0,\n\tQ_R2 = 128,\n\tQ_XS1 = 512,\n\tQ_XA1 = 640,\n\tQ_XS2 = 768,\n\tQ_XA2 = 896,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tRB_ADD_STAMP_NONE = 0,\n\tRB_ADD_STAMP_EXTEND = 2,\n\tRB_ADD_STAMP_ABSOLUTE = 4,\n\tRB_ADD_STAMP_FORCE = 8,\n};\n\nenum {\n\tRB_CTX_TRANSITION = 0,\n\tRB_CTX_NMI = 1,\n\tRB_CTX_IRQ = 2,\n\tRB_CTX_SOFTIRQ = 3,\n\tRB_CTX_NORMAL = 4,\n\tRB_CTX_MAX = 5,\n};\n\nenum {\n\tRB_ENA_STFWD = 32,\n\tRB_DIS_STFWD = 16,\n\tRB_ENA_OP_MD = 8,\n\tRB_DIS_OP_MD = 4,\n\tRB_RST_CLR = 2,\n\tRB_RST_SET = 1,\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nenum {\n\tRB_START = 0,\n\tRB_END = 4,\n\tRB_WP = 8,\n\tRB_RP = 12,\n\tRB_RX_UTPP = 16,\n\tRB_RX_LTPP = 20,\n\tRB_RX_UTHP = 24,\n\tRB_RX_LTHP = 28,\n\tRB_PC = 32,\n\tRB_LEV = 36,\n\tRB_CTRL = 40,\n\tRB_TST1 = 41,\n\tRB_TST2 = 42,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tRELAY_STATS_BUF_FULL = 1,\n\tRELAY_STATS_WRT_BIG = 2,\n\tRELAY_STATS_LAST = 2,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 5000,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRES_USAGE = 0,\n\tRES_RSVD_USAGE = 1,\n\tRES_LIMIT = 2,\n\tRES_RSVD_LIMIT = 3,\n\tRES_MAX_USAGE = 4,\n\tRES_RSVD_MAX_USAGE = 5,\n\tRES_FAILCNT = 6,\n\tRES_RSVD_FAILCNT = 7,\n};\n\nenum {\n\tRI_CLR_RD_PERR = 512,\n\tRI_CLR_WR_PERR = 256,\n\tRI_RST_CLR = 2,\n\tRI_RST_SET = 1,\n};\n\nenum {\n\tRPCAUTH_lockd = 0,\n\tRPCAUTH_mount = 1,\n\tRPCAUTH_nfs = 2,\n\tRPCAUTH_portmap = 3,\n\tRPCAUTH_statd = 4,\n\tRPCAUTH_nfsd4_cb = 5,\n\tRPCAUTH_cache = 6,\n\tRPCAUTH_nfsd = 7,\n\tRPCAUTH_RootEOF = 8,\n};\n\nenum {\n\tRPCBPROC_NULL = 0,\n\tRPCBPROC_SET = 1,\n\tRPCBPROC_UNSET = 2,\n\tRPCBPROC_GETPORT = 3,\n\tRPCBPROC_GETADDR = 3,\n\tRPCBPROC_DUMP = 4,\n\tRPCBPROC_CALLIT = 5,\n\tRPCBPROC_BCAST = 5,\n\tRPCBPROC_GETTIME = 6,\n\tRPCBPROC_UADDR2TADDR = 7,\n\tRPCBPROC_TADDR2UADDR = 8,\n\tRPCBPROC_GETVERSADDR = 9,\n\tRPCBPROC_INDIRECT = 10,\n\tRPCBPROC_GETADDRLIST = 11,\n\tRPCBPROC_GETSTAT = 12,\n};\n\nenum {\n\tRPCSVC_MAXPAYLOAD = 4194304,\n\tRPCSVC_MAXPAYLOAD_TCP = 4194304,\n\tRPCSVC_MAXPAYLOAD_UDP = 32768,\n};\n\nenum {\n\tRPC_PIPEFS_MOUNT = 0,\n\tRPC_PIPEFS_UMOUNT = 1,\n};\n\nenum {\n\tRPC_TASK_RUNNING = 0,\n\tRPC_TASK_QUEUED = 1,\n\tRPC_TASK_ACTIVE = 2,\n\tRPC_TASK_NEED_XMIT = 3,\n\tRPC_TASK_NEED_RECV = 4,\n\tRPC_TASK_MSG_PIN_WAIT = 5,\n};\n\nenum {\n\tRQ_SECURE = 0,\n\tRQ_LOCAL = 1,\n\tRQ_USEDEFERRAL = 2,\n\tRQ_DROPME = 3,\n\tRQ_VICTIM = 4,\n\tRQ_DATA = 5,\n};\n\nenum {\n\tRQ_WAIT_BUSY_PCT = 5,\n\tUNBUSY_THR_PCT = 75,\n\tMIN_DELAY_THR_PCT = 500,\n\tMAX_DELAY_THR_PCT = 25000,\n\tMIN_DELAY = 250,\n\tMAX_DELAY = 250000,\n\tDFGV_USAGE_PCT = 50,\n\tDFGV_PERIOD = 100000,\n\tMAX_LAGGING_PERIODS = 10,\n\tIOC_PAGE_SHIFT = 12,\n\tIOC_PAGE_SIZE = 4096,\n\tIOC_SECT_TO_PAGE_SHIFT = 3,\n\tLCOEF_RANDIO_PAGES = 4096,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTL8139 = 0,\n\tRTL8129 = 1,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRX_GCLKMAC_ENA = -2147483648,\n\tRX_GCLKMAC_OFF = 1073741824,\n\tRX_STFW_DIS = 536870912,\n\tRX_STFW_ENA = 268435456,\n\tRX_TRUNC_ON = 134217728,\n\tRX_TRUNC_OFF = 67108864,\n\tRX_VLAN_STRIP_ON = 33554432,\n\tRX_VLAN_STRIP_OFF = 16777216,\n\tRX_MACSEC_FLUSH_ON = 8388608,\n\tRX_MACSEC_FLUSH_OFF = 4194304,\n\tRX_MACSEC_ASF_FLUSH_ON = 2097152,\n\tRX_MACSEC_ASF_FLUSH_OFF = 1048576,\n\tGMF_RX_OVER_ON = 524288,\n\tGMF_RX_OVER_OFF = 262144,\n\tGMF_ASF_RX_OVER_ON = 131072,\n\tGMF_ASF_RX_OVER_OFF = 65536,\n\tGMF_WP_TST_ON = 16384,\n\tGMF_WP_TST_OFF = 8192,\n\tGMF_WP_STEP = 4096,\n\tGMF_RP_TST_ON = 1024,\n\tGMF_RP_TST_OFF = 512,\n\tGMF_RP_STEP = 256,\n\tGMF_RX_F_FL_ON = 128,\n\tGMF_RX_F_FL_OFF = 64,\n\tGMF_CLI_RX_FO = 32,\n\tGMF_CLI_RX_C = 16,\n\tGMF_OPER_ON = 8,\n\tGMF_OPER_OFF = 4,\n\tGMF_RST_CLR = 2,\n\tGMF_RST_SET = 1,\n\tRX_GMF_FL_THR_DEF = 10,\n\tGMF_RX_CTRL_DEF = 136,\n};\n\nenum {\n\tRX_IPV6_SA_MOB_ENA = 512,\n\tRX_IPV6_SA_MOB_DIS = 256,\n\tRX_IPV6_DA_MOB_ENA = 128,\n\tRX_IPV6_DA_MOB_DIS = 64,\n\tRX_PTR_SYNCDLY_ENA = 32,\n\tRX_PTR_SYNCDLY_DIS = 16,\n\tRX_ASF_NEWFLAG_ENA = 8,\n\tRX_ASF_NEWFLAG_DIS = 4,\n\tRX_FLSH_MISSPKT_ENA = 2,\n\tRX_FLSH_MISSPKT_DIS = 1,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tRworksched = 1,\n\tRpending = 2,\n\tWworksched = 4,\n\tWpending = 8,\n};\n\nenum {\n\tSAMPLES = 8,\n\tMIN_CHANGE = 5,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSCTP_AUTH_HMAC_ID_RESERVED_0 = 0,\n\tSCTP_AUTH_HMAC_ID_SHA1 = 1,\n\tSCTP_AUTH_HMAC_ID_RESERVED_2 = 2,\n\tSCTP_AUTH_HMAC_ID_SHA256 = 3,\n\t__SCTP_AUTH_HMAC_MAX = 4,\n};\n\nenum {\n\tSCTP_MAX_DUP_TSNS = 16,\n};\n\nenum {\n\tSCTP_MAX_STREAM = 65535,\n};\n\nenum {\n\tSC_STAT_CLR_IRQ = 16,\n\tSC_STAT_OP_ON = 8,\n\tSC_STAT_OP_OFF = 4,\n\tSC_STAT_RST_CLR = 2,\n\tSC_STAT_RST_SET = 1,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSECTION_MARKED_PRESENT_BIT = 0,\n\tSECTION_HAS_MEM_MAP_BIT = 1,\n\tSECTION_IS_ONLINE_BIT = 2,\n\tSECTION_IS_EARLY_BIT = 3,\n\tSECTION_IS_VMEMMAP_PREINIT_BIT = 4,\n\tSECTION_MAP_LAST_BIT = 5,\n};\n\nenum {\n\tSEG6_ATTR_UNSPEC = 0,\n\tSEG6_ATTR_DST = 1,\n\tSEG6_ATTR_DSTLEN = 2,\n\tSEG6_ATTR_HMACKEYID = 3,\n\tSEG6_ATTR_SECRET = 4,\n\tSEG6_ATTR_SECRETLEN = 5,\n\tSEG6_ATTR_ALGID = 6,\n\tSEG6_ATTR_HMACINFO = 7,\n\t__SEG6_ATTR_MAX = 8,\n};\n\nenum {\n\tSEG6_CMD_UNSPEC = 0,\n\tSEG6_CMD_SETHMAC = 1,\n\tSEG6_CMD_DUMPHMAC = 2,\n\tSEG6_CMD_SET_TUNSRC = 3,\n\tSEG6_CMD_GET_TUNSRC = 4,\n\t__SEG6_CMD_MAX = 5,\n};\n\nenum {\n\tSELNL_MSG_SETENFORCE = 16,\n\tSELNL_MSG_POLICYLOAD = 17,\n\tSELNL_MSG_MAX = 18,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSKCIPHER_WALK_SLOW = 1,\n\tSKCIPHER_WALK_COPY = 2,\n\tSKCIPHER_WALK_DIFF = 4,\n\tSKCIPHER_WALK_SLEEP = 8,\n};\n\nenum {\n\tSKX_PCI_UNCORE_IMC = 0,\n\tSKX_PCI_UNCORE_M2M = 1,\n\tSKX_PCI_UNCORE_UPI = 2,\n\tSKX_PCI_UNCORE_M2PCIE = 3,\n\tSKX_PCI_UNCORE_M3UPI = 4,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSNBEP_PCI_QPI_PORT0_FILTER = 0,\n\tSNBEP_PCI_QPI_PORT1_FILTER = 1,\n\tBDX_PCI_QPI_PORT2_FILTER = 2,\n};\n\nenum {\n\tSNBEP_PCI_UNCORE_HA = 0,\n\tSNBEP_PCI_UNCORE_IMC = 1,\n\tSNBEP_PCI_UNCORE_QPI = 2,\n\tSNBEP_PCI_UNCORE_R2PCIE = 3,\n\tSNBEP_PCI_UNCORE_R3QPI = 4,\n};\n\nenum {\n\tSNB_PCI_UNCORE_IMC = 0,\n};\n\nenum {\n\tSNDRV_CHMAP_UNKNOWN = 0,\n\tSNDRV_CHMAP_NA = 1,\n\tSNDRV_CHMAP_MONO = 2,\n\tSNDRV_CHMAP_FL = 3,\n\tSNDRV_CHMAP_FR = 4,\n\tSNDRV_CHMAP_RL = 5,\n\tSNDRV_CHMAP_RR = 6,\n\tSNDRV_CHMAP_FC = 7,\n\tSNDRV_CHMAP_LFE = 8,\n\tSNDRV_CHMAP_SL = 9,\n\tSNDRV_CHMAP_SR = 10,\n\tSNDRV_CHMAP_RC = 11,\n\tSNDRV_CHMAP_FLC = 12,\n\tSNDRV_CHMAP_FRC = 13,\n\tSNDRV_CHMAP_RLC = 14,\n\tSNDRV_CHMAP_RRC = 15,\n\tSNDRV_CHMAP_FLW = 16,\n\tSNDRV_CHMAP_FRW = 17,\n\tSNDRV_CHMAP_FLH = 18,\n\tSNDRV_CHMAP_FCH = 19,\n\tSNDRV_CHMAP_FRH = 20,\n\tSNDRV_CHMAP_TC = 21,\n\tSNDRV_CHMAP_TFL = 22,\n\tSNDRV_CHMAP_TFR = 23,\n\tSNDRV_CHMAP_TFC = 24,\n\tSNDRV_CHMAP_TRL = 25,\n\tSNDRV_CHMAP_TRR = 26,\n\tSNDRV_CHMAP_TRC = 27,\n\tSNDRV_CHMAP_TFLC = 28,\n\tSNDRV_CHMAP_TFRC = 29,\n\tSNDRV_CHMAP_TSL = 30,\n\tSNDRV_CHMAP_TSR = 31,\n\tSNDRV_CHMAP_LLFE = 32,\n\tSNDRV_CHMAP_RLFE = 33,\n\tSNDRV_CHMAP_BC = 34,\n\tSNDRV_CHMAP_BLC = 35,\n\tSNDRV_CHMAP_BRC = 36,\n\tSNDRV_CHMAP_LAST = 36,\n};\n\nenum {\n\tSNDRV_CTL_IOCTL_ELEM_LIST32 = 3225965840,\n\tSNDRV_CTL_IOCTL_ELEM_INFO32 = 3239073041,\n\tSNDRV_CTL_IOCTL_ELEM_READ32 = 3267646738,\n\tSNDRV_CTL_IOCTL_ELEM_WRITE32 = 3267646739,\n\tSNDRV_CTL_IOCTL_ELEM_ADD32 = 3239073047,\n\tSNDRV_CTL_IOCTL_ELEM_REPLACE32 = 3239073048,\n};\n\nenum {\n\tSNDRV_CTL_TLV_OP_READ = 0,\n\tSNDRV_CTL_TLV_OP_WRITE = 1,\n\tSNDRV_CTL_TLV_OP_CMD = -1,\n};\n\nenum {\n\tSNDRV_HWDEP_IFACE_OPL2 = 0,\n\tSNDRV_HWDEP_IFACE_OPL3 = 1,\n\tSNDRV_HWDEP_IFACE_OPL4 = 2,\n\tSNDRV_HWDEP_IFACE_SB16CSP = 3,\n\tSNDRV_HWDEP_IFACE_EMU10K1 = 4,\n\tSNDRV_HWDEP_IFACE_YSS225 = 5,\n\tSNDRV_HWDEP_IFACE_ICS2115 = 6,\n\tSNDRV_HWDEP_IFACE_SSCAPE = 7,\n\tSNDRV_HWDEP_IFACE_VX = 8,\n\tSNDRV_HWDEP_IFACE_MIXART = 9,\n\tSNDRV_HWDEP_IFACE_USX2Y = 10,\n\tSNDRV_HWDEP_IFACE_EMUX_WAVETABLE = 11,\n\tSNDRV_HWDEP_IFACE_BLUETOOTH = 12,\n\tSNDRV_HWDEP_IFACE_USX2Y_PCM = 13,\n\tSNDRV_HWDEP_IFACE_PCXHR = 14,\n\tSNDRV_HWDEP_IFACE_SB_RC = 15,\n\tSNDRV_HWDEP_IFACE_HDA = 16,\n\tSNDRV_HWDEP_IFACE_USB_STREAM = 17,\n\tSNDRV_HWDEP_IFACE_FW_DICE = 18,\n\tSNDRV_HWDEP_IFACE_FW_FIREWORKS = 19,\n\tSNDRV_HWDEP_IFACE_FW_BEBOB = 20,\n\tSNDRV_HWDEP_IFACE_FW_OXFW = 21,\n\tSNDRV_HWDEP_IFACE_FW_DIGI00X = 22,\n\tSNDRV_HWDEP_IFACE_FW_TASCAM = 23,\n\tSNDRV_HWDEP_IFACE_LINE6 = 24,\n\tSNDRV_HWDEP_IFACE_FW_MOTU = 25,\n\tSNDRV_HWDEP_IFACE_FW_FIREFACE = 26,\n\tSNDRV_HWDEP_IFACE_LAST = 26,\n};\n\nenum {\n\tSNDRV_HWDEP_IOCTL_DSP_LOAD32 = 1079003139,\n};\n\nenum {\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = 5,\n};\n\nenum {\n\tSNDRV_PCM_CLASS_GENERIC = 0,\n\tSNDRV_PCM_CLASS_MULTI = 1,\n\tSNDRV_PCM_CLASS_MODEM = 2,\n\tSNDRV_PCM_CLASS_DIGITIZER = 3,\n\tSNDRV_PCM_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_PCM_IOCTL_HW_REFINE32 = 3260825872,\n\tSNDRV_PCM_IOCTL_HW_PARAMS32 = 3260825873,\n\tSNDRV_PCM_IOCTL_SW_PARAMS32 = 3228057875,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT32 = 2154578208,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT32 = 3228320036,\n\tSNDRV_PCM_IOCTL_DELAY32 = 2147762465,\n\tSNDRV_PCM_IOCTL_CHANNEL_INFO32 = 2148548914,\n\tSNDRV_PCM_IOCTL_REWIND32 = 1074020678,\n\tSNDRV_PCM_IOCTL_FORWARD32 = 1074020681,\n\tSNDRV_PCM_IOCTL_WRITEI_FRAMES32 = 1074544976,\n\tSNDRV_PCM_IOCTL_READI_FRAMES32 = 2148286801,\n\tSNDRV_PCM_IOCTL_WRITEN_FRAMES32 = 1074544978,\n\tSNDRV_PCM_IOCTL_READN_FRAMES32 = 2148286803,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT64 = 2155888928,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT64 = 3229630756,\n};\n\nenum {\n\tSNDRV_PCM_MMAP_OFFSET_DATA = 0,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_OLD = 2147483648,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_OLD = 2164260864,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_NEW = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_NEW = 2197815296,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL = 2197815296,\n};\n\nenum {\n\tSNDRV_PCM_STREAM_PLAYBACK = 0,\n\tSNDRV_PCM_STREAM_CAPTURE = 1,\n\tSNDRV_PCM_STREAM_LAST = 1,\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_NONE = 0,\n\tSNDRV_PCM_TSTAMP_ENABLE = 1,\n\tSNDRV_PCM_TSTAMP_LAST = 1,\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC = 1,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW = 2,\n\tSNDRV_PCM_TSTAMP_TYPE_LAST = 2,\n};\n\nenum {\n\tSNDRV_SEQ_IOCTL_CREATE_PORT32 = 3231994656,\n\tSNDRV_SEQ_IOCTL_DELETE_PORT32 = 1084511009,\n\tSNDRV_SEQ_IOCTL_GET_PORT_INFO32 = 3231994658,\n\tSNDRV_SEQ_IOCTL_SET_PORT_INFO32 = 1084511011,\n\tSNDRV_SEQ_IOCTL_QUERY_NEXT_PORT32 = 3231994706,\n};\n\nenum {\n\tSNDRV_TIMER_CLASS_NONE = -1,\n\tSNDRV_TIMER_CLASS_SLAVE = 0,\n\tSNDRV_TIMER_CLASS_GLOBAL = 1,\n\tSNDRV_TIMER_CLASS_CARD = 2,\n\tSNDRV_TIMER_CLASS_PCM = 3,\n\tSNDRV_TIMER_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_TIMER_EVENT_RESOLUTION = 0,\n\tSNDRV_TIMER_EVENT_TICK = 1,\n\tSNDRV_TIMER_EVENT_START = 2,\n\tSNDRV_TIMER_EVENT_STOP = 3,\n\tSNDRV_TIMER_EVENT_CONTINUE = 4,\n\tSNDRV_TIMER_EVENT_PAUSE = 5,\n\tSNDRV_TIMER_EVENT_EARLY = 6,\n\tSNDRV_TIMER_EVENT_SUSPEND = 7,\n\tSNDRV_TIMER_EVENT_RESUME = 8,\n\tSNDRV_TIMER_EVENT_MSTART = 12,\n\tSNDRV_TIMER_EVENT_MSTOP = 13,\n\tSNDRV_TIMER_EVENT_MCONTINUE = 14,\n\tSNDRV_TIMER_EVENT_MPAUSE = 15,\n\tSNDRV_TIMER_EVENT_MSUSPEND = 17,\n\tSNDRV_TIMER_EVENT_MRESUME = 18,\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_GPARAMS32 = 1077695492,\n\tSNDRV_TIMER_IOCTL_INFO32 = 2162185233,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT32 = 1079530516,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT64 = 1080054804,\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_START_OLD = 21536,\n\tSNDRV_TIMER_IOCTL_STOP_OLD = 21537,\n\tSNDRV_TIMER_IOCTL_CONTINUE_OLD = 21538,\n\tSNDRV_TIMER_IOCTL_PAUSE_OLD = 21539,\n};\n\nenum {\n\tSNDRV_TIMER_SCLASS_NONE = 0,\n\tSNDRV_TIMER_SCLASS_APPLICATION = 1,\n\tSNDRV_TIMER_SCLASS_SEQUENCER = 2,\n\tSNDRV_TIMER_SCLASS_OSS_SEQUENCER = 3,\n\tSNDRV_TIMER_SCLASS_LAST = 3,\n};\n\nenum {\n\tSND_CTL_SUBDEV_PCM = 0,\n\tSND_CTL_SUBDEV_RAWMIDI = 1,\n\tSND_CTL_SUBDEV_ITEMS = 2,\n};\n\nenum {\n\tSND_INTEL_DSP_DRIVER_ANY = 0,\n\tSND_INTEL_DSP_DRIVER_LEGACY = 1,\n\tSND_INTEL_DSP_DRIVER_SST = 2,\n\tSND_INTEL_DSP_DRIVER_SOF = 3,\n\tSND_INTEL_DSP_DRIVER_AVS = 4,\n\tSND_INTEL_DSP_DRIVER_LAST = 4,\n};\n\nenum {\n\tSNR_PCI_UNCORE_M2M = 0,\n\tSNR_PCI_UNCORE_PCIE3 = 1,\n};\n\nenum {\n\tSNR_QAT_PMON_ID = 0,\n\tSNR_CBDMA_DMI_PMON_ID = 1,\n\tSNR_NIS_PMON_ID = 2,\n\tSNR_DLB_PMON_ID = 3,\n\tSNR_PCIE_GEN3_PMON_ID = 4,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSPI_BLIST_NOIUS = 1,\n};\n\nenum {\n\tSP_TASK_PENDING = 0,\n\tSP_NEED_VICTIM = 1,\n\tSP_VICTIM_REMAINS = 2,\n\tSP_TASK_STARTING = 3,\n};\n\nenum {\n\tSR_DMAR_FECTL_REG = 0,\n\tSR_DMAR_FEDATA_REG = 1,\n\tSR_DMAR_FEADDR_REG = 2,\n\tSR_DMAR_FEUADDR_REG = 3,\n\tMAX_SR_DMAR_REGS = 4,\n};\n\nenum {\n\tSTART_TS = 0,\n\tNOW_TS = 1,\n\tDELTA_TS = 2,\n\tJUMP_PREDICATE = 3,\n\tDELTA_TARGET = 4,\n\tN_CS_GPR = 5,\n};\n\nenum {\n\tSTAT_CTRL = 3712,\n\tSTAT_LAST_IDX = 3716,\n\tSTAT_LIST_ADDR_LO = 3720,\n\tSTAT_LIST_ADDR_HI = 3724,\n\tSTAT_TXA1_RIDX = 3728,\n\tSTAT_TXS1_RIDX = 3730,\n\tSTAT_TXA2_RIDX = 3732,\n\tSTAT_TXS2_RIDX = 3734,\n\tSTAT_TX_IDX_TH = 3736,\n\tSTAT_PUT_IDX = 3740,\n\tSTAT_FIFO_WP = 3744,\n\tSTAT_FIFO_RP = 3748,\n\tSTAT_FIFO_RSP = 3750,\n\tSTAT_FIFO_LEVEL = 3752,\n\tSTAT_FIFO_SHLVL = 3754,\n\tSTAT_FIFO_WM = 3756,\n\tSTAT_FIFO_ISR_WM = 3757,\n\tSTAT_LEV_TIMER_INI = 3760,\n\tSTAT_LEV_TIMER_CNT = 3764,\n\tSTAT_LEV_TIMER_CTRL = 3768,\n\tSTAT_LEV_TIMER_TEST = 3769,\n\tSTAT_TX_TIMER_INI = 3776,\n\tSTAT_TX_TIMER_CNT = 3780,\n\tSTAT_TX_TIMER_CTRL = 3784,\n\tSTAT_TX_TIMER_TEST = 3785,\n\tSTAT_ISR_TIMER_INI = 3792,\n\tSTAT_ISR_TIMER_CNT = 3796,\n\tSTAT_ISR_TIMER_CTRL = 3800,\n\tSTAT_ISR_TIMER_TEST = 3801,\n};\n\nenum {\n\tSUNRPC_MAX_UDP_SENDPAGES = 11,\n};\n\nenum {\n\tSUNRPC_PIPEFS_NFS_PRIO = 0,\n\tSUNRPC_PIPEFS_RPC_PRIO = 1,\n};\n\nenum {\n\tSVC_HANDSHAKE_TO = 5000,\n};\n\nenum {\n\tSVC_POOL_AUTO = -1,\n\tSVC_POOL_GLOBAL = 0,\n\tSVC_POOL_PERCPU = 1,\n\tSVC_POOL_PERNODE = 2,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWMII_SPEED_10 = 0,\n\tSWMII_SPEED_100 = 1,\n\tSWMII_SPEED_1000 = 2,\n\tSWMII_DUPLEX_HALF = 0,\n\tSWMII_DUPLEX_FULL = 1,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSW_BIT_CACHE_FLUSH_DONE = 0,\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = -1,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_ATTR_UNSPEC = 0,\n\tTASKSTATS_CMD_ATTR_PID = 1,\n\tTASKSTATS_CMD_ATTR_TGID = 2,\n\tTASKSTATS_CMD_ATTR_REGISTER_CPUMASK = 3,\n\tTASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK = 4,\n\t__TASKSTATS_CMD_ATTR_MAX = 5,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASKSTATS_TYPE_UNSPEC = 0,\n\tTASKSTATS_TYPE_PID = 1,\n\tTASKSTATS_TYPE_TGID = 2,\n\tTASKSTATS_TYPE_STATS = 3,\n\tTASKSTATS_TYPE_AGGR_PID = 4,\n\tTASKSTATS_TYPE_AGGR_TGID = 5,\n\tTASKSTATS_TYPE_NULL = 6,\n\t__TASKSTATS_TYPE_MAX = 7,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTBMU_TEST_BMU_TX_CHK_AUTO_OFF = -2147483648,\n\tTBMU_TEST_BMU_TX_CHK_AUTO_ON = 1073741824,\n\tTBMU_TEST_HOME_ADD_PAD_FIX1_EN = 536870912,\n\tTBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 268435456,\n\tTBMU_TEST_ROUTING_ADD_FIX_EN = 134217728,\n\tTBMU_TEST_ROUTING_ADD_FIX_DIS = 67108864,\n\tTBMU_TEST_HOME_ADD_FIX_EN = 33554432,\n\tTBMU_TEST_HOME_ADD_FIX_DIS = 16777216,\n\tTBMU_TEST_TEST_RSPTR_ON = 4194304,\n\tTBMU_TEST_TEST_RSPTR_OFF = 2097152,\n\tTBMU_TEST_TESTSTEP_RSPTR = 1048576,\n\tTBMU_TEST_TEST_RPTR_ON = 262144,\n\tTBMU_TEST_TEST_RPTR_OFF = 131072,\n\tTBMU_TEST_TESTSTEP_RPTR = 65536,\n\tTBMU_TEST_TEST_WSPTR_ON = 16384,\n\tTBMU_TEST_TEST_WSPTR_OFF = 8192,\n\tTBMU_TEST_TESTSTEP_WSPTR = 4096,\n\tTBMU_TEST_TEST_WPTR_ON = 1024,\n\tTBMU_TEST_TEST_WPTR_OFF = 512,\n\tTBMU_TEST_TESTSTEP_WPTR = 256,\n\tTBMU_TEST_TEST_REQ_NB_ON = 64,\n\tTBMU_TEST_TEST_REQ_NB_OFF = 32,\n\tTBMU_TEST_TESTSTEP_REQ_NB = 16,\n\tTBMU_TEST_TEST_DONE_IDX_ON = 4,\n\tTBMU_TEST_TEST_DONE_IDX_OFF = 2,\n\tTBMU_TEST_TESTSTEP_DONE_IDX = 1,\n};\n\nenum {\n\tTCA_ACT_UNSPEC = 0,\n\tTCA_ACT_KIND = 1,\n\tTCA_ACT_OPTIONS = 2,\n\tTCA_ACT_INDEX = 3,\n\tTCA_ACT_STATS = 4,\n\tTCA_ACT_PAD = 5,\n\tTCA_ACT_COOKIE = 6,\n\tTCA_ACT_FLAGS = 7,\n\tTCA_ACT_HW_STATS = 8,\n\tTCA_ACT_USED_HW_STATS = 9,\n\tTCA_ACT_IN_HW_COUNT = 10,\n\t__TCA_ACT_MAX = 11,\n};\n\nenum {\n\tTCA_CGROUP_UNSPEC = 0,\n\tTCA_CGROUP_ACT = 1,\n\tTCA_CGROUP_POLICE = 2,\n\tTCA_CGROUP_EMATCHES = 3,\n\t__TCA_CGROUP_MAX = 4,\n};\n\nenum {\n\tTCA_EMATCH_TREE_UNSPEC = 0,\n\tTCA_EMATCH_TREE_HDR = 1,\n\tTCA_EMATCH_TREE_LIST = 2,\n\t__TCA_EMATCH_TREE_MAX = 3,\n};\n\nenum {\n\tTCA_FLOWER_KEY_CT_FLAGS_NEW = 1,\n\tTCA_FLOWER_KEY_CT_FLAGS_ESTABLISHED = 2,\n\tTCA_FLOWER_KEY_CT_FLAGS_RELATED = 4,\n\tTCA_FLOWER_KEY_CT_FLAGS_TRACKED = 8,\n\tTCA_FLOWER_KEY_CT_FLAGS_INVALID = 16,\n\tTCA_FLOWER_KEY_CT_FLAGS_REPLY = 32,\n\t__TCA_FLOWER_KEY_CT_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_ROOT_UNSPEC = 0,\n\tTCA_ROOT_TAB = 1,\n\tTCA_ROOT_FLAGS = 2,\n\tTCA_ROOT_COUNT = 3,\n\tTCA_ROOT_TIME_DELTA = 4,\n\tTCA_ROOT_EXT_WARN_MSG = 5,\n\t__TCA_ROOT_MAX = 6,\n};\n\nenum {\n\tTCA_STAB_UNSPEC = 0,\n\tTCA_STAB_BASE = 1,\n\tTCA_STAB_DATA = 2,\n\t__TCA_STAB_MAX = 3,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 1,\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 14,\n\tTCP_DATA_OFFSET = 240,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nenum {\n\tTIM_START = 4,\n\tTIM_STOP = 2,\n\tTIM_CLR_IRQ = 1,\n};\n\nenum {\n\tTKIP_DECRYPT_OK = 0,\n\tTKIP_DECRYPT_NO_EXT_IV = -1,\n\tTKIP_DECRYPT_INVALID_KEYIDX = -2,\n\tTKIP_DECRYPT_REPLAY = -3,\n};\n\nenum {\n\tTLS_ALERT_DESC_CLOSE_NOTIFY = 0,\n\tTLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10,\n\tTLS_ALERT_DESC_BAD_RECORD_MAC = 20,\n\tTLS_ALERT_DESC_RECORD_OVERFLOW = 22,\n\tTLS_ALERT_DESC_HANDSHAKE_FAILURE = 40,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE = 42,\n\tTLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43,\n\tTLS_ALERT_DESC_CERTIFICATE_REVOKED = 44,\n\tTLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45,\n\tTLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46,\n\tTLS_ALERT_DESC_ILLEGAL_PARAMETER = 47,\n\tTLS_ALERT_DESC_UNKNOWN_CA = 48,\n\tTLS_ALERT_DESC_ACCESS_DENIED = 49,\n\tTLS_ALERT_DESC_DECODE_ERROR = 50,\n\tTLS_ALERT_DESC_DECRYPT_ERROR = 51,\n\tTLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52,\n\tTLS_ALERT_DESC_PROTOCOL_VERSION = 70,\n\tTLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71,\n\tTLS_ALERT_DESC_INTERNAL_ERROR = 80,\n\tTLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86,\n\tTLS_ALERT_DESC_USER_CANCELED = 90,\n\tTLS_ALERT_DESC_MISSING_EXTENSION = 109,\n\tTLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110,\n\tTLS_ALERT_DESC_UNRECOGNIZED_NAME = 112,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113,\n\tTLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115,\n\tTLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116,\n\tTLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120,\n};\n\nenum {\n\tTLS_ALERT_LEVEL_WARNING = 1,\n\tTLS_ALERT_LEVEL_FATAL = 2,\n};\n\nenum {\n\tTLS_NO_KEYRING = 0,\n\tTLS_NO_PEERID = 0,\n\tTLS_NO_CERT = 0,\n\tTLS_NO_PRIVKEY = 0,\n};\n\nenum {\n\tTLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20,\n\tTLS_RECORD_TYPE_ALERT = 21,\n\tTLS_RECORD_TYPE_HANDSHAKE = 22,\n\tTLS_RECORD_TYPE_DATA = 23,\n\tTLS_RECORD_TYPE_HEARTBEAT = 24,\n\tTLS_RECORD_TYPE_TLS12_CID = 25,\n\tTLS_RECORD_TYPE_ACK = 26,\n};\n\nenum {\n\tTOO_MANY_CLOSE = -1,\n\tTOO_MANY_OPEN = -2,\n\tMISSING_QUOTE = -3,\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_BAD_MAXACT_TYPE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_NON_UNIQ_SYMBOL = 10,\n\tTP_ERR_BAD_RETPROBE = 11,\n\tTP_ERR_NO_TRACEPOINT = 12,\n\tTP_ERR_BAD_TP_NAME = 13,\n\tTP_ERR_BAD_ADDR_SUFFIX = 14,\n\tTP_ERR_NO_GROUP_NAME = 15,\n\tTP_ERR_GROUP_TOO_LONG = 16,\n\tTP_ERR_BAD_GROUP_NAME = 17,\n\tTP_ERR_NO_EVENT_NAME = 18,\n\tTP_ERR_EVENT_TOO_LONG = 19,\n\tTP_ERR_BAD_EVENT_NAME = 20,\n\tTP_ERR_EVENT_EXIST = 21,\n\tTP_ERR_RETVAL_ON_PROBE = 22,\n\tTP_ERR_NO_RETVAL = 23,\n\tTP_ERR_BAD_STACK_NUM = 24,\n\tTP_ERR_BAD_ARG_NUM = 25,\n\tTP_ERR_BAD_VAR = 26,\n\tTP_ERR_BAD_REG_NAME = 27,\n\tTP_ERR_BAD_MEM_ADDR = 28,\n\tTP_ERR_BAD_IMM = 29,\n\tTP_ERR_IMMSTR_NO_CLOSE = 30,\n\tTP_ERR_FILE_ON_KPROBE = 31,\n\tTP_ERR_BAD_FILE_OFFS = 32,\n\tTP_ERR_SYM_ON_UPROBE = 33,\n\tTP_ERR_TOO_MANY_OPS = 34,\n\tTP_ERR_DEREF_NEED_BRACE = 35,\n\tTP_ERR_BAD_DEREF_OFFS = 36,\n\tTP_ERR_DEREF_OPEN_BRACE = 37,\n\tTP_ERR_COMM_CANT_DEREF = 38,\n\tTP_ERR_BAD_FETCH_ARG = 39,\n\tTP_ERR_ARRAY_NO_CLOSE = 40,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 41,\n\tTP_ERR_BAD_ARRAY_NUM = 42,\n\tTP_ERR_ARRAY_TOO_BIG = 43,\n\tTP_ERR_BAD_TYPE = 44,\n\tTP_ERR_BAD_STRING = 45,\n\tTP_ERR_BAD_SYMSTRING = 46,\n\tTP_ERR_BAD_BITFIELD = 47,\n\tTP_ERR_ARG_NAME_TOO_LONG = 48,\n\tTP_ERR_NO_ARG_NAME = 49,\n\tTP_ERR_BAD_ARG_NAME = 50,\n\tTP_ERR_USED_ARG_NAME = 51,\n\tTP_ERR_ARG_TOO_LONG = 52,\n\tTP_ERR_NO_ARG_BODY = 53,\n\tTP_ERR_BAD_INSN_BNDRY = 54,\n\tTP_ERR_FAIL_REG_PROBE = 55,\n\tTP_ERR_DIFF_PROBE_TYPE = 56,\n\tTP_ERR_DIFF_ARG_TYPE = 57,\n\tTP_ERR_SAME_PROBE = 58,\n\tTP_ERR_NO_EVENT_INFO = 59,\n\tTP_ERR_BAD_ATTACH_EVENT = 60,\n\tTP_ERR_BAD_ATTACH_ARG = 61,\n\tTP_ERR_NO_EP_FILTER = 62,\n\tTP_ERR_NOSUP_BTFARG = 63,\n\tTP_ERR_NO_BTFARG = 64,\n\tTP_ERR_NO_BTF_ENTRY = 65,\n\tTP_ERR_BAD_VAR_ARGS = 66,\n\tTP_ERR_NOFENTRY_ARGS = 67,\n\tTP_ERR_DOUBLE_ARGS = 68,\n\tTP_ERR_ARGS_2LONG = 69,\n\tTP_ERR_ARGIDX_2BIG = 70,\n\tTP_ERR_NO_PTR_STRCT = 71,\n\tTP_ERR_NOSUP_DAT_ARG = 72,\n\tTP_ERR_BAD_HYPHEN = 73,\n\tTP_ERR_NO_BTF_FIELD = 74,\n\tTP_ERR_BAD_BTF_TID = 75,\n\tTP_ERR_BAD_TYPE4STR = 76,\n\tTP_ERR_NEED_STRING_TYPE = 77,\n\tTP_ERR_TOO_MANY_ARGS = 78,\n\tTP_ERR_TOO_MANY_EARGS = 79,\n};\n\nenum {\n\tTRACEFS_EVENT_INODE = 2,\n\tTRACEFS_GID_PERM_SET = 4,\n\tTRACEFS_UID_PERM_SET = 8,\n\tTRACEFS_INSTANCE_INODE = 16,\n};\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n\tTRACE_ARRAY_FL_BOOT = 2,\n\tTRACE_ARRAY_FL_LAST_BOOT = 4,\n\tTRACE_ARRAY_FL_MOD_INIT = 8,\n\tTRACE_ARRAY_FL_MEMMAP = 16,\n\tTRACE_ARRAY_FL_VMALLOC = 32,\n};\n\nenum {\n\tTRACE_CTX_NMI = 0,\n\tTRACE_CTX_IRQ = 1,\n\tTRACE_CTX_SOFTIRQ = 2,\n\tTRACE_CTX_NORMAL = 3,\n\tTRACE_CTX_TRANSITION = 4,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 4,\n\tTRACE_EVENT_FL_TRACEPOINT = 8,\n\tTRACE_EVENT_FL_DYNAMIC = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n\tTRACE_EVENT_FL_EPROBE = 128,\n\tTRACE_EVENT_FL_FPROBE = 256,\n\tTRACE_EVENT_FL_CUSTOM = 512,\n\tTRACE_EVENT_FL_TEST_STR = 1024,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_FTRACE_BIT = 0,\n\tTRACE_FTRACE_NMI_BIT = 1,\n\tTRACE_FTRACE_IRQ_BIT = 2,\n\tTRACE_FTRACE_SIRQ_BIT = 3,\n\tTRACE_FTRACE_TRANSITION_BIT = 4,\n\tTRACE_INTERNAL_BIT = 5,\n\tTRACE_INTERNAL_NMI_BIT = 6,\n\tTRACE_INTERNAL_IRQ_BIT = 7,\n\tTRACE_INTERNAL_SIRQ_BIT = 8,\n\tTRACE_INTERNAL_TRANSITION_BIT = 9,\n\tTRACE_INTERNAL_EVENT_BIT = 10,\n\tTRACE_INTERNAL_EVENT_NMI_BIT = 11,\n\tTRACE_INTERNAL_EVENT_IRQ_BIT = 12,\n\tTRACE_INTERNAL_EVENT_SIRQ_BIT = 13,\n\tTRACE_INTERNAL_EVENT_TRANSITION_BIT = 14,\n\tTRACE_BRANCH_BIT = 15,\n\tTRACE_IRQ_BIT = 16,\n\tTRACE_RECORD_RECURSION_BIT = 17,\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tTST_FRC_DPERR_MR = 128,\n\tTST_FRC_DPERR_MW = 64,\n\tTST_FRC_DPERR_TR = 32,\n\tTST_FRC_DPERR_TW = 16,\n\tTST_FRC_APERR_M = 8,\n\tTST_FRC_APERR_T = 4,\n\tTST_CFG_WRITE_ON = 2,\n\tTST_CFG_WRITE_OFF = 1,\n};\n\nenum {\n\tTXA_ENA_FSYNC = 128,\n\tTXA_DIS_FSYNC = 64,\n\tTXA_ENA_ALLOC = 32,\n\tTXA_DIS_ALLOC = 16,\n\tTXA_START_RC = 8,\n\tTXA_STOP_RC = 4,\n\tTXA_ENA_ARB = 2,\n\tTXA_DIS_ARB = 1,\n};\n\nenum {\n\tTXA_ITI_INI = 512,\n\tTXA_ITI_VAL = 516,\n\tTXA_LIM_INI = 520,\n\tTXA_LIM_VAL = 524,\n\tTXA_CTRL = 528,\n\tTXA_TEST = 529,\n\tTXA_STAT = 530,\n\tRSS_KEY = 544,\n\tRSS_CFG = 584,\n};\n\nenum {\n\tTX_DYN_WM_ENA = 3,\n};\n\nenum {\n\tTX_GMF_EA = 3392,\n\tTX_GMF_AE_THR = 3396,\n\tTX_GMF_CTRL_T = 3400,\n\tTX_GMF_WP = 3424,\n\tTX_GMF_WSP = 3428,\n\tTX_GMF_WLEV = 3432,\n\tTX_GMF_RP = 3440,\n\tTX_GMF_RSTP = 3444,\n\tTX_GMF_RLEV = 3448,\n\tECU_AE_THR = 112,\n\tECU_TXFF_LEV = 416,\n\tECU_JUMBO_WM = 128,\n};\n\nenum {\n\tTX_STFW_DIS = -2147483648,\n\tTX_STFW_ENA = 1073741824,\n\tTX_VLAN_TAG_ON = 33554432,\n\tTX_VLAN_TAG_OFF = 16777216,\n\tTX_PCI_JUM_ENA = 8388608,\n\tTX_PCI_JUM_DIS = 4194304,\n\tGMF_WSP_TST_ON = 262144,\n\tGMF_WSP_TST_OFF = 131072,\n\tGMF_WSP_STEP = 65536,\n\tGMF_CLI_TX_FU = 64,\n\tGMF_CLI_TX_FC = 32,\n\tGMF_CLI_TX_PE = 16,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUDPTCP = 1,\n\tCALSUM = 2,\n\tWR_SUM = 4,\n\tINIT_SUM = 8,\n\tLOCK_SUM = 16,\n\tINS_VLAN = 32,\n\tEOP = 128,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNCORE_TYPE_DF = 0,\n\tUNCORE_TYPE_L3 = 1,\n\tUNCORE_TYPE_UMC = 2,\n\tUNCORE_TYPE_MAX = 3,\n};\n\nenum {\n\tUNDEFINED_CAPABLE = 0,\n\tSYSTEM_INTEL_MSR_CAPABLE = 1,\n\tSYSTEM_AMD_MSR_CAPABLE = 2,\n\tSYSTEM_IO_CAPABLE = 3,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tUNWIND_PENDING = 1,\n\tUNWIND_USED = 2,\n};\n\nenum {\n\tUNWIND_PENDING_BIT = 0,\n\tUNWIND_USED_BIT = 1,\n};\n\nenum {\n\tUS_FL_SINGLE_LUN = 1,\n\tUS_FL_NEED_OVERRIDE = 2,\n\tUS_FL_SCM_MULT_TARG = 4,\n\tUS_FL_FIX_INQUIRY = 8,\n\tUS_FL_FIX_CAPACITY = 16,\n\tUS_FL_IGNORE_RESIDUE = 32,\n\tUS_FL_BULK32 = 64,\n\tUS_FL_NOT_LOCKABLE = 128,\n\tUS_FL_GO_SLOW = 256,\n\tUS_FL_NO_WP_DETECT = 512,\n\tUS_FL_MAX_SECTORS_64 = 1024,\n\tUS_FL_IGNORE_DEVICE = 2048,\n\tUS_FL_CAPACITY_HEURISTICS = 4096,\n\tUS_FL_MAX_SECTORS_MIN = 8192,\n\tUS_FL_BULK_IGNORE_TAG = 16384,\n\tUS_FL_SANE_SENSE = 32768,\n\tUS_FL_CAPACITY_OK = 65536,\n\tUS_FL_BAD_SENSE = 131072,\n\tUS_FL_NO_READ_DISC_INFO = 262144,\n\tUS_FL_NO_READ_CAPACITY_16 = 524288,\n\tUS_FL_INITIAL_READ10 = 1048576,\n\tUS_FL_WRITE_CACHE = 2097152,\n\tUS_FL_NEEDS_CAP16 = 4194304,\n\tUS_FL_IGNORE_UAS = 8388608,\n\tUS_FL_BROKEN_FUA = 16777216,\n\tUS_FL_NO_ATA_1X = 33554432,\n\tUS_FL_NO_REPORT_OPCODES = 67108864,\n\tUS_FL_MAX_SECTORS_240 = 134217728,\n\tUS_FL_NO_REPORT_LUNS = 268435456,\n\tUS_FL_ALWAYS_SYNC = 536870912,\n\tUS_FL_NO_SAME = 1073741824,\n\tUS_FL_SENSE_AFTER_SYNC = 2147483648,\n};\n\nenum {\n\tVERBOSE_STATUS = 1,\n};\n\nenum {\n\tVIA_STRFILT_CNT_SHIFT = 16,\n\tVIA_STRFILT_FAIL = 32768,\n\tVIA_STRFILT_ENABLE = 16384,\n\tVIA_RAWBITS_ENABLE = 8192,\n\tVIA_RNG_ENABLE = 64,\n\tVIA_NOISESRC1 = 256,\n\tVIA_NOISESRC2 = 512,\n\tVIA_XSTORE_CNT_MASK = 15,\n\tVIA_RNG_CHUNK_8 = 0,\n\tVIA_RNG_CHUNK_4 = 1,\n\tVIA_RNG_CHUNK_4_MASK = 4294967295,\n\tVIA_RNG_CHUNK_2 = 2,\n\tVIA_RNG_CHUNK_2_MASK = 65535,\n\tVIA_RNG_CHUNK_1 = 3,\n\tVIA_RNG_CHUNK_1_MASK = 255,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tVP_MSIX_CONFIG_VECTOR = 0,\n\tVP_MSIX_VQ_VECTOR = 1,\n};\n\nenum {\n\tVTDSS_FMT_PS = 128,\n};\n\nenum {\n\tVTDSS_FMT_R = 1ULL,\n\tVTDSS_FMT_W = 2ULL,\n\tVTDSS_FMT_A = 256ULL,\n\tVTDSS_FMT_D = 512ULL,\n\tVTDSS_FMT_SNP = 2048ULL,\n\tVTDSS_FMT_OA = 4503599627366400ULL,\n};\n\nenum {\n\tVTIME_PER_SEC_SHIFT = 37ULL,\n\tVTIME_PER_SEC = 137438953472ULL,\n\tVTIME_PER_USEC = 137438ULL,\n\tVTIME_PER_NSEC = 137ULL,\n\tVRATE_MIN_PPM = 10000ULL,\n\tVRATE_MAX_PPM = 100000000ULL,\n\tVRATE_MIN = 1374ULL,\n\tVRATE_CLAMP_ADJ_PCT = 4ULL,\n\tAUTOP_CYCLE_NSEC = 10000000000ULL,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tWMI_READ_TAKES_NO_ARGS = 0,\n\tWMI_GUID_DUPLICATED = 1,\n\tWMI_NO_EVENT_DATA = 2,\n};\n\nenum {\n\tWOL_CTL_LINK_CHG_OCC = 32768,\n\tWOL_CTL_MAGIC_PKT_OCC = 16384,\n\tWOL_CTL_PATTERN_OCC = 8192,\n\tWOL_CTL_CLEAR_RESULT = 4096,\n\tWOL_CTL_ENA_PME_ON_LINK_CHG = 2048,\n\tWOL_CTL_DIS_PME_ON_LINK_CHG = 1024,\n\tWOL_CTL_ENA_PME_ON_MAGIC_PKT = 512,\n\tWOL_CTL_DIS_PME_ON_MAGIC_PKT = 256,\n\tWOL_CTL_ENA_PME_ON_PATTERN = 128,\n\tWOL_CTL_DIS_PME_ON_PATTERN = 64,\n\tWOL_CTL_ENA_LINK_CHG_UNIT = 32,\n\tWOL_CTL_DIS_LINK_CHG_UNIT = 16,\n\tWOL_CTL_ENA_MAGIC_PKT_UNIT = 8,\n\tWOL_CTL_DIS_MAGIC_PKT_UNIT = 4,\n\tWOL_CTL_ENA_PATTERN_UNIT = 2,\n\tWOL_CTL_DIS_PATTERN_UNIT = 1,\n};\n\nenum {\n\tX2APIC_OFF = 0,\n\tX2APIC_DISABLED = 1,\n\tX2APIC_ON = 2,\n\tX2APIC_ON_LOCKED = 3,\n};\n\nenum {\n\tX86_64_FMT_P = 1ULL,\n\tX86_64_FMT_RW = 2ULL,\n\tX86_64_FMT_U = 4ULL,\n\tX86_64_FMT_A = 32ULL,\n\tX86_64_FMT_D = 64ULL,\n\tX86_64_FMT_OA = 4503599627366400ULL,\n\tX86_64_FMT_XD = 9223372036854775808ULL,\n};\n\nenum {\n\tX86_64_FMT_PS = 128,\n};\n\nenum {\n\tX86_BR_NONE = 0,\n\tX86_BR_USER = 1,\n\tX86_BR_KERNEL = 2,\n\tX86_BR_CALL = 4,\n\tX86_BR_RET = 8,\n\tX86_BR_SYSCALL = 16,\n\tX86_BR_SYSRET = 32,\n\tX86_BR_INT = 64,\n\tX86_BR_IRET = 128,\n\tX86_BR_JCC = 256,\n\tX86_BR_JMP = 512,\n\tX86_BR_IRQ = 1024,\n\tX86_BR_IND_CALL = 2048,\n\tX86_BR_ABORT = 4096,\n\tX86_BR_IN_TX = 8192,\n\tX86_BR_NO_TX = 16384,\n\tX86_BR_ZERO_CALL = 32768,\n\tX86_BR_CALL_STACK = 65536,\n\tX86_BR_IND_JMP = 131072,\n\tX86_BR_TYPE_SAVE = 262144,\n};\n\nenum {\n\tX86_IRQ_ALLOC_LEGACY = 1,\n};\n\nenum {\n\tX86_PERF_KFREE_SHARED = 0,\n\tX86_PERF_KFREE_EXCL = 1,\n\tX86_PERF_KFREE_MAX = 2,\n};\n\nenum {\n\tX86_USER_RDPMC_NEVER_ENABLE = 0,\n\tX86_USER_RDPMC_CONDITIONAL_ENABLE = 1,\n\tX86_USER_RDPMC_ALWAYS_ENABLE = 2,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_DEV_OFFLOAD_IN = 1,\n\tXFRM_DEV_OFFLOAD_OUT = 2,\n\tXFRM_DEV_OFFLOAD_FWD = 3,\n};\n\nenum {\n\tXFRM_DEV_OFFLOAD_UNSPECIFIED = 0,\n\tXFRM_DEV_OFFLOAD_CRYPTO = 1,\n\tXFRM_DEV_OFFLOAD_PACKET = 2,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MODE_FLAG_TUNNEL = 1,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tXFRM_SHARE_ANY = 0,\n\tXFRM_SHARE_SESSION = 1,\n\tXFRM_SHARE_USER = 2,\n\tXFRM_SHARE_UNIQUE = 3,\n};\n\nenum {\n\tXFRM_STATE_VOID = 0,\n\tXFRM_STATE_ACQ = 1,\n\tXFRM_STATE_VALID = 2,\n\tXFRM_STATE_ERROR = 3,\n\tXFRM_STATE_EXPIRED = 4,\n\tXFRM_STATE_DEAD = 5,\n};\n\nenum {\n\tXPT_BUSY = 0,\n\tXPT_CONN = 1,\n\tXPT_CLOSE = 2,\n\tXPT_DATA = 3,\n\tXPT_TEMP = 4,\n\tXPT_DEAD = 5,\n\tXPT_CHNGBUF = 6,\n\tXPT_DEFERRED = 7,\n\tXPT_OLD = 8,\n\tXPT_LISTENER = 9,\n\tXPT_CACHE_AUTH = 10,\n\tXPT_LOCAL = 11,\n\tXPT_KILL_TEMP = 12,\n\tXPT_CONG_CTRL = 13,\n\tXPT_HANDSHAKE = 14,\n\tXPT_TLS_SESSION = 15,\n\tXPT_PEER_AUTH = 16,\n\tXPT_PEER_VALID = 17,\n\tXPT_RPCB_UNREG = 18,\n};\n\nenum {\n\tXT_CONNTRACK_STATE = 1,\n\tXT_CONNTRACK_PROTO = 2,\n\tXT_CONNTRACK_ORIGSRC = 4,\n\tXT_CONNTRACK_ORIGDST = 8,\n\tXT_CONNTRACK_REPLSRC = 16,\n\tXT_CONNTRACK_REPLDST = 32,\n\tXT_CONNTRACK_STATUS = 64,\n\tXT_CONNTRACK_EXPIRES = 128,\n\tXT_CONNTRACK_ORIGSRC_PORT = 256,\n\tXT_CONNTRACK_ORIGDST_PORT = 512,\n\tXT_CONNTRACK_REPLSRC_PORT = 1024,\n\tXT_CONNTRACK_REPLDST_PORT = 2048,\n\tXT_CONNTRACK_DIRECTION = 4096,\n\tXT_CONNTRACK_STATE_ALIAS = 8192,\n};\n\nenum {\n\tY2_ASF_OS_PRES = 16,\n\tY2_ASF_RESET = 8,\n\tY2_ASF_RUNNING = 4,\n\tY2_ASF_CLR_HSTI = 2,\n\tY2_ASF_IRQ = 1,\n\tY2_ASF_UC_STATE = 12,\n\tY2_ASF_CLK_HALT = 0,\n};\n\nenum {\n\tY2_B8_PREF_REGS = 1104,\n\tPREF_UNIT_CTRL = 0,\n\tPREF_UNIT_LAST_IDX = 4,\n\tPREF_UNIT_ADDR_LO = 8,\n\tPREF_UNIT_ADDR_HI = 12,\n\tPREF_UNIT_GET_IDX = 16,\n\tPREF_UNIT_PUT_IDX = 20,\n\tPREF_UNIT_FIFO_WP = 32,\n\tPREF_UNIT_FIFO_RP = 36,\n\tPREF_UNIT_FIFO_WM = 40,\n\tPREF_UNIT_FIFO_LEV = 44,\n\tPREF_UNIT_MASK_IDX = 4095,\n};\n\nenum {\n\tY2_CLK_DIV_VAL_MSK = 16711680,\n\tY2_CLK_DIV_VAL2_MSK = 14680064,\n\tY2_CLK_SELECT2_MSK = 2031616,\n\tY2_CLK_DIV_ENA = 2,\n\tY2_CLK_DIV_DIS = 1,\n};\n\nenum {\n\tY2_IS_HW_ERR = -2147483648,\n\tY2_IS_STAT_BMU = 1073741824,\n\tY2_IS_ASF = 536870912,\n\tY2_IS_CPU_TO = 268435456,\n\tY2_IS_POLL_CHK = 134217728,\n\tY2_IS_TWSI_RDY = 67108864,\n\tY2_IS_IRQ_SW = 33554432,\n\tY2_IS_TIMINT = 16777216,\n\tY2_IS_IRQ_PHY2 = 4096,\n\tY2_IS_IRQ_MAC2 = 2048,\n\tY2_IS_CHK_RX2 = 1024,\n\tY2_IS_CHK_TXS2 = 512,\n\tY2_IS_CHK_TXA2 = 256,\n\tY2_IS_PSM_ACK = 128,\n\tY2_IS_PTP_TIST = 64,\n\tY2_IS_PHY_QLNK = 32,\n\tY2_IS_IRQ_PHY1 = 16,\n\tY2_IS_IRQ_MAC1 = 8,\n\tY2_IS_CHK_RX1 = 4,\n\tY2_IS_CHK_TXS1 = 2,\n\tY2_IS_CHK_TXA1 = 1,\n\tY2_IS_BASE = -1073741824,\n\tY2_IS_PORT_1 = 29,\n\tY2_IS_PORT_2 = 7424,\n\tY2_IS_ERROR = -2147480307,\n};\n\nenum {\n\tY2_IS_TIST_OV = 536870912,\n\tY2_IS_SENSOR = 268435456,\n\tY2_IS_MST_ERR = 134217728,\n\tY2_IS_IRQ_STAT = 67108864,\n\tY2_IS_PCI_EXP = 33554432,\n\tY2_IS_PCI_NEXP = 16777216,\n\tY2_IS_PAR_RD2 = 8192,\n\tY2_IS_PAR_WR2 = 4096,\n\tY2_IS_PAR_MAC2 = 2048,\n\tY2_IS_PAR_RX2 = 1024,\n\tY2_IS_TCP_TXS2 = 512,\n\tY2_IS_TCP_TXA2 = 256,\n\tY2_IS_PAR_RD1 = 32,\n\tY2_IS_PAR_WR1 = 16,\n\tY2_IS_PAR_MAC1 = 8,\n\tY2_IS_PAR_RX1 = 4,\n\tY2_IS_TCP_TXS1 = 2,\n\tY2_IS_TCP_TXA1 = 1,\n\tY2_HWE_L1_MASK = 63,\n\tY2_HWE_L2_MASK = 16128,\n\tY2_HWE_ALL_MASK = 738213695,\n};\n\nenum {\n\tY2_STATUS_LNK2_INAC = 128,\n\tY2_CLK_GAT_LNK2_DIS = 64,\n\tY2_COR_CLK_LNK2_DIS = 32,\n\tY2_PCI_CLK_LNK2_DIS = 16,\n\tY2_STATUS_LNK1_INAC = 8,\n\tY2_CLK_GAT_LNK1_DIS = 4,\n\tY2_COR_CLK_LNK1_DIS = 2,\n\tY2_PCI_CLK_LNK1_DIS = 1,\n};\n\nenum {\n\tY2_VMAIN_AVAIL = 131072,\n\tY2_VAUX_AVAIL = 65536,\n\tY2_HW_WOL_ON = 32768,\n\tY2_HW_WOL_OFF = 16384,\n\tY2_ASF_ENABLE = 8192,\n\tY2_ASF_DISABLE = 4096,\n\tY2_CLK_RUN_ENA = 2048,\n\tY2_CLK_RUN_DIS = 1024,\n\tY2_LED_STAT_ON = 512,\n\tY2_LED_STAT_OFF = 256,\n\tCS_ST_SW_IRQ = 128,\n\tCS_CL_SW_IRQ = 64,\n\tCS_STOP_DONE = 32,\n\tCS_STOP_MAST = 16,\n\tCS_MRST_CLR = 8,\n\tCS_MRST_SET = 4,\n\tCS_RST_CLR = 2,\n\tCS_RST_SET = 1,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tZONELIST_NOFALLBACK = 1,\n\tMAX_ZONELISTS = 2,\n};\n\nenum {\n\t_DQUOT_USAGE_ENABLED = 0,\n\t_DQUOT_LIMITS_ENABLED = 1,\n\t_DQUOT_SUSPENDED = 2,\n\t_DQUOT_STATE_FLAGS = 3,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 0,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t__I915_SAMPLE_FREQ_ACT = 0,\n\t__I915_SAMPLE_FREQ_REQ = 1,\n\t__I915_SAMPLE_RC6 = 2,\n\t__I915_SAMPLE_RC6_LAST_REPORTED = 3,\n\t__I915_NUM_PMU_SAMPLERS = 4,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 10,\n\t__SCHED_FEAT_HRTICK = 11,\n\t__SCHED_FEAT_HRTICK_DL = 12,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 13,\n\t__SCHED_FEAT_TTWU_QUEUE = 14,\n\t__SCHED_FEAT_SIS_UTIL = 15,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 16,\n\t__SCHED_FEAT_RT_PUSH_IPI = 17,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 18,\n\t__SCHED_FEAT_LB_MIN = 19,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 20,\n\t__SCHED_FEAT_WA_IDLE = 21,\n\t__SCHED_FEAT_WA_WEIGHT = 22,\n\t__SCHED_FEAT_WA_BIAS = 23,\n\t__SCHED_FEAT_UTIL_EST = 24,\n\t__SCHED_FEAT_LATENCY_WARN = 25,\n\t__SCHED_FEAT_NI_RANDOM = 26,\n\t__SCHED_FEAT_NR = 27,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NO_OBJ_EXT_BIT = 24,\n\t___GFP_LAST_BIT = 25,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 4,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 5,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 7,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 8,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 9,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 10,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 11,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 12,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 13,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 14,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 15,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 16,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 17,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 18,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 19,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 20,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 21,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 22,\n\t__ctx_convertBPF_PROG_TYPE_NETFILTER = 23,\n\t__ctx_convert_unused = 24,\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_sra_exceeded_retry_limit = 5,\n\tattr_inode_readahead = 6,\n\tattr_trigger_test_error = 7,\n\tattr_first_error_time = 8,\n\tattr_last_error_time = 9,\n\tattr_clusters_in_group = 10,\n\tattr_mb_order = 11,\n\tattr_feature = 12,\n\tattr_pointer_pi = 13,\n\tattr_pointer_ui = 14,\n\tattr_pointer_ul = 15,\n\tattr_pointer_u64 = 16,\n\tattr_pointer_u8 = 17,\n\tattr_pointer_string = 18,\n\tattr_pointer_atomic = 19,\n\tattr_journal_task = 20,\n\tattr_err_report_sec = 21,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\te1000_10_half = 0,\n\te1000_10_full = 1,\n\te1000_100_half = 2,\n\te1000_100_full = 3,\n};\n\nenum {\n\te1000_igp_cable_length_10 = 10,\n\te1000_igp_cable_length_20 = 20,\n\te1000_igp_cable_length_30 = 30,\n\te1000_igp_cable_length_40 = 40,\n\te1000_igp_cable_length_50 = 50,\n\te1000_igp_cable_length_60 = 60,\n\te1000_igp_cable_length_70 = 70,\n\te1000_igp_cable_length_80 = 80,\n\te1000_igp_cable_length_90 = 90,\n\te1000_igp_cable_length_100 = 100,\n\te1000_igp_cable_length_110 = 110,\n\te1000_igp_cable_length_115 = 115,\n\te1000_igp_cable_length_120 = 120,\n\te1000_igp_cable_length_130 = 130,\n\te1000_igp_cable_length_140 = 140,\n\te1000_igp_cable_length_150 = 150,\n\te1000_igp_cable_length_160 = 160,\n\te1000_igp_cable_length_170 = 170,\n\te1000_igp_cable_length_180 = 180,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\tmechtype_caddy = 0,\n\tmechtype_tray = 1,\n\tmechtype_popup = 2,\n\tmechtype_individual_changer = 4,\n\tmechtype_cartridge_changer = 5,\n};\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tpreempt_dynamic_undefined = -1,\n\tpreempt_dynamic_none = 0,\n\tpreempt_dynamic_voluntary = 1,\n\tpreempt_dynamic_full = 2,\n\tpreempt_dynamic_lazy = 3,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\nenum {\n\tst_wordstart = 0,\n\tst_wordcmp = 1,\n\tst_wordskip = 2,\n\tst_bufcpy = 3,\n};\n\nenum {\n\tst_wordstart___2 = 0,\n\tst_wordcmp___2 = 1,\n\tst_wordskip___2 = 2,\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\nenum {\n\tx86_lbr_exclusive_lbr = 0,\n\tx86_lbr_exclusive_bts = 1,\n\tx86_lbr_exclusive_pt = 2,\n\tx86_lbr_exclusive_max = 3,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tOSL_GLOBAL_LOCK_HANDLER = 0,\n\tOSL_NOTIFY_HANDLER = 1,\n\tOSL_GPE_HANDLER = 2,\n\tOSL_DEBUGGER_MAIN_THREAD = 3,\n\tOSL_DEBUGGER_EXEC_THREAD = 4,\n\tOSL_EC_POLL_HANDLER = 5,\n\tOSL_EC_BURST_HANDLER = 6,\n} acpi_execute_type;\n\ntypedef enum {\n\tACPI_IMODE_LOAD_PASS1 = 1,\n\tACPI_IMODE_LOAD_PASS2 = 2,\n\tACPI_IMODE_EXECUTE = 3,\n} acpi_interpreter_mode;\n\ntypedef enum {\n\tACPI_TRACE_AML_METHOD = 0,\n\tACPI_TRACE_AML_OPCODE = 1,\n\tACPI_TRACE_AML_REGION = 2,\n} acpi_trace_event_type;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tneed_more = 0,\n\tblock_done = 1,\n\tfinish_started = 2,\n\tfinish_done = 3,\n} block_state;\n\ntypedef enum {\n\tCH_8139 = 0,\n\tCH_8139_K = 1,\n\tCH_8139A = 2,\n\tCH_8139A_G = 3,\n\tCH_8139B = 4,\n\tCH_8130 = 5,\n\tCH_8139C = 6,\n\tCH_8100 = 7,\n\tCH_8100B_8139D = 8,\n\tCH_8101 = 9,\n} chip_t;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\ntypedef enum {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok = 1,\n\te1000_1000t_rx_status_undefined = 255,\n} e1000_1000t_rx_status;\n\ntypedef enum {\n\te1000_10bt_ext_dist_enable_normal = 0,\n\te1000_10bt_ext_dist_enable_lower = 1,\n\te1000_10bt_ext_dist_enable_undefined = 255,\n} e1000_10bt_ext_dist_enable;\n\ntypedef enum {\n\te1000_auto_x_mode_manual_mdi = 0,\n\te1000_auto_x_mode_manual_mdix = 1,\n\te1000_auto_x_mode_auto1 = 2,\n\te1000_auto_x_mode_auto2 = 3,\n\te1000_auto_x_mode_undefined = 255,\n} e1000_auto_x_mode;\n\ntypedef enum {\n\te1000_bus_speed_unknown = 0,\n\te1000_bus_speed_33 = 1,\n\te1000_bus_speed_66 = 2,\n\te1000_bus_speed_100 = 3,\n\te1000_bus_speed_120 = 4,\n\te1000_bus_speed_133 = 5,\n\te1000_bus_speed_reserved = 6,\n} e1000_bus_speed;\n\ntypedef enum {\n\te1000_bus_type_unknown = 0,\n\te1000_bus_type_pci = 1,\n\te1000_bus_type_pcix = 2,\n\te1000_bus_type_reserved = 3,\n} e1000_bus_type;\n\ntypedef enum {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_32 = 1,\n\te1000_bus_width_64 = 2,\n\te1000_bus_width_reserved = 3,\n} e1000_bus_width;\n\ntypedef enum {\n\te1000_cable_length_50 = 0,\n\te1000_cable_length_50_80 = 1,\n\te1000_cable_length_80_110 = 2,\n\te1000_cable_length_110_140 = 3,\n\te1000_cable_length_140 = 4,\n\te1000_cable_length_undefined = 255,\n} e1000_cable_length;\n\ntypedef enum {\n\te1000_downshift_normal = 0,\n\te1000_downshift_activated = 1,\n\te1000_downshift_undefined = 255,\n} e1000_downshift;\n\ntypedef enum {\n\te1000_dsp_config_disabled = 0,\n\te1000_dsp_config_enabled = 1,\n\te1000_dsp_config_activated = 2,\n\te1000_dsp_config_undefined = 255,\n} e1000_dsp_config;\n\ntypedef enum {\n\te1000_eeprom_uninitialized = 0,\n\te1000_eeprom_spi = 1,\n\te1000_eeprom_microwire = 2,\n\te1000_eeprom_flash = 3,\n\te1000_eeprom_none = 4,\n\te1000_num_eeprom_types = 5,\n} e1000_eeprom_type;\n\ntypedef enum {\n\tE1000_FC_NONE = 0,\n\tE1000_FC_RX_PAUSE = 1,\n\tE1000_FC_TX_PAUSE = 2,\n\tE1000_FC_FULL = 3,\n\tE1000_FC_DEFAULT = 255,\n} e1000_fc_type;\n\ntypedef enum {\n\te1000_ffe_config_enabled = 0,\n\te1000_ffe_config_active = 1,\n\te1000_ffe_config_blocked = 2,\n} e1000_ffe_config;\n\ntypedef enum {\n\te1000_undefined = 0,\n\te1000_82542_rev2_0 = 1,\n\te1000_82542_rev2_1 = 2,\n\te1000_82543 = 3,\n\te1000_82544 = 4,\n\te1000_82540 = 5,\n\te1000_82545 = 6,\n\te1000_82545_rev_3 = 7,\n\te1000_82546 = 8,\n\te1000_ce4100 = 9,\n\te1000_82546_rev_3 = 10,\n\te1000_82541 = 11,\n\te1000_82541_rev_2 = 12,\n\te1000_82547 = 13,\n\te1000_82547_rev_2 = 14,\n\te1000_num_macs = 15,\n} e1000_mac_type;\n\ntypedef enum {\n\te1000_media_type_copper = 0,\n\te1000_media_type_fiber = 1,\n\te1000_media_type_internal_serdes = 2,\n\te1000_num_media_types = 3,\n} e1000_media_type;\n\ntypedef enum {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master = 1,\n\te1000_ms_force_slave = 2,\n\te1000_ms_auto = 3,\n} e1000_ms_type;\n\ntypedef enum {\n\te1000_phy_m88 = 0,\n\te1000_phy_igp = 1,\n\te1000_phy_8211 = 2,\n\te1000_phy_8201 = 3,\n\te1000_phy_undefined = 255,\n} e1000_phy_type;\n\ntypedef enum {\n\te1000_polarity_reversal_enabled = 0,\n\te1000_polarity_reversal_disabled = 1,\n\te1000_polarity_reversal_undefined = 255,\n} e1000_polarity_reversal;\n\ntypedef enum {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed = 1,\n\te1000_rev_polarity_undefined = 255,\n} e1000_rev_polarity;\n\ntypedef enum {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on = 1,\n\te1000_smart_speed_off = 2,\n} e1000_smart_speed;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n\tEXT4_IGET_BAD = 4,\n\tEXT4_IGET_EA_INODE = 8,\n} ext4_iget_flags;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tMAP_CHG_REUSE = 0,\n\tMAP_CHG_NEEDED = 1,\n\tMAP_CHG_ENFORCED = 2,\n} map_chg_state;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tSTATUSTYPE_INFO = 0,\n\tSTATUSTYPE_TABLE = 1,\n\tSTATUSTYPE_IMA = 2,\n} status_type_t;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum CSCRBits {\n\tCSCR_LinkOKBit = 1024,\n\tCSCR_LinkChangeBit = 2048,\n\tCSCR_LinkStatusBits = 61440,\n\tCSCR_LinkDownOffCmd = 960,\n\tCSCR_LinkDownCmd = 62400,\n};\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum Cfg9346Bits {\n\tCfg9346_Lock = 0,\n\tCfg9346_Unlock = 192,\n};\n\nenum ChipCmdBits {\n\tCmdReset = 16,\n\tCmdRxEnb = 8,\n\tCmdTxEnb = 4,\n\tRxBufEmpty = 1,\n};\n\nenum ClearBitMasks {\n\tMultiIntrClear = 61440,\n\tChipCmdClear = 226,\n\tConfig1Clear = 206,\n};\n\nenum Config1Bits {\n\tCfg1_PM_Enable = 1,\n\tCfg1_VPD_Enable = 2,\n\tCfg1_PIO = 4,\n\tCfg1_MMIO = 8,\n\tLWAKE = 16,\n\tCfg1_Driver_Load = 32,\n\tCfg1_LED0 = 64,\n\tCfg1_LED1 = 128,\n\tSLEEP = 2,\n\tPWRDN = 1,\n};\n\nenum Config3Bits {\n\tCfg3_FBtBEn = 1,\n\tCfg3_FuncRegEn = 2,\n\tCfg3_CLKRUN_En = 4,\n\tCfg3_CardB_En = 8,\n\tCfg3_LinkUp = 16,\n\tCfg3_Magic = 32,\n\tCfg3_PARM_En = 64,\n\tCfg3_GNTSel = 128,\n};\n\nenum Config4Bits {\n\tLWPTN = 4,\n};\n\nenum Config5Bits {\n\tCfg5_PME_STS = 1,\n\tCfg5_LANWake = 2,\n\tCfg5_LDPS = 4,\n\tCfg5_FIFOAddrPtr = 8,\n\tCfg5_UWF = 16,\n\tCfg5_MWF = 32,\n\tCfg5_BWF = 64,\n};\n\nenum IntrStatusBits {\n\tPCIErr = 32768,\n\tPCSTimeout = 16384,\n\tRxFIFOOver = 64,\n\tRxUnderrun = 32,\n\tRxOverflow = 16,\n\tTxErr = 8,\n\tTxOK = 4,\n\tRxErr = 2,\n\tRxOK = 1,\n\tRxAckBits = 81,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecPublicKey = 2,\n\tOID_id_prime192v1 = 3,\n\tOID_id_prime256v1 = 4,\n\tOID_id_ecdsa_with_sha1 = 5,\n\tOID_id_ecdsa_with_sha224 = 6,\n\tOID_id_ecdsa_with_sha256 = 7,\n\tOID_id_ecdsa_with_sha384 = 8,\n\tOID_id_ecdsa_with_sha512 = 9,\n\tOID_rsaEncryption = 10,\n\tOID_sha1WithRSAEncryption = 11,\n\tOID_sha256WithRSAEncryption = 12,\n\tOID_sha384WithRSAEncryption = 13,\n\tOID_sha512WithRSAEncryption = 14,\n\tOID_sha224WithRSAEncryption = 15,\n\tOID_data = 16,\n\tOID_signed_data = 17,\n\tOID_email_address = 18,\n\tOID_contentType = 19,\n\tOID_messageDigest = 20,\n\tOID_signingTime = 21,\n\tOID_smimeCapabilites = 22,\n\tOID_smimeAuthenticatedAttrs = 23,\n\tOID_mskrb5 = 24,\n\tOID_krb5 = 25,\n\tOID_krb5u2u = 26,\n\tOID_msIndirectData = 27,\n\tOID_msStatementType = 28,\n\tOID_msSpOpusInfo = 29,\n\tOID_msPeImageDataObjId = 30,\n\tOID_msIndividualSPKeyPurpose = 31,\n\tOID_msOutlookExpress = 32,\n\tOID_ntlmssp = 33,\n\tOID_negoex = 34,\n\tOID_spnego = 35,\n\tOID_IAKerb = 36,\n\tOID_PKU2U = 37,\n\tOID_Scram = 38,\n\tOID_certAuthInfoAccess = 39,\n\tOID_sha1 = 40,\n\tOID_id_ansip384r1 = 41,\n\tOID_id_ansip521r1 = 42,\n\tOID_sha256 = 43,\n\tOID_sha384 = 44,\n\tOID_sha512 = 45,\n\tOID_sha224 = 46,\n\tOID_commonName = 47,\n\tOID_surname = 48,\n\tOID_countryName = 49,\n\tOID_locality = 50,\n\tOID_stateOrProvinceName = 51,\n\tOID_organizationName = 52,\n\tOID_organizationUnitName = 53,\n\tOID_title = 54,\n\tOID_description = 55,\n\tOID_name = 56,\n\tOID_givenName = 57,\n\tOID_initials = 58,\n\tOID_generationalQualifier = 59,\n\tOID_subjectKeyIdentifier = 60,\n\tOID_keyUsage = 61,\n\tOID_subjectAltName = 62,\n\tOID_issuerAltName = 63,\n\tOID_basicConstraints = 64,\n\tOID_crlDistributionPoints = 65,\n\tOID_certPolicies = 66,\n\tOID_authorityKeyIdentifier = 67,\n\tOID_extKeyUsage = 68,\n\tOID_NetlogonMechanism = 69,\n\tOID_appleLocalKdcSupported = 70,\n\tOID_gostCPSignA = 71,\n\tOID_gostCPSignB = 72,\n\tOID_gostCPSignC = 73,\n\tOID_gost2012PKey256 = 74,\n\tOID_gost2012PKey512 = 75,\n\tOID_gost2012Digest256 = 76,\n\tOID_gost2012Digest512 = 77,\n\tOID_gost2012Signature256 = 78,\n\tOID_gost2012Signature512 = 79,\n\tOID_gostTC26Sign256A = 80,\n\tOID_gostTC26Sign256B = 81,\n\tOID_gostTC26Sign256C = 82,\n\tOID_gostTC26Sign256D = 83,\n\tOID_gostTC26Sign512A = 84,\n\tOID_gostTC26Sign512B = 85,\n\tOID_gostTC26Sign512C = 86,\n\tOID_sm2 = 87,\n\tOID_sm3 = 88,\n\tOID_SM2_with_SM3 = 89,\n\tOID_sm3WithRSAEncryption = 90,\n\tOID_TPMLoadableKey = 91,\n\tOID_TPMImportableKey = 92,\n\tOID_TPMSealedData = 93,\n\tOID_sha3_256 = 94,\n\tOID_sha3_384 = 95,\n\tOID_sha3_512 = 96,\n\tOID_id_ecdsa_with_sha3_256 = 97,\n\tOID_id_ecdsa_with_sha3_384 = 98,\n\tOID_id_ecdsa_with_sha3_512 = 99,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102,\n\tOID_id_ml_dsa_44 = 103,\n\tOID_id_ml_dsa_65 = 104,\n\tOID_id_ml_dsa_87 = 105,\n\tOID__NR = 106,\n};\n\nenum P4_ESCR_EMASKS {\n\tP4_EVENT_TC_DELIVER_MODE__DD = 512,\n\tP4_EVENT_TC_DELIVER_MODE__DB = 1024,\n\tP4_EVENT_TC_DELIVER_MODE__DI = 2048,\n\tP4_EVENT_TC_DELIVER_MODE__BD = 4096,\n\tP4_EVENT_TC_DELIVER_MODE__BB = 8192,\n\tP4_EVENT_TC_DELIVER_MODE__BI = 16384,\n\tP4_EVENT_TC_DELIVER_MODE__ID = 32768,\n\tP4_EVENT_BPU_FETCH_REQUEST__TCMISS = 512,\n\tP4_EVENT_ITLB_REFERENCE__HIT = 512,\n\tP4_EVENT_ITLB_REFERENCE__MISS = 1024,\n\tP4_EVENT_ITLB_REFERENCE__HIT_UK = 2048,\n\tP4_EVENT_MEMORY_CANCEL__ST_RB_FULL = 2048,\n\tP4_EVENT_MEMORY_CANCEL__64K_CONF = 4096,\n\tP4_EVENT_MEMORY_COMPLETE__LSC = 512,\n\tP4_EVENT_MEMORY_COMPLETE__SSC = 1024,\n\tP4_EVENT_LOAD_PORT_REPLAY__SPLIT_LD = 1024,\n\tP4_EVENT_STORE_PORT_REPLAY__SPLIT_ST = 1024,\n\tP4_EVENT_MOB_LOAD_REPLAY__NO_STA = 1024,\n\tP4_EVENT_MOB_LOAD_REPLAY__NO_STD = 4096,\n\tP4_EVENT_MOB_LOAD_REPLAY__PARTIAL_DATA = 8192,\n\tP4_EVENT_MOB_LOAD_REPLAY__UNALGN_ADDR = 16384,\n\tP4_EVENT_PAGE_WALK_TYPE__DTMISS = 512,\n\tP4_EVENT_PAGE_WALK_TYPE__ITMISS = 1024,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITS = 512,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITE = 1024,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITM = 2048,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITS = 4096,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITE = 8192,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITM = 16384,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_MISS = 131072,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_MISS = 262144,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__WR_2ndL_MISS = 524288,\n\tP4_EVENT_IOQ_ALLOCATION__DEFAULT = 512,\n\tP4_EVENT_IOQ_ALLOCATION__ALL_READ = 16384,\n\tP4_EVENT_IOQ_ALLOCATION__ALL_WRITE = 32768,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_UC = 65536,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WC = 131072,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WT = 262144,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WP = 524288,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WB = 1048576,\n\tP4_EVENT_IOQ_ALLOCATION__OWN = 4194304,\n\tP4_EVENT_IOQ_ALLOCATION__OTHER = 8388608,\n\tP4_EVENT_IOQ_ALLOCATION__PREFETCH = 16777216,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__DEFAULT = 512,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_READ = 16384,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_WRITE = 32768,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_UC = 65536,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WC = 131072,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WT = 262144,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WP = 524288,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WB = 1048576,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__OWN = 4194304,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__OTHER = 8388608,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__PREFETCH = 16777216,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_DRV = 512,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_OWN = 1024,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_OTHER = 2048,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_DRV = 4096,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_OWN = 8192,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_OTHER = 16384,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_TYPE0 = 512,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_TYPE1 = 1024,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LEN0 = 2048,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LEN1 = 4096,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_IO_TYPE = 16384,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LOCK_TYPE = 32768,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_CACHE_TYPE = 65536,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_SPLIT_TYPE = 131072,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_DEM_TYPE = 262144,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_ORD_TYPE = 524288,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE0 = 1048576,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE1 = 2097152,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE2 = 4194304,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE0 = 512,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE1 = 1024,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN0 = 2048,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN1 = 4096,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_IO_TYPE = 16384,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LOCK_TYPE = 32768,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_CACHE_TYPE = 65536,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_SPLIT_TYPE = 131072,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_DEM_TYPE = 262144,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_ORD_TYPE = 524288,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE0 = 1048576,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE1 = 2097152,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE2 = 4194304,\n\tP4_EVENT_SSE_INPUT_ASSIST__ALL = 16777216,\n\tP4_EVENT_PACKED_SP_UOP__ALL = 16777216,\n\tP4_EVENT_PACKED_DP_UOP__ALL = 16777216,\n\tP4_EVENT_SCALAR_SP_UOP__ALL = 16777216,\n\tP4_EVENT_SCALAR_DP_UOP__ALL = 16777216,\n\tP4_EVENT_64BIT_MMX_UOP__ALL = 16777216,\n\tP4_EVENT_128BIT_MMX_UOP__ALL = 16777216,\n\tP4_EVENT_X87_FP_UOP__ALL = 16777216,\n\tP4_EVENT_TC_MISC__FLUSH = 8192,\n\tP4_EVENT_GLOBAL_POWER_EVENTS__RUNNING = 512,\n\tP4_EVENT_TC_MS_XFER__CISC = 512,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_TC_BUILD = 512,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_TC_DELIVER = 1024,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_ROM = 2048,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CONDITIONAL = 1024,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CALL = 2048,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__RETURN = 4096,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__INDIRECT = 8192,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__CONDITIONAL = 1024,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__CALL = 2048,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__RETURN = 4096,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__INDIRECT = 8192,\n\tP4_EVENT_RESOURCE_STALL__SBFULL = 16384,\n\tP4_EVENT_WC_BUFFER__WCB_EVICTS = 512,\n\tP4_EVENT_WC_BUFFER__WCB_FULL_EVICTS = 1024,\n\tP4_EVENT_FRONT_END_EVENT__NBOGUS = 512,\n\tP4_EVENT_FRONT_END_EVENT__BOGUS = 1024,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS0 = 512,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS1 = 1024,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS2 = 2048,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS3 = 4096,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS0 = 8192,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS1 = 16384,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS2 = 32768,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS3 = 65536,\n\tP4_EVENT_REPLAY_EVENT__NBOGUS = 512,\n\tP4_EVENT_REPLAY_EVENT__BOGUS = 1024,\n\tP4_EVENT_INSTR_RETIRED__NBOGUSNTAG = 512,\n\tP4_EVENT_INSTR_RETIRED__NBOGUSTAG = 1024,\n\tP4_EVENT_INSTR_RETIRED__BOGUSNTAG = 2048,\n\tP4_EVENT_INSTR_RETIRED__BOGUSTAG = 4096,\n\tP4_EVENT_UOPS_RETIRED__NBOGUS = 512,\n\tP4_EVENT_UOPS_RETIRED__BOGUS = 1024,\n\tP4_EVENT_UOP_TYPE__TAGLOADS = 1024,\n\tP4_EVENT_UOP_TYPE__TAGSTORES = 2048,\n\tP4_EVENT_BRANCH_RETIRED__MMNP = 512,\n\tP4_EVENT_BRANCH_RETIRED__MMNM = 1024,\n\tP4_EVENT_BRANCH_RETIRED__MMTP = 2048,\n\tP4_EVENT_BRANCH_RETIRED__MMTM = 4096,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED__NBOGUS = 512,\n\tP4_EVENT_X87_ASSIST__FPSU = 512,\n\tP4_EVENT_X87_ASSIST__FPSO = 1024,\n\tP4_EVENT_X87_ASSIST__POAO = 2048,\n\tP4_EVENT_X87_ASSIST__POAU = 4096,\n\tP4_EVENT_X87_ASSIST__PREA = 8192,\n\tP4_EVENT_MACHINE_CLEAR__CLEAR = 512,\n\tP4_EVENT_MACHINE_CLEAR__MOCLEAR = 1024,\n\tP4_EVENT_MACHINE_CLEAR__SMCLEAR = 2048,\n\tP4_EVENT_INSTR_COMPLETED__NBOGUS = 512,\n\tP4_EVENT_INSTR_COMPLETED__BOGUS = 1024,\n};\n\nenum P4_EVENTS {\n\tP4_EVENT_TC_DELIVER_MODE = 0,\n\tP4_EVENT_BPU_FETCH_REQUEST = 1,\n\tP4_EVENT_ITLB_REFERENCE = 2,\n\tP4_EVENT_MEMORY_CANCEL = 3,\n\tP4_EVENT_MEMORY_COMPLETE = 4,\n\tP4_EVENT_LOAD_PORT_REPLAY = 5,\n\tP4_EVENT_STORE_PORT_REPLAY = 6,\n\tP4_EVENT_MOB_LOAD_REPLAY = 7,\n\tP4_EVENT_PAGE_WALK_TYPE = 8,\n\tP4_EVENT_BSQ_CACHE_REFERENCE = 9,\n\tP4_EVENT_IOQ_ALLOCATION = 10,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES = 11,\n\tP4_EVENT_FSB_DATA_ACTIVITY = 12,\n\tP4_EVENT_BSQ_ALLOCATION = 13,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES = 14,\n\tP4_EVENT_SSE_INPUT_ASSIST = 15,\n\tP4_EVENT_PACKED_SP_UOP = 16,\n\tP4_EVENT_PACKED_DP_UOP = 17,\n\tP4_EVENT_SCALAR_SP_UOP = 18,\n\tP4_EVENT_SCALAR_DP_UOP = 19,\n\tP4_EVENT_64BIT_MMX_UOP = 20,\n\tP4_EVENT_128BIT_MMX_UOP = 21,\n\tP4_EVENT_X87_FP_UOP = 22,\n\tP4_EVENT_TC_MISC = 23,\n\tP4_EVENT_GLOBAL_POWER_EVENTS = 24,\n\tP4_EVENT_TC_MS_XFER = 25,\n\tP4_EVENT_UOP_QUEUE_WRITES = 26,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE = 27,\n\tP4_EVENT_RETIRED_BRANCH_TYPE = 28,\n\tP4_EVENT_RESOURCE_STALL = 29,\n\tP4_EVENT_WC_BUFFER = 30,\n\tP4_EVENT_B2B_CYCLES = 31,\n\tP4_EVENT_BNR = 32,\n\tP4_EVENT_SNOOP = 33,\n\tP4_EVENT_RESPONSE = 34,\n\tP4_EVENT_FRONT_END_EVENT = 35,\n\tP4_EVENT_EXECUTION_EVENT = 36,\n\tP4_EVENT_REPLAY_EVENT = 37,\n\tP4_EVENT_INSTR_RETIRED = 38,\n\tP4_EVENT_UOPS_RETIRED = 39,\n\tP4_EVENT_UOP_TYPE = 40,\n\tP4_EVENT_BRANCH_RETIRED = 41,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED = 42,\n\tP4_EVENT_X87_ASSIST = 43,\n\tP4_EVENT_MACHINE_CLEAR = 44,\n\tP4_EVENT_INSTR_COMPLETED = 45,\n};\n\nenum P4_EVENT_OPCODES {\n\tP4_EVENT_TC_DELIVER_MODE_OPCODE = 257,\n\tP4_EVENT_BPU_FETCH_REQUEST_OPCODE = 768,\n\tP4_EVENT_ITLB_REFERENCE_OPCODE = 6147,\n\tP4_EVENT_MEMORY_CANCEL_OPCODE = 517,\n\tP4_EVENT_MEMORY_COMPLETE_OPCODE = 2050,\n\tP4_EVENT_LOAD_PORT_REPLAY_OPCODE = 1026,\n\tP4_EVENT_STORE_PORT_REPLAY_OPCODE = 1282,\n\tP4_EVENT_MOB_LOAD_REPLAY_OPCODE = 770,\n\tP4_EVENT_PAGE_WALK_TYPE_OPCODE = 260,\n\tP4_EVENT_BSQ_CACHE_REFERENCE_OPCODE = 3079,\n\tP4_EVENT_IOQ_ALLOCATION_OPCODE = 774,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES_OPCODE = 6662,\n\tP4_EVENT_FSB_DATA_ACTIVITY_OPCODE = 5894,\n\tP4_EVENT_BSQ_ALLOCATION_OPCODE = 1287,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES_OPCODE = 1543,\n\tP4_EVENT_SSE_INPUT_ASSIST_OPCODE = 13313,\n\tP4_EVENT_PACKED_SP_UOP_OPCODE = 2049,\n\tP4_EVENT_PACKED_DP_UOP_OPCODE = 3073,\n\tP4_EVENT_SCALAR_SP_UOP_OPCODE = 2561,\n\tP4_EVENT_SCALAR_DP_UOP_OPCODE = 3585,\n\tP4_EVENT_64BIT_MMX_UOP_OPCODE = 513,\n\tP4_EVENT_128BIT_MMX_UOP_OPCODE = 6657,\n\tP4_EVENT_X87_FP_UOP_OPCODE = 1025,\n\tP4_EVENT_TC_MISC_OPCODE = 1537,\n\tP4_EVENT_GLOBAL_POWER_EVENTS_OPCODE = 4870,\n\tP4_EVENT_TC_MS_XFER_OPCODE = 1280,\n\tP4_EVENT_UOP_QUEUE_WRITES_OPCODE = 2304,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE_OPCODE = 1282,\n\tP4_EVENT_RETIRED_BRANCH_TYPE_OPCODE = 1026,\n\tP4_EVENT_RESOURCE_STALL_OPCODE = 257,\n\tP4_EVENT_WC_BUFFER_OPCODE = 1285,\n\tP4_EVENT_B2B_CYCLES_OPCODE = 5635,\n\tP4_EVENT_BNR_OPCODE = 2051,\n\tP4_EVENT_SNOOP_OPCODE = 1539,\n\tP4_EVENT_RESPONSE_OPCODE = 1027,\n\tP4_EVENT_FRONT_END_EVENT_OPCODE = 2053,\n\tP4_EVENT_EXECUTION_EVENT_OPCODE = 3077,\n\tP4_EVENT_REPLAY_EVENT_OPCODE = 2309,\n\tP4_EVENT_INSTR_RETIRED_OPCODE = 516,\n\tP4_EVENT_UOPS_RETIRED_OPCODE = 260,\n\tP4_EVENT_UOP_TYPE_OPCODE = 514,\n\tP4_EVENT_BRANCH_RETIRED_OPCODE = 1541,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED_OPCODE = 772,\n\tP4_EVENT_X87_ASSIST_OPCODE = 773,\n\tP4_EVENT_MACHINE_CLEAR_OPCODE = 517,\n\tP4_EVENT_INSTR_COMPLETED_OPCODE = 1796,\n};\n\nenum P4_PEBS_METRIC {\n\tP4_PEBS_METRIC__none = 0,\n\tP4_PEBS_METRIC__1stl_cache_load_miss_retired = 1,\n\tP4_PEBS_METRIC__2ndl_cache_load_miss_retired = 2,\n\tP4_PEBS_METRIC__dtlb_load_miss_retired = 3,\n\tP4_PEBS_METRIC__dtlb_store_miss_retired = 4,\n\tP4_PEBS_METRIC__dtlb_all_miss_retired = 5,\n\tP4_PEBS_METRIC__tagged_mispred_branch = 6,\n\tP4_PEBS_METRIC__mob_load_replay_retired = 7,\n\tP4_PEBS_METRIC__split_load_retired = 8,\n\tP4_PEBS_METRIC__split_store_retired = 9,\n\tP4_PEBS_METRIC__max = 10,\n};\n\nenum RTL8139_registers {\n\tMAC0 = 0,\n\tMAR0 = 8,\n\tTxStatus0 = 16,\n\tTxAddr0 = 32,\n\tRxBuf = 48,\n\tChipCmd = 55,\n\tRxBufPtr = 56,\n\tRxBufAddr = 58,\n\tIntrMask = 60,\n\tIntrStatus = 62,\n\tTxConfig = 64,\n\tRxConfig = 68,\n\tTimer = 72,\n\tRxMissed = 76,\n\tCfg9346 = 80,\n\tConfig0 = 81,\n\tConfig1 = 82,\n\tTimerInt = 84,\n\tMediaStatus = 88,\n\tConfig3 = 89,\n\tConfig4 = 90,\n\tHltClk = 91,\n\tMultiIntr = 92,\n\tTxSummary = 96,\n\tBasicModeCtrl = 98,\n\tBasicModeStatus = 100,\n\tNWayAdvert = 102,\n\tNWayLPAR = 104,\n\tNWayExpansion = 106,\n\tFIFOTMS = 112,\n\tCSCR = 116,\n\tPARA78 = 120,\n\tFlashReg = 212,\n\tPARA7c = 124,\n\tConfig5 = 216,\n};\n\nenum RxStatusBits {\n\tRxMulticast = 32768,\n\tRxPhysical = 16384,\n\tRxBroadcast = 8192,\n\tRxBadSymbol = 32,\n\tRxRunt = 16,\n\tRxTooLong = 8,\n\tRxCRCErr = 4,\n\tRxBadAlign = 2,\n\tRxStatusOK = 1,\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum TG3_FLAGS {\n\tTG3_FLAG_TAGGED_STATUS = 0,\n\tTG3_FLAG_TXD_MBOX_HWBUG = 1,\n\tTG3_FLAG_USE_LINKCHG_REG = 2,\n\tTG3_FLAG_ERROR_PROCESSED = 3,\n\tTG3_FLAG_ENABLE_ASF = 4,\n\tTG3_FLAG_ASPM_WORKAROUND = 5,\n\tTG3_FLAG_POLL_SERDES = 6,\n\tTG3_FLAG_POLL_CPMU_LINK = 7,\n\tTG3_FLAG_MBOX_WRITE_REORDER = 8,\n\tTG3_FLAG_PCIX_TARGET_HWBUG = 9,\n\tTG3_FLAG_WOL_SPEED_100MB = 10,\n\tTG3_FLAG_WOL_ENABLE = 11,\n\tTG3_FLAG_EEPROM_WRITE_PROT = 12,\n\tTG3_FLAG_NVRAM = 13,\n\tTG3_FLAG_NVRAM_BUFFERED = 14,\n\tTG3_FLAG_SUPPORT_MSI = 15,\n\tTG3_FLAG_SUPPORT_MSIX = 16,\n\tTG3_FLAG_USING_MSI = 17,\n\tTG3_FLAG_USING_MSIX = 18,\n\tTG3_FLAG_PCIX_MODE = 19,\n\tTG3_FLAG_PCI_HIGH_SPEED = 20,\n\tTG3_FLAG_PCI_32BIT = 21,\n\tTG3_FLAG_SRAM_USE_CONFIG = 22,\n\tTG3_FLAG_TX_RECOVERY_PENDING = 23,\n\tTG3_FLAG_WOL_CAP = 24,\n\tTG3_FLAG_JUMBO_RING_ENABLE = 25,\n\tTG3_FLAG_PAUSE_AUTONEG = 26,\n\tTG3_FLAG_CPMU_PRESENT = 27,\n\tTG3_FLAG_40BIT_DMA_BUG = 28,\n\tTG3_FLAG_BROKEN_CHECKSUMS = 29,\n\tTG3_FLAG_JUMBO_CAPABLE = 30,\n\tTG3_FLAG_CHIP_RESETTING = 31,\n\tTG3_FLAG_INIT_COMPLETE = 32,\n\tTG3_FLAG_MAX_RXPEND_64 = 33,\n\tTG3_FLAG_PCI_EXPRESS = 34,\n\tTG3_FLAG_ASF_NEW_HANDSHAKE = 35,\n\tTG3_FLAG_HW_AUTONEG = 36,\n\tTG3_FLAG_IS_NIC = 37,\n\tTG3_FLAG_FLASH = 38,\n\tTG3_FLAG_FW_TSO = 39,\n\tTG3_FLAG_HW_TSO_1 = 40,\n\tTG3_FLAG_HW_TSO_2 = 41,\n\tTG3_FLAG_HW_TSO_3 = 42,\n\tTG3_FLAG_TSO_CAPABLE = 43,\n\tTG3_FLAG_TSO_BUG = 44,\n\tTG3_FLAG_ICH_WORKAROUND = 45,\n\tTG3_FLAG_1SHOT_MSI = 46,\n\tTG3_FLAG_NO_FWARE_REPORTED = 47,\n\tTG3_FLAG_NO_NVRAM_ADDR_TRANS = 48,\n\tTG3_FLAG_ENABLE_APE = 49,\n\tTG3_FLAG_PROTECTED_NVRAM = 50,\n\tTG3_FLAG_5701_DMA_BUG = 51,\n\tTG3_FLAG_USE_PHYLIB = 52,\n\tTG3_FLAG_MDIOBUS_INITED = 53,\n\tTG3_FLAG_LRG_PROD_RING_CAP = 54,\n\tTG3_FLAG_RGMII_INBAND_DISABLE = 55,\n\tTG3_FLAG_RGMII_EXT_IBND_RX_EN = 56,\n\tTG3_FLAG_RGMII_EXT_IBND_TX_EN = 57,\n\tTG3_FLAG_CLKREQ_BUG = 58,\n\tTG3_FLAG_NO_NVRAM = 59,\n\tTG3_FLAG_ENABLE_RSS = 60,\n\tTG3_FLAG_ENABLE_TSS = 61,\n\tTG3_FLAG_SHORT_DMA_BUG = 62,\n\tTG3_FLAG_USE_JUMBO_BDFLAG = 63,\n\tTG3_FLAG_L1PLLPD_EN = 64,\n\tTG3_FLAG_APE_HAS_NCSI = 65,\n\tTG3_FLAG_TX_TSTAMP_EN = 66,\n\tTG3_FLAG_4K_FIFO_LIMIT = 67,\n\tTG3_FLAG_5719_5720_RDMA_BUG = 68,\n\tTG3_FLAG_RESET_TASK_PENDING = 69,\n\tTG3_FLAG_PTP_CAPABLE = 70,\n\tTG3_FLAG_5705_PLUS = 71,\n\tTG3_FLAG_IS_5788 = 72,\n\tTG3_FLAG_5750_PLUS = 73,\n\tTG3_FLAG_5780_CLASS = 74,\n\tTG3_FLAG_5755_PLUS = 75,\n\tTG3_FLAG_57765_PLUS = 76,\n\tTG3_FLAG_57765_CLASS = 77,\n\tTG3_FLAG_5717_PLUS = 78,\n\tTG3_FLAG_IS_SSB_CORE = 79,\n\tTG3_FLAG_FLUSH_POSTED_WRITES = 80,\n\tTG3_FLAG_ROBOSWITCH = 81,\n\tTG3_FLAG_ONE_DMA_AT_ONCE = 82,\n\tTG3_FLAG_RGMII_MODE = 83,\n\tTG3_FLAG_NUMBER_OF_FLAGS = 84,\n};\n\nenum TxStatusBits {\n\tTxHostOwns = 8192,\n\tTxUnderrun = 16384,\n\tTxStatOK = 32768,\n\tTxOutOfWindow = 536870912,\n\tTxAborted = 1073741824,\n\tTxCarrierLost = 2147483648,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nenum ___mac80211_drop_reason {\n\t___RX_CONTINUE = 1,\n\t___RX_QUEUED = 0,\n\t___RX_DROP_UNUSABLE = 65536,\n\t___RX_DROP_U_MIC_FAIL = 65537,\n\t___RX_DROP_U_REPLAY = 65538,\n\t___RX_DROP_U_BAD_MMIE = 65539,\n\t___RX_DROP_U_DUP = 65540,\n\t___RX_DROP_U_SPURIOUS = 65541,\n\t___RX_DROP_U_DECRYPT_FAIL = 65542,\n\t___RX_DROP_U_NO_KEY_ID = 65543,\n\t___RX_DROP_U_BAD_CIPHER = 65544,\n\t___RX_DROP_U_OOM = 65545,\n\t___RX_DROP_U_NONSEQ_PN = 65546,\n\t___RX_DROP_U_BAD_KEY_COLOR = 65547,\n\t___RX_DROP_U_BAD_4ADDR = 65548,\n\t___RX_DROP_U_BAD_AMSDU = 65549,\n\t___RX_DROP_U_BAD_AMSDU_CIPHER = 65550,\n\t___RX_DROP_U_INVALID_8023 = 65551,\n\t___RX_DROP_U_RUNT_ACTION = 65552,\n\t___RX_DROP_U_UNPROT_ACTION = 65553,\n\t___RX_DROP_U_UNPROT_DUAL = 65554,\n\t___RX_DROP_U_UNPROT_UCAST_MGMT = 65555,\n\t___RX_DROP_U_UNPROT_MCAST_MGMT = 65556,\n\t___RX_DROP_U_UNPROT_BEACON = 65557,\n\t___RX_DROP_U_UNPROT_UNICAST_PUB_ACTION = 65558,\n\t___RX_DROP_U_UNPROT_ROBUST_ACTION = 65559,\n\t___RX_DROP_U_ACTION_UNKNOWN_SRC = 65560,\n\t___RX_DROP_U_REJECTED_ACTION_RESPONSE = 65561,\n\t___RX_DROP_U_EXPECT_DEFRAG_PROT = 65562,\n\t___RX_DROP_U_WEP_DEC_FAIL = 65563,\n\t___RX_DROP_U_NO_IV = 65564,\n\t___RX_DROP_U_NO_ICV = 65565,\n\t___RX_DROP_U_AP_RX_GROUPCAST = 65566,\n\t___RX_DROP_U_SHORT_MMIC = 65567,\n\t___RX_DROP_U_MMIC_FAIL = 65568,\n\t___RX_DROP_U_SHORT_TKIP = 65569,\n\t___RX_DROP_U_TKIP_FAIL = 65570,\n\t___RX_DROP_U_SHORT_CCMP = 65571,\n\t___RX_DROP_U_SHORT_CCMP_MIC = 65572,\n\t___RX_DROP_U_SHORT_GCMP = 65573,\n\t___RX_DROP_U_SHORT_GCMP_MIC = 65574,\n\t___RX_DROP_U_SHORT_CMAC = 65575,\n\t___RX_DROP_U_SHORT_CMAC256 = 65576,\n\t___RX_DROP_U_SHORT_GMAC = 65577,\n\t___RX_DROP_U_UNEXPECTED_VLAN_4ADDR = 65578,\n\t___RX_DROP_U_UNEXPECTED_STA_4ADDR = 65579,\n\t___RX_DROP_U_UNEXPECTED_VLAN_MCAST = 65580,\n\t___RX_DROP_U_NOT_PORT_CONTROL = 65581,\n\t___RX_DROP_U_UNEXPECTED_4ADDR_FRAME = 65582,\n\t___RX_DROP_U_BAD_BCN_KEYIDX = 65583,\n\t___RX_DROP_U_BAD_MGMT_KEYIDX = 65584,\n\t___RX_DROP_U_UNKNOWN_ACTION_REJECTED = 65585,\n\t___RX_DROP_U_MESH_DS_BITS = 65586,\n\t___RX_DROP_U_MESH_A3_MISMATCH = 65587,\n\t___RX_DROP_U_MESH_NO_A4 = 65588,\n\t___RX_DROP_U_MESH_A4_MISMATCH = 65589,\n\t___RX_DROP_U_MESH_UNEXP_DATA = 65590,\n\t___RX_DROP_U_MESH_WRONG_ACTION = 65591,\n\t___RX_DROP_U_MESH_UNEXP_MGMT = 65592,\n\t___RX_DROP_U_SPURIOUS_NOTIF = 65593,\n\t___RX_DROP_U_RUNT_DATA = 65594,\n\t___RX_DROP_U_KEY_TAINTED = 65595,\n\t___RX_DROP_U_UNPROTECTED = 65596,\n\t___RX_DROP_U_MCAST_FRAGMENT = 65597,\n\t___RX_DROP_U_DEFRAG_MISMATCH = 65598,\n\t___RX_DROP_U_RUNT_MESH_DATA = 65599,\n\t___RX_DROP_U_MESH_NO_TTL = 65600,\n\t___RX_DROP_U_MESH_RMC = 65601,\n\t___RX_DROP_U_MESH_BAD_AE = 65602,\n\t___RX_DROP_U_MESH_TTL_EXPIRED = 65603,\n\t___RX_DROP_U_MESH_NOT_FORWARDING = 65604,\n\t___RX_DROP_U_AMSDU_WITHOUT_DATA = 65605,\n\t___RX_DROP_U_NULL_DATA = 65606,\n\t___RX_DROP_U_UNEXPECTED_4ADDR = 65607,\n\t___RX_DROP_U_PORT_CONTROL = 65608,\n\t___RX_DROP_U_UNKNOWN_STA = 65609,\n\t___RX_DROP_U_RUNT_BAR = 65610,\n\t___RX_DROP_U_BAR_OUTSIDE_SESSION = 65611,\n\t___RX_DROP_U_CTRL_FRAME = 65612,\n\t___RX_DROP_U_RUNT_MGMT = 65613,\n\t___RX_DROP_U_EXPECTED_MGMT = 65614,\n\t___RX_DROP_U_NONBCAST_BEACON = 65615,\n\t___RX_DROP_U_MALFORMED_ACTION = 65616,\n\t___RX_DROP_U_UNKNOWN_MCAST_ACTION = 65617,\n\t___RX_DROP_U_UNEXPECTED_EXT_FRAME = 65618,\n\t___RX_DROP_U_UNHANDLED_MGMT = 65619,\n\t___RX_DROP_U_MCAST_DEAUTH = 65620,\n\t___RX_DROP_U_UNHANDLED_DEAUTH = 65621,\n\t___RX_DROP_U_MCAST_DISASSOC = 65622,\n\t___RX_DROP_U_UNHANDLED_DISASSOC = 65623,\n\t___RX_DROP_U_UNHANDLED_PREQ = 65624,\n\t___RX_DROP_U_UNHANDLED_MGMT_STYPE = 65625,\n\t___RX_DROP_U_NO_LINK = 65626,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _cache_table_type {\n\tCACHE_L1_INST = 1,\n\tCACHE_L1_DATA = 2,\n\tCACHE_L2 = 3,\n\tCACHE_L3 = 4,\n} __attribute__((mode(byte)));\n\nenum _cache_type {\n\tCTYPE_NULL = 0,\n\tCTYPE_DATA = 1,\n\tCTYPE_INST = 2,\n\tCTYPE_UNIFIED = 3,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_NO_USER_FLAGS = 13,\n\t_SLAB_RECLAIM_ACCOUNT = 14,\n\t_SLAB_OBJECT_POISON = 15,\n\t_SLAB_CMPXCHG_DOUBLE = 16,\n\t_SLAB_NO_OBJ_EXT = 17,\n\t_SLAB_FLAGS_LAST_BIT = 18,\n};\n\nenum _tlb_table_type {\n\tTLB_INST_4K = 5,\n\tTLB_INST_4M = 6,\n\tTLB_INST_2M_4M = 7,\n\tTLB_INST_ALL = 8,\n\tTLB_DATA_4K = 9,\n\tTLB_DATA_4M = 10,\n\tTLB_DATA_2M_4M = 11,\n\tTLB_DATA_4K_4M = 12,\n\tTLB_DATA_1G = 13,\n\tTLB_DATA_1G_2M_4M = 14,\n\tTLB_DATA0_4K = 15,\n\tTLB_DATA0_4M = 16,\n\tTLB_DATA0_2M_4M = 17,\n\tSTLB_4K = 18,\n\tSTLB_4K_2M = 19,\n} __attribute__((mode(byte)));\n\nenum access_coordinate_class {\n\tACCESS_COORDINATE_LOCAL = 0,\n\tACCESS_COORDINATE_CPU = 1,\n\tACCESS_COORDINATE_MAX = 2,\n};\n\nenum ack_type {\n\tACK_CLEAR = 0,\n\tACK_SET = 1,\n};\n\nenum acpi_attr_enum {\n\tACPI_ATTR_LABEL_SHOW = 0,\n\tACPI_ATTR_INDEX_SHOW = 1,\n};\n\nenum acpi_backlight_type {\n\tacpi_backlight_undef = -1,\n\tacpi_backlight_none = 0,\n\tacpi_backlight_video = 1,\n\tacpi_backlight_vendor = 2,\n\tacpi_backlight_native = 3,\n\tacpi_backlight_nvidia_wmi_ec = 4,\n\tacpi_backlight_apple_gmux = 5,\n\tacpi_backlight_dell_uart = 6,\n};\n\nenum acpi_bridge_type {\n\tACPI_BRIDGE_TYPE_PCIE = 1,\n\tACPI_BRIDGE_TYPE_CXL = 2,\n};\n\nenum acpi_bus_device_type {\n\tACPI_BUS_TYPE_DEVICE = 0,\n\tACPI_BUS_TYPE_POWER = 1,\n\tACPI_BUS_TYPE_PROCESSOR = 2,\n\tACPI_BUS_TYPE_THERMAL = 3,\n\tACPI_BUS_TYPE_POWER_BUTTON = 4,\n\tACPI_BUS_TYPE_SLEEP_BUTTON = 5,\n\tACPI_BUS_TYPE_ECDT_EC = 6,\n\tACPI_BUS_DEVICE_TYPE_COUNT = 7,\n};\n\nenum acpi_cdat_type {\n\tACPI_CDAT_TYPE_DSMAS = 0,\n\tACPI_CDAT_TYPE_DSLBIS = 1,\n\tACPI_CDAT_TYPE_DSMSCIS = 2,\n\tACPI_CDAT_TYPE_DSIS = 3,\n\tACPI_CDAT_TYPE_DSEMTS = 4,\n\tACPI_CDAT_TYPE_SSLBIS = 5,\n\tACPI_CDAT_TYPE_RESERVED = 6,\n};\n\nenum acpi_cedt_type {\n\tACPI_CEDT_TYPE_CHBS = 0,\n\tACPI_CEDT_TYPE_CFMWS = 1,\n\tACPI_CEDT_TYPE_CXIMS = 2,\n\tACPI_CEDT_TYPE_RDPAS = 3,\n\tACPI_CEDT_TYPE_RESERVED = 4,\n};\n\nenum acpi_device_swnode_dev_props {\n\tACPI_DEVICE_SWNODE_DEV_ROTATION = 0,\n\tACPI_DEVICE_SWNODE_DEV_CLOCK_FREQUENCY = 1,\n\tACPI_DEVICE_SWNODE_DEV_LED_MAX_MICROAMP = 2,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_MICROAMP = 3,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_TIMEOUT_US = 4,\n\tACPI_DEVICE_SWNODE_DEV_NUM_OF = 5,\n\tACPI_DEVICE_SWNODE_DEV_NUM_ENTRIES = 6,\n};\n\nenum acpi_device_swnode_ep_props {\n\tACPI_DEVICE_SWNODE_EP_REMOTE_EP = 0,\n\tACPI_DEVICE_SWNODE_EP_BUS_TYPE = 1,\n\tACPI_DEVICE_SWNODE_EP_REG = 2,\n\tACPI_DEVICE_SWNODE_EP_CLOCK_LANES = 3,\n\tACPI_DEVICE_SWNODE_EP_DATA_LANES = 4,\n\tACPI_DEVICE_SWNODE_EP_LANE_POLARITIES = 5,\n\tACPI_DEVICE_SWNODE_EP_LINK_FREQUENCIES = 6,\n\tACPI_DEVICE_SWNODE_EP_NUM_OF = 7,\n\tACPI_DEVICE_SWNODE_EP_NUM_ENTRIES = 8,\n};\n\nenum acpi_device_swnode_port_props {\n\tACPI_DEVICE_SWNODE_PORT_REG = 0,\n\tACPI_DEVICE_SWNODE_PORT_NUM_OF = 1,\n\tACPI_DEVICE_SWNODE_PORT_NUM_ENTRIES = 2,\n};\n\nenum acpi_dmar_scope_type {\n\tACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,\n\tACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,\n\tACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,\n\tACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,\n\tACPI_DMAR_SCOPE_TYPE_HPET = 4,\n\tACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,\n\tACPI_DMAR_SCOPE_TYPE_RESERVED = 6,\n};\n\nenum acpi_dmar_type {\n\tACPI_DMAR_TYPE_HARDWARE_UNIT = 0,\n\tACPI_DMAR_TYPE_RESERVED_MEMORY = 1,\n\tACPI_DMAR_TYPE_ROOT_ATS = 2,\n\tACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,\n\tACPI_DMAR_TYPE_NAMESPACE = 4,\n\tACPI_DMAR_TYPE_SATC = 5,\n\tACPI_DMAR_TYPE_SIDP = 6,\n\tACPI_DMAR_TYPE_RESERVED = 7,\n};\n\nenum acpi_ec_event_state {\n\tEC_EVENT_READY = 0,\n\tEC_EVENT_IN_PROGRESS = 1,\n\tEC_EVENT_COMPLETE = 2,\n};\n\nenum acpi_irq_model_id {\n\tACPI_IRQ_MODEL_PIC = 0,\n\tACPI_IRQ_MODEL_IOAPIC = 1,\n\tACPI_IRQ_MODEL_IOSAPIC = 2,\n\tACPI_IRQ_MODEL_PLATFORM = 3,\n\tACPI_IRQ_MODEL_GIC = 4,\n\tACPI_IRQ_MODEL_GIC_V5 = 5,\n\tACPI_IRQ_MODEL_LPIC = 6,\n\tACPI_IRQ_MODEL_RINTC = 7,\n\tACPI_IRQ_MODEL_COUNT = 8,\n};\n\nenum acpi_madt_multiproc_wakeup_version {\n\tACPI_MADT_MP_WAKEUP_VERSION_NONE = 0,\n\tACPI_MADT_MP_WAKEUP_VERSION_V1 = 1,\n\tACPI_MADT_MP_WAKEUP_VERSION_RESERVED = 2,\n};\n\nenum acpi_madt_type {\n\tACPI_MADT_TYPE_LOCAL_APIC = 0,\n\tACPI_MADT_TYPE_IO_APIC = 1,\n\tACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,\n\tACPI_MADT_TYPE_NMI_SOURCE = 3,\n\tACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,\n\tACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,\n\tACPI_MADT_TYPE_IO_SAPIC = 6,\n\tACPI_MADT_TYPE_LOCAL_SAPIC = 7,\n\tACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,\n\tACPI_MADT_TYPE_LOCAL_X2APIC = 9,\n\tACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,\n\tACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,\n\tACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,\n\tACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,\n\tACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,\n\tACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,\n\tACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,\n\tACPI_MADT_TYPE_CORE_PIC = 17,\n\tACPI_MADT_TYPE_LIO_PIC = 18,\n\tACPI_MADT_TYPE_HT_PIC = 19,\n\tACPI_MADT_TYPE_EIO_PIC = 20,\n\tACPI_MADT_TYPE_MSI_PIC = 21,\n\tACPI_MADT_TYPE_BIO_PIC = 22,\n\tACPI_MADT_TYPE_LPC_PIC = 23,\n\tACPI_MADT_TYPE_RINTC = 24,\n\tACPI_MADT_TYPE_IMSIC = 25,\n\tACPI_MADT_TYPE_APLIC = 26,\n\tACPI_MADT_TYPE_PLIC = 27,\n\tACPI_MADT_TYPE_GICV5_IRS = 28,\n\tACPI_MADT_TYPE_GICV5_ITS = 29,\n\tACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,\n\tACPI_MADT_TYPE_RESERVED = 31,\n\tACPI_MADT_TYPE_OEM_RESERVED = 128,\n};\n\nenum acpi_pcct_type {\n\tACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2,\n\tACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3,\n\tACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4,\n\tACPI_PCCT_TYPE_HW_REG_COMM_SUBSPACE = 5,\n\tACPI_PCCT_TYPE_RESERVED = 6,\n};\n\nenum acpi_predicate {\n\tall_versions = 0,\n\tless_than_or_equal = 1,\n\tequal = 2,\n\tgreater_than_or_equal = 3,\n};\n\nenum acpi_preferred_pm_profiles {\n\tPM_UNSPECIFIED = 0,\n\tPM_DESKTOP = 1,\n\tPM_MOBILE = 2,\n\tPM_WORKSTATION = 3,\n\tPM_ENTERPRISE_SERVER = 4,\n\tPM_SOHO_SERVER = 5,\n\tPM_APPLIANCE_PC = 6,\n\tPM_PERFORMANCE_SERVER = 7,\n\tPM_TABLET = 8,\n\tNR_PM_PROFILES = 9,\n};\n\nenum acpi_reconfig_event {\n\tACPI_RECONFIG_DEVICE_ADD = 0,\n\tACPI_RECONFIG_DEVICE_REMOVE = 1,\n};\n\nenum acpi_return_package_types {\n\tACPI_PTYPE1_FIXED = 1,\n\tACPI_PTYPE1_VAR = 2,\n\tACPI_PTYPE1_OPTION = 3,\n\tACPI_PTYPE2 = 4,\n\tACPI_PTYPE2_COUNT = 5,\n\tACPI_PTYPE2_PKG_COUNT = 6,\n\tACPI_PTYPE2_FIXED = 7,\n\tACPI_PTYPE2_MIN = 8,\n\tACPI_PTYPE2_REV_FIXED = 9,\n\tACPI_PTYPE2_FIX_VAR = 10,\n\tACPI_PTYPE2_VAR_VAR = 11,\n\tACPI_PTYPE2_UUID_PAIR = 12,\n\tACPI_PTYPE_CUSTOM = 13,\n};\n\nenum acpi_srat_type {\n\tACPI_SRAT_TYPE_CPU_AFFINITY = 0,\n\tACPI_SRAT_TYPE_MEMORY_AFFINITY = 1,\n\tACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2,\n\tACPI_SRAT_TYPE_GICC_AFFINITY = 3,\n\tACPI_SRAT_TYPE_GIC_ITS_AFFINITY = 4,\n\tACPI_SRAT_TYPE_GENERIC_AFFINITY = 5,\n\tACPI_SRAT_TYPE_GENERIC_PORT_AFFINITY = 6,\n\tACPI_SRAT_TYPE_RINTC_AFFINITY = 7,\n\tACPI_SRAT_TYPE_RESERVED = 8,\n};\n\nenum acpi_subtable_type {\n\tACPI_SUBTABLE_COMMON = 0,\n\tACPI_SUBTABLE_HMAT = 1,\n\tACPI_SUBTABLE_PRMT = 2,\n\tACPI_SUBTABLE_CEDT = 3,\n\tCDAT_SUBTABLE = 4,\n};\n\nenum acpi_video_level_idx {\n\tACPI_VIDEO_AC_LEVEL = 0,\n\tACPI_VIDEO_BATTERY_LEVEL = 1,\n\tACPI_VIDEO_FIRST_LEVEL = 2,\n};\n\nenum actions {\n\tREGISTER = 0,\n\tDEREGISTER = 1,\n\tCPU_DONT_CARE = 2,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum addr_stride {\n\tPTE_STRIDE = 0,\n\tPMD_STRIDE = 1,\n};\n\nenum addr_type_t {\n\tUNICAST_ADDR = 0,\n\tMULTICAST_ADDR = 1,\n\tANYCAST_ADDR = 2,\n};\n\nenum address_markers_idx {\n\tUSER_SPACE_NR = 0,\n\tKERNEL_SPACE_NR = 1,\n\tLDT_NR = 2,\n\tLOW_KERNEL_NR = 3,\n\tVMALLOC_START_NR = 4,\n\tVMEMMAP_START_NR = 5,\n\tCPU_ENTRY_AREA_NR = 6,\n\tESPFIX_START_NR = 7,\n\tEFI_END_NR = 8,\n\tHIGH_KERNEL_NR = 9,\n\tMODULES_VADDR_NR = 10,\n\tMODULES_END_NR = 11,\n\tFIXADDR_START_NR = 12,\n\tEND_OF_SPACE_NR = 13,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum align_flags {\n\tALIGN_VA_32 = 1,\n\tALIGN_VA_64 = 2,\n};\n\nenum alloc_mode {\n\tALLOC_NORMAL = 0,\n\tALLOC_DEFER_COHERENT_FLUSH = 1,\n};\n\nenum allow_write_msrs {\n\tMSR_WRITES_ON = 0,\n\tMSR_WRITES_OFF = 1,\n\tMSR_WRITES_DEFAULT = 2,\n};\n\nenum amd_chipset_gen {\n\tNOT_AMD_CHIPSET = 0,\n\tAMD_CHIPSET_SB600 = 1,\n\tAMD_CHIPSET_SB700 = 2,\n\tAMD_CHIPSET_SB800 = 3,\n\tAMD_CHIPSET_HUDSON2 = 4,\n\tAMD_CHIPSET_BOLTON = 5,\n\tAMD_CHIPSET_YANGTZE = 6,\n\tAMD_CHIPSET_TAISHAN = 7,\n\tAMD_CHIPSET_UNKNOWN = 8,\n};\n\nenum amd_iommu_intr_mode_type {\n\tAMD_IOMMU_GUEST_IR_LEGACY = 0,\n\tAMD_IOMMU_GUEST_IR_LEGACY_GA = 1,\n\tAMD_IOMMU_GUEST_IR_VAPIC = 2,\n};\n\nenum amd_pref_core {\n\tAMD_PREF_CORE_UNKNOWN = 0,\n\tAMD_PREF_CORE_SUPPORTED = 1,\n\tAMD_PREF_CORE_UNSUPPORTED = 2,\n};\n\nenum amd_pstate_mode {\n\tAMD_PSTATE_UNDEFINED = 0,\n\tAMD_PSTATE_DISABLE = 1,\n\tAMD_PSTATE_PASSIVE = 2,\n\tAMD_PSTATE_ACTIVE = 3,\n\tAMD_PSTATE_GUIDED = 4,\n\tAMD_PSTATE_MAX = 5,\n};\n\nenum aper_size_type {\n\tU8_APER_SIZE = 0,\n\tU16_APER_SIZE = 1,\n\tU32_APER_SIZE = 2,\n\tLVL2_APER_SIZE = 3,\n\tFIXED_APER_SIZE = 4,\n};\n\nenum apic_intr_mode_id {\n\tAPIC_PIC = 0,\n\tAPIC_VIRTUAL_WIRE = 1,\n\tAPIC_VIRTUAL_WIRE_NO_CONFIG = 2,\n\tAPIC_SYMMETRIC_IO = 3,\n\tAPIC_SYMMETRIC_IO_NO_ROUTING = 4,\n};\n\nenum array_state {\n\tclear = 0,\n\tinactive = 1,\n\tsuspended = 2,\n\treadonly = 3,\n\tread_auto = 4,\n\tclean = 5,\n\tactive = 6,\n\twrite_pending = 7,\n\tactive_idle = 8,\n\tbroken = 9,\n\tbad_word = 10,\n};\n\nenum asn1_class {\n\tASN1_UNIV = 0,\n\tASN1_APPL = 1,\n\tASN1_CONT = 2,\n\tASN1_PRIV = 3,\n};\n\nenum asn1_method {\n\tASN1_PRIM = 0,\n\tASN1_CONS = 1,\n};\n\nenum asn1_opcode {\n\tASN1_OP_MATCH = 0,\n\tASN1_OP_MATCH_OR_SKIP = 1,\n\tASN1_OP_MATCH_ACT = 2,\n\tASN1_OP_MATCH_ACT_OR_SKIP = 3,\n\tASN1_OP_MATCH_JUMP = 4,\n\tASN1_OP_MATCH_JUMP_OR_SKIP = 5,\n\tASN1_OP_MATCH_ANY = 8,\n\tASN1_OP_MATCH_ANY_OR_SKIP = 9,\n\tASN1_OP_MATCH_ANY_ACT = 10,\n\tASN1_OP_MATCH_ANY_ACT_OR_SKIP = 11,\n\tASN1_OP_COND_MATCH_OR_SKIP = 17,\n\tASN1_OP_COND_MATCH_ACT_OR_SKIP = 19,\n\tASN1_OP_COND_MATCH_JUMP_OR_SKIP = 21,\n\tASN1_OP_COND_MATCH_ANY = 24,\n\tASN1_OP_COND_MATCH_ANY_OR_SKIP = 25,\n\tASN1_OP_COND_MATCH_ANY_ACT = 26,\n\tASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 27,\n\tASN1_OP_COND_FAIL = 28,\n\tASN1_OP_COMPLETE = 29,\n\tASN1_OP_ACT = 30,\n\tASN1_OP_MAYBE_ACT = 31,\n\tASN1_OP_END_SEQ = 32,\n\tASN1_OP_END_SET = 33,\n\tASN1_OP_END_SEQ_OF = 34,\n\tASN1_OP_END_SET_OF = 35,\n\tASN1_OP_END_SEQ_ACT = 36,\n\tASN1_OP_END_SET_ACT = 37,\n\tASN1_OP_END_SEQ_OF_ACT = 38,\n\tASN1_OP_END_SET_OF_ACT = 39,\n\tASN1_OP_RETURN = 40,\n\tASN1_OP__NR = 41,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum assoc_status {\n\tASSOC_SUCCESS = 0,\n\tASSOC_REJECTED = 1,\n\tASSOC_TIMEOUT = 2,\n\tASSOC_ABANDON = 3,\n};\n\nenum asymmetric_payload_bits {\n\tasym_crypto = 0,\n\tasym_subtype = 1,\n\tasym_key_ids = 2,\n\tasym_auth = 3,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nenum ata_quirks {\n\t__ATA_QUIRK_DIAGNOSTIC = 0,\n\t__ATA_QUIRK_NODMA = 1,\n\t__ATA_QUIRK_NONCQ = 2,\n\t__ATA_QUIRK_BROKEN_HPA = 3,\n\t__ATA_QUIRK_DISABLE = 4,\n\t__ATA_QUIRK_HPA_SIZE = 5,\n\t__ATA_QUIRK_IVB = 6,\n\t__ATA_QUIRK_STUCK_ERR = 7,\n\t__ATA_QUIRK_BRIDGE_OK = 8,\n\t__ATA_QUIRK_ATAPI_MOD16_DMA = 9,\n\t__ATA_QUIRK_FIRMWARE_WARN = 10,\n\t__ATA_QUIRK_1_5_GBPS = 11,\n\t__ATA_QUIRK_NOSETXFER = 12,\n\t__ATA_QUIRK_BROKEN_FPDMA_AA = 13,\n\t__ATA_QUIRK_DUMP_ID = 14,\n\t__ATA_QUIRK_MAX_SEC_LBA48 = 15,\n\t__ATA_QUIRK_ATAPI_DMADIR = 16,\n\t__ATA_QUIRK_NO_NCQ_TRIM = 17,\n\t__ATA_QUIRK_NOLPM = 18,\n\t__ATA_QUIRK_WD_BROKEN_LPM = 19,\n\t__ATA_QUIRK_ZERO_AFTER_TRIM = 20,\n\t__ATA_QUIRK_NO_DMA_LOG = 21,\n\t__ATA_QUIRK_NOTRIM = 22,\n\t__ATA_QUIRK_MAX_SEC = 23,\n\t__ATA_QUIRK_MAX_TRIM_128M = 24,\n\t__ATA_QUIRK_NO_NCQ_ON_ATI = 25,\n\t__ATA_QUIRK_NO_LPM_ON_ATI = 26,\n\t__ATA_QUIRK_NO_ID_DEV_LOG = 27,\n\t__ATA_QUIRK_NO_LOG_DIR = 28,\n\t__ATA_QUIRK_NO_FUA = 29,\n\t__ATA_QUIRK_MAX = 30,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum audit_nfcfgop {\n\tAUDIT_XT_OP_REGISTER = 0,\n\tAUDIT_XT_OP_REPLACE = 1,\n\tAUDIT_XT_OP_UNREGISTER = 2,\n\tAUDIT_NFT_OP_TABLE_REGISTER = 3,\n\tAUDIT_NFT_OP_TABLE_UNREGISTER = 4,\n\tAUDIT_NFT_OP_CHAIN_REGISTER = 5,\n\tAUDIT_NFT_OP_CHAIN_UNREGISTER = 6,\n\tAUDIT_NFT_OP_RULE_REGISTER = 7,\n\tAUDIT_NFT_OP_RULE_UNREGISTER = 8,\n\tAUDIT_NFT_OP_SET_REGISTER = 9,\n\tAUDIT_NFT_OP_SET_UNREGISTER = 10,\n\tAUDIT_NFT_OP_SETELEM_REGISTER = 11,\n\tAUDIT_NFT_OP_SETELEM_UNREGISTER = 12,\n\tAUDIT_NFT_OP_GEN_REGISTER = 13,\n\tAUDIT_NFT_OP_OBJ_REGISTER = 14,\n\tAUDIT_NFT_OP_OBJ_UNREGISTER = 15,\n\tAUDIT_NFT_OP_OBJ_RESET = 16,\n\tAUDIT_NFT_OP_FLOWTABLE_REGISTER = 17,\n\tAUDIT_NFT_OP_FLOWTABLE_UNREGISTER = 18,\n\tAUDIT_NFT_OP_SETELEM_RESET = 19,\n\tAUDIT_NFT_OP_RULE_RESET = 20,\n\tAUDIT_NFT_OP_INVALID = 21,\n};\n\nenum audit_nlgrps {\n\tAUDIT_NLGRP_NONE = 0,\n\tAUDIT_NLGRP_READLOG = 1,\n\t__AUDIT_NLGRP_MAX = 2,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum audit_state {\n\tAUDIT_STATE_DISABLED = 0,\n\tAUDIT_STATE_BUILD = 1,\n\tAUDIT_STATE_RECORD = 2,\n};\n\nenum auditsc_class_t {\n\tAUDITSC_NATIVE = 0,\n\tAUDITSC_COMPAT = 1,\n\tAUDITSC_OPEN = 2,\n\tAUDITSC_OPENAT = 3,\n\tAUDITSC_SOCKETCALL = 4,\n\tAUDITSC_EXECVE = 5,\n\tAUDITSC_OPENAT2 = 6,\n\tAUDITSC_NVALS = 7,\n};\n\nenum autofs_notify {\n\tNFY_NONE = 0,\n\tNFY_MOUNT = 1,\n\tNFY_EXPIRE = 2,\n};\n\nenum aux_ch {\n\tAUX_CH_NONE = -1,\n\tAUX_CH_A = 0,\n\tAUX_CH_B = 1,\n\tAUX_CH_C = 2,\n\tAUX_CH_D = 3,\n\tAUX_CH_E = 4,\n\tAUX_CH_F = 5,\n\tAUX_CH_G = 6,\n\tAUX_CH_H = 7,\n\tAUX_CH_I = 8,\n\tAUX_CH_USBC1 = 3,\n\tAUX_CH_USBC2 = 4,\n\tAUX_CH_USBC3 = 5,\n\tAUX_CH_USBC4 = 6,\n\tAUX_CH_USBC5 = 7,\n\tAUX_CH_USBC6 = 8,\n\tAUX_CH_D_XELPD = 7,\n\tAUX_CH_E_XELPD = 8,\n};\n\nenum backlight_scale {\n\tBACKLIGHT_SCALE_UNKNOWN = 0,\n\tBACKLIGHT_SCALE_LINEAR = 1,\n\tBACKLIGHT_SCALE_NON_LINEAR = 2,\n};\n\nenum backlight_type {\n\tBACKLIGHT_RAW = 1,\n\tBACKLIGHT_PLATFORM = 2,\n\tBACKLIGHT_FIRMWARE = 3,\n\tBACKLIGHT_TYPE_MAX = 4,\n};\n\nenum backlight_update_reason {\n\tBACKLIGHT_UPDATE_HOTKEY = 0,\n\tBACKLIGHT_UPDATE_SYSFS = 1,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum bdb_block_id {\n\tBDB_GENERAL_FEATURES = 1,\n\tBDB_GENERAL_DEFINITIONS = 2,\n\tBDB_DISPLAY_TOGGLE = 3,\n\tBDB_MODE_SUPPORT_LIST = 4,\n\tBDB_GENERIC_MODE_TABLE = 5,\n\tBDB_EXT_MMIO_REGS = 6,\n\tBDB_SWF_IO = 7,\n\tBDB_SWF_MMIO = 8,\n\tBDB_DOT_CLOCK_OVERRIDE_ALM = 9,\n\tBDB_PSR = 9,\n\tBDB_MODE_REMOVAL_TABLE = 10,\n\tBDB_CHILD_DEVICE_TABLE = 11,\n\tBDB_DRIVER_FEATURES = 12,\n\tBDB_DRIVER_PERSISTENCE = 13,\n\tBDB_EXT_TABLE_PTRS = 14,\n\tBDB_DOT_CLOCK_OVERRIDE = 15,\n\tBDB_DISPLAY_SELECT_OLD = 16,\n\tBDB_SV_TEST_FUNCTIONS = 17,\n\tBDB_DRIVER_ROTATION = 18,\n\tBDB_DISPLAY_REMOVE_OLD = 19,\n\tBDB_OEM_CUSTOM = 20,\n\tBDB_EFP_LIST = 21,\n\tBDB_SDVO_LVDS_OPTIONS = 22,\n\tBDB_SDVO_LVDS_DTD = 23,\n\tBDB_SDVO_LVDS_PNP_ID = 24,\n\tBDB_SDVO_LVDS_PPS = 25,\n\tBDB_TV_OPTIONS = 26,\n\tBDB_EDP = 27,\n\tBDB_EFP_DTD = 28,\n\tBDB_DISPLAY_SELECT_IVB = 29,\n\tBDB_DISPLAY_REMOVE_IVB = 30,\n\tBDB_DISPLAY_SELECT_HSW = 31,\n\tBDB_DISPLAY_REMOVE_HSW = 32,\n\tBDB_LFP_OPTIONS = 40,\n\tBDB_LFP_DATA_PTRS = 41,\n\tBDB_LFP_DATA = 42,\n\tBDB_LFP_BACKLIGHT = 43,\n\tBDB_LFP_POWER = 44,\n\tBDB_EDP_BFI = 45,\n\tBDB_CHROMATICITY = 46,\n\tBDB_MIPI = 50,\n\tBDB_FIXED_SET_MODE = 51,\n\tBDB_MIPI_CONFIG = 52,\n\tBDB_MIPI_SEQUENCE = 53,\n\tBDB_RGB_PALETTE = 54,\n\tBDB_COMPRESSION_PARAMETERS_OLD = 55,\n\tBDB_COMPRESSION_PARAMETERS = 56,\n\tBDB_VSWING_PREEMPH = 57,\n\tBDB_GENERIC_DTD = 58,\n\tBDB_INT15_HOOK = 252,\n\tBDB_PRD_TABLE = 253,\n\tBDB_SKIP = 254,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bhi_mitigations {\n\tBHI_MITIGATION_OFF = 0,\n\tBHI_MITIGATION_AUTO = 1,\n\tBHI_MITIGATION_ON = 2,\n\tBHI_MITIGATION_VMEXIT_ONLY = 3,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum bitmap_page_attr {\n\tBITMAP_PAGE_DIRTY = 0,\n\tBITMAP_PAGE_PENDING = 1,\n\tBITMAP_PAGE_NEEDWRITE = 2,\n};\n\nenum bitmap_state {\n\tBITMAP_STALE = 1,\n\tBITMAP_WRITE_ERROR = 2,\n\tBITMAP_FIRST_USE = 3,\n\tBITMAP_CLEAN = 4,\n\tBITMAP_DAEMON_BUSY = 5,\n\tBITMAP_HOSTENDIAN = 15,\n};\n\nenum blacklist_hash_type {\n\tBLACKLIST_HASH_X509_TBS = 1,\n\tBLACKLIST_HASH_BINARY = 2,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blkg_iostat_type {\n\tBLKG_IOSTAT_READ = 0,\n\tBLKG_IOSTAT_WRITE = 1,\n\tBLKG_IOSTAT_DISCARD = 2,\n\tBLKG_IOSTAT_NR = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum blktrace_cat {\n\tBLK_TC_READ = 1,\n\tBLK_TC_WRITE = 2,\n\tBLK_TC_FLUSH = 4,\n\tBLK_TC_SYNC = 8,\n\tBLK_TC_SYNCIO = 8,\n\tBLK_TC_QUEUE = 16,\n\tBLK_TC_REQUEUE = 32,\n\tBLK_TC_ISSUE = 64,\n\tBLK_TC_COMPLETE = 128,\n\tBLK_TC_FS = 256,\n\tBLK_TC_PC = 512,\n\tBLK_TC_NOTIFY = 1024,\n\tBLK_TC_AHEAD = 2048,\n\tBLK_TC_META = 4096,\n\tBLK_TC_DISCARD = 8192,\n\tBLK_TC_DRV_DATA = 16384,\n\tBLK_TC_FUA = 32768,\n\tBLK_TC_END_V1 = 32768,\n\tBLK_TC_ZONE_APPEND = 65536,\n\tBLK_TC_ZONE_RESET = 131072,\n\tBLK_TC_ZONE_RESET_ALL = 262144,\n\tBLK_TC_ZONE_FINISH = 524288,\n\tBLK_TC_ZONE_OPEN = 1048576,\n\tBLK_TC_ZONE_CLOSE = 2097152,\n\tBLK_TC_WRITE_ZEROES = 4194304,\n\tBLK_TC_END_V2 = 4194304,\n};\n\nenum blktrace_notify {\n\t__BLK_TN_PROCESS = 0,\n\t__BLK_TN_TIMESTAMP = 1,\n\t__BLK_TN_MESSAGE = 2,\n\t__BLK_TN_CGROUP = 256,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_43bit_dma = 1,\n\tboard_ahci_ign_iferr = 2,\n\tboard_ahci_no_debounce_delay = 3,\n\tboard_ahci_no_msi = 4,\n\tboard_ahci_pcs_quirk = 5,\n\tboard_ahci_pcs_quirk_no_devslp = 6,\n\tboard_ahci_pcs_quirk_no_sntf = 7,\n\tboard_ahci_yes_fbs = 8,\n\tboard_ahci_yes_fbs_atapi_dma = 9,\n\tboard_ahci_al = 10,\n\tboard_ahci_avn = 11,\n\tboard_ahci_mcp65 = 12,\n\tboard_ahci_mcp77 = 13,\n\tboard_ahci_mcp89 = 14,\n\tboard_ahci_mv = 15,\n\tboard_ahci_sb600 = 16,\n\tboard_ahci_sb700 = 17,\n\tboard_ahci_vt8251 = 18,\n\tboard_ahci_mcp_linux = 12,\n\tboard_ahci_mcp67 = 12,\n\tboard_ahci_mcp73 = 12,\n\tboard_ahci_mcp79 = 13,\n};\n\nenum bp_type_idx {\n\tTYPE_INST = 0,\n\tTYPE_DATA = 0,\n\tTYPE_MAX = 1,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_perf_event_type {\n\tBPF_PERF_EVENT_UNSPEC = 0,\n\tBPF_PERF_EVENT_UPROBE = 1,\n\tBPF_PERF_EVENT_URETPROBE = 2,\n\tBPF_PERF_EVENT_KPROBE = 3,\n\tBPF_PERF_EVENT_KRETPROBE = 4,\n\tBPF_PERF_EVENT_TRACEPOINT = 5,\n\tBPF_PERF_EVENT_EVENT = 6,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum bss_compare_mode {\n\tBSS_CMP_REGULAR = 0,\n\tBSS_CMP_HIDE_ZLEN = 1,\n\tBSS_CMP_HIDE_NUL = 2,\n};\n\nenum bss_param_flags {\n\tBSS_PARAM_FLAGS_CTS_PROT = 1,\n\tBSS_PARAM_FLAGS_SHORT_PREAMBLE = 2,\n\tBSS_PARAM_FLAGS_SHORT_SLOT_TIME = 4,\n};\n\nenum bss_source_type {\n\tBSS_SOURCE_DIRECT = 0,\n\tBSS_SOURCE_MBSSID = 1,\n\tBSS_SOURCE_STA_PROFILE = 2,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum cache_tag_type {\n\tCACHE_TAG_IOTLB = 0,\n\tCACHE_TAG_DEVTLB = 1,\n\tCACHE_TAG_NESTING_IOTLB = 2,\n\tCACHE_TAG_NESTING_DEVTLB = 3,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum cb_command {\n\tcb_nop = 0,\n\tcb_iaaddr = 1,\n\tcb_config = 2,\n\tcb_multi = 3,\n\tcb_tx = 4,\n\tcb_ucode = 5,\n\tcb_dump = 6,\n\tcb_tx_sf = 8,\n\tcb_tx_nc = 16,\n\tcb_cid = 7936,\n\tcb_i = 8192,\n\tcb_s = 16384,\n\tcb_el = 32768,\n};\n\nenum cb_status {\n\tcb_complete = 32768,\n\tcb_ok = 8192,\n};\n\nenum cc_attr {\n\tCC_ATTR_MEM_ENCRYPT = 0,\n\tCC_ATTR_HOST_MEM_ENCRYPT = 1,\n\tCC_ATTR_GUEST_MEM_ENCRYPT = 2,\n\tCC_ATTR_GUEST_STATE_ENCRYPT = 3,\n\tCC_ATTR_GUEST_UNROLL_STRING_IO = 4,\n\tCC_ATTR_GUEST_SEV_SNP = 5,\n\tCC_ATTR_GUEST_SNP_SECURE_TSC = 6,\n\tCC_ATTR_HOST_SEV_SNP = 7,\n\tCC_ATTR_SNP_SECURE_AVIC = 8,\n};\n\nenum cc_vendor {\n\tCC_VENDOR_NONE = 0,\n\tCC_VENDOR_AMD = 1,\n\tCC_VENDOR_INTEL = 2,\n};\n\nenum cdrom_print_option {\n\tCTL_NAME = 0,\n\tCTL_SPEED = 1,\n\tCTL_SLOTS = 2,\n\tCTL_CAPABILITY = 3,\n};\n\nenum cea_speaker_placement {\n\tFL = 1,\n\tFC = 2,\n\tFR = 4,\n\tFLC = 8,\n\tFRC = 16,\n\tRL = 32,\n\tRC = 64,\n\tRR = 128,\n\tRLC = 256,\n\tRRC = 512,\n\tLFE = 1024,\n\tFLW = 2048,\n\tFRW = 4096,\n\tFLH = 8192,\n\tFCH = 16384,\n\tFRH = 32768,\n\tTC = 65536,\n};\n\nenum cfg80211_assoc_req_flags {\n\tASSOC_REQ_DISABLE_HT = 1,\n\tASSOC_REQ_DISABLE_VHT = 2,\n\tASSOC_REQ_USE_RRM = 4,\n\tCONNECT_REQ_EXTERNAL_AUTH_SUPPORT = 8,\n\tASSOC_REQ_DISABLE_HE = 16,\n\tASSOC_REQ_DISABLE_EHT = 32,\n\tCONNECT_REQ_MLO_SUPPORT = 64,\n\tASSOC_REQ_SPP_AMSDU = 128,\n\tASSOC_REQ_DISABLE_UHR = 256,\n};\n\nenum cfg80211_bss_frame_type {\n\tCFG80211_BSS_FTYPE_UNKNOWN = 0,\n\tCFG80211_BSS_FTYPE_BEACON = 1,\n\tCFG80211_BSS_FTYPE_PRESP = 2,\n\tCFG80211_BSS_FTYPE_S1G_BEACON = 3,\n};\n\nenum cfg80211_connect_params_changed {\n\tUPDATE_ASSOC_IES = 1,\n\tUPDATE_FILS_ERP_INFO = 2,\n\tUPDATE_AUTH_TYPE = 4,\n};\n\nenum cfg80211_event_type {\n\tEVENT_CONNECT_RESULT = 0,\n\tEVENT_ROAMED = 1,\n\tEVENT_DISCONNECTED = 2,\n\tEVENT_IBSS_JOINED = 3,\n\tEVENT_STOPPED = 4,\n\tEVENT_PORT_AUTHORIZED = 5,\n};\n\nenum cfg80211_nan_conf_changes {\n\tCFG80211_NAN_CONF_CHANGED_PREF = 1,\n\tCFG80211_NAN_CONF_CHANGED_BANDS = 2,\n\tCFG80211_NAN_CONF_CHANGED_CONFIG = 4,\n};\n\nenum cfg80211_rnr_iter_ret {\n\tRNR_ITER_CONTINUE = 0,\n\tRNR_ITER_BREAK = 1,\n\tRNR_ITER_ERROR = 2,\n};\n\nenum cfg80211_signal_type {\n\tCFG80211_SIGNAL_TYPE_NONE = 0,\n\tCFG80211_SIGNAL_TYPE_MBM = 1,\n\tCFG80211_SIGNAL_TYPE_UNSPEC = 2,\n};\n\nenum cfg80211_station_type {\n\tCFG80211_STA_AP_CLIENT = 0,\n\tCFG80211_STA_AP_CLIENT_UNASSOC = 1,\n\tCFG80211_STA_AP_MLME_CLIENT = 2,\n\tCFG80211_STA_AP_STA = 3,\n\tCFG80211_STA_IBSS = 4,\n\tCFG80211_STA_TDLS_PEER_SETUP = 5,\n\tCFG80211_STA_TDLS_PEER_ACTIVE = 6,\n\tCFG80211_STA_MESH_PEER_KERNEL = 7,\n\tCFG80211_STA_MESH_PEER_USER = 8,\n};\n\nenum cfi_mode {\n\tCFI_AUTO = 0,\n\tCFI_OFF = 1,\n\tCFI_KCFI = 2,\n\tCFI_FINEIBT = 3,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_COUNT = 0,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tio_cgrp_id = 3,\n\tdevices_cgrp_id = 4,\n\tfreezer_cgrp_id = 5,\n\tnet_cls_cgrp_id = 6,\n\tperf_event_cgrp_id = 7,\n\tnet_prio_cgrp_id = 8,\n\thugetlb_cgrp_id = 9,\n\tpids_cgrp_id = 10,\n\trdma_cgrp_id = 11,\n\tmisc_cgrp_id = 12,\n\tdebug_cgrp_id = 13,\n\tCGROUP_SUBSYS_COUNT = 14,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum check_link_response {\n\tHDCP_LINK_PROTECTED = 0,\n\tHDCP_TOPOLOGY_CHANGE = 1,\n\tHDCP_LINK_INTEGRITY_FAILURE = 2,\n\tHDCP_REAUTH_REQUEST = 3,\n};\n\nenum chip_flags {\n\tHasHltClk = 1,\n\tHasLWake = 2,\n};\n\nenum chipset_type {\n\tNOT_SUPPORTED = 0,\n\tSUPPORTED = 1,\n};\n\nenum class_map_type {\n\tDD_CLASS_TYPE_DISJOINT_BITS = 0,\n\tDD_CLASS_TYPE_LEVEL_NUM = 1,\n\tDD_CLASS_TYPE_DISJOINT_NAMES = 2,\n\tDD_CLASS_TYPE_LEVEL_NAMES = 3,\n};\n\nenum cleanup_prefix_rt_t {\n\tCLEANUP_PREFIX_RT_NOP = 0,\n\tCLEANUP_PREFIX_RT_DEL = 1,\n\tCLEANUP_PREFIX_RT_EXPIRE = 2,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum cntl_msg_types {\n\tIPCTNL_MSG_CT_NEW = 0,\n\tIPCTNL_MSG_CT_GET = 1,\n\tIPCTNL_MSG_CT_DELETE = 2,\n\tIPCTNL_MSG_CT_GET_CTRZERO = 3,\n\tIPCTNL_MSG_CT_GET_STATS_CPU = 4,\n\tIPCTNL_MSG_CT_GET_STATS = 5,\n\tIPCTNL_MSG_CT_GET_DYING = 6,\n\tIPCTNL_MSG_CT_GET_UNCONFIRMED = 7,\n\tIPCTNL_MSG_MAX = 8,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum console_type {\n\tCONS_BASIC = 1,\n\tCONS_EXTENDED = 2,\n};\n\nenum context {\n\tIN_KERNEL = 1,\n\tIN_USER = 2,\n\tIN_KERNEL_RECOV = 3,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cp_error_code {\n\tCP_EC = 32767,\n\tCP_RET = 1,\n\tCP_IRET = 2,\n\tCP_ENDBR = 3,\n\tCP_RSTRORSSP = 4,\n\tCP_SETSSBSY = 5,\n\tCP_ENCL = 32768,\n};\n\nenum cpa_warn {\n\tCPA_CONFLICT = 0,\n\tCPA_PROTECT = 1,\n\tCPA_DETECT = 2,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cppc_regs {\n\tHIGHEST_PERF = 0,\n\tNOMINAL_PERF = 1,\n\tLOW_NON_LINEAR_PERF = 2,\n\tLOWEST_PERF = 3,\n\tGUARANTEED_PERF = 4,\n\tDESIRED_PERF = 5,\n\tMIN_PERF = 6,\n\tMAX_PERF = 7,\n\tPERF_REDUC_TOLERANCE = 8,\n\tTIME_WINDOW = 9,\n\tCTR_WRAP_TIME = 10,\n\tREFERENCE_CTR = 11,\n\tDELIVERED_CTR = 12,\n\tPERF_LIMITED = 13,\n\tENABLE = 14,\n\tAUTO_SEL_ENABLE = 15,\n\tAUTO_ACT_WINDOW = 16,\n\tENERGY_PERF = 17,\n\tREFERENCE_PERF = 18,\n\tLOWEST_FREQ = 19,\n\tNOMINAL_FREQ = 20,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tNR_STATS = 10,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum cpuid_leafs {\n\tCPUID_1_EDX = 0,\n\tCPUID_8000_0001_EDX = 1,\n\tCPUID_8086_0001_EDX = 2,\n\tCPUID_LNX_1 = 3,\n\tCPUID_1_ECX = 4,\n\tCPUID_C000_0001_EDX = 5,\n\tCPUID_8000_0001_ECX = 6,\n\tCPUID_LNX_2 = 7,\n\tCPUID_LNX_3 = 8,\n\tCPUID_7_0_EBX = 9,\n\tCPUID_D_1_EAX = 10,\n\tCPUID_LNX_4 = 11,\n\tCPUID_7_1_EAX = 12,\n\tCPUID_8000_0008_EBX = 13,\n\tCPUID_6_EAX = 14,\n\tCPUID_8000_000A_EDX = 15,\n\tCPUID_7_ECX = 16,\n\tCPUID_LNX_6 = 17,\n\tCPUID_7_EDX = 18,\n\tCPUID_8000_001F_EAX = 19,\n\tCPUID_8000_0021_EAX = 20,\n\tCPUID_LNX_5 = 21,\n\tNR_CPUID_WORDS = 22,\n};\n\nenum cpuid_regs_idx {\n\tCPUID_EAX = 0,\n\tCPUID_EBX = 1,\n\tCPUID_ECX = 2,\n\tCPUID_EDX = 3,\n};\n\nenum createmode4 {\n\tNFS4_CREATE_UNCHECKED = 0,\n\tNFS4_CREATE_GUARDED = 1,\n\tNFS4_CREATE_EXCLUSIVE = 2,\n\tNFS4_CREATE_EXCLUSIVE4_1 = 3,\n};\n\nenum criteria {\n\tCR_POWER2_ALIGNED = 0,\n\tCR_GOAL_LEN_FAST = 1,\n\tCR_BEST_AVAIL_LEN = 2,\n\tCR_GOAL_LEN_SLOW = 3,\n\tCR_ANY_FREE = 4,\n\tEXT4_MB_NUM_CRS = 5,\n};\n\nenum csr_regs {\n\tB0_RAP = 0,\n\tB0_CTST = 4,\n\tB0_POWER_CTRL = 7,\n\tB0_ISRC = 8,\n\tB0_IMSK = 12,\n\tB0_HWE_ISRC = 16,\n\tB0_HWE_IMSK = 20,\n\tB0_Y2_SP_ISRC2 = 28,\n\tB0_Y2_SP_ISRC3 = 32,\n\tB0_Y2_SP_EISR = 36,\n\tB0_Y2_SP_LISR = 40,\n\tB0_Y2_SP_ICR = 44,\n\tB2_MAC_1 = 256,\n\tB2_MAC_2 = 264,\n\tB2_MAC_3 = 272,\n\tB2_CONN_TYP = 280,\n\tB2_PMD_TYP = 281,\n\tB2_MAC_CFG = 282,\n\tB2_CHIP_ID = 283,\n\tB2_E_0 = 284,\n\tB2_Y2_CLK_GATE = 285,\n\tB2_Y2_HW_RES = 286,\n\tB2_E_3 = 287,\n\tB2_Y2_CLK_CTRL = 288,\n\tB2_TI_INI = 304,\n\tB2_TI_VAL = 308,\n\tB2_TI_CTRL = 312,\n\tB2_TI_TEST = 313,\n\tB2_TST_CTRL1 = 344,\n\tB2_TST_CTRL2 = 345,\n\tB2_GP_IO = 348,\n\tB2_I2C_CTRL = 352,\n\tB2_I2C_DATA = 356,\n\tB2_I2C_IRQ = 360,\n\tB2_I2C_SW = 364,\n\tY2_PEX_PHY_DATA = 368,\n\tY2_PEX_PHY_ADDR = 370,\n\tB3_RAM_ADDR = 384,\n\tB3_RAM_DATA_LO = 388,\n\tB3_RAM_DATA_HI = 392,\n\tB3_RI_WTO_R1 = 400,\n\tB3_RI_WTO_XA1 = 401,\n\tB3_RI_WTO_XS1 = 402,\n\tB3_RI_RTO_R1 = 403,\n\tB3_RI_RTO_XA1 = 404,\n\tB3_RI_RTO_XS1 = 405,\n\tB3_RI_WTO_R2 = 406,\n\tB3_RI_WTO_XA2 = 407,\n\tB3_RI_WTO_XS2 = 408,\n\tB3_RI_RTO_R2 = 409,\n\tB3_RI_RTO_XA2 = 410,\n\tB3_RI_RTO_XS2 = 411,\n\tB3_RI_TO_VAL = 412,\n\tB3_RI_CTRL = 416,\n\tB3_RI_TEST = 418,\n\tB3_MA_TOINI_RX1 = 432,\n\tB3_MA_TOINI_RX2 = 433,\n\tB3_MA_TOINI_TX1 = 434,\n\tB3_MA_TOINI_TX2 = 435,\n\tB3_MA_TOVAL_RX1 = 436,\n\tB3_MA_TOVAL_RX2 = 437,\n\tB3_MA_TOVAL_TX1 = 438,\n\tB3_MA_TOVAL_TX2 = 439,\n\tB3_MA_TO_CTRL = 440,\n\tB3_MA_TO_TEST = 442,\n\tB3_MA_RCINI_RX1 = 448,\n\tB3_MA_RCINI_RX2 = 449,\n\tB3_MA_RCINI_TX1 = 450,\n\tB3_MA_RCINI_TX2 = 451,\n\tB3_MA_RCVAL_RX1 = 452,\n\tB3_MA_RCVAL_RX2 = 453,\n\tB3_MA_RCVAL_TX1 = 454,\n\tB3_MA_RCVAL_TX2 = 455,\n\tB3_MA_RC_CTRL = 456,\n\tB3_MA_RC_TEST = 458,\n\tB3_PA_TOINI_RX1 = 464,\n\tB3_PA_TOINI_RX2 = 468,\n\tB3_PA_TOINI_TX1 = 472,\n\tB3_PA_TOINI_TX2 = 476,\n\tB3_PA_TOVAL_RX1 = 480,\n\tB3_PA_TOVAL_RX2 = 484,\n\tB3_PA_TOVAL_TX1 = 488,\n\tB3_PA_TOVAL_TX2 = 492,\n\tB3_PA_CTRL = 496,\n\tB3_PA_TEST = 498,\n\tY2_CFG_SPC = 7168,\n\tY2_CFG_AER = 7424,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum ctattr_counters {\n\tCTA_COUNTERS_UNSPEC = 0,\n\tCTA_COUNTERS_PACKETS = 1,\n\tCTA_COUNTERS_BYTES = 2,\n\tCTA_COUNTERS32_PACKETS = 3,\n\tCTA_COUNTERS32_BYTES = 4,\n\tCTA_COUNTERS_PAD = 5,\n\t__CTA_COUNTERS_MAX = 6,\n};\n\nenum ctattr_expect {\n\tCTA_EXPECT_UNSPEC = 0,\n\tCTA_EXPECT_MASTER = 1,\n\tCTA_EXPECT_TUPLE = 2,\n\tCTA_EXPECT_MASK = 3,\n\tCTA_EXPECT_TIMEOUT = 4,\n\tCTA_EXPECT_ID = 5,\n\tCTA_EXPECT_HELP_NAME = 6,\n\tCTA_EXPECT_ZONE = 7,\n\tCTA_EXPECT_FLAGS = 8,\n\tCTA_EXPECT_CLASS = 9,\n\tCTA_EXPECT_NAT = 10,\n\tCTA_EXPECT_FN = 11,\n\t__CTA_EXPECT_MAX = 12,\n};\n\nenum ctattr_expect_nat {\n\tCTA_EXPECT_NAT_UNSPEC = 0,\n\tCTA_EXPECT_NAT_DIR = 1,\n\tCTA_EXPECT_NAT_TUPLE = 2,\n\t__CTA_EXPECT_NAT_MAX = 3,\n};\n\nenum ctattr_expect_stats {\n\tCTA_STATS_EXP_UNSPEC = 0,\n\tCTA_STATS_EXP_NEW = 1,\n\tCTA_STATS_EXP_CREATE = 2,\n\tCTA_STATS_EXP_DELETE = 3,\n\t__CTA_STATS_EXP_MAX = 4,\n};\n\nenum ctattr_filter {\n\tCTA_FILTER_UNSPEC = 0,\n\tCTA_FILTER_ORIG_FLAGS = 1,\n\tCTA_FILTER_REPLY_FLAGS = 2,\n\t__CTA_FILTER_MAX = 3,\n};\n\nenum ctattr_help {\n\tCTA_HELP_UNSPEC = 0,\n\tCTA_HELP_NAME = 1,\n\tCTA_HELP_INFO = 2,\n\t__CTA_HELP_MAX = 3,\n};\n\nenum ctattr_ip {\n\tCTA_IP_UNSPEC = 0,\n\tCTA_IP_V4_SRC = 1,\n\tCTA_IP_V4_DST = 2,\n\tCTA_IP_V6_SRC = 3,\n\tCTA_IP_V6_DST = 4,\n\t__CTA_IP_MAX = 5,\n};\n\nenum ctattr_l4proto {\n\tCTA_PROTO_UNSPEC = 0,\n\tCTA_PROTO_NUM = 1,\n\tCTA_PROTO_SRC_PORT = 2,\n\tCTA_PROTO_DST_PORT = 3,\n\tCTA_PROTO_ICMP_ID = 4,\n\tCTA_PROTO_ICMP_TYPE = 5,\n\tCTA_PROTO_ICMP_CODE = 6,\n\tCTA_PROTO_ICMPV6_ID = 7,\n\tCTA_PROTO_ICMPV6_TYPE = 8,\n\tCTA_PROTO_ICMPV6_CODE = 9,\n\t__CTA_PROTO_MAX = 10,\n};\n\nenum ctattr_nat {\n\tCTA_NAT_UNSPEC = 0,\n\tCTA_NAT_V4_MINIP = 1,\n\tCTA_NAT_V4_MAXIP = 2,\n\tCTA_NAT_PROTO = 3,\n\tCTA_NAT_V6_MINIP = 4,\n\tCTA_NAT_V6_MAXIP = 5,\n\t__CTA_NAT_MAX = 6,\n};\n\nenum ctattr_protoinfo {\n\tCTA_PROTOINFO_UNSPEC = 0,\n\tCTA_PROTOINFO_TCP = 1,\n\tCTA_PROTOINFO_DCCP = 2,\n\tCTA_PROTOINFO_SCTP = 3,\n\t__CTA_PROTOINFO_MAX = 4,\n};\n\nenum ctattr_protoinfo_tcp {\n\tCTA_PROTOINFO_TCP_UNSPEC = 0,\n\tCTA_PROTOINFO_TCP_STATE = 1,\n\tCTA_PROTOINFO_TCP_WSCALE_ORIGINAL = 2,\n\tCTA_PROTOINFO_TCP_WSCALE_REPLY = 3,\n\tCTA_PROTOINFO_TCP_FLAGS_ORIGINAL = 4,\n\tCTA_PROTOINFO_TCP_FLAGS_REPLY = 5,\n\t__CTA_PROTOINFO_TCP_MAX = 6,\n};\n\nenum ctattr_protonat {\n\tCTA_PROTONAT_UNSPEC = 0,\n\tCTA_PROTONAT_PORT_MIN = 1,\n\tCTA_PROTONAT_PORT_MAX = 2,\n\t__CTA_PROTONAT_MAX = 3,\n};\n\nenum ctattr_secctx {\n\tCTA_SECCTX_UNSPEC = 0,\n\tCTA_SECCTX_NAME = 1,\n\t__CTA_SECCTX_MAX = 2,\n};\n\nenum ctattr_seqadj {\n\tCTA_SEQADJ_UNSPEC = 0,\n\tCTA_SEQADJ_CORRECTION_POS = 1,\n\tCTA_SEQADJ_OFFSET_BEFORE = 2,\n\tCTA_SEQADJ_OFFSET_AFTER = 3,\n\t__CTA_SEQADJ_MAX = 4,\n};\n\nenum ctattr_stats_cpu {\n\tCTA_STATS_UNSPEC = 0,\n\tCTA_STATS_SEARCHED = 1,\n\tCTA_STATS_FOUND = 2,\n\tCTA_STATS_NEW = 3,\n\tCTA_STATS_INVALID = 4,\n\tCTA_STATS_IGNORE = 5,\n\tCTA_STATS_DELETE = 6,\n\tCTA_STATS_DELETE_LIST = 7,\n\tCTA_STATS_INSERT = 8,\n\tCTA_STATS_INSERT_FAILED = 9,\n\tCTA_STATS_DROP = 10,\n\tCTA_STATS_EARLY_DROP = 11,\n\tCTA_STATS_ERROR = 12,\n\tCTA_STATS_SEARCH_RESTART = 13,\n\tCTA_STATS_CLASH_RESOLVE = 14,\n\tCTA_STATS_CHAIN_TOOLONG = 15,\n\t__CTA_STATS_MAX = 16,\n};\n\nenum ctattr_stats_global {\n\tCTA_STATS_GLOBAL_UNSPEC = 0,\n\tCTA_STATS_GLOBAL_ENTRIES = 1,\n\tCTA_STATS_GLOBAL_MAX_ENTRIES = 2,\n\t__CTA_STATS_GLOBAL_MAX = 3,\n};\n\nenum ctattr_synproxy {\n\tCTA_SYNPROXY_UNSPEC = 0,\n\tCTA_SYNPROXY_ISN = 1,\n\tCTA_SYNPROXY_ITS = 2,\n\tCTA_SYNPROXY_TSOFF = 3,\n\t__CTA_SYNPROXY_MAX = 4,\n};\n\nenum ctattr_tstamp {\n\tCTA_TIMESTAMP_UNSPEC = 0,\n\tCTA_TIMESTAMP_START = 1,\n\tCTA_TIMESTAMP_STOP = 2,\n\tCTA_TIMESTAMP_PAD = 3,\n\t__CTA_TIMESTAMP_MAX = 4,\n};\n\nenum ctattr_tuple {\n\tCTA_TUPLE_UNSPEC = 0,\n\tCTA_TUPLE_IP = 1,\n\tCTA_TUPLE_PROTO = 2,\n\tCTA_TUPLE_ZONE = 3,\n\t__CTA_TUPLE_MAX = 4,\n};\n\nenum ctattr_type {\n\tCTA_UNSPEC = 0,\n\tCTA_TUPLE_ORIG = 1,\n\tCTA_TUPLE_REPLY = 2,\n\tCTA_STATUS = 3,\n\tCTA_PROTOINFO = 4,\n\tCTA_HELP = 5,\n\tCTA_NAT_SRC = 6,\n\tCTA_TIMEOUT = 7,\n\tCTA_MARK = 8,\n\tCTA_COUNTERS_ORIG = 9,\n\tCTA_COUNTERS_REPLY = 10,\n\tCTA_USE = 11,\n\tCTA_ID = 12,\n\tCTA_NAT_DST = 13,\n\tCTA_TUPLE_MASTER = 14,\n\tCTA_SEQ_ADJ_ORIG = 15,\n\tCTA_NAT_SEQ_ADJ_ORIG = 15,\n\tCTA_SEQ_ADJ_REPLY = 16,\n\tCTA_NAT_SEQ_ADJ_REPLY = 16,\n\tCTA_SECMARK = 17,\n\tCTA_ZONE = 18,\n\tCTA_SECCTX = 19,\n\tCTA_TIMESTAMP = 20,\n\tCTA_MARK_MASK = 21,\n\tCTA_LABELS = 22,\n\tCTA_LABELS_MASK = 23,\n\tCTA_SYNPROXY = 24,\n\tCTA_FILTER = 25,\n\tCTA_STATUS_MASK = 26,\n\tCTA_TIMESTAMP_EVENT = 27,\n\t__CTA_MAX = 28,\n};\n\nenum cti_port_type {\n\tCTI_PORT_TYPE_NONE = 0,\n\tCTI_PORT_TYPE_RS232 = 1,\n\tCTI_PORT_TYPE_RS422_485 = 2,\n\tCTI_PORT_TYPE_RS232_422_485_HW = 3,\n\tCTI_PORT_TYPE_RS232_422_485_SW = 4,\n\tCTI_PORT_TYPE_RS232_422_485_4B = 5,\n\tCTI_PORT_TYPE_RS232_422_485_2B = 6,\n\tCTI_PORT_TYPE_MAX = 7,\n};\n\nenum ctnl_exp_msg_types {\n\tIPCTNL_MSG_EXP_NEW = 0,\n\tIPCTNL_MSG_EXP_GET = 1,\n\tIPCTNL_MSG_EXP_DELETE = 2,\n\tIPCTNL_MSG_EXP_GET_STATS_CPU = 3,\n\tIPCTNL_MSG_EXP_MAX = 4,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum cuc_dump {\n\tcuc_dump_complete = 40965,\n\tcuc_dump_reset_complete = 40967,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum dax_access_mode {\n\tDAX_ACCESS = 0,\n\tDAX_RECOVERY_WRITE = 1,\n};\n\nenum dbc_state {\n\tDS_DISABLED = 0,\n\tDS_INITIALIZED = 1,\n\tDS_ENABLED = 2,\n\tDS_CONNECTED = 3,\n\tDS_CONFIGURED = 4,\n\tDS_MAX = 5,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dbuf_slice {\n\tDBUF_S1 = 0,\n\tDBUF_S2 = 1,\n\tDBUF_S3 = 2,\n\tDBUF_S4 = 3,\n\tI915_MAX_DBUF_SLICES = 4,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum depot_counter_id {\n\tDEPOT_COUNTER_REFD_ALLOCS = 0,\n\tDEPOT_COUNTER_REFD_FREES = 1,\n\tDEPOT_COUNTER_REFD_INUSE = 2,\n\tDEPOT_COUNTER_FREELIST_SIZE = 3,\n\tDEPOT_COUNTER_PERSIST_COUNT = 4,\n\tDEPOT_COUNTER_PERSIST_BYTES = 5,\n\tDEPOT_COUNTER_COUNT = 6,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum devcg_behavior {\n\tDEVCG_DEFAULT_NONE = 0,\n\tDEVCG_DEFAULT_ALLOW = 1,\n\tDEVCG_DEFAULT_DENY = 2,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum die_val {\n\tDIE_OOPS = 1,\n\tDIE_INT3 = 2,\n\tDIE_DEBUG = 3,\n\tDIE_PANIC = 4,\n\tDIE_NMI = 5,\n\tDIE_DIE = 6,\n\tDIE_KERNELDEBUG = 7,\n\tDIE_TRAP = 8,\n\tDIE_GPF = 9,\n\tDIE_CALL = 10,\n\tDIE_PAGE_FAULT = 11,\n\tDIE_NMIUNKNOWN = 12,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dm_io_mem_type {\n\tDM_IO_PAGE_LIST = 0,\n\tDM_IO_BIO = 1,\n\tDM_IO_VMA = 2,\n\tDM_IO_KMEM = 3,\n};\n\nenum dm_queue_mode {\n\tDM_TYPE_NONE = 0,\n\tDM_TYPE_BIO_BASED = 1,\n\tDM_TYPE_REQUEST_BASED = 2,\n\tDM_TYPE_DAX_BIO_BASED = 3,\n};\n\nenum dm_raid1_error {\n\tDM_RAID1_WRITE_ERROR = 0,\n\tDM_RAID1_FLUSH_ERROR = 1,\n\tDM_RAID1_SYNC_ERROR = 2,\n\tDM_RAID1_READ_ERROR = 3,\n};\n\nenum dm_rh_region_states {\n\tDM_RH_CLEAN = 1,\n\tDM_RH_DIRTY = 2,\n\tDM_RH_NOSYNC = 4,\n\tDM_RH_RECOVERING = 8,\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n\tDMA_PREP_REPEAT = 256,\n\tDMA_PREP_LOAD_EOT = 512,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SEQNO64_BIT = 0,\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 1,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 2,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 3,\n\tDMA_FENCE_FLAG_USER_BITS = 4,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nenum dma_resv_usage {\n\tDMA_RESV_USAGE_KERNEL = 0,\n\tDMA_RESV_USAGE_WRITE = 1,\n\tDMA_RESV_USAGE_READ = 2,\n\tDMA_RESV_USAGE_BOOKKEEP = 3,\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n\tDMA_SLAVE_BUSWIDTH_128_BYTES = 128,\n};\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n\tDMA_OUT_OF_ORDER = 4,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_COMPLETION_NO_ORDER = 13,\n\tDMA_REPEAT = 14,\n\tDMA_LOAD_EOT = 15,\n\tDMA_TX_TYPE_END = 16,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n\tDMAENGINE_ALIGN_128_BYTES = 7,\n\tDMAENGINE_ALIGN_256_BYTES = 8,\n};\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nenum dmc_event_id {\n\tDMC_EVENT_TRUE = 0,\n\tDMC_EVENT_FALSE = 1,\n};\n\nenum dmi_device_type {\n\tDMI_DEV_TYPE_ANY = 0,\n\tDMI_DEV_TYPE_OTHER = 1,\n\tDMI_DEV_TYPE_UNKNOWN = 2,\n\tDMI_DEV_TYPE_VIDEO = 3,\n\tDMI_DEV_TYPE_SCSI = 4,\n\tDMI_DEV_TYPE_ETHERNET = 5,\n\tDMI_DEV_TYPE_TOKENRING = 6,\n\tDMI_DEV_TYPE_SOUND = 7,\n\tDMI_DEV_TYPE_PATA = 8,\n\tDMI_DEV_TYPE_SATA = 9,\n\tDMI_DEV_TYPE_SAS = 10,\n\tDMI_DEV_TYPE_IPMI = -1,\n\tDMI_DEV_TYPE_OEM_STRING = -2,\n\tDMI_DEV_TYPE_DEV_ONBOARD = -3,\n\tDMI_DEV_TYPE_DEV_SLOT = -4,\n};\n\nenum dmi_entry_type {\n\tDMI_ENTRY_BIOS = 0,\n\tDMI_ENTRY_SYSTEM = 1,\n\tDMI_ENTRY_BASEBOARD = 2,\n\tDMI_ENTRY_CHASSIS = 3,\n\tDMI_ENTRY_PROCESSOR = 4,\n\tDMI_ENTRY_MEM_CONTROLLER = 5,\n\tDMI_ENTRY_MEM_MODULE = 6,\n\tDMI_ENTRY_CACHE = 7,\n\tDMI_ENTRY_PORT_CONNECTOR = 8,\n\tDMI_ENTRY_SYSTEM_SLOT = 9,\n\tDMI_ENTRY_ONBOARD_DEVICE = 10,\n\tDMI_ENTRY_OEMSTRINGS = 11,\n\tDMI_ENTRY_SYSCONF = 12,\n\tDMI_ENTRY_BIOS_LANG = 13,\n\tDMI_ENTRY_GROUP_ASSOC = 14,\n\tDMI_ENTRY_SYSTEM_EVENT_LOG = 15,\n\tDMI_ENTRY_PHYS_MEM_ARRAY = 16,\n\tDMI_ENTRY_MEM_DEVICE = 17,\n\tDMI_ENTRY_32_MEM_ERROR = 18,\n\tDMI_ENTRY_MEM_ARRAY_MAPPED_ADDR = 19,\n\tDMI_ENTRY_MEM_DEV_MAPPED_ADDR = 20,\n\tDMI_ENTRY_BUILTIN_POINTING_DEV = 21,\n\tDMI_ENTRY_PORTABLE_BATTERY = 22,\n\tDMI_ENTRY_SYSTEM_RESET = 23,\n\tDMI_ENTRY_HW_SECURITY = 24,\n\tDMI_ENTRY_SYSTEM_POWER_CONTROLS = 25,\n\tDMI_ENTRY_VOLTAGE_PROBE = 26,\n\tDMI_ENTRY_COOLING_DEV = 27,\n\tDMI_ENTRY_TEMP_PROBE = 28,\n\tDMI_ENTRY_ELECTRICAL_CURRENT_PROBE = 29,\n\tDMI_ENTRY_OOB_REMOTE_ACCESS = 30,\n\tDMI_ENTRY_BIS_ENTRY = 31,\n\tDMI_ENTRY_SYSTEM_BOOT = 32,\n\tDMI_ENTRY_MGMT_DEV = 33,\n\tDMI_ENTRY_MGMT_DEV_COMPONENT = 34,\n\tDMI_ENTRY_MGMT_DEV_THRES = 35,\n\tDMI_ENTRY_MEM_CHANNEL = 36,\n\tDMI_ENTRY_IPMI_DEV = 37,\n\tDMI_ENTRY_SYS_POWER_SUPPLY = 38,\n\tDMI_ENTRY_ADDITIONAL = 39,\n\tDMI_ENTRY_ONBOARD_DEV_EXT = 40,\n\tDMI_ENTRY_MGMT_CONTROLLER_HOST = 41,\n\tDMI_ENTRY_INACTIVE = 126,\n\tDMI_ENTRY_END_OF_TABLE = 127,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dock_callback_type {\n\tDOCK_CALL_HANDLER = 0,\n\tDOCK_CALL_FIXUP = 1,\n\tDOCK_CALL_UEVENT = 2,\n};\n\nenum dp_colorimetry {\n\tDP_COLORIMETRY_DEFAULT = 0,\n\tDP_COLORIMETRY_RGB_WIDE_FIXED = 1,\n\tDP_COLORIMETRY_BT709_YCC = 1,\n\tDP_COLORIMETRY_RGB_WIDE_FLOAT = 2,\n\tDP_COLORIMETRY_XVYCC_601 = 2,\n\tDP_COLORIMETRY_OPRGB = 3,\n\tDP_COLORIMETRY_XVYCC_709 = 3,\n\tDP_COLORIMETRY_DCI_P3_RGB = 4,\n\tDP_COLORIMETRY_SYCC_601 = 4,\n\tDP_COLORIMETRY_RGB_CUSTOM = 5,\n\tDP_COLORIMETRY_OPYCC_601 = 5,\n\tDP_COLORIMETRY_BT2020_RGB = 6,\n\tDP_COLORIMETRY_BT2020_CYCC = 6,\n\tDP_COLORIMETRY_BT2020_YCC = 7,\n};\n\nenum dp_content_type {\n\tDP_CONTENT_TYPE_NOT_DEFINED = 0,\n\tDP_CONTENT_TYPE_GRAPHICS = 1,\n\tDP_CONTENT_TYPE_PHOTO = 2,\n\tDP_CONTENT_TYPE_VIDEO = 3,\n\tDP_CONTENT_TYPE_GAME = 4,\n};\n\nenum dp_dynamic_range {\n\tDP_DYNAMIC_RANGE_VESA = 0,\n\tDP_DYNAMIC_RANGE_CTA = 1,\n};\n\nenum dp_pixelformat {\n\tDP_PIXELFORMAT_RGB = 0,\n\tDP_PIXELFORMAT_YUV444 = 1,\n\tDP_PIXELFORMAT_YUV422 = 2,\n\tDP_PIXELFORMAT_YUV420 = 3,\n\tDP_PIXELFORMAT_Y_ONLY = 4,\n\tDP_PIXELFORMAT_RAW = 5,\n\tDP_PIXELFORMAT_RESERVED = 6,\n};\n\nenum dpio_channel {\n\tDPIO_CH0 = 0,\n\tDPIO_CH1 = 1,\n};\n\nenum dpio_phy {\n\tDPIO_PHY0 = 0,\n\tDPIO_PHY1 = 1,\n\tDPIO_PHY2 = 2,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum drbg_prefixes {\n\tDRBG_PREFIX0 = 0,\n\tDRBG_PREFIX1 = 1,\n\tDRBG_PREFIX2 = 2,\n\tDRBG_PREFIX3 = 3,\n};\n\nenum drbg_seed_state {\n\tDRBG_SEED_STATE_UNSEEDED = 0,\n\tDRBG_SEED_STATE_PARTIAL = 1,\n\tDRBG_SEED_STATE_FULL = 2,\n};\n\nenum drm_bridge_attach_flags {\n\tDRM_BRIDGE_ATTACH_NO_CONNECTOR = 1,\n};\n\nenum drm_bridge_ops {\n\tDRM_BRIDGE_OP_DETECT = 1,\n\tDRM_BRIDGE_OP_EDID = 2,\n\tDRM_BRIDGE_OP_HPD = 4,\n\tDRM_BRIDGE_OP_MODES = 8,\n\tDRM_BRIDGE_OP_HDMI = 16,\n\tDRM_BRIDGE_OP_HDMI_AUDIO = 32,\n\tDRM_BRIDGE_OP_DP_AUDIO = 64,\n\tDRM_BRIDGE_OP_HDMI_CEC_NOTIFIER = 128,\n\tDRM_BRIDGE_OP_HDMI_CEC_ADAPTER = 256,\n\tDRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME = 512,\n\tDRM_BRIDGE_OP_HDMI_SPD_INFOFRAME = 1024,\n};\n\nenum drm_buddy_free_tree {\n\tDRM_BUDDY_CLEAR_TREE = 0,\n\tDRM_BUDDY_DIRTY_TREE = 1,\n\tDRM_BUDDY_MAX_FREE_TREES = 2,\n};\n\nenum drm_color_encoding {\n\tDRM_COLOR_YCBCR_BT601 = 0,\n\tDRM_COLOR_YCBCR_BT709 = 1,\n\tDRM_COLOR_YCBCR_BT2020 = 2,\n\tDRM_COLOR_ENCODING_MAX = 3,\n};\n\nenum drm_color_lut_tests {\n\tDRM_COLOR_LUT_EQUAL_CHANNELS = 1,\n\tDRM_COLOR_LUT_NON_DECREASING = 2,\n};\n\nenum drm_color_range {\n\tDRM_COLOR_YCBCR_LIMITED_RANGE = 0,\n\tDRM_COLOR_YCBCR_FULL_RANGE = 1,\n\tDRM_COLOR_RANGE_MAX = 2,\n};\n\nenum drm_colorop_curve_1d_type {\n\tDRM_COLOROP_1D_CURVE_SRGB_EOTF = 0,\n\tDRM_COLOROP_1D_CURVE_SRGB_INV_EOTF = 1,\n\tDRM_COLOROP_1D_CURVE_PQ_125_EOTF = 2,\n\tDRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF = 3,\n\tDRM_COLOROP_1D_CURVE_BT2020_INV_OETF = 4,\n\tDRM_COLOROP_1D_CURVE_BT2020_OETF = 5,\n\tDRM_COLOROP_1D_CURVE_GAMMA22 = 6,\n\tDRM_COLOROP_1D_CURVE_GAMMA22_INV = 7,\n\tDRM_COLOROP_1D_CURVE_COUNT = 8,\n};\n\nenum drm_colorop_lut1d_interpolation_type {\n\tDRM_COLOROP_LUT1D_INTERPOLATION_LINEAR = 0,\n};\n\nenum drm_colorop_lut3d_interpolation_type {\n\tDRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL = 0,\n};\n\nenum drm_colorop_type {\n\tDRM_COLOROP_1D_CURVE = 0,\n\tDRM_COLOROP_1D_LUT = 1,\n\tDRM_COLOROP_CTM_3X4 = 2,\n\tDRM_COLOROP_MULTIPLIER = 3,\n\tDRM_COLOROP_3D_LUT = 4,\n};\n\nenum drm_colorspace {\n\tDRM_MODE_COLORIMETRY_DEFAULT = 0,\n\tDRM_MODE_COLORIMETRY_NO_DATA = 0,\n\tDRM_MODE_COLORIMETRY_SMPTE_170M_YCC = 1,\n\tDRM_MODE_COLORIMETRY_BT709_YCC = 2,\n\tDRM_MODE_COLORIMETRY_XVYCC_601 = 3,\n\tDRM_MODE_COLORIMETRY_XVYCC_709 = 4,\n\tDRM_MODE_COLORIMETRY_SYCC_601 = 5,\n\tDRM_MODE_COLORIMETRY_OPYCC_601 = 6,\n\tDRM_MODE_COLORIMETRY_OPRGB = 7,\n\tDRM_MODE_COLORIMETRY_BT2020_CYCC = 8,\n\tDRM_MODE_COLORIMETRY_BT2020_RGB = 9,\n\tDRM_MODE_COLORIMETRY_BT2020_YCC = 10,\n\tDRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 = 11,\n\tDRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER = 12,\n\tDRM_MODE_COLORIMETRY_RGB_WIDE_FIXED = 13,\n\tDRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT = 14,\n\tDRM_MODE_COLORIMETRY_BT601_YCC = 15,\n\tDRM_MODE_COLORIMETRY_COUNT = 16,\n};\n\nenum drm_connector_force {\n\tDRM_FORCE_UNSPECIFIED = 0,\n\tDRM_FORCE_OFF = 1,\n\tDRM_FORCE_ON = 2,\n\tDRM_FORCE_ON_DIGITAL = 3,\n};\n\nenum drm_connector_registration_state {\n\tDRM_CONNECTOR_INITIALIZING = 0,\n\tDRM_CONNECTOR_REGISTERED = 1,\n\tDRM_CONNECTOR_UNREGISTERED = 2,\n};\n\nenum drm_connector_status {\n\tconnector_status_connected = 1,\n\tconnector_status_disconnected = 2,\n\tconnector_status_unknown = 3,\n};\n\nenum drm_connector_tv_mode {\n\tDRM_MODE_TV_MODE_NTSC = 0,\n\tDRM_MODE_TV_MODE_NTSC_443 = 1,\n\tDRM_MODE_TV_MODE_NTSC_J = 2,\n\tDRM_MODE_TV_MODE_PAL = 3,\n\tDRM_MODE_TV_MODE_PAL_M = 4,\n\tDRM_MODE_TV_MODE_PAL_N = 5,\n\tDRM_MODE_TV_MODE_SECAM = 6,\n\tDRM_MODE_TV_MODE_MONOCHROME = 7,\n\tDRM_MODE_TV_MODE_MAX = 8,\n};\n\nenum drm_debug_category {\n\tDRM_UT_CORE = 0,\n\tDRM_UT_DRIVER = 1,\n\tDRM_UT_KMS = 2,\n\tDRM_UT_PRIME = 3,\n\tDRM_UT_ATOMIC = 4,\n\tDRM_UT_VBL = 5,\n\tDRM_UT_STATE = 6,\n\tDRM_UT_LEASE = 7,\n\tDRM_UT_DP = 8,\n\tDRM_UT_DRMRES = 9,\n};\n\nenum drm_dp_dual_mode_type {\n\tDRM_DP_DUAL_MODE_NONE = 0,\n\tDRM_DP_DUAL_MODE_UNKNOWN = 1,\n\tDRM_DP_DUAL_MODE_TYPE1_DVI = 2,\n\tDRM_DP_DUAL_MODE_TYPE1_HDMI = 3,\n\tDRM_DP_DUAL_MODE_TYPE2_DVI = 4,\n\tDRM_DP_DUAL_MODE_TYPE2_HDMI = 5,\n\tDRM_DP_DUAL_MODE_LSPCON = 6,\n};\n\nenum drm_dp_mst_mode {\n\tDRM_DP_SST = 0,\n\tDRM_DP_MST = 1,\n\tDRM_DP_SST_SIDEBAND_MSG = 2,\n};\n\nenum drm_dp_mst_payload_allocation {\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_NONE = 0,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_LOCAL = 1,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_DFP = 2,\n\tDRM_DP_MST_PAYLOAD_ALLOCATION_REMOTE = 3,\n};\n\nenum drm_dp_phy {\n\tDP_PHY_DPRX = 0,\n\tDP_PHY_LTTPR1 = 1,\n\tDP_PHY_LTTPR2 = 2,\n\tDP_PHY_LTTPR3 = 3,\n\tDP_PHY_LTTPR4 = 4,\n\tDP_PHY_LTTPR5 = 5,\n\tDP_PHY_LTTPR6 = 6,\n\tDP_PHY_LTTPR7 = 7,\n\tDP_PHY_LTTPR8 = 8,\n\tDP_MAX_LTTPR_COUNT = 8,\n};\n\nenum drm_dp_quirk {\n\tDP_DPCD_QUIRK_CONSTANT_N = 0,\n\tDP_DPCD_QUIRK_NO_PSR = 1,\n\tDP_DPCD_QUIRK_NO_SINK_COUNT = 2,\n\tDP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD = 3,\n\tDP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS = 4,\n\tDP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC = 5,\n\tDP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT = 6,\n};\n\nenum drm_driver_feature {\n\tDRIVER_GEM = 1,\n\tDRIVER_MODESET = 2,\n\tDRIVER_RENDER = 8,\n\tDRIVER_ATOMIC = 16,\n\tDRIVER_SYNCOBJ = 32,\n\tDRIVER_SYNCOBJ_TIMELINE = 64,\n\tDRIVER_COMPUTE_ACCEL = 128,\n\tDRIVER_GEM_GPUVA = 256,\n\tDRIVER_CURSOR_HOTSPOT = 512,\n\tDRIVER_USE_AGP = 33554432,\n\tDRIVER_LEGACY = 67108864,\n\tDRIVER_PCI_DMA = 134217728,\n\tDRIVER_SG = 268435456,\n\tDRIVER_HAVE_DMA = 536870912,\n\tDRIVER_HAVE_IRQ = 1073741824,\n};\n\nenum drm_dsc_params_type {\n\tDRM_DSC_1_2_444 = 0,\n\tDRM_DSC_1_1_PRE_SCR = 1,\n\tDRM_DSC_1_2_422 = 2,\n\tDRM_DSC_1_2_420 = 3,\n};\n\nenum drm_edid_internal_quirk {\n\tEDID_QUIRK_PREFER_LARGE_60 = 1,\n\tEDID_QUIRK_135_CLOCK_TOO_HIGH = 2,\n\tEDID_QUIRK_PREFER_LARGE_75 = 3,\n\tEDID_QUIRK_DETAILED_IN_CM = 4,\n\tEDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 5,\n\tEDID_QUIRK_DETAILED_SYNC_PP = 6,\n\tEDID_QUIRK_FORCE_REDUCED_BLANKING = 7,\n\tEDID_QUIRK_FORCE_8BPC = 8,\n\tEDID_QUIRK_FORCE_12BPC = 9,\n\tEDID_QUIRK_FORCE_6BPC = 10,\n\tEDID_QUIRK_FORCE_10BPC = 11,\n\tEDID_QUIRK_NON_DESKTOP = 12,\n\tEDID_QUIRK_CAP_DSC_15BPP = 13,\n};\n\nenum drm_edid_quirk {\n\tDRM_EDID_QUIRK_DP_DPCD_PROBE = 0,\n\tDRM_EDID_QUIRK_NUM = 1,\n};\n\nenum drm_gem_object_status {\n\tDRM_GEM_OBJECT_RESIDENT = 1,\n\tDRM_GEM_OBJECT_PURGEABLE = 2,\n\tDRM_GEM_OBJECT_ACTIVE = 4,\n};\n\nenum drm_gpuva_flags {\n\tDRM_GPUVA_INVALIDATED = 1,\n\tDRM_GPUVA_SPARSE = 2,\n\tDRM_GPUVA_USERBITS = 4,\n};\n\nenum drm_gpuva_op_type {\n\tDRM_GPUVA_OP_MAP = 0,\n\tDRM_GPUVA_OP_REMAP = 1,\n\tDRM_GPUVA_OP_UNMAP = 2,\n\tDRM_GPUVA_OP_PREFETCH = 3,\n\tDRM_GPUVA_OP_DRIVER = 4,\n};\n\nenum drm_gpuvm_flags {\n\tDRM_GPUVM_RESV_PROTECTED = 1,\n\tDRM_GPUVM_IMMEDIATE_MODE = 2,\n\tDRM_GPUVM_USERBITS = 4,\n};\n\nenum drm_hdmi_broadcast_rgb {\n\tDRM_HDMI_BROADCAST_RGB_AUTO = 0,\n\tDRM_HDMI_BROADCAST_RGB_FULL = 1,\n\tDRM_HDMI_BROADCAST_RGB_LIMITED = 2,\n};\n\nenum drm_i915_gem_engine_class {\n\tI915_ENGINE_CLASS_RENDER = 0,\n\tI915_ENGINE_CLASS_COPY = 1,\n\tI915_ENGINE_CLASS_VIDEO = 2,\n\tI915_ENGINE_CLASS_VIDEO_ENHANCE = 3,\n\tI915_ENGINE_CLASS_COMPUTE = 4,\n\tI915_ENGINE_CLASS_INVALID = -1,\n};\n\nenum drm_i915_gem_memory_class {\n\tI915_MEMORY_CLASS_SYSTEM = 0,\n\tI915_MEMORY_CLASS_DEVICE = 1,\n};\n\nenum drm_i915_oa_format {\n\tI915_OA_FORMAT_A13 = 1,\n\tI915_OA_FORMAT_A29 = 2,\n\tI915_OA_FORMAT_A13_B8_C8 = 3,\n\tI915_OA_FORMAT_B4_C8 = 4,\n\tI915_OA_FORMAT_A45_B8_C8 = 5,\n\tI915_OA_FORMAT_B4_C8_A16 = 6,\n\tI915_OA_FORMAT_C4_B8 = 7,\n\tI915_OA_FORMAT_A12 = 8,\n\tI915_OA_FORMAT_A12_B8_C8 = 9,\n\tI915_OA_FORMAT_A32u40_A4u32_B8_C8 = 10,\n\tI915_OAR_FORMAT_A32u40_A4u32_B8_C8 = 11,\n\tI915_OA_FORMAT_A24u40_A14u32_B8_C8 = 12,\n\tI915_OAM_FORMAT_MPEC8u64_B8_C8 = 13,\n\tI915_OAM_FORMAT_MPEC8u32_B8_C8 = 14,\n\tI915_OA_FORMAT_MAX = 15,\n};\n\nenum drm_i915_perf_property_id {\n\tDRM_I915_PERF_PROP_CTX_HANDLE = 1,\n\tDRM_I915_PERF_PROP_SAMPLE_OA = 2,\n\tDRM_I915_PERF_PROP_OA_METRICS_SET = 3,\n\tDRM_I915_PERF_PROP_OA_FORMAT = 4,\n\tDRM_I915_PERF_PROP_OA_EXPONENT = 5,\n\tDRM_I915_PERF_PROP_HOLD_PREEMPTION = 6,\n\tDRM_I915_PERF_PROP_GLOBAL_SSEU = 7,\n\tDRM_I915_PERF_PROP_POLL_OA_PERIOD = 8,\n\tDRM_I915_PERF_PROP_OA_ENGINE_CLASS = 9,\n\tDRM_I915_PERF_PROP_OA_ENGINE_INSTANCE = 10,\n\tDRM_I915_PERF_PROP_MAX = 11,\n};\n\nenum drm_i915_perf_record_type {\n\tDRM_I915_PERF_RECORD_SAMPLE = 1,\n\tDRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,\n\tDRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,\n\tDRM_I915_PERF_RECORD_MAX = 4,\n};\n\nenum drm_i915_pmu_engine_sample {\n\tI915_SAMPLE_BUSY = 0,\n\tI915_SAMPLE_WAIT = 1,\n\tI915_SAMPLE_SEMA = 2,\n};\n\nenum drm_ioctl_flags {\n\tDRM_AUTH = 1,\n\tDRM_MASTER = 2,\n\tDRM_ROOT_ONLY = 4,\n\tDRM_RENDER_ALLOW = 32,\n};\n\nenum drm_link_status {\n\tDRM_LINK_STATUS_GOOD = 0,\n\tDRM_LINK_STATUS_BAD = 1,\n};\n\nenum drm_lspcon_mode {\n\tDRM_LSPCON_MODE_INVALID = 0,\n\tDRM_LSPCON_MODE_LS = 1,\n\tDRM_LSPCON_MODE_PCON = 2,\n};\n\nenum drm_minor_type {\n\tDRM_MINOR_PRIMARY = 0,\n\tDRM_MINOR_CONTROL = 1,\n\tDRM_MINOR_RENDER = 2,\n\tDRM_MINOR_ACCEL = 32,\n};\n\nenum drm_mm_insert_mode {\n\tDRM_MM_INSERT_BEST = 0,\n\tDRM_MM_INSERT_LOW = 1,\n\tDRM_MM_INSERT_HIGH = 2,\n\tDRM_MM_INSERT_EVICT = 3,\n\tDRM_MM_INSERT_ONCE = 2147483648,\n\tDRM_MM_INSERT_HIGHEST = 2147483650,\n\tDRM_MM_INSERT_LOWEST = 2147483649,\n};\n\nenum drm_mode_analog {\n\tDRM_MODE_ANALOG_NTSC = 0,\n\tDRM_MODE_ANALOG_PAL = 1,\n};\n\nenum drm_mode_status {\n\tMODE_OK = 0,\n\tMODE_HSYNC = 1,\n\tMODE_VSYNC = 2,\n\tMODE_H_ILLEGAL = 3,\n\tMODE_V_ILLEGAL = 4,\n\tMODE_BAD_WIDTH = 5,\n\tMODE_NOMODE = 6,\n\tMODE_NO_INTERLACE = 7,\n\tMODE_NO_DBLESCAN = 8,\n\tMODE_NO_VSCAN = 9,\n\tMODE_MEM = 10,\n\tMODE_VIRTUAL_X = 11,\n\tMODE_VIRTUAL_Y = 12,\n\tMODE_MEM_VIRT = 13,\n\tMODE_NOCLOCK = 14,\n\tMODE_CLOCK_HIGH = 15,\n\tMODE_CLOCK_LOW = 16,\n\tMODE_CLOCK_RANGE = 17,\n\tMODE_BAD_HVALUE = 18,\n\tMODE_BAD_VVALUE = 19,\n\tMODE_BAD_VSCAN = 20,\n\tMODE_HSYNC_NARROW = 21,\n\tMODE_HSYNC_WIDE = 22,\n\tMODE_HBLANK_NARROW = 23,\n\tMODE_HBLANK_WIDE = 24,\n\tMODE_VSYNC_NARROW = 25,\n\tMODE_VSYNC_WIDE = 26,\n\tMODE_VBLANK_NARROW = 27,\n\tMODE_VBLANK_WIDE = 28,\n\tMODE_PANEL = 29,\n\tMODE_INTERLACE_WIDTH = 30,\n\tMODE_ONE_WIDTH = 31,\n\tMODE_ONE_HEIGHT = 32,\n\tMODE_ONE_SIZE = 33,\n\tMODE_NO_REDUCED = 34,\n\tMODE_NO_STEREO = 35,\n\tMODE_NO_420 = 36,\n\tMODE_STALE = -3,\n\tMODE_BAD = -2,\n\tMODE_ERROR = -1,\n};\n\nenum drm_mode_subconnector {\n\tDRM_MODE_SUBCONNECTOR_Automatic = 0,\n\tDRM_MODE_SUBCONNECTOR_Unknown = 0,\n\tDRM_MODE_SUBCONNECTOR_VGA = 1,\n\tDRM_MODE_SUBCONNECTOR_DVID = 3,\n\tDRM_MODE_SUBCONNECTOR_DVIA = 4,\n\tDRM_MODE_SUBCONNECTOR_Composite = 5,\n\tDRM_MODE_SUBCONNECTOR_SVIDEO = 6,\n\tDRM_MODE_SUBCONNECTOR_Component = 8,\n\tDRM_MODE_SUBCONNECTOR_SCART = 9,\n\tDRM_MODE_SUBCONNECTOR_DisplayPort = 10,\n\tDRM_MODE_SUBCONNECTOR_HDMIA = 11,\n\tDRM_MODE_SUBCONNECTOR_Native = 15,\n\tDRM_MODE_SUBCONNECTOR_Wireless = 18,\n};\n\nenum drm_panel_orientation {\n\tDRM_MODE_PANEL_ORIENTATION_UNKNOWN = -1,\n\tDRM_MODE_PANEL_ORIENTATION_NORMAL = 0,\n\tDRM_MODE_PANEL_ORIENTATION_BOTTOM_UP = 1,\n\tDRM_MODE_PANEL_ORIENTATION_LEFT_UP = 2,\n\tDRM_MODE_PANEL_ORIENTATION_RIGHT_UP = 3,\n};\n\nenum drm_plane_type {\n\tDRM_PLANE_TYPE_OVERLAY = 0,\n\tDRM_PLANE_TYPE_PRIMARY = 1,\n\tDRM_PLANE_TYPE_CURSOR = 2,\n};\n\nenum drm_privacy_screen_status {\n\tPRIVACY_SCREEN_DISABLED = 0,\n\tPRIVACY_SCREEN_ENABLED = 1,\n\tPRIVACY_SCREEN_DISABLED_LOCKED = 2,\n\tPRIVACY_SCREEN_ENABLED_LOCKED = 3,\n};\n\nenum drm_scaling_filter {\n\tDRM_SCALING_FILTER_DEFAULT = 0,\n\tDRM_SCALING_FILTER_NEAREST_NEIGHBOR = 1,\n};\n\nenum drm_stat_type {\n\t_DRM_STAT_LOCK = 0,\n\t_DRM_STAT_OPENS = 1,\n\t_DRM_STAT_CLOSES = 2,\n\t_DRM_STAT_IOCTLS = 3,\n\t_DRM_STAT_LOCKS = 4,\n\t_DRM_STAT_UNLOCKS = 5,\n\t_DRM_STAT_VALUE = 6,\n\t_DRM_STAT_BYTE = 7,\n\t_DRM_STAT_COUNT = 8,\n\t_DRM_STAT_IRQ = 9,\n\t_DRM_STAT_PRIMARY = 10,\n\t_DRM_STAT_SECONDARY = 11,\n\t_DRM_STAT_DMA = 12,\n\t_DRM_STAT_SPECIAL = 13,\n\t_DRM_STAT_MISSED = 14,\n};\n\nenum drm_vblank_seq_type {\n\t_DRM_VBLANK_ABSOLUTE = 0,\n\t_DRM_VBLANK_RELATIVE = 1,\n\t_DRM_VBLANK_HIGH_CRTC_MASK = 62,\n\t_DRM_VBLANK_EVENT = 67108864,\n\t_DRM_VBLANK_FLIP = 134217728,\n\t_DRM_VBLANK_NEXTONMISS = 268435456,\n\t_DRM_VBLANK_SECONDARY = 536870912,\n\t_DRM_VBLANK_SIGNAL = 1073741824,\n};\n\nenum drrs_refresh_rate {\n\tDRRS_REFRESH_RATE_HIGH = 0,\n\tDRRS_REFRESH_RATE_LOW = 1,\n};\n\nenum drrs_type {\n\tDRRS_TYPE_NONE = 0,\n\tDRRS_TYPE_STATIC = 1,\n\tDRRS_TYPE_SEAMLESS = 2,\n};\n\nenum dw_dma_fc {\n\tDW_DMA_FC_D_M2M = 0,\n\tDW_DMA_FC_D_M2P = 1,\n\tDW_DMA_FC_D_P2M = 2,\n\tDW_DMA_FC_D_P2P = 3,\n\tDW_DMA_FC_P_P2M = 4,\n\tDW_DMA_FC_SP_P2P = 5,\n\tDW_DMA_FC_P_M2P = 6,\n\tDW_DMA_FC_DP_P2P = 7,\n};\n\nenum dw_dmac_flags {\n\tDW_DMA_IS_CYCLIC = 0,\n\tDW_DMA_IS_SOFT_LLP = 1,\n\tDW_DMA_IS_PAUSED = 2,\n\tDW_DMA_IS_INITIALIZED = 3,\n};\n\nenum dyn_constr_type {\n\tDYN_CONSTR_NONE = 0,\n\tDYN_CONSTR_BR_CNTR = 1,\n\tDYN_CONSTR_ACR_CNTR = 2,\n\tDYN_CONSTR_ACR_CAUSE = 3,\n\tDYN_CONSTR_PEBS = 4,\n\tDYN_CONSTR_PDIST = 5,\n\tDYN_CONSTR_MAX = 6,\n};\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok___2 = 0,\n\te1000_1000t_rx_status_ok___2 = 1,\n\te1000_1000t_rx_status_undefined___2 = 255,\n};\n\nenum e1000_boards {\n\tboard_82571 = 0,\n\tboard_82572 = 1,\n\tboard_82573 = 2,\n\tboard_82574 = 3,\n\tboard_82583 = 4,\n\tboard_80003es2lan = 5,\n\tboard_ich8lan = 6,\n\tboard_ich9lan = 7,\n\tboard_ich10lan = 8,\n\tboard_pchlan = 9,\n\tboard_pch2lan = 10,\n\tboard_pch_lpt = 11,\n\tboard_pch_spt = 12,\n\tboard_pch_cnp = 13,\n\tboard_pch_tgp = 14,\n\tboard_pch_adp = 15,\n\tboard_pch_mtp = 16,\n\tboard_pch_ptp = 17,\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown___2 = 0,\n\te1000_bus_width_pcie_x1 = 1,\n\te1000_bus_width_pcie_x2 = 2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32___2 = 9,\n\te1000_bus_width_64___2 = 10,\n\te1000_bus_width_reserved___2 = 11,\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause = 1,\n\te1000_fc_tx_pause = 2,\n\te1000_fc_full = 3,\n\te1000_fc_default = 255,\n};\n\nenum e1000_mac_type {\n\te1000_82571 = 0,\n\te1000_82572 = 1,\n\te1000_82573 = 2,\n\te1000_82574 = 3,\n\te1000_82583 = 4,\n\te1000_80003es2lan = 5,\n\te1000_ich8lan = 6,\n\te1000_ich9lan = 7,\n\te1000_ich10lan = 8,\n\te1000_pchlan = 9,\n\te1000_pch2lan = 10,\n\te1000_pch_lpt = 11,\n\te1000_pch_spt = 12,\n\te1000_pch_cnp = 13,\n\te1000_pch_tgp = 14,\n\te1000_pch_adp = 15,\n\te1000_pch_mtp = 16,\n\te1000_pch_lnp = 17,\n\te1000_pch_ptp = 18,\n\te1000_pch_nvp = 19,\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper___2 = 1,\n\te1000_media_type_fiber___2 = 2,\n\te1000_media_type_internal_serdes___2 = 3,\n\te1000_num_media_types___2 = 4,\n};\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf = 1,\n\te1000_mng_mode_pt = 2,\n\te1000_mng_mode_ipmi = 3,\n\te1000_mng_mode_host_if_only = 4,\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default___2 = 0,\n\te1000_ms_force_master___2 = 1,\n\te1000_ms_force_slave___2 = 2,\n\te1000_ms_auto___2 = 3,\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small = 1,\n\te1000_nvm_override_spi_large = 2,\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none = 1,\n\te1000_nvm_eeprom_spi = 2,\n\te1000_nvm_flash_hw = 3,\n\te1000_nvm_flash_sw = 4,\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none = 1,\n\te1000_phy_m88___2 = 2,\n\te1000_phy_igp___2 = 3,\n\te1000_phy_igp_2 = 4,\n\te1000_phy_gg82563 = 5,\n\te1000_phy_igp_3 = 6,\n\te1000_phy_ife = 7,\n\te1000_phy_bm = 8,\n\te1000_phy_82578 = 9,\n\te1000_phy_82577 = 10,\n\te1000_phy_82579 = 11,\n\te1000_phy_i217 = 12,\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal___2 = 0,\n\te1000_rev_polarity_reversed___2 = 1,\n\te1000_rev_polarity_undefined___2 = 255,\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress = 1,\n\te1000_serdes_link_autoneg_complete = 2,\n\te1000_serdes_link_forced_up = 3,\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default___2 = 0,\n\te1000_smart_speed_on___2 = 1,\n\te1000_smart_speed_off___2 = 2,\n};\n\nenum e1000_state_t {\n\t__E1000_TESTING = 0,\n\t__E1000_RESETTING = 1,\n\t__E1000_ACCESS_SHARED_RESOURCE = 2,\n\t__E1000_DOWN = 3,\n};\n\nenum e1000_state_t___2 {\n\t__E1000_TESTING___2 = 0,\n\t__E1000_RESETTING___2 = 1,\n\t__E1000_DOWN___2 = 2,\n\t__E1000_DISABLED = 3,\n};\n\nenum e1000_ulp_state {\n\te1000_ulp_state_unknown = 0,\n\te1000_ulp_state_off = 1,\n\te1000_ulp_state_on = 2,\n};\n\nenum e820_type {\n\tE820_TYPE_RAM = 1,\n\tE820_TYPE_RESERVED = 2,\n\tE820_TYPE_ACPI = 3,\n\tE820_TYPE_NVS = 4,\n\tE820_TYPE_UNUSABLE = 5,\n\tE820_TYPE_PMEM = 7,\n\tE820_TYPE_PRAM = 12,\n\tE820_TYPE_SOFT_RESERVED = 4026531839,\n};\n\nenum ec_command {\n\tACPI_EC_COMMAND_READ = 128,\n\tACPI_EC_COMMAND_WRITE = 129,\n\tACPI_EC_BURST_ENABLE = 130,\n\tACPI_EC_BURST_DISABLE = 131,\n\tACPI_EC_COMMAND_QUERY = 132,\n};\n\nenum edid_block_status {\n\tEDID_BLOCK_OK = 0,\n\tEDID_BLOCK_READ_FAIL = 1,\n\tEDID_BLOCK_NULL = 2,\n\tEDID_BLOCK_ZERO = 3,\n\tEDID_BLOCK_HEADER_CORRUPT = 4,\n\tEDID_BLOCK_HEADER_REPAIR = 5,\n\tEDID_BLOCK_HEADER_FIXED = 6,\n\tEDID_BLOCK_CHECKSUM = 7,\n\tEDID_BLOCK_VERSION = 8,\n};\n\nenum eeprom_cnfg_mdix {\n\teeprom_mdix_enabled = 128,\n};\n\nenum eeprom_config_asf {\n\teeprom_asf = 32768,\n\teeprom_gcl = 16384,\n};\n\nenum eeprom_ctrl_lo {\n\teesk = 1,\n\teecs = 2,\n\teedi = 4,\n\teedo = 8,\n};\n\nenum eeprom_id {\n\teeprom_id_wol = 32,\n};\n\nenum eeprom_offsets {\n\teeprom_cnfg_mdix = 3,\n\teeprom_phy_iface = 6,\n\teeprom_id = 10,\n\teeprom_config_asf = 13,\n\teeprom_smbus_addr = 144,\n};\n\nenum eeprom_op {\n\top_write = 5,\n\top_read = 6,\n\top_ewds = 16,\n\top_ewen = 19,\n};\n\nenum eeprom_phy_iface {\n\tNoSuchPhy = 0,\n\tI82553AB = 1,\n\tI82553C = 2,\n\tI82503 = 3,\n\tDP83840 = 4,\n\tS80C240 = 5,\n\tS80C24 = 6,\n\tI82555 = 7,\n\tDP83840A = 10,\n};\n\nenum efi_rts_ids {\n\tEFI_NONE = 0,\n\tEFI_GET_TIME = 1,\n\tEFI_SET_TIME = 2,\n\tEFI_GET_WAKEUP_TIME = 3,\n\tEFI_SET_WAKEUP_TIME = 4,\n\tEFI_GET_VARIABLE = 5,\n\tEFI_GET_NEXT_VARIABLE = 6,\n\tEFI_SET_VARIABLE = 7,\n\tEFI_QUERY_VARIABLE_INFO = 8,\n\tEFI_GET_NEXT_HIGH_MONO_COUNT = 9,\n\tEFI_RESET_SYSTEM = 10,\n\tEFI_UPDATE_CAPSULE = 11,\n\tEFI_QUERY_CAPSULE_CAPS = 12,\n\tEFI_ACPI_PRM_HANDLER = 13,\n};\n\nenum efi_secureboot_mode {\n\tefi_secureboot_mode_unset = 0,\n\tefi_secureboot_mode_unknown = 1,\n\tefi_secureboot_mode_disabled = 2,\n\tefi_secureboot_mode_enabled = 3,\n};\n\nenum ehci_hrtimer_event {\n\tEHCI_HRTIMER_POLL_ASS = 0,\n\tEHCI_HRTIMER_POLL_PSS = 1,\n\tEHCI_HRTIMER_POLL_DEAD = 2,\n\tEHCI_HRTIMER_UNLINK_INTR = 3,\n\tEHCI_HRTIMER_FREE_ITDS = 4,\n\tEHCI_HRTIMER_ACTIVE_UNLINK = 5,\n\tEHCI_HRTIMER_START_UNLINK_INTR = 6,\n\tEHCI_HRTIMER_ASYNC_UNLINKS = 7,\n\tEHCI_HRTIMER_IAA_WATCHDOG = 8,\n\tEHCI_HRTIMER_DISABLE_PERIODIC = 9,\n\tEHCI_HRTIMER_DISABLE_ASYNC = 10,\n\tEHCI_HRTIMER_IO_WATCHDOG = 11,\n\tEHCI_HRTIMER_NUM_EVENTS = 12,\n};\n\nenum ehci_rh_state {\n\tEHCI_RH_HALTED = 0,\n\tEHCI_RH_SUSPENDED = 1,\n\tEHCI_RH_RUNNING = 2,\n\tEHCI_RH_STOPPING = 3,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum energy_perf_value_index {\n\tEPB_INDEX_PERFORMANCE = 0,\n\tEPB_INDEX_BALANCE_PERFORMANCE = 1,\n\tEPB_INDEX_NORMAL = 2,\n\tEPB_INDEX_BALANCE_POWERSAVE = 3,\n\tEPB_INDEX_POWERSAVE = 4,\n};\n\nenum energy_perf_value_index___2 {\n\tEPP_INDEX_DEFAULT = 0,\n\tEPP_INDEX_PERFORMANCE = 1,\n\tEPP_INDEX_BALANCE_PERFORMANCE = 2,\n\tEPP_INDEX_BALANCE_POWERSAVE = 3,\n\tEPP_INDEX_POWERSAVE = 4,\n};\n\nenum energy_perf_value_index___3 {\n\tEPP_INDEX_DEFAULT___2 = 0,\n\tEPP_INDEX_PERFORMANCE___2 = 1,\n\tEPP_INDEX_BALANCE_PERFORMANCE___2 = 2,\n\tEPP_INDEX_BALANCE_POWERSAVE___2 = 3,\n\tEPP_INDEX_POWERSAVE___2 = 4,\n\tEPP_INDEX_MAX = 5,\n};\n\nenum environment_cap {\n\tENVIRON_ANY = 0,\n\tENVIRON_INDOOR = 1,\n\tENVIRON_OUTDOOR = 2,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n\tETT_EVENT_EPROBE = 64,\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_FROZEN = 8,\n\tEVENT_CPU = 16,\n\tEVENT_CGROUP = 32,\n\tEVENT_GUEST = 64,\n\tEVENT_FLAGS = 96,\n\tEVENT_ALL = 3,\n\tEVENT_TIME_FROZEN = 12,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum exception {\n\tEXCP_CONTEXT = 1,\n\tNO_EXCP = 2,\n};\n\nenum exception_stack_ordering {\n\tESTACK_DF = 0,\n\tESTACK_NMI = 1,\n\tESTACK_DB = 2,\n\tESTACK_MCE = 3,\n\tESTACK_VC = 4,\n\tESTACK_VC2 = 5,\n\tN_EXCEPTION_STACKS = 6,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum exit_fastpath_completion {\n\tEXIT_FASTPATH_NONE = 0,\n\tEXIT_FASTPATH_REENTER_GUEST = 1,\n\tEXIT_FASTPATH_EXIT_HANDLED = 2,\n\tEXIT_FASTPATH_EXIT_USERSPACE = 3,\n};\n\nenum ext4_journal_trigger_type {\n\tEXT4_JTR_ORPHAN_FILE = 0,\n\tEXT4_JTR_NONE = 1,\n};\n\nenum ext4_li_mode {\n\tEXT4_LI_MODE_PREFETCH_BBITMAP = 0,\n\tEXT4_LI_MODE_ITABLE = 1,\n};\n\nenum extra_reg_type {\n\tEXTRA_REG_NONE = -1,\n\tEXTRA_REG_RSP_0 = 0,\n\tEXTRA_REG_RSP_1 = 1,\n\tEXTRA_REG_LBR = 2,\n\tEXTRA_REG_LDLAT = 3,\n\tEXTRA_REG_FE = 4,\n\tEXTRA_REG_SNOOP_0 = 5,\n\tEXTRA_REG_SNOOP_1 = 6,\n\tEXTRA_REG_OMR_0 = 7,\n\tEXTRA_REG_OMR_1 = 8,\n\tEXTRA_REG_OMR_2 = 9,\n\tEXTRA_REG_OMR_3 = 10,\n\tEXTRA_REG_MAX = 11,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum faulttype {\n\tDMA_REMAP = 0,\n\tINTR_REMAP = 1,\n\tUNKNOWN = 2,\n};\n\nenum fb_op_origin {\n\tORIGIN_CPU = 0,\n\tORIGIN_CS = 1,\n\tORIGIN_FLIP = 2,\n\tORIGIN_DIRTYFB = 3,\n\tORIGIN_CURSOR_UPDATE = 4,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_EDATA = 10,\n\tFETCH_OP_DEREF = 11,\n\tFETCH_OP_UDEREF = 12,\n\tFETCH_OP_ST_RAW = 13,\n\tFETCH_OP_ST_MEM = 14,\n\tFETCH_OP_ST_UMEM = 15,\n\tFETCH_OP_ST_STRING = 16,\n\tFETCH_OP_ST_USTRING = 17,\n\tFETCH_OP_ST_SYMSTR = 18,\n\tFETCH_OP_ST_EDATA = 19,\n\tFETCH_OP_MOD_BF = 20,\n\tFETCH_OP_LP_ARRAY = 21,\n\tFETCH_OP_TP_ARG = 22,\n\tFETCH_OP_END = 23,\n\tFETCH_NOP_SYMBOL = 24,\n};\n\nenum fib6_walk_state {\n\tFWS_L = 0,\n\tFWS_R = 1,\n\tFWS_C = 2,\n\tFWS_U = 3,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum file_state {\n\tMEI_FILE_UNINITIALIZED = 0,\n\tMEI_FILE_INITIALIZING = 1,\n\tMEI_FILE_CONNECTING = 2,\n\tMEI_FILE_CONNECTED = 3,\n\tMEI_FILE_DISCONNECTING = 4,\n\tMEI_FILE_DISCONNECT_REPLY = 5,\n\tMEI_FILE_DISCONNECT_REQUIRED = 6,\n\tMEI_FILE_DISCONNECTED = 7,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum filter_pred_fn {\n\tFILTER_PRED_FN_NOP = 0,\n\tFILTER_PRED_FN_64 = 1,\n\tFILTER_PRED_FN_64_CPUMASK = 2,\n\tFILTER_PRED_FN_S64 = 3,\n\tFILTER_PRED_FN_U64 = 4,\n\tFILTER_PRED_FN_32 = 5,\n\tFILTER_PRED_FN_32_CPUMASK = 6,\n\tFILTER_PRED_FN_S32 = 7,\n\tFILTER_PRED_FN_U32 = 8,\n\tFILTER_PRED_FN_16 = 9,\n\tFILTER_PRED_FN_16_CPUMASK = 10,\n\tFILTER_PRED_FN_S16 = 11,\n\tFILTER_PRED_FN_U16 = 12,\n\tFILTER_PRED_FN_8 = 13,\n\tFILTER_PRED_FN_8_CPUMASK = 14,\n\tFILTER_PRED_FN_S8 = 15,\n\tFILTER_PRED_FN_U8 = 16,\n\tFILTER_PRED_FN_COMM = 17,\n\tFILTER_PRED_FN_STRING = 18,\n\tFILTER_PRED_FN_STRLOC = 19,\n\tFILTER_PRED_FN_STRRELLOC = 20,\n\tFILTER_PRED_FN_PCHAR_USER = 21,\n\tFILTER_PRED_FN_PCHAR = 22,\n\tFILTER_PRED_FN_CPU = 23,\n\tFILTER_PRED_FN_CPU_CPUMASK = 24,\n\tFILTER_PRED_FN_CPUMASK = 25,\n\tFILTER_PRED_FN_CPUMASK_CPU = 26,\n\tFILTER_PRED_FN_FUNCTION = 27,\n\tFILTER_PRED_FN_ = 28,\n\tFILTER_PRED_TEST_VISITED = 29,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum fixed_addresses {\n\tVSYSCALL_PAGE = 511,\n\tFIX_DBGP_BASE = 512,\n\tFIX_EARLYCON_MEM_BASE = 513,\n\tFIX_OHCI1394_BASE = 514,\n\tFIX_APIC_BASE = 515,\n\tFIX_IO_APIC_BASE_0 = 516,\n\tFIX_IO_APIC_BASE_END = 643,\n\t__end_of_permanent_fixed_addresses = 644,\n\tFIX_BTMAP_END = 1024,\n\tFIX_BTMAP_BEGIN = 1535,\n\t__end_of_fixed_addresses = 1536,\n};\n\nenum flag_bits {\n\tFaulty = 0,\n\tIn_sync = 1,\n\tBitmap_sync = 2,\n\tWriteMostly = 3,\n\tAutoDetected = 4,\n\tBlocked = 5,\n\tWriteErrorSeen = 6,\n\tFaultRecorded = 7,\n\tBlockedBadBlocks = 8,\n\tWantReplacement = 9,\n\tReplacement = 10,\n\tCandidate = 11,\n\tJournal = 12,\n\tClusterRemove = 13,\n\tExternalBbl = 14,\n\tFailFast = 15,\n\tLastDev = 16,\n\tCollisionCheck = 17,\n\tNonrot = 18,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_control {\n\tFC_NONE = 0,\n\tFC_TX = 1,\n\tFC_RX = 2,\n\tFC_BOTH = 3,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum flowlabel_reflect {\n\tFLOWLABEL_REFLECT_ESTABLISHED = 1,\n\tFLOWLABEL_REFLECT_TCP_RESET = 2,\n\tFLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum forcewake_domain_id {\n\tFW_DOMAIN_ID_RENDER = 0,\n\tFW_DOMAIN_ID_GT = 1,\n\tFW_DOMAIN_ID_MEDIA = 2,\n\tFW_DOMAIN_ID_MEDIA_VDBOX0 = 3,\n\tFW_DOMAIN_ID_MEDIA_VDBOX1 = 4,\n\tFW_DOMAIN_ID_MEDIA_VDBOX2 = 5,\n\tFW_DOMAIN_ID_MEDIA_VDBOX3 = 6,\n\tFW_DOMAIN_ID_MEDIA_VDBOX4 = 7,\n\tFW_DOMAIN_ID_MEDIA_VDBOX5 = 8,\n\tFW_DOMAIN_ID_MEDIA_VDBOX6 = 9,\n\tFW_DOMAIN_ID_MEDIA_VDBOX7 = 10,\n\tFW_DOMAIN_ID_MEDIA_VEBOX0 = 11,\n\tFW_DOMAIN_ID_MEDIA_VEBOX1 = 12,\n\tFW_DOMAIN_ID_MEDIA_VEBOX2 = 13,\n\tFW_DOMAIN_ID_MEDIA_VEBOX3 = 14,\n\tFW_DOMAIN_ID_GSC = 15,\n\tFW_DOMAIN_ID_COUNT = 16,\n};\n\nenum forcewake_domains {\n\tFORCEWAKE_RENDER = 1,\n\tFORCEWAKE_GT = 2,\n\tFORCEWAKE_MEDIA = 4,\n\tFORCEWAKE_MEDIA_VDBOX0 = 8,\n\tFORCEWAKE_MEDIA_VDBOX1 = 16,\n\tFORCEWAKE_MEDIA_VDBOX2 = 32,\n\tFORCEWAKE_MEDIA_VDBOX3 = 64,\n\tFORCEWAKE_MEDIA_VDBOX4 = 128,\n\tFORCEWAKE_MEDIA_VDBOX5 = 256,\n\tFORCEWAKE_MEDIA_VDBOX6 = 512,\n\tFORCEWAKE_MEDIA_VDBOX7 = 1024,\n\tFORCEWAKE_MEDIA_VEBOX0 = 2048,\n\tFORCEWAKE_MEDIA_VEBOX1 = 4096,\n\tFORCEWAKE_MEDIA_VEBOX2 = 8192,\n\tFORCEWAKE_MEDIA_VEBOX3 = 16384,\n\tFORCEWAKE_GSC = 32768,\n\tFORCEWAKE_ALL = 65535,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fscache_cache_state {\n\tFSCACHE_CACHE_IS_NOT_PRESENT = 0,\n\tFSCACHE_CACHE_IS_PREPARING = 1,\n\tFSCACHE_CACHE_IS_ACTIVE = 2,\n\tFSCACHE_CACHE_GOT_IOERROR = 3,\n\tFSCACHE_CACHE_IS_WITHDRAWN = 4,\n};\n\nenum fscache_cookie_state {\n\tFSCACHE_COOKIE_STATE_QUIESCENT = 0,\n\tFSCACHE_COOKIE_STATE_LOOKING_UP = 1,\n\tFSCACHE_COOKIE_STATE_CREATING = 2,\n\tFSCACHE_COOKIE_STATE_ACTIVE = 3,\n\tFSCACHE_COOKIE_STATE_INVALIDATING = 4,\n\tFSCACHE_COOKIE_STATE_FAILED = 5,\n\tFSCACHE_COOKIE_STATE_LRU_DISCARDING = 6,\n\tFSCACHE_COOKIE_STATE_WITHDRAWING = 7,\n\tFSCACHE_COOKIE_STATE_RELINQUISHING = 8,\n\tFSCACHE_COOKIE_STATE_DROPPED = 9,\n} __attribute__((mode(byte)));\n\nenum fscache_want_state {\n\tFSCACHE_WANT_PARAMS = 0,\n\tFSCACHE_WANT_WRITE = 1,\n\tFSCACHE_WANT_READ = 2,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum fw_hdcp_status {\n\tFW_HDCP_STATUS_SUCCESS = 0,\n\tFW_HDCP_STATUS_INTERNAL_ERROR = 4096,\n\tFW_HDCP_STATUS_UNKNOWN_ERROR = 4097,\n\tFW_HDCP_STATUS_INCORRECT_API_VERSION = 4098,\n\tFW_HDCP_STATUS_INVALID_FUNCTION = 4099,\n\tFW_HDCP_STATUS_INVALID_BUFFER_LENGTH = 4100,\n\tFW_HDCP_STATUS_INVALID_PARAMS = 4101,\n\tFW_HDCP_STATUS_AUTHENTICATION_FAILED = 4102,\n\tFW_HDCP_INVALID_SESSION_STATE = 24576,\n\tFW_HDCP_SRM_FRAGMENT_UNEXPECTED = 24577,\n\tFW_HDCP_SRM_INVALID_LENGTH = 24578,\n\tFW_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 24579,\n\tFW_HDCP_SRM_VERIFICATION_FAILED = 24580,\n\tFW_HDCP_SRM_VERSION_TOO_OLD = 24581,\n\tFW_HDCP_RX_CERT_VERIFICATION_FAILED = 24582,\n\tFW_HDCP_RX_REVOKED = 24583,\n\tFW_HDCP_H_VERIFICATION_FAILED = 24584,\n\tFW_HDCP_REPEATER_CHECK_UNEXPECTED = 24585,\n\tFW_HDCP_TOPOLOGY_MAX_EXCEEDED = 24586,\n\tFW_HDCP_V_VERIFICATION_FAILED = 24587,\n\tFW_HDCP_L_VERIFICATION_FAILED = 24588,\n\tFW_HDCP_STREAM_KEY_ALLOC_FAILED = 24589,\n\tFW_HDCP_BASE_KEY_RESET_FAILED = 24590,\n\tFW_HDCP_NONCE_GENERATION_FAILED = 24591,\n\tFW_HDCP_STATUS_INVALID_E_KEY_STATE = 24592,\n\tFW_HDCP_STATUS_INVALID_CS_ICV = 24593,\n\tFW_HDCP_STATUS_INVALID_KB_KEY_STATE = 24594,\n\tFW_HDCP_STATUS_INVALID_PAVP_MODE_ICV = 24595,\n\tFW_HDCP_STATUS_INVALID_PAVP_MODE = 24596,\n\tFW_HDCP_STATUS_LC_MAX_ATTEMPTS = 24597,\n\tFW_HDCP_STATUS_MISMATCH_IN_M = 24598,\n\tFW_HDCP_STATUS_RX_PROV_NOT_ALLOWED = 24599,\n\tFW_HDCP_STATUS_RX_PROV_WRONG_SUBJECT = 24600,\n\tFW_HDCP_RX_NEEDS_PROVISIONING = 24601,\n\tFW_HDCP_BKSV_ICV_AUTH_FAILED = 24608,\n\tFW_HDCP_STATUS_INVALID_STREAM_ID = 24609,\n\tFW_HDCP_STATUS_CHAIN_NOT_INITIALIZED = 24610,\n\tFW_HDCP_FAIL_NOT_EXPECTED = 24611,\n\tFW_HDCP_FAIL_HDCP_OFF = 24612,\n\tFW_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE = 24613,\n\tFW_HDCP_FAIL_AES_ECB_FAILURE = 24614,\n\tFW_HDCP_FEATURE_NOT_SUPPORTED = 24615,\n\tFW_HDCP_DMA_READ_ERROR = 24616,\n\tFW_HDCP_DMA_WRITE_ERROR = 24617,\n\tFW_HDCP_FAIL_INVALID_PACKET_SIZE = 24624,\n\tFW_HDCP_H264_PARSING_ERROR = 24625,\n\tFW_HDCP_HDCP2_ERRATA_VIDEO_VIOLATION = 24626,\n\tFW_HDCP_HDCP2_ERRATA_AUDIO_VIOLATION = 24627,\n\tFW_HDCP_TX_ACTIVE_ERROR = 24628,\n\tFW_HDCP_MODE_CHANGE_ERROR = 24629,\n\tFW_HDCP_STREAM_TYPE_ERROR = 24630,\n\tFW_HDCP_STREAM_MANAGE_NOT_POSSIBLE = 24631,\n\tFW_HDCP_STATUS_PORT_INVALID_COMMAND = 24632,\n\tFW_HDCP_STATUS_UNSUPPORTED_PROTOCOL = 24633,\n\tFW_HDCP_STATUS_INVALID_PORT_INDEX = 24634,\n\tFW_HDCP_STATUS_TX_AUTH_NEEDED = 24635,\n\tFW_HDCP_STATUS_NOT_INTEGRATED_PORT = 24636,\n\tFW_HDCP_STATUS_SESSION_MAX_REACHED = 24637,\n\tFW_HDCP_STATUS_NOT_HDCP_CAPABLE = 24641,\n\tFW_HDCP_STATUS_INVALID_STREAM_COUNT = 24642,\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n\tFW_OPT_PARTIAL = 128,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nenum fwdb_flags {\n\tFWDB_FLAG_NO_OFDM = 1,\n\tFWDB_FLAG_NO_OUTDOOR = 2,\n\tFWDB_FLAG_DFS = 4,\n\tFWDB_FLAG_NO_IR = 8,\n\tFWDB_FLAG_AUTO_BW = 16,\n};\n\nenum g4x_wm_level {\n\tG4X_WM_LEVEL_NORMAL = 0,\n\tG4X_WM_LEVEL_SR = 1,\n\tG4X_WM_LEVEL_HPLL = 2,\n\tNUM_G4X_WM_LEVELS = 3,\n};\n\nenum gddrnf4_status {\n\tGDD4_OK = 0,\n\tGDD4_UNAVAIL = 1,\n};\n\nenum gds_mitigations {\n\tGDS_MITIGATION_OFF = 0,\n\tGDS_MITIGATION_AUTO = 1,\n\tGDS_MITIGATION_UCODE_NEEDED = 2,\n\tGDS_MITIGATION_FORCE = 3,\n\tGDS_MITIGATION_FULL = 4,\n\tGDS_MITIGATION_FULL_LOCKED = 5,\n\tGDS_MITIGATION_HYPERVISOR = 6,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum gmbus_gpio {\n\tGPIOA = 0,\n\tGPIOB = 1,\n\tGPIOC = 2,\n\tGPIOD = 3,\n\tGPIOE = 4,\n\tGPIOF = 5,\n\tGPIOG = 6,\n\tGPIOH = 7,\n\t__GPIOI_UNUSED = 8,\n\tGPIOJ = 9,\n\tGPIOK = 10,\n\tGPIOL = 11,\n\tGPIOM = 12,\n\tGPION = 13,\n\tGPIOO = 14,\n};\n\nenum gpio_lookup_flags {\n\tGPIO_ACTIVE_HIGH = 0,\n\tGPIO_ACTIVE_LOW = 1,\n\tGPIO_OPEN_DRAIN = 2,\n\tGPIO_OPEN_SOURCE = 4,\n\tGPIO_PERSISTENT = 0,\n\tGPIO_TRANSITORY = 8,\n\tGPIO_PULL_UP = 16,\n\tGPIO_PULL_DOWN = 32,\n\tGPIO_PULL_DISABLE = 64,\n\tGPIO_LOOKUP_FLAGS_DEFAULT = 0,\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum guc_capture_group_types {\n\tGUC_STATE_CAPTURE_GROUP_TYPE_FULL = 0,\n\tGUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL = 1,\n\tGUC_STATE_CAPTURE_GROUP_TYPE_MAX = 2,\n};\n\nenum guc_capture_type {\n\tGUC_CAPTURE_LIST_TYPE_GLOBAL = 0,\n\tGUC_CAPTURE_LIST_TYPE_ENGINE_CLASS = 1,\n\tGUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE = 2,\n\tGUC_CAPTURE_LIST_TYPE_MAX = 3,\n};\n\nenum guc_log_buffer_type {\n\tGUC_DEBUG_LOG_BUFFER = 0,\n\tGUC_CRASH_DUMP_LOG_BUFFER = 1,\n\tGUC_CAPTURE_LOG_BUFFER = 2,\n\tGUC_MAX_LOG_BUFFER = 3,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum handshake_auth {\n\tHANDSHAKE_AUTH_UNSPEC = 0,\n\tHANDSHAKE_AUTH_UNAUTH = 1,\n\tHANDSHAKE_AUTH_PSK = 2,\n\tHANDSHAKE_AUTH_X509 = 3,\n};\n\nenum handshake_handler_class {\n\tHANDSHAKE_HANDLER_CLASS_NONE = 0,\n\tHANDSHAKE_HANDLER_CLASS_TLSHD = 1,\n\tHANDSHAKE_HANDLER_CLASS_MAX = 2,\n};\n\nenum handshake_msg_type {\n\tHANDSHAKE_MSG_TYPE_UNSPEC = 0,\n\tHANDSHAKE_MSG_TYPE_CLIENTHELLO = 1,\n\tHANDSHAKE_MSG_TYPE_SERVERHELLO = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hbm_host_enum_flags {\n\tMEI_HBM_ENUM_F_ALLOW_ADD = 1,\n\tMEI_HBM_ENUM_F_IMMEDIATE_ENUM = 2,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum hdcp_command_id {\n\t_WIDI_COMMAND_BASE = 196608,\n\tWIDI_INITIATE_HDCP2_SESSION = 196608,\n\tHDCP_GET_SRM_STATUS = 196609,\n\tHDCP_SEND_SRM_FRAGMENT = 196610,\n\t_WIRED_COMMAND_BASE = 200704,\n\tWIRED_INITIATE_HDCP2_SESSION = 200704,\n\tWIRED_VERIFY_RECEIVER_CERT = 200705,\n\tWIRED_AKE_SEND_HPRIME = 200706,\n\tWIRED_AKE_SEND_PAIRING_INFO = 200707,\n\tWIRED_INIT_LOCALITY_CHECK = 200708,\n\tWIRED_VALIDATE_LOCALITY = 200709,\n\tWIRED_GET_SESSION_KEY = 200710,\n\tWIRED_ENABLE_AUTH = 200711,\n\tWIRED_VERIFY_REPEATER = 200712,\n\tWIRED_REPEATER_AUTH_STREAM_REQ = 200713,\n\tWIRED_CLOSE_SESSION = 200714,\n\t_WIRED_COMMANDS_COUNT = 200715,\n};\n\nenum hdcp_ddi {\n\tHDCP_DDI_INVALID_PORT = 0,\n\tHDCP_DDI_B = 1,\n\tHDCP_DDI_C = 2,\n\tHDCP_DDI_D = 3,\n\tHDCP_DDI_E = 4,\n\tHDCP_DDI_F = 5,\n\tHDCP_DDI_A = 7,\n\tHDCP_DDI_RANGE_END = 7,\n};\n\nenum hdcp_port_type {\n\tHDCP_PORT_TYPE_INVALID = 0,\n\tHDCP_PORT_TYPE_INTEGRATED = 1,\n\tHDCP_PORT_TYPE_LSPCON = 2,\n\tHDCP_PORT_TYPE_CPDP = 3,\n};\n\nenum hdcp_transcoder {\n\tHDCP_INVALID_TRANSCODER = 0,\n\tHDCP_TRANSCODER_EDP = 1,\n\tHDCP_TRANSCODER_DSI0 = 2,\n\tHDCP_TRANSCODER_DSI1 = 3,\n\tHDCP_TRANSCODER_A = 16,\n\tHDCP_TRANSCODER_B = 17,\n\tHDCP_TRANSCODER_C = 18,\n\tHDCP_TRANSCODER_D = 19,\n};\n\nenum hdcp_wired_protocol {\n\tHDCP_PROTOCOL_INVALID = 0,\n\tHDCP_PROTOCOL_HDMI = 1,\n\tHDCP_PROTOCOL_DP = 2,\n};\n\nenum hdmi_3d_structure {\n\tHDMI_3D_STRUCTURE_INVALID = -1,\n\tHDMI_3D_STRUCTURE_FRAME_PACKING = 0,\n\tHDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1,\n\tHDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3,\n\tHDMI_3D_STRUCTURE_L_DEPTH = 4,\n\tHDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5,\n\tHDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8,\n};\n\nenum hdmi_active_aspect {\n\tHDMI_ACTIVE_ASPECT_16_9_TOP = 2,\n\tHDMI_ACTIVE_ASPECT_14_9_TOP = 3,\n\tHDMI_ACTIVE_ASPECT_16_9_CENTER = 4,\n\tHDMI_ACTIVE_ASPECT_PICTURE = 8,\n\tHDMI_ACTIVE_ASPECT_4_3 = 9,\n\tHDMI_ACTIVE_ASPECT_16_9 = 10,\n\tHDMI_ACTIVE_ASPECT_14_9 = 11,\n\tHDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15,\n};\n\nenum hdmi_audio_coding_type {\n\tHDMI_AUDIO_CODING_TYPE_STREAM = 0,\n\tHDMI_AUDIO_CODING_TYPE_PCM = 1,\n\tHDMI_AUDIO_CODING_TYPE_AC3 = 2,\n\tHDMI_AUDIO_CODING_TYPE_MPEG1 = 3,\n\tHDMI_AUDIO_CODING_TYPE_MP3 = 4,\n\tHDMI_AUDIO_CODING_TYPE_MPEG2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_DTS = 7,\n\tHDMI_AUDIO_CODING_TYPE_ATRAC = 8,\n\tHDMI_AUDIO_CODING_TYPE_DSD = 9,\n\tHDMI_AUDIO_CODING_TYPE_EAC3 = 10,\n\tHDMI_AUDIO_CODING_TYPE_DTS_HD = 11,\n\tHDMI_AUDIO_CODING_TYPE_MLP = 12,\n\tHDMI_AUDIO_CODING_TYPE_DST = 13,\n\tHDMI_AUDIO_CODING_TYPE_WMA_PRO = 14,\n\tHDMI_AUDIO_CODING_TYPE_CXT = 15,\n};\n\nenum hdmi_audio_coding_type_ext {\n\tHDMI_AUDIO_CODING_TYPE_EXT_CT = 0,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_EXT_DRA = 7,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10,\n};\n\nenum hdmi_audio_sample_frequency {\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7,\n};\n\nenum hdmi_audio_sample_size {\n\tHDMI_AUDIO_SAMPLE_SIZE_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_SIZE_16 = 1,\n\tHDMI_AUDIO_SAMPLE_SIZE_20 = 2,\n\tHDMI_AUDIO_SAMPLE_SIZE_24 = 3,\n};\n\nenum hdmi_colorimetry {\n\tHDMI_COLORIMETRY_NONE = 0,\n\tHDMI_COLORIMETRY_ITU_601 = 1,\n\tHDMI_COLORIMETRY_ITU_709 = 2,\n\tHDMI_COLORIMETRY_EXTENDED = 3,\n};\n\nenum hdmi_colorspace {\n\tHDMI_COLORSPACE_RGB = 0,\n\tHDMI_COLORSPACE_YUV422 = 1,\n\tHDMI_COLORSPACE_YUV444 = 2,\n\tHDMI_COLORSPACE_YUV420 = 3,\n\tHDMI_COLORSPACE_RESERVED4 = 4,\n\tHDMI_COLORSPACE_RESERVED5 = 5,\n\tHDMI_COLORSPACE_RESERVED6 = 6,\n\tHDMI_COLORSPACE_IDO_DEFINED = 7,\n};\n\nenum hdmi_content_type {\n\tHDMI_CONTENT_TYPE_GRAPHICS = 0,\n\tHDMI_CONTENT_TYPE_PHOTO = 1,\n\tHDMI_CONTENT_TYPE_CINEMA = 2,\n\tHDMI_CONTENT_TYPE_GAME = 3,\n};\n\nenum hdmi_eotf {\n\tHDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0,\n\tHDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1,\n\tHDMI_EOTF_SMPTE_ST2084 = 2,\n\tHDMI_EOTF_BT_2100_HLG = 3,\n};\n\nenum hdmi_extended_colorimetry {\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0,\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1,\n\tHDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2,\n\tHDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3,\n\tHDMI_EXTENDED_COLORIMETRY_OPRGB = 4,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020 = 6,\n\tHDMI_EXTENDED_COLORIMETRY_RESERVED = 7,\n};\n\nenum hdmi_force_audio {\n\tHDMI_AUDIO_OFF_DVI = -2,\n\tHDMI_AUDIO_OFF = -1,\n\tHDMI_AUDIO_AUTO = 0,\n\tHDMI_AUDIO_ON = 1,\n};\n\nenum hdmi_infoframe_type {\n\tHDMI_INFOFRAME_TYPE_VENDOR = 129,\n\tHDMI_INFOFRAME_TYPE_AVI = 130,\n\tHDMI_INFOFRAME_TYPE_SPD = 131,\n\tHDMI_INFOFRAME_TYPE_AUDIO = 132,\n\tHDMI_INFOFRAME_TYPE_DRM = 135,\n};\n\nenum hdmi_metadata_type {\n\tHDMI_STATIC_METADATA_TYPE1 = 0,\n};\n\nenum hdmi_nups {\n\tHDMI_NUPS_UNKNOWN = 0,\n\tHDMI_NUPS_HORIZONTAL = 1,\n\tHDMI_NUPS_VERTICAL = 2,\n\tHDMI_NUPS_BOTH = 3,\n};\n\nenum hdmi_packet_type {\n\tHDMI_PACKET_TYPE_NULL = 0,\n\tHDMI_PACKET_TYPE_AUDIO_CLOCK_REGEN = 1,\n\tHDMI_PACKET_TYPE_AUDIO_SAMPLE = 2,\n\tHDMI_PACKET_TYPE_GENERAL_CONTROL = 3,\n\tHDMI_PACKET_TYPE_ACP = 4,\n\tHDMI_PACKET_TYPE_ISRC1 = 5,\n\tHDMI_PACKET_TYPE_ISRC2 = 6,\n\tHDMI_PACKET_TYPE_ONE_BIT_AUDIO_SAMPLE = 7,\n\tHDMI_PACKET_TYPE_DST_AUDIO = 8,\n\tHDMI_PACKET_TYPE_HBR_AUDIO_STREAM = 9,\n\tHDMI_PACKET_TYPE_GAMUT_METADATA = 10,\n};\n\nenum hdmi_picture_aspect {\n\tHDMI_PICTURE_ASPECT_NONE = 0,\n\tHDMI_PICTURE_ASPECT_4_3 = 1,\n\tHDMI_PICTURE_ASPECT_16_9 = 2,\n\tHDMI_PICTURE_ASPECT_64_27 = 3,\n\tHDMI_PICTURE_ASPECT_256_135 = 4,\n\tHDMI_PICTURE_ASPECT_RESERVED = 5,\n};\n\nenum hdmi_quantization_range {\n\tHDMI_QUANTIZATION_RANGE_DEFAULT = 0,\n\tHDMI_QUANTIZATION_RANGE_LIMITED = 1,\n\tHDMI_QUANTIZATION_RANGE_FULL = 2,\n\tHDMI_QUANTIZATION_RANGE_RESERVED = 3,\n};\n\nenum hdmi_scan_mode {\n\tHDMI_SCAN_MODE_NONE = 0,\n\tHDMI_SCAN_MODE_OVERSCAN = 1,\n\tHDMI_SCAN_MODE_UNDERSCAN = 2,\n\tHDMI_SCAN_MODE_RESERVED = 3,\n};\n\nenum hdmi_spd_sdi {\n\tHDMI_SPD_SDI_UNKNOWN = 0,\n\tHDMI_SPD_SDI_DSTB = 1,\n\tHDMI_SPD_SDI_DVDP = 2,\n\tHDMI_SPD_SDI_DVHS = 3,\n\tHDMI_SPD_SDI_HDDVR = 4,\n\tHDMI_SPD_SDI_DVC = 5,\n\tHDMI_SPD_SDI_DSC = 6,\n\tHDMI_SPD_SDI_VCD = 7,\n\tHDMI_SPD_SDI_GAME = 8,\n\tHDMI_SPD_SDI_PC = 9,\n\tHDMI_SPD_SDI_BD = 10,\n\tHDMI_SPD_SDI_SACD = 11,\n\tHDMI_SPD_SDI_HDDVD = 12,\n\tHDMI_SPD_SDI_PMP = 13,\n};\n\nenum hdmi_ycc_quantization_range {\n\tHDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0,\n\tHDMI_YCC_QUANTIZATION_RANGE_FULL = 1,\n};\n\nenum hid_class_request {\n\tHID_REQ_GET_REPORT = 1,\n\tHID_REQ_GET_IDLE = 2,\n\tHID_REQ_GET_PROTOCOL = 3,\n\tHID_REQ_SET_REPORT = 9,\n\tHID_REQ_SET_IDLE = 10,\n\tHID_REQ_SET_PROTOCOL = 11,\n};\n\nenum hid_report_type {\n\tHID_INPUT_REPORT = 0,\n\tHID_OUTPUT_REPORT = 1,\n\tHID_FEATURE_REPORT = 2,\n\tHID_REPORT_TYPES = 3,\n};\n\nenum hid_type {\n\tHID_TYPE_OTHER = 0,\n\tHID_TYPE_USBMOUSE = 1,\n\tHID_TYPE_USBNONE = 2,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hn_flags_bits {\n\tHANDSHAKE_F_NET_DRAINING = 0,\n};\n\nenum hp_flags_bits {\n\tHANDSHAKE_F_PROTO_NOTIFY = 0,\n};\n\nenum hpd_pin {\n\tHPD_NONE = 0,\n\tHPD_TV = 0,\n\tHPD_CRT = 1,\n\tHPD_SDVO_B = 2,\n\tHPD_SDVO_C = 3,\n\tHPD_PORT_A = 4,\n\tHPD_PORT_B = 5,\n\tHPD_PORT_C = 6,\n\tHPD_PORT_D = 7,\n\tHPD_PORT_E = 8,\n\tHPD_PORT_TC1 = 9,\n\tHPD_PORT_TC2 = 10,\n\tHPD_PORT_TC3 = 11,\n\tHPD_PORT_TC4 = 12,\n\tHPD_PORT_TC5 = 13,\n\tHPD_PORT_TC6 = 14,\n\tHPD_NUM_PINS = 15,\n};\n\nenum hpet_mode {\n\tHPET_MODE_UNUSED = 0,\n\tHPET_MODE_LEGACY = 1,\n\tHPET_MODE_CLOCKEVT = 2,\n\tHPET_MODE_DEVICE = 3,\n};\n\nenum hprobe_state {\n\tHPROBE_LEASED = 0,\n\tHPROBE_STABLE = 1,\n\tHPROBE_GONE = 2,\n\tHPROBE_CONSUMED = 3,\n};\n\nenum hpx_type3_cfg_loc {\n\tHPX_CFG_PCICFG = 0,\n\tHPX_CFG_PCIE_CAP = 1,\n\tHPX_CFG_PCIE_CAP_EXT = 2,\n\tHPX_CFG_VEND_CAP = 3,\n\tHPX_CFG_DVSEC = 4,\n\tHPX_CFG_MAX = 5,\n};\n\nenum hpx_type3_dev_type {\n\tHPX_TYPE_ENDPOINT = 1,\n\tHPX_TYPE_LEG_END = 2,\n\tHPX_TYPE_RC_END = 4,\n\tHPX_TYPE_RC_EC = 8,\n\tHPX_TYPE_ROOT_PORT = 16,\n\tHPX_TYPE_UPSTREAM = 32,\n\tHPX_TYPE_DOWNSTREAM = 64,\n\tHPX_TYPE_PCI_BRIDGE = 128,\n\tHPX_TYPE_PCIE_BRIDGE = 256,\n};\n\nenum hpx_type3_fn_type {\n\tHPX_FN_NORMAL = 1,\n\tHPX_FN_SRIOV_PHYS = 2,\n\tHPX_FN_SRIOV_VIRT = 4,\n};\n\nenum hr_flags_bits {\n\tHANDSHAKE_F_REQ_COMPLETED = 0,\n\tHANDSHAKE_F_REQ_SESSION = 1,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nenum hub_activation_type {\n\tHUB_INIT = 0,\n\tHUB_INIT2 = 1,\n\tHUB_INIT3 = 2,\n\tHUB_POST_RESET = 3,\n\tHUB_RESUME = 4,\n\tHUB_RESET_RESUME = 5,\n};\n\nenum hub_led_mode {\n\tINDICATOR_AUTO = 0,\n\tINDICATOR_CYCLE = 1,\n\tINDICATOR_GREEN_BLINK = 2,\n\tINDICATOR_GREEN_BLINK_OFF = 3,\n\tINDICATOR_AMBER_BLINK = 4,\n\tINDICATOR_AMBER_BLINK_OFF = 5,\n\tINDICATOR_ALT_BLINK = 6,\n\tINDICATOR_ALT_BLINK_OFF = 7,\n} __attribute__((mode(byte)));\n\nenum hub_quiescing_type {\n\tHUB_DISCONNECT = 0,\n\tHUB_PRE_RESET = 1,\n\tHUB_SUSPEND = 2,\n};\n\nenum hugetlb_memory_event {\n\tHUGETLB_MAX = 0,\n\tHUGETLB_NR_MEMORY_EVENTS = 1,\n};\n\nenum hugetlb_page_flags {\n\tHPG_restore_reserve = 0,\n\tHPG_migratable = 1,\n\tHPG_temporary = 2,\n\tHPG_freed = 3,\n\tHPG_vmemmap_optimized = 4,\n\tHPG_raw_hwp_unreliable = 5,\n\tHPG_cma = 6,\n\t__NR_HPAGEFLAGS = 7,\n};\n\nenum hugetlb_param {\n\tOpt_gid___7 = 0,\n\tOpt_min_size = 1,\n\tOpt_mode___5 = 2,\n\tOpt_nr_inodes = 3,\n\tOpt_pagesize = 4,\n\tOpt_size = 5,\n\tOpt_uid___7 = 6,\n};\n\nenum hugetlbfs_size_type {\n\tNO_SIZE = 0,\n\tSIZE_STD = 1,\n\tSIZE_PERCENT = 2,\n};\n\nenum hv_isolation_type {\n\tHV_ISOLATION_TYPE_NONE = 0,\n\tHV_ISOLATION_TYPE_VBS = 1,\n\tHV_ISOLATION_TYPE_SNP = 2,\n\tHV_ISOLATION_TYPE_TDX = 3,\n};\n\nenum hv_tlb_flush_fifos {\n\tHV_L1_TLB_FLUSH_FIFO = 0,\n\tHV_L2_TLB_FLUSH_FIFO = 1,\n\tHV_NR_TLB_FLUSH_FIFOS = 2,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwerr_error_type {\n\tHWERR_RECOV_CPU = 0,\n\tHWERR_RECOV_MEMORY = 1,\n\tHWERR_RECOV_PCI = 2,\n\tHWERR_RECOV_CXL = 3,\n\tHWERR_RECOV_OTHERS = 4,\n\tHWERR_RECOV_MAX = 5,\n};\n\nenum hwmon_chip_attributes {\n\thwmon_chip_temp_reset_history = 0,\n\thwmon_chip_in_reset_history = 1,\n\thwmon_chip_curr_reset_history = 2,\n\thwmon_chip_power_reset_history = 3,\n\thwmon_chip_register_tz = 4,\n\thwmon_chip_update_interval = 5,\n\thwmon_chip_alarms = 6,\n\thwmon_chip_samples = 7,\n\thwmon_chip_curr_samples = 8,\n\thwmon_chip_in_samples = 9,\n\thwmon_chip_power_samples = 10,\n\thwmon_chip_temp_samples = 11,\n\thwmon_chip_beep_enable = 12,\n\thwmon_chip_pec = 13,\n};\n\nenum hwmon_curr_attributes {\n\thwmon_curr_enable = 0,\n\thwmon_curr_input = 1,\n\thwmon_curr_min = 2,\n\thwmon_curr_max = 3,\n\thwmon_curr_lcrit = 4,\n\thwmon_curr_crit = 5,\n\thwmon_curr_average = 6,\n\thwmon_curr_lowest = 7,\n\thwmon_curr_highest = 8,\n\thwmon_curr_reset_history = 9,\n\thwmon_curr_label = 10,\n\thwmon_curr_alarm = 11,\n\thwmon_curr_min_alarm = 12,\n\thwmon_curr_max_alarm = 13,\n\thwmon_curr_lcrit_alarm = 14,\n\thwmon_curr_crit_alarm = 15,\n\thwmon_curr_rated_min = 16,\n\thwmon_curr_rated_max = 17,\n\thwmon_curr_beep = 18,\n};\n\nenum hwmon_energy_attributes {\n\thwmon_energy_enable = 0,\n\thwmon_energy_input = 1,\n\thwmon_energy_label = 2,\n};\n\nenum hwmon_fan_attributes {\n\thwmon_fan_enable = 0,\n\thwmon_fan_input = 1,\n\thwmon_fan_label = 2,\n\thwmon_fan_min = 3,\n\thwmon_fan_max = 4,\n\thwmon_fan_div = 5,\n\thwmon_fan_pulses = 6,\n\thwmon_fan_target = 7,\n\thwmon_fan_alarm = 8,\n\thwmon_fan_min_alarm = 9,\n\thwmon_fan_max_alarm = 10,\n\thwmon_fan_fault = 11,\n\thwmon_fan_beep = 12,\n};\n\nenum hwmon_humidity_attributes {\n\thwmon_humidity_enable = 0,\n\thwmon_humidity_input = 1,\n\thwmon_humidity_label = 2,\n\thwmon_humidity_min = 3,\n\thwmon_humidity_min_hyst = 4,\n\thwmon_humidity_max = 5,\n\thwmon_humidity_max_hyst = 6,\n\thwmon_humidity_alarm = 7,\n\thwmon_humidity_fault = 8,\n\thwmon_humidity_rated_min = 9,\n\thwmon_humidity_rated_max = 10,\n\thwmon_humidity_min_alarm = 11,\n\thwmon_humidity_max_alarm = 12,\n};\n\nenum hwmon_in_attributes {\n\thwmon_in_enable = 0,\n\thwmon_in_input = 1,\n\thwmon_in_min = 2,\n\thwmon_in_max = 3,\n\thwmon_in_lcrit = 4,\n\thwmon_in_crit = 5,\n\thwmon_in_average = 6,\n\thwmon_in_lowest = 7,\n\thwmon_in_highest = 8,\n\thwmon_in_reset_history = 9,\n\thwmon_in_label = 10,\n\thwmon_in_alarm = 11,\n\thwmon_in_min_alarm = 12,\n\thwmon_in_max_alarm = 13,\n\thwmon_in_lcrit_alarm = 14,\n\thwmon_in_crit_alarm = 15,\n\thwmon_in_rated_min = 16,\n\thwmon_in_rated_max = 17,\n\thwmon_in_beep = 18,\n\thwmon_in_fault = 19,\n};\n\nenum hwmon_intrusion_attributes {\n\thwmon_intrusion_alarm = 0,\n\thwmon_intrusion_beep = 1,\n};\n\nenum hwmon_power_attributes {\n\thwmon_power_enable = 0,\n\thwmon_power_average = 1,\n\thwmon_power_average_interval = 2,\n\thwmon_power_average_interval_max = 3,\n\thwmon_power_average_interval_min = 4,\n\thwmon_power_average_highest = 5,\n\thwmon_power_average_lowest = 6,\n\thwmon_power_average_max = 7,\n\thwmon_power_average_min = 8,\n\thwmon_power_input = 9,\n\thwmon_power_input_highest = 10,\n\thwmon_power_input_lowest = 11,\n\thwmon_power_reset_history = 12,\n\thwmon_power_accuracy = 13,\n\thwmon_power_cap = 14,\n\thwmon_power_cap_hyst = 15,\n\thwmon_power_cap_max = 16,\n\thwmon_power_cap_min = 17,\n\thwmon_power_min = 18,\n\thwmon_power_max = 19,\n\thwmon_power_crit = 20,\n\thwmon_power_lcrit = 21,\n\thwmon_power_label = 22,\n\thwmon_power_alarm = 23,\n\thwmon_power_cap_alarm = 24,\n\thwmon_power_min_alarm = 25,\n\thwmon_power_max_alarm = 26,\n\thwmon_power_lcrit_alarm = 27,\n\thwmon_power_crit_alarm = 28,\n\thwmon_power_rated_min = 29,\n\thwmon_power_rated_max = 30,\n};\n\nenum hwmon_pwm_attributes {\n\thwmon_pwm_input = 0,\n\thwmon_pwm_enable = 1,\n\thwmon_pwm_mode = 2,\n\thwmon_pwm_freq = 3,\n\thwmon_pwm_auto_channels_temp = 4,\n};\n\nenum hwmon_sensor_types {\n\thwmon_chip = 0,\n\thwmon_temp = 1,\n\thwmon_in = 2,\n\thwmon_curr = 3,\n\thwmon_power = 4,\n\thwmon_energy = 5,\n\thwmon_energy64 = 6,\n\thwmon_humidity = 7,\n\thwmon_fan = 8,\n\thwmon_pwm = 9,\n\thwmon_intrusion = 10,\n\thwmon_max = 11,\n};\n\nenum hwmon_temp_attributes {\n\thwmon_temp_enable = 0,\n\thwmon_temp_input = 1,\n\thwmon_temp_type = 2,\n\thwmon_temp_lcrit = 3,\n\thwmon_temp_lcrit_hyst = 4,\n\thwmon_temp_min = 5,\n\thwmon_temp_min_hyst = 6,\n\thwmon_temp_max = 7,\n\thwmon_temp_max_hyst = 8,\n\thwmon_temp_crit = 9,\n\thwmon_temp_crit_hyst = 10,\n\thwmon_temp_emergency = 11,\n\thwmon_temp_emergency_hyst = 12,\n\thwmon_temp_alarm = 13,\n\thwmon_temp_lcrit_alarm = 14,\n\thwmon_temp_min_alarm = 15,\n\thwmon_temp_max_alarm = 16,\n\thwmon_temp_crit_alarm = 17,\n\thwmon_temp_emergency_alarm = 18,\n\thwmon_temp_fault = 19,\n\thwmon_temp_offset = 20,\n\thwmon_temp_label = 21,\n\thwmon_temp_lowest = 22,\n\thwmon_temp_highest = 23,\n\thwmon_temp_reset_history = 24,\n\thwmon_temp_rated_min = 25,\n\thwmon_temp_rated_max = 26,\n\thwmon_temp_beep = 27,\n};\n\nenum hwp_cpufreq_attr_index {\n\tHWP_BASE_FREQUENCY_INDEX = 0,\n\tHWP_PERFORMANCE_PREFERENCE_INDEX = 1,\n\tHWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX = 2,\n\tHWP_CPUFREQ_ATTR_COUNT = 3,\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum hybrid_pmu_type {\n\tnot_hybrid = 0,\n\thybrid_small = 1,\n\thybrid_big = 2,\n\thybrid_tiny = 4,\n\thybrid_big_small = 3,\n\thybrid_small_tiny = 5,\n\thybrid_big_small_tiny = 7,\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nenum i2c_driver_flags {\n\tI2C_DRV_ACPI_WAIVE_D0_PROBE = 1,\n};\n\nenum i8042_controller_reset_mode {\n\tI8042_RESET_NEVER = 0,\n\tI8042_RESET_ALWAYS = 1,\n\tI8042_RESET_ON_S2RAM = 2,\n};\n\nenum i915_cache_level {\n\tI915_CACHE_NONE = 0,\n\tI915_CACHE_LLC = 1,\n\tI915_CACHE_L3_LLC = 2,\n\tI915_CACHE_WT = 3,\n\tI915_MAX_CACHE_LEVEL = 4,\n};\n\nenum i915_component_type {\n\tI915_COMPONENT_AUDIO = 1,\n\tI915_COMPONENT_HDCP = 2,\n\tI915_COMPONENT_PXP = 3,\n\tI915_COMPONENT_GSC_PROXY = 4,\n\tINTEL_COMPONENT_LB = 5,\n};\n\nenum i915_gem_engine_type {\n\tI915_GEM_ENGINE_TYPE_INVALID = 0,\n\tI915_GEM_ENGINE_TYPE_PHYSICAL = 1,\n\tI915_GEM_ENGINE_TYPE_BALANCED = 2,\n\tI915_GEM_ENGINE_TYPE_PARALLEL = 3,\n};\n\nenum i915_gtt_view_type {\n\tI915_GTT_VIEW_NORMAL = 0,\n\tI915_GTT_VIEW_ROTATED = 24,\n\tI915_GTT_VIEW_PARTIAL = 12,\n\tI915_GTT_VIEW_REMAPPED = 52,\n};\n\nenum i915_map_type {\n\tI915_MAP_WB = 0,\n\tI915_MAP_WC = 1,\n\tI915_MAP_FORCE_WB = 2147483648,\n\tI915_MAP_FORCE_WC = 2147483649,\n};\n\nenum i915_mmap_type {\n\tI915_MMAP_TYPE_GTT = 0,\n\tI915_MMAP_TYPE_WC = 1,\n\tI915_MMAP_TYPE_WB = 2,\n\tI915_MMAP_TYPE_UC = 3,\n\tI915_MMAP_TYPE_FIXED = 4,\n};\n\nenum i915_mocs_table_index {\n\tI915_MOCS_UNCACHED = 0,\n\tI915_MOCS_PTE = 1,\n\tI915_MOCS_CACHED = 2,\n};\n\nenum i915_pmu_tracked_events {\n\t__I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0,\n\t__I915_PMU_REQUESTED_FREQUENCY_ENABLED = 1,\n\t__I915_PMU_RC6_RESIDENCY_ENABLED = 2,\n\t__I915_PMU_TRACKED_EVENT_COUNT = 3,\n};\n\nenum i915_power_well_id {\n\tDISP_PW_ID_NONE = 0,\n\tVLV_DISP_PW_DISP2D = 1,\n\tBXT_DISP_PW_DPIO_CMN_A = 2,\n\tVLV_DISP_PW_DPIO_CMN_BC = 3,\n\tGLK_DISP_PW_DPIO_CMN_C = 4,\n\tCHV_DISP_PW_DPIO_CMN_D = 5,\n\tHSW_DISP_PW_GLOBAL = 6,\n\tSKL_DISP_PW_MISC_IO = 7,\n\tSKL_DISP_PW_1 = 8,\n\tSKL_DISP_PW_2 = 9,\n\tICL_DISP_PW_3 = 10,\n\tSKL_DISP_DC_OFF = 11,\n\tTGL_DISP_PW_TC_COLD_OFF = 12,\n};\n\nenum i915_request_state {\n\tI915_REQUEST_UNKNOWN = 0,\n\tI915_REQUEST_COMPLETE = 1,\n\tI915_REQUEST_PENDING = 2,\n\tI915_REQUEST_QUEUED = 3,\n\tI915_REQUEST_ACTIVE = 4,\n};\n\nenum i915_sw_fence_notify {\n\tFENCE_COMPLETE = 0,\n\tFENCE_FREE = 1,\n};\n\nenum i9xx_plane_id {\n\tPLANE_A = 0,\n\tPLANE_B = 1,\n\tPLANE_C = 2,\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_FLUSH_GLOBAL = 256,\n\tIB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_device_cap_flags {\n\tIB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL,\n\tIB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL,\n\tIB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL,\n\tIB_UVERBS_DEVICE_RAW_MULTI = 8ULL,\n\tIB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL,\n\tIB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL,\n\tIB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL,\n\tIB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL,\n\tIB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL,\n\tIB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL,\n\tIB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL,\n\tIB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL,\n\tIB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL,\n\tIB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL,\n\tIB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL,\n\tIB_UVERBS_DEVICE_XRC = 1048576ULL,\n\tIB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL,\n\tIB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL,\n\tIB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL,\n\tIB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL,\n\tIB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL,\n\tIB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL,\n\tIB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL,\n\tIB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL,\n\tIB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL,\n};\n\nenum ib_uverbs_gid_type {\n\tIB_UVERBS_GID_TYPE_IB = 0,\n\tIB_UVERBS_GID_TYPE_ROCE_V1 = 1,\n\tIB_UVERBS_GID_TYPE_ROCE_V2 = 2,\n};\n\nenum ib_uverbs_odp_general_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT = 1,\n\tIB_UVERBS_ODP_SUPPORT_IMPLICIT = 2,\n};\n\nenum ib_uverbs_odp_transport_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT_SEND = 1,\n\tIB_UVERBS_ODP_SUPPORT_RECV = 2,\n\tIB_UVERBS_ODP_SUPPORT_WRITE = 4,\n\tIB_UVERBS_ODP_SUPPORT_READ = 8,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC = 16,\n\tIB_UVERBS_ODP_SUPPORT_SRQ_RECV = 32,\n\tIB_UVERBS_ODP_SUPPORT_FLUSH = 64,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 128,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_raw_packet_caps {\n\tIB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2,\n\tIB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4,\n\tIB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wc_opcode {\n\tIB_UVERBS_WC_SEND = 0,\n\tIB_UVERBS_WC_RDMA_WRITE = 1,\n\tIB_UVERBS_WC_RDMA_READ = 2,\n\tIB_UVERBS_WC_COMP_SWAP = 3,\n\tIB_UVERBS_WC_FETCH_ADD = 4,\n\tIB_UVERBS_WC_BIND_MW = 5,\n\tIB_UVERBS_WC_LOCAL_INV = 6,\n\tIB_UVERBS_WC_TSO = 7,\n\tIB_UVERBS_WC_FLUSH = 8,\n\tIB_UVERBS_WC_ATOMIC_WRITE = 9,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_UVERBS_WR_FLUSH = 14,\n\tIB_UVERBS_WR_ATOMIC_WRITE = 15,\n};\n\nenum ibs_states {\n\tIBS_ENABLED = 0,\n\tIBS_STARTED = 1,\n\tIBS_STOPPING = 2,\n\tIBS_STOPPED = 3,\n\tIBS_MAX_STATES = 4,\n};\n\nenum icl_port_dpll_id {\n\tICL_PORT_DPLL_DEFAULT = 0,\n\tICL_PORT_DPLL_MG_PHY = 1,\n\tICL_PORT_DPLL_COUNT = 2,\n};\n\nenum idle_boot_override {\n\tIDLE_NO_OVERRIDE = 0,\n\tIDLE_HALT = 1,\n\tIDLE_NOMWAIT = 2,\n\tIDLE_POLL = 3,\n};\n\nenum ieee80211_ac_numbers {\n\tIEEE80211_AC_VO = 0,\n\tIEEE80211_AC_VI = 1,\n\tIEEE80211_AC_BE = 2,\n\tIEEE80211_AC_BK = 3,\n};\n\nenum ieee80211_agg_stop_reason {\n\tAGG_STOP_DECLINED = 0,\n\tAGG_STOP_LOCAL_REQUEST = 1,\n\tAGG_STOP_PEER_REQUEST = 2,\n\tAGG_STOP_DESTROY_STA = 3,\n};\n\nenum ieee80211_ampdu_mlme_action {\n\tIEEE80211_AMPDU_RX_START = 0,\n\tIEEE80211_AMPDU_RX_STOP = 1,\n\tIEEE80211_AMPDU_TX_START = 2,\n\tIEEE80211_AMPDU_TX_STOP_CONT = 3,\n\tIEEE80211_AMPDU_TX_STOP_FLUSH = 4,\n\tIEEE80211_AMPDU_TX_STOP_FLUSH_CONT = 5,\n\tIEEE80211_AMPDU_TX_OPERATIONAL = 6,\n};\n\nenum ieee80211_ap_reg_power {\n\tIEEE80211_REG_UNSET_AP = 0,\n\tIEEE80211_REG_LPI_AP = 1,\n\tIEEE80211_REG_SP_AP = 2,\n\tIEEE80211_REG_VLP_AP = 3,\n};\n\nenum ieee80211_back_actioncode {\n\tWLAN_ACTION_ADDBA_REQ = 0,\n\tWLAN_ACTION_ADDBA_RESP = 1,\n\tWLAN_ACTION_DELBA = 2,\n};\n\nenum ieee80211_back_parties {\n\tWLAN_BACK_RECIPIENT = 0,\n\tWLAN_BACK_INITIATOR = 1,\n};\n\nenum ieee80211_bss_change {\n\tBSS_CHANGED_ASSOC = 1ULL,\n\tBSS_CHANGED_ERP_CTS_PROT = 2ULL,\n\tBSS_CHANGED_ERP_PREAMBLE = 4ULL,\n\tBSS_CHANGED_ERP_SLOT = 8ULL,\n\tBSS_CHANGED_HT = 16ULL,\n\tBSS_CHANGED_BASIC_RATES = 32ULL,\n\tBSS_CHANGED_BEACON_INT = 64ULL,\n\tBSS_CHANGED_BSSID = 128ULL,\n\tBSS_CHANGED_BEACON = 256ULL,\n\tBSS_CHANGED_BEACON_ENABLED = 512ULL,\n\tBSS_CHANGED_CQM = 1024ULL,\n\tBSS_CHANGED_IBSS = 2048ULL,\n\tBSS_CHANGED_ARP_FILTER = 4096ULL,\n\tBSS_CHANGED_QOS = 8192ULL,\n\tBSS_CHANGED_IDLE = 16384ULL,\n\tBSS_CHANGED_SSID = 32768ULL,\n\tBSS_CHANGED_AP_PROBE_RESP = 65536ULL,\n\tBSS_CHANGED_PS = 131072ULL,\n\tBSS_CHANGED_TXPOWER = 262144ULL,\n\tBSS_CHANGED_P2P_PS = 524288ULL,\n\tBSS_CHANGED_BEACON_INFO = 1048576ULL,\n\tBSS_CHANGED_BANDWIDTH = 2097152ULL,\n\tBSS_CHANGED_OCB = 4194304ULL,\n\tBSS_CHANGED_MU_GROUPS = 8388608ULL,\n\tBSS_CHANGED_KEEP_ALIVE = 16777216ULL,\n\tBSS_CHANGED_MCAST_RATE = 33554432ULL,\n\tBSS_CHANGED_FTM_RESPONDER = 67108864ULL,\n\tBSS_CHANGED_TWT = 134217728ULL,\n\tBSS_CHANGED_HE_OBSS_PD = 268435456ULL,\n\tBSS_CHANGED_HE_BSS_COLOR = 536870912ULL,\n\tBSS_CHANGED_FILS_DISCOVERY = 1073741824ULL,\n\tBSS_CHANGED_UNSOL_BCAST_PROBE_RESP = 2147483648ULL,\n\tBSS_CHANGED_MLD_VALID_LINKS = 8589934592ULL,\n\tBSS_CHANGED_MLD_TTLM = 17179869184ULL,\n\tBSS_CHANGED_TPE = 34359738368ULL,\n};\n\nenum ieee80211_bss_corrupt_data_flags {\n\tIEEE80211_BSS_CORRUPT_BEACON = 1,\n\tIEEE80211_BSS_CORRUPT_PROBE_RESP = 2,\n};\n\nenum ieee80211_bss_type {\n\tIEEE80211_BSS_TYPE_ESS = 0,\n\tIEEE80211_BSS_TYPE_PBSS = 1,\n\tIEEE80211_BSS_TYPE_IBSS = 2,\n\tIEEE80211_BSS_TYPE_MBSS = 3,\n\tIEEE80211_BSS_TYPE_ANY = 4,\n};\n\nenum ieee80211_bss_valid_data_flags {\n\tIEEE80211_BSS_VALID_WMM = 2,\n\tIEEE80211_BSS_VALID_RATES = 4,\n\tIEEE80211_BSS_VALID_ERP = 8,\n};\n\nenum ieee80211_category {\n\tWLAN_CATEGORY_SPECTRUM_MGMT = 0,\n\tWLAN_CATEGORY_QOS = 1,\n\tWLAN_CATEGORY_DLS = 2,\n\tWLAN_CATEGORY_BACK = 3,\n\tWLAN_CATEGORY_PUBLIC = 4,\n\tWLAN_CATEGORY_RADIO_MEASUREMENT = 5,\n\tWLAN_CATEGORY_FAST_BBS_TRANSITION = 6,\n\tWLAN_CATEGORY_HT = 7,\n\tWLAN_CATEGORY_SA_QUERY = 8,\n\tWLAN_CATEGORY_PROTECTED_DUAL_OF_ACTION = 9,\n\tWLAN_CATEGORY_WNM = 10,\n\tWLAN_CATEGORY_WNM_UNPROTECTED = 11,\n\tWLAN_CATEGORY_TDLS = 12,\n\tWLAN_CATEGORY_MESH_ACTION = 13,\n\tWLAN_CATEGORY_MULTIHOP_ACTION = 14,\n\tWLAN_CATEGORY_SELF_PROTECTED = 15,\n\tWLAN_CATEGORY_DMG = 16,\n\tWLAN_CATEGORY_WMM = 17,\n\tWLAN_CATEGORY_FST = 18,\n\tWLAN_CATEGORY_UNPROT_DMG = 20,\n\tWLAN_CATEGORY_VHT = 21,\n\tWLAN_CATEGORY_S1G = 22,\n\tWLAN_CATEGORY_PROTECTED_EHT = 37,\n\tWLAN_CATEGORY_VENDOR_SPECIFIC_PROTECTED = 126,\n\tWLAN_CATEGORY_VENDOR_SPECIFIC = 127,\n};\n\nenum ieee80211_chanctx_change {\n\tIEEE80211_CHANCTX_CHANGE_WIDTH = 1,\n\tIEEE80211_CHANCTX_CHANGE_RX_CHAINS = 2,\n\tIEEE80211_CHANCTX_CHANGE_RADAR = 4,\n\tIEEE80211_CHANCTX_CHANGE_CHANNEL = 8,\n\tIEEE80211_CHANCTX_CHANGE_MIN_DEF = 16,\n\tIEEE80211_CHANCTX_CHANGE_AP = 32,\n\tIEEE80211_CHANCTX_CHANGE_PUNCTURING = 64,\n};\n\nenum ieee80211_chanctx_iter_type {\n\tCHANCTX_ITER_ALL = 0,\n\tCHANCTX_ITER_RESERVED = 1,\n\tCHANCTX_ITER_ASSIGNED = 2,\n};\n\nenum ieee80211_chanctx_mode {\n\tIEEE80211_CHANCTX_SHARED = 0,\n\tIEEE80211_CHANCTX_EXCLUSIVE = 1,\n};\n\nenum ieee80211_chanctx_replace_state {\n\tIEEE80211_CHANCTX_REPLACE_NONE = 0,\n\tIEEE80211_CHANCTX_WILL_BE_REPLACED = 1,\n\tIEEE80211_CHANCTX_REPLACES_OTHER = 2,\n};\n\nenum ieee80211_chanctx_switch_mode {\n\tCHANCTX_SWMODE_REASSIGN_VIF = 0,\n\tCHANCTX_SWMODE_SWAP_CONTEXTS = 1,\n};\n\nenum ieee80211_channel_flags {\n\tIEEE80211_CHAN_DISABLED = 1,\n\tIEEE80211_CHAN_NO_IR = 2,\n\tIEEE80211_CHAN_PSD = 4,\n\tIEEE80211_CHAN_RADAR = 8,\n\tIEEE80211_CHAN_NO_HT40PLUS = 16,\n\tIEEE80211_CHAN_NO_HT40MINUS = 32,\n\tIEEE80211_CHAN_NO_OFDM = 64,\n\tIEEE80211_CHAN_NO_80MHZ = 128,\n\tIEEE80211_CHAN_NO_160MHZ = 256,\n\tIEEE80211_CHAN_INDOOR_ONLY = 512,\n\tIEEE80211_CHAN_IR_CONCURRENT = 1024,\n\tIEEE80211_CHAN_NO_20MHZ = 2048,\n\tIEEE80211_CHAN_NO_10MHZ = 4096,\n\tIEEE80211_CHAN_NO_HE = 8192,\n\tIEEE80211_CHAN_NO_UHR = 262144,\n\tIEEE80211_CHAN_NO_320MHZ = 524288,\n\tIEEE80211_CHAN_NO_EHT = 1048576,\n\tIEEE80211_CHAN_DFS_CONCURRENT = 2097152,\n\tIEEE80211_CHAN_NO_6GHZ_VLP_CLIENT = 4194304,\n\tIEEE80211_CHAN_NO_6GHZ_AFC_CLIENT = 8388608,\n\tIEEE80211_CHAN_CAN_MONITOR = 16777216,\n\tIEEE80211_CHAN_ALLOW_6GHZ_VLP_AP = 33554432,\n\tIEEE80211_CHAN_ALLOW_20MHZ_ACTIVITY = 67108864,\n\tIEEE80211_CHAN_S1G_NO_PRIMARY = 134217728,\n\tIEEE80211_CHAN_NO_4MHZ = 268435456,\n\tIEEE80211_CHAN_NO_8MHZ = 536870912,\n\tIEEE80211_CHAN_NO_16MHZ = 1073741824,\n};\n\nenum ieee80211_conf_changed {\n\tIEEE80211_CONF_CHANGE_SMPS = 2,\n\tIEEE80211_CONF_CHANGE_LISTEN_INTERVAL = 4,\n\tIEEE80211_CONF_CHANGE_MONITOR = 8,\n\tIEEE80211_CONF_CHANGE_PS = 16,\n\tIEEE80211_CONF_CHANGE_POWER = 32,\n\tIEEE80211_CONF_CHANGE_CHANNEL = 64,\n\tIEEE80211_CONF_CHANGE_RETRY_LIMITS = 128,\n\tIEEE80211_CONF_CHANGE_IDLE = 256,\n};\n\nenum ieee80211_conf_flags {\n\tIEEE80211_CONF_MONITOR = 1,\n\tIEEE80211_CONF_PS = 2,\n\tIEEE80211_CONF_IDLE = 4,\n\tIEEE80211_CONF_OFFCHANNEL = 8,\n};\n\nenum ieee80211_conn_bw_limit {\n\tIEEE80211_CONN_BW_LIMIT_20 = 0,\n\tIEEE80211_CONN_BW_LIMIT_40 = 1,\n\tIEEE80211_CONN_BW_LIMIT_80 = 2,\n\tIEEE80211_CONN_BW_LIMIT_160 = 3,\n\tIEEE80211_CONN_BW_LIMIT_320 = 4,\n};\n\nenum ieee80211_conn_mode {\n\tIEEE80211_CONN_MODE_S1G = 0,\n\tIEEE80211_CONN_MODE_LEGACY = 1,\n\tIEEE80211_CONN_MODE_HT = 2,\n\tIEEE80211_CONN_MODE_VHT = 3,\n\tIEEE80211_CONN_MODE_HE = 4,\n\tIEEE80211_CONN_MODE_EHT = 5,\n\tIEEE80211_CONN_MODE_UHR = 6,\n};\n\nenum ieee80211_csa_source {\n\tIEEE80211_CSA_SOURCE_BEACON = 0,\n\tIEEE80211_CSA_SOURCE_OTHER_LINK = 1,\n\tIEEE80211_CSA_SOURCE_PROT_ACTION = 2,\n\tIEEE80211_CSA_SOURCE_UNPROT_ACTION = 3,\n};\n\nenum ieee80211_edmg_bw_config {\n\tIEEE80211_EDMG_BW_CONFIG_4 = 4,\n\tIEEE80211_EDMG_BW_CONFIG_5 = 5,\n\tIEEE80211_EDMG_BW_CONFIG_6 = 6,\n\tIEEE80211_EDMG_BW_CONFIG_7 = 7,\n\tIEEE80211_EDMG_BW_CONFIG_8 = 8,\n\tIEEE80211_EDMG_BW_CONFIG_9 = 9,\n\tIEEE80211_EDMG_BW_CONFIG_10 = 10,\n\tIEEE80211_EDMG_BW_CONFIG_11 = 11,\n\tIEEE80211_EDMG_BW_CONFIG_12 = 12,\n\tIEEE80211_EDMG_BW_CONFIG_13 = 13,\n\tIEEE80211_EDMG_BW_CONFIG_14 = 14,\n\tIEEE80211_EDMG_BW_CONFIG_15 = 15,\n};\n\nenum ieee80211_eid {\n\tWLAN_EID_SSID = 0,\n\tWLAN_EID_SUPP_RATES = 1,\n\tWLAN_EID_FH_PARAMS = 2,\n\tWLAN_EID_DS_PARAMS = 3,\n\tWLAN_EID_CF_PARAMS = 4,\n\tWLAN_EID_TIM = 5,\n\tWLAN_EID_IBSS_PARAMS = 6,\n\tWLAN_EID_COUNTRY = 7,\n\tWLAN_EID_REQUEST = 10,\n\tWLAN_EID_QBSS_LOAD = 11,\n\tWLAN_EID_EDCA_PARAM_SET = 12,\n\tWLAN_EID_TSPEC = 13,\n\tWLAN_EID_TCLAS = 14,\n\tWLAN_EID_SCHEDULE = 15,\n\tWLAN_EID_CHALLENGE = 16,\n\tWLAN_EID_PWR_CONSTRAINT = 32,\n\tWLAN_EID_PWR_CAPABILITY = 33,\n\tWLAN_EID_TPC_REQUEST = 34,\n\tWLAN_EID_TPC_REPORT = 35,\n\tWLAN_EID_SUPPORTED_CHANNELS = 36,\n\tWLAN_EID_CHANNEL_SWITCH = 37,\n\tWLAN_EID_MEASURE_REQUEST = 38,\n\tWLAN_EID_MEASURE_REPORT = 39,\n\tWLAN_EID_QUIET = 40,\n\tWLAN_EID_IBSS_DFS = 41,\n\tWLAN_EID_ERP_INFO = 42,\n\tWLAN_EID_TS_DELAY = 43,\n\tWLAN_EID_TCLAS_PROCESSING = 44,\n\tWLAN_EID_HT_CAPABILITY = 45,\n\tWLAN_EID_QOS_CAPA = 46,\n\tWLAN_EID_RSN = 48,\n\tWLAN_EID_802_15_COEX = 49,\n\tWLAN_EID_EXT_SUPP_RATES = 50,\n\tWLAN_EID_AP_CHAN_REPORT = 51,\n\tWLAN_EID_NEIGHBOR_REPORT = 52,\n\tWLAN_EID_RCPI = 53,\n\tWLAN_EID_MOBILITY_DOMAIN = 54,\n\tWLAN_EID_FAST_BSS_TRANSITION = 55,\n\tWLAN_EID_TIMEOUT_INTERVAL = 56,\n\tWLAN_EID_RIC_DATA = 57,\n\tWLAN_EID_DSE_REGISTERED_LOCATION = 58,\n\tWLAN_EID_SUPPORTED_REGULATORY_CLASSES = 59,\n\tWLAN_EID_EXT_CHANSWITCH_ANN = 60,\n\tWLAN_EID_HT_OPERATION = 61,\n\tWLAN_EID_SECONDARY_CHANNEL_OFFSET = 62,\n\tWLAN_EID_BSS_AVG_ACCESS_DELAY = 63,\n\tWLAN_EID_ANTENNA_INFO = 64,\n\tWLAN_EID_RSNI = 65,\n\tWLAN_EID_MEASUREMENT_PILOT_TX_INFO = 66,\n\tWLAN_EID_BSS_AVAILABLE_CAPACITY = 67,\n\tWLAN_EID_BSS_AC_ACCESS_DELAY = 68,\n\tWLAN_EID_TIME_ADVERTISEMENT = 69,\n\tWLAN_EID_RRM_ENABLED_CAPABILITIES = 70,\n\tWLAN_EID_MULTIPLE_BSSID = 71,\n\tWLAN_EID_BSS_COEX_2040 = 72,\n\tWLAN_EID_BSS_INTOLERANT_CHL_REPORT = 73,\n\tWLAN_EID_OVERLAP_BSS_SCAN_PARAM = 74,\n\tWLAN_EID_RIC_DESCRIPTOR = 75,\n\tWLAN_EID_MMIE = 76,\n\tWLAN_EID_ASSOC_COMEBACK_TIME = 77,\n\tWLAN_EID_EVENT_REQUEST = 78,\n\tWLAN_EID_EVENT_REPORT = 79,\n\tWLAN_EID_DIAGNOSTIC_REQUEST = 80,\n\tWLAN_EID_DIAGNOSTIC_REPORT = 81,\n\tWLAN_EID_LOCATION_PARAMS = 82,\n\tWLAN_EID_NON_TX_BSSID_CAP = 83,\n\tWLAN_EID_SSID_LIST = 84,\n\tWLAN_EID_MULTI_BSSID_IDX = 85,\n\tWLAN_EID_FMS_DESCRIPTOR = 86,\n\tWLAN_EID_FMS_REQUEST = 87,\n\tWLAN_EID_FMS_RESPONSE = 88,\n\tWLAN_EID_QOS_TRAFFIC_CAPA = 89,\n\tWLAN_EID_BSS_MAX_IDLE_PERIOD = 90,\n\tWLAN_EID_TSF_REQUEST = 91,\n\tWLAN_EID_TSF_RESPOSNE = 92,\n\tWLAN_EID_WNM_SLEEP_MODE = 93,\n\tWLAN_EID_TIM_BCAST_REQ = 94,\n\tWLAN_EID_TIM_BCAST_RESP = 95,\n\tWLAN_EID_COLL_IF_REPORT = 96,\n\tWLAN_EID_CHANNEL_USAGE = 97,\n\tWLAN_EID_TIME_ZONE = 98,\n\tWLAN_EID_DMS_REQUEST = 99,\n\tWLAN_EID_DMS_RESPONSE = 100,\n\tWLAN_EID_LINK_ID = 101,\n\tWLAN_EID_WAKEUP_SCHEDUL = 102,\n\tWLAN_EID_CHAN_SWITCH_TIMING = 104,\n\tWLAN_EID_PTI_CONTROL = 105,\n\tWLAN_EID_PU_BUFFER_STATUS = 106,\n\tWLAN_EID_INTERWORKING = 107,\n\tWLAN_EID_ADVERTISEMENT_PROTOCOL = 108,\n\tWLAN_EID_EXPEDITED_BW_REQ = 109,\n\tWLAN_EID_QOS_MAP_SET = 110,\n\tWLAN_EID_ROAMING_CONSORTIUM = 111,\n\tWLAN_EID_EMERGENCY_ALERT = 112,\n\tWLAN_EID_MESH_CONFIG = 113,\n\tWLAN_EID_MESH_ID = 114,\n\tWLAN_EID_LINK_METRIC_REPORT = 115,\n\tWLAN_EID_CONGESTION_NOTIFICATION = 116,\n\tWLAN_EID_PEER_MGMT = 117,\n\tWLAN_EID_CHAN_SWITCH_PARAM = 118,\n\tWLAN_EID_MESH_AWAKE_WINDOW = 119,\n\tWLAN_EID_BEACON_TIMING = 120,\n\tWLAN_EID_MCCAOP_SETUP_REQ = 121,\n\tWLAN_EID_MCCAOP_SETUP_RESP = 122,\n\tWLAN_EID_MCCAOP_ADVERT = 123,\n\tWLAN_EID_MCCAOP_TEARDOWN = 124,\n\tWLAN_EID_GANN = 125,\n\tWLAN_EID_RANN = 126,\n\tWLAN_EID_EXT_CAPABILITY = 127,\n\tWLAN_EID_PREQ = 130,\n\tWLAN_EID_PREP = 131,\n\tWLAN_EID_PERR = 132,\n\tWLAN_EID_PXU = 137,\n\tWLAN_EID_PXUC = 138,\n\tWLAN_EID_AUTH_MESH_PEER_EXCH = 139,\n\tWLAN_EID_MIC = 140,\n\tWLAN_EID_DESTINATION_URI = 141,\n\tWLAN_EID_UAPSD_COEX = 142,\n\tWLAN_EID_WAKEUP_SCHEDULE = 143,\n\tWLAN_EID_EXT_SCHEDULE = 144,\n\tWLAN_EID_STA_AVAILABILITY = 145,\n\tWLAN_EID_DMG_TSPEC = 146,\n\tWLAN_EID_DMG_AT = 147,\n\tWLAN_EID_DMG_CAP = 148,\n\tWLAN_EID_CISCO_VENDOR_SPECIFIC = 150,\n\tWLAN_EID_DMG_OPERATION = 151,\n\tWLAN_EID_DMG_BSS_PARAM_CHANGE = 152,\n\tWLAN_EID_DMG_BEAM_REFINEMENT = 153,\n\tWLAN_EID_CHANNEL_MEASURE_FEEDBACK = 154,\n\tWLAN_EID_AWAKE_WINDOW = 157,\n\tWLAN_EID_MULTI_BAND = 158,\n\tWLAN_EID_ADDBA_EXT = 159,\n\tWLAN_EID_NEXT_PCP_LIST = 160,\n\tWLAN_EID_PCP_HANDOVER = 161,\n\tWLAN_EID_DMG_LINK_MARGIN = 162,\n\tWLAN_EID_SWITCHING_STREAM = 163,\n\tWLAN_EID_SESSION_TRANSITION = 164,\n\tWLAN_EID_DYN_TONE_PAIRING_REPORT = 165,\n\tWLAN_EID_CLUSTER_REPORT = 166,\n\tWLAN_EID_RELAY_CAP = 167,\n\tWLAN_EID_RELAY_XFER_PARAM_SET = 168,\n\tWLAN_EID_BEAM_LINK_MAINT = 169,\n\tWLAN_EID_MULTIPLE_MAC_ADDR = 170,\n\tWLAN_EID_U_PID = 171,\n\tWLAN_EID_DMG_LINK_ADAPT_ACK = 172,\n\tWLAN_EID_MCCAOP_ADV_OVERVIEW = 174,\n\tWLAN_EID_QUIET_PERIOD_REQ = 175,\n\tWLAN_EID_QUIET_PERIOD_RESP = 177,\n\tWLAN_EID_EPAC_POLICY = 182,\n\tWLAN_EID_CLISTER_TIME_OFF = 183,\n\tWLAN_EID_INTER_AC_PRIO = 184,\n\tWLAN_EID_SCS_DESCRIPTOR = 185,\n\tWLAN_EID_QLOAD_REPORT = 186,\n\tWLAN_EID_HCCA_TXOP_UPDATE_COUNT = 187,\n\tWLAN_EID_HL_STREAM_ID = 188,\n\tWLAN_EID_GCR_GROUP_ADDR = 189,\n\tWLAN_EID_ANTENNA_SECTOR_ID_PATTERN = 190,\n\tWLAN_EID_VHT_CAPABILITY = 191,\n\tWLAN_EID_VHT_OPERATION = 192,\n\tWLAN_EID_EXTENDED_BSS_LOAD = 193,\n\tWLAN_EID_WIDE_BW_CHANNEL_SWITCH = 194,\n\tWLAN_EID_TX_POWER_ENVELOPE = 195,\n\tWLAN_EID_CHANNEL_SWITCH_WRAPPER = 196,\n\tWLAN_EID_AID = 197,\n\tWLAN_EID_QUIET_CHANNEL = 198,\n\tWLAN_EID_OPMODE_NOTIF = 199,\n\tWLAN_EID_REDUCED_NEIGHBOR_REPORT = 201,\n\tWLAN_EID_AID_REQUEST = 210,\n\tWLAN_EID_AID_RESPONSE = 211,\n\tWLAN_EID_S1G_BCN_COMPAT = 213,\n\tWLAN_EID_S1G_SHORT_BCN_INTERVAL = 214,\n\tWLAN_EID_S1G_TWT = 216,\n\tWLAN_EID_S1G_CAPABILITIES = 217,\n\tWLAN_EID_VENDOR_SPECIFIC = 221,\n\tWLAN_EID_QOS_PARAMETER = 222,\n\tWLAN_EID_S1G_OPERATION = 232,\n\tWLAN_EID_CAG_NUMBER = 237,\n\tWLAN_EID_AP_CSN = 239,\n\tWLAN_EID_FILS_INDICATION = 240,\n\tWLAN_EID_DILS = 241,\n\tWLAN_EID_FRAGMENT = 242,\n\tWLAN_EID_RSNX = 244,\n\tWLAN_EID_EXTENSION = 255,\n};\n\nenum ieee80211_eid_ext {\n\tWLAN_EID_EXT_ASSOC_DELAY_INFO = 1,\n\tWLAN_EID_EXT_FILS_REQ_PARAMS = 2,\n\tWLAN_EID_EXT_FILS_KEY_CONFIRM = 3,\n\tWLAN_EID_EXT_FILS_SESSION = 4,\n\tWLAN_EID_EXT_FILS_HLP_CONTAINER = 5,\n\tWLAN_EID_EXT_FILS_IP_ADDR_ASSIGN = 6,\n\tWLAN_EID_EXT_KEY_DELIVERY = 7,\n\tWLAN_EID_EXT_FILS_WRAPPED_DATA = 8,\n\tWLAN_EID_EXT_FILS_PUBLIC_KEY = 12,\n\tWLAN_EID_EXT_FILS_NONCE = 13,\n\tWLAN_EID_EXT_FUTURE_CHAN_GUIDANCE = 14,\n\tWLAN_EID_EXT_DH_PARAMETER = 32,\n\tWLAN_EID_EXT_HE_CAPABILITY = 35,\n\tWLAN_EID_EXT_HE_OPERATION = 36,\n\tWLAN_EID_EXT_UORA = 37,\n\tWLAN_EID_EXT_HE_MU_EDCA = 38,\n\tWLAN_EID_EXT_HE_SPR = 39,\n\tWLAN_EID_EXT_NDP_FEEDBACK_REPORT_PARAMSET = 41,\n\tWLAN_EID_EXT_BSS_COLOR_CHG_ANN = 42,\n\tWLAN_EID_EXT_QUIET_TIME_PERIOD_SETUP = 43,\n\tWLAN_EID_EXT_ESS_REPORT = 45,\n\tWLAN_EID_EXT_OPS = 46,\n\tWLAN_EID_EXT_HE_BSS_LOAD = 47,\n\tWLAN_EID_EXT_MAX_CHANNEL_SWITCH_TIME = 52,\n\tWLAN_EID_EXT_MULTIPLE_BSSID_CONFIGURATION = 55,\n\tWLAN_EID_EXT_NON_INHERITANCE = 56,\n\tWLAN_EID_EXT_KNOWN_BSSID = 57,\n\tWLAN_EID_EXT_SHORT_SSID_LIST = 58,\n\tWLAN_EID_EXT_HE_6GHZ_CAPA = 59,\n\tWLAN_EID_EXT_UL_MU_POWER_CAPA = 60,\n\tWLAN_EID_EXT_EHT_OPERATION = 106,\n\tWLAN_EID_EXT_EHT_MULTI_LINK = 107,\n\tWLAN_EID_EXT_EHT_CAPABILITY = 108,\n\tWLAN_EID_EXT_TID_TO_LINK_MAPPING = 109,\n\tWLAN_EID_EXT_BANDWIDTH_INDICATION = 135,\n\tWLAN_EID_EXT_KNOWN_STA_IDENTIFCATION = 136,\n\tWLAN_EID_EXT_NON_AP_STA_REG_CON = 137,\n\tWLAN_EID_EXT_UHR_OPER = 151,\n\tWLAN_EID_EXT_UHR_CAPA = 152,\n\tWLAN_EID_EXT_MACP = 153,\n\tWLAN_EID_EXT_SMD = 154,\n\tWLAN_EID_EXT_BSS_SMD_TRANS_PARAMS = 155,\n\tWLAN_EID_EXT_CHAN_USAGE = 156,\n\tWLAN_EID_EXT_UHR_MODE_CHG = 157,\n\tWLAN_EID_EXT_UHR_PARAM_UPD = 158,\n\tWLAN_EID_EXT_TXPI = 159,\n};\n\nenum ieee80211_elems_parse_error {\n\tIEEE80211_PARSE_ERR_INVALID_END = 1,\n\tIEEE80211_PARSE_ERR_DUP_ELEM = 2,\n\tIEEE80211_PARSE_ERR_BAD_ELEM_SIZE = 4,\n\tIEEE80211_PARSE_ERR_UNEXPECTED_ELEM = 8,\n\tIEEE80211_PARSE_ERR_DUP_NEST_ML_BASIC = 16,\n};\n\nenum ieee80211_encrypt {\n\tENCRYPT_NO = 0,\n\tENCRYPT_MGMT = 1,\n\tENCRYPT_DATA = 2,\n};\n\nenum ieee80211_event_type {\n\tRSSI_EVENT = 0,\n\tMLME_EVENT = 1,\n\tBAR_RX_EVENT = 2,\n\tBA_FRAME_TIMEOUT = 3,\n};\n\nenum ieee80211_filter_flags {\n\tFIF_ALLMULTI = 2,\n\tFIF_FCSFAIL = 4,\n\tFIF_PLCPFAIL = 8,\n\tFIF_BCN_PRBRESP_PROMISC = 16,\n\tFIF_CONTROL = 32,\n\tFIF_OTHER_BSS = 64,\n\tFIF_PSPOLL = 128,\n\tFIF_PROBE_REQ = 256,\n\tFIF_MCAST_ACTION = 512,\n};\n\nenum ieee80211_frame_release_type {\n\tIEEE80211_FRAME_RELEASE_PSPOLL = 0,\n\tIEEE80211_FRAME_RELEASE_UAPSD = 1,\n};\n\nenum ieee80211_he_mcs_support {\n\tIEEE80211_HE_MCS_SUPPORT_0_7 = 0,\n\tIEEE80211_HE_MCS_SUPPORT_0_9 = 1,\n\tIEEE80211_HE_MCS_SUPPORT_0_11 = 2,\n\tIEEE80211_HE_MCS_NOT_SUPPORTED = 3,\n};\n\nenum ieee80211_ht_actioncode {\n\tWLAN_HT_ACTION_NOTIFY_CHANWIDTH = 0,\n\tWLAN_HT_ACTION_SMPS = 1,\n\tWLAN_HT_ACTION_PSMP = 2,\n\tWLAN_HT_ACTION_PCO_PHASE = 3,\n\tWLAN_HT_ACTION_CSI = 4,\n\tWLAN_HT_ACTION_NONCOMPRESSED_BF = 5,\n\tWLAN_HT_ACTION_COMPRESSED_BF = 6,\n\tWLAN_HT_ACTION_ASEL_IDX_FEEDBACK = 7,\n};\n\nenum ieee80211_ht_chanwidth_values {\n\tIEEE80211_HT_CHANWIDTH_20MHZ = 0,\n\tIEEE80211_HT_CHANWIDTH_ANY = 1,\n};\n\nenum ieee80211_hw_flags {\n\tIEEE80211_HW_HAS_RATE_CONTROL = 0,\n\tIEEE80211_HW_RX_INCLUDES_FCS = 1,\n\tIEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 2,\n\tIEEE80211_HW_SIGNAL_UNSPEC = 3,\n\tIEEE80211_HW_SIGNAL_DBM = 4,\n\tIEEE80211_HW_NEED_DTIM_BEFORE_ASSOC = 5,\n\tIEEE80211_HW_SPECTRUM_MGMT = 6,\n\tIEEE80211_HW_AMPDU_AGGREGATION = 7,\n\tIEEE80211_HW_SUPPORTS_PS = 8,\n\tIEEE80211_HW_PS_NULLFUNC_STACK = 9,\n\tIEEE80211_HW_SUPPORTS_DYNAMIC_PS = 10,\n\tIEEE80211_HW_MFP_CAPABLE = 11,\n\tIEEE80211_HW_WANT_MONITOR_VIF = 12,\n\tIEEE80211_HW_NO_VIRTUAL_MONITOR = 13,\n\tIEEE80211_HW_NO_AUTO_VIF = 14,\n\tIEEE80211_HW_SW_CRYPTO_CONTROL = 15,\n\tIEEE80211_HW_SUPPORT_FAST_XMIT = 16,\n\tIEEE80211_HW_REPORTS_TX_ACK_STATUS = 17,\n\tIEEE80211_HW_CONNECTION_MONITOR = 18,\n\tIEEE80211_HW_QUEUE_CONTROL = 19,\n\tIEEE80211_HW_SUPPORTS_PER_STA_GTK = 20,\n\tIEEE80211_HW_AP_LINK_PS = 21,\n\tIEEE80211_HW_TX_AMPDU_SETUP_IN_HW = 22,\n\tIEEE80211_HW_SUPPORTS_RC_TABLE = 23,\n\tIEEE80211_HW_P2P_DEV_ADDR_FOR_INTF = 24,\n\tIEEE80211_HW_TIMING_BEACON_ONLY = 25,\n\tIEEE80211_HW_SUPPORTS_HT_CCK_RATES = 26,\n\tIEEE80211_HW_CHANCTX_STA_CSA = 27,\n\tIEEE80211_HW_SUPPORTS_CLONED_SKBS = 28,\n\tIEEE80211_HW_SINGLE_SCAN_ON_ALL_BANDS = 29,\n\tIEEE80211_HW_TDLS_WIDER_BW = 30,\n\tIEEE80211_HW_SUPPORTS_AMSDU_IN_AMPDU = 31,\n\tIEEE80211_HW_BEACON_TX_STATUS = 32,\n\tIEEE80211_HW_NEEDS_UNIQUE_STA_ADDR = 33,\n\tIEEE80211_HW_SUPPORTS_REORDERING_BUFFER = 34,\n\tIEEE80211_HW_USES_RSS = 35,\n\tIEEE80211_HW_TX_AMSDU = 36,\n\tIEEE80211_HW_TX_FRAG_LIST = 37,\n\tIEEE80211_HW_REPORTS_LOW_ACK = 38,\n\tIEEE80211_HW_SUPPORTS_TX_FRAG = 39,\n\tIEEE80211_HW_SUPPORTS_TDLS_BUFFER_STA = 40,\n\tIEEE80211_HW_DOESNT_SUPPORT_QOS_NDP = 41,\n\tIEEE80211_HW_BUFF_MMPDU_TXQ = 42,\n\tIEEE80211_HW_SUPPORTS_VHT_EXT_NSS_BW = 43,\n\tIEEE80211_HW_STA_MMPDU_TXQ = 44,\n\tIEEE80211_HW_TX_STATUS_NO_AMPDU_LEN = 45,\n\tIEEE80211_HW_SUPPORTS_MULTI_BSSID = 46,\n\tIEEE80211_HW_SUPPORTS_ONLY_HE_MULTI_BSSID = 47,\n\tIEEE80211_HW_AMPDU_KEYBORDER_SUPPORT = 48,\n\tIEEE80211_HW_SUPPORTS_TX_ENCAP_OFFLOAD = 49,\n\tIEEE80211_HW_SUPPORTS_RX_DECAP_OFFLOAD = 50,\n\tIEEE80211_HW_SUPPORTS_CONC_MON_RX_DECAP = 51,\n\tIEEE80211_HW_DETECTS_COLOR_COLLISION = 52,\n\tIEEE80211_HW_MLO_MCAST_MULTI_LINK_TX = 53,\n\tIEEE80211_HW_DISALLOW_PUNCTURING = 54,\n\tIEEE80211_HW_HANDLES_QUIET_CSA = 55,\n\tIEEE80211_HW_STRICT = 56,\n\tNUM_IEEE80211_HW_FLAGS = 57,\n};\n\nenum ieee80211_idle_options {\n\tWLAN_IDLE_OPTIONS_PROTECTED_KEEP_ALIVE = 1,\n};\n\nenum ieee80211_interface_iteration_flags {\n\tIEEE80211_IFACE_ITER_NORMAL = 0,\n\tIEEE80211_IFACE_ITER_RESUME_ALL = 1,\n\tIEEE80211_IFACE_ITER_ACTIVE = 2,\n\tIEEE80211_IFACE_SKIP_SDATA_NOT_IN_DRIVER = 4,\n};\n\nenum ieee80211_internal_key_flags {\n\tKEY_FLAG_UPLOADED_TO_HARDWARE = 1,\n\tKEY_FLAG_TAINTED = 2,\n};\n\nenum ieee80211_internal_tkip_state {\n\tTKIP_STATE_NOT_INIT = 0,\n\tTKIP_STATE_PHASE1_DONE = 1,\n\tTKIP_STATE_PHASE1_HW_UPLOADED = 2,\n};\n\nenum ieee80211_key_flags {\n\tIEEE80211_KEY_FLAG_GENERATE_IV_MGMT = 1,\n\tIEEE80211_KEY_FLAG_GENERATE_IV = 2,\n\tIEEE80211_KEY_FLAG_GENERATE_MMIC = 4,\n\tIEEE80211_KEY_FLAG_PAIRWISE = 8,\n\tIEEE80211_KEY_FLAG_SW_MGMT_TX = 16,\n\tIEEE80211_KEY_FLAG_PUT_IV_SPACE = 32,\n\tIEEE80211_KEY_FLAG_RX_MGMT = 64,\n\tIEEE80211_KEY_FLAG_RESERVE_TAILROOM = 128,\n\tIEEE80211_KEY_FLAG_PUT_MIC_SPACE = 256,\n\tIEEE80211_KEY_FLAG_NO_AUTO_TX = 512,\n\tIEEE80211_KEY_FLAG_GENERATE_MMIE = 1024,\n\tIEEE80211_KEY_FLAG_SPP_AMSDU = 2048,\n};\n\nenum ieee80211_key_len {\n\tWLAN_KEY_LEN_WEP40 = 5,\n\tWLAN_KEY_LEN_WEP104 = 13,\n\tWLAN_KEY_LEN_CCMP = 16,\n\tWLAN_KEY_LEN_CCMP_256 = 32,\n\tWLAN_KEY_LEN_TKIP = 32,\n\tWLAN_KEY_LEN_AES_CMAC = 16,\n\tWLAN_KEY_LEN_SMS4 = 32,\n\tWLAN_KEY_LEN_GCMP = 16,\n\tWLAN_KEY_LEN_GCMP_256 = 32,\n\tWLAN_KEY_LEN_BIP_CMAC_256 = 32,\n\tWLAN_KEY_LEN_BIP_GMAC_128 = 16,\n\tWLAN_KEY_LEN_BIP_GMAC_256 = 32,\n};\n\nenum ieee80211_max_queues {\n\tIEEE80211_MAX_QUEUES = 16,\n\tIEEE80211_MAX_QUEUE_MAP = 65535,\n};\n\nenum ieee80211_mesh_path_metric {\n\tIEEE80211_PATH_METRIC_AIRTIME = 1,\n\tIEEE80211_PATH_METRIC_VENDOR = 255,\n};\n\nenum ieee80211_mesh_path_protocol {\n\tIEEE80211_PATH_PROTOCOL_HWMP = 1,\n\tIEEE80211_PATH_PROTOCOL_VENDOR = 255,\n};\n\nenum ieee80211_mesh_sync_method {\n\tIEEE80211_SYNC_METHOD_NEIGHBOR_OFFSET = 1,\n\tIEEE80211_SYNC_METHOD_VENDOR = 255,\n};\n\nenum ieee80211_mle_subelems {\n\tIEEE80211_MLE_SUBELEM_PER_STA_PROFILE = 0,\n\tIEEE80211_MLE_SUBELEM_FRAGMENT = 254,\n};\n\nenum ieee80211_mlme_event_data {\n\tAUTH_EVENT = 0,\n\tASSOC_EVENT = 1,\n\tDEAUTH_RX_EVENT = 2,\n\tDEAUTH_TX_EVENT = 3,\n};\n\nenum ieee80211_mlme_event_status {\n\tMLME_SUCCESS = 0,\n\tMLME_DENIED = 1,\n\tMLME_TIMEOUT = 2,\n};\n\nenum ieee80211_neg_ttlm_res {\n\tNEG_TTLM_RES_ACCEPT = 0,\n\tNEG_TTLM_RES_REJECT = 1,\n\tNEG_TTLM_RES_SUGGEST_PREFERRED = 2,\n};\n\nenum ieee80211_offload_flags {\n\tIEEE80211_OFFLOAD_ENCAP_ENABLED = 1,\n\tIEEE80211_OFFLOAD_ENCAP_4ADDR = 2,\n\tIEEE80211_OFFLOAD_DECAP_ENABLED = 4,\n};\n\nenum ieee80211_p2p_attr_id {\n\tIEEE80211_P2P_ATTR_STATUS = 0,\n\tIEEE80211_P2P_ATTR_MINOR_REASON = 1,\n\tIEEE80211_P2P_ATTR_CAPABILITY = 2,\n\tIEEE80211_P2P_ATTR_DEVICE_ID = 3,\n\tIEEE80211_P2P_ATTR_GO_INTENT = 4,\n\tIEEE80211_P2P_ATTR_GO_CONFIG_TIMEOUT = 5,\n\tIEEE80211_P2P_ATTR_LISTEN_CHANNEL = 6,\n\tIEEE80211_P2P_ATTR_GROUP_BSSID = 7,\n\tIEEE80211_P2P_ATTR_EXT_LISTEN_TIMING = 8,\n\tIEEE80211_P2P_ATTR_INTENDED_IFACE_ADDR = 9,\n\tIEEE80211_P2P_ATTR_MANAGABILITY = 10,\n\tIEEE80211_P2P_ATTR_CHANNEL_LIST = 11,\n\tIEEE80211_P2P_ATTR_ABSENCE_NOTICE = 12,\n\tIEEE80211_P2P_ATTR_DEVICE_INFO = 13,\n\tIEEE80211_P2P_ATTR_GROUP_INFO = 14,\n\tIEEE80211_P2P_ATTR_GROUP_ID = 15,\n\tIEEE80211_P2P_ATTR_INTERFACE = 16,\n\tIEEE80211_P2P_ATTR_OPER_CHANNEL = 17,\n\tIEEE80211_P2P_ATTR_INVITE_FLAGS = 18,\n\tIEEE80211_P2P_ATTR_VENDOR_SPECIFIC = 221,\n\tIEEE80211_P2P_ATTR_MAX = 222,\n};\n\nenum ieee80211_packet_rx_flags {\n\tIEEE80211_RX_AMSDU = 8,\n\tIEEE80211_RX_MALFORMED_ACTION_FRM = 16,\n\tIEEE80211_RX_DEFERRED_RELEASE = 32,\n};\n\nenum ieee80211_privacy {\n\tIEEE80211_PRIVACY_ON = 0,\n\tIEEE80211_PRIVACY_OFF = 1,\n\tIEEE80211_PRIVACY_ANY = 2,\n};\n\nenum ieee80211_protected_eht_actioncode {\n\tWLAN_PROTECTED_EHT_ACTION_TTLM_REQ = 0,\n\tWLAN_PROTECTED_EHT_ACTION_TTLM_RES = 1,\n\tWLAN_PROTECTED_EHT_ACTION_TTLM_TEARDOWN = 2,\n\tWLAN_PROTECTED_EHT_ACTION_EPCS_ENABLE_REQ = 3,\n\tWLAN_PROTECTED_EHT_ACTION_EPCS_ENABLE_RESP = 4,\n\tWLAN_PROTECTED_EHT_ACTION_EPCS_ENABLE_TEARDOWN = 5,\n\tWLAN_PROTECTED_EHT_ACTION_EML_OP_MODE_NOTIF = 6,\n\tWLAN_PROTECTED_EHT_ACTION_LINK_RECOMMEND = 7,\n\tWLAN_PROTECTED_EHT_ACTION_ML_OP_UPDATE_REQ = 8,\n\tWLAN_PROTECTED_EHT_ACTION_ML_OP_UPDATE_RESP = 9,\n\tWLAN_PROTECTED_EHT_ACTION_LINK_RECONFIG_NOTIF = 10,\n\tWLAN_PROTECTED_EHT_ACTION_LINK_RECONFIG_REQ = 11,\n\tWLAN_PROTECTED_EHT_ACTION_LINK_RECONFIG_RESP = 12,\n};\n\nenum ieee80211_pub_actioncode {\n\tWLAN_PUB_ACTION_20_40_BSS_COEX = 0,\n\tWLAN_PUB_ACTION_DSE_ENABLEMENT = 1,\n\tWLAN_PUB_ACTION_DSE_DEENABLEMENT = 2,\n\tWLAN_PUB_ACTION_DSE_REG_LOC_ANN = 3,\n\tWLAN_PUB_ACTION_EXT_CHANSW_ANN = 4,\n\tWLAN_PUB_ACTION_DSE_MSMT_REQ = 5,\n\tWLAN_PUB_ACTION_DSE_MSMT_RESP = 6,\n\tWLAN_PUB_ACTION_MSMT_PILOT = 7,\n\tWLAN_PUB_ACTION_DSE_PC = 8,\n\tWLAN_PUB_ACTION_VENDOR_SPECIFIC = 9,\n\tWLAN_PUB_ACTION_GAS_INITIAL_REQ = 10,\n\tWLAN_PUB_ACTION_GAS_INITIAL_RESP = 11,\n\tWLAN_PUB_ACTION_GAS_COMEBACK_REQ = 12,\n\tWLAN_PUB_ACTION_GAS_COMEBACK_RESP = 13,\n\tWLAN_PUB_ACTION_TDLS_DISCOVER_RES = 14,\n\tWLAN_PUB_ACTION_LOC_TRACK_NOTI = 15,\n\tWLAN_PUB_ACTION_QAB_REQUEST_FRAME = 16,\n\tWLAN_PUB_ACTION_QAB_RESPONSE_FRAME = 17,\n\tWLAN_PUB_ACTION_QMF_POLICY = 18,\n\tWLAN_PUB_ACTION_QMF_POLICY_CHANGE = 19,\n\tWLAN_PUB_ACTION_QLOAD_REQUEST = 20,\n\tWLAN_PUB_ACTION_QLOAD_REPORT = 21,\n\tWLAN_PUB_ACTION_HCCA_TXOP_ADVERT = 22,\n\tWLAN_PUB_ACTION_HCCA_TXOP_RESPONSE = 23,\n\tWLAN_PUB_ACTION_PUBLIC_KEY = 24,\n\tWLAN_PUB_ACTION_CHANNEL_AVAIL_QUERY = 25,\n\tWLAN_PUB_ACTION_CHANNEL_SCHEDULE_MGMT = 26,\n\tWLAN_PUB_ACTION_CONTACT_VERI_SIGNAL = 27,\n\tWLAN_PUB_ACTION_GDD_ENABLEMENT_REQ = 28,\n\tWLAN_PUB_ACTION_GDD_ENABLEMENT_RESP = 29,\n\tWLAN_PUB_ACTION_NETWORK_CHANNEL_CONTROL = 30,\n\tWLAN_PUB_ACTION_WHITE_SPACE_MAP_ANN = 31,\n\tWLAN_PUB_ACTION_FTM_REQUEST = 32,\n\tWLAN_PUB_ACTION_FTM_RESPONSE = 33,\n\tWLAN_PUB_ACTION_FILS_DISCOVERY = 34,\n};\n\nenum ieee80211_radiotap_ampdu_flags {\n\tIEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN = 1,\n\tIEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN = 2,\n\tIEEE80211_RADIOTAP_AMPDU_LAST_KNOWN = 4,\n\tIEEE80211_RADIOTAP_AMPDU_IS_LAST = 8,\n\tIEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR = 16,\n\tIEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN = 32,\n\tIEEE80211_RADIOTAP_AMPDU_EOF = 64,\n\tIEEE80211_RADIOTAP_AMPDU_EOF_KNOWN = 128,\n};\n\nenum ieee80211_radiotap_channel_flags {\n\tIEEE80211_CHAN_CCK = 32,\n\tIEEE80211_CHAN_OFDM = 64,\n\tIEEE80211_CHAN_2GHZ = 128,\n\tIEEE80211_CHAN_5GHZ = 256,\n\tIEEE80211_CHAN_DYN = 1024,\n\tIEEE80211_CHAN_HALF = 16384,\n\tIEEE80211_CHAN_QUARTER = 32768,\n};\n\nenum ieee80211_radiotap_flags {\n\tIEEE80211_RADIOTAP_F_CFP = 1,\n\tIEEE80211_RADIOTAP_F_SHORTPRE = 2,\n\tIEEE80211_RADIOTAP_F_WEP = 4,\n\tIEEE80211_RADIOTAP_F_FRAG = 8,\n\tIEEE80211_RADIOTAP_F_FCS = 16,\n\tIEEE80211_RADIOTAP_F_DATAPAD = 32,\n\tIEEE80211_RADIOTAP_F_BADFCS = 64,\n};\n\nenum ieee80211_radiotap_he_bits {\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3,\n\tIEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 4,\n\tIEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 8,\n\tIEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 16,\n\tIEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 32,\n\tIEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 64,\n\tIEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 128,\n\tIEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 256,\n\tIEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 512,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 1024,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 2048,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 4096,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 8192,\n\tIEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 1,\n\tIEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 2,\n\tIEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 4,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 8,\n\tIEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 16,\n\tIEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 32,\n\tIEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 64,\n\tIEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 128,\n\tIEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 16128,\n\tIEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 63,\n\tIEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 64,\n\tIEEE80211_RADIOTAP_HE_DATA3_UL_DL = 128,\n\tIEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 3840,\n\tIEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 4096,\n\tIEEE80211_RADIOTAP_HE_DATA3_CODING = 8192,\n\tIEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA3_STBC = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 15,\n\tIEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 32752,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 15,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 240,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 3840,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 61440,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 15,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI = 48,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 192,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3,\n\tIEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 1792,\n\tIEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 12288,\n\tIEEE80211_RADIOTAP_HE_DATA5_TXBF = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA6_NSTS = 15,\n\tIEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 16,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN = 32,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW = 192,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ = 0,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ = 1,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ = 2,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ = 3,\n\tIEEE80211_RADIOTAP_HE_DATA6_TXOP = 32512,\n\tIEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 32768,\n};\n\nenum ieee80211_radiotap_mcs_flags {\n\tIEEE80211_RADIOTAP_MCS_BW_MASK = 3,\n\tIEEE80211_RADIOTAP_MCS_BW_20 = 0,\n\tIEEE80211_RADIOTAP_MCS_BW_40 = 1,\n\tIEEE80211_RADIOTAP_MCS_BW_20L = 2,\n\tIEEE80211_RADIOTAP_MCS_BW_20U = 3,\n\tIEEE80211_RADIOTAP_MCS_SGI = 4,\n\tIEEE80211_RADIOTAP_MCS_FMT_GF = 8,\n\tIEEE80211_RADIOTAP_MCS_FEC_LDPC = 16,\n\tIEEE80211_RADIOTAP_MCS_STBC_MASK = 96,\n\tIEEE80211_RADIOTAP_MCS_STBC_1 = 1,\n\tIEEE80211_RADIOTAP_MCS_STBC_2 = 2,\n\tIEEE80211_RADIOTAP_MCS_STBC_3 = 3,\n\tIEEE80211_RADIOTAP_MCS_STBC_SHIFT = 5,\n};\n\nenum ieee80211_radiotap_mcs_have {\n\tIEEE80211_RADIOTAP_MCS_HAVE_BW = 1,\n\tIEEE80211_RADIOTAP_MCS_HAVE_MCS = 2,\n\tIEEE80211_RADIOTAP_MCS_HAVE_GI = 4,\n\tIEEE80211_RADIOTAP_MCS_HAVE_FMT = 8,\n\tIEEE80211_RADIOTAP_MCS_HAVE_FEC = 16,\n\tIEEE80211_RADIOTAP_MCS_HAVE_STBC = 32,\n};\n\nenum ieee80211_radiotap_presence {\n\tIEEE80211_RADIOTAP_TSFT = 0,\n\tIEEE80211_RADIOTAP_FLAGS = 1,\n\tIEEE80211_RADIOTAP_RATE = 2,\n\tIEEE80211_RADIOTAP_CHANNEL = 3,\n\tIEEE80211_RADIOTAP_FHSS = 4,\n\tIEEE80211_RADIOTAP_DBM_ANTSIGNAL = 5,\n\tIEEE80211_RADIOTAP_DBM_ANTNOISE = 6,\n\tIEEE80211_RADIOTAP_LOCK_QUALITY = 7,\n\tIEEE80211_RADIOTAP_TX_ATTENUATION = 8,\n\tIEEE80211_RADIOTAP_DB_TX_ATTENUATION = 9,\n\tIEEE80211_RADIOTAP_DBM_TX_POWER = 10,\n\tIEEE80211_RADIOTAP_ANTENNA = 11,\n\tIEEE80211_RADIOTAP_DB_ANTSIGNAL = 12,\n\tIEEE80211_RADIOTAP_DB_ANTNOISE = 13,\n\tIEEE80211_RADIOTAP_RX_FLAGS = 14,\n\tIEEE80211_RADIOTAP_TX_FLAGS = 15,\n\tIEEE80211_RADIOTAP_RTS_RETRIES = 16,\n\tIEEE80211_RADIOTAP_DATA_RETRIES = 17,\n\tIEEE80211_RADIOTAP_MCS = 19,\n\tIEEE80211_RADIOTAP_AMPDU_STATUS = 20,\n\tIEEE80211_RADIOTAP_VHT = 21,\n\tIEEE80211_RADIOTAP_TIMESTAMP = 22,\n\tIEEE80211_RADIOTAP_HE = 23,\n\tIEEE80211_RADIOTAP_HE_MU = 24,\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU = 26,\n\tIEEE80211_RADIOTAP_LSIG = 27,\n\tIEEE80211_RADIOTAP_TLV = 28,\n\tIEEE80211_RADIOTAP_RADIOTAP_NAMESPACE = 29,\n\tIEEE80211_RADIOTAP_VENDOR_NAMESPACE = 30,\n\tIEEE80211_RADIOTAP_EXT = 31,\n\tIEEE80211_RADIOTAP_EHT_USIG = 33,\n\tIEEE80211_RADIOTAP_EHT = 34,\n};\n\nenum ieee80211_radiotap_rx_flags {\n\tIEEE80211_RADIOTAP_F_RX_BADPLCP = 2,\n};\n\nenum ieee80211_radiotap_timestamp_flags {\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT = 0,\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT = 1,\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY = 2,\n};\n\nenum ieee80211_radiotap_tx_flags {\n\tIEEE80211_RADIOTAP_F_TX_FAIL = 1,\n\tIEEE80211_RADIOTAP_F_TX_CTS = 2,\n\tIEEE80211_RADIOTAP_F_TX_RTS = 4,\n\tIEEE80211_RADIOTAP_F_TX_NOACK = 8,\n\tIEEE80211_RADIOTAP_F_TX_NOSEQNO = 16,\n\tIEEE80211_RADIOTAP_F_TX_ORDER = 32,\n};\n\nenum ieee80211_radiotap_vht_bandwidth {\n\tIEEE80211_RADIOTAP_VHT_BW_20 = 0,\n\tIEEE80211_RADIOTAP_VHT_BW_40 = 1,\n\tIEEE80211_RADIOTAP_VHT_BW_80 = 4,\n\tIEEE80211_RADIOTAP_VHT_BW_160 = 11,\n};\n\nenum ieee80211_radiotap_vht_coding {\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER0 = 1,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER1 = 2,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER2 = 4,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER3 = 8,\n};\n\nenum ieee80211_radiotap_vht_flags {\n\tIEEE80211_RADIOTAP_VHT_FLAG_STBC = 1,\n\tIEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA = 2,\n\tIEEE80211_RADIOTAP_VHT_FLAG_SGI = 4,\n\tIEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 = 8,\n\tIEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM = 16,\n\tIEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED = 32,\n};\n\nenum ieee80211_radiotap_vht_known {\n\tIEEE80211_RADIOTAP_VHT_KNOWN_STBC = 1,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA = 2,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_GI = 4,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS = 8,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM = 16,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED = 32,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH = 64,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID = 128,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID = 256,\n};\n\nenum ieee80211_radiotap_zero_len_psdu_type {\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU_SOUNDING = 0,\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU_NOT_CAPTURED = 1,\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU_VENDOR = 255,\n};\n\nenum ieee80211_rate_control_changed {\n\tIEEE80211_RC_BW_CHANGED = 1,\n\tIEEE80211_RC_SMPS_CHANGED = 2,\n\tIEEE80211_RC_SUPP_RATES_CHANGED = 4,\n\tIEEE80211_RC_NSS_CHANGED = 8,\n};\n\nenum ieee80211_rate_flags {\n\tIEEE80211_RATE_SHORT_PREAMBLE = 1,\n\tIEEE80211_RATE_MANDATORY_A = 2,\n\tIEEE80211_RATE_MANDATORY_B = 4,\n\tIEEE80211_RATE_MANDATORY_G = 8,\n\tIEEE80211_RATE_ERP_G = 16,\n\tIEEE80211_RATE_SUPPORTS_5MHZ = 32,\n\tIEEE80211_RATE_SUPPORTS_10MHZ = 64,\n};\n\nenum ieee80211_reasoncode {\n\tWLAN_REASON_UNSPECIFIED = 1,\n\tWLAN_REASON_PREV_AUTH_NOT_VALID = 2,\n\tWLAN_REASON_DEAUTH_LEAVING = 3,\n\tWLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4,\n\tWLAN_REASON_DISASSOC_AP_BUSY = 5,\n\tWLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6,\n\tWLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7,\n\tWLAN_REASON_DISASSOC_STA_HAS_LEFT = 8,\n\tWLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9,\n\tWLAN_REASON_DISASSOC_BAD_POWER = 10,\n\tWLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11,\n\tWLAN_REASON_INVALID_IE = 13,\n\tWLAN_REASON_MIC_FAILURE = 14,\n\tWLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,\n\tWLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16,\n\tWLAN_REASON_IE_DIFFERENT = 17,\n\tWLAN_REASON_INVALID_GROUP_CIPHER = 18,\n\tWLAN_REASON_INVALID_PAIRWISE_CIPHER = 19,\n\tWLAN_REASON_INVALID_AKMP = 20,\n\tWLAN_REASON_UNSUPP_RSN_VERSION = 21,\n\tWLAN_REASON_INVALID_RSN_IE_CAP = 22,\n\tWLAN_REASON_IEEE8021X_FAILED = 23,\n\tWLAN_REASON_CIPHER_SUITE_REJECTED = 24,\n\tWLAN_REASON_TDLS_TEARDOWN_UNREACHABLE = 25,\n\tWLAN_REASON_TDLS_TEARDOWN_UNSPECIFIED = 26,\n\tWLAN_REASON_DISASSOC_UNSPECIFIED_QOS = 32,\n\tWLAN_REASON_DISASSOC_QAP_NO_BANDWIDTH = 33,\n\tWLAN_REASON_DISASSOC_LOW_ACK = 34,\n\tWLAN_REASON_DISASSOC_QAP_EXCEED_TXOP = 35,\n\tWLAN_REASON_QSTA_LEAVE_QBSS = 36,\n\tWLAN_REASON_QSTA_NOT_USE = 37,\n\tWLAN_REASON_QSTA_REQUIRE_SETUP = 38,\n\tWLAN_REASON_QSTA_TIMEOUT = 39,\n\tWLAN_REASON_QSTA_CIPHER_NOT_SUPP = 45,\n\tWLAN_REASON_MESH_PEER_CANCELED = 52,\n\tWLAN_REASON_MESH_MAX_PEERS = 53,\n\tWLAN_REASON_MESH_CONFIG = 54,\n\tWLAN_REASON_MESH_CLOSE = 55,\n\tWLAN_REASON_MESH_MAX_RETRIES = 56,\n\tWLAN_REASON_MESH_CONFIRM_TIMEOUT = 57,\n\tWLAN_REASON_MESH_INVALID_GTK = 58,\n\tWLAN_REASON_MESH_INCONSISTENT_PARAM = 59,\n\tWLAN_REASON_MESH_INVALID_SECURITY = 60,\n\tWLAN_REASON_MESH_PATH_ERROR = 61,\n\tWLAN_REASON_MESH_PATH_NOFORWARD = 62,\n\tWLAN_REASON_MESH_PATH_DEST_UNREACHABLE = 63,\n\tWLAN_REASON_MAC_EXISTS_IN_MBSS = 64,\n\tWLAN_REASON_MESH_CHAN_REGULATORY = 65,\n\tWLAN_REASON_MESH_CHAN = 66,\n};\n\nenum ieee80211_reconfig_type {\n\tIEEE80211_RECONFIG_TYPE_RESTART = 0,\n\tIEEE80211_RECONFIG_TYPE_SUSPEND = 1,\n};\n\nenum ieee80211_reg_conn_bits {\n\tIEEE80211_REG_CONN_LPI_VALID = 1,\n\tIEEE80211_REG_CONN_LPI_VALUE = 2,\n\tIEEE80211_REG_CONN_SP_VALID = 4,\n\tIEEE80211_REG_CONN_SP_VALUE = 8,\n};\n\nenum ieee80211_regd_source {\n\tREGD_SOURCE_INTERNAL_DB = 0,\n\tREGD_SOURCE_CRDA = 1,\n\tREGD_SOURCE_CACHED = 2,\n};\n\nenum ieee80211_regulatory_flags {\n\tREGULATORY_CUSTOM_REG = 1,\n\tREGULATORY_STRICT_REG = 2,\n\tREGULATORY_DISABLE_BEACON_HINTS = 4,\n\tREGULATORY_COUNTRY_IE_FOLLOW_POWER = 8,\n\tREGULATORY_COUNTRY_IE_IGNORE = 16,\n\tREGULATORY_ENABLE_RELAX_NO_IR = 32,\n\tREGULATORY_WIPHY_SELF_MANAGED = 128,\n};\n\nenum ieee80211_roc_type {\n\tIEEE80211_ROC_TYPE_NORMAL = 0,\n\tIEEE80211_ROC_TYPE_MGMT_TX = 1,\n};\n\nenum ieee80211_rssi_event_data {\n\tRSSI_EVENT_HIGH = 0,\n\tRSSI_EVENT_LOW = 1,\n};\n\nenum ieee80211_rx_flags {\n\tIEEE80211_RX_BEACON_REPORTED = 1,\n};\n\nenum ieee80211_s1g_actioncode {\n\tWLAN_S1G_AID_SWITCH_REQUEST = 0,\n\tWLAN_S1G_AID_SWITCH_RESPONSE = 1,\n\tWLAN_S1G_SYNC_CONTROL = 2,\n\tWLAN_S1G_STA_INFO_ANNOUNCE = 3,\n\tWLAN_S1G_EDCA_PARAM_SET = 4,\n\tWLAN_S1G_EL_OPERATION = 5,\n\tWLAN_S1G_TWT_SETUP = 6,\n\tWLAN_S1G_TWT_TEARDOWN = 7,\n\tWLAN_S1G_SECT_GROUP_ID_LIST = 8,\n\tWLAN_S1G_SECT_ID_FEEDBACK = 9,\n\tWLAN_S1G_TWT_INFORMATION = 11,\n};\n\nenum ieee80211_s1g_chanwidth {\n\tIEEE80211_S1G_CHANWIDTH_1MHZ = 0,\n\tIEEE80211_S1G_CHANWIDTH_2MHZ = 1,\n\tIEEE80211_S1G_CHANWIDTH_4MHZ = 3,\n\tIEEE80211_S1G_CHANWIDTH_8MHZ = 7,\n\tIEEE80211_S1G_CHANWIDTH_16MHZ = 15,\n};\n\nenum ieee80211_s1g_pri_chanwidth {\n\tIEEE80211_S1G_PRI_CHANWIDTH_2MHZ = 0,\n\tIEEE80211_S1G_PRI_CHANWIDTH_1MHZ = 1,\n};\n\nenum ieee80211_sa_query_action {\n\tWLAN_ACTION_SA_QUERY_REQUEST = 0,\n\tWLAN_ACTION_SA_QUERY_RESPONSE = 1,\n};\n\nenum ieee80211_sdata_state_bits {\n\tSDATA_STATE_RUNNING = 0,\n\tSDATA_STATE_OFFCHANNEL = 1,\n\tSDATA_STATE_OFFCHANNEL_BEACON_STOPPED = 2,\n};\n\nenum ieee80211_self_protected_actioncode {\n\tWLAN_SP_RESERVED = 0,\n\tWLAN_SP_MESH_PEERING_OPEN = 1,\n\tWLAN_SP_MESH_PEERING_CONFIRM = 2,\n\tWLAN_SP_MESH_PEERING_CLOSE = 3,\n\tWLAN_SP_MGK_INFORM = 4,\n\tWLAN_SP_MGK_ACK = 5,\n};\n\nenum ieee80211_smps_mode {\n\tIEEE80211_SMPS_AUTOMATIC = 0,\n\tIEEE80211_SMPS_OFF = 1,\n\tIEEE80211_SMPS_STATIC = 2,\n\tIEEE80211_SMPS_DYNAMIC = 3,\n\tIEEE80211_SMPS_NUM_MODES = 4,\n};\n\nenum ieee80211_spectrum_mgmt_actioncode {\n\tWLAN_ACTION_SPCT_MSR_REQ = 0,\n\tWLAN_ACTION_SPCT_MSR_RPRT = 1,\n\tWLAN_ACTION_SPCT_TPC_REQ = 2,\n\tWLAN_ACTION_SPCT_TPC_RPRT = 3,\n\tWLAN_ACTION_SPCT_CHL_SWITCH = 4,\n};\n\nenum ieee80211_sta_flags {\n\tIEEE80211_STA_CONNECTION_POLL = 2,\n\tIEEE80211_STA_CONTROL_PORT = 4,\n\tIEEE80211_STA_MFP_ENABLED = 64,\n\tIEEE80211_STA_UAPSD_ENABLED = 128,\n\tIEEE80211_STA_NULLFUNC_ACKED = 256,\n\tIEEE80211_STA_ENABLE_RRM = 32768,\n};\n\nenum ieee80211_sta_info_flags {\n\tWLAN_STA_AUTH = 0,\n\tWLAN_STA_ASSOC = 1,\n\tWLAN_STA_PS_STA = 2,\n\tWLAN_STA_AUTHORIZED = 3,\n\tWLAN_STA_SHORT_PREAMBLE = 4,\n\tWLAN_STA_WDS = 5,\n\tWLAN_STA_CLEAR_PS_FILT = 6,\n\tWLAN_STA_MFP = 7,\n\tWLAN_STA_BLOCK_BA = 8,\n\tWLAN_STA_PS_DRIVER = 9,\n\tWLAN_STA_PSPOLL = 10,\n\tWLAN_STA_TDLS_PEER = 11,\n\tWLAN_STA_TDLS_PEER_AUTH = 12,\n\tWLAN_STA_TDLS_INITIATOR = 13,\n\tWLAN_STA_TDLS_CHAN_SWITCH = 14,\n\tWLAN_STA_TDLS_OFF_CHANNEL = 15,\n\tWLAN_STA_TDLS_WIDER_BW = 16,\n\tWLAN_STA_UAPSD = 17,\n\tWLAN_STA_SP = 18,\n\tWLAN_STA_4ADDR_EVENT = 19,\n\tWLAN_STA_INSERTED = 20,\n\tWLAN_STA_RATE_CONTROL = 21,\n\tWLAN_STA_TOFFSET_KNOWN = 22,\n\tWLAN_STA_MPSP_OWNER = 23,\n\tWLAN_STA_MPSP_RECIPIENT = 24,\n\tWLAN_STA_PS_DELIVER = 25,\n\tWLAN_STA_USES_ENCRYPTION = 26,\n\tWLAN_STA_DECAP_OFFLOAD = 27,\n\tNUM_WLAN_STA_FLAGS = 28,\n};\n\nenum ieee80211_sta_rx_bandwidth {\n\tIEEE80211_STA_RX_BW_20 = 0,\n\tIEEE80211_STA_RX_BW_40 = 1,\n\tIEEE80211_STA_RX_BW_80 = 2,\n\tIEEE80211_STA_RX_BW_160 = 3,\n\tIEEE80211_STA_RX_BW_320 = 4,\n};\n\nenum ieee80211_sta_state {\n\tIEEE80211_STA_NOTEXIST = 0,\n\tIEEE80211_STA_NONE = 1,\n\tIEEE80211_STA_AUTH = 2,\n\tIEEE80211_STA_ASSOC = 3,\n\tIEEE80211_STA_AUTHORIZED = 4,\n};\n\nenum ieee80211_status_data {\n\tIEEE80211_STATUS_TYPE_MASK = 15,\n\tIEEE80211_STATUS_TYPE_INVALID = 0,\n\tIEEE80211_STATUS_TYPE_SMPS = 1,\n\tIEEE80211_STATUS_TYPE_NEG_TTLM = 2,\n\tIEEE80211_STATUS_SUBDATA_MASK = 8176,\n};\n\nenum ieee80211_statuscode {\n\tWLAN_STATUS_SUCCESS = 0,\n\tWLAN_STATUS_UNSPECIFIED_FAILURE = 1,\n\tWLAN_STATUS_CAPS_UNSUPPORTED = 10,\n\tWLAN_STATUS_REASSOC_NO_ASSOC = 11,\n\tWLAN_STATUS_ASSOC_DENIED_UNSPEC = 12,\n\tWLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13,\n\tWLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14,\n\tWLAN_STATUS_CHALLENGE_FAIL = 15,\n\tWLAN_STATUS_AUTH_TIMEOUT = 16,\n\tWLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17,\n\tWLAN_STATUS_ASSOC_DENIED_RATES = 18,\n\tWLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19,\n\tWLAN_STATUS_ASSOC_DENIED_NOPBCC = 20,\n\tWLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21,\n\tWLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22,\n\tWLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23,\n\tWLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24,\n\tWLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25,\n\tWLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26,\n\tWLAN_STATUS_ASSOC_REJECTED_TEMPORARILY = 30,\n\tWLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION = 31,\n\tWLAN_STATUS_INVALID_IE = 40,\n\tWLAN_STATUS_INVALID_GROUP_CIPHER = 41,\n\tWLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42,\n\tWLAN_STATUS_INVALID_AKMP = 43,\n\tWLAN_STATUS_UNSUPP_RSN_VERSION = 44,\n\tWLAN_STATUS_INVALID_RSN_IE_CAP = 45,\n\tWLAN_STATUS_CIPHER_SUITE_REJECTED = 46,\n\tWLAN_STATUS_UNSPECIFIED_QOS = 32,\n\tWLAN_STATUS_ASSOC_DENIED_NOBANDWIDTH = 33,\n\tWLAN_STATUS_ASSOC_DENIED_LOWACK = 34,\n\tWLAN_STATUS_ASSOC_DENIED_UNSUPP_QOS = 35,\n\tWLAN_STATUS_REQUEST_DECLINED = 37,\n\tWLAN_STATUS_INVALID_QOS_PARAM = 38,\n\tWLAN_STATUS_CHANGE_TSPEC = 39,\n\tWLAN_STATUS_WAIT_TS_DELAY = 47,\n\tWLAN_STATUS_NO_DIRECT_LINK = 48,\n\tWLAN_STATUS_STA_NOT_PRESENT = 49,\n\tWLAN_STATUS_STA_NOT_QSTA = 50,\n\tWLAN_STATUS_ANTI_CLOG_REQUIRED = 76,\n\tWLAN_STATUS_FCG_NOT_SUPP = 78,\n\tWLAN_STATUS_STA_NO_TBTT = 78,\n\tWLAN_STATUS_REJECTED_WITH_SUGGESTED_CHANGES = 39,\n\tWLAN_STATUS_REJECTED_FOR_DELAY_PERIOD = 47,\n\tWLAN_STATUS_REJECT_WITH_SCHEDULE = 83,\n\tWLAN_STATUS_PENDING_ADMITTING_FST_SESSION = 86,\n\tWLAN_STATUS_PERFORMING_FST_NOW = 87,\n\tWLAN_STATUS_PENDING_GAP_IN_BA_WINDOW = 88,\n\tWLAN_STATUS_REJECT_U_PID_SETTING = 89,\n\tWLAN_STATUS_REJECT_DSE_BAND = 96,\n\tWLAN_STATUS_DENIED_WITH_SUGGESTED_BAND_AND_CHANNEL = 99,\n\tWLAN_STATUS_DENIED_DUE_TO_SPECTRUM_MANAGEMENT = 103,\n\tWLAN_STATUS_FILS_AUTHENTICATION_FAILURE = 112,\n\tWLAN_STATUS_UNKNOWN_AUTHENTICATION_SERVER = 113,\n\tWLAN_STATUS_SAE_HASH_TO_ELEMENT = 126,\n\tWLAN_STATUS_SAE_PK = 127,\n\tWLAN_STATUS_DENIED_TID_TO_LINK_MAPPING = 133,\n\tWLAN_STATUS_PREF_TID_TO_LINK_MAPPING_SUGGESTED = 134,\n};\n\nenum ieee80211_sub_if_data_flags {\n\tIEEE80211_SDATA_ALLMULTI = 1,\n\tIEEE80211_SDATA_DONT_BRIDGE_PACKETS = 8,\n\tIEEE80211_SDATA_DISCONNECT_RESUME = 16,\n\tIEEE80211_SDATA_IN_DRIVER = 32,\n\tIEEE80211_SDATA_DISCONNECT_HW_RESTART = 64,\n};\n\nenum ieee80211_tdls_actioncode {\n\tWLAN_TDLS_SETUP_REQUEST = 0,\n\tWLAN_TDLS_SETUP_RESPONSE = 1,\n\tWLAN_TDLS_SETUP_CONFIRM = 2,\n\tWLAN_TDLS_TEARDOWN = 3,\n\tWLAN_TDLS_PEER_TRAFFIC_INDICATION = 4,\n\tWLAN_TDLS_CHANNEL_SWITCH_REQUEST = 5,\n\tWLAN_TDLS_CHANNEL_SWITCH_RESPONSE = 6,\n\tWLAN_TDLS_PEER_PSM_REQUEST = 7,\n\tWLAN_TDLS_PEER_PSM_RESPONSE = 8,\n\tWLAN_TDLS_PEER_TRAFFIC_RESPONSE = 9,\n\tWLAN_TDLS_DISCOVERY_REQUEST = 10,\n};\n\nenum ieee80211_timeout_interval_type {\n\tWLAN_TIMEOUT_REASSOC_DEADLINE = 1,\n\tWLAN_TIMEOUT_KEY_LIFETIME = 2,\n\tWLAN_TIMEOUT_ASSOC_COMEBACK = 3,\n};\n\nenum ieee80211_tpt_led_trigger_flags {\n\tIEEE80211_TPT_LEDTRIG_FL_RADIO = 1,\n\tIEEE80211_TPT_LEDTRIG_FL_WORK = 2,\n\tIEEE80211_TPT_LEDTRIG_FL_CONNECTED = 4,\n};\n\nenum ieee80211_twt_setup_cmd {\n\tTWT_SETUP_CMD_REQUEST = 0,\n\tTWT_SETUP_CMD_SUGGEST = 1,\n\tTWT_SETUP_CMD_DEMAND = 2,\n\tTWT_SETUP_CMD_GROUPING = 3,\n\tTWT_SETUP_CMD_ACCEPT = 4,\n\tTWT_SETUP_CMD_ALTERNATE = 5,\n\tTWT_SETUP_CMD_DICTATE = 6,\n\tTWT_SETUP_CMD_REJECT = 7,\n};\n\nenum ieee80211_tx_power_category_6ghz {\n\tIEEE80211_TPE_CAT_6GHZ_DEFAULT = 0,\n\tIEEE80211_TPE_CAT_6GHZ_SUBORDINATE = 1,\n};\n\nenum ieee80211_tx_power_intrpt_type {\n\tIEEE80211_TPE_LOCAL_EIRP = 0,\n\tIEEE80211_TPE_LOCAL_EIRP_PSD = 1,\n\tIEEE80211_TPE_REG_CLIENT_EIRP = 2,\n\tIEEE80211_TPE_REG_CLIENT_EIRP_PSD = 3,\n};\n\nenum ieee80211_unprotected_wnm_actioncode {\n\tWLAN_UNPROTECTED_WNM_ACTION_TIM = 0,\n\tWLAN_UNPROTECTED_WNM_ACTION_TIMING_MEASUREMENT_RESPONSE = 1,\n};\n\nenum ieee80211_vht_actioncode {\n\tWLAN_VHT_ACTION_COMPRESSED_BF = 0,\n\tWLAN_VHT_ACTION_GROUPID_MGMT = 1,\n\tWLAN_VHT_ACTION_OPMODE_NOTIF = 2,\n};\n\nenum ieee80211_vht_chanwidth {\n\tIEEE80211_VHT_CHANWIDTH_USE_HT = 0,\n\tIEEE80211_VHT_CHANWIDTH_80MHZ = 1,\n\tIEEE80211_VHT_CHANWIDTH_160MHZ = 2,\n\tIEEE80211_VHT_CHANWIDTH_80P80MHZ = 3,\n};\n\nenum ieee80211_vht_mcs_support {\n\tIEEE80211_VHT_MCS_SUPPORT_0_7 = 0,\n\tIEEE80211_VHT_MCS_SUPPORT_0_8 = 1,\n\tIEEE80211_VHT_MCS_SUPPORT_0_9 = 2,\n\tIEEE80211_VHT_MCS_NOT_SUPPORTED = 3,\n};\n\nenum ieee80211_vht_opmode_bits {\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK = 3,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ = 0,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ = 1,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_80MHZ = 2,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_160MHZ = 3,\n\tIEEE80211_OPMODE_NOTIF_BW_160_80P80 = 4,\n\tIEEE80211_OPMODE_NOTIF_RX_NSS_MASK = 112,\n\tIEEE80211_OPMODE_NOTIF_RX_NSS_SHIFT = 4,\n\tIEEE80211_OPMODE_NOTIF_RX_NSS_TYPE_BF = 128,\n};\n\nenum ieee80211_vif_flags {\n\tIEEE80211_VIF_BEACON_FILTER = 1,\n\tIEEE80211_VIF_SUPPORTS_CQM_RSSI = 2,\n\tIEEE80211_VIF_SUPPORTS_UAPSD = 4,\n\tIEEE80211_VIF_GET_NOA_UPDATE = 8,\n\tIEEE80211_VIF_EML_ACTIVE = 16,\n\tIEEE80211_VIF_IGNORE_OFDMA_WIDER_BW = 32,\n\tIEEE80211_VIF_REMOVE_AP_AFTER_DISASSOC = 64,\n};\n\nenum in6_addr_gen_mode {\n\tIN6_ADDR_GEN_MODE_EUI64 = 0,\n\tIN6_ADDR_GEN_MODE_NONE = 1,\n\tIN6_ADDR_GEN_MODE_STABLE_PRIVACY = 2,\n\tIN6_ADDR_GEN_MODE_RANDOM = 3,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum insn_mmio_type {\n\tINSN_MMIO_DECODE_FAILED = 0,\n\tINSN_MMIO_WRITE = 1,\n\tINSN_MMIO_WRITE_IMM = 2,\n\tINSN_MMIO_READ = 3,\n\tINSN_MMIO_READ_ZERO_EXTEND = 4,\n\tINSN_MMIO_READ_SIGN_EXTEND = 5,\n\tINSN_MMIO_MOVS = 6,\n};\n\nenum insn_mode {\n\tINSN_MODE_32 = 0,\n\tINSN_MODE_64 = 1,\n\tINSN_MODE_KERN = 2,\n\tINSN_NUM_MODES = 3,\n};\n\nenum insn_type {\n\tCALL = 0,\n\tNOP = 1,\n\tJMP = 2,\n\tRET = 3,\n\tJCC = 4,\n};\n\nenum intel_backlight_type {\n\tINTEL_BACKLIGHT_PMIC = 0,\n\tINTEL_BACKLIGHT_LPSS = 1,\n\tINTEL_BACKLIGHT_DISPLAY_DDI = 2,\n\tINTEL_BACKLIGHT_DSI_DCS = 3,\n\tINTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE = 4,\n\tINTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE = 5,\n};\n\nenum intel_bootrom_load_status {\n\tINTEL_BOOTROM_STATUS_NO_KEY_FOUND = 19,\n\tINTEL_BOOTROM_STATUS_AES_PROD_KEY_FOUND = 26,\n\tINTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE = 43,\n\tINTEL_BOOTROM_STATUS_RSA_FAILED = 80,\n\tINTEL_BOOTROM_STATUS_PAVPC_FAILED = 115,\n\tINTEL_BOOTROM_STATUS_WOPCM_FAILED = 116,\n\tINTEL_BOOTROM_STATUS_LOADLOC_FAILED = 117,\n\tINTEL_BOOTROM_STATUS_JUMP_PASSED = 118,\n\tINTEL_BOOTROM_STATUS_JUMP_FAILED = 119,\n\tINTEL_BOOTROM_STATUS_RC6CTXCONFIG_FAILED = 121,\n\tINTEL_BOOTROM_STATUS_MPUMAP_INCORRECT = 122,\n\tINTEL_BOOTROM_STATUS_EXCEPTION = 126,\n};\n\nenum intel_broadcast_rgb {\n\tINTEL_BROADCAST_RGB_AUTO = 0,\n\tINTEL_BROADCAST_RGB_FULL = 1,\n\tINTEL_BROADCAST_RGB_LIMITED = 2,\n};\n\nenum intel_color_block {\n\tINTEL_PLANE_CB_PRE_CSC_LUT = 0,\n\tINTEL_PLANE_CB_CSC = 1,\n\tINTEL_PLANE_CB_POST_CSC_LUT = 2,\n\tINTEL_PLANE_CB_3DLUT = 3,\n\tINTEL_CB_MAX = 4,\n};\n\nenum intel_cpu_type {\n\tINTEL_CPU_TYPE_UNKNOWN = 0,\n\tINTEL_CPU_TYPE_ATOM = 32,\n\tINTEL_CPU_TYPE_CORE = 64,\n};\n\nenum intel_ddb_partitioning {\n\tINTEL_DDB_PART_1_2 = 0,\n\tINTEL_DDB_PART_5_6 = 1,\n};\n\nenum intel_display_power_domain {\n\tPOWER_DOMAIN_DISPLAY_CORE = 0,\n\tPOWER_DOMAIN_PIPE_A = 1,\n\tPOWER_DOMAIN_PIPE_B = 2,\n\tPOWER_DOMAIN_PIPE_C = 3,\n\tPOWER_DOMAIN_PIPE_D = 4,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_A = 5,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_B = 6,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_C = 7,\n\tPOWER_DOMAIN_PIPE_PANEL_FITTER_D = 8,\n\tPOWER_DOMAIN_TRANSCODER_A = 9,\n\tPOWER_DOMAIN_TRANSCODER_B = 10,\n\tPOWER_DOMAIN_TRANSCODER_C = 11,\n\tPOWER_DOMAIN_TRANSCODER_D = 12,\n\tPOWER_DOMAIN_TRANSCODER_EDP = 13,\n\tPOWER_DOMAIN_TRANSCODER_DSI_A = 14,\n\tPOWER_DOMAIN_TRANSCODER_DSI_C = 15,\n\tPOWER_DOMAIN_TRANSCODER_VDSC_PW2 = 16,\n\tPOWER_DOMAIN_PORT_DDI_LANES_A = 17,\n\tPOWER_DOMAIN_PORT_DDI_LANES_B = 18,\n\tPOWER_DOMAIN_PORT_DDI_LANES_C = 19,\n\tPOWER_DOMAIN_PORT_DDI_LANES_D = 20,\n\tPOWER_DOMAIN_PORT_DDI_LANES_E = 21,\n\tPOWER_DOMAIN_PORT_DDI_LANES_F = 22,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC1 = 23,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC2 = 24,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC3 = 25,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC4 = 26,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC5 = 27,\n\tPOWER_DOMAIN_PORT_DDI_LANES_TC6 = 28,\n\tPOWER_DOMAIN_PORT_DDI_IO_A = 29,\n\tPOWER_DOMAIN_PORT_DDI_IO_B = 30,\n\tPOWER_DOMAIN_PORT_DDI_IO_C = 31,\n\tPOWER_DOMAIN_PORT_DDI_IO_D = 32,\n\tPOWER_DOMAIN_PORT_DDI_IO_E = 33,\n\tPOWER_DOMAIN_PORT_DDI_IO_F = 34,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC1 = 35,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC2 = 36,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC3 = 37,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC4 = 38,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC5 = 39,\n\tPOWER_DOMAIN_PORT_DDI_IO_TC6 = 40,\n\tPOWER_DOMAIN_PORT_DSI = 41,\n\tPOWER_DOMAIN_PORT_CRT = 42,\n\tPOWER_DOMAIN_PORT_OTHER = 43,\n\tPOWER_DOMAIN_VGA = 44,\n\tPOWER_DOMAIN_AUDIO_MMIO = 45,\n\tPOWER_DOMAIN_AUDIO_PLAYBACK = 46,\n\tPOWER_DOMAIN_AUX_IO_A = 47,\n\tPOWER_DOMAIN_AUX_IO_B = 48,\n\tPOWER_DOMAIN_AUX_IO_C = 49,\n\tPOWER_DOMAIN_AUX_IO_D = 50,\n\tPOWER_DOMAIN_AUX_IO_E = 51,\n\tPOWER_DOMAIN_AUX_IO_F = 52,\n\tPOWER_DOMAIN_AUX_A = 53,\n\tPOWER_DOMAIN_AUX_B = 54,\n\tPOWER_DOMAIN_AUX_C = 55,\n\tPOWER_DOMAIN_AUX_D = 56,\n\tPOWER_DOMAIN_AUX_E = 57,\n\tPOWER_DOMAIN_AUX_F = 58,\n\tPOWER_DOMAIN_AUX_USBC1 = 59,\n\tPOWER_DOMAIN_AUX_USBC2 = 60,\n\tPOWER_DOMAIN_AUX_USBC3 = 61,\n\tPOWER_DOMAIN_AUX_USBC4 = 62,\n\tPOWER_DOMAIN_AUX_USBC5 = 63,\n\tPOWER_DOMAIN_AUX_USBC6 = 64,\n\tPOWER_DOMAIN_AUX_TBT1 = 65,\n\tPOWER_DOMAIN_AUX_TBT2 = 66,\n\tPOWER_DOMAIN_AUX_TBT3 = 67,\n\tPOWER_DOMAIN_AUX_TBT4 = 68,\n\tPOWER_DOMAIN_AUX_TBT5 = 69,\n\tPOWER_DOMAIN_AUX_TBT6 = 70,\n\tPOWER_DOMAIN_GMBUS = 71,\n\tPOWER_DOMAIN_GT_IRQ = 72,\n\tPOWER_DOMAIN_DC_OFF = 73,\n\tPOWER_DOMAIN_TC_COLD_OFF = 74,\n\tPOWER_DOMAIN_INIT = 75,\n\tPOWER_DOMAIN_NUM = 76,\n\tPOWER_DOMAIN_INVALID = 76,\n};\n\nenum intel_display_wa {\n\tINTEL_DISPLAY_WA_13012396614 = 0,\n\tINTEL_DISPLAY_WA_14011503117 = 1,\n\tINTEL_DISPLAY_WA_14025769978 = 2,\n\tINTEL_DISPLAY_WA_15018326506 = 3,\n\tINTEL_DISPLAY_WA_16023588340 = 4,\n\tINTEL_DISPLAY_WA_16025573575 = 5,\n\tINTEL_DISPLAY_WA_22014263786 = 6,\n};\n\nenum intel_dmc_id {\n\tDMC_FW_MAIN = 0,\n\tDMC_FW_PIPEA = 1,\n\tDMC_FW_PIPEB = 2,\n\tDMC_FW_PIPEC = 3,\n\tDMC_FW_PIPED = 4,\n\tDMC_FW_MAX = 5,\n};\n\nenum intel_dp_aux_backlight_modparam {\n\tINTEL_DP_AUX_BACKLIGHT_AUTO = -1,\n\tINTEL_DP_AUX_BACKLIGHT_OFF = 0,\n\tINTEL_DP_AUX_BACKLIGHT_ON = 1,\n\tINTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,\n\tINTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,\n};\n\nenum intel_dpll_id {\n\tDPLL_ID_PRIVATE = -1,\n\tDPLL_ID_PCH_PLL_A = 0,\n\tDPLL_ID_PCH_PLL_B = 1,\n\tDPLL_ID_WRPLL1 = 0,\n\tDPLL_ID_WRPLL2 = 1,\n\tDPLL_ID_SPLL = 2,\n\tDPLL_ID_LCPLL_810 = 3,\n\tDPLL_ID_LCPLL_1350 = 4,\n\tDPLL_ID_LCPLL_2700 = 5,\n\tDPLL_ID_SKL_DPLL0 = 0,\n\tDPLL_ID_SKL_DPLL1 = 1,\n\tDPLL_ID_SKL_DPLL2 = 2,\n\tDPLL_ID_SKL_DPLL3 = 3,\n\tDPLL_ID_ICL_DPLL0 = 0,\n\tDPLL_ID_ICL_DPLL1 = 1,\n\tDPLL_ID_EHL_DPLL4 = 2,\n\tDPLL_ID_ICL_TBTPLL = 2,\n\tDPLL_ID_ICL_MGPLL1 = 3,\n\tDPLL_ID_ICL_MGPLL2 = 4,\n\tDPLL_ID_ICL_MGPLL3 = 5,\n\tDPLL_ID_ICL_MGPLL4 = 6,\n\tDPLL_ID_TGL_MGPLL5 = 7,\n\tDPLL_ID_TGL_MGPLL6 = 8,\n\tDPLL_ID_DG1_DPLL0 = 0,\n\tDPLL_ID_DG1_DPLL1 = 1,\n\tDPLL_ID_DG1_DPLL2 = 2,\n\tDPLL_ID_DG1_DPLL3 = 3,\n};\n\nenum intel_dram_type {\n\tINTEL_DRAM_UNKNOWN = 0,\n\tINTEL_DRAM_DDR2 = 1,\n\tINTEL_DRAM_DDR3 = 2,\n\tINTEL_DRAM_DDR4 = 3,\n\tINTEL_DRAM_LPDDR3 = 4,\n\tINTEL_DRAM_LPDDR4 = 5,\n\tINTEL_DRAM_DDR5 = 6,\n\tINTEL_DRAM_LPDDR5 = 7,\n\tINTEL_DRAM_GDDR = 8,\n\tINTEL_DRAM_GDDR_ECC = 9,\n\t__INTEL_DRAM_TYPE_MAX = 10,\n};\n\nenum intel_dsb_id {\n\tINTEL_DSB_0 = 0,\n\tINTEL_DSB_1 = 1,\n\tINTEL_DSB_2 = 2,\n\tI915_MAX_DSBS = 3,\n};\n\nenum intel_engine_id {\n\tRCS0 = 0,\n\tBCS0 = 1,\n\tBCS1 = 2,\n\tBCS2 = 3,\n\tBCS3 = 4,\n\tBCS4 = 5,\n\tBCS5 = 6,\n\tBCS6 = 7,\n\tBCS7 = 8,\n\tBCS8 = 9,\n\tVCS0 = 10,\n\tVCS1 = 11,\n\tVCS2 = 12,\n\tVCS3 = 13,\n\tVCS4 = 14,\n\tVCS5 = 15,\n\tVCS6 = 16,\n\tVCS7 = 17,\n\tVECS0 = 18,\n\tVECS1 = 19,\n\tVECS2 = 20,\n\tVECS3 = 21,\n\tCCS0 = 22,\n\tCCS1 = 23,\n\tCCS2 = 24,\n\tCCS3 = 25,\n\tGSC0 = 26,\n\tI915_NUM_ENGINES = 27,\n};\n\nenum intel_excl_state_type {\n\tINTEL_EXCL_UNUSED = 0,\n\tINTEL_EXCL_SHARED = 1,\n\tINTEL_EXCL_EXCLUSIVE = 2,\n};\n\nenum intel_fbc_id {\n\tINTEL_FBC_A = 0,\n\tINTEL_FBC_B = 1,\n\tINTEL_FBC_C = 2,\n\tINTEL_FBC_D = 3,\n\tI915_MAX_FBCS = 4,\n};\n\nenum intel_flipq_id {\n\tINTEL_FLIPQ_PLANE_1 = 0,\n\tINTEL_FLIPQ_PLANE_2 = 1,\n\tINTEL_FLIPQ_PLANE_3 = 2,\n\tINTEL_FLIPQ_GENERAL = 3,\n\tINTEL_FLIPQ_FAST = 4,\n\tMAX_INTEL_FLIPQ = 5,\n};\n\nenum intel_gsc_proxy_type {\n\tGSC_PROXY_MSG_TYPE_PROXY_INVALID = 0,\n\tGSC_PROXY_MSG_TYPE_PROXY_QUERY = 1,\n\tGSC_PROXY_MSG_TYPE_PROXY_PAYLOAD = 2,\n\tGSC_PROXY_MSG_TYPE_PROXY_END = 3,\n\tGSC_PROXY_MSG_TYPE_PROXY_NOTIFICATION = 4,\n};\n\nenum intel_gt_scratch_field {\n\tINTEL_GT_SCRATCH_FIELD_DEFAULT = 0,\n\tINTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,\n\tINTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,\n};\n\nenum intel_gt_sysfs_op {\n\tINTEL_GT_SYSFS_MIN = 0,\n\tINTEL_GT_SYSFS_MAX = 1,\n};\n\nenum intel_gt_type {\n\tGT_PRIMARY = 0,\n\tGT_TILE = 1,\n\tGT_MEDIA = 2,\n};\n\nenum intel_guc_action {\n\tINTEL_GUC_ACTION_DEFAULT = 0,\n\tINTEL_GUC_ACTION_REQUEST_PREEMPTION = 2,\n\tINTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 3,\n\tINTEL_GUC_ACTION_ALLOCATE_DOORBELL = 16,\n\tINTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 32,\n\tINTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 48,\n\tINTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 64,\n\tINTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 770,\n\tINTEL_GUC_ACTION_ENTER_S_STATE = 1281,\n\tINTEL_GUC_ACTION_EXIT_S_STATE = 1282,\n\tINTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 1286,\n\tINTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV = 1289,\n\tINTEL_GUC_ACTION_SCHED_CONTEXT = 4096,\n\tINTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 4097,\n\tINTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 4098,\n\tINTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 4099,\n\tINTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 4100,\n\tINTEL_GUC_ACTION_V69_SET_CONTEXT_PRIORITY = 4101,\n\tINTEL_GUC_ACTION_V69_SET_CONTEXT_EXECUTION_QUANTUM = 4102,\n\tINTEL_GUC_ACTION_V69_SET_CONTEXT_PREEMPTION_TIMEOUT = 4103,\n\tINTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 4104,\n\tINTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 4105,\n\tINTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 4107,\n\tINTEL_GUC_ACTION_SETUP_PC_GUCRC = 12292,\n\tINTEL_GUC_ACTION_AUTHENTICATE_HUC = 16384,\n\tINTEL_GUC_ACTION_GET_HWCONFIG = 16640,\n\tINTEL_GUC_ACTION_REGISTER_CONTEXT = 17666,\n\tINTEL_GUC_ACTION_DEREGISTER_CONTEXT = 17667,\n\tINTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 17920,\n\tINTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 17921,\n\tINTEL_GUC_ACTION_CLIENT_SOFT_RESET = 21767,\n\tINTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 21770,\n\tINTEL_GUC_ACTION_TLB_INVALIDATION = 28672,\n\tINTEL_GUC_ACTION_TLB_INVALIDATION_DONE = 28673,\n\tINTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 32770,\n\tINTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 32771,\n\tINTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 32772,\n\tINTEL_GUC_ACTION_NOTIFY_EXCEPTION = 32773,\n\tINTEL_GUC_ACTION_LIMIT = 32774,\n};\n\nenum intel_guc_load_status {\n\tINTEL_GUC_LOAD_STATUS_DEFAULT = 0,\n\tINTEL_GUC_LOAD_STATUS_START = 1,\n\tINTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH = 2,\n\tINTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH = 3,\n\tINTEL_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE = 4,\n\tINTEL_GUC_LOAD_STATUS_HWCONFIG_START = 5,\n\tINTEL_GUC_LOAD_STATUS_HWCONFIG_DONE = 6,\n\tINTEL_GUC_LOAD_STATUS_HWCONFIG_ERROR = 7,\n\tINTEL_GUC_LOAD_STATUS_GDT_DONE = 16,\n\tINTEL_GUC_LOAD_STATUS_IDT_DONE = 32,\n\tINTEL_GUC_LOAD_STATUS_LAPIC_DONE = 48,\n\tINTEL_GUC_LOAD_STATUS_GUCINT_DONE = 64,\n\tINTEL_GUC_LOAD_STATUS_DPC_READY = 80,\n\tINTEL_GUC_LOAD_STATUS_DPC_ERROR = 96,\n\tINTEL_GUC_LOAD_STATUS_EXCEPTION = 112,\n\tINTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID = 113,\n\tINTEL_GUC_LOAD_STATUS_PXP_TEARDOWN_CTRL_ENABLED = 114,\n\tINTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_START = 115,\n\tINTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID = 115,\n\tINTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID = 116,\n\tINTEL_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR = 117,\n\tINTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_END = 118,\n\tINTEL_GUC_LOAD_STATUS_READY = 240,\n};\n\nenum intel_guc_rc_options {\n\tINTEL_GUCRC_HOST_CONTROL = 0,\n\tINTEL_GUCRC_FIRMWARE_CONTROL = 1,\n};\n\nenum intel_guc_recv_message {\n\tINTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = 2,\n\tINTEL_GUC_RECV_MSG_EXCEPTION = 1073741824,\n};\n\nenum intel_guc_state_capture_event_status {\n\tINTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0,\n\tINTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 1,\n};\n\nenum intel_guc_tlb_inval_mode {\n\tINTEL_GUC_TLB_INVAL_MODE_HEAVY = 0,\n\tINTEL_GUC_TLB_INVAL_MODE_LITE = 1,\n};\n\nenum intel_guc_tlb_invalidation_type {\n\tINTEL_GUC_TLB_INVAL_ENGINES = 0,\n\tINTEL_GUC_TLB_INVAL_GUC = 3,\n};\n\nenum intel_hotplug_state {\n\tINTEL_HOTPLUG_UNCHANGED = 0,\n\tINTEL_HOTPLUG_CHANGED = 1,\n\tINTEL_HOTPLUG_RETRY = 2,\n};\n\nenum intel_huc_authentication_type {\n\tINTEL_HUC_AUTH_BY_GUC = 0,\n\tINTEL_HUC_AUTH_BY_GSC = 1,\n\tINTEL_HUC_AUTH_MAX_MODES = 2,\n};\n\nenum intel_huc_delayed_load_status {\n\tINTEL_HUC_WAITING_ON_GSC = 0,\n\tINTEL_HUC_WAITING_ON_PXP = 1,\n\tINTEL_HUC_DELAYED_LOAD_ERROR = 2,\n};\n\nenum intel_memory_type {\n\tINTEL_MEMORY_SYSTEM = 0,\n\tINTEL_MEMORY_LOCAL = 1,\n\tINTEL_MEMORY_STOLEN_SYSTEM = 2,\n\tINTEL_MEMORY_STOLEN_LOCAL = 3,\n\tINTEL_MEMORY_MOCK = 4,\n};\n\nenum intel_native_id {\n\tINTEL_ATOM_CMT_NATIVE_ID = 2,\n\tINTEL_ATOM_SKT_NATIVE_ID = 3,\n};\n\nenum intel_output_format {\n\tINTEL_OUTPUT_FORMAT_RGB = 0,\n\tINTEL_OUTPUT_FORMAT_YCBCR420 = 1,\n\tINTEL_OUTPUT_FORMAT_YCBCR444 = 2,\n};\n\nenum intel_output_type {\n\tINTEL_OUTPUT_UNUSED = 0,\n\tINTEL_OUTPUT_ANALOG = 1,\n\tINTEL_OUTPUT_DVO = 2,\n\tINTEL_OUTPUT_SDVO = 3,\n\tINTEL_OUTPUT_LVDS = 4,\n\tINTEL_OUTPUT_TVOUT = 5,\n\tINTEL_OUTPUT_HDMI = 6,\n\tINTEL_OUTPUT_DP = 7,\n\tINTEL_OUTPUT_EDP = 8,\n\tINTEL_OUTPUT_DSI = 9,\n\tINTEL_OUTPUT_DDI = 10,\n\tINTEL_OUTPUT_DP_MST = 11,\n};\n\nenum intel_panel_replay_dsc_support {\n\tINTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED = 0,\n\tINTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY = 1,\n\tINTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE = 2,\n};\n\nenum intel_pch {\n\tPCH_NOP = -1,\n\tPCH_NONE = 0,\n\tPCH_IBX = 1,\n\tPCH_CPT = 2,\n\tPCH_LPT_H = 3,\n\tPCH_LPT_LP = 4,\n\tPCH_SPT = 5,\n\tPCH_CNP = 6,\n\tPCH_ICP = 7,\n\tPCH_TGP = 8,\n\tPCH_ADP = 9,\n\tPCH_DG1 = 1024,\n\tPCH_DG2 = 1025,\n\tPCH_MTL = 1026,\n\tPCH_LNL = 1027,\n};\n\nenum intel_pipe_crc_source {\n\tINTEL_PIPE_CRC_SOURCE_NONE = 0,\n\tINTEL_PIPE_CRC_SOURCE_PLANE1 = 1,\n\tINTEL_PIPE_CRC_SOURCE_PLANE2 = 2,\n\tINTEL_PIPE_CRC_SOURCE_PLANE3 = 3,\n\tINTEL_PIPE_CRC_SOURCE_PLANE4 = 4,\n\tINTEL_PIPE_CRC_SOURCE_PLANE5 = 5,\n\tINTEL_PIPE_CRC_SOURCE_PLANE6 = 6,\n\tINTEL_PIPE_CRC_SOURCE_PLANE7 = 7,\n\tINTEL_PIPE_CRC_SOURCE_PIPE = 8,\n\tINTEL_PIPE_CRC_SOURCE_TV = 9,\n\tINTEL_PIPE_CRC_SOURCE_DP_B = 10,\n\tINTEL_PIPE_CRC_SOURCE_DP_C = 11,\n\tINTEL_PIPE_CRC_SOURCE_DP_D = 12,\n\tINTEL_PIPE_CRC_SOURCE_AUTO = 13,\n\tINTEL_PIPE_CRC_SOURCE_MAX = 14,\n};\n\nenum intel_platform {\n\tINTEL_PLATFORM_UNINITIALIZED = 0,\n\tINTEL_I830 = 1,\n\tINTEL_I845G = 2,\n\tINTEL_I85X = 3,\n\tINTEL_I865G = 4,\n\tINTEL_I915G = 5,\n\tINTEL_I915GM = 6,\n\tINTEL_I945G = 7,\n\tINTEL_I945GM = 8,\n\tINTEL_G33 = 9,\n\tINTEL_PINEVIEW = 10,\n\tINTEL_I965G = 11,\n\tINTEL_I965GM = 12,\n\tINTEL_G45 = 13,\n\tINTEL_GM45 = 14,\n\tINTEL_IRONLAKE = 15,\n\tINTEL_SANDYBRIDGE = 16,\n\tINTEL_IVYBRIDGE = 17,\n\tINTEL_VALLEYVIEW = 18,\n\tINTEL_HASWELL = 19,\n\tINTEL_BROADWELL = 20,\n\tINTEL_CHERRYVIEW = 21,\n\tINTEL_SKYLAKE = 22,\n\tINTEL_BROXTON = 23,\n\tINTEL_KABYLAKE = 24,\n\tINTEL_GEMINILAKE = 25,\n\tINTEL_COFFEELAKE = 26,\n\tINTEL_COMETLAKE = 27,\n\tINTEL_ICELAKE = 28,\n\tINTEL_ELKHARTLAKE = 29,\n\tINTEL_JASPERLAKE = 30,\n\tINTEL_TIGERLAKE = 31,\n\tINTEL_ROCKETLAKE = 32,\n\tINTEL_DG1 = 33,\n\tINTEL_ALDERLAKE_S = 34,\n\tINTEL_ALDERLAKE_P = 35,\n\tINTEL_DG2 = 36,\n\tINTEL_METEORLAKE = 37,\n\tINTEL_MAX_PLATFORMS = 38,\n};\n\nenum intel_ppgtt_type {\n\tINTEL_PPGTT_NONE = 0,\n\tINTEL_PPGTT_ALIASING = 1,\n\tINTEL_PPGTT_FULL = 2,\n};\n\nenum intel_quirk_id {\n\tQUIRK_BACKLIGHT_PRESENT = 0,\n\tQUIRK_INCREASE_DDI_DISABLED_TIME = 1,\n\tQUIRK_INCREASE_T12_DELAY = 2,\n\tQUIRK_INVERT_BRIGHTNESS = 3,\n\tQUIRK_LVDS_SSC_DISABLE = 4,\n\tQUIRK_NO_PPS_BACKLIGHT_POWER_HOOK = 5,\n\tQUIRK_FW_SYNC_LEN = 6,\n\tQUIRK_EDP_LIMIT_RATE_HBR2 = 7,\n};\n\nenum intel_rc6_res_type {\n\tINTEL_RC6_RES_RC6_LOCKED = 0,\n\tINTEL_RC6_RES_RC6 = 1,\n\tINTEL_RC6_RES_RC6p = 2,\n\tINTEL_RC6_RES_RC6pp = 3,\n\tINTEL_RC6_RES_MAX = 4,\n\tINTEL_RC6_RES_VLV_MEDIA = 2,\n};\n\nenum intel_region_id {\n\tINTEL_REGION_SMEM = 0,\n\tINTEL_REGION_LMEM_0 = 1,\n\tINTEL_REGION_LMEM_1 = 2,\n\tINTEL_REGION_LMEM_2 = 3,\n\tINTEL_REGION_LMEM_3 = 4,\n\tINTEL_REGION_STOLEN_SMEM = 5,\n\tINTEL_REGION_STOLEN_LMEM = 6,\n\tINTEL_REGION_UNKNOWN = 7,\n};\n\nenum intel_sbi_destination {\n\tSBI_ICLK = 0,\n\tSBI_MPHY = 1,\n};\n\nenum intel_steering_type {\n\tL3BANK = 0,\n\tMSLICE = 1,\n\tLNCF = 2,\n\tGAM = 3,\n\tDSS = 4,\n\tOADDRM = 5,\n\tINSTANCE0 = 6,\n\tNUM_STEERING_TYPES = 7,\n};\n\nenum intel_step {\n\tSTEP_NONE = 0,\n\tSTEP_A0 = 1,\n\tSTEP_A1 = 2,\n\tSTEP_A2 = 3,\n\tSTEP_A3 = 4,\n\tSTEP_B0 = 5,\n\tSTEP_B1 = 6,\n\tSTEP_B2 = 7,\n\tSTEP_B3 = 8,\n\tSTEP_C0 = 9,\n\tSTEP_C1 = 10,\n\tSTEP_C2 = 11,\n\tSTEP_C3 = 12,\n\tSTEP_D0 = 13,\n\tSTEP_D1 = 14,\n\tSTEP_D2 = 15,\n\tSTEP_D3 = 16,\n\tSTEP_E0 = 17,\n\tSTEP_E1 = 18,\n\tSTEP_E2 = 19,\n\tSTEP_E3 = 20,\n\tSTEP_F0 = 21,\n\tSTEP_F1 = 22,\n\tSTEP_F2 = 23,\n\tSTEP_F3 = 24,\n\tSTEP_G0 = 25,\n\tSTEP_G1 = 26,\n\tSTEP_G2 = 27,\n\tSTEP_G3 = 28,\n\tSTEP_H0 = 29,\n\tSTEP_H1 = 30,\n\tSTEP_H2 = 31,\n\tSTEP_H3 = 32,\n\tSTEP_I0 = 33,\n\tSTEP_I1 = 34,\n\tSTEP_I2 = 35,\n\tSTEP_I3 = 36,\n\tSTEP_J0 = 37,\n\tSTEP_J1 = 38,\n\tSTEP_J2 = 39,\n\tSTEP_J3 = 40,\n\tSTEP_FUTURE = 41,\n\tSTEP_FOREVER = 42,\n};\n\nenum intel_submission_method {\n\tINTEL_SUBMISSION_RING = 0,\n\tINTEL_SUBMISSION_ELSP = 1,\n\tINTEL_SUBMISSION_GUC = 2,\n};\n\nenum intel_tc_pin_assignment {\n\tINTEL_TC_PIN_ASSIGNMENT_NONE = 0,\n\tINTEL_TC_PIN_ASSIGNMENT_A = 1,\n\tINTEL_TC_PIN_ASSIGNMENT_B = 2,\n\tINTEL_TC_PIN_ASSIGNMENT_C = 3,\n\tINTEL_TC_PIN_ASSIGNMENT_D = 4,\n\tINTEL_TC_PIN_ASSIGNMENT_E = 5,\n\tINTEL_TC_PIN_ASSIGNMENT_F = 6,\n};\n\nenum intel_uc_fw_status {\n\tINTEL_UC_FIRMWARE_NOT_SUPPORTED = -1,\n\tINTEL_UC_FIRMWARE_UNINITIALIZED = 0,\n\tINTEL_UC_FIRMWARE_DISABLED = 1,\n\tINTEL_UC_FIRMWARE_SELECTED = 2,\n\tINTEL_UC_FIRMWARE_MISSING = 3,\n\tINTEL_UC_FIRMWARE_ERROR = 4,\n\tINTEL_UC_FIRMWARE_AVAILABLE = 5,\n\tINTEL_UC_FIRMWARE_INIT_FAIL = 6,\n\tINTEL_UC_FIRMWARE_LOADABLE = 7,\n\tINTEL_UC_FIRMWARE_LOAD_FAIL = 8,\n\tINTEL_UC_FIRMWARE_TRANSFERRED = 9,\n\tINTEL_UC_FIRMWARE_RUNNING = 10,\n};\n\nenum intel_uc_fw_type {\n\tINTEL_UC_FW_TYPE_GUC = 0,\n\tINTEL_UC_FW_TYPE_HUC = 1,\n\tINTEL_UC_FW_TYPE_GSC = 2,\n};\n\nenum intercept_words {\n\tINTERCEPT_CR = 0,\n\tINTERCEPT_DR = 1,\n\tINTERCEPT_EXCEPTION = 2,\n\tINTERCEPT_WORD3 = 3,\n\tINTERCEPT_WORD4 = 4,\n\tINTERCEPT_WORD5 = 5,\n\tMAX_INTERCEPT = 6,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioam6_event_attr {\n\tIOAM6_EVENT_ATTR_UNSPEC = 0,\n\tIOAM6_EVENT_ATTR_TRACE_NAMESPACE = 1,\n\tIOAM6_EVENT_ATTR_TRACE_NODELEN = 2,\n\tIOAM6_EVENT_ATTR_TRACE_TYPE = 3,\n\tIOAM6_EVENT_ATTR_TRACE_DATA = 4,\n\t__IOAM6_EVENT_ATTR_MAX = 5,\n};\n\nenum ioam6_event_type {\n\tIOAM6_EVENT_UNSPEC = 0,\n\tIOAM6_EVENT_TRACE = 1,\n};\n\nenum ioapic_domain_type {\n\tIOAPIC_DOMAIN_INVALID = 0,\n\tIOAPIC_DOMAIN_LEGACY = 1,\n\tIOAPIC_DOMAIN_STRICT = 2,\n\tIOAPIC_DOMAIN_DYNAMIC = 3,\n};\n\nenum ioc_running {\n\tIOC_IDLE = 0,\n\tIOC_RUNNING = 1,\n\tIOC_STOP = 2,\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_NOEXEC = 1,\n\tIOMMU_CAP_PRE_BOOT_PROTECTION = 2,\n\tIOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3,\n\tIOMMU_CAP_DEFERRED_FLUSH = 4,\n\tIOMMU_CAP_DIRTY_TRACKING = 5,\n};\n\nenum iommu_dma_queue_type {\n\tIOMMU_DMA_OPTS_PER_CPU_QUEUE = 0,\n\tIOMMU_DMA_OPTS_SINGLE_QUEUE = 1,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum iommu_fault_type {\n\tIOMMU_FAULT_PAGE_REQ = 1,\n};\n\nenum iommu_hw_info_type {\n\tIOMMU_HW_INFO_TYPE_NONE = 0,\n\tIOMMU_HW_INFO_TYPE_DEFAULT = 0,\n\tIOMMU_HW_INFO_TYPE_INTEL_VTD = 1,\n\tIOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,\n\tIOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,\n\tIOMMU_HW_INFO_TYPE_AMD = 4,\n};\n\nenum iommu_hw_info_vtd_flags {\n\tIOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1,\n};\n\nenum iommu_hw_queue_type {\n\tIOMMU_HW_QUEUE_TYPE_DEFAULT = 0,\n\tIOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,\n};\n\nenum iommu_hwpt_data_type {\n\tIOMMU_HWPT_DATA_NONE = 0,\n\tIOMMU_HWPT_DATA_VTD_S1 = 1,\n\tIOMMU_HWPT_DATA_ARM_SMMUV3 = 2,\n\tIOMMU_HWPT_DATA_AMD_GUEST = 3,\n};\n\nenum iommu_hwpt_invalidate_data_type {\n\tIOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0,\n\tIOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1,\n};\n\nenum iommu_hwpt_vtd_s1_flags {\n\tIOMMU_VTD_S1_SRE = 1,\n\tIOMMU_VTD_S1_EAFE = 2,\n\tIOMMU_VTD_S1_WPE = 4,\n};\n\nenum iommu_hwpt_vtd_s1_invalidate_flags {\n\tIOMMU_VTD_INV_FLAGS_LEAF = 1,\n};\n\nenum iommu_init_state {\n\tIOMMU_START_STATE = 0,\n\tIOMMU_IVRS_DETECTED = 1,\n\tIOMMU_ACPI_FINISHED = 2,\n\tIOMMU_ENABLED = 3,\n\tIOMMU_PCI_INIT = 4,\n\tIOMMU_INTERRUPTS_EN = 5,\n\tIOMMU_INITIALIZED = 6,\n\tIOMMU_NOT_FOUND = 7,\n\tIOMMU_INIT_ERROR = 8,\n\tIOMMU_CMDLINE_DISABLED = 9,\n};\n\nenum iommu_page_response_code {\n\tIOMMU_PAGE_RESP_SUCCESS = 0,\n\tIOMMU_PAGE_RESP_INVALID = 1,\n\tIOMMU_PAGE_RESP_FAILURE = 2,\n};\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nenum iommu_viommu_type {\n\tIOMMU_VIOMMU_TYPE_DEFAULT = 0,\n\tIOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,\n\tIOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,\n};\n\nenum iommufd_hwpt_alloc_flags {\n\tIOMMU_HWPT_ALLOC_NEST_PARENT = 1,\n\tIOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2,\n\tIOMMU_HWPT_FAULT_ID_VALID = 4,\n\tIOMMU_HWPT_ALLOC_PASID = 8,\n};\n\nenum iommufd_object_type {\n\tIOMMUFD_OBJ_NONE = 0,\n\tIOMMUFD_OBJ_ANY = 0,\n\tIOMMUFD_OBJ_DEVICE = 1,\n\tIOMMUFD_OBJ_HWPT_PAGING = 2,\n\tIOMMUFD_OBJ_HWPT_NESTED = 3,\n\tIOMMUFD_OBJ_IOAS = 4,\n\tIOMMUFD_OBJ_ACCESS = 5,\n\tIOMMUFD_OBJ_FAULT = 6,\n\tIOMMUFD_OBJ_VIOMMU = 7,\n\tIOMMUFD_OBJ_VDEVICE = 8,\n\tIOMMUFD_OBJ_VEVENTQ = 9,\n\tIOMMUFD_OBJ_HW_QUEUE = 10,\n\tIOMMUFD_OBJ_MAX = 11,\n};\n\nenum ip6_defrag_users {\n\tIP6_DEFRAG_LOCAL_DELIVER = 0,\n\tIP6_DEFRAG_CONNTRACK_IN = 1,\n\t__IP6_DEFRAG_CONNTRACK_IN = 65536,\n\tIP6_DEFRAG_CONNTRACK_OUT = 65537,\n\t__IP6_DEFRAG_CONNTRACK_OUT = 131072,\n\tIP6_DEFRAG_CONNTRACK_BRIDGE_IN = 131073,\n\t__IP6_DEFRAG_CONNTRACK_BRIDGE_IN = 196608,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_conntrack_events {\n\tIPCT_NEW = 0,\n\tIPCT_RELATED = 1,\n\tIPCT_DESTROY = 2,\n\tIPCT_REPLY = 3,\n\tIPCT_ASSURED = 4,\n\tIPCT_PROTOINFO = 5,\n\tIPCT_HELPER = 6,\n\tIPCT_MARK = 7,\n\tIPCT_SEQADJ = 8,\n\tIPCT_NATSEQADJ = 8,\n\tIPCT_SECMARK = 9,\n\tIPCT_LABEL = 10,\n\tIPCT_SYNPROXY = 11,\n\t__IPCT_MAX = 12,\n};\n\nenum ip_conntrack_expect_events {\n\tIPEXP_NEW = 0,\n\tIPEXP_DESTROY = 1,\n};\n\nenum ip_conntrack_info {\n\tIP_CT_ESTABLISHED = 0,\n\tIP_CT_RELATED = 1,\n\tIP_CT_NEW = 2,\n\tIP_CT_IS_REPLY = 3,\n\tIP_CT_ESTABLISHED_REPLY = 3,\n\tIP_CT_RELATED_REPLY = 4,\n\tIP_CT_NUMBER = 5,\n\tIP_CT_UNTRACKED = 7,\n};\n\nenum ip_conntrack_status {\n\tIPS_EXPECTED_BIT = 0,\n\tIPS_EXPECTED = 1,\n\tIPS_SEEN_REPLY_BIT = 1,\n\tIPS_SEEN_REPLY = 2,\n\tIPS_ASSURED_BIT = 2,\n\tIPS_ASSURED = 4,\n\tIPS_CONFIRMED_BIT = 3,\n\tIPS_CONFIRMED = 8,\n\tIPS_SRC_NAT_BIT = 4,\n\tIPS_SRC_NAT = 16,\n\tIPS_DST_NAT_BIT = 5,\n\tIPS_DST_NAT = 32,\n\tIPS_NAT_MASK = 48,\n\tIPS_SEQ_ADJUST_BIT = 6,\n\tIPS_SEQ_ADJUST = 64,\n\tIPS_SRC_NAT_DONE_BIT = 7,\n\tIPS_SRC_NAT_DONE = 128,\n\tIPS_DST_NAT_DONE_BIT = 8,\n\tIPS_DST_NAT_DONE = 256,\n\tIPS_NAT_DONE_MASK = 384,\n\tIPS_DYING_BIT = 9,\n\tIPS_DYING = 512,\n\tIPS_FIXED_TIMEOUT_BIT = 10,\n\tIPS_FIXED_TIMEOUT = 1024,\n\tIPS_TEMPLATE_BIT = 11,\n\tIPS_TEMPLATE = 2048,\n\tIPS_UNTRACKED_BIT = 12,\n\tIPS_UNTRACKED = 4096,\n\tIPS_NAT_CLASH_BIT = 12,\n\tIPS_NAT_CLASH = 4096,\n\tIPS_HELPER_BIT = 13,\n\tIPS_HELPER = 8192,\n\tIPS_OFFLOAD_BIT = 14,\n\tIPS_OFFLOAD = 16384,\n\tIPS_HW_OFFLOAD_BIT = 15,\n\tIPS_HW_OFFLOAD = 32768,\n\tIPS_UNCHANGEABLE_MASK = 56313,\n\t__IPS_MAX_BIT = 16,\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum irq_alloc_type {\n\tX86_IRQ_ALLOC_TYPE_IOAPIC = 1,\n\tX86_IRQ_ALLOC_TYPE_HPET = 2,\n\tX86_IRQ_ALLOC_TYPE_PCI_MSI = 3,\n\tX86_IRQ_ALLOC_TYPE_PCI_MSIX = 4,\n\tX86_IRQ_ALLOC_TYPE_DMAR = 5,\n\tX86_IRQ_ALLOC_TYPE_AMDVI = 6,\n\tX86_IRQ_ALLOC_TYPE_UV = 7,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum isofs_file_format {\n\tisofs_file_normal = 0,\n\tisofs_file_sparse = 1,\n\tisofs_file_compressed = 2,\n};\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum its_mitigation {\n\tITS_MITIGATION_OFF = 0,\n\tITS_MITIGATION_AUTO = 1,\n\tITS_MITIGATION_VMEXIT_ONLY = 2,\n\tITS_MITIGATION_ALIGNED_THUNKS = 3,\n\tITS_MITIGATION_RETPOLINE_STUFF = 4,\n};\n\nenum jbd2_shrink_type {\n\tJBD2_SHRINK_DESTROY = 0,\n\tJBD2_SHRINK_BUSY_STOP = 1,\n\tJBD2_SHRINK_BUSY_SKIP = 2,\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 17,\n\tBH_JWrite = 18,\n\tBH_Freed = 19,\n\tBH_Revoked = 20,\n\tBH_RevokeValid = 21,\n\tBH_JBDDirty = 22,\n\tBH_JournalHead = 23,\n\tBH_Shadow = 24,\n\tBH_Verified = 25,\n\tBH_JBDPrivateStart = 26,\n};\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nenum kcmp_type {\n\tKCMP_FILE = 0,\n\tKCMP_VM = 1,\n\tKCMP_FILES = 2,\n\tKCMP_FS = 3,\n\tKCMP_SIGHAND = 4,\n\tKCMP_IO = 5,\n\tKCMP_SYSVSEM = 6,\n\tKCMP_EPOLL_TFD = 7,\n\tKCMP_TYPES = 8,\n};\n\nenum kcore_type {\n\tKCORE_TEXT = 0,\n\tKCORE_VMALLOC = 1,\n\tKCORE_RAM = 2,\n\tKCORE_VMEMMAP = 3,\n\tKCORE_USER = 4,\n};\n\nenum kernel_gp_hint {\n\tGP_NO_HINT = 0,\n\tGP_NON_CANONICAL = 1,\n\tGP_CANONICAL = 2,\n\tGP_LASS_VIOLATION = 3,\n\tGP_NULL_POINTER = 4,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_being_used_for {\n\tVERIFYING_MODULE_SIGNATURE = 0,\n\tVERIFYING_FIRMWARE_SIGNATURE = 1,\n\tVERIFYING_KEXEC_PE_SIGNATURE = 2,\n\tVERIFYING_KEY_SIGNATURE = 3,\n\tVERIFYING_KEY_SELF_SIGNATURE = 4,\n\tVERIFYING_UNSPECIFIED_SIGNATURE = 5,\n\tVERIFYING_BPF_SIGNATURE = 6,\n\tNR__KEY_BEING_USED_FOR = 7,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_CGROUP = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_DMA = 2,\n\tNR_KMALLOC_TYPES = 3,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum kprobe_slot_state {\n\tSLOT_CLEAN = 0,\n\tSLOT_DIRTY = 1,\n\tSLOT_USED = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum kvm_apic_logical_mode {\n\tKVM_APIC_MODE_SW_DISABLED = 0,\n\tKVM_APIC_MODE_XAPIC_CLUSTER = 1,\n\tKVM_APIC_MODE_XAPIC_FLAT = 2,\n\tKVM_APIC_MODE_X2APIC = 3,\n\tKVM_APIC_MODE_MAP_DISABLED = 4,\n};\n\nenum kvm_bus {\n\tKVM_MMIO_BUS = 0,\n\tKVM_PIO_BUS = 1,\n\tKVM_VIRTIO_CCW_NOTIFY_BUS = 2,\n\tKVM_FAST_MMIO_BUS = 3,\n\tKVM_IOCSR_BUS = 4,\n\tKVM_NR_BUSES = 5,\n};\n\nenum kvm_irqchip_mode {\n\tKVM_IRQCHIP_NONE = 0,\n\tKVM_IRQCHIP_SPLIT = 1,\n};\n\nenum kvm_mmu_type {\n\tKVM_SHADOW_MMU = 0,\n\tKVM_TDP_MMU = 1,\n\tKVM_NR_MMU_TYPES = 2,\n};\n\nenum kvm_only_cpuid_leafs {\n\tCPUID_12_EAX = 22,\n\tCPUID_7_1_EDX = 23,\n\tCPUID_8000_0007_EDX = 24,\n\tCPUID_8000_0022_EAX = 25,\n\tCPUID_7_2_EDX = 26,\n\tCPUID_24_0_EBX = 27,\n\tCPUID_8000_0021_ECX = 28,\n\tCPUID_7_1_ECX = 29,\n\tCPUID_1E_1_EAX = 30,\n\tCPUID_24_1_ECX = 31,\n\tNR_KVM_CPU_CAPS = 32,\n\tNKVMCAPINTS = 10,\n};\n\nenum kvm_reg {\n\tVCPU_REGS_RAX = 0,\n\tVCPU_REGS_RCX = 1,\n\tVCPU_REGS_RDX = 2,\n\tVCPU_REGS_RBX = 3,\n\tVCPU_REGS_RSP = 4,\n\tVCPU_REGS_RBP = 5,\n\tVCPU_REGS_RSI = 6,\n\tVCPU_REGS_RDI = 7,\n\tVCPU_REGS_R8 = 8,\n\tVCPU_REGS_R9 = 9,\n\tVCPU_REGS_R10 = 10,\n\tVCPU_REGS_R11 = 11,\n\tVCPU_REGS_R12 = 12,\n\tVCPU_REGS_R13 = 13,\n\tVCPU_REGS_R14 = 14,\n\tVCPU_REGS_R15 = 15,\n\tVCPU_REGS_RIP = 16,\n\tNR_VCPU_REGS = 17,\n\tVCPU_EXREG_PDPTR = 17,\n\tVCPU_EXREG_CR0 = 18,\n\tVCPU_EXREG_CR3 = 19,\n\tVCPU_EXREG_ERAPS = 19,\n\tVCPU_EXREG_CR4 = 20,\n\tVCPU_EXREG_RFLAGS = 21,\n\tVCPU_EXREG_SEGMENTS = 22,\n\tVCPU_EXREG_EXIT_INFO_1 = 23,\n\tVCPU_EXREG_EXIT_INFO_2 = 24,\n};\n\nenum kvm_stat_kind {\n\tKVM_STAT_VM = 0,\n\tKVM_STAT_VCPU = 1,\n};\n\nenum kvm_suppress_eoi_broadcast_mode {\n\tKVM_SUPPRESS_EOI_BROADCAST_QUIRKED = 0,\n\tKVM_SUPPRESS_EOI_BROADCAST_ENABLED = 1,\n\tKVM_SUPPRESS_EOI_BROADCAST_DISABLED = 2,\n};\n\nenum l1d_flush_mitigations {\n\tL1D_FLUSH_OFF = 0,\n\tL1D_FLUSH_ON = 1,\n};\n\nenum l1tf_mitigations {\n\tL1TF_MITIGATION_OFF = 0,\n\tL1TF_MITIGATION_AUTO = 1,\n\tL1TF_MITIGATION_FLUSH_NOWARN = 2,\n\tL1TF_MITIGATION_FLUSH = 3,\n\tL1TF_MITIGATION_FLUSH_NOSMT = 4,\n\tL1TF_MITIGATION_FULL = 5,\n\tL1TF_MITIGATION_FULL_FORCE = 6,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum label_initialized {\n\tLABEL_INVALID = 0,\n\tLABEL_INITIALIZED = 1,\n\tLABEL_PENDING = 2,\n};\n\nenum latency_count {\n\tCOUNTS_10e2 = 0,\n\tCOUNTS_10e3 = 1,\n\tCOUNTS_10e4 = 2,\n\tCOUNTS_10e5 = 3,\n\tCOUNTS_10e6 = 4,\n\tCOUNTS_10e7 = 5,\n\tCOUNTS_10e8_plus = 6,\n\tCOUNTS_MIN = 7,\n\tCOUNTS_MAX = 8,\n\tCOUNTS_SUM = 9,\n\tCOUNTS_NUM = 10,\n};\n\nenum latency_range {\n\tlowest_latency = 0,\n\tlow_latency = 1,\n\tbulk_latency = 2,\n\tlatency_invalid = 255,\n};\n\nenum latency_type {\n\tDMAR_LATENCY_INV_IOTLB = 0,\n\tDMAR_LATENCY_INV_DEVTLB = 1,\n\tDMAR_LATENCY_INV_IEC = 2,\n\tDMAR_LATENCY_NUM = 3,\n};\n\nenum layoutdriver_policy_flags {\n\tPNFS_LAYOUTRET_ON_SETATTR = 1,\n\tPNFS_LAYOUTRET_ON_ERROR = 2,\n\tPNFS_READ_WHOLE_PAGE = 4,\n\tPNFS_LAYOUTGET_ON_OPEN = 8,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum led_default_state {\n\tLEDS_DEFSTATE_OFF = 0,\n\tLEDS_DEFSTATE_ON = 1,\n\tLEDS_DEFSTATE_KEEP = 2,\n};\n\nenum led_mode {\n\tMO_LED_NORM = 0,\n\tMO_LED_BLINK = 1,\n\tMO_LED_OFF = 2,\n\tMO_LED_ON = 3,\n};\n\nenum led_state {\n\tled_on = 1,\n\tled_off = 4,\n\tled_on_559 = 5,\n\tled_on_557 = 7,\n};\n\nenum led_trigger_netdev_modes {\n\tTRIGGER_NETDEV_LINK = 0,\n\tTRIGGER_NETDEV_LINK_10 = 1,\n\tTRIGGER_NETDEV_LINK_100 = 2,\n\tTRIGGER_NETDEV_LINK_1000 = 3,\n\tTRIGGER_NETDEV_LINK_2500 = 4,\n\tTRIGGER_NETDEV_LINK_5000 = 5,\n\tTRIGGER_NETDEV_LINK_10000 = 6,\n\tTRIGGER_NETDEV_HALF_DUPLEX = 7,\n\tTRIGGER_NETDEV_FULL_DUPLEX = 8,\n\tTRIGGER_NETDEV_TX = 9,\n\tTRIGGER_NETDEV_RX = 10,\n\tTRIGGER_NETDEV_TX_ERR = 11,\n\tTRIGGER_NETDEV_RX_ERR = 12,\n\t__TRIGGER_NETDEV_MAX = 13,\n};\n\nenum limit_by4 {\n\tNFS4_LIMIT_SIZE = 1,\n\tNFS4_LIMIT_BLOCKS = 2,\n};\n\nenum link_inband_signalling {\n\tLINK_INBAND_DISABLE = 1,\n\tLINK_INBAND_ENABLE = 2,\n\tLINK_INBAND_BYPASS = 4,\n};\n\nenum lock_type4 {\n\tNFS4_UNLOCK_LT = 0,\n\tNFS4_READ_LT = 1,\n\tNFS4_WRITE_LT = 2,\n\tNFS4_READW_LT = 3,\n\tNFS4_WRITEW_LT = 4,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum loopback {\n\tlb_none = 0,\n\tlb_mac = 1,\n\tlb_phy = 3,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lsm_event {\n\tLSM_POLICY_CHANGE = 0,\n\tLSM_STARTED_ALL = 1,\n};\n\nenum lsm_integrity_type {\n\tLSM_INT_DMVERITY_SIG_VALID = 0,\n\tLSM_INT_DMVERITY_ROOTHASH = 1,\n\tLSM_INT_FSVERITY_BUILTINSIG_VALID = 2,\n};\n\nenum lsm_order {\n\tLSM_ORDER_FIRST = -1,\n\tLSM_ORDER_MUTABLE = 0,\n\tLSM_ORDER_LAST = 1,\n};\n\nenum lspcon_vendor {\n\tLSPCON_VENDOR_MCA = 0,\n\tLSPCON_VENDOR_PARADE = 1,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum mac {\n\tmac_82557_D100_A = 0,\n\tmac_82557_D100_B = 1,\n\tmac_82557_D100_C = 2,\n\tmac_82558_D101_A4 = 4,\n\tmac_82558_D101_B0 = 5,\n\tmac_82559_D101M = 8,\n\tmac_82559_D101S = 9,\n\tmac_82550_D102 = 12,\n\tmac_82550_D102_C = 13,\n\tmac_82551_E = 14,\n\tmac_82551_F = 15,\n\tmac_82551_10 = 16,\n\tmac_unknown = 255,\n};\n\nenum mac80211_drop_reason {\n\tRX_CONTINUE = 1,\n\tRX_QUEUED = 0,\n\tRX_DROP_U_MIC_FAIL = 65537,\n\tRX_DROP_U_REPLAY = 65538,\n\tRX_DROP_U_BAD_MMIE = 65539,\n\tRX_DROP_U_DUP = 65540,\n\tRX_DROP_U_SPURIOUS = 65541,\n\tRX_DROP_U_DECRYPT_FAIL = 65542,\n\tRX_DROP_U_NO_KEY_ID = 65543,\n\tRX_DROP_U_BAD_CIPHER = 65544,\n\tRX_DROP_U_OOM = 65545,\n\tRX_DROP_U_NONSEQ_PN = 65546,\n\tRX_DROP_U_BAD_KEY_COLOR = 65547,\n\tRX_DROP_U_BAD_4ADDR = 65548,\n\tRX_DROP_U_BAD_AMSDU = 65549,\n\tRX_DROP_U_BAD_AMSDU_CIPHER = 65550,\n\tRX_DROP_U_INVALID_8023 = 65551,\n\tRX_DROP_U_RUNT_ACTION = 65552,\n\tRX_DROP_U_UNPROT_ACTION = 65553,\n\tRX_DROP_U_UNPROT_DUAL = 65554,\n\tRX_DROP_U_UNPROT_UCAST_MGMT = 65555,\n\tRX_DROP_U_UNPROT_MCAST_MGMT = 65556,\n\tRX_DROP_U_UNPROT_BEACON = 65557,\n\tRX_DROP_U_UNPROT_UNICAST_PUB_ACTION = 65558,\n\tRX_DROP_U_UNPROT_ROBUST_ACTION = 65559,\n\tRX_DROP_U_ACTION_UNKNOWN_SRC = 65560,\n\tRX_DROP_U_REJECTED_ACTION_RESPONSE = 65561,\n\tRX_DROP_U_EXPECT_DEFRAG_PROT = 65562,\n\tRX_DROP_U_WEP_DEC_FAIL = 65563,\n\tRX_DROP_U_NO_IV = 65564,\n\tRX_DROP_U_NO_ICV = 65565,\n\tRX_DROP_U_AP_RX_GROUPCAST = 65566,\n\tRX_DROP_U_SHORT_MMIC = 65567,\n\tRX_DROP_U_MMIC_FAIL = 65568,\n\tRX_DROP_U_SHORT_TKIP = 65569,\n\tRX_DROP_U_TKIP_FAIL = 65570,\n\tRX_DROP_U_SHORT_CCMP = 65571,\n\tRX_DROP_U_SHORT_CCMP_MIC = 65572,\n\tRX_DROP_U_SHORT_GCMP = 65573,\n\tRX_DROP_U_SHORT_GCMP_MIC = 65574,\n\tRX_DROP_U_SHORT_CMAC = 65575,\n\tRX_DROP_U_SHORT_CMAC256 = 65576,\n\tRX_DROP_U_SHORT_GMAC = 65577,\n\tRX_DROP_U_UNEXPECTED_VLAN_4ADDR = 65578,\n\tRX_DROP_U_UNEXPECTED_STA_4ADDR = 65579,\n\tRX_DROP_U_UNEXPECTED_VLAN_MCAST = 65580,\n\tRX_DROP_U_NOT_PORT_CONTROL = 65581,\n\tRX_DROP_U_UNEXPECTED_4ADDR_FRAME = 65582,\n\tRX_DROP_U_BAD_BCN_KEYIDX = 65583,\n\tRX_DROP_U_BAD_MGMT_KEYIDX = 65584,\n\tRX_DROP_U_UNKNOWN_ACTION_REJECTED = 65585,\n\tRX_DROP_U_MESH_DS_BITS = 65586,\n\tRX_DROP_U_MESH_A3_MISMATCH = 65587,\n\tRX_DROP_U_MESH_NO_A4 = 65588,\n\tRX_DROP_U_MESH_A4_MISMATCH = 65589,\n\tRX_DROP_U_MESH_UNEXP_DATA = 65590,\n\tRX_DROP_U_MESH_WRONG_ACTION = 65591,\n\tRX_DROP_U_MESH_UNEXP_MGMT = 65592,\n\tRX_DROP_U_SPURIOUS_NOTIF = 65593,\n\tRX_DROP_U_RUNT_DATA = 65594,\n\tRX_DROP_U_KEY_TAINTED = 65595,\n\tRX_DROP_U_UNPROTECTED = 65596,\n\tRX_DROP_U_MCAST_FRAGMENT = 65597,\n\tRX_DROP_U_DEFRAG_MISMATCH = 65598,\n\tRX_DROP_U_RUNT_MESH_DATA = 65599,\n\tRX_DROP_U_MESH_NO_TTL = 65600,\n\tRX_DROP_U_MESH_RMC = 65601,\n\tRX_DROP_U_MESH_BAD_AE = 65602,\n\tRX_DROP_U_MESH_TTL_EXPIRED = 65603,\n\tRX_DROP_U_MESH_NOT_FORWARDING = 65604,\n\tRX_DROP_U_AMSDU_WITHOUT_DATA = 65605,\n\tRX_DROP_U_NULL_DATA = 65606,\n\tRX_DROP_U_UNEXPECTED_4ADDR = 65607,\n\tRX_DROP_U_PORT_CONTROL = 65608,\n\tRX_DROP_U_UNKNOWN_STA = 65609,\n\tRX_DROP_U_RUNT_BAR = 65610,\n\tRX_DROP_U_BAR_OUTSIDE_SESSION = 65611,\n\tRX_DROP_U_CTRL_FRAME = 65612,\n\tRX_DROP_U_RUNT_MGMT = 65613,\n\tRX_DROP_U_EXPECTED_MGMT = 65614,\n\tRX_DROP_U_NONBCAST_BEACON = 65615,\n\tRX_DROP_U_MALFORMED_ACTION = 65616,\n\tRX_DROP_U_UNKNOWN_MCAST_ACTION = 65617,\n\tRX_DROP_U_UNEXPECTED_EXT_FRAME = 65618,\n\tRX_DROP_U_UNHANDLED_MGMT = 65619,\n\tRX_DROP_U_MCAST_DEAUTH = 65620,\n\tRX_DROP_U_UNHANDLED_DEAUTH = 65621,\n\tRX_DROP_U_MCAST_DISASSOC = 65622,\n\tRX_DROP_U_UNHANDLED_DISASSOC = 65623,\n\tRX_DROP_U_UNHANDLED_PREQ = 65624,\n\tRX_DROP_U_UNHANDLED_MGMT_STYPE = 65625,\n\tRX_DROP_U_NO_LINK = 65626,\n};\n\nenum mac80211_rate_control_flags {\n\tIEEE80211_TX_RC_USE_RTS_CTS = 1,\n\tIEEE80211_TX_RC_USE_CTS_PROTECT = 2,\n\tIEEE80211_TX_RC_USE_SHORT_PREAMBLE = 4,\n\tIEEE80211_TX_RC_MCS = 8,\n\tIEEE80211_TX_RC_GREEN_FIELD = 16,\n\tIEEE80211_TX_RC_40_MHZ_WIDTH = 32,\n\tIEEE80211_TX_RC_DUP_DATA = 64,\n\tIEEE80211_TX_RC_SHORT_GI = 128,\n\tIEEE80211_TX_RC_VHT_MCS = 256,\n\tIEEE80211_TX_RC_80_MHZ_WIDTH = 512,\n\tIEEE80211_TX_RC_160_MHZ_WIDTH = 1024,\n};\n\nenum mac80211_rx_encoding {\n\tRX_ENC_LEGACY = 0,\n\tRX_ENC_HT = 1,\n\tRX_ENC_VHT = 2,\n\tRX_ENC_HE = 3,\n\tRX_ENC_EHT = 4,\n\tRX_ENC_UHR = 5,\n};\n\nenum mac80211_rx_encoding_flags {\n\tRX_ENC_FLAG_SHORTPRE = 1,\n\tRX_ENC_FLAG_SHORT_GI = 4,\n\tRX_ENC_FLAG_HT_GF = 8,\n\tRX_ENC_FLAG_STBC_MASK = 48,\n\tRX_ENC_FLAG_LDPC = 64,\n\tRX_ENC_FLAG_BF = 128,\n};\n\nenum mac80211_rx_flags {\n\tRX_FLAG_MMIC_ERROR = 1,\n\tRX_FLAG_DECRYPTED = 2,\n\tRX_FLAG_ONLY_MONITOR = 4,\n\tRX_FLAG_MMIC_STRIPPED = 8,\n\tRX_FLAG_IV_STRIPPED = 16,\n\tRX_FLAG_FAILED_FCS_CRC = 32,\n\tRX_FLAG_FAILED_PLCP_CRC = 64,\n\tRX_FLAG_MACTIME_IS_RTAP_TS64 = 128,\n\tRX_FLAG_NO_SIGNAL_VAL = 256,\n\tRX_FLAG_AMPDU_DETAILS = 512,\n\tRX_FLAG_PN_VALIDATED = 1024,\n\tRX_FLAG_DUP_VALIDATED = 2048,\n\tRX_FLAG_AMPDU_LAST_KNOWN = 4096,\n\tRX_FLAG_AMPDU_IS_LAST = 8192,\n\tRX_FLAG_AMPDU_DELIM_CRC_ERROR = 16384,\n\tRX_FLAG_MACTIME = 196608,\n\tRX_FLAG_MACTIME_PLCP_START = 65536,\n\tRX_FLAG_MACTIME_START = 131072,\n\tRX_FLAG_MACTIME_END = 196608,\n\tRX_FLAG_SKIP_MONITOR = 262144,\n\tRX_FLAG_AMSDU_MORE = 524288,\n\tRX_FLAG_RADIOTAP_TLV_AT_END = 1048576,\n\tRX_FLAG_MIC_STRIPPED = 2097152,\n\tRX_FLAG_ALLOW_SAME_PN = 4194304,\n\tRX_FLAG_ICV_STRIPPED = 8388608,\n\tRX_FLAG_AMPDU_EOF_BIT = 16777216,\n\tRX_FLAG_AMPDU_EOF_BIT_KNOWN = 33554432,\n\tRX_FLAG_RADIOTAP_HE = 67108864,\n\tRX_FLAG_RADIOTAP_HE_MU = 134217728,\n\tRX_FLAG_RADIOTAP_LSIG = 268435456,\n\tRX_FLAG_NO_PSDU = 536870912,\n\tRX_FLAG_8023 = 1073741824,\n\tRX_FLAG_RADIOTAP_VHT = 2147483648,\n};\n\nenum mac80211_scan_flags {\n\tSCAN_SW_SCANNING = 0,\n\tSCAN_HW_SCANNING = 1,\n\tSCAN_ONCHANNEL_SCANNING = 2,\n\tSCAN_COMPLETED = 3,\n\tSCAN_ABORTED = 4,\n\tSCAN_HW_CANCELLED = 5,\n\tSCAN_BEACON_WAIT = 6,\n\tSCAN_BEACON_DONE = 7,\n};\n\nenum mac80211_scan_state {\n\tSCAN_DECISION = 0,\n\tSCAN_SET_CHANNEL = 1,\n\tSCAN_SEND_PROBE = 2,\n\tSCAN_SUSPEND = 3,\n\tSCAN_RESUME = 4,\n\tSCAN_ABORT = 5,\n};\n\nenum mac80211_tx_control_flags {\n\tIEEE80211_TX_CTRL_PORT_CTRL_PROTO = 1,\n\tIEEE80211_TX_CTRL_PS_RESPONSE = 2,\n\tIEEE80211_TX_CTRL_RATE_INJECT = 4,\n\tIEEE80211_TX_CTRL_AMSDU = 8,\n\tIEEE80211_TX_CTRL_FAST_XMIT = 16,\n\tIEEE80211_TX_CTRL_SKIP_MPATH_LOOKUP = 32,\n\tIEEE80211_TX_INTCFL_NEED_TXPROCESSING = 64,\n\tIEEE80211_TX_CTRL_NO_SEQNO = 128,\n\tIEEE80211_TX_CTRL_DONT_REORDER = 256,\n\tIEEE80211_TX_CTRL_MCAST_MLO_FIRST_TX = 512,\n\tIEEE80211_TX_CTRL_DONT_USE_RATE_MASK = 1024,\n\tIEEE80211_TX_CTRL_MLO_LINK = 4026531840,\n};\n\nenum mac80211_tx_info_flags {\n\tIEEE80211_TX_CTL_REQ_TX_STATUS = 1,\n\tIEEE80211_TX_CTL_ASSIGN_SEQ = 2,\n\tIEEE80211_TX_CTL_NO_ACK = 4,\n\tIEEE80211_TX_CTL_CLEAR_PS_FILT = 8,\n\tIEEE80211_TX_CTL_FIRST_FRAGMENT = 16,\n\tIEEE80211_TX_CTL_SEND_AFTER_DTIM = 32,\n\tIEEE80211_TX_CTL_AMPDU = 64,\n\tIEEE80211_TX_CTL_INJECTED = 128,\n\tIEEE80211_TX_STAT_TX_FILTERED = 256,\n\tIEEE80211_TX_STAT_ACK = 512,\n\tIEEE80211_TX_STAT_AMPDU = 1024,\n\tIEEE80211_TX_STAT_AMPDU_NO_BACK = 2048,\n\tIEEE80211_TX_CTL_RATE_CTRL_PROBE = 4096,\n\tIEEE80211_TX_INTFL_OFFCHAN_TX_OK = 8192,\n\tIEEE80211_TX_CTL_HW_80211_ENCAP = 16384,\n\tIEEE80211_TX_INTFL_RETRIED = 32768,\n\tIEEE80211_TX_INTFL_DONT_ENCRYPT = 65536,\n\tIEEE80211_TX_CTL_NO_PS_BUFFER = 131072,\n\tIEEE80211_TX_CTL_MORE_FRAMES = 262144,\n\tIEEE80211_TX_INTFL_RETRANSMISSION = 524288,\n\tIEEE80211_TX_INTFL_MLME_CONN_TX = 1048576,\n\tIEEE80211_TX_INTFL_NL80211_FRAME_TX = 2097152,\n\tIEEE80211_TX_CTL_LDPC = 4194304,\n\tIEEE80211_TX_CTL_STBC = 25165824,\n\tIEEE80211_TX_CTL_TX_OFFCHAN = 33554432,\n\tIEEE80211_TX_INTFL_TKIP_MIC_FAILURE = 67108864,\n\tIEEE80211_TX_CTL_NO_CCK_RATE = 134217728,\n\tIEEE80211_TX_STATUS_EOSP = 268435456,\n\tIEEE80211_TX_CTL_USE_MINRATE = 536870912,\n\tIEEE80211_TX_CTL_DONTFRAG = 1073741824,\n\tIEEE80211_TX_STAT_NOACK_TRANSMITTED = 2147483648,\n};\n\nenum mac80211_tx_status_flags {\n\tIEEE80211_TX_STATUS_ACK_SIGNAL_VALID = 1,\n};\n\nenum mac_version {\n\tRTL_GIGA_MAC_VER_02 = 0,\n\tRTL_GIGA_MAC_VER_03 = 1,\n\tRTL_GIGA_MAC_VER_04 = 2,\n\tRTL_GIGA_MAC_VER_05 = 3,\n\tRTL_GIGA_MAC_VER_06 = 4,\n\tRTL_GIGA_MAC_VER_07 = 5,\n\tRTL_GIGA_MAC_VER_08 = 6,\n\tRTL_GIGA_MAC_VER_09 = 7,\n\tRTL_GIGA_MAC_VER_10 = 8,\n\tRTL_GIGA_MAC_VER_14 = 9,\n\tRTL_GIGA_MAC_VER_17 = 10,\n\tRTL_GIGA_MAC_VER_18 = 11,\n\tRTL_GIGA_MAC_VER_19 = 12,\n\tRTL_GIGA_MAC_VER_20 = 13,\n\tRTL_GIGA_MAC_VER_21 = 14,\n\tRTL_GIGA_MAC_VER_22 = 15,\n\tRTL_GIGA_MAC_VER_23 = 16,\n\tRTL_GIGA_MAC_VER_24 = 17,\n\tRTL_GIGA_MAC_VER_25 = 18,\n\tRTL_GIGA_MAC_VER_26 = 19,\n\tRTL_GIGA_MAC_VER_28 = 20,\n\tRTL_GIGA_MAC_VER_29 = 21,\n\tRTL_GIGA_MAC_VER_30 = 22,\n\tRTL_GIGA_MAC_VER_31 = 23,\n\tRTL_GIGA_MAC_VER_32 = 24,\n\tRTL_GIGA_MAC_VER_33 = 25,\n\tRTL_GIGA_MAC_VER_34 = 26,\n\tRTL_GIGA_MAC_VER_35 = 27,\n\tRTL_GIGA_MAC_VER_36 = 28,\n\tRTL_GIGA_MAC_VER_37 = 29,\n\tRTL_GIGA_MAC_VER_38 = 30,\n\tRTL_GIGA_MAC_VER_39 = 31,\n\tRTL_GIGA_MAC_VER_40 = 32,\n\tRTL_GIGA_MAC_VER_42 = 33,\n\tRTL_GIGA_MAC_VER_43 = 34,\n\tRTL_GIGA_MAC_VER_44 = 35,\n\tRTL_GIGA_MAC_VER_46 = 36,\n\tRTL_GIGA_MAC_VER_48 = 37,\n\tRTL_GIGA_MAC_VER_51 = 38,\n\tRTL_GIGA_MAC_VER_52 = 39,\n\tRTL_GIGA_MAC_VER_61 = 40,\n\tRTL_GIGA_MAC_VER_63 = 41,\n\tRTL_GIGA_MAC_VER_64 = 42,\n\tRTL_GIGA_MAC_VER_66 = 43,\n\tRTL_GIGA_MAC_VER_70 = 44,\n\tRTL_GIGA_MAC_VER_80 = 45,\n\tRTL_GIGA_MAC_NONE = 46,\n\tRTL_GIGA_MAC_VER_LAST = 45,\n\tRTL_GIGA_MAC_VER_EXTENDED = 46,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum maindmc_event_id {\n\tMAINDMC_EVENT_CMP_ZERO = 8,\n\tMAINDMC_EVENT_CMP_ODD = 9,\n\tMAINDMC_EVENT_CMP_NEG = 10,\n\tMAINDMC_EVENT_CMP_CARRY = 11,\n\tMAINDMC_EVENT_TMR0_DONE = 20,\n\tMAINDMC_EVENT_TMR1_DONE = 21,\n\tMAINDMC_EVENT_TMR2_DONE = 22,\n\tMAINDMC_EVENT_COUNT0_DONE = 23,\n\tMAINDMC_EVENT_COUNT1_DONE = 24,\n\tMAINDMC_EVENT_PERF_CNTR_DARBF = 25,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_A_TRIGGER = 34,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_B_TRIGGER = 35,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_C_TRIGGER = 36,\n\tMAINDMC_EVENT_SCANLINE_INRANGE_FQ_D_TRIGGER = 37,\n\tMAINDMC_EVENT_1KHZ_FQ_A_TRIGGER = 38,\n\tMAINDMC_EVENT_1KHZ_FQ_B_TRIGGER = 39,\n\tMAINDMC_EVENT_1KHZ_FQ_C_TRIGGER = 40,\n\tMAINDMC_EVENT_1KHZ_FQ_D_TRIGGER = 41,\n\tMAINDMC_EVENT_SCANLINE_COMP_A = 42,\n\tMAINDMC_EVENT_SCANLINE_COMP_B = 43,\n\tMAINDMC_EVENT_SCANLINE_COMP_C = 44,\n\tMAINDMC_EVENT_SCANLINE_COMP_D = 45,\n\tMAINDMC_EVENT_VBLANK_DELAYED_A = 46,\n\tMAINDMC_EVENT_VBLANK_DELAYED_B = 47,\n\tMAINDMC_EVENT_VBLANK_DELAYED_C = 48,\n\tMAINDMC_EVENT_VBLANK_DELAYED_D = 49,\n\tMAINDMC_EVENT_VBLANK_A = 50,\n\tMAINDMC_EVENT_VBLANK_B = 51,\n\tMAINDMC_EVENT_VBLANK_C = 52,\n\tMAINDMC_EVENT_VBLANK_D = 53,\n\tMAINDMC_EVENT_HBLANK_A = 54,\n\tMAINDMC_EVENT_HBLANK_B = 55,\n\tMAINDMC_EVENT_HBLANK_C = 56,\n\tMAINDMC_EVENT_HBLANK_D = 57,\n\tMAINDMC_EVENT_VSYNC_A = 58,\n\tMAINDMC_EVENT_VSYNC_B = 59,\n\tMAINDMC_EVENT_VSYNC_C = 60,\n\tMAINDMC_EVENT_VSYNC_D = 61,\n\tMAINDMC_EVENT_SCANLINE_A = 62,\n\tMAINDMC_EVENT_SCANLINE_B = 63,\n\tMAINDMC_EVENT_SCANLINE_C = 64,\n\tMAINDMC_EVENT_SCANLINE_D = 65,\n\tMAINDMC_EVENT_PLANE1_FLIP_A = 66,\n\tMAINDMC_EVENT_PLANE2_FLIP_A = 67,\n\tMAINDMC_EVENT_PLANE3_FLIP_A = 68,\n\tMAINDMC_EVENT_PLANE4_FLIP_A = 69,\n\tMAINDMC_EVENT_PLANE5_FLIP_A = 70,\n\tMAINDMC_EVENT_PLANE6_FLIP_A = 71,\n\tMAINDMC_EVENT_PLANE7_FLIP_A = 72,\n\tMAINDMC_EVENT_PLANE1_FLIP_B = 73,\n\tMAINDMC_EVENT_PLANE2_FLIP_B = 74,\n\tMAINDMC_EVENT_PLANE3_FLIP_B = 75,\n\tMAINDMC_EVENT_PLANE4_FLIP_B = 76,\n\tMAINDMC_EVENT_PLANE5_FLIP_B = 77,\n\tMAINDMC_EVENT_PLANE6_FLIP_B = 78,\n\tMAINDMC_EVENT_PLANE7_FLIP_B = 79,\n\tMAINDMC_EVENT_PLANE1_FLIP_C = 80,\n\tMAINDMC_EVENT_PLANE2_FLIP_C = 81,\n\tMAINDMC_EVENT_PLANE3_FLIP_C = 82,\n\tMAINDMC_EVENT_PLANE4_FLIP_C = 83,\n\tMAINDMC_EVENT_PLANE5_FLIP_C = 84,\n\tMAINDMC_EVENT_PLANE6_FLIP_C = 85,\n\tMAINDMC_EVENT_PLANE7_FLIP_C = 86,\n\tMAINDMC_EVENT_PLANE1_FLIP_D = 87,\n\tMAINDMC_EVENT_PLANE2_FLIP_D = 88,\n\tMAINDMC_EVENT_PLANE3_FLIP_D = 89,\n\tMAINDMC_EVENT_PLANE4_FLIP_D = 90,\n\tMAINDMC_EVENT_PLANE5_FLIP_D = 91,\n\tMAINDMC_EVENT_PLANE6_FLIP_D = 92,\n\tMAINDMC_EVENT_PLANE7_FLIP_D = 93,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_A = 94,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_A = 95,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_A = 96,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_A = 97,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_A = 98,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_A = 99,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_A = 100,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_B = 101,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_B = 102,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_B = 103,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_B = 104,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_B = 105,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_B = 106,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_B = 107,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_C = 108,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_C = 109,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_C = 110,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_C = 111,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_C = 112,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_C = 113,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_C = 114,\n\tMAINDMC_EVENT_PLANE1_FLIP_DONE_D = 115,\n\tMAINDMC_EVENT_PLANE2_FLIP_DONE_D = 116,\n\tMAINDMC_EVENT_PLANE3_FLIP_DONE_D = 117,\n\tMAINDMC_EVENT_PLANE4_FLIP_DONE_D = 118,\n\tMAINDMC_EVENT_PLANE5_FLIP_DONE_D = 119,\n\tMAINDMC_EVENT_PLANE6_FLIP_DONE_D = 120,\n\tMAINDMC_EVENT_PLANE7_FLIP_DONE_D = 121,\n\tMAINDMC_EVENT_WIDI_GTT_FAULT_SL1 = 125,\n\tMAINDMC_EVENT_WIDI_GTT_FAULT_SL2 = 126,\n\tMAINDMC_EVENT_WIDI_CAP_ACTIVE_SL1 = 127,\n\tMAINDMC_EVENT_WIDI_CAP_ACTIVE_SL2 = 128,\n\tMAINDMC_EVENT_RENUKE_A = 133,\n\tMAINDMC_EVENT_RENUKE_B = 134,\n\tMAINDMC_EVENT_RENUKE_C = 135,\n\tMAINDMC_EVENT_RENUKE_D = 136,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_A = 137,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_B = 138,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_C = 139,\n\tMAINDMC_EVENT_DPFC_FIFO_FULL_D = 140,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_A = 141,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_B = 142,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_C = 143,\n\tMAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_D = 144,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_A = 145,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_B = 146,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_C = 147,\n\tMAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_D = 148,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_A = 149,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_B = 150,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_C = 151,\n\tMAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_D = 152,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_A = 153,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_B = 154,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_C = 155,\n\tMAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_D = 156,\n\tMAINDMC_EVENT_DISP_PCH_INT = 157,\n\tMAINDMC_EVENT_GTT_ERR = 158,\n\tMAINDMC_EVENT_VTD_ERR = 159,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_A = 160,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_B = 161,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_C = 162,\n\tMAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_D = 163,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_A = 164,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_B = 165,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_C = 166,\n\tMAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_D = 167,\n\tMAINDMC_EVENT_DC_CLOCK_OFF_START_EDP = 178,\n\tMAINDMC_EVENT_DC_CLOCK_OFF_START_DSI = 179,\n\tMAINDMC_EVENT_DCPR_DMC_CSR_START = 180,\n\tMAINDMC_EVENT_IN_PSR = 181,\n\tMAINDMC_EVENT_IN_MEMUP = 183,\n\tMAINDMC_EVENT_IN_VGA = 184,\n\tMAINDMC_EVENT_IN_KVM_SESSION = 186,\n\tMAINDMC_EVENT_DEWAKE = 187,\n\tMAINDMC_EVENT_TRAP_HIT = 189,\n\tMAINDMC_EVENT_CLK_USEC = 190,\n\tMAINDMC_EVENT_CLK_MSEC = 191,\n\tMAINDMC_EVENT_CHICKEN1 = 200,\n\tMAINDMC_EVENT_CHICKEN2 = 201,\n\tMAINDMC_EVENT_CHICKEN3 = 202,\n\tMAINDMC_EVENT_DDT_UBP = 203,\n\tMAINDMC_EVENT_HP_LATENCY = 205,\n\tMAINDMC_EVENT_LP_LATENCY = 206,\n\tMAINDMC_EVENT_WIDI_LP_REQ_SL1 = 207,\n\tMAINDMC_EVENT_WIDI_LP_REQ_SL2 = 208,\n\tMAINDMC_EVENT_DG_DMC_EVT_0 = 211,\n\tMAINDMC_EVENT_DG_DMC_EVT_1 = 212,\n\tMAINDMC_EVENT_DG_DMC_EVT_2 = 213,\n\tMAINDMC_EVENT_DG_DMC_EVT_3 = 214,\n\tMAINDMC_EVENT_DG_DMC_EVT_4 = 215,\n\tMAINDMC_EVENT_DACFE_CLK_STOP = 216,\n\tMAINDMC_EVENT_DACFE_AZILIA_SDI_WAKE = 217,\n\tMAINDMC_EVENT_AUDIO_DOUBLE_FUNC_GRP_RST = 218,\n\tMAINDMC_EVENT_AUDIO_CMD_VALID = 219,\n\tMAINDMC_EVENT_AUDIO_FRM_SYNC_BCLK = 220,\n\tMAINDMC_EVENT_AUDIO_FRM_SYNC_CDCLK = 221,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_A = 222,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_B = 223,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_C = 224,\n\tMAINDMC_EVENT_AUDIO_PRESENCE_DETECT_E = 225,\n\tMAINDMC_EVENT_CMTG_SCANLINE_IN_GB_DC6v = 226,\n\tMAINDMC_EVENT_DCPR_CMTG_SCANLINE_OUTSIDE_GB = 227,\n\tMAINDMC_EVENT_DC6v_BACKWARD_COMPAT = 228,\n\tMAINDMC_EVENT_DPMA_PM_ABORT = 229,\n\tMAINDMC_EVENT_STACK_OVF = 252,\n\tMAINDMC_EVENT_NO_CLAIM = 253,\n\tMAINDMC_EVENT_UNK_CMD = 254,\n\tMAINDMC_EVENT_HTP_MOD = 255,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum mca_msr {\n\tMCA_CTL = 0,\n\tMCA_STATUS = 1,\n\tMCA_ADDR = 2,\n\tMCA_MISC = 3,\n};\n\nenum mce_notifier_prios {\n\tMCE_PRIO_LOWEST = 0,\n\tMCE_PRIO_MCELOG = 1,\n\tMCE_PRIO_EDAC = 2,\n\tMCE_PRIO_NFIT = 3,\n\tMCE_PRIO_EXTLOG = 4,\n\tMCE_PRIO_UC = 5,\n\tMCE_PRIO_EARLY = 6,\n\tMCE_PRIO_CEC = 7,\n\tMCE_PRIO_HIGHEST = 7,\n};\n\nenum mcp_flags {\n\tMCP_TIMESTAMP = 1,\n\tMCP_UC = 2,\n\tMCP_QUEUE_LOG = 4,\n};\n\nenum md_ro_state {\n\tMD_RDWR = 0,\n\tMD_RDONLY = 1,\n\tMD_AUTO_READ = 2,\n\tMD_MAX_STATE = 3,\n};\n\nenum md_submodule_id {\n\tID_LINEAR = -1,\n\tID_RAID0 = 0,\n\tID_RAID1 = 1,\n\tID_RAID4 = 4,\n\tID_RAID5 = 5,\n\tID_RAID6 = 6,\n\tID_RAID10 = 10,\n\tID_CLUSTER = 11,\n\tID_BITMAP = 12,\n\tID_LLBITMAP = 13,\n\tID_BITMAP_NONE = 14,\n};\n\nenum md_submodule_type {\n\tMD_PERSONALITY = 0,\n\tMD_CLUSTER = 1,\n\tMD_BITMAP = 2,\n};\n\nenum mddev_flags {\n\tMD_ARRAY_FIRST_USE = 0,\n\tMD_CLOSING = 1,\n\tMD_JOURNAL_CLEAN = 2,\n\tMD_HAS_JOURNAL = 3,\n\tMD_CLUSTER_RESYNC_LOCKED = 4,\n\tMD_FAILFAST_SUPPORTED = 5,\n\tMD_HAS_PPL = 6,\n\tMD_HAS_MULTIPLE_PPLS = 7,\n\tMD_NOT_READY = 8,\n\tMD_BROKEN = 9,\n\tMD_DO_DELETE = 10,\n\tMD_DELETED = 11,\n\tMD_HAS_SUPERBLOCK = 12,\n\tMD_FAILLAST_DEV = 13,\n\tMD_SERIALIZE_POLICY = 14,\n};\n\nenum mddev_sb_flags {\n\tMD_SB_CHANGE_DEVS = 0,\n\tMD_SB_CHANGE_CLEAN = 1,\n\tMD_SB_CHANGE_PENDING = 2,\n\tMD_SB_NEED_REWRITE = 3,\n};\n\nenum mdi_ctrl {\n\tmdi_write = 67108864,\n\tmdi_read = 134217728,\n\tmdi_ready = 268435456,\n};\n\nenum mds_mitigations {\n\tMDS_MITIGATION_OFF = 0,\n\tMDS_MITIGATION_AUTO = 1,\n\tMDS_MITIGATION_FULL = 2,\n\tMDS_MITIGATION_VMWERV = 3,\n};\n\nenum mei_cb_file_ops {\n\tMEI_FOP_READ = 0,\n\tMEI_FOP_WRITE = 1,\n\tMEI_FOP_CONNECT = 2,\n\tMEI_FOP_DISCONNECT = 3,\n\tMEI_FOP_DISCONNECT_RSP = 4,\n\tMEI_FOP_NOTIFY_START = 5,\n\tMEI_FOP_NOTIFY_STOP = 6,\n\tMEI_FOP_DMA_MAP = 7,\n\tMEI_FOP_DMA_UNMAP = 8,\n};\n\nenum mei_cfg_idx {\n\tMEI_ME_UNDEF_CFG = 0,\n\tMEI_ME_ICH_CFG = 1,\n\tMEI_ME_ICH10_CFG = 2,\n\tMEI_ME_PCH6_CFG = 3,\n\tMEI_ME_PCH7_CFG = 4,\n\tMEI_ME_PCH_CPT_PBG_CFG = 5,\n\tMEI_ME_PCH8_CFG = 6,\n\tMEI_ME_PCH8_ITOUCH_CFG = 7,\n\tMEI_ME_PCH8_SPS_4_CFG = 8,\n\tMEI_ME_PCH12_CFG = 9,\n\tMEI_ME_PCH12_SPS_4_CFG = 10,\n\tMEI_ME_PCH12_SPS_CFG = 11,\n\tMEI_ME_PCH12_SPS_ITOUCH_CFG = 12,\n\tMEI_ME_PCH15_CFG = 13,\n\tMEI_ME_PCH15_SPS_CFG = 14,\n\tMEI_ME_GSC_CFG = 15,\n\tMEI_ME_GSCFI_CFG = 16,\n\tMEI_ME_NUM_CFG = 17,\n};\n\nenum mei_cl_connect_status {\n\tMEI_CL_CONN_SUCCESS = 0,\n\tMEI_CL_CONN_NOT_FOUND = 1,\n\tMEI_CL_CONN_ALREADY_STARTED = 2,\n\tMEI_CL_CONN_OUT_OF_RESOURCES = 3,\n\tMEI_CL_CONN_MESSAGE_SMALL = 4,\n\tMEI_CL_CONN_NOT_ALLOWED = 5,\n};\n\nenum mei_cl_disconnect_status {\n\tMEI_CL_DISCONN_SUCCESS = 0,\n};\n\nenum mei_cl_io_mode {\n\tMEI_CL_IO_TX_BLOCKING = 1,\n\tMEI_CL_IO_TX_INTERNAL = 2,\n\tMEI_CL_IO_RX_NONBLOCK = 4,\n\tMEI_CL_IO_SGL = 8,\n};\n\nenum mei_dev_pxp_mode {\n\tMEI_DEV_PXP_DEFAULT = 0,\n\tMEI_DEV_PXP_INIT = 1,\n\tMEI_DEV_PXP_SETUP = 2,\n\tMEI_DEV_PXP_READY = 3,\n};\n\nenum mei_dev_reset_to_pxp {\n\tMEI_DEV_RESET_TO_PXP_DEFAULT = 0,\n\tMEI_DEV_RESET_TO_PXP_PERFORMED = 1,\n\tMEI_DEV_RESET_TO_PXP_DONE = 2,\n};\n\nenum mei_dev_state {\n\tMEI_DEV_UNINITIALIZED = 0,\n\tMEI_DEV_INITIALIZING = 1,\n\tMEI_DEV_INIT_CLIENTS = 2,\n\tMEI_DEV_ENABLED = 3,\n\tMEI_DEV_RESETTING = 4,\n\tMEI_DEV_DISABLED = 5,\n\tMEI_DEV_POWERING_DOWN = 6,\n\tMEI_DEV_POWER_DOWN = 7,\n\tMEI_DEV_POWER_UP = 8,\n};\n\nenum mei_ext_hdr_type {\n\tMEI_EXT_HDR_NONE = 0,\n\tMEI_EXT_HDR_VTAG = 1,\n\tMEI_EXT_HDR_GSC = 2,\n};\n\nenum mei_file_transaction_states {\n\tMEI_IDLE = 0,\n\tMEI_WRITING = 1,\n\tMEI_WRITE_COMPLETE = 2,\n};\n\nenum mei_hbm_state {\n\tMEI_HBM_IDLE = 0,\n\tMEI_HBM_STARTING = 1,\n\tMEI_HBM_CAP_SETUP = 2,\n\tMEI_HBM_DR_SETUP = 3,\n\tMEI_HBM_ENUM_CLIENTS = 4,\n\tMEI_HBM_CLIENT_PROPERTIES = 5,\n\tMEI_HBM_STARTED = 6,\n\tMEI_HBM_STOPPED = 7,\n};\n\nenum mei_hbm_status {\n\tMEI_HBMS_SUCCESS = 0,\n\tMEI_HBMS_CLIENT_NOT_FOUND = 1,\n\tMEI_HBMS_ALREADY_EXISTS = 2,\n\tMEI_HBMS_REJECTED = 3,\n\tMEI_HBMS_INVALID_PARAMETER = 4,\n\tMEI_HBMS_NOT_ALLOWED = 5,\n\tMEI_HBMS_ALREADY_STARTED = 6,\n\tMEI_HBMS_NOT_STARTED = 7,\n\tMEI_HBMS_MAX = 8,\n};\n\nenum mei_pg_event {\n\tMEI_PG_EVENT_IDLE = 0,\n\tMEI_PG_EVENT_WAIT = 1,\n\tMEI_PG_EVENT_RECEIVED = 2,\n\tMEI_PG_EVENT_INTR_WAIT = 3,\n\tMEI_PG_EVENT_INTR_RECEIVED = 4,\n};\n\nenum mei_pg_state {\n\tMEI_PG_OFF = 0,\n\tMEI_PG_ON = 1,\n};\n\nenum mei_stop_reason_types {\n\tDRIVER_STOP_REQUEST = 0,\n\tDEVICE_D1_ENTRY = 1,\n\tDEVICE_D2_ENTRY = 2,\n\tDEVICE_D3_ENTRY = 3,\n\tSYSTEM_S1_ENTRY = 4,\n\tSYSTEM_S2_ENTRY = 5,\n\tSYSTEM_S3_ENTRY = 6,\n\tSYSTEM_S4_ENTRY = 7,\n\tSYSTEM_S5_ENTRY = 8,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 51,\n\tMEMCG_SOCK = 52,\n\tMEMCG_PERCPU_B = 53,\n\tMEMCG_VMALLOC = 54,\n\tMEMCG_KMEM = 55,\n\tMEMCG_ZSWAP_B = 56,\n\tMEMCG_ZSWAPPED = 57,\n\tMEMCG_NR_STAT = 58,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum mesh_path_flags {\n\tMESH_PATH_ACTIVE = 1,\n\tMESH_PATH_RESOLVING = 2,\n\tMESH_PATH_SN_VALID = 4,\n\tMESH_PATH_FIXED = 8,\n\tMESH_PATH_RESOLVED = 16,\n\tMESH_PATH_REQ_QUEUED = 32,\n\tMESH_PATH_DELETED = 64,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mext_move_type {\n\tMEXT_SKIP_EXTENT = 0,\n\tMEXT_MOVE_EXTENT = 1,\n\tMEXT_COPY_DATA = 2,\n};\n\nenum mf_flags {\n\tMF_COUNT_INCREASED = 1,\n\tMF_ACTION_REQUIRED = 2,\n\tMF_MUST_KILL = 4,\n\tMF_SOFT_OFFLINE = 8,\n\tMF_UNPOISON = 16,\n\tMF_SW_SIMULATED = 32,\n\tMF_NO_RETRY = 64,\n\tMF_MEM_PRE_REMOVE = 128,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\t__MIGRATE_TYPE_END = 3,\n\tMIGRATE_TYPES = 4,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum minstrel_sample_type {\n\tMINSTREL_SAMPLE_TYPE_INC = 0,\n\tMINSTREL_SAMPLE_TYPE_JUMP = 1,\n\tMINSTREL_SAMPLE_TYPE_SLOW = 2,\n\t__MINSTREL_SAMPLE_TYPE_MAX = 3,\n};\n\nenum mipi_dsi_compression_algo {\n\tMIPI_DSI_COMPRESSION_DSC = 0,\n\tMIPI_DSI_COMPRESSION_VENDOR = 3,\n};\n\nenum mipi_dsi_dcs_tear_mode {\n\tMIPI_DSI_DCS_TEAR_MODE_VBLANK = 0,\n\tMIPI_DSI_DCS_TEAR_MODE_VHBLANK = 1,\n};\n\nenum mipi_dsi_pixel_format {\n\tMIPI_DSI_FMT_RGB888 = 0,\n\tMIPI_DSI_FMT_RGB666 = 1,\n\tMIPI_DSI_FMT_RGB666_PACKED = 2,\n\tMIPI_DSI_FMT_RGB565 = 3,\n};\n\nenum mipi_seq {\n\tMIPI_SEQ_END = 0,\n\tMIPI_SEQ_DEASSERT_RESET = 1,\n\tMIPI_SEQ_INIT_OTP = 2,\n\tMIPI_SEQ_DISPLAY_ON = 3,\n\tMIPI_SEQ_DISPLAY_OFF = 4,\n\tMIPI_SEQ_ASSERT_RESET = 5,\n\tMIPI_SEQ_BACKLIGHT_ON = 6,\n\tMIPI_SEQ_BACKLIGHT_OFF = 7,\n\tMIPI_SEQ_TEAR_ON = 8,\n\tMIPI_SEQ_TEAR_OFF = 9,\n\tMIPI_SEQ_POWER_ON = 10,\n\tMIPI_SEQ_POWER_OFF = 11,\n\tMIPI_SEQ_MAX = 12,\n};\n\nenum mipi_seq_element {\n\tMIPI_SEQ_ELEM_END = 0,\n\tMIPI_SEQ_ELEM_SEND_PKT = 1,\n\tMIPI_SEQ_ELEM_DELAY = 2,\n\tMIPI_SEQ_ELEM_GPIO = 3,\n\tMIPI_SEQ_ELEM_I2C = 4,\n\tMIPI_SEQ_ELEM_SPI = 5,\n\tMIPI_SEQ_ELEM_PMIC = 6,\n\tMIPI_SEQ_ELEM_MAX = 7,\n};\n\nenum misc_res_type {\n\tMISC_CG_RES_TYPES = 0,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mmio_mitigations {\n\tMMIO_MITIGATION_OFF = 0,\n\tMMIO_MITIGATION_AUTO = 1,\n\tMMIO_MITIGATION_UCODE_NEEDED = 2,\n\tMMIO_MITIGATION_VERW = 3,\n};\n\nenum mmu_notifier_event {\n\tMMU_NOTIFY_UNMAP = 0,\n\tMMU_NOTIFY_CLEAR = 1,\n\tMMU_NOTIFY_PROTECTION_VMA = 2,\n\tMMU_NOTIFY_PROTECTION_PAGE = 3,\n\tMMU_NOTIFY_SOFT_DIRTY = 4,\n\tMMU_NOTIFY_RELEASE = 5,\n\tMMU_NOTIFY_MIGRATE = 6,\n\tMMU_NOTIFY_EXCLUSIVE = 7,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum monitor_flags {\n\tMONITOR_FLAG_CHANGED = 1,\n\tMONITOR_FLAG_FCSFAIL = 2,\n\tMONITOR_FLAG_PLCPFAIL = 4,\n\tMONITOR_FLAG_CONTROL = 8,\n\tMONITOR_FLAG_OTHER_BSS = 16,\n\tMONITOR_FLAG_COOK_FRAMES = 32,\n\tMONITOR_FLAG_ACTIVE = 64,\n\tMONITOR_FLAG_SKIP_TX = 128,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mountstat {\n\tMNT_OK = 0,\n\tMNT_EPERM = 1,\n\tMNT_ENOENT = 2,\n\tMNT_EACCES = 13,\n\tMNT_EINVAL = 22,\n};\n\nenum mountstat3 {\n\tMNT3_OK = 0,\n\tMNT3ERR_PERM = 1,\n\tMNT3ERR_NOENT = 2,\n\tMNT3ERR_IO = 5,\n\tMNT3ERR_ACCES = 13,\n\tMNT3ERR_NOTDIR = 20,\n\tMNT3ERR_INVAL = 22,\n\tMNT3ERR_NAMETOOLONG = 63,\n\tMNT3ERR_NOTSUPP = 10004,\n\tMNT3ERR_SERVERFAULT = 10006,\n};\n\nenum mp_irq_source_types {\n\tmp_INT = 0,\n\tmp_NMI = 1,\n\tmp_SMI = 2,\n\tmp_ExtINT = 3,\n};\n\nenum mpath_info_flags {\n\tMPATH_INFO_FRAME_QLEN = 1,\n\tMPATH_INFO_SN = 2,\n\tMPATH_INFO_METRIC = 4,\n\tMPATH_INFO_EXPTIME = 8,\n\tMPATH_INFO_DISCOVERY_TIMEOUT = 16,\n\tMPATH_INFO_DISCOVERY_RETRIES = 32,\n\tMPATH_INFO_FLAGS = 64,\n\tMPATH_INFO_HOP_COUNT = 128,\n\tMPATH_INFO_PATH_CHANGE = 256,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum net_xmit_qdisc_t {\n\t__NET_XMIT_STOLEN = 65536,\n\t__NET_XMIT_BYPASS = 131072,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_lag_hash {\n\tNETDEV_LAG_HASH_NONE = 0,\n\tNETDEV_LAG_HASH_L2 = 1,\n\tNETDEV_LAG_HASH_L34 = 2,\n\tNETDEV_LAG_HASH_L23 = 3,\n\tNETDEV_LAG_HASH_E23 = 4,\n\tNETDEV_LAG_HASH_E34 = 5,\n\tNETDEV_LAG_HASH_VLAN_SRCMAC = 6,\n\tNETDEV_LAG_HASH_UNKNOWN = 7,\n};\n\nenum netdev_lag_tx_type {\n\tNETDEV_LAG_TX_TYPE_UNKNOWN = 0,\n\tNETDEV_LAG_TX_TYPE_RANDOM = 1,\n\tNETDEV_LAG_TX_TYPE_BROADCAST = 2,\n\tNETDEV_LAG_TX_TYPE_ROUNDROBIN = 3,\n\tNETDEV_LAG_TX_TYPE_ACTIVEBACKUP = 4,\n\tNETDEV_LAG_TX_TYPE_HASH = 5,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netfs_collect_contig_trace {\n\tnetfs_contig_trace_collect = 0,\n\tnetfs_contig_trace_jump = 1,\n\tnetfs_contig_trace_unlock = 2,\n} __attribute__((mode(byte)));\n\nenum netfs_donate_trace {\n\tnetfs_trace_donate_tail_to_prev = 0,\n\tnetfs_trace_donate_to_prev = 1,\n\tnetfs_trace_donate_to_next = 2,\n\tnetfs_trace_donate_to_deferred_next = 3,\n} __attribute__((mode(byte)));\n\nenum netfs_failure {\n\tnetfs_fail_check_write_begin = 0,\n\tnetfs_fail_copy_to_cache = 1,\n\tnetfs_fail_dio_read_short = 2,\n\tnetfs_fail_dio_read_zero = 3,\n\tnetfs_fail_read = 4,\n\tnetfs_fail_short_read = 5,\n\tnetfs_fail_prepare_write = 6,\n\tnetfs_fail_write = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_folio_trace {\n\tnetfs_folio_is_uptodate = 0,\n\tnetfs_just_prefetch = 1,\n\tnetfs_whole_folio_modify = 2,\n\tnetfs_modify_and_clear = 3,\n\tnetfs_streaming_write = 4,\n\tnetfs_streaming_write_cont = 5,\n\tnetfs_flush_content = 6,\n\tnetfs_streaming_filled_page = 7,\n\tnetfs_streaming_cont_filled_page = 8,\n\tnetfs_folio_trace_abandon = 9,\n\tnetfs_folio_trace_alloc_buffer = 10,\n\tnetfs_folio_trace_cancel_copy = 11,\n\tnetfs_folio_trace_cancel_store = 12,\n\tnetfs_folio_trace_clear = 13,\n\tnetfs_folio_trace_clear_cc = 14,\n\tnetfs_folio_trace_clear_g = 15,\n\tnetfs_folio_trace_clear_s = 16,\n\tnetfs_folio_trace_copy_to_cache = 17,\n\tnetfs_folio_trace_end_copy = 18,\n\tnetfs_folio_trace_filled_gaps = 19,\n\tnetfs_folio_trace_kill = 20,\n\tnetfs_folio_trace_kill_cc = 21,\n\tnetfs_folio_trace_kill_g = 22,\n\tnetfs_folio_trace_kill_s = 23,\n\tnetfs_folio_trace_mkwrite = 24,\n\tnetfs_folio_trace_mkwrite_plus = 25,\n\tnetfs_folio_trace_not_under_wback = 26,\n\tnetfs_folio_trace_not_locked = 27,\n\tnetfs_folio_trace_put = 28,\n\tnetfs_folio_trace_read = 29,\n\tnetfs_folio_trace_read_done = 30,\n\tnetfs_folio_trace_read_gaps = 31,\n\tnetfs_folio_trace_read_unlock = 32,\n\tnetfs_folio_trace_redirtied = 33,\n\tnetfs_folio_trace_store = 34,\n\tnetfs_folio_trace_store_copy = 35,\n\tnetfs_folio_trace_store_plus = 36,\n\tnetfs_folio_trace_wthru = 37,\n\tnetfs_folio_trace_wthru_plus = 38,\n} __attribute__((mode(byte)));\n\nenum netfs_folioq_trace {\n\tnetfs_trace_folioq_alloc_buffer = 0,\n\tnetfs_trace_folioq_clear = 1,\n\tnetfs_trace_folioq_delete = 2,\n\tnetfs_trace_folioq_make_space = 3,\n\tnetfs_trace_folioq_rollbuf_init = 4,\n\tnetfs_trace_folioq_read_progress = 5,\n} __attribute__((mode(byte)));\n\nenum netfs_io_origin {\n\tNETFS_READAHEAD = 0,\n\tNETFS_READPAGE = 1,\n\tNETFS_READ_GAPS = 2,\n\tNETFS_READ_SINGLE = 3,\n\tNETFS_READ_FOR_WRITE = 4,\n\tNETFS_UNBUFFERED_READ = 5,\n\tNETFS_DIO_READ = 6,\n\tNETFS_WRITEBACK = 7,\n\tNETFS_WRITEBACK_SINGLE = 8,\n\tNETFS_WRITETHROUGH = 9,\n\tNETFS_UNBUFFERED_WRITE = 10,\n\tNETFS_DIO_WRITE = 11,\n\tNETFS_PGPRIV2_COPY_TO_CACHE = 12,\n\tnr__netfs_io_origin = 13,\n} __attribute__((mode(byte)));\n\nenum netfs_io_source {\n\tNETFS_SOURCE_UNKNOWN = 0,\n\tNETFS_FILL_WITH_ZEROES = 1,\n\tNETFS_DOWNLOAD_FROM_SERVER = 2,\n\tNETFS_READ_FROM_CACHE = 3,\n\tNETFS_INVALID_READ = 4,\n\tNETFS_UPLOAD_TO_SERVER = 5,\n\tNETFS_WRITE_TO_CACHE = 6,\n} __attribute__((mode(byte)));\n\nenum netfs_read_from_hole {\n\tNETFS_READ_HOLE_IGNORE = 0,\n\tNETFS_READ_HOLE_FAIL = 1,\n};\n\nenum netfs_read_trace {\n\tnetfs_read_trace_dio_read = 0,\n\tnetfs_read_trace_expanded = 1,\n\tnetfs_read_trace_readahead = 2,\n\tnetfs_read_trace_readpage = 3,\n\tnetfs_read_trace_read_gaps = 4,\n\tnetfs_read_trace_read_single = 5,\n\tnetfs_read_trace_prefetch_for_write = 6,\n\tnetfs_read_trace_write_begin = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_ref_trace {\n\tnetfs_rreq_trace_get_for_outstanding = 0,\n\tnetfs_rreq_trace_get_subreq = 1,\n\tnetfs_rreq_trace_put_complete = 2,\n\tnetfs_rreq_trace_put_discard = 3,\n\tnetfs_rreq_trace_put_failed = 4,\n\tnetfs_rreq_trace_put_no_submit = 5,\n\tnetfs_rreq_trace_put_return = 6,\n\tnetfs_rreq_trace_put_subreq = 7,\n\tnetfs_rreq_trace_put_work_ip = 8,\n\tnetfs_rreq_trace_see_work = 9,\n\tnetfs_rreq_trace_see_work_complete = 10,\n\tnetfs_rreq_trace_new = 11,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_trace {\n\tnetfs_rreq_trace_assess = 0,\n\tnetfs_rreq_trace_collect = 1,\n\tnetfs_rreq_trace_complete = 2,\n\tnetfs_rreq_trace_copy = 3,\n\tnetfs_rreq_trace_dirty = 4,\n\tnetfs_rreq_trace_done = 5,\n\tnetfs_rreq_trace_end_copy_to_cache = 6,\n\tnetfs_rreq_trace_free = 7,\n\tnetfs_rreq_trace_intr = 8,\n\tnetfs_rreq_trace_ki_complete = 9,\n\tnetfs_rreq_trace_recollect = 10,\n\tnetfs_rreq_trace_redirty = 11,\n\tnetfs_rreq_trace_resubmit = 12,\n\tnetfs_rreq_trace_set_abandon = 13,\n\tnetfs_rreq_trace_set_pause = 14,\n\tnetfs_rreq_trace_unlock = 15,\n\tnetfs_rreq_trace_unlock_pgpriv2 = 16,\n\tnetfs_rreq_trace_unmark = 17,\n\tnetfs_rreq_trace_unpause = 18,\n\tnetfs_rreq_trace_wait_ip = 19,\n\tnetfs_rreq_trace_wait_pause = 20,\n\tnetfs_rreq_trace_wait_quiesce = 21,\n\tnetfs_rreq_trace_waited_ip = 22,\n\tnetfs_rreq_trace_waited_pause = 23,\n\tnetfs_rreq_trace_waited_quiesce = 24,\n\tnetfs_rreq_trace_wake_ip = 25,\n\tnetfs_rreq_trace_wake_queue = 26,\n\tnetfs_rreq_trace_write_done = 27,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_ref_trace {\n\tnetfs_sreq_trace_get_copy_to_cache = 0,\n\tnetfs_sreq_trace_get_resubmit = 1,\n\tnetfs_sreq_trace_get_submit = 2,\n\tnetfs_sreq_trace_get_short_read = 3,\n\tnetfs_sreq_trace_new = 4,\n\tnetfs_sreq_trace_put_abandon = 5,\n\tnetfs_sreq_trace_put_cancel = 6,\n\tnetfs_sreq_trace_put_clear = 7,\n\tnetfs_sreq_trace_put_consumed = 8,\n\tnetfs_sreq_trace_put_done = 9,\n\tnetfs_sreq_trace_put_failed = 10,\n\tnetfs_sreq_trace_put_merged = 11,\n\tnetfs_sreq_trace_put_no_copy = 12,\n\tnetfs_sreq_trace_put_oom = 13,\n\tnetfs_sreq_trace_put_wip = 14,\n\tnetfs_sreq_trace_put_work = 15,\n\tnetfs_sreq_trace_put_terminated = 16,\n\tnetfs_sreq_trace_see_failed = 17,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_trace {\n\tnetfs_sreq_trace_abandoned = 0,\n\tnetfs_sreq_trace_add_donations = 1,\n\tnetfs_sreq_trace_added = 2,\n\tnetfs_sreq_trace_cache_nowrite = 3,\n\tnetfs_sreq_trace_cache_prepare = 4,\n\tnetfs_sreq_trace_cache_write = 5,\n\tnetfs_sreq_trace_cancel = 6,\n\tnetfs_sreq_trace_clear = 7,\n\tnetfs_sreq_trace_consumed = 8,\n\tnetfs_sreq_trace_discard = 9,\n\tnetfs_sreq_trace_donate_to_prev = 10,\n\tnetfs_sreq_trace_donate_to_next = 11,\n\tnetfs_sreq_trace_download_instead = 12,\n\tnetfs_sreq_trace_fail = 13,\n\tnetfs_sreq_trace_free = 14,\n\tnetfs_sreq_trace_hit_eof = 15,\n\tnetfs_sreq_trace_io_bad = 16,\n\tnetfs_sreq_trace_io_malformed = 17,\n\tnetfs_sreq_trace_io_unknown = 18,\n\tnetfs_sreq_trace_io_progress = 19,\n\tnetfs_sreq_trace_io_req_submitted = 20,\n\tnetfs_sreq_trace_io_retry_needed = 21,\n\tnetfs_sreq_trace_limited = 22,\n\tnetfs_sreq_trace_need_clear = 23,\n\tnetfs_sreq_trace_partial_read = 24,\n\tnetfs_sreq_trace_need_retry = 25,\n\tnetfs_sreq_trace_prepare = 26,\n\tnetfs_sreq_trace_prep_failed = 27,\n\tnetfs_sreq_trace_progress = 28,\n\tnetfs_sreq_trace_reprep_failed = 29,\n\tnetfs_sreq_trace_retry = 30,\n\tnetfs_sreq_trace_short = 31,\n\tnetfs_sreq_trace_split = 32,\n\tnetfs_sreq_trace_submit = 33,\n\tnetfs_sreq_trace_superfluous = 34,\n\tnetfs_sreq_trace_terminated = 35,\n\tnetfs_sreq_trace_wait_for = 36,\n\tnetfs_sreq_trace_write = 37,\n\tnetfs_sreq_trace_write_skip = 38,\n\tnetfs_sreq_trace_write_term = 39,\n} __attribute__((mode(byte)));\n\nenum netfs_write_trace {\n\tnetfs_write_trace_copy_to_cache = 0,\n\tnetfs_write_trace_dio_write = 1,\n\tnetfs_write_trace_unbuffered_write = 2,\n\tnetfs_write_trace_writeback = 3,\n\tnetfs_write_trace_writeback_single = 4,\n\tnetfs_write_trace_writethrough = 5,\n} __attribute__((mode(byte)));\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_ct_ecache_state {\n\tNFCT_ECACHE_DESTROY_FAIL = 0,\n\tNFCT_ECACHE_DESTROY_SENT = 1,\n};\n\nenum nf_ct_ext_id {\n\tNF_CT_EXT_HELPER = 0,\n\tNF_CT_EXT_NAT = 1,\n\tNF_CT_EXT_SEQADJ = 2,\n\tNF_CT_EXT_ACCT = 3,\n\tNF_CT_EXT_NUM = 4,\n};\n\nenum nf_ct_ftp_type {\n\tNF_CT_FTP_PORT = 0,\n\tNF_CT_FTP_PASV = 1,\n\tNF_CT_FTP_EPRT = 2,\n\tNF_CT_FTP_EPSV = 3,\n};\n\nenum nf_ct_helper_flags {\n\tNF_CT_HELPER_F_USERSPACE = 1,\n\tNF_CT_HELPER_F_CONFIGURED = 2,\n};\n\nenum nf_ct_sysctl_index {\n\tNF_SYSCTL_CT_MAX = 0,\n\tNF_SYSCTL_CT_COUNT = 1,\n\tNF_SYSCTL_CT_BUCKETS = 2,\n\tNF_SYSCTL_CT_CHECKSUM = 3,\n\tNF_SYSCTL_CT_LOG_INVALID = 4,\n\tNF_SYSCTL_CT_EXPECT_MAX = 5,\n\tNF_SYSCTL_CT_ACCT = 6,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_GENERIC = 7,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_SYN_SENT = 8,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_SYN_RECV = 9,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_ESTABLISHED = 10,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_FIN_WAIT = 11,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE_WAIT = 12,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_LAST_ACK = 13,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_TIME_WAIT = 14,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE = 15,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_RETRANS = 16,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_UNACK = 17,\n\tNF_SYSCTL_CT_PROTO_TCP_LOOSE = 18,\n\tNF_SYSCTL_CT_PROTO_TCP_LIBERAL = 19,\n\tNF_SYSCTL_CT_PROTO_TCP_IGNORE_INVALID_RST = 20,\n\tNF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS = 21,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP = 22,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM = 23,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_ICMP = 24,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6 = 25,\n\tNF_SYSCTL_CT_LAST_SYSCTL = 26,\n};\n\nenum nf_ct_tcp_action {\n\tNFCT_TCP_IGNORE = 0,\n\tNFCT_TCP_INVALID = 1,\n\tNFCT_TCP_ACCEPT = 2,\n};\n\nenum nf_dev_hooks {\n\tNF_NETDEV_INGRESS = 0,\n\tNF_NETDEV_EGRESS = 1,\n\tNF_NETDEV_NUMHOOKS = 2,\n};\n\nenum nf_hook_ops_type {\n\tNF_HOOK_OP_UNDEFINED = 0,\n\tNF_HOOK_OP_NF_TABLES = 1,\n\tNF_HOOK_OP_BPF = 2,\n\tNF_HOOK_OP_NFT_FT = 3,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nf_ip6_hook_priorities {\n\tNF_IP6_PRI_FIRST = -2147483648,\n\tNF_IP6_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP6_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP6_PRI_RAW = -300,\n\tNF_IP6_PRI_SELINUX_FIRST = -225,\n\tNF_IP6_PRI_CONNTRACK = -200,\n\tNF_IP6_PRI_MANGLE = -150,\n\tNF_IP6_PRI_NAT_DST = -100,\n\tNF_IP6_PRI_FILTER = 0,\n\tNF_IP6_PRI_SECURITY = 50,\n\tNF_IP6_PRI_NAT_SRC = 100,\n\tNF_IP6_PRI_SELINUX_LAST = 225,\n\tNF_IP6_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP6_PRI_LAST = 2147483647,\n};\n\nenum nf_ip_hook_priorities {\n\tNF_IP_PRI_FIRST = -2147483648,\n\tNF_IP_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP_PRI_RAW = -300,\n\tNF_IP_PRI_SELINUX_FIRST = -225,\n\tNF_IP_PRI_CONNTRACK = -200,\n\tNF_IP_PRI_MANGLE = -150,\n\tNF_IP_PRI_NAT_DST = -100,\n\tNF_IP_PRI_FILTER = 0,\n\tNF_IP_PRI_SECURITY = 50,\n\tNF_IP_PRI_NAT_SRC = 100,\n\tNF_IP_PRI_SELINUX_LAST = 225,\n\tNF_IP_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP_PRI_CONNTRACK_CONFIRM = 2147483647,\n\tNF_IP_PRI_LAST = 2147483647,\n};\n\nenum nf_log_type {\n\tNF_LOG_TYPE_LOG = 0,\n\tNF_LOG_TYPE_ULOG = 1,\n\tNF_LOG_TYPE_MAX = 2,\n};\n\nenum nf_nat_manip_type {\n\tNF_NAT_MANIP_SRC = 0,\n\tNF_NAT_MANIP_DST = 1,\n};\n\nenum nfnetlink_groups {\n\tNFNLGRP_NONE = 0,\n\tNFNLGRP_CONNTRACK_NEW = 1,\n\tNFNLGRP_CONNTRACK_UPDATE = 2,\n\tNFNLGRP_CONNTRACK_DESTROY = 3,\n\tNFNLGRP_CONNTRACK_EXP_NEW = 4,\n\tNFNLGRP_CONNTRACK_EXP_UPDATE = 5,\n\tNFNLGRP_CONNTRACK_EXP_DESTROY = 6,\n\tNFNLGRP_NFTABLES = 7,\n\tNFNLGRP_ACCT_QUOTA = 8,\n\tNFNLGRP_NFTRACE = 9,\n\t__NFNLGRP_MAX = 10,\n};\n\nenum nfnl_abort_action {\n\tNFNL_ABORT_NONE = 0,\n\tNFNL_ABORT_AUTOLOAD = 1,\n\tNFNL_ABORT_VALIDATE = 2,\n};\n\nenum nfnl_batch_attributes {\n\tNFNL_BATCH_UNSPEC = 0,\n\tNFNL_BATCH_GENID = 1,\n\t__NFNL_BATCH_MAX = 2,\n};\n\nenum nfnl_callback_type {\n\tNFNL_CB_UNSPEC = 0,\n\tNFNL_CB_MUTEX = 1,\n\tNFNL_CB_RCU = 2,\n\tNFNL_CB_BATCH = 3,\n};\n\nenum nfs3_createmode {\n\tNFS3_CREATE_UNCHECKED = 0,\n\tNFS3_CREATE_GUARDED = 1,\n\tNFS3_CREATE_EXCLUSIVE = 2,\n};\n\nenum nfs3_ftype {\n\tNF3NON = 0,\n\tNF3REG = 1,\n\tNF3DIR = 2,\n\tNF3BLK = 3,\n\tNF3CHR = 4,\n\tNF3LNK = 5,\n\tNF3SOCK = 6,\n\tNF3FIFO = 7,\n\tNF3BAD = 8,\n};\n\nenum nfs3_stable_how {\n\tNFS_UNSTABLE = 0,\n\tNFS_DATA_SYNC = 1,\n\tNFS_FILE_SYNC = 2,\n\tNFS_INVALID_STABLE_HOW = -1,\n};\n\nenum nfs4_acl_type {\n\tNFS4ACL_NONE = 0,\n\tNFS4ACL_ACL = 1,\n\tNFS4ACL_DACL = 2,\n\tNFS4ACL_SACL = 3,\n};\n\nenum nfs4_callback_procnum {\n\tCB_NULL = 0,\n\tCB_COMPOUND = 1,\n};\n\nenum nfs4_change_attr_type {\n\tNFS4_CHANGE_TYPE_IS_MONOTONIC_INCR = 0,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER = 1,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER_NOPNFS = 2,\n\tNFS4_CHANGE_TYPE_IS_TIME_METADATA = 3,\n\tNFS4_CHANGE_TYPE_IS_UNDEFINED = 4,\n};\n\nenum nfs4_client_state {\n\tNFS4CLNT_MANAGER_RUNNING = 0,\n\tNFS4CLNT_CHECK_LEASE = 1,\n\tNFS4CLNT_LEASE_EXPIRED = 2,\n\tNFS4CLNT_RECLAIM_REBOOT = 3,\n\tNFS4CLNT_RECLAIM_NOGRACE = 4,\n\tNFS4CLNT_DELEGRETURN = 5,\n\tNFS4CLNT_SESSION_RESET = 6,\n\tNFS4CLNT_LEASE_CONFIRM = 7,\n\tNFS4CLNT_SERVER_SCOPE_MISMATCH = 8,\n\tNFS4CLNT_PURGE_STATE = 9,\n\tNFS4CLNT_BIND_CONN_TO_SESSION = 10,\n\tNFS4CLNT_MOVED = 11,\n\tNFS4CLNT_LEASE_MOVED = 12,\n\tNFS4CLNT_DELEGATION_EXPIRED = 13,\n\tNFS4CLNT_RUN_MANAGER = 14,\n\tNFS4CLNT_MANAGER_AVAILABLE = 15,\n\tNFS4CLNT_RECALL_RUNNING = 16,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_READ = 17,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_RW = 18,\n\tNFS4CLNT_DELEGRETURN_DELAYED = 19,\n};\n\nenum nfs4_ff_op_type {\n\tNFS4_FF_OP_LAYOUTSTATS = 0,\n\tNFS4_FF_OP_LAYOUTRETURN = 1,\n};\n\nenum nfs4_open_delegation_type4 {\n\tNFS4_OPEN_DELEGATE_NONE = 0,\n\tNFS4_OPEN_DELEGATE_READ = 1,\n\tNFS4_OPEN_DELEGATE_WRITE = 2,\n\tNFS4_OPEN_DELEGATE_NONE_EXT = 3,\n\tNFS4_OPEN_DELEGATE_READ_ATTRS_DELEG = 4,\n\tNFS4_OPEN_DELEGATE_WRITE_ATTRS_DELEG = 5,\n};\n\nenum nfs4_session_state {\n\tNFS4_SESSION_INITING = 0,\n\tNFS4_SESSION_ESTABLISHED = 1,\n};\n\nenum nfs4_slot_tbl_state {\n\tNFS4_SLOT_TBL_DRAINING = 0,\n};\n\nenum nfs_cb_opnum4 {\n\tOP_CB_GETATTR = 3,\n\tOP_CB_RECALL = 4,\n\tOP_CB_LAYOUTRECALL = 5,\n\tOP_CB_NOTIFY = 6,\n\tOP_CB_PUSH_DELEG = 7,\n\tOP_CB_RECALL_ANY = 8,\n\tOP_CB_RECALLABLE_OBJ_AVAIL = 9,\n\tOP_CB_RECALL_SLOT = 10,\n\tOP_CB_SEQUENCE = 11,\n\tOP_CB_WANTS_CANCELLED = 12,\n\tOP_CB_NOTIFY_LOCK = 13,\n\tOP_CB_NOTIFY_DEVICEID = 14,\n\tOP_CB_OFFLOAD = 15,\n\tOP_CB_ILLEGAL = 10044,\n};\n\nenum nfs_ftype4 {\n\tNF4BAD = 0,\n\tNF4REG = 1,\n\tNF4DIR = 2,\n\tNF4BLK = 3,\n\tNF4CHR = 4,\n\tNF4LNK = 5,\n\tNF4SOCK = 6,\n\tNF4FIFO = 7,\n\tNF4ATTRDIR = 8,\n\tNF4NAMEDATTR = 9,\n};\n\nenum nfs_lock_status {\n\tNFS_LOCK_NOT_SET = 0,\n\tNFS_LOCK_LOCK = 1,\n\tNFS_LOCK_NOLOCK = 2,\n};\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nfs_param {\n\tOpt_ac = 0,\n\tOpt_acdirmax = 1,\n\tOpt_acdirmin = 2,\n\tOpt_acl___2 = 3,\n\tOpt_acregmax = 4,\n\tOpt_acregmin = 5,\n\tOpt_actimeo = 6,\n\tOpt_addr = 7,\n\tOpt_bg = 8,\n\tOpt_bsize = 9,\n\tOpt_clientaddr = 10,\n\tOpt_cto = 11,\n\tOpt_alignwrite = 12,\n\tOpt_fatal_neterrors = 13,\n\tOpt_fg = 14,\n\tOpt_fscache = 15,\n\tOpt_fscache_flag = 16,\n\tOpt_hard = 17,\n\tOpt_intr = 18,\n\tOpt_local_lock = 19,\n\tOpt_lock = 20,\n\tOpt_lookupcache = 21,\n\tOpt_migration = 22,\n\tOpt_minorversion = 23,\n\tOpt_mountaddr = 24,\n\tOpt_mounthost = 25,\n\tOpt_mountport = 26,\n\tOpt_mountproto = 27,\n\tOpt_mountvers = 28,\n\tOpt_namelen = 29,\n\tOpt_nconnect = 30,\n\tOpt_max_connect = 31,\n\tOpt_port___2 = 32,\n\tOpt_posix = 33,\n\tOpt_proto = 34,\n\tOpt_rdirplus = 35,\n\tOpt_rdirplus_none = 36,\n\tOpt_rdirplus_force = 37,\n\tOpt_rdma = 38,\n\tOpt_resvport = 39,\n\tOpt_retrans = 40,\n\tOpt_retry = 41,\n\tOpt_rsize = 42,\n\tOpt_sec = 43,\n\tOpt_sharecache = 44,\n\tOpt_sloppy = 45,\n\tOpt_soft = 46,\n\tOpt_softerr = 47,\n\tOpt_softreval = 48,\n\tOpt_source___3 = 49,\n\tOpt_tcp = 50,\n\tOpt_timeo = 51,\n\tOpt_trunkdiscovery = 52,\n\tOpt_udp = 53,\n\tOpt_v = 54,\n\tOpt_vers = 55,\n\tOpt_wsize = 56,\n\tOpt_write = 57,\n\tOpt_xprtsec = 58,\n\tOpt_cert_serial = 59,\n\tOpt_privkey_serial = 60,\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nenum nfs_stat_bytecounters {\n\tNFSIOS_NORMALREADBYTES = 0,\n\tNFSIOS_NORMALWRITTENBYTES = 1,\n\tNFSIOS_DIRECTREADBYTES = 2,\n\tNFSIOS_DIRECTWRITTENBYTES = 3,\n\tNFSIOS_SERVERREADBYTES = 4,\n\tNFSIOS_SERVERWRITTENBYTES = 5,\n\tNFSIOS_READPAGES = 6,\n\tNFSIOS_WRITEPAGES = 7,\n\t__NFSIOS_BYTESMAX = 8,\n};\n\nenum nfs_stat_eventcounters {\n\tNFSIOS_INODEREVALIDATE = 0,\n\tNFSIOS_DENTRYREVALIDATE = 1,\n\tNFSIOS_DATAINVALIDATE = 2,\n\tNFSIOS_ATTRINVALIDATE = 3,\n\tNFSIOS_VFSOPEN = 4,\n\tNFSIOS_VFSLOOKUP = 5,\n\tNFSIOS_VFSACCESS = 6,\n\tNFSIOS_VFSUPDATEPAGE = 7,\n\tNFSIOS_VFSREADPAGE = 8,\n\tNFSIOS_VFSREADPAGES = 9,\n\tNFSIOS_VFSWRITEPAGE = 10,\n\tNFSIOS_VFSWRITEPAGES = 11,\n\tNFSIOS_VFSGETDENTS = 12,\n\tNFSIOS_VFSSETATTR = 13,\n\tNFSIOS_VFSFLUSH = 14,\n\tNFSIOS_VFSFSYNC = 15,\n\tNFSIOS_VFSLOCK = 16,\n\tNFSIOS_VFSRELEASE = 17,\n\tNFSIOS_CONGESTIONWAIT = 18,\n\tNFSIOS_SETATTRTRUNC = 19,\n\tNFSIOS_EXTENDWRITE = 20,\n\tNFSIOS_SILLYRENAME = 21,\n\tNFSIOS_SHORTREAD = 22,\n\tNFSIOS_SHORTWRITE = 23,\n\tNFSIOS_DELAY = 24,\n\tNFSIOS_PNFS_READ = 25,\n\tNFSIOS_PNFS_WRITE = 26,\n\t__NFSIOS_COUNTSMAX = 27,\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n\tNFS4ERR_NOXATTR = 10095,\n\tNFS4ERR_XATTR2BIG = 10096,\n\tNFS4ERR_FIRST_FREE = 10097,\n};\n\nenum nfulnl_attr_config {\n\tNFULA_CFG_UNSPEC = 0,\n\tNFULA_CFG_CMD = 1,\n\tNFULA_CFG_MODE = 2,\n\tNFULA_CFG_NLBUFSIZ = 3,\n\tNFULA_CFG_TIMEOUT = 4,\n\tNFULA_CFG_QTHRESH = 5,\n\tNFULA_CFG_FLAGS = 6,\n\t__NFULA_CFG_MAX = 7,\n};\n\nenum nfulnl_attr_type {\n\tNFULA_UNSPEC = 0,\n\tNFULA_PACKET_HDR = 1,\n\tNFULA_MARK = 2,\n\tNFULA_TIMESTAMP = 3,\n\tNFULA_IFINDEX_INDEV = 4,\n\tNFULA_IFINDEX_OUTDEV = 5,\n\tNFULA_IFINDEX_PHYSINDEV = 6,\n\tNFULA_IFINDEX_PHYSOUTDEV = 7,\n\tNFULA_HWADDR = 8,\n\tNFULA_PAYLOAD = 9,\n\tNFULA_PREFIX = 10,\n\tNFULA_UID = 11,\n\tNFULA_SEQ = 12,\n\tNFULA_SEQ_GLOBAL = 13,\n\tNFULA_GID = 14,\n\tNFULA_HWTYPE = 15,\n\tNFULA_HWHEADER = 16,\n\tNFULA_HWLEN = 17,\n\tNFULA_CT = 18,\n\tNFULA_CT_INFO = 19,\n\tNFULA_VLAN = 20,\n\tNFULA_L2HDR = 21,\n\t__NFULA_MAX = 22,\n};\n\nenum nfulnl_msg_config_cmds {\n\tNFULNL_CFG_CMD_NONE = 0,\n\tNFULNL_CFG_CMD_BIND = 1,\n\tNFULNL_CFG_CMD_UNBIND = 2,\n\tNFULNL_CFG_CMD_PF_BIND = 3,\n\tNFULNL_CFG_CMD_PF_UNBIND = 4,\n};\n\nenum nfulnl_msg_types {\n\tNFULNL_MSG_PACKET = 0,\n\tNFULNL_MSG_CONFIG = 1,\n\tNFULNL_MSG_MAX = 2,\n};\n\nenum nfulnl_vlan_attr {\n\tNFULA_VLAN_UNSPEC = 0,\n\tNFULA_VLAN_PROTO = 1,\n\tNFULA_VLAN_TCI = 2,\n\t__NFULA_VLAN_MAX = 3,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nhlt_device_type {\n\tNHLT_DEVICE_BT = 0,\n\tNHLT_DEVICE_DMIC = 1,\n\tNHLT_DEVICE_I2S = 4,\n\tNHLT_DEVICE_INVALID = 5,\n};\n\nenum nhlt_link_type {\n\tNHLT_LINK_HDA = 0,\n\tNHLT_LINK_DSP = 1,\n\tNHLT_LINK_DMIC = 2,\n\tNHLT_LINK_SSP = 3,\n\tNHLT_LINK_INVALID = 4,\n};\n\nenum nl80211_ac {\n\tNL80211_AC_VO = 0,\n\tNL80211_AC_VI = 1,\n\tNL80211_AC_BE = 2,\n\tNL80211_AC_BK = 3,\n\tNL80211_NUM_ACS = 4,\n};\n\nenum nl80211_acl_policy {\n\tNL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED = 0,\n\tNL80211_ACL_POLICY_DENY_UNLESS_LISTED = 1,\n};\n\nenum nl80211_ap_settings_flags {\n\tNL80211_AP_SETTINGS_EXTERNAL_AUTH_SUPPORT = 1,\n\tNL80211_AP_SETTINGS_SA_QUERY_OFFLOAD_SUPPORT = 2,\n};\n\nenum nl80211_attr_coalesce_rule {\n\t__NL80211_COALESCE_RULE_INVALID = 0,\n\tNL80211_ATTR_COALESCE_RULE_DELAY = 1,\n\tNL80211_ATTR_COALESCE_RULE_CONDITION = 2,\n\tNL80211_ATTR_COALESCE_RULE_PKT_PATTERN = 3,\n\tNUM_NL80211_ATTR_COALESCE_RULE = 4,\n\tNL80211_ATTR_COALESCE_RULE_MAX = 3,\n};\n\nenum nl80211_attr_cqm {\n\t__NL80211_ATTR_CQM_INVALID = 0,\n\tNL80211_ATTR_CQM_RSSI_THOLD = 1,\n\tNL80211_ATTR_CQM_RSSI_HYST = 2,\n\tNL80211_ATTR_CQM_RSSI_THRESHOLD_EVENT = 3,\n\tNL80211_ATTR_CQM_PKT_LOSS_EVENT = 4,\n\tNL80211_ATTR_CQM_TXE_RATE = 5,\n\tNL80211_ATTR_CQM_TXE_PKTS = 6,\n\tNL80211_ATTR_CQM_TXE_INTVL = 7,\n\tNL80211_ATTR_CQM_BEACON_LOSS_EVENT = 8,\n\tNL80211_ATTR_CQM_RSSI_LEVEL = 9,\n\t__NL80211_ATTR_CQM_AFTER_LAST = 10,\n\tNL80211_ATTR_CQM_MAX = 9,\n};\n\nenum nl80211_attrs {\n\tNL80211_ATTR_UNSPEC = 0,\n\tNL80211_ATTR_WIPHY = 1,\n\tNL80211_ATTR_WIPHY_NAME = 2,\n\tNL80211_ATTR_IFINDEX = 3,\n\tNL80211_ATTR_IFNAME = 4,\n\tNL80211_ATTR_IFTYPE = 5,\n\tNL80211_ATTR_MAC = 6,\n\tNL80211_ATTR_KEY_DATA = 7,\n\tNL80211_ATTR_KEY_IDX = 8,\n\tNL80211_ATTR_KEY_CIPHER = 9,\n\tNL80211_ATTR_KEY_SEQ = 10,\n\tNL80211_ATTR_KEY_DEFAULT = 11,\n\tNL80211_ATTR_BEACON_INTERVAL = 12,\n\tNL80211_ATTR_DTIM_PERIOD = 13,\n\tNL80211_ATTR_BEACON_HEAD = 14,\n\tNL80211_ATTR_BEACON_TAIL = 15,\n\tNL80211_ATTR_STA_AID = 16,\n\tNL80211_ATTR_STA_FLAGS = 17,\n\tNL80211_ATTR_STA_LISTEN_INTERVAL = 18,\n\tNL80211_ATTR_STA_SUPPORTED_RATES = 19,\n\tNL80211_ATTR_STA_VLAN = 20,\n\tNL80211_ATTR_STA_INFO = 21,\n\tNL80211_ATTR_WIPHY_BANDS = 22,\n\tNL80211_ATTR_MNTR_FLAGS = 23,\n\tNL80211_ATTR_MESH_ID = 24,\n\tNL80211_ATTR_STA_PLINK_ACTION = 25,\n\tNL80211_ATTR_MPATH_NEXT_HOP = 26,\n\tNL80211_ATTR_MPATH_INFO = 27,\n\tNL80211_ATTR_BSS_CTS_PROT = 28,\n\tNL80211_ATTR_BSS_SHORT_PREAMBLE = 29,\n\tNL80211_ATTR_BSS_SHORT_SLOT_TIME = 30,\n\tNL80211_ATTR_HT_CAPABILITY = 31,\n\tNL80211_ATTR_SUPPORTED_IFTYPES = 32,\n\tNL80211_ATTR_REG_ALPHA2 = 33,\n\tNL80211_ATTR_REG_RULES = 34,\n\tNL80211_ATTR_MESH_CONFIG = 35,\n\tNL80211_ATTR_BSS_BASIC_RATES = 36,\n\tNL80211_ATTR_WIPHY_TXQ_PARAMS = 37,\n\tNL80211_ATTR_WIPHY_FREQ = 38,\n\tNL80211_ATTR_WIPHY_CHANNEL_TYPE = 39,\n\tNL80211_ATTR_KEY_DEFAULT_MGMT = 40,\n\tNL80211_ATTR_MGMT_SUBTYPE = 41,\n\tNL80211_ATTR_IE = 42,\n\tNL80211_ATTR_MAX_NUM_SCAN_SSIDS = 43,\n\tNL80211_ATTR_SCAN_FREQUENCIES = 44,\n\tNL80211_ATTR_SCAN_SSIDS = 45,\n\tNL80211_ATTR_GENERATION = 46,\n\tNL80211_ATTR_BSS = 47,\n\tNL80211_ATTR_REG_INITIATOR = 48,\n\tNL80211_ATTR_REG_TYPE = 49,\n\tNL80211_ATTR_SUPPORTED_COMMANDS = 50,\n\tNL80211_ATTR_FRAME = 51,\n\tNL80211_ATTR_SSID = 52,\n\tNL80211_ATTR_AUTH_TYPE = 53,\n\tNL80211_ATTR_REASON_CODE = 54,\n\tNL80211_ATTR_KEY_TYPE = 55,\n\tNL80211_ATTR_MAX_SCAN_IE_LEN = 56,\n\tNL80211_ATTR_CIPHER_SUITES = 57,\n\tNL80211_ATTR_FREQ_BEFORE = 58,\n\tNL80211_ATTR_FREQ_AFTER = 59,\n\tNL80211_ATTR_FREQ_FIXED = 60,\n\tNL80211_ATTR_WIPHY_RETRY_SHORT = 61,\n\tNL80211_ATTR_WIPHY_RETRY_LONG = 62,\n\tNL80211_ATTR_WIPHY_FRAG_THRESHOLD = 63,\n\tNL80211_ATTR_WIPHY_RTS_THRESHOLD = 64,\n\tNL80211_ATTR_TIMED_OUT = 65,\n\tNL80211_ATTR_USE_MFP = 66,\n\tNL80211_ATTR_STA_FLAGS2 = 67,\n\tNL80211_ATTR_CONTROL_PORT = 68,\n\tNL80211_ATTR_TESTDATA = 69,\n\tNL80211_ATTR_PRIVACY = 70,\n\tNL80211_ATTR_DISCONNECTED_BY_AP = 71,\n\tNL80211_ATTR_STATUS_CODE = 72,\n\tNL80211_ATTR_CIPHER_SUITES_PAIRWISE = 73,\n\tNL80211_ATTR_CIPHER_SUITE_GROUP = 74,\n\tNL80211_ATTR_WPA_VERSIONS = 75,\n\tNL80211_ATTR_AKM_SUITES = 76,\n\tNL80211_ATTR_REQ_IE = 77,\n\tNL80211_ATTR_RESP_IE = 78,\n\tNL80211_ATTR_PREV_BSSID = 79,\n\tNL80211_ATTR_KEY = 80,\n\tNL80211_ATTR_KEYS = 81,\n\tNL80211_ATTR_PID = 82,\n\tNL80211_ATTR_4ADDR = 83,\n\tNL80211_ATTR_SURVEY_INFO = 84,\n\tNL80211_ATTR_PMKID = 85,\n\tNL80211_ATTR_MAX_NUM_PMKIDS = 86,\n\tNL80211_ATTR_DURATION = 87,\n\tNL80211_ATTR_COOKIE = 88,\n\tNL80211_ATTR_WIPHY_COVERAGE_CLASS = 89,\n\tNL80211_ATTR_TX_RATES = 90,\n\tNL80211_ATTR_FRAME_MATCH = 91,\n\tNL80211_ATTR_ACK = 92,\n\tNL80211_ATTR_PS_STATE = 93,\n\tNL80211_ATTR_CQM = 94,\n\tNL80211_ATTR_LOCAL_STATE_CHANGE = 95,\n\tNL80211_ATTR_AP_ISOLATE = 96,\n\tNL80211_ATTR_WIPHY_TX_POWER_SETTING = 97,\n\tNL80211_ATTR_WIPHY_TX_POWER_LEVEL = 98,\n\tNL80211_ATTR_TX_FRAME_TYPES = 99,\n\tNL80211_ATTR_RX_FRAME_TYPES = 100,\n\tNL80211_ATTR_FRAME_TYPE = 101,\n\tNL80211_ATTR_CONTROL_PORT_ETHERTYPE = 102,\n\tNL80211_ATTR_CONTROL_PORT_NO_ENCRYPT = 103,\n\tNL80211_ATTR_SUPPORT_IBSS_RSN = 104,\n\tNL80211_ATTR_WIPHY_ANTENNA_TX = 105,\n\tNL80211_ATTR_WIPHY_ANTENNA_RX = 106,\n\tNL80211_ATTR_MCAST_RATE = 107,\n\tNL80211_ATTR_OFFCHANNEL_TX_OK = 108,\n\tNL80211_ATTR_BSS_HT_OPMODE = 109,\n\tNL80211_ATTR_KEY_DEFAULT_TYPES = 110,\n\tNL80211_ATTR_MAX_REMAIN_ON_CHANNEL_DURATION = 111,\n\tNL80211_ATTR_MESH_SETUP = 112,\n\tNL80211_ATTR_WIPHY_ANTENNA_AVAIL_TX = 113,\n\tNL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX = 114,\n\tNL80211_ATTR_SUPPORT_MESH_AUTH = 115,\n\tNL80211_ATTR_STA_PLINK_STATE = 116,\n\tNL80211_ATTR_WOWLAN_TRIGGERS = 117,\n\tNL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED = 118,\n\tNL80211_ATTR_SCHED_SCAN_INTERVAL = 119,\n\tNL80211_ATTR_INTERFACE_COMBINATIONS = 120,\n\tNL80211_ATTR_SOFTWARE_IFTYPES = 121,\n\tNL80211_ATTR_REKEY_DATA = 122,\n\tNL80211_ATTR_MAX_NUM_SCHED_SCAN_SSIDS = 123,\n\tNL80211_ATTR_MAX_SCHED_SCAN_IE_LEN = 124,\n\tNL80211_ATTR_SCAN_SUPP_RATES = 125,\n\tNL80211_ATTR_HIDDEN_SSID = 126,\n\tNL80211_ATTR_IE_PROBE_RESP = 127,\n\tNL80211_ATTR_IE_ASSOC_RESP = 128,\n\tNL80211_ATTR_STA_WME = 129,\n\tNL80211_ATTR_SUPPORT_AP_UAPSD = 130,\n\tNL80211_ATTR_ROAM_SUPPORT = 131,\n\tNL80211_ATTR_SCHED_SCAN_MATCH = 132,\n\tNL80211_ATTR_MAX_MATCH_SETS = 133,\n\tNL80211_ATTR_PMKSA_CANDIDATE = 134,\n\tNL80211_ATTR_TX_NO_CCK_RATE = 135,\n\tNL80211_ATTR_TDLS_ACTION = 136,\n\tNL80211_ATTR_TDLS_DIALOG_TOKEN = 137,\n\tNL80211_ATTR_TDLS_OPERATION = 138,\n\tNL80211_ATTR_TDLS_SUPPORT = 139,\n\tNL80211_ATTR_TDLS_EXTERNAL_SETUP = 140,\n\tNL80211_ATTR_DEVICE_AP_SME = 141,\n\tNL80211_ATTR_DONT_WAIT_FOR_ACK = 142,\n\tNL80211_ATTR_FEATURE_FLAGS = 143,\n\tNL80211_ATTR_PROBE_RESP_OFFLOAD = 144,\n\tNL80211_ATTR_PROBE_RESP = 145,\n\tNL80211_ATTR_DFS_REGION = 146,\n\tNL80211_ATTR_DISABLE_HT = 147,\n\tNL80211_ATTR_HT_CAPABILITY_MASK = 148,\n\tNL80211_ATTR_NOACK_MAP = 149,\n\tNL80211_ATTR_INACTIVITY_TIMEOUT = 150,\n\tNL80211_ATTR_RX_SIGNAL_DBM = 151,\n\tNL80211_ATTR_BG_SCAN_PERIOD = 152,\n\tNL80211_ATTR_WDEV = 153,\n\tNL80211_ATTR_USER_REG_HINT_TYPE = 154,\n\tNL80211_ATTR_CONN_FAILED_REASON = 155,\n\tNL80211_ATTR_AUTH_DATA = 156,\n\tNL80211_ATTR_VHT_CAPABILITY = 157,\n\tNL80211_ATTR_SCAN_FLAGS = 158,\n\tNL80211_ATTR_CHANNEL_WIDTH = 159,\n\tNL80211_ATTR_CENTER_FREQ1 = 160,\n\tNL80211_ATTR_CENTER_FREQ2 = 161,\n\tNL80211_ATTR_P2P_CTWINDOW = 162,\n\tNL80211_ATTR_P2P_OPPPS = 163,\n\tNL80211_ATTR_LOCAL_MESH_POWER_MODE = 164,\n\tNL80211_ATTR_ACL_POLICY = 165,\n\tNL80211_ATTR_MAC_ADDRS = 166,\n\tNL80211_ATTR_MAC_ACL_MAX = 167,\n\tNL80211_ATTR_RADAR_EVENT = 168,\n\tNL80211_ATTR_EXT_CAPA = 169,\n\tNL80211_ATTR_EXT_CAPA_MASK = 170,\n\tNL80211_ATTR_STA_CAPABILITY = 171,\n\tNL80211_ATTR_STA_EXT_CAPABILITY = 172,\n\tNL80211_ATTR_PROTOCOL_FEATURES = 173,\n\tNL80211_ATTR_SPLIT_WIPHY_DUMP = 174,\n\tNL80211_ATTR_DISABLE_VHT = 175,\n\tNL80211_ATTR_VHT_CAPABILITY_MASK = 176,\n\tNL80211_ATTR_MDID = 177,\n\tNL80211_ATTR_IE_RIC = 178,\n\tNL80211_ATTR_CRIT_PROT_ID = 179,\n\tNL80211_ATTR_MAX_CRIT_PROT_DURATION = 180,\n\tNL80211_ATTR_PEER_AID = 181,\n\tNL80211_ATTR_COALESCE_RULE = 182,\n\tNL80211_ATTR_CH_SWITCH_COUNT = 183,\n\tNL80211_ATTR_CH_SWITCH_BLOCK_TX = 184,\n\tNL80211_ATTR_CSA_IES = 185,\n\tNL80211_ATTR_CNTDWN_OFFS_BEACON = 186,\n\tNL80211_ATTR_CNTDWN_OFFS_PRESP = 187,\n\tNL80211_ATTR_RXMGMT_FLAGS = 188,\n\tNL80211_ATTR_STA_SUPPORTED_CHANNELS = 189,\n\tNL80211_ATTR_STA_SUPPORTED_OPER_CLASSES = 190,\n\tNL80211_ATTR_HANDLE_DFS = 191,\n\tNL80211_ATTR_SUPPORT_5_MHZ = 192,\n\tNL80211_ATTR_SUPPORT_10_MHZ = 193,\n\tNL80211_ATTR_OPMODE_NOTIF = 194,\n\tNL80211_ATTR_VENDOR_ID = 195,\n\tNL80211_ATTR_VENDOR_SUBCMD = 196,\n\tNL80211_ATTR_VENDOR_DATA = 197,\n\tNL80211_ATTR_VENDOR_EVENTS = 198,\n\tNL80211_ATTR_QOS_MAP = 199,\n\tNL80211_ATTR_MAC_HINT = 200,\n\tNL80211_ATTR_WIPHY_FREQ_HINT = 201,\n\tNL80211_ATTR_MAX_AP_ASSOC_STA = 202,\n\tNL80211_ATTR_TDLS_PEER_CAPABILITY = 203,\n\tNL80211_ATTR_SOCKET_OWNER = 204,\n\tNL80211_ATTR_CSA_C_OFFSETS_TX = 205,\n\tNL80211_ATTR_MAX_CSA_COUNTERS = 206,\n\tNL80211_ATTR_TDLS_INITIATOR = 207,\n\tNL80211_ATTR_USE_RRM = 208,\n\tNL80211_ATTR_WIPHY_DYN_ACK = 209,\n\tNL80211_ATTR_TSID = 210,\n\tNL80211_ATTR_USER_PRIO = 211,\n\tNL80211_ATTR_ADMITTED_TIME = 212,\n\tNL80211_ATTR_SMPS_MODE = 213,\n\tNL80211_ATTR_OPER_CLASS = 214,\n\tNL80211_ATTR_MAC_MASK = 215,\n\tNL80211_ATTR_WIPHY_SELF_MANAGED_REG = 216,\n\tNL80211_ATTR_EXT_FEATURES = 217,\n\tNL80211_ATTR_SURVEY_RADIO_STATS = 218,\n\tNL80211_ATTR_NETNS_FD = 219,\n\tNL80211_ATTR_SCHED_SCAN_DELAY = 220,\n\tNL80211_ATTR_REG_INDOOR = 221,\n\tNL80211_ATTR_MAX_NUM_SCHED_SCAN_PLANS = 222,\n\tNL80211_ATTR_MAX_SCAN_PLAN_INTERVAL = 223,\n\tNL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS = 224,\n\tNL80211_ATTR_SCHED_SCAN_PLANS = 225,\n\tNL80211_ATTR_PBSS = 226,\n\tNL80211_ATTR_BSS_SELECT = 227,\n\tNL80211_ATTR_STA_SUPPORT_P2P_PS = 228,\n\tNL80211_ATTR_PAD = 229,\n\tNL80211_ATTR_IFTYPE_EXT_CAPA = 230,\n\tNL80211_ATTR_MU_MIMO_GROUP_DATA = 231,\n\tNL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR = 232,\n\tNL80211_ATTR_SCAN_START_TIME_TSF = 233,\n\tNL80211_ATTR_SCAN_START_TIME_TSF_BSSID = 234,\n\tNL80211_ATTR_MEASUREMENT_DURATION = 235,\n\tNL80211_ATTR_MEASUREMENT_DURATION_MANDATORY = 236,\n\tNL80211_ATTR_MESH_PEER_AID = 237,\n\tNL80211_ATTR_NAN_MASTER_PREF = 238,\n\tNL80211_ATTR_BANDS = 239,\n\tNL80211_ATTR_NAN_FUNC = 240,\n\tNL80211_ATTR_NAN_MATCH = 241,\n\tNL80211_ATTR_FILS_KEK = 242,\n\tNL80211_ATTR_FILS_NONCES = 243,\n\tNL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED = 244,\n\tNL80211_ATTR_BSSID = 245,\n\tNL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI = 246,\n\tNL80211_ATTR_SCHED_SCAN_RSSI_ADJUST = 247,\n\tNL80211_ATTR_TIMEOUT_REASON = 248,\n\tNL80211_ATTR_FILS_ERP_USERNAME = 249,\n\tNL80211_ATTR_FILS_ERP_REALM = 250,\n\tNL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM = 251,\n\tNL80211_ATTR_FILS_ERP_RRK = 252,\n\tNL80211_ATTR_FILS_CACHE_ID = 253,\n\tNL80211_ATTR_PMK = 254,\n\tNL80211_ATTR_SCHED_SCAN_MULTI = 255,\n\tNL80211_ATTR_SCHED_SCAN_MAX_REQS = 256,\n\tNL80211_ATTR_WANT_1X_4WAY_HS = 257,\n\tNL80211_ATTR_PMKR0_NAME = 258,\n\tNL80211_ATTR_PORT_AUTHORIZED = 259,\n\tNL80211_ATTR_EXTERNAL_AUTH_ACTION = 260,\n\tNL80211_ATTR_EXTERNAL_AUTH_SUPPORT = 261,\n\tNL80211_ATTR_NSS = 262,\n\tNL80211_ATTR_ACK_SIGNAL = 263,\n\tNL80211_ATTR_CONTROL_PORT_OVER_NL80211 = 264,\n\tNL80211_ATTR_TXQ_STATS = 265,\n\tNL80211_ATTR_TXQ_LIMIT = 266,\n\tNL80211_ATTR_TXQ_MEMORY_LIMIT = 267,\n\tNL80211_ATTR_TXQ_QUANTUM = 268,\n\tNL80211_ATTR_HE_CAPABILITY = 269,\n\tNL80211_ATTR_FTM_RESPONDER = 270,\n\tNL80211_ATTR_FTM_RESPONDER_STATS = 271,\n\tNL80211_ATTR_TIMEOUT = 272,\n\tNL80211_ATTR_PEER_MEASUREMENTS = 273,\n\tNL80211_ATTR_AIRTIME_WEIGHT = 274,\n\tNL80211_ATTR_STA_TX_POWER_SETTING = 275,\n\tNL80211_ATTR_STA_TX_POWER = 276,\n\tNL80211_ATTR_SAE_PASSWORD = 277,\n\tNL80211_ATTR_TWT_RESPONDER = 278,\n\tNL80211_ATTR_HE_OBSS_PD = 279,\n\tNL80211_ATTR_WIPHY_EDMG_CHANNELS = 280,\n\tNL80211_ATTR_WIPHY_EDMG_BW_CONFIG = 281,\n\tNL80211_ATTR_VLAN_ID = 282,\n\tNL80211_ATTR_HE_BSS_COLOR = 283,\n\tNL80211_ATTR_IFTYPE_AKM_SUITES = 284,\n\tNL80211_ATTR_TID_CONFIG = 285,\n\tNL80211_ATTR_CONTROL_PORT_NO_PREAUTH = 286,\n\tNL80211_ATTR_PMK_LIFETIME = 287,\n\tNL80211_ATTR_PMK_REAUTH_THRESHOLD = 288,\n\tNL80211_ATTR_RECEIVE_MULTICAST = 289,\n\tNL80211_ATTR_WIPHY_FREQ_OFFSET = 290,\n\tNL80211_ATTR_CENTER_FREQ1_OFFSET = 291,\n\tNL80211_ATTR_SCAN_FREQ_KHZ = 292,\n\tNL80211_ATTR_HE_6GHZ_CAPABILITY = 293,\n\tNL80211_ATTR_FILS_DISCOVERY = 294,\n\tNL80211_ATTR_UNSOL_BCAST_PROBE_RESP = 295,\n\tNL80211_ATTR_S1G_CAPABILITY = 296,\n\tNL80211_ATTR_S1G_CAPABILITY_MASK = 297,\n\tNL80211_ATTR_SAE_PWE = 298,\n\tNL80211_ATTR_RECONNECT_REQUESTED = 299,\n\tNL80211_ATTR_SAR_SPEC = 300,\n\tNL80211_ATTR_DISABLE_HE = 301,\n\tNL80211_ATTR_OBSS_COLOR_BITMAP = 302,\n\tNL80211_ATTR_COLOR_CHANGE_COUNT = 303,\n\tNL80211_ATTR_COLOR_CHANGE_COLOR = 304,\n\tNL80211_ATTR_COLOR_CHANGE_ELEMS = 305,\n\tNL80211_ATTR_MBSSID_CONFIG = 306,\n\tNL80211_ATTR_MBSSID_ELEMS = 307,\n\tNL80211_ATTR_RADAR_BACKGROUND = 308,\n\tNL80211_ATTR_AP_SETTINGS_FLAGS = 309,\n\tNL80211_ATTR_EHT_CAPABILITY = 310,\n\tNL80211_ATTR_DISABLE_EHT = 311,\n\tNL80211_ATTR_MLO_LINKS = 312,\n\tNL80211_ATTR_MLO_LINK_ID = 313,\n\tNL80211_ATTR_MLD_ADDR = 314,\n\tNL80211_ATTR_MLO_SUPPORT = 315,\n\tNL80211_ATTR_MAX_NUM_AKM_SUITES = 316,\n\tNL80211_ATTR_EML_CAPABILITY = 317,\n\tNL80211_ATTR_MLD_CAPA_AND_OPS = 318,\n\tNL80211_ATTR_TX_HW_TIMESTAMP = 319,\n\tNL80211_ATTR_RX_HW_TIMESTAMP = 320,\n\tNL80211_ATTR_TD_BITMAP = 321,\n\tNL80211_ATTR_PUNCT_BITMAP = 322,\n\tNL80211_ATTR_MAX_HW_TIMESTAMP_PEERS = 323,\n\tNL80211_ATTR_HW_TIMESTAMP_ENABLED = 324,\n\tNL80211_ATTR_EMA_RNR_ELEMS = 325,\n\tNL80211_ATTR_MLO_LINK_DISABLED = 326,\n\tNL80211_ATTR_BSS_DUMP_INCLUDE_USE_DATA = 327,\n\tNL80211_ATTR_MLO_TTLM_DLINK = 328,\n\tNL80211_ATTR_MLO_TTLM_ULINK = 329,\n\tNL80211_ATTR_ASSOC_SPP_AMSDU = 330,\n\tNL80211_ATTR_WIPHY_RADIOS = 331,\n\tNL80211_ATTR_WIPHY_INTERFACE_COMBINATIONS = 332,\n\tNL80211_ATTR_VIF_RADIO_MASK = 333,\n\tNL80211_ATTR_SUPPORTED_SELECTORS = 334,\n\tNL80211_ATTR_MLO_RECONF_REM_LINKS = 335,\n\tNL80211_ATTR_EPCS = 336,\n\tNL80211_ATTR_ASSOC_MLD_EXT_CAPA_OPS = 337,\n\tNL80211_ATTR_WIPHY_RADIO_INDEX = 338,\n\tNL80211_ATTR_S1G_LONG_BEACON_PERIOD = 339,\n\tNL80211_ATTR_S1G_SHORT_BEACON = 340,\n\tNL80211_ATTR_BSS_PARAM = 341,\n\tNL80211_ATTR_NAN_CONFIG = 342,\n\tNL80211_ATTR_NAN_NEW_CLUSTER = 343,\n\tNL80211_ATTR_NAN_CAPABILITIES = 344,\n\tNL80211_ATTR_S1G_PRIMARY_2MHZ = 345,\n\tNL80211_ATTR_EPP_PEER = 346,\n\tNL80211_ATTR_UHR_CAPABILITY = 347,\n\tNL80211_ATTR_DISABLE_UHR = 348,\n\t__NL80211_ATTR_AFTER_LAST = 349,\n\tNUM_NL80211_ATTR = 349,\n\tNL80211_ATTR_MAX = 348,\n};\n\nenum nl80211_auth_type {\n\tNL80211_AUTHTYPE_OPEN_SYSTEM = 0,\n\tNL80211_AUTHTYPE_SHARED_KEY = 1,\n\tNL80211_AUTHTYPE_FT = 2,\n\tNL80211_AUTHTYPE_NETWORK_EAP = 3,\n\tNL80211_AUTHTYPE_SAE = 4,\n\tNL80211_AUTHTYPE_FILS_SK = 5,\n\tNL80211_AUTHTYPE_FILS_SK_PFS = 6,\n\tNL80211_AUTHTYPE_FILS_PK = 7,\n\tNL80211_AUTHTYPE_EPPKE = 8,\n\t__NL80211_AUTHTYPE_NUM = 9,\n\tNL80211_AUTHTYPE_MAX = 8,\n\tNL80211_AUTHTYPE_AUTOMATIC = 9,\n};\n\nenum nl80211_band {\n\tNL80211_BAND_2GHZ = 0,\n\tNL80211_BAND_5GHZ = 1,\n\tNL80211_BAND_60GHZ = 2,\n\tNL80211_BAND_6GHZ = 3,\n\tNL80211_BAND_S1GHZ = 4,\n\tNL80211_BAND_LC = 5,\n\tNUM_NL80211_BANDS = 6,\n};\n\nenum nl80211_band_attr {\n\t__NL80211_BAND_ATTR_INVALID = 0,\n\tNL80211_BAND_ATTR_FREQS = 1,\n\tNL80211_BAND_ATTR_RATES = 2,\n\tNL80211_BAND_ATTR_HT_MCS_SET = 3,\n\tNL80211_BAND_ATTR_HT_CAPA = 4,\n\tNL80211_BAND_ATTR_HT_AMPDU_FACTOR = 5,\n\tNL80211_BAND_ATTR_HT_AMPDU_DENSITY = 6,\n\tNL80211_BAND_ATTR_VHT_MCS_SET = 7,\n\tNL80211_BAND_ATTR_VHT_CAPA = 8,\n\tNL80211_BAND_ATTR_IFTYPE_DATA = 9,\n\tNL80211_BAND_ATTR_EDMG_CHANNELS = 10,\n\tNL80211_BAND_ATTR_EDMG_BW_CONFIG = 11,\n\tNL80211_BAND_ATTR_S1G_MCS_NSS_SET = 12,\n\tNL80211_BAND_ATTR_S1G_CAPA = 13,\n\t__NL80211_BAND_ATTR_AFTER_LAST = 14,\n\tNL80211_BAND_ATTR_MAX = 13,\n};\n\nenum nl80211_band_iftype_attr {\n\t__NL80211_BAND_IFTYPE_ATTR_INVALID = 0,\n\tNL80211_BAND_IFTYPE_ATTR_IFTYPES = 1,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_MAC = 2,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_PHY = 3,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_MCS_SET = 4,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_PPE = 5,\n\tNL80211_BAND_IFTYPE_ATTR_HE_6GHZ_CAPA = 6,\n\tNL80211_BAND_IFTYPE_ATTR_VENDOR_ELEMS = 7,\n\tNL80211_BAND_IFTYPE_ATTR_EHT_CAP_MAC = 8,\n\tNL80211_BAND_IFTYPE_ATTR_EHT_CAP_PHY = 9,\n\tNL80211_BAND_IFTYPE_ATTR_EHT_CAP_MCS_SET = 10,\n\tNL80211_BAND_IFTYPE_ATTR_EHT_CAP_PPE = 11,\n\tNL80211_BAND_IFTYPE_ATTR_UHR_CAP_MAC = 12,\n\tNL80211_BAND_IFTYPE_ATTR_UHR_CAP_PHY = 13,\n\t__NL80211_BAND_IFTYPE_ATTR_AFTER_LAST = 14,\n\tNL80211_BAND_IFTYPE_ATTR_MAX = 13,\n};\n\nenum nl80211_bitrate_attr {\n\t__NL80211_BITRATE_ATTR_INVALID = 0,\n\tNL80211_BITRATE_ATTR_RATE = 1,\n\tNL80211_BITRATE_ATTR_2GHZ_SHORTPREAMBLE = 2,\n\t__NL80211_BITRATE_ATTR_AFTER_LAST = 3,\n\tNL80211_BITRATE_ATTR_MAX = 2,\n};\n\nenum nl80211_bss {\n\t__NL80211_BSS_INVALID = 0,\n\tNL80211_BSS_BSSID = 1,\n\tNL80211_BSS_FREQUENCY = 2,\n\tNL80211_BSS_TSF = 3,\n\tNL80211_BSS_BEACON_INTERVAL = 4,\n\tNL80211_BSS_CAPABILITY = 5,\n\tNL80211_BSS_INFORMATION_ELEMENTS = 6,\n\tNL80211_BSS_SIGNAL_MBM = 7,\n\tNL80211_BSS_SIGNAL_UNSPEC = 8,\n\tNL80211_BSS_STATUS = 9,\n\tNL80211_BSS_SEEN_MS_AGO = 10,\n\tNL80211_BSS_BEACON_IES = 11,\n\tNL80211_BSS_CHAN_WIDTH = 12,\n\tNL80211_BSS_BEACON_TSF = 13,\n\tNL80211_BSS_PRESP_DATA = 14,\n\tNL80211_BSS_LAST_SEEN_BOOTTIME = 15,\n\tNL80211_BSS_PAD = 16,\n\tNL80211_BSS_PARENT_TSF = 17,\n\tNL80211_BSS_PARENT_BSSID = 18,\n\tNL80211_BSS_CHAIN_SIGNAL = 19,\n\tNL80211_BSS_FREQUENCY_OFFSET = 20,\n\tNL80211_BSS_MLO_LINK_ID = 21,\n\tNL80211_BSS_MLD_ADDR = 22,\n\tNL80211_BSS_USE_FOR = 23,\n\tNL80211_BSS_CANNOT_USE_REASONS = 24,\n\t__NL80211_BSS_AFTER_LAST = 25,\n\tNL80211_BSS_MAX = 24,\n};\n\nenum nl80211_bss_cannot_use_reasons {\n\tNL80211_BSS_CANNOT_USE_NSTR_NONPRIMARY = 1,\n\tNL80211_BSS_CANNOT_USE_6GHZ_PWR_MISMATCH = 2,\n};\n\nenum nl80211_bss_color_attributes {\n\t__NL80211_HE_BSS_COLOR_ATTR_INVALID = 0,\n\tNL80211_HE_BSS_COLOR_ATTR_COLOR = 1,\n\tNL80211_HE_BSS_COLOR_ATTR_DISABLED = 2,\n\tNL80211_HE_BSS_COLOR_ATTR_PARTIAL = 3,\n\t__NL80211_HE_BSS_COLOR_ATTR_LAST = 4,\n\tNL80211_HE_BSS_COLOR_ATTR_MAX = 3,\n};\n\nenum nl80211_bss_select_attr {\n\t__NL80211_BSS_SELECT_ATTR_INVALID = 0,\n\tNL80211_BSS_SELECT_ATTR_RSSI = 1,\n\tNL80211_BSS_SELECT_ATTR_BAND_PREF = 2,\n\tNL80211_BSS_SELECT_ATTR_RSSI_ADJUST = 3,\n\t__NL80211_BSS_SELECT_ATTR_AFTER_LAST = 4,\n\tNL80211_BSS_SELECT_ATTR_MAX = 3,\n};\n\nenum nl80211_bss_status {\n\tNL80211_BSS_STATUS_AUTHENTICATED = 0,\n\tNL80211_BSS_STATUS_ASSOCIATED = 1,\n\tNL80211_BSS_STATUS_IBSS_JOINED = 2,\n};\n\nenum nl80211_bss_use_for {\n\tNL80211_BSS_USE_FOR_NORMAL = 1,\n\tNL80211_BSS_USE_FOR_MLD_LINK = 2,\n};\n\nenum nl80211_chan_width {\n\tNL80211_CHAN_WIDTH_20_NOHT = 0,\n\tNL80211_CHAN_WIDTH_20 = 1,\n\tNL80211_CHAN_WIDTH_40 = 2,\n\tNL80211_CHAN_WIDTH_80 = 3,\n\tNL80211_CHAN_WIDTH_80P80 = 4,\n\tNL80211_CHAN_WIDTH_160 = 5,\n\tNL80211_CHAN_WIDTH_5 = 6,\n\tNL80211_CHAN_WIDTH_10 = 7,\n\tNL80211_CHAN_WIDTH_1 = 8,\n\tNL80211_CHAN_WIDTH_2 = 9,\n\tNL80211_CHAN_WIDTH_4 = 10,\n\tNL80211_CHAN_WIDTH_8 = 11,\n\tNL80211_CHAN_WIDTH_16 = 12,\n\tNL80211_CHAN_WIDTH_320 = 13,\n};\n\nenum nl80211_channel_type {\n\tNL80211_CHAN_NO_HT = 0,\n\tNL80211_CHAN_HT20 = 1,\n\tNL80211_CHAN_HT40MINUS = 2,\n\tNL80211_CHAN_HT40PLUS = 3,\n};\n\nenum nl80211_coalesce_condition {\n\tNL80211_COALESCE_CONDITION_MATCH = 0,\n\tNL80211_COALESCE_CONDITION_NO_MATCH = 1,\n};\n\nenum nl80211_commands {\n\tNL80211_CMD_UNSPEC = 0,\n\tNL80211_CMD_GET_WIPHY = 1,\n\tNL80211_CMD_SET_WIPHY = 2,\n\tNL80211_CMD_NEW_WIPHY = 3,\n\tNL80211_CMD_DEL_WIPHY = 4,\n\tNL80211_CMD_GET_INTERFACE = 5,\n\tNL80211_CMD_SET_INTERFACE = 6,\n\tNL80211_CMD_NEW_INTERFACE = 7,\n\tNL80211_CMD_DEL_INTERFACE = 8,\n\tNL80211_CMD_GET_KEY = 9,\n\tNL80211_CMD_SET_KEY = 10,\n\tNL80211_CMD_NEW_KEY = 11,\n\tNL80211_CMD_DEL_KEY = 12,\n\tNL80211_CMD_GET_BEACON = 13,\n\tNL80211_CMD_SET_BEACON = 14,\n\tNL80211_CMD_START_AP = 15,\n\tNL80211_CMD_NEW_BEACON = 15,\n\tNL80211_CMD_STOP_AP = 16,\n\tNL80211_CMD_DEL_BEACON = 16,\n\tNL80211_CMD_GET_STATION = 17,\n\tNL80211_CMD_SET_STATION = 18,\n\tNL80211_CMD_NEW_STATION = 19,\n\tNL80211_CMD_DEL_STATION = 20,\n\tNL80211_CMD_GET_MPATH = 21,\n\tNL80211_CMD_SET_MPATH = 22,\n\tNL80211_CMD_NEW_MPATH = 23,\n\tNL80211_CMD_DEL_MPATH = 24,\n\tNL80211_CMD_SET_BSS = 25,\n\tNL80211_CMD_SET_REG = 26,\n\tNL80211_CMD_REQ_SET_REG = 27,\n\tNL80211_CMD_GET_MESH_CONFIG = 28,\n\tNL80211_CMD_SET_MESH_CONFIG = 29,\n\tNL80211_CMD_SET_MGMT_EXTRA_IE = 30,\n\tNL80211_CMD_GET_REG = 31,\n\tNL80211_CMD_GET_SCAN = 32,\n\tNL80211_CMD_TRIGGER_SCAN = 33,\n\tNL80211_CMD_NEW_SCAN_RESULTS = 34,\n\tNL80211_CMD_SCAN_ABORTED = 35,\n\tNL80211_CMD_REG_CHANGE = 36,\n\tNL80211_CMD_AUTHENTICATE = 37,\n\tNL80211_CMD_ASSOCIATE = 38,\n\tNL80211_CMD_DEAUTHENTICATE = 39,\n\tNL80211_CMD_DISASSOCIATE = 40,\n\tNL80211_CMD_MICHAEL_MIC_FAILURE = 41,\n\tNL80211_CMD_REG_BEACON_HINT = 42,\n\tNL80211_CMD_JOIN_IBSS = 43,\n\tNL80211_CMD_LEAVE_IBSS = 44,\n\tNL80211_CMD_TESTMODE = 45,\n\tNL80211_CMD_CONNECT = 46,\n\tNL80211_CMD_ROAM = 47,\n\tNL80211_CMD_DISCONNECT = 48,\n\tNL80211_CMD_SET_WIPHY_NETNS = 49,\n\tNL80211_CMD_GET_SURVEY = 50,\n\tNL80211_CMD_NEW_SURVEY_RESULTS = 51,\n\tNL80211_CMD_SET_PMKSA = 52,\n\tNL80211_CMD_DEL_PMKSA = 53,\n\tNL80211_CMD_FLUSH_PMKSA = 54,\n\tNL80211_CMD_REMAIN_ON_CHANNEL = 55,\n\tNL80211_CMD_CANCEL_REMAIN_ON_CHANNEL = 56,\n\tNL80211_CMD_SET_TX_BITRATE_MASK = 57,\n\tNL80211_CMD_REGISTER_FRAME = 58,\n\tNL80211_CMD_REGISTER_ACTION = 58,\n\tNL80211_CMD_FRAME = 59,\n\tNL80211_CMD_ACTION = 59,\n\tNL80211_CMD_FRAME_TX_STATUS = 60,\n\tNL80211_CMD_ACTION_TX_STATUS = 60,\n\tNL80211_CMD_SET_POWER_SAVE = 61,\n\tNL80211_CMD_GET_POWER_SAVE = 62,\n\tNL80211_CMD_SET_CQM = 63,\n\tNL80211_CMD_NOTIFY_CQM = 64,\n\tNL80211_CMD_SET_CHANNEL = 65,\n\tNL80211_CMD_SET_WDS_PEER = 66,\n\tNL80211_CMD_FRAME_WAIT_CANCEL = 67,\n\tNL80211_CMD_JOIN_MESH = 68,\n\tNL80211_CMD_LEAVE_MESH = 69,\n\tNL80211_CMD_UNPROT_DEAUTHENTICATE = 70,\n\tNL80211_CMD_UNPROT_DISASSOCIATE = 71,\n\tNL80211_CMD_NEW_PEER_CANDIDATE = 72,\n\tNL80211_CMD_GET_WOWLAN = 73,\n\tNL80211_CMD_SET_WOWLAN = 74,\n\tNL80211_CMD_START_SCHED_SCAN = 75,\n\tNL80211_CMD_STOP_SCHED_SCAN = 76,\n\tNL80211_CMD_SCHED_SCAN_RESULTS = 77,\n\tNL80211_CMD_SCHED_SCAN_STOPPED = 78,\n\tNL80211_CMD_SET_REKEY_OFFLOAD = 79,\n\tNL80211_CMD_PMKSA_CANDIDATE = 80,\n\tNL80211_CMD_TDLS_OPER = 81,\n\tNL80211_CMD_TDLS_MGMT = 82,\n\tNL80211_CMD_UNEXPECTED_FRAME = 83,\n\tNL80211_CMD_PROBE_CLIENT = 84,\n\tNL80211_CMD_REGISTER_BEACONS = 85,\n\tNL80211_CMD_UNEXPECTED_4ADDR_FRAME = 86,\n\tNL80211_CMD_SET_NOACK_MAP = 87,\n\tNL80211_CMD_CH_SWITCH_NOTIFY = 88,\n\tNL80211_CMD_START_P2P_DEVICE = 89,\n\tNL80211_CMD_STOP_P2P_DEVICE = 90,\n\tNL80211_CMD_CONN_FAILED = 91,\n\tNL80211_CMD_SET_MCAST_RATE = 92,\n\tNL80211_CMD_SET_MAC_ACL = 93,\n\tNL80211_CMD_RADAR_DETECT = 94,\n\tNL80211_CMD_GET_PROTOCOL_FEATURES = 95,\n\tNL80211_CMD_UPDATE_FT_IES = 96,\n\tNL80211_CMD_FT_EVENT = 97,\n\tNL80211_CMD_CRIT_PROTOCOL_START = 98,\n\tNL80211_CMD_CRIT_PROTOCOL_STOP = 99,\n\tNL80211_CMD_GET_COALESCE = 100,\n\tNL80211_CMD_SET_COALESCE = 101,\n\tNL80211_CMD_CHANNEL_SWITCH = 102,\n\tNL80211_CMD_VENDOR = 103,\n\tNL80211_CMD_SET_QOS_MAP = 104,\n\tNL80211_CMD_ADD_TX_TS = 105,\n\tNL80211_CMD_DEL_TX_TS = 106,\n\tNL80211_CMD_GET_MPP = 107,\n\tNL80211_CMD_JOIN_OCB = 108,\n\tNL80211_CMD_LEAVE_OCB = 109,\n\tNL80211_CMD_CH_SWITCH_STARTED_NOTIFY = 110,\n\tNL80211_CMD_TDLS_CHANNEL_SWITCH = 111,\n\tNL80211_CMD_TDLS_CANCEL_CHANNEL_SWITCH = 112,\n\tNL80211_CMD_WIPHY_REG_CHANGE = 113,\n\tNL80211_CMD_ABORT_SCAN = 114,\n\tNL80211_CMD_START_NAN = 115,\n\tNL80211_CMD_STOP_NAN = 116,\n\tNL80211_CMD_ADD_NAN_FUNCTION = 117,\n\tNL80211_CMD_DEL_NAN_FUNCTION = 118,\n\tNL80211_CMD_CHANGE_NAN_CONFIG = 119,\n\tNL80211_CMD_NAN_MATCH = 120,\n\tNL80211_CMD_SET_MULTICAST_TO_UNICAST = 121,\n\tNL80211_CMD_UPDATE_CONNECT_PARAMS = 122,\n\tNL80211_CMD_SET_PMK = 123,\n\tNL80211_CMD_DEL_PMK = 124,\n\tNL80211_CMD_PORT_AUTHORIZED = 125,\n\tNL80211_CMD_RELOAD_REGDB = 126,\n\tNL80211_CMD_EXTERNAL_AUTH = 127,\n\tNL80211_CMD_STA_OPMODE_CHANGED = 128,\n\tNL80211_CMD_CONTROL_PORT_FRAME = 129,\n\tNL80211_CMD_GET_FTM_RESPONDER_STATS = 130,\n\tNL80211_CMD_PEER_MEASUREMENT_START = 131,\n\tNL80211_CMD_PEER_MEASUREMENT_RESULT = 132,\n\tNL80211_CMD_PEER_MEASUREMENT_COMPLETE = 133,\n\tNL80211_CMD_NOTIFY_RADAR = 134,\n\tNL80211_CMD_UPDATE_OWE_INFO = 135,\n\tNL80211_CMD_PROBE_MESH_LINK = 136,\n\tNL80211_CMD_SET_TID_CONFIG = 137,\n\tNL80211_CMD_UNPROT_BEACON = 138,\n\tNL80211_CMD_CONTROL_PORT_FRAME_TX_STATUS = 139,\n\tNL80211_CMD_SET_SAR_SPECS = 140,\n\tNL80211_CMD_OBSS_COLOR_COLLISION = 141,\n\tNL80211_CMD_COLOR_CHANGE_REQUEST = 142,\n\tNL80211_CMD_COLOR_CHANGE_STARTED = 143,\n\tNL80211_CMD_COLOR_CHANGE_ABORTED = 144,\n\tNL80211_CMD_COLOR_CHANGE_COMPLETED = 145,\n\tNL80211_CMD_SET_FILS_AAD = 146,\n\tNL80211_CMD_ASSOC_COMEBACK = 147,\n\tNL80211_CMD_ADD_LINK = 148,\n\tNL80211_CMD_REMOVE_LINK = 149,\n\tNL80211_CMD_ADD_LINK_STA = 150,\n\tNL80211_CMD_MODIFY_LINK_STA = 151,\n\tNL80211_CMD_REMOVE_LINK_STA = 152,\n\tNL80211_CMD_SET_HW_TIMESTAMP = 153,\n\tNL80211_CMD_LINKS_REMOVED = 154,\n\tNL80211_CMD_SET_TID_TO_LINK_MAPPING = 155,\n\tNL80211_CMD_ASSOC_MLO_RECONF = 156,\n\tNL80211_CMD_EPCS_CFG = 157,\n\tNL80211_CMD_NAN_NEXT_DW_NOTIFICATION = 158,\n\tNL80211_CMD_NAN_CLUSTER_JOINED = 159,\n\t__NL80211_CMD_AFTER_LAST = 160,\n\tNL80211_CMD_MAX = 159,\n};\n\nenum nl80211_connect_failed_reason {\n\tNL80211_CONN_FAIL_MAX_CLIENTS = 0,\n\tNL80211_CONN_FAIL_BLOCKED_CLIENT = 1,\n};\n\nenum nl80211_cqm_rssi_threshold_event {\n\tNL80211_CQM_RSSI_THRESHOLD_EVENT_LOW = 0,\n\tNL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH = 1,\n\tNL80211_CQM_RSSI_BEACON_LOSS_EVENT = 2,\n};\n\nenum nl80211_crit_proto_id {\n\tNL80211_CRIT_PROTO_UNSPEC = 0,\n\tNL80211_CRIT_PROTO_DHCP = 1,\n\tNL80211_CRIT_PROTO_EAPOL = 2,\n\tNL80211_CRIT_PROTO_APIPA = 3,\n\tNUM_NL80211_CRIT_PROTO = 4,\n};\n\nenum nl80211_dfs_regions {\n\tNL80211_DFS_UNSET = 0,\n\tNL80211_DFS_FCC = 1,\n\tNL80211_DFS_ETSI = 2,\n\tNL80211_DFS_JP = 3,\n};\n\nenum nl80211_dfs_state {\n\tNL80211_DFS_USABLE = 0,\n\tNL80211_DFS_UNAVAILABLE = 1,\n\tNL80211_DFS_AVAILABLE = 2,\n};\n\nenum nl80211_eht_gi {\n\tNL80211_RATE_INFO_EHT_GI_0_8 = 0,\n\tNL80211_RATE_INFO_EHT_GI_1_6 = 1,\n\tNL80211_RATE_INFO_EHT_GI_3_2 = 2,\n};\n\nenum nl80211_eht_ltf {\n\tNL80211_RATE_INFO_EHT_1XLTF = 0,\n\tNL80211_RATE_INFO_EHT_2XLTF = 1,\n\tNL80211_RATE_INFO_EHT_4XLTF = 2,\n\tNL80211_RATE_INFO_EHT_6XLTF = 3,\n\tNL80211_RATE_INFO_EHT_8XLTF = 4,\n};\n\nenum nl80211_eht_ru_alloc {\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_26 = 0,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_52 = 1,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_52P26 = 2,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_106 = 3,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_106P26 = 4,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_242 = 5,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_484 = 6,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_484P242 = 7,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_996 = 8,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_996P484 = 9,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_996P484P242 = 10,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_2x996 = 11,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_2x996P484 = 12,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_3x996 = 13,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_3x996P484 = 14,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC_4x996 = 15,\n};\n\nenum nl80211_ext_feature_index {\n\tNL80211_EXT_FEATURE_VHT_IBSS = 0,\n\tNL80211_EXT_FEATURE_RRM = 1,\n\tNL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER = 2,\n\tNL80211_EXT_FEATURE_SCAN_START_TIME = 3,\n\tNL80211_EXT_FEATURE_BSS_PARENT_TSF = 4,\n\tNL80211_EXT_FEATURE_SET_SCAN_DWELL = 5,\n\tNL80211_EXT_FEATURE_BEACON_RATE_LEGACY = 6,\n\tNL80211_EXT_FEATURE_BEACON_RATE_HT = 7,\n\tNL80211_EXT_FEATURE_BEACON_RATE_VHT = 8,\n\tNL80211_EXT_FEATURE_FILS_STA = 9,\n\tNL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA = 10,\n\tNL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED = 11,\n\tNL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI = 12,\n\tNL80211_EXT_FEATURE_CQM_RSSI_LIST = 13,\n\tNL80211_EXT_FEATURE_FILS_SK_OFFLOAD = 14,\n\tNL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_PSK = 15,\n\tNL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_1X = 16,\n\tNL80211_EXT_FEATURE_FILS_MAX_CHANNEL_TIME = 17,\n\tNL80211_EXT_FEATURE_ACCEPT_BCAST_PROBE_RESP = 18,\n\tNL80211_EXT_FEATURE_OCE_PROBE_REQ_HIGH_TX_RATE = 19,\n\tNL80211_EXT_FEATURE_OCE_PROBE_REQ_DEFERRAL_SUPPRESSION = 20,\n\tNL80211_EXT_FEATURE_MFP_OPTIONAL = 21,\n\tNL80211_EXT_FEATURE_LOW_SPAN_SCAN = 22,\n\tNL80211_EXT_FEATURE_LOW_POWER_SCAN = 23,\n\tNL80211_EXT_FEATURE_HIGH_ACCURACY_SCAN = 24,\n\tNL80211_EXT_FEATURE_DFS_OFFLOAD = 25,\n\tNL80211_EXT_FEATURE_CONTROL_PORT_OVER_NL80211 = 26,\n\tNL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT = 27,\n\tNL80211_EXT_FEATURE_DATA_ACK_SIGNAL_SUPPORT = 27,\n\tNL80211_EXT_FEATURE_TXQS = 28,\n\tNL80211_EXT_FEATURE_SCAN_RANDOM_SN = 29,\n\tNL80211_EXT_FEATURE_SCAN_MIN_PREQ_CONTENT = 30,\n\tNL80211_EXT_FEATURE_CAN_REPLACE_PTK0 = 31,\n\tNL80211_EXT_FEATURE_ENABLE_FTM_RESPONDER = 32,\n\tNL80211_EXT_FEATURE_AIRTIME_FAIRNESS = 33,\n\tNL80211_EXT_FEATURE_AP_PMKSA_CACHING = 34,\n\tNL80211_EXT_FEATURE_SCHED_SCAN_BAND_SPECIFIC_RSSI_THOLD = 35,\n\tNL80211_EXT_FEATURE_EXT_KEY_ID = 36,\n\tNL80211_EXT_FEATURE_STA_TX_PWR = 37,\n\tNL80211_EXT_FEATURE_SAE_OFFLOAD = 38,\n\tNL80211_EXT_FEATURE_VLAN_OFFLOAD = 39,\n\tNL80211_EXT_FEATURE_AQL = 40,\n\tNL80211_EXT_FEATURE_BEACON_PROTECTION = 41,\n\tNL80211_EXT_FEATURE_CONTROL_PORT_NO_PREAUTH = 42,\n\tNL80211_EXT_FEATURE_PROTECTED_TWT = 43,\n\tNL80211_EXT_FEATURE_DEL_IBSS_STA = 44,\n\tNL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS = 45,\n\tNL80211_EXT_FEATURE_BEACON_PROTECTION_CLIENT = 46,\n\tNL80211_EXT_FEATURE_SCAN_FREQ_KHZ = 47,\n\tNL80211_EXT_FEATURE_CONTROL_PORT_OVER_NL80211_TX_STATUS = 48,\n\tNL80211_EXT_FEATURE_OPERATING_CHANNEL_VALIDATION = 49,\n\tNL80211_EXT_FEATURE_4WAY_HANDSHAKE_AP_PSK = 50,\n\tNL80211_EXT_FEATURE_SAE_OFFLOAD_AP = 51,\n\tNL80211_EXT_FEATURE_FILS_DISCOVERY = 52,\n\tNL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP = 53,\n\tNL80211_EXT_FEATURE_BEACON_RATE_HE = 54,\n\tNL80211_EXT_FEATURE_SECURE_LTF = 55,\n\tNL80211_EXT_FEATURE_SECURE_RTT = 56,\n\tNL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE = 57,\n\tNL80211_EXT_FEATURE_BSS_COLOR = 58,\n\tNL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD = 59,\n\tNL80211_EXT_FEATURE_RADAR_BACKGROUND = 60,\n\tNL80211_EXT_FEATURE_POWERED_ADDR_CHANGE = 61,\n\tNL80211_EXT_FEATURE_PUNCT = 62,\n\tNL80211_EXT_FEATURE_SECURE_NAN = 63,\n\tNL80211_EXT_FEATURE_AUTH_AND_DEAUTH_RANDOM_TA = 64,\n\tNL80211_EXT_FEATURE_OWE_OFFLOAD = 65,\n\tNL80211_EXT_FEATURE_OWE_OFFLOAD_AP = 66,\n\tNL80211_EXT_FEATURE_DFS_CONCURRENT = 67,\n\tNL80211_EXT_FEATURE_SPP_AMSDU_SUPPORT = 68,\n\tNL80211_EXT_FEATURE_BEACON_RATE_EHT = 69,\n\tNL80211_EXT_FEATURE_EPPKE = 70,\n\tNL80211_EXT_FEATURE_ASSOC_FRAME_ENCRYPTION = 71,\n\tNUM_NL80211_EXT_FEATURES = 72,\n\tMAX_NL80211_EXT_FEATURES = 71,\n};\n\nenum nl80211_external_auth_action {\n\tNL80211_EXTERNAL_AUTH_START = 0,\n\tNL80211_EXTERNAL_AUTH_ABORT = 1,\n};\n\nenum nl80211_feature_flags {\n\tNL80211_FEATURE_SK_TX_STATUS = 1,\n\tNL80211_FEATURE_HT_IBSS = 2,\n\tNL80211_FEATURE_INACTIVITY_TIMER = 4,\n\tNL80211_FEATURE_CELL_BASE_REG_HINTS = 8,\n\tNL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL = 16,\n\tNL80211_FEATURE_SAE = 32,\n\tNL80211_FEATURE_LOW_PRIORITY_SCAN = 64,\n\tNL80211_FEATURE_SCAN_FLUSH = 128,\n\tNL80211_FEATURE_AP_SCAN = 256,\n\tNL80211_FEATURE_VIF_TXPOWER = 512,\n\tNL80211_FEATURE_NEED_OBSS_SCAN = 1024,\n\tNL80211_FEATURE_P2P_GO_CTWIN = 2048,\n\tNL80211_FEATURE_P2P_GO_OPPPS = 4096,\n\tNL80211_FEATURE_ADVERTISE_CHAN_LIMITS = 16384,\n\tNL80211_FEATURE_FULL_AP_CLIENT_STATE = 32768,\n\tNL80211_FEATURE_USERSPACE_MPM = 65536,\n\tNL80211_FEATURE_ACTIVE_MONITOR = 131072,\n\tNL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE = 262144,\n\tNL80211_FEATURE_DS_PARAM_SET_IE_IN_PROBES = 524288,\n\tNL80211_FEATURE_WFA_TPC_IE_IN_PROBES = 1048576,\n\tNL80211_FEATURE_QUIET = 2097152,\n\tNL80211_FEATURE_TX_POWER_INSERTION = 4194304,\n\tNL80211_FEATURE_ACKTO_ESTIMATION = 8388608,\n\tNL80211_FEATURE_STATIC_SMPS = 16777216,\n\tNL80211_FEATURE_DYNAMIC_SMPS = 33554432,\n\tNL80211_FEATURE_SUPPORTS_WMM_ADMISSION = 67108864,\n\tNL80211_FEATURE_MAC_ON_CREATE = 134217728,\n\tNL80211_FEATURE_TDLS_CHANNEL_SWITCH = 268435456,\n\tNL80211_FEATURE_SCAN_RANDOM_MAC_ADDR = 536870912,\n\tNL80211_FEATURE_SCHED_SCAN_RANDOM_MAC_ADDR = 1073741824,\n\tNL80211_FEATURE_ND_RANDOM_MAC_ADDR = 2147483648,\n};\n\nenum nl80211_fils_discovery_attributes {\n\t__NL80211_FILS_DISCOVERY_ATTR_INVALID = 0,\n\tNL80211_FILS_DISCOVERY_ATTR_INT_MIN = 1,\n\tNL80211_FILS_DISCOVERY_ATTR_INT_MAX = 2,\n\tNL80211_FILS_DISCOVERY_ATTR_TMPL = 3,\n\t__NL80211_FILS_DISCOVERY_ATTR_LAST = 4,\n\tNL80211_FILS_DISCOVERY_ATTR_MAX = 3,\n};\n\nenum nl80211_frequency_attr {\n\t__NL80211_FREQUENCY_ATTR_INVALID = 0,\n\tNL80211_FREQUENCY_ATTR_FREQ = 1,\n\tNL80211_FREQUENCY_ATTR_DISABLED = 2,\n\tNL80211_FREQUENCY_ATTR_NO_IR = 3,\n\t__NL80211_FREQUENCY_ATTR_NO_IBSS = 4,\n\tNL80211_FREQUENCY_ATTR_RADAR = 5,\n\tNL80211_FREQUENCY_ATTR_MAX_TX_POWER = 6,\n\tNL80211_FREQUENCY_ATTR_DFS_STATE = 7,\n\tNL80211_FREQUENCY_ATTR_DFS_TIME = 8,\n\tNL80211_FREQUENCY_ATTR_NO_HT40_MINUS = 9,\n\tNL80211_FREQUENCY_ATTR_NO_HT40_PLUS = 10,\n\tNL80211_FREQUENCY_ATTR_NO_80MHZ = 11,\n\tNL80211_FREQUENCY_ATTR_NO_160MHZ = 12,\n\tNL80211_FREQUENCY_ATTR_DFS_CAC_TIME = 13,\n\tNL80211_FREQUENCY_ATTR_INDOOR_ONLY = 14,\n\tNL80211_FREQUENCY_ATTR_IR_CONCURRENT = 15,\n\tNL80211_FREQUENCY_ATTR_NO_20MHZ = 16,\n\tNL80211_FREQUENCY_ATTR_NO_10MHZ = 17,\n\tNL80211_FREQUENCY_ATTR_WMM = 18,\n\tNL80211_FREQUENCY_ATTR_NO_HE = 19,\n\tNL80211_FREQUENCY_ATTR_OFFSET = 20,\n\tNL80211_FREQUENCY_ATTR_1MHZ = 21,\n\tNL80211_FREQUENCY_ATTR_2MHZ = 22,\n\tNL80211_FREQUENCY_ATTR_4MHZ = 23,\n\tNL80211_FREQUENCY_ATTR_8MHZ = 24,\n\tNL80211_FREQUENCY_ATTR_16MHZ = 25,\n\tNL80211_FREQUENCY_ATTR_NO_320MHZ = 26,\n\tNL80211_FREQUENCY_ATTR_NO_EHT = 27,\n\tNL80211_FREQUENCY_ATTR_PSD = 28,\n\tNL80211_FREQUENCY_ATTR_DFS_CONCURRENT = 29,\n\tNL80211_FREQUENCY_ATTR_NO_6GHZ_VLP_CLIENT = 30,\n\tNL80211_FREQUENCY_ATTR_NO_6GHZ_AFC_CLIENT = 31,\n\tNL80211_FREQUENCY_ATTR_CAN_MONITOR = 32,\n\tNL80211_FREQUENCY_ATTR_ALLOW_6GHZ_VLP_AP = 33,\n\tNL80211_FREQUENCY_ATTR_ALLOW_20MHZ_ACTIVITY = 34,\n\tNL80211_FREQUENCY_ATTR_NO_4MHZ = 35,\n\tNL80211_FREQUENCY_ATTR_NO_8MHZ = 36,\n\tNL80211_FREQUENCY_ATTR_NO_16MHZ = 37,\n\tNL80211_FREQUENCY_ATTR_S1G_NO_PRIMARY = 38,\n\tNL80211_FREQUENCY_ATTR_NO_UHR = 39,\n\t__NL80211_FREQUENCY_ATTR_AFTER_LAST = 40,\n\tNL80211_FREQUENCY_ATTR_MAX = 39,\n};\n\nenum nl80211_ftm_responder_attributes {\n\t__NL80211_FTM_RESP_ATTR_INVALID = 0,\n\tNL80211_FTM_RESP_ATTR_ENABLED = 1,\n\tNL80211_FTM_RESP_ATTR_LCI = 2,\n\tNL80211_FTM_RESP_ATTR_CIVICLOC = 3,\n\t__NL80211_FTM_RESP_ATTR_LAST = 4,\n\tNL80211_FTM_RESP_ATTR_MAX = 3,\n};\n\nenum nl80211_ftm_responder_stats {\n\t__NL80211_FTM_STATS_INVALID = 0,\n\tNL80211_FTM_STATS_SUCCESS_NUM = 1,\n\tNL80211_FTM_STATS_PARTIAL_NUM = 2,\n\tNL80211_FTM_STATS_FAILED_NUM = 3,\n\tNL80211_FTM_STATS_ASAP_NUM = 4,\n\tNL80211_FTM_STATS_NON_ASAP_NUM = 5,\n\tNL80211_FTM_STATS_TOTAL_DURATION_MSEC = 6,\n\tNL80211_FTM_STATS_UNKNOWN_TRIGGERS_NUM = 7,\n\tNL80211_FTM_STATS_RESCHEDULE_REQUESTS_NUM = 8,\n\tNL80211_FTM_STATS_OUT_OF_WINDOW_TRIGGERS_NUM = 9,\n\tNL80211_FTM_STATS_PAD = 10,\n\t__NL80211_FTM_STATS_AFTER_LAST = 11,\n\tNL80211_FTM_STATS_MAX = 10,\n};\n\nenum nl80211_he_gi {\n\tNL80211_RATE_INFO_HE_GI_0_8 = 0,\n\tNL80211_RATE_INFO_HE_GI_1_6 = 1,\n\tNL80211_RATE_INFO_HE_GI_3_2 = 2,\n};\n\nenum nl80211_he_ltf {\n\tNL80211_RATE_INFO_HE_1XLTF = 0,\n\tNL80211_RATE_INFO_HE_2XLTF = 1,\n\tNL80211_RATE_INFO_HE_4XLTF = 2,\n};\n\nenum nl80211_he_ru_alloc {\n\tNL80211_RATE_INFO_HE_RU_ALLOC_26 = 0,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_52 = 1,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_106 = 2,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_242 = 3,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_484 = 4,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_996 = 5,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_2x996 = 6,\n};\n\nenum nl80211_hidden_ssid {\n\tNL80211_HIDDEN_SSID_NOT_IN_USE = 0,\n\tNL80211_HIDDEN_SSID_ZERO_LEN = 1,\n\tNL80211_HIDDEN_SSID_ZERO_CONTENTS = 2,\n};\n\nenum nl80211_if_combination_attrs {\n\tNL80211_IFACE_COMB_UNSPEC = 0,\n\tNL80211_IFACE_COMB_LIMITS = 1,\n\tNL80211_IFACE_COMB_MAXNUM = 2,\n\tNL80211_IFACE_COMB_STA_AP_BI_MATCH = 3,\n\tNL80211_IFACE_COMB_NUM_CHANNELS = 4,\n\tNL80211_IFACE_COMB_RADAR_DETECT_WIDTHS = 5,\n\tNL80211_IFACE_COMB_RADAR_DETECT_REGIONS = 6,\n\tNL80211_IFACE_COMB_BI_MIN_GCD = 7,\n\tNUM_NL80211_IFACE_COMB = 8,\n\tMAX_NL80211_IFACE_COMB = 7,\n};\n\nenum nl80211_iface_limit_attrs {\n\tNL80211_IFACE_LIMIT_UNSPEC = 0,\n\tNL80211_IFACE_LIMIT_MAX = 1,\n\tNL80211_IFACE_LIMIT_TYPES = 2,\n\tNUM_NL80211_IFACE_LIMIT = 3,\n\tMAX_NL80211_IFACE_LIMIT = 2,\n};\n\nenum nl80211_iftype {\n\tNL80211_IFTYPE_UNSPECIFIED = 0,\n\tNL80211_IFTYPE_ADHOC = 1,\n\tNL80211_IFTYPE_STATION = 2,\n\tNL80211_IFTYPE_AP = 3,\n\tNL80211_IFTYPE_AP_VLAN = 4,\n\tNL80211_IFTYPE_WDS = 5,\n\tNL80211_IFTYPE_MONITOR = 6,\n\tNL80211_IFTYPE_MESH_POINT = 7,\n\tNL80211_IFTYPE_P2P_CLIENT = 8,\n\tNL80211_IFTYPE_P2P_GO = 9,\n\tNL80211_IFTYPE_P2P_DEVICE = 10,\n\tNL80211_IFTYPE_OCB = 11,\n\tNL80211_IFTYPE_NAN = 12,\n\tNUM_NL80211_IFTYPES = 13,\n\tNL80211_IFTYPE_MAX = 12,\n};\n\nenum nl80211_iftype_akm_attributes {\n\t__NL80211_IFTYPE_AKM_ATTR_INVALID = 0,\n\tNL80211_IFTYPE_AKM_ATTR_IFTYPES = 1,\n\tNL80211_IFTYPE_AKM_ATTR_SUITES = 2,\n\t__NL80211_IFTYPE_AKM_ATTR_LAST = 3,\n\tNL80211_IFTYPE_AKM_ATTR_MAX = 2,\n};\n\nenum nl80211_internal_flags_selector {\n\tNL80211_IFL_SEL_NONE = 0,\n\tNL80211_IFL_SEL_WIPHY = 1,\n\tNL80211_IFL_SEL_WDEV = 2,\n\tNL80211_IFL_SEL_NETDEV = 3,\n\tNL80211_IFL_SEL_NETDEV_LINK = 4,\n\tNL80211_IFL_SEL_NETDEV_NO_MLO = 5,\n\tNL80211_IFL_SEL_WIPHY_RTNL = 6,\n\tNL80211_IFL_SEL_WIPHY_RTNL_NOMTX = 7,\n\tNL80211_IFL_SEL_WDEV_RTNL = 8,\n\tNL80211_IFL_SEL_NETDEV_RTNL = 9,\n\tNL80211_IFL_SEL_NETDEV_UP = 10,\n\tNL80211_IFL_SEL_NETDEV_UP_LINK = 11,\n\tNL80211_IFL_SEL_NETDEV_UP_NO_MLO = 12,\n\tNL80211_IFL_SEL_NETDEV_UP_NO_MLO_CLEAR = 13,\n\tNL80211_IFL_SEL_NETDEV_UP_NOTMX = 14,\n\tNL80211_IFL_SEL_NETDEV_UP_NOTMX_MLO = 15,\n\tNL80211_IFL_SEL_NETDEV_UP_CLEAR = 16,\n\tNL80211_IFL_SEL_WDEV_UP = 17,\n\tNL80211_IFL_SEL_WDEV_UP_LINK = 18,\n\tNL80211_IFL_SEL_WDEV_UP_RTNL = 19,\n\tNL80211_IFL_SEL_WIPHY_CLEAR = 20,\n};\n\nenum nl80211_key_attributes {\n\t__NL80211_KEY_INVALID = 0,\n\tNL80211_KEY_DATA = 1,\n\tNL80211_KEY_IDX = 2,\n\tNL80211_KEY_CIPHER = 3,\n\tNL80211_KEY_SEQ = 4,\n\tNL80211_KEY_DEFAULT = 5,\n\tNL80211_KEY_DEFAULT_MGMT = 6,\n\tNL80211_KEY_TYPE = 7,\n\tNL80211_KEY_DEFAULT_TYPES = 8,\n\tNL80211_KEY_MODE = 9,\n\tNL80211_KEY_DEFAULT_BEACON = 10,\n\t__NL80211_KEY_AFTER_LAST = 11,\n\tNL80211_KEY_MAX = 10,\n};\n\nenum nl80211_key_default_types {\n\t__NL80211_KEY_DEFAULT_TYPE_INVALID = 0,\n\tNL80211_KEY_DEFAULT_TYPE_UNICAST = 1,\n\tNL80211_KEY_DEFAULT_TYPE_MULTICAST = 2,\n\tNUM_NL80211_KEY_DEFAULT_TYPES = 3,\n};\n\nenum nl80211_key_mode {\n\tNL80211_KEY_RX_TX = 0,\n\tNL80211_KEY_NO_TX = 1,\n\tNL80211_KEY_SET_TX = 2,\n};\n\nenum nl80211_key_type {\n\tNL80211_KEYTYPE_GROUP = 0,\n\tNL80211_KEYTYPE_PAIRWISE = 1,\n\tNL80211_KEYTYPE_PEERKEY = 2,\n\tNUM_NL80211_KEYTYPES = 3,\n};\n\nenum nl80211_mbssid_config_attributes {\n\t__NL80211_MBSSID_CONFIG_ATTR_INVALID = 0,\n\tNL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES = 1,\n\tNL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY = 2,\n\tNL80211_MBSSID_CONFIG_ATTR_INDEX = 3,\n\tNL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX = 4,\n\tNL80211_MBSSID_CONFIG_ATTR_EMA = 5,\n\tNL80211_MBSSID_CONFIG_ATTR_TX_LINK_ID = 6,\n\t__NL80211_MBSSID_CONFIG_ATTR_LAST = 7,\n\tNL80211_MBSSID_CONFIG_ATTR_MAX = 6,\n};\n\nenum nl80211_mesh_power_mode {\n\tNL80211_MESH_POWER_UNKNOWN = 0,\n\tNL80211_MESH_POWER_ACTIVE = 1,\n\tNL80211_MESH_POWER_LIGHT_SLEEP = 2,\n\tNL80211_MESH_POWER_DEEP_SLEEP = 3,\n\t__NL80211_MESH_POWER_AFTER_LAST = 4,\n\tNL80211_MESH_POWER_MAX = 3,\n};\n\nenum nl80211_mesh_setup_params {\n\t__NL80211_MESH_SETUP_INVALID = 0,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_PATH_SEL = 1,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_METRIC = 2,\n\tNL80211_MESH_SETUP_IE = 3,\n\tNL80211_MESH_SETUP_USERSPACE_AUTH = 4,\n\tNL80211_MESH_SETUP_USERSPACE_AMPE = 5,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_SYNC = 6,\n\tNL80211_MESH_SETUP_USERSPACE_MPM = 7,\n\tNL80211_MESH_SETUP_AUTH_PROTOCOL = 8,\n\t__NL80211_MESH_SETUP_ATTR_AFTER_LAST = 9,\n\tNL80211_MESH_SETUP_ATTR_MAX = 8,\n};\n\nenum nl80211_meshconf_params {\n\t__NL80211_MESHCONF_INVALID = 0,\n\tNL80211_MESHCONF_RETRY_TIMEOUT = 1,\n\tNL80211_MESHCONF_CONFIRM_TIMEOUT = 2,\n\tNL80211_MESHCONF_HOLDING_TIMEOUT = 3,\n\tNL80211_MESHCONF_MAX_PEER_LINKS = 4,\n\tNL80211_MESHCONF_MAX_RETRIES = 5,\n\tNL80211_MESHCONF_TTL = 6,\n\tNL80211_MESHCONF_AUTO_OPEN_PLINKS = 7,\n\tNL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES = 8,\n\tNL80211_MESHCONF_PATH_REFRESH_TIME = 9,\n\tNL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT = 10,\n\tNL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT = 11,\n\tNL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL = 12,\n\tNL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME = 13,\n\tNL80211_MESHCONF_HWMP_ROOTMODE = 14,\n\tNL80211_MESHCONF_ELEMENT_TTL = 15,\n\tNL80211_MESHCONF_HWMP_RANN_INTERVAL = 16,\n\tNL80211_MESHCONF_GATE_ANNOUNCEMENTS = 17,\n\tNL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL = 18,\n\tNL80211_MESHCONF_FORWARDING = 19,\n\tNL80211_MESHCONF_RSSI_THRESHOLD = 20,\n\tNL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR = 21,\n\tNL80211_MESHCONF_HT_OPMODE = 22,\n\tNL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT = 23,\n\tNL80211_MESHCONF_HWMP_ROOT_INTERVAL = 24,\n\tNL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL = 25,\n\tNL80211_MESHCONF_POWER_MODE = 26,\n\tNL80211_MESHCONF_AWAKE_WINDOW = 27,\n\tNL80211_MESHCONF_PLINK_TIMEOUT = 28,\n\tNL80211_MESHCONF_CONNECTED_TO_GATE = 29,\n\tNL80211_MESHCONF_NOLEARN = 30,\n\tNL80211_MESHCONF_CONNECTED_TO_AS = 31,\n\t__NL80211_MESHCONF_ATTR_AFTER_LAST = 32,\n\tNL80211_MESHCONF_ATTR_MAX = 31,\n};\n\nenum nl80211_mfp {\n\tNL80211_MFP_NO = 0,\n\tNL80211_MFP_REQUIRED = 1,\n\tNL80211_MFP_OPTIONAL = 2,\n};\n\nenum nl80211_mntr_flags {\n\t__NL80211_MNTR_FLAG_INVALID = 0,\n\tNL80211_MNTR_FLAG_FCSFAIL = 1,\n\tNL80211_MNTR_FLAG_PLCPFAIL = 2,\n\tNL80211_MNTR_FLAG_CONTROL = 3,\n\tNL80211_MNTR_FLAG_OTHER_BSS = 4,\n\tNL80211_MNTR_FLAG_COOK_FRAMES = 5,\n\tNL80211_MNTR_FLAG_ACTIVE = 6,\n\tNL80211_MNTR_FLAG_SKIP_TX = 7,\n\t__NL80211_MNTR_FLAG_AFTER_LAST = 8,\n\tNL80211_MNTR_FLAG_MAX = 7,\n};\n\nenum nl80211_mpath_info {\n\t__NL80211_MPATH_INFO_INVALID = 0,\n\tNL80211_MPATH_INFO_FRAME_QLEN = 1,\n\tNL80211_MPATH_INFO_SN = 2,\n\tNL80211_MPATH_INFO_METRIC = 3,\n\tNL80211_MPATH_INFO_EXPTIME = 4,\n\tNL80211_MPATH_INFO_FLAGS = 5,\n\tNL80211_MPATH_INFO_DISCOVERY_TIMEOUT = 6,\n\tNL80211_MPATH_INFO_DISCOVERY_RETRIES = 7,\n\tNL80211_MPATH_INFO_HOP_COUNT = 8,\n\tNL80211_MPATH_INFO_PATH_CHANGE = 9,\n\t__NL80211_MPATH_INFO_AFTER_LAST = 10,\n\tNL80211_MPATH_INFO_MAX = 9,\n};\n\nenum nl80211_multicast_groups {\n\tNL80211_MCGRP_CONFIG = 0,\n\tNL80211_MCGRP_SCAN = 1,\n\tNL80211_MCGRP_REGULATORY = 2,\n\tNL80211_MCGRP_MLME = 3,\n\tNL80211_MCGRP_VENDOR = 4,\n\tNL80211_MCGRP_NAN = 5,\n\tNL80211_MCGRP_TESTMODE = 6,\n};\n\nenum nl80211_nan_band_conf_attributes {\n\t__NL80211_NAN_BAND_CONF_INVALID = 0,\n\tNL80211_NAN_BAND_CONF_BAND = 1,\n\tNL80211_NAN_BAND_CONF_FREQ = 2,\n\tNL80211_NAN_BAND_CONF_RSSI_CLOSE = 3,\n\tNL80211_NAN_BAND_CONF_RSSI_MIDDLE = 4,\n\tNL80211_NAN_BAND_CONF_WAKE_DW = 5,\n\tNL80211_NAN_BAND_CONF_DISABLE_SCAN = 6,\n\tNUM_NL80211_NAN_BAND_CONF_ATTR = 7,\n\tNL80211_NAN_BAND_CONF_ATTR_MAX = 6,\n};\n\nenum nl80211_nan_capabilities {\n\t__NL80211_NAN_CAPABILITIES_INVALID = 0,\n\tNL80211_NAN_CAPA_CONFIGURABLE_SYNC = 1,\n\tNL80211_NAN_CAPA_USERSPACE_DE = 2,\n\tNL80211_NAN_CAPA_OP_MODE = 3,\n\tNL80211_NAN_CAPA_NUM_ANTENNAS = 4,\n\tNL80211_NAN_CAPA_MAX_CHANNEL_SWITCH_TIME = 5,\n\tNL80211_NAN_CAPA_CAPABILITIES = 6,\n\t__NL80211_NAN_CAPABILITIES_LAST = 7,\n\tNL80211_NAN_CAPABILITIES_MAX = 6,\n};\n\nenum nl80211_nan_conf_attributes {\n\t__NL80211_NAN_CONF_INVALID = 0,\n\tNL80211_NAN_CONF_CLUSTER_ID = 1,\n\tNL80211_NAN_CONF_EXTRA_ATTRS = 2,\n\tNL80211_NAN_CONF_VENDOR_ELEMS = 3,\n\tNL80211_NAN_CONF_BAND_CONFIGS = 4,\n\tNL80211_NAN_CONF_SCAN_PERIOD = 5,\n\tNL80211_NAN_CONF_SCAN_DWELL_TIME = 6,\n\tNL80211_NAN_CONF_DISCOVERY_BEACON_INTERVAL = 7,\n\tNL80211_NAN_CONF_NOTIFY_DW = 8,\n\tNUM_NL80211_NAN_CONF_ATTR = 9,\n\tNL80211_NAN_CONF_ATTR_MAX = 8,\n};\n\nenum nl80211_nan_func_attributes {\n\t__NL80211_NAN_FUNC_INVALID = 0,\n\tNL80211_NAN_FUNC_TYPE = 1,\n\tNL80211_NAN_FUNC_SERVICE_ID = 2,\n\tNL80211_NAN_FUNC_PUBLISH_TYPE = 3,\n\tNL80211_NAN_FUNC_PUBLISH_BCAST = 4,\n\tNL80211_NAN_FUNC_SUBSCRIBE_ACTIVE = 5,\n\tNL80211_NAN_FUNC_FOLLOW_UP_ID = 6,\n\tNL80211_NAN_FUNC_FOLLOW_UP_REQ_ID = 7,\n\tNL80211_NAN_FUNC_FOLLOW_UP_DEST = 8,\n\tNL80211_NAN_FUNC_CLOSE_RANGE = 9,\n\tNL80211_NAN_FUNC_TTL = 10,\n\tNL80211_NAN_FUNC_SERVICE_INFO = 11,\n\tNL80211_NAN_FUNC_SRF = 12,\n\tNL80211_NAN_FUNC_RX_MATCH_FILTER = 13,\n\tNL80211_NAN_FUNC_TX_MATCH_FILTER = 14,\n\tNL80211_NAN_FUNC_INSTANCE_ID = 15,\n\tNL80211_NAN_FUNC_TERM_REASON = 16,\n\tNUM_NL80211_NAN_FUNC_ATTR = 17,\n\tNL80211_NAN_FUNC_ATTR_MAX = 16,\n};\n\nenum nl80211_nan_func_term_reason {\n\tNL80211_NAN_FUNC_TERM_REASON_USER_REQUEST = 0,\n\tNL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED = 1,\n\tNL80211_NAN_FUNC_TERM_REASON_ERROR = 2,\n};\n\nenum nl80211_nan_function_type {\n\tNL80211_NAN_FUNC_PUBLISH = 0,\n\tNL80211_NAN_FUNC_SUBSCRIBE = 1,\n\tNL80211_NAN_FUNC_FOLLOW_UP = 2,\n\t__NL80211_NAN_FUNC_TYPE_AFTER_LAST = 3,\n\tNL80211_NAN_FUNC_MAX_TYPE = 2,\n};\n\nenum nl80211_nan_match_attributes {\n\t__NL80211_NAN_MATCH_INVALID = 0,\n\tNL80211_NAN_MATCH_FUNC_LOCAL = 1,\n\tNL80211_NAN_MATCH_FUNC_PEER = 2,\n\tNUM_NL80211_NAN_MATCH_ATTR = 3,\n\tNL80211_NAN_MATCH_ATTR_MAX = 2,\n};\n\nenum nl80211_nan_publish_type {\n\tNL80211_NAN_SOLICITED_PUBLISH = 1,\n\tNL80211_NAN_UNSOLICITED_PUBLISH = 2,\n};\n\nenum nl80211_nan_srf_attributes {\n\t__NL80211_NAN_SRF_INVALID = 0,\n\tNL80211_NAN_SRF_INCLUDE = 1,\n\tNL80211_NAN_SRF_BF = 2,\n\tNL80211_NAN_SRF_BF_IDX = 3,\n\tNL80211_NAN_SRF_MAC_ADDRS = 4,\n\tNUM_NL80211_NAN_SRF_ATTR = 5,\n\tNL80211_NAN_SRF_ATTR_MAX = 4,\n};\n\nenum nl80211_obss_pd_attributes {\n\t__NL80211_HE_OBSS_PD_ATTR_INVALID = 0,\n\tNL80211_HE_OBSS_PD_ATTR_MIN_OFFSET = 1,\n\tNL80211_HE_OBSS_PD_ATTR_MAX_OFFSET = 2,\n\tNL80211_HE_OBSS_PD_ATTR_NON_SRG_MAX_OFFSET = 3,\n\tNL80211_HE_OBSS_PD_ATTR_BSS_COLOR_BITMAP = 4,\n\tNL80211_HE_OBSS_PD_ATTR_PARTIAL_BSSID_BITMAP = 5,\n\tNL80211_HE_OBSS_PD_ATTR_SR_CTRL = 6,\n\t__NL80211_HE_OBSS_PD_ATTR_LAST = 7,\n\tNL80211_HE_OBSS_PD_ATTR_MAX = 6,\n};\n\nenum nl80211_packet_pattern_attr {\n\t__NL80211_PKTPAT_INVALID = 0,\n\tNL80211_PKTPAT_MASK = 1,\n\tNL80211_PKTPAT_PATTERN = 2,\n\tNL80211_PKTPAT_OFFSET = 3,\n\tNUM_NL80211_PKTPAT = 4,\n\tMAX_NL80211_PKTPAT = 3,\n};\n\nenum nl80211_peer_measurement_attrs {\n\t__NL80211_PMSR_ATTR_INVALID = 0,\n\tNL80211_PMSR_ATTR_MAX_PEERS = 1,\n\tNL80211_PMSR_ATTR_REPORT_AP_TSF = 2,\n\tNL80211_PMSR_ATTR_RANDOMIZE_MAC_ADDR = 3,\n\tNL80211_PMSR_ATTR_TYPE_CAPA = 4,\n\tNL80211_PMSR_ATTR_PEERS = 5,\n\tNUM_NL80211_PMSR_ATTR = 6,\n\tNL80211_PMSR_ATTR_MAX = 5,\n};\n\nenum nl80211_peer_measurement_ftm_capa {\n\t__NL80211_PMSR_FTM_CAPA_ATTR_INVALID = 0,\n\tNL80211_PMSR_FTM_CAPA_ATTR_ASAP = 1,\n\tNL80211_PMSR_FTM_CAPA_ATTR_NON_ASAP = 2,\n\tNL80211_PMSR_FTM_CAPA_ATTR_REQ_LCI = 3,\n\tNL80211_PMSR_FTM_CAPA_ATTR_REQ_CIVICLOC = 4,\n\tNL80211_PMSR_FTM_CAPA_ATTR_PREAMBLES = 5,\n\tNL80211_PMSR_FTM_CAPA_ATTR_BANDWIDTHS = 6,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_BURSTS_EXPONENT = 7,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_FTMS_PER_BURST = 8,\n\tNL80211_PMSR_FTM_CAPA_ATTR_TRIGGER_BASED = 9,\n\tNL80211_PMSR_FTM_CAPA_ATTR_NON_TRIGGER_BASED = 10,\n\tNL80211_PMSR_FTM_CAPA_ATTR_6GHZ_SUPPORT = 11,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_TX_LTF_REP = 12,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_RX_LTF_REP = 13,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_TX_STS = 14,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_RX_STS = 15,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_TOTAL_LTF_TX = 16,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_TOTAL_LTF_RX = 17,\n\tNL80211_PMSR_FTM_CAPA_ATTR_RSTA_SUPPORT = 18,\n\tNUM_NL80211_PMSR_FTM_CAPA_ATTR = 19,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX = 18,\n};\n\nenum nl80211_peer_measurement_ftm_failure_reasons {\n\tNL80211_PMSR_FTM_FAILURE_UNSPECIFIED = 0,\n\tNL80211_PMSR_FTM_FAILURE_NO_RESPONSE = 1,\n\tNL80211_PMSR_FTM_FAILURE_REJECTED = 2,\n\tNL80211_PMSR_FTM_FAILURE_WRONG_CHANNEL = 3,\n\tNL80211_PMSR_FTM_FAILURE_PEER_NOT_CAPABLE = 4,\n\tNL80211_PMSR_FTM_FAILURE_INVALID_TIMESTAMP = 5,\n\tNL80211_PMSR_FTM_FAILURE_PEER_BUSY = 6,\n\tNL80211_PMSR_FTM_FAILURE_BAD_CHANGED_PARAMS = 7,\n};\n\nenum nl80211_peer_measurement_ftm_req {\n\t__NL80211_PMSR_FTM_REQ_ATTR_INVALID = 0,\n\tNL80211_PMSR_FTM_REQ_ATTR_ASAP = 1,\n\tNL80211_PMSR_FTM_REQ_ATTR_PREAMBLE = 2,\n\tNL80211_PMSR_FTM_REQ_ATTR_NUM_BURSTS_EXP = 3,\n\tNL80211_PMSR_FTM_REQ_ATTR_BURST_PERIOD = 4,\n\tNL80211_PMSR_FTM_REQ_ATTR_BURST_DURATION = 5,\n\tNL80211_PMSR_FTM_REQ_ATTR_FTMS_PER_BURST = 6,\n\tNL80211_PMSR_FTM_REQ_ATTR_NUM_FTMR_RETRIES = 7,\n\tNL80211_PMSR_FTM_REQ_ATTR_REQUEST_LCI = 8,\n\tNL80211_PMSR_FTM_REQ_ATTR_REQUEST_CIVICLOC = 9,\n\tNL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED = 10,\n\tNL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED = 11,\n\tNL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK = 12,\n\tNL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR = 13,\n\tNL80211_PMSR_FTM_REQ_ATTR_RSTA = 14,\n\tNUM_NL80211_PMSR_FTM_REQ_ATTR = 15,\n\tNL80211_PMSR_FTM_REQ_ATTR_MAX = 14,\n};\n\nenum nl80211_peer_measurement_ftm_resp {\n\t__NL80211_PMSR_FTM_RESP_ATTR_INVALID = 0,\n\tNL80211_PMSR_FTM_RESP_ATTR_FAIL_REASON = 1,\n\tNL80211_PMSR_FTM_RESP_ATTR_BURST_INDEX = 2,\n\tNL80211_PMSR_FTM_RESP_ATTR_NUM_FTMR_ATTEMPTS = 3,\n\tNL80211_PMSR_FTM_RESP_ATTR_NUM_FTMR_SUCCESSES = 4,\n\tNL80211_PMSR_FTM_RESP_ATTR_BUSY_RETRY_TIME = 5,\n\tNL80211_PMSR_FTM_RESP_ATTR_NUM_BURSTS_EXP = 6,\n\tNL80211_PMSR_FTM_RESP_ATTR_BURST_DURATION = 7,\n\tNL80211_PMSR_FTM_RESP_ATTR_FTMS_PER_BURST = 8,\n\tNL80211_PMSR_FTM_RESP_ATTR_RSSI_AVG = 9,\n\tNL80211_PMSR_FTM_RESP_ATTR_RSSI_SPREAD = 10,\n\tNL80211_PMSR_FTM_RESP_ATTR_TX_RATE = 11,\n\tNL80211_PMSR_FTM_RESP_ATTR_RX_RATE = 12,\n\tNL80211_PMSR_FTM_RESP_ATTR_RTT_AVG = 13,\n\tNL80211_PMSR_FTM_RESP_ATTR_RTT_VARIANCE = 14,\n\tNL80211_PMSR_FTM_RESP_ATTR_RTT_SPREAD = 15,\n\tNL80211_PMSR_FTM_RESP_ATTR_DIST_AVG = 16,\n\tNL80211_PMSR_FTM_RESP_ATTR_DIST_VARIANCE = 17,\n\tNL80211_PMSR_FTM_RESP_ATTR_DIST_SPREAD = 18,\n\tNL80211_PMSR_FTM_RESP_ATTR_LCI = 19,\n\tNL80211_PMSR_FTM_RESP_ATTR_CIVICLOC = 20,\n\tNL80211_PMSR_FTM_RESP_ATTR_PAD = 21,\n\tNL80211_PMSR_FTM_RESP_ATTR_BURST_PERIOD = 22,\n\tNUM_NL80211_PMSR_FTM_RESP_ATTR = 23,\n\tNL80211_PMSR_FTM_RESP_ATTR_MAX = 22,\n};\n\nenum nl80211_peer_measurement_peer_attrs {\n\t__NL80211_PMSR_PEER_ATTR_INVALID = 0,\n\tNL80211_PMSR_PEER_ATTR_ADDR = 1,\n\tNL80211_PMSR_PEER_ATTR_CHAN = 2,\n\tNL80211_PMSR_PEER_ATTR_REQ = 3,\n\tNL80211_PMSR_PEER_ATTR_RESP = 4,\n\tNUM_NL80211_PMSR_PEER_ATTRS = 5,\n\tNL80211_PMSR_PEER_ATTR_MAX = 4,\n};\n\nenum nl80211_peer_measurement_req {\n\t__NL80211_PMSR_REQ_ATTR_INVALID = 0,\n\tNL80211_PMSR_REQ_ATTR_DATA = 1,\n\tNL80211_PMSR_REQ_ATTR_GET_AP_TSF = 2,\n\tNUM_NL80211_PMSR_REQ_ATTRS = 3,\n\tNL80211_PMSR_REQ_ATTR_MAX = 2,\n};\n\nenum nl80211_peer_measurement_resp {\n\t__NL80211_PMSR_RESP_ATTR_INVALID = 0,\n\tNL80211_PMSR_RESP_ATTR_DATA = 1,\n\tNL80211_PMSR_RESP_ATTR_STATUS = 2,\n\tNL80211_PMSR_RESP_ATTR_HOST_TIME = 3,\n\tNL80211_PMSR_RESP_ATTR_AP_TSF = 4,\n\tNL80211_PMSR_RESP_ATTR_FINAL = 5,\n\tNL80211_PMSR_RESP_ATTR_PAD = 6,\n\tNUM_NL80211_PMSR_RESP_ATTRS = 7,\n\tNL80211_PMSR_RESP_ATTR_MAX = 6,\n};\n\nenum nl80211_peer_measurement_status {\n\tNL80211_PMSR_STATUS_SUCCESS = 0,\n\tNL80211_PMSR_STATUS_REFUSED = 1,\n\tNL80211_PMSR_STATUS_TIMEOUT = 2,\n\tNL80211_PMSR_STATUS_FAILURE = 3,\n};\n\nenum nl80211_peer_measurement_type {\n\tNL80211_PMSR_TYPE_INVALID = 0,\n\tNL80211_PMSR_TYPE_FTM = 1,\n\tNUM_NL80211_PMSR_TYPES = 2,\n\tNL80211_PMSR_TYPE_MAX = 1,\n};\n\nenum nl80211_plink_action {\n\tNL80211_PLINK_ACTION_NO_ACTION = 0,\n\tNL80211_PLINK_ACTION_OPEN = 1,\n\tNL80211_PLINK_ACTION_BLOCK = 2,\n\tNUM_NL80211_PLINK_ACTIONS = 3,\n};\n\nenum nl80211_plink_state {\n\tNL80211_PLINK_LISTEN = 0,\n\tNL80211_PLINK_OPN_SNT = 1,\n\tNL80211_PLINK_OPN_RCVD = 2,\n\tNL80211_PLINK_CNF_RCVD = 3,\n\tNL80211_PLINK_ESTAB = 4,\n\tNL80211_PLINK_HOLDING = 5,\n\tNL80211_PLINK_BLOCKED = 6,\n\tNUM_NL80211_PLINK_STATES = 7,\n\tMAX_NL80211_PLINK_STATES = 6,\n};\n\nenum nl80211_pmksa_candidate_attr {\n\t__NL80211_PMKSA_CANDIDATE_INVALID = 0,\n\tNL80211_PMKSA_CANDIDATE_INDEX = 1,\n\tNL80211_PMKSA_CANDIDATE_BSSID = 2,\n\tNL80211_PMKSA_CANDIDATE_PREAUTH = 3,\n\tNUM_NL80211_PMKSA_CANDIDATE = 4,\n\tMAX_NL80211_PMKSA_CANDIDATE = 3,\n};\n\nenum nl80211_preamble {\n\tNL80211_PREAMBLE_LEGACY = 0,\n\tNL80211_PREAMBLE_HT = 1,\n\tNL80211_PREAMBLE_VHT = 2,\n\tNL80211_PREAMBLE_DMG = 3,\n\tNL80211_PREAMBLE_HE = 4,\n};\n\nenum nl80211_protocol_features {\n\tNL80211_PROTOCOL_FEATURE_SPLIT_WIPHY_DUMP = 1,\n};\n\nenum nl80211_ps_state {\n\tNL80211_PS_DISABLED = 0,\n\tNL80211_PS_ENABLED = 1,\n};\n\nenum nl80211_radar_event {\n\tNL80211_RADAR_DETECTED = 0,\n\tNL80211_RADAR_CAC_FINISHED = 1,\n\tNL80211_RADAR_CAC_ABORTED = 2,\n\tNL80211_RADAR_NOP_FINISHED = 3,\n\tNL80211_RADAR_PRE_CAC_EXPIRED = 4,\n\tNL80211_RADAR_CAC_STARTED = 5,\n};\n\nenum nl80211_rate_info {\n\t__NL80211_RATE_INFO_INVALID = 0,\n\tNL80211_RATE_INFO_BITRATE = 1,\n\tNL80211_RATE_INFO_MCS = 2,\n\tNL80211_RATE_INFO_40_MHZ_WIDTH = 3,\n\tNL80211_RATE_INFO_SHORT_GI = 4,\n\tNL80211_RATE_INFO_BITRATE32 = 5,\n\tNL80211_RATE_INFO_VHT_MCS = 6,\n\tNL80211_RATE_INFO_VHT_NSS = 7,\n\tNL80211_RATE_INFO_80_MHZ_WIDTH = 8,\n\tNL80211_RATE_INFO_80P80_MHZ_WIDTH = 9,\n\tNL80211_RATE_INFO_160_MHZ_WIDTH = 10,\n\tNL80211_RATE_INFO_10_MHZ_WIDTH = 11,\n\tNL80211_RATE_INFO_5_MHZ_WIDTH = 12,\n\tNL80211_RATE_INFO_HE_MCS = 13,\n\tNL80211_RATE_INFO_HE_NSS = 14,\n\tNL80211_RATE_INFO_HE_GI = 15,\n\tNL80211_RATE_INFO_HE_DCM = 16,\n\tNL80211_RATE_INFO_HE_RU_ALLOC = 17,\n\tNL80211_RATE_INFO_320_MHZ_WIDTH = 18,\n\tNL80211_RATE_INFO_EHT_MCS = 19,\n\tNL80211_RATE_INFO_EHT_NSS = 20,\n\tNL80211_RATE_INFO_EHT_GI = 21,\n\tNL80211_RATE_INFO_EHT_RU_ALLOC = 22,\n\tNL80211_RATE_INFO_S1G_MCS = 23,\n\tNL80211_RATE_INFO_S1G_NSS = 24,\n\tNL80211_RATE_INFO_1_MHZ_WIDTH = 25,\n\tNL80211_RATE_INFO_2_MHZ_WIDTH = 26,\n\tNL80211_RATE_INFO_4_MHZ_WIDTH = 27,\n\tNL80211_RATE_INFO_8_MHZ_WIDTH = 28,\n\tNL80211_RATE_INFO_16_MHZ_WIDTH = 29,\n\tNL80211_RATE_INFO_UHR_MCS = 30,\n\tNL80211_RATE_INFO_UHR_ELR = 31,\n\tNL80211_RATE_INFO_UHR_IM = 32,\n\t__NL80211_RATE_INFO_AFTER_LAST = 33,\n\tNL80211_RATE_INFO_MAX = 32,\n};\n\nenum nl80211_reg_initiator {\n\tNL80211_REGDOM_SET_BY_CORE = 0,\n\tNL80211_REGDOM_SET_BY_USER = 1,\n\tNL80211_REGDOM_SET_BY_DRIVER = 2,\n\tNL80211_REGDOM_SET_BY_COUNTRY_IE = 3,\n};\n\nenum nl80211_reg_rule_attr {\n\t__NL80211_REG_RULE_ATTR_INVALID = 0,\n\tNL80211_ATTR_REG_RULE_FLAGS = 1,\n\tNL80211_ATTR_FREQ_RANGE_START = 2,\n\tNL80211_ATTR_FREQ_RANGE_END = 3,\n\tNL80211_ATTR_FREQ_RANGE_MAX_BW = 4,\n\tNL80211_ATTR_POWER_RULE_MAX_ANT_GAIN = 5,\n\tNL80211_ATTR_POWER_RULE_MAX_EIRP = 6,\n\tNL80211_ATTR_DFS_CAC_TIME = 7,\n\tNL80211_ATTR_POWER_RULE_PSD = 8,\n\t__NL80211_REG_RULE_ATTR_AFTER_LAST = 9,\n\tNL80211_REG_RULE_ATTR_MAX = 8,\n};\n\nenum nl80211_reg_rule_flags {\n\tNL80211_RRF_NO_OFDM = 1,\n\tNL80211_RRF_NO_CCK = 2,\n\tNL80211_RRF_NO_INDOOR = 4,\n\tNL80211_RRF_NO_OUTDOOR = 8,\n\tNL80211_RRF_DFS = 16,\n\tNL80211_RRF_PTP_ONLY = 32,\n\tNL80211_RRF_PTMP_ONLY = 64,\n\tNL80211_RRF_NO_IR = 128,\n\t__NL80211_RRF_NO_IBSS = 256,\n\tNL80211_RRF_AUTO_BW = 2048,\n\tNL80211_RRF_IR_CONCURRENT = 4096,\n\tNL80211_RRF_NO_HT40MINUS = 8192,\n\tNL80211_RRF_NO_HT40PLUS = 16384,\n\tNL80211_RRF_NO_80MHZ = 32768,\n\tNL80211_RRF_NO_160MHZ = 65536,\n\tNL80211_RRF_NO_HE = 131072,\n\tNL80211_RRF_NO_320MHZ = 262144,\n\tNL80211_RRF_NO_EHT = 524288,\n\tNL80211_RRF_PSD = 1048576,\n\tNL80211_RRF_DFS_CONCURRENT = 2097152,\n\tNL80211_RRF_NO_6GHZ_VLP_CLIENT = 4194304,\n\tNL80211_RRF_NO_6GHZ_AFC_CLIENT = 8388608,\n\tNL80211_RRF_ALLOW_6GHZ_VLP_AP = 16777216,\n\tNL80211_RRF_ALLOW_20MHZ_ACTIVITY = 33554432,\n\tNL80211_RRF_NO_UHR = 67108864,\n};\n\nenum nl80211_reg_type {\n\tNL80211_REGDOM_TYPE_COUNTRY = 0,\n\tNL80211_REGDOM_TYPE_WORLD = 1,\n\tNL80211_REGDOM_TYPE_CUSTOM_WORLD = 2,\n\tNL80211_REGDOM_TYPE_INTERSECTION = 3,\n};\n\nenum nl80211_rekey_data {\n\t__NL80211_REKEY_DATA_INVALID = 0,\n\tNL80211_REKEY_DATA_KEK = 1,\n\tNL80211_REKEY_DATA_KCK = 2,\n\tNL80211_REKEY_DATA_REPLAY_CTR = 3,\n\tNL80211_REKEY_DATA_AKM = 4,\n\tNUM_NL80211_REKEY_DATA = 5,\n\tMAX_NL80211_REKEY_DATA = 4,\n};\n\nenum nl80211_s1g_short_beacon_attrs {\n\t__NL80211_S1G_SHORT_BEACON_ATTR_INVALID = 0,\n\tNL80211_S1G_SHORT_BEACON_ATTR_HEAD = 1,\n\tNL80211_S1G_SHORT_BEACON_ATTR_TAIL = 2,\n\t__NL80211_S1G_SHORT_BEACON_ATTR_LAST = 3,\n\tNL80211_S1G_SHORT_BEACON_ATTR_MAX = 2,\n};\n\nenum nl80211_sae_pwe_mechanism {\n\tNL80211_SAE_PWE_UNSPECIFIED = 0,\n\tNL80211_SAE_PWE_HUNT_AND_PECK = 1,\n\tNL80211_SAE_PWE_HASH_TO_ELEMENT = 2,\n\tNL80211_SAE_PWE_BOTH = 3,\n};\n\nenum nl80211_sar_attrs {\n\t__NL80211_SAR_ATTR_INVALID = 0,\n\tNL80211_SAR_ATTR_TYPE = 1,\n\tNL80211_SAR_ATTR_SPECS = 2,\n\t__NL80211_SAR_ATTR_LAST = 3,\n\tNL80211_SAR_ATTR_MAX = 2,\n};\n\nenum nl80211_sar_specs_attrs {\n\t__NL80211_SAR_ATTR_SPECS_INVALID = 0,\n\tNL80211_SAR_ATTR_SPECS_POWER = 1,\n\tNL80211_SAR_ATTR_SPECS_RANGE_INDEX = 2,\n\tNL80211_SAR_ATTR_SPECS_START_FREQ = 3,\n\tNL80211_SAR_ATTR_SPECS_END_FREQ = 4,\n\t__NL80211_SAR_ATTR_SPECS_LAST = 5,\n\tNL80211_SAR_ATTR_SPECS_MAX = 4,\n};\n\nenum nl80211_sar_type {\n\tNL80211_SAR_TYPE_POWER = 0,\n\tNUM_NL80211_SAR_TYPE = 1,\n};\n\nenum nl80211_scan_flags {\n\tNL80211_SCAN_FLAG_LOW_PRIORITY = 1,\n\tNL80211_SCAN_FLAG_FLUSH = 2,\n\tNL80211_SCAN_FLAG_AP = 4,\n\tNL80211_SCAN_FLAG_RANDOM_ADDR = 8,\n\tNL80211_SCAN_FLAG_FILS_MAX_CHANNEL_TIME = 16,\n\tNL80211_SCAN_FLAG_ACCEPT_BCAST_PROBE_RESP = 32,\n\tNL80211_SCAN_FLAG_OCE_PROBE_REQ_HIGH_TX_RATE = 64,\n\tNL80211_SCAN_FLAG_OCE_PROBE_REQ_DEFERRAL_SUPPRESSION = 128,\n\tNL80211_SCAN_FLAG_LOW_SPAN = 256,\n\tNL80211_SCAN_FLAG_LOW_POWER = 512,\n\tNL80211_SCAN_FLAG_HIGH_ACCURACY = 1024,\n\tNL80211_SCAN_FLAG_RANDOM_SN = 2048,\n\tNL80211_SCAN_FLAG_MIN_PREQ_CONTENT = 4096,\n\tNL80211_SCAN_FLAG_FREQ_KHZ = 8192,\n\tNL80211_SCAN_FLAG_COLOCATED_6GHZ = 16384,\n};\n\nenum nl80211_sched_scan_match_attr {\n\t__NL80211_SCHED_SCAN_MATCH_ATTR_INVALID = 0,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_SSID = 1,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RSSI = 2,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RELATIVE_RSSI = 3,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RSSI_ADJUST = 4,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_BSSID = 5,\n\tNL80211_SCHED_SCAN_MATCH_PER_BAND_RSSI = 6,\n\t__NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST = 7,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_MAX = 6,\n};\n\nenum nl80211_sched_scan_plan {\n\t__NL80211_SCHED_SCAN_PLAN_INVALID = 0,\n\tNL80211_SCHED_SCAN_PLAN_INTERVAL = 1,\n\tNL80211_SCHED_SCAN_PLAN_ITERATIONS = 2,\n\t__NL80211_SCHED_SCAN_PLAN_AFTER_LAST = 3,\n\tNL80211_SCHED_SCAN_PLAN_MAX = 2,\n};\n\nenum nl80211_smps_mode {\n\tNL80211_SMPS_OFF = 0,\n\tNL80211_SMPS_STATIC = 1,\n\tNL80211_SMPS_DYNAMIC = 2,\n\t__NL80211_SMPS_AFTER_LAST = 3,\n\tNL80211_SMPS_MAX = 2,\n};\n\nenum nl80211_sta_bss_param {\n\t__NL80211_STA_BSS_PARAM_INVALID = 0,\n\tNL80211_STA_BSS_PARAM_CTS_PROT = 1,\n\tNL80211_STA_BSS_PARAM_SHORT_PREAMBLE = 2,\n\tNL80211_STA_BSS_PARAM_SHORT_SLOT_TIME = 3,\n\tNL80211_STA_BSS_PARAM_DTIM_PERIOD = 4,\n\tNL80211_STA_BSS_PARAM_BEACON_INTERVAL = 5,\n\t__NL80211_STA_BSS_PARAM_AFTER_LAST = 6,\n\tNL80211_STA_BSS_PARAM_MAX = 5,\n};\n\nenum nl80211_sta_flags {\n\t__NL80211_STA_FLAG_INVALID = 0,\n\tNL80211_STA_FLAG_AUTHORIZED = 1,\n\tNL80211_STA_FLAG_SHORT_PREAMBLE = 2,\n\tNL80211_STA_FLAG_WME = 3,\n\tNL80211_STA_FLAG_MFP = 4,\n\tNL80211_STA_FLAG_AUTHENTICATED = 5,\n\tNL80211_STA_FLAG_TDLS_PEER = 6,\n\tNL80211_STA_FLAG_ASSOCIATED = 7,\n\tNL80211_STA_FLAG_SPP_AMSDU = 8,\n\t__NL80211_STA_FLAG_AFTER_LAST = 9,\n\tNL80211_STA_FLAG_MAX = 8,\n};\n\nenum nl80211_sta_info {\n\t__NL80211_STA_INFO_INVALID = 0,\n\tNL80211_STA_INFO_INACTIVE_TIME = 1,\n\tNL80211_STA_INFO_RX_BYTES = 2,\n\tNL80211_STA_INFO_TX_BYTES = 3,\n\tNL80211_STA_INFO_LLID = 4,\n\tNL80211_STA_INFO_PLID = 5,\n\tNL80211_STA_INFO_PLINK_STATE = 6,\n\tNL80211_STA_INFO_SIGNAL = 7,\n\tNL80211_STA_INFO_TX_BITRATE = 8,\n\tNL80211_STA_INFO_RX_PACKETS = 9,\n\tNL80211_STA_INFO_TX_PACKETS = 10,\n\tNL80211_STA_INFO_TX_RETRIES = 11,\n\tNL80211_STA_INFO_TX_FAILED = 12,\n\tNL80211_STA_INFO_SIGNAL_AVG = 13,\n\tNL80211_STA_INFO_RX_BITRATE = 14,\n\tNL80211_STA_INFO_BSS_PARAM = 15,\n\tNL80211_STA_INFO_CONNECTED_TIME = 16,\n\tNL80211_STA_INFO_STA_FLAGS = 17,\n\tNL80211_STA_INFO_BEACON_LOSS = 18,\n\tNL80211_STA_INFO_T_OFFSET = 19,\n\tNL80211_STA_INFO_LOCAL_PM = 20,\n\tNL80211_STA_INFO_PEER_PM = 21,\n\tNL80211_STA_INFO_NONPEER_PM = 22,\n\tNL80211_STA_INFO_RX_BYTES64 = 23,\n\tNL80211_STA_INFO_TX_BYTES64 = 24,\n\tNL80211_STA_INFO_CHAIN_SIGNAL = 25,\n\tNL80211_STA_INFO_CHAIN_SIGNAL_AVG = 26,\n\tNL80211_STA_INFO_EXPECTED_THROUGHPUT = 27,\n\tNL80211_STA_INFO_RX_DROP_MISC = 28,\n\tNL80211_STA_INFO_BEACON_RX = 29,\n\tNL80211_STA_INFO_BEACON_SIGNAL_AVG = 30,\n\tNL80211_STA_INFO_TID_STATS = 31,\n\tNL80211_STA_INFO_RX_DURATION = 32,\n\tNL80211_STA_INFO_PAD = 33,\n\tNL80211_STA_INFO_ACK_SIGNAL = 34,\n\tNL80211_STA_INFO_ACK_SIGNAL_AVG = 35,\n\tNL80211_STA_INFO_RX_MPDUS = 36,\n\tNL80211_STA_INFO_FCS_ERROR_COUNT = 37,\n\tNL80211_STA_INFO_CONNECTED_TO_GATE = 38,\n\tNL80211_STA_INFO_TX_DURATION = 39,\n\tNL80211_STA_INFO_AIRTIME_WEIGHT = 40,\n\tNL80211_STA_INFO_AIRTIME_LINK_METRIC = 41,\n\tNL80211_STA_INFO_ASSOC_AT_BOOTTIME = 42,\n\tNL80211_STA_INFO_CONNECTED_TO_AS = 43,\n\t__NL80211_STA_INFO_AFTER_LAST = 44,\n\tNL80211_STA_INFO_MAX = 43,\n};\n\nenum nl80211_sta_p2p_ps_status {\n\tNL80211_P2P_PS_UNSUPPORTED = 0,\n\tNL80211_P2P_PS_SUPPORTED = 1,\n\tNUM_NL80211_P2P_PS_STATUS = 2,\n};\n\nenum nl80211_sta_wme_attr {\n\t__NL80211_STA_WME_INVALID = 0,\n\tNL80211_STA_WME_UAPSD_QUEUES = 1,\n\tNL80211_STA_WME_MAX_SP = 2,\n\t__NL80211_STA_WME_AFTER_LAST = 3,\n\tNL80211_STA_WME_MAX = 2,\n};\n\nenum nl80211_survey_info {\n\t__NL80211_SURVEY_INFO_INVALID = 0,\n\tNL80211_SURVEY_INFO_FREQUENCY = 1,\n\tNL80211_SURVEY_INFO_NOISE = 2,\n\tNL80211_SURVEY_INFO_IN_USE = 3,\n\tNL80211_SURVEY_INFO_TIME = 4,\n\tNL80211_SURVEY_INFO_TIME_BUSY = 5,\n\tNL80211_SURVEY_INFO_TIME_EXT_BUSY = 6,\n\tNL80211_SURVEY_INFO_TIME_RX = 7,\n\tNL80211_SURVEY_INFO_TIME_TX = 8,\n\tNL80211_SURVEY_INFO_TIME_SCAN = 9,\n\tNL80211_SURVEY_INFO_PAD = 10,\n\tNL80211_SURVEY_INFO_TIME_BSS_RX = 11,\n\tNL80211_SURVEY_INFO_FREQUENCY_OFFSET = 12,\n\t__NL80211_SURVEY_INFO_AFTER_LAST = 13,\n\tNL80211_SURVEY_INFO_MAX = 12,\n};\n\nenum nl80211_tdls_operation {\n\tNL80211_TDLS_DISCOVERY_REQ = 0,\n\tNL80211_TDLS_SETUP = 1,\n\tNL80211_TDLS_TEARDOWN = 2,\n\tNL80211_TDLS_ENABLE_LINK = 3,\n\tNL80211_TDLS_DISABLE_LINK = 4,\n};\n\nenum nl80211_tid_config {\n\tNL80211_TID_CONFIG_ENABLE = 0,\n\tNL80211_TID_CONFIG_DISABLE = 1,\n};\n\nenum nl80211_tid_config_attr {\n\t__NL80211_TID_CONFIG_ATTR_INVALID = 0,\n\tNL80211_TID_CONFIG_ATTR_PAD = 1,\n\tNL80211_TID_CONFIG_ATTR_VIF_SUPP = 2,\n\tNL80211_TID_CONFIG_ATTR_PEER_SUPP = 3,\n\tNL80211_TID_CONFIG_ATTR_OVERRIDE = 4,\n\tNL80211_TID_CONFIG_ATTR_TIDS = 5,\n\tNL80211_TID_CONFIG_ATTR_NOACK = 6,\n\tNL80211_TID_CONFIG_ATTR_RETRY_SHORT = 7,\n\tNL80211_TID_CONFIG_ATTR_RETRY_LONG = 8,\n\tNL80211_TID_CONFIG_ATTR_AMPDU_CTRL = 9,\n\tNL80211_TID_CONFIG_ATTR_RTSCTS_CTRL = 10,\n\tNL80211_TID_CONFIG_ATTR_AMSDU_CTRL = 11,\n\tNL80211_TID_CONFIG_ATTR_TX_RATE_TYPE = 12,\n\tNL80211_TID_CONFIG_ATTR_TX_RATE = 13,\n\t__NL80211_TID_CONFIG_ATTR_AFTER_LAST = 14,\n\tNL80211_TID_CONFIG_ATTR_MAX = 13,\n};\n\nenum nl80211_tid_stats {\n\t__NL80211_TID_STATS_INVALID = 0,\n\tNL80211_TID_STATS_RX_MSDU = 1,\n\tNL80211_TID_STATS_TX_MSDU = 2,\n\tNL80211_TID_STATS_TX_MSDU_RETRIES = 3,\n\tNL80211_TID_STATS_TX_MSDU_FAILED = 4,\n\tNL80211_TID_STATS_PAD = 5,\n\tNL80211_TID_STATS_TXQ_STATS = 6,\n\tNUM_NL80211_TID_STATS = 7,\n\tNL80211_TID_STATS_MAX = 6,\n};\n\nenum nl80211_timeout_reason {\n\tNL80211_TIMEOUT_UNSPECIFIED = 0,\n\tNL80211_TIMEOUT_SCAN = 1,\n\tNL80211_TIMEOUT_AUTH = 2,\n\tNL80211_TIMEOUT_ASSOC = 3,\n};\n\nenum nl80211_tx_power_setting {\n\tNL80211_TX_POWER_AUTOMATIC = 0,\n\tNL80211_TX_POWER_LIMITED = 1,\n\tNL80211_TX_POWER_FIXED = 2,\n};\n\nenum nl80211_tx_rate_attributes {\n\t__NL80211_TXRATE_INVALID = 0,\n\tNL80211_TXRATE_LEGACY = 1,\n\tNL80211_TXRATE_HT = 2,\n\tNL80211_TXRATE_VHT = 3,\n\tNL80211_TXRATE_GI = 4,\n\tNL80211_TXRATE_HE = 5,\n\tNL80211_TXRATE_HE_GI = 6,\n\tNL80211_TXRATE_HE_LTF = 7,\n\tNL80211_TXRATE_EHT = 8,\n\tNL80211_TXRATE_EHT_GI = 9,\n\tNL80211_TXRATE_EHT_LTF = 10,\n\t__NL80211_TXRATE_AFTER_LAST = 11,\n\tNL80211_TXRATE_MAX = 10,\n};\n\nenum nl80211_tx_rate_setting {\n\tNL80211_TX_RATE_AUTOMATIC = 0,\n\tNL80211_TX_RATE_LIMITED = 1,\n\tNL80211_TX_RATE_FIXED = 2,\n};\n\nenum nl80211_txq_attr {\n\t__NL80211_TXQ_ATTR_INVALID = 0,\n\tNL80211_TXQ_ATTR_AC = 1,\n\tNL80211_TXQ_ATTR_TXOP = 2,\n\tNL80211_TXQ_ATTR_CWMIN = 3,\n\tNL80211_TXQ_ATTR_CWMAX = 4,\n\tNL80211_TXQ_ATTR_AIFS = 5,\n\t__NL80211_TXQ_ATTR_AFTER_LAST = 6,\n\tNL80211_TXQ_ATTR_MAX = 5,\n};\n\nenum nl80211_txq_stats {\n\t__NL80211_TXQ_STATS_INVALID = 0,\n\tNL80211_TXQ_STATS_BACKLOG_BYTES = 1,\n\tNL80211_TXQ_STATS_BACKLOG_PACKETS = 2,\n\tNL80211_TXQ_STATS_FLOWS = 3,\n\tNL80211_TXQ_STATS_DROPS = 4,\n\tNL80211_TXQ_STATS_ECN_MARKS = 5,\n\tNL80211_TXQ_STATS_OVERLIMIT = 6,\n\tNL80211_TXQ_STATS_OVERMEMORY = 7,\n\tNL80211_TXQ_STATS_COLLISIONS = 8,\n\tNL80211_TXQ_STATS_TX_BYTES = 9,\n\tNL80211_TXQ_STATS_TX_PACKETS = 10,\n\tNL80211_TXQ_STATS_MAX_FLOWS = 11,\n\tNUM_NL80211_TXQ_STATS = 12,\n\tNL80211_TXQ_STATS_MAX = 11,\n};\n\nenum nl80211_txrate_gi {\n\tNL80211_TXRATE_DEFAULT_GI = 0,\n\tNL80211_TXRATE_FORCE_SGI = 1,\n\tNL80211_TXRATE_FORCE_LGI = 2,\n};\n\nenum nl80211_unsol_bcast_probe_resp_attributes {\n\t__NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INVALID = 0,\n\tNL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INT = 1,\n\tNL80211_UNSOL_BCAST_PROBE_RESP_ATTR_TMPL = 2,\n\t__NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_LAST = 3,\n\tNL80211_UNSOL_BCAST_PROBE_RESP_ATTR_MAX = 2,\n};\n\nenum nl80211_user_reg_hint_type {\n\tNL80211_USER_REG_HINT_USER = 0,\n\tNL80211_USER_REG_HINT_CELL_BASE = 1,\n\tNL80211_USER_REG_HINT_INDOOR = 2,\n};\n\nenum nl80211_wiphy_radio_attrs {\n\t__NL80211_WIPHY_RADIO_ATTR_INVALID = 0,\n\tNL80211_WIPHY_RADIO_ATTR_INDEX = 1,\n\tNL80211_WIPHY_RADIO_ATTR_FREQ_RANGE = 2,\n\tNL80211_WIPHY_RADIO_ATTR_INTERFACE_COMBINATION = 3,\n\tNL80211_WIPHY_RADIO_ATTR_ANTENNA_MASK = 4,\n\tNL80211_WIPHY_RADIO_ATTR_RTS_THRESHOLD = 5,\n\t__NL80211_WIPHY_RADIO_ATTR_LAST = 6,\n\tNL80211_WIPHY_RADIO_ATTR_MAX = 5,\n};\n\nenum nl80211_wiphy_radio_freq_range {\n\t__NL80211_WIPHY_RADIO_FREQ_ATTR_INVALID = 0,\n\tNL80211_WIPHY_RADIO_FREQ_ATTR_START = 1,\n\tNL80211_WIPHY_RADIO_FREQ_ATTR_END = 2,\n\t__NL80211_WIPHY_RADIO_FREQ_ATTR_LAST = 3,\n\tNL80211_WIPHY_RADIO_FREQ_ATTR_MAX = 2,\n};\n\nenum nl80211_wmm_rule {\n\t__NL80211_WMMR_INVALID = 0,\n\tNL80211_WMMR_CW_MIN = 1,\n\tNL80211_WMMR_CW_MAX = 2,\n\tNL80211_WMMR_AIFSN = 3,\n\tNL80211_WMMR_TXOP = 4,\n\t__NL80211_WMMR_LAST = 5,\n\tNL80211_WMMR_MAX = 4,\n};\n\nenum nl80211_wowlan_tcp_attrs {\n\t__NL80211_WOWLAN_TCP_INVALID = 0,\n\tNL80211_WOWLAN_TCP_SRC_IPV4 = 1,\n\tNL80211_WOWLAN_TCP_DST_IPV4 = 2,\n\tNL80211_WOWLAN_TCP_DST_MAC = 3,\n\tNL80211_WOWLAN_TCP_SRC_PORT = 4,\n\tNL80211_WOWLAN_TCP_DST_PORT = 5,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD = 6,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD_SEQ = 7,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD_TOKEN = 8,\n\tNL80211_WOWLAN_TCP_DATA_INTERVAL = 9,\n\tNL80211_WOWLAN_TCP_WAKE_PAYLOAD = 10,\n\tNL80211_WOWLAN_TCP_WAKE_MASK = 11,\n\tNUM_NL80211_WOWLAN_TCP = 12,\n\tMAX_NL80211_WOWLAN_TCP = 11,\n};\n\nenum nl80211_wowlan_triggers {\n\t__NL80211_WOWLAN_TRIG_INVALID = 0,\n\tNL80211_WOWLAN_TRIG_ANY = 1,\n\tNL80211_WOWLAN_TRIG_DISCONNECT = 2,\n\tNL80211_WOWLAN_TRIG_MAGIC_PKT = 3,\n\tNL80211_WOWLAN_TRIG_PKT_PATTERN = 4,\n\tNL80211_WOWLAN_TRIG_GTK_REKEY_SUPPORTED = 5,\n\tNL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE = 6,\n\tNL80211_WOWLAN_TRIG_EAP_IDENT_REQUEST = 7,\n\tNL80211_WOWLAN_TRIG_4WAY_HANDSHAKE = 8,\n\tNL80211_WOWLAN_TRIG_RFKILL_RELEASE = 9,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_80211 = 10,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_80211_LEN = 11,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_8023 = 12,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_8023_LEN = 13,\n\tNL80211_WOWLAN_TRIG_TCP_CONNECTION = 14,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_MATCH = 15,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_CONNLOST = 16,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_NOMORETOKENS = 17,\n\tNL80211_WOWLAN_TRIG_NET_DETECT = 18,\n\tNL80211_WOWLAN_TRIG_NET_DETECT_RESULTS = 19,\n\tNL80211_WOWLAN_TRIG_UNPROTECTED_DEAUTH_DISASSOC = 20,\n\tNUM_NL80211_WOWLAN_TRIG = 21,\n\tMAX_NL80211_WOWLAN_TRIG = 20,\n};\n\nenum nl80211_wpa_versions {\n\tNL80211_WPA_VERSION_1 = 1,\n\tNL80211_WPA_VERSION_2 = 2,\n\tNL80211_WPA_VERSION_3 = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum nmi_states {\n\tNMI_NOT_RUNNING = 0,\n\tNMI_EXECUTING = 1,\n\tNMI_LATCHED = 2,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_IOMMU_PAGES = 39,\n\tNR_SWAPCACHE = 40,\n\tPGPROMOTE_SUCCESS = 41,\n\tPGPROMOTE_CANDIDATE = 42,\n\tPGPROMOTE_CANDIDATE_NRL = 43,\n\tPGDEMOTE_KSWAPD = 44,\n\tPGDEMOTE_DIRECT = 45,\n\tPGDEMOTE_KHUGEPAGED = 46,\n\tPGDEMOTE_PROACTIVE = 47,\n\tNR_HUGETLB = 48,\n\tNR_BALLOON_PAGES = 49,\n\tNR_KERNEL_FILE_PAGES = 50,\n\tNR_VM_NODE_STAT_ITEMS = 51,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 2,\n\tN_MEMORY = 3,\n\tN_CPU = 4,\n\tN_GENERIC_INITIATOR = 5,\n\tNR_NODE_STATES = 6,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum numa_faults_stats {\n\tNUMA_MEM = 0,\n\tNUMA_CPU = 1,\n\tNUMA_MEMBUF = 2,\n\tNUMA_CPUBUF = 3,\n};\n\nenum numa_stat_item {\n\tNUMA_HIT = 0,\n\tNUMA_MISS = 1,\n\tNUMA_FOREIGN = 2,\n\tNUMA_INTERLEAVE_HIT = 3,\n\tNUMA_LOCAL = 4,\n\tNUMA_OTHER = 5,\n\tNR_VM_NUMA_EVENT_ITEMS = 6,\n};\n\nenum numa_topology_type {\n\tNUMA_DIRECT = 0,\n\tNUMA_GLUELESS_MESH = 1,\n\tNUMA_BACKPLANE = 2,\n};\n\nenum numa_type {\n\tnode_has_spare = 0,\n\tnode_fully_busy = 1,\n\tnode_overloaded = 2,\n};\n\nenum numa_vmaskip_reason {\n\tNUMAB_SKIP_UNSUITABLE = 0,\n\tNUMAB_SKIP_SHARED_RO = 1,\n\tNUMAB_SKIP_INACCESSIBLE = 2,\n\tNUMAB_SKIP_SCAN_DELAY = 3,\n\tNUMAB_SKIP_PID_INACTIVE = 4,\n\tNUMAB_SKIP_IGNORE_PID = 5,\n\tNUMAB_SKIP_SEQ_COMPLETED = 6,\n};\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n\tNVMEM_TYPE_FRAM = 4,\n};\n\nenum oa_type {\n\tTYPE_OAG = 0,\n\tTYPE_OAM = 1,\n};\n\nenum oatc14_hdd_status {\n\tOATC14_HDD_STATUS_CABLE_OK = 0,\n\tOATC14_HDD_STATUS_OPEN = 1,\n\tOATC14_HDD_STATUS_SHORT = 2,\n\tOATC14_HDD_STATUS_NOT_DETECTABLE = 3,\n};\n\nenum ocb_deferred_task_flags {\n\tOCB_WORK_HOUSEKEEPING = 0,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum ohci_rh_state {\n\tOHCI_RH_HALTED = 0,\n\tOHCI_RH_SUSPENDED = 1,\n\tOHCI_RH_RUNNING = 2,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum open_claim_type4 {\n\tNFS4_OPEN_CLAIM_NULL = 0,\n\tNFS4_OPEN_CLAIM_PREVIOUS = 1,\n\tNFS4_OPEN_CLAIM_DELEGATE_CUR = 2,\n\tNFS4_OPEN_CLAIM_DELEGATE_PREV = 3,\n\tNFS4_OPEN_CLAIM_FH = 4,\n\tNFS4_OPEN_CLAIM_DELEG_CUR_FH = 5,\n\tNFS4_OPEN_CLAIM_DELEG_PREV_FH = 6,\n};\n\nenum opentype4 {\n\tNFS4_OPEN_NOCREATE = 0,\n\tNFS4_OPEN_CREATE = 1,\n};\n\nenum operation_mode {\n\tDP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0,\n\tDP_AS_SDP_AVT_FIXED_VTOTAL = 1,\n\tDP_AS_SDP_FAVT_TRR_NOT_REACHED = 2,\n\tDP_AS_SDP_FAVT_TRR_REACHED = 3,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum p9_cache_bits {\n\tCACHE_NONE = 0,\n\tCACHE_FILE = 1,\n\tCACHE_META = 2,\n\tCACHE_WRITEBACK = 4,\n\tCACHE_LOOSE = 8,\n\tCACHE_FSCACHE = 128,\n};\n\nenum p9_cache_shortcuts {\n\tCACHE_SC_NONE = 0,\n\tCACHE_SC_READAHEAD = 1,\n\tCACHE_SC_MMAP = 5,\n\tCACHE_SC_LOOSE = 15,\n\tCACHE_SC_FSCACHE = 143,\n};\n\nenum p9_fid_reftype {\n\tP9_FID_REF_CREATE = 0,\n\tP9_FID_REF_GET = 1,\n\tP9_FID_REF_PUT = 2,\n\tP9_FID_REF_DESTROY = 3,\n} __attribute__((mode(byte)));\n\nenum p9_msg_t {\n\tP9_TLERROR = 6,\n\tP9_RLERROR = 7,\n\tP9_TSTATFS = 8,\n\tP9_RSTATFS = 9,\n\tP9_TLOPEN = 12,\n\tP9_RLOPEN = 13,\n\tP9_TLCREATE = 14,\n\tP9_RLCREATE = 15,\n\tP9_TSYMLINK = 16,\n\tP9_RSYMLINK = 17,\n\tP9_TMKNOD = 18,\n\tP9_RMKNOD = 19,\n\tP9_TRENAME = 20,\n\tP9_RRENAME = 21,\n\tP9_TREADLINK = 22,\n\tP9_RREADLINK = 23,\n\tP9_TGETATTR = 24,\n\tP9_RGETATTR = 25,\n\tP9_TSETATTR = 26,\n\tP9_RSETATTR = 27,\n\tP9_TXATTRWALK = 30,\n\tP9_RXATTRWALK = 31,\n\tP9_TXATTRCREATE = 32,\n\tP9_RXATTRCREATE = 33,\n\tP9_TREADDIR = 40,\n\tP9_RREADDIR = 41,\n\tP9_TFSYNC = 50,\n\tP9_RFSYNC = 51,\n\tP9_TLOCK = 52,\n\tP9_RLOCK = 53,\n\tP9_TGETLOCK = 54,\n\tP9_RGETLOCK = 55,\n\tP9_TLINK = 70,\n\tP9_RLINK = 71,\n\tP9_TMKDIR = 72,\n\tP9_RMKDIR = 73,\n\tP9_TRENAMEAT = 74,\n\tP9_RRENAMEAT = 75,\n\tP9_TUNLINKAT = 76,\n\tP9_RUNLINKAT = 77,\n\tP9_TVERSION = 100,\n\tP9_RVERSION = 101,\n\tP9_TAUTH = 102,\n\tP9_RAUTH = 103,\n\tP9_TATTACH = 104,\n\tP9_RATTACH = 105,\n\tP9_TERROR = 106,\n\tP9_RERROR = 107,\n\tP9_TFLUSH = 108,\n\tP9_RFLUSH = 109,\n\tP9_TWALK = 110,\n\tP9_RWALK = 111,\n\tP9_TOPEN = 112,\n\tP9_ROPEN = 113,\n\tP9_TCREATE = 114,\n\tP9_RCREATE = 115,\n\tP9_TREAD = 116,\n\tP9_RREAD = 117,\n\tP9_TWRITE = 118,\n\tP9_RWRITE = 119,\n\tP9_TCLUNK = 120,\n\tP9_RCLUNK = 121,\n\tP9_TREMOVE = 122,\n\tP9_RREMOVE = 123,\n\tP9_TSTAT = 124,\n\tP9_RSTAT = 125,\n\tP9_TWSTAT = 126,\n\tP9_RWSTAT = 127,\n};\n\nenum p9_open_mode_t {\n\tP9_OREAD = 0,\n\tP9_OWRITE = 1,\n\tP9_ORDWR = 2,\n\tP9_OEXEC = 3,\n\tP9_OTRUNC = 16,\n\tP9_OREXEC = 32,\n\tP9_ORCLOSE = 64,\n\tP9_OAPPEND = 128,\n\tP9_OEXCL = 4096,\n\tP9L_MODE_MASK = 8191,\n\tP9L_DIRECT = 8192,\n\tP9L_NOWRITECACHE = 16384,\n\tP9L_LOOSE = 32768,\n};\n\nenum p9_perm_t {\n\tP9_DMDIR = 2147483648,\n\tP9_DMAPPEND = 1073741824,\n\tP9_DMEXCL = 536870912,\n\tP9_DMMOUNT = 268435456,\n\tP9_DMAUTH = 134217728,\n\tP9_DMTMP = 67108864,\n\tP9_DMSYMLINK = 33554432,\n\tP9_DMLINK = 16777216,\n\tP9_DMDEVICE = 8388608,\n\tP9_DMNAMEDPIPE = 2097152,\n\tP9_DMSOCKET = 1048576,\n\tP9_DMSETUID = 524288,\n\tP9_DMSETGID = 262144,\n\tP9_DMSETVTX = 65536,\n};\n\nenum p9_proto_versions {\n\tp9_proto_legacy = 0,\n\tp9_proto_2000u = 1,\n\tp9_proto_2000L = 2,\n};\n\nenum p9_req_status_t {\n\tREQ_STATUS_ALLOC = 0,\n\tREQ_STATUS_UNSENT = 1,\n\tREQ_STATUS_SENT = 2,\n\tREQ_STATUS_RCVD = 3,\n\tREQ_STATUS_FLSHD = 4,\n\tREQ_STATUS_ERROR = 5,\n};\n\nenum p9_session_flags {\n\tV9FS_PROTO_2000U = 1,\n\tV9FS_PROTO_2000L = 2,\n\tV9FS_ACCESS_SINGLE = 4,\n\tV9FS_ACCESS_USER = 8,\n\tV9FS_ACCESS_CLIENT = 16,\n\tV9FS_POSIX_ACL = 32,\n\tV9FS_NO_XATTR = 64,\n\tV9FS_IGNORE_QV = 128,\n\tV9FS_DIRECT_IO = 256,\n\tV9FS_SYNC = 512,\n};\n\nenum p9_trans_status {\n\tConnected = 0,\n\tBeginDisconnect = 1,\n\tDisconnected = 2,\n\tHung = 3,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum page_cache_mode {\n\t_PAGE_CACHE_MODE_WB = 0,\n\t_PAGE_CACHE_MODE_WC = 1,\n\t_PAGE_CACHE_MODE_UC_MINUS = 2,\n\t_PAGE_CACHE_MODE_UC = 3,\n\t_PAGE_CACHE_MODE_WT = 4,\n\t_PAGE_CACHE_MODE_WP = 5,\n\t_PAGE_CACHE_MODE_NUM = 8,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 4096,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\t__NR_PAGEBLOCK_BITS = 4,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\tPG_arch_2 = 21,\n\t__NR_PAGEFLAGS = 22,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum panel_type {\n\tPANEL_TYPE_OPREGION = 0,\n\tPANEL_TYPE_VBT = 1,\n\tPANEL_TYPE_PNPID = 2,\n\tPANEL_TYPE_FALLBACK = 3,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_bf_sort_state {\n\tpci_bf_sort_default = 0,\n\tpci_force_nobf = 1,\n\tpci_force_bf = 2,\n\tpci_dmi_bf = 3,\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_15625000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_oxsemi = 71,\n\tpbn_oxsemi_1_15625000 = 72,\n\tpbn_oxsemi_2_15625000 = 73,\n\tpbn_oxsemi_4_15625000 = 74,\n\tpbn_oxsemi_8_15625000 = 75,\n\tpbn_intel_i960 = 76,\n\tpbn_sgi_ioc3 = 77,\n\tpbn_computone_4 = 78,\n\tpbn_computone_6 = 79,\n\tpbn_computone_8 = 80,\n\tpbn_sbsxrsio = 81,\n\tpbn_pasemi_1682M = 82,\n\tpbn_ni8430_2 = 83,\n\tpbn_ni8430_4 = 84,\n\tpbn_ni8430_8 = 85,\n\tpbn_ni8430_16 = 86,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 87,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 90,\n\tpbn_ce4100_1_115200 = 91,\n\tpbn_omegapci = 92,\n\tpbn_NETMOS9900_2s_115200 = 93,\n\tpbn_brcm_trumanage = 94,\n\tpbn_fintek_4 = 95,\n\tpbn_fintek_8 = 96,\n\tpbn_fintek_12 = 97,\n\tpbn_fintek_F81504A = 98,\n\tpbn_fintek_F81508A = 99,\n\tpbn_fintek_F81512A = 100,\n\tpbn_wch382_2 = 101,\n\tpbn_wch384_4 = 102,\n\tpbn_wch384_8 = 103,\n\tpbn_sunix_pci_1s = 104,\n\tpbn_sunix_pci_2s = 105,\n\tpbn_sunix_pci_4s = 106,\n\tpbn_sunix_pci_8s = 107,\n\tpbn_sunix_pci_16s = 108,\n\tpbn_titan_1_4000000 = 109,\n\tpbn_titan_2_4000000 = 110,\n\tpbn_titan_4_4000000 = 111,\n\tpbn_titan_8_4000000 = 112,\n\tpbn_moxa_2 = 113,\n\tpbn_moxa_4 = 114,\n\tpbn_moxa_8 = 115,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_dev_reg_1 {\n\tPCI_Y2_PIG_ENA = -2147483648,\n\tPCI_Y2_DLL_DIS = 1073741824,\n\tPCI_SW_PWR_ON_RST = 1073741824,\n\tPCI_Y2_PHY2_COMA = 536870912,\n\tPCI_Y2_PHY1_COMA = 268435456,\n\tPCI_Y2_PHY2_POWD = 134217728,\n\tPCI_Y2_PHY1_POWD = 67108864,\n\tPCI_Y2_PME_LEGACY = 32768,\n\tPCI_PHY_LNK_TIM_MSK = 768,\n\tPCI_ENA_L1_EVENT = 128,\n\tPCI_ENA_GPHY_LNK = 64,\n\tPCI_FORCE_PEX_L1 = 32,\n};\n\nenum pci_dev_reg_2 {\n\tPCI_VPD_WR_THR = 4278190080,\n\tPCI_DEV_SEL = 16646144,\n\tPCI_VPD_ROM_SZ = 114688,\n\tPCI_PATCH_DIR = 3840,\n\tPCI_EXT_PATCHS = 240,\n\tPCI_EN_DUMMY_RD = 8,\n\tPCI_REV_DESC = 4,\n\tPCI_USEDATA64 = 1,\n};\n\nenum pci_dev_reg_3 {\n\tP_CLK_ASF_REGS_DIS = 262144,\n\tP_CLK_COR_REGS_D0_DIS = 131072,\n\tP_CLK_MACSEC_DIS = 131072,\n\tP_CLK_PCI_REGS_D0_DIS = 65536,\n\tP_CLK_COR_YTB_ARB_DIS = 32768,\n\tP_CLK_MAC_LNK1_D3_DIS = 16384,\n\tP_CLK_COR_LNK1_D0_DIS = 8192,\n\tP_CLK_MAC_LNK1_D0_DIS = 4096,\n\tP_CLK_COR_LNK1_D3_DIS = 2048,\n\tP_CLK_PCI_MST_ARB_DIS = 1024,\n\tP_CLK_COR_REGS_D3_DIS = 512,\n\tP_CLK_PCI_REGS_D3_DIS = 256,\n\tP_CLK_REF_LNK1_GM_DIS = 128,\n\tP_CLK_COR_LNK1_GM_DIS = 64,\n\tP_CLK_PCI_COMMON_DIS = 32,\n\tP_CLK_COR_COMMON_DIS = 16,\n\tP_CLK_PCI_LNK1_BMU_DIS = 8,\n\tP_CLK_COR_LNK1_BMU_DIS = 4,\n\tP_CLK_PCI_LNK1_BIU_DIS = 2,\n\tP_CLK_COR_LNK1_BIU_DIS = 1,\n\tPCIE_OUR3_WOL_D3_COLD_SET = 406548,\n};\n\nenum pci_dev_reg_4 {\n\tP_PEX_LTSSM_STAT_MSK = 4261412864,\n\tP_PEX_LTSSM_L1_STAT = 52,\n\tP_PEX_LTSSM_DET_STAT = 1,\n\tP_TIMER_VALUE_MSK = 16711680,\n\tP_FORCE_ASPM_REQUEST = 32768,\n\tP_ASPM_GPHY_LINK_DOWN = 16384,\n\tP_ASPM_INT_FIFO_EMPTY = 8192,\n\tP_ASPM_CLKRUN_REQUEST = 4096,\n\tP_ASPM_FORCE_CLKREQ_ENA = 16,\n\tP_ASPM_CLKREQ_PAD_CTL = 8,\n\tP_ASPM_A1_MODE_SELECT = 4,\n\tP_CLK_GATE_PEX_UNIT_ENA = 2,\n\tP_CLK_GATE_ROOT_COR_ENA = 1,\n\tP_ASPM_CONTROL_MSK = 61440,\n};\n\nenum pci_dev_reg_5 {\n\tP_CTL_DIV_CORE_CLK_ENA = -2147483648,\n\tP_CTL_SRESET_VMAIN_AV = 1073741824,\n\tP_CTL_BYPASS_VMAIN_AV = 536870912,\n\tP_CTL_TIM_VMAIN_AV_MSK = 402653184,\n\tP_REL_PCIE_RST_DE_ASS = 67108864,\n\tP_REL_GPHY_REC_PACKET = 33554432,\n\tP_REL_INT_FIFO_N_EMPTY = 16777216,\n\tP_REL_MAIN_PWR_AVAIL = 8388608,\n\tP_REL_CLKRUN_REQ_REL = 4194304,\n\tP_REL_PCIE_RESET_ASS = 2097152,\n\tP_REL_PME_ASSERTED = 1048576,\n\tP_REL_PCIE_EXIT_L1_ST = 524288,\n\tP_REL_LOADER_NOT_FIN = 262144,\n\tP_REL_PCIE_RX_EX_IDLE = 131072,\n\tP_REL_GPHY_LINK_UP = 65536,\n\tP_GAT_PCIE_RST_ASSERTED = 1024,\n\tP_GAT_GPHY_N_REC_PACKET = 512,\n\tP_GAT_INT_FIFO_EMPTY = 256,\n\tP_GAT_MAIN_PWR_N_AVAIL = 128,\n\tP_GAT_CLKRUN_REQ_REL = 64,\n\tP_GAT_PCIE_RESET_ASS = 32,\n\tP_GAT_PME_DE_ASSERTED = 16,\n\tP_GAT_PCIE_ENTER_L1_ST = 8,\n\tP_GAT_LOADER_FINISHED = 4,\n\tP_GAT_PCIE_RX_EL_IDLE = 2,\n\tP_GAT_GPHY_LINK_DOWN = 1,\n\tPCIE_OUR5_EVENT_CLK_D3_SET = 50987786,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_hotplug_event {\n\tPCI_HOTPLUG_LINK_UP = 0,\n\tPCI_HOTPLUG_LINK_DOWN = 1,\n\tPCI_HOTPLUG_CARD_PRESENT = 2,\n\tPCI_HOTPLUG_CARD_NOT_PRESENT = 3,\n};\n\nenum pci_irq_reroute_variant {\n\tINTEL_IRQ_REROUTE_VARIANT = 1,\n\tMAX_IRQ_REROUTE_VARIANTS = 3,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum pedit_cmd {\n\tTCA_PEDIT_KEY_EX_CMD_SET = 0,\n\tTCA_PEDIT_KEY_EX_CMD_ADD = 1,\n\t__PEDIT_CMD_MAX = 2,\n};\n\nenum pedit_header_type {\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK = 0,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_ETH = 1,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP4 = 2,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP6 = 3,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_TCP = 4,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_UDP = 5,\n\t__PEDIT_HDR_TYPE_MAX = 6,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nenum perf_adl_uncore_imc_freerunning_types {\n\tADL_MMIO_UNCORE_IMC_DATA_TOTAL = 0,\n\tADL_MMIO_UNCORE_IMC_DATA_READ = 1,\n\tADL_MMIO_UNCORE_IMC_DATA_WRITE = 2,\n\tADL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE = 262144,\n\tPERF_SAMPLE_BRANCH_COUNTERS = 524288,\n\tPERF_SAMPLE_BRANCH_MAX = 1048576,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 18446744073709551584ULL,\n\tPERF_CONTEXT_KERNEL = 18446744073709551488ULL,\n\tPERF_CONTEXT_USER = 18446744073709551104ULL,\n\tPERF_CONTEXT_USER_DEFERRED = 18446744073709550976ULL,\n\tPERF_CONTEXT_GUEST = 18446744073709549568ULL,\n\tPERF_CONTEXT_GUEST_KERNEL = 18446744073709549440ULL,\n\tPERF_CONTEXT_GUEST_USER = 18446744073709549056ULL,\n\tPERF_CONTEXT_MAX = 18446744073709547521ULL,\n};\n\nenum perf_cstate_core_events {\n\tPERF_CSTATE_CORE_C1_RES = 0,\n\tPERF_CSTATE_CORE_C3_RES = 1,\n\tPERF_CSTATE_CORE_C6_RES = 2,\n\tPERF_CSTATE_CORE_C7_RES = 3,\n\tPERF_CSTATE_CORE_EVENT_MAX = 4,\n};\n\nenum perf_cstate_module_events {\n\tPERF_CSTATE_MODULE_C6_RES = 0,\n\tPERF_CSTATE_MODULE_EVENT_MAX = 1,\n};\n\nenum perf_cstate_pkg_events {\n\tPERF_CSTATE_PKG_C2_RES = 0,\n\tPERF_CSTATE_PKG_C3_RES = 1,\n\tPERF_CSTATE_PKG_C6_RES = 2,\n\tPERF_CSTATE_PKG_C7_RES = 3,\n\tPERF_CSTATE_PKG_C8_RES = 4,\n\tPERF_CSTATE_PKG_C9_RES = 5,\n\tPERF_CSTATE_PKG_C10_RES = 6,\n\tPERF_CSTATE_PKG_EVENT_MAX = 7,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_LOST = 16,\n\tPERF_FORMAT_MAX = 32,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_DATA_PAGE_SIZE = 4194304,\n\tPERF_SAMPLE_CODE_PAGE_SIZE = 8388608,\n\tPERF_SAMPLE_WEIGHT_STRUCT = 16777216,\n\tPERF_SAMPLE_MAX = 33554432,\n};\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = -5,\n\tPERF_EVENT_STATE_REVOKED = -4,\n\tPERF_EVENT_STATE_EXIT = -3,\n\tPERF_EVENT_STATE_ERROR = -2,\n\tPERF_EVENT_STATE_OFF = -1,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = -1,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_TEXT_POKE = 20,\n\tPERF_RECORD_AUX_OUTPUT_HW_ID = 21,\n\tPERF_RECORD_CALLCHAIN_DEFERRED = 22,\n\tPERF_RECORD_MAX = 23,\n};\n\nenum perf_event_x86_regs {\n\tPERF_REG_X86_AX = 0,\n\tPERF_REG_X86_BX = 1,\n\tPERF_REG_X86_CX = 2,\n\tPERF_REG_X86_DX = 3,\n\tPERF_REG_X86_SI = 4,\n\tPERF_REG_X86_DI = 5,\n\tPERF_REG_X86_BP = 6,\n\tPERF_REG_X86_SP = 7,\n\tPERF_REG_X86_IP = 8,\n\tPERF_REG_X86_FLAGS = 9,\n\tPERF_REG_X86_CS = 10,\n\tPERF_REG_X86_SS = 11,\n\tPERF_REG_X86_DS = 12,\n\tPERF_REG_X86_ES = 13,\n\tPERF_REG_X86_FS = 14,\n\tPERF_REG_X86_GS = 15,\n\tPERF_REG_X86_R8 = 16,\n\tPERF_REG_X86_R9 = 17,\n\tPERF_REG_X86_R10 = 18,\n\tPERF_REG_X86_R11 = 19,\n\tPERF_REG_X86_R12 = 20,\n\tPERF_REG_X86_R13 = 21,\n\tPERF_REG_X86_R14 = 22,\n\tPERF_REG_X86_R15 = 23,\n\tPERF_REG_X86_32_MAX = 16,\n\tPERF_REG_X86_64_MAX = 24,\n\tPERF_REG_X86_XMM0 = 32,\n\tPERF_REG_X86_XMM1 = 34,\n\tPERF_REG_X86_XMM2 = 36,\n\tPERF_REG_X86_XMM3 = 38,\n\tPERF_REG_X86_XMM4 = 40,\n\tPERF_REG_X86_XMM5 = 42,\n\tPERF_REG_X86_XMM6 = 44,\n\tPERF_REG_X86_XMM7 = 46,\n\tPERF_REG_X86_XMM8 = 48,\n\tPERF_REG_X86_XMM9 = 50,\n\tPERF_REG_X86_XMM10 = 52,\n\tPERF_REG_X86_XMM11 = 54,\n\tPERF_REG_X86_XMM12 = 56,\n\tPERF_REG_X86_XMM13 = 58,\n\tPERF_REG_X86_XMM14 = 60,\n\tPERF_REG_X86_XMM15 = 62,\n\tPERF_REG_X86_XMM_MAX = 64,\n};\n\nenum perf_hw_cache_id {\n\tPERF_COUNT_HW_CACHE_L1D = 0,\n\tPERF_COUNT_HW_CACHE_L1I = 1,\n\tPERF_COUNT_HW_CACHE_LL = 2,\n\tPERF_COUNT_HW_CACHE_DTLB = 3,\n\tPERF_COUNT_HW_CACHE_ITLB = 4,\n\tPERF_COUNT_HW_CACHE_BPU = 5,\n\tPERF_COUNT_HW_CACHE_NODE = 6,\n\tPERF_COUNT_HW_CACHE_MAX = 7,\n};\n\nenum perf_hw_cache_op_id {\n\tPERF_COUNT_HW_CACHE_OP_READ = 0,\n\tPERF_COUNT_HW_CACHE_OP_WRITE = 1,\n\tPERF_COUNT_HW_CACHE_OP_PREFETCH = 2,\n\tPERF_COUNT_HW_CACHE_OP_MAX = 3,\n};\n\nenum perf_hw_cache_op_result_id {\n\tPERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,\n\tPERF_COUNT_HW_CACHE_RESULT_MISS = 1,\n\tPERF_COUNT_HW_CACHE_RESULT_MAX = 2,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_msr_id {\n\tPERF_MSR_TSC = 0,\n\tPERF_MSR_APERF = 1,\n\tPERF_MSR_MPERF = 2,\n\tPERF_MSR_PPERF = 3,\n\tPERF_MSR_SMI = 4,\n\tPERF_MSR_PTSC = 5,\n\tPERF_MSR_IRPERF = 6,\n\tPERF_MSR_THERM = 7,\n\tPERF_MSR_EVENT_MAX = 8,\n};\n\nenum perf_pmu_scope {\n\tPERF_PMU_SCOPE_NONE = 0,\n\tPERF_PMU_SCOPE_CORE = 1,\n\tPERF_PMU_SCOPE_DIE = 2,\n\tPERF_PMU_SCOPE_CLUSTER = 3,\n\tPERF_PMU_SCOPE_PKG = 4,\n\tPERF_PMU_SCOPE_SYS_WIDE = 5,\n\tPERF_PMU_MAX_SCOPE = 6,\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum perf_rapl_pkg_events {\n\tPERF_RAPL_PP0 = 0,\n\tPERF_RAPL_PKG = 1,\n\tPERF_RAPL_RAM = 2,\n\tPERF_RAPL_PP1 = 3,\n\tPERF_RAPL_PSYS = 4,\n\tPERF_RAPL_PKG_EVENTS_MAX = 5,\n\tNR_RAPL_PKG_DOMAINS = 5,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nenum perf_snb_uncore_imc_freerunning_types {\n\tSNB_PCI_UNCORE_IMC_DATA_READS = 0,\n\tSNB_PCI_UNCORE_IMC_DATA_WRITES = 1,\n\tSNB_PCI_UNCORE_IMC_GT_REQUESTS = 2,\n\tSNB_PCI_UNCORE_IMC_IA_REQUESTS = 3,\n\tSNB_PCI_UNCORE_IMC_IO_REQUESTS = 4,\n\tSNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX = 5,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum perf_tgl_uncore_imc_freerunning_types {\n\tTGL_MMIO_UNCORE_IMC_DATA_TOTAL = 0,\n\tTGL_MMIO_UNCORE_IMC_DATA_READ = 1,\n\tTGL_MMIO_UNCORE_IMC_DATA_WRITE = 2,\n\tTGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum perf_uncore_dmr_iio_freerunning_type_id {\n\tDMR_ITC_INB_DATA_BW = 0,\n\tDMR_ITC_BW_IN = 1,\n\tDMR_OTC_BW_OUT = 2,\n\tDMR_OTC_CLOCK_TICKS = 3,\n\tDMR_IIO_FREERUNNING_TYPE_MAX = 4,\n};\n\nenum perf_uncore_icx_iio_freerunning_type_id {\n\tICX_IIO_MSR_IOCLK = 0,\n\tICX_IIO_MSR_BW_IN = 1,\n\tICX_IIO_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum perf_uncore_icx_imc_freerunning_type_id {\n\tICX_IMC_DCLK = 0,\n\tICX_IMC_DDR = 1,\n\tICX_IMC_DDRT = 2,\n\tICX_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_uncore_iio_freerunning_type_id {\n\tSKX_IIO_MSR_IOCLK = 0,\n\tSKX_IIO_MSR_BW = 1,\n\tSKX_IIO_MSR_UTIL = 2,\n\tSKX_IIO_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_uncore_snr_iio_freerunning_type_id {\n\tSNR_IIO_MSR_IOCLK = 0,\n\tSNR_IIO_MSR_BW_IN = 1,\n\tSNR_IIO_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum perf_uncore_snr_imc_freerunning_type_id {\n\tSNR_IMC_DCLK = 0,\n\tSNR_IMC_DDR = 1,\n\tSNR_IMC_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum perf_uncore_spr_iio_freerunning_type_id {\n\tSPR_IIO_MSR_IOCLK = 0,\n\tSPR_IIO_MSR_BW_IN = 1,\n\tSPR_IIO_MSR_BW_OUT = 2,\n\tSPR_IIO_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum perf_uncore_spr_imc_freerunning_type_id {\n\tSPR_IMC_DCLK = 0,\n\tSPR_IMC_PQ_CYCLES = 1,\n\tSPR_IMC_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum pg_level {\n\tPG_LEVEL_NONE = 0,\n\tPG_LEVEL_4K = 1,\n\tPG_LEVEL_2M = 2,\n\tPG_LEVEL_1G = 3,\n\tPG_LEVEL_512G = 4,\n\tPG_LEVEL_256T = 5,\n\tPG_LEVEL_NUM = 6,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum phy {\n\tphy_100a = 992,\n\tphy_100c = 55575208,\n\tphy_82555_tx = 22020776,\n\tphy_nsc_tx = 1543512064,\n\tphy_82562_et = 53478056,\n\tphy_82562_em = 52429480,\n\tphy_82562_ek = 51380904,\n\tphy_82562_eh = 24117928,\n\tphy_82552_v = 3496017997,\n\tphy_unknown = 4294967295,\n};\n\nenum phy___2 {\n\tPHY_NONE = -1,\n\tPHY_A = 0,\n\tPHY_B = 1,\n\tPHY_C = 2,\n\tPHY_D = 3,\n\tPHY_E = 4,\n\tPHY_F = 5,\n\tPHY_G = 6,\n\tPHY_H = 7,\n\tPHY_I = 8,\n\tI915_MAX_PHYS = 9,\n};\n\nenum phy_fia {\n\tFIA1 = 0,\n\tFIA2 = 1,\n\tFIA3 = 2,\n};\n\nenum phy_media {\n\tPHY_MEDIA_DEFAULT = 0,\n\tPHY_MEDIA_SR = 1,\n\tPHY_MEDIA_DAC = 2,\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n\tPHY_MODE_HDMI = 20,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_port_parent {\n\tPHY_PORT_PHY = 0,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_state_work {\n\tPHY_STATE_WORK_NONE = 0,\n\tPHY_STATE_WORK_ANEG = 1,\n\tPHY_STATE_WORK_SUSPEND = 2,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_ufs_state {\n\tPHY_UFS_HIBERN8_ENTER = 0,\n\tPHY_UFS_HIBERN8_EXIT = 1,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum pid_axes {\n\tPID_AXIS_X = 0,\n\tPID_AXIS_Y = 1,\n\tPID_AXIS_Z = 2,\n\tPID_AXIS_RX = 3,\n\tPID_AXIS_RY = 4,\n\tPID_AXIS_RZ = 5,\n\tPID_AXIS_SLIDER = 6,\n\tPID_AXIS_DIAL = 7,\n\tPID_AXIS_WHEEL = 8,\n\tPID_AXES_COUNT = 9,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidcg_event {\n\tPIDCG_MAX = 0,\n\tPIDCG_FORKFAIL = 1,\n\tNR_PIDCG_EVENTS = 2,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum piix_controller_ids {\n\tpiix_pata_mwdma = 0,\n\tpiix_pata_33 = 1,\n\tich_pata_33 = 2,\n\tich_pata_66 = 3,\n\tich_pata_100 = 4,\n\tich_pata_100_nomwdma1 = 5,\n\tich5_sata = 6,\n\tich6_sata = 7,\n\tich6m_sata = 8,\n\tich8_sata = 9,\n\tich8_2port_sata = 10,\n\tich8m_apple_sata = 11,\n\ttolapai_sata = 12,\n\tpiix_pata_vmw = 13,\n\tich8_sata_snb = 14,\n\tich8_2port_sata_snb = 15,\n\tich8_2port_sata_byt = 16,\n};\n\nenum pinctrl_map_type {\n\tPIN_MAP_TYPE_INVALID = 0,\n\tPIN_MAP_TYPE_DUMMY_STATE = 1,\n\tPIN_MAP_TYPE_MUX_GROUP = 2,\n\tPIN_MAP_TYPE_CONFIGS_PIN = 3,\n\tPIN_MAP_TYPE_CONFIGS_GROUP = 4,\n};\n\nenum pipe {\n\tINVALID_PIPE = -1,\n\tPIPE_A = 0,\n\tPIPE_B = 1,\n\tPIPE_C = 2,\n\tPIPE_D = 3,\n\t_PIPE_EDP = 4,\n\tI915_MAX_PIPES = 4,\n};\n\nenum pipedmc_event_id {\n\tPIPEDMC_EVENT_TMR0_DONE = 20,\n\tPIPEDMC_EVENT_TMR1_DONE = 21,\n\tPIPEDMC_EVENT_TMR2_DONE = 22,\n\tPIPEDMC_EVENT_COUNT0_DONE = 23,\n\tPIPEDMC_EVENT_COUNT1_DONE = 24,\n\tPIPEDMC_EVENT_PGA_PGB_RESTORE_DONE = 25,\n\tPIPEDMC_EVENT_PG1_PG2_RESTORE_DONE = 26,\n\tPIPEDMC_EVENT_PGA_PGB_SAVE_DONE = 27,\n\tPIPEDMC_EVENT_PG1_PG2_SAVE_DONE = 28,\n\tPIPEDMC_EVENT_FULL_FQ_WAKE_TRIGGER = 43,\n\tPIPEDMC_EVENT_1KHZ_FQ_TRIGGER = 44,\n\tPIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER = 45,\n\tPIPEDMC_EVENT_SCANLINE_INRANGE = 46,\n\tPIPEDMC_EVENT_SCANLINE_OUTRANGE = 47,\n\tPIPEDMC_EVENT_SCANLINE_EQUAL = 48,\n\tPIPEDMC_EVENT_DELAYED_VBLANK = 49,\n\tPIPEDMC_EVENT_VBLANK = 50,\n\tPIPEDMC_EVENT_HBLANK = 51,\n\tPIPEDMC_EVENT_VSYNC = 52,\n\tPIPEDMC_EVENT_SCANLINE_FROM_DMUX = 53,\n\tPIPEDMC_EVENT_PLANE1_FLIP = 54,\n\tPIPEDMC_EVENT_PLANE2_FLIP = 55,\n\tPIPEDMC_EVENT_PLANE3_FLIP = 56,\n\tPIPEDMC_EVENT_PLANE4_FLIP = 57,\n\tPIPEDMC_EVENT_PLANE5_FLIP = 58,\n\tPIPEDMC_EVENT_PLANE6_FLIP = 59,\n\tPIPEDMC_EVENT_PLANE7_FLIP = 60,\n\tPIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER = 61,\n\tPIPEDMC_EVENT_PLANE1_FLIP_DONE = 86,\n\tPIPEDMC_EVENT_PLANE2_FLIP_DONE = 87,\n\tPIPEDMC_EVENT_PLANE3_FLIP_DONE = 88,\n\tPIPEDMC_EVENT_PLANE4_FLIP_DONE = 89,\n\tPIPEDMC_EVENT_PLANE5_FLIP_DONE = 90,\n\tPIPEDMC_EVENT_PLANE6_FLIP_DONE = 91,\n\tPIPEDMC_EVENT_PLANE7_FLIP_DONE = 92,\n\tPIPEDMC_EVENT_GTT_ERR = 155,\n\tPIPEDMC_EVENT_IN_PSR = 181,\n\tPIPEDMC_EVENT_DSI_DMC_IDLE = 182,\n\tPIPEDMC_EVENT_PSR2_DMC_IDLE = 183,\n\tPIPEDMC_EVENT_IN_VGA = 184,\n\tPIPEDMC_EVENT_TRAP_HIT = 189,\n\tPIPEDMC_EVENT_CLK_USEC = 190,\n\tPIPEDMC_EVENT_CLK_MSEC = 191,\n\tPIPEDMC_EVENT_CHICKEN1 = 200,\n\tPIPEDMC_EVENT_CHICKEN2 = 201,\n\tPIPEDMC_EVENT_CHICKEN3 = 202,\n\tPIPEDMC_EVENT_DDT_UBP = 203,\n\tPIPEDMC_EVENT_LP_LATENCY = 206,\n\tPIPEDMC_EVENT_LACE_PART_A_HIST_TRIGGER = 223,\n\tPIPEDMC_EVENT_LACE_PART_B_HIST_TRIGGER = 224,\n\tPIPEDMC_EVENT_STACK_OVF = 252,\n\tPIPEDMC_EVENT_NO_CLAIM = 253,\n\tPIPEDMC_EVENT_UNK_CMD = 254,\n\tPIPEDMC_EVENT_HTP_MOD = 255,\n};\n\nenum pkcs7_actions {\n\tACT_pkcs7_check_content_type = 0,\n\tACT_pkcs7_extract_cert = 1,\n\tACT_pkcs7_note_OID = 2,\n\tACT_pkcs7_note_certificate_list = 3,\n\tACT_pkcs7_note_content = 4,\n\tACT_pkcs7_note_data = 5,\n\tACT_pkcs7_note_signed_info = 6,\n\tACT_pkcs7_note_signeddata_version = 7,\n\tACT_pkcs7_note_signerinfo_version = 8,\n\tACT_pkcs7_sig_note_authenticated_attr = 9,\n\tACT_pkcs7_sig_note_digest_algo = 10,\n\tACT_pkcs7_sig_note_issuer = 11,\n\tACT_pkcs7_sig_note_pkey_algo = 12,\n\tACT_pkcs7_sig_note_serial = 13,\n\tACT_pkcs7_sig_note_set_of_authattrs = 14,\n\tACT_pkcs7_sig_note_signature = 15,\n\tACT_pkcs7_sig_note_skid = 16,\n\tNR__pkcs7_actions = 17,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum plane_id {\n\tPLANE_1 = 0,\n\tPLANE_2 = 1,\n\tPLANE_3 = 2,\n\tPLANE_4 = 3,\n\tPLANE_5 = 4,\n\tPLANE_6 = 5,\n\tPLANE_7 = 6,\n\tPLANE_CURSOR = 7,\n\tI915_MAX_PLANES = 8,\n\tPLANE_PRIMARY = 0,\n\tPLANE_SPRITE0 = 1,\n\tPLANE_SPRITE1 = 2,\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = -1,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum pmc_type {\n\tKVM_PMC_GP = 0,\n\tKVM_PMC_FIXED = 1,\n};\n\nenum pnfs_block_extent_state {\n\tPNFS_BLOCK_READWRITE_DATA = 0,\n\tPNFS_BLOCK_READ_DATA = 1,\n\tPNFS_BLOCK_INVALID_DATA = 2,\n\tPNFS_BLOCK_NONE_DATA = 3,\n};\n\nenum pnfs_block_volume_type {\n\tPNFS_BLOCK_VOLUME_SIMPLE = 0,\n\tPNFS_BLOCK_VOLUME_SLICE = 1,\n\tPNFS_BLOCK_VOLUME_CONCAT = 2,\n\tPNFS_BLOCK_VOLUME_STRIPE = 3,\n\tPNFS_BLOCK_VOLUME_SCSI = 4,\n};\n\nenum pnfs_iomode {\n\tIOMODE_READ = 1,\n\tIOMODE_RW = 2,\n\tIOMODE_ANY = 3,\n};\n\nenum pnfs_layout_destroy_mode {\n\tPNFS_LAYOUT_INVALIDATE = 0,\n\tPNFS_LAYOUT_BULK_RETURN = 1,\n\tPNFS_LAYOUT_FILE_BULK_RETURN = 2,\n};\n\nenum pnfs_layoutreturn_type {\n\tRETURN_FILE = 1,\n\tRETURN_FSID = 2,\n\tRETURN_ALL = 3,\n};\n\nenum pnfs_layouttype {\n\tLAYOUT_NFSV4_1_FILES = 1,\n\tLAYOUT_OSD2_OBJECTS = 2,\n\tLAYOUT_BLOCK_VOLUME = 3,\n\tLAYOUT_FLEX_FILES = 4,\n\tLAYOUT_SCSI = 5,\n\tLAYOUT_TYPE_MAX = 6,\n};\n\nenum pnfs_notify_deviceid_type4 {\n\tNOTIFY_DEVICEID4_CHANGE = 2,\n\tNOTIFY_DEVICEID4_DELETE = 4,\n};\n\nenum pnfs_try_status {\n\tPNFS_ATTEMPTED = 0,\n\tPNFS_NOT_ATTEMPTED = 1,\n\tPNFS_TRY_AGAIN = 2,\n};\n\nenum pnfs_update_layout_reason {\n\tPNFS_UPDATE_LAYOUT_UNKNOWN = 0,\n\tPNFS_UPDATE_LAYOUT_NO_PNFS = 1,\n\tPNFS_UPDATE_LAYOUT_RD_ZEROLEN = 2,\n\tPNFS_UPDATE_LAYOUT_MDSTHRESH = 3,\n\tPNFS_UPDATE_LAYOUT_NOMEM = 4,\n\tPNFS_UPDATE_LAYOUT_BULK_RECALL = 5,\n\tPNFS_UPDATE_LAYOUT_IO_TEST_FAIL = 6,\n\tPNFS_UPDATE_LAYOUT_FOUND_CACHED = 7,\n\tPNFS_UPDATE_LAYOUT_RETURN = 8,\n\tPNFS_UPDATE_LAYOUT_RETRY = 9,\n\tPNFS_UPDATE_LAYOUT_BLOCKED = 10,\n\tPNFS_UPDATE_LAYOUT_INVALID_OPEN = 11,\n\tPNFS_UPDATE_LAYOUT_SEND_LAYOUTGET = 12,\n\tPNFS_UPDATE_LAYOUT_EXIT = 13,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port {\n\tPORT_NONE = -1,\n\tPORT_A = 0,\n\tPORT_B = 1,\n\tPORT_C = 2,\n\tPORT_D = 3,\n\tPORT_E = 4,\n\tPORT_F = 5,\n\tPORT_G = 6,\n\tPORT_H = 7,\n\tPORT_I = 8,\n\tPORT_TC1 = 3,\n\tPORT_TC2 = 4,\n\tPORT_TC3 = 5,\n\tPORT_TC4 = 6,\n\tPORT_TC5 = 7,\n\tPORT_TC6 = 8,\n\tPORT_D_XELPD = 7,\n\tPORT_E_XELPD = 8,\n\tI915_MAX_PORTS = 9,\n};\n\nenum port___2 {\n\tsoftware_reset = 0,\n\tselftest = 1,\n\tselective_reset = 2,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum power_supply_charge_behaviour {\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO = 0,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE = 1,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE_AWAKE = 2,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE = 3,\n};\n\nenum power_supply_charge_type {\n\tPOWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_CHARGE_TYPE_NONE = 1,\n\tPOWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2,\n\tPOWER_SUPPLY_CHARGE_TYPE_FAST = 3,\n\tPOWER_SUPPLY_CHARGE_TYPE_STANDARD = 4,\n\tPOWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5,\n\tPOWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6,\n\tPOWER_SUPPLY_CHARGE_TYPE_LONGLIFE = 7,\n\tPOWER_SUPPLY_CHARGE_TYPE_BYPASS = 8,\n};\n\nenum power_supply_notifier_events {\n\tPSY_EVENT_PROP_CHANGED = 0,\n};\n\nenum power_supply_property {\n\tPOWER_SUPPLY_PROP_STATUS = 0,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPE = 1,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPES = 2,\n\tPOWER_SUPPLY_PROP_HEALTH = 3,\n\tPOWER_SUPPLY_PROP_PRESENT = 4,\n\tPOWER_SUPPLY_PROP_ONLINE = 5,\n\tPOWER_SUPPLY_PROP_AUTHENTIC = 6,\n\tPOWER_SUPPLY_PROP_TECHNOLOGY = 7,\n\tPOWER_SUPPLY_PROP_CYCLE_COUNT = 8,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX = 9,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN = 10,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN = 11,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN = 12,\n\tPOWER_SUPPLY_PROP_VOLTAGE_NOW = 13,\n\tPOWER_SUPPLY_PROP_VOLTAGE_AVG = 14,\n\tPOWER_SUPPLY_PROP_VOLTAGE_OCV = 15,\n\tPOWER_SUPPLY_PROP_VOLTAGE_BOOT = 16,\n\tPOWER_SUPPLY_PROP_CURRENT_MAX = 17,\n\tPOWER_SUPPLY_PROP_CURRENT_NOW = 18,\n\tPOWER_SUPPLY_PROP_CURRENT_AVG = 19,\n\tPOWER_SUPPLY_PROP_CURRENT_BOOT = 20,\n\tPOWER_SUPPLY_PROP_POWER_NOW = 21,\n\tPOWER_SUPPLY_PROP_POWER_AVG = 22,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL_DESIGN = 23,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN = 24,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL = 25,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY = 26,\n\tPOWER_SUPPLY_PROP_CHARGE_NOW = 27,\n\tPOWER_SUPPLY_PROP_CHARGE_AVG = 28,\n\tPOWER_SUPPLY_PROP_CHARGE_COUNTER = 29,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT = 30,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX = 31,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE = 32,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX = 33,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT = 34,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX = 35,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD = 36,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD = 37,\n\tPOWER_SUPPLY_PROP_CHARGE_BEHAVIOUR = 38,\n\tPOWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT = 39,\n\tPOWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT = 40,\n\tPOWER_SUPPLY_PROP_INPUT_POWER_LIMIT = 41,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL_DESIGN = 42,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN = 43,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL = 44,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY = 45,\n\tPOWER_SUPPLY_PROP_ENERGY_NOW = 46,\n\tPOWER_SUPPLY_PROP_ENERGY_AVG = 47,\n\tPOWER_SUPPLY_PROP_CAPACITY = 48,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MIN = 49,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MAX = 50,\n\tPOWER_SUPPLY_PROP_CAPACITY_ERROR_MARGIN = 51,\n\tPOWER_SUPPLY_PROP_CAPACITY_LEVEL = 52,\n\tPOWER_SUPPLY_PROP_TEMP = 53,\n\tPOWER_SUPPLY_PROP_TEMP_MAX = 54,\n\tPOWER_SUPPLY_PROP_TEMP_MIN = 55,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MIN = 56,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MAX = 57,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT = 58,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN = 59,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX = 60,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW = 61,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG = 62,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_NOW = 63,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_AVG = 64,\n\tPOWER_SUPPLY_PROP_TYPE = 65,\n\tPOWER_SUPPLY_PROP_USB_TYPE = 66,\n\tPOWER_SUPPLY_PROP_SCOPE = 67,\n\tPOWER_SUPPLY_PROP_PRECHARGE_CURRENT = 68,\n\tPOWER_SUPPLY_PROP_CHARGE_TERM_CURRENT = 69,\n\tPOWER_SUPPLY_PROP_CALIBRATE = 70,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_YEAR = 71,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_MONTH = 72,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_DAY = 73,\n\tPOWER_SUPPLY_PROP_INTERNAL_RESISTANCE = 74,\n\tPOWER_SUPPLY_PROP_STATE_OF_HEALTH = 75,\n\tPOWER_SUPPLY_PROP_MODEL_NAME = 76,\n\tPOWER_SUPPLY_PROP_MANUFACTURER = 77,\n\tPOWER_SUPPLY_PROP_SERIAL_NUMBER = 78,\n};\n\nenum power_supply_type {\n\tPOWER_SUPPLY_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_TYPE_BATTERY = 1,\n\tPOWER_SUPPLY_TYPE_UPS = 2,\n\tPOWER_SUPPLY_TYPE_MAINS = 3,\n\tPOWER_SUPPLY_TYPE_USB = 4,\n\tPOWER_SUPPLY_TYPE_USB_DCP = 5,\n\tPOWER_SUPPLY_TYPE_USB_CDP = 6,\n\tPOWER_SUPPLY_TYPE_USB_ACA = 7,\n\tPOWER_SUPPLY_TYPE_USB_TYPE_C = 8,\n\tPOWER_SUPPLY_TYPE_USB_PD = 9,\n\tPOWER_SUPPLY_TYPE_USB_PD_DRP = 10,\n\tPOWER_SUPPLY_TYPE_APPLE_BRICK_ID = 11,\n\tPOWER_SUPPLY_TYPE_WIRELESS = 12,\n};\n\nenum power_supply_usb_type {\n\tPOWER_SUPPLY_USB_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_USB_TYPE_SDP = 1,\n\tPOWER_SUPPLY_USB_TYPE_DCP = 2,\n\tPOWER_SUPPLY_USB_TYPE_CDP = 3,\n\tPOWER_SUPPLY_USB_TYPE_ACA = 4,\n\tPOWER_SUPPLY_USB_TYPE_C = 5,\n\tPOWER_SUPPLY_USB_TYPE_PD = 6,\n\tPOWER_SUPPLY_USB_TYPE_PD_DRP = 7,\n\tPOWER_SUPPLY_USB_TYPE_PD_PPS = 8,\n\tPOWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID = 9,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum prio_policy {\n\tPOLICY_NO_CHANGE = 0,\n\tPOLICY_PROMOTE_TO_RT = 1,\n\tPOLICY_RESTRICT_TO_BE = 2,\n\tPOLICY_ALL_TO_IDLE = 3,\n\tPOLICY_NONE_TO_RT = 4,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_print_type {\n\tPROBE_PRINT_NORMAL = 0,\n\tPROBE_PRINT_RETURN = 1,\n\tPROBE_PRINT_EVENT = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_cn_mcast_op {\n\tPROC_CN_MCAST_LISTEN = 1,\n\tPROC_CN_MCAST_IGNORE = 2,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___8 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum protection_domain_mode {\n\tPD_MODE_NONE = 0,\n\tPD_MODE_V1 = 1,\n\tPD_MODE_V2 = 2,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum ps2_disposition {\n\tPS2_PROCESS = 0,\n\tPS2_IGNORE = 1,\n\tPS2_ERROR = 2,\n};\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nenum pt_capabilities {\n\tPT_CAP_max_subleaf = 0,\n\tPT_CAP_cr3_filtering = 1,\n\tPT_CAP_psb_cyc = 2,\n\tPT_CAP_ip_filtering = 3,\n\tPT_CAP_mtc = 4,\n\tPT_CAP_ptwrite = 5,\n\tPT_CAP_power_event_trace = 6,\n\tPT_CAP_event_trace = 7,\n\tPT_CAP_tnt_disable = 8,\n\tPT_CAP_topa_output = 9,\n\tPT_CAP_topa_multiple_entries = 10,\n\tPT_CAP_single_range_output = 11,\n\tPT_CAP_output_subsys = 12,\n\tPT_CAP_payloads_lip = 13,\n\tPT_CAP_num_address_ranges = 14,\n\tPT_CAP_mtc_periods = 15,\n\tPT_CAP_cycle_thresholds = 16,\n\tPT_CAP_psb_periods = 17,\n};\n\nenum pt_entry_type {\n\tPT_ENTRY_EMPTY = 0,\n\tPT_ENTRY_TABLE = 1,\n\tPT_ENTRY_OA = 2,\n};\n\nenum pt_features {\n\tPT_FEAT_DMA_INCOHERENT = 0,\n\tPT_FEAT_FULL_VA = 1,\n\tPT_FEAT_DYNAMIC_TOP = 2,\n\tPT_FEAT_SIGN_EXTEND = 3,\n\tPT_FEAT_FLUSH_RANGE = 4,\n\tPT_FEAT_FLUSH_RANGE_NO_GAPS = 5,\n\tPT_FEAT_FMT_START = 6,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum pti_clone_level {\n\tPTI_CLONE_PMD = 0,\n\tPTI_CLONE_PTE = 1,\n};\n\nenum pti_mode {\n\tPTI_AUTO = 0,\n\tPTI_FORCE_OFF = 1,\n\tPTI_FORCE_ON = 2,\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_EXTOFF = 2,\n\tPTP_CLOCK_PPS = 3,\n\tPTP_CLOCK_PPSUSR = 4,\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nenum pwm_polarity {\n\tPWM_POLARITY_NORMAL = 0,\n\tPWM_POLARITY_INVERSED = 1,\n};\n\nenum pxp_status {\n\tPXP_STATUS_SUCCESS = 0,\n\tPXP_STATUS_ERROR_API_VERSION = 4098,\n\tPXP_STATUS_NOT_READY = 4110,\n\tPXP_STATUS_PLATFCONFIG_KF1_NOVERIF = 4122,\n\tPXP_STATUS_PLATFCONFIG_KF1_BAD = 4127,\n\tPXP_STATUS_OP_NOT_PERMITTED = 16403,\n};\n\nenum qdisc_class_ops_flags {\n\tQDISC_CLASS_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum queue_stop_reason {\n\tIEEE80211_QUEUE_STOP_REASON_DRIVER = 0,\n\tIEEE80211_QUEUE_STOP_REASON_PS = 1,\n\tIEEE80211_QUEUE_STOP_REASON_CSA = 2,\n\tIEEE80211_QUEUE_STOP_REASON_AGGREGATION = 3,\n\tIEEE80211_QUEUE_STOP_REASON_SUSPEND = 4,\n\tIEEE80211_QUEUE_STOP_REASON_SKB_ADD = 5,\n\tIEEE80211_QUEUE_STOP_REASON_OFFCHANNEL = 6,\n\tIEEE80211_QUEUE_STOP_REASON_FLUSH = 7,\n\tIEEE80211_QUEUE_STOP_REASON_TDLS_TEARDOWN = 8,\n\tIEEE80211_QUEUE_STOP_REASON_RESERVE_TID = 9,\n\tIEEE80211_QUEUE_STOP_REASON_IFTYPE_CHANGE = 10,\n\tIEEE80211_QUEUE_STOP_REASONS = 11,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum ramfs_param {\n\tOpt_mode___6 = 0,\n};\n\nenum rapl_unit_quirk {\n\tRAPL_UNIT_QUIRK_NONE = 0,\n\tRAPL_UNIT_QUIRK_INTEL_HSW = 1,\n\tRAPL_UNIT_QUIRK_INTEL_SPR = 2,\n};\n\nenum rate_control_capabilities {\n\tRATE_CTRL_CAPA_VHT_EXT_NSS_BW = 1,\n\tRATE_CTRL_CAPA_AMPDU_TRIGGER = 2,\n};\n\nenum rate_info_bw {\n\tRATE_INFO_BW_20 = 0,\n\tRATE_INFO_BW_5 = 1,\n\tRATE_INFO_BW_10 = 2,\n\tRATE_INFO_BW_40 = 3,\n\tRATE_INFO_BW_80 = 4,\n\tRATE_INFO_BW_160 = 5,\n\tRATE_INFO_BW_HE_RU = 6,\n\tRATE_INFO_BW_320 = 7,\n\tRATE_INFO_BW_EHT_RU = 8,\n\tRATE_INFO_BW_1 = 9,\n\tRATE_INFO_BW_2 = 10,\n\tRATE_INFO_BW_4 = 11,\n\tRATE_INFO_BW_8 = 12,\n\tRATE_INFO_BW_16 = 13,\n};\n\nenum rate_info_flags {\n\tRATE_INFO_FLAGS_MCS = 1,\n\tRATE_INFO_FLAGS_VHT_MCS = 2,\n\tRATE_INFO_FLAGS_SHORT_GI = 4,\n\tRATE_INFO_FLAGS_DMG = 8,\n\tRATE_INFO_FLAGS_HE_MCS = 16,\n\tRATE_INFO_FLAGS_EDMG = 32,\n\tRATE_INFO_FLAGS_EXTENDED_SC_DMG = 64,\n\tRATE_INFO_FLAGS_EHT_MCS = 128,\n\tRATE_INFO_FLAGS_S1G_MCS = 256,\n\tRATE_INFO_FLAGS_UHR_MCS = 512,\n\tRATE_INFO_FLAGS_UHR_ELR_MCS = 1024,\n\tRATE_INFO_FLAGS_UHR_IM = 2048,\n};\n\nenum rc_driver_type {\n\tRC_DRIVER_SCANCODE = 0,\n\tRC_DRIVER_IR_RAW = 1,\n\tRC_DRIVER_IR_RAW_TX = 2,\n};\n\nenum rc_proto {\n\tRC_PROTO_UNKNOWN = 0,\n\tRC_PROTO_OTHER = 1,\n\tRC_PROTO_RC5 = 2,\n\tRC_PROTO_RC5X_20 = 3,\n\tRC_PROTO_RC5_SZ = 4,\n\tRC_PROTO_JVC = 5,\n\tRC_PROTO_SONY12 = 6,\n\tRC_PROTO_SONY15 = 7,\n\tRC_PROTO_SONY20 = 8,\n\tRC_PROTO_NEC = 9,\n\tRC_PROTO_NECX = 10,\n\tRC_PROTO_NEC32 = 11,\n\tRC_PROTO_SANYO = 12,\n\tRC_PROTO_MCIR2_KBD = 13,\n\tRC_PROTO_MCIR2_MSE = 14,\n\tRC_PROTO_RC6_0 = 15,\n\tRC_PROTO_RC6_6A_20 = 16,\n\tRC_PROTO_RC6_6A_24 = 17,\n\tRC_PROTO_RC6_6A_32 = 18,\n\tRC_PROTO_RC6_MCE = 19,\n\tRC_PROTO_SHARP = 20,\n\tRC_PROTO_XMP = 21,\n\tRC_PROTO_CEC = 22,\n\tRC_PROTO_IMON = 23,\n\tRC_PROTO_RCMM12 = 24,\n\tRC_PROTO_RCMM24 = 25,\n\tRC_PROTO_RCMM32 = 26,\n\tRC_PROTO_XBOX_DVD = 27,\n\tRC_PROTO_MAX = 27,\n};\n\nenum rdmacg_file_type {\n\tRDMACG_RESOURCE_TYPE_MAX = 0,\n\tRDMACG_RESOURCE_TYPE_STAT = 1,\n};\n\nenum rdmacg_resource_type {\n\tRDMACG_RESOURCE_HCA_HANDLE = 0,\n\tRDMACG_RESOURCE_HCA_OBJECT = 1,\n\tRDMACG_RESOURCE_MAX = 2,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum recovery_flags {\n\tMD_RECOVERY_NEEDED = 0,\n\tMD_RECOVERY_RUNNING = 1,\n\tMD_RECOVERY_INTR = 2,\n\tMD_RECOVERY_DONE = 3,\n\tMD_RECOVERY_FROZEN = 4,\n\tMD_RECOVERY_WAIT = 5,\n\tMD_RECOVERY_SYNC = 6,\n\tMD_RECOVERY_REQUESTED = 7,\n\tMD_RECOVERY_CHECK = 8,\n\tMD_RECOVERY_RECOVER = 9,\n\tMD_RECOVERY_RESHAPE = 10,\n\tMD_RESYNCING_REMOTE = 11,\n\tMD_RECOVERY_LAZY_RECOVER = 12,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum reg_request_treatment {\n\tREG_REQ_OK = 0,\n\tREG_REQ_IGNORE = 1,\n\tREG_REQ_INTERSECT = 2,\n\tREG_REQ_ALREADY_SET = 3,\n};\n\nenum reg_type {\n\tREG_TYPE_RM = 0,\n\tREG_TYPE_REG = 1,\n\tREG_TYPE_INDEX = 2,\n\tREG_TYPE_BASE = 3,\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_FLAT = 2,\n\tREGCACHE_MAPLE = 3,\n\tREGCACHE_FLAT_S = 4,\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum report_header {\n\tHDR_32_BIT = 0,\n\tHDR_64_BIT = 1,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reset_control_flags {\n\tRESET_CONTROL_EXCLUSIVE = 4,\n\tRESET_CONTROL_EXCLUSIVE_DEASSERTED = 12,\n\tRESET_CONTROL_EXCLUSIVE_RELEASED = 0,\n\tRESET_CONTROL_SHARED = 1,\n\tRESET_CONTROL_SHARED_DEASSERTED = 9,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE = 6,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_DEASSERTED = 14,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_RELEASED = 2,\n\tRESET_CONTROL_OPTIONAL_SHARED = 3,\n\tRESET_CONTROL_OPTIONAL_SHARED_DEASSERTED = 11,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum retbleed_mitigation {\n\tRETBLEED_MITIGATION_NONE = 0,\n\tRETBLEED_MITIGATION_AUTO = 1,\n\tRETBLEED_MITIGATION_UNRET = 2,\n\tRETBLEED_MITIGATION_IBPB = 3,\n\tRETBLEED_MITIGATION_IBRS = 4,\n\tRETBLEED_MITIGATION_EIBRS = 5,\n\tRETBLEED_MITIGATION_STUFF = 6,\n};\n\nenum rfds_mitigations {\n\tRFDS_MITIGATION_OFF = 0,\n\tRFDS_MITIGATION_AUTO = 1,\n\tRFDS_MITIGATION_VERW = 2,\n\tRFDS_MITIGATION_UCODE_NEEDED = 3,\n};\n\nenum rfkill_hard_block_reasons {\n\tRFKILL_HARD_BLOCK_SIGNAL = 1,\n\tRFKILL_HARD_BLOCK_NOT_OWNER = 2,\n};\n\nenum rfkill_input_master_mode {\n\tRFKILL_INPUT_MASTER_UNLOCK = 0,\n\tRFKILL_INPUT_MASTER_RESTORE = 1,\n\tRFKILL_INPUT_MASTER_UNBLOCKALL = 2,\n\tNUM_RFKILL_INPUT_MASTER_MODES = 3,\n};\n\nenum rfkill_operation {\n\tRFKILL_OP_ADD = 0,\n\tRFKILL_OP_DEL = 1,\n\tRFKILL_OP_CHANGE = 2,\n\tRFKILL_OP_CHANGE_ALL = 3,\n};\n\nenum rfkill_sched_op {\n\tRFKILL_GLOBAL_OP_EPO = 0,\n\tRFKILL_GLOBAL_OP_RESTORE = 1,\n\tRFKILL_GLOBAL_OP_UNLOCK = 2,\n\tRFKILL_GLOBAL_OP_UNBLOCK = 3,\n};\n\nenum rfkill_type {\n\tRFKILL_TYPE_ALL = 0,\n\tRFKILL_TYPE_WLAN = 1,\n\tRFKILL_TYPE_BLUETOOTH = 2,\n\tRFKILL_TYPE_UWB = 3,\n\tRFKILL_TYPE_WIMAX = 4,\n\tRFKILL_TYPE_WWAN = 5,\n\tRFKILL_TYPE_GPS = 6,\n\tRFKILL_TYPE_FM = 7,\n\tRFKILL_TYPE_NFC = 8,\n\tNUM_RFKILL_TYPES = 9,\n};\n\nenum rfkill_user_states {\n\tRFKILL_USER_STATE_SOFT_BLOCKED = 0,\n\tRFKILL_USER_STATE_UNBLOCKED = 1,\n\tRFKILL_USER_STATE_HARD_BLOCKED = 2,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nenum rpc_accept_stat {\n\tRPC_SUCCESS = 0,\n\tRPC_PROG_UNAVAIL = 1,\n\tRPC_PROG_MISMATCH = 2,\n\tRPC_PROC_UNAVAIL = 3,\n\tRPC_GARBAGE_ARGS = 4,\n\tRPC_SYSTEM_ERR = 5,\n\tRPC_DROP_REPLY = 60000,\n};\n\nenum rpc_auth_flavors {\n\tRPC_AUTH_NULL = 0,\n\tRPC_AUTH_UNIX = 1,\n\tRPC_AUTH_SHORT = 2,\n\tRPC_AUTH_DES = 3,\n\tRPC_AUTH_KRB = 4,\n\tRPC_AUTH_GSS = 6,\n\tRPC_AUTH_TLS = 7,\n\tRPC_AUTH_MAXFLAVOR = 8,\n\tRPC_AUTH_GSS_KRB5 = 390003,\n\tRPC_AUTH_GSS_KRB5I = 390004,\n\tRPC_AUTH_GSS_KRB5P = 390005,\n\tRPC_AUTH_GSS_LKEY = 390006,\n\tRPC_AUTH_GSS_LKEYI = 390007,\n\tRPC_AUTH_GSS_LKEYP = 390008,\n\tRPC_AUTH_GSS_SPKM = 390009,\n\tRPC_AUTH_GSS_SPKMI = 390010,\n\tRPC_AUTH_GSS_SPKMP = 390011,\n};\n\nenum rpc_auth_stat {\n\tRPC_AUTH_OK = 0,\n\tRPC_AUTH_BADCRED = 1,\n\tRPC_AUTH_REJECTEDCRED = 2,\n\tRPC_AUTH_BADVERF = 3,\n\tRPC_AUTH_REJECTEDVERF = 4,\n\tRPC_AUTH_TOOWEAK = 5,\n\tRPC_AUTH_INVALIDRESP = 6,\n\tRPC_AUTH_FAILED = 7,\n\tRPCSEC_GSS_CREDPROBLEM = 13,\n\tRPCSEC_GSS_CTXPROBLEM = 14,\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum rpc_gss_proc {\n\tRPC_GSS_PROC_DATA = 0,\n\tRPC_GSS_PROC_INIT = 1,\n\tRPC_GSS_PROC_CONTINUE_INIT = 2,\n\tRPC_GSS_PROC_DESTROY = 3,\n};\n\nenum rpc_gss_svc {\n\tRPC_GSS_SVC_NONE = 1,\n\tRPC_GSS_SVC_INTEGRITY = 2,\n\tRPC_GSS_SVC_PRIVACY = 3,\n};\n\nenum rpc_msg_type {\n\tRPC_CALL = 0,\n\tRPC_REPLY = 1,\n};\n\nenum rpc_reject_stat {\n\tRPC_MISMATCH = 0,\n\tRPC_AUTH_ERROR = 1,\n};\n\nenum rpc_reply_stat {\n\tRPC_MSG_ACCEPTED = 0,\n\tRPC_MSG_DENIED = 1,\n};\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rsaprivkey_actions {\n\tACT_rsa_get_d = 0,\n\tACT_rsa_get_dp = 1,\n\tACT_rsa_get_dq = 2,\n\tACT_rsa_get_e = 3,\n\tACT_rsa_get_n = 4,\n\tACT_rsa_get_p = 5,\n\tACT_rsa_get_q = 6,\n\tACT_rsa_get_qinv = 7,\n\tNR__rsaprivkey_actions = 8,\n};\n\nenum rsapubkey_actions {\n\tACT_rsa_get_e___2 = 0,\n\tACT_rsa_get_n___2 = 1,\n\tNR__rsapubkey_actions = 2,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rt6_nud_state {\n\tRT6_NUD_FAIL_HARD = -3,\n\tRT6_NUD_FAIL_PROBE = -2,\n\tRT6_NUD_FAIL_DO_RR = -1,\n\tRT6_NUD_SUCCEED = 1,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtl8125_registers {\n\tLEDSEL0 = 24,\n\tINT_CFG0_8125 = 52,\n\tIntrMask_8125 = 56,\n\tIntrStatus_8125 = 60,\n\tINT_CFG1_8125 = 122,\n\tLEDSEL2 = 132,\n\tLEDSEL1 = 134,\n\tTxPoll_8125 = 144,\n\tLEDSEL3 = 150,\n\tMAC0_BKP = 6624,\n\tRSS_CTRL_8125 = 17664,\n\tQ_NUM_CTRL_8125 = 18432,\n\tEEE_TXIDLE_TIMER_8125 = 24648,\n};\n\nenum rtl8168_8101_registers {\n\tCSIDR = 100,\n\tCSIAR = 104,\n\tPMCH = 111,\n\tEPHYAR = 128,\n\tDLLPR = 208,\n\tDBG_REG = 209,\n\tTWSI = 210,\n\tMCU = 211,\n\tEFUSEAR = 220,\n\tMISC_1 = 242,\n};\n\nenum rtl8168_registers {\n\tLED_CTRL = 24,\n\tLED_FREQ = 26,\n\tEEE_LED = 27,\n\tERIDR = 112,\n\tERIAR = 116,\n\tEPHY_RXER_NUM = 124,\n\tOCPDR = 176,\n\tOCPAR = 180,\n\tGPHY_OCP = 184,\n\tRDSAR1 = 208,\n\tMISC = 240,\n\tCOMBO_LTR_EXTEND = 182,\n};\n\nenum rtl_dash_type {\n\tRTL_DASH_NONE = 0,\n\tRTL_DASH_DP = 1,\n\tRTL_DASH_EP = 2,\n\tRTL_DASH_25_BP = 3,\n};\n\nenum rtl_desc_bit {\n\tDescOwn = -2147483648,\n\tRingEnd = 1073741824,\n\tFirstFrag = 536870912,\n\tLastFrag = 268435456,\n};\n\nenum rtl_flag {\n\tRTL_FLAG_TASK_RESET_PENDING = 0,\n\tRTL_FLAG_TASK_TX_TIMEOUT = 1,\n\tRTL_FLAG_MAX = 2,\n};\n\nenum rtl_fw_opcode {\n\tPHY_READ = 0,\n\tPHY_DATA_OR = 1,\n\tPHY_DATA_AND = 2,\n\tPHY_BJMPN = 3,\n\tPHY_MDIO_CHG = 4,\n\tPHY_CLEAR_READCOUNT = 7,\n\tPHY_WRITE = 8,\n\tPHY_READCOUNT_EQ_SKIP = 9,\n\tPHY_COMP_EQ_SKIPN = 10,\n\tPHY_COMP_NEQ_SKIPN = 11,\n\tPHY_WRITE_PREVIOUS = 12,\n\tPHY_SKIPN = 13,\n\tPHY_DELAY_MS = 14,\n};\n\nenum rtl_register_content {\n\tSYSErr = 32768,\n\tPCSTimeout___2 = 16384,\n\tSWInt = 256,\n\tTxDescUnavail = 128,\n\tRxFIFOOver___2 = 64,\n\tLinkChg = 32,\n\tRxOverflow___2 = 16,\n\tTxErr___2 = 8,\n\tTxOK___2 = 4,\n\tRxErr___2 = 2,\n\tRxOK___2 = 1,\n\tRxRWT = 4194304,\n\tRxRES = 2097152,\n\tRxRUNT = 1048576,\n\tRxCRC = 524288,\n\tStopReq = 128,\n\tCmdReset___2 = 16,\n\tCmdRxEnb___2 = 8,\n\tCmdTxEnb___2 = 4,\n\tRxBufEmpty___2 = 1,\n\tHPQ = 128,\n\tNPQ = 64,\n\tFSWInt = 1,\n\tCfg9346_Lock___2 = 0,\n\tCfg9346_Unlock___2 = 192,\n\tAcceptErr = 32,\n\tAcceptRunt = 16,\n\tAcceptBroadcast = 8,\n\tAcceptMulticast = 4,\n\tAcceptMyPhys = 2,\n\tAcceptAllPhys = 1,\n\tTxInterFrameGapShift = 24,\n\tTxDMAShift = 8,\n\tLEDS1 = 128,\n\tLEDS0 = 64,\n\tSpeed_down = 16,\n\tMEMMAP = 8,\n\tIOMAP = 4,\n\tVPD = 2,\n\tPMEnable = 1,\n\tClkReqEn = 128,\n\tMSIEnable = 32,\n\tPCI_Clock_66MHz = 1,\n\tPCI_Clock_33MHz = 0,\n\tMagicPacket = 32,\n\tLinkUp = 16,\n\tJumbo_En0 = 4,\n\tRdy_to_L23 = 2,\n\tBeacon_en = 1,\n\tJumbo_En1 = 2,\n\tBWF = 64,\n\tMWF = 32,\n\tUWF = 16,\n\tSpi_en = 8,\n\tLanWake = 2,\n\tPMEStatus = 1,\n\tASPM_en = 1,\n\tEnableBist = 32768,\n\tMac_dbgo_oe = 16384,\n\tEnAnaPLL = 16384,\n\tNormal_mode = 8192,\n\tForce_half_dup = 4096,\n\tForce_rxflow_en = 2048,\n\tForce_txflow_en = 1024,\n\tCxpl_dbg_sel = 512,\n\tASF = 256,\n\tPktCntrDisable = 128,\n\tMac_dbgo_sel = 28,\n\tRxVlan = 64,\n\tRxChkSum = 32,\n\tPCIDAC = 16,\n\tPCIMulRW = 8,\n\tTBI_Enable = 128,\n\tTxFlowCtrl = 64,\n\tRxFlowCtrl = 32,\n\t_1000bpsF = 16,\n\t_100bps = 8,\n\t_10bps = 4,\n\tLinkStatus = 2,\n\tFullDup = 1,\n\tCounterReset = 1,\n\tCounterDump = 8,\n\tMagicPacket_v2 = 65536,\n};\n\nenum rtl_registers {\n\tMAC0___2 = 0,\n\tMAC4 = 4,\n\tMAR0___2 = 8,\n\tCounterAddrLow = 16,\n\tCounterAddrHigh = 20,\n\tTxDescStartAddrLow = 32,\n\tTxDescStartAddrHigh = 36,\n\tTxHDescStartAddrLow = 40,\n\tTxHDescStartAddrHigh = 44,\n\tFLASH = 48,\n\tERSR = 54,\n\tChipCmd___2 = 55,\n\tTxPoll = 56,\n\tIntrMask___2 = 60,\n\tIntrStatus___2 = 62,\n\tTxConfig___2 = 64,\n\tTX_CONFIG_V2 = 24752,\n\tRxConfig___2 = 68,\n\tCfg9346___2 = 80,\n\tConfig0___2 = 81,\n\tConfig1___2 = 82,\n\tConfig2 = 83,\n\tConfig3___2 = 84,\n\tConfig4___2 = 85,\n\tConfig5___2 = 86,\n\tPHYAR = 96,\n\tPHYstatus = 108,\n\tRxMaxSize = 218,\n\tCPlusCmd = 224,\n\tIntrMitigate = 226,\n\tRxDescAddrLow = 228,\n\tRxDescAddrHigh = 232,\n\tEarlyTxThres = 236,\n\tMaxTxPacketSize = 236,\n\tFuncEvent = 240,\n\tFuncEventMask = 244,\n\tFuncPresetState = 248,\n\tIBCR0 = 248,\n\tIBCR2 = 249,\n\tIBIMR0 = 250,\n\tIBISR0 = 251,\n\tFuncForceEvent = 252,\n\tALDPS_LTR = 57506,\n\tLTR_OBFF_LOCK = 57394,\n\tLTR_SNOOP = 57396,\n};\n\nenum rtl_rx_desc_bit {\n\tPID1 = 262144,\n\tPID0 = 131072,\n\tIPFail = 65536,\n\tUDPFail = 32768,\n\tTCPFail = 16384,\n\tRxVlanTag = 65536,\n};\n\nenum rtl_tx_desc_bit {\n\tTD_LSO = 134217728,\n\tTxVlanTag = 131072,\n};\n\nenum rtl_tx_desc_bit_0 {\n\tTD0_TCP_CS = 65536,\n\tTD0_UDP_CS = 131072,\n\tTD0_IP_CS = 262144,\n};\n\nenum rtl_tx_desc_bit_1 {\n\tTD1_GTSENV4 = 67108864,\n\tTD1_GTSENV6 = 33554432,\n\tTD1_IPv6_CS = 268435456,\n\tTD1_IPv4_CS = 536870912,\n\tTD1_TCP_CS = 1073741824,\n\tTD1_UDP_CS = -2147483648,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum ru_state {\n\tRU_SUSPENDED = 0,\n\tRU_RUNNING = 1,\n\tRU_UNINITIALIZED = -1,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum rx_mode_bits {\n\tAcceptErr___2 = 32,\n\tAcceptRunt___2 = 16,\n\tAcceptBroadcast___2 = 8,\n\tAcceptMulticast___2 = 4,\n\tAcceptMyPhys___2 = 2,\n\tAcceptAllPhys___2 = 1,\n};\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum scb_cmd_hi {\n\tirq_mask_none = 0,\n\tirq_mask_all = 1,\n\tirq_sw_gen = 2,\n};\n\nenum scb_cmd_lo {\n\tcuc_nop = 0,\n\truc_start = 1,\n\truc_load_base = 6,\n\tcuc_start = 16,\n\tcuc_resume = 32,\n\tcuc_dump_addr = 64,\n\tcuc_dump_stats = 80,\n\tcuc_load_base = 96,\n\tcuc_dump_reset = 112,\n};\n\nenum scb_stat_ack {\n\tstat_ack_not_ours = 0,\n\tstat_ack_sw_gen = 4,\n\tstat_ack_rnr = 16,\n\tstat_ack_cu_idle = 32,\n\tstat_ack_frame_rx = 64,\n\tstat_ack_cu_cmd_done = 128,\n\tstat_ack_not_present = 255,\n\tstat_ack_rx = 84,\n\tstat_ack_tx = 160,\n};\n\nenum scb_status {\n\trus_no_res = 8,\n\trus_ready = 16,\n\trus_mask = 60,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_code_set {\n\tPS_CODE_SET_BINARY = 1,\n\tPS_CODE_SET_ASCII = 2,\n\tPS_CODE_SET_UTF8 = 3,\n};\n\nenum scsi_designator_type {\n\tPS_DESIGNATOR_T10 = 1,\n\tPS_DESIGNATOR_EUI64 = 2,\n\tPS_DESIGNATOR_NAA = 3,\n\tPS_DESIGNATOR_NAME = 8,\n};\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP___2 = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 10000,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_cid {\n\tSCTP_CID_DATA = 0,\n\tSCTP_CID_INIT = 1,\n\tSCTP_CID_INIT_ACK = 2,\n\tSCTP_CID_SACK = 3,\n\tSCTP_CID_HEARTBEAT = 4,\n\tSCTP_CID_HEARTBEAT_ACK = 5,\n\tSCTP_CID_ABORT = 6,\n\tSCTP_CID_SHUTDOWN = 7,\n\tSCTP_CID_SHUTDOWN_ACK = 8,\n\tSCTP_CID_ERROR = 9,\n\tSCTP_CID_COOKIE_ECHO = 10,\n\tSCTP_CID_COOKIE_ACK = 11,\n\tSCTP_CID_ECN_ECNE = 12,\n\tSCTP_CID_ECN_CWR = 13,\n\tSCTP_CID_SHUTDOWN_COMPLETE = 14,\n\tSCTP_CID_AUTH = 15,\n\tSCTP_CID_I_DATA = 64,\n\tSCTP_CID_FWD_TSN = 192,\n\tSCTP_CID_ASCONF = 193,\n\tSCTP_CID_I_FWD_TSN = 194,\n\tSCTP_CID_ASCONF_ACK = 128,\n\tSCTP_CID_RECONF = 130,\n\tSCTP_CID_PAD = 132,\n};\n\nenum sctp_conntrack {\n\tSCTP_CONNTRACK_NONE = 0,\n\tSCTP_CONNTRACK_CLOSED = 1,\n\tSCTP_CONNTRACK_COOKIE_WAIT = 2,\n\tSCTP_CONNTRACK_COOKIE_ECHOED = 3,\n\tSCTP_CONNTRACK_ESTABLISHED = 4,\n\tSCTP_CONNTRACK_SHUTDOWN_SENT = 5,\n\tSCTP_CONNTRACK_SHUTDOWN_RECD = 6,\n\tSCTP_CONNTRACK_SHUTDOWN_ACK_SENT = 7,\n\tSCTP_CONNTRACK_HEARTBEAT_SENT = 8,\n\tSCTP_CONNTRACK_HEARTBEAT_ACKED = 9,\n\tSCTP_CONNTRACK_MAX = 10,\n};\n\nenum sctp_endpoint_type {\n\tSCTP_EP_TYPE_SOCKET = 0,\n\tSCTP_EP_TYPE_ASSOCIATION = 1,\n};\n\nenum sctp_event_timeout {\n\tSCTP_EVENT_TIMEOUT_NONE = 0,\n\tSCTP_EVENT_TIMEOUT_T1_COOKIE = 1,\n\tSCTP_EVENT_TIMEOUT_T1_INIT = 2,\n\tSCTP_EVENT_TIMEOUT_T2_SHUTDOWN = 3,\n\tSCTP_EVENT_TIMEOUT_T3_RTX = 4,\n\tSCTP_EVENT_TIMEOUT_T4_RTO = 5,\n\tSCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD = 6,\n\tSCTP_EVENT_TIMEOUT_HEARTBEAT = 7,\n\tSCTP_EVENT_TIMEOUT_RECONF = 8,\n\tSCTP_EVENT_TIMEOUT_PROBE = 9,\n\tSCTP_EVENT_TIMEOUT_SACK = 10,\n\tSCTP_EVENT_TIMEOUT_AUTOCLOSE = 11,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum sctp_param {\n\tSCTP_PARAM_HEARTBEAT_INFO = 256,\n\tSCTP_PARAM_IPV4_ADDRESS = 1280,\n\tSCTP_PARAM_IPV6_ADDRESS = 1536,\n\tSCTP_PARAM_STATE_COOKIE = 1792,\n\tSCTP_PARAM_UNRECOGNIZED_PARAMETERS = 2048,\n\tSCTP_PARAM_COOKIE_PRESERVATIVE = 2304,\n\tSCTP_PARAM_HOST_NAME_ADDRESS = 2816,\n\tSCTP_PARAM_SUPPORTED_ADDRESS_TYPES = 3072,\n\tSCTP_PARAM_ECN_CAPABLE = 128,\n\tSCTP_PARAM_RANDOM = 640,\n\tSCTP_PARAM_CHUNKS = 896,\n\tSCTP_PARAM_HMAC_ALGO = 1152,\n\tSCTP_PARAM_SUPPORTED_EXT = 2176,\n\tSCTP_PARAM_FWD_TSN_SUPPORT = 192,\n\tSCTP_PARAM_ADD_IP = 448,\n\tSCTP_PARAM_DEL_IP = 704,\n\tSCTP_PARAM_ERR_CAUSE = 960,\n\tSCTP_PARAM_SET_PRIMARY = 1216,\n\tSCTP_PARAM_SUCCESS_REPORT = 1472,\n\tSCTP_PARAM_ADAPTATION_LAYER_IND = 1728,\n\tSCTP_PARAM_RESET_OUT_REQUEST = 3328,\n\tSCTP_PARAM_RESET_IN_REQUEST = 3584,\n\tSCTP_PARAM_RESET_TSN_REQUEST = 3840,\n\tSCTP_PARAM_RESET_RESPONSE = 4096,\n\tSCTP_PARAM_RESET_ADD_OUT_STREAMS = 4352,\n\tSCTP_PARAM_RESET_ADD_IN_STREAMS = 4608,\n};\n\nenum sctp_scope {\n\tSCTP_SCOPE_GLOBAL = 0,\n\tSCTP_SCOPE_PRIVATE = 1,\n\tSCTP_SCOPE_LINK = 2,\n\tSCTP_SCOPE_LOOPBACK = 3,\n\tSCTP_SCOPE_UNUSABLE = 4,\n};\n\nenum sctp_socket_type {\n\tSCTP_SOCKET_UDP = 0,\n\tSCTP_SOCKET_UDP_HIGH_BANDWIDTH = 1,\n\tSCTP_SOCKET_TCP = 2,\n};\n\nenum sctp_state {\n\tSCTP_STATE_CLOSED = 0,\n\tSCTP_STATE_COOKIE_WAIT = 1,\n\tSCTP_STATE_COOKIE_ECHOED = 2,\n\tSCTP_STATE_ESTABLISHED = 3,\n\tSCTP_STATE_SHUTDOWN_PENDING = 4,\n\tSCTP_STATE_SHUTDOWN_SENT = 5,\n\tSCTP_STATE_SHUTDOWN_RECEIVED = 6,\n\tSCTP_STATE_SHUTDOWN_ACK_SENT = 7,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 30000,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_HAS_CGROUP_WEIGHT = 65536ULL,\n\tSCX_OPS_ALL_FLAGS = 65663ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1,\n\t__SCX_REENQ_FILTER_MASK = 65535,\n\t__SCX_REENQ_USER_MASK = 1,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum sdp_header_types {\n\tSDP_HDR_UNSPEC = 0,\n\tSDP_HDR_VERSION = 1,\n\tSDP_HDR_OWNER = 2,\n\tSDP_HDR_CONNECTION = 3,\n\tSDP_HDR_MEDIA = 4,\n};\n\nenum sel_inos {\n\tSEL_ROOT_INO = 2,\n\tSEL_LOAD = 3,\n\tSEL_ENFORCE = 4,\n\tSEL_CONTEXT = 5,\n\tSEL_ACCESS = 6,\n\tSEL_CREATE = 7,\n\tSEL_RELABEL = 8,\n\tSEL_USER = 9,\n\tSEL_POLICYVERS = 10,\n\tSEL_COMMIT_BOOLS = 11,\n\tSEL_MLS = 12,\n\tSEL_DISABLE = 13,\n\tSEL_MEMBER = 14,\n\tSEL_CHECKREQPROT = 15,\n\tSEL_COMPAT_NET = 16,\n\tSEL_REJECT_UNKNOWN = 17,\n\tSEL_DENY_UNKNOWN = 18,\n\tSEL_STATUS = 19,\n\tSEL_POLICY = 20,\n\tSEL_VALIDATE_TRANS = 21,\n\tSEL_INO_NEXT = 22,\n};\n\nenum selinux_nlgroups {\n\tSELNLGRP_NONE = 0,\n\tSELNLGRP_AVC = 1,\n\t__SELNLGRP_MAX = 2,\n};\n\nenum ser {\n\tSER_REQUIRED = 1,\n\tNO_SER = 2,\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nenum set_event_iter_type {\n\tSET_EVENT_FILE = 0,\n\tSET_EVENT_MOD = 1,\n};\n\nenum set_key_cmd {\n\tSET_KEY = 0,\n\tDISABLE_KEY = 1,\n};\n\nenum severity_level {\n\tMCE_NO_SEVERITY = 0,\n\tMCE_DEFERRED_SEVERITY = 1,\n\tMCE_UCNA_SEVERITY = 1,\n\tMCE_KEEP_SEVERITY = 2,\n\tMCE_SOME_SEVERITY = 3,\n\tMCE_AO_SEVERITY = 4,\n\tMCE_UC_SEVERITY = 5,\n\tMCE_AR_SEVERITY = 6,\n\tMCE_PANIC_SEVERITY = 7,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum shmem_param {\n\tOpt_gid___9 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___7 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes___2 = 5,\n\tOpt_size___2 = 6,\n\tOpt_uid___8 = 7,\n\tOpt_inode32 = 8,\n\tOpt_inode64 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota___2 = 11,\n\tOpt_usrquota___2 = 12,\n\tOpt_grpquota___2 = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum show_regs_mode {\n\tSHOW_REGS_SHORT = 0,\n\tSHOW_REGS_USER = 1,\n\tSHOW_REGS_ALL = 2,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sip_expectation_classes {\n\tSIP_EXPECT_SIGNALLING = 0,\n\tSIP_EXPECT_AUDIO = 1,\n\tSIP_EXPECT_VIDEO = 2,\n\tSIP_EXPECT_IMAGE = 3,\n\t__SIP_EXPECT_MAX = 4,\n};\n\nenum sip_header_types {\n\tSIP_HDR_CSEQ = 0,\n\tSIP_HDR_FROM = 1,\n\tSIP_HDR_TO = 2,\n\tSIP_HDR_CONTACT = 3,\n\tSIP_HDR_VIA_UDP = 4,\n\tSIP_HDR_VIA_TCP = 5,\n\tSIP_HDR_EXPIRES = 6,\n\tSIP_HDR_CONTENT_LENGTH = 7,\n\tSIP_HDR_CALL_ID = 8,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_ext_id {\n\tSKB_EXT_SEC_PATH = 0,\n\tSKB_EXT_NUM = 1,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum skl_power_gate {\n\tSKL_PG0 = 0,\n\tSKL_PG1 = 1,\n\tSKL_PG2 = 2,\n\tICL_PG3 = 3,\n\tICL_PG4 = 4,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN = 0,\n\tPARTIAL = 1,\n\tUP = 2,\n\tFULL = 3,\n};\n\nenum slpc_event_id {\n\tSLPC_EVENT_RESET = 0,\n\tSLPC_EVENT_SHUTDOWN = 1,\n\tSLPC_EVENT_PLATFORM_INFO_CHANGE = 2,\n\tSLPC_EVENT_DISPLAY_MODE_CHANGE = 3,\n\tSLPC_EVENT_FLIP_COMPLETE = 4,\n\tSLPC_EVENT_QUERY_TASK_STATE = 5,\n\tSLPC_EVENT_PARAMETER_SET = 6,\n\tSLPC_EVENT_PARAMETER_UNSET = 7,\n};\n\nenum slpc_global_state {\n\tSLPC_GLOBAL_STATE_NOT_RUNNING = 0,\n\tSLPC_GLOBAL_STATE_INITIALIZING = 1,\n\tSLPC_GLOBAL_STATE_RESETTING = 2,\n\tSLPC_GLOBAL_STATE_RUNNING = 3,\n\tSLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,\n\tSLPC_GLOBAL_STATE_ERROR = 5,\n};\n\nenum slpc_media_ratio_mode {\n\tSLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL = 0,\n\tSLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE = 1,\n\tSLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,\n};\n\nenum slpc_param_id {\n\tSLPC_PARAM_TASK_ENABLE_GTPERF = 0,\n\tSLPC_PARAM_TASK_DISABLE_GTPERF = 1,\n\tSLPC_PARAM_TASK_ENABLE_BALANCER = 2,\n\tSLPC_PARAM_TASK_DISABLE_BALANCER = 3,\n\tSLPC_PARAM_TASK_ENABLE_DCC = 4,\n\tSLPC_PARAM_TASK_DISABLE_DCC = 5,\n\tSLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,\n\tSLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,\n\tSLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,\n\tSLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,\n\tSLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,\n\tSLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,\n\tSLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,\n\tSLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,\n\tSLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,\n\tSLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,\n\tSLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,\n\tSLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,\n\tSLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,\n\tSLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,\n\tSLPC_PARAM_GLOBAL_RT_MODE_TURBO_FREQ_DELTA_MHZ = 20,\n\tSLPC_PARAM_PWRGATE_RC_MODE = 21,\n\tSLPC_PARAM_EDR_MODE_COMPUTE_TIMEOUT_MS = 22,\n\tSLPC_PARAM_EDR_QOS_FREQ_MHZ = 23,\n\tSLPC_PARAM_MEDIA_FF_RATIO_MODE = 24,\n\tSLPC_PARAM_ENABLE_IA_FREQ_LIMITING = 25,\n\tSLPC_PARAM_STRATEGIES = 26,\n\tSLPC_PARAM_POWER_PROFILE = 27,\n\tSLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY = 28,\n\tSLPC_MAX_PARAM = 32,\n};\n\nenum slpc_power_profiles {\n\tSLPC_POWER_PROFILES_BASE = 0,\n\tSLPC_POWER_PROFILES_POWER_SAVING = 1,\n};\n\nenum smbios_attr_enum {\n\tSMBIOS_ATTR_NONE = 0,\n\tSMBIOS_ATTR_LABEL_SHOW = 1,\n\tSMBIOS_ATTR_INSTANCE_SHOW = 2,\n};\n\nenum smca_bank_types {\n\tSMCA_LS = 0,\n\tSMCA_LS_V2 = 1,\n\tSMCA_IF = 2,\n\tSMCA_L2_CACHE = 3,\n\tSMCA_DE = 4,\n\tSMCA_RESERVED = 5,\n\tSMCA_EX = 6,\n\tSMCA_FP = 7,\n\tSMCA_L3_CACHE = 8,\n\tSMCA_CS = 9,\n\tSMCA_CS_V2 = 10,\n\tSMCA_PIE = 11,\n\tSMCA_UMC = 12,\n\tSMCA_UMC_V2 = 13,\n\tSMCA_MA_LLC = 14,\n\tSMCA_PB = 15,\n\tSMCA_PSP = 16,\n\tSMCA_PSP_V2 = 17,\n\tSMCA_SMU = 18,\n\tSMCA_SMU_V2 = 19,\n\tSMCA_MP5 = 20,\n\tSMCA_MPDMA = 21,\n\tSMCA_NBIO = 22,\n\tSMCA_PCIE = 23,\n\tSMCA_PCIE_V2 = 24,\n\tSMCA_XGMI_PCS = 25,\n\tSMCA_NBIF = 26,\n\tSMCA_SHUB = 27,\n\tSMCA_SATA = 28,\n\tSMCA_USB = 29,\n\tSMCA_USR_DP = 30,\n\tSMCA_USR_CP = 31,\n\tSMCA_GMI_PCS = 32,\n\tSMCA_XGMI_PHY = 33,\n\tSMCA_WAFL_PHY = 34,\n\tSMCA_GMI_PHY = 35,\n\tN_SMCA_BANK_TYPES = 36,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum snd_compr_direction {\n\tSND_COMPRESS_PLAYBACK = 0,\n\tSND_COMPRESS_CAPTURE = 1,\n\tSND_COMPRESS_ACCEL = 2,\n};\n\nenum snd_ctl_add_mode {\n\tCTL_ADD_EXCLUSIVE = 0,\n\tCTL_REPLACE = 1,\n\tCTL_ADD_ON_REPLACE = 2,\n};\n\nenum snd_device_state {\n\tSNDRV_DEV_BUILD = 0,\n\tSNDRV_DEV_REGISTERED = 1,\n\tSNDRV_DEV_DISCONNECTED = 2,\n};\n\nenum snd_device_type {\n\tSNDRV_DEV_LOWLEVEL = 0,\n\tSNDRV_DEV_INFO = 1,\n\tSNDRV_DEV_BUS = 2,\n\tSNDRV_DEV_CODEC = 3,\n\tSNDRV_DEV_PCM = 4,\n\tSNDRV_DEV_COMPRESS = 5,\n\tSNDRV_DEV_RAWMIDI = 6,\n\tSNDRV_DEV_TIMER = 7,\n\tSNDRV_DEV_SEQUENCER = 8,\n\tSNDRV_DEV_HWDEP = 9,\n\tSNDRV_DEV_JACK = 10,\n\tSNDRV_DEV_CONTROL = 11,\n};\n\nenum snd_dma_sync_mode {\n\tSNDRV_DMA_SYNC_CPU = 0,\n\tSNDRV_DMA_SYNC_DEVICE = 1,\n};\n\nenum snd_jack_types {\n\tSND_JACK_HEADPHONE = 1,\n\tSND_JACK_MICROPHONE = 2,\n\tSND_JACK_HEADSET = 3,\n\tSND_JACK_LINEOUT = 4,\n\tSND_JACK_MECHANICAL = 8,\n\tSND_JACK_VIDEOOUT = 16,\n\tSND_JACK_AVOUT = 20,\n\tSND_JACK_LINEIN = 32,\n\tSND_JACK_USB = 64,\n\tSND_JACK_BTN_0 = 16384,\n\tSND_JACK_BTN_1 = 8192,\n\tSND_JACK_BTN_2 = 4096,\n\tSND_JACK_BTN_3 = 2048,\n\tSND_JACK_BTN_4 = 1024,\n\tSND_JACK_BTN_5 = 512,\n};\n\nenum sndrv_ctl_event_type {\n\tSNDRV_CTL_EVENT_ELEM = 0,\n\tSNDRV_CTL_EVENT_LAST = 0,\n};\n\nenum snoop_when {\n\tSUBMIT = 0,\n\tCOMPLETE = 1,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum sony_worker {\n\tSONY_WORKER_STATE = 0,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum spectre_v1_mitigation {\n\tSPECTRE_V1_MITIGATION_NONE = 0,\n\tSPECTRE_V1_MITIGATION_AUTO = 1,\n};\n\nenum spectre_v2_mitigation {\n\tSPECTRE_V2_NONE = 0,\n\tSPECTRE_V2_RETPOLINE = 1,\n\tSPECTRE_V2_LFENCE = 2,\n\tSPECTRE_V2_EIBRS = 3,\n\tSPECTRE_V2_EIBRS_RETPOLINE = 4,\n\tSPECTRE_V2_EIBRS_LFENCE = 5,\n\tSPECTRE_V2_IBRS = 6,\n};\n\nenum spectre_v2_mitigation_cmd {\n\tSPECTRE_V2_CMD_NONE = 0,\n\tSPECTRE_V2_CMD_AUTO = 1,\n\tSPECTRE_V2_CMD_FORCE = 2,\n\tSPECTRE_V2_CMD_RETPOLINE = 3,\n\tSPECTRE_V2_CMD_RETPOLINE_GENERIC = 4,\n\tSPECTRE_V2_CMD_RETPOLINE_LFENCE = 5,\n\tSPECTRE_V2_CMD_EIBRS = 6,\n\tSPECTRE_V2_CMD_EIBRS_RETPOLINE = 7,\n\tSPECTRE_V2_CMD_EIBRS_LFENCE = 8,\n\tSPECTRE_V2_CMD_IBRS = 9,\n};\n\nenum spectre_v2_user_mitigation {\n\tSPECTRE_V2_USER_NONE = 0,\n\tSPECTRE_V2_USER_STRICT = 1,\n\tSPECTRE_V2_USER_STRICT_PREFERRED = 2,\n\tSPECTRE_V2_USER_PRCTL = 3,\n\tSPECTRE_V2_USER_SECCOMP = 4,\n};\n\nenum spectre_v2_user_mitigation_cmd {\n\tSPECTRE_V2_USER_CMD_NONE = 0,\n\tSPECTRE_V2_USER_CMD_AUTO = 1,\n\tSPECTRE_V2_USER_CMD_FORCE = 2,\n\tSPECTRE_V2_USER_CMD_PRCTL = 3,\n\tSPECTRE_V2_USER_CMD_PRCTL_IBPB = 4,\n\tSPECTRE_V2_USER_CMD_SECCOMP = 5,\n\tSPECTRE_V2_USER_CMD_SECCOMP_IBPB = 6,\n};\n\nenum spi_compare_returns {\n\tSPI_COMPARE_SUCCESS = 0,\n\tSPI_COMPARE_FAILURE = 1,\n\tSPI_COMPARE_SKIP_TEST = 2,\n};\n\nenum spi_signal_type {\n\tSPI_SIGNAL_UNKNOWN = 1,\n\tSPI_SIGNAL_SE = 2,\n\tSPI_SIGNAL_LVD = 3,\n\tSPI_SIGNAL_HVD = 4,\n};\n\nenum split_lock_detect_state {\n\tsld_off = 0,\n\tsld_warn = 1,\n\tsld_fatal = 2,\n\tsld_ratelimit = 3,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum srbds_mitigations {\n\tSRBDS_MITIGATION_OFF = 0,\n\tSRBDS_MITIGATION_AUTO = 1,\n\tSRBDS_MITIGATION_UCODE_NEEDED = 2,\n\tSRBDS_MITIGATION_FULL = 3,\n\tSRBDS_MITIGATION_TSX_OFF = 4,\n\tSRBDS_MITIGATION_HYPERVISOR = 5,\n};\n\nenum srso_mitigation {\n\tSRSO_MITIGATION_NONE = 0,\n\tSRSO_MITIGATION_AUTO = 1,\n\tSRSO_MITIGATION_UCODE_NEEDED = 2,\n\tSRSO_MITIGATION_SAFE_RET_UCODE_NEEDED = 3,\n\tSRSO_MITIGATION_MICROCODE = 4,\n\tSRSO_MITIGATION_NOSMT = 5,\n\tSRSO_MITIGATION_SAFE_RET = 6,\n\tSRSO_MITIGATION_IBPB = 7,\n\tSRSO_MITIGATION_IBPB_ON_VMEXIT = 8,\n\tSRSO_MITIGATION_BP_SPEC_REDUCE = 9,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum ssb_mitigation {\n\tSPEC_STORE_BYPASS_NONE = 0,\n\tSPEC_STORE_BYPASS_AUTO = 1,\n\tSPEC_STORE_BYPASS_DISABLE = 2,\n\tSPEC_STORE_BYPASS_PRCTL = 3,\n\tSPEC_STORE_BYPASS_SECCOMP = 4,\n};\n\nenum sta_link_apply_mode {\n\tSTA_LINK_MODE_NEW = 0,\n\tSTA_LINK_MODE_STA_MODIFY = 1,\n\tSTA_LINK_MODE_LINK_MODIFY = 2,\n};\n\nenum sta_notify_cmd {\n\tSTA_NOTIFY_SLEEP = 0,\n\tSTA_NOTIFY_AWAKE = 1,\n};\n\nenum sta_stats_type {\n\tSTA_STATS_RATE_TYPE_INVALID = 0,\n\tSTA_STATS_RATE_TYPE_LEGACY = 1,\n\tSTA_STATS_RATE_TYPE_HT = 2,\n\tSTA_STATS_RATE_TYPE_VHT = 3,\n\tSTA_STATS_RATE_TYPE_HE = 4,\n\tSTA_STATS_RATE_TYPE_S1G = 5,\n\tSTA_STATS_RATE_TYPE_EHT = 6,\n\tSTA_STATS_RATE_TYPE_UHR = 7,\n};\n\nenum stack_type {\n\tSTACK_TYPE_UNKNOWN = 0,\n\tSTACK_TYPE_TASK = 1,\n\tSTACK_TYPE_IRQ = 2,\n\tSTACK_TYPE_SOFTIRQ = 3,\n\tSTACK_TYPE_ENTRY = 4,\n\tSTACK_TYPE_EXCEPTION = 5,\n\tSTACK_TYPE_EXCEPTION_LAST = 10,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum state_protect_how4 {\n\tSP4_NONE = 0,\n\tSP4_MACH_CRED = 1,\n\tSP4_SSV = 2,\n};\n\nenum station_parameters_apply_mask {\n\tSTATION_PARAM_APPLY_UAPSD = 1,\n\tSTATION_PARAM_APPLY_CAPABILITY = 2,\n\tSTATION_PARAM_APPLY_PLINK_STATE = 4,\n};\n\nenum status_css {\n\tCSS_TCPUDPCSOK = 128,\n\tCSS_ISUDP = 64,\n\tCSS_ISTCP = 32,\n\tCSS_ISIPFRAG = 16,\n\tCSS_ISIPV6 = 8,\n\tCSS_IPV4CSUMOK = 4,\n\tCSS_ISIPV4 = 2,\n\tCSS_LINK_BIT = 1,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum stripetype4 {\n\tSTRIPE_SPARSE = 1,\n\tSTRIPE_DENSE = 2,\n};\n\nenum subpixel_order {\n\tSubPixelUnknown = 0,\n\tSubPixelHorizontalRGB = 1,\n\tSubPixelHorizontalBGR = 2,\n\tSubPixelVerticalRGB = 3,\n\tSubPixelVerticalBGR = 4,\n\tSubPixelNone = 5,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum survey_info_flags {\n\tSURVEY_INFO_NOISE_DBM = 1,\n\tSURVEY_INFO_IN_USE = 2,\n\tSURVEY_INFO_TIME = 4,\n\tSURVEY_INFO_TIME_BUSY = 8,\n\tSURVEY_INFO_TIME_EXT_BUSY = 16,\n\tSURVEY_INFO_TIME_RX = 32,\n\tSURVEY_INFO_TIME_TX = 64,\n\tSURVEY_INFO_TIME_SCAN = 128,\n\tSURVEY_INFO_TIME_BSS_RX = 256,\n};\n\nenum suspend_mode {\n\tPRESUSPEND = 0,\n\tPRESUSPEND_UNDO = 1,\n\tPOSTSUSPEND = 2,\n};\n\nenum suspend_stat_step {\n\tSUSPEND_WORKING = 0,\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nenum svc_auth_status {\n\tSVC_GARBAGE = 1,\n\tSVC_VALID = 2,\n\tSVC_NEGATIVE = 3,\n\tSVC_OK = 4,\n\tSVC_DROP = 5,\n\tSVC_CLOSE = 6,\n\tSVC_DENIED = 7,\n\tSVC_PENDING = 8,\n\tSVC_COMPLETE = 9,\n};\n\nenum sw_activity {\n\tOFF = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum switch_power_state {\n\tDRM_SWITCH_POWER_ON = 0,\n\tDRM_SWITCH_POWER_OFF = 1,\n\tDRM_SWITCH_POWER_CHANGING = 2,\n\tDRM_SWITCH_POWER_DYNAMIC_OFF = 3,\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nenum sync {\n\tDEFAULTSYNC = 0,\n\tNOSYNC = 1,\n\tFORCESYNC = 2,\n};\n\nenum sync_action {\n\tACTION_RESYNC = 0,\n\tACTION_RECOVER = 1,\n\tACTION_CHECK = 2,\n\tACTION_REPAIR = 3,\n\tACTION_RESHAPE = 4,\n\tACTION_FROZEN = 5,\n\tACTION_IDLE = 6,\n\tNR_SYNC_ACTIONS = 7,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum syscall_work_bit {\n\tSYSCALL_WORK_BIT_SECCOMP = 0,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACEPOINT = 1,\n\tSYSCALL_WORK_BIT_SYSCALL_TRACE = 2,\n\tSYSCALL_WORK_BIT_SYSCALL_EMU = 3,\n\tSYSCALL_WORK_BIT_SYSCALL_AUDIT = 4,\n\tSYSCALL_WORK_BIT_SYSCALL_USER_DISPATCH = 5,\n\tSYSCALL_WORK_BIT_SYSCALL_EXIT_TRAP = 6,\n\tSYSCALL_WORK_BIT_SYSCALL_RSEQ_SLICE = 7,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum taa_mitigations {\n\tTAA_MITIGATION_OFF = 0,\n\tTAA_MITIGATION_AUTO = 1,\n\tTAA_MITIGATION_UCODE_NEEDED = 2,\n\tTAA_MITIGATION_VERW = 3,\n\tTAA_MITIGATION_TSX_DISABLED = 4,\n};\n\nenum target_state {\n\tSTATE_DISABLED = 0,\n\tSTATE_ENABLED = 1,\n\tSTATE_DEACTIVATED = 2,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_fifo_command {\n\tTC_FIFO_REPLACE = 0,\n\tTC_FIFO_DESTROY = 1,\n\tTC_FIFO_STATS = 2,\n};\n\nenum tc_link_layer {\n\tTC_LINKLAYER_UNAWARE = 0,\n\tTC_LINKLAYER_ETHERNET = 1,\n\tTC_LINKLAYER_ATM = 2,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_port {\n\tTC_PORT_NONE = -1,\n\tTC_PORT_1 = 0,\n\tTC_PORT_2 = 1,\n\tTC_PORT_3 = 2,\n\tTC_PORT_4 = 3,\n\tTC_PORT_5 = 4,\n\tTC_PORT_6 = 5,\n\tI915_MAX_TC_PORTS = 6,\n};\n\nenum tc_port_mode {\n\tTC_PORT_DISCONNECTED = 0,\n\tTC_PORT_TBT_ALT = 1,\n\tTC_PORT_DP_ALT = 2,\n\tTC_PORT_LEGACY = 3,\n};\n\nenum tc_root_command {\n\tTC_ROOT_GRAFT = 0,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcf_proto_ops_flags {\n\tTCF_PROTO_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_bit_set {\n\tTCP_SYN_SET = 0,\n\tTCP_SYNACK_SET = 1,\n\tTCP_FIN_SET = 2,\n\tTCP_ACK_SET = 3,\n\tTCP_RST_SET = 4,\n\tTCP_NONE_SET = 5,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_conntrack {\n\tTCP_CONNTRACK_NONE = 0,\n\tTCP_CONNTRACK_SYN_SENT = 1,\n\tTCP_CONNTRACK_SYN_RECV = 2,\n\tTCP_CONNTRACK_ESTABLISHED = 3,\n\tTCP_CONNTRACK_FIN_WAIT = 4,\n\tTCP_CONNTRACK_CLOSE_WAIT = 5,\n\tTCP_CONNTRACK_LAST_ACK = 6,\n\tTCP_CONNTRACK_TIME_WAIT = 7,\n\tTCP_CONNTRACK_CLOSE = 8,\n\tTCP_CONNTRACK_LISTEN = 9,\n\tTCP_CONNTRACK_MAX = 10,\n\tTCP_CONNTRACK_IGNORE = 11,\n\tTCP_CONNTRACK_RETRANS = 12,\n\tTCP_CONNTRACK_UNACK = 13,\n\tTCP_CONNTRACK_TIMEOUT_MAX = 14,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum thermal_device_mode {\n\tTHERMAL_DEVICE_DISABLED = 0,\n\tTHERMAL_DEVICE_ENABLED = 1,\n};\n\nenum thermal_genl_attr {\n\tTHERMAL_GENL_ATTR_UNSPEC = 0,\n\tTHERMAL_GENL_ATTR_TZ = 1,\n\tTHERMAL_GENL_ATTR_TZ_ID = 2,\n\tTHERMAL_GENL_ATTR_TZ_TEMP = 3,\n\tTHERMAL_GENL_ATTR_TZ_TRIP = 4,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_ID = 5,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_TYPE = 6,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_TEMP = 7,\n\tTHERMAL_GENL_ATTR_TZ_TRIP_HYST = 8,\n\tTHERMAL_GENL_ATTR_TZ_MODE = 9,\n\tTHERMAL_GENL_ATTR_TZ_NAME = 10,\n\tTHERMAL_GENL_ATTR_TZ_CDEV_WEIGHT = 11,\n\tTHERMAL_GENL_ATTR_TZ_GOV = 12,\n\tTHERMAL_GENL_ATTR_TZ_GOV_NAME = 13,\n\tTHERMAL_GENL_ATTR_CDEV = 14,\n\tTHERMAL_GENL_ATTR_CDEV_ID = 15,\n\tTHERMAL_GENL_ATTR_CDEV_CUR_STATE = 16,\n\tTHERMAL_GENL_ATTR_CDEV_MAX_STATE = 17,\n\tTHERMAL_GENL_ATTR_CDEV_NAME = 18,\n\tTHERMAL_GENL_ATTR_GOV_NAME = 19,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY = 20,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY_ID = 21,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY_PERFORMANCE = 22,\n\tTHERMAL_GENL_ATTR_CPU_CAPABILITY_EFFICIENCY = 23,\n\tTHERMAL_GENL_ATTR_THRESHOLD = 24,\n\tTHERMAL_GENL_ATTR_THRESHOLD_TEMP = 25,\n\tTHERMAL_GENL_ATTR_THRESHOLD_DIRECTION = 26,\n\tTHERMAL_GENL_ATTR_TZ_PREV_TEMP = 27,\n\t__THERMAL_GENL_ATTR_MAX = 28,\n};\n\nenum thermal_genl_cmd {\n\tTHERMAL_GENL_CMD_UNSPEC = 0,\n\tTHERMAL_GENL_CMD_TZ_GET_ID = 1,\n\tTHERMAL_GENL_CMD_TZ_GET_TRIP = 2,\n\tTHERMAL_GENL_CMD_TZ_GET_TEMP = 3,\n\tTHERMAL_GENL_CMD_TZ_GET_GOV = 4,\n\tTHERMAL_GENL_CMD_TZ_GET_MODE = 5,\n\tTHERMAL_GENL_CMD_CDEV_GET = 6,\n\tTHERMAL_GENL_CMD_THRESHOLD_GET = 7,\n\tTHERMAL_GENL_CMD_THRESHOLD_ADD = 8,\n\tTHERMAL_GENL_CMD_THRESHOLD_DELETE = 9,\n\tTHERMAL_GENL_CMD_THRESHOLD_FLUSH = 10,\n\t__THERMAL_GENL_CMD_MAX = 11,\n};\n\nenum thermal_genl_event {\n\tTHERMAL_GENL_EVENT_UNSPEC = 0,\n\tTHERMAL_GENL_EVENT_TZ_CREATE = 1,\n\tTHERMAL_GENL_EVENT_TZ_DELETE = 2,\n\tTHERMAL_GENL_EVENT_TZ_DISABLE = 3,\n\tTHERMAL_GENL_EVENT_TZ_ENABLE = 4,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_UP = 5,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_DOWN = 6,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_CHANGE = 7,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_ADD = 8,\n\tTHERMAL_GENL_EVENT_TZ_TRIP_DELETE = 9,\n\tTHERMAL_GENL_EVENT_CDEV_ADD = 10,\n\tTHERMAL_GENL_EVENT_CDEV_DELETE = 11,\n\tTHERMAL_GENL_EVENT_CDEV_STATE_UPDATE = 12,\n\tTHERMAL_GENL_EVENT_TZ_GOV_CHANGE = 13,\n\tTHERMAL_GENL_EVENT_CPU_CAPABILITY_CHANGE = 14,\n\tTHERMAL_GENL_EVENT_THRESHOLD_ADD = 15,\n\tTHERMAL_GENL_EVENT_THRESHOLD_DELETE = 16,\n\tTHERMAL_GENL_EVENT_THRESHOLD_FLUSH = 17,\n\tTHERMAL_GENL_EVENT_THRESHOLD_UP = 18,\n\tTHERMAL_GENL_EVENT_THRESHOLD_DOWN = 19,\n\t__THERMAL_GENL_EVENT_MAX = 20,\n};\n\nenum thermal_genl_multicast_groups {\n\tTHERMAL_GENL_SAMPLING_GROUP = 0,\n\tTHERMAL_GENL_EVENT_GROUP = 1,\n\tTHERMAL_GENL_MAX_GROUP = 1,\n};\n\nenum thermal_genl_sampling {\n\tTHERMAL_GENL_SAMPLING_TEMP = 0,\n\t__THERMAL_GENL_SAMPLING_MAX = 1,\n};\n\nenum thermal_notify_event {\n\tTHERMAL_EVENT_UNSPECIFIED = 0,\n\tTHERMAL_EVENT_TEMP_SAMPLE = 1,\n\tTHERMAL_TRIP_VIOLATED = 2,\n\tTHERMAL_TRIP_CHANGED = 3,\n\tTHERMAL_DEVICE_DOWN = 4,\n\tTHERMAL_DEVICE_UP = 5,\n\tTHERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6,\n\tTHERMAL_TABLE_CHANGED = 7,\n\tTHERMAL_EVENT_KEEP_ALIVE = 8,\n\tTHERMAL_TZ_BIND_CDEV = 9,\n\tTHERMAL_TZ_UNBIND_CDEV = 10,\n\tTHERMAL_INSTANCE_WEIGHT_CHANGED = 11,\n\tTHERMAL_TZ_RESUME = 12,\n\tTHERMAL_TZ_ADD_THRESHOLD = 13,\n\tTHERMAL_TZ_DEL_THRESHOLD = 14,\n\tTHERMAL_TZ_FLUSH_THRESHOLDS = 15,\n};\n\nenum thermal_trend {\n\tTHERMAL_TREND_STABLE = 0,\n\tTHERMAL_TREND_RAISING = 1,\n\tTHERMAL_TREND_DROPPING = 2,\n};\n\nenum thermal_trip_type {\n\tTHERMAL_TRIP_ACTIVE = 0,\n\tTHERMAL_TRIP_PASSIVE = 1,\n\tTHERMAL_TRIP_HOT = 2,\n\tTHERMAL_TRIP_CRITICAL = 3,\n};\n\nenum tick_broadcast_mode {\n\tTICK_BROADCAST_OFF = 0,\n\tTICK_BROADCAST_ON = 1,\n\tTICK_BROADCAST_FORCE = 2,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPERS_MAX = 1,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timer_tread_format {\n\tTREAD_FORMAT_NONE = 0,\n\tTREAD_FORMAT_TIME64 = 1,\n\tTREAD_FORMAT_TIME32 = 2,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum tlb_flush_reason {\n\tTLB_FLUSH_ON_TASK_SWITCH = 0,\n\tTLB_REMOTE_SHOOTDOWN = 1,\n\tTLB_LOCAL_SHOOTDOWN = 2,\n\tTLB_LOCAL_MM_SHOOTDOWN = 3,\n\tTLB_REMOTE_SEND_IPI = 4,\n\tTLB_REMOTE_WRONG_CPU = 5,\n};\n\nenum topo_types {\n\tINVALID_TYPE = 0,\n\tSMT_TYPE = 1,\n\tCORE_TYPE = 2,\n\tMAX_TYPE_0B = 3,\n\tMODULE_TYPE = 3,\n\tAMD_CCD_TYPE = 3,\n\tTILE_TYPE = 4,\n\tAMD_SOCKET_TYPE = 4,\n\tMAX_TYPE_80000026 = 5,\n\tDIE_TYPE = 5,\n\tDIEGRP_TYPE = 6,\n\tMAX_TYPE_1F = 7,\n};\n\nenum tp_func_state {\n\tTP_FUNC_0 = 0,\n\tTP_FUNC_1 = 1,\n\tTP_FUNC_2 = 2,\n\tTP_FUNC_N = 3,\n};\n\nenum tp_transition_sync {\n\tTP_TRANSITION_SYNC_1_0_1 = 0,\n\tTP_TRANSITION_SYNC_N_2_1 = 1,\n\t_NR_TP_TRANSITION_SYNC = 2,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_NEED_RESCHED_LAZY = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n\tTRACE_FLAG_BH_OFF = 128,\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n\tTRACE_FILE_PAUSE = 8,\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_FIELDS_BIT = 8,\n\tTRACE_ITER_PRINTK_BIT = 9,\n\tTRACE_ITER_ANNOTATE_BIT = 10,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 11,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 12,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 13,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 14,\n\tTRACE_ITER_LATENCY_FMT_BIT = 15,\n\tTRACE_ITER_RECORD_CMD_BIT = 16,\n\tTRACE_ITER_RECORD_TGID_BIT = 17,\n\tTRACE_ITER_OVERWRITE_BIT = 18,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 19,\n\tTRACE_ITER_IRQ_INFO_BIT = 20,\n\tTRACE_ITER_MARKERS_BIT = 21,\n\tTRACE_ITER_EVENT_FORK_BIT = 22,\n\tTRACE_ITER_TRACE_PRINTK_BIT = 23,\n\tTRACE_ITER_COPY_MARKER_BIT = 24,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 25,\n\tTRACE_ITER_HASH_PTR_BIT = 26,\n\tTRACE_ITER_BITMASK_LIST_BIT = 27,\n\tTRACE_ITER_STACKTRACE_BIT = 28,\n\tTRACE_ITER_LAST_BIT = 29,\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_GRAPH_RETADDR_ENT = 12,\n\tTRACE_USER_STACK = 13,\n\tTRACE_BLK = 14,\n\tTRACE_BPUTS = 15,\n\tTRACE_HWLAT = 16,\n\tTRACE_OSNOISE = 17,\n\tTRACE_TIMERLAT = 18,\n\tTRACE_RAW_DATA = 19,\n\tTRACE_FUNC_REPEATS = 20,\n\t__TRACE_LAST_TYPE = 21,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum transcoder {\n\tINVALID_TRANSCODER = -1,\n\tTRANSCODER_A = 0,\n\tTRANSCODER_B = 1,\n\tTRANSCODER_C = 2,\n\tTRANSCODER_D = 3,\n\tTRANSCODER_EDP = 4,\n\tTRANSCODER_DSI_0 = 5,\n\tTRANSCODER_DSI_1 = 6,\n\tTRANSCODER_DSI_A = 5,\n\tTRANSCODER_DSI_C = 6,\n\tI915_MAX_TRANSCODERS = 7,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum tsa_mitigations {\n\tTSA_MITIGATION_NONE = 0,\n\tTSA_MITIGATION_AUTO = 1,\n\tTSA_MITIGATION_UCODE_NEEDED = 2,\n\tTSA_MITIGATION_USER_KERNEL = 3,\n\tTSA_MITIGATION_VM = 4,\n\tTSA_MITIGATION_FULL = 5,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum tsx_ctrl_states {\n\tTSX_CTRL_AUTO = 0,\n\tTSX_CTRL_ENABLE = 1,\n\tTSX_CTRL_DISABLE = 2,\n\tTSX_CTRL_RTM_ALWAYS_ABORT = 3,\n\tTSX_CTRL_NOT_SUPPORTED = 4,\n};\n\nenum ttm_bo_type {\n\tttm_bo_type_device = 0,\n\tttm_bo_type_kernel = 1,\n\tttm_bo_type_sg = 2,\n};\n\nenum ttm_caching {\n\tttm_uncached = 0,\n\tttm_write_combined = 1,\n\tttm_cached = 2,\n};\n\nenum ttm_lru_item_type {\n\tTTM_LRU_RESOURCE = 0,\n\tTTM_LRU_HITCH = 1,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tunnel_encap_types {\n\tTUNNEL_ENCAP_NONE = 0,\n\tTUNNEL_ENCAP_FOU = 1,\n\tTUNNEL_ENCAP_GUE = 2,\n\tTUNNEL_ENCAP_MPLS = 3,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum tx_config_bits {\n\tTxIFGShift = 24,\n\tTxIFG84 = 0,\n\tTxIFG88 = 16777216,\n\tTxIFG92 = 33554432,\n\tTxIFG96 = 50331648,\n\tTxLoopBack = 393216,\n\tTxCRC = 65536,\n\tTxClearAbt = 1,\n\tTxDMAShift___2 = 8,\n\tTxRetryShift = 4,\n\tTxVersionMask = 2088763392,\n};\n\nenum txq_info_flags {\n\tIEEE80211_TXQ_STOP = 0,\n\tIEEE80211_TXQ_AMPDU = 1,\n\tIEEE80211_TXQ_NO_AMSDU = 2,\n\tIEEE80211_TXQ_DIRTY = 3,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum uart_iotype {\n\tUPIO_UNKNOWN = -1,\n\tUPIO_PORT = 0,\n\tUPIO_HUB6 = 1,\n\tUPIO_MEM = 2,\n\tUPIO_MEM32 = 3,\n\tUPIO_AU = 4,\n\tUPIO_TSI = 5,\n\tUPIO_MEM32BE = 6,\n\tUPIO_MEM16 = 7,\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucode_state {\n\tUCODE_OK = 0,\n\tUCODE_NEW = 1,\n\tUCODE_NEW_SAFE = 2,\n\tUCODE_UPDATED = 3,\n\tUCODE_NFOUND = 4,\n\tUCODE_ERROR = 5,\n\tUCODE_TIMEOUT = 6,\n\tUCODE_OFFLINE = 7,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_COUNTS = 10,\n};\n\nenum udp_conntrack {\n\tUDP_CT_UNREPLIED = 0,\n\tUDP_CT_REPLIED = 1,\n\tUDP_CT_MAX = 2,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum uhci_rh_state {\n\tUHCI_RH_RESET = 0,\n\tUHCI_RH_SUSPENDED = 1,\n\tUHCI_RH_AUTO_STOPPED = 2,\n\tUHCI_RH_RESUMING = 3,\n\tUHCI_RH_SUSPENDING = 4,\n\tUHCI_RH_RUNNING = 5,\n\tUHCI_RH_RUNNING_NODEVS = 6,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum uncore_access_type {\n\tUNCORE_ACCESS_MSR = 0,\n\tUNCORE_ACCESS_MMIO = 1,\n\tUNCORE_ACCESS_PCI = 2,\n\tUNCORE_ACCESS_MAX = 3,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_user_type {\n\tUNWIND_USER_TYPE_NONE = 0,\n\tUNWIND_USER_TYPE_FP = 1,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nenum usb3_link_state {\n\tUSB3_LPM_U0 = 0,\n\tUSB3_LPM_U1 = 1,\n\tUSB3_LPM_U2 = 2,\n\tUSB3_LPM_U3 = 3,\n};\n\nenum usb_charger_state {\n\tUSB_CHARGER_DEFAULT = 0,\n\tUSB_CHARGER_PRESENT = 1,\n\tUSB_CHARGER_ABSENT = 2,\n};\n\nenum usb_charger_type {\n\tUNKNOWN_TYPE = 0,\n\tSDP_TYPE = 1,\n\tDCP_TYPE = 2,\n\tCDP_TYPE = 3,\n\tACA_TYPE = 4,\n};\n\nenum usb_dev_authorize_policy {\n\tUSB_DEVICE_AUTHORIZE_NONE = 0,\n\tUSB_DEVICE_AUTHORIZE_ALL = 1,\n\tUSB_DEVICE_AUTHORIZE_INTERNAL = 2,\n};\n\nenum usb_device_speed {\n\tUSB_SPEED_UNKNOWN = 0,\n\tUSB_SPEED_LOW = 1,\n\tUSB_SPEED_FULL = 2,\n\tUSB_SPEED_HIGH = 3,\n\tUSB_SPEED_WIRELESS = 4,\n\tUSB_SPEED_SUPER = 5,\n\tUSB_SPEED_SUPER_PLUS = 6,\n};\n\nenum usb_device_state {\n\tUSB_STATE_NOTATTACHED = 0,\n\tUSB_STATE_ATTACHED = 1,\n\tUSB_STATE_POWERED = 2,\n\tUSB_STATE_RECONNECTING = 3,\n\tUSB_STATE_UNAUTHENTICATED = 4,\n\tUSB_STATE_DEFAULT = 5,\n\tUSB_STATE_ADDRESS = 6,\n\tUSB_STATE_CONFIGURED = 7,\n\tUSB_STATE_SUSPENDED = 8,\n};\n\nenum usb_dr_mode {\n\tUSB_DR_MODE_UNKNOWN = 0,\n\tUSB_DR_MODE_HOST = 1,\n\tUSB_DR_MODE_PERIPHERAL = 2,\n\tUSB_DR_MODE_OTG = 3,\n};\n\nenum usb_interface_condition {\n\tUSB_INTERFACE_UNBOUND = 0,\n\tUSB_INTERFACE_BINDING = 1,\n\tUSB_INTERFACE_BOUND = 2,\n\tUSB_INTERFACE_UNBINDING = 3,\n};\n\nenum usb_led_event {\n\tUSB_LED_EVENT_HOST = 0,\n\tUSB_LED_EVENT_GADGET = 1,\n};\n\nenum usb_link_tunnel_mode {\n\tUSB_LINK_UNKNOWN = 0,\n\tUSB_LINK_NATIVE = 1,\n\tUSB_LINK_TUNNELED = 2,\n};\n\nenum usb_otg_state {\n\tOTG_STATE_UNDEFINED = 0,\n\tOTG_STATE_B_IDLE = 1,\n\tOTG_STATE_B_SRP_INIT = 2,\n\tOTG_STATE_B_PERIPHERAL = 3,\n\tOTG_STATE_B_WAIT_ACON = 4,\n\tOTG_STATE_B_HOST = 5,\n\tOTG_STATE_A_IDLE = 6,\n\tOTG_STATE_A_WAIT_VRISE = 7,\n\tOTG_STATE_A_WAIT_BCON = 8,\n\tOTG_STATE_A_HOST = 9,\n\tOTG_STATE_A_SUSPEND = 10,\n\tOTG_STATE_A_PERIPHERAL = 11,\n\tOTG_STATE_A_WAIT_VFALL = 12,\n\tOTG_STATE_A_VBUS_ERR = 13,\n};\n\nenum usb_phy_events {\n\tUSB_EVENT_NONE = 0,\n\tUSB_EVENT_VBUS = 1,\n\tUSB_EVENT_ID = 2,\n\tUSB_EVENT_CHARGER = 3,\n\tUSB_EVENT_ENUMERATED = 4,\n};\n\nenum usb_phy_type {\n\tUSB_PHY_TYPE_UNDEFINED = 0,\n\tUSB_PHY_TYPE_USB2 = 1,\n\tUSB_PHY_TYPE_USB3 = 2,\n};\n\nenum usb_port_connect_type {\n\tUSB_PORT_CONNECT_TYPE_UNKNOWN = 0,\n\tUSB_PORT_CONNECT_TYPE_HOT_PLUG = 1,\n\tUSB_PORT_CONNECT_TYPE_HARD_WIRED = 2,\n\tUSB_PORT_NOT_USED = 3,\n};\n\nenum usb_ssp_rate {\n\tUSB_SSP_GEN_UNKNOWN = 0,\n\tUSB_SSP_GEN_2x1 = 1,\n\tUSB_SSP_GEN_1x2 = 2,\n\tUSB_SSP_GEN_2x2 = 3,\n};\n\nenum usb_wireless_status {\n\tUSB_WIRELESS_STATUS_NA = 0,\n\tUSB_WIRELESS_STATUS_DISCONNECTED = 1,\n\tUSB_WIRELESS_STATUS_CONNECTED = 2,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum uv_system_type {\n\tUV_NONE = 0,\n\tUV_LEGACY_APIC = 1,\n\tUV_X2APIC = 2,\n};\n\nenum v4l2_av1_segment_feature {\n\tV4L2_AV1_SEG_LVL_ALT_Q = 0,\n\tV4L2_AV1_SEG_LVL_ALT_LF_Y_V = 1,\n\tV4L2_AV1_SEG_LVL_REF_FRAME = 5,\n\tV4L2_AV1_SEG_LVL_REF_SKIP = 6,\n\tV4L2_AV1_SEG_LVL_REF_GLOBALMV = 7,\n\tV4L2_AV1_SEG_LVL_MAX = 8,\n};\n\nenum v4l2_fwnode_bus_type {\n\tV4L2_FWNODE_BUS_TYPE_GUESS = 0,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_CPHY = 1,\n\tV4L2_FWNODE_BUS_TYPE_CSI1 = 2,\n\tV4L2_FWNODE_BUS_TYPE_CCP2 = 3,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_DPHY = 4,\n\tV4L2_FWNODE_BUS_TYPE_PARALLEL = 5,\n\tV4L2_FWNODE_BUS_TYPE_BT656 = 6,\n\tV4L2_FWNODE_BUS_TYPE_DPI = 7,\n\tNR_OF_V4L2_FWNODE_BUS_TYPE = 8,\n};\n\nenum v4l2_preemphasis {\n\tV4L2_PREEMPHASIS_DISABLED = 0,\n\tV4L2_PREEMPHASIS_50_uS = 1,\n\tV4L2_PREEMPHASIS_75_uS = 2,\n};\n\nenum vbt_gmbus_ddi {\n\tDDC_BUS_DDI_B = 1,\n\tDDC_BUS_DDI_C = 2,\n\tDDC_BUS_DDI_D = 3,\n\tDDC_BUS_DDI_F = 4,\n\tICL_DDC_BUS_DDI_A = 1,\n\tICL_DDC_BUS_DDI_B = 2,\n\tTGL_DDC_BUS_DDI_C = 3,\n\tRKL_DDC_BUS_DDI_D = 3,\n\tRKL_DDC_BUS_DDI_E = 4,\n\tICL_DDC_BUS_PORT_1 = 4,\n\tICL_DDC_BUS_PORT_2 = 5,\n\tICL_DDC_BUS_PORT_3 = 6,\n\tICL_DDC_BUS_PORT_4 = 7,\n\tTGL_DDC_BUS_PORT_5 = 8,\n\tTGL_DDC_BUS_PORT_6 = 9,\n\tADLS_DDC_BUS_PORT_TC1 = 2,\n\tADLS_DDC_BUS_PORT_TC2 = 3,\n\tADLS_DDC_BUS_PORT_TC3 = 4,\n\tADLS_DDC_BUS_PORT_TC4 = 5,\n\tADLP_DDC_BUS_PORT_TC1 = 3,\n\tADLP_DDC_BUS_PORT_TC2 = 4,\n\tADLP_DDC_BUS_PORT_TC3 = 5,\n\tADLP_DDC_BUS_PORT_TC4 = 6,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_TSC = 1,\n\tVDSO_CLOCKMODE_PVCLOCK = 2,\n\tVDSO_CLOCKMODE_HVCLOCK = 3,\n\tVDSO_CLOCKMODE_MAX = 4,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum vga_switcheroo_client_id {\n\tVGA_SWITCHEROO_UNKNOWN_ID = 4096,\n\tVGA_SWITCHEROO_IGD = 0,\n\tVGA_SWITCHEROO_DIS = 1,\n\tVGA_SWITCHEROO_MAX_CLIENTS = 2,\n};\n\nenum vga_switcheroo_handler_flags_t {\n\tVGA_SWITCHEROO_CAN_SWITCH_DDC = 1,\n\tVGA_SWITCHEROO_NEEDS_EDP_CONFIG = 2,\n};\n\nenum vga_switcheroo_state {\n\tVGA_SWITCHEROO_OFF = 0,\n\tVGA_SWITCHEROO_ON = 1,\n\tVGA_SWITCHEROO_NOT_FOUND = 2,\n};\n\nenum vgt_g2v_type {\n\tVGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,\n\tVGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY = 3,\n\tVGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE = 4,\n\tVGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY = 5,\n\tVGT_G2V_EXECLIST_CONTEXT_CREATE = 6,\n\tVGT_G2V_EXECLIST_CONTEXT_DESTROY = 7,\n\tVGT_G2V_MAX = 8,\n};\n\nenum virtio_gpu_ctrl_type {\n\tVIRTIO_GPU_UNDEFINED = 0,\n\tVIRTIO_GPU_CMD_GET_DISPLAY_INFO = 256,\n\tVIRTIO_GPU_CMD_RESOURCE_CREATE_2D = 257,\n\tVIRTIO_GPU_CMD_RESOURCE_UNREF = 258,\n\tVIRTIO_GPU_CMD_SET_SCANOUT = 259,\n\tVIRTIO_GPU_CMD_RESOURCE_FLUSH = 260,\n\tVIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D = 261,\n\tVIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING = 262,\n\tVIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING = 263,\n\tVIRTIO_GPU_CMD_GET_CAPSET_INFO = 264,\n\tVIRTIO_GPU_CMD_GET_CAPSET = 265,\n\tVIRTIO_GPU_CMD_GET_EDID = 266,\n\tVIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID = 267,\n\tVIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB = 268,\n\tVIRTIO_GPU_CMD_SET_SCANOUT_BLOB = 269,\n\tVIRTIO_GPU_CMD_CTX_CREATE = 512,\n\tVIRTIO_GPU_CMD_CTX_DESTROY = 513,\n\tVIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE = 514,\n\tVIRTIO_GPU_CMD_CTX_DETACH_RESOURCE = 515,\n\tVIRTIO_GPU_CMD_RESOURCE_CREATE_3D = 516,\n\tVIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D = 517,\n\tVIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D = 518,\n\tVIRTIO_GPU_CMD_SUBMIT_3D = 519,\n\tVIRTIO_GPU_CMD_RESOURCE_MAP_BLOB = 520,\n\tVIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB = 521,\n\tVIRTIO_GPU_CMD_UPDATE_CURSOR = 768,\n\tVIRTIO_GPU_CMD_MOVE_CURSOR = 769,\n\tVIRTIO_GPU_RESP_OK_NODATA = 4352,\n\tVIRTIO_GPU_RESP_OK_DISPLAY_INFO = 4353,\n\tVIRTIO_GPU_RESP_OK_CAPSET_INFO = 4354,\n\tVIRTIO_GPU_RESP_OK_CAPSET = 4355,\n\tVIRTIO_GPU_RESP_OK_EDID = 4356,\n\tVIRTIO_GPU_RESP_OK_RESOURCE_UUID = 4357,\n\tVIRTIO_GPU_RESP_OK_MAP_INFO = 4358,\n\tVIRTIO_GPU_RESP_ERR_UNSPEC = 4608,\n\tVIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY = 4609,\n\tVIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID = 4610,\n\tVIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID = 4611,\n\tVIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID = 4612,\n\tVIRTIO_GPU_RESP_ERR_INVALID_PARAMETER = 4613,\n};\n\nenum virtio_gpu_formats {\n\tVIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,\n\tVIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,\n\tVIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,\n\tVIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,\n\tVIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,\n\tVIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,\n\tVIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,\n\tVIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,\n};\n\nenum virtio_gpu_shm_id {\n\tVIRTIO_GPU_SHM_ID_UNDEFINED = 0,\n\tVIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1,\n};\n\nenum virtio_input_config_select {\n\tVIRTIO_INPUT_CFG_UNSET = 0,\n\tVIRTIO_INPUT_CFG_ID_NAME = 1,\n\tVIRTIO_INPUT_CFG_ID_SERIAL = 2,\n\tVIRTIO_INPUT_CFG_ID_DEVIDS = 3,\n\tVIRTIO_INPUT_CFG_PROP_BITS = 16,\n\tVIRTIO_INPUT_CFG_EV_BITS = 17,\n\tVIRTIO_INPUT_CFG_ABS_INFO = 18,\n};\n\nenum virtnet_xmit_type {\n\tVIRTNET_XMIT_TYPE_SKB = 0,\n\tVIRTNET_XMIT_TYPE_SKB_ORPHAN = 1,\n\tVIRTNET_XMIT_TYPE_XDP = 2,\n\tVIRTNET_XMIT_TYPE_XSK = 3,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vlv_iosf_sb_unit {\n\tVLV_IOSF_SB_BUNIT = 0,\n\tVLV_IOSF_SB_CCK = 1,\n\tVLV_IOSF_SB_CCU = 2,\n\tVLV_IOSF_SB_DPIO = 3,\n\tVLV_IOSF_SB_DPIO_2 = 4,\n\tVLV_IOSF_SB_FLISDSI = 5,\n\tVLV_IOSF_SB_GPIO = 6,\n\tVLV_IOSF_SB_NC = 7,\n\tVLV_IOSF_SB_PUNIT = 8,\n};\n\nenum vlv_wm_level {\n\tVLV_WM_LEVEL_PM2 = 0,\n\tVLV_WM_LEVEL_PM5 = 1,\n\tVLV_WM_LEVEL_DDR_DVFS = 2,\n\tNUM_VLV_WM_LEVELS = 3,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_DMA = 4,\n\tPGALLOC_DMA32 = 5,\n\tPGALLOC_NORMAL = 6,\n\tPGALLOC_MOVABLE = 7,\n\tALLOCSTALL_DMA = 8,\n\tALLOCSTALL_DMA32 = 9,\n\tALLOCSTALL_NORMAL = 10,\n\tALLOCSTALL_MOVABLE = 11,\n\tPGSCAN_SKIP_DMA = 12,\n\tPGSCAN_SKIP_DMA32 = 13,\n\tPGSCAN_SKIP_NORMAL = 14,\n\tPGSCAN_SKIP_MOVABLE = 15,\n\tPGFREE = 16,\n\tPGACTIVATE = 17,\n\tPGDEACTIVATE = 18,\n\tPGLAZYFREE = 19,\n\tPGFAULT = 20,\n\tPGMAJFAULT = 21,\n\tPGLAZYFREED = 22,\n\tPGREFILL = 23,\n\tPGREUSE = 24,\n\tPGSTEAL_KSWAPD = 25,\n\tPGSTEAL_DIRECT = 26,\n\tPGSTEAL_KHUGEPAGED = 27,\n\tPGSTEAL_PROACTIVE = 28,\n\tPGSCAN_KSWAPD = 29,\n\tPGSCAN_DIRECT = 30,\n\tPGSCAN_KHUGEPAGED = 31,\n\tPGSCAN_PROACTIVE = 32,\n\tPGSCAN_DIRECT_THROTTLE = 33,\n\tPGSCAN_ANON = 34,\n\tPGSCAN_FILE = 35,\n\tPGSTEAL_ANON = 36,\n\tPGSTEAL_FILE = 37,\n\tPGSCAN_ZONE_RECLAIM_SUCCESS = 38,\n\tPGSCAN_ZONE_RECLAIM_FAILED = 39,\n\tPGINODESTEAL = 40,\n\tSLABS_SCANNED = 41,\n\tKSWAPD_INODESTEAL = 42,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 43,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 44,\n\tPAGEOUTRUN = 45,\n\tPGROTATED = 46,\n\tDROP_PAGECACHE = 47,\n\tDROP_SLAB = 48,\n\tOOM_KILL = 49,\n\tNUMA_PTE_UPDATES = 50,\n\tNUMA_HUGE_PTE_UPDATES = 51,\n\tNUMA_HINT_FAULTS = 52,\n\tNUMA_HINT_FAULTS_LOCAL = 53,\n\tNUMA_PAGE_MIGRATE = 54,\n\tPGMIGRATE_SUCCESS = 55,\n\tPGMIGRATE_FAIL = 56,\n\tTHP_MIGRATION_SUCCESS = 57,\n\tTHP_MIGRATION_FAIL = 58,\n\tTHP_MIGRATION_SPLIT = 59,\n\tCOMPACTMIGRATE_SCANNED = 60,\n\tCOMPACTFREE_SCANNED = 61,\n\tCOMPACTISOLATED = 62,\n\tCOMPACTSTALL = 63,\n\tCOMPACTFAIL = 64,\n\tCOMPACTSUCCESS = 65,\n\tKCOMPACTD_WAKE = 66,\n\tKCOMPACTD_MIGRATE_SCANNED = 67,\n\tKCOMPACTD_FREE_SCANNED = 68,\n\tHTLB_BUDDY_PGALLOC = 69,\n\tHTLB_BUDDY_PGALLOC_FAIL = 70,\n\tUNEVICTABLE_PGCULLED = 71,\n\tUNEVICTABLE_PGSCANNED = 72,\n\tUNEVICTABLE_PGRESCUED = 73,\n\tUNEVICTABLE_PGMLOCKED = 74,\n\tUNEVICTABLE_PGMUNLOCKED = 75,\n\tUNEVICTABLE_PGCLEARED = 76,\n\tUNEVICTABLE_PGSTRANDED = 77,\n\tSWAP_RA = 78,\n\tSWAP_RA_HIT = 79,\n\tSWPIN_ZERO = 80,\n\tSWPOUT_ZERO = 81,\n\tDIRECT_MAP_LEVEL2_SPLIT = 82,\n\tDIRECT_MAP_LEVEL3_SPLIT = 83,\n\tDIRECT_MAP_LEVEL2_COLLAPSE = 84,\n\tDIRECT_MAP_LEVEL3_COLLAPSE = 85,\n\tKSTACK_1K = 86,\n\tKSTACK_2K = 87,\n\tKSTACK_4K = 88,\n\tKSTACK_8K = 89,\n\tKSTACK_16K = 90,\n\tNR_VM_EVENT_ITEMS = 91,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vma_resv_mode {\n\tVMA_NEEDS_RESV = 0,\n\tVMA_COMMIT_RESV = 1,\n\tVMA_END_RESV = 2,\n\tVMA_ADD_RESV = 3,\n\tVMA_DEL_RESV = 4,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum vmscape_mitigations {\n\tVMSCAPE_MITIGATION_NONE = 0,\n\tVMSCAPE_MITIGATION_AUTO = 1,\n\tVMSCAPE_MITIGATION_IBPB_EXIT_TO_USER = 2,\n\tVMSCAPE_MITIGATION_IBPB_ON_VMEXIT = 3,\n};\n\nenum vmx_feature_leafs {\n\tMISC_FEATURES = 0,\n\tPRIMARY_CTLS = 1,\n\tSECONDARY_CTLS = 2,\n\tTERTIARY_CTLS_LOW = 3,\n\tTERTIARY_CTLS_HIGH = 4,\n\tNR_VMX_FEATURE_WORDS = 5,\n};\n\nenum vmx_l1d_flush_state {\n\tVMENTER_L1D_FLUSH_AUTO = 0,\n\tVMENTER_L1D_FLUSH_NEVER = 1,\n\tVMENTER_L1D_FLUSH_COND = 2,\n\tVMENTER_L1D_FLUSH_ALWAYS = 3,\n\tVMENTER_L1D_FLUSH_EPT_DISABLED = 4,\n\tVMENTER_L1D_FLUSH_NOT_REQUIRED = 5,\n};\n\nenum vp_vq_vector_policy {\n\tVP_VQ_VECTOR_POLICY_EACH = 0,\n\tVP_VQ_VECTOR_POLICY_SHARED_SLOW = 1,\n\tVP_VQ_VECTOR_POLICY_SHARED = 2,\n};\n\nenum vq_layout {\n\tVQ_LAYOUT_SPLIT = 0,\n\tVQ_LAYOUT_PACKED = 1,\n\tVQ_LAYOUT_SPLIT_IN_ORDER = 2,\n\tVQ_LAYOUT_PACKED_IN_ORDER = 3,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum wd_read_status {\n\tWD_READ_SUCCESS = 0,\n\tWD_READ_UNSTABLE = 1,\n\tWD_READ_SKIP = 2,\n};\n\nenum which_selector {\n\tFS = 0,\n\tGS = 1,\n};\n\nenum why_no_delegation4 {\n\tWND4_NOT_WANTED = 0,\n\tWND4_CONTENTION = 1,\n\tWND4_RESOURCE = 2,\n\tWND4_NOT_SUPP_FTYPE = 3,\n\tWND4_WRITE_DELEG_NOT_SUPP_FTYPE = 4,\n\tWND4_NOT_SUPP_UPGRADE = 5,\n\tWND4_NOT_SUPP_DOWNGRADE = 6,\n\tWND4_CANCELLED = 7,\n\tWND4_IS_DIR = 8,\n};\n\nenum wiphy_bss_param_flags {\n\tWIPHY_BSS_PARAM_CTS_PROT = 1,\n\tWIPHY_BSS_PARAM_SHORT_PREAMBLE = 2,\n\tWIPHY_BSS_PARAM_SHORT_SLOT_TIME = 4,\n\tWIPHY_BSS_PARAM_BASIC_RATES = 8,\n\tWIPHY_BSS_PARAM_AP_ISOLATE = 16,\n\tWIPHY_BSS_PARAM_HT_OPMODE = 32,\n\tWIPHY_BSS_PARAM_P2P_CTWINDOW = 64,\n\tWIPHY_BSS_PARAM_P2P_OPPPS = 128,\n};\n\nenum wiphy_flags {\n\tWIPHY_FLAG_SUPPORTS_EXT_KEK_KCK = 1,\n\tWIPHY_FLAG_SUPPORTS_MLO = 2,\n\tWIPHY_FLAG_SPLIT_SCAN_6GHZ = 4,\n\tWIPHY_FLAG_NETNS_OK = 8,\n\tWIPHY_FLAG_PS_ON_BY_DEFAULT = 16,\n\tWIPHY_FLAG_4ADDR_AP = 32,\n\tWIPHY_FLAG_4ADDR_STATION = 64,\n\tWIPHY_FLAG_CONTROL_PORT_PROTOCOL = 128,\n\tWIPHY_FLAG_IBSS_RSN = 256,\n\tWIPHY_FLAG_DISABLE_WEXT = 512,\n\tWIPHY_FLAG_MESH_AUTH = 1024,\n\tWIPHY_FLAG_SUPPORTS_EXT_KCK_32 = 2048,\n\tWIPHY_FLAG_SUPPORTS_NSTR_NONPRIMARY = 4096,\n\tWIPHY_FLAG_SUPPORTS_FW_ROAM = 8192,\n\tWIPHY_FLAG_AP_UAPSD = 16384,\n\tWIPHY_FLAG_SUPPORTS_TDLS = 32768,\n\tWIPHY_FLAG_TDLS_EXTERNAL_SETUP = 65536,\n\tWIPHY_FLAG_HAVE_AP_SME = 131072,\n\tWIPHY_FLAG_REPORTS_OBSS = 262144,\n\tWIPHY_FLAG_AP_PROBE_RESP_OFFLOAD = 524288,\n\tWIPHY_FLAG_OFFCHAN_TX = 1048576,\n\tWIPHY_FLAG_HAS_REMAIN_ON_CHANNEL = 2097152,\n\tWIPHY_FLAG_SUPPORTS_5_10_MHZ = 4194304,\n\tWIPHY_FLAG_HAS_CHANNEL_SWITCH = 8388608,\n\tWIPHY_FLAG_NOTIFY_REGDOM_BY_DRIVER = 16777216,\n\tWIPHY_FLAG_CHANNEL_CHANGE_ON_BEACON = 33554432,\n};\n\nenum wiphy_nan_flags {\n\tWIPHY_NAN_FLAGS_CONFIGURABLE_SYNC = 1,\n\tWIPHY_NAN_FLAGS_USERSPACE_DE = 2,\n};\n\nenum wiphy_opmode_flag {\n\tSTA_OPMODE_MAX_BW_CHANGED = 1,\n\tSTA_OPMODE_SMPS_MODE_CHANGED = 2,\n\tSTA_OPMODE_N_SS_CHANGED = 4,\n};\n\nenum wiphy_params_flags {\n\tWIPHY_PARAM_RETRY_SHORT = 1,\n\tWIPHY_PARAM_RETRY_LONG = 2,\n\tWIPHY_PARAM_FRAG_THRESHOLD = 4,\n\tWIPHY_PARAM_RTS_THRESHOLD = 8,\n\tWIPHY_PARAM_COVERAGE_CLASS = 16,\n\tWIPHY_PARAM_DYN_ACK = 32,\n\tWIPHY_PARAM_TXQ_LIMIT = 64,\n\tWIPHY_PARAM_TXQ_MEMORY_LIMIT = 128,\n\tWIPHY_PARAM_TXQ_QUANTUM = 256,\n};\n\nenum wiphy_vendor_command_flags {\n\tWIPHY_VENDOR_CMD_NEED_WDEV = 1,\n\tWIPHY_VENDOR_CMD_NEED_NETDEV = 2,\n\tWIPHY_VENDOR_CMD_NEED_RUNNING = 4,\n};\n\nenum wiphy_wowlan_support_flags {\n\tWIPHY_WOWLAN_ANY = 1,\n\tWIPHY_WOWLAN_MAGIC_PKT = 2,\n\tWIPHY_WOWLAN_DISCONNECT = 4,\n\tWIPHY_WOWLAN_SUPPORTS_GTK_REKEY = 8,\n\tWIPHY_WOWLAN_GTK_REKEY_FAILURE = 16,\n\tWIPHY_WOWLAN_EAP_IDENTITY_REQ = 32,\n\tWIPHY_WOWLAN_4WAY_HANDSHAKE = 64,\n\tWIPHY_WOWLAN_RFKILL_RELEASE = 128,\n\tWIPHY_WOWLAN_NET_DETECT = 256,\n};\n\nenum wmi_brightness_method {\n\tWMI_BRIGHTNESS_METHOD_LEVEL = 1,\n\tWMI_BRIGHTNESS_METHOD_SOURCE = 2,\n\tWMI_BRIGHTNESS_METHOD_MAX = 3,\n};\n\nenum wmi_brightness_mode {\n\tWMI_BRIGHTNESS_MODE_GET = 0,\n\tWMI_BRIGHTNESS_MODE_SET = 1,\n\tWMI_BRIGHTNESS_MODE_GET_MAX_LEVEL = 2,\n\tWMI_BRIGHTNESS_MODE_MAX = 3,\n};\n\nenum wmi_brightness_source {\n\tWMI_BRIGHTNESS_SOURCE_GPU = 1,\n\tWMI_BRIGHTNESS_SOURCE_EC = 2,\n\tWMI_BRIGHTNESS_SOURCE_AUX = 3,\n\tWMI_BRIGHTNESS_SOURCE_MAX = 4,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 43,\n\tWORK_OFFQ_POOL_BITS = 31,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 300000,\n\tMAYDAY_INITIAL_TIMEOUT = 10,\n\tMAYDAY_INTERVAL = 100,\n\tCREATE_COOLDOWN = 1000,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 64,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum x509_actions {\n\tACT_x509_extract_key_data = 0,\n\tACT_x509_extract_name_segment = 1,\n\tACT_x509_note_OID = 2,\n\tACT_x509_note_issuer = 3,\n\tACT_x509_note_not_after = 4,\n\tACT_x509_note_not_before = 5,\n\tACT_x509_note_params = 6,\n\tACT_x509_note_serial = 7,\n\tACT_x509_note_sig_algo = 8,\n\tACT_x509_note_signature = 9,\n\tACT_x509_note_subject = 10,\n\tACT_x509_note_tbs_certificate = 11,\n\tACT_x509_process_extension = 12,\n\tNR__x509_actions = 13,\n};\n\nenum x509_akid_actions {\n\tACT_x509_akid_note_kid = 0,\n\tACT_x509_akid_note_name = 1,\n\tACT_x509_akid_note_serial = 2,\n\tACT_x509_extract_name_segment___2 = 3,\n\tACT_x509_note_OID___2 = 4,\n\tNR__x509_akid_actions = 5,\n};\n\nenum x86_hardware_subarch {\n\tX86_SUBARCH_PC = 0,\n\tX86_SUBARCH_LGUEST = 1,\n\tX86_SUBARCH_XEN = 2,\n\tX86_SUBARCH_INTEL_MID = 3,\n\tX86_SUBARCH_CE4100 = 4,\n\tX86_NR_SUBARCHS = 5,\n};\n\nenum x86_hypervisor_type {\n\tX86_HYPER_NATIVE = 0,\n\tX86_HYPER_VMWARE = 1,\n\tX86_HYPER_MS_HYPERV = 2,\n\tX86_HYPER_XEN_PV = 3,\n\tX86_HYPER_XEN_HVM = 4,\n\tX86_HYPER_KVM = 5,\n\tX86_HYPER_JAILHOUSE = 6,\n\tX86_HYPER_ACRN = 7,\n\tX86_HYPER_BHYVE = 8,\n};\n\nenum x86_intercept_stage;\n\nenum x86_legacy_i8042_state {\n\tX86_LEGACY_I8042_PLATFORM_ABSENT = 0,\n\tX86_LEGACY_I8042_FIRMWARE_ABSENT = 1,\n\tX86_LEGACY_I8042_EXPECTED_PRESENT = 2,\n};\n\nenum x86_pf_error_code {\n\tX86_PF_PROT = 1,\n\tX86_PF_WRITE = 2,\n\tX86_PF_USER = 4,\n\tX86_PF_RSVD = 8,\n\tX86_PF_INSTR = 16,\n\tX86_PF_PK = 32,\n\tX86_PF_SHSTK = 64,\n\tX86_PF_SGX = 32768,\n\tX86_PF_RMP = 2147483648,\n};\n\nenum x86_regset_32 {\n\tREGSET32_GENERAL = 0,\n\tREGSET32_FP = 1,\n\tREGSET32_XFP = 2,\n\tREGSET32_XSTATE = 3,\n\tREGSET32_TLS = 4,\n\tREGSET32_IOPERM = 5,\n};\n\nenum x86_regset_64 {\n\tREGSET64_GENERAL = 0,\n\tREGSET64_FP = 1,\n\tREGSET64_IOPERM = 2,\n\tREGSET64_XSTATE = 3,\n\tREGSET64_SSP = 4,\n};\n\nenum x86_topology_cpu_type {\n\tTOPO_CPU_TYPE_PERFORMANCE = 0,\n\tTOPO_CPU_TYPE_EFFICIENCY = 1,\n\tTOPO_CPU_TYPE_UNKNOWN = 2,\n};\n\nenum x86_topology_domains {\n\tTOPO_SMT_DOMAIN = 0,\n\tTOPO_CORE_DOMAIN = 1,\n\tTOPO_MODULE_DOMAIN = 2,\n\tTOPO_TILE_DOMAIN = 3,\n\tTOPO_DIE_DOMAIN = 4,\n\tTOPO_DIEGRP_DOMAIN = 5,\n\tTOPO_PKG_DOMAIN = 6,\n\tTOPO_MAX_DOMAIN = 7,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xfeature {\n\tXFEATURE_FP = 0,\n\tXFEATURE_SSE = 1,\n\tXFEATURE_YMM = 2,\n\tXFEATURE_BNDREGS = 3,\n\tXFEATURE_BNDCSR = 4,\n\tXFEATURE_OPMASK = 5,\n\tXFEATURE_ZMM_Hi256 = 6,\n\tXFEATURE_Hi16_ZMM = 7,\n\tXFEATURE_PT_UNIMPLEMENTED_SO_FAR = 8,\n\tXFEATURE_PKRU = 9,\n\tXFEATURE_PASID = 10,\n\tXFEATURE_CET_USER = 11,\n\tXFEATURE_CET_KERNEL = 12,\n\tXFEATURE_RSRVD_COMP_13 = 13,\n\tXFEATURE_RSRVD_COMP_14 = 14,\n\tXFEATURE_LBR = 15,\n\tXFEATURE_RSRVD_COMP_16 = 16,\n\tXFEATURE_XTILE_CFG = 17,\n\tXFEATURE_XTILE_DATA = 18,\n\tXFEATURE_APX = 19,\n\tXFEATURE_MAX = 20,\n};\n\nenum xfer_buf_dir {\n\tTO_XFER_BUF = 0,\n\tFROM_XFER_BUF = 1,\n};\n\nenum xfrm_ae_ftype_t {\n\tXFRM_AE_UNSPEC = 0,\n\tXFRM_AE_RTHR = 1,\n\tXFRM_AE_RVAL = 2,\n\tXFRM_AE_LVAL = 4,\n\tXFRM_AE_ETHR = 8,\n\tXFRM_AE_CR = 16,\n\tXFRM_AE_CE = 32,\n\tXFRM_AE_CU = 64,\n\t__XFRM_AE_MAX = 65,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_nlgroups {\n\tXFRMNLGRP_NONE = 0,\n\tXFRMNLGRP_ACQUIRE = 1,\n\tXFRMNLGRP_EXPIRE = 2,\n\tXFRMNLGRP_SA = 3,\n\tXFRMNLGRP_POLICY = 4,\n\tXFRMNLGRP_AEVENTS = 5,\n\tXFRMNLGRP_REPORT = 6,\n\tXFRMNLGRP_MIGRATE = 7,\n\tXFRMNLGRP_MAPPING = 8,\n\t__XFRMNLGRP_MAX = 9,\n};\n\nenum xfrm_pol_inexact_candidate_type {\n\tXFRM_POL_CAND_BOTH = 0,\n\tXFRM_POL_CAND_SADDR = 1,\n\tXFRM_POL_CAND_DADDR = 2,\n\tXFRM_POL_CAND_ANY = 3,\n\tXFRM_POL_CAND_MAX = 4,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xfrm_sa_dir {\n\tXFRM_SA_DIR_IN = 1,\n\tXFRM_SA_DIR_OUT = 2,\n};\n\nenum xfrm_sadattr_type_t {\n\tXFRMA_SAD_UNSPEC = 0,\n\tXFRMA_SAD_CNT = 1,\n\tXFRMA_SAD_HINFO = 2,\n\t__XFRMA_SAD_MAX = 3,\n};\n\nenum xfrm_spdattr_type_t {\n\tXFRMA_SPD_UNSPEC = 0,\n\tXFRMA_SPD_INFO = 1,\n\tXFRMA_SPD_HINFO = 2,\n\tXFRMA_SPD_IPV4_HTHRESH = 3,\n\tXFRMA_SPD_IPV6_HTHRESH = 4,\n\t__XFRMA_SPD_MAX = 5,\n};\n\nenum xhci_cancelled_td_status {\n\tTD_DIRTY = 0,\n\tTD_HALTED = 1,\n\tTD_CLEARING_CACHE = 2,\n\tTD_CLEARING_CACHE_DEFERRED = 3,\n\tTD_CLEARED = 4,\n};\n\nenum xhci_ep_reset_type {\n\tEP_HARD_RESET = 0,\n\tEP_SOFT_RESET = 1,\n};\n\nenum xhci_overhead_type {\n\tLS_OVERHEAD_TYPE = 0,\n\tFS_OVERHEAD_TYPE = 1,\n\tHS_OVERHEAD_TYPE = 2,\n};\n\nenum xhci_ring_type {\n\tTYPE_CTRL = 0,\n\tTYPE_ISOC = 1,\n\tTYPE_BULK = 2,\n\tTYPE_INTR = 3,\n\tTYPE_STREAM = 4,\n\tTYPE_COMMAND = 5,\n\tTYPE_EVENT = 6,\n};\n\nenum xhci_setup_dev {\n\tSETUP_CONTEXT_ONLY = 0,\n\tSETUP_CONTEXT_ADDRESS = 1,\n};\n\nenum xhci_sideband_notify_type {\n\tXHCI_SIDEBAND_XFER_RING_FREE = 0,\n};\n\nenum xhci_sideband_type {\n\tXHCI_SIDEBAND_AUDIO = 0,\n\tXHCI_SIDEBAND_VENDOR = 1,\n};\n\nenum xprt_transports {\n\tXPRT_TRANSPORT_UDP = 17,\n\tXPRT_TRANSPORT_TCP = 6,\n\tXPRT_TRANSPORT_BC_TCP = -2147483642,\n\tXPRT_TRANSPORT_RDMA = 256,\n\tXPRT_TRANSPORT_BC_RDMA = -2147483392,\n\tXPRT_TRANSPORT_LOCAL = 257,\n\tXPRT_TRANSPORT_TCP_TLS = 258,\n};\n\nenum xprt_xid_rb_cmp {\n\tXID_RB_EQUAL = 0,\n\tXID_RB_LEFT = 1,\n\tXID_RB_RIGHT = 2,\n};\n\nenum xprtsec_policies {\n\tRPC_XPRTSEC_NONE = 0,\n\tRPC_XPRTSEC_TLS_ANON = 1,\n\tRPC_XPRTSEC_TLS_X509 = 2,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xstate_copy_mode {\n\tXSTATE_COPY_FP = 0,\n\tXSTATE_COPY_FX = 1,\n\tXSTATE_COPY_XSAVE = 2,\n};\n\nenum xt_policy_flags {\n\tXT_POLICY_MATCH_IN = 1,\n\tXT_POLICY_MATCH_OUT = 2,\n\tXT_POLICY_MATCH_NONE = 4,\n\tXT_POLICY_MATCH_STRICT = 8,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum yukon_ec_rev {\n\tCHIP_REV_YU_EC_A1 = 0,\n\tCHIP_REV_YU_EC_A2 = 1,\n\tCHIP_REV_YU_EC_A3 = 2,\n};\n\nenum yukon_ec_u_rev {\n\tCHIP_REV_YU_EC_U_A0 = 1,\n\tCHIP_REV_YU_EC_U_A1 = 2,\n\tCHIP_REV_YU_EC_U_B0 = 3,\n\tCHIP_REV_YU_EC_U_B1 = 5,\n};\n\nenum yukon_ex_rev {\n\tCHIP_REV_YU_EX_A0 = 1,\n\tCHIP_REV_YU_EX_B0 = 2,\n};\n\nenum yukon_fe_p_rev {\n\tCHIP_REV_YU_FE2_A0 = 0,\n};\n\nenum yukon_prm_rev {\n\tCHIP_REV_YU_PRM_Z1 = 1,\n\tCHIP_REV_YU_PRM_A0 = 2,\n};\n\nenum yukon_supr_rev {\n\tCHIP_REV_YU_SU_A0 = 0,\n\tCHIP_REV_YU_SU_B0 = 1,\n\tCHIP_REV_YU_SU_B1 = 3,\n};\n\nenum yukon_xl_rev {\n\tCHIP_REV_YU_XL_A0 = 0,\n\tCHIP_REV_YU_XL_A1 = 1,\n\tCHIP_REV_YU_XL_A2 = 2,\n\tCHIP_REV_YU_XL_A3 = 3,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_FREE_CMA_PAGES = 9,\n\tNR_VM_ZONE_STAT_ITEMS = 10,\n};\n\nenum zone_type {\n\tZONE_DMA = 0,\n\tZONE_DMA32 = 1,\n\tZONE_NORMAL = 2,\n\tZONE_MOVABLE = 3,\n\t__MAX_NR_ZONES = 4,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\ntypedef _Bool bool;\n\ntypedef __int128 unsigned __u128;\n\ntypedef __u128 u128;\n\ntypedef u128 freelist_full_t;\n\ntypedef char __pad_after_uframe[0];\n\ntypedef char __pad_before_u32[0];\n\ntypedef char __pad_before_uframe[0];\n\ntypedef char acpi_bus_id[8];\n\ntypedef char acpi_device_class[20];\n\ntypedef char acpi_device_name[40];\n\ntypedef char *acpi_string;\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_daddr_t;\n\ntypedef int __kernel_ipc_pid_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_mqd_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __s32;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef __s32 s32;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_daddr_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_key_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_off_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef s32 dma_cookie_t;\n\ntypedef int ext4_grpblk_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef int initcall_entry_t;\n\ntypedef int insn_value_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef int mm_id_mapcount_t;\n\ntypedef int mpi_size_t;\n\ntypedef __kernel_mqd_t mqd_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef __s32 sctp_assoc_t;\n\ntypedef int snd_ctl_elem_iface_t;\n\ntypedef int snd_ctl_elem_type_t;\n\ntypedef int snd_pcm_access_t;\n\ntypedef int snd_pcm_format_t;\n\ntypedef int snd_pcm_hw_param_t;\n\ntypedef int snd_pcm_state_t;\n\ntypedef int snd_pcm_subformat_t;\n\ntypedef int snd_seq_client_type_t;\n\ntypedef int suspend_state_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef const int tracepoint_ptr_t;\n\ntypedef int vma_flag_t;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_long_t __kernel_ptrdiff_t;\n\ntypedef __kernel_long_t __kernel_ssize_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef long int mpi_limb_signed_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef long int snd_pcm_sframes_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 Elf64_Sxword;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef __s64 s64;\n\ntypedef s64 compat_loff_t;\n\ntypedef s64 int64_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef long long int qsize_t;\n\ntypedef __s64 time64_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef __u64 __virtio64;\n\ntypedef u64 acpi_bus_address;\n\ntypedef u64 acpi_integer;\n\ntypedef u64 acpi_io_address;\n\ntypedef u64 acpi_physical_address;\n\ntypedef u64 acpi_size;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 clientid4;\n\ntypedef u64 compat_u64;\n\ntypedef long long unsigned int cycles_t;\n\ntypedef u64 dma_addr_t;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef u64 gen8_pte_t;\n\ntypedef u64 gfn_t;\n\ntypedef u64 gpa_t;\n\ntypedef u64 hfn_t;\n\ntypedef u64 hpa_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef hfn_t kvm_pfn_t;\n\ntypedef long long unsigned int llu;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 pci_bus_addr_t;\n\ntypedef u64 phys_addr_t;\n\ntypedef u64 pt_oaddr_t;\n\ntypedef u64 pt_vaddr_t;\n\ntypedef u64 sector_t;\n\ntypedef sector_t region_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u64 sci_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef u64 u_int64_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef u64 upf_t;\n\ntypedef uint64_t vli_type;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef __kernel_ulong_t __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef long unsigned int mpi_limb_t;\n\ntypedef mpi_limb_t UWtype;\n\ntypedef long unsigned int __kernel_old_dev_t;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int efi_status_t;\n\ntypedef long unsigned int elf_greg_t;\n\ntypedef elf_greg_t elf_gregset_t[27];\n\ntypedef long unsigned int gva_t;\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int kimage_entry_t;\n\ntypedef long unsigned int mce_banks_t[1];\n\ntypedef mpi_limb_t *mpi_ptr_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int old_sigset_t;\n\ntypedef long unsigned int p4dval_t;\n\ntypedef long unsigned int perf_trace_t[1024];\n\ntypedef long unsigned int pgdval_t;\n\ntypedef long unsigned int pgprotval_t;\n\ntypedef long unsigned int pmdval_t;\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int pteval_t;\n\ntypedef long unsigned int pudval_t;\n\ntypedef long unsigned int snd_pcm_uframes_t;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int u_long;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulg;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef short unsigned int ush;\n\ntypedef ush Pos;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef u16 __compat_gid_t;\n\ntypedef u16 __compat_uid_t;\n\ntypedef __u16 __hc16;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef short unsigned int __kernel_old_gid_t;\n\ntypedef short unsigned int __kernel_old_uid_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef u16 acpi_owner_id;\n\ntypedef u16 acpi_rs_length;\n\ntypedef __u16 bitmap_counter_t;\n\ntypedef u16 blk_short_t;\n\ntypedef __u16 comp_t;\n\ntypedef u16 compat_dev_t;\n\ntypedef u16 compat_ipc_pid_t;\n\ntypedef u16 compat_mode_t;\n\ntypedef u16 compat_nlink_t;\n\ntypedef u16 compat_ushort_t;\n\ntypedef u16 efi_char16_t;\n\ntypedef __kernel_gid16_t gid16_t;\n\ntypedef u16 hda_nid_t;\n\ntypedef __kernel_old_gid_t old_gid_t;\n\ntypedef __kernel_old_uid_t old_uid_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef u16 u_int16_t;\n\ntypedef short unsigned int u_short;\n\ntypedef u16 ucs2_char_t;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef short unsigned int vifi_t;\n\ntypedef u16 wchar_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 acpi_adr_space_type;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef unsigned char cisdata_t;\n\ntypedef u8 dscp_t;\n\ntypedef __u8 dvd_challenge[10];\n\ntypedef __u8 dvd_key[5];\n\ntypedef u8 efi_bool_t;\n\ntypedef unsigned char insn_byte_t;\n\ntypedef u8 kprobe_opcode_t;\n\ntypedef __u8 mtrr_type;\n\ntypedef u8 retpoline_thunk_t[32];\n\ntypedef unsigned char snd_seq_event_type_t;\n\ntypedef unsigned char u8___2;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef unsigned char uch;\n\ntypedef u8 uprobe_opcode_t;\n\ntypedef __u8 virtio_net_ctrl_ack;\n\ntypedef unsigned int __u32;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef __u32 u32;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef unsigned int IPos;\n\ntypedef unsigned int OM_uint32;\n\ntypedef unsigned int UHWtype;\n\ntypedef __u32 __be32;\n\ntypedef u32 __compat_gid32_t;\n\ntypedef u32 __compat_uid32_t;\n\ntypedef __u32 __hc32;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_gid_t;\n\ntypedef unsigned int __kernel_mode_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __virtio32;\n\ntypedef __u32 __wsum;\n\ntypedef u32 acpi_event_status;\n\ntypedef u32 acpi_mutex_handle;\n\ntypedef u32 acpi_name;\n\ntypedef u32 acpi_object_type;\n\ntypedef u32 acpi_rsdesc_size;\n\ntypedef u32 acpi_status;\n\ntypedef unsigned int autofs_wqt_t;\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef u32 codel_time_t;\n\ntypedef __u32 comp2_t;\n\ntypedef u32 compat_aio_context_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_ino_t;\n\ntypedef u32 compat_old_sigset_t;\n\ntypedef u32 compat_sigset_word;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef u32 depot_flags_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef uint32_t drbg_flag_t;\n\ntypedef unsigned int drm_magic_t;\n\ntypedef u32 errseq_t;\n\ntypedef unsigned int ext4_group_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef u32 gen6_pte_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef unsigned int ieee80211_rx_result;\n\ntypedef unsigned int ieee80211_tx_result;\n\ntypedef unsigned int insn_attr_t;\n\ntypedef u32 intel_engine_mask_t;\n\ntypedef unsigned int ioasid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef unsigned int mm_id_t;\n\ntypedef __kernel_mode_t mode_t;\n\ntypedef u32 nlink_t;\n\ntypedef u32 note_buf_t[92];\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef u32 phys_cpuid_t;\n\ntypedef unsigned int pipe_index_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef __kernel_uid32_t qid_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef u32 rpc_authflavor_t;\n\ntypedef __be32 rpc_fraghdr;\n\ntypedef unsigned int sk_buff_data_t;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int snd_seq_tick_time_t;\n\ntypedef unsigned int speed_t;\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int tid_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef u32 u_int32_t;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef unsigned int upstat_t;\n\ntypedef u32 usb_port_location_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\nstruct buffer_head;\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct dentry;\n\nstruct file;\n\ntypedef struct {\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tint offset;\n\tint size;\n\tchar *magic;\n\tchar *mask;\n\tconst char *interpreter;\n\tchar *name;\n\tstruct dentry *dentry;\n\tstruct file *interp_file;\n\trefcount_t users;\n} Node;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef struct {\n\tU32 f1c;\n\tU32 f1d;\n\tU32 f7b;\n\tU32 f7c;\n} ZSTD_cpuid_t;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tlong unsigned int fds_bits[16];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef union {\n} aes_encrypt_arg;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef atomic64_t atomic_long_t;\n\ntypedef struct {\n\t__be64 a;\n\t__be64 b;\n} be128;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\traw_spinlock_t *lock2;\n} class_double_raw_spinlock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_jump_label_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_init_t;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\nstruct snd_pcm_substream;\n\ntypedef struct {\n\tstruct snd_pcm_substream *lock;\n} class_pcm_stream_lock_irq_t;\n\ntypedef struct {\n\tstruct snd_pcm_substream *lock;\n\tlong unsigned int flags;\n} class_pcm_stream_lock_irqsave_t;\n\nstruct perf_cpu_context;\n\nstruct perf_event_context;\n\ntypedef struct {\n\tstruct perf_cpu_context *cpuctx;\n\tstruct perf_event_context *ctx;\n} class_perf_ctx_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_notrace_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\nstruct srcu_ctr;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tstruct srcu_ctr *scp;\n} class_srcu_fast_notrace_t;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\nstruct uart_port;\n\ntypedef struct {\n\tstruct uart_port *lock;\n\tlong unsigned int flags;\n} class_uart_port_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_write_lock_irqsave_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef __kernel_fsid_t compat_fsid_t;\n\ntypedef struct {\n\tcompat_sigset_word sig[2];\n} compat_sigset_t;\n\ntypedef struct {\n\t__be16 disc_information_length;\n\t__u8 disc_status: 2;\n\t__u8 border_status: 2;\n\t__u8 erasable: 1;\n\t__u8 reserved1: 3;\n\t__u8 n_first_track;\n\t__u8 n_sessions_lsb;\n\t__u8 first_track_lsb;\n\t__u8 last_track_lsb;\n\t__u8 mrw_status: 2;\n\t__u8 dbit: 1;\n\t__u8 reserved2: 2;\n\t__u8 uru: 1;\n\t__u8 dbc_v: 1;\n\t__u8 did_v: 1;\n\t__u8 disc_type;\n\t__u8 n_sessions_msb;\n\t__u8 first_track_msb;\n\t__u8 last_track_msb;\n\t__u32 disc_id;\n\t__u32 lead_in;\n\t__u32 lead_out;\n\t__u8 disc_bar_code[8];\n\t__u8 reserved3;\n\t__u8 n_opc;\n} disc_information;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\nstruct dvd_lu_send_agid {\n\t__u8 type;\n\tunsigned int agid: 2;\n};\n\nstruct dvd_host_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_send_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key key;\n};\n\nstruct dvd_lu_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_lu_send_title_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key title_key;\n\tint lba;\n\tunsigned int cpm: 1;\n\tunsigned int cp_sec: 1;\n\tunsigned int cgms: 2;\n};\n\nstruct dvd_lu_send_asf {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tunsigned int asf: 1;\n};\n\nstruct dvd_host_send_rpcstate {\n\t__u8 type;\n\t__u8 pdrc;\n};\n\nstruct dvd_lu_send_rpcstate {\n\t__u8 type: 2;\n\t__u8 vra: 3;\n\t__u8 ucca: 3;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_lu_send_agid lsa;\n\tstruct dvd_host_send_challenge hsc;\n\tstruct dvd_send_key lsk;\n\tstruct dvd_lu_send_challenge lsc;\n\tstruct dvd_send_key hsk;\n\tstruct dvd_lu_send_title_key lstk;\n\tstruct dvd_lu_send_asf lsasf;\n\tstruct dvd_host_send_rpcstate hrpcs;\n\tstruct dvd_lu_send_rpcstate lrpcs;\n} dvd_authinfo;\n\nstruct dvd_layer {\n\t__u8 book_version: 4;\n\t__u8 book_type: 4;\n\t__u8 min_rate: 4;\n\t__u8 disc_size: 4;\n\t__u8 layer_type: 4;\n\t__u8 track_path: 1;\n\t__u8 nlayers: 2;\n\tchar: 1;\n\t__u8 track_density: 4;\n\t__u8 linear_density: 4;\n\t__u8 bca: 1;\n\t__u32 start_sector;\n\t__u32 end_sector;\n\t__u32 end_sector_l0;\n};\n\nstruct dvd_physical {\n\t__u8 type;\n\t__u8 layer_num;\n\tstruct dvd_layer layer[4];\n};\n\nstruct dvd_copyright {\n\t__u8 type;\n\t__u8 layer_num;\n\t__u8 cpst;\n\t__u8 rmi;\n};\n\nstruct dvd_disckey {\n\t__u8 type;\n\tunsigned int agid: 2;\n\t__u8 value[2048];\n};\n\nstruct dvd_bca {\n\t__u8 type;\n\tint len;\n\t__u8 value[188];\n};\n\nstruct dvd_manufact {\n\t__u8 type;\n\t__u8 layer_num;\n\tint len;\n\t__u8 value[2048];\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_physical physical;\n\tstruct dvd_copyright copyright;\n\tstruct dvd_disckey disckey;\n\tstruct dvd_bca bca;\n\tstruct dvd_manufact manufact;\n} dvd_struct;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 headersize;\n\tu32 flags;\n\tu32 imagesize;\n} efi_capsule_header_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 table;\n} efi_config_table_32_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu64 table;\n} efi_config_table_64_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_guid_t guid;\n\t\tvoid *table;\n\t};\n\tefi_config_table_32_t mixed_mode;\n} efi_config_table_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tlong unsigned int *ptr;\n\tconst char name[16];\n} efi_config_table_type_t;\n\ntypedef struct {\n\tu32 type;\n\tu32 pad;\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu64 num_pages;\n\tu64 attribute;\n} efi_memory_desc_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 num_entries;\n\tu32 desc_size;\n\tu32 flags;\n\tefi_memory_desc_t entry[0];\n} efi_memory_attributes_table_t;\n\ntypedef struct {\n\tu16 version;\n\tu16 length;\n\tu32 runtime_services_supported;\n} efi_rt_properties_table_t;\n\ntypedef struct {\n\tu64 signature;\n\tu32 revision;\n\tu32 headersize;\n\tu32 crc32;\n\tu32 reserved;\n} efi_table_hdr_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 get_time;\n\tu32 set_time;\n\tu32 get_wakeup_time;\n\tu32 set_wakeup_time;\n\tu32 set_virtual_address_map;\n\tu32 convert_pointer;\n\tu32 get_variable;\n\tu32 get_next_variable;\n\tu32 set_variable;\n\tu32 get_next_high_mono_count;\n\tu32 reset_system;\n\tu32 update_capsule;\n\tu32 query_capsule_caps;\n\tu32 query_variable_info;\n} efi_runtime_services_32_t;\n\ntypedef struct {\n\tu16 year;\n\tu8 month;\n\tu8 day;\n\tu8 hour;\n\tu8 minute;\n\tu8 second;\n\tu8 pad1;\n\tu32 nanosecond;\n\ts16 timezone;\n\tu8 daylight;\n\tu8 pad2;\n} efi_time_t;\n\ntypedef struct {\n\tu32 resolution;\n\tu32 accuracy;\n\tu8 sets_to_zero;\n} efi_time_cap_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tefi_status_t (*get_time)(efi_time_t *, efi_time_cap_t *);\n\t\tefi_status_t (*set_time)(efi_time_t *);\n\t\tefi_status_t (*get_wakeup_time)(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\t\tefi_status_t (*set_wakeup_time)(efi_bool_t, efi_time_t *);\n\t\tefi_status_t (*set_virtual_address_map)(long unsigned int, long unsigned int, u32, efi_memory_desc_t *);\n\t\tvoid *convert_pointer;\n\t\tefi_status_t (*get_variable)(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\t\tefi_status_t (*get_next_variable)(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\t\tefi_status_t (*set_variable)(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\t\tefi_status_t (*get_next_high_mono_count)(u32 *);\n\t\tvoid (*reset_system)(int, efi_status_t, long unsigned int, efi_char16_t *);\n\t\tefi_status_t (*update_capsule)(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\t\tefi_status_t (*query_capsule_caps)(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\t\tefi_status_t (*query_variable_info)(u32, u64 *, u64 *, u64 *);\n\t};\n\tefi_runtime_services_32_t mixed_mode;\n} efi_runtime_services_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 fw_vendor;\n\tu32 fw_revision;\n\tu32 con_in_handle;\n\tu32 con_in;\n\tu32 con_out_handle;\n\tu32 con_out;\n\tu32 stderr_handle;\n\tu32 stderr;\n\tu32 runtime;\n\tu32 boottime;\n\tu32 nr_tables;\n\tu32 tables;\n} efi_system_table_32_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu64 fw_vendor;\n\tu32 fw_revision;\n\tu32 __pad1;\n\tu64 con_in_handle;\n\tu64 con_in;\n\tu64 con_out_handle;\n\tu64 con_out;\n\tu64 stderr_handle;\n\tu64 stderr;\n\tu64 runtime;\n\tu64 boottime;\n\tu32 nr_tables;\n\tu32 __pad2;\n\tu64 tables;\n} efi_system_table_64_t;\n\nunion efi_simple_text_input_protocol;\n\ntypedef union efi_simple_text_input_protocol efi_simple_text_input_protocol_t;\n\nunion efi_simple_text_output_protocol;\n\ntypedef union efi_simple_text_output_protocol efi_simple_text_output_protocol_t;\n\nunion efi_boot_services;\n\ntypedef union efi_boot_services efi_boot_services_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tlong unsigned int fw_vendor;\n\t\tu32 fw_revision;\n\t\tlong unsigned int con_in_handle;\n\t\tefi_simple_text_input_protocol_t *con_in;\n\t\tlong unsigned int con_out_handle;\n\t\tefi_simple_text_output_protocol_t *con_out;\n\t\tlong unsigned int stderr_handle;\n\t\tlong unsigned int stderr;\n\t\tefi_runtime_services_t *runtime;\n\t\tefi_boot_services_t *boottime;\n\t\tlong unsigned int nr_tables;\n\t\tlong unsigned int tables;\n\t};\n\tefi_system_table_32_t mixed_mode;\n} efi_system_table_t;\n\ntypedef struct {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n} ext4_acl_entry;\n\ntypedef struct {\n\t__le32 a_version;\n} ext4_acl_header;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic64_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tu32 reg;\n} i915_mcr_reg_t;\n\ntypedef struct {\n\tu32 reg;\n} i915_reg_t;\n\ntypedef union {\n\tu8 hsw[3];\n\tlong unsigned int xehp[1];\n} intel_sseu_ss_mask_t;\n\ntypedef struct {\n\tunsigned int __nmi_count;\n\tunsigned int apic_timer_irqs;\n\tunsigned int irq_spurious_count;\n\tunsigned int icr_read_retry_count;\n\tunsigned int x86_platform_ipis;\n\tunsigned int apic_perf_irqs;\n\tunsigned int apic_irq_work_irqs;\n\tunsigned int irq_resched_count;\n\tunsigned int irq_call_count;\n\tunsigned int irq_tlb_count;\n\tunsigned int irq_thermal_count;\n\tunsigned int irq_threshold_count;\n\tunsigned int irq_deferred_error_count;\n\tunsigned int irq_hv_callback_count;\n\tlong: 64;\n} irq_cpustat_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\t__le64 b;\n\t__le64 a;\n} le128;\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef struct {\n\tlocal_t a;\n} local64_t;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct qspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tstruct {\n\t\t\tu8 locked;\n\t\t\tu8 pending;\n\t\t};\n\t\tstruct {\n\t\t\tu16 locked_pending;\n\t\t\tu16 tail;\n\t\t};\n\t};\n};\n\ntypedef struct qspinlock arch_spinlock_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n};\n\nstruct ldt_struct;\n\nstruct vdso_image;\n\ntypedef struct {\n\tu64 ctx_id;\n\tatomic64_t tlb_gen;\n\tlong unsigned int next_trim_cpumask;\n\tstruct rw_semaphore ldt_usr_sem;\n\tstruct ldt_struct *ldt;\n\tlong unsigned int flags;\n\tstruct mutex lock;\n\tvoid *vdso;\n\tconst struct vdso_image *vdso_image;\n\tatomic_t perf_rdpmc_allowed;\n\tu16 pkey_allocation_map;\n\ts16 execute_only_pkey;\n\tu16 global_asid;\n\tbool asid_transition;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[1];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tchar data[8];\n} nfs4_verifier;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\ntypedef struct {\n\tp4dval_t p4d;\n} p4d_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\ntypedef struct {\n\tpgdval_t pgd;\n} pgd_t;\n\ntypedef struct {\n\tpmdval_t pmd;\n} pmd_t;\n\ntypedef struct {\n\tlong unsigned int bits[4];\n} pnp_irq_mask_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tpteval_t pte;\n} pte_t;\n\ntypedef struct {\n\tpudval_t pud;\n} pud_t;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\t__u16 report_key_length;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 ucca: 3;\n\t__u8 vra: 3;\n\t__u8 type_code: 2;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n\t__u8 reserved3;\n} rpc_state_t;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[1];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\ntypedef atomic_t snd_use_lock_t;\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\tu32 high;\n\tu32 low;\n} tg3_stat64_t;\n\ntypedef struct {\n\t__be16 track_information_length;\n\t__u8 track_lsb;\n\t__u8 session_lsb;\n\t__u8 reserved1;\n\t__u8 track_mode: 4;\n\t__u8 copy: 1;\n\t__u8 damage: 1;\n\t__u8 reserved2: 2;\n\t__u8 data_mode: 4;\n\t__u8 fp: 1;\n\t__u8 packet: 1;\n\t__u8 blank: 1;\n\t__u8 rt: 1;\n\t__u8 nwa_v: 1;\n\t__u8 lra_v: 1;\n\t__u8 reserved3: 6;\n\t__be32 track_start;\n\t__be32 next_writable;\n\t__be32 free_blocks;\n\t__be32 fixed_packet_size;\n\t__be32 track_size;\n\t__be32 last_rec_address;\n} track_information;\n\ntypedef struct {\n\tint data;\n\tint audio;\n\tint cdi;\n\tint xa;\n\tlong int error;\n} tracktype;\n\ntypedef struct {\n\tlocal64_t v;\n} u64_stats_t;\n\ntypedef struct {\n\tu32 val;\n} uint_fixed_16_16_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_le;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\nunion IO_APIC_reg_00 {\n\tu32 raw;\n\tstruct {\n\t\tu32 __reserved_2: 14;\n\t\tu32 LTS: 1;\n\t\tu32 delivery_type: 1;\n\t\tu32 __reserved_1: 8;\n\t\tu32 ID: 8;\n\t} bits;\n};\n\nunion IO_APIC_reg_01 {\n\tu32 raw;\n\tstruct {\n\t\tu32 version: 8;\n\t\tu32 __reserved_2: 7;\n\t\tu32 PRQ: 1;\n\t\tu32 entries: 8;\n\t\tu32 __reserved_1: 8;\n\t} bits;\n};\n\nunion IO_APIC_reg_02 {\n\tu32 raw;\n\tstruct {\n\t\tu32 __reserved_2: 24;\n\t\tu32 arbitration: 4;\n\t\tu32 __reserved_1: 4;\n\t} bits;\n};\n\nunion IO_APIC_reg_03 {\n\tu32 raw;\n\tstruct {\n\t\tu32 boot_DT: 1;\n\t\tu32 __reserved_1: 31;\n\t} bits;\n};\n\nstruct IO_APIC_route_entry {\n\tunion {\n\t\tstruct {\n\t\t\tu64 vector: 8;\n\t\t\tu64 delivery_mode: 3;\n\t\t\tu64 dest_mode_logical: 1;\n\t\t\tu64 delivery_status: 1;\n\t\t\tu64 active_low: 1;\n\t\t\tu64 irr: 1;\n\t\t\tu64 is_level: 1;\n\t\t\tu64 masked: 1;\n\t\t\tu64 reserved_0: 15;\n\t\t\tu64 reserved_1: 17;\n\t\t\tu64 virt_destid_8_14: 7;\n\t\t\tu64 destid_0_7: 8;\n\t\t};\n\t\tstruct {\n\t\t\tu64 ir_shared_0: 8;\n\t\t\tu64 ir_zero: 3;\n\t\t\tu64 ir_index_15: 1;\n\t\t\tu64 ir_shared_1: 5;\n\t\t\tu64 ir_reserved_0: 31;\n\t\t\tu64 ir_format: 1;\n\t\t\tu64 ir_index_0_14: 15;\n\t\t};\n\t\tstruct {\n\t\t\tu64 w1: 32;\n\t\t\tu64 w2: 32;\n\t\t};\n\t};\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lock_class_key {};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong int privdata[0];\n};\n\nstruct Qdisc_class_common {\n\tu32 classid;\n\tunsigned int filter_cnt;\n\tstruct hlist_node hnode;\n};\n\nstruct hlist_head;\n\nstruct Qdisc_class_hash {\n\tstruct hlist_head *hash;\n\tunsigned int hashsize;\n\tunsigned int hashmask;\n\tunsigned int hashelems;\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct RR_CL_s {\n\t__u8 location[8];\n};\n\nstruct RR_NM_s {\n\t__u8 flags;\n\tchar name[0];\n};\n\nstruct RR_PL_s {\n\t__u8 location[8];\n};\n\nstruct RR_PN_s {\n\t__u8 dev_high[8];\n\t__u8 dev_low[8];\n};\n\nstruct RR_PX_s {\n\t__u8 mode[8];\n\t__u8 n_links[8];\n\t__u8 uid[8];\n\t__u8 gid[8];\n};\n\nstruct RR_RR_s {\n\t__u8 flags[1];\n};\n\nstruct SL_component {\n\t__u8 flags;\n\t__u8 len;\n\t__u8 text[0];\n};\n\nstruct RR_SL_s {\n\t__u8 flags;\n\tstruct SL_component link;\n};\n\nstruct RR_TF_s {\n\t__u8 flags;\n\t__u8 data[0];\n};\n\nstruct RR_ZF_s {\n\t__u8 algorithm[2];\n\t__u8 parms[2];\n\t__u8 real_size[8];\n};\n\nstruct RxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\nstruct SU_CE_s {\n\t__u8 extent[8];\n\t__u8 offset[8];\n\t__u8 size[8];\n};\n\nstruct SU_ER_s {\n\t__u8 len_id;\n\t__u8 len_des;\n\t__u8 len_src;\n\t__u8 ext_ver;\n\t__u8 data[0];\n};\n\nstruct SU_SP_s {\n\t__u8 magic[2];\n\t__u8 skip;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct lockdep_map {};\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool work_in_progress;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tbool smart_suspend: 1;\n\tbool must_resume: 1;\n\tbool may_skip_resume: 1;\n\tbool out_band_wakeup: 1;\n\tbool strict_midlayer: 1;\n\tstruct hrtimer suspend_timer;\n\tu64 timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tbool idle_notification: 1;\n\tbool request_pending: 1;\n\tbool deferred_resume: 1;\n\tbool needs_force_resume: 1;\n\tbool runtime_auto: 1;\n\tbool ignore_children: 1;\n\tbool no_callbacks: 1;\n\tbool irq_safe: 1;\n\tbool use_autosuspend: 1;\n\tbool timer_autosuspends: 1;\n\tbool memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tenum rpm_status last_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct dev_archdata {};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct io_tlb_mem;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct dev_msi_info msi;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct io_tlb_mem *dma_io_tlb_mem;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tint numa_node;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_skip_sync: 1;\n\tbool dma_iommu: 1;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct TxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n};\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tint bmi2;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct fred_cs {\n\tu64 cs: 16;\n\tu64 sl: 2;\n\tu64 wfe: 1;\n};\n\nstruct fred_ss {\n\tu64 ss: 16;\n\tu64 sti: 1;\n\tu64 swevent: 1;\n\tu64 nmi: 1;\n\tint: 13;\n\tu64 vector: 8;\n\tshort: 8;\n\tu64 type: 4;\n\tchar: 4;\n\tu64 enclave: 1;\n\tu64 l: 1;\n\tu64 nested: 1;\n\tchar: 1;\n\tu64 insnlen: 4;\n};\n\nstruct pt_regs {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bp;\n\tlong unsigned int bx;\n\tlong unsigned int r11;\n\tlong unsigned int r10;\n\tlong unsigned int r9;\n\tlong unsigned int r8;\n\tlong unsigned int ax;\n\tlong unsigned int cx;\n\tlong unsigned int dx;\n\tlong unsigned int si;\n\tlong unsigned int di;\n\tlong unsigned int orig_ax;\n\tlong unsigned int ip;\n\tunion {\n\t\tu16 cs;\n\t\tu64 csx;\n\t\tstruct fred_cs fred_cs;\n\t};\n\tlong unsigned int flags;\n\tlong unsigned int sp;\n\tunion {\n\t\tu16 ss;\n\t\tu64 ssx;\n\t\tstruct fred_ss fred_ss;\n\t};\n};\n\nstruct __arch_ftrace_regs {\n\tstruct pt_regs regs;\n};\n\nstruct __arch_relative_insn {\n\tu8 op;\n\ts32 raddr;\n} __attribute__((packed));\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n\tu16 src;\n\tu16 dst;\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct idr;\n\nstruct __class_idr {\n\tstruct idr *idr;\n\tint id;\n};\n\ntypedef struct __class_idr class_idr_alloc_t;\n\nstruct cpumask;\n\nstruct __cmp_key {\n\tconst struct cpumask *cpus;\n\tstruct cpumask ***masks;\n\tint node;\n\tint cpu;\n\tint w;\n};\n\nstruct __compat_aio_sigset {\n\tcompat_uptr_t sigmask;\n\tcompat_size_t sigsetsize;\n};\n\nstruct drm_colorop;\n\nstruct drm_colorop_state;\n\nstruct __drm_colorops_state {\n\tstruct drm_colorop *ptr;\n\tstruct drm_colorop_state *state;\n\tstruct drm_colorop_state *old_state;\n\tstruct drm_colorop_state *new_state;\n};\n\nstruct drm_connector;\n\nstruct drm_connector_state;\n\nstruct __drm_connnectors_state {\n\tstruct drm_connector *ptr;\n\tstruct drm_connector_state *state_to_destroy;\n\tstruct drm_connector_state *old_state;\n\tstruct drm_connector_state *new_state;\n\ts32 *out_fence_ptr;\n};\n\nstruct drm_crtc;\n\nstruct drm_crtc_state;\n\nstruct drm_crtc_commit;\n\nstruct __drm_crtcs_state {\n\tstruct drm_crtc *ptr;\n\tstruct drm_crtc_state *state_to_destroy;\n\tstruct drm_crtc_state *old_state;\n\tstruct drm_crtc_state *new_state;\n\tstruct drm_crtc_commit *commit;\n\ts32 *out_fence_ptr;\n\tu64 last_vblank_count;\n};\n\nstruct drm_plane;\n\nstruct drm_plane_state;\n\nstruct __drm_planes_state {\n\tstruct drm_plane *ptr;\n\tstruct drm_plane_state *state_to_destroy;\n\tstruct drm_plane_state *old_state;\n\tstruct drm_plane_state *new_state;\n};\n\nstruct drm_private_obj;\n\nstruct drm_private_state;\n\nstruct __drm_private_objs_state {\n\tstruct drm_private_obj *ptr;\n\tstruct drm_private_state *state_to_destroy;\n\tstruct drm_private_state *old_state;\n\tstruct drm_private_state *new_state;\n};\n\nstruct __ext_steer_reg {\n\tconst char *name;\n\ti915_mcr_reg_t reg;\n};\n\nstruct __fat_dirent {\n\tlong int d_ino;\n\t__kernel_off_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[256];\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct pmu;\n\nstruct cgroup;\n\nstruct __group_key {\n\tint cpu;\n\tstruct pmu *pmu;\n\tstruct cgroup *cgroup;\n};\n\nstruct guc_mmio_reg_set {\n\tu32 address;\n\tu16 count;\n\tu16 reserved;\n};\n\nstruct guc_ads {\n\tstruct guc_mmio_reg_set reg_state_list[512];\n\tu32 reserved0;\n\tu32 scheduler_policies;\n\tu32 gt_system_info;\n\tu32 reserved1;\n\tu32 control_data;\n\tu32 golden_context_lrca[16];\n\tu32 eng_state_size[16];\n\tu32 private_data;\n\tu32 reserved2;\n\tu32 capture_instance[32];\n\tu32 capture_class[32];\n\tu32 capture_global[2];\n\tu32 wa_klv_addr_lo;\n\tu32 wa_klv_addr_hi;\n\tu32 wa_klv_size;\n\tu32 reserved[11];\n};\n\nstruct guc_policies {\n\tu32 submission_queue_depth[16];\n\tu32 dpc_promote_time;\n\tu32 is_valid;\n\tu32 max_num_work_items;\n\tu32 global_flags;\n\tu32 reserved[4];\n};\n\nstruct guc_gt_system_info {\n\tu8 mapping_table[512];\n\tu32 engine_enabled_masks[16];\n\tu32 generic_gt_sysinfo[16];\n};\n\nstruct guc_engine_usage_record {\n\tu32 current_context_index;\n\tu32 last_switch_in_stamp;\n\tu32 reserved0;\n\tu32 total_runtime;\n\tu32 reserved1[4];\n};\n\nstruct guc_engine_usage {\n\tstruct guc_engine_usage_record engines[512];\n};\n\nstruct guc_mmio_reg {\n\tu32 offset;\n\tu32 value;\n\tu32 flags;\n\tu32 mask;\n};\n\nstruct __guc_ads_blob {\n\tstruct guc_ads ads;\n\tstruct guc_policies policies;\n\tstruct guc_gt_system_info system_info;\n\tstruct guc_engine_usage engine_usage;\n\tstruct guc_mmio_reg regset[0];\n};\n\nstruct __guc_capture_ads_cache {\n\tbool is_valid;\n\tvoid *ptr;\n\tsize_t size;\n\tint status;\n};\n\nstruct __guc_capture_bufstate {\n\tu32 size;\n\tvoid *data;\n\tu32 rd;\n\tu32 wr;\n};\n\nstruct gcap_reg_list_info {\n\tu32 vfid;\n\tu32 num_regs;\n\tstruct guc_mmio_reg *regs;\n};\n\nstruct __guc_capture_parsed_output {\n\tstruct list_head link;\n\tbool is_partial;\n\tu32 eng_class;\n\tu32 eng_inst;\n\tu32 guc_id;\n\tu32 lrca;\n\tstruct gcap_reg_list_info reginfo[3];\n};\n\nstruct __guc_mmio_reg_descr {\n\ti915_reg_t reg;\n\tu32 flags;\n\tu32 mask;\n\tconst char *regname;\n};\n\nstruct __guc_mmio_reg_descr_group {\n\tconst struct __guc_mmio_reg_descr *list;\n\tu32 num_regs;\n\tu32 owner;\n\tu32 type;\n\tu32 engine;\n\tstruct __guc_mmio_reg_descr *extlist;\n};\n\nstruct hda_codec;\n\nstruct __hda_power_obj {\n\tstruct hda_codec *codec;\n\tint err;\n};\n\ntypedef struct __hda_power_obj class_snd_hda_power_pm_t;\n\ntypedef struct __hda_power_obj class_snd_hda_power_t;\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct sha512_block_state {\n\tu64 h[8];\n};\n\nstruct __sha512_ctx {\n\tstruct sha512_block_state state;\n\tu64 bytecount_lo;\n\tu64 bytecount_hi;\n\tu8 buf[128];\n};\n\nstruct __hmac_sha512_ctx {\n\tstruct __sha512_ctx sha_ctx;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __hmac_sha512_key {\n\tstruct sha512_block_state istate;\n\tstruct sha512_block_state ostate;\n};\n\nstruct ww_acquire_ctx;\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n};\n\nstruct drm_modeset_lock {\n\tstruct ww_mutex mutex;\n\tstruct list_head head;\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct drm_modeset_acquire_ctx;\n\nstruct drm_mode_config_funcs;\n\nstruct drm_property;\n\nstruct drm_atomic_state;\n\nstruct drm_mode_config_helper_funcs;\n\nstruct drm_mode_config {\n\tstruct mutex mutex;\n\tstruct drm_modeset_lock connection_mutex;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct mutex idr_mutex;\n\tstruct idr object_idr;\n\tstruct idr tile_idr;\n\tstruct mutex fb_lock;\n\tint num_fb;\n\tstruct list_head fb_list;\n\tspinlock_t connector_list_lock;\n\tint num_connector;\n\tstruct ida connector_ida;\n\tstruct list_head connector_list;\n\tstruct llist_head connector_free_list;\n\tstruct work_struct connector_free_work;\n\tint num_encoder;\n\tstruct list_head encoder_list;\n\tint num_total_plane;\n\tstruct list_head plane_list;\n\tstruct raw_spinlock panic_lock;\n\tint num_colorop;\n\tstruct list_head colorop_list;\n\tint num_crtc;\n\tstruct list_head crtc_list;\n\tstruct list_head property_list;\n\tstruct list_head privobj_list;\n\tunsigned int min_width;\n\tunsigned int min_height;\n\tunsigned int max_width;\n\tunsigned int max_height;\n\tconst struct drm_mode_config_funcs *funcs;\n\tbool poll_enabled;\n\tbool poll_running;\n\tbool delayed_event;\n\tstruct delayed_work output_poll_work;\n\tstruct mutex blob_lock;\n\tstruct list_head property_blob_list;\n\tstruct drm_property *edid_property;\n\tstruct drm_property *dpms_property;\n\tstruct drm_property *path_property;\n\tstruct drm_property *tile_property;\n\tstruct drm_property *link_status_property;\n\tstruct drm_property *plane_type_property;\n\tstruct drm_property *prop_src_x;\n\tstruct drm_property *prop_src_y;\n\tstruct drm_property *prop_src_w;\n\tstruct drm_property *prop_src_h;\n\tstruct drm_property *prop_crtc_x;\n\tstruct drm_property *prop_crtc_y;\n\tstruct drm_property *prop_crtc_w;\n\tstruct drm_property *prop_crtc_h;\n\tstruct drm_property *prop_fb_id;\n\tstruct drm_property *prop_in_fence_fd;\n\tstruct drm_property *prop_out_fence_ptr;\n\tstruct drm_property *prop_crtc_id;\n\tstruct drm_property *prop_fb_damage_clips;\n\tstruct drm_property *prop_active;\n\tstruct drm_property *prop_mode_id;\n\tstruct drm_property *prop_vrr_enabled;\n\tstruct drm_property *dvi_i_subconnector_property;\n\tstruct drm_property *dvi_i_select_subconnector_property;\n\tstruct drm_property *dp_subconnector_property;\n\tstruct drm_property *tv_subconnector_property;\n\tstruct drm_property *tv_select_subconnector_property;\n\tstruct drm_property *legacy_tv_mode_property;\n\tstruct drm_property *tv_mode_property;\n\tstruct drm_property *tv_left_margin_property;\n\tstruct drm_property *tv_right_margin_property;\n\tstruct drm_property *tv_top_margin_property;\n\tstruct drm_property *tv_bottom_margin_property;\n\tstruct drm_property *tv_brightness_property;\n\tstruct drm_property *tv_contrast_property;\n\tstruct drm_property *tv_flicker_reduction_property;\n\tstruct drm_property *tv_overscan_property;\n\tstruct drm_property *tv_saturation_property;\n\tstruct drm_property *tv_hue_property;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *aspect_ratio_property;\n\tstruct drm_property *content_type_property;\n\tstruct drm_property *degamma_lut_property;\n\tstruct drm_property *degamma_lut_size_property;\n\tstruct drm_property *ctm_property;\n\tstruct drm_property *gamma_lut_property;\n\tstruct drm_property *gamma_lut_size_property;\n\tstruct drm_property *suggested_x_property;\n\tstruct drm_property *suggested_y_property;\n\tstruct drm_property *non_desktop_property;\n\tstruct drm_property *panel_orientation_property;\n\tstruct drm_property *writeback_fb_id_property;\n\tstruct drm_property *writeback_pixel_formats_property;\n\tstruct drm_property *writeback_out_fence_ptr_property;\n\tstruct drm_property *hdr_output_metadata_property;\n\tstruct drm_property *content_protection_property;\n\tstruct drm_property *hdcp_content_type_property;\n\tuint32_t preferred_depth;\n\tuint32_t prefer_shadow;\n\tbool quirk_addfb_prefer_xbgr_30bpp;\n\tbool quirk_addfb_prefer_host_byte_order;\n\tbool async_page_flip;\n\tbool fb_modifiers_not_supported;\n\tbool normalize_zpos;\n\tstruct drm_property *modifiers_property;\n\tstruct drm_property *async_modifiers_property;\n\tstruct drm_property *size_hints_property;\n\tuint32_t cursor_width;\n\tuint32_t cursor_height;\n\tstruct drm_atomic_state *suspend_state;\n\tconst struct drm_mode_config_helper_funcs *helper_private;\n};\n\nstruct drm_vram_mm;\n\nstruct drm_fb_helper;\n\nstruct drm_driver;\n\nstruct drm_minor;\n\nstruct drm_master;\n\nstruct inode;\n\nstruct drm_vblank_crtc;\n\nstruct drm_vma_offset_manager;\n\nstruct drm_device {\n\tint if_version;\n\tstruct kref ref;\n\tstruct device *dev;\n\tstruct device *dma_dev;\n\tstruct {\n\t\tstruct list_head resources;\n\t\tvoid *final_kfree;\n\t\tspinlock_t lock;\n\t} managed;\n\tconst struct drm_driver *driver;\n\tvoid *dev_private;\n\tstruct drm_minor *primary;\n\tstruct drm_minor *render;\n\tstruct drm_minor *accel;\n\tbool registered;\n\tstruct drm_master *master;\n\tu32 driver_features;\n\tbool unplugged;\n\tstruct inode *anon_inode;\n\tchar *unique;\n\tstruct mutex master_mutex;\n\tatomic_t open_count;\n\tstruct mutex filelist_mutex;\n\tstruct list_head filelist;\n\tstruct list_head filelist_internal;\n\tstruct mutex clientlist_mutex;\n\tstruct list_head clientlist;\n\tstruct list_head client_sysrq_list;\n\tbool vblank_disable_immediate;\n\tstruct drm_vblank_crtc *vblank;\n\tspinlock_t vblank_time_lock;\n\tspinlock_t vbl_lock;\n\tu32 max_vblank_count;\n\tstruct list_head vblank_event_list;\n\tspinlock_t event_lock;\n\tunsigned int num_crtcs;\n\tstruct drm_mode_config mode_config;\n\tstruct mutex object_name_lock;\n\tstruct idr object_name_idr;\n\tstruct drm_vma_offset_manager *vma_offset_manager;\n\tstruct drm_vram_mm *vram_mm;\n\tenum switch_power_state switch_power_state;\n\tstruct drm_fb_helper *fb_helper;\n\tstruct dentry *debugfs_root;\n};\n\nstruct intel_display;\n\nstruct __intel_generic_device {\n\tstruct drm_device drm;\n\tstruct intel_display *display;\n};\n\nstruct __ip6_tnl_parm {\n\tchar name[16];\n\tint link;\n\t__u8 proto;\n\t__u8 encap_limit;\n\t__u8 hop_limit;\n\tbool collect_md;\n\t__be32 flowinfo;\n\t__u32 flags;\n\tstruct in6_addr laddr;\n\tstruct in6_addr raddr;\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\t__u32 fwmark;\n\t__u32 index;\n\t__u8 erspan_ver;\n\t__u8 dir;\n\t__u16 hwid;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct __large_struct {\n\tlong unsigned int buf[100];\n};\n\nstruct __old_kernel_stat {\n\tshort unsigned int st_dev;\n\tshort unsigned int st_ino;\n\tshort unsigned int st_mode;\n\tshort unsigned int st_nlink;\n\tshort unsigned int st_uid;\n\tshort unsigned int st_gid;\n\tshort unsigned int st_rdev;\n\tunsigned int st_size;\n\tunsigned int st_atime;\n\tunsigned int st_mtime;\n\tunsigned int st_ctime;\n};\n\nstruct sha3_state {\n\tunion {\n\t\t__le64 words[25];\n\t\tu8 bytes[200];\n\t\tu64 native_words[25];\n\t};\n};\n\nstruct __sha3_ctx {\n\tstruct sha3_state state;\n\tu8 digest_size;\n\tu8 block_size;\n\tu8 absorb_offset;\n\tu8 squeeze_offset;\n};\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[8];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[8];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct __snd_pcm_mmap_control64_buggy {\n\t__pad_before_u32 __pad1;\n\t__u32 appl_ptr;\n\t__pad_before_u32 __pad2;\n\t__pad_before_u32 __pad3;\n\t__u32 avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct snd_seq_real_time {\n\tunsigned int tv_sec;\n\tunsigned int tv_nsec;\n};\n\nunion snd_seq_timestamp {\n\tsnd_seq_tick_time_t tick;\n\tstruct snd_seq_real_time time;\n};\n\nstruct snd_seq_addr {\n\tunsigned char client;\n\tunsigned char port;\n};\n\nstruct snd_seq_ev_note {\n\tunsigned char channel;\n\tunsigned char note;\n\tunsigned char velocity;\n\tunsigned char off_velocity;\n\tunsigned int duration;\n};\n\nstruct snd_seq_ev_ctrl {\n\tunsigned char channel;\n\tunsigned char unused1;\n\tunsigned char unused2;\n\tunsigned char unused3;\n\tunsigned int param;\n\tint value;\n};\n\nstruct snd_seq_ev_raw8 {\n\tunsigned char d[12];\n};\n\nstruct snd_seq_ev_raw32 {\n\tunsigned int d[3];\n};\n\nstruct snd_seq_ev_ext {\n\tunsigned int len;\n\tvoid *ptr;\n} __attribute__((packed));\n\nstruct snd_seq_queue_skew {\n\tunsigned int value;\n\tunsigned int base;\n};\n\nstruct snd_seq_ev_queue_control {\n\tunsigned char queue;\n\tunsigned char pad[3];\n\tunion {\n\t\tint value;\n\t\tunion snd_seq_timestamp time;\n\t\tunsigned int position;\n\t\tstruct snd_seq_queue_skew skew;\n\t\tunsigned int d32[2];\n\t\tunsigned char d8[8];\n\t} param;\n};\n\nstruct snd_seq_connect {\n\tstruct snd_seq_addr sender;\n\tstruct snd_seq_addr dest;\n};\n\nstruct snd_seq_result {\n\tint event;\n\tint result;\n};\n\nstruct snd_seq_event;\n\nstruct snd_seq_ev_quote {\n\tstruct snd_seq_addr origin;\n\tshort unsigned int value;\n\tstruct snd_seq_event *event;\n} __attribute__((packed));\n\nstruct snd_seq_ev_ump_notify {\n\tunsigned char client;\n\tunsigned char block;\n};\n\nunion snd_seq_event_data {\n\tstruct snd_seq_ev_note note;\n\tstruct snd_seq_ev_ctrl control;\n\tstruct snd_seq_ev_raw8 raw8;\n\tstruct snd_seq_ev_raw32 raw32;\n\tstruct snd_seq_ev_ext ext;\n\tstruct snd_seq_ev_queue_control queue;\n\tunion snd_seq_timestamp time;\n\tstruct snd_seq_addr addr;\n\tstruct snd_seq_connect connect;\n\tstruct snd_seq_result result;\n\tstruct snd_seq_ev_quote quote;\n\tstruct snd_seq_ev_ump_notify ump_notify;\n};\n\nstruct snd_seq_event {\n\tsnd_seq_event_type_t type;\n\tunsigned char flags;\n\tchar tag;\n\tunsigned char queue;\n\tunion snd_seq_timestamp time;\n\tstruct snd_seq_addr source;\n\tstruct snd_seq_addr dest;\n\tunion snd_seq_event_data data;\n};\n\nunion __snd_seq_event {\n\tstruct snd_seq_event legacy;\n\tstruct {\n\t\tstruct snd_seq_event event;\n\t} raw;\n};\n\nstruct __snd_timespec {\n\t__s32 tv_sec;\n\t__s32 tv_nsec;\n};\n\nstruct __track_dentry_update_args {\n\tstruct dentry *dentry;\n\tint op;\n};\n\nstruct __track_range_args {\n\text4_lblk_t start;\n\text4_lblk_t end;\n};\n\nunion __u128_halves {\n\tu128 full;\n\tstruct {\n\t\tu64 low;\n\t\tu64 high;\n\t};\n};\n\nstruct __uprobe_key {\n\tstruct inode *inode;\n\tloff_t offset;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct __va_list_tag {\n\tunsigned int gp_offset;\n\tunsigned int fp_offset;\n\tvoid *overflow_arg_area;\n\tvoid *reg_save_area;\n};\n\ntypedef __builtin_va_list va_list;\n\nstruct drm_mm;\n\nstruct drm_mm_node {\n\tlong unsigned int color;\n\tu64 start;\n\tu64 size;\n\tstruct drm_mm *mm;\n\tstruct list_head node_list;\n\tstruct list_head hole_stack;\n\tstruct rb_node rb;\n\tstruct rb_node rb_hole_size;\n\tstruct rb_node rb_hole_addr;\n\tu64 __subtree_last;\n\tu64 hole_size;\n\tu64 subtree_max_hole;\n\tlong unsigned int flags;\n};\n\nstruct _balloon_info_ {\n\tstruct drm_mm_node space[4];\n};\n\nstruct net_device;\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nunion _cpuid4_leaf_eax {\n\tstruct {\n\t\tenum _cache_type type: 5;\n\t\tunsigned int level: 3;\n\t\tunsigned int is_self_initializing: 1;\n\t\tunsigned int is_fully_associative: 1;\n\t\tunsigned int reserved: 4;\n\t\tunsigned int num_threads_sharing: 12;\n\t\tunsigned int num_cores_on_die: 6;\n\t} split;\n\tu32 full;\n};\n\nunion _cpuid4_leaf_ebx {\n\tstruct {\n\t\tunsigned int coherency_line_size: 12;\n\t\tunsigned int physical_line_partition: 10;\n\t\tunsigned int ways_of_associativity: 10;\n\t} split;\n\tu32 full;\n};\n\nunion _cpuid4_leaf_ecx {\n\tstruct {\n\t\tunsigned int number_of_sets: 32;\n\t} split;\n\tu32 full;\n};\n\nstruct _cpuid4_info {\n\tunion _cpuid4_leaf_eax eax;\n\tunion _cpuid4_leaf_ebx ebx;\n\tunion _cpuid4_leaf_ecx ecx;\n\tunsigned int id;\n\tlong unsigned int size;\n};\n\nstruct jump_entry;\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct _ddebug {\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n\tconst char *format;\n\tunsigned int lineno: 18;\n\tunsigned int class_id: 6;\n\tunsigned int flags: 8;\n\tunion {\n\t\tstruct static_key_true dd_key_true;\n\t\tstruct static_key_false dd_key_false;\n\t} key;\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _fpreg {\n\t__u16 significand[4];\n\t__u16 exponent;\n};\n\nstruct _fpxreg {\n\t__u16 significand[4];\n\t__u16 exponent;\n\t__u16 padding[3];\n};\n\nstruct _xmmreg {\n\t__u32 element[4];\n};\n\nstruct _fpx_sw_bytes {\n\t__u32 magic1;\n\t__u32 extended_size;\n\t__u64 xfeatures;\n\t__u32 xstate_size;\n\t__u32 padding[7];\n};\n\nstruct _fpstate_32 {\n\t__u32 cw;\n\t__u32 sw;\n\t__u32 tag;\n\t__u32 ipoff;\n\t__u32 cssel;\n\t__u32 dataoff;\n\t__u32 datasel;\n\tstruct _fpreg _st[8];\n\t__u16 status;\n\t__u16 magic;\n\t__u32 _fxsr_env[6];\n\t__u32 mxcsr;\n\t__u32 reserved;\n\tstruct _fpxreg _fxsr_st[8];\n\tstruct _xmmreg _xmm[8];\n\tunion {\n\t\t__u32 padding1[44];\n\t\t__u32 padding[44];\n\t};\n\tunion {\n\t\t__u32 padding2[12];\n\t\tstruct _fpx_sw_bytes sw_reserved;\n\t};\n};\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n} __attribute__((packed));\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct intel_gtt_driver;\n\nstruct pci_dev;\n\nstruct page;\n\nstruct _intel_private {\n\tconst struct intel_gtt_driver *driver;\n\tstruct pci_dev *pcidev;\n\tstruct pci_dev *bridge_dev;\n\tu8 *registers;\n\tphys_addr_t gtt_phys_addr;\n\tu32 PGETBL_save;\n\tu32 *gtt;\n\tbool clear_fake_agp;\n\tint num_dcache_entries;\n\tvoid *i9xx_flush_page;\n\tchar *i81x_gtt_table;\n\tstruct resource ifp_resource;\n\tint resource_valid;\n\tstruct page *scratch_page;\n\tphys_addr_t scratch_page_dma;\n\tint refcount;\n\tunsigned int needs_dmar: 1;\n\tphys_addr_t gma_bus_addr;\n\tresource_size_t stolen_size;\n\tunsigned int gtt_total_entries;\n\tunsigned int gtt_mappable_entries;\n};\n\nstruct kvm_stats_desc {\n\t__u32 flags;\n\t__s16 exponent;\n\t__u16 size;\n\t__u32 offset;\n\t__u32 bucket_size;\n\tchar name[0];\n};\n\nstruct _kvm_stats_desc {\n\tstruct kvm_stats_desc desc;\n\tchar name[48];\n};\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct _thermal_state {\n\tu64 next_check;\n\tu64 last_interrupt_time;\n\tstruct delayed_work therm_work;\n\tlong unsigned int count;\n\tlong unsigned int last_count;\n\tlong unsigned int max_time_ms;\n\tlong unsigned int total_time_ms;\n\tbool rate_control_active;\n\tbool new_event;\n\tu8 level;\n\tu8 sample_index;\n\tu8 sample_count;\n\tu8 average;\n\tu8 baseline_temp;\n\tu8 temp_samples[3];\n};\n\nstruct a4tech_sc {\n\tlong unsigned int quirks;\n\tunsigned int hw_wheel;\n\t__s32 delayed_value;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct ac6_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct access_coordinate {\n\tunsigned int read_bandwidth;\n\tunsigned int write_bandwidth;\n\tunsigned int read_latency;\n\tunsigned int write_latency;\n};\n\nstruct acct {\n\tchar ac_flag;\n\tchar ac_version;\n\t__u16 ac_uid16;\n\t__u16 ac_gid16;\n\t__u16 ac_tty;\n\t__u32 ac_btime;\n\tcomp_t ac_utime;\n\tcomp_t ac_stime;\n\tcomp_t ac_etime;\n\tcomp_t ac_mem;\n\tcomp_t ac_io;\n\tcomp_t ac_rw;\n\tcomp_t ac_minflt;\n\tcomp_t ac_majflt;\n\tcomp_t ac_swaps;\n\t__u16 ac_ahz;\n\t__u32 ac_exitcode;\n\tchar ac_comm[17];\n\t__u8 ac_etime_hi;\n\t__u16 ac_etime_lo;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n};\n\ntypedef struct acct acct_t;\n\nstruct drm_dp_nak_reply {\n\tguid_t guid;\n\tu8 reason;\n\tu8 nak_data;\n};\n\nstruct drm_dp_link_addr_reply_port {\n\tbool input_port;\n\tu8 peer_device_type;\n\tu8 port_number;\n\tbool mcs;\n\tbool ddps;\n\tbool legacy_device_plug_status;\n\tu8 dpcd_revision;\n\tguid_t peer_guid;\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n};\n\nstruct drm_dp_link_address_ack_reply {\n\tguid_t guid;\n\tu8 nports;\n\tstruct drm_dp_link_addr_reply_port ports[16];\n};\n\nstruct drm_dp_port_number_rep {\n\tu8 port_number;\n};\n\nstruct drm_dp_enum_path_resources_ack_reply {\n\tu8 port_number;\n\tbool fec_capable;\n\tu16 full_payload_bw_number;\n\tu16 avail_payload_bw_number;\n};\n\nstruct drm_dp_allocate_payload_ack_reply {\n\tu8 port_number;\n\tu8 vcpi;\n\tu16 allocated_pbn;\n};\n\nstruct drm_dp_query_payload_ack_reply {\n\tu8 port_number;\n\tu16 allocated_pbn;\n};\n\nstruct drm_dp_remote_dpcd_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_dpcd_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_remote_dpcd_write_nak_reply {\n\tu8 port_number;\n\tu8 reason;\n\tu8 bytes_written_before_failure;\n};\n\nstruct drm_dp_remote_i2c_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_i2c_read_nak_reply {\n\tu8 port_number;\n\tu8 nak_reason;\n\tu8 i2c_nak_transaction;\n};\n\nstruct drm_dp_remote_i2c_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_query_stream_enc_status_ack_reply {\n\tu8 stream_id;\n\tbool reply_signed;\n\tbool unauthorizable_device_present;\n\tbool legacy_device_present;\n\tbool query_capable_device_present;\n\tbool hdcp_1x_device_present;\n\tbool hdcp_2x_device_present;\n\tbool auth_completed;\n\tbool encryption_enabled;\n\tbool repeater_present;\n\tu8 state;\n};\n\nunion ack_replies {\n\tstruct drm_dp_nak_reply nak;\n\tstruct drm_dp_link_address_ack_reply link_addr;\n\tstruct drm_dp_port_number_rep port_number;\n\tstruct drm_dp_enum_path_resources_ack_reply path_resources;\n\tstruct drm_dp_allocate_payload_ack_reply allocate_payload;\n\tstruct drm_dp_query_payload_ack_reply query_payload;\n\tstruct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack;\n\tstruct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack;\n\tstruct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack;\n\tstruct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack;\n\tstruct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack;\n\tstruct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;\n\tstruct drm_dp_query_stream_enc_status_ack_reply enc_status;\n};\n\nstruct drm_dp_connection_status_notify {\n\tguid_t guid;\n\tu8 port_number;\n\tbool legacy_device_plug_status;\n\tbool displayport_device_plug_status;\n\tbool message_capability_status;\n\tbool input_port;\n\tu8 peer_device_type;\n};\n\nstruct drm_dp_port_number_req {\n\tu8 port_number;\n};\n\nstruct drm_dp_resource_status_notify {\n\tu8 port_number;\n\tguid_t guid;\n\tu16 available_pbn;\n};\n\nstruct drm_dp_query_payload {\n\tu8 port_number;\n\tu8 vcpi;\n};\n\nstruct drm_dp_allocate_payload {\n\tu8 port_number;\n\tu8 number_sdp_streams;\n\tu8 vcpi;\n\tu16 pbn;\n\tu8 sdp_stream_sink[16];\n};\n\nstruct drm_dp_remote_dpcd_read {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n};\n\nstruct drm_dp_remote_dpcd_write {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_remote_i2c_read_tx {\n\tu8 i2c_dev_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n\tu8 no_stop_bit;\n\tu8 i2c_transaction_delay;\n};\n\nstruct drm_dp_remote_i2c_read {\n\tu8 num_transactions;\n\tu8 port_number;\n\tstruct drm_dp_remote_i2c_read_tx transactions[4];\n\tu8 read_i2c_device_id;\n\tu8 num_bytes_read;\n};\n\nstruct drm_dp_remote_i2c_write {\n\tu8 port_number;\n\tu8 write_i2c_device_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_query_stream_enc_status {\n\tu8 stream_id;\n\tu8 client_id[7];\n\tu8 stream_event;\n\tbool valid_stream_event;\n\tu8 stream_behavior;\n\tu8 valid_stream_behavior;\n};\n\nunion ack_req {\n\tstruct drm_dp_connection_status_notify conn_stat;\n\tstruct drm_dp_port_number_req port_num;\n\tstruct drm_dp_resource_status_notify resource_stat;\n\tstruct drm_dp_query_payload query_payload;\n\tstruct drm_dp_allocate_payload allocate_payload;\n\tstruct drm_dp_remote_dpcd_read dpcd_read;\n\tstruct drm_dp_remote_dpcd_write dpcd_write;\n\tstruct drm_dp_remote_i2c_read i2c_read;\n\tstruct drm_dp_remote_i2c_write i2c_write;\n\tstruct drm_dp_query_stream_enc_status enc_status;\n};\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n};\n\nstruct comp_alg_common {\n\tstruct crypto_alg base;\n};\n\nstruct acomp_req;\n\nstruct crypto_acomp;\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\ntypedef void (*crypto_completion_t)(void *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n\tunsigned int dma_length;\n\tunsigned int dma_flags;\n};\n\nstruct acomp_req_chain {\n\tcrypto_completion_t compl;\n\tvoid *data;\n\tstruct scatterlist ssg;\n\tstruct scatterlist dsg;\n\tunion {\n\t\tconst u8 *src;\n\t\tstruct folio *sfolio;\n\t};\n\tunion {\n\t\tu8 *dst;\n\t\tstruct folio *dfolio;\n\t};\n\tu32 flags;\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tunion {\n\t\tstruct scatterlist *dst;\n\t\tu8 *dvirt;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct acomp_req_chain chain;\n\tvoid *__ctx[0];\n};\n\nunion crypto_no_such_thing;\n\nstruct scatter_walk {\n\tunion {\n\t\tvoid * const addr;\n\t\tunion crypto_no_such_thing *__addr;\n\t};\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct acomp_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tint flags;\n};\n\nstruct power_supply;\n\nunion power_supply_propval;\n\nstruct power_supply_desc {\n\tconst char *name;\n\tenum power_supply_type type;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tu32 usb_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, enum power_supply_property);\n\tvoid (*external_power_changed)(struct power_supply *);\n\tbool no_thermal;\n\tint use_for_apm;\n};\n\nstruct notifier_block;\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct acpi_device;\n\nstruct acpi_ac {\n\tstruct power_supply *charger;\n\tstruct power_supply_desc charger_desc;\n\tstruct acpi_device *device;\n\tlong long unsigned int state;\n\tstruct notifier_block battery_nb;\n};\n\nstruct acpi_address16_attribute {\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n};\n\nstruct acpi_address32_attribute {\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n};\n\nstruct acpi_address64_attribute {\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n};\n\nstruct acpi_namespace_node;\n\nstruct acpi_address_range {\n\tstruct acpi_address_range *next;\n\tstruct acpi_namespace_node *region_node;\n\tacpi_physical_address start_address;\n\tacpi_physical_address end_address;\n};\n\nstruct acpi_battery {\n\tstruct mutex update_lock;\n\tstruct power_supply *bat;\n\tstruct power_supply_desc bat_desc;\n\tstruct acpi_device *device;\n\tstruct notifier_block pm_nb;\n\tstruct list_head list;\n\tlong unsigned int update_time;\n\tint revision;\n\tint rate_now;\n\tint capacity_now;\n\tint voltage_now;\n\tint design_capacity;\n\tint full_charge_capacity;\n\tint technology;\n\tint design_voltage;\n\tint design_capacity_warning;\n\tint design_capacity_low;\n\tint cycle_count;\n\tint measurement_accuracy;\n\tint max_sampling_time;\n\tint min_sampling_time;\n\tint max_averaging_interval;\n\tint min_averaging_interval;\n\tint capacity_granularity_1;\n\tint capacity_granularity_2;\n\tint alarm;\n\tchar model_number[64];\n\tchar serial_number[64];\n\tchar type[64];\n\tchar oem_info[64];\n\tint state;\n\tint power_unit;\n\tlong unsigned int flags;\n};\n\nstruct acpi_battery_hook {\n\tconst char *name;\n\tint (*add_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tint (*remove_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tstruct list_head list;\n};\n\nstruct acpi_bit_register_info {\n\tu8 parent_register;\n\tu8 bit_position;\n\tu16 access_bit_mask;\n};\n\nstruct acpi_buffer {\n\tacpi_size length;\n\tvoid *pointer;\n};\n\nstruct acpi_bus_event {\n\tstruct list_head node;\n\tacpi_device_class device_class;\n\tacpi_bus_id bus_id;\n\tu32 type;\n\tu32 data;\n};\n\nstruct acpi_bus_type {\n\tstruct list_head list;\n\tconst char *name;\n\tbool (*match)(struct device *);\n\tstruct acpi_device * (*find_companion)(struct device *);\n\tvoid (*setup)(struct device *);\n};\n\nstruct input_dev;\n\nstruct acpi_button {\n\tstruct acpi_device *adev;\n\tstruct device *dev;\n\tunsigned int type;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tlong unsigned int pushed;\n\tint last_state;\n\tktime_t last_time;\n\tbool suspended;\n\tbool lid_state_initialized;\n};\n\nstruct acpi_cdat_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_cfmws {\n\tstruct acpi_cedt_header header;\n\tu32 reserved1;\n\tu64 base_hpa;\n\tu64 window_size;\n\tu8 interleave_ways;\n\tu8 interleave_arithmetic;\n\tu16 reserved2;\n\tu32 granularity;\n\tu16 restrictions;\n\tu16 qtg_id;\n\tu32 interleave_targets[0];\n} __attribute__((packed));\n\nstruct acpi_comment_node {\n\tchar *comment;\n\tstruct acpi_comment_node *next;\n};\n\nstruct acpi_common_descriptor {\n\tvoid *common_pointer;\n\tu8 descriptor_type;\n};\n\nstruct acpi_common_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n};\n\nstruct acpi_connection_info {\n\tu8 *connection;\n\tu16 length;\n\tu8 access_length;\n};\n\nunion acpi_parse_object;\n\nstruct acpi_control_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu16 opcode;\n\tunion acpi_parse_object *predicate_op;\n\tu8 *aml_predicate_start;\n\tu8 *package_end;\n\tu64 loop_timeout;\n};\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct acpi_pct_register;\n\nstruct acpi_cpufreq_data {\n\tunsigned int resume;\n\tunsigned int cpu_feature;\n\tunsigned int acpi_perf_cpu;\n\tcpumask_var_t freqdomain_cpus;\n\tvoid (*cpu_freq_write)(struct acpi_pct_register *, u32);\n\tu32 (*cpu_freq_read)(struct acpi_pct_register *);\n};\n\nstruct acpi_create_field_info {\n\tstruct acpi_namespace_node *region_node;\n\tstruct acpi_namespace_node *field_node;\n\tstruct acpi_namespace_node *register_node;\n\tstruct acpi_namespace_node *data_register_node;\n\tstruct acpi_namespace_node *connection_node;\n\tu8 *resource_buffer;\n\tu32 bank_value;\n\tu32 field_bit_position;\n\tu32 field_bit_length;\n\tu16 resource_length;\n\tu16 pin_number_index;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 field_type;\n\tu8 access_length;\n};\n\nstruct acpi_csrt_group {\n\tu32 length;\n\tu32 vendor_id;\n\tu32 subvendor_id;\n\tu16 device_id;\n\tu16 subdevice_id;\n\tu16 revision;\n\tu16 reserved;\n\tu32 shared_info_length;\n};\n\nstruct acpi_csrt_shared_info {\n\tu16 major_version;\n\tu16 minor_version;\n\tu32 mmio_base_low;\n\tu32 mmio_base_high;\n\tu32 gsi_interrupt;\n\tu8 interrupt_polarity;\n\tu8 interrupt_mode;\n\tu8 num_channels;\n\tu8 dma_address_width;\n\tu16 base_request_line;\n\tu16 num_handshake_signals;\n\tu32 max_block_size;\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct address_space;\n\nstruct vm_area_struct;\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct acpi_data_attr {\n\tstruct bin_attribute attr;\n\tu64 addr;\n};\n\ntypedef void *acpi_handle;\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nunion acpi_object;\n\nstruct acpi_device_data {\n\tconst union acpi_object *pointer;\n\tstruct list_head properties;\n\tconst union acpi_object *of_compatible;\n\tstruct list_head subnodes;\n};\n\nstruct acpi_data_node {\n\tstruct list_head sibling;\n\tconst char *name;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tstruct acpi_device_data data;\n\tstruct kobject kobj;\n\tstruct completion kobj_done;\n};\n\nstruct acpi_data_node_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct acpi_data_node *, char *);\n\tssize_t (*store)(struct acpi_data_node *, const char *, size_t);\n};\n\nstruct acpi_data_obj {\n\tchar *name;\n\tint (*fn)(void *, struct acpi_data_attr *);\n};\n\nstruct acpi_data_table_mapping {\n\tvoid *pointer;\n};\n\nstruct acpi_dep_data {\n\tstruct list_head node;\n\tacpi_handle supplier;\n\tacpi_handle consumer;\n\tbool honor_dep;\n\tbool met;\n\tbool free_when_met;\n};\n\nunion acpi_operand_object;\n\nstruct acpi_object_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n};\n\nstruct acpi_object_integer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 fill[3];\n\tu64 value;\n};\n\nstruct acpi_object_string {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tchar *pointer;\n\tu32 length;\n};\n\nstruct acpi_object_buffer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 *pointer;\n\tu32 length;\n\tu32 aml_length;\n\tu8 *aml_start;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_object_package {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **elements;\n\tu8 *aml_start;\n\tu32 aml_length;\n\tu32 count;\n};\n\nstruct acpi_object_event {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tvoid *os_semaphore;\n};\n\nstruct acpi_walk_state;\n\ntypedef acpi_status (*acpi_internal_method)(struct acpi_walk_state *);\n\nstruct acpi_object_method {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 info_flags;\n\tu8 param_count;\n\tu8 sync_level;\n\tunion acpi_operand_object *mutex;\n\tunion acpi_operand_object *node;\n\tu8 *aml_start;\n\tunion {\n\t\tacpi_internal_method implementation;\n\t\tunion acpi_operand_object *handler;\n\t} dispatch;\n\tu32 aml_length;\n\tacpi_owner_id owner_id;\n\tu8 thread_count;\n};\n\nstruct acpi_thread_state;\n\nstruct acpi_object_mutex {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 sync_level;\n\tu16 acquisition_depth;\n\tvoid *os_mutex;\n\tu64 thread_id;\n\tstruct acpi_thread_state *owner_thread;\n\tunion acpi_operand_object *prev;\n\tunion acpi_operand_object *next;\n\tstruct acpi_namespace_node *node;\n\tu8 original_sync_level;\n};\n\nstruct acpi_object_region {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler;\n\tunion acpi_operand_object *next;\n\tacpi_physical_address address;\n\tu32 length;\n\tvoid *pointer;\n};\n\nstruct acpi_object_notify_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_gpe_block_info;\n\nstruct acpi_object_device {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tstruct acpi_gpe_block_info *gpe_block;\n};\n\nstruct acpi_object_power_resource {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tu32 system_level;\n\tu32 resource_order;\n};\n\nstruct acpi_object_processor {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 proc_id;\n\tu8 length;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tacpi_io_address address;\n};\n\nstruct acpi_object_thermal_zone {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_object_field_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n};\n\nstruct acpi_object_region_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu16 resource_length;\n\tunion acpi_operand_object *region_obj;\n\tu8 *resource_buffer;\n\tu16 pin_number_index;\n\tu8 *internal_pcc_buffer;\n};\n\nstruct acpi_object_buffer_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu8 is_create_field;\n\tunion acpi_operand_object *buffer_obj;\n};\n\nstruct acpi_object_bank_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n\tunion acpi_operand_object *bank_obj;\n};\n\nstruct acpi_object_index_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *index_obj;\n\tunion acpi_operand_object *data_obj;\n};\n\ntypedef void (*acpi_notify_handler)(acpi_handle, u32, void *);\n\nstruct acpi_object_notify_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tu32 handler_type;\n\tacpi_notify_handler handler;\n\tvoid *context;\n\tunion acpi_operand_object *next[2];\n};\n\ntypedef acpi_status (*acpi_adr_space_handler)(u32, acpi_physical_address, u32, u64 *, void *, void *);\n\ntypedef acpi_status (*acpi_adr_space_setup)(acpi_handle, u32, void *, void **);\n\nstruct acpi_object_addr_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tu8 handler_flags;\n\tacpi_adr_space_handler handler;\n\tstruct acpi_namespace_node *node;\n\tvoid *context;\n\tvoid *context_mutex;\n\tacpi_adr_space_setup setup;\n\tunion acpi_operand_object *region_list;\n\tunion acpi_operand_object *next;\n};\n\nstruct acpi_object_reference {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 class;\n\tu8 target_type;\n\tu8 resolved;\n\tvoid *object;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **where;\n\tu8 *index_pointer;\n\tu8 *aml;\n\tu32 value;\n};\n\nstruct acpi_object_extra {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *method_REG;\n\tstruct acpi_namespace_node *scope_node;\n\tvoid *region_context;\n\tu8 *aml_start;\n\tu32 aml_length;\n};\n\ntypedef void (*acpi_object_handler)(acpi_handle, void *);\n\nstruct acpi_object_data {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tacpi_object_handler handler;\n\tvoid *pointer;\n};\n\nstruct acpi_object_cache_list {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *next;\n};\n\nunion acpi_name_union {\n\tu32 integer;\n\tchar ascii[4];\n};\n\nstruct acpi_namespace_node {\n\tunion acpi_operand_object *object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 flags;\n\tunion acpi_name_union name;\n\tstruct acpi_namespace_node *parent;\n\tstruct acpi_namespace_node *child;\n\tstruct acpi_namespace_node *peer;\n\tacpi_owner_id owner_id;\n};\n\nunion acpi_operand_object {\n\tstruct acpi_object_common common;\n\tstruct acpi_object_integer integer;\n\tstruct acpi_object_string string;\n\tstruct acpi_object_buffer buffer;\n\tstruct acpi_object_package package;\n\tstruct acpi_object_event event;\n\tstruct acpi_object_method method;\n\tstruct acpi_object_mutex mutex;\n\tstruct acpi_object_region region;\n\tstruct acpi_object_notify_common common_notify;\n\tstruct acpi_object_device device;\n\tstruct acpi_object_power_resource power_resource;\n\tstruct acpi_object_processor processor;\n\tstruct acpi_object_thermal_zone thermal_zone;\n\tstruct acpi_object_field_common common_field;\n\tstruct acpi_object_region_field field;\n\tstruct acpi_object_buffer_field buffer_field;\n\tstruct acpi_object_bank_field bank_field;\n\tstruct acpi_object_index_field index_field;\n\tstruct acpi_object_notify_handler notify;\n\tstruct acpi_object_addr_handler address_space;\n\tstruct acpi_object_reference reference;\n\tstruct acpi_object_extra extra;\n\tstruct acpi_object_data data;\n\tstruct acpi_object_cache_list cache;\n\tstruct acpi_namespace_node node;\n};\n\nunion acpi_parse_value {\n\tu64 integer;\n\tu32 size;\n\tchar *string;\n\tu8 *buffer;\n\tchar *name;\n\tunion acpi_parse_object *arg;\n};\n\nstruct acpi_parse_obj_common {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n};\n\nstruct acpi_parse_obj_named {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tchar *path;\n\tu8 *data;\n\tu32 length;\n\tu32 name;\n};\n\nstruct acpi_parse_obj_asl {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tunion acpi_parse_object *child;\n\tunion acpi_parse_object *parent_method;\n\tchar *filename;\n\tu8 file_changed;\n\tchar *parent_filename;\n\tchar *external_name;\n\tchar *namepath;\n\tchar name_seg[4];\n\tu32 extra_value;\n\tu32 column;\n\tu32 line_number;\n\tu32 logical_line_number;\n\tu32 logical_byte_offset;\n\tu32 end_line;\n\tu32 end_logical_line;\n\tu32 acpi_btype;\n\tu32 aml_length;\n\tu32 aml_subtree_length;\n\tu32 final_aml_length;\n\tu32 final_aml_offset;\n\tu32 compile_flags;\n\tu16 parse_opcode;\n\tu8 aml_opcode_length;\n\tu8 aml_pkg_len_bytes;\n\tu8 extra;\n\tchar parse_op_name[20];\n};\n\nunion acpi_parse_object {\n\tstruct acpi_parse_obj_common common;\n\tstruct acpi_parse_obj_named named;\n\tstruct acpi_parse_obj_asl asl;\n};\n\nunion acpi_descriptor {\n\tstruct acpi_common_descriptor common;\n\tunion acpi_operand_object object;\n\tstruct acpi_namespace_node node;\n\tunion acpi_parse_object op;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct acpi_dev_match_info {\n\tstruct acpi_device_id hid[2];\n\tconst char *uid;\n\ts64 hrv;\n};\n\nstruct acpi_dev_walk_context {\n\tint (*fn)(struct acpi_device *, void *);\n\tvoid *data;\n};\n\nstruct acpi_device_status {\n\tu32 present: 1;\n\tu32 enabled: 1;\n\tu32 show_in_ui: 1;\n\tu32 functional: 1;\n\tu32 battery_present: 1;\n\tu32 reserved: 27;\n};\n\nstruct acpi_device_flags {\n\tu32 dynamic_status: 1;\n\tu32 removable: 1;\n\tu32 ejectable: 1;\n\tu32 power_manageable: 1;\n\tu32 match_driver: 1;\n\tu32 initialized: 1;\n\tu32 visited: 1;\n\tu32 hotplug_notify: 1;\n\tu32 is_dock_station: 1;\n\tu32 of_compatible_ok: 1;\n\tu32 coherent_dma: 1;\n\tu32 cca_seen: 1;\n\tu32 enumeration_by_parent: 1;\n\tu32 honor_deps: 1;\n\tu32 reserved: 18;\n};\n\nstruct acpi_pnp_type {\n\tu32 hardware_id: 1;\n\tu32 bus_address: 1;\n\tu32 platform_id: 1;\n\tu32 backlight: 1;\n\tu32 reserved: 28;\n};\n\nstruct acpi_device_pnp {\n\tacpi_bus_id bus_id;\n\tint instance_no;\n\tstruct acpi_pnp_type type;\n\tacpi_bus_address bus_address;\n\tchar *unique_id;\n\tstruct list_head ids;\n\tacpi_device_name device_name;\n\tacpi_device_class device_class;\n};\n\nstruct acpi_device_power_flags {\n\tu32 explicit_get: 1;\n\tu32 power_resources: 1;\n\tu32 inrush_current: 1;\n\tu32 power_removed: 1;\n\tu32 ignore_parent: 1;\n\tu32 dsw_present: 1;\n\tu32 reserved: 26;\n};\n\nstruct acpi_device_power_state {\n\tstruct list_head resources;\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 explicit_set: 1;\n\t\tu8 reserved: 6;\n\t} flags;\n\tint power;\n\tint latency;\n};\n\nstruct acpi_device_power {\n\tint state;\n\tstruct acpi_device_power_flags flags;\n\tstruct acpi_device_power_state states[5];\n\tu8 state_for_enumeration;\n};\n\nstruct acpi_device_wakeup_flags {\n\tu8 valid: 1;\n\tu8 notifier_present: 1;\n};\n\nstruct acpi_device_wakeup_context {\n\tvoid (*func)(struct acpi_device_wakeup_context *);\n\tstruct device *dev;\n};\n\nstruct acpi_device_wakeup {\n\tacpi_handle gpe_device;\n\tu64 gpe_number;\n\tu64 sleep_state;\n\tstruct list_head resources;\n\tstruct acpi_device_wakeup_flags flags;\n\tstruct acpi_device_wakeup_context context;\n\tstruct wakeup_source *ws;\n\tint prepare_count;\n\tint enable_count;\n};\n\nstruct acpi_device_perf_flags {\n\tu8 reserved: 8;\n};\n\nstruct acpi_device_perf_state;\n\nstruct acpi_device_perf {\n\tint state;\n\tstruct acpi_device_perf_flags flags;\n\tint state_count;\n\tstruct acpi_device_perf_state *states;\n};\n\nstruct proc_dir_entry;\n\nstruct acpi_device_dir {\n\tstruct proc_dir_entry *entry;\n};\n\nstruct acpi_scan_handler;\n\nstruct acpi_hotplug_context;\n\nstruct acpi_device_software_nodes;\n\nstruct acpi_gpio_mapping;\n\nstruct acpi_device {\n\tu32 pld_crc;\n\tint device_type;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct list_head wakeup_list;\n\tstruct list_head del_list;\n\tstruct acpi_device_status status;\n\tstruct acpi_device_flags flags;\n\tstruct acpi_device_pnp pnp;\n\tstruct acpi_device_power power;\n\tstruct acpi_device_wakeup wakeup;\n\tstruct acpi_device_perf performance;\n\tstruct acpi_device_dir dir;\n\tstruct acpi_device_data data;\n\tstruct acpi_scan_handler *handler;\n\tstruct acpi_hotplug_context *hp;\n\tstruct acpi_device_software_nodes *swnodes;\n\tconst struct acpi_gpio_mapping *driver_gpios;\n\tvoid *driver_data;\n\tstruct device dev;\n\tunsigned int physical_node_count;\n\tunsigned int dep_unmet;\n\tstruct list_head physical_node_list;\n\tstruct mutex physical_node_lock;\n\tvoid (*remove)(struct acpi_device *);\n};\n\nstruct acpi_device_bus_id {\n\tconst char *bus_id;\n\tstruct ida instance_ida;\n\tstruct list_head node;\n};\n\nstruct acpi_pnp_device_id {\n\tu32 length;\n\tchar *string;\n};\n\nstruct acpi_pnp_device_id_list {\n\tu32 count;\n\tu32 list_size;\n\tstruct acpi_pnp_device_id ids[0];\n};\n\nstruct acpi_device_info {\n\tu32 info_size;\n\tu32 name;\n\tacpi_object_type type;\n\tu8 param_count;\n\tu16 valid;\n\tu8 flags;\n\tu8 highest_dstates[4];\n\tu8 lowest_dstates[5];\n\tu64 address;\n\tstruct acpi_pnp_device_id hardware_id;\n\tstruct acpi_pnp_device_id unique_id;\n\tstruct acpi_pnp_device_id class_code;\n\tstruct acpi_pnp_device_id_list compatible_id_list;\n};\n\ntypedef int (*acpi_op_add)(struct acpi_device *);\n\ntypedef void (*acpi_op_remove)(struct acpi_device *);\n\ntypedef void (*acpi_op_notify)(struct acpi_device *, u32);\n\nstruct acpi_device_ops {\n\tacpi_op_add add;\n\tacpi_op_remove remove;\n\tacpi_op_notify notify;\n};\n\nstruct acpi_device_perf_state {\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 reserved: 7;\n\t} flags;\n\tu8 power;\n\tu8 performance;\n\tint latency;\n};\n\nstruct acpi_device_physical_node {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int node_id;\n\tbool put_online: 1;\n};\n\nstruct acpi_device_properties {\n\tstruct list_head list;\n\tconst guid_t *guid;\n\tunion acpi_object *properties;\n\tvoid **bufs;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[1];\n\t\t} value;\n\t};\n};\n\nstruct software_node;\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct acpi_device_software_node_port {\n\tchar port_name[9];\n\tu32 data_lanes[8];\n\tu32 lane_polarities[9];\n\tu64 link_frequencies[8];\n\tunsigned int port_nr;\n\tbool crs_csi2_local;\n\tstruct property_entry port_props[2];\n\tstruct property_entry ep_props[8];\n\tstruct software_node_ref_args remote_ep[1];\n};\n\nstruct acpi_device_software_nodes {\n\tstruct property_entry dev_props[6];\n\tstruct software_node *nodes;\n\tconst struct software_node **nodeptrs;\n\tstruct acpi_device_software_node_port *ports;\n\tunsigned int num_ports;\n};\n\nstruct acpi_table_desc;\n\nstruct acpi_evaluate_info;\n\nstruct acpi_device_walk_info {\n\tstruct acpi_table_desc *table_desc;\n\tstruct acpi_evaluate_info *evaluate_info;\n\tu32 device_count;\n\tu32 num_STA;\n\tu32 num_INI;\n};\n\nstruct acpi_dlayer {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct acpi_dlevel {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct dma_chan;\n\nstruct acpi_dma_spec;\n\nstruct acpi_dma {\n\tstruct list_head dma_controllers;\n\tstruct device *dev;\n\tstruct dma_chan * (*acpi_dma_xlate)(struct acpi_dma_spec *, struct acpi_dma *);\n\tvoid *data;\n\tshort unsigned int base_request_line;\n\tshort unsigned int end_request_line;\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan *, void *);\n\nstruct acpi_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct acpi_dma_spec {\n\tint chan_id;\n\tint slave_id;\n\tstruct device *dev;\n};\n\nstruct acpi_dma_parser_data {\n\tstruct acpi_dma_spec dma_spec;\n\tsize_t index;\n\tsize_t n;\n};\n\nstruct acpi_dmar_header {\n\tu16 type;\n\tu16 length;\n};\n\nstruct acpi_dmar_andd {\n\tstruct acpi_dmar_header header;\n\tu8 reserved[3];\n\tu8 device_number;\n\tunion {\n\t\tchar __pad;\n\t\tstruct {\n\t\t\tstruct {} __Empty_device_name;\n\t\t\tchar device_name[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct acpi_dmar_atsr {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu16 segment;\n};\n\nstruct acpi_dmar_device_scope {\n\tu8 entry_type;\n\tu8 length;\n\tu8 flags;\n\tu8 reserved;\n\tu8 enumeration_id;\n\tu8 bus;\n};\n\nstruct acpi_dmar_hardware_unit {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 size;\n\tu16 segment;\n\tu64 address;\n};\n\nstruct acpi_dmar_pci_path {\n\tu8 device;\n\tu8 function;\n};\n\nstruct acpi_dmar_reserved_memory {\n\tstruct acpi_dmar_header header;\n\tu16 reserved;\n\tu16 segment;\n\tu64 base_address;\n\tu64 end_address;\n};\n\nstruct acpi_dmar_rhsa {\n\tstruct acpi_dmar_header header;\n\tu32 reserved;\n\tu64 base_address;\n\tu32 proximity_domain;\n} __attribute__((packed));\n\nstruct acpi_dmar_satc {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu16 segment;\n};\n\nstruct of_device_id;\n\nstruct dev_pm_ops;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct acpi_driver {\n\tchar name[80];\n\tchar class[80];\n\tconst struct acpi_device_id *ids;\n\tunsigned int flags;\n\tstruct acpi_device_ops ops;\n\tstruct device_driver drv;\n};\n\nstruct transaction;\n\nstruct acpi_ec {\n\tacpi_handle handle;\n\tint gpe;\n\tint irq;\n\tlong unsigned int command_addr;\n\tlong unsigned int data_addr;\n\tbool global_lock;\n\tlong unsigned int flags;\n\tlong unsigned int reference_count;\n\tstruct mutex mutex;\n\twait_queue_head_t wait;\n\tstruct list_head list;\n\tstruct transaction *curr;\n\tspinlock_t lock;\n\tstruct work_struct work;\n\tlong unsigned int timestamp;\n\tenum acpi_ec_event_state event_state;\n\tunsigned int events_to_process;\n\tunsigned int events_in_progress;\n\tunsigned int queries_in_progress;\n\tbool busy_polling;\n\tunsigned int polling_guard;\n};\n\nstruct transaction {\n\tconst u8 *wdata;\n\tu8 *rdata;\n\tshort unsigned int irq_count;\n\tu8 command;\n\tu8 wi;\n\tu8 ri;\n\tu8 wlen;\n\tu8 rlen;\n\tu8 flags;\n};\n\nstruct acpi_ec_query_handler;\n\nstruct acpi_ec_query {\n\tstruct transaction transaction;\n\tstruct work_struct work;\n\tstruct acpi_ec_query_handler *handler;\n\tstruct acpi_ec *ec;\n};\n\ntypedef int (*acpi_ec_query_func)(void *);\n\nstruct acpi_ec_query_handler {\n\tstruct list_head node;\n\tacpi_ec_query_func func;\n\tacpi_handle handle;\n\tvoid *data;\n\tu8 query_bit;\n\tstruct kref kref;\n};\n\nunion acpi_predefined_info;\n\nstruct acpi_evaluate_info {\n\tstruct acpi_namespace_node *prefix_node;\n\tconst char *relative_pathname;\n\tunion acpi_operand_object **parameters;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *obj_desc;\n\tchar *full_pathname;\n\tconst union acpi_predefined_info *predefined;\n\tunion acpi_operand_object *return_object;\n\tunion acpi_operand_object *parent_package;\n\tu32 return_flags;\n\tu32 return_btype;\n\tu16 param_count;\n\tu16 node_flags;\n\tu8 pass_number;\n\tu8 return_object_type;\n\tu8 flags;\n};\n\nstruct acpi_exception_info {\n\tchar *name;\n};\n\nstruct acpi_exdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n} __attribute__((packed));\n\nstruct acpi_fadt_info {\n\tconst char *name;\n\tu16 address64;\n\tu16 address32;\n\tu16 length;\n\tu8 default_length;\n\tu8 flags;\n};\n\nstruct acpi_generic_address;\n\nstruct acpi_fadt_pm_info {\n\tstruct acpi_generic_address *target;\n\tu16 source;\n\tu8 register_num;\n};\n\nstruct acpi_fan_fif {\n\tu8 revision;\n\tu8 fine_grain_ctrl;\n\tu8 step_size;\n\tu8 low_speed_notification;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct acpi_fan_fps;\n\nstruct thermal_cooling_device;\n\nstruct acpi_fan {\n\tacpi_handle handle;\n\tbool acpi4;\n\tbool has_fst;\n\tstruct acpi_fan_fif fif;\n\tstruct acpi_fan_fps *fps;\n\tint fps_count;\n\tu32 fan_trip_granularity;\n\tstruct device *hdev;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device_attribute fst_speed;\n\tstruct device_attribute fine_grain_control;\n};\n\nstruct acpi_fan_fps {\n\tu64 control;\n\tu64 trip_point;\n\tu64 speed;\n\tu64 noise_level;\n\tu64 power;\n\tchar name[20];\n\tstruct device_attribute dev_attr;\n};\n\nstruct acpi_fan_fst {\n\tu64 revision;\n\tu64 control;\n\tu64 speed;\n};\n\nstruct acpi_ffh_info {\n\tu64 offset;\n\tu64 length;\n};\n\ntypedef u32 (*acpi_event_handler)(void *);\n\nstruct acpi_fixed_event_handler {\n\tacpi_event_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_fixed_event_info {\n\tu8 status_register_id;\n\tu8 enable_register_id;\n\tu16 status_bit_mask;\n\tu16 enable_bit_mask;\n};\n\nstruct acpi_ged_device {\n\tstruct device *dev;\n\tstruct list_head event_list;\n};\n\nstruct acpi_ged_event {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int gsi;\n\tunsigned int irq;\n\tacpi_handle handle;\n};\n\nstruct acpi_ged_handler_info {\n\tstruct acpi_ged_handler_info *next;\n\tu32 int_id;\n\tstruct acpi_namespace_node *evt_method;\n};\n\nstruct acpi_generic_address {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_update_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *object;\n};\n\nstruct acpi_scope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_pscope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 arg_count;\n\tunion acpi_parse_object *op;\n\tu8 *arg_end;\n\tu8 *pkg_end;\n\tu32 arg_list;\n};\n\nstruct acpi_pkg_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 index;\n\tunion acpi_operand_object *source_object;\n\tunion acpi_operand_object *dest_object;\n\tstruct acpi_walk_state *walk_state;\n\tvoid *this_target_obj;\n\tu32 num_packages;\n};\n\nstruct acpi_thread_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 current_sync_level;\n\tstruct acpi_walk_state *walk_state_list;\n\tunion acpi_operand_object *acquired_mutex_list;\n\tu64 thread_id;\n};\n\nstruct acpi_result_values {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *obj_desc[8];\n};\n\nstruct acpi_global_notify_handler;\n\nstruct acpi_notify_info {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 handler_list_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler_list_head;\n\tstruct acpi_global_notify_handler *global;\n};\n\nunion acpi_generic_state {\n\tstruct acpi_common_state common;\n\tstruct acpi_control_state control;\n\tstruct acpi_update_state update;\n\tstruct acpi_scope_state scope;\n\tstruct acpi_pscope_state parse_scope;\n\tstruct acpi_pkg_state pkg;\n\tstruct acpi_thread_state thread;\n\tstruct acpi_result_values results;\n\tstruct acpi_notify_info notify;\n};\n\nstruct acpi_genl_event {\n\tacpi_device_class device_class;\n\tchar bus_id[15];\n\tu32 type;\n\tu32 data;\n};\n\ntypedef acpi_status (*acpi_walk_callback)(acpi_handle, u32, void *, void **);\n\nstruct acpi_get_devices_info {\n\tacpi_walk_callback user_function;\n\tvoid *context;\n\tconst char *hid;\n};\n\nstruct acpi_global_notify_handler {\n\tacpi_notify_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_gpe_address {\n\tu8 space_id;\n\tu64 address;\n};\n\nstruct acpi_gpe_xrupt_info;\n\nstruct acpi_gpe_register_info;\n\nstruct acpi_gpe_event_info;\n\nstruct acpi_gpe_block_info {\n\tstruct acpi_namespace_node *node;\n\tstruct acpi_gpe_block_info *previous;\n\tstruct acpi_gpe_block_info *next;\n\tstruct acpi_gpe_xrupt_info *xrupt_block;\n\tstruct acpi_gpe_register_info *register_info;\n\tstruct acpi_gpe_event_info *event_info;\n\tu64 address;\n\tu32 register_count;\n\tu16 gpe_count;\n\tu16 block_base_number;\n\tu8 space_id;\n\tu8 initialized;\n};\n\nstruct acpi_gpe_block_status_context {\n\tstruct acpi_gpe_register_info *gpe_skip_register_info;\n\tu8 gpe_skip_mask;\n\tu8 retval;\n};\n\nstruct acpi_gpe_device_info {\n\tu32 index;\n\tu32 next_block_base_index;\n\tacpi_status status;\n\tstruct acpi_namespace_node *gpe_device;\n};\n\nstruct acpi_gpe_handler_info;\n\nstruct acpi_gpe_notify_info;\n\nunion acpi_gpe_dispatch_info {\n\tstruct acpi_namespace_node *method_node;\n\tstruct acpi_gpe_handler_info *handler;\n\tstruct acpi_gpe_notify_info *notify_list;\n};\n\nstruct acpi_gpe_event_info {\n\tunion acpi_gpe_dispatch_info dispatch;\n\tstruct acpi_gpe_register_info *register_info;\n\tu8 flags;\n\tu8 gpe_number;\n\tu8 runtime_count;\n\tu8 disable_for_dispatch;\n};\n\ntypedef u32 (*acpi_gpe_handler)(acpi_handle, u32, void *);\n\nstruct acpi_gpe_handler_info {\n\tacpi_gpe_handler address;\n\tvoid *context;\n\tstruct acpi_namespace_node *method_node;\n\tu8 original_flags;\n\tu8 originally_enabled;\n};\n\nstruct acpi_gpe_notify_info {\n\tstruct acpi_namespace_node *device_node;\n\tstruct acpi_gpe_notify_info *next;\n};\n\nstruct acpi_gpe_register_info {\n\tstruct acpi_gpe_address status_address;\n\tstruct acpi_gpe_address enable_address;\n\tu16 base_gpe_number;\n\tu8 enable_for_wake;\n\tu8 enable_for_run;\n\tu8 mask_for_run;\n\tu8 enable_mask;\n};\n\nstruct acpi_gpe_walk_info {\n\tstruct acpi_namespace_node *gpe_device;\n\tstruct acpi_gpe_block_info *gpe_block;\n\tu16 count;\n\tacpi_owner_id owner_id;\n\tu8 execute_by_owner_id;\n};\n\nstruct acpi_gpe_xrupt_info {\n\tstruct acpi_gpe_xrupt_info *previous;\n\tstruct acpi_gpe_xrupt_info *next;\n\tstruct acpi_gpe_block_info *gpe_block_list_head;\n\tu32 interrupt_number;\n};\n\nstruct acpi_gpio_params;\n\nstruct acpi_gpio_mapping {\n\tconst char *name;\n\tconst struct acpi_gpio_params *data;\n\tunsigned int size;\n\tunsigned int quirks;\n};\n\nstruct acpi_gpio_params {\n\tunsigned int crs_entry_index;\n\tshort unsigned int line_index;\n\tbool active_low;\n};\n\nstruct acpi_handle_list {\n\tu32 count;\n\tacpi_handle *handles;\n};\n\nstruct acpi_hardware_id {\n\tstruct list_head list;\n\tconst char *id;\n};\n\nstruct acpi_hmat_structure {\n\tu16 type;\n\tu16 reserved;\n\tu32 length;\n};\n\ntypedef int (*acpi_hp_notify)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_uevent)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_fixup)(struct acpi_device *);\n\nstruct acpi_hotplug_context {\n\tstruct acpi_device *self;\n\tacpi_hp_notify notify;\n\tacpi_hp_uevent uevent;\n\tacpi_hp_fixup fixup;\n};\n\nstruct acpi_hotplug_profile {\n\tstruct kobject kobj;\n\tint (*scan_dependent)(struct acpi_device *);\n\tvoid (*notify_online)(struct acpi_device *);\n\tbool enabled: 1;\n\tbool demand_offline: 1;\n};\n\nstruct acpi_hp_work {\n\tstruct work_struct work;\n\tstruct acpi_device *adev;\n\tu32 src;\n};\n\nstruct acpi_init_walk_info {\n\tu32 table_index;\n\tu32 object_count;\n\tu32 method_count;\n\tu32 serial_method_count;\n\tu32 non_serial_method_count;\n\tu32 serialized_method_count;\n\tu32 device_count;\n\tu32 op_region_count;\n\tu32 field_count;\n\tu32 buffer_count;\n\tu32 package_count;\n\tu32 op_region_init;\n\tu32 field_init;\n\tu32 buffer_init;\n\tu32 package_init;\n\tacpi_owner_id owner_id;\n};\n\nstruct acpi_interface_info {\n\tchar *name;\n\tstruct acpi_interface_info *next;\n\tu8 flags;\n\tu8 value;\n};\n\nstruct acpi_io_attribute {\n\tu8 range_type;\n\tu8 translation;\n\tu8 translation_type;\n\tu8 reserved1;\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct acpi_ioremap {\n\tstruct list_head list;\n\tvoid *virt;\n\tacpi_physical_address phys;\n\tacpi_size size;\n\tunion {\n\t\tlong unsigned int refcount;\n\t\tstruct rcu_work rwork;\n\t} track;\n};\n\nstruct acpi_lpat {\n\tint temp;\n\tint raw;\n};\n\nstruct acpi_lpat_conversion_table {\n\tstruct acpi_lpat *lpat;\n\tint lpat_count;\n};\n\nstruct acpi_lpi_state {\n\tu32 min_residency;\n\tu32 wake_latency;\n\tu32 flags;\n\tu32 arch_flags;\n\tu32 res_cnt_freq;\n\tu32 enable_parent_state;\n\tu64 address;\n\tu8 index;\n\tu8 entry_method;\n\tchar desc[32];\n};\n\nstruct acpi_lpi_states_array {\n\tunsigned int size;\n\tunsigned int composite_states_size;\n\tstruct acpi_lpi_state *entries;\n\tstruct acpi_lpi_state *composite_states[8];\n};\n\nstruct acpi_lpit_header {\n\tu32 type;\n\tu32 length;\n\tu16 unique_id;\n\tu16 reserved;\n\tu32 flags;\n};\n\nstruct acpi_lpit_native {\n\tstruct acpi_lpit_header header;\n\tstruct acpi_generic_address entry_trigger;\n\tu32 residency;\n\tu32 latency;\n\tstruct acpi_generic_address residency_counter;\n\tu64 counter_frequency;\n};\n\nstruct acpi_subtable_header {\n\tu8 type;\n\tu8 length;\n};\n\nstruct acpi_madt_core_pic {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu32 processor_id;\n\tu32 core_id;\n\tu32 flags;\n} __attribute__((packed));\n\nstruct acpi_madt_generic_distributor {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 gic_id;\n\tu64 base_address;\n\tu32 global_irq_base;\n\tu8 version;\n\tu8 reserved2[3];\n};\n\nstruct acpi_madt_generic_interrupt {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 cpu_interface_number;\n\tu32 uid;\n\tu32 flags;\n\tu32 parking_version;\n\tu32 performance_interrupt;\n\tu64 parked_address;\n\tu64 base_address;\n\tu64 gicv_base_address;\n\tu64 gich_base_address;\n\tu32 vgic_interrupt;\n\tu64 gicr_base_address;\n\tu64 arm_mpidr;\n\tu8 efficiency_class;\n\tu8 reserved2[1];\n\tu16 spe_interrupt;\n\tu16 trbe_interrupt;\n\tu16 iaffid;\n\tu32 irs_id;\n} __attribute__((packed));\n\nstruct acpi_madt_interrupt_override {\n\tstruct acpi_subtable_header header;\n\tu8 bus;\n\tu8 source_irq;\n\tu32 global_irq;\n\tu16 inti_flags;\n} __attribute__((packed));\n\nstruct acpi_madt_interrupt_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu8 type;\n\tu8 id;\n\tu8 eid;\n\tu8 io_sapic_vector;\n\tu32 global_irq;\n\tu32 flags;\n};\n\nstruct acpi_madt_io_apic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 address;\n\tu32 global_irq_base;\n};\n\nstruct acpi_madt_io_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 global_irq_base;\n\tu64 address;\n};\n\nstruct acpi_madt_local_apic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu32 lapic_flags;\n};\n\nstruct acpi_madt_local_apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu16 inti_flags;\n\tu8 lint;\n} __attribute__((packed));\n\nstruct acpi_madt_local_apic_override {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_madt_local_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu8 eid;\n\tu8 reserved[3];\n\tu32 lapic_flags;\n\tu32 uid;\n\tchar uid_string[0];\n};\n\nstruct acpi_madt_local_x2apic {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 local_apic_id;\n\tu32 lapic_flags;\n\tu32 uid;\n};\n\nstruct acpi_madt_local_x2apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 uid;\n\tu8 lint;\n\tu8 reserved[3];\n};\n\nstruct acpi_madt_multiproc_wakeup {\n\tstruct acpi_subtable_header header;\n\tu16 version;\n\tu32 reserved;\n\tu64 mailbox_address;\n\tu64 reset_vector;\n};\n\nstruct acpi_madt_multiproc_wakeup_mailbox {\n\tu16 command;\n\tu16 reserved;\n\tu32 apic_id;\n\tu64 wakeup_vector;\n\tu8 reserved_os[2032];\n\tu8 reserved_firmware[2048];\n};\n\nstruct acpi_madt_nmi_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 global_irq;\n};\n\nstruct acpi_madt_rintc {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 reserved;\n\tu32 flags;\n\tu64 hart_id;\n\tu32 uid;\n\tu32 ext_intc_id;\n\tu64 imsic_addr;\n\tu32 imsic_size;\n} __attribute__((packed));\n\nstruct acpi_mcfg_allocation {\n\tu64 address;\n\tu16 pci_segment;\n\tu8 start_bus_number;\n\tu8 end_bus_number;\n\tu32 reserved;\n};\n\nstruct acpi_mem_mapping {\n\tacpi_physical_address physical_address;\n\tu8 *logical_address;\n\tacpi_size length;\n\tstruct acpi_mem_mapping *next_mm;\n};\n\nstruct acpi_mem_space_context {\n\tu32 length;\n\tacpi_physical_address address;\n\tstruct acpi_mem_mapping *cur_mm;\n\tstruct acpi_mem_mapping *first_mm;\n};\n\nstruct acpi_memory_attribute {\n\tu8 write_protect;\n\tu8 caching;\n\tu8 range_type;\n\tu8 translation;\n};\n\nstruct acpi_subtbl_hdr_16 {\n\tu16 type;\n\tu16 length;\n};\n\nstruct acpi_mrrm_mem_range_entry {\n\tstruct acpi_subtbl_hdr_16 header;\n\tu32 reserved0;\n\tu64 addr_base;\n\tu64 addr_len;\n\tu16 region_id_flags;\n\tu8 local_region_id;\n\tu8 remote_region_id;\n\tu32 reserved1;\n};\n\nstruct acpi_mutex_info {\n\tvoid *mutex;\n\tu32 use_count;\n\tu64 thread_id;\n};\n\nstruct acpi_name_info {\n\tchar name[4];\n\tu16 argument_list;\n\tu8 expected_btypes;\n} __attribute__((packed));\n\nstruct acpi_namestring_info {\n\tconst char *external_name;\n\tconst char *next_external_char;\n\tchar *internal_name;\n\tu32 length;\n\tu32 num_segments;\n\tu32 num_carats;\n\tu8 fully_qualified;\n};\n\nstruct acpi_nhlt_config {\n\tu32 capabilities_size;\n\tu8 capabilities[0];\n};\n\nstruct acpi_nhlt_gendevice_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n};\n\nstruct acpi_nhlt_micdevice_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n\tu8 array_type;\n};\n\nstruct acpi_nhlt_vendor_mic_config {\n\tu8 type;\n\tu8 panel;\n\tu16 speaker_position_distance;\n\tu16 horizontal_offset;\n\tu16 vertical_offset;\n\tu8 frequency_low_band;\n\tu8 frequency_high_band;\n\tu16 direction_angle;\n\tu16 elevation_angle;\n\tu16 work_vertical_angle_begin;\n\tu16 work_vertical_angle_end;\n\tu16 work_horizontal_angle_begin;\n\tu16 work_horizontal_angle_end;\n};\n\nstruct acpi_nhlt_vendor_micdevice_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n\tu8 array_type;\n\tu8 mics_count;\n\tstruct acpi_nhlt_vendor_mic_config mics[0];\n};\n\nunion acpi_nhlt_device_config {\n\tu8 virtual_slot;\n\tstruct acpi_nhlt_gendevice_config gen;\n\tstruct acpi_nhlt_micdevice_config mic;\n\tstruct acpi_nhlt_vendor_micdevice_config vendor_mic;\n};\n\nstruct acpi_nhlt_endpoint {\n\tu32 length;\n\tu8 link_type;\n\tu8 instance_id;\n\tu16 vendor_id;\n\tu16 device_id;\n\tu16 revision_id;\n\tu32 subsystem_id;\n\tu8 device_type;\n\tu8 direction;\n\tu8 virtual_bus_id;\n} __attribute__((packed));\n\nstruct acpi_nhlt_wave_formatext {\n\tu16 format_tag;\n\tu16 channel_count;\n\tu32 samples_per_sec;\n\tu32 avg_bytes_per_sec;\n\tu16 block_align;\n\tu16 bits_per_sample;\n\tu16 extra_format_size;\n\tu16 valid_bits_per_sample;\n\tu32 channel_mask;\n\tu8 subformat[16];\n};\n\nstruct acpi_nhlt_format_config {\n\tstruct acpi_nhlt_wave_formatext format;\n\tstruct acpi_nhlt_config config;\n};\n\nstruct acpi_nhlt_formats_config {\n\tu8 formats_count;\n\tstruct acpi_nhlt_format_config formats[0];\n} __attribute__((packed));\n\nunion acpi_object {\n\tacpi_object_type type;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu64 value;\n\t} integer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tchar *pointer;\n\t} string;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tu8 *pointer;\n\t} buffer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 count;\n\t\tunion acpi_object *elements;\n\t} package;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tacpi_object_type actual_type;\n\t\tacpi_handle handle;\n\t} reference;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 proc_id;\n\t\tacpi_io_address pblk_address;\n\t\tu32 pblk_length;\n\t} processor;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 system_level;\n\t\tu32 resource_order;\n\t} power_resource;\n};\n\nstruct acpi_object_list {\n\tu32 count;\n\tunion acpi_object *pointer;\n};\n\nstruct acpi_offsets {\n\tsize_t offset;\n\tu8 mode;\n};\n\nstruct acpi_opcode_info {\n\tchar *name;\n\tu32 parse_args;\n\tu32 runtime_args;\n\tu16 flags;\n\tu8 object_type;\n\tu8 class;\n\tu8 type;\n};\n\ntypedef void (*acpi_osd_exec_callback)(void *);\n\nstruct acpi_os_dpc {\n\tacpi_osd_exec_callback function;\n\tvoid *context;\n\tstruct work_struct work;\n};\n\nstruct acpi_osc_context {\n\tchar *uuid_str;\n\tint rev;\n\tstruct acpi_buffer cap;\n\tstruct acpi_buffer ret;\n};\n\nstruct acpi_osi_config {\n\tu8 default_disabling;\n\tunsigned int linux_enable: 1;\n\tunsigned int linux_dmi: 1;\n\tunsigned int linux_cmdline: 1;\n\tunsigned int darwin_enable: 1;\n\tunsigned int darwin_dmi: 1;\n\tunsigned int darwin_cmdline: 1;\n};\n\nstruct acpi_osi_entry {\n\tchar string[64];\n\tbool enable;\n};\n\nstruct acpi_package_info {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 object_type2;\n\tu8 count2;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info2 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[4];\n\tu8 reserved;\n};\n\nstruct acpi_package_info3 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[2];\n\tu8 tail_object_type;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info4 {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 sub_object_types;\n\tu8 pkg_count;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_parse_state {\n\tu8 *aml_start;\n\tu8 *aml;\n\tu8 *aml_end;\n\tu8 *pkg_start;\n\tu8 *pkg_end;\n\tunion acpi_parse_object *start_op;\n\tstruct acpi_namespace_node *start_node;\n\tunion acpi_generic_state *scope;\n\tunion acpi_parse_object *start_scope;\n\tu32 aml_size;\n};\n\nstruct acpi_pcc_info {\n\tu8 subspace_id;\n\tu16 length;\n\tu8 *internal_buffer;\n};\n\nstruct acpi_pcct_ext_pcc_master {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved1;\n\tu64 base_address;\n\tu32 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu32 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_set_mask;\n\tu64 reserved2;\n\tstruct acpi_generic_address cmd_complete_register;\n\tu64 cmd_complete_mask;\n\tstruct acpi_generic_address cmd_update_register;\n\tu64 cmd_update_preserve_mask;\n\tu64 cmd_update_set_mask;\n\tstruct acpi_generic_address error_status_register;\n\tu64 error_status_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_ext_pcc_shared_memory {\n\tu32 signature;\n\tu32 flags;\n\tu32 length;\n\tu32 command;\n};\n\nstruct acpi_pcct_hw_reduced {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pcct_hw_reduced_type2 {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_write_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_shared_memory {\n\tu32 signature;\n\tu16 command;\n\tu16 status;\n};\n\nstruct acpi_pcct_subspace {\n\tstruct acpi_subtable_header header;\n\tu8 reserved[6];\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pci_device {\n\tacpi_handle device;\n\tstruct acpi_pci_device *next;\n};\n\nstruct acpi_pci_id {\n\tu16 segment;\n\tu16 bus;\n\tu16 device;\n\tu16 function;\n};\n\nstruct acpi_pci_ioapic {\n\tacpi_handle root_handle;\n\tacpi_handle handle;\n\tu32 gsi_base;\n\tstruct resource res;\n\tstruct pci_dev *pdev;\n\tstruct list_head list;\n};\n\nstruct acpi_pci_link_irq {\n\tu32 active;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 resource_type;\n\tu8 possible_count;\n\tu32 possible[16];\n\tu8 initialized: 1;\n\tu8 reserved: 7;\n};\n\nstruct acpi_pci_link {\n\tstruct list_head list;\n\tstruct acpi_device *device;\n\tstruct acpi_pci_link_irq irq;\n\tint refcnt;\n};\n\nstruct pci_bus;\n\nstruct acpi_pci_root {\n\tstruct acpi_device *device;\n\tstruct pci_bus *bus;\n\tu16 segment;\n\tint bridge_type;\n\tstruct resource secondary;\n\tu32 osc_support_set;\n\tu32 osc_control_set;\n\tu32 osc_ext_support_set;\n\tu32 osc_ext_control_set;\n\tphys_addr_t mcfg_addr;\n};\n\nstruct acpi_pci_root_ops;\n\nstruct acpi_pci_root_info {\n\tstruct acpi_pci_root *root;\n\tstruct acpi_device *bridge;\n\tstruct acpi_pci_root_ops *ops;\n\tstruct list_head resources;\n\tchar name[16];\n};\n\nstruct pci_ops;\n\nstruct acpi_pci_root_ops {\n\tstruct pci_ops *pci_ops;\n\tint (*init_info)(struct acpi_pci_root_info *);\n\tvoid (*release_info)(struct acpi_pci_root_info *);\n\tint (*prepare_resources)(struct acpi_pci_root_info *);\n};\n\nstruct acpi_pci_routing_table {\n\tu32 length;\n\tu32 pin;\n\tu64 address;\n\tu32 source_index;\n\tunion {\n\t\tchar pad[4];\n\t\tstruct {\n\t\t\tstruct {} __Empty_source;\n\t\t\tchar source[0];\n\t\t};\n\t};\n};\n\nstruct acpi_pct_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_pkg_info {\n\tu8 *free_space;\n\tacpi_size length;\n\tu32 object_space;\n\tu32 num_packages;\n};\n\nstruct acpi_platform_list {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n\tchar *table;\n\tenum acpi_predicate pred;\n\tchar *reason;\n\tu32 data;\n};\n\nstruct acpi_pld_info {\n\tu8 revision;\n\tu8 ignore_color;\n\tu8 red;\n\tu8 green;\n\tu8 blue;\n\tu16 width;\n\tu16 height;\n\tu8 user_visible;\n\tu8 dock;\n\tu8 lid;\n\tu8 panel;\n\tu8 vertical_position;\n\tu8 horizontal_position;\n\tu8 shape;\n\tu8 group_orientation;\n\tu8 group_token;\n\tu8 group_position;\n\tu8 bay;\n\tu8 ejectable;\n\tu8 ospm_eject_required;\n\tu8 cabinet_number;\n\tu8 card_cage_number;\n\tu8 reference;\n\tu8 rotation;\n\tu8 order;\n\tu8 reserved;\n\tu16 vertical_offset;\n\tu16 horizontal_offset;\n};\n\nstruct acpi_port_info {\n\tchar *name;\n\tu16 start;\n\tu16 end;\n\tu8 osi_dependency;\n};\n\nstruct acpi_power_dependent_device {\n\tstruct device *dev;\n\tstruct list_head node;\n};\n\nstruct acpi_power_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_power_resource {\n\tstruct acpi_device device;\n\tstruct list_head list_node;\n\tu32 system_level;\n\tu32 order;\n\tunsigned int ref_count;\n\tu8 state;\n\tstruct mutex resource_lock;\n\tstruct list_head dependents;\n};\n\nstruct acpi_power_resource_entry {\n\tstruct list_head node;\n\tstruct acpi_power_resource *resource;\n};\n\nunion acpi_predefined_info {\n\tstruct acpi_name_info info;\n\tstruct acpi_package_info ret_info;\n\tstruct acpi_package_info2 ret_info2;\n\tstruct acpi_package_info3 ret_info3;\n\tstruct acpi_package_info4 ret_info4;\n};\n\nstruct acpi_predefined_names {\n\tconst char *name;\n\tu8 type;\n\tchar *val;\n};\n\nstruct acpi_prmt_handler_info {\n\tu16 revision;\n\tu16 length;\n\tu8 handler_guid[16];\n\tu64 handler_address;\n\tu64 static_data_buffer_address;\n\tu64 acpi_param_buffer_address;\n} __attribute__((packed));\n\nstruct acpi_prmt_module_header {\n\tu16 revision;\n\tu16 length;\n};\n\nstruct acpi_prmt_module_info {\n\tu16 revision;\n\tu16 length;\n\tu8 module_guid[16];\n\tu16 major_rev;\n\tu16 minor_rev;\n\tu16 handler_info_count;\n\tu32 handler_info_offset;\n\tu64 mmio_list_pointer;\n} __attribute__((packed));\n\nstruct acpi_probe_entry;\n\ntypedef bool (*acpi_probe_entry_validate_subtbl)(struct acpi_subtable_header *, struct acpi_probe_entry *);\n\nstruct acpi_table_header;\n\ntypedef int (*acpi_tbl_table_handler)(struct acpi_table_header *);\n\nunion acpi_subtable_headers;\n\ntypedef int (*acpi_tbl_entry_handler)(union acpi_subtable_headers *, const long unsigned int);\n\nstruct acpi_probe_entry {\n\t__u8 id[5];\n\t__u8 type;\n\tacpi_probe_entry_validate_subtbl subtable_valid;\n\tunion {\n\t\tacpi_tbl_table_handler probe_table;\n\t\tacpi_tbl_entry_handler probe_subtbl;\n\t};\n\tkernel_ulong_t driver_data;\n};\n\nstruct acpi_processor_flags {\n\tu8 power: 1;\n\tu8 performance: 1;\n\tu8 throttling: 1;\n\tu8 limit: 1;\n\tu8 bm_control: 1;\n\tu8 bm_check: 1;\n\tu8 has_cst: 1;\n\tu8 has_lpi: 1;\n\tu8 power_setup_done: 1;\n\tu8 bm_rld_set: 1;\n\tu8 previously_online: 1;\n};\n\nstruct acpi_processor_cx {\n\tu8 valid;\n\tu8 type;\n\tu32 address;\n\tu8 entry_method;\n\tu8 index;\n\tu32 latency;\n\tu8 bm_sts_skip;\n\tchar desc[32];\n};\n\nstruct acpi_processor_power {\n\tint count;\n\tunion {\n\t\tstruct acpi_processor_cx states[8];\n\t\tstruct acpi_lpi_state lpi_states[8];\n\t};\n\tint timer_broadcast_on_state;\n};\n\nstruct acpi_tsd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_processor_tx {\n\tu16 power;\n\tu16 performance;\n};\n\nstruct acpi_processor_tx_tss;\n\nstruct acpi_processor;\n\nstruct acpi_processor_throttling {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_tx_tss *states_tss;\n\tstruct acpi_tsd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tint (*acpi_processor_get_throttling)(struct acpi_processor *);\n\tint (*acpi_processor_set_throttling)(struct acpi_processor *, int, bool);\n\tu32 address;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 tsd_valid_flag;\n\tunsigned int shared_type;\n\tstruct acpi_processor_tx states[16];\n};\n\nstruct acpi_processor_lx {\n\tint px;\n\tint tx;\n};\n\nstruct acpi_processor_limit {\n\tstruct acpi_processor_lx state;\n\tstruct acpi_processor_lx thermal;\n\tstruct acpi_processor_lx user;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct freq_constraints;\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct acpi_processor_performance;\n\nstruct acpi_processor {\n\tacpi_handle handle;\n\tu32 acpi_id;\n\tphys_cpuid_t phys_id;\n\tu32 id;\n\tu32 pblk;\n\tint performance_platform_limit;\n\tint throttling_platform_limit;\n\tstruct acpi_processor_flags flags;\n\tstruct acpi_processor_power power;\n\tstruct acpi_processor_performance *performance;\n\tstruct acpi_processor_throttling throttling;\n\tstruct acpi_processor_limit limit;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device *dev;\n\tstruct freq_qos_request perflib_req;\n\tstruct freq_qos_request thermal_req;\n};\n\nstruct acpi_processor_errata {\n\tu8 smp;\n\tstruct {\n\t\tu8 throttle: 1;\n\t\tu8 fdma: 1;\n\t\tu8 reserved: 6;\n\t\tu32 bmisx;\n\t} piix4;\n};\n\nstruct acpi_psd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_processor_px;\n\nstruct acpi_processor_performance {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_px *states;\n\tstruct acpi_psd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tunsigned int shared_type;\n};\n\nstruct acpi_processor_px {\n\tu64 core_frequency;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 bus_master_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_processor_throttling_arg {\n\tstruct acpi_processor *pr;\n\tint target_state;\n\tbool force;\n};\n\nstruct acpi_processor_tx_tss {\n\tu64 freqpercentage;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_prt_entry {\n\tstruct acpi_pci_id id;\n\tu8 pin;\n\tacpi_handle link;\n\tu32 index;\n};\n\nstruct acpi_reg_walk_info {\n\tu32 function;\n\tu32 reg_run_count;\n\tacpi_adr_space_type space_id;\n};\n\ntypedef acpi_status (*acpi_repair_function)(struct acpi_evaluate_info *, union acpi_operand_object **);\n\nstruct acpi_repair_info {\n\tchar name[4];\n\tacpi_repair_function repair_function;\n};\n\nstruct acpi_resource_irq {\n\tu8 descriptor_length;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tunion {\n\t\tu8 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu8 interrupts[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_dma {\n\tu8 type;\n\tu8 bus_master;\n\tu8 transfer;\n\tu8 channel_count;\n\tunion {\n\t\tu8 channel;\n\t\tstruct {\n\t\t\tstruct {} __Empty_channels;\n\t\t\tu8 channels[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_start_dependent {\n\tu8 descriptor_length;\n\tu8 compatibility_priority;\n\tu8 performance_robustness;\n};\n\nstruct acpi_resource_io {\n\tu8 io_decode;\n\tu8 alignment;\n\tu8 address_length;\n\tu16 minimum;\n\tu16 maximum;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_io {\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_dma {\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct acpi_resource_vendor {\n\tu16 byte_length;\n\tu8 byte_data[0];\n};\n\nstruct acpi_resource_vendor_typed {\n\tu16 byte_length;\n\tu8 uuid_subtype;\n\tu8 uuid[16];\n\tu8 byte_data[0];\n} __attribute__((packed));\n\nstruct acpi_resource_end_tag {\n\tu8 checksum;\n};\n\nstruct acpi_resource_memory24 {\n\tu8 write_protect;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_memory32 {\n\tu8 write_protect;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_memory32 {\n\tu8 write_protect;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nunion acpi_resource_attribute {\n\tstruct acpi_memory_attribute mem;\n\tstruct acpi_io_attribute io;\n\tu8 type_specific;\n};\n\nstruct acpi_resource_source {\n\tu8 index;\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_address16 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address16_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address32 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address32_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address64_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tu8 revision_ID;\n\tstruct acpi_address64_attribute address;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_irq {\n\tu8 producer_consumer;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tstruct acpi_resource_source resource_source;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct acpi_resource_generic_register {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_resource_gpio {\n\tu8 revision_id;\n\tu8 connection_type;\n\tu8 producer_consumer;\n\tu8 pin_config;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 io_restriction;\n\tu8 triggering;\n\tu8 polarity;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_i2c_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 access_mode;\n\tu16 slave_address;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_spi_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 wire_mode;\n\tu8 device_polarity;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_uart_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 endian;\n\tu8 data_bits;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 parity;\n\tu8 lines_enabled;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu32 default_baud_rate;\n} __attribute__((packed));\n\nstruct acpi_resource_csi2_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 local_port_instance;\n\tu8 phy_type;\n} __attribute__((packed));\n\nstruct acpi_resource_common_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_function {\n\tu8 revision_id;\n\tu8 pin_config;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_label {\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tu16 *pin_table;\n\tstruct acpi_resource_label resource_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_function {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_clock_input {\n\tu8 revision_id;\n\tu8 mode;\n\tu8 scale;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n};\n\nunion acpi_resource_data {\n\tstruct acpi_resource_irq irq;\n\tstruct acpi_resource_dma dma;\n\tstruct acpi_resource_start_dependent start_dpf;\n\tstruct acpi_resource_io io;\n\tstruct acpi_resource_fixed_io fixed_io;\n\tstruct acpi_resource_fixed_dma fixed_dma;\n\tstruct acpi_resource_vendor vendor;\n\tstruct acpi_resource_vendor_typed vendor_typed;\n\tstruct acpi_resource_end_tag end_tag;\n\tstruct acpi_resource_memory24 memory24;\n\tstruct acpi_resource_memory32 memory32;\n\tstruct acpi_resource_fixed_memory32 fixed_memory32;\n\tstruct acpi_resource_address16 address16;\n\tstruct acpi_resource_address32 address32;\n\tstruct acpi_resource_address64 address64;\n\tstruct acpi_resource_extended_address64 ext_address64;\n\tstruct acpi_resource_extended_irq extended_irq;\n\tstruct acpi_resource_generic_register generic_reg;\n\tstruct acpi_resource_gpio gpio;\n\tstruct acpi_resource_i2c_serialbus i2c_serial_bus;\n\tstruct acpi_resource_spi_serialbus spi_serial_bus;\n\tstruct acpi_resource_uart_serialbus uart_serial_bus;\n\tstruct acpi_resource_csi2_serialbus csi2_serial_bus;\n\tstruct acpi_resource_common_serialbus common_serial_bus;\n\tstruct acpi_resource_pin_function pin_function;\n\tstruct acpi_resource_pin_config pin_config;\n\tstruct acpi_resource_pin_group pin_group;\n\tstruct acpi_resource_pin_group_function pin_group_function;\n\tstruct acpi_resource_pin_group_config pin_group_config;\n\tstruct acpi_resource_clock_input clock_input;\n\tstruct acpi_resource_address address;\n};\n\nstruct acpi_resource {\n\tu32 type;\n\tu32 length;\n\tunion acpi_resource_data data;\n};\n\nstruct acpi_rsconvert_info {\n\tu8 opcode;\n\tu8 resource_offset;\n\tu8 aml_offset;\n\tu8 value;\n};\n\nstruct acpi_rsdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n\tconst char **pointer;\n} __attribute__((packed));\n\nstruct acpi_rw_lock {\n\tvoid *writer_mutex;\n\tvoid *reader_mutex;\n\tu32 num_readers;\n};\n\nstruct acpi_s2idle_dev_ops {\n\tstruct list_head list_node;\n\tvoid (*prepare)(void);\n\tvoid (*check)(void);\n\tvoid (*restore)(void);\n};\n\nstruct acpi_scan_handler {\n\tstruct list_head list_node;\n\tconst struct acpi_device_id *ids;\n\tbool (*match)(const char *, const struct acpi_device_id **);\n\tint (*attach)(struct acpi_device *, const struct acpi_device_id *);\n\tvoid (*detach)(struct acpi_device *);\n\tvoid (*post_eject)(struct acpi_device *);\n\tvoid (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n\tstruct acpi_hotplug_profile hotplug;\n};\n\nstruct acpi_scan_system_dev {\n\tstruct list_head node;\n\tstruct acpi_device *adev;\n};\n\ntypedef u32 (*acpi_sci_handler)(void *);\n\nstruct acpi_sci_handler_info {\n\tstruct acpi_sci_handler_info *next;\n\tacpi_sci_handler address;\n\tvoid *context;\n};\n\nstruct acpi_signal_fatal_info {\n\tu32 type;\n\tu32 code;\n\tu32 argument;\n};\n\ntypedef acpi_status (*acpi_object_converter)(struct acpi_namespace_node *, union acpi_operand_object *, union acpi_operand_object **);\n\nstruct acpi_simple_repair_info {\n\tchar name[4];\n\tu32 unexpected_btypes;\n\tu32 package_index;\n\tacpi_object_converter object_converter;\n};\n\nstruct acpi_srat_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 proximity_domain_lo;\n\tu8 apic_id;\n\tu32 flags;\n\tu8 local_sapic_eid;\n\tu8 proximity_domain_hi[3];\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_generic_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 reserved;\n\tu8 device_handle_type;\n\tu32 proximity_domain;\n\tu8 device_handle[16];\n\tu32 flags;\n\tu32 reserved1;\n};\n\nstruct acpi_srat_gicc_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n} __attribute__((packed));\n\nstruct acpi_srat_mem_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu16 reserved;\n\tu64 base_address;\n\tu64 length;\n\tu32 reserved1;\n\tu32 flags;\n\tu64 reserved2;\n} __attribute__((packed));\n\nstruct acpi_srat_rintc_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_x2apic_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 apic_id;\n\tu32 flags;\n\tu32 clock_domain;\n\tu32 reserved2;\n};\n\nstruct acpi_subtable_entry {\n\tunion acpi_subtable_headers *hdr;\n\tenum acpi_subtable_type type;\n};\n\nunion acpi_subtable_headers {\n\tstruct acpi_subtable_header common;\n\tstruct acpi_hmat_structure hmat;\n\tstruct acpi_prmt_module_header prmt;\n\tstruct acpi_cedt_header cedt;\n\tstruct acpi_cdat_header cdat;\n};\n\ntypedef int (*acpi_tbl_entry_handler_arg)(union acpi_subtable_headers *, void *, const long unsigned int);\n\nstruct acpi_subtable_proc {\n\tint id;\n\tacpi_tbl_entry_handler handler;\n\tacpi_tbl_entry_handler_arg handler_arg;\n\tvoid *arg;\n\tint count;\n};\n\nstruct acpi_table_attr {\n\tstruct bin_attribute attr;\n\tchar name[4];\n\tint instance;\n\tchar filename[8];\n\tstruct list_head node;\n};\n\nstruct acpi_table_header {\n\tchar signature[4];\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tchar oem_id[6];\n\tchar oem_table_id[8];\n\tu32 oem_revision;\n\tchar asl_compiler_id[4];\n\tu32 asl_compiler_revision;\n};\n\nstruct acpi_table_bert {\n\tstruct acpi_table_header header;\n\tu32 region_length;\n\tu64 address;\n};\n\nstruct acpi_table_bgrt {\n\tstruct acpi_table_header header;\n\tu16 version;\n\tu8 status;\n\tu8 image_type;\n\tu64 image_address;\n\tu32 image_offset_x;\n\tu32 image_offset_y;\n};\n\nstruct acpi_table_boot {\n\tstruct acpi_table_header header;\n\tu8 cmos_index;\n\tu8 reserved[3];\n};\n\nstruct acpi_table_ccel {\n\tstruct acpi_table_header header;\n\tu8 CCtype;\n\tu8 Ccsub_type;\n\tu16 reserved;\n\tu64 log_area_minimum_length;\n\tu64 log_area_start_address;\n};\n\nstruct acpi_table_cdat {\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tu8 reserved[6];\n\tu32 sequence;\n};\n\nstruct acpi_table_csrt {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_table_desc {\n\tacpi_physical_address address;\n\tstruct acpi_table_header *pointer;\n\tu32 length;\n\tunion acpi_name_union signature;\n\tacpi_owner_id owner_id;\n\tu8 flags;\n\tu16 validation_count;\n};\n\nstruct acpi_table_dmar {\n\tstruct acpi_table_header header;\n\tu8 width;\n\tu8 flags;\n\tu8 reserved[10];\n};\n\nstruct acpi_table_ecdt {\n\tstruct acpi_table_header header;\n\tstruct acpi_generic_address control;\n\tstruct acpi_generic_address data;\n\tu32 uid;\n\tu8 gpe;\n\tu8 id[0];\n} __attribute__((packed));\n\nstruct acpi_table_facs {\n\tchar signature[4];\n\tu32 length;\n\tu32 hardware_signature;\n\tu32 firmware_waking_vector;\n\tu32 global_lock;\n\tu32 flags;\n\tu64 xfirmware_waking_vector;\n\tu8 version;\n\tu8 reserved[3];\n\tu32 ospm_flags;\n\tu8 reserved1[24];\n};\n\nstruct acpi_table_fadt {\n\tstruct acpi_table_header header;\n\tu32 facs;\n\tu32 dsdt;\n\tu8 model;\n\tu8 preferred_profile;\n\tu16 sci_interrupt;\n\tu32 smi_command;\n\tu8 acpi_enable;\n\tu8 acpi_disable;\n\tu8 s4_bios_request;\n\tu8 pstate_control;\n\tu32 pm1a_event_block;\n\tu32 pm1b_event_block;\n\tu32 pm1a_control_block;\n\tu32 pm1b_control_block;\n\tu32 pm2_control_block;\n\tu32 pm_timer_block;\n\tu32 gpe0_block;\n\tu32 gpe1_block;\n\tu8 pm1_event_length;\n\tu8 pm1_control_length;\n\tu8 pm2_control_length;\n\tu8 pm_timer_length;\n\tu8 gpe0_block_length;\n\tu8 gpe1_block_length;\n\tu8 gpe1_base;\n\tu8 cst_control;\n\tu16 c2_latency;\n\tu16 c3_latency;\n\tu16 flush_size;\n\tu16 flush_stride;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 day_alarm;\n\tu8 month_alarm;\n\tu8 century;\n\tu16 boot_flags;\n\tu8 reserved;\n\tu32 flags;\n\tstruct acpi_generic_address reset_register;\n\tu8 reset_value;\n\tu16 arm_boot_flags;\n\tu8 minor_revision;\n\tu64 Xfacs;\n\tu64 Xdsdt;\n\tstruct acpi_generic_address xpm1a_event_block;\n\tstruct acpi_generic_address xpm1b_event_block;\n\tstruct acpi_generic_address xpm1a_control_block;\n\tstruct acpi_generic_address xpm1b_control_block;\n\tstruct acpi_generic_address xpm2_control_block;\n\tstruct acpi_generic_address xpm_timer_block;\n\tstruct acpi_generic_address xgpe0_block;\n\tstruct acpi_generic_address xgpe1_block;\n\tstruct acpi_generic_address sleep_control;\n\tstruct acpi_generic_address sleep_status;\n\tu64 hypervisor_id;\n} __attribute__((packed));\n\nstruct acpi_table_hpet {\n\tstruct acpi_table_header header;\n\tu32 id;\n\tstruct acpi_generic_address address;\n\tu8 sequence;\n\tu16 minimum_tick;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct acpi_table_list {\n\tstruct acpi_table_desc *tables;\n\tu32 current_table_count;\n\tu32 max_table_count;\n\tu8 flags;\n};\n\nstruct acpi_table_lpit {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_table_madt {\n\tstruct acpi_table_header header;\n\tu32 address;\n\tu32 flags;\n};\n\nstruct acpi_table_mcfg {\n\tstruct acpi_table_header header;\n\tu8 reserved[8];\n};\n\nstruct acpi_table_mrrm {\n\tstruct acpi_table_header header;\n\tu8 max_mem_region;\n\tu8 flags;\n\tu8 reserved[26];\n\tu8 memory_range_entry[0];\n};\n\nstruct acpi_table_nhlt {\n\tstruct acpi_table_header header;\n\tu8 endpoints_count;\n} __attribute__((packed));\n\nstruct acpi_table_pcct {\n\tstruct acpi_table_header header;\n\tu32 flags;\n\tu64 reserved;\n};\n\nstruct acpi_table_rsdp {\n\tchar signature[8];\n\tu8 checksum;\n\tchar oem_id[6];\n\tu8 revision;\n\tu32 rsdt_physical_address;\n\tu32 length;\n\tu64 xsdt_physical_address;\n\tu8 extended_checksum;\n\tu8 reserved[3];\n} __attribute__((packed));\n\nstruct acpi_table_slit {\n\tstruct acpi_table_header header;\n\tu64 locality_count;\n\tu8 entry[0];\n} __attribute__((packed));\n\nstruct acpi_table_spcr {\n\tstruct acpi_table_header header;\n\tu8 interface_type;\n\tu8 reserved[3];\n\tstruct acpi_generic_address serial_port;\n\tu8 interrupt_type;\n\tu8 pc_interrupt;\n\tu32 interrupt;\n\tu8 baud_rate;\n\tu8 parity;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 terminal_type;\n\tu8 language;\n\tu16 pci_device_id;\n\tu16 pci_vendor_id;\n\tu8 pci_bus;\n\tu8 pci_device;\n\tu8 pci_function;\n\tu32 pci_flags;\n\tu8 pci_segment;\n\tu32 uart_clk_freq;\n\tu32 precise_baudrate;\n\tu16 name_space_string_length;\n\tu16 name_space_string_offset;\n\tchar name_space_string[0];\n} __attribute__((packed));\n\nstruct acpi_table_srat {\n\tstruct acpi_table_header header;\n\tu32 table_revision;\n\tu64 reserved;\n};\n\nstruct acpi_table_stao {\n\tstruct acpi_table_header header;\n\tu8 ignore_uart;\n} __attribute__((packed));\n\nstruct acpi_thermal_trip {\n\tlong unsigned int temp_dk;\n\tstruct acpi_handle_list devices;\n};\n\nstruct acpi_thermal_passive {\n\tstruct acpi_thermal_trip trip;\n\tlong unsigned int tc1;\n\tlong unsigned int tc2;\n\tlong unsigned int delay;\n};\n\nstruct acpi_thermal_active {\n\tstruct acpi_thermal_trip trip;\n};\n\nstruct acpi_thermal_trips {\n\tstruct acpi_thermal_passive passive;\n\tstruct acpi_thermal_active active[10];\n};\n\nstruct thermal_zone_device;\n\nstruct acpi_thermal {\n\tstruct acpi_device *device;\n\tacpi_bus_id name;\n\tlong unsigned int temp_dk;\n\tlong unsigned int last_temp_dk;\n\tlong unsigned int polling_frequency;\n\tvolatile u8 zombie;\n\tstruct acpi_thermal_trips trips;\n\tstruct thermal_zone_device *thermal_zone;\n\tint kelvin_offset;\n\tstruct work_struct thermal_check_work;\n\tstruct mutex thermal_check_lock;\n\trefcount_t thermal_check_count;\n};\n\nstruct acpi_vendor_uuid {\n\tu8 subtype;\n\tu8 data[16];\n};\n\nstruct acpi_vendor_walk_info {\n\tstruct acpi_vendor_uuid *uuid;\n\tstruct acpi_buffer *buffer;\n\tacpi_status status;\n};\n\nstruct acpi_video_brightness_flags {\n\tu8 _BCL_no_ac_battery_levels: 1;\n\tu8 _BCL_reversed: 1;\n\tu8 _BQC_use_index: 1;\n};\n\nstruct acpi_video_bus_cap {\n\tu8 _DOS: 1;\n\tu8 _DOD: 1;\n\tu8 _ROM: 1;\n\tu8 _GPD: 1;\n\tu8 _SPD: 1;\n\tu8 _VPO: 1;\n\tu8 reserved: 2;\n};\n\nstruct acpi_video_bus_flags {\n\tu8 multihead: 1;\n\tu8 rom: 1;\n\tu8 post: 1;\n\tu8 reserved: 5;\n};\n\nstruct acpi_video_enumerated_device;\n\nstruct acpi_video_bus {\n\tstruct acpi_device *device;\n\tbool backlight_registered;\n\tu8 dos_setting;\n\tstruct acpi_video_enumerated_device *attached_array;\n\tu8 attached_count;\n\tu8 child_count;\n\tstruct acpi_video_bus_cap cap;\n\tstruct acpi_video_bus_flags flags;\n\tstruct list_head video_device_list;\n\tstruct mutex device_list_lock;\n\tstruct list_head entry;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tstruct notifier_block pm_nb;\n};\n\nstruct acpi_video_device_flags {\n\tu8 crt: 1;\n\tu8 lcd: 1;\n\tu8 tvout: 1;\n\tu8 dvi: 1;\n\tu8 bios: 1;\n\tu8 unknown: 1;\n\tu8 notify: 1;\n\tu8 reserved: 1;\n};\n\nstruct acpi_video_device_cap {\n\tu8 _ADR: 1;\n\tu8 _BCL: 1;\n\tu8 _BCM: 1;\n\tu8 _BQC: 1;\n\tu8 _BCQ: 1;\n\tu8 _DDC: 1;\n};\n\nstruct acpi_video_device_brightness;\n\nstruct backlight_device;\n\nstruct acpi_video_device {\n\tlong unsigned int device_id;\n\tstruct acpi_video_device_flags flags;\n\tstruct acpi_video_device_cap cap;\n\tstruct list_head entry;\n\tstruct delayed_work switch_brightness_work;\n\tint switch_brightness_event;\n\tstruct acpi_video_bus *video;\n\tstruct acpi_device *dev;\n\tstruct acpi_video_device_brightness *brightness;\n\tstruct backlight_device *backlight;\n\tstruct thermal_cooling_device *cooling_dev;\n};\n\nstruct acpi_video_device_attrib {\n\tu32 display_index: 4;\n\tu32 display_port_attachment: 4;\n\tu32 display_type: 4;\n\tu32 vendor_specific: 4;\n\tu32 bios_can_detect: 1;\n\tu32 depend_on_vga: 1;\n\tu32 pipe_id: 3;\n\tu32 reserved: 10;\n\tu32 device_id_scheme: 1;\n};\n\nstruct acpi_video_device_brightness {\n\tint curr;\n\tint count;\n\tint *levels;\n\tstruct acpi_video_brightness_flags flags;\n};\n\nstruct acpi_video_enumerated_device {\n\tunion {\n\t\tu32 int_val;\n\t\tstruct acpi_video_device_attrib attrib;\n\t} value;\n\tstruct acpi_video_device *bind_info;\n};\n\nstruct acpi_wakeup_handler {\n\tstruct list_head list_node;\n\tbool (*wakeup)(void *);\n\tvoid *context;\n};\n\nstruct acpi_walk_info {\n\tu32 debug_level;\n\tu32 count;\n\tacpi_owner_id owner_id;\n\tu8 display_type;\n};\n\ntypedef acpi_status (*acpi_parse_downwards)(struct acpi_walk_state *, union acpi_parse_object **);\n\ntypedef acpi_status (*acpi_parse_upwards)(struct acpi_walk_state *);\n\nstruct acpi_walk_state {\n\tstruct acpi_walk_state *next;\n\tu8 descriptor_type;\n\tu8 walk_type;\n\tu16 opcode;\n\tu8 next_op_info;\n\tu8 num_operands;\n\tu8 operand_index;\n\tacpi_owner_id owner_id;\n\tu8 last_predicate;\n\tu8 current_result;\n\tu8 return_used;\n\tu8 scope_depth;\n\tu8 pass_number;\n\tu8 namespace_override;\n\tu8 result_size;\n\tu8 result_count;\n\tu8 *aml;\n\tu32 arg_types;\n\tu32 method_breakpoint;\n\tu32 user_breakpoint;\n\tu32 parse_flags;\n\tstruct acpi_parse_state parser_state;\n\tu32 prev_arg_types;\n\tu32 arg_count;\n\tu16 method_nesting_depth;\n\tu8 method_is_nested;\n\tstruct acpi_namespace_node arguments[7];\n\tstruct acpi_namespace_node local_variables[8];\n\tunion acpi_operand_object *operands[9];\n\tunion acpi_operand_object **params;\n\tu8 *aml_last_while;\n\tunion acpi_operand_object **caller_return_desc;\n\tunion acpi_generic_state *control_state;\n\tstruct acpi_namespace_node *deferred_node;\n\tunion acpi_operand_object *implicit_return_obj;\n\tstruct acpi_namespace_node *method_call_node;\n\tunion acpi_parse_object *method_call_op;\n\tunion acpi_operand_object *method_desc;\n\tstruct acpi_namespace_node *method_node;\n\tchar *method_pathname;\n\tunion acpi_parse_object *op;\n\tconst struct acpi_opcode_info *op_info;\n\tunion acpi_parse_object *origin;\n\tunion acpi_operand_object *result_obj;\n\tunion acpi_generic_state *results;\n\tunion acpi_operand_object *return_desc;\n\tunion acpi_generic_state *scope_info;\n\tunion acpi_parse_object *prev_op;\n\tunion acpi_parse_object *next_op;\n\tstruct acpi_thread_state *thread;\n\tacpi_parse_downwards descending_callback;\n\tacpi_parse_upwards ascending_callback;\n};\n\nstruct acpihid_map_entry {\n\tstruct list_head list;\n\tu8 uid[256];\n\tu8 hid[9];\n\tu32 devid;\n\tu32 root_devid;\n\tbool cmd_line;\n\tstruct iommu_group *group;\n};\n\nstruct pnp_dev;\n\nstruct acpipnp_parse_option_s {\n\tstruct pnp_dev *dev;\n\tunsigned int option_flags;\n};\n\nstruct action_cache {\n\tlong unsigned int allow_native[8];\n\tlong unsigned int allow_compat[8];\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct action_gate_entry {\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n};\n\nstruct action_ops {\n\tint (*pre_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tint (*do_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*undo_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*post_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n};\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct i915_active_fence {\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct i915_active;\n\nstruct active_node {\n\tstruct rb_node node;\n\tstruct i915_active_fence base;\n\tstruct i915_active *ref;\n\tu64 timeline;\n};\n\nstruct addr_marker {\n\tlong unsigned int start_address;\n\tconst char *name;\n\tlong unsigned int max_lines;\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct audit_ntp_val {\n\tlong long int oldval;\n\tlong long int newval;\n};\n\nstruct audit_ntp_data {\n\tstruct audit_ntp_val vals[6];\n};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n};\n\nstruct adjust_trip_data {\n\tstruct acpi_thermal *tz;\n\tu32 event;\n};\n\nstruct crypto_aead;\n\nstruct aead_request;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tstruct crypto_alg base;\n};\n\nstruct aead_geniv_ctx {\n\tspinlock_t lock;\n\tstruct crypto_aead *child;\n\tu8 salt[0];\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tvoid *__ctx[0];\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tvoid *__ctx[0];\n};\n\nunion aes_enckey_arch {\n\tu32 rndkeys[60];\n};\n\nstruct aes_enckey {\n\tu32 len;\n\tu32 nrounds;\n\tu32 padding[2];\n\tunion aes_enckey_arch k;\n};\n\nunion aes_invkey_arch {\n\tu32 inv_rndkeys[60];\n};\n\nstruct aes_key {\n\tstruct aes_enckey;\n\tunion aes_invkey_arch inv_k;\n};\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct aggressiveness_profile2_entry {\n\tu8 opst_aggressiveness: 4;\n\tu8 elp_aggressiveness: 4;\n};\n\nstruct aggressiveness_profile3_entry {\n\tu8 apd_aggressiveness: 4;\n\tu8 pixoptix_aggressiveness: 4;\n};\n\nstruct aggressiveness_profile4_entry {\n\tu8 xpst_aggressiveness: 4;\n\tu8 tcon_aggressiveness: 4;\n};\n\nstruct aggressiveness_profile_entry {\n\tu8 dpst_aggressiveness: 4;\n\tu8 lace_aggressiveness: 4;\n};\n\nstruct agp_3_5_dev {\n\tstruct list_head list;\n\tu8 capndx;\n\tu32 maxbw;\n\tstruct pci_dev *dev;\n};\n\nstruct agp_version;\n\nstruct agp_bridge_driver;\n\nstruct vm_operations_struct;\n\nstruct agp_bridge_data {\n\tconst struct agp_version *version;\n\tconst struct agp_bridge_driver *driver;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *previous_size;\n\tvoid *current_size;\n\tvoid *dev_private_data;\n\tstruct pci_dev *dev;\n\tu32 *gatt_table;\n\tu32 *gatt_table_real;\n\tlong unsigned int scratch_page;\n\tstruct page *scratch_page_page;\n\tdma_addr_t scratch_page_dma;\n\tlong unsigned int gart_bus_addr;\n\tlong unsigned int gatt_bus_addr;\n\tu32 mode;\n\tlong unsigned int *key_list;\n\tatomic_t current_memory_agp;\n\tatomic_t agp_in_use;\n\tint max_memory_agp;\n\tint aperture_size_idx;\n\tint capndx;\n\tint flags;\n\tchar major_version;\n\tchar minor_version;\n\tstruct list_head list;\n\tu32 apbase_config;\n\tstruct list_head mapped_list;\n\tspinlock_t mapped_lock;\n};\n\nstruct gatt_mask;\n\nstruct agp_memory;\n\nstruct agp_bridge_driver {\n\tstruct module *owner;\n\tconst void *aperture_sizes;\n\tint num_aperture_sizes;\n\tenum aper_size_type size_type;\n\tbool cant_use_aperture;\n\tbool needs_scratch_page;\n\tconst struct gatt_mask *masks;\n\tint (*fetch_size)(void);\n\tint (*configure)(void);\n\tvoid (*agp_enable)(struct agp_bridge_data *, u32);\n\tvoid (*cleanup)(void);\n\tvoid (*tlb_flush)(struct agp_memory *);\n\tlong unsigned int (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int);\n\tvoid (*cache_flush)(void);\n\tint (*create_gatt_table)(struct agp_bridge_data *);\n\tint (*free_gatt_table)(struct agp_bridge_data *);\n\tint (*insert_memory)(struct agp_memory *, off_t, int);\n\tint (*remove_memory)(struct agp_memory *, off_t, int);\n\tstruct agp_memory * (*alloc_by_type)(size_t, int);\n\tvoid (*free_by_type)(struct agp_memory *);\n\tstruct page * (*agp_alloc_page)(struct agp_bridge_data *);\n\tint (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t);\n\tvoid (*agp_destroy_page)(struct page *, int);\n\tvoid (*agp_destroy_pages)(struct agp_memory *);\n\tint (*agp_type_to_mask_type)(struct agp_bridge_data *, int);\n};\n\nstruct agp_version {\n\tu16 major;\n\tu16 minor;\n};\n\nstruct agp_kern_info {\n\tstruct agp_version version;\n\tstruct pci_dev *device;\n\tenum chipset_type chipset;\n\tlong unsigned int mode;\n\tlong unsigned int aper_base;\n\tsize_t aper_size;\n\tint max_memory;\n\tint current_memory;\n\tbool cant_use_aperture;\n\tlong unsigned int page_mask;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct agp_memory {\n\tstruct agp_memory *next;\n\tstruct agp_memory *prev;\n\tstruct agp_bridge_data *bridge;\n\tstruct page **pages;\n\tsize_t page_count;\n\tint key;\n\tint num_scratch_pages;\n\toff_t pg_start;\n\tu32 type;\n\tu32 physical;\n\tbool is_bound;\n\tbool is_flushed;\n\tstruct list_head mapped_list;\n\tstruct scatterlist *sg_list;\n\tint num_sg;\n};\n\nstruct crypto_ahash;\n\nstruct ah_data {\n\tint icv_full_len;\n\tint icv_trunc_len;\n\tstruct crypto_ahash *ahash;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nstruct ip_tunnel;\n\nstruct ip6_tnl;\n\nstruct xfrm_tunnel_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tunion {\n\t\tstruct ip_tunnel *ip4;\n\t\tstruct ip6_tnl *ip6;\n\t} tunnel;\n};\n\nstruct xfrm_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 low;\n\t\t\t__u32 hi;\n\t\t} output;\n\t\tstruct {\n\t\t\t__be32 low;\n\t\t\t__be32 hi;\n\t\t} input;\n\t} seq;\n};\n\nstruct ah_skb_cb {\n\tstruct xfrm_skb_cb xfrm;\n\tvoid *tmp;\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*export_core)(struct ahash_request *, void *);\n\tint (*import_core)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_ahash *);\n\tvoid (*exit_tfm)(struct crypto_ahash *);\n\tint (*clone_tfm)(struct crypto_ahash *, struct crypto_ahash *);\n\tstruct hash_alg_common halg;\n};\n\nstruct ahash_hmac_ctx {\n\tstruct crypto_ahash *hash;\n\tu8 pads[0];\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[112];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tu8 *result;\n\tstruct scatterlist sg_head[2];\n\tcrypto_completion_t saved_complete;\n\tvoid *saved_data;\n\tvoid *__ctx[0];\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct ata_link;\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct reset_control;\n\nstruct regulator;\n\nstruct clk_bulk_data;\n\nstruct phy___3;\n\nstruct ata_port;\n\nstruct ata_host;\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 mask_port_map;\n\tu32 mask_port_ext;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 saved_port_cap[32];\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tunsigned int n_clks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int f_rsts;\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy___3 **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[15];\n\tchar *irq_desc;\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct eventfd_ctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct airtime_info {\n\tu64 rx_airtime;\n\tu64 tx_airtime;\n\tlong unsigned int last_active;\n\ts32 deficit;\n\tatomic_t aql_tx_pending;\n\tu32 aql_limit_low;\n\tu32 aql_limit_high;\n};\n\nstruct akcipher_request;\n\nstruct crypto_akcipher;\n\nstruct akcipher_alg {\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[56];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct alert_data {\n\tshort unsigned int addr;\n\tenum i2c_alert_protocol type;\n\tunsigned int data;\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct psmouse;\n\nstruct alps_nibble_commands;\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct als_data_entry {\n\tu16 backlight_adjust;\n\tu16 lux;\n};\n\nstruct alt_instr {\n\ts32 instr_offset;\n\ts32 repl_offset;\n\tunion {\n\t\tstruct {\n\t\t\tu32 cpuid: 16;\n\t\t\tu32 flags: 16;\n\t\t};\n\t\tu32 ft_flags;\n\t};\n\tu8 instrlen;\n\tu8 replacementlen;\n} __attribute__((packed));\n\nstruct amd_aperf_mperf {\n\tu64 aperf;\n\tu64 mperf;\n\tu64 tsc;\n};\n\nstruct amd_chipset_type {\n\tenum amd_chipset_gen gen;\n\tu8 rev;\n};\n\nstruct amd_chipset_info {\n\tstruct pci_dev *nb_dev;\n\tstruct pci_dev *smbus_dev;\n\tint nb_type;\n\tstruct amd_chipset_type sb_type;\n\tint isoc_reqs;\n\tint probe_count;\n\tbool need_pll_quirk;\n};\n\nunion perf_cached {\n\tstruct {\n\t\tu8 highest_perf;\n\t\tu8 nominal_perf;\n\t\tu8 lowest_nonlinear_perf;\n\t\tu8 lowest_perf;\n\t\tu8 min_limit_perf;\n\t\tu8 max_limit_perf;\n\t\tu8 bios_min_perf;\n\t};\n\tu64 val;\n};\n\nstruct amd_cpudata {\n\tint cpu;\n\tstruct freq_qos_request req[2];\n\tu64 cppc_req_cached;\n\tunion perf_cached perf;\n\tu8 prefcore_ranking;\n\tu32 min_limit_freq;\n\tu32 max_limit_freq;\n\tu32 nominal_freq;\n\tu32 lowest_nonlinear_freq;\n\tstruct amd_aperf_mperf cur;\n\tstruct amd_aperf_mperf prev;\n\tu64 freq;\n\tbool boost_supported;\n\tbool hw_prefcore;\n\tu32 policy;\n\tbool suspended;\n\tu8 epp_default;\n};\n\nstruct amd_hostbridge {\n\tu32 bus;\n\tu32 slot;\n\tu32 device;\n};\n\nstruct iommu_ops;\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n\tstruct iommu_group *singleton_group;\n\tu32 max_pasids;\n\tbool ready;\n};\n\nstruct amd_iommu_pci_seg;\n\nstruct iopf_queue;\n\nstruct amd_iommu {\n\tstruct list_head list;\n\tint index;\n\traw_spinlock_t lock;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *root_pdev;\n\tu64 mmio_phys;\n\tu64 mmio_phys_end;\n\tu8 *mmio_base;\n\tu32 cap;\n\tu8 acpi_flags;\n\tu64 features;\n\tu64 features2;\n\tu16 devid;\n\tu16 cap_ptr;\n\tstruct amd_iommu_pci_seg *pci_seg;\n\tu64 exclusion_start;\n\tu64 exclusion_length;\n\tu8 *cmd_buf;\n\tu32 cmd_buf_head;\n\tu32 cmd_buf_tail;\n\tu8 *evt_buf;\n\tunsigned char evt_irq_name[16];\n\tu8 *ppr_log;\n\tunsigned char ppr_irq_name[16];\n\tu8 *ga_log;\n\tunsigned char ga_irq_name[16];\n\tu8 *ga_log_tail;\n\tbool int_enabled;\n\tbool need_sync;\n\tbool irtcachedis_enabled;\n\tstruct iommu_device iommu;\n\tu32 stored_addr_lo;\n\tu32 stored_addr_hi;\n\tu32 stored_l1[108];\n\tu32 stored_l2[131];\n\tu8 max_banks;\n\tu8 max_counters;\n\tu32 flags;\n\tvolatile u64 *cmd_sem;\n\tu64 cmd_sem_val;\n\tu64 cmd_sem_paddr;\n\tstruct iopf_queue *iopf_queue;\n\tunsigned char iopfq_name[32];\n};\n\nstruct amd_iommu_event_desc {\n\tstruct device_attribute attr;\n\tconst char *event;\n};\n\nstruct dev_table_entry;\n\nstruct irq_remap_table;\n\nstruct amd_iommu_pci_seg {\n\tstruct list_head list;\n\tstruct llist_head dev_data_list;\n\tu16 id;\n\tu16 last_bdf;\n\tu32 dev_table_size;\n\tstruct dev_table_entry *dev_table;\n\tstruct amd_iommu **rlookup_table;\n\tstruct irq_remap_table **irq_lookup_table;\n\tstruct dev_table_entry *old_dev_tbl_cpy;\n\tu16 *alias_table;\n\tstruct list_head unity_map;\n};\n\nstruct iommufd_object {\n\trefcount_t wait_cnt;\n\trefcount_t users;\n\tenum iommufd_object_type type;\n\tunsigned int id;\n};\n\nstruct iommufd_ctx;\n\nstruct iommufd_hwpt_paging;\n\nstruct iommufd_viommu_ops;\n\nstruct iommufd_viommu {\n\tstruct iommufd_object obj;\n\tstruct iommufd_ctx *ictx;\n\tstruct iommu_device *iommu_dev;\n\tstruct iommufd_hwpt_paging *hwpt;\n\tconst struct iommufd_viommu_ops *ops;\n\tstruct xarray vdevs;\n\tstruct list_head veventqs;\n\tstruct rw_semaphore veventqs_rwsem;\n\tenum iommu_viommu_type type;\n};\n\nstruct protection_domain;\n\nstruct amd_iommu_viommu {\n\tstruct iommufd_viommu core;\n\tstruct protection_domain *parent;\n\tstruct list_head pdom_list;\n\tstruct xarray gdomid_array;\n};\n\nstruct amd_l3_cache {\n\tunsigned int indices;\n\tu8 subcaches[4];\n};\n\nstruct amd_lps0_hid_device_data {\n\tconst bool check_off_by_one;\n};\n\nstruct event_constraint {\n\tunion {\n\t\tlong unsigned int idxmsk[1];\n\t\tu64 idxmsk64;\n\t};\n\tu64 code;\n\tu64 cmask;\n\tint weight;\n\tint overlap;\n\tint flags;\n\tunsigned int size;\n};\n\nstruct perf_event;\n\nstruct amd_nb {\n\tint nb_id;\n\tint refcnt;\n\tstruct perf_event *owners[64];\n\tstruct event_constraint event_constraints[64];\n};\n\nstruct amd_nb_bus_dev_range {\n\tu8 bus;\n\tu8 dev_base;\n\tu8 dev_limit;\n};\n\nstruct amd_northbridge {\n\tstruct pci_dev *misc;\n\tstruct pci_dev *link;\n\tstruct amd_l3_cache l3_cache;\n};\n\nstruct amd_northbridge_info {\n\tu16 num;\n\tu64 flags;\n\tstruct amd_northbridge *nb;\n};\n\nunion amd_uncore_info;\n\nstruct amd_uncore_pmu;\n\nstruct amd_uncore {\n\tunion amd_uncore_info *info;\n\tstruct amd_uncore_pmu *pmus;\n\tunsigned int num_pmus;\n\tbool init_done;\n\tvoid (*scan)(struct amd_uncore *, unsigned int);\n\tint (*init)(struct amd_uncore *, unsigned int);\n\tvoid (*move)(struct amd_uncore *, unsigned int);\n\tvoid (*free)(struct amd_uncore *, unsigned int);\n};\n\nstruct amd_uncore_ctx {\n\tint refcnt;\n\tint cpu;\n\tstruct perf_event **events;\n\tlong unsigned int active_mask[1];\n\tint nr_active;\n\tstruct hrtimer hrtimer;\n\tu64 hrtimer_duration;\n};\n\nunion amd_uncore_info {\n\tstruct {\n\t\tu64 aux_data: 32;\n\t\tu64 num_pmcs: 8;\n\t\tu64 gid: 8;\n\t\tu64 cid: 8;\n\t} split;\n\tu64 full;\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct perf_cpu_pmu_context;\n\nstruct mm_struct;\n\nstruct perf_event_pmu_context;\n\nstruct kmem_cache;\n\nstruct perf_output_handle;\n\nstruct pmu {\n\tstruct list_head entry;\n\tspinlock_t events_lock;\n\tstruct list_head events;\n\tstruct module *module;\n\tstruct device *dev;\n\tstruct device *parent;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tunsigned int scope;\n\tstruct perf_cpu_pmu_context **cpu_pmu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tstruct kmem_cache *task_ctx_cache;\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tbool (*filter)(struct pmu *, int);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\nstruct amd_uncore_pmu {\n\tchar name[16];\n\tint num_counters;\n\tint rdpmc_base;\n\tu32 msr_base;\n\tint group;\n\tcpumask_t active_mask;\n\tstruct pmu pmu;\n\tstruct amd_uncore_ctx **ctx;\n};\n\nstruct amdv1pt_write_attrs {\n\tu64 descriptor_bits;\n\tgfp_t gfp;\n};\n\nstruct aml_resource_small_header {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_large_header {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_irq {\n\tu8 descriptor_type;\n\tu16 irq_mask;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct aml_resource_dma {\n\tu8 descriptor_type;\n\tu8 dma_channel_mask;\n\tu8 flags;\n};\n\nstruct aml_resource_start_dependent {\n\tu8 descriptor_type;\n\tu8 flags;\n};\n\nstruct aml_resource_end_dependent {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_io {\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu8 alignment;\n\tu8 address_length;\n};\n\nstruct aml_resource_fixed_io {\n\tu8 descriptor_type;\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_dma {\n\tu8 descriptor_type;\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_small {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_end_tag {\n\tu8 descriptor_type;\n\tu8 checksum;\n};\n\nstruct aml_resource_memory24 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_generic_register {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 address_space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_large {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address16 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_extended_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu8 revision_ID;\n\tu8 reserved;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct aml_resource_extended_irq {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu8 interrupt_count;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct aml_resource_gpio {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 connection_type;\n\tu16 flags;\n\tu16 int_flags;\n\tu8 pin_config;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_i2c_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu16 slave_address;\n} __attribute__((packed));\n\nstruct aml_resource_spi_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n} __attribute__((packed));\n\nstruct aml_resource_uart_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 default_baud_rate;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu8 parity;\n\tu8 lines_enabled;\n} __attribute__((packed));\n\nstruct aml_resource_csi2_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_common_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config;\n\tu16 function_number;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 pin_table_offset;\n\tu16 label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 function_number;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_clock_input {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n} __attribute__((packed));\n\nstruct aml_resource_address {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n} __attribute__((packed));\n\nunion aml_resource {\n\tu8 descriptor_type;\n\tstruct aml_resource_small_header small_header;\n\tstruct aml_resource_large_header large_header;\n\tstruct aml_resource_irq irq;\n\tstruct aml_resource_dma dma;\n\tstruct aml_resource_start_dependent start_dpf;\n\tstruct aml_resource_end_dependent end_dpf;\n\tstruct aml_resource_io io;\n\tstruct aml_resource_fixed_io fixed_io;\n\tstruct aml_resource_fixed_dma fixed_dma;\n\tstruct aml_resource_vendor_small vendor_small;\n\tstruct aml_resource_end_tag end_tag;\n\tstruct aml_resource_memory24 memory24;\n\tstruct aml_resource_generic_register generic_reg;\n\tstruct aml_resource_vendor_large vendor_large;\n\tstruct aml_resource_memory32 memory32;\n\tstruct aml_resource_fixed_memory32 fixed_memory32;\n\tstruct aml_resource_address16 address16;\n\tstruct aml_resource_address32 address32;\n\tstruct aml_resource_address64 address64;\n\tstruct aml_resource_extended_address64 ext_address64;\n\tstruct aml_resource_extended_irq extended_irq;\n\tstruct aml_resource_gpio gpio;\n\tstruct aml_resource_i2c_serialbus i2c_serial_bus;\n\tstruct aml_resource_spi_serialbus spi_serial_bus;\n\tstruct aml_resource_uart_serialbus uart_serial_bus;\n\tstruct aml_resource_csi2_serialbus csi2_serial_bus;\n\tstruct aml_resource_common_serialbus common_serial_bus;\n\tstruct aml_resource_pin_function pin_function;\n\tstruct aml_resource_pin_config pin_config;\n\tstruct aml_resource_pin_group pin_group;\n\tstruct aml_resource_pin_group_function pin_group_function;\n\tstruct aml_resource_pin_group_config pin_group_config;\n\tstruct aml_resource_clock_input clock_input;\n\tstruct aml_resource_address address;\n\tu32 dword_item;\n\tu16 word_item;\n\tu8 byte_item;\n};\n\nstruct analog_param_field {\n\tunsigned int even;\n\tunsigned int odd;\n};\n\nstruct analog_param_range {\n\tunsigned int min;\n\tunsigned int typ;\n\tunsigned int max;\n};\n\nstruct analog_parameters {\n\tunsigned int num_lines;\n\tunsigned int line_duration_ns;\n\tstruct analog_param_range hact_ns;\n\tstruct analog_param_range hfp_ns;\n\tstruct analog_param_range hslen_ns;\n\tstruct analog_param_range hbp_ns;\n\tstruct analog_param_range hblk_ns;\n\tunsigned int bt601_hfp;\n\tstruct analog_param_field vfp_lines;\n\tstruct analog_param_field vslen_lines;\n\tstruct analog_param_field vbp_lines;\n};\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct apd_private_data;\n\nstruct apd_device_desc {\n\tunsigned int fixed_clk_rate;\n\tstruct property_entry *properties;\n\tint (*setup)(struct apd_private_data *);\n};\n\nstruct clk;\n\nstruct apd_private_data {\n\tstruct clk *clk;\n\tstruct acpi_device *adev;\n\tconst struct apd_device_desc *dev_desc;\n};\n\nstruct aper_size_info_16 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu16 size_value;\n};\n\nstruct aper_size_info_32 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu32 size_value;\n};\n\nstruct aper_size_info_8 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu8 size_value;\n};\n\nstruct aper_size_info_fixed {\n\tint size;\n\tint num_entries;\n\tint page_order;\n};\n\nstruct aper_size_info_lvl2 {\n\tint size;\n\tint num_entries;\n\tu32 size_value;\n};\n\nstruct aperfmperf {\n\tseqcount_t seq;\n\tlong unsigned int last_update;\n\tu64 acnt;\n\tu64 mcnt;\n\tu64 aperf;\n\tu64 mperf;\n};\n\nstruct aperture_range {\n\tstruct device *dev;\n\tresource_size_t base;\n\tresource_size_t size;\n\tstruct list_head lh;\n\tvoid (*detach)(struct device *);\n};\n\nstruct api_context {\n\tstruct completion done;\n\tint status;\n};\n\nstruct apic {\n\tvoid (*eoi)(void);\n\tvoid (*native_eoi)(void);\n\tvoid (*write)(u32, u32);\n\tu32 (*read)(u32);\n\tvoid (*wait_icr_idle)(void);\n\tu32 (*safe_wait_icr_idle)(void);\n\tvoid (*send_IPI)(int, int);\n\tvoid (*send_IPI_mask)(const struct cpumask *, int);\n\tvoid (*send_IPI_mask_allbutself)(const struct cpumask *, int);\n\tvoid (*send_IPI_allbutself)(int);\n\tvoid (*send_IPI_all)(int);\n\tvoid (*send_IPI_self)(int);\n\tu32 disable_esr: 1;\n\tu32 dest_mode_logical: 1;\n\tu32 x2apic_set_max_apicid: 1;\n\tu32 nmi_to_offline_cpu: 1;\n\tu32 (*calc_dest_apicid)(unsigned int);\n\tu64 (*icr_read)(void);\n\tvoid (*icr_write)(u32, u32);\n\tu32 max_apic_id;\n\tint (*probe)(void);\n\tvoid (*setup)(void);\n\tvoid (*teardown)(void);\n\tint (*acpi_madt_oem_check)(char *, char *);\n\tvoid (*init_apic_ldr)(void);\n\tu32 (*cpu_present_to_apicid)(int);\n\tu32 (*get_apic_id)(u32);\n\tint (*wakeup_secondary_cpu)(u32, long unsigned int, unsigned int);\n\tint (*wakeup_secondary_cpu_64)(u32, long unsigned int, unsigned int);\n\tvoid (*update_vector)(unsigned int, unsigned int, bool);\n\tchar *name;\n};\n\nstruct irq_cfg {\n\tunsigned int dest_apicid;\n\tunsigned int vector;\n};\n\nstruct apic_chip_data {\n\tstruct irq_cfg hw_irq_cfg;\n\tunsigned int vector;\n\tunsigned int prev_vector;\n\tunsigned int cpu;\n\tunsigned int prev_cpu;\n\tunsigned int irq;\n\tstruct hlist_node clist;\n\tunsigned int move_in_progress: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int can_reserve: 1;\n\tunsigned int has_reserved: 1;\n};\n\nunion apic_ir {\n\tlong unsigned int map[4];\n\tu32 regs[8];\n};\n\nstruct apic_override {\n\tvoid (*eoi)(void);\n\tvoid (*native_eoi)(void);\n\tvoid (*write)(u32, u32);\n\tu32 (*read)(u32);\n\tvoid (*send_IPI)(int, int);\n\tvoid (*send_IPI_mask)(const struct cpumask *, int);\n\tvoid (*send_IPI_mask_allbutself)(const struct cpumask *, int);\n\tvoid (*send_IPI_allbutself)(int);\n\tvoid (*send_IPI_all)(int);\n\tvoid (*send_IPI_self)(int);\n\tu64 (*icr_read)(void);\n\tvoid (*icr_write)(u32, u32);\n\tint (*wakeup_secondary_cpu)(u32, long unsigned int, unsigned int);\n\tint (*wakeup_secondary_cpu_64)(u32, long unsigned int, unsigned int);\n};\n\nstruct apm_bios_info {\n\t__u16 version;\n\t__u16 cseg;\n\t__u32 offset;\n\t__u16 cseg_16;\n\t__u16 dseg;\n\t__u16 flags;\n\t__u16 cseg_len;\n\t__u16 cseg_16_len;\n\t__u16 dseg_len;\n};\n\nstruct apple_backlight_config_report {\n\tu8 report_id;\n\tu8 version;\n\tu16 backlight_off;\n\tu16 backlight_on_min;\n\tu16 backlight_on_max;\n};\n\nstruct apple_backlight_set_report {\n\tu8 report_id;\n\tu8 version;\n\tu16 backlight;\n\tu16 rate;\n};\n\nstruct apple_key_translation {\n\tu16 from;\n\tu16 to;\n\tlong unsigned int flags;\n};\n\nstruct led_pattern;\n\nstruct led_trigger;\n\nstruct led_hw_trigger_type;\n\nstruct led_classdev {\n\tconst char *name;\n\tunsigned int brightness;\n\tunsigned int max_brightness;\n\tunsigned int color;\n\tint flags;\n\tlong unsigned int work_flags;\n\tvoid (*brightness_set)(struct led_classdev *, enum led_brightness);\n\tint (*brightness_set_blocking)(struct led_classdev *, enum led_brightness);\n\tenum led_brightness (*brightness_get)(struct led_classdev *);\n\tint (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *);\n\tint (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int);\n\tint (*pattern_clear)(struct led_classdev *);\n\tstruct device *dev;\n\tconst struct attribute_group **groups;\n\tstruct list_head node;\n\tconst char *default_trigger;\n\tlong unsigned int blink_delay_on;\n\tlong unsigned int blink_delay_off;\n\tstruct timer_list blink_timer;\n\tint blink_brightness;\n\tint new_blink_brightness;\n\tvoid (*flash_resume)(struct led_classdev *);\n\tstruct workqueue_struct *wq;\n\tstruct work_struct set_brightness_work;\n\tint delayed_set_value;\n\tlong unsigned int delayed_delay_on;\n\tlong unsigned int delayed_delay_off;\n\tstruct rw_semaphore trigger_lock;\n\tstruct led_trigger *trigger;\n\tstruct list_head trig_list;\n\tvoid *trigger_data;\n\tbool activated;\n\tstruct led_hw_trigger_type *trigger_type;\n\tconst char *hw_control_trigger;\n\tint (*hw_control_is_supported)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_set)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_get)(struct led_classdev *, long unsigned int *);\n\tstruct device * (*hw_control_get_device)(struct led_classdev *);\n\tstruct mutex led_access;\n};\n\nstruct hid_report;\n\nstruct apple_magic_backlight {\n\tstruct led_classdev cdev;\n\tstruct hid_report *brightness;\n\tstruct hid_report *power;\n};\n\nstruct apple_non_apple_keyboard {\n\tchar *name;\n};\n\nstruct hid_device;\n\nstruct apple_sc_backlight;\n\nstruct apple_sc {\n\tstruct hid_device *hdev;\n\tlong unsigned int quirks;\n\tunsigned int fn_on;\n\tunsigned int fn_found;\n\tlong unsigned int pressed_numlock[12];\n\tstruct timer_list battery_timer;\n\tstruct apple_sc_backlight *backlight;\n};\n\nstruct apple_sc_backlight {\n\tstruct led_classdev cdev;\n\tstruct hid_device *hdev;\n};\n\nstruct apply_range_data {\n\tstruct page **pages;\n\tint i;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct arc4_ctx {\n\tu32 S[256];\n\tu32 x;\n\tu32 y;\n};\n\nstruct arch_elf_state {};\n\nstruct arch_hw_breakpoint {\n\tlong unsigned int address;\n\tlong unsigned int mask;\n\tu8 len;\n\tu8 type;\n};\n\nstruct arch_hybrid_cpu_scale {\n\tlong unsigned int capacity;\n\tlong unsigned int freq_ratio;\n};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct lbr_entry {\n\tu64 from;\n\tu64 to;\n\tu64 info;\n};\n\nstruct arch_lbr_state {\n\tu64 lbr_ctl;\n\tu64 lbr_depth;\n\tu64 ler_from;\n\tu64 ler_to;\n\tu64 ler_info;\n\tstruct lbr_entry entries[0];\n};\n\nstruct arch_optimized_insn {\n\tkprobe_opcode_t copied_insn[4];\n\tkprobe_opcode_t *insn;\n\tsize_t size;\n};\n\nstruct arch_pebs_aux {\n\tu64 address;\n\tu64 rsvd;\n\tu64 rsvd2;\n\tu64 rsvd3;\n\tu64 rsvd4;\n\tu64 aux;\n\tu64 instr_latency: 16;\n\tu64 pad2: 16;\n\tu64 cache_latency: 16;\n\tu64 pad3: 16;\n\tu64 tsx_tuning;\n};\n\nstruct arch_pebs_basic {\n\tu64 ip;\n\tu64 applicable_counters;\n\tu64 tsc;\n\tu64 retire: 16;\n\tu64 valid: 1;\n\tu64 rsvd: 47;\n\tu64 rsvd2;\n\tu64 rsvd3;\n};\n\nstruct arch_pebs_cap {\n\tu64 caps;\n\tu64 counters;\n\tu64 pdists;\n};\n\nstruct arch_pebs_cntr_header {\n\tu32 cntr;\n\tu32 fixed;\n\tu32 metrics;\n\tu32 reserved;\n};\n\nstruct arch_pebs_gprs {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 cx;\n\tu64 dx;\n\tu64 bx;\n\tu64 sp;\n\tu64 bp;\n\tu64 si;\n\tu64 di;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 ssp;\n\tu64 rsvd;\n};\n\nstruct arch_pebs_header {\n\tunion {\n\t\tu64 format;\n\t\tstruct {\n\t\t\tu64 size: 16;\n\t\t\tu64 rsvd: 14;\n\t\t\tu64 mode: 1;\n\t\t\tu64 cont: 1;\n\t\t\tu64 rsvd2: 3;\n\t\t\tu64 cntr: 5;\n\t\t\tu64 lbr: 2;\n\t\t\tu64 rsvd3: 7;\n\t\t\tu64 xmm: 1;\n\t\t\tu64 ymmh: 1;\n\t\t\tu64 rsvd4: 2;\n\t\t\tu64 opmask: 1;\n\t\t\tu64 zmmh: 1;\n\t\t\tu64 h16zmm: 1;\n\t\t\tu64 rsvd5: 5;\n\t\t\tu64 gpr: 1;\n\t\t\tu64 aux: 1;\n\t\t\tu64 basic: 1;\n\t\t};\n\t};\n\tu64 rsvd6;\n};\n\nunion arch_pebs_index {\n\tstruct {\n\t\tu64 rsvd: 4;\n\t\tu64 wr: 23;\n\t\tu64 rsvd2: 4;\n\t\tu64 full: 1;\n\t\tu64 en: 1;\n\t\tu64 rsvd3: 3;\n\t\tu64 thresh: 23;\n\t\tu64 rsvd4: 5;\n\t};\n\tu64 whole;\n};\n\nstruct arch_pebs_lbr_header {\n\tu64 rsvd;\n\tu64 ctl;\n\tu64 depth;\n\tu64 ler_from;\n\tu64 ler_to;\n\tu64 ler_info;\n};\n\nstruct kprobe;\n\nstruct arch_specific_insn {\n\tkprobe_opcode_t *insn;\n\tunsigned int boostable: 1;\n\tunsigned char size;\n\tunion {\n\t\tunsigned char opcode;\n\t\tstruct {\n\t\t\tunsigned char type;\n\t\t} jcc;\n\t\tstruct {\n\t\t\tunsigned char type;\n\t\t\tunsigned char asize;\n\t\t} loop;\n\t\tstruct {\n\t\t\tunsigned char reg;\n\t\t} indirect;\n\t};\n\ts32 rel32;\n\tvoid (*emulate_op)(struct kprobe *, struct pt_regs *);\n\tint tp_len;\n};\n\nstruct arch_tlbflush_unmap_batch {\n\tstruct cpumask cpumask;\n\tbool unmapped_pages;\n};\n\nstruct uprobe_xol_ops;\n\nstruct arch_uprobe {\n\tunion {\n\t\tu8 insn[16];\n\t\tu8 ixol[16];\n\t};\n\tconst struct uprobe_xol_ops *ops;\n\tunion {\n\t\tstruct {\n\t\t\ts32 offs;\n\t\t\tu8 ilen;\n\t\t\tu8 opc1;\n\t\t} branch;\n\t\tstruct {\n\t\t\tu8 fixups;\n\t\t\tu8 ilen;\n\t\t} defparam;\n\t\tstruct {\n\t\t\tu8 reg_offset;\n\t\t\tu8 ilen;\n\t\t} push;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct arch_uprobe_task {\n\tlong unsigned int saved_scratch_register;\n\tunsigned int saved_trap_nr;\n\tunsigned int saved_tf;\n};\n\nstruct sysv_va_list {\n\tunsigned int gp_offset;\n\tunsigned int fp_offset;\n\tvoid *overflow_arg_area;\n\tvoid *reg_save_area;\n};\n\nstruct arch_va_list {\n\tlong unsigned int regs[6];\n\tstruct sysv_va_list args;\n};\n\nstruct arch_vdso_time_data {};\n\nstruct arena_free_span {\n\tstruct llist_node node;\n\tlong unsigned int uaddr;\n\tu32 page_cnt;\n};\n\nstruct arg_dev_net_ip {\n\tstruct net *net;\n\tstruct in6_addr *addr;\n};\n\nstruct arg_netdev_event {\n\tconst struct net_device *dev;\n\tunion {\n\t\tunsigned char nh_flags;\n\t\tlong unsigned int event;\n\t};\n};\n\nstruct args_askumount {\n\t__u32 may_umount;\n};\n\nstruct args_expire {\n\t__u32 how;\n};\n\nstruct args_fail {\n\t__u32 token;\n\t__s32 status;\n};\n\nstruct args_in {\n\t__u32 type;\n};\n\nstruct args_out {\n\t__u32 devid;\n\t__u32 magic;\n};\n\nstruct args_ismountpoint {\n\tunion {\n\t\tstruct args_in in;\n\t\tstruct args_out out;\n\t};\n};\n\nstruct args_openmount {\n\t__u32 devid;\n};\n\nstruct args_protosubver {\n\t__u32 sub_version;\n};\n\nstruct args_protover {\n\t__u32 version;\n};\n\nstruct args_ready {\n\t__u32 token;\n};\n\nstruct args_requester {\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct args_setpipefd {\n\t__s32 pipefd;\n};\n\nstruct args_timeout {\n\t__u64 timeout;\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct trace_array;\n\nstruct trace_buffer;\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tu64 time_start;\n\tint cpu;\n};\n\ntypedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t);\n\nstruct asn1_decoder {\n\tconst unsigned char *machine;\n\tsize_t machlen;\n\tconst asn1_action_t *actions;\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct asymmetric_key_id {\n\tshort unsigned int len;\n\tunsigned char data[0];\n};\n\nstruct asymmetric_key_ids {\n\tvoid *id[3];\n};\n\nstruct key_preparsed_payload;\n\nstruct asymmetric_key_parser {\n\tstruct list_head link;\n\tstruct module *owner;\n\tconst char *name;\n\tint (*parse)(struct key_preparsed_payload *);\n};\n\nstruct key;\n\nstruct seq_file;\n\nstruct kernel_pkey_params;\n\nstruct kernel_pkey_query;\n\nstruct public_key_signature;\n\nstruct asymmetric_key_subtype {\n\tstruct module *owner;\n\tconst char *name;\n\tshort unsigned int name_len;\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tvoid (*destroy)(void *, void *);\n\tint (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*verify_signature)(const struct key *, const struct public_key_signature *);\n};\n\nstruct usb_dev_state;\n\nstruct pid;\n\nstruct urb;\n\nstruct usb_memory;\n\nstruct async {\n\tstruct list_head asynclist;\n\tstruct usb_dev_state *ps;\n\tstruct pid *pid;\n\tconst struct cred *cred;\n\tunsigned int signr;\n\tunsigned int ifnum;\n\tvoid *userbuffer;\n\tvoid *userurb;\n\tsigval_t userurb_sigval;\n\tstruct urb *urb;\n\tstruct usb_memory *usbm;\n\tunsigned int mem_usage;\n\tint status;\n\tu8 bulk_addr;\n\tu8 bulk_status;\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct ata_acpi_drive {\n\tu32 pio;\n\tu32 dma;\n};\n\nstruct ata_acpi_gtf {\n\tu8 tf[7];\n};\n\nstruct ata_acpi_gtm {\n\tstruct ata_acpi_drive drive[2];\n\tu32 flags;\n};\n\nstruct ata_device;\n\nstruct ata_acpi_hotplug_context {\n\tstruct acpi_hotplug_context hp;\n\tunion {\n\t\tstruct ata_port *ap;\n\t\tstruct ata_device *dev;\n\t} data;\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nstruct ata_cdl {\n\tu8 desc_log_buf[512];\n\tu8 ncq_sense_log_buf[1024];\n};\n\nstruct ata_cpr {\n\tu8 num;\n\tu8 num_storage_elements;\n\tu64 start_lba;\n\tu64 num_lbas;\n};\n\nstruct ata_cpr_log {\n\tu8 nr_cpr;\n\tstruct ata_cpr cpr[0];\n};\n\nstruct ata_dev_quirk_value {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 val;\n};\n\nstruct ata_dev_quirks_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 quirks;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tu64 quirks;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tunion acpi_object *gtf_cache;\n\tunsigned int gtf_filter;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 gp_log_dir[512];\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tstruct ata_cpr_log *cpr_log;\n\tstruct ata_cdl *cdl;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 sector_buf[512];\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst unsigned int *timeouts;\n};\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[16];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tu64 value;\n\tu8 cbl;\n\tu8 spd_limit;\n\tunsigned int xfer_mask;\n\tu64 quirk_on;\n\tu64 quirk_off;\n\tunsigned int pflags_on;\n\tu16 lflags_on;\n\tu16 lflags_off;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tunion {\n\t\tu8 error;\n\t\tu8 feature;\n\t};\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tunion {\n\t\tu8 status;\n\t\tu8 command;\n\t};\n\tu32 auxiliary;\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct scsi_cmnd;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tu64 qc_active;\n\tint nr_active_links;\n\tstruct work_struct deferred_qc_work;\n\tstruct ata_queued_cmd *deferred_qc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct delayed_work scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tunsigned int fastdrain_cnt;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tstruct ata_acpi_gtm __acpi_init_gtm;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nstruct ata_reset_operations {\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tvoid (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tvoid (*qc_ncq_fill_rtf)(struct ata_port *, u64);\n\tint (*cable_detect)(struct ata_port *);\n\tunsigned int (*mode_filter)(struct ata_device *, unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, __le16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tstruct ata_reset_operations reset;\n\tstruct ata_reset_operations pmp_reset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nstruct ata_timing {\n\tshort unsigned int mode;\n\tshort unsigned int setup;\n\tshort unsigned int act8b;\n\tshort unsigned int rec8b;\n\tshort unsigned int cyc8b;\n\tshort unsigned int active;\n\tshort unsigned int recover;\n\tshort unsigned int dmack_hold;\n\tshort unsigned int cycle;\n\tshort unsigned int udma;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ps2dev;\n\ntypedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int);\n\ntypedef void (*ps2_receive_handler_t)(struct ps2dev *, u8);\n\nstruct serio;\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n\tps2_pre_receive_handler_t pre_receive_handler;\n\tps2_receive_handler_t receive_handler;\n};\n\nstruct vivaldi_data {\n\tu32 function_row_physmap[24];\n\tunsigned int num_function_row_keys;\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[8];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tstruct vivaldi_data vdata;\n};\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct aud_ts_cdclk_m_n {\n\tu8 m;\n\tu16 n;\n};\n\nstruct audit_aux_data {\n\tstruct audit_aux_data *next;\n\tint type;\n};\n\nstruct audit_cap_data {\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n\tunion {\n\t\tunsigned int fE;\n\t\tkernel_cap_t effective;\n\t};\n\tkernel_cap_t ambient;\n\tkuid_t rootid;\n};\n\nstruct audit_aux_data_bprm_fcaps {\n\tstruct audit_aux_data d;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tstruct audit_cap_data old_pcap;\n\tstruct audit_cap_data new_pcap;\n};\n\nstruct lsm_prop_selinux {\n\tu32 secid;\n};\n\nstruct lsm_prop_smack {};\n\nstruct lsm_prop_apparmor {};\n\nstruct lsm_prop_bpf {};\n\nstruct lsm_prop {\n\tstruct lsm_prop_selinux selinux;\n\tstruct lsm_prop_smack smack;\n\tstruct lsm_prop_apparmor apparmor;\n\tstruct lsm_prop_bpf bpf;\n};\n\nstruct audit_aux_data_pids {\n\tstruct audit_aux_data d;\n\tpid_t target_pid[16];\n\tkuid_t target_auid[16];\n\tkuid_t target_uid[16];\n\tunsigned int target_sessionid[16];\n\tstruct lsm_prop target_ref[16];\n\tchar target_comm[256];\n\tint pid_count;\n};\n\nstruct audit_stamp {\n\tstruct timespec64 ctime;\n\tunsigned int serial;\n};\n\nstruct audit_context;\n\nstruct audit_buffer {\n\tstruct sk_buff *skb;\n\tstruct sk_buff_head skb_list;\n\tstruct audit_context *ctx;\n\tstruct audit_stamp stamp;\n\tgfp_t gfp_mask;\n};\n\nstruct audit_tree;\n\nstruct audit_node {\n\tstruct list_head list;\n\tstruct audit_tree *owner;\n\tunsigned int index;\n};\n\nstruct fsnotify_mark;\n\nstruct audit_chunk {\n\tstruct list_head hash;\n\tlong unsigned int key;\n\tstruct fsnotify_mark *mark;\n\tstruct list_head trees;\n\tint count;\n\tatomic_long_t refs;\n\tstruct callback_head head;\n\tstruct audit_node owners[0];\n};\n\nstruct filename;\n\nstruct audit_names {\n\tstruct list_head list;\n\tstruct filename *name;\n\tint name_len;\n\tbool hidden;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tstruct lsm_prop oprop;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tunsigned char type;\n\tbool should_free;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct mq_attr {\n\t__kernel_long_t mq_flags;\n\t__kernel_long_t mq_maxmsg;\n\t__kernel_long_t mq_msgsize;\n\t__kernel_long_t mq_curmsgs;\n\t__kernel_long_t __reserved[4];\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct audit_proctitle {\n\tint len;\n\tchar *value;\n};\n\nstruct audit_tree_refs;\n\nstruct audit_context {\n\tint dummy;\n\tenum {\n\t\tAUDIT_CTX_UNUSED = 0,\n\t\tAUDIT_CTX_SYSCALL = 1,\n\t\tAUDIT_CTX_URING = 2,\n\t} context;\n\tenum audit_state state;\n\tenum audit_state current_state;\n\tstruct audit_stamp stamp;\n\tint major;\n\tint uring_op;\n\tlong unsigned int argv[4];\n\tlong int return_code;\n\tu64 prio;\n\tint return_valid;\n\tstruct audit_names preallocated_names[5];\n\tint name_count;\n\tstruct list_head names_list;\n\tchar *filterkey;\n\tstruct path pwd;\n\tstruct audit_aux_data *aux;\n\tstruct audit_aux_data *aux_pids;\n\tstruct __kernel_sockaddr_storage *sockaddr;\n\tsize_t sockaddr_len;\n\tpid_t ppid;\n\tkuid_t uid;\n\tkuid_t euid;\n\tkuid_t suid;\n\tkuid_t fsuid;\n\tkgid_t gid;\n\tkgid_t egid;\n\tkgid_t sgid;\n\tkgid_t fsgid;\n\tlong unsigned int personality;\n\tint arch;\n\tpid_t target_pid;\n\tkuid_t target_auid;\n\tkuid_t target_uid;\n\tunsigned int target_sessionid;\n\tstruct lsm_prop target_ref;\n\tchar target_comm[16];\n\tstruct audit_tree_refs *trees;\n\tstruct audit_tree_refs *first_trees;\n\tstruct list_head killed_trees;\n\tint tree_count;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tint nargs;\n\t\t\tlong int args[6];\n\t\t} socketcall;\n\t\tstruct {\n\t\t\tkuid_t uid;\n\t\t\tkgid_t gid;\n\t\t\tumode_t mode;\n\t\t\tstruct lsm_prop oprop;\n\t\t\tint has_perm;\n\t\t\tuid_t perm_uid;\n\t\t\tgid_t perm_gid;\n\t\t\tumode_t perm_mode;\n\t\t\tlong unsigned int qbytes;\n\t\t} ipc;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tstruct mq_attr mqstat;\n\t\t} mq_getsetattr;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tint sigev_signo;\n\t\t} mq_notify;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tsize_t msg_len;\n\t\t\tunsigned int msg_prio;\n\t\t\tstruct timespec64 abs_timeout;\n\t\t} mq_sendrecv;\n\t\tstruct {\n\t\t\tint oflag;\n\t\t\tumode_t mode;\n\t\t\tstruct mq_attr attr;\n\t\t} mq_open;\n\t\tstruct {\n\t\t\tpid_t pid;\n\t\t\tstruct audit_cap_data cap;\n\t\t} capset;\n\t\tstruct {\n\t\t\tint fd;\n\t\t\tint flags;\n\t\t} mmap;\n\t\tstruct open_how openat2;\n\t\tstruct {\n\t\t\tint argc;\n\t\t} execve;\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t} module;\n\t\tstruct {\n\t\t\tstruct audit_ntp_data ntp_data;\n\t\t\tstruct timespec64 tk_injoffset;\n\t\t} time;\n\t};\n\tint fds[2];\n\tstruct audit_proctitle proctitle;\n};\n\nstruct audit_ctl_mutex {\n\tstruct mutex lock;\n\tvoid *owner;\n};\n\nstruct audit_field;\n\nstruct audit_watch;\n\nstruct audit_fsnotify_mark;\n\nstruct audit_krule {\n\tu32 pflags;\n\tu32 flags;\n\tu32 listnr;\n\tu32 action;\n\tu32 mask[64];\n\tu32 buflen;\n\tu32 field_count;\n\tchar *filterkey;\n\tstruct audit_field *fields;\n\tstruct audit_field *arch_f;\n\tstruct audit_field *inode_f;\n\tstruct audit_watch *watch;\n\tstruct audit_tree *tree;\n\tstruct audit_fsnotify_mark *exe;\n\tstruct list_head rlist;\n\tstruct list_head list;\n\tu64 prio;\n};\n\nstruct audit_entry {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tstruct audit_krule rule;\n};\n\nstruct audit_features {\n\t__u32 vers;\n\t__u32 mask;\n\t__u32 features;\n\t__u32 lock;\n};\n\nstruct audit_field {\n\tu32 type;\n\tunion {\n\t\tu32 val;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tstruct {\n\t\t\tchar *lsm_str;\n\t\t\tvoid *lsm_rule;\n\t\t};\n\t};\n\tu32 op;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark_connector;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct audit_fsnotify_mark {\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar *path;\n\tstruct fsnotify_mark mark;\n\tstruct audit_krule *rule;\n};\n\nstruct sock;\n\nstruct audit_net {\n\tstruct sock *sk;\n};\n\nstruct audit_netlink_list {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff_head q;\n};\n\nstruct audit_nfcfgop_tab {\n\tenum audit_nfcfgop op;\n\tconst char *s;\n};\n\nstruct audit_parent {\n\tstruct list_head watches;\n\tstruct fsnotify_mark mark;\n};\n\nstruct audit_reply {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff *skb;\n};\n\nstruct audit_rule_data {\n\t__u32 flags;\n\t__u32 action;\n\t__u32 field_count;\n\t__u32 mask[64];\n\t__u32 fields[64];\n\t__u32 values[64];\n\t__u32 fieldflags[64];\n\t__u32 buflen;\n\tchar buf[0];\n};\n\nstruct audit_sig_info {\n\tuid_t uid;\n\tpid_t pid;\n\tchar ctx[0];\n};\n\nstruct audit_status {\n\t__u32 mask;\n\t__u32 enabled;\n\t__u32 failure;\n\t__u32 pid;\n\t__u32 rate_limit;\n\t__u32 backlog_limit;\n\t__u32 lost;\n\t__u32 backlog;\n\tunion {\n\t\t__u32 version;\n\t\t__u32 feature_bitmap;\n\t};\n\t__u32 backlog_wait_time;\n\t__u32 backlog_wait_time_actual;\n};\n\nstruct audit_tree {\n\trefcount_t count;\n\tint goner;\n\tstruct audit_chunk *root;\n\tstruct list_head chunks;\n\tstruct list_head rules;\n\tstruct list_head list;\n\tstruct list_head same_root;\n\tstruct callback_head head;\n\tchar pathname[0];\n};\n\nstruct audit_tree_mark {\n\tstruct fsnotify_mark mark;\n\tstruct audit_chunk *chunk;\n};\n\nstruct audit_tree_refs {\n\tstruct audit_tree_refs *next;\n\tstruct audit_chunk *c[31];\n};\n\nstruct audit_tty_status {\n\t__u32 enabled;\n\t__u32 log_passwd;\n};\n\nstruct audit_watch {\n\trefcount_t count;\n\tdev_t dev;\n\tchar *path;\n\tlong unsigned int ino;\n\tstruct audit_parent *parent;\n\tstruct list_head wlist;\n\tstruct list_head rules;\n};\n\nstruct auditd_connection {\n\tstruct pid *pid;\n\tu32 portid;\n\tstruct net *net;\n\tstruct callback_head rcu;\n};\n\nstruct auth_cred {\n\tconst struct cred *cred;\n\tconst char *principal;\n};\n\nstruct auth_ops;\n\nstruct auth_domain {\n\tstruct kref ref;\n\tstruct hlist_node hash;\n\tchar *name;\n\tstruct auth_ops *flavour;\n\tstruct callback_head callback_head;\n};\n\nstruct svc_rqst;\n\nstruct auth_ops {\n\tchar *name;\n\tstruct module *owner;\n\tint flavour;\n\tenum svc_auth_status (*accept)(struct svc_rqst *);\n\tint (*release)(struct svc_rqst *);\n\tvoid (*domain_release)(struct auth_domain *);\n\tenum svc_auth_status (*set_client)(struct svc_rqst *);\n\trpc_authflavor_t (*pseudoflavor)(struct svc_rqst *);\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct authenc_esn_instance_ctx {\n\tstruct crypto_ahash_spawn auth;\n\tstruct crypto_skcipher_spawn enc;\n};\n\nstruct authenc_esn_request_ctx {\n\tstruct scatterlist src[2];\n\tstruct scatterlist dst[2];\n\tchar tail[0];\n};\n\nstruct authenc_instance_ctx {\n\tstruct crypto_ahash_spawn auth;\n\tstruct crypto_skcipher_spawn enc;\n\tunsigned int reqoff;\n};\n\nstruct authenc_request_ctx {\n\tstruct scatterlist src[2];\n\tstruct scatterlist dst[2];\n\tchar tail[0];\n};\n\nstruct i915_active {\n\tatomic_t count;\n\tstruct mutex mutex;\n\tspinlock_t tree_lock;\n\tstruct active_node *cache;\n\tstruct rb_root tree;\n\tstruct i915_active_fence excl;\n\tlong unsigned int flags;\n\tint (*active)(struct i915_active *);\n\tvoid (*retire)(struct i915_active *);\n\tstruct work_struct work;\n\tstruct llist_head preallocated_barriers;\n};\n\nstruct auto_active {\n\tstruct i915_active base;\n\tstruct kref ref;\n};\n\nstruct auto_out_pin {\n\thda_nid_t pin;\n\tshort int seq;\n};\n\nstruct auto_pin_cfg_item {\n\thda_nid_t pin;\n\tint type;\n\tunsigned int is_headset_mic: 1;\n\tunsigned int is_headphone_mic: 1;\n\tunsigned int has_boost_on_pin: 1;\n\tint order;\n};\n\nstruct auto_pin_cfg {\n\tint line_outs;\n\thda_nid_t line_out_pins[5];\n\tint speaker_outs;\n\thda_nid_t speaker_pins[5];\n\tint hp_outs;\n\tint line_out_type;\n\thda_nid_t hp_pins[5];\n\tint num_inputs;\n\tstruct auto_pin_cfg_item inputs[18];\n\tint dig_outs;\n\thda_nid_t dig_out_pins[2];\n\thda_nid_t dig_in_pin;\n\thda_nid_t mono_out_pin;\n\tint dig_out_type[2];\n\tint dig_in_type;\n};\n\nstruct autofs_dev_ioctl {\n\t__u32 ver_major;\n\t__u32 ver_minor;\n\t__u32 size;\n\t__s32 ioctlfd;\n\tunion {\n\t\tstruct args_protover protover;\n\t\tstruct args_protosubver protosubver;\n\t\tstruct args_openmount openmount;\n\t\tstruct args_ready ready;\n\t\tstruct args_fail fail;\n\t\tstruct args_setpipefd setpipefd;\n\t\tstruct args_timeout timeout;\n\t\tstruct args_requester requester;\n\t\tstruct args_expire expire;\n\t\tstruct args_askumount askumount;\n\t\tstruct args_ismountpoint ismountpoint;\n\t};\n\tchar path[0];\n};\n\nstruct autofs_fs_context {\n\tkuid_t uid;\n\tkgid_t gid;\n\tint pgrp;\n\tbool pgrp_set;\n};\n\nstruct autofs_sb_info;\n\nstruct autofs_info {\n\tstruct dentry *dentry;\n\tint flags;\n\tstruct completion expire_complete;\n\tstruct list_head active;\n\tstruct list_head expiring;\n\tstruct autofs_sb_info *sbi;\n\tlong unsigned int exp_timeout;\n\tlong unsigned int last_used;\n\tint count;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_packet_hdr {\n\tint proto_version;\n\tint type;\n};\n\nstruct autofs_packet_expire {\n\tstruct autofs_packet_hdr hdr;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_expire_multi {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_missing {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nunion autofs_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_packet_missing missing;\n\tstruct autofs_packet_expire expire;\n\tstruct autofs_packet_expire_multi expire_multi;\n};\n\nstruct super_block;\n\nstruct autofs_wait_queue;\n\nstruct autofs_sb_info {\n\tu32 magic;\n\tint pipefd;\n\tstruct file *pipe;\n\tstruct pid *oz_pgrp;\n\tu64 mnt_ns_id;\n\tint version;\n\tint sub_version;\n\tint min_proto;\n\tint max_proto;\n\tunsigned int flags;\n\tlong unsigned int exp_timeout;\n\tunsigned int type;\n\tstruct super_block *sb;\n\tstruct mutex wq_mutex;\n\tstruct mutex pipe_mutex;\n\tspinlock_t fs_lock;\n\tstruct autofs_wait_queue *queues;\n\tspinlock_t lookup_lock;\n\tstruct list_head active_list;\n\tstruct list_head expiring_list;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_v5_packet {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\t__u32 dev;\n\t__u64 ino;\n\t__u32 uid;\n\t__u32 gid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 len;\n\tchar name[256];\n};\n\ntypedef struct autofs_v5_packet autofs_packet_expire_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_expire_indirect_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_indirect_t;\n\nunion autofs_v5_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_v5_packet v5_packet;\n\tautofs_packet_missing_indirect_t missing_indirect;\n\tautofs_packet_expire_indirect_t expire_indirect;\n\tautofs_packet_missing_direct_t missing_direct;\n\tautofs_packet_expire_direct_t expire_direct;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n};\n\nstruct autofs_wait_queue {\n\twait_queue_head_t queue;\n\tstruct autofs_wait_queue *next;\n\tautofs_wqt_t wait_queue_token;\n\tstruct qstr name;\n\tu32 offset;\n\tu32 dev;\n\tu64 ino;\n\tkuid_t uid;\n\tkgid_t gid;\n\tpid_t pid;\n\tpid_t tgid;\n\tint status;\n\tunsigned int wait_ctr;\n};\n\nstruct auxiliary_device {\n\tstruct device dev;\n\tconst char *name;\n\tu32 id;\n\tstruct {\n\t\tstruct xarray irqs;\n\t\tstruct mutex lock;\n\t\tbool irq_dir_exists;\n\t} sysfs;\n};\n\nstruct auxiliary_device_id {\n\tchar name[40];\n\tkernel_ulong_t driver_data;\n};\n\nstruct auxiliary_driver {\n\tint (*probe)(struct auxiliary_device *, const struct auxiliary_device_id *);\n\tvoid (*remove)(struct auxiliary_device *);\n\tvoid (*shutdown)(struct auxiliary_device *);\n\tint (*suspend)(struct auxiliary_device *, pm_message_t);\n\tint (*resume)(struct auxiliary_device *);\n\tconst char *name;\n\tstruct device_driver driver;\n\tconst struct auxiliary_device_id *id_table;\n};\n\nstruct auxiliary_irq_info {\n\tstruct device_attribute sysfs_attr;\n\tchar name[11];\n};\n\nstruct av_decision {\n\tu32 allowed;\n\tu32 auditallow;\n\tu32 auditdeny;\n\tu32 seqno;\n\tu32 flags;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct avc_cache {\n\tstruct hlist_head slots[512];\n\tspinlock_t slots_lock[512];\n\tatomic_t lru_hint;\n\tatomic_t active_nodes;\n\tu32 latest_notif;\n};\n\nstruct avc_cache_stats {\n\tunsigned int lookups;\n\tunsigned int misses;\n\tunsigned int allocations;\n\tunsigned int reclaims;\n\tunsigned int frees;\n};\n\nstruct avc_callback_node {\n\tint (*callback)(u32);\n\tu32 events;\n\tstruct avc_callback_node *next;\n};\n\nstruct avc_xperms_node;\n\nstruct avc_entry {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tstruct av_decision avd;\n\tstruct avc_xperms_node *xp_node;\n};\n\nstruct avc_node {\n\tstruct avc_entry ae;\n\tstruct hlist_node list;\n\tstruct callback_head rhead;\n};\n\nstruct extended_perms_data;\n\nstruct extended_perms_decision {\n\tu8 used;\n\tu8 driver;\n\tu8 base_perm;\n\tstruct extended_perms_data *allowed;\n\tstruct extended_perms_data *auditallow;\n\tstruct extended_perms_data *dontaudit;\n};\n\nstruct avc_xperms_decision_node {\n\tstruct extended_perms_decision xpd;\n\tstruct list_head xpd_list;\n};\n\nstruct extended_perms_data {\n\tu32 p[8];\n};\n\nstruct extended_perms {\n\tu16 len;\n\tu8 base_perms;\n\tstruct extended_perms_data drivers;\n};\n\nstruct avc_xperms_node {\n\tstruct extended_perms xp;\n\tstruct list_head xpd_head;\n};\n\nstruct avdc_entry {\n\tu32 isid;\n\tu32 allowed;\n\tu32 audited;\n\tbool permissive;\n};\n\nstruct avtab_node;\n\nstruct avtab {\n\tstruct avtab_node **htable;\n\tu32 nel;\n\tu32 nslot;\n\tu32 mask;\n};\n\nstruct avtab_extended_perms;\n\nstruct avtab_datum {\n\tunion {\n\t\tu32 data;\n\t\tstruct avtab_extended_perms *xperms;\n\t} u;\n};\n\nstruct avtab_extended_perms {\n\tu8 specified;\n\tu8 driver;\n\tstruct extended_perms_data perms;\n};\n\nstruct avtab_key {\n\tu16 source_type;\n\tu16 target_type;\n\tu16 target_class;\n\tu16 specified;\n};\n\nstruct avtab_node {\n\tstruct avtab_key key;\n\tstruct avtab_datum datum;\n\tstruct avtab_node *next;\n};\n\nstruct hdac_rb {\n\t__le32 *buf;\n\tdma_addr_t addr;\n\tshort unsigned int rp;\n\tshort unsigned int wp;\n\tint cmds[8];\n\tu32 res[8];\n};\n\nstruct snd_dma_device {\n\tint type;\n\tenum dma_data_direction dir;\n\tbool need_sync;\n\tstruct device *dev;\n};\n\nstruct snd_dma_buffer {\n\tstruct snd_dma_device dev;\n\tunsigned char *area;\n\tdma_addr_t addr;\n\tsize_t bytes;\n\tvoid *private_data;\n};\n\nstruct hdac_bus_ops;\n\nstruct hdac_ext_bus_ops;\n\nstruct hdac_device;\n\nstruct drm_audio_component;\n\nstruct hdac_bus {\n\tstruct device *dev;\n\tconst struct hdac_bus_ops *ops;\n\tconst struct hdac_ext_bus_ops *ext_ops;\n\tlong unsigned int addr;\n\tvoid *remap_addr;\n\tint irq;\n\tvoid *ppcap;\n\tvoid *spbcap;\n\tvoid *mlcap;\n\tvoid *gtscap;\n\tvoid *drsmcap;\n\tstruct list_head codec_list;\n\tunsigned int num_codecs;\n\tstruct hdac_device *caddr_tbl[16];\n\tu32 unsol_queue[128];\n\tunsigned int unsol_rp;\n\tunsigned int unsol_wp;\n\tstruct work_struct unsol_work;\n\tlong unsigned int codec_mask;\n\tlong unsigned int codec_powered;\n\tstruct hdac_rb corb;\n\tstruct hdac_rb rirb;\n\tunsigned int last_cmd[8];\n\twait_queue_head_t rirb_wq;\n\tstruct snd_dma_buffer rb;\n\tstruct snd_dma_buffer posbuf;\n\tint dma_type;\n\tstruct list_head stream_list;\n\tbool chip_init: 1;\n\tbool aligned_mmio: 1;\n\tbool sync_write: 1;\n\tbool use_posbuf: 1;\n\tbool snoop: 1;\n\tbool align_bdle_4k: 1;\n\tbool reverse_assign: 1;\n\tbool corbrp_self_clear: 1;\n\tbool polling_mode: 1;\n\tbool needs_damn_long_delay: 1;\n\tbool not_use_interrupts: 1;\n\tbool access_sdnctl_in_dword: 1;\n\tbool use_pio_for_commands: 1;\n\tint poll_count;\n\tint bdl_pos_adj;\n\tunsigned int dma_stop_delay;\n\tspinlock_t reg_lock;\n\tstruct mutex cmd_mutex;\n\tstruct mutex lock;\n\tstruct drm_audio_component *audio_component;\n\tlong int display_power_status;\n\tlong unsigned int display_power_active;\n\tint num_streams;\n\tint idx;\n\tstruct list_head hlink_list;\n\tbool cmd_dma_state;\n\tunsigned int sdo_limit;\n\tdma_addr_t addr_offset;\n};\n\nstruct snd_card;\n\nstruct hda_bus {\n\tstruct hdac_bus core;\n\tstruct snd_card *card;\n\tstruct pci_dev *pci;\n\tconst char *modelname;\n\tstruct mutex prepare_mutex;\n\tlong unsigned int pcm_dev_bits[1];\n\tunsigned int allow_bus_reset: 1;\n\tunsigned int shutdown: 1;\n\tunsigned int response_reset: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int no_response_fallback: 1;\n\tunsigned int bus_probing: 1;\n\tunsigned int keep_power: 1;\n\tunsigned int jackpoll_in_suspend: 1;\n\tint primary_dig_out_type;\n\tunsigned int mixer_assigned;\n};\n\nstruct azx;\n\nstruct azx_dev;\n\ntypedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);\n\ntypedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int);\n\nstruct hda_controller_ops;\n\nstruct azx {\n\tstruct hda_bus bus;\n\tstruct snd_card *card;\n\tstruct pci_dev *pci;\n\tint dev_index;\n\tint driver_type;\n\tunsigned int driver_caps;\n\tint playback_streams;\n\tint playback_index_offset;\n\tint capture_streams;\n\tint capture_index_offset;\n\tint num_streams;\n\tint jackpoll_interval;\n\tconst struct hda_controller_ops *ops;\n\tazx_get_pos_callback_t get_position[2];\n\tazx_get_delay_callback_t get_delay[2];\n\tstruct mutex open_mutex;\n\tstruct list_head pcm_list;\n\tint codec_probe_mask;\n\tunsigned int beep_mode;\n\tbool ctl_dev_id;\n\tint bdl_pos_adj;\n\tunsigned int running: 1;\n\tunsigned int fallback_to_single_cmd: 1;\n\tunsigned int single_cmd: 1;\n\tunsigned int msi: 1;\n\tunsigned int probing: 1;\n\tunsigned int snoop: 1;\n\tunsigned int uc_buffer: 1;\n\tunsigned int align_buffer_size: 1;\n\tunsigned int disabled: 1;\n\tunsigned int pm_prepared: 1;\n\tunsigned int gts_present: 1;\n};\n\nstruct cyclecounter;\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct snd_compr_stream;\n\nstruct hdac_stream {\n\tstruct hdac_bus *bus;\n\tstruct snd_dma_buffer bdl;\n\t__le32 *posbuf;\n\tint direction;\n\tunsigned int bufsize;\n\tunsigned int period_bytes;\n\tunsigned int frags;\n\tunsigned int fifo_size;\n\tvoid *sd_addr;\n\tvoid *spib_addr;\n\tvoid *fifo_addr;\n\tvoid *dpibr_addr;\n\tu32 dpib;\n\tu32 lpib;\n\tu32 sd_int_sta_mask;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_compr_stream *cstream;\n\tunsigned int format_val;\n\tunsigned char stream_tag;\n\tunsigned char index;\n\tint assigned_key;\n\tbool opened: 1;\n\tbool running: 1;\n\tbool prepared: 1;\n\tbool no_period_wakeup: 1;\n\tbool locked: 1;\n\tbool stripe: 1;\n\tu64 curr_pos;\n\tlong unsigned int start_wallclk;\n\tlong unsigned int period_wallclk;\n\tstruct timecounter tc;\n\tstruct cyclecounter cc;\n\tint delay_negative_threshold;\n\tstruct list_head list;\n};\n\nstruct azx_dev {\n\tstruct hdac_stream core;\n\tunsigned int irq_pending: 1;\n\tunsigned int insufficient: 1;\n};\n\nstruct snd_pcm;\n\nstruct hda_pcm;\n\nstruct azx_pcm {\n\tstruct azx *chip;\n\tstruct snd_pcm *pcm;\n\tstruct hda_codec *codec;\n\tstruct hda_pcm *info;\n\tstruct list_head list;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct backing_dev_info;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tloff_t prev_pos;\n};\n\nstruct file_operations;\n\nstruct fown_struct;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\tvoid *f_security;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backlight_properties {\n\tint brightness;\n\tint max_brightness;\n\tint power;\n\tenum backlight_type type;\n\tunsigned int state;\n\tenum backlight_scale scale;\n};\n\nstruct backlight_ops;\n\nstruct backlight_device {\n\tstruct backlight_properties props;\n\tstruct mutex update_lock;\n\tstruct mutex ops_lock;\n\tconst struct backlight_ops *ops;\n\tstruct list_head entry;\n\tstruct device dev;\n\tint use_count;\n};\n\nstruct backlight_ops {\n\tunsigned int options;\n\tint (*update_status)(struct backlight_device *);\n\tint (*get_brightness)(struct backlight_device *);\n\tbool (*controls_device)(struct backlight_device *, struct device *);\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct i915_vma;\n\nstruct batch_chunk {\n\tstruct i915_vma *vma;\n\tu32 offset;\n\tu32 *start;\n\tu32 *end;\n\tu32 max_items;\n};\n\nstruct local_lock {};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_vals {\n\tu32 max_threads;\n\tu32 state_start;\n\tu32 surface_start;\n\tu32 surface_height;\n\tu32 surface_width;\n\tu32 size;\n};\n\nstruct bd_holder_disk {\n\tstruct list_head list;\n\tstruct kobject *holder_dir;\n\tint refcnt;\n};\n\nstruct bdb_block_entry {\n\tstruct list_head node;\n\tenum bdb_block_id section_id;\n\tu8 data[0];\n};\n\nstruct dsc_compression_parameters_entry {\n\tu8 version_major: 4;\n\tu8 version_minor: 4;\n\tu8 rc_buffer_block_size: 2;\n\tu8 reserved1: 6;\n\tu8 rc_buffer_size;\n\tu32 slices_per_line;\n\tu8 line_buffer_depth: 4;\n\tu8 reserved2: 4;\n\tu8 block_prediction_enable: 1;\n\tu8 reserved3: 7;\n\tu8 max_bpp;\n\tu8 reserved4: 1;\n\tu8 support_8bpc: 1;\n\tu8 support_10bpc: 1;\n\tu8 support_12bpc: 1;\n\tu8 reserved5: 4;\n\tu16 slice_height;\n} __attribute__((packed));\n\nstruct bdb_compression_parameters {\n\tu16 entry_size;\n\tstruct dsc_compression_parameters_entry data[16];\n};\n\nstruct bdb_driver_features {\n\tu8 boot_dev_algorithm: 1;\n\tu8 allow_display_switch_dvd: 1;\n\tu8 allow_display_switch_dos: 1;\n\tu8 hotplug_dvo: 1;\n\tu8 dual_view_zoom: 1;\n\tu8 int15h_hook: 1;\n\tu8 sprite_in_clone: 1;\n\tu8 primary_lfp_id: 1;\n\tu16 boot_mode_x;\n\tu16 boot_mode_y;\n\tu8 boot_mode_bpp;\n\tu8 boot_mode_refresh;\n\tu16 enable_lfp_primary: 1;\n\tu16 selective_mode_pruning: 1;\n\tu16 dual_frequency: 1;\n\tu16 render_clock_freq: 1;\n\tu16 nt_clone_support: 1;\n\tu16 power_scheme_ui: 1;\n\tu16 sprite_display_assign: 1;\n\tu16 cui_aspect_scaling: 1;\n\tu16 preserve_aspect_ratio: 1;\n\tu16 sdvo_device_power_down: 1;\n\tu16 crt_hotplug: 1;\n\tu16 lvds_config: 2;\n\tu16 tv_hotplug: 1;\n\tu16 hdmi_config: 2;\n\tu8 static_display: 1;\n\tu8 embedded_platform: 1;\n\tu8 display_subsystem_enable: 1;\n\tu8 reserved0: 5;\n\tu16 legacy_crt_max_x;\n\tu16 legacy_crt_max_y;\n\tu8 legacy_crt_max_refresh;\n\tu8 hdmi_termination: 1;\n\tu8 cea861d_hdmi_support: 1;\n\tu8 self_refresh_enable: 1;\n\tu8 reserved1: 5;\n\tu8 custom_vbt_version;\n\tu16 rmpm_enabled: 1;\n\tu16 s2ddt_enabled: 1;\n\tu16 dpst_enabled: 1;\n\tu16 bltclt_enabled: 1;\n\tu16 adb_enabled: 1;\n\tu16 drrs_enabled: 1;\n\tu16 grs_enabled: 1;\n\tu16 gpmt_enabled: 1;\n\tu16 tbt_enabled: 1;\n\tu16 psr_enabled: 1;\n\tu16 ips_enabled: 1;\n\tu16 dfps_enabled: 1;\n\tu16 dmrrs_enabled: 1;\n\tu16 adt_enabled: 1;\n\tu16 hpd_wake: 1;\n\tu16 pc_feature_valid: 1;\n} __attribute__((packed));\n\nstruct bdb_edid_dtd {\n\tu16 clock;\n\tu8 hactive_lo;\n\tu8 hblank_lo;\n\tu8 hblank_hi: 4;\n\tu8 hactive_hi: 4;\n\tu8 vactive_lo;\n\tu8 vblank_lo;\n\tu8 vblank_hi: 4;\n\tu8 vactive_hi: 4;\n\tu8 hsync_off_lo;\n\tu8 hsync_pulse_width_lo;\n\tu8 vsync_pulse_width_lo: 4;\n\tu8 vsync_off_lo: 4;\n\tu8 vsync_pulse_width_hi: 2;\n\tu8 vsync_off_hi: 2;\n\tu8 hsync_pulse_width_hi: 2;\n\tu8 hsync_off_hi: 2;\n\tu8 himage_lo;\n\tu8 vimage_lo;\n\tu8 vimage_hi: 4;\n\tu8 himage_hi: 4;\n\tu8 h_border;\n\tu8 v_border;\n\tu8 rsvd1: 3;\n\tu8 digital: 2;\n\tu8 vsync_positive: 1;\n\tu8 hsync_positive: 1;\n\tu8 non_interlaced: 1;\n};\n\nstruct bdb_edid_pnp_id {\n\tu16 mfg_name;\n\tu16 product_code;\n\tu32 serial;\n\tu8 mfg_week;\n\tu8 mfg_year;\n} __attribute__((packed));\n\nstruct bdb_edid_product_name {\n\tchar name[13];\n};\n\nstruct edp_power_seq {\n\tu16 t1_t3;\n\tu16 t8;\n\tu16 t9;\n\tu16 t10;\n\tu16 t11_t12;\n};\n\nstruct edp_fast_link_params {\n\tu8 rate: 4;\n\tu8 lanes: 4;\n\tu8 preemphasis: 4;\n\tu8 vswing: 4;\n};\n\nstruct edp_pwm_delays {\n\tu16 pwm_on_to_backlight_enable;\n\tu16 backlight_disable_to_pwm_off;\n};\n\nstruct edp_full_link_params {\n\tu8 preemphasis: 4;\n\tu8 vswing: 4;\n};\n\nstruct edp_apical_params {\n\tu32 panel_oui;\n\tu32 dpcd_base_address;\n\tu32 dpcd_idridix_control_0;\n\tu32 dpcd_option_select;\n\tu32 dpcd_backlight;\n\tu32 ambient_light;\n\tu32 backlight_scale;\n};\n\nstruct bdb_edp {\n\tstruct edp_power_seq power_seqs[16];\n\tu32 color_depth;\n\tstruct edp_fast_link_params fast_link_params[16];\n\tu32 sdrrs_msa_timing_delay;\n\tu16 edp_s3d_feature;\n\tu16 edp_t3_optimization;\n\tu64 edp_vswing_preemph;\n\tu16 fast_link_training;\n\tu16 dpcd_600h_write_required;\n\tstruct edp_pwm_delays pwm_delays[16];\n\tu16 full_link_params_provided;\n\tstruct edp_full_link_params full_link_params[16];\n\tu16 apical_enable;\n\tstruct edp_apical_params apical_params[16];\n\tu16 edp_fast_link_training_rate[16];\n\tu16 edp_max_port_link_rate[16];\n\tu16 edp_dsc_disable;\n\tu16 t6_delay_support;\n\tu16 link_idle_time[16];\n} __attribute__((packed));\n\nstruct bdb_general_definitions {\n\tu8 crt_ddc_gmbus_pin;\n\tu8 dpms_non_acpi: 1;\n\tu8 skip_boot_crt_detect: 1;\n\tu8 dpms_aim: 1;\n\tu8 rsvd1: 5;\n\tu8 boot_display[2];\n\tu8 child_dev_size;\n\tu8 devices[0];\n};\n\nstruct bdb_general_features {\n\tu8 panel_fitting: 2;\n\tu8 flexaim: 1;\n\tu8 msg_enable: 1;\n\tu8 clear_screen: 3;\n\tu8 color_flip: 1;\n\tu8 download_ext_vbt: 1;\n\tu8 enable_ssc: 1;\n\tu8 ssc_freq: 1;\n\tu8 enable_lfp_on_override: 1;\n\tu8 disable_ssc_ddt: 1;\n\tu8 underscan_vga_timings: 1;\n\tu8 display_clock_mode: 1;\n\tu8 vbios_hotplug_support: 1;\n\tu8 disable_smooth_vision: 1;\n\tu8 single_dvi: 1;\n\tu8 rotate_180: 1;\n\tu8 fdi_rx_polarity_inverted: 1;\n\tu8 vbios_extended_mode: 1;\n\tu8 copy_ilfp_dtd_to_sdvo_lvds_dtd: 1;\n\tu8 panel_best_fit_timing: 1;\n\tu8 ignore_strap_state: 1;\n\tu8 legacy_monitor_detect;\n\tu8 int_crt_support: 1;\n\tu8 int_tv_support: 1;\n\tu8 int_efp_support: 1;\n\tu8 dp_ssc_enable: 1;\n\tu8 dp_ssc_freq: 1;\n\tu8 dp_ssc_dongle_supported: 1;\n\tu8 rsvd11: 2;\n\tu8 tc_hpd_retry_timeout: 7;\n\tu8 rsvd12: 1;\n\tu8 afc_startup_config: 2;\n\tu8 rsvd13: 6;\n};\n\nstruct generic_dtd_entry {\n\tu32 pixel_clock;\n\tu16 hactive;\n\tu16 hblank;\n\tu16 hfront_porch;\n\tu16 hsync;\n\tu16 vactive;\n\tu16 vblank;\n\tu16 vfront_porch;\n\tu16 vsync;\n\tu16 width_mm;\n\tu16 height_mm;\n\tu8 rsvd_flags: 6;\n\tu8 vsync_positive_polarity: 1;\n\tu8 hsync_positive_polarity: 1;\n\tu8 rsvd[3];\n};\n\nstruct bdb_generic_dtd {\n\tu16 gdtd_size;\n\tstruct generic_dtd_entry dtd[0];\n} __attribute__((packed));\n\nstruct bdb_header {\n\tu8 signature[16];\n\tu16 version;\n\tu16 header_size;\n\tu16 bdb_size;\n};\n\nstruct lfp_backlight_data_entry {\n\tu8 type: 2;\n\tu8 active_low_pwm: 1;\n\tu8 i2c_pin: 3;\n\tu8 i2c_speed: 2;\n\tu16 pwm_freq_hz;\n\tu8 min_brightness;\n\tu8 i2c_address;\n\tu8 i2c_command;\n} __attribute__((packed));\n\nstruct lfp_backlight_control_method {\n\tu8 type: 4;\n\tu8 controller: 4;\n};\n\nstruct lfp_brightness_level {\n\tu16 level;\n\tu16 reserved;\n};\n\nstruct bdb_lfp_backlight {\n\tu8 entry_size;\n\tstruct lfp_backlight_data_entry data[16];\n\tu8 level[16];\n\tstruct lfp_backlight_control_method backlight_control[16];\n\tstruct lfp_brightness_level brightness_level[16];\n\tstruct lfp_brightness_level brightness_min_level[16];\n\tu8 brightness_precision_bits[16];\n\tu16 hdr_dpcd_refresh_timeout[16];\n} __attribute__((packed));\n\nstruct fp_timing {\n\tu16 x_res;\n\tu16 y_res;\n\tu32 lvds_reg;\n\tu32 lvds_reg_val;\n\tu32 pp_on_reg;\n\tu32 pp_on_reg_val;\n\tu32 pp_off_reg;\n\tu32 pp_off_reg_val;\n\tu32 pp_cycle_reg;\n\tu32 pp_cycle_reg_val;\n\tu32 pfit_reg;\n\tu32 pfit_reg_val;\n\tu16 terminator;\n} __attribute__((packed));\n\nstruct lfp_data_entry {\n\tstruct fp_timing fp_timing;\n\tstruct bdb_edid_dtd dvo_timing;\n\tstruct bdb_edid_pnp_id pnp_id;\n};\n\nstruct bdb_lfp_data {\n\tstruct lfp_data_entry data[16];\n};\n\nstruct lfp_data_ptr_table {\n\tu16 offset;\n\tu8 table_size;\n} __attribute__((packed));\n\nstruct lfp_data_ptr {\n\tstruct lfp_data_ptr_table fp_timing;\n\tstruct lfp_data_ptr_table dvo_timing;\n\tstruct lfp_data_ptr_table panel_pnp_id;\n};\n\nstruct bdb_lfp_data_ptrs {\n\tu8 num_entries;\n\tstruct lfp_data_ptr ptr[16];\n\tstruct lfp_data_ptr_table panel_name;\n};\n\nstruct lfp_black_border {\n\tu8 top;\n\tu8 bottom;\n\tu8 left;\n\tu8 right;\n};\n\nstruct bdb_lfp_data_tail {\n\tstruct bdb_edid_product_name panel_name[16];\n\tu16 scaling_enable;\n\tu8 seamless_drrs_min_refresh_rate[16];\n\tu8 pixel_overlap_count[16];\n\tstruct lfp_black_border black_border[16];\n\tu16 dual_lfp_port_sync_enable;\n\tu16 gpu_dithering_for_banding_artifacts;\n};\n\nstruct bdb_lfp_options {\n\tu8 panel_type;\n\tu8 panel_type2;\n\tu8 pfit_mode: 2;\n\tu8 pfit_text_mode_enhanced: 1;\n\tu8 pfit_gfx_mode_enhanced: 1;\n\tu8 pfit_ratio_auto: 1;\n\tu8 pixel_dither: 1;\n\tu8 lvds_edid: 1;\n\tu8 rsvd2: 1;\n\tu8 rsvd4;\n\tu32 lvds_panel_channel_bits;\n\tu16 ssc_bits;\n\tu16 ssc_freq;\n\tu16 ssc_ddt;\n\tu16 panel_color_depth;\n\tu32 dps_panel_type_bits;\n\tu32 blt_control_type_bits;\n\tu16 lcdvcc_s0_enable;\n\tu32 rotation;\n\tu32 position;\n} __attribute__((packed));\n\nstruct lfp_power_features {\n\tu8 dpst_support: 1;\n\tu8 power_conservation_pref: 3;\n\tu8 reserved2: 1;\n\tu8 lace_enabled_status: 1;\n\tu8 lace_support: 1;\n\tu8 als_enable: 1;\n};\n\nstruct panel_identification {\n\tu8 panel_technology: 4;\n\tu8 reserved: 4;\n};\n\nstruct bdb_lfp_power {\n\tstruct lfp_power_features features;\n\tstruct als_data_entry als[5];\n\tu8 lace_aggressiveness_profile: 3;\n\tu8 reserved1: 5;\n\tu16 dpst;\n\tu16 psr;\n\tu16 drrs;\n\tu16 lace_support;\n\tu16 adt;\n\tu16 dmrrs;\n\tu16 adb;\n\tu16 lace_enabled_status;\n\tstruct aggressiveness_profile_entry aggressiveness[16];\n\tu16 hobl;\n\tu16 vrr_feature_enabled;\n\tu16 elp;\n\tu16 opst;\n\tstruct aggressiveness_profile2_entry aggressiveness2[16];\n\tu16 apd;\n\tu16 pixoptix;\n\tstruct aggressiveness_profile3_entry aggressiveness3[16];\n\tstruct panel_identification panel_identification[16];\n\tu16 xpst_support;\n\tu16 tcon_based_backlight_optimization;\n\tstruct aggressiveness_profile4_entry aggressiveness4[16];\n\tu16 tcon_backlight_xpst_coexistence;\n} __attribute__((packed));\n\nstruct mipi_config {\n\tu16 panel_id;\n\tstruct {\n\t\tu32 enable_dithering: 1;\n\t\tu32 rsvd1: 1;\n\t\tu32 is_bridge: 1;\n\t\tu32 panel_arch_type: 2;\n\t\tu32 is_cmd_mode: 1;\n\t\tu32 video_transfer_mode: 2;\n\t\tu32 cabc_supported: 1;\n\t\tu32 pwm_blc: 1;\n\t\tu32 videomode_color_format: 4;\n\t\tu32 rotation: 2;\n\t\tu32 bta_disable: 1;\n\t\tu32 rsvd2: 15;\n\t};\n\tstruct {\n\t\tu16 dual_link: 2;\n\t\tu16 lane_cnt: 2;\n\t\tu16 pixel_overlap: 3;\n\t\tu16 rgb_flip: 1;\n\t\tu16 dl_dcs_cabc_ports: 2;\n\t\tu16 dl_dcs_backlight_ports: 2;\n\t\tu16 port_sync: 1;\n\t\tu16 rsvd3: 3;\n\t};\n\tstruct {\n\t\tu16 dsi_usage: 1;\n\t\tu16 rsvd4: 15;\n\t};\n\tu8 rsvd5;\n\tu32 target_burst_mode_freq;\n\tu32 dsi_ddr_clk;\n\tu32 bridge_ref_clk;\n\tstruct {\n\t\tu8 byte_clk_sel: 2;\n\t\tu8 rsvd6: 6;\n\t};\n\tstruct {\n\t\tu16 dphy_param_valid: 1;\n\t\tu16 eot_pkt_disabled: 1;\n\t\tu16 enable_clk_stop: 1;\n\t\tu16 blanking_packets_during_bllp: 1;\n\t\tu16 lp_clock_during_lpm: 1;\n\t\tu16 rsvd7: 11;\n\t};\n\tu32 hs_tx_timeout;\n\tu32 lp_rx_timeout;\n\tu32 turn_around_timeout;\n\tu32 device_reset_timer;\n\tu32 master_init_timer;\n\tu32 dbi_bw_timer;\n\tu32 lp_byte_clk_val;\n\tstruct {\n\t\tu32 prepare_cnt: 6;\n\t\tu32 rsvd8: 2;\n\t\tu32 clk_zero_cnt: 8;\n\t\tu32 trail_cnt: 5;\n\t\tu32 rsvd9: 3;\n\t\tu32 exit_zero_cnt: 6;\n\t\tu32 rsvd10: 2;\n\t};\n\tu32 clk_lane_switch_cnt;\n\tu32 hl_switch_cnt;\n\tu32 rsvd11[6];\n\tu8 tclk_miss;\n\tu8 tclk_post;\n\tu8 rsvd12;\n\tu8 tclk_pre;\n\tu8 tclk_prepare;\n\tu8 tclk_settle;\n\tu8 tclk_term_enable;\n\tu8 tclk_trail;\n\tu16 tclk_prepare_clkzero;\n\tu8 rsvd13;\n\tu8 td_term_enable;\n\tu8 teot;\n\tu8 ths_exit;\n\tu8 ths_prepare;\n\tu16 ths_prepare_hszero;\n\tu8 rsvd14;\n\tu8 ths_settle;\n\tu8 ths_skip;\n\tu8 ths_trail;\n\tu8 tinit;\n\tu8 tlpx;\n\tu8 rsvd15[3];\n\tu8 panel_enable;\n\tu8 bl_enable;\n\tu8 pwm_enable;\n\tu8 reset_r_n;\n\tu8 pwr_down_r;\n\tu8 stdby_r_n;\n} __attribute__((packed));\n\nstruct mipi_pps_data {\n\tu16 panel_on_delay;\n\tu16 bl_enable_delay;\n\tu16 bl_disable_delay;\n\tu16 panel_off_delay;\n\tu16 panel_power_cycle_delay;\n};\n\nstruct bdb_mipi_config {\n\tstruct mipi_config config[6];\n\tstruct mipi_pps_data pps[6];\n\tstruct edp_pwm_delays pwm_delays[6];\n\tu8 pmic_i2c_bus_number[6];\n};\n\nstruct bdb_mipi_sequence {\n\tu8 version;\n\tu8 data[0];\n};\n\nstruct psr_table {\n\tu8 full_link: 1;\n\tu8 require_aux_to_wakeup: 1;\n\tu8 feature_bits_rsvd: 6;\n\tu8 idle_frames: 4;\n\tu8 lines_to_wait: 3;\n\tu8 wait_times_rsvd: 1;\n\tu16 tp1_wakeup_time;\n\tu16 tp2_tp3_wakeup_time;\n};\n\nstruct bdb_psr {\n\tstruct psr_table psr_table[16];\n\tu32 psr2_tp2_tp3_wakeup_time;\n};\n\nstruct bdb_sdvo_lvds_dtd {\n\tstruct bdb_edid_dtd dtd[4];\n};\n\nstruct bdb_sdvo_lvds_options {\n\tu8 panel_backlight;\n\tu8 h40_set_panel_type;\n\tu8 panel_type;\n\tu8 ssc_clk_freq;\n\tu16 als_low_trip;\n\tu16 als_high_trip;\n\tu8 sclalarcoeff_tab_row_num;\n\tu8 sclalarcoeff_tab_row_size;\n\tu8 coefficient[8];\n\tu8 panel_misc_bits_1;\n\tu8 panel_misc_bits_2;\n\tu8 panel_misc_bits_3;\n\tu8 panel_misc_bits_4;\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tvoid *bd_security;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tvoid *i_security;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct ieee80211_meshconf_ie;\n\nstruct cfg80211_mbssid_elems;\n\nstruct cfg80211_rnr_elems;\n\nstruct beacon_data {\n\tu8 *head;\n\tu8 *tail;\n\tint head_len;\n\tint tail_len;\n\tstruct ieee80211_meshconf_ie *meshconf;\n\tu16 cntdwn_counter_offsets[2];\n\tu8 cntdwn_current_counter;\n\tstruct cfg80211_mbssid_elems *mbssid_ies;\n\tstruct cfg80211_rnr_elems *rnr_ies;\n\tstruct callback_head callback_head;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct qrwlock {\n\tunion {\n\t\tatomic_t cnts;\n\t\tstruct {\n\t\t\tu8 wlocked;\n\t\t\tu8 __lstate[3];\n\t\t};\n\t};\n\tarch_spinlock_t wait_lock;\n};\n\ntypedef struct qrwlock arch_rwlock_t;\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n};\n\nstruct binfmt_misc {\n\tstruct list_head entries;\n\trwlock_t entries_lock;\n\tbool enabled;\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n} __attribute__((packed));\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct blkcg_gq;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tstruct blkcg_gq *bi_blkg;\n\tu64 issue_time_ns;\n\tu64 bi_iocost_cost;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tu64 bc_dun[4];\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec;\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct fsverity_info;\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct fsverity_info *vi;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bitmap_page;\n\nstruct bitmap_counts {\n\tspinlock_t lock;\n\tstruct bitmap_page *bp;\n\tlong unsigned int pages;\n\tlong unsigned int missing_pages;\n\tlong unsigned int chunkshift;\n\tlong unsigned int chunks;\n};\n\nstruct bitmap_storage {\n\tstruct file *file;\n\tstruct page *sb_page;\n\tlong unsigned int sb_index;\n\tstruct page **filemap;\n\tlong unsigned int *filemap_attr;\n\tlong unsigned int file_pages;\n\tlong unsigned int bytes;\n};\n\nstruct mddev;\n\nstruct bitmap {\n\tstruct bitmap_counts counts;\n\tstruct mddev *mddev;\n\t__u64 events_cleared;\n\tint need_sync;\n\tstruct bitmap_storage storage;\n\tlong unsigned int flags;\n\tint allclean;\n\tatomic_t behind_writes;\n\tlong unsigned int behind_writes_used;\n\tlong unsigned int daemon_lastrun;\n\tlong unsigned int last_end_sync;\n\tatomic_t pending_writes;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t overflow_wait;\n\twait_queue_head_t behind_wait;\n\tstruct kernfs_node *sysfs_can_clear;\n\tint cluster_slot;\n};\n\nstruct md_submodule_head {\n\tenum md_submodule_type type;\n\tenum md_submodule_id id;\n\tconst char *name;\n\tstruct module *owner;\n};\n\ntypedef void md_bitmap_fn(struct mddev *, sector_t, long unsigned int);\n\nstruct md_bitmap_stats;\n\nstruct bitmap_operations {\n\tstruct md_submodule_head head;\n\tbool (*enabled)(void *, bool);\n\tint (*create)(struct mddev *);\n\tint (*resize)(struct mddev *, sector_t, int);\n\tint (*load)(struct mddev *);\n\tvoid (*destroy)(struct mddev *);\n\tvoid (*flush)(struct mddev *);\n\tvoid (*write_all)(struct mddev *);\n\tvoid (*dirty_bits)(struct mddev *, long unsigned int, long unsigned int);\n\tvoid (*unplug)(struct mddev *, bool);\n\tvoid (*daemon_work)(struct mddev *);\n\tvoid (*start_behind_write)(struct mddev *);\n\tvoid (*end_behind_write)(struct mddev *);\n\tvoid (*wait_behind_writes)(struct mddev *);\n\tmd_bitmap_fn *start_write;\n\tmd_bitmap_fn *end_write;\n\tmd_bitmap_fn *start_discard;\n\tmd_bitmap_fn *end_discard;\n\tsector_t (*skip_sync_blocks)(struct mddev *, sector_t);\n\tbool (*blocks_synced)(struct mddev *, sector_t);\n\tbool (*start_sync)(struct mddev *, sector_t, sector_t *, bool);\n\tvoid (*end_sync)(struct mddev *, sector_t, sector_t *);\n\tvoid (*cond_end_sync)(struct mddev *, sector_t, bool);\n\tvoid (*close_sync)(struct mddev *);\n\tvoid (*update_sb)(void *);\n\tint (*get_stats)(void *, struct md_bitmap_stats *);\n\tvoid (*sync_with_cluster)(struct mddev *, sector_t, sector_t, sector_t, sector_t);\n\tvoid * (*get_from_slot)(struct mddev *, int);\n\tint (*copy_from_slot)(struct mddev *, int, sector_t *, sector_t *, bool);\n\tvoid (*set_pages)(void *, long unsigned int);\n\tvoid (*free)(void *);\n\tstruct attribute_group *group;\n};\n\nstruct bitmap_page {\n\tchar *map;\n\tunsigned int hijacked: 1;\n\tunsigned int pending: 1;\n\tunsigned int count: 30;\n};\n\nstruct bitmap_super_s {\n\t__le32 magic;\n\t__le32 version;\n\t__u8 uuid[16];\n\t__le64 events;\n\t__le64 events_cleared;\n\t__le64 sync_size;\n\t__le32 state;\n\t__le32 chunksize;\n\t__le32 daemon_sleep;\n\t__le32 write_behind;\n\t__le32 sectors_reserved;\n\t__le32 nodes;\n\t__u8 cluster_name[64];\n\t__u8 pad[120];\n};\n\ntypedef struct bitmap_super_s bitmap_super_t;\n\nstruct bitmap_unplug_work {\n\tstruct work_struct work;\n\tstruct bitmap *bitmap;\n\tstruct completion *done;\n};\n\nstruct bl_dev_msg {\n\tint32_t status;\n\tuint32_t major;\n\tuint32_t minor;\n};\n\nstruct bl_msg_hdr {\n\tu8 type;\n\tu16 totallen;\n};\n\nstruct rpc_pipe_msg {\n\tstruct list_head list;\n\tvoid *data;\n\tsize_t len;\n\tsize_t copied;\n\tint errno;\n};\n\nstruct bl_pipe_msg {\n\tstruct rpc_pipe_msg msg;\n\twait_queue_head_t *bl_wq;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct blk_crypto_profile;\n\nstruct blk_crypto_ll_ops {\n\tint (*keyslot_program)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*keyslot_evict)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*derive_sw_secret)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*import_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*generate_key)(struct blk_crypto_profile *, u8 *);\n\tint (*prepare_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n};\n\nstruct blk_crypto_keyslot;\n\nstruct blk_crypto_profile {\n\tstruct blk_crypto_ll_ops ll_ops;\n\tunsigned int max_dun_bytes_supported;\n\tunsigned int key_types_supported;\n\tunsigned int modes_supported[5];\n\tstruct device *dev;\n\tunsigned int num_slots;\n\tstruct rw_semaphore lock;\n\tstruct lock_class_key lockdep_key;\n\twait_queue_head_t idle_slots_wait_queue;\n\tstruct list_head idle_slots;\n\tspinlock_t idle_slots_lock;\n\tstruct hlist_head *slot_hashtable;\n\tunsigned int log_slot_ht_size;\n\tstruct blk_crypto_keyslot *slots;\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct request;\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_independent_access_range;\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_io_trace {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 action;\n\t__u32 pid;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n};\n\nstruct blk_io_trace2 {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 pid;\n\t__u64 action;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n\t__u8 pad[12];\n};\n\nstruct blk_io_trace_remap {\n\t__be32 device_from;\n\t__be32 device_to;\n\t__be64 sector_from;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct blk_iolatency {\n\tstruct rq_qos rqos;\n\tstruct timer_list timer;\n\tbool enabled;\n\tatomic_t enable_cnt;\n\tstruct work_struct enable_work;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 64;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 64;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct rchan;\n\nstruct blk_trace {\n\tint version;\n\tint trace_state;\n\tstruct rchan *rchan;\n\tlong unsigned int *sequence;\n\tunsigned char *msg_data;\n\tu64 act_mask;\n\tu64 start_lba;\n\tu64 end_lba;\n\tu32 pid;\n\tu32 dev;\n\tstruct dentry *dir;\n\tstruct list_head running_list;\n\tatomic_t dropped;\n};\n\nstruct blk_user_trace_setup {\n\tchar name[32];\n\t__u16 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n};\n\nstruct blk_user_trace_setup2 {\n\tchar name[64];\n\t__u64 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n\t__u32 flags;\n\t__u64 reserved[11];\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct cgroup_subsys;\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n};\n\nstruct blkcg_policy_data;\n\nstruct blkcg {\n\tstruct cgroup_subsys_state css;\n\tspinlock_t lock;\n\trefcount_t online_pin;\n\tatomic_t congestion_count;\n\tstruct xarray blkg_tree;\n\tstruct blkcg_gq *blkg_hint;\n\tstruct hlist_head blkg_list;\n\tstruct blkcg_policy_data *cpd[6];\n\tstruct list_head all_blkcgs_node;\n\tstruct llist_head *lhead;\n};\n\nstruct blkg_iostat {\n\tu64 bytes[3];\n\tu64 ios[3];\n};\n\nstruct blkg_iostat_set {\n\tstruct u64_stats_sync sync;\n\tstruct blkcg_gq *blkg;\n\tstruct llist_node lnode;\n\tint lqueued;\n\tstruct blkg_iostat cur;\n\tstruct blkg_iostat last;\n};\n\nstruct blkg_policy_data;\n\nstruct blkcg_gq {\n\tstruct request_queue *q;\n\tstruct list_head q_node;\n\tstruct hlist_node blkcg_node;\n\tstruct blkcg *blkcg;\n\tstruct blkcg_gq *parent;\n\tstruct percpu_ref refcnt;\n\tbool online;\n\tstruct blkg_iostat_set *iostat_cpu;\n\tstruct blkg_iostat_set iostat;\n\tstruct blkg_policy_data *pd[6];\n\tunion {\n\t\tstruct work_struct async_bio_work;\n\t\tstruct work_struct free_work;\n\t};\n\tatomic_t use_delay;\n\tatomic64_t delay_nsec;\n\tatomic64_t delay_start;\n\tu64 last_delay;\n\tint last_use;\n\tstruct callback_head callback_head;\n};\n\ntypedef struct blkcg_policy_data *blkcg_pol_alloc_cpd_fn(gfp_t);\n\ntypedef void blkcg_pol_free_cpd_fn(struct blkcg_policy_data *);\n\ntypedef struct blkg_policy_data *blkcg_pol_alloc_pd_fn(struct gendisk *, struct blkcg *, gfp_t);\n\ntypedef void blkcg_pol_init_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_online_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_offline_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_free_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_reset_pd_stats_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_stat_pd_fn(struct blkg_policy_data *, struct seq_file *);\n\nstruct cftype;\n\nstruct blkcg_policy {\n\tint plid;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tblkcg_pol_alloc_cpd_fn *cpd_alloc_fn;\n\tblkcg_pol_free_cpd_fn *cpd_free_fn;\n\tblkcg_pol_alloc_pd_fn *pd_alloc_fn;\n\tblkcg_pol_init_pd_fn *pd_init_fn;\n\tblkcg_pol_online_pd_fn *pd_online_fn;\n\tblkcg_pol_offline_pd_fn *pd_offline_fn;\n\tblkcg_pol_free_pd_fn *pd_free_fn;\n\tblkcg_pol_reset_pd_stats_fn *pd_reset_stats_fn;\n\tblkcg_pol_stat_pd_fn *pd_stat_fn;\n};\n\nstruct blkcg_policy_data {\n\tstruct blkcg *blkcg;\n\tint plid;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bio bio;\n\tlong: 64;\n};\n\nstruct blkg_conf_ctx {\n\tchar *input;\n\tchar *body;\n\tstruct block_device *bdev;\n\tstruct blkcg_gq *blkg;\n};\n\nstruct blkg_policy_data {\n\tstruct blkcg_gq *blkg;\n\tint plid;\n\tbool online;\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[128];\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct mem_zone_bm_rtree;\n\nstruct rtree_node;\n\nstruct bm_position {\n\tstruct mem_zone_bm_rtree *zone;\n\tstruct rtree_node *node;\n\tlong unsigned int node_pfn;\n\tlong unsigned int cur_pfn;\n\tint node_bit;\n};\n\nstruct bmp_header {\n\tu16 id;\n\tu32 size;\n} __attribute__((packed));\n\nstruct boot_e820_entry {\n\t__u64 addr;\n\t__u64 size;\n\t__u32 type;\n} __attribute__((packed));\n\nstruct screen_info {\n\t__u8 orig_x;\n\t__u8 orig_y;\n\t__u16 ext_mem_k;\n\t__u16 orig_video_page;\n\t__u8 orig_video_mode;\n\t__u8 orig_video_cols;\n\t__u8 flags;\n\t__u8 unused2;\n\t__u16 orig_video_ega_bx;\n\t__u16 unused3;\n\t__u8 orig_video_lines;\n\t__u8 orig_video_isVGA;\n\t__u16 orig_video_points;\n\t__u16 lfb_width;\n\t__u16 lfb_height;\n\t__u16 lfb_depth;\n\t__u32 lfb_base;\n\t__u32 lfb_size;\n\t__u16 cl_magic;\n\t__u16 cl_offset;\n\t__u16 lfb_linelength;\n\t__u8 red_size;\n\t__u8 red_pos;\n\t__u8 green_size;\n\t__u8 green_pos;\n\t__u8 blue_size;\n\t__u8 blue_pos;\n\t__u8 rsvd_size;\n\t__u8 rsvd_pos;\n\t__u16 vesapm_seg;\n\t__u16 vesapm_off;\n\t__u16 pages;\n\t__u16 vesa_attributes;\n\t__u32 capabilities;\n\t__u32 ext_lfb_base;\n\t__u8 _reserved[2];\n} __attribute__((packed));\n\nstruct ist_info {\n\t__u32 signature;\n\t__u32 command;\n\t__u32 event;\n\t__u32 perf_level;\n};\n\nstruct sys_desc_table {\n\t__u16 length;\n\t__u8 table[14];\n};\n\nstruct olpc_ofw_header {\n\t__u32 ofw_magic;\n\t__u32 ofw_version;\n\t__u32 cif_handler;\n\t__u32 irq_desc_table;\n};\n\nstruct edid_info {\n\tunsigned char dummy[128];\n};\n\nstruct efi_info {\n\t__u32 efi_loader_signature;\n\t__u32 efi_systab;\n\t__u32 efi_memdesc_size;\n\t__u32 efi_memdesc_version;\n\t__u32 efi_memmap;\n\t__u32 efi_memmap_size;\n\t__u32 efi_systab_hi;\n\t__u32 efi_memmap_hi;\n};\n\nstruct setup_header {\n\t__u8 setup_sects;\n\t__u16 root_flags;\n\t__u32 syssize;\n\t__u16 ram_size;\n\t__u16 vid_mode;\n\t__u16 root_dev;\n\t__u16 boot_flag;\n\t__u16 jump;\n\t__u32 header;\n\t__u16 version;\n\t__u32 realmode_swtch;\n\t__u16 start_sys_seg;\n\t__u16 kernel_version;\n\t__u8 type_of_loader;\n\t__u8 loadflags;\n\t__u16 setup_move_size;\n\t__u32 code32_start;\n\t__u32 ramdisk_image;\n\t__u32 ramdisk_size;\n\t__u32 bootsect_kludge;\n\t__u16 heap_end_ptr;\n\t__u8 ext_loader_ver;\n\t__u8 ext_loader_type;\n\t__u32 cmd_line_ptr;\n\t__u32 initrd_addr_max;\n\t__u32 kernel_alignment;\n\t__u8 relocatable_kernel;\n\t__u8 min_alignment;\n\t__u16 xloadflags;\n\t__u32 cmdline_size;\n\t__u32 hardware_subarch;\n\t__u64 hardware_subarch_data;\n\t__u32 payload_offset;\n\t__u32 payload_length;\n\t__u64 setup_data;\n\t__u64 pref_address;\n\t__u32 init_size;\n\t__u32 handover_offset;\n\t__u32 kernel_info_offset;\n} __attribute__((packed));\n\nstruct edd_device_params {\n\t__u16 length;\n\t__u16 info_flags;\n\t__u32 num_default_cylinders;\n\t__u32 num_default_heads;\n\t__u32 sectors_per_track;\n\t__u64 number_of_sectors;\n\t__u16 bytes_per_sector;\n\t__u32 dpte_ptr;\n\t__u16 key;\n\t__u8 device_path_info_length;\n\t__u8 reserved2;\n\t__u16 reserved3;\n\t__u8 host_bus_type[4];\n\t__u8 interface_type[8];\n\tunion {\n\t\tstruct {\n\t\t\t__u16 base_address;\n\t\t\t__u16 reserved1;\n\t\t\t__u32 reserved2;\n\t\t} isa;\n\t\tstruct {\n\t\t\t__u8 bus;\n\t\t\t__u8 slot;\n\t\t\t__u8 function;\n\t\t\t__u8 channel;\n\t\t\t__u32 reserved;\n\t\t} pci;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} ibnd;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} xprs;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} htpt;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} unknown;\n\t} interface_path;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 reserved1;\n\t\t\t__u16 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} ata;\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 lun;\n\t\t\t__u8 reserved1;\n\t\t\t__u8 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} atapi;\n\t\tstruct {\n\t\t\t__u16 id;\n\t\t\t__u64 lun;\n\t\t\t__u16 reserved1;\n\t\t\t__u32 reserved2;\n\t\t} __attribute__((packed)) scsi;\n\t\tstruct {\n\t\t\t__u64 serial_number;\n\t\t\t__u64 reserved;\n\t\t} usb;\n\t\tstruct {\n\t\t\t__u64 eui;\n\t\t\t__u64 reserved;\n\t\t} i1394;\n\t\tstruct {\n\t\t\t__u64 wwid;\n\t\t\t__u64 lun;\n\t\t} fibre;\n\t\tstruct {\n\t\t\t__u64 identity_tag;\n\t\t\t__u64 reserved;\n\t\t} i2o;\n\t\tstruct {\n\t\t\t__u32 array_number;\n\t\t\t__u32 reserved1;\n\t\t\t__u64 reserved2;\n\t\t} raid;\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 reserved1;\n\t\t\t__u16 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} sata;\n\t\tstruct {\n\t\t\t__u64 reserved1;\n\t\t\t__u64 reserved2;\n\t\t} unknown;\n\t} device_path;\n\t__u8 reserved4;\n\t__u8 checksum;\n} __attribute__((packed));\n\nstruct edd_info {\n\t__u8 device;\n\t__u8 version;\n\t__u16 interface_support;\n\t__u16 legacy_max_cylinder;\n\t__u8 legacy_max_head;\n\t__u8 legacy_sectors_per_track;\n\tstruct edd_device_params params;\n};\n\nstruct boot_params {\n\tstruct screen_info screen_info;\n\tstruct apm_bios_info apm_bios_info;\n\t__u8 _pad2[4];\n\t__u64 tboot_addr;\n\tstruct ist_info ist_info;\n\t__u64 acpi_rsdp_addr;\n\t__u8 _pad3[8];\n\t__u8 hd0_info[16];\n\t__u8 hd1_info[16];\n\tstruct sys_desc_table sys_desc_table;\n\tstruct olpc_ofw_header olpc_ofw_header;\n\t__u32 ext_ramdisk_image;\n\t__u32 ext_ramdisk_size;\n\t__u32 ext_cmd_line_ptr;\n\t__u8 _pad4[112];\n\t__u32 cc_blob_address;\n\tstruct edid_info edid_info;\n\tstruct efi_info efi_info;\n\t__u32 alt_mem_k;\n\t__u32 scratch;\n\t__u8 e820_entries;\n\t__u8 eddbuf_entries;\n\t__u8 edd_mbr_sig_buf_entries;\n\t__u8 kbd_status;\n\t__u8 secure_boot;\n\t__u8 _pad5[2];\n\t__u8 sentinel;\n\t__u8 _pad6[1];\n\tstruct setup_header hdr;\n\t__u8 _pad7[36];\n\t__u32 edd_mbr_sig_buffer[16];\n\tstruct boot_e820_entry e820_table[128];\n\t__u8 _pad8[48];\n\tstruct edd_info eddbuf[6];\n\t__u8 _pad9[276];\n};\n\nstruct boot_params_to_save {\n\tunsigned int start;\n\tunsigned int len;\n};\n\nstruct boot_triggers {\n\tconst char *event;\n\tchar *trigger;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct bp_slots_histogram {\n\tatomic_t count[4];\n};\n\nstruct bp_cpuinfo {\n\tunsigned int cpu_pinned;\n\tstruct bp_slots_histogram tsk_pinned;\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tvoid *security;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n};\n\nstruct range_tree {\n\tstruct rb_root_cached it_root;\n\tstruct rb_root_cached range_size_root;\n};\n\ntypedef struct qspinlock rqspinlock_t;\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct vm_struct;\n\nstruct bpf_arena {\n\tstruct bpf_map map;\n\tu64 user_vm_start;\n\tu64 user_vm_end;\n\tstruct vm_struct *kern_vm;\n\tstruct range_tree rt;\n\trqspinlock_t spinlock;\n\tstruct list_head vma_list;\n\tstruct mutex lock;\n\tstruct irq_work free_irq;\n\tstruct work_struct free_work;\n\tstruct llist_head free_spans;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct bpf_prog;\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 0;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ct_opts {\n\ts32 netns_id;\n\ts32 error;\n\tu8 l4proto;\n\tu8 dir;\n\tu16 ct_zone_id;\n\tu8 ct_zone_dir;\n\tu8 reserved[3];\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct skb_ext;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tlong unsigned int _nfct;\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\t__u8 active_extensions;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tstruct skb_ext *extensions;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_rxq_info;\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t\tu64 frame_sz_flags_init;\n\t};\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\ntypedef struct pt_regs bpf_user_pt_regs_t;\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_sample_data;\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_prog;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_kern;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct static_call_key;\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n\tstruct static_call_key *sc_key;\n\tvoid *sc_tramp;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n};\n\nstruct bpf_cgroup_storage;\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n};\n\nstruct obj_cgroup;\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 0;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct dma_buf;\n\nstruct bpf_iter__dmabuf {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct dma_buf *dmabuf;\n\t};\n};\n\nstruct fib6_info;\n\nstruct bpf_iter__ipv6_route {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct fib6_info *rt;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct sock_common;\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 0;\n\tint bucket;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n};\n\nstruct bpf_iter_dmabuf {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_dmabuf_kern {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 0;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n};\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tatomic64_t revision;\n\tu32 count;\n};\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\ntypedef unsigned int nf_hookfn(void *, struct sk_buff *, const struct nf_hook_state *);\n\nstruct nf_hook_ops {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tnf_hookfn *hook;\n\tstruct net_device *dev;\n\tvoid *priv;\n\tu8 pf;\n\tenum nf_hook_ops_type hook_ops_type: 8;\n\tunsigned int hooknum;\n\tint priority;\n};\n\nstruct nf_defrag_hook;\n\nstruct bpf_nf_link {\n\tstruct bpf_link link;\n\tstruct nf_hook_ops hook_ops;\n\tnetns_tracker ns_tracker;\n\tstruct net *net;\n\tu32 dead;\n\tconst struct nf_defrag_hook *defrag_hook;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_perf_link {\n\tstruct bpf_link link;\n\tstruct file *perf_file;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tvoid *security;\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct tracepoint;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 64;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\trqspinlock_t spinlock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t busy;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int consumer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct bpf_security_struct {\n\tu32 sid;\n\tu32 perms;\n\tu32 grantor_sid;\n};\n\nstruct bpf_session_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tbool is_return;\n\tvoid *data;\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nstruct stack_map_bucket;\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_dummy_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_ext_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n\tvoid *security;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n};\n\nunion perf_sample_weight {\n\t__u64 full;\n\tstruct {\n\t\t__u32 var1_dw;\n\t\t__u16 var2_w;\n\t\t__u16 var3_w;\n\t};\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_op: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_blk: 3;\n\t\t__u64 mem_hops: 3;\n\t\t__u64 mem_region: 5;\n\t\t__u64 mem_rsvd: 13;\n\t};\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n};\n\nstruct perf_callchain_entry;\n\nstruct perf_raw_record;\n\nstruct perf_branch_stack;\n\nstruct perf_sample_data {\n\tu64 sample_flags;\n\tu64 period;\n\tu64 dyn_size;\n\tu64 type;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tu64 ip;\n\tstruct perf_callchain_entry *callchain;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 *br_stack_cntr;\n\tunion perf_sample_weight weight;\n\tunion perf_mem_data_src data_src;\n\tu64 txn;\n\tstruct perf_regs regs_user;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 stream_id;\n\tu64 cgroup;\n\tu64 addr;\n\tu64 phys_addr;\n\tu64 data_page_size;\n\tu64 code_page_size;\n\tu64 aux_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[38];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *, __u64 *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *, __u64 *);\n\tbool (*filter)(struct uprobe_consumer *, struct mm_struct *);\n\tstruct list_head cons_node;\n\t__u64 id;\n};\n\nstruct bpf_uprobe_multi_link;\n\nstruct uprobe;\n\nstruct bpf_uprobe {\n\tstruct bpf_uprobe_multi_link *link;\n\tloff_t offset;\n\tlong unsigned int ref_ctr_offset;\n\tu64 cookie;\n\tstruct uprobe *uprobe;\n\tstruct uprobe_consumer consumer;\n\tbool session;\n};\n\nstruct bpf_uprobe_multi_link {\n\tstruct path path;\n\tstruct bpf_link link;\n\tu32 cnt;\n\tstruct bpf_uprobe *uprobes;\n\tstruct task_struct *task;\n};\n\nstruct bpf_uprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tlong unsigned int entry_ip;\n\tstruct bpf_uprobe *uprobe;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpf_xfrm_state {\n\t__u32 reqid;\n\t__u32 spi;\n\t__u16 family;\n\t__u16 ext;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n};\n\nstruct bpf_xfrm_state_opts {\n\ts32 error;\n\ts32 netns_id;\n\tu32 mark;\n\txfrm_address_t daddr;\n\t__be32 spi;\n\tu8 proto;\n\tu16 family;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nstruct br_input_skb_cb {\n\tstruct net_device *brdev;\n\tu16 frag_max_size;\n\tu8 proxyarp_replied: 1;\n\tu8 src_port_isolated: 1;\n\tu8 promisc: 1;\n\tu32 backup_nhid;\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct branch_entry {\n\tunion {\n\t\tstruct {\n\t\t\tu64 ip: 58;\n\t\t\tu64 ip_sign_ext: 5;\n\t\t\tu64 mispredict: 1;\n\t\t} split;\n\t\tu64 full;\n\t} from;\n\tunion {\n\t\tstruct {\n\t\t\tu64 ip: 58;\n\t\t\tu64 ip_sign_ext: 3;\n\t\t\tu64 reserved: 1;\n\t\t\tu64 spec: 1;\n\t\t\tu64 valid: 1;\n\t\t} split;\n\t\tu64 full;\n\t} to;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct bsd_acct_struct {\n\tstruct fs_pin pin;\n\tatomic_long_t count;\n\tstruct callback_head rcu;\n\tstruct mutex lock;\n\tbool active;\n\tbool check_space;\n\tlong unsigned int needcheck;\n\tstruct file *file;\n\tstruct pid_namespace *ns;\n\tstruct work_struct work;\n\tstruct completion done;\n\tacct_t ac;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n};\n\nstruct bss_parameters {\n\tint link_id;\n\tint use_cts_prot;\n\tint use_short_preamble;\n\tint use_short_slot_time;\n\tconst u8 *basic_rates;\n\tu8 basic_rates_len;\n\tint ap_isolate;\n\tint ht_opmode;\n\ts8 p2p_ctwindow;\n\ts8 p2p_opp_ps;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[56];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_anon_stack {\n\tu32 tid;\n\tu32 offset;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_ptr {\n\tvoid *ptr;\n\t__u32 type_id;\n\t__u32 flags;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, struct __va_list_tag *);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct bts_phys {\n\tstruct page *page;\n\tlong unsigned int size;\n\tlong unsigned int offset;\n\tlong unsigned int displacement;\n};\n\nstruct bts_buffer {\n\tsize_t real_size;\n\tunsigned int nr_pages;\n\tunsigned int nr_bufs;\n\tunsigned int cur_buf;\n\tbool snapshot;\n\tlocal_t data_size;\n\tlocal_t head;\n\tlong unsigned int end;\n\tvoid **data_pages;\n\tstruct bts_phys buf[0];\n};\n\nstruct perf_buffer;\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tunion {\n\t\tu64 flags;\n\t\tu64 aux_flags;\n\t\tstruct {\n\t\t\tu64 skip_read: 1;\n\t\t};\n\t};\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct debug_store {\n\tu64 bts_buffer_base;\n\tu64 bts_index;\n\tu64 bts_absolute_maximum;\n\tu64 bts_interrupt_threshold;\n\tu64 pebs_buffer_base;\n\tu64 pebs_index;\n\tu64 pebs_absolute_maximum;\n\tu64 pebs_interrupt_threshold;\n\tu64 pebs_event_reset[48];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bts_ctx {\n\tstruct perf_output_handle handle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct debug_store ds_back;\n\tint state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bts_record {\n\tu64 from;\n\tu64 to;\n\tu64 flags;\n};\n\nstruct hlist_nulls_node;\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 64;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct buddy_page_mask {\n\tu32 page_mask;\n\tu8 type;\n\tu8 num_channels;\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n};\n\nstruct buffer_data_read_page {\n\tunsigned int order;\n\tstruct buffer_data_page *data;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tunsigned int order;\n\tu32 id: 30;\n\tu32 range: 1;\n\tstruct buffer_data_page *page;\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct bug_entry {\n\tint bug_addr_disp;\n\tint format_disp;\n\tint file_disp;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct bulk_cb_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 DataTransferLength;\n\t__u8 Flags;\n\t__u8 Lun;\n\t__u8 Length;\n\t__u8 CDB[16];\n};\n\nstruct bulk_cs_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 Residue;\n\t__u8 Status;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct bxt_ddi_buf_trans {\n\tu8 margin;\n\tu8 scale;\n\tu8 enable;\n\tu8 deemphasis;\n};\n\nstruct bxt_dpio_phy_info {\n\tbool dual_channel;\n\tenum dpio_phy rcomp_phy;\n\tint reset_delay;\n\tu32 pwron_mask;\n\tstruct {\n\t\tenum port port;\n\t} channel[2];\n};\n\nstruct bxt_dpll_hw_state {\n\tu32 ebb0;\n\tu32 ebb4;\n\tu32 pll0;\n\tu32 pll1;\n\tu32 pll2;\n\tu32 pll3;\n\tu32 pll6;\n\tu32 pll8;\n\tu32 pll9;\n\tu32 pll10;\n\tu32 pcsdw12;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct cache_head;\n\nstruct cache_deferred_req {\n\tstruct hlist_node hash;\n\tstruct list_head recent;\n\tstruct cache_head *item;\n\tvoid *owner;\n\tvoid (*revisit)(struct cache_deferred_req *, int);\n};\n\nstruct cache_detail {\n\tstruct module *owner;\n\tint hash_size;\n\tstruct hlist_head *hash_table;\n\tspinlock_t hash_lock;\n\tchar *name;\n\tvoid (*cache_put)(struct kref *);\n\tint (*cache_upcall)(struct cache_detail *, struct cache_head *);\n\tvoid (*cache_request)(struct cache_detail *, struct cache_head *, char **, int *);\n\tint (*cache_parse)(struct cache_detail *, char *, int);\n\tint (*cache_show)(struct seq_file *, struct cache_detail *, struct cache_head *);\n\tvoid (*warn_no_listener)(struct cache_detail *, int);\n\tstruct cache_head * (*alloc)(void);\n\tvoid (*flush)(void);\n\tint (*match)(struct cache_head *, struct cache_head *);\n\tvoid (*init)(struct cache_head *, struct cache_head *);\n\tvoid (*update)(struct cache_head *, struct cache_head *);\n\ttime64_t flush_time;\n\tstruct list_head others;\n\ttime64_t nextcheck;\n\tint entries;\n\tstruct list_head queue;\n\tatomic_t writers;\n\ttime64_t last_close;\n\ttime64_t last_warn;\n\tunion {\n\t\tstruct proc_dir_entry *procfs;\n\t\tstruct dentry *pipefs;\n\t};\n\tstruct net *net;\n};\n\nstruct cache_head {\n\tstruct hlist_node cache_list;\n\ttime64_t expiry_time;\n\ttime64_t last_refresh;\n\tstruct kref ref;\n\tlong unsigned int flags;\n};\n\nstruct cache_map {\n\tu64 start;\n\tu64 end;\n\tu64 flags;\n\tu64 type: 8;\n\tu64 fixed: 1;\n};\n\nstruct cache_queue {\n\tstruct list_head list;\n\tint reader;\n};\n\nstruct cache_reader {\n\tstruct cache_queue q;\n\tint offset;\n};\n\nstruct cache_req {\n\tstruct cache_deferred_req * (*defer)(struct cache_req *);\n\tlong unsigned int thread_wait;\n};\n\nstruct cache_request {\n\tstruct cache_queue q;\n\tstruct cache_head *item;\n\tchar *buf;\n\tint len;\n\tint readers;\n};\n\nstruct intel_iommu;\n\nstruct cache_tag {\n\tstruct list_head node;\n\tenum cache_tag_type type;\n\tstruct intel_iommu *iommu;\n\tstruct device *dev;\n\tu16 domain_id;\n\tioasid_t pasid;\n\tunsigned int users;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct calipso_doi {\n\tu32 doi;\n\tu32 type;\n\trefcount_t refcount;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct calipso_map_cache_bkt {\n\tspinlock_t lock;\n\tu32 size;\n\tstruct list_head list;\n};\n\nstruct netlbl_lsm_cache;\n\nstruct calipso_map_cache_entry {\n\tu32 hash;\n\tunsigned char *key;\n\tsize_t key_len;\n\tstruct netlbl_lsm_cache *lsm_data;\n\tu32 activity;\n\tstruct list_head list;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct cb_process_state;\n\nstruct xdr_stream;\n\nstruct callback_op {\n\t__be32 (*process_op)(void *, void *, struct cb_process_state *);\n\t__be32 (*decode_args)(struct svc_rqst *, struct xdr_stream *, void *);\n\t__be32 (*encode_res)(struct svc_rqst *, struct xdr_stream *, const void *);\n\tlong int res_maxsize;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nstruct callthunk_sites {\n\ts32 *call_start;\n\ts32 *call_end;\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct yenta_socket;\n\nstruct cardbus_type {\n\tint (*override)(struct yenta_socket *);\n\tvoid (*save_state)(struct yenta_socket *);\n\tvoid (*restore_state)(struct yenta_socket *);\n\tint (*sock_init)(struct yenta_socket *);\n};\n\nstruct cat_datum {\n\tu32 value;\n\tunsigned char isalias;\n};\n\nstruct config {\n\tu8 byte_count: 6;\n\tu8 pad0: 2;\n\tu8 rx_fifo_limit: 4;\n\tu8 tx_fifo_limit: 3;\n\tu8 pad1: 1;\n\tu8 adaptive_ifs;\n\tu8 mwi_enable: 1;\n\tu8 type_enable: 1;\n\tu8 read_align_enable: 1;\n\tu8 term_write_cache_line: 1;\n\tu8 pad3: 4;\n\tu8 rx_dma_max_count: 7;\n\tu8 pad4: 1;\n\tu8 tx_dma_max_count: 7;\n\tu8 dma_max_count_enable: 1;\n\tu8 late_scb_update: 1;\n\tu8 direct_rx_dma: 1;\n\tu8 tno_intr: 1;\n\tu8 cna_intr: 1;\n\tu8 standard_tcb: 1;\n\tu8 standard_stat_counter: 1;\n\tu8 rx_save_overruns: 1;\n\tu8 rx_save_bad_frames: 1;\n\tu8 rx_discard_short_frames: 1;\n\tu8 tx_underrun_retry: 2;\n\tu8 pad7: 2;\n\tu8 rx_extended_rfd: 1;\n\tu8 tx_two_frames_in_fifo: 1;\n\tu8 tx_dynamic_tbd: 1;\n\tu8 mii_mode: 1;\n\tu8 pad8: 6;\n\tu8 csma_disabled: 1;\n\tu8 rx_tcpudp_checksum: 1;\n\tu8 pad9: 3;\n\tu8 vlan_arp_tco: 1;\n\tu8 link_status_wake: 1;\n\tu8 arp_wake: 1;\n\tu8 mcmatch_wake: 1;\n\tu8 pad10: 3;\n\tu8 no_source_addr_insertion: 1;\n\tu8 preamble_length: 2;\n\tu8 loopback: 2;\n\tu8 linear_priority: 3;\n\tu8 pad11: 5;\n\tu8 linear_priority_mode: 1;\n\tu8 pad12: 3;\n\tu8 ifs: 4;\n\tu8 ip_addr_lo;\n\tu8 ip_addr_hi;\n\tu8 promiscuous_mode: 1;\n\tu8 broadcast_disabled: 1;\n\tu8 wait_after_win: 1;\n\tu8 pad15_1: 1;\n\tu8 ignore_ul_bit: 1;\n\tu8 crc_16_bit: 1;\n\tu8 pad15_2: 1;\n\tu8 crs_or_cdt: 1;\n\tu8 fc_delay_lo;\n\tu8 fc_delay_hi;\n\tu8 rx_stripping: 1;\n\tu8 tx_padding: 1;\n\tu8 rx_crc_transfer: 1;\n\tu8 rx_long_ok: 1;\n\tu8 fc_priority_threshold: 3;\n\tu8 pad18: 1;\n\tu8 addr_wake: 1;\n\tu8 magic_packet_disable: 1;\n\tu8 fc_disable: 1;\n\tu8 fc_restop: 1;\n\tu8 fc_restart: 1;\n\tu8 fc_reject: 1;\n\tu8 full_duplex_force: 1;\n\tu8 full_duplex_pin: 1;\n\tu8 pad20_1: 5;\n\tu8 fc_priority_location: 1;\n\tu8 multi_ia: 1;\n\tu8 pad20_2: 1;\n\tu8 pad21_1: 3;\n\tu8 multicast_all: 1;\n\tu8 pad21_2: 4;\n\tu8 rx_d102_mode: 1;\n\tu8 rx_vlan_drop: 1;\n\tu8 pad22: 6;\n\tu8 pad_d102[9];\n};\n\nstruct multi {\n\t__le16 count;\n\tu8 addr[386];\n};\n\nstruct cb {\n\t__le16 status;\n\t__le16 command;\n\t__le32 link;\n\tunion {\n\t\tu8 iaaddr[6];\n\t\t__le32 ucode[134];\n\t\tstruct config config;\n\t\tstruct multi multi;\n\t\tstruct {\n\t\t\tu32 tbd_array;\n\t\t\tu16 tcb_byte_count;\n\t\t\tu8 threshold;\n\t\t\tu8 tbd_count;\n\t\t\tstruct {\n\t\t\t\t__le32 buf_addr;\n\t\t\t\t__le16 size;\n\t\t\t\tu16 eol;\n\t\t\t} tbd;\n\t\t} tcb;\n\t\t__le32 dump_buffer_addr;\n\t} u;\n\tstruct cb *next;\n\tstruct cb *prev;\n\tdma_addr_t dma_addr;\n\tstruct sk_buff *skb;\n};\n\nstruct cb_compound_hdr_arg {\n\tunsigned int taglen;\n\tconst char *tag;\n\tunsigned int minorversion;\n\tunsigned int cb_ident;\n\tunsigned int nops;\n};\n\nstruct cb_compound_hdr_res {\n\t__be32 *status;\n\tunsigned int taglen;\n\tconst char *tag;\n\t__be32 *nops;\n};\n\nstruct cb_devicenotifyitem;\n\nstruct cb_devicenotifyargs {\n\tuint32_t ndevs;\n\tstruct cb_devicenotifyitem *devs;\n};\n\nstruct nfs4_deviceid {\n\tchar data[16];\n};\n\nstruct cb_devicenotifyitem {\n\tuint32_t cbd_notify_type;\n\tuint32_t cbd_layout_type;\n\tstruct nfs4_deviceid cbd_dev_id;\n\tuint32_t cbd_immediate;\n};\n\nstruct nfs_fh {\n\tshort unsigned int size;\n\tunsigned char data[128];\n};\n\nstruct cb_getattrargs {\n\tstruct nfs_fh fh;\n\tuint32_t bitmap[3];\n};\n\nstruct cb_getattrres {\n\t__be32 status;\n\tuint32_t bitmap[3];\n\tuint64_t size;\n\tuint64_t change_attr;\n\tstruct timespec64 atime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 mtime;\n};\n\nstruct cb_id {\n\t__u32 idx;\n\t__u32 val;\n};\n\nstruct cb_kernel {\n\tconst void *data;\n\tu32 size;\n};\n\nstruct pnfs_layout_range {\n\tu32 iomode;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct nfs4_stateid_struct {\n\tunion {\n\t\tchar data[16];\n\t\tstruct {\n\t\t\t__be32 seqid;\n\t\t\tchar other[12];\n\t\t};\n\t};\n\tenum {\n\t\tNFS4_INVALID_STATEID_TYPE = 0,\n\t\tNFS4_SPECIAL_STATEID_TYPE = 1,\n\t\tNFS4_OPEN_STATEID_TYPE = 2,\n\t\tNFS4_LOCK_STATEID_TYPE = 3,\n\t\tNFS4_DELEGATION_STATEID_TYPE = 4,\n\t\tNFS4_LAYOUT_STATEID_TYPE = 5,\n\t\tNFS4_PNFS_DS_STATEID_TYPE = 6,\n\t\tNFS4_REVOKED_STATEID_TYPE = 7,\n\t\tNFS4_FREED_STATEID_TYPE = 8,\n\t} type;\n};\n\ntypedef struct nfs4_stateid_struct nfs4_stateid;\n\nstruct nfs_fsid {\n\tuint64_t major;\n\tuint64_t minor;\n};\n\nstruct cb_layoutrecallargs {\n\tuint32_t cbl_recall_type;\n\tuint32_t cbl_layout_type;\n\tuint32_t cbl_layoutchanged;\n\tunion {\n\t\tstruct {\n\t\t\tstruct nfs_fh cbl_fh;\n\t\t\tstruct pnfs_layout_range cbl_range;\n\t\t\tnfs4_stateid cbl_stateid;\n\t\t};\n\t\tstruct nfs_fsid cbl_fsid;\n\t};\n};\n\nstruct nfs_lowner {\n\t__u64 clientid;\n\t__u64 id;\n\tdev_t s_dev;\n};\n\nstruct cb_notify_lock_args {\n\tstruct nfs_fh cbnl_fh;\n\tstruct nfs_lowner cbnl_owner;\n\tbool cbnl_valid;\n};\n\nstruct nfs_client;\n\nstruct nfs4_slot;\n\nstruct cb_process_state {\n\tstruct nfs_client *clp;\n\tstruct nfs4_slot *slot;\n\tstruct net *net;\n\tu32 minorversion;\n\t__be32 drc_status;\n\tunsigned int referring_calls;\n};\n\nstruct cb_recallanyargs {\n\tuint32_t craa_objs_to_keep;\n\tuint32_t craa_type_mask;\n};\n\nstruct cb_recallargs {\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tuint32_t truncate;\n};\n\nstruct cb_recallslotargs {\n\tuint32_t crsa_target_highest_slotid;\n};\n\nstruct nfs4_sessionid {\n\tunsigned char data[16];\n};\n\nstruct referring_call_list;\n\nstruct cb_sequenceargs {\n\tstruct sockaddr *csa_addr;\n\tstruct nfs4_sessionid csa_sessionid;\n\tuint32_t csa_sequenceid;\n\tuint32_t csa_slotid;\n\tuint32_t csa_highestslotid;\n\tuint32_t csa_cachethis;\n\tuint32_t csa_nrclists;\n\tstruct referring_call_list *csa_rclists;\n};\n\nstruct cb_sequenceres {\n\t__be32 csr_status;\n\tstruct nfs4_sessionid csr_sessionid;\n\tuint32_t csr_sequenceid;\n\tuint32_t csr_slotid;\n\tuint32_t csr_highestslotid;\n\tuint32_t csr_target_highestslotid;\n};\n\nstruct crypto_cipher;\n\nstruct cbcmac_tfm_ctx {\n\tstruct crypto_cipher *child;\n};\n\nstruct ccm_instance_ctx {\n\tstruct crypto_skcipher_spawn ctr;\n\tstruct crypto_ahash_spawn mac;\n};\n\nstruct ccs_modesel_head {\n\t__u8 _r1;\n\t__u8 medium;\n\t__u8 _r2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_blocks_hi;\n\t__u8 number_blocks_med;\n\t__u8 number_blocks_lo;\n\t__u8 _r3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct cdrom_msf0 {\n\t__u8 minute;\n\t__u8 second;\n\t__u8 frame;\n};\n\nunion cdrom_addr {\n\tstruct cdrom_msf0 msf;\n\tint lba;\n};\n\nstruct cdrom_blk {\n\tunsigned int from;\n\tshort unsigned int len;\n};\n\nstruct cdrom_mechstat_header {\n\t__u8 curslot: 5;\n\t__u8 changer_state: 2;\n\t__u8 fault: 1;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 mech_state: 3;\n\t__u8 curlba[3];\n\t__u8 nslots;\n\t__u16 slot_tablelen;\n};\n\nstruct cdrom_slot {\n\t__u8 change: 1;\n\t__u8 reserved1: 6;\n\t__u8 disc_present: 1;\n\t__u8 reserved2[3];\n};\n\nstruct cdrom_changer_info {\n\tstruct cdrom_mechstat_header hdr;\n\tstruct cdrom_slot slots[256];\n};\n\nstruct cdrom_device_ops;\n\nstruct cdrom_device_info {\n\tconst struct cdrom_device_ops *ops;\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tvoid *handle;\n\tint mask;\n\tint speed;\n\tint capacity;\n\tunsigned int options: 30;\n\tunsigned int mc_flags: 2;\n\tunsigned int vfs_events;\n\tunsigned int ioctl_events;\n\tint use_count;\n\tchar name[20];\n\t__u8 sanyo_slot: 2;\n\t__u8 keeplocked: 1;\n\t__u8 reserved: 5;\n\tint cdda_method;\n\t__u8 last_sense;\n\t__u8 media_written;\n\tshort unsigned int mmc3_profile;\n\tint mrw_mode_page;\n\tbool opened_for_data;\n\t__s64 last_media_change_ms;\n};\n\nstruct cdrom_multisession;\n\nstruct cdrom_mcn;\n\nstruct packet_command;\n\nstruct cdrom_device_ops {\n\tint (*open)(struct cdrom_device_info *, int);\n\tvoid (*release)(struct cdrom_device_info *);\n\tint (*drive_status)(struct cdrom_device_info *, int);\n\tunsigned int (*check_events)(struct cdrom_device_info *, unsigned int, int);\n\tint (*tray_move)(struct cdrom_device_info *, int);\n\tint (*lock_door)(struct cdrom_device_info *, int);\n\tint (*select_speed)(struct cdrom_device_info *, long unsigned int);\n\tint (*get_last_session)(struct cdrom_device_info *, struct cdrom_multisession *);\n\tint (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);\n\tint (*reset)(struct cdrom_device_info *);\n\tint (*audio_ioctl)(struct cdrom_device_info *, unsigned int, void *);\n\tint (*generic_packet)(struct cdrom_device_info *, struct packet_command *);\n\tint (*read_cdda_bpc)(struct cdrom_device_info *, void *, u32, u32, u8 *);\n\tconst int capability;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct cdrom_mcn {\n\t__u8 medium_catalog_number[14];\n};\n\nstruct cdrom_msf {\n\t__u8 cdmsf_min0;\n\t__u8 cdmsf_sec0;\n\t__u8 cdmsf_frame0;\n\t__u8 cdmsf_min1;\n\t__u8 cdmsf_sec1;\n\t__u8 cdmsf_frame1;\n};\n\nstruct cdrom_multisession {\n\tunion cdrom_addr addr;\n\t__u8 xa_flag;\n\t__u8 addr_format;\n};\n\nstruct cdrom_read_audio {\n\tunion cdrom_addr addr;\n\t__u8 addr_format;\n\tint nframes;\n\t__u8 *buf;\n};\n\nstruct cdrom_subchnl {\n\t__u8 cdsc_format;\n\t__u8 cdsc_audiostatus;\n\t__u8 cdsc_adr: 4;\n\t__u8 cdsc_ctrl: 4;\n\t__u8 cdsc_trk;\n\t__u8 cdsc_ind;\n\tunion cdrom_addr cdsc_absaddr;\n\tunion cdrom_addr cdsc_reladdr;\n};\n\nstruct cdrom_sysctl_settings {\n\tchar info[1000];\n\tint autoclose;\n\tint autoeject;\n\tint debug;\n\tint lock;\n\tint check;\n};\n\nstruct cdrom_ti {\n\t__u8 cdti_trk0;\n\t__u8 cdti_ind0;\n\t__u8 cdti_trk1;\n\t__u8 cdti_ind1;\n};\n\nstruct cdrom_timed_media_change_info {\n\t__s64 last_media_change;\n\t__u64 media_flags;\n};\n\nstruct cdrom_tocentry {\n\t__u8 cdte_track;\n\t__u8 cdte_adr: 4;\n\t__u8 cdte_ctrl: 4;\n\t__u8 cdte_format;\n\tunion cdrom_addr cdte_addr;\n\t__u8 cdte_datamode;\n};\n\nstruct cdrom_tochdr {\n\t__u8 cdth_trk0;\n\t__u8 cdth_trk1;\n};\n\nstruct cdrom_volctrl {\n\t__u8 channel0;\n\t__u8 channel1;\n\t__u8 channel2;\n\t__u8 channel3;\n};\n\nstruct clock_event_device;\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct cea_db {\n\tu8 tag_length;\n\tu8 data[0];\n};\n\nstruct drm_edid;\n\nstruct drm_edid_iter {\n\tconst struct drm_edid *drm_edid;\n\tint index;\n};\n\nstruct displayid_iter {\n\tconst struct drm_edid *drm_edid;\n\tconst u8 *section;\n\tint length;\n\tint idx;\n\tint ext_index;\n\tu8 version;\n\tu8 primary_use;\n\tu8 quirks;\n};\n\nstruct cea_db_iter {\n\tstruct drm_edid_iter edid_iter;\n\tstruct displayid_iter displayid_iter;\n\tconst u8 *collection;\n\tint index;\n\tint end;\n};\n\nstruct cea_exception_stacks {\n\tchar DF_stack_guard[4096];\n\tchar DF_stack[8192];\n\tchar NMI_stack_guard[4096];\n\tchar NMI_stack[8192];\n\tchar DB_stack_guard[4096];\n\tchar DB_stack[8192];\n\tchar MCE_stack_guard[4096];\n\tchar MCE_stack[8192];\n\tchar VC_stack_guard[4096];\n\tchar VC_stack[8192];\n\tchar VC2_stack_guard[4096];\n\tchar VC2_stack[8192];\n\tchar IST_top_guard[4096];\n};\n\nstruct cea_sad {\n\tu8 format;\n\tu8 channels;\n\tu8 freq;\n\tu8 byte2;\n};\n\nstruct cec_adapter;\n\nstruct cec_msg;\n\nstruct cec_adap_ops {\n\tint (*adap_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_all_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_pin_enable)(struct cec_adapter *, bool);\n\tint (*adap_log_addr)(struct cec_adapter *, u8);\n\tvoid (*adap_unconfigured)(struct cec_adapter *);\n\tint (*adap_transmit)(struct cec_adapter *, u8, u32, struct cec_msg *);\n\tvoid (*adap_nb_transmit_canceled)(struct cec_adapter *, const struct cec_msg *);\n\tvoid (*adap_status)(struct cec_adapter *, struct seq_file *);\n\tvoid (*adap_free)(struct cec_adapter *);\n\tint (*error_inj_show)(struct cec_adapter *, struct seq_file *);\n\tbool (*error_inj_parse_line)(struct cec_adapter *, char *);\n\tvoid (*configured)(struct cec_adapter *);\n\tint (*received)(struct cec_adapter *, struct cec_msg *);\n};\n\nstruct cec_devnode {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tint minor;\n\tstruct mutex lock;\n\tbool registered;\n\tbool unregistered;\n\tstruct mutex lock_fhs;\n\tstruct list_head fhs;\n};\n\nstruct cec_log_addrs {\n\t__u8 log_addr[4];\n\t__u16 log_addr_mask;\n\t__u8 cec_version;\n\t__u8 num_log_addrs;\n\t__u32 vendor_id;\n\t__u32 flags;\n\tchar osd_name[15];\n\t__u8 primary_device_type[4];\n\t__u8 log_addr_type[4];\n\t__u8 all_device_types[4];\n\t__u8 features[48];\n};\n\nstruct cec_drm_connector_info {\n\t__u32 card_no;\n\t__u32 connector_id;\n};\n\nstruct cec_connector_info {\n\t__u32 type;\n\tunion {\n\t\tstruct cec_drm_connector_info drm;\n\t\t__u32 raw[16];\n\t};\n};\n\nstruct rc_dev;\n\nstruct cec_data;\n\nstruct cec_fh;\n\nstruct cec_adapter {\n\tstruct module *owner;\n\tchar name[32];\n\tstruct cec_devnode devnode;\n\tstruct mutex lock;\n\tstruct rc_dev *rc;\n\tstruct list_head transmit_queue;\n\tunsigned int transmit_queue_sz;\n\tstruct list_head wait_queue;\n\tstruct cec_data *transmitting;\n\tbool transmit_in_progress;\n\tbool transmit_in_progress_aborted;\n\tunsigned int xfer_timeout_ms;\n\tstruct task_struct *kthread_config;\n\tstruct completion config_completion;\n\tstruct task_struct *kthread;\n\twait_queue_head_t kthread_waitq;\n\tconst struct cec_adap_ops *ops;\n\tvoid *priv;\n\tu32 capabilities;\n\tu8 available_log_addrs;\n\tu16 phys_addr;\n\tbool needs_hpd;\n\tbool is_enabled;\n\tbool is_claiming_log_addrs;\n\tbool is_configuring;\n\tbool must_reconfigure;\n\tbool is_configured;\n\tbool cec_pin_is_high;\n\tbool adap_controls_phys_addr;\n\tu8 last_initiator;\n\tu32 monitor_all_cnt;\n\tu32 monitor_pin_cnt;\n\tu32 follower_cnt;\n\tstruct cec_fh *cec_follower;\n\tstruct cec_fh *cec_initiator;\n\tbool passthrough;\n\tstruct cec_log_addrs log_addrs;\n\tstruct cec_connector_info conn_info;\n\tu32 tx_timeout_cnt;\n\tu32 tx_low_drive_cnt;\n\tu32 tx_error_cnt;\n\tu32 tx_arb_lost_cnt;\n\tu32 tx_low_drive_log_cnt;\n\tu32 tx_error_log_cnt;\n\tstruct dentry *cec_dir;\n\tu32 sequence;\n\tchar input_phys[40];\n};\n\nstruct cec_msg {\n\t__u64 tx_ts;\n\t__u64 rx_ts;\n\t__u32 len;\n\t__u32 timeout;\n\t__u32 sequence;\n\t__u32 flags;\n\t__u8 msg[16];\n\t__u8 reply;\n\t__u8 rx_status;\n\t__u8 tx_status;\n\t__u8 tx_arb_lost_cnt;\n\t__u8 tx_nack_cnt;\n\t__u8 tx_low_drive_cnt;\n\t__u8 tx_error_cnt;\n};\n\nstruct cec_data {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tstruct cec_msg msg;\n\tu8 match_len;\n\tu8 match_reply[5];\n\tstruct cec_fh *fh;\n\tstruct delayed_work work;\n\tstruct completion c;\n\tu8 attempts;\n\tbool blocking;\n\tbool completed;\n};\n\nstruct cec_event_state_change {\n\t__u16 phys_addr;\n\t__u16 log_addr_mask;\n\t__u16 have_conn_info;\n};\n\nstruct cec_event_lost_msgs {\n\t__u32 lost_msgs;\n};\n\nstruct cec_event {\n\t__u64 ts;\n\t__u32 event;\n\t__u32 flags;\n\tunion {\n\t\tstruct cec_event_state_change state_change;\n\t\tstruct cec_event_lost_msgs lost_msgs;\n\t\t__u32 raw[16];\n\t};\n};\n\nstruct cec_event_entry {\n\tstruct list_head list;\n\tstruct cec_event ev;\n};\n\nstruct cec_fh {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tu8 mode_initiator;\n\tu8 mode_follower;\n\twait_queue_head_t wait;\n\tstruct mutex lock;\n\tstruct list_head events[8];\n\tu16 queued_events[8];\n\tunsigned int total_queued_events;\n\tstruct cec_event_entry core_events[2];\n\tstruct list_head msgs;\n\tunsigned int queued_msgs;\n};\n\nstruct mac_address {\n\tu8 addr[6];\n};\n\nstruct cfg80211_acl_data {\n\tenum nl80211_acl_policy acl_policy;\n\tint n_acl_entries;\n\tstruct mac_address mac_addrs[0];\n};\n\nstruct ieee80211_edmg {\n\tu8 channels;\n\tenum ieee80211_edmg_bw_config bw_config;\n};\n\nstruct ieee80211_channel;\n\nstruct cfg80211_chan_def {\n\tstruct ieee80211_channel *chan;\n\tenum nl80211_chan_width width;\n\tu32 center_freq1;\n\tu32 center_freq2;\n\tstruct ieee80211_edmg edmg;\n\tu16 freq1_offset;\n\tu16 punctured;\n\tbool s1g_primary_2mhz;\n};\n\nstruct cfg80211_he_bss_color {\n\tu8 color;\n\tbool enabled;\n\tbool partial;\n};\n\nstruct cfg80211_beacon_data {\n\tunsigned int link_id;\n\tconst u8 *head;\n\tconst u8 *tail;\n\tconst u8 *beacon_ies;\n\tconst u8 *proberesp_ies;\n\tconst u8 *assocresp_ies;\n\tconst u8 *probe_resp;\n\tconst u8 *lci;\n\tconst u8 *civicloc;\n\tstruct cfg80211_mbssid_elems *mbssid_ies;\n\tstruct cfg80211_rnr_elems *rnr_ies;\n\ts8 ftm_responder;\n\tsize_t head_len;\n\tsize_t tail_len;\n\tsize_t beacon_ies_len;\n\tsize_t proberesp_ies_len;\n\tsize_t assocresp_ies_len;\n\tsize_t probe_resp_len;\n\tsize_t lci_len;\n\tsize_t civicloc_len;\n\tstruct cfg80211_he_bss_color he_bss_color;\n\tbool he_bss_color_valid;\n};\n\nstruct cfg80211_crypto_settings {\n\tu32 wpa_versions;\n\tu32 cipher_group;\n\tint n_ciphers_pairwise;\n\tu32 ciphers_pairwise[5];\n\tint n_akm_suites;\n\tu32 akm_suites[10];\n\tbool control_port;\n\t__be16 control_port_ethertype;\n\tbool control_port_no_encrypt;\n\tbool control_port_over_nl80211;\n\tbool control_port_no_preauth;\n\tconst u8 *psk;\n\tconst u8 *sae_pwd;\n\tu8 sae_pwd_len;\n\tenum nl80211_sae_pwe_mechanism sae_pwe;\n};\n\nstruct cfg80211_bitrate_mask {\n\tstruct {\n\t\tu32 legacy;\n\t\tu8 ht_mcs[10];\n\t\tu16 vht_mcs[8];\n\t\tu16 he_mcs[8];\n\t\tu16 eht_mcs[16];\n\t\tenum nl80211_txrate_gi gi;\n\t\tenum nl80211_he_gi he_gi;\n\t\tenum nl80211_eht_gi eht_gi;\n\t\tenum nl80211_he_ltf he_ltf;\n\t\tenum nl80211_eht_ltf eht_ltf;\n\t} control[6];\n};\n\nstruct ieee80211_he_obss_pd {\n\tbool enable;\n\tu8 sr_ctrl;\n\tu8 non_srg_max_offset;\n\tu8 min_offset;\n\tu8 max_offset;\n\tu8 bss_color_bitmap[8];\n\tu8 partial_bssid_bitmap[8];\n};\n\nstruct cfg80211_fils_discovery {\n\tbool update;\n\tu32 min_interval;\n\tu32 max_interval;\n\tsize_t tmpl_len;\n\tconst u8 *tmpl;\n};\n\nstruct cfg80211_unsol_bcast_probe_resp {\n\tbool update;\n\tu32 interval;\n\tsize_t tmpl_len;\n\tconst u8 *tmpl;\n};\n\nstruct wireless_dev;\n\nstruct cfg80211_mbssid_config {\n\tstruct wireless_dev *tx_wdev;\n\tu8 tx_link_id;\n\tu8 index;\n\tbool ema;\n};\n\nstruct cfg80211_s1g_short_beacon {\n\tbool update;\n\tconst u8 *short_head;\n\tconst u8 *short_tail;\n\tsize_t short_head_len;\n\tsize_t short_tail_len;\n};\n\nstruct ieee80211_ht_cap;\n\nstruct ieee80211_vht_cap;\n\nstruct ieee80211_he_cap_elem;\n\nstruct ieee80211_he_operation;\n\nstruct ieee80211_eht_cap_elem;\n\nstruct ieee80211_eht_operation;\n\nstruct ieee80211_uhr_operation;\n\nstruct cfg80211_ap_settings {\n\tstruct cfg80211_chan_def chandef;\n\tstruct cfg80211_beacon_data beacon;\n\tint beacon_interval;\n\tint dtim_period;\n\tconst u8 *ssid;\n\tsize_t ssid_len;\n\tenum nl80211_hidden_ssid hidden_ssid;\n\tstruct cfg80211_crypto_settings crypto;\n\tbool privacy;\n\tenum nl80211_auth_type auth_type;\n\tint inactivity_timeout;\n\tu8 p2p_ctwindow;\n\tbool p2p_opp_ps;\n\tconst struct cfg80211_acl_data *acl;\n\tbool pbss;\n\tstruct cfg80211_bitrate_mask beacon_rate;\n\tconst struct ieee80211_ht_cap *ht_cap;\n\tconst struct ieee80211_vht_cap *vht_cap;\n\tconst struct ieee80211_he_cap_elem *he_cap;\n\tconst struct ieee80211_he_operation *he_oper;\n\tconst struct ieee80211_eht_cap_elem *eht_cap;\n\tconst struct ieee80211_eht_operation *eht_oper;\n\tconst struct ieee80211_uhr_operation *uhr_oper;\n\tbool ht_required;\n\tbool vht_required;\n\tbool he_required;\n\tbool sae_h2e_required;\n\tbool twt_responder;\n\tu32 flags;\n\tstruct ieee80211_he_obss_pd he_obss_pd;\n\tstruct cfg80211_fils_discovery fils_discovery;\n\tstruct cfg80211_unsol_bcast_probe_resp unsol_bcast_probe_resp;\n\tstruct cfg80211_mbssid_config mbssid_config;\n\tu8 s1g_long_beacon_period;\n\tstruct cfg80211_s1g_short_beacon s1g_short_beacon;\n};\n\nstruct cfg80211_ap_update {\n\tstruct cfg80211_beacon_data beacon;\n\tstruct cfg80211_fils_discovery fils_discovery;\n\tstruct cfg80211_unsol_bcast_probe_resp unsol_bcast_probe_resp;\n\tstruct cfg80211_s1g_short_beacon s1g_short_beacon;\n};\n\nstruct cfg80211_bss;\n\nstruct cfg80211_assoc_failure {\n\tconst u8 *ap_mld_addr;\n\tstruct cfg80211_bss *bss[15];\n\tbool timeout;\n};\n\nstruct cfg80211_assoc_link {\n\tstruct cfg80211_bss *bss;\n\tconst u8 *elems;\n\tsize_t elems_len;\n\tint error;\n};\n\nstruct ieee80211_mcs_info {\n\tu8 rx_mask[10];\n\t__le16 rx_highest;\n\tu8 tx_params;\n\tu8 reserved[3];\n};\n\nstruct ieee80211_ht_cap {\n\t__le16 cap_info;\n\tu8 ampdu_params_info;\n\tstruct ieee80211_mcs_info mcs;\n\t__le16 extended_ht_cap_info;\n\t__le32 tx_BF_cap_info;\n\tu8 antenna_selection_info;\n} __attribute__((packed));\n\nstruct ieee80211_vht_mcs_info {\n\t__le16 rx_mcs_map;\n\t__le16 rx_highest;\n\t__le16 tx_mcs_map;\n\t__le16 tx_highest;\n};\n\nstruct ieee80211_vht_cap {\n\t__le32 vht_cap_info;\n\tstruct ieee80211_vht_mcs_info supp_mcs;\n};\n\nstruct ieee80211_s1g_cap {\n\tu8 capab_info[10];\n\tu8 supp_mcs_nss[5];\n};\n\nstruct cfg80211_assoc_request {\n\tstruct cfg80211_bss *bss;\n\tconst u8 *ie;\n\tconst u8 *prev_bssid;\n\tsize_t ie_len;\n\tstruct cfg80211_crypto_settings crypto;\n\tbool use_mfp;\n\tint: 0;\n\tu32 flags;\n\tconst u8 *supported_selectors;\n\tu8 supported_selectors_len;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tstruct ieee80211_vht_cap vht_capa;\n\tstruct ieee80211_vht_cap vht_capa_mask;\n\tlong: 0;\n\tconst u8 *fils_kek;\n\tsize_t fils_kek_len;\n\tconst u8 *fils_nonces;\n\tstruct ieee80211_s1g_cap s1g_capa;\n\tstruct ieee80211_s1g_cap s1g_capa_mask;\n\tlong: 0;\n\tstruct cfg80211_assoc_link links[15];\n\tconst u8 *ap_mld_addr;\n\ts8 link_id;\n\tshort: 0;\n\tu16 ext_mld_capa_ops;\n\tlong: 0;\n} __attribute__((packed));\n\nstruct cfg80211_auth_request {\n\tstruct cfg80211_bss *bss;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tconst u8 *supported_selectors;\n\tu8 supported_selectors_len;\n\tenum nl80211_auth_type auth_type;\n\tconst u8 *key;\n\tu8 key_len;\n\ts8 key_idx;\n\tconst u8 *auth_data;\n\tsize_t auth_data_len;\n\ts8 link_id;\n\tconst u8 *ap_mld_addr;\n};\n\nstruct cfg80211_beacon_registration {\n\tstruct list_head list;\n\tu32 nlportid;\n};\n\nstruct cfg80211_beaconing_check_config {\n\tenum nl80211_iftype iftype;\n\tenum ieee80211_ap_reg_power reg_power;\n\tbool relax;\n};\n\nstruct cfg80211_bss_ies;\n\nstruct cfg80211_bss {\n\tstruct ieee80211_channel *channel;\n\tconst struct cfg80211_bss_ies *ies;\n\tconst struct cfg80211_bss_ies *beacon_ies;\n\tconst struct cfg80211_bss_ies *proberesp_ies;\n\tstruct cfg80211_bss *hidden_beacon_bss;\n\tstruct cfg80211_bss *transmitted_bss;\n\tstruct list_head nontrans_list;\n\ts32 signal;\n\tu64 ts_boottime;\n\tu16 beacon_interval;\n\tu16 capability;\n\tu8 bssid[6];\n\tu8 chains;\n\ts8 chain_signal[4];\n\tu8 proberesp_ecsa_stuck: 1;\n\tu8 bssid_index;\n\tu8 max_bssid_indicator;\n\tu8 use_for;\n\tu8 cannot_use_reasons;\n\tlong: 0;\n\tu8 priv[0];\n};\n\nstruct cfg80211_bss_ies {\n\tu64 tsf;\n\tstruct callback_head callback_head;\n\tint len;\n\tbool from_beacon;\n\tu8 data[0];\n};\n\nstruct cfg80211_bss_select_adjust {\n\tenum nl80211_band band;\n\ts8 delta;\n};\n\nstruct cfg80211_bss_selection {\n\tenum nl80211_bss_select_attr behaviour;\n\tunion {\n\t\tenum nl80211_band band_pref;\n\t\tstruct cfg80211_bss_select_adjust adjust;\n\t} param;\n};\n\nstruct key_params {\n\tconst u8 *key;\n\tconst u8 *seq;\n\tint key_len;\n\tint seq_len;\n\tu16 vlan_id;\n\tu32 cipher;\n\tenum nl80211_key_mode mode;\n};\n\nstruct cfg80211_cached_keys {\n\tstruct key_params params[4];\n\tu8 data[52];\n\tint def;\n};\n\nstruct cfg80211_pkt_pattern;\n\nstruct cfg80211_coalesce_rules {\n\tint delay;\n\tenum nl80211_coalesce_condition condition;\n\tstruct cfg80211_pkt_pattern *patterns;\n\tint n_patterns;\n};\n\nstruct cfg80211_coalesce {\n\tint n_rules;\n\tstruct cfg80211_coalesce_rules rules[0];\n};\n\nstruct cfg80211_colocated_ap {\n\tstruct list_head list;\n\tu8 bssid[6];\n\tu8 ssid[32];\n\tsize_t ssid_len;\n\tu32 short_ssid;\n\tu32 center_freq;\n\tu8 unsolicited_probe: 1;\n\tu8 oct_recommended: 1;\n\tu8 same_ssid: 1;\n\tu8 multi_bss: 1;\n\tu8 transmitted_bssid: 1;\n\tu8 colocated_ess: 1;\n\tu8 short_ssid_valid: 1;\n\ts8 psd_20;\n};\n\nstruct cfg80211_color_change_settings {\n\tstruct cfg80211_beacon_data beacon_color_change;\n\tu16 counter_offset_beacon;\n\tu16 counter_offset_presp;\n\tstruct cfg80211_beacon_data beacon_next;\n\tstruct cfg80211_unsol_bcast_probe_resp unsol_bcast_probe_resp;\n\tu8 count;\n\tu8 color;\n\tu8 link_id;\n};\n\nstruct cfg80211_connect_params {\n\tstruct ieee80211_channel *channel;\n\tstruct ieee80211_channel *channel_hint;\n\tconst u8 *bssid;\n\tconst u8 *bssid_hint;\n\tconst u8 *ssid;\n\tsize_t ssid_len;\n\tenum nl80211_auth_type auth_type;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tbool privacy;\n\tenum nl80211_mfp mfp;\n\tstruct cfg80211_crypto_settings crypto;\n\tconst u8 *key;\n\tu8 key_len;\n\tu8 key_idx;\n\tu32 flags;\n\tint bg_scan_period;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tstruct ieee80211_vht_cap vht_capa;\n\tstruct ieee80211_vht_cap vht_capa_mask;\n\tbool pbss;\n\tstruct cfg80211_bss_selection bss_select;\n\tconst u8 *prev_bssid;\n\tconst u8 *fils_erp_username;\n\tsize_t fils_erp_username_len;\n\tconst u8 *fils_erp_realm;\n\tsize_t fils_erp_realm_len;\n\tu16 fils_erp_next_seq_num;\n\tconst u8 *fils_erp_rrk;\n\tsize_t fils_erp_rrk_len;\n\tbool want_1x;\n\tstruct ieee80211_edmg edmg;\n};\n\nstruct cfg80211_conn {\n\tstruct cfg80211_connect_params params;\n\tenum {\n\t\tCFG80211_CONN_SCANNING = 0,\n\t\tCFG80211_CONN_SCAN_AGAIN = 1,\n\t\tCFG80211_CONN_AUTHENTICATE_NEXT = 2,\n\t\tCFG80211_CONN_AUTHENTICATING = 3,\n\t\tCFG80211_CONN_AUTH_FAILED_TIMEOUT = 4,\n\t\tCFG80211_CONN_ASSOCIATE_NEXT = 5,\n\t\tCFG80211_CONN_ASSOCIATING = 6,\n\t\tCFG80211_CONN_ASSOC_FAILED = 7,\n\t\tCFG80211_CONN_ASSOC_FAILED_TIMEOUT = 8,\n\t\tCFG80211_CONN_DEAUTH = 9,\n\t\tCFG80211_CONN_ABANDON = 10,\n\t\tCFG80211_CONN_CONNECTED = 11,\n\t} state;\n\tu8 bssid[6];\n\tu8 prev_bssid[6];\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tbool auto_auth;\n\tbool prev_bssid_valid;\n};\n\nstruct cfg80211_fils_resp_params {\n\tconst u8 *kek;\n\tsize_t kek_len;\n\tbool update_erp_next_seq_num;\n\tu16 erp_next_seq_num;\n\tconst u8 *pmk;\n\tsize_t pmk_len;\n\tconst u8 *pmkid;\n};\n\nstruct cfg80211_connect_resp_params {\n\tint status;\n\tconst u8 *req_ie;\n\tsize_t req_ie_len;\n\tconst u8 *resp_ie;\n\tsize_t resp_ie_len;\n\tstruct cfg80211_fils_resp_params fils;\n\tenum nl80211_timeout_reason timeout_reason;\n\tconst u8 *ap_mld_addr;\n\tu16 valid_links;\n\tstruct {\n\t\tconst u8 *addr;\n\t\tconst u8 *bssid;\n\t\tstruct cfg80211_bss *bss;\n\t\tu16 status;\n\t} links[15];\n};\n\nstruct cfg80211_cqm_config {\n\tstruct callback_head callback_head;\n\tu32 rssi_hyst;\n\ts32 last_rssi_event_value;\n\tenum nl80211_cqm_rssi_threshold_event last_rssi_event_type;\n\tbool use_range_api;\n\tint n_rssi_thresholds;\n\ts32 rssi_thresholds[0];\n};\n\nstruct cfg80211_csa_settings {\n\tstruct cfg80211_chan_def chandef;\n\tstruct cfg80211_beacon_data beacon_csa;\n\tconst u16 *counter_offsets_beacon;\n\tconst u16 *counter_offsets_presp;\n\tunsigned int n_counter_offsets_beacon;\n\tunsigned int n_counter_offsets_presp;\n\tstruct cfg80211_beacon_data beacon_after;\n\tstruct cfg80211_unsol_bcast_probe_resp unsol_bcast_probe_resp;\n\tbool radar_required;\n\tbool block_tx;\n\tu8 count;\n\tu8 link_id;\n};\n\nstruct cfg80211_deauth_request {\n\tconst u8 *bssid;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu16 reason_code;\n\tbool local_state_change;\n};\n\nstruct cfg80211_disassoc_request {\n\tconst u8 *ap_addr;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu16 reason_code;\n\tbool local_state_change;\n};\n\nstruct cfg80211_dscp_exception {\n\tu8 dscp;\n\tu8 up;\n};\n\nstruct cfg80211_dscp_range {\n\tu8 low;\n\tu8 high;\n};\n\nstruct cfg80211_roam_info {\n\tconst u8 *req_ie;\n\tsize_t req_ie_len;\n\tconst u8 *resp_ie;\n\tsize_t resp_ie_len;\n\tstruct cfg80211_fils_resp_params fils;\n\tconst u8 *ap_mld_addr;\n\tu16 valid_links;\n\tstruct {\n\t\tconst u8 *addr;\n\t\tconst u8 *bssid;\n\t\tstruct ieee80211_channel *channel;\n\t\tstruct cfg80211_bss *bss;\n\t} links[15];\n};\n\nstruct cfg80211_event {\n\tstruct list_head list;\n\tenum cfg80211_event_type type;\n\tunion {\n\t\tstruct cfg80211_connect_resp_params cr;\n\t\tstruct cfg80211_roam_info rm;\n\t\tstruct {\n\t\t\tconst u8 *ie;\n\t\t\tsize_t ie_len;\n\t\t\tu16 reason;\n\t\t\tbool locally_generated;\n\t\t} dc;\n\t\tstruct {\n\t\t\tu8 bssid[6];\n\t\t\tstruct ieee80211_channel *channel;\n\t\t} ij;\n\t\tstruct {\n\t\t\tu8 peer_addr[6];\n\t\t\tconst u8 *td_bitmap;\n\t\t\tu8 td_bitmap_len;\n\t\t} pa;\n\t};\n\tint link_id;\n};\n\nstruct cfg80211_ssid {\n\tu8 ssid[32];\n\tu8 ssid_len;\n};\n\nstruct cfg80211_external_auth_params {\n\tenum nl80211_external_auth_action action;\n\tu8 bssid[6];\n\tstruct cfg80211_ssid ssid;\n\tunsigned int key_mgmt_suite;\n\tu16 status;\n\tconst u8 *pmkid;\n\tu8 mld_addr[6];\n};\n\nstruct cfg80211_fils_aad {\n\tconst u8 *macaddr;\n\tconst u8 *kek;\n\tu8 kek_len;\n\tconst u8 *snonce;\n\tconst u8 *anonce;\n};\n\nstruct cfg80211_ft_event_params {\n\tconst u8 *ies;\n\tsize_t ies_len;\n\tconst u8 *target_ap;\n\tconst u8 *ric_ies;\n\tsize_t ric_ies_len;\n};\n\nstruct cfg80211_ftm_responder_stats {\n\tu32 filled;\n\tu32 success_num;\n\tu32 partial_num;\n\tu32 failed_num;\n\tu32 asap_num;\n\tu32 non_asap_num;\n\tu64 total_duration_ms;\n\tu32 unknown_triggers_num;\n\tu32 reschedule_requests_num;\n\tu32 out_of_window_triggers_num;\n};\n\nstruct cfg80211_gtk_rekey_data {\n\tconst u8 *kek;\n\tconst u8 *kck;\n\tconst u8 *replay_ctr;\n\tu32 akm;\n\tu8 kek_len;\n\tu8 kck_len;\n};\n\nstruct cfg80211_ibss_params {\n\tconst u8 *ssid;\n\tconst u8 *bssid;\n\tstruct cfg80211_chan_def chandef;\n\tconst u8 *ie;\n\tu8 ssid_len;\n\tu8 ie_len;\n\tu16 beacon_interval;\n\tu32 basic_rates;\n\tbool channel_fixed;\n\tbool privacy;\n\tbool control_port;\n\tbool control_port_over_nl80211;\n\tbool userspace_handles_dfs;\n\tint mcast_rate[6];\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tstruct key_params *wep_keys;\n\tint wep_tx_key;\n};\n\nstruct cfg80211_inform_bss {\n\tstruct ieee80211_channel *chan;\n\ts32 signal;\n\tu64 boottime_ns;\n\tu64 parent_tsf;\n\tu8 parent_bssid[6];\n\tu8 chains;\n\ts8 chain_signal[4];\n\tu8 restrict_use: 1;\n\tu8 use_for: 7;\n\tu8 cannot_use_reasons;\n\tvoid *drv_data;\n};\n\nstruct cfg80211_inform_single_bss_data {\n\tstruct cfg80211_inform_bss *drv_data;\n\tenum cfg80211_bss_frame_type ftype;\n\tstruct ieee80211_channel *channel;\n\tu8 bssid[6];\n\tu64 tsf;\n\tu16 capability;\n\tu16 beacon_interval;\n\tconst u8 *ie;\n\tsize_t ielen;\n\tenum bss_source_type bss_source;\n\tstruct cfg80211_bss *source_bss;\n\tu8 max_bssid_indicator;\n\tu8 bssid_index;\n\tu8 use_for;\n\tu64 cannot_use_reasons;\n};\n\nstruct cfg80211_internal_bss {\n\tstruct list_head list;\n\tstruct list_head hidden_list;\n\tstruct rb_node rbn;\n\tlong unsigned int ts;\n\tlong unsigned int refcount;\n\tatomic_t hold;\n\tu64 parent_tsf;\n\tu8 parent_bssid[6];\n\tenum bss_source_type bss_source;\n\tstruct cfg80211_bss pub;\n};\n\nstruct cfg80211_match_set {\n\tstruct cfg80211_ssid ssid;\n\tu8 bssid[6];\n\ts32 rssi_thold;\n};\n\nstruct cfg80211_mbssid_elems {\n\tu8 cnt;\n\tstruct {\n\t\tconst u8 *data;\n\t\tsize_t len;\n\t} elem[0];\n};\n\nstruct cfg80211_mgmt_registration {\n\tstruct list_head list;\n\tstruct wireless_dev *wdev;\n\tu32 nlportid;\n\tint match_len;\n\t__le16 frame_type;\n\tbool multicast_rx;\n\tu8 match[0];\n};\n\nstruct cfg80211_mgmt_tx_params {\n\tstruct ieee80211_channel *chan;\n\tbool offchan;\n\tunsigned int wait;\n\tconst u8 *buf;\n\tsize_t len;\n\tbool no_cck;\n\tbool dont_wait_for_ack;\n\tint n_csa_offsets;\n\tconst u16 *csa_offsets;\n\tint link_id;\n};\n\nstruct cfg80211_ml_reconf_req {\n\tstruct cfg80211_assoc_link add_links[15];\n\tu16 rem_links;\n\tu16 ext_mld_capa_ops;\n};\n\nstruct ieee80211_multi_link_elem;\n\nstruct ieee80211_mle_per_sta_profile;\n\nstruct cfg80211_mle {\n\tstruct ieee80211_multi_link_elem *mle;\n\tstruct ieee80211_mle_per_sta_profile *sta_prof[15];\n\tssize_t sta_prof_len[15];\n\tu8 data[0];\n};\n\nstruct cfg80211_mlo_reconf_done_data {\n\tconst u8 *buf;\n\tsize_t len;\n\tbool driver_initiated;\n\tu16 added_links;\n\tstruct {\n\t\tstruct cfg80211_bss *bss;\n\t\tu8 *addr;\n\t} links[15];\n};\n\nstruct cfg80211_nan_band_config {\n\tstruct ieee80211_channel *chan;\n\ts8 rssi_close;\n\ts8 rssi_middle;\n\tu8 awake_dw_interval;\n\tbool disable_scan;\n};\n\nstruct cfg80211_nan_conf {\n\tu8 master_pref;\n\tu8 bands;\n\tconst u8 *cluster_id;\n\tu16 scan_period;\n\tu16 scan_dwell_time;\n\tu8 discovery_beacon_interval;\n\tbool enable_dw_notification;\n\tstruct cfg80211_nan_band_config band_cfgs[6];\n\tconst u8 *extra_nan_attrs;\n\tu16 extra_nan_attrs_len;\n\tconst u8 *vendor_elems;\n\tu16 vendor_elems_len;\n};\n\nstruct cfg80211_nan_func_filter;\n\nstruct cfg80211_nan_func {\n\tenum nl80211_nan_function_type type;\n\tu8 service_id[6];\n\tu8 publish_type;\n\tbool close_range;\n\tbool publish_bcast;\n\tbool subscribe_active;\n\tu8 followup_id;\n\tu8 followup_reqid;\n\tstruct mac_address followup_dest;\n\tu32 ttl;\n\tconst u8 *serv_spec_info;\n\tu8 serv_spec_info_len;\n\tbool srf_include;\n\tconst u8 *srf_bf;\n\tu8 srf_bf_len;\n\tu8 srf_bf_idx;\n\tstruct mac_address *srf_macs;\n\tint srf_num_macs;\n\tstruct cfg80211_nan_func_filter *rx_filters;\n\tstruct cfg80211_nan_func_filter *tx_filters;\n\tu8 num_tx_filters;\n\tu8 num_rx_filters;\n\tu8 instance_id;\n\tu64 cookie;\n};\n\nstruct cfg80211_nan_func_filter {\n\tconst u8 *filter;\n\tu8 len;\n};\n\nstruct cfg80211_nan_match_params {\n\tenum nl80211_nan_function_type type;\n\tu8 inst_id;\n\tu8 peer_inst_id;\n\tconst u8 *addr;\n\tu8 info_len;\n\tconst u8 *info;\n\tu64 cookie;\n};\n\nstruct wiphy;\n\nstruct cfg80211_wowlan;\n\nstruct vif_params;\n\nstruct station_parameters;\n\nstruct station_del_parameters;\n\nstruct station_info;\n\nstruct mpath_info;\n\nstruct mesh_config;\n\nstruct mesh_setup;\n\nstruct ocb_setup;\n\nstruct ieee80211_txq_params;\n\nstruct cfg80211_scan_request;\n\nstruct survey_info;\n\nstruct cfg80211_pmksa;\n\nstruct mgmt_frame_regs;\n\nstruct cfg80211_sched_scan_request;\n\nstruct cfg80211_update_ft_ies_params;\n\nstruct cfg80211_qos_map;\n\nstruct cfg80211_txq_stats;\n\nstruct cfg80211_pmk_conf;\n\nstruct cfg80211_pmsr_request;\n\nstruct cfg80211_update_owe_info;\n\nstruct cfg80211_tid_config;\n\nstruct cfg80211_sar_specs;\n\nstruct link_station_parameters;\n\nstruct link_station_del_parameters;\n\nstruct cfg80211_set_hw_timestamp;\n\nstruct cfg80211_ttlm_params;\n\nstruct cfg80211_ops {\n\tint (*suspend)(struct wiphy *, struct cfg80211_wowlan *);\n\tint (*resume)(struct wiphy *);\n\tvoid (*set_wakeup)(struct wiphy *, bool);\n\tstruct wireless_dev * (*add_virtual_intf)(struct wiphy *, const char *, unsigned char, enum nl80211_iftype, struct vif_params *);\n\tint (*del_virtual_intf)(struct wiphy *, struct wireless_dev *);\n\tint (*change_virtual_intf)(struct wiphy *, struct net_device *, enum nl80211_iftype, struct vif_params *);\n\tint (*add_intf_link)(struct wiphy *, struct wireless_dev *, unsigned int);\n\tvoid (*del_intf_link)(struct wiphy *, struct wireless_dev *, unsigned int);\n\tint (*add_key)(struct wiphy *, struct net_device *, int, u8, bool, const u8 *, struct key_params *);\n\tint (*get_key)(struct wiphy *, struct net_device *, int, u8, bool, const u8 *, void *, void (*)(void *, struct key_params *));\n\tint (*del_key)(struct wiphy *, struct net_device *, int, u8, bool, const u8 *);\n\tint (*set_default_key)(struct wiphy *, struct net_device *, int, u8, bool, bool);\n\tint (*set_default_mgmt_key)(struct wiphy *, struct net_device *, int, u8);\n\tint (*set_default_beacon_key)(struct wiphy *, struct net_device *, int, u8);\n\tint (*start_ap)(struct wiphy *, struct net_device *, struct cfg80211_ap_settings *);\n\tint (*change_beacon)(struct wiphy *, struct net_device *, struct cfg80211_ap_update *);\n\tint (*stop_ap)(struct wiphy *, struct net_device *, unsigned int);\n\tint (*add_station)(struct wiphy *, struct net_device *, const u8 *, struct station_parameters *);\n\tint (*del_station)(struct wiphy *, struct net_device *, struct station_del_parameters *);\n\tint (*change_station)(struct wiphy *, struct net_device *, const u8 *, struct station_parameters *);\n\tint (*get_station)(struct wiphy *, struct net_device *, const u8 *, struct station_info *);\n\tint (*dump_station)(struct wiphy *, struct net_device *, int, u8 *, struct station_info *);\n\tint (*add_mpath)(struct wiphy *, struct net_device *, const u8 *, const u8 *);\n\tint (*del_mpath)(struct wiphy *, struct net_device *, const u8 *);\n\tint (*change_mpath)(struct wiphy *, struct net_device *, const u8 *, const u8 *);\n\tint (*get_mpath)(struct wiphy *, struct net_device *, u8 *, u8 *, struct mpath_info *);\n\tint (*dump_mpath)(struct wiphy *, struct net_device *, int, u8 *, u8 *, struct mpath_info *);\n\tint (*get_mpp)(struct wiphy *, struct net_device *, u8 *, u8 *, struct mpath_info *);\n\tint (*dump_mpp)(struct wiphy *, struct net_device *, int, u8 *, u8 *, struct mpath_info *);\n\tint (*get_mesh_config)(struct wiphy *, struct net_device *, struct mesh_config *);\n\tint (*update_mesh_config)(struct wiphy *, struct net_device *, u32, const struct mesh_config *);\n\tint (*join_mesh)(struct wiphy *, struct net_device *, const struct mesh_config *, const struct mesh_setup *);\n\tint (*leave_mesh)(struct wiphy *, struct net_device *);\n\tint (*join_ocb)(struct wiphy *, struct net_device *, struct ocb_setup *);\n\tint (*leave_ocb)(struct wiphy *, struct net_device *);\n\tint (*change_bss)(struct wiphy *, struct net_device *, struct bss_parameters *);\n\tvoid (*inform_bss)(struct wiphy *, struct cfg80211_bss *, const struct cfg80211_bss_ies *, void *);\n\tint (*set_txq_params)(struct wiphy *, struct net_device *, struct ieee80211_txq_params *);\n\tint (*libertas_set_mesh_channel)(struct wiphy *, struct net_device *, struct ieee80211_channel *);\n\tint (*set_monitor_channel)(struct wiphy *, struct net_device *, struct cfg80211_chan_def *);\n\tint (*scan)(struct wiphy *, struct cfg80211_scan_request *);\n\tvoid (*abort_scan)(struct wiphy *, struct wireless_dev *);\n\tint (*auth)(struct wiphy *, struct net_device *, struct cfg80211_auth_request *);\n\tint (*assoc)(struct wiphy *, struct net_device *, struct cfg80211_assoc_request *);\n\tint (*deauth)(struct wiphy *, struct net_device *, struct cfg80211_deauth_request *);\n\tint (*disassoc)(struct wiphy *, struct net_device *, struct cfg80211_disassoc_request *);\n\tint (*connect)(struct wiphy *, struct net_device *, struct cfg80211_connect_params *);\n\tint (*update_connect_params)(struct wiphy *, struct net_device *, struct cfg80211_connect_params *, u32);\n\tint (*disconnect)(struct wiphy *, struct net_device *, u16);\n\tint (*join_ibss)(struct wiphy *, struct net_device *, struct cfg80211_ibss_params *);\n\tint (*leave_ibss)(struct wiphy *, struct net_device *);\n\tint (*set_mcast_rate)(struct wiphy *, struct net_device *, int *);\n\tint (*set_wiphy_params)(struct wiphy *, int, u32);\n\tint (*set_tx_power)(struct wiphy *, struct wireless_dev *, int, enum nl80211_tx_power_setting, int);\n\tint (*get_tx_power)(struct wiphy *, struct wireless_dev *, int, unsigned int, int *);\n\tvoid (*rfkill_poll)(struct wiphy *);\n\tint (*set_bitrate_mask)(struct wiphy *, struct net_device *, unsigned int, const u8 *, const struct cfg80211_bitrate_mask *);\n\tint (*dump_survey)(struct wiphy *, struct net_device *, int, struct survey_info *);\n\tint (*set_pmksa)(struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\tint (*del_pmksa)(struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\tint (*flush_pmksa)(struct wiphy *, struct net_device *);\n\tint (*remain_on_channel)(struct wiphy *, struct wireless_dev *, struct ieee80211_channel *, unsigned int, u64 *);\n\tint (*cancel_remain_on_channel)(struct wiphy *, struct wireless_dev *, u64);\n\tint (*mgmt_tx)(struct wiphy *, struct wireless_dev *, struct cfg80211_mgmt_tx_params *, u64 *);\n\tint (*mgmt_tx_cancel_wait)(struct wiphy *, struct wireless_dev *, u64);\n\tint (*set_power_mgmt)(struct wiphy *, struct net_device *, bool, int);\n\tint (*set_cqm_rssi_config)(struct wiphy *, struct net_device *, s32, u32);\n\tint (*set_cqm_rssi_range_config)(struct wiphy *, struct net_device *, s32, s32);\n\tint (*set_cqm_txe_config)(struct wiphy *, struct net_device *, u32, u32, u32);\n\tvoid (*update_mgmt_frame_registrations)(struct wiphy *, struct wireless_dev *, struct mgmt_frame_regs *);\n\tint (*set_antenna)(struct wiphy *, int, u32, u32);\n\tint (*get_antenna)(struct wiphy *, int, u32 *, u32 *);\n\tint (*sched_scan_start)(struct wiphy *, struct net_device *, struct cfg80211_sched_scan_request *);\n\tint (*sched_scan_stop)(struct wiphy *, struct net_device *, u64);\n\tint (*set_rekey_data)(struct wiphy *, struct net_device *, struct cfg80211_gtk_rekey_data *);\n\tint (*tdls_mgmt)(struct wiphy *, struct net_device *, const u8 *, int, u8, u8, u16, u32, bool, const u8 *, size_t);\n\tint (*tdls_oper)(struct wiphy *, struct net_device *, const u8 *, enum nl80211_tdls_operation);\n\tint (*probe_client)(struct wiphy *, struct net_device *, const u8 *, u64 *);\n\tint (*set_noack_map)(struct wiphy *, struct net_device *, u16);\n\tint (*get_channel)(struct wiphy *, struct wireless_dev *, unsigned int, struct cfg80211_chan_def *);\n\tint (*start_p2p_device)(struct wiphy *, struct wireless_dev *);\n\tvoid (*stop_p2p_device)(struct wiphy *, struct wireless_dev *);\n\tint (*set_mac_acl)(struct wiphy *, struct net_device *, const struct cfg80211_acl_data *);\n\tint (*start_radar_detection)(struct wiphy *, struct net_device *, struct cfg80211_chan_def *, u32, int);\n\tvoid (*end_cac)(struct wiphy *, struct net_device *, unsigned int);\n\tint (*update_ft_ies)(struct wiphy *, struct net_device *, struct cfg80211_update_ft_ies_params *);\n\tint (*crit_proto_start)(struct wiphy *, struct wireless_dev *, enum nl80211_crit_proto_id, u16);\n\tvoid (*crit_proto_stop)(struct wiphy *, struct wireless_dev *);\n\tint (*set_coalesce)(struct wiphy *, struct cfg80211_coalesce *);\n\tint (*channel_switch)(struct wiphy *, struct net_device *, struct cfg80211_csa_settings *);\n\tint (*set_qos_map)(struct wiphy *, struct net_device *, struct cfg80211_qos_map *);\n\tint (*set_ap_chanwidth)(struct wiphy *, struct net_device *, unsigned int, struct cfg80211_chan_def *);\n\tint (*add_tx_ts)(struct wiphy *, struct net_device *, u8, const u8 *, u8, u16);\n\tint (*del_tx_ts)(struct wiphy *, struct net_device *, u8, const u8 *);\n\tint (*tdls_channel_switch)(struct wiphy *, struct net_device *, const u8 *, u8, struct cfg80211_chan_def *);\n\tvoid (*tdls_cancel_channel_switch)(struct wiphy *, struct net_device *, const u8 *);\n\tint (*start_nan)(struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *);\n\tvoid (*stop_nan)(struct wiphy *, struct wireless_dev *);\n\tint (*add_nan_func)(struct wiphy *, struct wireless_dev *, struct cfg80211_nan_func *);\n\tvoid (*del_nan_func)(struct wiphy *, struct wireless_dev *, u64);\n\tint (*nan_change_conf)(struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *, u32);\n\tint (*set_multicast_to_unicast)(struct wiphy *, struct net_device *, const bool);\n\tint (*get_txq_stats)(struct wiphy *, struct wireless_dev *, struct cfg80211_txq_stats *);\n\tint (*set_pmk)(struct wiphy *, struct net_device *, const struct cfg80211_pmk_conf *);\n\tint (*del_pmk)(struct wiphy *, struct net_device *, const u8 *);\n\tint (*external_auth)(struct wiphy *, struct net_device *, struct cfg80211_external_auth_params *);\n\tint (*tx_control_port)(struct wiphy *, struct net_device *, const u8 *, size_t, const u8 *, const __be16, const bool, int, u64 *);\n\tint (*get_ftm_responder_stats)(struct wiphy *, struct net_device *, struct cfg80211_ftm_responder_stats *);\n\tint (*start_pmsr)(struct wiphy *, struct wireless_dev *, struct cfg80211_pmsr_request *);\n\tvoid (*abort_pmsr)(struct wiphy *, struct wireless_dev *, struct cfg80211_pmsr_request *);\n\tint (*update_owe_info)(struct wiphy *, struct net_device *, struct cfg80211_update_owe_info *);\n\tint (*probe_mesh_link)(struct wiphy *, struct net_device *, const u8 *, size_t);\n\tint (*set_tid_config)(struct wiphy *, struct net_device *, struct cfg80211_tid_config *);\n\tint (*reset_tid_config)(struct wiphy *, struct net_device *, const u8 *, u8);\n\tint (*set_sar_specs)(struct wiphy *, struct cfg80211_sar_specs *);\n\tint (*color_change)(struct wiphy *, struct net_device *, struct cfg80211_color_change_settings *);\n\tint (*set_fils_aad)(struct wiphy *, struct net_device *, struct cfg80211_fils_aad *);\n\tint (*set_radar_background)(struct wiphy *, struct cfg80211_chan_def *);\n\tint (*add_link_station)(struct wiphy *, struct net_device *, struct link_station_parameters *);\n\tint (*mod_link_station)(struct wiphy *, struct net_device *, struct link_station_parameters *);\n\tint (*del_link_station)(struct wiphy *, struct net_device *, struct link_station_del_parameters *);\n\tint (*set_hw_timestamp)(struct wiphy *, struct net_device *, struct cfg80211_set_hw_timestamp *);\n\tint (*set_ttlm)(struct wiphy *, struct net_device *, struct cfg80211_ttlm_params *);\n\tu32 (*get_radio_mask)(struct wiphy *, struct net_device *);\n\tint (*assoc_ml_reconf)(struct wiphy *, struct net_device *, struct cfg80211_ml_reconf_req *);\n\tint (*set_epcs)(struct wiphy *, struct net_device *, bool);\n};\n\nstruct cfg80211_per_bw_puncturing_values {\n\tu8 len;\n\tconst u16 *valid_values;\n};\n\nstruct cfg80211_pkt_pattern {\n\tconst u8 *mask;\n\tconst u8 *pattern;\n\tint pattern_len;\n\tint pkt_offset;\n};\n\nstruct cfg80211_pmk_conf {\n\tconst u8 *aa;\n\tu8 pmk_len;\n\tconst u8 *pmk;\n\tconst u8 *pmk_r0_name;\n};\n\nstruct cfg80211_pmksa {\n\tconst u8 *bssid;\n\tconst u8 *pmkid;\n\tconst u8 *pmk;\n\tsize_t pmk_len;\n\tconst u8 *ssid;\n\tsize_t ssid_len;\n\tconst u8 *cache_id;\n\tu32 pmk_lifetime;\n\tu8 pmk_reauth_threshold;\n};\n\nstruct cfg80211_pmsr_capabilities {\n\tunsigned int max_peers;\n\tu8 report_ap_tsf: 1;\n\tu8 randomize_mac_addr: 1;\n\tstruct {\n\t\tu32 preambles;\n\t\tu32 bandwidths;\n\t\ts8 max_bursts_exponent;\n\t\tu8 max_ftms_per_burst;\n\t\tu8 supported: 1;\n\t\tu8 asap: 1;\n\t\tu8 non_asap: 1;\n\t\tu8 request_lci: 1;\n\t\tu8 request_civicloc: 1;\n\t\tu8 trigger_based: 1;\n\t\tu8 non_trigger_based: 1;\n\t\tu8 support_6ghz: 1;\n\t\tu8 max_tx_ltf_rep;\n\t\tu8 max_rx_ltf_rep;\n\t\tu8 max_tx_sts;\n\t\tu8 max_rx_sts;\n\t\tu8 max_total_ltf_tx;\n\t\tu8 max_total_ltf_rx;\n\t\tu8 support_rsta: 1;\n\t} ftm;\n};\n\nstruct cfg80211_pmsr_ftm_request_peer {\n\tenum nl80211_preamble preamble;\n\tu16 burst_period;\n\tu8 requested: 1;\n\tu8 asap: 1;\n\tu8 request_lci: 1;\n\tu8 request_civicloc: 1;\n\tu8 trigger_based: 1;\n\tu8 non_trigger_based: 1;\n\tu8 lmr_feedback: 1;\n\tu8 rsta: 1;\n\tu8 num_bursts_exp;\n\tu8 burst_duration;\n\tu8 ftms_per_burst;\n\tu8 ftmr_retries;\n\tu8 bss_color;\n};\n\nstruct rate_info {\n\tu16 flags;\n\tu16 legacy;\n\tu8 mcs;\n\tu8 nss;\n\tu8 bw;\n\tu8 he_gi;\n\tu8 he_dcm;\n\tu8 he_ru_alloc;\n\tu8 n_bonded_ch;\n\tu8 eht_gi;\n\tu8 eht_ru_alloc;\n};\n\nstruct cfg80211_pmsr_ftm_result {\n\tconst u8 *lci;\n\tconst u8 *civicloc;\n\tunsigned int lci_len;\n\tunsigned int civicloc_len;\n\tenum nl80211_peer_measurement_ftm_failure_reasons failure_reason;\n\tu32 num_ftmr_attempts;\n\tu32 num_ftmr_successes;\n\ts16 burst_index;\n\tu8 busy_retry_time;\n\tu8 num_bursts_exp;\n\tu8 burst_duration;\n\tu8 ftms_per_burst;\n\tu16 burst_period;\n\ts32 rssi_avg;\n\ts32 rssi_spread;\n\tstruct rate_info tx_rate;\n\tstruct rate_info rx_rate;\n\ts64 rtt_avg;\n\ts64 rtt_variance;\n\ts64 rtt_spread;\n\ts64 dist_avg;\n\ts64 dist_variance;\n\ts64 dist_spread;\n\tu16 num_ftmr_attempts_valid: 1;\n\tu16 num_ftmr_successes_valid: 1;\n\tu16 rssi_avg_valid: 1;\n\tu16 rssi_spread_valid: 1;\n\tu16 tx_rate_valid: 1;\n\tu16 rx_rate_valid: 1;\n\tu16 rtt_avg_valid: 1;\n\tu16 rtt_variance_valid: 1;\n\tu16 rtt_spread_valid: 1;\n\tu16 dist_avg_valid: 1;\n\tu16 dist_variance_valid: 1;\n\tu16 dist_spread_valid: 1;\n};\n\nstruct cfg80211_pmsr_request_peer {\n\tu8 addr[6];\n\tstruct cfg80211_chan_def chandef;\n\tu8 report_ap_tsf: 1;\n\tstruct cfg80211_pmsr_ftm_request_peer ftm;\n};\n\nstruct cfg80211_pmsr_request {\n\tu64 cookie;\n\tvoid *drv_data;\n\tu32 n_peers;\n\tu32 nl_portid;\n\tu32 timeout;\n\tu8 mac_addr[6];\n\tu8 mac_addr_mask[6];\n\tstruct list_head list;\n\tstruct cfg80211_pmsr_request_peer peers[0];\n};\n\nstruct cfg80211_pmsr_result {\n\tu64 host_time;\n\tu64 ap_tsf;\n\tenum nl80211_peer_measurement_status status;\n\tu8 addr[6];\n\tu8 final: 1;\n\tu8 ap_tsf_valid: 1;\n\tenum nl80211_peer_measurement_type type;\n\tunion {\n\t\tstruct cfg80211_pmsr_ftm_result ftm;\n\t};\n};\n\nstruct cfg80211_qos_map {\n\tu8 num_des;\n\tstruct cfg80211_dscp_exception dscp_exception[21];\n\tstruct cfg80211_dscp_range up[8];\n};\n\nstruct rfkill;\n\nstruct rfkill_ops {\n\tvoid (*poll)(struct rfkill *, void *);\n\tvoid (*query)(struct rfkill *, void *);\n\tint (*set_block)(void *, bool);\n};\n\nstruct wiphy_work;\n\ntypedef void (*wiphy_work_func_t)(struct wiphy *, struct wiphy_work *);\n\nstruct wiphy_work {\n\tstruct list_head entry;\n\twiphy_work_func_t func;\n};\n\nstruct wiphy_nan_capa {\n\tu32 flags;\n\tu8 op_mode;\n\tu8 n_antennas;\n\tu16 max_channel_switch_time;\n\tu8 dev_capabilities;\n};\n\nstruct ieee80211_txrx_stypes;\n\nstruct ieee80211_iface_combination;\n\nstruct wiphy_iftype_akm_suites;\n\nstruct wiphy_wowlan_support;\n\nstruct wiphy_iftype_ext_capab;\n\nstruct ieee80211_supported_band;\n\nstruct regulatory_request;\n\nstruct wiphy_radio_cfg;\n\nstruct ieee80211_regdomain;\n\nstruct wiphy_coalesce_support;\n\nstruct wiphy_vendor_command;\n\nstruct nl80211_vendor_cmd_info;\n\nstruct cfg80211_sar_capa;\n\nstruct wiphy_radio;\n\nstruct wiphy {\n\tstruct mutex mtx;\n\tu8 perm_addr[6];\n\tu8 addr_mask[6];\n\tstruct mac_address *addresses;\n\tconst struct ieee80211_txrx_stypes *mgmt_stypes;\n\tconst struct ieee80211_iface_combination *iface_combinations;\n\tint n_iface_combinations;\n\tu16 software_iftypes;\n\tu16 n_addresses;\n\tu16 interface_modes;\n\tu16 max_acl_mac_addrs;\n\tu32 flags;\n\tu32 regulatory_flags;\n\tu32 features;\n\tu8 ext_features[9];\n\tu32 ap_sme_capa;\n\tenum cfg80211_signal_type signal_type;\n\tint bss_priv_size;\n\tu8 max_scan_ssids;\n\tu8 max_sched_scan_reqs;\n\tu8 max_sched_scan_ssids;\n\tu8 max_match_sets;\n\tu16 max_scan_ie_len;\n\tu16 max_sched_scan_ie_len;\n\tu32 max_sched_scan_plans;\n\tu32 max_sched_scan_plan_interval;\n\tu32 max_sched_scan_plan_iterations;\n\tint n_cipher_suites;\n\tconst u32 *cipher_suites;\n\tint n_akm_suites;\n\tconst u32 *akm_suites;\n\tconst struct wiphy_iftype_akm_suites *iftype_akm_suites;\n\tunsigned int num_iftype_akm_suites;\n\tu8 retry_short;\n\tu8 retry_long;\n\tu32 frag_threshold;\n\tu32 rts_threshold;\n\tu8 coverage_class;\n\tchar fw_version[32];\n\tu32 hw_version;\n\tconst struct wiphy_wowlan_support *wowlan;\n\tstruct cfg80211_wowlan *wowlan_config;\n\tu16 max_remain_on_channel_duration;\n\tu8 max_num_pmkids;\n\tu32 available_antennas_tx;\n\tu32 available_antennas_rx;\n\tu32 probe_resp_offload;\n\tconst u8 *extended_capabilities;\n\tconst u8 *extended_capabilities_mask;\n\tu8 extended_capabilities_len;\n\tconst struct wiphy_iftype_ext_capab *iftype_ext_capab;\n\tunsigned int num_iftype_ext_capab;\n\tconst void *privid;\n\tstruct ieee80211_supported_band *bands[6];\n\tvoid (*reg_notifier)(struct wiphy *, struct regulatory_request *);\n\tstruct wiphy_radio_cfg *radio_cfg;\n\tconst struct ieee80211_regdomain *regd;\n\tstruct device dev;\n\tbool registered;\n\tstruct dentry *debugfsdir;\n\tconst struct ieee80211_ht_cap *ht_capa_mod_mask;\n\tconst struct ieee80211_vht_cap *vht_capa_mod_mask;\n\tstruct list_head wdev_list;\n\tpossible_net_t _net;\n\tconst struct wiphy_coalesce_support *coalesce;\n\tconst struct wiphy_vendor_command *vendor_commands;\n\tconst struct nl80211_vendor_cmd_info *vendor_events;\n\tint n_vendor_commands;\n\tint n_vendor_events;\n\tu16 max_ap_assoc_sta;\n\tu8 max_num_csa_counters;\n\tu32 bss_param_support;\n\tu32 bss_select_support;\n\tu8 nan_supported_bands;\n\tstruct wiphy_nan_capa nan_capa;\n\tu32 txq_limit;\n\tu32 txq_memory_limit;\n\tu32 txq_quantum;\n\tlong unsigned int tx_queue_len;\n\tu8 support_mbssid: 1;\n\tu8 support_only_he_mbssid: 1;\n\tconst struct cfg80211_pmsr_capabilities *pmsr_capa;\n\tstruct {\n\t\tu64 peer;\n\t\tu64 vif;\n\t\tu8 max_retry;\n\t} tid_config_support;\n\tu8 max_data_retry_count;\n\tconst struct cfg80211_sar_capa *sar_capa;\n\tstruct rfkill *rfkill;\n\tu8 mbssid_max_interfaces;\n\tu8 ema_max_profile_periodicity;\n\tu16 max_num_akm_suites;\n\tu16 hw_timestamp_max_peers;\n\tint n_radio;\n\tconst struct wiphy_radio *radio;\n\tlong: 64;\n\tchar priv[0];\n};\n\nstruct cfg80211_scan_request_int;\n\nstruct genl_info;\n\nstruct cfg80211_registered_device {\n\tconst struct cfg80211_ops *ops;\n\tstruct list_head list;\n\tstruct rfkill_ops rfkill_ops;\n\tstruct work_struct rfkill_block;\n\tchar country_ie_alpha2[2];\n\tconst struct ieee80211_regdomain *requested_regd;\n\tenum environment_cap env;\n\tint wiphy_idx;\n\tint devlist_generation;\n\tint wdev_id;\n\tint opencount;\n\twait_queue_head_t dev_wait;\n\tstruct list_head beacon_registrations;\n\tspinlock_t beacon_registrations_lock;\n\tint num_running_ifaces;\n\tint num_running_monitor_ifaces;\n\tu64 cookie_counter;\n\tspinlock_t bss_lock;\n\tstruct list_head bss_list;\n\tstruct rb_root bss_tree;\n\tu32 bss_generation;\n\tu32 bss_entries;\n\tstruct cfg80211_scan_request_int *scan_req;\n\tstruct cfg80211_scan_request_int *int_scan_req;\n\tstruct sk_buff *scan_msg;\n\tstruct list_head sched_scan_req_list;\n\ttime64_t suspend_at;\n\tstruct wiphy_work scan_done_wk;\n\tstruct genl_info *cur_cmd_info;\n\tstruct work_struct conn_work;\n\tstruct work_struct event_work;\n\tstruct delayed_work dfs_update_channels_wk;\n\tstruct wireless_dev *background_radar_wdev;\n\tstruct cfg80211_chan_def background_radar_chandef;\n\tstruct delayed_work background_cac_done_wk;\n\tstruct work_struct background_cac_abort_wk;\n\tu32 crit_proto_nlportid;\n\tstruct cfg80211_coalesce *coalesce;\n\tstruct work_struct destroy_work;\n\tstruct wiphy_work sched_scan_stop_wk;\n\tstruct work_struct sched_scan_res_wk;\n\tstruct cfg80211_chan_def radar_chandef;\n\tstruct work_struct propagate_radar_detect_wk;\n\tstruct cfg80211_chan_def cac_done_chandef;\n\tstruct work_struct propagate_cac_done_wk;\n\tstruct work_struct mgmt_registrations_update_wk;\n\tspinlock_t mgmt_registrations_lock;\n\tstruct work_struct wiphy_work;\n\tstruct list_head wiphy_work_list;\n\tspinlock_t wiphy_work_lock;\n\tbool suspended;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct wiphy wiphy;\n};\n\nstruct cfg80211_rnr_elems {\n\tu8 cnt;\n\tstruct {\n\t\tconst u8 *data;\n\t\tsize_t len;\n\t} elem[0];\n};\n\nstruct cfg80211_rx_assoc_resp_data {\n\tconst u8 *buf;\n\tsize_t len;\n\tconst u8 *req_ies;\n\tsize_t req_ies_len;\n\tint uapsd_queues;\n\tconst u8 *ap_mld_addr;\n\tstruct {\n\t\tu8 addr[6];\n\t\tstruct cfg80211_bss *bss;\n\t\tu16 status;\n\t} links[15];\n};\n\nstruct cfg80211_rx_info {\n\tint freq;\n\tint sig_dbm;\n\tbool have_link_id;\n\tu8 link_id;\n\tconst u8 *buf;\n\tsize_t len;\n\tu32 flags;\n\tu64 rx_tstamp;\n\tu64 ack_tstamp;\n};\n\nstruct cfg80211_sar_freq_ranges;\n\nstruct cfg80211_sar_capa {\n\tenum nl80211_sar_type type;\n\tu32 num_freq_ranges;\n\tconst struct cfg80211_sar_freq_ranges *freq_ranges;\n};\n\nstruct cfg80211_sar_freq_ranges {\n\tu32 start_freq;\n\tu32 end_freq;\n};\n\nstruct cfg80211_sar_sub_specs {\n\ts32 power;\n\tu32 freq_range_index;\n};\n\nstruct cfg80211_sar_specs {\n\tenum nl80211_sar_type type;\n\tu32 num_sub_specs;\n\tstruct cfg80211_sar_sub_specs sub_specs[0];\n};\n\nstruct cfg80211_scan_6ghz_params {\n\tu32 short_ssid;\n\tu32 channel_idx;\n\tu8 bssid[6];\n\tbool unsolicited_probe;\n\tbool short_ssid_valid;\n\tbool psc_no_listen;\n\ts8 psd_20;\n};\n\nstruct cfg80211_scan_info {\n\tu64 scan_start_tsf;\n\tu8 tsf_bssid[6];\n\tbool aborted;\n};\n\nstruct cfg80211_scan_request {\n\tstruct cfg80211_ssid *ssids;\n\tint n_ssids;\n\tu32 n_channels;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu16 duration;\n\tbool duration_mandatory;\n\tu32 flags;\n\tu32 rates[6];\n\tstruct wireless_dev *wdev;\n\tu8 mac_addr[6];\n\tu8 mac_addr_mask[6];\n\tu8 bssid[6];\n\tstruct wiphy *wiphy;\n\tlong unsigned int scan_start;\n\tbool no_cck;\n\tbool scan_6ghz;\n\tbool first_part;\n\tu32 n_6ghz_params;\n\tstruct cfg80211_scan_6ghz_params *scan_6ghz_params;\n\ts8 tsf_report_link_id;\n\tstruct ieee80211_channel *channels[0];\n};\n\nstruct cfg80211_scan_request_int {\n\tstruct cfg80211_scan_info info;\n\tbool notified;\n\tstruct cfg80211_scan_request req;\n};\n\nstruct cfg80211_sched_scan_plan {\n\tu32 interval;\n\tu32 iterations;\n};\n\nstruct cfg80211_sched_scan_request {\n\tu64 reqid;\n\tstruct cfg80211_ssid *ssids;\n\tint n_ssids;\n\tu32 n_channels;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu32 flags;\n\tstruct cfg80211_match_set *match_sets;\n\tint n_match_sets;\n\ts32 min_rssi_thold;\n\tu32 delay;\n\tstruct cfg80211_sched_scan_plan *scan_plans;\n\tint n_scan_plans;\n\tu8 mac_addr[6];\n\tu8 mac_addr_mask[6];\n\tbool relative_rssi_set;\n\ts8 relative_rssi;\n\tstruct cfg80211_bss_select_adjust rssi_adjust;\n\tstruct wiphy *wiphy;\n\tstruct net_device *dev;\n\tlong unsigned int scan_start;\n\tbool report_results;\n\tstruct callback_head callback_head;\n\tu32 owner_nlportid;\n\tbool nl_owner_dead;\n\tstruct list_head list;\n\tstruct ieee80211_channel *channels[0];\n};\n\nstruct cfg80211_set_hw_timestamp {\n\tconst u8 *macaddr;\n\tbool enable;\n};\n\nstruct cfg80211_tid_cfg {\n\tbool config_override;\n\tu8 tids;\n\tu64 mask;\n\tenum nl80211_tid_config noack;\n\tu8 retry_long;\n\tu8 retry_short;\n\tenum nl80211_tid_config ampdu;\n\tenum nl80211_tid_config rtscts;\n\tenum nl80211_tid_config amsdu;\n\tenum nl80211_tx_rate_setting txrate_type;\n\tstruct cfg80211_bitrate_mask txrate_mask;\n};\n\nstruct cfg80211_tid_config {\n\tconst u8 *peer;\n\tu32 n_tid_conf;\n\tstruct cfg80211_tid_cfg tid_conf[0];\n};\n\nstruct cfg80211_txq_stats {\n\tu32 filled;\n\tu32 backlog_bytes;\n\tu32 backlog_packets;\n\tu32 flows;\n\tu32 drops;\n\tu32 ecn_marks;\n\tu32 overlimit;\n\tu32 overmemory;\n\tu32 collisions;\n\tu32 tx_bytes;\n\tu32 tx_packets;\n\tu32 max_flows;\n};\n\nstruct cfg80211_tid_stats {\n\tu32 filled;\n\tu64 rx_msdu;\n\tu64 tx_msdu;\n\tu64 tx_msdu_retries;\n\tu64 tx_msdu_failed;\n\tstruct cfg80211_txq_stats txq_stats;\n};\n\nstruct cfg80211_ttlm_params {\n\tu16 dlink[8];\n\tu16 ulink[8];\n};\n\nstruct cfg80211_tx_status {\n\tu64 cookie;\n\tu64 tx_tstamp;\n\tu64 ack_tstamp;\n\tconst u8 *buf;\n\tsize_t len;\n\tbool ack;\n};\n\nstruct cfg80211_update_ft_ies_params {\n\tu16 md;\n\tconst u8 *ie;\n\tsize_t ie_len;\n};\n\nstruct cfg80211_update_owe_info {\n\tu8 peer[6];\n\tu16 status;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tint assoc_link_id;\n\tu8 peer_mld_addr[6];\n};\n\nstruct cfg80211_wowlan_tcp;\n\nstruct cfg80211_wowlan {\n\tbool any;\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\tstruct cfg80211_pkt_pattern *patterns;\n\tstruct cfg80211_wowlan_tcp *tcp;\n\tint n_patterns;\n\tstruct cfg80211_sched_scan_request *nd_config;\n};\n\nstruct cfg80211_wowlan_nd_match;\n\nstruct cfg80211_wowlan_nd_info {\n\tint n_matches;\n\tstruct cfg80211_wowlan_nd_match *matches[0];\n};\n\nstruct cfg80211_wowlan_nd_match {\n\tstruct cfg80211_ssid ssid;\n\tint n_channels;\n\tu32 channels[0];\n};\n\nstruct nl80211_wowlan_tcp_data_seq {\n\t__u32 start;\n\t__u32 offset;\n\t__u32 len;\n};\n\nstruct nl80211_wowlan_tcp_data_token {\n\t__u32 offset;\n\t__u32 len;\n\t__u8 token_stream[0];\n};\n\nstruct socket;\n\nstruct cfg80211_wowlan_tcp {\n\tstruct socket *sock;\n\t__be32 src;\n\t__be32 dst;\n\tu16 src_port;\n\tu16 dst_port;\n\tu8 dst_mac[6];\n\tint payload_len;\n\tconst u8 *payload;\n\tstruct nl80211_wowlan_tcp_data_seq payload_seq;\n\tu32 data_interval;\n\tu32 wake_len;\n\tconst u8 *wake_data;\n\tconst u8 *wake_mask;\n\tu32 tokens_size;\n\tstruct nl80211_wowlan_tcp_data_token payload_tok;\n};\n\nstruct cfg80211_wowlan_wakeup {\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\tbool packet_80211;\n\tbool tcp_match;\n\tbool tcp_connlost;\n\tbool tcp_nomoretokens;\n\tbool unprot_deauth_disassoc;\n\ts32 pattern_idx;\n\tu32 packet_present_len;\n\tu32 packet_len;\n\tconst void *packet;\n\tstruct cfg80211_wowlan_nd_info *net_detect;\n};\n\nstruct cfs_bandwidth {\n\traw_spinlock_t lock;\n\tktime_t period;\n\tu64 quota;\n\tu64 runtime;\n\tu64 burst;\n\tu64 runtime_snap;\n\ts64 hierarchical_quota;\n\tu8 idle;\n\tu8 period_active;\n\tu8 slack_started;\n\tstruct hrtimer period_timer;\n\tstruct hrtimer slack_timer;\n\tstruct list_head throttled_cfs_rq;\n\tint nr_periods;\n\tint nr_throttled;\n\tint nr_burst;\n\tu64 throttled_time;\n\tu64 burst_time;\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n};\n\nstruct sched_entity;\n\nstruct task_group;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tint runtime_enabled;\n\ts64 runtime_remaining;\n\tu64 throttled_pelt_idle;\n\tu64 throttled_clock;\n\tu64 throttled_clock_pelt;\n\tu64 throttled_clock_pelt_time;\n\tu64 throttled_clock_self;\n\tu64 throttled_clock_self_time;\n\tbool throttled: 1;\n\tbool pelt_clock_throttled: 1;\n\tint throttle_count;\n\tstruct list_head throttled_list;\n\tstruct list_head throttled_csd_list;\n\tstruct list_head throttled_limbo_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cfs_schedulable_data {\n\tstruct task_group *tg;\n\tu64 period;\n\tu64 quota;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 ntime;\n};\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n};\n\nstruct cgroup_bpf {};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[0];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[14];\n\tint nr_dying_subsys[14];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[14];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct cgroup_cls_state {\n\tstruct cgroup_subsys_state css;\n\tu32 classid;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 64;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct ch7017_priv {\n\tu8 dummy;\n};\n\nstruct ch7xxx_did_struct {\n\tu8 did;\n\tchar *name;\n};\n\nstruct ch7xxx_id_struct {\n\tu8 vid;\n\tchar *name;\n};\n\nstruct ch7xxx_priv {\n\tbool quiet;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct linked_page;\n\nstruct chain_allocator {\n\tstruct linked_page *chain;\n\tunsigned int used_space;\n\tgfp_t gfp_mask;\n\tint safe_needed;\n};\n\nstruct e820_entry;\n\nstruct change_member {\n\tstruct e820_entry *entry;\n\tu64 addr;\n};\n\nstruct channel_map_table {\n\tunsigned char map;\n\tint spk_mask;\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct check_loop_arg {\n\tstruct qdisc_walker w;\n\tstruct Qdisc *p;\n\tint depth;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct child_device_config {\n\tu16 handle;\n\tu16 device_type;\n\tunion {\n\t\tu8 device_id[10];\n\t\tstruct {\n\t\t\tu8 i2c_speed;\n\t\t\tu8 dp_onboard_redriver_preemph: 3;\n\t\t\tu8 dp_onboard_redriver_vswing: 3;\n\t\t\tu8 dp_onboard_redriver_present: 1;\n\t\t\tu8 reserved0: 1;\n\t\t\tu8 dp_ondock_redriver_preemph: 3;\n\t\t\tu8 dp_ondock_redriver_vswing: 3;\n\t\t\tu8 dp_ondock_redriver_present: 1;\n\t\t\tu8 reserved1: 1;\n\t\t\tu8 hdmi_level_shifter_value: 5;\n\t\t\tu8 hdmi_max_data_rate: 3;\n\t\t\tu16 dtd_buf_ptr;\n\t\t\tu8 edidless_efp: 1;\n\t\t\tu8 compression_enable: 1;\n\t\t\tu8 compression_method_cps: 1;\n\t\t\tu8 ganged_edp: 1;\n\t\t\tu8 lttpr_non_transparent: 1;\n\t\t\tu8 disable_compression_for_ext_disp: 1;\n\t\t\tu8 reserved2: 2;\n\t\t\tu8 compression_structure_index: 4;\n\t\t\tu8 reserved3: 4;\n\t\t\tu8 hdmi_max_frl_rate: 4;\n\t\t\tu8 hdmi_max_frl_rate_valid: 1;\n\t\t\tu8 reserved4: 3;\n\t\t\tu8 reserved5;\n\t\t};\n\t};\n\tu16 addin_offset;\n\tu8 dvo_port;\n\tu8 i2c_pin;\n\tu8 target_addr;\n\tu8 ddc_pin;\n\tu16 edid_ptr;\n\tu8 dvo_cfg;\n\tunion {\n\t\tstruct {\n\t\t\tu8 dvo2_port;\n\t\t\tu8 i2c2_pin;\n\t\t\tu8 target2_addr;\n\t\t\tu8 ddc2_pin;\n\t\t};\n\t\tstruct {\n\t\t\tu8 efp_routed: 1;\n\t\t\tu8 lane_reversal: 1;\n\t\t\tu8 lspcon: 1;\n\t\t\tu8 iboost: 1;\n\t\t\tu8 hpd_invert: 1;\n\t\t\tu8 use_vbt_vswing: 1;\n\t\t\tu8 dp_max_lane_count: 2;\n\t\t\tu8 hdmi_support: 1;\n\t\t\tu8 dp_support: 1;\n\t\t\tu8 tmds_support: 1;\n\t\t\tu8 support_reserved: 5;\n\t\t\tu8 aux_channel;\n\t\t\tu8 dongle_detect;\n\t\t};\n\t};\n\tu8 pipe_cap: 2;\n\tu8 sdvo_stall: 1;\n\tu8 hpd_status: 2;\n\tu8 integrated_encoder: 1;\n\tu8 capabilities_reserved: 2;\n\tu8 dvo_wiring;\n\tunion {\n\t\tu8 dvo2_wiring;\n\t\tu8 mipi_bridge_type;\n\t};\n\tu16 extended_type;\n\tu8 dvo_function;\n\tu8 dp_usb_type_c: 1;\n\tu8 tbt: 1;\n\tu8 dedicated_external: 1;\n\tu8 dyn_port_over_tc: 1;\n\tu8 dp_port_trace_length: 4;\n\tu8 dp_gpio_index;\n\tu16 dp_gpio_pin_num;\n\tu8 dp_iboost_level: 4;\n\tu8 hdmi_iboost_level: 4;\n\tu8 dp_max_link_rate: 3;\n\tu8 dp_max_link_rate_reserved: 5;\n\tu8 efp_index;\n\tu32 edp_data_rate_override: 12;\n\tu32 edp_data_rate_override_reserved: 20;\n} __attribute__((packed));\n\nstruct iolatency_grp;\n\nstruct child_latency_info {\n\tspinlock_t lock;\n\tu64 last_scale_event;\n\tu64 scale_lat;\n\tu64 nr_samples;\n\tstruct iolatency_grp *scale_grp;\n\tatomic_t scale_cookie;\n};\n\nstruct chipset {\n\tu32 vendor;\n\tu32 device;\n\tu32 class;\n\tu32 class_mask;\n\tu32 flags;\n\tvoid (*f)(int, int, int);\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct cipso_v4_std_map_tbl;\n\nstruct cipso_v4_doi {\n\tu32 doi;\n\tu32 type;\n\tunion {\n\t\tstruct cipso_v4_std_map_tbl *std;\n\t} map;\n\tu8 tags[5];\n\trefcount_t refcount;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct cipso_v4_map_cache_bkt {\n\tspinlock_t lock;\n\tu32 size;\n\tstruct list_head list;\n};\n\nstruct cipso_v4_map_cache_entry {\n\tu32 hash;\n\tunsigned char *key;\n\tsize_t key_len;\n\tstruct netlbl_lsm_cache *lsm_data;\n\tu32 activity;\n\tstruct list_head list;\n};\n\nstruct cipso_v4_std_map_tbl {\n\tstruct {\n\t\tu32 *cipso;\n\t\tu32 *local;\n\t\tu32 cipso_size;\n\t\tu32 local_size;\n\t} lvl;\n\tstruct {\n\t\tu32 *cipso;\n\t\tu32 *local;\n\t\tu32 cipso_size;\n\t\tu32 local_size;\n\t} cat;\n};\n\nstruct cis_cache_entry {\n\tstruct list_head node;\n\tunsigned int addr;\n\tunsigned int len;\n\tunsigned int attr;\n\tunsigned char cache[0];\n};\n\nstruct cistpl_device_t {\n\tu_char ndev;\n\tstruct {\n\t\tu_char type;\n\t\tu_char wp;\n\t\tu_int speed;\n\t\tu_int size;\n\t} dev[4];\n};\n\ntypedef struct cistpl_device_t cistpl_device_t;\n\nstruct cistpl_checksum_t {\n\tu_short addr;\n\tu_short len;\n\tu_char sum;\n};\n\ntypedef struct cistpl_checksum_t cistpl_checksum_t;\n\nstruct cistpl_longlink_t {\n\tu_int addr;\n};\n\ntypedef struct cistpl_longlink_t cistpl_longlink_t;\n\nstruct cistpl_longlink_mfc_t {\n\tu_char nfn;\n\tstruct {\n\t\tu_char space;\n\t\tu_int addr;\n\t} fn[8];\n};\n\ntypedef struct cistpl_longlink_mfc_t cistpl_longlink_mfc_t;\n\nstruct cistpl_vers_1_t {\n\tu_char major;\n\tu_char minor;\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_vers_1_t cistpl_vers_1_t;\n\nstruct cistpl_altstr_t {\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_altstr_t cistpl_altstr_t;\n\nstruct cistpl_jedec_t {\n\tu_char nid;\n\tstruct {\n\t\tu_char mfr;\n\t\tu_char info;\n\t} id[4];\n};\n\ntypedef struct cistpl_jedec_t cistpl_jedec_t;\n\nstruct cistpl_manfid_t {\n\tu_short manf;\n\tu_short card;\n};\n\ntypedef struct cistpl_manfid_t cistpl_manfid_t;\n\nstruct cistpl_funcid_t {\n\tu_char func;\n\tu_char sysinit;\n};\n\ntypedef struct cistpl_funcid_t cistpl_funcid_t;\n\nstruct cistpl_funce_t {\n\tu_char type;\n\tu_char data[0];\n};\n\ntypedef struct cistpl_funce_t cistpl_funce_t;\n\nstruct cistpl_bar_t {\n\tu_char attr;\n\tu_int size;\n};\n\ntypedef struct cistpl_bar_t cistpl_bar_t;\n\nstruct cistpl_config_t {\n\tu_char last_idx;\n\tu_int base;\n\tu_int rmask[4];\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_config_t cistpl_config_t;\n\nstruct cistpl_power_t {\n\tu_char present;\n\tu_char flags;\n\tu_int param[7];\n};\n\ntypedef struct cistpl_power_t cistpl_power_t;\n\nstruct cistpl_timing_t {\n\tu_int wait;\n\tu_int waitscale;\n\tu_int ready;\n\tu_int rdyscale;\n\tu_int reserved;\n\tu_int rsvscale;\n};\n\ntypedef struct cistpl_timing_t cistpl_timing_t;\n\nstruct cistpl_io_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int base;\n\t\tu_int len;\n\t} win[16];\n};\n\ntypedef struct cistpl_io_t cistpl_io_t;\n\nstruct cistpl_irq_t {\n\tu_int IRQInfo1;\n\tu_int IRQInfo2;\n};\n\ntypedef struct cistpl_irq_t cistpl_irq_t;\n\nstruct cistpl_mem_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int len;\n\t\tu_int card_addr;\n\t\tu_int host_addr;\n\t} win[8];\n};\n\ntypedef struct cistpl_mem_t cistpl_mem_t;\n\nstruct cistpl_cftable_entry_t {\n\tu_char index;\n\tu_short flags;\n\tu_char interface;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tcistpl_timing_t timing;\n\tcistpl_io_t io;\n\tcistpl_irq_t irq;\n\tcistpl_mem_t mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_t cistpl_cftable_entry_t;\n\nstruct cistpl_cftable_entry_cb_t {\n\tu_char index;\n\tu_int flags;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tu_char io;\n\tcistpl_irq_t irq;\n\tu_char mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_cb_t cistpl_cftable_entry_cb_t;\n\nstruct cistpl_device_geo_t {\n\tu_char ngeo;\n\tstruct {\n\t\tu_char buswidth;\n\t\tu_int erase_block;\n\t\tu_int read_block;\n\t\tu_int write_block;\n\t\tu_int partition;\n\t\tu_int interleave;\n\t} geo[4];\n};\n\ntypedef struct cistpl_device_geo_t cistpl_device_geo_t;\n\nstruct cistpl_vers_2_t {\n\tu_char vers;\n\tu_char comply;\n\tu_short dindex;\n\tu_char vspec8;\n\tu_char vspec9;\n\tu_char nhdr;\n\tu_char vendor;\n\tu_char info;\n\tchar str[244];\n};\n\ntypedef struct cistpl_vers_2_t cistpl_vers_2_t;\n\nstruct cistpl_org_t {\n\tu_char data_org;\n\tchar desc[30];\n};\n\ntypedef struct cistpl_org_t cistpl_org_t;\n\nstruct cistpl_format_t {\n\tu_char type;\n\tu_char edc;\n\tu_int offset;\n\tu_int length;\n};\n\ntypedef struct cistpl_format_t cistpl_format_t;\n\nunion cisparse_t {\n\tcistpl_device_t device;\n\tcistpl_checksum_t checksum;\n\tcistpl_longlink_t longlink;\n\tcistpl_longlink_mfc_t longlink_mfc;\n\tcistpl_vers_1_t version_1;\n\tcistpl_altstr_t altstr;\n\tcistpl_jedec_t jedec;\n\tcistpl_manfid_t manfid;\n\tcistpl_funcid_t funcid;\n\tcistpl_funce_t funce;\n\tcistpl_bar_t bar;\n\tcistpl_config_t config;\n\tcistpl_cftable_entry_t cftable_entry;\n\tcistpl_cftable_entry_cb_t cftable_entry_cb;\n\tcistpl_device_geo_t device_geo;\n\tcistpl_vers_2_t vers_2;\n\tcistpl_org_t org;\n\tcistpl_format_t format;\n};\n\ntypedef union cisparse_t cisparse_t;\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct hashtab_node;\n\nstruct hashtab {\n\tstruct hashtab_node **htable;\n\tu32 size;\n\tu32 nel;\n};\n\nstruct symtab {\n\tstruct hashtab table;\n\tu32 nprim;\n};\n\nstruct common_datum;\n\nstruct constraint_node;\n\nstruct class_datum {\n\tu32 value;\n\tchar *comkey;\n\tstruct common_datum *comdatum;\n\tstruct symtab permissions;\n\tstruct constraint_node *constraints;\n\tstruct constraint_node *validatetrans;\n\tchar default_user;\n\tchar default_role;\n\tchar default_type;\n\tchar default_range;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_info {\n\tint class;\n\tchar *class_name;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n};\n\nstruct i915_sw_fence;\n\ntypedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *, enum i915_sw_fence_notify);\n\nstruct i915_sw_fence {\n\twait_queue_head_t wait;\n\ti915_sw_fence_notify_t fn;\n\tatomic_t pending;\n\tint error;\n};\n\nstruct i915_sw_dma_fence_cb {\n\tstruct dma_fence_cb base;\n\tstruct i915_sw_fence *fence;\n};\n\nstruct dma_fence_work_ops;\n\nstruct dma_fence_work {\n\tstruct dma_fence dma;\n\tspinlock_t lock;\n\tstruct i915_sw_fence chain;\n\tstruct i915_sw_dma_fence_cb cb;\n\tstruct work_struct work;\n\tconst struct dma_fence_work_ops *ops;\n};\n\nstruct drm_i915_gem_object;\n\nstruct clflush {\n\tstruct dma_fence_work base;\n\tstruct drm_i915_gem_object *obj;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct list_head wd_list;\n\tu64 cs_last;\n\tu64 wd_last;\n\tstruct module *owner;\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct dm_table;\n\nstruct dm_io;\n\nstruct clone_info {\n\tstruct dm_table *map;\n\tstruct bio *bio;\n\tstruct dm_io *io;\n\tsector_t sector;\n\tunsigned int sector_count;\n\tbool is_abnormal_io: 1;\n\tbool submit_as_polled: 1;\n};\n\nstruct tc_action;\n\nstruct tcf_exts_miss_cookie_node;\n\nstruct tcf_exts {\n\t__u32 type;\n\tint nr_actions;\n\tstruct tc_action **actions;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct tcf_exts_miss_cookie_node *miss_cookie_node;\n\tint action;\n\tint police;\n};\n\nstruct tcf_ematch_tree_hdr {\n\t__u16 nmatches;\n\t__u16 progid;\n};\n\nstruct tcf_ematch;\n\nstruct tcf_ematch_tree {\n\tstruct tcf_ematch_tree_hdr hdr;\n\tstruct tcf_ematch *matches;\n};\n\nstruct tcf_proto;\n\nstruct cls_cgroup_head {\n\tu32 handle;\n\tstruct tcf_exts exts;\n\tstruct tcf_ematch_tree ematches;\n\tstruct tcf_proto *tp;\n\tstruct rcu_work rwork;\n};\n\nstruct cmac_tfm_ctx {\n\tstruct crypto_cipher *child;\n\t__be64 consts[0];\n};\n\nstruct drm_i915_cmd_descriptor;\n\nstruct cmd_node {\n\tconst struct drm_i915_cmd_descriptor *desc;\n\tstruct hlist_node node;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmos_rtc;\n\nstruct rtc_time;\n\nstruct cmos_read_alarm_callback_param {\n\tstruct cmos_rtc *cmos;\n\tstruct rtc_time *time;\n\tunsigned char rtc_control;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtc_device;\n\nstruct cmos_rtc {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tint irq;\n\tstruct resource *iomem;\n\ttime64_t alarm_expires;\n\tvoid (*wake_on)(struct device *);\n\tvoid (*wake_off)(struct device *);\n\tu8 enabled_wake;\n\tu8 suspend_ctrl;\n\tu8 day_alrm;\n\tu8 mon_alrm;\n\tu8 century;\n\tstruct rtc_wkalrm saved_wkalrm;\n};\n\nstruct cmos_rtc_board_info {\n\tvoid (*wake_on)(struct device *);\n\tvoid (*wake_off)(struct device *);\n\tu32 flags;\n\tint address_space;\n\tu8 rtc_day_alarm;\n\tu8 rtc_mon_alarm;\n\tu8 rtc_century;\n};\n\nstruct cmos_set_alarm_callback_param {\n\tstruct cmos_rtc *cmos;\n\tunsigned char mon;\n\tunsigned char mday;\n\tunsigned char hrs;\n\tunsigned char min;\n\tunsigned char sec;\n\tstruct rtc_wkalrm *t;\n};\n\nstruct cmp_data {\n\tstruct task_struct *thr;\n\tstruct crypto_acomp *cc;\n\tstruct acomp_req *cr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct cn_callback_id {\n\tunsigned char name[32];\n\tstruct cb_id id;\n};\n\nstruct cn_queue_dev;\n\nstruct cn_msg;\n\nstruct netlink_skb_parms;\n\nstruct cn_callback_entry {\n\tstruct list_head callback_entry;\n\trefcount_t refcnt;\n\tstruct cn_queue_dev *pdev;\n\tstruct cn_callback_id id;\n\tvoid (*callback)(struct cn_msg *, struct netlink_skb_parms *);\n\tu32 seq;\n\tu32 group;\n};\n\nstruct cn_dev {\n\tstruct cb_id id;\n\tu32 seq;\n\tu32 groups;\n\tstruct sock *nls;\n\tstruct cn_queue_dev *cbdev;\n};\n\nstruct cn_msg {\n\tstruct cb_id id;\n\t__u32 seq;\n\t__u32 ack;\n\t__u16 len;\n\t__u16 flags;\n\t__u8 data[0];\n};\n\nstruct cn_queue_dev {\n\tatomic_t refcnt;\n\tunsigned char name[32];\n\tstruct list_head queue_list;\n\tspinlock_t queue_lock;\n\tstruct sock *nls;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct codel_params {\n\tcodel_time_t target;\n\tcodel_time_t ce_threshold;\n\tcodel_time_t interval;\n\tu32 mtu;\n\tbool ecn;\n\tu8 ce_threshold_selector;\n\tu8 ce_threshold_mask;\n};\n\nstruct codel_stats {\n\tu32 maxpacket;\n\tu32 drop_count;\n\tu32 drop_len;\n\tu32 ecn_mark;\n\tu32 ce_mark;\n};\n\nstruct codel_vars {\n\tu32 count;\n\tu32 lastcount;\n\tbool dropping;\n\tu16 rec_inv_sqrt;\n\tcodel_time_t first_above_time;\n\tcodel_time_t drop_next;\n\tcodel_time_t ldelay;\n};\n\nstruct element;\n\nstruct colocated_ap_data {\n\tconst struct element *ssid_elem;\n\tstruct list_head ap_list;\n\tu32 s_ssid_tmp;\n\tint n_coloc;\n};\n\nstruct color_conversion {\n\tu16 ry;\n\tu16 gy;\n\tu16 by;\n\tu16 ay;\n\tu16 ru;\n\tu16 gu;\n\tu16 bu;\n\tu16 au;\n\tu16 rv;\n\tu16 gv;\n\tu16 bv;\n\tu16 av;\n};\n\nstruct comm_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tchar comm[16];\n};\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n};\n\nstruct lsm_network_audit;\n\nstruct lsm_ioctlop_audit;\n\nstruct lsm_ibpkey_audit;\n\nstruct lsm_ibendport_audit;\n\nstruct selinux_audit_data;\n\nstruct common_audit_data {\n\tchar type;\n\tunion {\n\t\tstruct path path;\n\t\tstruct dentry *dentry;\n\t\tstruct inode *inode;\n\t\tstruct lsm_network_audit *net;\n\t\tint cap;\n\t\tint ipc_id;\n\t\tstruct task_struct *tsk;\n\t\tstruct {\n\t\t\tkey_serial_t key;\n\t\t\tchar *key_desc;\n\t\t} key_struct;\n\t\tchar *kmod_name;\n\t\tstruct lsm_ioctlop_audit *op;\n\t\tstruct file *file;\n\t\tstruct lsm_ibpkey_audit *ibpkey;\n\t\tstruct lsm_ibendport_audit *ibendport;\n\t\tint reason;\n\t\tconst char *anonclass;\n\t\tu16 nlmsg_type;\n\t} u;\n\tunion {\n\t\tstruct selinux_audit_data *selinux_audit_data;\n\t};\n};\n\nstruct common_datum {\n\tu32 value;\n\tstruct symtab permissions;\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[11];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_blk_user_trace_setup {\n\tchar name[32];\n\tu16 act_mask;\n\tint: 0;\n\tu32 buf_size;\n\tu32 buf_nr;\n\tcompat_u64 start_lba;\n\tcompat_u64 end_lba;\n\tu32 pid;\n} __attribute__((packed));\n\nstruct compat_blkpg_ioctl_arg {\n\tcompat_int_t op;\n\tcompat_int_t flags;\n\tcompat_int_t datalen;\n\tcompat_caddr_t data;\n};\n\nstruct compat_cdrom_generic_command {\n\tunsigned char cmd[12];\n\tcompat_caddr_t buffer;\n\tcompat_uint_t buflen;\n\tcompat_int_t stat;\n\tcompat_caddr_t sense;\n\tunsigned char data_direction;\n\tunsigned char pad[3];\n\tcompat_int_t quiet;\n\tcompat_int_t timeout;\n\tcompat_caddr_t unused;\n};\n\nstruct compat_cdrom_read_audio {\n\tunion cdrom_addr addr;\n\tu8 addr_format;\n\tcompat_int_t nframes;\n\tcompat_caddr_t buf;\n};\n\nstruct compat_cmsghdr {\n\tcompat_size_t cmsg_len;\n\tcompat_int_t cmsg_level;\n\tcompat_int_t cmsg_type;\n};\n\nstruct compat_console_font_op {\n\tcompat_uint_t op;\n\tcompat_uint_t flags;\n\tcompat_uint_t width;\n\tcompat_uint_t height;\n\tcompat_uint_t charcount;\n\tcompat_caddr_t data;\n};\n\nstruct compat_dirent {\n\tu32 d_ino;\n\tcompat_off_t d_off;\n\tu16 d_reclen;\n\tchar d_name[256];\n};\n\nstruct compat_elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tcompat_ulong_t pr_flag;\n\t__compat_uid_t pr_uid;\n\t__compat_gid_t pr_gid;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct compat_elf_siginfo {\n\tcompat_int_t si_signo;\n\tcompat_int_t si_code;\n\tcompat_int_t si_errno;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct compat_elf_prstatus_common {\n\tstruct compat_elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tcompat_ulong_t pr_sigpend;\n\tcompat_ulong_t pr_sighold;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tstruct old_timeval32 pr_utime;\n\tstruct old_timeval32 pr_stime;\n\tstruct old_timeval32 pr_cutime;\n\tstruct old_timeval32 pr_cstime;\n};\n\nstruct user_regs_struct {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bp;\n\tlong unsigned int bx;\n\tlong unsigned int r11;\n\tlong unsigned int r10;\n\tlong unsigned int r9;\n\tlong unsigned int r8;\n\tlong unsigned int ax;\n\tlong unsigned int cx;\n\tlong unsigned int dx;\n\tlong unsigned int si;\n\tlong unsigned int di;\n\tlong unsigned int orig_ax;\n\tlong unsigned int ip;\n\tlong unsigned int cs;\n\tlong unsigned int flags;\n\tlong unsigned int sp;\n\tlong unsigned int ss;\n\tlong unsigned int fs_base;\n\tlong unsigned int gs_base;\n\tlong unsigned int ds;\n\tlong unsigned int es;\n\tlong unsigned int fs;\n\tlong unsigned int gs;\n};\n\ntypedef struct user_regs_struct compat_elf_gregset_t;\n\nstruct compat_elf_prstatus {\n\tstruct compat_elf_prstatus_common common;\n\tcompat_elf_gregset_t pr_reg;\n\tcompat_int_t pr_fpvalid;\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct compat_ethtool_rx_flow_spec {\n\tu32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\tcompat_u64 ring_cookie;\n\tu32 location;\n} __attribute__((packed));\n\nstruct compat_ethtool_rxnfc {\n\tu32 cmd;\n\tu32 flow_type;\n\tcompat_u64 data;\n\tstruct compat_ethtool_rx_flow_spec fs;\n\tu32 rule_cnt;\n\tu32 rule_locs[0];\n} __attribute__((packed));\n\nstruct compat_ext4_new_group_input {\n\tu32 group;\n\tcompat_u64 block_bitmap;\n\tcompat_u64 inode_bitmap;\n\tcompat_u64 inode_table;\n\tu32 blocks_count;\n\tu16 reserved_blocks;\n\tu16 unused;\n} __attribute__((packed));\n\nstruct compat_flock {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_off_t l_start;\n\tcompat_off_t l_len;\n\tcompat_pid_t l_pid;\n};\n\nstruct compat_flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_loff_t l_start;\n\tcompat_loff_t l_len;\n\tcompat_pid_t l_pid;\n} __attribute__((packed));\n\nstruct compat_fs_qfilestat {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 qfs_nblks;\n\tcompat_uint_t qfs_nextents;\n} __attribute__((packed));\n\nstruct compat_fs_quota_stat {\n\t__s8 qs_version;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tlong: 0;\n\tstruct compat_fs_qfilestat qs_uquota;\n\tstruct compat_fs_qfilestat qs_gquota;\n\tcompat_uint_t qs_incoredqs;\n\tcompat_int_t qs_btimelimit;\n\tcompat_int_t qs_itimelimit;\n\tcompat_int_t qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct compat_linux_dirent;\n\nstruct compat_getdents_callback {\n\tstruct dir_context ctx;\n\tstruct compat_linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t} __attribute__((packed));\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n} __attribute__((packed));\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n} __attribute__((packed));\n\nstruct compat_hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tu32 start;\n};\n\nstruct compat_hpet_info {\n\tcompat_ulong_t hi_ireqfreq;\n\tcompat_ulong_t hi_flags;\n\tshort unsigned int hi_hpet;\n\tshort unsigned int hi_timer;\n};\n\nstruct compat_if_dqblk {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 dqb_bsoftlimit;\n\tcompat_u64 dqb_curspace;\n\tcompat_u64 dqb_ihardlimit;\n\tcompat_u64 dqb_isoftlimit;\n\tcompat_u64 dqb_curinodes;\n\tcompat_u64 dqb_btime;\n\tcompat_u64 dqb_itime;\n\tcompat_uint_t dqb_valid;\n} __attribute__((packed));\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\tu32 rtmsg_type;\n\tu16 rtmsg_dst_len;\n\tu16 rtmsg_src_len;\n\tu32 rtmsg_metric;\n\tu32 rtmsg_info;\n\tu32 rtmsg_flags;\n\ts32 rtmsg_ifindex;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_ipc64_perm {\n\tcompat_key_t key;\n\t__compat_uid32_t uid;\n\t__compat_gid32_t gid;\n\t__compat_uid32_t cuid;\n\t__compat_gid32_t cgid;\n\tcompat_mode_t mode;\n\tunsigned char __pad1[2];\n\tcompat_ushort_t seq;\n\tcompat_ushort_t __pad2;\n\tcompat_ulong_t unused1;\n\tcompat_ulong_t unused2;\n};\n\nstruct compat_ipc_kludge {\n\tcompat_uptr_t msgp;\n\tcompat_long_t msgtyp;\n};\n\nstruct compat_ipc_perm {\n\tkey_t key;\n\t__compat_uid_t uid;\n\t__compat_gid_t gid;\n\t__compat_uid_t cuid;\n\t__compat_gid_t cgid;\n\tcompat_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct compat_kexec_segment {\n\tcompat_uptr_t buf;\n\tcompat_size_t bufsz;\n\tcompat_ulong_t mem;\n\tcompat_size_t memsz;\n};\n\nstruct compat_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct compat_loop_info {\n\tcompat_int_t lo_number;\n\tcompat_dev_t lo_device;\n\tcompat_ulong_t lo_inode;\n\tcompat_dev_t lo_rdevice;\n\tcompat_int_t lo_offset;\n\tcompat_int_t lo_encrypt_type;\n\tcompat_int_t lo_encrypt_key_size;\n\tcompat_int_t lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tcompat_ulong_t lo_init[2];\n\tchar reserved[4];\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_mq_attr {\n\tcompat_long_t mq_flags;\n\tcompat_long_t mq_maxmsg;\n\tcompat_long_t mq_msgsize;\n\tcompat_long_t mq_curmsgs;\n\tcompat_long_t __reserved[4];\n};\n\nstruct compat_msgbuf {\n\tcompat_long_t mtype;\n\tchar mtext[0];\n};\n\nstruct compat_msqid64_ds {\n\tstruct compat_ipc64_perm msg_perm;\n\tcompat_ulong_t msg_stime;\n\tcompat_ulong_t msg_stime_high;\n\tcompat_ulong_t msg_rtime;\n\tcompat_ulong_t msg_rtime_high;\n\tcompat_ulong_t msg_ctime;\n\tcompat_ulong_t msg_ctime_high;\n\tcompat_ulong_t msg_cbytes;\n\tcompat_ulong_t msg_qnum;\n\tcompat_ulong_t msg_qbytes;\n\tcompat_pid_t msg_lspid;\n\tcompat_pid_t msg_lrpid;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_msqid_ds {\n\tstruct compat_ipc_perm msg_perm;\n\tcompat_uptr_t msg_first;\n\tcompat_uptr_t msg_last;\n\told_time32_t msg_stime;\n\told_time32_t msg_rtime;\n\told_time32_t msg_ctime;\n\tcompat_ulong_t msg_lcbytes;\n\tcompat_ulong_t msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\tcompat_ipc_pid_t msg_lspid;\n\tcompat_ipc_pid_t msg_lrpid;\n};\n\nstruct compat_nfs_string {\n\tcompat_uint_t len;\n\tcompat_uptr_t data;\n};\n\nstruct compat_nfs4_mount_data_v1 {\n\tcompat_int_t version;\n\tcompat_int_t flags;\n\tcompat_int_t rsize;\n\tcompat_int_t wsize;\n\tcompat_int_t timeo;\n\tcompat_int_t retrans;\n\tcompat_int_t acregmin;\n\tcompat_int_t acregmax;\n\tcompat_int_t acdirmin;\n\tcompat_int_t acdirmax;\n\tstruct compat_nfs_string client_addr;\n\tstruct compat_nfs_string mnt_path;\n\tstruct compat_nfs_string hostname;\n\tcompat_uint_t host_addrlen;\n\tcompat_uptr_t host_addr;\n\tcompat_int_t proto;\n\tcompat_int_t auth_flavourlen;\n\tcompat_uptr_t auth_flavours;\n};\n\nstruct compat_old_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct compat_old_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_old_sigset_t sa_mask;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n};\n\nstruct compat_readdir_callback {\n\tstruct dir_context ctx;\n\tstruct compat_old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct compat_resume_swap_area {\n\tcompat_loff_t offset;\n\tu32 dev;\n} __attribute__((packed));\n\nstruct compat_rlimit {\n\tcompat_ulong_t rlim_cur;\n\tcompat_ulong_t rlim_max;\n};\n\nstruct compat_robust_list {\n\tcompat_uptr_t next;\n};\n\nstruct compat_robust_list_head {\n\tstruct compat_robust_list list;\n\tcompat_long_t futex_offset;\n\tcompat_uptr_t list_op_pending;\n};\n\nstruct compat_rtentry {\n\tu32 rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tu32 rt_pad3;\n\tunsigned char rt_tos;\n\tunsigned char rt_class;\n\tshort int rt_pad4;\n\tshort int rt_metric;\n\tcompat_uptr_t rt_dev;\n\tu32 rt_mtu;\n\tu32 rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct compat_rusage {\n\tstruct old_timeval32 ru_utime;\n\tstruct old_timeval32 ru_stime;\n\tcompat_long_t ru_maxrss;\n\tcompat_long_t ru_ixrss;\n\tcompat_long_t ru_idrss;\n\tcompat_long_t ru_isrss;\n\tcompat_long_t ru_minflt;\n\tcompat_long_t ru_majflt;\n\tcompat_long_t ru_nswap;\n\tcompat_long_t ru_inblock;\n\tcompat_long_t ru_oublock;\n\tcompat_long_t ru_msgsnd;\n\tcompat_long_t ru_msgrcv;\n\tcompat_long_t ru_nsignals;\n\tcompat_long_t ru_nvcsw;\n\tcompat_long_t ru_nivcsw;\n};\n\nstruct compat_sel_arg_struct {\n\tcompat_ulong_t n;\n\tcompat_uptr_t inp;\n\tcompat_uptr_t outp;\n\tcompat_uptr_t exp;\n\tcompat_uptr_t tvp;\n};\n\nstruct compat_semid64_ds {\n\tstruct compat_ipc64_perm sem_perm;\n\tcompat_ulong_t sem_otime;\n\tcompat_ulong_t sem_otime_high;\n\tcompat_ulong_t sem_ctime;\n\tcompat_ulong_t sem_ctime_high;\n\tcompat_ulong_t sem_nsems;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_semid_ds {\n\tstruct compat_ipc_perm sem_perm;\n\told_time32_t sem_otime;\n\told_time32_t sem_ctime;\n\tcompat_uptr_t sem_base;\n\tcompat_uptr_t sem_pending;\n\tcompat_uptr_t sem_pending_last;\n\tcompat_uptr_t undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct compat_sg_io_hdr {\n\tcompat_int_t interface_id;\n\tcompat_int_t dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tcompat_uint_t dxfer_len;\n\tcompat_uint_t dxferp;\n\tcompat_uptr_t cmdp;\n\tcompat_uptr_t sbp;\n\tcompat_uint_t timeout;\n\tcompat_uint_t flags;\n\tcompat_int_t pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tcompat_int_t resid;\n\tcompat_uint_t duration;\n\tcompat_uint_t info;\n};\n\nstruct compat_sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\nstruct compat_shm_info {\n\tcompat_int_t used_ids;\n\tcompat_ulong_t shm_tot;\n\tcompat_ulong_t shm_rss;\n\tcompat_ulong_t shm_swp;\n\tcompat_ulong_t swap_attempts;\n\tcompat_ulong_t swap_successes;\n};\n\nstruct compat_shmid64_ds {\n\tstruct compat_ipc64_perm shm_perm;\n\tcompat_size_t shm_segsz;\n\tcompat_ulong_t shm_atime;\n\tcompat_ulong_t shm_atime_high;\n\tcompat_ulong_t shm_dtime;\n\tcompat_ulong_t shm_dtime_high;\n\tcompat_ulong_t shm_ctime;\n\tcompat_ulong_t shm_ctime_high;\n\tcompat_pid_t shm_cpid;\n\tcompat_pid_t shm_lpid;\n\tcompat_ulong_t shm_nattch;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_shmid_ds {\n\tstruct compat_ipc_perm shm_perm;\n\tint shm_segsz;\n\told_time32_t shm_atime;\n\told_time32_t shm_dtime;\n\told_time32_t shm_ctime;\n\tcompat_ipc_pid_t shm_cpid;\n\tcompat_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tcompat_uptr_t shm_unused2;\n\tcompat_uptr_t shm_unused3;\n};\n\nstruct compat_shminfo64 {\n\tcompat_ulong_t shmmax;\n\tcompat_ulong_t shmmin;\n\tcompat_ulong_t shmmni;\n\tcompat_ulong_t shmseg;\n\tcompat_ulong_t shmall;\n\tcompat_ulong_t __unused1;\n\tcompat_ulong_t __unused2;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n\tcompat_sigset_t sa_mask;\n};\n\nstruct compat_sigaltstack {\n\tcompat_uptr_t ss_sp;\n\tint ss_flags;\n\tcompat_size_t ss_size;\n};\n\ntypedef struct compat_sigaltstack compat_stack_t;\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_sigevent {\n\tcompat_sigval_t sigev_value;\n\tcompat_int_t sigev_signo;\n\tcompat_int_t sigev_notify;\n\tunion {\n\t\tcompat_int_t _pad[13];\n\t\tcompat_int_t _tid;\n\t\tstruct {\n\t\t\tcompat_uptr_t _function;\n\t\t\tcompat_uptr_t _attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\ntypedef struct compat_siginfo compat_siginfo_t;\n\nstruct compat_sigset_argpack {\n\tcompat_uptr_t p;\n\tcompat_size_t size;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct compat_sioc_sg_req {\n\tstruct in_addr src;\n\tstruct in_addr grp;\n\tcompat_ulong_t pktcnt;\n\tcompat_ulong_t bytecnt;\n\tcompat_ulong_t wrong_if;\n};\n\nstruct compat_sioc_vif_req {\n\tvifi_t vifi;\n\tcompat_ulong_t icount;\n\tcompat_ulong_t ocount;\n\tcompat_ulong_t ibytes;\n\tcompat_ulong_t obytes;\n};\n\nstruct compat_snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct compat_stat {\n\tu32 st_dev;\n\tcompat_ino_t st_ino;\n\tcompat_mode_t st_mode;\n\tcompat_nlink_t st_nlink;\n\t__compat_uid_t st_uid;\n\t__compat_gid_t st_gid;\n\tu32 st_rdev;\n\tu32 st_size;\n\tu32 st_blksize;\n\tu32 st_blocks;\n\tu32 st_atime;\n\tu32 st_atime_nsec;\n\tu32 st_mtime;\n\tu32 st_mtime_nsec;\n\tu32 st_ctime;\n\tu32 st_ctime_nsec;\n\tu32 __unused4;\n\tu32 __unused5;\n};\n\nstruct compat_statfs {\n\tint f_type;\n\tint f_bsize;\n\tint f_blocks;\n\tint f_bfree;\n\tint f_bavail;\n\tint f_files;\n\tint f_ffree;\n\tcompat_fsid_t f_fsid;\n\tint f_namelen;\n\tint f_frsize;\n\tint f_flags;\n\tint f_spare[4];\n};\n\nstruct compat_statfs64 {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_frsize;\n\t__u32 f_flags;\n\t__u32 f_spare[4];\n} __attribute__((packed));\n\nstruct compat_sysinfo {\n\ts32 uptime;\n\tu32 loads[3];\n\tu32 totalram;\n\tu32 freeram;\n\tu32 sharedram;\n\tu32 bufferram;\n\tu32 totalswap;\n\tu32 freeswap;\n\tu16 procs;\n\tu16 pad;\n\tu32 totalhigh;\n\tu32 freehigh;\n\tu32 mem_unit;\n\tchar _f[8];\n};\n\nstruct compat_tms {\n\tcompat_clock_t tms_utime;\n\tcompat_clock_t tms_stime;\n\tcompat_clock_t tms_cutime;\n\tcompat_clock_t tms_cstime;\n};\n\nstruct compat_unimapdesc {\n\tshort unsigned int entry_ct;\n\tcompat_caddr_t entries;\n};\n\nstruct compat_ustat {\n\tcompat_daddr_t f_tfree;\n\tcompat_ino_t f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\nstruct compound_hdr {\n\tint32_t status;\n\tuint32_t nops;\n\t__be32 *nops_p;\n\tuint32_t taglen;\n\tchar *tag;\n\tuint32_t replen;\n\tu32 minorversion;\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct cond_av_list {\n\tstruct avtab_node **nodes;\n\tu32 len;\n};\n\nstruct cond_bool_datum {\n\tu32 value;\n\tint state;\n};\n\nstruct cond_expr_node;\n\nstruct cond_expr {\n\tstruct cond_expr_node *nodes;\n\tu32 len;\n};\n\nstruct cond_expr_node {\n\tu32 expr_type;\n\tu32 boolean;\n};\n\nstruct policydb;\n\nstruct cond_insertf_data {\n\tstruct policydb *p;\n\tstruct avtab_node **dst;\n\tstruct cond_av_list *other;\n};\n\nstruct cond_node {\n\tint cur_state;\n\tstruct cond_expr expr;\n\tstruct cond_av_list true_list;\n\tstruct cond_av_list false_list;\n};\n\nstruct dmi_system_id;\n\nstruct snd_soc_acpi_codecs;\n\nstruct config_entry {\n\tu32 flags;\n\tu16 device;\n\tu8 acpi_hid[16];\n\tconst struct dmi_system_id *dmi_table;\n\tconst struct snd_soc_acpi_codecs *codec_hid;\n};\n\nstruct deflate_state;\n\ntypedef struct deflate_state deflate_state;\n\ntypedef block_state (*compress_func)(deflate_state *, int);\n\nstruct config_s {\n\tush good_length;\n\tush max_lazy;\n\tush nice_length;\n\tush max_chain;\n\tcompress_func func;\n};\n\ntypedef struct config_s config;\n\nstruct config_t {\n\tstruct kref ref;\n\tunsigned int state;\n\tstruct resource io[2];\n\tstruct resource mem[4];\n};\n\ntypedef struct config_t config_t;\n\nstruct connect_timeout_data {\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct conntrack_gc_work {\n\tstruct delayed_work dwork;\n\tu32 next_bucket;\n\tu32 avg_timeout;\n\tu32 count;\n\tu32 start_time;\n\tbool exiting;\n\tbool early_drop;\n};\n\nstruct console;\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct;\n\nstruct console___2 {\n\tstruct list_head list;\n\tstruct hvc_struct *hvc;\n\tstruct winsize ws;\n\tu32 vtermno;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct ebitmap_node;\n\nstruct ebitmap {\n\tstruct ebitmap_node *node;\n\tu32 highbit;\n};\n\nstruct type_set;\n\nstruct constraint_expr {\n\tu32 expr_type;\n\tu32 attr;\n\tu32 op;\n\tstruct ebitmap names;\n\tstruct type_set *type_names;\n\tstruct constraint_expr *next;\n};\n\nstruct constraint_node {\n\tu32 permissions;\n\tstruct constraint_expr *expr;\n\tstruct constraint_node *next;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct microcode_amd;\n\nstruct cont_desc {\n\tstruct microcode_amd *mc;\n\tu32 psize;\n\tu8 *data;\n\tsize_t size;\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n};\n\nstruct mls_level {\n\tu32 sens;\n\tstruct ebitmap cat;\n};\n\nstruct mls_range {\n\tstruct mls_level level[2];\n};\n\nstruct context___2 {\n\tu32 user;\n\tu32 role;\n\tu32 type;\n\tu32 len;\n\tstruct mls_range range;\n\tchar *str;\n};\n\nstruct context_entry {\n\tu64 lo;\n\tu64 hi;\n};\n\nstruct guc_update_context_policy_header {\n\tu32 action;\n\tu32 ctx_id;\n};\n\nstruct guc_klv_generic_dw_t {\n\tu32 kl;\n\tu32 value;\n};\n\nstruct guc_update_context_policy {\n\tstruct guc_update_context_policy_header header;\n\tstruct guc_klv_generic_dw_t klv[5];\n};\n\nstruct context_policy {\n\tu32 count;\n\tstruct guc_update_context_policy h2g;\n};\n\nstruct context_tracking {\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct virtio_net_ctrl_hdr {\n\t__u8 class;\n\t__u8 cmd;\n};\n\nstruct control_buf {\n\tstruct virtio_net_ctrl_hdr hdr;\n\tvirtio_net_ctrl_ack status;\n};\n\nstruct convert_context_args {\n\tstruct policydb *oldp;\n\tstruct policydb *newp;\n};\n\nstruct cooling_spec {\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tunsigned int weight;\n};\n\nstruct copy_subpage_arg {\n\tstruct folio *dst;\n\tstruct folio *src;\n\tstruct vm_area_struct *vma;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_text {\n\tlong unsigned int base;\n\tlong unsigned int end;\n\tconst char *name;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct pgprot {\n\tpgprotval_t pgprot;\n};\n\ntypedef struct pgprot pgprot_t;\n\nstruct cpa_data {\n\tlong unsigned int *vaddr;\n\tpgd_t *pgd;\n\tpgprot_t mask_set;\n\tpgprot_t mask_clr;\n\tlong unsigned int numpages;\n\tlong unsigned int curpage;\n\tlong unsigned int pfn;\n\tunsigned int flags;\n\tunsigned int force_split: 1;\n\tunsigned int force_static_prot: 1;\n\tunsigned int force_flush_all: 1;\n\tstruct page **pages;\n};\n\nstruct cparams {\n\tu16 i;\n\tu16 t;\n\tu16 m;\n\tu16 c;\n};\n\nstruct cpc_reg {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct cpc_register_resource {\n\tacpi_object_type type;\n\tu64 *sys_mem_vaddr;\n\tunion {\n\t\tstruct cpc_reg reg;\n\t\tu64 int_value;\n\t} cpc_entry;\n};\n\nstruct cpc_desc {\n\tint num_entries;\n\tint version;\n\tint cpu_id;\n\tint write_cmd_status;\n\tint write_cmd_id;\n\traw_spinlock_t rmw_lock;\n\tstruct cpc_register_resource cpc_regs[21];\n\tstruct acpi_psd_package domain_info;\n\tstruct kobject kobj;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cppc_perf_caps {\n\tu32 guaranteed_perf;\n\tu32 highest_perf;\n\tu32 nominal_perf;\n\tu32 lowest_perf;\n\tu32 lowest_nonlinear_perf;\n\tu32 lowest_freq;\n\tu32 nominal_freq;\n};\n\nstruct cppc_perf_ctrls {\n\tu32 max_perf;\n\tu32 min_perf;\n\tu32 desired_perf;\n\tu32 energy_perf;\n\tbool auto_sel;\n};\n\nstruct cppc_perf_fb_ctrs {\n\tu64 reference;\n\tu64 delivered;\n\tu64 reference_perf;\n\tu64 wraparound_time;\n};\n\nstruct cppc_cpudata {\n\tstruct cppc_perf_caps perf_caps;\n\tstruct cppc_perf_ctrls perf_ctrls;\n\tstruct cppc_perf_fb_ctrs perf_fb_ctrs;\n\tunsigned int shared_type;\n\tcpumask_var_t shared_cpu_map;\n};\n\nstruct pcc_mbox_chan;\n\nstruct cppc_pcc_data {\n\tstruct pcc_mbox_chan *pcc_channel;\n\tbool pcc_channel_acquired;\n\tunsigned int deadline_us;\n\tunsigned int pcc_mpar;\n\tunsigned int pcc_mrtt;\n\tunsigned int pcc_nominal;\n\tbool pending_pcc_write_cmd;\n\tbool platform_owns_pcc;\n\tunsigned int pcc_write_cnt;\n\tstruct rw_semaphore pcc_lock;\n\twait_queue_head_t pcc_write_wait_q;\n\tktime_t last_cmd_cmpl_time;\n\tktime_t last_mpar_reset;\n\tint mpar_count;\n\tint refcount;\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct update_util_data {\n\tvoid (*func)(struct update_util_data *, u64, unsigned int);\n};\n\nstruct policy_dbs_info;\n\nstruct cpu_dbs_info {\n\tu64 prev_cpu_idle;\n\tu64 prev_update_time;\n\tu64 prev_cpu_nice;\n\tunsigned int prev_load;\n\tstruct update_util_data update_util;\n\tstruct policy_dbs_info *policy_dbs;\n};\n\nstruct cpuinfo_x86;\n\nstruct cpu_dev {\n\tconst char *c_vendor;\n\tconst char *c_ident[2];\n\tvoid (*c_early_init)(struct cpuinfo_x86 *);\n\tvoid (*c_bsp_init)(struct cpuinfo_x86 *);\n\tvoid (*c_init)(struct cpuinfo_x86 *);\n\tvoid (*c_identify)(struct cpuinfo_x86 *);\n\tvoid (*c_detect_tlb)(struct cpuinfo_x86 *);\n\tint c_x86_vendor;\n};\n\nstruct entry_stack {\n\tchar stack[4096];\n};\n\nstruct entry_stack_page {\n\tstruct entry_stack stack;\n};\n\nstruct x86_hw_tss {\n\tu32 reserved1;\n\tu64 sp0;\n\tu64 sp1;\n\tu64 sp2;\n\tu64 reserved2;\n\tu64 ist[7];\n\tu32 reserved3;\n\tu32 reserved4;\n\tu16 reserved5;\n\tu16 io_bitmap_base;\n} __attribute__((packed));\n\nstruct x86_io_bitmap {\n\tu64 prev_sequence;\n\tunsigned int prev_max;\n\tlong unsigned int bitmap[1025];\n\tlong unsigned int mapall[1025];\n};\n\nstruct tss_struct {\n\tstruct x86_hw_tss x86_tss;\n\tstruct x86_io_bitmap io_bitmap;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct debug_store_buffers {\n\tchar bts_buffer[65536];\n\tchar pebs_buffer[65536];\n};\n\nstruct cpu_entry_area {\n\tchar gdt[4096];\n\tstruct entry_stack_page entry_stack_page;\n\tstruct tss_struct tss;\n\tstruct cea_exception_stacks estacks;\n\tstruct debug_store cpu_debug_store;\n\tstruct debug_store_buffers cpu_debug_buffers;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 spec: 2;\n\t__u64 new_type: 4;\n\t__u64 priv: 3;\n\t__u64 reserved: 31;\n};\n\nstruct perf_branch_stack {\n\tu64 nr;\n\tu64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct perf_guest_switch_msr {\n\tunsigned int msr;\n\tu64 host;\n\tu64 guest;\n};\n\nstruct er_account;\n\nstruct intel_shared_regs;\n\nstruct intel_excl_cntrs;\n\nstruct cpu_hw_events {\n\tstruct perf_event *events[64];\n\tlong unsigned int active_mask[1];\n\tlong unsigned int dirty[1];\n\tint enabled;\n\tint n_events;\n\tint n_added;\n\tint n_txn;\n\tint n_txn_pair;\n\tint n_txn_metric;\n\tint assign[64];\n\tu64 tags[64];\n\tstruct perf_event *event_list[64];\n\tstruct event_constraint *event_constraint[64];\n\tint n_excl;\n\tint n_late_setup;\n\tunsigned int txn_flags;\n\tint is_fake;\n\tstruct debug_store *ds;\n\tvoid *ds_bts_vaddr;\n\tvoid *pebs_vaddr;\n\tu64 pebs_enabled;\n\tint n_pebs;\n\tint n_large_pebs;\n\tint n_pebs_via_pt;\n\tint pebs_output;\n\tu64 pebs_data_cfg;\n\tu64 active_pebs_data_cfg;\n\tint pebs_record_size;\n\tu64 fixed_ctrl_val;\n\tu64 active_fixed_ctrl_val;\n\tu64 acr_cfg_b[64];\n\tu64 acr_cfg_c[64];\n\tu64 cfg_c_val[64];\n\tint lbr_users;\n\tint lbr_pebs_users;\n\tstruct perf_branch_stack lbr_stack;\n\tstruct perf_branch_entry lbr_entries[32];\n\tu64 lbr_counters[32];\n\tunion {\n\t\tstruct er_account *lbr_sel;\n\t\tstruct er_account *lbr_ctl;\n\t};\n\tu64 br_sel;\n\tvoid *last_task_ctx;\n\tint last_log_id;\n\tint lbr_select;\n\tvoid *lbr_xsave;\n\tu64 intel_ctrl_guest_mask;\n\tu64 intel_ctrl_host_mask;\n\tstruct perf_guest_switch_msr guest_switch_msrs[64];\n\tu64 intel_cp_status;\n\tstruct intel_shared_regs *shared_regs;\n\tstruct event_constraint *constraint_list;\n\tstruct intel_excl_cntrs *excl_cntrs;\n\tint excl_thread_id;\n\tu64 tfa_shadow;\n\tint n_metric;\n\tstruct amd_nb *amd_nb;\n\tint brs_active;\n\tu64 perf_ctr_virt_mask;\n\tint n_pair;\n\tvoid *kfree_on_online[2];\n\tstruct pmu *pmu;\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_perf_ibs {\n\tstruct perf_event *event;\n\tlong unsigned int state[1];\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_signature {\n\tunsigned int sig;\n\tunsigned int pf;\n\tunsigned int rev;\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct kernel_cpustat;\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tu64 *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct pstate_data {\n\tint current_pstate;\n\tint min_pstate;\n\tint max_pstate;\n\tint max_pstate_physical;\n\tint perf_ctl_scaling;\n\tint scaling;\n\tint turbo_pstate;\n\tunsigned int min_freq;\n\tunsigned int max_freq;\n\tunsigned int turbo_freq;\n};\n\nstruct vid_data {\n\tint min;\n\tint max;\n\tint turbo;\n\tint32_t ratio;\n};\n\nstruct sample {\n\tint32_t core_avg_perf;\n\tint32_t busy_scaled;\n\tu64 aperf;\n\tu64 mperf;\n\tu64 tsc;\n\tu64 time;\n};\n\nstruct cpudata {\n\tint cpu;\n\tunsigned int policy;\n\tstruct update_util_data update_util;\n\tbool update_util_set;\n\tstruct pstate_data pstate;\n\tstruct vid_data vid;\n\tu64 last_update;\n\tu64 last_sample_time;\n\tu64 aperf_mperf_shift;\n\tu64 prev_aperf;\n\tu64 prev_mperf;\n\tu64 prev_tsc;\n\tstruct sample sample;\n\tint32_t min_perf_ratio;\n\tint32_t max_perf_ratio;\n\tstruct acpi_processor_performance acpi_perf_data;\n\tbool valid_pss_table;\n\tunsigned int iowait_boost;\n\ts16 epp_powersave;\n\ts16 epp_policy;\n\ts16 epp_default;\n\ts16 epp_cached;\n\tu64 hwp_req_cached;\n\tu64 hwp_cap_cached;\n\tu64 last_io_update;\n\tunsigned int capacity_perf;\n\tunsigned int sched_flags;\n\tu32 hwp_boost_min;\n\tbool suspended;\n\tstruct delayed_work hwp_notify_work;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_policy;\n\nstruct cpufreq_policy_data;\n\nstruct freq_attr;\n\nstruct cpufreq_driver {\n\tchar name[16];\n\tu16 flags;\n\tvoid *driver_data;\n\tint (*init)(struct cpufreq_policy *);\n\tint (*verify)(struct cpufreq_policy_data *);\n\tint (*setpolicy)(struct cpufreq_policy *);\n\tint (*target)(struct cpufreq_policy *, unsigned int, unsigned int);\n\tint (*target_index)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*fast_switch)(struct cpufreq_policy *, unsigned int);\n\tvoid (*adjust_perf)(unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get)(unsigned int);\n\tvoid (*update_limits)(struct cpufreq_policy *);\n\tint (*bios_limit)(int, unsigned int *);\n\tint (*online)(struct cpufreq_policy *);\n\tint (*offline)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n\tvoid (*ready)(struct cpufreq_policy *);\n\tstruct freq_attr **attr;\n\tbool boost_enabled;\n\tint (*set_boost)(struct cpufreq_policy *, int);\n\tvoid (*register_em)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_freqs {\n\tstruct cpufreq_policy *policy;\n\tunsigned int old;\n\tunsigned int new;\n\tu8 flags;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tstruct list_head governor_list;\n\tstruct module *owner;\n\tu8 flags;\n};\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_read_t;\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_write_t;\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct cpufreq_stats;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tbool strict_target;\n\tbool efficiencies_available;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tbool boost_enabled;\n\tbool boost_supported;\n\tunsigned int cached_target_freq;\n\tunsigned int cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpufreq_policy_data {\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tstruct cpufreq_frequency_table *freq_table;\n\tunsigned int cpu;\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nunion cpuid10_eax {\n\tstruct {\n\t\tunsigned int version_id: 8;\n\t\tunsigned int num_counters: 8;\n\t\tunsigned int bit_width: 8;\n\t\tunsigned int mask_length: 8;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid10_ebx {\n\tstruct {\n\t\tunsigned int no_unhalted_core_cycles: 1;\n\t\tunsigned int no_instructions_retired: 1;\n\t\tunsigned int no_unhalted_reference_cycles: 1;\n\t\tunsigned int no_llc_reference: 1;\n\t\tunsigned int no_llc_misses: 1;\n\t\tunsigned int no_branch_instruction_retired: 1;\n\t\tunsigned int no_branch_misses_retired: 1;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid10_edx {\n\tstruct {\n\t\tunsigned int num_counters_fixed: 5;\n\t\tunsigned int bit_width_fixed: 8;\n\t\tunsigned int reserved1: 2;\n\t\tunsigned int anythread_deprecated: 1;\n\t\tunsigned int reserved2: 16;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid28_eax {\n\tstruct {\n\t\tunsigned int lbr_depth_mask: 8;\n\t\tunsigned int reserved: 22;\n\t\tunsigned int lbr_deep_c_reset: 1;\n\t\tunsigned int lbr_lip: 1;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid28_ebx {\n\tstruct {\n\t\tunsigned int lbr_cpl: 1;\n\t\tunsigned int lbr_filter: 1;\n\t\tunsigned int lbr_call_stack: 1;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid28_ecx {\n\tstruct {\n\t\tunsigned int lbr_mispred: 1;\n\t\tunsigned int lbr_timed_lbr: 1;\n\t\tunsigned int lbr_br_type: 1;\n\t\tunsigned int reserved: 13;\n\t\tunsigned int lbr_counters: 4;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid35_eax {\n\tstruct {\n\t\tunsigned int leaf0: 1;\n\t\tunsigned int cntr_subleaf: 1;\n\t\tunsigned int acr_subleaf: 1;\n\t\tunsigned int events_subleaf: 1;\n\t\tunsigned int pebs_caps_subleaf: 1;\n\t\tunsigned int pebs_cnts_subleaf: 1;\n\t\tunsigned int reserved: 26;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid35_ebx {\n\tstruct {\n\t\tunsigned int umask2: 1;\n\t\tunsigned int eq: 1;\n\t\tunsigned int rdpmc_user_disable: 1;\n\t\tunsigned int reserved: 29;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid_0x80000022_ebx {\n\tstruct {\n\t\tunsigned int num_core_pmc: 4;\n\t\tunsigned int lbr_v2_stack_sz: 6;\n\t\tunsigned int num_df_pmc: 6;\n\t\tunsigned int num_umc_pmc: 6;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid_1_eax {\n\tstruct {\n\t\t__u32 stepping: 4;\n\t\t__u32 model: 4;\n\t\t__u32 family: 4;\n\t\t__u32 __reserved0: 4;\n\t\t__u32 ext_model: 4;\n\t\t__u32 ext_fam: 8;\n\t\t__u32 __reserved1: 4;\n\t};\n\t__u32 full;\n};\n\nstruct cpuid_bit {\n\tu16 feature;\n\tu8 reg;\n\tu8 bit;\n\tu32 level;\n\tu32 sub_leaf;\n};\n\nstruct cpuid_dep {\n\tunsigned int feature;\n\tunsigned int depends;\n};\n\nstruct cpuid_dependent_feature {\n\tu32 feature;\n\tu32 level;\n};\n\nstruct cpuid_regs {\n\tu32 eax;\n\tu32 ebx;\n\tu32 ecx;\n\tu32 edx;\n};\n\nstruct cpuid_regs_done {\n\tstruct cpuid_regs regs;\n\tstruct completion done;\n};\n\nstruct cpuidle_device;\n\nstruct cpuidle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_device *, char *);\n\tssize_t (*store)(struct cpuidle_device *, const char *, size_t);\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct cpuidle_device_kobj {\n\tstruct cpuidle_device *dev;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct cpuidle_governor {\n\tchar name[16];\n\tstruct list_head governor_list;\n\tunsigned int rating;\n\tint (*enable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tvoid (*disable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tint (*select)(struct cpuidle_driver *, struct cpuidle_device *, bool *);\n\tvoid (*reflect)(struct cpuidle_device *, int);\n};\n\nstruct cpuidle_state_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_state *, struct cpuidle_state_usage *, char *);\n\tssize_t (*store)(struct cpuidle_state *, struct cpuidle_state_usage *, const char *, size_t);\n};\n\nstruct cpuidle_state_kobj {\n\tstruct cpuidle_state *state;\n\tstruct cpuidle_state_usage *state_usage;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n\tstruct cpuidle_device *device;\n};\n\nstruct cpuinfo_topology {\n\tu32 apicid;\n\tu32 initial_apicid;\n\tu32 pkg_id;\n\tu32 die_id;\n\tu32 cu_id;\n\tu32 core_id;\n\tu32 logical_pkg_id;\n\tu32 logical_die_id;\n\tu32 logical_core_id;\n\tu32 amd_node_id;\n\tu32 llc_id;\n\tu32 l2c_id;\n\tunion {\n\t\tu32 cpu_type;\n\t\tstruct {\n\t\t\tu32 intel_native_model_id: 24;\n\t\t\tu32 intel_type: 8;\n\t\t};\n\t\tstruct {\n\t\t\tu32 amd_num_processors: 16;\n\t\t\tu32 amd_power_eff_ranking: 8;\n\t\t\tu32 amd_native_model_id: 4;\n\t\t\tu32 amd_type: 4;\n\t\t};\n\t};\n};\n\nstruct cpuinfo_x86 {\n\tunion {\n\t\tstruct {\n\t\t\t__u8 x86_model;\n\t\t\t__u8 x86;\n\t\t\t__u8 x86_vendor;\n\t\t\t__u8 x86_reserved;\n\t\t};\n\t\t__u32 x86_vfm;\n\t};\n\t__u8 x86_stepping;\n\tint x86_tlbsize;\n\t__u32 vmx_capability[5];\n\t__u8 x86_virt_bits;\n\t__u8 x86_phys_bits;\n\t__u32 extended_cpuid_level;\n\tint cpuid_level;\n\tunion {\n\t\t__u32 x86_capability[24];\n\t\tlong unsigned int x86_capability_alignment;\n\t};\n\tchar x86_vendor_id[16];\n\tchar x86_model_id[64];\n\tstruct cpuinfo_topology topo;\n\tunsigned int x86_cache_size;\n\tint x86_cache_alignment;\n\tint x86_cache_max_rmid;\n\tint x86_cache_occ_scale;\n\tint x86_cache_mbm_width_offset;\n\tint x86_power;\n\tlong unsigned int loops_per_jiffy;\n\tu64 ppin;\n\tu16 x86_clflush_size;\n\tu16 booted_cores;\n\tu16 cpu_index;\n\tbool smt_active;\n\tu32 microcode;\n\tu8 x86_cache_bits;\n\tunsigned int initialized: 1;\n};\n\nstruct cpumap {\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int managed_allocated;\n\tbool initialized;\n\tbool online;\n\tlong unsigned int *managed_map;\n\tlong unsigned int alloc_map[0];\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct crash_mem {\n\tunsigned int max_nr_ranges;\n\tunsigned int nr_ranges;\n\tstruct range ranges[0];\n};\n\nstruct crc_data {\n\tstruct task_struct *thr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tunsigned int run_threads;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tu32 *crc32;\n\tsize_t **unc_len;\n\tunsigned char **unc;\n};\n\nstruct drm_i915_private;\n\nstruct intel_memory_region;\n\nstruct create_ext {\n\tstruct drm_i915_private *i915;\n\tstruct intel_memory_region *placements[7];\n\tunsigned int n_placements;\n\tunsigned int placement_mask;\n\tlong unsigned int flags;\n\tunsigned int pat_index;\n};\n\nstruct i915_gem_proto_context;\n\nstruct drm_i915_file_private;\n\nstruct create_ext___2 {\n\tstruct i915_gem_proto_context *pc;\n\tstruct drm_i915_file_private *fpriv;\n};\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tvoid *security;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct cred_security_struct {\n\tu32 osid;\n\tu32 sid;\n\tu32 exec_sid;\n\tu32 create_sid;\n\tu32 keycreate_sid;\n\tu32 sockcreate_sid;\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct crs_csi2 {\n\tstruct list_head entry;\n\tacpi_handle handle;\n\tstruct acpi_device_software_nodes *swnodes;\n\tstruct list_head connections;\n\tu32 port_count;\n};\n\nstruct crs_csi2_connection {\n\tstruct list_head entry;\n\tstruct acpi_resource_csi2_serialbus csi2_data;\n\tacpi_handle remote_handle;\n\tchar remote_name[0];\n};\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_acomp_stream {\n\tspinlock_t lock;\n\tvoid *ctx;\n};\n\nstruct crypto_acomp_streams {\n\tvoid * (*alloc_ctx)(void);\n\tvoid (*free_ctx)(void *);\n\tstruct crypto_acomp_stream *streams;\n\tstruct work_struct stream_work;\n\tcpumask_t stream_want;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_aes_ctx {\n\tu32 key_enc[60];\n\tu32 key_dec[60];\n\tu32 key_length;\n};\n\nstruct crypto_ahash {\n\tbool using_shash;\n\tunsigned int statesize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_akcipher_sync_data {\n\tstruct crypto_akcipher *tfm;\n\tconst void *src;\n\tvoid *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct akcipher_request *req;\n\tstruct crypto_wait cwait;\n\tstruct scatterlist sg;\n\tu8 *buf;\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_skcipher;\n\nstruct crypto_authenc_ctx {\n\tstruct crypto_ahash *auth;\n\tstruct crypto_skcipher *enc;\n};\n\nstruct crypto_authenc_esn_ctx {\n\tunsigned int reqoff;\n\tstruct crypto_ahash *auth;\n\tstruct crypto_skcipher *enc;\n};\n\nstruct crypto_authenc_key_param {\n\t__be32 enckeylen;\n};\n\nstruct crypto_authenc_keys {\n\tconst u8 *authkey;\n\tconst u8 *enckey;\n\tunsigned int authkeylen;\n\tunsigned int enckeylen;\n};\n\nstruct crypto_ccm_ctx {\n\tstruct crypto_ahash *mac;\n\tstruct crypto_skcipher *ctr;\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_ccm_req_priv_ctx {\n\tu8 odata[16];\n\tu8 idata[16];\n\tu8 auth_tag[16];\n\tu32 flags;\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tunion {\n\t\tstruct ahash_request ahreq;\n\t\tstruct skcipher_request skreq;\n\t};\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_gcm_ctx {\n\tstruct crypto_skcipher *ctr;\n\tstruct crypto_ahash *ghash;\n};\n\nstruct crypto_gcm_ghash_ctx {\n\tunsigned int cryptlen;\n\tstruct scatterlist *src;\n\tint (*complete)(struct aead_request *, u32);\n};\n\nstruct crypto_gcm_req_priv_ctx {\n\tu8 iv[16];\n\tu8 auth_tag[16];\n\tu8 iauth_tag[16];\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct scatterlist sg;\n\tstruct crypto_gcm_ghash_ctx ghash_ctx;\n\tunion {\n\t\tstruct ahash_request ahreq;\n\t\tstruct skcipher_request skreq;\n\t} u;\n};\n\nstruct crypto_hash_walk {\n\tconst char *data;\n\tunsigned int offset;\n\tunsigned int flags;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n};\n\nstruct crypto_kpp {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_kpp_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n\tbool test_started;\n};\n\nstruct crypto_lskcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_lskcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct crypto_rfc3686_ctx {\n\tstruct crypto_skcipher *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc3686_req_ctx {\n\tu8 iv[16];\n\tstruct skcipher_request subreq;\n};\n\nstruct crypto_rfc4106_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4106_req_ctx {\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rfc4309_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[3];\n};\n\nstruct crypto_rfc4309_req_ctx {\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rfc4543_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4543_instance_ctx {\n\tstruct crypto_aead_spawn aead;\n};\n\nstruct crypto_rfc4543_req_ctx {\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sig {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sig_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sync_aead {\n\tstruct crypto_aead base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct hlist_head dead;\n\tstruct module *module;\n\tstruct work_struct free_work;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tvoid (*destroy)(struct crypto_alg *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n\tunsigned int algsize;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_alg data;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct csi2_resources_walk_data {\n\tacpi_handle handle;\n\tstruct list_head connections;\n};\n\nstruct csr {\n\tstruct {\n\t\tu8 status;\n\t\tu8 stat_ack;\n\t\tu8 cmd_lo;\n\t\tu8 cmd_hi;\n\t\tu32 gen_ptr;\n\t} scb;\n\tu32 port;\n\tu16 flash_ctrl;\n\tu8 eeprom_ctrl_lo;\n\tu8 eeprom_ctrl_hi;\n\tu32 mdi_ctrl;\n\tu32 rx_dma_count;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[14];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[14];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct cstate_entry {\n\tstruct {\n\t\tunsigned int eax;\n\t\tunsigned int ecx;\n\t} states[8];\n};\n\nstruct cstate_model {\n\tlong unsigned int core_events;\n\tlong unsigned int pkg_events;\n\tlong unsigned int module_events;\n\tlong unsigned int quirks;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ct_data_s {\n\tunion {\n\t\tush freq;\n\t\tush code;\n\t} fc;\n\tunion {\n\t\tush dad;\n\t\tush len;\n\t} dl;\n};\n\ntypedef struct ct_data_s ct_data;\n\nstruct ct_incoming_msg {\n\tstruct list_head link;\n\tu32 size;\n\tu32 msg[0];\n};\n\nstruct ct_request {\n\tstruct list_head link;\n\tu32 fence;\n\tu32 status;\n\tu32 response_len;\n\tu32 *response_buf;\n};\n\nstruct ctl_table;\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nunion nf_inet_addr {\n\t__u32 all[4];\n\t__be32 ip;\n\t__be32 ip6[4];\n\tstruct in_addr in;\n\tstruct in6_addr in6;\n};\n\nunion nf_conntrack_man_proto {\n\t__be16 all;\n\tstruct {\n\t\t__be16 port;\n\t} tcp;\n\tstruct {\n\t\t__be16 port;\n\t} udp;\n\tstruct {\n\t\t__be16 id;\n\t} icmp;\n\tstruct {\n\t\t__be16 port;\n\t} dccp;\n\tstruct {\n\t\t__be16 port;\n\t} sctp;\n\tstruct {\n\t\t__be16 key;\n\t} gre;\n};\n\nstruct nf_conntrack_man {\n\tunion nf_inet_addr u3;\n\tunion nf_conntrack_man_proto u;\n\tu_int16_t l3num;\n};\n\nstruct nf_conntrack_tuple {\n\tstruct nf_conntrack_man src;\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion {\n\t\t\t__be16 all;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} tcp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} udp;\n\t\t\tstruct {\n\t\t\t\tu_int8_t type;\n\t\t\t\tu_int8_t code;\n\t\t\t} icmp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} dccp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} sctp;\n\t\t\tstruct {\n\t\t\t\t__be16 key;\n\t\t\t} gre;\n\t\t} u;\n\t\tu_int8_t protonum;\n\t\tstruct {} __nfct_hash_offsetend;\n\t\tu_int8_t dir;\n\t} dst;\n};\n\nstruct nf_conntrack_zone {\n\tu16 id;\n\tu8 flags;\n\tu8 dir;\n};\n\nstruct ctnetlink_filter_u32 {\n\tu32 val;\n\tu32 mask;\n};\n\nstruct ctnetlink_filter {\n\tu8 family;\n\tbool zone_filter;\n\tu_int32_t orig_flags;\n\tu_int32_t reply_flags;\n\tstruct nf_conntrack_tuple orig;\n\tstruct nf_conntrack_tuple reply;\n\tstruct nf_conntrack_zone zone;\n\tstruct ctnetlink_filter_u32 mark;\n\tstruct ctnetlink_filter_u32 status;\n};\n\nstruct ctnetlink_list_dump_ctx {\n\tlong unsigned int last_id;\n\tunsigned int cpu;\n\tbool done;\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct cvt_timing {\n\tu8 code[3];\n};\n\nstruct cxsr_latency {\n\tbool is_desktop: 1;\n\tbool is_ddr3: 1;\n\tu16 fsb_freq;\n\tu16 mem_freq;\n\tu16 display_sr;\n\tu16 display_hpll_disable;\n\tu16 cursor_sr;\n\tu16 cursor_hpll_disable;\n};\n\nstruct cyc2ns_data {\n\tu32 cyc2ns_mul;\n\tu32 cyc2ns_shift;\n\tu64 cyc2ns_offset;\n};\n\nstruct cyc2ns {\n\tstruct cyc2ns_data data[2];\n\tseqcount_latch_t seq;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct dax_device;\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct dax_operations {\n\tlong int (*direct_access)(struct dax_device *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\tint (*zero_page_range)(struct dax_device *, long unsigned int, size_t);\n\tsize_t (*recovery_write)(struct dax_device *, long unsigned int, void *, size_t, struct iov_iter *);\n};\n\nstruct xhci_dbc;\n\nstruct dbc_driver {\n\tint (*configure)(struct xhci_dbc *);\n\tvoid (*disconnect)(struct xhci_dbc *);\n};\n\nstruct xhci_ring;\n\nstruct dbc_ep {\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tstruct xhci_ring *ring;\n\tunsigned int direction: 1;\n\tunsigned int halted: 1;\n};\n\nstruct dbc_regs {\n\t__le32 capability;\n\t__le32 doorbell;\n\t__le32 ersts;\n\t__le32 __reserved_0;\n\t__le64 erstba;\n\t__le64 erdp;\n\t__le32 control;\n\t__le32 status;\n\t__le32 portsc;\n\t__le32 __reserved_1;\n\t__le64 dccp;\n\t__le32 devinfo1;\n\t__le32 devinfo2;\n};\n\nunion xhci_trb;\n\nstruct dbc_request {\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tvoid (*complete)(struct xhci_dbc *, struct dbc_request *);\n\tstruct list_head list_pool;\n\tint status;\n\tunsigned int actual;\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tdma_addr_t trb_dma;\n\tunion xhci_trb *trb;\n\tunsigned int direction: 1;\n};\n\nstruct dbc_str {\n\tchar manufacturer[127];\n\tchar product[127];\n\tchar serial[127];\n};\n\nstruct dbc_str_descs {\n\tchar string0[254];\n\tchar manufacturer[254];\n\tchar product[254];\n\tchar serial[254];\n};\n\nstruct gov_attr_set {\n\tstruct kobject kobj;\n\tstruct list_head policy_list;\n\tstruct mutex update_lock;\n\tint usage_count;\n};\n\nstruct dbs_governor;\n\nstruct dbs_data {\n\tstruct gov_attr_set attr_set;\n\tstruct dbs_governor *gov;\n\tvoid *tuners;\n\tunsigned int ignore_nice_load;\n\tunsigned int sampling_rate;\n\tunsigned int sampling_down_factor;\n\tunsigned int up_threshold;\n\tunsigned int io_is_busy;\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct dbs_governor {\n\tstruct cpufreq_governor gov;\n\tstruct kobj_type kobj_type;\n\tstruct dbs_data *gdbs_data;\n\tunsigned int (*gov_dbs_update)(struct cpufreq_policy *);\n\tstruct policy_dbs_info * (*alloc)(void);\n\tvoid (*free)(struct policy_dbs_info *);\n\tint (*init)(struct dbs_data *);\n\tvoid (*exit)(struct dbs_data *);\n\tvoid (*start)(struct cpufreq_policy *);\n};\n\nstruct dbuf_slice_conf_entry {\n\tu8 active_pipes;\n\tu8 dbuf_mask[4];\n\tbool join_mbus;\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct ddebug_class_map {\n\tstruct list_head link;\n\tstruct module *mod;\n\tconst char *mod_name;\n\tconst char **class_names;\n\tconst int length;\n\tconst int base;\n\tenum class_map_type map_type;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct ohci_hcd;\n\nstruct debug_buffer {\n\tssize_t (*fill_func)(struct debug_buffer *);\n\tstruct ohci_hcd *ohci;\n\tstruct mutex mutex;\n\tsize_t count;\n\tchar *page;\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct dec_data {\n\tstruct task_struct *thr;\n\tstruct crypto_acomp *cc;\n\tstruct acomp_req *cr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n};\n\nstruct decryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tstruct scatterlist frags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct z_stream_s;\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct static_tree_desc_s;\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\nstruct tree_desc_s {\n\tct_data *dyn_tree;\n\tint max_code;\n\tstatic_tree_desc *stat_desc;\n};\n\nstruct deflate_state {\n\tz_streamp strm;\n\tint status;\n\tByte *pending_buf;\n\tulg pending_buf_size;\n\tByte *pending_out;\n\tint pending;\n\tint noheader;\n\tByte data_type;\n\tByte method;\n\tint last_flush;\n\tuInt w_size;\n\tuInt w_bits;\n\tuInt w_mask;\n\tByte *window;\n\tulg window_size;\n\tPos *prev;\n\tPos *head;\n\tuInt ins_h;\n\tuInt hash_size;\n\tuInt hash_bits;\n\tuInt hash_mask;\n\tuInt hash_shift;\n\tlong int block_start;\n\tuInt match_length;\n\tIPos prev_match;\n\tint match_available;\n\tuInt strstart;\n\tuInt match_start;\n\tuInt lookahead;\n\tuInt prev_length;\n\tuInt max_chain_length;\n\tuInt max_lazy_match;\n\tint level;\n\tint strategy;\n\tuInt good_match;\n\tint nice_match;\n\tstruct ct_data_s dyn_ltree[573];\n\tstruct ct_data_s dyn_dtree[61];\n\tstruct ct_data_s bl_tree[39];\n\tstruct tree_desc_s l_desc;\n\tstruct tree_desc_s d_desc;\n\tstruct tree_desc_s bl_desc;\n\tush bl_count[16];\n\tint heap[573];\n\tint heap_len;\n\tint heap_max;\n\tuch depth[573];\n\tuch *l_buf;\n\tuInt lit_bufsize;\n\tuInt last_lit;\n\tush *d_buf;\n\tulg opt_len;\n\tulg static_len;\n\tulg compressed_len;\n\tuInt matches;\n\tint last_eob_len;\n\tush bi_buf;\n\tint bi_valid;\n};\n\nstruct deflate_workspace {\n\tdeflate_state deflate_memory;\n\tByte *window_memory;\n\tPos *prev_memory;\n\tPos *head_memory;\n\tchar *overlay_memory;\n};\n\ntypedef struct deflate_workspace deflate_workspace;\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct demotion_nodes {\n\tnodemask_t preferred;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nunion shortname_store {\n\tunsigned char string[40];\n\tlong unsigned int words[5];\n};\n\nstruct lockref {\n\tunion {\n\t\t__u64 lock_count;\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_info_args {\n\tint parent_ino;\n\tint dname_len;\n\tint ino;\n\tint inode_len;\n\tchar *dname;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 64;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct desc_ptr {\n\tshort unsigned int size;\n\tlong unsigned int address;\n} __attribute__((packed));\n\nstruct desc_struct {\n\tu16 limit0;\n\tu16 base0;\n\tu16 base1: 8;\n\tu16 type: 4;\n\tu16 s: 1;\n\tu16 dpl: 2;\n\tu16 p: 1;\n\tu16 limit1: 4;\n\tu16 avl: 1;\n\tu16 l: 1;\n\tu16 d: 1;\n\tu16 g: 1;\n\tu16 base2: 8;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct detailed_data_monitor_range {\n\tu8 min_vfreq;\n\tu8 max_vfreq;\n\tu8 min_hfreq_khz;\n\tu8 max_hfreq_khz;\n\tu8 pixel_clock_mhz;\n\tu8 flags;\n\tunion {\n\t\tstruct {\n\t\t\tu8 reserved;\n\t\t\tu8 hfreq_start_khz;\n\t\t\tu8 c;\n\t\t\t__le16 m;\n\t\t\tu8 k;\n\t\t\tu8 j;\n\t\t} __attribute__((packed)) gtf2;\n\t\tstruct {\n\t\t\tu8 version;\n\t\t\tu8 data1;\n\t\t\tu8 data2;\n\t\t\tu8 supported_aspects;\n\t\t\tu8 flags;\n\t\t\tu8 supported_scalings;\n\t\t\tu8 preferred_refresh;\n\t\t} cvt;\n\t} formula;\n};\n\nstruct detailed_data_string {\n\tu8 str[13];\n};\n\nstruct detailed_data_wpindex {\n\tu8 white_yx_lo;\n\tu8 white_x_hi;\n\tu8 white_y_hi;\n\tu8 gamma;\n};\n\nstruct detailed_mode_closure {\n\tstruct drm_connector *connector;\n\tconst struct drm_edid *drm_edid;\n\tbool preferred;\n\tint modes;\n};\n\nstruct std_timing {\n\tu8 hsize;\n\tu8 vfreq_aspect;\n};\n\nstruct detailed_non_pixel {\n\tu8 pad1;\n\tu8 type;\n\tu8 pad2;\n\tunion {\n\t\tstruct detailed_data_string str;\n\t\tstruct detailed_data_monitor_range range;\n\t\tstruct detailed_data_wpindex color;\n\t\tstruct std_timing timings[6];\n\t\tstruct cvt_timing cvt[4];\n\t} data;\n};\n\nstruct detailed_pixel_timing {\n\tu8 hactive_lo;\n\tu8 hblank_lo;\n\tu8 hactive_hblank_hi;\n\tu8 vactive_lo;\n\tu8 vblank_lo;\n\tu8 vactive_vblank_hi;\n\tu8 hsync_offset_lo;\n\tu8 hsync_pulse_width_lo;\n\tu8 vsync_offset_pulse_width_lo;\n\tu8 hsync_vsync_offset_pulse_width_hi;\n\tu8 width_mm_lo;\n\tu8 height_mm_lo;\n\tu8 width_height_mm_hi;\n\tu8 hborder;\n\tu8 vborder;\n\tu8 misc;\n};\n\nstruct detailed_timing {\n\t__le16 pixel_clock;\n\tunion {\n\t\tstruct detailed_pixel_timing pixel_data;\n\t\tstruct detailed_non_pixel other_data;\n\t} data;\n};\n\nstruct detected_devices_node {\n\tstruct list_head list;\n\tdev_t dev;\n};\n\nstruct dev_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head exceptions;\n\tenum devcg_behavior behavior;\n};\n\nstruct dev_exception_item {\n\tu32 major;\n\tu32 minor;\n\tshort int type;\n\tshort int access;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n\tu32 max_pasids;\n\tu32 attach_deferred: 1;\n\tu32 pci_32bit_workaround: 1;\n\tu32 require_direct: 1;\n\tu32 shadow_on_flush: 1;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct dev_pasid_info {\n\tstruct list_head link_domain;\n\tstruct device *dev;\n\tioasid_t pasid;\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct dev_pm_domain_attach_data {\n\tconst char * const *pd_names;\n\tconst u32 num_pd_names;\n\tconst u32 pd_flags;\n};\n\nstruct device_link;\n\nstruct dev_pm_domain_list {\n\tstruct device **pd_devs;\n\tstruct device_link **pd_links;\n\tu32 *opp_tokens;\n\tu32 num_pds;\n};\n\nstruct opp_table;\n\nstruct dev_pm_opp;\n\ntypedef int (*config_clks_t)(struct device *, struct opp_table *, struct dev_pm_opp *, void *, bool);\n\ntypedef int (*config_regulators_t)(struct device *, struct dev_pm_opp *, struct dev_pm_opp *, struct regulator **, unsigned int);\n\nstruct dev_pm_opp_config {\n\tconst char * const *clk_names;\n\tconfig_clks_t config_clks;\n\tconst char *prop_name;\n\tconfig_regulators_t config_regulators;\n\tconst unsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char * const *regulator_names;\n\tstruct device *required_dev;\n\tunsigned int required_dev_index;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\nstruct dev_table_entry {\n\tunion {\n\t\tu64 data[4];\n\t\tu128 data128[2];\n\t};\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct dmar_domain;\n\nstruct pasid_table;\n\nstruct device_domain_info {\n\tstruct list_head link;\n\tu32 segment;\n\tu8 bus;\n\tu8 devfn;\n\tu16 pfsid;\n\tu8 pasid_supported: 3;\n\tu8 pasid_enabled: 1;\n\tu8 pri_supported: 1;\n\tu8 pri_enabled: 1;\n\tu8 ats_supported: 1;\n\tu8 ats_enabled: 1;\n\tu8 dtlb_extra_inval: 1;\n\tu8 domain_attached: 1;\n\tu8 ats_qdep;\n\tunsigned int iopf_refcount;\n\tstruct device *dev;\n\tstruct intel_iommu *iommu;\n\tstruct dmar_domain *domain;\n\tstruct pasid_table *pasid_table;\n\tstruct rb_node node;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devid_map {\n\tstruct list_head list;\n\tu8 id;\n\tu32 devid;\n\tbool cmd_line;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n};\n\nstruct devlink;\n\nstruct ib_device;\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_linecard;\n\nstruct devlink_port_ops;\n\nstruct devlink_rate;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nunion dfixed {\n\tu32 full;\n};\n\ntypedef union dfixed fixed20_12;\n\nstruct dg2_snps_phy_buf_trans {\n\tu8 vswing;\n\tu8 pre_cursor;\n\tu8 post_cursor;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\nstruct dio {\n\tint flags;\n\tblk_opf_t opf;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tbool is_pinned;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 64;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n\tu64 cookie;\n\tbool initialized;\n};\n\nstruct dirty_throttle_control {\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct displayid_block {\n\tu8 tag;\n\tu8 rev;\n\tu8 num_bytes;\n};\n\nstruct displayid_detailed_timings_1 {\n\tu8 pixel_clock[3];\n\tu8 flags;\n\t__le16 hactive;\n\t__le16 hblank;\n\t__le16 hsync;\n\t__le16 hsw;\n\t__le16 vactive;\n\t__le16 vblank;\n\t__le16 vsync;\n\t__le16 vsw;\n};\n\nstruct displayid_detailed_timing_block {\n\tstruct displayid_block base;\n\tstruct displayid_detailed_timings_1 timings[0];\n} __attribute__((packed));\n\nstruct displayid_formula_timings_9 {\n\tu8 flags;\n\t__le16 hactive;\n\t__le16 vactive;\n\tu8 vrefresh;\n} __attribute__((packed));\n\nstruct displayid_formula_timing_block {\n\tstruct displayid_block base;\n\tstruct displayid_formula_timings_9 timings[0];\n};\n\nstruct displayid_header {\n\tu8 rev;\n\tu8 bytes;\n\tu8 prod_id;\n\tu8 ext_count;\n};\n\nstruct drm_edid_ident {\n\tu32 panel_id;\n\tconst char *name;\n};\n\nstruct displayid_quirk {\n\tconst struct drm_edid_ident ident;\n\tu8 quirks;\n};\n\nstruct displayid_tiled_block {\n\tstruct displayid_block base;\n\tu8 tile_cap;\n\tu8 topo[3];\n\tu8 tile_size[4];\n\tu8 tile_pixel_bezel[5];\n\tu8 topology_id[8];\n};\n\nstruct displayid_vesa_vendor_specific_block {\n\tstruct displayid_block base;\n\tu8 oui[3];\n\tu8 data_structure_type;\n\tu8 mso;\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\nstruct dm_arg {\n\tunsigned int min;\n\tunsigned int max;\n\tchar *error;\n};\n\nstruct dm_arg_set {\n\tunsigned int argc;\n\tchar **argv;\n};\n\nstruct dm_bio_details {\n\tstruct block_device *bi_bdev;\n\tint __bi_remaining;\n\tlong unsigned int bi_flags;\n\tstruct bvec_iter bi_iter;\n\tbio_end_io_t *bi_end_io;\n};\n\nstruct dm_blkdev_id {\n\tu8 *id;\n\tenum blk_unique_id type;\n};\n\nstruct dm_dev {\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct dax_device *dax_dev;\n\tblk_mode_t mode;\n\tchar name[16];\n};\n\nstruct dm_dev_internal {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev *dm_dev;\n};\n\nstruct dm_dirty_log_type;\n\nstruct dm_target;\n\nstruct dm_dirty_log {\n\tstruct dm_dirty_log_type *type;\n\tint (*flush_callback_fn)(struct dm_target *);\n\tvoid *context;\n};\n\nstruct dm_dirty_log_type {\n\tconst char *name;\n\tstruct module *module;\n\tstruct list_head list;\n\tint (*ctr)(struct dm_dirty_log *, struct dm_target *, unsigned int, char **);\n\tvoid (*dtr)(struct dm_dirty_log *);\n\tint (*presuspend)(struct dm_dirty_log *);\n\tint (*postsuspend)(struct dm_dirty_log *);\n\tint (*resume)(struct dm_dirty_log *);\n\tuint32_t (*get_region_size)(struct dm_dirty_log *);\n\tint (*is_clean)(struct dm_dirty_log *, region_t);\n\tint (*in_sync)(struct dm_dirty_log *, region_t, int);\n\tint (*flush)(struct dm_dirty_log *);\n\tvoid (*mark_region)(struct dm_dirty_log *, region_t);\n\tvoid (*clear_region)(struct dm_dirty_log *, region_t);\n\tint (*get_resync_work)(struct dm_dirty_log *, region_t *);\n\tvoid (*set_region_sync)(struct dm_dirty_log *, region_t, int);\n\tregion_t (*get_sync_count)(struct dm_dirty_log *);\n\tint (*status)(struct dm_dirty_log *, status_type_t, char *, unsigned int);\n\tint (*is_remote_recovering)(struct dm_dirty_log *, region_t);\n};\n\nstruct dm_file {\n\tvolatile unsigned int global_event_nr;\n};\n\nstruct dm_stats_aux {\n\tbool merged;\n\tlong long unsigned int duration_ns;\n};\n\nstruct dm_target_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tunsigned int target_bio_nr;\n\tstruct dm_io *io;\n\tstruct dm_target *ti;\n\tunsigned int *len_ptr;\n\tsector_t old_sector;\n\tstruct bio clone;\n};\n\nstruct mapped_device;\n\nstruct dm_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tspinlock_t lock;\n\tlong unsigned int start_time;\n\tvoid *data;\n\tstruct dm_io *next;\n\tstruct dm_stats_aux stats_aux;\n\tblk_status_t status;\n\tbool requeue_flush_with_data;\n\tatomic_t io_count;\n\tstruct mapped_device *md;\n\tstruct bio *orig_bio;\n\tunsigned int sector_offset;\n\tunsigned int sectors;\n\tstruct dm_target_io tio;\n};\n\nstruct dm_io_client {\n\tmempool_t pool;\n\tstruct bio_set bios;\n};\n\nstruct page_list;\n\nstruct dm_io_memory {\n\tenum dm_io_mem_type type;\n\tunsigned int offset;\n\tunion {\n\t\tstruct page_list *pl;\n\t\tstruct bio *bio;\n\t\tvoid *vma;\n\t\tvoid *addr;\n\t} ptr;\n};\n\ntypedef void (*io_notify_fn)(long unsigned int, void *);\n\nstruct dm_io_notify {\n\tio_notify_fn fn;\n\tvoid *context;\n};\n\nstruct dm_io_region {\n\tstruct block_device *bdev;\n\tsector_t sector;\n\tsector_t count;\n};\n\nstruct dm_io_request {\n\tblk_opf_t bi_opf;\n\tstruct dm_io_memory mem;\n\tstruct dm_io_notify notify;\n\tstruct dm_io_client *client;\n};\n\nstruct dm_ioctl {\n\t__u32 version[3];\n\t__u32 data_size;\n\t__u32 data_start;\n\t__u32 target_count;\n\t__s32 open_count;\n\t__u32 flags;\n\t__u32 event_nr;\n\t__u32 padding;\n\t__u64 dev;\n\tchar name[128];\n\tchar uuid[129];\n\tchar data[7];\n};\n\nstruct dm_kcopyd_throttle;\n\nstruct dm_kcopyd_client {\n\tstruct page_list *pages;\n\tunsigned int nr_reserved_pages;\n\tunsigned int nr_free_pages;\n\tunsigned int sub_job_size;\n\tstruct dm_io_client *io_client;\n\twait_queue_head_t destroyq;\n\tmempool_t job_pool;\n\tstruct workqueue_struct *kcopyd_wq;\n\tstruct work_struct kcopyd_work;\n\tstruct dm_kcopyd_throttle *throttle;\n\tatomic_t nr_jobs;\n\tspinlock_t job_lock;\n\tstruct list_head callback_jobs;\n\tstruct list_head complete_jobs;\n\tstruct list_head io_jobs;\n\tstruct list_head pages_jobs;\n};\n\nstruct dm_kcopyd_throttle {\n\tunsigned int throttle;\n\tunsigned int num_io_jobs;\n\tunsigned int io_period;\n\tunsigned int total_period;\n\tunsigned int last_jiffies;\n};\n\nstruct dm_kobject_holder {\n\tstruct kobject kobj;\n\tstruct completion completion;\n};\n\nstruct dm_md_mempools {\n\tstruct bio_set bs;\n\tstruct bio_set io_bs;\n};\n\nstruct dm_name_list {\n\t__u64 dev;\n\t__u32 next;\n\tchar name[0];\n};\n\nstruct pr_keys;\n\nstruct pr_held_reservation;\n\nstruct dm_pr {\n\tu64 old_key;\n\tu64 new_key;\n\tu32 flags;\n\tbool abort;\n\tbool fail_early;\n\tint ret;\n\tenum pr_type type;\n\tstruct pr_keys *read_keys;\n\tstruct pr_held_reservation *rsv;\n};\n\nstruct mirror;\n\nstruct dm_raid1_bio_record {\n\tstruct mirror *m;\n\tstruct dm_bio_details details;\n\tregion_t write_region;\n};\n\nstruct dm_region_hash;\n\nstruct dm_region {\n\tstruct dm_region_hash *rh;\n\tregion_t key;\n\tint state;\n\tstruct list_head hash_list;\n\tstruct list_head list;\n\tatomic_t pending;\n\tstruct bio_list delayed_bios;\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct dm_region_hash {\n\tuint32_t region_size;\n\tunsigned int region_shift;\n\tstruct dm_dirty_log *log;\n\trwlock_t hash_lock;\n\tunsigned int mask;\n\tunsigned int nr_buckets;\n\tunsigned int prime;\n\tunsigned int shift;\n\tstruct list_head *buckets;\n\tint flush_failure;\n\tunsigned int max_recovery;\n\tspinlock_t region_lock;\n\tatomic_t recovery_in_flight;\n\tstruct list_head clean_regions;\n\tstruct list_head quiesced_regions;\n\tstruct list_head recovered_regions;\n\tstruct list_head failed_recovered_regions;\n\tstruct semaphore recovery_count;\n\tmempool_t region_pool;\n\tvoid *context;\n\tsector_t target_begin;\n\tvoid (*dispatch_bios)(void *, struct bio_list *);\n\tvoid (*wakeup_workers)(void *);\n\tvoid (*wakeup_all_recovery_waiters)(void *);\n};\n\nstruct dm_rq_target_io;\n\nstruct dm_rq_clone_bio_info {\n\tstruct bio *orig;\n\tstruct dm_rq_target_io *tio;\n\tstruct bio clone;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_worker;\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nunion map_info {\n\tvoid *ptr;\n};\n\nstruct dm_rq_target_io {\n\tstruct mapped_device *md;\n\tstruct dm_target *ti;\n\tstruct request *orig;\n\tstruct request *clone;\n\tstruct kthread_work work;\n\tblk_status_t error;\n\tunion map_info info;\n\tstruct dm_stats_aux stats_aux;\n\tlong unsigned int duration_jiffies;\n\tunsigned int n_sectors;\n\tunsigned int completed;\n};\n\nstruct dm_stat_percpu {\n\tlong long unsigned int sectors[2];\n\tlong long unsigned int ios[2];\n\tlong long unsigned int merges[2];\n\tlong long unsigned int ticks[2];\n\tlong long unsigned int io_ticks[2];\n\tlong long unsigned int io_ticks_total;\n\tlong long unsigned int time_in_queue;\n\tlong long unsigned int *histogram;\n};\n\nstruct dm_stat_shared {\n\tatomic_t in_flight[2];\n\tlong long unsigned int stamp;\n\tstruct dm_stat_percpu tmp;\n};\n\nstruct dm_stat {\n\tstruct list_head list_entry;\n\tint id;\n\tunsigned int stat_flags;\n\tsize_t n_entries;\n\tsector_t start;\n\tsector_t end;\n\tsector_t step;\n\tunsigned int n_histogram_entries;\n\tlong long unsigned int *histogram_boundaries;\n\tconst char *program_id;\n\tconst char *aux_data;\n\tstruct callback_head callback_head;\n\tsize_t shared_alloc_size;\n\tsize_t percpu_alloc_size;\n\tsize_t histogram_alloc_size;\n\tstruct dm_stat_percpu *stat_percpu[64];\n\tstruct dm_stat_shared stat_shared[0];\n};\n\nstruct dm_stats_last_position;\n\nstruct dm_stats {\n\tstruct mutex mutex;\n\tstruct list_head list;\n\tstruct dm_stats_last_position *last;\n\tbool precise_timestamps;\n};\n\nstruct dm_stats_last_position {\n\tsector_t last_sector;\n\tunsigned int last_rw;\n};\n\nstruct dm_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mapped_device *, char *);\n\tssize_t (*store)(struct mapped_device *, const char *, size_t);\n};\n\nstruct target_type;\n\nstruct dm_table {\n\tstruct mapped_device *md;\n\tenum dm_queue_mode type;\n\tunsigned int depth;\n\tunsigned int counts[16];\n\tsector_t *index[16];\n\tunsigned int num_targets;\n\tunsigned int num_allocated;\n\tsector_t *highs;\n\tstruct dm_target *targets;\n\tstruct target_type *immutable_target_type;\n\tbool integrity_supported: 1;\n\tbool singleton: 1;\n\tbool flush_bypasses_map: 1;\n\tblk_mode_t mode;\n\tstruct list_head devices;\n\tvoid (*event_fn)(void *);\n\tvoid *event_context;\n\tstruct dm_md_mempools *mempools;\n};\n\nstruct dm_target {\n\tstruct dm_table *table;\n\tstruct target_type *type;\n\tsector_t begin;\n\tsector_t len;\n\tuint32_t max_io_len;\n\tunsigned int num_flush_bios;\n\tunsigned int num_discard_bios;\n\tunsigned int num_secure_erase_bios;\n\tunsigned int num_write_zeroes_bios;\n\tunsigned int per_io_data_size;\n\tvoid *private;\n\tchar *error;\n\tbool flush_supported: 1;\n\tbool discards_supported: 1;\n\tbool zone_reset_all_supported: 1;\n\tbool max_discard_granularity: 1;\n\tbool limit_swap_bios: 1;\n\tbool emulate_zone_append: 1;\n\tbool accounts_remapped_io: 1;\n\tbool needs_bio_set_dev: 1;\n\tbool flush_bypasses_map: 1;\n\tbool mempool_needs_integrity: 1;\n};\n\nstruct dm_target_deps {\n\t__u32 count;\n\t__u32 padding;\n\t__u64 dev[0];\n};\n\nstruct dm_target_msg {\n\t__u64 sector;\n\tchar message[0];\n};\n\nstruct dm_target_spec {\n\t__u64 sector_start;\n\t__u64 length;\n\t__s32 status;\n\t__u32 next;\n\tchar target_type[16];\n};\n\nstruct dm_target_versions {\n\t__u32 next;\n\t__u32 version[3];\n\tchar name[0];\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nstruct dmaengine_result;\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dmaengine_unmap_data;\n\nstruct dma_descriptor_metadata_ops;\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_resv;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct dma_iova_state;\n\nstruct dma_buf_dma {\n\tstruct sg_table sgt;\n\tstruct dma_iova_state *state;\n\tsize_t size;\n};\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct dma_buf_export_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_import_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_buf_sg_table_wrapper {\n\tstruct sg_table *original;\n\tstruct sg_table wrapper;\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_chan___2 {\n\tint lock;\n\tconst char *device_id;\n};\n\nstruct dma_device;\n\nstruct dma_chan_dev;\n\nstruct dma_chan_percpu;\n\nstruct dma_router;\n\nstruct dma_chan {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan *chan;\n\tstruct device device;\n\tint dev_id;\n\tbool chan_dma_dev;\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_chan_tbl_ent {\n\tstruct dma_chan *chan;\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nstruct dma_vec;\n\nstruct dma_interleaved_template;\n\nstruct dma_slave_caps;\n\nstruct dma_slave_config;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan *);\n\tint (*device_router_config)(struct dma_chan *);\n\tvoid (*device_free_chan_resources)(struct dma_chan *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_peripheral_dma_vec)(struct dma_chan *, const struct dma_vec *, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan *, struct dma_interleaved_template *, long unsigned int);\n\tvoid (*device_caps)(struct dma_chan *, struct dma_slave_caps *);\n\tint (*device_config)(struct dma_chan *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan *);\n\tint (*device_resume)(struct dma_chan *);\n\tint (*device_terminate_all)(struct dma_chan *);\n\tvoid (*device_synchronize)(struct dma_chan *);\n\tenum dma_status (*device_tx_status)(struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_fence_array;\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n\tstruct dma_fence_array_cb callbacks[0];\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tstruct dma_fence *prev;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tunion {\n\t\tstruct dma_fence_cb cb;\n\t\tstruct irq_work work;\n\t};\n\tspinlock_t lock;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_fence_unwrap {\n\tstruct dma_fence *chain;\n\tstruct dma_fence *array;\n\tunsigned int index;\n};\n\nstruct dma_fence_work_ops {\n\tconst char *name;\n\tvoid (*work)(struct dma_fence_work *);\n\tvoid (*release)(struct dma_fence_work *);\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tstruct dma_resv_list *fences;\n};\n\nstruct dma_resv_iter {\n\tstruct dma_resv *obj;\n\tenum dma_resv_usage usage;\n\tstruct dma_fence *fence;\n\tenum dma_resv_usage fence_usage;\n\tunsigned int index;\n\tstruct dma_resv_list *fences;\n\tunsigned int num_fences;\n\tbool is_restarted;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 num_fences;\n\tu32 max_fences;\n\tstruct dma_fence *table[0];\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_sgt_handle {\n\tstruct sg_table sgt;\n\tstruct page **pages;\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_vec {\n\tdma_addr_t addr;\n\tsize_t len;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct net_devmem_dmabuf_binding;\n\nstruct dmabuf_genpool_chunk_owner {\n\tstruct net_iov_area area;\n\tstruct net_devmem_dmabuf_binding *binding;\n\tdma_addr_t base_dma_addr;\n};\n\nstruct dmabuf_iter_priv {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmaengine_desc_callback {\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\nstruct dmaengine_unmap_data {\n\tu8 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dmaengine_unmap_pool {\n\tstruct kmem_cache *cache;\n\tconst char *name;\n\tmempool_t *pool;\n\tsize_t size;\n};\n\nstruct dmar_dev_scope;\n\nstruct dmar_atsr_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n\tu8 include_all: 1;\n};\n\nstruct dmar_dev_scope {\n\tstruct device *dev;\n\tu8 bus;\n\tu8 devfn;\n};\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommufd_hw_pagetable;\n\nstruct iommu_domain;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_ops;\n\nstruct iommu_dirty_ops;\n\nstruct iopf_group;\n\nstruct iommu_dma_cookie;\n\nstruct iommu_dma_msi_cookie;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct pt_iommu_ops;\n\nstruct pt_iommu_driver_ops;\n\nstruct pt_iommu {\n\tstruct iommu_domain domain;\n\tconst struct pt_iommu_ops *ops;\n\tconst struct pt_iommu_driver_ops *driver_ops;\n\tint nid;\n\tstruct device *iommu_device;\n};\n\nstruct pt_common {\n\tuintptr_t top_of_table;\n\tu8 max_oasz_lg2;\n\tu8 max_vasz_lg2;\n\tunsigned int features;\n};\n\nstruct pt_x86_64 {\n\tstruct pt_common common;\n};\n\nstruct pt_iommu_x86_64 {\n\tstruct pt_iommu iommu;\n\tstruct pt_x86_64 x86_64_pt;\n};\n\nstruct pt_vtdss {\n\tstruct pt_common common;\n};\n\nstruct pt_iommu_vtdss {\n\tstruct pt_iommu iommu;\n\tstruct pt_vtdss vtdss_pt;\n};\n\nstruct iommu_hwpt_vtd_s1 {\n\t__u64 flags;\n\t__u64 pgtbl_addr;\n\t__u32 addr_width;\n\t__u32 __reserved;\n};\n\nstruct mmu_notifier_ops;\n\nstruct mmu_notifier {\n\tstruct hlist_node hlist;\n\tconst struct mmu_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct callback_head rcu;\n\tunsigned int users;\n};\n\nstruct qi_batch;\n\nstruct dmar_domain {\n\tunion {\n\t\tstruct iommu_domain domain;\n\t\tstruct pt_iommu iommu;\n\t\tstruct pt_iommu_x86_64 fspt;\n\t\tstruct pt_iommu_vtdss sspt;\n\t};\n\tstruct xarray iommu_array;\n\tu8 force_snooping: 1;\n\tu8 dirty_tracking: 1;\n\tu8 nested_parent: 1;\n\tu8 iotlb_sync_map: 1;\n\tspinlock_t lock;\n\tstruct list_head devices;\n\tstruct list_head dev_pasids;\n\tspinlock_t cache_lock;\n\tstruct list_head cache_tags;\n\tstruct qi_batch *qi_batch;\n\tunion {\n\t\tstruct {\n\t\t\tspinlock_t s1_lock;\n\t\t\tstruct list_head s1_domains;\n\t\t};\n\t\tstruct {\n\t\t\tstruct dmar_domain *s2_domain;\n\t\t\tstruct iommu_hwpt_vtd_s1 s1_cfg;\n\t\t\tstruct list_head s2_link;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mmu_notifier notifier;\n\t\t};\n\t};\n};\n\nstruct dmar_drhd_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tu64 reg_base_addr;\n\tlong unsigned int reg_size;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n\tu16 segment;\n\tu8 ignored: 1;\n\tu8 include_all: 1;\n\tu8 gfx_dedicated: 1;\n\tstruct intel_iommu *iommu;\n};\n\nstruct dmar_pci_path {\n\tu8 bus;\n\tu8 device;\n\tu8 function;\n};\n\nstruct dmar_pci_notify_info {\n\tstruct pci_dev *dev;\n\tlong unsigned int event;\n\tint bus;\n\tu16 seg;\n\tu16 level;\n\tstruct dmar_pci_path path[0];\n};\n\ntypedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);\n\nstruct dmar_res_callback {\n\tdmar_res_handler_t cb[7];\n\tvoid *arg[7];\n\tbool ignore_unhandled;\n\tbool print_entry;\n};\n\nstruct dmar_rmrr_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tu64 base_address;\n\tu64 end_address;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n};\n\nstruct dmar_satc_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tstruct dmar_dev_scope *devices;\n\tstruct intel_iommu *iommu;\n\tint devices_cnt;\n\tu8 atc_required: 1;\n};\n\nstruct dmc_fw_info {\n\tu32 mmio_count;\n\ti915_reg_t mmioaddr[20];\n\tu32 mmiodata[20];\n\tu32 dmc_offset;\n\tu32 start_mmioaddr;\n\tu32 dmc_fw_size;\n\tu32 *payload;\n\tbool present;\n};\n\nstruct dmi_device {\n\tstruct list_head list;\n\tint type;\n\tconst char *name;\n\tvoid *device_data;\n};\n\nstruct dmi_dev_onboard {\n\tstruct dmi_device dev;\n\tint instance;\n\tint segment;\n\tint bus;\n\tint devfn;\n};\n\nstruct dmi_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint field;\n};\n\nstruct dmi_header {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n};\n\nstruct dmi_memdev_info {\n\tconst char *device;\n\tconst char *bank;\n\tu64 size;\n\tu16 handle;\n\tu8 type;\n};\n\nstruct dmi_onboard_device_info {\n\tconst char *name;\n\tu8 type;\n\tshort unsigned int i2c_addr;\n\tconst char *i2c_type;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct dock_dependent_device {\n\tstruct list_head list;\n\tstruct acpi_device *adev;\n};\n\nstruct platform_device;\n\nstruct dock_station {\n\tacpi_handle handle;\n\tlong unsigned int last_dock_time;\n\tu32 flags;\n\tstruct list_head dependent_devices;\n\tstruct list_head sibling;\n\tstruct platform_device *dock_device;\n};\n\nstruct dotl_iattr_map {\n\tint iattr_valid;\n\tint p9_iattr_valid;\n};\n\nstruct dotl_openflag_map {\n\tint open_flag;\n\tint dotl_flag;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct drm_edp_backlight_info {\n\tu8 pwmgen_bit_count;\n\tu8 pwm_freq_pre_divider;\n\tu32 max;\n\tbool lsb_reg_used: 1;\n\tbool aux_enable: 1;\n\tbool aux_set: 1;\n\tbool luminance_set: 1;\n};\n\nstruct drm_dp_aux;\n\nstruct dp_aux_backlight {\n\tstruct backlight_device *base;\n\tstruct drm_dp_aux *aux;\n\tstruct drm_edp_backlight_info info;\n\tbool enabled;\n};\n\nstruct dp_sdp_header {\n\tu8 HB0;\n\tu8 HB1;\n\tu8 HB2;\n\tu8 HB3;\n};\n\nstruct dp_sdp {\n\tstruct dp_sdp_header sdp_header;\n\tu8 db[32];\n};\n\nstruct dpages {\n\tvoid (*get_page)(struct dpages *, struct page **, long unsigned int *, unsigned int *);\n\tvoid (*next_page)(struct dpages *);\n\tunion {\n\t\tunsigned int context_u;\n\t\tstruct bvec_iter context_bi;\n\t};\n\tvoid *context_ptr;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n};\n\nstruct dpcd_quirk {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tbool is_branch;\n\tu32 quirks;\n};\n\nstruct dpll {\n\tint n;\n\tint m1;\n\tint m2;\n\tint p1;\n\tint p2;\n\tint dot;\n\tint vco;\n\tint m;\n\tint p;\n};\n\nstruct intel_dpll_funcs;\n\nstruct dpll_info {\n\tconst char *name;\n\tconst struct intel_dpll_funcs *funcs;\n\tenum intel_dpll_id id;\n\tenum intel_display_power_domain power_domain;\n\tbool always_on;\n\tbool is_alt_port_dpll;\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 64;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n};\n\nstruct dqstats {\n\tlong unsigned int stat[8];\n\tstruct percpu_counter counter[8];\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct dquot_warn {\n\tstruct super_block *w_sb;\n\tstruct kqid w_dq_id;\n\tshort int w_type;\n};\n\nstruct dram_dimm_info {\n\tu16 size;\n\tu8 width;\n\tu8 ranks;\n};\n\nstruct dram_channel_info {\n\tstruct dram_dimm_info dimm_l;\n\tstruct dram_dimm_info dimm_s;\n\tu8 ranks;\n\tbool is_16gb_dimm;\n};\n\nstruct dram_info {\n\tenum intel_dram_type type;\n\tunsigned int fsb_freq;\n\tunsigned int mem_freq;\n\tu8 num_channels;\n\tu8 num_qgv_points;\n\tu8 num_psf_gv_points;\n\tbool ecc_impacting_de_bw;\n\tbool symmetric_memory;\n\tbool has_16gb_dimms;\n};\n\nstruct drbg_core {\n\tdrbg_flag_t flags;\n\t__u8 statelen;\n\t__u8 blocklen_bytes;\n\tchar cra_name[128];\n\tchar backend_cra_name[128];\n};\n\nstruct drbg_string {\n\tconst unsigned char *buf;\n\tsize_t len;\n\tstruct list_head list;\n};\n\nstruct drbg_state_ops;\n\nstruct drbg_state {\n\tstruct mutex drbg_mutex;\n\tunsigned char *V;\n\tunsigned char *Vbuf;\n\tunsigned char *C;\n\tunsigned char *Cbuf;\n\tsize_t reseed_ctr;\n\tsize_t reseed_threshold;\n\tunsigned char *scratchpad;\n\tunsigned char *scratchpadbuf;\n\tvoid *priv_data;\n\tstruct crypto_skcipher *ctr_handle;\n\tstruct skcipher_request *ctr_req;\n\t__u8 *outscratchpadbuf;\n\t__u8 *outscratchpad;\n\tstruct crypto_wait ctr_wait;\n\tstruct scatterlist sg_in;\n\tstruct scatterlist sg_out;\n\tenum drbg_seed_state seeded;\n\tlong unsigned int last_seed_time;\n\tbool pr;\n\tbool fips_primed;\n\tunsigned char *prev;\n\tstruct crypto_rng *jent;\n\tconst struct drbg_state_ops *d_ops;\n\tconst struct drbg_core *core;\n\tstruct drbg_string test_data;\n};\n\nstruct drbg_state_ops {\n\tint (*update)(struct drbg_state *, struct list_head *, int);\n\tint (*generate)(struct drbg_state *, unsigned char *, unsigned int, struct list_head *);\n\tint (*crypto_init)(struct drbg_state *);\n\tint (*crypto_fini)(struct drbg_state *);\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drm_object_properties;\n\nstruct drm_mode_object {\n\tuint32_t id;\n\tuint32_t type;\n\tstruct drm_object_properties *properties;\n\tstruct kref refcount;\n\tvoid (*free_cb)(struct kref *);\n};\n\nstruct drm_format_info;\n\nstruct drm_framebuffer_funcs;\n\nstruct drm_gem_object;\n\nstruct drm_framebuffer {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar comm[16];\n\tconst struct drm_format_info *format;\n\tconst struct drm_framebuffer_funcs *funcs;\n\tunsigned int pitches[4];\n\tunsigned int offsets[4];\n\tuint64_t modifier;\n\tunsigned int width;\n\tunsigned int height;\n\tint flags;\n\tunsigned int internal_flags;\n\tstruct list_head filp_head;\n\tstruct drm_gem_object *obj[4];\n};\n\nstruct drm_afbc_framebuffer {\n\tstruct drm_framebuffer base;\n\tu32 block_width;\n\tu32 block_height;\n\tu32 aligned_width;\n\tu32 aligned_height;\n\tu32 offset;\n\tu32 afbc_size;\n};\n\nstruct drm_rect {\n\tint x1;\n\tint y1;\n\tint x2;\n\tint y2;\n};\n\nstruct drm_atomic_helper_damage_iter {\n\tstruct drm_rect plane_src;\n\tconst struct drm_rect *clips;\n\tuint32_t num_clips;\n\tuint32_t curr_clip;\n\tbool full_update;\n};\n\nstruct drm_atomic_state {\n\tstruct kref ref;\n\tstruct drm_device *dev;\n\tbool allow_modeset: 1;\n\tbool legacy_cursor_update: 1;\n\tbool async_update: 1;\n\tbool duplicated: 1;\n\tbool checked: 1;\n\tbool plane_color_pipeline: 1;\n\tstruct __drm_colorops_state *colorops;\n\tstruct __drm_planes_state *planes;\n\tstruct __drm_crtcs_state *crtcs;\n\tint num_connector;\n\tstruct __drm_connnectors_state *connectors;\n\tint num_private_objs;\n\tstruct __drm_private_objs_state *private_objs;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct drm_crtc_commit *fake_commit;\n\tstruct work_struct commit_work;\n};\n\nstruct drm_audio_component_ops;\n\nstruct drm_audio_component_audio_ops;\n\nstruct drm_audio_component {\n\tstruct device *dev;\n\tconst struct drm_audio_component_ops *ops;\n\tconst struct drm_audio_component_audio_ops *audio_ops;\n\tstruct completion master_bind_complete;\n};\n\nstruct drm_audio_component_audio_ops {\n\tvoid *audio_ptr;\n\tvoid (*pin_eld_notify)(void *, int, int);\n\tint (*pin2port)(void *, int);\n\tint (*master_bind)(struct device *, struct drm_audio_component *);\n\tvoid (*master_unbind)(struct device *, struct drm_audio_component *);\n};\n\nstruct drm_audio_component_ops {\n\tstruct module *owner;\n\tlong unsigned int (*get_power)(struct device *);\n\tvoid (*put_power)(struct device *, long unsigned int);\n\tvoid (*codec_wake_override)(struct device *, bool);\n\tint (*get_cdclk_freq)(struct device *);\n\tint (*sync_audio_rate)(struct device *, int, int, int);\n\tint (*get_eld)(struct device *, int, int, bool *, unsigned char *, int);\n};\n\nstruct drm_auth {\n\tdrm_magic_t magic;\n};\n\nstruct drm_private_state_funcs;\n\nstruct drm_private_obj {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_modeset_lock lock;\n\tstruct drm_private_state *state;\n\tconst struct drm_private_state_funcs *funcs;\n};\n\nstruct drm_encoder;\n\nstruct drm_bridge_timings;\n\nstruct drm_bridge_funcs;\n\nstruct i2c_adapter;\n\nstruct drm_bridge {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tstruct drm_encoder *encoder;\n\tstruct list_head chain_node;\n\tstruct device_node *of_node;\n\tstruct list_head list;\n\tconst struct drm_bridge_timings *timings;\n\tconst struct drm_bridge_funcs *funcs;\n\tvoid *container;\n\tstruct kref refcount;\n\tbool unplugged;\n\tvoid *driver_private;\n\tenum drm_bridge_ops ops;\n\tint type;\n\tbool interlace_allowed;\n\tbool ycbcr_420_allowed;\n\tbool pre_enable_prev_first;\n\tbool support_hdcp;\n\tstruct i2c_adapter *ddc;\n\tconst char *vendor;\n\tconst char *product;\n\tunsigned int supported_formats;\n\tunsigned int max_bpc;\n\tstruct device *hdmi_cec_dev;\n\tstruct device *hdmi_audio_dev;\n\tint hdmi_audio_max_i2s_playback_channels;\n\tu64 hdmi_audio_i2s_formats;\n\tunsigned int hdmi_audio_spdif_playback: 1;\n\tint hdmi_audio_dai_port;\n\tconst char *hdmi_cec_adapter_name;\n\tu8 hdmi_cec_available_las;\n\tstruct mutex hpd_mutex;\n\tvoid (*hpd_cb)(void *, enum drm_connector_status);\n\tvoid *hpd_data;\n\tstruct drm_bridge *next_bridge;\n};\n\nstruct hdmi_codec_daifmt;\n\nstruct hdmi_codec_params;\n\nstruct drm_display_info;\n\nstruct drm_display_mode;\n\nstruct drm_bridge_state;\n\nstruct drm_bridge_funcs {\n\tint (*attach)(struct drm_bridge *, struct drm_encoder *, enum drm_bridge_attach_flags);\n\tvoid (*destroy)(struct drm_bridge *);\n\tvoid (*detach)(struct drm_bridge *);\n\tenum drm_mode_status (*mode_valid)(struct drm_bridge *, const struct drm_display_info *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_bridge *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*disable)(struct drm_bridge *);\n\tvoid (*post_disable)(struct drm_bridge *);\n\tvoid (*mode_set)(struct drm_bridge *, const struct drm_display_mode *, const struct drm_display_mode *);\n\tvoid (*pre_enable)(struct drm_bridge *);\n\tvoid (*enable)(struct drm_bridge *);\n\tvoid (*atomic_pre_enable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_bridge *, struct drm_atomic_state *);\n\tvoid (*atomic_post_disable)(struct drm_bridge *, struct drm_atomic_state *);\n\tstruct drm_bridge_state * (*atomic_duplicate_state)(struct drm_bridge *);\n\tvoid (*atomic_destroy_state)(struct drm_bridge *, struct drm_bridge_state *);\n\tu32 * (*atomic_get_output_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, unsigned int *);\n\tu32 * (*atomic_get_input_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, u32, unsigned int *);\n\tint (*atomic_check)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *);\n\tstruct drm_bridge_state * (*atomic_reset)(struct drm_bridge *);\n\tenum drm_connector_status (*detect)(struct drm_bridge *, struct drm_connector *);\n\tint (*get_modes)(struct drm_bridge *, struct drm_connector *);\n\tconst struct drm_edid * (*edid_read)(struct drm_bridge *, struct drm_connector *);\n\tvoid (*hpd_notify)(struct drm_bridge *, struct drm_connector *, enum drm_connector_status);\n\tvoid (*hpd_enable)(struct drm_bridge *);\n\tvoid (*hpd_disable)(struct drm_bridge *);\n\tenum drm_mode_status (*hdmi_tmds_char_rate_valid)(const struct drm_bridge *, const struct drm_display_mode *, long long unsigned int);\n\tint (*hdmi_clear_avi_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_avi_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_hdmi_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_hdmi_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_hdr_drm_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_hdr_drm_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_spd_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_spd_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_clear_audio_infoframe)(struct drm_bridge *);\n\tint (*hdmi_write_audio_infoframe)(struct drm_bridge *, const u8 *, size_t);\n\tint (*hdmi_audio_startup)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_audio_prepare)(struct drm_bridge *, struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*hdmi_audio_shutdown)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_audio_mute_stream)(struct drm_bridge *, struct drm_connector *, bool, int);\n\tint (*hdmi_cec_init)(struct drm_bridge *, struct drm_connector *);\n\tint (*hdmi_cec_enable)(struct drm_bridge *, bool);\n\tint (*hdmi_cec_log_addr)(struct drm_bridge *, u8);\n\tint (*hdmi_cec_transmit)(struct drm_bridge *, u8, u32, struct cec_msg *);\n\tint (*dp_audio_startup)(struct drm_bridge *, struct drm_connector *);\n\tint (*dp_audio_prepare)(struct drm_bridge *, struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*dp_audio_shutdown)(struct drm_bridge *, struct drm_connector *);\n\tint (*dp_audio_mute_stream)(struct drm_bridge *, struct drm_connector *, bool, int);\n\tvoid (*debugfs_init)(struct drm_bridge *, struct dentry *);\n};\n\nstruct drm_private_state {\n\tstruct drm_atomic_state *state;\n\tstruct drm_private_obj *obj;\n};\n\nstruct drm_bus_cfg {\n\tu32 format;\n\tu32 flags;\n};\n\nstruct drm_bridge_state {\n\tstruct drm_private_state base;\n\tstruct drm_bridge *bridge;\n\tstruct drm_bus_cfg input_bus_cfg;\n\tstruct drm_bus_cfg output_bus_cfg;\n};\n\nstruct drm_bridge_timings {\n\tu32 input_bus_flags;\n\tu32 setup_time_ps;\n\tu32 hold_time_ps;\n\tbool dual_link;\n};\n\nstruct drm_buddy_block;\n\nstruct drm_buddy {\n\tstruct rb_root **free_trees;\n\tstruct drm_buddy_block **roots;\n\tunsigned int n_roots;\n\tunsigned int max_order;\n\tu64 chunk_size;\n\tu64 size;\n\tu64 avail;\n\tu64 clear_avail;\n};\n\nstruct drm_buddy_block {\n\tu64 header;\n\tstruct drm_buddy_block *left;\n\tstruct drm_buddy_block *right;\n\tstruct drm_buddy_block *parent;\n\tvoid *private;\n\tunion {\n\t\tstruct rb_node rb;\n\t\tstruct list_head link;\n\t};\n\tstruct list_head tmp_link;\n};\n\nstruct drm_client {\n\tint idx;\n\tint auth;\n\tlong unsigned int pid;\n\tlong unsigned int uid;\n\tlong unsigned int magic;\n\tlong unsigned int iocs;\n};\n\nstruct drm_client32 {\n\tint idx;\n\tint auth;\n\tu32 pid;\n\tu32 uid;\n\tu32 magic;\n\tu32 iocs;\n};\n\ntypedef struct drm_client32 drm_client32_t;\n\nstruct drm_clip_rect {\n\tshort unsigned int x1;\n\tshort unsigned int y1;\n\tshort unsigned int x2;\n\tshort unsigned int y2;\n};\n\nstruct drm_connector_tv_margins {\n\tunsigned int bottom;\n\tunsigned int left;\n\tunsigned int right;\n\tunsigned int top;\n};\n\nstruct drm_cmdline_mode {\n\tchar name[32];\n\tbool specified;\n\tbool refresh_specified;\n\tbool bpp_specified;\n\tunsigned int pixel_clock;\n\tint xres;\n\tint yres;\n\tint bpp;\n\tint refresh;\n\tbool rb;\n\tbool interlace;\n\tbool cvt;\n\tbool margins;\n\tenum drm_connector_force force;\n\tunsigned int rotation_reflection;\n\tenum drm_panel_orientation panel_orientation;\n\tstruct drm_connector_tv_margins tv_margins;\n\tenum drm_connector_tv_mode tv_mode;\n\tbool tv_mode_specified;\n};\n\nstruct drm_color_ctm {\n\t__u64 matrix[9];\n};\n\nstruct drm_color_ctm_3x4 {\n\t__u64 matrix[12];\n};\n\nstruct drm_color_lut {\n\t__u16 red;\n\t__u16 green;\n\t__u16 blue;\n\t__u16 reserved;\n};\n\nstruct drm_color_lut32 {\n\t__u32 red;\n\t__u32 green;\n\t__u32 blue;\n\t__u32 reserved;\n};\n\nstruct drm_object_properties {\n\tint count;\n\tstruct drm_property *properties[64];\n\tuint64_t values[64];\n};\n\nstruct drm_colorop {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tunsigned int index;\n\tstruct drm_mode_object base;\n\tstruct drm_plane *plane;\n\tstruct drm_colorop_state *state;\n\tstruct drm_object_properties properties;\n\tenum drm_colorop_type type;\n\tstruct drm_colorop *next;\n\tstruct drm_property *type_property;\n\tstruct drm_property *bypass_property;\n\tuint32_t size;\n\tenum drm_colorop_lut1d_interpolation_type lut1d_interpolation;\n\tenum drm_colorop_lut3d_interpolation_type lut3d_interpolation;\n\tstruct drm_property *lut1d_interpolation_property;\n\tstruct drm_property *curve_1d_type_property;\n\tstruct drm_property *multiplier_property;\n\tstruct drm_property *size_property;\n\tstruct drm_property *lut3d_interpolation_property;\n\tstruct drm_property *data_property;\n\tstruct drm_property *next_property;\n};\n\nstruct drm_property_blob;\n\nstruct drm_colorop_state {\n\tstruct drm_colorop *colorop;\n\tbool bypass;\n\tenum drm_colorop_curve_1d_type curve_1d_type;\n\tuint64_t multiplier;\n\tstruct drm_property_blob *data;\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_conn_prop_enum_list {\n\tint type;\n\tconst char *name;\n\tstruct ida ida;\n};\n\nstruct drm_scrambling {\n\tbool supported;\n\tbool low_rates;\n};\n\nstruct drm_scdc {\n\tbool supported;\n\tbool read_request;\n\tstruct drm_scrambling scrambling;\n};\n\nstruct drm_hdmi_dsc_cap {\n\tbool v_1p2;\n\tbool native_420;\n\tbool all_bpp;\n\tu8 bpc_supported;\n\tu8 max_slices;\n\tint clk_per_slice;\n\tu8 max_lanes;\n\tu8 max_frl_rate_per_lane;\n\tu8 total_chunk_kbytes;\n};\n\nstruct drm_hdmi_info {\n\tstruct drm_scdc scdc;\n\tlong unsigned int y420_vdb_modes[4];\n\tlong unsigned int y420_cmdb_modes[4];\n\tu8 y420_dc_modes;\n\tu8 max_frl_rate_per_lane;\n\tu8 max_lanes;\n\tstruct drm_hdmi_dsc_cap dsc_cap;\n};\n\nstruct hdr_static_metadata {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\t__u16 max_cll;\n\t__u16 max_fall;\n\t__u16 min_cll;\n};\n\nstruct hdr_sink_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_static_metadata hdmi_type1;\n\t};\n};\n\nstruct drm_monitor_range_info {\n\tu16 min_vfreq;\n\tu16 max_vfreq;\n};\n\nstruct drm_luminance_range_info {\n\tu32 min_luminance;\n\tu32 max_luminance;\n};\n\nstruct drm_display_info {\n\tunsigned int width_mm;\n\tunsigned int height_mm;\n\tunsigned int bpc;\n\tenum subpixel_order subpixel_order;\n\tint panel_orientation;\n\tu32 color_formats;\n\tconst u32 *bus_formats;\n\tunsigned int num_bus_formats;\n\tu32 bus_flags;\n\tint max_tmds_clock;\n\tbool dvi_dual;\n\tbool is_hdmi;\n\tbool has_audio;\n\tbool has_hdmi_infoframe;\n\tbool rgb_quant_range_selectable;\n\tu8 edid_hdmi_rgb444_dc_modes;\n\tu8 edid_hdmi_ycbcr444_dc_modes;\n\tu8 cea_rev;\n\tstruct drm_hdmi_info hdmi;\n\tstruct hdr_sink_metadata hdr_sink_metadata;\n\tbool non_desktop;\n\tstruct drm_monitor_range_info monitor_range;\n\tstruct drm_luminance_range_info luminance_range;\n\tu8 mso_stream_count;\n\tu8 mso_pixel_overlap;\n\tu32 max_dsc_bpp;\n\tu8 *vics;\n\tint vics_len;\n\tu32 quirks;\n\tu16 source_physical_address;\n};\n\nstruct drm_privacy_screen;\n\nstruct hdmi_any_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n};\n\nstruct hdmi_avi_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tbool itc;\n\tunsigned char pixel_repeat;\n\tenum hdmi_colorspace colorspace;\n\tenum hdmi_scan_mode scan_mode;\n\tenum hdmi_colorimetry colorimetry;\n\tenum hdmi_picture_aspect picture_aspect;\n\tenum hdmi_active_aspect active_aspect;\n\tenum hdmi_extended_colorimetry extended_colorimetry;\n\tenum hdmi_quantization_range quantization_range;\n\tenum hdmi_nups nups;\n\tunsigned char video_code;\n\tenum hdmi_ycc_quantization_range ycc_quantization_range;\n\tenum hdmi_content_type content_type;\n\tshort unsigned int top_bar;\n\tshort unsigned int bottom_bar;\n\tshort unsigned int left_bar;\n\tshort unsigned int right_bar;\n};\n\nstruct hdmi_spd_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tchar vendor[8];\n\tchar product[16];\n\tenum hdmi_spd_sdi sdi;\n};\n\nstruct hdmi_vendor_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned int oui;\n\tu8 vic;\n\tenum hdmi_3d_structure s3d_struct;\n\tunsigned int s3d_ext_data;\n};\n\nunion hdmi_vendor_any_infoframe {\n\tstruct {\n\t\tenum hdmi_infoframe_type type;\n\t\tunsigned char version;\n\t\tunsigned char length;\n\t\tunsigned int oui;\n\t} any;\n\tstruct hdmi_vendor_infoframe hdmi;\n};\n\nstruct hdmi_audio_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned char channels;\n\tenum hdmi_audio_coding_type coding_type;\n\tenum hdmi_audio_sample_size sample_size;\n\tenum hdmi_audio_sample_frequency sample_frequency;\n\tenum hdmi_audio_coding_type_ext coding_type_ext;\n\tunsigned char channel_allocation;\n\tunsigned char level_shift_value;\n\tbool downmix_inhibit;\n};\n\nstruct hdmi_drm_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_eotf eotf;\n\tenum hdmi_metadata_type metadata_type;\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} white_point;\n\tu16 max_display_mastering_luminance;\n\tu16 min_display_mastering_luminance;\n\tu16 max_cll;\n\tu16 max_fall;\n};\n\nunion hdmi_infoframe {\n\tstruct hdmi_any_infoframe any;\n\tstruct hdmi_avi_infoframe avi;\n\tstruct hdmi_spd_infoframe spd;\n\tunion hdmi_vendor_any_infoframe vendor;\n\tstruct hdmi_audio_infoframe audio;\n\tstruct hdmi_drm_infoframe drm;\n};\n\nstruct drm_connector_hdmi_infoframe {\n\tunion hdmi_infoframe data;\n\tbool set;\n};\n\nstruct drm_connector_hdmi_funcs;\n\nstruct drm_connector_hdmi {\n\tunsigned char vendor[8];\n\tunsigned char product[16];\n\tlong unsigned int supported_formats;\n\tconst struct drm_connector_hdmi_funcs *funcs;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct drm_connector_hdmi_infoframe audio;\n\t} infoframes;\n};\n\nstruct drm_connector_hdmi_audio_funcs;\n\nstruct drm_connector_hdmi_audio {\n\tconst struct drm_connector_hdmi_audio_funcs *funcs;\n\tstruct platform_device *codec_pdev;\n\tstruct mutex lock;\n\tvoid (*plugged_cb)(struct device *, bool);\n\tstruct device *plugged_cb_dev;\n\tbool last_state;\n\tint dai_port;\n};\n\nstruct drm_connector_cec_funcs;\n\nstruct drm_connector_cec {\n\tstruct mutex mutex;\n\tconst struct drm_connector_cec_funcs *funcs;\n\tvoid *data;\n};\n\nstruct drm_connector_funcs;\n\nstruct drm_connector_helper_funcs;\n\nstruct drm_tile_group;\n\nstruct drm_connector {\n\tstruct drm_device *dev;\n\tstruct device *kdev;\n\tstruct device_attribute *attr;\n\tstruct fwnode_handle *fwnode;\n\tstruct list_head head;\n\tstruct list_head global_connector_list_entry;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tstruct mutex mutex;\n\tunsigned int index;\n\tint connector_type;\n\tint connector_type_id;\n\tbool interlace_allowed;\n\tbool doublescan_allowed;\n\tbool stereo_allowed;\n\tbool ycbcr_420_allowed;\n\tenum drm_connector_registration_state registration_state;\n\tstruct list_head modes;\n\tenum drm_connector_status status;\n\tstruct list_head probed_modes;\n\tstruct drm_display_info display_info;\n\tconst struct drm_connector_funcs *funcs;\n\tstruct drm_property_blob *edid_blob_ptr;\n\tstruct drm_object_properties properties;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *vrr_capable_property;\n\tstruct drm_property *colorspace_property;\n\tstruct drm_property_blob *path_blob_ptr;\n\tunsigned int max_bpc;\n\tstruct drm_property *max_bpc_property;\n\tstruct drm_privacy_screen *privacy_screen;\n\tstruct notifier_block privacy_screen_notifier;\n\tstruct drm_property *privacy_screen_sw_state_property;\n\tstruct drm_property *privacy_screen_hw_state_property;\n\tstruct drm_property *broadcast_rgb_property;\n\tuint8_t polled;\n\tint dpms;\n\tconst struct drm_connector_helper_funcs *helper_private;\n\tstruct drm_cmdline_mode cmdline_mode;\n\tenum drm_connector_force force;\n\tconst struct drm_edid *edid_override;\n\tstruct mutex edid_override_mutex;\n\tu64 epoch_counter;\n\tu32 possible_encoders;\n\tstruct drm_encoder *encoder;\n\tuint8_t eld[128];\n\tstruct mutex eld_mutex;\n\tbool latency_present[2];\n\tint video_latency[2];\n\tint audio_latency[2];\n\tstruct i2c_adapter *ddc;\n\tint null_edid_counter;\n\tunsigned int bad_edid_counter;\n\tbool edid_corrupt;\n\tu8 real_edid_checksum;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_connector_state *state;\n\tstruct drm_property_blob *tile_blob_ptr;\n\tbool has_tile;\n\tstruct drm_tile_group *tile_group;\n\tbool tile_is_single_monitor;\n\tuint8_t num_h_tile;\n\tuint8_t num_v_tile;\n\tuint8_t tile_h_loc;\n\tuint8_t tile_v_loc;\n\tuint16_t tile_h_size;\n\tuint16_t tile_v_size;\n\tstruct llist_node free_node;\n\tstruct drm_connector_hdmi hdmi;\n\tstruct drm_connector_hdmi_audio hdmi_audio;\n\tstruct drm_connector_cec cec;\n};\n\nstruct drm_connector_cec_funcs {\n\tvoid (*phys_addr_invalidate)(struct drm_connector *);\n\tvoid (*phys_addr_set)(struct drm_connector *, u16);\n};\n\nstruct drm_printer;\n\nstruct drm_connector_funcs {\n\tint (*dpms)(struct drm_connector *, int);\n\tvoid (*reset)(struct drm_connector *);\n\tenum drm_connector_status (*detect)(struct drm_connector *, bool);\n\tvoid (*force)(struct drm_connector *);\n\tint (*fill_modes)(struct drm_connector *, uint32_t, uint32_t);\n\tint (*set_property)(struct drm_connector *, struct drm_property *, uint64_t);\n\tint (*late_register)(struct drm_connector *);\n\tvoid (*early_unregister)(struct drm_connector *);\n\tvoid (*destroy)(struct drm_connector *);\n\tstruct drm_connector_state * (*atomic_duplicate_state)(struct drm_connector *);\n\tvoid (*atomic_destroy_state)(struct drm_connector *, struct drm_connector_state *);\n\tint (*atomic_set_property)(struct drm_connector *, struct drm_connector_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_connector *, const struct drm_connector_state *, struct drm_property *, uint64_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_connector_state *);\n\tvoid (*oob_hotplug_event)(struct drm_connector *, enum drm_connector_status);\n\tvoid (*debugfs_init)(struct drm_connector *, struct dentry *);\n};\n\nstruct drm_connector_hdmi_audio_funcs {\n\tint (*startup)(struct drm_connector *);\n\tint (*prepare)(struct drm_connector *, struct hdmi_codec_daifmt *, struct hdmi_codec_params *);\n\tvoid (*shutdown)(struct drm_connector *);\n\tint (*mute_stream)(struct drm_connector *, bool, int);\n};\n\nstruct drm_connector_infoframe_funcs {\n\tint (*clear_infoframe)(struct drm_connector *);\n\tint (*write_infoframe)(struct drm_connector *, const u8 *, size_t);\n};\n\nstruct drm_connector_hdmi_funcs {\n\tenum drm_mode_status (*tmds_char_rate_valid)(const struct drm_connector *, const struct drm_display_mode *, long long unsigned int);\n\tconst struct drm_edid * (*read_edid)(struct drm_connector *);\n\tstruct drm_connector_infoframe_funcs avi;\n\tstruct drm_connector_infoframe_funcs hdmi;\n\tstruct drm_connector_infoframe_funcs audio;\n\tstruct drm_connector_infoframe_funcs hdr_drm;\n\tstruct drm_connector_infoframe_funcs spd;\n};\n\nstruct drm_connector_hdmi_state {\n\tenum drm_hdmi_broadcast_rgb broadcast_rgb;\n\tstruct {\n\t\tstruct drm_connector_hdmi_infoframe avi;\n\t\tstruct drm_connector_hdmi_infoframe hdr_drm;\n\t\tstruct drm_connector_hdmi_infoframe spd;\n\t\tstruct drm_connector_hdmi_infoframe hdmi;\n\t} infoframes;\n\tbool is_limited_range;\n\tunsigned int output_bpc;\n\tenum hdmi_colorspace output_format;\n\tlong long unsigned int tmds_char_rate;\n};\n\nstruct drm_writeback_connector;\n\nstruct drm_writeback_job;\n\nstruct drm_connector_helper_funcs {\n\tint (*get_modes)(struct drm_connector *);\n\tint (*detect_ctx)(struct drm_connector *, struct drm_modeset_acquire_ctx *, bool);\n\tenum drm_mode_status (*mode_valid)(struct drm_connector *, const struct drm_display_mode *);\n\tint (*mode_valid_ctx)(struct drm_connector *, const struct drm_display_mode *, struct drm_modeset_acquire_ctx *, enum drm_mode_status *);\n\tstruct drm_encoder * (*best_encoder)(struct drm_connector *);\n\tstruct drm_encoder * (*atomic_best_encoder)(struct drm_connector *, struct drm_atomic_state *);\n\tint (*atomic_check)(struct drm_connector *, struct drm_atomic_state *);\n\tvoid (*atomic_commit)(struct drm_connector *, struct drm_atomic_state *);\n\tint (*prepare_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n\tvoid (*cleanup_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n\tvoid (*enable_hpd)(struct drm_connector *);\n\tvoid (*disable_hpd)(struct drm_connector *);\n};\n\nstruct drm_connector_list_iter {\n\tstruct drm_device *dev;\n\tstruct drm_connector *conn;\n};\n\nstruct drm_tv_connector_state {\n\tenum drm_mode_subconnector select_subconnector;\n\tenum drm_mode_subconnector subconnector;\n\tstruct drm_connector_tv_margins margins;\n\tunsigned int legacy_mode;\n\tunsigned int mode;\n\tunsigned int brightness;\n\tunsigned int contrast;\n\tunsigned int flicker_reduction;\n\tunsigned int overscan;\n\tunsigned int saturation;\n\tunsigned int hue;\n};\n\nstruct drm_connector_state {\n\tstruct drm_connector *connector;\n\tstruct drm_crtc *crtc;\n\tstruct drm_encoder *best_encoder;\n\tenum drm_link_status link_status;\n\tstruct drm_atomic_state *state;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_tv_connector_state tv;\n\tbool self_refresh_aware;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n\tunsigned int content_type;\n\tunsigned int hdcp_content_type;\n\tunsigned int scaling_mode;\n\tunsigned int content_protection;\n\tenum drm_colorspace colorspace;\n\tstruct drm_writeback_job *writeback_job;\n\tu8 max_requested_bpc;\n\tu8 max_bpc;\n\tenum drm_privacy_screen_status privacy_screen_sw_state;\n\tstruct drm_property_blob *hdr_output_metadata;\n\tstruct drm_connector_hdmi_state hdmi;\n};\n\nstruct drm_display_mode {\n\tint clock;\n\tu16 hdisplay;\n\tu16 hsync_start;\n\tu16 hsync_end;\n\tu16 htotal;\n\tu16 hskew;\n\tu16 vdisplay;\n\tu16 vsync_start;\n\tu16 vsync_end;\n\tu16 vtotal;\n\tu16 vscan;\n\tu32 flags;\n\tint crtc_clock;\n\tu16 crtc_hdisplay;\n\tu16 crtc_hblank_start;\n\tu16 crtc_hblank_end;\n\tu16 crtc_hsync_start;\n\tu16 crtc_hsync_end;\n\tu16 crtc_htotal;\n\tu16 crtc_hskew;\n\tu16 crtc_vdisplay;\n\tu16 crtc_vblank_start;\n\tu16 crtc_vblank_end;\n\tu16 crtc_vsync_start;\n\tu16 crtc_vsync_end;\n\tu16 crtc_vtotal;\n\tu16 width_mm;\n\tu16 height_mm;\n\tu8 type;\n\tbool expose_to_userspace;\n\tstruct list_head head;\n\tchar name[32];\n\tenum drm_mode_status status;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n};\n\nstruct drm_crtc_crc_entry;\n\nstruct drm_crtc_crc {\n\tspinlock_t lock;\n\tconst char *source;\n\tbool opened;\n\tbool overflow;\n\tstruct drm_crtc_crc_entry *entries;\n\tint head;\n\tint tail;\n\tsize_t values_cnt;\n\twait_queue_head_t wq;\n};\n\nstruct drm_crtc_funcs;\n\nstruct drm_crtc_helper_funcs;\n\nstruct drm_self_refresh_data;\n\nstruct drm_crtc {\n\tstruct drm_device *dev;\n\tstruct device_node *port;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tstruct drm_plane *primary;\n\tstruct drm_plane *cursor;\n\tunsigned int index;\n\tint cursor_x;\n\tint cursor_y;\n\tbool enabled;\n\tstruct drm_display_mode mode;\n\tstruct drm_display_mode hwmode;\n\tint x;\n\tint y;\n\tconst struct drm_crtc_funcs *funcs;\n\tuint32_t gamma_size;\n\tuint16_t *gamma_store;\n\tconst struct drm_crtc_helper_funcs *helper_private;\n\tstruct drm_object_properties properties;\n\tstruct drm_property *scaling_filter_property;\n\tstruct drm_property *sharpness_strength_property;\n\tstruct drm_crtc_state *state;\n\tstruct list_head commit_list;\n\tspinlock_t commit_lock;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_crtc_crc crc;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n\tstruct drm_self_refresh_data *self_refresh_data;\n};\n\nstruct drm_pending_vblank_event;\n\nstruct drm_crtc_commit {\n\tstruct drm_crtc *crtc;\n\tstruct kref ref;\n\tstruct completion flip_done;\n\tstruct completion hw_done;\n\tstruct completion cleanup_done;\n\tstruct list_head commit_entry;\n\tstruct drm_pending_vblank_event *event;\n\tbool abort_completion;\n};\n\nstruct drm_crtc_crc_entry {\n\tbool has_frame_counter;\n\tuint32_t frame;\n\tuint32_t crcs[10];\n};\n\nstruct drm_file;\n\nstruct drm_mode_set;\n\nstruct drm_crtc_funcs {\n\tvoid (*reset)(struct drm_crtc *);\n\tint (*cursor_set)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t);\n\tint (*cursor_set2)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t, int32_t, int32_t);\n\tint (*cursor_move)(struct drm_crtc *, int, int);\n\tint (*gamma_set)(struct drm_crtc *, u16 *, u16 *, u16 *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_crtc *);\n\tint (*set_config)(struct drm_mode_set *, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip_target)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*set_property)(struct drm_crtc *, struct drm_property *, uint64_t);\n\tstruct drm_crtc_state * (*atomic_duplicate_state)(struct drm_crtc *);\n\tvoid (*atomic_destroy_state)(struct drm_crtc *, struct drm_crtc_state *);\n\tint (*atomic_set_property)(struct drm_crtc *, struct drm_crtc_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_crtc *, const struct drm_crtc_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_crtc *);\n\tvoid (*early_unregister)(struct drm_crtc *);\n\tint (*set_crc_source)(struct drm_crtc *, const char *);\n\tint (*verify_crc_source)(struct drm_crtc *, const char *, size_t *);\n\tconst char * const * (*get_crc_sources)(struct drm_crtc *, size_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_crtc_state *);\n\tu32 (*get_vblank_counter)(struct drm_crtc *);\n\tint (*enable_vblank)(struct drm_crtc *);\n\tvoid (*disable_vblank)(struct drm_crtc *);\n\tbool (*get_vblank_timestamp)(struct drm_crtc *, int *, ktime_t *, bool);\n};\n\nstruct drm_crtc_get_sequence {\n\t__u32 crtc_id;\n\t__u32 active;\n\t__u64 sequence;\n\t__s64 sequence_ns;\n};\n\nstruct drm_crtc_helper_funcs {\n\tvoid (*dpms)(struct drm_crtc *, int);\n\tvoid (*prepare)(struct drm_crtc *);\n\tvoid (*commit)(struct drm_crtc *);\n\tenum drm_mode_status (*mode_valid)(struct drm_crtc *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_crtc *, const struct drm_display_mode *, struct drm_display_mode *);\n\tint (*mode_set)(struct drm_crtc *, struct drm_display_mode *, struct drm_display_mode *, int, int, struct drm_framebuffer *);\n\tvoid (*mode_set_nofb)(struct drm_crtc *);\n\tint (*mode_set_base)(struct drm_crtc *, int, int, struct drm_framebuffer *);\n\tvoid (*disable)(struct drm_crtc *);\n\tint (*atomic_check)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_begin)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_flush)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_crtc *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_crtc *, struct drm_atomic_state *);\n\tbool (*get_scanout_position)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n\tbool (*handle_vblank_timeout)(struct drm_crtc *);\n};\n\nstruct drm_crtc_queue_sequence {\n\t__u32 crtc_id;\n\t__u32 flags;\n\t__u64 sequence;\n\t__u64 user_data;\n};\n\nstruct drm_crtc_state {\n\tstruct drm_crtc *crtc;\n\tbool enable;\n\tbool active;\n\tbool planes_changed: 1;\n\tbool mode_changed: 1;\n\tbool active_changed: 1;\n\tbool connectors_changed: 1;\n\tbool zpos_changed: 1;\n\tbool color_mgmt_changed: 1;\n\tbool no_vblank;\n\tu32 plane_mask;\n\tu32 connector_mask;\n\tu32 encoder_mask;\n\tstruct drm_display_mode adjusted_mode;\n\tstruct drm_display_mode mode;\n\tstruct drm_property_blob *mode_blob;\n\tstruct drm_property_blob *degamma_lut;\n\tstruct drm_property_blob *ctm;\n\tstruct drm_property_blob *gamma_lut;\n\tu32 target_vblank;\n\tbool async_flip;\n\tbool vrr_enabled;\n\tbool self_refresh_active;\n\tenum drm_scaling_filter scaling_filter;\n\tu8 sharpness_strength;\n\tstruct drm_pending_vblank_event *event;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_debugfs_info {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n\tu32 driver_features;\n\tvoid *data;\n};\n\nstruct drm_debugfs_entry {\n\tstruct drm_device *dev;\n\tstruct drm_debugfs_info file;\n\tstruct list_head list;\n};\n\nstruct drm_dmi_panel_orientation_data {\n\tint width;\n\tint height;\n\tconst char * const *bios_dates;\n\tint orientation;\n};\n\nstruct drm_dp_as_sdp {\n\tunsigned char sdp_type;\n\tunsigned char revision;\n\tunsigned char length;\n\tint vtotal;\n\tint target_rr;\n\tint duration_incr_ms;\n\tint duration_decr_ms;\n\tbool target_rr_divider;\n\tenum operation_mode mode;\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n\tstruct regulator *bus_regulator;\n\tstruct dentry *debugfs;\n\tlong unsigned int addrs_in_instantiation[2];\n};\n\nstruct drm_dp_aux_cec {\n\tstruct mutex lock;\n\tstruct cec_adapter *adap;\n\tstruct drm_connector *connector;\n\tstruct delayed_work unregister_work;\n};\n\nstruct drm_dp_aux_msg;\n\nstruct drm_dp_aux {\n\tconst char *name;\n\tstruct i2c_adapter ddc;\n\tstruct device *dev;\n\tstruct drm_device *drm_dev;\n\tstruct drm_crtc *crtc;\n\tstruct mutex hw_mutex;\n\tstruct work_struct crc_work;\n\tu8 crc_count;\n\tssize_t (*transfer)(struct drm_dp_aux *, struct drm_dp_aux_msg *);\n\tint (*wait_hpd_asserted)(struct drm_dp_aux *, long unsigned int);\n\tunsigned int i2c_nack_count;\n\tunsigned int i2c_defer_count;\n\tstruct drm_dp_aux_cec cec;\n\tbool is_remote;\n\tbool powered_down;\n\tbool no_zero_sized;\n\tbool dpcd_probe_disabled;\n};\n\nstruct drm_dp_aux_msg {\n\tunsigned int address;\n\tu8 request;\n\tu8 reply;\n\tvoid *buffer;\n\tsize_t size;\n};\n\nstruct drm_dp_dpcd_ident {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tu8 hw_rev;\n\tu8 sw_major_rev;\n\tu8 sw_minor_rev;\n};\n\nstruct drm_dp_desc {\n\tstruct drm_dp_dpcd_ident ident;\n\tu32 quirks;\n};\n\nstruct drm_dp_mst_port;\n\nstruct drm_dp_mst_atomic_payload {\n\tstruct drm_dp_mst_port *port;\n\ts8 vc_start_slot;\n\tu8 vcpi;\n\tint time_slots;\n\tint pbn;\n\tbool delete: 1;\n\tbool dsc_enabled: 1;\n\tenum drm_dp_mst_payload_allocation payload_allocation_status;\n\tstruct list_head next;\n};\n\nstruct drm_dp_mst_topology_mgr;\n\nstruct drm_dp_mst_branch {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tstruct list_head destroy_next;\n\tu8 rad[8];\n\tu8 lct;\n\tint num_ports;\n\tstruct list_head ports;\n\tstruct drm_dp_mst_port *port_parent;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tbool link_address_sent;\n\tguid_t guid;\n};\n\nstruct drm_dp_mst_port {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tu8 port_num;\n\tbool input;\n\tbool mcs;\n\tbool ddps;\n\tu8 pdt;\n\tbool ldps;\n\tu8 dpcd_rev;\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n\tuint16_t full_pbn;\n\tstruct list_head next;\n\tstruct drm_dp_mst_branch *mstb;\n\tstruct drm_dp_aux aux;\n\tstruct drm_dp_aux *passthrough_aux;\n\tstruct drm_dp_mst_branch *parent;\n\tstruct drm_connector *connector;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tconst struct drm_edid *cached_edid;\n\tbool fec_capable;\n};\n\nstruct drm_dp_mst_topology_cbs {\n\tstruct drm_connector * (*add_connector)(struct drm_dp_mst_topology_mgr *, struct drm_dp_mst_port *, const char *);\n\tvoid (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *);\n};\n\nstruct drm_dp_sideband_msg_hdr {\n\tu8 lct;\n\tu8 lcr;\n\tu8 rad[8];\n\tbool broadcast;\n\tbool path_msg;\n\tu8 msg_len;\n\tbool somt;\n\tbool eomt;\n\tbool seqno;\n};\n\nstruct drm_dp_sideband_msg_rx {\n\tu8 chunk[48];\n\tu8 msg[256];\n\tu8 curchunk_len;\n\tu8 curchunk_idx;\n\tu8 curchunk_hdrlen;\n\tu8 curlen;\n\tbool have_somt;\n\tbool have_eomt;\n\tstruct drm_dp_sideband_msg_hdr initial_hdr;\n};\n\nstruct drm_dp_mst_topology_mgr {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tconst struct drm_dp_mst_topology_cbs *cbs;\n\tint max_dpcd_transaction_bytes;\n\tstruct drm_dp_aux *aux;\n\tint max_payloads;\n\tint conn_base_id;\n\tstruct drm_dp_sideband_msg_rx up_req_recv;\n\tstruct drm_dp_sideband_msg_rx down_rep_recv;\n\tstruct mutex lock;\n\tstruct mutex probe_lock;\n\tbool mst_state: 1;\n\tbool payload_id_table_cleared: 1;\n\tbool reset_rx_state: 1;\n\tu8 payload_count;\n\tu8 next_start_slot;\n\tstruct drm_dp_mst_branch *mst_primary;\n\tu8 dpcd[15];\n\tu8 sink_count;\n\tconst struct drm_private_state_funcs *funcs;\n\tstruct mutex qlock;\n\tstruct list_head tx_msg_downq;\n\twait_queue_head_t tx_waitq;\n\tstruct work_struct work;\n\tstruct work_struct tx_work;\n\tstruct list_head destroy_port_list;\n\tstruct list_head destroy_branch_device_list;\n\tstruct mutex delayed_destroy_lock;\n\tstruct workqueue_struct *delayed_destroy_wq;\n\tstruct work_struct delayed_destroy_work;\n\tstruct list_head up_req_list;\n\tstruct mutex up_req_lock;\n\tstruct work_struct up_req_work;\n};\n\nstruct drm_dp_mst_topology_state {\n\tstruct drm_private_state base;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tu32 pending_crtc_mask;\n\tstruct drm_crtc_commit **commit_deps;\n\tsize_t num_commit_deps;\n\tu32 payload_mask;\n\tstruct list_head payloads;\n\tu8 total_avail_slots;\n\tu8 start_slot;\n\tfixed20_12 pbn_div;\n};\n\nstruct drm_dp_sideband_msg_req_body {\n\tu8 req_type;\n\tunion ack_req u;\n};\n\nstruct drm_dp_pending_up_req {\n\tstruct drm_dp_sideband_msg_hdr hdr;\n\tstruct drm_dp_sideband_msg_req_body msg;\n\tstruct list_head next;\n};\n\nstruct drm_dp_phy_test_params {\n\tint link_rate;\n\tu8 num_lanes;\n\tu8 phy_pattern;\n\tu8 hbr2_reset[2];\n\tu8 custom80[10];\n\tbool enhanced_frame_cap;\n};\n\nstruct drm_dp_sideband_msg_reply_body {\n\tu8 reply_type;\n\tu8 req_type;\n\tunion ack_replies u;\n};\n\nstruct drm_dp_sideband_msg_tx {\n\tu8 msg[256];\n\tu8 chunk[48];\n\tu8 cur_offset;\n\tu8 cur_len;\n\tstruct drm_dp_mst_branch *dst;\n\tstruct list_head next;\n\tint seqno;\n\tint state;\n\tbool path_msg;\n\tstruct drm_dp_sideband_msg_reply_body reply;\n};\n\nstruct drm_dp_tunnel;\n\nstruct ref_tracker;\n\nstruct drm_dp_tunnel_ref {\n\tstruct drm_dp_tunnel *tunnel;\n\tstruct ref_tracker *tracker;\n};\n\nstruct drm_dp_vsc_sdp {\n\tunsigned char sdp_type;\n\tunsigned char revision;\n\tunsigned char length;\n\tenum dp_pixelformat pixelformat;\n\tenum dp_colorimetry colorimetry;\n\tint bpc;\n\tenum dp_dynamic_range dynamic_range;\n\tenum dp_content_type content_type;\n};\n\nstruct drm_fb_helper_surface_size;\n\nstruct drm_mode_create_dumb;\n\nstruct drm_ioctl_desc;\n\nstruct drm_driver {\n\tint (*load)(struct drm_device *, long unsigned int);\n\tint (*open)(struct drm_device *, struct drm_file *);\n\tvoid (*postclose)(struct drm_device *, struct drm_file *);\n\tvoid (*unload)(struct drm_device *);\n\tvoid (*release)(struct drm_device *);\n\tvoid (*master_set)(struct drm_device *, struct drm_file *, bool);\n\tvoid (*master_drop)(struct drm_device *, struct drm_file *);\n\tvoid (*debugfs_init)(struct drm_minor *);\n\tstruct drm_gem_object * (*gem_create_object)(struct drm_device *, size_t);\n\tint (*prime_handle_to_fd)(struct drm_device *, struct drm_file *, uint32_t, uint32_t, int *);\n\tint (*prime_fd_to_handle)(struct drm_device *, struct drm_file *, int, uint32_t *);\n\tstruct drm_gem_object * (*gem_prime_import)(struct drm_device *, struct dma_buf *);\n\tstruct drm_gem_object * (*gem_prime_import_sg_table)(struct drm_device *, struct dma_buf_attachment *, struct sg_table *);\n\tint (*dumb_create)(struct drm_file *, struct drm_device *, struct drm_mode_create_dumb *);\n\tint (*dumb_map_offset)(struct drm_file *, struct drm_device *, uint32_t, uint64_t *);\n\tint (*fbdev_probe)(struct drm_fb_helper *, struct drm_fb_helper_surface_size *);\n\tvoid (*show_fdinfo)(struct drm_printer *, struct drm_file *);\n\tint major;\n\tint minor;\n\tint patchlevel;\n\tchar *name;\n\tchar *desc;\n\tu32 driver_features;\n\tconst struct drm_ioctl_desc *ioctls;\n\tint num_ioctls;\n\tconst struct file_operations *fops;\n};\n\nstruct drm_dsc_rc_range_parameters {\n\tu8 range_min_qp;\n\tu8 range_max_qp;\n\tu8 range_bpg_offset;\n};\n\nstruct drm_dsc_config {\n\tu8 line_buf_depth;\n\tu8 bits_per_component;\n\tbool convert_rgb;\n\tu8 slice_count;\n\tu16 slice_width;\n\tu16 slice_height;\n\tbool simple_422;\n\tu16 pic_width;\n\tu16 pic_height;\n\tu8 rc_tgt_offset_high;\n\tu8 rc_tgt_offset_low;\n\tu16 bits_per_pixel;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_quant_incr_limit0;\n\tu16 initial_xmit_delay;\n\tu16 initial_dec_delay;\n\tbool block_pred_enable;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu16 rc_buf_thresh[14];\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n\tu16 rc_model_size;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 initial_scale_value;\n\tu16 scale_decrement_interval;\n\tu16 scale_increment_interval;\n\tu16 nfl_bpg_offset;\n\tu16 slice_bpg_offset;\n\tu16 final_offset;\n\tbool vbr_enable;\n\tu8 mux_word_size;\n\tu16 slice_chunk_size;\n\tu16 rc_bits;\n\tu8 dsc_version_minor;\n\tu8 dsc_version_major;\n\tbool native_422;\n\tbool native_420;\n\tu8 second_line_bpg_offset;\n\tu16 nsl_bpg_offset;\n\tu16 second_line_offset_adj;\n};\n\nstruct drm_dsc_picture_parameter_set {\n\tu8 dsc_version;\n\tu8 pps_identifier;\n\tu8 pps_reserved;\n\tu8 pps_3;\n\tu8 pps_4;\n\tu8 bits_per_pixel_low;\n\t__be16 pic_height;\n\t__be16 pic_width;\n\t__be16 slice_height;\n\t__be16 slice_width;\n\t__be16 chunk_size;\n\tu8 initial_xmit_delay_high;\n\tu8 initial_xmit_delay_low;\n\t__be16 initial_dec_delay;\n\tu8 pps20_reserved;\n\tu8 initial_scale_value;\n\t__be16 scale_increment_interval;\n\tu8 scale_decrement_interval_high;\n\tu8 scale_decrement_interval_low;\n\tu8 pps26_reserved;\n\tu8 first_line_bpg_offset;\n\t__be16 nfl_bpg_offset;\n\t__be16 slice_bpg_offset;\n\t__be16 initial_offset;\n\t__be16 final_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\t__be16 rc_model_size;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_tgt_offset;\n\tu8 rc_buf_thresh[14];\n\t__be16 rc_range_parameters[15];\n\tu8 native_422_420;\n\tu8 second_line_bpg_offset;\n\t__be16 nsl_bpg_offset;\n\t__be16 second_line_offset_adj;\n\tu32 pps_long_94_reserved;\n\tu32 pps_long_98_reserved;\n\tu32 pps_long_102_reserved;\n\tu32 pps_long_106_reserved;\n\tu32 pps_long_110_reserved;\n\tu32 pps_long_114_reserved;\n\tu32 pps_long_118_reserved;\n\tu32 pps_long_122_reserved;\n\t__be16 pps_short_126_reserved;\n} __attribute__((packed));\n\nstruct drm_dsc_pps_infoframe {\n\tstruct dp_sdp_header pps_header;\n\tstruct drm_dsc_picture_parameter_set pps_payload;\n};\n\nstruct edid;\n\nstruct drm_edid {\n\tsize_t size;\n\tconst struct edid *edid;\n};\n\nstruct drm_edid_match_closure {\n\tconst struct drm_edid_ident *ident;\n\tbool matched;\n};\n\nstruct drm_edid_product_id {\n\t__be16 manufacturer_name;\n\t__le16 product_code;\n\t__le32 serial_number;\n\tu8 week_of_manufacture;\n\tu8 year_of_manufacture;\n} __attribute__((packed));\n\nstruct drm_encoder_funcs;\n\nstruct drm_encoder_helper_funcs;\n\nstruct drm_encoder {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tint encoder_type;\n\tunsigned int index;\n\tuint32_t possible_crtcs;\n\tuint32_t possible_clones;\n\tstruct drm_crtc *crtc;\n\tstruct list_head bridge_chain;\n\tconst struct drm_encoder_funcs *funcs;\n\tconst struct drm_encoder_helper_funcs *helper_private;\n\tstruct dentry *debugfs_entry;\n};\n\nstruct drm_encoder_funcs {\n\tvoid (*reset)(struct drm_encoder *);\n\tvoid (*destroy)(struct drm_encoder *);\n\tint (*late_register)(struct drm_encoder *);\n\tvoid (*early_unregister)(struct drm_encoder *);\n\tvoid (*debugfs_init)(struct drm_encoder *, struct dentry *);\n};\n\nstruct drm_encoder_helper_funcs {\n\tvoid (*dpms)(struct drm_encoder *, int);\n\tenum drm_mode_status (*mode_valid)(struct drm_encoder *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_encoder *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*prepare)(struct drm_encoder *);\n\tvoid (*commit)(struct drm_encoder *);\n\tvoid (*mode_set)(struct drm_encoder *, struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*atomic_mode_set)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n\tenum drm_connector_status (*detect)(struct drm_encoder *, struct drm_connector *);\n\tvoid (*atomic_disable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*disable)(struct drm_encoder *);\n\tvoid (*enable)(struct drm_encoder *);\n\tint (*atomic_check)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n};\n\nstruct drm_event {\n\t__u32 type;\n\t__u32 length;\n};\n\nstruct drm_event_crtc_sequence {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__s64 time_ns;\n\t__u64 sequence;\n};\n\nstruct drm_event_vblank {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__u32 tv_sec;\n\t__u32 tv_usec;\n\t__u32 sequence;\n\t__u32 crtc_id;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n};\n\nstruct drm_exec {\n\tu32 flags;\n\tstruct ww_acquire_ctx ticket;\n\tunsigned int num_objects;\n\tunsigned int max_objects;\n\tstruct drm_gem_object **objects;\n\tstruct drm_gem_object *contended;\n\tstruct drm_gem_object *prelocked;\n};\n\nstruct drm_prime_file_private {\n\tstruct mutex lock;\n\tstruct rb_root dmabufs;\n\tstruct rb_root handles;\n};\n\nstruct drm_file {\n\tbool authenticated;\n\tbool stereo_allowed;\n\tbool universal_planes;\n\tbool atomic;\n\tbool aspect_ratio_allowed;\n\tbool writeback_connectors;\n\tbool plane_color_pipeline;\n\tbool was_master;\n\tbool is_master;\n\tbool supports_virtualized_cursor_plane;\n\tstruct drm_master *master;\n\tspinlock_t master_lookup_lock;\n\tstruct pid *pid;\n\tu64 client_id;\n\tdrm_magic_t magic;\n\tstruct list_head lhead;\n\tstruct drm_minor *minor;\n\tstruct idr object_idr;\n\tspinlock_t table_lock;\n\tstruct xarray syncobj_xa;\n\tstruct file *filp;\n\tvoid *driver_priv;\n\tstruct list_head fbs;\n\tstruct mutex fbs_lock;\n\tstruct list_head blobs;\n\twait_queue_head_t event_wait;\n\tstruct list_head pending_event_list;\n\tstruct list_head event_list;\n\tint event_space;\n\tstruct mutex event_read_lock;\n\tstruct drm_prime_file_private prime;\n\tconst char *client_name;\n\tstruct mutex client_name_lock;\n\tstruct dentry *debugfs_client;\n};\n\nstruct drm_flip_task {\n\tstruct list_head node;\n\tvoid *data;\n};\n\nstruct drm_flip_work;\n\ntypedef void (*drm_flip_func_t)(struct drm_flip_work *, void *);\n\nstruct drm_flip_work {\n\tconst char *name;\n\tdrm_flip_func_t func;\n\tstruct work_struct worker;\n\tstruct list_head queued;\n\tstruct list_head commited;\n\tspinlock_t lock;\n};\n\nstruct drm_format_conv_state {\n\tstruct {\n\t\tvoid *mem;\n\t\tsize_t size;\n\t\tbool preallocated;\n\t} tmp;\n};\n\nstruct drm_format_info {\n\tu32 format;\n\tu8 depth;\n\tu8 num_planes;\n\tunion {\n\t\tu8 cpp[4];\n\t\tu8 char_per_block[4];\n\t};\n\tu8 block_w[4];\n\tu8 block_h[4];\n\tu8 hsub;\n\tu8 vsub;\n\tbool has_alpha;\n\tbool is_yuv;\n\tbool is_color_indexed;\n};\n\nstruct drm_format_modifier {\n\t__u64 formats;\n\t__u32 offset;\n\t__u32 pad;\n\t__u64 modifier;\n};\n\nstruct drm_format_modifier_blob {\n\t__u32 version;\n\t__u32 flags;\n\t__u32 count_formats;\n\t__u32 formats_offset;\n\t__u32 count_modifiers;\n\t__u32 modifiers_offset;\n};\n\nstruct drm_framebuffer_funcs {\n\tvoid (*destroy)(struct drm_framebuffer *);\n\tint (*create_handle)(struct drm_framebuffer *, struct drm_file *, unsigned int *);\n\tint (*dirty)(struct drm_framebuffer *, struct drm_file *, unsigned int, unsigned int, struct drm_clip_rect *, unsigned int);\n};\n\nstruct drm_gem_change_handle {\n\t__u32 handle;\n\t__u32 new_handle;\n};\n\nstruct drm_gem_close {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_gem_flink {\n\t__u32 handle;\n\t__u32 name;\n};\n\nstruct drm_gem_lru {\n\tstruct mutex *lock;\n\tlong int count;\n\tstruct list_head list;\n};\n\nstruct drm_vma_offset_node {\n\trwlock_t vm_lock;\n\tstruct drm_mm_node vm_node;\n\tstruct rb_root vm_files;\n\tvoid *driver_private;\n};\n\nstruct drm_gem_object_funcs;\n\nstruct drm_gem_object {\n\tstruct kref refcount;\n\tunsigned int handle_count;\n\tstruct drm_device *dev;\n\tstruct file *filp;\n\tstruct drm_vma_offset_node vma_node;\n\tsize_t size;\n\tint name;\n\tstruct dma_buf *dma_buf;\n\tstruct dma_buf_attachment *import_attach;\n\tstruct dma_resv *resv;\n\tstruct dma_resv _resv;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct mutex lock;\n\t} gpuva;\n\tconst struct drm_gem_object_funcs *funcs;\n\tstruct list_head lru_node;\n\tstruct drm_gem_lru *lru;\n};\n\nstruct drm_gem_object_funcs {\n\tvoid (*free)(struct drm_gem_object *);\n\tint (*open)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*close)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*print_info)(struct drm_printer *, unsigned int, const struct drm_gem_object *);\n\tstruct dma_buf * (*export)(struct drm_gem_object *, int);\n\tint (*pin)(struct drm_gem_object *);\n\tvoid (*unpin)(struct drm_gem_object *);\n\tstruct sg_table * (*get_sg_table)(struct drm_gem_object *);\n\tint (*vmap)(struct drm_gem_object *, struct iosys_map *);\n\tvoid (*vunmap)(struct drm_gem_object *, struct iosys_map *);\n\tint (*mmap)(struct drm_gem_object *, struct vm_area_struct *);\n\tint (*evict)(struct drm_gem_object *);\n\tenum drm_gem_object_status (*status)(struct drm_gem_object *);\n\tsize_t (*rss)(struct drm_gem_object *);\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct drm_gem_open {\n\t__u32 name;\n\t__u32 handle;\n\t__u64 size;\n};\n\nstruct drm_gem_shmem_object {\n\tstruct drm_gem_object base;\n\tstruct page **pages;\n\trefcount_t pages_use_count;\n\trefcount_t pages_pin_count;\n\tint madv;\n\tstruct list_head madv_list;\n\tstruct sg_table *sgt;\n\tvoid *vaddr;\n\trefcount_t vmap_use_count;\n\tbool pages_mark_dirty_on_put: 1;\n\tbool pages_mark_accessed_on_put: 1;\n\tbool map_wc: 1;\n};\n\nstruct drm_get_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_gpuvm;\n\nstruct drm_gpuvm_bo;\n\nstruct drm_gpuva {\n\tstruct drm_gpuvm *vm;\n\tstruct drm_gpuvm_bo *vm_bo;\n\tenum drm_gpuva_flags flags;\n\tstruct {\n\t\tu64 addr;\n\t\tu64 range;\n\t} va;\n\tstruct {\n\t\tu64 offset;\n\t\tstruct drm_gem_object *obj;\n\t\tstruct list_head entry;\n\t} gem;\n\tstruct {\n\t\tstruct rb_node node;\n\t\tstruct list_head entry;\n\t\tu64 __subtree_last;\n\t} rb;\n};\n\nstruct drm_gpuva_op_map {\n\tstruct {\n\t\tu64 addr;\n\t\tu64 range;\n\t} va;\n\tstruct {\n\t\tu64 offset;\n\t\tstruct drm_gem_object *obj;\n\t} gem;\n};\n\nstruct drm_gpuva_op_unmap;\n\nstruct drm_gpuva_op_remap {\n\tstruct drm_gpuva_op_map *prev;\n\tstruct drm_gpuva_op_map *next;\n\tstruct drm_gpuva_op_unmap *unmap;\n};\n\nstruct drm_gpuva_op_unmap {\n\tstruct drm_gpuva *va;\n\tbool keep;\n};\n\nstruct drm_gpuva_op_prefetch {\n\tstruct drm_gpuva *va;\n};\n\nstruct drm_gpuva_op {\n\tstruct list_head entry;\n\tenum drm_gpuva_op_type op;\n\tunion {\n\t\tstruct drm_gpuva_op_map map;\n\t\tstruct drm_gpuva_op_remap remap;\n\t\tstruct drm_gpuva_op_unmap unmap;\n\t\tstruct drm_gpuva_op_prefetch prefetch;\n\t};\n};\n\nstruct drm_gpuvm_ops;\n\nstruct drm_gpuvm {\n\tconst char *name;\n\tenum drm_gpuvm_flags flags;\n\tstruct drm_device *drm;\n\tu64 mm_start;\n\tu64 mm_range;\n\tstruct {\n\t\tstruct rb_root_cached tree;\n\t\tstruct list_head list;\n\t} rb;\n\tstruct kref kref;\n\tstruct drm_gpuva kernel_alloc_node;\n\tconst struct drm_gpuvm_ops *ops;\n\tstruct drm_gem_object *r_obj;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct list_head *local_list;\n\t\tspinlock_t lock;\n\t} extobj;\n\tstruct {\n\t\tstruct list_head list;\n\t\tstruct list_head *local_list;\n\t\tspinlock_t lock;\n\t} evict;\n\tstruct llist_head bo_defer;\n};\n\nstruct drm_gpuvm_bo {\n\tstruct drm_gpuvm *vm;\n\tstruct drm_gem_object *obj;\n\tbool evicted;\n\tstruct kref kref;\n\tstruct {\n\t\tstruct list_head gpuva;\n\t\tstruct {\n\t\t\tstruct list_head gem;\n\t\t\tstruct list_head extobj;\n\t\t\tstruct list_head evict;\n\t\t\tstruct llist_node bo_defer;\n\t\t} entry;\n\t} list;\n};\n\nstruct drm_gpuvm_ops {\n\tvoid (*vm_free)(struct drm_gpuvm *);\n\tstruct drm_gpuva_op * (*op_alloc)(void);\n\tvoid (*op_free)(struct drm_gpuva_op *);\n\tstruct drm_gpuvm_bo * (*vm_bo_alloc)(void);\n\tvoid (*vm_bo_free)(struct drm_gpuvm_bo *);\n\tint (*vm_bo_validate)(struct drm_gpuvm_bo *, struct drm_exec *);\n\tint (*sm_step_map)(struct drm_gpuva_op *, void *);\n\tint (*sm_step_remap)(struct drm_gpuva_op *, void *);\n\tint (*sm_step_unmap)(struct drm_gpuva_op *, void *);\n};\n\nstruct drm_hdmi_acr_n_cts_entry {\n\tunsigned int n;\n\tunsigned int cts;\n};\n\nstruct drm_hdmi_acr_data {\n\tlong unsigned int tmds_clock_khz;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_32k;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_44k1;\n\tstruct drm_hdmi_acr_n_cts_entry n_cts_48k;\n};\n\nstruct drm_i915_clock_gating_funcs {\n\tvoid (*init_clock_gating)(struct drm_i915_private *);\n};\n\nstruct drm_i915_cmd_descriptor {\n\tu32 flags;\n\tstruct {\n\t\tu32 value;\n\t\tu32 mask;\n\t} cmd;\n\tunion {\n\t\tu32 fixed;\n\t\tu32 mask;\n\t} length;\n\tstruct {\n\t\tu32 offset;\n\t\tu32 mask;\n\t\tu32 step;\n\t} reg;\n\tstruct {\n\t\tu32 offset;\n\t\tu32 mask;\n\t\tu32 expected;\n\t\tu32 condition_offset;\n\t\tu32 condition_mask;\n\t} bits[3];\n};\n\nstruct drm_i915_cmd_table {\n\tconst struct drm_i915_cmd_descriptor *table;\n\tint count;\n};\n\nstruct i915_engine_class_instance {\n\t__u16 engine_class;\n\t__u16 engine_instance;\n};\n\nstruct drm_i915_engine_info {\n\tstruct i915_engine_class_instance engine;\n\t__u32 rsvd0;\n\t__u64 flags;\n\t__u64 capabilities;\n\t__u16 logical_instance;\n\t__u16 rsvd1[3];\n\t__u64 rsvd2[3];\n};\n\nstruct drm_i915_error_state_buf {\n\tstruct drm_i915_private *i915;\n\tstruct scatterlist *sgl;\n\tstruct scatterlist *cur;\n\tstruct scatterlist *end;\n\tchar *buf;\n\tsize_t bytes;\n\tsize_t size;\n\tloff_t iter;\n\tint err;\n};\n\nstruct i915_drm_client;\n\nstruct drm_i915_file_private {\n\tstruct drm_i915_private *i915;\n\tunion {\n\t\tstruct drm_file *file;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct mutex proto_context_lock;\n\tstruct xarray proto_context_xa;\n\tstruct xarray context_xa;\n\tstruct xarray vm_xa;\n\tunsigned int bsd_engine;\n\tatomic_t ban_score;\n\tlong unsigned int hang_timestamp;\n\tstruct i915_drm_client *client;\n};\n\nstruct drm_i915_gem_busy {\n\t__u32 handle;\n\t__u32 busy;\n};\n\nstruct drm_i915_gem_caching {\n\t__u32 handle;\n\t__u32 caching;\n};\n\nstruct drm_i915_gem_context_create_ext {\n\t__u32 ctx_id;\n\t__u32 flags;\n\t__u64 extensions;\n};\n\nstruct i915_user_extension {\n\t__u64 next_extension;\n\t__u32 name;\n\t__u32 flags;\n\t__u32 rsvd[4];\n};\n\nstruct drm_i915_gem_context_param {\n\t__u32 ctx_id;\n\t__u32 size;\n\t__u64 param;\n\t__u64 value;\n};\n\nstruct drm_i915_gem_context_create_ext_setparam {\n\tstruct i915_user_extension base;\n\tstruct drm_i915_gem_context_param param;\n};\n\nstruct drm_i915_gem_context_destroy {\n\t__u32 ctx_id;\n\t__u32 pad;\n};\n\nstruct drm_i915_gem_context_param_sseu {\n\tstruct i915_engine_class_instance engine;\n\t__u32 flags;\n\t__u64 slice_mask;\n\t__u64 subslice_mask;\n\t__u16 min_eus_per_subslice;\n\t__u16 max_eus_per_subslice;\n\t__u32 rsvd;\n};\n\nstruct drm_i915_gem_create {\n\t__u64 size;\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_i915_gem_create_ext {\n\t__u64 size;\n\t__u32 handle;\n\t__u32 flags;\n\t__u64 extensions;\n};\n\nstruct drm_i915_gem_create_ext_memory_regions {\n\tstruct i915_user_extension base;\n\t__u32 pad;\n\t__u32 num_regions;\n\t__u64 regions;\n};\n\nstruct drm_i915_gem_create_ext_protected_content {\n\tstruct i915_user_extension base;\n\t__u32 flags;\n};\n\nstruct drm_i915_gem_create_ext_set_pat {\n\tstruct i915_user_extension base;\n\t__u32 pat_index;\n\t__u32 rsvd;\n};\n\nstruct drm_i915_gem_exec_fence {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_i915_gem_exec_object2 {\n\t__u32 handle;\n\t__u32 relocation_count;\n\t__u64 relocs_ptr;\n\t__u64 alignment;\n\t__u64 offset;\n\t__u64 flags;\n\tunion {\n\t\t__u64 rsvd1;\n\t\t__u64 pad_to_size;\n\t};\n\t__u64 rsvd2;\n};\n\nstruct drm_i915_gem_execbuffer2 {\n\t__u64 buffers_ptr;\n\t__u32 buffer_count;\n\t__u32 batch_start_offset;\n\t__u32 batch_len;\n\t__u32 DR1;\n\t__u32 DR4;\n\t__u32 num_cliprects;\n\t__u64 cliprects_ptr;\n\t__u64 flags;\n\t__u64 rsvd1;\n\t__u64 rsvd2;\n};\n\nstruct drm_i915_gem_execbuffer_ext_timeline_fences {\n\tstruct i915_user_extension base;\n\t__u64 fence_count;\n\t__u64 handles_ptr;\n\t__u64 values_ptr;\n};\n\nstruct drm_i915_gem_get_aperture {\n\t__u64 aper_size;\n\t__u64 aper_available_size;\n};\n\nstruct drm_i915_gem_get_tiling {\n\t__u32 handle;\n\t__u32 tiling_mode;\n\t__u32 swizzle_mode;\n\t__u32 phys_swizzle_mode;\n};\n\nstruct drm_i915_gem_madvise {\n\t__u32 handle;\n\t__u32 madv;\n\t__u32 retained;\n};\n\nstruct drm_i915_gem_memory_class_instance {\n\t__u16 memory_class;\n\t__u16 memory_instance;\n};\n\nstruct drm_i915_gem_mmap {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 addr_ptr;\n\t__u64 flags;\n};\n\nstruct drm_i915_gem_mmap_offset {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 flags;\n\t__u64 extensions;\n};\n\nstruct ttm_device;\n\nstruct ttm_resource;\n\nstruct ttm_tt;\n\nstruct ttm_lru_bulk_move;\n\nstruct ttm_buffer_object {\n\tstruct drm_gem_object base;\n\tstruct ttm_device *bdev;\n\tenum ttm_bo_type type;\n\tuint32_t page_alignment;\n\tvoid (*destroy)(struct ttm_buffer_object *);\n\tstruct kref kref;\n\tstruct ttm_resource *resource;\n\tstruct ttm_tt *ttm;\n\tbool deleted;\n\tstruct ttm_lru_bulk_move *bulk_move;\n\tunsigned int priority;\n\tunsigned int pin_count;\n\tstruct work_struct delayed_delete;\n\tstruct sg_table *sg;\n};\n\nstruct i915_page_sizes {\n\tunsigned int phys;\n\tunsigned int sg;\n};\n\nstruct i915_gem_object_page_iter {\n\tstruct scatterlist *sg_pos;\n\tunsigned int sg_idx;\n\tstruct xarray radix;\n\tstruct mutex lock;\n};\n\nstruct interval_tree_node {\n\tstruct rb_node rb;\n\tlong unsigned int start;\n\tlong unsigned int last;\n\tlong unsigned int __subtree_last;\n};\n\nstruct mmu_interval_notifier_ops;\n\nstruct mmu_interval_notifier {\n\tstruct interval_tree_node interval_tree;\n\tconst struct mmu_interval_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct hlist_node deferred_item;\n\tlong unsigned int invalidate_seq;\n};\n\nstruct i915_gem_userptr {\n\tuintptr_t ptr;\n\tlong unsigned int notifier_seq;\n\tstruct mmu_interval_notifier notifier;\n\tstruct page **pvec;\n\tint page_ref;\n};\n\nstruct drm_i915_gem_object_ops;\n\nstruct i915_address_space;\n\nstruct i915_frontbuffer;\n\nstruct i915_refct_sgt;\n\nstruct drm_i915_gem_object {\n\tunion {\n\t\tstruct drm_gem_object base;\n\t\tstruct ttm_buffer_object __do_not_access;\n\t};\n\tconst struct drm_i915_gem_object_ops *ops;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head list;\n\t\tstruct rb_root tree;\n\t} vma;\n\tstruct list_head lut_list;\n\tspinlock_t lut_lock;\n\tstruct list_head obj_link;\n\tstruct i915_address_space *shares_resv_from;\n\tstruct i915_drm_client *client;\n\tstruct list_head client_link;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct llist_node freed;\n\t};\n\tunsigned int userfault_count;\n\tstruct list_head userfault_link;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct rb_root offsets;\n\t} mmo;\n\tlong unsigned int flags;\n\tunsigned int mem_flags;\n\tunsigned int pat_index: 6;\n\tunsigned int pat_set_by_user: 1;\n\tunsigned int cache_coherent: 2;\n\tunsigned int cache_dirty: 1;\n\tunsigned int is_dpt: 1;\n\tu16 read_domains;\n\tu16 write_domain;\n\tstruct i915_frontbuffer *frontbuffer;\n\tunsigned int tiling_and_stride;\n\tstruct {\n\t\tatomic_t pages_pin_count;\n\t\tatomic_t shrink_pin;\n\t\tbool ttm_shrinkable;\n\t\tbool unknown_state;\n\t\tstruct intel_memory_region **placements;\n\t\tint n_placements;\n\t\tstruct intel_memory_region *region;\n\t\tstruct ttm_resource *res;\n\t\tstruct list_head region_link;\n\t\tstruct i915_refct_sgt *rsgt;\n\t\tstruct sg_table *pages;\n\t\tvoid *mapping;\n\t\tstruct i915_page_sizes page_sizes;\n\t\tstruct i915_gem_object_page_iter get_page;\n\t\tstruct i915_gem_object_page_iter get_dma_page;\n\t\tstruct list_head link;\n\t\tunsigned int madv: 2;\n\t\tbool dirty: 1;\n\t\tu32 tlb[2];\n\t} mm;\n\tstruct {\n\t\tstruct i915_refct_sgt *cached_io_rsgt;\n\t\tstruct i915_gem_object_page_iter get_io_page;\n\t\tstruct drm_i915_gem_object *backup;\n\t\tbool created: 1;\n\t} ttm;\n\tu32 pxp_key_instance;\n\tlong unsigned int *bit_17;\n\tunion {\n\t\tstruct i915_gem_userptr userptr;\n\t\tstruct drm_mm_node *stolen;\n\t\tresource_size_t bo_offset;\n\t\tlong unsigned int scratch;\n\t\tu64 encode;\n\t\tvoid *gvt_info;\n\t};\n};\n\nstruct drm_i915_gem_pread;\n\nstruct drm_i915_gem_pwrite;\n\nstruct drm_i915_gem_object_ops {\n\tunsigned int flags;\n\tint (*get_pages)(struct drm_i915_gem_object *);\n\tvoid (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);\n\tint (*truncate)(struct drm_i915_gem_object *);\n\tint (*shrink)(struct drm_i915_gem_object *, unsigned int);\n\tint (*pread)(struct drm_i915_gem_object *, const struct drm_i915_gem_pread *);\n\tint (*pwrite)(struct drm_i915_gem_object *, const struct drm_i915_gem_pwrite *);\n\tu64 (*mmap_offset)(struct drm_i915_gem_object *);\n\tvoid (*unmap_virtual)(struct drm_i915_gem_object *);\n\tint (*dmabuf_export)(struct drm_i915_gem_object *);\n\tvoid (*adjust_lru)(struct drm_i915_gem_object *);\n\tvoid (*delayed_free)(struct drm_i915_gem_object *);\n\tint (*migrate)(struct drm_i915_gem_object *, struct intel_memory_region *, unsigned int);\n\tvoid (*release)(struct drm_i915_gem_object *);\n\tconst struct vm_operations_struct *mmap_ops;\n\tconst char *name;\n};\n\nstruct drm_i915_gem_pread {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_gem_pwrite {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_gem_relocation_entry {\n\t__u32 target_handle;\n\t__u32 delta;\n\t__u64 offset;\n\t__u64 presumed_offset;\n\t__u32 read_domains;\n\t__u32 write_domain;\n};\n\nstruct drm_i915_gem_set_domain {\n\t__u32 handle;\n\t__u32 read_domains;\n\t__u32 write_domain;\n};\n\nstruct drm_i915_gem_set_tiling {\n\t__u32 handle;\n\t__u32 tiling_mode;\n\t__u32 stride;\n\t__u32 swizzle_mode;\n};\n\nstruct drm_i915_gem_sw_finish {\n\t__u32 handle;\n};\n\nstruct drm_i915_gem_userptr {\n\t__u64 user_ptr;\n\t__u64 user_size;\n\t__u32 flags;\n\t__u32 handle;\n};\n\nstruct drm_i915_gem_vm_control {\n\t__u64 extensions;\n\t__u32 flags;\n\t__u32 vm_id;\n};\n\nstruct drm_i915_gem_wait {\n\t__u32 bo_handle;\n\t__u32 flags;\n\t__s64 timeout_ns;\n};\n\nstruct drm_i915_get_pipe_from_crtc_id {\n\t__u32 crtc_id;\n\t__u32 pipe;\n};\n\nstruct drm_i915_getparam {\n\t__s32 param;\n\tint *value;\n};\n\ntypedef struct drm_i915_getparam drm_i915_getparam_t;\n\nstruct drm_i915_getparam32 {\n\ts32 param;\n\tu32 value;\n};\n\nstruct drm_i915_memory_region_info {\n\tstruct drm_i915_gem_memory_class_instance region;\n\t__u32 rsvd0;\n\t__u64 probed_size;\n\t__u64 unallocated_size;\n\tunion {\n\t\t__u64 rsvd1[8];\n\t\tstruct {\n\t\t\t__u64 probed_cpu_visible_size;\n\t\t\t__u64 unallocated_cpu_visible_size;\n\t\t};\n\t};\n};\n\nstruct drm_i915_mocs_entry {\n\tu32 control_value;\n\tu16 l3cc_value;\n\tu16 used;\n};\n\nstruct drm_i915_mocs_table {\n\tunsigned int size;\n\tunsigned int n_entries;\n\tconst struct drm_i915_mocs_entry *table;\n\tu8 uc_index;\n\tu8 wb_index;\n\tu8 unused_entries_index;\n};\n\nstruct drm_i915_perf_oa_config {\n\tchar uuid[36];\n\t__u32 n_mux_regs;\n\t__u32 n_boolean_regs;\n\t__u32 n_flex_regs;\n\t__u64 mux_regs_ptr;\n\t__u64 boolean_regs_ptr;\n\t__u64 flex_regs_ptr;\n};\n\nstruct drm_i915_perf_open_param {\n\t__u32 flags;\n\t__u32 num_properties;\n\t__u64 properties_ptr;\n};\n\nstruct drm_i915_perf_record_header {\n\t__u32 type;\n\t__u16 pad;\n\t__u16 size;\n};\n\nstruct i915_params {\n\tint modeset;\n\tint enable_guc;\n\tint guc_log_level;\n\tchar *guc_firmware_path;\n\tchar *huc_firmware_path;\n\tchar *gsc_firmware_path;\n\tbool memtest;\n\tint mmio_debug;\n\tunsigned int reset;\n\tchar *force_probe;\n\tunsigned int request_timeout_ms;\n\tunsigned int lmem_size;\n\tunsigned int lmem_bar_size;\n\tbool enable_hangcheck;\n\tbool error_capture;\n\tbool enable_gvt;\n\tbool enable_debug_only_api;\n};\n\nstruct intel_ip_version {\n\tu8 ver;\n\tu8 rel;\n\tu8 step;\n};\n\nstruct intel_step_info {\n\tu8 graphics_step;\n\tu8 media_step;\n};\n\nstruct intel_runtime_info {\n\tstruct {\n\t\tstruct intel_ip_version ip;\n\t} graphics;\n\tstruct {\n\t\tstruct intel_ip_version ip;\n\t} media;\n\tu32 platform_mask[2];\n\tu16 device_id;\n\tstruct intel_step_info step;\n\tunsigned int page_sizes;\n\tenum intel_ppgtt_type ppgtt_type;\n\tunsigned int ppgtt_size;\n\tbool has_pooled_eu;\n};\n\nstruct intel_driver_caps {\n\tunsigned int scheduler;\n\tbool has_logical_contexts: 1;\n};\n\nstruct i915_dsm {\n\tstruct resource stolen;\n\tstruct resource reserved;\n\tresource_size_t usable_size;\n};\n\nstruct intel_uncore;\n\nstruct intel_uncore_funcs {\n\tenum forcewake_domains (*read_fw_domains)(struct intel_uncore *, i915_reg_t);\n\tenum forcewake_domains (*write_fw_domains)(struct intel_uncore *, i915_reg_t);\n\tu8 (*mmio_readb)(struct intel_uncore *, i915_reg_t, bool);\n\tu16 (*mmio_readw)(struct intel_uncore *, i915_reg_t, bool);\n\tu32 (*mmio_readl)(struct intel_uncore *, i915_reg_t, bool);\n\tu64 (*mmio_readq)(struct intel_uncore *, i915_reg_t, bool);\n\tvoid (*mmio_writeb)(struct intel_uncore *, i915_reg_t, u8, bool);\n\tvoid (*mmio_writew)(struct intel_uncore *, i915_reg_t, u16, bool);\n\tvoid (*mmio_writel)(struct intel_uncore *, i915_reg_t, u32, bool);\n};\n\nstruct intel_gt;\n\nstruct intel_runtime_pm;\n\nstruct intel_forcewake_range;\n\nstruct i915_mmio_range;\n\nstruct intel_uncore_fw_get;\n\nstruct intel_uncore_forcewake_domain;\n\nstruct intel_uncore_mmio_debug;\n\nstruct intel_uncore {\n\tvoid *regs;\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt *gt;\n\tstruct intel_runtime_pm *rpm;\n\tspinlock_t lock;\n\tu32 gsi_offset;\n\tunsigned int flags;\n\tconst struct intel_forcewake_range *fw_domains_table;\n\tunsigned int fw_domains_table_entries;\n\tconst struct i915_mmio_range *shadowed_reg_table;\n\tunsigned int shadowed_reg_table_entries;\n\tstruct notifier_block pmic_bus_access_nb;\n\tconst struct intel_uncore_fw_get *fw_get_funcs;\n\tstruct intel_uncore_funcs funcs;\n\tunsigned int fifo_count;\n\tenum forcewake_domains fw_domains;\n\tenum forcewake_domains fw_domains_active;\n\tenum forcewake_domains fw_domains_timer;\n\tenum forcewake_domains fw_domains_saved;\n\tstruct intel_uncore_forcewake_domain *fw_domain[16];\n\tunsigned int user_forcewake_count;\n\tstruct intel_uncore_mmio_debug *debug;\n};\n\nstruct intel_uncore_mmio_debug {\n\tspinlock_t lock;\n\tint unclaimed_mmio_check;\n\tint saved_mmio_check;\n\tu32 suspend_count;\n};\n\nstruct i915_virtual_gpu {\n\tstruct mutex lock;\n\tbool active;\n\tu32 caps;\n\tu32 *initial_mmio;\n\tu8 *initial_cfg_space;\n\tstruct list_head entry;\n};\n\nstruct intel_gvt;\n\nstruct pm_qos_request {\n\tstruct plist_node node;\n\tstruct pm_qos_constraints *qos;\n};\n\nstruct drm_mm {\n\tvoid (*color_adjust)(const struct drm_mm_node *, long unsigned int, u64 *, u64 *);\n\tstruct list_head hole_stack;\n\tstruct drm_mm_node head_node;\n\tstruct rb_root_cached interval_tree;\n\tstruct rb_root_cached holes_size;\n\tstruct rb_root holes_addr;\n\tlong unsigned int scan_active;\n};\n\nstruct shrinker;\n\nstruct i915_gem_mm {\n\tstruct intel_memory_region *stolen_region;\n\tstruct drm_mm stolen;\n\tstruct mutex stolen_lock;\n\tspinlock_t obj_lock;\n\tstruct list_head purge_list;\n\tstruct list_head shrink_list;\n\tstruct llist_head free_list;\n\tstruct work_struct free_work;\n\tatomic_t free_count;\n\tstruct intel_memory_region *regions[7];\n\tstruct notifier_block oom_notifier;\n\tstruct notifier_block vmap_notifier;\n\tstruct shrinker *shrinker;\n\tu64 shrink_memory;\n\tu32 shrink_count;\n};\n\nstruct intel_l3_parity {\n\tu32 *remap_info[2];\n\tstruct work_struct error_work;\n\tint which_slice;\n};\n\nstruct i915_gpu_coredump;\n\nstruct i915_gpu_error {\n\tspinlock_t lock;\n\tstruct i915_gpu_coredump *first_error;\n\tatomic_t reset_count;\n\tatomic_t reset_engine_count[5];\n};\n\ntypedef struct ref_tracker *intel_wakeref_t;\n\nstruct intel_wakeref_auto {\n\tstruct drm_i915_private *i915;\n\tstruct timer_list timer;\n\tintel_wakeref_t wakeref;\n\tspinlock_t lock;\n\trefcount_t count;\n};\n\nstruct intel_runtime_pm {\n\tatomic_t wakeref_count;\n\tstruct device *kdev;\n\tbool available;\n\tbool no_wakeref_tracking;\n\tspinlock_t lmem_userfault_lock;\n\tstruct list_head lmem_userfault_list;\n\tstruct intel_wakeref_auto userfault_wakeref;\n};\n\nstruct i915_perf;\n\nstruct i915_perf_stream;\n\nstruct i915_oa_ops {\n\tbool (*is_valid_b_counter_reg)(struct i915_perf *, u32);\n\tbool (*is_valid_mux_reg)(struct i915_perf *, u32);\n\tbool (*is_valid_flex_reg)(struct i915_perf *, u32);\n\tint (*enable_metric_set)(struct i915_perf_stream *, struct i915_active *);\n\tvoid (*disable_metric_set)(struct i915_perf_stream *);\n\tvoid (*oa_enable)(struct i915_perf_stream *);\n\tvoid (*oa_disable)(struct i915_perf_stream *);\n\tint (*read)(struct i915_perf_stream *, char *, size_t, size_t *);\n\tu32 (*oa_hw_tail_read)(struct i915_perf_stream *);\n};\n\nstruct i915_oa_format;\n\nstruct i915_perf {\n\tstruct drm_i915_private *i915;\n\tstruct kobject *metrics_kobj;\n\tstruct mutex metrics_lock;\n\tstruct idr metrics_idr;\n\tstruct ratelimit_state spurious_report_rs;\n\tstruct ratelimit_state tail_pointer_race;\n\tu32 gen7_latched_oastatus1;\n\tu32 ctx_oactxctrl_offset;\n\tu32 ctx_flexeu0_offset;\n\tu32 gen8_valid_ctx_bit;\n\tstruct i915_oa_ops ops;\n\tconst struct i915_oa_format *oa_formats;\n\tlong unsigned int format_mask[1];\n\tatomic64_t noa_programming_delay;\n};\n\nstruct i915_gem_contexts {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct i915_pmu_sample {\n\tu64 cur;\n};\n\nstruct i915_pmu {\n\tstruct pmu base;\n\tbool registered;\n\tconst char *name;\n\tspinlock_t lock;\n\tunsigned int unparked;\n\tstruct hrtimer timer;\n\tu32 enable;\n\tktime_t timer_last;\n\tunsigned int enable_count[9];\n\tbool timer_enabled;\n\tstruct i915_pmu_sample sample[8];\n\tktime_t sleep_last[2];\n\tlong unsigned int irq_count;\n\tstruct attribute_group events_attr_group;\n\tvoid *i915_attr;\n\tvoid *pmu_attr;\n};\n\nstruct dmem_cgroup_region;\n\nstruct ttm_resource_manager_func;\n\nstruct ttm_resource_manager {\n\tbool use_type;\n\tbool use_tt;\n\tstruct ttm_device *bdev;\n\tuint64_t size;\n\tconst struct ttm_resource_manager_func *func;\n\tspinlock_t eviction_lock;\n\tstruct dma_fence *eviction_fences[8];\n\tstruct list_head lru[4];\n\tuint64_t usage;\n\tstruct dmem_cgroup_region *cg;\n};\n\nstruct ttm_pool;\n\nstruct ttm_pool_type {\n\tstruct ttm_pool *pool;\n\tunsigned int order;\n\tenum ttm_caching caching;\n\tstruct list_head shrinker_list;\n\tspinlock_t lock;\n\tstruct list_head pages;\n};\n\nstruct ttm_pool {\n\tstruct device *dev;\n\tint nid;\n\tunsigned int alloc_flags;\n\tstruct {\n\t\tstruct ttm_pool_type orders[11];\n\t} caching[3];\n};\n\nstruct ttm_device_funcs;\n\nstruct ttm_device {\n\tstruct list_head device_list;\n\tunsigned int alloc_flags;\n\tconst struct ttm_device_funcs *funcs;\n\tstruct ttm_resource_manager sysman;\n\tstruct ttm_resource_manager *man_drv[9];\n\tstruct drm_vma_offset_manager *vma_manager;\n\tstruct ttm_pool pool;\n\tspinlock_t lru_lock;\n\tstruct list_head unevictable;\n\tstruct address_space *dev_mapping;\n\tstruct workqueue_struct *wq;\n};\n\nstruct intel_device_info;\n\nstruct vlv_s0ix_state;\n\nstruct i915_hwmon;\n\nstruct intel_pxp;\n\nstruct drm_i915_private {\n\tstruct drm_device drm;\n\tstruct intel_display *display;\n\tbool do_release;\n\tstruct i915_params params;\n\tconst struct intel_device_info *__info;\n\tstruct intel_runtime_info __runtime;\n\tstruct intel_driver_caps caps;\n\tstruct i915_dsm dsm;\n\tstruct intel_uncore uncore;\n\tstruct intel_uncore_mmio_debug mmio_debug;\n\tstruct i915_virtual_gpu vgpu;\n\tstruct intel_gvt *gvt;\n\tstruct {\n\t\tstruct pci_dev *pdev;\n\t\tstruct resource mch_res;\n\t\tbool mchbar_need_disable;\n\t} gmch;\n\tunion {\n\t\tstruct llist_head uabi_engines_llist;\n\t\tstruct list_head uabi_engines_list;\n\t\tstruct rb_root uabi_engines;\n\t};\n\tunsigned int engine_uabi_class_count[5];\n\tbool irqs_enabled;\n\tstruct mutex sbi_lock;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tlong unsigned int locked_unit_mask;\n\t\tstruct pm_qos_request qos;\n\t} vlv_iosf_sb;\n\tstruct mutex sb_lock;\n\tu32 gen2_imr_mask;\n\tbool preserve_bios_swizzle;\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_struct *unordered_wq;\n\tconst struct drm_i915_clock_gating_funcs *clock_gating_funcs;\n\tlong unsigned int gem_quirks;\n\tstruct i915_gem_mm mm;\n\tstruct intel_l3_parity l3_parity;\n\tu32 edram_size_mb;\n\tstruct i915_gpu_error gpu_error;\n\tu32 suspend_count;\n\tstruct vlv_s0ix_state *vlv_s0ix_state;\n\tstruct intel_runtime_pm runtime_pm;\n\tstruct i915_perf perf;\n\tstruct i915_hwmon *hwmon;\n\tstruct intel_gt *gt[2];\n\tstruct kobject *sysfs_gt;\n\tstruct intel_gt *media_gt;\n\tstruct {\n\t\tstruct i915_gem_contexts contexts;\n\t\tstruct file *mmap_singleton;\n\t} gem;\n\tspinlock_t frontbuffer_lock;\n\tstruct intel_pxp *pxp;\n\tstruct i915_pmu pmu;\n\tstruct ttm_device bdev;\n};\n\nstruct drm_i915_query {\n\t__u32 num_items;\n\t__u32 flags;\n\t__u64 items_ptr;\n};\n\nstruct drm_i915_query_engine_info {\n\t__u32 num_engines;\n\t__u32 rsvd[3];\n\tstruct drm_i915_engine_info engines[0];\n};\n\nstruct drm_i915_query_guc_submission_version {\n\t__u32 branch;\n\t__u32 major;\n\t__u32 minor;\n\t__u32 patch;\n};\n\nstruct drm_i915_query_item {\n\t__u64 query_id;\n\t__s32 length;\n\t__u32 flags;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_query_memory_regions {\n\t__u32 num_regions;\n\t__u32 rsvd[3];\n\tstruct drm_i915_memory_region_info regions[0];\n};\n\nstruct drm_i915_query_perf_config {\n\tunion {\n\t\t__u64 n_configs;\n\t\t__u64 config;\n\t\tchar uuid[36];\n\t};\n\t__u32 flags;\n\t__u8 data[0];\n};\n\nstruct drm_i915_query_topology_info {\n\t__u16 flags;\n\t__u16 max_slices;\n\t__u16 max_subslices;\n\t__u16 max_eus_per_subslice;\n\t__u16 subslice_offset;\n\t__u16 subslice_stride;\n\t__u16 eu_offset;\n\t__u16 eu_stride;\n\t__u8 data[0];\n};\n\nstruct drm_i915_reg_descriptor {\n\ti915_reg_t addr;\n\tu32 mask;\n\tu32 value;\n};\n\nstruct drm_i915_reg_read {\n\t__u64 offset;\n\t__u64 val;\n};\n\nstruct drm_i915_reg_table {\n\tconst struct drm_i915_reg_descriptor *regs;\n\tint num_regs;\n};\n\nstruct drm_i915_reset_stats {\n\t__u32 ctx_id;\n\t__u32 flags;\n\t__u32 reset_count;\n\t__u32 batch_active;\n\t__u32 batch_pending;\n\t__u32 pad;\n};\n\nstruct drm_info_list {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n\tu32 driver_features;\n\tvoid *data;\n};\n\nstruct drm_info_node {\n\tstruct drm_minor *minor;\n\tconst struct drm_info_list *info_ent;\n\tstruct list_head list;\n\tstruct dentry *dent;\n};\n\nstruct drm_intel_overlay_attrs {\n\t__u32 flags;\n\t__u32 color_key;\n\t__s32 brightness;\n\t__u32 contrast;\n\t__u32 saturation;\n\t__u32 gamma0;\n\t__u32 gamma1;\n\t__u32 gamma2;\n\t__u32 gamma3;\n\t__u32 gamma4;\n\t__u32 gamma5;\n};\n\nstruct drm_intel_overlay_put_image {\n\t__u32 flags;\n\t__u32 bo_handle;\n\t__u16 stride_Y;\n\t__u16 stride_UV;\n\t__u32 offset_Y;\n\t__u32 offset_U;\n\t__u32 offset_V;\n\t__u16 src_width;\n\t__u16 src_height;\n\t__u16 src_scan_width;\n\t__u16 src_scan_height;\n\t__u32 crtc_id;\n\t__u16 dst_x;\n\t__u16 dst_y;\n\t__u16 dst_width;\n\t__u16 dst_height;\n};\n\nstruct drm_intel_sprite_colorkey {\n\t__u32 plane_id;\n\t__u32 min_value;\n\t__u32 channel_mask;\n\t__u32 max_value;\n\t__u32 flags;\n};\n\ntypedef int drm_ioctl_t(struct drm_device *, void *, struct drm_file *);\n\nstruct drm_ioctl_desc {\n\tunsigned int cmd;\n\tenum drm_ioctl_flags flags;\n\tdrm_ioctl_t *func;\n\tconst char *name;\n};\n\nstruct drm_master {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tchar *unique;\n\tint unique_len;\n\tstruct idr magic_map;\n\tvoid *driver_priv;\n\tstruct drm_master *lessor;\n\tint lessee_id;\n\tstruct list_head lessee_list;\n\tstruct list_head lessees;\n\tstruct idr leases;\n\tstruct idr lessee_idr;\n};\n\nstruct drm_memory_stats {\n\tu64 shared;\n\tu64 private;\n\tu64 resident;\n\tu64 purgeable;\n\tu64 active;\n};\n\nstruct drm_minor {\n\tint index;\n\tint type;\n\tstruct device *kdev;\n\tstruct drm_device *dev;\n\tstruct dentry *debugfs_symlink;\n\tstruct dentry *debugfs_root;\n};\n\nstruct drm_mm_scan {\n\tstruct drm_mm *mm;\n\tu64 size;\n\tu64 alignment;\n\tu64 remainder_mask;\n\tu64 range_start;\n\tu64 range_end;\n\tu64 hit_start;\n\tu64 hit_end;\n\tlong unsigned int color;\n\tenum drm_mm_insert_mode mode;\n};\n\nstruct drm_mode_atomic {\n\t__u32 flags;\n\t__u32 count_objs;\n\t__u64 objs_ptr;\n\t__u64 count_props_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u64 reserved;\n\t__u64 user_data;\n};\n\nstruct drm_mode_card_res {\n\t__u64 fb_id_ptr;\n\t__u64 crtc_id_ptr;\n\t__u64 connector_id_ptr;\n\t__u64 encoder_id_ptr;\n\t__u32 count_fbs;\n\t__u32 count_crtcs;\n\t__u32 count_connectors;\n\t__u32 count_encoders;\n\t__u32 min_width;\n\t__u32 max_width;\n\t__u32 min_height;\n\t__u32 max_height;\n};\n\nstruct drm_mode_closefb {\n\t__u32 fb_id;\n\t__u32 pad;\n};\n\nstruct drm_mode_fb_cmd2;\n\nstruct drm_mode_config_funcs {\n\tstruct drm_framebuffer * (*fb_create)(struct drm_device *, struct drm_file *, const struct drm_format_info *, const struct drm_mode_fb_cmd2 *);\n\tconst struct drm_format_info * (*get_format_info)(u32, u64);\n\tenum drm_mode_status (*mode_valid)(struct drm_device *, const struct drm_display_mode *);\n\tint (*atomic_check)(struct drm_device *, struct drm_atomic_state *);\n\tint (*atomic_commit)(struct drm_device *, struct drm_atomic_state *, bool);\n\tstruct drm_atomic_state * (*atomic_state_alloc)(struct drm_device *);\n\tvoid (*atomic_state_clear)(struct drm_atomic_state *);\n\tvoid (*atomic_state_free)(struct drm_atomic_state *);\n};\n\nstruct drm_mode_config_helper_funcs {\n\tvoid (*atomic_commit_tail)(struct drm_atomic_state *);\n\tint (*atomic_commit_setup)(struct drm_atomic_state *);\n};\n\nstruct drm_mode_connector_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 connector_id;\n};\n\nstruct drm_mode_create_blob {\n\t__u64 data;\n\t__u32 length;\n\t__u32 blob_id;\n};\n\nstruct drm_mode_create_dumb {\n\t__u32 height;\n\t__u32 width;\n\t__u32 bpp;\n\t__u32 flags;\n\t__u32 handle;\n\t__u32 pitch;\n\t__u64 size;\n};\n\nstruct drm_mode_create_lease {\n\t__u64 object_ids;\n\t__u32 object_count;\n\t__u32 flags;\n\t__u32 lessee_id;\n\t__u32 fd;\n};\n\nstruct drm_mode_modeinfo {\n\t__u32 clock;\n\t__u16 hdisplay;\n\t__u16 hsync_start;\n\t__u16 hsync_end;\n\t__u16 htotal;\n\t__u16 hskew;\n\t__u16 vdisplay;\n\t__u16 vsync_start;\n\t__u16 vsync_end;\n\t__u16 vtotal;\n\t__u16 vscan;\n\t__u32 vrefresh;\n\t__u32 flags;\n\t__u32 type;\n\tchar name[32];\n};\n\nstruct drm_mode_crtc {\n\t__u64 set_connectors_ptr;\n\t__u32 count_connectors;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 x;\n\t__u32 y;\n\t__u32 gamma_size;\n\t__u32 mode_valid;\n\tstruct drm_mode_modeinfo mode;\n};\n\nstruct drm_mode_crtc_lut {\n\t__u32 crtc_id;\n\t__u32 gamma_size;\n\t__u64 red;\n\t__u64 green;\n\t__u64 blue;\n};\n\nstruct drm_mode_crtc_page_flip_target {\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 sequence;\n\t__u64 user_data;\n};\n\nstruct drm_mode_cursor {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n};\n\nstruct drm_mode_cursor2 {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n\t__s32 hot_x;\n\t__s32 hot_y;\n};\n\nstruct drm_mode_destroy_blob {\n\t__u32 blob_id;\n};\n\nstruct drm_mode_destroy_dumb {\n\t__u32 handle;\n};\n\nstruct drm_mode_fb_cmd {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pitch;\n\t__u32 bpp;\n\t__u32 depth;\n\t__u32 handle;\n};\n\nstruct drm_mode_fb_cmd2 {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pixel_format;\n\t__u32 flags;\n\t__u32 handles[4];\n\t__u32 pitches[4];\n\t__u32 offsets[4];\n\t__u64 modifier[4];\n};\n\nstruct drm_mode_fb_cmd232 {\n\tu32 fb_id;\n\tu32 width;\n\tu32 height;\n\tu32 pixel_format;\n\tu32 flags;\n\tu32 handles[4];\n\tu32 pitches[4];\n\tu32 offsets[4];\n\tu64 modifier[4];\n} __attribute__((packed));\n\nstruct drm_mode_fb_dirty_cmd {\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 color;\n\t__u32 num_clips;\n\t__u64 clips_ptr;\n};\n\nstruct drm_mode_get_blob {\n\t__u32 blob_id;\n\t__u32 length;\n\t__u64 data;\n};\n\nstruct drm_mode_get_connector {\n\t__u64 encoders_ptr;\n\t__u64 modes_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_modes;\n\t__u32 count_props;\n\t__u32 count_encoders;\n\t__u32 encoder_id;\n\t__u32 connector_id;\n\t__u32 connector_type;\n\t__u32 connector_type_id;\n\t__u32 connection;\n\t__u32 mm_width;\n\t__u32 mm_height;\n\t__u32 subpixel;\n\t__u32 pad;\n};\n\nstruct drm_mode_get_encoder {\n\t__u32 encoder_id;\n\t__u32 encoder_type;\n\t__u32 crtc_id;\n\t__u32 possible_crtcs;\n\t__u32 possible_clones;\n};\n\nstruct drm_mode_get_lease {\n\t__u32 count_objects;\n\t__u32 pad;\n\t__u64 objects_ptr;\n};\n\nstruct drm_mode_get_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 possible_crtcs;\n\t__u32 gamma_size;\n\t__u32 count_format_types;\n\t__u64 format_type_ptr;\n};\n\nstruct drm_mode_get_plane_res {\n\t__u64 plane_id_ptr;\n\t__u32 count_planes;\n};\n\nstruct drm_mode_get_property {\n\t__u64 values_ptr;\n\t__u64 enum_blob_ptr;\n\t__u32 prop_id;\n\t__u32 flags;\n\tchar name[32];\n\t__u32 count_values;\n\t__u32 count_enum_blobs;\n};\n\nstruct drm_mode_list_lessees {\n\t__u32 count_lessees;\n\t__u32 pad;\n\t__u64 lessees_ptr;\n};\n\nstruct drm_mode_map_dumb {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n};\n\nstruct drm_mode_obj_get_properties {\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_props;\n\t__u32 obj_id;\n\t__u32 obj_type;\n};\n\nstruct drm_mode_obj_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 obj_id;\n\t__u32 obj_type;\n};\n\nstruct drm_mode_property_enum {\n\t__u64 value;\n\tchar name[32];\n};\n\nstruct drm_mode_rect {\n\t__s32 x1;\n\t__s32 y1;\n\t__s32 x2;\n\t__s32 y2;\n};\n\nstruct drm_mode_revoke_lease {\n\t__u32 lessee_id;\n};\n\nstruct drm_mode_rmfb_work {\n\tstruct work_struct work;\n\tstruct list_head fbs;\n};\n\nstruct drm_mode_set {\n\tstruct drm_framebuffer *fb;\n\tstruct drm_crtc *crtc;\n\tstruct drm_display_mode *mode;\n\tuint32_t x;\n\tuint32_t y;\n\tstruct drm_connector **connectors;\n\tsize_t num_connectors;\n};\n\nstruct drm_mode_set_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__s32 crtc_x;\n\t__s32 crtc_y;\n\t__u32 crtc_w;\n\t__u32 crtc_h;\n\t__u32 src_x;\n\t__u32 src_y;\n\t__u32 src_h;\n\t__u32 src_w;\n};\n\nstruct drm_modeset_acquire_ctx {\n\tstruct ww_acquire_ctx ww_ctx;\n\tstruct drm_modeset_lock *contended;\n\tdepot_stack_handle_t stack_depot;\n\tstruct list_head locked;\n\tbool trylock_only;\n\tbool interruptible;\n};\n\nstruct drm_named_mode {\n\tconst char *name;\n\tunsigned int pixel_clock_khz;\n\tunsigned int xres;\n\tunsigned int yres;\n\tunsigned int flags;\n\tunsigned int tv_mode;\n};\n\nstruct sync_file;\n\nstruct drm_out_fence_state {\n\ts32 *out_fence_ptr;\n\tstruct sync_file *sync_file;\n\tint fd;\n};\n\nstruct drm_panel_funcs;\n\nstruct drm_panel {\n\tstruct device *dev;\n\tstruct backlight_device *backlight;\n\tconst struct drm_panel_funcs *funcs;\n\tint connector_type;\n\tstruct list_head list;\n\tstruct list_head followers;\n\tstruct mutex follower_lock;\n\tbool prepare_prev_first;\n\tbool prepared;\n\tbool enabled;\n\tvoid *container;\n\tstruct kref refcount;\n};\n\nstruct drm_panel_follower_funcs;\n\nstruct drm_panel_follower {\n\tconst struct drm_panel_follower_funcs *funcs;\n\tstruct list_head list;\n\tstruct drm_panel *panel;\n};\n\nstruct drm_panel_follower_funcs {\n\tint (*panel_prepared)(struct drm_panel_follower *);\n\tint (*panel_unpreparing)(struct drm_panel_follower *);\n\tint (*panel_enabled)(struct drm_panel_follower *);\n\tint (*panel_disabling)(struct drm_panel_follower *);\n};\n\nstruct display_timing;\n\nstruct drm_panel_funcs {\n\tint (*prepare)(struct drm_panel *);\n\tint (*enable)(struct drm_panel *);\n\tint (*disable)(struct drm_panel *);\n\tint (*unprepare)(struct drm_panel *);\n\tint (*get_modes)(struct drm_panel *, struct drm_connector *);\n\tenum drm_panel_orientation (*get_orientation)(struct drm_panel *);\n\tint (*get_timings)(struct drm_panel *, unsigned int, struct display_timing *);\n\tvoid (*debugfs_init)(struct drm_panel *, struct dentry *);\n};\n\nstruct drm_pending_event {\n\tstruct completion *completion;\n\tvoid (*completion_release)(struct completion *);\n\tstruct drm_event *event;\n\tstruct dma_fence *fence;\n\tstruct drm_file *file_priv;\n\tstruct list_head link;\n\tstruct list_head pending_link;\n};\n\nstruct drm_pending_vblank_event {\n\tstruct drm_pending_event base;\n\tunsigned int pipe;\n\tu64 sequence;\n\tunion {\n\t\tstruct drm_event base;\n\t\tstruct drm_event_vblank vbl;\n\t\tstruct drm_event_crtc_sequence seq;\n\t} event;\n};\n\nstruct kmsg_dump_detail;\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct drm_plane_funcs;\n\nstruct drm_plane_helper_funcs;\n\nstruct drm_plane {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tuint32_t possible_crtcs;\n\tuint32_t *format_types;\n\tunsigned int format_count;\n\tbool format_default;\n\tuint64_t *modifiers;\n\tunsigned int modifier_count;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct drm_framebuffer *old_fb;\n\tconst struct drm_plane_funcs *funcs;\n\tstruct drm_object_properties properties;\n\tenum drm_plane_type type;\n\tunsigned int index;\n\tconst struct drm_plane_helper_funcs *helper_private;\n\tstruct drm_plane_state *state;\n\tstruct drm_property *alpha_property;\n\tstruct drm_property *zpos_property;\n\tstruct drm_property *rotation_property;\n\tstruct drm_property *blend_mode_property;\n\tstruct drm_property *color_encoding_property;\n\tstruct drm_property *color_range_property;\n\tstruct drm_property *color_pipeline_property;\n\tstruct drm_property *scaling_filter_property;\n\tstruct drm_property *hotspot_x_property;\n\tstruct drm_property *hotspot_y_property;\n\tstruct kmsg_dumper kmsg_panic;\n};\n\nstruct drm_plane_funcs {\n\tint (*update_plane)(struct drm_plane *, struct drm_crtc *, struct drm_framebuffer *, int, int, unsigned int, unsigned int, uint32_t, uint32_t, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*disable_plane)(struct drm_plane *, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_plane *);\n\tvoid (*reset)(struct drm_plane *);\n\tint (*set_property)(struct drm_plane *, struct drm_property *, uint64_t);\n\tstruct drm_plane_state * (*atomic_duplicate_state)(struct drm_plane *);\n\tvoid (*atomic_destroy_state)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_set_property)(struct drm_plane *, struct drm_plane_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_plane *, const struct drm_plane_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_plane *);\n\tvoid (*early_unregister)(struct drm_plane *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_plane_state *);\n\tbool (*format_mod_supported)(struct drm_plane *, uint32_t, uint64_t);\n\tbool (*format_mod_supported_async)(struct drm_plane *, u32, u64);\n};\n\nstruct drm_scanout_buffer;\n\nstruct drm_plane_helper_funcs {\n\tint (*prepare_fb)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_plane *, struct drm_plane_state *);\n\tint (*begin_fb_access)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*end_fb_access)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_check)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_update)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_plane *, struct drm_atomic_state *);\n\tvoid (*atomic_disable)(struct drm_plane *, struct drm_atomic_state *);\n\tint (*atomic_async_check)(struct drm_plane *, struct drm_atomic_state *, bool);\n\tvoid (*atomic_async_update)(struct drm_plane *, struct drm_atomic_state *);\n\tint (*get_scanout_buffer)(struct drm_plane *, struct drm_scanout_buffer *);\n\tvoid (*panic_flush)(struct drm_plane *);\n};\n\nstruct drm_plane_size_hint {\n\t__u16 width;\n\t__u16 height;\n};\n\nstruct drm_plane_state {\n\tstruct drm_plane *plane;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *fence;\n\tint32_t crtc_x;\n\tint32_t crtc_y;\n\tuint32_t crtc_w;\n\tuint32_t crtc_h;\n\tuint32_t src_x;\n\tuint32_t src_y;\n\tuint32_t src_h;\n\tuint32_t src_w;\n\tint32_t hotspot_x;\n\tint32_t hotspot_y;\n\tu16 alpha;\n\tuint16_t pixel_blend_mode;\n\tunsigned int rotation;\n\tunsigned int zpos;\n\tunsigned int normalized_zpos;\n\tenum drm_color_encoding color_encoding;\n\tenum drm_color_range color_range;\n\tstruct drm_property_blob *fb_damage_clips;\n\tbool ignore_damage_clips;\n\tstruct drm_rect src;\n\tstruct drm_rect dst;\n\tbool visible;\n\tenum drm_scaling_filter scaling_filter;\n\tstruct drm_colorop *color_pipeline;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n\tbool color_mgmt_changed: 1;\n};\n\nstruct drm_prime_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct drm_prime_member {\n\tstruct dma_buf *dma_buf;\n\tuint32_t handle;\n\tstruct rb_node dmabuf_rb;\n\tstruct rb_node handle_rb;\n};\n\nstruct drm_print_iterator {\n\tvoid *data;\n\tssize_t start;\n\tssize_t remain;\n\tssize_t offset;\n};\n\nstruct va_format;\n\nstruct drm_printer {\n\tvoid (*printfn)(struct drm_printer *, struct va_format *);\n\tvoid (*puts)(struct drm_printer *, const char *);\n\tvoid *arg;\n\tconst void *origin;\n\tconst char *prefix;\n\tstruct {\n\t\tunsigned int series;\n\t\tunsigned int counter;\n\t} line;\n\tenum drm_debug_category category;\n};\n\nstruct drm_private_state_funcs {\n\tstruct drm_private_state * (*atomic_duplicate_state)(struct drm_private_obj *);\n\tvoid (*atomic_destroy_state)(struct drm_private_obj *, struct drm_private_state *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_private_state *);\n};\n\nstruct drm_prop_enum_list {\n\tint type;\n\tconst char *name;\n};\n\nstruct drm_property {\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tuint32_t flags;\n\tchar name[32];\n\tuint32_t num_values;\n\tuint64_t *values;\n\tstruct drm_device *dev;\n\tstruct list_head enum_list;\n};\n\nstruct drm_property_blob {\n\tstruct drm_mode_object base;\n\tstruct drm_device *dev;\n\tstruct list_head head_global;\n\tstruct list_head head_file;\n\tsize_t length;\n\tvoid *data;\n};\n\nstruct drm_property_enum {\n\tuint64_t value;\n\tstruct list_head head;\n\tchar name[32];\n};\n\nstruct drm_scanout_buffer {\n\tconst struct drm_format_info *format;\n\tstruct iosys_map map[4];\n\tstruct page **pages;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int pitch[4];\n\tvoid (*set_pixel)(struct drm_scanout_buffer *, unsigned int, unsigned int, u32);\n\tvoid *private;\n};\n\nstruct ewma_psr_time {\n\tlong unsigned int internal;\n};\n\nstruct drm_self_refresh_data {\n\tstruct drm_crtc *crtc;\n\tstruct delayed_work entry_work;\n\tstruct mutex avg_mutex;\n\tstruct ewma_psr_time entry_avg_ms;\n\tstruct ewma_psr_time exit_avg_ms;\n};\n\nstruct drm_set_client_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_set_client_name {\n\t__u64 name_len;\n\t__u64 name;\n};\n\nstruct drm_set_version {\n\tint drm_di_major;\n\tint drm_di_minor;\n\tint drm_dd_major;\n\tint drm_dd_minor;\n};\n\nstruct drm_shadow_plane_state {\n\tstruct drm_plane_state base;\n\tstruct drm_format_conv_state fmtcnv_state;\n\tstruct iosys_map map[4];\n\tstruct iosys_map data[4];\n};\n\nstruct drm_simple_display_pipe_funcs;\n\nstruct drm_simple_display_pipe {\n\tstruct drm_crtc crtc;\n\tstruct drm_plane plane;\n\tstruct drm_encoder encoder;\n\tstruct drm_connector *connector;\n\tconst struct drm_simple_display_pipe_funcs *funcs;\n};\n\nstruct drm_simple_display_pipe_funcs {\n\tenum drm_mode_status (*mode_valid)(struct drm_simple_display_pipe *, const struct drm_display_mode *);\n\tvoid (*enable)(struct drm_simple_display_pipe *, struct drm_crtc_state *, struct drm_plane_state *);\n\tvoid (*disable)(struct drm_simple_display_pipe *);\n\tint (*check)(struct drm_simple_display_pipe *, struct drm_plane_state *, struct drm_crtc_state *);\n\tvoid (*update)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*prepare_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*begin_fb_access)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tvoid (*end_fb_access)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*enable_vblank)(struct drm_simple_display_pipe *);\n\tvoid (*disable_vblank)(struct drm_simple_display_pipe *);\n\tvoid (*reset_crtc)(struct drm_simple_display_pipe *);\n\tstruct drm_crtc_state * (*duplicate_crtc_state)(struct drm_simple_display_pipe *);\n\tvoid (*destroy_crtc_state)(struct drm_simple_display_pipe *, struct drm_crtc_state *);\n\tvoid (*reset_plane)(struct drm_simple_display_pipe *);\n\tstruct drm_plane_state * (*duplicate_plane_state)(struct drm_simple_display_pipe *);\n\tvoid (*destroy_plane_state)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n};\n\nstruct drm_stats {\n\tlong unsigned int count;\n\tstruct {\n\t\tlong unsigned int value;\n\t\tenum drm_stat_type type;\n\t} data[15];\n};\n\nstruct drm_stats32 {\n\tu32 count;\n\tstruct {\n\t\tu32 value;\n\t\tenum drm_stat_type type;\n\t} data[15];\n};\n\ntypedef struct drm_stats32 drm_stats32_t;\n\nstruct drm_syncobj {\n\tstruct kref refcount;\n\tstruct dma_fence *fence;\n\tstruct list_head cb_list;\n\tstruct list_head ev_fd_list;\n\tspinlock_t lock;\n\tstruct file *file;\n};\n\nstruct drm_syncobj_array {\n\t__u64 handles;\n\t__u32 count_handles;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_create {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_syncobj_destroy {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_eventfd {\n\t__u32 handle;\n\t__u32 flags;\n\t__u64 point;\n\t__s32 fd;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n\t__u32 pad;\n\t__u64 point;\n};\n\nstruct drm_syncobj_timeline_array {\n\t__u64 handles;\n\t__u64 points;\n\t__u32 count_handles;\n\t__u32 flags;\n};\n\nstruct drm_syncobj_timeline_wait {\n\t__u64 handles;\n\t__u64 points;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n\t__u64 deadline_nsec;\n};\n\nstruct drm_syncobj_transfer {\n\t__u32 src_handle;\n\t__u32 dst_handle;\n\t__u64 src_point;\n\t__u64 dst_point;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_wait {\n\t__u64 handles;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n\t__u64 deadline_nsec;\n};\n\nstruct drm_tile_group {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tint id;\n\tu8 group_data[8];\n};\n\nstruct drm_unique {\n\t__kernel_size_t unique_len;\n\tchar *unique;\n};\n\nstruct drm_unique32 {\n\tu32 unique_len;\n\tu32 unique;\n};\n\ntypedef struct drm_unique32 drm_unique32_t;\n\nstruct drm_vblank_crtc_config {\n\tint offdelay_ms;\n\tbool disable_immediate;\n};\n\nstruct drm_vblank_crtc_timer {\n\tstruct hrtimer timer;\n\tspinlock_t interval_lock;\n\tktime_t interval;\n\tstruct drm_crtc *crtc;\n};\n\nstruct drm_vblank_crtc {\n\tstruct drm_device *dev;\n\twait_queue_head_t queue;\n\tstruct timer_list disable_timer;\n\tseqlock_t seqlock;\n\tatomic64_t count;\n\tktime_t time;\n\tatomic_t refcount;\n\tu32 last;\n\tu32 max_vblank_count;\n\tunsigned int inmodeset;\n\tunsigned int pipe;\n\tint framedur_ns;\n\tint linedur_ns;\n\tstruct drm_display_mode hwmode;\n\tstruct drm_vblank_crtc_config config;\n\tbool enabled;\n\tstruct kthread_worker *worker;\n\tstruct list_head pending_work;\n\twait_queue_head_t work_wait_queue;\n\tstruct drm_vblank_crtc_timer vblank_timer;\n};\n\nstruct drm_vblank_work {\n\tstruct kthread_work base;\n\tstruct drm_vblank_crtc *vblank;\n\tu64 count;\n\tint cancelling;\n\tstruct list_head node;\n};\n\nstruct drm_version {\n\tint version_major;\n\tint version_minor;\n\tint version_patchlevel;\n\t__kernel_size_t name_len;\n\tchar *name;\n\t__kernel_size_t date_len;\n\tchar *date;\n\t__kernel_size_t desc_len;\n\tchar *desc;\n};\n\nstruct drm_version_32 {\n\tint version_major;\n\tint version_minor;\n\tint version_patchlevel;\n\tu32 name_len;\n\tu32 name;\n\tu32 date_len;\n\tu32 date;\n\tu32 desc_len;\n\tu32 desc;\n};\n\ntypedef struct drm_version_32 drm_version32_t;\n\nstruct drm_virtgpu_3d_box {\n\t__u32 x;\n\t__u32 y;\n\t__u32 z;\n\t__u32 w;\n\t__u32 h;\n\t__u32 d;\n};\n\nstruct drm_virtgpu_3d_transfer_from_host {\n\t__u32 bo_handle;\n\tstruct drm_virtgpu_3d_box box;\n\t__u32 level;\n\t__u32 offset;\n\t__u32 stride;\n\t__u32 layer_stride;\n};\n\nstruct drm_virtgpu_3d_transfer_to_host {\n\t__u32 bo_handle;\n\tstruct drm_virtgpu_3d_box box;\n\t__u32 level;\n\t__u32 offset;\n\t__u32 stride;\n\t__u32 layer_stride;\n};\n\nstruct drm_virtgpu_3d_wait {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_virtgpu_context_init {\n\t__u32 num_params;\n\t__u32 pad;\n\t__u64 ctx_set_params;\n};\n\nstruct drm_virtgpu_context_set_param {\n\t__u64 param;\n\t__u64 value;\n};\n\nstruct drm_virtgpu_execbuffer {\n\t__u32 flags;\n\t__u32 size;\n\t__u64 command;\n\t__u64 bo_handles;\n\t__u32 num_bo_handles;\n\t__s32 fence_fd;\n\t__u32 ring_idx;\n\t__u32 syncobj_stride;\n\t__u32 num_in_syncobjs;\n\t__u32 num_out_syncobjs;\n\t__u64 in_syncobjs;\n\t__u64 out_syncobjs;\n};\n\nstruct drm_virtgpu_execbuffer_syncobj {\n\t__u32 handle;\n\t__u32 flags;\n\t__u64 point;\n};\n\nstruct drm_virtgpu_get_caps {\n\t__u32 cap_set_id;\n\t__u32 cap_set_ver;\n\t__u64 addr;\n\t__u32 size;\n\t__u32 pad;\n};\n\nstruct drm_virtgpu_getparam {\n\t__u64 param;\n\t__u64 value;\n};\n\nstruct drm_virtgpu_map {\n\t__u64 offset;\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_virtgpu_resource_create {\n\t__u32 target;\n\t__u32 format;\n\t__u32 bind;\n\t__u32 width;\n\t__u32 height;\n\t__u32 depth;\n\t__u32 array_size;\n\t__u32 last_level;\n\t__u32 nr_samples;\n\t__u32 flags;\n\t__u32 bo_handle;\n\t__u32 res_handle;\n\t__u32 size;\n\t__u32 stride;\n};\n\nstruct drm_virtgpu_resource_create_blob {\n\t__u32 blob_mem;\n\t__u32 blob_flags;\n\t__u32 bo_handle;\n\t__u32 res_handle;\n\t__u64 size;\n\t__u32 pad;\n\t__u32 cmd_size;\n\t__u64 cmd;\n\t__u64 blob_id;\n};\n\nstruct drm_virtgpu_resource_info {\n\t__u32 bo_handle;\n\t__u32 res_handle;\n\t__u32 size;\n\t__u32 blob_mem;\n};\n\nstruct drm_vma_offset_file {\n\tstruct rb_node vm_rb;\n\tstruct drm_file *vm_tag;\n\tlong unsigned int vm_count;\n};\n\nstruct drm_vma_offset_manager {\n\trwlock_t vm_lock;\n\tstruct drm_mm vm_addr_space_mm;\n};\n\nstruct drm_wait_vblank_request {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong unsigned int signal;\n};\n\nstruct drm_wait_vblank_reply {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong int tval_sec;\n\tlong int tval_usec;\n};\n\nunion drm_wait_vblank {\n\tstruct drm_wait_vblank_request request;\n\tstruct drm_wait_vblank_reply reply;\n};\n\nstruct drm_wait_vblank_request32 {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tu32 signal;\n};\n\nstruct drm_wait_vblank_reply32 {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\ts32 tval_sec;\n\ts32 tval_usec;\n};\n\nunion drm_wait_vblank32 {\n\tstruct drm_wait_vblank_request32 request;\n\tstruct drm_wait_vblank_reply32 reply;\n};\n\ntypedef union drm_wait_vblank32 drm_wait_vblank32_t;\n\nstruct drm_wedge_task_info {\n\tpid_t pid;\n\tchar comm[16];\n};\n\nstruct drm_writeback_connector {\n\tstruct drm_connector base;\n\tstruct drm_encoder encoder;\n\tstruct drm_property_blob *pixel_formats_blob_ptr;\n\tspinlock_t job_lock;\n\tstruct list_head job_queue;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n};\n\nstruct drm_writeback_job {\n\tstruct drm_writeback_connector *connector;\n\tbool prepared;\n\tstruct work_struct cleanup_work;\n\tstruct list_head list_entry;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *out_fence;\n\tvoid *priv;\n};\n\ntypedef void (*drmres_release_t)(struct drm_device *, void *);\n\nstruct drmres_node {\n\tstruct list_head entry;\n\tdrmres_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct drmres {\n\tstruct drmres_node node;\n\tu8 data[0];\n};\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct drv_cmd {\n\tstruct acpi_pct_register *reg;\n\tu32 val;\n\tunion {\n\t\tvoid (*write)(struct acpi_pct_register *, u32);\n\t\tu32 (*read)(struct acpi_pct_register *);\n\t} func;\n};\n\nstruct pci_driver;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct dst_entry;\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tlocal_lock_t bh_lock;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct dst_ops;\n\nstruct xfrm_state;\n\nstruct uncached_list;\n\nstruct lwtunnel_state;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tstruct xfrm_state *xfrm;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\trcuref_t __rcuref;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n\tstruct lwtunnel_state *lwtstate;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct uart_8250_port;\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_tx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan *rxchan;\n\tstruct dma_chan *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct dw8250_port_data {\n\tint line;\n\tstruct uart_8250_dma dma;\n\tu32 cpr_value;\n\tu8 dlf_size;\n\tbool hw_rs485_support;\n};\n\nstruct dw_lli {\n\t__le32 sar;\n\t__le32 dar;\n\t__le32 llp;\n\t__le32 ctllo;\n\t__le32 ctlhi;\n\t__le32 sstat;\n\t__le32 dstat;\n};\n\nstruct dw_desc {\n\tstruct dw_lli lli;\n\tstruct list_head desc_node;\n\tstruct list_head tx_list;\n\tstruct dma_async_tx_descriptor txd;\n\tsize_t len;\n\tsize_t total_len;\n\tu32 residue;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct dw_dma_chan;\n\nstruct dw_dma_platform_data;\n\nstruct dw_dma {\n\tstruct dma_device dma;\n\tchar name[20];\n\tvoid *regs;\n\tstruct dma_pool *desc_pool;\n\tstruct tasklet_struct tasklet;\n\tstruct dw_dma_chan *chan;\n\tu8 all_chan_mask;\n\tu8 in_use;\n\tvoid (*initialize_chan)(struct dw_dma_chan *);\n\tvoid (*suspend_chan)(struct dw_dma_chan *, bool);\n\tvoid (*resume_chan)(struct dw_dma_chan *, bool);\n\tu32 (*prepare_ctllo)(struct dw_dma_chan *);\n\tu32 (*bytes2block)(struct dw_dma_chan *, size_t, unsigned int, size_t *);\n\tsize_t (*block2bytes)(struct dw_dma_chan *, u32, u32);\n\tvoid (*set_device_name)(struct dw_dma *, int);\n\tvoid (*disable)(struct dw_dma *);\n\tvoid (*enable)(struct dw_dma *);\n\tstruct dw_dma_platform_data *pdata;\n};\n\nstruct dw_dma_slave {\n\tstruct device *dma_dev;\n\tu8 src_id;\n\tu8 dst_id;\n\tu8 m_master;\n\tu8 p_master;\n\tu8 channels;\n\tbool hs_polarity;\n};\n\nstruct dw_dma_chan {\n\tstruct dma_chan chan;\n\tvoid *ch_regs;\n\tu8 mask;\n\tu8 priority;\n\tenum dma_transfer_direction direction;\n\tstruct list_head *tx_node_active;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tstruct list_head active_list;\n\tstruct list_head queue;\n\tunsigned int descs_allocated;\n\tunsigned int block_size;\n\tbool nollp;\n\tu32 max_burst;\n\tstruct dw_dma_slave dws;\n\tstruct dma_slave_config dma_sconfig;\n};\n\nstruct dw_dma_chan_regs {\n\tu32 SAR;\n\tu32 __pad_SAR;\n\tu32 DAR;\n\tu32 __pad_DAR;\n\tu32 LLP;\n\tu32 __pad_LLP;\n\tu32 CTL_LO;\n\tu32 CTL_HI;\n\tu32 SSTAT;\n\tu32 __pad_SSTAT;\n\tu32 DSTAT;\n\tu32 __pad_DSTAT;\n\tu32 SSTATAR;\n\tu32 __pad_SSTATAR;\n\tu32 DSTATAR;\n\tu32 __pad_DSTATAR;\n\tu32 CFG_LO;\n\tu32 CFG_HI;\n\tu32 SGR;\n\tu32 __pad_SGR;\n\tu32 DSR;\n\tu32 __pad_DSR;\n};\n\nstruct dw_dma_chip {\n\tstruct device *dev;\n\tint id;\n\tint irq;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct dw_dma *dw;\n\tconst struct dw_dma_platform_data *pdata;\n};\n\nstruct dw_dma_chip_pdata {\n\tconst struct dw_dma_platform_data *pdata;\n\tint (*probe)(struct dw_dma_chip *);\n\tint (*remove)(struct dw_dma_chip *);\n\tstruct dw_dma_chip *chip;\n\tu8 m_master;\n\tu8 p_master;\n};\n\nstruct dw_dma_irq_regs {\n\tu32 XFER;\n\tu32 __pad_XFER;\n\tu32 BLOCK;\n\tu32 __pad_BLOCK;\n\tu32 SRC_TRAN;\n\tu32 __pad_SRC_TRAN;\n\tu32 DST_TRAN;\n\tu32 __pad_DST_TRAN;\n\tu32 ERROR;\n\tu32 __pad_ERROR;\n};\n\nstruct dw_dma_platform_data {\n\tu32 nr_masters;\n\tu32 nr_channels;\n\tu32 chan_allocation_order;\n\tu32 chan_priority;\n\tu32 block_size;\n\tu32 data_width[4];\n\tu32 multi_block[8];\n\tu32 max_burst[8];\n\tu32 protctl;\n\tu32 quirks;\n};\n\nstruct dw_dma_regs {\n\tstruct dw_dma_chan_regs CHAN[8];\n\tstruct dw_dma_irq_regs RAW;\n\tstruct dw_dma_irq_regs STATUS;\n\tstruct dw_dma_irq_regs MASK;\n\tstruct dw_dma_irq_regs CLEAR;\n\tu32 STATUS_INT;\n\tu32 __pad_STATUS_INT;\n\tu32 REQ_SRC;\n\tu32 __pad_REQ_SRC;\n\tu32 REQ_DST;\n\tu32 __pad_REQ_DST;\n\tu32 SGL_REQ_SRC;\n\tu32 __pad_SGL_REQ_SRC;\n\tu32 SGL_REQ_DST;\n\tu32 __pad_SGL_REQ_DST;\n\tu32 LAST_SRC;\n\tu32 __pad_LAST_SRC;\n\tu32 LAST_DST;\n\tu32 __pad_LAST_DST;\n\tu32 CFG;\n\tu32 __pad_CFG;\n\tu32 CH_EN;\n\tu32 __pad_CH_EN;\n\tu32 ID;\n\tu32 __pad_ID;\n\tu32 TEST;\n\tu32 __pad_TEST;\n\tu32 CLASS_PRIORITY0;\n\tu32 __pad_CLASS_PRIORITY0;\n\tu32 CLASS_PRIORITY1;\n\tu32 __pad_CLASS_PRIORITY1;\n\tu32 __reserved;\n\tu32 DWC_PARAMS[8];\n\tu32 MULTI_BLK_TYPE;\n\tu32 MAX_BLK_SIZE;\n\tu32 DW_PARAMS;\n\tu32 COMP_TYPE;\n\tu32 COMP_VERSION;\n\tu32 FIFO_PARTITION0;\n\tu32 __pad_FIFO_PARTITION0;\n\tu32 FIFO_PARTITION1;\n\tu32 __pad_FIFO_PARTITION1;\n\tu32 SAI_ERR;\n\tu32 __pad_SAI_ERR;\n\tu32 GLOBAL_CFG;\n\tu32 __pad_GLOBAL_CFG;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct dyn_event_operations;\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(const char *);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct napi_config;\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint poll_owner;\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n};\n\nstruct e1000_eeprom_info {\n\te1000_eeprom_type type;\n\tu16 word_size;\n\tu16 opcode_bits;\n\tu16 address_bits;\n\tu16 delay_usec;\n\tu16 page_size;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\nstruct e1000_shadow_ram;\n\nstruct e1000_hw {\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tvoid *ce4100_gbe_mdio_base_virt;\n\te1000_mac_type mac_type;\n\te1000_phy_type phy_type;\n\tu32 phy_init_script;\n\te1000_media_type media_type;\n\tvoid *back;\n\tstruct e1000_shadow_ram *eeprom_shadow_ram;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\te1000_fc_type fc;\n\te1000_bus_speed bus_speed;\n\te1000_bus_width bus_width;\n\te1000_bus_type bus_type;\n\tstruct e1000_eeprom_info eeprom;\n\te1000_ms_type master_slave;\n\te1000_ms_type original_master_slave;\n\te1000_ffe_config ffe_config_state;\n\tu32 asf_firmware_present;\n\tu32 eeprom_semaphore_present;\n\tlong unsigned int io_base;\n\tu32 phy_id;\n\tu32 phy_revision;\n\tu32 phy_addr;\n\tu32 original_fc;\n\tu32 txcw;\n\tu32 autoneg_failed;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tu32 mc_filter_type;\n\tu32 num_mc_addrs;\n\tu32 collision_delta;\n\tu32 tx_packet_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tbool tx_pkt_filtering;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tu16 phy_spd_default;\n\tu16 autoneg_advertised;\n\tu16 pci_cmd_word;\n\tu16 fc_high_water;\n\tu16 fc_low_water;\n\tu16 fc_pause_time;\n\tu16 current_ifs_val;\n\tu16 ifs_min_val;\n\tu16 ifs_max_val;\n\tu16 ifs_step_size;\n\tu16 ifs_ratio;\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n\tu8 autoneg;\n\tu8 mdix;\n\tu8 forced_speed_duplex;\n\tu8 wait_autoneg_complete;\n\tu8 dma_fairness;\n\tu8 mac_addr[6];\n\tu8 perm_mac_addr[6];\n\tbool disable_polarity_correction;\n\tbool speed_downgraded;\n\te1000_smart_speed smart_speed;\n\te1000_dsp_config dsp_config_state;\n\tbool get_link_status;\n\tbool serdes_has_link;\n\tbool tbi_compatibility_en;\n\tbool tbi_compatibility_on;\n\tbool laa_is_present;\n\tbool phy_reset_disable;\n\tbool initialize_hw_bits_disable;\n\tbool fc_send_xon;\n\tbool fc_strict_ieee;\n\tbool report_tx_early;\n\tbool adaptive_ifs;\n\tbool ifs_params_forced;\n\tbool in_ifs_mode;\n\tbool mng_reg_access_disabled;\n\tbool leave_av_bit_off;\n\tbool bad_tx_carr_stats_fd;\n\tbool has_smbus;\n};\n\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 txerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorcl;\n\tu64 gorch;\n\tu64 gotcl;\n\tu64 gotch;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rlerrc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 torl;\n\tu64 torh;\n\tu64 totl;\n\tu64 toth;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_info {\n\te1000_cable_length cable_length;\n\te1000_10bt_ext_dist_enable extended_10bt_distance;\n\te1000_rev_polarity cable_polarity;\n\te1000_downshift downshift;\n\te1000_polarity_reversal polarity_correction;\n\te1000_auto_x_mode mdix_mode;\n\te1000_1000t_rx_status local_rx;\n\te1000_1000t_rx_status remote_rx;\n};\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_tx_buffer;\n\nstruct e1000_tx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_tx_buffer *buffer_info;\n\tu16 tdh;\n\tu16 tdt;\n\tbool last_tx_tso;\n};\n\nstruct e1000_rx_buffer;\n\nstruct e1000_rx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_rx_buffer *buffer_info;\n\tstruct sk_buff *rx_skb_top;\n\tint cpu;\n\tu16 rdh;\n\tu16 rdt;\n};\n\nstruct e1000_adapter {\n\tlong unsigned int active_vlans[64];\n\tu16 mng_vlan_id;\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu32 wol;\n\tu32 smartspeed;\n\tu32 en_mng_pt;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tspinlock_t stats_lock;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tu8 fc_autoneg;\n\tstruct e1000_tx_ring *tx_ring;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tu32 gotcl;\n\tu64 gotcl_old;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu8 tx_timeout_factor;\n\tatomic_t tx_fifo_stall;\n\tbool pcix_82544;\n\tbool detect_tx_hung;\n\tbool dump_buffers;\n\tbool (*clean_rx)(struct e1000_adapter *, struct e1000_rx_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_adapter *, struct e1000_rx_ring *, int);\n\tstruct e1000_rx_ring *rx_ring;\n\tstruct napi_struct napi;\n\tint num_tx_queues;\n\tint num_rx_queues;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tbool rx_csum;\n\tu32 gorcl;\n\tu64 gorcl_old;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw hw;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_phy_info phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tu32 test_icr;\n\tstruct e1000_tx_ring test_tx_ring;\n\tstruct e1000_rx_ring test_rx_ring;\n\tint msg_enable;\n\tbool tso_force;\n\tbool smart_power_down;\n\tbool quad_port_a;\n\tlong unsigned int flags;\n\tu32 eeprom_wol;\n\tint bars;\n\tint need_ioport;\n\tbool discarding;\n\tstruct work_struct reset_task;\n\tstruct delayed_work watchdog_task;\n\tstruct delayed_work fifo_stall_task;\n\tstruct delayed_work phy_info_task;\n};\n\nstruct e1000_hw___2;\n\nstruct e1000_mac_operations {\n\ts32 (*id_led_init)(struct e1000_hw___2 *);\n\ts32 (*blink_led)(struct e1000_hw___2 *);\n\tbool (*check_mng_mode)(struct e1000_hw___2 *);\n\ts32 (*check_for_link)(struct e1000_hw___2 *);\n\ts32 (*cleanup_led)(struct e1000_hw___2 *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw___2 *);\n\tvoid (*clear_vfta)(struct e1000_hw___2 *);\n\ts32 (*get_bus_info)(struct e1000_hw___2 *);\n\tvoid (*set_lan_id)(struct e1000_hw___2 *);\n\ts32 (*get_link_up_info)(struct e1000_hw___2 *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw___2 *);\n\ts32 (*led_off)(struct e1000_hw___2 *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw___2 *);\n\ts32 (*init_hw)(struct e1000_hw___2 *);\n\ts32 (*setup_link)(struct e1000_hw___2 *);\n\ts32 (*setup_physical_interface)(struct e1000_hw___2 *);\n\ts32 (*setup_led)(struct e1000_hw___2 *);\n\tvoid (*write_vfta)(struct e1000_hw___2 *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw___2 *);\n\tint (*rar_set)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw___2 *);\n\tu32 (*rar_get_count)(struct e1000_hw___2 *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type type;\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tenum e1000_serdes_link_state serdes_link_state;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tu16 refresh_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_phy_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*cfg_on_link_up)(struct e1000_hw___2 *);\n\ts32 (*check_polarity)(struct e1000_hw___2 *);\n\ts32 (*check_reset_block)(struct e1000_hw___2 *);\n\ts32 (*commit)(struct e1000_hw___2 *);\n\ts32 (*force_speed_duplex)(struct e1000_hw___2 *);\n\ts32 (*get_cfg_done)(struct e1000_hw___2 *);\n\ts32 (*get_cable_length)(struct e1000_hw___2 *);\n\ts32 (*get_info)(struct e1000_hw___2 *);\n\ts32 (*set_page)(struct e1000_hw___2 *, u16);\n\ts32 (*read_reg)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw___2 *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\ts32 (*reset)(struct e1000_hw___2 *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*write_reg)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw___2 *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw___2 *);\n\tvoid (*power_down)(struct e1000_hw___2 *);\n};\n\nstruct e1000_phy_info___2 {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tu32 retry_count;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n\tbool retry_enabled;\n};\n\nstruct e1000_nvm_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*read)(struct e1000_hw___2 *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\tvoid (*reload)(struct e1000_hw___2 *);\n\ts32 (*update)(struct e1000_hw___2 *);\n\ts32 (*valid_led_default)(struct e1000_hw___2 *, u16 *);\n\ts32 (*validate)(struct e1000_hw___2 *);\n\ts32 (*write)(struct e1000_hw___2 *, u16, u16, u16 *);\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_width width;\n\tu16 func;\n};\n\nstruct e1000_dev_spec_82571 {\n\tbool laa_is_present;\n\tu32 smb_counter;\n};\n\nstruct e1000_dev_spec_80003es2lan {\n\tbool mdic_wa_enable;\n};\n\nstruct e1000_shadow_ram___2 {\n\tu16 value;\n\tbool modified;\n};\n\nstruct e1000_dev_spec_ich8lan {\n\tbool kmrn_lock_loss_workaround_enabled;\n\tstruct e1000_shadow_ram___2 shadow_ram[2048];\n\tbool nvm_k1_enabled;\n\tbool eee_disable;\n\tu16 eee_lp_ability;\n\tenum e1000_ulp_state ulp_state;\n};\n\nstruct e1000_adapter___2;\n\nstruct e1000_hw___2 {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *hw_addr;\n\tvoid *flash_address;\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info___2 phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82571 e82571;\n\t\tstruct e1000_dev_spec_80003es2lan e80003es2lan;\n\t\tstruct e1000_dev_spec_ich8lan ich8lan;\n\t} dev_spec;\n};\n\nstruct e1000_hw_stats___2 {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_regs {\n\tu16 bmcr;\n\tu16 bmsr;\n\tu16 advertise;\n\tu16 lpa;\n\tu16 expansion;\n\tu16 ctrl1000;\n\tu16 stat1000;\n\tu16 estatus;\n};\n\nstruct e1000_buffer;\n\nstruct e1000_ring {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\tvoid *head;\n\tvoid *tail;\n\tstruct e1000_buffer *buffer_info;\n\tchar name[21];\n\tu32 ims_val;\n\tu32 itr_val;\n\tvoid *itr_register;\n\tint set_itr;\n\tstruct sk_buff *rx_skb_top;\n};\n\nstruct ifreq;\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct ptp_pin_desc;\n\nstruct ptp_system_timestamp;\n\nstruct system_device_crosststamp;\n\nstruct ptp_clock_request;\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[32];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint n_per_lp;\n\tint pps;\n\tunsigned int supported_perout_flags;\n\tunsigned int supported_extts_flags;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\ts32 (*getmaxphase)(struct ptp_clock_info *);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*getcycles64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n\tint (*perout_loopback)(struct ptp_clock_info *, unsigned int, int);\n};\n\nstruct e1000_info;\n\nstruct msix_entry;\n\nstruct ptp_clock;\n\nstruct e1000_adapter___2 {\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tstruct timer_list blink_timer;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tconst struct e1000_info *ei;\n\tlong unsigned int active_vlans[64];\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu16 mng_vlan_id;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu16 eeprom_vers;\n\tlong unsigned int state;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct e1000_ring *tx_ring;\n\tu32 tx_fifo_limit;\n\tstruct napi_struct napi;\n\tunsigned int uncorr_errors;\n\tunsigned int corr_errors;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tbool detect_tx_hung;\n\tbool tx_hang_recheck;\n\tu8 tx_timeout_factor;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 gotc;\n\tu64 gotc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu32 tx_dma_failed;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tlong: 64;\n\tlong: 64;\n\tbool (*clean_rx)(struct e1000_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_ring *, int, gfp_t);\n\tstruct e1000_ring *rx_ring;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu64 rx_hdr_split;\n\tu32 gorc;\n\tu64 gorc_old;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_dma_failed;\n\tu32 rx_hwtstamp_cleared;\n\tunsigned int rx_ps_pages;\n\tu16 rx_ps_bsize0;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw___2 hw;\n\tspinlock_t stats64_lock;\n\tstruct e1000_hw_stats___2 stats;\n\tstruct e1000_phy_info___2 phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tstruct e1000_phy_regs phy_regs;\n\tstruct e1000_ring test_tx_ring;\n\tstruct e1000_ring test_rx_ring;\n\tu32 test_icr;\n\tu32 msg_enable;\n\tunsigned int num_vectors;\n\tstruct msix_entry *msix_entries;\n\tint int_mode;\n\tu32 eiac_mask;\n\tu32 eeprom_wol;\n\tu32 wol;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\tbool fc_autoneg;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tstruct work_struct downshift_task;\n\tstruct work_struct update_phy_task;\n\tstruct work_struct print_hang_task;\n\tint phy_hang_count;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tstruct kernel_hwtstamp_config hwtstamp_config;\n\tstruct delayed_work systim_overflow_work;\n\tstruct sk_buff *tx_hwtstamp_skb;\n\tlong unsigned int tx_hwtstamp_start;\n\tstruct work_struct tx_hwtstamp_work;\n\tspinlock_t systim_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct pm_qos_request pm_qos_req;\n\tlong int ptp_delta;\n\tu16 eee_advert;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct e1000_ps_page;\n\nstruct e1000_buffer {\n\tdma_addr_t dma;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int time_stamp;\n\t\t\tu16 length;\n\t\t\tu16 next_to_watch;\n\t\t\tunsigned int segs;\n\t\t\tunsigned int bytecount;\n\t\t\tu16 mapped_as_page;\n\t\t};\n\t\tstruct {\n\t\t\tstruct e1000_ps_page *ps_pages;\n\t\t\tstruct page *page;\n\t\t};\n\t};\n};\n\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss;\n\t\t\tu8 ipcso;\n\t\t\t__le16 ipcse;\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss;\n\t\t\tu8 tucso;\n\t\t\t__le16 tucse;\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 hdr_len;\n\t\t\t__le16 mss;\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\nstruct e1000_info {\n\tenum e1000_mac_type mac;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\ts32 (*get_variants)(struct e1000_adapter___2 *);\n\tconst struct e1000_mac_operations *mac_ops;\n\tconst struct e1000_phy_operations *phy_ops;\n\tconst struct e1000_nvm_operations *nvm_ops;\n};\n\nstruct e1000_opt_list {\n\tint i;\n\tchar *str;\n};\n\nstruct e1000_option {\n\tenum {\n\t\tenable_option = 0,\n\t\trange_option = 1,\n\t\tlist_option = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tconst struct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_option___2 {\n\tenum {\n\t\tenable_option___2 = 0,\n\t\trange_option___2 = 1,\n\t\tlist_option___2 = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tstruct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_ps_page {\n\tstruct page *page;\n\tu64 dma;\n};\n\nstruct e1000_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nstruct e1000_rx_buffer {\n\tunion {\n\t\tstruct page *page;\n\t\tu8 *data;\n\t} rxbuf;\n\tdma_addr_t dma;\n};\n\nstruct e1000_rx_desc {\n\t__le64 buffer_addr;\n\t__le16 length;\n\t__le16 csum;\n\tu8 status;\n\tu8 errors;\n\t__le16 special;\n};\n\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t__le64 buffer_addr[4];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length0;\n\t\t\t__le16 vlan;\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t__le16 length[3];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb;\n};\n\nstruct e1000_shadow_ram {\n\tu16 eeprom_word;\n\tbool modified;\n};\n\nstruct e1000_stats {\n\tchar stat_string[32];\n\tint type;\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct e1000_tx_buffer {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n\tlong unsigned int time_stamp;\n\tu16 length;\n\tu16 next_to_watch;\n\tbool mapped_as_page;\n\tshort unsigned int segs;\n\tunsigned int bytecount;\n};\n\nstruct e1000_tx_desc {\n\t__le64 buffer_addr;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length;\n\t\t\tu8 cso;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 css;\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\nstruct e820_entry {\n\tu64 addr;\n\tu64 size;\n\tenum e820_type type;\n} __attribute__((packed));\n\nstruct e820_table {\n\tu32 nr_entries;\n\tstruct e820_entry entries[320];\n};\n\nstruct usb_device;\n\nstruct each_dev_arg {\n\tvoid *data;\n\tint (*fn)(struct usb_device *, void *);\n};\n\nstruct early_load_data {\n\tu32 old_rev;\n\tu32 new_rev;\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\tunion {\n\t\t__u32 padding[5];\n\t\tstruct {\n\t\t\t__u8 addr_recv;\n\t\t\t__u8 addr_dest;\n\t\t\t__u8 padding0[2];\n\t\t\t__u32 padding1[4];\n\t\t};\n\t};\n};\n\nstruct gpio_desc;\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct ktermios;\n\nstruct uart_state;\n\nstruct uart_ops;\n\nstruct serial_port_device;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int ctrl_id;\n\tunsigned int port_id;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char quirks;\n\tenum uart_iotype iotype;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tupf_t flags;\n\tupstat_t status;\n\tbool hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int frame_time;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tstruct serial_port_device *port_dev;\n\tlong unsigned int sysrq;\n\tu8 sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tunsigned char console_reinit;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct serial_rs485 rs485_supported;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct gpio_desc *rs485_rx_during_tx_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tstruct uart_port port;\n\tchar options[32];\n\tunsigned int baud;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nstruct eb_fence {\n\tstruct drm_syncobj *syncobj;\n\tstruct dma_fence *dma_fence;\n\tu64 value;\n\tstruct dma_fence_chain *chain_fence;\n};\n\nstruct eb_vma {\n\tstruct i915_vma *vma;\n\tunsigned int flags;\n\tstruct drm_i915_gem_exec_object2 *exec;\n\tstruct list_head bind_link;\n\tstruct list_head reloc_link;\n\tstruct hlist_node node;\n\tu32 handle;\n};\n\nstruct ebitmap_node {\n\tstruct ebitmap_node *next;\n\tlong unsigned int maps[6];\n\tu32 startbit;\n};\n\nstruct td;\n\nstruct ed {\n\t__hc32 hwINFO;\n\t__hc32 hwTailP;\n\t__hc32 hwHeadP;\n\t__hc32 hwNextED;\n\tdma_addr_t dma;\n\tstruct td *dummy;\n\tstruct ed *ed_next;\n\tstruct ed *ed_prev;\n\tstruct list_head td_list;\n\tstruct list_head in_use_list;\n\tu8 state;\n\tu8 type;\n\tu8 branch;\n\tu16 interval;\n\tu16 load;\n\tu16 last_iso;\n\tu16 tick;\n\tunsigned int takeback_wdh_cnt;\n\tstruct td *pending_td;\n\tlong: 64;\n};\n\nstruct est_timings {\n\tu8 t1;\n\tu8 t2;\n\tu8 mfg_rsvd;\n};\n\nstruct edid {\n\tu8 header[8];\n\tunion {\n\t\tstruct drm_edid_product_id product_id;\n\t\tstruct {\n\t\t\tu8 mfg_id[2];\n\t\t\tu8 prod_code[2];\n\t\t\tu32 serial;\n\t\t\tu8 mfg_week;\n\t\t\tu8 mfg_year;\n\t\t} __attribute__((packed));\n\t};\n\tu8 version;\n\tu8 revision;\n\tu8 input;\n\tu8 width_cm;\n\tu8 height_cm;\n\tu8 gamma;\n\tu8 features;\n\tu8 red_green_lo;\n\tu8 blue_white_lo;\n\tu8 red_x;\n\tu8 red_y;\n\tu8 green_x;\n\tu8 green_y;\n\tu8 blue_x;\n\tu8 blue_y;\n\tu8 white_x;\n\tu8 white_y;\n\tstruct est_timings established_timings;\n\tstruct std_timing standard_timings[8];\n\tstruct detailed_timing detailed_timings[4];\n\tu8 extensions;\n\tu8 checksum;\n};\n\nstruct edid_quirk {\n\tconst struct drm_edid_ident ident;\n\tu32 quirks;\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[2];\n\tlong unsigned int advertised[2];\n\tlong unsigned int lp_advertised[2];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct eeepc_cpufv {\n\tint num;\n\tint cur;\n};\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct eeepc_laptop {\n\tacpi_handle handle;\n\tu32 cm_supported;\n\tbool cpufv_disabled;\n\tbool hotplug_disabled;\n\tu16 event_count[128];\n\tstruct platform_device *platform_device;\n\tstruct acpi_device *device;\n\tstruct backlight_device *backlight_device;\n\tstruct input_dev *inputdev;\n\tstruct rfkill *wlan_rfkill;\n\tstruct rfkill *bluetooth_rfkill;\n\tstruct rfkill *wwan3g_rfkill;\n\tstruct rfkill *wimax_rfkill;\n\tstruct hotplug_slot hotplug_slot;\n\tstruct mutex hotplug_lock;\n\tstruct led_classdev tpd_led;\n\tint tpd_led_wk;\n\tstruct workqueue_struct *led_workqueue;\n\tstruct work_struct tpd_led_work;\n};\n\nstruct eeprom_93cx6 {\n\tvoid *data;\n\tvoid (*register_read)(struct eeprom_93cx6 *);\n\tvoid (*register_write)(struct eeprom_93cx6 *);\n\tint width;\n\tunsigned int quirks;\n\tchar drive_data;\n\tchar reg_data_in;\n\tchar reg_data_out;\n\tchar reg_data_clock;\n\tchar reg_chip_select;\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\ntypedef efi_status_t efi_get_time_t(efi_time_t *, efi_time_cap_t *);\n\ntypedef efi_status_t efi_set_time_t(efi_time_t *);\n\ntypedef efi_status_t efi_get_wakeup_time_t(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\ntypedef efi_status_t efi_set_wakeup_time_t(efi_bool_t, efi_time_t *);\n\ntypedef efi_status_t efi_get_variable_t(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\ntypedef efi_status_t efi_get_next_variable_t(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\ntypedef efi_status_t efi_set_variable_t(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\ntypedef efi_status_t efi_query_variable_info_t(u32, u64 *, u64 *, u64 *);\n\ntypedef efi_status_t efi_update_capsule_t(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\ntypedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\ntypedef efi_status_t efi_get_next_high_mono_count_t(u32 *);\n\ntypedef void efi_reset_system_t(int, efi_status_t, long unsigned int, efi_char16_t *);\n\nstruct efi_memory_map {\n\tphys_addr_t phys_map;\n\tvoid *map;\n\tvoid *map_end;\n\tint nr_map;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nstruct efi {\n\tconst efi_runtime_services_t *runtime;\n\tunsigned int runtime_version;\n\tunsigned int runtime_supported_mask;\n\tlong unsigned int acpi;\n\tlong unsigned int acpi20;\n\tlong unsigned int smbios;\n\tlong unsigned int smbios3;\n\tlong unsigned int esrt;\n\tlong unsigned int tpm_log;\n\tlong unsigned int tpm_final_log;\n\tlong unsigned int ovmf_debug_log;\n\tlong unsigned int mokvar_table;\n\tlong unsigned int coco_secret;\n\tlong unsigned int unaccepted;\n\tefi_get_time_t *get_time;\n\tefi_set_time_t *set_time;\n\tefi_get_wakeup_time_t *get_wakeup_time;\n\tefi_set_wakeup_time_t *set_wakeup_time;\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_info_t *query_variable_info;\n\tefi_query_variable_info_t *query_variable_info_nonblocking;\n\tefi_update_capsule_t *update_capsule;\n\tefi_query_capsule_caps_t *query_capsule_caps;\n\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\tefi_reset_system_t *reset_system;\n\tstruct efi_memory_map memmap;\n\tlong unsigned int flags;\n};\n\nstruct efi_mem_range {\n\tstruct range range;\n\tu64 attribute;\n};\n\nstruct efi_memory_map_data {\n\tphys_addr_t phys_map;\n\tlong unsigned int size;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nunion efi_rts_args {\n\tstruct {\n\t\tefi_time_t *time;\n\t\tefi_time_cap_t *capabilities;\n\t} GET_TIME;\n\tstruct {\n\t\tefi_time_t *time;\n\t} SET_TIME;\n\tstruct {\n\t\tefi_bool_t *enabled;\n\t\tefi_bool_t *pending;\n\t\tefi_time_t *time;\n\t} GET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_bool_t enable;\n\t\tefi_time_t *time;\n\t} SET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 *attr;\n\t\tlong unsigned int *data_size;\n\t\tvoid *data;\n\t} GET_VARIABLE;\n\tstruct {\n\t\tlong unsigned int *name_size;\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t} GET_NEXT_VARIABLE;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 attr;\n\t\tlong unsigned int data_size;\n\t\tvoid *data;\n\t} SET_VARIABLE;\n\tstruct {\n\t\tu32 attr;\n\t\tu64 *storage_space;\n\t\tu64 *remaining_space;\n\t\tu64 *max_variable_size;\n\t} QUERY_VARIABLE_INFO;\n\tstruct {\n\t\tu32 *high_count;\n\t} GET_NEXT_HIGH_MONO_COUNT;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tlong unsigned int sg_list;\n\t} UPDATE_CAPSULE;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tu64 *max_size;\n\t\tint *reset_type;\n\t} QUERY_CAPSULE_CAPS;\n\tstruct {\n\t\tefi_status_t (*acpi_prm_handler)(u64, void *);\n\t\tu64 param_buffer_addr;\n\t\tvoid *context;\n\t} ACPI_PRM_HANDLER;\n};\n\nstruct efi_runtime_map_entry {\n\tefi_memory_desc_t md;\n\tstruct kobject kobj;\n};\n\nstruct efi_runtime_work {\n\tunion efi_rts_args *args;\n\tefi_status_t status;\n\tstruct work_struct work;\n\tenum efi_rts_ids efi_rts_id;\n\tstruct completion efi_rts_comp;\n\tconst void *caller;\n};\n\nstruct efi_setup_data {\n\tu64 fw_vendor;\n\tu64 __unused;\n\tu64 tables;\n\tu64 smbios;\n\tu64 reserved[8];\n};\n\nstruct efi_system_resource_entry_v1 {\n\tefi_guid_t fw_class;\n\tu32 fw_type;\n\tu32 fw_version;\n\tu32 lowest_supported_fw_version;\n\tu32 capsule_flags;\n\tu32 last_attempt_version;\n\tu32 last_attempt_status;\n};\n\nstruct efi_system_resource_table {\n\tu32 fw_resource_count;\n\tu32 fw_resource_count_max;\n\tu64 fw_resource_version;\n\tu8 entries[0];\n};\n\nstruct efi_tcg2_final_events_table {\n\tu64 version;\n\tu64 nr_events;\n\tu8 events[0];\n};\n\nstruct efi_unaccepted_memory {\n\tu32 version;\n\tu32 unit_size;\n\tu64 phys_base;\n\tu64 size;\n\tlong unsigned int bitmap[0];\n};\n\ntypedef efi_status_t efi_query_variable_store_t(u32, long unsigned int, bool);\n\nstruct efivar_operations {\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_store_t *query_variable_store;\n\tefi_query_variable_info_t *query_variable_info;\n};\n\nstruct efivars {\n\tstruct kset *kset;\n\tconst struct efivar_operations *ops;\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct ehci_dev {\n\tu32 bus;\n\tu32 slot;\n\tu32 func;\n};\n\nstruct usb_hcd;\n\nstruct ehci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\nstruct ehci_qh;\n\nstruct ehci_itd;\n\nstruct ehci_sitd;\n\nstruct ehci_fstn;\n\nunion ehci_shadow {\n\tstruct ehci_qh *qh;\n\tstruct ehci_itd *itd;\n\tstruct ehci_sitd *sitd;\n\tstruct ehci_fstn *fstn;\n\t__le32 *hw_next;\n\tvoid *ptr;\n};\n\nstruct ehci_fstn {\n\t__le32 hw_next;\n\t__le32 hw_prev;\n\tdma_addr_t fstn_dma;\n\tunion ehci_shadow fstn_next;\n\tlong: 64;\n};\n\nstruct ehci_regs;\n\nstruct ehci_hcd {\n\tenum ehci_hrtimer_event next_hrtimer_event;\n\tunsigned int enabled_hrtimer_events;\n\tktime_t hr_timeouts[12];\n\tstruct hrtimer hrtimer;\n\tint PSS_poll_count;\n\tint ASS_poll_count;\n\tint died_poll_count;\n\tstruct ehci_caps *caps;\n\tstruct ehci_regs *regs;\n\tstruct ehci_dbg_port *debug;\n\t__u32 hcs_params;\n\tspinlock_t lock;\n\tenum ehci_rh_state rh_state;\n\tbool scanning: 1;\n\tbool need_rescan: 1;\n\tbool intr_unlinking: 1;\n\tbool iaa_in_progress: 1;\n\tbool async_unlinking: 1;\n\tbool shutdown: 1;\n\tstruct ehci_qh *qh_scan_next;\n\tstruct ehci_qh *async;\n\tstruct ehci_qh *dummy;\n\tstruct list_head async_unlink;\n\tstruct list_head async_idle;\n\tunsigned int async_unlink_cycle;\n\tunsigned int async_count;\n\t__le32 old_current;\n\t__le32 old_token;\n\tunsigned int periodic_size;\n\t__le32 *periodic;\n\tdma_addr_t periodic_dma;\n\tstruct list_head intr_qh_list;\n\tunsigned int i_thresh;\n\tunion ehci_shadow *pshadow;\n\tstruct list_head intr_unlink_wait;\n\tstruct list_head intr_unlink;\n\tunsigned int intr_unlink_wait_cycle;\n\tunsigned int intr_unlink_cycle;\n\tunsigned int now_frame;\n\tunsigned int last_iso_frame;\n\tunsigned int intr_count;\n\tunsigned int isoc_count;\n\tunsigned int periodic_count;\n\tunsigned int uframe_periodic_max;\n\tstruct list_head cached_itd_list;\n\tstruct ehci_itd *last_itd_to_free;\n\tstruct list_head cached_sitd_list;\n\tstruct ehci_sitd *last_sitd_to_free;\n\tlong unsigned int reset_done[15];\n\tlong unsigned int bus_suspended;\n\tlong unsigned int companion_ports;\n\tlong unsigned int owned_ports;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int suspended_ports;\n\tlong unsigned int resuming_ports;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *qtd_pool;\n\tstruct dma_pool *itd_pool;\n\tstruct dma_pool *sitd_pool;\n\tunsigned int random_frame;\n\tlong unsigned int next_statechange;\n\tktime_t last_periodic_enable;\n\tu32 command;\n\tunsigned int no_selective_suspend: 1;\n\tunsigned int has_fsl_port_bug: 1;\n\tunsigned int has_fsl_hs_errata: 1;\n\tunsigned int has_fsl_susp_errata: 1;\n\tunsigned int has_ci_pec_bug: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_capbase: 1;\n\tunsigned int has_amcc_usb23: 1;\n\tunsigned int need_io_watchdog: 1;\n\tunsigned int amd_pll_fix: 1;\n\tunsigned int use_dummy_qh: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int frame_index_bug: 1;\n\tunsigned int need_oc_pp_cycle: 1;\n\tunsigned int imx28_write_fix: 1;\n\tunsigned int spurious_oc: 1;\n\tunsigned int is_aspeed: 1;\n\tunsigned int zx_wakeup_clear_needed: 1;\n\t__le32 *ohci_hcctrl_reg;\n\tunsigned int has_hostpc: 1;\n\tunsigned int has_tdi_phy_lpm: 1;\n\tunsigned int has_ppcd: 1;\n\tu8 sbrn;\n\tu8 bandwidth[64];\n\tu8 tt_budget[64];\n\tstruct list_head tt_list;\n\tlong unsigned int priv[0];\n};\n\nstruct ehci_iso_packet {\n\tu64 bufp;\n\t__le32 transaction;\n\tu8 cross;\n\tu32 buf1;\n};\n\nstruct ehci_iso_sched {\n\tstruct list_head td_list;\n\tunsigned int span;\n\tunsigned int first_packet;\n\tstruct ehci_iso_packet packet[0];\n};\n\nstruct usb_host_endpoint;\n\nstruct ehci_per_sched {\n\tstruct usb_device *udev;\n\tstruct usb_host_endpoint *ep;\n\tstruct list_head ps_list;\n\tu16 tt_usecs;\n\tu16 cs_mask;\n\tu16 period;\n\tu16 phase;\n\tu8 bw_phase;\n\tu8 phase_uf;\n\tu8 usecs;\n\tu8 c_usecs;\n\tu8 bw_uperiod;\n\tu8 bw_period;\n};\n\nstruct ehci_qh_hw;\n\nstruct ehci_iso_stream {\n\tstruct ehci_qh_hw *hw;\n\tu8 bEndpointAddress;\n\tu8 highspeed;\n\tstruct list_head td_list;\n\tstruct list_head free_list;\n\tstruct ehci_per_sched ps;\n\tunsigned int next_uframe;\n\t__le32 splits;\n\tu16 uperiod;\n\tu16 maxp;\n\tunsigned int bandwidth;\n\t__le32 buf0;\n\t__le32 buf1;\n\t__le32 buf2;\n\t__le32 address;\n};\n\nstruct ehci_itd {\n\t__le32 hw_next;\n\t__le32 hw_transaction[8];\n\t__le32 hw_bufp[7];\n\t__le32 hw_bufp_hi[7];\n\tdma_addr_t itd_dma;\n\tunion ehci_shadow itd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head itd_list;\n\tunsigned int frame;\n\tunsigned int pg;\n\tunsigned int index[8];\n\tlong: 64;\n};\n\nstruct ehci_qtd;\n\nstruct ehci_qh {\n\tstruct ehci_qh_hw *hw;\n\tdma_addr_t qh_dma;\n\tunion ehci_shadow qh_next;\n\tstruct list_head qtd_list;\n\tstruct list_head intr_node;\n\tstruct ehci_qtd *dummy;\n\tstruct list_head unlink_node;\n\tstruct ehci_per_sched ps;\n\tunsigned int unlink_cycle;\n\tu8 qh_state;\n\tu8 xacterrs;\n\tu8 unlink_reason;\n\tu8 gap_uf;\n\tunsigned int is_out: 1;\n\tunsigned int clearing_tt: 1;\n\tunsigned int dequeue_during_giveback: 1;\n\tunsigned int should_be_inactive: 1;\n};\n\nstruct ehci_qh_hw {\n\t__le32 hw_next;\n\t__le32 hw_info1;\n\t__le32 hw_info2;\n\t__le32 hw_current;\n\t__le32 hw_qtd_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ehci_qtd {\n\t__le32 hw_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tdma_addr_t qtd_dma;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tunion {\n\t\tu32 port_status[15];\n\t\tstruct {\n\t\t\tu32 reserved3[9];\n\t\t\tu32 usbmode;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved4;\n\t\t\tu32 hostpc[15];\n\t\t};\n\t\tu32 brcm_insnreg[4];\n\t};\n\tu32 reserved5[2];\n\tu32 usbmode_ex;\n};\n\nstruct ehci_sitd {\n\t__le32 hw_next;\n\t__le32 hw_fullspeed_ep;\n\t__le32 hw_uframe;\n\t__le32 hw_results;\n\t__le32 hw_buf[2];\n\t__le32 hw_backpointer;\n\t__le32 hw_buf_hi[2];\n\tdma_addr_t sitd_dma;\n\tunion ehci_shadow sitd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head sitd_list;\n\tunsigned int frame;\n\tunsigned int index;\n};\n\nstruct usb_tt;\n\nstruct ehci_tt {\n\tu16 bandwidth[8];\n\tstruct list_head tt_list;\n\tstruct list_head ps_list;\n\tstruct usb_tt *usb_tt;\n\tint tt_port;\n};\n\nstruct element {\n\tu8 id;\n\tu8 datalen;\n\tu8 data[0];\n};\n\nstruct elevator_queue;\n\nstruct io_cq;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf32_shdr {\n\tElf32_Word sh_name;\n\tElf32_Word sh_type;\n\tElf32_Word sh_flags;\n\tElf32_Addr sh_addr;\n\tElf32_Off sh_offset;\n\tElf32_Word sh_size;\n\tElf32_Word sh_link;\n\tElf32_Word sh_info;\n\tElf32_Word sh_addralign;\n\tElf32_Word sh_entsize;\n};\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_note {\n\tElf64_Word n_namesz;\n\tElf64_Word n_descsz;\n\tElf64_Word n_type;\n};\n\ntypedef struct elf64_note Elf64_Nhdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct elf64_rela {\n\tElf64_Addr r_offset;\n\tElf64_Xword r_info;\n\tElf64_Sxword r_addend;\n};\n\ntypedef struct elf64_rela Elf64_Rela;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\ntypedef struct elf64_shdr Elf64_Shdr;\n\nstruct elf64_sym {\n\tElf64_Word st_name;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf64_Half st_shndx;\n\tElf64_Addr st_value;\n\tElf64_Xword st_size;\n};\n\ntypedef struct elf64_sym Elf64_Sym;\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tcompat_siginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info___2;\n\nstruct elf_note_info___2 {\n\tstruct elf_thread_core_info___2 *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info___2 {\n\tstruct elf_thread_core_info___2 *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct compat_elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct trace_event_file;\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nunion encrypted_buff {\n\tu8 e_kpub_km[128];\n\tu8 e_kh_km_m[32];\n\tstruct {\n\t\tu8 e_kh_km[16];\n\t\tu8 m[16];\n\t};\n};\n\nstruct xdr_buf;\n\nstruct encryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tint pos;\n\tstruct xdr_buf *outbuf;\n\tstruct page **pages;\n\tstruct scatterlist infrags[4];\n\tstruct scatterlist outfrags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct engine_mmio_base {\n\tu32 graphics_ver: 8;\n\tu32 base: 24;\n};\n\nstruct engine_info {\n\tu8 class;\n\tu8 instance;\n\tstruct engine_mmio_base mmio_bases[3];\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\nstruct usb_endpoint_descriptor;\n\nstruct ep_device {\n\tstruct usb_endpoint_descriptor *desc;\n\tstruct usb_device *udev;\n\tstruct device dev;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct ephy_info {\n\tunsigned int offset;\n\tu16 mask;\n\tu16 bits;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n} __attribute__((packed));\n\nstruct epoll_event {\n\t__poll_t events;\n\t__u64 data;\n} __attribute__((packed));\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct trace_eprobe;\n\nstruct eprobe_data {\n\tstruct trace_event_file *file;\n\tstruct trace_eprobe *ep;\n};\n\nstruct eprobe_trace_entry_head {\n\tstruct trace_entry ent;\n};\n\nstruct equiv_cpu_entry {\n\tu32 installed_cpu;\n\tu32 fixed_errata_mask;\n\tu32 fixed_errata_compare;\n\tu16 equiv_cpu;\n\tu16 res;\n};\n\nstruct equiv_cpu_table {\n\tunsigned int num_entries;\n\tstruct equiv_cpu_entry *entry;\n};\n\nstruct er_account {\n\traw_spinlock_t lock;\n\tu64 config;\n\tu64 reg;\n\tatomic_t ref;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu16 pos;\n\tu64 ts;\n};\n\nstruct error_info {\n\tshort unsigned int code12;\n\tshort unsigned int size;\n};\n\nstruct error_info2 {\n\tunsigned char code1;\n\tunsigned char code2_min;\n\tunsigned char code2_max;\n\tconst char *str;\n\tconst char *fmt;\n};\n\nstruct errormap {\n\tchar *name;\n\tint val;\n\tint namelen;\n\tstruct hlist_node list;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct ip_esp_hdr;\n\nstruct esp_info {\n\tstruct ip_esp_hdr *esph;\n\t__be64 seqno;\n\tint tfclen;\n\tint tailen;\n\tint plen;\n\tint clen;\n\tint len;\n\tint nfrags;\n\t__u8 proto;\n\tbool inplace;\n};\n\nstruct esp_output_extra {\n\t__be32 seqhi;\n\tu32 esphoff;\n};\n\nstruct esp_skb_cb {\n\tstruct xfrm_skb_cb xfrm;\n\tvoid *tmp;\n};\n\nstruct esre_entry;\n\nstruct esre_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct esre_entry *, char *);\n};\n\nstruct esre_entry {\n\tunion {\n\t\tstruct efi_system_resource_entry_v1 *esre1;\n\t} esre;\n\tstruct kobject kobj;\n\tstruct list_head list;\n};\n\nstruct estack_pages {\n\tu32 offs;\n\tu16 size;\n\tu16 type;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct firmware;\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[2];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[2];\n\t\tlong unsigned int advertising[2];\n\t\tlong unsigned int lp_advertising[2];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_regs;\n\nstruct ethtool_wolinfo;\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_test;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxnfc;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_ts_stats;\n\nstruct ethtool_tunable;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_device;\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\t__u64 ring_cookie;\n\t__u32 location;\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct input_handler;\n\nstruct input_value;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct fasync_struct;\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct event_trigger_data;\n\nstruct ring_buffer_event;\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*parse)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*trigger)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tbool (*count_func)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_data *);\n};\n\nstruct event_counter {\n\tu32 count;\n\tu32 flags;\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nstruct event_header {\n\t__be16 data_len;\n\t__u8 notification_class: 3;\n\t__u8 reserved1: 4;\n\t__u8 nea: 1;\n\t__u8 supp_event_class;\n};\n\nstruct event_mod_load {\n\tstruct list_head list;\n\tchar *module;\n\tchar *match;\n\tchar *system;\n\tchar *event;\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tint flags;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n\tstruct llist_node llist;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventfs_attr {\n\tint mode;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\ntypedef int (*eventfs_callback)(const char *, umode_t *, void **, const struct file_operations **);\n\ntypedef void (*eventfs_release)(const char *, void *);\n\nstruct eventfs_entry {\n\tconst char *name;\n\teventfs_callback callback;\n\teventfs_release release;\n};\n\nstruct eventfs_inode {\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head children;\n\tconst struct eventfs_entry *entries;\n\tconst char *name;\n\tstruct eventfs_attr *entry_attrs;\n\tvoid *data;\n\tstruct eventfs_attr attr;\n\tstruct kref kref;\n\tunsigned int is_freed: 1;\n\tunsigned int is_events: 1;\n\tunsigned int nr_entries: 30;\n\tunsigned int ino;\n};\n\nstruct eventfs_root_inode {\n\tstruct eventfs_inode ei;\n\tstruct dentry *events_dir;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n};\n\nstruct ewma__engine_latency {\n\tlong unsigned int internal;\n};\n\nstruct ewma_avg_signal {\n\tlong unsigned int internal;\n};\n\nstruct ewma_beacon_signal {\n\tlong unsigned int internal;\n};\n\nstruct ewma_pkt_len {\n\tlong unsigned int internal;\n};\n\nstruct ewma_runtime {\n\tlong unsigned int internal;\n};\n\nstruct ewma_signal {\n\tlong unsigned int internal;\n};\n\nstruct exar8250_board;\n\nstruct exar8250 {\n\tunsigned int nr;\n\tunsigned int osc_freq;\n\tstruct exar8250_board *board;\n\tstruct eeprom_93cx6 eeprom;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tconst struct serial_rs485 *rs485_supported;\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n\tvoid (*unregister_gpio)(struct uart_8250_port *);\n};\n\nstruct exception_stacks {\n\tchar DF_stack_guard[0];\n\tchar DF_stack[8192];\n\tchar NMI_stack_guard[0];\n\tchar NMI_stack[8192];\n\tchar DB_stack_guard[0];\n\tchar DB_stack[8192];\n\tchar MCE_stack_guard[0];\n\tchar MCE_stack[8192];\n\tchar VC_stack_guard[0];\n\tchar VC_stack[0];\n\tchar VC2_stack_guard[0];\n\tchar VC2_stack[0];\n\tchar IST_top_guard[0];\n};\n\nstruct exception_table_entry {\n\tint insn;\n\tint fixup;\n\tint data;\n};\n\nstruct exec_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct i915_request;\n\nstruct execlists_capture {\n\tstruct work_struct work;\n\tstruct i915_request *rq;\n\tstruct i915_gpu_coredump *error;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct execmem_cache {\n\tstruct mutex mutex;\n\tstruct maple_tree busy_areas;\n\tstruct maple_tree free_areas;\n\tunsigned int pending_free_cnt;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_cb {\n\tstruct irq_work work;\n\tstruct i915_sw_fence *fence;\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct exit_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__u32 exit_code;\n\t__u32 exit_signal;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct iattr;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_buddy;\n\nstruct ext4_prealloc_space;\n\nstruct ext4_locality_group;\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\text4_grpblk_t ac_orig_goal_len;\n\text4_group_t ac_prefetch_grp;\n\tunsigned int ac_prefetch_ios;\n\tunsigned int ac_prefetch_nr;\n\tint ac_first_err;\n\t__u32 ac_flags;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_cX_found[5];\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct ext4_buddy *ac_e4b;\n\tstruct folio *ac_bitmap_folio;\n\tstruct folio *ac_buddy_folio;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_group_info;\n\nstruct ext4_buddy {\n\tstruct folio *bd_buddy_folio;\n\tvoid *bd_buddy;\n\tstruct folio *bd_bitmap_folio;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_hash {\n\t__le32 hash;\n\t__le32 minor_hash;\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\nstruct ext4_err_translation {\n\tint code;\n\tint errno;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct extent_status;\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_extent;\n\nstruct ext4_extent_idx;\n\nstruct ext4_extent_header;\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_fc_add_range {\n\t__le32 fc_ino;\n\t__u8 fc_ex[12];\n};\n\nstruct ext4_fc_alloc_region {\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tint ino;\n\tint len;\n};\n\nstruct ext4_fc_del_range {\n\t__le32 fc_ino;\n\t__le32 fc_lblk;\n\t__le32 fc_len;\n};\n\nstruct ext4_fc_dentry_info {\n\t__le32 fc_parent_ino;\n\t__le32 fc_ino;\n\t__u8 fc_dname[0];\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n};\n\nstruct ext4_fc_dentry_update {\n\tint fcd_op;\n\tint fcd_parent;\n\tint fcd_ino;\n\tstruct name_snapshot fcd_name;\n\tstruct list_head fcd_list;\n\tstruct list_head fcd_dilist;\n};\n\nstruct ext4_fc_head {\n\t__le32 fc_features;\n\t__le32 fc_tid;\n};\n\nstruct ext4_fc_inode {\n\t__le32 fc_ino;\n\t__u8 fc_raw_inode[0];\n};\n\nstruct ext4_fc_replay_state {\n\tint fc_replay_num_tags;\n\tint fc_replay_expected_off;\n\tint fc_current_pass;\n\tint fc_cur_tag;\n\tint fc_crc;\n\tstruct ext4_fc_alloc_region *fc_regions;\n\tint fc_regions_size;\n\tint fc_regions_used;\n\tint fc_regions_valid;\n\tint *fc_modified_inodes;\n\tint fc_modified_inodes_used;\n\tint fc_modified_inodes_size;\n};\n\nstruct ext4_fc_stats {\n\tunsigned int fc_ineligible_reason_count[13];\n\tlong unsigned int fc_num_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_failed_commits;\n\tlong unsigned int fc_skipped_commits;\n\tlong unsigned int fc_numblks;\n\tu64 s_fc_avg_commit_time;\n};\n\nstruct ext4_fc_tail {\n\t__le32 fc_tid;\n\t__le32 fc_crc;\n};\n\nstruct ext4_fc_tl {\n\t__le16 fc_tag;\n\t__le16 fc_len;\n};\n\nstruct ext4_fc_tl_mem {\n\tu16 fc_tag;\n\tu16 fc_len;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nstruct fscrypt_dummy_policy {};\n\nstruct ext4_fs_context {\n\tchar *s_qf_names[3];\n\tstruct fscrypt_dummy_policy dummy_enc_policy;\n\tint s_jquota_fmt;\n\tshort unsigned int qname_spec;\n\tlong unsigned int vals_s_flags;\n\tlong unsigned int mask_s_flags;\n\tlong unsigned int journal_devnum;\n\tlong unsigned int s_commit_interval;\n\tlong unsigned int s_stripe;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_want_extra_isize;\n\tunsigned int s_li_wait_mult;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int journal_ioprio;\n\tunsigned int vals_s_mount_opt;\n\tunsigned int mask_s_mount_opt;\n\tunsigned int vals_s_mount_opt2;\n\tunsigned int mask_s_mount_opt2;\n\tunsigned int opt_flags;\n\tunsigned int spec;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\text4_fsblk_t s_sb_block;\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\nstruct ext4_getfsmap_info;\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\tint bb_avg_fragment_size_order;\n\text4_grpblk_t bb_largest_free_order;\n\text4_group_t bb_group;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct jbd2_inode;\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tunion {\n\t\tstruct list_head i_orphan;\n\t\tunsigned int i_orphan_idx;\n\t};\n\tstruct list_head i_fc_dilist;\n\tstruct list_head i_fc_list;\n\text4_lblk_t i_fc_lblk_start;\n\text4_lblk_t i_fc_lblk_len;\n\tspinlock_t i_raw_lock;\n\twait_queue_head_t i_fc_wait;\n\tspinlock_t i_fc_lock;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tstruct timespec64 i_crtime;\n\tatomic_t i_prealloc_active;\n\tunsigned int i_reserved_data_blocks;\n\tstruct rb_root i_prealloc_node;\n\trwlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\tu64 i_es_seq;\n\text4_group_t i_last_alloc_group;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tqsize_t i_reserved_quota;\n\tspinlock_t i_block_reservation_lock;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\tstruct dquot *i_dquot[3];\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\trefcount_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n};\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tsector_t io_next_block;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct ext4_journal_trigger {\n\tstruct jbd2_buffer_trigger_type tr_triggers;\n\tstruct super_block *sb;\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tenum ext4_li_mode lr_mode;\n\text4_group_t lr_first_not_zeroed;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n\tu64 m_seq;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n\tint s_jquota_fmt;\n\tchar *s_qf_names[3];\n};\n\nstruct ext4_new_group_data;\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t resize_bg;\n\text4_group_t count;\n};\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct ext4_orphan_block {\n\tatomic_t ob_free_entries;\n\tstruct buffer_head *ob_bh;\n};\n\nstruct ext4_orphan_block_tail {\n\t__le32 ob_magic;\n\t__le32 ob_checksum;\n};\n\nstruct ext4_orphan_info {\n\tint of_blocks;\n\t__u32 of_csum_seed;\n\tstruct ext4_orphan_block *of_binfo;\n};\n\nstruct ext4_prealloc_space {\n\tunion {\n\t\tstruct rb_node inode_node;\n\t\tstruct list_head lg_list;\n\t} pa_node;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tunion {\n\t\trwlock_t *inode_lock;\n\t\tspinlock_t *lg_lock;\n\t} pa_node_lock;\n\tstruct inode *pa_inode;\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct ext4_super_block;\n\nstruct journal_s;\n\nstruct ext4_system_blocks;\n\nstruct flex_groups;\n\nstruct mb_cache;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tlong unsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\tunsigned int s_def_mount_opt2;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct percpu_counter s_sra_exceeded_retry_limit;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct buffer_head *s_mmp_bh;\n\tstruct journal_s *s_journal;\n\tlong unsigned int s_ext4_flags;\n\tstruct mutex s_orphan_lock;\n\tstruct list_head s_orphan;\n\tstruct ext4_orphan_info s_orphan_info;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct file *s_journal_bdev_file;\n\tchar *s_qf_names[3];\n\tint s_jquota_fmt;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *s_system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tatomic_t s_mb_free_pending;\n\tstruct list_head s_freed_data_list[2];\n\tstruct list_head s_discard_list;\n\tstruct work_struct s_discard_work;\n\tatomic_t s_retry_alloc_pending;\n\tstruct xarray *s_mb_avg_fragment_size;\n\tstruct xarray *s_mb_largest_free_orders;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_max_linear_groups;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int s_mb_prefetch;\n\tunsigned int s_mb_prefetch_limit;\n\tunsigned int s_mb_best_avail_max_trim_order;\n\tunsigned int s_sb_update_sec;\n\tunsigned int s_sb_update_kb;\n\text4_group_t *s_mb_last_groups;\n\tunsigned int s_mb_nr_global_goals;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_cX_ex_scanned[5];\n\tatomic_t s_bal_groups_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_stream_goals;\n\tatomic_t s_bal_len_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tatomic64_t s_bal_cX_groups_considered[5];\n\tatomic64_t s_bal_cX_hits[5];\n\tatomic64_t s_bal_cX_failed[5];\n\tatomic_t s_mb_buddies_generated;\n\tatomic64_t s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tlong unsigned int s_err_report_sec;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tlong unsigned int s_last_trim_minblks;\n\tu16 s_min_folio_order;\n\tu16 s_max_folio_order;\n\t__u32 s_csum_seed;\n\tstruct shrinker *s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache *s_ea_block_cache;\n\tstruct mb_cache *s_ea_inode_cache;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_es_lock;\n\tstruct ext4_journal_trigger s_journal_triggers[1];\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tatomic_t s_warning_count;\n\tatomic_t s_msg_count;\n\tstruct fscrypt_dummy_policy s_dummy_enc_policy;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tu64 s_dax_part_off;\n\terrseq_t s_bdev_wb_err;\n\tspinlock_t s_bdev_wb_lock;\n\tspinlock_t s_error_lock;\n\tint s_add_error_count;\n\tint s_first_error_code;\n\t__u32 s_first_error_line;\n\t__u32 s_first_error_ino;\n\t__u64 s_first_error_block;\n\tconst char *s_first_error_func;\n\ttime64_t s_first_error_time;\n\tint s_last_error_code;\n\t__u32 s_last_error_line;\n\t__u32 s_last_error_ino;\n\t__u64 s_last_error_block;\n\tconst char *s_last_error_func;\n\ttime64_t s_last_error_time;\n\tstruct work_struct s_sb_upd_work;\n\tunsigned int s_awu_min;\n\tunsigned int s_awu_max;\n\tatomic_t s_fc_subtid;\n\tstruct list_head s_fc_q[2];\n\tstruct list_head s_fc_dentry_q[2];\n\tunsigned int s_fc_bytes;\n\tstruct mutex s_fc_lock;\n\tstruct buffer_head *s_fc_bh;\n\tstruct ext4_fc_stats s_fc_stats;\n\ttid_t s_fc_ineligible_tid;\n\tstruct ext4_fc_replay_state s_fc_replay_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_orphan_file_inum;\n\t__le16 s_def_resuid_hi;\n\t__le16 s_def_resgid_hi;\n\t__le32 s_reserved[93];\n\t__le32 s_checksum;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n\tu32 ino;\n};\n\nstruct ext4_tune_sb_params {\n\t__u32 set_flags;\n\t__u32 checkinterval;\n\t__u16 errors_behavior;\n\t__u16 mnt_count;\n\t__u16 max_mnt_count;\n\t__u16 raid_stride;\n\t__u64 last_check_time;\n\t__u64 reserved_blocks;\n\t__u64 blocks_count;\n\t__u32 default_mnt_opts;\n\t__u32 reserved_uid;\n\t__u32 reserved_gid;\n\t__u32 raid_stripe_width;\n\t__u16 encoding;\n\t__u16 encoding_flags;\n\t__u8 def_hash_alg;\n\t__u8 pad_1;\n\t__u16 pad_2;\n\t__u32 feature_compat;\n\t__u32 feature_incompat;\n\t__u32 feature_ro_compat;\n\t__u32 set_feature_compat_mask;\n\t__u32 set_feature_incompat_mask;\n\t__u32 set_feature_ro_compat_mask;\n\t__u32 clear_feature_compat_mask;\n\t__u32 clear_feature_incompat_mask;\n\t__u32 clear_feature_ro_compat_mask;\n\t__u8 mount_opts[64];\n\t__u8 pad[68];\n};\n\nstruct ext4_xattr_entry;\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n};\n\nstruct msg_msg;\n\nstruct ext_wait_queue {\n\tstruct task_struct *task;\n\tstruct list_head list;\n\tstruct msg_msg *msg;\n\tint state;\n};\n\nstruct extended_signature {\n\tunsigned int sig;\n\tunsigned int pf;\n\tunsigned int cksum;\n};\n\nstruct extended_sigtable {\n\tunsigned int count;\n\tunsigned int cksum;\n\tunsigned int reserved[3];\n\tstruct extended_signature sigs[0];\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\text4_fsblk_t es_pblk;\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct extra_reg {\n\tunsigned int event;\n\tunsigned int msr;\n\tu64 config_mask;\n\tu64 valid_mask;\n\tint idx;\n\tbool extra_msr_access;\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct failover_ops;\n\nstruct failover {\n\tstruct list_head list;\n\tstruct net_device *failover_dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct failover_ops *ops;\n};\n\nstruct failover_ops {\n\tint (*slave_pre_register)(struct net_device *, struct net_device *);\n\tint (*slave_register)(struct net_device *, struct net_device *);\n\tint (*slave_pre_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_link_change)(struct net_device *, struct net_device *);\n\tint (*slave_name_change)(struct net_device *, struct net_device *);\n\trx_handler_result_t (*slave_handle_frame)(struct sk_buff **);\n};\n\nstruct fanotify_response_info_header {\n\t__u8 type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_response_info_audit_rule {\n\tstruct fanotify_response_info_header hdr;\n\t__u32 rule_number;\n\t__u32 subj_trust;\n\t__u32 obj_trust;\n};\n\nstruct fanout_args {\n\t__u16 id;\n\t__u16 type_flags;\n\t__u32 max_num_members;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_bios_param_block {\n\tu16 fat_sector_size;\n\tu8 fat_sec_per_clus;\n\tu16 fat_reserved;\n\tu8 fat_fats;\n\tu16 fat_dir_entries;\n\tu16 fat_sectors;\n\tu16 fat_fat_length;\n\tu32 fat_total_sect;\n\tu8 fat16_state;\n\tu32 fat16_vol_id;\n\tu32 fat32_length;\n\tu32 fat32_root_cluster;\n\tu16 fat32_info_sector;\n\tu8 fat32_state;\n\tu32 fat32_vol_id;\n};\n\nstruct fat_boot_fsinfo {\n\t__le32 signature1;\n\t__le32 reserved1[120];\n\t__le32 signature2;\n\t__le32 free_clusters;\n\t__le32 next_cluster;\n\t__le32 reserved2[4];\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fat_cache {\n\tstruct list_head cache_list;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_cache_id {\n\tunsigned int id;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_entry {\n\tint entry;\n\tunion {\n\t\tu8 *ent12_p[2];\n\t\t__le16 *ent16_p;\n\t\t__le32 *ent32_p;\n\t} u;\n\tint nr_bhs;\n\tstruct buffer_head *bhs[2];\n\tstruct inode *fat_inode;\n};\n\nstruct fat_fid {\n\tu32 i_gen;\n\tu32 i_pos_low;\n\tu16 i_pos_hi;\n\tu16 parent_i_pos_hi;\n\tu32 parent_i_pos_low;\n\tu32 parent_i_gen;\n};\n\nstruct fat_floppy_defaults {\n\tunsigned int nr_sectors;\n\tunsigned int sec_per_clus;\n\tunsigned int dir_entries;\n\tunsigned int media;\n\tunsigned int fat_length;\n};\n\nstruct fat_ioctl_filldir_callback {\n\tstruct dir_context ctx;\n\tvoid *dirent;\n\tint result;\n\tconst char *longname;\n\tint long_len;\n\tconst char *shortname;\n\tint short_len;\n};\n\nstruct fat_mount_options {\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tshort unsigned int fs_fmask;\n\tshort unsigned int fs_dmask;\n\tshort unsigned int codepage;\n\tint time_offset;\n\tchar *iocharset;\n\tshort unsigned int shortname;\n\tunsigned char name_check;\n\tunsigned char errors;\n\tunsigned char nfs;\n\tshort unsigned int allow_utime;\n\tunsigned int quiet: 1;\n\tunsigned int showexec: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int dotsOK: 1;\n\tunsigned int isvfat: 1;\n\tunsigned int utf8: 1;\n\tunsigned int unicode_xlate: 1;\n\tunsigned int numtail: 1;\n\tunsigned int flush: 1;\n\tunsigned int nocase: 1;\n\tunsigned int usefree: 1;\n\tunsigned int tz_set: 1;\n\tunsigned int rodir: 1;\n\tunsigned int discard: 1;\n\tunsigned int dos1xfloppy: 1;\n\tunsigned int debug: 1;\n};\n\nstruct msdos_dir_entry;\n\nstruct fat_slot_info {\n\tloff_t i_pos;\n\tloff_t slot_off;\n\tint nr_slots;\n\tstruct msdos_dir_entry *de;\n\tstruct buffer_head *bh;\n};\n\nstruct fatent_operations {\n\tvoid (*ent_blocknr)(struct super_block *, int, int *, sector_t *);\n\tvoid (*ent_set_ptr)(struct fat_entry *, int);\n\tint (*ent_bread)(struct super_block *, struct fat_entry *, int, sector_t);\n\tint (*ent_get)(struct fat_entry *);\n\tvoid (*ent_put)(struct fat_entry *, int);\n\tint (*ent_next)(struct fat_entry *);\n};\n\nstruct fatent_ra {\n\tsector_t cur;\n\tsector_t limit;\n\tunsigned int ra_blocks;\n\tsector_t ra_advance;\n\tsector_t ra_next;\n\tsector_t ra_limit;\n};\n\nstruct fault_attr {};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_plane_view_dims {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int tile_width;\n\tunsigned int tile_height;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct nv_ethtool_stats {\n\tu64 tx_bytes;\n\tu64 tx_zero_rexmt;\n\tu64 tx_one_rexmt;\n\tu64 tx_many_rexmt;\n\tu64 tx_late_collision;\n\tu64 tx_fifo_errors;\n\tu64 tx_carrier_errors;\n\tu64 tx_excess_deferral;\n\tu64 tx_retry_error;\n\tu64 rx_frame_error;\n\tu64 rx_extra_byte;\n\tu64 rx_late_collision;\n\tu64 rx_runt;\n\tu64 rx_frame_too_long;\n\tu64 rx_over_errors;\n\tu64 rx_crc_errors;\n\tu64 rx_frame_align_error;\n\tu64 rx_length_error;\n\tu64 rx_unicast;\n\tu64 rx_multicast;\n\tu64 rx_broadcast;\n\tu64 rx_packets;\n\tu64 rx_errors_total;\n\tu64 tx_errors_total;\n\tu64 tx_deferral;\n\tu64 tx_packets;\n\tu64 rx_bytes;\n\tu64 tx_pause;\n\tu64 rx_pause;\n\tu64 rx_drop_frame;\n\tu64 tx_unicast;\n\tu64 tx_multicast;\n\tu64 tx_broadcast;\n};\n\nstruct ring_desc;\n\nstruct ring_desc_ex;\n\nunion ring_type {\n\tstruct ring_desc *orig;\n\tstruct ring_desc_ex *ex;\n};\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct nv_skb_map;\n\nstruct nv_txrx_stats;\n\nstruct fe_priv {\n\tspinlock_t lock;\n\tstruct net_device *dev;\n\tstruct napi_struct napi;\n\tspinlock_t hwstats_lock;\n\tstruct nv_ethtool_stats estats;\n\tint in_shutdown;\n\tu32 linkspeed;\n\tint duplex;\n\tint autoneg;\n\tint fixed_mode;\n\tint phyaddr;\n\tint wolenabled;\n\tunsigned int phy_oui;\n\tunsigned int phy_model;\n\tunsigned int phy_rev;\n\tu16 gigabit;\n\tint intr_test;\n\tint recover_error;\n\tint quiet_count;\n\tdma_addr_t ring_addr;\n\tstruct pci_dev *pci_dev;\n\tu32 orig_mac[2];\n\tu32 events;\n\tu32 irqmask;\n\tu32 desc_ver;\n\tu32 txrxctl_bits;\n\tu32 vlanctl_bits;\n\tu32 driver_data;\n\tu32 device_id;\n\tu32 register_size;\n\tu32 mac_in_use;\n\tint mgmt_version;\n\tint mgmt_sema;\n\tvoid *base;\n\tunion ring_type get_rx;\n\tunion ring_type put_rx;\n\tunion ring_type last_rx;\n\tstruct nv_skb_map *get_rx_ctx;\n\tstruct nv_skb_map *put_rx_ctx;\n\tstruct nv_skb_map *last_rx_ctx;\n\tstruct nv_skb_map *rx_skb;\n\tunion ring_type rx_ring;\n\tunsigned int rx_buf_sz;\n\tunsigned int pkt_limit;\n\tstruct timer_list oom_kick;\n\tstruct timer_list nic_poll;\n\tstruct timer_list stats_poll;\n\tu32 nic_poll_irq;\n\tint rx_ring_size;\n\tstruct u64_stats_sync swstats_rx_syncp;\n\tstruct nv_txrx_stats *txrx_stats;\n\tint need_linktimer;\n\tlong unsigned int link_timeout;\n\tunion ring_type get_tx;\n\tunion ring_type put_tx;\n\tunion ring_type last_tx;\n\tstruct nv_skb_map *get_tx_ctx;\n\tstruct nv_skb_map *put_tx_ctx;\n\tstruct nv_skb_map *last_tx_ctx;\n\tstruct nv_skb_map *tx_skb;\n\tunion ring_type tx_ring;\n\tu32 tx_flags;\n\tint tx_ring_size;\n\tint tx_limit;\n\tu32 tx_pkts_in_progress;\n\tstruct nv_skb_map *tx_change_owner;\n\tstruct nv_skb_map *tx_end_flip;\n\tint tx_stop;\n\tstruct u64_stats_sync swstats_tx_syncp;\n\tu32 msi_flags;\n\tstruct msix_entry msi_x_entry[8];\n\tu32 pause_flags;\n\tu32 saved_config_space[385];\n\tchar name_rx[19];\n\tchar name_tx[19];\n\tchar name_other[22];\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[2];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct trace_seq;\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tbool is_signed;\n\tbool is_string;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[2];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct ff_periodic_effect_compat {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\tcompat_uptr_t custom_data;\n};\n\nstruct ff_effect_compat {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect_compat periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t} u;\n};\n\nstruct fib_kuid_range {\n\tkuid_t start;\n\tkuid_t end;\n};\n\nstruct fib_rule_port_range {\n\t__u16 start;\n\t__u16 end;\n};\n\nstruct fib_rule {\n\tstruct list_head list;\n\tint iifindex;\n\tint oifindex;\n\tu32 mark;\n\tu32 mark_mask;\n\tu32 flags;\n\tu32 table;\n\tu8 action;\n\tu8 l3mdev;\n\tu8 proto;\n\tu8 ip_proto;\n\tu32 target;\n\t__be64 tun_id;\n\tstruct fib_rule *ctarget;\n\tstruct net *fr_net;\n\trefcount_t refcnt;\n\tu32 pref;\n\tint suppress_ifgroup;\n\tint suppress_prefixlen;\n\tchar iifname[16];\n\tchar oifname[16];\n\tstruct fib_kuid_range uid_range;\n\tstruct fib_rule_port_range sport_range;\n\tstruct fib_rule_port_range dport_range;\n\tu16 sport_mask;\n\tu16 dport_mask;\n\tu8 iif_is_l3_master;\n\tu8 oif_is_l3_master;\n\tstruct callback_head rcu;\n};\n\nstruct fib4_rule {\n\tstruct fib_rule common;\n\tu8 dst_len;\n\tu8 src_len;\n\tdscp_t dscp;\n\tdscp_t dscp_mask;\n\tu8 dscp_full: 1;\n\t__be32 src;\n\t__be32 srcmask;\n\t__be32 dst;\n\t__be32 dstmask;\n};\n\nstruct fib6_node;\n\nstruct fib6_walker {\n\tstruct list_head lh;\n\tstruct fib6_node *root;\n\tstruct fib6_node *node;\n\tstruct fib6_info *leaf;\n\tenum fib6_walk_state state;\n\tunsigned int skip;\n\tunsigned int count;\n\tunsigned int skip_in_node;\n\tint (*func)(struct fib6_walker *);\n\tvoid *args;\n};\n\nstruct fib6_cleaner {\n\tstruct fib6_walker w;\n\tstruct net *net;\n\tint (*func)(struct fib6_info *, void *);\n\tint sernum;\n\tvoid *arg;\n\tbool skip_notify;\n};\n\nstruct nlmsghdr;\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct fib6_dump_arg {\n\tstruct net *net;\n\tstruct notifier_block *nb;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib6_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib6_info *rt;\n\tunsigned int nsiblings;\n};\n\nstruct fib6_gc_args {\n\tint timeout;\n\tint more;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_nh_age_excptn_arg {\n\tstruct fib6_gc_args *gc_args;\n\tlong unsigned int now;\n};\n\nstruct fib6_nh_del_cached_rt_arg {\n\tstruct fib6_config *cfg;\n\tstruct fib6_info *f6i;\n};\n\nstruct fib6_nh_dm_arg {\n\tstruct net *net;\n\tconst struct in6_addr *saddr;\n\tint oif;\n\tint flags;\n\tstruct fib6_nh *nh;\n};\n\nstruct rt6_rtnl_dump_arg;\n\nstruct fib6_nh_exception_dump_walker {\n\tstruct rt6_rtnl_dump_arg *dump;\n\tstruct fib6_info *rt;\n\tunsigned int flags;\n\tunsigned int skip;\n\tunsigned int count;\n};\n\nstruct fib6_nh_excptn_arg {\n\tstruct rt6_info *rt;\n\tint plen;\n};\n\nstruct fib6_nh_frl_arg {\n\tu32 flags;\n\tint oif;\n\tint strict;\n\tint *mpri;\n\tbool *do_rr;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_match_arg {\n\tconst struct net_device *dev;\n\tconst struct in6_addr *gw;\n\tstruct fib6_nh *match;\n};\n\nstruct fib6_result;\n\nstruct flowi6;\n\nstruct fib6_nh_rd_arg {\n\tstruct fib6_result *res;\n\tstruct flowi6 *fl6;\n\tconst struct in6_addr *gw;\n\tstruct rt6_info **ret;\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_lookup_arg {\n\tvoid *lookup_ptr;\n\tconst void *lookup_data;\n\tvoid *result;\n\tstruct fib_rule *rule;\n\tu32 table;\n\tint flags;\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tloff_t pos;\n\tt_key key;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_rule_hdr {\n\t__u8 family;\n\t__u8 dst_len;\n\t__u8 src_len;\n\t__u8 tos;\n\t__u8 table;\n\t__u8 res1;\n\t__u8 res2;\n\t__u8 action;\n\t__u32 flags;\n};\n\nstruct fib_rule_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_rule *rule;\n};\n\nstruct fib_rule_uid_range {\n\t__u32 start;\n\t__u32 end;\n};\n\nstruct flowi;\n\nstruct fib_rules_ops {\n\tint family;\n\tstruct list_head list;\n\tint rule_size;\n\tint addr_size;\n\tint unresolved_rules;\n\tint nr_goto_rules;\n\tunsigned int fib_rules_seq;\n\tint (*action)(struct fib_rule *, struct flowi *, int, struct fib_lookup_arg *);\n\tbool (*suppress)(struct fib_rule *, int, struct fib_lookup_arg *);\n\tint (*match)(struct fib_rule *, struct flowi *, int);\n\tint (*configure)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*delete)(struct fib_rule *);\n\tint (*compare)(struct fib_rule *, struct fib_rule_hdr *, struct nlattr **);\n\tint (*fill)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *);\n\tsize_t (*nlmsg_payload)(struct fib_rule *);\n\tvoid (*flush_cache)(struct fib_rules_ops *);\n\tint nlgroup;\n\tstruct list_head rules_list;\n\tstruct module *owner;\n\tstruct net *fro_net;\n\tstruct callback_head rcu;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} __attribute__((packed)) i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct io_uring_cmd;\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct file_range {\n\tconst struct path *path;\n\tloff_t pos;\n\tsize_t count;\n};\n\nstruct page_counter;\n\nstruct file_region {\n\tstruct list_head link;\n\tlong int from;\n\tlong int to;\n\tstruct page_counter *reservation_counter;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct file_security_struct {\n\tu32 sid;\n\tu32 fown_sid;\n\tu32 isid;\n\tu32 pseqno;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[168];\n};\n\nstruct filename_trans_datum {\n\tstruct ebitmap stypes;\n\tu32 otype;\n\tstruct filename_trans_datum *next;\n};\n\nstruct filename_trans_key {\n\tu32 ttype;\n\tu16 tclass;\n\tconst char *name;\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct fils_discovery_data {\n\tstruct callback_head callback_head;\n\tint len;\n\tu8 data[0];\n};\n\nstruct filter_head {\n\tstruct list_head list;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rcu_work rwork;\n\t};\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\nstruct regex;\n\nstruct ftrace_event_field;\n\nstruct filter_pred {\n\tstruct regex *regex;\n\tstruct cpumask *mask;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tu64 val;\n\tu64 val2;\n\tenum filter_pred_fn fn_num;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nstruct find_child_walk_data {\n\tstruct acpi_device *adev;\n\tu64 address;\n\tint score;\n\tbool check_sta;\n\tbool check_children;\n};\n\nstruct find_interface_arg {\n\tint minor;\n\tstruct device_driver *drv;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct firmware_map_entry {\n\tu64 start;\n\tu64 end;\n\tconst char *type;\n\tstruct list_head list;\n\tstruct kobject kobj;\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\nstruct fixed_phy_status {\n\tint speed;\n\tint duplex;\n\tbool link: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n};\n\nstruct fixed_phy {\n\tstruct phy_device *phydev;\n\tstruct fixed_phy_status status;\n\tint (*link_update)(struct net_device *, struct fixed_phy_status *);\n};\n\nstruct fixed_range_block {\n\tint base_msr;\n\tint ranges;\n};\n\nstruct flex {\n\ti915_reg_t reg;\n\tu32 offset;\n\tu32 value;\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct flow_action_police {\n\tu32 burst;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n};\n\nstruct nf_flowtable;\n\nstruct ip_tunnel_info;\n\nstruct psample_group;\n\nstruct flow_action_cookie;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 0;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct flush_tlb_info {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tu64 new_tlb_gen;\n\tunsigned int initiating_cpu;\n\tu8 stride_shift;\n\tu8 freed_tables;\n\tu8 trim_cpumask;\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nstruct page_pool;\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n\tlong: 64;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tatomic_t _entire_mapcount;\n\t\t\t\t\tatomic_t _pincount;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct mem_cgroup;\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct follower_init_arg {\n\tstruct hda_codec *codec;\n\tint step;\n};\n\nstruct font_data {\n\tunsigned int extra[4];\n\tconst unsigned char data[0];\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tconst void *data;\n\tint pref;\n};\n\nstruct inactive_task_frame {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bx;\n\tlong unsigned int bp;\n\tlong unsigned int ret_addr;\n};\n\nstruct fork_frame {\n\tstruct inactive_task_frame frame;\n\tstruct pt_regs regs;\n};\n\nstruct fork_proc_event {\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n\t__kernel_pid_t child_pid;\n\t__kernel_pid_t child_tgid;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fregs_state {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n\tu32 status;\n};\n\nstruct fxregs_state {\n\tu16 cwd;\n\tu16 swd;\n\tu16 twd;\n\tu16 fop;\n\tunion {\n\t\tstruct {\n\t\t\tu64 rip;\n\t\t\tu64 rdp;\n\t\t};\n\t\tstruct {\n\t\t\tu32 fip;\n\t\t\tu32 fcs;\n\t\t\tu32 foo;\n\t\t\tu32 fos;\n\t\t};\n\t};\n\tu32 mxcsr;\n\tu32 mxcsr_mask;\n\tu32 st_space[32];\n\tu32 xmm_space[64];\n\tu32 padding[12];\n\tunion {\n\t\tu32 padding1[12];\n\t\tu32 sw_reserved[12];\n\t};\n};\n\nstruct math_emu_info;\n\nstruct swregs_state {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n\tu8 ftop;\n\tu8 changed;\n\tu8 lookahead;\n\tu8 no_update;\n\tu8 rm;\n\tu8 alimit;\n\tstruct math_emu_info *info;\n\tu32 entry_eip;\n};\n\nstruct xstate_header {\n\tu64 xfeatures;\n\tu64 xcomp_bv;\n\tu64 reserved[6];\n};\n\nstruct xregs_state {\n\tstruct fxregs_state i387;\n\tstruct xstate_header header;\n\tu8 extended_state_area[0];\n};\n\nunion fpregs_state {\n\tstruct fregs_state fsave;\n\tstruct fxregs_state fxsave;\n\tstruct swregs_state soft;\n\tstruct xregs_state xsave;\n\tu8 __padding[4096];\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\nstruct fpstate {\n\tunsigned int size;\n\tunsigned int user_size;\n\tu64 xfeatures;\n\tu64 user_xfeatures;\n\tu64 xfd;\n\tunsigned int is_valloc: 1;\n\tunsigned int is_guest: 1;\n\tunsigned int is_confidential: 1;\n\tunsigned int in_use: 1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion fpregs_state regs;\n};\n\nstruct fpu_state_perm {\n\tu64 __state_perm;\n\tunsigned int __state_size;\n\tunsigned int __user_state_size;\n};\n\nstruct fpu {\n\tunsigned int last_cpu;\n\tlong unsigned int avx512_timestamp;\n\tstruct fpstate *fpstate;\n\tstruct fpstate *__task_fpstate;\n\tstruct fpu_state_perm perm;\n\tstruct fpu_state_perm guest_perm;\n\tstruct fpstate __fpstate;\n};\n\nstruct fpu_guest {\n\tu64 xfeatures;\n\tu64 xfd_err;\n\tunsigned int uabi_size;\n\tstruct fpstate *fpstate;\n};\n\nstruct fpu_state_config {\n\tunsigned int max_size;\n\tunsigned int default_size;\n\tu64 max_features;\n\tu64 default_features;\n\tu64 legacy_features;\n\tu64 independent_features;\n};\n\nstruct fq_flow;\n\nstruct fq {\n\tstruct fq_flow *flows;\n\tlong unsigned int *flows_bitmap;\n\tstruct list_head tin_backlog;\n\tspinlock_t lock;\n\tu32 flows_cnt;\n\tu32 limit;\n\tu32 memory_limit;\n\tu32 memory_usage;\n\tu32 quantum;\n\tu32 backlog;\n\tu32 overlimit;\n\tu32 overmemory;\n\tu32 collisions;\n};\n\nstruct fq_tin;\n\nstruct fq_flow {\n\tstruct fq_tin *tin;\n\tstruct list_head flowchain;\n\tstruct sk_buff_head queue;\n\tu32 backlog;\n\tint deficit;\n};\n\nstruct fq_tin {\n\tstruct list_head new_flows;\n\tstruct list_head old_flows;\n\tstruct list_head tin_list;\n\tstruct fq_flow default_flow;\n\tu32 backlog_bytes;\n\tu32 backlog_packets;\n\tu32 overlimit;\n\tu32 collisions;\n\tu32 flows;\n\tu32 tx_bytes;\n\tu32 tx_packets;\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhashtable rhashtable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct frag_queue {\n\tstruct inet_frag_queue q;\n\tint iif;\n\t__u16 nhoffset;\n\tu8 ecn;\n};\n\nstruct free_area {\n\tstruct list_head free_list[4];\n\tlong unsigned int nr_free;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t\tshort unsigned int stride;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tfreelist_full_t freelist_counters;\n\t};\n};\n\nstruct freerunning_counters {\n\tunsigned int counter_base;\n\tunsigned int counter_offset;\n\tunsigned int box_offset;\n\tunsigned int num_counters;\n\tunsigned int bits;\n\tunsigned int *box_offsets;\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n};\n\nstruct freq_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpufreq_policy *, char *);\n\tssize_t (*store)(struct cpufreq_policy *, const char *, size_t);\n};\n\nstruct freq_band_range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct muldiv {\n\tu32 multiplier;\n\tu32 divider;\n};\n\nstruct freq_desc {\n\tbool use_msr_plat;\n\tstruct muldiv muldiv[16];\n\tu32 freqs[16];\n\tu32 mask;\n};\n\nstruct intel_frontbuffer;\n\nstruct frontbuffer_fence_cb {\n\tstruct dma_fence_cb base;\n\tstruct intel_frontbuffer *front;\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_disk_quota {\n\t__s8 d_version;\n\t__s8 d_flags;\n\t__u16 d_fieldmask;\n\t__u32 d_id;\n\t__u64 d_blk_hardlimit;\n\t__u64 d_blk_softlimit;\n\t__u64 d_ino_hardlimit;\n\t__u64 d_ino_softlimit;\n\t__u64 d_bcount;\n\t__u64 d_icount;\n\t__s32 d_itimer;\n\t__s32 d_btimer;\n\t__u16 d_iwarns;\n\t__u16 d_bwarns;\n\t__s8 d_itimer_hi;\n\t__s8 d_btimer_hi;\n\t__s8 d_rtbtimer_hi;\n\t__s8 d_padding2;\n\t__u64 d_rtb_hardlimit;\n\t__u64 d_rtb_softlimit;\n\t__u64 d_rtbcount;\n\t__s32 d_rtbtimer;\n\t__u16 d_rtbwarns;\n\t__s16 d_padding3;\n\tchar d_padding4[8];\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_qfilestat {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n};\n\ntypedef struct fs_qfilestat fs_qfilestat_t;\n\nstruct fs_qfilestatv {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n\t__u32 qfs_pad;\n};\n\nstruct fs_quota_stat {\n\t__s8 qs_version;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tfs_qfilestat_t qs_uquota;\n\tfs_qfilestat_t qs_gquota;\n\t__u32 qs_incoredqs;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n};\n\nstruct fs_quota_statv {\n\t__s8 qs_version;\n\t__u8 qs_pad1;\n\t__u16 qs_flags;\n\t__u32 qs_incoredqs;\n\tstruct fs_qfilestatv qs_uquota;\n\tstruct fs_qfilestatv qs_gquota;\n\tstruct fs_qfilestatv qs_pquota;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n\t__u16 qs_rtbwarnlimit;\n\t__u16 qs_pad3;\n\t__u32 qs_pad4;\n\t__u64 qs_pad2[7];\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fscache_cache_ops;\n\nstruct fscache_cache {\n\tconst struct fscache_cache_ops *ops;\n\tstruct list_head cache_link;\n\tvoid *cache_priv;\n\trefcount_t ref;\n\tatomic_t n_volumes;\n\tatomic_t n_accesses;\n\tatomic_t object_count;\n\tunsigned int debug_id;\n\tenum fscache_cache_state state;\n\tchar *name;\n};\n\nstruct fscache_volume;\n\nstruct fscache_cookie;\n\nstruct netfs_cache_resources;\n\nstruct fscache_cache_ops {\n\tconst char *name;\n\tvoid (*acquire_volume)(struct fscache_volume *);\n\tvoid (*free_volume)(struct fscache_volume *);\n\tbool (*lookup_cookie)(struct fscache_cookie *);\n\tvoid (*withdraw_cookie)(struct fscache_cookie *);\n\tvoid (*resize_cookie)(struct netfs_cache_resources *, loff_t);\n\tbool (*invalidate_cookie)(struct fscache_cookie *);\n\tbool (*begin_operation)(struct netfs_cache_resources *, enum fscache_want_state);\n\tvoid (*prepare_to_write)(struct fscache_cookie *);\n};\n\nstruct fscache_cookie {\n\trefcount_t ref;\n\tatomic_t n_active;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n\tspinlock_t lock;\n\tstruct fscache_volume *volume;\n\tvoid *cache_priv;\n\tstruct hlist_bl_node hash_link;\n\tstruct list_head proc_link;\n\tstruct list_head commit_link;\n\tstruct work_struct work;\n\tloff_t object_size;\n\tlong unsigned int unused_at;\n\tlong unsigned int flags;\n\tenum fscache_cookie_state state;\n\tu8 advice;\n\tu8 key_len;\n\tu8 aux_len;\n\tu32 key_hash;\n\tunion {\n\t\tvoid *key;\n\t\tu8 inline_key[16];\n\t};\n\tunion {\n\t\tvoid *aux;\n\t\tu8 inline_aux[8];\n\t};\n};\n\nstruct fscache_volume {\n\trefcount_t ref;\n\tatomic_t n_cookies;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int key_hash;\n\tu8 *key;\n\tstruct list_head proc_link;\n\tstruct hlist_bl_node hash_link;\n\tstruct work_struct work;\n\tstruct fscache_cache *cache;\n\tvoid *cache_priv;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu8 coherency_len;\n\tu8 coherency[0];\n};\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_nokey_name;\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_io;\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu32 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n\tconst char *driver_override;\n};\n\nstruct fsl_mc_resource_pool;\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tunsigned int virq;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\traw_spinlock_t spinlock;\n\t};\n};\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct fsuuid {\n\t__u32 fsu_len;\n\t__u32 fsu_flags;\n\t__u8 fsu_uuid[0];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nstruct ftp_search {\n\tconst char *pattern;\n\tsize_t plen;\n\tchar skip;\n\tchar term;\n\tenum nf_ct_ftp_type ftptype;\n\tint (*getnum)(const char *, size_t, struct nf_conntrack_man *, char, unsigned int *);\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8156];\n};\n\nstruct tracer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tchar *fmt;\n\tunsigned int fmt_size;\n\tatomic_t wait_index;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool closed;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int spare_size;\n\tunsigned int read;\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int args[0];\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tunsigned int is_signed: 1;\n\tunsigned int needs_test: 1;\n\tint len;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct func_repeats_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu16 count;\n\tu16 top_delta_ts;\n\tu32 bottom_delta_ts;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nstruct uc_fw_platform_requirement;\n\nstruct fw_blobs_by_type {\n\tconst struct uc_fw_platform_requirement *blobs;\n\tu32 count;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_info {\n\tu32 magic;\n\tchar version[32];\n\t__le32 fw_start;\n\t__le32 fw_len;\n\tu8 chksum;\n} __attribute__((packed));\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tsize_t offset;\n\tu32 opt_flags;\n\tconst char *fw_name;\n};\n\nunion fw_table_header {\n\tstruct acpi_table_header acpi;\n\tstruct acpi_table_cdat cdat;\n};\n\nstruct fwdb_collection {\n\tu8 len;\n\tu8 n_rules;\n\tu8 dfs_region;\n\tint: 0;\n};\n\nstruct fwdb_country {\n\tu8 alpha2[2];\n\t__be16 coll_ptr;\n};\n\nstruct fwdb_header {\n\t__be32 magic;\n\t__be32 version;\n\tstruct fwdb_country country[0];\n};\n\nstruct fwdb_rule {\n\tu8 len;\n\tu8 flags;\n\t__be16 max_eirp;\n\t__be32 start;\n\t__be32 end;\n\t__be32 max_bw;\n\t__be16 cac_timeout;\n\t__be16 wmm_ptr;\n};\n\nstruct fwdb_wmm_ac {\n\tu8 ecw;\n\tu8 aifsn;\n\t__be16 cot;\n};\n\nstruct fwdb_wmm_rule {\n\tstruct fwdb_wmm_ac client[4];\n\tstruct fwdb_wmm_ac ap[4];\n};\n\nunion fwnet_hwaddr {\n\tu8 u[16];\n\tstruct {\n\t\t__be64 uniq_id;\n\t\tu8 max_rec;\n\t\tu8 sspd;\n\t\tu8 fifo[6];\n\t} uc;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_reference_args;\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct g4x_pipe_wm {\n\tu16 plane[8];\n\tu16 fbc;\n};\n\nstruct g4x_sr_wm {\n\tu16 plane;\n\tu16 cursor;\n\tu16 fbc;\n};\n\nstruct g4x_wm_state {\n\tstruct g4x_pipe_wm wm;\n\tstruct g4x_sr_wm sr;\n\tstruct g4x_sr_wm hpll;\n\tbool cxsr;\n\tbool hpll_en;\n\tbool fbc_en;\n};\n\nstruct g4x_wm_values {\n\tstruct g4x_pipe_wm pipe[2];\n\tstruct g4x_sr_wm sr;\n\tstruct g4x_sr_wm hpll;\n\tbool cxsr;\n\tbool hpll_en;\n\tbool fbc_en;\n};\n\nstruct idt_bits {\n\tu16 ist: 3;\n\tu16 zero: 5;\n\tu16 type: 5;\n\tu16 dpl: 2;\n\tu16 p: 1;\n};\n\nstruct gate_struct {\n\tu16 offset_low;\n\tu16 segment;\n\tstruct idt_bits bits;\n\tu16 offset_middle;\n\tu32 offset_high;\n\tu32 reserved;\n};\n\ntypedef struct gate_struct gate_desc;\n\nstruct gatt_mask {\n\tlong unsigned int mask;\n\tu32 type;\n};\n\nstruct gcm_instance_ctx {\n\tstruct crypto_skcipher_spawn ctr;\n\tstruct crypto_ahash_spawn ghash;\n};\n\nstruct gcr3_tbl_info {\n\tu64 *gcr3_tbl;\n\tint glx;\n\tu32 pasid_cnt;\n\tu16 domid;\n};\n\nstruct gcry_mpi;\n\ntypedef struct gcry_mpi *MPI;\n\nstruct gcry_mpi {\n\tint alloced;\n\tint nlimbs;\n\tint nbits;\n\tint sign;\n\tunsigned int flags;\n\tmpi_limb_t *d;\n};\n\nstruct gdt_page {\n\tstruct desc_struct gdt[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct i915_vm_pt_stash;\n\nstruct i915_vma_resource;\n\nstruct i915_vma_ops {\n\tvoid (*bind_vma)(struct i915_address_space *, struct i915_vm_pt_stash *, struct i915_vma_resource *, unsigned int, u32);\n\tvoid (*unbind_vma)(struct i915_address_space *, struct i915_vma_resource *);\n};\n\nstruct i915_page_table;\n\nstruct i915_address_space {\n\tstruct kref ref;\n\tstruct work_struct release_work;\n\tstruct drm_mm mm;\n\tstruct {\n\t\tstruct drm_i915_gem_object *obj;\n\t\tstruct i915_vma *vma;\n\t} rsvd;\n\tstruct intel_gt *gt;\n\tstruct drm_i915_private *i915;\n\tstruct drm_i915_file_private *fpriv;\n\tstruct device *dma;\n\tu64 total;\n\tu64 reserved;\n\tu64 min_alignment[4];\n\tunsigned int bind_async_flags;\n\tstruct mutex mutex;\n\tstruct kref resv_ref;\n\tstruct dma_resv _resv;\n\tstruct drm_i915_gem_object *scratch[4];\n\tstruct list_head bound_list;\n\tstruct list_head unbound_list;\n\tbool is_ggtt: 1;\n\tbool is_dpt: 1;\n\tbool has_read_only: 1;\n\tbool skip_pte_rewrite: 1;\n\tu8 top;\n\tu8 pd_shift;\n\tu8 scratch_order;\n\tlong unsigned int lmem_pt_obj_flags;\n\tstruct rb_root_cached pending_unbind;\n\tstruct drm_i915_gem_object * (*alloc_pt_dma)(struct i915_address_space *, int);\n\tstruct drm_i915_gem_object * (*alloc_scratch_dma)(struct i915_address_space *, int);\n\tu64 (*pte_encode)(dma_addr_t, unsigned int, u32);\n\tdma_addr_t (*pte_decode)(u64, bool *, bool *);\n\tvoid (*allocate_va_range)(struct i915_address_space *, struct i915_vm_pt_stash *, u64, u64);\n\tvoid (*clear_range)(struct i915_address_space *, u64, u64);\n\tvoid (*scratch_range)(struct i915_address_space *, u64, u64);\n\tvoid (*insert_page)(struct i915_address_space *, dma_addr_t, u64, unsigned int, u32);\n\tvoid (*insert_entries)(struct i915_address_space *, struct i915_vma_resource *, unsigned int, u32);\n\tvoid (*raw_insert_page)(struct i915_address_space *, dma_addr_t, u64, unsigned int, u32);\n\tvoid (*raw_insert_entries)(struct i915_address_space *, struct i915_vma_resource *, unsigned int, u32);\n\tdma_addr_t (*read_entry)(struct i915_address_space *, u64, bool *, bool *);\n\tvoid (*cleanup)(struct i915_address_space *);\n\tvoid (*foreach)(struct i915_address_space *, u64, u64, void (*)(struct i915_address_space *, struct i915_page_table *, void *), void *);\n\tstruct i915_vma_ops vma_ops;\n};\n\nstruct i915_page_directory;\n\nstruct i915_ppgtt {\n\tstruct i915_address_space vm;\n\tstruct i915_page_directory *pd;\n};\n\nstruct gen6_ppgtt {\n\tstruct i915_ppgtt base;\n\tstruct mutex flush;\n\tstruct i915_vma *vma;\n\tgen6_pte_t *pd_addr;\n\tu32 pp_dir;\n\tatomic_t pin_count;\n\tbool scan_for_unused_pt;\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct gen_pool;\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct list_head slave_bdevs;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tstruct cdrom_device_info *cdi;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct ocontext;\n\nstruct genfs {\n\tchar *fstype;\n\tstruct ocontext *head;\n\tstruct genfs *next;\n};\n\nstruct netlink_callback;\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[64];\n\t\tu8 data[512];\n\t};\n};\n\nstruct get_key_cookie {\n\tstruct sk_buff *msg;\n\tint error;\n\tint idx;\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct gf128mul_4k {\n\tbe128 t[256];\n};\n\nstruct gf128mul_64k {\n\tstruct gf128mul_4k *t[16];\n};\n\nstruct kvm_memory_slot;\n\nstruct gfn_to_hva_cache {\n\tu64 generation;\n\tgpa_t gpa;\n\tlong unsigned int hva;\n\tlong unsigned int len;\n\tstruct kvm_memory_slot *memslot;\n};\n\nstruct kvm;\n\nstruct gfn_to_pfn_cache {\n\tu64 generation;\n\tgpa_t gpa;\n\tlong unsigned int uhva;\n\tstruct kvm_memory_slot *memslot;\n\tstruct kvm *kvm;\n\tstruct list_head list;\n\trwlock_t lock;\n\tstruct mutex refresh_lock;\n\tvoid *khva;\n\tkvm_pfn_t pfn;\n\tbool active;\n\tbool valid;\n};\n\nstruct ghash_ctx {\n\tstruct gf128mul_4k *gf128;\n};\n\nstruct ghash_desc_ctx {\n\tu8 buffer[16];\n};\n\nstruct ghcb_save_area {\n\tu8 reserved_0x0[203];\n\tu8 cpl;\n\tu8 reserved_0xcc[116];\n\tu64 xss;\n\tu8 reserved_0x148[24];\n\tu64 dr7;\n\tu8 reserved_0x168[16];\n\tu64 rip;\n\tu8 reserved_0x180[88];\n\tu64 rsp;\n\tu8 reserved_0x1e0[24];\n\tu64 rax;\n\tu8 reserved_0x200[264];\n\tu64 rcx;\n\tu64 rdx;\n\tu64 rbx;\n\tu8 reserved_0x320[8];\n\tu64 rbp;\n\tu64 rsi;\n\tu64 rdi;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu8 reserved_0x380[16];\n\tu64 sw_exit_code;\n\tu64 sw_exit_info_1;\n\tu64 sw_exit_info_2;\n\tu64 sw_scratch;\n\tu8 reserved_0x3b0[56];\n\tu64 xcr0;\n\tu8 valid_bitmap[16];\n\tu64 x87_state_gpa;\n};\n\nstruct ghcb {\n\tstruct ghcb_save_area save;\n\tu8 reserved_save[1016];\n\tu8 shared_buffer[2032];\n\tu8 reserved_0xff0[10];\n\tu16 protocol_version;\n\tu32 ghcb_usage;\n};\n\nstruct giveback_urb_bh {\n\tbool running;\n\tbool high_prio;\n\tspinlock_t lock;\n\tstruct list_head head;\n\tstruct work_struct bh;\n\tstruct usb_host_endpoint *completing_ep;\n};\n\nstruct global_params {\n\tbool no_turbo;\n\tbool turbo_disabled;\n\tint max_perf_pct;\n\tint min_perf_pct;\n};\n\nstruct gmbus_pin {\n\tconst char *name;\n\tenum gmbus_gpio gpio;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct governor_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gov_attr_set *, char *);\n\tssize_t (*store)(struct gov_attr_set *, const char *, size_t);\n};\n\nstruct gpio_device;\n\nstruct gpio_chip {\n\tconst char *label;\n\tstruct gpio_device *gpiodev;\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tstruct module *owner;\n\tint (*request)(struct gpio_chip *, unsigned int);\n\tvoid (*free)(struct gpio_chip *, unsigned int);\n\tint (*get_direction)(struct gpio_chip *, unsigned int);\n\tint (*direction_input)(struct gpio_chip *, unsigned int);\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tint (*get)(struct gpio_chip *, unsigned int);\n\tint (*get_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n\tint (*set_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set_config)(struct gpio_chip *, unsigned int, long unsigned int);\n\tint (*to_irq)(struct gpio_chip *, unsigned int);\n\tvoid (*dbg_show)(struct seq_file *, struct gpio_chip *);\n\tint (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tint (*add_pin_ranges)(struct gpio_chip *);\n\tint (*en_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint (*dis_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint base;\n\tu16 ngpio;\n\tu16 offset;\n\tconst char * const *names;\n\tbool can_sleep;\n};\n\nstruct gpiod_lookup {\n\tconst char *key;\n\tu16 chip_hwnum;\n\tconst char *con_id;\n\tunsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct gpiod_lookup_table {\n\tstruct list_head list;\n\tconst char *dev_id;\n\tstruct gpiod_lookup table[0];\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n};\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct gsb_buffer {\n\tu8 status;\n\tu8 len;\n\tunion {\n\t\tu16 wdata;\n\t\tu8 bdata;\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct gsc_def {\n\tconst char *name;\n\tlong unsigned int bar;\n\tsize_t bar_size;\n\tbool use_polling;\n\tbool slow_firmware;\n\tsize_t lmem_size;\n};\n\nstruct gsc_heci_pkt {\n\tu64 addr_in;\n\tu32 size_in;\n\tu64 addr_out;\n\tu32 size_out;\n};\n\nstruct intel_gsc_mtl_header {\n\tu32 validity_marker;\n\tu8 heci_client_id;\n\tu8 reserved1;\n\tu16 header_version;\n\tu64 host_session_handle;\n\tu64 gsc_message_handle;\n\tu32 message_size;\n\tu32 flags;\n\tu32 status;\n} __attribute__((packed));\n\nstruct intel_gsc_proxy_header {\n\tu32 hdr;\n\tu32 source;\n\tu32 destination;\n\tu32 status;\n};\n\nstruct gsc_proxy_msg {\n\tstruct intel_gsc_mtl_header header;\n\tstruct intel_gsc_proxy_header proxy_header;\n};\n\nstruct intel_context;\n\nstruct gsccs_session_resources {\n\tu64 host_session_handle;\n\tstruct intel_context *ce;\n\tstruct i915_vma *pkt_vma;\n\tvoid *pkt_vaddr;\n\tstruct i915_vma *bb_vma;\n\tvoid *bb_vaddr;\n};\n\nstruct rpc_clnt;\n\nstruct rpc_pipe_ops;\n\nstruct gss_alloc_pdo {\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tconst struct rpc_pipe_ops *upcall_ops;\n};\n\nstruct rpcsec_gss_oid {\n\tunsigned int len;\n\tu8 data[32];\n};\n\nstruct gss_api_ops;\n\nstruct pf_desc;\n\nstruct gss_api_mech {\n\tstruct list_head gm_list;\n\tstruct module *gm_owner;\n\tstruct rpcsec_gss_oid gm_oid;\n\tchar *gm_name;\n\tconst struct gss_api_ops *gm_ops;\n\tint gm_pf_num;\n\tstruct pf_desc *gm_pfs;\n\tconst char *gm_upcall_enctypes;\n};\n\nstruct gss_ctx;\n\nstruct xdr_netobj;\n\nstruct gss_api_ops {\n\tint (*gss_import_sec_context)(const void *, size_t, struct gss_ctx *, time64_t *, gfp_t);\n\tu32 (*gss_get_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_verify_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_wrap)(struct gss_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*gss_unwrap)(struct gss_ctx *, int, int, struct xdr_buf *);\n\tvoid (*gss_delete_sec_context)(void *);\n};\n\nstruct rpc_authops;\n\nstruct rpc_cred_cache;\n\nstruct rpc_auth {\n\tunsigned int au_cslack;\n\tunsigned int au_rslack;\n\tunsigned int au_verfsize;\n\tunsigned int au_ralign;\n\tlong unsigned int au_flags;\n\tconst struct rpc_authops *au_ops;\n\trpc_authflavor_t au_flavor;\n\trefcount_t au_count;\n\tstruct rpc_cred_cache *au_credcache;\n};\n\nstruct gss_pipe;\n\nstruct gss_auth {\n\tstruct kref kref;\n\tstruct hlist_node hash;\n\tstruct rpc_auth rpc_auth;\n\tstruct gss_api_mech *mech;\n\tenum rpc_gss_svc service;\n\tstruct rpc_clnt *client;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct gss_pipe *gss_pipe[2];\n\tconst char *target_name;\n};\n\nstruct xdr_netobj {\n\tunsigned int len;\n\tu8 *data;\n};\n\nstruct gss_cl_ctx {\n\trefcount_t count;\n\tenum rpc_gss_proc gc_proc;\n\tu32 gc_seq;\n\tu32 gc_seq_xmit;\n\tspinlock_t gc_seq_lock;\n\tstruct gss_ctx *gc_gss_ctx;\n\tstruct xdr_netobj gc_wire_ctx;\n\tstruct xdr_netobj gc_acceptor;\n\tu32 gc_win;\n\tlong unsigned int gc_expiry;\n\tstruct callback_head gc_rcu;\n};\n\nstruct rpc_credops;\n\nstruct rpc_cred {\n\tstruct hlist_node cr_hash;\n\tstruct list_head cr_lru;\n\tstruct callback_head cr_rcu;\n\tstruct rpc_auth *cr_auth;\n\tconst struct rpc_credops *cr_ops;\n\tlong unsigned int cr_expire;\n\tlong unsigned int cr_flags;\n\trefcount_t cr_count;\n\tconst struct cred *cr_cred;\n};\n\nstruct gss_upcall_msg;\n\nstruct gss_cred {\n\tstruct rpc_cred gc_base;\n\tenum rpc_gss_svc gc_service;\n\tstruct gss_cl_ctx *gc_ctx;\n\tstruct gss_upcall_msg *gc_upcall;\n\tconst char *gc_principal;\n\tlong unsigned int gc_upcall_timestamp;\n};\n\nstruct gss_ctx {\n\tstruct gss_api_mech *mech_type;\n\tvoid *internal_ctx_id;\n\tunsigned int slack;\n\tunsigned int align;\n};\n\nstruct gss_domain {\n\tstruct auth_domain h;\n\tu32 pseudoflavor;\n};\n\nstruct krb5_ctx;\n\nstruct gss_krb5_enctype {\n\tconst u32 etype;\n\tconst u32 ctype;\n\tconst char *name;\n\tconst char *encrypt_name;\n\tconst char *aux_cipher;\n\tconst char *cksum_name;\n\tconst u16 signalg;\n\tconst u16 sealalg;\n\tconst u32 cksumlength;\n\tconst u32 keyed_cksum;\n\tconst u32 keybytes;\n\tconst u32 keylength;\n\tconst u32 Kc_length;\n\tconst u32 Ke_length;\n\tconst u32 Ki_length;\n\tint (*derive_key)(const struct gss_krb5_enctype *, const struct xdr_netobj *, struct xdr_netobj *, const struct xdr_netobj *, gfp_t);\n\tu32 (*encrypt)(struct krb5_ctx *, u32, struct xdr_buf *, struct page **);\n\tu32 (*decrypt)(struct krb5_ctx *, u32, u32, struct xdr_buf *, u32 *, u32 *);\n\tu32 (*get_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*verify_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*wrap)(struct krb5_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*unwrap)(struct krb5_ctx *, int, int, struct xdr_buf *, unsigned int *, unsigned int *);\n};\n\nstruct rpc_pipe_dir_object_ops;\n\nstruct rpc_pipe_dir_object {\n\tstruct list_head pdo_head;\n\tconst struct rpc_pipe_dir_object_ops *pdo_ops;\n\tvoid *pdo_data;\n};\n\nstruct rpc_pipe;\n\nstruct gss_pipe {\n\tstruct rpc_pipe_dir_object pdo;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tstruct kref kref;\n};\n\nstruct rpc_gss_wire_cred {\n\tu32 gc_v;\n\tu32 gc_proc;\n\tu32 gc_seq;\n\tu32 gc_svc;\n\tstruct xdr_netobj gc_ctx;\n};\n\nstruct rsc;\n\nstruct gss_svc_data {\n\tstruct rpc_gss_wire_cred clcred;\n\tu32 gsd_databody_offset;\n\tstruct rsc *rsci;\n\t__be32 gsd_seq_num;\n\tu8 gsd_scratch[40];\n};\n\nstruct gss_svc_seq_data {\n\tu32 sd_max;\n\tlong unsigned int sd_win[2];\n\tspinlock_t sd_lock;\n};\n\nstruct rpc_timer {\n\tstruct list_head list;\n\tlong unsigned int expires;\n\tstruct delayed_work dwork;\n};\n\nstruct rpc_wait_queue {\n\tspinlock_t lock;\n\tstruct list_head tasks[4];\n\tunsigned char maxpriority;\n\tunsigned char priority;\n\tunsigned char nr;\n\tunsigned int qlen;\n\tstruct rpc_timer timer_list;\n\tconst char *name;\n};\n\nstruct gss_upcall_msg {\n\trefcount_t count;\n\tkuid_t uid;\n\tconst char *service_name;\n\tstruct rpc_pipe_msg msg;\n\tstruct list_head list;\n\tstruct gss_auth *auth;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_wait_queue rpc_waitqueue;\n\twait_queue_head_t waitqueue;\n\tstruct gss_cl_ctx *ctx;\n\tchar databuf[256];\n};\n\nstruct gssp_in_token {\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n};\n\nstruct svc_cred {\n\tkuid_t cr_uid;\n\tkgid_t cr_gid;\n\tstruct group_info *cr_group_info;\n\tu32 cr_flavor;\n\tchar *cr_raw_principal;\n\tchar *cr_principal;\n\tchar *cr_targ_princ;\n\tstruct gss_api_mech *cr_gss_mech;\n};\n\nstruct gssp_upcall_data {\n\tstruct xdr_netobj in_handle;\n\tstruct gssp_in_token in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tstruct rpcsec_gss_oid mech_oid;\n\tstruct svc_cred creds;\n\tint found_creds;\n\tint major_status;\n\tint minor_status;\n};\n\ntypedef struct xdr_netobj utf8string;\n\ntypedef struct xdr_netobj gssx_buffer;\n\nstruct gssx_option;\n\nstruct gssx_option_array {\n\tu32 count;\n\tstruct gssx_option *data;\n};\n\nstruct gssx_call_ctx {\n\tutf8string locale;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx;\n\nstruct gssx_cred;\n\nstruct gssx_cb;\n\nstruct gssx_arg_accept_sec_context {\n\tstruct gssx_call_ctx call_ctx;\n\tstruct gssx_ctx *context_handle;\n\tstruct gssx_cred *cred_handle;\n\tstruct gssp_in_token input_token;\n\tstruct gssx_cb *input_cb;\n\tu32 ret_deleg_cred;\n\tstruct gssx_option_array options;\n\tstruct page **pages;\n\tunsigned int npages;\n};\n\nstruct gssx_cb {\n\tu64 initiator_addrtype;\n\tgssx_buffer initiator_address;\n\tu64 acceptor_addrtype;\n\tgssx_buffer acceptor_address;\n\tgssx_buffer application_data;\n};\n\nstruct gssx_name {\n\tgssx_buffer display_name;\n};\n\ntypedef struct gssx_name gssx_name;\n\nstruct gssx_cred_element;\n\nstruct gssx_cred_element_array {\n\tu32 count;\n\tstruct gssx_cred_element *data;\n};\n\nstruct gssx_cred {\n\tgssx_name desired_name;\n\tstruct gssx_cred_element_array elements;\n\tgssx_buffer cred_handle_reference;\n\tu32 needs_release;\n};\n\ntypedef struct xdr_netobj gssx_OID;\n\nstruct gssx_cred_element {\n\tgssx_name MN;\n\tgssx_OID mech;\n\tu32 cred_usage;\n\tu64 initiator_time_rec;\n\tu64 acceptor_time_rec;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx {\n\tgssx_buffer exported_context_token;\n\tgssx_buffer state;\n\tu32 need_release;\n\tgssx_OID mech;\n\tgssx_name src_name;\n\tgssx_name targ_name;\n\tu64 lifetime;\n\tu64 ctx_flags;\n\tu32 locally_initiated;\n\tu32 open;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_name_attr {\n\tgssx_buffer attr;\n\tgssx_buffer value;\n\tstruct gssx_option_array extensions;\n};\n\nstruct gssx_name_attr_array {\n\tu32 count;\n\tstruct gssx_name_attr *data;\n};\n\nstruct gssx_option {\n\tgssx_buffer option;\n\tgssx_buffer value;\n};\n\nstruct gssx_status {\n\tu64 major_status;\n\tgssx_OID mech;\n\tu64 minor_status;\n\tutf8string major_status_string;\n\tutf8string minor_status_string;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_res_accept_sec_context {\n\tstruct gssx_status status;\n\tstruct gssx_ctx *context_handle;\n\tgssx_buffer *output_token;\n\tstruct gssx_option_array options;\n};\n\nstruct gt_defaults {\n\tu32 min_freq;\n\tu32 max_freq;\n\tu8 rps_up_threshold;\n\tu8 rps_down_threshold;\n};\n\nstruct guc_ct_buffer_desc {\n\tu32 head;\n\tu32 tail;\n\tu32 status;\n\tu32 reserved[13];\n};\n\nstruct guc_ctxt_registration_info {\n\tu32 flags;\n\tu32 context_idx;\n\tu32 engine_class;\n\tu32 engine_submit_mask;\n\tu32 wq_desc_lo;\n\tu32 wq_desc_hi;\n\tu32 wq_base_lo;\n\tu32 wq_base_hi;\n\tu32 wq_size;\n\tu32 hwlrca_lo;\n\tu32 hwlrca_hi;\n};\n\nstruct guc_debug_capture_list_header {\n\tu32 info;\n};\n\nstruct guc_debug_capture_list {\n\tstruct guc_debug_capture_list_header header;\n\tstruct guc_mmio_reg regs[0];\n};\n\nstruct guc_sched_wq_desc {\n\tu32 head;\n\tu32 tail;\n\tu32 error_offset;\n\tu32 wq_status;\n\tu32 reserved[28];\n};\n\nstruct guc_process_desc_v69 {\n\tu32 stage_id;\n\tu64 db_base_addr;\n\tu32 head;\n\tu32 tail;\n\tu32 error_offset;\n\tu64 wq_base_addr;\n\tu32 wq_size_bytes;\n\tu32 wq_status;\n\tu32 engine_presence;\n\tu32 priority;\n\tu32 reserved[36];\n} __attribute__((packed));\n\nunion guc_descs {\n\tstruct guc_sched_wq_desc wq_desc;\n\tstruct guc_process_desc_v69 pdesc;\n};\n\nstruct intel_ctb_coredump {\n\tu32 raw_head;\n\tu32 head;\n\tu32 raw_tail;\n\tu32 tail;\n\tu32 raw_status;\n\tu32 desc_offset;\n\tu32 cmds_offset;\n\tu32 size;\n};\n\nstruct i915_vma_coredump;\n\nstruct guc_info {\n\tstruct intel_ctb_coredump ctb[2];\n\tstruct i915_vma_coredump *vma_ctb;\n\tstruct i915_vma_coredump *vma_log;\n\tu32 *hw_state;\n\tu32 timestamp;\n\tu16 last_fence;\n\tbool is_guc_capture;\n};\n\nstruct guc_log_buffer_state {\n\tu32 marker[2];\n\tu32 read_ptr;\n\tu32 write_ptr;\n\tu32 size;\n\tu32 sampled_write_ptr;\n\tu32 wrap_offset;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flush_to_file: 1;\n\t\t\tu32 buffer_full_cnt: 4;\n\t\t\tu32 reserved: 27;\n\t\t};\n\t\tu32 flags;\n\t};\n\tu32 version;\n};\n\nstruct guc_log_section {\n\tu32 max;\n\tu32 flag;\n\tu32 default_val;\n\tconst char *name;\n};\n\nstruct guc_lrc_desc_v69 {\n\tu32 hw_context_desc;\n\tu32 slpm_perf_mode_hint;\n\tu32 slpm_freq_hint;\n\tu32 engine_submit_mask;\n\tu8 engine_class;\n\tu8 reserved0[3];\n\tu32 priority;\n\tu32 process_desc;\n\tu32 wq_addr;\n\tu32 wq_size;\n\tu32 context_flags;\n\tu32 execution_quantum;\n\tu32 preemption_timeout;\n\tu32 policy_flags;\n\tu32 reserved1[19];\n};\n\nstruct guc_state_capture_group_header_t {\n\tu32 owner;\n\tu32 info;\n};\n\nstruct guc_state_capture_header_t {\n\tu32 owner;\n\tu32 info;\n\tu32 lrca;\n\tu32 guc_id;\n\tu32 num_mmios;\n};\n\nstruct guc_update_scheduling_policy_header {\n\tu32 action;\n};\n\nstruct guc_update_scheduling_policy {\n\tstruct guc_update_scheduling_policy_header header;\n\tu32 data[3];\n};\n\nunion intel_engine_tlb_inv_reg {\n\ti915_reg_t reg;\n\ti915_mcr_reg_t mcr_reg;\n};\n\nstruct intel_engine_tlb_inv {\n\tbool mcr;\n\tunion intel_engine_tlb_inv_reg reg;\n\tu32 request;\n\tu32 done;\n};\n\nstruct intel_sseu {\n\tu8 slice_mask;\n\tu8 subslice_mask;\n\tu8 min_eus_per_subslice;\n\tu8 max_eus_per_subslice;\n};\n\nstruct intel_wakeref_ops;\n\nstruct intel_wakeref {\n\tatomic_t count;\n\tstruct mutex mutex;\n\tintel_wakeref_t wakeref;\n\tstruct drm_i915_private *i915;\n\tconst struct intel_wakeref_ops *ops;\n\tstruct delayed_work work;\n};\n\nstruct intel_engine_pmu {\n\tu32 enable;\n\tunsigned int enable_count[3];\n\tstruct i915_pmu_sample sample[3];\n};\n\nstruct intel_hw_status_page {\n\tstruct list_head timelines;\n\tstruct i915_vma *vma;\n\tu32 *addr;\n};\n\nstruct i915_wa_ctx_bb {\n\tu32 offset;\n\tu32 size;\n};\n\nstruct i915_ctx_workarounds {\n\tstruct i915_wa_ctx_bb indirect_ctx;\n\tstruct i915_wa_ctx_bb per_ctx;\n\tstruct i915_vma *vma;\n};\n\nstruct i915_wa;\n\nstruct i915_wa_list {\n\tstruct intel_gt *gt;\n\tconst char *name;\n\tconst char *engine_name;\n\tstruct i915_wa *list;\n\tunsigned int count;\n\tunsigned int wa_count;\n};\n\nstruct intel_engine_execlists {\n\tstruct timer_list timer;\n\tstruct timer_list preempt;\n\tconst struct i915_request *preempt_target;\n\tu32 ccid;\n\tu32 yield;\n\tu32 error_interrupt;\n\tu32 reset_ccid;\n\tu32 *submit_reg;\n\tu32 *ctrl_reg;\n\tstruct i915_request * const *active;\n\tstruct i915_request *inflight[3];\n\tstruct i915_request *pending[3];\n\tunsigned int port_mask;\n\tstruct rb_root_cached virtual;\n\tu32 *csb_write;\n\tu64 *csb_status;\n\tu8 csb_size;\n\tu8 csb_head;\n};\n\nstruct intel_engine_execlists_stats {\n\tunsigned int active;\n\tseqcount_t lock;\n\tktime_t total;\n\tktime_t start;\n};\n\nstruct intel_engine_guc_stats {\n\tbool running;\n\tu32 prev_total;\n\tu64 total_gt_clks;\n\tu64 start_gt_clk;\n\tu64 total;\n};\n\nstruct i915_sched_engine;\n\nstruct intel_ring;\n\nstruct intel_timeline;\n\nstruct intel_breadcrumbs;\n\nstruct intel_context_ops;\n\nstruct i915_perf_group;\n\nstruct intel_engine_cs {\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt *gt;\n\tstruct intel_uncore *uncore;\n\tchar name[8];\n\tenum intel_engine_id id;\n\tenum intel_engine_id legacy_idx;\n\tunsigned int guc_id;\n\tintel_engine_mask_t mask;\n\tu32 reset_domain;\n\tintel_engine_mask_t logical_mask;\n\tu8 class;\n\tu8 instance;\n\tu16 uabi_class;\n\tu16 uabi_instance;\n\tu32 uabi_capabilities;\n\tu32 context_size;\n\tu32 mmio_base;\n\tstruct intel_engine_tlb_inv tlb_inv;\n\tenum forcewake_domains fw_domain;\n\tunsigned int fw_active;\n\tlong unsigned int context_tag;\n\tunion {\n\t\tstruct llist_node uabi_llist;\n\t\tstruct list_head uabi_list;\n\t\tstruct rb_node uabi_node;\n\t};\n\tstruct intel_sseu sseu;\n\tstruct i915_sched_engine *sched_engine;\n\tstruct i915_request *request_pool;\n\tstruct intel_context *hung_ce;\n\tstruct llist_head barrier_tasks;\n\tstruct intel_context *kernel_context;\n\tstruct intel_context *bind_context;\n\tbool bind_context_ready;\n\tstruct list_head pinned_contexts_list;\n\tintel_engine_mask_t saturated;\n\tstruct {\n\t\tstruct delayed_work work;\n\t\tstruct i915_request *systole;\n\t\tlong unsigned int blocked;\n\t} heartbeat;\n\tlong unsigned int serial;\n\tlong unsigned int wakeref_serial;\n\tintel_wakeref_t wakeref_track;\n\tstruct intel_wakeref wakeref;\n\tstruct file *default_state;\n\tstruct {\n\t\tstruct intel_ring *ring;\n\t\tstruct intel_timeline *timeline;\n\t} legacy;\n\tstruct ewma__engine_latency latency;\n\tstruct intel_breadcrumbs *breadcrumbs;\n\tstruct intel_engine_pmu pmu;\n\tstruct intel_hw_status_page status_page;\n\tstruct i915_ctx_workarounds wa_ctx;\n\tstruct i915_wa_list ctx_wa_list;\n\tstruct i915_wa_list wa_list;\n\tstruct i915_wa_list whitelist;\n\tu32 irq_keep_mask;\n\tu32 irq_enable_mask;\n\tvoid (*irq_enable)(struct intel_engine_cs *);\n\tvoid (*irq_disable)(struct intel_engine_cs *);\n\tvoid (*irq_handler)(struct intel_engine_cs *, u16);\n\tvoid (*sanitize)(struct intel_engine_cs *);\n\tint (*resume)(struct intel_engine_cs *);\n\tstruct {\n\t\tvoid (*prepare)(struct intel_engine_cs *);\n\t\tvoid (*rewind)(struct intel_engine_cs *, bool);\n\t\tvoid (*cancel)(struct intel_engine_cs *);\n\t\tvoid (*finish)(struct intel_engine_cs *);\n\t} reset;\n\tvoid (*park)(struct intel_engine_cs *);\n\tvoid (*unpark)(struct intel_engine_cs *);\n\tvoid (*bump_serial)(struct intel_engine_cs *);\n\tvoid (*set_default_submission)(struct intel_engine_cs *);\n\tconst struct intel_context_ops *cops;\n\tint (*request_alloc)(struct i915_request *);\n\tint (*emit_flush)(struct i915_request *, u32);\n\tint (*emit_bb_start)(struct i915_request *, u64, u32, unsigned int);\n\tint (*emit_init_breadcrumb)(struct i915_request *);\n\tu32 * (*emit_fini_breadcrumb)(struct i915_request *, u32 *);\n\tunsigned int emit_fini_breadcrumb_dw;\n\tvoid (*submit_request)(struct i915_request *);\n\tvoid (*release)(struct intel_engine_cs *);\n\tvoid (*add_active_request)(struct i915_request *);\n\tvoid (*remove_active_request)(struct i915_request *);\n\tktime_t (*busyness)(struct intel_engine_cs *, ktime_t *);\n\tstruct intel_engine_execlists execlists;\n\tstruct intel_timeline *retire;\n\tstruct work_struct retire_work;\n\tstruct atomic_notifier_head context_status_notifier;\n\tunsigned int flags;\n\tstruct hlist_head cmd_hash[512];\n\tconst struct drm_i915_reg_table *reg_tables;\n\tint reg_table_count;\n\tu32 (*get_cmd_length_mask)(u32);\n\tstruct {\n\t\tunion {\n\t\t\tstruct intel_engine_execlists_stats execlists;\n\t\t\tstruct intel_engine_guc_stats guc;\n\t\t};\n\t\tktime_t rps;\n\t} stats;\n\tstruct {\n\t\tlong unsigned int heartbeat_interval_ms;\n\t\tlong unsigned int max_busywait_duration_ns;\n\t\tlong unsigned int preempt_timeout_ms;\n\t\tlong unsigned int stop_timeout_ms;\n\t\tlong unsigned int timeslice_duration_ms;\n\t} props;\n\tstruct {\n\t\tlong unsigned int heartbeat_interval_ms;\n\t\tlong unsigned int max_busywait_duration_ns;\n\t\tlong unsigned int preempt_timeout_ms;\n\t\tlong unsigned int stop_timeout_ms;\n\t\tlong unsigned int timeslice_duration_ms;\n\t} defaults;\n\tstruct i915_perf_group *oa_group;\n};\n\nstruct intel_context_stats {\n\tu64 active;\n\tstruct {\n\t\tstruct ewma_runtime avg;\n\t\tu64 total;\n\t\tu32 last;\n\t} runtime;\n};\n\nstruct i915_gem_context;\n\nstruct intel_context {\n\tunion {\n\t\tstruct kref ref;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct intel_engine_cs *engine;\n\tstruct intel_engine_cs *inflight;\n\tstruct i915_address_space *vm;\n\tstruct i915_gem_context *gem_context;\n\tstruct file *default_state;\n\tstruct list_head signal_link;\n\tstruct list_head signals;\n\tspinlock_t signal_lock;\n\tstruct i915_vma *state;\n\tu32 ring_size;\n\tstruct intel_ring *ring;\n\tstruct intel_timeline *timeline;\n\tintel_wakeref_t wakeref;\n\tlong unsigned int flags;\n\tstruct {\n\t\tu64 timeout_us;\n\t} watchdog;\n\tu32 *lrc_reg_state;\n\tunion {\n\t\tstruct {\n\t\t\tu32 lrca;\n\t\t\tu32 ccid;\n\t\t};\n\t\tu64 desc;\n\t} lrc;\n\tu32 tag;\n\tstruct intel_context_stats stats;\n\tunsigned int active_count;\n\tatomic_t pin_count;\n\tstruct mutex pin_mutex;\n\tstruct i915_active active;\n\tconst struct intel_context_ops *ops;\n\tstruct intel_sseu sseu;\n\tstruct list_head pinned_contexts_link;\n\tu8 wa_bb_page;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tu32 sched_state;\n\t\tstruct list_head fences;\n\t\tstruct i915_sw_fence blocked;\n\t\tstruct list_head requests;\n\t\tu8 prio;\n\t\tu32 prio_count[4];\n\t\tstruct delayed_work sched_disable_delay_work;\n\t} guc_state;\n\tstruct {\n\t\tu16 id;\n\t\tatomic_t ref;\n\t\tstruct list_head link;\n\t} guc_id;\n\tstruct list_head destroyed_link;\n\tstruct {\n\t\tunion {\n\t\t\tstruct list_head child_list;\n\t\t\tstruct list_head child_link;\n\t\t};\n\t\tstruct intel_context *parent;\n\t\tstruct i915_request *last_rq;\n\t\tu64 fence_context;\n\t\tu32 seqno;\n\t\tu8 number_children;\n\t\tu8 child_index;\n\t\tstruct {\n\t\t\tu16 wqi_head;\n\t\t\tu16 wqi_tail;\n\t\t\tu32 *wq_head;\n\t\t\tu32 *wq_tail;\n\t\t\tu32 *wq_status;\n\t\t\tu8 parent_page;\n\t\t} guc;\n\t} parallel;\n};\n\nstruct guc_virtual_engine {\n\tstruct intel_engine_cs base;\n\tstruct intel_context context;\n};\n\nstruct guest_domain_mapping_info {\n\trefcount_t users;\n\tu32 hdom_id;\n};\n\nstruct guid_block {\n\tguid_t guid;\n\tunion {\n\t\tchar object_id[2];\n\t\tstruct {\n\t\t\tunsigned char notify_id;\n\t\t\tunsigned char reserved;\n\t\t};\n\t};\n\tu8 instance_count;\n\tu8 flags;\n};\n\nunion handle_parts {\n\tdepot_stack_handle_t handle;\n\tstruct {\n\t\tu32 pool_index_plus_1: 17;\n\t\tu32 offset: 10;\n\t\tu32 extra: 5;\n\t};\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct handshake_net {\n\tspinlock_t hn_lock;\n\tint hn_pending;\n\tint hn_pending_max;\n\tstruct list_head hn_requests;\n\tlong unsigned int hn_flags;\n};\n\nstruct handshake_req;\n\nstruct handshake_proto {\n\tint hp_handler_class;\n\tsize_t hp_privsize;\n\tlong unsigned int hp_flags;\n\tint (*hp_accept)(struct handshake_req *, struct genl_info *, int);\n\tvoid (*hp_done)(struct handshake_req *, unsigned int, struct genl_info *);\n\tvoid (*hp_destroy)(struct handshake_req *);\n};\n\nstruct handshake_req {\n\tstruct list_head hr_list;\n\tstruct rhash_head hr_rhash;\n\tlong unsigned int hr_flags;\n\tconst struct handshake_proto *hr_proto;\n\tstruct sock *hr_sk;\n\tvoid (*hr_odestruct)(struct sock *);\n\tchar hr_priv[0];\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hash_cell {\n\tstruct rb_node name_node;\n\tstruct rb_node uuid_node;\n\tbool name_set;\n\tbool uuid_set;\n\tchar *name;\n\tchar *uuid;\n\tstruct mapped_device *md;\n\tstruct dm_table *new_map;\n};\n\nstruct hash_prefix {\n\tconst char *name;\n\tconst u8 *data;\n\tsize_t size;\n};\n\nstruct hashtab_key_params {\n\tu32 (*hash)(const void *);\n\tint (*cmp)(const void *, const void *);\n};\n\nstruct hashtab_node {\n\tvoid *key;\n\tvoid *datum;\n\tstruct hashtab_node *next;\n};\n\nstruct mei_client_properties {\n\tuuid_le protocol_name;\n\tu8 protocol_version;\n\tu8 max_number_of_connections;\n\tu8 fixed_address;\n\tu8 single_recv_buf: 1;\n\tu8 vt_supported: 1;\n\tu8 reserved: 6;\n\tu32 max_msg_length;\n};\n\nstruct hbm_add_client_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 reserved[2];\n\tstruct mei_client_properties client_properties;\n};\n\nstruct hbm_add_client_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 status;\n\tu8 reserved;\n};\n\nstruct hbm_capability_request {\n\tu8 hbm_cmd;\n\tu8 capability_requested[3];\n};\n\nstruct hbm_capability_response {\n\tu8 hbm_cmd;\n\tu8 capability_granted[3];\n};\n\nstruct hbm_client_connect_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 reserved;\n};\n\nstruct hbm_client_connect_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 status;\n};\n\nstruct hbm_client_dma_map_request {\n\tu8 hbm_cmd;\n\tu8 client_buffer_id;\n\tu8 reserved[2];\n\tu32 address_lsb;\n\tu32 address_msb;\n\tu32 size;\n};\n\nstruct hbm_client_dma_response {\n\tu8 hbm_cmd;\n\tu8 status;\n};\n\nstruct hbm_client_dma_unmap_request {\n\tu8 hbm_cmd;\n\tu8 status;\n\tu8 client_buffer_id;\n\tu8 reserved;\n};\n\nstruct hbm_dma_mem_dscr {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 size;\n};\n\nstruct hbm_dma_ring_ctrl {\n\tu32 hbuf_wr_idx;\n\tu32 reserved1;\n\tu32 hbuf_rd_idx;\n\tu32 reserved2;\n\tu32 dbuf_wr_idx;\n\tu32 reserved3;\n\tu32 dbuf_rd_idx;\n\tu32 reserved4;\n};\n\nstruct hbm_dma_setup_request {\n\tu8 hbm_cmd;\n\tu8 reserved[3];\n\tstruct hbm_dma_mem_dscr dma_dscr[3];\n};\n\nstruct hbm_dma_setup_response {\n\tu8 hbm_cmd;\n\tu8 status;\n\tu8 reserved[2];\n};\n\nstruct hbm_flow_control {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 reserved[5];\n};\n\nstruct hbm_host_enum_request {\n\tu8 hbm_cmd;\n\tu8 flags;\n\tu8 reserved[2];\n};\n\nstruct hbm_host_enum_response {\n\tu8 hbm_cmd;\n\tu8 reserved[3];\n\tu8 valid_addresses[32];\n};\n\nstruct hbm_host_stop_request {\n\tu8 hbm_cmd;\n\tu8 reason;\n\tu8 reserved[2];\n};\n\nstruct hbm_version {\n\tu8 minor_version;\n\tu8 major_version;\n};\n\nstruct hbm_host_version_request {\n\tu8 hbm_cmd;\n\tu8 reserved;\n\tstruct hbm_version host_version;\n};\n\nstruct hbm_host_version_response {\n\tu8 hbm_cmd;\n\tu8 host_version_supported;\n\tstruct hbm_version me_max_version;\n};\n\nstruct hbm_notification_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 start;\n};\n\nstruct hbm_notification_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 status;\n\tu8 start;\n\tu8 reserved[3];\n};\n\nstruct hbm_power_gate {\n\tu8 hbm_cmd;\n\tu8 reserved[3];\n};\n\nstruct hbm_props_request {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 reserved[2];\n};\n\nstruct hbm_props_response {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 status;\n\tu8 reserved;\n\tstruct mei_client_properties client_properties;\n};\n\nstruct hc_driver {\n\tconst char *description;\n\tconst char *product_desc;\n\tsize_t hcd_priv_size;\n\tirqreturn_t (*irq)(struct usb_hcd *);\n\tint flags;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*pci_suspend)(struct usb_hcd *, bool);\n\tint (*pci_resume)(struct usb_hcd *, pm_message_t);\n\tint (*pci_poweroff_late)(struct usb_hcd *, bool);\n\tvoid (*stop)(struct usb_hcd *);\n\tvoid (*shutdown)(struct usb_hcd *);\n\tint (*get_frame_number)(struct usb_hcd *);\n\tint (*urb_enqueue)(struct usb_hcd *, struct urb *, gfp_t);\n\tint (*urb_dequeue)(struct usb_hcd *, struct urb *, int);\n\tint (*map_urb_for_dma)(struct usb_hcd *, struct urb *, gfp_t);\n\tvoid (*unmap_urb_for_dma)(struct usb_hcd *, struct urb *);\n\tvoid (*endpoint_disable)(struct usb_hcd *, struct usb_host_endpoint *);\n\tvoid (*endpoint_reset)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*hub_status_data)(struct usb_hcd *, char *);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n\tint (*bus_suspend)(struct usb_hcd *);\n\tint (*bus_resume)(struct usb_hcd *);\n\tint (*start_port_reset)(struct usb_hcd *, unsigned int);\n\tlong unsigned int (*get_resuming_ports)(struct usb_hcd *);\n\tvoid (*relinquish_port)(struct usb_hcd *, int);\n\tint (*port_handed_over)(struct usb_hcd *, int);\n\tvoid (*clear_tt_buffer_complete)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*alloc_dev)(struct usb_hcd *, struct usb_device *);\n\tvoid (*free_dev)(struct usb_hcd *, struct usb_device *);\n\tint (*alloc_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, unsigned int, gfp_t);\n\tint (*free_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, gfp_t);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*address_device)(struct usb_hcd *, struct usb_device *, unsigned int);\n\tint (*enable_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*reset_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_device)(struct usb_hcd *, struct usb_device *);\n\tint (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);\n\tint (*enable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*disable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*find_raw_port_number)(struct usb_hcd *, int);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n\tint (*submit_single_step_set_feature)(struct usb_hcd *, struct urb *, int);\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hda_amp_list {\n\thda_nid_t nid;\n\tunsigned char dir;\n\tunsigned char idx;\n};\n\nstruct hda_beep {\n\tstruct input_dev *dev;\n\tstruct hda_codec *codec;\n\tchar phys[32];\n\tint tone;\n\thda_nid_t nid;\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int linear_tone: 1;\n\tunsigned int playing: 1;\n\tunsigned int keep_power_at_enable: 1;\n\tstruct work_struct beep_work;\n\tvoid (*power_hook)(struct hda_beep *, bool);\n};\n\nstruct snd_array {\n\tunsigned int used;\n\tunsigned int alloced;\n\tunsigned int elem_size;\n\tunsigned int alloc_align;\n\tvoid *list;\n};\n\nstruct hdac_widget_tree;\n\nstruct regmap;\n\nstruct hdac_device {\n\tstruct device dev;\n\tint type;\n\tstruct hdac_bus *bus;\n\tunsigned int addr;\n\tstruct list_head list;\n\thda_nid_t afg;\n\thda_nid_t mfg;\n\tunsigned int vendor_id;\n\tunsigned int subsystem_id;\n\tunsigned int revision_id;\n\tunsigned int afg_function_id;\n\tunsigned int mfg_function_id;\n\tunsigned int afg_unsol: 1;\n\tunsigned int mfg_unsol: 1;\n\tunsigned int power_caps;\n\tconst char *vendor_name;\n\tconst char *chip_name;\n\tint (*exec_verb)(struct hdac_device *, unsigned int, unsigned int, unsigned int *);\n\tunsigned int num_nodes;\n\thda_nid_t start_nid;\n\thda_nid_t end_nid;\n\tatomic_t in_pm;\n\tstruct mutex widget_lock;\n\tstruct hdac_widget_tree *widgets;\n\tstruct regmap *regmap;\n\tstruct mutex regmap_lock;\n\tstruct snd_array vendor_verbs;\n\tbool lazy_cache: 1;\n\tbool caps_overwriting: 1;\n\tbool cache_coef: 1;\n\tunsigned int registered: 1;\n};\n\nstruct hda_device_id;\n\nstruct snd_hwdep;\n\nstruct snd_info_buffer;\n\nstruct hda_fixup;\n\nstruct hda_codec {\n\tstruct hdac_device core;\n\tstruct hda_bus *bus;\n\tstruct snd_card *card;\n\tunsigned int addr;\n\tu32 probe_id;\n\tconst struct hda_device_id *preset;\n\tconst char *modelname;\n\tstruct list_head pcm_list_head;\n\trefcount_t pcm_ref;\n\twait_queue_head_t remove_sleep;\n\tvoid *spec;\n\tstruct hda_beep *beep;\n\tunsigned int beep_mode;\n\tbool beep_just_power_on;\n\tu32 *wcaps;\n\tstruct snd_array mixers;\n\tstruct snd_array nids;\n\tstruct list_head conn_list;\n\tstruct mutex spdif_mutex;\n\tstruct mutex control_mutex;\n\tstruct snd_array spdif_out;\n\tunsigned int spdif_in_enable;\n\tconst hda_nid_t *follower_dig_outs;\n\tstruct snd_array init_pins;\n\tstruct snd_array driver_pins;\n\tstruct snd_array cvt_setups;\n\tstruct mutex user_mutex;\n\tstruct snd_hwdep *hwdep;\n\tunsigned int configured: 1;\n\tunsigned int in_freeing: 1;\n\tunsigned int display_power_control: 1;\n\tunsigned int spdif_status_reset: 1;\n\tunsigned int pin_amp_workaround: 1;\n\tunsigned int single_adc_amp: 1;\n\tunsigned int no_sticky_stream: 1;\n\tunsigned int pins_shutup: 1;\n\tunsigned int no_trigger_sense: 1;\n\tunsigned int no_jack_detect: 1;\n\tunsigned int inv_eapd: 1;\n\tunsigned int inv_jack_detect: 1;\n\tunsigned int pcm_format_first: 1;\n\tunsigned int cached_write: 1;\n\tunsigned int dp_mst: 1;\n\tunsigned int dump_coef: 1;\n\tunsigned int power_save_node: 1;\n\tunsigned int auto_runtime_pm: 1;\n\tunsigned int force_pin_prefix: 1;\n\tunsigned int link_down_at_suspend: 1;\n\tunsigned int relaxed_resume: 1;\n\tunsigned int forced_resume: 1;\n\tunsigned int no_stream_clean_at_suspend: 1;\n\tunsigned int ctl_dev_id: 1;\n\tlong unsigned int power_on_acct;\n\tlong unsigned int power_off_acct;\n\tlong unsigned int power_jiffies;\n\tunsigned int (*power_filter)(struct hda_codec *, hda_nid_t, unsigned int);\n\tvoid (*proc_widget_hook)(struct snd_info_buffer *, struct hda_codec *, hda_nid_t);\n\tstruct snd_array jacktbl;\n\tlong unsigned int jackpoll_interval;\n\tstruct delayed_work jackpoll_work;\n\tint depop_delay;\n\tint fixup_id;\n\tconst struct hda_fixup *fixup_list;\n\tconst char *fixup_name;\n\tstruct snd_array verbs;\n};\n\nstruct hdac_driver {\n\tstruct device_driver driver;\n\tint type;\n\tconst struct hda_device_id *id_table;\n\tint (*match)(struct hdac_device *, const struct hdac_driver *);\n\tvoid (*unsol_event)(struct hdac_device *, unsigned int);\n\tint (*probe)(struct hdac_device *);\n\tint (*remove)(struct hdac_device *);\n\tvoid (*shutdown)(struct hdac_device *);\n};\n\nstruct hda_codec_ops;\n\nstruct hda_codec_driver {\n\tstruct hdac_driver core;\n\tconst struct hda_device_id *id;\n\tconst struct hda_codec_ops *ops;\n};\n\nstruct hda_codec_ops {\n\tint (*probe)(struct hda_codec *, const struct hda_device_id *);\n\tvoid (*remove)(struct hda_codec *);\n\tint (*build_controls)(struct hda_codec *);\n\tint (*build_pcms)(struct hda_codec *);\n\tint (*init)(struct hda_codec *);\n\tvoid (*unsol_event)(struct hda_codec *, unsigned int);\n\tvoid (*set_power_state)(struct hda_codec *, hda_nid_t, unsigned int);\n\tint (*suspend)(struct hda_codec *);\n\tint (*resume)(struct hda_codec *);\n\tint (*check_power_status)(struct hda_codec *, hda_nid_t);\n\tvoid (*stream_pm)(struct hda_codec *, hda_nid_t, bool);\n};\n\nstruct hda_conn_list {\n\tstruct list_head list;\n\tint len;\n\thda_nid_t nid;\n\thda_nid_t conns[0];\n};\n\nstruct hda_controller_ops {\n\tint (*disable_msi_reset_irq)(struct azx *);\n\tint (*position_check)(struct azx *, struct azx_dev *);\n\tint (*link_power)(struct azx *, bool);\n};\n\nstruct hda_cvt_setup {\n\thda_nid_t nid;\n\tu8 stream_tag;\n\tu8 channel_id;\n\tu16 format_id;\n\tunsigned char active;\n\tunsigned char dirty;\n};\n\nstruct hda_device_id {\n\t__u32 vendor_id;\n\t__u32 rev_id;\n\t__u8 api_version;\n\tconst char *name;\n\tlong unsigned int driver_data;\n};\n\nstruct hda_pintbl;\n\nstruct hda_verb;\n\nstruct hda_fixup {\n\tint type;\n\tbool chained: 1;\n\tbool chained_before: 1;\n\tint chain_id;\n\tunion {\n\t\tconst struct hda_pintbl *pins;\n\t\tconst struct hda_verb *verbs;\n\t\tvoid (*func)(struct hda_codec *, const struct hda_fixup *, int);\n\t} v;\n};\n\nstruct hda_input_mux_item {\n\tchar label[32];\n\tunsigned int index;\n};\n\nstruct hda_input_mux {\n\tunsigned int num_items;\n\tstruct hda_input_mux_item items[36];\n};\n\nstruct hda_intel {\n\tstruct azx chip;\n\tstruct work_struct irq_pending_work;\n\tstruct completion probe_wait;\n\tstruct delayed_work probe_work;\n\tstruct list_head list;\n\tunsigned int irq_pending_warned: 1;\n\tunsigned int probe_continued: 1;\n\tunsigned int runtime_pm_disabled: 1;\n\tunsigned int use_vga_switcheroo: 1;\n\tunsigned int vga_switcheroo_registered: 1;\n\tunsigned int init_failed: 1;\n\tunsigned int freed: 1;\n\tbool need_i915_power: 1;\n\tint probe_retry;\n};\n\nstruct hda_jack_callback;\n\ntypedef void (*hda_jack_callback_fn)(struct hda_codec *, struct hda_jack_callback *);\n\nstruct hda_jack_tbl;\n\nstruct hda_jack_callback {\n\thda_nid_t nid;\n\tint dev_id;\n\thda_jack_callback_fn func;\n\tunsigned int private_data;\n\tunsigned int unsol_res;\n\tstruct hda_jack_tbl *jack;\n\tstruct hda_jack_callback *next;\n};\n\nstruct hda_jack_keymap {\n\tenum snd_jack_types type;\n\tint key;\n};\n\nstruct snd_jack;\n\nstruct hda_jack_tbl {\n\thda_nid_t nid;\n\tint dev_id;\n\tunsigned char tag;\n\tstruct hda_jack_callback *callback;\n\tunsigned int pin_sense;\n\tunsigned int jack_detect: 1;\n\tunsigned int jack_dirty: 1;\n\tunsigned int phantom_jack: 1;\n\tunsigned int block_report: 1;\n\thda_nid_t gating_jack;\n\thda_nid_t gated_jack;\n\thda_nid_t key_report_jack;\n\tint type;\n\tint button_state;\n\tstruct snd_jack *jack;\n};\n\nstruct hda_loopback_check {\n\tconst struct hda_amp_list *amplist;\n\tint power_on;\n};\n\nstruct hda_model_fixup {\n\tconst int id;\n\tconst char *name;\n};\n\nstruct hda_multi_out {\n\tint num_dacs;\n\tconst hda_nid_t *dac_nids;\n\thda_nid_t hp_nid;\n\thda_nid_t hp_out_nid[5];\n\thda_nid_t extra_out_nid[5];\n\thda_nid_t dig_out_nid;\n\tconst hda_nid_t *follower_dig_outs;\n\tint max_channels;\n\tint dig_out_used;\n\tint no_share_stream;\n\tint share_spdif;\n\tunsigned int analog_rates;\n\tunsigned int analog_maxbps;\n\tu64 analog_formats;\n\tunsigned int spdif_rates;\n\tunsigned int spdif_maxbps;\n\tu64 spdif_formats;\n};\n\nstruct snd_kcontrol;\n\nstruct hda_nid_item {\n\tstruct snd_kcontrol *kctl;\n\tunsigned int index;\n\thda_nid_t nid;\n\tshort unsigned int flags;\n};\n\nstruct hda_pcm_stream;\n\nstruct hda_pcm_ops {\n\tint (*open)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tint (*close)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tint (*prepare)(struct hda_pcm_stream *, struct hda_codec *, unsigned int, unsigned int, struct snd_pcm_substream *);\n\tint (*cleanup)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tunsigned int (*get_delay)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n};\n\nstruct snd_pcm_chmap_elem;\n\nstruct hda_pcm_stream {\n\tunsigned int substreams;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\thda_nid_t nid;\n\tu32 rates;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int maxbps;\n\tconst struct snd_pcm_chmap_elem *chmap;\n\tstruct hda_pcm_ops ops;\n};\n\nstruct hda_pcm {\n\tchar *name;\n\tstruct hda_pcm_stream stream[2];\n\tunsigned int pcm_type;\n\tint device;\n\tstruct snd_pcm *pcm;\n\tbool own_chmap;\n\tstruct hda_codec *codec;\n\tstruct list_head list;\n\tunsigned int disconnected: 1;\n};\n\nstruct hda_pincfg {\n\thda_nid_t nid;\n\tunsigned char ctrl;\n\tunsigned char target;\n\tunsigned int cfg;\n};\n\nstruct hda_pintbl {\n\thda_nid_t nid;\n\tu32 val;\n};\n\nstruct hda_quirk {\n\tshort unsigned int subvendor;\n\tshort unsigned int subdevice;\n\tshort unsigned int subdevice_mask;\n\tbool match_codec_ssid;\n\tint value;\n};\n\nstruct hda_rate_tbl {\n\tunsigned int hz;\n\tunsigned int alsa_bits;\n\tunsigned int hda_fmt;\n};\n\nstruct hda_spdif_out {\n\thda_nid_t nid;\n\tunsigned int status;\n\tshort unsigned int ctls;\n};\n\nstruct hda_vendor_id {\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct hda_verb {\n\thda_nid_t nid;\n\tu32 verb;\n\tu32 param;\n};\n\nstruct hda_verb_ioctl {\n\tu32 verb;\n\tu32 res;\n};\n\nstruct hda_vmaster_mute_hook {\n\tstruct snd_kcontrol *sw_kctl;\n\tvoid (*hook)(void *, int);\n\tstruct hda_codec *codec;\n};\n\nstruct hdac_bus_ops {\n\tint (*command)(struct hdac_bus *, unsigned int);\n\tint (*get_response)(struct hdac_bus *, unsigned int, unsigned int *);\n\tvoid (*link_power)(struct hdac_device *, bool);\n};\n\nstruct hdac_cea_channel_speaker_allocation {\n\tint ca_index;\n\tint speakers[8];\n\tint channels;\n\tint spk_mask;\n};\n\nstruct hdac_chmap;\n\nstruct hdac_chmap_ops {\n\tint (*chmap_cea_alloc_validate_get_type)(struct hdac_chmap *, struct hdac_cea_channel_speaker_allocation *, int);\n\tvoid (*cea_alloc_to_tlv_chmap)(struct hdac_chmap *, struct hdac_cea_channel_speaker_allocation *, unsigned int *, int);\n\tint (*chmap_validate)(struct hdac_chmap *, int, int, unsigned char *);\n\tint (*get_spk_alloc)(struct hdac_device *, int);\n\tvoid (*get_chmap)(struct hdac_device *, int, unsigned char *);\n\tvoid (*set_chmap)(struct hdac_device *, int, unsigned char *, int);\n\tbool (*is_pcm_attached)(struct hdac_device *, int);\n\tint (*pin_get_slot_channel)(struct hdac_device *, hda_nid_t, int);\n\tint (*pin_set_slot_channel)(struct hdac_device *, hda_nid_t, int, int);\n\tvoid (*set_channel_count)(struct hdac_device *, hda_nid_t, int);\n};\n\nstruct hdac_chmap {\n\tunsigned int channels_max;\n\tstruct hdac_chmap_ops ops;\n\tstruct hdac_device *hdac;\n};\n\nstruct hdac_ext_bus_ops {\n\tint (*hdev_attach)(struct hdac_device *);\n\tint (*hdev_detach)(struct hdac_device *);\n};\n\nstruct hdac_widget_tree {\n\tstruct kobject *root;\n\tstruct kobject *afg;\n\tstruct kobject **nodes;\n};\n\nstruct hdcp2_tx_caps {\n\tu8 version;\n\tu8 tx_cap_mask[2];\n};\n\nstruct hdcp2_ake_init {\n\tu8 msg_id;\n\tu8 r_tx[8];\n\tstruct hdcp2_tx_caps tx_caps;\n};\n\nstruct hdcp2_ake_no_stored_km {\n\tu8 msg_id;\n\tu8 e_kpub_km[128];\n};\n\nstruct hdcp2_cert_rx {\n\tu8 receiver_id[5];\n\tu8 kpub_rx[131];\n\tu8 reserved[2];\n\tu8 dcp_signature[384];\n};\n\nstruct hdcp2_ake_send_cert {\n\tu8 msg_id;\n\tstruct hdcp2_cert_rx cert_rx;\n\tu8 r_rx[8];\n\tu8 rx_caps[3];\n};\n\nstruct hdcp2_ake_send_hprime {\n\tu8 msg_id;\n\tu8 h_prime[32];\n};\n\nstruct hdcp2_ake_send_pairing_info {\n\tu8 msg_id;\n\tu8 e_kh_km[16];\n};\n\nstruct hdcp2_dp_errata_stream_type {\n\tu8 msg_id;\n\tu8 stream_type;\n};\n\nstruct hdcp2_dp_msg_data {\n\tu8 msg_id;\n\tu32 offset;\n\tbool msg_detectable;\n\tu32 timeout;\n\tu32 timeout2;\n\tu32 msg_read_timeout;\n};\n\nstruct hdcp2_hdmi_msg_timeout {\n\tu8 msg_id;\n\tu16 timeout;\n};\n\nstruct hdcp2_lc_init {\n\tu8 msg_id;\n\tu8 r_n[8];\n};\n\nstruct hdcp2_lc_send_lprime {\n\tu8 msg_id;\n\tu8 l_prime[32];\n};\n\nstruct hdcp2_rep_send_ack {\n\tu8 msg_id;\n\tu8 v[16];\n};\n\nstruct hdcp2_rep_send_receiverid_list {\n\tu8 msg_id;\n\tu8 rx_info[2];\n\tu8 seq_num_v[3];\n\tu8 v_prime[16];\n\tu8 receiver_ids[155];\n};\n\nstruct hdcp2_streamid_type {\n\tu8 stream_id;\n\tu8 stream_type;\n};\n\nstruct hdcp2_rep_stream_manage {\n\tu8 msg_id;\n\tu8 seq_num_m[3];\n\t__be16 k;\n\tstruct hdcp2_streamid_type streams[4];\n};\n\nstruct hdcp2_rep_stream_ready {\n\tu8 msg_id;\n\tu8 m_prime[32];\n};\n\nstruct hdcp2_ske_send_eks {\n\tu8 msg_id;\n\tu8 e_dkey_ks[16];\n\tu8 riv[8];\n};\n\nstruct hdcp_cmd_header {\n\tu32 api_version;\n\tu32 command_id;\n\tenum fw_hdcp_status status;\n\tu32 buffer_len;\n};\n\nstruct hdcp_port_data {\n\tenum hdcp_ddi hdcp_ddi;\n\tenum hdcp_transcoder hdcp_transcoder;\n\tu8 port_type;\n\tu8 protocol;\n\tu16 k;\n\tu32 seq_num_m;\n\tstruct hdcp2_streamid_type *streams;\n};\n\nstruct hdcp_port_id {\n\tu8 integrated_port_type;\n\tu8 physical_port;\n\tu8 attached_transcoder;\n\tu8 reserved;\n};\n\nstruct hdcp_srm_header {\n\tu8 srm_id;\n\tu8 reserved;\n\t__be16 srm_version;\n\tu8 srm_gen_no;\n} __attribute__((packed));\n\nstruct hdmi_aud_ncts {\n\tint sample_rate;\n\tint clock;\n\tint n;\n\tint cts;\n};\n\nstruct hdr_metadata_infoframe {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} white_point;\n\t__u16 max_display_mastering_luminance;\n\t__u16 min_display_mastering_luminance;\n\t__u16 max_cll;\n\t__u16 max_fall;\n};\n\nstruct hdr_output_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_metadata_infoframe hdmi_metadata_type1;\n\t};\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[12];\n};\n\nstruct hib_bio_batch {\n\tatomic_t count;\n\twait_queue_head_t wait;\n\tblk_status_t error;\n\tstruct blk_plug plug;\n};\n\nstruct hid_class_descriptor {\n\t__u8 bDescriptorType;\n\t__le16 wDescriptorLength;\n} __attribute__((packed));\n\nstruct hid_collection {\n\tint parent_idx;\n\tunsigned int type;\n\tunsigned int usage;\n\tunsigned int level;\n};\n\nstruct hid_control_fifo {\n\tunsigned char dir;\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_debug_list {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tchar *type;\n\t\t\tconst char *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tchar *ptr;\n\t\t\tconst char *ptr_const;\n\t\t};\n\t\tchar buf[0];\n\t} hid_debug_fifo;\n\tstruct fasync_struct *fasync;\n\tstruct hid_device *hdev;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct hid_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdHID;\n\t__u8 bCountryCode;\n\t__u8 bNumDescriptors;\n\tstruct hid_class_descriptor rpt_desc;\n\tstruct hid_class_descriptor opt_descs[0];\n} __attribute__((packed));\n\nstruct hid_report_enum {\n\tunsigned int numbered;\n\tstruct list_head report_list;\n\tstruct hid_report *report_id_hash[256];\n};\n\nstruct hid_driver;\n\nstruct hid_ll_driver;\n\nstruct hid_field;\n\nstruct hid_usage;\n\nstruct hid_device {\n\tconst __u8 *dev_rdesc;\n\tconst __u8 *bpf_rdesc;\n\tconst __u8 *rdesc;\n\tunsigned int dev_rsize;\n\tunsigned int bpf_rsize;\n\tunsigned int rsize;\n\tunsigned int collection_size;\n\tstruct hid_collection *collection;\n\tunsigned int maxcollection;\n\tunsigned int maxapplication;\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\t__u32 version;\n\tenum hid_type type;\n\tunsigned int country;\n\tstruct hid_report_enum report_enum[3];\n\tstruct work_struct led_work;\n\tstruct semaphore driver_input_lock;\n\tstruct device dev;\n\tstruct hid_driver *driver;\n\tvoid *devres_group_id;\n\tconst struct hid_ll_driver *ll_driver;\n\tstruct mutex ll_open_lock;\n\tunsigned int ll_open_count;\n\tlong unsigned int status;\n\tunsigned int claimed;\n\tunsigned int quirks;\n\tunsigned int initial_quirks;\n\tbool io_started;\n\tstruct list_head inputs;\n\tvoid *hiddev;\n\tvoid *hidraw;\n\tchar name[128];\n\tchar phys[64];\n\tchar uniq[64];\n\tvoid *driver_data;\n\tint (*ff_init)(struct hid_device *);\n\tint (*hiddev_connect)(struct hid_device *, unsigned int);\n\tvoid (*hiddev_disconnect)(struct hid_device *);\n\tvoid (*hiddev_hid_event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*hiddev_report_event)(struct hid_device *, struct hid_report *);\n\tshort unsigned int debug;\n\tstruct dentry *debug_dir;\n\tstruct dentry *debug_rdesc;\n\tstruct dentry *debug_events;\n\tstruct list_head debug_list;\n\tspinlock_t debug_list_lock;\n\twait_queue_head_t debug_wait;\n\tstruct kref ref;\n\tunsigned int id;\n};\n\nstruct hid_device_id {\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hid_report_id;\n\nstruct hid_usage_id;\n\nstruct hid_input;\n\nstruct hid_driver {\n\tconst char *name;\n\tconst struct hid_device_id *id_table;\n\tstruct list_head dyn_list;\n\tspinlock_t dyn_lock;\n\tbool (*match)(struct hid_device *, bool);\n\tint (*probe)(struct hid_device *, const struct hid_device_id *);\n\tvoid (*remove)(struct hid_device *);\n\tconst struct hid_report_id *report_table;\n\tint (*raw_event)(struct hid_device *, struct hid_report *, u8 *, int);\n\tconst struct hid_usage_id *usage_table;\n\tint (*event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*report)(struct hid_device *, struct hid_report *);\n\tconst __u8 * (*report_fixup)(struct hid_device *, __u8 *, unsigned int *);\n\tint (*input_mapping)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_mapped)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_configured)(struct hid_device *, struct hid_input *);\n\tvoid (*feature_mapping)(struct hid_device *, struct hid_field *, struct hid_usage *);\n\tint (*suspend)(struct hid_device *, pm_message_t);\n\tint (*resume)(struct hid_device *);\n\tint (*reset_resume)(struct hid_device *);\n\tvoid (*on_hid_hw_open)(struct hid_device *);\n\tvoid (*on_hid_hw_close)(struct hid_device *);\n\tstruct device_driver driver;\n};\n\nstruct hid_dynid {\n\tstruct list_head list;\n\tstruct hid_device_id id;\n};\n\nstruct hid_field {\n\tunsigned int physical;\n\tunsigned int logical;\n\tunsigned int application;\n\tstruct hid_usage *usage;\n\tunsigned int maxusage;\n\tunsigned int flags;\n\tunsigned int report_offset;\n\tunsigned int report_size;\n\tunsigned int report_count;\n\tunsigned int report_type;\n\t__s32 *value;\n\t__s32 *new_value;\n\t__s32 *usages_priorities;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tbool ignored;\n\tstruct hid_report *report;\n\tunsigned int index;\n\tstruct hid_input *hidinput;\n\t__u16 dpad;\n\tunsigned int slot_idx;\n};\n\nstruct hid_field_entry {\n\tstruct list_head list;\n\tstruct hid_field *field;\n\tunsigned int index;\n\t__s32 priority;\n};\n\nstruct hid_global {\n\tunsigned int usage_page;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tunsigned int report_id;\n\tunsigned int report_size;\n\tunsigned int report_count;\n};\n\nstruct hid_input {\n\tstruct list_head list;\n\tstruct hid_report *report;\n\tstruct input_dev *input;\n\tconst char *name;\n\tstruct list_head reports;\n\tunsigned int application;\n\tbool registered;\n};\n\nstruct hid_item {\n\tunsigned int format;\n\t__u8 size;\n\t__u8 type;\n\t__u8 tag;\n\tunion {\n\t\t__u8 u8;\n\t\t__s8 s8;\n\t\t__u16 u16;\n\t\t__s16 s16;\n\t\t__u32 u32;\n\t\t__s32 s32;\n\t\tconst __u8 *longdata;\n\t} data;\n};\n\nstruct hid_ll_driver {\n\tint (*start)(struct hid_device *);\n\tvoid (*stop)(struct hid_device *);\n\tint (*open)(struct hid_device *);\n\tvoid (*close)(struct hid_device *);\n\tint (*power)(struct hid_device *, int);\n\tint (*parse)(struct hid_device *);\n\tvoid (*request)(struct hid_device *, struct hid_report *, int);\n\tint (*wait)(struct hid_device *);\n\tint (*raw_request)(struct hid_device *, unsigned char, __u8 *, size_t, unsigned char, int);\n\tint (*output_report)(struct hid_device *, __u8 *, size_t);\n\tint (*idle)(struct hid_device *, int, int, int);\n\tbool (*may_wakeup)(struct hid_device *);\n\tunsigned int max_buffer_size;\n};\n\nstruct hid_local {\n\tunsigned int usage[12288];\n\tu8 usage_size[12288];\n\tunsigned int collection_index[12288];\n\tunsigned int usage_index;\n\tunsigned int usage_minimum;\n\tunsigned int delimiter_depth;\n\tunsigned int delimiter_branch;\n};\n\nstruct hid_output_fifo {\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_parser {\n\tstruct hid_global global;\n\tstruct hid_global global_stack[4];\n\tunsigned int global_stack_ptr;\n\tstruct hid_local local;\n\tunsigned int *collection_stack;\n\tunsigned int collection_stack_ptr;\n\tunsigned int collection_stack_size;\n\tstruct hid_device *device;\n\tunsigned int scan_flags;\n};\n\nstruct hid_report {\n\tstruct list_head list;\n\tstruct list_head hidinput_list;\n\tstruct list_head field_entry_list;\n\tunsigned int id;\n\tenum hid_report_type type;\n\tunsigned int application;\n\tstruct hid_field *field[256];\n\tstruct hid_field_entry *field_entries;\n\tunsigned int maxfield;\n\tunsigned int size;\n\tstruct hid_device *device;\n\tbool tool_active;\n\tunsigned int tool;\n};\n\nstruct hid_report_id {\n\t__u32 report_type;\n};\n\nstruct hid_usage {\n\tunsigned int hid;\n\tunsigned int collection_index;\n\tunsigned int usage_index;\n\t__s8 resolution_multiplier;\n\t__s8 wheel_factor;\n\t__u16 code;\n\t__u8 type;\n\t__s16 hat_min;\n\t__s16 hat_max;\n\t__s16 hat_dir;\n\t__s16 wheel_accumulated;\n};\n\nstruct hid_usage_entry {\n\tunsigned int page;\n\tunsigned int usage;\n\tconst char *description;\n};\n\nstruct hid_usage_id {\n\t__u32 usage_hid;\n\t__u32 usage_type;\n\t__u32 usage_code;\n};\n\nstruct hiddev {\n\tint minor;\n\tint exist;\n\tint open;\n\tstruct mutex existancelock;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tbool initialized;\n};\n\nstruct hiddev_collection_info {\n\t__u32 index;\n\t__u32 type;\n\t__u32 usage;\n\t__u32 level;\n};\n\nstruct hiddev_devinfo {\n\t__u32 bustype;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 ifnum;\n\t__s16 vendor;\n\t__s16 product;\n\t__s16 version;\n\t__u32 num_applications;\n};\n\nstruct hiddev_event {\n\tunsigned int hid;\n\tint value;\n};\n\nstruct hiddev_field_info {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 field_index;\n\t__u32 maxusage;\n\t__u32 flags;\n\t__u32 physical;\n\t__u32 logical;\n\t__u32 application;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__u32 unit_exponent;\n\t__u32 unit;\n};\n\nstruct hiddev_usage_ref {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 field_index;\n\t__u32 usage_index;\n\t__u32 usage_code;\n\t__s32 value;\n};\n\nstruct hiddev_list {\n\tstruct hiddev_usage_ref buffer[2048];\n\tint head;\n\tint tail;\n\tunsigned int flags;\n\tstruct fasync_struct *fasync;\n\tstruct hiddev *hiddev;\n\tstruct list_head node;\n\tstruct mutex thread_lock;\n};\n\nstruct hiddev_report_info {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 num_fields;\n};\n\nstruct hiddev_usage_ref_multi {\n\tstruct hiddev_usage_ref uref;\n\t__u32 num_values;\n\t__s32 values[1024];\n};\n\nstruct hidraw {\n\tunsigned int minor;\n\tint exist;\n\tint open;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct device *dev;\n\tspinlock_t list_lock;\n\tstruct list_head list;\n};\n\nstruct hidraw_devinfo {\n\t__u32 bustype;\n\t__s16 vendor;\n\t__s16 product;\n};\n\nstruct hidraw_report {\n\t__u8 *value;\n\tint len;\n};\n\nstruct hidraw_list {\n\tstruct hidraw_report buffer[64];\n\tint head;\n\tint tail;\n\tstruct fasync_struct *fasync;\n\tstruct hidraw *hidraw;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n\tbool revoked;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct hmac_ctx {\n\tstruct crypto_shash *hash;\n\tu8 pads[0];\n};\n\nstruct md5_block_state {\n\tu32 h[4];\n};\n\nstruct md5_ctx {\n\tstruct md5_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_md5_ctx {\n\tstruct md5_ctx hash_ctx;\n\tstruct md5_block_state ostate;\n};\n\nstruct hmac_md5_key {\n\tstruct md5_block_state istate;\n\tstruct md5_block_state ostate;\n};\n\nstruct sha1_block_state {\n\tu32 h[5];\n};\n\nstruct sha1_ctx {\n\tstruct sha1_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_sha1_ctx {\n\tstruct sha1_ctx sha_ctx;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha1_key {\n\tstruct sha1_block_state istate;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha384_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha384_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hmac_sha512_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha512_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct hpet_timer {\n\tu64 hpet_config;\n\tunion {\n\t\tu64 _hpet_hc64;\n\t\tu32 _hpet_hc32;\n\t\tlong unsigned int _hpet_compare;\n\t} _u1;\n\tu64 hpet_fsb[2];\n};\n\nstruct hpet {\n\tu64 hpet_cap;\n\tu64 res0;\n\tu64 hpet_config;\n\tu64 res1;\n\tu64 hpet_isr;\n\tu64 res2[25];\n\tunion {\n\t\tu64 _hpet_mc64;\n\t\tu32 _hpet_mc32;\n\t\tlong unsigned int _hpet_mc;\n\t} _u0;\n\tu64 res3;\n\tstruct hpet_timer hpet_timers[0];\n};\n\nstruct hpet_channel;\n\nstruct hpet_base {\n\tunsigned int nr_channels;\n\tunsigned int nr_clockevents;\n\tunsigned int boot_cfg;\n\tstruct hpet_channel *channels;\n};\n\nstruct hpet_channel {\n\tstruct clock_event_device evt;\n\tunsigned int num;\n\tunsigned int cpu;\n\tunsigned int irq;\n\tunsigned int in_use;\n\tenum hpet_mode mode;\n\tunsigned int boot_cfg;\n\tchar name[10];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hpet_data {\n\tlong unsigned int hd_phys_address;\n\tvoid *hd_address;\n\tshort unsigned int hd_nirqs;\n\tunsigned int hd_state;\n\tunsigned int hd_irq[32];\n};\n\nstruct hpets;\n\nstruct hpet_dev {\n\tstruct hpets *hd_hpets;\n\tstruct hpet *hd_hpet;\n\tstruct hpet_timer *hd_timer;\n\tlong unsigned int hd_ireqfreq;\n\tlong unsigned int hd_irqdata;\n\twait_queue_head_t hd_waitqueue;\n\tstruct fasync_struct *hd_async_queue;\n\tunsigned int hd_flags;\n\tunsigned int hd_irq;\n\tunsigned int hd_hdwirq;\n\tchar hd_name[7];\n};\n\nstruct hpet_info {\n\tlong unsigned int hi_ireqfreq;\n\tlong unsigned int hi_flags;\n\tshort unsigned int hi_hpet;\n\tshort unsigned int hi_timer;\n};\n\nunion hpet_lock {\n\tstruct {\n\t\tarch_spinlock_t lock;\n\t\tu32 value;\n\t};\n\tu64 lockval;\n};\n\nstruct hpets {\n\tstruct hpets *hp_next;\n\tstruct hpet *hp_hpet;\n\tlong unsigned int hp_hpet_phys;\n\tlong long unsigned int hp_tick_freq;\n\tlong unsigned int hp_delta;\n\tunsigned int hp_ntimer;\n\tunsigned int hp_which;\n\tstruct hpet_dev hp_dev[0];\n};\n\nstruct hprobe {\n\tenum hprobe_state state;\n\tint srcu_idx;\n\tstruct uprobe *uprobe;\n};\n\nstruct hpx_type0 {\n\tu32 revision;\n\tu8 cache_line_size;\n\tu8 latency_timer;\n\tu8 enable_serr;\n\tu8 enable_perr;\n};\n\nstruct hpx_type1 {\n\tu32 revision;\n\tu8 max_mem_read;\n\tu8 avg_max_split;\n\tu16 tot_max_split;\n};\n\nstruct hpx_type2 {\n\tu32 revision;\n\tu32 unc_err_mask_and;\n\tu32 unc_err_mask_or;\n\tu32 unc_err_sever_and;\n\tu32 unc_err_sever_or;\n\tu32 cor_err_mask_and;\n\tu32 cor_err_mask_or;\n\tu32 adv_err_cap_and;\n\tu32 adv_err_cap_or;\n\tu16 pci_exp_devctl_and;\n\tu16 pci_exp_devctl_or;\n\tu16 pci_exp_lnkctl_and;\n\tu16 pci_exp_lnkctl_or;\n\tu32 sec_unc_err_sever_and;\n\tu32 sec_unc_err_sever_or;\n\tu32 sec_unc_err_mask_and;\n\tu32 sec_unc_err_mask_or;\n};\n\nstruct hpx_type3 {\n\tu16 device_type;\n\tu16 function_type;\n\tu16 config_space_location;\n\tu16 pci_exp_cap_id;\n\tu16 pci_exp_cap_ver;\n\tu16 pci_exp_vendor_id;\n\tu16 dvsec_id;\n\tu16 dvsec_rev;\n\tu16 match_offset;\n\tu32 match_mask_and;\n\tu32 match_value;\n\tu16 reg_offset;\n\tu32 reg_mask_and;\n\tu32 reg_mask_or;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tktime_t offset;\n\tlong: 64;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tstruct hrtimer_clock_base clock_base[8];\n\tcall_single_data_t csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n};\n\nstruct hs_primary_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\t__u8 id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 unused4[28];\n\t__u8 root_directory_record[34];\n};\n\nstruct hs_volume_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2033];\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {\n\tstruct mutex resize_lock;\n\tstruct lock_class_key resize_key;\n\tint next_nid_to_alloc;\n\tint next_nid_to_free;\n\tunsigned int order;\n\tunsigned int demote_order;\n\tlong unsigned int mask;\n\tlong unsigned int max_huge_pages;\n\tlong unsigned int nr_huge_pages;\n\tlong unsigned int free_huge_pages;\n\tlong unsigned int resv_huge_pages;\n\tlong unsigned int surplus_huge_pages;\n\tlong unsigned int nr_overcommit_huge_pages;\n\tstruct list_head hugepage_activelist;\n\tstruct list_head hugepage_freelists[64];\n\tunsigned int max_huge_pages_node[64];\n\tunsigned int nr_huge_pages_node[64];\n\tunsigned int free_huge_pages_node[64];\n\tunsigned int surplus_huge_pages_node[64];\n\tchar name[32];\n};\n\nstruct hsu_dma_chan;\n\nstruct hsu_dma {\n\tstruct dma_device dma;\n\tstruct hsu_dma_chan *chan;\n\tshort unsigned int nr_channels;\n};\n\nstruct virt_dma_desc;\n\nstruct virt_dma_chan {\n\tstruct dma_chan chan;\n\tstruct tasklet_struct task;\n\tvoid (*desc_free)(struct virt_dma_desc *);\n\tspinlock_t lock;\n\tstruct list_head desc_allocated;\n\tstruct list_head desc_submitted;\n\tstruct list_head desc_issued;\n\tstruct list_head desc_completed;\n\tstruct list_head desc_terminated;\n\tstruct virt_dma_desc *cyclic;\n};\n\nstruct hsu_dma_desc;\n\nstruct hsu_dma_chan {\n\tstruct virt_dma_chan vchan;\n\tvoid *reg;\n\tenum dma_transfer_direction direction;\n\tstruct dma_slave_config config;\n\tstruct hsu_dma_desc *desc;\n};\n\nstruct hsu_dma_chip {\n\tstruct device *dev;\n\tint irq;\n\tvoid *regs;\n\tunsigned int length;\n\tunsigned int offset;\n\tstruct hsu_dma *hsu;\n};\n\nstruct virt_dma_desc {\n\tstruct dma_async_tx_descriptor tx;\n\tstruct dmaengine_result tx_result;\n\tstruct list_head node;\n};\n\nstruct hsu_dma_sg;\n\nstruct hsu_dma_desc {\n\tstruct virt_dma_desc vdesc;\n\tenum dma_transfer_direction direction;\n\tstruct hsu_dma_sg *sg;\n\tunsigned int nents;\n\tsize_t length;\n\tunsigned int active;\n\tenum dma_status status;\n};\n\nstruct hsu_dma_sg {\n\tdma_addr_t addr;\n\tunsigned int len;\n};\n\nstruct hsu_dma_slave {\n\tstruct device *dma_dev;\n\tint chan_id;\n};\n\nstruct hsw_ddi_buf_trans {\n\tu32 trans1;\n\tu32 trans2;\n\tu8 i_boost;\n};\n\nstruct hsw_dpll_hw_state {\n\tu32 wrpll;\n\tu32 spll;\n};\n\nunion hsw_tsx_tuning {\n\tstruct {\n\t\tu32 cycles_last_block: 32;\n\t\tu32 hle_abort: 1;\n\t\tu32 rtm_abort: 1;\n\t\tu32 instruction_abort: 1;\n\t\tu32 non_instruction_abort: 1;\n\t\tu32 retry: 1;\n\t\tu32 data_conflict: 1;\n\t\tu32 capacity_writes: 1;\n\t\tu32 capacity_reads: 1;\n\t};\n\tu64 value;\n};\n\nstruct hsw_wrpll_rnp {\n\tunsigned int p;\n\tunsigned int n2;\n\tunsigned int r2;\n};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tlong: 0;\n\tchar key[0];\n};\n\nstruct cma;\n\nstruct huge_bootmem_page {\n\tstruct list_head list;\n\tstruct hstate *hstate;\n\tlong unsigned int flags;\n\tstruct cma *cma;\n};\n\nstruct hugepage_subpool {\n\tspinlock_t lock;\n\tlong int count;\n\tlong int max_hpages;\n\tlong int used_hpages;\n\tstruct hstate *hstate;\n\tlong int min_hpages;\n\tlong int rsv_hpages;\n};\n\nstruct page_counter {\n\tatomic_long_t usage;\n\tlong unsigned int failcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int emin;\n\tatomic_long_t min_usage;\n\tatomic_long_t children_min_usage;\n\tlong unsigned int elow;\n\tatomic_long_t low_usage;\n\tatomic_long_t children_low_usage;\n\tlong unsigned int watermark;\n\tlong unsigned int local_watermark;\n\tstruct cacheline_padding _pad2_;\n\tbool protection_support;\n\tbool track_failcnt;\n\tlong unsigned int min;\n\tlong unsigned int low;\n\tlong unsigned int high;\n\tlong unsigned int max;\n\tstruct page_counter *parent;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hugetlb_cgroup_per_node;\n\nstruct hugetlb_cgroup {\n\tstruct cgroup_subsys_state css;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter hugepage[2];\n\tstruct page_counter rsvd_hugepage[2];\n\tatomic_long_t events[2];\n\tatomic_long_t events_local[2];\n\tstruct cgroup_file events_file[2];\n\tstruct cgroup_file events_local_file[2];\n\tstruct hugetlb_cgroup_per_node *nodeinfo[0];\n};\n\nstruct hugetlb_cgroup_per_node {\n\tlong unsigned int usage[2];\n};\n\nstruct hugetlb_cmdline {\n\tchar *val;\n\tint (*setup)(char *);\n};\n\nstruct hugetlb_vma_lock {\n\tstruct kref refs;\n\tstruct rw_semaphore rw_sema;\n\tstruct vm_area_struct *vma;\n};\n\nstruct hugetlbfs_fs_context {\n\tstruct hstate *hstate;\n\tlong long unsigned int max_size_opt;\n\tlong long unsigned int min_size_opt;\n\tlong int max_hpages;\n\tlong int nr_inodes;\n\tlong int min_hpages;\n\tenum hugetlbfs_size_type max_val_type;\n\tenum hugetlbfs_size_type min_val_type;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hugetlbfs_inode_info {\n\tstruct inode vfs_inode;\n\tunsigned int seals;\n};\n\nstruct hugetlbfs_sb_info {\n\tlong int max_inodes;\n\tlong int free_inodes;\n\tspinlock_t stat_lock;\n\tstruct hstate *hstate;\n\tstruct hugepage_subpool *spool;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nunion hv_hypervisor_version_info {\n\tstruct {\n\t\tu32 build_number;\n\t\tu32 minor_version: 16;\n\t\tu32 major_version: 16;\n\t\tu32 service_pack;\n\t\tu32 service_number: 24;\n\t\tu32 service_branch: 8;\n\t};\n\tstruct {\n\t\tu32 eax;\n\t\tu32 ebx;\n\t\tu32 ecx;\n\t\tu32 edx;\n\t};\n};\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 config1;\n\t\t\tu64 last_tag;\n\t\t\tu64 dyn_constraint;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tu64 aux_config;\n\t\t\tunsigned int aux_paused;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tstruct arch_hw_breakpoint info;\n\t\t\tstruct rhlist_head bp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tunion {\n\t\tstruct {\n\t\t\tu64 last_period;\n\t\t\tlocal64_t period_left;\n\t\t};\n\t\tstruct {\n\t\t\tu64 saved_metric;\n\t\t\tu64 saved_slots;\n\t\t};\n\t};\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hwerr_info {\n\tatomic_t count;\n\ttime64_t timestamp;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n};\n\nstruct hwm_energy_info {\n\tu32 reg_val_prev;\n\tlong int accum_energy;\n};\n\nstruct hwm_fan_info {\n\tu32 reg_val_prev;\n\tu64 time_prev;\n};\n\nstruct hwm_drvdata {\n\tstruct i915_hwmon *hwmon;\n\tstruct intel_uncore *uncore;\n\tstruct device *hwmon_dev;\n\tstruct hwm_energy_info ei;\n\tstruct hwm_fan_info fi;\n\tchar name[12];\n\tint gt_n;\n\tbool reset_in_progress;\n\twait_queue_head_t waitq;\n};\n\nstruct hwm_reg {\n\ti915_reg_t gt_perf_status;\n\ti915_reg_t pkg_temp;\n\ti915_reg_t pkg_power_sku_unit;\n\ti915_reg_t pkg_power_sku;\n\ti915_reg_t pkg_rapl_limit;\n\ti915_reg_t energy_status_all;\n\ti915_reg_t energy_status_tile;\n\ti915_reg_t fan_speed;\n};\n\nstruct hwmon_channel_info {\n\tenum hwmon_sensor_types type;\n\tconst u32 *config;\n};\n\nstruct hwmon_ops;\n\nstruct hwmon_chip_info {\n\tconst struct hwmon_ops *ops;\n\tconst struct hwmon_channel_info * const *info;\n};\n\nstruct hwmon_device {\n\tconst char *name;\n\tconst char *label;\n\tstruct device dev;\n\tconst struct hwmon_chip_info *chip;\n\tstruct mutex lock;\n\tstruct list_head tzdata;\n\tstruct attribute_group group;\n\tconst struct attribute_group **groups;\n};\n\nstruct hwmon_device_attribute {\n\tstruct device_attribute dev_attr;\n\tconst struct hwmon_ops *ops;\n\tenum hwmon_sensor_types type;\n\tu32 attr;\n\tint index;\n\tchar name[32];\n};\n\nstruct hwmon_ops {\n\tumode_t visible;\n\tumode_t (*is_visible)(const void *, enum hwmon_sensor_types, u32, int);\n\tint (*read)(struct device *, enum hwmon_sensor_types, u32, int, long int *);\n\tint (*read_string)(struct device *, enum hwmon_sensor_types, u32, int, const char **);\n\tint (*write)(struct device *, enum hwmon_sensor_types, u32, int, long int);\n};\n\nstruct hwmon_thermal_data {\n\tstruct list_head node;\n\tstruct device *dev;\n\tint index;\n\tstruct thermal_zone_device *tzd;\n};\n\nstruct hwmon_type_attr_list {\n\tconst u32 *attrs;\n\tsize_t n_attrs;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct x86_hyper_init {\n\tvoid (*init_platform)(void);\n\tvoid (*guest_late_init)(void);\n\tbool (*x2apic_available)(void);\n\tbool (*msi_ext_dest_id)(void);\n\tvoid (*init_mem_mapping)(void);\n\tvoid (*init_after_bootmem)(void);\n};\n\nstruct x86_hyper_runtime {\n\tvoid (*pin_vcpu)(int);\n\tvoid (*sev_es_hcall_prepare)(struct ghcb *, struct pt_regs *);\n\tbool (*sev_es_hcall_finish)(struct ghcb *, struct pt_regs *);\n\tbool (*is_private_mmio)(u64);\n};\n\nstruct hypervisor_x86 {\n\tconst char *name;\n\tuint32_t (*detect)(void);\n\tenum x86_hypervisor_type type;\n\tstruct x86_hyper_init init;\n\tstruct x86_hyper_runtime runtime;\n\tbool ignore_nopv;\n};\n\nstruct i2c_acpi_handler_data {\n\tstruct acpi_connection_info info;\n\tstruct i2c_adapter *adapter;\n};\n\nstruct i2c_acpi_irq_context {\n\tint irq;\n\tbool wake_capable;\n};\n\nstruct i2c_board_info;\n\nstruct i2c_acpi_lookup {\n\tstruct i2c_board_info *info;\n\tacpi_handle adapter_handle;\n\tacpi_handle device_handle;\n\tacpi_handle search_handle;\n\tint n;\n\tint index;\n\tu32 speed;\n\tu32 min_speed;\n\tu32 force_speed;\n};\n\nstruct intel_dsi;\n\nstruct i2c_adapter_lookup {\n\tu16 target_addr;\n\tstruct intel_dsi *intel_dsi;\n\tacpi_handle dev_handle;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n};\n\nstruct i2c_algo_bit_data {\n\tvoid *data;\n\tvoid (*setsda)(void *, int);\n\tvoid (*setscl)(void *, int);\n\tint (*getsda)(void *);\n\tint (*getscl)(void *);\n\tint (*pre_xfer)(struct i2c_adapter *);\n\tvoid (*post_xfer)(struct i2c_adapter *);\n\tint udelay;\n\tint timeout;\n\tbool can_do_atomic;\n};\n\nstruct i2c_msg;\n\nunion i2c_smbus_data;\n\nstruct i2c_algorithm {\n\tunion {\n\t\tint (*xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tunion {\n\t\tint (*xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n};\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_gpio;\n};\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n\tvoid *devres_group_id;\n\tstruct dentry *debugfs;\n};\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *);\n\tvoid (*remove)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tu32 flags;\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nstruct i2c_smbus_alert {\n\tstruct work_struct alert;\n\tstruct i2c_client *ara;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct user_regs_struct32 {\n\t__u32 ebx;\n\t__u32 ecx;\n\t__u32 edx;\n\t__u32 esi;\n\t__u32 edi;\n\t__u32 ebp;\n\t__u32 eax;\n\tshort unsigned int ds;\n\tshort unsigned int __ds;\n\tshort unsigned int es;\n\tshort unsigned int __es;\n\tshort unsigned int fs;\n\tshort unsigned int __fs;\n\tshort unsigned int gs;\n\tshort unsigned int __gs;\n\t__u32 orig_eax;\n\t__u32 eip;\n\tshort unsigned int cs;\n\tshort unsigned int __cs;\n\t__u32 eflags;\n\t__u32 esp;\n\tshort unsigned int ss;\n\tshort unsigned int __ss;\n};\n\nstruct i386_elf_prstatus {\n\tstruct compat_elf_prstatus_common common;\n\tstruct user_regs_struct32 pr_reg;\n\tcompat_int_t pr_fpvalid;\n};\n\nstruct i801_priv {\n\tstruct i2c_adapter adapter;\n\tvoid *smba;\n\tunsigned char original_hstcfg;\n\tunsigned char original_hstcnt;\n\tunsigned char original_slvcmd;\n\tstruct pci_dev *pci_dev;\n\tunsigned int features;\n\tstruct completion done;\n\tu8 status;\n\tu8 cmd;\n\tbool is_read;\n\tint count;\n\tint len;\n\tu8 *data;\n\tstruct platform_device *tco_pdev;\n\tbool acpi_reserved;\n};\n\nstruct i8042_port {\n\tstruct serio *serio;\n\tint irq;\n\tbool exists;\n\tbool driver_bound;\n\tsigned char mux;\n};\n\nstruct i915_audio_component {\n\tstruct drm_audio_component base;\n\tint aud_sample_rate[9];\n};\n\nstruct i915_capture_list {\n\tstruct i915_vma_resource *vma_res;\n\tstruct i915_capture_list *next;\n};\n\nstruct i915_color_plane_view {\n\tu32 offset;\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned int mapping_stride;\n\tunsigned int scanout_stride;\n};\n\nstruct i915_context_engines_bond {\n\tstruct i915_user_extension base;\n\tstruct i915_engine_class_instance master;\n\t__u16 virtual_index;\n\t__u16 num_bonds;\n\t__u64 flags;\n\t__u64 mbz64[4];\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_engines_load_balance {\n\tstruct i915_user_extension base;\n\t__u16 engine_index;\n\t__u16 num_siblings;\n\t__u32 flags;\n\t__u64 mbz64;\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_engines_parallel_submit {\n\tstruct i915_user_extension base;\n\t__u16 engine_index;\n\t__u16 width;\n\t__u16 num_siblings;\n\t__u16 mbz16;\n\t__u64 flags;\n\t__u64 mbz64[3];\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_param_engines {\n\t__u64 extensions;\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_debugfs_files {\n\tconst char *name;\n\tconst struct file_operations *fops;\n};\n\nstruct i915_sched_node;\n\nstruct i915_dependency {\n\tstruct i915_sched_node *signaler;\n\tstruct i915_sched_node *waiter;\n\tstruct list_head signal_link;\n\tstruct list_head wait_link;\n\tstruct list_head dfs_link;\n\tlong unsigned int flags;\n};\n\nstruct i915_deps {\n\tstruct dma_fence *single;\n\tstruct dma_fence **fences;\n\tunsigned int num_deps;\n\tunsigned int fences_size;\n\tgfp_t gfp;\n};\n\nstruct i915_dpt {\n\tstruct i915_address_space vm;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_vma *vma;\n\tvoid *iomem;\n};\n\nstruct i915_drm_client {\n\tstruct kref kref;\n\tspinlock_t ctx_lock;\n\tstruct list_head ctx_list;\n\tspinlock_t objects_lock;\n\tstruct list_head objects_list;\n\tatomic64_t past_runtime[5];\n};\n\nstruct i915_error_regs {\n\ti915_reg_t emr;\n\ti915_reg_t eir;\n};\n\nstruct i915_gem_ww_ctx {\n\tstruct ww_acquire_ctx ctx;\n\tstruct list_head obj_list;\n\tstruct drm_i915_gem_object *contended;\n\tbool intr;\n};\n\nstruct reloc_cache {\n\tstruct drm_mm_node node;\n\tlong unsigned int vaddr;\n\tlong unsigned int page;\n\tunsigned int graphics_ver;\n\tbool use_64bit_reloc: 1;\n\tbool has_llc: 1;\n\tbool has_fence: 1;\n\tbool needs_unfenced: 1;\n};\n\nstruct intel_gt_buffer_pool_node;\n\nstruct i915_execbuffer {\n\tstruct drm_i915_private *i915;\n\tstruct drm_file *file;\n\tstruct drm_i915_gem_execbuffer2 *args;\n\tstruct drm_i915_gem_exec_object2 *exec;\n\tstruct eb_vma *vma;\n\tstruct intel_gt *gt;\n\tstruct intel_context *context;\n\tstruct i915_gem_context *gem_context;\n\tintel_wakeref_t wakeref;\n\tintel_wakeref_t wakeref_gt0;\n\tstruct i915_request *requests[9];\n\tstruct eb_vma *batches[9];\n\tstruct i915_vma *trampoline;\n\tstruct dma_fence *composite_fence;\n\tunsigned int buffer_count;\n\tunsigned int num_batches;\n\tstruct list_head unbound;\n\tstruct list_head relocs;\n\tstruct i915_gem_ww_ctx ww;\n\tstruct reloc_cache reloc_cache;\n\tu64 invalid_flags;\n\tu64 batch_len[9];\n\tu32 batch_start_offset;\n\tu32 batch_flags;\n\tstruct intel_gt_buffer_pool_node *batch_pool;\n\tint lut_size;\n\tstruct hlist_head *buckets;\n\tstruct eb_fence *fences;\n\tlong unsigned int num_fences;\n\tstruct i915_capture_list *capture_lists[9];\n};\n\nstruct i915_ext_attribute {\n\tstruct device_attribute attr;\n\tlong unsigned int val;\n};\n\nstruct i915_ggtt;\n\nstruct i915_fence_reg {\n\tstruct list_head link;\n\tstruct i915_ggtt *ggtt;\n\tstruct i915_vma *vma;\n\tatomic_t pin_count;\n\tstruct i915_active active;\n\tint id;\n\tbool dirty;\n\tu32 start;\n\tu32 size;\n\tu32 tiling;\n\tu32 stride;\n};\n\nstruct intel_frontbuffer {\n\tstruct intel_display *display;\n\tatomic_t bits;\n\tstruct work_struct flush_work;\n};\n\nstruct i915_frontbuffer {\n\tstruct intel_frontbuffer base;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_active write;\n\tstruct callback_head rcu;\n\tstruct kref ref;\n};\n\nstruct i915_gem_apply_to_region_ops;\n\nstruct i915_gem_apply_to_region {\n\tconst struct i915_gem_apply_to_region_ops *ops;\n\tstruct i915_gem_ww_ctx *ww;\n\tu32 interruptible: 1;\n};\n\nstruct i915_gem_apply_to_region_ops {\n\tint (*process_obj)(struct i915_gem_apply_to_region *, struct drm_i915_gem_object *);\n};\n\nstruct i915_sched_attr {\n\tint priority;\n};\n\nstruct i915_gem_engines;\n\nstruct i915_gem_context {\n\tstruct drm_i915_private *i915;\n\tstruct drm_i915_file_private *file_priv;\n\tstruct i915_gem_engines *engines;\n\tstruct mutex engines_mutex;\n\tstruct drm_syncobj *syncobj;\n\tstruct i915_address_space *vm;\n\tstruct pid *pid;\n\tstruct list_head link;\n\tstruct i915_drm_client *client;\n\tstruct list_head client_link;\n\tstruct kref ref;\n\tstruct work_struct release_work;\n\tstruct callback_head rcu;\n\tlong unsigned int user_flags;\n\tlong unsigned int flags;\n\tbool uses_protected_content;\n\tintel_wakeref_t pxp_wakeref;\n\tstruct mutex mutex;\n\tstruct i915_sched_attr sched;\n\tatomic_t guilty_count;\n\tatomic_t active_count;\n\tlong unsigned int hang_timestamp[2];\n\tu8 remap_slice;\n\tstruct xarray handles_vma;\n\tstruct mutex lut_mutex;\n\tchar name[24];\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head engines;\n\t} stale;\n};\n\nstruct i915_gem_context_coredump {\n\tchar comm[16];\n\tu64 total_runtime;\n\tu64 avg_runtime;\n\tpid_t pid;\n\tint active;\n\tint guilty;\n\tstruct i915_sched_attr sched_attr;\n\tu32 hwsp_seqno;\n};\n\nstruct i915_gem_context_param_context_image {\n\tstruct i915_engine_class_instance engine;\n\t__u32 flags;\n\t__u32 size;\n\t__u32 mbz;\n\t__u64 image;\n};\n\nstruct i915_gem_engines {\n\tunion {\n\t\tstruct list_head link;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct i915_sw_fence fence;\n\tstruct i915_gem_context *ctx;\n\tunsigned int num_engines;\n\tstruct intel_context *engines[0];\n};\n\nstruct i915_gem_engines_iter {\n\tunsigned int idx;\n\tconst struct i915_gem_engines *engines;\n};\n\nstruct i915_gem_proto_engine;\n\nstruct i915_gem_proto_context {\n\tstruct drm_i915_file_private *fpriv;\n\tstruct i915_address_space *vm;\n\tlong unsigned int user_flags;\n\tstruct i915_sched_attr sched;\n\tint num_user_engines;\n\tstruct i915_gem_proto_engine *user_engines;\n\tstruct intel_sseu legacy_rcs_sseu;\n\tbool single_timeline;\n\tbool uses_protected_content;\n\tintel_wakeref_t pxp_wakeref;\n};\n\nstruct i915_gem_proto_engine {\n\tenum i915_gem_engine_type type;\n\tstruct intel_engine_cs *engine;\n\tunsigned int num_siblings;\n\tunsigned int width;\n\tstruct intel_engine_cs **siblings;\n\tstruct intel_sseu sseu;\n};\n\nstruct i915_gem_ttm_pm_apply {\n\tstruct i915_gem_apply_to_region base;\n\tbool allow_gpu: 1;\n\tbool backup_pinned: 1;\n};\n\nstruct io_mapping {\n\tresource_size_t base;\n\tlong unsigned int size;\n\tpgprot_t prot;\n\tvoid *iomem;\n};\n\nstruct i915_ggtt {\n\tstruct i915_address_space vm;\n\tstruct io_mapping iomap;\n\tstruct resource gmadr;\n\tresource_size_t mappable_end;\n\tvoid *gsm;\n\tvoid (*invalidate)(struct i915_ggtt *);\n\tstruct i915_ppgtt *alias;\n\tbool do_idle_maps;\n\tint mtrr;\n\tu32 bit_6_swizzle_x;\n\tu32 bit_6_swizzle_y;\n\tu32 pin_bias;\n\tunsigned int num_fences;\n\tstruct i915_fence_reg *fence_regs;\n\tstruct list_head fence_list;\n\tstruct list_head userfault_list;\n\tstruct mutex error_mutex;\n\tstruct drm_mm_node error_capture;\n\tstruct drm_mm_node uc_fw;\n\tstruct list_head gt_list;\n};\n\nstruct intel_gt_definition;\n\nstruct intel_device_info {\n\tenum intel_platform platform;\n\tunsigned int dma_mask_size;\n\tconst struct intel_gt_definition *extra_gt_list;\n\tu8 gt;\n\tintel_engine_mask_t platform_engine_mask;\n\tu32 memory_regions;\n\tu8 is_mobile: 1;\n\tu8 require_force_probe: 1;\n\tu8 is_dgfx: 1;\n\tu8 has_64bit_reloc: 1;\n\tu8 has_64k_pages: 1;\n\tu8 gpu_reset_clobbers_display: 1;\n\tu8 has_reset_engine: 1;\n\tu8 has_3d_pipeline: 1;\n\tu8 has_flat_ccs: 1;\n\tu8 has_global_mocs: 1;\n\tu8 has_gmd_id: 1;\n\tu8 has_gt_uc: 1;\n\tu8 has_heci_pxp: 1;\n\tu8 has_heci_gscfi: 1;\n\tu8 has_guc_deprivilege: 1;\n\tu8 has_guc_tlb_invalidation: 1;\n\tu8 has_l3_ccs_read: 1;\n\tu8 has_l3_dpf: 1;\n\tu8 has_llc: 1;\n\tu8 has_logical_ring_contexts: 1;\n\tu8 has_logical_ring_elsq: 1;\n\tu8 has_media_ratio_mode: 1;\n\tu8 has_mslice_steering: 1;\n\tu8 has_oa_bpc_reporting: 1;\n\tu8 has_oa_slice_contrib_limits: 1;\n\tu8 has_oam: 1;\n\tu8 has_one_eu_per_fuse_bit: 1;\n\tu8 has_pxp: 1;\n\tu8 has_rc6: 1;\n\tu8 has_rc6p: 1;\n\tu8 has_rps: 1;\n\tu8 has_runtime_pm: 1;\n\tu8 has_snoop: 1;\n\tu8 has_coherent_ggtt: 1;\n\tu8 tuning_thread_rr_after_dep: 1;\n\tu8 unfenced_needs_alignment: 1;\n\tu8 hws_needs_physical: 1;\n\tconst struct intel_runtime_info __runtime;\n\tu32 cachelevel_to_pat[4];\n\tu32 max_pat_index;\n};\n\nstruct intel_gt_coredump;\n\nstruct intel_display_snapshot;\n\nstruct i915_gpu_coredump {\n\tstruct kref ref;\n\tktime_t time;\n\tktime_t boottime;\n\tktime_t uptime;\n\tlong unsigned int capture;\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt_coredump *gt;\n\tchar error_msg[128];\n\tbool simulated;\n\tbool wakelock;\n\tbool suspended;\n\tint iommu;\n\tu32 reset_count;\n\tu32 suspend_count;\n\tstruct intel_device_info device_info;\n\tstruct intel_runtime_info runtime_info;\n\tstruct intel_driver_caps driver_caps;\n\tstruct i915_params params;\n\tstruct scatterlist *sgl;\n\tstruct scatterlist *fit;\n\tstruct intel_display_snapshot *display_snapshot;\n};\n\nstruct i915_gsc_proxy_component_ops;\n\nstruct i915_gsc_proxy_component {\n\tstruct device *mei_dev;\n\tconst struct i915_gsc_proxy_component_ops *ops;\n};\n\nstruct i915_gsc_proxy_component_ops {\n\tstruct module *owner;\n\tint (*send)(struct device *, const void *, size_t);\n\tint (*recv)(struct device *, void *, size_t);\n};\n\nstruct intel_partial_info {\n\tu64 offset;\n\tunsigned int size;\n} __attribute__((packed));\n\nstruct intel_remapped_plane_info {\n\tu32 offset: 31;\n\tu32 linear: 1;\n\tunion {\n\t\tstruct {\n\t\t\tu16 width;\n\t\t\tu16 height;\n\t\t\tu16 src_stride;\n\t\t\tu16 dst_stride;\n\t\t};\n\t\tu32 size;\n\t};\n};\n\nstruct intel_rotation_info {\n\tstruct intel_remapped_plane_info plane[2];\n};\n\nstruct intel_remapped_info {\n\tstruct intel_remapped_plane_info plane[4];\n\tu32 plane_alignment;\n};\n\nstruct i915_gtt_view {\n\tenum i915_gtt_view_type type;\n\tunion {\n\t\tstruct intel_partial_info partial;\n\t\tstruct intel_rotation_info rotated;\n\t\tstruct intel_remapped_info remapped;\n\t};\n};\n\nstruct i915_hdcp_ops;\n\nstruct i915_hdcp_arbiter {\n\tstruct device *hdcp_dev;\n\tconst struct i915_hdcp_ops *ops;\n\tstruct mutex mutex;\n};\n\nstruct i915_hdcp_ops {\n\tstruct module *owner;\n\tint (*initiate_hdcp2_session)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_init *);\n\tint (*verify_receiver_cert_prepare_km)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_cert *, bool *, struct hdcp2_ake_no_stored_km *, size_t *);\n\tint (*verify_hprime)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_hprime *);\n\tint (*store_pairing_info)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_pairing_info *);\n\tint (*initiate_locality_check)(struct device *, struct hdcp_port_data *, struct hdcp2_lc_init *);\n\tint (*verify_lprime)(struct device *, struct hdcp_port_data *, struct hdcp2_lc_send_lprime *);\n\tint (*get_session_key)(struct device *, struct hdcp_port_data *, struct hdcp2_ske_send_eks *);\n\tint (*repeater_check_flow_prepare_ack)(struct device *, struct hdcp_port_data *, struct hdcp2_rep_send_receiverid_list *, struct hdcp2_rep_send_ack *);\n\tint (*verify_mprime)(struct device *, struct hdcp_port_data *, struct hdcp2_rep_stream_ready *);\n\tint (*enable_hdcp_authentication)(struct device *, struct hdcp_port_data *);\n\tint (*close_hdcp_session)(struct device *, struct hdcp_port_data *);\n};\n\nstruct i915_hwmon {\n\tstruct hwm_drvdata ddat;\n\tstruct hwm_drvdata ddat_gt[2];\n\tstruct mutex hwmon_lock;\n\tstruct hwm_reg rg;\n\tint scl_shift_power;\n\tint scl_shift_energy;\n\tint scl_shift_time;\n};\n\nstruct i915_irq_regs {\n\ti915_reg_t imr;\n\ti915_reg_t ier;\n\ti915_reg_t iir;\n};\n\nstruct i915_lut_handle {\n\tstruct list_head obj_link;\n\tstruct i915_gem_context *ctx;\n\tu32 handle;\n};\n\nstruct i915_mmap_offset {\n\tstruct drm_vma_offset_node vma_node;\n\tstruct drm_i915_gem_object *obj;\n\tenum i915_mmap_type mmap_type;\n\tstruct rb_node offset;\n};\n\nstruct i915_mmio_range {\n\tu32 start;\n\tu32 end;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct i915_oa_reg;\n\nstruct i915_oa_config {\n\tstruct i915_perf *perf;\n\tchar uuid[37];\n\tint id;\n\tconst struct i915_oa_reg *mux_regs;\n\tu32 mux_regs_len;\n\tconst struct i915_oa_reg *b_counter_regs;\n\tu32 b_counter_regs_len;\n\tconst struct i915_oa_reg *flex_regs;\n\tu32 flex_regs_len;\n\tstruct attribute_group sysfs_metric;\n\tstruct attribute *attrs[2];\n\tstruct kobj_attribute sysfs_metric_id;\n\tstruct kref ref;\n\tstruct callback_head rcu;\n};\n\nstruct i915_oa_config_bo {\n\tstruct llist_node node;\n\tstruct i915_oa_config *oa_config;\n\tstruct i915_vma *vma;\n};\n\nstruct i915_oa_format {\n\tu32 format;\n\tint size;\n\tint type;\n\tenum report_header header;\n};\n\nstruct i915_oa_reg {\n\ti915_reg_t addr;\n\tu32 value;\n};\n\nstruct i915_page_table {\n\tstruct drm_i915_gem_object *base;\n\tunion {\n\t\tatomic_t used;\n\t\tstruct i915_page_table *stash;\n\t};\n\tbool is_compact;\n};\n\nstruct i915_page_directory {\n\tstruct i915_page_table pt;\n\tspinlock_t lock;\n\tvoid **entry;\n};\n\nstruct i915_perf_regs {\n\tu32 base;\n\ti915_reg_t oa_head_ptr;\n\ti915_reg_t oa_tail_ptr;\n\ti915_reg_t oa_buffer;\n\ti915_reg_t oa_ctx_ctrl;\n\ti915_reg_t oa_ctrl;\n\ti915_reg_t oa_debug;\n\ti915_reg_t oa_status;\n\tu32 oa_ctrl_counter_format_shift;\n};\n\nstruct i915_perf_group {\n\tstruct i915_perf_stream *exclusive_stream;\n\tu32 num_engines;\n\tstruct i915_perf_regs regs;\n\tenum oa_type type;\n};\n\nstruct i915_perf_gt {\n\tstruct mutex lock;\n\tstruct intel_sseu sseu;\n\tu32 num_perf_groups;\n\tstruct i915_perf_group *group;\n};\n\nstruct i915_perf_stream_ops;\n\nstruct i915_perf_stream {\n\tstruct i915_perf *perf;\n\tstruct intel_uncore *uncore;\n\tstruct intel_engine_cs *engine;\n\tstruct mutex lock;\n\tu32 sample_flags;\n\tint sample_size;\n\tstruct i915_gem_context *ctx;\n\tbool enabled;\n\tbool hold_preemption;\n\tconst struct i915_perf_stream_ops *ops;\n\tstruct i915_oa_config *oa_config;\n\tstruct llist_head oa_config_bos;\n\tstruct intel_context *pinned_ctx;\n\tu32 specific_ctx_id;\n\tu32 specific_ctx_id_mask;\n\tstruct hrtimer poll_check_timer;\n\twait_queue_head_t poll_wq;\n\tbool pollin;\n\tbool periodic;\n\tint period_exponent;\n\tstruct {\n\t\tconst struct i915_oa_format *format;\n\t\tstruct i915_vma *vma;\n\t\tu8 *vaddr;\n\t\tu32 last_ctx_id;\n\t\tspinlock_t ptr_lock;\n\t\tu32 head;\n\t\tu32 tail;\n\t} oa_buffer;\n\tstruct i915_vma *noa_wait;\n\tu64 poll_oa_period;\n};\n\nstruct i915_perf_stream_ops {\n\tvoid (*enable)(struct i915_perf_stream *);\n\tvoid (*disable)(struct i915_perf_stream *);\n\tvoid (*poll_wait)(struct i915_perf_stream *, struct file *, poll_table *);\n\tint (*wait_unlocked)(struct i915_perf_stream *);\n\tint (*read)(struct i915_perf_stream *, char *, size_t, size_t *);\n\tvoid (*destroy)(struct i915_perf_stream *);\n};\n\nstruct i915_power_domain_list {\n\tconst enum intel_display_power_domain *list;\n\tu8 count;\n};\n\nstruct intel_power_domain_mask {\n\tlong unsigned int bits[2];\n};\n\nstruct i915_power_well;\n\nstruct i915_power_domains {\n\tbool initializing;\n\tbool display_core_suspended;\n\tint power_well_count;\n\tu32 dc_state;\n\tu32 target_dc_state;\n\tu32 allowed_dc_mask;\n\tstruct ref_tracker *init_wakeref;\n\tstruct ref_tracker *disable_wakeref;\n\tstruct mutex lock;\n\tint domain_use_count[76];\n\tstruct delayed_work async_put_work;\n\tstruct ref_tracker *async_put_wakeref;\n\tstruct intel_power_domain_mask async_put_domains[2];\n\tint async_put_next_delay;\n\tstruct i915_power_well *power_wells;\n};\n\nstruct i915_power_well_desc;\n\nstruct i915_power_well {\n\tconst struct i915_power_well_desc *desc;\n\tstruct intel_power_domain_mask domains;\n\tint count;\n\tbool hw_enabled;\n\tu8 instance_idx;\n};\n\nstruct i915_power_well_ops;\n\nstruct i915_power_well_instance_list;\n\nstruct i915_power_well_desc {\n\tconst struct i915_power_well_ops *ops;\n\tconst struct i915_power_well_instance_list *instances;\n\tu16 irq_pipe_mask: 4;\n\tu16 always_on: 1;\n\tu16 fixed_enable_delay: 1;\n\tu16 has_vga: 1;\n\tu16 has_fuses: 1;\n\tu16 is_tc_tbt: 1;\n\tu16 enable_timeout;\n};\n\nstruct i915_power_well_desc_list {\n\tconst struct i915_power_well_desc *list;\n\tu8 count;\n};\n\nstruct i915_power_well_instance {\n\tconst char *name;\n\tconst struct i915_power_domain_list *domain_list;\n\tenum i915_power_well_id id;\n\tunion {\n\t\tstruct {\n\t\t\tu8 idx;\n\t\t} vlv;\n\t\tstruct {\n\t\t\tenum dpio_phy phy;\n\t\t} bxt;\n\t\tstruct {\n\t\t\tu8 idx;\n\t\t} hsw;\n\t\tstruct {\n\t\t\tu8 aux_ch;\n\t\t} xelpdp;\n\t};\n};\n\nstruct i915_power_well_instance_list {\n\tconst struct i915_power_well_instance *list;\n\tu8 count;\n};\n\nstruct i915_power_well_regs;\n\nstruct i915_power_well_ops {\n\tconst struct i915_power_well_regs *regs;\n\tvoid (*sync_hw)(struct intel_display *, struct i915_power_well *);\n\tvoid (*enable)(struct intel_display *, struct i915_power_well *);\n\tvoid (*disable)(struct intel_display *, struct i915_power_well *);\n\tbool (*is_enabled)(struct intel_display *, struct i915_power_well *);\n};\n\nstruct i915_power_well_regs {\n\ti915_reg_t bios;\n\ti915_reg_t driver;\n\ti915_reg_t kvmr;\n\ti915_reg_t debug;\n};\n\nstruct i915_priolist {\n\tstruct list_head requests;\n\tstruct rb_node node;\n\tint priority;\n};\n\nstruct i915_pxp_component_ops;\n\nstruct i915_pxp_component {\n\tstruct device *tee_dev;\n\tconst struct i915_pxp_component_ops *ops;\n\tstruct mutex mutex;\n};\n\nstruct i915_pxp_component_ops {\n\tstruct module *owner;\n\tint (*send)(struct device *, const void *, size_t, long unsigned int);\n\tint (*recv)(struct device *, void *, size_t, long unsigned int);\n\tssize_t (*gsc_command)(struct device *, u8, u32, struct scatterlist *, size_t, struct scatterlist *);\n};\n\nstruct i915_refct_sgt_ops;\n\nstruct i915_refct_sgt {\n\tstruct kref kref;\n\tstruct sg_table table;\n\tsize_t size;\n\tconst struct i915_refct_sgt_ops *ops;\n};\n\nstruct i915_refct_sgt_ops {\n\tvoid (*release)(struct kref *);\n};\n\nstruct i915_request_duration_cb {\n\tstruct dma_fence_cb cb;\n\tktime_t emitted;\n};\n\nstruct i915_sched_node {\n\tstruct list_head signalers_list;\n\tstruct list_head waiters_list;\n\tstruct list_head link;\n\tstruct i915_sched_attr attr;\n\tunsigned int flags;\n\tintel_engine_mask_t semaphores;\n};\n\nstruct i915_request_watchdog {\n\tstruct llist_node link;\n\tstruct hrtimer timer;\n};\n\nstruct i915_request {\n\tstruct dma_fence fence;\n\tspinlock_t lock;\n\tstruct drm_i915_private *i915;\n\tstruct intel_engine_cs *engine;\n\tstruct intel_context *context;\n\tstruct intel_ring *ring;\n\tstruct intel_timeline *timeline;\n\tstruct list_head signal_link;\n\tstruct llist_node signal_node;\n\tlong unsigned int rcustate;\n\tstruct pin_cookie cookie;\n\tstruct i915_sw_fence submit;\n\tunion {\n\t\twait_queue_entry_t submitq;\n\t\tstruct i915_sw_dma_fence_cb dmaq;\n\t\tstruct i915_request_duration_cb duration;\n\t};\n\tstruct llist_head execute_cb;\n\tstruct i915_sw_fence semaphore;\n\tstruct irq_work submit_work;\n\tstruct i915_sched_node sched;\n\tstruct i915_dependency dep;\n\tintel_engine_mask_t execution_mask;\n\tconst u32 *hwsp_seqno;\n\tu32 head;\n\tu32 infix;\n\tu32 postfix;\n\tu32 tail;\n\tu32 wa_tail;\n\tu32 reserved_space;\n\tstruct i915_vma_resource *batch_res;\n\tstruct i915_capture_list *capture_list;\n\tlong unsigned int emitted_jiffies;\n\tstruct list_head link;\n\tstruct i915_request_watchdog watchdog;\n\tstruct list_head guc_fence_link;\n\tu8 guc_prio;\n\twait_queue_entry_t hucq;\n};\n\nstruct i915_request_coredump {\n\tlong unsigned int flags;\n\tpid_t pid;\n\tu32 context;\n\tu32 seqno;\n\tu32 head;\n\tu32 tail;\n\tstruct i915_sched_attr sched_attr;\n};\n\nstruct i915_sched_engine {\n\tstruct kref ref;\n\tspinlock_t lock;\n\tstruct list_head requests;\n\tstruct list_head hold;\n\tstruct tasklet_struct tasklet;\n\tstruct i915_priolist default_priolist;\n\tint queue_priority_hint;\n\tstruct rb_root_cached queue;\n\tbool no_priolist;\n\tvoid *private_data;\n\tvoid (*destroy)(struct kref *);\n\tbool (*disabled)(struct i915_sched_engine *);\n\tvoid (*kick_backend)(const struct i915_request *, int);\n\tvoid (*bump_inflight_request_prio)(struct i915_request *, int);\n\tvoid (*retire_inflight_request_prio)(struct i915_request *);\n\tvoid (*schedule)(struct i915_request *, const struct i915_sched_attr *);\n};\n\nstruct i915_str_attribute {\n\tstruct device_attribute attr;\n\tconst char *str;\n};\n\nstruct i915_sw_dma_fence_cb_timer {\n\tstruct i915_sw_dma_fence_cb base;\n\tstruct dma_fence *dma;\n\tstruct timer_list timer;\n\tstruct irq_work work;\n\tstruct callback_head rcu;\n};\n\nstruct i915_syncmap {\n\tu64 prefix;\n\tunsigned int height;\n\tunsigned int bitmap;\n\tstruct i915_syncmap *parent;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_seqno;\n\t\t\tu32 seqno[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_child;\n\t\t\tstruct i915_syncmap *child[0];\n\t\t};\n\t};\n};\n\nstruct i915_ttm_buddy_manager {\n\tstruct ttm_resource_manager manager;\n\tstruct drm_buddy mm;\n\tstruct list_head reserved;\n\tstruct mutex lock;\n\tlong unsigned int visible_size;\n\tlong unsigned int visible_avail;\n\tlong unsigned int visible_reserved;\n\tu64 default_page_size;\n};\n\nstruct ttm_bus_placement {\n\tvoid *addr;\n\tphys_addr_t offset;\n\tbool is_iomem;\n\tenum ttm_caching caching;\n};\n\nstruct dmem_cgroup_pool_state;\n\nstruct ttm_lru_item {\n\tstruct list_head link;\n\tenum ttm_lru_item_type type;\n};\n\nstruct ttm_resource {\n\tlong unsigned int start;\n\tsize_t size;\n\tuint32_t mem_type;\n\tuint32_t placement;\n\tstruct ttm_bus_placement bus;\n\tstruct ttm_buffer_object *bo;\n\tstruct dmem_cgroup_pool_state *css;\n\tstruct ttm_lru_item lru;\n};\n\nstruct i915_ttm_buddy_resource {\n\tstruct ttm_resource base;\n\tstruct list_head blocks;\n\tlong unsigned int flags;\n\tlong unsigned int used_visible_size;\n\tstruct drm_buddy *mm;\n};\n\nstruct ttm_kmap_iter_ops;\n\nstruct ttm_kmap_iter {\n\tconst struct ttm_kmap_iter_ops *ops;\n};\n\nstruct ttm_kmap_iter_tt {\n\tstruct ttm_kmap_iter base;\n\tstruct ttm_tt *tt;\n\tpgprot_t prot;\n};\n\nstruct ttm_kmap_iter_iomap {\n\tstruct ttm_kmap_iter base;\n\tstruct io_mapping *iomap;\n\tstruct sg_table *st;\n\tresource_size_t start;\n\tstruct {\n\t\tstruct scatterlist *sg;\n\t\tlong unsigned int i;\n\t\tlong unsigned int end;\n\t\tlong unsigned int offs;\n\t} cache;\n};\n\nstruct i915_ttm_memcpy_arg {\n\tunion {\n\t\tstruct ttm_kmap_iter_tt tt;\n\t\tstruct ttm_kmap_iter_iomap io;\n\t} _dst_iter;\n\tunion {\n\t\tstruct ttm_kmap_iter_tt tt;\n\t\tstruct ttm_kmap_iter_iomap io;\n\t} _src_iter;\n\tstruct ttm_kmap_iter *dst_iter;\n\tstruct ttm_kmap_iter *src_iter;\n\tlong unsigned int num_pages;\n\tbool clear;\n\tstruct i915_refct_sgt *src_rsgt;\n\tstruct i915_refct_sgt *dst_rsgt;\n};\n\nstruct i915_ttm_memcpy_work {\n\tstruct dma_fence fence;\n\tstruct work_struct work;\n\tspinlock_t lock;\n\tstruct irq_work irq_work;\n\tstruct dma_fence_cb cb;\n\tstruct i915_ttm_memcpy_arg arg;\n\tstruct drm_i915_private *i915;\n\tstruct drm_i915_gem_object *obj;\n\tbool memcpy_allowed;\n};\n\nstruct ttm_pool_tt_restore;\n\nstruct ttm_tt {\n\tstruct page **pages;\n\tuint32_t page_flags;\n\tuint32_t num_pages;\n\tstruct sg_table *sg;\n\tdma_addr_t *dma_address;\n\tstruct file *swap_storage;\n\tstruct file *backup;\n\tenum ttm_caching caching;\n\tstruct ttm_pool_tt_restore *restore;\n};\n\nstruct i915_ttm_tt {\n\tstruct ttm_tt ttm;\n\tstruct device *dev;\n\tstruct i915_refct_sgt cached_rsgt;\n\tbool is_shmem;\n\tstruct file *filp;\n};\n\nstruct i915_vm_pt_stash {\n\tstruct i915_page_table *pt[2];\n\tint pt_sz;\n};\n\nstruct i915_vma {\n\tstruct drm_mm_node node;\n\tstruct i915_address_space *vm;\n\tconst struct i915_vma_ops *ops;\n\tstruct drm_i915_gem_object *obj;\n\tstruct sg_table *pages;\n\tvoid *iomap;\n\tvoid *private;\n\tstruct i915_fence_reg *fence;\n\tu64 size;\n\tstruct i915_page_sizes page_sizes;\n\tstruct i915_mmap_offset *mmo;\n\tu32 guard;\n\tu32 fence_size;\n\tu32 fence_alignment;\n\tu32 display_alignment;\n\tatomic_t open_count;\n\tatomic_t flags;\n\tstruct i915_active active;\n\tatomic_t pages_count;\n\tbool vm_ddestroy;\n\tstruct i915_gtt_view gtt_view;\n\tstruct list_head vm_link;\n\tstruct list_head obj_link;\n\tstruct rb_node obj_node;\n\tstruct list_head evict_link;\n\tstruct list_head closed_link;\n\tstruct i915_vma_resource *resource;\n};\n\nstruct i915_vma_bindinfo {\n\tstruct sg_table *pages;\n\tstruct i915_page_sizes page_sizes;\n\tstruct i915_refct_sgt *pages_rsgt;\n\tbool readonly: 1;\n\tbool lmem: 1;\n};\n\nstruct internal_state;\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\nstruct i915_vma_compress {\n\tstruct folio_batch pool;\n\tstruct z_stream_s zstream;\n\tvoid *tmp;\n};\n\nstruct i915_vma_coredump {\n\tstruct i915_vma_coredump *next;\n\tchar name[20];\n\tu64 gtt_offset;\n\tu64 gtt_size;\n\tu32 gtt_page_sizes;\n\tint unused;\n\tstruct list_head page_list;\n};\n\nstruct i915_vma_resource {\n\tstruct dma_fence unbind_fence;\n\tspinlock_t lock;\n\trefcount_t hold_count;\n\tstruct work_struct work;\n\tstruct i915_sw_fence chain;\n\tstruct rb_node rb;\n\tu64 __subtree_last;\n\tstruct i915_address_space *vm;\n\tintel_wakeref_t wakeref;\n\tstruct i915_vma_bindinfo bi;\n\tstruct intel_memory_region *mr;\n\tconst struct i915_vma_ops *ops;\n\tvoid *private;\n\tu64 start;\n\tu64 node_size;\n\tu64 vma_size;\n\tu32 guard;\n\tu32 page_sizes_gtt;\n\tu32 bound_flags;\n\tbool allocated: 1;\n\tbool immediate_unbind: 1;\n\tbool needs_wakeref: 1;\n\tbool skip_pte_rewrite: 1;\n\tu32 *tlb;\n};\n\nstruct i915_vma_work {\n\tstruct dma_fence_work base;\n\tstruct i915_address_space *vm;\n\tstruct i915_vm_pt_stash stash;\n\tstruct i915_vma_resource *vma_res;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_sw_dma_fence_cb cb;\n\tunsigned int pat_index;\n\tunsigned int flags;\n};\n\nstruct i915_wa {\n\tunion {\n\t\ti915_reg_t reg;\n\t\ti915_mcr_reg_t mcr_reg;\n\t};\n\tu32 clr;\n\tu32 set;\n\tu32 read;\n\tu32 masked_reg: 1;\n\tu32 is_mcr: 1;\n};\n\nstruct i9xx_dpll_hw_state {\n\tu32 dpll;\n\tu32 dpll_md;\n\tu32 fp0;\n\tu32 fp1;\n};\n\nstruct ia_constants {\n\tunsigned int min_gpu_freq;\n\tunsigned int max_gpu_freq;\n\tunsigned int min_ring_freq;\n\tunsigned int max_ia_freq;\n};\n\nstruct iapp_layer2_update {\n\tu8 da[6];\n\tu8 sa[6];\n\t__be16 len;\n\tu8 dsap;\n\tu8 ssap;\n\tu8 control;\n\tu8 xid_info[3];\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n};\n\nunion ibs_fetch_ctl {\n\t__u64 val;\n\tstruct {\n\t\t__u64 fetch_maxcnt: 16;\n\t\t__u64 fetch_cnt: 16;\n\t\t__u64 fetch_lat: 16;\n\t\t__u64 fetch_en: 1;\n\t\t__u64 fetch_val: 1;\n\t\t__u64 fetch_comp: 1;\n\t\t__u64 ic_miss: 1;\n\t\t__u64 phy_addr_valid: 1;\n\t\t__u64 l1tlb_pgsz: 2;\n\t\t__u64 l1tlb_miss: 1;\n\t\t__u64 l2tlb_miss: 1;\n\t\t__u64 rand_en: 1;\n\t\t__u64 fetch_l2_miss: 1;\n\t\t__u64 l3_miss_only: 1;\n\t\t__u64 fetch_oc_miss: 1;\n\t\t__u64 fetch_l3_miss: 1;\n\t\t__u64 reserved: 2;\n\t};\n};\n\nunion ibs_op_ctl {\n\t__u64 val;\n\tstruct {\n\t\t__u64 opmaxcnt: 16;\n\t\t__u64 l3_miss_only: 1;\n\t\t__u64 op_en: 1;\n\t\t__u64 op_val: 1;\n\t\t__u64 cnt_ctl: 1;\n\t\t__u64 opmaxcnt_ext: 7;\n\t\t__u64 reserved0: 5;\n\t\t__u64 opcurcnt: 27;\n\t\t__u64 ldlat_thrsh: 4;\n\t\t__u64 ldlat_en: 1;\n\t};\n};\n\nunion ibs_op_data {\n\t__u64 val;\n\tstruct {\n\t\t__u64 comp_to_ret_ctr: 16;\n\t\t__u64 tag_to_ret_ctr: 16;\n\t\t__u64 reserved1: 2;\n\t\t__u64 op_return: 1;\n\t\t__u64 op_brn_taken: 1;\n\t\t__u64 op_brn_misp: 1;\n\t\t__u64 op_brn_ret: 1;\n\t\t__u64 op_rip_invalid: 1;\n\t\t__u64 op_brn_fuse: 1;\n\t\t__u64 op_microcode: 1;\n\t\t__u64 reserved2: 23;\n\t};\n};\n\nunion ibs_op_data2 {\n\t__u64 val;\n\tstruct {\n\t\t__u64 data_src_lo: 3;\n\t\t__u64 reserved0: 1;\n\t\t__u64 rmt_node: 1;\n\t\t__u64 cache_hit_st: 1;\n\t\t__u64 data_src_hi: 2;\n\t\t__u64 reserved1: 56;\n\t};\n};\n\nunion ibs_op_data3 {\n\t__u64 val;\n\tstruct {\n\t\t__u64 ld_op: 1;\n\t\t__u64 st_op: 1;\n\t\t__u64 dc_l1tlb_miss: 1;\n\t\t__u64 dc_l2tlb_miss: 1;\n\t\t__u64 dc_l1tlb_hit_2m: 1;\n\t\t__u64 dc_l1tlb_hit_1g: 1;\n\t\t__u64 dc_l2tlb_hit_2m: 1;\n\t\t__u64 dc_miss: 1;\n\t\t__u64 dc_mis_acc: 1;\n\t\t__u64 reserved: 4;\n\t\t__u64 dc_wc_mem_acc: 1;\n\t\t__u64 dc_uc_mem_acc: 1;\n\t\t__u64 dc_locked_op: 1;\n\t\t__u64 dc_miss_no_mab_alloc: 1;\n\t\t__u64 dc_lin_addr_valid: 1;\n\t\t__u64 dc_phy_addr_valid: 1;\n\t\t__u64 dc_l2_tlb_hit_1g: 1;\n\t\t__u64 l2_miss: 1;\n\t\t__u64 sw_pf: 1;\n\t\t__u64 op_mem_width: 4;\n\t\t__u64 op_dc_miss_open_mem_reqs: 6;\n\t\t__u64 dc_miss_lat: 16;\n\t\t__u64 tlb_refill_lat: 16;\n\t};\n};\n\nstruct ibx_audio_regs {\n\ti915_reg_t hdmiw_hdmiedid;\n\ti915_reg_t aud_config;\n\ti915_reg_t aud_cntl_st;\n\ti915_reg_t aud_cntrl_st2;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct ich8_pr {\n\tu32 base: 13;\n\tu32 reserved1: 2;\n\tu32 rpe: 1;\n\tu32 limit: 13;\n\tu32 reserved2: 2;\n\tu32 wpe: 1;\n};\n\nunion ich8_flash_protected_range {\n\tstruct ich8_pr range;\n\tu32 regval;\n};\n\nstruct ich8_hsflctl {\n\tu16 flcgo: 1;\n\tu16 flcycle: 2;\n\tu16 reserved: 5;\n\tu16 fldbcount: 2;\n\tu16 flockdn: 6;\n};\n\nstruct ich8_hsfsts {\n\tu16 flcdone: 1;\n\tu16 flcerr: 1;\n\tu16 dael: 1;\n\tu16 berasesz: 2;\n\tu16 flcinprog: 1;\n\tu16 reserved1: 2;\n\tu16 reserved2: 6;\n\tu16 fldesvalid: 1;\n\tu16 flockdn: 1;\n};\n\nunion ich8_hws_flash_ctrl {\n\tstruct ich8_hsflctl hsf_ctrl;\n\tu16 regval;\n};\n\nunion ich8_hws_flash_status {\n\tstruct ich8_hsfsts hsf_status;\n\tu16 regval;\n};\n\nstruct ich_laptop {\n\tu16 device;\n\tu16 subvendor;\n\tu16 subdevice;\n};\n\nstruct skl_wrpll_params {\n\tu32 dco_fraction;\n\tu32 dco_integer;\n\tu32 qdiv_ratio;\n\tu32 qdiv_mode;\n\tu32 kdiv;\n\tu32 pdiv;\n\tu32 central_freq;\n};\n\nstruct icl_combo_pll_params {\n\tint clock;\n\tstruct skl_wrpll_params wrpll;\n};\n\nstruct icl_ddi_buf_trans {\n\tu8 dw2_swing_sel;\n\tu8 dw7_n_scalar;\n\tu8 dw4_cursor_coeff;\n\tu8 dw4_post_cursor_2;\n\tu8 dw4_post_cursor_1;\n};\n\nstruct icl_dpll_hw_state {\n\tu32 cfgcr0;\n\tu32 cfgcr1;\n\tu32 div0;\n\tu32 mg_refclkin_ctl;\n\tu32 mg_clktop2_coreclkctl1;\n\tu32 mg_clktop2_hsclkctl;\n\tu32 mg_pll_div0;\n\tu32 mg_pll_div1;\n\tu32 mg_pll_lf;\n\tu32 mg_pll_frac_lock;\n\tu32 mg_pll_ssc;\n\tu32 mg_pll_bias;\n\tu32 mg_pll_tdc_coldst_bias;\n\tu32 mg_pll_bias_mask;\n\tu32 mg_pll_tdc_coldst_bias_mask;\n};\n\nstruct icl_mg_phy_ddi_buf_trans {\n\tu8 cri_txdeemph_override_11_6;\n\tu8 cri_txdeemph_override_5_0;\n\tu8 cri_txdeemph_override_17_12;\n};\n\nstruct skl_dpll_hw_state {\n\tu32 ctrl1;\n\tu32 cfgcr1;\n\tu32 cfgcr2;\n};\n\nstruct intel_mpllb_state {\n\tu32 clock;\n\tu32 ref_control;\n\tu32 mpllb_cp;\n\tu32 mpllb_div;\n\tu32 mpllb_div2;\n\tu32 mpllb_fracn1;\n\tu32 mpllb_fracn2;\n\tu32 mpllb_sscen;\n\tu32 mpllb_sscstep;\n};\n\nstruct intel_c10pll_state {\n\tu32 clock;\n\tu8 tx;\n\tu8 cmn;\n\tu8 pll[20];\n};\n\nstruct intel_c20pll_vdr_state {\n\tu8 custom_width;\n\tu8 serdes_rate;\n\tu8 hdmi_rate;\n};\n\nstruct intel_c20pll_state {\n\tu32 clock;\n\tu16 tx[3];\n\tu16 cmn[4];\n\tunion {\n\t\tu16 mplla[10];\n\t\tu16 mpllb[11];\n\t};\n\tstruct intel_c20pll_vdr_state vdr;\n};\n\nstruct intel_cx0pll_state {\n\tunion {\n\t\tstruct intel_c10pll_state c10;\n\t\tstruct intel_c20pll_state c20;\n\t};\n\tint lane_count;\n\tbool ssc_enabled;\n\tbool use_c10;\n\tbool tbt_mode;\n};\n\nstruct intel_lt_phy_pll_state {\n\tu32 clock;\n\tu8 addr_msb[13];\n\tu8 addr_lsb[13];\n\tu8 data[52];\n\tu8 config[3];\n\tbool ssc_enabled;\n\tbool tbt_mode;\n};\n\nstruct intel_dpll_hw_state {\n\tunion {\n\t\tstruct i9xx_dpll_hw_state i9xx;\n\t\tstruct hsw_dpll_hw_state hsw;\n\t\tstruct skl_dpll_hw_state skl;\n\t\tstruct bxt_dpll_hw_state bxt;\n\t\tstruct icl_dpll_hw_state icl;\n\t\tstruct intel_mpllb_state mpllb;\n\t\tstruct intel_cx0pll_state cx0pll;\n\t\tstruct intel_lt_phy_pll_state ltpll;\n\t};\n};\n\nstruct intel_dpll;\n\nstruct icl_port_dpll {\n\tstruct intel_dpll *pll;\n\tstruct intel_dpll_hw_state hw_state;\n};\n\nstruct icl_procmon {\n\tconst char *name;\n\tu32 dw1;\n\tu32 dw9;\n\tu32 dw10;\n};\n\nstruct iclkip_params {\n\tu32 iclk_virtual_root_freq;\n\tu32 iclk_pi_range;\n\tu32 divsel;\n\tu32 phaseinc;\n\tu32 auxdiv;\n\tu32 phasedir;\n\tu32 desired_divisor;\n};\n\nstruct icmp6_err {\n\tint err;\n\tint fatal;\n};\n\nstruct icmp6_ext_iio_addr6_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\tstruct in6_addr addr6;\n};\n\nstruct icmp6_filter {\n\t__u32 data[8];\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 reserved1: 4;\n\t__u8 version: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[7];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6_msg {\n\tstruct sk_buff *skb;\n\tint offset;\n\tuint8_t type;\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct id_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tunion {\n\t\t__u32 ruid;\n\t\t__u32 rgid;\n\t} r;\n\tunion {\n\t\t__u32 euid;\n\t\t__u32 egid;\n\t} e;\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[16];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n};\n\nstruct idmap_legacy_upcalldata;\n\nstruct idmap {\n\tstruct rpc_pipe_dir_object idmap_pdo;\n\tstruct rpc_pipe *idmap_pipe;\n\tstruct idmap_legacy_upcalldata *idmap_upcall_data;\n\tstruct mutex idmap_mutex;\n\tstruct user_namespace *user_ns;\n};\n\nstruct idmap_msg {\n\t__u8 im_type;\n\t__u8 im_conv;\n\tchar im_name[128];\n\t__u32 im_id;\n\t__u8 im_status;\n};\n\nstruct idmap_legacy_upcalldata {\n\tstruct rpc_pipe_msg pipe_msg;\n\tstruct idmap_msg idmap_msg;\n\tstruct key *authkey;\n\tstruct idmap *idmap;\n};\n\nstruct idt_data {\n\tunsigned int vector;\n\tunsigned int segment;\n\tstruct idt_bits bits;\n\tconst void *addr;\n};\n\nstruct ieee80211_addba_ext_ie {\n\tu8 data;\n};\n\nstruct ieee80211_adv_ttlm_info {\n\tu16 switch_time;\n\tu32 duration;\n\tu16 map;\n\tbool active;\n};\n\nstruct ieee80211_aid_response_ie {\n\t__le16 aid;\n\tu8 switch_count;\n\t__le16 response_int;\n} __attribute__((packed));\n\nstruct ieee80211_sta;\n\nstruct ieee80211_ampdu_params {\n\tenum ieee80211_ampdu_mlme_action action;\n\tstruct ieee80211_sta *sta;\n\tu16 tid;\n\tu16 ssn;\n\tu16 buf_size;\n\tbool amsdu;\n\tu16 timeout;\n};\n\nstruct ieee80211_ba_event {\n\tstruct ieee80211_sta *sta;\n\tu16 tid;\n\tu16 ssn;\n};\n\nstruct ieee80211_eht_operation_info {\n\tu8 control;\n\tu8 ccfs0;\n\tu8 ccfs1;\n\tu8 optional[0];\n};\n\nstruct ieee80211_bandwidth_indication {\n\tu8 params;\n\tstruct ieee80211_eht_operation_info info;\n};\n\nstruct ieee80211_bar {\n\t__le16 frame_control;\n\t__le16 duration;\n\t__u8 ra[6];\n\t__u8 ta[6];\n\t__le16 control;\n\t__le16 start_seq_num;\n};\n\nstruct ieee80211_rate;\n\nstruct ieee80211_bss {\n\tu32 device_ts_beacon;\n\tu32 device_ts_presp;\n\tbool wmm_used;\n\tbool uapsd_supported;\n\tu8 supp_rates[32];\n\tsize_t supp_rates_len;\n\tstruct ieee80211_rate *beacon_rate;\n\tu32 vht_cap_info;\n\tbool has_erp_value;\n\tu8 erp_value;\n\tu8 corrupt_data;\n\tu8 valid_data;\n};\n\nstruct ieee80211_chan_req {\n\tstruct cfg80211_chan_def oper;\n\tstruct cfg80211_chan_def ap;\n};\n\nstruct ieee80211_mu_group_data {\n\tu8 membership[8];\n\tu8 position[16];\n};\n\nstruct ieee80211_p2p_noa_desc {\n\tu8 count;\n\t__le32 duration;\n\t__le32 interval;\n\t__le32 start_time;\n} __attribute__((packed));\n\nstruct ieee80211_p2p_noa_attr {\n\tu8 index;\n\tu8 oppps_ctwindow;\n\tstruct ieee80211_p2p_noa_desc desc[4];\n};\n\nstruct ieee80211_fils_discovery {\n\tu32 min_interval;\n\tu32 max_interval;\n};\n\nstruct ieee80211_parsed_tpe_eirp {\n\tbool valid;\n\ts8 power[5];\n\tu8 count;\n};\n\nstruct ieee80211_parsed_tpe_psd {\n\tbool valid;\n\ts8 power[16];\n\tu8 count;\n\tu8 n;\n};\n\nstruct ieee80211_parsed_tpe {\n\tstruct ieee80211_parsed_tpe_eirp max_local[2];\n\tstruct ieee80211_parsed_tpe_eirp max_reg_client[2];\n\tstruct ieee80211_parsed_tpe_psd psd_local[2];\n\tstruct ieee80211_parsed_tpe_psd psd_reg_client[2];\n};\n\nstruct ieee80211_vif;\n\nstruct ieee80211_ftm_responder_params;\n\nstruct ieee80211_chanctx_conf;\n\nstruct ieee80211_bss_conf {\n\tstruct ieee80211_vif *vif;\n\tstruct cfg80211_bss *bss;\n\tconst u8 *bssid;\n\tunsigned int link_id;\n\tu8 addr[6];\n\tu8 htc_trig_based_pkt_ext;\n\tbool uora_exists;\n\tu8 uora_ocw_range;\n\tu16 frame_time_rts_th;\n\tbool he_support;\n\tbool twt_requester;\n\tbool twt_responder;\n\tbool twt_protected;\n\tbool twt_broadcast;\n\tbool use_cts_prot;\n\tbool use_short_preamble;\n\tbool use_short_slot;\n\tbool enable_beacon;\n\tu8 dtim_period;\n\tu16 beacon_int;\n\tu16 assoc_capability;\n\tu64 sync_tsf;\n\tu32 sync_device_ts;\n\tu8 sync_dtim_count;\n\tu32 basic_rates;\n\tstruct ieee80211_rate *beacon_rate;\n\tint mcast_rate[6];\n\tu16 ht_operation_mode;\n\ts32 cqm_rssi_thold;\n\tu32 cqm_rssi_hyst;\n\ts32 cqm_rssi_low;\n\ts32 cqm_rssi_high;\n\tstruct ieee80211_chan_req chanreq;\n\tstruct ieee80211_mu_group_data mu_group;\n\tbool qos;\n\tbool hidden_ssid;\n\tint txpower;\n\tenum nl80211_tx_power_setting txpower_type;\n\tstruct ieee80211_p2p_noa_attr p2p_noa_attr;\n\tbool allow_p2p_go_ps;\n\tu16 max_idle_period;\n\tbool protected_keep_alive;\n\tbool ftm_responder;\n\tstruct ieee80211_ftm_responder_params *ftmr_params;\n\tbool nontransmitted;\n\tstruct ieee80211_bss_conf *tx_bss_conf;\n\tu8 transmitter_bssid[6];\n\tu8 bssid_index;\n\tu8 bssid_indicator;\n\tbool ema_ap;\n\tu8 profile_periodicity;\n\tstruct {\n\t\tu32 params;\n\t\tu16 nss_set;\n\t} he_oper;\n\tstruct ieee80211_he_obss_pd he_obss_pd;\n\tstruct cfg80211_he_bss_color he_bss_color;\n\tstruct ieee80211_fils_discovery fils_discovery;\n\tu32 unsol_bcast_probe_resp_interval;\n\tstruct cfg80211_bitrate_mask beacon_tx_rate;\n\tenum ieee80211_ap_reg_power power_type;\n\tstruct ieee80211_parsed_tpe tpe;\n\tu8 pwr_reduction;\n\tbool eht_support;\n\tbool epcs_support;\n\tbool uhr_support;\n\tbool csa_active;\n\tbool mu_mimo_owner;\n\tstruct ieee80211_chanctx_conf *chanctx_conf;\n\tbool color_change_active;\n\tu8 color_change_color;\n\tbool ht_ldpc;\n\tbool vht_ldpc;\n\tbool he_ldpc;\n\tbool vht_su_beamformer;\n\tbool vht_su_beamformee;\n\tbool vht_mu_beamformer;\n\tbool vht_mu_beamformee;\n\tbool he_su_beamformer;\n\tbool he_su_beamformee;\n\tbool he_mu_beamformer;\n\tbool he_full_ul_mumimo;\n\tbool eht_su_beamformer;\n\tbool eht_su_beamformee;\n\tbool eht_mu_beamformer;\n\tbool eht_80mhz_full_bw_ul_mumimo;\n\tbool eht_disable_mcs15;\n\tu8 bss_param_ch_cnt;\n\tu8 bss_param_ch_cnt_link_id;\n\tu8 s1g_long_beacon_period;\n};\n\nstruct ieee80211_bss_max_idle_period_ie {\n\t__le16 max_idle_period;\n\tu8 idle_options;\n} __attribute__((packed));\n\nstruct ieee80211_bssid_index {\n\tu8 bssid_index;\n\tu8 dtim_period;\n\tu8 dtim_count;\n};\n\nstruct ieee80211_ch_switch_timing {\n\t__le16 switch_time;\n\t__le16 switch_timeout;\n};\n\nstruct ieee80211_chanctx_conf {\n\tstruct cfg80211_chan_def def;\n\tstruct cfg80211_chan_def min_def;\n\tstruct cfg80211_chan_def ap;\n\tint radio_idx;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tbool radar_enabled;\n\tlong: 0;\n\tu8 drv_priv[0];\n};\n\nstruct ieee80211_chanctx {\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tenum ieee80211_chanctx_replace_state replace_state;\n\tstruct ieee80211_chanctx *replace_ctx;\n\tenum ieee80211_chanctx_mode mode;\n\tbool driver_present;\n\tstruct ieee80211_chan_req req;\n\tbool radar_detected;\n\tstruct ieee80211_chanctx_conf conf;\n};\n\nstruct ieee80211_sub_if_data;\n\nstruct ieee80211_link_data;\n\nstruct ieee80211_chanctx_user_iter {\n\tstruct ieee80211_chan_req *chanreq;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct ieee80211_link_data *link;\n\tenum nl80211_iftype iftype;\n\tbool reserved;\n\tbool radar_required;\n\tbool done;\n\tenum {\n\t\tCHANCTX_ITER_POS_ASSIGNED = 0,\n\t\tCHANCTX_ITER_POS_RESERVED = 1,\n\t\tCHANCTX_ITER_POS_DONE = 2,\n\t} per_link;\n};\n\nstruct ieee80211_channel {\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tu16 hw_value;\n\tu32 flags;\n\tint max_antenna_gain;\n\tint max_power;\n\tint max_reg_power;\n\tbool beacon_found;\n\tu32 orig_flags;\n\tint orig_mag;\n\tint orig_mpwr;\n\tenum nl80211_dfs_state dfs_state;\n\tlong unsigned int dfs_state_entered;\n\tunsigned int dfs_cac_ms;\n\ts8 psd;\n};\n\nstruct ieee80211_channel_sw_ie {\n\tu8 mode;\n\tu8 new_ch_num;\n\tu8 count;\n};\n\nstruct ieee80211_channel_switch {\n\tu64 timestamp;\n\tu32 device_timestamp;\n\tbool block_tx;\n\tstruct cfg80211_chan_def chandef;\n\tu8 count;\n\tu8 link_id;\n\tu32 delay;\n};\n\nstruct ieee80211_color_change_settings {\n\tu16 counter_offset_beacon;\n\tu16 counter_offset_presp;\n\tu8 count;\n};\n\nstruct ieee80211_conf {\n\tu32 flags;\n\tint power_level;\n\tint dynamic_ps_timeout;\n\tu16 listen_interval;\n\tu8 ps_dtim_period;\n\tu8 long_frame_max_tx_count;\n\tu8 short_frame_max_tx_count;\n\tstruct cfg80211_chan_def chandef;\n\tbool radar_enabled;\n\tenum ieee80211_smps_mode smps_mode;\n};\n\nstruct ieee80211_conn_settings {\n\tenum ieee80211_conn_mode mode;\n\tenum ieee80211_conn_bw_limit bw_limit;\n};\n\nstruct ieee80211_country_ie_triplet {\n\tunion {\n\t\tstruct {\n\t\t\tu8 first_channel;\n\t\t\tu8 num_channels;\n\t\t\ts8 max_power;\n\t\t} chans;\n\t\tstruct {\n\t\t\tu8 reg_extension_id;\n\t\t\tu8 reg_class;\n\t\t\tu8 coverage_class;\n\t\t} ext;\n\t};\n};\n\nstruct ieee80211_csa_ie {\n\tstruct ieee80211_chan_req chanreq;\n\tu8 mode;\n\tu8 count;\n\tu8 ttl;\n\tu16 pre_value;\n\tu16 reason_code;\n\tu32 max_switch_time;\n};\n\nstruct ieee80211_csa_settings {\n\tconst u16 *counter_offsets_beacon;\n\tconst u16 *counter_offsets_presp;\n\tint n_counter_offsets_beacon;\n\tint n_counter_offsets_presp;\n\tu8 count;\n};\n\nstruct ieee80211_cts {\n\t__le16 frame_control;\n\t__le16 duration;\n\tu8 ra[6];\n};\n\nstruct ieee80211_eht_cap_elem_fixed {\n\tu8 mac_cap_info[2];\n\tu8 phy_cap_info[9];\n};\n\nstruct ieee80211_eht_cap_elem {\n\tstruct ieee80211_eht_cap_elem_fixed fixed;\n\tu8 optional[0];\n};\n\nstruct ieee80211_eht_mcs_nss_supp_20mhz_only {\n\tunion {\n\t\tstruct {\n\t\t\tu8 rx_tx_mcs7_max_nss;\n\t\t\tu8 rx_tx_mcs9_max_nss;\n\t\t\tu8 rx_tx_mcs11_max_nss;\n\t\t\tu8 rx_tx_mcs13_max_nss;\n\t\t};\n\t\tu8 rx_tx_max_nss[4];\n\t};\n};\n\nstruct ieee80211_eht_mcs_nss_supp_bw {\n\tunion {\n\t\tstruct {\n\t\t\tu8 rx_tx_mcs9_max_nss;\n\t\t\tu8 rx_tx_mcs11_max_nss;\n\t\t\tu8 rx_tx_mcs13_max_nss;\n\t\t};\n\t\tu8 rx_tx_max_nss[3];\n\t};\n};\n\nstruct ieee80211_eht_mcs_nss_supp {\n\tunion {\n\t\tstruct ieee80211_eht_mcs_nss_supp_20mhz_only only_20mhz;\n\t\tstruct {\n\t\t\tstruct ieee80211_eht_mcs_nss_supp_bw _80;\n\t\t\tstruct ieee80211_eht_mcs_nss_supp_bw _160;\n\t\t\tstruct ieee80211_eht_mcs_nss_supp_bw _320;\n\t\t} bw;\n\t};\n};\n\nstruct ieee80211_eht_operation {\n\tu8 params;\n\tstruct ieee80211_eht_mcs_nss_supp_20mhz_only basic_mcs_nss;\n\tu8 optional[0];\n};\n\nstruct ieee80211_tdls_lnkie;\n\nstruct ieee80211_tim_ie;\n\nstruct ieee80211_ht_operation;\n\nstruct ieee80211_vht_operation;\n\nstruct ieee80211_he_spr;\n\nstruct ieee80211_mu_edca_param_set;\n\nstruct ieee80211_he_6ghz_capa;\n\nstruct ieee80211_rann_ie;\n\nstruct ieee80211_ext_chansw_ie;\n\nstruct ieee80211_wide_bw_chansw_ie;\n\nstruct ieee80211_timeout_interval_ie;\n\nstruct ieee80211_sec_chan_offs_ie;\n\nstruct ieee80211_mesh_chansw_params_ie;\n\nstruct ieee80211_multiple_bssid_configuration;\n\nstruct ieee80211_s1g_oper_ie;\n\nstruct ieee80211_s1g_bcn_compat_ie;\n\nstruct ieee80211_ttlm_elem;\n\nstruct ieee80211_uhr_cap;\n\nstruct ieee802_11_elems {\n\tconst u8 *ie_start;\n\tsize_t total_len;\n\tu32 crc;\n\tconst struct ieee80211_tdls_lnkie *lnk_id;\n\tconst struct ieee80211_ch_switch_timing *ch_sw_timing;\n\tconst u8 *ext_capab;\n\tconst u8 *ssid;\n\tconst u8 *supp_rates;\n\tconst u8 *ds_params;\n\tconst struct ieee80211_tim_ie *tim;\n\tconst u8 *rsn;\n\tconst u8 *rsnx;\n\tconst u8 *erp_info;\n\tconst u8 *ext_supp_rates;\n\tconst u8 *wmm_info;\n\tconst u8 *wmm_param;\n\tconst struct ieee80211_ht_cap *ht_cap_elem;\n\tconst struct ieee80211_ht_operation *ht_operation;\n\tconst struct ieee80211_vht_cap *vht_cap_elem;\n\tconst struct ieee80211_vht_operation *vht_operation;\n\tconst struct ieee80211_meshconf_ie *mesh_config;\n\tconst u8 *he_cap;\n\tconst struct ieee80211_he_operation *he_operation;\n\tconst struct ieee80211_he_spr *he_spr;\n\tconst struct ieee80211_mu_edca_param_set *mu_edca_param_set;\n\tconst struct ieee80211_he_6ghz_capa *he_6ghz_capa;\n\tconst u8 *uora_element;\n\tconst u8 *mesh_id;\n\tconst u8 *peering;\n\tconst __le16 *awake_window;\n\tconst u8 *preq;\n\tconst u8 *prep;\n\tconst u8 *perr;\n\tconst struct ieee80211_rann_ie *rann;\n\tconst struct ieee80211_channel_sw_ie *ch_switch_ie;\n\tconst struct ieee80211_ext_chansw_ie *ext_chansw_ie;\n\tconst struct ieee80211_wide_bw_chansw_ie *wide_bw_chansw_ie;\n\tconst u8 *max_channel_switch_time;\n\tconst u8 *country_elem;\n\tconst u8 *pwr_constr_elem;\n\tconst u8 *cisco_dtpc_elem;\n\tconst struct ieee80211_timeout_interval_ie *timeout_int;\n\tconst u8 *opmode_notif;\n\tconst struct ieee80211_sec_chan_offs_ie *sec_chan_offs;\n\tstruct ieee80211_mesh_chansw_params_ie *mesh_chansw_params_ie;\n\tconst struct ieee80211_bss_max_idle_period_ie *max_idle_period_ie;\n\tconst struct ieee80211_multiple_bssid_configuration *mbssid_config_ie;\n\tconst struct ieee80211_bssid_index *bssid_index;\n\tu8 max_bssid_indicator;\n\tu8 dtim_count;\n\tu8 dtim_period;\n\tconst struct ieee80211_addba_ext_ie *addba_ext_ie;\n\tconst struct ieee80211_s1g_cap *s1g_capab;\n\tconst struct ieee80211_s1g_oper_ie *s1g_oper;\n\tconst struct ieee80211_s1g_bcn_compat_ie *s1g_bcn_compat;\n\tconst struct ieee80211_aid_response_ie *aid_resp;\n\tconst struct ieee80211_eht_cap_elem *eht_cap;\n\tconst struct ieee80211_eht_operation *eht_operation;\n\tconst struct ieee80211_multi_link_elem *ml_basic;\n\tconst struct ieee80211_multi_link_elem *ml_reconf;\n\tconst struct ieee80211_multi_link_elem *ml_epcs;\n\tconst struct ieee80211_bandwidth_indication *bandwidth_indication;\n\tconst struct ieee80211_ttlm_elem *ttlm[2];\n\tconst struct ieee80211_uhr_cap *uhr_cap;\n\tconst struct ieee80211_uhr_operation *uhr_operation;\n\tstruct ieee80211_parsed_tpe tpe;\n\tstruct ieee80211_parsed_tpe csa_tpe;\n\tu8 ext_capab_len;\n\tu8 ssid_len;\n\tu8 supp_rates_len;\n\tu8 tim_len;\n\tu8 rsn_len;\n\tu8 rsnx_len;\n\tu8 ext_supp_rates_len;\n\tu8 wmm_info_len;\n\tu8 wmm_param_len;\n\tu8 he_cap_len;\n\tu8 mesh_id_len;\n\tu8 peering_len;\n\tu8 preq_len;\n\tu8 prep_len;\n\tu8 perr_len;\n\tu8 country_elem_len;\n\tu8 bssid_index_len;\n\tu8 eht_cap_len;\n\tu8 uhr_cap_len;\n\tu8 uhr_operation_len;\n\tsize_t ml_basic_len;\n\tsize_t ml_reconf_len;\n\tsize_t ml_epcs_len;\n\tu8 ttlm_num;\n\tstruct ieee80211_mle_per_sta_profile *prof;\n\tsize_t sta_prof_len;\n\tu8 parse_error;\n};\n\nstruct ieee80211_elems_parse {\n\tstruct ieee802_11_elems elems;\n\tconst struct element *ml_basic_elem;\n\tconst struct element *ml_reconf_elem;\n\tconst struct element *ml_epcs_elem;\n\tbool multi_link_inner;\n\tbool skip_vendor;\n\tsize_t scratch_len;\n\tu8 *scratch_pos;\n\tu8 scratch[0];\n};\n\nstruct ieee80211_elems_parse_params {\n\tenum ieee80211_conn_mode mode;\n\tconst u8 *start;\n\tsize_t len;\n\tu8 type;\n\tu64 filter;\n\tu32 crc;\n\tstruct cfg80211_bss *bss;\n\tint link_id;\n\tbool from_ap;\n};\n\nstruct ieee80211_mutable_offsets {\n\tu16 tim_offset;\n\tu16 tim_length;\n\tu16 cntdwn_counter_offs[2];\n\tu16 mbssid_off;\n};\n\nstruct ieee80211_ema_beacons {\n\tu8 cnt;\n\tstruct {\n\t\tstruct sk_buff *skb;\n\t\tstruct ieee80211_mutable_offsets offs;\n\t} bcn[0];\n};\n\nstruct ieee80211_eml_params {\n\tu8 link_id;\n\tu8 control;\n\tu16 link_bitmap;\n\tu8 emlmr_mcs_map_count;\n\tu8 emlmr_mcs_map_bw[9];\n};\n\nstruct ieee80211_enh_crit_upd {\n\tu8 v;\n};\n\nstruct ieee80211_rssi_event {\n\tenum ieee80211_rssi_event_data data;\n};\n\nstruct ieee80211_mlme_event {\n\tenum ieee80211_mlme_event_data data;\n\tenum ieee80211_mlme_event_status status;\n\tu16 reason;\n};\n\nstruct ieee80211_event {\n\tenum ieee80211_event_type type;\n\tunion {\n\t\tstruct ieee80211_rssi_event rssi;\n\t\tstruct ieee80211_mlme_event mlme;\n\t\tstruct ieee80211_ba_event ba;\n\t} u;\n};\n\nstruct ieee80211_ext {\n\t__le16 frame_control;\n\t__le16 duration;\n\tunion {\n\t\tstruct {\n\t\t\tu8 sa[6];\n\t\t\t__le32 timestamp;\n\t\t\tu8 change_seq;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) s1g_beacon;\n\t} u;\n};\n\nstruct ieee80211_ext_chansw_ie {\n\tu8 mode;\n\tu8 new_operating_class;\n\tu8 new_ch_num;\n\tu8 count;\n};\n\nstruct ieee80211_fast_rx {\n\tstruct net_device *dev;\n\tenum nl80211_iftype vif_type;\n\tu8 vif_addr[6];\n\tu8 rfc1042_hdr[6];\n\t__be16 control_port_protocol;\n\t__le16 expected_ds_bits;\n\tu8 icv_len;\n\tu8 key: 1;\n\tu8 internal_forward: 1;\n\tu8 uses_rss: 1;\n\tu8 da_offs;\n\tu8 sa_offs;\n\tstruct callback_head callback_head;\n};\n\nstruct ieee80211_key;\n\nstruct ieee80211_fast_tx {\n\tstruct ieee80211_key *key;\n\tu8 hdr_len;\n\tu8 sa_offs;\n\tu8 da_offs;\n\tu8 pn_offs;\n\tu8 band;\n\tshort: 0;\n\tu8 hdr[56];\n\tstruct callback_head callback_head;\n};\n\nstruct ieee80211_fragment_entry {\n\tstruct sk_buff_head skb_list;\n\tlong unsigned int first_frag_time;\n\tu16 seq;\n\tu16 extra_len;\n\tu16 last_frag;\n\tu8 rx_queue;\n\tu8 check_sequential_pn: 1;\n\tu8 is_protected: 1;\n\tu8 last_pn[6];\n\tunsigned int key_color;\n};\n\nstruct ieee80211_fragment_cache {\n\tstruct ieee80211_fragment_entry entries[4];\n\tunsigned int next;\n};\n\nstruct ieee80211_freq_range {\n\tu32 start_freq_khz;\n\tu32 end_freq_khz;\n\tu32 max_bandwidth_khz;\n};\n\nstruct ieee80211_ftm_responder_params {\n\tconst u8 *lci;\n\tconst u8 *civicloc;\n\tsize_t lci_len;\n\tsize_t civicloc_len;\n};\n\nstruct ieee80211_hdr {\n\t__le16 frame_control;\n\t__le16 duration_id;\n\tunion {\n\t\tstruct {\n\t\t\tu8 addr1[6];\n\t\t\tu8 addr2[6];\n\t\t\tu8 addr3[6];\n\t\t};\n\t\tstruct {\n\t\t\tu8 addr1[6];\n\t\t\tu8 addr2[6];\n\t\t\tu8 addr3[6];\n\t\t} addrs;\n\t};\n\t__le16 seq_ctrl;\n\tu8 addr4[6];\n};\n\nstruct ieee80211_hdr_3addr {\n\t__le16 frame_control;\n\t__le16 duration_id;\n\tu8 addr1[6];\n\tu8 addr2[6];\n\tu8 addr3[6];\n\t__le16 seq_ctrl;\n};\n\nstruct ieee80211_he_6ghz_capa {\n\t__le16 capa;\n};\n\nstruct ieee80211_he_6ghz_oper {\n\tu8 primary;\n\tu8 control;\n\tu8 ccfs0;\n\tu8 ccfs1;\n\tu8 minrate;\n};\n\nstruct ieee80211_he_cap_elem {\n\tu8 mac_cap_info[6];\n\tu8 phy_cap_info[11];\n};\n\nstruct ieee80211_he_mcs_nss_supp {\n\t__le16 rx_mcs_80;\n\t__le16 tx_mcs_80;\n\t__le16 rx_mcs_160;\n\t__le16 tx_mcs_160;\n\t__le16 rx_mcs_80p80;\n\t__le16 tx_mcs_80p80;\n};\n\nstruct ieee80211_he_mu_edca_param_ac_rec {\n\tu8 aifsn;\n\tu8 ecw_min_max;\n\tu8 mu_edca_timer;\n};\n\nstruct ieee80211_he_operation {\n\t__le32 he_oper_params;\n\t__le16 he_mcs_nss_set;\n\tu8 optional[0];\n} __attribute__((packed));\n\nstruct ieee80211_he_spr {\n\tu8 he_sr_control;\n\tu8 optional[0];\n};\n\nstruct ieee80211_ht_operation {\n\tu8 primary_chan;\n\tu8 ht_param;\n\t__le16 operation_mode;\n\t__le16 stbc_param;\n\tu8 basic_set[16];\n};\n\nstruct ieee80211_hw {\n\tstruct ieee80211_conf conf;\n\tstruct wiphy *wiphy;\n\tconst char *rate_control_algorithm;\n\tvoid *priv;\n\tlong unsigned int flags[1];\n\tunsigned int extra_tx_headroom;\n\tunsigned int extra_beacon_tailroom;\n\tint vif_data_size;\n\tint sta_data_size;\n\tint chanctx_data_size;\n\tint txq_data_size;\n\tu16 queues;\n\tu16 max_listen_interval;\n\ts8 max_signal;\n\tu8 max_rates;\n\tu8 max_report_rates;\n\tu8 max_rate_tries;\n\tu16 max_rx_aggregation_subframes;\n\tu16 max_tx_aggregation_subframes;\n\tu8 max_tx_fragments;\n\tu8 offchannel_tx_hw_queue;\n\tu8 radiotap_mcs_details;\n\tu16 radiotap_vht_details;\n\tstruct {\n\t\tint units_pos;\n\t\ts16 accuracy;\n\t} radiotap_timestamp;\n\tnetdev_features_t netdev_features;\n\tu8 uapsd_queues;\n\tu8 uapsd_max_sp_len;\n\tu8 max_nan_de_entries;\n\tu8 tx_sk_pacing_shift;\n\tu8 weight_multiplier;\n\tu32 max_mtu;\n\tconst s8 *tx_power_levels;\n\tu8 max_txpwr_levels_idx;\n};\n\nstruct ps_data {\n\tu8 tim[256];\n\tstruct sk_buff_head bc_buf;\n\tatomic_t num_sta_ps;\n\tint dtim_count;\n\tbool dtim_bc_mc;\n\tint sb_count;\n};\n\nstruct ieee80211_if_ap {\n\tstruct list_head vlans;\n\tstruct ps_data ps;\n\tatomic_t num_mcast_sta;\n\tbool multicast_to_unicast;\n\tbool active;\n};\n\nstruct ieee80211_if_ibss {\n\tstruct timer_list timer;\n\tstruct wiphy_work csa_connection_drop_work;\n\tlong unsigned int last_scan_completed;\n\tu32 basic_rates;\n\tbool fixed_bssid;\n\tbool fixed_channel;\n\tbool privacy;\n\tbool control_port;\n\tbool userspace_handles_dfs;\n\tshort: 0;\n\tu8 bssid[6];\n\tu8 ssid[32];\n\tu8 ssid_len;\n\tu8 ie_len;\n\tu8 *ie;\n\tstruct cfg80211_chan_def chandef;\n\tlong unsigned int ibss_join_req;\n\tstruct beacon_data *presp;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tspinlock_t incomplete_lock;\n\tstruct list_head incomplete_stations;\n\tenum {\n\t\tIEEE80211_IBSS_MLME_SEARCH = 0,\n\t\tIEEE80211_IBSS_MLME_JOINED = 1,\n\t} state;\n};\n\nstruct wiphy_delayed_work {\n\tstruct wiphy_work work;\n\tstruct wiphy *wiphy;\n\tstruct timer_list timer;\n};\n\nstruct ieee80211_sta_tx_tspec {\n\tlong unsigned int time_slice_start;\n\tu32 admitted_time;\n\tu8 tsid;\n\ts8 up;\n\tu32 consumed_tx_time;\n\tenum {\n\t\tTX_TSPEC_ACTION_NONE = 0,\n\t\tTX_TSPEC_ACTION_DOWNGRADE = 1,\n\t\tTX_TSPEC_ACTION_STOP_DOWNGRADE = 2,\n\t} action;\n\tbool downgraded;\n};\n\nstruct wiphy_hrtimer_work {\n\tstruct wiphy_work work;\n\tstruct wiphy *wiphy;\n\tstruct hrtimer timer;\n};\n\nstruct ieee80211_mgd_auth_data;\n\nstruct ieee80211_mgd_assoc_data;\n\nstruct ieee80211_if_managed {\n\tstruct timer_list timer;\n\tstruct timer_list conn_mon_timer;\n\tstruct timer_list bcn_mon_timer;\n\tstruct wiphy_work monitor_work;\n\tstruct wiphy_work beacon_connection_loss_work;\n\tstruct wiphy_work csa_connection_drop_work;\n\tlong unsigned int beacon_timeout;\n\tlong unsigned int probe_timeout;\n\tint probe_send_count;\n\tbool nullfunc_failed;\n\tu8 connection_loss: 1;\n\tu8 driver_disconnect: 1;\n\tu8 reconnect: 1;\n\tu8 associated: 1;\n\tstruct ieee80211_mgd_auth_data *auth_data;\n\tstruct ieee80211_mgd_assoc_data *assoc_data;\n\tlong unsigned int userspace_selectors[2];\n\tbool powersave;\n\tbool broken_ap;\n\tunsigned int flags;\n\tu16 mcast_seq_last;\n\tbool status_acked;\n\tbool status_received;\n\t__le16 status_fc;\n\tenum {\n\t\tIEEE80211_MFP_DISABLED = 0,\n\t\tIEEE80211_MFP_OPTIONAL = 1,\n\t\tIEEE80211_MFP_REQUIRED = 2,\n\t} mfp;\n\tunsigned int uapsd_queues;\n\tunsigned int uapsd_max_sp_len;\n\tu8 use_4addr;\n\tint rssi_min_thold;\n\tint rssi_max_thold;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tstruct ieee80211_vht_cap vht_capa;\n\tstruct ieee80211_vht_cap vht_capa_mask;\n\tstruct ieee80211_s1g_cap s1g_capa;\n\tstruct ieee80211_s1g_cap s1g_capa_mask;\n\tu8 tdls_peer[6];\n\tstruct wiphy_delayed_work tdls_peer_del_work;\n\tstruct sk_buff *orig_teardown_skb;\n\tstruct sk_buff *teardown_skb;\n\tspinlock_t teardown_lock;\n\tbool tdls_wider_bw_prohibited;\n\tstruct ieee80211_sta_tx_tspec tx_tspec[4];\n\tstruct wiphy_delayed_work tx_tspec_wk;\n\tu8 *assoc_req_ies;\n\tsize_t assoc_req_ies_len;\n\tstruct wiphy_hrtimer_work ml_reconf_work;\n\tu16 removed_links;\n\tstruct wiphy_hrtimer_work ttlm_work;\n\tstruct ieee80211_adv_ttlm_info ttlm_info;\n\tstruct wiphy_work teardown_ttlm_work;\n\tu8 dialog_token_alloc;\n\tstruct wiphy_delayed_work neg_ttlm_timeout_work;\n\tstruct {\n\t\tstruct ieee80211_mgd_assoc_data *add_links_data;\n\t\tstruct wiphy_delayed_work wk;\n\t\tu16 removed_links;\n\t\tu16 added_links;\n\t\tu8 dialog_token;\n\t} reconf;\n\tstruct {\n\t\tbool enabled;\n\t\tu8 dialog_token;\n\t} epcs;\n};\n\nstruct mesh_preq_queue {\n\tstruct list_head list;\n\tu8 dst[6];\n\tu8 flags;\n};\n\nstruct mesh_stats {\n\t__u32 fwded_mcast;\n\t__u32 fwded_unicast;\n\t__u32 fwded_frames;\n\t__u32 dropped_frames_ttl;\n\t__u32 dropped_frames_no_route;\n};\n\nstruct mesh_config {\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu16 min_discovery_timeout;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tbool dot11MeshConnectedToMeshGate;\n\tbool dot11MeshConnectedToAuthServer;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tenum nl80211_mesh_power_mode power_mode;\n\tu16 dot11MeshAwakeWindowDuration;\n\tu32 plink_timeout;\n\tbool dot11MeshNolearn;\n};\n\nstruct mesh_table {\n\tstruct hlist_head known_gates;\n\tspinlock_t gates_lock;\n\tstruct rhashtable rhead;\n\tstruct hlist_head walk_head;\n\tspinlock_t walk_lock;\n\tatomic_t entries;\n};\n\nstruct mesh_tx_cache {\n\tstruct rhashtable rht;\n\tstruct hlist_head walk_head;\n\tspinlock_t walk_lock;\n};\n\nstruct mesh_rmc;\n\nstruct ieee80211_mesh_sync_ops;\n\nstruct mesh_csa_settings;\n\nstruct ieee80211_if_mesh {\n\tstruct timer_list housekeeping_timer;\n\tstruct timer_list mesh_path_timer;\n\tstruct timer_list mesh_path_root_timer;\n\tlong unsigned int wrkq_flags;\n\tlong unsigned int mbss_changed[1];\n\tbool userspace_handles_dfs;\n\tu8 mesh_id[32];\n\tsize_t mesh_id_len;\n\tu8 mesh_pp_id;\n\tu8 mesh_pm_id;\n\tu8 mesh_cc_id;\n\tu8 mesh_sp_id;\n\tu8 mesh_auth_id;\n\tu32 sn;\n\tu32 preq_id;\n\tatomic_t mpaths;\n\tlong unsigned int last_sn_update;\n\tlong unsigned int next_perr;\n\tlong unsigned int last_preq;\n\tstruct mesh_rmc *rmc;\n\tspinlock_t mesh_preq_queue_lock;\n\tstruct mesh_preq_queue preq_queue;\n\tint preq_queue_len;\n\tstruct mesh_stats mshstats;\n\tstruct mesh_config mshcfg;\n\tatomic_t estab_plinks;\n\tatomic_t mesh_seqnum;\n\tbool accepting_plinks;\n\tint num_gates;\n\tstruct beacon_data *beacon;\n\tconst u8 *ie;\n\tu8 ie_len;\n\tenum {\n\t\tIEEE80211_MESH_SEC_NONE = 0,\n\t\tIEEE80211_MESH_SEC_AUTHED = 1,\n\t\tIEEE80211_MESH_SEC_SECURED = 2,\n\t} security;\n\tbool user_mpm;\n\tconst struct ieee80211_mesh_sync_ops *sync_ops;\n\ts64 sync_offset_clockdrift_max;\n\tspinlock_t sync_offset_lock;\n\tenum nl80211_mesh_power_mode nonpeer_pm;\n\tint ps_peers_light_sleep;\n\tint ps_peers_deep_sleep;\n\tstruct ps_data ps;\n\tstruct mesh_csa_settings *csa;\n\tenum {\n\t\tIEEE80211_MESH_CSA_ROLE_NONE = 0,\n\t\tIEEE80211_MESH_CSA_ROLE_INIT = 1,\n\t\tIEEE80211_MESH_CSA_ROLE_REPEATER = 2,\n\t} csa_role;\n\tu8 chsw_ttl;\n\tu16 pre_value;\n\tint meshconf_offset;\n\tstruct mesh_table mesh_paths;\n\tstruct mesh_table mpp_paths;\n\tint mesh_paths_generation;\n\tint mpp_paths_generation;\n\tstruct mesh_tx_cache tx_cache;\n};\n\nstruct ieee80211_if_mntr {\n\tu32 flags;\n\tu8 mu_follow_addr[6];\n\tstruct list_head list;\n};\n\nstruct ieee80211_if_nan {\n\tstruct cfg80211_nan_conf conf;\n\tbool started;\n\tspinlock_t func_lock;\n\tstruct idr function_inst_ids;\n};\n\nstruct ieee80211_if_ocb {\n\tstruct timer_list housekeeping_timer;\n\tlong unsigned int wrkq_flags;\n\tspinlock_t incomplete_lock;\n\tstruct list_head incomplete_stations;\n\tbool joined;\n};\n\nstruct sta_info;\n\nstruct ieee80211_if_vlan {\n\tstruct list_head list;\n\tstruct sta_info *sta;\n\tatomic_t num_mcast_sta;\n};\n\nstruct ieee80211_iface_limit;\n\nstruct ieee80211_iface_combination {\n\tconst struct ieee80211_iface_limit *limits;\n\tu32 num_different_channels;\n\tu16 max_interfaces;\n\tu8 n_limits;\n\tbool beacon_int_infra_match;\n\tu8 radar_detect_widths;\n\tu8 radar_detect_regions;\n\tu32 beacon_int_min_gcd;\n};\n\nstruct ieee80211_iface_limit {\n\tu16 max;\n\tu16 types;\n};\n\nstruct tkip_ctx {\n\tu16 p1k[5];\n\tu32 p1k_iv32;\n\tenum ieee80211_internal_tkip_state state;\n};\n\nstruct tkip_ctx_rx {\n\tstruct tkip_ctx ctx;\n\tu32 iv32;\n\tu16 iv16;\n};\n\nstruct ieee80211_key_conf {\n\tatomic64_t tx_pn;\n\tu32 cipher;\n\tu8 icv_len;\n\tu8 iv_len;\n\tu8 hw_key_idx;\n\ts8 keyidx;\n\tu16 flags;\n\ts8 link_id;\n\tu8 keylen;\n\tu8 key[0];\n};\n\nstruct ieee80211_local;\n\nstruct ieee80211_key {\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct sta_info *sta;\n\tstruct list_head list;\n\tunsigned int flags;\n\tunion {\n\t\tstruct {\n\t\t\tspinlock_t txlock;\n\t\t\tstruct tkip_ctx tx;\n\t\t\tstruct tkip_ctx_rx rx[16];\n\t\t\tu32 mic_failures;\n\t\t} tkip;\n\t\tstruct {\n\t\t\tu8 rx_pn[102];\n\t\t\tstruct crypto_aead *tfm;\n\t\t\tu32 replays;\n\t\t} ccmp;\n\t\tstruct {\n\t\t\tu8 rx_pn[6];\n\t\t\tstruct crypto_shash *tfm;\n\t\t\tu32 replays;\n\t\t\tu32 icverrors;\n\t\t} aes_cmac;\n\t\tstruct {\n\t\t\tu8 rx_pn[6];\n\t\t\tstruct crypto_aead *tfm;\n\t\t\tu32 replays;\n\t\t\tu32 icverrors;\n\t\t} aes_gmac;\n\t\tstruct {\n\t\t\tu8 rx_pn[102];\n\t\t\tstruct crypto_aead *tfm;\n\t\t\tu32 replays;\n\t\t} gcmp;\n\t\tstruct {\n\t\t\tu8 rx_pn[272];\n\t\t} gen;\n\t} u;\n\tunsigned int color;\n\tstruct ieee80211_key_conf conf;\n};\n\nstruct ieee80211_key_seq {\n\tunion {\n\t\tstruct {\n\t\t\tu32 iv32;\n\t\t\tu16 iv16;\n\t\t} tkip;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} ccmp;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} aes_cmac;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} aes_gmac;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} gcmp;\n\t\tstruct {\n\t\t\tu8 seq[16];\n\t\t\tu8 seq_len;\n\t\t} hw;\n\t};\n};\n\nstruct ieee80211_link_data_managed {\n\tu8 bssid[6];\n\tu8 dtim_period;\n\tenum ieee80211_smps_mode req_smps;\n\tenum ieee80211_smps_mode driver_smps_mode;\n\tstruct ieee80211_conn_settings conn;\n\ts16 p2p_noa_index;\n\tbool tdls_chan_switch_prohibited;\n\tbool have_beacon;\n\tbool tracking_signal_avg;\n\tbool disable_wmm_tracking;\n\tbool operating_11g_mode;\n\tstruct {\n\t\tstruct wiphy_hrtimer_work switch_work;\n\t\tstruct cfg80211_chan_def ap_chandef;\n\t\tstruct ieee80211_parsed_tpe tpe;\n\t\tktime_t time;\n\t\tbool waiting_bcn;\n\t\tbool ignored_same_chan;\n\t\tbool blocked_tx;\n\t} csa;\n\tstruct wiphy_work request_smps_work;\n\tstruct wiphy_work recalc_smps;\n\tbool beacon_crc_valid;\n\tu32 beacon_crc;\n\tstruct ewma_beacon_signal ave_beacon_signal;\n\tint last_ave_beacon_signal;\n\tunsigned int count_beacon_signal;\n\tunsigned int beacon_loss_count;\n\tint last_cqm_event_signal;\n\tint wmm_last_param_set;\n\tint mu_edca_last_param_set;\n};\n\nstruct probe_resp;\n\nstruct unsol_bcast_probe_resp_data;\n\nstruct s1g_short_beacon_data;\n\nstruct ieee80211_link_data_ap {\n\tstruct beacon_data *beacon;\n\tstruct probe_resp *probe_resp;\n\tstruct fils_discovery_data *fils_discovery;\n\tstruct unsol_bcast_probe_resp_data *unsol_bcast_probe_resp;\n\tstruct s1g_short_beacon_data *s1g_short_beacon;\n\tstruct cfg80211_beacon_data *next_beacon;\n};\n\nstruct ieee80211_tx_queue_params {\n\tu16 txop;\n\tu16 cw_min;\n\tu16 cw_max;\n\tu8 aifs;\n\tbool acm;\n\tbool uapsd;\n\tbool mu_edca;\n\tstruct ieee80211_he_mu_edca_param_ac_rec mu_edca_param_rec;\n};\n\nstruct ieee80211_link_data {\n\tstruct ieee80211_sub_if_data *sdata;\n\tunsigned int link_id;\n\tstruct ieee80211_key *gtk[8];\n\tstruct ieee80211_key *default_multicast_key;\n\tstruct ieee80211_key *default_mgmt_key;\n\tstruct ieee80211_key *default_beacon_key;\n\tbool operating_11g_mode;\n\tstruct {\n\t\tstruct wiphy_work finalize_work;\n\t\tstruct ieee80211_chan_req chanreq;\n\t} csa;\n\tstruct wiphy_work color_change_finalize_work;\n\tstruct wiphy_delayed_work color_collision_detect_work;\n\tu64 color_bitmap;\n\tstruct ieee80211_chanctx *reserved_chanctx;\n\tstruct ieee80211_chan_req reserved;\n\tbool reserved_radar_required;\n\tbool reserved_ready;\n\tu8 needed_rx_chains;\n\tenum ieee80211_smps_mode smps_mode;\n\tint user_power_level;\n\tint ap_power_level;\n\tbool radar_required;\n\tstruct wiphy_hrtimer_work dfs_cac_timer_work;\n\tunion {\n\t\tstruct ieee80211_link_data_managed mgd;\n\t\tstruct ieee80211_link_data_ap ap;\n\t} u;\n\tstruct ieee80211_tx_queue_params tx_conf[4];\n\tstruct ieee80211_bss_conf *conf;\n};\n\nstruct ieee80211_sta_ht_cap {\n\tu16 cap;\n\tbool ht_supported;\n\tu8 ampdu_factor;\n\tu8 ampdu_density;\n\tstruct ieee80211_mcs_info mcs;\n\tshort: 0;\n} __attribute__((packed));\n\nstruct ieee80211_sta_vht_cap {\n\tbool vht_supported;\n\tu32 cap;\n\tstruct ieee80211_vht_mcs_info vht_mcs;\n};\n\nstruct ieee80211_sta_he_cap {\n\tbool has_he;\n\tstruct ieee80211_he_cap_elem he_cap_elem;\n\tstruct ieee80211_he_mcs_nss_supp he_mcs_nss_supp;\n\tu8 ppe_thres[25];\n} __attribute__((packed));\n\nstruct ieee80211_sta_eht_cap {\n\tbool has_eht;\n\tstruct ieee80211_eht_cap_elem_fixed eht_cap_elem;\n\tstruct ieee80211_eht_mcs_nss_supp eht_mcs_nss_supp;\n\tu8 eht_ppe_thres[32];\n};\n\nstruct ieee80211_uhr_cap_mac {\n\tu8 mac_cap[5];\n};\n\nstruct ieee80211_uhr_cap_phy {\n\tu8 cap;\n};\n\nstruct ieee80211_sta_uhr_cap {\n\tbool has_uhr;\n\tstruct ieee80211_uhr_cap_mac mac;\n\tstruct ieee80211_uhr_cap_phy phy;\n};\n\nstruct ieee80211_sta_s1g_cap {\n\tbool s1g;\n\tu8 cap[10];\n\tu8 nss_mcs[5];\n};\n\nstruct ieee80211_sta_aggregates {\n\tu16 max_amsdu_len;\n\tu16 max_rc_amsdu_len;\n\tu16 max_tid_amsdu_len[16];\n};\n\nstruct ieee80211_sta_txpwr {\n\ts16 power;\n\tenum nl80211_tx_power_setting type;\n};\n\nstruct ieee80211_link_sta {\n\tstruct ieee80211_sta *sta;\n\tu8 addr[6];\n\tu8 link_id;\n\tlong: 0;\n\tenum ieee80211_smps_mode smps_mode;\n\tu32 supp_rates[6];\n\tstruct ieee80211_sta_ht_cap ht_cap;\n\tint: 0;\n\tstruct ieee80211_sta_vht_cap vht_cap;\n\tstruct ieee80211_sta_he_cap he_cap;\n\tstruct ieee80211_he_6ghz_capa he_6ghz_capa;\n\tstruct ieee80211_sta_eht_cap eht_cap;\n\tstruct ieee80211_sta_uhr_cap uhr_cap;\n\tstruct ieee80211_sta_s1g_cap s1g_cap;\n\tshort: 0;\n\tstruct ieee80211_sta_aggregates agg;\n\tu8 rx_nss;\n\tlong: 0;\n\tenum ieee80211_sta_rx_bandwidth bandwidth;\n\tstruct ieee80211_sta_txpwr txpwr;\n\tlong: 0;\n} __attribute__((packed));\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct led_trigger {\n\tconst char *name;\n\tint (*activate)(struct led_classdev *);\n\tvoid (*deactivate)(struct led_classdev *);\n\tenum led_brightness brightness;\n\tstruct led_hw_trigger_type *trigger_type;\n\tspinlock_t leddev_list_lock;\n\tstruct list_head led_cdevs;\n\tstruct list_head next_trig;\n\tconst struct attribute_group **groups;\n};\n\nstruct ieee80211_ops;\n\nstruct rate_control_ref;\n\nstruct ieee80211_scan_request;\n\nstruct tpt_led_trigger;\n\nstruct ieee80211_local {\n\tstruct ieee80211_hw hw;\n\tstruct fq fq;\n\tstruct codel_vars *cvars;\n\tstruct codel_params cparams;\n\tspinlock_t active_txq_lock[4];\n\tstruct list_head active_txqs[4];\n\tu16 schedule_round[4];\n\tspinlock_t handle_wake_tx_queue_lock;\n\tu16 airtime_flags;\n\tu32 aql_txq_limit_low[4];\n\tu32 aql_txq_limit_high[4];\n\tu32 aql_threshold;\n\tatomic_t aql_total_pending_airtime;\n\tatomic_t aql_ac_pending_airtime[4];\n\tconst struct ieee80211_ops *ops;\n\tstruct workqueue_struct *workqueue;\n\tlong unsigned int queue_stop_reasons[16];\n\tint q_stop_reasons[176];\n\tspinlock_t queue_stop_reason_lock;\n\tint open_count;\n\tint monitors;\n\tint virt_monitors;\n\tint tx_mntrs;\n\tint fif_fcsfail;\n\tint fif_plcpfail;\n\tint fif_control;\n\tint fif_other_bss;\n\tint fif_pspoll;\n\tint fif_probe_req;\n\tbool probe_req_reg;\n\tbool rx_mcast_action_reg;\n\tunsigned int filter_flags;\n\tstruct cfg80211_chan_def dflt_chandef;\n\tbool emulate_chanctx;\n\tspinlock_t filter_lock;\n\tstruct wiphy_work reconfig_filter;\n\tstruct netdev_hw_addr_list mc_list;\n\tbool tim_in_locked_section;\n\tbool suspended;\n\tbool suspending;\n\tbool resuming;\n\tbool quiescing;\n\tbool started;\n\tbool in_reconfig;\n\tbool reconfig_failure;\n\tbool wowlan;\n\tstruct wiphy_work radar_detected_work;\n\tu8 rx_chains;\n\tu8 sband_allocated;\n\tint tx_headroom;\n\tstruct tasklet_struct tasklet;\n\tstruct sk_buff_head skb_queue;\n\tstruct sk_buff_head skb_queue_unreliable;\n\tspinlock_t rx_path_lock;\n\tspinlock_t tim_lock;\n\tlong unsigned int num_sta;\n\tstruct list_head sta_list;\n\tstruct rhltable sta_hash;\n\tstruct rhltable link_sta_hash;\n\tstruct timer_list sta_cleanup;\n\tint sta_generation;\n\tstruct sk_buff_head pending[16];\n\tstruct tasklet_struct tx_pending_tasklet;\n\tstruct tasklet_struct wake_txqs_tasklet;\n\tatomic_t agg_queue_stop[16];\n\tatomic_t iff_allmultis;\n\tstruct rate_control_ref *rate_ctrl;\n\tstruct arc4_ctx wep_tx_ctx;\n\tstruct arc4_ctx wep_rx_ctx;\n\tu32 wep_iv;\n\tstruct list_head interfaces;\n\tstruct list_head mon_list;\n\tstruct mutex iflist_mtx;\n\tlong unsigned int scanning;\n\tstruct cfg80211_ssid scan_ssid;\n\tstruct cfg80211_scan_request *int_scan_req;\n\tstruct cfg80211_scan_request *scan_req;\n\tstruct ieee80211_scan_request *hw_scan_req;\n\tstruct cfg80211_chan_def scan_chandef;\n\tenum nl80211_band hw_scan_band;\n\tint scan_channel_idx;\n\tint scan_ies_len;\n\tint hw_scan_ies_bufsize;\n\tstruct cfg80211_scan_info scan_info;\n\tstruct wiphy_work sched_scan_stopped_work;\n\tstruct ieee80211_sub_if_data *sched_scan_sdata;\n\tstruct cfg80211_sched_scan_request *sched_scan_req;\n\tu8 scan_addr[6];\n\tlong unsigned int leave_oper_channel_time;\n\tenum mac80211_scan_state next_scan_state;\n\tstruct wiphy_delayed_work scan_work;\n\tstruct ieee80211_sub_if_data *scan_sdata;\n\tstruct ieee80211_channel *tmp_channel;\n\tstruct list_head chanctx_list;\n\tstruct led_trigger tx_led;\n\tstruct led_trigger rx_led;\n\tstruct led_trigger assoc_led;\n\tstruct led_trigger radio_led;\n\tstruct led_trigger tpt_led;\n\tatomic_t tx_led_active;\n\tatomic_t rx_led_active;\n\tatomic_t assoc_led_active;\n\tatomic_t radio_led_active;\n\tatomic_t tpt_led_active;\n\tstruct tpt_led_trigger *tpt_led_trigger;\n\tint total_ps_buffered;\n\tbool pspolling;\n\tstruct ieee80211_sub_if_data *ps_sdata;\n\tstruct wiphy_work dynamic_ps_enable_work;\n\tstruct wiphy_work dynamic_ps_disable_work;\n\tstruct timer_list dynamic_ps_timer;\n\tstruct notifier_block ifa_notifier;\n\tstruct notifier_block ifa6_notifier;\n\tint dynamic_ps_forced_timeout;\n\tint user_power_level;\n\tstruct work_struct restart_work;\n\tstruct wiphy_delayed_work roc_work;\n\tstruct list_head roc_list;\n\tstruct wiphy_work hw_roc_start;\n\tstruct wiphy_work hw_roc_done;\n\tlong unsigned int hw_roc_start_time;\n\tu64 roc_cookie_counter;\n\tstruct idr ack_status_frames;\n\tspinlock_t ack_status_lock;\n\tstruct ieee80211_sub_if_data *monitor_sdata;\n\tstruct ieee80211_chan_req monitor_chanreq;\n\tu8 ext_capa[8];\n\tbool wbrf_supported;\n};\n\nstruct ieee80211_low_level_stats {\n\tunsigned int dot11ACKFailureCount;\n\tunsigned int dot11RTSFailureCount;\n\tunsigned int dot11FCSErrorCount;\n\tunsigned int dot11RTSSuccessCount;\n};\n\nstruct ieee80211_mesh_chansw_params_ie {\n\tu8 mesh_ttl;\n\tu8 mesh_flags;\n\t__le16 mesh_reason;\n\t__le16 mesh_pre_value;\n};\n\nstruct ieee80211_mgmt;\n\nstruct ieee80211_rx_status;\n\nstruct ieee80211_mesh_sync_ops {\n\tvoid (*rx_bcn_presp)(struct ieee80211_sub_if_data *, u16, struct ieee80211_mgmt *, unsigned int, const struct ieee80211_meshconf_ie *, struct ieee80211_rx_status *);\n\tvoid (*adjust_tsf)(struct ieee80211_sub_if_data *, struct beacon_data *);\n};\n\nstruct ieee80211_meshconf_ie {\n\tu8 meshconf_psel;\n\tu8 meshconf_pmetric;\n\tu8 meshconf_congest;\n\tu8 meshconf_synch;\n\tu8 meshconf_auth;\n\tu8 meshconf_form;\n\tu8 meshconf_cap;\n};\n\nstruct ieee80211_mgd_assoc_data {\n\tstruct {\n\t\tstruct cfg80211_bss *bss;\n\t\tu8 addr[6];\n\t\tu8 ap_ht_param;\n\t\tstruct ieee80211_vht_cap ap_vht_cap;\n\t\tlong: 0;\n\t\tsize_t elems_len;\n\t\tu8 *elems;\n\t\tstruct ieee80211_conn_settings conn;\n\t\tu16 status;\n\t\tlong: 0;\n\t} __attribute__((packed)) link[15];\n\tu8 ap_addr[6];\n\tconst u8 *supp_rates;\n\tu8 supp_rates_len;\n\tlong unsigned int timeout;\n\tint tries;\n\tu8 prev_ap_addr[6];\n\tu8 ssid[32];\n\tu8 ssid_len;\n\tbool wmm;\n\tbool uapsd;\n\tbool need_beacon;\n\tbool synced;\n\tbool timeout_started;\n\tbool comeback;\n\tbool s1g;\n\tbool spp_amsdu;\n\ts8 assoc_link_id;\n\t__le16 ext_mld_capa_ops;\n\tu8 fils_nonces[32];\n\tu8 fils_kek[64];\n\tsize_t fils_kek_len;\n\tsize_t ie_len;\n\tu8 *ie_pos;\n\tu8 ie[0];\n};\n\nstruct ieee80211_mgd_auth_data {\n\tstruct cfg80211_bss *bss;\n\tlong unsigned int timeout;\n\tint tries;\n\tu16 algorithm;\n\tu16 expected_transaction;\n\tlong unsigned int userspace_selectors[2];\n\tu8 key[13];\n\tu8 key_len;\n\tu8 key_idx;\n\tbool done;\n\tbool waiting;\n\tbool peer_confirmed;\n\tbool timeout_started;\n\tint link_id;\n\tu8 ap_addr[6];\n\tu16 trans;\n\tu16 status;\n\tsize_t data_len;\n\tu8 data[0];\n};\n\nstruct ieee80211_msrment_ie {\n\tu8 token;\n\tu8 mode;\n\tu8 type;\n\tu8 request[0];\n};\n\nstruct ieee80211_tpc_report_ie {\n\tu8 tx_power;\n\tu8 link_margin;\n};\n\nstruct ieee80211_mgmt {\n\t__le16 frame_control;\n\t__le16 duration;\n\tu8 da[6];\n\tu8 sa[6];\n\tu8 bssid[6];\n\t__le16 seq_ctrl;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 auth_alg;\n\t\t\t__le16 auth_transaction;\n\t\t\t__le16 status_code;\n\t\t\tu8 variable[0];\n\t\t} auth;\n\t\tstruct {\n\t\t\t__le16 reason_code;\n\t\t} deauth;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 listen_interval;\n\t\t\tu8 variable[0];\n\t\t} assoc_req;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 status_code;\n\t\t\t__le16 aid;\n\t\t\tu8 variable[0];\n\t\t} assoc_resp;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 status_code;\n\t\t\t__le16 aid;\n\t\t\tu8 variable[0];\n\t\t} reassoc_resp;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 status_code;\n\t\t\tu8 variable[0];\n\t\t} s1g_assoc_resp;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 status_code;\n\t\t\tu8 variable[0];\n\t\t} s1g_reassoc_resp;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 listen_interval;\n\t\t\tu8 current_ap[6];\n\t\t\tu8 variable[0];\n\t\t} reassoc_req;\n\t\tstruct {\n\t\t\t__le16 reason_code;\n\t\t} disassoc;\n\t\tstruct {\n\t\t\t__le64 timestamp;\n\t\t\t__le16 beacon_int;\n\t\t\t__le16 capab_info;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) beacon;\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty_variable;\n\t\t\t\tu8 variable[0];\n\t\t\t};\n\t\t} probe_req;\n\t\tstruct {\n\t\t\t__le64 timestamp;\n\t\t\t__le16 beacon_int;\n\t\t\t__le16 capab_info;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) probe_resp;\n\t\tstruct {\n\t\t\tu8 category;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 status_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} wme_action;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} chan_switch;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tstruct ieee80211_ext_chansw_ie data;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} ext_chan_switch;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 element_id;\n\t\t\t\t\tu8 length;\n\t\t\t\t\tstruct ieee80211_msrment_ie msr_elem;\n\t\t\t\t} measurement;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\t__le16 capab;\n\t\t\t\t\t__le16 timeout;\n\t\t\t\t\t__le16 start_seq_num;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} addba_req;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\t__le16 status;\n\t\t\t\t\t__le16 capab;\n\t\t\t\t\t__le16 timeout;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} addba_resp;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\t__le16 params;\n\t\t\t\t\t__le16 reason_code;\n\t\t\t\t} __attribute__((packed)) delba;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} self_prot;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} mesh_action;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action;\n\t\t\t\t\tu8 trans_id[2];\n\t\t\t\t} sa_query;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action;\n\t\t\t\t\tu8 smps_control;\n\t\t\t\t} ht_smps;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 chanwidth;\n\t\t\t\t} ht_notify_cw;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\t__le16 capability;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} tdls_discover_resp;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 operating_mode;\n\t\t\t\t} vht_opmode_notif;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 membership[8];\n\t\t\t\t\tu8 position[16];\n\t\t\t\t} vht_group_notif;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 tpc_elem_id;\n\t\t\t\t\tu8 tpc_elem_length;\n\t\t\t\t\tstruct ieee80211_tpc_report_ie tpc;\n\t\t\t\t} tpc_report;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 follow_up;\n\t\t\t\t\tu8 tod[6];\n\t\t\t\t\tu8 toa[6];\n\t\t\t\t\t__le16 tod_error;\n\t\t\t\t\t__le16 toa_error;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} __attribute__((packed)) ftm;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} s1g;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 follow_up;\n\t\t\t\t\tu32 tod;\n\t\t\t\t\tu32 toa;\n\t\t\t\t\tu8 max_tod_error;\n\t\t\t\t\tu8 max_toa_error;\n\t\t\t\t} __attribute__((packed)) wnm_timing_msr;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} ttlm_req;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\t__le16 status_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} ttlm_res;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t} ttlm_tear_down;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} ml_reconf_req;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 count;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} ml_reconf_resp;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} epcs;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 control;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} eml_omn;\n\t\t\t} u;\n\t\t} action;\n\t\tstruct {\n\t\t\tstruct {} __empty_body;\n\t\t\tu8 body[0];\n\t\t};\n\t} u;\n};\n\nstruct ieee80211_mle_basic_common_info {\n\tu8 len;\n\tu8 mld_mac_addr[6];\n\tu8 variable[0];\n};\n\nstruct ieee80211_mle_per_sta_profile {\n\t__le16 control;\n\tu8 sta_info_len;\n\tu8 variable[0];\n} __attribute__((packed));\n\nstruct ieee80211_mmie {\n\tu8 element_id;\n\tu8 length;\n\t__le16 key_id;\n\tu8 sequence_number[6];\n\tu8 mic[8];\n};\n\nstruct ieee80211_mmie_16 {\n\tu8 element_id;\n\tu8 length;\n\t__le16 key_id;\n\tu8 sequence_number[6];\n\tu8 mic[16];\n};\n\nstruct ieee80211_mmie_var {\n\tu8 element_id;\n\tu8 length;\n\t__le16 key_id;\n\tu8 sequence_number[6];\n\tu8 mic[0];\n};\n\nstruct ieee80211_mu_edca_param_set {\n\tu8 mu_qos_info;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_be;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_bk;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_vi;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_vo;\n};\n\nstruct ieee80211_multi_link_elem {\n\t__le16 control;\n\tu8 variable[0];\n};\n\nstruct ieee80211_multiple_bssid_configuration {\n\tu8 bssid_count;\n\tu8 profile_periodicity;\n};\n\nstruct ieee80211_neg_ttlm {\n\tu16 downlink[8];\n\tu16 uplink[8];\n\tbool valid;\n};\n\nstruct ieee80211_neighbor_ap_info {\n\tu8 tbtt_info_hdr;\n\tu8 tbtt_info_len;\n\tu8 op_class;\n\tu8 channel;\n};\n\nstruct ieee80211_noa_data {\n\tu32 next_tsf;\n\tbool has_next_tsf;\n\tu8 absent;\n\tu8 count[4];\n\tstruct {\n\t\tu32 start;\n\t\tu32 duration;\n\t\tu32 interval;\n\t} desc[4];\n};\n\nstruct ieee80211_tx_control;\n\nstruct ieee80211_scan_ies;\n\nstruct link_station_info;\n\nstruct ieee80211_prep_tx_info;\n\nstruct ieee80211_vif_chanctx_switch;\n\nstruct inet6_dev;\n\nstruct ieee80211_tdls_ch_sw_params;\n\nstruct ieee80211_txq;\n\nstruct ieee80211_twt_setup;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct ieee80211_ops {\n\tvoid (*tx)(struct ieee80211_hw *, struct ieee80211_tx_control *, struct sk_buff *);\n\tint (*start)(struct ieee80211_hw *);\n\tvoid (*stop)(struct ieee80211_hw *, bool);\n\tint (*suspend)(struct ieee80211_hw *, struct cfg80211_wowlan *);\n\tint (*resume)(struct ieee80211_hw *);\n\tvoid (*set_wakeup)(struct ieee80211_hw *, bool);\n\tint (*add_interface)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*change_interface)(struct ieee80211_hw *, struct ieee80211_vif *, enum nl80211_iftype, bool);\n\tvoid (*remove_interface)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*config)(struct ieee80211_hw *, int, u32);\n\tvoid (*bss_info_changed)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *, u64);\n\tvoid (*vif_cfg_changed)(struct ieee80211_hw *, struct ieee80211_vif *, u64);\n\tvoid (*link_info_changed)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *, u64);\n\tint (*start_ap)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *);\n\tvoid (*stop_ap)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *);\n\tu64 (*prepare_multicast)(struct ieee80211_hw *, struct netdev_hw_addr_list *);\n\tvoid (*configure_filter)(struct ieee80211_hw *, unsigned int, unsigned int *, u64);\n\tvoid (*config_iface_filter)(struct ieee80211_hw *, struct ieee80211_vif *, unsigned int, unsigned int);\n\tint (*set_tim)(struct ieee80211_hw *, struct ieee80211_sta *, bool);\n\tint (*set_key)(struct ieee80211_hw *, enum set_key_cmd, struct ieee80211_vif *, struct ieee80211_sta *, struct ieee80211_key_conf *);\n\tvoid (*update_tkip_key)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_key_conf *, struct ieee80211_sta *, u32, u16 *);\n\tvoid (*set_rekey_data)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_gtk_rekey_data *);\n\tvoid (*set_default_unicast_key)(struct ieee80211_hw *, struct ieee80211_vif *, int);\n\tint (*hw_scan)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_scan_request *);\n\tvoid (*cancel_hw_scan)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*sched_scan_start)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_sched_scan_request *, struct ieee80211_scan_ies *);\n\tint (*sched_scan_stop)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*sw_scan_start)(struct ieee80211_hw *, struct ieee80211_vif *, const u8 *);\n\tvoid (*sw_scan_complete)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*get_stats)(struct ieee80211_hw *, struct ieee80211_low_level_stats *);\n\tvoid (*get_key_seq)(struct ieee80211_hw *, struct ieee80211_key_conf *, struct ieee80211_key_seq *);\n\tint (*set_frag_threshold)(struct ieee80211_hw *, int, u32);\n\tint (*set_rts_threshold)(struct ieee80211_hw *, int, u32);\n\tint (*sta_add)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tint (*sta_remove)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*sta_notify)(struct ieee80211_hw *, struct ieee80211_vif *, enum sta_notify_cmd, struct ieee80211_sta *);\n\tint (*sta_set_txpwr)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tint (*sta_state)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, enum ieee80211_sta_state, enum ieee80211_sta_state);\n\tvoid (*sta_pre_rcu_remove)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*link_sta_rc_update)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_link_sta *, u32);\n\tvoid (*sta_rate_tbl_update)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*sta_statistics)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, struct station_info *);\n\tint (*conf_tx)(struct ieee80211_hw *, struct ieee80211_vif *, unsigned int, u16, const struct ieee80211_tx_queue_params *);\n\tu64 (*get_tsf)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*set_tsf)(struct ieee80211_hw *, struct ieee80211_vif *, u64);\n\tvoid (*offset_tsf)(struct ieee80211_hw *, struct ieee80211_vif *, s64);\n\tvoid (*reset_tsf)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*tx_last_beacon)(struct ieee80211_hw *);\n\tvoid (*link_sta_statistics)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_link_sta *, struct link_station_info *);\n\tint (*ampdu_action)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_ampdu_params *);\n\tint (*get_survey)(struct ieee80211_hw *, int, struct survey_info *);\n\tvoid (*rfkill_poll)(struct ieee80211_hw *);\n\tvoid (*set_coverage_class)(struct ieee80211_hw *, int, s16);\n\tvoid (*flush)(struct ieee80211_hw *, struct ieee80211_vif *, u32, bool);\n\tvoid (*flush_sta)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel_switch *);\n\tint (*set_antenna)(struct ieee80211_hw *, int, u32, u32);\n\tint (*get_antenna)(struct ieee80211_hw *, int, u32 *, u32 *);\n\tint (*remain_on_channel)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel *, int, enum ieee80211_roc_type);\n\tint (*cancel_remain_on_channel)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*set_ringparam)(struct ieee80211_hw *, u32, u32);\n\tvoid (*get_ringparam)(struct ieee80211_hw *, u32 *, u32 *, u32 *, u32 *);\n\tbool (*tx_frames_pending)(struct ieee80211_hw *);\n\tint (*set_bitrate_mask)(struct ieee80211_hw *, struct ieee80211_vif *, const struct cfg80211_bitrate_mask *);\n\tvoid (*event_callback)(struct ieee80211_hw *, struct ieee80211_vif *, const struct ieee80211_event *);\n\tvoid (*allow_buffered_frames)(struct ieee80211_hw *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\tvoid (*release_buffered_frames)(struct ieee80211_hw *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\tint (*get_et_sset_count)(struct ieee80211_hw *, struct ieee80211_vif *, int);\n\tvoid (*get_et_stats)(struct ieee80211_hw *, struct ieee80211_vif *, struct ethtool_stats *, u64 *);\n\tvoid (*get_et_strings)(struct ieee80211_hw *, struct ieee80211_vif *, u32, u8 *);\n\tvoid (*mgd_prepare_tx)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_prep_tx_info *);\n\tvoid (*mgd_complete_tx)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_prep_tx_info *);\n\tvoid (*mgd_protect_tdls_discover)(struct ieee80211_hw *, struct ieee80211_vif *, unsigned int);\n\tint (*add_chanctx)(struct ieee80211_hw *, struct ieee80211_chanctx_conf *);\n\tvoid (*remove_chanctx)(struct ieee80211_hw *, struct ieee80211_chanctx_conf *);\n\tvoid (*change_chanctx)(struct ieee80211_hw *, struct ieee80211_chanctx_conf *, u32);\n\tint (*assign_vif_chanctx)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *, struct ieee80211_chanctx_conf *);\n\tvoid (*unassign_vif_chanctx)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *, struct ieee80211_chanctx_conf *);\n\tint (*switch_vif_chanctx)(struct ieee80211_hw *, struct ieee80211_vif_chanctx_switch *, int, enum ieee80211_chanctx_switch_mode);\n\tvoid (*reconfig_complete)(struct ieee80211_hw *, enum ieee80211_reconfig_type);\n\tvoid (*ipv6_addr_change)(struct ieee80211_hw *, struct ieee80211_vif *, struct inet6_dev *);\n\tvoid (*channel_switch_beacon)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_chan_def *);\n\tint (*pre_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel_switch *);\n\tint (*post_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *);\n\tvoid (*abort_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *);\n\tvoid (*channel_switch_rx_beacon)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel_switch *);\n\tint (*join_ibss)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*leave_ibss)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tu32 (*get_expected_throughput)(struct ieee80211_hw *, struct ieee80211_sta *);\n\tint (*get_txpower)(struct ieee80211_hw *, struct ieee80211_vif *, unsigned int, int *);\n\tint (*tdls_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, u8, struct cfg80211_chan_def *, struct sk_buff *, u32);\n\tvoid (*tdls_cancel_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*tdls_recv_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_tdls_ch_sw_params *);\n\tvoid (*wake_tx_queue)(struct ieee80211_hw *, struct ieee80211_txq *);\n\tvoid (*sync_rx_queues)(struct ieee80211_hw *);\n\tint (*start_nan)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_nan_conf *);\n\tint (*stop_nan)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*nan_change_conf)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_nan_conf *, u32);\n\tint (*add_nan_func)(struct ieee80211_hw *, struct ieee80211_vif *, const struct cfg80211_nan_func *);\n\tvoid (*del_nan_func)(struct ieee80211_hw *, struct ieee80211_vif *, u8);\n\tbool (*can_aggregate_in_amsdu)(struct ieee80211_hw *, struct sk_buff *, struct sk_buff *);\n\tint (*get_ftm_responder_stats)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_ftm_responder_stats *);\n\tint (*start_pmsr)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_pmsr_request *);\n\tvoid (*abort_pmsr)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_pmsr_request *);\n\tint (*set_tid_config)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, struct cfg80211_tid_config *);\n\tint (*reset_tid_config)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, u8);\n\tvoid (*update_vif_offload)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*sta_set_4addr)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, bool);\n\tint (*set_sar_specs)(struct ieee80211_hw *, const struct cfg80211_sar_specs *);\n\tvoid (*sta_set_decap_offload)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, bool);\n\tvoid (*add_twt_setup)(struct ieee80211_hw *, struct ieee80211_sta *, struct ieee80211_twt_setup *);\n\tvoid (*twt_teardown_request)(struct ieee80211_hw *, struct ieee80211_sta *, u8);\n\tint (*set_radar_background)(struct ieee80211_hw *, struct cfg80211_chan_def *);\n\tint (*net_fill_forward_path)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, struct net_device_path_ctx *, struct net_device_path *);\n\tbool (*can_activate_links)(struct ieee80211_hw *, struct ieee80211_vif *, u16);\n\tint (*change_vif_links)(struct ieee80211_hw *, struct ieee80211_vif *, u16, u16, struct ieee80211_bss_conf **);\n\tint (*change_sta_links)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, u16, u16);\n\tint (*set_hw_timestamp)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_set_hw_timestamp *);\n\tint (*net_setup_tc)(struct ieee80211_hw *, struct ieee80211_vif *, struct net_device *, enum tc_setup_type, void *);\n\tenum ieee80211_neg_ttlm_res (*can_neg_ttlm)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_neg_ttlm *);\n\tvoid (*prep_add_interface)(struct ieee80211_hw *, enum nl80211_iftype);\n\tint (*set_eml_op_mode)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, struct ieee80211_eml_params *);\n};\n\nstruct ieee80211_power_rule {\n\tu32 max_antenna_gain;\n\tu32 max_eirp;\n};\n\nstruct ieee80211_prep_tx_info {\n\tu16 duration;\n\tu16 subtype;\n\tu8 success: 1;\n\tu8 was_assoc: 1;\n\tint link_id;\n};\n\nstruct ieee80211_pspoll {\n\t__le16 frame_control;\n\t__le16 aid;\n\tu8 bssid[6];\n\tu8 ta[6];\n};\n\nstruct ieee80211_qos_hdr {\n\t__le16 frame_control;\n\t__le16 duration_id;\n\tu8 addr1[6];\n\tu8 addr2[6];\n\tu8 addr3[6];\n\t__le16 seq_ctrl;\n\t__le16 qos_ctrl;\n};\n\nstruct ieee80211_qos_hdr_4addr {\n\t__le16 frame_control;\n\t__le16 duration_id;\n\tu8 addr1[6];\n\tu8 addr2[6];\n\tu8 addr3[6];\n\t__le16 seq_ctrl;\n\tu8 addr4[6];\n\t__le16 qos_ctrl;\n};\n\nstruct ieee80211_radiotap_he {\n\t__le16 data1;\n\t__le16 data2;\n\t__le16 data3;\n\t__le16 data4;\n\t__le16 data5;\n\t__le16 data6;\n};\n\nstruct ieee80211_radiotap_he_mu {\n\t__le16 flags1;\n\t__le16 flags2;\n\tu8 ru_ch1[4];\n\tu8 ru_ch2[4];\n};\n\nstruct ieee80211_radiotap_header_fixed {\n\tuint8_t it_version;\n\tuint8_t it_pad;\n\t__le16 it_len;\n\t__le32 it_present;\n};\n\nstruct ieee80211_radiotap_header {\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t it_version;\n\t\t\tuint8_t it_pad;\n\t\t\t__le16 it_len;\n\t\t\t__le32 it_present;\n\t\t};\n\t\tstruct ieee80211_radiotap_header_fixed hdr;\n\t};\n\t__le32 it_optional[0];\n};\n\nstruct ieee80211_radiotap_vendor_namespaces;\n\nstruct ieee80211_radiotap_namespace;\n\nstruct ieee80211_radiotap_iterator {\n\tstruct ieee80211_radiotap_header *_rtheader;\n\tconst struct ieee80211_radiotap_vendor_namespaces *_vns;\n\tconst struct ieee80211_radiotap_namespace *current_namespace;\n\tunsigned char *_arg;\n\tunsigned char *_next_ns_data;\n\t__le32 *_next_bitmap;\n\tunsigned char *this_arg;\n\tint this_arg_index;\n\tint this_arg_size;\n\tint is_radiotap_ns;\n\tint _max_length;\n\tint _arg_index;\n\tuint32_t _bitmap_shifter;\n\tint _reset_on_ext;\n};\n\nstruct ieee80211_radiotap_lsig {\n\t__le16 data1;\n\t__le16 data2;\n};\n\nstruct radiotap_align_size;\n\nstruct ieee80211_radiotap_namespace {\n\tconst struct radiotap_align_size *align_size;\n\tint n_bits;\n\tuint32_t oui;\n\tuint8_t subns;\n};\n\nstruct ieee80211_radiotap_vendor_namespaces {\n\tconst struct ieee80211_radiotap_namespace *ns;\n\tint n_ns;\n};\n\nstruct ieee80211_radiotap_vht {\n\t__le16 known;\n\tu8 flags;\n\tu8 bandwidth;\n\tu8 mcs_nss[4];\n\tu8 coding;\n\tu8 group_id;\n\t__le16 partial_aid;\n};\n\nstruct ieee80211_rann_ie {\n\tu8 rann_flags;\n\tu8 rann_hopcount;\n\tu8 rann_ttl;\n\tu8 rann_addr[6];\n\t__le32 rann_seq;\n\t__le32 rann_interval;\n\t__le32 rann_metric;\n} __attribute__((packed));\n\nstruct ieee80211_rate {\n\tu32 flags;\n\tu16 bitrate;\n\tu16 hw_value;\n\tu16 hw_value_short;\n};\n\nstruct ieee80211_rate_status {\n\tstruct rate_info rate_idx;\n\tu8 try_count;\n\tu8 tx_power_idx;\n};\n\nstruct ieee80211_wmm_ac {\n\tu16 cw_min;\n\tu16 cw_max;\n\tu16 cot;\n\tu8 aifsn;\n};\n\nstruct ieee80211_wmm_rule {\n\tstruct ieee80211_wmm_ac client[4];\n\tstruct ieee80211_wmm_ac ap[4];\n};\n\nstruct ieee80211_reg_rule {\n\tstruct ieee80211_freq_range freq_range;\n\tstruct ieee80211_power_rule power_rule;\n\tstruct ieee80211_wmm_rule wmm_rule;\n\tu32 flags;\n\tu32 dfs_cac_ms;\n\tbool has_wmm;\n\ts8 psd;\n};\n\nstruct ieee80211_regdomain {\n\tstruct callback_head callback_head;\n\tu32 n_reg_rules;\n\tchar alpha2[3];\n\tenum nl80211_dfs_regions dfs_region;\n\tstruct ieee80211_reg_rule reg_rules[0];\n};\n\nstruct ieee80211_rnr_mld_params {\n\tu8 mld_id;\n\t__le16 params;\n} __attribute__((packed));\n\nstruct ieee80211_roc_work {\n\tstruct list_head list;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct ieee80211_channel *chan;\n\tbool started;\n\tbool abort;\n\tbool hw_begun;\n\tbool notified;\n\tbool on_channel;\n\tlong unsigned int start_time;\n\tu32 duration;\n\tu32 req_duration;\n\tstruct sk_buff *frame;\n\tu64 cookie;\n\tu64 mgmt_tx_cookie;\n\tenum ieee80211_roc_type type;\n};\n\nstruct ieee80211_rts {\n\t__le16 frame_control;\n\t__le16 duration;\n\tu8 ra[6];\n\tu8 ta[6];\n};\n\nstruct link_sta_info;\n\nstruct ieee80211_rx_data {\n\tstruct list_head *list;\n\tstruct sk_buff *skb;\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct ieee80211_link_data *link;\n\tstruct sta_info *sta;\n\tstruct link_sta_info *link_sta;\n\tstruct ieee80211_key *key;\n\tunsigned int flags;\n\tint seqno_idx;\n\tint security_idx;\n\tint link_id;\n\tunion {\n\t\tstruct {\n\t\t\tu32 iv32;\n\t\t\tu16 iv16;\n\t\t} tkip;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} ccm_gcm;\n\t};\n};\n\nstruct ieee80211_rx_status {\n\tu64 mactime;\n\tunion {\n\t\tu64 boottime_ns;\n\t\tktime_t ack_tx_hwtstamp;\n\t};\n\tu32 device_timestamp;\n\tu32 ampdu_reference;\n\tu32 flag;\n\tu16 freq: 13;\n\tu16 freq_offset: 1;\n\tu8 enc_flags;\n\tu8 encoding: 3;\n\tu8 bw: 4;\n\tunion {\n\t\tstruct {\n\t\t\tu8 he_ru: 3;\n\t\t\tu8 he_gi: 2;\n\t\t\tu8 he_dcm: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu8 ru: 4;\n\t\t\tu8 gi: 2;\n\t\t} eht;\n\t\tstruct {\n\t\t\tu8 ru: 4;\n\t\t\tu8 gi: 2;\n\t\t\tu8 elr: 1;\n\t\t\tu8 im: 1;\n\t\t} uhr;\n\t};\n\tu8 rate_idx;\n\tu8 nss;\n\tu8 rx_flags;\n\tu8 band;\n\tu8 antenna;\n\ts8 signal;\n\tu8 chains;\n\ts8 chain_signal[4];\n\tu8 zero_length_psdu_type;\n\tu8 link_valid: 1;\n\tu8 link_id: 4;\n};\n\nstruct ieee80211_s1g_bcn_compat_ie {\n\t__le16 compat_info;\n\t__le16 beacon_int;\n\t__le32 tsf_completion;\n};\n\nstruct ieee80211_s1g_oper_ie {\n\tu8 ch_width;\n\tu8 oper_class;\n\tu8 primary_ch;\n\tu8 oper_ch;\n\t__le16 basic_mcs_nss;\n};\n\nstruct ieee80211_sband_iftype_data {\n\tu16 types_mask;\n\tstruct ieee80211_sta_he_cap he_cap;\n\tstruct ieee80211_he_6ghz_capa he_6ghz_capa;\n\tstruct ieee80211_sta_eht_cap eht_cap;\n\tstruct ieee80211_sta_uhr_cap uhr_cap;\n\tlong: 0;\n\tstruct {\n\t\tconst u8 *data;\n\t\tunsigned int len;\n\t} vendor_elems;\n} __attribute__((packed));\n\nstruct ieee80211_scan_ies {\n\tconst u8 *ies[6];\n\tsize_t len[6];\n\tconst u8 *common_ies;\n\tsize_t common_ie_len;\n};\n\nstruct ieee80211_scan_request {\n\tstruct ieee80211_scan_ies ies;\n\tstruct cfg80211_scan_request req;\n};\n\nstruct ieee80211_sec_chan_offs_ie {\n\tu8 sec_chan_offs;\n};\n\nstruct ieee80211_sta_rates;\n\nstruct ieee80211_sta {\n\tu8 addr[6];\n\tu16 aid;\n\tu16 max_rx_aggregation_subframes;\n\tbool wme;\n\tu8 uapsd_queues;\n\tu8 max_sp;\n\tstruct ieee80211_sta_rates *rates;\n\tbool tdls;\n\tbool tdls_initiator;\n\tbool mfp;\n\tbool mlo;\n\tbool spp_amsdu;\n\tu8 max_amsdu_subframes;\n\tu16 eml_cap;\n\tstruct ieee80211_sta_aggregates *cur;\n\tbool support_p2p_ps;\n\tstruct ieee80211_txq *txq[17];\n\tu16 valid_links;\n\tbool epp_peer;\n\tlong: 0;\n\tstruct ieee80211_link_sta deflink;\n\tstruct ieee80211_link_sta *link[15];\n\tu8 drv_priv[0];\n};\n\nstruct ieee80211_sta_rates {\n\tstruct callback_head callback_head;\n\tstruct {\n\t\ts8 idx;\n\t\tu8 count;\n\t\tu8 count_cts;\n\t\tu8 count_rts;\n\t\tu16 flags;\n\t} rate[4];\n};\n\nstruct ieee80211_sta_removed_link_stats {\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu64 rx_bytes;\n\tu64 tx_bytes;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tu32 beacon_loss_count;\n\tu32 expected_throughput;\n\tstruct {\n\t\tu64 rx_msdu;\n\t\tu64 tx_msdu;\n\t\tu64 tx_msdu_retries;\n\t\tu64 tx_msdu_failed;\n\t} pertid_stats;\n};\n\nstruct ieee80211_sta_rx_stats {\n\tlong unsigned int packets;\n\tlong unsigned int last_rx;\n\tlong unsigned int num_duplicates;\n\tlong unsigned int fragments;\n\tlong unsigned int dropped;\n\tint last_signal;\n\tu8 chains;\n\ts8 chain_signal_last[4];\n\tu32 last_rate;\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t bytes;\n\tu64_stats_t msdu[17];\n};\n\nstruct wireless_dev {\n\tstruct wiphy *wiphy;\n\tenum nl80211_iftype iftype;\n\tstruct list_head list;\n\tstruct net_device *netdev;\n\tu32 identifier;\n\tstruct list_head mgmt_registrations;\n\tu8 mgmt_registrations_need_update: 1;\n\tbool use_4addr;\n\tbool is_running;\n\tbool registered;\n\tbool registering;\n\tshort: 0;\n\tu8 address[6];\n\tstruct cfg80211_conn *conn;\n\tstruct cfg80211_cached_keys *connect_keys;\n\tenum ieee80211_bss_type conn_bss_type;\n\tu32 conn_owner_nlportid;\n\tstruct work_struct disconnect_wk;\n\tu8 disconnect_bssid[6];\n\tstruct list_head event_list;\n\tspinlock_t event_lock;\n\tu8 connected: 1;\n\tbool ps;\n\tint ps_timeout;\n\tu32 ap_unexpected_nlportid;\n\tu32 owner_nlportid;\n\tbool nl_owner_dead;\n\tstruct wiphy_work cqm_rssi_work;\n\tstruct cfg80211_cqm_config *cqm_config;\n\tstruct list_head pmsr_list;\n\tspinlock_t pmsr_lock;\n\tstruct work_struct pmsr_free_wk;\n\tlong unsigned int unprot_beacon_reported;\n\tunion {\n\t\tstruct {\n\t\t\tu8 connected_addr[6];\n\t\t\tu8 ssid[32];\n\t\t\tu8 ssid_len;\n\t\t\tlong: 0;\n\t\t} client;\n\t\tstruct {\n\t\t\tint beacon_interval;\n\t\t\tstruct cfg80211_chan_def preset_chandef;\n\t\t\tstruct cfg80211_chan_def chandef;\n\t\t\tu8 id[32];\n\t\t\tu8 id_len;\n\t\t\tu8 id_up_len;\n\t\t} mesh;\n\t\tstruct {\n\t\t\tstruct cfg80211_chan_def preset_chandef;\n\t\t\tu8 ssid[32];\n\t\t\tu8 ssid_len;\n\t\t} ap;\n\t\tstruct {\n\t\t\tstruct cfg80211_internal_bss *current_bss;\n\t\t\tstruct cfg80211_chan_def chandef;\n\t\t\tint beacon_interval;\n\t\t\tu8 ssid[32];\n\t\t\tu8 ssid_len;\n\t\t} ibss;\n\t\tstruct {\n\t\t\tstruct cfg80211_chan_def chandef;\n\t\t} ocb;\n\t\tstruct {\n\t\t\tu8 cluster_id[6];\n\t\t} nan;\n\t} u;\n\tstruct {\n\t\tu8 addr[6];\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tunsigned int beacon_interval;\n\t\t\t\tstruct cfg80211_chan_def chandef;\n\t\t\t} ap;\n\t\t\tstruct {\n\t\t\t\tstruct cfg80211_internal_bss *current_bss;\n\t\t\t} client;\n\t\t};\n\t\tbool cac_started;\n\t\tlong unsigned int cac_start_time;\n\t\tunsigned int cac_time_ms;\n\t} links[15];\n\tu16 valid_links;\n\tu32 radio_mask;\n};\n\nstruct ieee80211_vif_cfg {\n\tbool assoc;\n\tbool ibss_joined;\n\tbool ibss_creator;\n\tbool ps;\n\tu16 aid;\n\tu16 eml_cap;\n\tu16 eml_med_sync_delay;\n\tu16 mld_capa_op;\n\t__be32 arp_addr_list[4];\n\tint arp_addr_cnt;\n\tu8 ssid[32];\n\tsize_t ssid_len;\n\tbool s1g;\n\tbool idle;\n\tu8 ap_addr[6];\n};\n\nstruct ieee80211_vif {\n\tenum nl80211_iftype type;\n\tstruct ieee80211_vif_cfg cfg;\n\tstruct ieee80211_bss_conf bss_conf;\n\tstruct ieee80211_bss_conf *link_conf[15];\n\tu16 valid_links;\n\tu16 active_links;\n\tu16 dormant_links;\n\tu16 suspended_links;\n\tstruct ieee80211_neg_ttlm neg_ttlm;\n\tu8 addr[6];\n\tbool addr_valid;\n\tbool p2p;\n\tu8 cab_queue;\n\tu8 hw_queue[4];\n\tstruct ieee80211_txq *txq;\n\tnetdev_features_t netdev_features;\n\tu32 driver_flags;\n\tu32 offload_flags;\n\tbool probe_req_reg;\n\tbool rx_mcast_action_reg;\n\tlong: 0;\n\tu8 drv_priv[0];\n};\n\nstruct mac80211_qos_map;\n\nstruct ieee80211_sub_if_data {\n\tstruct list_head list;\n\tstruct wireless_dev wdev;\n\tstruct list_head key_list;\n\tint crypto_tx_tailroom_needed_cnt;\n\tint crypto_tx_tailroom_pending_dec;\n\tstruct wiphy_delayed_work dec_tailroom_needed_wk;\n\tstruct net_device *dev;\n\tstruct ieee80211_local *local;\n\tunsigned int flags;\n\tlong unsigned int state;\n\tchar name[16];\n\tstruct ieee80211_fragment_cache frags;\n\tu16 noack_map;\n\tu8 wmm_acm;\n\tstruct ieee80211_key *keys[4];\n\tstruct ieee80211_key *default_unicast_key;\n\tu16 sequence_number;\n\tu16 mld_mcast_seq;\n\t__be16 control_port_protocol;\n\tbool control_port_no_encrypt;\n\tbool control_port_no_preauth;\n\tbool control_port_over_nl80211;\n\tatomic_t num_tx_queued;\n\tstruct mac80211_qos_map *qos_map;\n\tstruct wiphy_work work;\n\tstruct sk_buff_head skb_queue;\n\tstruct sk_buff_head status_queue;\n\tstruct ieee80211_if_ap *bss;\n\tu32 rc_rateidx_mask[6];\n\tbool rc_has_mcs_mask[6];\n\tu8 rc_rateidx_mcs_mask[60];\n\tbool rc_has_vht_mcs_mask[6];\n\tu16 rc_rateidx_vht_mcs_mask[48];\n\tu32 beacon_rateidx_mask[6];\n\tbool beacon_rate_set;\n\tunion {\n\t\tstruct ieee80211_if_ap ap;\n\t\tstruct ieee80211_if_vlan vlan;\n\t\tstruct ieee80211_if_managed mgd;\n\t\tstruct ieee80211_if_ibss ibss;\n\t\tstruct ieee80211_if_mesh mesh;\n\t\tstruct ieee80211_if_ocb ocb;\n\t\tstruct ieee80211_if_mntr mntr;\n\t\tstruct ieee80211_if_nan nan;\n\t} u;\n\tstruct ieee80211_link_data deflink;\n\tstruct ieee80211_link_data *link[15];\n\tstruct wiphy_work activate_links_work;\n\tu16 desired_active_links;\n\tu16 restart_active_links;\n\tu32 tx_handlers_drop;\n\tstruct ieee80211_vif vif;\n};\n\nstruct ieee80211_supported_band {\n\tstruct ieee80211_channel *channels;\n\tstruct ieee80211_rate *bitrates;\n\tenum nl80211_band band;\n\tint n_channels;\n\tint n_bitrates;\n\tstruct ieee80211_sta_ht_cap ht_cap;\n\tstruct ieee80211_sta_vht_cap vht_cap;\n\tstruct ieee80211_sta_s1g_cap s1g_cap;\n\tstruct ieee80211_edmg edmg_cap;\n\tu16 n_iftype_data;\n\tconst struct ieee80211_sband_iftype_data *iftype_data;\n};\n\nstruct ieee80211_tbtt_info_7_8_9 {\n\tu8 tbtt_offset;\n\tu8 bssid[6];\n\tu8 bss_params;\n\ts8 psd_20;\n};\n\nstruct ieee80211_tbtt_info_ge_11 {\n\tu8 tbtt_offset;\n\tu8 bssid[6];\n\t__le32 short_ssid;\n\tu8 bss_params;\n\ts8 psd_20;\n\tstruct ieee80211_rnr_mld_params mld_params;\n\tstruct ieee80211_enh_crit_upd enh_crit_upd;\n} __attribute__((packed));\n\nstruct ieee80211_tdls_ch_sw_params {\n\tstruct ieee80211_sta *sta;\n\tstruct cfg80211_chan_def *chandef;\n\tu8 action_code;\n\tu32 status;\n\tu32 timestamp;\n\tu16 switch_time;\n\tu16 switch_timeout;\n\tstruct sk_buff *tmpl_skb;\n\tu32 ch_sw_tm_ie;\n};\n\nstruct ieee80211_tdls_data {\n\tu8 da[6];\n\tu8 sa[6];\n\t__be16 ether_type;\n\tu8 payload_type;\n\tu8 category;\n\tu8 action_code;\n\tunion {\n\t\tstruct {\n\t\t\tu8 dialog_token;\n\t\t\t__le16 capability;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) setup_req;\n\t\tstruct {\n\t\t\t__le16 status_code;\n\t\t\tu8 dialog_token;\n\t\t\t__le16 capability;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) setup_resp;\n\t\tstruct {\n\t\t\t__le16 status_code;\n\t\t\tu8 dialog_token;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) setup_cfm;\n\t\tstruct {\n\t\t\t__le16 reason_code;\n\t\t\tu8 variable[0];\n\t\t} teardown;\n\t\tstruct {\n\t\t\tu8 dialog_token;\n\t\t\tu8 variable[0];\n\t\t} discover_req;\n\t\tstruct {\n\t\t\tu8 target_channel;\n\t\t\tu8 oper_class;\n\t\t\tu8 variable[0];\n\t\t} chan_switch_req;\n\t\tstruct {\n\t\t\t__le16 status_code;\n\t\t\tu8 variable[0];\n\t\t} chan_switch_resp;\n\t} u;\n};\n\nstruct ieee80211_tdls_lnkie {\n\tu8 ie_type;\n\tu8 ie_len;\n\tu8 bssid[6];\n\tu8 init_sta[6];\n\tu8 resp_sta[6];\n};\n\nstruct ieee80211_tim_ie {\n\tu8 dtim_count;\n\tu8 dtim_period;\n\tu8 bitmap_ctrl;\n\tunion {\n\t\tu8 required_octet;\n\t\tstruct {\n\t\t\tstruct {} __empty_virtual_map;\n\t\t\tu8 virtual_map[0];\n\t\t};\n\t};\n};\n\nstruct ieee80211_timeout_interval_ie {\n\tu8 type;\n\t__le32 value;\n} __attribute__((packed));\n\nstruct ieee80211_tpt_blink {\n\tint throughput;\n\tint blink_time;\n};\n\nstruct ieee80211_ttlm_elem {\n\tu8 control;\n\tu8 optional[0];\n};\n\nstruct ieee80211_twt_params {\n\t__le16 req_type;\n\t__le64 twt;\n\tu8 min_twt_dur;\n\t__le16 mantissa;\n\tu8 channel;\n} __attribute__((packed));\n\nstruct ieee80211_twt_setup {\n\tu8 dialog_token;\n\tu8 element_id;\n\tu8 length;\n\tu8 control;\n\tu8 params[0];\n};\n\nstruct ieee80211_tx_control {\n\tstruct ieee80211_sta *sta;\n};\n\nstruct ieee80211_tx_rate {\n\ts8 idx;\n\tu16 count: 5;\n\tu16 flags: 11;\n} __attribute__((packed));\n\nstruct ieee80211_tx_data {\n\tstruct sk_buff *skb;\n\tstruct sk_buff_head skbs;\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct sta_info *sta;\n\tstruct ieee80211_key *key;\n\tstruct ieee80211_tx_rate rate;\n\tunsigned int flags;\n};\n\nstruct ieee80211_tx_info {\n\tu32 flags;\n\tu32 band: 3;\n\tu32 status_data_idr: 1;\n\tu32 status_data: 13;\n\tu32 hw_queue: 4;\n\tu32 tx_time_est: 10;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct ieee80211_tx_rate rates[4];\n\t\t\t\t\ts8 rts_cts_rate_idx;\n\t\t\t\t\tu8 use_rts: 1;\n\t\t\t\t\tu8 use_cts_prot: 1;\n\t\t\t\t\tu8 short_preamble: 1;\n\t\t\t\t\tu8 skip_table: 1;\n\t\t\t\t\tu8 antennas: 2;\n\t\t\t\t};\n\t\t\t\tlong unsigned int jiffies;\n\t\t\t};\n\t\t\tstruct ieee80211_vif *vif;\n\t\t\tstruct ieee80211_key_conf *hw_key;\n\t\t\tu32 flags;\n\t\t\tcodel_time_t enqueue_time;\n\t\t} control;\n\t\tstruct {\n\t\t\tu64 cookie;\n\t\t} ack;\n\t\tstruct {\n\t\t\tstruct ieee80211_tx_rate rates[4];\n\t\t\ts32 ack_signal;\n\t\t\tu8 ampdu_ack_len;\n\t\t\tu8 ampdu_len;\n\t\t\tu8 antenna;\n\t\t\tu8 pad;\n\t\t\tu16 tx_time;\n\t\t\tu8 flags;\n\t\t\tu8 pad2;\n\t\t\tvoid *status_driver_data[2];\n\t\t} status;\n\t\tstruct {\n\t\t\tstruct ieee80211_tx_rate driver_rates[4];\n\t\t\tu8 pad[4];\n\t\t\tvoid *rate_driver_data[3];\n\t\t};\n\t\tvoid *driver_data[5];\n\t};\n};\n\nstruct ieee80211_tx_pwr_env {\n\tu8 info;\n\tu8 variable[0];\n};\n\nstruct ieee80211_tx_rate_control {\n\tstruct ieee80211_hw *hw;\n\tstruct ieee80211_supported_band *sband;\n\tstruct ieee80211_bss_conf *bss_conf;\n\tstruct sk_buff *skb;\n\tstruct ieee80211_tx_rate reported_rate;\n\tbool rts;\n\tbool short_preamble;\n\tu32 rate_idx_mask;\n\tu8 *rate_idx_mcs_mask;\n\tbool bss;\n};\n\nstruct ieee80211_tx_status {\n\tstruct ieee80211_sta *sta;\n\tstruct ieee80211_tx_info *info;\n\tstruct sk_buff *skb;\n\tstruct ieee80211_rate_status *rates;\n\tktime_t ack_hwtstamp;\n\tu8 n_rates;\n\tstruct list_head *free_list;\n};\n\nstruct ieee80211_txq {\n\tstruct ieee80211_vif *vif;\n\tstruct ieee80211_sta *sta;\n\tu8 tid;\n\tu8 ac;\n\tlong: 0;\n\tu8 drv_priv[0];\n};\n\nstruct ieee80211_txq_params {\n\tenum nl80211_ac ac;\n\tu16 txop;\n\tu16 cwmin;\n\tu16 cwmax;\n\tu8 aifs;\n\tint link_id;\n};\n\nstruct ieee80211_txrx_stypes {\n\tu16 tx;\n\tu16 rx;\n};\n\nstruct ieee80211_uhr_cap {\n\tstruct ieee80211_uhr_cap_mac mac;\n\tu8 variable[0];\n};\n\nstruct ieee80211_uhr_npca_info {\n\t__le32 params;\n\t__le16 dis_subch_bmap[0];\n};\n\nstruct ieee80211_uhr_operation {\n\t__le16 params;\n\tu8 basic_mcs_nss_set[4];\n\tu8 variable[0];\n};\n\nstruct ieee80211_vht_operation {\n\tu8 chan_width;\n\tu8 center_freq_seg0_idx;\n\tu8 center_freq_seg1_idx;\n\t__le16 basic_mcs_set;\n} __attribute__((packed));\n\nstruct ieee80211_vif_chanctx_switch {\n\tstruct ieee80211_vif *vif;\n\tstruct ieee80211_bss_conf *link_conf;\n\tstruct ieee80211_chanctx_conf *old_ctx;\n\tstruct ieee80211_chanctx_conf *new_ctx;\n};\n\nstruct ieee80211_wide_bw_chansw_ie {\n\tu8 new_channel_width;\n\tu8 new_center_freq_seg0;\n\tu8 new_center_freq_seg1;\n};\n\nstruct ieee80211_wmm_ac_param {\n\tu8 aci_aifsn;\n\tu8 cw;\n\t__le16 txop_limit;\n};\n\nstruct ieee80211_wmm_param_ie {\n\tu8 element_id;\n\tu8 len;\n\tu8 oui[3];\n\tu8 oui_type;\n\tu8 oui_subtype;\n\tu8 version;\n\tu8 qos_info;\n\tu8 reserved;\n\tstruct ieee80211_wmm_ac_param ac[4];\n};\n\nstruct ieee80211s_hdr {\n\tu8 flags;\n\tu8 ttl;\n\t__le32 seqnum;\n\tu8 eaddr1[6];\n\tu8 eaddr2[6];\n} __attribute__((packed));\n\nstruct if6_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tint offset;\n};\n\nstruct if_dqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n};\n\nstruct if_dqinfo {\n\t__u64 dqi_bgrace;\n\t__u64 dqi_igrace;\n\t__u32 dqi_flags;\n\t__u32 dqi_valid;\n};\n\nstruct if_nextdqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n\t__u32 dqb_id;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa6_config {\n\tconst struct in6_addr *pfx;\n\tunsigned int plen;\n\tu8 ifa_proto;\n\tconst struct in6_addr *peer_pfx;\n\tu32 rt_priority;\n\tu32 ifa_flags;\n\tu32 preferred_lft;\n\tu32 valid_lft;\n\tu16 scope;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct iface_combination_params {\n\tint radio_idx;\n\tint num_different_channels;\n\tu8 radar_detect;\n\tint iftype_num[13];\n\tu32 new_beacon_int;\n};\n\nstruct ifaddrlblmsg {\n\t__u8 ifal_family;\n\t__u8 __ifal_reserved;\n\t__u8 ifal_prefixlen;\n\t__u8 ifal_flags;\n\t__u32 ifal_index;\n\t__u32 ifal_seq;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_cacheinfo {\n\t__u32 max_reasm_len;\n\t__u32 tstamp;\n\t__u32 reachable_time;\n\t__u32 retrans_time;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct igmp6_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct igmp6_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *im;\n};\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpmsg {\n\t__u32 unused1;\n\t__u32 unused2;\n\tunsigned char im_msgtype;\n\tunsigned char im_mbz;\n\tunsigned char im_vif;\n\tunsigned char im_vif_hi;\n\tstruct in_addr im_src;\n\tstruct in_addr im_dst;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 qrv: 3;\n\t__u8 suppress: 1;\n\t__u8 resv: 4;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct ignore_entry {\n\tu16 vid;\n\tu16 pid;\n\tu16 bcdmin;\n\tu16 bcdmax;\n};\n\nstruct ilk_wm_maximums {\n\tu16 pri;\n\tu16 spr;\n\tu16 cur;\n\tu16 fbc;\n};\n\nstruct ilk_wm_values {\n\tu32 wm_pipe[3];\n\tu32 wm_lp[3];\n\tu32 wm_lp_spr[3];\n\tbool enable_fbc_wm;\n\tenum intel_ddb_partitioning partitioning;\n};\n\nstruct imc_uncore_pci_dev {\n\t__u32 pci_id;\n\tstruct pci_driver *driver;\n};\n\nstruct in6_flowlabel_req {\n\tstruct in6_addr flr_dst;\n\t__be32 flr_label;\n\t__u8 flr_action;\n\t__u8 flr_share;\n\t__u16 flr_flags;\n\t__u16 flr_expires;\n\t__u16 flr_linger;\n\t__u32 __flr_pad;\n};\n\nstruct in6_ifreq {\n\tstruct in6_addr ifr6_addr;\n\t__u32 ifr6_prefixlen;\n\tint ifr6_ifindex;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\t__u32 rtmsg_type;\n\t__u16 rtmsg_dst_len;\n\t__u16 rtmsg_src_len;\n\t__u32 rtmsg_metric;\n\tlong unsigned int rtmsg_info;\n\t__u32 rtmsg_flags;\n\tint rtmsg_ifindex;\n};\n\nstruct in6_validator_info {\n\tstruct in6_addr i6vi_addr;\n\tstruct inet6_dev *i6vi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[1];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv6_txoptions;\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n\tu8 dontfrag: 1;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n\tenum addr_type_t type;\n\tbool force_rt_scope_universe;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n\tu32 secret;\n};\n\nunion inet_addr {\n\t__be32 ip;\n\tstruct in6_addr in6;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tshort unsigned int addr_type;\n\tstruct in6_addr v6_rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct sock_cgroup_data {\n\tstruct cgroup *cgroup;\n\tu32 classid;\n\tu16 prioidx;\n};\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct xfrm_policy;\n\nstruct sock_reuseport;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\tstruct xfrm_policy *sk_policy[2];\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tnetdev_features_t sk_route_caps;\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tktime_t sk_stamp;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tvoid *sk_security;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n\tstruct inet6_cork base6;\n};\n\nstruct ipv6_pinfo;\n\nstruct ipv6_fl_socklist;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct proto_ops;\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\nstruct inform_bss_update_data {\n\tstruct ieee80211_rx_status *rx_status;\n\tbool beacon;\n};\n\nstruct x86_mapping_info;\n\nstruct init_pgtable_data {\n\tstruct x86_mapping_info *info;\n\tpgd_t *level4p;\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inode_security_struct {\n\tstruct inode *inode;\n\tstruct list_head list;\n\tu32 task_sid;\n\tu32 sid;\n\tu16 sclass;\n\tunsigned char initialized;\n\tspinlock_t lock;\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[12];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[1];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[2];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[12];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[12];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[1];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[2];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_event_compat {\n\tcompat_ulong_t sec;\n\tcompat_ulong_t usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_led {\n\tstruct led_classdev cdev;\n\tstruct input_handle *handle;\n\tunsigned int code;\n};\n\nstruct input_leds {\n\tstruct input_handle handle;\n\tunsigned int num_leds;\n\tstruct input_led leds[0];\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_res {\n\tu16 w;\n\tu16 h;\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insert_entries {\n\tstruct i915_address_space *vm;\n\tstruct i915_vma_resource *vma_res;\n\tunsigned int pat_index;\n\tu32 flags;\n};\n\nstruct insert_page {\n\tstruct i915_address_space *vm;\n\tdma_addr_t addr;\n\tu64 offset;\n\tunsigned int pat_index;\n};\n\nstruct insert_pte_data {\n\tu64 offset;\n};\n\nstruct insn_field {\n\tunion {\n\t\tinsn_value_t value;\n\t\tinsn_byte_t bytes[4];\n\t};\n\tunsigned char got;\n\tunsigned char nbytes;\n};\n\nstruct insn {\n\tstruct insn_field prefixes;\n\tstruct insn_field rex_prefix;\n\tunion {\n\t\tstruct insn_field vex_prefix;\n\t\tstruct insn_field xop_prefix;\n\t};\n\tstruct insn_field opcode;\n\tstruct insn_field modrm;\n\tstruct insn_field sib;\n\tstruct insn_field displacement;\n\tunion {\n\t\tstruct insn_field immediate;\n\t\tstruct insn_field moffset1;\n\t\tstruct insn_field immediate1;\n\t};\n\tunion {\n\t\tstruct insn_field moffset2;\n\t\tstruct insn_field immediate2;\n\t};\n\tint emulate_prefix_size;\n\tinsn_attr_t attr;\n\tunsigned char opnd_bytes;\n\tunsigned char addr_bytes;\n\tunsigned char length;\n\tunsigned char x86_64;\n\tconst insn_byte_t *kaddr;\n\tconst insn_byte_t *end_kaddr;\n\tconst insn_byte_t *next_byte;\n};\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nunion intcapxt {\n\tu64 capxt;\n\tstruct {\n\t\tu64 reserved_0: 2;\n\t\tu64 dest_mode_logical: 1;\n\t\tu64 reserved_1: 5;\n\t\tu64 destid_0_23: 24;\n\t\tu64 vector: 8;\n\t\tu64 reserved_2: 16;\n\t\tu64 destid_24_31: 8;\n\t};\n};\n\nstruct intel_agp_driver_description {\n\tunsigned int chip_id;\n\tchar *name;\n\tconst struct agp_bridge_driver *driver;\n};\n\nstruct intel_dpll_state {\n\tu8 pipe_mask;\n\tstruct intel_dpll_hw_state hw_state;\n};\n\nstruct intel_dp_tunnel_inherited_state;\n\nstruct intel_global_objs_state;\n\nstruct intel_atomic_state {\n\tstruct drm_atomic_state base;\n\tstruct ref_tracker *wakeref;\n\tstruct intel_global_objs_state *global_objs;\n\tint num_global_objs;\n\tbool internal;\n\tbool dpll_set;\n\tbool modeset;\n\tstruct intel_dpll_state dpll_state[9];\n\tstruct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;\n\tbool skip_intermediate_wm;\n\tbool rps_interactive;\n\tstruct work_struct cleanup_work;\n};\n\nstruct intel_encoder;\n\nstruct intel_audio_state {\n\tstruct intel_encoder *encoder;\n\tu8 eld[128];\n};\n\nstruct intel_audio {\n\tstruct i915_audio_component *component;\n\tbool component_registered;\n\tstruct mutex mutex;\n\tint power_refcount;\n\tu32 freq_cntrl;\n\tstruct intel_audio_state state[7];\n\tstruct {\n\t\tstruct platform_device *platdev;\n\t\tint irq;\n\t} lpe;\n};\n\nstruct intel_crtc_state;\n\nstruct intel_audio_funcs {\n\tvoid (*audio_codec_enable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_codec_disable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_codec_get_config)(struct intel_encoder *, struct intel_crtc_state *);\n};\n\nstruct intel_bios_encoder_data {\n\tstruct intel_display *display;\n\tstruct child_device_config child;\n\tstruct dsc_compression_parameters_entry *dsc;\n\tstruct list_head node;\n};\n\nstruct intel_breadcrumbs {\n\tstruct kref ref;\n\tatomic_t active;\n\tspinlock_t signalers_lock;\n\tstruct list_head signalers;\n\tstruct llist_head signaled_requests;\n\tatomic_t signaler_active;\n\tspinlock_t irq_lock;\n\tstruct irq_work irq_work;\n\tunsigned int irq_enabled;\n\tintel_wakeref_t irq_armed;\n\tintel_engine_mask_t engine_mask;\n\tstruct intel_engine_cs *irq_engine;\n\tbool (*irq_enable)(struct intel_breadcrumbs *);\n\tvoid (*irq_disable)(struct intel_breadcrumbs *);\n};\n\nstruct intel_bw_info {\n\tunsigned int deratedbw[8];\n\tunsigned int psf_bw[3];\n\tunsigned int peakbw[8];\n\tu8 num_qgv_points;\n\tu8 num_psf_gv_points;\n\tu8 num_planes;\n};\n\nstruct intel_global_obj;\n\nstruct intel_global_commit;\n\nstruct intel_global_state {\n\tstruct intel_global_obj *obj;\n\tstruct intel_atomic_state *state;\n\tstruct intel_global_commit *commit;\n\tstruct kref ref;\n\tbool changed;\n\tbool serialized;\n};\n\nstruct intel_bw_state {\n\tstruct intel_global_state base;\n\tu8 pipe_sagv_reject;\n\tu8 active_pipes;\n\tu16 qgv_point_peakbw;\n\tu16 qgv_points_mask;\n\tunsigned int data_rate[4];\n\tu8 num_active_planes[4];\n};\n\nstruct scaler_filter_coeff {\n\tu16 sign;\n\tu16 exp;\n\tu16 mantissa;\n};\n\nstruct intel_casf {\n\tstruct scaler_filter_coeff coeff[7];\n\tu8 strength;\n\tu8 win_size;\n\tbool casf_enable;\n};\n\nstruct intel_cdclk_config {\n\tunsigned int cdclk;\n\tunsigned int vco;\n\tunsigned int ref;\n\tunsigned int bypass;\n\tu8 voltage_level;\n\tbool joined_mbus;\n};\n\nstruct intel_cdclk_funcs {\n\tvoid (*get_cdclk)(struct intel_display *, struct intel_cdclk_config *);\n\tvoid (*set_cdclk)(struct intel_display *, const struct intel_cdclk_config *, enum pipe);\n\tint (*modeset_calc_cdclk)(struct intel_atomic_state *);\n\tu8 (*calc_voltage_level)(int);\n};\n\nstruct intel_cdclk_state {\n\tstruct intel_global_state base;\n\tstruct intel_cdclk_config logical;\n\tstruct intel_cdclk_config actual;\n\tint dbuf_bw_min_cdclk;\n\tint min_cdclk[4];\n\tu8 min_voltage_level[4];\n\tenum pipe pipe;\n\tint force_min_cdclk;\n\tu8 enabled_pipes;\n\tu8 active_pipes;\n\tbool disable_pipes;\n};\n\nstruct intel_cdclk_vals {\n\tu32 cdclk;\n\tu16 refclk;\n\tu16 waveform;\n\tu8 ratio;\n};\n\nstruct intel_cmtg_config {\n\tbool cmtg_a_enable;\n\tbool cmtg_b_enable;\n\tbool trans_a_secondary;\n\tbool trans_b_secondary;\n};\n\nstruct intel_crtc;\n\nstruct intel_dsb;\n\nstruct intel_plane_state;\n\nstruct intel_color_funcs {\n\tint (*color_check)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*color_commit_noarm)(struct intel_dsb *, const struct intel_crtc_state *);\n\tvoid (*color_commit_arm)(struct intel_dsb *, const struct intel_crtc_state *);\n\tvoid (*color_post_update)(const struct intel_crtc_state *);\n\tvoid (*load_luts)(const struct intel_crtc_state *);\n\tvoid (*read_luts)(struct intel_crtc_state *);\n\tbool (*lut_equal)(const struct intel_crtc_state *, const struct drm_property_blob *, const struct drm_property_blob *, bool);\n\tvoid (*read_csc)(struct intel_crtc_state *);\n\tvoid (*get_config)(struct intel_crtc_state *);\n\tvoid (*load_plane_csc_matrix)(struct intel_dsb *, const struct intel_plane_state *);\n\tvoid (*load_plane_luts)(struct intel_dsb *, const struct intel_plane_state *);\n};\n\nstruct intel_colorop {\n\tstruct drm_colorop base;\n\tenum intel_color_block id;\n};\n\nstruct pwm_state {\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tbool usage_power;\n};\n\nstruct intel_pps_delays {\n\tu16 power_up;\n\tu16 backlight_on;\n\tu16 backlight_off;\n\tu16 power_down;\n\tu16 power_cycle;\n};\n\nstruct intel_vbt_panel_data {\n\tstruct drm_display_mode *lfp_vbt_mode;\n\tstruct drm_display_mode *sdvo_lvds_vbt_mode;\n\tint panel_type;\n\tunsigned int lvds_dither: 1;\n\tunsigned int bios_lvds_val;\n\tbool vrr;\n\tu8 seamless_drrs_min_refresh_rate;\n\tenum drrs_type drrs_type;\n\tstruct {\n\t\tint max_link_rate;\n\t\tint rate;\n\t\tint lanes;\n\t\tint preemphasis;\n\t\tint vswing;\n\t\tint bpp;\n\t\tstruct intel_pps_delays pps;\n\t\tu8 drrs_msa_timing_delay;\n\t\tbool low_vswing;\n\t\tbool hobl;\n\t\tbool dsc_disable;\n\t} edp;\n\tstruct {\n\t\tbool enable;\n\t\tbool full_link;\n\t\tbool require_aux_wakeup;\n\t\tint idle_frames;\n\t\tint tp1_wakeup_time_us;\n\t\tint tp2_tp3_wakeup_time_us;\n\t\tint psr2_tp2_tp3_wakeup_time_us;\n\t} psr;\n\tstruct {\n\t\tu16 pwm_freq_hz;\n\t\tu16 brightness_precision_bits;\n\t\tu16 hdr_dpcd_refresh_timeout;\n\t\tbool present;\n\t\tbool active_low_pwm;\n\t\tu8 min_brightness;\n\t\ts8 controller;\n\t\tenum intel_backlight_type type;\n\t} backlight;\n\tstruct {\n\t\tu16 panel_id;\n\t\tstruct mipi_config *config;\n\t\tstruct mipi_pps_data *pps;\n\t\tu16 bl_ports;\n\t\tu16 cabc_ports;\n\t\tu8 seq_version;\n\t\tu32 size;\n\t\tu8 *data;\n\t\tconst u8 *sequence[12];\n\t\tu8 *deassert_seq;\n\t\tenum drm_panel_orientation orientation;\n\t} dsi;\n};\n\nstruct pwm_device;\n\nstruct intel_panel_bl_funcs;\n\nstruct intel_connector;\n\nstruct intel_panel {\n\tstruct drm_panel *base;\n\tconst struct drm_edid *fixed_edid;\n\tstruct list_head fixed_modes;\n\tstruct {\n\t\tbool present;\n\t\tu32 level;\n\t\tu32 min;\n\t\tu32 max;\n\t\tbool enabled;\n\t\tbool combination_mode;\n\t\tbool active_low_pwm;\n\t\tbool alternate_pwm_increment;\n\t\tu32 pwm_level_min;\n\t\tu32 pwm_level_max;\n\t\tbool pwm_enabled;\n\t\tbool util_pin_active_low;\n\t\tu8 controller;\n\t\tstruct pwm_device *pwm;\n\t\tstruct pwm_state pwm_state;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct drm_edp_backlight_info info;\n\t\t\t\tbool luminance_control_support;\n\t\t\t} vesa;\n\t\t\tstruct {\n\t\t\t\tbool sdr_uses_aux;\n\t\t\t\tbool supports_2084_decode;\n\t\t\t\tbool supports_2020_gamut;\n\t\t\t\tbool supports_segmented_backlight;\n\t\t\t\tbool supports_sdp_colorimetry;\n\t\t\t\tbool supports_tone_mapping;\n\t\t\t} intel_cap;\n\t\t} edp;\n\t\tstruct backlight_device *device;\n\t\tconst struct intel_panel_bl_funcs *funcs;\n\t\tconst struct intel_panel_bl_funcs *pwm_funcs;\n\t\tvoid (*power)(struct intel_connector *, bool);\n\t} backlight;\n\tstruct intel_vbt_panel_data vbt;\n};\n\nstruct intel_hdcp_shim;\n\nstruct intel_hdcp {\n\tconst struct intel_hdcp_shim *shim;\n\tstruct mutex mutex;\n\tu64 value;\n\tstruct delayed_work check_work;\n\tstruct work_struct prop_work;\n\tbool hdcp_encrypted;\n\tbool hdcp2_supported;\n\tbool hdcp2_encrypted;\n\tu8 content_type;\n\tbool is_paired;\n\tbool is_repeater;\n\tu32 seq_num_v;\n\tu32 seq_num_m;\n\twait_queue_head_t cp_irq_queue;\n\tatomic_t cp_irq_count;\n\tint cp_irq_count_cached;\n\tenum transcoder cpu_transcoder;\n\tenum transcoder stream_transcoder;\n\tbool force_hdcp14;\n};\n\nstruct intel_dp;\n\nstruct intel_connector {\n\tstruct drm_connector base;\n\tstruct intel_encoder *encoder;\n\tu32 acpi_device_id;\n\tbool (*get_hw_state)(struct intel_connector *);\n\tvoid (*sync_state)(struct intel_connector *, const struct intel_crtc_state *);\n\tstruct intel_panel panel;\n\tconst struct drm_edid *detect_edid;\n\tint hotplug_retries;\n\tu8 polled;\n\tint force_joined_pipes;\n\tstruct {\n\t\tstruct drm_dp_aux *dsc_decompression_aux;\n\t\tu8 dsc_dpcd[16];\n\t\tu8 fec_capability;\n\t\tu8 dsc_hblank_expansion_quirk: 1;\n\t\tu8 dsc_throughput_quirk: 1;\n\t\tu8 dsc_decompression_enabled: 1;\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tint rgb_yuv444;\n\t\t\t\tint yuv422_420;\n\t\t\t} overall_throughput;\n\t\t\tint max_line_width;\n\t\t} dsc_branch_caps;\n\t\tstruct {\n\t\t\tu8 dpcd[7];\n\t\t\tbool support;\n\t\t\tbool su_support;\n\t\t\tenum intel_panel_replay_dsc_support dsc_support;\n\t\t\tu16 su_w_granularity;\n\t\t\tu16 su_y_granularity;\n\t\t} panel_replay_caps;\n\t\tstruct {\n\t\t\tu8 dpcd[2];\n\t\t\tbool support;\n\t\t\tbool su_support;\n\t\t\tu16 su_w_granularity;\n\t\t\tu16 su_y_granularity;\n\t\t\tu8 sync_latency;\n\t\t} psr_caps;\n\t} dp;\n\tstruct {\n\t\tstruct drm_dp_mst_port *port;\n\t\tstruct intel_dp *dp;\n\t} mst;\n\tstruct {\n\t\tint force_bpp_x16;\n\t} link;\n\tstruct work_struct modeset_retry_work;\n\tstruct intel_hdcp hdcp;\n};\n\nstruct intel_context_ops {\n\tlong unsigned int flags;\n\tint (*alloc)(struct intel_context *);\n\tvoid (*revoke)(struct intel_context *, struct i915_request *, unsigned int);\n\tvoid (*close)(struct intel_context *);\n\tint (*pre_pin)(struct intel_context *, struct i915_gem_ww_ctx *, void **);\n\tint (*pin)(struct intel_context *, void *);\n\tvoid (*unpin)(struct intel_context *);\n\tvoid (*post_unpin)(struct intel_context *);\n\tvoid (*cancel_request)(struct intel_context *, struct i915_request *);\n\tvoid (*enter)(struct intel_context *);\n\tvoid (*exit)(struct intel_context *);\n\tvoid (*sched_disable)(struct intel_context *);\n\tvoid (*update_stats)(struct intel_context *);\n\tvoid (*reset)(struct intel_context *);\n\tvoid (*destroy)(struct kref *);\n\tstruct intel_context * (*create_virtual)(struct intel_engine_cs **, unsigned int, long unsigned int);\n\tstruct intel_context * (*create_parallel)(struct intel_engine_cs **, unsigned int, unsigned int);\n\tstruct intel_engine_cs * (*get_sibling)(struct intel_engine_cs *, unsigned int);\n};\n\nstruct intel_ddi_buf_trans;\n\nstruct intel_encoder {\n\tstruct drm_encoder base;\n\tenum intel_output_type type;\n\tenum port port;\n\tu16 cloneable;\n\tu8 pipe_mask;\n\tstruct delayed_work link_check_work;\n\tvoid (*link_check)(struct intel_encoder *);\n\tenum intel_hotplug_state (*hotplug)(struct intel_encoder *, struct intel_connector *);\n\tenum intel_output_type (*compute_output_type)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tint (*compute_config)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tint (*compute_config_late)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tvoid (*pre_pll_enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*pre_enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*post_disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*post_pll_disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*update_pipe)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_enable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_disable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tbool (*get_hw_state)(struct intel_encoder *, enum pipe *);\n\tvoid (*get_config)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*sync_state)(struct intel_encoder *, const struct intel_crtc_state *);\n\tbool (*initial_fastset_check)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*get_power_domains)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*suspend)(struct intel_encoder *);\n\tvoid (*suspend_complete)(struct intel_encoder *);\n\tvoid (*shutdown)(struct intel_encoder *);\n\tvoid (*shutdown_complete)(struct intel_encoder *);\n\tvoid (*enable_clock)(struct intel_encoder *, const struct intel_crtc_state *);\n\tvoid (*disable_clock)(struct intel_encoder *);\n\tbool (*is_clock_enabled)(struct intel_encoder *);\n\tenum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *, const struct intel_crtc_state *);\n\tconst struct intel_ddi_buf_trans * (*get_buf_trans)(struct intel_encoder *, const struct intel_crtc_state *, int *);\n\tvoid (*set_signal_levels)(struct intel_encoder *, const struct intel_crtc_state *);\n\tenum hpd_pin hpd_pin;\n\tenum intel_display_power_domain power_domain;\n\tconst struct intel_bios_encoder_data *devdata;\n};\n\nstruct intel_crt {\n\tstruct intel_encoder base;\n\tbool force_hotplug_required;\n\ti915_reg_t adpa_reg;\n};\n\nstruct intel_display_power_domain_set {\n\tstruct intel_power_domain_mask mask;\n};\n\nstruct intel_flipq {\n\tu32 start_mmioaddr;\n\tenum intel_flipq_id flipq_id;\n\tu8 tail;\n};\n\nstruct intel_wm_level {\n\tbool enable;\n\tu32 pri_val;\n\tu32 spr_val;\n\tu32 cur_val;\n\tu32 fbc_val;\n};\n\nstruct intel_pipe_wm {\n\tstruct intel_wm_level wm[5];\n\tbool fbc_wm_enabled;\n\tbool pipe_enabled;\n\tbool sprites_enabled;\n\tbool sprites_scaled;\n};\n\nstruct vlv_wm_state {\n\tstruct g4x_pipe_wm wm[3];\n\tstruct g4x_sr_wm sr[3];\n\tu8 num_levels;\n\tbool cxsr;\n};\n\nstruct intel_link_m_n {\n\tu32 tu;\n\tu32 data_m;\n\tu32 data_n;\n\tu32 link_m;\n\tu32 link_n;\n};\n\nstruct intel_pipe_crc {\n\tspinlock_t lock;\n\tint skipped;\n\tenum intel_pipe_crc_source source;\n};\n\nstruct intel_overlay;\n\nstruct intel_crtc {\n\tstruct drm_crtc base;\n\tenum pipe pipe;\n\tbool active;\n\tu8 plane_ids_mask;\n\tu8 mode_flags;\n\tu16 vmax_vblank_start;\n\tstruct intel_display_power_domain_set enabled_power_domains;\n\tstruct intel_display_power_domain_set hw_readout_power_domains;\n\tstruct intel_overlay *overlay;\n\tstruct intel_crtc_state *config;\n\tstruct drm_pending_vblank_event *flip_done_event;\n\tstruct drm_pending_vblank_event *dsb_event;\n\tstruct drm_pending_vblank_event *flipq_event;\n\tbool cpu_fifo_underrun_disabled;\n\tbool pch_fifo_underrun_disabled;\n\tstruct intel_flipq flipq[5];\n\tstruct {\n\t\tunion {\n\t\t\tstruct intel_pipe_wm ilk;\n\t\t\tstruct vlv_wm_state vlv;\n\t\t\tstruct g4x_wm_state g4x;\n\t\t} active;\n\t} wm;\n\tstruct {\n\t\tstruct mutex mutex;\n\t\tstruct delayed_work work;\n\t\tenum drrs_refresh_rate refresh_rate;\n\t\tunsigned int frontbuffer_bits;\n\t\tunsigned int busy_frontbuffer_bits;\n\t\tenum transcoder cpu_transcoder;\n\t\tstruct intel_link_m_n m_n;\n\t\tstruct intel_link_m_n m2_n2;\n\t} drrs;\n\tstruct {\n\t\tu64 flip_count;\n\t} dc_balance;\n\tint scanline_offset;\n\tstruct {\n\t\tunsigned int start_vbl_count;\n\t\tktime_t start_vbl_time;\n\t\tint min_vbl;\n\t\tint max_vbl;\n\t\tint scanline_start;\n\t} debug;\n\tint num_scalers;\n\tstruct pm_qos_request vblank_pm_qos;\n\tstruct intel_pipe_crc pipe_crc;\n\tbool vblank_psr_notify;\n};\n\nstruct intel_scaler {\n\tu32 mode;\n\tbool in_use;\n\tint hscale;\n\tint vscale;\n};\n\nstruct intel_crtc_scaler_state {\n\tstruct intel_scaler scalers[2];\n\tunsigned int scaler_users;\n\tint scaler_id;\n};\n\nstruct intel_csc_matrix {\n\tu16 coeff[9];\n\tu16 preoff[3];\n\tu16 postoff[3];\n};\n\nstruct skl_wm_level {\n\tu16 min_ddb_alloc;\n\tu16 blocks;\n\tu8 lines;\n\tbool enable;\n\tbool ignore_lines;\n\tbool auto_min_alloc_wm_enable;\n\tbool can_sagv;\n};\n\nstruct skl_plane_wm {\n\tstruct skl_wm_level wm[8];\n\tstruct skl_wm_level uv_wm[8];\n\tstruct skl_wm_level trans_wm;\n\tstruct {\n\t\tstruct skl_wm_level wm0;\n\t\tstruct skl_wm_level trans_wm;\n\t} sagv;\n\tbool is_planar;\n};\n\nstruct skl_pipe_wm {\n\tstruct skl_plane_wm planes[8];\n\tbool use_sagv_wm;\n};\n\nstruct skl_ddb_entry {\n\tu16 start;\n\tu16 end;\n};\n\nstruct vlv_fifo_state {\n\tu16 plane[8];\n};\n\nstruct intel_crtc_wm_state {\n\tunion {\n\t\tstruct {\n\t\t\tstruct intel_pipe_wm intermediate;\n\t\t\tstruct intel_pipe_wm optimal;\n\t\t} ilk;\n\t\tstruct {\n\t\t\tstruct skl_pipe_wm raw;\n\t\t\tstruct skl_pipe_wm optimal;\n\t\t\tstruct skl_ddb_entry ddb;\n\t\t\tstruct skl_ddb_entry plane_ddb[8];\n\t\t\tstruct skl_ddb_entry plane_ddb_y[8];\n\t\t\tu16 plane_min_ddb[8];\n\t\t\tu16 plane_interim_ddb[8];\n\t\t} skl;\n\t\tstruct {\n\t\t\tstruct g4x_pipe_wm raw[3];\n\t\t\tstruct vlv_wm_state intermediate;\n\t\t\tstruct vlv_wm_state optimal;\n\t\t\tstruct vlv_fifo_state fifo_state;\n\t\t} vlv;\n\t\tstruct {\n\t\t\tstruct g4x_pipe_wm raw[3];\n\t\t\tstruct g4x_wm_state intermediate;\n\t\t\tstruct g4x_wm_state optimal;\n\t\t} g4x;\n\t};\n\tbool need_postvbl_update;\n};\n\nstruct intel_crtc_state {\n\tstruct drm_crtc_state uapi;\n\tstruct {\n\t\tbool active;\n\t\tbool enable;\n\t\tstruct drm_property_blob *degamma_lut;\n\t\tstruct drm_property_blob *gamma_lut;\n\t\tstruct drm_property_blob *ctm;\n\t\tstruct drm_display_mode mode;\n\t\tstruct drm_display_mode pipe_mode;\n\t\tstruct drm_display_mode adjusted_mode;\n\t\tenum drm_scaling_filter scaling_filter;\n\t\tstruct intel_casf casf_params;\n\t} hw;\n\tstruct drm_property_blob *pre_csc_lut;\n\tstruct drm_property_blob *post_csc_lut;\n\tstruct intel_csc_matrix csc;\n\tstruct intel_csc_matrix output_csc;\n\tlong unsigned int quirks;\n\tunsigned int fb_bits;\n\tbool update_pipe;\n\tbool update_m_n;\n\tbool update_lrr;\n\tbool disable_cxsr;\n\tbool update_wm_pre;\n\tbool update_wm_post;\n\tbool fifo_changed;\n\tbool preload_luts;\n\tbool inherited;\n\tbool do_async_flip;\n\tstruct drm_rect pipe_src;\n\tunsigned int pixel_rate;\n\tbool has_pch_encoder;\n\tbool has_infoframe;\n\tenum transcoder cpu_transcoder;\n\tbool limited_color_range;\n\tunsigned int output_types;\n\tbool has_hdmi_sink;\n\tbool has_audio;\n\tbool dither;\n\tbool dither_force_disable;\n\tbool clock_set;\n\tbool sdvo_tv_clock;\n\tbool bw_constrained;\n\tstruct dpll dpll;\n\tstruct intel_dpll *intel_dpll;\n\tstruct intel_dpll_hw_state dpll_hw_state;\n\tstruct icl_port_dpll icl_port_dplls[2];\n\tstruct {\n\t\tu32 ctrl;\n\t\tu32 div;\n\t} dsi_pll;\n\tint max_link_bpp_x16;\n\tint pipe_bpp;\n\tint min_hblank;\n\tstruct intel_link_m_n dp_m_n;\n\tstruct intel_link_m_n dp_m2_n2;\n\tbool has_drrs;\n\tbool has_psr;\n\tbool has_sel_update;\n\tbool enable_psr2_sel_fetch;\n\tbool enable_psr2_su_region_et;\n\tbool req_psr2_sdp_prior_scanline;\n\tbool has_panel_replay;\n\tbool link_off_after_as_sdp_when_pr_active;\n\tbool disable_as_sdp_when_pr_active;\n\tbool wm_level_disabled;\n\tbool pkg_c_latency_used;\n\tenum intel_panel_replay_dsc_support panel_replay_dsc_support;\n\tu32 dc3co_exitline;\n\tu16 su_y_granularity;\n\tu8 active_non_psr_pipes;\n\tconst char *no_psr_reason;\n\tint port_clock;\n\tunsigned int pixel_multiplier;\n\tu8 mode_flags;\n\tu8 lane_count;\n\tu8 lane_lat_optim_mask;\n\tu8 min_voltage_level;\n\tstruct {\n\t\tu32 control;\n\t\tu32 pgm_ratios;\n\t\tu32 lvds_border_bits;\n\t} gmch_pfit;\n\tstruct {\n\t\tstruct drm_rect dst;\n\t\tbool enabled;\n\t\tbool force_thru;\n\t} pch_pfit;\n\tint fdi_lanes;\n\tstruct intel_link_m_n fdi_m_n;\n\tbool ips_enabled;\n\tbool crc_enabled;\n\tbool double_wide;\n\tstruct intel_crtc_scaler_state scaler_state;\n\tenum pipe hsw_workaround_pipe;\n\tstruct intel_crtc_wm_state wm;\n\tint min_cdclk;\n\tint plane_min_cdclk[8];\n\tu32 data_rate[8];\n\tu32 data_rate_y[8];\n\tu64 rel_data_rate[8];\n\tu64 rel_data_rate_y[8];\n\tu32 gamma_mode;\n\tunion {\n\t\tu32 csc_mode;\n\t\tu32 cgm_mode;\n\t};\n\tu8 enabled_planes;\n\tu8 active_planes;\n\tu8 scaled_planes;\n\tu8 nv12_planes;\n\tu8 c8_planes;\n\tu8 update_planes;\n\tu8 async_flip_planes;\n\tu8 framestart_delay;\n\tu8 msa_timing_delay;\n\tstruct {\n\t\tu32 enable;\n\t\tu32 gcp;\n\t\tunion hdmi_infoframe avi;\n\t\tunion hdmi_infoframe spd;\n\t\tunion hdmi_infoframe hdmi;\n\t\tunion hdmi_infoframe drm;\n\t\tstruct drm_dp_vsc_sdp vsc;\n\t\tstruct drm_dp_as_sdp as_sdp;\n\t} infoframes;\n\tu8 eld[128];\n\tbool hdmi_scrambling;\n\tbool hdmi_high_tmds_clock_ratio;\n\tenum intel_output_format output_format;\n\tenum intel_output_format sink_format;\n\tbool gamma_enable;\n\tbool csc_enable;\n\tbool wgc_enable;\n\tu8 joiner_pipes;\n\tstruct {\n\t\tbool compression_enabled_on_link;\n\t\tbool compression_enable;\n\t\tint num_streams;\n\t\tu16 compressed_bpp_x16;\n\t\tu8 slice_count;\n\t\tstruct drm_dsc_config config;\n\t} dsc;\n\tstruct drm_dp_tunnel_ref dp_tunnel_ref;\n\tu16 linetime;\n\tu16 ips_linetime;\n\tbool enhanced_framing;\n\tbool fec_enable;\n\tbool sdp_split_enable;\n\tenum transcoder master_transcoder;\n\tu8 sync_mode_slaves_mask;\n\tenum transcoder mst_master_transcoder;\n\tstruct intel_dsb *dsb_color;\n\tstruct intel_dsb *dsb_commit;\n\tbool use_dsb;\n\tbool use_flipq;\n\tu32 psr2_man_track_ctl;\n\tu32 pipe_srcsz_early_tpt;\n\tstruct drm_rect psr2_su_area;\n\tstruct {\n\t\tbool enable;\n\t\tbool in_range;\n\t\tu8 pipeline_full;\n\t\tu16 flipline;\n\t\tu16 vmin;\n\t\tu16 vmax;\n\t\tu16 guardband;\n\t\tu32 vsync_end;\n\t\tu32 vsync_start;\n\t\tstruct {\n\t\t\tbool enable;\n\t\t\tu16 vmin;\n\t\t\tu16 vmax;\n\t\t\tu16 guardband;\n\t\t\tu16 slope;\n\t\t\tu16 max_increase;\n\t\t\tu16 max_decrease;\n\t\t\tu16 vblank_target;\n\t\t} dc_balance;\n\t} vrr;\n\tstruct {\n\t\tbool enable;\n\t\tu64 cmrr_n;\n\t\tu64 cmrr_m;\n\t} cmrr;\n\tstruct {\n\t\tbool enable;\n\t\tu8 link_count;\n\t\tu8 pixel_overlap;\n\t} splitter;\n\tstruct drm_vblank_work vblank_work;\n\tbool has_lobf;\n\tu16 set_context_latency;\n\tstruct {\n\t\tu8 io_wake_lines;\n\t\tu8 fast_wake_lines;\n\t\tu8 check_entry_lines;\n\t\tu8 aux_less_wake_lines;\n\t\tu8 silence_period_sym_clocks;\n\t\tu8 lfps_half_cycle_num_of_syms;\n\t} alpm_state;\n\tbool plane_color_changed;\n};\n\nstruct intel_css_header {\n\tu32 module_type;\n\tu32 header_len;\n\tu32 header_ver;\n\tu32 module_id;\n\tu32 module_vendor;\n\tu32 date;\n\tu32 size;\n\tu32 key_size;\n\tu32 modulus_size;\n\tu32 exponent_size;\n\tu32 reserved1[12];\n\tu32 version;\n\tu32 reserved2[8];\n\tu32 kernel_header_info;\n};\n\nstruct intel_dbuf_bw {\n\tunsigned int max_bw[4];\n\tu8 active_planes[4];\n};\n\nstruct intel_dbuf_bw_state {\n\tstruct intel_global_state base;\n\tstruct intel_dbuf_bw dbuf_bw[4];\n};\n\nstruct intel_dbuf_state {\n\tstruct intel_global_state base;\n\tstruct skl_ddb_entry ddb[4];\n\tunsigned int weight[4];\n\tu8 slices[4];\n\tu8 enabled_slices;\n\tu8 active_pipes;\n\tu8 mdclk_cdclk_ratio;\n\tbool joined_mbus;\n};\n\nunion intel_ddi_buf_trans_entry;\n\nstruct intel_ddi_buf_trans {\n\tconst union intel_ddi_buf_trans_entry *entries;\n\tu8 num_entries;\n\tu8 hdmi_default_entry;\n};\n\nstruct tgl_dkl_phy_ddi_buf_trans {\n\tu8 vswing;\n\tu8 preshoot;\n\tu8 de_emphasis;\n};\n\nstruct xe3plpd_lt_phy_buf_trans {\n\tu8 txswing;\n\tu8 txswing_level;\n\tu8 pre_cursor;\n\tu8 main_cursor;\n\tu8 post_cursor;\n};\n\nunion intel_ddi_buf_trans_entry {\n\tstruct hsw_ddi_buf_trans hsw;\n\tstruct bxt_ddi_buf_trans bxt;\n\tstruct icl_ddi_buf_trans icl;\n\tstruct icl_mg_phy_ddi_buf_trans mg;\n\tstruct tgl_dkl_phy_ddi_buf_trans dkl;\n\tstruct dg2_snps_phy_buf_trans snps;\n\tstruct xe3plpd_lt_phy_buf_trans lt;\n};\n\nstruct intel_ddi_port_domains {\n\tenum port port_start;\n\tenum port port_end;\n\tenum aux_ch aux_ch_start;\n\tenum aux_ch aux_ch_end;\n\tenum intel_display_power_domain ddi_lanes;\n\tenum intel_display_power_domain ddi_io;\n\tenum intel_display_power_domain aux_io;\n\tenum intel_display_power_domain aux_legacy_usbc;\n\tenum intel_display_power_domain aux_tbt;\n};\n\nstruct intel_digital_connector_state {\n\tstruct drm_connector_state base;\n\tenum hdmi_force_audio force_audio;\n\tint broadcast_rgb;\n};\n\nstruct intel_dp_link_config {\n\tu8 link_rate_idx: 6;\n\tu8 lane_count_exp: 2;\n};\n\nstruct intel_pps {\n\tint panel_power_up_delay;\n\tint panel_power_down_delay;\n\tint panel_power_cycle_delay;\n\tint backlight_on_delay;\n\tint backlight_off_delay;\n\tstruct delayed_work panel_vdd_work;\n\tbool want_panel_vdd;\n\tbool initializing;\n\tlong unsigned int last_power_on;\n\tlong unsigned int last_backlight_off;\n\tktime_t panel_power_off_time;\n\tstruct ref_tracker *vdd_wakeref;\n\tunion {\n\t\tenum pipe vlv_pps_pipe;\n\t\tint pps_idx;\n\t};\n\tenum pipe vlv_active_pipe;\n\tbool bxt_pps_reset;\n\tstruct intel_pps_delays pps_delays;\n\tstruct intel_pps_delays bios_pps_delays;\n};\n\nstruct intel_dp_compliance_data {\n\tlong unsigned int edid;\n\tu8 video_pattern;\n\tu16 hdisplay;\n\tu16 vdisplay;\n\tu8 bpc;\n\tstruct drm_dp_phy_test_params phytest;\n};\n\nstruct intel_dp_compliance {\n\tlong unsigned int test_type;\n\tstruct intel_dp_compliance_data test_data;\n\tbool test_active;\n\tint test_link_rate;\n\tu8 test_lane_count;\n};\n\nstruct intel_dp_pcon_frl {\n\tbool is_trained;\n\tint trained_rate_gbps;\n};\n\nstruct intel_psr {\n\tstruct mutex lock;\n\tu32 debug;\n\tbool sink_support;\n\tbool source_support;\n\tbool enabled;\n\tint pause_counter;\n\tenum pipe pipe;\n\tenum transcoder transcoder;\n\tbool active;\n\tstruct work_struct work;\n\tunsigned int busy_frontbuffer_bits;\n\tbool link_standby;\n\tbool sel_update_enabled;\n\tbool psr2_sel_fetch_enabled;\n\tbool psr2_sel_fetch_cff_enabled;\n\tbool su_region_et_enabled;\n\tbool req_psr2_sdp_prior_scanline;\n\tktime_t last_entry_attempt;\n\tktime_t last_exit;\n\tbool sink_not_reliable;\n\tbool irq_aux_error;\n\tu16 su_w_granularity;\n\tu16 su_y_granularity;\n\tbool source_panel_replay_support;\n\tbool sink_panel_replay_support;\n\tbool panel_replay_enabled;\n\tu32 dc3co_exitline;\n\tu32 dc3co_exit_delay;\n\tstruct delayed_work dc3co_work;\n\tu8 entry_setup_frames;\n\tu8 io_wake_lines;\n\tu8 fast_wake_lines;\n\tbool link_ok;\n\tbool pkg_c_latency_used;\n\tu8 active_non_psr_pipes;\n\tconst char *no_psr_reason;\n};\n\nstruct intel_dp_mst_encoder;\n\nstruct intel_dp {\n\ti915_reg_t output_reg;\n\tu32 DP;\n\tint link_rate;\n\tu8 lane_count;\n\tu8 sink_count;\n\tbool needs_modeset_retry;\n\tbool use_max_params;\n\tu8 dpcd[15];\n\tu8 downstream_ports[16];\n\tu8 edp_dpcd[5];\n\tu8 lttpr_common_caps[8];\n\tu8 lttpr_phy_caps[24];\n\tu8 pcon_dsc_dpcd[13];\n\tint num_source_rates;\n\tconst int *source_rates;\n\tint num_sink_rates;\n\tint sink_rates[8];\n\tbool use_rate_select;\n\tint max_sink_lane_count;\n\tint num_common_rates;\n\tint common_rates[8];\n\tstruct {\n\t\tbool active;\n\t\tint num_configs;\n\t\tstruct intel_dp_link_config configs[24];\n\t\tint max_lane_count;\n\t\tint max_rate;\n\t\tint mst_probed_lane_count;\n\t\tint mst_probed_rate;\n\t\tint force_lane_count;\n\t\tint force_rate;\n\t\tbool retrain_disabled;\n\t\tint seq_train_failures;\n\t\tint force_train_failure;\n\t\tbool force_retrain;\n\t} link;\n\tbool reset_link_params;\n\tint mso_link_count;\n\tint mso_pixel_overlap;\n\tstruct drm_dp_desc desc;\n\tstruct drm_dp_aux aux;\n\tu32 aux_busy_last_status;\n\tu8 train_set[4];\n\tstruct intel_pps pps;\n\tbool is_mst;\n\tenum drm_dp_mst_mode mst_detect;\n\tstruct intel_connector *attached_connector;\n\tbool as_sdp_supported;\n\tstruct drm_dp_tunnel *tunnel;\n\tbool tunnel_suspended: 1;\n\tstruct {\n\t\tstruct intel_dp_mst_encoder *stream_encoders[4];\n\t\tstruct drm_dp_mst_topology_mgr mgr;\n\t\tint active_streams;\n\t} mst;\n\tu32 (*get_aux_clock_divider)(struct intel_dp *, int);\n\tu32 (*get_aux_send_ctl)(struct intel_dp *, int, u32);\n\ti915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *);\n\ti915_reg_t (*aux_ch_data_reg)(struct intel_dp *, int);\n\tvoid (*prepare_link_retrain)(struct intel_dp *, const struct intel_crtc_state *);\n\tvoid (*set_link_train)(struct intel_dp *, const struct intel_crtc_state *, u8);\n\tvoid (*set_idle_link_train)(struct intel_dp *, const struct intel_crtc_state *);\n\tu8 (*preemph_max)(struct intel_dp *);\n\tu8 (*voltage_max)(struct intel_dp *, const struct intel_crtc_state *);\n\tstruct intel_dp_compliance compliance;\n\tstruct {\n\t\tint min_tmds_clock;\n\t\tint max_tmds_clock;\n\t\tint max_dotclock;\n\t\tint pcon_max_frl_bw;\n\t\tu8 max_bpc;\n\t\tbool ycbcr_444_to_420;\n\t\tbool ycbcr420_passthrough;\n\t\tbool rgb_to_ycbcr;\n\t} dfp;\n\tstruct pm_qos_request pm_qos;\n\tbool force_dsc_en;\n\tint force_dsc_output_format;\n\tbool force_dsc_fractional_bpp_en;\n\tint force_dsc_bpc;\n\tbool hobl_failed;\n\tbool hobl_active;\n\tstruct intel_dp_pcon_frl frl;\n\tstruct intel_psr psr;\n\tlong unsigned int last_oui_write;\n\tbool oui_valid;\n\tbool colorimetry_support;\n\tstruct {\n\t\tenum transcoder transcoder;\n\t\tstruct mutex lock;\n\t\tbool lobf_disable_debug;\n\t\tbool sink_alpm_error;\n\t} alpm;\n\tu8 alpm_dpcd;\n\tstruct {\n\t\tlong unsigned int mask;\n\t} quirks;\n};\n\nstruct cec_notifier;\n\nstruct intel_hdmi {\n\ti915_reg_t hdmi_reg;\n\tstruct {\n\t\tenum drm_dp_dual_mode_type type;\n\t\tint max_tmds_clock;\n\t} dp_dual_mode;\n\tstruct intel_connector *attached_connector;\n\tstruct cec_notifier *cec_notifier;\n};\n\nstruct intel_lspcon {\n\tbool active;\n\tbool hdr_supported;\n\tenum drm_lspcon_mode mode;\n\tenum lspcon_vendor vendor;\n};\n\nstruct intel_tc_port;\n\nstruct intel_digital_port {\n\tstruct intel_encoder base;\n\tstruct intel_dp dp;\n\tstruct intel_hdmi hdmi;\n\tstruct intel_lspcon lspcon;\n\tenum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);\n\tbool lane_reversal;\n\tbool ddi_a_4_lanes;\n\tbool release_cl2_override;\n\tbool dedicated_external;\n\tu8 max_lanes;\n\tenum aux_ch aux_ch;\n\tenum intel_display_power_domain ddi_io_power_domain;\n\tstruct ref_tracker *ddi_io_wakeref;\n\tstruct ref_tracker *aux_wakeref;\n\tstruct intel_tc_port *tc;\n\tstruct {\n\t\tstruct mutex mutex;\n\t\tunsigned int num_streams;\n\t\tbool auth_status;\n\t\tstruct hdcp_port_data port_data;\n\t\tbool mst_type1_capable;\n\t} hdcp;\n\tvoid (*write_infoframe)(struct intel_encoder *, const struct intel_crtc_state *, unsigned int, const void *, ssize_t);\n\tvoid (*read_infoframe)(struct intel_encoder *, const struct intel_crtc_state *, unsigned int, void *, ssize_t);\n\tvoid (*set_infoframes)(struct intel_encoder *, bool, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tu32 (*infoframes_enabled)(struct intel_encoder *, const struct intel_crtc_state *);\n\tbool (*connected)(struct intel_encoder *);\n\tvoid (*lock)(struct intel_digital_port *);\n\tvoid (*unlock)(struct intel_digital_port *);\n};\n\nstruct intel_display_platforms {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int g4x: 1;\n\t\t\tlong unsigned int mobile: 1;\n\t\t\tlong unsigned int dgfx: 1;\n\t\t\tlong unsigned int i830: 1;\n\t\t\tlong unsigned int i845g: 1;\n\t\t\tlong unsigned int i85x: 1;\n\t\t\tlong unsigned int i865g: 1;\n\t\t\tlong unsigned int i915g: 1;\n\t\t\tlong unsigned int i915gm: 1;\n\t\t\tlong unsigned int i945g: 1;\n\t\t\tlong unsigned int i945gm: 1;\n\t\t\tlong unsigned int g33: 1;\n\t\t\tlong unsigned int pineview: 1;\n\t\t\tlong unsigned int i965g: 1;\n\t\t\tlong unsigned int i965gm: 1;\n\t\t\tlong unsigned int g45: 1;\n\t\t\tlong unsigned int gm45: 1;\n\t\t\tlong unsigned int ironlake: 1;\n\t\t\tlong unsigned int sandybridge: 1;\n\t\t\tlong unsigned int ivybridge: 1;\n\t\t\tlong unsigned int valleyview: 1;\n\t\t\tlong unsigned int haswell: 1;\n\t\t\tlong unsigned int haswell_ult: 1;\n\t\t\tlong unsigned int haswell_ulx: 1;\n\t\t\tlong unsigned int broadwell: 1;\n\t\t\tlong unsigned int broadwell_ult: 1;\n\t\t\tlong unsigned int broadwell_ulx: 1;\n\t\t\tlong unsigned int cherryview: 1;\n\t\t\tlong unsigned int skylake: 1;\n\t\t\tlong unsigned int skylake_ult: 1;\n\t\t\tlong unsigned int skylake_ulx: 1;\n\t\t\tlong unsigned int broxton: 1;\n\t\t\tlong unsigned int kabylake: 1;\n\t\t\tlong unsigned int kabylake_ult: 1;\n\t\t\tlong unsigned int kabylake_ulx: 1;\n\t\t\tlong unsigned int geminilake: 1;\n\t\t\tlong unsigned int coffeelake: 1;\n\t\t\tlong unsigned int coffeelake_ult: 1;\n\t\t\tlong unsigned int coffeelake_ulx: 1;\n\t\t\tlong unsigned int cometlake: 1;\n\t\t\tlong unsigned int cometlake_ult: 1;\n\t\t\tlong unsigned int cometlake_ulx: 1;\n\t\t\tlong unsigned int icelake: 1;\n\t\t\tlong unsigned int icelake_port_f: 1;\n\t\t\tlong unsigned int jasperlake: 1;\n\t\t\tlong unsigned int elkhartlake: 1;\n\t\t\tlong unsigned int tigerlake: 1;\n\t\t\tlong unsigned int tigerlake_uy: 1;\n\t\t\tlong unsigned int rocketlake: 1;\n\t\t\tlong unsigned int dg1: 1;\n\t\t\tlong unsigned int alderlake_s: 1;\n\t\t\tlong unsigned int alderlake_s_raptorlake_s: 1;\n\t\t\tlong unsigned int alderlake_p: 1;\n\t\t\tlong unsigned int alderlake_p_alderlake_n: 1;\n\t\t\tlong unsigned int alderlake_p_raptorlake_p: 1;\n\t\t\tlong unsigned int alderlake_p_raptorlake_u: 1;\n\t\t\tlong unsigned int dg2: 1;\n\t\t\tlong unsigned int dg2_g10: 1;\n\t\t\tlong unsigned int dg2_g11: 1;\n\t\t\tlong unsigned int dg2_g12: 1;\n\t\t\tlong unsigned int meteorlake: 1;\n\t\t\tlong unsigned int meteorlake_u: 1;\n\t\t\tlong unsigned int lunarlake: 1;\n\t\t\tlong unsigned int battlemage: 1;\n\t\t\tlong unsigned int pantherlake: 1;\n\t\t\tlong unsigned int pantherlake_wildcatlake: 1;\n\t\t\tlong unsigned int novalake: 1;\n\t\t};\n\t\tlong unsigned int bitmap[2];\n\t};\n};\n\nstruct intel_global_state_funcs;\n\nstruct intel_global_obj {\n\tstruct list_head head;\n\tstruct intel_global_state *state;\n\tconst struct intel_global_state_funcs *funcs;\n};\n\nstruct sys_cache_cfg {\n\tstruct mutex lock;\n\tenum intel_fbc_id id;\n};\n\nstruct intel_fbdev;\n\nstruct intel_display_ip_ver {\n\tu16 ver;\n\tu16 rel;\n\tu16 step;\n};\n\nstruct intel_display_runtime_info {\n\tstruct intel_display_ip_ver ip;\n\tint step;\n\tu32 rawclk_freq;\n\tu8 pipe_mask;\n\tu8 cpu_transcoder_mask;\n\tu16 port_mask;\n\tu8 num_sprites[4];\n\tu8 num_scalers[4];\n\tu8 fbc_mask;\n\tbool has_hdcp;\n\tbool has_dmc;\n\tbool has_dsc;\n\tbool edp_typec_support;\n\tbool has_dbuf_overlap_detection;\n};\n\nstruct drm_dp_tunnel_mgr;\n\nstruct intel_dpll {\n\tstruct intel_dpll_state state;\n\tu8 index;\n\tu8 active_mask;\n\tbool on;\n\tconst struct dpll_info *info;\n\tstruct ref_tracker *wakeref;\n};\n\nstruct intel_dpll_mgr;\n\nstruct intel_dpll_global {\n\tstruct mutex lock;\n\tint num_dpll;\n\tstruct intel_dpll dplls[9];\n\tconst struct intel_dpll_mgr *mgr;\n\tstruct {\n\t\tint nssc;\n\t\tint ssc;\n\t} ref_clks;\n\tu8 pch_ssc_use;\n};\n\nstruct intel_frontbuffer_tracking {\n\tspinlock_t lock;\n\tunsigned int busy_bits;\n};\n\nstruct intel_hotplug {\n\tstruct delayed_work hotplug_work;\n\tconst u32 *hpd;\n\tconst u32 *pch_hpd;\n\tstruct {\n\t\tlong unsigned int last_jiffies;\n\t\tint count;\n\t\tint blocked_count;\n\t\tenum {\n\t\t\tHPD_ENABLED = 0,\n\t\t\tHPD_DISABLED = 1,\n\t\t\tHPD_MARK_DISABLED = 2,\n\t\t} state;\n\t} stats[15];\n\tu32 event_bits;\n\tu32 retry_bits;\n\tstruct delayed_work reenable_work;\n\tu32 long_hpd_pin_mask;\n\tu32 short_hpd_pin_mask;\n\tstruct work_struct dig_port_work;\n\tstruct work_struct poll_init_work;\n\tbool poll_enabled;\n\tbool detection_work_enabled;\n\tunsigned int hpd_storm_threshold;\n\tu8 hpd_short_storm_enabled;\n\tlong unsigned int oob_hotplug_last_state;\n\tstruct workqueue_struct *dp_wq;\n\tbool ignore_long_hpd;\n};\n\nstruct intel_display_params {\n\tchar *dmc_firmware_path;\n\tchar *vbt_firmware;\n\tint lvds_channel_mode;\n\tint panel_use_ssc;\n\tint vbt_sdvo_panel_type;\n\tint enable_dc;\n\tbool enable_dpt;\n\tbool enable_dsb;\n\tbool enable_flipq;\n\tbool enable_sagv;\n\tint disable_power_well;\n\tbool enable_ips;\n\tint invert_brightness;\n\tint edp_vswing;\n\tint enable_dpcd_backlight;\n\tbool load_detect_test;\n\tbool force_reset_modeset_test;\n\tbool disable_display;\n\tbool verbose_state_checks;\n\tbool nuclear_pageflip;\n\tbool enable_dp_mst;\n\tint enable_fbc;\n\tint enable_psr;\n\tint enable_panel_replay;\n\tbool psr_safest_params;\n\tbool enable_psr2_sel_fetch;\n\tint enable_dmc_wl;\n};\n\nstruct sdvo_device_mapping {\n\tu8 initialized;\n\tu8 dvo_port;\n\tu8 target_addr;\n\tu8 dvo_wiring;\n\tu8 i2c_pin;\n\tu8 ddc_pin;\n};\n\nstruct intel_vbt_data {\n\tu16 version;\n\tunsigned int int_tv_support: 1;\n\tunsigned int int_crt_support: 1;\n\tunsigned int lvds_use_ssc: 1;\n\tunsigned int int_lvds_support: 1;\n\tunsigned int display_clock_mode: 1;\n\tunsigned int fdi_rx_polarity_inverted: 1;\n\tint lvds_ssc_freq;\n\tenum drm_panel_orientation orientation;\n\tbool override_afc_startup;\n\tu8 override_afc_startup_val;\n\tint crt_ddc_pin;\n\tstruct list_head display_devices;\n\tstruct list_head bdb_blocks;\n\tstruct sdvo_device_mapping sdvo_mappings[2];\n};\n\nstruct intel_dmc_wl {\n\tspinlock_t lock;\n\tbool enabled;\n\tbool taken;\n\trefcount_t refcount;\n\tu32 dc_state;\n\tstruct delayed_work work;\n};\n\nstruct vlv_wm_ddl_values {\n\tu8 plane[8];\n};\n\nstruct vlv_wm_values {\n\tstruct g4x_pipe_wm pipe[3];\n\tstruct g4x_sr_wm sr;\n\tstruct vlv_wm_ddl_values ddl[3];\n\tu8 level;\n\tbool cxsr;\n};\n\nstruct intel_wm {\n\tu16 pri_latency[5];\n\tu16 spr_latency[5];\n\tu16 cur_latency[5];\n\tu16 skl_latency[8];\n\tunion {\n\t\tstruct ilk_wm_values hw;\n\t\tstruct vlv_wm_values vlv;\n\t\tstruct g4x_wm_values g4x;\n\t};\n\tu8 num_levels;\n\tstruct mutex wm_mutex;\n\tbool ipc_enabled;\n};\n\nstruct intel_display_parent_interface;\n\nstruct intel_display_funcs;\n\nstruct intel_dpll_global_funcs;\n\nstruct intel_hotplug_funcs;\n\nstruct intel_wm_funcs;\n\nstruct intel_fdi_funcs;\n\nstruct intel_dmc;\n\nstruct intel_fbc;\n\nstruct intel_gmbus;\n\nstruct intel_hdcp_gsc_context;\n\nstruct intel_display_device_info;\n\nstruct intel_opregion;\n\nstruct intel_display {\n\tstruct drm_device *drm;\n\tstruct intel_display_platforms platform;\n\tenum intel_pch pch_type;\n\tconst struct intel_display_parent_interface *parent;\n\tstruct {\n\t\tconst struct intel_display_funcs *display;\n\t\tconst struct intel_cdclk_funcs *cdclk;\n\t\tconst struct intel_dpll_global_funcs *dpll;\n\t\tconst struct intel_hotplug_funcs *hotplug;\n\t\tconst struct intel_wm_funcs *wm;\n\t\tconst struct intel_fdi_funcs *fdi;\n\t\tconst struct intel_color_funcs *color;\n\t\tconst struct intel_audio_funcs *audio;\n\t} funcs;\n\tstruct {\n\t\tbool any_task_allowed;\n\t\tstruct task_struct *allowed_task;\n\t} access;\n\tstruct {\n\t\tstruct mutex lock;\n\t} backlight;\n\tstruct {\n\t\tstruct intel_global_obj obj;\n\t\tstruct intel_bw_info max[6];\n\t} bw;\n\tstruct {\n\t\tstruct intel_cdclk_config hw;\n\t\tconst struct intel_cdclk_vals *table;\n\t\tstruct intel_global_obj obj;\n\t\tunsigned int max_cdclk_freq;\n\t\tunsigned int max_dotclk_freq;\n\t\tunsigned int skl_preferred_vco_freq;\n\t} cdclk;\n\tstruct {\n\t\tstruct drm_property_blob *glk_linear_degamma_lut;\n\t} color;\n\tstruct {\n\t\tu8 enabled_slices;\n\t\tstruct intel_global_obj obj;\n\t} dbuf;\n\tstruct {\n\t\tstruct intel_global_obj obj;\n\t} dbuf_bw;\n\tstruct {\n\t\tspinlock_t phy_lock;\n\t} dkl;\n\tstruct {\n\t\tstruct intel_dmc *dmc;\n\t\tstruct ref_tracker *wakeref;\n\t} dmc;\n\tstruct {\n\t\tu32 mmio_base;\n\t} dsi;\n\tstruct {\n\t\tconst struct dram_info *info;\n\t} dram;\n\tstruct {\n\t\tstruct intel_fbc *instances[4];\n\t\tstruct sys_cache_cfg sys_cache;\n\t} fbc;\n\tstruct {\n\t\tstruct intel_fbdev *fbdev;\n\t} fbdev;\n\tstruct {\n\t\tunsigned int pll_freq;\n\t\tu32 rx_config;\n\t} fdi;\n\tstruct {\n\t\tstruct list_head obj_list;\n\t} global;\n\tstruct {\n\t\tu32 mmio_base;\n\t\tstruct mutex mutex;\n\t\tstruct intel_gmbus *bus[15];\n\t\twait_queue_head_t wait_queue;\n\t} gmbus;\n\tstruct {\n\t\tstruct i915_hdcp_arbiter *arbiter;\n\t\tbool comp_added;\n\t\tstruct intel_hdcp_gsc_context *gsc_context;\n\t\tstruct mutex hdcp_mutex;\n\t} hdcp;\n\tstruct {\n\t\tu32 state;\n\t} hti;\n\tstruct {\n\t\tconst struct intel_display_device_info *__device_info;\n\t\tstruct intel_display_runtime_info __runtime_info;\n\t} info;\n\tstruct {\n\t\tbool false_color;\n\t} ips;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool vlv_display_irqs_enabled;\n\t\tu8 vblank_enabled;\n\t\tint vblank_enable_count;\n\t\tstruct work_struct vblank_notify_work;\n\t\tu32 vlv_imr_mask;\n\t\tu32 ilk_de_imr_mask;\n\t\tu32 de_pipe_imr_mask[4];\n\t\tu32 pipestat_irq_mask[4];\n\t} irq;\n\tstruct {\n\t\tu16 linetime[4];\n\t\tbool disable[4];\n\t} pkgc;\n\tstruct {\n\t\twait_queue_head_t waitqueue;\n\t\tstruct mutex lock;\n\t\tstruct intel_global_obj obj;\n\t} pmdemand;\n\tstruct {\n\t\tstruct i915_power_domains domains;\n\t\tu32 chv_phy_control;\n\t\tbool chv_phy_assert[2];\n\t} power;\n\tstruct {\n\t\tu32 mmio_base;\n\t\tstruct mutex mutex;\n\t} pps;\n\tstruct {\n\t\tstruct drm_property *broadcast_rgb;\n\t\tstruct drm_property *force_audio;\n\t} properties;\n\tstruct {\n\t\tlong unsigned int mask;\n\t} quirks;\n\tstruct {\n\t\tstruct drm_atomic_state *modeset_state;\n\t\tstruct drm_modeset_acquire_ctx reset_ctx;\n\t\tatomic_t pending_fb_pin;\n\t\tu32 saveDSPARB;\n\t\tu32 saveSWF0[16];\n\t\tu32 saveSWF1[16];\n\t\tu32 saveSWF3[3];\n\t\tu16 saveGCDGMBUS;\n\t} restore;\n\tstruct {\n\t\tenum {\n\t\t\tI915_SAGV_UNKNOWN = 0,\n\t\t\tI915_SAGV_DISABLED = 1,\n\t\t\tI915_SAGV_ENABLED = 2,\n\t\t\tI915_SAGV_NOT_CONTROLLED = 3,\n\t\t} status;\n\t\tu32 block_time_us;\n\t} sagv;\n\tstruct {\n\t\tstruct mutex lock;\n\t} sbi;\n\tstruct {\n\t\tu8 phy_failed_calibration;\n\t} snps;\n\tstruct {\n\t\tu32 chv_dpll_md[4];\n\t\tu32 bxt_phy_grc;\n\t} state;\n\tstruct {\n\t\tunsigned int hpll_freq;\n\t\tunsigned int czclk_freq;\n\t} vlv_clock;\n\tstruct {\n\t\tstruct workqueue_struct *modeset;\n\t\tstruct workqueue_struct *flip;\n\t\tstruct workqueue_struct *cleanup;\n\t\tstruct workqueue_struct *unordered;\n\t} wq;\n\tstruct drm_dp_tunnel_mgr *dp_tunnel_mgr;\n\tstruct intel_audio audio;\n\tstruct intel_dpll_global dpll;\n\tstruct intel_frontbuffer_tracking fb_tracking;\n\tstruct intel_hotplug hotplug;\n\tstruct intel_opregion *opregion;\n\tstruct intel_overlay *overlay;\n\tstruct intel_display_params params;\n\tstruct intel_vbt_data vbt;\n\tstruct intel_dmc_wl wl;\n\tstruct intel_wm wm;\n\tstruct work_struct psr_dc5_dc6_wa_work;\n};\n\nstruct intel_display_device_info {\n\tconst struct intel_display_runtime_info __runtime_defaults;\n\tu8 abox_mask;\n\tstruct {\n\t\tu16 size;\n\t\tu8 slice_mask;\n\t} dbuf;\n\tu8 cursor_needs_physical: 1;\n\tu8 has_cdclk_crawl: 1;\n\tu8 has_cdclk_squash: 1;\n\tu8 has_ddi: 1;\n\tu8 has_dp_mst: 1;\n\tu8 has_dsb: 1;\n\tu8 has_fpga_dbg: 1;\n\tu8 has_gmch: 1;\n\tu8 has_hotplug: 1;\n\tu8 has_hti: 1;\n\tu8 has_ipc: 1;\n\tu8 has_overlay: 1;\n\tu8 has_psr: 1;\n\tu8 has_psr_hw_tracking: 1;\n\tu8 overlay_needs_physical: 1;\n\tu8 supports_tv: 1;\n\tu32 mmio_offset;\n\tu32 pipe_offsets[7];\n\tu32 trans_offsets[7];\n\tu32 cursor_offsets[4];\n\tstruct {\n\t\tu32 degamma_lut_size;\n\t\tu32 gamma_lut_size;\n\t\tu32 degamma_lut_tests;\n\t\tu32 gamma_lut_tests;\n\t} color;\n};\n\nstruct intel_initial_plane_config;\n\nstruct intel_display_funcs {\n\tbool (*get_pipe_config)(struct intel_crtc *, struct intel_crtc_state *);\n\tvoid (*get_initial_plane_config)(struct intel_crtc *, struct intel_initial_plane_config *);\n\tbool (*fixup_initial_plane_config)(struct intel_crtc *, const struct intel_initial_plane_config *);\n\tvoid (*crtc_enable)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*crtc_disable)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*commit_modeset_enables)(struct intel_atomic_state *);\n};\n\nstruct intel_display_hdcp_interface {\n\tssize_t (*gsc_msg_send)(struct intel_hdcp_gsc_context *, void *, size_t, void *, size_t);\n\tbool (*gsc_check_status)(struct drm_device *);\n\tstruct intel_hdcp_gsc_context * (*gsc_context_alloc)(struct drm_device *);\n\tvoid (*gsc_context_free)(struct intel_hdcp_gsc_context *);\n};\n\nstruct intel_display_initial_plane_interface {\n\tvoid (*vblank_wait)(struct drm_crtc *);\n\tstruct drm_gem_object * (*alloc_obj)(struct drm_device *, struct intel_initial_plane_config *);\n\tint (*setup)(struct drm_plane_state *, struct intel_initial_plane_config *, struct drm_framebuffer *, struct i915_vma *);\n\tvoid (*config_fini)(struct intel_initial_plane_config *);\n};\n\nstruct intel_display_irq_interface {\n\tbool (*enabled)(struct drm_device *);\n\tvoid (*synchronize)(struct drm_device *);\n};\n\nstruct intel_display_irq_snapshot {\n\tu32 derrmr;\n};\n\nstruct intel_panic;\n\nstruct intel_display_panic_interface {\n\tstruct intel_panic * (*alloc)(void);\n\tint (*setup)(struct intel_panic *, struct drm_scanout_buffer *);\n\tvoid (*finish)(struct intel_panic *);\n};\n\nstruct intel_display_pc8_interface;\n\nstruct intel_display_rpm_interface;\n\nstruct intel_display_rps_interface;\n\nstruct intel_display_stolen_interface;\n\nstruct intel_display_parent_interface {\n\tconst struct intel_display_hdcp_interface *hdcp;\n\tconst struct intel_display_initial_plane_interface *initial_plane;\n\tconst struct intel_display_irq_interface *irq;\n\tconst struct intel_display_panic_interface *panic;\n\tconst struct intel_display_pc8_interface *pc8;\n\tconst struct intel_display_rpm_interface *rpm;\n\tconst struct intel_display_rps_interface *rps;\n\tconst struct intel_display_stolen_interface *stolen;\n\tstruct {\n\t\tvoid (*fence_priority_display)(struct dma_fence *);\n\t\tbool (*has_auxccs)(struct drm_device *);\n\t\tbool (*has_fenced_regions)(struct drm_device *);\n\t\tbool (*vgpu_active)(struct drm_device *);\n\t};\n};\n\nstruct intel_display_pc8_interface {\n\tvoid (*block)(struct drm_device *);\n\tvoid (*unblock)(struct drm_device *);\n};\n\nstruct intel_display_rpm_interface {\n\tstruct ref_tracker * (*get)(const struct drm_device *);\n\tstruct ref_tracker * (*get_raw)(const struct drm_device *);\n\tstruct ref_tracker * (*get_if_in_use)(const struct drm_device *);\n\tstruct ref_tracker * (*get_noresume)(const struct drm_device *);\n\tvoid (*put)(const struct drm_device *, struct ref_tracker *);\n\tvoid (*put_raw)(const struct drm_device *, struct ref_tracker *);\n\tvoid (*put_unchecked)(const struct drm_device *);\n\tbool (*suspended)(const struct drm_device *);\n\tvoid (*assert_held)(const struct drm_device *);\n\tvoid (*assert_block)(const struct drm_device *);\n\tvoid (*assert_unblock)(const struct drm_device *);\n};\n\nstruct intel_display_rps_interface {\n\tvoid (*boost_if_not_started)(struct dma_fence *);\n\tvoid (*mark_interactive)(struct drm_device *, bool);\n\tvoid (*ilk_irq_handler)(struct drm_device *);\n};\n\nstruct intel_overlay_snapshot;\n\nstruct intel_dmc_snapshot;\n\nstruct intel_display_snapshot {\n\tstruct intel_display *display;\n\tstruct intel_display_device_info info;\n\tstruct intel_display_runtime_info runtime_info;\n\tstruct intel_display_params params;\n\tstruct intel_overlay_snapshot *overlay;\n\tstruct intel_dmc_snapshot *dmc;\n\tstruct intel_display_irq_snapshot *irq;\n};\n\nstruct intel_stolen_node;\n\nstruct intel_display_stolen_interface {\n\tint (*insert_node_in_range)(struct intel_stolen_node *, u64, unsigned int, u64, u64);\n\tint (*insert_node)(struct intel_stolen_node *, u64, unsigned int);\n\tvoid (*remove_node)(struct intel_stolen_node *);\n\tbool (*initialized)(struct drm_device *);\n\tbool (*node_allocated)(const struct intel_stolen_node *);\n\tu64 (*node_offset)(const struct intel_stolen_node *);\n\tu64 (*area_address)(struct drm_device *);\n\tu64 (*area_size)(struct drm_device *);\n\tu64 (*node_address)(const struct intel_stolen_node *);\n\tu64 (*node_size)(const struct intel_stolen_node *);\n\tstruct intel_stolen_node * (*node_alloc)(struct drm_device *);\n\tvoid (*node_free)(const struct intel_stolen_node *);\n};\n\nstruct intel_dkl_phy_reg {\n\tu32 reg: 24;\n\tu32 bank_idx: 4;\n};\n\nstruct intel_dmc {\n\tstruct intel_display *display;\n\tstruct work_struct work;\n\tconst char *fw_path;\n\tu32 max_fw_size;\n\tu32 version;\n\tstruct {\n\t\tu32 dc5_start;\n\t\tu32 count;\n\t} dc6_allowed;\n\tstruct dmc_fw_info dmc_info[5];\n};\n\nstruct intel_dmc_header_base {\n\tu32 signature;\n\tu8 header_len;\n\tu8 header_ver;\n\tu16 dmcc_ver;\n\tu32 project;\n\tu32 fw_size;\n\tu32 fw_version;\n};\n\nstruct intel_dmc_header_v1 {\n\tstruct intel_dmc_header_base base;\n\tu32 mmio_count;\n\tu32 mmioaddr[8];\n\tu32 mmiodata[8];\n\tchar dfile[32];\n\tu32 reserved1[2];\n};\n\nstruct intel_dmc_header_v3 {\n\tstruct intel_dmc_header_base base;\n\tu32 start_mmioaddr;\n\tu32 reserved[9];\n\tchar dfile[32];\n\tu32 mmio_count;\n\tu32 mmioaddr[20];\n\tu32 mmiodata[20];\n};\n\nstruct intel_dmc_snapshot {\n\tbool initialized;\n\tbool loaded;\n\tu32 version;\n};\n\nstruct intel_dmc_wl_range {\n\tu32 start;\n\tu32 end;\n};\n\nstruct intel_dmi_quirk {\n\tvoid (*hook)(struct intel_display *);\n\tconst struct dmi_system_id (*dmi_id_list)[0];\n};\n\nstruct intel_dp_mst_encoder {\n\tstruct intel_encoder base;\n\tenum pipe pipe;\n\tstruct intel_digital_port *primary;\n\tstruct intel_connector *connector;\n};\n\nstruct intel_dpcd_quirk {\n\tint device;\n\tint subsystem_vendor;\n\tint subsystem_device;\n\tu8 sink_oui[3];\n\tu8 sink_device_id[6];\n\tvoid (*hook)(struct intel_dp *);\n};\n\nstruct intel_dpll_funcs {\n\tvoid (*enable)(struct intel_display *, struct intel_dpll *, const struct intel_dpll_hw_state *);\n\tvoid (*disable)(struct intel_display *, struct intel_dpll *);\n\tbool (*get_hw_state)(struct intel_display *, struct intel_dpll *, struct intel_dpll_hw_state *);\n\tint (*get_freq)(struct intel_display *, const struct intel_dpll *, const struct intel_dpll_hw_state *);\n};\n\nstruct intel_dpll_global_funcs {\n\tint (*crtc_compute_clock)(struct intel_atomic_state *, struct intel_crtc *);\n\tint (*crtc_get_dpll)(struct intel_atomic_state *, struct intel_crtc *);\n};\n\nstruct intel_dpll_mgr {\n\tconst struct dpll_info *dpll_info;\n\tint (*compute_dplls)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tint (*get_dplls)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tvoid (*put_dplls)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*update_active_dpll)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tvoid (*update_ref_clks)(struct intel_display *);\n\tvoid (*dump_hw_state)(struct drm_printer *, const struct intel_dpll_hw_state *);\n\tbool (*compare_hw_state)(const struct intel_dpll_hw_state *, const struct intel_dpll_hw_state *);\n};\n\nstruct intel_dsb_buffer;\n\nstruct intel_dsb {\n\tenum intel_dsb_id id;\n\tstruct intel_dsb_buffer *dsb_buf;\n\tstruct intel_crtc *crtc;\n\tunsigned int size;\n\tunsigned int free_pos;\n\tu32 ins[2];\n\tunsigned int ins_start_offset;\n\tu32 chicken;\n\tint hw_dewake_scanline;\n};\n\nstruct intel_dsb_buffer {\n\tu32 *cmd_buf;\n\tstruct i915_vma *vma;\n\tsize_t buf_size;\n};\n\nstruct intel_dsi_host;\n\nstruct intel_dsi {\n\tstruct intel_encoder base;\n\tstruct intel_dsi_host *dsi_hosts[9];\n\tstruct ref_tracker *io_wakeref[9];\n\tstruct gpio_desc *gpio_panel;\n\tstruct gpio_desc *gpio_backlight;\n\tstruct intel_connector *attached_connector;\n\tunion {\n\t\tu16 ports;\n\t\tu16 phys;\n\t};\n\tint channel;\n\tu16 operation_mode;\n\tunsigned int lane_count;\n\tint i2c_bus_num;\n\tenum mipi_dsi_pixel_format pixel_format;\n\tint video_mode;\n\tu8 eotp_pkt;\n\tu8 clock_stop;\n\tu8 escape_clk_div;\n\tu8 dual_link;\n\tbool bgr_enabled;\n\tu8 pixel_overlap;\n\tu32 bw_timer;\n\tu32 dphy_reg;\n\tu32 dphy_data_lane_reg;\n\tu32 video_frmt_cfg_bits;\n\tu16 lp_byte_clk;\n\tu16 hs_tx_timeout;\n\tu16 lp_rx_timeout;\n\tu16 turn_arnd_val;\n\tu16 rst_timer_val;\n\tu16 hs_to_lp_count;\n\tu16 clk_lp_to_hs_count;\n\tu16 clk_hs_to_lp_count;\n\tu16 init_count;\n\tu32 pclk;\n\tu16 burst_mode_ratio;\n\tu16 backlight_off_delay;\n\tu16 backlight_on_delay;\n\tu16 panel_on_delay;\n\tu16 panel_off_delay;\n\tu16 panel_pwr_cycle_delay;\n\tktime_t panel_power_off_time;\n};\n\nstruct mipi_dsi_host_ops;\n\nstruct mipi_dsi_host {\n\tstruct device *dev;\n\tconst struct mipi_dsi_host_ops *ops;\n\tstruct list_head list;\n};\n\nstruct mipi_dsi_device;\n\nstruct intel_dsi_host {\n\tstruct mipi_dsi_host base;\n\tstruct intel_dsi *intel_dsi;\n\tenum port port;\n\tstruct mipi_dsi_device *device;\n};\n\nstruct intel_dvo_dev_ops;\n\nstruct intel_dvo_device {\n\tconst char *name;\n\tint type;\n\tenum port port;\n\tu32 gpio;\n\tint target_addr;\n\tconst struct intel_dvo_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct i2c_adapter *i2c_bus;\n};\n\nstruct intel_dvo {\n\tstruct intel_encoder base;\n\tstruct intel_dvo_device dev;\n\tstruct intel_connector *attached_connector;\n};\n\nstruct intel_dvo_dev_ops {\n\tbool (*init)(struct intel_dvo_device *, struct i2c_adapter *);\n\tvoid (*dpms)(struct intel_dvo_device *, bool);\n\tenum drm_mode_status (*mode_valid)(struct intel_dvo_device *, const struct drm_display_mode *);\n\tvoid (*mode_set)(struct intel_dvo_device *, const struct drm_display_mode *, const struct drm_display_mode *);\n\tenum drm_connector_status (*detect)(struct intel_dvo_device *);\n\tbool (*get_hw_state)(struct intel_dvo_device *);\n\tvoid (*destroy)(struct intel_dvo_device *);\n\tvoid (*dump_regs)(struct intel_dvo_device *);\n};\n\nstruct intel_early_ops {\n\tresource_size_t (*stolen_size)(int, int, int);\n\tresource_size_t (*stolen_base)(int, int, int, resource_size_t);\n};\n\nstruct intel_engine_capture_vma {\n\tstruct intel_engine_capture_vma *next;\n\tstruct i915_vma_resource *vma_res;\n\tchar name[16];\n\tbool lockdep_cookie;\n};\n\nstruct intel_instdone {\n\tu32 instdone;\n\tu32 slice_common;\n\tu32 slice_common_extra[2];\n\tu32 sampler[128];\n\tu32 row[128];\n\tu32 geom_svg[128];\n};\n\nstruct intel_guc_state_capture;\n\nstruct intel_engine_coredump {\n\tconst struct intel_engine_cs *engine;\n\tbool hung;\n\tbool simulated;\n\tu32 reset_count;\n\tu32 rq_head;\n\tu32 rq_post;\n\tu32 rq_tail;\n\tu32 ccid;\n\tu32 start;\n\tu32 tail;\n\tu32 head;\n\tu32 ctl;\n\tu32 mode;\n\tu32 hws;\n\tu32 ipeir;\n\tu32 ipehr;\n\tu32 esr;\n\tu32 bbstate;\n\tu32 instpm;\n\tu32 instps;\n\tu64 bbaddr;\n\tu64 acthd;\n\tu32 fault_reg;\n\tu64 faddr;\n\tu32 rc_psmi;\n\tu32 nopid;\n\tu32 excc;\n\tu32 cmd_cctl;\n\tu32 cscmdop;\n\tu32 ctx_sr_ctl;\n\tu32 dma_faddr_hi;\n\tu32 dma_faddr_lo;\n\tstruct intel_instdone instdone;\n\tstruct intel_guc_state_capture *guc_capture;\n\tstruct __guc_capture_parsed_output *guc_capture_node;\n\tstruct i915_gem_context_coredump context;\n\tstruct i915_vma_coredump *vma;\n\tstruct i915_request_coredump execlist[2];\n\tunsigned int num_ports;\n\tstruct {\n\t\tu32 gfx_mode;\n\t\tunion {\n\t\t\tu64 pdp[4];\n\t\t\tu32 pp_dir_base;\n\t\t};\n\t} vm_info;\n\tstruct intel_engine_coredump *next;\n};\n\nstruct intel_excl_states {\n\tenum intel_excl_state_type state[64];\n\tbool sched_started;\n};\n\nstruct intel_excl_cntrs {\n\traw_spinlock_t lock;\n\tstruct intel_excl_states states[2];\n\tunion {\n\t\tu16 has_exclusive[2];\n\t\tu32 exclusive_present;\n\t};\n\tint refcnt;\n\tunsigned int core_id;\n};\n\nstruct intel_fb_view {\n\tstruct i915_gtt_view gtt;\n\tstruct i915_color_plane_view color_plane[4];\n};\n\nstruct intel_plane;\n\nstruct intel_fbc_state {\n\tstruct intel_plane *plane;\n\tunsigned int cfb_stride;\n\tunsigned int cfb_size;\n\tunsigned int fence_y_offset;\n\tu16 override_cfb_stride;\n\tu16 interval;\n\ts8 fence_id;\n\tstruct drm_rect dirty_rect;\n};\n\nstruct intel_fbc_funcs;\n\nstruct intel_fbc {\n\tstruct intel_display *display;\n\tconst struct intel_fbc_funcs *funcs;\n\tstruct mutex lock;\n\tunsigned int busy_bits;\n\tstruct intel_stolen_node *compressed_fb;\n\tstruct intel_stolen_node *compressed_llb;\n\tenum intel_fbc_id id;\n\tu8 limit;\n\tbool false_color;\n\tbool active;\n\tbool activated;\n\tbool flip_pending;\n\tbool underrun_detected;\n\tstruct work_struct underrun_work;\n\tstruct intel_fbc_state state;\n\tconst char *no_fbc_reason;\n};\n\nstruct intel_fbc_funcs {\n\tvoid (*activate)(struct intel_fbc *);\n\tvoid (*deactivate)(struct intel_fbc *);\n\tbool (*is_active)(struct intel_fbc *);\n\tbool (*is_compressing)(struct intel_fbc *);\n\tvoid (*nuke)(struct intel_fbc *);\n\tvoid (*program_cfb)(struct intel_fbc *);\n\tvoid (*set_false_color)(struct intel_fbc *, bool);\n};\n\nstruct intel_fdi_funcs {\n\tvoid (*fdi_link_train)(struct intel_crtc *, const struct intel_crtc_state *);\n};\n\nstruct intel_forcewake_range {\n\tu32 start;\n\tu32 end;\n\tenum forcewake_domains domains;\n};\n\nstruct intel_framebuffer {\n\tstruct drm_framebuffer base;\n\tstruct intel_frontbuffer *frontbuffer;\n\tstruct intel_fb_view normal_view;\n\tunion {\n\t\tstruct intel_fb_view rotated_view;\n\t\tstruct intel_fb_view remapped_view;\n\t};\n\tstruct i915_address_space *dpt_vm;\n\tunsigned int min_alignment;\n\tunsigned int vtd_guard;\n\tunsigned int (*panic_tiling)(unsigned int, unsigned int, unsigned int);\n\tstruct intel_panic *panic;\n};\n\nstruct intel_fw_info {\n\tu8 reserved1;\n\tu8 dmc_id;\n\tchar stepping;\n\tchar substepping;\n\tu32 offset;\n\tu32 reserved2;\n};\n\nstruct intel_global_commit {\n\tstruct kref ref;\n\tstruct completion done;\n};\n\nstruct intel_global_objs_state {\n\tstruct intel_global_obj *ptr;\n\tstruct intel_global_state *state;\n\tstruct intel_global_state *old_state;\n\tstruct intel_global_state *new_state;\n};\n\nstruct intel_global_state_funcs {\n\tstruct intel_global_state * (*atomic_duplicate_state)(struct intel_global_obj *);\n\tvoid (*atomic_destroy_state)(struct intel_global_obj *, struct intel_global_state *);\n};\n\nstruct intel_gmbus {\n\tstruct i2c_adapter adapter;\n\tu32 force_bit;\n\tu32 reg0;\n\ti915_reg_t gpio_reg;\n\tstruct i2c_algo_bit_data bit_algo;\n\tstruct intel_display *display;\n};\n\nstruct mei_aux_device;\n\nstruct intel_gsc_intf {\n\tstruct mei_aux_device *adev;\n\tstruct drm_i915_gem_object *gem_obj;\n\tint irq;\n\tunsigned int id;\n};\n\nstruct intel_gsc {\n\tstruct intel_gsc_intf intf[2];\n};\n\nstruct intel_gsc_bpdt_entry {\n\tu32 type;\n\tu32 sub_partition_offset;\n\tu32 sub_partition_size;\n};\n\nstruct intel_gsc_version {\n\tu16 major;\n\tu16 minor;\n\tu16 hotfix;\n\tu16 build;\n};\n\nstruct intel_gsc_bpdt_header {\n\tu32 signature;\n\tu16 descriptor_count;\n\tu8 version;\n\tu8 configuration;\n\tu32 crc32;\n\tu32 build_version;\n\tstruct intel_gsc_version tool_version;\n};\n\nstruct intel_gsc_cpd_entry {\n\tu8 name[12];\n\tu32 offset;\n\tu32 length;\n\tu8 reserved[4];\n};\n\nstruct intel_gsc_cpd_header_v2 {\n\tu32 header_marker;\n\tu32 num_of_entries;\n\tu8 header_version;\n\tu8 entry_version;\n\tu8 header_length;\n\tu8 flags;\n\tu32 partition_name;\n\tu32 crc32;\n};\n\nstruct intel_gsc_heci_non_priv_pkt {\n\tu64 addr_in;\n\tu32 size_in;\n\tu64 addr_out;\n\tu32 size_out;\n\tstruct i915_vma *heci_pkt_vma;\n\tstruct i915_vma *bb_vma;\n};\n\nstruct intel_gsc_partition {\n\tu32 offset;\n\tu32 size;\n};\n\nstruct intel_gsc_layout_pointers {\n\tu8 rom_bypass_vector[16];\n\tu16 size;\n\tu8 flags;\n\tu8 reserved;\n\tu32 crc32;\n\tstruct intel_gsc_partition datap;\n\tstruct intel_gsc_partition boot1;\n\tstruct intel_gsc_partition boot2;\n\tstruct intel_gsc_partition boot3;\n\tstruct intel_gsc_partition boot4;\n\tstruct intel_gsc_partition boot5;\n\tstruct intel_gsc_partition temp_pages;\n};\n\nstruct intel_gsc_manifest_header {\n\tu32 header_type;\n\tu32 header_length;\n\tu32 header_version;\n\tu32 flags;\n\tu32 vendor;\n\tu32 date;\n\tu32 size;\n\tu32 header_id;\n\tu32 internal_data;\n\tstruct intel_gsc_version fw_version;\n\tu32 security_version;\n\tstruct intel_gsc_version meu_kit_version;\n\tu32 meu_manifest_version;\n\tu8 general_data[4];\n\tu8 reserved3[56];\n\tu32 modulus_size;\n\tu32 exponent_size;\n};\n\nstruct intel_gsc_mkhi_header {\n\tu8 group_id;\n\tu8 command;\n\tu8 reserved;\n\tu8 result;\n};\n\nstruct intel_uc_fw_ver {\n\tu32 major;\n\tu32 minor;\n\tu32 patch;\n\tu32 build;\n};\n\nstruct intel_uc_fw_file {\n\tconst char *path;\n\tstruct intel_uc_fw_ver ver;\n};\n\nstruct intel_uc_fw {\n\tenum intel_uc_fw_type type;\n\tunion {\n\t\tconst enum intel_uc_fw_status status;\n\t\tenum intel_uc_fw_status __status;\n\t};\n\tstruct intel_uc_fw_file file_wanted;\n\tstruct intel_uc_fw_file file_selected;\n\tbool user_overridden;\n\tsize_t size;\n\tstruct drm_i915_gem_object *obj;\n\tbool needs_ggtt_mapping;\n\tstruct i915_vma_resource vma_res;\n\tstruct i915_vma *rsa_data;\n\tu32 rsa_size;\n\tu32 ucode_size;\n\tu32 private_data_size;\n\tu32 dma_start_offset;\n\tbool has_gsc_headers;\n};\n\nstruct intel_gsc_uc {\n\tstruct intel_uc_fw fw;\n\tstruct intel_uc_fw_ver release;\n\tu32 security_version;\n\tstruct i915_vma *local;\n\tvoid *local_vaddr;\n\tstruct intel_context *ce;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct work;\n\tu32 gsc_work_actions;\n\tstruct {\n\t\tstruct i915_gsc_proxy_component *component;\n\t\tbool component_added;\n\t\tstruct i915_vma *vma;\n\t\tvoid *to_gsc;\n\t\tvoid *to_csme;\n\t\tstruct mutex mutex;\n\t} proxy;\n};\n\nstruct intel_guc_log {\n\tu32 level;\n\tstruct mutex guc_lock;\n\tstruct {\n\t\ts32 bytes;\n\t\ts32 units;\n\t\ts32 count;\n\t\tu32 flag;\n\t} sizes[3];\n\tbool sizes_initialised;\n\tstruct i915_vma *vma;\n\tvoid *buf_addr;\n\tstruct {\n\t\tbool buf_in_use;\n\t\tbool started;\n\t\tstruct work_struct flush_work;\n\t\tstruct rchan *channel;\n\t\tstruct mutex lock;\n\t\tu32 full_count;\n\t} relay;\n\tstruct {\n\t\tu32 sampled_overflow;\n\t\tu32 overflow;\n\t\tu32 flush;\n\t} stats[3];\n};\n\nstruct intel_guc_ct_buffer {\n\tspinlock_t lock;\n\tstruct guc_ct_buffer_desc *desc;\n\tu32 *cmds;\n\tu32 size;\n\tu32 resv_space;\n\tu32 tail;\n\tu32 head;\n\tatomic_t space;\n\tbool broken;\n};\n\nstruct intel_guc_ct {\n\tstruct i915_vma *vma;\n\tbool enabled;\n\tstruct {\n\t\tstruct intel_guc_ct_buffer send;\n\t\tstruct intel_guc_ct_buffer recv;\n\t} ctbs;\n\tstruct tasklet_struct receive_tasklet;\n\twait_queue_head_t wq;\n\tstruct {\n\t\tu16 last_fence;\n\t\tspinlock_t lock;\n\t\tstruct list_head pending;\n\t\tstruct list_head incoming;\n\t\tstruct work_struct worker;\n\t} requests;\n\tktime_t stall_time;\n};\n\nstruct slpc_shared_data;\n\nstruct intel_guc_slpc {\n\tstruct i915_vma *vma;\n\tstruct slpc_shared_data *vaddr;\n\tbool supported;\n\tbool selected;\n\tbool min_is_rpmax;\n\tu32 min_freq;\n\tu32 rp0_freq;\n\tu32 rp1_freq;\n\tu32 boost_freq;\n\tu32 min_freq_softlimit;\n\tu32 max_freq_softlimit;\n\tbool ignore_eff_freq;\n\tu32 power_profile;\n\tu32 media_ratio_mode;\n\tstruct mutex lock;\n\tstruct work_struct boost_work;\n\tatomic_t num_waiters;\n\tu32 num_boosts;\n};\n\nstruct intel_guc {\n\tstruct intel_uc_fw fw;\n\tstruct intel_guc_log log;\n\tstruct intel_guc_ct ct;\n\tstruct intel_guc_slpc slpc;\n\tstruct intel_guc_state_capture *capture;\n\tstruct dentry *dbgfs_node;\n\tstruct i915_sched_engine *sched_engine;\n\tstruct i915_request *stalled_request;\n\tenum {\n\t\tSTALL_NONE = 0,\n\t\tSTALL_REGISTER_CONTEXT = 1,\n\t\tSTALL_MOVE_LRC_TAIL = 2,\n\t\tSTALL_ADD_REQUEST = 3,\n\t} submission_stall_reason;\n\tspinlock_t irq_lock;\n\tunsigned int msg_enabled_mask;\n\tatomic_t outstanding_submission_g2h;\n\tstruct xarray tlb_lookup;\n\tu32 serial_slot;\n\tu32 next_seqno;\n\tstruct {\n\t\tbool enabled;\n\t\tvoid (*reset)(struct intel_guc *);\n\t\tvoid (*enable)(struct intel_guc *);\n\t\tvoid (*disable)(struct intel_guc *);\n\t} interrupts;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct ida guc_ids;\n\t\tint num_guc_ids;\n\t\tlong unsigned int *guc_ids_bitmap;\n\t\tstruct list_head guc_id_list;\n\t\tunsigned int guc_ids_in_use;\n\t\tstruct list_head destroyed_contexts;\n\t\tstruct work_struct destroyed_worker;\n\t\tstruct work_struct reset_fail_worker;\n\t\tintel_engine_mask_t reset_fail_mask;\n\t\tunsigned int sched_disable_delay_ms;\n\t\tunsigned int sched_disable_gucid_threshold;\n\t} submission_state;\n\tbool submission_supported;\n\tbool submission_selected;\n\tbool submission_initialized;\n\tstruct intel_uc_fw_ver submission_version;\n\tbool rc_supported;\n\tbool rc_selected;\n\tstruct i915_vma *ads_vma;\n\tstruct iosys_map ads_map;\n\tu32 ads_regset_size;\n\tu32 ads_regset_count[27];\n\tstruct guc_mmio_reg *ads_regset;\n\tu32 ads_golden_ctxt_size;\n\tu32 ads_waklv_size;\n\tu32 ads_capture_size;\n\tstruct i915_vma *lrc_desc_pool_v69;\n\tvoid *lrc_desc_pool_vaddr_v69;\n\tstruct xarray context_lookup;\n\tu32 params[14];\n\tstruct {\n\t\tu32 base;\n\t\tunsigned int count;\n\t\tenum forcewake_domains fw_domains;\n\t} send_regs;\n\ti915_reg_t notify_reg;\n\tu32 mmio_msg;\n\tstruct mutex send_mutex;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tu64 gt_stamp;\n\t\tlong unsigned int ping_delay;\n\t\tstruct delayed_work work;\n\t\tu32 shift;\n\t\tlong unsigned int last_stat_jiffies;\n\t} timestamp;\n\tstruct work_struct dead_guc_worker;\n\tlong unsigned int last_dead_guc_jiffies;\n};\n\nstruct intel_huc {\n\tstruct intel_uc_fw fw;\n\tstruct {\n\t\ti915_reg_t reg;\n\t\tu32 mask;\n\t\tu32 value;\n\t} status[2];\n\tstruct {\n\t\tstruct i915_sw_fence fence;\n\t\tstruct hrtimer timer;\n\t\tstruct notifier_block nb;\n\t\tenum intel_huc_delayed_load_status status;\n\t} delayed_load;\n\tstruct i915_vma *heci_pkt;\n\tbool loaded_via_gsc;\n};\n\nstruct intel_uc_ops;\n\nstruct intel_uc {\n\tconst struct intel_uc_ops *ops;\n\tstruct intel_gsc_uc gsc;\n\tstruct intel_guc guc;\n\tstruct intel_huc huc;\n\tstruct drm_i915_gem_object *load_err_log;\n\tbool reset_in_progress;\n\tbool fw_table_invalid;\n};\n\nstruct intel_wopcm {\n\tu32 size;\n\tstruct {\n\t\tu32 base;\n\t\tu32 size;\n\t} guc;\n};\n\nstruct seqcount_mutex {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_mutex seqcount_mutex_t;\n\nstruct intel_gt_timelines {\n\tspinlock_t lock;\n\tstruct list_head active_list;\n};\n\nstruct intel_gt_requests {\n\tstruct delayed_work retire_work;\n};\n\nstruct intel_reset {\n\tlong unsigned int flags;\n\tstruct mutex mutex;\n\twait_queue_head_t queue;\n\tstruct srcu_struct backoff_srcu;\n};\n\nstruct intel_llc {};\n\nstruct intel_rc6 {\n\ti915_reg_t res_reg[4];\n\tu64 prev_hw_residency[4];\n\tu64 cur_residency[4];\n\tu32 ctl_enable;\n\tu32 bios_rc_state;\n\tstruct drm_i915_gem_object *pctx;\n\tbool supported: 1;\n\tbool enabled: 1;\n\tbool manual: 1;\n\tbool wakeref: 1;\n\tbool bios_state_captured: 1;\n};\n\nstruct intel_rps_ei {\n\tktime_t ktime;\n\tu32 render_c0;\n\tu32 media_c0;\n};\n\nstruct intel_ips {\n\tu64 last_count1;\n\tlong unsigned int last_time1;\n\tlong unsigned int chipset_power;\n\tu64 last_count2;\n\tu64 last_time2;\n\tlong unsigned int gfx_power;\n\tu8 corr;\n\tint c;\n\tint m;\n};\n\nstruct intel_rps {\n\tstruct mutex lock;\n\tstruct timer_list timer;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n\tktime_t pm_timestamp;\n\tu32 pm_interval;\n\tu32 pm_iir;\n\tu32 pm_intrmsk_mbz;\n\tu32 pm_events;\n\tu8 cur_freq;\n\tu8 last_freq;\n\tu8 min_freq_softlimit;\n\tu8 max_freq_softlimit;\n\tu8 max_freq;\n\tu8 min_freq;\n\tu8 boost_freq;\n\tu8 idle_freq;\n\tu8 efficient_freq;\n\tu8 rp1_freq;\n\tu8 rp0_freq;\n\tu16 gpll_ref_freq;\n\tint last_adj;\n\tstruct {\n\t\tstruct mutex mutex;\n\t\tenum {\n\t\t\tLOW_POWER = 0,\n\t\t\tBETWEEN = 1,\n\t\t\tHIGH_POWER = 2,\n\t\t} mode;\n\t\tunsigned int interactive;\n\t\tu8 up_threshold;\n\t\tu8 down_threshold;\n\t} power;\n\tatomic_t num_waiters;\n\tunsigned int boosts;\n\tstruct intel_rps_ei ei;\n\tstruct intel_ips ips;\n};\n\nstruct intel_gt_buffer_pool {\n\tspinlock_t lock;\n\tstruct list_head cache_list[4];\n\tstruct delayed_work work;\n};\n\nstruct intel_migrate {\n\tstruct intel_context *context;\n};\n\nstruct sseu_dev_info {\n\tu8 slice_mask;\n\tintel_sseu_ss_mask_t subslice_mask;\n\tintel_sseu_ss_mask_t geometry_subslice_mask;\n\tintel_sseu_ss_mask_t compute_subslice_mask;\n\tunion {\n\t\tu16 hsw[24];\n\t\tu16 xehp[64];\n\t} eu_mask;\n\tu16 eu_total;\n\tu8 eu_per_subslice;\n\tu8 min_eu_in_pool;\n\tu8 subslice_7eu[3];\n\tu8 has_slice_pg: 1;\n\tu8 has_subslice_pg: 1;\n\tu8 has_eu_pg: 1;\n\tu8 has_xehp_dss: 1;\n\tu8 max_slices;\n\tu8 max_subslices;\n\tu8 max_eus_per_subslice;\n};\n\nstruct intel_hwconfig {\n\tu32 size;\n\tvoid *ptr;\n};\n\nstruct intel_gt_info {\n\tunsigned int id;\n\tintel_engine_mask_t engine_mask;\n\tu32 l3bank_mask;\n\tu8 num_engines;\n\tu8 sfc_mask;\n\tu8 vdbox_sfc_access;\n\tstruct sseu_dev_info sseu;\n\tlong unsigned int mslice_mask;\n\tstruct intel_hwconfig hwconfig;\n};\n\nstruct intel_mmio_range;\n\nstruct intel_gt {\n\tstruct drm_i915_private *i915;\n\tconst char *name;\n\tenum intel_gt_type type;\n\tstruct intel_uncore *uncore;\n\tstruct i915_ggtt *ggtt;\n\tstruct intel_uc uc;\n\tstruct intel_gsc gsc;\n\tstruct intel_wopcm wopcm;\n\tstruct {\n\t\tstruct mutex invalidate_lock;\n\t\tseqcount_mutex_t seqno;\n\t} tlb;\n\tstruct i915_wa_list wa_list;\n\tstruct intel_gt_timelines timelines;\n\tstruct intel_gt_requests requests;\n\tstruct {\n\t\tstruct llist_head list;\n\t\tstruct work_struct work;\n\t} watchdog;\n\tstruct intel_wakeref wakeref;\n\tatomic_t user_wakeref;\n\tstruct list_head closed_vma;\n\tspinlock_t closed_lock;\n\tktime_t last_init_time;\n\tstruct intel_reset reset;\n\tintel_wakeref_t awake;\n\tu32 clock_frequency;\n\tu32 clock_period_ns;\n\tstruct intel_llc llc;\n\tstruct intel_rc6 rc6;\n\tstruct intel_rps rps;\n\tspinlock_t *irq_lock;\n\tu32 gt_imr;\n\tu32 pm_ier;\n\tu32 pm_imr;\n\tu32 pm_guc_events;\n\tstruct {\n\t\tbool active;\n\t\tseqcount_mutex_t lock;\n\t\tktime_t total;\n\t\tktime_t start;\n\t} stats;\n\tstruct intel_engine_cs *engine[27];\n\tstruct intel_engine_cs *engine_class[54];\n\tenum intel_submission_method submission_method;\n\tstruct {\n\t\tintel_engine_mask_t cslices;\n\t} ccs;\n\tstruct i915_address_space *vm;\n\tstruct intel_gt_buffer_pool buffer_pool;\n\tstruct i915_vma *scratch;\n\tstruct intel_migrate migrate;\n\tconst struct intel_mmio_range *steering_table[7];\n\tstruct {\n\t\tu8 groupid;\n\t\tu8 instanceid;\n\t} default_steering;\n\tspinlock_t mcr_lock;\n\tphys_addr_t phys_addr;\n\tstruct intel_gt_info info;\n\tstruct {\n\t\tu8 uc_index;\n\t\tu8 wb_index;\n\t} mocs;\n\tstruct kobject sysfs_gt;\n\tstruct gt_defaults defaults;\n\tstruct kobject *sysfs_defaults;\n\tstruct work_struct wedge;\n\tstruct i915_perf_gt perf;\n\tstruct list_head ggtt_link;\n};\n\nstruct intel_gt_bool_throttle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\ti915_reg_t (*reg32)(struct intel_gt *);\n\tu32 mask;\n};\n\nstruct intel_gt_buffer_pool_node {\n\tstruct i915_active active;\n\tstruct drm_i915_gem_object *obj;\n\tstruct list_head link;\n\tunion {\n\t\tstruct intel_gt_buffer_pool *pool;\n\t\tstruct intel_gt_buffer_pool_node *free;\n\t\tstruct callback_head rcu;\n\t};\n\tlong unsigned int age;\n\tenum i915_map_type type;\n\tu32 pinned;\n};\n\nstruct intel_uc_coredump;\n\nstruct intel_gt_coredump {\n\tconst struct intel_gt *_gt;\n\tbool awake;\n\tbool simulated;\n\tstruct intel_gt_info info;\n\tu32 eir;\n\tu32 pgtbl_er;\n\tu32 gtier[6];\n\tu32 ngtier;\n\tu32 forcewake;\n\tu32 error;\n\tu32 err_int;\n\tu32 fault_data0;\n\tu32 fault_data1;\n\tu32 done_reg;\n\tu32 gac_eco;\n\tu32 gam_ecochk;\n\tu32 gab_ctl;\n\tu32 gfx_mode;\n\tu32 gtt_cache;\n\tu32 aux_err;\n\tu32 gam_done;\n\tu32 clock_frequency;\n\tu32 clock_period_ns;\n\tu32 sfc_done[4];\n\tu32 nfence;\n\tu64 fence[32];\n\tstruct intel_engine_coredump *engine;\n\tstruct intel_uc_coredump *uc;\n\tstruct intel_gt_coredump *next;\n};\n\nstruct intel_gt_debugfs_file {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tbool (*eval)(void *);\n};\n\nstruct intel_gt_definition {\n\tenum intel_gt_type type;\n\tchar *name;\n\tu32 mapping_base;\n\tu32 gsi_offset;\n\tintel_engine_mask_t engine_mask;\n};\n\nstruct intel_gtt_driver {\n\tunsigned int gen: 8;\n\tunsigned int is_g33: 1;\n\tunsigned int is_pineview: 1;\n\tunsigned int is_ironlake: 1;\n\tunsigned int has_pgtbl_enable: 1;\n\tunsigned int dma_mask_size: 8;\n\tint (*setup)(void);\n\tvoid (*cleanup)(void);\n\tvoid (*write_entry)(dma_addr_t, unsigned int, unsigned int);\n\tdma_addr_t (*read_entry)(unsigned int, bool *, bool *);\n\tbool (*check_flags)(unsigned int);\n\tvoid (*chipset_flush)(void);\n};\n\nstruct intel_gtt_driver_description {\n\tunsigned int gmch_chip_id;\n\tchar *name;\n\tconst struct intel_gtt_driver *gtt_driver;\n};\n\nstruct intel_guc_state_capture {\n\tconst struct __guc_mmio_reg_descr_group *reglists;\n\tstruct __guc_mmio_reg_descr_group *extlists;\n\tstruct __guc_capture_ads_cache ads_cache[96];\n\tvoid *ads_null_cache;\n\tstruct list_head cachelist;\n\tint max_mmio_per_node;\n\tstruct list_head outlist;\n};\n\nstruct intel_guc_tlb_wait {\n\tstruct wait_queue_head wq;\n\tbool busy;\n};\n\nstruct intel_hdcp_gsc_context {\n\tstruct drm_i915_private *i915;\n\tstruct i915_vma *vma;\n\tvoid *hdcp_cmd_in;\n\tvoid *hdcp_cmd_out;\n};\n\nstruct intel_hdcp_shim {\n\tint (*write_an_aksv)(struct intel_digital_port *, u8 *);\n\tint (*read_bksv)(struct intel_digital_port *, u8 *);\n\tint (*read_bstatus)(struct intel_digital_port *, u8 *);\n\tint (*repeater_present)(struct intel_digital_port *, bool *);\n\tint (*read_ri_prime)(struct intel_digital_port *, u8 *);\n\tint (*read_ksv_ready)(struct intel_digital_port *, bool *);\n\tint (*read_ksv_fifo)(struct intel_digital_port *, int, u8 *);\n\tint (*read_v_prime_part)(struct intel_digital_port *, int, u32 *);\n\tint (*toggle_signalling)(struct intel_digital_port *, enum transcoder, bool);\n\tint (*stream_encryption)(struct intel_connector *, bool);\n\tbool (*check_link)(struct intel_digital_port *, struct intel_connector *);\n\tint (*hdcp_get_capability)(struct intel_digital_port *, bool *);\n\tenum hdcp_wired_protocol protocol;\n\tint (*hdcp_2_2_get_capability)(struct intel_connector *, bool *);\n\tint (*write_2_2_msg)(struct intel_connector *, void *, size_t);\n\tint (*read_2_2_msg)(struct intel_connector *, u8, void *, size_t);\n\tint (*config_stream_type)(struct intel_connector *, bool, u8);\n\tint (*stream_2_2_encryption)(struct intel_connector *, bool);\n\tint (*check_2_2_link)(struct intel_digital_port *, struct intel_connector *);\n\tint (*get_remote_hdcp_capability)(struct intel_connector *, bool *, bool *);\n};\n\nstruct intel_hdmi_lpe_audio_port_pdata {\n\tu8 eld[128];\n\tint port;\n\tint pipe;\n\tint ls_clock;\n\tbool dp_output;\n};\n\nstruct intel_hdmi_lpe_audio_pdata {\n\tstruct intel_hdmi_lpe_audio_port_pdata port[3];\n\tint num_ports;\n\tint num_pipes;\n\tvoid (*notify_audio_lpe)(struct platform_device *, int);\n\tspinlock_t lpe_audio_slock;\n};\n\nstruct intel_hotplug_funcs {\n\tvoid (*hpd_irq_setup)(struct intel_display *);\n\tvoid (*hpd_enable_detection)(struct intel_encoder *);\n};\n\nstruct intel_initial_plane_config {\n\tstruct intel_framebuffer *fb;\n\tstruct intel_memory_region *mem;\n\tresource_size_t phys_base;\n\tstruct i915_vma *vma;\n\tint size;\n\tu32 base;\n\tu8 rotation;\n};\n\nstruct iommu_flush {\n\tvoid (*flush_context)(struct intel_iommu *, u16, u16, u8, u64);\n\tvoid (*flush_iotlb)(struct intel_iommu *, u16, u64, unsigned int, u64);\n};\n\nstruct root_entry;\n\nstruct page_req_dsc;\n\nstruct q_inval;\n\nstruct iommu_pmu;\n\nstruct intel_iommu {\n\tvoid *reg;\n\tu64 reg_phys;\n\tu64 reg_size;\n\tu64 cap;\n\tu64 ecap;\n\tu64 vccap;\n\tu64 ecmdcap[4];\n\tu32 gcmd;\n\traw_spinlock_t register_lock;\n\tint seq_id;\n\tint agaw;\n\tint msagaw;\n\tunsigned int irq;\n\tunsigned int pr_irq;\n\tunsigned int perf_irq;\n\tu16 segment;\n\tunsigned char name[16];\n\tstruct mutex did_lock;\n\tstruct ida domain_ida;\n\tlong unsigned int *copied_tables;\n\tspinlock_t lock;\n\tstruct root_entry *root_entry;\n\tstruct iommu_flush flush;\n\tstruct page_req_dsc *prq;\n\tunsigned char prq_name[16];\n\tlong unsigned int prq_seq_number;\n\tstruct completion prq_complete;\n\tstruct iopf_queue *iopf_queue;\n\tunsigned char iopfq_name[16];\n\tstruct mutex iopf_lock;\n\tstruct q_inval *qi;\n\tu32 iommu_state[4];\n\tstruct rb_root device_rbtree;\n\tspinlock_t device_rbtree_lock;\n\tstruct iommu_device iommu;\n\tint node;\n\tu32 flags;\n\tstruct dmar_drhd_unit *drhd;\n\tvoid *perf_statistic;\n\tstruct iommu_pmu *pmu;\n};\n\nstruct intel_limit {\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} dot;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} vco;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} n;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m1;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m2;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} p;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} p1;\n\tstruct {\n\t\tint dot_limit;\n\t\tint p2_slow;\n\t\tint p2_fast;\n\t} p2;\n};\n\nstruct intel_link_bw_limits {\n\tu8 link_dsc_pipes;\n\tu8 bpp_limit_reached_pipes;\n\tint max_bpp_x16[4];\n};\n\nstruct intel_lvds_pps {\n\tstruct intel_pps_delays delays;\n\tint divider;\n\tint port;\n\tbool powerdown_on_reset;\n};\n\nstruct intel_lvds_encoder {\n\tstruct intel_encoder base;\n\tbool is_dual_link;\n\ti915_reg_t reg;\n\tu32 a3_power;\n\tstruct intel_lvds_pps init_pps;\n\tu32 init_lvds_val;\n\tstruct intel_connector *attached_connector;\n};\n\nstruct intel_memory_region_ops;\n\nstruct intel_memory_region {\n\tstruct drm_i915_private *i915;\n\tconst struct intel_memory_region_ops *ops;\n\tstruct io_mapping iomap;\n\tstruct resource region;\n\tstruct resource io;\n\tresource_size_t min_page_size;\n\tresource_size_t total;\n\tu16 type;\n\tu16 instance;\n\tenum intel_region_id id;\n\tchar name[16];\n\tchar uabi_name[20];\n\tbool private;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct list_head list;\n\t} objects;\n\tbool is_range_manager;\n\tvoid *region_private;\n};\n\nstruct intel_memory_region_ops {\n\tint (*init)(struct intel_memory_region *);\n\tint (*release)(struct intel_memory_region *);\n\tint (*init_object)(struct intel_memory_region *, struct drm_i915_gem_object *, resource_size_t, resource_size_t, resource_size_t, unsigned int);\n};\n\nstruct intel_mmio_range {\n\tu32 start;\n\tu32 end;\n};\n\nstruct intel_modifier_desc {\n\tu64 modifier;\n\tstruct {\n\t\tu8 from;\n\t\tu8 until;\n\t} display_ver;\n\tconst struct drm_format_info *formats;\n\tint format_count;\n\tu8 plane_caps;\n\tstruct {\n\t\tu8 cc_planes: 3;\n\t\tu8 packed_aux_planes: 4;\n\t\tchar: 1;\n\t\tu8 planar_aux_planes: 4;\n\t} ccs;\n};\n\nstruct opregion_header;\n\nstruct opregion_acpi;\n\nstruct opregion_swsci;\n\nstruct opregion_asle;\n\nstruct opregion_asle_ext;\n\nstruct intel_opregion {\n\tstruct intel_display *display;\n\tstruct opregion_header *header;\n\tstruct opregion_acpi *acpi;\n\tstruct opregion_swsci *swsci;\n\tu32 swsci_gbda_sub_functions;\n\tu32 swsci_sbcb_sub_functions;\n\tstruct opregion_asle *asle;\n\tstruct opregion_asle_ext *asle_ext;\n\tvoid *rvda;\n\tconst void *vbt;\n\tu32 vbt_size;\n\tstruct work_struct asle_work;\n\tstruct notifier_block acpi_notifier;\n};\n\nstruct overlay_registers;\n\nstruct intel_overlay {\n\tstruct intel_display *display;\n\tstruct intel_context *context;\n\tstruct intel_crtc *crtc;\n\tstruct i915_vma *vma;\n\tstruct i915_vma *old_vma;\n\tstruct intel_frontbuffer *frontbuffer;\n\tbool active;\n\tbool pfit_active;\n\tu32 pfit_vscale_ratio;\n\tu32 color_key: 24;\n\tu32 color_key_enabled: 1;\n\tu32 brightness;\n\tu32 contrast;\n\tu32 saturation;\n\tu32 old_xscale;\n\tu32 old_yscale;\n\tstruct drm_i915_gem_object *reg_bo;\n\tstruct overlay_registers *regs;\n\tu32 flip_addr;\n\tstruct i915_active last_flip;\n\tvoid (*flip_complete)(struct intel_overlay *);\n};\n\nstruct overlay_registers {\n\tu32 OBUF_0Y;\n\tu32 OBUF_1Y;\n\tu32 OBUF_0U;\n\tu32 OBUF_0V;\n\tu32 OBUF_1U;\n\tu32 OBUF_1V;\n\tu32 OSTRIDE;\n\tu32 YRGB_VPH;\n\tu32 UV_VPH;\n\tu32 HORZ_PH;\n\tu32 INIT_PHS;\n\tu32 DWINPOS;\n\tu32 DWINSZ;\n\tu32 SWIDTH;\n\tu32 SWIDTHSW;\n\tu32 SHEIGHT;\n\tu32 YRGBSCALE;\n\tu32 UVSCALE;\n\tu32 OCLRC0;\n\tu32 OCLRC1;\n\tu32 DCLRKV;\n\tu32 DCLRKM;\n\tu32 SCLRKVH;\n\tu32 SCLRKVL;\n\tu32 SCLRKEN;\n\tu32 OCONFIG;\n\tu32 OCMD;\n\tu32 RESERVED1;\n\tu32 OSTART_0Y;\n\tu32 OSTART_1Y;\n\tu32 OSTART_0U;\n\tu32 OSTART_0V;\n\tu32 OSTART_1U;\n\tu32 OSTART_1V;\n\tu32 OTILEOFF_0Y;\n\tu32 OTILEOFF_1Y;\n\tu32 OTILEOFF_0U;\n\tu32 OTILEOFF_0V;\n\tu32 OTILEOFF_1U;\n\tu32 OTILEOFF_1V;\n\tu32 FASTHSCALE;\n\tu32 UVSCALEV;\n\tu32 RESERVEDC[86];\n\tu16 Y_VCOEFS[51];\n\tu16 RESERVEDD[77];\n\tu16 Y_HCOEFS[85];\n\tu16 RESERVEDE[171];\n\tu16 UV_VCOEFS[51];\n\tu16 RESERVEDF[77];\n\tu16 UV_HCOEFS[51];\n\tu16 RESERVEDG[77];\n};\n\nstruct intel_overlay_snapshot {\n\tstruct overlay_registers regs;\n\tlong unsigned int base;\n\tu32 dovsta;\n\tu32 isr;\n};\n\nstruct intel_package_header {\n\tu8 header_len;\n\tu8 header_ver;\n\tu8 reserved[10];\n\tu32 num_entries;\n};\n\nstruct intel_panel_bl_funcs {\n\tint (*setup)(struct intel_connector *, enum pipe);\n\tu32 (*get)(struct intel_connector *, enum pipe);\n\tvoid (*set)(const struct drm_connector_state *, u32);\n\tvoid (*disable)(const struct drm_connector_state *, u32);\n\tvoid (*enable)(const struct intel_crtc_state *, const struct drm_connector_state *, u32);\n\tu32 (*hz_to_pwm)(struct intel_connector *, u32);\n};\n\nstruct intel_panic {\n\tstruct page **pages;\n\tint page;\n\tvoid *vaddr;\n};\n\nstruct intel_plane_error;\n\nstruct intel_plane {\n\tstruct drm_plane base;\n\tenum i9xx_plane_id i9xx_plane;\n\tenum plane_id id;\n\tenum pipe pipe;\n\tbool need_async_flip_toggle_wa;\n\tu8 vtd_guard;\n\tu32 frontbuffer_bit;\n\tstruct {\n\t\tu32 base;\n\t\tu32 cntl;\n\t\tu32 size;\n\t} cursor;\n\tstruct intel_fbc *fbc;\n\tint (*min_width)(const struct drm_framebuffer *, int, unsigned int);\n\tint (*max_width)(const struct drm_framebuffer *, int, unsigned int);\n\tint (*max_height)(const struct drm_framebuffer *, int, unsigned int);\n\tunsigned int (*min_alignment)(struct intel_plane *, const struct drm_framebuffer *, int);\n\tunsigned int (*max_stride)(struct intel_plane *, const struct drm_format_info *, u64, unsigned int);\n\tbool (*can_async_flip)(u64);\n\tvoid (*update_noarm)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *, const struct intel_plane_state *);\n\tvoid (*update_arm)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *, const struct intel_plane_state *);\n\tvoid (*disable_arm)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *);\n\tvoid (*capture_error)(struct intel_crtc *, struct intel_plane *, struct intel_plane_error *);\n\tbool (*get_hw_state)(struct intel_plane *, enum pipe *);\n\tint (*check_plane)(struct intel_crtc_state *, struct intel_plane_state *);\n\tu32 (*surf_offset)(const struct intel_plane_state *);\n\tint (*min_cdclk)(const struct intel_crtc_state *, const struct intel_plane_state *);\n\tvoid (*async_flip)(struct intel_dsb *, struct intel_plane *, const struct intel_crtc_state *, const struct intel_plane_state *, bool);\n\tvoid (*enable_flip_done)(struct intel_plane *);\n\tvoid (*disable_flip_done)(struct intel_plane *);\n\tvoid (*disable_tiling)(struct intel_plane *);\n};\n\nstruct intel_plane_error {\n\tu32 ctl;\n\tu32 surf;\n\tu32 surflive;\n};\n\nstruct intel_plane_state {\n\tstruct drm_plane_state uapi;\n\tstruct {\n\t\tstruct drm_crtc *crtc;\n\t\tstruct drm_framebuffer *fb;\n\t\tu16 alpha;\n\t\tu16 pixel_blend_mode;\n\t\tunsigned int rotation;\n\t\tenum drm_color_encoding color_encoding;\n\t\tenum drm_color_range color_range;\n\t\tenum drm_scaling_filter scaling_filter;\n\t\tstruct drm_property_blob *ctm;\n\t\tstruct drm_property_blob *degamma_lut;\n\t\tstruct drm_property_blob *gamma_lut;\n\t\tstruct drm_property_blob *lut_3d;\n\t} hw;\n\tstruct i915_vma *ggtt_vma;\n\tstruct i915_vma *dpt_vma;\n\tlong unsigned int flags;\n\tstruct intel_fb_view view;\n\tstruct drm_vblank_work unpin_work;\n\tbool decrypt;\n\tbool force_black;\n\tbool is_y_plane;\n\tu32 ctl;\n\tu32 color_ctl;\n\tu32 cus_ctl;\n\tu32 surf;\n\tint scaler_id;\n\tstruct intel_plane *planar_linked_plane;\n\tstruct drm_intel_sprite_colorkey ckey;\n\tstruct drm_rect psr2_sel_fetch_area;\n\tu64 ccval;\n\tconst char *no_fbc_reason;\n\tstruct drm_rect damage;\n};\n\nstruct pmdemand_params {\n\tu16 qclk_gv_bw;\n\tu8 voltage_index;\n\tu8 qclk_gv_index;\n\tu8 active_pipes;\n\tu8 active_dbufs;\n\tu8 active_phys;\n\tu8 plls;\n\tu16 cdclk_freq_mhz;\n\tu16 ddiclk_max;\n\tu8 scalers;\n};\n\nstruct intel_pmdemand_state {\n\tstruct intel_global_state base;\n\tint ddi_clocks[4];\n\tu16 active_combo_phys_mask;\n\tstruct pmdemand_params params;\n};\n\nstruct intel_psf_gv_point {\n\tu8 clk;\n};\n\nstruct intel_pxp {\n\tstruct intel_gt *ctrl_gt;\n\tbool platform_cfg_is_bad;\n\tu32 kcr_base;\n\tstruct gsccs_session_resources gsccs_res;\n\tstruct i915_pxp_component *pxp_component;\n\tstruct device_link *dev_link;\n\tbool pxp_component_added;\n\tstruct intel_context *ce;\n\tstruct mutex arb_mutex;\n\tbool arb_is_valid;\n\tu32 key_instance;\n\tstruct mutex tee_mutex;\n\tstruct {\n\t\tstruct drm_i915_gem_object *obj;\n\t\tvoid *vaddr;\n\t} stream_cmd;\n\tbool hw_state_invalidated;\n\tbool irq_enabled;\n\tstruct completion termination;\n\tstruct work_struct session_work;\n\tu32 session_events;\n};\n\nstruct intel_qgv_point {\n\tu16 dclk;\n\tu16 t_rp;\n\tu16 t_rdpre;\n\tu16 t_rc;\n\tu16 t_ras;\n\tu16 t_rcd;\n};\n\nstruct intel_qgv_info {\n\tstruct intel_qgv_point points[8];\n\tstruct intel_psf_gv_point psf_points[3];\n\tu8 num_points;\n\tu8 num_psf_points;\n\tu8 t_bl;\n\tu8 max_numchannels;\n\tu8 channel_width;\n\tu8 deinterleave;\n};\n\nstruct intel_quirk {\n\tint device;\n\tint subsystem_vendor;\n\tint subsystem_device;\n\tvoid (*hook)(struct intel_display *);\n};\n\nstruct intel_renderstate_rodata;\n\nstruct intel_renderstate {\n\tstruct i915_gem_ww_ctx ww;\n\tconst struct intel_renderstate_rodata *rodata;\n\tstruct i915_vma *vma;\n\tu32 batch_offset;\n\tu32 batch_size;\n\tu32 aux_offset;\n\tu32 aux_size;\n};\n\nstruct intel_renderstate_rodata {\n\tconst u32 *reloc;\n\tconst u32 *batch;\n\tconst u32 batch_items;\n};\n\nstruct intel_ring {\n\tstruct kref ref;\n\tstruct i915_vma *vma;\n\tvoid *vaddr;\n\tatomic_t pin_count;\n\tu32 head;\n\tu32 tail;\n\tu32 emit;\n\tu32 space;\n\tu32 size;\n\tu32 wrap;\n\tu32 effective_size;\n};\n\nstruct intel_rom {\n\tstruct pci_dev *pdev;\n\tvoid *oprom;\n\tstruct intel_uncore *uncore;\n\tloff_t offset;\n\tsize_t size;\n\tu32 (*read32)(struct intel_rom *, loff_t);\n\tu16 (*read16)(struct intel_rom *, loff_t);\n\tvoid (*read_block)(struct intel_rom *, void *, loff_t, size_t);\n\tvoid (*free)(struct intel_rom *);\n};\n\nstruct intel_rps_freq_caps {\n\tu8 rp0_freq;\n\tu8 rp1_freq;\n\tu8 min_freq;\n};\n\nstruct intel_sa_info {\n\tu16 displayrtids;\n\tu8 deburst;\n\tu8 deprogbwlimit;\n\tu8 derating;\n};\n\nstruct intel_sdvo;\n\nstruct intel_sdvo_ddc {\n\tstruct i2c_adapter ddc;\n\tstruct intel_sdvo *sdvo;\n\tu8 ddc_bus;\n};\n\nstruct intel_sdvo_caps {\n\tu8 vendor_id;\n\tu8 device_id;\n\tu8 device_rev_id;\n\tu8 sdvo_version_major;\n\tu8 sdvo_version_minor;\n\tunsigned int sdvo_num_inputs: 2;\n\tunsigned int smooth_scaling: 1;\n\tunsigned int sharp_scaling: 1;\n\tunsigned int up_scaling: 1;\n\tunsigned int down_scaling: 1;\n\tunsigned int stall_support: 1;\n\tunsigned int pad: 1;\n\tu16 output_flags;\n};\n\nstruct intel_sdvo {\n\tstruct intel_encoder base;\n\tstruct i2c_adapter *i2c;\n\tu8 target_addr;\n\tstruct intel_sdvo_ddc ddc[3];\n\ti915_reg_t sdvo_reg;\n\tstruct intel_sdvo_caps caps;\n\tu8 colorimetry_cap;\n\tint pixel_clock_min;\n\tint pixel_clock_max;\n\tu16 hotplug_active;\n\tu8 dtd_sdvo_flags;\n};\n\nstruct intel_sdvo_connector {\n\tstruct intel_connector base;\n\tu16 output_flag;\n\tu8 tv_format_supported[19];\n\tint format_supported_num;\n\tstruct drm_property *tv_format;\n\tstruct drm_property *left;\n\tstruct drm_property *right;\n\tstruct drm_property *top;\n\tstruct drm_property *bottom;\n\tstruct drm_property *hpos;\n\tstruct drm_property *vpos;\n\tstruct drm_property *contrast;\n\tstruct drm_property *saturation;\n\tstruct drm_property *hue;\n\tstruct drm_property *sharpness;\n\tstruct drm_property *flicker_filter;\n\tstruct drm_property *flicker_filter_adaptive;\n\tstruct drm_property *flicker_filter_2d;\n\tstruct drm_property *tv_chroma_filter;\n\tstruct drm_property *tv_luma_filter;\n\tstruct drm_property *dot_crawl;\n\tstruct drm_property *brightness;\n\tu32 max_hscan;\n\tu32 max_vscan;\n\tbool is_hdmi;\n};\n\nstruct intel_sdvo_connector_state {\n\tstruct intel_digital_connector_state base;\n\tstruct {\n\t\tunsigned int overscan_h;\n\t\tunsigned int overscan_v;\n\t\tunsigned int hpos;\n\t\tunsigned int vpos;\n\t\tunsigned int sharpness;\n\t\tunsigned int flicker_filter;\n\t\tunsigned int flicker_filter_2d;\n\t\tunsigned int flicker_filter_adaptive;\n\t\tunsigned int chroma_filter;\n\t\tunsigned int luma_filter;\n\t\tunsigned int dot_crawl;\n\t} tv;\n};\n\nstruct intel_sdvo_dtd {\n\tstruct {\n\t\tu16 clock;\n\t\tu8 h_active;\n\t\tu8 h_blank;\n\t\tu8 h_high;\n\t\tu8 v_active;\n\t\tu8 v_blank;\n\t\tu8 v_high;\n\t} part1;\n\tstruct {\n\t\tu8 h_sync_off;\n\t\tu8 h_sync_width;\n\t\tu8 v_sync_off_width;\n\t\tu8 sync_off_width_high;\n\t\tu8 dtd_flags;\n\t\tu8 sdvo_flags;\n\t\tu8 v_sync_off_high;\n\t\tu8 reserved;\n\t} part2;\n};\n\nstruct intel_sdvo_encode {\n\tu8 dvi_rev;\n\tu8 hdmi_rev;\n};\n\nstruct intel_sdvo_enhancements_reply {\n\tunsigned int flicker_filter: 1;\n\tunsigned int flicker_filter_adaptive: 1;\n\tunsigned int flicker_filter_2d: 1;\n\tunsigned int saturation: 1;\n\tunsigned int hue: 1;\n\tunsigned int brightness: 1;\n\tunsigned int contrast: 1;\n\tunsigned int overscan_h: 1;\n\tunsigned int overscan_v: 1;\n\tunsigned int hpos: 1;\n\tunsigned int vpos: 1;\n\tunsigned int sharpness: 1;\n\tunsigned int dot_crawl: 1;\n\tunsigned int dither: 1;\n\tunsigned int tv_chroma_filter: 1;\n\tunsigned int tv_luma_filter: 1;\n} __attribute__((packed));\n\nstruct intel_sdvo_get_trained_inputs_response {\n\tunsigned int input0_trained: 1;\n\tunsigned int input1_trained: 1;\n\tunsigned int pad: 6;\n} __attribute__((packed));\n\nstruct intel_sdvo_in_out_map {\n\tu16 in0;\n\tu16 in1;\n};\n\nstruct intel_sdvo_pixel_clock_range {\n\tu16 min;\n\tu16 max;\n};\n\nstruct intel_sdvo_preferred_input_timing_args {\n\tu16 clock;\n\tu16 width;\n\tu16 height;\n\tu8 interlace: 1;\n\tu8 scaled: 1;\n\tu8 pad: 6;\n} __attribute__((packed));\n\nstruct intel_sdvo_sdtv_resolution_request {\n\tunsigned int ntsc_m: 1;\n\tunsigned int ntsc_j: 1;\n\tunsigned int ntsc_443: 1;\n\tunsigned int pal_b: 1;\n\tunsigned int pal_d: 1;\n\tunsigned int pal_g: 1;\n\tunsigned int pal_h: 1;\n\tunsigned int pal_i: 1;\n\tunsigned int pal_m: 1;\n\tunsigned int pal_n: 1;\n\tunsigned int pal_nc: 1;\n\tunsigned int pal_60: 1;\n\tunsigned int secam_b: 1;\n\tunsigned int secam_d: 1;\n\tunsigned int secam_g: 1;\n\tunsigned int secam_k: 1;\n\tunsigned int secam_k1: 1;\n\tunsigned int secam_l: 1;\n\tunsigned int secam_60: 1;\n\tunsigned int pad: 5;\n} __attribute__((packed));\n\nstruct intel_sdvo_set_target_input_args {\n\tunsigned int target_1: 1;\n\tunsigned int pad: 7;\n} __attribute__((packed));\n\nstruct intel_sdvo_tv_format {\n\tunsigned int ntsc_m: 1;\n\tunsigned int ntsc_j: 1;\n\tunsigned int ntsc_443: 1;\n\tunsigned int pal_b: 1;\n\tunsigned int pal_d: 1;\n\tunsigned int pal_g: 1;\n\tunsigned int pal_h: 1;\n\tunsigned int pal_i: 1;\n\tunsigned int pal_m: 1;\n\tunsigned int pal_n: 1;\n\tunsigned int pal_nc: 1;\n\tunsigned int pal_60: 1;\n\tunsigned int secam_b: 1;\n\tunsigned int secam_d: 1;\n\tunsigned int secam_g: 1;\n\tunsigned int secam_k: 1;\n\tunsigned int secam_k1: 1;\n\tunsigned int secam_l: 1;\n\tunsigned int secam_60: 1;\n\tunsigned int hdtv_std_smpte_240m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_240m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_260m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_260m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_50: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_23: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_24: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_25: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_29: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_30: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_50: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_59: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_60: 1;\n\tunsigned int hdtv_std_smpte_295m_1080i_50: 1;\n\tunsigned int hdtv_std_smpte_295m_1080p_50: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_59: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_60: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_50: 1;\n\tunsigned int hdtv_std_smpte_293m_480p_59: 1;\n\tunsigned int hdtv_std_smpte_170m_480i_59: 1;\n\tunsigned int hdtv_std_iturbt601_576i_50: 1;\n\tunsigned int hdtv_std_iturbt601_576p_50: 1;\n\tunsigned int hdtv_std_eia_7702a_480i_60: 1;\n\tunsigned int hdtv_std_eia_7702a_480p_60: 1;\n\tunsigned int pad: 3;\n} __attribute__((packed));\n\nstruct intel_shared_regs {\n\tstruct er_account regs[11];\n\tint refcnt;\n\tunsigned int core_id;\n};\n\nstruct intel_stolen_node {\n\tstruct drm_i915_private *i915;\n\tstruct drm_mm_node node;\n};\n\nstruct intel_tc_phy_ops {\n\tenum intel_display_power_domain (*cold_off_domain)(struct intel_tc_port *);\n\tu32 (*hpd_live_status)(struct intel_tc_port *);\n\tbool (*is_ready)(struct intel_tc_port *);\n\tbool (*is_owned)(struct intel_tc_port *);\n\tvoid (*get_hw_state)(struct intel_tc_port *);\n\tbool (*connect)(struct intel_tc_port *, int);\n\tvoid (*disconnect)(struct intel_tc_port *);\n\tvoid (*init)(struct intel_tc_port *);\n};\n\nstruct intel_tc_port {\n\tstruct intel_digital_port *dig_port;\n\tconst struct intel_tc_phy_ops *phy_ops;\n\tstruct mutex lock;\n\tstruct ref_tracker *lock_wakeref;\n\tstruct delayed_work disconnect_phy_work;\n\tstruct delayed_work link_reset_work;\n\tint link_refcount;\n\tbool legacy_port: 1;\n\tconst char *port_name;\n\tenum tc_port_mode mode;\n\tenum tc_port_mode init_mode;\n\tenum phy_fia phy_fia;\n\tenum intel_tc_pin_assignment pin_assignment;\n\tu8 phy_fia_idx;\n\tu8 max_lane_count;\n};\n\nstruct intel_timeline {\n\tu64 fence_context;\n\tu32 seqno;\n\tstruct mutex mutex;\n\tatomic_t pin_count;\n\tatomic_t active_count;\n\tvoid *hwsp_map;\n\tconst u32 *hwsp_seqno;\n\tstruct i915_vma *hwsp_ggtt;\n\tu32 hwsp_offset;\n\tbool has_initial_breadcrumb;\n\tstruct list_head requests;\n\tstruct i915_active_fence last_request;\n\tstruct i915_active active;\n\tstruct intel_timeline *retire;\n\tstruct i915_syncmap *sync;\n\tstruct list_head link;\n\tstruct intel_gt *gt;\n\tstruct list_head engine_link;\n\tstruct kref kref;\n\tstruct callback_head rcu;\n};\n\nstruct intel_tv {\n\tstruct intel_encoder base;\n\tint type;\n};\n\nstruct intel_tv_connector_state {\n\tstruct drm_connector_state base;\n\tstruct {\n\t\tu16 top;\n\t\tu16 bottom;\n\t} margins;\n\tbool bypass_vfilter;\n};\n\nstruct intel_uc_coredump {\n\tstruct intel_uc_fw guc_fw;\n\tstruct intel_uc_fw huc_fw;\n\tstruct guc_info guc;\n};\n\nstruct intel_uc_ops {\n\tint (*sanitize)(struct intel_uc *);\n\tvoid (*init_fw)(struct intel_uc *);\n\tvoid (*fini_fw)(struct intel_uc *);\n\tint (*init)(struct intel_uc *);\n\tvoid (*fini)(struct intel_uc *);\n\tint (*init_hw)(struct intel_uc *);\n\tvoid (*fini_hw)(struct intel_uc *);\n\tvoid (*resume_mappings)(struct intel_uc *);\n};\n\nstruct intel_uncore_extra_reg {\n\traw_spinlock_t lock;\n\tu64 config;\n\tu64 config1;\n\tu64 config2;\n\tatomic_t ref;\n};\n\nstruct intel_uncore_pmu;\n\nstruct intel_uncore_box {\n\tint dieid;\n\tint n_active;\n\tint n_events;\n\tint cpu;\n\tlong unsigned int flags;\n\tatomic_t refcnt;\n\tstruct perf_event *events[10];\n\tstruct perf_event *event_list[10];\n\tstruct event_constraint *event_constraint[10];\n\tlong unsigned int active_mask[1];\n\tu64 tags[10];\n\tstruct pci_dev *pci_dev;\n\tstruct intel_uncore_pmu *pmu;\n\tu64 hrtimer_duration;\n\tstruct hrtimer hrtimer;\n\tstruct list_head list;\n\tstruct list_head active_list;\n\tvoid *io_addr;\n\tstruct intel_uncore_extra_reg shared_regs[0];\n};\n\nstruct intel_uncore_discovery_type {\n\tstruct rb_node node;\n\tenum uncore_access_type access_type;\n\tstruct rb_root units;\n\tu16 type;\n\tu8 num_counters;\n\tu8 counter_width;\n\tu8 ctl_offset;\n\tu8 ctr_offset;\n\tu16 num_units;\n};\n\nstruct intel_uncore_discovery_unit {\n\tstruct rb_node node;\n\tunsigned int pmu_idx;\n\tunsigned int id;\n\tunsigned int die;\n\tu64 addr;\n};\n\nstruct intel_uncore_forcewake_domain {\n\tstruct intel_uncore *uncore;\n\tenum forcewake_domain_id id;\n\tenum forcewake_domains mask;\n\tunsigned int wake_count;\n\tbool active;\n\tstruct hrtimer timer;\n\tu32 *reg_set;\n\tu32 *reg_ack;\n};\n\nstruct intel_uncore_fw_get {\n\tvoid (*force_wake_get)(struct intel_uncore *, enum forcewake_domains);\n};\n\nstruct intel_uncore_ops {\n\tvoid (*init_box)(struct intel_uncore_box *);\n\tvoid (*exit_box)(struct intel_uncore_box *);\n\tvoid (*disable_box)(struct intel_uncore_box *);\n\tvoid (*enable_box)(struct intel_uncore_box *);\n\tvoid (*disable_event)(struct intel_uncore_box *, struct perf_event *);\n\tvoid (*enable_event)(struct intel_uncore_box *, struct perf_event *);\n\tu64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);\n\tint (*hw_config)(struct intel_uncore_box *, struct perf_event *);\n\tstruct event_constraint * (*get_constraint)(struct intel_uncore_box *, struct perf_event *);\n\tvoid (*put_constraint)(struct intel_uncore_box *, struct perf_event *);\n};\n\nstruct intel_uncore_type;\n\nstruct intel_uncore_pmu {\n\tstruct pmu pmu;\n\tchar name[32];\n\tint pmu_idx;\n\tbool registered;\n\tatomic_t activeboxes;\n\tcpumask_t cpu_mask;\n\tstruct intel_uncore_type *type;\n\tstruct intel_uncore_box **boxes;\n};\n\nstruct uncore_iio_topology;\n\nstruct uncore_upi_topology;\n\nstruct intel_uncore_topology {\n\tint pmu_idx;\n\tunion {\n\t\tvoid *untyped;\n\t\tstruct uncore_iio_topology *iio;\n\t\tstruct uncore_upi_topology *upi;\n\t};\n};\n\nstruct uncore_event_desc;\n\nstruct intel_uncore_type {\n\tconst char *name;\n\tint num_counters;\n\tint num_boxes;\n\tint perf_ctr_bits;\n\tint fixed_ctr_bits;\n\tint num_freerunning_types;\n\tint type_id;\n\tunsigned int perf_ctr;\n\tunsigned int event_ctl;\n\tunsigned int event_mask;\n\tunsigned int event_mask_ext;\n\tunsigned int fixed_ctr;\n\tunsigned int fixed_ctl;\n\tunsigned int box_ctl;\n\tunion {\n\t\tunsigned int msr_offset;\n\t\tunsigned int mmio_offset;\n\t};\n\tunsigned int mmio_map_size;\n\tunsigned int num_shared_regs: 8;\n\tunsigned int single_fixed: 1;\n\tunsigned int pair_ctr_ctl: 1;\n\tunion {\n\t\tu64 *msr_offsets;\n\t\tu64 *pci_offsets;\n\t\tu64 *mmio_offsets;\n\t};\n\tstruct event_constraint unconstrainted;\n\tstruct event_constraint *constraints;\n\tstruct intel_uncore_pmu *pmus;\n\tstruct intel_uncore_ops *ops;\n\tstruct uncore_event_desc *event_descs;\n\tstruct freerunning_counters *freerunning;\n\tconst struct attribute_group *attr_groups[4];\n\tconst struct attribute_group **attr_update;\n\tstruct pmu *pmu;\n\tstruct rb_root *boxes;\n\tstruct intel_uncore_topology **topology;\n\tint (*get_topology)(struct intel_uncore_type *);\n\tvoid (*set_mapping)(struct intel_uncore_type *);\n\tvoid (*cleanup_mapping)(struct intel_uncore_type *);\n\tvoid (*cleanup_extra_boxes)(struct intel_uncore_type *);\n};\n\nstruct intel_vblank_evade_ctx {\n\tstruct intel_crtc *crtc;\n\tint min;\n\tint max;\n\tint vblank_start;\n\tbool need_vlv_dsi_wa;\n};\n\nstruct intel_wakeref_lockclass {\n\tstruct lock_class_key mutex;\n\tstruct lock_class_key work;\n};\n\nstruct intel_wakeref_ops {\n\tint (*get)(struct intel_wakeref *);\n\tint (*put)(struct intel_wakeref *);\n};\n\nstruct intel_watermark_params {\n\tu16 fifo_size;\n\tu16 max_wm;\n\tu8 default_wm;\n\tu8 guard_size;\n\tu8 cacheline_size;\n};\n\nstruct intel_wedge_me {\n\tstruct delayed_work work;\n\tstruct intel_gt *gt;\n\tconst char *name;\n};\n\nstruct intel_wm_config {\n\tunsigned int num_pipes_active;\n\tbool sprites_enabled;\n\tbool sprites_scaled;\n};\n\nstruct intel_wm_funcs {\n\tvoid (*update_wm)(struct intel_display *);\n\tint (*compute_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*initial_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*atomic_update_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*optimize_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tint (*compute_global_watermarks)(struct intel_atomic_state *);\n\tvoid (*get_hw_state)(struct intel_display *);\n\tvoid (*sanitize)(struct intel_display *);\n};\n\nunion intel_x86_pebs_dse {\n\tu64 val;\n\tstruct {\n\t\tunsigned int ld_dse: 4;\n\t\tunsigned int ld_stlb_miss: 1;\n\t\tunsigned int ld_locked: 1;\n\t\tunsigned int ld_data_blk: 1;\n\t\tunsigned int ld_addr_blk: 1;\n\t\tunsigned int ld_reserved: 24;\n\t};\n\tstruct {\n\t\tunsigned int st_l1d_hit: 1;\n\t\tunsigned int st_reserved1: 3;\n\t\tunsigned int st_stlb_miss: 1;\n\t\tunsigned int st_locked: 1;\n\t\tunsigned int st_reserved2: 26;\n\t};\n\tstruct {\n\t\tunsigned int st_lat_dse: 4;\n\t\tunsigned int st_lat_stlb_miss: 1;\n\t\tunsigned int st_lat_locked: 1;\n\t\tunsigned int ld_reserved3: 26;\n\t};\n\tstruct {\n\t\tunsigned int mtl_dse: 5;\n\t\tunsigned int mtl_locked: 1;\n\t\tunsigned int mtl_stlb_miss: 1;\n\t\tunsigned int mtl_fwd_blk: 1;\n\t\tunsigned int ld_reserved4: 24;\n\t};\n\tstruct {\n\t\tunsigned int lnc_dse: 8;\n\t\tunsigned int ld_reserved5: 2;\n\t\tunsigned int lnc_stlb_miss: 1;\n\t\tunsigned int lnc_locked: 1;\n\t\tunsigned int lnc_data_blk: 1;\n\t\tunsigned int lnc_addr_blk: 1;\n\t\tunsigned int ld_reserved6: 18;\n\t};\n\tstruct {\n\t\tunsigned int pnc_dse: 8;\n\t\tunsigned int pnc_l2_miss: 1;\n\t\tunsigned int pnc_stlb_clean_hit: 1;\n\t\tunsigned int pnc_stlb_any_hit: 1;\n\t\tunsigned int pnc_stlb_miss: 1;\n\t\tunsigned int pnc_locked: 1;\n\t\tunsigned int pnc_data_blk: 1;\n\t\tunsigned int pnc_addr_blk: 1;\n\t\tunsigned int pnc_fb_full: 1;\n\t\tunsigned int ld_reserved8: 16;\n\t};\n\tstruct {\n\t\tunsigned int arw_dse: 8;\n\t\tunsigned int arw_l2_miss: 1;\n\t\tunsigned int arw_xq_promotion: 1;\n\t\tunsigned int arw_reissue: 1;\n\t\tunsigned int arw_stlb_miss: 1;\n\t\tunsigned int arw_locked: 1;\n\t\tunsigned int arw_data_blk: 1;\n\t\tunsigned int arw_addr_blk: 1;\n\t\tunsigned int arw_fb_full: 1;\n\t\tunsigned int ld_reserved9: 16;\n\t};\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct io {\n\tlong unsigned int error_bits;\n\tatomic_t count;\n\tstruct dm_io_client *client;\n\tio_notify_fn callback;\n\tvoid *context;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n\tlong: 64;\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct io_apic {\n\tunsigned int index;\n\tunsigned int unused[3];\n\tunsigned int data;\n\tunsigned int unused2[11];\n\tunsigned int eoi;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bitmap {\n\tu64 sequence;\n\trefcount_t refcnt;\n\tunsigned int max;\n\tlong unsigned int bitmap[1024];\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_err_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[1];\n\tlong unsigned int sqe_op[2];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 64;\n\tlong: 64;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tlb_area {\n\tlong unsigned int used;\n\tunsigned int index;\n\tspinlock_t lock;\n};\n\nstruct io_tlb_slot;\n\nstruct io_tlb_pool {\n\tphys_addr_t start;\n\tphys_addr_t end;\n\tvoid *vaddr;\n\tlong unsigned int nslabs;\n\tbool late_alloc;\n\tunsigned int nareas;\n\tunsigned int area_nslabs;\n\tstruct io_tlb_area *areas;\n\tstruct io_tlb_slot *slots;\n};\n\nstruct io_tlb_mem {\n\tstruct io_tlb_pool defpool;\n\tlong unsigned int nslabs;\n\tstruct dentry *debugfs;\n\tbool force_bounce;\n\tbool for_alloc;\n\tatomic_long_t total_used;\n\tatomic_long_t used_hiwater;\n\tatomic_long_t transient_nslabs;\n};\n\nstruct io_tlb_slot {\n\tphys_addr_t orig_addr;\n\tsize_t alloc_size;\n\tshort unsigned int list;\n\tshort unsigned int pad_slots;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 64;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_window_t {\n\tu_int InUse;\n\tu_int Config;\n\tstruct resource *res;\n};\n\ntypedef struct io_window_t io_window_t;\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[64];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n\tlong: 64;\n};\n\nstruct ioam6_hdr {\n\t__u8 opt_type;\n\t__u8 opt_len;\n\tchar: 8;\n\t__u8 type;\n};\n\nstruct ioam6_schema;\n\nstruct ioam6_namespace {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_schema *schema;\n\t__be16 id;\n\t__be32 data;\n\t__be64 data_wide;\n};\n\nstruct ioam6_pernet_data {\n\tstruct mutex lock;\n\tstruct rhashtable namespaces;\n\tstruct rhashtable schemas;\n};\n\nstruct ioam6_schema {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_namespace *ns;\n\tu32 id;\n\tint len;\n\t__be32 hdr;\n\tu8 data[0];\n};\n\nstruct ioam6_trace_hdr {\n\t__be16 namespace_id;\n\tchar: 2;\n\t__u8 overflow: 1;\n\t__u8 nodelen: 5;\n\t__u8 remlen: 7;\n\tunion {\n\t\t__be32 type_be32;\n\t\tstruct {\n\t\t\t__u32 bit7: 1;\n\t\t\t__u32 bit6: 1;\n\t\t\t__u32 bit5: 1;\n\t\t\t__u32 bit4: 1;\n\t\t\t__u32 bit3: 1;\n\t\t\t__u32 bit2: 1;\n\t\t\t__u32 bit1: 1;\n\t\t\t__u32 bit0: 1;\n\t\t\t__u32 bit15: 1;\n\t\t\t__u32 bit14: 1;\n\t\t\t__u32 bit13: 1;\n\t\t\t__u32 bit12: 1;\n\t\t\t__u32 bit11: 1;\n\t\t\t__u32 bit10: 1;\n\t\t\t__u32 bit9: 1;\n\t\t\t__u32 bit8: 1;\n\t\t\t__u32 bit23: 1;\n\t\t\t__u32 bit22: 1;\n\t\t\t__u32 bit21: 1;\n\t\t\t__u32 bit20: 1;\n\t\t\t__u32 bit19: 1;\n\t\t\t__u32 bit18: 1;\n\t\t\t__u32 bit17: 1;\n\t\t\t__u32 bit16: 1;\n\t\t} type;\n\t};\n\t__u8 data[0];\n};\n\nstruct mpc_ioapic {\n\tunsigned char type;\n\tunsigned char apicid;\n\tunsigned char apicver;\n\tunsigned char flags;\n\tunsigned int apicaddr;\n};\n\nstruct mp_ioapic_gsi {\n\tu32 gsi_base;\n\tu32 gsi_end;\n};\n\nstruct irq_domain_ops;\n\nstruct ioapic_domain_cfg {\n\tenum ioapic_domain_type type;\n\tconst struct irq_domain_ops *ops;\n\tstruct device_node *dev;\n};\n\nstruct ioapic {\n\tint nr_registers;\n\tstruct IO_APIC_route_entry *saved_registers;\n\tstruct mpc_ioapic mp_config;\n\tstruct mp_ioapic_gsi gsi_config;\n\tstruct ioapic_domain_cfg irqdomain_cfg;\n\tstruct irq_domain *irqdomain;\n\tstruct resource *iomem_res;\n};\n\nstruct ioapic_alloc_info {\n\tint pin;\n\tint node;\n\tu32 is_level: 1;\n\tu32 active_low: 1;\n\tu32 valid: 1;\n};\n\nstruct ioc_params {\n\tu32 qos[6];\n\tu64 i_lcoefs[6];\n\tu64 lcoefs[6];\n\tu32 too_fast_vrate_pct;\n\tu32 too_slow_vrate_pct;\n};\n\nstruct ioc_margins {\n\ts64 min;\n\ts64 low;\n\ts64 target;\n};\n\nstruct ioc_pcpu_stat;\n\nstruct ioc {\n\tstruct rq_qos rqos;\n\tbool enabled;\n\tstruct ioc_params params;\n\tstruct ioc_margins margins;\n\tu32 period_us;\n\tu32 timer_slack_ns;\n\tu64 vrate_min;\n\tu64 vrate_max;\n\tspinlock_t lock;\n\tstruct timer_list timer;\n\tstruct list_head active_iocgs;\n\tstruct ioc_pcpu_stat *pcpu_stat;\n\tenum ioc_running running;\n\tatomic64_t vtime_rate;\n\tu64 vtime_base_rate;\n\ts64 vtime_err;\n\tseqcount_spinlock_t period_seqcount;\n\tu64 period_at;\n\tu64 period_at_vtime;\n\tatomic64_t cur_period;\n\tint busy_level;\n\tbool weights_updated;\n\tatomic_t hweight_gen;\n\tu64 dfgv_period_at;\n\tu64 dfgv_period_rem;\n\tu64 dfgv_usage_us_sum;\n\tu64 autop_too_fast_at;\n\tu64 autop_too_slow_at;\n\tint autop_idx;\n\tbool user_qos_params: 1;\n\tbool user_cost_model: 1;\n};\n\nstruct ioc_cgrp {\n\tstruct blkcg_policy_data cpd;\n\tunsigned int dfl_weight;\n};\n\nstruct iocg_stat {\n\tu64 usage_us;\n\tu64 wait_us;\n\tu64 indebt_us;\n\tu64 indelay_us;\n};\n\nstruct iocg_pcpu_stat;\n\nstruct ioc_gq {\n\tstruct blkg_policy_data pd;\n\tstruct ioc *ioc;\n\tu32 cfg_weight;\n\tu32 weight;\n\tu32 active;\n\tu32 inuse;\n\tu32 last_inuse;\n\ts64 saved_margin;\n\tsector_t cursor;\n\tatomic64_t vtime;\n\tatomic64_t done_vtime;\n\tu64 abs_vdebt;\n\tu64 delay;\n\tu64 delay_at;\n\tatomic64_t active_period;\n\tstruct list_head active_list;\n\tu64 child_active_sum;\n\tu64 child_inuse_sum;\n\tu64 child_adjusted_sum;\n\tint hweight_gen;\n\tu32 hweight_active;\n\tu32 hweight_inuse;\n\tu32 hweight_donating;\n\tu32 hweight_after_donation;\n\tstruct list_head walk_list;\n\tstruct list_head surplus_list;\n\tstruct wait_queue_head waitq;\n\tstruct hrtimer waitq_timer;\n\tu64 activated_at;\n\tstruct iocg_pcpu_stat *pcpu_stat;\n\tstruct iocg_stat stat;\n\tstruct iocg_stat last_stat;\n\tu64 last_stat_abs_vusage;\n\tu64 usage_delta_us;\n\tu64 wait_since;\n\tu64 indebt_since;\n\tu64 indelay_since;\n\tint level;\n\tstruct ioc_gq *ancestors[0];\n};\n\nstruct ioc_missed {\n\tlocal_t nr_met;\n\tlocal_t nr_missed;\n\tu32 last_met;\n\tu32 last_missed;\n};\n\nstruct ioc_now {\n\tu64 now_ns;\n\tu64 now;\n\tu64 vnow;\n};\n\nstruct ioc_pcpu_stat {\n\tstruct ioc_missed missed[2];\n\tlocal64_t rq_wait_ns;\n\tu64 last_rq_wait_ns;\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct iocg_pcpu_stat {\n\tlocal64_t abs_vusage;\n};\n\nstruct iocg_wait {\n\tstruct wait_queue_entry wait;\n\tstruct bio *bio;\n\tu64 abs_cost;\n\tbool committed;\n};\n\nstruct iocg_wake_ctx {\n\tstruct ioc_gq *iocg;\n\tu32 hw_inuse;\n\ts64 vbudget;\n};\n\nstruct snd_seq_client;\n\nstruct ioctl_handler {\n\tunsigned int cmd;\n\tint (*func)(struct snd_seq_client *, void *);\n};\n\nstruct percentile_stats {\n\tu64 total;\n\tu64 missed;\n};\n\nstruct latency_stat {\n\tunion {\n\t\tstruct percentile_stats ps;\n\t\tstruct blk_rq_stat rqs;\n\t};\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct iolatency_grp {\n\tstruct blkg_policy_data pd;\n\tstruct latency_stat *stats;\n\tstruct latency_stat cur_stat;\n\tstruct blk_iolatency *blkiolat;\n\tunsigned int max_depth;\n\tstruct rq_wait rq_wait;\n\tatomic64_t window_start;\n\tatomic_t scale_cookie;\n\tu64 min_lat_nsec;\n\tu64 cur_win_nsec;\n\tu64 lat_avg;\n\tu64 nr_samples;\n\tbool ssd;\n\tstruct child_latency_info child_lat;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tstruct bio io_bio;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n};\n\nstruct iommu_attach_handle {\n\tstruct iommu_domain *domain;\n};\n\nstruct iommu_cmd {\n\tu32 data[4];\n};\n\nstruct iommu_dev_data {\n\tstruct mutex mutex;\n\tspinlock_t dte_lock;\n\tstruct list_head list;\n\tstruct llist_node dev_data_list;\n\tstruct protection_domain *domain;\n\tstruct gcr3_tbl_info gcr3_info;\n\tstruct device *dev;\n\tu16 devid;\n\tunsigned int max_irqs;\n\tu32 max_pasids;\n\tu32 flags;\n\tint ats_qdep;\n\tu8 ats_enabled: 1;\n\tu8 pri_enabled: 1;\n\tu8 pasid_enabled: 1;\n\tu8 pri_tlp: 1;\n\tu8 ppr: 1;\n\tbool use_vapic;\n\tbool defer_attach;\n\tstruct ratelimit_state rs;\n};\n\nstruct iova_bitmap;\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_dirty_bitmap {\n\tstruct iova_bitmap *bitmap;\n\tstruct iommu_iotlb_gather *gather;\n};\n\nstruct iommu_dirty_ops {\n\tint (*set_dirty_tracking)(struct iommu_domain *, bool);\n\tint (*read_and_clear_dirty)(struct iommu_domain *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct iova {\n\tstruct rb_node node;\n\tlong unsigned int pfn_hi;\n\tlong unsigned int pfn_lo;\n};\n\nstruct iova_rcache;\n\nstruct iova_domain {\n\tspinlock_t iova_rbtree_lock;\n\tstruct rb_root rbroot;\n\tstruct rb_node *cached_node;\n\tstruct rb_node *cached32_node;\n\tlong unsigned int granule;\n\tlong unsigned int start_pfn;\n\tlong unsigned int dma_32bit_pfn;\n\tlong unsigned int max32_alloc_size;\n\tstruct iova anchor;\n\tstruct iova_rcache *rcaches;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct iommu_dma_options {\n\tenum iommu_dma_queue_type qt;\n\tsize_t fq_size;\n\tunsigned int fq_timeout;\n};\n\nstruct iova_fq;\n\nstruct iommu_dma_cookie {\n\tstruct iova_domain iovad;\n\tstruct list_head msi_page_list;\n\tunion {\n\t\tstruct iova_fq *single_fq;\n\t\tstruct iova_fq *percpu_fq;\n\t};\n\tatomic64_t fq_flush_start_cnt;\n\tatomic64_t fq_flush_finish_cnt;\n\tstruct timer_list fq_timer;\n\tatomic_t fq_timer_on;\n\tstruct iommu_domain *fq_domain;\n\tstruct iommu_dma_options options;\n};\n\nstruct iommu_dma_msi_cookie {\n\tdma_addr_t msi_iova;\n\tstruct list_head msi_page_list;\n};\n\nstruct iommu_dma_msi_page {\n\tstruct list_head list;\n\tdma_addr_t iova;\n\tphys_addr_t phys;\n};\n\nstruct iommu_domain_info {\n\tstruct intel_iommu *iommu;\n\tunsigned int refcnt;\n\tu16 did;\n};\n\nstruct iommu_user_data_array;\n\nstruct iommu_domain_ops {\n\tint (*attach_dev)(struct iommu_domain *, struct device *, struct iommu_domain *);\n\tint (*set_dev_pasid)(struct iommu_domain *, struct device *, ioasid_t, struct iommu_domain *);\n\tint (*map_pages)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct iommu_domain *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tint (*iotlb_sync_map)(struct iommu_domain *, long unsigned int, size_t);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tint (*cache_invalidate_user)(struct iommu_domain *, struct iommu_user_data_array *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tbool (*enforce_cache_coherency)(struct iommu_domain *);\n\tint (*set_pgtable_quirks)(struct iommu_domain *, long unsigned int);\n\tvoid (*free)(struct iommu_domain *);\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iommu_fault_param {\n\tstruct mutex lock;\n\trefcount_t users;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n\tstruct iopf_queue *queue;\n\tstruct list_head queue_list;\n\tstruct list_head partial;\n\tstruct list_head faults;\n};\n\nstruct iommu_fwspec {\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct xarray pasid_array;\n\tstruct mutex mutex;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *blocking_domain;\n\tstruct iommu_domain *resetting_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n\tunsigned int owner_cnt;\n\tvoid *owner;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct iommu_hw_info_vtd {\n\t__u32 flags;\n\t__u32 __reserved;\n\t__u64 cap_reg;\n\t__u64 ecap_reg;\n};\n\nstruct iommu_hwpt_vtd_s1_invalidate {\n\t__u64 addr;\n\t__u64 npages;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct iommu_pages_list {\n\tstruct list_head pages;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n\tstruct iommu_pages_list freelist;\n\tbool queued;\n};\n\nstruct iommu_mm_data {\n\tu32 pasid;\n\tstruct mm_struct *mm;\n\tstruct list_head sva_domains;\n\tstruct list_head mm_list_elm;\n};\n\nstruct iommu_user_data;\n\nstruct of_phandle_args;\n\nstruct iopf_fault;\n\nstruct iommu_page_response;\n\nstruct iommu_ops {\n\tbool (*capable)(struct device *, enum iommu_cap);\n\tvoid * (*hw_info)(struct device *, u32 *, enum iommu_hw_info_type *);\n\tstruct iommu_domain * (*domain_alloc_identity)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_paging_flags)(struct device *, u32, const struct iommu_user_data *);\n\tstruct iommu_domain * (*domain_alloc_paging)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_sva)(struct device *, struct mm_struct *);\n\tstruct iommu_domain * (*domain_alloc_nested)(struct device *, struct iommu_domain *, u32, const struct iommu_user_data *);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tint (*of_xlate)(struct device *, const struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct device *);\n\tvoid (*page_response)(struct device *, struct iopf_fault *, struct iommu_page_response *);\n\tint (*def_domain_type)(struct device *);\n\tsize_t (*get_viommu_size)(struct device *, enum iommu_viommu_type);\n\tint (*viommu_init)(struct iommufd_viommu *, struct iommu_domain *, const struct iommu_user_data *);\n\tconst struct iommu_domain_ops *default_domain_ops;\n\tstruct module *owner;\n\tstruct iommu_domain *identity_domain;\n\tstruct iommu_domain *blocked_domain;\n\tstruct iommu_domain *release_domain;\n\tstruct iommu_domain *default_domain;\n\tu8 user_pasid_table: 1;\n};\n\nstruct iommu_page_response {\n\tu32 pasid;\n\tu32 grpid;\n\tu32 code;\n};\n\nstruct iommu_pmu {\n\tstruct intel_iommu *iommu;\n\tu32 num_cntr;\n\tu32 num_eg;\n\tu32 cntr_width;\n\tu32 cntr_stride;\n\tu32 filter;\n\tvoid *base;\n\tvoid *cfg_reg;\n\tvoid *cntr_reg;\n\tvoid *overflow;\n\tu64 *evcap;\n\tu32 **cntr_evcap;\n\tstruct pmu pmu;\n\tlong unsigned int used_mask[1];\n\tstruct perf_event *event_list[64];\n\tunsigned char irq_name[16];\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n\tvoid (*free)(struct device *, struct iommu_resv_region *);\n};\n\nstruct iommu_sva {\n\tstruct iommu_attach_handle handle;\n\tstruct device *dev;\n\trefcount_t users;\n};\n\nstruct iommu_user_data {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t len;\n};\n\nstruct iommu_user_data_array {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t entry_len;\n\tu32 entry_num;\n};\n\nstruct iommufd_access;\n\nstruct iommufd_hw_queue {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_access *access;\n\tu64 base_addr;\n\tsize_t length;\n\tenum iommu_hw_queue_type type;\n\tvoid (*destroy)(struct iommufd_hw_queue *);\n};\n\nstruct iommufd_device;\n\nstruct iommufd_vdevice {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_device *idev;\n\tu64 virt_id;\n\tvoid (*destroy)(struct iommufd_vdevice *);\n};\n\nstruct iommufd_viommu_ops {\n\tvoid (*destroy)(struct iommufd_viommu *);\n\tstruct iommu_domain * (*alloc_domain_nested)(struct iommufd_viommu *, u32, const struct iommu_user_data *);\n\tint (*cache_invalidate)(struct iommufd_viommu *, struct iommu_user_data_array *);\n\tconst size_t vdevice_size;\n\tint (*vdevice_init)(struct iommufd_vdevice *);\n\tsize_t (*get_hw_queue_size)(struct iommufd_viommu *, enum iommu_hw_queue_type);\n\tint (*hw_queue_init_phys)(struct iommufd_hw_queue *, u32, phys_addr_t);\n};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct iopf_queue {\n\tstruct workqueue_struct *wq;\n\tstruct list_head devices;\n\tstruct mutex lock;\n};\n\nstruct ioprio_blkcg {\n\tstruct blkcg_policy_data cpd;\n\tenum prio_policy prio_policy;\n};\n\nstruct ioptdesc {\n\tlong unsigned int __page_flags;\n\tstruct list_head iopt_freelist_elm;\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tu8 incoherent;\n\t\tlong unsigned int __index;\n\t};\n\tvoid *_private;\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n};\n\nstruct ioremap_desc {\n\tunsigned int flags;\n};\n\nstruct iova_magazine;\n\nstruct iova_cpu_rcache {\n\tspinlock_t lock;\n\tstruct iova_magazine *loaded;\n\tstruct iova_magazine *prev;\n};\n\nstruct iova_fq_entry {\n\tlong unsigned int iova_pfn;\n\tlong unsigned int pages;\n\tstruct iommu_pages_list freelist;\n\tu64 counter;\n};\n\nstruct iova_fq {\n\tspinlock_t lock;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int mod_mask;\n\tstruct iova_fq_entry entries[0];\n};\n\nstruct iova_magazine {\n\tunion {\n\t\tlong unsigned int size;\n\t\tstruct iova_magazine *next;\n\t};\n\tlong unsigned int pfns[127];\n};\n\nstruct iova_rcache {\n\tspinlock_t lock;\n\tunsigned int depot_size;\n\tstruct iova_magazine *depot;\n\tstruct iova_cpu_rcache *cpu_rcaches;\n\tstruct iova_domain *iovad;\n\tstruct delayed_work work;\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct ip6_frag_state {\n\tu8 *prevhdr;\n\tunsigned int hlen;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\tint hroom;\n\tint troom;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ipv6hdr;\n\nstruct ip6_fraglist_iter {\n\tstruct ipv6hdr *tmp_hdr;\n\tstruct sk_buff *frag;\n\tint offset;\n\tunsigned int hlen;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct ip6_mtuinfo {\n\tstruct sockaddr_in6 ip6m_addr;\n\t__u32 ip6m_mtu;\n};\n\nstruct ip6_ra_chain {\n\tstruct ip6_ra_chain *next;\n\tstruct sock *sk;\n\tint sel;\n\tvoid (*destructor)(struct sock *);\n};\n\nstruct ip6_rt_info {\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\tu_int32_t mark;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip6_tnl {\n\tstruct ip6_tnl *next;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tstruct __ip6_tnl_parm parms;\n\tstruct flowi fl;\n\tstruct dst_cache dst_cache;\n\tstruct gro_cells gro_cells;\n\tint err_count;\n\tlong unsigned int err_time;\n\t__u32 i_seqno;\n\tatomic_t o_seqno;\n\tint hlen;\n\tint tun_hlen;\n\tint encap_hlen;\n\tstruct ip_tunnel_encap encap;\n\tint mlink;\n};\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip6addrlbl_entry {\n\tstruct in6_addr prefix;\n\tint prefixlen;\n\tint ifindex;\n\tint addrtype;\n\tu32 label;\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n};\n\nstruct ip6addrlbl_init_table {\n\tconst struct in6_addr *prefix;\n\tint prefixlen;\n\tu32 label;\n};\n\nstruct ip6fl_iter_state {\n\tstruct seq_net_private p;\n\tstruct pid_namespace *pid_ns;\n\tint bucket;\n};\n\nstruct ip6rd_flowi {\n\tstruct flowi6 fl6;\n\tstruct in6_addr gateway;\n};\n\nstruct ip6t_ip6 {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n\tstruct in6_addr smsk;\n\tstruct in6_addr dmsk;\n\tchar iniface[16];\n\tchar outiface[16];\n\tunsigned char iniface_mask[16];\n\tunsigned char outiface_mask[16];\n\t__u16 proto;\n\t__u8 tos;\n\t__u8 flags;\n\t__u8 invflags;\n};\n\nstruct xt_counters {\n\t__u64 pcnt;\n\t__u64 bcnt;\n};\n\nstruct ip6t_entry {\n\tstruct ip6t_ip6 ipv6;\n\tunsigned int nfcache;\n\t__u16 target_offset;\n\t__u16 next_offset;\n\tunsigned int comefrom;\n\tstruct xt_counters counters;\n\tunsigned char elems[0];\n};\n\nstruct ip6t_icmp {\n\t__u8 type;\n\t__u8 code[2];\n\t__u8 invflags;\n};\n\nstruct ip6t_ipv6header_info {\n\t__u8 matchflags;\n\t__u8 invflags;\n\t__u8 modeflag;\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_beet_phdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 padlen;\n\t__u8 reserved;\n};\n\nstruct ip_conntrack_stat {\n\tunsigned int found;\n\tunsigned int invalid;\n\tunsigned int insert;\n\tunsigned int insert_failed;\n\tunsigned int clash_resolve;\n\tunsigned int drop;\n\tunsigned int early_drop;\n\tunsigned int error;\n\tunsigned int expect_new;\n\tunsigned int expect_create;\n\tunsigned int expect_delete;\n\tunsigned int search_restart;\n\tunsigned int chaintoolong;\n};\n\nstruct ip_ct_sctp {\n\tenum sctp_conntrack state;\n\t__be32 vtag[2];\n\tu8 init[2];\n\tu8 last_dir;\n\tu8 flags;\n};\n\nstruct ip_ct_tcp_state {\n\tu_int32_t td_end;\n\tu_int32_t td_maxend;\n\tu_int32_t td_maxwin;\n\tu_int32_t td_maxack;\n\tu_int8_t td_scale;\n\tu_int8_t flags;\n};\n\nstruct ip_ct_tcp {\n\tstruct ip_ct_tcp_state seen[2];\n\tu_int8_t state;\n\tu_int8_t last_dir;\n\tu_int8_t retrans;\n\tu_int8_t last_index;\n\tu_int32_t last_seq;\n\tu_int32_t last_ack;\n\tu_int32_t last_end;\n\tu_int16_t last_win;\n\tu_int8_t last_wscale;\n\tu_int8_t last_flags;\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct unix_domain;\n\nstruct ip_map {\n\tstruct cache_head h;\n\tchar m_class[8];\n\tstruct in6_addr m_addr;\n\tstruct unix_domain *m_client;\n\tstruct callback_head m_rcu;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_rt_info {\n\t__be32 daddr;\n\t__be32 saddr;\n\tu_int8_t tos;\n\tu_int32_t mark;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl_entry;\n\nstruct ip_tunnel {\n\tstruct ip_tunnel *next;\n\tstruct hlist_node hash_node;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tlong unsigned int err_time;\n\tint err_count;\n\tu32 i_seqno;\n\tatomic_t o_seqno;\n\tint tun_hlen;\n\tu32 index;\n\tu8 erspan_ver;\n\tu8 dir;\n\tu16 hwid;\n\tstruct dst_cache dst_cache;\n\tstruct ip_tunnel_parm_kern parms;\n\tint mlink;\n\tint encap_hlen;\n\tint hlen;\n\tstruct ip_tunnel_encap encap;\n\tstruct ip_tunnel_prl_entry *prl;\n\tunsigned int prl_count;\n\tunsigned int ip_tnl_net_id;\n\tstruct gro_cells gro_cells;\n\t__u32 fwmark;\n\tbool collect_md;\n\tbool ignore_df;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 0;\n\tu8 options[0];\n};\n\nstruct rtnl_link_ops;\n\nstruct ip_tunnel_net {\n\tstruct net_device *fb_tunnel_dev;\n\tstruct rtnl_link_ops *rtnl_link_ops;\n\tstruct hlist_head tunnels[128];\n\tstruct ip_tunnel *collect_md_tun;\n\tint type;\n};\n\nstruct ip_tunnel_parm {\n\tchar name[16];\n\tint link;\n\t__be16 i_flags;\n\t__be16 o_flags;\n\t__be32 i_key;\n\t__be32 o_key;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl {\n\t__be32 addr;\n\t__u16 flags;\n\t__u16 __reserved;\n\t__u32 datalen;\n\t__u32 __reserved2;\n};\n\nstruct ip_tunnel_prl_entry {\n\tstruct ip_tunnel_prl_entry *next;\n\t__be32 addr;\n\tu16 flags;\n\tstruct callback_head callback_head;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned char __pad1[0];\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\t__kernel_ulong_t __unused1;\n\t__kernel_ulong_t __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tstruct rhashtable key_ht;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct ipc_security_struct {\n\tu16 sclass;\n\tu32 sid;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n};\n\nstruct ipcm6_cookie {\n\tstruct sockcm_cookie sockc;\n\t__s16 hlimit;\n\t__s16 tclass;\n\t__u16 gso_size;\n\t__s8 dontfrag;\n\tstruct ipv6_txoptions *opt;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n};\n\nstruct ipt_ip {\n\tstruct in_addr src;\n\tstruct in_addr dst;\n\tstruct in_addr smsk;\n\tstruct in_addr dmsk;\n\tchar iniface[16];\n\tchar outiface[16];\n\tunsigned char iniface_mask[16];\n\tunsigned char outiface_mask[16];\n\t__u16 proto;\n\t__u8 flags;\n\t__u8 invflags;\n};\n\nstruct ipt_entry {\n\tstruct ipt_ip ip;\n\tunsigned int nfcache;\n\t__u16 target_offset;\n\t__u16 next_offset;\n\tunsigned int comefrom;\n\tstruct xt_counters counters;\n\tunsigned char elems[0];\n};\n\nstruct ipt_icmp {\n\t__u8 type;\n\t__u8 code[2];\n\t__u8 invflags;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mreq {\n\tstruct in6_addr ipv6mr_multiaddr;\n\tint ipv6mr_ifindex;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_params {\n\t__s32 disable_ipv6;\n\t__s32 autoconf;\n};\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib6_walker w;\n\tloff_t skip;\n\tstruct fib6_table *tbl;\n\tint sernum;\n};\n\nstruct ipv6_rpl_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u32 cmpre: 4;\n\t__u32 cmpri: 4;\n\t__u32 reserved: 4;\n\t__u32 pad: 4;\n\t__u32 reserved1: 16;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_addr;\n\t\t\tstruct in6_addr addr[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\t__u8 data[0];\n\t\t};\n\t} segments;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct ipv6_saddr_dst {\n\tconst struct in6_addr *addr;\n\tint ifindex;\n\tint scope;\n\tint label;\n\tunsigned int prefs;\n};\n\nstruct ipv6_saddr_score {\n\tint rule;\n\tint addr_type;\n\tstruct inet6_ifaddr *ifa;\n\tlong unsigned int scorebits[1];\n\tint scopedist;\n\tint matchlen;\n};\n\nstruct ipv6_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u8 first_segment;\n\t__u8 flags;\n\t__u16 tag;\n\tstruct in6_addr segments[0];\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tvoid (*xfrm6_local_rxpmtu)(struct sk_buff *, u32);\n\tint (*xfrm6_udp_encap_rcv)(struct sock *, struct sk_buff *);\n\tstruct sk_buff * (*xfrm6_gro_udp_encap_rcv)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*xfrm6_rcv_encap)(struct sk_buff *, int, __be32, int);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct uv_alloc_info {\n\tint limit;\n\tint blade;\n\tlong unsigned int offset;\n\tchar *name;\n};\n\nstruct msi_desc;\n\nstruct irq_alloc_info {\n\tenum irq_alloc_type type;\n\tu32 flags;\n\tu32 devid;\n\tirq_hw_number_t hwirq;\n\tconst struct cpumask *mask;\n\tstruct msi_desc *desc;\n\tvoid *data;\n\tunion {\n\t\tstruct ioapic_alloc_info ioapic;\n\t\tstruct uv_alloc_info uv;\n\t};\n};\n\ntypedef struct irq_alloc_info msi_alloc_info_t;\n\nstruct irq_data;\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tunsigned int node;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n\tcpumask_var_t effective_affinity;\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tcpumask_var_t pending_mask;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct hlist_node resend_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct irq_desc *vector_irq_t[256];\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec;\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_info {\n\tu8 bus;\n\tu8 devfn;\n\tstruct {\n\t\tu8 link;\n\t\tu16 bitmap;\n\t} __attribute__((packed)) irq[4];\n\tu8 slot;\n\tu8 rfu;\n};\n\nstruct irq_info___2 {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\nstruct irq_matrix {\n\tunsigned int matrix_bits;\n\tunsigned int alloc_start;\n\tunsigned int alloc_end;\n\tunsigned int alloc_size;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int systembits_inalloc;\n\tunsigned int total_allocated;\n\tunsigned int online_maps;\n\tstruct cpumap *maps;\n\tlong unsigned int *system_map;\n\tlong unsigned int scratch_map[0];\n};\n\nstruct irq_override_cmp {\n\tconst struct dmi_system_id *system;\n\tunsigned char irq;\n\tunsigned char triggering;\n\tunsigned char polarity;\n\tunsigned char shareable;\n\tbool override;\n};\n\nstruct irq_pin_list {\n\tstruct list_head list;\n\tint apic;\n\tint pin;\n};\n\nstruct irq_remap_table {\n\traw_spinlock_t lock;\n\tunsigned int min_index;\n\tu32 *table;\n};\n\nstruct irq_router {\n\tchar *name;\n\tu16 vendor;\n\tu16 device;\n\tint (*get)(struct pci_dev *, struct pci_dev *, int);\n\tint (*set)(struct pci_dev *, struct pci_dev *, int, int);\n\tint (*lvl)(struct pci_dev *, struct pci_dev *, int, int);\n};\n\nstruct irq_router_handler {\n\tu16 vendor;\n\tint (*probe)(struct irq_router *, struct pci_dev *, u16);\n};\n\nstruct irq_routing_table {\n\tu32 signature;\n\tu16 version;\n\tu16 size;\n\tu8 rtr_bus;\n\tu8 rtr_devfn;\n\tu16 exclusive_irqs;\n\tu16 rtr_vendor;\n\tu16 rtr_device;\n\tu32 miniport_data;\n\tu8 rfu[11];\n\tu8 checksum;\n\tstruct irq_info slots[0];\n};\n\nstruct irq_stack {\n\tchar stack[16384];\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqentry_state {\n\tunion {\n\t\tbool exit_rcu;\n\t\tbool lockdep;\n\t};\n};\n\ntypedef struct irqentry_state irqentry_state_t;\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct irt_routing_table {\n\tu32 signature;\n\tu8 size;\n\tu8 used;\n\tu16 exclusive_irqs;\n\tstruct irq_info slots[0];\n};\n\nstruct iso_directory_record {\n\t__u8 length[1];\n\t__u8 ext_attr_length[1];\n\t__u8 extent[8];\n\t__u8 size[8];\n\t__u8 date[7];\n\t__u8 flags[1];\n\t__u8 file_unit_size[1];\n\t__u8 interleave[1];\n\t__u8 volume_sequence_number[4];\n\t__u8 name_len[1];\n\tchar name[0];\n};\n\nstruct iso_inode_info {\n\tlong unsigned int i_iget5_block;\n\tlong unsigned int i_iget5_offset;\n\tunsigned int i_first_extent;\n\tunsigned char i_file_format;\n\tunsigned char i_format_parm[3];\n\tlong unsigned int i_next_section_block;\n\tlong unsigned int i_next_section_offset;\n\toff_t i_section_size;\n\tstruct inode vfs_inode;\n};\n\nstruct iso_primary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_rec {\n\tint error_count;\n\tint numdesc;\n};\n\nstruct iso_supplementary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 flags[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 escape[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_volume_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2041];\n};\n\nstruct isoch_data {\n\tu32 maxbw;\n\tu32 n;\n\tu32 y;\n\tu32 l;\n\tu32 rq;\n\tstruct agp_3_5_dev *dev;\n};\n\nstruct isofs_fid {\n\tu32 block;\n\tu16 offset;\n\tu16 parent_offset;\n\tu32 generation;\n\tu32 parent_block;\n\tu32 parent_generation;\n};\n\nstruct isofs_iget5_callback_data {\n\tlong unsigned int block;\n\tlong unsigned int offset;\n};\n\nstruct isofs_options {\n\tunsigned int rock: 1;\n\tunsigned int joliet: 1;\n\tunsigned int cruft: 1;\n\tunsigned int hide: 1;\n\tunsigned int showassoc: 1;\n\tunsigned int nocompress: 1;\n\tunsigned int overriderockperm: 1;\n\tunsigned int uid_set: 1;\n\tunsigned int gid_set: 1;\n\tunsigned char map;\n\tunsigned char check;\n\tunsigned int blocksize;\n\tumode_t fmode;\n\tumode_t dmode;\n\tkgid_t gid;\n\tkuid_t uid;\n\tchar *iocharset;\n\ts32 session;\n\ts32 sbsector;\n};\n\nstruct nls_table;\n\nstruct isofs_sb_info {\n\tlong unsigned int s_ninodes;\n\tlong unsigned int s_nzones;\n\tlong unsigned int s_firstdatazone;\n\tlong unsigned int s_log_zone_size;\n\tlong unsigned int s_max_size;\n\tint s_rock_offset;\n\ts32 s_sbsector;\n\tunsigned char s_joliet_level;\n\tunsigned char s_mapping;\n\tunsigned char s_check;\n\tunsigned char s_session;\n\tunsigned int s_high_sierra: 1;\n\tunsigned int s_rock: 2;\n\tunsigned int s_cruft: 1;\n\tunsigned int s_nocompress: 1;\n\tunsigned int s_hide: 1;\n\tunsigned int s_showassoc: 1;\n\tunsigned int s_overriderockperm: 1;\n\tunsigned int s_uid_set: 1;\n\tunsigned int s_gid_set: 1;\n\tumode_t s_fmode;\n\tumode_t s_dmode;\n\tkgid_t s_gid;\n\tkuid_t s_uid;\n\tstruct nls_table *s_nls_iocharset;\n};\n\nstruct itco_wdt_platform_data {\n\tchar name[32];\n\tunsigned int version;\n\tbool no_reboot_use_pmc;\n};\n\nstruct iter_state {\n\tstruct seq_net_private p;\n\tunsigned int bucket;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct its_array {\n\tvoid **pages;\n\tint num;\n};\n\nstruct ivch_priv {\n\tbool quiet;\n\tu16 width;\n\tu16 height;\n\tu16 reg_backup[24];\n};\n\nstruct ivhd_dte_flags {\n\tstruct list_head list;\n\tu16 segid;\n\tu16 devid_first;\n\tu16 devid_last;\n\tlong: 64;\n\tstruct dev_table_entry dte;\n};\n\nstruct ivhd_entry {\n\tu8 type;\n\tu16 devid;\n\tu8 flags;\n\tunion {\n\t\tstruct {\n\t\t\tu32 ext;\n\t\t\tu32 hidh;\n\t\t};\n\t\tstruct {\n\t\t\tu32 ext;\n\t\t\tu32 hidh;\n\t\t} ext_hid;\n\t};\n\tu64 cid;\n\tu8 uidf;\n\tu8 uidl;\n\tu8 uid;\n} __attribute__((packed));\n\nstruct ivhd_header {\n\tu8 type;\n\tu8 flags;\n\tu16 length;\n\tu16 devid;\n\tu16 cap_ptr;\n\tu64 mmio_phys;\n\tu16 pci_seg;\n\tu16 info;\n\tu32 efr_attr;\n\tu64 efr_reg;\n\tu64 efr_reg2;\n};\n\nstruct ivmd_header {\n\tu8 type;\n\tu8 flags;\n\tu16 length;\n\tu16 devid;\n\tu16 aux;\n\tu16 pci_seg;\n\tu8 resv[6];\n\tu64 range_start;\n\tu64 range_length;\n};\n\nstruct ivrs_quirk_entry {\n\tu8 id;\n\tu32 devid;\n};\n\nstruct iw_node_attr {\n\tstruct kobj_attribute kobj_attr;\n\tint nid;\n};\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_s journal_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong long unsigned int blocknr;\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct transaction_stats_s;\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct jit_context {\n\tint cleanup_addr;\n\tint tail_call_direct_label;\n\tint tail_call_indirect_label;\n};\n\nstruct rand_data;\n\nstruct shash_desc;\n\nstruct jitterentropy {\n\tspinlock_t jent_lock;\n\tstruct rand_data *entropy_collector;\n\tstruct crypto_shash *tfm;\n\tstruct shash_desc *sdesc;\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\twait_queue_head_t j_fc_wait;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tstruct shrinker *j_shrinker;\n\tstruct percpu_counter j_checkpoint_jh_count;\n\ttransaction_t *j_shrink_transaction;\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tlong unsigned int j_fc_first;\n\tlong unsigned int j_fc_off;\n\tlong unsigned int j_fc_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\terrseq_t j_fs_dev_wb_err;\n\tunsigned int j_total_len;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tint j_transaction_overhead_buffers;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tstruct buffer_head **j_fc_wbuf;\n\tint j_wbufsize;\n\tint j_fc_wbufsize;\n\tpid_t j_last_sync_writer;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tint (*j_submit_inode_data_buffers)(struct jbd2_inode *);\n\tint (*j_finish_inode_data_buffers)(struct jbd2_inode *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\t__u32 j_csum_seed;\n\tstruct lock_class_key jbd2_trans_commit_key;\n\tvoid (*j_fc_cleanup_callback)(struct journal_s *, int, tid_t);\n\tint (*j_fc_replay_callback)(struct journal_s *, struct buffer_head *, enum passtype, int, tid_t);\n\tint (*j_bmap)(struct journal_s *, sector_t *);\n};\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__be32 s_num_fc_blks;\n\t__be32 s_head;\n\t__u32 s_padding[40];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nstruct jump_entry {\n\ts32 code;\n\ts32 target;\n\tlong int key;\n};\n\nstruct jump_label_patch {\n\tconst void *code;\n\tint size;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\ntypedef void __restorefn_t(void);\n\ntypedef __restorefn_t *__sigrestore_t;\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[56];\n\tint exported;\n\tint show_value;\n};\n\nstruct karatsuba_ctx {\n\tstruct karatsuba_ctx *next;\n\tmpi_ptr_t tspace;\n\tmpi_size_t tspace_size;\n\tmpi_ptr_t tp;\n\tmpi_size_t tp_size;\n};\n\nstruct kaslr_memory_region {\n\tlong unsigned int *base;\n\tlong unsigned int *end;\n\tlong unsigned int size_tb;\n};\n\nstruct kbd_led_trigger {\n\tstruct led_trigger trigger;\n\tunsigned int mask;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tint: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcmp_epoll_slot {\n\t__u32 efd;\n\t__u32 tfd;\n\t__u32 toff;\n};\n\ntypedef void (*dm_kcopyd_notify_fn)(int, long unsigned int, void *);\n\nstruct kcopyd_job {\n\tstruct dm_kcopyd_client *kc;\n\tstruct list_head list;\n\tunsigned int flags;\n\tint read_err;\n\tlong unsigned int write_err;\n\tenum req_op op;\n\tstruct dm_io_region source;\n\tunsigned int num_dests;\n\tstruct dm_io_region dests[8];\n\tstruct page_list *pages;\n\tdm_kcopyd_notify_fn fn;\n\tvoid *context;\n\tstruct mutex lock;\n\tatomic_t sub_jobs;\n\tsector_t progress;\n\tsector_t write_offset;\n\tstruct kcopyd_job *master_job;\n};\n\nstruct kcore_list {\n\tstruct list_head list;\n\tlong unsigned int addr;\n\tsize_t size;\n\tint type;\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[10];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tint value_offset;\n\tint name_offset;\n\tint namespace_offset;\n};\n\nstruct kernel_vm86_regs {\n\tstruct pt_regs pt;\n\tshort unsigned int es;\n\tshort unsigned int __esh;\n\tshort unsigned int ds;\n\tshort unsigned int __dsh;\n\tshort unsigned int fs;\n\tshort unsigned int __fsh;\n\tshort unsigned int gs;\n\tshort unsigned int __gsh;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[1024];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct kexec_link_entry {\n\tconst char *target;\n\tconst char *name;\n};\n\nstruct kexec_load_limit {\n\tstruct mutex mutex;\n\tint limit;\n};\n\nstruct kexec_segment {\n\tunion {\n\t\tvoid *buf;\n\t\tvoid *kbuf;\n\t};\n\tsize_t bufsz;\n\tlong unsigned int mem;\n\tsize_t memsz;\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[6];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_entry {\n\tint type;\n\tu32 code;\n\tunion {\n\t\tu16 keycode;\n\t\tstruct {\n\t\t\tu8 code;\n\t\t\tu8 value;\n\t\t} sw;\n\t};\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct key_parse {\n\tstruct key_params p;\n\tint idx;\n\tint type;\n\tbool def;\n\tbool defmgmt;\n\tbool defbeacon;\n\tbool def_uni;\n\tbool def_multi;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_security_struct {\n\tu32 sid;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\ttime64_t now;\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct kho_data {\n\t__u64 fdt_addr;\n\t__u64 fdt_size;\n\t__u64 scratch_addr;\n\t__u64 scratch_size;\n};\n\nstruct kimage_arch {\n\tpgd_t *pgd;\n\tp4d_t *p4d;\n\tpud_t *pud;\n\tpmd_t *pmd;\n\tpte_t *pte;\n};\n\nstruct kimage {\n\tkimage_entry_t head;\n\tkimage_entry_t *entry;\n\tkimage_entry_t *last_entry;\n\tlong unsigned int start;\n\tstruct page *control_code_page;\n\tstruct page *swap_page;\n\tvoid *vmcoreinfo_data_copy;\n\tlong unsigned int nr_segments;\n\tstruct kexec_segment segment[16];\n\tstruct page *segment_cma[16];\n\tstruct list_head control_pages;\n\tstruct list_head dest_pages;\n\tstruct list_head unusable_pages;\n\tlong unsigned int control_page;\n\tunsigned int type: 1;\n\tunsigned int preserve_context: 1;\n\tunsigned int file_mode: 1;\n\tunsigned int hotplug_support: 1;\n\tunsigned int no_cma: 1;\n\tstruct kimage_arch arch;\n\tint hp_action;\n\tint elfcorehdr_index;\n\tbool elfcorehdr_updated;\n\tstruct {\n\t\tstruct kexec_segment *scratch;\n\t\tphys_addr_t fdt;\n\t} kho;\n\tvoid *elf_headers;\n\tlong unsigned int elf_headers_sz;\n\tlong unsigned int elf_load_addr;\n\tlong unsigned int dm_crypt_keys_addr;\n\tlong unsigned int dm_crypt_keys_sz;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct km_event {\n\tunion {\n\t\tu32 hard;\n\t\tu32 proto;\n\t\tu32 byid;\n\t\tu32 aevent;\n\t\tu32 type;\n\t} data;\n\tu32 seq;\n\tu32 portid;\n\tu32 event;\n\tstruct net *net;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[3];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {};\n\ntypedef struct kmem_cache *kmem_buckets[14];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tunsigned int remote_node_defrag_ratio;\n\tstruct kmem_cache_node *node[64];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct kobj_engine {\n\tstruct kobject base;\n\tstruct intel_engine_cs *engine;\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kpp_request;\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tstruct crypto_alg base;\n};\n\nstruct kpp_instance {\n\tvoid (*free)(struct kpp_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[48];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct kpp_alg alg;\n\t};\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct kprobe_blacklist_entry {\n\tstruct list_head list;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n};\n\nstruct prev_kprobe {\n\tstruct kprobe *kp;\n\tlong unsigned int status;\n\tlong unsigned int old_flags;\n\tlong unsigned int saved_flags;\n};\n\nstruct kprobe_ctlblk {\n\tlong unsigned int kprobe_status;\n\tlong unsigned int kprobe_old_flags;\n\tlong unsigned int kprobe_saved_flags;\n\tstruct prev_kprobe prev_kprobe;\n};\n\nstruct kprobe_insn_cache {\n\tstruct mutex mutex;\n\tvoid * (*alloc)(void);\n\tvoid (*free)(void *);\n\tconst char *sym;\n\tstruct list_head pages;\n\tsize_t insn_size;\n\tint nr_garbage;\n};\n\nstruct kprobe_insn_page {\n\tstruct list_head list;\n\tkprobe_opcode_t *insns;\n\tstruct kprobe_insn_cache *cache;\n\tint nused;\n\tint ngarbage;\n\tchar slot_used[0];\n};\n\nstruct kprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n};\n\nstruct krb5_ctx {\n\tint initiate;\n\tu32 enctype;\n\tu32 flags;\n\tconst struct gss_krb5_enctype *gk5e;\n\tstruct crypto_sync_skcipher *enc;\n\tstruct crypto_sync_skcipher *seq;\n\tstruct crypto_sync_skcipher *acceptor_enc;\n\tstruct crypto_sync_skcipher *initiator_enc;\n\tstruct crypto_sync_skcipher *acceptor_enc_aux;\n\tstruct crypto_sync_skcipher *initiator_enc_aux;\n\tstruct crypto_ahash *acceptor_sign;\n\tstruct crypto_ahash *initiator_sign;\n\tstruct crypto_ahash *initiator_integ;\n\tstruct crypto_ahash *acceptor_integ;\n\tu8 Ksess[32];\n\tu8 cksum[32];\n\tatomic_t seq_send;\n\tatomic64_t seq_send64;\n\ttime64_t endtime;\n\tstruct xdr_netobj mech_used;\n};\n\nstruct kretprobe_instance;\n\ntypedef int (*kretprobe_handler_t)(struct kretprobe_instance *, struct pt_regs *);\n\nstruct rethook;\n\nstruct kretprobe {\n\tstruct kprobe kp;\n\tkretprobe_handler_t handler;\n\tkretprobe_handler_t entry_handler;\n\tint maxactive;\n\tint nmissed;\n\tsize_t data_size;\n\tstruct rethook *rh;\n};\n\nstruct kretprobe_blackpoint {\n\tconst char *name;\n\tvoid *addr;\n};\n\nstruct rethook_node {\n\tstruct callback_head rcu;\n\tstruct llist_node llist;\n\tstruct rethook *rethook;\n\tlong unsigned int ret_addr;\n\tlong unsigned int frame;\n};\n\nstruct kretprobe_instance {\n\tstruct rethook_node node;\n\tchar data[0];\n};\n\nstruct kretprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int func;\n\tlong unsigned int ret_ip;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kvm_memslots {\n\tu64 generation;\n\tatomic_long_t last_used_slot;\n\tstruct rb_root_cached hva_tree;\n\tstruct rb_root gfn_tree;\n\tstruct hlist_head id_hash[128];\n\tint node_idx;\n};\n\nstruct kvm_vm_stat_generic {\n\tu64 remote_tlb_flush;\n\tu64 remote_tlb_flush_requests;\n};\n\nstruct kvm_vm_stat {\n\tstruct kvm_vm_stat_generic generic;\n\tu64 mmu_shadow_zapped;\n\tu64 mmu_pte_write;\n\tu64 mmu_pde_zapped;\n\tu64 mmu_flooded;\n\tu64 mmu_recycled;\n\tu64 mmu_cache_miss;\n\tu64 mmu_unsync;\n\tunion {\n\t\tstruct {\n\t\t\tatomic64_t pages_4k;\n\t\t\tatomic64_t pages_2m;\n\t\t\tatomic64_t pages_1g;\n\t\t};\n\t\tatomic64_t pages[3];\n\t};\n\tu64 nx_lpage_splits;\n\tu64 max_mmu_page_hash_collisions;\n\tu64 max_mmu_rmap_size;\n};\n\nstruct kvm_possible_nx_huge_pages {\n\tstruct list_head pages;\n\tu64 nr_pages;\n};\n\nstruct vhost_task;\n\nstruct once {\n\tatomic_t state;\n\tstruct mutex lock;\n};\n\nstruct kvm_mmu_memory_cache {\n\tgfp_t gfp_zero;\n\tgfp_t gfp_custom;\n\tu64 init_value;\n\tstruct kmem_cache *kmem_cache;\n\tint capacity;\n\tint nobjs;\n\tvoid **objects;\n};\n\nstruct kvm_apic_map;\n\nstruct kvm_x86_msr_filter;\n\nstruct kvm_x86_pmu_event_filter;\n\nstruct kvm_arch {\n\tlong unsigned int n_used_mmu_pages;\n\tlong unsigned int n_requested_mmu_pages;\n\tlong unsigned int n_max_mmu_pages;\n\tunsigned int indirect_shadow_pages;\n\tu8 mmu_valid_gen;\n\tu8 vm_type;\n\tbool has_private_mem;\n\tbool has_protected_state;\n\tbool has_protected_eoi;\n\tbool pre_fault_allowed;\n\tstruct hlist_head *mmu_page_hash;\n\tstruct list_head active_mmu_pages;\n\tstruct kvm_possible_nx_huge_pages possible_nx_huge_pages[2];\n\tspinlock_t mmu_unsync_pages_lock;\n\tu64 shadow_mmio_value;\n\tatomic_t noncoherent_dma_count;\n\tlong unsigned int nr_possible_bypass_irqs;\n\tatomic_t vapics_in_nmi_mode;\n\tstruct mutex apic_map_lock;\n\tstruct kvm_apic_map *apic_map;\n\tatomic_t apic_map_dirty;\n\tbool apic_access_memslot_enabled;\n\tbool apic_access_memslot_inhibited;\n\tstruct rw_semaphore apicv_update_lock;\n\tlong unsigned int apicv_inhibit_reasons;\n\tgpa_t wall_clock;\n\tu64 disabled_exits;\n\ts64 kvmclock_offset;\n\traw_spinlock_t tsc_write_lock;\n\tu64 last_tsc_nsec;\n\tu64 last_tsc_write;\n\tu32 last_tsc_khz;\n\tu64 last_tsc_offset;\n\tu64 cur_tsc_nsec;\n\tu64 cur_tsc_write;\n\tu64 cur_tsc_offset;\n\tu64 cur_tsc_generation;\n\tint nr_vcpus_matched_tsc;\n\tu32 default_tsc_khz;\n\tbool user_set_tsc;\n\tu64 apic_bus_cycle_ns;\n\tseqcount_raw_spinlock_t pvclock_sc;\n\tbool use_master_clock;\n\tu64 master_kernel_ns;\n\tu64 master_cycle_now;\n\tbool backwards_tsc_observed;\n\tbool boot_vcpu_runs_old_kvmclock;\n\tu32 bsp_vcpu_id;\n\tu64 disabled_quirks;\n\tenum kvm_irqchip_mode irqchip_mode;\n\tu8 nr_reserved_ioapic_pins;\n\tbool disabled_lapic_found;\n\tbool x2apic_format;\n\tbool x2apic_broadcast_quirk_disabled;\n\tenum kvm_suppress_eoi_broadcast_mode suppress_eoi_broadcast_mode;\n\tbool has_mapped_host_mmio;\n\tbool guest_can_read_msr_platform_info;\n\tbool exception_payload_enabled;\n\tbool triple_fault_event;\n\tbool bus_lock_detection_enabled;\n\tbool enable_pmu;\n\tbool created_mediated_pmu;\n\tu32 notify_window;\n\tu32 notify_vmexit_flags;\n\tbool exit_on_emulation_error;\n\tu32 user_space_msr_mask;\n\tstruct kvm_x86_msr_filter *msr_filter;\n\tu32 hypercall_exit_enabled;\n\tbool sgx_provisioning_allowed;\n\tstruct kvm_x86_pmu_event_filter *pmu_event_filter;\n\tstruct vhost_task *nx_huge_page_recovery_thread;\n\tu64 nx_huge_page_last;\n\tstruct once nx_once;\n\tstruct list_head tdp_mmu_roots;\n\tspinlock_t tdp_mmu_pages_lock;\n\tbool shadow_root_allocated;\n\tu32 max_vcpu_ids;\n\tbool disable_nx_huge_pages;\n\tstruct kvm_mmu_memory_cache split_shadow_page_cache;\n\tstruct kvm_mmu_memory_cache split_page_header_cache;\n\tstruct kvm_mmu_memory_cache split_desc_cache;\n\tgfn_t gfn_direct_bits;\n\tint cpu_dirty_log_size;\n};\n\nstruct kvm_io_bus;\n\nstruct kvm_stat_data;\n\nstruct kvm {\n\trwlock_t mmu_lock;\n\tstruct mutex slots_lock;\n\tstruct mutex slots_arch_lock;\n\tstruct mm_struct *mm;\n\tlong unsigned int nr_memslot_pages;\n\tstruct kvm_memslots __memslots[2];\n\tstruct kvm_memslots *memslots[1];\n\tstruct xarray vcpu_array;\n\tatomic_t nr_memslots_dirty_logging;\n\tspinlock_t mn_invalidate_lock;\n\tlong unsigned int mn_active_invalidate_count;\n\tstruct rcuwait mn_memslots_update_rcuwait;\n\tspinlock_t gpc_lock;\n\tstruct list_head gpc_list;\n\tatomic_t online_vcpus;\n\tint max_vcpus;\n\tint created_vcpus;\n\tint last_boosted_vcpu;\n\tstruct list_head vm_list;\n\tstruct mutex lock;\n\tstruct kvm_io_bus *buses[5];\n\tstruct list_head ioeventfds;\n\tstruct kvm_vm_stat stat;\n\tstruct kvm_arch arch;\n\trefcount_t users_count;\n\tstruct mutex irq_lock;\n\tstruct mmu_notifier mmu_notifier;\n\tlong unsigned int mmu_invalidate_seq;\n\tlong int mmu_invalidate_in_progress;\n\tgfn_t mmu_invalidate_range_start;\n\tgfn_t mmu_invalidate_range_end;\n\tstruct list_head devices;\n\tu64 manual_dirty_log_protect;\n\tstruct dentry *debugfs_dentry;\n\tstruct kvm_stat_data **debugfs_stat_data;\n\tstruct srcu_struct srcu;\n\tstruct srcu_struct irq_srcu;\n\tpid_t userspace_pid;\n\tbool override_halt_poll_ns;\n\tunsigned int max_halt_poll_ns;\n\tu32 dirty_ring_size;\n\tbool dirty_ring_with_bitmap;\n\tbool vm_bugged;\n\tbool vm_dead;\n\tchar stats_id[48];\n};\n\nstruct kvm_lapic;\n\nstruct kvm_apic_map {\n\tstruct callback_head rcu;\n\tenum kvm_apic_logical_mode logical_mode;\n\tu32 max_apic_id;\n\tunion {\n\t\tstruct kvm_lapic *xapic_flat_map[8];\n\t\tstruct kvm_lapic *xapic_cluster_map[64];\n\t};\n\tstruct kvm_lapic *phys_map[0];\n};\n\nstruct kvm_rmap_head;\n\nstruct kvm_lpage_info;\n\nstruct kvm_arch_memory_slot {\n\tstruct kvm_rmap_head *rmap[3];\n\tstruct kvm_lpage_info *lpage_info[2];\n\tshort unsigned int *gfn_write_track;\n};\n\nstruct kvm_clock_pairing {\n\t__s64 sec;\n\t__s64 nsec;\n\t__u64 tsc;\n\t__u32 flags;\n\t__u32 pad[9];\n};\n\nunion kvm_mmu_page_role {\n\tu32 word;\n\tstruct {\n\t\tunsigned int level: 4;\n\t\tunsigned int has_4_byte_gpte: 1;\n\t\tunsigned int quadrant: 2;\n\t\tunsigned int direct: 1;\n\t\tunsigned int access: 3;\n\t\tunsigned int invalid: 1;\n\t\tunsigned int efer_nx: 1;\n\t\tunsigned int cr0_wp: 1;\n\t\tunsigned int smep_andnot_wp: 1;\n\t\tunsigned int smap_andnot_wp: 1;\n\t\tunsigned int ad_disabled: 1;\n\t\tunsigned int guest_mode: 1;\n\t\tunsigned int passthrough: 1;\n\t\tunsigned int is_mirror: 1;\n\t\tchar: 4;\n\t\tunsigned int smm: 8;\n\t};\n};\n\nunion kvm_mmu_extended_role {\n\tu32 word;\n\tstruct {\n\t\tunsigned int valid: 1;\n\t\tunsigned int execonly: 1;\n\t\tunsigned int cr4_pse: 1;\n\t\tunsigned int cr4_pke: 1;\n\t\tunsigned int cr4_smap: 1;\n\t\tunsigned int cr4_smep: 1;\n\t\tunsigned int cr4_la57: 1;\n\t\tunsigned int efer_lma: 1;\n\t};\n};\n\nunion kvm_cpu_role {\n\tu64 as_u64;\n\tstruct {\n\t\tunion kvm_mmu_page_role base;\n\t\tunion kvm_mmu_extended_role ext;\n\t};\n};\n\nstruct kvm_cpuid_entry2 {\n\t__u32 function;\n\t__u32 index;\n\t__u32 flags;\n\t__u32 eax;\n\t__u32 ebx;\n\t__u32 ecx;\n\t__u32 edx;\n\t__u32 padding[3];\n};\n\nstruct kvm_debug_exit_arch {\n\t__u32 exception;\n\t__u32 pad;\n\t__u64 pc;\n\t__u64 dr6;\n\t__u64 dr7;\n};\n\nstruct kvm_dirty_gfn {\n\t__u32 flags;\n\t__u32 slot;\n\t__u64 offset;\n};\n\nstruct kvm_dirty_ring {\n\tu32 dirty_index;\n\tu32 reset_index;\n\tu32 size;\n\tu32 soft_limit;\n\tstruct kvm_dirty_gfn *dirty_gfns;\n\tint index;\n};\n\nstruct kvm_dtable {\n\t__u64 base;\n\t__u16 limit;\n\t__u16 padding[3];\n};\n\nstruct kvm_enc_region {\n\t__u64 addr;\n\t__u64 size;\n};\n\nstruct kvm_exit_snp_req_certs {\n\t__u64 gpa;\n\t__u64 npages;\n\t__u64 ret;\n};\n\nstruct kvm_hyperv_exit {\n\t__u32 type;\n\t__u32 pad1;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 evt_page;\n\t\t\t__u64 msg_page;\n\t\t} synic;\n\t\tstruct {\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[2];\n\t\t} hcall;\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 status;\n\t\t\t__u64 send_page;\n\t\t\t__u64 recv_page;\n\t\t\t__u64 pending_page;\n\t\t} syndbg;\n\t} u;\n};\n\nstruct kvm_io_device;\n\nstruct kvm_io_range {\n\tgpa_t addr;\n\tint len;\n\tstruct kvm_io_device *dev;\n};\n\nstruct kvm_io_bus {\n\tint dev_count;\n\tint ioeventfd_count;\n\tstruct callback_head rcu;\n\tstruct kvm_io_range range[0];\n};\n\nstruct kvm_lpage_info {\n\tint disallow_lpage;\n};\n\nstruct kvm_memory_slot {\n\tstruct hlist_node id_node[2];\n\tstruct interval_tree_node hva_node[2];\n\tstruct rb_node gfn_node[2];\n\tgfn_t base_gfn;\n\tlong unsigned int npages;\n\tlong unsigned int *dirty_bitmap;\n\tstruct kvm_arch_memory_slot arch;\n\tlong unsigned int userspace_addr;\n\tu32 flags;\n\tshort int id;\n\tu16 as_id;\n};\n\nstruct kvm_mmio_fragment {\n\tgpa_t gpa;\n\tvoid *data;\n\tunsigned int len;\n};\n\nstruct kvm_page_fault;\n\nstruct x86_exception;\n\nstruct kvm_mmu_page;\n\nstruct kvm_mmu_root_info {\n\tgpa_t pgd;\n\thpa_t hpa;\n};\n\nstruct rsvd_bits_validate {\n\tu64 rsvd_bits_mask[10];\n\tu64 bad_mt_xwr;\n};\n\nstruct kvm_vcpu;\n\nstruct kvm_mmu {\n\tlong unsigned int (*get_guest_pgd)(struct kvm_vcpu *);\n\tu64 (*get_pdptr)(struct kvm_vcpu *, int);\n\tint (*page_fault)(struct kvm_vcpu *, struct kvm_page_fault *);\n\tvoid (*inject_page_fault)(struct kvm_vcpu *, struct x86_exception *);\n\tgpa_t (*gva_to_gpa)(struct kvm_vcpu *, struct kvm_mmu *, gpa_t, u64, struct x86_exception *);\n\tint (*sync_spte)(struct kvm_vcpu *, struct kvm_mmu_page *, int);\n\tstruct kvm_mmu_root_info root;\n\thpa_t mirror_root_hpa;\n\tunion kvm_cpu_role cpu_role;\n\tunion kvm_mmu_page_role root_role;\n\tu32 pkru_mask;\n\tstruct kvm_mmu_root_info prev_roots[3];\n\tu8 permissions[16];\n\tu64 *pae_root;\n\tu64 *pml4_root;\n\tu64 *pml5_root;\n\tstruct rsvd_bits_validate shadow_zero_check;\n\tstruct rsvd_bits_validate guest_rsvd_check;\n\tu64 pdptrs[4];\n};\n\nstruct kvm_mtrr {\n\tu64 var[16];\n\tu64 fixed_64k;\n\tu64 fixed_16k[2];\n\tu64 fixed_4k[8];\n\tu64 deftype;\n};\n\nstruct kvm_vmx_nested_state_hdr {\n\t__u64 vmxon_pa;\n\t__u64 vmcs12_pa;\n\tstruct {\n\t\t__u16 flags;\n\t} smm;\n\t__u16 pad;\n\t__u32 flags;\n\t__u64 preemption_timer_deadline;\n};\n\nstruct kvm_svm_nested_state_hdr {\n\t__u64 vmcb_pa;\n};\n\nstruct kvm_vmx_nested_state_data {\n\t__u8 vmcs12[4096];\n\t__u8 shadow_vmcs12[4096];\n};\n\nstruct kvm_svm_nested_state_data {\n\t__u8 vmcb12[4096];\n};\n\nstruct kvm_nested_state {\n\t__u16 flags;\n\t__u16 format;\n\t__u32 size;\n\tunion {\n\t\tstruct kvm_vmx_nested_state_hdr vmx;\n\t\tstruct kvm_svm_nested_state_hdr svm;\n\t\t__u8 pad[120];\n\t} hdr;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_vmx;\n\t\t\tstruct kvm_vmx_nested_state_data vmx[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_svm;\n\t\t\tstruct kvm_svm_nested_state_data svm[0];\n\t\t};\n\t} data;\n};\n\nstruct kvm_pio_request {\n\tlong unsigned int count;\n\tint in;\n\tint port;\n\tint size;\n};\n\nstruct kvm_pmc {\n\tenum pmc_type type;\n\tu8 idx;\n\tbool is_paused;\n\tbool intr;\n\tu64 counter;\n\tu64 emulated_counter;\n\tu64 eventsel;\n\tu64 eventsel_hw;\n\tstruct perf_event *perf_event;\n\tstruct kvm_vcpu *vcpu;\n\tu64 current_config;\n};\n\nstruct kvm_pmu {\n\tu8 version;\n\tunsigned int nr_arch_gp_counters;\n\tunsigned int nr_arch_fixed_counters;\n\tunsigned int available_event_types;\n\tu64 fixed_ctr_ctrl;\n\tu64 fixed_ctr_ctrl_hw;\n\tu64 fixed_ctr_ctrl_rsvd;\n\tu64 global_ctrl;\n\tu64 global_status;\n\tu64 counter_bitmask[2];\n\tu64 global_ctrl_rsvd;\n\tu64 global_status_rsvd;\n\tu64 reserved_bits;\n\tu64 raw_event_mask;\n\tstruct kvm_pmc gp_counters[8];\n\tstruct kvm_pmc fixed_counters[3];\n\tunion {\n\t\tlong unsigned int reprogram_pmi[1];\n\t\tatomic64_t __reprogram_pmi;\n\t};\n\tlong unsigned int all_valid_pmc_idx[1];\n\tlong unsigned int pmc_in_use[1];\n\tlong unsigned int pmc_counting_instructions[1];\n\tlong unsigned int pmc_counting_branches[1];\n\tu64 ds_area;\n\tu64 pebs_enable;\n\tu64 pebs_enable_rsvd;\n\tu64 pebs_data_cfg;\n\tu64 pebs_data_cfg_rsvd;\n\tu64 host_cross_mapped_mask;\n\tbool need_cleanup;\n\tu8 event_count;\n};\n\nstruct kvm_ptp_clock {\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info caps;\n};\n\nstruct kvm_queued_exception {\n\tbool pending;\n\tbool injected;\n\tbool has_error_code;\n\tu8 vector;\n\tu32 error_code;\n\tlong unsigned int payload;\n\tbool has_payload;\n};\n\nstruct kvm_queued_interrupt {\n\tbool injected;\n\tbool soft;\n\tu8 nr;\n};\n\nstruct kvm_regs {\n\t__u64 rax;\n\t__u64 rbx;\n\t__u64 rcx;\n\t__u64 rdx;\n\t__u64 rsi;\n\t__u64 rdi;\n\t__u64 rsp;\n\t__u64 rbp;\n\t__u64 r8;\n\t__u64 r9;\n\t__u64 r10;\n\t__u64 r11;\n\t__u64 r12;\n\t__u64 r13;\n\t__u64 r14;\n\t__u64 r15;\n\t__u64 rip;\n\t__u64 rflags;\n};\n\nstruct kvm_rmap_head {\n\tatomic_long_t val;\n};\n\nstruct kvm_xen_exit {\n\t__u32 type;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 longmode;\n\t\t\t__u32 cpl;\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[6];\n\t\t} hcall;\n\t} u;\n};\n\nstruct kvm_segment {\n\t__u64 base;\n\t__u32 limit;\n\t__u16 selector;\n\t__u8 type;\n\t__u8 present;\n\t__u8 dpl;\n\t__u8 db;\n\t__u8 s;\n\t__u8 l;\n\t__u8 g;\n\t__u8 avl;\n\t__u8 unusable;\n\t__u8 padding;\n};\n\nstruct kvm_sregs {\n\tstruct kvm_segment cs;\n\tstruct kvm_segment ds;\n\tstruct kvm_segment es;\n\tstruct kvm_segment fs;\n\tstruct kvm_segment gs;\n\tstruct kvm_segment ss;\n\tstruct kvm_segment tr;\n\tstruct kvm_segment ldt;\n\tstruct kvm_dtable gdt;\n\tstruct kvm_dtable idt;\n\t__u64 cr0;\n\t__u64 cr2;\n\t__u64 cr3;\n\t__u64 cr4;\n\t__u64 cr8;\n\t__u64 efer;\n\t__u64 apic_base;\n\t__u64 interrupt_bitmap[4];\n};\n\nstruct kvm_vcpu_events {\n\tstruct {\n\t\t__u8 injected;\n\t\t__u8 nr;\n\t\t__u8 has_error_code;\n\t\t__u8 pending;\n\t\t__u32 error_code;\n\t} exception;\n\tstruct {\n\t\t__u8 injected;\n\t\t__u8 nr;\n\t\t__u8 soft;\n\t\t__u8 shadow;\n\t} interrupt;\n\tstruct {\n\t\t__u8 injected;\n\t\t__u8 pending;\n\t\t__u8 masked;\n\t\t__u8 pad;\n\t} nmi;\n\t__u32 sipi_vector;\n\t__u32 flags;\n\tstruct {\n\t\t__u8 smm;\n\t\t__u8 pending;\n\t\t__u8 smm_inside_nmi;\n\t\t__u8 latched_init;\n\t} smi;\n\tstruct {\n\t\t__u8 pending;\n\t} triple_fault;\n\t__u8 reserved[26];\n\t__u8 exception_has_payload;\n\t__u64 exception_payload;\n};\n\nstruct kvm_sync_regs {\n\tstruct kvm_regs regs;\n\tstruct kvm_sregs sregs;\n\tstruct kvm_vcpu_events events;\n};\n\nstruct kvm_run {\n\t__u8 request_interrupt_window;\n\t__u8 immediate_exit__unsafe;\n\t__u8 padding1[6];\n\t__u32 exit_reason;\n\t__u8 ready_for_interrupt_injection;\n\t__u8 if_flag;\n\t__u16 flags;\n\t__u64 cr8;\n\t__u64 apic_base;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 hardware_exit_reason;\n\t\t} hw;\n\t\tstruct {\n\t\t\t__u64 hardware_entry_failure_reason;\n\t\t\t__u32 cpu;\n\t\t} fail_entry;\n\t\tstruct {\n\t\t\t__u32 exception;\n\t\t\t__u32 error_code;\n\t\t} ex;\n\t\tstruct {\n\t\t\t__u8 direction;\n\t\t\t__u8 size;\n\t\t\t__u16 port;\n\t\t\t__u32 count;\n\t\t\t__u64 data_offset;\n\t\t} io;\n\t\tstruct {\n\t\t\tstruct kvm_debug_exit_arch arch;\n\t\t} debug;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} mmio;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} iocsr_io;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u64 ret;\n\t\t\tunion {\n\t\t\t\t__u64 flags;\n\t\t\t};\n\t\t} hypercall;\n\t\tstruct {\n\t\t\t__u64 rip;\n\t\t\t__u32 is_write;\n\t\t\t__u32 pad;\n\t\t} tpr_access;\n\t\tstruct {\n\t\t\t__u8 icptcode;\n\t\t\t__u16 ipa;\n\t\t\t__u32 ipb;\n\t\t} s390_sieic;\n\t\t__u64 s390_reset_flags;\n\t\tstruct {\n\t\t\t__u64 trans_exc_code;\n\t\t\t__u32 pgm_code;\n\t\t} s390_ucontrol;\n\t\tstruct {\n\t\t\t__u32 dcrn;\n\t\t\t__u32 data;\n\t\t\t__u8 is_write;\n\t\t} dcr;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 data[16];\n\t\t} internal;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 flags;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 insn_size;\n\t\t\t\t\t__u8 insn_bytes[15];\n\t\t\t\t};\n\t\t\t};\n\t\t} emulation_failure;\n\t\tstruct {\n\t\t\t__u64 gprs[32];\n\t\t} osi;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 ret;\n\t\t\t__u64 args[9];\n\t\t} papr_hcall;\n\t\tstruct {\n\t\t\t__u16 subchannel_id;\n\t\t\t__u16 subchannel_nr;\n\t\t\t__u32 io_int_parm;\n\t\t\t__u32 io_int_word;\n\t\t\t__u32 ipb;\n\t\t\t__u8 dequeued;\n\t\t} s390_tsch;\n\t\tstruct {\n\t\t\t__u32 epr;\n\t\t} epr;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\t__u32 ndata;\n\t\t\tunion {\n\t\t\t\t__u64 data[16];\n\t\t\t};\n\t\t} system_event;\n\t\tstruct {\n\t\t\t__u64 addr;\n\t\t\t__u8 ar;\n\t\t\t__u8 reserved;\n\t\t\t__u8 fc;\n\t\t\t__u8 sel1;\n\t\t\t__u16 sel2;\n\t\t} s390_stsi;\n\t\tstruct {\n\t\t\t__u8 vector;\n\t\t} eoi;\n\t\tstruct kvm_hyperv_exit hyperv;\n\t\tstruct {\n\t\t\t__u64 esr_iss;\n\t\t\t__u64 fault_ipa;\n\t\t} arm_nisv;\n\t\tstruct {\n\t\t\t__u8 error;\n\t\t\t__u8 pad[7];\n\t\t\t__u32 reason;\n\t\t\t__u32 index;\n\t\t\t__u64 data;\n\t\t} msr;\n\t\tstruct kvm_xen_exit xen;\n\t\tstruct {\n\t\t\tlong unsigned int extension_id;\n\t\t\tlong unsigned int function_id;\n\t\t\tlong unsigned int args[6];\n\t\t\tlong unsigned int ret[2];\n\t\t} riscv_sbi;\n\t\tstruct {\n\t\t\tlong unsigned int csr_num;\n\t\t\tlong unsigned int new_value;\n\t\t\tlong unsigned int write_mask;\n\t\t\tlong unsigned int ret_value;\n\t\t} riscv_csr;\n\t\tstruct {\n\t\t\t__u32 flags;\n\t\t} notify;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 gpa;\n\t\t\t__u64 size;\n\t\t} memory_fault;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 nr;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 data[5];\n\t\t\t\t} unknown;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 gpa;\n\t\t\t\t\t__u64 size;\n\t\t\t\t} get_quote;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 leaf;\n\t\t\t\t\t__u64 r11;\n\t\t\t\t\t__u64 r12;\n\t\t\t\t\t__u64 r13;\n\t\t\t\t\t__u64 r14;\n\t\t\t\t} get_tdvmcall_info;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 vector;\n\t\t\t\t} setup_event_notify;\n\t\t\t};\n\t\t} tdx;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 esr;\n\t\t\t__u64 gva;\n\t\t\t__u64 gpa;\n\t\t} arm_sea;\n\t\tstruct kvm_exit_snp_req_certs snp_req_certs;\n\t\tchar padding[256];\n\t};\n\t__u64 kvm_valid_regs;\n\t__u64 kvm_dirty_regs;\n\tunion {\n\t\tstruct kvm_sync_regs regs;\n\t\tchar padding[2048];\n\t} s;\n};\n\nstruct kvm_stat_data {\n\tstruct kvm *kvm;\n\tconst struct _kvm_stats_desc *desc;\n\tenum kvm_stat_kind kind;\n};\n\nstruct kvm_steal_time {\n\t__u64 steal;\n\t__u32 version;\n\t__u32 flags;\n\t__u8 preempted;\n\t__u8 u8_pad[3];\n\t__u32 pad[11];\n};\n\nstruct kvm_task_sleep_head {\n\traw_spinlock_t lock;\n\tstruct hlist_head list;\n};\n\nstruct kvm_task_sleep_node {\n\tstruct hlist_node link;\n\tstruct swait_queue_head wq;\n\tu32 token;\n\tint cpu;\n\tbool dummy;\n};\n\nstruct x86_emulate_ctxt;\n\nstruct kvm_vcpu_arch {\n\tlong unsigned int regs[17];\n\tu32 regs_avail;\n\tu32 regs_dirty;\n\tlong unsigned int cr0;\n\tlong unsigned int cr0_guest_owned_bits;\n\tlong unsigned int cr2;\n\tlong unsigned int cr3;\n\tlong unsigned int cr4;\n\tlong unsigned int cr4_guest_owned_bits;\n\tlong unsigned int cr4_guest_rsvd_bits;\n\tlong unsigned int cr8;\n\tu32 host_pkru;\n\tu32 pkru;\n\tu32 hflags;\n\tu64 efer;\n\tu64 host_debugctl;\n\tu64 apic_base;\n\tstruct kvm_lapic *apic;\n\tbool load_eoi_exitmap_pending;\n\tlong unsigned int ioapic_handled_vectors[4];\n\tlong unsigned int apic_attention;\n\tint32_t apic_arb_prio;\n\tint mp_state;\n\tu64 ia32_misc_enable_msr;\n\tu64 smbase;\n\tu64 smi_count;\n\tbool at_instruction_boundary;\n\tbool tpr_access_reporting;\n\tbool xfd_no_write_intercept;\n\tu64 microcode_version;\n\tu64 arch_capabilities;\n\tu64 perf_capabilities;\n\tstruct kvm_mmu *mmu;\n\tstruct kvm_mmu root_mmu;\n\tstruct kvm_mmu guest_mmu;\n\tstruct kvm_mmu nested_mmu;\n\tstruct kvm_mmu *walk_mmu;\n\tstruct kvm_mmu_memory_cache mmu_pte_list_desc_cache;\n\tstruct kvm_mmu_memory_cache mmu_shadow_page_cache;\n\tstruct kvm_mmu_memory_cache mmu_shadowed_info_cache;\n\tstruct kvm_mmu_memory_cache mmu_page_header_cache;\n\tstruct kvm_mmu_memory_cache mmu_external_spt_cache;\n\tstruct fpu_guest guest_fpu;\n\tu64 xcr0;\n\tu64 guest_supported_xcr0;\n\tu64 ia32_xss;\n\tu64 guest_supported_xss;\n\tstruct kvm_pio_request pio;\n\tvoid *pio_data;\n\tvoid *sev_pio_data;\n\tunsigned int sev_pio_count;\n\tu8 event_exit_inst_len;\n\tbool exception_from_userspace;\n\tstruct kvm_queued_exception exception;\n\tstruct kvm_queued_exception exception_vmexit;\n\tstruct kvm_queued_interrupt interrupt;\n\tint halt_request;\n\tint cpuid_nent;\n\tstruct kvm_cpuid_entry2 *cpuid_entries;\n\tbool cpuid_dynamic_bits_dirty;\n\tbool is_amd_compatible;\n\tu32 cpu_caps[32];\n\tu64 reserved_gpa_bits;\n\tint maxphyaddr;\n\tstruct x86_emulate_ctxt *emulate_ctxt;\n\tbool emulate_regs_need_sync_to_vcpu;\n\tbool emulate_regs_need_sync_from_vcpu;\n\tint (*complete_userspace_io)(struct kvm_vcpu *);\n\tlong unsigned int cui_linear_rip;\n\tint cui_rdmsr_imm_reg;\n\tgpa_t time;\n\ts8 pvclock_tsc_shift;\n\tu32 pvclock_tsc_mul;\n\tunsigned int hw_tsc_khz;\n\tstruct gfn_to_pfn_cache pv_time;\n\tbool pvclock_set_guest_stopped_request;\n\tstruct {\n\t\tu8 preempted;\n\t\tu64 msr_val;\n\t\tu64 last_steal;\n\t\tstruct gfn_to_hva_cache cache;\n\t} st;\n\tu64 l1_tsc_offset;\n\tu64 tsc_offset;\n\tu64 last_guest_tsc;\n\tu64 last_host_tsc;\n\tu64 tsc_offset_adjustment;\n\tu64 this_tsc_nsec;\n\tu64 this_tsc_write;\n\tu64 this_tsc_generation;\n\tbool tsc_catchup;\n\tbool tsc_always_catchup;\n\ts8 virtual_tsc_shift;\n\tu32 virtual_tsc_mult;\n\tu32 virtual_tsc_khz;\n\ts64 ia32_tsc_adjust_msr;\n\tu64 msr_ia32_power_ctl;\n\tu64 l1_tsc_scaling_ratio;\n\tu64 tsc_scaling_ratio;\n\tatomic_t nmi_queued;\n\tunsigned int nmi_pending;\n\tbool nmi_injected;\n\tbool smi_pending;\n\tu8 handling_intr_from_guest;\n\tstruct kvm_mtrr mtrr_state;\n\tu64 pat;\n\tunsigned int switch_db_regs;\n\tlong unsigned int db[4];\n\tlong unsigned int dr6;\n\tlong unsigned int dr7;\n\tlong unsigned int eff_db[4];\n\tlong unsigned int guest_debug_dr7;\n\tu64 msr_platform_info;\n\tu64 msr_misc_features_enables;\n\tu64 mcg_cap;\n\tu64 mcg_status;\n\tu64 mcg_ctl;\n\tu64 mcg_ext_ctl;\n\tu64 *mce_banks;\n\tu64 *mci_ctl2_banks;\n\tu64 mmio_gva;\n\tunsigned int mmio_access;\n\tgfn_t mmio_gfn;\n\tu64 mmio_gen;\n\tstruct kvm_pmu pmu;\n\tlong unsigned int singlestep_rip;\n\tcpumask_var_t wbinvd_dirty_mask;\n\tlong unsigned int last_retry_eip;\n\tlong unsigned int last_retry_addr;\n\tstruct {\n\t\tbool halted;\n\t\tgfn_t gfns[64];\n\t\tstruct gfn_to_hva_cache data;\n\t\tu64 msr_en_val;\n\t\tu64 msr_int_val;\n\t\tu16 vec;\n\t\tu32 id;\n\t\tu32 host_apf_flags;\n\t\tbool send_always;\n\t\tbool delivery_as_pf_vmexit;\n\t\tbool pageready_pending;\n\t} apf;\n\tstruct {\n\t\tu64 length;\n\t\tu64 status;\n\t} osvw;\n\tstruct {\n\t\tu64 msr_val;\n\t\tstruct gfn_to_hva_cache data;\n\t} pv_eoi;\n\tu64 msr_kvm_poll_control;\n\tstruct {\n\t\tbool pv_unhalted;\n\t} pv;\n\tint pending_ioapic_eoi;\n\tint pending_external_vector;\n\tint highest_stale_pending_ioapic_eoi;\n\tbool preempted_in_kernel;\n\tint last_vmentry_cpu;\n\tu64 msr_hwcr;\n\tstruct {\n\t\tu32 features;\n\t\tbool enforce;\n\t} pv_cpuid;\n\tbool guest_state_protected;\n\tbool guest_tsc_protected;\n\tbool pdptrs_from_userspace;\n};\n\nstruct kvm_vcpu_stat_generic {\n\tu64 halt_successful_poll;\n\tu64 halt_attempted_poll;\n\tu64 halt_poll_invalid;\n\tu64 halt_wakeup;\n\tu64 halt_poll_success_ns;\n\tu64 halt_poll_fail_ns;\n\tu64 halt_wait_ns;\n\tu64 halt_poll_success_hist[32];\n\tu64 halt_poll_fail_hist[32];\n\tu64 halt_wait_hist[32];\n\tu64 blocking;\n};\n\nstruct kvm_vcpu_stat {\n\tstruct kvm_vcpu_stat_generic generic;\n\tu64 pf_taken;\n\tu64 pf_fixed;\n\tu64 pf_emulate;\n\tu64 pf_spurious;\n\tu64 pf_fast;\n\tu64 pf_mmio_spte_created;\n\tu64 pf_guest;\n\tu64 tlb_flush;\n\tu64 invlpg;\n\tu64 exits;\n\tu64 io_exits;\n\tu64 mmio_exits;\n\tu64 signal_exits;\n\tu64 irq_window_exits;\n\tu64 nmi_window_exits;\n\tu64 l1d_flush;\n\tu64 halt_exits;\n\tu64 request_irq_exits;\n\tu64 irq_exits;\n\tu64 host_state_reload;\n\tu64 fpu_reload;\n\tu64 insn_emulation;\n\tu64 insn_emulation_fail;\n\tu64 hypercalls;\n\tu64 irq_injections;\n\tu64 nmi_injections;\n\tu64 req_event;\n\tu64 nested_run;\n\tu64 directed_yield_attempted;\n\tu64 directed_yield_successful;\n\tu64 preemption_reported;\n\tu64 preemption_other;\n\tu64 guest_mode;\n\tu64 notify_window_exits;\n};\n\nstruct kvm_vcpu {\n\tstruct kvm *kvm;\n\tint cpu;\n\tint vcpu_id;\n\tint vcpu_idx;\n\tint ____srcu_idx;\n\tint mode;\n\tu64 requests;\n\tlong unsigned int guest_debug;\n\tstruct mutex mutex;\n\tstruct kvm_run *run;\n\tstruct rcuwait wait;\n\tstruct pid *pid;\n\trwlock_t pid_lock;\n\tint sigset_active;\n\tsigset_t sigset;\n\tunsigned int halt_poll_ns;\n\tbool valid_wakeup;\n\tint mmio_needed;\n\tint mmio_read_completed;\n\tint mmio_is_write;\n\tint mmio_cur_fragment;\n\tint mmio_nr_fragments;\n\tstruct kvm_mmio_fragment mmio_fragments[2];\n\tbool wants_to_run;\n\tbool preempted;\n\tbool ready;\n\tbool scheduled_out;\n\tstruct kvm_vcpu_arch arch;\n\tstruct kvm_vcpu_stat stat;\n\tchar stats_id[48];\n\tstruct kvm_dirty_ring dirty_ring;\n\tstruct kvm_memory_slot *last_used_slot;\n\tu64 last_used_slot_gen;\n};\n\nstruct kvm_vcpu_pv_apf_data {\n\t__u32 flags;\n\t__u32 token;\n\t__u8 pad[56];\n};\n\nstruct msr_bitmap_range {\n\tu32 flags;\n\tu32 nmsrs;\n\tu32 base;\n\tlong unsigned int *bitmap;\n};\n\nstruct kvm_x86_msr_filter {\n\tu8 count;\n\tbool default_allow: 1;\n\tstruct msr_bitmap_range ranges[16];\n};\n\nstruct kvm_x86_nested_ops {\n\tvoid (*leave_nested)(struct kvm_vcpu *);\n\tbool (*is_exception_vmexit)(struct kvm_vcpu *, u8, u32);\n\tint (*check_events)(struct kvm_vcpu *);\n\tbool (*has_events)(struct kvm_vcpu *, bool);\n\tvoid (*triple_fault)(struct kvm_vcpu *);\n\tint (*get_state)(struct kvm_vcpu *, struct kvm_nested_state *, unsigned int);\n\tint (*set_state)(struct kvm_vcpu *, struct kvm_nested_state *, struct kvm_nested_state *);\n\tbool (*get_nested_state_pages)(struct kvm_vcpu *);\n\tint (*write_log_dirty)(struct kvm_vcpu *, gpa_t);\n\tint (*enable_evmcs)(struct kvm_vcpu *, uint16_t *);\n\tuint16_t (*get_evmcs_version)(struct kvm_vcpu *);\n\tvoid (*hv_inject_synthetic_vmexit_post_tlb_flush)(struct kvm_vcpu *);\n};\n\ntypedef void cpu_emergency_virt_cb(void);\n\nstruct x86_instruction_info;\n\nstruct kvm_kernel_irqfd;\n\nstruct msr_data;\n\nstruct kvm_x86_ops {\n\tconst char *name;\n\tint (*check_processor_compatibility)(void);\n\tint (*enable_virtualization_cpu)(void);\n\tvoid (*disable_virtualization_cpu)(void);\n\tcpu_emergency_virt_cb *emergency_disable_virtualization_cpu;\n\tvoid (*hardware_unsetup)(void);\n\tbool (*has_emulated_msr)(struct kvm *, u32);\n\tvoid (*vcpu_after_set_cpuid)(struct kvm_vcpu *);\n\tunsigned int vm_size;\n\tint (*vm_init)(struct kvm *);\n\tvoid (*vm_destroy)(struct kvm *);\n\tvoid (*vm_pre_destroy)(struct kvm *);\n\tint (*vcpu_precreate)(struct kvm *);\n\tint (*vcpu_create)(struct kvm_vcpu *);\n\tvoid (*vcpu_free)(struct kvm_vcpu *);\n\tvoid (*vcpu_reset)(struct kvm_vcpu *, bool);\n\tvoid (*prepare_switch_to_guest)(struct kvm_vcpu *);\n\tvoid (*vcpu_load)(struct kvm_vcpu *, int);\n\tvoid (*vcpu_put)(struct kvm_vcpu *);\n\tconst u64 HOST_OWNED_DEBUGCTL;\n\tvoid (*update_exception_bitmap)(struct kvm_vcpu *);\n\tint (*get_msr)(struct kvm_vcpu *, struct msr_data *);\n\tint (*set_msr)(struct kvm_vcpu *, struct msr_data *);\n\tu64 (*get_segment_base)(struct kvm_vcpu *, int);\n\tvoid (*get_segment)(struct kvm_vcpu *, struct kvm_segment *, int);\n\tint (*get_cpl)(struct kvm_vcpu *);\n\tint (*get_cpl_no_cache)(struct kvm_vcpu *);\n\tvoid (*set_segment)(struct kvm_vcpu *, struct kvm_segment *, int);\n\tvoid (*get_cs_db_l_bits)(struct kvm_vcpu *, int *, int *);\n\tbool (*is_valid_cr0)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*set_cr0)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*post_set_cr3)(struct kvm_vcpu *, long unsigned int);\n\tbool (*is_valid_cr4)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*set_cr4)(struct kvm_vcpu *, long unsigned int);\n\tint (*set_efer)(struct kvm_vcpu *, u64);\n\tvoid (*get_idt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*set_idt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*get_gdt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*set_gdt)(struct kvm_vcpu *, struct desc_ptr *);\n\tvoid (*sync_dirty_debug_regs)(struct kvm_vcpu *);\n\tvoid (*set_dr7)(struct kvm_vcpu *, long unsigned int);\n\tvoid (*cache_reg)(struct kvm_vcpu *, enum kvm_reg);\n\tlong unsigned int (*get_rflags)(struct kvm_vcpu *);\n\tvoid (*set_rflags)(struct kvm_vcpu *, long unsigned int);\n\tbool (*get_if_flag)(struct kvm_vcpu *);\n\tvoid (*flush_tlb_all)(struct kvm_vcpu *);\n\tvoid (*flush_tlb_current)(struct kvm_vcpu *);\n\tvoid (*flush_tlb_gva)(struct kvm_vcpu *, gva_t);\n\tvoid (*flush_tlb_guest)(struct kvm_vcpu *);\n\tint (*vcpu_pre_run)(struct kvm_vcpu *);\n\tenum exit_fastpath_completion (*vcpu_run)(struct kvm_vcpu *, u64);\n\tint (*handle_exit)(struct kvm_vcpu *, enum exit_fastpath_completion);\n\tint (*skip_emulated_instruction)(struct kvm_vcpu *);\n\tvoid (*update_emulated_instruction)(struct kvm_vcpu *);\n\tvoid (*set_interrupt_shadow)(struct kvm_vcpu *, int);\n\tu32 (*get_interrupt_shadow)(struct kvm_vcpu *);\n\tvoid (*patch_hypercall)(struct kvm_vcpu *, unsigned char *);\n\tvoid (*inject_irq)(struct kvm_vcpu *, bool);\n\tvoid (*inject_nmi)(struct kvm_vcpu *);\n\tvoid (*inject_exception)(struct kvm_vcpu *);\n\tvoid (*cancel_injection)(struct kvm_vcpu *);\n\tint (*interrupt_allowed)(struct kvm_vcpu *, bool);\n\tint (*nmi_allowed)(struct kvm_vcpu *, bool);\n\tbool (*get_nmi_mask)(struct kvm_vcpu *);\n\tvoid (*set_nmi_mask)(struct kvm_vcpu *, bool);\n\tbool (*is_vnmi_pending)(struct kvm_vcpu *);\n\tbool (*set_vnmi_pending)(struct kvm_vcpu *);\n\tvoid (*enable_nmi_window)(struct kvm_vcpu *);\n\tvoid (*enable_irq_window)(struct kvm_vcpu *);\n\tvoid (*update_cr8_intercept)(struct kvm_vcpu *, int, int);\n\tconst bool x2apic_icr_is_split;\n\tconst long unsigned int required_apicv_inhibits;\n\tbool allow_apicv_in_x2apic_without_x2apic_virtualization;\n\tvoid (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *);\n\tvoid (*hwapic_isr_update)(struct kvm_vcpu *, int);\n\tvoid (*load_eoi_exitmap)(struct kvm_vcpu *, u64 *);\n\tvoid (*set_virtual_apic_mode)(struct kvm_vcpu *);\n\tvoid (*set_apic_access_page_addr)(struct kvm_vcpu *);\n\tvoid (*deliver_interrupt)(struct kvm_lapic *, int, int, int);\n\tint (*sync_pir_to_irr)(struct kvm_vcpu *);\n\tint (*set_tss_addr)(struct kvm *, unsigned int);\n\tint (*set_identity_map_addr)(struct kvm *, u64);\n\tu8 (*get_mt_mask)(struct kvm_vcpu *, gfn_t, bool);\n\tvoid (*load_mmu_pgd)(struct kvm_vcpu *, hpa_t, int);\n\tint (*link_external_spt)(struct kvm *, gfn_t, enum pg_level, void *);\n\tint (*set_external_spte)(struct kvm *, gfn_t, enum pg_level, u64);\n\tint (*free_external_spt)(struct kvm *, gfn_t, enum pg_level, void *);\n\tvoid (*remove_external_spte)(struct kvm *, gfn_t, enum pg_level, u64);\n\tbool (*has_wbinvd_exit)(void);\n\tu64 (*get_l2_tsc_offset)(struct kvm_vcpu *);\n\tu64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *);\n\tvoid (*write_tsc_offset)(struct kvm_vcpu *);\n\tvoid (*write_tsc_multiplier)(struct kvm_vcpu *);\n\tvoid (*get_exit_info)(struct kvm_vcpu *, u32 *, u64 *, u64 *, u32 *, u32 *);\n\tvoid (*get_entry_info)(struct kvm_vcpu *, u32 *, u32 *);\n\tint (*check_intercept)(struct kvm_vcpu *, struct x86_instruction_info *, enum x86_intercept_stage, struct x86_exception *);\n\tvoid (*handle_exit_irqoff)(struct kvm_vcpu *);\n\tvoid (*update_cpu_dirty_logging)(struct kvm_vcpu *);\n\tconst struct kvm_x86_nested_ops *nested_ops;\n\tvoid (*vcpu_blocking)(struct kvm_vcpu *);\n\tvoid (*vcpu_unblocking)(struct kvm_vcpu *);\n\tint (*pi_update_irte)(struct kvm_kernel_irqfd *, struct kvm *, unsigned int, uint32_t, struct kvm_vcpu *, u32);\n\tvoid (*pi_start_bypass)(struct kvm *);\n\tvoid (*apicv_pre_state_restore)(struct kvm_vcpu *);\n\tvoid (*apicv_post_state_restore)(struct kvm_vcpu *);\n\tbool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *);\n\tbool (*protected_apic_has_interrupt)(struct kvm_vcpu *);\n\tint (*set_hv_timer)(struct kvm_vcpu *, u64, bool *);\n\tvoid (*cancel_hv_timer)(struct kvm_vcpu *);\n\tvoid (*setup_mce)(struct kvm_vcpu *);\n\tint (*dev_get_attr)(u32, u64, u64 *);\n\tint (*mem_enc_ioctl)(struct kvm *, void *);\n\tint (*vcpu_mem_enc_ioctl)(struct kvm_vcpu *, void *);\n\tint (*vcpu_mem_enc_unlocked_ioctl)(struct kvm_vcpu *, void *);\n\tint (*mem_enc_register_region)(struct kvm *, struct kvm_enc_region *);\n\tint (*mem_enc_unregister_region)(struct kvm *, struct kvm_enc_region *);\n\tint (*vm_copy_enc_context_from)(struct kvm *, unsigned int);\n\tint (*vm_move_enc_context_from)(struct kvm *, unsigned int);\n\tvoid (*guest_memory_reclaimed)(struct kvm *);\n\tint (*get_feature_msr)(u32, u64 *);\n\tint (*check_emulate_instruction)(struct kvm_vcpu *, int, void *, int);\n\tbool (*apic_init_signal_blocked)(struct kvm_vcpu *);\n\tint (*enable_l2_tlb_flush)(struct kvm_vcpu *);\n\tvoid (*migrate_timers)(struct kvm_vcpu *);\n\tvoid (*recalc_intercepts)(struct kvm_vcpu *);\n\tint (*complete_emulated_msr)(struct kvm_vcpu *, int);\n\tvoid (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *, u8);\n\tlong unsigned int (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *);\n\tgva_t (*get_untagged_addr)(struct kvm_vcpu *, gva_t, unsigned int);\n\tvoid * (*alloc_apic_backing_page)(struct kvm_vcpu *);\n\tint (*gmem_prepare)(struct kvm *, kvm_pfn_t, gfn_t, int);\n\tvoid (*gmem_invalidate)(kvm_pfn_t, kvm_pfn_t);\n\tint (*gmem_max_mapping_level)(struct kvm *, kvm_pfn_t, bool);\n};\n\nstruct kvm_x86_pmu_event_filter {\n\t__u32 action;\n\t__u32 nevents;\n\t__u32 fixed_counter_bitmap;\n\t__u32 flags;\n\t__u32 nr_includes;\n\t__u32 nr_excludes;\n\t__u64 *includes;\n\t__u64 *excludes;\n\t__u64 events[0];\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nunion l1_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 8;\n\t\tunsigned int assoc: 8;\n\t\tunsigned int size_in_kb: 8;\n\t};\n\tunsigned int val;\n};\n\nunion l2_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 4;\n\t\tunsigned int assoc: 4;\n\t\tunsigned int size_in_kb: 16;\n\t};\n\tunsigned int val;\n};\n\nunion l3_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 4;\n\t\tunsigned int assoc: 4;\n\t\tunsigned int res: 2;\n\t\tunsigned int size_encoded: 14;\n\t};\n\tunsigned int val;\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tu64 val[2];\n};\n\nstruct layout_verification {\n\tu32 mode;\n\tu64 start;\n\tu64 inval;\n\tu64 cowread;\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct ldt_struct {\n\tstruct desc_struct *entries;\n\tunsigned int nr_entries;\n\tint slot;\n};\n\nstruct ldttss_desc {\n\tu16 limit0;\n\tu16 base0;\n\tu16 base1: 8;\n\tu16 type: 5;\n\tu16 dpl: 2;\n\tu16 p: 1;\n\tu16 limit1: 4;\n\tu16 zero0: 3;\n\tu16 g: 1;\n\tu16 base2: 8;\n\tu32 base3;\n\tu32 zero1;\n};\n\ntypedef struct ldttss_desc ldt_desc;\n\ntypedef struct ldttss_desc tss_desc;\n\nstruct leaf_0x2_reg {\n\tint: 31;\n\tu32 invalid: 1;\n};\n\nunion leaf_0x2_regs {\n\tstruct leaf_0x2_reg reg[4];\n\tu32 regv[4];\n\tu8 desc[16];\n};\n\nstruct leaf_0x2_table {\n\tunion {\n\t\tenum _cache_table_type c_type;\n\t\tenum _tlb_table_type t_type;\n\t};\n\tunion {\n\t\tshort int c_size;\n\t\tshort int entries;\n\t};\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct mc_subled;\n\nstruct led_classdev_mc {\n\tstruct led_classdev led_cdev;\n\tunsigned int num_colors;\n\tstruct mc_subled *subled_info;\n};\n\nstruct led_hw_trigger_type {\n\tint dummy;\n};\n\nstruct led_init_data {\n\tstruct fwnode_handle *fwnode;\n\tconst char *default_label;\n\tconst char *devicename;\n\tbool devname_mandatory;\n};\n\nstruct led_lookup_data {\n\tstruct list_head list;\n\tconst char *provider;\n\tconst char *dev_id;\n\tconst char *con_id;\n};\n\nstruct led_pattern {\n\tu32 delta_t;\n\tint brightness;\n};\n\nstruct led_properties {\n\tu32 color;\n\tbool color_present;\n\tconst char *function;\n\tu32 func_enum;\n\tbool func_enum_present;\n\tconst char *label;\n};\n\nstruct legacy_pic {\n\tint nr_legacy_irqs;\n\tstruct irq_chip *chip;\n\tvoid (*mask)(unsigned int);\n\tvoid (*unmask)(unsigned int);\n\tvoid (*mask_all)(void);\n\tvoid (*restore_mask)(void);\n\tvoid (*init)(int);\n\tint (*probe)(void);\n\tint (*irq_pending)(unsigned int);\n\tvoid (*make_irq)(unsigned int);\n};\n\nstruct legacy_ring {\n\tstruct intel_gt *gt;\n\tu8 class;\n\tu8 instance;\n};\n\nstruct level_datum {\n\tstruct mls_level level;\n\tunsigned char isalias;\n};\n\nstruct lifebook_data {\n\tstruct input_dev *dev2;\n\tchar phys[32];\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linear_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_capabilities {\n\tint speed;\n\tunsigned int duplex;\n\tlong unsigned int linkmodes[2];\n};\n\nstruct link_config_limits {\n\tint min_rate;\n\tint max_rate;\n\tint min_lane_count;\n\tint max_lane_count;\n\tstruct {\n\t\tint min_bpp;\n\t\tint max_bpp;\n\t} pipe;\n\tstruct {\n\t\tint min_bpp_x16;\n\t\tint max_bpp_x16;\n\t} link;\n};\n\nstruct link_container {\n\tstruct ieee80211_link_data data;\n\tstruct ieee80211_bss_conf conf;\n};\n\nstruct link_ctl_info {\n\tsnd_ctl_elem_type_t type;\n\tint count;\n\tint min_val;\n\tint max_val;\n};\n\nstruct snd_ctl_elem_id {\n\tunsigned int numid;\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tunsigned char name[44];\n\tunsigned int index;\n};\n\nstruct snd_ctl_elem_info;\n\ntypedef int snd_kcontrol_info_t(struct snd_kcontrol *, struct snd_ctl_elem_info *);\n\nstruct snd_ctl_elem_value;\n\ntypedef int snd_kcontrol_get_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_put_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_tlv_rw_t(struct snd_kcontrol *, int, unsigned int, unsigned int *);\n\nstruct snd_ctl_file;\n\nstruct snd_kcontrol_volatile {\n\tstruct snd_ctl_file *owner;\n\tunsigned int access;\n};\n\nstruct snd_kcontrol {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_kcontrol *);\n\tstruct snd_kcontrol_volatile vd[0];\n};\n\nstruct link_master;\n\nstruct link_follower {\n\tstruct list_head list;\n\tstruct link_master *master;\n\tstruct link_ctl_info info;\n\tint vals[2];\n\tunsigned int flags;\n\tstruct snd_kcontrol *kctl;\n\tstruct snd_kcontrol follower;\n};\n\nstruct link_master {\n\tstruct list_head followers;\n\tstruct link_ctl_info info;\n\tint val;\n\tunsigned int tlv[4];\n\tvoid (*hook)(void *, int);\n\tvoid *hook_private_data;\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct link_sta_info {\n\tu8 addr[6];\n\tu8 link_id;\n\tu8 op_mode_nss;\n\tu8 capa_nss;\n\tstruct rhlist_head link_hash_node;\n\tstruct sta_info *sta;\n\tstruct ieee80211_key *gtk[8];\n\tstruct ieee80211_sta_rx_stats *pcpu_rx_stats;\n\tstruct ieee80211_sta_rx_stats rx_stats;\n\tstruct {\n\t\tstruct ewma_signal signal;\n\t\tstruct ewma_signal chain_signal[4];\n\t} rx_stats_avg;\n\tstruct {\n\t\tlong unsigned int filtered;\n\t\tlong unsigned int retry_failed;\n\t\tlong unsigned int retry_count;\n\t\tunsigned int lost_packets;\n\t\tlong unsigned int last_pkt_time;\n\t\tu64 msdu_retries[17];\n\t\tu64 msdu_failed[17];\n\t\tlong unsigned int last_ack;\n\t\ts8 last_ack_signal;\n\t\tbool ack_signal_filled;\n\t\tstruct ewma_avg_signal avg_ack_signal;\n\t} status_stats;\n\tstruct {\n\t\tu64 packets[4];\n\t\tu64 bytes[4];\n\t\tstruct ieee80211_tx_rate last_rate;\n\t\tstruct rate_info last_rate_info;\n\t\tu64 msdu[17];\n\t} tx_stats;\n\tenum ieee80211_sta_rx_bandwidth cur_max_bandwidth;\n\tenum ieee80211_sta_rx_bandwidth rx_omi_bw_rx;\n\tenum ieee80211_sta_rx_bandwidth rx_omi_bw_tx;\n\tenum ieee80211_sta_rx_bandwidth rx_omi_bw_staging;\n\tstruct ieee80211_link_sta *pub;\n};\n\nstruct link_station_del_parameters {\n\tconst u8 *mld_mac;\n\tu32 link_id;\n};\n\nstruct sta_bss_parameters {\n\tu8 flags;\n\tu8 dtim_period;\n\tu16 beacon_interval;\n};\n\nstruct link_station_info {\n\tu64 filled;\n\tu32 connected_time;\n\tu32 inactive_time;\n\tu64 assoc_at;\n\tu64 rx_bytes;\n\tu64 tx_bytes;\n\ts8 signal;\n\ts8 signal_avg;\n\tu8 chains;\n\ts8 chain_signal[4];\n\ts8 chain_signal_avg[4];\n\tstruct rate_info txrate;\n\tstruct rate_info rxrate;\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tstruct sta_bss_parameters bss_param;\n\tu32 beacon_loss_count;\n\tu32 expected_throughput;\n\tu64 tx_duration;\n\tu64 rx_duration;\n\tu64 rx_beacon;\n\tu8 rx_beacon_signal_avg;\n\tu16 airtime_weight;\n\ts8 ack_signal;\n\ts8 avg_ack_signal;\n\tstruct cfg80211_tid_stats *pertid;\n\tu32 rx_mpdu_count;\n\tu32 fcs_err_count;\n\tu8 addr[6];\n};\n\nstruct sta_txpwr {\n\ts16 power;\n\tenum nl80211_tx_power_setting type;\n};\n\nstruct link_station_parameters {\n\tconst u8 *mld_mac;\n\tint link_id;\n\tconst u8 *link_mac;\n\tconst u8 *supported_rates;\n\tu8 supported_rates_len;\n\tconst struct ieee80211_ht_cap *ht_capa;\n\tconst struct ieee80211_vht_cap *vht_capa;\n\tu8 opmode_notif;\n\tbool opmode_notif_used;\n\tconst struct ieee80211_he_cap_elem *he_capa;\n\tu8 he_capa_len;\n\tstruct sta_txpwr txpwr;\n\tbool txpwr_set;\n\tconst struct ieee80211_he_6ghz_capa *he_6ghz_capa;\n\tconst struct ieee80211_eht_cap_elem *eht_capa;\n\tu8 eht_capa_len;\n\tconst struct ieee80211_s1g_cap *s1g_capa;\n\tconst struct ieee80211_uhr_cap *uhr_capa;\n\tu8 uhr_capa_len;\n};\n\nstruct linked_page {\n\tstruct linked_page *next;\n\tchar data[4088];\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n};\n\nstruct linux_efi_initrd {\n\tlong unsigned int base;\n\tlong unsigned int size;\n};\n\nstruct linux_efi_memreserve {\n\tint size;\n\tatomic_t count;\n\tphys_addr_t next;\n\tstruct {\n\t\tphys_addr_t base;\n\t\tphys_addr_t size;\n\t} entry[0];\n};\n\nstruct linux_efi_random_seed {\n\tu32 size;\n\tu8 bits[0];\n};\n\nstruct linux_efi_tpm_eventlog {\n\tu32 size;\n\tu32 final_events_preboot_size;\n\tu8 version;\n\tu8 log[0];\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct listener {\n\tstruct list_head list;\n\tpid_t pid;\n\tchar valid;\n};\n\nstruct listener_list {\n\tstruct rw_semaphore sem;\n\tstruct list_head list;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf64_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct location;\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n\tloff_t idx;\n};\n\nstruct local_event {\n\tlocal_lock_t lock;\n\t__u32 count;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct location {\n\tdepot_stack_handle_t handle;\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong unsigned int waste;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[1];\n\tnodemask_t nodes;\n};\n\nstruct lock_manager {\n\tstruct list_head list;\n\tbool block_opens;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct lockd_net {\n\tunsigned int nlmsvc_users;\n\tlong unsigned int next_gc;\n\tlong unsigned int nrhosts;\n\tu32 gracetime;\n\tu16 tcp_port;\n\tu16 udp_port;\n\tstruct delayed_work grace_period_end;\n\tstruct lock_manager lockd_manager;\n\tstruct list_head nsm_handles;\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tloff_t li_pos;\n};\n\nstruct log_header_core {\n\tuint32_t magic;\n\tuint32_t version;\n\tuint64_t nr_regions;\n};\n\nstruct log_header_disk;\n\nstruct log_c {\n\tstruct dm_target *ti;\n\tint touched_dirtied;\n\tint touched_cleaned;\n\tint flush_failed;\n\tuint32_t region_size;\n\tunsigned int region_count;\n\tregion_t sync_count;\n\tunsigned int bitset_uint32_count;\n\tuint32_t *clean_bits;\n\tuint32_t *sync_bits;\n\tuint32_t *recovering_bits;\n\tint sync_search;\n\tenum sync sync;\n\tstruct dm_io_request io_req;\n\tint log_dev_failed;\n\tint log_dev_flush_failed;\n\tstruct dm_dev *log_dev;\n\tstruct log_header_core header;\n\tstruct dm_io_region header_location;\n\tstruct log_header_disk *disk_header;\n};\n\nstruct log_header_disk {\n\t__le32 magic;\n\t__le32 version;\n\t__le64 nr_regions;\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct lookup_args {\n\tint offset;\n\tconst struct in6_addr *addr;\n};\n\nstruct loop_cmd {\n\tstruct list_head list_entry;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct cgroup_subsys_state *memcg_css;\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nstruct loop_device {\n\tint lo_number;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tchar lo_file_name[64];\n\tstruct file *lo_backing_file;\n\tunsigned int lo_min_dio_size;\n\tstruct block_device *lo_device;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tspinlock_t lo_work_lock;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rootcg_work;\n\tstruct list_head rootcg_cmd_list;\n\tstruct list_head idle_worker_list;\n\tstruct rb_root worker_tree;\n\tstruct timer_list timer;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n\tstruct mutex lo_mutex;\n\tbool idr_visible;\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_worker {\n\tstruct rb_node rb_node;\n\tstruct work_struct work;\n\tstruct list_head cmd_list;\n\tstruct list_head idle_list;\n\tstruct loop_device *lo;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tlong unsigned int last_ran_at;\n};\n\nunion lower_chunk {\n\tunion lower_chunk *next;\n\tlong unsigned int data[256];\n};\n\nstruct lpi_constraints {\n\tacpi_handle handle;\n\tint min_dstate;\n};\n\nstruct lpi_device_constraint {\n\tint uid;\n\tint min_dstate;\n\tint function_states;\n};\n\nstruct lpi_device_constraint_amd {\n\tchar *name;\n\tint enabled;\n\tint function_states;\n\tint min_dstate;\n};\n\nstruct lpi_device_info {\n\tchar *name;\n\tint enabled;\n\tunion acpi_object *package;\n};\n\nstruct lpit_residency_info {\n\tstruct acpi_generic_address gaddr;\n\tu64 frequency;\n\tvoid *iomem_addr;\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct lpss8250_board;\n\nstruct lpss8250 {\n\tstruct dw8250_port_data data;\n\tstruct lpss8250_board *board;\n\tstruct dw_dma_chip dma_chip;\n\tstruct dw_dma_slave dma_param;\n\tu8 dma_maxburst;\n};\n\nstruct lpss8250_board {\n\tlong unsigned int freq;\n\tunsigned int base_baud;\n\tint (*setup)(struct lpss8250 *, struct uart_port *);\n\tvoid (*exit)(struct lpss8250 *);\n};\n\nstruct lri {\n\ti915_reg_t reg;\n\tu32 value;\n};\n\nstruct zswap_lruvec_state {};\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct skcipher_alg_common {\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct lskcipher_alg {\n\tint (*setkey)(struct crypto_lskcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*decrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*init)(struct crypto_lskcipher *);\n\tvoid (*exit)(struct crypto_lskcipher *);\n\tstruct skcipher_alg_common co;\n};\n\nstruct lskcipher_instance {\n\tvoid (*free)(struct lskcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct lskcipher_alg alg;\n\t};\n};\n\nstruct lsm_blob_sizes {\n\tunsigned int lbs_cred;\n\tunsigned int lbs_file;\n\tunsigned int lbs_ib;\n\tunsigned int lbs_inode;\n\tunsigned int lbs_sock;\n\tunsigned int lbs_superblock;\n\tunsigned int lbs_ipc;\n\tunsigned int lbs_key;\n\tunsigned int lbs_msg_msg;\n\tunsigned int lbs_perf_event;\n\tunsigned int lbs_task;\n\tunsigned int lbs_xattr_count;\n\tunsigned int lbs_tun_dev;\n\tunsigned int lbs_bdev;\n\tunsigned int lbs_bpf_map;\n\tunsigned int lbs_bpf_prog;\n\tunsigned int lbs_bpf_token;\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct lsm_ctx {\n\t__u64 id;\n\t__u64 flags;\n\t__u64 len;\n\t__u64 ctx_len;\n\t__u8 ctx[0];\n};\n\nstruct lsm_ibendport_audit {\n\tconst char *dev_name;\n\tu8 port;\n};\n\nstruct lsm_ibpkey_audit {\n\tu64 subnet_prefix;\n\tu16 pkey;\n};\n\nstruct lsm_id {\n\tconst char *name;\n\tu64 id;\n};\n\nstruct lsm_info {\n\tconst struct lsm_id *id;\n\tenum lsm_order order;\n\tlong unsigned int flags;\n\tstruct lsm_blob_sizes *blobs;\n\tint *enabled;\n\tint (*init)(void);\n\tint (*initcall_pure)(void);\n\tint (*initcall_early)(void);\n\tint (*initcall_core)(void);\n\tint (*initcall_subsys)(void);\n\tint (*initcall_fs)(void);\n\tint (*initcall_device)(void);\n\tint (*initcall_late)(void);\n};\n\nstruct lsm_ioctlop_audit {\n\tstruct path path;\n\tu16 cmd;\n};\n\nstruct lsm_network_audit {\n\tint netif;\n\tconst struct sock *sk;\n\tu16 family;\n\t__be16 dport;\n\t__be16 sport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 daddr;\n\t\t\t__be32 saddr;\n\t\t} v4;\n\t\tstruct {\n\t\t\tstruct in6_addr daddr;\n\t\t\tstruct in6_addr saddr;\n\t\t} v6;\n\t} fam;\n};\n\nstruct security_hook_list;\n\nstruct lsm_static_call {\n\tstruct static_call_key *key;\n\tvoid *trampoline;\n\tstruct security_hook_list *hl;\n\tstruct static_key_false *active;\n};\n\nstruct lsm_static_calls_table {\n\tstruct lsm_static_call binder_set_context_mgr[2];\n\tstruct lsm_static_call binder_transaction[2];\n\tstruct lsm_static_call binder_transfer_binder[2];\n\tstruct lsm_static_call binder_transfer_file[2];\n\tstruct lsm_static_call ptrace_access_check[2];\n\tstruct lsm_static_call ptrace_traceme[2];\n\tstruct lsm_static_call capget[2];\n\tstruct lsm_static_call capset[2];\n\tstruct lsm_static_call capable[2];\n\tstruct lsm_static_call quotactl[2];\n\tstruct lsm_static_call quota_on[2];\n\tstruct lsm_static_call syslog[2];\n\tstruct lsm_static_call settime[2];\n\tstruct lsm_static_call vm_enough_memory[2];\n\tstruct lsm_static_call bprm_creds_for_exec[2];\n\tstruct lsm_static_call bprm_creds_from_file[2];\n\tstruct lsm_static_call bprm_check_security[2];\n\tstruct lsm_static_call bprm_committing_creds[2];\n\tstruct lsm_static_call bprm_committed_creds[2];\n\tstruct lsm_static_call fs_context_submount[2];\n\tstruct lsm_static_call fs_context_dup[2];\n\tstruct lsm_static_call fs_context_parse_param[2];\n\tstruct lsm_static_call sb_alloc_security[2];\n\tstruct lsm_static_call sb_delete[2];\n\tstruct lsm_static_call sb_free_security[2];\n\tstruct lsm_static_call sb_free_mnt_opts[2];\n\tstruct lsm_static_call sb_eat_lsm_opts[2];\n\tstruct lsm_static_call sb_mnt_opts_compat[2];\n\tstruct lsm_static_call sb_remount[2];\n\tstruct lsm_static_call sb_kern_mount[2];\n\tstruct lsm_static_call sb_show_options[2];\n\tstruct lsm_static_call sb_statfs[2];\n\tstruct lsm_static_call sb_mount[2];\n\tstruct lsm_static_call sb_umount[2];\n\tstruct lsm_static_call sb_pivotroot[2];\n\tstruct lsm_static_call sb_set_mnt_opts[2];\n\tstruct lsm_static_call sb_clone_mnt_opts[2];\n\tstruct lsm_static_call move_mount[2];\n\tstruct lsm_static_call dentry_init_security[2];\n\tstruct lsm_static_call dentry_create_files_as[2];\n\tstruct lsm_static_call path_notify[2];\n\tstruct lsm_static_call inode_alloc_security[2];\n\tstruct lsm_static_call inode_free_security[2];\n\tstruct lsm_static_call inode_free_security_rcu[2];\n\tstruct lsm_static_call inode_init_security[2];\n\tstruct lsm_static_call inode_init_security_anon[2];\n\tstruct lsm_static_call inode_create[2];\n\tstruct lsm_static_call inode_post_create_tmpfile[2];\n\tstruct lsm_static_call inode_link[2];\n\tstruct lsm_static_call inode_unlink[2];\n\tstruct lsm_static_call inode_symlink[2];\n\tstruct lsm_static_call inode_mkdir[2];\n\tstruct lsm_static_call inode_rmdir[2];\n\tstruct lsm_static_call inode_mknod[2];\n\tstruct lsm_static_call inode_rename[2];\n\tstruct lsm_static_call inode_readlink[2];\n\tstruct lsm_static_call inode_follow_link[2];\n\tstruct lsm_static_call inode_permission[2];\n\tstruct lsm_static_call inode_setattr[2];\n\tstruct lsm_static_call inode_post_setattr[2];\n\tstruct lsm_static_call inode_getattr[2];\n\tstruct lsm_static_call inode_xattr_skipcap[2];\n\tstruct lsm_static_call inode_setxattr[2];\n\tstruct lsm_static_call inode_post_setxattr[2];\n\tstruct lsm_static_call inode_getxattr[2];\n\tstruct lsm_static_call inode_listxattr[2];\n\tstruct lsm_static_call inode_removexattr[2];\n\tstruct lsm_static_call inode_post_removexattr[2];\n\tstruct lsm_static_call inode_file_setattr[2];\n\tstruct lsm_static_call inode_file_getattr[2];\n\tstruct lsm_static_call inode_set_acl[2];\n\tstruct lsm_static_call inode_post_set_acl[2];\n\tstruct lsm_static_call inode_get_acl[2];\n\tstruct lsm_static_call inode_remove_acl[2];\n\tstruct lsm_static_call inode_post_remove_acl[2];\n\tstruct lsm_static_call inode_need_killpriv[2];\n\tstruct lsm_static_call inode_killpriv[2];\n\tstruct lsm_static_call inode_getsecurity[2];\n\tstruct lsm_static_call inode_setsecurity[2];\n\tstruct lsm_static_call inode_listsecurity[2];\n\tstruct lsm_static_call inode_getlsmprop[2];\n\tstruct lsm_static_call inode_copy_up[2];\n\tstruct lsm_static_call inode_copy_up_xattr[2];\n\tstruct lsm_static_call inode_setintegrity[2];\n\tstruct lsm_static_call kernfs_init_security[2];\n\tstruct lsm_static_call file_permission[2];\n\tstruct lsm_static_call file_alloc_security[2];\n\tstruct lsm_static_call file_release[2];\n\tstruct lsm_static_call file_free_security[2];\n\tstruct lsm_static_call file_ioctl[2];\n\tstruct lsm_static_call file_ioctl_compat[2];\n\tstruct lsm_static_call mmap_addr[2];\n\tstruct lsm_static_call mmap_file[2];\n\tstruct lsm_static_call file_mprotect[2];\n\tstruct lsm_static_call file_lock[2];\n\tstruct lsm_static_call file_fcntl[2];\n\tstruct lsm_static_call file_set_fowner[2];\n\tstruct lsm_static_call file_send_sigiotask[2];\n\tstruct lsm_static_call file_receive[2];\n\tstruct lsm_static_call file_open[2];\n\tstruct lsm_static_call file_post_open[2];\n\tstruct lsm_static_call file_truncate[2];\n\tstruct lsm_static_call task_alloc[2];\n\tstruct lsm_static_call task_free[2];\n\tstruct lsm_static_call cred_alloc_blank[2];\n\tstruct lsm_static_call cred_free[2];\n\tstruct lsm_static_call cred_prepare[2];\n\tstruct lsm_static_call cred_transfer[2];\n\tstruct lsm_static_call cred_getsecid[2];\n\tstruct lsm_static_call cred_getlsmprop[2];\n\tstruct lsm_static_call kernel_act_as[2];\n\tstruct lsm_static_call kernel_create_files_as[2];\n\tstruct lsm_static_call kernel_module_request[2];\n\tstruct lsm_static_call kernel_load_data[2];\n\tstruct lsm_static_call kernel_post_load_data[2];\n\tstruct lsm_static_call kernel_read_file[2];\n\tstruct lsm_static_call kernel_post_read_file[2];\n\tstruct lsm_static_call task_fix_setuid[2];\n\tstruct lsm_static_call task_fix_setgid[2];\n\tstruct lsm_static_call task_fix_setgroups[2];\n\tstruct lsm_static_call task_setpgid[2];\n\tstruct lsm_static_call task_getpgid[2];\n\tstruct lsm_static_call task_getsid[2];\n\tstruct lsm_static_call current_getlsmprop_subj[2];\n\tstruct lsm_static_call task_getlsmprop_obj[2];\n\tstruct lsm_static_call task_setnice[2];\n\tstruct lsm_static_call task_setioprio[2];\n\tstruct lsm_static_call task_getioprio[2];\n\tstruct lsm_static_call task_prlimit[2];\n\tstruct lsm_static_call task_setrlimit[2];\n\tstruct lsm_static_call task_setscheduler[2];\n\tstruct lsm_static_call task_getscheduler[2];\n\tstruct lsm_static_call task_movememory[2];\n\tstruct lsm_static_call task_kill[2];\n\tstruct lsm_static_call task_prctl[2];\n\tstruct lsm_static_call task_to_inode[2];\n\tstruct lsm_static_call userns_create[2];\n\tstruct lsm_static_call ipc_permission[2];\n\tstruct lsm_static_call ipc_getlsmprop[2];\n\tstruct lsm_static_call msg_msg_alloc_security[2];\n\tstruct lsm_static_call msg_msg_free_security[2];\n\tstruct lsm_static_call msg_queue_alloc_security[2];\n\tstruct lsm_static_call msg_queue_free_security[2];\n\tstruct lsm_static_call msg_queue_associate[2];\n\tstruct lsm_static_call msg_queue_msgctl[2];\n\tstruct lsm_static_call msg_queue_msgsnd[2];\n\tstruct lsm_static_call msg_queue_msgrcv[2];\n\tstruct lsm_static_call shm_alloc_security[2];\n\tstruct lsm_static_call shm_free_security[2];\n\tstruct lsm_static_call shm_associate[2];\n\tstruct lsm_static_call shm_shmctl[2];\n\tstruct lsm_static_call shm_shmat[2];\n\tstruct lsm_static_call sem_alloc_security[2];\n\tstruct lsm_static_call sem_free_security[2];\n\tstruct lsm_static_call sem_associate[2];\n\tstruct lsm_static_call sem_semctl[2];\n\tstruct lsm_static_call sem_semop[2];\n\tstruct lsm_static_call netlink_send[2];\n\tstruct lsm_static_call d_instantiate[2];\n\tstruct lsm_static_call getselfattr[2];\n\tstruct lsm_static_call setselfattr[2];\n\tstruct lsm_static_call getprocattr[2];\n\tstruct lsm_static_call setprocattr[2];\n\tstruct lsm_static_call ismaclabel[2];\n\tstruct lsm_static_call secid_to_secctx[2];\n\tstruct lsm_static_call lsmprop_to_secctx[2];\n\tstruct lsm_static_call secctx_to_secid[2];\n\tstruct lsm_static_call release_secctx[2];\n\tstruct lsm_static_call inode_invalidate_secctx[2];\n\tstruct lsm_static_call inode_notifysecctx[2];\n\tstruct lsm_static_call inode_setsecctx[2];\n\tstruct lsm_static_call inode_getsecctx[2];\n\tstruct lsm_static_call unix_stream_connect[2];\n\tstruct lsm_static_call unix_may_send[2];\n\tstruct lsm_static_call socket_create[2];\n\tstruct lsm_static_call socket_post_create[2];\n\tstruct lsm_static_call socket_socketpair[2];\n\tstruct lsm_static_call socket_bind[2];\n\tstruct lsm_static_call socket_connect[2];\n\tstruct lsm_static_call socket_listen[2];\n\tstruct lsm_static_call socket_accept[2];\n\tstruct lsm_static_call socket_sendmsg[2];\n\tstruct lsm_static_call socket_recvmsg[2];\n\tstruct lsm_static_call socket_getsockname[2];\n\tstruct lsm_static_call socket_getpeername[2];\n\tstruct lsm_static_call socket_getsockopt[2];\n\tstruct lsm_static_call socket_setsockopt[2];\n\tstruct lsm_static_call socket_shutdown[2];\n\tstruct lsm_static_call socket_sock_rcv_skb[2];\n\tstruct lsm_static_call socket_getpeersec_stream[2];\n\tstruct lsm_static_call socket_getpeersec_dgram[2];\n\tstruct lsm_static_call sk_alloc_security[2];\n\tstruct lsm_static_call sk_free_security[2];\n\tstruct lsm_static_call sk_clone_security[2];\n\tstruct lsm_static_call sk_getsecid[2];\n\tstruct lsm_static_call sock_graft[2];\n\tstruct lsm_static_call inet_conn_request[2];\n\tstruct lsm_static_call inet_csk_clone[2];\n\tstruct lsm_static_call inet_conn_established[2];\n\tstruct lsm_static_call secmark_relabel_packet[2];\n\tstruct lsm_static_call secmark_refcount_inc[2];\n\tstruct lsm_static_call secmark_refcount_dec[2];\n\tstruct lsm_static_call req_classify_flow[2];\n\tstruct lsm_static_call tun_dev_alloc_security[2];\n\tstruct lsm_static_call tun_dev_create[2];\n\tstruct lsm_static_call tun_dev_attach_queue[2];\n\tstruct lsm_static_call tun_dev_attach[2];\n\tstruct lsm_static_call tun_dev_open[2];\n\tstruct lsm_static_call sctp_assoc_request[2];\n\tstruct lsm_static_call sctp_bind_connect[2];\n\tstruct lsm_static_call sctp_sk_clone[2];\n\tstruct lsm_static_call sctp_assoc_established[2];\n\tstruct lsm_static_call mptcp_add_subflow[2];\n\tstruct lsm_static_call key_alloc[2];\n\tstruct lsm_static_call key_permission[2];\n\tstruct lsm_static_call key_getsecurity[2];\n\tstruct lsm_static_call key_post_create_or_update[2];\n\tstruct lsm_static_call audit_rule_init[2];\n\tstruct lsm_static_call audit_rule_known[2];\n\tstruct lsm_static_call audit_rule_match[2];\n\tstruct lsm_static_call audit_rule_free[2];\n\tstruct lsm_static_call bpf[2];\n\tstruct lsm_static_call bpf_map[2];\n\tstruct lsm_static_call bpf_prog[2];\n\tstruct lsm_static_call bpf_map_create[2];\n\tstruct lsm_static_call bpf_map_free[2];\n\tstruct lsm_static_call bpf_prog_load[2];\n\tstruct lsm_static_call bpf_prog_free[2];\n\tstruct lsm_static_call bpf_token_create[2];\n\tstruct lsm_static_call bpf_token_free[2];\n\tstruct lsm_static_call bpf_token_cmd[2];\n\tstruct lsm_static_call bpf_token_capable[2];\n\tstruct lsm_static_call locked_down[2];\n\tstruct lsm_static_call perf_event_open[2];\n\tstruct lsm_static_call perf_event_alloc[2];\n\tstruct lsm_static_call perf_event_read[2];\n\tstruct lsm_static_call perf_event_write[2];\n\tstruct lsm_static_call uring_override_creds[2];\n\tstruct lsm_static_call uring_sqpoll[2];\n\tstruct lsm_static_call uring_cmd[2];\n\tstruct lsm_static_call uring_allowed[2];\n\tstruct lsm_static_call initramfs_populated[2];\n\tstruct lsm_static_call bdev_alloc_security[2];\n\tstruct lsm_static_call bdev_free_security[2];\n\tstruct lsm_static_call bdev_setintegrity[2];\n};\n\nstruct phy_param_t {\n\tu32 val;\n\tu32 addr;\n};\n\nstruct lt_phy_params {\n\tstruct phy_param_t pll_reg4;\n\tstruct phy_param_t pll_reg3;\n\tstruct phy_param_t pll_reg5;\n\tstruct phy_param_t pll_reg57;\n\tstruct phy_param_t lf;\n\tstruct phy_param_t tdc;\n\tstruct phy_param_t ssc;\n\tstruct phy_param_t bias2;\n\tstruct phy_param_t bias_trim;\n\tstruct phy_param_t dco_med;\n\tstruct phy_param_t dco_fine;\n\tstruct phy_param_t ssc_inj;\n\tstruct phy_param_t surv_bonus;\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwq_node {\n\tstruct llist_node node;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct mac80211_qos_map {\n\tstruct cfg80211_qos_map qos_map;\n\tstruct callback_head callback_head;\n};\n\nstruct machine_ops {\n\tvoid (*restart)(char *);\n\tvoid (*halt)(void);\n\tvoid (*power_off)(void);\n\tvoid (*shutdown)(void);\n\tvoid (*crash_shutdown)(struct pt_regs *);\n\tvoid (*emergency_restart)(void);\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct mafield {\n\tconst char *prefix;\n\tint field;\n};\n\nstruct map_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct efi_runtime_map_entry *, char *);\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct map_info___2 {\n\tstruct map_info___2 *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct map_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int page_size_mask;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[9];\n\tvoid *slot[10];\n\tlong unsigned int gap[10];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[33];\n\tunion {\n\t\tstruct maple_enode *slot[34];\n\t\tstruct {\n\t\t\tlong unsigned int padding[21];\n\t\t\tlong unsigned int gap[21];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[15];\n\tunion {\n\t\tvoid *slot[16];\n\t\tstruct {\n\t\t\tvoid *pad[15];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[31];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct mapped_device {\n\tstruct mutex suspend_lock;\n\tstruct mutex table_devices_lock;\n\tstruct list_head table_devices;\n\tvoid *map;\n\tlong unsigned int flags;\n\tstruct mutex type_lock;\n\tenum dm_queue_mode type;\n\tint numa_node_id;\n\tstruct request_queue *queue;\n\tatomic_t holders;\n\tatomic_t open_count;\n\tstruct dm_target *immutable_target;\n\tstruct target_type *immutable_target_type;\n\tchar name[16];\n\tstruct gendisk *disk;\n\tstruct dax_device *dax_dev;\n\twait_queue_head_t wait;\n\tlong unsigned int *pending_io;\n\tstruct hd_geometry geometry;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct work;\n\tspinlock_t deferred_lock;\n\tstruct bio_list deferred;\n\tstruct work_struct requeue_work;\n\tstruct dm_io *requeue_list;\n\tvoid *interface_ptr;\n\twait_queue_head_t eventq;\n\tatomic_t event_nr;\n\tatomic_t uevent_seq;\n\tstruct list_head uevent_list;\n\tspinlock_t uevent_lock;\n\tbool init_tio_pdu: 1;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct dm_stats stats;\n\tunsigned int internal_suspend_count;\n\tint swap_bios;\n\tstruct semaphore swap_bios_semaphore;\n\tstruct mutex swap_bios_lock;\n\tstruct dm_md_mempools *mempools;\n\tstruct dm_kobject_holder kobj_holder;\n\tstruct srcu_struct io_barrier;\n};\n\nstruct nf_conn;\n\nstruct masq_dev_work {\n\tstruct work_struct work;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tunion nf_inet_addr addr;\n\tint ifindex;\n\tint (*iter)(struct nf_conn *, void *);\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct math_emu_info {\n\tlong int ___orig_eip;\n\tstruct pt_regs *regs;\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker *c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tlong unsigned int e_flags;\n\tu64 e_value;\n};\n\nstruct mbox_controller;\n\nstruct mbox_client;\n\nstruct mbox_chan {\n\tstruct mbox_controller *mbox;\n\tunsigned int txdone_method;\n\tstruct mbox_client *cl;\n\tstruct completion tx_complete;\n\tvoid *active_req;\n\tunsigned int msg_count;\n\tunsigned int msg_free;\n\tvoid *msg_data[20];\n\tspinlock_t lock;\n\tvoid *con_priv;\n};\n\nstruct mbox_chan_ops {\n\tint (*send_data)(struct mbox_chan *, void *);\n\tint (*flush)(struct mbox_chan *, long unsigned int);\n\tint (*startup)(struct mbox_chan *);\n\tvoid (*shutdown)(struct mbox_chan *);\n\tbool (*last_tx_done)(struct mbox_chan *);\n\tbool (*peek_data)(struct mbox_chan *);\n};\n\nstruct mbox_client {\n\tstruct device *dev;\n\tbool tx_block;\n\tlong unsigned int tx_tout;\n\tbool knows_txdone;\n\tvoid (*rx_callback)(struct mbox_client *, void *);\n\tvoid (*tx_prepare)(struct mbox_client *, void *);\n\tvoid (*tx_done)(struct mbox_client *, void *, int);\n};\n\nstruct mbox_controller {\n\tstruct device *dev;\n\tconst struct mbox_chan_ops *ops;\n\tstruct mbox_chan *chans;\n\tint num_chans;\n\tbool txdone_irq;\n\tbool txdone_poll;\n\tunsigned int txpoll_period;\n\tstruct mbox_chan * (*fw_xlate)(struct mbox_controller *, const struct fwnode_reference_args *);\n\tstruct mbox_chan * (*of_xlate)(struct mbox_controller *, const struct of_phandle_args *);\n\tstruct hrtimer poll_hrt;\n\tspinlock_t poll_hrt_lock;\n\tstruct list_head node;\n};\n\nstruct mc146818_get_time_callback_param {\n\tstruct rtc_time *time;\n\tunsigned char ctrl;\n\tunsigned char century;\n};\n\nstruct mc_subled {\n\tunsigned int color_index;\n\tunsigned int brightness;\n\tunsigned int intensity;\n\tunsigned int channel;\n};\n\nstruct mca_config {\n\t__u64 lmce_disabled: 1;\n\t__u64 disabled: 1;\n\t__u64 ser: 1;\n\t__u64 recovery: 1;\n\t__u64 bios_cmci_threshold: 1;\n\t__u64 initialized: 1;\n\t__u64 __reserved: 58;\n\tbool dont_log_ce;\n\tbool cmci_disabled;\n\tbool ignore_ce;\n\tbool print_all;\n\tint monarch_timeout;\n\tint panic_timeout;\n\tu32 rip_msr;\n\ts8 bootlog;\n};\n\nstruct storm_bank {\n\tu64 history;\n\tu64 timestamp;\n\tbool in_storm_mode;\n\tbool poll_only;\n};\n\nstruct mca_storm_desc {\n\tstruct storm_bank banks[64];\n\tu8 stormy_bank_count;\n\tbool poll_mode;\n};\n\nstruct mce {\n\t__u64 status;\n\t__u64 misc;\n\t__u64 addr;\n\t__u64 mcgstatus;\n\t__u64 ip;\n\t__u64 tsc;\n\t__u64 time;\n\t__u8 cpuvendor;\n\t__u8 inject_flags;\n\t__u8 severity;\n\t__u8 pad;\n\t__u32 cpuid;\n\t__u8 cs;\n\t__u8 bank;\n\t__u8 cpu;\n\t__u8 finished;\n\t__u32 extcpu;\n\t__u32 socketid;\n\t__u32 apicid;\n\t__u64 mcgcap;\n\t__u64 synd;\n\t__u64 ipid;\n\t__u64 ppin;\n\t__u32 microcode;\n\t__u64 kflags;\n};\n\nstruct mce_amd_cpu_data {\n\tmce_banks_t thr_intr_banks;\n\tmce_banks_t dfr_intr_banks;\n\tu32 thr_intr_en: 1;\n\tu32 dfr_intr_en: 1;\n\tu32 __resv: 30;\n};\n\nstruct mce_bank {\n\tu64 ctl;\n\t__u64 init: 1;\n\t__u64 lsb_in_status: 1;\n\t__u64 __reserved_1: 62;\n};\n\nstruct mce_bank_dev {\n\tstruct device_attribute attr;\n\tchar attrname[16];\n\tu8 bank;\n};\n\nunion vendor_info {\n\tstruct {\n\t\tu64 synd1;\n\t\tu64 synd2;\n\t} amd;\n};\n\nstruct mce_hw_err {\n\tstruct mce m;\n\tunion vendor_info vendor;\n};\n\nstruct mce_evt_llist {\n\tstruct llist_node llnode;\n\tstruct mce_hw_err err;\n};\n\nstruct mce_vendor_flags {\n\t__u64 overflow_recov: 1;\n\t__u64 succor: 1;\n\t__u64 smca: 1;\n\t__u64 zen_ifu_quirk: 1;\n\t__u64 amd_threshold: 1;\n\t__u64 p5: 1;\n\t__u64 winchip: 1;\n\t__u64 snb_ifu_quirk: 1;\n\t__u64 skx_repmov_quirk: 1;\n\t__u64 __reserved_0: 55;\n};\n\nstruct mcs_group {\n\tu8 shift;\n\tu16 duration[14];\n};\n\nstruct mcs_group___2 {\n\tu16 flags;\n\tu8 streams;\n\tu8 shift;\n\tu8 bw;\n\tu16 duration[10];\n};\n\nstruct mcs_spinlock {\n\tstruct mcs_spinlock *next;\n\tint locked;\n\tint count;\n};\n\nstruct md_bitmap_stats {\n\tu64 events_cleared;\n\tint behind_writes;\n\tbool behind_wait;\n\tlong unsigned int missing_pages;\n\tlong unsigned int file_pages;\n\tlong unsigned int sync_size;\n\tlong unsigned int pages;\n\tstruct file *file;\n};\n\nstruct md_rdev;\n\nstruct md_cluster_operations {\n\tstruct md_submodule_head head;\n\tint (*join)(struct mddev *, int);\n\tint (*leave)(struct mddev *);\n\tint (*slot_number)(struct mddev *);\n\tint (*resync_info_update)(struct mddev *, sector_t, sector_t);\n\tint (*resync_start_notify)(struct mddev *);\n\tint (*resync_status_get)(struct mddev *);\n\tvoid (*resync_info_get)(struct mddev *, sector_t *, sector_t *);\n\tint (*metadata_update_start)(struct mddev *);\n\tint (*metadata_update_finish)(struct mddev *);\n\tvoid (*metadata_update_cancel)(struct mddev *);\n\tint (*resync_start)(struct mddev *);\n\tint (*resync_finish)(struct mddev *);\n\tint (*area_resyncing)(struct mddev *, int, sector_t, sector_t);\n\tint (*add_new_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*add_new_disk_cancel)(struct mddev *);\n\tint (*new_disk_ack)(struct mddev *, bool);\n\tint (*remove_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*load_bitmaps)(struct mddev *, int);\n\tint (*gather_bitmaps)(struct md_rdev *);\n\tint (*resize_bitmaps)(struct mddev *, sector_t, sector_t);\n\tint (*lock_all_bitmaps)(struct mddev *);\n\tvoid (*unlock_all_bitmaps)(struct mddev *);\n\tvoid (*update_size)(struct mddev *, sector_t);\n};\n\nstruct md_io_clone {\n\tstruct mddev *mddev;\n\tstruct bio *orig_bio;\n\tlong unsigned int start_time;\n\tsector_t offset;\n\tlong unsigned int sectors;\n\tenum stat_group rw;\n\tstruct bio bio_clone;\n};\n\nstruct md_personality {\n\tstruct md_submodule_head head;\n\tbool (*make_request)(struct mddev *, struct bio *);\n\tint (*run)(struct mddev *);\n\tint (*start)(struct mddev *);\n\tvoid (*free)(struct mddev *, void *);\n\tvoid (*status)(struct seq_file *, struct mddev *);\n\tvoid (*error_handler)(struct mddev *, struct md_rdev *);\n\tint (*hot_add_disk)(struct mddev *, struct md_rdev *);\n\tint (*hot_remove_disk)(struct mddev *, struct md_rdev *);\n\tint (*spare_active)(struct mddev *);\n\tsector_t (*sync_request)(struct mddev *, sector_t, sector_t, int *);\n\tint (*resize)(struct mddev *, sector_t);\n\tsector_t (*size)(struct mddev *, sector_t, int);\n\tint (*check_reshape)(struct mddev *);\n\tint (*start_reshape)(struct mddev *);\n\tvoid (*finish_reshape)(struct mddev *);\n\tvoid (*update_reshape_pos)(struct mddev *);\n\tvoid (*prepare_suspend)(struct mddev *);\n\tvoid (*quiesce)(struct mddev *, int);\n\tvoid * (*takeover)(struct mddev *);\n\tint (*change_consistency_policy)(struct mddev *, const char *);\n\tvoid (*bitmap_sector)(struct mddev *, sector_t *, long unsigned int *);\n};\n\nstruct serial_in_rdev;\n\nstruct md_rdev {\n\tstruct list_head same_set;\n\tsector_t sectors;\n\tstruct mddev *mddev;\n\tlong unsigned int last_events;\n\tstruct block_device *meta_bdev;\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct page *sb_page;\n\tstruct page *bb_page;\n\tint sb_loaded;\n\t__u64 sb_events;\n\tsector_t data_offset;\n\tsector_t new_data_offset;\n\tsector_t sb_start;\n\tint sb_size;\n\tint preferred_minor;\n\tstruct kobject kobj;\n\tlong unsigned int flags;\n\twait_queue_head_t blocked_wait;\n\tint desc_nr;\n\tint raid_disk;\n\tint new_raid_disk;\n\tint saved_raid_disk;\n\tunion {\n\t\tsector_t recovery_offset;\n\t\tsector_t journal_tail;\n\t};\n\tatomic_t nr_pending;\n\tatomic_t read_errors;\n\ttime64_t last_read_error;\n\tatomic_t corrected_errors;\n\tstruct serial_in_rdev *serial;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_unack_badblocks;\n\tstruct kernfs_node *sysfs_badblocks;\n\tstruct badblocks badblocks;\n\tstruct {\n\t\tshort int offset;\n\t\tunsigned int size;\n\t\tsector_t sector;\n\t} ppl;\n};\n\nstruct md_setup_args {\n\tint minor;\n\tint partitioned;\n\tint level;\n\tint chunk;\n\tchar *device_names;\n};\n\nstruct md_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mddev *, char *);\n\tssize_t (*store)(struct mddev *, const char *, size_t);\n};\n\nstruct md_thread {\n\tvoid (*run)(struct md_thread *);\n\tstruct mddev *mddev;\n\twait_queue_head_t wqueue;\n\tlong unsigned int flags;\n\tstruct task_struct *tsk;\n\tlong unsigned int timeout;\n\tvoid *private;\n};\n\nstruct md_cluster_info;\n\nstruct mddev {\n\tvoid *private;\n\tstruct md_personality *pers;\n\tdev_t unit;\n\tint md_minor;\n\tstruct list_head disks;\n\tlong unsigned int flags;\n\tlong unsigned int sb_flags;\n\tint suspended;\n\tstruct mutex suspend_mutex;\n\tstruct percpu_ref active_io;\n\tint ro;\n\tint sysfs_active;\n\tstruct gendisk *gendisk;\n\tstruct gendisk *dm_gendisk;\n\tstruct kobject kobj;\n\tint hold_active;\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tint persistent;\n\tint external;\n\tchar metadata_type[17];\n\tint chunk_sectors;\n\ttime64_t ctime;\n\ttime64_t utime;\n\tint level;\n\tint layout;\n\tchar clevel[16];\n\tint raid_disks;\n\tint max_disks;\n\tsector_t dev_sectors;\n\tsector_t array_sectors;\n\tint external_size;\n\tunsigned int logical_block_size;\n\t__u64 events;\n\tint can_decrease_events;\n\tchar uuid[16];\n\tsector_t reshape_position;\n\tint delta_disks;\n\tint new_level;\n\tint new_layout;\n\tint new_chunk_sectors;\n\tint reshape_backwards;\n\tstruct md_thread *thread;\n\tstruct md_thread *sync_thread;\n\tenum sync_action last_sync_action;\n\tsector_t curr_resync;\n\tsector_t curr_resync_completed;\n\tlong unsigned int resync_mark;\n\tsector_t resync_mark_cnt;\n\tsector_t curr_mark_cnt;\n\tsector_t resync_max_sectors;\n\tatomic64_t resync_mismatches;\n\tsector_t suspend_lo;\n\tsector_t suspend_hi;\n\tint sync_speed_min;\n\tint sync_speed_max;\n\tint sync_io_depth;\n\tint parallel_resync;\n\tint ok_start_degraded;\n\tlong unsigned int recovery;\n\tint in_sync;\n\tstruct mutex open_mutex;\n\tstruct mutex reconfig_mutex;\n\tatomic_t active;\n\tatomic_t openers;\n\tint changed;\n\tint degraded;\n\tlong unsigned int normal_io_events;\n\tatomic_t recovery_active;\n\twait_queue_head_t recovery_wait;\n\tsector_t resync_offset;\n\tsector_t resync_min;\n\tsector_t resync_max;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_action;\n\tstruct kernfs_node *sysfs_completed;\n\tstruct kernfs_node *sysfs_degraded;\n\tstruct kernfs_node *sysfs_level;\n\tstruct work_struct del_work;\n\tstruct work_struct sync_work;\n\tspinlock_t lock;\n\twait_queue_head_t sb_wait;\n\tatomic_t pending_writes;\n\tunsigned int safemode;\n\tunsigned int safemode_delay;\n\tstruct timer_list safemode_timer;\n\tstruct percpu_ref writes_pending;\n\tint sync_checkers;\n\tenum md_submodule_id bitmap_id;\n\tvoid *bitmap;\n\tstruct bitmap_operations *bitmap_ops;\n\tstruct {\n\t\tstruct file *file;\n\t\tloff_t offset;\n\t\tlong unsigned int space;\n\t\tloff_t default_offset;\n\t\tlong unsigned int default_space;\n\t\tstruct mutex mutex;\n\t\tlong unsigned int chunksize;\n\t\tlong unsigned int daemon_sleep;\n\t\tlong unsigned int max_write_behind;\n\t\tint external;\n\t\tint nodes;\n\t\tchar cluster_name[64];\n\t} bitmap_info;\n\tatomic_t max_corr_read_errors;\n\tstruct list_head all_mddevs;\n\tconst struct attribute_group *to_remove;\n\tstruct bio_set bio_set;\n\tstruct bio_set sync_set;\n\tstruct bio_set io_clone_set;\n\tstruct work_struct event_work;\n\tmempool_t *serial_info_pool;\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tstruct md_cluster_info *cluster_info;\n\tstruct md_cluster_operations *cluster_ops;\n\tunsigned int good_device_nr;\n\tunsigned int noio_flag;\n\tstruct list_head deleting;\n\tatomic_t sync_seq;\n};\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct mii_bus;\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n\tvoid (*shutdown)(struct mdio_device *);\n};\n\nstruct mdiobus_devres {\n\tstruct mii_bus *mii;\n};\n\nstruct mdp_device_descriptor_s {\n\t__u32 number;\n\t__u32 major;\n\t__u32 minor;\n\t__u32 raid_disk;\n\t__u32 state;\n\t__u32 reserved[27];\n};\n\ntypedef struct mdp_device_descriptor_s mdp_disk_t;\n\nstruct mdp_superblock_1 {\n\t__le32 magic;\n\t__le32 major_version;\n\t__le32 feature_map;\n\t__le32 pad0;\n\t__u8 set_uuid[16];\n\tchar set_name[32];\n\t__le64 ctime;\n\t__le32 level;\n\t__le32 layout;\n\t__le64 size;\n\t__le32 chunksize;\n\t__le32 raid_disks;\n\tunion {\n\t\t__le32 bitmap_offset;\n\t\tstruct {\n\t\t\t__le16 offset;\n\t\t\t__le16 size;\n\t\t} ppl;\n\t};\n\t__le32 new_level;\n\t__le64 reshape_position;\n\t__le32 delta_disks;\n\t__le32 new_layout;\n\t__le32 new_chunk;\n\t__le32 new_offset;\n\t__le64 data_offset;\n\t__le64 data_size;\n\t__le64 super_offset;\n\tunion {\n\t\t__le64 recovery_offset;\n\t\t__le64 journal_tail;\n\t};\n\t__le32 dev_number;\n\t__le32 cnt_corrected_read;\n\t__u8 device_uuid[16];\n\t__u8 devflags;\n\t__u8 bblog_shift;\n\t__le16 bblog_size;\n\t__le32 bblog_offset;\n\t__le64 utime;\n\t__le64 events;\n\t__le64 resync_offset;\n\t__le32 sb_csum;\n\t__le32 max_dev;\n\t__le32 logical_block_size;\n\t__u8 pad3[28];\n\t__le16 dev_roles[0];\n};\n\nstruct mdp_superblock_s {\n\t__u32 md_magic;\n\t__u32 major_version;\n\t__u32 minor_version;\n\t__u32 patch_version;\n\t__u32 gvalid_words;\n\t__u32 set_uuid0;\n\t__u32 ctime;\n\t__u32 level;\n\t__u32 size;\n\t__u32 nr_disks;\n\t__u32 raid_disks;\n\t__u32 md_minor;\n\t__u32 not_persistent;\n\t__u32 set_uuid1;\n\t__u32 set_uuid2;\n\t__u32 set_uuid3;\n\t__u32 gstate_creserved[16];\n\t__u32 utime;\n\t__u32 state;\n\t__u32 active_disks;\n\t__u32 working_disks;\n\t__u32 failed_disks;\n\t__u32 spare_disks;\n\t__u32 sb_csum;\n\t__u32 events_lo;\n\t__u32 events_hi;\n\t__u32 cp_events_lo;\n\t__u32 cp_events_hi;\n\t__u32 recovery_cp;\n\t__u64 reshape_position;\n\t__u32 new_level;\n\t__u32 delta_disks;\n\t__u32 new_layout;\n\t__u32 new_chunk;\n\t__u32 gstate_sreserved[14];\n\t__u32 layout;\n\t__u32 chunk_size;\n\t__u32 root_pv;\n\t__u32 root_block;\n\t__u32 pstate_reserved[60];\n\tmdp_disk_t disks[27];\n\t__u32 reserved[0];\n\tmdp_disk_t this_disk;\n};\n\ntypedef struct mdp_superblock_s mdp_super_t;\n\nstruct mdu_array_info_s {\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tunsigned int ctime;\n\tint level;\n\tint size;\n\tint nr_disks;\n\tint raid_disks;\n\tint md_minor;\n\tint not_persistent;\n\tunsigned int utime;\n\tint state;\n\tint active_disks;\n\tint working_disks;\n\tint failed_disks;\n\tint spare_disks;\n\tint layout;\n\tint chunk_size;\n};\n\ntypedef struct mdu_array_info_s mdu_array_info_t;\n\nstruct mdu_bitmap_file_s {\n\tchar pathname[4096];\n};\n\ntypedef struct mdu_bitmap_file_s mdu_bitmap_file_t;\n\nstruct mdu_disk_info_s {\n\tint number;\n\tint major;\n\tint minor;\n\tint raid_disk;\n\tint state;\n};\n\ntypedef struct mdu_disk_info_s mdu_disk_info_t;\n\nstruct mdu_version_s {\n\tint major;\n\tint minor;\n\tint patchlevel;\n};\n\ntypedef struct mdu_version_s mdu_version_t;\n\nstruct measure_breadcrumb {\n\tstruct i915_request rq;\n\tstruct intel_ring ring;\n\tu32 cs[2048];\n};\n\nstruct media_event_desc {\n\t__u8 media_event_code: 4;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 media_present: 1;\n\t__u8 reserved2: 6;\n\t__u8 start_slot;\n\t__u8 end_slot;\n};\n\nstruct mei_aux_device {\n\tstruct auxiliary_device aux_dev;\n\tint irq;\n\tstruct resource bar;\n\tstruct resource ext_op_mem;\n\tbool slow_firmware;\n};\n\nstruct mei_bus_message {\n\tu8 hbm_cmd;\n\tu8 data[0];\n};\n\nstruct mei_fw_status {\n\tint count;\n\tu32 status[6];\n};\n\nstruct mei_cfg {\n\tconst struct mei_fw_status fw_status;\n\tbool (*quirk_probe)(const struct pci_dev *);\n\tconst char *kind;\n\tsize_t dma_size[3];\n\tu32 fw_ver_supported: 1;\n\tu32 hw_trc_supported: 1;\n};\n\nstruct mei_dma_data {\n\tu8 buffer_id;\n\tvoid *vaddr;\n\tdma_addr_t daddr;\n\tsize_t size;\n};\n\nstruct mei_device;\n\nstruct mei_me_client;\n\nstruct mei_cl_device;\n\nstruct mei_cl {\n\tstruct list_head link;\n\tstruct mei_device *dev;\n\tenum file_state state;\n\twait_queue_head_t tx_wait;\n\twait_queue_head_t rx_wait;\n\twait_queue_head_t wait;\n\twait_queue_head_t ev_wait;\n\tstruct fasync_struct *ev_async;\n\tint status;\n\tstruct mei_me_client *me_cl;\n\tconst struct file *fp;\n\tu8 host_client_id;\n\tstruct list_head vtag_map;\n\tu8 tx_flow_ctrl_creds;\n\tu8 rx_flow_ctrl_creds;\n\tu8 timer_count;\n\tu8 notify_en;\n\tu8 notify_ev;\n\tu8 tx_cb_queued;\n\tenum mei_file_transaction_states writing_state;\n\tstruct list_head rd_pending;\n\tspinlock_t rd_completed_lock;\n\tstruct list_head rd_completed;\n\tstruct mei_dma_data dma;\n\tu8 dma_mapped;\n\tstruct mei_cl_device *cldev;\n};\n\nstruct mei_msg_data {\n\tsize_t size;\n\tunsigned char *data;\n};\n\nstruct mei_ext_hdr;\n\nstruct mei_cl_cb {\n\tstruct list_head list;\n\tstruct mei_cl *cl;\n\tenum mei_cb_file_ops fop_type;\n\tstruct mei_msg_data buf;\n\tsize_t buf_idx;\n\tu8 vtag;\n\tconst struct file *fp;\n\tint status;\n\tu32 internal: 1;\n\tu32 blocking: 1;\n\tstruct mei_ext_hdr *ext_hdr;\n};\n\ntypedef void (*mei_cldev_cb_t)(struct mei_cl_device *);\n\nstruct mei_cl_device {\n\tstruct list_head bus_list;\n\tstruct mei_device *bus;\n\tstruct device dev;\n\tstruct mei_me_client *me_cl;\n\tstruct mei_cl *cl;\n\tchar name[32];\n\tstruct work_struct rx_work;\n\tmei_cldev_cb_t rx_cb;\n\tstruct work_struct notif_work;\n\tmei_cldev_cb_t notif_cb;\n\tunsigned int do_match: 1;\n\tunsigned int is_added: 1;\n\tvoid *priv_data;\n};\n\nstruct mei_cl_device_id {\n\tchar name[32];\n\tuuid_le uuid;\n\t__u8 version;\n\tkernel_ulong_t driver_info;\n};\n\nstruct mei_cl_driver {\n\tstruct device_driver driver;\n\tconst char *name;\n\tconst struct mei_cl_device_id *id_table;\n\tint (*probe)(struct mei_cl_device *, const struct mei_cl_device_id *);\n\tvoid (*remove)(struct mei_cl_device *);\n};\n\nstruct mei_cl_vtag {\n\tstruct list_head list;\n\tconst struct file *fp;\n\tu8 vtag;\n\tu8 pending_read: 1;\n};\n\nstruct mei_client {\n\t__u32 max_msg_length;\n\t__u8 protocol_version;\n\t__u8 reserved[3];\n};\n\nstruct mei_connect_client_data {\n\tunion {\n\t\tuuid_le in_client_uuid;\n\t\tstruct mei_client out_client_properties;\n\t};\n};\n\nstruct mei_connect_client_vtag {\n\tuuid_le in_client_uuid;\n\t__u8 vtag;\n\t__u8 reserved[3];\n};\n\nstruct mei_connect_client_data_vtag {\n\tunion {\n\t\tstruct mei_connect_client_vtag connect;\n\t\tstruct mei_client out_client_properties;\n\t};\n};\n\nstruct mei_dev_timeouts {\n\tlong unsigned int hw_ready;\n\tint connect;\n\tlong unsigned int cl_connect;\n\tint client_init;\n\tlong unsigned int pgi;\n\tunsigned int d0i3;\n\tlong unsigned int hbm;\n\tlong unsigned int mkhi_recv;\n\tlong unsigned int link_reset_wait;\n};\n\nstruct mei_dma_dscr {\n\tvoid *vaddr;\n\tdma_addr_t daddr;\n\tsize_t size;\n};\n\nstruct mei_fw_version {\n\tu8 platform;\n\tu8 major;\n\tu16 minor;\n\tu16 buildno;\n\tu16 hotfix;\n};\n\nstruct mei_hw_ops;\n\nstruct mei_device {\n\tstruct device *parent;\n\tstruct device dev;\n\tstruct cdev *cdev;\n\tint minor;\n\tstruct list_head write_list;\n\tstruct list_head write_waiting_list;\n\tstruct list_head ctrl_wr_list;\n\tstruct list_head ctrl_rd_list;\n\tu8 tx_queue_limit;\n\tstruct list_head file_list;\n\tlong int open_handle_count;\n\tstruct mutex device_lock;\n\tstruct delayed_work timer_work;\n\tbool recvd_hw_ready;\n\twait_queue_head_t wait_hw_ready;\n\twait_queue_head_t wait_pg;\n\twait_queue_head_t wait_hbm_start;\n\tlong unsigned int reset_count;\n\tenum mei_dev_state dev_state;\n\twait_queue_head_t wait_dev_state;\n\tenum mei_hbm_state hbm_state;\n\tenum mei_dev_pxp_mode pxp_mode;\n\tu16 init_clients_timer;\n\tenum mei_pg_event pg_event;\n\tstruct dev_pm_domain pg_domain;\n\tunsigned char rd_msg_buf[512];\n\tu32 rd_msg_hdr[512];\n\tint rd_msg_hdr_count;\n\tbool hbuf_is_ready;\n\tstruct mei_dma_dscr dr_dscr[3];\n\tstruct hbm_version version;\n\tunsigned int hbm_f_pg_supported: 1;\n\tunsigned int hbm_f_dc_supported: 1;\n\tunsigned int hbm_f_dot_supported: 1;\n\tunsigned int hbm_f_ev_supported: 1;\n\tunsigned int hbm_f_fa_supported: 1;\n\tunsigned int hbm_f_ie_supported: 1;\n\tunsigned int hbm_f_os_supported: 1;\n\tunsigned int hbm_f_dr_supported: 1;\n\tunsigned int hbm_f_vt_supported: 1;\n\tunsigned int hbm_f_cap_supported: 1;\n\tunsigned int hbm_f_cd_supported: 1;\n\tunsigned int hbm_f_gsc_supported: 1;\n\tstruct mei_fw_version fw_ver[3];\n\tunsigned int fw_f_fw_ver_supported: 1;\n\tunsigned int fw_ver_received: 1;\n\tstruct rw_semaphore me_clients_rwsem;\n\tstruct list_head me_clients;\n\tlong unsigned int me_clients_map[4];\n\tlong unsigned int host_clients_map[4];\n\tbool allow_fixed_address;\n\tbool override_fixed_address;\n\tstruct mei_dev_timeouts timeouts;\n\tstruct work_struct reset_work;\n\tstruct work_struct bus_rescan_work;\n\tstruct list_head device_list;\n\tstruct mutex cl_bus_lock;\n\tconst char *kind;\n\tstruct dentry *dbgfs_dir;\n\tenum mei_dev_reset_to_pxp gsc_reset_to_pxp;\n\tconst struct mei_hw_ops *ops;\n\tchar hw[0];\n};\n\nstruct mei_ext_hdr {\n\tu8 type;\n\tu8 length;\n};\n\nstruct mei_ext_hdr_gsc_f2h {\n\tstruct mei_ext_hdr hdr;\n\tu8 client_id;\n\tu8 reserved;\n\tu32 fence_id;\n\tu32 written;\n};\n\nstruct mei_gsc_sgl {\n\tu32 low;\n\tu32 high;\n\tu32 length;\n};\n\nstruct mei_ext_hdr_gsc_h2f {\n\tstruct mei_ext_hdr hdr;\n\tu8 client_id;\n\tu8 addr_type;\n\tu32 fence_id;\n\tu8 input_address_count;\n\tu8 output_address_count;\n\tu8 reserved[2];\n\tstruct mei_gsc_sgl sgl[0];\n};\n\nstruct mei_ext_hdr_vtag {\n\tstruct mei_ext_hdr hdr;\n\tu8 vtag;\n\tu8 reserved;\n};\n\nstruct mei_ext_meta_hdr {\n\tu8 count;\n\tu8 size;\n\tu8 reserved[2];\n\tu8 hdrs[0];\n};\n\nstruct mei_fixup {\n\tconst uuid_le uuid;\n\tvoid (*hook)(struct mei_cl_device *);\n};\n\nstruct mei_hbm_cl_cmd {\n\tu8 hbm_cmd;\n\tu8 me_addr;\n\tu8 host_addr;\n\tu8 data;\n};\n\nstruct mei_hw_ops {\n\tbool (*host_is_ready)(struct mei_device *);\n\tbool (*hw_is_ready)(struct mei_device *);\n\tint (*hw_reset)(struct mei_device *, bool);\n\tint (*hw_start)(struct mei_device *);\n\tint (*hw_config)(struct mei_device *);\n\tint (*fw_status)(struct mei_device *, struct mei_fw_status *);\n\tint (*trc_status)(struct mei_device *, u32 *);\n\tenum mei_pg_state (*pg_state)(struct mei_device *);\n\tbool (*pg_in_transition)(struct mei_device *);\n\tbool (*pg_is_enabled)(struct mei_device *);\n\tvoid (*intr_clear)(struct mei_device *);\n\tvoid (*intr_enable)(struct mei_device *);\n\tvoid (*intr_disable)(struct mei_device *);\n\tvoid (*synchronize_irq)(struct mei_device *);\n\tint (*hbuf_free_slots)(struct mei_device *);\n\tbool (*hbuf_is_ready)(struct mei_device *);\n\tu32 (*hbuf_depth)(const struct mei_device *);\n\tint (*write)(struct mei_device *, const void *, size_t, const void *, size_t);\n\tint (*rdbuf_full_slots)(struct mei_device *);\n\tu32 (*read_hdr)(const struct mei_device *);\n\tint (*read)(struct mei_device *, unsigned char *, long unsigned int);\n};\n\nstruct mei_me_client {\n\tstruct list_head list;\n\tstruct kref refcnt;\n\tstruct mei_client_properties props;\n\tu8 client_id;\n\tu8 tx_flow_ctrl_creds;\n\tu8 connect_count;\n\tu8 bus_added;\n};\n\nstruct mei_me_hw {\n\tconst struct mei_cfg *cfg;\n\tvoid *mem_addr;\n\tint irq;\n\tenum mei_pg_state pg_state;\n\tbool d0i3_supported;\n\tu8 hbuf_depth;\n\tint (*read_fws)(const struct mei_device *, int, u32 *);\n\tstruct task_struct *polling_thread;\n\twait_queue_head_t wait_active;\n\tbool is_active;\n};\n\nstruct mei_msg_hdr {\n\tu32 me_addr: 8;\n\tu32 host_addr: 8;\n\tu32 length: 9;\n\tu32 reserved: 3;\n\tu32 extended: 1;\n\tu32 dma_ring: 1;\n\tu32 internal: 1;\n\tu32 msg_complete: 1;\n\tu32 extension[0];\n};\n\nstruct mei_nfc_cmd {\n\tu8 command;\n\tu8 status;\n\tu16 req_id;\n\tu32 reserved;\n\tu16 data_size;\n\tu8 sub_command;\n\tu8 data[0];\n} __attribute__((packed));\n\nstruct mei_nfc_if_version {\n\tu8 radio_version_sw[3];\n\tu8 reserved[3];\n\tu8 radio_version_hw[3];\n\tu8 i2c_addr;\n\tu8 fw_ivn;\n\tu8 vendor_id;\n\tu8 radio_type;\n};\n\nstruct mei_nfc_reply {\n\tu8 command;\n\tu8 status;\n\tu16 req_id;\n\tu32 reserved;\n\tu16 data_size;\n\tu8 sub_command;\n\tu8 reply_status;\n\tu8 data[0];\n};\n\nstruct mei_os_ver {\n\t__le16 build;\n\t__le16 reserved1;\n\tu8 os_type;\n\tu8 major;\n\tu8 minor;\n\tu8 reserved2;\n};\n\nstruct stats {\n\t__le32 tx_good_frames;\n\t__le32 tx_max_collisions;\n\t__le32 tx_late_collisions;\n\t__le32 tx_underruns;\n\t__le32 tx_lost_crs;\n\t__le32 tx_deferred;\n\t__le32 tx_single_collisions;\n\t__le32 tx_multiple_collisions;\n\t__le32 tx_total_collisions;\n\t__le32 rx_good_frames;\n\t__le32 rx_crc_errors;\n\t__le32 rx_alignment_errors;\n\t__le32 rx_resource_errors;\n\t__le32 rx_overrun_errors;\n\t__le32 rx_cdt_errors;\n\t__le32 rx_short_frame_errors;\n\t__le32 fc_xmt_pause;\n\t__le32 fc_rcv_pause;\n\t__le32 fc_rcv_unsupported;\n\t__le16 xmt_tco_frames;\n\t__le16 rcv_tco_frames;\n\t__le32 complete;\n};\n\nstruct mem {\n\tstruct {\n\t\tu32 signature;\n\t\tu32 result;\n\t} selftest;\n\tstruct stats stats;\n\tu8 dump_buf[596];\n};\n\nstruct pglist_data;\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n};\n\nstruct mem_entry {\n\tu32 offset;\n\tu32 len;\n};\n\nstruct mem_extent {\n\tstruct list_head hook;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mem_section_usage;\n\nstruct mem_section {\n\tlong unsigned int section_mem_map;\n\tstruct mem_section_usage *usage;\n};\n\nstruct mem_section_usage {\n\tstruct callback_head rcu;\n\tlong unsigned int subsection_map[1];\n\tlong unsigned int pageblock_flags[0];\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct mem_zone_bm_rtree {\n\tstruct list_head list;\n\tstruct list_head nodes;\n\tstruct list_head leaves;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tstruct rtree_node *rtree;\n\tint levels;\n\tunsigned int blocks;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n\tint nid;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct memmap_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct firmware_map_entry *, char *);\n};\n\nstruct memory_bitmap {\n\tstruct list_head zones;\n\tstruct linked_page *p_list;\n\tstruct bm_position cur;\n};\n\nstruct memory_dev_type {\n\tstruct list_head tier_sibling;\n\tstruct list_head list;\n\tint adistance;\n\tnodemask_t nodes;\n\tstruct kref kref;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct memory_tier {\n\tstruct list_head list;\n\tstruct list_head memory_types;\n\tint adistance_start;\n\tstruct device dev;\n\tnodemask_t lower_tier_mask;\n};\n\nstruct mempolicy {\n\tatomic_t refcnt;\n\tshort unsigned int mode;\n\tshort unsigned int flags;\n\tnodemask_t nodes;\n\tint home_node;\n\tunion {\n\t\tnodemask_t cpuset_mems_allowed;\n\t\tnodemask_t user_nodemask;\n\t} w;\n};\n\nstruct mempolicy_operations {\n\tint (*create)(struct mempolicy *, const nodemask_t *);\n\tvoid (*rebind)(struct mempolicy *, const nodemask_t *);\n};\n\nstruct memtype {\n\tu64 start;\n\tu64 end;\n\tu64 subtree_max_end;\n\tenum page_cache_mode type;\n\tstruct rb_node rb;\n};\n\nstruct menu_device {\n\tint needs_update;\n\tint tick_wakeup;\n\tu64 next_timer_ns;\n\tunsigned int bucket;\n\tunsigned int correction_factor[6];\n\tunsigned int intervals[8];\n\tint interval_ptr;\n};\n\nstruct merge_sched_data {\n\tint can_add_hw;\n\tenum event_type_t event_type;\n};\n\nstruct mesh_csa_settings {\n\tstruct callback_head callback_head;\n\tstruct cfg80211_csa_settings settings;\n};\n\nstruct mesh_path {\n\tu8 dst[6];\n\tu8 mpp[6];\n\tstruct rhash_head rhash;\n\tstruct hlist_node walk_list;\n\tstruct hlist_node gate_list;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct sta_info *next_hop;\n\tstruct timer_list timer;\n\tstruct sk_buff_head frame_queue;\n\tstruct callback_head rcu;\n\tu32 sn;\n\tu32 metric;\n\tu8 hop_count;\n\tlong unsigned int exp_time;\n\tu32 discovery_timeout;\n\tu8 discovery_retries;\n\tenum mesh_path_flags flags;\n\tspinlock_t state_lock;\n\tu8 rann_snd_addr[6];\n\tu32 rann_metric;\n\tlong unsigned int last_preq_to_root;\n\tlong unsigned int fast_tx_check;\n\tbool is_root;\n\tbool is_gate;\n\tu32 path_change_count;\n};\n\nstruct mesh_rmc {\n\tstruct hlist_head bucket[256];\n\tu32 idx_mask;\n};\n\nstruct mesh_setup {\n\tstruct cfg80211_chan_def chandef;\n\tconst u8 *mesh_id;\n\tu8 mesh_id_len;\n\tu8 sync_method;\n\tu8 path_sel_proto;\n\tu8 path_metric;\n\tu8 auth_id;\n\tconst u8 *ie;\n\tu8 ie_len;\n\tbool is_authenticated;\n\tbool is_secure;\n\tbool user_mpm;\n\tu8 dtim_period;\n\tu16 beacon_interval;\n\tint mcast_rate[6];\n\tu32 basic_rates;\n\tstruct cfg80211_bitrate_mask beacon_rate;\n\tbool userspace_handles_dfs;\n\tbool control_port_over_nl80211;\n};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mext_data {\n\tstruct inode *orig_inode;\n\tstruct inode *donor_inode;\n\tstruct ext4_map_blocks orig_map;\n\text4_lblk_t donor_lblk;\n};\n\nstruct mr_mfc {\n\tstruct rhlist_head mnode;\n\tshort unsigned int mfc_parent;\n\tint mfc_flags;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int expires;\n\t\t\tstruct sk_buff_head unresolved;\n\t\t} unres;\n\t\tstruct {\n\t\t\tlong unsigned int last_assert;\n\t\t\tint minvif;\n\t\t\tint maxvif;\n\t\t\tatomic_long_t bytes;\n\t\t\tatomic_long_t pkt;\n\t\t\tatomic_long_t wrong_if;\n\t\t\tlong unsigned int lastuse;\n\t\t\tunsigned char ttls[32];\n\t\t\trefcount_t refcount;\n\t\t} res;\n\t} mfc_un;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tvoid (*free)(struct callback_head *);\n};\n\nstruct mfc_cache_cmp_arg {\n\t__be32 mfc_mcastgrp;\n\t__be32 mfc_origin;\n};\n\nstruct mfc_cache {\n\tstruct mr_mfc _c;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 mfc_mcastgrp;\n\t\t\t__be32 mfc_origin;\n\t\t};\n\t\tstruct mfc_cache_cmp_arg cmparg;\n\t};\n};\n\nstruct mfc_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct mr_mfc *mfc;\n\tu32 tb_id;\n};\n\nstruct mfcctl {\n\tstruct in_addr mfcc_origin;\n\tstruct in_addr mfcc_mcastgrp;\n\tvifi_t mfcc_parent;\n\tunsigned char mfcc_ttls[32];\n\tunsigned int mfcc_pkt_cnt;\n\tunsigned int mfcc_byte_cnt;\n\tunsigned int mfcc_wrong_if;\n\tint mfcc_expire;\n};\n\nstruct mgmt_frame_regs {\n\tu32 global_stypes;\n\tu32 interface_stypes;\n\tu32 global_mcast_stypes;\n\tu32 interface_mcast_stypes;\n};\n\nstruct michael_mic_ctx {\n\tu32 l;\n\tu32 r;\n};\n\nstruct microcode_header_amd {\n\tu32 data_code;\n\tu32 patch_id;\n\tu16 mc_patch_data_id;\n\tu8 mc_patch_data_len;\n\tu8 init_flag;\n\tu32 mc_patch_data_checksum;\n\tu32 nb_dev_id;\n\tu32 sb_dev_id;\n\tu16 processor_rev_id;\n\tu8 nb_rev_id;\n\tu8 sb_rev_id;\n\tu8 bios_api_rev;\n\tu8 reserved1[3];\n\tu32 match_reg[8];\n};\n\nstruct microcode_amd {\n\tstruct microcode_header_amd hdr;\n\tunsigned int mpb[0];\n};\n\nstruct microcode_header_intel {\n\tunsigned int hdrver;\n\tunsigned int rev;\n\tunsigned int date;\n\tunsigned int sig;\n\tunsigned int cksum;\n\tunsigned int ldrver;\n\tunsigned int pf;\n\tunsigned int datasize;\n\tunsigned int totalsize;\n\tunsigned int metasize;\n\tunsigned int min_req_ver;\n\tunsigned int reserved;\n};\n\nstruct microcode_intel {\n\tstruct microcode_header_intel hdr;\n\tunsigned int bits[0];\n};\n\nstruct microcode_ops {\n\tenum ucode_state (*request_microcode_fw)(int, struct device *);\n\tvoid (*microcode_fini_cpu)(int);\n\tenum ucode_state (*apply_microcode)(int);\n\tvoid (*stage_microcode)(void);\n\tint (*collect_cpu_info)(int, struct cpu_signature *);\n\tvoid (*finalize_late_load)(int);\n\tunsigned int nmi_safe: 1;\n\tunsigned int use_nmi: 1;\n\tunsigned int use_staging: 1;\n};\n\nstruct mid8250_board;\n\nstruct mid8250 {\n\tint line;\n\tint dma_index;\n\tstruct pci_dev *dma_dev;\n\tstruct uart_8250_dma dma;\n\tstruct mid8250_board *board;\n\tstruct hsu_dma_chip dma_chip;\n};\n\nstruct mid8250_board {\n\tlong unsigned int freq;\n\tunsigned int base_baud;\n\tunsigned int bar;\n\tint (*setup)(struct mid8250 *, struct uart_port *);\n\tvoid (*exit)(struct mid8250 *);\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_mpol {\n\tstruct mempolicy *pol;\n\tlong unsigned int ilx;\n};\n\nstruct migration_swap_arg {\n\tstruct task_struct *src_task;\n\tstruct task_struct *dst_task;\n\tint src_cpu;\n\tint dst_cpu;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n};\n\nstruct mii_if_info {\n\tint phy_id;\n\tint advertising;\n\tint phy_id_mask;\n\tint reg_num_mask;\n\tunsigned int full_duplex: 1;\n\tunsigned int force_media: 1;\n\tunsigned int supports_gmii: 1;\n\tstruct net_device *dev;\n\tint (*mdio_read)(struct net_device *, int, int);\n\tvoid (*mdio_write)(struct net_device *, int, int, int);\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct min_heap_callbacks {\n\tbool (*less)(const void *, const void *, void *);\n\tvoid (*swp)(void *, void *, void *);\n};\n\nstruct min_heap_char {\n\tsize_t nr;\n\tsize_t size;\n\tchar *data;\n\tchar preallocated[0];\n};\n\ntypedef struct min_heap_char min_heap_char;\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minimode {\n\tshort int w;\n\tshort int h;\n\tshort int r;\n\tshort int rb;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct minstrel_sample_category {\n\tu8 sample_group;\n\tu16 sample_rates[5];\n\tu16 cur_sample_rates[5];\n};\n\nstruct minstrel_rate_stats {\n\tu16 attempts;\n\tu16 last_attempts;\n\tu16 success;\n\tu16 last_success;\n\tu32 att_hist;\n\tu32 succ_hist;\n\tu16 prob_avg;\n\tu16 prob_avg_1;\n\tu8 retry_count;\n\tu8 retry_count_rtscts;\n\tbool retry_updated;\n};\n\nstruct minstrel_mcs_group_data {\n\tu8 index;\n\tu8 column;\n\tu16 max_group_tp_rate[4];\n\tu16 max_group_prob_rate;\n\tstruct minstrel_rate_stats rates[10];\n};\n\nstruct minstrel_ht_sta {\n\tstruct ieee80211_sta *sta;\n\tunsigned int ampdu_len;\n\tunsigned int ampdu_packets;\n\tunsigned int avg_ampdu_len;\n\tu16 max_tp_rate[4];\n\tu16 max_prob_rate;\n\tlong unsigned int last_stats_update;\n\tunsigned int overhead;\n\tunsigned int overhead_rtscts;\n\tunsigned int overhead_legacy;\n\tunsigned int overhead_legacy_rtscts;\n\tunsigned int total_packets;\n\tunsigned int sample_packets;\n\tu32 tx_flags;\n\tbool use_short_preamble;\n\tu8 band;\n\tu8 sample_seq;\n\tu16 sample_rate;\n\tlong unsigned int sample_time;\n\tstruct minstrel_sample_category sample[3];\n\tu16 supported[42];\n\tstruct minstrel_mcs_group_data groups[42];\n};\n\nstruct minstrel_priv {\n\tstruct ieee80211_hw *hw;\n\tunsigned int cw_min;\n\tunsigned int cw_max;\n\tunsigned int max_retry;\n\tunsigned int segment_size;\n\tunsigned int update_interval;\n\tu8 cck_rates[4];\n\tu8 ofdm_rates[48];\n};\n\nstruct mipi_dsi_device {\n\tstruct mipi_dsi_host *host;\n\tstruct device dev;\n\tbool attached;\n\tchar name[20];\n\tunsigned int channel;\n\tunsigned int lanes;\n\tenum mipi_dsi_pixel_format format;\n\tlong unsigned int mode_flags;\n\tlong unsigned int hs_rate;\n\tlong unsigned int lp_rate;\n\tstruct drm_dsc_config *dsc;\n};\n\nstruct mipi_dsi_device_info {\n\tchar type[20];\n\tu32 channel;\n\tstruct device_node *node;\n};\n\nstruct mipi_dsi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct mipi_dsi_device *);\n\tvoid (*remove)(struct mipi_dsi_device *);\n\tvoid (*shutdown)(struct mipi_dsi_device *);\n};\n\nstruct mipi_dsi_msg;\n\nstruct mipi_dsi_host_ops {\n\tint (*attach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tint (*detach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tssize_t (*transfer)(struct mipi_dsi_host *, const struct mipi_dsi_msg *);\n};\n\nstruct mipi_dsi_msg {\n\tu8 channel;\n\tu8 type;\n\tu16 flags;\n\tsize_t tx_len;\n\tconst void *tx_buf;\n\tsize_t rx_len;\n\tvoid *rx_buf;\n};\n\nstruct mipi_dsi_multi_context {\n\tstruct mipi_dsi_device *dsi;\n\tint accum_err;\n};\n\nstruct mipi_dsi_packet {\n\tsize_t size;\n\tu8 header[4];\n\tsize_t payload_length;\n\tconst u8 *payload;\n};\n\nstruct mirror_set;\n\nstruct mirror {\n\tstruct mirror_set *ms;\n\tatomic_t error_count;\n\tlong unsigned int error_type;\n\tstruct dm_dev *dev;\n\tsector_t offset;\n};\n\nstruct mirror_set {\n\tstruct dm_target *ti;\n\tstruct list_head list;\n\tuint64_t features;\n\tspinlock_t lock;\n\tstruct bio_list reads;\n\tstruct bio_list writes;\n\tstruct bio_list failures;\n\tstruct bio_list holds;\n\tstruct dm_region_hash *rh;\n\tstruct dm_kcopyd_client *kcopyd_client;\n\tstruct dm_io_client *io_client;\n\tregion_t nr_regions;\n\tint in_sync;\n\tint log_failure;\n\tint leg_failure;\n\tatomic_t suspend;\n\tatomic_t default_mirror;\n\tstruct workqueue_struct *kmirrord_wq;\n\tstruct work_struct kmirrord_work;\n\tstruct timer_list timer;\n\tlong unsigned int timer_pending;\n\tstruct work_struct trigger_event;\n\tunsigned int nr_mirrors;\n\tstruct mirror mirror[0];\n};\n\nstruct misc_res {\n\tu64 max;\n\tatomic64_t watermark;\n\tatomic64_t usage;\n\tatomic64_t events;\n\tatomic64_t events_local;\n};\n\nstruct misc_cg {\n\tstruct cgroup_subsys_state css;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct misc_res res[0];\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct mkhi_fw_ver_block {\n\tu16 minor;\n\tu8 major;\n\tu8 platform;\n\tu16 buildno;\n\tu16 hotfix;\n};\n\nstruct mkhi_fw_ver {\n\tstruct mkhi_fw_ver_block ver[3];\n};\n\nstruct mkhi_rule_id {\n\t__le16 rule_type;\n\tu8 feature_id;\n\tu8 reserved;\n};\n\nstruct mkhi_fwcaps {\n\tstruct mkhi_rule_id id;\n\tu8 len;\n\tu8 data[0];\n} __attribute__((packed));\n\nstruct mkhi_msg_hdr {\n\tu8 group_id;\n\tu8 command;\n\tu8 reserved;\n\tu8 result;\n};\n\nstruct mkhi_gfx_mem_ready {\n\tstruct mkhi_msg_hdr hdr;\n\tu32 flags;\n};\n\nstruct mkhi_msg {\n\tstruct mkhi_msg_hdr hdr;\n\tu8 data[0];\n};\n\nstruct ml_effect_state {\n\tstruct ff_effect *effect;\n\tlong unsigned int flags;\n\tint count;\n\tlong unsigned int play_at;\n\tlong unsigned int stop_at;\n\tlong unsigned int adj_at;\n};\n\nstruct ml_device {\n\tvoid *private;\n\tstruct ml_effect_state states[16];\n\tint gain;\n\tstruct timer_list timer;\n\tstruct input_dev *dev;\n\tint (*play_effect)(struct input_dev *, void *, struct ff_effect *);\n};\n\nstruct mld2_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\tstruct in6_addr grec_mca;\n\tstruct in6_addr grec_src[0];\n};\n\nstruct mld2_query {\n\tstruct icmp6hdr mld2q_hdr;\n\tstruct in6_addr mld2q_mca;\n\t__u8 mld2q_qrv: 3;\n\t__u8 mld2q_suppress: 1;\n\t__u8 mld2q_resv2: 4;\n\t__u8 mld2q_qqic;\n\t__be16 mld2q_nsrcs;\n\tstruct in6_addr mld2q_srcs[0];\n};\n\nstruct mld2_report {\n\tstruct icmp6hdr mld2r_hdr;\n\tstruct mld2_grec mld2r_grec[0];\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tstruct ethtool_mm_stats stats;\n};\n\ntypedef struct mm_struct *class_mmap_read_lock_t;\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n\tstruct hlist_head head_tramps;\n};\n\nstruct mmu_notifier_subscriptions;\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int mmap_compat_base;\n\t\tlong unsigned int mmap_compat_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct rcuwait vma_writer_wait;\n\t\tseqcount_t mm_lock_seq;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[52];\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tstruct mmu_notifier_subscriptions *notifier_subscriptions;\n\t\tlong unsigned int numa_next_scan;\n\t\tlong unsigned int numa_scan_offset;\n\t\tint numa_scan_seq;\n\t\tatomic_t tlb_flush_pending;\n\t\tatomic_t tlb_flush_batched;\n\t\tstruct uprobes_state uprobes_state;\n\t\tatomic_long_t hugetlb_usage;\n\t\tstruct work_struct async_put_work;\n\t\tstruct iommu_mm_data *iommu_mm;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct mmap_arg_struct32 {\n\tunsigned int addr;\n\tunsigned int len;\n\tunsigned int prot;\n\tunsigned int flags;\n\tunsigned int fd;\n\tunsigned int offset;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mminit_pfnnid_cache {\n\tlong unsigned int last_start;\n\tlong unsigned int last_end;\n\tint last_nid;\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct encoded_page;\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct encoded_page *encoded_pages[0];\n};\n\nstruct mmu_table_batch;\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tstruct mmu_table_batch *batch;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n};\n\nstruct mmu_notifier_range;\n\nstruct mmu_interval_notifier_ops {\n\tbool (*invalidate)(struct mmu_interval_notifier *, const struct mmu_notifier_range *, long unsigned int);\n};\n\nstruct mmu_notifier_ops {\n\tvoid (*release)(struct mmu_notifier *, struct mm_struct *);\n\tint (*clear_flush_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*clear_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*test_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int);\n\tint (*invalidate_range_start)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range_end)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*arch_invalidate_secondary_tlbs)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tstruct mmu_notifier * (*alloc_notifier)(struct mm_struct *);\n\tvoid (*free_notifier)(struct mmu_notifier *);\n};\n\nstruct mmu_notifier_range {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int flags;\n\tenum mmu_notifier_event event;\n\tvoid *owner;\n};\n\nstruct mmu_notifier_subscriptions {\n\tstruct hlist_head list;\n\tbool has_itree;\n\tspinlock_t lock;\n\tlong unsigned int invalidate_seq;\n\tlong unsigned int active_invalidate_ranges;\n\tstruct rb_root_cached itree;\n\twait_queue_head_t wq;\n\tstruct hlist_head deferred_list;\n};\n\nstruct mmu_table_batch {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tvoid *tables[0];\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 64;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct orc_entry;\n\nstruct mod_arch_specific {\n\tunsigned int num_orcs;\n\tint *orc_unwind_ip;\n\tstruct orc_entry *orc_unwind;\n\tstruct its_array its_pages;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf64_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct mode_page_header {\n\t__be16 mode_data_length;\n\t__u8 medium_type;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 reserved3;\n\t__be16 desc_length;\n};\n\nstruct modesel_head {\n\t__u8 reserved1;\n\t__u8 medium;\n\t__u8 reserved2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_of_blocks_hi;\n\t__u8 number_of_blocks_med;\n\t__u8 number_of_blocks_lo;\n\t__u8 reserved3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n\tstruct mod_tree_node mtn;\n};\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_event_call;\n\nstruct trace_eval_map;\n\nstruct static_call_site;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[56];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tvoid *kprobes_text_start;\n\tunsigned int kprobes_text_size;\n\tlong unsigned int *kprobe_blacklist;\n\tunsigned int num_kprobe_blacklist;\n\tint num_static_call_sites;\n\tstruct static_call_site *static_call_sites;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n\tlong: 64;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_string {\n\tstruct list_head next;\n\tstruct module *module;\n\tchar *str;\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct mon_bin_hdr;\n\nstruct mon_bin_get {\n\tstruct mon_bin_hdr *hdr;\n\tvoid *data;\n\tsize_t alloc;\n};\n\nstruct mon_bin_get32 {\n\tu32 hdr32;\n\tu32 data32;\n\tu32 alloc32;\n};\n\nstruct mon_bin_hdr {\n\tu64 id;\n\tunsigned char type;\n\tunsigned char xfer_type;\n\tunsigned char epnum;\n\tunsigned char devnum;\n\tshort unsigned int busnum;\n\tchar flag_setup;\n\tchar flag_data;\n\ts64 ts_sec;\n\ts32 ts_usec;\n\tint status;\n\tunsigned int len_urb;\n\tunsigned int len_cap;\n\tunion {\n\t\tunsigned char setup[8];\n\t\tstruct iso_rec iso;\n\t} s;\n\tint interval;\n\tint start_frame;\n\tunsigned int xfer_flags;\n\tunsigned int ndesc;\n};\n\nstruct mon_bin_isodesc {\n\tint iso_status;\n\tunsigned int iso_off;\n\tunsigned int iso_len;\n\tu32 _pad;\n};\n\nstruct mon_bin_mfetch {\n\tu32 *offvec;\n\tu32 nfetch;\n\tu32 nflush;\n};\n\nstruct mon_bin_mfetch32 {\n\tu32 offvec32;\n\tu32 nfetch32;\n\tu32 nflush32;\n};\n\nstruct mon_bin_stats {\n\tu32 queued;\n\tu32 dropped;\n};\n\nstruct usb_bus;\n\nstruct mon_bus {\n\tstruct list_head bus_link;\n\tspinlock_t lock;\n\tstruct usb_bus *u_bus;\n\tint text_inited;\n\tint bin_inited;\n\tstruct dentry *dent_s;\n\tstruct dentry *dent_t;\n\tstruct dentry *dent_u;\n\tstruct device *classdev;\n\tint nreaders;\n\tstruct list_head r_list;\n\tstruct kref ref;\n\tunsigned int cnt_events;\n\tunsigned int cnt_text_lost;\n};\n\nstruct mon_iso_desc {\n\tint status;\n\tunsigned int offset;\n\tunsigned int length;\n};\n\nstruct mon_event_text {\n\tstruct list_head e_link;\n\tint type;\n\tlong unsigned int id;\n\tunsigned int tstamp;\n\tint busnum;\n\tchar devnum;\n\tchar epnum;\n\tchar is_in;\n\tchar xfertype;\n\tint length;\n\tint status;\n\tint interval;\n\tint start_frame;\n\tint error_count;\n\tchar setup_flag;\n\tchar data_flag;\n\tint numdesc;\n\tstruct mon_iso_desc isodesc[5];\n\tunsigned char setup[8];\n\tunsigned char data[32];\n};\n\nstruct mon_pgmap {\n\tstruct page *pg;\n\tunsigned char *ptr;\n};\n\nstruct mon_reader {\n\tstruct list_head r_link;\n\tstruct mon_bus *m_bus;\n\tvoid *r_data;\n\tvoid (*rnf_submit)(void *, struct urb *);\n\tvoid (*rnf_error)(void *, struct urb *, int);\n\tvoid (*rnf_complete)(void *, struct urb *, int);\n};\n\nstruct mon_reader_bin {\n\tspinlock_t b_lock;\n\tunsigned int b_size;\n\tunsigned int b_cnt;\n\tunsigned int b_in;\n\tunsigned int b_out;\n\tunsigned int b_read;\n\tstruct mon_pgmap *b_vec;\n\twait_queue_head_t b_wait;\n\tstruct mutex fetch_lock;\n\tint mmap_active;\n\tstruct mon_reader r;\n\tunsigned int cnt_lost;\n};\n\nstruct mon_reader_text {\n\tstruct kmem_cache *e_slab;\n\tint nevents;\n\tstruct list_head e_list;\n\tstruct mon_reader r;\n\twait_queue_head_t wait;\n\tint printf_size;\n\tsize_t printf_offset;\n\tsize_t printf_togo;\n\tchar *printf_buf;\n\tstruct mutex printf_lock;\n\tchar slab_name[30];\n};\n\nstruct mon_text_ptr {\n\tint cnt;\n\tint limit;\n\tchar *pbuf;\n};\n\nstruct motion_output_report_02 {\n\tu8 type;\n\tu8 zero;\n\tu8 r;\n\tu8 g;\n\tu8 b;\n\tu8 zero2;\n\tu8 rumble;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct mountres {\n\tint errno;\n\tstruct nfs_fh *fh;\n\tunsigned int *auth_count;\n\trpc_authflavor_t *auth_flavors;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct mp_chip_data {\n\tstruct list_head irq_2_pin;\n\tstruct IO_APIC_route_entry entry;\n\tbool is_level;\n\tbool active_low;\n\tbool isa_irq;\n\tu32 count;\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tunsigned int can_map: 1;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tloff_t end_pos;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n\tunsigned int journalled_more_data: 1;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpath_info {\n\tu32 filled;\n\tu32 frame_qlen;\n\tu32 sn;\n\tu32 metric;\n\tu32 exptime;\n\tu32 discovery_timeout;\n\tu8 discovery_retries;\n\tu8 flags;\n\tu8 hop_count;\n\tu32 path_change_count;\n\tint generation;\n};\n\nstruct mpc_bus {\n\tunsigned char type;\n\tunsigned char busid;\n\tunsigned char bustype[6];\n};\n\nstruct mpc_cpu {\n\tunsigned char type;\n\tunsigned char apicid;\n\tunsigned char apicver;\n\tunsigned char cpuflag;\n\tunsigned int cpufeature;\n\tunsigned int featureflag;\n\tunsigned int reserved[2];\n};\n\nstruct mpc_intsrc {\n\tunsigned char type;\n\tunsigned char irqtype;\n\tshort unsigned int irqflag;\n\tunsigned char srcbus;\n\tunsigned char srcbusirq;\n\tunsigned char dstapic;\n\tunsigned char dstirq;\n};\n\nstruct mpc_lintsrc {\n\tunsigned char type;\n\tunsigned char irqtype;\n\tshort unsigned int irqflag;\n\tunsigned char srcbusid;\n\tunsigned char srcbusirq;\n\tunsigned char destapic;\n\tunsigned char destapiclint;\n};\n\nstruct mpc_table {\n\tchar signature[4];\n\tshort unsigned int length;\n\tchar spec;\n\tchar checksum;\n\tchar oem[8];\n\tchar productid[12];\n\tunsigned int oemptr;\n\tshort unsigned int oemsize;\n\tshort unsigned int oemcount;\n\tunsigned int lapic;\n\tunsigned int reserved;\n};\n\nstruct mpf_intel {\n\tchar signature[4];\n\tunsigned int physptr;\n\tunsigned char length;\n\tunsigned char specification;\n\tunsigned char checksum;\n\tunsigned char feature1;\n\tunsigned char feature2;\n\tunsigned char feature3;\n\tunsigned char feature4;\n\tunsigned char feature5;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mptcp_out_options {};\n\nstruct mptcp_sock {};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct mqueue_fs_context {\n\tstruct ipc_namespace *ipc_ns;\n\tbool newns;\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[12];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct posix_msg_tree_node;\n\nstruct mqueue_inode_info {\n\tspinlock_t lock;\n\tstruct inode vfs_inode;\n\twait_queue_head_t wait_q;\n\tstruct rb_root msg_tree;\n\tstruct rb_node *msg_tree_rightmost;\n\tstruct posix_msg_tree_node *node_cache;\n\tstruct mq_attr attr;\n\tstruct sigevent notify;\n\tstruct pid *notify_owner;\n\tu32 notify_self_exec_id;\n\tstruct user_namespace *notify_user_ns;\n\tstruct ucounts *ucounts;\n\tstruct sock *notify_sock;\n\tstruct sk_buff *notify_cookie;\n\tstruct ext_wait_queue e_wait_q[2];\n\tlong unsigned int qsize;\n};\n\nstruct mr_table;\n\nstruct mr_mfc_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tstruct list_head *cache;\n\tspinlock_t *lock;\n};\n\nstruct mr_table_ops {\n\tconst struct rhashtable_params *rht_params;\n\tvoid *cmparg_any;\n};\n\nstruct vif_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tlong unsigned int bytes_in;\n\tlong unsigned int bytes_out;\n\tlong unsigned int pkt_in;\n\tlong unsigned int pkt_out;\n\tlong unsigned int rate_limit;\n\tunsigned char threshold;\n\tshort unsigned int flags;\n\tint link;\n\tstruct netdev_phys_item_id dev_parent_id;\n\t__be32 local;\n\t__be32 remote;\n};\n\nstruct mr_table {\n\tstruct list_head list;\n\tpossible_net_t net;\n\tstruct mr_table_ops ops;\n\tu32 id;\n\tstruct sock *mroute_sk;\n\tstruct timer_list ipmr_expire_timer;\n\tstruct list_head mfc_unres_queue;\n\tstruct vif_device vif_table[32];\n\tstruct rhltable mfc_hash;\n\tstruct list_head mfc_cache_list;\n\tint maxvif;\n\tatomic_t cache_resolve_queue_len;\n\tbool mroute_do_assert;\n\tbool mroute_do_pim;\n\tbool mroute_do_wrvifwhole;\n\tint mroute_reg_vif_num;\n};\n\nstruct mr_vif_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tint ct;\n};\n\nstruct mrrm_mem_range_entry {\n\tu64 base;\n\tu64 length;\n\tint node;\n\tu8 local_region_id;\n\tu8 remote_region_id;\n};\n\nstruct mrw_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u8 write: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n\t__u8 reserved4;\n\t__u8 reserved5;\n};\n\nstruct ms_data {\n\tlong unsigned int quirks;\n\tstruct hid_device *hdev;\n\tstruct work_struct ff_worker;\n\t__u8 strong;\n\t__u8 weak;\n\tvoid *output_report_dmabuf;\n};\n\nstruct ms_hyperv_info {\n\tu32 features;\n\tu32 priv_high;\n\tu32 ext_features;\n\tu32 misc_features;\n\tu32 hints;\n\tu32 nested_features;\n\tu32 max_vp_index;\n\tu32 max_lp_index;\n\tu8 vtl;\n\tunion {\n\t\tu32 isolation_config_a;\n\t\tstruct {\n\t\t\tu32 paravisor_present: 1;\n\t\t\tu32 reserved_a1: 31;\n\t\t};\n\t};\n\tunion {\n\t\tu32 isolation_config_b;\n\t\tstruct {\n\t\t\tu32 cvm_type: 4;\n\t\t\tu32 reserved_b1: 1;\n\t\t\tu32 shared_gpa_boundary_active: 1;\n\t\t\tu32 shared_gpa_boundary_bits: 6;\n\t\t\tu32 reserved_b2: 20;\n\t\t};\n\t};\n\tu64 shared_gpa_boundary;\n\tbool msi_ext_dest_id;\n\tbool confidential_vmbus_available;\n};\n\nstruct msdos_dir_entry {\n\t__u8 name[11];\n\t__u8 attr;\n\t__u8 lcase;\n\t__u8 ctime_cs;\n\t__le16 ctime;\n\t__le16 cdate;\n\t__le16 adate;\n\t__le16 starthi;\n\t__le16 time;\n\t__le16 date;\n\t__le16 start;\n\t__le32 size;\n};\n\nstruct msdos_dir_slot {\n\t__u8 id;\n\t__u8 name0_4[10];\n\t__u8 attr;\n\t__u8 reserved;\n\t__u8 alias_checksum;\n\t__u8 name5_10[12];\n\t__le16 start;\n\t__u8 name11_12[4];\n};\n\nstruct msdos_inode_info {\n\tspinlock_t cache_lru_lock;\n\tstruct list_head cache_lru;\n\tint nr_caches;\n\tunsigned int cache_valid_id;\n\tloff_t mmu_private;\n\tint i_start;\n\tint i_logstart;\n\tint i_attrs;\n\tloff_t i_pos;\n\tstruct hlist_node i_fat_hash;\n\tstruct hlist_node i_dir_hash;\n\tstruct rw_semaphore truncate_lock;\n\tstruct timespec64 i_crtime;\n\tstruct inode vfs_inode;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct msdos_sb_info {\n\tshort unsigned int sec_per_clus;\n\tshort unsigned int cluster_bits;\n\tunsigned int cluster_size;\n\tunsigned char fats;\n\tunsigned char fat_bits;\n\tshort unsigned int fat_start;\n\tlong unsigned int fat_length;\n\tlong unsigned int dir_start;\n\tshort unsigned int dir_entries;\n\tlong unsigned int data_start;\n\tlong unsigned int max_cluster;\n\tlong unsigned int root_cluster;\n\tlong unsigned int fsinfo_sector;\n\tstruct mutex fat_lock;\n\tstruct mutex nfs_build_inode_lock;\n\tstruct mutex s_lock;\n\tunsigned int prev_free;\n\tunsigned int free_clusters;\n\tunsigned int free_clus_valid;\n\tstruct fat_mount_options options;\n\tstruct nls_table *nls_disk;\n\tstruct nls_table *nls_io;\n\tconst void *dir_ops;\n\tint dir_per_block;\n\tint dir_per_block_bits;\n\tunsigned int vol_id;\n\tint fatent_shift;\n\tconst struct fatent_operations *fatent_ops;\n\tstruct inode *fat_inode;\n\tstruct inode *fsinfo_inode;\n\tstruct ratelimit_state ratelimit;\n\tspinlock_t inode_hash_lock;\n\tstruct hlist_head inode_hashtable[256];\n\tspinlock_t dir_hash_lock;\n\tstruct hlist_head dir_hashtable[256];\n\tunsigned int dirty;\n\tstruct callback_head rcu;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_security_struct {\n\tu32 sid;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct x86_msi_addr_lo {\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved_0: 2;\n\t\t\tu32 dest_mode_logical: 1;\n\t\t\tu32 redirect_hint: 1;\n\t\t\tu32 reserved_1: 1;\n\t\t\tu32 virt_destid_8_14: 7;\n\t\t\tu32 destid_0_7: 8;\n\t\t\tu32 base_address: 12;\n\t\t};\n\t\tstruct {\n\t\t\tu32 dmar_reserved_0: 2;\n\t\t\tu32 dmar_index_15: 1;\n\t\t\tu32 dmar_subhandle_valid: 1;\n\t\t\tu32 dmar_format: 1;\n\t\t\tu32 dmar_index_0_14: 15;\n\t\t\tu32 dmar_base_address: 12;\n\t\t};\n\t};\n};\n\ntypedef struct x86_msi_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct x86_msi_addr_hi {\n\tu32 reserved: 8;\n\tu32 destid_8_31: 24;\n};\n\ntypedef struct x86_msi_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct x86_msi_data {\n\tunion {\n\t\tstruct {\n\t\t\tu32 vector: 8;\n\t\t\tu32 delivery_mode: 3;\n\t\t\tu32 dest_mode_logical: 1;\n\t\t\tu32 reserved: 2;\n\t\t\tu32 active_low: 1;\n\t\t\tu32 is_level: 1;\n\t\t};\n\t\tu32 dmar_subhandle;\n\t};\n};\n\ntypedef struct x86_msi_data arch_msi_msg_data_t;\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong int msg_stime;\n\tlong int msg_rtime;\n\tlong int msg_ctime;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct msr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 l;\n\t\t\tu32 h;\n\t\t};\n\t\tu64 q;\n\t};\n};\n\nstruct msr_data {\n\tbool host_initiated;\n\tu32 index;\n\tu64 data;\n};\n\nstruct msr_enumeration {\n\tu32 msr_no;\n\tu32 feature;\n};\n\nstruct msr_info {\n\tu32 msr_no;\n\tstruct msr reg;\n\tstruct msr *msrs;\n\tint err;\n};\n\nstruct msr_info_completion {\n\tstruct msr_info msr;\n\tstruct completion done;\n};\n\nstruct msr_regs_info {\n\tu32 *regs;\n\tint err;\n};\n\nstruct mtl_gsc_ver_msg_in {\n\tstruct intel_gsc_mtl_header header;\n\tstruct intel_gsc_mkhi_header mkhi;\n};\n\nstruct mtl_gsc_ver_msg_out {\n\tstruct intel_gsc_mtl_header header;\n\tstruct intel_gsc_mkhi_header mkhi;\n\tu16 proj_major;\n\tu16 compat_major;\n\tu16 compat_minor;\n\tu16 reserved[5];\n};\n\nstruct pxp_cmd_header {\n\tu32 api_version;\n\tu32 command_id;\n\tunion {\n\t\tu32 status;\n\t\tu32 stream_id;\n\t};\n\tu32 buffer_len;\n};\n\nstruct pxp43_new_huc_auth_in {\n\tstruct pxp_cmd_header header;\n\tu64 huc_base_address;\n\tu32 huc_size;\n} __attribute__((packed));\n\nstruct mtl_huc_auth_msg_in {\n\tstruct intel_gsc_mtl_header header;\n\tstruct pxp43_new_huc_auth_in huc_in;\n};\n\nstruct pxp43_huc_auth_out {\n\tstruct pxp_cmd_header header;\n};\n\nstruct mtl_huc_auth_msg_out {\n\tstruct intel_gsc_mtl_header header;\n\tstruct pxp43_huc_auth_out huc_out;\n};\n\nstruct mtrr_gentry {\n\t__u64 base;\n\t__u32 size;\n\t__u32 regnum;\n\t__u32 type;\n\t__u32 _pad;\n};\n\nstruct mtrr_gentry32 {\n\tcompat_ulong_t regnum;\n\tcompat_uint_t base;\n\tcompat_uint_t size;\n\tcompat_uint_t type;\n};\n\nstruct mtrr_ops {\n\tu32 var_regs;\n\tvoid (*set)(unsigned int, long unsigned int, long unsigned int, mtrr_type);\n\tvoid (*get)(unsigned int, long unsigned int *, long unsigned int *, mtrr_type *);\n\tint (*get_free_region)(long unsigned int, long unsigned int, int);\n\tint (*validate_add_page)(long unsigned int, long unsigned int, unsigned int);\n\tint (*have_wrcomb)(void);\n};\n\nstruct mtrr_sentry {\n\t__u64 base;\n\t__u32 size;\n\t__u32 type;\n};\n\nstruct mtrr_sentry32 {\n\tcompat_ulong_t base;\n\tcompat_uint_t size;\n\tcompat_uint_t type;\n};\n\nstruct mtrr_var_range {\n\t__u32 base_lo;\n\t__u32 base_hi;\n\t__u32 mask_lo;\n\t__u32 mask_hi;\n};\n\nstruct mtrr_state_type {\n\tstruct mtrr_var_range var_ranges[256];\n\tmtrr_type fixed_ranges[88];\n\tunsigned char enabled;\n\tbool have_fixed;\n\tmtrr_type def_type;\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\nstruct mwait_cpu_dead {\n\tunsigned int control;\n\tunsigned int status;\n};\n\nstruct my_u {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u0 {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u1 {\n\t__le64 a;\n\t__le64 b;\n\t__le64 c;\n\t__le64 d;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[4];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[64];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u32 offset;\n\t__u32 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct nat_keepalive {\n\tstruct net *net;\n\tu16 family;\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\t__u32 smark;\n};\n\nstruct nat_keepalive_work_ctx {\n\ttime64_t next_run;\n\ttime64_t now;\n};\n\nstruct nf_nat_hooks_net {\n\tstruct nf_hook_ops *nat_hook_ops;\n\tunsigned int users;\n};\n\nstruct nat_net {\n\tstruct nf_nat_hooks_net nat_proto_net[11];\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n};\n\nstruct nd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\t__u8 opt[0];\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct nduseroptmsg {\n\tunsigned char nduseropt_family;\n\tunsigned char nduseropt_pad1;\n\tshort unsigned int nduseropt_opts_len;\n\tint nduseropt_ifindex;\n\t__u8 nduseropt_icmp_type;\n\t__u8 nduseropt_icmp_code;\n\tshort unsigned int nduseropt_pad2;\n\tunsigned int nduseropt_pad3;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tlong: 0;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct ref_tracker_dir {};\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct udp_mib *udplite_statistics;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct sysctl_fib_multipath_hash_seed {\n\tu32 user_seed;\n\tu32 mp_seed;\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 0;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tstruct fib_rules_ops *rules_ops;\n\tstruct fib_table *fib_main;\n\tstruct fib_table *fib_default;\n\tunsigned int fib_rules_require_fldissect;\n\tbool fib_has_custom_rules;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct mr_table *mrt;\n\tstruct sysctl_fib_multipath_hash_seed sysctl_fib_multipath_hash_seed;\n\tu32 sysctl_fib_multipath_hash_fields;\n\tu8 sysctl_fib_multipath_use_neigh;\n\tu8 sysctl_fib_multipath_hash_policy;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tu32 multipath_hash_fields;\n\tu8 multipath_hash_policy;\n\t__u8 __cacheline_group_begin__sysctl_ipv6_flowlabel[0];\n\tu8 flowlabel_consistency;\n\tu8 auto_flowlabels;\n\tu8 flowlabel_state_ranges;\n\t__u8 __cacheline_group_end__sysctl_ipv6_flowlabel[0];\n\tu8 icmpv6_echo_ignore_all;\n\tu8 icmpv6_echo_ignore_multicast;\n\tu8 icmpv6_echo_ignore_anycast;\n\tint icmpv6_time;\n\tlong unsigned int icmpv6_ratemask[4];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tu8 anycast_src_echo_reply;\n\tu8 bindv6only;\n\tu8 ip_nonlocal_bind;\n\tu8 fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tu32 ioam6_id;\n\tu64 ioam6_id_wide;\n\tu8 skip_notify_on_dev_down;\n\tu8 fib_notify_on_flag_change;\n\tu8 icmpv6_error_anycast_as_unicast;\n\tu8 icmpv6_errors_extension_mask;\n};\n\nstruct rt6_statistics;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct dst_ops ip6_dst_ops;\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tspinlock_t fib_table_hash_lock;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tatomic_t ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned char flowlabel_has_excl;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct hlist_head *inet6_addr_lst;\n\tspinlock_t addrconf_hash_lock;\n\tstruct delayed_work addr_chk_work;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tstruct ioam6_pernet_data *ioam6_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nf_logger;\n\nstruct nf_hook_entries;\n\nstruct netns_nf {\n\tstruct proc_dir_entry *proc_netfilter;\n\tconst struct nf_logger *nf_loggers[11];\n\tstruct ctl_table_header *nf_log_dir_header;\n\tstruct nf_hook_entries *hooks_ipv4[5];\n\tstruct nf_hook_entries *hooks_ipv6[5];\n\tunsigned int defrag_ipv4_users;\n\tunsigned int defrag_ipv6_users;\n};\n\nstruct nf_ct_event_notifier;\n\nstruct nf_generic_net {\n\tunsigned int timeout;\n};\n\nstruct nf_tcp_net {\n\tunsigned int timeouts[14];\n\tu8 tcp_loose;\n\tu8 tcp_be_liberal;\n\tu8 tcp_max_retrans;\n\tu8 tcp_ignore_invalid_rst;\n};\n\nstruct nf_udp_net {\n\tunsigned int timeouts[2];\n};\n\nstruct nf_icmp_net {\n\tunsigned int timeout;\n};\n\nstruct nf_ip_net {\n\tstruct nf_generic_net generic;\n\tstruct nf_tcp_net tcp;\n\tstruct nf_udp_net udp;\n\tstruct nf_icmp_net icmp;\n\tstruct nf_icmp_net icmpv6;\n};\n\nstruct netns_ct {\n\tu8 sysctl_log_invalid;\n\tu8 sysctl_events;\n\tu8 sysctl_acct;\n\tu8 sysctl_tstamp;\n\tu8 sysctl_checksum;\n\tstruct ip_conntrack_stat *stat;\n\tstruct nf_ct_event_notifier *nf_conntrack_event_cb;\n\tstruct nf_ip_net nf_ct_proto;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct xfrm_policy_hash {\n\tstruct hlist_head *table;\n\tunsigned int hmask;\n\tu8 dbits4;\n\tu8 sbits4;\n\tu8 dbits6;\n\tu8 sbits6;\n};\n\nstruct xfrm_policy_hthresh {\n\tstruct work_struct work;\n\tseqlock_t lock;\n\tu8 lbits4;\n\tu8 rbits4;\n\tu8 lbits6;\n\tu8 rbits6;\n};\n\nstruct netns_xfrm {\n\tstruct list_head state_all;\n\tstruct hlist_head *state_bydst;\n\tstruct hlist_head *state_bysrc;\n\tstruct hlist_head *state_byspi;\n\tstruct hlist_head *state_byseq;\n\tstruct hlist_head *state_cache_input;\n\tunsigned int state_hmask;\n\tunsigned int state_num;\n\tstruct work_struct state_hash_work;\n\tstruct list_head policy_all;\n\tstruct hlist_head *policy_byidx;\n\tunsigned int policy_idx_hmask;\n\tunsigned int idx_generator;\n\tstruct xfrm_policy_hash policy_bydst[3];\n\tunsigned int policy_count[6];\n\tstruct work_struct policy_hash_work;\n\tstruct xfrm_policy_hthresh policy_hthresh;\n\tstruct list_head inexact_bins;\n\tstruct sock *nlsk;\n\tstruct sock *nlsk_stash;\n\tu32 sysctl_aevent_etime;\n\tu32 sysctl_aevent_rseqth;\n\tint sysctl_larval_drop;\n\tu32 sysctl_acq_expires;\n\tu8 policy_default[3];\n\tstruct ctl_table_header *sysctl_hdr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct dst_ops xfrm4_dst_ops;\n\tstruct dst_ops xfrm6_dst_ops;\n\tspinlock_t xfrm_state_lock;\n\tseqcount_spinlock_t xfrm_state_hash_generation;\n\tseqcount_spinlock_t xfrm_policy_hash_generation;\n\tspinlock_t xfrm_policy_lock;\n\tstruct mutex xfrm_cfg_mutex;\n\tstruct delayed_work nat_keepalive_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct netns_nf nf;\n\tstruct netns_ct ct;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_xfrm xfrm;\n\tu64 net_cookie;\n\tstruct sock *diag_nlsk;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_sw_netstats;\n\nstruct pcpu_dstats;\n\nstruct netpoll_info;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct xdp_dev_bulk_queue;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct netprio_map;\n\nstruct phy_link_topology;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct nf_hook_entries *nf_hooks_egress;\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct netpoll_info *npinfo;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tstruct wireless_dev *ieee80211_ptr;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tstruct nf_hook_entries *nf_hooks_ingress;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct hlist_head qdisc_hash[16];\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct netprio_map *priomap;\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tlong: 64;\n\tlong: 64;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct rtnl_link_stats64;\n\nstruct netdev_bpf;\n\nstruct xdp_frame;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tvoid (*ndo_poll_controller)(struct net_device *);\n\tint (*ndo_netpoll_setup)(struct net_device *);\n\tvoid (*ndo_netpoll_cleanup)(struct net_device *);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct net_failover_info {\n\tstruct net_device *primary_dev;\n\tstruct net_device *standby_dev;\n\tstruct rtnl_link_stats64 primary_stats;\n\tstruct rtnl_link_stats64 standby_stats;\n\tstruct rtnl_link_stats64 failover_stats;\n\tspinlock_t stats_lock;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct inet6_protocol tcpv6_protocol;\n\tstruct inet6_protocol udpv6_protocol;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_packet_attrs {\n\tconst unsigned char *src;\n\tconst unsigned char *dst;\n\tu32 ip_src;\n\tu32 ip_dst;\n\tbool tcp;\n\tu16 sport;\n\tu16 dport;\n\tint timeout;\n\tint size;\n\tint max_size;\n\tu8 id;\n\tu16 queue_mapping;\n\tbool bad_csum;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct net_test {\n\tchar name[32];\n\tint (*fn)(struct net_device *);\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct net_test_priv {\n\tstruct net_packet_attrs *packet;\n\tstruct packet_type pt;\n\tstruct completion comp;\n\tint double_vlan;\n\tint vlan_id;\n\tint ok;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netconsole_target_stats {\n\tu64_stats_t xmit_drop_count;\n\tu64_stats_t enomem_count;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct netpoll {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tchar dev_name[16];\n\tu8 dev_mac[6];\n\tconst char *name;\n\tunion inet_addr local_ip;\n\tunion inet_addr remote_ip;\n\tbool ipv6;\n\tu16 local_port;\n\tu16 remote_port;\n\tu8 remote_mac[6];\n\tstruct sk_buff_head skb_pool;\n\tstruct work_struct refill_wq;\n};\n\nstruct netconsole_target {\n\tstruct list_head list;\n\tstruct netconsole_target_stats stats;\n\tenum target_state state;\n\tbool extended;\n\tbool release;\n\tstruct netpoll np;\n\tchar buf[1000];\n\tstruct work_struct resume_wq;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct xsk_buff_pool;\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_lag_lower_state_info {\n\tu8 link_up: 1;\n\tu8 tx_enabled: 1;\n};\n\nstruct netdev_lag_upper_info {\n\tenum netdev_lag_tx_type tx_type;\n\tenum netdev_lag_hash hash_type;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tlong: 64;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tint numa_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n};\n\nstruct netevent_redirect {\n\tstruct dst_entry *old;\n\tstruct dst_entry *new;\n\tstruct neighbour *neigh;\n\tconst void *daddr;\n};\n\ntypedef void (*netfs_io_terminated_t)(void *, ssize_t);\n\nstruct netfs_io_subrequest;\n\nstruct netfs_cache_ops {\n\tvoid (*end_operation)(struct netfs_cache_resources *);\n\tint (*read)(struct netfs_cache_resources *, loff_t, struct iov_iter *, enum netfs_read_from_hole, netfs_io_terminated_t, void *);\n\tint (*write)(struct netfs_cache_resources *, loff_t, struct iov_iter *, netfs_io_terminated_t, void *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_cache_resources *, long long unsigned int *, long long unsigned int *, long long unsigned int);\n\tenum netfs_io_source (*prepare_read)(struct netfs_io_subrequest *, long long unsigned int);\n\tvoid (*prepare_write_subreq)(struct netfs_io_subrequest *);\n\tint (*prepare_write)(struct netfs_cache_resources *, loff_t *, size_t *, size_t, loff_t, bool);\n\tenum netfs_io_source (*prepare_ondemand_read)(struct netfs_cache_resources *, loff_t, size_t *, loff_t, long unsigned int *, ino_t);\n\tint (*query_occupancy)(struct netfs_cache_resources *, loff_t, size_t, size_t, loff_t *, size_t *);\n};\n\nstruct netfs_cache_resources {\n\tconst struct netfs_cache_ops *ops;\n\tvoid *cache_priv;\n\tvoid *cache_priv2;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n};\n\nstruct netfs_group;\n\nstruct netfs_folio {\n\tstruct netfs_group *netfs_group;\n\tunsigned int dirty_offset;\n\tunsigned int dirty_len;\n};\n\nstruct netfs_group {\n\trefcount_t ref;\n\tvoid (*free)(struct netfs_group *);\n};\n\nstruct netfs_request_ops;\n\nstruct netfs_inode {\n\tstruct inode inode;\n\tconst struct netfs_request_ops *ops;\n\tstruct mutex wb_lock;\n\tloff_t remote_i_size;\n\tloff_t zero_point;\n\tatomic_t io_count;\n\tlong unsigned int flags;\n};\n\nstruct netfs_io_stream {\n\tstruct netfs_io_subrequest *construct;\n\tsize_t sreq_max_len;\n\tunsigned int sreq_max_segs;\n\tunsigned int submit_off;\n\tunsigned int submit_len;\n\tunsigned int submit_extendable_to;\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tstruct list_head subrequests;\n\tstruct netfs_io_subrequest *front;\n\tlong long unsigned int collected_to;\n\tsize_t transferred;\n\tshort unsigned int error;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tbool avail;\n\tbool active;\n\tbool need_retry;\n\tbool failed;\n\tbool transferred_valid;\n};\n\nstruct rolling_buffer {\n\tstruct folio_queue *head;\n\tstruct folio_queue *tail;\n\tstruct iov_iter iter;\n\tu8 next_head_slot;\n\tu8 first_tail_slot;\n};\n\nstruct netfs_io_request {\n\tunion {\n\t\tstruct work_struct cleanup_work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct work_struct work;\n\tstruct inode *inode;\n\tstruct address_space *mapping;\n\tstruct kiocb *iocb;\n\tstruct netfs_cache_resources cache_resources;\n\tstruct netfs_io_request *copy_to_cache;\n\tstruct list_head proc_link;\n\tstruct netfs_io_stream io_streams[2];\n\tstruct netfs_group *group;\n\tstruct rolling_buffer buffer;\n\twait_queue_head_t waitq;\n\tvoid *netfs_priv;\n\tvoid *netfs_priv2;\n\tstruct bio_vec *direct_bv;\n\tlong long unsigned int submitted;\n\tlong long unsigned int len;\n\tsize_t transferred;\n\tlong int error;\n\tlong long unsigned int i_size;\n\tlong long unsigned int start;\n\tatomic64_t issued_to;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int abandon_to;\n\tlong unsigned int no_unlock_folio;\n\tunsigned int direct_bv_count;\n\tunsigned int debug_id;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tatomic_t subreq_counter;\n\tunsigned int nr_group_rel;\n\tspinlock_t lock;\n\tunsigned char front_folio_order;\n\tenum netfs_io_origin origin;\n\tbool direct_bv_unpin;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tconst struct netfs_request_ops *netfs_ops;\n};\n\nstruct netfs_io_subrequest {\n\tstruct netfs_io_request *rreq;\n\tstruct work_struct work;\n\tstruct list_head rreq_link;\n\tstruct iov_iter io_iter;\n\tlong long unsigned int start;\n\tsize_t len;\n\tsize_t transferred;\n\trefcount_t ref;\n\tshort int error;\n\tshort unsigned int debug_index;\n\tunsigned int nr_segs;\n\tu8 retry_count;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tlong unsigned int flags;\n};\n\nstruct netfs_request_ops {\n\tmempool_t *request_pool;\n\tmempool_t *subrequest_pool;\n\tint (*init_request)(struct netfs_io_request *, struct file *);\n\tvoid (*free_request)(struct netfs_io_request *);\n\tvoid (*free_subrequest)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_io_request *);\n\tint (*prepare_read)(struct netfs_io_subrequest *);\n\tvoid (*issue_read)(struct netfs_io_subrequest *);\n\tbool (*is_still_valid)(struct netfs_io_request *);\n\tint (*check_write_begin)(struct file *, loff_t, unsigned int, struct folio **, void **);\n\tvoid (*done)(struct netfs_io_request *);\n\tvoid (*update_i_size)(struct inode *, loff_t);\n\tvoid (*post_modify)(struct inode *);\n\tvoid (*begin_writeback)(struct netfs_io_request *);\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*retry_request)(struct netfs_io_request *, struct netfs_io_stream *);\n\tvoid (*invalidate_cache)(struct netfs_io_request *);\n};\n\nstruct netif_security_struct {\n\tconst struct net *ns;\n\tint ifindex;\n\tu32 sid;\n};\n\nstruct netlbl_af4list {\n\t__be32 addr;\n\t__be32 mask;\n\tu32 valid;\n\tstruct list_head list;\n};\n\nstruct netlbl_af6list {\n\tstruct in6_addr addr;\n\tstruct in6_addr mask;\n\tu32 valid;\n\tstruct list_head list;\n};\n\nstruct netlbl_audit {\n\tstruct lsm_prop prop;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n};\n\nstruct netlbl_calipso_doiwalk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nstruct netlbl_lsm_secattr;\n\nstruct netlbl_calipso_ops {\n\tint (*doi_add)(struct calipso_doi *, struct netlbl_audit *);\n\tvoid (*doi_free)(struct calipso_doi *);\n\tint (*doi_remove)(u32, struct netlbl_audit *);\n\tstruct calipso_doi * (*doi_getdef)(u32);\n\tvoid (*doi_putdef)(struct calipso_doi *);\n\tint (*doi_walk)(u32 *, int (*)(struct calipso_doi *, void *), void *);\n\tint (*sock_getattr)(struct sock *, struct netlbl_lsm_secattr *);\n\tint (*sock_setattr)(struct sock *, const struct calipso_doi *, const struct netlbl_lsm_secattr *);\n\tvoid (*sock_delattr)(struct sock *);\n\tint (*req_setattr)(struct request_sock *, const struct calipso_doi *, const struct netlbl_lsm_secattr *);\n\tvoid (*req_delattr)(struct request_sock *);\n\tint (*opt_getattr)(const unsigned char *, struct netlbl_lsm_secattr *);\n\tunsigned char * (*skbuff_optptr)(const struct sk_buff *);\n\tint (*skbuff_setattr)(struct sk_buff *, const struct calipso_doi *, const struct netlbl_lsm_secattr *);\n\tint (*skbuff_delattr)(struct sk_buff *);\n\tvoid (*cache_invalidate)(void);\n\tint (*cache_add)(const unsigned char *, const struct netlbl_lsm_secattr *);\n};\n\nstruct netlbl_cipsov4_doiwalk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nstruct netlbl_domaddr_map;\n\nstruct netlbl_dommap_def {\n\tu32 type;\n\tunion {\n\t\tstruct netlbl_domaddr_map *addrsel;\n\t\tstruct cipso_v4_doi *cipso;\n\t\tstruct calipso_doi *calipso;\n\t};\n};\n\nstruct netlbl_dom_map {\n\tchar *domain;\n\tstruct netlbl_dommap_def def;\n\tu16 family;\n\tu32 valid;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_domaddr4_map {\n\tstruct netlbl_dommap_def def;\n\tstruct netlbl_af4list list;\n};\n\nstruct netlbl_domaddr6_map {\n\tstruct netlbl_dommap_def def;\n\tstruct netlbl_af6list list;\n};\n\nstruct netlbl_domaddr_map {\n\tstruct list_head list4;\n\tstruct list_head list6;\n};\n\nstruct netlbl_domhsh_tbl {\n\tstruct list_head *tbl;\n\tu32 size;\n};\n\nstruct netlbl_domhsh_walk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nstruct netlbl_domhsh_walk_arg___2 {\n\tstruct netlbl_audit *audit_info;\n\tu32 doi;\n};\n\nstruct netlbl_lsm_cache {\n\trefcount_t refcount;\n\tvoid (*free)(const void *);\n\tvoid *data;\n};\n\nstruct netlbl_lsm_catmap {\n\tu32 startbit;\n\tu64 bitmap[4];\n\tstruct netlbl_lsm_catmap *next;\n};\n\nstruct netlbl_lsm_secattr {\n\tu32 flags;\n\tu32 type;\n\tchar *domain;\n\tstruct netlbl_lsm_cache *cache;\n\tstruct {\n\t\tstruct {\n\t\t\tstruct netlbl_lsm_catmap *cat;\n\t\t\tu32 lvl;\n\t\t} mls;\n\t\tu32 secid;\n\t} attr;\n};\n\nstruct netlbl_unlhsh_addr4 {\n\tu32 secid;\n\tstruct netlbl_af4list list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_unlhsh_addr6 {\n\tu32 secid;\n\tstruct netlbl_af6list list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_unlhsh_iface {\n\tint ifindex;\n\tstruct list_head addr4_list;\n\tstruct list_head addr6_list;\n\tu32 valid;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_unlhsh_tbl {\n\tstruct list_head *tbl;\n\tu32 size;\n};\n\nstruct netlbl_unlhsh_walk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netnode_security_struct {\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} addr;\n\tu32 sid;\n\tu16 family;\n};\n\nstruct netpoll_info {\n\trefcount_t refcnt;\n\tstruct semaphore dev_lock;\n\tstruct sk_buff_head txq;\n\tstruct delayed_work tx_work;\n\tstruct callback_head rcu;\n};\n\nstruct netport_security_struct {\n\tu32 sid;\n\tu16 port;\n\tu8 protocol;\n};\n\nstruct netprio_map {\n\tstruct callback_head rcu;\n\tu32 priomap_len;\n\tu32 priomap[0];\n};\n\nstruct netsfhdr {\n\t__be32 version;\n\t__be64 magic;\n\tu8 id;\n} __attribute__((packed));\n\nstruct new_asid {\n\tunsigned int asid: 16;\n\tunsigned int need_flush: 1;\n};\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_conntrack {\n\trefcount_t use;\n};\n\nstruct nf_conntrack_tuple_hash {\n\tstruct hlist_nulls_node hnnode;\n\tstruct nf_conntrack_tuple tuple;\n};\n\nstruct nf_ct_udp {\n\tlong unsigned int stream_ts;\n};\n\nstruct nf_ct_gre {\n\tunsigned int stream_timeout;\n\tunsigned int timeout;\n};\n\nunion nf_conntrack_proto {\n\tstruct ip_ct_sctp sctp;\n\tstruct ip_ct_tcp tcp;\n\tstruct nf_ct_udp udp;\n\tstruct nf_ct_gre gre;\n\tunsigned int tmpl_padto;\n};\n\nstruct nf_ct_ext;\n\nstruct nf_conn {\n\tstruct nf_conntrack ct_general;\n\tspinlock_t lock;\n\tu32 timeout;\n\tstruct nf_conntrack_tuple_hash tuplehash[2];\n\tlong unsigned int status;\n\tpossible_net_t ct_net;\n\tstruct hlist_node nat_bysource;\n\tstruct {} __nfct_init_offset;\n\tstruct nf_conn *master;\n\tu_int32_t secmark;\n\tstruct nf_ct_ext *ext;\n\tunion nf_conntrack_proto proto;\n};\n\nstruct nf_conn___init {\n\tstruct nf_conn ct;\n};\n\nstruct nf_conn_counter {\n\tatomic64_t packets;\n\tatomic64_t bytes;\n};\n\nstruct nf_conn_acct {\n\tstruct nf_conn_counter counter[2];\n};\n\nstruct nf_conntrack_helper;\n\nstruct nf_conn_help {\n\tstruct nf_conntrack_helper *helper;\n\tstruct hlist_head expectations;\n\tu8 expecting[4];\n\tlong: 0;\n\tchar data[32];\n};\n\nstruct nf_conn_labels {\n\tlong unsigned int bits[2];\n};\n\nunion nf_conntrack_nat_help {};\n\nstruct nf_conn_nat {\n\tunion nf_conntrack_nat_help help;\n\tint masq_index;\n};\n\nstruct nf_ct_seqadj {\n\tu32 correction_pos;\n\ts32 offset_before;\n\ts32 offset_after;\n};\n\nstruct nf_conn_seqadj {\n\tstruct nf_ct_seqadj seq[2];\n};\n\nstruct nf_conn_synproxy {\n\tu32 isn;\n\tu32 its;\n\tu32 tsoff;\n};\n\nstruct nf_ct_timeout;\n\nstruct nf_conn_timeout {\n\tstruct nf_ct_timeout *timeout;\n};\n\nstruct nf_conn_tstamp {\n\tu_int64_t start;\n\tu_int64_t stop;\n};\n\nstruct nf_conntrack_tuple_mask {\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion nf_conntrack_man_proto u;\n\t} src;\n};\n\nstruct nf_conntrack_expect {\n\tstruct hlist_node lnode;\n\tstruct hlist_node hnode;\n\tstruct nf_conntrack_tuple tuple;\n\tstruct nf_conntrack_tuple_mask mask;\n\trefcount_t use;\n\tunsigned int flags;\n\tunsigned int class;\n\tvoid (*expectfn)(struct nf_conn *, struct nf_conntrack_expect *);\n\tstruct nf_conntrack_helper *helper;\n\tstruct nf_conn *master;\n\tstruct timer_list timeout;\n\tunion nf_inet_addr saved_addr;\n\tunion nf_conntrack_man_proto saved_proto;\n\tenum ip_conntrack_dir dir;\n\tstruct callback_head rcu;\n};\n\nstruct nf_conntrack_expect_policy {\n\tunsigned int max_expected;\n\tunsigned int timeout;\n\tchar name[16];\n};\n\nstruct nf_conntrack_helper {\n\tstruct hlist_node hnode;\n\tchar name[16];\n\trefcount_t refcnt;\n\tstruct module *me;\n\tconst struct nf_conntrack_expect_policy *expect_policy;\n\tstruct nf_conntrack_tuple tuple;\n\tint (*help)(struct sk_buff *, unsigned int, struct nf_conn *, enum ip_conntrack_info);\n\tvoid (*destroy)(struct nf_conn *);\n\tint (*from_nlattr)(struct nlattr *, struct nf_conn *);\n\tint (*to_nlattr)(struct sk_buff *, const struct nf_conn *);\n\tunsigned int expect_class_max;\n\tunsigned int flags;\n\tunsigned int queue_num;\n\tu16 data_len;\n\tchar nat_mod_name[16];\n};\n\nstruct nf_conntrack_l4proto {\n\tu_int8_t l4proto;\n\tbool allow_clash;\n\tu16 nlattr_size;\n\tbool (*can_early_drop)(const struct nf_conn *);\n\tint (*to_nlattr)(struct sk_buff *, struct nlattr *, struct nf_conn *, bool);\n\tint (*from_nlattr)(struct nlattr **, struct nf_conn *);\n\tint (*tuple_to_nlattr)(struct sk_buff *, const struct nf_conntrack_tuple *);\n\tunsigned int (*nlattr_tuple_size)(void);\n\tint (*nlattr_to_tuple)(struct nlattr **, struct nf_conntrack_tuple *, u_int32_t);\n\tconst struct nla_policy *nla_policy;\n\tstruct {\n\t\tint (*nlattr_to_obj)(struct nlattr **, struct net *, void *);\n\t\tint (*obj_to_nlattr)(struct sk_buff *, const void *);\n\t\tu16 obj_size;\n\t\tu16 nlattr_max;\n\t\tconst struct nla_policy *nla_policy;\n\t} ctnl_timeout;\n};\n\nstruct nf_conntrack_nat_helper {\n\tstruct list_head list;\n\tchar mod_name[16];\n\tstruct module *module;\n};\n\nstruct nf_conntrack_net {\n\tatomic_t count;\n\tunsigned int expect_count;\n\tunsigned int users4;\n\tunsigned int users6;\n\tunsigned int users_bridge;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct nf_ct_bridge_info {\n\tstruct nf_hook_ops *ops;\n\tunsigned int ops_size;\n\tstruct module *me;\n};\n\nstruct nf_ct_ext {\n\tu8 offset[4];\n\tu8 len;\n\tunsigned int gen_id;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct nf_ct_ftp_master {\n\tu_int32_t seq_aft_nl[4];\n\tu_int16_t seq_aft_nl_num[2];\n\tu_int16_t flags[2];\n};\n\nstruct nf_ct_helper_expectfn {\n\tstruct list_head head;\n\tconst char *name;\n\tvoid (*expectfn)(struct nf_conn *, struct nf_conntrack_expect *);\n};\n\nstruct nf_ct_hook {\n\tint (*update)(struct net *, struct sk_buff *);\n\tvoid (*destroy)(struct nf_conntrack *);\n\tbool (*get_tuple_skb)(struct nf_conntrack_tuple *, const struct sk_buff *);\n\tvoid (*attach)(struct sk_buff *, const struct sk_buff *);\n\tvoid (*set_closing)(struct nf_conntrack *);\n\tint (*confirm)(struct sk_buff *);\n\tu32 (*get_id)(const struct nf_conntrack *);\n};\n\nstruct nf_ct_iter_data {\n\tstruct net *net;\n\tvoid *data;\n\tu32 portid;\n\tint report;\n};\n\nstruct nf_ct_sip_master {\n\tunsigned int register_cseq;\n\tunsigned int invite_cseq;\n\t__be16 forced_dport;\n};\n\nstruct nf_ct_tcp_flags {\n\t__u8 flags;\n\t__u8 mask;\n};\n\nstruct nf_ct_timeout {\n\t__u16 l3num;\n\tconst struct nf_conntrack_l4proto *l4proto;\n\tchar data[0];\n};\n\nstruct nf_defrag_hook {\n\tstruct module *owner;\n\tint (*enable)(struct net *);\n\tvoid (*disable)(struct net *);\n};\n\nstruct nf_hook_entry {\n\tnf_hookfn *hook;\n\tvoid *priv;\n};\n\nstruct nf_hook_entries {\n\tu16 num_hook_entries;\n\tstruct nf_hook_entry hooks[0];\n};\n\nstruct nf_hook_entries_rcu_head {\n\tstruct callback_head head;\n\tvoid *allocation;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nf_queue_entry;\n\nstruct nf_ipv6_ops {\n\tvoid (*route_input)(struct sk_buff *);\n\tint (*fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tint (*reroute)(struct sk_buff *, const struct nf_queue_entry *);\n};\n\nstruct nf_log_buf {\n\tunsigned int count;\n\tchar buf[1020];\n};\n\nstruct nf_loginfo;\n\ntypedef void nf_logfn(struct net *, u_int8_t, unsigned int, const struct sk_buff *, const struct net_device *, const struct net_device *, const struct nf_loginfo *, const char *);\n\nstruct nf_logger {\n\tchar *name;\n\tenum nf_log_type type;\n\tnf_logfn *logfn;\n\tstruct module *me;\n};\n\nstruct nf_loginfo {\n\tu_int8_t type;\n\tunion {\n\t\tstruct {\n\t\t\tu_int32_t copy_len;\n\t\t\tu_int16_t group;\n\t\t\tu_int16_t qthreshold;\n\t\t\tu_int16_t flags;\n\t\t} ulog;\n\t\tstruct {\n\t\t\tu_int8_t level;\n\t\t\tu_int8_t logflags;\n\t\t} log;\n\t} u;\n};\n\nstruct nf_mttg_trav {\n\tstruct list_head *head;\n\tstruct list_head *curr;\n\tuint8_t class;\n};\n\nstruct nf_nat_hook {\n\tint (*parse_nat_setup)(struct nf_conn *, enum nf_nat_manip_type, const struct nlattr *);\n\tvoid (*decode_session)(struct sk_buff *, struct flowi *);\n\tvoid (*remove_nat_bysrc)(struct nf_conn *);\n};\n\nstruct nf_nat_lookup_hook_priv {\n\tstruct nf_hook_entries *entries;\n\tstruct callback_head callback_head;\n};\n\nstruct nf_nat_proto_clean {\n\tu8 l3proto;\n\tu8 l4proto;\n};\n\nstruct nf_nat_range2 {\n\tunsigned int flags;\n\tunion nf_inet_addr min_addr;\n\tunion nf_inet_addr max_addr;\n\tunion nf_conntrack_man_proto min_proto;\n\tunion nf_conntrack_man_proto max_proto;\n\tunion nf_conntrack_man_proto base_proto;\n};\n\nstruct nf_nat_sip_hooks {\n\tunsigned int (*msg)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *);\n\tvoid (*seq_adjust)(struct sk_buff *, unsigned int, s16);\n\tunsigned int (*expect)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, struct nf_conntrack_expect *, unsigned int, unsigned int);\n\tunsigned int (*sdp_addr)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, enum sdp_header_types, enum sdp_header_types, const union nf_inet_addr *);\n\tunsigned int (*sdp_port)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, unsigned int, u_int16_t);\n\tunsigned int (*sdp_session)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, const union nf_inet_addr *);\n\tunsigned int (*sdp_media)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, struct nf_conntrack_expect *, struct nf_conntrack_expect *, unsigned int, unsigned int, union nf_inet_addr *);\n};\n\nstruct nf_queue_entry {\n\tstruct list_head list;\n\tstruct rhash_head hash_node;\n\tstruct sk_buff *skb;\n\tunsigned int id;\n\tunsigned int hook_index;\n\tstruct nf_hook_state state;\n\tbool nf_ct_is_unconfirmed;\n\tu16 size;\n\tu16 queue_num;\n};\n\nstruct nf_queue_handler {\n\tint (*outfn)(struct nf_queue_entry *, unsigned int);\n\tvoid (*nf_hook_drop)(struct net *);\n};\n\nstruct nf_sockopt_ops {\n\tstruct list_head list;\n\tu_int8_t pf;\n\tint set_optmin;\n\tint set_optmax;\n\tint (*set)(struct sock *, int, sockptr_t, unsigned int);\n\tint get_optmin;\n\tint get_optmax;\n\tint (*get)(struct sock *, int, void *, int *);\n\tstruct module *owner;\n};\n\nstruct nfgenmsg {\n\t__u8 nfgen_family;\n\t__u8 version;\n\t__be16 res_id;\n};\n\nstruct nfnl_callback;\n\nstruct nfnetlink_subsystem {\n\tconst char *name;\n\t__u8 subsys_id;\n\t__u8 cb_count;\n\tconst struct nfnl_callback *cb;\n\tstruct module *owner;\n\tint (*commit)(struct net *, struct sk_buff *);\n\tint (*abort)(struct net *, struct sk_buff *, enum nfnl_abort_action);\n\tbool (*valid_genid)(struct net *, u32);\n};\n\nstruct nfnl_info;\n\nstruct nfnl_callback {\n\tint (*call)(struct sk_buff *, const struct nfnl_info *, const struct nlattr * const *);\n\tconst struct nla_policy *policy;\n\tenum nfnl_callback_type type;\n\t__u16 attr_count;\n};\n\nstruct nfnl_ct_hook {\n\tsize_t (*build_size)(const struct nf_conn *);\n\tint (*build)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, u_int16_t, u_int16_t);\n\tint (*parse)(const struct nlattr *, struct nf_conn *);\n\tint (*attach_expect)(const struct nlattr *, struct nf_conn *, u32, u32);\n\tvoid (*seq_adjust)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, s32);\n};\n\nstruct nfnl_err {\n\tstruct list_head head;\n\tstruct nlmsghdr *nlh;\n\tint err;\n\tstruct netlink_ext_ack extack;\n};\n\nstruct nfnl_info {\n\tstruct net *net;\n\tstruct sock *sk;\n\tconst struct nlmsghdr *nlh;\n\tconst struct nfgenmsg *nfmsg;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct nfnl_log_net {\n\tspinlock_t instances_lock;\n\tstruct hlist_head instance_table[16];\n\tatomic_t global_seq;\n};\n\nstruct nfnl_net {\n\tstruct sock *nfnl;\n};\n\nstruct nfs2_fh {\n\tchar data[32];\n};\n\nstruct nfs3_accessargs {\n\tstruct nfs_fh *fh;\n\t__u32 access;\n};\n\nstruct nfs_fattr;\n\nstruct nfs3_accessres {\n\tstruct nfs_fattr *fattr;\n\t__u32 access;\n};\n\nstruct nfs3_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n\tenum nfs3_createmode createmode;\n\t__be32 verifier[2];\n};\n\nstruct rpc_procinfo;\n\nstruct rpc_message {\n\tconst struct rpc_procinfo *rpc_proc;\n\tvoid *rpc_argp;\n\tvoid *rpc_resp;\n\tconst struct cred *rpc_cred;\n};\n\nstruct nfs3_mkdirargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_mknodargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tenum nfs3_ftype type;\n\tstruct iattr *sattr;\n\tdev_t rdev;\n};\n\nstruct nfs3_diropres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs4_string;\n\nstruct nfs4_threshold;\n\nstruct nfs4_label;\n\nstruct nfs_fattr {\n\t__u64 valid;\n\tumode_t mode;\n\t__u32 nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\t__u64 size;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 blocksize;\n\t\t\t__u32 blocks;\n\t\t} nfs2;\n\t\tstruct {\n\t\t\t__u64 used;\n\t\t} nfs3;\n\t} du;\n\tstruct nfs_fsid fsid;\n\t__u64 fileid;\n\t__u64 mounted_on_fileid;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\t__u64 change_attr;\n\t__u64 pre_change_attr;\n\t__u64 pre_size;\n\tstruct timespec64 pre_mtime;\n\tstruct timespec64 pre_ctime;\n\tlong unsigned int time_start;\n\tlong unsigned int gencount;\n\tstruct nfs4_string *owner_name;\n\tstruct nfs4_string *group_name;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs3_createdata {\n\tstruct rpc_message msg;\n\tunion {\n\t\tstruct nfs3_createargs create;\n\t\tstruct nfs3_mkdirargs mkdir;\n\t\tstruct nfs3_symlinkargs symlink;\n\t\tstruct nfs3_mknodargs mknod;\n\t} arg;\n\tstruct nfs3_diropres res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_fattr dir_attr;\n};\n\nstruct nfs3_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs3_fh {\n\tshort unsigned int size;\n\tunsigned char data[64];\n};\n\nstruct nfs3_getaclargs {\n\tstruct nfs_fh *fh;\n\tint mask;\n\tstruct page **pages;\n};\n\nstruct nfs3_getaclres {\n\tstruct nfs_fattr *fattr;\n\tint mask;\n\tunsigned int acl_access_count;\n\tunsigned int acl_default_count;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n};\n\nstruct nfs3_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs3_linkres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_readdirargs {\n\tstruct nfs_fh *fh;\n\t__u64 cookie;\n\t__be32 verf[2];\n\tbool plus;\n\tunsigned int count;\n\tstruct page **pages;\n};\n\nstruct nfs3_readdirres {\n\tstruct nfs_fattr *dir_attr;\n\t__be32 *verf;\n\tbool plus;\n};\n\nstruct nfs3_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs3_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n\tunsigned int guard;\n\tstruct timespec64 guardtime;\n};\n\nstruct nfs3_setaclargs {\n\tstruct inode *inode;\n\tint mask;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n\tsize_t len;\n\tunsigned int npages;\n\tstruct page **pages;\n};\n\nstruct nfs41_bind_conn_to_session_args {\n\tstruct nfs_client *client;\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n\tint retries;\n};\n\nstruct nfs41_bind_conn_to_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n};\n\nstruct nfs4_channel_attrs {\n\tu32 max_rqst_sz;\n\tu32 max_resp_sz;\n\tu32 max_resp_sz_cached;\n\tu32 max_ops;\n\tu32 max_reqs;\n};\n\nstruct nfs41_create_session_args {\n\tstruct nfs_client *client;\n\tu64 clientid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tuint32_t cb_program;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs41_create_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs4_op_map {\n\tunion {\n\t\tlong unsigned int longs[2];\n\t\tu32 words[4];\n\t} u;\n};\n\nstruct nfs41_state_protection {\n\tu32 how;\n\tstruct nfs4_op_map enforce;\n\tstruct nfs4_op_map allow;\n};\n\nstruct nfs41_exchange_id_args {\n\tstruct nfs_client *client;\n\tnfs4_verifier verifier;\n\tu32 flags;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_server_owner;\n\nstruct nfs41_server_scope;\n\nstruct nfs41_impl_id;\n\nstruct nfs41_exchange_id_res {\n\tu64 clientid;\n\tu32 seqid;\n\tu32 flags;\n\tstruct nfs41_server_owner *server_owner;\n\tstruct nfs41_server_scope *server_scope;\n\tstruct nfs41_impl_id *impl_id;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_exchange_id_data {\n\tstruct nfs41_exchange_id_res res;\n\tstruct nfs41_exchange_id_args args;\n};\n\nstruct nfs4_sequence_args {\n\tstruct nfs4_slot *sa_slot;\n\tu8 sa_cache_this: 1;\n\tu8 sa_privileged: 1;\n};\n\nstruct nfs41_free_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_sequence_slot_ops;\n\nstruct nfs4_sequence_res {\n\tconst struct nfs4_sequence_slot_ops *sr_slot_ops;\n\tstruct nfs4_slot *sr_slot;\n\tlong unsigned int sr_timestamp;\n\tint sr_status;\n\tu32 sr_status_flags;\n\tu32 sr_highest_slotid;\n\tu32 sr_target_highest_slotid;\n};\n\nstruct nfs41_free_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfstime4 {\n\tint64_t seconds;\n\tuint32_t nseconds;\n};\n\nstruct nfs41_impl_id {\n\tchar domain[1025];\n\tchar name[1025];\n\tstruct nfstime4 date;\n};\n\nstruct nfs41_reclaim_complete_args {\n\tstruct nfs4_sequence_args seq_args;\n\tunsigned char one_fs: 1;\n};\n\nstruct nfs41_reclaim_complete_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs41_secinfo_no_name_args {\n\tstruct nfs4_sequence_args seq_args;\n\tint style;\n};\n\nstruct nfs41_server_owner {\n\tuint64_t minor_id;\n\tuint32_t major_id_sz;\n\tchar major_id[1024];\n};\n\nstruct nfs41_server_scope {\n\tuint32_t server_scope_sz;\n\tchar server_scope[1024];\n};\n\nstruct nfs41_test_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs41_test_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfs42_layoutstat_devinfo;\n\nstruct nfs42_layoutstat_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tint num_dev;\n\tstruct nfs42_layoutstat_devinfo *devinfo;\n};\n\nstruct nfs4_xdr_opaque_ops;\n\nstruct nfs4_xdr_opaque_data {\n\tconst struct nfs4_xdr_opaque_ops *ops;\n\tvoid *data;\n};\n\nstruct nfs42_layoutstat_devinfo {\n\tstruct nfs4_deviceid dev_id;\n\t__u64 offset;\n\t__u64 length;\n\t__u64 read_count;\n\t__u64 read_bytes;\n\t__u64 write_count;\n\t__u64 write_bytes;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs4_accessargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tu32 access;\n};\n\nstruct nfs_server;\n\nstruct nfs4_accessres {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tu32 supported;\n\tu32 access;\n};\n\nstruct nfs4_add_xprt_data {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct nfs4_cached_acl {\n\tenum nfs4_acl_type type;\n\tint cached;\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct nfs4_call_sync_data {\n\tconst struct nfs_server *seq_server;\n\tstruct nfs4_sequence_args *seq_args;\n\tstruct nfs4_sequence_res *seq_res;\n};\n\nstruct nfs4_change_info {\n\tu32 atomic;\n\tu64 before;\n\tu64 after;\n};\n\nstruct nfs_seqid;\n\nstruct nfs4_layoutreturn_args;\n\nstruct nfs_closeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n\tfmode_t fmode;\n\tu32 share_access;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs4_layoutreturn_res;\n\nstruct nfs_closeres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct pnfs_layout_hdr;\n\nstruct nfs4_layoutreturn_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_layout_hdr *layout;\n\tstruct inode *inode;\n\tstruct pnfs_layout_range range;\n\tnfs4_stateid stateid;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data *ld_private;\n};\n\nstruct nfs4_layoutreturn_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 lrs_present;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_state;\n\nstruct nfs4_closedata {\n\tstruct inode *inode;\n\tstruct nfs4_state *state;\n\tstruct nfs_closeargs arg;\n\tstruct nfs_closeres res;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs_write_verifier {\n\tchar data[8];\n};\n\nstruct nfs_writeverf {\n\tstruct nfs_write_verifier verifier;\n\tenum nfs3_stable_how committed;\n};\n\nstruct nfs4_copy_state {\n\tstruct list_head copies;\n\tstruct list_head src_copies;\n\tnfs4_stateid stateid;\n\tstruct completion completion;\n\tuint64_t count;\n\tstruct nfs_writeverf verf;\n\tint error;\n\tint flags;\n\tstruct nfs4_state *parent_src_state;\n\tstruct nfs4_state *parent_dst_state;\n};\n\nstruct nfs4_create_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tu32 ftype;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page **pages;\n\t\t\tunsigned int len;\n\t\t} symlink;\n\t\tstruct {\n\t\t\tu32 specdata1;\n\t\t\tu32 specdata2;\n\t\t} device;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst struct iattr *attrs;\n\tconst struct nfs_fh *dir_fh;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n};\n\nstruct nfs4_create_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info dir_cinfo;\n};\n\nstruct nfs4_createdata {\n\tstruct rpc_message msg;\n\tstruct nfs4_create_arg arg;\n\tstruct nfs4_create_res res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n};\n\nstruct nfs4_delegattr {\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tbool atime_set;\n\tbool mtime_set;\n};\n\nstruct nfs4_delegreturnargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fhandle;\n\tconst nfs4_stateid *stateid;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n\tstruct nfs4_delegattr *sattr_args;\n};\n\nstruct nfs4_delegreturnres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n\tbool sattr_res;\n\tint sattr_ret;\n};\n\nstruct nfs4_delegreturndata {\n\tstruct nfs4_delegreturnargs args;\n\tstruct nfs4_delegreturnres res;\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs4_delegattr sattr;\n\tstruct nfs_fattr fattr;\n\tint rpc_status;\n\tstruct inode *inode;\n};\n\nstruct pnfs_layoutdriver_type;\n\nstruct nfs4_deviceid_node {\n\tstruct hlist_node node;\n\tstruct hlist_node tmpnode;\n\tconst struct pnfs_layoutdriver_type *ld;\n\tconst struct nfs_client *nfs_client;\n\tlong unsigned int flags;\n\tlong unsigned int timestamp_unavailable;\n\tstruct nfs4_deviceid deviceid;\n\tstruct callback_head rcu;\n\tatomic_t ref;\n};\n\nstruct nfs4_ds_server {\n\tstruct list_head list;\n\tstruct rpc_clnt *rpc_clnt;\n};\n\nstruct nfs4_exception {\n\tstruct nfs4_state *state;\n\tstruct inode *inode;\n\tnfs4_stateid *stateid;\n\tlong int timeout;\n\tshort unsigned int retrans;\n\tunsigned char task_is_privileged: 1;\n\tunsigned char delay: 1;\n\tunsigned char recovering: 1;\n\tunsigned char retry: 1;\n\tbool interruptible;\n};\n\nstruct nfs4_ff_busy_timer {\n\tktime_t start_time;\n\tatomic_t n_ops;\n};\n\nstruct nfs4_ff_ds_version {\n\tu32 version;\n\tu32 minor_version;\n\tu32 rsize;\n\tu32 wsize;\n\tbool tightly_coupled;\n};\n\nstruct nfs4_ff_io_stat {\n\t__u64 ops_requested;\n\t__u64 bytes_requested;\n\t__u64 ops_completed;\n\t__u64 bytes_completed;\n\t__u64 bytes_not_delivered;\n\tktime_t total_busy_time;\n\tktime_t aggregate_completion_time;\n};\n\nstruct nfs4_pnfs_ds;\n\nstruct nfs4_ff_layout_ds {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 ds_versions_cnt;\n\tstruct nfs4_ff_ds_version *ds_versions;\n\tstruct nfs4_pnfs_ds *ds;\n};\n\nstruct nfs4_ff_layout_ds_err {\n\tstruct list_head list;\n\tu64 offset;\n\tu64 length;\n\tint status;\n\tenum nfs_opnum4 opnum;\n\tnfs4_stateid stateid;\n\tstruct nfs4_deviceid deviceid;\n};\n\nstruct nfsd_file;\n\nstruct nfs_file_localio {\n\tstruct nfsd_file *ro_file;\n\tstruct nfsd_file *rw_file;\n\tstruct list_head list;\n\tvoid *nfs_uuid;\n};\n\nstruct nfs4_ff_layoutstat {\n\tstruct nfs4_ff_io_stat io_stat;\n\tstruct nfs4_ff_busy_timer busy_timer;\n};\n\nstruct nfs4_ff_layout_mirror;\n\nstruct nfs4_ff_layout_ds_stripe {\n\tstruct nfs4_ff_layout_mirror *mirror;\n\tstruct nfs4_deviceid devid;\n\tu32 efficiency;\n\tstruct nfs4_ff_layout_ds *mirror_ds;\n\tu32 fh_versions_cnt;\n\tstruct nfs_fh *fh_versions;\n\tnfs4_stateid stateid;\n\tconst struct cred *ro_cred;\n\tconst struct cred *rw_cred;\n\tstruct nfs_file_localio nfl;\n\tstruct nfs4_ff_layoutstat read_stat;\n\tstruct nfs4_ff_layoutstat write_stat;\n\tktime_t start_time;\n};\n\nstruct nfs4_ff_layout_mirror {\n\tstruct pnfs_layout_hdr *layout;\n\tstruct list_head mirrors;\n\tu32 dss_count;\n\tstruct nfs4_ff_layout_ds_stripe *dss;\n\trefcount_t ref;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu32 report_interval;\n};\n\nstruct pnfs_layout_segment {\n\tstruct list_head pls_list;\n\tstruct list_head pls_lc_list;\n\tstruct list_head pls_commits;\n\tstruct pnfs_layout_range pls_range;\n\trefcount_t pls_refcount;\n\tu32 pls_seq;\n\tlong unsigned int pls_flags;\n\tstruct pnfs_layout_hdr *pls_layout;\n};\n\nstruct nfs4_ff_layout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu64 stripe_unit;\n\tu32 flags;\n\tu32 mirror_array_cnt;\n\tstruct nfs4_ff_layout_mirror *mirror_array[0];\n};\n\nstruct nfs4_file_layout_dsaddr {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 stripe_count;\n\tu8 *stripe_indices;\n\tu32 ds_num;\n\tstruct nfs4_pnfs_ds *ds_list[0];\n};\n\nstruct pnfs_layout_hdr {\n\trefcount_t plh_refcount;\n\tatomic_t plh_outstanding;\n\tstruct list_head plh_layouts;\n\tstruct list_head plh_bulk_destroy;\n\tstruct list_head plh_segs;\n\tstruct list_head plh_return_segs;\n\tlong unsigned int plh_block_lgets;\n\tlong unsigned int plh_retry_timestamp;\n\tlong unsigned int plh_flags;\n\tnfs4_stateid plh_stateid;\n\tu32 plh_barrier;\n\tu32 plh_return_seq;\n\tenum pnfs_iomode plh_return_iomode;\n\tloff_t plh_lwb;\n\tconst struct cred *plh_lc_cred;\n\tstruct inode *plh_inode;\n\tstruct callback_head plh_rcu;\n};\n\nstruct pnfs_commit_ops;\n\nstruct pnfs_ds_commit_info {\n\tstruct list_head commits;\n\tunsigned int nwritten;\n\tunsigned int ncommitting;\n\tconst struct pnfs_commit_ops *ops;\n};\n\nstruct nfs4_filelayout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n};\n\nstruct nfs4_filelayout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu32 stripe_type;\n\tu32 commit_through_mds;\n\tu32 stripe_unit;\n\tu32 first_stripe_index;\n\tu64 pattern_offset;\n\tstruct nfs4_deviceid deviceid;\n\tstruct nfs4_file_layout_dsaddr *dsaddr;\n\tunsigned int num_fh;\n\tstruct nfs_fh **fh_array;\n};\n\nstruct nfs4_flexfile_layout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tstruct list_head mirrors;\n\tstruct list_head error_list;\n\tktime_t last_report_time;\n};\n\nstruct nfs4_flexfile_layoutreturn_args {\n\tstruct list_head errors;\n\tstruct nfs42_layoutstat_devinfo devinfo[4];\n\tunsigned int num_errors;\n\tunsigned int num_dev;\n\tstruct page *pages[1];\n};\n\nstruct nfs4_string {\n\tunsigned int len;\n\tchar *data;\n};\n\nstruct nfs4_pathname {\n\tunsigned int ncomponents;\n\tstruct nfs4_string components[512];\n};\n\nstruct nfs4_fs_location {\n\tunsigned int nservers;\n\tstruct nfs4_string servers[10];\n\tstruct nfs4_pathname rootpath;\n};\n\nstruct nfs4_fs_locations {\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tstruct nfs4_pathname fs_path;\n\tint nlocations;\n\tstruct nfs4_fs_location locations[10];\n};\n\nstruct nfs4_fs_locations_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct nfs_fh *fh;\n\tconst struct qstr *name;\n\tstruct page *page;\n\tconst u32 *bitmask;\n\tclientid4 clientid;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fs_locations_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_fs_locations *fs_locations;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tclientid4 clientid;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fh *fh;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsinfo;\n\nstruct nfs4_fsinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsinfo *fsinfo;\n};\n\nstruct nfs4_gdd_res {\n\tu32 status;\n\tnfs4_stateid deleg;\n};\n\nstruct nfs4_get_lease_time_args {\n\tstruct nfs4_sequence_args la_seq_args;\n};\n\nstruct nfs4_get_lease_time_res;\n\nstruct nfs4_get_lease_time_data {\n\tstruct nfs4_get_lease_time_args *args;\n\tstruct nfs4_get_lease_time_res *res;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_get_lease_time_res {\n\tstruct nfs4_sequence_res lr_seq_res;\n\tstruct nfs_fsinfo *lr_fsinfo;\n};\n\nstruct nfs4_getattr_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tbool get_dir_deleg;\n};\n\nstruct nfs4_getattr_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_gdd_res *gdd_res;\n};\n\nstruct pnfs_device;\n\nstruct nfs4_getdeviceinfo_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_device *pdev;\n\t__u32 notify_types;\n};\n\nstruct nfs4_getdeviceinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct pnfs_device *pdev;\n\t__u32 notification;\n};\n\nstruct nfs4_label {\n\tuint32_t lfs;\n\tuint32_t pi;\n\tu32 lsmid;\n\tu32 len;\n\tchar *label;\n};\n\nstruct nfs4_layoutcommit_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n\t__u64 lastbytewritten;\n\tstruct inode *inode;\n\tconst u32 *bitmask;\n\tsize_t layoutupdate_len;\n\tstruct page *layoutupdate_page;\n\tstruct page **layoutupdate_pages;\n\t__be32 *start_p;\n};\n\nstruct rpc_wait {\n\tstruct list_head list;\n\tstruct list_head links;\n\tstruct list_head timer_list;\n};\n\nstruct rpc_call_ops;\n\nstruct rpc_xprt;\n\nstruct rpc_rqst;\n\nstruct rpc_task {\n\tatomic_t tk_count;\n\tint tk_status;\n\tstruct list_head tk_task;\n\tvoid (*tk_callback)(struct rpc_task *);\n\tvoid (*tk_action)(struct rpc_task *);\n\tlong unsigned int tk_timeout;\n\tlong unsigned int tk_runstate;\n\tstruct rpc_wait_queue *tk_waitqueue;\n\tunion {\n\t\tstruct work_struct tk_work;\n\t\tstruct rpc_wait tk_wait;\n\t} u;\n\tstruct rpc_message tk_msg;\n\tvoid *tk_calldata;\n\tconst struct rpc_call_ops *tk_ops;\n\tstruct rpc_clnt *tk_client;\n\tstruct rpc_xprt *tk_xprt;\n\tstruct rpc_cred *tk_op_cred;\n\tstruct rpc_rqst *tk_rqstp;\n\tstruct workqueue_struct *tk_workqueue;\n\tktime_t tk_start;\n\tpid_t tk_owner;\n\tint tk_rpc_status;\n\tshort unsigned int tk_flags;\n\tshort unsigned int tk_timeouts;\n\tshort unsigned int tk_pid;\n\tunsigned char tk_priority: 2;\n\tunsigned char tk_garb_retry: 2;\n\tunsigned char tk_cred_retry: 2;\n};\n\nstruct nfs4_layoutcommit_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tint status;\n};\n\nstruct nfs4_layoutcommit_data {\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct list_head lseg_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tstruct nfs4_layoutcommit_args args;\n\tstruct nfs4_layoutcommit_res res;\n};\n\nstruct nfs4_layoutdriver_data {\n\tstruct page **pages;\n\t__u32 pglen;\n\t__u32 len;\n};\n\nstruct nfs_open_context;\n\nstruct nfs4_layoutget_args {\n\tstruct nfs4_sequence_args seq_args;\n\t__u32 type;\n\tstruct pnfs_layout_range range;\n\t__u64 minlength;\n\t__u32 maxcount;\n\tstruct inode *inode;\n\tstruct nfs_open_context *ctx;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data layout;\n};\n\nstruct nfs4_layoutget_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint status;\n\t__u32 return_on_close;\n\tstruct pnfs_layout_range range;\n\t__u32 type;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data *layoutp;\n};\n\nstruct nfs4_layoutget {\n\tstruct nfs4_layoutget_args args;\n\tstruct nfs4_layoutget_res res;\n\tconst struct cred *cred;\n\tstruct pnfs_layout_hdr *lo;\n\tgfp_t gfp_flags;\n};\n\nstruct nfs4_layoutreturn {\n\tstruct nfs4_layoutreturn_args args;\n\tstruct nfs4_layoutreturn_res res;\n\tconst struct cred *cred;\n\tstruct nfs_client *clp;\n\tstruct inode *inode;\n\tint rpc_status;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs4_link_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_link_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *dir_attr;\n};\n\nstruct nfs_seqid_counter {\n\tktime_t create_time;\n\tu64 owner_id;\n\tint flags;\n\tu32 counter;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct rpc_wait_queue wait;\n};\n\nstruct nfs4_lock_state {\n\tstruct list_head ls_locks;\n\tstruct nfs4_state *ls_state;\n\tlong unsigned int ls_flags;\n\tstruct nfs_seqid_counter ls_seqid;\n\tnfs4_stateid ls_stateid;\n\trefcount_t ls_count;\n\tfl_owner_t ls_owner;\n};\n\nstruct nfs4_lock_waiter {\n\tstruct inode *inode;\n\tstruct nfs_lowner owner;\n\twait_queue_entry_t wait;\n};\n\nstruct nfs_lock_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *lock_seqid;\n\tnfs4_stateid lock_stateid;\n\tstruct nfs_seqid *open_seqid;\n\tnfs4_stateid open_stateid;\n\tstruct nfs_lowner lock_owner;\n\tunsigned char block: 1;\n\tunsigned char reclaim: 1;\n\tunsigned char new_lock: 1;\n\tunsigned char new_lock_owner: 1;\n};\n\nstruct nfs_lock_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *lock_seqid;\n\tstruct nfs_seqid *open_seqid;\n};\n\nstruct nfs4_lockdata {\n\tstruct nfs_lock_args arg;\n\tstruct nfs_lock_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct file_lock fl;\n\tlong unsigned int timestamp;\n\tint rpc_status;\n\tint cancelled;\n\tstruct nfs_server *server;\n};\n\nstruct nfs4_lookup_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookup_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_lookup_root_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_mig_recovery_ops {\n\tint (*get_locations)(struct nfs_server *, struct nfs_fh *, struct nfs4_fs_locations *, struct page *, const struct cred *);\n\tint (*fsid_present)(struct inode *, const struct cred *);\n};\n\nstruct nfs4_state_recovery_ops;\n\nstruct nfs4_state_maintenance_ops;\n\nstruct nfs4_minor_version_ops {\n\tu32 minor_version;\n\tunsigned int init_caps;\n\tint (*init_client)(struct nfs_client *);\n\tvoid (*shutdown_client)(struct nfs_client *);\n\tbool (*match_stateid)(const nfs4_stateid *, const nfs4_stateid *);\n\tint (*find_root_sec)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *);\n\tvoid (*free_lock_state)(struct nfs_server *, struct nfs4_lock_state *);\n\tint (*test_and_free_expired)(struct nfs_server *, nfs4_stateid *, const struct cred *);\n\tstruct nfs_seqid * (*alloc_seqid)(struct nfs_seqid_counter *, gfp_t);\n\tvoid (*session_trunk)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tconst struct rpc_call_ops *call_sync_ops;\n\tconst struct nfs4_sequence_slot_ops *sequence_slot_ops;\n\tconst struct nfs4_state_recovery_ops *reboot_recovery_ops;\n\tconst struct nfs4_state_recovery_ops *nograce_recovery_ops;\n\tconst struct nfs4_state_maintenance_ops *state_renewal_ops;\n\tconst struct nfs4_mig_recovery_ops *mig_recovery_ops;\n};\n\nstruct nfs_string {\n\tunsigned int len;\n\tconst char *data;\n};\n\nstruct nfs4_mount_data {\n\tint version;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct nfs_string client_addr;\n\tstruct nfs_string mnt_path;\n\tstruct nfs_string hostname;\n\tunsigned int host_addrlen;\n\tstruct sockaddr *host_addr;\n\tint proto;\n\tint auth_flavourlen;\n\tint *auth_flavours;\n};\n\nstruct nfs4_open_caps {\n\tu32 oa_share_access[1];\n\tu32 oa_share_deny[1];\n\tu32 oa_share_access_want[1];\n\tu32 oa_open_claim[1];\n\tu32 oa_createmode[1];\n};\n\nstruct nfs4_open_createattrs {\n\tstruct nfs4_label *label;\n\tstruct iattr *sattr;\n\tconst __u32 verf[2];\n};\n\nstruct nfs4_open_delegation {\n\t__u32 open_delegation_type;\n\tunion {\n\t\tstruct {\n\t\t\tfmode_t type;\n\t\t\t__u32 do_recall;\n\t\t\tnfs4_stateid stateid;\n\t\t\tlong unsigned int pagemod_limit;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 why_no_delegation;\n\t\t\t__u32 will_notify;\n\t\t};\n\t};\n};\n\nstruct stateowner_id {\n\t__u64 create_time;\n\t__u64 uniquifier;\n};\n\nstruct nfs_openargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct nfs_seqid *seqid;\n\tint open_flags;\n\tfmode_t fmode;\n\tu32 share_access;\n\tu32 access;\n\t__u64 clientid;\n\tstruct stateowner_id id;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iattr *attrs;\n\t\t\tnfs4_verifier verifier;\n\t\t};\n\t\tnfs4_stateid delegation;\n\t\t__u32 delegation_type;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst u32 *open_bitmap;\n\tenum open_claim_type4 claim;\n\tenum createmode4 createmode;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n\tstruct nfs4_layoutget_args *lg_args;\n};\n\nstruct nfs_openres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fh fh;\n\tstruct nfs4_change_info cinfo;\n\t__u32 rflags;\n\tstruct nfs_fattr *f_attr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\t__u32 attrset[3];\n\tstruct nfs4_string *owner;\n\tstruct nfs4_string *group_owner;\n\tstruct nfs4_open_delegation delegation;\n\t__u32 access_request;\n\t__u32 access_supported;\n\t__u32 access_result;\n\tstruct nfs4_layoutget_res *lg_res;\n};\n\nstruct nfs_open_confirmargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tnfs4_stateid *stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_open_confirmres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs4_state_owner;\n\nstruct nfs4_opendata {\n\tstruct kref kref;\n\tstruct nfs_openargs o_arg;\n\tstruct nfs_openres o_res;\n\tstruct nfs_open_confirmargs c_arg;\n\tstruct nfs_open_confirmres c_res;\n\tstruct nfs4_string owner_name;\n\tstruct nfs4_string group_name;\n\tstruct nfs4_label *a_label;\n\tstruct nfs_fattr f_attr;\n\tstruct dentry *dir;\n\tstruct dentry *dentry;\n\tstruct nfs4_state_owner *owner;\n\tstruct nfs4_state *state;\n\tstruct iattr attrs;\n\tstruct nfs4_layoutget *lgp;\n\tlong unsigned int timestamp;\n\tbool rpc_done;\n\tbool file_created;\n\tbool is_recover;\n\tbool cancelled;\n\tint rpc_status;\n};\n\nstruct nfs4_pathconf_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_pathconf;\n\nstruct nfs4_pathconf_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_pathconf *pathconf;\n};\n\nstruct nfs4_pnfs_ds {\n\tstruct list_head ds_node;\n\tchar *ds_remotestr;\n\tstruct list_head ds_addrs;\n\tconst struct net *ds_net;\n\tstruct nfs_client *ds_clp;\n\trefcount_t ds_count;\n\tlong unsigned int ds_state;\n};\n\nstruct nfs4_pnfs_ds_addr {\n\tstruct __kernel_sockaddr_storage da_addr;\n\tsize_t da_addrlen;\n\tstruct list_head da_node;\n\tchar *da_remotestr;\n\tconst char *da_netid;\n\tint da_transport;\n};\n\nstruct nfs4_readdir_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tu64 cookie;\n\tnfs4_verifier verifier;\n\tu32 count;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tconst u32 *bitmask;\n\tbool plus;\n};\n\nstruct nfs4_readdir_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_verifier verifier;\n\tunsigned int pgbase;\n};\n\nstruct nfs4_readlink {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs4_readlink_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_reclaim_complete_data {\n\tstruct nfs_client *clp;\n\tstruct nfs41_reclaim_complete_args arg;\n\tstruct nfs41_reclaim_complete_res res;\n};\n\nstruct rpcsec_gss_info {\n\tstruct rpcsec_gss_oid oid;\n\tu32 qop;\n\tu32 service;\n};\n\nstruct nfs4_secinfo4 {\n\tu32 flavor;\n\tstruct rpcsec_gss_info flavor_info;\n};\n\nstruct nfs4_secinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n};\n\nstruct nfs4_secinfo_flavors {\n\tunsigned int num_flavors;\n\tstruct nfs4_secinfo4 flavors[0];\n};\n\nstruct nfs4_secinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_secinfo_flavors *flavors;\n};\n\nstruct nfs4_sequence_data {\n\tstruct nfs_client *clp;\n\tstruct nfs4_sequence_args args;\n\tstruct nfs4_sequence_res res;\n};\n\nstruct nfs4_sequence_slot_ops {\n\tint (*process)(struct rpc_task *, struct nfs4_sequence_res *);\n\tint (*done)(struct rpc_task *, struct nfs4_sequence_res *);\n\tvoid (*free_slot)(struct nfs4_sequence_res *);\n};\n\nstruct nfs4_server_caps_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fhandle;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_server_caps_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 attr_bitmask[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 has_links;\n\tu32 has_symlinks;\n\tu32 fh_expire_type;\n\tu32 case_insensitive;\n\tu32 case_preserving;\n\tstruct nfs4_open_caps open_caps;\n};\n\nstruct nfs4_session;\n\nstruct nfs4_slot_table {\n\tstruct nfs4_session *session;\n\tstruct nfs4_slot *slots;\n\tlong unsigned int used_slots[16];\n\tspinlock_t slot_tbl_lock;\n\tstruct rpc_wait_queue slot_tbl_waitq;\n\twait_queue_head_t slot_waitq;\n\tu32 max_slots;\n\tu32 max_slotid;\n\tu32 highest_used_slotid;\n\tu32 target_highest_slotid;\n\tu32 server_highest_slotid;\n\ts32 d_target_highest_slotid;\n\ts32 d2_target_highest_slotid;\n\tlong unsigned int generation;\n\tstruct completion complete;\n\tlong unsigned int slot_tbl_state;\n};\n\nstruct nfs4_session {\n\tstruct nfs4_sessionid sess_id;\n\tu32 flags;\n\tlong unsigned int session_state;\n\tu32 hash_alg;\n\tu32 ssv_len;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_slot_table fc_slot_table;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tstruct nfs4_slot_table bc_slot_table;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_setclientid {\n\tconst nfs4_verifier *sc_verifier;\n\tu32 sc_prog;\n\tunsigned int sc_netid_len;\n\tchar sc_netid[6];\n\tunsigned int sc_uaddr_len;\n\tchar sc_uaddr[58];\n\tstruct nfs_client *sc_clnt;\n\tstruct rpc_cred *sc_cred;\n};\n\nstruct nfs4_setclientid_res {\n\tu64 clientid;\n\tnfs4_verifier confirm;\n};\n\nstruct nfs4_slot {\n\tstruct nfs4_slot_table *table;\n\tstruct nfs4_slot *next;\n\tlong unsigned int generation;\n\tu32 slot_nr;\n\tu32 seq_nr;\n\tu32 seq_nr_last_acked;\n\tu32 seq_nr_highest_sent;\n\tunsigned int privileged: 1;\n\tunsigned int seq_done: 1;\n};\n\nstruct nfs4_state {\n\tstruct list_head open_states;\n\tstruct list_head inode_states;\n\tstruct list_head lock_states;\n\tstruct nfs4_state_owner *owner;\n\tstruct inode *inode;\n\tlong unsigned int flags;\n\tspinlock_t state_lock;\n\tseqlock_t seqlock;\n\tnfs4_stateid stateid;\n\tnfs4_stateid open_stateid;\n\tunsigned int n_rdonly;\n\tunsigned int n_wronly;\n\tunsigned int n_rdwr;\n\tfmode_t state;\n\trefcount_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs4_state_maintenance_ops {\n\tint (*sched_state_renewal)(struct nfs_client *, const struct cred *, unsigned int);\n\tconst struct cred * (*get_state_renewal_cred)(struct nfs_client *);\n\tint (*renew_lease)(struct nfs_client *, const struct cred *);\n};\n\nstruct nfs4_state_owner {\n\tstruct nfs_server *so_server;\n\tstruct list_head so_lru;\n\tlong unsigned int so_expires;\n\tstruct rb_node so_server_node;\n\tconst struct cred *so_cred;\n\tspinlock_t so_lock;\n\tatomic_t so_count;\n\tlong unsigned int so_flags;\n\tstruct list_head so_states;\n\tstruct nfs_seqid_counter so_seqid;\n\tstruct mutex so_delegreturn_mutex;\n};\n\nstruct nfs4_state_recovery_ops {\n\tint owner_flag_bit;\n\tint state_flag_bit;\n\tint (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);\n\tint (*recover_lock)(struct nfs4_state *, struct file_lock *);\n\tint (*establish_clid)(struct nfs_client *, const struct cred *);\n\tint (*reclaim_complete)(struct nfs_client *, const struct cred *);\n\tint (*detect_trunking)(struct nfs_client *, struct nfs_client **, const struct cred *);\n};\n\nstruct nfs4_statfs_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsstat;\n\nstruct nfs4_statfs_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsstat *fsstat;\n};\n\nstruct nfs4_threshold {\n\t__u32 bm;\n\t__u32 l_type;\n\t__u64 rd_sz;\n\t__u64 wr_sz;\n\t__u64 rd_io_sz;\n\t__u64 wr_io_sz;\n};\n\nstruct nfs_locku_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *seqid;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs_locku_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_lock_context;\n\nstruct nfs4_unlockdata {\n\tstruct nfs_locku_args arg;\n\tstruct nfs_locku_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct file_lock fl;\n\tstruct nfs_server *server;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_xdr_opaque_ops {\n\tvoid (*encode)(struct xdr_stream *, const void *, const struct nfs4_xdr_opaque_data *);\n\tvoid (*free)(struct nfs4_xdr_opaque_data *);\n};\n\nstruct nfs_access_entry {\n\tstruct rb_node rb_node;\n\tstruct list_head lru;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tstruct group_info *group_info;\n\tu64 timestamp;\n\t__u32 mask;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_auth_info {\n\tunsigned int flavor_len;\n\trpc_authflavor_t flavors[12];\n};\n\nstruct nfs_cache_array_entry {\n\tu64 cookie;\n\tu64 ino;\n\tconst char *name;\n\tunsigned int name_len;\n\tunsigned char d_type;\n};\n\nstruct nfs_cache_array {\n\tu64 change_attr;\n\tu64 last_cookie;\n\tunsigned int size;\n\tunsigned char folio_full: 1;\n\tunsigned char folio_is_eof: 1;\n\tunsigned char cookies_are_ordered: 1;\n\tstruct nfs_cache_array_entry array[0];\n};\n\nstruct svc_serv;\n\nstruct nfs_callback_data {\n\tunsigned int users;\n\tstruct svc_serv *serv;\n};\n\nstruct xprtsec_parms {\n\tenum xprtsec_policies policy;\n\tkey_serial_t cert_serial;\n\tkey_serial_t privkey_serial;\n};\n\nstruct nfs_rpc_ops;\n\nstruct nfs_subversion;\n\nstruct nfs_client {\n\trefcount_t cl_count;\n\tatomic_t cl_mds_count;\n\tint cl_cons_state;\n\tlong unsigned int cl_res_state;\n\tlong unsigned int cl_flags;\n\tstruct __kernel_sockaddr_storage cl_addr;\n\tsize_t cl_addrlen;\n\tchar *cl_hostname;\n\tchar *cl_acceptor;\n\tstruct list_head cl_share_link;\n\tstruct list_head cl_superblocks;\n\tstruct rpc_clnt *cl_rpcclient;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tint cl_proto;\n\tstruct nfs_subversion *cl_nfs_mod;\n\tu32 cl_minorversion;\n\tunsigned int cl_nconnect;\n\tunsigned int cl_max_connect;\n\tconst char *cl_principal;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct list_head cl_ds_clients;\n\tu64 cl_clientid;\n\tnfs4_verifier cl_confirm;\n\tlong unsigned int cl_state;\n\tspinlock_t cl_lock;\n\tlong unsigned int cl_lease_time;\n\tlong unsigned int cl_last_renewal;\n\tstruct delayed_work cl_renewd;\n\tstruct rpc_wait_queue cl_rpcwaitq;\n\tstruct idmap *cl_idmap;\n\tconst char *cl_owner_id;\n\tu32 cl_cb_ident;\n\tconst struct nfs4_minor_version_ops *cl_mvops;\n\tlong unsigned int cl_mig_gen;\n\tstruct nfs4_slot_table *cl_slot_tbl;\n\tu32 cl_seqid;\n\tu32 cl_exchange_flags;\n\tstruct nfs4_session *cl_session;\n\tbool cl_preserve_clid;\n\tstruct nfs41_server_owner *cl_serverowner;\n\tstruct nfs41_server_scope *cl_serverscope;\n\tstruct nfs41_impl_id *cl_implid;\n\tlong unsigned int cl_sp4_flags;\n\twait_queue_head_t cl_lock_waitq;\n\tchar cl_ipaddr[48];\n\tstruct net *cl_net;\n\tnetns_tracker cl_ns_tracker;\n\tstruct list_head pending_cb_stateids;\n\tstruct callback_head rcu;\n};\n\nstruct rpc_timeout;\n\nstruct nfs_client_initdata {\n\tlong unsigned int init_flags;\n\tconst char *hostname;\n\tconst struct __kernel_sockaddr_storage *addr;\n\tconst char *nodename;\n\tconst char *ip_addr;\n\tsize_t addrlen;\n\tstruct nfs_subversion *nfs_mod;\n\tint proto;\n\tu32 minorversion;\n\tunsigned int nconnect;\n\tunsigned int max_connect;\n\tstruct net *net;\n\tconst struct rpc_timeout *timeparms;\n\tconst struct cred *cred;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct nfs_clone_mount {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_commit_data;\n\nstruct nfs_commit_info;\n\nstruct nfs_page;\n\nstruct nfs_commit_completion_ops {\n\tvoid (*completion)(struct nfs_commit_data *);\n\tvoid (*resched_write)(struct nfs_commit_info *, struct nfs_page *);\n};\n\nstruct nfs_commitargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\t__u64 offset;\n\t__u32 count;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_commitres {\n\tstruct nfs4_sequence_res seq_res;\n\t__u32 op_status;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_writeverf *verf;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs_direct_req;\n\nstruct nfs_commit_data {\n\tstruct rpc_task task;\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_writeverf verf;\n\tstruct list_head pages;\n\tstruct list_head list;\n\tstruct nfs_direct_req *dreq;\n\tstruct nfs_commitargs args;\n\tstruct nfs_commitres res;\n\tstruct nfs_open_context *context;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_index;\n\tloff_t lwb;\n\tconst struct rpc_call_ops *mds_ops;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n\tint (*commit_done_cb)(struct rpc_task *, struct nfs_commit_data *);\n\tlong unsigned int flags;\n};\n\nstruct nfs_mds_commit_info;\n\nstruct nfs_commit_info {\n\tstruct inode *inode;\n\tstruct nfs_mds_commit_info *mds;\n\tstruct pnfs_ds_commit_info *ds;\n\tstruct nfs_direct_req *dreq;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n};\n\nstruct nfs_delegation {\n\tstruct hlist_node hash;\n\tstruct list_head super_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tfmode_t type;\n\tlong unsigned int pagemod_limit;\n\t__u64 change_attr;\n\tlong unsigned int test_gen;\n\tlong unsigned int flags;\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_mds_commit_info {\n\tatomic_t rpcs_out;\n\tatomic_long_t ncommit;\n\tstruct list_head list;\n};\n\nstruct nfs_direct_req {\n\tstruct kref kref;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct kiocb *iocb;\n\tstruct inode *inode;\n\tatomic_t io_count;\n\tspinlock_t lock;\n\tloff_t io_start;\n\tssize_t count;\n\tssize_t max_count;\n\tssize_t error;\n\tstruct completion completion;\n\tstruct nfs_mds_commit_info mds_cinfo;\n\tstruct pnfs_ds_commit_info ds_cinfo;\n\tstruct work_struct work;\n\tint flags;\n};\n\nstruct nfs_entry {\n\t__u64 ino;\n\t__u64 cookie;\n\tconst char *name;\n\tunsigned int len;\n\tint eof;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tunsigned char d_type;\n\tstruct nfs_server *server;\n};\n\nstruct nfs_find_desc {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_free_stateid_data {\n\tstruct nfs_server *server;\n\tstruct nfs41_free_stateid_args args;\n\tstruct nfs41_free_stateid_res res;\n};\n\nstruct nfs_fs_context {\n\tbool internal;\n\tbool skip_reconfig_option_check;\n\tbool need_mount;\n\tbool sloppy;\n\tunsigned int flags;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tunsigned int timeo;\n\tunsigned int retrans;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namlen;\n\tunsigned int options;\n\tunsigned int bsize;\n\tstruct nfs_auth_info auth_info;\n\trpc_authflavor_t selected_flavor;\n\tstruct xprtsec_parms xprtsec;\n\tchar *client_address;\n\tunsigned int version;\n\tunsigned int minorversion;\n\tchar *fscache_uniq;\n\tshort unsigned int protofamily;\n\tshort unsigned int mountfamily;\n\tbool has_sec_mnt_opts;\n\tint lock_status;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tu32 version;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t} mount_server;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tchar *export_path;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t\tshort unsigned int nconnect;\n\t\tshort unsigned int max_connect;\n\t\tshort unsigned int export_path_len;\n\t} nfs_server;\n\tstruct nfs_fh *mntfh;\n\tstruct nfs_server *server;\n\tstruct nfs_subversion *nfs_mod;\n\tstruct nfs_clone_mount clone_data;\n};\n\nstruct nfs_fsinfo {\n\tstruct nfs_fattr *fattr;\n\t__u32 rtmax;\n\t__u32 rtpref;\n\t__u32 rtmult;\n\t__u32 wtmax;\n\t__u32 wtpref;\n\t__u32 wtmult;\n\t__u32 dtpref;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\t__u32 lease_time;\n\t__u32 nlayouttypes;\n\t__u32 layouttype[8];\n\t__u32 blksize;\n\t__u32 clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\t__u32 xattr_support;\n};\n\nstruct nfs_fsstat {\n\tstruct nfs_fattr *fattr;\n\t__u64 tbytes;\n\t__u64 fbytes;\n\t__u64 abytes;\n\t__u64 tfiles;\n\t__u64 ffiles;\n\t__u64 afiles;\n};\n\nstruct nfs_getaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_getaclres {\n\tstruct nfs4_sequence_res seq_res;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tsize_t acl_data_offset;\n\tint acl_flags;\n\tstruct folio *acl_scratch;\n};\n\nstruct nfs_inode {\n\t__u64 fileid;\n\tstruct nfs_fh fh;\n\tlong unsigned int flags;\n\tlong unsigned int cache_validity;\n\tstruct timespec64 btime;\n\tlong unsigned int read_cache_jiffies;\n\tlong unsigned int attrtimeo;\n\tlong unsigned int attrtimeo_timestamp;\n\tlong unsigned int attr_gencount;\n\tstruct rb_root access_cache;\n\tstruct list_head access_cache_entry_lru;\n\tstruct list_head access_cache_inode_lru;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int cache_change_attribute;\n\t\t\t__be32 cookieverf[2];\n\t\t\tstruct rw_semaphore rmdir_sem;\n\t\t};\n\t\tstruct {\n\t\t\tatomic_long_t nrequests;\n\t\t\tatomic_long_t redirtied_pages;\n\t\t\tstruct nfs_mds_commit_info commit_info;\n\t\t\tstruct mutex commit_mutex;\n\t\t};\n\t};\n\tstruct list_head open_files;\n\tstruct {\n\t\tint cnt;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 end;\n\t\t} gap[16];\n\t} *ooo;\n\tstruct nfs4_cached_acl *nfs4_acl;\n\tstruct list_head open_states;\n\tstruct nfs_delegation *delegation;\n\tstruct rw_semaphore rwsem;\n\tstruct pnfs_layout_hdr *layout;\n\t__u64 write_io;\n\t__u64 read_io;\n\tunion {\n\t\tstruct inode vfs_inode;\n\t};\n};\n\nstruct nfs_io_completion {\n\tvoid (*complete)(void *);\n\tvoid *data;\n\tstruct kref refcount;\n};\n\nstruct nfs_iostats {\n\tlong long unsigned int bytes[8];\n\tlong unsigned int events[27];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nfs_lock_context {\n\trefcount_t count;\n\tstruct list_head list;\n\tstruct nfs_open_context *open_context;\n\tfl_owner_t lockowner;\n\tatomic_t io_count;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_lockt_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_lockt_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct file_lock *denied;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct nfs_mount_data {\n\tint version;\n\tint fd;\n\tstruct nfs2_fh old_root;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct sockaddr_in addr;\n\tchar hostname[256];\n\tint namlen;\n\tunsigned int bsize;\n\tstruct nfs3_fh root;\n\tint pseudoflavor;\n\tchar context[257];\n};\n\nstruct nfs_mount_request {\n\tstruct __kernel_sockaddr_storage *sap;\n\tsize_t salen;\n\tchar *hostname;\n\tchar *dirpath;\n\tu32 version;\n\tshort unsigned int protocol;\n\tstruct nfs_fh *fh;\n\tint noresvport;\n\tunsigned int *auth_flav_len;\n\trpc_authflavor_t *auth_flavs;\n\tstruct net *net;\n};\n\nstruct rpc_program;\n\nstruct rpc_stat {\n\tconst struct rpc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int netreconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcretrans;\n\tunsigned int rpcauthrefresh;\n\tunsigned int rpcgarbage;\n};\n\nstruct nfs_netns_client;\n\nstruct nfs_net {\n\tstruct cache_detail *nfs_dns_resolve;\n\tstruct rpc_pipe *bl_device_pipe;\n\tstruct bl_dev_msg bl_mount_reply;\n\twait_queue_head_t bl_wq;\n\tstruct mutex bl_mutex;\n\tstruct list_head nfs_client_list;\n\tstruct list_head nfs_volume_list;\n\tstruct idr cb_ident_idr;\n\tshort unsigned int nfs_callback_tcpport;\n\tshort unsigned int nfs_callback_tcpport6;\n\tint cb_users[2];\n\tstruct list_head nfs4_data_server_cache;\n\tspinlock_t nfs4_data_server_lock;\n\tstruct nfs_netns_client *nfs_client;\n\tspinlock_t nfs_client_lock;\n\tktime_t boot_time;\n\tstruct rpc_stat rpcstats;\n\tstruct proc_dir_entry *proc_nfsfs;\n};\n\nstruct nfs_netns_client {\n\tstruct kobject kobject;\n\tstruct kobject nfs_net_kobj;\n\tstruct net *net;\n\tconst char *identifier;\n};\n\nstruct nfs_open_context {\n\tstruct nfs_lock_context lock_context;\n\tfl_owner_t flock_owner;\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\tstruct rpc_cred *ll_cred;\n\tstruct nfs4_state *state;\n\tfmode_t mode;\n\tint error;\n\tlong unsigned int flags;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tstruct nfs_file_localio nfl;\n};\n\nstruct nfs_open_dir_context {\n\tstruct list_head list;\n\tatomic_t cache_hits;\n\tatomic_t cache_misses;\n\tlong unsigned int attr_gencount;\n\t__be32 verf[2];\n\t__u64 dir_cookie;\n\t__u64 last_cookie;\n\tlong unsigned int page_index;\n\tunsigned int dtsize;\n\tbool force_clear;\n\tbool eof;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_page {\n\tstruct list_head wb_list;\n\tunion {\n\t\tstruct page *wb_page;\n\t\tstruct folio *wb_folio;\n\t};\n\tstruct nfs_lock_context *wb_lock_context;\n\tlong unsigned int wb_index;\n\tunsigned int wb_offset;\n\tunsigned int wb_pgbase;\n\tunsigned int wb_bytes;\n\tstruct kref wb_kref;\n\tlong unsigned int wb_flags;\n\tstruct nfs_write_verifier wb_verf;\n\tstruct nfs_page *wb_this_page;\n\tstruct nfs_page *wb_head;\n\tshort unsigned int wb_nio;\n};\n\nstruct nfs_page_array {\n\tstruct page **pagevec;\n\tunsigned int npages;\n\tstruct page *page_array[8];\n};\n\nstruct nfs_page_iter_page {\n\tconst struct nfs_page *req;\n\tsize_t count;\n};\n\nstruct nfs_pgio_mirror {\n\tstruct list_head pg_list;\n\tlong unsigned int pg_bytes_written;\n\tsize_t pg_count;\n\tsize_t pg_bsize;\n\tunsigned int pg_base;\n\tunsigned char pg_recoalesce: 1;\n};\n\nstruct nfs_pageio_ops;\n\nstruct nfs_rw_ops;\n\nstruct nfs_pgio_completion_ops;\n\nstruct nfs_pageio_descriptor {\n\tstruct inode *pg_inode;\n\tconst struct nfs_pageio_ops *pg_ops;\n\tconst struct nfs_rw_ops *pg_rw_ops;\n\tint pg_ioflags;\n\tint pg_error;\n\tconst struct rpc_call_ops *pg_rpc_callops;\n\tconst struct nfs_pgio_completion_ops *pg_completion_ops;\n\tstruct pnfs_layout_segment *pg_lseg;\n\tstruct nfs_io_completion *pg_io_completion;\n\tstruct nfs_direct_req *pg_dreq;\n\tunsigned int pg_bsize;\n\tu32 pg_mirror_count;\n\tstruct nfs_pgio_mirror *pg_mirrors;\n\tstruct nfs_pgio_mirror pg_mirrors_static[1];\n\tstruct nfs_pgio_mirror *pg_mirrors_dynamic;\n\tu32 pg_mirror_idx;\n\tshort unsigned int pg_maxretrans;\n\tunsigned char pg_moreio: 1;\n};\n\nstruct nfs_pageio_ops {\n\tvoid (*pg_init)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tsize_t (*pg_test)(struct nfs_pageio_descriptor *, struct nfs_page *, struct nfs_page *);\n\tint (*pg_doio)(struct nfs_pageio_descriptor *);\n\tunsigned int (*pg_get_mirror_count)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tvoid (*pg_cleanup)(struct nfs_pageio_descriptor *);\n\tstruct nfs_pgio_mirror * (*pg_get_mirror)(struct nfs_pageio_descriptor *, u32);\n\tu32 (*pg_set_mirror)(struct nfs_pageio_descriptor *, u32);\n};\n\nstruct nfs_pathconf {\n\tstruct nfs_fattr *fattr;\n\t__u32 max_link;\n\t__u32 max_namelen;\n};\n\nstruct nfs_pgio_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct nfs_open_context *context;\n\tstruct nfs_lock_context *lock_context;\n\tnfs4_stateid stateid;\n\t__u64 offset;\n\t__u32 count;\n\tunsigned int pgbase;\n\tstruct page **pages;\n\tunion {\n\t\tunsigned int replen;\n\t\tstruct {\n\t\t\tconst u32 *bitmask;\n\t\t\tu32 bitmask_store[3];\n\t\t\tenum nfs3_stable_how stable;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header;\n\nstruct nfs_pgio_completion_ops {\n\tvoid (*error_cleanup)(struct list_head *, int);\n\tvoid (*init_hdr)(struct nfs_pgio_header *);\n\tvoid (*completion)(struct nfs_pgio_header *);\n\tvoid (*reschedule_io)(struct nfs_pgio_header *);\n};\n\nstruct nfs_pgio_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\t__u64 count;\n\t__u32 op_status;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int replen;\n\t\t\tint eof;\n\t\t\tvoid *scratch;\n\t\t};\n\t\tstruct {\n\t\t\tstruct nfs_writeverf *verf;\n\t\t\tconst struct nfs_server *server;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header {\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct list_head pages;\n\tstruct nfs_page *req;\n\tstruct nfs_writeverf verf;\n\tfmode_t rw_mode;\n\tstruct pnfs_layout_segment *lseg;\n\tloff_t io_start;\n\tconst struct rpc_call_ops *mds_ops;\n\tvoid (*release)(struct nfs_pgio_header *);\n\tconst struct nfs_pgio_completion_ops *completion_ops;\n\tconst struct nfs_rw_ops *rw_ops;\n\tstruct nfs_io_completion *io_completion;\n\tstruct nfs_direct_req *dreq;\n\tshort unsigned int retrans;\n\tint pnfs_error;\n\tint error;\n\tunsigned int good_bytes;\n\tlong unsigned int flags;\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_pgio_args args;\n\tstruct nfs_pgio_res res;\n\tlong unsigned int timestamp;\n\tint (*pgio_done_cb)(struct rpc_task *, struct nfs_pgio_header *);\n\t__u64 mds_offset;\n\tstruct nfs_page_array page_array;\n\tstruct nfs_client *ds_clp;\n\tu32 ds_commit_idx;\n\tu32 pgio_mirror_idx;\n};\n\nstruct nfs_readdir_arg {\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\t__be32 *verf;\n\tu64 cookie;\n\tstruct page **pages;\n\tunsigned int page_len;\n\tbool plus;\n};\n\nstruct nfs_readdir_descriptor {\n\tstruct file *file;\n\tstruct folio *folio;\n\tstruct dir_context *ctx;\n\tlong unsigned int folio_index;\n\tlong unsigned int folio_index_max;\n\tu64 dir_cookie;\n\tu64 last_cookie;\n\tloff_t current_index;\n\t__be32 verf[2];\n\tlong unsigned int dir_verifier;\n\tlong unsigned int timestamp;\n\tlong unsigned int gencount;\n\tlong unsigned int attr_gencount;\n\tunsigned int cache_entry_index;\n\tunsigned int buffer_fills;\n\tunsigned int dtsize;\n\tbool clear_cache;\n\tbool plus;\n\tbool eob;\n\tbool eof;\n};\n\nstruct nfs_readdir_res {\n\t__be32 *verf;\n};\n\nstruct nfs_referral_count {\n\tstruct list_head list;\n\tconst struct task_struct *task;\n\tunsigned int referral_count;\n};\n\nstruct nfs_removeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct qstr name;\n};\n\nstruct nfs_removeres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs_renameargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *old_dir;\n\tconst struct nfs_fh *new_dir;\n\tconst struct qstr *old_name;\n\tconst struct qstr *new_name;\n};\n\nstruct nfs_renameres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs4_change_info old_cinfo;\n\tstruct nfs_fattr *old_fattr;\n\tstruct nfs4_change_info new_cinfo;\n\tstruct nfs_fattr *new_fattr;\n};\n\nstruct nfs_renamedata {\n\tstruct nfs_renameargs args;\n\tstruct nfs_renameres res;\n\tstruct rpc_task task;\n\tconst struct cred *cred;\n\tstruct inode *old_dir;\n\tstruct dentry *old_dentry;\n\tstruct nfs_fattr old_fattr;\n\tstruct inode *new_dir;\n\tstruct dentry *new_dentry;\n\tstruct nfs_fattr new_fattr;\n\tvoid (*complete)(struct rpc_task *, struct nfs_renamedata *);\n\tlong int timeout;\n\tbool cancelled;\n};\n\nstruct nlmclnt_operations;\n\nstruct nfs_unlinkdata;\n\nstruct nfs_rpc_ops {\n\tu32 version;\n\tconst struct dentry_operations *dentry_ops;\n\tconst struct inode_operations *dir_inode_ops;\n\tconst struct inode_operations *file_inode_ops;\n\tconst struct file_operations *file_ops;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tint (*getroot)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*submount)(struct fs_context *, struct nfs_server *);\n\tint (*try_get_tree)(struct fs_context *);\n\tint (*getattr)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, struct inode *);\n\tint (*setattr)(struct dentry *, struct nfs_fattr *, struct iattr *);\n\tint (*lookup)(struct inode *, struct dentry *, const struct qstr *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*lookupp)(struct inode *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*access)(struct inode *, struct nfs_access_entry *, const struct cred *);\n\tint (*readlink)(struct inode *, struct page *, unsigned int, unsigned int);\n\tint (*create)(struct inode *, struct dentry *, struct iattr *, int);\n\tint (*remove)(struct inode *, struct dentry *);\n\tvoid (*unlink_setup)(struct rpc_message *, struct dentry *, struct inode *);\n\tvoid (*unlink_rpc_prepare)(struct rpc_task *, struct nfs_unlinkdata *);\n\tint (*unlink_done)(struct rpc_task *, struct inode *);\n\tvoid (*rename_setup)(struct rpc_message *, struct dentry *, struct dentry *, struct inode *);\n\tvoid (*rename_rpc_prepare)(struct rpc_task *, struct nfs_renamedata *);\n\tint (*rename_done)(struct rpc_task *, struct inode *, struct inode *);\n\tint (*link)(struct inode *, struct inode *, const struct qstr *);\n\tint (*symlink)(struct inode *, struct dentry *, struct folio *, unsigned int, struct iattr *);\n\tstruct dentry * (*mkdir)(struct inode *, struct dentry *, struct iattr *);\n\tint (*rmdir)(struct inode *, const struct qstr *);\n\tint (*readdir)(struct nfs_readdir_arg *, struct nfs_readdir_res *);\n\tint (*mknod)(struct inode *, struct dentry *, struct iattr *, dev_t);\n\tint (*statfs)(struct nfs_server *, struct nfs_fh *, struct nfs_fsstat *);\n\tint (*fsinfo)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*pathconf)(struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *);\n\tint (*set_capabilities)(struct nfs_server *, struct nfs_fh *);\n\tint (*decode_dirent)(struct xdr_stream *, struct nfs_entry *, bool);\n\tint (*pgio_rpc_prepare)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*read_setup)(struct nfs_pgio_header *, struct rpc_message *);\n\tint (*read_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*write_setup)(struct nfs_pgio_header *, struct rpc_message *, struct rpc_clnt **);\n\tint (*write_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*commit_setup)(struct nfs_commit_data *, struct rpc_message *, struct rpc_clnt **);\n\tvoid (*commit_rpc_prepare)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*commit_done)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tint (*lock_check_bounds)(const struct file_lock *);\n\tvoid (*clear_acl_cache)(struct inode *);\n\tvoid (*close_context)(struct nfs_open_context *, int);\n\tstruct inode * (*open_context)(struct inode *, struct nfs_open_context *, int, struct iattr *, int *);\n\tint (*have_delegation)(struct inode *, fmode_t, int);\n\tvoid (*return_delegation)(struct inode *);\n\tstruct nfs_client * (*alloc_client)(const struct nfs_client_initdata *);\n\tstruct nfs_client * (*init_client)(struct nfs_client *, const struct nfs_client_initdata *);\n\tvoid (*free_client)(struct nfs_client *);\n\tstruct nfs_server * (*create_server)(struct fs_context *);\n\tstruct nfs_server * (*clone_server)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, rpc_authflavor_t);\n\tint (*discover_trunking)(struct nfs_server *, struct nfs_fh *);\n\tvoid (*enable_swap)(struct inode *);\n\tvoid (*disable_swap)(struct inode *);\n};\n\nstruct rpc_task_setup;\n\nstruct nfs_rw_ops {\n\tstruct nfs_pgio_header * (*rw_alloc_header)(void);\n\tvoid (*rw_free_header)(struct nfs_pgio_header *);\n\tint (*rw_done)(struct rpc_task *, struct nfs_pgio_header *, struct inode *);\n\tvoid (*rw_result)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*rw_initiate)(struct nfs_pgio_header *, struct rpc_message *, const struct nfs_rpc_ops *, struct rpc_task_setup *, int);\n};\n\nstruct nfs_seqid {\n\tstruct nfs_seqid_counter *sequence;\n\tstruct list_head list;\n\tstruct rpc_task *task;\n};\n\nstruct nlm_host;\n\nstruct nfs_server {\n\tstruct nfs_client *nfs_client;\n\tstruct list_head client_link;\n\tstruct list_head master_link;\n\tstruct rpc_clnt *client;\n\tstruct rpc_clnt *client_acl;\n\tstruct nlm_host *nlm_host;\n\tstruct nfs_iostats *io_stats;\n\twait_queue_head_t write_congestion_wait;\n\tatomic_long_t writeback;\n\tunsigned int write_congested;\n\tunsigned int flags;\n\tunsigned int automount_inherit;\n\tunsigned int caps;\n\t__u64 fattr_valid;\n\tunsigned int rsize;\n\tunsigned int rpages;\n\tunsigned int wsize;\n\tunsigned int wtmult;\n\tunsigned int dtsize;\n\tshort unsigned int port;\n\tunsigned int bsize;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namelen;\n\tunsigned int options;\n\tunsigned int clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\tstruct nfs_fsid fsid;\n\tint s_sysfs_id;\n\t__u64 maxfilesize;\n\tlong unsigned int mount_time;\n\tstruct super_block *super;\n\tdev_t s_dev;\n\tstruct nfs_auth_info auth_info;\n\tu32 fh_expire_type;\n\tu32 pnfs_blksize;\n\tu32 attr_bitmask[3];\n\tu32 attr_bitmask_nl[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 cache_consistency_bitmask[3];\n\tu32 acl_bitmask;\n\tstruct pnfs_layoutdriver_type *pnfs_curr_ld;\n\tstruct rpc_wait_queue roc_rpcwaitq;\n\tstruct rb_root state_owners;\n\tatomic64_t owner_ctr;\n\tstruct list_head state_owners_lru;\n\tstruct list_head layouts;\n\tstruct list_head delegations;\n\tspinlock_t delegations_lock;\n\tstruct list_head delegations_return;\n\tstruct list_head delegations_lru;\n\tstruct list_head delegations_delayed;\n\tatomic_long_t nr_active_delegations;\n\tunsigned int delegation_hash_mask;\n\tstruct hlist_head *delegation_hash_table;\n\tstruct list_head ss_copies;\n\tstruct list_head ss_src_copies;\n\tlong unsigned int delegation_flags;\n\tlong unsigned int delegation_gen;\n\tlong unsigned int mig_gen;\n\tlong unsigned int mig_status;\n\tvoid (*destroy)(struct nfs_server *);\n\tatomic_t active;\n\tstruct __kernel_sockaddr_storage mountd_address;\n\tsize_t mountd_addrlen;\n\tu32 mountd_version;\n\tshort unsigned int mountd_port;\n\tshort unsigned int mountd_protocol;\n\tstruct rpc_wait_queue uoc_rpcwaitq;\n\tunsigned int read_hdrsize;\n\tconst struct cred *cred;\n\tbool has_sec_mnt_opts;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_setaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_setaclres {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs_setattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct iattr *iap;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n};\n\nstruct nfs_setattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct rpc_version;\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct nfs_subversion {\n\tstruct module *owner;\n\tstruct file_system_type *nfs_fs;\n\tconst struct rpc_version *rpc_vers;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tconst struct super_operations *sops;\n\tconst struct xattr_handler * const *xattr;\n};\n\nstruct nfs_unlinkdata {\n\tstruct nfs_removeargs args;\n\tstruct nfs_removeres res;\n\tstruct dentry *dentry;\n\twait_queue_head_t wq;\n\tconst struct cred *cred;\n\tstruct nfs_fattr dir_attr;\n\tlong int timeout;\n};\n\nstruct xdr_array2_desc;\n\ntypedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *, void *);\n\nstruct xdr_array2_desc {\n\tunsigned int elem_size;\n\tunsigned int array_len;\n\tunsigned int array_maxlen;\n\txdr_xcode_elem_t xcode;\n};\n\nstruct nfsacl_decode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n};\n\nstruct nfsacl_encode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n\tint typeflag;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct nfsacl_simple_acl {\n\tstruct posix_acl_hdr acl;\n\tstruct posix_acl_entry ace[4];\n};\n\nstruct nft_ct_frag6_pernet {\n\tstruct ctl_table_header *nf_frag_frags_hdr;\n\tstruct fqdir *fqdir;\n};\n\nstruct nfulnl_instance {\n\tstruct hlist_node hlist;\n\tspinlock_t lock;\n\trefcount_t use;\n\tunsigned int qlen;\n\tstruct sk_buff *skb;\n\tstruct timer_list timer;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct user_namespace *peer_user_ns;\n\tu32 peer_portid;\n\tunsigned int flushtimeout;\n\tunsigned int nlbufsiz;\n\tunsigned int qthreshold;\n\tu_int32_t copy_range;\n\tu_int32_t seq;\n\tu_int16_t group_num;\n\tu_int16_t flags;\n\tu_int8_t copy_mode;\n\tstruct callback_head rcu;\n};\n\nstruct nfulnl_msg_config_cmd {\n\t__u8 command;\n};\n\nstruct nfulnl_msg_config_mode {\n\t__be32 copy_range;\n\t__u8 copy_mode;\n\t__u8 _pad;\n} __attribute__((packed));\n\nstruct nfulnl_msg_packet_hdr {\n\t__be16 hw_protocol;\n\t__u8 hook;\n\t__u8 _pad;\n};\n\nstruct nfulnl_msg_packet_hw {\n\t__be16 hw_addrlen;\n\t__u16 _pad;\n\t__u8 hw_addr[8];\n};\n\nstruct nfulnl_msg_packet_timestamp {\n\t__be64 sec;\n\t__be64 usec;\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhlt_specific_cfg {\n\tu32 size;\n\tu8 caps[0];\n};\n\nstruct nhlt_endpoint {\n\tu32 length;\n\tu8 linktype;\n\tu8 instance_id;\n\tu16 vendor_id;\n\tu16 device_id;\n\tu16 revision_id;\n\tu32 subsystem_id;\n\tu8 device_type;\n\tu8 direction;\n\tu8 virtual_bus_id;\n\tstruct nhlt_specific_cfg config;\n} __attribute__((packed));\n\nstruct nhlt_acpi_table {\n\tstruct acpi_table_header header;\n\tu8 endpoint_count;\n\tstruct nhlt_endpoint desc[0];\n} __attribute__((packed));\n\nstruct nhlt_device_specific_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n};\n\nstruct nhlt_dmic_array_config {\n\tstruct nhlt_device_specific_config device_config;\n\tu8 array_type;\n};\n\nstruct wav_fmt {\n\tu16 fmt_tag;\n\tu16 channels;\n\tu32 samples_per_sec;\n\tu32 avg_bytes_per_sec;\n\tu16 block_align;\n\tu16 bits_per_sample;\n\tu16 cb_size;\n} __attribute__((packed));\n\nunion samples {\n\tu16 valid_bits_per_sample;\n\tu16 samples_per_block;\n\tu16 reserved;\n};\n\nstruct wav_fmt_ext {\n\tstruct wav_fmt fmt;\n\tunion samples sample;\n\tu32 channel_mask;\n\tu8 sub_fmt[16];\n};\n\nstruct nhlt_fmt_cfg {\n\tstruct wav_fmt_ext fmt_ext;\n\tstruct nhlt_specific_cfg config;\n};\n\nstruct nhlt_fmt {\n\tu8 fmt_count;\n\tstruct nhlt_fmt_cfg fmt_config[0];\n} __attribute__((packed));\n\nstruct nhlt_vendor_dmic_array_config {\n\tstruct nhlt_dmic_array_config dmic_config;\n\tu8 nb_mics;\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct rfd {\n\t__le16 status;\n\t__le16 command;\n\t__le32 link;\n\t__le32 rbd;\n\t__le16 actual_size;\n\t__le16 size;\n};\n\nstruct param_range {\n\tu32 min;\n\tu32 max;\n\tu32 count;\n};\n\nstruct params {\n\tstruct param_range rfds;\n\tstruct param_range cbs;\n};\n\nstruct rx;\n\nstruct nic {\n\tu32 msg_enable;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tu16 (*mdio_ctrl)(struct nic *, u32, u32, u32, u16);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rx *rxs;\n\tstruct rx *rx_to_use;\n\tstruct rx *rx_to_clean;\n\tstruct rfd blank_rfd;\n\tenum ru_state ru_running;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t cb_lock;\n\tspinlock_t cmd_lock;\n\tstruct csr *csr;\n\tenum scb_cmd_lo cuc_cmd;\n\tunsigned int cbs_avail;\n\tstruct napi_struct napi;\n\tstruct cb *cbs;\n\tstruct cb *cb_to_use;\n\tstruct cb *cb_to_send;\n\tstruct cb *cb_to_clean;\n\t__le16 tx_command;\n\tlong: 64;\n\tlong: 64;\n\tenum {\n\t\tich = 1,\n\t\tpromiscuous = 2,\n\t\tmulticast_all = 4,\n\t\twol_magic = 8,\n\t\tich_10h_workaround = 16,\n\t} flags;\n\tenum mac mac;\n\tenum phy phy;\n\tstruct params params;\n\tstruct timer_list watchdog;\n\tstruct mii_if_info mii;\n\tstruct work_struct tx_timeout_task;\n\tenum loopback loopback;\n\tstruct mem *mem;\n\tdma_addr_t dma_addr;\n\tstruct dma_pool *cbs_pool;\n\tdma_addr_t cbs_dma_addr;\n\tu8 adaptive_ifs;\n\tu8 tx_threshold;\n\tu32 tx_frames;\n\tu32 tx_collisions;\n\tu32 tx_deferred;\n\tu32 tx_single_collisions;\n\tu32 tx_multiple_collisions;\n\tu32 tx_fc_pause;\n\tu32 tx_tco_frames;\n\tu32 rx_fc_pause;\n\tu32 rx_fc_unsupported;\n\tu32 rx_tco_frames;\n\tu32 rx_short_frame_errors;\n\tu32 rx_over_length_errors;\n\tu16 eeprom_wc;\n\t__le16 eeprom[256];\n\tspinlock_t mdio_lock;\n\tconst struct firmware *fw;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nl80211_bss_select_rssi_adjust {\n\t__u8 band;\n\t__s8 delta;\n};\n\nstruct nl80211_pattern_support {\n\t__u32 max_patterns;\n\t__u32 min_pattern_len;\n\t__u32 max_pattern_len;\n\t__u32 max_pkt_offset;\n};\n\nstruct nl80211_coalesce_rule_support {\n\t__u32 max_rules;\n\tstruct nl80211_pattern_support pat;\n\t__u32 max_delay;\n};\n\nstruct nl80211_dump_wiphy_state {\n\ts64 filter_wiphy;\n\tlong int start;\n\tlong int split_start;\n\tlong int band_start;\n\tlong int chan_start;\n\tlong int capa_start;\n\tbool split;\n};\n\nstruct nl80211_mlme_event {\n\tenum nl80211_commands cmd;\n\tconst u8 *buf;\n\tsize_t buf_len;\n\tint uapsd_queues;\n\tconst u8 *req_ies;\n\tsize_t req_ies_len;\n\tbool reconnect;\n};\n\nstruct nl80211_sta_flag_update {\n\t__u32 mask;\n\t__u32 set;\n};\n\nstruct nl80211_txrate_eht {\n\t__u16 mcs[16];\n};\n\nstruct nl80211_txrate_he {\n\t__u16 mcs[8];\n};\n\nstruct nl80211_txrate_vht {\n\t__u16 mcs[8];\n};\n\nstruct nl80211_vendor_cmd_info {\n\t__u32 vendor_id;\n\t__u32 subcmd;\n};\n\nstruct nl80211_wowlan_tcp_data_token_feature {\n\t__u32 min_len;\n\t__u32 max_len;\n\t__u32 bufsize;\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlm_cookie {\n\tunsigned char data[32];\n\tunsigned int len;\n};\n\nstruct nlm_lock {\n\tchar *caller;\n\tunsigned int len;\n\tstruct nfs_fh fh;\n\tstruct xdr_netobj oh;\n\tu32 svid;\n\tu64 lock_start;\n\tu64 lock_len;\n\tstruct file_lock fl;\n};\n\nstruct nlm_args {\n\tstruct nlm_cookie cookie;\n\tstruct nlm_lock lock;\n\tu32 block;\n\tu32 reclaim;\n\tu32 state;\n\tu32 monitor;\n\tu32 fsm_access;\n\tu32 fsm_mode;\n};\n\nstruct nlm_rqst;\n\nstruct nlm_file;\n\nstruct nlm_block {\n\tstruct kref b_count;\n\tstruct list_head b_list;\n\tstruct list_head b_flist;\n\tstruct nlm_rqst *b_call;\n\tstruct svc_serv *b_daemon;\n\tstruct nlm_host *b_host;\n\tlong unsigned int b_when;\n\tunsigned int b_id;\n\tunsigned char b_granted;\n\tstruct nlm_file *b_file;\n\tstruct cache_req *b_cache_req;\n\tstruct cache_deferred_req *b_deferred_req;\n\tunsigned int b_flags;\n};\n\nstruct nlm_share;\n\nstruct nlm_file {\n\tstruct hlist_node f_list;\n\tstruct nfs_fh f_handle;\n\tstruct file *f_file[2];\n\tstruct nlm_share *f_shares;\n\tstruct list_head f_blocks;\n\tunsigned int f_locks;\n\tunsigned int f_count;\n\tstruct mutex f_mutex;\n};\n\nstruct nsm_handle;\n\nstruct nlm_host {\n\tstruct hlist_node h_hash;\n\tstruct __kernel_sockaddr_storage h_addr;\n\tsize_t h_addrlen;\n\tstruct __kernel_sockaddr_storage h_srcaddr;\n\tsize_t h_srcaddrlen;\n\tstruct rpc_clnt *h_rpcclnt;\n\tchar *h_name;\n\tu32 h_version;\n\tshort unsigned int h_proto;\n\tshort unsigned int h_reclaiming: 1;\n\tshort unsigned int h_server: 1;\n\tshort unsigned int h_noresvport: 1;\n\tshort unsigned int h_inuse: 1;\n\twait_queue_head_t h_gracewait;\n\tstruct rw_semaphore h_rwsem;\n\tu32 h_state;\n\tu32 h_nsmstate;\n\tu32 h_pidcount;\n\trefcount_t h_count;\n\tstruct mutex h_mutex;\n\tlong unsigned int h_nextrebind;\n\tlong unsigned int h_expires;\n\tstruct list_head h_lockowners;\n\tspinlock_t h_lock;\n\tstruct list_head h_granted;\n\tstruct list_head h_reclaim;\n\tstruct nsm_handle *h_nsmhandle;\n\tchar *h_addrbuf;\n\tstruct net *net;\n\tconst struct cred *h_cred;\n\tchar nodename[65];\n\tconst struct nlmclnt_operations *h_nlmclnt_ops;\n};\n\nstruct nlm_lockowner {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct nlm_host *host;\n\tfl_owner_t owner;\n\tuint32_t pid;\n};\n\nstruct nlm_lookup_host_info {\n\tconst int server;\n\tconst struct sockaddr *sap;\n\tconst size_t salen;\n\tconst short unsigned int protocol;\n\tconst u32 version;\n\tconst char *hostname;\n\tconst size_t hostname_len;\n\tconst int noresvport;\n\tstruct net *net;\n\tconst struct cred *cred;\n};\n\nstruct nsm_private {\n\tunsigned char data[16];\n};\n\nstruct nlm_reboot {\n\tchar *mon;\n\tunsigned int len;\n\tu32 state;\n\tstruct nsm_private priv;\n};\n\nstruct nlm_res {\n\tstruct nlm_cookie cookie;\n\t__be32 status;\n\tstruct nlm_lock lock;\n};\n\nstruct nlm_rqst {\n\trefcount_t a_count;\n\tunsigned int a_flags;\n\tstruct nlm_host *a_host;\n\tstruct nlm_args a_args;\n\tstruct nlm_res a_res;\n\tstruct nlm_block *a_block;\n\tunsigned int a_retries;\n\tu8 a_owner[74];\n\tvoid *a_callback_data;\n};\n\nstruct nlm_share {\n\tstruct nlm_share *s_next;\n\tstruct nlm_host *s_host;\n\tstruct nlm_file *s_file;\n\tstruct xdr_netobj s_owner;\n\tu32 s_access;\n\tu32 s_mode;\n};\n\nstruct nlm_wait {\n\tstruct list_head b_list;\n\twait_queue_head_t b_wait;\n\tstruct nlm_host *b_host;\n\tstruct file_lock *b_lock;\n\t__be32 b_status;\n};\n\nstruct nlmclnt_initdata {\n\tconst char *hostname;\n\tconst struct sockaddr *address;\n\tsize_t addrlen;\n\tshort unsigned int protocol;\n\tu32 nfs_version;\n\tint noresvport;\n\tstruct net *net;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tconst struct cred *cred;\n};\n\nstruct nlmclnt_operations {\n\tvoid (*nlmclnt_alloc_call)(void *);\n\tbool (*nlmclnt_unlock_prepare)(struct rpc_task *, void *);\n\tvoid (*nlmclnt_release_call)(void *);\n};\n\nstruct nlmsg_perm {\n\tu16 nlmsg_type;\n\tu32 perm;\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nlmsvc_binding {\n\t__be32 (*fopen)(struct svc_rqst *, struct nfs_fh *, struct file **, int);\n\tvoid (*fclose)(struct file *);\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\ntypedef int (*nmi_handler_t)(unsigned int, struct pt_regs *);\n\nstruct nmi_desc {\n\traw_spinlock_t lock;\n\tnmi_handler_t emerg_handler;\n\tstruct list_head head;\n};\n\nstruct nmi_stats {\n\tunsigned int normal;\n\tunsigned int unknown;\n\tunsigned int external;\n\tunsigned int swallow;\n\tlong unsigned int recv_jiffies;\n\tlong unsigned int idt_seq;\n\tlong unsigned int idt_nmi_seq;\n\tlong unsigned int idt_ignored;\n\tatomic_long_t idt_calls;\n\tlong unsigned int idt_seq_snap;\n\tlong unsigned int idt_nmi_seq_snap;\n\tlong unsigned int idt_ignored_snap;\n\tlong int idt_calls_snap;\n};\n\nstruct nmiaction {\n\tstruct list_head list;\n\tnmi_handler_t handler;\n\tu64 max_duration;\n\tlong unsigned int flags;\n\tconst char *name;\n};\n\nstruct node {\n\tstruct device dev;\n\tstruct list_head access_list;\n};\n\nstruct node_access_nodes {\n\tstruct device dev;\n\tstruct list_head list_node;\n\tunsigned int access;\n};\n\nstruct node_attr {\n\tstruct device_attribute attr;\n\tenum node_states state;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_hstate {\n\tstruct kobject *hugepages_kobj;\n\tstruct kobject *hstate_kobjs[2];\n};\n\nstruct node_memory_type_map {\n\tstruct memory_dev_type *memtype;\n\tint map_count;\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct nodemask_scratch {\n\tnodemask_t mask1;\n\tnodemask_t mask2;\n};\n\nstruct nosave_region {\n\tstruct list_head list;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct ns2501_configuration {\n\tu8 sync;\n\tu8 conf;\n\tu8 syncb;\n\tu8 dither;\n\tu8 pll_a;\n\tu16 pll_b;\n\tu16 hstart;\n\tu16 hstop;\n\tu16 vstart;\n\tu16 vstop;\n\tu16 vsync;\n\tu16 vtotal;\n\tu16 hpos;\n\tu16 vpos;\n\tu16 voffs;\n\tu16 hscale;\n\tu16 vscale;\n};\n\nstruct ns2501_priv {\n\tbool quiet;\n\tconst struct ns2501_configuration *conf;\n};\n\nstruct ns2501_reg {\n\tu8 offset;\n\tu8 value;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct nsm_args {\n\tstruct nsm_private *priv;\n\tu32 prog;\n\tu32 vers;\n\tu32 proc;\n\tchar *mon_name;\n\tconst char *nodename;\n};\n\nstruct nsm_handle {\n\tstruct list_head sm_link;\n\trefcount_t sm_count;\n\tchar *sm_mon_name;\n\tchar *sm_name;\n\tstruct __kernel_sockaddr_storage sm_addr;\n\tsize_t sm_addrlen;\n\tunsigned int sm_monitored: 1;\n\tunsigned int sm_sticky: 1;\n\tstruct nsm_private sm_priv;\n\tchar sm_addrbuf[51];\n};\n\nstruct nsm_res {\n\tu32 status;\n\tu32 state;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n} __attribute__((packed));\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct ntrig_data {\n\t__u16 x;\n\t__u16 y;\n\t__u16 w;\n\t__u16 h;\n\t__u16 id;\n\tbool tipswitch;\n\tbool confidence;\n\tbool first_contact_touch;\n\tbool reading_mt;\n\t__u8 mt_footer[4];\n\t__u8 mt_foot_count;\n\t__s8 act_state;\n\t__s8 deactivate_slack;\n\t__s8 activate_slack;\n\t__u16 min_width;\n\t__u16 min_height;\n\t__u16 activation_width;\n\t__u16 activation_height;\n\t__u16 sensor_logical_width;\n\t__u16 sensor_logical_height;\n\t__u16 sensor_physical_width;\n\t__u16 sensor_physical_height;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t drops1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct numa_group {\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tint nr_tasks;\n\tpid_t gid;\n\tint active_nodes;\n\tstruct callback_head rcu;\n\tlong unsigned int total_faults;\n\tlong unsigned int max_faults_cpu;\n\tlong unsigned int faults[0];\n};\n\nstruct numa_maps {\n\tlong unsigned int pages;\n\tlong unsigned int anon;\n\tlong unsigned int active;\n\tlong unsigned int writeback;\n\tlong unsigned int mapcount_max;\n\tlong unsigned int dirty;\n\tlong unsigned int swapcache;\n\tlong unsigned int node[64];\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n\tbool mmap_locked;\n\tstruct vm_area_struct *locked_vma;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tstruct mempolicy *task_mempolicy;\n};\n\nstruct numa_maps_private {\n\tstruct proc_maps_private proc_maps;\n\tstruct numa_maps md;\n};\n\nstruct numa_memblk {\n\tu64 start;\n\tu64 end;\n\tint nid;\n};\n\nstruct numa_meminfo {\n\tint nr_blks;\n\tstruct numa_memblk blk[128];\n};\n\nstruct numa_stats {\n\tlong unsigned int load;\n\tlong unsigned int runnable;\n\tlong unsigned int util;\n\tlong unsigned int compute_capacity;\n\tunsigned int nr_running;\n\tunsigned int weight;\n\tenum numa_type node_type;\n\tint idle_cpu;\n};\n\nstruct nv_ethtool_str {\n\tchar name[32];\n};\n\nstruct nv_skb_map {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n\tunsigned int dma_len: 31;\n\tunsigned int dma_single: 1;\n\tstruct ring_desc_ex *first_tx_desc;\n\tstruct nv_skb_map *next_tx_ctx;\n};\n\nstruct nv_txrx_stats {\n\tu64 stat_rx_packets;\n\tu64 stat_rx_bytes;\n\tu64 stat_rx_missed_errors;\n\tu64 stat_rx_dropped;\n\tu64 stat_tx_packets;\n\tu64 stat_tx_bytes;\n\tu64 stat_tx_dropped;\n};\n\nstruct nvmem_cell_entry;\n\nstruct nvmem_cell {\n\tstruct nvmem_cell_entry *entry;\n\tconst char *id;\n\tint index;\n};\n\ntypedef int (*nvmem_cell_post_process_t)(void *, const char *, int, unsigned int, void *, size_t);\n\nstruct nvmem_device;\n\nstruct nvmem_cell_entry {\n\tconst char *name;\n\tint offset;\n\tsize_t raw_len;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n\tstruct device_node *np;\n\tstruct nvmem_device *nvmem;\n\tstruct list_head node;\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tsize_t raw_len;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n\tstruct device_node *np;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n};\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nstruct nvmem_keepout;\n\nstruct nvmem_layout;\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tbool add_legacy_fixed_of_cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool ignore_wp;\n\tstruct nvmem_layout *layout;\n\tstruct device_node *of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device {\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct list_head node;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tstruct nvmem_layout *layout;\n\tvoid *priv;\n\tbool sysfs_cells_populated;\n};\n\nstruct nvmem_keepout {\n\tunsigned int start;\n\tunsigned int end;\n\tunsigned char value;\n};\n\nstruct nvmem_layout {\n\tstruct device dev;\n\tstruct nvmem_device *nvmem;\n\tint (*add_cells)(struct nvmem_layout *);\n};\n\nstruct nvram_ops {\n\tssize_t (*get_size)(void);\n\tunsigned char (*read_byte)(int);\n\tvoid (*write_byte)(unsigned char, int);\n\tssize_t (*read)(char *, size_t, loff_t *);\n\tssize_t (*write)(char *, size_t, loff_t *);\n\tlong int (*initialize)(void);\n\tlong int (*set_checksum)(void);\n};\n\nstruct nvs_page {\n\tlong unsigned int phys_start;\n\tunsigned int size;\n\tvoid *kaddr;\n\tvoid *data;\n\tbool unmap;\n\tstruct list_head node;\n};\n\nstruct nvs_region {\n\t__u64 phys_start;\n\t__u64 size;\n\tstruct list_head node;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct ocb_setup {\n\tstruct cfg80211_chan_def chandef;\n};\n\nstruct ocontext {\n\tunion {\n\t\tchar *name;\n\t\tstruct {\n\t\t\tu8 protocol;\n\t\t\tu16 low_port;\n\t\t\tu16 high_port;\n\t\t} port;\n\t\tstruct {\n\t\t\tu32 addr;\n\t\t\tu32 mask;\n\t\t} node;\n\t\tstruct {\n\t\t\tu32 addr[4];\n\t\t\tu32 mask[4];\n\t\t} node6;\n\t\tstruct {\n\t\t\tu64 subnet_prefix;\n\t\t\tu16 low_pkey;\n\t\t\tu16 high_pkey;\n\t\t} ibpkey;\n\t\tstruct {\n\t\t\tchar *dev_name;\n\t\t\tu8 port;\n\t\t} ibendport;\n\t} u;\n\tunion {\n\t\tu32 sclass;\n\t\tu32 behavior;\n\t} v;\n\tstruct context___2 context[2];\n\tu32 sid[2];\n\tstruct ocontext *next;\n};\n\nstruct od_dbs_tuners {\n\tunsigned int powersave_bias;\n};\n\nstruct od_ops {\n\tunsigned int (*powersave_bias_target)(struct cpufreq_policy *, unsigned int, unsigned int);\n};\n\nstruct policy_dbs_info {\n\tstruct cpufreq_policy *policy;\n\tstruct mutex update_mutex;\n\tu64 last_sample_time;\n\ts64 sample_delay_ns;\n\tatomic_t work_count;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\tstruct dbs_data *dbs_data;\n\tstruct list_head list;\n\tunsigned int rate_mult;\n\tunsigned int idle_periods;\n\tbool is_shared;\n\tbool work_in_progress;\n};\n\nstruct od_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int freq_lo;\n\tunsigned int freq_lo_delay_us;\n\tunsigned int freq_hi_delay_us;\n\tunsigned int sample_type: 1;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nstruct ohci {\n\tvoid *registers;\n};\n\nstruct ohci_driver_overrides {\n\tconst char *product_desc;\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n};\n\nstruct ohci_hcca {\n\t__hc32 int_table[32];\n\t__hc32 frame_no;\n\t__hc32 done_head;\n\tu8 reserved_for_hc[116];\n\tu8 what[4];\n};\n\nstruct ohci_regs;\n\nstruct ohci_hcd {\n\tspinlock_t lock;\n\tstruct ohci_regs *regs;\n\tstruct ohci_hcca *hcca;\n\tdma_addr_t hcca_dma;\n\tstruct ed *ed_rm_list;\n\tstruct ed *ed_bulktail;\n\tstruct ed *ed_controltail;\n\tstruct ed *periodic[32];\n\tvoid (*start_hnp)(struct ohci_hcd *);\n\tstruct dma_pool *td_cache;\n\tstruct dma_pool *ed_cache;\n\tstruct td *td_hash[64];\n\tstruct td *dl_start;\n\tstruct td *dl_end;\n\tstruct list_head pending;\n\tstruct list_head eds_in_use;\n\tenum ohci_rh_state rh_state;\n\tint num_ports;\n\tint load[32];\n\tu32 hc_control;\n\tlong unsigned int next_statechange;\n\tu32 fminterval;\n\tunsigned int autostop: 1;\n\tunsigned int working: 1;\n\tunsigned int restart_work: 1;\n\tlong unsigned int flags;\n\tunsigned int prev_frame_no;\n\tunsigned int wdh_cnt;\n\tunsigned int prev_wdh_cnt;\n\tu32 prev_donehead;\n\tstruct timer_list io_watchdog;\n\tstruct work_struct nec_work;\n\tstruct dentry *debug_dir;\n\tlong unsigned int priv[0];\n};\n\nstruct ohci_roothub_regs {\n\t__hc32 a;\n\t__hc32 b;\n\t__hc32 status;\n\t__hc32 portstatus[15];\n};\n\nstruct ohci_regs {\n\t__hc32 revision;\n\t__hc32 control;\n\t__hc32 cmdstatus;\n\t__hc32 intrstatus;\n\t__hc32 intrenable;\n\t__hc32 intrdisable;\n\t__hc32 hcca;\n\t__hc32 ed_periodcurrent;\n\t__hc32 ed_controlhead;\n\t__hc32 ed_controlcurrent;\n\t__hc32 ed_bulkhead;\n\t__hc32 ed_bulkcurrent;\n\t__hc32 donehead;\n\t__hc32 fminterval;\n\t__hc32 fmremaining;\n\t__hc32 fmnumber;\n\t__hc32 periodicstart;\n\t__hc32 lsthresh;\n\tstruct ohci_roothub_regs roothub;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_itimerval32 {\n\tstruct old_timeval32 it_interval;\n\tstruct old_timeval32 it_value;\n};\n\nstruct old_linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n};\n\nstruct old_timex32 {\n\tu32 modes;\n\ts32 offset;\n\ts32 freq;\n\ts32 maxerror;\n\ts32 esterror;\n\ts32 status;\n\ts32 constant;\n\ts32 precision;\n\ts32 tolerance;\n\tstruct old_timeval32 time;\n\ts32 tick;\n\ts32 ppsfreq;\n\ts32 jitter;\n\ts32 shift;\n\ts32 stabil;\n\ts32 jitcnt;\n\ts32 calcnt;\n\ts32 errcnt;\n\ts32 stbcnt;\n\ts32 tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct old_utimbuf32 {\n\told_time32_t actime;\n\told_time32_t modtime;\n};\n\nstruct old_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n};\n\nstruct oldold_utsname {\n\tchar sysname[9];\n\tchar nodename[9];\n\tchar release[9];\n\tchar version[9];\n\tchar machine[9];\n};\n\nunion omr_encoding {\n\tstruct {\n\t\tu8 omr_source: 4;\n\t\tu8 omr_remote: 1;\n\t\tu8 omr_hitm: 1;\n\t\tu8 omr_snoop: 1;\n\t\tu8 omr_promoted: 1;\n\t};\n\tu8 omr_full;\n};\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct opregion_acpi {\n\tu32 drdy;\n\tu32 csts;\n\tu32 cevt;\n\tu8 rsvd1[20];\n\tu32 didl[8];\n\tu32 cpdl[8];\n\tu32 cadl[8];\n\tu32 nadl[8];\n\tu32 aslp;\n\tu32 tidx;\n\tu32 chpd;\n\tu32 clid;\n\tu32 cdck;\n\tu32 sxsw;\n\tu32 evts;\n\tu32 cnot;\n\tu32 nrdy;\n\tu32 did2[7];\n\tu32 cpd2[7];\n\tu8 rsvd2[4];\n};\n\nstruct opregion_asle {\n\tu32 ardy;\n\tu32 aslc;\n\tu32 tche;\n\tu32 alsi;\n\tu32 bclp;\n\tu32 pfit;\n\tu32 cblv;\n\tu16 bclm[20];\n\tu32 cpfm;\n\tu32 epfm;\n\tu8 plut[74];\n\tu32 pfmb;\n\tu32 cddv;\n\tu32 pcft;\n\tu32 srot;\n\tu32 iuer;\n\tu64 fdss;\n\tu32 fdsp;\n\tu32 stat;\n\tu64 rvda;\n\tu32 rvds;\n\tu8 rsvd[58];\n} __attribute__((packed));\n\nstruct opregion_asle_ext {\n\tu32 phed;\n\tu8 bddc[256];\n\tu8 rsvd[764];\n};\n\nstruct opregion_header {\n\tu8 signature[16];\n\tu32 size;\n\tstruct {\n\t\tu8 rsvd;\n\t\tu8 revision;\n\t\tu8 minor;\n\t\tu8 major;\n\t} over;\n\tu8 bios_ver[32];\n\tu8 vbios_ver[16];\n\tu8 driver_ver[16];\n\tu32 mboxes;\n\tu32 driver_model;\n\tu32 pcon;\n\tu8 dver[32];\n\tu8 rsvd[124];\n};\n\nstruct opregion_swsci {\n\tu32 scic;\n\tu32 parm;\n\tu32 dslp;\n\tu8 rsvd[244];\n};\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct optimized_kprobe {\n\tstruct kprobe kp;\n\tstruct list_head list;\n\tstruct arch_optimized_insn optinsn;\n};\n\nstruct orc_entry {\n\ts16 sp_offset;\n\ts16 bp_offset;\n\tunsigned int sp_reg: 4;\n\tunsigned int bp_reg: 4;\n\tunsigned int type: 3;\n\tunsigned int signal: 1;\n} __attribute__((packed));\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\nstruct osnoise_entry {\n\tstruct trace_entry ent;\n\tu64 noise;\n\tu64 runtime;\n\tu64 max_sample;\n\tunsigned int hw_count;\n\tunsigned int nmi_count;\n\tunsigned int irq_count;\n\tunsigned int softirq_count;\n\tunsigned int thread_count;\n};\n\nstruct x86_cpu_id {\n\t__u16 vendor;\n\t__u16 family;\n\t__u16 model;\n\t__u16 steppings;\n\t__u16 feature;\n\t__u16 flags;\n\t__u8 type;\n\tkernel_ulong_t driver_data;\n};\n\nstruct override_status_id {\n\tstruct acpi_device_id hid[2];\n\tstruct x86_cpu_id cpu_ids[2];\n\tstruct dmi_system_id dmi_ids[2];\n\tconst char *uid;\n\tconst char *path;\n\tlong long unsigned int status;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tu64 bus_offset;\n};\n\nstruct p2sb_res_cache {\n\tu32 bus_dev_id;\n\tstruct resource res;\n};\n\nstruct p4_event_alias {\n\tu64 original;\n\tu64 alternative;\n};\n\nstruct p4_event_bind {\n\tunsigned int opcode;\n\tunsigned int escr_msr[2];\n\tunsigned int escr_emask;\n\tunsigned int shared;\n\tsigned char cntr[6];\n};\n\nstruct p4_pebs_bind {\n\tunsigned int metric_pebs;\n\tunsigned int metric_vert;\n};\n\nstruct p9_trans_module;\n\nstruct p9_client {\n\tspinlock_t lock;\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n\tenum p9_trans_status status;\n\tvoid *trans;\n\tstruct kmem_cache *fcall_cache;\n\tunion {\n\t\tstruct {\n\t\t\tint rfd;\n\t\t\tint wfd;\n\t\t} fd;\n\t\tstruct {\n\t\t\tu16 port;\n\t\t\tbool privport;\n\t\t} tcp;\n\t} trans_opts;\n\tstruct idr fids;\n\tstruct idr reqs;\n\tchar name[65];\n};\n\nstruct p9_client_opts {\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n};\n\nstruct p9_fcall {\n\tu32 size;\n\tu8 id;\n\tu16 tag;\n\tsize_t offset;\n\tsize_t capacity;\n\tstruct kmem_cache *cache;\n\tu8 *sdata;\n\tbool zc;\n};\n\nstruct p9_conn;\n\nstruct p9_poll_wait {\n\tstruct p9_conn *conn;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_addr;\n};\n\nstruct p9_req_t;\n\nstruct p9_conn {\n\tstruct list_head mux_list;\n\tstruct p9_client *client;\n\tint err;\n\tspinlock_t req_lock;\n\tstruct list_head req_list;\n\tstruct list_head unsent_req_list;\n\tstruct p9_req_t *rreq;\n\tstruct p9_req_t *wreq;\n\tchar tmp_buf[7];\n\tstruct p9_fcall rc;\n\tint wpos;\n\tint wsize;\n\tchar *wbuf;\n\tstruct list_head poll_pending_link;\n\tstruct p9_poll_wait poll_wait[2];\n\tpoll_table pt;\n\tstruct work_struct rq;\n\tstruct work_struct wq;\n\tlong unsigned int wsched;\n};\n\nstruct p9_qid {\n\tu8 type;\n\tu32 version;\n\tu64 path;\n};\n\nstruct p9_dirent {\n\tstruct p9_qid qid;\n\tu64 d_off;\n\tunsigned char d_type;\n\tchar d_name[256];\n};\n\nstruct p9_fd_opts {\n\tint rfd;\n\tint wfd;\n\tu16 port;\n\tbool privport;\n};\n\nstruct p9_fid {\n\tstruct p9_client *clnt;\n\tu32 fid;\n\trefcount_t count;\n\tint mode;\n\tstruct p9_qid qid;\n\tu32 iounit;\n\tkuid_t uid;\n\tvoid *rdir;\n\tstruct hlist_node dlist;\n\tstruct hlist_node ilist;\n};\n\nstruct p9_flock {\n\tu8 type;\n\tu32 flags;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_getlock {\n\tu8 type;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_iattr_dotl {\n\tu32 valid;\n\tu32 mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tu64 size;\n\tu64 atime_sec;\n\tu64 atime_nsec;\n\tu64 mtime_sec;\n\tu64 mtime_nsec;\n};\n\nstruct p9_rdir {\n\tint head;\n\tint tail;\n\tuint8_t buf[0];\n};\n\nstruct p9_rdma_opts {\n\tshort int port;\n\tbool privport;\n\tint sq_depth;\n\tint rq_depth;\n\tlong int timeout;\n};\n\nstruct p9_req_t {\n\tint status;\n\tint t_err;\n\trefcount_t refcount;\n\twait_queue_head_t wq;\n\tstruct p9_fcall tc;\n\tstruct p9_fcall rc;\n\tstruct list_head req_list;\n};\n\nstruct p9_rstatfs {\n\tu32 type;\n\tu32 bsize;\n\tu64 blocks;\n\tu64 bfree;\n\tu64 bavail;\n\tu64 files;\n\tu64 ffree;\n\tu64 fsid;\n\tu32 namelen;\n};\n\nstruct p9_session_opts {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tlong int session_lock_timeout;\n};\n\nstruct p9_stat_dotl {\n\tu64 st_result_mask;\n\tstruct p9_qid qid;\n\tu32 st_mode;\n\tkuid_t st_uid;\n\tkgid_t st_gid;\n\tu64 st_nlink;\n\tu64 st_rdev;\n\tu64 st_size;\n\tu64 st_blksize;\n\tu64 st_blocks;\n\tu64 st_atime_sec;\n\tu64 st_atime_nsec;\n\tu64 st_mtime_sec;\n\tu64 st_mtime_nsec;\n\tu64 st_ctime_sec;\n\tu64 st_ctime_nsec;\n\tu64 st_btime_sec;\n\tu64 st_btime_nsec;\n\tu64 st_gen;\n\tu64 st_data_version;\n};\n\nstruct p9_trans_fd {\n\tstruct file *rd;\n\tstruct file *wr;\n\tstruct p9_conn conn;\n};\n\nstruct p9_trans_module {\n\tstruct list_head list;\n\tchar *name;\n\tint maxsize;\n\tbool pooled_rbuffers;\n\tbool def;\n\tbool supports_vmalloc;\n\tstruct module *owner;\n\tint (*create)(struct p9_client *, struct fs_context *);\n\tvoid (*close)(struct p9_client *);\n\tint (*request)(struct p9_client *, struct p9_req_t *);\n\tint (*cancel)(struct p9_client *, struct p9_req_t *);\n\tint (*cancelled)(struct p9_client *, struct p9_req_t *);\n\tint (*zc_request)(struct p9_client *, struct p9_req_t *, struct iov_iter *, struct iov_iter *, int, int, int);\n\tint (*show_options)(struct seq_file *, struct p9_client *);\n};\n\nstruct p9_wstat {\n\tu16 size;\n\tu16 type;\n\tu32 dev;\n\tstruct p9_qid qid;\n\tu32 mode;\n\tu32 atime;\n\tu32 mtime;\n\tu64 length;\n\tconst char *name;\n\tconst char *uid;\n\tconst char *gid;\n\tconst char *muid;\n\tchar *extension;\n\tkuid_t n_uid;\n\tkgid_t n_gid;\n\tkuid_t n_muid;\n};\n\nstruct pacct_struct {\n\tint ac_flag;\n\tlong int ac_exitcode;\n\tlong unsigned int ac_mem;\n\tu64 ac_utime;\n\tu64 ac_stime;\n\tlong unsigned int ac_minflt;\n\tlong unsigned int ac_majflt;\n};\n\nstruct scsi_sense_hdr;\n\nstruct packet_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct scsi_sense_hdr *sshdr;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 history[16];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t tp_drops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct padata_cpumask {\n\tcpumask_var_t pcpu;\n\tcpumask_var_t cbcpu;\n};\n\nstruct padata_instance {\n\tstruct hlist_node cpu_online_node;\n\tstruct hlist_node cpu_dead_node;\n\tstruct workqueue_struct *parallel_wq;\n\tstruct workqueue_struct *serial_wq;\n\tstruct list_head pslist;\n\tstruct padata_cpumask cpumask;\n\tstruct kobject kobj;\n\tstruct mutex lock;\n\tu8 flags;\n};\n\nstruct padata_list {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct padata_mt_job {\n\tvoid (*thread_fn)(long unsigned int, long unsigned int, void *);\n\tvoid *fn_arg;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int min_chunk;\n\tint max_threads;\n\tbool numa_aware;\n};\n\nstruct padata_mt_job_state {\n\tspinlock_t lock;\n\tstruct completion completion;\n\tstruct padata_mt_job *job;\n\tint nworks;\n\tint nworks_fini;\n\tlong unsigned int chunk_size;\n};\n\nstruct parallel_data;\n\nstruct padata_priv {\n\tstruct list_head list;\n\tstruct parallel_data *pd;\n\tint cb_cpu;\n\tunsigned int seq_nr;\n\tint info;\n\tvoid (*parallel)(struct padata_priv *);\n\tvoid (*serial)(struct padata_priv *);\n};\n\nstruct padata_serial_queue {\n\tstruct padata_list serial;\n\tstruct work_struct work;\n\tstruct parallel_data *pd;\n};\n\nstruct padata_shell {\n\tstruct padata_instance *pinst;\n\tstruct parallel_data *pd;\n\tstruct parallel_data *opd;\n\tstruct list_head list;\n};\n\nstruct padata_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct padata_instance *, const struct attribute *, char *);\n\tssize_t (*store)(struct padata_instance *, const struct attribute *, const char *, size_t);\n};\n\nstruct padata_work {\n\tstruct work_struct pw_work;\n\tstruct list_head pw_list;\n\tvoid *pw_data;\n};\n\ntypedef struct page *pgtable_t;\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_list {\n\tstruct page_list *next;\n\tstruct page *page;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tlong: 0;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\tlong: 0;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tu32 xdp_mem_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pp_alloc_cache alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t} user;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_req_dsc {\n\tunion {\n\t\tstruct {\n\t\t\tu64 type: 8;\n\t\t\tu64 pasid_present: 1;\n\t\t\tu64 rsvd: 7;\n\t\t\tu64 rid: 16;\n\t\t\tu64 pasid: 20;\n\t\t\tu64 exe_req: 1;\n\t\t\tu64 pm_req: 1;\n\t\t\tu64 rsvd2: 10;\n\t\t};\n\t\tu64 qw_0;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu64 rd_req: 1;\n\t\t\tu64 wr_req: 1;\n\t\t\tu64 lpig: 1;\n\t\t\tu64 prg_index: 9;\n\t\t\tu64 addr: 52;\n\t\t};\n\t\tu64 qw_1;\n\t};\n\tu64 qw_2;\n\tu64 qw_3;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n\tlong: 64;\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pagerange_state {\n\tlong unsigned int cur_pfn;\n\tint ram;\n\tint not_ram;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct panel_bridge {\n\tstruct drm_bridge bridge;\n\tstruct drm_connector connector;\n\tstruct drm_panel *panel;\n\tu32 connector_type;\n};\n\nstruct parallel_data {\n\tstruct padata_shell *ps;\n\tstruct padata_list *reorder_list;\n\tstruct padata_serial_queue *squeue;\n\trefcount_t refcnt;\n\tunsigned int seq_nr;\n\tunsigned int processed;\n\tint cpu;\n\tstruct padata_cpumask cpumask;\n};\n\nstruct parallel_io {\n\tstruct kref refcnt;\n\tvoid (*pnfs_callback)(void *);\n\tvoid *data;\n};\n\nstruct thermal_genl_cpu_caps;\n\nstruct param {\n\tstruct nlattr **attrs;\n\tstruct sk_buff *msg;\n\tconst char *name;\n\tint tz_id;\n\tint cdev_id;\n\tint trip_id;\n\tint trip_temp;\n\tint trip_type;\n\tint trip_hyst;\n\tint temp;\n\tint prev_temp;\n\tint direction;\n\tint cdev_state;\n\tint cdev_max_state;\n\tstruct thermal_genl_cpu_caps *cpu_capabilities;\n\tint cpu_capabilities_count;\n};\n\nstruct pv_cpu_ops {\n\tvoid (*io_delay)(void);\n};\n\nstruct pv_irq_ops {\n\tvoid (*safe_halt)(void);\n\tvoid (*halt)(void);\n};\n\nstruct pv_mmu_ops {\n\tvoid (*flush_tlb_user)(void);\n\tvoid (*flush_tlb_kernel)(void);\n\tvoid (*flush_tlb_one_user)(long unsigned int);\n\tvoid (*flush_tlb_multi)(const struct cpumask *, const struct flush_tlb_info *);\n\tvoid (*exit_mmap)(struct mm_struct *);\n\tvoid (*notify_page_enc_status_changed)(long unsigned int, int, bool);\n};\n\nstruct paravirt_patch_template {\n\tstruct pv_cpu_ops cpu;\n\tstruct pv_irq_ops irq;\n\tstruct pv_mmu_ops mmu;\n};\n\nstruct sync_semaphore {\n\tu32 semaphore;\n\tu8 unused[60];\n};\n\nstruct parent_scratch {\n\tunion guc_descs descs;\n\tstruct sync_semaphore go;\n\tstruct sync_semaphore join[9];\n\tu8 unused[1216];\n\tu32 wq[512];\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct pasid_dir_entry {\n\tu64 val;\n};\n\nstruct pasid_entry {\n\tu64 val[8];\n};\n\nstruct pasid_table {\n\tvoid *table;\n\tu32 max_pasid;\n};\n\nstruct patch_digest {\n\tu32 patch_id;\n\tu8 sha256[32];\n};\n\nstruct patch_site {\n\tu8 *instr;\n\tstruct alt_instr *alt;\n\tu8 buff[254];\n\tu8 len;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct pbe {\n\tvoid *address;\n\tvoid *orig_address;\n\tstruct pbe *next;\n};\n\nstruct pcc_mbox_chan {\n\tstruct mbox_chan *mchan;\n\tu64 shmem_base_addr;\n\tvoid *shmem;\n\tu64 shmem_size;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n};\n\nstruct pcc_chan_reg {\n\tvoid *vaddr;\n\tstruct acpi_generic_address *gas;\n\tu64 preserve_mask;\n\tu64 set_mask;\n\tu64 status_mask;\n};\n\nstruct pcc_chan_info {\n\tstruct pcc_mbox_chan chan;\n\tstruct pcc_chan_reg db;\n\tstruct pcc_chan_reg plat_irq_ack;\n\tstruct pcc_chan_reg cmd_complete;\n\tstruct pcc_chan_reg cmd_update;\n\tstruct pcc_chan_reg error;\n\tint plat_irq;\n\tu8 type;\n\tunsigned int plat_irq_flags;\n\tbool chan_in_use;\n};\n\nstruct pcc_data {\n\tstruct pcc_mbox_chan *pcc_chan;\n\tstruct completion done;\n\tstruct mbox_client cl;\n\tstruct acpi_pcc_info ctx;\n};\n\nstruct pccard_io_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t start;\n\tphys_addr_t stop;\n};\n\ntypedef struct pccard_io_map pccard_io_map;\n\nstruct pccard_mem_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t static_start;\n\tu_int card_start;\n\tstruct resource *res;\n};\n\ntypedef struct pccard_mem_map pccard_mem_map;\n\nstruct pcmcia_socket;\n\nstruct socket_state_t;\n\ntypedef struct socket_state_t socket_state_t;\n\nstruct pccard_operations {\n\tint (*init)(struct pcmcia_socket *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*get_status)(struct pcmcia_socket *, u_int *);\n\tint (*set_socket)(struct pcmcia_socket *, socket_state_t *);\n\tint (*set_io_map)(struct pcmcia_socket *, struct pccard_io_map *);\n\tint (*set_mem_map)(struct pcmcia_socket *, struct pccard_mem_map *);\n};\n\nstruct pccard_resource_ops {\n\tint (*validate_mem)(struct pcmcia_socket *);\n\tint (*find_io)(struct pcmcia_socket *, unsigned int, unsigned int *, unsigned int, unsigned int, struct resource **);\n\tstruct resource * (*find_mem)(long unsigned int, long unsigned int, long unsigned int, int, struct pcmcia_socket *);\n\tint (*init)(struct pcmcia_socket *);\n\tvoid (*exit)(struct pcmcia_socket *);\n};\n\nstruct pci2phy_map {\n\tstruct list_head list;\n\tint segment;\n\tint pbus_to_dieid[256];\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_check_idx_range {\n\tint start;\n\tint end;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct rcec_ea;\n\nstruct pcie_link_state;\n\nstruct pcie_bwctrl_data;\n\nstruct pci_sriov;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tstruct rcec_ea *rcec_ea;\n\tstruct pci_dev *rcec;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tstruct pcie_link_state *link_state;\n\tunsigned int aspm_l0s_support: 1;\n\tunsigned int aspm_l1_support: 1;\n\tunsigned int ltr_path: 1;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[11];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[11];\n\tstruct bin_attribute *res_attr_wc[11];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tunion {\n\t\tstruct pci_sriov *sriov;\n\t\tstruct pci_dev *physfn;\n\t};\n\tu16 ats_cap;\n\tu8 ats_stu;\n\tu16 pri_cap;\n\tu32 pri_reqs_alloc;\n\tunsigned int pasid_required: 1;\n\tu16 pasid_cap;\n\tu16 pasid_features;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_extra_dev {\n\tstruct pci_dev *dev[4];\n};\n\nstruct pci_filp_private {\n\tenum pci_mmap_state mmap_state;\n\tint write_combine;\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tint hook_offset;\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct pci_hostbridge_probe {\n\tu32 bus;\n\tu32 slot;\n\tu32 vendor;\n\tu32 device;\n};\n\nstruct pci_mmcfg_hostbridge_probe {\n\tu32 bus;\n\tu32 devfn;\n\tu32 vendor;\n\tu32 device;\n\tconst char * (*probe)(void);\n};\n\nstruct pci_mmcfg_region {\n\tstruct list_head list;\n\tstruct resource res;\n\tu64 address;\n\tchar *virt;\n\tu16 segment;\n\tu8 start_bus;\n\tu8 end_bus;\n\tchar name[30];\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_osc_bit_struct {\n\tu32 bit;\n\tchar *desc;\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pci_raw_ops {\n\tint (*read)(unsigned int, unsigned int, unsigned int, int, int, u32 *);\n\tint (*write)(unsigned int, unsigned int, unsigned int, int, int, u32);\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_root_info {\n\tstruct list_head list;\n\tchar name[12];\n\tstruct list_head resources;\n\tstruct resource busn;\n\tint node;\n\tint link;\n};\n\nstruct pci_sysdata {\n\tint domain;\n\tint node;\n\tstruct acpi_device *companion;\n\tvoid *iommu;\n\tvoid *fwnode;\n};\n\nstruct pci_root_info___2 {\n\tstruct acpi_pci_root_info common;\n\tstruct pci_sysdata sd;\n\tbool mcfg_added;\n\tu8 start_bus;\n\tu8 end_bus;\n};\n\nstruct pci_root_res {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct serial_private;\n\nstruct pciserial_board;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct setup_data {\n\t__u64 next;\n\t__u32 type;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct pci_setup_rom {\n\tstruct setup_data data;\n\tuint16_t vendor;\n\tuint16_t devid;\n\tuint64_t pcilen;\n\tlong unsigned int segment;\n\tlong unsigned int bus;\n\tlong unsigned int device;\n\tlong unsigned int function;\n\tuint8_t romdata[0];\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pci_sriov {\n\tint pos;\n\tint nres;\n\tu32 cap;\n\tu16 ctrl;\n\tu16 total_VFs;\n\tu16 initial_VFs;\n\tu16 num_VFs;\n\tu16 offset;\n\tu16 stride;\n\tu16 vf_device;\n\tu32 pgsz;\n\tu8 link;\n\tu8 max_VF_buses;\n\tu16 driver_max_VFs;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *self;\n\tu32 class;\n\tu8 hdr_type;\n\tu16 subsystem_vendor;\n\tu16 subsystem_device;\n\tresource_size_t barsz[6];\n\tu16 vf_rebar_cap;\n\tbool drivers_autoprobe;\n};\n\nstruct pcibios_fwaddrmap {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n\tresource_size_t fw_addr[11];\n};\n\nstruct pcie_bwctrl_data {\n\tstruct mutex set_speed_mutex;\n\tstruct thermal_cooling_device *cdev;\n};\n\nstruct pcie_device {\n\tint irq;\n\tstruct pci_dev *port;\n\tu32 service;\n\tvoid *priv_data;\n\tstruct device device;\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tint: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n};\n\nstruct pcie_pme_service_data {\n\tspinlock_t lock;\n\tstruct pcie_device *srv;\n\tstruct work_struct work;\n\tbool noirq;\n};\n\nstruct pcie_port_service_driver {\n\tconst char *name;\n\tint (*probe)(struct pcie_device *);\n\tvoid (*remove)(struct pcie_device *);\n\tint (*suspend)(struct pcie_device *);\n\tint (*resume_noirq)(struct pcie_device *);\n\tint (*resume)(struct pcie_device *);\n\tint (*runtime_suspend)(struct pcie_device *);\n\tint (*runtime_resume)(struct pcie_device *);\n\tint (*slot_reset)(struct pcie_device *);\n\tint port_type;\n\tu32 service;\n\tstruct device_driver driver;\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[11];\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct pcm_format_data {\n\tunsigned char width;\n\tunsigned char phys;\n\tsigned char le;\n\tsigned char signd;\n\tunsigned char silence[8];\n};\n\nstruct resource_map;\n\nstruct pcmcia_align_data {\n\tlong unsigned int mask;\n\tlong unsigned int offset;\n\tstruct resource_map *map;\n};\n\nstruct pcmcia_callback {\n\tstruct module *owner;\n\tint (*add)(struct pcmcia_socket *);\n\tint (*remove)(struct pcmcia_socket *);\n\tvoid (*requery)(struct pcmcia_socket *);\n\tint (*validate)(struct pcmcia_socket *, unsigned int *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*early_resume)(struct pcmcia_socket *);\n\tint (*resume)(struct pcmcia_socket *);\n};\n\nstruct pcmcia_device;\n\nstruct pcmcia_cfg_mem {\n\tstruct pcmcia_device *p_dev;\n\tint (*conf_check)(struct pcmcia_device *, void *);\n\tvoid *priv_data;\n\tcisparse_t parse;\n\tcistpl_cftable_entry_t dflt;\n};\n\nstruct pcmcia_device {\n\tstruct pcmcia_socket *socket;\n\tchar *devname;\n\tu8 device_no;\n\tu8 func;\n\tstruct config_t *function_config;\n\tstruct list_head socket_device_list;\n\tunsigned int irq;\n\tstruct resource *resource[6];\n\tresource_size_t card_addr;\n\tunsigned int vpp;\n\tunsigned int config_flags;\n\tunsigned int config_base;\n\tunsigned int config_index;\n\tunsigned int config_regs;\n\tunsigned int io_lines;\n\tu16 suspended: 1;\n\tu16 _irq: 1;\n\tu16 _io: 1;\n\tu16 _win: 4;\n\tu16 _locked: 1;\n\tu16 allow_func_id_match: 1;\n\tu16 has_manf_id: 1;\n\tu16 has_card_id: 1;\n\tu16 has_func_id: 1;\n\tu16 reserved: 4;\n\tu8 func_id;\n\tu16 manf_id;\n\tu16 card_id;\n\tchar *prod_id[4];\n\tu64 dma_mask;\n\tstruct device dev;\n\tvoid *priv;\n\tunsigned int open;\n};\n\nstruct pcmcia_device_id {\n\t__u16 match_flags;\n\t__u16 manf_id;\n\t__u16 card_id;\n\t__u8 func_id;\n\t__u8 function;\n\t__u8 device_no;\n\t__u32 prod_id_hash[4];\n\tconst char *prod_id[4];\n\tkernel_ulong_t driver_info;\n\tchar *cisfile;\n};\n\nstruct pcmcia_dynids {\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct pcmcia_driver {\n\tconst char *name;\n\tint (*probe)(struct pcmcia_device *);\n\tvoid (*remove)(struct pcmcia_device *);\n\tint (*suspend)(struct pcmcia_device *);\n\tint (*resume)(struct pcmcia_device *);\n\tstruct module *owner;\n\tconst struct pcmcia_device_id *id_table;\n\tstruct device_driver drv;\n\tstruct pcmcia_dynids dynids;\n};\n\nstruct pcmcia_dynid {\n\tstruct list_head node;\n\tstruct pcmcia_device_id id;\n};\n\nstruct pcmcia_loop_get {\n\tsize_t len;\n\tcisdata_t **buf;\n};\n\nstruct tuple_t;\n\ntypedef struct tuple_t tuple_t;\n\nstruct pcmcia_loop_mem {\n\tstruct pcmcia_device *p_dev;\n\tvoid *priv_data;\n\tint (*loop_tuple)(struct pcmcia_device *, tuple_t *, void *);\n};\n\nstruct socket_state_t {\n\tu_int flags;\n\tu_int csc_mask;\n\tu_char Vcc;\n\tu_char Vpp;\n\tu_char io_irq;\n};\n\nstruct pcmcia_socket {\n\tstruct module *owner;\n\tsocket_state_t socket;\n\tu_int state;\n\tu_int suspended_state;\n\tu_short functions;\n\tu_short lock_count;\n\tpccard_mem_map cis_mem;\n\tvoid *cis_virt;\n\tio_window_t io[2];\n\tpccard_mem_map win[4];\n\tstruct list_head cis_cache;\n\tsize_t fake_cis_len;\n\tu8 *fake_cis;\n\tstruct list_head socket_list;\n\tstruct completion socket_released;\n\tunsigned int sock;\n\tu_int features;\n\tu_int irq_mask;\n\tu_int map_size;\n\tu_int io_offset;\n\tu_int pci_irq;\n\tstruct pci_dev *cb_dev;\n\tu8 resource_setup_done;\n\tstruct pccard_operations *ops;\n\tstruct pccard_resource_ops *resource_ops;\n\tvoid *resource_data;\n\tvoid (*zoom_video)(struct pcmcia_socket *, int);\n\tint (*power_hook)(struct pcmcia_socket *, int);\n\tvoid (*tune_bridge)(struct pcmcia_socket *, struct pci_bus *);\n\tstruct task_struct *thread;\n\tstruct completion thread_done;\n\tunsigned int thread_events;\n\tunsigned int sysfs_events;\n\tstruct mutex skt_mutex;\n\tstruct mutex ops_mutex;\n\tspinlock_t thread_lock;\n\tstruct pcmcia_callback *callback;\n\tstruct list_head devices_list;\n\tu8 device_count;\n\tu8 pcmcia_pfc;\n\tatomic_t present;\n\tunsigned int pcmcia_irq;\n\tstruct device dev;\n\tvoid *driver_data;\n\tint resume_status;\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 64;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pdev_archdata {};\n\nstruct pdom_dev_data {\n\tstruct iommu_dev_data *dev_data;\n\tioasid_t pasid;\n\tstruct list_head list;\n};\n\nstruct pdom_iommu_info {\n\tstruct amd_iommu *iommu;\n\tu32 refcnt;\n};\n\nstruct pebs_basic {\n\tu64 format_group: 32;\n\tu64 retire_latency: 16;\n\tu64 format_size: 16;\n\tu64 ip;\n\tu64 applicable_counters;\n\tu64 tsc;\n};\n\nstruct pebs_cntr_header {\n\tu32 cntr;\n\tu32 fixed;\n\tu32 metrics;\n\tu32 reserved;\n};\n\nstruct pebs_gprs {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 cx;\n\tu64 dx;\n\tu64 bx;\n\tu64 sp;\n\tu64 bp;\n\tu64 si;\n\tu64 di;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n};\n\nstruct pebs_meminfo {\n\tu64 address;\n\tu64 aux;\n\tunion {\n\t\tu64 mem_latency;\n\t\tstruct {\n\t\t\tu64 instr_latency: 16;\n\t\t\tu64 pad2: 16;\n\t\t\tu64 cache_latency: 16;\n\t\t\tu64 pad3: 16;\n\t\t};\n\t};\n\tu64 tsx_tuning;\n};\n\nstruct pebs_record_core {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n};\n\nstruct pebs_record_nhm {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 status;\n\tu64 dla;\n\tu64 dse;\n\tu64 lat;\n};\n\nstruct pebs_record_skl {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 status;\n\tu64 dla;\n\tu64 dse;\n\tu64 lat;\n\tu64 real_ip;\n\tu64 tsx_tuning;\n\tu64 tsc;\n};\n\nstruct pebs_xmm {\n\tu64 xmm[32];\n};\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[51];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tu8 expire;\n\tshort int free_count;\n\tstruct list_head lists[12];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[10];\n\ts8 stat_threshold;\n\tlong unsigned int vm_numa_event[6];\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\nstruct percpu_free_defer {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\ntypedef struct percpu_rw_semaphore *class_percpu_read_t;\n\ntypedef struct percpu_rw_semaphore *class_percpu_write_t;\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[1];\n\tlong unsigned int offset[1];\n\tlocal_lock_t lock;\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_amd_iommu {\n\tstruct list_head list;\n\tstruct pmu pmu;\n\tstruct amd_iommu *iommu;\n\tchar name[24];\n\tu8 max_banks;\n\tu8 max_counters;\n\tu64 cntr_assign_mask;\n\traw_spinlock_t lock;\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu64 hw_id;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___3 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct perf_event_mmap_page;\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\trefcount_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tstruct mutex aux_mutex;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\trefcount_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tint aux_in_pause_resume;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct unwind_stacktrace;\n\nstruct perf_callchain_deferred_event {\n\tstruct unwind_stacktrace *trace;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 cookie;\n\t\tu64 nr;\n\t\tu64 ips[0];\n\t} event;\n};\n\nstruct perf_callchain_entry {\n\tu64 nr;\n\tu64 ip[0];\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nunion perf_capabilities {\n\tstruct {\n\t\tu64 lbr_format: 6;\n\t\tu64 pebs_trap: 1;\n\t\tu64 pebs_arch_reg: 1;\n\t\tu64 pebs_format: 4;\n\t\tu64 smm_freeze: 1;\n\t\tu64 full_width_write: 1;\n\t\tu64 pebs_baseline: 1;\n\t\tu64 perf_metrics: 1;\n\t\tu64 pebs_output_pt_available: 1;\n\t\tu64 pebs_timing_info: 1;\n\t\tu64 anythread_deprecated: 1;\n\t\tu64 rdpmc_metrics_clear: 1;\n\t};\n\tu64 capabilities;\n};\n\nstruct perf_cgroup_info;\n\nstruct perf_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct perf_cgroup_info *info;\n};\n\nstruct perf_cgroup_event {\n\tchar *path;\n\tint path_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 id;\n\t\tchar path[0];\n\t} event_id;\n};\n\nstruct perf_time_ctx {\n\tu64 time;\n\tu64 stamp;\n\tu64 offset;\n};\n\nstruct perf_cgroup_info {\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tint active;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tu64 index;\n};\n\nstruct perf_event_context {\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head pmu_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tint nr_events;\n\tint nr_user;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tstruct perf_event_context *parent_ctx;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tint nr_cgroups;\n\tstruct callback_head callback_head;\n\tlocal_t nr_no_switch_fast;\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint online;\n\tstruct perf_cgroup *cgrp;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_event_pmu_context {\n\tstruct pmu *pmu;\n\tstruct perf_event_context *ctx;\n\tstruct list_head pmu_ctx_entry;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tunsigned int embedded: 1;\n\tunsigned int nr_events;\n\tunsigned int nr_cgroups;\n\tunsigned int nr_freq;\n\tatomic_t refcount;\n\tstruct callback_head callback_head;\n\tint rotate_necessary;\n};\n\nstruct perf_cpu_pmu_context {\n\tstruct perf_event_pmu_context epc;\n\tstruct perf_event_pmu_context *task_epc;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint active_oncpu;\n\tint exclusive;\n\tint pmu_disable_count;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n};\n\nstruct perf_ctx_data {\n\tstruct callback_head callback_head;\n\trefcount_t refcount;\n\tint global;\n\tstruct kmem_cache *ctx_cache;\n\tvoid *data;\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 text_poke: 1;\n\t__u64 build_id: 1;\n\t__u64 inherit_thread: 1;\n\t__u64 remove_on_exec: 1;\n\t__u64 sigtrap: 1;\n\t__u64 defer_callchain: 1;\n\t__u64 defer_output: 1;\n\t__u64 __reserved_1: 24;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\tunion {\n\t\t__u32 aux_action;\n\t\tstruct {\n\t\t\t__u32 aux_start_paused: 1;\n\t\t\t__u32 aux_pause: 1;\n\t\t\t__u32 aux_resume: 1;\n\t\t\t__u32 __reserved_3: 29;\n\t\t};\n\t};\n\t__u64 sig_data;\n\t__u64 config3;\n\t__u64 config4;\n};\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tunsigned int group_generation;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tstruct perf_event_pmu_context *pmu_ctx;\n\tatomic_long_t refcount;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\trefcount_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tunsigned int pending_wakeup;\n\tunsigned int pending_kill;\n\tunsigned int pending_disable;\n\tlong unsigned int pending_addr;\n\tstruct irq_work pending_irq;\n\tstruct irq_work pending_disable_irq;\n\tstruct callback_head pending_task;\n\tunsigned int pending_work;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tu64 id;\n\tatomic64_t lost_samples;\n\tu64 (*clock)(void);\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tstruct bpf_prog *prog;\n\tu64 bpf_cookie;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tstruct perf_cgroup *cgrp;\n\tvoid *security;\n\tstruct list_head sb_list;\n\tstruct list_head pmu_list;\n\tu32 orig_type;\n};\n\nstruct perf_event_min_heap {\n\tsize_t nr;\n\tsize_t size;\n\tstruct perf_event **data;\n\tstruct perf_event *preallocated[0];\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_user_time_short: 1;\n\t\t\t__u64 cap_____res: 58;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u32 __reserved_1;\n\t__u64 time_cycles;\n\t__u64 time_mask;\n\t__u8 __reserved[928];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct perf_event_security_struct {\n\tu32 sid;\n};\n\nstruct perf_ibs {\n\tstruct pmu pmu;\n\tunsigned int msr;\n\tu64 config_mask;\n\tu64 cnt_mask;\n\tu64 enable_mask;\n\tu64 valid_mask;\n\tu16 min_period;\n\tu64 max_period;\n\tlong unsigned int offset_mask[1];\n\tint offset_max;\n\tunsigned int fetch_count_reset_broken: 1;\n\tunsigned int fetch_ignore_if_zero_rip: 1;\n\tstruct cpu_perf_ibs *pcpu;\n\tu64 (*get_count)(u64);\n};\n\nstruct perf_ibs_data {\n\tu32 size;\n\tunion {\n\t\tu32 data[0];\n\t\tu32 caps;\n\t};\n\tu64 regs[8];\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tu8 build_id[20];\n\tu32 build_id_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_msr {\n\tu64 msr;\n\tstruct attribute_group *grp;\n\tbool (*test)(int, void *);\n\tbool no_check;\n\tu64 mask;\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_open_properties {\n\tu32 sample_flags;\n\tu64 single_context: 1;\n\tu64 hold_preemption: 1;\n\tu64 ctx_handle;\n\tint metrics_set;\n\tint oa_format;\n\tbool oa_periodic;\n\tint oa_period_exponent;\n\tstruct intel_engine_cs *engine;\n\tbool has_sseu;\n\tstruct intel_sseu sseu;\n\tu64 poll_oa_period;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n};\n\nstruct perf_pmu_events_ht_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str_ht;\n\tconst char *event_str_noht;\n};\n\nstruct perf_pmu_events_hybrid_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n\tu64 pmu_type;\n};\n\nstruct perf_pmu_format_hybrid_attr {\n\tstruct device_attribute attr;\n\tu64 pmu_type;\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n} __attribute__((packed));\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct sched_state {\n\tint weight;\n\tint event;\n\tint counter;\n\tint unassigned;\n\tint nr_gp;\n\tu64 used;\n};\n\nstruct perf_sched {\n\tint max_weight;\n\tint max_events;\n\tint max_gp;\n\tint saved_states;\n\tstruct event_constraint **constraints;\n\tstruct sched_state state;\n\tstruct sched_state saved[2];\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_text_poke_event {\n\tconst void *old_bytes;\n\tconst void *new_bytes;\n\tsize_t pad;\n\tu16 old_len;\n\tu16 new_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t} event_id;\n};\n\nstruct pericom8250 {\n\tvoid *virt;\n\tunsigned int nr;\n\tint line[0];\n};\n\nstruct perm_datum {\n\tu32 value;\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct pf_desc {\n\tu32 pseudoflavor;\n\tu32 qop;\n\tu32 service;\n\tchar *name;\n\tchar *auth_domain_name;\n\tstruct auth_domain *domain;\n\tbool datatouch;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct pfnmap_track_ctx {\n\tstruct kref kref;\n\tlong unsigned int pfn;\n\tlong unsigned int size;\n};\n\nstruct ptdump_range;\n\nstruct ptdump_state {\n\tvoid (*note_page_pte)(struct ptdump_state *, long unsigned int, pte_t);\n\tvoid (*note_page_pmd)(struct ptdump_state *, long unsigned int, pmd_t);\n\tvoid (*note_page_pud)(struct ptdump_state *, long unsigned int, pud_t);\n\tvoid (*note_page_p4d)(struct ptdump_state *, long unsigned int, p4d_t);\n\tvoid (*note_page_pgd)(struct ptdump_state *, long unsigned int, pgd_t);\n\tvoid (*note_page_flush)(struct ptdump_state *);\n\tvoid (*effective_prot_pte)(struct ptdump_state *, pte_t);\n\tvoid (*effective_prot_pmd)(struct ptdump_state *, pmd_t);\n\tvoid (*effective_prot_pud)(struct ptdump_state *, pud_t);\n\tvoid (*effective_prot_p4d)(struct ptdump_state *, p4d_t);\n\tvoid (*effective_prot_pgd)(struct ptdump_state *, pgd_t);\n\tconst struct ptdump_range *range;\n};\n\nstruct pg_state {\n\tstruct ptdump_state ptdump;\n\tint level;\n\tpgprotval_t current_prot;\n\tpgprotval_t effective_prot;\n\tpgprotval_t prot_levels[5];\n\tlong unsigned int start_address;\n\tconst struct addr_marker *marker;\n\tlong unsigned int lines;\n\tbool to_dmesg;\n\tbool check_wx;\n\tlong unsigned int wx_pages;\n\tstruct seq_file *seq;\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[4];\n\tint node;\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tconst char *name;\n\tint initialized;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[11];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 0;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[10];\n\tatomic_long_t vm_numa_event[6];\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[257];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[4];\n\tstruct zonelist node_zonelists[2];\n\tint nr_zones;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tlong unsigned int min_unmapped_pages;\n\tlong unsigned int min_slab_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tunsigned int nbp_rl_start;\n\tlong unsigned int nbp_rl_nr_cand;\n\tunsigned int nbp_threshold;\n\tunsigned int nbp_th_start;\n\tlong unsigned int nbp_th_nr_cand;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[51];\n\tstruct memory_tier *memtier;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tu32 max_link_rate;\n\tenum phy_mode mode;\n};\n\nstruct phy_ops;\n\nstruct phy___3 {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tstruct lock_class_key lockdep_key;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n\tstruct dentry *debugfs;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_lvds {\n\tunsigned int bits_per_lane_and_dclk_cycle;\n\tlong unsigned int differential_clk_rate;\n\tunsigned int lanes;\n\tbool is_slave;\n};\n\nstruct phy_configure_opts_hdmi {\n\tunsigned int bpc;\n\tunion {\n\t\tlong long unsigned int tmds_char_rate;\n\t\tstruct {\n\t\t\tu8 rate_per_lane;\n\t\t\tu8 lanes;\n\t\t} frl;\n\t};\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n\tstruct phy_configure_opts_lvds lvds;\n\tstruct phy_configure_opts_hdmi hdmi;\n};\n\nstruct phylink;\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[1];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tlong unsigned int adv_old[2];\n\tlong unsigned int supported_eee[2];\n\tlong unsigned int advertising_eee[2];\n\tlong unsigned int eee_disabled_modes[2];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[1];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nunion phy_notify {\n\tenum phy_ufs_state ufs_state;\n};\n\nstruct phy_ops {\n\tint (*init)(struct phy___3 *);\n\tint (*exit)(struct phy___3 *);\n\tint (*power_on)(struct phy___3 *);\n\tint (*power_off)(struct phy___3 *);\n\tint (*set_mode)(struct phy___3 *, enum phy_mode, int);\n\tint (*set_media)(struct phy___3 *, enum phy_media);\n\tint (*set_speed)(struct phy___3 *, int);\n\tint (*configure)(struct phy___3 *, union phy_configure_opts *);\n\tint (*validate)(struct phy___3 *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy___3 *);\n\tint (*calibrate)(struct phy___3 *);\n\tint (*connect)(struct phy___3 *, int);\n\tint (*disconnect)(struct phy___3 *, int);\n\tint (*notify_phystate)(struct phy___3 *, union phy_notify);\n\tvoid (*release)(struct phy___3 *);\n\tstruct module *owner;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_port_ops;\n\nstruct phy_port {\n\tstruct list_head head;\n\tenum phy_port_parent parent_type;\n\tunion {\n\t\tstruct phy_device *phy;\n\t};\n\tconst struct phy_port_ops *ops;\n\tint pairs;\n\tlong unsigned int mediums;\n\tlong unsigned int supported[2];\n\tlong unsigned int interfaces[1];\n\tunsigned int not_described: 1;\n\tunsigned int active: 1;\n\tunsigned int is_mii: 1;\n\tunsigned int is_sfp: 1;\n};\n\nstruct phy_port_ops {\n\tvoid (*link_up)(struct phy_port *);\n\tvoid (*link_down)(struct phy_port *);\n\tint (*configure_mii)(struct phy_port *, bool, phy_interface_t);\n};\n\nstruct phy_reg {\n\tu16 reg;\n\tu16 val;\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phylib_stubs {\n\tint (*hwtstamp_get)(struct phy_device *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct phy_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_ext_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct fs_pin *bacct;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidff_usage {\n\tstruct hid_field *field;\n\ts32 *value;\n};\n\nstruct pidff_effect {\n\tint pid_id;\n\tint is_infinite;\n\tunsigned int loop_count;\n};\n\nstruct pidff_device {\n\tstruct hid_device *hid;\n\tstruct hid_report *reports[13];\n\tstruct pidff_usage set_effect[7];\n\tstruct pidff_usage set_envelope[5];\n\tstruct pidff_usage set_condition[8];\n\tstruct pidff_usage set_periodic[5];\n\tstruct pidff_usage set_constant[2];\n\tstruct pidff_usage set_ramp[3];\n\tstruct pidff_usage device_gain[1];\n\tstruct pidff_usage block_load[2];\n\tstruct pidff_usage pool[3];\n\tstruct pidff_usage effect_operation[2];\n\tstruct pidff_usage block_free[1];\n\tstruct pidff_effect effect[64];\n\tstruct hid_field *create_new_effect_type;\n\tstruct hid_field *set_effect_type;\n\tstruct hid_field *effect_direction;\n\tstruct hid_field *axes_enable;\n\tstruct hid_field *device_control;\n\tstruct hid_field *block_load_status;\n\tstruct hid_field *effect_operation_status;\n\tint control_id[6];\n\tint type_id[11];\n\tint status_id[3];\n\tint operation_id[2];\n\tint direction_axis_id[9];\n\tu32 quirks;\n\tu8 effect_count;\n\tu8 axis_count;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pids_cgroup {\n\tstruct cgroup_subsys_state css;\n\tatomic64_t counter;\n\tatomic64_t limit;\n\tint64_t watermark;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tatomic64_t events[2];\n\tatomic64_t events_local[2];\n};\n\nstruct piix_host_priv {\n\tconst int *map;\n\tu32 saved_iocfg;\n\tvoid *sidpr;\n};\n\nstruct piix_map_db {\n\tconst u32 mask;\n\tconst u16 port_enable;\n\tconst int map[0];\n};\n\nstruct pimreghdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__be16 csum;\n\t__be32 flags;\n};\n\nstruct pinctrl_map_mux {\n\tconst char *group;\n\tconst char *function;\n};\n\nstruct pinctrl_map_configs {\n\tconst char *group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_map {\n\tconst char *dev_name;\n\tconst char *name;\n\tenum pinctrl_map_type type;\n\tconst char *ctrl_dev_name;\n\tunion {\n\t\tstruct pinctrl_map_mux mux;\n\t\tstruct pinctrl_map_configs configs;\n\t} data;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe_buffer;\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nstruct pipe_fault_handler {\n\tbool (*handle)(struct intel_crtc *, enum plane_id);\n\tu32 fault;\n\tenum plane_id plane_id;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct pipe_wait {\n\tstruct trace_iterator *iter;\n\tint wait_index;\n};\n\nstruct pixel_format {\n\tunsigned char bits_per_pixel;\n\tbool indexed;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} alpha;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} red;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} green;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} blue;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char offset;\n\t\t\tunsigned char length;\n\t\t} index;\n\t};\n};\n\nstruct pkcs1pad_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct pkcs1pad_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n};\n\nstruct pkcs1pad_request {\n\tstruct scatterlist in_sg[2];\n\tstruct scatterlist out_sg[1];\n\tuint8_t *in_buf;\n\tuint8_t *out_buf;\n\tstruct akcipher_request child_req;\n};\n\nstruct x509_certificate;\n\nstruct pkcs7_signed_info;\n\nstruct pkcs7_message {\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate *crl;\n\tstruct pkcs7_signed_info *signed_infos;\n\tu8 version;\n\tbool have_authattrs;\n\tenum OID data_type;\n\tsize_t data_len;\n\tsize_t data_hdrlen;\n\tconst void *data;\n};\n\nstruct pkcs7_parse_context {\n\tstruct pkcs7_message *msg;\n\tstruct pkcs7_signed_info *sinfo;\n\tstruct pkcs7_signed_info **ppsinfo;\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate **ppcerts;\n\tlong unsigned int data;\n\tenum OID last_oid;\n\tunsigned int x509_index;\n\tunsigned int sinfo_index;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_skid;\n\tunsigned int raw_skid_size;\n\tbool expect_skid;\n};\n\nstruct pkcs7_signed_info {\n\tstruct pkcs7_signed_info *next;\n\tstruct x509_certificate *signer;\n\tunsigned int index;\n\tbool unsupported_crypto;\n\tbool blacklisted;\n\tconst void *msgdigest;\n\tunsigned int msgdigest_len;\n\tunsigned int authattrs_len;\n\tconst void *authattrs;\n\tlong unsigned int aa_set;\n\ttime64_t signing_time;\n\tstruct public_key_signature *sig;\n};\n\nstruct pkru_state {\n\tu32 pkru;\n\tu32 pad;\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tunsigned int uartclk;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tunsigned int type;\n\tupf_t flags;\n\tu16 bugs;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n};\n\nstruct stepping_desc {\n\tconst enum intel_step *map;\n\tsize_t size;\n};\n\nstruct subplatform_desc;\n\nstruct platform_desc {\n\tstruct intel_display_platforms platforms;\n\tconst char *name;\n\tconst struct subplatform_desc *subplatforms;\n\tconst struct intel_display_device_info *info;\n\tstruct stepping_desc step_info;\n};\n\nstruct mfd_cell;\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_hibernation_ops {\n\tint (*begin)(pm_message_t);\n\tvoid (*end)(void);\n\tint (*pre_snapshot)(void);\n\tvoid (*finish)(void);\n\tint (*prepare)(void);\n\tint (*enter)(void);\n\tvoid (*leave)(void);\n\tint (*pre_restore)(void);\n\tvoid (*restore_cleanup)(void);\n\tvoid (*recover)(void);\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)(void);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tvoid (*check)(void);\n\tbool (*wake)(void);\n\tvoid (*restore_early)(void);\n\tvoid (*restore)(void);\n\tvoid (*end)(void);\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)(void);\n\tvoid (*finish)(void);\n\tbool (*suspend_again)(void);\n\tvoid (*end)(void);\n\tvoid (*recover)(void);\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct plff_device {\n\tstruct hid_report *report;\n\ts32 maxval;\n\ts32 *strong;\n\ts32 *weak;\n};\n\nstruct pll_output_params {\n\tu32 ssc_up_spread;\n\tu32 mpll_div5_en;\n\tu32 hdmi_div;\n\tu32 ana_cp_int;\n\tu32 ana_cp_prop;\n\tu32 refclk_postscalar;\n\tu32 tx_clk_div;\n\tu32 fracn_quot;\n\tu32 fracn_rem;\n\tu32 fracn_den;\n\tu32 fracn_en;\n\tu32 pmix_en;\n\tu32 multiplier;\n\tint mpll_ana_v2i;\n\tint ana_freq_vco;\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct pmap {\n\tsize_t offset;\n\tconst char *name;\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct pnfs_block_dev_map;\n\nstruct pnfs_block_dev {\n\tstruct nfs4_deviceid_node node;\n\tu64 start;\n\tu64 len;\n\tenum pnfs_block_volume_type type;\n\tu32 nr_children;\n\tstruct pnfs_block_dev *children;\n\tu64 chunk_size;\n\tstruct file *bdev_file;\n\tu64 disk_offset;\n\tlong unsigned int flags;\n\tu64 pr_key;\n\tbool (*map)(struct pnfs_block_dev *, u64, struct pnfs_block_dev_map *);\n};\n\nstruct pnfs_block_dev_map {\n\tu64 start;\n\tu64 len;\n\tu64 disk_offset;\n\tstruct block_device *bdev;\n};\n\nstruct pnfs_block_extent {\n\tunion {\n\t\tstruct rb_node be_node;\n\t\tstruct list_head be_list;\n\t};\n\tstruct nfs4_deviceid_node *be_device;\n\tsector_t be_f_offset;\n\tsector_t be_length;\n\tsector_t be_v_offset;\n\tenum pnfs_block_extent_state be_state;\n\tunsigned int be_tag;\n};\n\nstruct pnfs_block_layout {\n\tstruct pnfs_layout_hdr bl_layout;\n\tstruct rb_root bl_ext_rw;\n\tstruct rb_root bl_ext_ro;\n\tspinlock_t bl_ext_lock;\n\tbool bl_scsi_layout;\n\tu64 bl_lwb;\n};\n\nstruct pnfs_block_volume {\n\tenum pnfs_block_volume_type type;\n\tunion {\n\t\tstruct {\n\t\t\tint len;\n\t\t\tint nr_sigs;\n\t\t\tstruct {\n\t\t\t\tu64 offset;\n\t\t\t\tu32 sig_len;\n\t\t\t\tu8 sig[128];\n\t\t\t} sigs[4];\n\t\t} simple;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 len;\n\t\t\tu32 volume;\n\t\t} slice;\n\t\tstruct {\n\t\t\tu32 volumes_count;\n\t\t\tu32 volumes[64];\n\t\t} concat;\n\t\tstruct {\n\t\t\tu64 chunk_size;\n\t\t\tu32 volumes_count;\n\t\t\tu32 volumes[64];\n\t\t} stripe;\n\t\tstruct {\n\t\t\tenum scsi_code_set code_set;\n\t\t\tenum scsi_designator_type designator_type;\n\t\t\tint designator_len;\n\t\t\tu8 designator[256];\n\t\t\tu64 pr_key;\n\t\t} scsi;\n\t};\n};\n\nstruct pnfs_commit_bucket {\n\tstruct list_head written;\n\tstruct list_head committing;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_writeverf direct_verf;\n};\n\nstruct pnfs_commit_array {\n\tstruct list_head cinfo_list;\n\tstruct list_head lseg_list;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tunsigned int nbuckets;\n\tstruct pnfs_commit_bucket buckets[0];\n};\n\nstruct pnfs_commit_ops {\n\tvoid (*setup_ds_info)(struct pnfs_ds_commit_info *, struct pnfs_layout_segment *);\n\tvoid (*release_ds_info)(struct pnfs_ds_commit_info *, struct inode *);\n\tint (*commit_pagelist)(struct inode *, struct list_head *, int, struct nfs_commit_info *);\n\tvoid (*mark_request_commit)(struct nfs_page *, struct pnfs_layout_segment *, struct nfs_commit_info *, u32);\n\tvoid (*clear_request_commit)(struct nfs_page *, struct nfs_commit_info *);\n\tint (*scan_commit_lists)(struct nfs_commit_info *, int);\n\tvoid (*recover_commit_reqs)(struct list_head *, struct nfs_commit_info *);\n};\n\nstruct pnfs_device {\n\tstruct nfs4_deviceid dev_id;\n\tunsigned int layout_type;\n\tunsigned int mincount;\n\tunsigned int maxcount;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tunsigned char nocache: 1;\n};\n\nstruct pnfs_layoutdriver_type {\n\tstruct list_head pnfs_tblid;\n\tconst u32 id;\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int flags;\n\tunsigned int max_layoutget_response;\n\tint (*set_layoutdriver)(struct nfs_server *, const struct nfs_fh *);\n\tint (*clear_layoutdriver)(struct nfs_server *);\n\tstruct pnfs_layout_hdr * (*alloc_layout_hdr)(struct inode *, gfp_t);\n\tvoid (*free_layout_hdr)(struct pnfs_layout_hdr *);\n\tstruct pnfs_layout_segment * (*alloc_lseg)(struct pnfs_layout_hdr *, struct nfs4_layoutget_res *, gfp_t);\n\tvoid (*free_lseg)(struct pnfs_layout_segment *);\n\tvoid (*add_lseg)(struct pnfs_layout_hdr *, struct pnfs_layout_segment *, struct list_head *);\n\tvoid (*return_range)(struct pnfs_layout_hdr *, struct pnfs_layout_range *);\n\tconst struct nfs_pageio_ops *pg_read_ops;\n\tconst struct nfs_pageio_ops *pg_write_ops;\n\tstruct pnfs_ds_commit_info * (*get_ds_info)(struct inode *);\n\tint (*sync)(struct inode *, bool);\n\tenum pnfs_try_status (*read_pagelist)(struct nfs_pgio_header *);\n\tenum pnfs_try_status (*write_pagelist)(struct nfs_pgio_header *, int);\n\tvoid (*free_deviceid_node)(struct nfs4_deviceid_node *);\n\tstruct nfs4_deviceid_node * (*alloc_deviceid_node)(struct nfs_server *, struct pnfs_device *, gfp_t);\n\tint (*prepare_layoutreturn)(struct nfs4_layoutreturn_args *);\n\tvoid (*cleanup_layoutcommit)(struct nfs4_layoutcommit_data *);\n\tint (*prepare_layoutcommit)(struct nfs4_layoutcommit_args *);\n\tint (*prepare_layoutstats)(struct nfs42_layoutstat_args *);\n\tvoid (*cancel_io)(struct pnfs_layout_segment *);\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_device_id;\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_link;\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_dma {\n\tunsigned char map;\n\tunsigned char flags;\n};\n\nstruct pnp_fixup {\n\tchar id[8];\n\tvoid (*quirk_function)(struct pnp_dev *);\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_info_buffer {\n\tchar *buffer;\n\tchar *curr;\n\tlong unsigned int size;\n\tlong unsigned int len;\n\tint stop;\n\tint error;\n};\n\ntypedef struct pnp_info_buffer pnp_info_buffer_t;\n\nstruct pnp_irq {\n\tpnp_irq_mask_t map;\n\tunsigned char flags;\n};\n\nstruct pnp_mem {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_port {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_option {\n\tstruct list_head list;\n\tunsigned int flags;\n\tlong unsigned int type;\n\tunion {\n\t\tstruct pnp_port port;\n\t\tstruct pnp_irq irq;\n\t\tstruct pnp_dma dma;\n\t\tstruct pnp_mem mem;\n\t} u;\n};\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pnp_resource {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct policy_file;\n\nstruct policy_data {\n\tstruct policydb *p;\n\tstruct policy_file *fp;\n};\n\nstruct policy_file {\n\tchar *data;\n\tsize_t len;\n};\n\nstruct policy_load_memory {\n\tsize_t len;\n\tvoid *data;\n};\n\nstruct role_datum;\n\nstruct user_datum;\n\nstruct type_datum;\n\nstruct role_allow;\n\nstruct policydb {\n\tint mls_enabled;\n\tstruct symtab symtab[8];\n\tchar **sym_val_to_name[8];\n\tstruct class_datum **class_val_to_struct;\n\tstruct role_datum **role_val_to_struct;\n\tstruct user_datum **user_val_to_struct;\n\tstruct type_datum **type_val_to_struct;\n\tstruct avtab te_avtab;\n\tstruct hashtab role_tr;\n\tstruct ebitmap filename_trans_ttypes;\n\tstruct hashtab filename_trans;\n\tu32 compat_filename_trans_count;\n\tstruct cond_bool_datum **bool_val_to_struct;\n\tstruct avtab te_cond_avtab;\n\tstruct cond_node *cond_list;\n\tu32 cond_list_len;\n\tstruct role_allow *role_allow;\n\tstruct ocontext *ocontexts[9];\n\tstruct genfs *genfs;\n\tstruct hashtab range_tr;\n\tstruct ebitmap *type_attr_map_array;\n\tstruct ebitmap policycaps;\n\tstruct ebitmap permissive_map;\n\tstruct ebitmap neveraudit_map;\n\tsize_t len;\n\tunsigned int policyvers;\n\tunsigned int reject_unknown: 1;\n\tunsigned int allow_unknown: 1;\n\tu16 process_class;\n\tu32 process_trans_perms;\n};\n\nstruct policydb_compat_info {\n\tunsigned int version;\n\tunsigned int sym_num;\n\tunsigned int ocon_num;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[9];\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct port_stats {\n\tlong unsigned int bytes_sent;\n\tlong unsigned int bytes_received;\n\tlong unsigned int bytes_discarded;\n};\n\nstruct ports_device;\n\nstruct port_buffer;\n\nstruct virtqueue;\n\nstruct port___3 {\n\tstruct list_head list;\n\tstruct ports_device *portdev;\n\tstruct port_buffer *inbuf;\n\tspinlock_t inbuf_lock;\n\tspinlock_t outvq_lock;\n\tstruct virtqueue *in_vq;\n\tstruct virtqueue *out_vq;\n\tstruct dentry *debugfs_file;\n\tstruct port_stats stats;\n\tstruct console___2 cons;\n\tstruct cdev *cdev;\n\tstruct device *dev;\n\tstruct kref kref;\n\twait_queue_head_t waitqueue;\n\tchar *name;\n\tstruct fasync_struct *async_queue;\n\tu32 id;\n\tbool outvq_full;\n\tbool host_connected;\n\tbool guest_connected;\n};\n\nstruct port_buffer {\n\tchar *buf;\n\tsize_t size;\n\tsize_t len;\n\tsize_t offset;\n\tdma_addr_t dma;\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int sgpages;\n\tstruct scatterlist sg[0];\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct portdrv_service_data {\n\tstruct pcie_port_service_driver *drv;\n\tstruct device *dev;\n\tu32 service;\n};\n\nstruct virtio_console_control {\n\t__virtio32 id;\n\t__virtio16 event;\n\t__virtio16 value;\n};\n\nstruct virtio_device;\n\nstruct ports_device {\n\tstruct list_head list;\n\tstruct work_struct control_work;\n\tstruct work_struct config_work;\n\tstruct list_head ports;\n\tspinlock_t ports_lock;\n\tspinlock_t c_ivq_lock;\n\tspinlock_t c_ovq_lock;\n\tu32 max_nr_ports;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *c_ivq;\n\tstruct virtqueue *c_ovq;\n\tstruct virtio_console_control cpkt;\n\tstruct virtqueue **in_vqs;\n\tstruct virtqueue **out_vqs;\n\tint chr_major;\n};\n\nstruct ports_driver_data {\n\tstruct dentry *debugfs_dir;\n\tstruct list_head portdevs;\n\tstruct list_head consoles;\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct posix_cputimers_work {\n\tstruct callback_head work;\n\tstruct mutex mutex;\n\tunsigned int scheduled;\n};\n\nstruct posix_msg_tree_node {\n\tstruct rb_node rb_node;\n\tstruct list_head msg_list;\n\tint priority;\n};\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct power_supply_battery_info;\n\nstruct power_supply {\n\tconst struct power_supply_desc *desc;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tchar **supplied_from;\n\tsize_t num_supplies;\n\tvoid *drv_data;\n\tstruct device dev;\n\tstruct work_struct changed_work;\n\tstruct delayed_work deferred_register_work;\n\tspinlock_t changed_lock;\n\tbool changed;\n\tbool update_groups;\n\tbool initialized;\n\tbool removing;\n\tatomic_t use_cnt;\n\tstruct power_supply_battery_info *battery_info;\n\tstruct rw_semaphore extensions_sem;\n\tstruct list_head extensions;\n\tstruct thermal_zone_device *tzd;\n\tstruct thermal_cooling_device *tcd;\n\tstruct led_trigger *trig;\n\tstruct led_trigger *charging_trig;\n\tstruct led_trigger *full_trig;\n\tstruct led_trigger *charging_blink_full_solid_trig;\n\tstruct led_trigger *charging_orange_full_green_trig;\n};\n\nstruct power_supply_attr {\n\tconst char *prop_name;\n\tchar attr_name[31];\n\tstruct device_attribute dev_attr;\n\tconst char * const *text_values;\n\tint text_values_len;\n};\n\nstruct power_supply_maintenance_charge_table;\n\nstruct power_supply_battery_ocv_table;\n\nstruct power_supply_resistance_temp_table;\n\nstruct power_supply_vbat_ri_table;\n\nstruct power_supply_battery_info {\n\tunsigned int technology;\n\tint energy_full_design_uwh;\n\tint charge_full_design_uah;\n\tint voltage_min_design_uv;\n\tint voltage_max_design_uv;\n\tint tricklecharge_current_ua;\n\tint precharge_current_ua;\n\tint precharge_voltage_max_uv;\n\tint charge_term_current_ua;\n\tint charge_restart_voltage_uv;\n\tint overvoltage_limit_uv;\n\tint constant_charge_current_max_ua;\n\tint constant_charge_voltage_max_uv;\n\tconst struct power_supply_maintenance_charge_table *maintenance_charge;\n\tint maintenance_charge_size;\n\tint alert_low_temp_charge_current_ua;\n\tint alert_low_temp_charge_voltage_uv;\n\tint alert_high_temp_charge_current_ua;\n\tint alert_high_temp_charge_voltage_uv;\n\tint factory_internal_resistance_uohm;\n\tint factory_internal_resistance_charging_uohm;\n\tint ocv_temp[20];\n\tint temp_ambient_alert_min;\n\tint temp_ambient_alert_max;\n\tint temp_alert_min;\n\tint temp_alert_max;\n\tint temp_min;\n\tint temp_max;\n\tconst struct power_supply_battery_ocv_table *ocv_table[20];\n\tint ocv_table_size[20];\n\tconst struct power_supply_resistance_temp_table *resist_table;\n\tint resist_table_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_discharging;\n\tint vbat2ri_discharging_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_charging;\n\tint vbat2ri_charging_size;\n\tint bti_resistance_ohm;\n\tint bti_resistance_tolerance;\n};\n\nstruct power_supply_battery_ocv_table {\n\tint ocv;\n\tint capacity;\n};\n\nstruct power_supply_config {\n\tstruct fwnode_handle *fwnode;\n\tvoid *drv_data;\n\tconst struct attribute_group **attr_grp;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tbool no_wakeup_source;\n};\n\nstruct power_supply_ext {\n\tconst char * const name;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property);\n};\n\nstruct power_supply_ext_registration {\n\tstruct list_head list_head;\n\tconst struct power_supply_ext *ext;\n\tstruct device *dev;\n\tvoid *data;\n};\n\nstruct power_supply_hwmon {\n\tstruct power_supply *psy;\n\tlong unsigned int *props;\n};\n\nstruct power_supply_led_trigger {\n\tstruct led_trigger trig;\n\tstruct power_supply *psy;\n};\n\nstruct power_supply_maintenance_charge_table {\n\tint charge_current_max_ua;\n\tint charge_voltage_max_uv;\n\tint charge_safety_timer_minutes;\n};\n\nunion power_supply_propval {\n\tint intval;\n\tconst char *strval;\n};\n\nstruct power_supply_resistance_temp_table {\n\tint temp;\n\tint resistance;\n};\n\nstruct power_supply_vbat_ri_table {\n\tint vbat_uv;\n\tint ri_uohm;\n};\n\nstruct ppin_info {\n\tint feature;\n\tint msr_ppin_ctl;\n\tint msr_ppin;\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pps_bind_args {\n\tint tsformat;\n\tint edge;\n\tint consumer;\n};\n\nstruct pps_device;\n\nstruct pps_source_info {\n\tchar name[32];\n\tchar path[32];\n\tint mode;\n\tvoid (*echo)(struct pps_device *, int, void *);\n\tstruct module *owner;\n\tstruct device *dev;\n};\n\nstruct pps_ktime {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kparams {\n\tint api_version;\n\tint mode;\n\tstruct pps_ktime assert_off_tu;\n\tstruct pps_ktime clear_off_tu;\n};\n\nstruct pps_device {\n\tstruct pps_source_info info;\n\tstruct pps_kparams params;\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tunsigned int last_ev;\n\tunsigned int last_fetched_ev;\n\twait_queue_head_t queue;\n\tunsigned int id;\n\tconst void *lookup_cookie;\n\tstruct device dev;\n\tstruct fasync_struct *async_queue;\n\tspinlock_t lock;\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct pps_kinfo {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n};\n\nstruct pps_fdata {\n\tstruct pps_kinfo info;\n\tstruct pps_ktime timeout;\n};\n\nstruct pps_ktime_compat {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kinfo_compat {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime_compat assert_tu;\n\tstruct pps_ktime_compat clear_tu;\n\tint current_mode;\n} __attribute__((packed));\n\nstruct pps_fdata_compat {\n\tstruct pps_kinfo_compat info;\n\tstruct pps_ktime_compat timeout;\n} __attribute__((packed));\n\nstruct pps_registers {\n\ti915_reg_t pp_ctrl;\n\ti915_reg_t pp_stat;\n\ti915_reg_t pp_on;\n\ti915_reg_t pp_off;\n\ti915_reg_t pp_div;\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n};\n\nstruct prefix_cacheinfo {\n\t__u32 preferred_time;\n\t__u32 valid_time;\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\tunion {\n\t\t__u8 flags;\n\t\tstruct {\n\t\t\t__u8 reserved: 4;\n\t\t\t__u8 preferpd: 1;\n\t\t\t__u8 routeraddr: 1;\n\t\t\t__u8 autoconf: 1;\n\t\t\t__u8 onlink: 1;\n\t\t};\n\t};\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct prefixmsg {\n\tunsigned char prefix_family;\n\tunsigned char prefix_pad1;\n\tshort unsigned int prefix_pad2;\n\tint prefix_ifindex;\n\tunsigned char prefix_type;\n\tunsigned char prefix_len;\n\tunsigned char prefix_flags;\n\tunsigned char prefix_pad3;\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct prioq_match_arg {\n\tint client;\n\tint timestamp;\n};\n\nstruct snd_seq_remove_events;\n\nstruct prioq_remove_match_arg {\n\tint client;\n\tstruct snd_seq_remove_events *info;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\nstruct prm_buffer {\n\tu8 prm_status;\n\tu64 efi_status;\n\tu8 prm_cmd;\n\tguid_t handler_guid;\n} __attribute__((packed));\n\nstruct prm_mmio_info;\n\nstruct prm_context_buffer {\n\tchar signature[4];\n\tu16 revision;\n\tu16 reserved;\n\tguid_t identifier;\n\tu64 static_data_buffer;\n\tstruct prm_mmio_info *mmio_ranges;\n};\n\nstruct prm_handler_info {\n\tefi_guid_t guid;\n\tefi_status_t (*handler_addr)(u64, void *);\n\tu64 static_data_buffer_addr;\n\tu64 acpi_param_buffer_addr;\n\tstruct list_head handler_list;\n};\n\nstruct prm_mmio_addr_range {\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu32 length;\n} __attribute__((packed));\n\nstruct prm_mmio_info {\n\tu64 mmio_count;\n\tstruct prm_mmio_addr_range addr_ranges[0];\n};\n\nstruct prm_module_info {\n\tguid_t guid;\n\tu16 major_rev;\n\tu16 minor_rev;\n\tu16 handler_count;\n\tstruct prm_mmio_info *mmio_info;\n\tbool updatable;\n\tstruct list_head module_list;\n\tstruct prm_handler_info handlers[0];\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct probe_entry_arg {\n\tstruct fetch_insn *code;\n\tunsigned int size;\n};\n\nstruct probe_resp {\n\tstruct callback_head callback_head;\n\tint len;\n\tu16 cntdwn_counter_offsets[2];\n\tu8 data[0];\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n};\n\nstruct sid_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct ptrace_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t tracer_pid;\n\t__kernel_pid_t tracer_tgid;\n};\n\nstruct proc_event {\n\tenum proc_cn_event what;\n\t__u32 cpu;\n\t__u64 timestamp_ns;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 err;\n\t\t} ack;\n\t\tstruct fork_proc_event fork;\n\t\tstruct exec_proc_event exec;\n\t\tstruct id_proc_event id;\n\t\tstruct sid_proc_event sid;\n\t\tstruct ptrace_proc_event ptrace;\n\t\tstruct comm_proc_event comm;\n\t\tstruct coredump_proc_event coredump;\n\t\tstruct exit_proc_event exit;\n\t} event_data;\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_input {\n\tenum proc_cn_mcast_op mcast_op;\n\tenum proc_cn_event event_type;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_nfs_info {\n\tint flag;\n\tconst char *str;\n\tconst char *nostr;\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*proc_compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tstruct timespec64 val;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct pt_amdv1 {\n\tstruct pt_common common;\n};\n\nstruct pt_iommu_amdv1 {\n\tstruct pt_iommu iommu;\n\tstruct pt_amdv1 amdpt;\n};\n\nstruct protection_domain {\n\tunion {\n\t\tstruct iommu_domain domain;\n\t\tstruct pt_iommu iommu;\n\t\tstruct pt_iommu_amdv1 amdv1;\n\t\tstruct pt_iommu_x86_64 amdv2;\n\t};\n\tstruct list_head dev_list;\n\tspinlock_t lock;\n\tu16 id;\n\tenum protection_domain_mode pd_mode;\n\tbool dirty_tracking;\n\tstruct xarray iommu_array;\n\tstruct mmu_notifier mn;\n\tstruct list_head dev_data_list;\n\tstruct list_head viommu_list;\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*compat_ioctl)(struct sock *, unsigned int, long unsigned int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct prt_quirk {\n\tconst struct dmi_system_id *system;\n\tunsigned int segment;\n\tunsigned int bus;\n\tunsigned int device;\n\tunsigned char pin;\n\tconst char *source;\n\tconst char *actual_source;\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct psample_group {\n\tstruct list_head list;\n\tstruct net *net;\n\tu32 group_num;\n\tu32 refcount;\n\tu32 seq;\n\tstruct callback_head rcu;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psi_group {};\n\nstruct psmouse_protocol;\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct pstate_funcs {\n\tint (*get_max)(int);\n\tint (*get_max_physical)(int);\n\tint (*get_min)(int);\n\tint (*get_turbo)(int);\n\tint (*get_scaling)(void);\n\tint (*get_cpu_scaling)(int);\n\tint (*get_aperf_mperf_shift)(void);\n\tu64 (*get_val)(struct cpudata *, int);\n\tvoid (*get_vid)(struct cpudata *);\n};\n\nstruct psy_am_i_supplied_data {\n\tstruct power_supply *psy;\n\tunsigned int count;\n};\n\nstruct psy_for_each_psy_cb_data {\n\tint (*fn)(struct power_supply *, void *);\n\tvoid *data;\n};\n\nstruct psy_get_supplier_prop_data {\n\tstruct power_supply *psy;\n\tenum power_supply_property psp;\n\tunion power_supply_propval *val;\n};\n\nstruct pt_filter {\n\tlong unsigned int msr_a;\n\tlong unsigned int msr_b;\n\tlong unsigned int config;\n};\n\nstruct pt_filters {\n\tstruct pt_filter filter[4];\n\tunsigned int nr_filters;\n};\n\nstruct pt {\n\tstruct perf_output_handle handle;\n\tstruct pt_filters filters;\n\tint handle_nmi;\n\tint vmx_on;\n\tint pause_allowed;\n\tint resume_allowed;\n\tu64 output_base;\n\tu64 output_mask;\n};\n\nstruct pt_address_range {\n\tlong unsigned int msr_a;\n\tlong unsigned int msr_b;\n\tunsigned int reg_off;\n};\n\nstruct topa;\n\nstruct topa_entry;\n\nstruct pt_buffer {\n\tstruct list_head tables;\n\tstruct topa *first;\n\tstruct topa *last;\n\tstruct topa *cur;\n\tunsigned int cur_idx;\n\tsize_t output_off;\n\tlong unsigned int nr_pages;\n\tlocal_t data_size;\n\tlocal64_t head;\n\tbool snapshot;\n\tbool single;\n\tbool wrapped;\n\tlong int stop_pos;\n\tlong int intr_pos;\n\tstruct topa_entry *stop_te;\n\tstruct topa_entry *intr_te;\n\tvoid **data_pages;\n};\n\nstruct pt_cap_desc {\n\tconst char *name;\n\tu32 leaf;\n\tu8 reg;\n\tu32 mask;\n};\n\nstruct pt_iommu_cfg {\n\tunsigned int features;\n\tu8 hw_max_vasz_lg2;\n\tu8 hw_max_oasz_lg2;\n};\n\nstruct pt_iommu_amdv1_cfg {\n\tstruct pt_iommu_cfg common;\n\tunsigned int starting_level;\n};\n\nstruct pt_iommu_amdv1_hw_info {\n\tu64 host_pt_root;\n\tu8 mode;\n};\n\nstruct pt_iommu_collect_args {\n\tstruct iommu_pages_list free_list;\n\tu8 check_mapped: 1;\n};\n\nstruct pt_iommu_dirty_args {\n\tstruct iommu_dirty_bitmap *dirty;\n\tunsigned int flags;\n};\n\nstruct pt_iommu_driver_ops {\n\tvoid (*change_top)(struct pt_iommu *, phys_addr_t, unsigned int);\n\tspinlock_t * (*get_top_lock)(struct pt_iommu *);\n};\n\nstruct pt_iommu_info {\n\tu64 pgsize_bitmap;\n};\n\nstruct vtdss_pt_write_attrs {\n\tu64 descriptor_bits;\n\tgfp_t gfp;\n};\n\nstruct pt_iommu_map_args {\n\tstruct iommu_iotlb_gather *iotlb_gather;\n\tstruct vtdss_pt_write_attrs attrs;\n\tpt_oaddr_t oa;\n\tunsigned int leaf_pgsize_lg2;\n\tunsigned int leaf_level;\n};\n\nstruct x86_64_pt_write_attrs {\n\tu64 descriptor_bits;\n\tgfp_t gfp;\n};\n\nstruct pt_iommu_map_args___2 {\n\tstruct iommu_iotlb_gather *iotlb_gather;\n\tstruct x86_64_pt_write_attrs attrs;\n\tpt_oaddr_t oa;\n\tunsigned int leaf_pgsize_lg2;\n\tunsigned int leaf_level;\n};\n\nstruct pt_iommu_map_args___3 {\n\tstruct iommu_iotlb_gather *iotlb_gather;\n\tstruct amdv1pt_write_attrs attrs;\n\tpt_oaddr_t oa;\n\tunsigned int leaf_pgsize_lg2;\n\tunsigned int leaf_level;\n};\n\nstruct pt_iommu_ops {\n\tint (*set_dirty)(struct pt_iommu *, dma_addr_t);\n\tvoid (*get_info)(struct pt_iommu *, struct pt_iommu_info *);\n\tvoid (*deinit)(struct pt_iommu *);\n};\n\nstruct pt_iommu_vtdss_cfg {\n\tstruct pt_iommu_cfg common;\n\tunsigned int top_level;\n};\n\nstruct pt_iommu_vtdss_hw_info {\n\tu64 ssptptr;\n\tu8 aw;\n};\n\nstruct pt_iommu_x86_64_cfg {\n\tstruct pt_iommu_cfg common;\n\tunsigned int top_level;\n};\n\nstruct pt_iommu_x86_64_hw_info {\n\tu64 gcr3_pt;\n\tu8 levels;\n};\n\nstruct pt_pmu {\n\tstruct pmu pmu;\n\tu32 caps[8];\n\tbool vmx;\n\tbool branch_en_always_on;\n\tlong unsigned int max_nonturbo_ratio;\n\tunsigned int tsc_art_num;\n\tunsigned int tsc_art_den;\n};\n\nstruct pt_table_p;\n\nstruct pt_range {\n\tstruct pt_common *common;\n\tstruct pt_table_p *top_table;\n\tpt_vaddr_t va;\n\tpt_vaddr_t last_va;\n\tu8 top_level;\n\tu8 max_vasz_lg2;\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\nstruct pt_state {\n\tstruct pt_range *range;\n\tstruct pt_table_p *table;\n\tstruct pt_table_p *table_lower;\n\tu64 entry;\n\tenum pt_entry_type type;\n\tshort unsigned int index;\n\tshort unsigned int end_index;\n\tu8 level;\n};\n\nstruct pt_unmap_args {\n\tstruct iommu_pages_list free_list;\n\tpt_vaddr_t unmapped;\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t\tatomic_t pt_share_count;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n};\n\nstruct ptdump_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct ptp_clock {\n\tstruct posix_clock clock;\n\tstruct device dev;\n\tstruct ptp_clock_info *info;\n\tdev_t devid;\n\tint index;\n\tstruct pps_device *pps_source;\n\tlong int dialed_frequency;\n\tstruct list_head tsevqs;\n\tspinlock_t tsevqs_lock;\n\tstruct mutex pincfg_mux;\n\twait_queue_head_t tsev_wq;\n\tint defunct;\n\tstruct device_attribute *pin_dev_attr;\n\tstruct attribute **pin_attr;\n\tstruct attribute_group pin_attr_group;\n\tconst struct attribute_group *pin_attr_groups[2];\n\tstruct kthread_worker *kworker;\n\tstruct kthread_delayed_work aux_work;\n\tunsigned int max_vclocks;\n\tunsigned int n_vclocks;\n\tint *vclock_index;\n\tstruct mutex n_vclocks_mux;\n\tbool is_virtual_clock;\n\tbool has_cycles;\n\tstruct dentry *debugfs_root;\n};\n\nstruct ptp_clock_caps {\n\tint max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint pps;\n\tint n_pins;\n\tint cross_timestamping;\n\tint adjust_phase;\n\tint max_phase_adj;\n\tint rsv[11];\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\ts64 offset;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_perout_request {\n\tunion {\n\t\tstruct ptp_clock_time start;\n\t\tstruct ptp_clock_time phase;\n\t};\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunion {\n\t\tstruct ptp_clock_time on;\n\t\tunsigned int rsv[4];\n\t};\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_extts_event {\n\tstruct ptp_clock_time t;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct ptp_sys_offset {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[51];\n};\n\nstruct ptp_sys_offset_extended {\n\tunsigned int n_samples;\n\t__kernel_clockid_t clockid;\n\tunsigned int rsv[2];\n\tstruct ptp_clock_time ts[75];\n};\n\nstruct ptp_sys_offset_precise {\n\tstruct ptp_clock_time device;\n\tstruct ptp_clock_time sys_realtime;\n\tstruct ptp_clock_time sys_monoraw;\n\tunsigned int rsv[4];\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n\tclockid_t clockid;\n};\n\nstruct ptp_vclock {\n\tstruct ptp_clock *pclock;\n\tstruct ptp_clock_info info;\n\tstruct ptp_clock *clock;\n\tstruct hlist_node vclock_hash_node;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct mutex lock;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_sud_config {\n\t__u64 mode;\n\t__u64 selector;\n\t__u64 offset;\n\t__u64 len;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct public_key {\n\tvoid *key;\n\tu32 keylen;\n\tenum OID algo;\n\tvoid *params;\n\tu32 paramlen;\n\tbool key_is_private;\n\tconst char *id_type;\n\tconst char *pkey_algo;\n\tlong unsigned int key_eflags;\n};\n\nstruct public_key_signature {\n\tstruct asymmetric_key_id *auth_ids[3];\n\tu8 *s;\n\tu8 *m;\n\tu32 s_size;\n\tu32 m_size;\n\tbool m_free;\n\tbool algo_takes_data;\n\tconst char *pkey_algo;\n\tconst char *hash_algo;\n\tconst char *encoding;\n};\n\nstruct pv_info {\n\tconst char *name;\n};\n\nstruct pvclock_vcpu_time_info {\n\tu32 version;\n\tu32 pad0;\n\tu64 tsc_timestamp;\n\tu64 system_time;\n\tu32 tsc_to_system_mul;\n\ts8 tsc_shift;\n\tu8 flags;\n\tu8 pad[2];\n};\n\nstruct pvclock_vsyscall_time_info {\n\tstruct pvclock_vcpu_time_info pvti;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pvclock_wall_clock {\n\tu32 version;\n\tu32 sec;\n\tu32 nsec;\n};\n\nstruct pwm_args {\n\tu64 period;\n\tenum pwm_polarity polarity;\n};\n\nstruct pwm_capture {\n\tunsigned int period;\n\tunsigned int duty_cycle;\n};\n\nstruct pwm_chip;\n\nstruct pwm_device {\n\tconst char *label;\n\tlong unsigned int flags;\n\tunsigned int hwpwm;\n\tstruct pwm_chip *chip;\n\tstruct pwm_args args;\n\tstruct pwm_state state;\n\tstruct pwm_state last;\n};\n\nstruct pwm_ops;\n\nstruct pwm_chip {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tconst struct pwm_ops *ops;\n\tstruct module *owner;\n\tunsigned int id;\n\tunsigned int npwm;\n\tstruct pwm_device * (*of_xlate)(struct pwm_chip *, const struct of_phandle_args *);\n\tbool atomic;\n\tstruct gpio_chip gpio;\n\tbool uses_pwmchip_alloc;\n\tbool operational;\n\tunion {\n\t\tstruct mutex nonatomic_lock;\n\t\tspinlock_t atomic_lock;\n\t};\n\tstruct pwm_device pwms[0];\n};\n\nstruct pwm_waveform;\n\nstruct pwm_ops {\n\tint (*request)(struct pwm_chip *, struct pwm_device *);\n\tvoid (*free)(struct pwm_chip *, struct pwm_device *);\n\tint (*capture)(struct pwm_chip *, struct pwm_device *, struct pwm_capture *, long unsigned int);\n\tsize_t sizeof_wfhw;\n\tint (*round_waveform_tohw)(struct pwm_chip *, struct pwm_device *, const struct pwm_waveform *, void *);\n\tint (*round_waveform_fromhw)(struct pwm_chip *, struct pwm_device *, const void *, struct pwm_waveform *);\n\tint (*read_waveform)(struct pwm_chip *, struct pwm_device *, void *);\n\tint (*write_waveform)(struct pwm_chip *, struct pwm_device *, const void *);\n\tint (*apply)(struct pwm_chip *, struct pwm_device *, const struct pwm_state *);\n\tint (*get_state)(struct pwm_chip *, struct pwm_device *, struct pwm_state *);\n};\n\nstruct pwm_waveform {\n\tu64 period_length_ns;\n\tu64 duty_length_ns;\n\tu64 duty_offset_ns;\n};\n\nstruct pxp42_create_arb_in {\n\tstruct pxp_cmd_header header;\n\tu32 protection_mode;\n\tu32 session_id;\n};\n\nstruct pxp42_create_arb_out {\n\tstruct pxp_cmd_header header;\n};\n\nstruct pxp42_inv_stream_key_in {\n\tstruct pxp_cmd_header header;\n\tu32 rsvd[3];\n};\n\nstruct pxp42_inv_stream_key_out {\n\tstruct pxp_cmd_header header;\n\tu32 rsvd;\n};\n\nstruct pxp43_start_huc_auth_in {\n\tstruct pxp_cmd_header header;\n\t__le64 huc_base_address;\n};\n\nstruct q_inval {\n\traw_spinlock_t q_lock;\n\tvoid *desc;\n\tint *desc_status;\n\tint free_head;\n\tint free_tail;\n\tint free_cnt;\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qdisc_dump_args {\n\tstruct qdisc_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct qdisc_rate_table {\n\tstruct tc_ratespec rate;\n\tu32 data[256];\n\tstruct qdisc_rate_table *next;\n\tint refcnt;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_watchdog {\n\tstruct hrtimer timer;\n\tstruct Qdisc *qdisc;\n};\n\nstruct qi_desc {\n\tu64 qw0;\n\tu64 qw1;\n\tu64 qw2;\n\tu64 qw3;\n};\n\nstruct qi_batch {\n\tstruct qi_desc descs[16];\n\tunsigned int index;\n};\n\nstruct qnode {\n\tstruct mcs_spinlock mcs;\n};\n\nstruct qt_disk_dqdbheader {\n\t__le32 dqdh_next_free;\n\t__le32 dqdh_prev_free;\n\t__le16 dqdh_entries;\n\t__le16 dqdh_pad1;\n\t__le32 dqdh_pad2;\n};\n\nstruct qtree_fmt_operations {\n\tvoid (*mem2disk_dqblk)(void *, struct dquot *);\n\tvoid (*disk2mem_dqblk)(struct dquot *, void *);\n\tint (*is_id)(void *, struct dquot *);\n};\n\nstruct qtree_mem_dqinfo {\n\tstruct super_block *dqi_sb;\n\tint dqi_type;\n\tunsigned int dqi_blocks;\n\tunsigned int dqi_free_blk;\n\tunsigned int dqi_free_entry;\n\tunsigned int dqi_blocksize_bits;\n\tunsigned int dqi_entry_size;\n\tunsigned int dqi_usable_bs;\n\tunsigned int dqi_qtree_depth;\n\tconst struct qtree_fmt_operations *dqi_ops;\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct queue_pages {\n\tstruct list_head *pagelist;\n\tlong unsigned int flags;\n\tnodemask_t *nmask;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct vm_area_struct *first;\n\tstruct folio *large;\n\tlong int nr_failed;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quirk_entry {\n\tu16 vid;\n\tu16 pid;\n\tu32 flags;\n};\n\nstruct quirk_entry___2 {\n\tu32 nominal_freq;\n\tu32 lowest_freq;\n};\n\nstruct quirk_printer_struct {\n\t__u16 vendorId;\n\t__u16 productId;\n\tunsigned int quirks;\n};\n\nstruct quirks_list_struct {\n\tstruct hid_device_id hid_bl_item;\n\tstruct list_head node;\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n};\n\nstruct quota_module_name {\n\tint qm_fmt_id;\n\tchar *qm_mod_name;\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct ra_msg {\n\tstruct icmp6hdr icmph;\n\t__be32 reachable_time;\n\t__be32 retrans_timer;\n};\n\nstruct radiotap_align_size {\n\tuint8_t align: 4;\n\tuint8_t size: 4;\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct rand_data {\n\tvoid *hash_state;\n\t__u64 prev_time;\n\t__u64 last_delta;\n\t__s64 last_delta2;\n\tunsigned int flags;\n\tunsigned int osr;\n\tunsigned char *mem;\n\tunsigned int memlocation;\n\tunsigned int memblocks;\n\tunsigned int memblocksize;\n\tunsigned int memaccessloops;\n\tunsigned int rct_count;\n\tunsigned int apt_cutoff;\n\tunsigned int apt_cutoff_permanent;\n\tunsigned int apt_observations;\n\tunsigned int apt_count;\n\tunsigned int apt_base;\n\tunsigned int health_failure;\n\tunsigned int apt_base_set: 1;\n};\n\nstruct range_node {\n\tstruct rb_node rn_rbnode;\n\tstruct rb_node rb_range_size;\n\tu32 rn_start;\n\tu32 rn_last;\n\tu32 __rn_subtree_last;\n};\n\nstruct range_trans {\n\tu32 source_type;\n\tu32 target_type;\n\tu32 target_class;\n};\n\nstruct rapl_model {\n\tstruct perf_msr *rapl_pkg_msrs;\n\tstruct perf_msr *rapl_core_msrs;\n\tlong unsigned int pkg_events;\n\tlong unsigned int core_events;\n\tunsigned int msr_power_unit;\n\tenum rapl_unit_quirk unit_quirk;\n};\n\nstruct rapl_pmu {\n\traw_spinlock_t lock;\n\tint n_active;\n\tint cpu;\n\tstruct list_head active_list;\n\tstruct pmu *pmu;\n\tktime_t timer_interval;\n\tstruct hrtimer hrtimer;\n};\n\nstruct rapl_pmus {\n\tstruct pmu pmu;\n\tunsigned int nr_rapl_pmu;\n\tunsigned int cntr_mask;\n\tstruct rapl_pmu *rapl_pmu[0];\n};\n\nstruct rate_control_ops;\n\nstruct rate_control_alg {\n\tstruct list_head list;\n\tconst struct rate_control_ops *ops;\n};\n\nstruct rate_control_ops {\n\tlong unsigned int capa;\n\tconst char *name;\n\tvoid * (*alloc)(struct ieee80211_hw *);\n\tvoid (*add_debugfs)(struct ieee80211_hw *, void *, struct dentry *);\n\tvoid (*free)(void *);\n\tvoid * (*alloc_sta)(void *, struct ieee80211_sta *, gfp_t);\n\tvoid (*rate_init)(void *, struct ieee80211_supported_band *, struct cfg80211_chan_def *, struct ieee80211_sta *, void *);\n\tvoid (*rate_update)(void *, struct ieee80211_supported_band *, struct cfg80211_chan_def *, struct ieee80211_sta *, void *, u32);\n\tvoid (*free_sta)(void *, struct ieee80211_sta *, void *);\n\tvoid (*tx_status_ext)(void *, struct ieee80211_supported_band *, void *, struct ieee80211_tx_status *);\n\tvoid (*tx_status)(void *, struct ieee80211_supported_band *, struct ieee80211_sta *, void *, struct sk_buff *);\n\tvoid (*get_rate)(void *, struct ieee80211_sta *, void *, struct ieee80211_tx_rate_control *);\n\tvoid (*add_sta_debugfs)(void *, void *, struct dentry *);\n\tu32 (*get_expected_throughput)(void *);\n};\n\nstruct rate_control_ref {\n\tconst struct rate_control_ops *ops;\n\tvoid *priv;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n};\n\nstruct raw6_frag_vec {\n\tstruct msghdr *msg;\n\tint hlen;\n\tchar c[4];\n};\n\nstruct raw6_sock {\n\tstruct inet_sock inet;\n\t__u32 checksum;\n\t__u32 offset;\n\tstruct icmp6_filter filter;\n\t__u32 ip6mr_table;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tu64 before;\n\tu64 after;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tatomic_t seq;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rb_time_struct {\n\tlocal64_t time;\n};\n\ntypedef struct rb_time_struct rb_time_t;\n\nstruct rb_wait_data {\n\tstruct rb_irq_work *irq_work;\n\tint seq;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct rc_map_table;\n\nstruct rc_map {\n\tstruct rc_map_table *scan;\n\tunsigned int size;\n\tunsigned int len;\n\tunsigned int alloc;\n\tenum rc_proto rc_proto;\n\tconst char *name;\n\tspinlock_t lock;\n};\n\nstruct ir_raw_event_ctrl;\n\nstruct rc_scancode_filter {\n\tu32 data;\n\tu32 mask;\n};\n\nstruct rc_dev {\n\tstruct device dev;\n\tbool managed_alloc;\n\tbool registered;\n\tbool idle;\n\tbool encode_wakeup;\n\tunsigned int minor;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst char *device_name;\n\tconst char *input_phys;\n\tstruct input_id input_id;\n\tconst char *driver_name;\n\tconst char *map_name;\n\tstruct rc_map rc_map;\n\tstruct mutex lock;\n\tstruct ir_raw_event_ctrl *raw;\n\tstruct input_dev *input_dev;\n\tenum rc_driver_type driver_type;\n\tu32 users;\n\tu64 allowed_protocols;\n\tu64 enabled_protocols;\n\tu64 allowed_wakeup_protocols;\n\tenum rc_proto wakeup_protocol;\n\tstruct rc_scancode_filter scancode_filter;\n\tstruct rc_scancode_filter scancode_wakeup_filter;\n\tu32 scancode_mask;\n\tvoid *priv;\n\tspinlock_t keylock;\n\tbool keypressed;\n\tu8 last_toggle;\n\tu32 last_keycode;\n\tenum rc_proto last_protocol;\n\tu64 last_scancode;\n\tlong unsigned int keyup_jiffies;\n\tstruct timer_list timer_keyup;\n\tstruct timer_list timer_repeat;\n\tu32 timeout;\n\tu32 min_timeout;\n\tu32 max_timeout;\n\tu32 rx_resolution;\n\tint (*change_protocol)(struct rc_dev *, u64 *);\n\tint (*open)(struct rc_dev *);\n\tvoid (*close)(struct rc_dev *);\n\tint (*s_tx_mask)(struct rc_dev *, u32);\n\tint (*s_tx_carrier)(struct rc_dev *, u32);\n\tint (*s_tx_duty_cycle)(struct rc_dev *, u32);\n\tint (*s_rx_carrier_range)(struct rc_dev *, u32, u32);\n\tint (*tx_ir)(struct rc_dev *, unsigned int *, unsigned int);\n\tvoid (*s_idle)(struct rc_dev *, bool);\n\tint (*s_wideband_receiver)(struct rc_dev *, int);\n\tint (*s_carrier_report)(struct rc_dev *, int);\n\tint (*s_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_wakeup_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_timeout)(struct rc_dev *, unsigned int);\n};\n\nstruct rc_map_table {\n\tu64 scancode;\n\tu32 keycode;\n};\n\nstruct rc_parameters {\n\tu16 initial_xmit_delay;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n};\n\nstruct rc_parameters_data {\n\tu8 bpp;\n\tu8 bpc;\n\tstruct rc_parameters params;\n};\n\nstruct rcec_ea {\n\tu8 nextbusn;\n\tu8 lastbusn;\n\tu32 bitmap;\n};\n\nstruct rchan_callbacks;\n\nstruct rchan_buf;\n\nstruct rchan {\n\tu32 version;\n\tsize_t subbuf_size;\n\tsize_t n_subbufs;\n\tsize_t alloc_size;\n\tconst struct rchan_callbacks *cb;\n\tstruct kref kref;\n\tvoid *private_data;\n\tstruct rchan_buf **buf;\n\tint is_global;\n\tstruct list_head list;\n\tstruct dentry *parent;\n\tint has_base_filename;\n\tchar base_filename[255];\n};\n\nstruct rchan_buf_stats {\n\tunsigned int full_count;\n\tunsigned int big_count;\n};\n\nstruct rchan_buf {\n\tvoid *start;\n\tvoid *data;\n\tsize_t offset;\n\tsize_t subbufs_produced;\n\tsize_t subbufs_consumed;\n\tstruct rchan *chan;\n\twait_queue_head_t read_wait;\n\tstruct irq_work wakeup_work;\n\tstruct dentry *dentry;\n\tstruct kref kref;\n\tstruct rchan_buf_stats stats;\n\tstruct page **page_array;\n\tunsigned int page_count;\n\tunsigned int finalized;\n\tsize_t *padding;\n\tsize_t bytes_consumed;\n\tsize_t early_bytes;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rchan_callbacks {\n\tint (*subbuf_start)(struct rchan_buf *, void *, void *);\n\tstruct dentry * (*create_buf_file)(const char *, struct dentry *, umode_t, struct rchan_buf *, int *);\n\tint (*remove_buf_file)(struct dentry *);\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t fqslock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion rcu_special {\n\tstruct {\n\t\tu8 blocked;\n\t\tu8 need_qs;\n\t\tu8 exp_hint;\n\t\tu8 need_mb;\n\t} b;\n\tu32 s;\n};\n\nstruct rcu_stall_chk_rdr {\n\tint nesting;\n\tunion rcu_special rs;\n\tbool on_blkd_list;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[5];\n\tstruct rcu_node *level[3];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rcu_tasks;\n\ntypedef void (*rcu_tasks_gp_func_t)(struct rcu_tasks *);\n\ntypedef void (*pregp_func_t)(struct list_head *);\n\ntypedef void (*pertask_func_t)(struct task_struct *, struct list_head *);\n\ntypedef void (*postscan_func_t)(struct list_head *);\n\ntypedef void (*holdouts_func_t)(struct list_head *, bool, bool *);\n\ntypedef void (*postgp_func_t)(struct rcu_tasks *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\nstruct rcu_tasks_percpu;\n\nstruct rcu_tasks {\n\tstruct rcuwait cbs_wait;\n\traw_spinlock_t cbs_gbl_lock;\n\tstruct mutex tasks_gp_mutex;\n\tint gp_state;\n\tint gp_sleep;\n\tint init_fract;\n\tlong unsigned int gp_jiffies;\n\tlong unsigned int gp_start;\n\tlong unsigned int tasks_gp_seq;\n\tlong unsigned int n_ipis;\n\tlong unsigned int n_ipis_fails;\n\tstruct task_struct *kthread_ptr;\n\tlong unsigned int lazy_jiffies;\n\trcu_tasks_gp_func_t gp_func;\n\tpregp_func_t pregp_func;\n\tpertask_func_t pertask_func;\n\tpostscan_func_t postscan_func;\n\tholdouts_func_t holdouts_func;\n\tpostgp_func_t postgp_func;\n\tcall_rcu_func_t call_func;\n\tunsigned int wait_state;\n\tstruct rcu_tasks_percpu *rtpcpu;\n\tstruct rcu_tasks_percpu **rtpcp_array;\n\tint percpu_enqueue_shift;\n\tint percpu_enqueue_lim;\n\tint percpu_dequeue_lim;\n\tlong unsigned int percpu_dequeue_gpseq;\n\tstruct mutex barrier_q_mutex;\n\tatomic_t barrier_q_count;\n\tstruct completion barrier_q_completion;\n\tlong unsigned int barrier_q_seq;\n\tlong unsigned int barrier_q_start;\n\tchar *name;\n\tchar *kname;\n};\n\nstruct rcu_tasks_percpu {\n\tstruct rcu_segcblist cblist;\n\traw_spinlock_t lock;\n\tlong unsigned int rtp_jiffies;\n\tlong unsigned int rtp_n_lock_retries;\n\tstruct timer_list lazy_timer;\n\tunsigned int urgent_gp;\n\tstruct work_struct rtp_work;\n\tstruct irq_work rtp_irq_work;\n\tstruct callback_head barrier_q_head;\n\tstruct list_head rtp_blkd_tasks;\n\tstruct list_head rtp_exit_list;\n\tint cpu;\n\tint index;\n\tstruct rcu_tasks *rtpp;\n};\n\nstruct rd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\tstruct in6_addr dest;\n\t__u8 opt[0];\n};\n\nstruct rdev_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct md_rdev *, char *);\n\tssize_t (*store)(struct md_rdev *, const char *, size_t);\n};\n\nstruct rdma_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head rpools;\n};\n\nstruct rdmacg_device {\n\tstruct list_head dev_node;\n\tstruct list_head rpools;\n\tchar *name;\n};\n\nstruct rdmacg_resource {\n\tint max;\n\tint usage;\n};\n\nstruct rdmacg_resource_pool {\n\tstruct rdmacg_device *device;\n\tstruct rdmacg_resource resources[2];\n\tstruct list_head cg_node;\n\tstruct list_head dev_node;\n\tu64 usage_sum;\n\tint num_max_cnt;\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct readdir_callback {\n\tstruct dir_context ctx;\n\tstruct old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct real_mode_header {\n\tu32 text_start;\n\tu32 ro_end;\n\tu32 trampoline_start;\n\tu32 trampoline_header;\n\tu32 trampoline_start64;\n\tu32 trampoline_pgd;\n\tu32 wakeup_start;\n\tu32 wakeup_header;\n\tu32 machine_real_restart_asm;\n\tu32 machine_real_restart_seg;\n};\n\nstruct virtnet_rq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t drops;\n\tu64_stats_t xdp_packets;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_redirects;\n\tu64_stats_t xdp_drops;\n\tu64_stats_t kicks;\n};\n\nstruct virtnet_interrupt_coalesce {\n\tu32 max_packets;\n\tu32 max_usecs;\n};\n\nstruct virtnet_rq_dma;\n\nstruct receive_queue {\n\tstruct virtqueue *vq;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tstruct virtnet_rq_stats stats;\n\tu16 calls;\n\tbool dim_enabled;\n\tstruct mutex dim_lock;\n\tstruct dim dim;\n\tu32 packets_in_napi;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct page *pages;\n\tstruct ewma_pkt_len mrg_avg_pkt_len;\n\tstruct page_frag alloc_frag;\n\tstruct scatterlist sg[19];\n\tunsigned int min_buf_len;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct virtnet_rq_dma *last_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xsk_rxq_info;\n\tstruct xdp_buff **xsk_buffs;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tlong unsigned int head_block;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\nstruct referring_call {\n\tuint32_t rc_sequenceid;\n\tuint32_t rc_slotid;\n};\n\nstruct referring_call_list {\n\tstruct nfs4_sessionid rcl_sessionid;\n\tuint32_t rcl_nrefcalls;\n\tstruct referring_call *rcl_refcalls;\n};\n\nstruct reg_beacon {\n\tstruct list_head list;\n\tstruct ieee80211_channel chan;\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct reg_regdb_apply_request {\n\tstruct list_head list;\n\tconst struct ieee80211_regdomain *regdom;\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nstruct reg_whitelist {\n\ti915_reg_t offset_ldw;\n\ti915_reg_t offset_udw;\n\tu8 min_graphics_ver;\n\tu8 max_graphics_ver;\n\tu8 size;\n};\n\nstruct regcache_flat_data {\n\tlong unsigned int *valid;\n\tunsigned int data[0];\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tint (*populate)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regcache_rbtree_node;\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong unsigned int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\nstruct register_test {\n\t__u32 reg;\n\t__u32 mask;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\ts8 reg_shift;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct hwspinlock;\n\nstruct regmap_bus;\n\nstruct regmap_access_table;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_spinlock;\n\t\t\tlong unsigned int raw_spinlock_flags;\n\t\t};\n\t};\n\tstruct lock_class_key *lock_key;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tunsigned int reg_base;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool async;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool max_register_is_set;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tbool defer_caching;\n\tbool force_write_field;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool can_sleep;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regmap_range;\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_noinc_write)(void *, unsigned int, const void *, size_t);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_noinc_read)(void *, unsigned int, void *, size_t);\n\ntypedef void (*regmap_hw_free_context)(void *);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)(void);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tbool free_on_exit;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_noinc_write reg_noinc_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_reg_noinc_read reg_noinc_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint reg_shift;\n\tunsigned int reg_base;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tbool can_sleep;\n\tbool fast_io;\n\tbool io_port;\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tunsigned int max_register;\n\tbool max_register_is_0;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool use_relaxed_mmio;\n\tbool can_multi_write;\n\tbool use_hwlock;\n\tbool use_raw_spinlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tstruct list_head link;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regulatory_request {\n\tstruct callback_head callback_head;\n\tint wiphy_idx;\n\tenum nl80211_reg_initiator initiator;\n\tenum nl80211_user_reg_hint_type user_reg_hint_type;\n\tchar alpha2[3];\n\tenum nl80211_dfs_regions dfs_region;\n\tbool intersect;\n\tbool processed;\n\tenum environment_cap country_ie_env;\n\tstruct list_head list;\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\nstruct sgt_iter {\n\tstruct scatterlist *sgp;\n\tunion {\n\t\tlong unsigned int pfn;\n\t\tdma_addr_t dma;\n\t};\n\tunsigned int curr;\n\tunsigned int max;\n};\n\nstruct remap_pfn {\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tpgprot_t prot;\n\tstruct sgt_iter sgt;\n\tresource_size_t iobase;\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tu64 alloc_time_ns;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tstruct device *dev;\n\tenum rpm_status rpm_status;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tlong unsigned int blkcg_pols[1];\n\tstruct blkcg_gq *root_blkg;\n\tstruct list_head blkg_list;\n\tstruct mutex blkcg_mutex;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_trace *blk_trace;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct request_wait {\n\tstruct dma_fence_cb cb;\n\tstruct task_struct *tsk;\n};\n\nstruct res_proc_context {\n\tstruct list_head *list;\n\tint (*preproc)(struct acpi_resource *, void *);\n\tvoid *preproc_data;\n\tint count;\n\tint error;\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct resource_map {\n\tu_long base;\n\tu_long num;\n\tstruct resource_map *next;\n};\n\nstruct resource_win {\n\tstruct resource res;\n\tresource_size_t offset;\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct restore_data_record {\n\tlong unsigned int jump_address;\n\tlong unsigned int jump_address_phys;\n\tlong unsigned int cr3;\n\tlong unsigned int magic;\n\tlong unsigned int e820_checksum;\n};\n\nstruct resume_swap_area {\n\t__kernel_loff_t offset;\n\t__u32 dev;\n} __attribute__((packed));\n\nstruct resv_map {\n\tstruct kref refs;\n\tspinlock_t lock;\n\tstruct list_head regions;\n\tlong int adds_in_progress;\n\tstruct list_head region_cache;\n\tlong int region_cache_count;\n\tstruct rw_semaphore rw_sema;\n\tstruct page_counter *reservation_counter;\n\tlong unsigned int pages_per_hpage;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct rethook {\n\tvoid *data;\n\tvoid (*handler)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\tstruct objpool_head pool;\n\tstruct callback_head rcu;\n};\n\nstruct return_consumer {\n\t__u64 cookie;\n\t__u64 id;\n};\n\nstruct return_instance {\n\tstruct hprobe hprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tint cons_cnt;\n\tstruct return_instance *next;\n\tstruct callback_head rcu;\n\tstruct return_consumer consumer;\n\tstruct return_consumer *extra_consumers;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct rfkill {\n\tspinlock_t lock;\n\tenum rfkill_type type;\n\tlong unsigned int state;\n\tlong unsigned int hard_block_reasons;\n\tu32 idx;\n\tbool registered;\n\tbool persistent;\n\tbool polling_paused;\n\tbool suspended;\n\tbool need_sync;\n\tconst struct rfkill_ops *ops;\n\tvoid *data;\n\tstruct led_trigger led_trigger;\n\tconst char *ledtrigname;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct delayed_work poll_work;\n\tstruct work_struct uevent_work;\n\tstruct work_struct sync_work;\n\tchar name[0];\n};\n\nstruct rfkill_data {\n\tstruct list_head list;\n\tstruct list_head events;\n\tstruct mutex mtx;\n\twait_queue_head_t read_wait;\n\tbool input_handler;\n\tu8 max_size;\n};\n\nstruct rfkill_event_ext {\n\t__u32 idx;\n\t__u8 type;\n\t__u8 op;\n\t__u8 soft;\n\t__u8 hard;\n\t__u8 hard_block_reasons;\n} __attribute__((packed));\n\nstruct rfkill_int_event {\n\tstruct list_head list;\n\tstruct rfkill_event_ext ev;\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct ring_buffer_cpu_meta {\n\tlong unsigned int first_buffer;\n\tlong unsigned int head_buffer;\n\tlong unsigned int commit_buffer;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tint buffers[0];\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tlong unsigned int cache_pages_removed;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tsize_t event_size;\n\tint missed_events;\n};\n\nstruct ring_buffer_meta {\n\tint magic;\n\tint struct_sizes;\n\tlong unsigned int total_size;\n\tlong unsigned int buffers_offset;\n};\n\nstruct trace_buffer_meta;\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tlong unsigned int cnt;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_lost;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\trb_time_t write_stamp;\n\trb_time_t before_stamp;\n\tu64 event_stamp[5];\n\tu64 read_stamp;\n\tlong unsigned int pages_removed;\n\tunsigned int mapped;\n\tunsigned int user_mapped;\n\tstruct mutex mapping_lock;\n\tlong unsigned int *subbuf_ids;\n\tstruct trace_buffer_meta *meta_page;\n\tstruct ring_buffer_cpu_meta *ring_meta;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct ring_desc {\n\t__le32 buf;\n\t__le32 flaglen;\n};\n\nstruct ring_desc_ex {\n\t__le32 bufhigh;\n\t__le32 buflow;\n\t__le32 txvlan;\n\t__le32 flaglen;\n};\n\nstruct ring_info {\n\tstruct sk_buff *skb;\n\tu32 len;\n};\n\nstruct ring_info___2 {\n\tu8 *data;\n\tdma_addr_t mapping;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_gpio_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_gpio_data gpio_data;\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tstruct crypto_alg base;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct rock_ridge {\n\t__u8 signature[2];\n\t__u8 len;\n\t__u8 version;\n\tunion {\n\t\tstruct SU_SP_s SP;\n\t\tstruct SU_CE_s CE;\n\t\tstruct SU_ER_s ER;\n\t\tstruct RR_RR_s RR;\n\t\tstruct RR_PX_s PX;\n\t\tstruct RR_PN_s PN;\n\t\tstruct RR_SL_s SL;\n\t\tstruct RR_NM_s NM;\n\t\tstruct RR_CL_s CL;\n\t\tstruct RR_PL_s PL;\n\t\tstruct RR_TF_s TF;\n\t\tstruct RR_ZF_s ZF;\n\t} u;\n};\n\nstruct rock_state {\n\tvoid *buffer;\n\tunsigned char *chr;\n\tint len;\n\tint cont_size;\n\tint cont_extent;\n\tint cont_offset;\n\tint cont_loops;\n\tstruct inode *inode;\n};\n\nstruct role_allow {\n\tu32 role;\n\tu32 new_role;\n\tstruct role_allow *next;\n};\n\nstruct role_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap dominates;\n\tstruct ebitmap types;\n};\n\nstruct role_trans_datum {\n\tu32 new_role;\n};\n\nstruct role_trans_key {\n\tu32 role;\n\tu32 type;\n\tu32 tclass;\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct root_entry {\n\tu64 lo;\n\tu64 hi;\n};\n\nstruct rpc_add_xprt_test {\n\tvoid (*add_xprt_test)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tvoid *data;\n};\n\nstruct rpc_auth_create_args {\n\trpc_authflavor_t pseudoflavor;\n\tconst char *target_name;\n};\n\nstruct rpc_authops {\n\tstruct module *owner;\n\trpc_authflavor_t au_flavor;\n\tchar *au_name;\n\tstruct rpc_auth * (*create)(const struct rpc_auth_create_args *, struct rpc_clnt *);\n\tvoid (*destroy)(struct rpc_auth *);\n\tint (*hash_cred)(struct auth_cred *, unsigned int);\n\tstruct rpc_cred * (*lookup_cred)(struct rpc_auth *, struct auth_cred *, int);\n\tstruct rpc_cred * (*crcreate)(struct rpc_auth *, struct auth_cred *, int, gfp_t);\n\trpc_authflavor_t (*info2flavor)(struct rpcsec_gss_info *);\n\tint (*flavor2info)(rpc_authflavor_t, struct rpcsec_gss_info *);\n\tint (*key_timeout)(struct rpc_auth *, struct rpc_cred *);\n\tint (*ping)(struct rpc_clnt *);\n};\n\nstruct rpc_bind_conn_calldata {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct rpc_buffer {\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct rpc_call_ops {\n\tvoid (*rpc_call_prepare)(struct rpc_task *, void *);\n\tvoid (*rpc_call_done)(struct rpc_task *, void *);\n\tvoid (*rpc_count_stats)(struct rpc_task *, void *);\n\tvoid (*rpc_release)(void *);\n};\n\nstruct rpc_xprt_switch;\n\nstruct rpc_cb_add_xprt_calldata {\n\tstruct rpc_xprt_switch *xps;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_pipe_dir_head {\n\tstruct list_head pdh_entries;\n\tstruct dentry *pdh_dentry;\n};\n\nstruct rpc_rtt {\n\tlong unsigned int timeo;\n\tlong unsigned int srtt[5];\n\tlong unsigned int sdrtt[5];\n\tint ntimeouts[5];\n};\n\nstruct rpc_timeout {\n\tlong unsigned int to_initval;\n\tlong unsigned int to_maxval;\n\tlong unsigned int to_increment;\n\tunsigned int to_retries;\n\tunsigned char to_exponential;\n};\n\nstruct rpc_xprt_iter_ops;\n\nstruct rpc_xprt_iter {\n\tstruct rpc_xprt_switch *xpi_xpswitch;\n\tstruct rpc_xprt *xpi_cursor;\n\tconst struct rpc_xprt_iter_ops *xpi_ops;\n};\n\nstruct rpc_iostats;\n\nstruct rpc_sysfs_client;\n\nstruct rpc_clnt {\n\trefcount_t cl_count;\n\tunsigned int cl_clid;\n\tstruct list_head cl_clients;\n\tstruct list_head cl_tasks;\n\tatomic_t cl_pid;\n\tspinlock_t cl_lock;\n\tstruct rpc_xprt *cl_xprt;\n\tconst struct rpc_procinfo *cl_procinfo;\n\tu32 cl_prog;\n\tu32 cl_vers;\n\tu32 cl_maxproc;\n\tstruct rpc_auth *cl_auth;\n\tstruct rpc_stat *cl_stats;\n\tstruct rpc_iostats *cl_metrics;\n\tunsigned int cl_softrtry: 1;\n\tunsigned int cl_softerr: 1;\n\tunsigned int cl_discrtry: 1;\n\tunsigned int cl_noretranstimeo: 1;\n\tunsigned int cl_autobind: 1;\n\tunsigned int cl_chatty: 1;\n\tunsigned int cl_shutdown: 1;\n\tunsigned int cl_netunreach_fatal: 1;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct rpc_rtt *cl_rtt;\n\tconst struct rpc_timeout *cl_timeout;\n\tatomic_t cl_swapper;\n\tint cl_nodelen;\n\tchar cl_nodename[65];\n\tstruct rpc_pipe_dir_head cl_pipedir_objects;\n\tstruct rpc_clnt *cl_parent;\n\tstruct rpc_rtt cl_rtt_default;\n\tstruct rpc_timeout cl_timeout_default;\n\tconst struct rpc_program *cl_program;\n\tconst char *cl_principal;\n\tstruct rpc_sysfs_client *cl_sysfs;\n\tunion {\n\t\tstruct rpc_xprt_iter cl_xpi;\n\t\tstruct work_struct cl_work;\n\t};\n\tconst struct cred *cl_cred;\n\tunsigned int cl_max_connect;\n\tstruct super_block *pipefs_sb;\n\tatomic_t cl_task_count;\n};\n\nstruct svc_xprt;\n\nstruct rpc_create_args {\n\tstruct net *net;\n\tint protocol;\n\tstruct sockaddr *address;\n\tsize_t addrsize;\n\tstruct sockaddr *saddress;\n\tconst struct rpc_timeout *timeout;\n\tconst char *servername;\n\tconst char *nodename;\n\tconst struct rpc_program *program;\n\tstruct rpc_stat *stats;\n\tu32 prognumber;\n\tu32 version;\n\trpc_authflavor_t authflavor;\n\tu32 nconnect;\n\tlong unsigned int flags;\n\tchar *client_name;\n\tstruct svc_xprt *bc_xprt;\n\tconst struct cred *cred;\n\tunsigned int max_connect;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct rpc_cred_cache {\n\tstruct hlist_head *hashtable;\n\tunsigned int hashbits;\n\tspinlock_t lock;\n};\n\nstruct rpc_credops {\n\tconst char *cr_name;\n\tint (*cr_init)(struct rpc_auth *, struct rpc_cred *);\n\tvoid (*crdestroy)(struct rpc_cred *);\n\tint (*crmatch)(struct auth_cred *, struct rpc_cred *, int);\n\tint (*crmarshal)(struct rpc_task *, struct xdr_stream *);\n\tint (*crrefresh)(struct rpc_task *);\n\tint (*crvalidate)(struct rpc_task *, struct xdr_stream *);\n\tint (*crwrap_req)(struct rpc_task *, struct xdr_stream *);\n\tint (*crunwrap_resp)(struct rpc_task *, struct xdr_stream *);\n\tint (*crkey_timeout)(struct rpc_cred *);\n\tchar * (*crstringify_acceptor)(struct rpc_cred *);\n\tbool (*crneed_reencode)(struct rpc_task *);\n};\n\nstruct rpc_filelist {\n\tconst char *name;\n\tconst struct file_operations *i_fop;\n\tumode_t mode;\n};\n\nstruct rpc_inode {\n\tstruct inode vfs_inode;\n\tvoid *private;\n\tstruct rpc_pipe *pipe;\n\twait_queue_head_t waitq;\n};\n\nstruct rpc_iostats {\n\tspinlock_t om_lock;\n\tlong unsigned int om_ops;\n\tlong unsigned int om_ntrans;\n\tlong unsigned int om_timeouts;\n\tlong long unsigned int om_bytes_sent;\n\tlong long unsigned int om_bytes_recv;\n\tktime_t om_queue;\n\tktime_t om_rtt;\n\tktime_t om_execute;\n\tlong unsigned int om_error_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rpc_pipe {\n\tstruct list_head pipe;\n\tstruct list_head in_upcall;\n\tstruct list_head in_downcall;\n\tint pipelen;\n\tint nreaders;\n\tint nwriters;\n\tint flags;\n\tstruct delayed_work queue_timeout;\n\tconst struct rpc_pipe_ops *ops;\n\tspinlock_t lock;\n\tstruct dentry *dentry;\n};\n\nstruct rpc_pipe_dir_object_ops {\n\tint (*create)(struct dentry *, struct rpc_pipe_dir_object *);\n\tvoid (*destroy)(struct dentry *, struct rpc_pipe_dir_object *);\n};\n\nstruct rpc_pipe_ops {\n\tssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char *, size_t);\n\tssize_t (*downcall)(struct file *, const char *, size_t);\n\tvoid (*release_pipe)(struct inode *);\n\tint (*open_pipe)(struct inode *);\n\tvoid (*destroy_msg)(struct rpc_pipe_msg *);\n};\n\ntypedef void (*kxdreproc_t)(struct rpc_rqst *, struct xdr_stream *, const void *);\n\ntypedef int (*kxdrdproc_t)(struct rpc_rqst *, struct xdr_stream *, void *);\n\nstruct rpc_procinfo {\n\tu32 p_proc;\n\tkxdreproc_t p_encode;\n\tkxdrdproc_t p_decode;\n\tunsigned int p_arglen;\n\tunsigned int p_replen;\n\tunsigned int p_timer;\n\tu32 p_statidx;\n\tconst char *p_name;\n};\n\nstruct rpc_program {\n\tconst char *name;\n\tu32 number;\n\tunsigned int nrvers;\n\tconst struct rpc_version **version;\n\tstruct rpc_stat *stats;\n\tconst char *pipe_dir_name;\n};\n\nstruct xdr_buf {\n\tstruct kvec head[1];\n\tstruct kvec tail[1];\n\tstruct bio_vec *bvec;\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int flags;\n\tunsigned int buflen;\n\tunsigned int len;\n};\n\nstruct rpc_rqst {\n\tstruct rpc_xprt *rq_xprt;\n\tstruct xdr_buf rq_snd_buf;\n\tstruct xdr_buf rq_rcv_buf;\n\tstruct rpc_task *rq_task;\n\tstruct rpc_cred *rq_cred;\n\t__be32 rq_xid;\n\tint rq_cong;\n\tu32 rq_seqnos[3];\n\tunsigned int rq_seqno_count;\n\tint rq_enc_pages_num;\n\tstruct page **rq_enc_pages;\n\tvoid (*rq_release_snd_buf)(struct rpc_rqst *);\n\tunion {\n\t\tstruct list_head rq_list;\n\t\tstruct rb_node rq_recv;\n\t};\n\tstruct list_head rq_xmit;\n\tstruct list_head rq_xmit2;\n\tvoid *rq_buffer;\n\tsize_t rq_callsize;\n\tvoid *rq_rbuffer;\n\tsize_t rq_rcvsize;\n\tsize_t rq_xmit_bytes_sent;\n\tsize_t rq_reply_bytes_recvd;\n\tstruct xdr_buf rq_private_buf;\n\tlong unsigned int rq_majortimeo;\n\tlong unsigned int rq_minortimeo;\n\tlong unsigned int rq_timeout;\n\tktime_t rq_rtt;\n\tunsigned int rq_retries;\n\tunsigned int rq_connect_cookie;\n\tatomic_t rq_pin;\n\tu32 rq_bytes_sent;\n\tktime_t rq_xtime;\n\tint rq_ntrans;\n\tstruct lwq_node rq_bc_list;\n\tlong unsigned int rq_bc_pa_state;\n\tstruct list_head rq_bc_pa_list;\n};\n\nstruct rpc_sysfs_client {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_clnt *clnt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt {\n\tstruct kobject kobject;\n\tstruct rpc_xprt *xprt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt_switch {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_xprt_switch *xprt_switch;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_task_setup {\n\tstruct rpc_task *task;\n\tstruct rpc_clnt *rpc_client;\n\tstruct rpc_xprt *rpc_xprt;\n\tstruct rpc_cred *rpc_op_cred;\n\tconst struct rpc_message *rpc_message;\n\tconst struct rpc_call_ops *callback_ops;\n\tvoid *callback_data;\n\tstruct workqueue_struct *workqueue;\n\tshort unsigned int flags;\n\tsigned char priority;\n};\n\nstruct rpc_version {\n\tu32 number;\n\tunsigned int nrprocs;\n\tconst struct rpc_procinfo *procs;\n\tunsigned int *counts;\n};\n\nstruct rpc_xprt_ops;\n\nstruct xprt_class;\n\nstruct rpc_xprt {\n\tstruct kref kref;\n\tconst struct rpc_xprt_ops *ops;\n\tunsigned int id;\n\tconst struct rpc_timeout *timeout;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tint prot;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tsize_t max_payload;\n\tstruct rpc_wait_queue binding;\n\tstruct rpc_wait_queue sending;\n\tstruct rpc_wait_queue pending;\n\tstruct rpc_wait_queue backlog;\n\tstruct list_head free;\n\tunsigned int max_reqs;\n\tunsigned int min_reqs;\n\tunsigned int num_reqs;\n\tlong unsigned int state;\n\tunsigned char resvport: 1;\n\tunsigned char reuseport: 1;\n\tatomic_t swapper;\n\tunsigned int bind_index;\n\tstruct list_head xprt_switch;\n\tlong unsigned int bind_timeout;\n\tlong unsigned int reestablish_timeout;\n\tstruct xprtsec_parms xprtsec;\n\tunsigned int connect_cookie;\n\tstruct work_struct task_cleanup;\n\tstruct timer_list timer;\n\tlong unsigned int last_used;\n\tlong unsigned int idle_timeout;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int max_reconnect_timeout;\n\tatomic_long_t queuelen;\n\tspinlock_t transport_lock;\n\tspinlock_t reserve_lock;\n\tspinlock_t queue_lock;\n\tu32 xid;\n\tstruct rpc_task *snd_task;\n\tstruct list_head xmit_queue;\n\tatomic_long_t xmit_queuelen;\n\tstruct svc_xprt *bc_xprt;\n\tstruct svc_serv *bc_serv;\n\tunsigned int bc_alloc_max;\n\tunsigned int bc_alloc_count;\n\tatomic_t bc_slot_count;\n\tspinlock_t bc_pa_lock;\n\tstruct list_head bc_pa_list;\n\tstruct rb_root recv_queue;\n\tstruct {\n\t\tlong unsigned int bind_count;\n\t\tlong unsigned int connect_count;\n\t\tlong unsigned int connect_start;\n\t\tlong unsigned int connect_time;\n\t\tlong unsigned int sends;\n\t\tlong unsigned int recvs;\n\t\tlong unsigned int bad_xids;\n\t\tlong unsigned int max_slots;\n\t\tlong long unsigned int req_u;\n\t\tlong long unsigned int bklog_u;\n\t\tlong long unsigned int sending_u;\n\t\tlong long unsigned int pending_u;\n\t} stat;\n\tstruct net *xprt_net;\n\tnetns_tracker ns_tracker;\n\tconst char *servername;\n\tconst char *address_strings[6];\n\tstruct callback_head rcu;\n\tconst struct xprt_class *xprt_class;\n\tstruct rpc_sysfs_xprt *xprt_sysfs;\n\tbool main;\n};\n\nstruct rpc_xprt_iter_ops {\n\tvoid (*xpi_rewind)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_xprt)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_next)(struct rpc_xprt_iter *);\n};\n\nstruct rpc_xprt_ops {\n\tvoid (*set_buffer_size)(struct rpc_xprt *, size_t, size_t);\n\tint (*reserve_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*alloc_slot)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*free_slot)(struct rpc_xprt *, struct rpc_rqst *);\n\tvoid (*rpcbind)(struct rpc_task *);\n\tvoid (*set_port)(struct rpc_xprt *, short unsigned int);\n\tvoid (*connect)(struct rpc_xprt *, struct rpc_task *);\n\tint (*get_srcaddr)(struct rpc_xprt *, char *, size_t);\n\tshort unsigned int (*get_srcport)(struct rpc_xprt *);\n\tint (*buf_alloc)(struct rpc_task *);\n\tvoid (*buf_free)(struct rpc_task *);\n\tint (*prepare_request)(struct rpc_rqst *, struct xdr_buf *);\n\tint (*send_request)(struct rpc_rqst *);\n\tvoid (*abort_send_request)(struct rpc_rqst *);\n\tvoid (*wait_for_reply_request)(struct rpc_task *);\n\tvoid (*timer)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_request)(struct rpc_task *);\n\tvoid (*close)(struct rpc_xprt *);\n\tvoid (*destroy)(struct rpc_xprt *);\n\tvoid (*set_connect_timeout)(struct rpc_xprt *, long unsigned int, long unsigned int);\n\tvoid (*print_stats)(struct rpc_xprt *, struct seq_file *);\n\tint (*enable_swap)(struct rpc_xprt *);\n\tvoid (*disable_swap)(struct rpc_xprt *);\n\tvoid (*inject_disconnect)(struct rpc_xprt *);\n\tint (*bc_setup)(struct rpc_xprt *, unsigned int);\n\tsize_t (*bc_maxpayload)(struct rpc_xprt *);\n\tunsigned int (*bc_num_slots)(struct rpc_xprt *);\n\tvoid (*bc_free_rqst)(struct rpc_rqst *);\n\tvoid (*bc_destroy)(struct rpc_xprt *, unsigned int);\n};\n\nstruct rpc_xprt_switch {\n\tspinlock_t xps_lock;\n\tstruct kref xps_kref;\n\tunsigned int xps_id;\n\tunsigned int xps_nxprts;\n\tunsigned int xps_nactive;\n\tunsigned int xps_nunique_destaddr_xprts;\n\tatomic_long_t xps_queuelen;\n\tstruct list_head xps_xprt_list;\n\tstruct net *xps_net;\n\tconst struct rpc_xprt_iter_ops *xps_iter_ops;\n\tstruct rpc_sysfs_xprt_switch *xps_sysfs;\n\tstruct callback_head xps_rcu;\n};\n\nstruct rpcb_info {\n\tu32 rpc_vers;\n\tconst struct rpc_procinfo *rpc_proc;\n};\n\nstruct rpcbind_args {\n\tstruct rpc_xprt *r_xprt;\n\tu32 r_prog;\n\tu32 r_vers;\n\tu32 r_prot;\n\tshort unsigned int r_port;\n\tconst char *r_netid;\n\tconst char *r_addr;\n\tconst char *r_owner;\n\tint r_status;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[2];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n};\n\nstruct sched_info {\n\tlong unsigned int pcount;\n\tlong long unsigned int run_delay;\n\tlong long unsigned int max_run_delay;\n\tlong long unsigned int min_run_delay;\n\tlong long unsigned int last_arrival;\n\tlong long unsigned int last_queued;\n\tstruct timespec64 max_run_delay_ts;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tcall_single_data_t nohz_csd;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tunsigned int numa_migrate_on;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 64;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tu64 prev_steal_time;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tlong: 64;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tktime_t hrtick_time;\n\tstruct sched_info rq_sched_info;\n\tlong long unsigned int rq_cpu_time;\n\tunsigned int yld_count;\n\tunsigned int sched_count;\n\tunsigned int sched_goidle;\n\tunsigned int ttwu_count;\n\tunsigned int ttwu_local;\n\tstruct cpuidle_state *idle_state;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tcpumask_var_t scratch_mask;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t cfsb_csd;\n\tstruct list_head cfsb_csd_list;\n\tatomic_t nr_iowait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n};\n\nstruct rs_msg {\n\tstruct icmp6hdr icmph;\n\t__u8 opt[0];\n};\n\nstruct rsa_key {\n\tconst u8 *n;\n\tconst u8 *e;\n\tconst u8 *d;\n\tconst u8 *p;\n\tconst u8 *q;\n\tconst u8 *dp;\n\tconst u8 *dq;\n\tconst u8 *qinv;\n\tsize_t n_sz;\n\tsize_t e_sz;\n\tsize_t d_sz;\n\tsize_t p_sz;\n\tsize_t q_sz;\n\tsize_t dp_sz;\n\tsize_t dq_sz;\n\tsize_t qinv_sz;\n};\n\nstruct rsa_mpi_key {\n\tMPI n;\n\tMPI e;\n\tMPI d;\n\tMPI p;\n\tMPI q;\n\tMPI dp;\n\tMPI dq;\n\tMPI qinv;\n};\n\nstruct rsassa_pkcs1_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct rsassa_pkcs1_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n\tconst struct hash_prefix *hash_prefix;\n};\n\nstruct rsc {\n\tstruct cache_head h;\n\tstruct xdr_netobj handle;\n\tstruct svc_cred cred;\n\tstruct gss_svc_seq_data seqdata;\n\tstruct gss_ctx *mechctx;\n\tstruct callback_head callback_head;\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rsi {\n\tstruct cache_head h;\n\tstruct xdr_netobj in_handle;\n\tstruct xdr_netobj in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tint major_status;\n\tint minor_status;\n\tstruct callback_head callback_head;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rsvd_count {\n\tint ndelayed;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct rt0_hdr {\n\tstruct ipv6_rt_hdr rt_hdr;\n\t__u32 reserved;\n\tstruct in6_addr addr[0];\n};\n\nstruct rt6_exception {\n\tstruct hlist_node hlist;\n\tstruct rt6_info *rt6i;\n\tlong unsigned int stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct rt6_mtu_change_arg {\n\tstruct net_device *dev;\n\tunsigned int mtu;\n\tstruct fib6_info *f6i;\n};\n\nstruct rt6_nh {\n\tstruct fib6_info *fib6_info;\n\tstruct fib6_config r_cfg;\n\tstruct list_head list;\n};\n\nstruct rt6_rtnl_dump_arg {\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct net *net;\n\tstruct fib_dump_filter filter;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\t__kernel_size_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct sigcontext_64 {\n\t__u64 r8;\n\t__u64 r9;\n\t__u64 r10;\n\t__u64 r11;\n\t__u64 r12;\n\t__u64 r13;\n\t__u64 r14;\n\t__u64 r15;\n\t__u64 di;\n\t__u64 si;\n\t__u64 bp;\n\t__u64 bx;\n\t__u64 dx;\n\t__u64 ax;\n\t__u64 cx;\n\t__u64 sp;\n\t__u64 ip;\n\t__u64 flags;\n\t__u16 cs;\n\t__u16 gs;\n\t__u16 fs;\n\t__u16 ss;\n\t__u64 err;\n\t__u64 trapno;\n\t__u64 oldmask;\n\t__u64 cr2;\n\t__u64 fpstate;\n\t__u64 reserved1[8];\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tstruct sigcontext_64 uc_mcontext;\n\tsigset_t uc_sigmask;\n};\n\nstruct rt_sigframe {\n\tchar *pretcode;\n\tstruct ucontext uc;\n\tstruct siginfo info;\n};\n\nstruct sigcontext_32 {\n\t__u16 gs;\n\t__u16 __gsh;\n\t__u16 fs;\n\t__u16 __fsh;\n\t__u16 es;\n\t__u16 __esh;\n\t__u16 ds;\n\t__u16 __dsh;\n\t__u32 di;\n\t__u32 si;\n\t__u32 bp;\n\t__u32 sp;\n\t__u32 bx;\n\t__u32 dx;\n\t__u32 cx;\n\t__u32 ax;\n\t__u32 trapno;\n\t__u32 err;\n\t__u32 ip;\n\t__u16 cs;\n\t__u16 __csh;\n\t__u32 flags;\n\t__u32 sp_at_signal;\n\t__u16 ss;\n\t__u16 __ssh;\n\t__u32 fpstate;\n\t__u32 oldmask;\n\t__u32 cr2;\n};\n\nstruct ucontext_ia32 {\n\tunsigned int uc_flags;\n\tunsigned int uc_link;\n\tcompat_stack_t uc_stack;\n\tstruct sigcontext_32 uc_mcontext;\n\tcompat_sigset_t uc_sigmask;\n};\n\nstruct rt_sigframe_ia32 {\n\tu32 pretcode;\n\tint sig;\n\tu32 pinfo;\n\tu32 puc;\n\tcompat_siginfo_t info;\n\tstruct ucontext_ia32 uc;\n\tchar retcode[8];\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rta_mfc_stats {\n\t__u64 mfcs_packets;\n\t__u64 mfcs_bytes;\n\t__u64 mfcs_wrong_if;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtl8139_stats {\n\tu64 packets;\n\tu64 bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct rtl_extra_stats {\n\tlong unsigned int early_rx;\n\tlong unsigned int tx_buf_mapped;\n\tlong unsigned int tx_timeouts;\n\tlong unsigned int rx_lost_in_ring;\n};\n\nstruct rtl8139_private {\n\tvoid *mmio_addr;\n\tint drv_flags;\n\tstruct pci_dev *pci_dev;\n\tu32 msg_enable;\n\tstruct napi_struct napi;\n\tstruct net_device *dev;\n\tunsigned char *rx_ring;\n\tunsigned int cur_rx;\n\tstruct rtl8139_stats rx_stats;\n\tdma_addr_t rx_ring_dma;\n\tunsigned int tx_flag;\n\tlong unsigned int cur_tx;\n\tlong unsigned int dirty_tx;\n\tstruct rtl8139_stats tx_stats;\n\tunsigned char *tx_buf[4];\n\tunsigned char *tx_bufs;\n\tdma_addr_t tx_bufs_dma;\n\tsigned char phys[4];\n\tchar twistie;\n\tchar twist_row;\n\tchar twist_col;\n\tunsigned int watchdog_fired: 1;\n\tunsigned int default_port: 4;\n\tunsigned int have_thread: 1;\n\tspinlock_t lock;\n\tspinlock_t rx_lock;\n\tchip_t chipset;\n\tu32 rx_config;\n\tstruct rtl_extra_stats xstats;\n\tstruct delayed_work thread;\n\tstruct mii_if_info mii;\n\tunsigned int regs_len;\n\tlong unsigned int fifo_copy_timeout;\n};\n\nstruct rtl8169_counters {\n\t__le64 tx_packets;\n\t__le64 rx_packets;\n\t__le64 tx_errors;\n\t__le32 rx_errors;\n\t__le16 rx_missed;\n\t__le16 align_errors;\n\t__le32 tx_one_collision;\n\t__le32 tx_multi_collision;\n\t__le64 rx_unicast;\n\t__le64 rx_broadcast;\n\t__le32 rx_multicast;\n\t__le16 tx_aborted;\n\t__le16 tx_underrun;\n\t__le64 tx_octets;\n\t__le64 rx_octets;\n\t__le64 rx_multicast64;\n\t__le64 tx_unicast64;\n\t__le64 tx_broadcast64;\n\t__le64 tx_multicast64;\n\t__le32 tx_pause_on;\n\t__le32 tx_pause_off;\n\t__le32 tx_pause_all;\n\t__le32 tx_deferred;\n\t__le32 tx_late_collision;\n\t__le32 tx_all_collision;\n\t__le32 tx_aborted32;\n\t__le32 align_errors32;\n\t__le32 rx_frame_too_long;\n\t__le32 rx_runt;\n\t__le32 rx_pause_on;\n\t__le32 rx_pause_off;\n\t__le32 rx_pause_all;\n\t__le32 rx_unknown_opcode;\n\t__le32 rx_mac_error;\n\t__le32 tx_underrun32;\n\t__le32 rx_mac_missed;\n\t__le32 rx_tcam_dropped;\n\t__le32 tdu;\n\t__le32 rdu;\n};\n\nstruct rtl8169_tc_offsets {\n\tbool inited;\n\t__le64 tx_errors;\n\t__le32 tx_multi_collision;\n\t__le16 tx_aborted;\n\t__le16 rx_missed;\n};\n\nstruct r8169_led_classdev;\n\nstruct rtl_fw;\n\nstruct rtl8169_private {\n\tvoid *mmio_addr;\n\tstruct pci_dev *pci_dev;\n\tstruct net_device *dev;\n\tstruct phy_device *phydev;\n\tstruct napi_struct napi;\n\tenum mac_version mac_version;\n\tenum rtl_dash_type dash_type;\n\tu32 cur_rx;\n\tu32 cur_tx;\n\tu32 dirty_tx;\n\tstruct TxDesc *TxDescArray;\n\tstruct RxDesc *RxDescArray;\n\tdma_addr_t TxPhyAddr;\n\tdma_addr_t RxPhyAddr;\n\tstruct page *Rx_databuff[256];\n\tstruct ring_info tx_skb[256];\n\tu16 cp_cmd;\n\tu16 tx_lpi_timer;\n\tu32 irq_mask;\n\tint irq;\n\tstruct clk *clk;\n\tstruct {\n\t\tlong unsigned int flags[1];\n\t\tstruct work_struct work;\n\t} wk;\n\traw_spinlock_t mac_ocp_lock;\n\tstruct mutex led_lock;\n\tunsigned int supports_gmii: 1;\n\tunsigned int aspm_manageable: 1;\n\tunsigned int dash_enabled: 1;\n\tbool sfp_mode: 1;\n\tdma_addr_t counters_phys_addr;\n\tstruct rtl8169_counters *counters;\n\tstruct rtl8169_tc_offsets tc_offset;\n\tu32 saved_wolopts;\n\tconst char *fw_name;\n\tstruct rtl_fw *rtl_fw;\n\tstruct r8169_led_classdev *leds;\n\tu32 ocp_base;\n};\n\nstruct rtl821x_priv {\n\tbool enable_aldps;\n\tbool disable_clk_out;\n\tstruct clk *clk;\n\tu16 iner;\n};\n\nstruct rtl_chip_info {\n\tu32 mask;\n\tu32 val;\n\tenum mac_version mac_version;\n\tconst char *name;\n\tconst char *fw_name;\n};\n\nstruct rtl_coalesce_info {\n\tu32 speed;\n\tu32 scale_nsecs[4];\n};\n\nstruct rtl_cond {\n\tbool (*check)(struct rtl8169_private *);\n\tconst char *msg;\n};\n\ntypedef void (*rtl_fw_write_t)(struct rtl8169_private *, int, int);\n\ntypedef int (*rtl_fw_read_t)(struct rtl8169_private *, int);\n\nstruct rtl_fw_phy_action {\n\t__le32 *code;\n\tsize_t size;\n};\n\nstruct rtl_fw {\n\trtl_fw_write_t phy_write;\n\trtl_fw_read_t phy_read;\n\trtl_fw_write_t mac_mcu_write;\n\trtl_fw_read_t mac_mcu_read;\n\tconst struct firmware *fw;\n\tconst char *fw_name;\n\tstruct device *dev;\n\tchar version[32];\n\tstruct rtl_fw_phy_action phy_action;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtree_node {\n\tstruct list_head list;\n\tlong unsigned int *data;\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rwrt_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u32 last_lba;\n\t__u32 block_size;\n\t__u16 blocking;\n\t__u8 page_present: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx {\n\tstruct rx *next;\n\tstruct rx *prev;\n\tstruct sk_buff *skb;\n\tdma_addr_t dma_addr;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct rx_ring_info {\n\tstruct sk_buff *skb;\n\tdma_addr_t data_addr;\n\t__u32 data_size;\n\tdma_addr_t frag_addr[2];\n};\n\nstruct s1g_short_beacon_data {\n\tstruct callback_head callback_head;\n\tu8 *short_head;\n\tu8 *short_tail;\n\tint short_head_len;\n\tint short_tail_len;\n};\n\nstruct s1g_tim_aid {\n\tu16 aid;\n\tu8 target_blk;\n\tu8 target_subblk;\n\tu8 target_subblk_bit;\n};\n\nstruct s1g_tim_enc_block {\n\tu8 enc_mode;\n\tbool inverse;\n\tconst u8 *ptr;\n\tu8 len;\n\tu8 olb_blk_offset;\n};\n\nstruct s3_save {\n\tu32 command;\n\tu32 dev_nt;\n\tu64 dcbaa_ptr;\n\tu32 config_reg;\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct value_name_pair;\n\nstruct sa_name_list {\n\tint opcode;\n\tconst struct value_name_pair *arr;\n\tint arr_sz;\n};\n\nstruct sadb_alg {\n\t__u8 sadb_alg_id;\n\t__u8 sadb_alg_ivlen;\n\t__u16 sadb_alg_minbits;\n\t__u16 sadb_alg_maxbits;\n\t__u16 sadb_alg_reserved;\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar saved_cmdlines[0];\n};\n\nstruct saved_msr;\n\nstruct saved_msrs {\n\tunsigned int num;\n\tstruct saved_msr *array;\n};\n\nstruct saved_context {\n\tstruct pt_regs regs;\n\tu16 ds;\n\tu16 es;\n\tu16 fs;\n\tu16 gs;\n\tlong unsigned int kernelmode_gs_base;\n\tlong unsigned int usermode_gs_base;\n\tlong unsigned int fs_base;\n\tlong unsigned int cr0;\n\tlong unsigned int cr2;\n\tlong unsigned int cr3;\n\tlong unsigned int cr4;\n\tu64 misc_enable;\n\tstruct saved_msrs saved_msrs;\n\tlong unsigned int efer;\n\tu16 gdt_pad;\n\tstruct desc_ptr gdt_desc;\n\tu16 idt_pad;\n\tstruct desc_ptr idt;\n\tu16 ldt;\n\tu16 tss;\n\tlong unsigned int tr;\n\tlong unsigned int safety;\n\tlong unsigned int return_address;\n\tbool misc_enable_saved;\n} __attribute__((packed));\n\nstruct saved_msr {\n\tbool valid;\n\tstruct msr_info info;\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct scan_area {\n\tu64 addr;\n\tu64 size;\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_cache {\n\tstruct list_head *priolist;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n};\n\nstruct sched_clock_data {\n\tu64 tick_raw;\n\tu64 tick_gtod;\n\tu64 clock;\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tunsigned int lb_count[3];\n\tunsigned int lb_failed[3];\n\tunsigned int lb_balanced[3];\n\tunsigned int lb_imbalance_load[3];\n\tunsigned int lb_imbalance_util[3];\n\tunsigned int lb_imbalance_task[3];\n\tunsigned int lb_imbalance_misfit[3];\n\tunsigned int lb_gained[3];\n\tunsigned int lb_hot_gained[3];\n\tunsigned int lb_nobusyg[3];\n\tunsigned int lb_nobusyq[3];\n\tunsigned int alb_count;\n\tunsigned int alb_failed;\n\tunsigned int alb_pushed;\n\tunsigned int sbe_count;\n\tunsigned int sbe_balanced;\n\tunsigned int sbe_pushed;\n\tunsigned int sbf_count;\n\tunsigned int sbf_balanced;\n\tunsigned int sbf_pushed;\n\tunsigned int ttwu_wake_remote;\n\tunsigned int ttwu_move_affine;\n\tunsigned int ttwu_move_balance;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n};\n\nstruct sched_statistics {\n\tu64 wait_start;\n\tu64 wait_max;\n\tu64 wait_count;\n\tu64 wait_sum;\n\tu64 iowait_count;\n\tu64 iowait_sum;\n\tu64 sleep_start;\n\tu64 sleep_max;\n\ts64 sum_sleep_runtime;\n\tu64 block_start;\n\tu64 block_max;\n\ts64 sum_block_runtime;\n\ts64 exec_max;\n\tu64 slice_max;\n\tu64 nr_migrations_cold;\n\tu64 nr_failed_migrations_affine;\n\tu64 nr_failed_migrations_running;\n\tu64 nr_failed_migrations_hot;\n\tu64 nr_forced_migrations;\n\tu64 nr_wakeups;\n\tu64 nr_wakeups_sync;\n\tu64 nr_wakeups_migrate;\n\tu64 nr_wakeups_local;\n\tu64 nr_wakeups_remote;\n\tu64 nr_wakeups_affine;\n\tu64 nr_wakeups_affine_attempts;\n\tu64 nr_wakeups_passive;\n\tu64 nr_wakeups_idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sched_entity_stats {\n\tstruct sched_entity se;\n\tstruct sched_statistics stats;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct scheduling_policy {\n\tu32 max_words;\n\tu32 num_words;\n\tu32 count;\n\tstruct guc_update_scheduling_policy h2g;\n};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n\tu32 secid;\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scomp_alg {\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_acomp_streams streams;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tunion {\n\t\tvoid *src;\n\t\tlong unsigned int saddr;\n\t};\n};\n\nstruct scsi_cd {\n\tunsigned int capacity;\n\tstruct scsi_device *device;\n\tunsigned int vendor;\n\tlong unsigned int ms_offset;\n\tunsigned int writeable: 1;\n\tunsigned int use: 1;\n\tunsigned int xa_flag: 1;\n\tunsigned int readcd_known: 1;\n\tunsigned int readcd_cdda: 1;\n\tunsigned int media_present: 1;\n\tint tur_mismatch;\n\tbool tur_changed: 1;\n\tbool get_event_changed: 1;\n\tbool ignore_get_event: 1;\n\tstruct cdrom_device_info cdi;\n\tstruct mutex lock;\n\tstruct gendisk *disk;\n};\n\ntypedef struct scsi_cd Scsi_CD;\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*compat_ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 ic_enable: 1;\n\tu8 cs_enble: 1;\n\tu8 st_enble: 1;\n\tu8 reserved1: 3;\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved2[3];\n\tu8 lbm_descriptor_type: 4;\n\tu8 rlbsr: 2;\n\tu8 reserved3: 1;\n\tu8 acdlu: 1;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_proc_entry {\n\tstruct list_head entry;\n\tconst struct scsi_host_template *sht;\n\tstruct proc_dir_entry *proc_dir;\n\tunsigned int present;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 reserved1: 7;\n\tu8 perm: 1;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 rel_lifetime: 6;\n\tu8 reserved3: 2;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct sctp_paramhdr {\n\t__be16 type;\n\t__be16 length;\n};\n\nstruct sctp_adaptation_ind_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 adaptation_ind;\n};\n\nstruct sctp_addip_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 crr_id;\n};\n\nstruct sctp_addiphdr {\n\t__be32 serial;\n};\n\nstruct sockaddr_inet {\n\tshort unsigned int sa_family;\n\tchar sa_data[26];\n};\n\nunion sctp_addr {\n\tstruct sockaddr_inet sa;\n\tstruct sockaddr_in v4;\n\tstruct sockaddr_in6 v6;\n};\n\nstruct sctp_ipv4addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in_addr addr;\n};\n\nstruct sctp_ipv6addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in6_addr addr;\n};\n\nunion sctp_addr_param {\n\tstruct sctp_paramhdr p;\n\tstruct sctp_ipv4addr_param v4;\n\tstruct sctp_ipv6addr_param v6;\n};\n\nstruct sctp_transport;\n\nstruct sctp_sock;\n\nstruct sctp_af {\n\tint (*sctp_xmit)(struct sk_buff *, struct sctp_transport *);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*get_dst)(struct sctp_transport *, union sctp_addr *, struct flowi *, struct sock *);\n\tvoid (*get_saddr)(struct sctp_sock *, struct sctp_transport *, struct flowi *);\n\tvoid (*copy_addrlist)(struct list_head *, struct net_device *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *);\n\tvoid (*addr_copy)(union sctp_addr *, union sctp_addr *);\n\tvoid (*from_skb)(union sctp_addr *, struct sk_buff *, int);\n\tvoid (*from_sk)(union sctp_addr *, struct sock *);\n\tbool (*from_addr_param)(union sctp_addr *, union sctp_addr_param *, __be16, int);\n\tint (*to_addr_param)(const union sctp_addr *, union sctp_addr_param *);\n\tint (*addr_valid)(union sctp_addr *, struct sctp_sock *, const struct sk_buff *);\n\tenum sctp_scope (*scope)(union sctp_addr *);\n\tvoid (*inaddr_any)(union sctp_addr *, __be16);\n\tint (*is_any)(const union sctp_addr *);\n\tint (*available)(union sctp_addr *, struct sctp_sock *);\n\tint (*skb_iif)(const struct sk_buff *);\n\tint (*skb_sdif)(const struct sk_buff *);\n\tint (*is_ce)(const struct sk_buff *);\n\tvoid (*seq_dump_addr)(struct seq_file *, union sctp_addr *);\n\tvoid (*ecn_capable)(struct sock *);\n\t__u16 net_header_len;\n\tint sockaddr_len;\n\tint (*ip_options_len)(struct sock *);\n\tsa_family_t sa_family;\n\tstruct list_head list;\n};\n\nstruct sctp_chunk;\n\nstruct sctp_inq {\n\tstruct list_head in_chunk_list;\n\tstruct sctp_chunk *in_progress;\n\tstruct work_struct immediate;\n};\n\nstruct sctp_bind_addr {\n\t__u16 port;\n\tstruct list_head address_list;\n};\n\nstruct sctp_ep_common {\n\tenum sctp_endpoint_type type;\n\trefcount_t refcnt;\n\tbool dead;\n\tstruct sock *sk;\n\tstruct net *net;\n\tstruct sctp_inq inqueue;\n\tstruct sctp_bind_addr bind_addr;\n};\n\nstruct sctp_cookie {\n\t__u32 my_vtag;\n\t__u32 peer_vtag;\n\t__u32 my_ttag;\n\t__u32 peer_ttag;\n\tktime_t expiration;\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u32 initial_tsn;\n\tunion sctp_addr peer_addr;\n\t__u16 my_port;\n\t__u8 prsctp_capable;\n\t__u8 padding;\n\t__u32 adaptation_ind;\n\t__u8 auth_random[36];\n\t__u8 auth_hmacs[10];\n\t__u8 auth_chunks[20];\n\t__u32 raw_addr_list_len;\n};\n\nstruct sctp_tsnmap {\n\tlong unsigned int *tsn_map;\n\t__u32 base_tsn;\n\t__u32 cumulative_tsn_ack_point;\n\t__u32 max_tsn_seen;\n\t__u16 len;\n\t__u16 pending_data;\n\t__u16 num_dup_tsns;\n\t__be32 dup_tsns[16];\n};\n\nstruct sctp_inithdr_host {\n\t__u32 init_tag;\n\t__u32 a_rwnd;\n\t__u16 num_outbound_streams;\n\t__u16 num_inbound_streams;\n\t__u32 initial_tsn;\n};\n\nstruct sctp_stream_out_ext;\n\nstruct sctp_stream_out {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\tstruct sctp_stream_out_ext *ext;\n\t__u8 state;\n};\n\nstruct sctp_stream_in {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\t__u32 fsn;\n\t__u32 fsn_uo;\n\tchar pd_mode;\n\tchar pd_mode_uo;\n};\n\nstruct sctp_stream_interleave;\n\nstruct sctp_stream {\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_out type[0];\n\t} out;\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_in type[0];\n\t} in;\n\t__u16 outcnt;\n\t__u16 incnt;\n\tstruct sctp_stream_out *out_curr;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t\tstruct sctp_stream_out_ext *rr_next;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t};\n\t};\n\tstruct sctp_stream_interleave *si;\n};\n\nstruct sctp_sched_ops;\n\nstruct sctp_association;\n\nstruct sctp_outq {\n\tstruct sctp_association *asoc;\n\tstruct list_head out_chunk_list;\n\tconst struct sctp_sched_ops *sched;\n\tunsigned int out_qlen;\n\tunsigned int error;\n\tstruct list_head control_chunk_list;\n\tstruct list_head sacked;\n\tstruct list_head retransmit;\n\tstruct list_head abandoned;\n\t__u32 outstanding_bytes;\n\tchar fast_rtx;\n\tchar cork;\n};\n\nstruct sctp_ulpq {\n\tchar pd_mode;\n\tstruct sctp_association *asoc;\n\tstruct sk_buff_head reasm;\n\tstruct sk_buff_head reasm_uo;\n\tstruct sk_buff_head lobby;\n};\n\nstruct sctp_priv_assoc_stats {\n\tstruct __kernel_sockaddr_storage obs_rto_ipaddr;\n\t__u64 max_obs_rto;\n\t__u64 isacks;\n\t__u64 osacks;\n\t__u64 opackets;\n\t__u64 ipackets;\n\t__u64 rtxchunks;\n\t__u64 outofseqtsns;\n\t__u64 idupchunks;\n\t__u64 gapcnt;\n\t__u64 ouodchunks;\n\t__u64 iuodchunks;\n\t__u64 oodchunks;\n\t__u64 iodchunks;\n\t__u64 octrlchunks;\n\t__u64 ictrlchunks;\n};\n\nstruct sctp_endpoint;\n\nstruct sctp_random_param;\n\nstruct sctp_chunks_param;\n\nstruct sctp_hmac_algo_param;\n\nstruct sctp_auth_bytes;\n\nstruct sctp_shared_key;\n\nstruct sctp_association {\n\tstruct sctp_ep_common base;\n\tstruct list_head asocs;\n\tsctp_assoc_t assoc_id;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_cookie c;\n\tstruct {\n\t\tstruct list_head transport_addr_list;\n\t\t__u32 rwnd;\n\t\t__u16 transport_count;\n\t\t__u16 port;\n\t\tstruct sctp_transport *primary_path;\n\t\tunion sctp_addr primary_addr;\n\t\tstruct sctp_transport *active_path;\n\t\tstruct sctp_transport *retran_path;\n\t\tstruct sctp_transport *last_sent_to;\n\t\tstruct sctp_transport *last_data_from;\n\t\tstruct sctp_tsnmap tsn_map;\n\t\t__be16 addip_disabled_mask;\n\t\t__u16 ecn_capable: 1;\n\t\t__u16 ipv4_address: 1;\n\t\t__u16 ipv6_address: 1;\n\t\t__u16 asconf_capable: 1;\n\t\t__u16 prsctp_capable: 1;\n\t\t__u16 reconf_capable: 1;\n\t\t__u16 intl_capable: 1;\n\t\t__u16 auth_capable: 1;\n\t\t__u16 sack_needed: 1;\n\t\t__u16 sack_generation: 1;\n\t\t__u16 zero_window_announced: 1;\n\t\t__u32 sack_cnt;\n\t\t__u32 adaptation_ind;\n\t\tstruct sctp_inithdr_host i;\n\t\tvoid *cookie;\n\t\tint cookie_len;\n\t\t__u32 addip_serial;\n\t\tstruct sctp_random_param *peer_random;\n\t\tstruct sctp_chunks_param *peer_chunks;\n\t\tstruct sctp_hmac_algo_param *peer_hmacs;\n\t} peer;\n\tenum sctp_state state;\n\tint overall_error_count;\n\tktime_t cookie_life;\n\tlong unsigned int rto_initial;\n\tlong unsigned int rto_max;\n\tlong unsigned int rto_min;\n\tint max_burst;\n\tint max_retrans;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u16 max_init_attempts;\n\t__u16 init_retries;\n\tlong unsigned int max_init_timeo;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u8 pmtu_pending;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\t__u32 sackfreq;\n\tlong unsigned int sackdelay;\n\tlong unsigned int timeouts[12];\n\tstruct timer_list timers[12];\n\tstruct sctp_transport *shutdown_last_sent_to;\n\tstruct sctp_transport *init_last_sent_to;\n\tint shutdown_retries;\n\t__u32 next_tsn;\n\t__u32 ctsn_ack_point;\n\t__u32 adv_peer_ack_point;\n\t__u32 highest_sacked;\n\t__u32 fast_recovery_exit;\n\t__u8 fast_recovery;\n\t__u16 unack_data;\n\t__u32 rtx_data_chunks;\n\t__u32 rwnd;\n\t__u32 a_rwnd;\n\t__u32 rwnd_over;\n\t__u32 rwnd_press;\n\tint sndbuf_used;\n\tatomic_t rmem_alloc;\n\twait_queue_head_t wait;\n\t__u32 frag_point;\n\t__u32 user_frag;\n\tint init_err_counter;\n\tint init_cycle;\n\t__u16 default_stream;\n\t__u16 default_flags;\n\t__u32 default_ppid;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tstruct sctp_stream stream;\n\tstruct sctp_outq outqueue;\n\tstruct sctp_ulpq ulpq;\n\t__u32 last_ecne_tsn;\n\t__u32 last_cwr_tsn;\n\tint numduptsns;\n\tstruct sctp_chunk *addip_last_asconf;\n\tstruct list_head asconf_ack_list;\n\tstruct list_head addip_chunk_list;\n\t__u32 addip_serial;\n\tint src_out_of_asoc_ok;\n\tunion sctp_addr *asconf_addr_del_pending;\n\tstruct sctp_transport *new_transport;\n\tstruct list_head endpoint_shared_keys;\n\tstruct sctp_auth_bytes *asoc_shared_key;\n\tstruct sctp_shared_key *shkey;\n\t__u16 default_hmac_id;\n\t__u16 active_key_id;\n\t__u8 need_ecne: 1;\n\t__u8 temp: 1;\n\t__u8 pf_expose: 2;\n\t__u8 force_delay: 1;\n\t__u8 strreset_enable;\n\t__u8 strreset_outstanding;\n\t__u32 strreset_outseq;\n\t__u32 strreset_inseq;\n\t__u32 strreset_result[2];\n\tstruct sctp_chunk *strreset_chunk;\n\tstruct sctp_priv_assoc_stats stats;\n\tint sent_cnt_removable;\n\t__u16 subscribe;\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tu32 secid;\n\tu32 peer_secid;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_assocparams {\n\tsctp_assoc_t sasoc_assoc_id;\n\t__u16 sasoc_asocmaxrxt;\n\t__u16 sasoc_number_peer_destinations;\n\t__u32 sasoc_peer_rwnd;\n\t__u32 sasoc_local_rwnd;\n\t__u32 sasoc_cookie_life;\n};\n\nstruct sctp_auth_bytes {\n\trefcount_t refcnt;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct sctp_authhdr {\n\t__be16 shkey_id;\n\t__be16 hmac_id;\n};\n\nstruct sctp_bind_bucket {\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct hlist_node node;\n\tstruct hlist_head owner;\n\tstruct net *net;\n};\n\nstruct sctp_cookie_preserve_param;\n\nstruct sctp_hostname_param;\n\nstruct sctp_cookie_param;\n\nstruct sctp_supported_addrs_param;\n\nstruct sctp_supported_ext_param;\n\nunion sctp_params {\n\tvoid *v;\n\tstruct sctp_paramhdr *p;\n\tstruct sctp_cookie_preserve_param *life;\n\tstruct sctp_hostname_param *dns;\n\tstruct sctp_cookie_param *cookie;\n\tstruct sctp_supported_addrs_param *sat;\n\tstruct sctp_ipv4addr_param *v4;\n\tstruct sctp_ipv6addr_param *v6;\n\tunion sctp_addr_param *addr;\n\tstruct sctp_adaptation_ind_param *aind;\n\tstruct sctp_supported_ext_param *ext;\n\tstruct sctp_random_param *random;\n\tstruct sctp_chunks_param *chunks;\n\tstruct sctp_hmac_algo_param *hmac_algo;\n\tstruct sctp_addip_param *addip;\n};\n\nstruct sctp_sndrcvinfo {\n\t__u16 sinfo_stream;\n\t__u16 sinfo_ssn;\n\t__u16 sinfo_flags;\n\t__u32 sinfo_ppid;\n\t__u32 sinfo_context;\n\t__u32 sinfo_timetolive;\n\t__u32 sinfo_tsn;\n\t__u32 sinfo_cumtsn;\n\tsctp_assoc_t sinfo_assoc_id;\n};\n\nstruct sctp_datahdr;\n\nstruct sctp_inithdr;\n\nstruct sctp_sackhdr;\n\nstruct sctp_heartbeathdr;\n\nstruct sctp_sender_hb_info;\n\nstruct sctp_shutdownhdr;\n\nstruct sctp_signed_cookie;\n\nstruct sctp_ecnehdr;\n\nstruct sctp_cwrhdr;\n\nstruct sctp_errhdr;\n\nstruct sctp_fwdtsn_hdr;\n\nstruct sctp_idatahdr;\n\nstruct sctp_ifwdtsn_hdr;\n\nstruct sctp_chunkhdr;\n\nstruct sctphdr;\n\nstruct sctp_datamsg;\n\nstruct sctp_chunk {\n\tstruct list_head list;\n\trefcount_t refcnt;\n\tint sent_count;\n\tunion {\n\t\tstruct list_head transmitted_list;\n\t\tstruct list_head stream_list;\n\t};\n\tstruct list_head frag_list;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct sk_buff *head_skb;\n\t\tstruct sctp_shared_key *shkey;\n\t};\n\tunion sctp_params param_hdr;\n\tunion {\n\t\t__u8 *v;\n\t\tstruct sctp_datahdr *data_hdr;\n\t\tstruct sctp_inithdr *init_hdr;\n\t\tstruct sctp_sackhdr *sack_hdr;\n\t\tstruct sctp_heartbeathdr *hb_hdr;\n\t\tstruct sctp_sender_hb_info *hbs_hdr;\n\t\tstruct sctp_shutdownhdr *shutdown_hdr;\n\t\tstruct sctp_signed_cookie *cookie_hdr;\n\t\tstruct sctp_ecnehdr *ecne_hdr;\n\t\tstruct sctp_cwrhdr *ecn_cwr_hdr;\n\t\tstruct sctp_errhdr *err_hdr;\n\t\tstruct sctp_addiphdr *addip_hdr;\n\t\tstruct sctp_fwdtsn_hdr *fwdtsn_hdr;\n\t\tstruct sctp_authhdr *auth_hdr;\n\t\tstruct sctp_idatahdr *idata_hdr;\n\t\tstruct sctp_ifwdtsn_hdr *ifwdtsn_hdr;\n\t} subh;\n\t__u8 *chunk_end;\n\tstruct sctp_chunkhdr *chunk_hdr;\n\tstruct sctphdr *sctp_hdr;\n\tstruct sctp_sndrcvinfo sinfo;\n\tstruct sctp_association *asoc;\n\tstruct sctp_ep_common *rcvr;\n\tlong unsigned int sent_at;\n\tunion sctp_addr source;\n\tunion sctp_addr dest;\n\tstruct sctp_datamsg *msg;\n\tstruct sctp_transport *transport;\n\tstruct sk_buff *auth_chunk;\n\t__u16 rtt_in_progress: 1;\n\t__u16 has_tsn: 1;\n\t__u16 has_ssn: 1;\n\t__u16 singleton: 1;\n\t__u16 end_of_packet: 1;\n\t__u16 ecn_ce_done: 1;\n\t__u16 pdiscard: 1;\n\t__u16 tsn_gap_acked: 1;\n\t__u16 data_accepted: 1;\n\t__u16 auth: 1;\n\t__u16 has_asconf: 1;\n\t__u16 pmtu_probe: 1;\n\t__u16 tsn_missing_report: 2;\n\t__u16 fast_retransmit: 2;\n};\n\nstruct sctp_chunkhdr {\n\t__u8 type;\n\t__u8 flags;\n\t__be16 length;\n};\n\nstruct sctp_chunks_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_cookie_param {\n\tstruct sctp_paramhdr p;\n\t__u8 body[0];\n};\n\nstruct sctp_cookie_preserve_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 lifespan_increment;\n};\n\nstruct sctp_cwrhdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_datahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 ssn;\n\t__u32 ppid;\n};\n\nstruct sctp_datamsg {\n\tstruct list_head chunks;\n\trefcount_t refcnt;\n\tlong unsigned int expires_at;\n\tint send_error;\n\tu8 send_failed: 1;\n\tu8 can_delay: 1;\n\tu8 abandoned: 1;\n};\n\nstruct sctp_ecnehdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_endpoint {\n\tstruct sctp_ep_common base;\n\tstruct hlist_node node;\n\tint hashent;\n\tstruct list_head asocs;\n\tstruct hmac_sha256_key cookie_auth_key;\n\t__u32 sndbuf_policy;\n\t__u32 rcvbuf_policy;\n\tstruct sctp_hmac_algo_param *auth_hmacs_list;\n\tstruct sctp_chunks_param *auth_chunk_list;\n\tstruct list_head endpoint_shared_keys;\n\t__u16 active_key_id;\n\t__u8 ecn_enable: 1;\n\t__u8 auth_enable: 1;\n\t__u8 intl_enable: 1;\n\t__u8 prsctp_enable: 1;\n\t__u8 asconf_enable: 1;\n\t__u8 reconf_enable: 1;\n\t__u8 strreset_enable;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_errhdr {\n\t__be16 cause;\n\t__be16 length;\n};\n\nstruct sctp_fwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_heartbeathdr {\n\tstruct sctp_paramhdr info;\n};\n\nstruct sctp_hmac_algo_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 hmac_ids[0];\n};\n\nstruct sctp_hostname_param {\n\tstruct sctp_paramhdr param_hdr;\n\tuint8_t hostname[0];\n};\n\nstruct sctp_idatahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 reserved;\n\t__be32 mid;\n\tunion {\n\t\t__u32 ppid;\n\t\t__be32 fsn;\n\t};\n};\n\nstruct sctp_ifwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_inithdr {\n\t__be32 init_tag;\n\t__be32 a_rwnd;\n\t__be16 num_outbound_streams;\n\t__be16 num_inbound_streams;\n\t__be32 initial_tsn;\n};\n\nstruct sctp_initmsg {\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u16 sinit_max_attempts;\n\t__u16 sinit_max_init_timeo;\n};\n\nstruct sctp_packet {\n\t__u16 source_port;\n\t__u16 destination_port;\n\t__u32 vtag;\n\tstruct list_head chunk_list;\n\tsize_t overhead;\n\tsize_t size;\n\tsize_t max_size;\n\tstruct sctp_transport *transport;\n\tstruct sctp_chunk *auth;\n\tu8 has_cookie_echo: 1;\n\tu8 has_sack: 1;\n\tu8 has_auth: 1;\n\tu8 has_data: 1;\n\tu8 ipfragok: 1;\n};\n\nstruct sctp_paddrparams {\n\tsctp_assoc_t spp_assoc_id;\n\tstruct __kernel_sockaddr_storage spp_address;\n\t__u32 spp_hbinterval;\n\t__u16 spp_pathmaxrxt;\n\t__u32 spp_pathmtu;\n\t__u32 spp_sackdelay;\n\t__u32 spp_flags;\n\t__u32 spp_ipv6_flowlabel;\n\t__u8 spp_dscp;\n\tint: 0;\n} __attribute__((packed));\n\nstruct sctp_ulpevent;\n\nstruct sctp_pf {\n\tvoid (*event_msgname)(struct sctp_ulpevent *, char *, int *);\n\tvoid (*skb_msgname)(struct sk_buff *, char *, int *);\n\tint (*af_supported)(sa_family_t, struct sctp_sock *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *, struct sctp_sock *);\n\tint (*bind_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*send_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*supported_addrs)(const struct sctp_sock *, __be16 *);\n\tint (*addr_to_user)(struct sctp_sock *, union sctp_addr *);\n\tvoid (*to_sk_saddr)(union sctp_addr *, struct sock *);\n\tvoid (*to_sk_daddr)(union sctp_addr *, struct sock *);\n\tvoid (*copy_ip_options)(struct sock *, struct sock *);\n\tstruct sctp_af *af;\n};\n\nstruct sctp_random_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 random_val[0];\n};\n\nstruct sctp_rtoinfo {\n\tsctp_assoc_t srto_assoc_id;\n\t__u32 srto_initial;\n\t__u32 srto_max;\n\t__u32 srto_min;\n};\n\nstruct sctp_sackhdr {\n\t__be32 cum_tsn_ack;\n\t__be32 a_rwnd;\n\t__be16 num_gap_ack_blocks;\n\t__be16 num_dup_tsns;\n};\n\nstruct sctp_sender_hb_info {\n\tstruct sctp_paramhdr param_hdr;\n\tunion sctp_addr daddr;\n\tlong unsigned int sent_at;\n\t__u64 hb_nonce;\n\t__u32 probe_size;\n};\n\nstruct sctp_shared_key {\n\tstruct list_head key_list;\n\tstruct sctp_auth_bytes *key;\n\trefcount_t refcnt;\n\t__u16 key_id;\n\t__u8 deactivated;\n};\n\nstruct sctp_shutdownhdr {\n\t__be32 cum_tsn_ack;\n};\n\nstruct sctp_signed_cookie {\n\t__u8 mac[32];\n\t__u32 __pad;\n\tstruct sctp_cookie c;\n} __attribute__((packed));\n\nstruct sctp_sock {\n\tstruct inet_sock inet;\n\tenum sctp_socket_type type;\n\tstruct sctp_pf *pf;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_bind_bucket *bind_hash;\n\t__u16 default_stream;\n\t__u32 default_ppid;\n\t__u16 default_flags;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tint max_burst;\n\t__u32 hbinterval;\n\t__u32 probe_interval;\n\t__be16 udp_port;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 sackdelay;\n\t__u32 sackfreq;\n\t__u32 param_flags;\n\t__u32 default_ss;\n\tstruct sctp_rtoinfo rtoinfo;\n\tstruct sctp_paddrparams paddrparam;\n\tstruct sctp_assocparams assocparams;\n\t__u16 subscribe;\n\tstruct sctp_initmsg initmsg;\n\tint user_frag;\n\t__u32 autoclose;\n\t__u32 adaptation_ind;\n\t__u32 pd_point;\n\t__u16 nodelay: 1;\n\t__u16 pf_expose: 2;\n\t__u16 reuse: 1;\n\t__u16 disable_fragments: 1;\n\t__u16 v4mapped: 1;\n\t__u16 frag_interleave: 1;\n\t__u16 recvrcvinfo: 1;\n\t__u16 recvnxtinfo: 1;\n\t__u16 data_ready_signalled: 1;\n\t__u16 cookie_auth_enable: 1;\n\tatomic_t pd_mode;\n\tstruct sk_buff_head pd_lobby;\n\tstruct list_head auto_asconf_list;\n\tint do_auto_asconf;\n};\n\nstruct sctp_stream_interleave {\n\t__u16 data_chunk_len;\n\t__u16 ftsn_chunk_len;\n\tstruct sctp_chunk * (*make_datafrag)(const struct sctp_association *, const struct sctp_sndrcvinfo *, int, __u8, gfp_t);\n\tvoid (*assign_number)(struct sctp_chunk *);\n\tbool (*validate_data)(struct sctp_chunk *);\n\tint (*ulpevent_data)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tint (*enqueue_event)(struct sctp_ulpq *, struct sctp_ulpevent *);\n\tvoid (*renege_events)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tvoid (*start_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*abort_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*generate_ftsn)(struct sctp_outq *, __u32);\n\tbool (*validate_ftsn)(struct sctp_chunk *);\n\tvoid (*report_ftsn)(struct sctp_ulpq *, __u32);\n\tvoid (*handle_ftsn)(struct sctp_ulpq *, struct sctp_chunk *);\n};\n\nstruct sctp_stream_priorities;\n\nstruct sctp_stream_out_ext {\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tstruct list_head outq;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t\tstruct sctp_stream_priorities *prio_head;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t\t__u32 fc_length;\n\t\t\t__u16 fc_weight;\n\t\t};\n\t};\n};\n\nstruct sctp_stream_priorities {\n\tstruct list_head prio_sched;\n\tstruct list_head active;\n\tstruct sctp_stream_out_ext *next;\n\t__u16 prio;\n\t__u16 users;\n};\n\nstruct sctp_supported_addrs_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 types[0];\n};\n\nstruct sctp_supported_ext_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_transport {\n\tstruct list_head transports;\n\tstruct rhlist_head node;\n\trefcount_t refcnt;\n\t__u32 dead: 1;\n\t__u32 rto_pending: 1;\n\t__u32 hb_sent: 1;\n\t__u32 pmtu_pending: 1;\n\t__u32 dst_pending_confirm: 1;\n\t__u32 sack_generation: 1;\n\tu32 dst_cookie;\n\tstruct flowi fl;\n\tunion sctp_addr ipaddr;\n\tstruct sctp_af *af_specific;\n\tstruct sctp_association *asoc;\n\tlong unsigned int rto;\n\t__u32 rtt;\n\t__u32 rttvar;\n\t__u32 srtt;\n\t__u32 cwnd;\n\t__u32 ssthresh;\n\t__u32 partial_bytes_acked;\n\t__u32 flight_size;\n\t__u32 burst_limited;\n\tstruct dst_entry *dst;\n\tunion sctp_addr saddr;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\tlong unsigned int sackdelay;\n\t__u32 sackfreq;\n\tatomic_t mtu_info;\n\tktime_t last_time_heard;\n\tlong unsigned int last_time_sent;\n\tlong unsigned int last_time_ecne_reduced;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\tint init_sent_count;\n\tint state;\n\tshort unsigned int error_count;\n\tstruct timer_list T3_rtx_timer;\n\tstruct timer_list hb_timer;\n\tstruct timer_list proto_unreach_timer;\n\tstruct timer_list reconf_timer;\n\tstruct timer_list probe_timer;\n\tstruct list_head transmitted;\n\tstruct sctp_packet packet;\n\tstruct list_head send_ready;\n\tstruct {\n\t\t__u32 next_tsn_at_change;\n\t\tchar changeover_active;\n\t\tchar cycling_changeover;\n\t\tchar cacc_saw_newack;\n\t} cacc;\n\tstruct {\n\t\t__u16 pmtu;\n\t\t__u16 probe_size;\n\t\t__u16 probe_high;\n\t\t__u8 probe_count;\n\t\t__u8 state;\n\t} pl;\n\t__u64 hb_nonce;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_ulpevent {\n\tstruct sctp_association *asoc;\n\tstruct sctp_chunk *chunk;\n\tunsigned int rmem_len;\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\tunion {\n\t\t__u32 ppid;\n\t\t__u32 fsn;\n\t};\n\t__u32 tsn;\n\t__u32 cumtsn;\n\t__u16 stream;\n\t__u16 flags;\n\t__u16 msg_flags;\n} __attribute__((packed));\n\nstruct sctphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 vtag;\n\t__le32 checksum;\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tconst char *reason;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[1];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work error_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tvoid *__ctx[0];\n};\n\nstruct sdesc {\n\tstruct shash_desc shash;\n};\n\nstruct sdp_media_type {\n\tconst char *name;\n\tunsigned int len;\n\tenum sip_expectation_classes class;\n};\n\nstruct sdw_intel_acpi_info {\n\tacpi_handle handle;\n\tint count;\n\tu32 link_mask;\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct security_class_mapping {\n\tconst char *name;\n\tconst char *perms[33];\n};\n\nstruct timezone;\n\nstruct xattr;\n\nstruct sembuf;\n\nunion security_list_options {\n\tint (*binder_set_context_mgr)(const struct cred *);\n\tint (*binder_transaction)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_binder)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_file)(const struct cred *, const struct cred *, const struct file *);\n\tint (*ptrace_access_check)(struct task_struct *, unsigned int);\n\tint (*ptrace_traceme)(struct task_struct *);\n\tint (*capget)(const struct task_struct *, kernel_cap_t *, kernel_cap_t *, kernel_cap_t *);\n\tint (*capset)(struct cred *, const struct cred *, const kernel_cap_t *, const kernel_cap_t *, const kernel_cap_t *);\n\tint (*capable)(const struct cred *, struct user_namespace *, int, unsigned int);\n\tint (*quotactl)(int, int, int, const struct super_block *);\n\tint (*quota_on)(struct dentry *);\n\tint (*syslog)(int);\n\tint (*settime)(const struct timespec64 *, const struct timezone *);\n\tint (*vm_enough_memory)(struct mm_struct *, long int);\n\tint (*bprm_creds_for_exec)(struct linux_binprm *);\n\tint (*bprm_creds_from_file)(struct linux_binprm *, const struct file *);\n\tint (*bprm_check_security)(struct linux_binprm *);\n\tvoid (*bprm_committing_creds)(const struct linux_binprm *);\n\tvoid (*bprm_committed_creds)(const struct linux_binprm *);\n\tint (*fs_context_submount)(struct fs_context *, struct super_block *);\n\tint (*fs_context_dup)(struct fs_context *, struct fs_context *);\n\tint (*fs_context_parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*sb_alloc_security)(struct super_block *);\n\tvoid (*sb_delete)(struct super_block *);\n\tvoid (*sb_free_security)(struct super_block *);\n\tvoid (*sb_free_mnt_opts)(void *);\n\tint (*sb_eat_lsm_opts)(char *, void **);\n\tint (*sb_mnt_opts_compat)(struct super_block *, void *);\n\tint (*sb_remount)(struct super_block *, void *);\n\tint (*sb_kern_mount)(const struct super_block *);\n\tint (*sb_show_options)(struct seq_file *, struct super_block *);\n\tint (*sb_statfs)(struct dentry *);\n\tint (*sb_mount)(const char *, const struct path *, const char *, long unsigned int, void *);\n\tint (*sb_umount)(struct vfsmount *, int);\n\tint (*sb_pivotroot)(const struct path *, const struct path *);\n\tint (*sb_set_mnt_opts)(struct super_block *, void *, long unsigned int, long unsigned int *);\n\tint (*sb_clone_mnt_opts)(const struct super_block *, struct super_block *, long unsigned int, long unsigned int *);\n\tint (*move_mount)(const struct path *, const struct path *);\n\tint (*dentry_init_security)(struct dentry *, int, const struct qstr *, const char **, struct lsm_context *);\n\tint (*dentry_create_files_as)(struct dentry *, int, const struct qstr *, const struct cred *, struct cred *);\n\tint (*path_notify)(const struct path *, u64, unsigned int);\n\tint (*inode_alloc_security)(struct inode *);\n\tvoid (*inode_free_security)(struct inode *);\n\tvoid (*inode_free_security_rcu)(void *);\n\tint (*inode_init_security)(struct inode *, struct inode *, const struct qstr *, struct xattr *, int *);\n\tint (*inode_init_security_anon)(struct inode *, const struct qstr *, const struct inode *);\n\tint (*inode_create)(struct inode *, struct dentry *, umode_t);\n\tvoid (*inode_post_create_tmpfile)(struct mnt_idmap *, struct inode *);\n\tint (*inode_link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_unlink)(struct inode *, struct dentry *);\n\tint (*inode_symlink)(struct inode *, struct dentry *, const char *);\n\tint (*inode_mkdir)(struct inode *, struct dentry *, umode_t);\n\tint (*inode_rmdir)(struct inode *, struct dentry *);\n\tint (*inode_mknod)(struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*inode_rename)(struct inode *, struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_readlink)(struct dentry *);\n\tint (*inode_follow_link)(struct dentry *, struct inode *, bool);\n\tint (*inode_permission)(struct inode *, int);\n\tint (*inode_setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tvoid (*inode_post_setattr)(struct mnt_idmap *, struct dentry *, int);\n\tint (*inode_getattr)(const struct path *);\n\tint (*inode_xattr_skipcap)(const char *);\n\tint (*inode_setxattr)(struct mnt_idmap *, struct dentry *, const char *, const void *, size_t, int);\n\tvoid (*inode_post_setxattr)(struct dentry *, const char *, const void *, size_t, int);\n\tint (*inode_getxattr)(struct dentry *, const char *);\n\tint (*inode_listxattr)(struct dentry *);\n\tint (*inode_removexattr)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_removexattr)(struct dentry *, const char *);\n\tint (*inode_file_setattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_file_getattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_set_acl)(struct mnt_idmap *, struct dentry *, const char *, struct posix_acl *);\n\tvoid (*inode_post_set_acl)(struct dentry *, const char *, struct posix_acl *);\n\tint (*inode_get_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_need_killpriv)(struct dentry *);\n\tint (*inode_killpriv)(struct mnt_idmap *, struct dentry *);\n\tint (*inode_getsecurity)(struct mnt_idmap *, struct inode *, const char *, void **, bool);\n\tint (*inode_setsecurity)(struct inode *, const char *, const void *, size_t, int);\n\tint (*inode_listsecurity)(struct inode *, char *, size_t);\n\tvoid (*inode_getlsmprop)(struct inode *, struct lsm_prop *);\n\tint (*inode_copy_up)(struct dentry *, struct cred **);\n\tint (*inode_copy_up_xattr)(struct dentry *, const char *);\n\tint (*inode_setintegrity)(const struct inode *, enum lsm_integrity_type, const void *, size_t);\n\tint (*kernfs_init_security)(struct kernfs_node *, struct kernfs_node *);\n\tint (*file_permission)(struct file *, int);\n\tint (*file_alloc_security)(struct file *);\n\tvoid (*file_release)(struct file *);\n\tvoid (*file_free_security)(struct file *);\n\tint (*file_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*file_ioctl_compat)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap_addr)(long unsigned int);\n\tint (*mmap_file)(struct file *, long unsigned int, long unsigned int, long unsigned int);\n\tint (*file_mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int);\n\tint (*file_lock)(struct file *, unsigned int);\n\tint (*file_fcntl)(struct file *, unsigned int, long unsigned int);\n\tvoid (*file_set_fowner)(struct file *);\n\tint (*file_send_sigiotask)(struct task_struct *, struct fown_struct *, int);\n\tint (*file_receive)(struct file *);\n\tint (*file_open)(struct file *);\n\tint (*file_post_open)(struct file *, int);\n\tint (*file_truncate)(struct file *);\n\tint (*task_alloc)(struct task_struct *, u64);\n\tvoid (*task_free)(struct task_struct *);\n\tint (*cred_alloc_blank)(struct cred *, gfp_t);\n\tvoid (*cred_free)(struct cred *);\n\tint (*cred_prepare)(struct cred *, const struct cred *, gfp_t);\n\tvoid (*cred_transfer)(struct cred *, const struct cred *);\n\tvoid (*cred_getsecid)(const struct cred *, u32 *);\n\tvoid (*cred_getlsmprop)(const struct cred *, struct lsm_prop *);\n\tint (*kernel_act_as)(struct cred *, u32);\n\tint (*kernel_create_files_as)(struct cred *, struct inode *);\n\tint (*kernel_module_request)(char *);\n\tint (*kernel_load_data)(enum kernel_load_data_id, bool);\n\tint (*kernel_post_load_data)(char *, loff_t, enum kernel_load_data_id, char *);\n\tint (*kernel_read_file)(struct file *, enum kernel_read_file_id, bool);\n\tint (*kernel_post_read_file)(struct file *, char *, loff_t, enum kernel_read_file_id);\n\tint (*task_fix_setuid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgroups)(struct cred *, const struct cred *);\n\tint (*task_setpgid)(struct task_struct *, pid_t);\n\tint (*task_getpgid)(struct task_struct *);\n\tint (*task_getsid)(struct task_struct *);\n\tvoid (*current_getlsmprop_subj)(struct lsm_prop *);\n\tvoid (*task_getlsmprop_obj)(struct task_struct *, struct lsm_prop *);\n\tint (*task_setnice)(struct task_struct *, int);\n\tint (*task_setioprio)(struct task_struct *, int);\n\tint (*task_getioprio)(struct task_struct *);\n\tint (*task_prlimit)(const struct cred *, const struct cred *, unsigned int);\n\tint (*task_setrlimit)(struct task_struct *, unsigned int, struct rlimit *);\n\tint (*task_setscheduler)(struct task_struct *);\n\tint (*task_getscheduler)(struct task_struct *);\n\tint (*task_movememory)(struct task_struct *);\n\tint (*task_kill)(struct task_struct *, struct kernel_siginfo *, int, const struct cred *);\n\tint (*task_prctl)(int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tvoid (*task_to_inode)(struct task_struct *, struct inode *);\n\tint (*userns_create)(const struct cred *);\n\tint (*ipc_permission)(struct kern_ipc_perm *, short int);\n\tvoid (*ipc_getlsmprop)(struct kern_ipc_perm *, struct lsm_prop *);\n\tint (*msg_msg_alloc_security)(struct msg_msg *);\n\tvoid (*msg_msg_free_security)(struct msg_msg *);\n\tint (*msg_queue_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*msg_queue_free_security)(struct kern_ipc_perm *);\n\tint (*msg_queue_associate)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgctl)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgsnd)(struct kern_ipc_perm *, struct msg_msg *, int);\n\tint (*msg_queue_msgrcv)(struct kern_ipc_perm *, struct msg_msg *, struct task_struct *, long int, int);\n\tint (*shm_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*shm_free_security)(struct kern_ipc_perm *);\n\tint (*shm_associate)(struct kern_ipc_perm *, int);\n\tint (*shm_shmctl)(struct kern_ipc_perm *, int);\n\tint (*shm_shmat)(struct kern_ipc_perm *, char *, int);\n\tint (*sem_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*sem_free_security)(struct kern_ipc_perm *);\n\tint (*sem_associate)(struct kern_ipc_perm *, int);\n\tint (*sem_semctl)(struct kern_ipc_perm *, int);\n\tint (*sem_semop)(struct kern_ipc_perm *, struct sembuf *, unsigned int, int);\n\tint (*netlink_send)(struct sock *, struct sk_buff *);\n\tvoid (*d_instantiate)(struct dentry *, struct inode *);\n\tint (*getselfattr)(unsigned int, struct lsm_ctx *, u32 *, u32);\n\tint (*setselfattr)(unsigned int, struct lsm_ctx *, u32, u32);\n\tint (*getprocattr)(struct task_struct *, const char *, char **);\n\tint (*setprocattr)(const char *, void *, size_t);\n\tint (*ismaclabel)(const char *);\n\tint (*secid_to_secctx)(u32, struct lsm_context *);\n\tint (*lsmprop_to_secctx)(struct lsm_prop *, struct lsm_context *);\n\tint (*secctx_to_secid)(const char *, u32, u32 *);\n\tvoid (*release_secctx)(struct lsm_context *);\n\tvoid (*inode_invalidate_secctx)(struct inode *);\n\tint (*inode_notifysecctx)(struct inode *, void *, u32);\n\tint (*inode_setsecctx)(struct dentry *, void *, u32);\n\tint (*inode_getsecctx)(struct inode *, struct lsm_context *);\n\tint (*unix_stream_connect)(struct sock *, struct sock *, struct sock *);\n\tint (*unix_may_send)(struct socket *, struct socket *);\n\tint (*socket_create)(int, int, int, int);\n\tint (*socket_post_create)(struct socket *, int, int, int, int);\n\tint (*socket_socketpair)(struct socket *, struct socket *);\n\tint (*socket_bind)(struct socket *, struct sockaddr *, int);\n\tint (*socket_connect)(struct socket *, struct sockaddr *, int);\n\tint (*socket_listen)(struct socket *, int);\n\tint (*socket_accept)(struct socket *, struct socket *);\n\tint (*socket_sendmsg)(struct socket *, struct msghdr *, int);\n\tint (*socket_recvmsg)(struct socket *, struct msghdr *, int, int);\n\tint (*socket_getsockname)(struct socket *);\n\tint (*socket_getpeername)(struct socket *);\n\tint (*socket_getsockopt)(struct socket *, int, int);\n\tint (*socket_setsockopt)(struct socket *, int, int);\n\tint (*socket_shutdown)(struct socket *, int);\n\tint (*socket_sock_rcv_skb)(struct sock *, struct sk_buff *);\n\tint (*socket_getpeersec_stream)(struct socket *, sockptr_t, sockptr_t, unsigned int);\n\tint (*socket_getpeersec_dgram)(struct socket *, struct sk_buff *, u32 *);\n\tint (*sk_alloc_security)(struct sock *, int, gfp_t);\n\tvoid (*sk_free_security)(struct sock *);\n\tvoid (*sk_clone_security)(const struct sock *, struct sock *);\n\tvoid (*sk_getsecid)(const struct sock *, u32 *);\n\tvoid (*sock_graft)(struct sock *, struct socket *);\n\tint (*inet_conn_request)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*inet_csk_clone)(struct sock *, const struct request_sock *);\n\tvoid (*inet_conn_established)(struct sock *, struct sk_buff *);\n\tint (*secmark_relabel_packet)(u32);\n\tvoid (*secmark_refcount_inc)(void);\n\tvoid (*secmark_refcount_dec)(void);\n\tvoid (*req_classify_flow)(const struct request_sock *, struct flowi_common *);\n\tint (*tun_dev_alloc_security)(void *);\n\tint (*tun_dev_create)(void);\n\tint (*tun_dev_attach_queue)(void *);\n\tint (*tun_dev_attach)(struct sock *, void *);\n\tint (*tun_dev_open)(void *);\n\tint (*sctp_assoc_request)(struct sctp_association *, struct sk_buff *);\n\tint (*sctp_bind_connect)(struct sock *, int, struct sockaddr *, int);\n\tvoid (*sctp_sk_clone)(struct sctp_association *, struct sock *, struct sock *);\n\tint (*sctp_assoc_established)(struct sctp_association *, struct sk_buff *);\n\tint (*mptcp_add_subflow)(struct sock *, struct sock *);\n\tint (*key_alloc)(struct key *, const struct cred *, long unsigned int);\n\tint (*key_permission)(key_ref_t, const struct cred *, enum key_need_perm);\n\tint (*key_getsecurity)(struct key *, char **);\n\tvoid (*key_post_create_or_update)(struct key *, struct key *, const void *, size_t, long unsigned int, bool);\n\tint (*audit_rule_init)(u32, u32, char *, void **, gfp_t);\n\tint (*audit_rule_known)(struct audit_krule *);\n\tint (*audit_rule_match)(struct lsm_prop *, u32, u32, void *);\n\tvoid (*audit_rule_free)(void *);\n\tint (*bpf)(int, union bpf_attr *, unsigned int, bool);\n\tint (*bpf_map)(struct bpf_map *, fmode_t);\n\tint (*bpf_prog)(struct bpf_prog *);\n\tint (*bpf_map_create)(struct bpf_map *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_map_free)(struct bpf_map *);\n\tint (*bpf_prog_load)(struct bpf_prog *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_prog_free)(struct bpf_prog *);\n\tint (*bpf_token_create)(struct bpf_token *, union bpf_attr *, const struct path *);\n\tvoid (*bpf_token_free)(struct bpf_token *);\n\tint (*bpf_token_cmd)(const struct bpf_token *, enum bpf_cmd);\n\tint (*bpf_token_capable)(const struct bpf_token *, int);\n\tint (*locked_down)(enum lockdown_reason);\n\tint (*perf_event_open)(int);\n\tint (*perf_event_alloc)(struct perf_event *);\n\tint (*perf_event_read)(struct perf_event *);\n\tint (*perf_event_write)(struct perf_event *);\n\tint (*uring_override_creds)(const struct cred *);\n\tint (*uring_sqpoll)(void);\n\tint (*uring_cmd)(struct io_uring_cmd *);\n\tint (*uring_allowed)(void);\n\tvoid (*initramfs_populated)(void);\n\tint (*bdev_alloc_security)(struct block_device *);\n\tvoid (*bdev_free_security)(struct block_device *);\n\tint (*bdev_setintegrity)(struct block_device *, enum lsm_integrity_type, const void *, size_t);\n\tvoid *lsm_func_addr;\n};\n\nstruct security_hook_list {\n\tstruct lsm_static_call *scalls;\n\tunion security_list_options hook;\n\tconst struct lsm_id *lsmid;\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nstruct sel_netif {\n\tstruct list_head list;\n\tstruct netif_security_struct nsec;\n\tstruct callback_head callback_head;\n};\n\nstruct sel_netnode {\n\tstruct netnode_security_struct nsec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netnode_bkt {\n\tunsigned int size;\n\tstruct list_head list;\n};\n\nstruct sel_netport {\n\tstruct netport_security_struct psec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netport_bkt {\n\tint size;\n\tstruct list_head list;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct selinux_audit_data {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tu32 requested;\n\tu32 audited;\n\tu32 denied;\n\tint result;\n};\n\nstruct selinux_audit_rule {\n\tu32 au_seqno;\n\tstruct context___2 au_ctxt;\n};\n\nstruct selinux_avc {\n\tunsigned int avc_cache_threshold;\n\tstruct avc_cache avc_cache;\n};\n\nstruct selinux_fs_info {\n\tstruct dentry *bool_dir;\n\tunsigned int bool_num;\n\tchar **bool_pending_names;\n\tint *bool_pending_values;\n\tstruct dentry *class_dir;\n\tlong unsigned int last_class_ino;\n\tbool policy_opened;\n\tlong unsigned int last_ino;\n\tstruct super_block *sb;\n};\n\nstruct selinux_kernel_status {\n\tu32 version;\n\tu32 sequence;\n\tu32 enforcing;\n\tu32 policyload;\n\tu32 deny_unknown;\n};\n\nstruct selinux_policy;\n\nstruct selinux_policy_convert_data;\n\nstruct selinux_load_state {\n\tstruct selinux_policy *policy;\n\tstruct selinux_policy_convert_data *convert_data;\n};\n\nstruct selinux_mapping;\n\nstruct selinux_map {\n\tstruct selinux_mapping *mapping;\n\tu16 size;\n};\n\nstruct selinux_mapping {\n\tu16 value;\n\tu16 num_perms;\n\tu32 perms[32];\n};\n\nstruct selinux_mnt_opts {\n\tu32 fscontext_sid;\n\tu32 context_sid;\n\tu32 rootcontext_sid;\n\tu32 defcontext_sid;\n};\n\nstruct sidtab;\n\nstruct selinux_policy {\n\tstruct sidtab *sidtab;\n\tstruct policydb policydb;\n\tstruct selinux_map map;\n\tu32 latest_granting;\n};\n\nstruct sidtab_convert_params {\n\tstruct convert_context_args *args;\n\tstruct sidtab *target;\n};\n\nstruct selinux_policy_convert_data {\n\tstruct convert_context_args args;\n\tstruct sidtab_convert_params sidtab_params;\n};\n\nstruct selinux_state {\n\tbool enforcing;\n\tbool initialized;\n\tbool policycap[15];\n\tstruct page *status_page;\n\tstruct mutex status_lock;\n\tstruct selinux_policy *policy;\n\tstruct mutex policy_mutex;\n};\n\nstruct selnl_msg_policyload {\n\t__u32 seqno;\n};\n\nstruct selnl_msg_setenforce {\n\t__s32 val;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\ttime64_t sem_otime;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\t__kernel_long_t sem_otime;\n\t__kernel_ulong_t __unused1;\n\t__kernel_long_t sem_ctime;\n\t__kernel_ulong_t __unused2;\n\t__kernel_ulong_t sem_nsems;\n\t__kernel_ulong_t __unused3;\n\t__kernel_ulong_t __unused4;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct virtnet_sq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_tx_drops;\n\tu64_stats_t kicks;\n\tu64_stats_t tx_timeouts;\n\tu64_stats_t stop;\n\tu64_stats_t wake;\n};\n\nstruct send_queue {\n\tstruct virtqueue *vq;\n\tstruct scatterlist sg[19];\n\tchar name[16];\n\tstruct virtnet_sq_stats stats;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct napi_struct napi;\n\tbool reset;\n\tstruct xsk_buff_pool *xsk_pool;\n\tdma_addr_t xsk_hdr_dma_addr;\n};\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n\tbool has_siginfo;\n\tstruct kernel_siginfo info;\n};\n\nstruct sensor_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint index;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct seqcount_rwlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_rwlock seqcount_rwlock_t;\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct serial_ctrl_device {\n\tstruct device dev;\n\tstruct ida port_ida;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_in_rdev {\n\tstruct rb_root_cached serial_rb;\n\tspinlock_t serial_lock;\n\twait_queue_head_t serial_io_wait;\n};\n\nstruct serial_port_device {\n\tstruct device dev;\n\tstruct uart_port *port;\n\tunsigned int tx_enabled: 1;\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\nstruct serial_struct32 {\n\tcompat_int_t type;\n\tcompat_int_t line;\n\tcompat_uint_t port;\n\tcompat_int_t irq;\n\tcompat_int_t flags;\n\tcompat_int_t xmit_fifo_size;\n\tcompat_int_t custom_divisor;\n\tcompat_int_t baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char;\n\tcompat_int_t hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tcompat_uint_t iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tcompat_int_t reserved;\n};\n\ntypedef struct serio *class_serio_pause_rx_t;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nstruct serport {\n\tstruct tty_struct *tty;\n\twait_queue_head_t wait;\n\tstruct serio *serio;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_config_request {\n\tstruct usb_device *udev;\n\tint config;\n\tstruct work_struct work;\n\tstruct list_head node;\n};\n\nstruct set_event_iter {\n\tenum set_event_iter_type type;\n\tunion {\n\t\tstruct trace_event_file *file;\n\t\tstruct event_mod_load *event_mod;\n\t};\n};\n\nstruct set_mtrr_data {\n\tlong unsigned int smp_base;\n\tlong unsigned int smp_size;\n\tunsigned int smp_reg;\n\tmtrr_type smp_type;\n};\n\nstruct set_proto_ctx_engines {\n\tstruct drm_i915_private *i915;\n\tunsigned int num_engines;\n\tstruct i915_gem_proto_engine *engines;\n};\n\nstruct setup_data_node {\n\tu64 paddr;\n\tu32 type;\n\tu32 len;\n};\n\nstruct setup_indirect {\n\t__u32 type;\n\t__u32 reserved;\n\t__u64 len;\n\t__u64 addr;\n};\n\nstruct sev_config {\n\t__u64 debug: 1;\n\t__u64 ghcbs_initialized: 1;\n\t__u64 use_cas: 1;\n\t__u64 __reserved: 61;\n};\n\nstruct severity {\n\tu64 mask;\n\tu64 result;\n\tunsigned char sev;\n\tshort unsigned int mcgmask;\n\tshort unsigned int mcgres;\n\tunsigned char ser;\n\tunsigned char context;\n\tunsigned char excp;\n\tunsigned char covered;\n\tunsigned int cpu_vfm;\n\tunsigned char cpu_minstepping;\n\tunsigned char bank_lo;\n\tunsigned char bank_hi;\n\tchar *msg;\n};\n\nstruct sfc_lock_data {\n\ti915_reg_t lock_reg;\n\ti915_reg_t ack_reg;\n\ti915_reg_t usage_reg;\n\tu32 lock_bit;\n\tu32 ack_bit;\n\tu32 usage_bit;\n\tu32 reset_bit;\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_module_caps {\n\tlong unsigned int interfaces[1];\n\tlong unsigned int link_modes[2];\n\tbool may_have_phy;\n\tu8 port;\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *, struct phy_device *);\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_device {\n\tstruct scsi_device *device;\n\twait_queue_head_t open_wait;\n\tstruct mutex open_rel_lock;\n\tint sg_tablesize;\n\tu32 index;\n\tstruct list_head sfds;\n\trwlock_t sfd_lock;\n\tatomic_t detaching;\n\tbool exclude;\n\tint open_cnt;\n\tchar sgdebug;\n\tchar name[32];\n\tstruct cdev *cdev;\n\tstruct kref d_ref;\n};\n\ntypedef struct sg_device Sg_device;\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_scatter_hold {\n\tshort unsigned int k_use_sg;\n\tunsigned int sglist_len;\n\tunsigned int bufflen;\n\tstruct page **pages;\n\tint page_order;\n\tchar dio_in_use;\n\tunsigned char cmd_opcode;\n};\n\ntypedef struct sg_scatter_hold Sg_scatter_hold;\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\ntypedef struct sg_io_hdr sg_io_hdr_t;\n\nstruct sg_fd;\n\nstruct sg_request {\n\tstruct list_head entry;\n\tstruct sg_fd *parentfp;\n\tSg_scatter_hold data;\n\tsg_io_hdr_t header;\n\tunsigned char sense_b[96];\n\tchar res_used;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar done;\n\tstruct request *rq;\n\tstruct bio *bio;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_request Sg_request;\n\nstruct sg_fd {\n\tstruct list_head sfd_siblings;\n\tstruct sg_device *parentdp;\n\twait_queue_head_t read_wait;\n\trwlock_t rq_list_lock;\n\tstruct mutex f_mutex;\n\tint timeout;\n\tint timeout_user;\n\tSg_scatter_hold reserve;\n\tstruct list_head rq_list;\n\tstruct fasync_struct *async_qp;\n\tSg_request req_arr[16];\n\tchar force_packid;\n\tchar cmd_q;\n\tunsigned char next_cmd_len;\n\tchar keep_orphan;\n\tchar mmap_called;\n\tchar res_in_use;\n\tstruct kref f_ref;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_fd Sg_fd;\n\nstruct sg_header {\n\tint pack_len;\n\tint reply_len;\n\tint pack_id;\n\tint result;\n\tunsigned int twelve_byte: 1;\n\tunsigned int target_status: 5;\n\tunsigned int host_status: 8;\n\tunsigned int driver_status: 8;\n\tunsigned int other_flags: 10;\n\tunsigned char sense_buffer[16];\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_list {\n\tunsigned int n;\n\tunsigned int size;\n\tsize_t len;\n\tstruct scatterlist *sg;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sg_proc_deviter {\n\tloff_t index;\n\tsize_t max;\n};\n\nstruct sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\ntypedef struct sg_req_info sg_req_info_t;\n\nstruct sg_scsi_id {\n\tint host_no;\n\tint channel;\n\tint scsi_id;\n\tint lun;\n\tint scsi_type;\n\tshort int h_cmd_per_lun;\n\tshort int d_queue_depth;\n\tint unused[2];\n};\n\ntypedef struct sg_scsi_id sg_scsi_id_t;\n\nstruct sgt_dma {\n\tstruct scatterlist *sg;\n\tdma_addr_t dma;\n\tdma_addr_t max;\n};\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha384_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct sha3_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct sha512_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct shake_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct shared_policy {\n\tstruct rb_root root;\n\trwlock_t lock;\n};\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*export_core)(struct shash_desc *, void *);\n\tint (*import_core)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tint (*clone_tfm)(struct crypto_shash *, struct crypto_shash *);\n\tunsigned int descsize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int digestsize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct hash_alg_common halg;\n\t};\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[120];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\t__kernel_size_t shm_segsz;\n\tlong int shm_atime;\n\tlong int shm_dtime;\n\tlong int shm_ctime;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct shortname_info {\n\tunsigned char lower: 1;\n\tunsigned char upper: 1;\n\tunsigned char valid: 1;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct sidtab_node_inner;\n\nstruct sidtab_node_leaf;\n\nunion sidtab_entry_inner {\n\tstruct sidtab_node_inner *ptr_inner;\n\tstruct sidtab_node_leaf *ptr_leaf;\n};\n\nstruct sidtab_str_cache;\n\nstruct sidtab_entry {\n\tu32 sid;\n\tu32 hash;\n\tstruct context___2 context;\n\tstruct sidtab_str_cache *cache;\n\tstruct hlist_node list;\n};\n\nstruct sidtab_isid_entry {\n\tint set;\n\tstruct sidtab_entry entry;\n};\n\nstruct sidtab {\n\tunion sidtab_entry_inner roots[4];\n\tu32 count;\n\tstruct sidtab_convert_params *convert;\n\tbool frozen;\n\tspinlock_t lock;\n\tu32 cache_free_slots;\n\tstruct list_head cache_lru_list;\n\tspinlock_t cache_lock;\n\tstruct sidtab_isid_entry isids[27];\n\tstruct hlist_head context_to_sid[512];\n};\n\nstruct sidtab_node_inner {\n\tunion sidtab_entry_inner entries[512];\n};\n\nstruct sidtab_node_leaf {\n\tstruct sidtab_entry entries[39];\n};\n\nstruct sidtab_str_cache {\n\tstruct callback_head rcu_member;\n\tstruct list_head lru_member;\n\tstruct sidtab_entry *parent;\n\tu32 len;\n\tchar str[0];\n};\n\nstruct sig_alg {\n\tint (*sign)(struct crypto_sig *, const void *, unsigned int, void *, unsigned int);\n\tint (*verify)(struct crypto_sig *, const void *, unsigned int, const void *, unsigned int);\n\tint (*set_pub_key)(struct crypto_sig *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_sig *, const void *, unsigned int);\n\tunsigned int (*key_size)(struct crypto_sig *);\n\tunsigned int (*digest_size)(struct crypto_sig *);\n\tunsigned int (*max_size)(struct crypto_sig *);\n\tint (*init)(struct crypto_sig *);\n\tvoid (*exit)(struct crypto_sig *);\n\tstruct crypto_alg base;\n};\n\nstruct sig_instance {\n\tvoid (*free)(struct sig_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[72];\n\t\t\tstruct crypto_instance base;\n\t\t};\n\t\tstruct sig_alg alg;\n\t};\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sigframe_ia32 {\n\tu32 pretcode;\n\tint sig;\n\tstruct sigcontext_32 sc;\n\tstruct _fpstate_32 fpstate_unused;\n\tunsigned int extramask[1];\n\tchar retcode[8];\n};\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {\n\tu64 rchar;\n\tu64 wchar;\n\tu64 syscr;\n\tu64 syscw;\n\tu64 read_bytes;\n\tu64 write_bytes;\n\tu64 cancelled_write_bytes;\n};\n\nstruct taskstats;\n\nstruct tty_audit_buf;\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct pacct_struct pacct;\n\tstruct taskstats *stats;\n\tunsigned int audit_tty;\n\tstruct tty_audit_buf *tty_audit_buf;\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct sil164_priv {\n\tbool quiet;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct sioc_sg_req {\n\tstruct in_addr src;\n\tstruct in_addr grp;\n\tlong unsigned int pktcnt;\n\tlong unsigned int bytecnt;\n\tlong unsigned int wrong_if;\n};\n\nstruct sioc_vif_req {\n\tvifi_t vifi;\n\tlong unsigned int icount;\n\tlong unsigned int ocount;\n\tlong unsigned int ibytes;\n\tlong unsigned int obytes;\n};\n\nstruct sip_handler {\n\tconst char *method;\n\tunsigned int len;\n\tint (*request)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int);\n\tint (*response)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, unsigned int);\n};\n\nstruct sip_header {\n\tconst char *name;\n\tconst char *cname;\n\tconst char *search;\n\tunsigned int len;\n\tunsigned int clen;\n\tunsigned int slen;\n\tint (*match_len)(const struct nf_conn *, const char *, const char *, int *);\n};\n\nstruct sit_net {\n\tstruct ip_tunnel *tunnels_r_l[16];\n\tstruct ip_tunnel *tunnels_r[16];\n\tstruct ip_tunnel *tunnels_l[16];\n\tstruct ip_tunnel *tunnels_wc[1];\n\tstruct ip_tunnel **tunnels[4];\n\tstruct net_device *fb_tunnel_dev;\n};\n\nstruct sixaxis_led {\n\tu8 time_enabled;\n\tu8 duty_length;\n\tu8 enabled;\n\tu8 duty_off;\n\tu8 duty_on;\n};\n\nstruct sixaxis_rumble {\n\tu8 padding;\n\tu8 right_duration;\n\tu8 right_motor_on;\n\tu8 left_duration;\n\tu8 left_motor_force;\n};\n\nstruct sixaxis_output_report {\n\tu8 report_id;\n\tstruct sixaxis_rumble rumble;\n\tu8 padding[4];\n\tu8 leds_bitmap;\n\tstruct sixaxis_led led[4];\n\tstruct sixaxis_led _reserved;\n};\n\nunion sixaxis_output_report_01 {\n\tstruct sixaxis_output_report data;\n\tu8 buf[36];\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct sk_security_struct {\n\tenum {\n\t\tNLBL_UNSET = 0,\n\t\tNLBL_REQUIRE = 1,\n\t\tNLBL_LABELED = 2,\n\t\tNLBL_REQSKB = 3,\n\t\tNLBL_CONNLABELED = 4,\n\t} nlbl_state;\n\tstruct netlbl_lsm_secattr *nlbl_secattr;\n\tu32 sid;\n\tu32 peer_sid;\n\tu16 sclass;\n\tenum {\n\t\tSCTP_ASSOC_UNSET = 0,\n\t\tSCTP_ASSOC_SET = 1,\n\t} sctp_assoc_state;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct skb_ext {\n\trefcount_t refcnt;\n\tu8 offset[1];\n\tu8 chunks;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*export)(struct skcipher_request *, void *);\n\tint (*import)(struct skcipher_request *, const void *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int walksize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int min_keysize;\n\t\t\tunsigned int max_keysize;\n\t\t\tunsigned int ivsize;\n\t\t\tunsigned int chunksize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct skcipher_alg_common co;\n\t};\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[88];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int nbytes;\n\tunsigned int total;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct skl_dpll_regs {\n\ti915_reg_t ctl;\n\ti915_reg_t cfgcr1;\n\ti915_reg_t cfgcr2;\n};\n\nstruct skl_hw_state {\n\tstruct skl_ddb_entry ddb[8];\n\tstruct skl_ddb_entry ddb_y[8];\n\tu16 min_ddb[8];\n\tu16 interim_ddb[8];\n\tstruct skl_pipe_wm wm;\n};\n\nstruct skl_plane_ddb_iter {\n\tu64 data_rate;\n\tu16 start;\n\tu16 size;\n};\n\nstruct skl_prefill_ctx {\n\tstruct {\n\t\tunsigned int fixed;\n\t\tunsigned int wm0;\n\t\tunsigned int scaler_1st;\n\t\tunsigned int scaler_2nd;\n\t\tunsigned int dsc;\n\t\tunsigned int full;\n\t} prefill;\n\tstruct {\n\t\tunsigned int cdclk;\n\t\tunsigned int scaler_1st;\n\t\tunsigned int scaler_2nd;\n\t} adj;\n};\n\nstruct skl_wm_params {\n\tbool x_tiled;\n\tbool y_tiled;\n\tbool rc_surface;\n\tbool is_planar;\n\tu32 width;\n\tu8 cpp;\n\tu32 plane_pixel_rate;\n\tu32 y_min_scanlines;\n\tu32 plane_bytes_per_line;\n\tuint_fixed_16_16_t plane_blocks_per_line;\n\tuint_fixed_16_16_t y_tile_minimum;\n\tu32 linetime_us;\n\tu32 dbuf_block_size;\n};\n\nstruct skl_wrpll_context {\n\tu64 min_deviation;\n\tu64 central_freq;\n\tu64 dco_freq;\n\tunsigned int p;\n};\n\nstruct sku_microcode {\n\tu32 vfm;\n\tu8 stepping;\n\tu32 microcode;\n};\n\nstruct sky2_status_le;\n\nstruct sky2_hw {\n\tvoid *regs;\n\tstruct pci_dev *pdev;\n\tstruct napi_struct napi;\n\tstruct net_device *dev[2];\n\tlong unsigned int flags;\n\tu8 chip_id;\n\tu8 chip_rev;\n\tu8 pmd_type;\n\tu8 ports;\n\tstruct sky2_status_le *st_le;\n\tu32 st_size;\n\tu32 st_idx;\n\tdma_addr_t st_dma;\n\tstruct timer_list watchdog_timer;\n\tstruct work_struct restart_work;\n\twait_queue_head_t msi_wait;\n\tchar irq_name[0];\n};\n\nstruct sky2_stats {\n\tstruct u64_stats_sync syncp;\n\tu64 packets;\n\tu64 bytes;\n};\n\nstruct tx_ring_info;\n\nstruct sky2_tx_le;\n\nstruct sky2_rx_le;\n\nstruct sky2_port {\n\tstruct sky2_hw *hw;\n\tstruct net_device *netdev;\n\tunsigned int port;\n\tu32 msg_enable;\n\tspinlock_t phy_lock;\n\tstruct tx_ring_info *tx_ring;\n\tstruct sky2_tx_le *tx_le;\n\tstruct sky2_stats tx_stats;\n\tu16 tx_ring_size;\n\tu16 tx_cons;\n\tu16 tx_prod;\n\tu16 tx_next;\n\tu16 tx_pending;\n\tu16 tx_last_mss;\n\tu32 tx_last_upper;\n\tu32 tx_tcpsum;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rx_ring_info *rx_ring;\n\tstruct sky2_rx_le *rx_le;\n\tstruct sky2_stats rx_stats;\n\tu16 rx_next;\n\tu16 rx_put;\n\tu16 rx_pending;\n\tu16 rx_data_size;\n\tu16 rx_nfrags;\n\tlong unsigned int last_rx;\n\tstruct {\n\t\tlong unsigned int last;\n\t\tu32 mac_rp;\n\t\tu8 mac_lev;\n\t\tu8 fifo_rp;\n\t\tu8 fifo_lev;\n\t} check;\n\tdma_addr_t rx_le_map;\n\tdma_addr_t tx_le_map;\n\tu16 advertising;\n\tu16 speed;\n\tu8 wol;\n\tu8 duplex;\n\tu16 flags;\n\tenum flow_control flow_mode;\n\tenum flow_control flow_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sky2_rx_le {\n\t__le32 addr;\n\t__le16 length;\n\tu8 ctrl;\n\tu8 opcode;\n};\n\nstruct sky2_stat {\n\tchar name[32];\n\tu16 offset;\n};\n\nstruct sky2_status_le {\n\t__le32 status;\n\t__le16 length;\n\tu8 css;\n\tu8 opcode;\n};\n\nstruct sky2_tx_le {\n\t__le32 addr;\n\t__le16 length;\n\tu8 ctrl;\n\tu8 opcode;\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong: 64;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct slpc_override_params {\n\tu32 bits[8];\n\tu32 values[256];\n};\n\nstruct slpc_shared_data_header {\n\tu32 size;\n\tu32 global_state;\n\tu32 display_data_addr;\n};\n\nstruct slpc_task_state_data {\n\tunion {\n\t\tu32 task_status_padding;\n\t\tstruct {\n\t\t\tu32 status;\n\t\t};\n\t};\n\tunion {\n\t\tu32 freq_padding;\n\t\tstruct {\n\t\t\tu32 freq;\n\t\t};\n\t};\n};\n\nstruct slpc_shared_data {\n\tstruct slpc_shared_data_header header;\n\tu8 shared_data_header_pad[52];\n\tu8 platform_info_pad[64];\n\tstruct slpc_task_state_data task_state_data;\n\tu8 task_state_data_pad[56];\n\tstruct slpc_override_params override_params;\n\tu8 override_params_pad[32];\n\tu8 shared_data_pad[2816];\n\tu8 reserved_mode_definition[4096];\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct smca_hwid;\n\nstruct smca_bank {\n\tconst struct smca_hwid *hwid;\n\tu32 id;\n\tu8 sysfs_id;\n\tu64 paddrv: 1;\n\tlong: 23;\n\tu64 __reserved: 63;\n};\n\nstruct smca_hwid {\n\tunsigned int bank_type;\n\tu32 hwid_mcatype;\n};\n\nstruct smp_alt_module {\n\tstruct module *mod;\n\tchar *name;\n\tconst s32 *locks;\n\tconst s32 *locks_end;\n\tu8 *text;\n\tu8 *text_end;\n\tstruct list_head next;\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smp_ops {\n\tvoid (*smp_prepare_boot_cpu)(void);\n\tvoid (*smp_prepare_cpus)(unsigned int);\n\tvoid (*smp_cpus_done)(unsigned int);\n\tvoid (*stop_other_cpus)(int);\n\tvoid (*crash_stop_other_cpus)(void);\n\tvoid (*smp_send_reschedule)(int);\n\tvoid (*cleanup_dead_cpu)(unsigned int);\n\tvoid (*poll_sync_state)(void);\n\tint (*kick_ap_alive)(unsigned int, struct task_struct *);\n\tint (*cpu_disable)(void);\n\tvoid (*cpu_die)(unsigned int);\n\tvoid (*play_dead)(void);\n\tvoid (*stop_this_cpu)(void);\n\tvoid (*send_call_func_ipi)(const struct cpumask *);\n\tvoid (*send_call_func_single_ipi)(int);\n};\n\nstruct smp_text_poke_loc {\n\ts32 rel_addr;\n\ts32 disp;\n\tu8 len;\n\tu8 opcode;\n\tconst u8 text[5];\n\tu8 old;\n};\n\nstruct smp_text_poke_array {\n\tstruct smp_text_poke_loc vec[256];\n\tint nr_entries;\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct snap {\n\tint slen;\n\tchar str[80];\n};\n\nstruct snapshot_handle {\n\tunsigned int cur;\n\tvoid *buffer;\n\tint sync_read;\n};\n\nstruct snapshot_data {\n\tstruct snapshot_handle handle;\n\tint swap;\n\tint mode;\n\tbool frozen;\n\tbool ready;\n\tbool platform_support;\n\tbool free_bitmaps;\n\tdev_t dev;\n};\n\nstruct snd_aes_iec958 {\n\tunsigned char status[24];\n\tunsigned char subcode[147];\n\tunsigned char pad;\n\tunsigned char dig_subframe[4];\n};\n\nstruct snd_shutdown_f_ops;\n\nstruct snd_info_entry;\n\nstruct snd_card {\n\tint number;\n\tchar id[16];\n\tchar driver[16];\n\tchar shortname[32];\n\tchar longname[80];\n\tchar irq_descr[32];\n\tchar mixername[80];\n\tchar components[128];\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_card *);\n\tstruct list_head devices;\n\tstruct device *ctl_dev;\n\tunsigned int last_numid;\n\tstruct rw_semaphore controls_rwsem;\n\trwlock_t controls_rwlock;\n\tint controls_count;\n\tsize_t user_ctl_alloc_size;\n\tstruct list_head controls;\n\tstruct list_head ctl_files;\n\tstruct xarray ctl_numids;\n\tstruct xarray ctl_hash;\n\tbool ctl_hash_collision;\n\tstruct snd_info_entry *proc_root;\n\tstruct proc_dir_entry *proc_root_link;\n\tstruct list_head files_list;\n\tstruct snd_shutdown_f_ops *s_f_ops;\n\tspinlock_t files_lock;\n\tint shutdown;\n\tstruct completion *release_completion;\n\tstruct device *dev;\n\tstruct device card_dev;\n\tconst struct attribute_group *dev_groups[4];\n\tbool registered;\n\tbool managed;\n\tbool releasing;\n\tint sync_irq;\n\twait_queue_head_t remove_sleep;\n\tsize_t total_pcm_alloc_bytes;\n\tstruct mutex memory_mutex;\n\tunsigned int power_state;\n\tatomic_t power_ref;\n\twait_queue_head_t power_sleep;\n\twait_queue_head_t power_ref_sleep;\n};\n\nstruct snd_enc_wma {\n\t__u32 super_block_align;\n};\n\nstruct snd_enc_vorbis {\n\t__s32 quality;\n\t__u32 managed;\n\t__u32 max_bit_rate;\n\t__u32 min_bit_rate;\n\t__u32 downmix;\n};\n\nstruct snd_enc_real {\n\t__u32 quant_bits;\n\t__u32 start_region;\n\t__u32 num_regions;\n};\n\nstruct snd_enc_flac {\n\t__u32 num;\n\t__u32 gain;\n};\n\nstruct snd_enc_generic {\n\t__u32 bw;\n\t__s32 reserved[15];\n};\n\nstruct snd_dec_flac {\n\t__u16 sample_size;\n\t__u16 min_blk_size;\n\t__u16 max_blk_size;\n\t__u16 min_frame_size;\n\t__u16 max_frame_size;\n\t__u16 reserved;\n};\n\nstruct snd_dec_wma {\n\t__u32 encoder_option;\n\t__u32 adv_encoder_option;\n\t__u32 adv_encoder_option2;\n\t__u32 reserved;\n};\n\nstruct snd_dec_alac {\n\t__u32 frame_length;\n\t__u8 compatible_version;\n\t__u8 pb;\n\t__u8 mb;\n\t__u8 kb;\n\t__u32 max_run;\n\t__u32 max_frame_bytes;\n};\n\nstruct snd_dec_ape {\n\t__u16 compatible_version;\n\t__u16 compression_level;\n\t__u32 format_flags;\n\t__u32 blocks_per_frame;\n\t__u32 final_frame_blocks;\n\t__u32 total_frames;\n\t__u32 seek_table_present;\n};\n\nstruct snd_dec_opus_ch_map {\n\t__u8 stream_count;\n\t__u8 coupled_count;\n\t__u8 channel_map[8];\n};\n\nstruct snd_dec_opus {\n\t__u8 version;\n\t__u8 num_channels;\n\t__u16 pre_skip;\n\t__u32 sample_rate;\n\t__u16 output_gain;\n\t__u8 mapping_family;\n\tstruct snd_dec_opus_ch_map chan_map;\n};\n\nunion snd_codec_options {\n\tstruct snd_enc_wma wma;\n\tstruct snd_enc_vorbis vorbis;\n\tstruct snd_enc_real real;\n\tstruct snd_enc_flac flac;\n\tstruct snd_enc_generic generic;\n\tstruct snd_dec_flac flac_d;\n\tstruct snd_dec_wma wma_d;\n\tstruct snd_dec_alac alac_d;\n\tstruct snd_dec_ape ape_d;\n\tstruct snd_dec_opus opus_d;\n\tstruct {\n\t\t__u32 out_sample_rate;\n\t} src_d;\n};\n\nstruct snd_codec {\n\t__u32 id;\n\t__u32 ch_in;\n\t__u32 ch_out;\n\t__u32 sample_rate;\n\t__u32 bit_rate;\n\t__u32 rate_control;\n\t__u32 profile;\n\t__u32 level;\n\t__u32 ch_mode;\n\t__u32 format;\n\t__u32 align;\n\tunion snd_codec_options options;\n\t__u32 pcm_format;\n\t__u32 reserved[2];\n};\n\nstruct snd_codec_desc_src {\n\t__u32 out_sample_rate_min;\n\t__u32 out_sample_rate_max;\n};\n\nstruct snd_codec_desc {\n\t__u32 max_ch;\n\t__u32 sample_rates[32];\n\t__u32 num_sample_rates;\n\t__u32 bit_rate[32];\n\t__u32 num_bitrates;\n\t__u32 rate_control;\n\t__u32 profiles;\n\t__u32 modes;\n\t__u32 formats;\n\t__u32 min_buffer;\n\t__u32 pcm_formats;\n\tunion {\n\t\t__u32 u_space[6];\n\t\tstruct snd_codec_desc_src src;\n\t};\n\t__u32 reserved[8];\n};\n\nstruct snd_compr_ops;\n\nstruct snd_compr {\n\tconst char *name;\n\tstruct device *dev;\n\tstruct snd_compr_ops *ops;\n\tvoid *private_data;\n\tstruct snd_card *card;\n\tunsigned int direction;\n\tstruct mutex lock;\n\tint device;\n\tbool use_pause_in_draining;\n\tchar id[64];\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_info_entry *proc_info_entry;\n};\n\nstruct snd_compr_caps {\n\t__u32 num_codecs;\n\t__u32 direction;\n\t__u32 min_fragment_size;\n\t__u32 max_fragment_size;\n\t__u32 min_fragments;\n\t__u32 max_fragments;\n\t__u32 codecs[32];\n\t__u32 reserved[11];\n};\n\nstruct snd_compr_codec_caps {\n\t__u32 codec;\n\t__u32 num_descriptors;\n\tstruct snd_codec_desc descriptor[32];\n};\n\nstruct snd_compr_metadata {\n\t__u32 key;\n\t__u32 value[8];\n};\n\nstruct snd_compr_params;\n\nstruct snd_compr_tstamp64;\n\nstruct snd_compr_ops {\n\tint (*open)(struct snd_compr_stream *);\n\tint (*free)(struct snd_compr_stream *);\n\tint (*set_params)(struct snd_compr_stream *, struct snd_compr_params *);\n\tint (*get_params)(struct snd_compr_stream *, struct snd_codec *);\n\tint (*set_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*get_metadata)(struct snd_compr_stream *, struct snd_compr_metadata *);\n\tint (*trigger)(struct snd_compr_stream *, int);\n\tint (*pointer)(struct snd_compr_stream *, struct snd_compr_tstamp64 *);\n\tint (*copy)(struct snd_compr_stream *, char *, size_t);\n\tint (*mmap)(struct snd_compr_stream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_compr_stream *, size_t);\n\tint (*get_caps)(struct snd_compr_stream *, struct snd_compr_caps *);\n\tint (*get_codec_caps)(struct snd_compr_stream *, struct snd_compr_codec_caps *);\n};\n\nstruct snd_compressed_buffer {\n\t__u32 fragment_size;\n\t__u32 fragments;\n};\n\nstruct snd_compr_params {\n\tstruct snd_compressed_buffer buffer;\n\tstruct snd_codec codec;\n\t__u8 no_wake_mode;\n};\n\nstruct snd_compr_runtime {\n\tsnd_pcm_state_t state;\n\tstruct snd_compr_ops *ops;\n\tvoid *buffer;\n\tu64 buffer_size;\n\tu32 fragment_size;\n\tu32 fragments;\n\tu64 total_bytes_available;\n\tu64 total_bytes_transferred;\n\twait_queue_head_t sleep;\n\tvoid *private_data;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n};\n\nstruct snd_compr_stream {\n\tconst char *name;\n\tstruct snd_compr_ops *ops;\n\tstruct snd_compr_runtime *runtime;\n\tstruct snd_compr *device;\n\tstruct delayed_work error_work;\n\tenum snd_compr_direction direction;\n\tbool metadata_set;\n\tbool next_track;\n\tbool partial_drain;\n\tbool pause_in_draining;\n\tvoid *private_data;\n\tstruct snd_dma_buffer dma_buffer;\n};\n\nstruct snd_compr_tstamp64 {\n\t__u32 byte_offset;\n\t__u64 copied_total;\n\t__u64 pcm_frames;\n\t__u64 pcm_io_frames;\n\t__u32 sampling_rate;\n} __attribute__((packed));\n\nstruct snd_ctl_card_info {\n\tint card;\n\tint pad;\n\tunsigned char id[16];\n\tunsigned char driver[16];\n\tunsigned char name[32];\n\tunsigned char longname[80];\n\tunsigned char reserved_[16];\n\tunsigned char mixername[80];\n\tunsigned char components[128];\n};\n\nstruct snd_ctl_elem_info {\n\tstruct snd_ctl_elem_id id;\n\tsnd_ctl_elem_type_t type;\n\tunsigned int access;\n\tunsigned int count;\n\t__kernel_pid_t owner;\n\tunion {\n\t\tstruct {\n\t\t\tlong int min;\n\t\t\tlong int max;\n\t\t\tlong int step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tlong long int min;\n\t\t\tlong long int max;\n\t\t\tlong long int step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tunsigned int items;\n\t\t\tunsigned int item;\n\t\t\tchar name[64];\n\t\t\t__u64 names_ptr;\n\t\t\tunsigned int names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_info32 {\n\tstruct snd_ctl_elem_id id;\n\ts32 type;\n\tu32 access;\n\tu32 count;\n\ts32 owner;\n\tunion {\n\t\tstruct {\n\t\t\ts32 min;\n\t\t\ts32 max;\n\t\t\ts32 step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tu64 min;\n\t\t\tu64 max;\n\t\t\tu64 step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tu32 items;\n\t\t\tu32 item;\n\t\t\tchar name[64];\n\t\t\tu64 names_ptr;\n\t\t\tu32 names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_list {\n\tunsigned int offset;\n\tunsigned int space;\n\tunsigned int used;\n\tunsigned int count;\n\tstruct snd_ctl_elem_id *pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_list32 {\n\tu32 offset;\n\tu32 space;\n\tu32 used;\n\tu32 count;\n\tu32 pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_value {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect: 1;\n\tunion {\n\t\tunion {\n\t\t\tlong int value[128];\n\t\t\tlong int *value_ptr;\n\t\t} integer;\n\t\tunion {\n\t\t\tlong long int value[64];\n\t\t\tlong long int *value_ptr;\n\t\t} integer64;\n\t\tunion {\n\t\t\tunsigned int item[128];\n\t\t\tunsigned int *item_ptr;\n\t\t} enumerated;\n\t\tunion {\n\t\t\tunsigned char data[512];\n\t\t\tunsigned char *data_ptr;\n\t\t} bytes;\n\t\tstruct snd_aes_iec958 iec958;\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_ctl_elem_value32 {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect;\n\tunion {\n\t\ts32 integer[128];\n\t\tunsigned char data[512];\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_ctl_event {\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int mask;\n\t\t\tstruct snd_ctl_elem_id id;\n\t\t} elem;\n\t\tunsigned char data8[60];\n\t} data;\n};\n\nstruct snd_fasync;\n\nstruct snd_ctl_file {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tstruct pid *pid;\n\tint preferred_subdevice[2];\n\twait_queue_head_t change_sleep;\n\tspinlock_t read_lock;\n\tstruct snd_fasync *fasync;\n\tint subscribed;\n\tstruct list_head events;\n};\n\nstruct snd_ctl_layer_ops {\n\tstruct snd_ctl_layer_ops *next;\n\tconst char *module_name;\n\tvoid (*lregister)(struct snd_card *);\n\tvoid (*ldisconnect)(struct snd_card *);\n\tvoid (*lnotify)(struct snd_card *, unsigned int, struct snd_kcontrol *, unsigned int);\n};\n\nstruct snd_ctl_tlv {\n\tunsigned int numid;\n\tunsigned int length;\n\tunsigned int tlv[0];\n};\n\nstruct snd_device_ops;\n\nstruct snd_device {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tenum snd_device_state state;\n\tenum snd_device_type type;\n\tvoid *device_data;\n\tconst struct snd_device_ops *ops;\n};\n\nstruct snd_device_ops {\n\tint (*dev_free)(struct snd_device *);\n\tint (*dev_register)(struct snd_device *);\n\tint (*dev_disconnect)(struct snd_device *);\n};\n\nstruct snd_dma_data {\n\tint dma;\n};\n\nstruct snd_dma_sg_fallback {\n\tstruct sg_table sgt;\n\tsize_t count;\n\tstruct page **pages;\n\tunsigned int *npages;\n};\n\nstruct snd_fasync {\n\tstruct fasync_struct *fasync;\n\tint signal;\n\tint poll;\n\tint on;\n\tstruct list_head list;\n};\n\nstruct snd_hda_pin_quirk {\n\tunsigned int codec;\n\tshort unsigned int subvendor;\n\tconst struct hda_pintbl *pins;\n\tint value;\n};\n\nstruct snd_timer;\n\nstruct snd_hrtimer {\n\tstruct snd_timer *timer;\n\tstruct hrtimer hrt;\n\tbool in_callback;\n};\n\nstruct snd_hwdep_dsp_status;\n\nstruct snd_hwdep_dsp_image;\n\nstruct snd_hwdep_ops {\n\tlong long int (*llseek)(struct snd_hwdep *, struct file *, long long int, int);\n\tlong int (*read)(struct snd_hwdep *, char *, long int, loff_t *);\n\tlong int (*write)(struct snd_hwdep *, const char *, long int, loff_t *);\n\tint (*open)(struct snd_hwdep *, struct file *);\n\tint (*release)(struct snd_hwdep *, struct file *);\n\t__poll_t (*poll)(struct snd_hwdep *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_hwdep *, struct file *, unsigned int, long unsigned int);\n\tint (*ioctl_compat)(struct snd_hwdep *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_hwdep *, struct file *, struct vm_area_struct *);\n\tint (*dsp_status)(struct snd_hwdep *, struct snd_hwdep_dsp_status *);\n\tint (*dsp_load)(struct snd_hwdep *, struct snd_hwdep_dsp_image *);\n};\n\nstruct snd_hwdep {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tchar id[32];\n\tchar name[80];\n\tint iface;\n\tstruct snd_hwdep_ops ops;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_hwdep *);\n\tstruct device *dev;\n\tstruct mutex open_mutex;\n\tint used;\n\tunsigned int dsp_loaded;\n\tunsigned int exclusive: 1;\n};\n\nstruct snd_hwdep_dsp_image {\n\tunsigned int index;\n\tunsigned char name[64];\n\tunsigned char *image;\n\tsize_t length;\n\tlong unsigned int driver_data;\n};\n\nstruct snd_hwdep_dsp_image32 {\n\tu32 index;\n\tunsigned char name[64];\n\tu32 image;\n\tu32 length;\n\tu32 driver_data;\n};\n\nstruct snd_hwdep_dsp_status {\n\tunsigned int version;\n\tunsigned char id[32];\n\tunsigned int num_dsps;\n\tunsigned int dsp_loaded;\n\tunsigned int chip_ready;\n\tunsigned char reserved[16];\n};\n\nstruct snd_hwdep_info {\n\tunsigned int device;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tint iface;\n\tunsigned char reserved[64];\n};\n\nstruct snd_info_buffer {\n\tchar *buffer;\n\tunsigned int curr;\n\tunsigned int size;\n\tunsigned int len;\n\tint stop;\n\tint error;\n};\n\nstruct snd_info_entry_text {\n\tvoid (*read)(struct snd_info_entry *, struct snd_info_buffer *);\n\tvoid (*write)(struct snd_info_entry *, struct snd_info_buffer *);\n};\n\nstruct snd_info_entry_ops;\n\nstruct snd_info_entry {\n\tconst char *name;\n\tumode_t mode;\n\tlong int size;\n\tshort unsigned int content;\n\tunion {\n\t\tstruct snd_info_entry_text text;\n\t\tconst struct snd_info_entry_ops *ops;\n\t} c;\n\tstruct snd_info_entry *parent;\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_info_entry *);\n\tstruct proc_dir_entry *p;\n\tstruct mutex access;\n\tstruct list_head children;\n\tstruct list_head list;\n};\n\nstruct snd_info_entry_ops {\n\tint (*open)(struct snd_info_entry *, short unsigned int, void **);\n\tint (*release)(struct snd_info_entry *, short unsigned int, void *);\n\tssize_t (*read)(struct snd_info_entry *, void *, struct file *, char *, size_t, loff_t);\n\tssize_t (*write)(struct snd_info_entry *, void *, struct file *, const char *, size_t, loff_t);\n\tloff_t (*llseek)(struct snd_info_entry *, void *, struct file *, loff_t, int);\n\t__poll_t (*poll)(struct snd_info_entry *, void *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_info_entry *, void *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_info_entry *, void *, struct inode *, struct file *, struct vm_area_struct *);\n};\n\nstruct snd_info_private_data {\n\tstruct snd_info_buffer *rbuffer;\n\tstruct snd_info_buffer *wbuffer;\n\tstruct snd_info_entry *entry;\n\tvoid *file_private_data;\n};\n\nstruct snd_interval {\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int openmin: 1;\n\tunsigned int openmax: 1;\n\tunsigned int integer: 1;\n\tunsigned int empty: 1;\n};\n\nstruct snd_jack {\n\tstruct list_head kctl_list;\n\tstruct snd_card *card;\n\tconst char *id;\n\tstruct input_dev *input_dev;\n\tstruct mutex input_dev_lock;\n\tint registered;\n\tint type;\n\tchar name[100];\n\tunsigned int key[6];\n\tint hw_status_cache;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_jack *);\n};\n\nstruct snd_jack_kctl {\n\tstruct snd_kcontrol *kctl;\n\tstruct list_head list;\n\tunsigned int mask_bits;\n\tstruct snd_jack *jack;\n\tbool sw_inject_enable;\n};\n\nstruct snd_kcontrol_new {\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tconst char *name;\n\tunsigned int index;\n\tunsigned int access;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n};\n\nstruct snd_kctl_event {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int mask;\n};\n\ntypedef int (*snd_kctl_ioctl_func_t)(struct snd_card *, struct snd_ctl_file *, unsigned int, long unsigned int);\n\nstruct snd_kctl_ioctl {\n\tstruct list_head list;\n\tsnd_kctl_ioctl_func_t fioctl;\n};\n\nstruct snd_malloc_ops {\n\tvoid * (*alloc)(struct snd_dma_buffer *, size_t);\n\tvoid (*free)(struct snd_dma_buffer *);\n\tdma_addr_t (*get_addr)(struct snd_dma_buffer *, size_t);\n\tstruct page * (*get_page)(struct snd_dma_buffer *, size_t);\n\tunsigned int (*get_chunk_size)(struct snd_dma_buffer *, unsigned int, unsigned int);\n\tint (*mmap)(struct snd_dma_buffer *, struct vm_area_struct *);\n\tvoid (*sync)(struct snd_dma_buffer *, enum snd_dma_sync_mode);\n};\n\nstruct snd_mask {\n\t__u32 bits[8];\n};\n\nstruct snd_minor {\n\tint type;\n\tint card;\n\tint device;\n\tconst struct file_operations *f_ops;\n\tvoid *private_data;\n\tstruct device *dev;\n\tstruct snd_card *card_ptr;\n};\n\nstruct snd_monitor_file {\n\tstruct file *file;\n\tconst struct file_operations *disconnected_f_op;\n\tstruct list_head shutdown_list;\n\tstruct list_head list;\n};\n\nstruct snd_pci_quirk {\n\tshort unsigned int subvendor;\n\tshort unsigned int subdevice;\n\tshort unsigned int subdevice_mask;\n\tint value;\n};\n\nstruct snd_pcm_str {\n\tint stream;\n\tstruct snd_pcm *pcm;\n\tunsigned int substream_count;\n\tunsigned int substream_opened;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_kcontrol *chmap_kctl;\n\tstruct device *dev;\n};\n\nstruct snd_pcm {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tunsigned int info_flags;\n\tshort unsigned int dev_class;\n\tshort unsigned int dev_subclass;\n\tchar id[64];\n\tchar name[80];\n\tstruct snd_pcm_str streams[2];\n\tstruct mutex open_mutex;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm *);\n\tbool internal;\n\tbool nonatomic;\n\tbool no_device_suspend;\n};\n\nstruct snd_pcm_audio_tstamp_config {\n\tu32 type_requested: 4;\n\tu32 report_delay: 1;\n};\n\nstruct snd_pcm_audio_tstamp_report {\n\tu32 valid: 1;\n\tu32 actual_type: 4;\n\tu32 accuracy_report: 1;\n\tu32 accuracy;\n};\n\nstruct snd_pcm_channel_info {\n\tunsigned int channel;\n\t__kernel_off_t offset;\n\tunsigned int first;\n\tunsigned int step;\n};\n\nstruct snd_pcm_channel_info32 {\n\tu32 channel;\n\tu32 offset;\n\tu32 first;\n\tu32 step;\n};\n\nstruct snd_pcm_chmap {\n\tstruct snd_pcm *pcm;\n\tint stream;\n\tstruct snd_kcontrol *kctl;\n\tconst struct snd_pcm_chmap_elem *chmap;\n\tunsigned int max_channels;\n\tunsigned int channel_mask;\n\tvoid *private_data;\n};\n\nstruct snd_pcm_chmap_elem {\n\tunsigned char channels;\n\tunsigned char map[15];\n};\n\nstruct snd_pcm_file {\n\tstruct snd_pcm_substream *substream;\n\tint no_compat_mmap;\n\tunsigned int user_pversion;\n};\n\nstruct snd_pcm_group {\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head substreams;\n\trefcount_t refs;\n};\n\nstruct snd_pcm_hardware {\n\tunsigned int info;\n\tu64 formats;\n\tu32 subformats;\n\tunsigned int rates;\n\tunsigned int rate_min;\n\tunsigned int rate_max;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\tsize_t buffer_bytes_max;\n\tsize_t period_bytes_min;\n\tsize_t period_bytes_max;\n\tunsigned int periods_min;\n\tunsigned int periods_max;\n\tsize_t fifo_size;\n};\n\nstruct snd_pcm_hw_constraint_list {\n\tconst unsigned int *list;\n\tunsigned int count;\n\tunsigned int mask;\n};\n\nstruct snd_pcm_hw_constraint_ranges {\n\tunsigned int count;\n\tconst struct snd_interval *ranges;\n\tunsigned int mask;\n};\n\nstruct snd_ratden;\n\nstruct snd_pcm_hw_constraint_ratdens {\n\tint nrats;\n\tconst struct snd_ratden *rats;\n};\n\nstruct snd_ratnum;\n\nstruct snd_pcm_hw_constraint_ratnums {\n\tint nrats;\n\tconst struct snd_ratnum *rats;\n};\n\nstruct snd_pcm_hw_rule;\n\nstruct snd_pcm_hw_constraints {\n\tstruct snd_mask masks[3];\n\tstruct snd_interval intervals[12];\n\tunsigned int rules_num;\n\tunsigned int rules_all;\n\tstruct snd_pcm_hw_rule *rules;\n};\n\nstruct snd_pcm_hw_params {\n\tunsigned int flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tunsigned int rmask;\n\tunsigned int cmask;\n\tunsigned int info;\n\tunsigned int msbits;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tsnd_pcm_uframes_t fifo_size;\n\tunsigned char sync[16];\n\tunsigned char reserved[48];\n};\n\nstruct snd_pcm_hw_params32 {\n\tu32 flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tu32 rmask;\n\tu32 cmask;\n\tu32 info;\n\tu32 msbits;\n\tu32 rate_num;\n\tu32 rate_den;\n\tu32 fifo_size;\n\tunsigned char reserved[64];\n};\n\ntypedef int (*snd_pcm_hw_rule_func_t)(struct snd_pcm_hw_params *, struct snd_pcm_hw_rule *);\n\nstruct snd_pcm_hw_rule {\n\tunsigned int cond;\n\tint var;\n\tint deps[5];\n\tsnd_pcm_hw_rule_func_t func;\n\tvoid *private;\n};\n\nstruct snd_pcm_info {\n\tunsigned int device;\n\tunsigned int subdevice;\n\tint stream;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tunsigned char subname[32];\n\tint dev_class;\n\tint dev_subclass;\n\tunsigned int subdevices_count;\n\tunsigned int subdevices_avail;\n\tunsigned char pad1[16];\n\tunsigned char reserved[64];\n};\n\nstruct snd_pcm_mmap_control {\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t appl_ptr;\n\t__pad_before_uframe __pad2;\n\t__pad_before_uframe __pad3;\n\tsnd_pcm_uframes_t avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct snd_pcm_mmap_control32 {\n\tu32 appl_ptr;\n\tu32 avail_min;\n};\n\nstruct snd_pcm_mmap_status {\n\tsnd_pcm_state_t state;\n\t__u32 pad1;\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t hw_ptr;\n\t__pad_after_uframe __pad2;\n\tstruct __kernel_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 pad3;\n\tstruct __kernel_timespec audio_tstamp;\n};\n\nstruct snd_pcm_mmap_status32 {\n\tsnd_pcm_state_t state;\n\ts32 pad1;\n\tu32 hw_ptr;\n\tstruct __snd_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\tstruct __snd_timespec audio_tstamp;\n};\n\nstruct snd_pcm_ops {\n\tint (*open)(struct snd_pcm_substream *);\n\tint (*close)(struct snd_pcm_substream *);\n\tint (*ioctl)(struct snd_pcm_substream *, unsigned int, void *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_pcm_substream *, int);\n\tint (*sync_stop)(struct snd_pcm_substream *);\n\tsnd_pcm_uframes_t (*pointer)(struct snd_pcm_substream *);\n\tint (*get_time_info)(struct snd_pcm_substream *, struct timespec64 *, struct timespec64 *, struct snd_pcm_audio_tstamp_config *, struct snd_pcm_audio_tstamp_report *);\n\tint (*fill_silence)(struct snd_pcm_substream *, int, long unsigned int, long unsigned int);\n\tint (*copy)(struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\tstruct page * (*page)(struct snd_pcm_substream *, long unsigned int);\n\tint (*mmap)(struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_pcm_substream *);\n};\n\nstruct snd_pcm_runtime {\n\tsnd_pcm_state_t state;\n\tsnd_pcm_state_t suspended_state;\n\tstruct snd_pcm_substream *trigger_master;\n\tstruct timespec64 trigger_tstamp;\n\tbool trigger_tstamp_latched;\n\tint overrange;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t hw_ptr_base;\n\tsnd_pcm_uframes_t hw_ptr_interrupt;\n\tlong unsigned int hw_ptr_jiffies;\n\tlong unsigned int hw_ptr_buffer_jiffies;\n\tsnd_pcm_sframes_t delay;\n\tu64 hw_ptr_wrap;\n\tsnd_pcm_access_t access;\n\tsnd_pcm_format_t format;\n\tsnd_pcm_subformat_t subformat;\n\tunsigned int rate;\n\tunsigned int channels;\n\tsnd_pcm_uframes_t period_size;\n\tunsigned int periods;\n\tsnd_pcm_uframes_t buffer_size;\n\tsnd_pcm_uframes_t min_align;\n\tsize_t byte_align;\n\tunsigned int frame_bits;\n\tunsigned int sample_bits;\n\tunsigned int info;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tunsigned int no_period_wakeup: 1;\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tsnd_pcm_uframes_t silence_start;\n\tsnd_pcm_uframes_t silence_filled;\n\tbool std_sync_id;\n\tstruct snd_pcm_mmap_status *status;\n\tstruct snd_pcm_mmap_control *control;\n\tsnd_pcm_uframes_t twake;\n\twait_queue_head_t sleep;\n\twait_queue_head_t tsleep;\n\tstruct snd_fasync *fasync;\n\tbool stop_operating;\n\tstruct mutex buffer_mutex;\n\tatomic_t buffer_accessing;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm_runtime *);\n\tstruct snd_pcm_hardware hw;\n\tstruct snd_pcm_hw_constraints hw_constraints;\n\tunsigned int timer_resolution;\n\tint tstamp_type;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n\tunsigned int buffer_changed: 1;\n\tstruct snd_pcm_audio_tstamp_config audio_tstamp_config;\n\tstruct snd_pcm_audio_tstamp_report audio_tstamp_report;\n\tstruct timespec64 driver_tstamp;\n};\n\nstruct snd_pcm_status32 {\n\tsnd_pcm_state_t state;\n\ts32 trigger_tstamp_sec;\n\ts32 trigger_tstamp_nsec;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts32 audio_tstamp_sec;\n\ts32 audio_tstamp_nsec;\n\ts32 driver_tstamp_sec;\n\ts32 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[36];\n};\n\nstruct snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tsnd_pcm_uframes_t appl_ptr;\n\tsnd_pcm_uframes_t hw_ptr;\n\tsnd_pcm_sframes_t delay;\n\tsnd_pcm_uframes_t avail;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t overrange;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\t__u32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nstruct snd_pcm_substream {\n\tstruct snd_pcm *pcm;\n\tstruct snd_pcm_str *pstr;\n\tvoid *private_data;\n\tint number;\n\tchar name[32];\n\tint stream;\n\tstruct pm_qos_request latency_pm_qos_req;\n\tsize_t buffer_bytes_max;\n\tstruct snd_dma_buffer dma_buffer;\n\tsize_t dma_max;\n\tconst struct snd_pcm_ops *ops;\n\tstruct snd_pcm_runtime *runtime;\n\tstruct snd_timer *timer;\n\tunsigned int timer_running: 1;\n\tlong int wait_time;\n\tstruct snd_pcm_substream *next;\n\tstruct list_head link_list;\n\tstruct snd_pcm_group self_group;\n\tstruct snd_pcm_group *group;\n\tint ref_count;\n\tatomic_t mmap_count;\n\tunsigned int f_flags;\n\tvoid (*pcm_release)(struct snd_pcm_substream *);\n\tstruct pid *pid;\n\tstruct snd_info_entry *proc_root;\n\tunsigned int hw_opened: 1;\n\tunsigned int managed_buffer_alloc: 1;\n};\n\nstruct snd_pcm_sw_params {\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tunsigned int sleep_min;\n\tsnd_pcm_uframes_t avail_min;\n\tsnd_pcm_uframes_t xfer_align;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tunsigned int proto;\n\tunsigned int tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_sw_params32 {\n\ts32 tstamp_mode;\n\tu32 period_step;\n\tu32 sleep_min;\n\tu32 avail_min;\n\tu32 xfer_align;\n\tu32 start_threshold;\n\tu32 stop_threshold;\n\tu32 silence_threshold;\n\tu32 silence_size;\n\tu32 boundary;\n\tu32 proto;\n\tu32 tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_sync_ptr {\n\t__u32 flags;\n\t__u32 pad1;\n\tunion {\n\t\tstruct snd_pcm_mmap_status status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_pcm_sync_ptr32 {\n\tu32 flags;\n\tunion {\n\t\tstruct snd_pcm_mmap_status32 status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control32 control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_ratden {\n\tunsigned int num_min;\n\tunsigned int num_max;\n\tunsigned int num_step;\n\tunsigned int den;\n};\n\nstruct snd_ratnum {\n\tunsigned int num;\n\tunsigned int den_min;\n\tunsigned int den_max;\n\tunsigned int den_step;\n};\n\nstruct snd_seq_fifo;\n\nstruct snd_seq_user_client {\n\tstruct file *file;\n\tstruct pid *owner;\n\tstruct snd_seq_fifo *fifo;\n\tint fifo_pool_size;\n};\n\nstruct snd_seq_kernel_client {\n\tstruct snd_card *card;\n};\n\nstruct snd_seq_pool;\n\nstruct snd_seq_client {\n\tsnd_seq_client_type_t type;\n\tunsigned int accept_input: 1;\n\tunsigned int accept_output: 1;\n\tunsigned int midi_version;\n\tunsigned int user_pversion;\n\tchar name[64];\n\tint number;\n\tunsigned int filter;\n\tlong unsigned int event_filter[4];\n\tshort unsigned int group_filter;\n\tsnd_use_lock_t use_lock;\n\tint event_lost;\n\tint num_ports;\n\tstruct list_head ports_list_head;\n\trwlock_t ports_lock;\n\tstruct mutex ports_mutex;\n\tstruct mutex ioctl_mutex;\n\tint convert32;\n\tint ump_endpoint_port;\n\tstruct snd_seq_pool *pool;\n\tunion {\n\t\tstruct snd_seq_user_client user;\n\t\tstruct snd_seq_kernel_client kernel;\n\t} data;\n\tvoid **ump_info;\n};\n\nstruct snd_seq_client_info {\n\tint client;\n\tsnd_seq_client_type_t type;\n\tchar name[64];\n\tunsigned int filter;\n\tunsigned char multicast_filter[8];\n\tunsigned char event_filter[32];\n\tint num_ports;\n\tint event_lost;\n\tint card;\n\tint pid;\n\tunsigned int midi_version;\n\tunsigned int group_filter;\n\tchar reserved[48];\n};\n\nstruct snd_seq_client_pool {\n\tint client;\n\tint output_pool;\n\tint input_pool;\n\tint output_room;\n\tint output_free;\n\tint input_free;\n\tchar reserved[64];\n};\n\nstruct snd_seq_port_subscribe;\n\nstruct snd_seq_port_subs_info {\n\tstruct list_head list_head;\n\tunsigned int count;\n\tunsigned int exclusive: 1;\n\tstruct rw_semaphore list_mutex;\n\trwlock_t list_lock;\n\tint (*open)(void *, struct snd_seq_port_subscribe *);\n\tint (*close)(void *, struct snd_seq_port_subscribe *);\n};\n\nstruct snd_seq_client_port {\n\tstruct snd_seq_addr addr;\n\tstruct module *owner;\n\tchar name[64];\n\tstruct list_head list;\n\tsnd_use_lock_t use_lock;\n\tstruct snd_seq_port_subs_info c_src;\n\tstruct snd_seq_port_subs_info c_dest;\n\tint (*event_input)(struct snd_seq_event *, int, void *, int, int);\n\tvoid (*private_free)(void *);\n\tvoid *private_data;\n\tunsigned int closing: 1;\n\tunsigned int timestamping: 1;\n\tunsigned int time_real: 1;\n\tint time_queue;\n\tunsigned int capability;\n\tunsigned int type;\n\tint midi_channels;\n\tint midi_voices;\n\tint synth_voices;\n\tunsigned char direction;\n\tunsigned char ump_group;\n\tbool is_midi1;\n};\n\nstruct snd_seq_device {\n\tstruct snd_card *card;\n\tint device;\n\tconst char *id;\n\tchar name[80];\n\tint argsize;\n\tvoid *driver_data;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_seq_device *);\n\tstruct device dev;\n};\n\nstruct snd_seq_driver {\n\tint (*probe)(struct snd_seq_device *);\n\tvoid (*remove)(struct snd_seq_device *);\n\tstruct device_driver driver;\n\tchar *id;\n\tint argsize;\n};\n\nstruct snd_seq_dummy_port {\n\tint client;\n\tint port;\n\tint duplex;\n\tint connect;\n};\n\nstruct snd_seq_event_cell {\n\tunion {\n\t\tstruct snd_seq_event event;\n\t\tunion __snd_seq_event ump;\n\t};\n\tstruct snd_seq_pool *pool;\n\tstruct snd_seq_event_cell *next;\n};\n\ntypedef struct snd_seq_fifo *class_snd_seq_fifo_t;\n\nstruct snd_seq_fifo {\n\tstruct snd_seq_pool *pool;\n\tstruct snd_seq_event_cell *head;\n\tstruct snd_seq_event_cell *tail;\n\tint cells;\n\tspinlock_t lock;\n\tsnd_use_lock_t use_lock;\n\twait_queue_head_t input_sleep;\n\tatomic_t overflow;\n};\n\nstruct snd_seq_pool {\n\tstruct snd_seq_event_cell *ptr;\n\tstruct snd_seq_event_cell *free;\n\tint total_elements;\n\tatomic_t counter;\n\tint size;\n\tint room;\n\tint closing;\n\tint max_used;\n\tint event_alloc_nopool;\n\tint event_alloc_failures;\n\tint event_alloc_success;\n\twait_queue_head_t output_sleep;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_port_callback {\n\tstruct module *owner;\n\tvoid *private_data;\n\tint (*subscribe)(void *, struct snd_seq_port_subscribe *);\n\tint (*unsubscribe)(void *, struct snd_seq_port_subscribe *);\n\tint (*use)(void *, struct snd_seq_port_subscribe *);\n\tint (*unuse)(void *, struct snd_seq_port_subscribe *);\n\tint (*event_input)(struct snd_seq_event *, int, void *, int, int);\n\tvoid (*private_free)(void *);\n};\n\nstruct snd_seq_port_info {\n\tstruct snd_seq_addr addr;\n\tchar name[64];\n\tunsigned int capability;\n\tunsigned int type;\n\tint midi_channels;\n\tint midi_voices;\n\tint synth_voices;\n\tint read_use;\n\tint write_use;\n\tvoid *kernel;\n\tunsigned int flags;\n\tunsigned char time_queue;\n\tunsigned char direction;\n\tunsigned char ump_group;\n\tchar reserved[57];\n};\n\nstruct snd_seq_port_info32 {\n\tstruct snd_seq_addr addr;\n\tchar name[64];\n\tu32 capability;\n\tu32 type;\n\ts32 midi_channels;\n\ts32 midi_voices;\n\ts32 synth_voices;\n\ts32 read_use;\n\ts32 write_use;\n\tu32 kernel;\n\tu32 flags;\n\tunsigned char time_queue;\n\tchar reserved[59];\n};\n\nstruct snd_seq_port_subscribe {\n\tstruct snd_seq_addr sender;\n\tstruct snd_seq_addr dest;\n\tunsigned int voices;\n\tunsigned int flags;\n\tunsigned char queue;\n\tunsigned char pad[3];\n\tchar reserved[64];\n};\n\nstruct snd_seq_prioq {\n\tstruct snd_seq_event_cell *head;\n\tstruct snd_seq_event_cell *tail;\n\tint cells;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_query_subs {\n\tstruct snd_seq_addr root;\n\tint type;\n\tint index;\n\tint num_subs;\n\tstruct snd_seq_addr addr;\n\tunsigned char queue;\n\tunsigned int flags;\n\tchar reserved[64];\n};\n\nstruct snd_seq_timer;\n\nstruct snd_seq_queue {\n\tint queue;\n\tchar name[64];\n\tstruct snd_seq_prioq *tickq;\n\tstruct snd_seq_prioq *timeq;\n\tstruct snd_seq_timer *timer;\n\tint owner;\n\tbool locked;\n\tbool klocked;\n\tbool check_again;\n\tbool check_blocked;\n\tunsigned int flags;\n\tunsigned int info_flags;\n\tspinlock_t owner_lock;\n\tspinlock_t check_lock;\n\tlong unsigned int clients_bitmap[3];\n\tunsigned int clients;\n\tstruct mutex timer_mutex;\n\tsnd_use_lock_t use_lock;\n};\n\nstruct snd_seq_queue_client {\n\tint queue;\n\tint client;\n\tint used;\n\tchar reserved[64];\n};\n\nstruct snd_seq_queue_info {\n\tint queue;\n\tint owner;\n\tunsigned int locked: 1;\n\tchar name[64];\n\tunsigned int flags;\n\tchar reserved[60];\n};\n\nstruct snd_seq_queue_status {\n\tint queue;\n\tint events;\n\tsnd_seq_tick_time_t tick;\n\tstruct snd_seq_real_time time;\n\tint running;\n\tint flags;\n\tchar reserved[64];\n};\n\nstruct snd_seq_queue_tempo {\n\tint queue;\n\tunsigned int tempo;\n\tint ppq;\n\tunsigned int skew_value;\n\tunsigned int skew_base;\n\tshort unsigned int tempo_base;\n\tchar reserved[22];\n};\n\nstruct snd_timer_id {\n\tint dev_class;\n\tint dev_sclass;\n\tint card;\n\tint device;\n\tint subdevice;\n};\n\nstruct snd_seq_queue_timer {\n\tint queue;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct snd_timer_id id;\n\t\t\tunsigned int resolution;\n\t\t} alsa;\n\t} u;\n\tchar reserved[64];\n};\n\ntypedef struct snd_seq_real_time snd_seq_real_time_t;\n\nstruct snd_seq_remove_events {\n\tunsigned int remove_mode;\n\tunion snd_seq_timestamp time;\n\tunsigned char queue;\n\tstruct snd_seq_addr dest;\n\tunsigned char channel;\n\tint type;\n\tchar tag;\n\tint reserved[10];\n};\n\nstruct snd_seq_running_info {\n\tunsigned char client;\n\tunsigned char big_endian;\n\tunsigned char cpu_mode;\n\tunsigned char pad;\n\tunsigned char reserved[12];\n};\n\nstruct snd_seq_subscribers {\n\tstruct snd_seq_port_subscribe info;\n\tstruct list_head src_list;\n\tstruct list_head dest_list;\n\tatomic_t ref_count;\n};\n\nstruct snd_seq_system_info {\n\tint queues;\n\tint clients;\n\tint ports;\n\tint channels;\n\tint cur_clients;\n\tint cur_queues;\n\tchar reserved[24];\n};\n\nstruct snd_seq_timer_tick {\n\tsnd_seq_tick_time_t cur_tick;\n\tlong unsigned int resolution;\n\tlong unsigned int fraction;\n};\n\nstruct snd_timer_instance;\n\nstruct snd_seq_timer {\n\tunsigned int running: 1;\n\tunsigned int initialized: 1;\n\tunsigned int tempo;\n\tint ppq;\n\tsnd_seq_real_time_t cur_time;\n\tstruct snd_seq_timer_tick tick;\n\tint tick_updated;\n\tint type;\n\tstruct snd_timer_id alsa_id;\n\tstruct snd_timer_instance *timeri;\n\tunsigned int ticks;\n\tlong unsigned int preferred_resolution;\n\tunsigned int skew;\n\tunsigned int skew_base;\n\tunsigned int tempo_base;\n\tstruct timespec64 last_update;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_ump_event {\n\tsnd_seq_event_type_t type;\n\tunsigned char flags;\n\tchar tag;\n\tunsigned char queue;\n\tunion snd_seq_timestamp time;\n\tstruct snd_seq_addr source;\n\tstruct snd_seq_addr dest;\n\tunion {\n\t\tunion snd_seq_event_data data;\n\t\tunsigned int ump[4];\n\t};\n};\n\nstruct snd_seq_usage {\n\tint cur;\n\tint peak;\n};\n\nstruct snd_soc_acpi_codecs {\n\tint num_codecs;\n\tu8 codecs[48];\n};\n\nstruct snd_timer_hardware {\n\tunsigned int flags;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tlong unsigned int ticks;\n\tint (*open)(struct snd_timer *);\n\tint (*close)(struct snd_timer *);\n\tlong unsigned int (*c_resolution)(struct snd_timer *);\n\tint (*start)(struct snd_timer *);\n\tint (*stop)(struct snd_timer *);\n\tint (*set_period)(struct snd_timer *, long unsigned int, long unsigned int);\n\tint (*precise_resolution)(struct snd_timer *, long unsigned int *, long unsigned int *);\n};\n\nstruct snd_timer {\n\tint tmr_class;\n\tstruct snd_card *card;\n\tstruct module *module;\n\tint tmr_device;\n\tint tmr_subdevice;\n\tchar id[64];\n\tchar name[80];\n\tunsigned int flags;\n\tint running;\n\tlong unsigned int sticks;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer *);\n\tstruct snd_timer_hardware hw;\n\tspinlock_t lock;\n\tstruct list_head device_list;\n\tstruct list_head open_list_head;\n\tstruct list_head active_list_head;\n\tstruct list_head ack_list_head;\n\tstruct list_head sack_list_head;\n\tstruct work_struct task_work;\n\tint max_instances;\n\tint num_instances;\n};\n\nstruct snd_timer_ginfo {\n\tstruct snd_timer_id tid;\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tunsigned int clients;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gparams {\n\tstruct snd_timer_id tid;\n\tlong unsigned int period_num;\n\tlong unsigned int period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gparams32 {\n\tstruct snd_timer_id tid;\n\tu32 period_num;\n\tu32 period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gstatus {\n\tstruct snd_timer_id tid;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_num;\n\tlong unsigned int resolution_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_info {\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_info32 {\n\tu32 flags;\n\ts32 card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tu32 reserved0;\n\tu32 resolution;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_instance {\n\tstruct snd_timer *timer;\n\tchar *owner;\n\tunsigned int flags;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer_instance *);\n\tvoid (*callback)(struct snd_timer_instance *, long unsigned int, long unsigned int);\n\tvoid (*ccallback)(struct snd_timer_instance *, int, struct timespec64 *, long unsigned int);\n\tvoid (*disconnect)(struct snd_timer_instance *);\n\tvoid *callback_data;\n\tlong unsigned int ticks;\n\tlong unsigned int cticks;\n\tlong unsigned int pticks;\n\tlong unsigned int resolution;\n\tlong unsigned int lost;\n\tint slave_class;\n\tunsigned int slave_id;\n\tstruct list_head open_list;\n\tstruct list_head active_list;\n\tstruct list_head ack_list;\n\tstruct list_head slave_list_head;\n\tstruct list_head slave_active_head;\n\tstruct snd_timer_instance *master;\n};\n\nstruct snd_timer_params {\n\tunsigned int flags;\n\tunsigned int ticks;\n\tunsigned int queue_size;\n\tunsigned int reserved0;\n\tunsigned int filter;\n\tunsigned char reserved[60];\n};\n\nstruct snd_timer_read {\n\tunsigned int resolution;\n\tunsigned int ticks;\n};\n\nstruct snd_timer_select {\n\tstruct snd_timer_id id;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_status32 {\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_status64 {\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_system_private {\n\tstruct timer_list tlist;\n\tstruct snd_timer *snd_timer;\n\tlong unsigned int last_expires;\n\tlong unsigned int last_jiffies;\n\tlong unsigned int correction;\n};\n\nstruct snd_timer_tread32 {\n\tint event;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int val;\n};\n\nstruct snd_timer_tread64 {\n\tint event;\n\tu8 pad1[4];\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int val;\n\tu8 pad2[4];\n};\n\nstruct snd_timer_uinfo {\n\t__u64 resolution;\n\tint fd;\n\tunsigned int id;\n\tunsigned char reserved[16];\n};\n\nstruct snd_timer_user {\n\tstruct snd_timer_instance *timeri;\n\tint tread;\n\tlong unsigned int ticks;\n\tlong unsigned int overrun;\n\tint qhead;\n\tint qtail;\n\tint qused;\n\tint queue_size;\n\tbool disconnected;\n\tstruct snd_timer_read *queue;\n\tstruct snd_timer_tread64 *tqueue;\n\tspinlock_t qlock;\n\tlong unsigned int last_resolution;\n\tunsigned int filter;\n\tstruct timespec64 tstamp;\n\twait_queue_head_t qchange_sleep;\n\tstruct snd_fasync *fasync;\n\tstruct mutex ioctl_lock;\n};\n\nstruct snd_xferi {\n\tsnd_pcm_sframes_t result;\n\tvoid *buf;\n\tsnd_pcm_uframes_t frames;\n};\n\nstruct snd_xferi32 {\n\ts32 result;\n\tu32 buf;\n\tu32 frames;\n};\n\nstruct snd_xfern {\n\tsnd_pcm_sframes_t result;\n\tvoid **bufs;\n\tsnd_pcm_uframes_t frames;\n};\n\nstruct snd_xfern32 {\n\ts32 result;\n\tu32 bufs;\n\tu32 frames;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sock_xprt {\n\tstruct rpc_xprt xprt;\n\tstruct socket *sock;\n\tstruct sock *inet;\n\tstruct file *file;\n\tstruct {\n\t\tstruct {\n\t\t\t__be32 fraghdr;\n\t\t\t__be32 xid;\n\t\t\t__be32 calldir;\n\t\t};\n\t\tu32 offset;\n\t\tu32 len;\n\t\tlong unsigned int copied;\n\t} recv;\n\tstruct {\n\t\tu32 offset;\n\t} xmit;\n\tlong unsigned int sock_state;\n\tstruct delayed_work connect_worker;\n\tstruct work_struct error_worker;\n\tstruct work_struct recv_worker;\n\tstruct mutex recv_mutex;\n\tstruct completion handshake_done;\n\tstruct __kernel_sockaddr_storage srcaddr;\n\tshort unsigned int srcport;\n\tint xprt_err;\n\tstruct rpc_clnt *clnt;\n\tsize_t rcvsize;\n\tsize_t sndsize;\n\tstruct rpc_timeout tcp_timeout;\n\tvoid (*old_data_ready)(struct sock *);\n\tvoid (*old_state_change)(struct sock *);\n\tvoid (*old_write_space)(struct sock *);\n\tvoid (*old_error_report)(struct sock *);\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 64;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct socket_data {\n\tstruct resource_map mem_db;\n\tstruct resource_map mem_db_valid;\n\tstruct resource_map io_db;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int input_queue_head;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t defer_csd;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct sony_sc {\n\tspinlock_t lock;\n\tstruct list_head list_node;\n\tstruct hid_device *hdev;\n\tstruct input_dev *input_dev;\n\tstruct input_dev *touchpad;\n\tstruct input_dev *sensor_dev;\n\tstruct led_classdev *leds[4];\n\tlong unsigned int quirks;\n\tstruct work_struct state_worker;\n\tvoid (*send_output_report)(struct sony_sc *);\n\tstruct power_supply *battery;\n\tstruct power_supply_desc battery_desc;\n\tint device_id;\n\tu8 *output_report_dmabuf;\n\tu8 mac_address[6];\n\tu8 state_worker_initialized;\n\tu8 defer_initialization;\n\tu8 battery_capacity;\n\tint battery_status;\n\tu8 led_state[4];\n\tu8 led_delay_on[4];\n\tu8 led_delay_off[4];\n\tu8 led_count;\n\tstruct urb *ghl_urb;\n\tstruct timer_list ghl_poke_timer;\n};\n\nstruct sp_node {\n\tstruct rb_node nd;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct mempolicy *policy;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct space_resv_32 {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n} __attribute__((packed));\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n};\n\nstruct spi_function_template {\n\tvoid (*get_period)(struct scsi_target *);\n\tvoid (*set_period)(struct scsi_target *, int);\n\tvoid (*get_offset)(struct scsi_target *);\n\tvoid (*set_offset)(struct scsi_target *, int);\n\tvoid (*get_width)(struct scsi_target *);\n\tvoid (*set_width)(struct scsi_target *, int);\n\tvoid (*get_iu)(struct scsi_target *);\n\tvoid (*set_iu)(struct scsi_target *, int);\n\tvoid (*get_dt)(struct scsi_target *);\n\tvoid (*set_dt)(struct scsi_target *, int);\n\tvoid (*get_qas)(struct scsi_target *);\n\tvoid (*set_qas)(struct scsi_target *, int);\n\tvoid (*get_wr_flow)(struct scsi_target *);\n\tvoid (*set_wr_flow)(struct scsi_target *, int);\n\tvoid (*get_rd_strm)(struct scsi_target *);\n\tvoid (*set_rd_strm)(struct scsi_target *, int);\n\tvoid (*get_rti)(struct scsi_target *);\n\tvoid (*set_rti)(struct scsi_target *, int);\n\tvoid (*get_pcomp_en)(struct scsi_target *);\n\tvoid (*set_pcomp_en)(struct scsi_target *, int);\n\tvoid (*get_hold_mcs)(struct scsi_target *);\n\tvoid (*set_hold_mcs)(struct scsi_target *, int);\n\tvoid (*get_signalling)(struct Scsi_Host *);\n\tvoid (*set_signalling)(struct Scsi_Host *, enum spi_signal_type);\n\tint (*deny_binding)(struct scsi_target *);\n\tlong unsigned int show_period: 1;\n\tlong unsigned int show_offset: 1;\n\tlong unsigned int show_width: 1;\n\tlong unsigned int show_iu: 1;\n\tlong unsigned int show_dt: 1;\n\tlong unsigned int show_qas: 1;\n\tlong unsigned int show_wr_flow: 1;\n\tlong unsigned int show_rd_strm: 1;\n\tlong unsigned int show_rti: 1;\n\tlong unsigned int show_pcomp_en: 1;\n\tlong unsigned int show_hold_mcs: 1;\n};\n\nstruct spi_host_attrs {\n\tenum spi_signal_type signalling;\n};\n\nstruct spi_internal {\n\tstruct scsi_transport_template t;\n\tstruct spi_function_template *f;\n};\n\nstruct spi_transport_attrs {\n\tint period;\n\tint min_period;\n\tint offset;\n\tint max_offset;\n\tunsigned int width: 1;\n\tunsigned int max_width: 1;\n\tunsigned int iu: 1;\n\tunsigned int max_iu: 1;\n\tunsigned int dt: 1;\n\tunsigned int qas: 1;\n\tunsigned int max_qas: 1;\n\tunsigned int wr_flow: 1;\n\tunsigned int rd_strm: 1;\n\tunsigned int rti: 1;\n\tunsigned int pcomp_en: 1;\n\tunsigned int hold_mcs: 1;\n\tunsigned int initial_dv: 1;\n\tlong unsigned int flags;\n\tunsigned int support_sync: 1;\n\tunsigned int support_wide: 1;\n\tunsigned int support_dt: 1;\n\tunsigned int support_dt_only;\n\tunsigned int support_ius;\n\tunsigned int support_qas;\n\tunsigned int dv_pending: 1;\n\tunsigned int dv_in_progress: 1;\n\tstruct mutex dv_mutex;\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct sr6_tlv {\n\t__u8 type;\n\t__u8 len;\n\t__u8 data[0];\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_node;\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[3];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct ssb_state {\n\tstruct ssb_state *shared_state;\n\traw_spinlock_t lock;\n\tunsigned int disable_state;\n\tlong unsigned int local_state;\n};\n\nstruct tid_ampdu_rx;\n\nstruct tid_ampdu_tx;\n\nstruct sta_ampdu_mlme {\n\tstruct tid_ampdu_rx *tid_rx[16];\n\tu8 tid_rx_token[16];\n\tlong unsigned int tid_rx_timer_expired[1];\n\tlong unsigned int tid_rx_stop_requested[1];\n\tlong unsigned int tid_rx_manage_offl[1];\n\tlong unsigned int agg_session_valid[1];\n\tlong unsigned int unexpected_agg[1];\n\tstruct wiphy_work work;\n\tstruct tid_ampdu_tx *tid_tx[16];\n\tstruct tid_ampdu_tx *tid_start_tx[16];\n\tlong unsigned int last_addba_req_time[16];\n\tu8 addba_req_num[16];\n\tu8 dialog_token_allocator;\n};\n\nstruct sta_bss_param_ch_cnt_data {\n\tstruct ieee80211_sub_if_data *sdata;\n\tu8 reporting_link_id;\n\tu8 mld_id;\n};\n\nstruct sta_csa_rnr_iter_data {\n\tstruct ieee80211_link_data *link;\n\tstruct ieee80211_channel *chan;\n\tu8 mld_id;\n};\n\nstruct sta_info {\n\tstruct list_head list;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct rhlist_head hash_node;\n\tu8 addr[6];\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct ieee80211_key *ptk[4];\n\tu8 ptk_idx;\n\tstruct rate_control_ref *rate_ctrl;\n\tvoid *rate_ctrl_priv;\n\tspinlock_t rate_ctrl_lock;\n\tspinlock_t lock;\n\tstruct ieee80211_fast_tx *fast_tx;\n\tstruct ieee80211_fast_rx *fast_rx;\n\tstruct work_struct drv_deliver_wk;\n\tu16 listen_interval;\n\tbool dead;\n\tbool removed;\n\tbool uploaded;\n\tenum ieee80211_sta_state sta_state;\n\tlong unsigned int _flags;\n\tspinlock_t ps_lock;\n\tstruct sk_buff_head ps_tx_buf[4];\n\tstruct sk_buff_head tx_filtered[4];\n\tlong unsigned int driver_buffered_tids;\n\tlong unsigned int txq_buffered_tids;\n\tu64 assoc_at;\n\tlong int last_connected;\n\t__le16 last_seq_ctrl[17];\n\tu16 tid_seq[16];\n\tstruct airtime_info airtime[4];\n\tu16 airtime_weight;\n\tstruct sta_ampdu_mlme ampdu_mlme;\n\tu8 reserved_tid;\n\ts8 amsdu_mesh_control;\n\tstruct cfg80211_chan_def tdls_chandef;\n\tstruct ieee80211_fragment_cache frags;\n\tstruct ieee80211_sta_aggregates cur;\n\tstruct link_sta_info deflink;\n\tstruct link_sta_info *link[15];\n\tstruct ieee80211_sta_removed_link_stats rem_link_stats;\n\tstruct ieee80211_sta sta;\n};\n\nstruct sta_link_alloc {\n\tstruct link_sta_info info;\n\tstruct ieee80211_link_sta sta;\n\tstruct callback_head callback_head;\n};\n\nstruct sta_opmode_info {\n\tu32 changed;\n\tenum nl80211_smps_mode smps_mode;\n\tenum nl80211_chan_width bw;\n\tu8 rx_nss;\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[0];\n};\n\nstruct stack_frame {\n\tstruct stack_frame *next_frame;\n\tlong unsigned int return_address;\n};\n\nstruct stack_frame_ia32 {\n\tu32 next_frame;\n\tu32 return_address;\n};\n\nstruct stack_frame_user {\n\tconst void *next_fp;\n\tlong unsigned int ret_addr;\n};\n\nstruct stack_info {\n\tenum stack_type type;\n\tlong unsigned int *begin;\n\tlong unsigned int *end;\n\tlong unsigned int *next_sp;\n};\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tu64 data[0];\n};\n\nstruct stack_record {\n\tstruct list_head hash_list;\n\tu32 hash;\n\tu32 size;\n\tunion handle_parts handle;\n\trefcount_t count;\n\tunion {\n\t\tlong unsigned int entries[64];\n\t\tstruct {\n\t\t\tstruct list_head free_list;\n\t\t\tlong unsigned int rcu_state;\n\t\t};\n\t};\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\nstruct staging_state {\n\tvoid *mmio_base;\n\tunsigned int ucode_len;\n\tunsigned int chunk_size;\n\tunsigned int bytes_sent;\n\tunsigned int offset;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\t__kernel_ulong_t st_dev;\n\t__kernel_ulong_t st_ino;\n\t__kernel_ulong_t st_nlink;\n\tunsigned int st_mode;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tunsigned int __pad0;\n\t__kernel_ulong_t st_rdev;\n\t__kernel_long_t st_size;\n\t__kernel_long_t st_blksize;\n\t__kernel_long_t st_blocks;\n\t__kernel_ulong_t st_atime;\n\t__kernel_ulong_t st_atime_nsec;\n\t__kernel_ulong_t st_mtime;\n\t__kernel_ulong_t st_mtime_nsec;\n\t__kernel_ulong_t st_ctime;\n\t__kernel_ulong_t st_ctime_nsec;\n\t__kernel_long_t __unused[3];\n};\n\nstruct stat64 {\n\tlong long unsigned int st_dev;\n\tunsigned char __pad0[4];\n\tunsigned int __st_ino;\n\tunsigned int st_mode;\n\tunsigned int st_nlink;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tlong long unsigned int st_rdev;\n\tunsigned char __pad3[4];\n\tlong long int st_size;\n\tunsigned int st_blksize;\n\tlong long int st_blocks;\n\tunsigned int st_atime;\n\tunsigned int st_atime_nsec;\n\tunsigned int st_mtime;\n\tunsigned int st_mtime_nsec;\n\tunsigned int st_ctime;\n\tunsigned int st_ctime_nsec;\n\tlong long unsigned int st_ino;\n} __attribute__((packed));\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct tracer_stat;\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct statfs {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__kernel_long_t f_blocks;\n\t__kernel_long_t f_bfree;\n\t__kernel_long_t f_bavail;\n\t__kernel_long_t f_files;\n\t__kernel_long_t f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct statfs64 {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct static_call_mod;\n\nstruct static_call_key {\n\tvoid *func;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct static_call_mod *mods;\n\t\tstruct static_call_site *sites;\n\t};\n};\n\nstruct static_call_mod {\n\tstruct static_call_mod *next;\n\tstruct module *mod;\n\tstruct static_call_site *sites;\n};\n\nstruct static_call_site {\n\ts32 addr;\n\ts32 key;\n};\n\nstruct static_call_tramp_key {\n\ts32 tramp;\n\ts32 key;\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_tree_desc_s {\n\tconst ct_data *static_tree;\n\tconst int *extra_bits;\n\tint extra_base;\n\tint elems;\n\tint max_length;\n};\n\nstruct station_del_parameters {\n\tconst u8 *mac;\n\tu8 subtype;\n\tu16 reason_code;\n\tint link_id;\n};\n\nstruct station_info {\n\tu64 filled;\n\tu32 connected_time;\n\tu32 inactive_time;\n\tu64 assoc_at;\n\tu64 rx_bytes;\n\tu64 tx_bytes;\n\ts8 signal;\n\ts8 signal_avg;\n\tu8 chains;\n\ts8 chain_signal[4];\n\ts8 chain_signal_avg[4];\n\tstruct rate_info txrate;\n\tstruct rate_info rxrate;\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tstruct sta_bss_parameters bss_param;\n\tstruct nl80211_sta_flag_update sta_flags;\n\tint generation;\n\tu32 beacon_loss_count;\n\tconst u8 *assoc_req_ies;\n\tsize_t assoc_req_ies_len;\n\ts64 t_offset;\n\tu16 llid;\n\tu16 plid;\n\tu8 plink_state;\n\tu8 connected_to_gate;\n\tu8 connected_to_as;\n\tu32 airtime_link_metric;\n\tenum nl80211_mesh_power_mode local_pm;\n\tenum nl80211_mesh_power_mode peer_pm;\n\tenum nl80211_mesh_power_mode nonpeer_pm;\n\tu32 expected_throughput;\n\tu16 airtime_weight;\n\ts8 ack_signal;\n\ts8 avg_ack_signal;\n\tstruct cfg80211_tid_stats *pertid;\n\tu64 tx_duration;\n\tu64 rx_duration;\n\tu64 rx_beacon;\n\tu8 rx_beacon_signal_avg;\n\tu32 rx_mpdu_count;\n\tu32 fcs_err_count;\n\tbool mlo_params_valid;\n\tu8 assoc_link_id;\n\tu8 mld_addr[6];\n\tconst u8 *assoc_resp_ies;\n\tsize_t assoc_resp_ies_len;\n\tu16 valid_links;\n\tstruct link_station_info *links[15];\n};\n\nstruct station_parameters {\n\tstruct net_device *vlan;\n\tu32 sta_flags_mask;\n\tu32 sta_flags_set;\n\tu32 sta_modify_mask;\n\tint listen_interval;\n\tu16 aid;\n\tu16 vlan_id;\n\tu16 peer_aid;\n\tu8 plink_action;\n\tu8 plink_state;\n\tu8 uapsd_queues;\n\tu8 max_sp;\n\tenum nl80211_mesh_power_mode local_pm;\n\tu16 capability;\n\tconst u8 *ext_capab;\n\tu8 ext_capab_len;\n\tconst u8 *supported_channels;\n\tu8 supported_channels_len;\n\tconst u8 *supported_oper_classes;\n\tu8 supported_oper_classes_len;\n\tint support_p2p_ps;\n\tu16 airtime_weight;\n\tbool eml_cap_present;\n\tu16 eml_cap;\n\tstruct link_station_parameters link_sta_params;\n\tbool epp_peer;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct stepping_info {\n\tchar stepping;\n\tchar substepping;\n};\n\nstruct stereo_mandatory_mode {\n\tint width;\n\tint height;\n\tint vrefresh;\n\tunsigned int flags;\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct stripe {\n\tstruct dm_dev *dev;\n\tsector_t physical_start;\n\tatomic_t error_count;\n};\n\nstruct stripe_c {\n\tuint32_t stripes;\n\tint stripes_shift;\n\tsector_t stripe_width;\n\tuint32_t chunk_size;\n\tint chunk_size_shift;\n\tstruct dm_target *ti;\n\tstruct work_struct trigger_event;\n\tstruct stripe stripe[0];\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct subplatform_desc {\n\tstruct intel_display_platforms platforms;\n\tconst char *name;\n\tconst u16 *pciidlist;\n\tstruct stepping_desc step_info;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\nstruct subsys_tbl_ent {\n\tu16 subsys_vendor;\n\tu16 subsys_devid;\n\tu32 phy_id;\n};\n\nstruct sugov_policy;\n\nstruct sugov_cpu {\n\tstruct update_util_data update_util;\n\tstruct sugov_policy *sg_policy;\n\tunsigned int cpu;\n\tbool iowait_boost_pending;\n\tunsigned int iowait_boost;\n\tu64 last_update;\n\tlong unsigned int util;\n\tlong unsigned int bw_min;\n\tlong unsigned int saved_idle_calls;\n};\n\nstruct sugov_tunables;\n\nstruct sugov_policy {\n\tstruct cpufreq_policy *policy;\n\tstruct sugov_tunables *tunables;\n\tstruct list_head tunables_hook;\n\traw_spinlock_t update_lock;\n\tu64 last_freq_update_time;\n\ts64 freq_update_delay_ns;\n\tunsigned int next_freq;\n\tunsigned int cached_raw_freq;\n\tstruct irq_work irq_work;\n\tstruct kthread_work work;\n\tstruct mutex work_lock;\n\tstruct kthread_worker worker;\n\tstruct task_struct *thread;\n\tbool work_in_progress;\n\tbool limits_changed;\n\tbool need_freq_update;\n};\n\nstruct sugov_tunables {\n\tstruct gov_attr_set attr_set;\n\tunsigned int rate_limit_us;\n};\n\nstruct sunrpc_net {\n\tstruct proc_dir_entry *proc_net_rpc;\n\tstruct cache_detail *ip_map_cache;\n\tstruct cache_detail *unix_gid_cache;\n\tstruct cache_detail *rsc_cache;\n\tstruct cache_detail *rsi_cache;\n\tstruct super_block *pipefs_sb;\n\tstruct rpc_pipe *gssd_dummy;\n\tstruct mutex pipefs_sb_lock;\n\tstruct list_head all_clients;\n\tspinlock_t rpc_client_lock;\n\tstruct rpc_clnt *rpcb_local_clnt;\n\tstruct rpc_clnt *rpcb_local_clnt4;\n\tspinlock_t rpcb_clnt_lock;\n\tunsigned int rpcb_users;\n\tunsigned int rpcb_is_af_local: 1;\n\tstruct mutex gssp_lock;\n\tstruct rpc_clnt *gssp_clnt;\n\tint use_gss_proxy;\n\tint pipe_version;\n\tatomic_t pipe_users;\n\tstruct proc_dir_entry *use_gssp_proc;\n\tstruct proc_dir_entry *gss_krb5_enctypes;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct mtd_info;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tvoid *s_security;\n\tconst struct xattr_handler * const *s_xattr;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 0;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t);\n\tssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t);\n\tstruct dquot ** (*get_dquots)(struct inode *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct super_type {\n\tchar *name;\n\tstruct module *owner;\n\tint (*load_super)(struct md_rdev *, struct md_rdev *, int);\n\tint (*validate_super)(struct mddev *, struct md_rdev *, struct md_rdev *);\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tlong long unsigned int (*rdev_size_change)(struct md_rdev *, sector_t);\n\tint (*allow_new_offset)(struct md_rdev *, long long unsigned int);\n};\n\nstruct superblock_security_struct {\n\tu32 sid;\n\tu32 def_sid;\n\tu32 mntpoint_sid;\n\tu32 creator_sid;\n\tshort unsigned int behavior;\n\tshort unsigned int flags;\n\tstruct mutex lock;\n\tstruct list_head isec_head;\n\tspinlock_t isec_lock;\n};\n\nstruct survey_info {\n\tstruct ieee80211_channel *channel;\n\tu64 time;\n\tu64 time_busy;\n\tu64 time_ext_busy;\n\tu64 time_rx;\n\tu64 time_tx;\n\tu64 time_scan;\n\tu64 time_bss_rx;\n\tu32 filled;\n\ts8 noise;\n};\n\nstruct suspend_stats {\n\tunsigned int step_failures[8];\n\tunsigned int success;\n\tunsigned int fail;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tu64 last_hw_sleep;\n\tu64 total_hw_sleep;\n\tu64 max_hw_sleep;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nstruct svc_deferred_req {\n\tu32 prot;\n\tstruct svc_xprt *xprt;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tstruct __kernel_sockaddr_storage daddr;\n\tsize_t daddrlen;\n\tvoid *xprt_ctxt;\n\tstruct cache_deferred_req handle;\n\tint argslen;\n\t__be32 args[0];\n};\n\nstruct svc_info {\n\tstruct svc_serv *serv;\n\tstruct mutex *mutex;\n};\n\nstruct svc_pool {\n\tunsigned int sp_id;\n\tunsigned int sp_nrthreads;\n\tunsigned int sp_nrthrmin;\n\tunsigned int sp_nrthrmax;\n\tstruct lwq sp_xprts;\n\tstruct list_head sp_all_threads;\n\tstruct llist_head sp_idle_threads;\n\tstruct percpu_counter sp_messages_arrived;\n\tstruct percpu_counter sp_sockets_queued;\n\tstruct percpu_counter sp_threads_woken;\n\tlong unsigned int sp_flags;\n};\n\nstruct svc_pool_map {\n\tint count;\n\tint mode;\n\tunsigned int npools;\n\tunsigned int *pool_to;\n\tunsigned int *to_pool;\n};\n\nstruct svc_procedure {\n\t__be32 (*pc_func)(struct svc_rqst *);\n\tbool (*pc_decode)(struct svc_rqst *, struct xdr_stream *);\n\tbool (*pc_encode)(struct svc_rqst *, struct xdr_stream *);\n\tvoid (*pc_release)(struct svc_rqst *);\n\tunsigned int pc_argsize;\n\tunsigned int pc_argzero;\n\tunsigned int pc_ressize;\n\tunsigned int pc_cachetype;\n\tunsigned int pc_xdrressize;\n\tconst char *pc_name;\n};\n\nstruct svc_process_info {\n\tunion {\n\t\tint (*dispatch)(struct svc_rqst *);\n\t\tstruct {\n\t\t\tunsigned int lovers;\n\t\t\tunsigned int hivers;\n\t\t} mismatch;\n\t};\n};\n\nstruct svc_version;\n\nstruct svc_program {\n\tu32 pg_prog;\n\tunsigned int pg_lovers;\n\tunsigned int pg_hivers;\n\tunsigned int pg_nvers;\n\tconst struct svc_version **pg_vers;\n\tchar *pg_name;\n\tchar *pg_class;\n\tenum svc_auth_status (*pg_authenticate)(struct svc_rqst *);\n\t__be32 (*pg_init_request)(struct svc_rqst *, const struct svc_program *, struct svc_process_info *);\n\tint (*pg_rpcbind_set)(struct net *, const struct svc_program *, u32, int, short unsigned int, short unsigned int);\n};\n\nstruct xdr_stream {\n\t__be32 *p;\n\tstruct xdr_buf *buf;\n\t__be32 *end;\n\tstruct kvec *iov;\n\tstruct kvec scratch;\n\tstruct page **page_ptr;\n\tvoid *page_kaddr;\n\tunsigned int nwords;\n\tstruct rpc_rqst *rqst;\n};\n\nstruct svc_rqst {\n\tstruct list_head rq_all;\n\tstruct llist_node rq_idle;\n\tstruct callback_head rq_rcu_head;\n\tstruct svc_xprt *rq_xprt;\n\tstruct __kernel_sockaddr_storage rq_addr;\n\tsize_t rq_addrlen;\n\tstruct __kernel_sockaddr_storage rq_daddr;\n\tsize_t rq_daddrlen;\n\tstruct svc_serv *rq_server;\n\tstruct svc_pool *rq_pool;\n\tconst struct svc_procedure *rq_procinfo;\n\tstruct auth_ops *rq_authop;\n\tstruct svc_cred rq_cred;\n\tvoid *rq_xprt_ctxt;\n\tstruct svc_deferred_req *rq_deferred;\n\tstruct xdr_buf rq_arg;\n\tstruct xdr_stream rq_arg_stream;\n\tstruct xdr_stream rq_res_stream;\n\tstruct folio *rq_scratch_folio;\n\tstruct xdr_buf rq_res;\n\tlong unsigned int rq_maxpages;\n\tstruct page **rq_pages;\n\tstruct page **rq_respages;\n\tstruct page **rq_next_page;\n\tstruct page **rq_page_end;\n\tstruct folio_batch rq_fbatch;\n\tstruct bio_vec *rq_bvec;\n\t__be32 rq_xid;\n\tu32 rq_prog;\n\tu32 rq_vers;\n\tu32 rq_proc;\n\tu32 rq_prot;\n\tint rq_cachetype;\n\tlong unsigned int rq_flags;\n\tktime_t rq_qtime;\n\tvoid *rq_argp;\n\tvoid *rq_resp;\n\t__be32 *rq_accept_statp;\n\tvoid *rq_auth_data;\n\t__be32 rq_auth_stat;\n\tint rq_auth_slack;\n\tint rq_reserved;\n\tktime_t rq_stime;\n\tstruct cache_req rq_chandle;\n\tstruct auth_domain *rq_client;\n\tstruct auth_domain *rq_gssclient;\n\tstruct task_struct *rq_task;\n\tstruct net *rq_bc_net;\n\tint rq_err;\n\tlong unsigned int bc_to_initval;\n\tunsigned int bc_to_retries;\n\tunsigned int rq_status_counter;\n\tvoid **rq_lease_breaker;\n};\n\nstruct svc_stat;\n\nstruct svc_serv {\n\tstruct svc_program *sv_programs;\n\tstruct svc_stat *sv_stats;\n\tspinlock_t sv_lock;\n\tunsigned int sv_nprogs;\n\tunsigned int sv_nrthreads;\n\tunsigned int sv_max_payload;\n\tunsigned int sv_max_mesg;\n\tunsigned int sv_xdrsize;\n\tstruct list_head sv_permsocks;\n\tstruct list_head sv_tempsocks;\n\tint sv_tmpcnt;\n\tstruct timer_list sv_temptimer;\n\tchar *sv_name;\n\tunsigned int sv_nrpools;\n\tbool sv_is_pooled;\n\tstruct svc_pool *sv_pools;\n\tint (*sv_threadfn)(void *);\n\tstruct lwq sv_cb_list;\n\tbool sv_bc_enabled;\n};\n\nstruct svc_xprt_class;\n\nstruct svc_xprt_ops;\n\nstruct svc_xprt {\n\tstruct svc_xprt_class *xpt_class;\n\tconst struct svc_xprt_ops *xpt_ops;\n\tstruct kref xpt_ref;\n\tktime_t xpt_qtime;\n\tstruct list_head xpt_list;\n\tstruct lwq_node xpt_ready;\n\tlong unsigned int xpt_flags;\n\tstruct svc_serv *xpt_server;\n\tatomic_t xpt_reserved;\n\tatomic_t xpt_nr_rqsts;\n\tstruct mutex xpt_mutex;\n\tspinlock_t xpt_lock;\n\tvoid *xpt_auth_cache;\n\tstruct list_head xpt_deferred;\n\tstruct __kernel_sockaddr_storage xpt_local;\n\tsize_t xpt_locallen;\n\tstruct __kernel_sockaddr_storage xpt_remote;\n\tsize_t xpt_remotelen;\n\tchar xpt_remotebuf[58];\n\tstruct list_head xpt_users;\n\tstruct net *xpt_net;\n\tnetns_tracker ns_tracker;\n\tconst struct cred *xpt_cred;\n\tstruct rpc_xprt *xpt_bc_xprt;\n\tstruct rpc_xprt_switch *xpt_bc_xps;\n};\n\nstruct svc_sock {\n\tstruct svc_xprt sk_xprt;\n\tstruct socket *sk_sock;\n\tstruct sock *sk_sk;\n\tvoid (*sk_ostate)(struct sock *);\n\tvoid (*sk_odata)(struct sock *);\n\tvoid (*sk_owspace)(struct sock *);\n\tstruct bio_vec *sk_bvec;\n\t__be32 sk_marker;\n\tu32 sk_tcplen;\n\tu32 sk_datalen;\n\tstruct page_frag_cache sk_frag_cache;\n\tstruct completion sk_handshake_done;\n\tlong unsigned int sk_maxpages;\n\tstruct page *sk_pages[0];\n};\n\nstruct svc_stat {\n\tstruct svc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcbadfmt;\n\tunsigned int rpcbadauth;\n\tunsigned int rpcbadclnt;\n};\n\nstruct svc_version {\n\tu32 vs_vers;\n\tu32 vs_nproc;\n\tconst struct svc_procedure *vs_proc;\n\tlong unsigned int *vs_count;\n\tu32 vs_xdrsize;\n\tbool vs_hidden;\n\tbool vs_rpcb_optnl;\n\tbool vs_need_cong_ctrl;\n\tint (*vs_dispatch)(struct svc_rqst *);\n};\n\nstruct svc_xprt_class {\n\tconst char *xcl_name;\n\tstruct module *xcl_owner;\n\tconst struct svc_xprt_ops *xcl_ops;\n\tstruct list_head xcl_list;\n\tu32 xcl_max_payload;\n\tint xcl_ident;\n};\n\nstruct svc_xprt_ops {\n\tstruct svc_xprt * (*xpo_create)(struct svc_serv *, struct net *, struct sockaddr *, int, int);\n\tstruct svc_xprt * (*xpo_accept)(struct svc_xprt *);\n\tint (*xpo_has_wspace)(struct svc_xprt *);\n\tint (*xpo_recvfrom)(struct svc_rqst *);\n\tint (*xpo_sendto)(struct svc_rqst *);\n\tint (*xpo_result_payload)(struct svc_rqst *, unsigned int, unsigned int);\n\tvoid (*xpo_release_ctxt)(struct svc_xprt *, void *);\n\tvoid (*xpo_detach)(struct svc_xprt *);\n\tvoid (*xpo_free)(struct svc_xprt *);\n\tvoid (*xpo_kill_temp_xprt)(struct svc_xprt *);\n\tvoid (*xpo_handshake)(struct svc_xprt *);\n};\n\nstruct svc_xpt_user {\n\tstruct list_head list;\n\tvoid (*callback)(struct svc_xpt_user *);\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[1];\n\tstruct list_head frag_clusters[1];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_map_page;\n\nstruct swap_map_page_list;\n\nstruct swap_map_handle {\n\tstruct swap_map_page *cur;\n\tstruct swap_map_page_list *maps;\n\tsector_t cur_swap;\n\tsector_t first_sector;\n\tunsigned int k;\n\tlong unsigned int reqd_free_pages;\n\tu32 crc32;\n};\n\nstruct swap_map_page {\n\tsector_t entries[511];\n\tsector_t next_swap;\n};\n\nstruct swap_map_page_list {\n\tstruct swap_map_page *map;\n\tstruct swap_map_page_list *next;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[1];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[256];\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n};\n\nstruct swmii_regs {\n\tu16 bmsr;\n\tu16 lpa;\n\tu16 lpagb;\n\tu16 estat;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct swoc_info {\n\t__u8 rev;\n\t__u8 reserved[8];\n\t__u16 LinuxSKU;\n\t__u16 LinuxVer;\n\t__u8 reserved2[47];\n} __attribute__((packed));\n\nstruct swsusp_extent {\n\tstruct rb_node node;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct swsusp_header {\n\tchar reserved[4056];\n\tu32 hw_sig;\n\tu32 crc32;\n\tsector_t image;\n\tunsigned int flags;\n\tchar orig_sig[10];\n\tchar sig[10];\n};\n\nstruct swsusp_info {\n\tstruct new_utsname uts;\n\tu32 version_code;\n\tlong unsigned int num_physpages;\n\tint cpus;\n\tlong unsigned int image_pages;\n\tlong unsigned int pages;\n\tlong unsigned int size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sym_count_ctx {\n\tunsigned int count;\n\tconst char *name;\n};\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tbool pt_port_open;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct sync_fence_info {\n\tchar obj_name[32];\n\tchar driver_name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u64 timestamp_ns;\n};\n\nstruct sync_file {\n\tstruct file *file;\n\tchar user_name[32];\n\tstruct list_head sync_file_list;\n\twait_queue_head_t wq;\n\tlong unsigned int flags;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct sync_file_info {\n\tchar name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u32 num_fences;\n\t__u32 pad;\n\t__u64 sync_fence_info;\n};\n\nstruct sync_io {\n\tlong unsigned int error_bits;\n\tstruct completion wait;\n};\n\nstruct sync_merge_data {\n\tchar name[32];\n\t__s32 fd2;\n\t__s32 fence;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct sync_set_deadline {\n\t__u64 deadline_ns;\n\t__u64 pad;\n};\n\nstruct syncobj_eventfd_entry {\n\tstruct list_head node;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tstruct drm_syncobj *syncobj;\n\tstruct eventfd_ctx *ev_fd_ctx;\n\tu64 point;\n\tu32 flags;\n};\n\nstruct syncobj_wait_entry {\n\tstruct list_head node;\n\tstruct task_struct *task;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tu64 point;\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_user_dispatch {\n\tchar *selector;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tbool on_dispatch;\n};\n\nstruct syscore_ops;\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysfb_display_info {\n\tstruct screen_info screen;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysfs_wi_group {\n\tstruct kobject wi_kobj;\n\tstruct mutex kobj_lock;\n\tstruct iw_node_attr *nattrs[0];\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[0];\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[12];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tunsigned int shift;\n\tunsigned int shift_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[12];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct table_device {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev dm_dev;\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\ntypedef int (*dm_ctr_fn)(struct dm_target *, unsigned int, char **);\n\ntypedef void (*dm_dtr_fn)(struct dm_target *);\n\ntypedef int (*dm_map_fn)(struct dm_target *, struct bio *);\n\ntypedef int (*dm_clone_and_map_request_fn)(struct dm_target *, struct request *, union map_info *, struct request **);\n\ntypedef void (*dm_release_clone_request_fn)(struct request *, union map_info *);\n\ntypedef int (*dm_endio_fn)(struct dm_target *, struct bio *, blk_status_t *);\n\ntypedef int (*dm_request_endio_fn)(struct dm_target *, struct request *, blk_status_t, union map_info *);\n\ntypedef void (*dm_presuspend_fn)(struct dm_target *);\n\ntypedef void (*dm_presuspend_undo_fn)(struct dm_target *);\n\ntypedef void (*dm_postsuspend_fn)(struct dm_target *);\n\ntypedef int (*dm_preresume_fn)(struct dm_target *);\n\ntypedef void (*dm_resume_fn)(struct dm_target *);\n\ntypedef void (*dm_status_fn)(struct dm_target *, status_type_t, unsigned int, char *, unsigned int);\n\ntypedef int (*dm_message_fn)(struct dm_target *, unsigned int, char **, char *, unsigned int);\n\ntypedef int (*dm_prepare_ioctl_fn)(struct dm_target *, struct block_device **, unsigned int, long unsigned int, bool *);\n\ntypedef int (*dm_report_zones_fn)(struct dm_target *);\n\ntypedef int (*dm_busy_fn)(struct dm_target *);\n\ntypedef int (*iterate_devices_callout_fn)(struct dm_target *, struct dm_dev *, sector_t, sector_t, void *);\n\ntypedef int (*dm_iterate_devices_fn)(struct dm_target *, iterate_devices_callout_fn, void *);\n\ntypedef void (*dm_io_hints_fn)(struct dm_target *, struct queue_limits *);\n\ntypedef long int (*dm_dax_direct_access_fn)(struct dm_target *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\ntypedef int (*dm_dax_zero_page_range_fn)(struct dm_target *, long unsigned int, size_t);\n\ntypedef size_t (*dm_dax_recovery_write_fn)(struct dm_target *, long unsigned int, void *, size_t, struct iov_iter *);\n\nstruct target_type {\n\tuint64_t features;\n\tconst char *name;\n\tstruct module *module;\n\tunsigned int version[3];\n\tdm_ctr_fn ctr;\n\tdm_dtr_fn dtr;\n\tdm_map_fn map;\n\tdm_clone_and_map_request_fn clone_and_map_rq;\n\tdm_release_clone_request_fn release_clone_rq;\n\tdm_endio_fn end_io;\n\tdm_request_endio_fn rq_end_io;\n\tdm_presuspend_fn presuspend;\n\tdm_presuspend_undo_fn presuspend_undo;\n\tdm_postsuspend_fn postsuspend;\n\tdm_preresume_fn preresume;\n\tdm_resume_fn resume;\n\tdm_status_fn status;\n\tdm_message_fn message;\n\tdm_prepare_ioctl_fn prepare_ioctl;\n\tdm_report_zones_fn report_zones;\n\tdm_busy_fn busy;\n\tdm_iterate_devices_fn iterate_devices;\n\tdm_io_hints_fn io_hints;\n\tdm_dax_direct_access_fn direct_access;\n\tdm_dax_zero_page_range_fn dax_zero_page_range;\n\tdm_dax_recovery_write_fn dax_recovery_write;\n\tstruct list_head list;\n};\n\nstruct task_delay_info {\n\traw_spinlock_t lock;\n\tu64 blkio_start;\n\tu64 blkio_delay_max;\n\tu64 blkio_delay_min;\n\tu64 blkio_delay;\n\tu64 swapin_start;\n\tu64 swapin_delay_max;\n\tu64 swapin_delay_min;\n\tu64 swapin_delay;\n\tu32 blkio_count;\n\tu32 swapin_count;\n\tu64 freepages_start;\n\tu64 freepages_delay_max;\n\tu64 freepages_delay_min;\n\tu64 freepages_delay;\n\tu64 thrashing_start;\n\tu64 thrashing_delay_max;\n\tu64 thrashing_delay_min;\n\tu64 thrashing_delay;\n\tu64 compact_start;\n\tu64 compact_delay_max;\n\tu64 compact_delay_min;\n\tu64 compact_delay;\n\tu64 wpcopy_start;\n\tu64 wpcopy_delay_max;\n\tu64 wpcopy_delay_min;\n\tu64 wpcopy_delay;\n\tu64 irq_delay_max;\n\tu64 irq_delay_min;\n\tu64 irq_delay;\n\tu32 freepages_count;\n\tu32 thrashing_count;\n\tu32 compact_count;\n\tu32 wpcopy_count;\n\tu32 irq_count;\n\tstruct timespec64 blkio_delay_max_ts;\n\tstruct timespec64 swapin_delay_max_ts;\n\tstruct timespec64 freepages_delay_max_ts;\n\tstruct timespec64 thrashing_delay_max_ts;\n\tstruct timespec64 compact_delay_max_ts;\n\tstruct timespec64 wpcopy_delay_max_ts;\n\tstruct timespec64 irq_delay_max_ts;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t load_avg;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_numa_env {\n\tstruct task_struct *p;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tint imb_numa_nr;\n\tstruct numa_stats src_stats;\n\tstruct numa_stats dst_stats;\n\tint imbalance_pct;\n\tint dist;\n\tstruct task_struct *best_task;\n\tlong int best_imp;\n\tint best_cpu;\n};\n\nstruct task_security_struct {\n\tstruct {\n\t\tu32 sid;\n\t\tu32 seqno;\n\t\tunsigned int dir_spot;\n\t\tstruct avdc_entry dir[4];\n\t\tbool permissive_neveraudit;\n\t} avdcache;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct thread_info {\n\tlong unsigned int flags;\n\tlong unsigned int syscall_work;\n\tu32 status;\n\tu32 cpu;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {\n\tstruct arch_tlbflush_unmap_batch arch;\n\tbool flush_required;\n\tbool writable;\n};\n\nunion unwind_task_id {\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 cnt;\n\t};\n\tu64 id;\n};\n\nstruct unwind_cache;\n\nstruct unwind_task_info {\n\tatomic_long_t unwind_mask;\n\tstruct unwind_cache *cache;\n\tstruct callback_head work;\n\tunion unwind_task_id id;\n};\n\nstruct thread_struct {\n\tstruct desc_struct tls_array[3];\n\tlong unsigned int sp;\n\tshort unsigned int es;\n\tshort unsigned int ds;\n\tshort unsigned int fsindex;\n\tshort unsigned int gsindex;\n\tlong unsigned int fsbase;\n\tlong unsigned int gsbase;\n\tstruct perf_event *ptrace_bps[4];\n\tlong unsigned int virtual_dr6;\n\tlong unsigned int ptrace_dr7;\n\tlong unsigned int cr2;\n\tlong unsigned int trap_nr;\n\tlong unsigned int error_code;\n\tstruct io_bitmap *io_bitmap;\n\tlong unsigned int iopl_emul;\n\tunsigned int iopl_warn: 1;\n\tu32 pkru;\n};\n\nstruct uprobe_task;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct task_group *sched_task_group;\n\tstruct callback_head sched_throttle_work;\n\tstruct list_head throttle_node;\n\tbool throttled;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_statistics stats;\n\tunsigned int btrace_seq;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tint rcu_read_lock_nesting;\n\tunion rcu_special rcu_read_unlock_special;\n\tstruct list_head rcu_node_entry;\n\tstruct rcu_node *rcu_blocked_node;\n\tlong unsigned int rcu_tasks_nvcsw;\n\tu8 rcu_tasks_holdout;\n\tu8 rcu_tasks_idx;\n\tint rcu_tasks_idle_cpu;\n\tstruct list_head rcu_tasks_holdout_list;\n\tint rcu_tasks_exit_cpu;\n\tstruct list_head rcu_tasks_exit_list;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int restore_sigmask: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int use_memdelay: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int pasid_activated: 1;\n\tunsigned int reported_split_lock: 1;\n\tunsigned int in_thrashing: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct posix_cputimers_work posix_cputimers_work;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct audit_context *audit_context;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tu64 acct_rss_mem1;\n\tu64 acct_vm_mem1;\n\tu64 acct_timexpd;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct compat_robust_list_head *compat_robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tu8 perf_recursion[4];\n\tstruct perf_event_context *perf_event_ctxp;\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct perf_ctx_data *perf_ctx_data;\n\tstruct mempolicy *mempolicy;\n\tshort int il_prev;\n\tu8 il_weight;\n\tshort int pref_node_fork;\n\tint numa_scan_seq;\n\tunsigned int numa_scan_period;\n\tunsigned int numa_scan_period_max;\n\tint numa_preferred_nid;\n\tlong unsigned int numa_migrate_retry;\n\tu64 node_stamp;\n\tu64 last_task_numa_placement;\n\tu64 last_sum_exec_runtime;\n\tstruct callback_head numa_work;\n\tstruct numa_group *numa_group;\n\tlong unsigned int *numa_faults;\n\tlong unsigned int total_numa_faults;\n\tlong unsigned int numa_faults_locality[3];\n\tlong unsigned int numa_pages_migrated;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tstruct task_delay_info *delays;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tlong unsigned int trace_recursion;\n\tstruct gendisk *throttle_disk;\n\tstruct uprobe_task *utask;\n\tstruct kmap_ctrl kmap_ctrl;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\tstruct vm_struct *stack_vm_area;\n\trefcount_t stack_refcount;\n\tvoid *security;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tvoid *mce_vaddr;\n\t__u64 mce_kflags;\n\tu64 mce_addr;\n\t__u64 mce_ripv: 1;\n\t__u64 mce_whole_page: 1;\n\t__u64 __mce_reserved: 62;\n\tstruct callback_head mce_kill_me;\n\tint mce_count;\n\tstruct llist_head kretprobe_instances;\n\tstruct llist_head rethooks;\n\tstruct callback_head l1d_flush_kill;\n\tstruct unwind_task_info unwind_info;\n\tstruct thread_struct thread;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct taskstats {\n\t__u16 version;\n\t__u32 ac_exitcode;\n\t__u8 ac_flag;\n\t__u8 ac_nice;\n\t__u64 cpu_count;\n\t__u64 cpu_delay_total;\n\t__u64 blkio_count;\n\t__u64 blkio_delay_total;\n\t__u64 swapin_count;\n\t__u64 swapin_delay_total;\n\t__u64 cpu_run_real_total;\n\t__u64 cpu_run_virtual_total;\n\tchar ac_comm[32];\n\t__u8 ac_sched;\n\t__u8 ac_pad[3];\n\tlong: 0;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u64 ac_etime;\n\t__u64 ac_utime;\n\t__u64 ac_stime;\n\t__u64 ac_minflt;\n\t__u64 ac_majflt;\n\t__u64 coremem;\n\t__u64 virtmem;\n\t__u64 hiwater_rss;\n\t__u64 hiwater_vm;\n\t__u64 read_char;\n\t__u64 write_char;\n\t__u64 read_syscalls;\n\t__u64 write_syscalls;\n\t__u64 read_bytes;\n\t__u64 write_bytes;\n\t__u64 cancelled_write_bytes;\n\t__u64 nvcsw;\n\t__u64 nivcsw;\n\t__u64 ac_utimescaled;\n\t__u64 ac_stimescaled;\n\t__u64 cpu_scaled_run_real_total;\n\t__u64 freepages_count;\n\t__u64 freepages_delay_total;\n\t__u64 thrashing_count;\n\t__u64 thrashing_delay_total;\n\t__u64 ac_btime64;\n\t__u64 compact_count;\n\t__u64 compact_delay_total;\n\t__u32 ac_tgid;\n\t__u64 ac_tgetime;\n\t__u64 ac_exe_dev;\n\t__u64 ac_exe_inode;\n\t__u64 wpcopy_count;\n\t__u64 wpcopy_delay_total;\n\t__u64 irq_count;\n\t__u64 irq_delay_total;\n\t__u64 cpu_delay_max;\n\t__u64 cpu_delay_min;\n\t__u64 blkio_delay_max;\n\t__u64 blkio_delay_min;\n\t__u64 swapin_delay_max;\n\t__u64 swapin_delay_min;\n\t__u64 freepages_delay_max;\n\t__u64 freepages_delay_min;\n\t__u64 thrashing_delay_max;\n\t__u64 thrashing_delay_min;\n\t__u64 compact_delay_max;\n\t__u64 compact_delay_min;\n\t__u64 wpcopy_delay_max;\n\t__u64 wpcopy_delay_min;\n\t__u64 irq_delay_max;\n\t__u64 irq_delay_min;\n\tstruct __kernel_timespec cpu_delay_max_ts;\n\tstruct __kernel_timespec blkio_delay_max_ts;\n\tstruct __kernel_timespec swapin_delay_max_ts;\n\tstruct __kernel_timespec freepages_delay_max_ts;\n\tstruct __kernel_timespec thrashing_delay_max_ts;\n\tstruct __kernel_timespec compact_delay_max_ts;\n\tstruct __kernel_timespec wpcopy_delay_max_ts;\n\tstruct __kernel_timespec irq_delay_max_ts;\n};\n\nstruct tbtt_info_iter_data {\n\tconst struct ieee80211_neighbor_ap_info *ap_info;\n\tu8 param_ch_count;\n\tu32 use_for;\n\tu8 mld_id;\n\tu8 link_id;\n\tbool non_tx;\n};\n\nstruct tc_act_pernet_id {\n\tstruct list_head list;\n\tunsigned int id;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tstruct tcf_t tcfa_tm;\n\tlong: 64;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n};\n\nstruct tc_action_net {\n\tstruct tcf_idrinfo *idrinfo;\n\tconst struct tc_action_ops *ops;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_bind_class_args {\n\tstruct qdisc_walker w;\n\tlong unsigned int new_cl;\n\tu32 portid;\n\tu32 clid;\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_fifo_qopt {\n\t__u32 limit;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_fifo_qopt_offload {\n\tenum tc_fifo_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t};\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_pedit_key {\n\t__u32 mask;\n\t__u32 val;\n\t__u32 off;\n\t__u32 at;\n\t__u32 offmask;\n\t__u32 shift;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_root_qopt_offload {\n\tenum tc_root_command command;\n\tu32 handle;\n\tbool ingress;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tcamsg {\n\tunsigned char tca_family;\n\tunsigned char tca__pad1;\n\tshort unsigned int tca__pad2;\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcf_bind_args {\n\tstruct tcf_walker w;\n\tlong unsigned int base;\n\tlong unsigned int cl;\n\tu32 classid;\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\ntypedef void tcf_chain_head_change_t(struct tcf_proto *, void *);\n\nstruct tcf_block_ext_info {\n\tenum flow_block_binder_type binder_type;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n\tu32 block_index;\n};\n\nstruct tcf_block_owner_item {\n\tstruct list_head list;\n\tstruct Qdisc *q;\n\tenum flow_block_binder_type binder_type;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_chain_info {\n\tstruct tcf_proto **pprev;\n\tstruct tcf_proto *next;\n};\n\nstruct tcf_dump_args {\n\tstruct tcf_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct tcf_block *block;\n\tstruct Qdisc *q;\n\tu32 parent;\n\tbool terse_dump;\n};\n\nstruct tcf_ematch_ops;\n\nstruct tcf_ematch {\n\tstruct tcf_ematch_ops *ops;\n\tlong unsigned int data;\n\tunsigned int datalen;\n\tu16 matchid;\n\tu16 flags;\n\tstruct net *net;\n};\n\nstruct tcf_ematch_hdr {\n\t__u16 matchid;\n\t__u16 kind;\n\t__u16 flags;\n\t__u16 pad;\n};\n\nstruct tcf_pkt_info;\n\nstruct tcf_ematch_ops {\n\tint kind;\n\tint datalen;\n\tint (*change)(struct net *, void *, int, struct tcf_ematch *);\n\tint (*match)(struct sk_buff *, struct tcf_ematch *, struct tcf_pkt_info *);\n\tvoid (*destroy)(struct tcf_ematch *);\n\tint (*dump)(struct sk_buff *, struct tcf_ematch *);\n\tstruct module *owner;\n\tstruct list_head link;\n};\n\nunion tcf_exts_miss_cookie {\n\tstruct {\n\t\tu32 miss_cookie_base;\n\t\tu32 act_index;\n\t};\n\tu64 miss_cookie;\n};\n\nstruct tcf_exts_miss_cookie_node {\n\tconst struct tcf_chain *chain;\n\tconst struct tcf_proto *tp;\n\tconst struct tcf_exts *exts;\n\tu32 chain_index;\n\tu32 tp_prio;\n\tu32 handle;\n\tu32 miss_cookie_base;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_filter_chain_list_item {\n\tstruct list_head list;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_net {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n};\n\nstruct tcf_pedit_parms;\n\nstruct tcf_pedit {\n\tstruct tc_action common;\n\tstruct tcf_pedit_parms *parms;\n\tlong: 64;\n};\n\nstruct tcf_pedit_key_ex {\n\tenum pedit_header_type htype;\n\tenum pedit_cmd cmd;\n};\n\nstruct tcf_pedit_parms {\n\tstruct tc_pedit_key *tcfp_keys;\n\tstruct tcf_pedit_key_ex *tcfp_keys_ex;\n\tint action;\n\tu32 tcfp_off_max_hint;\n\tunsigned char tcfp_nkeys;\n\tunsigned char tcfp_flags;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_pkt_info {\n\tunsigned char *ptr;\n\tint nexthdr;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_qevent {\n\tstruct tcf_block *block;\n\tstruct tcf_block_ext_info info;\n\tstruct tcf_proto *filter_chain;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcp4_pseudohdr {\n\t__be32 saddr;\n\t__be32 daddr;\n\t__u8 pad;\n\t__u8 protocol;\n\t__be16 len;\n};\n\nstruct tcp6_pseudohdr {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\t__be32 len;\n\t__be32 protocol;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_sock_af_ops;\n\nstruct tcp_md5sig_info;\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tconst struct tcp_sock_af_ops *af_specific;\n\tstruct tcp_md5sig_info *md5sig_info;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig {\n\tstruct __kernel_sockaddr_storage tcpm_addr;\n\t__u8 tcpm_flags;\n\t__u8 tcpm_prefixlen;\n\t__u16 tcpm_keylen;\n\tint tcpm_ifindex;\n\t__u8 tcpm_key[80];\n};\n\nstruct tcp_md5sig_info {\n\tstruct hlist_head head;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\tstruct tcp_md5sig_key * (*req_md5_lookup)(const struct sock *, const struct sock *);\n\tvoid (*calc_md5_hash)(char *, const struct tcp_md5sig_key *, const struct sock *, const struct sk_buff *);\n\t__u32 (*cookie_init_seq)(const struct sk_buff *, __u16 *);\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t};\n};\n\nstruct tcp_sock_af_ops {\n\tstruct tcp_md5sig_key * (*md5_lookup)(const struct sock *, const struct sock *);\n\tvoid (*calc_md5_hash)(char *, const struct tcp_md5sig_key *, const struct sock *, const struct sk_buff *);\n\tint (*md5_parse)(struct sock *, int, sockptr_t, int);\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n\tstruct tcp_md5sig_key *tw_md5_key;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 ae: 1;\n\t__u16 res1: 3;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n};\n\nstruct td {\n\t__hc32 hwINFO;\n\t__hc32 hwCBP;\n\t__hc32 hwNextTD;\n\t__hc32 hwBE;\n\t__hc16 hwPSW[2];\n\t__u8 index;\n\tstruct ed *ed;\n\tstruct td *td_hash;\n\tstruct td *next_dl_td;\n\tstruct urb *urb;\n\tdma_addr_t td_dma;\n\tdma_addr_t data_dma;\n\tstruct list_head td_list;\n\tlong: 64;\n};\n\nstruct temp_masks {\n\tu32 tcc_offset;\n\tu32 digital_readout;\n\tu32 pkg_digital_readout;\n};\n\nstruct temp_regset {\n\tstruct guc_mmio_reg *registers;\n\tstruct guc_mmio_reg *storage;\n\tu32 storage_used;\n\tu32 storage_max;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[8];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nunion text_poke_insn {\n\tu8 text[5];\n\tstruct {\n\t\tu8 opcode;\n\t\ts32 disp;\n\t} __attribute__((packed));\n};\n\nstruct tfp410_priv {\n\tbool quiet;\n};\n\nstruct tg3_rx_buffer_desc;\n\nstruct tg3_ext_rx_buffer_desc;\n\nstruct tg3_rx_prodring_set {\n\tu32 rx_std_prod_idx;\n\tu32 rx_std_cons_idx;\n\tu32 rx_jmb_prod_idx;\n\tu32 rx_jmb_cons_idx;\n\tstruct tg3_rx_buffer_desc *rx_std;\n\tstruct tg3_ext_rx_buffer_desc *rx_jmb;\n\tstruct ring_info___2 *rx_std_buffers;\n\tstruct ring_info___2 *rx_jmb_buffers;\n\tdma_addr_t rx_std_mapping;\n\tdma_addr_t rx_jmb_mapping;\n};\n\nstruct tg3;\n\nstruct tg3_hw_status;\n\nstruct tg3_tx_buffer_desc;\n\nstruct tg3_tx_ring_info;\n\nstruct tg3_napi {\n\tstruct napi_struct napi;\n\tstruct tg3 *tp;\n\tstruct tg3_hw_status *hw_status;\n\tu32 chk_msi_cnt;\n\tu32 last_tag;\n\tu32 last_irq_tag;\n\tu32 int_mbox;\n\tu32 coal_now;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 consmbox;\n\tu32 rx_rcb_ptr;\n\tu32 last_rx_cons;\n\tu16 *rx_rcb_prod_idx;\n\tstruct tg3_rx_prodring_set prodring;\n\tstruct tg3_rx_buffer_desc *rx_rcb;\n\tlong unsigned int rx_dropped;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 tx_prod;\n\tu32 tx_cons;\n\tu32 tx_pending;\n\tu32 last_tx_cons;\n\tu32 prodmbox;\n\tstruct tg3_tx_buffer_desc *tx_ring;\n\tstruct tg3_tx_ring_info *tx_buffers;\n\tlong unsigned int tx_dropped;\n\tdma_addr_t status_mapping;\n\tdma_addr_t rx_rcb_mapping;\n\tdma_addr_t tx_desc_mapping;\n\tchar irq_lbl[32];\n\tunsigned int irq_vec;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tg3_ethtool_stats {\n\tu64 rx_octets;\n\tu64 rx_fragments;\n\tu64 rx_ucast_packets;\n\tu64 rx_mcast_packets;\n\tu64 rx_bcast_packets;\n\tu64 rx_fcs_errors;\n\tu64 rx_align_errors;\n\tu64 rx_xon_pause_rcvd;\n\tu64 rx_xoff_pause_rcvd;\n\tu64 rx_mac_ctrl_rcvd;\n\tu64 rx_xoff_entered;\n\tu64 rx_frame_too_long_errors;\n\tu64 rx_jabbers;\n\tu64 rx_undersize_packets;\n\tu64 rx_in_length_errors;\n\tu64 rx_out_length_errors;\n\tu64 rx_64_or_less_octet_packets;\n\tu64 rx_65_to_127_octet_packets;\n\tu64 rx_128_to_255_octet_packets;\n\tu64 rx_256_to_511_octet_packets;\n\tu64 rx_512_to_1023_octet_packets;\n\tu64 rx_1024_to_1522_octet_packets;\n\tu64 rx_1523_to_2047_octet_packets;\n\tu64 rx_2048_to_4095_octet_packets;\n\tu64 rx_4096_to_8191_octet_packets;\n\tu64 rx_8192_to_9022_octet_packets;\n\tu64 tx_octets;\n\tu64 tx_collisions;\n\tu64 tx_xon_sent;\n\tu64 tx_xoff_sent;\n\tu64 tx_flow_control;\n\tu64 tx_mac_errors;\n\tu64 tx_single_collisions;\n\tu64 tx_mult_collisions;\n\tu64 tx_deferred;\n\tu64 tx_excessive_collisions;\n\tu64 tx_late_collisions;\n\tu64 tx_collide_2times;\n\tu64 tx_collide_3times;\n\tu64 tx_collide_4times;\n\tu64 tx_collide_5times;\n\tu64 tx_collide_6times;\n\tu64 tx_collide_7times;\n\tu64 tx_collide_8times;\n\tu64 tx_collide_9times;\n\tu64 tx_collide_10times;\n\tu64 tx_collide_11times;\n\tu64 tx_collide_12times;\n\tu64 tx_collide_13times;\n\tu64 tx_collide_14times;\n\tu64 tx_collide_15times;\n\tu64 tx_ucast_packets;\n\tu64 tx_mcast_packets;\n\tu64 tx_bcast_packets;\n\tu64 tx_carrier_sense_errors;\n\tu64 tx_discards;\n\tu64 tx_errors;\n\tu64 dma_writeq_full;\n\tu64 dma_write_prioq_full;\n\tu64 rxbds_empty;\n\tu64 rx_discards;\n\tu64 rx_errors;\n\tu64 rx_threshold_hit;\n\tu64 dma_readq_full;\n\tu64 dma_read_prioq_full;\n\tu64 tx_comp_queue_full;\n\tu64 ring_set_send_prod_index;\n\tu64 ring_status_update;\n\tu64 nic_irqs;\n\tu64 nic_avoided_irqs;\n\tu64 nic_tx_threshold_hit;\n\tu64 mbuf_lwm_thresh_hit;\n};\n\nstruct tg3_link_config {\n\tu32 advertising;\n\tu32 speed;\n\tu8 duplex;\n\tu8 autoneg;\n\tu8 flowctrl;\n\tu8 active_flowctrl;\n\tu8 active_duplex;\n\tu32 active_speed;\n\tu32 rmt_adv;\n};\n\nstruct tg3_bufmgr_config {\n\tu32 mbuf_read_dma_low_water;\n\tu32 mbuf_mac_rx_low_water;\n\tu32 mbuf_high_water;\n\tu32 mbuf_read_dma_low_water_jumbo;\n\tu32 mbuf_mac_rx_low_water_jumbo;\n\tu32 mbuf_high_water_jumbo;\n\tu32 dma_low_water;\n\tu32 dma_high_water;\n};\n\nstruct tg3_hw_stats;\n\nstruct tg3 {\n\tunsigned int irq_sync;\n\tspinlock_t lock;\n\tspinlock_t indirect_lock;\n\tu32 (*read32)(struct tg3 *, u32);\n\tvoid (*write32)(struct tg3 *, u32, u32);\n\tu32 (*read32_mbox)(struct tg3 *, u32);\n\tvoid (*write32_mbox)(struct tg3 *, u32, u32);\n\tvoid *regs;\n\tvoid *aperegs;\n\tstruct net_device *dev;\n\tstruct pci_dev *pdev;\n\tu32 coal_now;\n\tu32 msg_enable;\n\tstruct ptp_clock_info ptp_info;\n\tstruct ptp_clock *ptp_clock;\n\ts64 ptp_adjust;\n\tu8 ptp_txts_retrycnt;\n\tvoid (*write32_tx_mbox)(struct tg3 *, u32, u32);\n\tu32 dma_limit;\n\tu32 txq_req;\n\tu32 txq_cnt;\n\tu32 txq_max;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tg3_napi napi[5];\n\tvoid (*write32_rx_mbox)(struct tg3 *, u32, u32);\n\tu32 rx_copy_thresh;\n\tu32 rx_std_ring_mask;\n\tu32 rx_jmb_ring_mask;\n\tu32 rx_ret_ring_mask;\n\tu32 rx_pending;\n\tu32 rx_jumbo_pending;\n\tu32 rx_std_max_post;\n\tu32 rx_offset;\n\tu32 rx_pkt_map_sz;\n\tu32 rxq_req;\n\tu32 rxq_cnt;\n\tu32 rxq_max;\n\tbool rx_refill;\n\tstruct rtnl_link_stats64 net_stats_prev;\n\tstruct tg3_ethtool_stats estats_prev;\n\tlong unsigned int tg3_flags[2];\n\tunion {\n\t\tlong unsigned int phy_crc_errors;\n\t\tlong unsigned int last_event_jiffies;\n\t};\n\tstruct timer_list timer;\n\tu16 timer_counter;\n\tu16 timer_multiplier;\n\tu32 timer_offset;\n\tu16 asf_counter;\n\tu16 asf_multiplier;\n\tu32 serdes_counter;\n\tstruct tg3_link_config link_config;\n\tstruct tg3_bufmgr_config bufmgr_config;\n\tu32 rx_mode;\n\tu32 tx_mode;\n\tu32 mac_mode;\n\tu32 mi_mode;\n\tu32 misc_host_ctrl;\n\tu32 grc_mode;\n\tu32 grc_local_ctrl;\n\tu32 dma_rwctrl;\n\tu32 coalesce_mode;\n\tu32 pwrmgmt_thresh;\n\tu32 rxptpctl;\n\tu32 pci_chip_rev_id;\n\tu16 pci_cmd;\n\tu8 pci_cacheline_sz;\n\tu8 pci_lat_timer;\n\tint pci_fn;\n\tint msi_cap;\n\tint pcix_cap;\n\tint pcie_readrq;\n\tstruct mii_bus *mdio_bus;\n\tint old_link;\n\tu8 phy_addr;\n\tu8 phy_ape_lock;\n\tu32 phy_id;\n\tu32 phy_flags;\n\tu32 led_ctrl;\n\tu32 phy_otp;\n\tu32 setlpicnt;\n\tu8 rss_ind_tbl[128];\n\tchar board_part_number[24];\n\tchar fw_ver[32];\n\tu32 nic_sram_data_cfg;\n\tu32 pci_clock_ctrl;\n\tstruct pci_dev *pdev_peer;\n\tstruct tg3_hw_stats *hw_stats;\n\tdma_addr_t stats_mapping;\n\tstruct work_struct reset_task;\n\tstruct sk_buff *tx_tstamp_skb;\n\tu64 pre_tx_ts;\n\tint nvram_lock_cnt;\n\tu32 nvram_size;\n\tu32 nvram_pagesize;\n\tu32 nvram_jedecnum;\n\tunsigned int irq_max;\n\tunsigned int irq_cnt;\n\tstruct ethtool_coalesce coal;\n\tstruct ethtool_keee eee;\n\tconst char *fw_needed;\n\tconst struct firmware *fw;\n\tu32 fw_len;\n\tstruct device *hwmon_dev;\n\tbool link_up;\n\tbool pcierr_recovery;\n\tu32 ape_hb;\n\tlong unsigned int ape_hb_interval;\n\tlong unsigned int ape_hb_jiffies;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tg3_dev_id {\n\tu32 vendor;\n\tu32 device;\n\tu32 rev;\n};\n\nstruct tg3_dev_id___2 {\n\tu32 vendor;\n\tu32 device;\n};\n\nstruct tg3_rx_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 idx_len;\n\tu32 type_flags;\n\tu32 ip_tcp_csum;\n\tu32 err_vlan;\n\tu32 reserved;\n\tu32 opaque;\n};\n\nstruct tg3_ext_rx_buffer_desc {\n\tstruct {\n\t\tu32 addr_hi;\n\t\tu32 addr_lo;\n\t} addrlist[3];\n\tu32 len2_len1;\n\tu32 resv_len3;\n\tstruct tg3_rx_buffer_desc std;\n};\n\nstruct tg3_fiber_aneginfo {\n\tint state;\n\tu32 flags;\n\tlong unsigned int link_time;\n\tlong unsigned int cur_time;\n\tu32 ability_match_cfg;\n\tint ability_match_count;\n\tchar ability_match;\n\tchar idle_match;\n\tchar ack_match;\n\tu32 txconfig;\n\tu32 rxconfig;\n};\n\nstruct tg3_firmware_hdr {\n\t__be32 version;\n\t__be32 base_addr;\n\t__be32 len;\n};\n\nstruct tg3_hw_stats {\n\tu8 __reserved0[256];\n\ttg3_stat64_t rx_octets;\n\tu64 __reserved1;\n\ttg3_stat64_t rx_fragments;\n\ttg3_stat64_t rx_ucast_packets;\n\ttg3_stat64_t rx_mcast_packets;\n\ttg3_stat64_t rx_bcast_packets;\n\ttg3_stat64_t rx_fcs_errors;\n\ttg3_stat64_t rx_align_errors;\n\ttg3_stat64_t rx_xon_pause_rcvd;\n\ttg3_stat64_t rx_xoff_pause_rcvd;\n\ttg3_stat64_t rx_mac_ctrl_rcvd;\n\ttg3_stat64_t rx_xoff_entered;\n\ttg3_stat64_t rx_frame_too_long_errors;\n\ttg3_stat64_t rx_jabbers;\n\ttg3_stat64_t rx_undersize_packets;\n\ttg3_stat64_t rx_in_length_errors;\n\ttg3_stat64_t rx_out_length_errors;\n\ttg3_stat64_t rx_64_or_less_octet_packets;\n\ttg3_stat64_t rx_65_to_127_octet_packets;\n\ttg3_stat64_t rx_128_to_255_octet_packets;\n\ttg3_stat64_t rx_256_to_511_octet_packets;\n\ttg3_stat64_t rx_512_to_1023_octet_packets;\n\ttg3_stat64_t rx_1024_to_1522_octet_packets;\n\ttg3_stat64_t rx_1523_to_2047_octet_packets;\n\ttg3_stat64_t rx_2048_to_4095_octet_packets;\n\ttg3_stat64_t rx_4096_to_8191_octet_packets;\n\ttg3_stat64_t rx_8192_to_9022_octet_packets;\n\tu64 __unused0[37];\n\ttg3_stat64_t tx_octets;\n\tu64 __reserved2;\n\ttg3_stat64_t tx_collisions;\n\ttg3_stat64_t tx_xon_sent;\n\ttg3_stat64_t tx_xoff_sent;\n\ttg3_stat64_t tx_flow_control;\n\ttg3_stat64_t tx_mac_errors;\n\ttg3_stat64_t tx_single_collisions;\n\ttg3_stat64_t tx_mult_collisions;\n\ttg3_stat64_t tx_deferred;\n\tu64 __reserved3;\n\ttg3_stat64_t tx_excessive_collisions;\n\ttg3_stat64_t tx_late_collisions;\n\ttg3_stat64_t tx_collide_2times;\n\ttg3_stat64_t tx_collide_3times;\n\ttg3_stat64_t tx_collide_4times;\n\ttg3_stat64_t tx_collide_5times;\n\ttg3_stat64_t tx_collide_6times;\n\ttg3_stat64_t tx_collide_7times;\n\ttg3_stat64_t tx_collide_8times;\n\ttg3_stat64_t tx_collide_9times;\n\ttg3_stat64_t tx_collide_10times;\n\ttg3_stat64_t tx_collide_11times;\n\ttg3_stat64_t tx_collide_12times;\n\ttg3_stat64_t tx_collide_13times;\n\ttg3_stat64_t tx_collide_14times;\n\ttg3_stat64_t tx_collide_15times;\n\ttg3_stat64_t tx_ucast_packets;\n\ttg3_stat64_t tx_mcast_packets;\n\ttg3_stat64_t tx_bcast_packets;\n\ttg3_stat64_t tx_carrier_sense_errors;\n\ttg3_stat64_t tx_discards;\n\ttg3_stat64_t tx_errors;\n\tu64 __unused1[31];\n\ttg3_stat64_t COS_rx_packets[16];\n\ttg3_stat64_t COS_rx_filter_dropped;\n\ttg3_stat64_t dma_writeq_full;\n\ttg3_stat64_t dma_write_prioq_full;\n\ttg3_stat64_t rxbds_empty;\n\ttg3_stat64_t rx_discards;\n\ttg3_stat64_t rx_errors;\n\ttg3_stat64_t rx_threshold_hit;\n\tu64 __unused2[9];\n\ttg3_stat64_t COS_out_packets[16];\n\ttg3_stat64_t dma_readq_full;\n\ttg3_stat64_t dma_read_prioq_full;\n\ttg3_stat64_t tx_comp_queue_full;\n\ttg3_stat64_t ring_set_send_prod_index;\n\ttg3_stat64_t ring_status_update;\n\ttg3_stat64_t nic_irqs;\n\ttg3_stat64_t nic_avoided_irqs;\n\ttg3_stat64_t nic_tx_threshold_hit;\n\ttg3_stat64_t mbuf_lwm_thresh_hit;\n\tu8 __reserved4[312];\n};\n\nstruct tg3_hw_status {\n\tu32 status;\n\tu32 status_tag;\n\tu16 rx_jumbo_consumer;\n\tu16 rx_consumer;\n\tu16 rx_mini_consumer;\n\tu16 reserved;\n\tstruct {\n\t\tu16 rx_producer;\n\t\tu16 tx_consumer;\n\t} idx[16];\n};\n\nstruct tg3_internal_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 nic_mbuf;\n\tu16 len;\n\tu16 cqid_sqid;\n\tu32 flags;\n\tu32 __cookie1;\n\tu32 __cookie2;\n\tu32 __cookie3;\n};\n\nstruct tg3_ocir {\n\tu32 signature;\n\tu16 version_flags;\n\tu16 refresh_int;\n\tu32 refresh_tmr;\n\tu32 update_tmr;\n\tu32 dst_base_addr;\n\tu16 src_hdr_offset;\n\tu16 src_hdr_length;\n\tu16 src_data_offset;\n\tu16 src_data_length;\n\tu16 dst_hdr_offset;\n\tu16 dst_data_offset;\n\tu16 dst_reg_upd_offset;\n\tu16 dst_sem_offset;\n\tu32 reserved1[2];\n\tu32 port0_flags;\n\tu32 port1_flags;\n\tu32 port2_flags;\n\tu32 port3_flags;\n\tu32 reserved2;\n};\n\nstruct tg3_tx_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 len_flags;\n\tu32 vlan_tag;\n};\n\nstruct tg3_tx_ring_info {\n\tstruct sk_buff *skb;\n\tdma_addr_t mapping;\n\tbool fragmented;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct thermal_attr {\n\tstruct device_attribute attr;\n\tchar name[20];\n};\n\ntypedef struct thermal_cooling_device *class_cooling_dev_t;\n\nstruct thermal_cooling_device_ops;\n\nstruct thermal_cooling_device {\n\tint id;\n\tconst char *type;\n\tlong unsigned int max_state;\n\tstruct device device;\n\tstruct device_node *np;\n\tvoid *devdata;\n\tvoid *stats;\n\tconst struct thermal_cooling_device_ops *ops;\n\tbool updated;\n\tstruct mutex lock;\n\tstruct list_head thermal_instances;\n\tstruct list_head node;\n};\n\nstruct thermal_cooling_device_ops {\n\tint (*get_max_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*get_cur_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*set_cur_state)(struct thermal_cooling_device *, long unsigned int);\n\tint (*get_requested_power)(struct thermal_cooling_device *, u32 *);\n\tint (*state2power)(struct thermal_cooling_device *, long unsigned int, u32 *);\n\tint (*power2state)(struct thermal_cooling_device *, u32, long unsigned int *);\n};\n\nstruct thermal_genl_cpu_caps {\n\tint cpu;\n\tint performance;\n\tint efficiency;\n};\n\nstruct thermal_genl_notify {\n\tint mcgrp;\n};\n\nstruct thermal_trip;\n\nstruct thermal_governor {\n\tconst char *name;\n\tint (*bind_to_tz)(struct thermal_zone_device *);\n\tvoid (*unbind_from_tz)(struct thermal_zone_device *);\n\tvoid (*trip_crossed)(struct thermal_zone_device *, const struct thermal_trip *, bool);\n\tvoid (*manage)(struct thermal_zone_device *);\n\tvoid (*update_tz)(struct thermal_zone_device *, enum thermal_notify_event);\n\tstruct list_head governor_list;\n};\n\nstruct thermal_hwmon_attr {\n\tstruct device_attribute attr;\n\tchar name[16];\n};\n\nstruct thermal_hwmon_device {\n\tchar type[20];\n\tstruct device *device;\n\tint count;\n\tstruct list_head tz_list;\n\tstruct list_head node;\n};\n\nstruct thermal_hwmon_temp {\n\tstruct list_head hwmon_node;\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_hwmon_attr temp_input;\n\tstruct thermal_hwmon_attr temp_crit;\n};\n\nstruct thermal_instance {\n\tint id;\n\tchar name[20];\n\tstruct thermal_cooling_device *cdev;\n\tconst struct thermal_trip *trip;\n\tbool initialized;\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tlong unsigned int target;\n\tchar attr_name[20];\n\tstruct device_attribute attr;\n\tchar weight_attr_name[20];\n\tstruct device_attribute weight_attr;\n\tstruct list_head trip_node;\n\tstruct list_head cdev_node;\n\tunsigned int weight;\n\tbool upper_no_limit;\n};\n\nstruct thermal_state {\n\tstruct _thermal_state core_throttle;\n\tstruct _thermal_state core_power_limit;\n\tstruct _thermal_state package_throttle;\n\tstruct _thermal_state package_power_limit;\n\tstruct _thermal_state core_thresh0;\n\tstruct _thermal_state core_thresh1;\n\tstruct _thermal_state pkg_thresh0;\n\tstruct _thermal_state pkg_thresh1;\n};\n\nstruct thermal_trip {\n\tint temperature;\n\tint hysteresis;\n\tenum thermal_trip_type type;\n\tu8 flags;\n\tvoid *priv;\n};\n\nstruct thermal_trip_attrs {\n\tstruct thermal_attr type;\n\tstruct thermal_attr temp;\n\tstruct thermal_attr hyst;\n};\n\nstruct thermal_trip_desc {\n\tstruct thermal_trip trip;\n\tstruct thermal_trip_attrs trip_attrs;\n\tstruct list_head list_node;\n\tstruct list_head thermal_instances;\n\tint threshold;\n};\n\ntypedef struct thermal_zone_device *class_thermal_zone_get_by_id_t;\n\ntypedef struct thermal_zone_device *class_thermal_zone_reverse_t;\n\ntypedef struct thermal_zone_device *class_thermal_zone_t;\n\nstruct thermal_zone_device_ops {\n\tbool (*should_bind)(struct thermal_zone_device *, const struct thermal_trip *, struct thermal_cooling_device *, struct cooling_spec *);\n\tint (*get_temp)(struct thermal_zone_device *, int *);\n\tint (*set_trips)(struct thermal_zone_device *, int, int);\n\tint (*change_mode)(struct thermal_zone_device *, enum thermal_device_mode);\n\tint (*set_trip_temp)(struct thermal_zone_device *, const struct thermal_trip *, int);\n\tint (*get_crit_temp)(struct thermal_zone_device *, int *);\n\tint (*set_emul_temp)(struct thermal_zone_device *, int);\n\tint (*get_trend)(struct thermal_zone_device *, const struct thermal_trip *, enum thermal_trend *);\n\tvoid (*hot)(struct thermal_zone_device *);\n\tvoid (*critical)(struct thermal_zone_device *);\n};\n\nstruct thermal_zone_params;\n\nstruct thermal_zone_device {\n\tint id;\n\tchar type[20];\n\tstruct device device;\n\tstruct completion removal;\n\tstruct completion resume;\n\tstruct attribute_group trips_attribute_group;\n\tstruct list_head trips_high;\n\tstruct list_head trips_reached;\n\tstruct list_head trips_invalid;\n\tenum thermal_device_mode mode;\n\tvoid *devdata;\n\tint num_trips;\n\tlong unsigned int passive_delay_jiffies;\n\tlong unsigned int polling_delay_jiffies;\n\tlong unsigned int recheck_delay_jiffies;\n\tint temperature;\n\tint last_temperature;\n\tint emul_temperature;\n\tint passive;\n\tint prev_low_trip;\n\tint prev_high_trip;\n\tstruct thermal_zone_device_ops ops;\n\tstruct thermal_zone_params *tzp;\n\tstruct thermal_governor *governor;\n\tvoid *governor_data;\n\tstruct ida ida;\n\tstruct mutex lock;\n\tstruct list_head node;\n\tstruct delayed_work poll_queue;\n\tenum thermal_notify_event notify_event;\n\tu8 state;\n\tstruct list_head user_thresholds;\n\tstruct thermal_trip_desc trips[0];\n};\n\nstruct thermal_zone_params {\n\tconst char *governor_name;\n\tbool no_hwmon;\n\tu32 sustainable_power;\n\ts32 k_po;\n\ts32 k_pu;\n\ts32 k_i;\n\ts32 k_d;\n\ts32 integral_cutoff;\n\tint slope;\n\tint offset;\n};\n\nstruct thread_deferred_req {\n\tstruct cache_deferred_req handle;\n\tstruct completion completion;\n};\n\nstruct threshold_block;\n\nstruct thresh_restart {\n\tstruct threshold_block *b;\n\tint set_lvt_off;\n\tint lvt_off;\n\tu16 old_limit;\n};\n\nstruct threshold_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct threshold_block *, char *);\n\tssize_t (*store)(struct threshold_block *, const char *, size_t);\n};\n\nstruct threshold_bank {\n\tstruct kobject *kobj;\n\tstruct list_head miscj;\n};\n\nstruct threshold_block {\n\tunsigned int block;\n\tunsigned int bank;\n\tunsigned int cpu;\n\tu32 address;\n\tbool interrupt_enable;\n\tbool interrupt_capable;\n\tu16 threshold_limit;\n\tstruct kobject kobj;\n\tstruct list_head miscj;\n};\n\nstruct throttling_tstate {\n\tunsigned int cpu;\n\tint target_state;\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct tid_ampdu_rx {\n\tstruct callback_head callback_head;\n\tspinlock_t reorder_lock;\n\tu64 reorder_buf_filtered;\n\tstruct sk_buff_head *reorder_buf;\n\tlong unsigned int *reorder_time;\n\tstruct sta_info *sta;\n\tstruct timer_list session_timer;\n\tstruct timer_list reorder_timer;\n\tlong unsigned int last_rx;\n\tu16 head_seq_num;\n\tu16 stored_mpdu_num;\n\tu16 ssn;\n\tu16 buf_size;\n\tu16 timeout;\n\tu8 tid;\n\tu8 auto_seq: 1;\n\tu8 removed: 1;\n\tu8 started: 1;\n};\n\nstruct tid_ampdu_tx {\n\tstruct callback_head callback_head;\n\tstruct timer_list session_timer;\n\tstruct timer_list addba_resp_timer;\n\tstruct sk_buff_head pending;\n\tstruct sta_info *sta;\n\tlong unsigned int state;\n\tlong unsigned int last_tx;\n\tu16 timeout;\n\tu8 dialog_token;\n\tu8 stop_initiator;\n\tbool tx_stop;\n\tu16 buf_size;\n\tu16 ssn;\n\tu16 failed_bar_ssn;\n\tbool bar_pending;\n\tbool amsdu;\n\tu8 tid;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[9];\n\tstruct hlist_head vectors[576];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timerlat_entry {\n\tstruct trace_entry ent;\n\tunsigned int seqnum;\n\tint context;\n\tu64 timer_latency;\n};\n\nstruct timestamp_event_queue {\n\tstruct ptp_extts_event buf[128];\n\tint head;\n\tint tail;\n\tspinlock_t lock;\n\tstruct list_head qlist;\n\tlong unsigned int *mask;\n\tstruct dentry *debugfs_instance;\n\tstruct debugfs_u32_array dfs_bitmap;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tstruct tk_read_base base[2];\n};\n\nstruct tlb_context {\n\tu64 ctx_id;\n\tu64 tlb_gen;\n};\n\nstruct tlb_state {\n\tstruct mm_struct *loaded_mm;\n\tunion {\n\t\tstruct mm_struct *last_user_mm;\n\t\tlong unsigned int last_user_mm_spec;\n\t};\n\tu16 loaded_mm_asid;\n\tu16 next_asid;\n\tbool invalidate_other;\n\tshort unsigned int user_pcid_flush_mask;\n\tlong unsigned int cr4;\n\tstruct tlb_context ctxs[6];\n};\n\nstruct tlb_state_shared {\n\tbool is_lazy;\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\ntypedef void (*tls_done_func_t)(void *, int, key_serial_t);\n\nstruct tls_handshake_args {\n\tstruct socket *ta_sock;\n\ttls_done_func_t ta_done;\n\tvoid *ta_data;\n\tconst char *ta_peername;\n\tunsigned int ta_timeout_ms;\n\tkey_serial_t ta_keyring;\n\tkey_serial_t ta_my_cert;\n\tkey_serial_t ta_my_privkey;\n\tunsigned int ta_num_peerids;\n\tkey_serial_t ta_my_peerids[5];\n};\n\nstruct tls_handshake_req {\n\tvoid (*th_consumer_done)(void *, int, key_serial_t);\n\tvoid *th_consumer_data;\n\tint th_type;\n\tunsigned int th_timeout_ms;\n\tint th_auth_mode;\n\tconst char *th_peername;\n\tkey_serial_t th_keyring;\n\tkey_serial_t th_certificate;\n\tkey_serial_t th_privkey;\n\tunsigned int th_num_peerids;\n\tkey_serial_t th_peerid[5];\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tu64 now;\n\tbool check;\n};\n\nstruct tmp_ext {\n\tstruct in6_addr daddr;\n\tchar hdrs[0];\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnl_ptk_info {\n\tlong unsigned int flags[1];\n\t__be16 proto;\n\t__be32 key;\n\t__be32 seq;\n\tint hdr_len;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct topa {\n\tstruct list_head list;\n\tu64 offset;\n\tsize_t size;\n\tint last;\n\tunsigned int z_count;\n};\n\nstruct topa_entry {\n\tu64 end: 1;\n\tu64 rsvd0: 1;\n\tu64 intr: 1;\n\tu64 rsvd1: 1;\n\tu64 stop: 1;\n\tu64 rsvd2: 1;\n\tu64 size: 4;\n\tu64 rsvd3: 2;\n\tu64 base: 40;\n\tu64 rsvd4: 12;\n};\n\nstruct topa_page {\n\tstruct topa_entry table[507];\n\tstruct topa topa;\n};\n\nstruct topo_scan {\n\tstruct cpuinfo_x86 *c;\n\tunsigned int dom_shifts[7];\n\tunsigned int dom_ncpus[7];\n\tunsigned int ebx1_nproc_shift;\n\tu16 amd_nodes_per_pkg;\n\tu16 amd_node_id;\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nstruct tp_transition_snapshot {\n\tlong unsigned int rcu;\n\tlong unsigned int srcu_gp;\n\tbool ongoing;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct tpt_led_trigger {\n\tchar name[32];\n\tconst struct ieee80211_tpt_blink *blink_table;\n\tunsigned int blink_table_len;\n\tstruct timer_list timer;\n\tstruct ieee80211_local *local;\n\tlong unsigned int prev_traffic;\n\tlong unsigned int tx_bytes;\n\tlong unsigned int rx_bytes;\n\tunsigned int active;\n\tunsigned int want;\n\tbool running;\n};\n\nstruct trace_module_delta;\n\nstruct trace_pid_list;\n\nstruct tracer_flags;\n\nstruct trace_options;\n\nstruct trace_func_repeats;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tstruct array_buffer array_buffer;\n\tunsigned int mapped;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_size;\n\tchar *range_name;\n\tlong int text_delta;\n\tstruct trace_module_delta *module_delta;\n\tvoid *scratch;\n\tint scratch_size;\n\tint buffer_disabled;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tstruct tracer_flags *current_trace_flags;\n\tu64 trace_flags;\n\tunsigned char trace_flags_index[64];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tconst char *system_names;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct eventfs_inode *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct list_head marker_list;\n\tstruct list_head tracers;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tcpumask_var_t pipe_cpumask;\n\tint ref;\n\tint trace_ref;\n\tstruct list_head mod_events;\n\tint no_filter_buffering_ref;\n\tunsigned int syscall_buf_sz;\n\tstruct list_head hist_vars;\n\tstruct trace_func_repeats *last_func_repeats;\n\tbool ring_buffer_expanded;\n};\n\nstruct trace_array_cpu {\n\tlocal_t disabled;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tbool ignore_pid;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\ntypedef struct trace_buffer *class_ring_buffer_nest_t;\n\nstruct trace_buffer {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tatomic_t resizing;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)(void);\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_end;\n\tstruct ring_buffer_meta *meta;\n\tunsigned int subbuf_size;\n\tunsigned int subbuf_order;\n\tunsigned int max_data_size;\n};\n\nstruct trace_buffer_meta {\n\t__u32 meta_page_size;\n\t__u32 meta_struct_len;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tstruct {\n\t\t__u64 lost_events;\n\t\t__u32 id;\n\t\t__u32 read;\n\t} reader;\n\t__u64 flags;\n\t__u64 entries;\n\t__u64 overrun;\n\t__u64 read;\n\t__u64 Reserved1;\n\t__u64 Reserved2;\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct trace_chandef_entry {\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n};\n\nstruct trace_probe_event;\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_entry_arg *entry_arg;\n\tstruct probe_arg args[0];\n};\n\nstruct trace_eprobe {\n\tconst char *event_system;\n\tconst char *event_name;\n\tchar *filter_str;\n\tstruct trace_event_call *event;\n\tstruct dyn_event devent;\n\tstruct trace_probe tp;\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tunsigned int trace_ctx;\n\tstruct pt_regs *regs;\n};\n\nstruct trace_event_class;\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tconst char *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tunion {\n\t\tvoid *module;\n\t\tatomic_t refcnt;\n\t};\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct trace_event_fields;\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_event_data_offsets_9p_client_req {};\n\nstruct trace_event_data_offsets_9p_client_res {};\n\nstruct trace_event_data_offsets_9p_fid_ref {};\n\nstruct trace_event_data_offsets_9p_protocol_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_alarm_class {};\n\nstruct trace_event_data_offsets_alarmtimer_suspend {};\n\nstruct trace_event_data_offsets_alloc_vmap_area {};\n\nstruct trace_event_data_offsets_amd_pstate_epp_perf {};\n\nstruct trace_event_data_offsets_amd_pstate_perf {};\n\nstruct trace_event_data_offsets_api_beacon_loss {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_chswitch_done {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_connection_loss {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_cqm_rssi_notify {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_disconnect {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_enable_rssi_reports {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_eosp {};\n\nstruct trace_event_data_offsets_api_finalize_rx_omi_bw {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_gtk_rekey_notify {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_prepare_rx_omi_bw {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_radar_detected {};\n\nstruct trace_event_data_offsets_api_request_smps {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_return_bool {};\n\nstruct trace_event_data_offsets_api_return_void {};\n\nstruct trace_event_data_offsets_api_scan_completed {};\n\nstruct trace_event_data_offsets_api_sched_scan_results {};\n\nstruct trace_event_data_offsets_api_sched_scan_stopped {};\n\nstruct trace_event_data_offsets_api_send_eosp_nullfunc {};\n\nstruct trace_event_data_offsets_api_sta_block_awake {};\n\nstruct trace_event_data_offsets_api_sta_set_buffered {};\n\nstruct trace_event_data_offsets_api_start_tx_ba_cb {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_start_tx_ba_session {};\n\nstruct trace_event_data_offsets_api_stop_tx_ba_cb {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_api_stop_tx_ba_session {};\n\nstruct trace_event_data_offsets_ata_bmdma_status {};\n\nstruct trace_event_data_offsets_ata_eh_action_template {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy_qc {};\n\nstruct trace_event_data_offsets_ata_exec_command_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_begin_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_end_template {};\n\nstruct trace_event_data_offsets_ata_port_eh_begin_template {};\n\nstruct trace_event_data_offsets_ata_qc_complete_template {};\n\nstruct trace_event_data_offsets_ata_qc_issue_template {};\n\nstruct trace_event_data_offsets_ata_sff_hsm_template {};\n\nstruct trace_event_data_offsets_ata_sff_template {};\n\nstruct trace_event_data_offsets_ata_tf_load {};\n\nstruct trace_event_data_offsets_ata_transfer_data_template {};\n\nstruct trace_event_data_offsets_azx_get_position {};\n\nstruct trace_event_data_offsets_azx_pcm {};\n\nstruct trace_event_data_offsets_azx_pcm_trigger {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_bl_ext_tree_prepare_commit {};\n\nstruct trace_event_data_offsets_blkdev_zone_mgmt {};\n\nstruct trace_event_data_offsets_block_bio {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_completion {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_zwplug {};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\nstruct trace_event_data_offsets_bpf_trace_printk {\n\tu32 bpf_string;\n\tconst void *bpf_string_ptr_;\n};\n\nstruct trace_event_data_offsets_bpf_trigger_tp {};\n\nstruct trace_event_data_offsets_bpf_xdp_link_attach_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_tag_flush {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_tag_log {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_cap_capable {};\n\nstruct trace_event_data_offsets_cdev_update {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_assoc_comeback {};\n\nstruct trace_event_data_offsets_cfg80211_bss_color_notify {};\n\nstruct trace_event_data_offsets_cfg80211_bss_evt {};\n\nstruct trace_event_data_offsets_cfg80211_cac_event {};\n\nstruct trace_event_data_offsets_cfg80211_ch_switch_notify {};\n\nstruct trace_event_data_offsets_cfg80211_ch_switch_started_notify {};\n\nstruct trace_event_data_offsets_cfg80211_control_port_tx_status {};\n\nstruct trace_event_data_offsets_cfg80211_cqm_pktloss_notify {};\n\nstruct trace_event_data_offsets_cfg80211_cqm_rssi_notify {};\n\nstruct trace_event_data_offsets_cfg80211_epcs_changed {};\n\nstruct trace_event_data_offsets_cfg80211_ft_event {\n\tu32 ies;\n\tconst void *ies_ptr_;\n\tu32 ric_ies;\n\tconst void *ric_ies_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_get_bss {\n\tu32 ssid;\n\tconst void *ssid_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_ibss_joined {};\n\nstruct trace_event_data_offsets_cfg80211_inform_bss_frame {\n\tu32 mgmt;\n\tconst void *mgmt_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_links_removed {};\n\nstruct trace_event_data_offsets_cfg80211_mgmt_tx_status {};\n\nstruct trace_event_data_offsets_cfg80211_michael_mic_failure {};\n\nstruct trace_event_data_offsets_cfg80211_mlo_reconf_add_done {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_nan_cluster_joined {};\n\nstruct trace_event_data_offsets_cfg80211_netdev_mac_evt {};\n\nstruct trace_event_data_offsets_cfg80211_new_sta {};\n\nstruct trace_event_data_offsets_cfg80211_next_nan_dw_notif {};\n\nstruct trace_event_data_offsets_cfg80211_pmksa_candidate_notify {};\n\nstruct trace_event_data_offsets_cfg80211_pmsr_complete {};\n\nstruct trace_event_data_offsets_cfg80211_pmsr_report {};\n\nstruct trace_event_data_offsets_cfg80211_probe_status {};\n\nstruct trace_event_data_offsets_cfg80211_radar_event {};\n\nstruct trace_event_data_offsets_cfg80211_ready_on_channel {};\n\nstruct trace_event_data_offsets_cfg80211_ready_on_channel_expired {};\n\nstruct trace_event_data_offsets_cfg80211_reg_can_beacon {};\n\nstruct trace_event_data_offsets_cfg80211_report_obss_beacon {};\n\nstruct trace_event_data_offsets_cfg80211_report_wowlan_wakeup {\n\tu32 packet;\n\tconst void *packet_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_return_bool {};\n\nstruct trace_event_data_offsets_cfg80211_rx_control_port {};\n\nstruct trace_event_data_offsets_cfg80211_rx_evt {};\n\nstruct trace_event_data_offsets_cfg80211_rx_mgmt {};\n\nstruct trace_event_data_offsets_cfg80211_scan_done {\n\tu32 ie;\n\tconst void *ie_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_send_assoc_failure {};\n\nstruct trace_event_data_offsets_cfg80211_send_rx_assoc {};\n\nstruct trace_event_data_offsets_cfg80211_stop_link {};\n\nstruct trace_event_data_offsets_cfg80211_tdls_oper_request {};\n\nstruct trace_event_data_offsets_cfg80211_tx_mgmt_expired {};\n\nstruct trace_event_data_offsets_cfg80211_tx_mlme_mgmt {\n\tu32 frame;\n\tconst void *frame_ptr_;\n};\n\nstruct trace_event_data_offsets_cfg80211_update_owe_info_event {\n\tu32 ie;\n\tconst void *ie_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tconst void *dst_path_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_rstat {};\n\nstruct trace_event_data_offsets_chanswitch_evt {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_compact_retry {};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_contention_begin {};\n\nstruct trace_event_data_offsets_contention_end {};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_cpu_idle_miss {};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_csd_function {};\n\nstruct trace_event_data_offsets_csd_queue_cpu {};\n\nstruct trace_event_data_offsets_ctime {};\n\nstruct trace_event_data_offsets_ctime_ns_xchg {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_end {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_start {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 parent;\n\tconst void *parent_ptr_;\n\tu32 pm_ops;\n\tconst void *pm_ops_ptr_;\n};\n\nstruct trace_event_data_offsets_devres {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_attach_dev {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_fd {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence_unsignaled {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg_err {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_single {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 addrs;\n\tconst void *addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dql_stall_detected {};\n\nstruct trace_event_data_offsets_drm_vblank_event {};\n\nstruct trace_event_data_offsets_drm_vblank_event_delivered {};\n\nstruct trace_event_data_offsets_drm_vblank_event_queued {};\n\nstruct trace_event_data_offsets_drv_add_nan_func {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_add_twt_setup {};\n\nstruct trace_event_data_offsets_drv_ampdu_action {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_can_activate_links {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_can_neg_ttlm {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_change_chanctx {};\n\nstruct trace_event_data_offsets_drv_change_interface {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_change_sta_links {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_change_vif_links {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_channel_switch_beacon {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_conf_tx {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_config {};\n\nstruct trace_event_data_offsets_drv_config_iface_filter {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_configure_filter {};\n\nstruct trace_event_data_offsets_drv_del_nan_func {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_event_callback {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_flush {};\n\nstruct trace_event_data_offsets_drv_get_antenna {};\n\nstruct trace_event_data_offsets_drv_get_expected_throughput {};\n\nstruct trace_event_data_offsets_drv_get_ftm_responder_stats {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_get_key_seq {};\n\nstruct trace_event_data_offsets_drv_get_ringparam {};\n\nstruct trace_event_data_offsets_drv_get_stats {};\n\nstruct trace_event_data_offsets_drv_get_survey {};\n\nstruct trace_event_data_offsets_drv_get_txpower {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_join_ibss {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n\tu32 ssid;\n\tconst void *ssid_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_link_info_changed {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_link_sta_rc_update {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_link_sta_statistics {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_nan_change_conf {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_neg_ttlm_res {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_net_setup_tc {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_offset_tsf {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_prep_add_interface {};\n\nstruct trace_event_data_offsets_drv_prepare_multicast {};\n\nstruct trace_event_data_offsets_drv_reconfig_complete {};\n\nstruct trace_event_data_offsets_drv_remain_on_channel {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_return_bool {};\n\nstruct trace_event_data_offsets_drv_return_int {};\n\nstruct trace_event_data_offsets_drv_return_u32 {};\n\nstruct trace_event_data_offsets_drv_return_u64 {};\n\nstruct trace_event_data_offsets_drv_set_antenna {};\n\nstruct trace_event_data_offsets_drv_set_bitrate_mask {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_set_coverage_class {};\n\nstruct trace_event_data_offsets_drv_set_default_unicast_key {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_set_eml_op_mode {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_set_frag_threshold {};\n\nstruct trace_event_data_offsets_drv_set_key {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_set_rekey_data {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_set_ringparam {};\n\nstruct trace_event_data_offsets_drv_set_rts_threshold {};\n\nstruct trace_event_data_offsets_drv_set_tim {};\n\nstruct trace_event_data_offsets_drv_set_tsf {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_set_wakeup {};\n\nstruct trace_event_data_offsets_drv_sta_notify {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_sta_set_txpwr {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_sta_state {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_start_ap {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n\tu32 ssid;\n\tconst void *ssid_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_start_nan {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_stop {};\n\nstruct trace_event_data_offsets_drv_stop_ap {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_stop_nan {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_sw_scan_start {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_switch_vif_chanctx {\n\tu32 vifs;\n\tconst void *vifs_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_tdls_cancel_channel_switch {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_tdls_channel_switch {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_tdls_recv_channel_switch {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_twt_teardown_request {};\n\nstruct trace_event_data_offsets_drv_update_tkip_key {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_vif_cfg_changed {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n\tu32 arp_addr_list;\n\tconst void *arp_addr_list_ptr_;\n\tu32 ssid;\n\tconst void *ssid_ptr_;\n};\n\nstruct trace_event_data_offsets_drv_wake_tx_queue {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_e1000e_trace_mac_register {};\n\nstruct trace_event_data_offsets_emulate_vsyscall {};\n\nstruct trace_event_data_offsets_error_report_template {};\n\nstruct trace_event_data_offsets_exceptions {};\n\nstruct trace_event_data_offsets_exit_mmap {};\n\nstruct trace_event_data_offsets_ext4__bitmap_load {};\n\nstruct trace_event_data_offsets_ext4__es_extent {};\n\nstruct trace_event_data_offsets_ext4__es_shrink_enter {};\n\nstruct trace_event_data_offsets_ext4__fallocate_mode {};\n\nstruct trace_event_data_offsets_ext4__folio_op {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_enter {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_exit {};\n\nstruct trace_event_data_offsets_ext4__mb_new_pa {};\n\nstruct trace_event_data_offsets_ext4__mballoc {};\n\nstruct trace_event_data_offsets_ext4__trim {};\n\nstruct trace_event_data_offsets_ext4__truncate {};\n\nstruct trace_event_data_offsets_ext4__write_begin {};\n\nstruct trace_event_data_offsets_ext4__write_end {};\n\nstruct trace_event_data_offsets_ext4_alloc_da_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_inode {};\n\nstruct trace_event_data_offsets_ext4_begin_ordered_truncate {};\n\nstruct trace_event_data_offsets_ext4_collapse_range {};\n\nstruct trace_event_data_offsets_ext4_da_release_space {};\n\nstruct trace_event_data_offsets_ext4_da_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_update_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_end {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_start {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages_extent {};\n\nstruct trace_event_data_offsets_ext4_discard_blocks {};\n\nstruct trace_event_data_offsets_ext4_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_drop_inode {};\n\nstruct trace_event_data_offsets_ext4_error {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_enter {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_exit {};\n\nstruct trace_event_data_offsets_ext4_es_insert_delayed_extent {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_es_remove_extent {};\n\nstruct trace_event_data_offsets_ext4_es_shrink {};\n\nstruct trace_event_data_offsets_ext4_es_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_ext4_evict_inode {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_enter {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_fastpath {};\n\nstruct trace_event_data_offsets_ext4_ext_handle_unwritten_extents {};\n\nstruct trace_event_data_offsets_ext4_ext_load_extent {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space_done {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_idx {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_leaf {};\n\nstruct trace_event_data_offsets_ext4_ext_show_extent {};\n\nstruct trace_event_data_offsets_ext4_fallocate_exit {};\n\nstruct trace_event_data_offsets_ext4_fc_cleanup {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_start {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_stop {};\n\nstruct trace_event_data_offsets_ext4_fc_replay {};\n\nstruct trace_event_data_offsets_ext4_fc_replay_scan {};\n\nstruct trace_event_data_offsets_ext4_fc_stats {};\n\nstruct trace_event_data_offsets_ext4_fc_track_dentry {};\n\nstruct trace_event_data_offsets_ext4_fc_track_inode {};\n\nstruct trace_event_data_offsets_ext4_fc_track_range {};\n\nstruct trace_event_data_offsets_ext4_forget {};\n\nstruct trace_event_data_offsets_ext4_free_blocks {};\n\nstruct trace_event_data_offsets_ext4_free_inode {};\n\nstruct trace_event_data_offsets_ext4_fsmap_class {};\n\nstruct trace_event_data_offsets_ext4_get_implied_cluster_alloc_exit {};\n\nstruct trace_event_data_offsets_ext4_getfsmap_class {};\n\nstruct trace_event_data_offsets_ext4_insert_range {};\n\nstruct trace_event_data_offsets_ext4_invalidate_folio_op {};\n\nstruct trace_event_data_offsets_ext4_journal_start_inode {};\n\nstruct trace_event_data_offsets_ext4_journal_start_reserved {};\n\nstruct trace_event_data_offsets_ext4_journal_start_sb {};\n\nstruct trace_event_data_offsets_ext4_lazy_itable_init {};\n\nstruct trace_event_data_offsets_ext4_load_inode {};\n\nstruct trace_event_data_offsets_ext4_mark_inode_dirty {};\n\nstruct trace_event_data_offsets_ext4_mb_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_mb_release_group_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_inode_pa {};\n\nstruct trace_event_data_offsets_ext4_mballoc_alloc {};\n\nstruct trace_event_data_offsets_ext4_mballoc_prealloc {};\n\nstruct trace_event_data_offsets_ext4_move_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_move_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_nfs_commit_metadata {};\n\nstruct trace_event_data_offsets_ext4_other_inode_update_time {};\n\nstruct trace_event_data_offsets_ext4_prefetch_bitmaps {};\n\nstruct trace_event_data_offsets_ext4_read_block_bitmap_load {};\n\nstruct trace_event_data_offsets_ext4_remove_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_inode {};\n\nstruct trace_event_data_offsets_ext4_shutdown {};\n\nstruct trace_event_data_offsets_ext4_sync_file_enter {};\n\nstruct trace_event_data_offsets_ext4_sync_file_exit {};\n\nstruct trace_event_data_offsets_ext4_sync_fs {};\n\nstruct trace_event_data_offsets_ext4_unlink_enter {};\n\nstruct trace_event_data_offsets_ext4_unlink_exit {};\n\nstruct trace_event_data_offsets_ext4_update_sb {};\n\nstruct trace_event_data_offsets_ext4_writepages {};\n\nstruct trace_event_data_offsets_ext4_writepages_result {};\n\nstruct trace_event_data_offsets_ff_layout_commit_error {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_fib6_table_lookup {};\n\nstruct trace_event_data_offsets_fib_table_lookup {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_fill_mg_cmtime {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_fl_getdevinfo {\n\tu32 mds_addr;\n\tconst void *mds_addr_ptr_;\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_free_vmap_area_noflush {};\n\nstruct trace_event_data_offsets_g4x_wm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_guest_halt_poll_ns {};\n\nstruct trace_event_data_offsets_handshake_alert_class {};\n\nstruct trace_event_data_offsets_handshake_complete {};\n\nstruct trace_event_data_offsets_handshake_error_class {};\n\nstruct trace_event_data_offsets_handshake_event_class {};\n\nstruct trace_event_data_offsets_handshake_fd_class {};\n\nstruct trace_event_data_offsets_hda_get_response {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_hda_pm {};\n\nstruct trace_event_data_offsets_hda_send_cmd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_hda_unsol_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_hdac_stream {};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_setup {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hugetlbfs__inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_alloc_inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_fallocate {};\n\nstruct trace_event_data_offsets_hugetlbfs_setattr {\n\tu32 d_name;\n\tconst void *d_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_class {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_show_string {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_read {};\n\nstruct trace_event_data_offsets_i2c_reply {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_result {};\n\nstruct trace_event_data_offsets_i2c_write {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i915_context {};\n\nstruct trace_event_data_offsets_i915_gem_evict {};\n\nstruct trace_event_data_offsets_i915_gem_evict_node {};\n\nstruct trace_event_data_offsets_i915_gem_evict_vm {};\n\nstruct trace_event_data_offsets_i915_gem_object {};\n\nstruct trace_event_data_offsets_i915_gem_object_create {};\n\nstruct trace_event_data_offsets_i915_gem_object_fault {};\n\nstruct trace_event_data_offsets_i915_gem_object_pread {};\n\nstruct trace_event_data_offsets_i915_gem_object_pwrite {};\n\nstruct trace_event_data_offsets_i915_gem_shrink {};\n\nstruct trace_event_data_offsets_i915_ppgtt {};\n\nstruct trace_event_data_offsets_i915_reg_rw {};\n\nstruct trace_event_data_offsets_i915_request {};\n\nstruct trace_event_data_offsets_i915_request_queue {};\n\nstruct trace_event_data_offsets_i915_request_wait_begin {};\n\nstruct trace_event_data_offsets_i915_vma_bind {};\n\nstruct trace_event_data_offsets_i915_vma_unbind {};\n\nstruct trace_event_data_offsets_icmp_send {};\n\nstruct trace_event_data_offsets_inet_sk_error_report {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n\tconst void *level_ptr_;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_intel_cpu_fifo_underrun {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_crtc_flip_done {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_crtc_vblank_work_end {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_crtc_vblank_work_start {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_fbc_activate {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_fbc_deactivate {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_fbc_nuke {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_frontbuffer_flush {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_frontbuffer_invalidate {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_memory_cxsr {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pch_fifo_underrun {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_crc {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_disable {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_enable {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_scaler_update_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_update_end {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_update_start {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_pipe_update_vblank_evaded {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_async_flip {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_disable_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_scaler_update_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_update_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_plane_update_noarm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_intel_scaler_disable_arm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_cqe_overflow {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_defer {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_fail_link {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_local_work_run {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_req_failed {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_short_write {};\n\nstruct trace_event_data_offsets_io_uring_submit_req {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_add {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_work_run {};\n\nstruct trace_event_data_offsets_iocg_inuse_update {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_ioc_vrate_adj {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_iocg_forgive_debt {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iocost_iocg_state {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 cgroup;\n\tconst void *cgroup_ptr_;\n};\n\nstruct trace_event_data_offsets_iomap_add_to_ioend {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_dio_complete {};\n\nstruct trace_event_data_offsets_iomap_dio_rw_begin {};\n\nstruct trace_event_data_offsets_iomap_iter {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_send_cpu {};\n\nstruct trace_event_data_offsets_ipi_send_cpumask {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_irq_matrix_cpu {};\n\nstruct trace_event_data_offsets_irq_matrix_global {};\n\nstruct trace_event_data_offsets_irq_matrix_global_update {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint_stats {};\n\nstruct trace_event_data_offsets_jbd2_commit {};\n\nstruct trace_event_data_offsets_jbd2_end_commit {};\n\nstruct trace_event_data_offsets_jbd2_handle_extend {};\n\nstruct trace_event_data_offsets_jbd2_handle_start_class {};\n\nstruct trace_event_data_offsets_jbd2_handle_stats {};\n\nstruct trace_event_data_offsets_jbd2_journal_shrink {};\n\nstruct trace_event_data_offsets_jbd2_lock_buffer_stall {};\n\nstruct trace_event_data_offsets_jbd2_run_stats {};\n\nstruct trace_event_data_offsets_jbd2_shrink_checkpoint_list {};\n\nstruct trace_event_data_offsets_jbd2_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_jbd2_submit_inode_data {};\n\nstruct trace_event_data_offsets_jbd2_update_log_tail {};\n\nstruct trace_event_data_offsets_jbd2_write_superblock {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\nstruct trace_event_data_offsets_key_handle {};\n\nstruct trace_event_data_offsets_kfree {};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_kmalloc {};\n\nstruct trace_event_data_offsets_kmem_cache_alloc {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kmem_cache_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\nstruct trace_event_data_offsets_link_station_add_mod {\n\tu32 supported_rates;\n\tconst void *supported_rates_ptr_;\n\tu32 he_capa;\n\tconst void *he_capa_ptr_;\n\tu32 eht_capa;\n\tconst void *eht_capa_ptr_;\n};\n\nstruct trace_event_data_offsets_local_chanctx {};\n\nstruct trace_event_data_offsets_local_only_evt {};\n\nstruct trace_event_data_offsets_local_sdata_addr_evt {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_local_sdata_chanctx {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_local_sdata_evt {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_local_u32_evt {};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_ma_op {};\n\nstruct trace_event_data_offsets_ma_read {};\n\nstruct trace_event_data_offsets_ma_write {};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_mark_victim {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_mce_record {\n\tu32 v_data;\n\tconst void *v_data_ptr_;\n};\n\nstruct trace_event_data_offsets_mdio_access {};\n\nstruct trace_event_data_offsets_mei_pci_cfg_read {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 reg;\n\tconst void *reg_ptr_;\n};\n\nstruct trace_event_data_offsets_mei_reg_read {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 reg;\n\tconst void *reg_ptr_;\n};\n\nstruct trace_event_data_offsets_mei_reg_write {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 reg;\n\tconst void *reg_ptr_;\n};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_mgd_prepare_complete_tx_evt {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_migration_pte {};\n\nstruct trace_event_data_offsets_mm_calculate_totalreserve_pages {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_filemap_fault {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache_range {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\nstruct trace_event_data_offsets_mm_migrate_pages_start {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_lowmem_reserve {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 upper_name;\n\tconst void *upper_name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_wmarks {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_clear_hopeless {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_reclaim_fail {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\nstruct trace_event_data_offsets_mm_vmscan_reclaim_pages {};\n\nstruct trace_event_data_offsets_mm_vmscan_throttled {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_write_folio {};\n\nstruct trace_event_data_offsets_mmap_lock {};\n\nstruct trace_event_data_offsets_mmap_lock_acquire_returned {};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mpath_evt {};\n\nstruct trace_event_data_offsets_msr_trace_class {};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_netdev_frame_event {\n\tu32 frame;\n\tconst void *frame_ptr_;\n};\n\nstruct trace_event_data_offsets_netdev_mac_evt {};\n\nstruct trace_event_data_offsets_netfs_collect {};\n\nstruct trace_event_data_offsets_netfs_collect_folio {};\n\nstruct trace_event_data_offsets_netfs_collect_gap {};\n\nstruct trace_event_data_offsets_netfs_collect_sreq {};\n\nstruct trace_event_data_offsets_netfs_collect_state {};\n\nstruct trace_event_data_offsets_netfs_collect_stream {};\n\nstruct trace_event_data_offsets_netfs_copy2cache {};\n\nstruct trace_event_data_offsets_netfs_failure {};\n\nstruct trace_event_data_offsets_netfs_folio {};\n\nstruct trace_event_data_offsets_netfs_folioq {};\n\nstruct trace_event_data_offsets_netfs_read {};\n\nstruct trace_event_data_offsets_netfs_rreq {};\n\nstruct trace_event_data_offsets_netfs_rreq_ref {};\n\nstruct trace_event_data_offsets_netfs_sreq {};\n\nstruct trace_event_data_offsets_netfs_sreq_ref {};\n\nstruct trace_event_data_offsets_netfs_write {};\n\nstruct trace_event_data_offsets_netfs_write_iter {};\n\nstruct trace_event_data_offsets_netlink_extack {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_cached_open {};\n\nstruct trace_event_data_offsets_nfs4_cb_error_class {};\n\nstruct trace_event_data_offsets_nfs4_cb_offload {};\n\nstruct trace_event_data_offsets_nfs4_cb_seqid_err {};\n\nstruct trace_event_data_offsets_nfs4_cb_sequence {};\n\nstruct trace_event_data_offsets_nfs4_clientid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_close {};\n\nstruct trace_event_data_offsets_nfs4_commit_event {};\n\nstruct trace_event_data_offsets_nfs4_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_delegreturn_exit {};\n\nstruct trace_event_data_offsets_nfs4_deviceid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_deviceid_status {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_flexfiles_io_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_getattr_event {};\n\nstruct trace_event_data_offsets_nfs4_idmap_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_event {};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_layoutget {};\n\nstruct trace_event_data_offsets_nfs4_lock_event {};\n\nstruct trace_event_data_offsets_nfs4_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_lookupp {};\n\nstruct trace_event_data_offsets_nfs4_match_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_open_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_read_event {};\n\nstruct trace_event_data_offsets_nfs4_rename {\n\tu32 oldname;\n\tconst void *oldname_ptr_;\n\tu32 newname;\n\tconst void *newname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_sequence_done {};\n\nstruct trace_event_data_offsets_nfs4_set_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_set_lock {};\n\nstruct trace_event_data_offsets_nfs4_setup_sequence {};\n\nstruct trace_event_data_offsets_nfs4_state_lock_reclaim {};\n\nstruct trace_event_data_offsets_nfs4_state_mgr {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_state_mgr_failed {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n\tu32 section;\n\tconst void *section_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_test_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_trunked_exchange_id {\n\tu32 main_addr;\n\tconst void *main_addr_ptr_;\n\tu32 trunk_addr;\n\tconst void *trunk_addr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_write_event {};\n\nstruct trace_event_data_offsets_nfs4_xdr_bad_operation {};\n\nstruct trace_event_data_offsets_nfs4_xdr_event {};\n\nstruct trace_event_data_offsets_nfs_access_exit {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead_done {};\n\nstruct trace_event_data_offsets_nfs_atomic_open_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_atomic_open_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_commit_done {};\n\nstruct trace_event_data_offsets_nfs_create_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_create_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_direct_req_class {};\n\nstruct trace_event_data_offsets_nfs_directory_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_directory_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_fh_to_dentry {};\n\nstruct trace_event_data_offsets_nfs_folio_event {};\n\nstruct trace_event_data_offsets_nfs_folio_event_done {};\n\nstruct trace_event_data_offsets_nfs_initiate_commit {};\n\nstruct trace_event_data_offsets_nfs_initiate_read {};\n\nstruct trace_event_data_offsets_nfs_initiate_write {};\n\nstruct trace_event_data_offsets_nfs_inode_event {};\n\nstruct trace_event_data_offsets_nfs_inode_event_done {};\n\nstruct trace_event_data_offsets_nfs_inode_range_event {};\n\nstruct trace_event_data_offsets_nfs_kiocb_event {};\n\nstruct trace_event_data_offsets_nfs_link_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_link_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_local_open_fh {};\n\nstruct trace_event_data_offsets_nfs_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_lookup_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_assign {\n\tu32 option;\n\tconst void *option_ptr_;\n\tu32 value;\n\tconst void *value_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_option {\n\tu32 option;\n\tconst void *option_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_path {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_page_class {};\n\nstruct trace_event_data_offsets_nfs_page_error_class {};\n\nstruct trace_event_data_offsets_nfs_pgio_error {};\n\nstruct trace_event_data_offsets_nfs_readdir_event {};\n\nstruct trace_event_data_offsets_nfs_readpage_done {};\n\nstruct trace_event_data_offsets_nfs_readpage_short {};\n\nstruct trace_event_data_offsets_nfs_rename_event {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_rename_event_done {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_sillyrename_unlink {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_update_size_class {};\n\nstruct trace_event_data_offsets_nfs_writeback_done {};\n\nstruct trace_event_data_offsets_nfs_xdr_event {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_nlmclnt_lock_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_nmi_handler {};\n\nstruct trace_event_data_offsets_notifier_info {};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_page_cache_ra_op {};\n\nstruct trace_event_data_offsets_page_cache_ra_order {};\n\nstruct trace_event_data_offsets_page_cache_ra_unbounded {};\n\nstruct trace_event_data_offsets_page_pool_release {};\n\nstruct trace_event_data_offsets_page_pool_state_hold {};\n\nstruct trace_event_data_offsets_page_pool_state_release {};\n\nstruct trace_event_data_offsets_page_pool_update_nid {};\n\nstruct trace_event_data_offsets_pci_hp_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n\tu32 slot;\n\tconst void *slot_ptr_;\n};\n\nstruct trace_event_data_offsets_pcie_link_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_pmap_register {};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_err_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_ds_connect {\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_layout_event {};\n\nstruct trace_event_data_offsets_pnfs_update_layout {};\n\nstruct trace_event_data_offsets_prq_report {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 buff;\n\tconst void *buff_ptr_;\n};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_purge_vmap_area_lazy {};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_enqueue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qi_submit {\n\tu32 iommu;\n\tconst void *iommu_ptr_;\n};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kvfree_callback {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_segcb_stats {};\n\nstruct trace_event_data_offsets_rcu_sr_normal {};\n\nstruct trace_event_data_offsets_rcu_stall_warning {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_watching {};\n\nstruct trace_event_data_offsets_rdev_add_key {};\n\nstruct trace_event_data_offsets_rdev_add_nan_func {};\n\nstruct trace_event_data_offsets_rdev_add_tx_ts {};\n\nstruct trace_event_data_offsets_rdev_add_virtual_intf {\n\tu32 vir_intf_name;\n\tconst void *vir_intf_name_ptr_;\n};\n\nstruct trace_event_data_offsets_rdev_assoc {\n\tu32 elements;\n\tconst void *elements_ptr_;\n\tu32 fils_kek;\n\tconst void *fils_kek_ptr_;\n\tu32 fils_nonces;\n\tconst void *fils_nonces_ptr_;\n};\n\nstruct trace_event_data_offsets_rdev_assoc_ml_reconf {};\n\nstruct trace_event_data_offsets_rdev_auth {};\n\nstruct trace_event_data_offsets_rdev_cancel_remain_on_channel {};\n\nstruct trace_event_data_offsets_rdev_change_beacon {\n\tu32 head;\n\tconst void *head_ptr_;\n\tu32 tail;\n\tconst void *tail_ptr_;\n\tu32 beacon_ies;\n\tconst void *beacon_ies_ptr_;\n\tu32 proberesp_ies;\n\tconst void *proberesp_ies_ptr_;\n\tu32 assocresp_ies;\n\tconst void *assocresp_ies_ptr_;\n\tu32 probe_resp;\n\tconst void *probe_resp_ptr_;\n};\n\nstruct trace_event_data_offsets_rdev_change_bss {};\n\nstruct trace_event_data_offsets_rdev_change_virtual_intf {};\n\nstruct trace_event_data_offsets_rdev_channel_switch {\n\tu32 bcn_ofs;\n\tconst void *bcn_ofs_ptr_;\n\tu32 pres_ofs;\n\tconst void *pres_ofs_ptr_;\n};\n\nstruct trace_event_data_offsets_rdev_color_change {};\n\nstruct trace_event_data_offsets_rdev_connect {};\n\nstruct trace_event_data_offsets_rdev_crit_proto_start {};\n\nstruct trace_event_data_offsets_rdev_crit_proto_stop {};\n\nstruct trace_event_data_offsets_rdev_deauth {};\n\nstruct trace_event_data_offsets_rdev_del_link_station {};\n\nstruct trace_event_data_offsets_rdev_del_nan_func {};\n\nstruct trace_event_data_offsets_rdev_del_pmk {};\n\nstruct trace_event_data_offsets_rdev_del_tx_ts {};\n\nstruct trace_event_data_offsets_rdev_disassoc {};\n\nstruct trace_event_data_offsets_rdev_disconnect {};\n\nstruct trace_event_data_offsets_rdev_dump_mpath {};\n\nstruct trace_event_data_offsets_rdev_dump_mpp {};\n\nstruct trace_event_data_offsets_rdev_dump_station {};\n\nstruct trace_event_data_offsets_rdev_dump_survey {};\n\nstruct trace_event_data_offsets_rdev_end_cac {};\n\nstruct trace_event_data_offsets_rdev_external_auth {};\n\nstruct trace_event_data_offsets_rdev_get_antenna {};\n\nstruct trace_event_data_offsets_rdev_get_ftm_responder_stats {};\n\nstruct trace_event_data_offsets_rdev_get_mpp {};\n\nstruct trace_event_data_offsets_rdev_get_tx_power {};\n\nstruct trace_event_data_offsets_rdev_inform_bss {};\n\nstruct trace_event_data_offsets_rdev_join_ibss {};\n\nstruct trace_event_data_offsets_rdev_join_mesh {};\n\nstruct trace_event_data_offsets_rdev_join_ocb {};\n\nstruct trace_event_data_offsets_rdev_libertas_set_mesh_channel {};\n\nstruct trace_event_data_offsets_rdev_mgmt_tx {};\n\nstruct trace_event_data_offsets_rdev_mgmt_tx_cancel_wait {};\n\nstruct trace_event_data_offsets_rdev_nan_change_conf {};\n\nstruct trace_event_data_offsets_rdev_pmksa {};\n\nstruct trace_event_data_offsets_rdev_probe_client {};\n\nstruct trace_event_data_offsets_rdev_probe_mesh_link {};\n\nstruct trace_event_data_offsets_rdev_remain_on_channel {};\n\nstruct trace_event_data_offsets_rdev_reset_tid_config {};\n\nstruct trace_event_data_offsets_rdev_return_chandef {};\n\nstruct trace_event_data_offsets_rdev_return_int {};\n\nstruct trace_event_data_offsets_rdev_return_int_cookie {};\n\nstruct trace_event_data_offsets_rdev_return_int_int {};\n\nstruct trace_event_data_offsets_rdev_return_int_mesh_config {};\n\nstruct trace_event_data_offsets_rdev_return_int_mpath_info {};\n\nstruct trace_event_data_offsets_rdev_return_int_station_info {};\n\nstruct trace_event_data_offsets_rdev_return_int_survey_info {};\n\nstruct trace_event_data_offsets_rdev_return_int_tx_rx {};\n\nstruct trace_event_data_offsets_rdev_return_void_tx_rx {};\n\nstruct trace_event_data_offsets_rdev_scan {};\n\nstruct trace_event_data_offsets_rdev_set_antenna {};\n\nstruct trace_event_data_offsets_rdev_set_ap_chanwidth {};\n\nstruct trace_event_data_offsets_rdev_set_bitrate_mask {};\n\nstruct trace_event_data_offsets_rdev_set_coalesce {};\n\nstruct trace_event_data_offsets_rdev_set_cqm_rssi_config {};\n\nstruct trace_event_data_offsets_rdev_set_cqm_rssi_range_config {};\n\nstruct trace_event_data_offsets_rdev_set_cqm_txe_config {};\n\nstruct trace_event_data_offsets_rdev_set_default_beacon_key {};\n\nstruct trace_event_data_offsets_rdev_set_default_key {};\n\nstruct trace_event_data_offsets_rdev_set_default_mgmt_key {};\n\nstruct trace_event_data_offsets_rdev_set_epcs {};\n\nstruct trace_event_data_offsets_rdev_set_fils_aad {};\n\nstruct trace_event_data_offsets_rdev_set_hw_timestamp {};\n\nstruct trace_event_data_offsets_rdev_set_mac_acl {};\n\nstruct trace_event_data_offsets_rdev_set_mcast_rate {};\n\nstruct trace_event_data_offsets_rdev_set_monitor_channel {};\n\nstruct trace_event_data_offsets_rdev_set_multicast_to_unicast {};\n\nstruct trace_event_data_offsets_rdev_set_noack_map {};\n\nstruct trace_event_data_offsets_rdev_set_pmk {\n\tu32 pmk;\n\tconst void *pmk_ptr_;\n\tu32 pmk_r0_name;\n\tconst void *pmk_r0_name_ptr_;\n};\n\nstruct trace_event_data_offsets_rdev_set_power_mgmt {};\n\nstruct trace_event_data_offsets_rdev_set_qos_map {};\n\nstruct trace_event_data_offsets_rdev_set_radar_background {};\n\nstruct trace_event_data_offsets_rdev_set_sar_specs {};\n\nstruct trace_event_data_offsets_rdev_set_tid_config {};\n\nstruct trace_event_data_offsets_rdev_set_ttlm {};\n\nstruct trace_event_data_offsets_rdev_set_tx_power {};\n\nstruct trace_event_data_offsets_rdev_set_txq_params {};\n\nstruct trace_event_data_offsets_rdev_set_wiphy_params {};\n\nstruct trace_event_data_offsets_rdev_start_ap {};\n\nstruct trace_event_data_offsets_rdev_start_nan {};\n\nstruct trace_event_data_offsets_rdev_start_radar_detection {};\n\nstruct trace_event_data_offsets_rdev_stop_ap {};\n\nstruct trace_event_data_offsets_rdev_suspend {};\n\nstruct trace_event_data_offsets_rdev_tdls_cancel_channel_switch {};\n\nstruct trace_event_data_offsets_rdev_tdls_channel_switch {};\n\nstruct trace_event_data_offsets_rdev_tdls_mgmt {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_rdev_tdls_oper {};\n\nstruct trace_event_data_offsets_rdev_tx_control_port {};\n\nstruct trace_event_data_offsets_rdev_update_connect_params {};\n\nstruct trace_event_data_offsets_rdev_update_ft_ies {\n\tu32 ie;\n\tconst void *ie_ptr_;\n};\n\nstruct trace_event_data_offsets_rdev_update_mesh_config {};\n\nstruct trace_event_data_offsets_rdev_update_mgmt_frame_registrations {};\n\nstruct trace_event_data_offsets_rdev_update_owe_info {\n\tu32 ie;\n\tconst void *ie_ptr_;\n};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_regcache_drop_region {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regcache_sync {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 status;\n\tconst void *status_ptr_;\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_register_class {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_async {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bool {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bulk {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_reg {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_release_evt {};\n\nstruct trace_event_data_offsets_rpc_buf_alloc {};\n\nstruct trace_event_data_offsets_rpc_call_rpcerror {};\n\nstruct trace_event_data_offsets_rpc_clnt_class {};\n\nstruct trace_event_data_offsets_rpc_clnt_clone_err {};\n\nstruct trace_event_data_offsets_rpc_clnt_new {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_clnt_new_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_failure {};\n\nstruct trace_event_data_offsets_rpc_reply_event {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_request {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_socket_nospace {};\n\nstruct trace_event_data_offsets_rpc_stats_latency {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_queued {\n\tu32 q_name;\n\tconst void *q_name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_running {};\n\nstruct trace_event_data_offsets_rpc_task_status {};\n\nstruct trace_event_data_offsets_rpc_tls_class {\n\tu32 servername;\n\tconst void *servername_ptr_;\n\tu32 progname;\n\tconst void *progname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_alignment {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_rpc_xdr_overflow {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_lifetime_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_getport {\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_register {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_setport {};\n\nstruct trace_event_data_offsets_rpcb_unregister {\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_bad_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_context {\n\tu32 acceptor;\n\tconst void *acceptor_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_createauth {};\n\nstruct trace_event_data_offsets_rpcgss_ctx_class {\n\tu32 principal;\n\tconst void *principal_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_gssapi_event {};\n\nstruct trace_event_data_offsets_rpcgss_import_ctx {};\n\nstruct trace_event_data_offsets_rpcgss_need_reencode {};\n\nstruct trace_event_data_offsets_rpcgss_oid_to_mech {\n\tu32 oid;\n\tconst void *oid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_svc_accept_upcall {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_authenticate {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_gssapi_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_bad {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_class {};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_low {};\n\nstruct trace_event_data_offsets_rpcgss_svc_unwrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_wrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_unwrap_failed {};\n\nstruct trace_event_data_offsets_rpcgss_upcall_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_upcall_result {};\n\nstruct trace_event_data_offsets_rpcgss_update_slack {};\n\nstruct trace_event_data_offsets_rpm_internal {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_return_int {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_status {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\nstruct trace_event_data_offsets_rtc_alarm_irq_enable {};\n\nstruct trace_event_data_offsets_rtc_irq_set_freq {};\n\nstruct trace_event_data_offsets_rtc_irq_set_state {};\n\nstruct trace_event_data_offsets_rtc_offset_class {};\n\nstruct trace_event_data_offsets_rtc_time_alarm_class {};\n\nstruct trace_event_data_offsets_rtc_timer_class {};\n\nstruct trace_event_data_offsets_sched_ext_bypass_lb {};\n\nstruct trace_event_data_offsets_sched_ext_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_ext_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_end {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_start {};\n\nstruct trace_event_data_offsets_sched_kthread_work_queue_work {};\n\nstruct trace_event_data_offsets_sched_migrate_task {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_move_numa {};\n\nstruct trace_event_data_offsets_sched_numa_pair_template {};\n\nstruct trace_event_data_offsets_sched_pi_setprio {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_prepare_exec {\n\tu32 interp;\n\tconst void *interp_ptr_;\n\tu32 filename;\n\tconst void *filename_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exit {};\n\nstruct trace_event_data_offsets_sched_process_fork {\n\tu32 parent_comm;\n\tconst void *parent_comm_ptr_;\n\tu32 child_comm;\n\tconst void *child_comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_wait {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_skip_cpuset_numa {};\n\nstruct trace_event_data_offsets_sched_skip_vma_numa {};\n\nstruct trace_event_data_offsets_sched_stat_runtime {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_stat_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\nstruct trace_event_data_offsets_selinux_audited {\n\tu32 scontext;\n\tconst void *scontext_ptr_;\n\tu32 tcontext;\n\tconst void *tcontext_ptr_;\n\tu32 tclass;\n\tconst void *tclass_ptr_;\n};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_sk_data_ready {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_smbus_read {};\n\nstruct trace_event_data_offsets_smbus_reply {};\n\nstruct trace_event_data_offsets_smbus_result {};\n\nstruct trace_event_data_offsets_smbus_write {};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_sock_msg_length {};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_softirq {};\n\nstruct trace_event_data_offsets_sta_event {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sta_flag_evt {\n\tu32 vif_name;\n\tconst void *vif_name_ptr_;\n};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_station_add_change {\n\tu32 supported_rates;\n\tconst void *supported_rates_ptr_;\n\tu32 ext_capab;\n\tconst void *ext_capab_ptr_;\n\tu32 supported_channels;\n\tconst void *supported_channels_ptr_;\n\tu32 supported_oper_classes;\n\tconst void *supported_oper_classes_ptr_;\n};\n\nstruct trace_event_data_offsets_station_del {};\n\nstruct trace_event_data_offsets_stop_queue {};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_svc_alloc_arg_err {};\n\nstruct trace_event_data_offsets_svc_authenticate {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_deferred_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_pool_thread_event {};\n\nstruct trace_event_data_offsets_svc_process {\n\tu32 service;\n\tconst void *service_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_replace_page_err {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_status {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_stats_latency {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_unregister {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_svc_xdr_msg_class {};\n\nstruct trace_event_data_offsets_svc_xprt_accept {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_create_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_dequeue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_enqueue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_accept_class {\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_lifetime_class {};\n\nstruct trace_event_data_offsets_svcsock_marker {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_recv_short {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_state {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_swiotlb_bounced {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_prctl_unknown {};\n\nstruct trace_event_data_offsets_task_rename {};\n\nstruct trace_event_data_offsets_tasklet {};\n\nstruct trace_event_data_offsets_tcp_ao_event {};\n\nstruct trace_event_data_offsets_tcp_cong_state_set {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_event_skb {};\n\nstruct trace_event_data_offsets_tcp_hash_event {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\nstruct trace_event_data_offsets_tcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_tcp_retransmit_skb {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_send_reset {};\n\nstruct trace_event_data_offsets_tcp_sendmsg_locked {};\n\nstruct trace_event_data_offsets_thermal_temperature {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_zone_trip {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_tick_stop {};\n\nstruct trace_event_data_offsets_timer_base_idle {};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_tlb_flush {};\n\nstruct trace_event_data_offsets_tls_contenttype {};\n\nstruct trace_event_data_offsets_tmigr_connect_child_parent {};\n\nstruct trace_event_data_offsets_tmigr_connect_cpu_parent {};\n\nstruct trace_event_data_offsets_tmigr_cpugroup {};\n\nstruct trace_event_data_offsets_tmigr_group_and_cpu {};\n\nstruct trace_event_data_offsets_tmigr_group_set {};\n\nstruct trace_event_data_offsets_tmigr_handle_remote {};\n\nstruct trace_event_data_offsets_tmigr_idle {};\n\nstruct trace_event_data_offsets_tmigr_update_events {};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_usb_core_log_usb_device {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_vector_activate {};\n\nstruct trace_event_data_offsets_vector_alloc {};\n\nstruct trace_event_data_offsets_vector_alloc_managed {};\n\nstruct trace_event_data_offsets_vector_config {};\n\nstruct trace_event_data_offsets_vector_free_moved {};\n\nstruct trace_event_data_offsets_vector_mod {};\n\nstruct trace_event_data_offsets_vector_reserve {};\n\nstruct trace_event_data_offsets_vector_setup {};\n\nstruct trace_event_data_offsets_vector_teardown {};\n\nstruct trace_event_data_offsets_virtio_gpu_cmd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_vlv_fifo_size {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_vlv_wm {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\nstruct trace_event_data_offsets_wake_queue {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_wiphy_delayed_work_queue {};\n\nstruct trace_event_data_offsets_wiphy_enabled_evt {};\n\nstruct trace_event_data_offsets_wiphy_hrtimer_work_queue {};\n\nstruct trace_event_data_offsets_wiphy_id_evt {};\n\nstruct trace_event_data_offsets_wiphy_netdev_evt {};\n\nstruct trace_event_data_offsets_wiphy_netdev_id_evt {};\n\nstruct trace_event_data_offsets_wiphy_netdev_mac_evt {};\n\nstruct trace_event_data_offsets_wiphy_only_evt {};\n\nstruct trace_event_data_offsets_wiphy_wdev_cookie_evt {};\n\nstruct trace_event_data_offsets_wiphy_wdev_evt {};\n\nstruct trace_event_data_offsets_wiphy_wdev_link_evt {};\n\nstruct trace_event_data_offsets_wiphy_work_event {};\n\nstruct trace_event_data_offsets_wiphy_work_worker_start {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_queue_work {\n\tu32 workqueue;\n\tconst void *workqueue_ptr_;\n};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_folio_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_x86_fpu {};\n\nstruct trace_event_data_offsets_x86_irq_vector {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_data_offsets_xhci_dbc_log_request {};\n\nstruct trace_event_data_offsets_xhci_log_ctrl_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_doorbell {};\n\nstruct trace_event_data_offsets_xhci_log_ep_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_free_virt_dev {};\n\nstruct trace_event_data_offsets_xhci_log_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_portsc {};\n\nstruct trace_event_data_offsets_xhci_log_ring {};\n\nstruct trace_event_data_offsets_xhci_log_slot_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_stream_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_trb {};\n\nstruct trace_event_data_offsets_xhci_log_urb {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_virt_dev {};\n\nstruct trace_event_data_offsets_xprt_cong_event {};\n\nstruct trace_event_data_offsets_xprt_ping {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_reserve {};\n\nstruct trace_event_data_offsets_xprt_retransmit {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_transmit {};\n\nstruct trace_event_data_offsets_xprt_writelock_event {};\n\nstruct trace_event_data_offsets_xs_data_ready {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_socket_event {};\n\nstruct trace_event_data_offsets_xs_socket_event_done {};\n\nstruct trace_event_data_offsets_xs_stream_read_data {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_stream_read_request {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst unsigned int is_signed: 1;\n\t\t\tunsigned int needs_test: 1;\n\t\t\tconst int filter_type;\n\t\t\tconst int len;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct eventfs_inode *ei;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\trefcount_t ref;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nstruct trace_event_raw_9p_client_req {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_client_res {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\t__u32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_fid_ref {\n\tstruct trace_entry ent;\n\tint fid;\n\tint refcount;\n\t__u8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_protocol_dump {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u16 tag;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarmtimer_suspend {\n\tstruct trace_entry ent;\n\ts64 expires;\n\tunsigned char alarm_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alloc_vmap_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int vstart;\n\tlong unsigned int vend;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_amd_pstate_epp_perf {\n\tstruct trace_entry ent;\n\tunsigned int cpu_id;\n\tu8 highest_perf;\n\tu8 epp;\n\tu8 min_perf;\n\tu8 max_perf;\n\tbool boost;\n\tbool changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_amd_pstate_perf {\n\tstruct trace_entry ent;\n\tu8 min_perf;\n\tu8 target_perf;\n\tu8 capacity;\n\tlong long unsigned int freq;\n\tlong long unsigned int mperf;\n\tlong long unsigned int aperf;\n\tlong long unsigned int tsc;\n\tunsigned int cpu_id;\n\tbool fast_switch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_beacon_loss {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_chswitch_done {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tbool success;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_connection_loss {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_cqm_rssi_notify {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 rssi_event;\n\ts32 rssi_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_disconnect {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint reconnect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_enable_rssi_reports {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint rssi_min_thold;\n\tint rssi_max_thold;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_eosp {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_finalize_rx_omi_bw {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tint link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_gtk_rekey_notify {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 bssid[6];\n\tu8 replay_ctr[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_prepare_rx_omi_bw {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tint link_id;\n\tu32 bw;\n\tbool result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_radar_detected {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_request_smps {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint link_id;\n\tu32 smps_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_return_bool {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_return_void {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_scan_completed {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool aborted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sched_scan_results {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sched_scan_stopped {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_send_eosp_nullfunc {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu8 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sta_block_awake {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tbool block;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sta_set_buffered {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu8 tid;\n\tbool buffered;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_start_tx_ba_cb {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 ra[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_start_tx_ba_session {\n\tstruct trace_entry ent;\n\tchar sta_addr[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_stop_tx_ba_cb {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 ra[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_stop_tx_ba_session {\n\tstruct trace_entry ent;\n\tchar sta_addr[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_bmdma_status {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char host_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_action_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy_qc {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_exec_command_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char feature;\n\tunsigned char hob_nsect;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tlong unsigned int deadline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_end_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tint rc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_port_eh_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_complete_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char status;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char error;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_issue_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tunsigned char proto;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_hsm_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int protocol;\n\tunsigned int hsm_state;\n\tunsigned char dev_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char hsm_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_tf_load {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_transfer_data_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int flags;\n\tunsigned int offset;\n\tunsigned int bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_get_position {\n\tstruct trace_entry ent;\n\tint card;\n\tint idx;\n\tunsigned int pos;\n\tunsigned int delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_pcm {\n\tstruct trace_entry ent;\n\tunsigned char stream_tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_pcm_trigger {\n\tstruct trace_entry ent;\n\tint card;\n\tint idx;\n\tint cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int wb_setpoint;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bl_ext_tree_prepare_commit {\n\tstruct trace_entry ent;\n\tint ret;\n\tsize_t count;\n\tu64 lwb;\n\tbool not_all_ranges;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_blkdev_zone_mgmt {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t nr_sectors;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_completion {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_zwplug {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int zno;\n\tsector_t sector;\n\tunsigned int nr_sectors;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trace_printk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bpf_string;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trigger_tp {\n\tstruct trace_entry ent;\n\tint nonce;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_xdp_link_attach_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_event {\n\tstruct trace_entry ent;\n\tconst struct cache_head *h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_tag_flush {\n\tstruct trace_entry ent;\n\tu32 __data_loc_iommu;\n\tu32 __data_loc_dev;\n\tu16 type;\n\tu16 domain_id;\n\tu32 pasid;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int addr;\n\tlong unsigned int pages;\n\tlong unsigned int mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_tag_log {\n\tstruct trace_entry ent;\n\tu32 __data_loc_iommu;\n\tu32 __data_loc_dev;\n\tu16 type;\n\tu16 domain_id;\n\tu32 pasid;\n\tu32 users;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cap_capable {\n\tstruct trace_entry ent;\n\tconst struct cred *cred;\n\tstruct user_namespace *target_ns;\n\tconst struct user_namespace *capable_ns;\n\tint cap;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cdev_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int target;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_assoc_comeback {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu8 ap_addr[6];\n\tu32 timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_bss_color_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu32 cmd;\n\tu8 count;\n\tu64 color_bitmap;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_bss_evt {\n\tstruct trace_entry ent;\n\tu8 bssid[6];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_cac_event {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_radar_event evt;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ch_switch_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ch_switch_started_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_control_port_tx_status {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_cqm_pktloss_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu32 num_packets;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_cqm_rssi_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_cqm_rssi_threshold_event rssi_event;\n\ts32 rssi_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_epcs_changed {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu32 enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ft_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 __data_loc_ies;\n\tu8 target_ap[6];\n\tu32 __data_loc_ric_ies;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_get_bss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tu8 bssid[6];\n\tu32 __data_loc_ssid;\n\tenum ieee80211_bss_type bss_type;\n\tenum ieee80211_privacy privacy;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ibss_joined {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_inform_bss_frame {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tu32 __data_loc_mgmt;\n\ts32 signal;\n\tu64 ts_boottime;\n\tu64 parent_tsf;\n\tu8 parent_bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_links_removed {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu16 link_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_mgmt_tx_status {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_michael_mic_failure {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tenum nl80211_key_type key_type;\n\tint key_id;\n\tu8 tsc[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_mlo_reconf_add_done {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu16 link_mask;\n\tu32 __data_loc_buf;\n\tbool driver_initiated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_nan_cluster_joined {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu8 cluster_id[6];\n\tbool new_cluster;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_netdev_mac_evt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 macaddr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_new_sta {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 mac_addr[6];\n\tint generation;\n\tu32 connected_time;\n\tu32 inactive_time;\n\tu32 rx_bytes;\n\tu32 tx_bytes;\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tu32 beacon_loss_count;\n\tu16 llid;\n\tu16 plid;\n\tu8 plink_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_next_nan_dw_notif {\n\tstruct trace_entry ent;\n\tu32 id;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_pmksa_candidate_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tint index;\n\tu8 bssid[6];\n\tbool preauth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_pmsr_complete {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_pmsr_report {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tu8 addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_probe_status {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tu64 cookie;\n\tbool acked;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_radar_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tbool offchan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ready_on_channel {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tunsigned int duration;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ready_on_channel_expired {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_reg_can_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tenum nl80211_iftype iftype;\n\tu32 prohibited_flags;\n\tu32 permitting_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_report_obss_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint freq;\n\tint sig_dbm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_report_wowlan_wakeup {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tbool non_wireless;\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\ts32 pattern_idx;\n\tu32 packet_len;\n\tu32 __data_loc_packet;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_return_bool {\n\tstruct trace_entry ent;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_rx_control_port {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tint len;\n\tu8 from[6];\n\tu16 proto;\n\tbool unencrypted;\n\tint link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_rx_evt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tint link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_rx_mgmt {\n\tstruct trace_entry ent;\n\tu32 id;\n\tint freq;\n\tint sig_dbm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_scan_done {\n\tstruct trace_entry ent;\n\tu32 n_channels;\n\tu32 __data_loc_ie;\n\tu32 rates[6];\n\tu32 wdev_id;\n\tu8 wiphy_mac[6];\n\tbool no_cck;\n\tbool aborted;\n\tu64 scan_start_tsf;\n\tu8 tsf_bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_send_assoc_failure {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 ap_addr[6];\n\tbool timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_send_rx_assoc {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 ap_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_stop_link {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tint link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_tdls_oper_request {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tenum nl80211_tdls_operation oper;\n\tu16 reason_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_tx_mgmt_expired {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_tx_mlme_mgmt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu32 __data_loc_frame;\n\tint reconnect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_update_owe_info_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu32 __data_loc_ie;\n\tint assoc_link_id;\n\tu8 peer_mld_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_level;\n\tu64 dst_id;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu32 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_rstat {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tint cpu;\n\tbool contended;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_chanswitch_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu64 timestamp;\n\tu32 device_timestamp;\n\tbool block_tx;\n\tu8 count;\n\tu8 link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_begin {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_end {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_idle_miss {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool below;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_function {\n\tstruct trace_entry ent;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_queue_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\tu32 ctime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime_ns_xchg {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tu32 gen;\n\tu32 old;\n\tu32 new;\n\tu32 cur;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_parent;\n\tu32 __data_loc_pm_ops;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devres {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tstruct device *dev;\n\tconst char *op;\n\tvoid *node;\n\tu32 __data_loc_name;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tgfp_t flags;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tgfp_t flags;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_attach_dev {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tstruct dma_buf_attachment *attach;\n\tbool is_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_fd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence_unsignaled {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 phys_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tint full_nents;\n\tint full_ents;\n\tbool truncated;\n\tu32 __data_loc_phys_addrs;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tint err;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_single {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_addrs;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dql_stall_detected {\n\tstruct trace_entry ent;\n\tshort unsigned int thrs;\n\tunsigned int len;\n\tlong unsigned int last_reap;\n\tlong unsigned int hist_head;\n\tlong unsigned int now;\n\tlong unsigned int hist[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event {\n\tstruct trace_entry ent;\n\tint crtc;\n\tunsigned int seq;\n\tktime_t time;\n\tbool high_prec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event_delivered {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event_queued {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_add_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 type;\n\tu8 inst_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_add_twt_setup {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu8 dialog_token;\n\tu8 control;\n\t__le16 req_type;\n\t__le64 twt;\n\tu8 duration;\n\t__le16 mantissa;\n\tu8 channel;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_ampdu_action {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tenum ieee80211_ampdu_mlme_action ieee80211_ampdu_mlme_action;\n\tchar sta_addr[6];\n\tu16 tid;\n\tu16 ssn;\n\tu16 buf_size;\n\tbool amsdu;\n\tu16 timeout;\n\tu16 action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_can_activate_links {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu16 active_links;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_can_neg_ttlm {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu16 downlink[16];\n\tu16 uplink[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_change_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 min_control_freq;\n\tu32 min_freq_offset;\n\tu32 min_chan_width;\n\tu32 min_center_freq1;\n\tu32 min_freq1_offset;\n\tu32 min_center_freq2;\n\tu32 ap_control_freq;\n\tu32 ap_freq_offset;\n\tu32 ap_chan_width;\n\tu32 ap_center_freq1;\n\tu32 ap_freq1_offset;\n\tu32 ap_center_freq2;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tu32 changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_change_interface {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 new_type;\n\tbool new_p2p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_change_sta_links {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu16 old_links;\n\tu16 new_links;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_change_vif_links {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu16 old_links;\n\tu16 new_links;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_channel_switch_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_conf_tx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tunsigned int link_id;\n\tu16 ac;\n\tu16 txop;\n\tu16 cw_min;\n\tu16 cw_max;\n\tu8 aifs;\n\tbool uapsd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\tu32 changed;\n\tu32 flags;\n\tint power_level;\n\tint dynamic_ps_timeout;\n\tu16 listen_interval;\n\tu8 long_frame_max_tx_count;\n\tu8 short_frame_max_tx_count;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tint smps;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_config_iface_filter {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tunsigned int filter_flags;\n\tunsigned int changed_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_configure_filter {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tunsigned int changed;\n\tunsigned int total;\n\tu64 multicast;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_del_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 instance_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_event_callback {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_flush {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool drop;\n\tu32 queues;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_antenna {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\tu32 tx_ant;\n\tu32 rx_ant;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_expected_throughput {\n\tstruct trace_entry ent;\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_ftm_responder_stats {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_key_seq {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 cipher;\n\tu8 hw_key_idx;\n\tu8 flags;\n\ts8 keyidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_ringparam {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx;\n\tu32 tx_max;\n\tu32 rx;\n\tu32 rx_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_stats {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tunsigned int ackfail;\n\tunsigned int rtsfail;\n\tunsigned int fcserr;\n\tunsigned int rtssucc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_survey {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_txpower {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tunsigned int link_id;\n\tint dbm;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_join_ibss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 dtimper;\n\tu16 bcnint;\n\tu32 __data_loc_ssid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_link_info_changed {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu64 changed;\n\tint link_id;\n\tbool cts;\n\tbool shortpre;\n\tbool shortslot;\n\tbool enable_beacon;\n\tu8 dtimper;\n\tu16 bcnint;\n\tu16 assoc_cap;\n\tu64 sync_tsf;\n\tu32 sync_device_ts;\n\tu8 sync_dtim_count;\n\tu32 basic_rates;\n\tint mcast_rate[6];\n\tu16 ht_operation_mode;\n\ts32 cqm_rssi_thold;\n\ts32 cqm_rssi_hyst;\n\tu32 channel_width;\n\tu32 channel_cfreq1;\n\tu32 channel_cfreq1_offset;\n\tbool qos;\n\tbool hidden_ssid;\n\tint txpower;\n\tu8 p2p_oppps_ctwindow;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_link_sta_rc_update {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 changed;\n\tu32 link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_link_sta_statistics {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_nan_change_conf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 master_pref;\n\tu8 bands;\n\tu32 changes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_neg_ttlm_res {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 res;\n\tu16 downlink[16];\n\tu16 uplink[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_net_setup_tc {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_offset_tsf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\ts64 tsf_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_prep_add_interface {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_prepare_multicast {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint mc_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_reconfig_complete {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu8 reconfig_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_remain_on_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint center_freq;\n\tint freq_offset;\n\tunsigned int duration;\n\tu32 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_bool {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_int {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_u32 {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_u64 {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu64 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_antenna {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx_ant;\n\tu32 rx_ant;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_bitrate_mask {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 legacy_2g;\n\tu32 legacy_5g;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_coverage_class {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\ts16 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_default_unicast_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint key_idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_eml_op_mode {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 link_id;\n\tu8 control;\n\tu16 link_bitmap;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_frag_threshold {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 cmd;\n\tu32 cipher;\n\tu8 hw_key_idx;\n\tu8 flags;\n\ts8 keyidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_rekey_data {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 kek[16];\n\tu8 kck[16];\n\tu8 replay_ctr[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_ringparam {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx;\n\tu32 rx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_rts_threshold {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_tim {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tbool set;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_tsf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu64 tsf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_wakeup {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sta_notify {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sta_set_txpwr {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\ts16 txpwr;\n\tu8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sta_state {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 old_state;\n\tu32 new_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_start_ap {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 link_id;\n\tu8 dtimper;\n\tu16 bcnint;\n\tu32 __data_loc_ssid;\n\tbool hidden_ssid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_start_nan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 master_pref;\n\tu8 bands;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_stop {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool suspend;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_stop_ap {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_stop_nan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sw_scan_start {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar mac_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_switch_vif_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint n_vifs;\n\tu32 mode;\n\tu32 __data_loc_vifs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_tdls_cancel_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_tdls_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu8 oper_class;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_tdls_recv_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 action_code;\n\tchar sta_addr[6];\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 status;\n\tbool peer_initiator;\n\tu32 timestamp;\n\tu16 switch_time;\n\tu16 switch_timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_twt_teardown_request {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu8 flowid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_update_tkip_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 iv32;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_vif_cfg_changed {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu64 changed;\n\tbool assoc;\n\tbool ibss_joined;\n\tbool ibss_creator;\n\tu16 aid;\n\tu32 __data_loc_arp_addr_list;\n\tint arp_addr_cnt;\n\tu32 __data_loc_ssid;\n\tint s1g;\n\tbool idle;\n\tbool ps;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_wake_tx_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu8 ac;\n\tu8 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_e1000e_trace_mac_register {\n\tstruct trace_entry ent;\n\tuint32_t reg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_emulate_vsyscall {\n\tstruct trace_entry ent;\n\tint nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_error_report_template {\n\tstruct trace_entry ent;\n\tenum error_detector error_detector;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exceptions {\n\tstruct trace_entry ent;\n\tlong unsigned int address;\n\tlong unsigned int ip;\n\tlong unsigned int error_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exit_mmap {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tstruct maple_tree *mt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_shrink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_to_scan;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__fallocate_mode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tint mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int flags;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int mflags;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mb_new_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 pa_pstart;\n\t__u64 pa_lstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mballoc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__trim {\n\tstruct trace_entry ent;\n\tint dev_major;\n\tint dev_minor;\n\t__u32 group;\n\tint start;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int copied;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_alloc_da_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int data_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_begin_ordered_truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_collapse_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_release_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint freed_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint reserve_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_update_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint used_blocks;\n\tint reserved_data_blocks;\n\tint quota_claim;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 lblk;\n\t__u32 len;\n\t__u32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 blk;\n\t__u64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_drop_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint drop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tconst char *function;\n\tunsigned int line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_insert_delayed_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tbool lclu_allocated;\n\tbool end_allocated;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tint found;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_remove_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t lblk;\n\tloff_t len;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tlong long unsigned int scan_time;\n\tint nr_skipped;\n\tint retried;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_evict_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_fastpath {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\text4_lblk_t i_lblk;\n\tunsigned int i_len;\n\text4_fsblk_t i_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_handle_unwritten_extents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tunsigned int allocated;\n\text4_fsblk_t newblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_load_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tshort unsigned int eh_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_idx {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_leaf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t ee_lblk;\n\text4_fsblk_t ee_pblk;\n\tshort int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_show_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tshort unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fallocate_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int blocks;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_cleanup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint j_fc_off;\n\tint full;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_stop {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nblks;\n\tint reason;\n\tint num_fc;\n\tint num_fc_ineligible;\n\tint nblks_agg;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint tag;\n\tint ino;\n\tint priv1;\n\tint priv2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint error;\n\tint off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int fc_ineligible_rc[13];\n\tlong unsigned int fc_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_numblks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_dentry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tlong int start;\n\tlong int end;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_forget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tint is_metadata;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tlong unsigned int count;\n\tint flags;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u64 blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu32 agno;\n\tu64 bno;\n\tu64 len;\n\tu64 owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_implied_cluster_alloc_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu64 block;\n\tu64 len;\n\tu64 owner;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_insert_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_invalidate_folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tsize_t offset;\n\tsize_t length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_inode {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_reserved {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_lazy_itable_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_load_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mark_inode_dirty {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint needed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_group_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 pa_pstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_inode_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\t__u32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 goal_logical;\n\tint goal_start;\n\t__u32 goal_group;\n\tint goal_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\t__u16 found;\n\t__u16 groups;\n\t__u16 buddy;\n\t__u16 flags;\n\t__u16 tail;\n\t__u8 cr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_prealloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tunsigned int orig_flags;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int m_len;\n\tu64 move_len;\n\tint move_type;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_nfs_commit_metadata {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_other_inode_update_time {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t orig_ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_prefetch_bitmaps {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\t__u32 next;\n\t__u32 ios;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_read_block_bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tbool prefetch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_remove_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\text4_fsblk_t ee_pblk;\n\text4_lblk_t ee_lblk;\n\tshort unsigned int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tint datasync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_update_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\text4_fsblk_t fsblk;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages_result {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tint pages_written;\n\tlong int pages_skipped;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ff_layout_commit_error {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib6_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu32 flowlabel;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[16];\n\t__u8 dst[16];\n\tu16 sport;\n\tu16 dport;\n\tu8 proto;\n\tu8 rt_type;\n\tchar name[16];\n\t__u8 gw[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tchar name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lease *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tlong unsigned int break_time;\n\tlong unsigned int downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int pid;\n\tunsigned int flags;\n\tunsigned char type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fill_mg_cmtime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\ttime64_t mtime_s;\n\tu32 ctime_ns;\n\tu32 mtime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fl_getdevinfo {\n\tstruct trace_entry ent;\n\tu32 __data_loc_mds_addr;\n\tunsigned char deviceid[16];\n\tu32 __data_loc_ds_ips;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_free_vmap_area_noflush {\n\tstruct trace_entry ent;\n\tlong unsigned int va_start;\n\tlong unsigned int nr_lazy;\n\tlong unsigned int nr_lazy_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_g4x_wm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu16 primary;\n\tu16 sprite;\n\tu16 cursor;\n\tu16 sr_plane;\n\tu16 sr_cursor;\n\tu16 sr_fbc;\n\tu16 hpll_plane;\n\tu16 hpll_cursor;\n\tu16 hpll_fbc;\n\tbool cxsr;\n\tbool hpll;\n\tbool fbc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_guest_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_alert_class {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int level;\n\tlong unsigned int description;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_complete {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint status;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_error_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint err;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_event_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_fd_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint fd;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_get_response {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 addr;\n\tu32 res;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_pm {\n\tstruct trace_entry ent;\n\tint dev_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_send_cmd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_unsol_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 res;\n\tu32 res_ex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hdac_stream {\n\tstruct trace_entry ent;\n\tunsigned char stream_tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_setup {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs__inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u16 mode;\n\tloff_t size;\n\tunsigned int nlink;\n\tunsigned int seals;\n\tblkcnt_t blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_alloc_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_fallocate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint mode;\n\tloff_t offset;\n\tloff_t len;\n\tloff_t size;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_setattr {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int d_len;\n\tu32 __data_loc_d_name;\n\tunsigned int ia_valid;\n\tunsigned int ia_mode;\n\tloff_t old_size;\n\tloff_t ia_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_class {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tlong long int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_show_string {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tu32 __data_loc_label;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 nr_msgs;\n\t__s16 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_context {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_gem_context *ctx;\n\tstruct i915_address_space *vm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tu64 size;\n\tu64 align;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict_node {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tu64 start;\n\tu64 size;\n\tlong unsigned int color;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict_vm {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_create {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_fault {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 index;\n\tbool gtt;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_pread {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 offset;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_pwrite {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 offset;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_shrink {\n\tstruct trace_entry ent;\n\tint dev;\n\tlong unsigned int target;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_ppgtt {\n\tstruct trace_entry ent;\n\tstruct i915_address_space *vm;\n\tu32 dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_reg_rw {\n\tstruct trace_entry ent;\n\tu64 val;\n\tu32 reg;\n\tu16 write;\n\tu16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tu32 tail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request_queue {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request_wait_begin {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_vma_bind {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_address_space *vm;\n\tu64 offset;\n\tu64 size;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_vma_unbind {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_address_space *vm;\n\tu64 offset;\n\tu64 size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icmp_send {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint type;\n\tint code;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u16 sport;\n\t__u16 dport;\n\tshort unsigned int ulen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sk_error_report {\n\tstruct trace_entry ent;\n\tint error;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\ntypedef int (*initcall_t)(void);\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_cpu_fifo_underrun {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_crtc_flip_done {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_crtc_vblank_work_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_crtc_vblank_work_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_activate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_name;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_deactivate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_name;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_nuke {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_name;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_frontbuffer_flush {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tunsigned int frontbuffer_bits;\n\tunsigned int origin;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_frontbuffer_invalidate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tunsigned int frontbuffer_bits;\n\tunsigned int origin;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_memory_cxsr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 frame[4];\n\tu32 scanline[4];\n\tbool old;\n\tbool new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pch_fifo_underrun {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_crc {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 crcs[5];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_disable {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 frame[4];\n\tu32 scanline[4];\n\tchar pipe_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_enable {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 frame[4];\n\tu32 scanline[4];\n\tchar pipe_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_scaler_update_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tint scaler_id;\n\tu32 frame;\n\tu32 scanline;\n\tint x;\n\tint y;\n\tint w;\n\tint h;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_vblank_evaded {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_async_flip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tbool async_flip;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_disable_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_scaler_update_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tint scaler_id;\n\tu32 frame;\n\tu32 scanline;\n\tint x;\n\tint y;\n\tint w;\n\tint h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_update_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 format;\n\tint src[4];\n\tint dst[4];\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_plane_update_noarm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 format;\n\tint src[4];\n\tint dst[4];\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_scaler_disable_arm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tint scaler_id;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint res;\n\tunsigned int cflags;\n\tu64 extra1;\n\tu64 extra2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqe_overflow {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong long unsigned int user_data;\n\ts32 res;\n\tu32 cflags;\n\tvoid *ocqe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tu8 opcode;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tvoid *link;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_local_work_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint count;\n\tunsigned int loops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tint events;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tstruct io_wq_work *work;\n\tbool hashed;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_req_failed {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tu8 flags;\n\tu8 ioprio;\n\tu64 off;\n\tu64 addr;\n\tu32 len;\n\tu32 op_flags;\n\tu16 buf_index;\n\tu16 personality;\n\tu32 file_index;\n\tu64 pad1;\n\tu64 addr3;\n\tint error;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_short_write {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu64 fpos;\n\tu64 wanted;\n\tu64 got;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_req {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tbool sq_thread;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_work_run {\n\tstruct trace_entry ent;\n\tvoid *tctx;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocg_inuse_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu32 old_inuse;\n\tu32 new_inuse;\n\tu64 old_hweight_inuse;\n\tu64 new_hweight_inuse;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_ioc_vrate_adj {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu64 old_vrate;\n\tu64 new_vrate;\n\tint busy_level;\n\tu32 read_missed_ppm;\n\tu32 write_missed_ppm;\n\tu32 rq_wait_pct;\n\tint nr_lagging;\n\tint nr_shortages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_iocg_forgive_debt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu64 vnow;\n\tu32 usage_pct;\n\tu64 old_debt;\n\tu64 new_debt;\n\tu64 old_delay;\n\tu64 new_delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iocost_iocg_state {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tu32 __data_loc_cgroup;\n\tu64 now;\n\tu64 vnow;\n\tu64 vrate;\n\tu64 last_period;\n\tu64 cur_period;\n\tu64 vtime;\n\tu32 weight;\n\tu32 inuse;\n\tu64 hweight_active;\n\tu64 hweight_inuse;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_add_to_ioend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 pos;\n\tu64 dirty_len;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tint ki_flags;\n\tbool aio;\n\tint error;\n\tssize_t ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_rw_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tsize_t count;\n\tsize_t done_before;\n\tint ki_flags;\n\tunsigned int dio_flags;\n\tbool aio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_iter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t pos;\n\tu64 length;\n\tint status;\n\tunsigned int flags;\n\tconst void *ops;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t size;\n\tloff_t offset;\n\tu64 length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpumask {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_cpu {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int cpu;\n\tbool online;\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_global {\n\tstruct trace_entry ent;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_global_update {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int chp_time;\n\t__u32 forced_to_close;\n\t__u32 written;\n\t__u32 dropped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_end_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\ttid_t head;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_extend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint buffer_credits;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_start_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint interval;\n\tint sync;\n\tint requested_blocks;\n\tint dirtied_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_journal_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_lock_buffer_stall {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int stall_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_run_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int wait;\n\tlong unsigned int request_delay;\n\tlong unsigned int running;\n\tlong unsigned int locked;\n\tlong unsigned int flushing;\n\tlong unsigned int logging;\n\t__u32 handle_count;\n\t__u32 blocks;\n\t__u32 blocks_logged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_checkpoint_list {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t first_tid;\n\ttid_t tid;\n\ttid_t last_tid;\n\tlong unsigned int nr_freed;\n\ttid_t next_tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_shrunk;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_submit_inode_data {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_update_log_tail {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tail_sequence;\n\ttid_t first_tid;\n\tlong unsigned int block_nr;\n\tlong unsigned int freed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_write_superblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tblk_opf_t write_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_key_handle {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 mac_addr[6];\n\tint link_id;\n\tu8 key_index;\n\tbool pairwise;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tvoid *rx_sk;\n\tshort unsigned int protocol;\n\tenum skb_drop_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmalloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tbool accounted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_link_station_add_mod {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 mld_mac[6];\n\tu8 link_mac[6];\n\tu32 link_id;\n\tu32 __data_loc_supported_rates;\n\tu8 ht_capa[26];\n\tu8 vht_capa[12];\n\tu8 opmode_notif;\n\tbool opmode_notif_used;\n\tu32 __data_loc_he_capa;\n\tu8 he_6ghz_capa[2];\n\tu32 __data_loc_eht_capa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 min_control_freq;\n\tu32 min_freq_offset;\n\tu32 min_chan_width;\n\tu32 min_center_freq1;\n\tu32 min_freq1_offset;\n\tu32 min_center_freq2;\n\tu32 ap_control_freq;\n\tu32 ap_freq_offset;\n\tu32 ap_chan_width;\n\tu32 ap_center_freq1;\n\tu32 ap_freq1_offset;\n\tu32 ap_center_freq2;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_only_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_sdata_addr_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_sdata_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 min_control_freq;\n\tu32 min_freq_offset;\n\tu32 min_chan_width;\n\tu32 min_center_freq1;\n\tu32 min_freq1_offset;\n\tu32 min_center_freq2;\n\tu32 ap_control_freq;\n\tu32 ap_freq_offset;\n\tu32 ap_chan_width;\n\tu32 ap_center_freq1;\n\tu32 ap_freq1_offset;\n\tu32 ap_center_freq2;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_sdata_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_u32_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_op {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_read {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_write {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tlong unsigned int piv;\n\tvoid *val;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tu32 __data_loc_comm;\n\tlong unsigned int total_vm;\n\tlong unsigned int anon_rss;\n\tlong unsigned int file_rss;\n\tlong unsigned int shmem_rss;\n\tuid_t uid;\n\tlong unsigned int pgtables;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mce_record {\n\tstruct trace_entry ent;\n\tu64 mcgcap;\n\tu64 mcgstatus;\n\tu64 status;\n\tu64 addr;\n\tu64 misc;\n\tu64 synd;\n\tu64 ipid;\n\tu64 ip;\n\tu64 tsc;\n\tu64 ppin;\n\tu64 walltime;\n\tu32 cpu;\n\tu32 cpuid;\n\tu32 apicid;\n\tu32 socketid;\n\tu8 cs;\n\tu8 bank;\n\tu8 cpuvendor;\n\tu32 microcode;\n\tu32 __data_loc_v_data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mdio_access {\n\tstruct trace_entry ent;\n\tchar busid[61];\n\tchar read;\n\tu8 addr;\n\tu16 val;\n\tunsigned int regnum;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mei_pci_cfg_read {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_reg;\n\tu32 offs;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mei_reg_read {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_reg;\n\tu32 offs;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mei_reg_write {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_reg;\n\tu32 offs;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct xdp_mem_allocator;\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mgd_prepare_complete_tx_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 duration;\n\tu16 subtype;\n\tu8 success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pte {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_calculate_totalreserve_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int totalreserve_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tunsigned char order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache_range {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int last_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tenum lru_list lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tlong unsigned int thp_succeeded;\n\tlong unsigned int thp_failed;\n\tlong unsigned int thp_split;\n\tlong unsigned int large_folio_split;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages_start {\n\tstruct trace_entry ent;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tint percpu_refill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tlong unsigned int gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_lowmem_reserve {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tu32 __data_loc_upper_name;\n\tlong int lowmem_reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_wmarks {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tlong unsigned int watermark_min;\n\tlong unsigned int watermark_low;\n\tlong unsigned int watermark_high;\n\tlong unsigned int watermark_promo;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tlong unsigned int gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_clear_hopeless {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_reclaim_fail {\n\tstruct trace_entry ent;\n\tint nid;\n\tint failures;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_reclaim_pages {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_throttled {\n\tstruct trace_entry ent;\n\tint nid;\n\tint usec_timeout;\n\tint usec_delayed;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_write_folio {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock_acquire_returned {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tbool success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mpath_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 next_hop[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_msr_trace_class {\n\tstruct trace_entry ent;\n\tunsigned int msr;\n\tu64 val;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netdev_frame_event {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu32 __data_loc_frame;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netdev_mac_evt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 mac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int len;\n\tlong long unsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_folio {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tlong unsigned int index;\n\tlong long unsigned int fend;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int collected_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_gap {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tunsigned char type;\n\tlong long unsigned int from;\n\tlong long unsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_sreq {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int subreq;\n\tunsigned int stream;\n\tunsigned int len;\n\tunsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_state {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int notes;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_stream {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int front;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_copy2cache {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int creq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_failure {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_failure what;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folio {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tlong unsigned int index;\n\tunsigned int nr;\n\tenum netfs_folio_trace why;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folioq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int id;\n\tenum netfs_folioq_trace trace;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_read {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int cookie;\n\tloff_t i_size;\n\tloff_t start;\n\tsize_t len;\n\tenum netfs_read_trace what;\n\tunsigned int netfs_inode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int flags;\n\tenum netfs_io_origin origin;\n\tenum netfs_rreq_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tint ref;\n\tenum netfs_rreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort unsigned int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_sreq_trace what;\n\tu8 slot;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int subreq;\n\tint ref;\n\tenum netfs_sreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tenum netfs_write_trace what;\n\tlong long unsigned int start;\n\tlong long unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write_iter {\n\tstruct trace_entry ent;\n\tlong long unsigned int start;\n\tsize_t len;\n\tunsigned int flags;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netlink_extack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cached_open {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_error_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 cbident;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_offload {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tloff_t cb_count;\n\tint cb_how;\n\tint cb_stateid_seq;\n\tu32 cb_stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_seqid_err {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clientid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_close {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_commit_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tloff_t offset;\n\tu32 count;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegation_event {\n\tstruct trace_entry ent;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegreturn_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_status {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint status;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_flexfiles_io_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_getattr_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int valid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_idmap_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 id;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_layoutget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 iomode;\n\tu64 offset;\n\tu64 count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lock_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookup_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookupp {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_match_stateid_event {\n\tstruct trace_entry ent;\n\tint s1_seq;\n\tint s2_seq;\n\tu32 s1_hash;\n\tu32 s2_hash;\n\tint s1_type;\n\tint s2_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_open_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint openstateid_seq;\n\tu32 openstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_read_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 olddir;\n\tu32 __data_loc_oldname;\n\tu64 newdir;\n\tu32 __data_loc_newname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_sequence_done {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int target_highest_slotid;\n\tlong unsigned int status_flags;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_delegation_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_lock {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint lockstateid_seq;\n\tu32 lockstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_setup_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_used_slotid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_lock_reclaim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int state_flags;\n\tlong unsigned int lock_flags;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr_failed {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tu32 __data_loc_section;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_test_stateid_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_trunked_exchange_id {\n\tstruct trace_entry ent;\n\tu32 __data_loc_main_addr;\n\tu32 __data_loc_trunk_addr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_write_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_bad_operation {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tu32 expected;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_access_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tunsigned int mask;\n\tunsigned int permitted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_commit_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_direct_req_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t offset;\n\tssize_t count;\n\tssize_t error;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_fh_to_dentry {\n\tstruct trace_entry ent;\n\tint error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_read {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_write {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tlong unsigned int stable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_range_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t range_start;\n\tloff_t range_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_kiocb_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_local_open_fh {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_assign {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tu32 __data_loc_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_option {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_path {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tconst struct nfs_page *req;\n\tloff_t offset;\n\tunsigned int count;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tunsigned int count;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_pgio_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tloff_t pos;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readdir_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tchar verifier[8];\n\tu64 cookie;\n\tlong unsigned int index;\n\tunsigned int dtsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_short {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 old_dir;\n\tu64 new_dir;\n\tu32 __data_loc_old_name;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 old_dir;\n\tu32 __data_loc_old_name;\n\tu64 new_dir;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_sillyrename_unlink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_update_size_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t cur_size;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_writeback_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tlong unsigned int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nlmclnt_lock_event {\n\tstruct trace_entry ent;\n\tu32 oh;\n\tu32 svid;\n\tu32 fh;\n\tlong unsigned int status;\n\tu64 start;\n\tu64 len;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nmi_handler {\n\tstruct trace_entry ent;\n\tvoid *handler;\n\ts64 delta_ns;\n\tint handled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_notifier_info {\n\tstruct trace_entry ent;\n\tvoid *cb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_op {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n\tlong unsigned int req_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_order {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_unbounded {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int nr_to_read;\n\tlong unsigned int lookahead_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\ts32 inflight;\n\tu32 hold;\n\tu32 release;\n\tu64 cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_hold {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 hold;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 release;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_update_nid {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tint pool_nid;\n\tint new_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pci_hp_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tu32 __data_loc_slot;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pcie_link_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tunsigned int type;\n\tunsigned int reason;\n\tunsigned int cur_bus_speed;\n\tunsigned int max_bus_speed;\n\tunsigned int width;\n\tunsigned int flit_mode;\n\tunsigned int link_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pmap_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_err_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tlong unsigned int status;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_ds_connect {\n\tstruct trace_entry ent;\n\tu32 __data_loc_ds_ips;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_layout_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_update_layout {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tenum pnfs_update_layout_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_prq_report {\n\tstruct trace_entry ent;\n\tu64 dw0;\n\tu64 dw1;\n\tu64 dw2;\n\tu64 dw3;\n\tlong unsigned int seq;\n\tu32 __data_loc_iommu;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_buff;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_purge_vmap_area_lazy {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int npurged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_enqueue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qi_submit {\n\tstruct trace_entry ent;\n\tu64 qw0;\n\tu64 qw1;\n\tu64 qw2;\n\tu64 qw3;\n\tu32 __data_loc_iommu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kvfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_segcb_stats {\n\tstruct trace_entry ent;\n\tconst char *ctx;\n\tlong unsigned int gp_seq[4];\n\tlong int seglen[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_sr_normal {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tconst char *srevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_stall_warning {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_watching {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint counter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 mac_addr[6];\n\tint link_id;\n\tu8 key_index;\n\tbool pairwise;\n\tu8 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu8 func_type;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_tx_ts {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu8 tsid;\n\tu8 user_prio;\n\tu16 admitted_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_virtual_intf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 __data_loc_vir_intf_name;\n\tenum nl80211_iftype type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_assoc {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu8 prev_bssid[6];\n\tbool use_mfp;\n\tu32 flags;\n\tu32 __data_loc_elements;\n\tu8 ht_capa[26];\n\tu8 ht_capa_mask[26];\n\tu8 vht_capa[12];\n\tu8 vht_capa_mask[12];\n\tu32 __data_loc_fils_kek;\n\tu32 __data_loc_fils_nonces;\n\tu16 ext_mld_capa_ops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_assoc_ml_reconf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 add_links;\n\tu16 rem_links;\n\tu16 ext_mld_capa_ops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_auth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tenum nl80211_auth_type auth_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_cancel_remain_on_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_change_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint link_id;\n\tu32 __data_loc_head;\n\tu32 __data_loc_tail;\n\tu32 __data_loc_beacon_ies;\n\tu32 __data_loc_proberesp_ies;\n\tu32 __data_loc_assocresp_ies;\n\tu32 __data_loc_probe_resp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_change_bss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint use_cts_prot;\n\tint use_short_preamble;\n\tint use_short_slot_time;\n\tint ap_isolate;\n\tint ht_opmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_change_virtual_intf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_iftype type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tbool radar_required;\n\tbool block_tx;\n\tu8 count;\n\tu32 __data_loc_bcn_ofs;\n\tu32 __data_loc_pres_ofs;\n\tu8 link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_color_change {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 count;\n\tu16 bcn_ofs;\n\tu16 pres_ofs;\n\tu8 link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_connect {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tchar ssid[33];\n\tenum nl80211_auth_type auth_type;\n\tbool privacy;\n\tu32 wpa_versions;\n\tu32 flags;\n\tu8 prev_bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_crit_proto_start {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu16 proto;\n\tu16 duration;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_crit_proto_stop {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_deauth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu16 reason_code;\n\tbool local_state_change;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_del_link_station {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 mld_mac[6];\n\tu32 link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_del_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_del_pmk {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 aa[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_del_tx_ts {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu8 tsid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_disassoc {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu16 reason_code;\n\tbool local_state_change;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_disconnect {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 reason_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_mpath {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 next_hop[6];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_mpp {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 mpp[6];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_station {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_survey {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_end_cac {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_external_auth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu8 ssid[33];\n\tu16 status;\n\tu8 mld_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_get_antenna {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_get_ftm_responder_stats {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu64 timestamp;\n\tu32 success_num;\n\tu32 partial_num;\n\tu32 failed_num;\n\tu32 asap_num;\n\tu32 non_asap_num;\n\tu64 duration;\n\tu32 unknown_triggers;\n\tu32 reschedule;\n\tu32 out_of_window;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_get_mpp {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 mpp[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_get_tx_power {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tint radio_idx;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_inform_bss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu8 bssid[6];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_join_ibss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tchar ssid[33];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_join_mesh {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 min_discovery_timeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tbool dot11MeshNolearn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_join_ocb {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_libertas_set_mesh_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_mgmt_tx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tbool offchan;\n\tunsigned int wait;\n\tbool no_cck;\n\tbool dont_wait_for_ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_mgmt_tx_cancel_wait {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_nan_change_conf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu8 master_pref;\n\tu8 bands;\n\tu32 changes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_pmksa {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_probe_client {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_probe_mesh_link {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dest[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_remain_on_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tunsigned int duration;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_reset_tid_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu8 tids;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_chandef {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_cookie {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_int {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint func_ret;\n\tint func_fill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_mesh_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 min_discovery_timeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tbool dot11MeshNolearn;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_mpath_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tint generation;\n\tu32 filled;\n\tu32 frame_qlen;\n\tu32 sn;\n\tu32 metric;\n\tu32 exptime;\n\tu32 discovery_timeout;\n\tu8 discovery_retries;\n\tu8 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_station_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tint generation;\n\tu32 connected_time;\n\tu32 inactive_time;\n\tu32 rx_bytes;\n\tu32 tx_bytes;\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tu32 beacon_loss_count;\n\tu16 llid;\n\tu16 plid;\n\tu8 plink_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_survey_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tint ret;\n\tu64 time;\n\tu64 time_busy;\n\tu64 time_ext_busy;\n\tu64 time_rx;\n\tu64 time_tx;\n\tu64 time_scan;\n\tu32 filled;\n\ts8 noise;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_tx_rx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tu32 tx;\n\tu32 rx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_void_tx_rx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx;\n\tu32 tx_max;\n\tu32 rx;\n\tu32 rx_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_scan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_antenna {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\tu32 tx;\n\tu32 rx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_ap_chanwidth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_bitrate_mask {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tunsigned int link_id;\n\tu8 peer[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_coalesce {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint n_rules;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_cqm_rssi_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\ts32 rssi_thold;\n\tu32 rssi_hyst;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_cqm_rssi_range_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\ts32 rssi_low;\n\ts32 rssi_high;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_cqm_txe_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 rate;\n\tu32 pkts;\n\tu32 intvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_default_beacon_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint link_id;\n\tu8 key_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_default_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint link_id;\n\tu8 key_index;\n\tbool unicast;\n\tbool multicast;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_default_mgmt_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint link_id;\n\tu8 key_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_epcs {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tbool val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_fils_aad {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 macaddr[6];\n\tu8 kek_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_hw_timestamp {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 macaddr[6];\n\tbool enable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_mac_acl {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 acl_policy;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_mcast_rate {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint mcast_rate[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_monitor_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_multicast_to_unicast {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tbool enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_noack_map {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 noack_map;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_pmk {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 aa[6];\n\tu8 pmk_len;\n\tu8 pmk_r0_name_len;\n\tu32 __data_loc_pmk;\n\tu32 __data_loc_pmk_r0_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_power_mgmt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tbool enabled;\n\tint timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_qos_map {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 num_des;\n\tu8 dscp_exception[42];\n\tu8 up[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_radar_background {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_sar_specs {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu16 type;\n\tu16 num;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_tid_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_ttlm {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dlink[16];\n\tu8 ulink[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_tx_power {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tint radio_idx;\n\tenum nl80211_tx_power_setting type;\n\tint mbm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_txq_params {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_ac ac;\n\tu16 txop;\n\tu16 cwmin;\n\tu16 cwmax;\n\tu8 aifs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_wiphy_params {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint radio_idx;\n\tu32 changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_start_ap {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tint beacon_interval;\n\tint dtim_period;\n\tchar ssid[33];\n\tenum nl80211_hidden_ssid hidden_ssid;\n\tu32 wpa_ver;\n\tbool privacy;\n\tenum nl80211_auth_type auth_type;\n\tint inactivity_timeout;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_start_nan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu8 master_pref;\n\tu8 bands;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_start_radar_detection {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tu32 cac_time_ms;\n\tint link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_stop_ap {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_suspend {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool any;\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\tbool valid_wow;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_cancel_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tu8 oper_class;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu16 punctured;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_mgmt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tint link_id;\n\tu8 action_code;\n\tu8 dialog_token;\n\tu16 status_code;\n\tu32 peer_capability;\n\tbool initiator;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_oper {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tenum nl80211_tdls_operation oper;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tx_control_port {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dest[6];\n\t__be16 proto;\n\tbool unencrypted;\n\tint link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_connect_params {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_ft_ies {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 md;\n\tu32 __data_loc_ie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_mesh_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 min_discovery_timeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tbool dot11MeshNolearn;\n\tu32 mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_mgmt_frame_registrations {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu16 global_stypes;\n\tu16 interface_stypes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_owe_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu16 status;\n\tu32 __data_loc_ie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_drop_region {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int from;\n\tunsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_sync {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_status;\n\tu32 __data_loc_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_register_class {\n\tstruct trace_entry ent;\n\tu32 version;\n\tlong unsigned int family;\n\tshort unsigned int protocol;\n\tshort unsigned int port;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_async {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_block {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bool {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bulk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tu32 __data_loc_buf;\n\tint val_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_reg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_release_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu16 tids;\n\tint num_frames;\n\tint reason;\n\tbool more_data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_buf_alloc {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tsize_t callsize;\n\tsize_t recvsize;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_call_rpcerror {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint tk_status;\n\tint rpc_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_class {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_clone_err {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tlong unsigned int xprtsec;\n\tlong unsigned int flags;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new_err {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_failure {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_reply_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 __data_loc_progname;\n\tu32 version;\n\tu32 __data_loc_procname;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_request {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tbool async;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_socket_nospace {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int total;\n\tunsigned int remaining;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_stats_latency {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tlong unsigned int backlog;\n\tlong unsigned int rtt;\n\tlong unsigned int execute;\n\tu32 xprt_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_queued {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tlong unsigned int timeout;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tu32 __data_loc_q_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_running {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *action;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_tls_class {\n\tstruct trace_entry ent;\n\tlong unsigned int requested_policy;\n\tu32 version;\n\tu32 __data_loc_servername;\n\tu32 __data_loc_progname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_alignment {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t offset;\n\tunsigned int copied;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_overflow {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t requested;\n\tconst void *end;\n\tconst void *p;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_lifetime_class {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_getport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int bind_version;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_setport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tshort unsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_unregister {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_bad_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 expected;\n\tu32 received;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_context {\n\tstruct trace_entry ent;\n\tlong unsigned int expiry;\n\tlong unsigned int now;\n\tunsigned int timeout;\n\tu32 window_size;\n\tint len;\n\tu32 __data_loc_acceptor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_createauth {\n\tstruct trace_entry ent;\n\tunsigned int flavor;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_ctx_class {\n\tstruct trace_entry ent;\n\tconst void *cred;\n\tlong unsigned int service;\n\tu32 __data_loc_principal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_gssapi_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 maj_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_import_ctx {\n\tstruct trace_entry ent;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_need_reencode {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seq_xmit;\n\tu32 seqno;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_oid_to_mech {\n\tstruct trace_entry ent;\n\tu32 __data_loc_oid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_accept_upcall {\n\tstruct trace_entry ent;\n\tu32 minor_status;\n\tlong unsigned int major_status;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 seqno;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_gssapi_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 maj_stat;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_bad {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_low {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_unwrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_wrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_unwrap_failed {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_result {\n\tstruct trace_entry ent;\n\tu32 uid;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_update_slack {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tconst void *auth;\n\tunsigned int rslack;\n\tunsigned int ralign;\n\tunsigned int verfsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_internal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flags;\n\tint usage_count;\n\tint disable_depth;\n\tint runtime_auto;\n\tint request_pending;\n\tint irq_safe;\n\tint child_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_return_int {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int ip;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\ts32 node_id;\n\ts32 mm_cid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_alarm_irq_enable {\n\tstruct trace_entry ent;\n\tunsigned int enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_freq {\n\tstruct trace_entry ent;\n\tint freq;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_state {\n\tstruct trace_entry ent;\n\tint enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_offset_class {\n\tstruct trace_entry ent;\n\tlong int offset;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_time_alarm_class {\n\tstruct trace_entry ent;\n\ttime64_t secs;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_timer_class {\n\tstruct trace_entry ent;\n\tstruct rtc_timer *timer;\n\tktime_t expires;\n\tktime_t period;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_bypass_lb {\n\tstruct trace_entry ent;\n\t__u32 node;\n\t__u32 nr_cpus;\n\t__u32 nr_tasks;\n\t__u32 nr_balanced;\n\t__u32 before_min;\n\t__u32 before_max;\n\t__u32 after_min;\n\t__u32 after_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_dump {\n\tstruct trace_entry ent;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\t__s64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *worker;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_move_numa {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_numa_pair_template {\n\tstruct trace_entry ent;\n\tpid_t src_pid;\n\tpid_t src_tgid;\n\tpid_t src_ngid;\n\tint src_cpu;\n\tint src_nid;\n\tpid_t dst_pid;\n\tpid_t dst_tgid;\n\tpid_t dst_ngid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_prepare_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_interp;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exit {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tbool group_dead;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tu32 __data_loc_parent_comm;\n\tpid_t parent_pid;\n\tu32 __data_loc_child_comm;\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_cpuset_numa {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tlong unsigned int mem_allowed[1];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_vma_numa {\n\tstruct trace_entry ent;\n\tlong unsigned int numa_scan_offset;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tenum numa_vmaskip_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 runtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_selinux_audited {\n\tstruct trace_entry ent;\n\tu32 requested;\n\tu32 denied;\n\tu32 audited;\n\tint result;\n\tu32 __data_loc_scontext;\n\tu32 __data_loc_tcontext;\n\tu32 __data_loc_tclass;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sk_data_ready {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 family;\n\t__u16 protocol;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 flags;\n\t__u16 addr;\n\t__u8 command;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 read_write;\n\t__u8 command;\n\t__s16 res;\n\t__u32 protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int sysctl_mem[3];\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_msg_length {\n\tstruct trace_entry ent;\n\tvoid *sk;\n\t__u16 family;\n\t__u16 protocol;\n\tint ret;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sta_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sta_flag_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tbool enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_station_add_change {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tu32 sta_flags_mask;\n\tu32 sta_flags_set;\n\tu32 sta_modify_mask;\n\tint listen_interval;\n\tu16 capability;\n\tu16 aid;\n\tu8 plink_action;\n\tu8 plink_state;\n\tu8 uapsd_queues;\n\tu8 max_sp;\n\tu8 opmode_notif;\n\tbool opmode_notif_used;\n\tu8 ht_capa[26];\n\tu8 vht_capa[12];\n\tchar vlan[16];\n\tu32 __data_loc_supported_rates;\n\tu32 __data_loc_ext_capab;\n\tu32 __data_loc_supported_channels;\n\tu32 __data_loc_supported_oper_classes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_station_del {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tu8 subtype;\n\tu16 reason_code;\n\tint link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_stop_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu16 queue;\n\tu32 reason;\n\tint refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_alloc_arg_err {\n\tstruct trace_entry ent;\n\tunsigned int requested;\n\tunsigned int allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int svc_status;\n\tlong unsigned int auth_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_deferred_event {\n\tstruct trace_entry ent;\n\tconst void *dr;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_pool_thread_event {\n\tstruct trace_entry ent;\n\tunsigned int pool_id;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_process {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 vers;\n\tu32 proc;\n\tu32 __data_loc_service;\n\tu32 __data_loc_procedure;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_replace_page_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tconst void *begin;\n\tconst void *respages;\n\tconst void *nextpage;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tint status;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_stats_latency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int execute;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_unregister {\n\tstruct trace_entry ent;\n\tu32 version;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_msg_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_accept {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_service;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_create_err {\n\tstruct trace_entry ent;\n\tlong int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_dequeue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tlong unsigned int wakeup;\n\tlong unsigned int qtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_enqueue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_accept_class {\n\tstruct trace_entry ent;\n\tlong int status;\n\tu32 __data_loc_service;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_class {\n\tstruct trace_entry ent;\n\tssize_t result;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_lifetime_class {\n\tstruct trace_entry ent;\n\tunsigned int netns_ino;\n\tconst void *svsk;\n\tconst void *sk;\n\tlong unsigned int type;\n\tlong unsigned int family;\n\tlong unsigned int state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_marker {\n\tstruct trace_entry ent;\n\tunsigned int length;\n\tbool last;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_recv_short {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_state {\n\tstruct trace_entry ent;\n\tlong unsigned int socket_state;\n\tlong unsigned int sock_state;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_swiotlb_bounced {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu64 dma_mask;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tbool force;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tu64 clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_prctl_unknown {\n\tstruct trace_entry ent;\n\tint option;\n\tlong unsigned int arg2;\n\tlong unsigned int arg3;\n\tlong unsigned int arg4;\n\tlong unsigned int arg5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tasklet {\n\tstruct trace_entry ent;\n\tvoid *tasklet;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_ao_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\t__u8 keyid;\n\t__u8 rnext;\n\t__u8 maclen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_cong_state_set {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u8 cong_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_hash_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\t__u64 sock_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_ssthresh;\n\t__u32 window_clamp;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_send_reset {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\tenum sk_rst_reason reason;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_sendmsg_locked {\n\tstruct trace_entry ent;\n\tconst void *skb_addr;\n\tint skb_len;\n\tint msg_left;\n\tint size_goal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_temperature {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint temp_prev;\n\tint temp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_zone_trip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint trip;\n\tenum thermal_trip_type trip_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_base_idle {\n\tstruct trace_entry ent;\n\tbool is_idle;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int bucket_expiry;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tlb_flush {\n\tstruct trace_entry ent;\n\tint reason;\n\tlong unsigned int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tls_contenttype {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_child_parent {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_cpu_parent {\n\tstruct trace_entry ent;\n\tvoid *parent;\n\tunsigned int cpu;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_cpugroup {\n\tstruct trace_entry ent;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_and_cpu {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tu32 childmask;\n\tu8 active;\n\tu8 migrator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_set {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_handle_remote {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_idle {\n\tstruct trace_entry ent;\n\tu64 nextevt;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_update_events {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *group;\n\tu64 nextevt;\n\tu64 group_next_expiry;\n\tu64 child_evt_expiry;\n\tunsigned int group_lvl;\n\tunsigned int child_evtcpu;\n\tu8 child_active;\n\tu8 group_active;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_usb_core_log_usb_device {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum usb_device_speed speed;\n\tenum usb_device_state state;\n\tshort unsigned int bus_mA;\n\tunsigned int authorized;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_activate {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_managed;\n\tbool can_reserve;\n\tbool reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_alloc {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tbool reserved;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_alloc_managed {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_config {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tunsigned int cpu;\n\tunsigned int apicdest;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_free_moved {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int cpu;\n\tunsigned int vector;\n\tbool is_managed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_mod {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tunsigned int cpu;\n\tunsigned int prev_vector;\n\tunsigned int prev_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_reserve {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_setup {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_legacy;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_teardown {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_managed;\n\tbool has_reserved;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_virtio_gpu_cmd {\n\tstruct trace_entry ent;\n\tint dev;\n\tunsigned int vq;\n\tu32 __data_loc_name;\n\tu32 type;\n\tu32 flags;\n\tu64 fence_id;\n\tu32 ctx_id;\n\tu32 num_free;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vlv_fifo_size {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 sprite0_start;\n\tu32 sprite1_start;\n\tu32 fifo_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vlv_wm {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tchar pipe_name;\n\tu32 frame;\n\tu32 scanline;\n\tu32 level;\n\tu32 cxsr;\n\tu32 primary;\n\tu32 sprite0;\n\tu32 sprite1;\n\tu32 cursor;\n\tu32 sr_plane;\n\tu32 sr_cursor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu16 queue;\n\tu32 reason;\n\tint refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_delayed_work_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tvoid *instance;\n\tvoid *func;\n\tlong unsigned int delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_enabled_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_hrtimer_work_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tvoid *instance;\n\tvoid *func;\n\tktime_t delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_id_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu64 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_netdev_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_netdev_id_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu64 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_netdev_mac_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_only_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_wdev_cookie_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_wdev_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_wdev_link_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tunsigned int link_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_work_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tvoid *instance;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_work_worker_start {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tu32 __data_loc_workqueue;\n\tint req_cpu;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_folio_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_x86_fpu {\n\tstruct trace_entry ent;\n\tstruct fpu *fpu;\n\tbool load_fpu;\n\tu64 xfeatures;\n\tu64 xcomp_bv;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_x86_irq_vector {\n\tstruct trace_entry ent;\n\tint vector;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tunsigned int xdp_pass;\n\tunsigned int xdp_drop;\n\tunsigned int xdp_redirect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_dbc_log_request {\n\tstruct trace_entry ent;\n\tstruct dbc_request *req;\n\tbool dir;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctrl_ctx {\n\tstruct trace_entry ent;\n\tu32 drop;\n\tu32 add;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctx {\n\tstruct trace_entry ent;\n\tint ctx_64;\n\tunsigned int ctx_type;\n\tdma_addr_t ctx_dma;\n\tu8 *ctx_va;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_doorbell {\n\tstruct trace_entry ent;\n\tu32 slot;\n\tu32 doorbell;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ep_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu64 deq;\n\tu32 tx_info;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_free_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint slot_id;\n\tu16 current_mel;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_portsc {\n\tstruct trace_entry ent;\n\tu32 busnum;\n\tu32 portnum;\n\tu32 portsc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ring {\n\tstruct trace_entry ent;\n\tu32 type;\n\tvoid *ring;\n\tdma_addr_t enq;\n\tdma_addr_t deq;\n\tunsigned int num_segs;\n\tunsigned int stream_id;\n\tunsigned int cycle_state;\n\tunsigned int bounce_buf_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_slot_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu32 tt_info;\n\tu32 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_stream_ctx {\n\tstruct trace_entry ent;\n\tunsigned int stream_id;\n\tu64 stream_ring;\n\tdma_addr_t ctx_array_dma;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_trb {\n\tstruct trace_entry ent;\n\tdma_addr_t dma;\n\tu32 type;\n\tu32 field0;\n\tu32 field1;\n\tu32 field2;\n\tu32 field3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_urb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tvoid *urb;\n\tunsigned int pipe;\n\tunsigned int stream;\n\tint status;\n\tunsigned int flags;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tint length;\n\tint actual;\n\tint epnum;\n\tint dir_in;\n\tint type;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint devnum;\n\tint state;\n\tint speed;\n\tu8 portnum;\n\tu8 level;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_cong_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tbool wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_ping {\n\tstruct trace_entry ent;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_reserve {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_retransmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint ntrans;\n\tint version;\n\tlong unsigned int timeout;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_transmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_writelock_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_data_ready {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event {\n\tstruct trace_entry ent;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event_done {\n\tstruct trace_entry ent;\n\tint error;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_data {\n\tstruct trace_entry ent;\n\tssize_t err;\n\tsize_t total;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tu32 xid;\n\tlong unsigned int copied;\n\tunsigned int reclen;\n\tunsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n\tint flags;\n};\n\nstruct trace_func_repeats {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int count;\n\tu64 ts_last_call;\n};\n\nstruct trace_kprobe {\n\tstruct dyn_event devent;\n\tstruct kretprobe rp;\n\tlong unsigned int *nhit;\n\tconst char *symbol;\n\tstruct trace_probe tp;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n};\n\nstruct trace_min_max_param {\n\tstruct mutex *lock;\n\tu64 *val;\n\tu64 *min;\n\tu64 *max;\n};\n\nstruct trace_mod_entry {\n\tlong unsigned int mod_addr;\n\tchar mod_name[56];\n};\n\nstruct trace_module_delta {\n\tstruct callback_head rcu;\n\tlong int delta[0];\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tbool fail;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nunion upper_chunk;\n\nstruct trace_pid_list {\n\tseqcount_raw_spinlock_t seqcount;\n\traw_spinlock_t lock;\n\tstruct irq_work refill_irqwork;\n\tunion upper_chunk *upper[256];\n\tunion upper_chunk *upper_list;\n\tunion lower_chunk *lower_list;\n\tint free_upper_chunks;\n\tint free_lower_chunks;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nstruct trace_scratch {\n\tunsigned int clock_id;\n\tlong unsigned int text_addr;\n\tlong unsigned int nr_entries;\n\tstruct trace_mod_entry entries[0];\n};\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct eventfs_inode *ei;\n\tint ref_count;\n\tint nr_events;\n};\n\nstruct trace_vif_entry {\n\tenum nl80211_iftype vif_type;\n\tbool p2p;\n\tchar vif_name[16];\n} __attribute__((packed));\n\nstruct trace_switch_entry {\n\tstruct trace_vif_entry vif;\n\tunsigned int link_id;\n\tstruct trace_chandef_entry old_chandef;\n\tstruct trace_chandef_entry new_chandef;\n} __attribute__((packed));\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tchar *filename;\n\tstruct uprobe *uprobe;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int *nhits;\n\tstruct trace_probe tp;\n};\n\nstruct trace_user_buf {\n\tchar *buf;\n};\n\nstruct trace_user_buf_info {\n\tstruct trace_user_buf *tbuf;\n\tsize_t size;\n\tint ref;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct tracefs_inode {\n\tstruct inode vfs_inode;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tvoid *private;\n};\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct traceprobe_parse_context {\n\tstruct trace_event_call *event;\n\tconst char *funcname;\n\tconst struct btf_type *proto;\n\tconst struct btf_param *params;\n\ts32 nr_params;\n\tstruct btf *btf;\n\tconst struct btf_type *last_type;\n\tu32 last_bitoffs;\n\tu32 last_bitsize;\n\tstruct trace_probe *tp;\n\tunsigned int flags;\n\tint offset;\n};\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u64, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tstruct tracer_flags *default_flags;\n\tint enabled;\n\tbool print_max;\n\tbool allow_instances;\n\tbool noboot;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct tracers {\n\tstruct list_head list;\n\tstruct tracer *tracer;\n\tstruct tracer_flags *flags;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar *cmd;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tdepot_stack_handle_t handle;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct trampoline_header {\n\tu64 start;\n\tu64 efer;\n\tu32 cr4;\n\tu32 flags;\n\tu32 lock;\n};\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n};\n\ntypedef struct tree_desc_s tree_desc;\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsc_adjust {\n\ts64 bootval;\n\ts64 adjusted;\n\tlong unsigned int nextcheck;\n\tbool warned;\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct ttm_agp_backend {\n\tstruct ttm_tt ttm;\n\tstruct agp_memory *mem;\n\tstruct agp_bridge_data *bridge;\n};\n\nstruct ttm_backup_flags {\n\tu32 purge: 1;\n\tu32 writeback: 1;\n};\n\nstruct ttm_operation_ctx;\n\nstruct ttm_lru_walk_arg {\n\tstruct ttm_operation_ctx *ctx;\n\tstruct ww_acquire_ctx *ticket;\n\tbool trylock_only;\n};\n\nstruct ttm_lru_walk_ops;\n\nstruct ttm_lru_walk {\n\tconst struct ttm_lru_walk_ops *ops;\n\tstruct ttm_lru_walk_arg arg;\n};\n\nstruct ttm_place;\n\nstruct ttm_bo_evict_walk {\n\tstruct ttm_lru_walk walk;\n\tconst struct ttm_place *place;\n\tstruct ttm_buffer_object *evictor;\n\tstruct ttm_resource **res;\n\tlong unsigned int evicted;\n\tstruct dmem_cgroup_pool_state *limit_pool;\n\tbool try_low;\n\tbool hit_low;\n};\n\nstruct ttm_bo_kmap_obj {\n\tvoid *virtual;\n\tstruct page *page;\n\tenum {\n\t\tttm_bo_map_iomap = 129,\n\t\tttm_bo_map_vmap = 2,\n\t\tttm_bo_map_kmap = 3,\n\t\tttm_bo_map_premapped = 132,\n\t} bo_kmap_type;\n\tstruct ttm_buffer_object *bo;\n};\n\nstruct ttm_bo_lru_cursor;\n\ntypedef struct ttm_bo_lru_cursor *class_ttm_bo_lru_cursor_t;\n\nstruct ttm_resource_cursor {\n\tstruct ttm_resource_manager *man;\n\tstruct ttm_lru_item hitch;\n\tstruct list_head bulk_link;\n\tstruct ttm_lru_bulk_move *bulk;\n\tunsigned int mem_type;\n\tunsigned int priority;\n};\n\nstruct ttm_bo_lru_cursor {\n\tstruct ttm_resource_cursor res_curs;\n\tstruct ttm_buffer_object *bo;\n\tbool needs_unlock;\n\tstruct ttm_lru_walk_arg *arg;\n};\n\nstruct ttm_bo_shrink_flags {\n\tu32 purge: 1;\n\tu32 writeback: 1;\n\tu32 allow_move: 1;\n};\n\nstruct ttm_bo_swapout_walk {\n\tstruct ttm_lru_walk walk;\n\tgfp_t gfp_flags;\n\tbool hit_low;\n\tbool evict_low;\n};\n\nstruct ttm_placement;\n\nstruct ttm_device_funcs {\n\tstruct ttm_tt * (*ttm_tt_create)(struct ttm_buffer_object *, uint32_t);\n\tint (*ttm_tt_populate)(struct ttm_device *, struct ttm_tt *, struct ttm_operation_ctx *);\n\tvoid (*ttm_tt_unpopulate)(struct ttm_device *, struct ttm_tt *);\n\tvoid (*ttm_tt_destroy)(struct ttm_device *, struct ttm_tt *);\n\tbool (*eviction_valuable)(struct ttm_buffer_object *, const struct ttm_place *);\n\tvoid (*evict_flags)(struct ttm_buffer_object *, struct ttm_placement *);\n\tint (*move)(struct ttm_buffer_object *, bool, struct ttm_operation_ctx *, struct ttm_resource *, struct ttm_place *);\n\tvoid (*delete_mem_notify)(struct ttm_buffer_object *);\n\tvoid (*swap_notify)(struct ttm_buffer_object *);\n\tint (*io_mem_reserve)(struct ttm_device *, struct ttm_resource *);\n\tvoid (*io_mem_free)(struct ttm_device *, struct ttm_resource *);\n\tlong unsigned int (*io_mem_pfn)(struct ttm_buffer_object *, long unsigned int);\n\tint (*access_memory)(struct ttm_buffer_object *, long unsigned int, void *, int, int);\n\tvoid (*release_notify)(struct ttm_buffer_object *);\n};\n\nstruct ttm_global {\n\tstruct page *dummy_read_page;\n\tstruct list_head device_list;\n\tatomic_t bo_count;\n};\n\nstruct ttm_kmap_iter_linear_io {\n\tstruct ttm_kmap_iter base;\n\tstruct iosys_map dmap;\n\tbool needs_unmap;\n};\n\nstruct ttm_kmap_iter_ops {\n\tvoid (*map_local)(struct ttm_kmap_iter *, struct iosys_map *, long unsigned int);\n\tvoid (*unmap_local)(struct ttm_kmap_iter *, struct iosys_map *);\n\tbool maps_tt;\n};\n\nstruct ttm_lru_bulk_move_pos {\n\tstruct ttm_resource *first;\n\tstruct ttm_resource *last;\n};\n\nstruct ttm_lru_bulk_move {\n\tstruct ttm_lru_bulk_move_pos pos[36];\n\tstruct list_head cursor_list;\n};\n\nstruct ttm_lru_walk_ops {\n\ts64 (*process_bo)(struct ttm_lru_walk *, struct ttm_buffer_object *);\n};\n\nstruct ttm_operation_ctx {\n\tbool interruptible;\n\tbool no_wait_gpu;\n\tbool gfp_retry_mayfail;\n\tbool allow_res_evict;\n\tstruct dma_resv *resv;\n\tuint64_t bytes_moved;\n};\n\nstruct ttm_place {\n\tunsigned int fpfn;\n\tunsigned int lpfn;\n\tuint32_t mem_type;\n\tuint32_t flags;\n};\n\nstruct ttm_placement {\n\tunsigned int num_placement;\n\tconst struct ttm_place *placement;\n};\n\nstruct ttm_pool_alloc_state {\n\tstruct page **pages;\n\tstruct page **caching_divide;\n\tdma_addr_t *dma_addr;\n\tlong unsigned int remaining_pages;\n\tenum ttm_caching tt_caching;\n};\n\nstruct ttm_pool_dma {\n\tdma_addr_t addr;\n\tlong unsigned int vaddr;\n};\n\nstruct ttm_pool_tt_restore {\n\tstruct ttm_pool *pool;\n\tstruct ttm_pool_alloc_state snapshot_alloc;\n\tstruct page *alloced_page;\n\tdma_addr_t first_dma;\n\tlong unsigned int alloced_pages;\n\tlong unsigned int restored_pages;\n\tenum ttm_caching page_caching;\n\tunsigned int order;\n};\n\nstruct ttm_range_manager {\n\tstruct ttm_resource_manager manager;\n\tstruct drm_mm mm;\n\tspinlock_t lock;\n};\n\nstruct ttm_range_mgr_node {\n\tstruct ttm_resource base;\n\tstruct drm_mm_node mm_nodes[0];\n};\n\nstruct ttm_resource_manager_func {\n\tint (*alloc)(struct ttm_resource_manager *, struct ttm_buffer_object *, const struct ttm_place *, struct ttm_resource **);\n\tvoid (*free)(struct ttm_resource_manager *, struct ttm_resource *);\n\tbool (*intersects)(struct ttm_resource_manager *, struct ttm_resource *, const struct ttm_place *, size_t);\n\tbool (*compatible)(struct ttm_resource_manager *, struct ttm_resource *, const struct ttm_place *, size_t);\n\tvoid (*debug)(struct ttm_resource_manager *, struct drm_printer *);\n};\n\nstruct ttm_transfer_obj {\n\tstruct ttm_buffer_object base;\n\tstruct ttm_buffer_object *bo;\n};\n\nstruct ttm_validate_buffer {\n\tstruct list_head head;\n\tstruct ttm_buffer_object *bo;\n\tunsigned int num_shared;\n};\n\nstruct tty_audit_buf {\n\tstruct mutex mutex;\n\tdev_t dev;\n\tbool icanon;\n\tsize_t valid;\n\tu8 *data;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct tun_security_struct {\n\tu32 sid;\n};\n\nstruct tuple_flags {\n\tu_int link_space: 4;\n\tu_int has_link: 1;\n\tu_int mfc_fn: 3;\n\tu_int space: 4;\n};\n\nstruct tuple_t {\n\tu_int Attributes;\n\tcisdata_t DesiredTuple;\n\tu_int Flags;\n\tu_int LinkOffset;\n\tu_int CISOffset;\n\tcisdata_t TupleCode;\n\tcisdata_t TupleLink;\n\tcisdata_t TupleOffset;\n\tcisdata_t TupleDataMax;\n\tcisdata_t TupleDataLen;\n\tcisdata_t *TupleData;\n};\n\nstruct video_levels;\n\nstruct tv_mode {\n\tconst char *name;\n\tu32 clock;\n\tu16 refresh;\n\tu8 oversample;\n\tu8 hsync_end;\n\tu16 hblank_start;\n\tu16 hblank_end;\n\tu16 htotal;\n\tbool progressive: 1;\n\tbool trilevel_sync: 1;\n\tbool component_only: 1;\n\tu8 vsync_start_f1;\n\tu8 vsync_start_f2;\n\tu8 vsync_len;\n\tbool veq_ena: 1;\n\tu8 veq_start_f1;\n\tu8 veq_start_f2;\n\tu8 veq_len;\n\tu8 vi_end_f1;\n\tu8 vi_end_f2;\n\tu16 nbr_end;\n\tbool burst_ena: 1;\n\tu8 hburst_start;\n\tu8 hburst_len;\n\tu8 vburst_start_f1;\n\tu16 vburst_end_f1;\n\tu8 vburst_start_f2;\n\tu16 vburst_end_f2;\n\tu8 vburst_start_f3;\n\tu16 vburst_end_f3;\n\tu8 vburst_start_f4;\n\tu16 vburst_end_f4;\n\tu16 dda2_size;\n\tu16 dda3_size;\n\tu8 dda1_inc;\n\tu16 dda2_inc;\n\tu16 dda3_inc;\n\tu32 sc_reset;\n\tbool pal_burst: 1;\n\tconst struct video_levels *composite_levels;\n\tconst struct video_levels *svideo_levels;\n\tconst struct color_conversion *composite_color;\n\tconst struct color_conversion *svideo_color;\n\tconst u32 *filter_table;\n};\n\nstruct tx_ring_info {\n\tstruct sk_buff *skb;\n\tlong unsigned int flags;\n\tdma_addr_t mapaddr;\n\t__u32 maplen;\n};\n\nstruct txq_info {\n\tstruct fq_tin tin;\n\tstruct codel_vars def_cvars;\n\tstruct codel_stats cstats;\n\tu16 schedule_round;\n\tstruct list_head schedule_order;\n\tstruct sk_buff_head frags;\n\tlong unsigned int flags;\n\tstruct ieee80211_txq txq;\n};\n\nstruct type_datum {\n\tu32 value;\n\tu32 bounds;\n\tunsigned char primary;\n\tunsigned char attribute;\n};\n\nstruct type_set {\n\tstruct ebitmap types;\n\tstruct ebitmap negset;\n\tu32 flags;\n};\n\nstruct typec_connector {\n\tvoid (*attach)(struct typec_connector *, struct device *);\n\tvoid (*deattach)(struct typec_connector *, struct device *);\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n};\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n\tvoid (*setup_timer)(struct uart_8250_port *);\n};\n\ntypedef struct uart_8250_port *class_serial8250_rpm_t;\n\nstruct mctrl_gpios;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tu16 bugs;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tu16 lsr_saved_flags;\n\tu16 lsr_save_mask;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *, bool);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *, bool);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*start_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\ntypedef struct uart_port *class_uart_port_lock_irq_t;\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct uc_css_header {\n\tu32 module_type;\n\tu32 header_size_dw;\n\tu32 header_version;\n\tu32 module_id;\n\tu32 module_vendor;\n\tu32 date;\n\tu32 size_dw;\n\tu32 key_size_dw;\n\tu32 modulus_size_dw;\n\tu32 exponent_size_dw;\n\tu32 time;\n\tchar username[8];\n\tchar buildnumber[12];\n\tu32 sw_version;\n\tu32 vf_version;\n\tu32 reserved0[12];\n\tunion {\n\t\tu32 private_data_size;\n\t\tu32 reserved1;\n\t};\n\tu32 header_info;\n};\n\nstruct uc_fw_blob {\n\tconst char *path;\n\tbool legacy;\n\tu8 major;\n\tu8 minor;\n\tu8 patch;\n\tbool has_gsc_headers;\n} __attribute__((packed));\n\nstruct uc_fw_platform_requirement {\n\tenum intel_platform p;\n\tu8 rev;\n\tconst struct uc_fw_blob blob;\n} __attribute__((packed));\n\nstruct ucode_cpu_info {\n\tstruct cpu_signature cpu_sig;\n\tvoid *mc;\n};\n\nstruct ucode_patch {\n\tstruct list_head plist;\n\tvoid *data;\n\tunsigned int size;\n\tu32 patch_id;\n\tu16 equiv_cpu;\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[10];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n\tu16 len;\n\tbool is_linear;\n\tbool csum_unnecessary;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 64;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct uhci_td;\n\nstruct uhci_qh;\n\nstruct uhci_hcd {\n\tlong unsigned int io_addr;\n\tvoid *regs;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *td_pool;\n\tstruct uhci_td *term_td;\n\tstruct uhci_qh *skelqh[11];\n\tstruct uhci_qh *next_qh;\n\tspinlock_t lock;\n\tdma_addr_t frame_dma_handle;\n\t__le32 *frame;\n\tvoid **frame_cpu;\n\tenum uhci_rh_state rh_state;\n\tlong unsigned int auto_stop_time;\n\tunsigned int frame_number;\n\tunsigned int is_stopped;\n\tunsigned int last_iso_frame;\n\tunsigned int cur_iso_frame;\n\tunsigned int scan_in_progress: 1;\n\tunsigned int need_rescan: 1;\n\tunsigned int dead: 1;\n\tunsigned int RD_enable: 1;\n\tunsigned int is_initialized: 1;\n\tunsigned int fsbr_is_on: 1;\n\tunsigned int fsbr_is_wanted: 1;\n\tunsigned int fsbr_expiring: 1;\n\tstruct timer_list fsbr_timer;\n\tunsigned int oc_low: 1;\n\tunsigned int wait_for_hp: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int is_aspeed: 1;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int resuming_ports;\n\tlong unsigned int ports_timeout;\n\tstruct list_head idle_qh_list;\n\tint rh_numports;\n\twait_queue_head_t waitqh;\n\tint num_waiting;\n\tint total_load;\n\tshort int load[32];\n\tstruct clk *clk;\n\tstruct reset_control *rsts;\n\tvoid (*reset_hc)(struct uhci_hcd *);\n\tint (*check_and_reset_hc)(struct uhci_hcd *);\n\tvoid (*configure_hc)(struct uhci_hcd *);\n\tint (*resume_detect_interrupts_are_broken)(struct uhci_hcd *);\n\tint (*global_suspend_mode_is_broken)(struct uhci_hcd *);\n};\n\nstruct usb_iso_packet_descriptor;\n\nstruct uhci_qh {\n\t__le32 link;\n\t__le32 element;\n\tdma_addr_t dma_handle;\n\tstruct list_head node;\n\tstruct usb_host_endpoint *hep;\n\tstruct usb_device *udev;\n\tstruct list_head queue;\n\tstruct uhci_td *dummy_td;\n\tstruct uhci_td *post_td;\n\tstruct usb_iso_packet_descriptor *iso_packet_desc;\n\tlong unsigned int advance_jiffies;\n\tunsigned int unlink_frame;\n\tunsigned int period;\n\tshort int phase;\n\tshort int load;\n\tunsigned int iso_frame;\n\tint state;\n\tint type;\n\tint skel;\n\tunsigned int initial_toggle: 1;\n\tunsigned int needs_fixup: 1;\n\tunsigned int is_stopped: 1;\n\tunsigned int wait_expired: 1;\n\tunsigned int bandwidth_reserved: 1;\n};\n\nstruct uhci_td {\n\t__le32 link;\n\t__le32 status;\n\t__le32 token;\n\t__le32 buffer;\n\tdma_addr_t dma_handle;\n\tstruct list_head list;\n\tint frame;\n\tstruct list_head fl_list;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct uncore_discovery_domain {\n\tu32 discovery_base;\n\tbool base_is_pci;\n\tint (*global_init)(u64);\n\tint *units_ignore;\n};\n\nstruct uncore_event_desc {\n\tstruct device_attribute attr;\n\tconst char *config;\n};\n\nstruct uncore_global_discovery {\n\tunion {\n\t\tu64 table1;\n\t\tstruct {\n\t\t\tu64 type: 8;\n\t\t\tu64 stride: 8;\n\t\t\tu64 max_units: 10;\n\t\t\tu64 __reserved_1: 36;\n\t\t\tu64 access_type: 2;\n\t\t};\n\t};\n\tu64 ctl;\n\tunion {\n\t\tu64 table3;\n\t\tstruct {\n\t\t\tu64 status_offset: 8;\n\t\t\tu64 num_status: 16;\n\t\t\tu64 __reserved_2: 40;\n\t\t};\n\t};\n};\n\nstruct uncore_iio_topology {\n\tint pci_bus_no;\n\tint segment;\n};\n\nstruct uncore_plat_init {\n\tvoid (*cpu_init)(void);\n\tint (*pci_init)(void);\n\tvoid (*mmio_init)(void);\n\tstruct uncore_discovery_domain domain[2];\n};\n\nstruct uncore_unit_discovery {\n\tunion {\n\t\tu64 table1;\n\t\tstruct {\n\t\t\tu64 num_regs: 8;\n\t\t\tu64 ctl_offset: 8;\n\t\t\tu64 bit_width: 8;\n\t\t\tu64 ctr_offset: 8;\n\t\t\tu64 status_offset: 8;\n\t\t\tu64 __reserved_1: 22;\n\t\t\tu64 access_type: 2;\n\t\t};\n\t};\n\tu64 ctl;\n\tunion {\n\t\tu64 table3;\n\t\tstruct {\n\t\t\tu64 box_type: 16;\n\t\t\tu64 box_id: 16;\n\t\t\tu64 __reserved_2: 32;\n\t\t};\n\t};\n};\n\nstruct uncore_upi_topology {\n\tint die_to;\n\tint pmu_idx_to;\n\tint enabled;\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct unity_map_entry {\n\tstruct list_head list;\n\tu16 devid_start;\n\tu16 devid_end;\n\tu64 address_start;\n\tu64 address_end;\n\tint prot;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_domain {\n\tstruct auth_domain h;\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_gid {\n\tstruct cache_head h;\n\tkuid_t uid;\n\tstruct group_info *gi;\n\tstruct callback_head rcu;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 secid;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\nstruct unsol_bcast_probe_resp_data {\n\tstruct callback_head callback_head;\n\tint len;\n\tu8 data[0];\n};\n\nstruct unwind_cache {\n\tlong unsigned int unwind_completed;\n\tunsigned int nr_entries;\n\tlong unsigned int entries[0];\n};\n\nstruct unwind_stacktrace {\n\tunsigned int nr;\n\tlong unsigned int *entries;\n};\n\nstruct unwind_state {\n\tstruct stack_info stack_info;\n\tlong unsigned int stack_mask;\n\tstruct task_struct *task;\n\tint graph_idx;\n\tstruct llist_node *kr_cur;\n\tbool error;\n\tbool signal;\n\tbool full_regs;\n\tlong unsigned int sp;\n\tlong unsigned int bp;\n\tlong unsigned int ip;\n\tstruct pt_regs *regs;\n\tstruct pt_regs *prev_regs;\n};\n\nstruct unwind_user_frame {\n\ts32 cfa_off;\n\ts32 ra_off;\n\ts32 fp_off;\n\tbool use_fp;\n};\n\nstruct unwind_user_state {\n\tlong unsigned int ip;\n\tlong unsigned int sp;\n\tlong unsigned int fp;\n\tunsigned int ws;\n\tenum unwind_user_type current_type;\n\tunsigned int available_types;\n\tbool topmost;\n\tbool done;\n};\n\nstruct unwind_work;\n\ntypedef void (*unwind_callback_t)(struct unwind_work *, struct unwind_stacktrace *, u64);\n\nstruct unwind_work {\n\tstruct list_head list;\n\tunwind_callback_t func;\n\tint bit;\n};\n\nstruct update_classid_context {\n\tu32 classid;\n\tunsigned int batch;\n};\n\nunion upper_chunk {\n\tunion upper_chunk *next;\n\tunion lower_chunk *data[256];\n};\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct list_head consumers;\n\tstruct inode *inode;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n\tint dsize;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_syscall_args {\n\tlong unsigned int ax;\n\tlong unsigned int r11;\n\tlong unsigned int cx;\n\tlong unsigned int retaddr;\n};\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunsigned int depth;\n\tstruct return_instance *return_instances;\n\tstruct return_instance *ri_pool;\n\tstruct timer_list ri_timer;\n\tseqcount_t ri_seqcount;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tbool signal_denied;\n\tstruct arch_uprobe *auprobe;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\nstruct uprobe_trampoline {\n\tstruct hlist_node node;\n\tlong unsigned int vaddr;\n};\n\nstruct uprobe_xol_ops {\n\tbool (*emulate)(struct arch_uprobe *, struct pt_regs *);\n\tint (*pre_xol)(struct arch_uprobe *, struct pt_regs *);\n\tint (*post_xol)(struct arch_uprobe *, struct pt_regs *);\n\tvoid (*abort)(struct arch_uprobe *, struct pt_regs *);\n};\n\ntypedef void (*usb_complete_t)(struct urb *);\n\nstruct usb_iso_packet_descriptor {\n\tunsigned int offset;\n\tunsigned int length;\n\tunsigned int actual_length;\n\tint status;\n};\n\nstruct usb_anchor;\n\nstruct urb {\n\tstruct kref kref;\n\tint unlinked;\n\tvoid *hcpriv;\n\tatomic_t use_count;\n\tatomic_t reject;\n\tstruct list_head urb_list;\n\tstruct list_head anchor_list;\n\tstruct usb_anchor *anchor;\n\tstruct usb_device *dev;\n\tstruct usb_host_endpoint *ep;\n\tunsigned int pipe;\n\tunsigned int stream_id;\n\tint status;\n\tunsigned int transfer_flags;\n\tvoid *transfer_buffer;\n\tdma_addr_t transfer_dma;\n\tstruct scatterlist *sg;\n\tstruct sg_table *sgt;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tu32 transfer_buffer_length;\n\tu32 actual_length;\n\tunsigned char *setup_packet;\n\tdma_addr_t setup_dma;\n\tint start_frame;\n\tint number_of_packets;\n\tint interval;\n\tint error_count;\n\tvoid *context;\n\tusb_complete_t complete;\n\tstruct usb_iso_packet_descriptor iso_frame_desc[0];\n};\n\nstruct urb_priv {\n\tstruct ed *ed;\n\tu16 length;\n\tu16 td_cnt;\n\tstruct list_head pending;\n\tstruct td *td[0];\n};\n\nstruct urb_priv___2 {\n\tstruct list_head node;\n\tstruct urb *urb;\n\tstruct uhci_qh *qh;\n\tstruct list_head td_list;\n\tunsigned int fsbr: 1;\n};\n\nstruct xhci_segment;\n\nstruct xhci_td {\n\tstruct list_head td_list;\n\tstruct list_head cancelled_td_list;\n\tint status;\n\tenum xhci_cancelled_td_status cancel_status;\n\tstruct urb *urb;\n\tstruct xhci_segment *start_seg;\n\tunion xhci_trb *start_trb;\n\tstruct xhci_segment *end_seg;\n\tunion xhci_trb *end_trb;\n\tstruct xhci_segment *bounce_seg;\n\tbool urb_length_set;\n\tbool error_mid_td;\n};\n\nstruct urb_priv___3 {\n\tint num_tds;\n\tint num_tds_done;\n\tstruct xhci_td td[0];\n};\n\ntypedef struct urb_priv urb_priv_t;\n\nstruct uretprobe_syscall_args {\n\tlong unsigned int r11;\n\tlong unsigned int cx;\n\tlong unsigned int ax;\n};\n\nstruct us_data;\n\ntypedef int (*trans_cmnd)(struct scsi_cmnd *, struct us_data *);\n\ntypedef int (*trans_reset)(struct us_data *);\n\ntypedef void (*proto_cmnd)(struct scsi_cmnd *, struct us_data *);\n\nstruct usb_sg_request {\n\tint status;\n\tsize_t bytes;\n\tspinlock_t lock;\n\tstruct usb_device *dev;\n\tint pipe;\n\tint entries;\n\tstruct urb **urbs;\n\tint count;\n\tstruct completion complete;\n};\n\ntypedef void (*extra_data_destructor)(void *);\n\ntypedef void (*pm_hook)(struct us_data *, int);\n\nstruct usb_interface;\n\nstruct us_unusual_dev;\n\nstruct usb_ctrlrequest;\n\nstruct us_data {\n\tstruct mutex dev_mutex;\n\tstruct usb_device *pusb_dev;\n\tstruct usb_interface *pusb_intf;\n\tconst struct us_unusual_dev *unusual_dev;\n\tu64 fflags;\n\tlong unsigned int dflags;\n\tunsigned int send_bulk_pipe;\n\tunsigned int recv_bulk_pipe;\n\tunsigned int send_ctrl_pipe;\n\tunsigned int recv_ctrl_pipe;\n\tunsigned int recv_intr_pipe;\n\tchar *transport_name;\n\tchar *protocol_name;\n\t__le32 bcs_signature;\n\tu8 subclass;\n\tu8 protocol;\n\tu8 max_lun;\n\tu8 ifnum;\n\tu8 ep_bInterval;\n\ttrans_cmnd transport;\n\ttrans_reset transport_reset;\n\tproto_cmnd proto_handler;\n\tstruct scsi_cmnd *srb;\n\tunsigned int tag;\n\tchar scsi_name[32];\n\tstruct urb *current_urb;\n\tstruct usb_ctrlrequest *cr;\n\tstruct usb_sg_request current_sg;\n\tunsigned char *iobuf;\n\tdma_addr_t iobuf_dma;\n\tstruct task_struct *ctl_thread;\n\tstruct completion cmnd_ready;\n\tstruct completion notify;\n\twait_queue_head_t delay_wait;\n\tstruct delayed_work scan_dwork;\n\tvoid *extra;\n\textra_data_destructor extra_destructor;\n\tpm_hook suspend_resume_hook;\n\tint use_last_sector_hacks;\n\tint last_sector_retries;\n};\n\nstruct us_unusual_dev {\n\tconst char *vendorName;\n\tconst char *productName;\n\t__u8 useProtocol;\n\t__u8 useTransport;\n\tint (*initFunction)(struct us_data *);\n};\n\nstruct usage_priority {\n\t__u32 usage;\n\tbool global;\n\tunsigned int slot_overwrite;\n};\n\nstruct usb2_lpm_parameters {\n\tunsigned int besl;\n\tint timeout;\n};\n\nstruct usb3_lpm_parameters {\n\tunsigned int mel;\n\tunsigned int pel;\n\tunsigned int sel;\n\tint timeout;\n};\n\nstruct usb_anchor {\n\tstruct list_head urb_list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tatomic_t suspend_wakeups;\n\tunsigned int poisoned: 1;\n};\n\nstruct usb_bos_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumDeviceCaps;\n} __attribute__((packed));\n\nstruct usb_bus {\n\tstruct device *controller;\n\tstruct device *sysdev;\n\tint busnum;\n\tconst char *bus_name;\n\tu8 uses_pio_for_control;\n\tu8 otg_port;\n\tunsigned int is_b_host: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int no_stop_on_short: 1;\n\tunsigned int no_sg_constraint: 1;\n\tunsigned int sg_tablesize;\n\tint devnum_next;\n\tstruct mutex devnum_next_mutex;\n\tlong unsigned int devmap[2];\n\tstruct usb_device *root_hub;\n\tstruct usb_bus *hs_companion;\n\tint bandwidth_allocated;\n\tint bandwidth_int_reqs;\n\tint bandwidth_isoc_reqs;\n\tunsigned int resuming_ports;\n\tstruct mon_bus *mon_bus;\n\tint monitored;\n};\n\nstruct usb_cdc_acm_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n};\n\nstruct usb_cdc_call_mgmt_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n\t__u8 bDataInterface;\n};\n\nstruct usb_cdc_country_functional_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iCountryCodeRelDate;\n\tunion {\n\t\t__le16 wCountryCode0;\n\t\tstruct {\n\t\t\tstruct {} __empty_wCountryCodes;\n\t\t\t__le16 wCountryCodes[0];\n\t\t};\n\t};\n};\n\nstruct usb_cdc_dmm_desc {\n\t__u8 bFunctionLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubtype;\n\t__u16 bcdVersion;\n\t__le16 wMaxCommand;\n} __attribute__((packed));\n\nstruct usb_cdc_ether_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iMACAddress;\n\t__le32 bmEthernetStatistics;\n\t__le16 wMaxSegmentSize;\n\t__le16 wNumberMCFilters;\n\t__u8 bNumberPowerFilters;\n} __attribute__((packed));\n\nstruct usb_cdc_header_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdCDC;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMVersion;\n\t__le16 wMaxControlMessage;\n\t__u8 bNumberFilters;\n\t__u8 bMaxFilterSize;\n\t__le16 wMaxSegmentSize;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_extended_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMExtendedVersion;\n\t__u8 bMaxOutstandingCommandMessages;\n\t__le16 wMTU;\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n\t__u8 bGUID[16];\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_detail_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bGuidDescriptorType;\n\t__u8 bDetailData[0];\n};\n\nstruct usb_cdc_ncm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdNcmVersion;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_network_terminal_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bEntityId;\n\t__u8 iName;\n\t__u8 bChannelIndex;\n\t__u8 bPhysicalInterface;\n};\n\nstruct usb_cdc_obex_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n} __attribute__((packed));\n\nstruct usb_cdc_union_desc;\n\nstruct usb_cdc_parsed_header {\n\tstruct usb_cdc_union_desc *usb_cdc_union_desc;\n\tstruct usb_cdc_header_desc *usb_cdc_header_desc;\n\tstruct usb_cdc_call_mgmt_descriptor *usb_cdc_call_mgmt_descriptor;\n\tstruct usb_cdc_acm_descriptor *usb_cdc_acm_descriptor;\n\tstruct usb_cdc_country_functional_desc *usb_cdc_country_functional_desc;\n\tstruct usb_cdc_network_terminal_desc *usb_cdc_network_terminal_desc;\n\tstruct usb_cdc_ether_desc *usb_cdc_ether_desc;\n\tstruct usb_cdc_dmm_desc *usb_cdc_dmm_desc;\n\tstruct usb_cdc_mdlm_desc *usb_cdc_mdlm_desc;\n\tstruct usb_cdc_mdlm_detail_desc *usb_cdc_mdlm_detail_desc;\n\tstruct usb_cdc_obex_desc *usb_cdc_obex_desc;\n\tstruct usb_cdc_ncm_desc *usb_cdc_ncm_desc;\n\tstruct usb_cdc_mbim_desc *usb_cdc_mbim_desc;\n\tstruct usb_cdc_mbim_extended_desc *usb_cdc_mbim_extended_desc;\n\tbool phonet_magic_present;\n};\n\nstruct usb_cdc_union_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bMasterInterface0;\n\tunion {\n\t\t__u8 bSlaveInterface0;\n\t\tstruct {\n\t\t\tstruct {} __empty_bSlaveInterfaces;\n\t\t\t__u8 bSlaveInterfaces[0];\n\t\t};\n\t};\n};\n\nstruct usb_charger_current {\n\tunsigned int sdp_min;\n\tunsigned int sdp_max;\n\tunsigned int dcp_min;\n\tunsigned int dcp_max;\n\tunsigned int cdp_min;\n\tunsigned int cdp_max;\n\tunsigned int aca_min;\n\tunsigned int aca_max;\n};\n\nstruct usb_class_driver {\n\tchar *name;\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tconst struct file_operations *fops;\n\tint minor_base;\n};\n\nstruct usb_config_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumInterfaces;\n\t__u8 bConfigurationValue;\n\t__u8 iConfiguration;\n\t__u8 bmAttributes;\n\t__u8 bMaxPower;\n} __attribute__((packed));\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_debug_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDebugInEndpoint;\n\t__u8 bDebugOutEndpoint;\n};\n\nstruct usb_descriptor_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n};\n\nstruct usb_dev_cap_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_dev_state {\n\tstruct list_head list;\n\tstruct usb_device *dev;\n\tstruct file *file;\n\tspinlock_t lock;\n\tstruct list_head async_pending;\n\tstruct list_head async_completed;\n\tstruct list_head memory_list;\n\twait_queue_head_t wait;\n\twait_queue_head_t wait_for_resume;\n\tunsigned int discsignr;\n\tstruct pid *disc_pid;\n\tconst struct cred *cred;\n\tsigval_t disccontext;\n\tlong unsigned int ifclaimed;\n\tu32 disabled_bulk_eps;\n\tlong unsigned int interface_allowed_mask;\n\tint not_yet_resumed;\n\tbool suspend_allowed;\n\tbool privileges_dropped;\n};\n\nstruct usb_endpoint_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bEndpointAddress;\n\t__u8 bmAttributes;\n\t__le16 wMaxPacketSize;\n\t__u8 bInterval;\n\t__u8 bRefresh;\n\t__u8 bSynchAddress;\n} __attribute__((packed));\n\nstruct usb_ss_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bMaxBurst;\n\t__u8 bmAttributes;\n\t__le16 wBytesPerInterval;\n};\n\nstruct usb_ssp_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wReseved;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_eusb2_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wMaxPacketSize;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_host_endpoint {\n\tstruct usb_endpoint_descriptor desc;\n\tstruct usb_ss_ep_comp_descriptor ss_ep_comp;\n\tstruct usb_ssp_isoc_ep_comp_descriptor ssp_isoc_ep_comp;\n\tstruct usb_eusb2_isoc_ep_comp_descriptor eusb2_isoc_ep_comp;\n\tlong: 0;\n\tstruct list_head urb_list;\n\tvoid *hcpriv;\n\tstruct ep_device *ep_dev;\n\tunsigned char *extra;\n\tint extralen;\n\tint enabled;\n\tint streams;\n\tlong: 0;\n} __attribute__((packed));\n\nstruct usb_device_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__le16 idVendor;\n\t__le16 idProduct;\n\t__le16 bcdDevice;\n\t__u8 iManufacturer;\n\t__u8 iProduct;\n\t__u8 iSerialNumber;\n\t__u8 bNumConfigurations;\n};\n\nstruct usb_host_bos;\n\nstruct usb_host_config;\n\nstruct usb_device {\n\tint devnum;\n\tchar devpath[16];\n\tu32 route;\n\tenum usb_device_state state;\n\tenum usb_device_speed speed;\n\tunsigned int rx_lanes;\n\tunsigned int tx_lanes;\n\tenum usb_ssp_rate ssp_rate;\n\tstruct usb_tt *tt;\n\tint ttport;\n\tunsigned int toggle[2];\n\tstruct usb_device *parent;\n\tstruct usb_bus *bus;\n\tstruct usb_host_endpoint ep0;\n\tstruct device dev;\n\tstruct usb_device_descriptor descriptor;\n\tstruct usb_host_bos *bos;\n\tstruct usb_host_config *config;\n\tstruct usb_host_config *actconfig;\n\tstruct usb_host_endpoint *ep_in[16];\n\tstruct usb_host_endpoint *ep_out[16];\n\tchar **rawdescriptors;\n\tshort unsigned int bus_mA;\n\tu8 portnum;\n\tu8 level;\n\tu8 devaddr;\n\tunsigned int can_submit: 1;\n\tunsigned int persist_enabled: 1;\n\tunsigned int reset_in_progress: 1;\n\tunsigned int have_langid: 1;\n\tunsigned int authorized: 1;\n\tunsigned int authenticated: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int lpm_devinit_allow: 1;\n\tunsigned int usb2_hw_lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_besl_capable: 1;\n\tunsigned int usb2_hw_lpm_enabled: 1;\n\tunsigned int usb2_hw_lpm_allowed: 1;\n\tunsigned int usb3_lpm_u1_enabled: 1;\n\tunsigned int usb3_lpm_u2_enabled: 1;\n\tint string_langid;\n\tchar *product;\n\tchar *manufacturer;\n\tchar *serial;\n\tstruct list_head filelist;\n\tint maxchild;\n\tu32 quirks;\n\tatomic_t urbnum;\n\tlong unsigned int active_duration;\n\tlong unsigned int connect_time;\n\tunsigned int do_remote_wakeup: 1;\n\tunsigned int reset_resume: 1;\n\tunsigned int port_is_suspended: 1;\n\tunsigned int offload_at_suspend: 1;\n\tint offload_usage;\n\tenum usb_link_tunnel_mode tunnel_mode;\n\tstruct device_link *usb4_link;\n\tint slot_id;\n\tstruct usb2_lpm_parameters l1_params;\n\tstruct usb3_lpm_parameters u1_params;\n\tstruct usb3_lpm_parameters u2_params;\n\tunsigned int lpm_disable_count;\n\tu16 hub_delay;\n\tunsigned int use_generic_driver: 1;\n};\n\nstruct usb_device_id;\n\nstruct usb_device_driver {\n\tconst char *name;\n\tbool (*match)(struct usb_device *);\n\tint (*probe)(struct usb_device *);\n\tvoid (*disconnect)(struct usb_device *);\n\tint (*suspend)(struct usb_device *, pm_message_t);\n\tint (*resume)(struct usb_device *, pm_message_t);\n\tint (*choose_configuration)(struct usb_device *);\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tconst struct usb_device_id *id_table;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int generic_subclass: 1;\n};\n\nstruct usb_device_id {\n\t__u16 match_flags;\n\t__u16 idVendor;\n\t__u16 idProduct;\n\t__u16 bcdDevice_lo;\n\t__u16 bcdDevice_hi;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 bInterfaceNumber;\n\tkernel_ulong_t driver_info;\n};\n\nstruct usb_dynids {\n\tstruct list_head list;\n};\n\nstruct usb_driver {\n\tconst char *name;\n\tint (*probe)(struct usb_interface *, const struct usb_device_id *);\n\tvoid (*disconnect)(struct usb_interface *);\n\tint (*unlocked_ioctl)(struct usb_interface *, unsigned int, void *);\n\tint (*suspend)(struct usb_interface *, pm_message_t);\n\tint (*resume)(struct usb_interface *);\n\tint (*reset_resume)(struct usb_interface *);\n\tint (*pre_reset)(struct usb_interface *);\n\tint (*post_reset)(struct usb_interface *);\n\tvoid (*shutdown)(struct usb_interface *);\n\tconst struct usb_device_id *id_table;\n\tconst struct attribute_group **dev_groups;\n\tstruct usb_dynids dynids;\n\tstruct device_driver driver;\n\tunsigned int no_dynamic_id: 1;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int disable_hub_initiated_lpm: 1;\n\tunsigned int soft_unbind: 1;\n};\n\nstruct usb_dynid {\n\tstruct list_head node;\n\tstruct usb_device_id id;\n};\n\nstruct usb_ext_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__le32 bmAttributes;\n} __attribute__((packed));\n\nstruct usb_phy;\n\nstruct usb_phy_roothub;\n\nstruct usb_hcd {\n\tstruct usb_bus self;\n\tstruct kref kref;\n\tconst char *product_desc;\n\tint speed;\n\tchar irq_descr[24];\n\tstruct timer_list rh_timer;\n\tstruct urb *status_urb;\n\tstruct work_struct wakeup_work;\n\tstruct work_struct died_work;\n\tconst struct hc_driver *driver;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_phy_roothub *phy_roothub;\n\tlong unsigned int flags;\n\tenum usb_dev_authorize_policy dev_policy;\n\tunsigned int rh_registered: 1;\n\tunsigned int rh_pollable: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int msi_enabled: 1;\n\tunsigned int skip_phy_initialization: 1;\n\tunsigned int uses_new_polling: 1;\n\tunsigned int has_tt: 1;\n\tunsigned int amd_resume_bug: 1;\n\tunsigned int can_do_streams: 1;\n\tunsigned int tpl_support: 1;\n\tunsigned int cant_recv_wakeups: 1;\n\tunsigned int irq;\n\tvoid *regs;\n\tresource_size_t rsrc_start;\n\tresource_size_t rsrc_len;\n\tunsigned int power_budget;\n\tstruct giveback_urb_bh high_prio_bh;\n\tstruct giveback_urb_bh low_prio_bh;\n\tstruct mutex *address0_mutex;\n\tstruct mutex *bandwidth_mutex;\n\tstruct usb_hcd *shared_hcd;\n\tstruct usb_hcd *primary_hcd;\n\tstruct dma_pool *pool[4];\n\tint state;\n\tstruct gen_pool *localmem_pool;\n\tlong unsigned int hcd_priv[0];\n};\n\nstruct usb_ss_cap_descriptor;\n\nstruct usb_ssp_cap_descriptor;\n\nstruct usb_ss_container_id_descriptor;\n\nstruct usb_ptm_cap_descriptor;\n\nstruct usb_host_bos {\n\tstruct usb_bos_descriptor *desc;\n\tstruct usb_ext_cap_descriptor *ext_cap;\n\tstruct usb_ss_cap_descriptor *ss_cap;\n\tstruct usb_ssp_cap_descriptor *ssp_cap;\n\tstruct usb_ss_container_id_descriptor *ss_id;\n\tstruct usb_ptm_cap_descriptor *ptm_cap;\n};\n\nstruct usb_interface_assoc_descriptor;\n\nstruct usb_interface_cache;\n\nstruct usb_host_config {\n\tstruct usb_config_descriptor desc;\n\tchar *string;\n\tstruct usb_interface_assoc_descriptor *intf_assoc[16];\n\tstruct usb_interface *interface[32];\n\tstruct usb_interface_cache *intf_cache[32];\n\tunsigned char *extra;\n\tint extralen;\n};\n\nstruct usb_interface_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bInterfaceNumber;\n\t__u8 bAlternateSetting;\n\t__u8 bNumEndpoints;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 iInterface;\n};\n\nstruct usb_host_interface {\n\tstruct usb_interface_descriptor desc;\n\tint extralen;\n\tunsigned char *extra;\n\tstruct usb_host_endpoint *endpoint;\n\tchar *string;\n};\n\nstruct usb_hub_status {\n\t__le16 wHubStatus;\n\t__le16 wHubChange;\n};\n\nstruct usb_port_status {\n\t__le16 wPortStatus;\n\t__le16 wPortChange;\n\t__le32 dwExtPortStatus;\n};\n\nstruct usb_tt {\n\tstruct usb_device *hub;\n\tint multi;\n\tunsigned int think_time;\n\tvoid *hcpriv;\n\tspinlock_t lock;\n\tstruct list_head clear_list;\n\tstruct work_struct clear_work;\n};\n\nstruct usb_hub_descriptor;\n\nstruct usb_port;\n\nstruct usb_hub {\n\tstruct device *intfdev;\n\tstruct usb_device *hdev;\n\tstruct kref kref;\n\tstruct urb *urb;\n\tu8 (*buffer)[8];\n\tunion {\n\t\tstruct usb_hub_status hub;\n\t\tstruct usb_port_status port;\n\t} *status;\n\tstruct mutex status_mutex;\n\tint error;\n\tint nerrors;\n\tlong unsigned int event_bits[1];\n\tlong unsigned int change_bits[1];\n\tlong unsigned int removed_bits[1];\n\tlong unsigned int wakeup_bits[1];\n\tlong unsigned int power_bits[1];\n\tlong unsigned int child_usage_bits[1];\n\tlong unsigned int warm_reset_bits[1];\n\tstruct usb_hub_descriptor *descriptor;\n\tstruct usb_tt tt;\n\tunsigned int mA_per_port;\n\tunsigned int wakeup_enabled_descendants;\n\tunsigned int limited_power: 1;\n\tunsigned int quiescing: 1;\n\tunsigned int disconnected: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int quirk_disable_autosuspend: 1;\n\tunsigned int quirk_check_port_auto_suspend: 1;\n\tunsigned int has_indicators: 1;\n\tu8 indicator[31];\n\tstruct delayed_work leds;\n\tstruct delayed_work init_work;\n\tstruct delayed_work post_resume_work;\n\tstruct work_struct events;\n\tspinlock_t irq_urb_lock;\n\tstruct timer_list irq_urb_retry;\n\tstruct usb_port **ports;\n\tstruct list_head onboard_devs;\n};\n\nstruct usb_hub_descriptor {\n\t__u8 bDescLength;\n\t__u8 bDescriptorType;\n\t__u8 bNbrPorts;\n\t__le16 wHubCharacteristics;\n\t__u8 bPwrOn2PwrGood;\n\t__u8 bHubContrCurrent;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 DeviceRemovable[4];\n\t\t\t__u8 PortPwrCtrlMask[4];\n\t\t} hs;\n\t\tstruct {\n\t\t\t__u8 bHubHdrDecLat;\n\t\t\t__le16 wHubDelay;\n\t\t\t__le16 DeviceRemovable;\n\t\t} __attribute__((packed)) ss;\n\t} u;\n} __attribute__((packed));\n\nstruct usb_interface {\n\tstruct usb_host_interface *altsetting;\n\tstruct usb_host_interface *cur_altsetting;\n\tunsigned int num_altsetting;\n\tstruct usb_interface_assoc_descriptor *intf_assoc;\n\tint minor;\n\tenum usb_interface_condition condition;\n\tunsigned int sysfs_files_created: 1;\n\tunsigned int ep_devs_created: 1;\n\tunsigned int unregistering: 1;\n\tunsigned int needs_remote_wakeup: 1;\n\tunsigned int needs_altsetting0: 1;\n\tunsigned int needs_binding: 1;\n\tunsigned int resetting_device: 1;\n\tunsigned int authorized: 1;\n\tenum usb_wireless_status wireless_status;\n\tstruct work_struct wireless_status_work;\n\tstruct device dev;\n\tstruct device *usb_dev;\n\tstruct work_struct reset_ws;\n};\n\nstruct usb_interface_assoc_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bFirstInterface;\n\t__u8 bInterfaceCount;\n\t__u8 bFunctionClass;\n\t__u8 bFunctionSubClass;\n\t__u8 bFunctionProtocol;\n\t__u8 iFunction;\n};\n\nstruct usb_interface_cache {\n\tunsigned int num_altsetting;\n\tstruct kref ref;\n\tstruct usb_host_interface altsetting[0];\n};\n\nstruct usb_memory {\n\tstruct list_head memlist;\n\tint vma_use_count;\n\tint urb_use_count;\n\tu32 size;\n\tvoid *mem;\n\tdma_addr_t dma_handle;\n\tlong unsigned int vm_start;\n\tstruct usb_dev_state *ps;\n};\n\nstruct usb_mon_operations {\n\tvoid (*urb_submit)(struct usb_bus *, struct urb *);\n\tvoid (*urb_submit_error)(struct usb_bus *, struct urb *, int);\n\tvoid (*urb_complete)(struct usb_bus *, struct urb *, int);\n};\n\nstruct usb_gadget;\n\nstruct usb_otg {\n\tu8 default_a;\n\tstruct phy___3 *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_bus *host;\n\tstruct usb_gadget *gadget;\n\tenum usb_otg_state state;\n\tint (*set_host)(struct usb_otg *, struct usb_bus *);\n\tint (*set_peripheral)(struct usb_otg *, struct usb_gadget *);\n\tint (*set_vbus)(struct usb_otg *, bool);\n\tint (*start_srp)(struct usb_otg *);\n\tint (*start_hnp)(struct usb_otg *);\n};\n\nstruct extcon_dev;\n\nstruct usb_phy_io_ops;\n\nstruct usb_phy {\n\tstruct device *dev;\n\tconst char *label;\n\tunsigned int flags;\n\tenum usb_phy_type type;\n\tenum usb_phy_events last_event;\n\tstruct usb_otg *otg;\n\tstruct device *io_dev;\n\tstruct usb_phy_io_ops *io_ops;\n\tvoid *io_priv;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *id_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct notifier_block type_nb;\n\tenum usb_charger_type chg_type;\n\tenum usb_charger_state chg_state;\n\tstruct usb_charger_current chg_cur;\n\tstruct work_struct chg_work;\n\tstruct atomic_notifier_head notifier;\n\tu16 port_status;\n\tu16 port_change;\n\tstruct list_head head;\n\tint (*init)(struct usb_phy *);\n\tvoid (*shutdown)(struct usb_phy *);\n\tint (*set_vbus)(struct usb_phy *, int);\n\tint (*set_power)(struct usb_phy *, unsigned int);\n\tint (*set_suspend)(struct usb_phy *, int);\n\tint (*set_wakeup)(struct usb_phy *, bool);\n\tint (*notify_connect)(struct usb_phy *, enum usb_device_speed);\n\tint (*notify_disconnect)(struct usb_phy *, enum usb_device_speed);\n\tenum usb_charger_type (*charger_detect)(struct usb_phy *);\n};\n\nstruct usb_phy_io_ops {\n\tint (*read)(struct usb_phy *, u32);\n\tint (*write)(struct usb_phy *, u32, u32);\n};\n\nstruct usb_phy_roothub {\n\tstruct phy___3 *phy;\n\tstruct list_head list;\n};\n\nstruct usb_port {\n\tstruct usb_device *child;\n\tstruct device dev;\n\tstruct usb_dev_state *port_owner;\n\tstruct usb_port *peer;\n\tstruct typec_connector *connector;\n\tstruct dev_pm_qos_request *req;\n\tenum usb_port_connect_type connect_type;\n\tenum usb_device_state state;\n\tstruct kernfs_node *state_kn;\n\tusb_port_location_t location;\n\tstruct mutex status_lock;\n\tu32 over_current_count;\n\tu8 portnum;\n\tu32 quirks;\n\tunsigned int early_stop: 1;\n\tunsigned int ignore_event: 1;\n\tunsigned int is_superspeed: 1;\n\tunsigned int usb3_lpm_u1_permit: 1;\n\tunsigned int usb3_lpm_u2_permit: 1;\n};\n\nstruct usb_ptm_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_qualifier_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__u8 bNumConfigurations;\n\t__u8 bRESERVED;\n};\n\nstruct usb_set_sel_req {\n\t__u8 u1_sel;\n\t__u8 u1_pel;\n\t__le16 u2_sel;\n\t__le16 u2_pel;\n};\n\nstruct usb_ss_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bmAttributes;\n\t__le16 wSpeedSupported;\n\t__u8 bFunctionalitySupport;\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n};\n\nstruct usb_ss_container_id_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__u8 ContainerID[16];\n};\n\nstruct usb_ssp_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__le32 bmAttributes;\n\t__le16 wFunctionalitySupport;\n\t__le16 wReserved;\n\tunion {\n\t\t__le32 legacy_padding;\n\t\tstruct {\n\t\t\tstruct {} __empty_bmSublinkSpeedAttr;\n\t\t\t__le32 bmSublinkSpeedAttr[0];\n\t\t};\n\t};\n};\n\nstruct usb_tt_clear {\n\tstruct list_head clear_list;\n\tunsigned int tt;\n\tu16 devinfo;\n\tstruct usb_hcd *hcd;\n\tstruct usb_host_endpoint *ep;\n};\n\nstruct usbdevfs_bulktransfer {\n\tunsigned int ep;\n\tunsigned int len;\n\tunsigned int timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_bulktransfer32 {\n\tcompat_uint_t ep;\n\tcompat_uint_t len;\n\tcompat_uint_t timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_connectinfo {\n\tunsigned int devnum;\n\tunsigned char slow;\n};\n\nstruct usbdevfs_conninfo_ex {\n\t__u32 size;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 speed;\n\t__u8 num_ports;\n\t__u8 ports[7];\n};\n\nstruct usbdevfs_ctrltransfer {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\t__u32 timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_ctrltransfer32 {\n\tu8 bRequestType;\n\tu8 bRequest;\n\tu16 wValue;\n\tu16 wIndex;\n\tu16 wLength;\n\tu32 timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_disconnect_claim {\n\tunsigned int interface;\n\tunsigned int flags;\n\tchar driver[256];\n};\n\nstruct usbdevfs_disconnectsignal {\n\tunsigned int signr;\n\tvoid *context;\n};\n\nstruct usbdevfs_disconnectsignal32 {\n\tcompat_int_t signr;\n\tcompat_caddr_t context;\n};\n\nstruct usbdevfs_getdriver {\n\tunsigned int interface;\n\tchar driver[256];\n};\n\nstruct usbdevfs_hub_portinfo {\n\tchar nports;\n\tchar port[127];\n};\n\nstruct usbdevfs_ioctl {\n\tint ifno;\n\tint ioctl_code;\n\tvoid *data;\n};\n\nstruct usbdevfs_ioctl32 {\n\ts32 ifno;\n\ts32 ioctl_code;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_iso_packet_desc {\n\tunsigned int length;\n\tunsigned int actual_length;\n\tunsigned int status;\n};\n\nstruct usbdevfs_setinterface {\n\tunsigned int interface;\n\tunsigned int altsetting;\n};\n\nstruct usbdevfs_streams {\n\tunsigned int num_streams;\n\tunsigned int num_eps;\n\tunsigned char eps[0];\n};\n\nstruct usbdevfs_urb {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tint status;\n\tunsigned int flags;\n\tvoid *buffer;\n\tint buffer_length;\n\tint actual_length;\n\tint start_frame;\n\tunion {\n\t\tint number_of_packets;\n\t\tunsigned int stream_id;\n\t};\n\tint error_count;\n\tunsigned int signr;\n\tvoid *usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbdevfs_urb32 {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tcompat_int_t status;\n\tcompat_uint_t flags;\n\tcompat_caddr_t buffer;\n\tcompat_int_t buffer_length;\n\tcompat_int_t actual_length;\n\tcompat_int_t start_frame;\n\tcompat_int_t number_of_packets;\n\tcompat_int_t error_count;\n\tcompat_uint_t signr;\n\tcompat_caddr_t usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbhid_device {\n\tstruct hid_device *hid;\n\tstruct usb_interface *intf;\n\tint ifnum;\n\tunsigned int bufsize;\n\tstruct urb *urbin;\n\tchar *inbuf;\n\tdma_addr_t inbuf_dma;\n\tstruct urb *urbctrl;\n\tstruct usb_ctrlrequest *cr;\n\tstruct hid_control_fifo ctrl[256];\n\tunsigned char ctrlhead;\n\tunsigned char ctrltail;\n\tchar *ctrlbuf;\n\tdma_addr_t ctrlbuf_dma;\n\tlong unsigned int last_ctrl;\n\tstruct urb *urbout;\n\tstruct hid_output_fifo out[256];\n\tunsigned char outhead;\n\tunsigned char outtail;\n\tchar *outbuf;\n\tdma_addr_t outbuf_dma;\n\tlong unsigned int last_out;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tlong unsigned int iofl;\n\tstruct timer_list io_retry;\n\tlong unsigned int stop_retry;\n\tunsigned int retry_delay;\n\tstruct work_struct reset_work;\n\twait_queue_head_t wait;\n};\n\nstruct usblp {\n\tstruct usb_device *dev;\n\tstruct mutex wmut;\n\tstruct mutex mut;\n\tspinlock_t lock;\n\tchar *readbuf;\n\tchar *statusbuf;\n\tstruct usb_anchor urbs;\n\twait_queue_head_t rwait;\n\twait_queue_head_t wwait;\n\tint readcount;\n\tint ifnum;\n\tstruct usb_interface *intf;\n\tstruct {\n\t\tint alt_setting;\n\t\tstruct usb_endpoint_descriptor *epwrite;\n\t\tstruct usb_endpoint_descriptor *epread;\n\t} protocol[4];\n\tint current_protocol;\n\tint minor;\n\tint wcomplete;\n\tint rcomplete;\n\tint wstatus;\n\tint rstatus;\n\tunsigned int quirks;\n\tunsigned int flags;\n\tunsigned char used;\n\tunsigned char present;\n\tunsigned char bidir;\n\tunsigned char no_paper;\n\tunsigned char *device_id_string;\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct used_entry {\n\tu32 id;\n\tu32 len;\n};\n\nstruct user_arg_ptr {\n\tbool is_compat;\n\tunion {\n\t\tconst char * const *native;\n\t\tconst compat_uptr_t *compat;\n\t} ptr;\n};\n\nstruct user_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap roles;\n\tstruct mls_range range;\n\tstruct mls_level dfltlevel;\n};\n\nstruct user_desc {\n\tunsigned int entry_number;\n\tunsigned int base_addr;\n\tunsigned int limit;\n\tunsigned int seg_32bit: 1;\n\tunsigned int contents: 2;\n\tunsigned int read_exec_only: 1;\n\tunsigned int limit_in_pages: 1;\n\tunsigned int seg_not_present: 1;\n\tunsigned int useable: 1;\n\tunsigned int lm: 1;\n};\n\nstruct user_element {\n\tstruct snd_ctl_elem_info info;\n\tstruct snd_card *card;\n\tchar *elem_data;\n\tlong unsigned int elem_data_size;\n\tvoid *tlv_data;\n\tlong unsigned int tlv_data_size;\n\tvoid *priv_data;\n};\n\nstruct user_i387_ia32_struct {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[10];\n\tlong int rlimit_max[4];\n\tstruct binfmt_misc *binfmt_misc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n};\n\nstruct user_threshold {\n\tstruct list_head list_node;\n\tint temperature;\n\tint direction;\n};\n\nstruct userspace_policy {\n\tunsigned int is_managed;\n\tunsigned int setspeed;\n\tstruct mutex mutex;\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tlong unsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct ustring_buffer {\n\tchar buffer[1024];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct utimbuf {\n\t__kernel_old_time_t actime;\n\t__kernel_old_time_t modtime;\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct v2_disk_dqheader {\n\t__le32 dqh_magic;\n\t__le32 dqh_version;\n};\n\nstruct v2_disk_dqinfo {\n\t__le32 dqi_bgrace;\n\t__le32 dqi_igrace;\n\t__le32 dqi_flags;\n\t__le32 dqi_blocks;\n\t__le32 dqi_free_blk;\n\t__le32 dqi_free_entry;\n};\n\nstruct v2r0_disk_dqblk {\n\t__le32 dqb_id;\n\t__le32 dqb_ihardlimit;\n\t__le32 dqb_isoftlimit;\n\t__le32 dqb_curinodes;\n\t__le32 dqb_bhardlimit;\n\t__le32 dqb_bsoftlimit;\n\t__le64 dqb_curspace;\n\t__le64 dqb_btime;\n\t__le64 dqb_itime;\n};\n\nstruct v2r1_disk_dqblk {\n\t__le32 dqb_id;\n\t__le32 dqb_pad;\n\t__le64 dqb_ihardlimit;\n\t__le64 dqb_isoftlimit;\n\t__le64 dqb_curinodes;\n\t__le64 dqb_bhardlimit;\n\t__le64 dqb_bsoftlimit;\n\t__le64 dqb_curspace;\n\t__le64 dqb_btime;\n\t__le64 dqb_itime;\n};\n\nstruct v9fs_context {\n\tstruct p9_client_opts client_opts;\n\tstruct p9_fd_opts fd_opts;\n\tstruct p9_rdma_opts rdma_opts;\n\tstruct p9_session_opts session_opts;\n};\n\nstruct v9fs_inode {\n\tstruct netfs_inode netfs;\n\tstruct p9_qid qid;\n\tunsigned int cache_validity;\n\tstruct mutex v_mutex;\n};\n\nstruct v9fs_session_info {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tunsigned int maxdata;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tstruct p9_client *clnt;\n\tstruct list_head slist;\n\tstruct rw_semaphore rename_sem;\n\tlong int session_lock_timeout;\n};\n\nstruct va_alignment {\n\tint flags;\n\tlong unsigned int mask;\n\tlong unsigned int bits;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct value_name_pair {\n\tint value;\n\tconst char *name;\n};\n\nstruct var_mtrr_range_state {\n\tlong unsigned int base_pfn;\n\tlong unsigned int size_pfn;\n\tmtrr_type type;\n};\n\nstruct vbt_header {\n\tu8 signature[20];\n\tu16 version;\n\tu16 header_size;\n\tu16 vbt_size;\n\tu8 vbt_checksum;\n\tu8 reserved0;\n\tu32 bdb_offset;\n\tu32 aim_offset[4];\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[4];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcpu_fpu_config {\n\tunsigned int size;\n\tu64 features;\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 max_cycles;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_exception_table_entry {\n\tint insn;\n\tint fixup;\n};\n\nstruct vdso_image {\n\tvoid *data;\n\tlong unsigned int size;\n\tlong unsigned int alt;\n\tlong unsigned int alt_len;\n\tlong unsigned int extable_base;\n\tlong unsigned int extable_len;\n\tconst void *extable;\n\tlong int sym_VDSO32_NOTE_MASK;\n\tlong int sym___kernel_sigreturn;\n\tlong int sym___kernel_rt_sigreturn;\n\tlong int sym___kernel_vsyscall;\n\tlong int sym_int80_landing_pad;\n\tlong int sym_vdso32_sigreturn_landing_pad;\n\tlong int sym_vdso32_rt_sigreturn_landing_pad;\n};\n\nstruct vdso_rng_data {\n\tu64 generation;\n\tu8 is_ready;\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ve_node {\n\tstruct rb_node rb;\n\tint prio;\n};\n\nstruct vector_cleanup {\n\tstruct hlist_head head;\n\tstruct timer_list timer;\n};\n\nstruct vers_iter {\n\tsize_t param_size;\n\tstruct dm_target_versions *vers;\n\tstruct dm_target_versions *old_vers;\n\tchar *end;\n\tuint32_t flags;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tbool is_firmware_default;\n\tunsigned int (*set_decode)(struct pci_dev *, bool);\n};\n\nstruct vga_switcheroo_client_ops {\n\tvoid (*set_gpu_state)(struct pci_dev *, enum vga_switcheroo_state);\n\tvoid (*reprobe)(struct pci_dev *);\n\tbool (*can_switch)(struct pci_dev *);\n\tvoid (*gpu_bound)(struct pci_dev *, enum vga_switcheroo_client_id);\n};\n\nstruct vgastate {\n\tvoid *vgabase;\n\tlong unsigned int membase;\n\t__u32 memsize;\n\t__u32 flags;\n\t__u32 depth;\n\t__u32 num_attr;\n\t__u32 num_crtc;\n\t__u32 num_gfx;\n\t__u32 num_seq;\n\tvoid *vidstate;\n};\n\nstruct video_levels {\n\tu16 blank;\n\tu16 black;\n\tu8 burst;\n};\n\nstruct vif_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct net_device *dev;\n\tshort unsigned int vif_index;\n\tshort unsigned int vif_flags;\n\tu32 tb_id;\n};\n\nstruct vif_params {\n\tu32 flags;\n\tint use_4addr;\n\tu8 macaddr[6];\n\tconst u8 *vht_mumimo_groups;\n\tconst u8 *vht_mumimo_follow_addr;\n};\n\nstruct vifctl {\n\tvifi_t vifc_vifi;\n\tunsigned char vifc_flags;\n\tunsigned char vifc_threshold;\n\tunsigned int vifc_rate_limit;\n\tunion {\n\t\tstruct in_addr vifc_lcl_addr;\n\t\tint vifc_lcl_ifindex;\n\t};\n\tstruct in_addr vifc_rmt_addr;\n};\n\nstruct virtio_blk_outhdr {\n\t__virtio32 type;\n\t__virtio32 ioprio;\n\t__virtio64 sector;\n};\n\nstruct virtblk_req {\n\tstruct virtio_blk_outhdr out_hdr;\n\tunion {\n\t\tu8 status;\n\t\tstruct {\n\t\t\t__virtio64 sector;\n\t\t\tu8 status;\n\t\t} zone_append;\n\t} in_hdr;\n\tsize_t in_hdr_len;\n\tstruct sg_table sg_table;\n\tstruct scatterlist sg[0];\n};\n\nstruct virtio_9p_config {\n\t__virtio16 tag_len;\n\t__u8 tag[0];\n};\n\nstruct virtio_admin_cmd {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__le64 group_member_id;\n\tstruct scatterlist *data_sg;\n\tstruct scatterlist *result_sg;\n\tstruct completion completion;\n\tu32 result_sg_size;\n\tint ret;\n};\n\nstruct virtio_admin_cmd_cap_get_data {\n\t__le16 id;\n\t__u8 reserved[6];\n};\n\nstruct virtio_admin_cmd_cap_set_data {\n\t__le16 id;\n\t__u8 reserved[6];\n\t__u8 cap_specific_data[0];\n};\n\nstruct virtio_admin_cmd_dev_mode_set_data {\n\t__u8 flags;\n};\n\nstruct virtio_admin_cmd_resource_obj_cmd_hdr {\n\t__le16 type;\n\t__u8 reserved[2];\n\t__le32 id;\n};\n\nstruct virtio_dev_part_hdr {\n\t__le16 part_type;\n\t__u8 flags;\n\t__u8 reserved;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 offset;\n\t\t\t__le32 reserved;\n\t\t} pci_common_cfg;\n\t\tstruct {\n\t\t\t__le16 index;\n\t\t\t__u8 reserved[6];\n\t\t} vq_index;\n\t} selector;\n\t__le32 length;\n};\n\nstruct virtio_admin_cmd_dev_parts_get_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n\tstruct virtio_dev_part_hdr hdr_list[0];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_result {\n\tunion {\n\t\tstruct {\n\t\t\t__le32 size;\n\t\t\t__le32 reserved;\n\t\t} parts_size;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t} hdr_list_count;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t\tstruct virtio_dev_part_hdr hdrs[0];\n\t\t} hdr_list;\n\t};\n};\n\nstruct virtio_admin_cmd_hdr {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__u8 reserved1[12];\n\t__le64 group_member_id;\n};\n\nstruct virtio_admin_cmd_legacy_rd_data {\n\t__u8 offset;\n};\n\nstruct virtio_admin_cmd_legacy_wr_data {\n\t__u8 offset;\n\t__u8 reserved[7];\n\t__u8 registers[0];\n};\n\nstruct virtio_admin_cmd_notify_info_data {\n\t__u8 flags;\n\t__u8 bar;\n\t__u8 padding[6];\n\t__le64 offset;\n};\n\nstruct virtio_admin_cmd_notify_info_result {\n\tstruct virtio_admin_cmd_notify_info_data entries[4];\n};\n\nstruct virtio_admin_cmd_query_cap_id_result {\n\t__le64 supported_caps[1];\n};\n\nstruct virtio_admin_cmd_resource_obj_create_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__le64 flags;\n\t__u8 resource_obj_specific_data[0];\n};\n\nstruct virtio_admin_cmd_status {\n\t__le16 status;\n\t__le16 status_qualifier;\n\t__u8 reserved2[4];\n};\n\nstruct virtio_blk_vq;\n\nstruct virtio_blk {\n\tstruct mutex vdev_mutex;\n\tstruct virtio_device *vdev;\n\tstruct gendisk *disk;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct work_struct config_work;\n\tint index;\n\tint num_vqs;\n\tint io_queues[3];\n\tstruct virtio_blk_vq *vqs;\n\tunsigned int zone_sectors;\n};\n\nstruct virtio_blk_geometry {\n\t__virtio16 cylinders;\n\t__u8 heads;\n\t__u8 sectors;\n};\n\nstruct virtio_blk_zoned_characteristics {\n\t__virtio32 zone_sectors;\n\t__virtio32 max_open_zones;\n\t__virtio32 max_active_zones;\n\t__virtio32 max_append_sectors;\n\t__virtio32 write_granularity;\n\t__u8 model;\n\t__u8 unused2[3];\n};\n\nstruct virtio_blk_config {\n\t__virtio64 capacity;\n\t__virtio32 size_max;\n\t__virtio32 seg_max;\n\tstruct virtio_blk_geometry geometry;\n\t__virtio32 blk_size;\n\t__u8 physical_block_exp;\n\t__u8 alignment_offset;\n\t__virtio16 min_io_size;\n\t__virtio32 opt_io_size;\n\t__u8 wce;\n\t__u8 unused;\n\t__virtio16 num_queues;\n\t__virtio32 max_discard_sectors;\n\t__virtio32 max_discard_seg;\n\t__virtio32 discard_sector_alignment;\n\t__virtio32 max_write_zeroes_sectors;\n\t__virtio32 max_write_zeroes_seg;\n\t__u8 write_zeroes_may_unmap;\n\t__u8 unused1[3];\n\t__virtio32 max_secure_erase_sectors;\n\t__virtio32 max_secure_erase_seg;\n\t__virtio32 secure_erase_sector_alignment;\n\tstruct virtio_blk_zoned_characteristics zoned;\n};\n\nstruct virtio_blk_discard_write_zeroes {\n\t__le64 sector;\n\t__le32 num_sectors;\n\t__le32 flags;\n};\n\nstruct virtio_blk_vq {\n\tstruct virtqueue *vq;\n\tspinlock_t lock;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct virtio_chan {\n\tbool inuse;\n\tspinlock_t lock;\n\tstruct p9_client *client;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *vq;\n\tint ring_bufs_avail;\n\twait_queue_head_t *vc_wq;\n\tlong unsigned int p9_max_pages;\n\tstruct scatterlist sg[128];\n\tchar *tag;\n\tstruct list_head chan_list;\n};\n\nstruct virtqueue_info;\n\nstruct virtio_shm_region;\n\nstruct virtio_config_ops {\n\tvoid (*get)(struct virtio_device *, unsigned int, void *, unsigned int);\n\tvoid (*set)(struct virtio_device *, unsigned int, const void *, unsigned int);\n\tu32 (*generation)(struct virtio_device *);\n\tu8 (*get_status)(struct virtio_device *);\n\tvoid (*set_status)(struct virtio_device *, u8);\n\tvoid (*reset)(struct virtio_device *);\n\tint (*find_vqs)(struct virtio_device *, unsigned int, struct virtqueue **, struct virtqueue_info *, struct irq_affinity *);\n\tvoid (*del_vqs)(struct virtio_device *);\n\tvoid (*synchronize_cbs)(struct virtio_device *);\n\tu64 (*get_features)(struct virtio_device *);\n\tvoid (*get_extended_features)(struct virtio_device *, u64 *);\n\tint (*finalize_features)(struct virtio_device *);\n\tconst char * (*bus_name)(struct virtio_device *);\n\tint (*set_vq_affinity)(struct virtqueue *, const struct cpumask *);\n\tconst struct cpumask * (*get_vq_affinity)(struct virtio_device *, int);\n\tbool (*get_shm_region)(struct virtio_device *, struct virtio_shm_region *, u8);\n\tint (*disable_vq_and_reset)(struct virtqueue *);\n\tint (*enable_vq_after_reset)(struct virtqueue *);\n};\n\nstruct virtio_console_config {\n\t__virtio16 cols;\n\t__virtio16 rows;\n\t__virtio32 max_nr_ports;\n\t__virtio32 emerg_wr;\n};\n\nstruct virtio_dev_parts_cap {\n\t__u8 get_parts_resource_objects_limit;\n\t__u8 set_parts_resource_objects_limit;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct vringh_config_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_map_ops;\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_dma_buf_ops {\n\tstruct dma_buf_ops ops;\n\tint (*device_attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*get_uuid)(struct dma_buf *, uuid_t *);\n};\n\nstruct virtio_driver {\n\tstruct device_driver driver;\n\tconst struct virtio_device_id *id_table;\n\tconst unsigned int *feature_table;\n\tunsigned int feature_table_size;\n\tconst unsigned int *feature_table_legacy;\n\tunsigned int feature_table_size_legacy;\n\tint (*validate)(struct virtio_device *);\n\tint (*probe)(struct virtio_device *);\n\tvoid (*scan)(struct virtio_device *);\n\tvoid (*remove)(struct virtio_device *);\n\tvoid (*config_changed)(struct virtio_device *);\n\tint (*freeze)(struct virtio_device *);\n\tint (*restore)(struct virtio_device *);\n\tint (*reset_prepare)(struct virtio_device *);\n\tint (*reset_done)(struct virtio_device *);\n\tvoid (*shutdown)(struct virtio_device *);\n};\n\nstruct virtio_gpu_box {\n\t__le32 x;\n\t__le32 y;\n\t__le32 z;\n\t__le32 w;\n\t__le32 h;\n\t__le32 d;\n};\n\nstruct virtio_gpu_ctrl_hdr {\n\t__le32 type;\n\t__le32 flags;\n\t__le64 fence_id;\n\t__le32 ctx_id;\n\t__u8 ring_idx;\n\t__u8 padding[3];\n};\n\nstruct virtio_gpu_cmd_get_edid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 scanout;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_cmd_submit {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 size;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_config {\n\t__le32 events_read;\n\t__le32 events_clear;\n\t__le32 num_scanouts;\n\t__le32 num_capsets;\n};\n\nstruct virtio_gpu_ctx_create {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 nlen;\n\t__le32 context_init;\n\tchar debug_name[64];\n};\n\nstruct virtio_gpu_ctx_destroy {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n};\n\nstruct virtio_gpu_ctx_resource {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_cursor_pos {\n\t__le32 scanout_id;\n\t__le32 x;\n\t__le32 y;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_rect {\n\t__le32 x;\n\t__le32 y;\n\t__le32 width;\n\t__le32 height;\n};\n\nstruct virtio_gpu_display_one {\n\tstruct virtio_gpu_rect r;\n\t__le32 enabled;\n\t__le32 flags;\n};\n\nstruct virtio_gpu_update_cursor {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_cursor_pos pos;\n\t__le32 resource_id;\n\t__le32 hot_x;\n\t__le32 hot_y;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_output {\n\tint index;\n\tstruct drm_crtc crtc;\n\tstruct drm_connector conn;\n\tstruct drm_encoder enc;\n\tstruct virtio_gpu_display_one info;\n\tstruct virtio_gpu_update_cursor cursor;\n\tconst struct drm_edid *drm_edid;\n\tint cur_x;\n\tint cur_y;\n\tbool needs_modeset;\n};\n\nstruct virtio_gpu_queue {\n\tstruct virtqueue *vq;\n\tspinlock_t qlock;\n\twait_queue_head_t ack_queue;\n\tstruct work_struct dequeue_work;\n\tuint32_t seqno;\n};\n\nstruct virtio_gpu_fence_driver {\n\tatomic64_t last_fence_id;\n\tuint64_t current_fence_id;\n\tuint64_t context;\n\tstruct list_head fences;\n\tspinlock_t lock;\n};\n\nstruct virtio_shm_region {\n\tu64 addr;\n\tu64 len;\n};\n\nstruct virtio_gpu_drv_capset;\n\nstruct virtio_gpu_device {\n\tstruct drm_device *ddev;\n\tstruct virtio_device *vdev;\n\tstruct virtio_gpu_output outputs[16];\n\tuint32_t num_scanouts;\n\tstruct virtio_gpu_queue ctrlq;\n\tstruct virtio_gpu_queue cursorq;\n\tstruct kmem_cache *vbufs;\n\tatomic_t pending_commands;\n\tstruct ida resource_ida;\n\twait_queue_head_t resp_wq;\n\tspinlock_t display_info_lock;\n\tbool display_info_pending;\n\tstruct virtio_gpu_fence_driver fence_drv;\n\tstruct ida ctx_id_ida;\n\tbool has_virgl_3d;\n\tbool has_edid;\n\tbool has_indirect;\n\tbool has_resource_assign_uuid;\n\tbool has_resource_blob;\n\tbool has_host_visible;\n\tbool has_context_init;\n\tstruct virtio_shm_region host_visible_region;\n\tstruct drm_mm host_visible_mm;\n\tstruct work_struct config_changed_work;\n\tstruct work_struct obj_free_work;\n\tspinlock_t obj_free_lock;\n\tstruct list_head obj_free_list;\n\tstruct virtio_gpu_drv_capset *capsets;\n\tuint32_t num_capsets;\n\tuint64_t capset_id_mask;\n\tstruct list_head cap_cache;\n\tspinlock_t resource_export_lock;\n\tspinlock_t host_visible_lock;\n};\n\nstruct virtio_gpu_drv_cap_cache {\n\tstruct list_head head;\n\tvoid *caps_cache;\n\tuint32_t id;\n\tuint32_t version;\n\tuint32_t size;\n\tatomic_t is_valid;\n};\n\nstruct virtio_gpu_drv_capset {\n\tuint32_t id;\n\tuint32_t max_version;\n\tuint32_t max_size;\n};\n\nstruct virtio_gpu_fence_event;\n\nstruct virtio_gpu_fence {\n\tstruct dma_fence f;\n\tuint32_t ring_idx;\n\tuint64_t fence_id;\n\tbool emit_fence_info;\n\tstruct virtio_gpu_fence_event *e;\n\tstruct virtio_gpu_fence_driver *drv;\n\tstruct list_head node;\n};\n\nstruct virtio_gpu_fence_event {\n\tstruct drm_pending_event base;\n\tstruct drm_event event;\n};\n\nstruct virtio_gpu_fpriv {\n\tuint32_t ctx_id;\n\tuint32_t context_init;\n\tbool context_created;\n\tuint32_t num_rings;\n\tuint64_t base_fence_ctx;\n\tuint64_t ring_idx_mask;\n\tstruct mutex context_lock;\n\tchar debug_name[65];\n\tbool explicit_debug_name;\n};\n\nstruct virtio_gpu_framebuffer {\n\tstruct drm_framebuffer base;\n\tstruct virtio_gpu_fence *fence;\n};\n\nstruct virtio_gpu_get_capset {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 capset_id;\n\t__le32 capset_version;\n};\n\nstruct virtio_gpu_get_capset_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 capset_index;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_mem_entry {\n\t__le64 addr;\n\t__le32 length;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_object {\n\tstruct drm_gem_shmem_object base;\n\tstruct sg_table *sgt;\n\tuint32_t hw_res_handle;\n\tbool dumb;\n\tbool created;\n\tbool attached;\n\tbool host3d_blob;\n\tbool guest_blob;\n\tuint32_t blob_mem;\n\tuint32_t blob_flags;\n\tint uuid_state;\n\tuuid_t uuid;\n};\n\nstruct virtio_gpu_object_array {\n\tstruct ww_acquire_ctx ticket;\n\tstruct list_head next;\n\tu32 nents;\n\tu32 total;\n\tstruct drm_gem_object *objs[0];\n};\n\nstruct virtio_gpu_object_params {\n\tlong unsigned int size;\n\tbool dumb;\n\tbool virgl;\n\tbool blob;\n\tuint32_t format;\n\tuint32_t width;\n\tuint32_t height;\n\tuint32_t target;\n\tuint32_t bind;\n\tuint32_t depth;\n\tuint32_t array_size;\n\tuint32_t last_level;\n\tuint32_t nr_samples;\n\tuint32_t flags;\n\tuint32_t ctx_id;\n\tuint32_t blob_mem;\n\tuint32_t blob_flags;\n\tuint64_t blob_id;\n};\n\nstruct virtio_gpu_object_shmem {\n\tstruct virtio_gpu_object base;\n};\n\nstruct virtio_gpu_object_vram {\n\tstruct virtio_gpu_object base;\n\tuint32_t map_state;\n\tuint32_t map_info;\n\tstruct drm_mm_node vram_node;\n};\n\nstruct virtio_gpu_plane_state {\n\tstruct drm_plane_state base;\n\tstruct virtio_gpu_fence *fence;\n};\n\nstruct virtio_gpu_resource_assign_uuid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_attach_backing {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 nr_entries;\n};\n\nstruct virtio_gpu_resource_create_2d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 format;\n\t__le32 width;\n\t__le32 height;\n};\n\nstruct virtio_gpu_resource_create_3d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 target;\n\t__le32 format;\n\t__le32 bind;\n\t__le32 width;\n\t__le32 height;\n\t__le32 depth;\n\t__le32 array_size;\n\t__le32 last_level;\n\t__le32 nr_samples;\n\t__le32 flags;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_create_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 blob_mem;\n\t__le32 blob_flags;\n\t__le32 nr_entries;\n\t__le64 blob_id;\n\t__le64 size;\n};\n\nstruct virtio_gpu_resource_detach_backing {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_flush {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_map_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n\t__le64 offset;\n};\n\nstruct virtio_gpu_resource_unmap_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resource_unref {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resp_capset {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__u8 capset_data[0];\n};\n\nstruct virtio_gpu_resp_capset_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 capset_id;\n\t__le32 capset_max_version;\n\t__le32 capset_max_size;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_resp_display_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_display_one pmodes[16];\n};\n\nstruct virtio_gpu_resp_edid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__le32 size;\n\t__le32 padding;\n\t__u8 edid[1024];\n};\n\nstruct virtio_gpu_resp_map_info {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__u32 map_info;\n\t__u32 padding;\n};\n\nstruct virtio_gpu_resp_resource_uuid {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\t__u8 uuid[16];\n};\n\nstruct virtio_gpu_set_scanout {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le32 scanout_id;\n\t__le32 resource_id;\n};\n\nstruct virtio_gpu_set_scanout_blob {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le32 scanout_id;\n\t__le32 resource_id;\n\t__le32 width;\n\t__le32 height;\n\t__le32 format;\n\t__le32 padding;\n\t__le32 strides[4];\n\t__le32 offsets[4];\n};\n\nstruct virtio_gpu_submit_post_dep;\n\nstruct virtio_gpu_submit {\n\tstruct virtio_gpu_submit_post_dep *post_deps;\n\tunsigned int num_out_syncobjs;\n\tstruct drm_syncobj **in_syncobjs;\n\tunsigned int num_in_syncobjs;\n\tstruct virtio_gpu_object_array *buflist;\n\tstruct drm_virtgpu_execbuffer *exbuf;\n\tstruct virtio_gpu_fence *out_fence;\n\tstruct virtio_gpu_fpriv *vfpriv;\n\tstruct virtio_gpu_device *vgdev;\n\tstruct sync_file *sync_file;\n\tstruct drm_file *file;\n\tint out_fence_fd;\n\tu64 fence_ctx;\n\tu32 ring_idx;\n\tvoid *buf;\n};\n\nstruct virtio_gpu_submit_post_dep {\n\tstruct drm_syncobj *syncobj;\n\tstruct dma_fence_chain *chain;\n\tu64 point;\n};\n\nstruct virtio_gpu_transfer_host_3d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_box box;\n\t__le64 offset;\n\t__le32 resource_id;\n\t__le32 level;\n\t__le32 stride;\n\t__le32 layer_stride;\n};\n\nstruct virtio_gpu_transfer_to_host_2d {\n\tstruct virtio_gpu_ctrl_hdr hdr;\n\tstruct virtio_gpu_rect r;\n\t__le64 offset;\n\t__le32 resource_id;\n\t__le32 padding;\n};\n\nstruct virtio_gpu_vbuffer;\n\ntypedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *, struct virtio_gpu_vbuffer *);\n\nstruct virtio_gpu_vbuffer {\n\tchar *buf;\n\tint size;\n\tvoid *data_buf;\n\tuint32_t data_size;\n\tchar *resp_buf;\n\tint resp_size;\n\tvirtio_gpu_resp_cb resp_cb;\n\tvoid *resp_cb_data;\n\tstruct virtio_gpu_object_array *objs;\n\tstruct list_head list;\n\tuint32_t seqno;\n};\n\nstruct virtio_input_event {\n\t__le16 type;\n\t__le16 code;\n\t__le32 value;\n};\n\nstruct virtio_input {\n\tstruct virtio_device *vdev;\n\tstruct input_dev *idev;\n\tchar name[64];\n\tchar serial[64];\n\tchar phys[64];\n\tstruct virtqueue *evt;\n\tstruct virtqueue *sts;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_input_event evts[64];\n\t__u8 __cacheline_group_end__[0];\n\tspinlock_t lock;\n\tbool ready;\n};\n\nstruct virtio_input_absinfo {\n\t__le32 min;\n\t__le32 max;\n\t__le32 fuzz;\n\t__le32 flat;\n\t__le32 res;\n};\n\nstruct virtio_input_devids {\n\t__le16 bustype;\n\t__le16 vendor;\n\t__le16 product;\n\t__le16 version;\n};\n\nstruct virtio_input_config {\n\t__u8 select;\n\t__u8 subsel;\n\t__u8 size;\n\t__u8 reserved[5];\n\tunion {\n\t\tchar string[128];\n\t\t__u8 bitmap[128];\n\t\tstruct virtio_input_absinfo abs;\n\t\tstruct virtio_input_devids ids;\n\t} u;\n};\n\nstruct virtio_map_ops {\n\tdma_addr_t (*map_page)(union virtio_map, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid * (*alloc)(union virtio_map, size_t, dma_addr_t *, gfp_t);\n\tvoid (*free)(union virtio_map, size_t, void *, dma_addr_t, long unsigned int);\n\tbool (*need_sync)(union virtio_map, dma_addr_t);\n\tint (*mapping_error)(union virtio_map, dma_addr_t);\n\tsize_t (*max_mapping_size)(union virtio_map);\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1 {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\tunion {\n\t\tstruct {\n\t\t\t__virtio16 csum_start;\n\t\t\t__virtio16 csum_offset;\n\t\t};\n\t\tstruct {\n\t\t\t__virtio16 start;\n\t\t\t__virtio16 offset;\n\t\t} csum;\n\t\tstruct {\n\t\t\t__le16 segments;\n\t\t\t__le16 dup_acks;\n\t\t} rsc;\n\t};\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1_hash {\n\tstruct virtio_net_hdr_v1 hdr;\n\t__le16 hash_value_lo;\n\t__le16 hash_value_hi;\n\t__le16 hash_report;\n\t__le16 padding;\n};\n\nstruct virtio_net_hdr_v1_hash_tunnel {\n\tstruct virtio_net_hdr_v1_hash hash_hdr;\n\t__le16 outer_th_offset;\n\t__le16 inner_nh_offset;\n};\n\nstruct virtio_net_common_hdr {\n\tunion {\n\t\tstruct virtio_net_hdr hdr;\n\t\tstruct virtio_net_hdr_mrg_rxbuf mrg_hdr;\n\t\tstruct virtio_net_hdr_v1_hash hash_v1_hdr;\n\t\tstruct virtio_net_hdr_v1_hash_tunnel tnl_hdr;\n\t};\n};\n\nstruct virtio_net_config {\n\t__u8 mac[6];\n\t__virtio16 status;\n\t__virtio16 max_virtqueue_pairs;\n\t__virtio16 mtu;\n\t__le32 speed;\n\t__u8 duplex;\n\t__u8 rss_max_key_size;\n\t__le16 rss_max_indirection_table_length;\n\t__le32 supported_hash_types;\n};\n\nstruct virtio_net_ctrl_coal {\n\t__le32 max_packets;\n\t__le32 max_usecs;\n};\n\nstruct virtio_net_ctrl_coal_rx {\n\t__le32 rx_max_packets;\n\t__le32 rx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_tx {\n\t__le32 tx_max_packets;\n\t__le32 tx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_vq {\n\t__le16 vqn;\n\t__le16 reserved;\n\tstruct virtio_net_ctrl_coal coal;\n};\n\nstruct virtio_net_ctrl_mac {\n\t__virtio32 entries;\n\t__u8 macs[0];\n};\n\nstruct virtio_net_ctrl_mq {\n\t__virtio16 virtqueue_pairs;\n};\n\nstruct virtio_net_ctrl_queue_stats {\n\tstruct {\n\t\t__le16 vq_index;\n\t\t__le16 reserved[3];\n\t\t__le64 types_bitmap[1];\n\t} stats[1];\n};\n\nstruct virtio_net_rss_config_hdr {\n\t__le32 hash_types;\n\t__le16 indirection_table_mask;\n\t__le16 unclassified_queue;\n\t__le16 indirection_table[0];\n};\n\nstruct virtio_net_rss_config_trailer {\n\t__le16 max_tx_vq;\n\t__u8 hash_key_length;\n\t__u8 hash_key_data[0];\n};\n\nstruct virtio_net_stats_capabilities {\n\t__le64 supported_stats_types[1];\n};\n\nstruct virtio_net_stats_reply_hdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__le16 vq_index;\n\t__le16 reserved1;\n\t__le16 size;\n};\n\nstruct virtio_pci_vq_info;\n\nstruct virtio_pci_admin_vq {\n\tstruct virtio_pci_vq_info *info;\n\tspinlock_t lock;\n\tu64 supported_cmds;\n\tu64 supported_caps;\n\tu8 max_dev_parts_objects;\n\tstruct ida dev_parts_ida;\n\tchar name[10];\n\tu16 vq_index;\n};\n\nstruct virtio_pci_common_cfg {\n\t__le32 device_feature_select;\n\t__le32 device_feature;\n\t__le32 guest_feature_select;\n\t__le32 guest_feature;\n\t__le16 msix_config;\n\t__le16 num_queues;\n\t__u8 device_status;\n\t__u8 config_generation;\n\t__le16 queue_select;\n\t__le16 queue_size;\n\t__le16 queue_msix_vector;\n\t__le16 queue_enable;\n\t__le16 queue_notify_off;\n\t__le32 queue_desc_lo;\n\t__le32 queue_desc_hi;\n\t__le32 queue_avail_lo;\n\t__le32 queue_avail_hi;\n\t__le32 queue_used_lo;\n\t__le32 queue_used_hi;\n};\n\nstruct virtio_pci_legacy_device {\n\tstruct pci_dev *pci_dev;\n\tu8 *isr;\n\tvoid *ioaddr;\n\tstruct virtio_device_id id;\n};\n\nstruct virtio_pci_modern_device {\n\tstruct pci_dev *pci_dev;\n\tstruct virtio_pci_common_cfg *common;\n\tvoid *device;\n\tvoid *notify_base;\n\tresource_size_t notify_pa;\n\tu8 *isr;\n\tsize_t notify_len;\n\tsize_t device_len;\n\tsize_t common_len;\n\tint notify_map_cap;\n\tu32 notify_offset_multiplier;\n\tint modern_bars;\n\tstruct virtio_device_id id;\n\tint (*device_id_check)(struct pci_dev *);\n\tu64 dma_mask;\n};\n\nstruct virtio_pci_device {\n\tstruct virtio_device vdev;\n\tstruct pci_dev *pci_dev;\n\tunion {\n\t\tstruct virtio_pci_legacy_device ldev;\n\t\tstruct virtio_pci_modern_device mdev;\n\t};\n\tbool is_legacy;\n\tu8 *isr;\n\tspinlock_t lock;\n\tstruct list_head virtqueues;\n\tstruct list_head slow_virtqueues;\n\tstruct virtio_pci_vq_info **vqs;\n\tstruct virtio_pci_admin_vq admin_vq;\n\tint msix_enabled;\n\tint intx_enabled;\n\tcpumask_var_t *msix_affinity_masks;\n\tchar (*msix_names)[256];\n\tunsigned int msix_vectors;\n\tunsigned int msix_used_vectors;\n\tbool per_vq_vectors;\n\tstruct virtqueue * (*setup_vq)(struct virtio_pci_device *, struct virtio_pci_vq_info *, unsigned int, void (*)(struct virtqueue *), const char *, bool, u16);\n\tvoid (*del_vq)(struct virtio_pci_vq_info *);\n\tu16 (*config_vector)(struct virtio_pci_device *, u16);\n\tint (*avq_index)(struct virtio_device *, u16 *, u16 *);\n};\n\nstruct virtio_pci_modern_common_cfg {\n\tstruct virtio_pci_common_cfg cfg;\n\t__le16 queue_notify_data;\n\t__le16 queue_reset;\n\t__le16 admin_queue_index;\n\t__le16 admin_queue_num;\n};\n\nstruct virtio_pci_vq_info {\n\tstruct virtqueue *vq;\n\tstruct list_head node;\n\tunsigned int msix_vector;\n};\n\nstruct virtio_resource_obj_dev_parts {\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_scsi;\n\nstruct virtio_scsi_event;\n\nstruct virtio_scsi_event_node {\n\tstruct virtio_scsi *vscsi;\n\tstruct virtio_scsi_event *event;\n\tstruct work_struct work;\n};\n\nstruct virtio_scsi_vq {\n\tspinlock_t vq_lock;\n\tstruct virtqueue *vq;\n};\n\nstruct virtio_scsi_event {\n\t__virtio32 event;\n\t__u8 lun[8];\n\t__virtio32 reason;\n};\n\nstruct virtio_scsi {\n\tstruct virtio_device *vdev;\n\tstruct virtio_scsi_event_node event_list[8];\n\tu32 num_queues;\n\tint io_queues[3];\n\tstruct hlist_node node;\n\tbool stop_events;\n\tstruct virtio_scsi_vq ctrl_vq;\n\tstruct virtio_scsi_vq event_vq;\n\t__u8 __cacheline_group_begin__[0];\n\tstruct virtio_scsi_event events[8];\n\t__u8 __cacheline_group_end__[0];\n\tstruct virtio_scsi_vq req_vqs[0];\n};\n\nstruct virtio_scsi_cmd_req {\n\t__u8 lun[8];\n\t__virtio64 tag;\n\t__u8 task_attr;\n\t__u8 prio;\n\t__u8 crn;\n\t__u8 cdb[32];\n} __attribute__((packed));\n\nstruct virtio_scsi_cmd_req_pi {\n\t__u8 lun[8];\n\t__virtio64 tag;\n\t__u8 task_attr;\n\t__u8 prio;\n\t__u8 crn;\n\t__virtio32 pi_bytesout;\n\t__virtio32 pi_bytesin;\n\t__u8 cdb[32];\n} __attribute__((packed));\n\nstruct virtio_scsi_ctrl_tmf_req {\n\t__virtio32 type;\n\t__virtio32 subtype;\n\t__u8 lun[8];\n\t__virtio64 tag;\n};\n\nstruct virtio_scsi_ctrl_an_req {\n\t__virtio32 type;\n\t__u8 lun[8];\n\t__virtio32 event_requested;\n};\n\nstruct virtio_scsi_cmd_resp {\n\t__virtio32 sense_len;\n\t__virtio32 resid;\n\t__virtio16 status_qualifier;\n\t__u8 status;\n\t__u8 response;\n\t__u8 sense[96];\n};\n\nstruct virtio_scsi_ctrl_tmf_resp {\n\t__u8 response;\n};\n\nstruct virtio_scsi_ctrl_an_resp {\n\t__virtio32 event_actual;\n\t__u8 response;\n} __attribute__((packed));\n\nstruct virtio_scsi_cmd {\n\tstruct scsi_cmnd *sc;\n\tstruct completion *comp;\n\tunion {\n\t\tstruct virtio_scsi_cmd_req cmd;\n\t\tstruct virtio_scsi_cmd_req_pi cmd_pi;\n\t\tstruct virtio_scsi_ctrl_tmf_req tmf;\n\t\tstruct virtio_scsi_ctrl_an_req an;\n\t} req;\n\tunion {\n\t\tstruct virtio_scsi_cmd_resp cmd;\n\t\tstruct virtio_scsi_ctrl_tmf_resp tmf;\n\t\tstruct virtio_scsi_ctrl_an_resp an;\n\t\tstruct virtio_scsi_event evt;\n\t} resp;\n\tlong: 64;\n} __attribute__((packed));\n\nstruct virtio_scsi_config {\n\t__virtio32 num_queues;\n\t__virtio32 seg_max;\n\t__virtio32 max_sectors;\n\t__virtio32 cmd_per_lun;\n\t__virtio32 event_info_size;\n\t__virtio32 sense_size;\n\t__virtio32 cdb_size;\n\t__virtio16 max_channel;\n\t__virtio16 max_target;\n\t__virtio32 max_lun;\n};\n\nstruct virtnet_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *cvq;\n\tstruct net_device *dev;\n\tstruct send_queue *sq;\n\tstruct receive_queue *rq;\n\tunsigned int status;\n\tu16 max_queue_pairs;\n\tu16 curr_queue_pairs;\n\tu16 xdp_queue_pairs;\n\tbool xdp_enabled;\n\tbool big_packets;\n\tunsigned int big_packets_num_skbfrags;\n\tbool mergeable_rx_bufs;\n\tbool has_rss;\n\tbool has_rss_hash_report;\n\tu8 rss_key_size;\n\tu16 rss_indir_table_size;\n\tu32 rss_hash_types_supported;\n\tu32 rss_hash_types_saved;\n\tbool has_cvq;\n\tstruct mutex cvq_lock;\n\tbool any_header_sg;\n\tu8 hdr_len;\n\tbool tx_tnl;\n\tbool rx_tnl;\n\tbool rx_tnl_csum;\n\tstruct work_struct config_work;\n\tstruct work_struct rx_mode_work;\n\tbool rx_mode_work_enabled;\n\tbool affinity_hint_set;\n\tstruct hlist_node node;\n\tstruct hlist_node node_dead;\n\tstruct control_buf *ctrl;\n\tu8 duplex;\n\tu32 speed;\n\tbool rx_dim_enabled;\n\tstruct virtnet_interrupt_coalesce intr_coal_tx;\n\tstruct virtnet_interrupt_coalesce intr_coal_rx;\n\tlong unsigned int guest_offloads;\n\tlong unsigned int guest_offloads_capable;\n\tstruct failover *failover;\n\tu64 device_stats_cap;\n\tstruct virtio_net_rss_config_hdr *rss_hdr;\n\tunion {\n\t\tstruct virtio_net_rss_config_trailer rss_trailer;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[3];\n\t\t\tu8 rss_hash_key_data[40];\n\t\t};\n\t};\n};\n\nstruct virtnet_rq_dma {\n\tdma_addr_t addr;\n\tu32 ref;\n\tu16 len;\n\tu16 need_sync;\n};\n\nstruct virtnet_sq_free_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 napi_packets;\n\tu64 napi_bytes;\n\tu64 xsk;\n};\n\nstruct virtnet_stat_desc {\n\tchar desc[32];\n\tsize_t offset;\n\tsize_t qstat_offset;\n};\n\nstruct virtnet_stats_ctx {\n\tbool to_qstat;\n\tu32 desc_num[3];\n\tu64 bitmap[3];\n\tu32 size[3];\n\tu64 *data;\n};\n\nstruct virtqueue {\n\tstruct list_head list;\n\tvoid (*callback)(struct virtqueue *);\n\tconst char *name;\n\tstruct virtio_device *vdev;\n\tunsigned int index;\n\tunsigned int num_free;\n\tunsigned int num_max;\n\tbool reset;\n\tvoid *priv;\n};\n\ntypedef void vq_callback_t(struct virtqueue *);\n\nstruct virtqueue_info {\n\tconst char *name;\n\tvq_callback_t *callback;\n\tbool ctx;\n};\n\nstruct vring_virtqueue;\n\nstruct virtqueue_ops {\n\tint (*add)(struct vring_virtqueue *, struct scatterlist **, unsigned int, unsigned int, unsigned int, void *, void *, bool, gfp_t, long unsigned int);\n\tvoid * (*get)(struct vring_virtqueue *, unsigned int *, void **);\n\tbool (*kick_prepare)(struct vring_virtqueue *);\n\tvoid (*disable_cb)(struct vring_virtqueue *);\n\tbool (*enable_cb_delayed)(struct vring_virtqueue *);\n\tunsigned int (*enable_cb_prepare)(struct vring_virtqueue *);\n\tbool (*poll)(const struct vring_virtqueue *, unsigned int);\n\tvoid * (*detach_unused_buf)(struct vring_virtqueue *);\n\tbool (*more_used)(const struct vring_virtqueue *);\n\tint (*resize)(struct vring_virtqueue *, u32);\n\tvoid (*reset)(struct vring_virtqueue *);\n};\n\nstruct virtual_engine {\n\tstruct intel_engine_cs base;\n\tstruct intel_context context;\n\tstruct rcu_work rcu;\n\tstruct i915_request *request;\n\tstruct ve_node nodes[27];\n\tunsigned int num_siblings;\n\tstruct intel_engine_cs *siblings[0];\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vlv_s0ix_state {\n\tu32 wr_watermark;\n\tu32 gfx_prio_ctrl;\n\tu32 arb_mode;\n\tu32 gfx_pend_tlb0;\n\tu32 gfx_pend_tlb1;\n\tu32 lra_limits[13];\n\tu32 media_max_req_count;\n\tu32 gfx_max_req_count;\n\tu32 render_hwsp;\n\tu32 ecochk;\n\tu32 bsd_hwsp;\n\tu32 blt_hwsp;\n\tu32 tlb_rd_addr;\n\tu32 g3dctl;\n\tu32 gsckgctl;\n\tu32 mbctl;\n\tu32 ucgctl1;\n\tu32 ucgctl3;\n\tu32 rcgctl1;\n\tu32 rcgctl2;\n\tu32 rstctl;\n\tu32 misccpctl;\n\tu32 gfxpause;\n\tu32 rpdeuhwtc;\n\tu32 rpdeuc;\n\tu32 ecobus;\n\tu32 pwrdwnupctl;\n\tu32 rp_down_timeout;\n\tu32 rp_deucsw;\n\tu32 rcubmabdtmr;\n\tu32 rcedata;\n\tu32 spare2gh;\n\tu32 gt_imr;\n\tu32 gt_ier;\n\tu32 pm_imr;\n\tu32 pm_ier;\n\tu32 gt_scratch[8];\n\tu32 tilectl;\n\tu32 gt_fifoctl;\n\tu32 gtlc_wake_ctrl;\n\tu32 gtlc_survive;\n\tu32 pmwgicz;\n\tu32 gu_ctl0;\n\tu32 gu_ctl1;\n\tu32 pcbr;\n\tu32 clock_gate_dis2;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {};\n\nstruct vma_numab_state;\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tunsigned int vm_lock_seq;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct mempolicy *vm_policy;\n\tstruct vma_numab_state *numab_state;\n\trefcount_t vm_refcnt;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n\tstruct pfnmap_track_ctx *pfnmap_track_ctx;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[91];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n\tint (*set_policy)(struct vm_area_struct *, struct mempolicy *);\n\tstruct mempolicy * (*get_policy)(struct vm_area_struct *, long unsigned int, long unsigned int *);\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct vm_stack {\n\tstruct callback_head rcu;\n\tstruct vm_struct *stack_vm_area;\n};\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int page_order;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_exclude_readers_state {\n\tstruct vm_area_struct *vma;\n\tint state;\n\tbool detaching;\n\tbool detached;\n\tbool exclusive;\n};\n\nstruct vma_list {\n\tstruct vm_area_struct *vma;\n\tstruct list_head head;\n\trefcount_t mmap_count;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_numab_state {\n\tlong unsigned int next_scan;\n\tlong unsigned int pids_active_reset;\n\tlong unsigned int pids_active[2];\n\tint start_scan_seq;\n\tint prev_scan_seq;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[16];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmap_pfn_data {\n\tlong unsigned int *pfns;\n\tpgprot_t prot;\n\tunsigned int idx;\n};\n\nstruct vmclock_abi {\n\t__le32 magic;\n\t__le32 size;\n\t__le16 version;\n\t__u8 counter_id;\n\t__u8 time_type;\n\t__le32 seq_count;\n\t__le64 disruption_marker;\n\t__le64 flags;\n\t__u8 pad[2];\n\t__u8 clock_status;\n\t__u8 leap_second_smearing_hint;\n\t__le16 tai_offset_sec;\n\t__u8 leap_indicator;\n\t__u8 counter_period_shift;\n\t__le64 counter_value;\n\t__le64 counter_period_frac_sec;\n\t__le64 counter_period_esterror_rate_frac_sec;\n\t__le64 counter_period_maxerror_rate_frac_sec;\n\t__le64 time_sec;\n\t__le64 time_frac_sec;\n\t__le64 time_esterror_nanosec;\n\t__le64 time_maxerror_nanosec;\n\t__le64 vm_generation_counter;\n};\n\nstruct vmclock_state;\n\nstruct vmclock_file_state {\n\tstruct vmclock_state *st;\n\tatomic_t seq;\n};\n\nstruct vmclock_state {\n\tstruct resource res;\n\tstruct vmclock_abi *clk;\n\tstruct miscdevice miscdev;\n\twait_queue_head_t disrupt_wait;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct ptp_clock *ptp_clock;\n\tenum clocksource_ids cs_id;\n\tenum clocksource_ids sys_cs_id;\n\tint index;\n\tchar *name;\n};\n\nstruct vmcore_cb {\n\tbool (*pfn_is_ram)(struct vmcore_cb *, long unsigned int);\n\tint (*get_device_ram)(struct vmcore_cb *, struct list_head *);\n\tstruct list_head next;\n};\n\nstruct vmcore_range {\n\tstruct list_head list;\n\tlong long unsigned int paddr;\n\tlong long unsigned int size;\n\tloff_t offset;\n};\n\nstruct vmemmap_remap_walk {\n\tvoid (*remap_pte)(pte_t *, long unsigned int, struct vmemmap_remap_walk *);\n\tlong unsigned int nr_walked;\n\tstruct page *reuse_page;\n\tlong unsigned int reuse_addr;\n\tstruct list_head *vmemmap_pages;\n\tlong unsigned int flags;\n};\n\nstruct vmware_steal_time {\n\tunion {\n\t\tu64 clock;\n\t\tstruct {\n\t\t\tu32 clock_low;\n\t\t\tu32 clock_high;\n\t\t};\n\t};\n\tu64 reserved[7];\n};\n\nstruct vring_desc;\n\ntypedef struct vring_desc vring_desc_t;\n\nstruct vring_avail;\n\ntypedef struct vring_avail vring_avail_t;\n\nstruct vring_used;\n\ntypedef struct vring_used vring_used_t;\n\nstruct vring {\n\tunsigned int num;\n\tvring_desc_t *desc;\n\tvring_avail_t *avail;\n\tvring_used_t *used;\n};\n\nstruct vring_avail {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\t__virtio16 ring[0];\n};\n\nstruct vring_desc {\n\t__virtio64 addr;\n\t__virtio32 len;\n\t__virtio16 flags;\n\t__virtio16 next;\n};\n\nstruct vring_desc_extra {\n\tdma_addr_t addr;\n\tu32 len;\n\tu16 flags;\n\tu16 next;\n};\n\nstruct vring_packed_desc;\n\nstruct vring_desc_state_packed {\n\tvoid *data;\n\tstruct vring_packed_desc *indir_desc;\n\tu16 num;\n\tu16 last;\n\tu32 total_in_len;\n};\n\nstruct vring_desc_state_split {\n\tvoid *data;\n\tstruct vring_desc *indir_desc;\n\tu32 total_in_len;\n};\n\nstruct vring_packed_desc {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 id;\n\t__le16 flags;\n};\n\nstruct vring_packed_desc_event {\n\t__le16 off_wrap;\n\t__le16 flags;\n};\n\nstruct vring_used_elem {\n\t__virtio32 id;\n\t__virtio32 len;\n};\n\ntypedef struct vring_used_elem vring_used_elem_t;\n\nstruct vring_used {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\tvring_used_elem_t ring[0];\n};\n\nstruct vring_virtqueue_split {\n\tstruct vring vring;\n\tu16 avail_flags_shadow;\n\tu16 avail_idx_shadow;\n\tstruct vring_desc_state_split *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t queue_dma_addr;\n\tsize_t queue_size_in_bytes;\n\tu32 vring_align;\n\tbool may_reduce_num;\n};\n\nstruct vring_virtqueue_packed {\n\tstruct {\n\t\tunsigned int num;\n\t\tstruct vring_packed_desc *desc;\n\t\tstruct vring_packed_desc_event *driver;\n\t\tstruct vring_packed_desc_event *device;\n\t} vring;\n\tbool avail_wrap_counter;\n\tu16 avail_used_flags;\n\tu16 next_avail_idx;\n\tu16 event_flags_shadow;\n\tstruct vring_desc_state_packed *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t ring_dma_addr;\n\tdma_addr_t driver_event_dma_addr;\n\tdma_addr_t device_event_dma_addr;\n\tsize_t ring_size_in_bytes;\n\tsize_t event_size_in_bytes;\n};\n\nstruct vring_virtqueue {\n\tstruct virtqueue vq;\n\tbool use_map_api;\n\tbool weak_barriers;\n\tbool broken;\n\tbool indirect;\n\tbool event;\n\tenum vq_layout layout;\n\tunsigned int free_head;\n\tstruct used_entry batch_last;\n\tunsigned int num_added;\n\tu16 last_used_idx;\n\tu16 last_used;\n\tbool event_triggered;\n\tunion {\n\t\tstruct vring_virtqueue_split split;\n\t\tstruct vring_virtqueue_packed packed;\n\t};\n\tbool (*notify)(struct virtqueue *);\n\tbool we_own_ring;\n\tunion virtio_map map;\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_barrier {\n\tstruct wait_queue_entry base;\n\tstruct i915_active *ref;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wait_rps_boost {\n\tstruct wait_queue_entry wait;\n\tstruct drm_crtc *crtc;\n\tstruct dma_fence *fence;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nstruct wakeup_header {\n\tu16 video_mode;\n\tu32 pmode_entry;\n\tu16 pmode_cs;\n\tu32 pmode_cr0;\n\tu32 pmode_cr3;\n\tu32 pmode_cr4;\n\tu32 pmode_efer_low;\n\tu32 pmode_efer_high;\n\tu64 pmode_gdt;\n\tu32 pmode_misc_en_low;\n\tu32 pmode_misc_en_high;\n\tu32 pmode_behavior;\n\tu32 realmode_flags;\n\tu32 real_magic;\n\tu32 signature;\n} __attribute__((packed));\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n};\n\nstruct walk_rcec_data {\n\tstruct pci_dev *rcec;\n\tint (*user_callback)(struct pci_dev *, void *);\n\tvoid *user_data;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct wbrf_ranges_in_out {\n\tu64 num_of_ranges;\n\tstruct freq_band_range band_list[11];\n};\n\nstruct weighted_interleave_state {\n\tbool mode_auto;\n\tu8 iw_table[0];\n};\n\nstruct widget_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct hdac_device *, hda_nid_t, struct widget_attribute *, char *);\n\tssize_t (*store)(struct hdac_device *, hda_nid_t, struct widget_attribute *, const char *, size_t);\n};\n\ntypedef struct wiphy *class_wiphy_t;\n\nstruct wiphy_coalesce_support {\n\tint n_rules;\n\tint max_delay;\n\tint n_patterns;\n\tint pattern_max_len;\n\tint pattern_min_len;\n\tint max_pkt_offset;\n};\n\nstruct wiphy_iftype_akm_suites {\n\tu16 iftypes_mask;\n\tconst u32 *akm_suites;\n\tint n_akm_suites;\n};\n\nstruct wiphy_iftype_ext_capab {\n\tenum nl80211_iftype iftype;\n\tconst u8 *extended_capabilities;\n\tconst u8 *extended_capabilities_mask;\n\tu8 extended_capabilities_len;\n\tu16 eml_capabilities;\n\tu16 mld_capa_and_ops;\n};\n\nstruct wiphy_radio_freq_range;\n\nstruct wiphy_radio {\n\tconst struct wiphy_radio_freq_range *freq_range;\n\tint n_freq_range;\n\tconst struct ieee80211_iface_combination *iface_combinations;\n\tint n_iface_combinations;\n\tu32 antenna_mask;\n};\n\nstruct wiphy_radio_cfg {\n\tu32 rts_threshold;\n\tstruct dentry *radio_debugfsdir;\n};\n\nstruct wiphy_radio_freq_range {\n\tu32 start_freq;\n\tu32 end_freq;\n};\n\nstruct wiphy_vendor_command {\n\tstruct nl80211_vendor_cmd_info info;\n\tu32 flags;\n\tint (*doit)(struct wiphy *, struct wireless_dev *, const void *, int);\n\tint (*dumpit)(struct wiphy *, struct wireless_dev *, struct sk_buff *, const void *, int, long unsigned int *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n};\n\nstruct wiphy_wowlan_tcp_support;\n\nstruct wiphy_wowlan_support {\n\tu32 flags;\n\tint n_patterns;\n\tint pattern_max_len;\n\tint pattern_min_len;\n\tint max_pkt_offset;\n\tint max_nd_match_sets;\n\tconst struct wiphy_wowlan_tcp_support *tcp;\n};\n\nstruct wiphy_wowlan_tcp_support {\n\tconst struct nl80211_wowlan_tcp_data_token_feature *tok;\n\tu32 data_payload_max;\n\tu32 data_interval_max;\n\tu32 wake_payload_max;\n\tbool seq;\n};\n\nstruct wired_cmd_ake_send_hprime_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 h_prime[32];\n};\n\nstruct wired_cmd_ake_send_hprime_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_ake_send_pairing_info_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 e_kh_km[16];\n};\n\nstruct wired_cmd_ake_send_pairing_info_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_close_session_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_close_session_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_enable_auth_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 stream_type;\n} __attribute__((packed));\n\nstruct wired_cmd_enable_auth_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_get_session_key_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_get_session_key_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 e_dkey_ks[16];\n\tu8 r_iv[8];\n};\n\nstruct wired_cmd_init_locality_check_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_init_locality_check_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 r_n[8];\n};\n\nstruct wired_cmd_initiate_hdcp2_session_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 protocol;\n} __attribute__((packed));\n\nstruct wired_cmd_initiate_hdcp2_session_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 r_tx[8];\n\tstruct hdcp2_tx_caps tx_caps;\n} __attribute__((packed));\n\nstruct wired_cmd_repeater_auth_stream_req_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 seq_num_m[3];\n\tu8 m_prime[32];\n\t__be16 k;\n\tstruct hdcp2_streamid_type streams[0];\n} __attribute__((packed));\n\nstruct wired_cmd_repeater_auth_stream_req_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_validate_locality_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 l_prime[32];\n};\n\nstruct wired_cmd_validate_locality_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n};\n\nstruct wired_cmd_verify_receiver_cert_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tstruct hdcp2_cert_rx cert_rx;\n\tu8 r_rx[8];\n\tu8 rx_caps[3];\n} __attribute__((packed));\n\nstruct wired_cmd_verify_receiver_cert_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 km_stored;\n\tu8 reserved[3];\n\tunion encrypted_buff ekm_buff;\n};\n\nstruct wired_cmd_verify_repeater_in {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 rx_info[2];\n\tu8 seq_num_v[3];\n\tu8 v_prime[16];\n\tu8 receiver_ids[155];\n};\n\nstruct wired_cmd_verify_repeater_out {\n\tstruct hdcp_cmd_header header;\n\tstruct hdcp_port_id port;\n\tu8 content_type_supported;\n\tu8 v[16];\n} __attribute__((packed));\n\nstruct wmi_device {\n\tstruct device dev;\n\tbool setable;\n\tconst char *driver_override;\n};\n\ntypedef void (*wmi_notify_handler)(union acpi_object *, void *);\n\nstruct wmi_block {\n\tstruct wmi_device dev;\n\tstruct guid_block gblock;\n\tstruct acpi_device *acpi_device;\n\tstruct rw_semaphore notify_lock;\n\twmi_notify_handler handler;\n\tvoid *handler_data;\n\tbool driver_ready;\n\tlong unsigned int flags;\n};\n\nstruct wmi_brightness_args {\n\tu32 mode;\n\tu32 val;\n\tu32 ret;\n\tu32 ignored[3];\n};\n\nstruct wmi_buffer {\n\tsize_t length;\n\tvoid *data;\n};\n\nstruct wmi_device_id {\n\tconst char guid_string[37];\n\tconst void *context;\n};\n\nstruct wmi_driver {\n\tstruct device_driver driver;\n\tconst struct wmi_device_id *id_table;\n\tbool no_notify_data;\n\tbool no_singleton;\n\tint (*probe)(struct wmi_device *, const void *);\n\tvoid (*remove)(struct wmi_device *);\n\tvoid (*shutdown)(struct wmi_device *);\n\tvoid (*notify)(struct wmi_device *, union acpi_object *);\n\tvoid (*notify_new)(struct wmi_device *, const struct wmi_buffer *);\n};\n\nstruct wmi_guid_count_context {\n\tconst guid_t *guid;\n\tint count;\n};\n\nstruct wmi_string {\n\t__le16 length;\n\t__le16 chars[0];\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int one_bits;\n\tconst long unsigned int high_bits;\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct work_queue_wrapper {\n\tstruct work_struct work;\n\tstruct scsi_device *sdev;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct write_opcode_ctx {\n\tlong unsigned int base;\n\tint expect;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct x509_certificate {\n\tstruct x509_certificate *next;\n\tstruct x509_certificate *signer;\n\tstruct public_key *pub;\n\tstruct public_key_signature *sig;\n\tu8 sha256[32];\n\tchar *issuer;\n\tchar *subject;\n\tstruct asymmetric_key_id *id;\n\tstruct asymmetric_key_id *skid;\n\ttime64_t valid_from;\n\ttime64_t valid_to;\n\tconst void *tbs;\n\tunsigned int tbs_size;\n\tunsigned int raw_sig_size;\n\tconst void *raw_sig;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_subject;\n\tunsigned int raw_subject_size;\n\tunsigned int raw_skid_size;\n\tconst void *raw_skid;\n\tunsigned int index;\n\tbool seen;\n\tbool verified;\n\tbool self_signed;\n\tbool unsupported_sig;\n\tbool blacklisted;\n};\n\nstruct x509_parse_context {\n\tstruct x509_certificate *cert;\n\tlong unsigned int data;\n\tconst void *key;\n\tsize_t key_size;\n\tconst void *params;\n\tsize_t params_size;\n\tenum OID key_algo;\n\tenum OID last_oid;\n\tenum OID sig_algo;\n\tu8 o_size;\n\tu8 cn_size;\n\tu8 email_size;\n\tu16 o_offset;\n\tu16 cn_offset;\n\tu16 email_offset;\n\tunsigned int raw_akid_size;\n\tconst void *raw_akid;\n\tconst void *akid_raw_issuer;\n\tunsigned int akid_raw_issuer_size;\n};\n\nstruct x64_jit_data {\n\tstruct bpf_binary_header *rw_header;\n\tstruct bpf_binary_header *header;\n\tint *addrs;\n\tu8 *image;\n\tint proglen;\n\tstruct jit_context ctx;\n};\n\nstruct x86_apic_ops {\n\tunsigned int (*io_apic_read)(unsigned int, unsigned int);\n\tvoid (*restore)(void);\n};\n\nstruct x86_cpuinit_ops {\n\tvoid (*setup_percpu_clockev)(void);\n\tvoid (*early_percpu_clock_init)(void);\n\tvoid (*fixup_cpu_id)(struct cpuinfo_x86 *, int);\n\tbool parallel_bringup;\n};\n\nstruct x86_guest {\n\tint (*enc_status_change_prepare)(long unsigned int, int, bool);\n\tint (*enc_status_change_finish)(long unsigned int, int, bool);\n\tbool (*enc_tlb_flush_required)(bool);\n\tbool (*enc_cache_flush_required)(void);\n\tvoid (*enc_kexec_begin)(void);\n\tvoid (*enc_kexec_finish)(void);\n};\n\nstruct x86_hybrid_pmu {\n\tstruct pmu pmu;\n\tconst char *name;\n\tenum hybrid_pmu_type pmu_type;\n\tcpumask_t supported_cpus;\n\tunion perf_capabilities intel_cap;\n\tu64 intel_ctrl;\n\tu64 pebs_events_mask;\n\tu64 config_mask;\n\tunion {\n\t\tu64 cntr_mask64;\n\t\tlong unsigned int cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 fixed_cntr_mask64;\n\t\tlong unsigned int fixed_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cntr_mask64;\n\t\tlong unsigned int acr_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cause_mask64;\n\t\tlong unsigned int acr_cause_mask[1];\n\t};\n\tstruct event_constraint unconstrained;\n\tu64 hw_cache_event_ids[42];\n\tu64 hw_cache_extra_regs[42];\n\tstruct event_constraint *event_constraints;\n\tstruct event_constraint *pebs_constraints;\n\tstruct extra_reg *extra_regs;\n\tunsigned int late_ack: 1;\n\tunsigned int mid_ack: 1;\n\tunsigned int enabled_ack: 1;\n\tstruct arch_pebs_cap arch_pebs_cap;\n\tu64 pebs_data_source[256];\n};\n\nstruct x86_init_acpi {\n\tvoid (*set_root_pointer)(u64);\n\tu64 (*get_root_pointer)(void);\n\tvoid (*reduced_hw_early_init)(void);\n};\n\nstruct x86_init_iommu {\n\tint (*iommu_init)(void);\n};\n\nstruct x86_init_irqs {\n\tvoid (*pre_vector_init)(void);\n\tvoid (*intr_init)(void);\n\tvoid (*intr_mode_select)(void);\n\tvoid (*intr_mode_init)(void);\n\tstruct irq_domain * (*create_pci_msi_domain)(void);\n};\n\nstruct x86_init_mpparse {\n\tvoid (*setup_ioapic_ids)(void);\n\tvoid (*find_mptable)(void);\n\tvoid (*early_parse_smp_cfg)(void);\n\tvoid (*parse_smp_cfg)(void);\n};\n\nstruct x86_init_oem {\n\tvoid (*arch_setup)(void);\n\tvoid (*banner)(void);\n};\n\nstruct x86_init_resources {\n\tvoid (*probe_roms)(void);\n\tvoid (*reserve_resources)(void);\n\tchar * (*memory_setup)(void);\n\tvoid (*dmi_setup)(void);\n};\n\nstruct x86_init_paging {\n\tvoid (*pagetable_init)(void);\n};\n\nstruct x86_init_timers {\n\tvoid (*setup_percpu_clockev)(void);\n\tvoid (*timer_init)(void);\n\tvoid (*wallclock_init)(void);\n};\n\nstruct x86_init_pci {\n\tint (*arch_init)(void);\n\tint (*init)(void);\n\tvoid (*init_irq)(void);\n\tvoid (*fixup_irqs)(void);\n};\n\nstruct x86_init_ops {\n\tstruct x86_init_resources resources;\n\tstruct x86_init_mpparse mpparse;\n\tstruct x86_init_irqs irqs;\n\tstruct x86_init_oem oem;\n\tstruct x86_init_paging paging;\n\tstruct x86_init_timers timers;\n\tstruct x86_init_iommu iommu;\n\tstruct x86_init_pci pci;\n\tstruct x86_hyper_init hyper;\n\tstruct x86_init_acpi acpi;\n};\n\nstruct x86_legacy_devices {\n\tint pnpbios;\n};\n\nstruct x86_legacy_features {\n\tenum x86_legacy_i8042_state i8042;\n\tint rtc;\n\tint warm_reset;\n\tint no_vga;\n\tint reserve_bios_regions;\n\tstruct x86_legacy_devices devices;\n};\n\nstruct x86_mapping_info {\n\tvoid * (*alloc_pgt_page)(void *);\n\tvoid (*free_pgt_page)(void *, void *);\n\tvoid *context;\n\tlong unsigned int page_flag;\n\tlong unsigned int offset;\n\tbool direct_gbpages;\n\tlong unsigned int kernpg_flag;\n};\n\nstruct x86_perf_regs {\n\tstruct pt_regs regs;\n\tu64 *xmm_regs;\n};\n\nstruct x86_perf_task_context_opt {\n\tint lbr_callstack_users;\n\tint lbr_stack_state;\n\tint log_id;\n};\n\nstruct x86_perf_task_context {\n\tu64 lbr_sel;\n\tint tos;\n\tint valid_lbrs;\n\tstruct x86_perf_task_context_opt opt;\n\tstruct lbr_entry lbr[32];\n};\n\nstruct x86_perf_task_context_arch_lbr {\n\tstruct x86_perf_task_context_opt opt;\n\tstruct lbr_entry entries[0];\n};\n\nstruct x86_perf_task_context_arch_lbr_xsave {\n\tstruct x86_perf_task_context_opt opt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct xregs_state xsave;\n\t\tstruct {\n\t\t\tstruct fxregs_state i387;\n\t\t\tstruct xstate_header header;\n\t\t\tstruct arch_lbr_state lbr;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t};\n};\n\nstruct x86_platform_ops {\n\tlong unsigned int (*calibrate_cpu)(void);\n\tlong unsigned int (*calibrate_tsc)(void);\n\tvoid (*get_wallclock)(struct timespec64 *);\n\tint (*set_wallclock)(const struct timespec64 *);\n\tvoid (*iommu_shutdown)(void);\n\tbool (*is_untracked_pat_range)(u64, u64);\n\tvoid (*nmi_init)(void);\n\tunsigned char (*get_nmi_reason)(void);\n\tvoid (*save_sched_clock_state)(void);\n\tvoid (*restore_sched_clock_state)(void);\n\tvoid (*apic_post_init)(void);\n\tstruct x86_legacy_features legacy;\n\tvoid (*set_legacy_features)(void);\n\tvoid (*realmode_reserve)(void);\n\tvoid (*realmode_init)(void);\n\tstruct x86_hyper_runtime hyper;\n\tstruct x86_guest guest;\n};\n\nstruct x86_pmu_quirk;\n\nstruct x86_pmu {\n\tconst char *name;\n\tint version;\n\tint (*handle_irq)(struct pt_regs *);\n\tvoid (*disable_all)(void);\n\tvoid (*enable_all)(int);\n\tvoid (*enable)(struct perf_event *);\n\tvoid (*disable)(struct perf_event *);\n\tvoid (*assign)(struct perf_event *, int);\n\tvoid (*add)(struct perf_event *);\n\tvoid (*del)(struct perf_event *);\n\tvoid (*read)(struct perf_event *);\n\tint (*set_period)(struct perf_event *);\n\tu64 (*update)(struct perf_event *);\n\tint (*hw_config)(struct perf_event *);\n\tint (*schedule_events)(struct cpu_hw_events *, int, int *);\n\tvoid (*late_setup)(void);\n\tvoid (*pebs_enable)(struct perf_event *);\n\tvoid (*pebs_disable)(struct perf_event *);\n\tvoid (*pebs_enable_all)(void);\n\tvoid (*pebs_disable_all)(void);\n\tunsigned int eventsel;\n\tunsigned int perfctr;\n\tunsigned int fixedctr;\n\tint (*addr_offset)(int, bool);\n\tint (*rdpmc_index)(int);\n\tu64 (*event_map)(int);\n\tint max_events;\n\tu64 config_mask;\n\tunion {\n\t\tu64 cntr_mask64;\n\t\tlong unsigned int cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 fixed_cntr_mask64;\n\t\tlong unsigned int fixed_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cntr_mask64;\n\t\tlong unsigned int acr_cntr_mask[1];\n\t};\n\tunion {\n\t\tu64 acr_cause_mask64;\n\t\tlong unsigned int acr_cause_mask[1];\n\t};\n\tint cntval_bits;\n\tu64 cntval_mask;\n\tunion {\n\t\tlong unsigned int events_maskl;\n\t\tlong unsigned int events_mask[1];\n\t};\n\tint events_mask_len;\n\tint apic;\n\tu64 max_period;\n\tstruct event_constraint * (*get_event_constraints)(struct cpu_hw_events *, int, struct perf_event *);\n\tvoid (*put_event_constraints)(struct cpu_hw_events *, struct perf_event *);\n\tvoid (*start_scheduling)(struct cpu_hw_events *);\n\tvoid (*commit_scheduling)(struct cpu_hw_events *, int, int);\n\tvoid (*stop_scheduling)(struct cpu_hw_events *);\n\tstruct event_constraint *event_constraints;\n\tstruct x86_pmu_quirk *quirks;\n\tvoid (*limit_period)(struct perf_event *, s64 *);\n\tunsigned int late_ack: 1;\n\tunsigned int mid_ack: 1;\n\tunsigned int enabled_ack: 1;\n\tint attr_rdpmc_broken;\n\tint attr_rdpmc;\n\tstruct attribute **format_attrs;\n\tssize_t (*events_sysfs_show)(char *, u64);\n\tconst struct attribute_group **attr_update;\n\tlong unsigned int attr_freeze_on_smi;\n\tint (*cpu_prepare)(int);\n\tvoid (*cpu_starting)(int);\n\tvoid (*cpu_dying)(int);\n\tvoid (*cpu_dead)(int);\n\tvoid (*check_microcode)(void);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tu64 intel_ctrl;\n\tunion perf_capabilities intel_cap;\n\tunsigned int bts: 1;\n\tunsigned int bts_active: 1;\n\tunsigned int ds_pebs: 1;\n\tunsigned int pebs_active: 1;\n\tunsigned int pebs_broken: 1;\n\tunsigned int pebs_prec_dist: 1;\n\tunsigned int pebs_no_tlb: 1;\n\tunsigned int pebs_no_isolation: 1;\n\tunsigned int pebs_block: 1;\n\tunsigned int pebs_ept: 1;\n\tunsigned int arch_pebs: 1;\n\tint pebs_record_size;\n\tint pebs_buffer_size;\n\tu64 pebs_events_mask;\n\tvoid (*drain_pebs)(struct pt_regs *, struct perf_sample_data *);\n\tstruct event_constraint *pebs_constraints;\n\tvoid (*pebs_aliases)(struct perf_event *);\n\tu64 (*pebs_latency_data)(struct perf_event *, u64);\n\tlong unsigned int large_pebs_flags;\n\tu64 rtm_abort_event;\n\tu64 pebs_capable;\n\tstruct arch_pebs_cap arch_pebs_cap;\n\tunsigned int lbr_tos;\n\tunsigned int lbr_from;\n\tunsigned int lbr_to;\n\tunsigned int lbr_info;\n\tunsigned int lbr_nr;\n\tunion {\n\t\tu64 lbr_sel_mask;\n\t\tu64 lbr_ctl_mask;\n\t};\n\tunion {\n\t\tconst int *lbr_sel_map;\n\t\tint *lbr_ctl_map;\n\t};\n\tu64 lbr_callstack_users;\n\tbool lbr_double_abort;\n\tbool lbr_pt_coexist;\n\tunsigned int lbr_has_info: 1;\n\tunsigned int lbr_has_tsx: 1;\n\tunsigned int lbr_from_flags: 1;\n\tunsigned int lbr_to_cycles: 1;\n\tunsigned int lbr_depth_mask: 8;\n\tunsigned int lbr_deep_c_reset: 1;\n\tunsigned int lbr_lip: 1;\n\tunsigned int lbr_cpl: 1;\n\tunsigned int lbr_filter: 1;\n\tunsigned int lbr_call_stack: 1;\n\tunsigned int lbr_mispred: 1;\n\tunsigned int lbr_timed_lbr: 1;\n\tunsigned int lbr_br_type: 1;\n\tunsigned int lbr_counters: 4;\n\tvoid (*lbr_reset)(void);\n\tvoid (*lbr_read)(struct cpu_hw_events *);\n\tvoid (*lbr_save)(void *);\n\tvoid (*lbr_restore)(void *);\n\tatomic_t lbr_exclusive[3];\n\tint num_topdown_events;\n\tunsigned int amd_nb_constraints: 1;\n\tu64 perf_ctr_pair_en;\n\tstruct extra_reg *extra_regs;\n\tunsigned int flags;\n\tstruct perf_guest_switch_msr * (*guest_get_msrs)(int *, void *);\n\tint (*check_period)(struct perf_event *, u64);\n\tint (*aux_output_match)(struct perf_event *);\n\tvoid (*filter)(struct pmu *, int, bool *);\n\tint num_hybrid_pmus;\n\tstruct x86_hybrid_pmu *hybrid_pmu;\n\tenum intel_cpu_type (*get_hybrid_cpu_type)(void);\n};\n\nstruct x86_pmu_capability {\n\tint version;\n\tint num_counters_gp;\n\tint num_counters_fixed;\n\tint bit_width_gp;\n\tint bit_width_fixed;\n\tunsigned int events_mask;\n\tint events_mask_len;\n\tunsigned int pebs_ept: 1;\n\tunsigned int mediated: 1;\n};\n\nunion x86_pmu_config {\n\tstruct {\n\t\tu64 event: 8;\n\t\tu64 umask: 8;\n\t\tu64 usr: 1;\n\t\tu64 os: 1;\n\t\tu64 edge: 1;\n\t\tu64 pc: 1;\n\t\tu64 interrupt: 1;\n\t\tu64 __reserved1: 1;\n\t\tu64 en: 1;\n\t\tu64 inv: 1;\n\t\tu64 cmask: 8;\n\t\tu64 event2: 4;\n\t\tu64 __reserved2: 4;\n\t\tu64 go: 1;\n\t\tu64 ho: 1;\n\t} bits;\n\tu64 value;\n};\n\nstruct x86_pmu_lbr {\n\tunsigned int nr;\n\tunsigned int from;\n\tunsigned int to;\n\tunsigned int info;\n\tbool has_callstack;\n};\n\nstruct x86_pmu_quirk {\n\tstruct x86_pmu_quirk *next;\n\tvoid (*func)(void);\n};\n\nstruct x86_topology_system {\n\tunsigned int dom_shifts[7];\n\tunsigned int dom_size[7];\n};\n\nstruct x86_xfeat_component {\n\t__u32 type;\n\t__u32 size;\n\t__u32 offset;\n\t__u32 flags;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[3];\n\t\tlong unsigned int marks[3];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xb1s_ff_report {\n\t__u8 report_id;\n\t__u8 enable;\n\t__u8 magnitude[4];\n\t__u8 duration_10ms;\n\t__u8 start_delay_10ms;\n\t__u8 loop_count;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n\tlong: 64;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 64;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n};\n\nstruct xdr_skb_reader {\n\tstruct sk_buff *skb;\n\tunsigned int offset;\n\tbool need_checksum;\n\tsize_t count;\n\t__wsum csum;\n};\n\nstruct xfrm4_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm4_protocol *next;\n\tint priority;\n};\n\nstruct xfrm6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tstruct xfrm6_protocol *next;\n\tint priority;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_aead_name {\n\tconst char *name;\n\tint icvbits;\n};\n\nstruct xfrm_usersa_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u16 family;\n\t__u8 proto;\n};\n\nstruct xfrm_aevent_id {\n\tstruct xfrm_usersa_id sa_id;\n\txfrm_address_t saddr;\n\t__u32 flags;\n\t__u32 reqid;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead_info {\n\tchar *geniv;\n\tu16 icv_truncbits;\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth_info {\n\tu16 icv_truncbits;\n\tu16 icv_fullbits;\n};\n\nstruct xfrm_algo_comp_info {\n\tu16 threshold;\n};\n\nstruct xfrm_algo_encr_info {\n\tchar *geniv;\n\tu16 blockbits;\n\tu16 defkeybits;\n};\n\nstruct xfrm_algo_desc {\n\tchar *name;\n\tchar *compat;\n\tu8 available: 1;\n\tu8 pfkey_supported: 1;\n\tunion {\n\t\tstruct xfrm_algo_aead_info aead;\n\t\tstruct xfrm_algo_auth_info auth;\n\t\tstruct xfrm_algo_encr_info encr;\n\t\tstruct xfrm_algo_comp_info comp;\n\t} uinfo;\n\tstruct sadb_alg desc;\n};\n\nstruct xfrm_algo_list {\n\tint (*find)(const char *, u32, u32);\n\tstruct xfrm_algo_desc *algs;\n\tint entries;\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_dst {\n\tunion {\n\t\tstruct dst_entry dst;\n\t\tstruct rtable rt;\n\t\tstruct rt6_info rt6;\n\t} u;\n\tstruct dst_entry *route;\n\tstruct dst_entry *child;\n\tstruct dst_entry *path;\n\tstruct xfrm_policy *pols[2];\n\tint num_pols;\n\tint num_xfrms;\n\tu32 xfrm_genid;\n\tu32 policy_genid;\n\tu32 route_mtu_cached;\n\tu32 child_mtu_cached;\n\tu32 route_cookie;\n\tu32 path_cookie;\n};\n\nstruct xfrm_dst_lookup_params {\n\tstruct net *net;\n\tdscp_t dscp;\n\tint oif;\n\txfrm_address_t *saddr;\n\txfrm_address_t *daddr;\n\tu32 mark;\n\t__u8 ipproto;\n\tunion flowi_uli uli;\n};\n\nstruct xfrm_dump_info {\n\tstruct sk_buff *in_skb;\n\tstruct sk_buff *out_skb;\n\tu32 nlmsg_seq;\n\tu16 nlmsg_flags;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_flo {\n\tstruct dst_entry *dst_orig;\n\tu8 flags;\n};\n\nstruct xfrm_flow_keys {\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_control control;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t} addrs;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_keyid gre;\n};\n\nstruct xfrm_hash_state_ptrs {\n\tconst struct hlist_head *bydst;\n\tconst struct hlist_head *bysrc;\n\tconst struct hlist_head *byspi;\n\tunsigned int hmask;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_if_decode_session_result;\n\nstruct xfrm_if_cb {\n\tbool (*decode_session)(struct sk_buff *, short unsigned int, struct xfrm_if_decode_session_result *);\n};\n\nstruct xfrm_if_decode_session_result {\n\tstruct net *net;\n\tu32 if_id;\n};\n\nstruct xfrm_input_afinfo {\n\tu8 family;\n\tbool is_ipip;\n\tint (*callback)(struct sk_buff *, u8, int);\n};\n\nstruct xfrm_kmaddress {\n\txfrm_address_t local;\n\txfrm_address_t remote;\n\tu32 reserved;\n\tu16 family;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_link {\n\tint (*doit)(struct sk_buff *, struct nlmsghdr *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *nla_pol;\n\tint nla_max;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_tmpl;\n\nstruct xfrm_selector;\n\nstruct xfrm_migrate;\n\nstruct xfrm_mgr {\n\tstruct list_head list;\n\tint (*notify)(struct xfrm_state *, const struct km_event *);\n\tint (*acquire)(struct xfrm_state *, struct xfrm_tmpl *, struct xfrm_policy *);\n\tstruct xfrm_policy * (*compile_policy)(struct sock *, int, u8 *, int, int *);\n\tint (*new_mapping)(struct xfrm_state *, xfrm_address_t *, __be16);\n\tint (*notify_policy)(struct xfrm_policy *, int, const struct km_event *);\n\tint (*report)(struct net *, u8, struct xfrm_selector *, xfrm_address_t *);\n\tint (*migrate)(const struct xfrm_selector *, u8, u8, const struct xfrm_migrate *, int, const struct xfrm_kmaddress *, const struct xfrm_encap_tmpl *);\n\tbool (*is_alive)(const struct km_event *);\n};\n\nstruct xfrm_migrate {\n\txfrm_address_t old_daddr;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_daddr;\n\txfrm_address_t new_saddr;\n\tu8 proto;\n\tu8 mode;\n\tu16 reserved;\n\tu32 reqid;\n\tu16 old_family;\n\tu16 new_family;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_mode_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\t__be16 id;\n\t__be16 frag_off;\n\tu8 ihl;\n\tu8 tos;\n\tu8 ttl;\n\tu8 protocol;\n\tu8 optlen;\n\tu8 flow_lbl[3];\n};\n\nstruct xfrm_pol_inexact_key {\n\tpossible_net_t net;\n\tu32 if_id;\n\tu16 family;\n\tu8 dir;\n\tu8 type;\n};\n\nstruct xfrm_pol_inexact_bin {\n\tstruct xfrm_pol_inexact_key k;\n\tstruct rhash_head head;\n\tstruct hlist_head hhead;\n\tseqcount_spinlock_t count;\n\tstruct rb_root root_d;\n\tstruct rb_root root_s;\n\tstruct list_head inexact_bins;\n\tstruct callback_head rcu;\n};\n\nstruct xfrm_pol_inexact_candidates {\n\tstruct hlist_head *res[4];\n};\n\nstruct xfrm_pol_inexact_node {\n\tstruct rb_node node;\n\tunion {\n\t\txfrm_address_t addr;\n\t\tstruct callback_head rcu;\n\t};\n\tu8 prefixlen;\n\tstruct rb_root root;\n\tstruct hlist_head hhead;\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_policy_walk_entry {\n\tstruct list_head all;\n\tu8 dead;\n};\n\nstruct xfrm_policy_queue {\n\tstruct sk_buff_head hold_queue;\n\tstruct timer_list hold_timer;\n\tlong unsigned int timeout;\n};\n\nstruct xfrm_tmpl {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tshort unsigned int encap_family;\n\tu32 reqid;\n\tu8 mode;\n\tu8 share;\n\tu8 optional;\n\tu8 allalgs;\n\tu32 aalgos;\n\tu32 ealgos;\n\tu32 calgos;\n};\n\nstruct xfrm_sec_ctx;\n\nstruct xfrm_policy {\n\tpossible_net_t xp_net;\n\tstruct hlist_node bydst;\n\tstruct hlist_node byidx;\n\tstruct hlist_head state_cache_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tu32 pos;\n\tstruct timer_list timer;\n\tatomic_t genid;\n\tu32 priority;\n\tu32 index;\n\tu32 if_id;\n\tstruct xfrm_mark mark;\n\tstruct xfrm_selector selector;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_policy_walk_entry walk;\n\tstruct xfrm_policy_queue polq;\n\tbool bydst_reinsert;\n\tu8 type;\n\tu8 action;\n\tu8 flags;\n\tu8 xfrm_nr;\n\tu16 family;\n\tstruct xfrm_sec_ctx *security;\n\tstruct xfrm_tmpl xfrm_vec[6];\n\tstruct callback_head rcu;\n\tstruct xfrm_dev_offload xdo;\n};\n\nstruct xfrm_policy_afinfo {\n\tstruct dst_ops *dst_ops;\n\tstruct dst_entry * (*dst_lookup)(const struct xfrm_dst_lookup_params *);\n\tint (*get_saddr)(xfrm_address_t *, const struct xfrm_dst_lookup_params *);\n\tint (*fill_dst)(struct xfrm_dst *, struct net_device *, const struct flowi *);\n\tstruct dst_entry * (*blackhole_route)(struct net *, struct dst_entry *);\n};\n\nstruct xfrm_policy_walk {\n\tstruct xfrm_policy_walk_entry walk;\n\tu8 type;\n\tu32 seq;\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_spi_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunsigned int daddroff;\n\tunsigned int family;\n\t__be32 seq;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_state_afinfo {\n\tu8 family;\n\tu8 proto;\n\tconst struct xfrm_type_offload *type_offload_esp;\n\tconst struct xfrm_type *type_esp;\n\tconst struct xfrm_type *type_ipip;\n\tconst struct xfrm_type *type_ipip6;\n\tconst struct xfrm_type *type_comp;\n\tconst struct xfrm_type *type_ah;\n\tconst struct xfrm_type *type_routing;\n\tconst struct xfrm_type *type_dstopts;\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*transport_finish)(struct sk_buff *, int);\n\tvoid (*local_error)(struct sk_buff *, u32);\n};\n\nstruct xfrm_trans_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tint (*finish)(struct net *, struct sock *, struct sk_buff *);\n\tstruct net *net;\n};\n\nstruct xfrm_trans_tasklet {\n\tstruct work_struct work;\n\tspinlock_t queue_lock;\n\tstruct sk_buff_head queue;\n};\n\nstruct xfrm_translator {\n\tint (*alloc_compat)(struct sk_buff *, const struct nlmsghdr *);\n\tstruct nlmsghdr * (*rcv_msg_compat)(const struct nlmsghdr *, int, const struct nla_policy *, struct netlink_ext_ack *);\n\tint (*xlate_user_policy_sockptr)(u8 **, int);\n\tstruct module *owner;\n};\n\nstruct xfrm_tunnel {\n\tint (*handler)(struct sk_buff *);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm_tunnel *next;\n\tint priority;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xfrm_userpolicy_info {\n\tstruct xfrm_selector sel;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\t__u32 priority;\n\t__u32 index;\n\t__u8 dir;\n\t__u8 action;\n\t__u8 flags;\n\t__u8 share;\n};\n\nstruct xfrm_user_acquire {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_userpolicy_info policy;\n\t__u32 aalgos;\n\t__u32 ealgos;\n\t__u32 calgos;\n\t__u32 seq;\n};\n\nstruct xfrm_usersa_info {\n\tstruct xfrm_selector sel;\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_stats stats;\n\t__u32 seq;\n\t__u32 reqid;\n\t__u16 family;\n\t__u8 mode;\n\t__u8 replay_window;\n\t__u8 flags;\n};\n\nstruct xfrm_user_expire {\n\tstruct xfrm_usersa_info state;\n\t__u8 hard;\n};\n\nstruct xfrm_user_mapping {\n\tstruct xfrm_usersa_id id;\n\t__u32 reqid;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_saddr;\n\t__be16 old_sport;\n\t__be16 new_sport;\n};\n\nstruct xfrm_user_offload {\n\tint ifindex;\n\t__u8 flags;\n};\n\nstruct xfrm_user_polexpire {\n\tstruct xfrm_userpolicy_info pol;\n\t__u8 hard;\n};\n\nstruct xfrm_user_report {\n\t__u8 proto;\n\tstruct xfrm_selector sel;\n};\n\nstruct xfrm_user_sec_ctx {\n\t__u16 len;\n\t__u16 exttype;\n\t__u8 ctx_alg;\n\t__u8 ctx_doi;\n\t__u16 ctx_len;\n};\n\nstruct xfrm_user_tmpl {\n\tstruct xfrm_id id;\n\t__u16 family;\n\txfrm_address_t saddr;\n\t__u32 reqid;\n\t__u8 mode;\n\t__u8 share;\n\t__u8 optional;\n\t__u32 aalgos;\n\t__u32 ealgos;\n\t__u32 calgos;\n};\n\nstruct xfrm_userpolicy_default {\n\t__u8 in;\n\t__u8 fwd;\n\t__u8 out;\n};\n\nstruct xfrm_userpolicy_id {\n\tstruct xfrm_selector sel;\n\t__u32 index;\n\t__u8 dir;\n};\n\nstruct xfrm_userpolicy_type {\n\t__u8 type;\n\t__u16 reserved1;\n\t__u8 reserved2;\n};\n\nstruct xfrm_usersa_flush {\n\t__u8 proto;\n};\n\nstruct xfrm_userspi_info {\n\tstruct xfrm_usersa_info info;\n\t__u32 min;\n\t__u32 max;\n};\n\nstruct xfrmk_sadinfo {\n\tu32 sadhcnt;\n\tu32 sadhmcnt;\n\tu32 sadcnt;\n};\n\nstruct xfrmk_spdinfo {\n\tu32 incnt;\n\tu32 outcnt;\n\tu32 fwdcnt;\n\tu32 inscnt;\n\tu32 outscnt;\n\tu32 fwdscnt;\n\tu32 spdhcnt;\n\tu32 spdhmcnt;\n};\n\nstruct xfrmu_sadhinfo {\n\t__u32 sadhcnt;\n\t__u32 sadhmcnt;\n};\n\nstruct xfrmu_spdhinfo {\n\t__u32 spdhcnt;\n\t__u32 spdhmcnt;\n};\n\nstruct xfrmu_spdhthresh {\n\t__u8 lbits;\n\t__u8 rbits;\n};\n\nstruct xfrmu_spdinfo {\n\t__u32 incnt;\n\t__u32 outcnt;\n\t__u32 fwdcnt;\n\t__u32 inscnt;\n\t__u32 outscnt;\n\t__u32 fwdscnt;\n};\n\nstruct xhci_bus_state {\n\tlong unsigned int bus_suspended;\n\tlong unsigned int next_statechange;\n\tu32 port_c_suspend;\n\tu32 suspended_ports;\n\tu32 port_remote_wakeup;\n\tlong unsigned int resuming_ports;\n};\n\nstruct xhci_bw_info {\n\tunsigned int ep_interval;\n\tunsigned int mult;\n\tunsigned int num_packets;\n\tunsigned int max_packet_size;\n\tunsigned int max_esit_payload;\n\tunsigned int type;\n};\n\nstruct xhci_cap_regs {\n\t__le32 hc_capbase;\n\t__le32 hcs_params1;\n\t__le32 hcs_params2;\n\t__le32 hcs_params3;\n\t__le32 hcc_params;\n\t__le32 db_off;\n\t__le32 run_regs_off;\n\t__le32 hcc_params2;\n};\n\nstruct xhci_container_ctx;\n\nstruct xhci_command {\n\tstruct xhci_container_ctx *in_ctx;\n\tu32 status;\n\tu32 comp_param;\n\tint slot_id;\n\tstruct completion *completion;\n\tunion xhci_trb *command_trb;\n\tstruct list_head cmd_list;\n\tunsigned int timeout_ms;\n};\n\nstruct xhci_container_ctx {\n\tunsigned int type;\n\tint size;\n\tu8 *bytes;\n\tdma_addr_t dma;\n};\n\nstruct xhci_erst_entry;\n\nstruct xhci_erst {\n\tstruct xhci_erst_entry *entries;\n\tunsigned int num_entries;\n\tdma_addr_t erst_dma_addr;\n};\n\nstruct xhci_hcd;\n\nstruct xhci_dbc {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tstruct xhci_hcd *xhci;\n\tstruct dbc_regs *regs;\n\tstruct xhci_ring *ring_evt;\n\tstruct xhci_ring *ring_in;\n\tstruct xhci_ring *ring_out;\n\tstruct xhci_erst erst;\n\tstruct xhci_container_ctx *ctx;\n\tstruct dbc_str_descs *str_descs;\n\tdma_addr_t str_descs_dma;\n\tsize_t str_descs_size;\n\tstruct dbc_str str;\n\tu16 idVendor;\n\tu16 idProduct;\n\tu16 bcdDevice;\n\tu8 bInterfaceProtocol;\n\tenum dbc_state state;\n\tstruct delayed_work event_work;\n\tunsigned int poll_interval;\n\tlong unsigned int xfer_timestamp;\n\tunsigned int resume_required: 1;\n\tstruct dbc_ep eps[2];\n\tconst struct dbc_driver *driver;\n\tvoid *priv;\n};\n\nstruct xhci_device_context_array {\n\t__le64 dev_context_ptrs[256];\n\tdma_addr_t dma;\n};\n\nstruct xhci_doorbell_array {\n\t__le32 doorbell[256];\n};\n\nstruct xhci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n};\n\nstruct xhci_ep_ctx {\n\t__le32 ep_info;\n\t__le32 ep_info2;\n\t__le64 deq;\n\t__le32 tx_info;\n\t__le32 reserved[3];\n};\n\nstruct xhci_stream_info;\n\nstruct xhci_ep_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *show_ring;\n\tunsigned int stream_id;\n};\n\nstruct xhci_erst_entry {\n\t__le64 seg_addr;\n\t__le32 seg_size;\n\t__le32 rsvd;\n};\n\nstruct xhci_event_cmd {\n\t__le64 cmd_trb;\n\t__le32 status;\n\t__le32 flags;\n};\n\nstruct xhci_file_map {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct xhci_generic_trb {\n\t__le32 field[4];\n};\n\nstruct xhci_port;\n\nstruct xhci_hub {\n\tstruct xhci_port **ports;\n\tunsigned int num_ports;\n\tstruct usb_hcd *hcd;\n\tstruct xhci_bus_state bus_state;\n\tu8 maj_rev;\n\tu8 min_rev;\n};\n\nstruct xhci_op_regs;\n\nstruct xhci_run_regs;\n\nstruct xhci_interrupter;\n\nstruct xhci_scratchpad;\n\nstruct xhci_virt_device;\n\nstruct xhci_root_port_bw_info;\n\nstruct xhci_port_cap;\n\nstruct xhci_hcd {\n\tstruct usb_hcd *main_hcd;\n\tstruct usb_hcd *shared_hcd;\n\tstruct xhci_cap_regs *cap_regs;\n\tstruct xhci_op_regs *op_regs;\n\tstruct xhci_run_regs *run_regs;\n\tstruct xhci_doorbell_array *dba;\n\t__u32 hcs_params2;\n\t__u32 hcs_params3;\n\t__u32 hcc_params;\n\t__u32 hcc_params2;\n\tspinlock_t lock;\n\tu16 hci_version;\n\tu16 max_interrupters;\n\tu8 max_slots;\n\tu8 max_ports;\n\tu32 imod_interval;\n\tu32 page_size;\n\tint nvecs;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\tstruct reset_control *reset;\n\tstruct xhci_device_context_array *dcbaa;\n\tstruct xhci_interrupter **interrupters;\n\tstruct xhci_ring *cmd_ring;\n\tunsigned int cmd_ring_state;\n\tstruct list_head cmd_list;\n\tunsigned int cmd_ring_reserved_trbs;\n\tstruct delayed_work cmd_timer;\n\tstruct completion cmd_ring_stop_completion;\n\tstruct xhci_command *current_cmd;\n\tstruct xhci_scratchpad *scratchpad;\n\tstruct mutex mutex;\n\tstruct xhci_virt_device *devs[256];\n\tstruct xhci_root_port_bw_info *rh_bw;\n\tstruct dma_pool *device_pool;\n\tstruct dma_pool *segment_pool;\n\tstruct dma_pool *small_streams_pool;\n\tstruct dma_pool *port_bw_pool;\n\tstruct dma_pool *medium_streams_pool;\n\tunsigned int xhc_state;\n\tlong unsigned int run_graceperiod;\n\tstruct s3_save s3;\n\tlong long unsigned int quirks;\n\tunsigned int num_active_eps;\n\tunsigned int limit_active_eps;\n\tstruct xhci_port *hw_ports;\n\tstruct xhci_hub usb2_rhub;\n\tstruct xhci_hub usb3_rhub;\n\tunsigned int hw_lpm_support: 1;\n\tunsigned int broken_suspend: 1;\n\tunsigned int allow_single_roothub: 1;\n\tstruct xhci_port_cap *port_caps;\n\tunsigned int num_port_caps;\n\tstruct timer_list comp_mode_recovery_timer;\n\tu32 port_status_u0;\n\tu16 test_mode;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_slots;\n\tstruct list_head regset_list;\n\tvoid *dbc;\n\tlong unsigned int priv[0];\n};\n\nstruct xhci_input_control_ctx {\n\t__le32 drop_flags;\n\t__le32 add_flags;\n\t__le32 rsvd2[6];\n};\n\nstruct xhci_intr_reg;\n\nstruct xhci_interrupter {\n\tstruct xhci_ring *event_ring;\n\tstruct xhci_erst erst;\n\tstruct xhci_intr_reg *ir_set;\n\tunsigned int intr_num;\n\tbool ip_autoclear;\n\tu32 isoc_bei_interval;\n\tu32 s3_iman;\n\tu32 s3_imod;\n\tu32 s3_erst_size;\n\tu64 s3_erst_base;\n\tu64 s3_erst_dequeue;\n};\n\nstruct xhci_interval_bw {\n\tunsigned int num_packets;\n\tstruct list_head endpoints;\n\tunsigned int overhead[3];\n};\n\nstruct xhci_interval_bw_table {\n\tunsigned int interval0_esit_payload;\n\tstruct xhci_interval_bw interval_bw[16];\n\tunsigned int bw_used;\n\tunsigned int ss_bw_in;\n\tunsigned int ss_bw_out;\n};\n\nstruct xhci_intr_reg {\n\t__le32 iman;\n\t__le32 imod;\n\t__le32 erst_size;\n\t__le32 rsvd;\n\t__le64 erst_base;\n\t__le64 erst_dequeue;\n};\n\nstruct xhci_link_trb {\n\t__le64 segment_ptr;\n\t__le32 intr_target;\n\t__le32 control;\n};\n\nstruct xhci_port_regs {\n\t__le32 portsc;\n\t__le32 portpmsc;\n\t__le32 portli;\n\t__le32 porthlmpc;\n};\n\nstruct xhci_op_regs {\n\t__le32 command;\n\t__le32 status;\n\t__le32 page_size;\n\t__le32 reserved1;\n\t__le32 reserved2;\n\t__le32 dev_notification;\n\t__le64 cmd_ring;\n\t__le32 reserved3[4];\n\t__le64 dcbaa_ptr;\n\t__le32 config_reg;\n\t__le32 reserved4[241];\n\tstruct xhci_port_regs port_regs[0];\n};\n\nstruct xhci_port {\n\tstruct xhci_port_regs *port_reg;\n\tint hw_portnum;\n\tint hcd_portnum;\n\tstruct xhci_hub *rhub;\n\tstruct xhci_port_cap *port_cap;\n\tunsigned int lpm_incapable: 1;\n\tlong unsigned int resume_timestamp;\n\tbool rexit_active;\n\tint slot_id;\n\tstruct completion rexit_done;\n\tstruct completion u3exit_done;\n};\n\nstruct xhci_port_cap {\n\tu32 *psi;\n\tu8 psi_count;\n\tu8 psi_uid_count;\n\tu8 maj_rev;\n\tu8 min_rev;\n\tu32 protocol_caps;\n};\n\nstruct xhci_regset {\n\tchar name[32];\n\tstruct debugfs_regset32 regset;\n\tsize_t nregs;\n\tstruct list_head list;\n};\n\nstruct xhci_ring {\n\tstruct xhci_segment *first_seg;\n\tstruct xhci_segment *last_seg;\n\tunion xhci_trb *enqueue;\n\tstruct xhci_segment *enq_seg;\n\tunion xhci_trb *dequeue;\n\tstruct xhci_segment *deq_seg;\n\tstruct list_head td_list;\n\tu32 cycle_state;\n\tunsigned int stream_id;\n\tunsigned int num_segs;\n\tunsigned int num_trbs_free;\n\tunsigned int bounce_buf_len;\n\tenum xhci_ring_type type;\n\tu32 old_trb_comp_code;\n\tstruct xarray *trb_address_map;\n};\n\nstruct xhci_root_port_bw_info {\n\tstruct list_head tts;\n\tunsigned int num_active_tts;\n\tstruct xhci_interval_bw_table bw_table;\n};\n\nstruct xhci_run_regs {\n\t__le32 microframe_index;\n\t__le32 rsvd[7];\n\tstruct xhci_intr_reg ir_set[1024];\n};\n\nstruct xhci_scratchpad {\n\tu64 *sp_array;\n\tdma_addr_t sp_dma;\n\tvoid **sp_buffers;\n};\n\nstruct xhci_segment {\n\tunion xhci_trb *trbs;\n\tstruct xhci_segment *next;\n\tunsigned int num;\n\tdma_addr_t dma;\n\tdma_addr_t bounce_dma;\n\tvoid *bounce_buf;\n\tunsigned int bounce_offs;\n\tunsigned int bounce_len;\n};\n\nstruct xhci_virt_ep;\n\nstruct xhci_sideband_event;\n\nstruct xhci_sideband {\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_virt_device *vdev;\n\tstruct xhci_virt_ep *eps[31];\n\tstruct xhci_interrupter *ir;\n\tenum xhci_sideband_type type;\n\tstruct mutex mutex;\n\tstruct usb_interface *intf;\n\tint (*notify_client)(struct usb_interface *, struct xhci_sideband_event *);\n};\n\nstruct xhci_sideband_event {\n\tenum xhci_sideband_notify_type type;\n\tvoid *evt_data;\n};\n\nstruct xhci_slot_ctx {\n\t__le32 dev_info;\n\t__le32 dev_info2;\n\t__le32 tt_info;\n\t__le32 dev_state;\n\t__le32 reserved[4];\n};\n\nstruct xhci_slot_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_ep_priv *eps[31];\n\tstruct xhci_virt_device *dev;\n};\n\nstruct xhci_stream_ctx {\n\t__le64 stream_ring;\n\t__le32 reserved[2];\n};\n\nstruct xhci_stream_info {\n\tstruct xhci_ring **stream_rings;\n\tunsigned int num_streams;\n\tstruct xhci_stream_ctx *stream_ctx_array;\n\tunsigned int num_stream_ctxs;\n\tdma_addr_t ctx_array_dma;\n\tstruct xarray trb_address_map;\n\tstruct xhci_command *free_streams_command;\n};\n\nstruct xhci_transfer_event {\n\t__le64 buffer;\n\t__le32 transfer_len;\n\t__le32 flags;\n};\n\nunion xhci_trb {\n\tstruct xhci_link_trb link;\n\tstruct xhci_transfer_event trans_event;\n\tstruct xhci_event_cmd event_cmd;\n\tstruct xhci_generic_trb generic;\n};\n\nstruct xhci_tt_bw_info {\n\tstruct list_head tt_list;\n\tint slot_id;\n\tint ttport;\n\tstruct xhci_interval_bw_table bw_table;\n\tint active_eps;\n};\n\nstruct xhci_virt_ep {\n\tstruct xhci_virt_device *vdev;\n\tunsigned int ep_index;\n\tstruct xhci_ring *ring;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *new_ring;\n\tunsigned int err_count;\n\tunsigned int ep_state;\n\tstruct list_head cancelled_td_list;\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_segment *queued_deq_seg;\n\tunion xhci_trb *queued_deq_ptr;\n\tbool skip;\n\tstruct xhci_bw_info bw_info;\n\tstruct list_head bw_endpoint_list;\n\tlong unsigned int stop_time;\n\tint next_frame_id;\n\tbool use_extended_tbc;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xhci_virt_device {\n\tint slot_id;\n\tstruct usb_device *udev;\n\tstruct xhci_container_ctx *out_ctx;\n\tstruct xhci_container_ctx *in_ctx;\n\tstruct xhci_virt_ep eps[31];\n\tstruct xhci_port *rhub_port;\n\tstruct xhci_interval_bw_table *bw_table;\n\tstruct xhci_tt_bw_info *tt_info;\n\tlong unsigned int flags;\n\tu16 current_mel;\n\tvoid *debugfs_private;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tlong unsigned int *bitmap;\n\tstruct page *page;\n\tlong unsigned int vaddr;\n};\n\nstruct xprt_addr {\n\tconst char *addr;\n\tstruct callback_head rcu;\n};\n\nstruct xprt_create;\n\nstruct xprt_class {\n\tstruct list_head list;\n\tint ident;\n\tstruct rpc_xprt * (*setup)(struct xprt_create *);\n\tstruct module *owner;\n\tchar name[32];\n\tconst char *netid[0];\n};\n\nstruct xprt_create {\n\tint ident;\n\tstruct net *net;\n\tstruct sockaddr *srcaddr;\n\tstruct sockaddr *dstaddr;\n\tsize_t addrlen;\n\tconst char *servername;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rpc_xprt_switch *bc_xps;\n\tunsigned int flags;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xt_match;\n\nstruct xt_target;\n\nstruct xt_action_param {\n\tunion {\n\t\tconst struct xt_match *match;\n\t\tconst struct xt_target *target;\n\t};\n\tunion {\n\t\tconst void *matchinfo;\n\t\tconst void *targinfo;\n\t};\n\tconst struct nf_hook_state *state;\n\tunsigned int thoff;\n\tu16 fragoff;\n\tbool hotdrop;\n};\n\nstruct xt_af {\n\tstruct mutex mutex;\n\tstruct list_head match;\n\tstruct list_head target;\n};\n\nstruct xt_connsecmark_target_info {\n\t__u8 mode;\n};\n\nstruct xt_conntrack_mtinfo1 {\n\tunion nf_inet_addr origsrc_addr;\n\tunion nf_inet_addr origsrc_mask;\n\tunion nf_inet_addr origdst_addr;\n\tunion nf_inet_addr origdst_mask;\n\tunion nf_inet_addr replsrc_addr;\n\tunion nf_inet_addr replsrc_mask;\n\tunion nf_inet_addr repldst_addr;\n\tunion nf_inet_addr repldst_mask;\n\t__u32 expires_min;\n\t__u32 expires_max;\n\t__u16 l4proto;\n\t__be16 origsrc_port;\n\t__be16 origdst_port;\n\t__be16 replsrc_port;\n\t__be16 repldst_port;\n\t__u16 match_flags;\n\t__u16 invert_flags;\n\t__u8 state_mask;\n\t__u8 status_mask;\n};\n\nstruct xt_conntrack_mtinfo2 {\n\tunion nf_inet_addr origsrc_addr;\n\tunion nf_inet_addr origsrc_mask;\n\tunion nf_inet_addr origdst_addr;\n\tunion nf_inet_addr origdst_mask;\n\tunion nf_inet_addr replsrc_addr;\n\tunion nf_inet_addr replsrc_mask;\n\tunion nf_inet_addr repldst_addr;\n\tunion nf_inet_addr repldst_mask;\n\t__u32 expires_min;\n\t__u32 expires_max;\n\t__u16 l4proto;\n\t__be16 origsrc_port;\n\t__be16 origdst_port;\n\t__be16 replsrc_port;\n\t__be16 repldst_port;\n\t__u16 match_flags;\n\t__u16 invert_flags;\n\t__u16 state_mask;\n\t__u16 status_mask;\n};\n\nstruct xt_conntrack_mtinfo3 {\n\tunion nf_inet_addr origsrc_addr;\n\tunion nf_inet_addr origsrc_mask;\n\tunion nf_inet_addr origdst_addr;\n\tunion nf_inet_addr origdst_mask;\n\tunion nf_inet_addr replsrc_addr;\n\tunion nf_inet_addr replsrc_mask;\n\tunion nf_inet_addr repldst_addr;\n\tunion nf_inet_addr repldst_mask;\n\t__u32 expires_min;\n\t__u32 expires_max;\n\t__u16 l4proto;\n\t__u16 origsrc_port;\n\t__u16 origdst_port;\n\t__u16 replsrc_port;\n\t__u16 repldst_port;\n\t__u16 match_flags;\n\t__u16 invert_flags;\n\t__u16 state_mask;\n\t__u16 status_mask;\n\t__u16 origsrc_port_high;\n\t__u16 origdst_port_high;\n\t__u16 replsrc_port_high;\n\t__u16 repldst_port_high;\n};\n\nstruct xt_counters_info {\n\tchar name[32];\n\tunsigned int num_counters;\n\tstruct xt_counters counters[0];\n};\n\nstruct xt_entry_match {\n\tunion {\n\t\tstruct {\n\t\t\t__u16 match_size;\n\t\t\tchar name[29];\n\t\t\t__u8 revision;\n\t\t} user;\n\t\tstruct {\n\t\t\t__u16 match_size;\n\t\t\tstruct xt_match *match;\n\t\t} kernel;\n\t\t__u16 match_size;\n\t} u;\n\tunsigned char data[0];\n};\n\nstruct xt_entry_target {\n\tunion {\n\t\tstruct {\n\t\t\t__u16 target_size;\n\t\t\tchar name[29];\n\t\t\t__u8 revision;\n\t\t} user;\n\t\tstruct {\n\t\t\t__u16 target_size;\n\t\t\tstruct xt_target *target;\n\t\t} kernel;\n\t\t__u16 target_size;\n\t} u;\n\tunsigned char data[0];\n};\n\nstruct xt_error_target {\n\tstruct xt_entry_target target;\n\tchar errorname[30];\n};\n\nstruct xt_mtchk_param;\n\nstruct xt_mtdtor_param;\n\nstruct xt_match {\n\tstruct list_head list;\n\tconst char name[29];\n\tu_int8_t revision;\n\tbool (*match)(const struct sk_buff *, struct xt_action_param *);\n\tint (*checkentry)(const struct xt_mtchk_param *);\n\tvoid (*destroy)(const struct xt_mtdtor_param *);\n\tstruct module *me;\n\tconst char *table;\n\tunsigned int matchsize;\n\tunsigned int usersize;\n\tunsigned int hooks;\n\tshort unsigned int proto;\n\tshort unsigned int family;\n};\n\nstruct xt_mtchk_param {\n\tstruct net *net;\n\tconst char *table;\n\tconst void *entryinfo;\n\tconst struct xt_match *match;\n\tvoid *matchinfo;\n\tunsigned int hook_mask;\n\tu_int8_t family;\n\tbool nft_compat;\n};\n\nstruct xt_mtdtor_param {\n\tstruct net *net;\n\tconst struct xt_match *match;\n\tvoid *matchinfo;\n\tu_int8_t family;\n};\n\nstruct xt_nflog_info {\n\t__u32 len;\n\t__u16 group;\n\t__u16 threshold;\n\t__u16 flags;\n\t__u16 pad;\n\tchar prefix[64];\n};\n\nstruct xt_pernet {\n\tstruct list_head tables[11];\n};\n\nstruct xt_policy_spec {\n\t__u8 saddr: 1;\n\t__u8 daddr: 1;\n\t__u8 proto: 1;\n\t__u8 mode: 1;\n\t__u8 spi: 1;\n\t__u8 reqid: 1;\n};\n\nstruct xt_policy_elem {\n\tunion {\n\t\tstruct {\n\t\t\tunion nf_inet_addr saddr;\n\t\t\tunion nf_inet_addr smask;\n\t\t\tunion nf_inet_addr daddr;\n\t\t\tunion nf_inet_addr dmask;\n\t\t};\n\t};\n\t__be32 spi;\n\t__u32 reqid;\n\t__u8 proto;\n\t__u8 mode;\n\tstruct xt_policy_spec match;\n\tstruct xt_policy_spec invert;\n};\n\nstruct xt_policy_info {\n\tstruct xt_policy_elem pol[4];\n\t__u16 flags;\n\t__u16 len;\n};\n\nstruct xt_secmark_target_info {\n\t__u8 mode;\n\t__u32 secid;\n\tchar secctx[256];\n};\n\nstruct xt_secmark_target_info_v1 {\n\t__u8 mode;\n\tchar secctx[256];\n\t__u32 secid;\n};\n\nstruct xt_standard_target {\n\tstruct xt_entry_target target;\n\tint verdict;\n};\n\nstruct xt_state_info {\n\tunsigned int statemask;\n};\n\nstruct xt_table_info;\n\nstruct xt_table {\n\tstruct list_head list;\n\tunsigned int valid_hooks;\n\tstruct xt_table_info *private;\n\tstruct nf_hook_ops *ops;\n\tstruct module *me;\n\tu_int8_t af;\n\tint priority;\n\tconst char name[32];\n};\n\nstruct xt_table_info {\n\tunsigned int size;\n\tunsigned int number;\n\tunsigned int initial_entries;\n\tunsigned int hook_entry[5];\n\tunsigned int underflow[5];\n\tunsigned int stacksize;\n\tvoid ***jumpstack;\n\tunsigned char entries[0];\n};\n\nstruct xt_tgchk_param;\n\nstruct xt_tgdtor_param;\n\nstruct xt_target {\n\tstruct list_head list;\n\tconst char name[29];\n\tu_int8_t revision;\n\tunsigned int (*target)(struct sk_buff *, const struct xt_action_param *);\n\tint (*checkentry)(const struct xt_tgchk_param *);\n\tvoid (*destroy)(const struct xt_tgdtor_param *);\n\tstruct module *me;\n\tconst char *table;\n\tunsigned int targetsize;\n\tunsigned int usersize;\n\tunsigned int hooks;\n\tshort unsigned int proto;\n\tshort unsigned int family;\n};\n\nstruct xt_tcp {\n\t__u16 spts[2];\n\t__u16 dpts[2];\n\t__u8 option;\n\t__u8 flg_mask;\n\t__u8 flg_cmp;\n\t__u8 invflags;\n};\n\nstruct xt_tcpmss_info {\n\t__u16 mss;\n};\n\nstruct xt_template {\n\tstruct list_head list;\n\tint (*table_init)(struct net *);\n\tstruct module *me;\n\tchar name[32];\n};\n\nstruct xt_tgchk_param {\n\tstruct net *net;\n\tconst char *table;\n\tconst void *entryinfo;\n\tconst struct xt_target *target;\n\tvoid *targinfo;\n\tunsigned int hook_mask;\n\tu_int8_t family;\n\tbool nft_compat;\n};\n\nstruct xt_tgdtor_param {\n\tstruct net *net;\n\tconst struct xt_target *target;\n\tvoid *targinfo;\n\tu_int8_t family;\n};\n\nstruct xt_udp {\n\t__u16 spts[2];\n\t__u16 dpts[2];\n\t__u8 invflags;\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct yenta_socket {\n\tstruct pci_dev *dev;\n\tint cb_irq;\n\tint io_irq;\n\tvoid *base;\n\tstruct timer_list poll_timer;\n\tstruct pcmcia_socket socket;\n\tstruct cardbus_type *type;\n\tu32 flags;\n\tunsigned int probe_status;\n\tunsigned int private[8];\n\tu32 saved_state[2];\n};\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\nunion zen_patch_rev {\n\tstruct {\n\t\t__u32 rev: 8;\n\t\t__u32 stepping: 4;\n\t\t__u32 model: 4;\n\t\t__u32 __reserved: 4;\n\t\t__u32 ext_model: 4;\n\t\t__u32 ext_fam: 8;\n\t};\n\t__u32 ucode_rev;\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef acpi_status (*acpi_exception_handler)(acpi_status, acpi_name, u16, u32, void *);\n\ntypedef acpi_status (*acpi_execute_op)(struct acpi_walk_state *);\n\ntypedef void (*acpi_gbl_event_handler)(u32, acpi_handle, u32, void *);\n\ntypedef acpi_status (*acpi_gpe_callback)(struct acpi_gpe_xrupt_info *, struct acpi_gpe_block_info *, void *);\n\ntypedef acpi_status (*acpi_init_handler)(acpi_handle, u32);\n\ntypedef u32 (*acpi_interface_handler)(acpi_string, u32);\n\ntypedef u32 (*acpi_osd_handler)(void *);\n\ntypedef acpi_status (*acpi_pkg_callback)(u8, union acpi_operand_object *, union acpi_generic_state *, void *);\n\ntypedef acpi_status (*acpi_table_handler)(u32, void *, void *);\n\ntypedef acpi_status (*acpi_walk_aml_callback)(u8 *, u32, u32, u8, void **);\n\ntypedef acpi_status (*acpi_walk_resource_callback)(struct acpi_resource *, void *);\n\ntypedef void amd_pmu_branch_reset_t(void);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\ntypedef void blk_log_action_t(struct trace_iterator *, const char *, bool);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u32 (*bpf_prog_run_fn)(const struct bpf_prog *, const void *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_d_path)(const struct path *, char *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_pe)(struct bpf_perf_event_data_kern *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_trace)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_branch_snapshot)(void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid_curr)(void);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_task)(void);\n\ntypedef u64 (*btf_bpf_get_current_task_btf)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_func_ip_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_pe)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_sleepable)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_pe)(struct bpf_perf_event_data_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack_sleepable)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_probe_read_compat)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_printf_btf)(struct seq_file *, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_sk_ancestor_cgroup_id)(struct sock *, int);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_cgroup_id)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_ancestor_cgroup_id)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_cgroup_id)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_get_xfrm_state)(struct sk_buff *, u32, struct bpf_xfrm_state *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_snprintf_btf)(char *, u32, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_task_pt_regs)(struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv4)(struct iphdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv4)(struct iphdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_vprintk)(char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_get_func_arg)(void *, u32, u64 *);\n\ntypedef u64 (*btf_get_func_arg_cnt)(void *);\n\ntypedef u64 (*btf_get_func_ret)(void *, u64 *);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*btf_trace_9p_client_req)(void *, struct p9_client *, int8_t, int);\n\ntypedef void (*btf_trace_9p_client_res)(void *, struct p9_client *, int8_t, int, int);\n\ntypedef void (*btf_trace_9p_fid_ref)(void *, struct p9_fid *, __u8);\n\ntypedef void (*btf_trace_9p_protocol_dump)(void *, struct p9_client *, struct p9_fcall *);\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_suspend)(void *, ktime_t, int);\n\ntypedef void (*btf_trace_alloc_vmap_area)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_amd_pstate_epp_perf)(void *, unsigned int, u8, u8, u8, u8, bool, bool);\n\ntypedef void (*btf_trace_amd_pstate_perf)(void *, u8, u8, u8, u64, u64, u64, u64, unsigned int, bool);\n\ntypedef void (*btf_trace_api_beacon_loss)(void *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_api_chswitch_done)(void *, struct ieee80211_sub_if_data *, bool, unsigned int);\n\ntypedef void (*btf_trace_api_connection_loss)(void *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_api_cqm_beacon_loss_notify)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_api_cqm_rssi_notify)(void *, struct ieee80211_sub_if_data *, enum nl80211_cqm_rssi_threshold_event, s32);\n\ntypedef void (*btf_trace_api_disconnect)(void *, struct ieee80211_sub_if_data *, bool);\n\ntypedef void (*btf_trace_api_enable_rssi_reports)(void *, struct ieee80211_sub_if_data *, int, int);\n\ntypedef void (*btf_trace_api_eosp)(void *, struct ieee80211_local *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_api_finalize_rx_omi_bw)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct link_sta_info *);\n\ntypedef void (*btf_trace_api_gtk_rekey_notify)(void *, struct ieee80211_sub_if_data *, const u8 *, const u8 *);\n\ntypedef void (*btf_trace_api_prepare_rx_omi_bw)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct link_sta_info *, enum ieee80211_sta_rx_bandwidth);\n\ntypedef void (*btf_trace_api_radar_detected)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_ready_on_channel)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_remain_on_channel_expired)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_request_smps)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_link_data *, enum ieee80211_smps_mode);\n\ntypedef void (*btf_trace_api_restart_hw)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_return_bool)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_api_return_void)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_scan_completed)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_api_sched_scan_results)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_sched_scan_stopped)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_send_eosp_nullfunc)(void *, struct ieee80211_local *, struct ieee80211_sta *, u8);\n\ntypedef void (*btf_trace_api_sta_block_awake)(void *, struct ieee80211_local *, struct ieee80211_sta *, bool);\n\ntypedef void (*btf_trace_api_sta_set_buffered)(void *, struct ieee80211_local *, struct ieee80211_sta *, u8, bool);\n\ntypedef void (*btf_trace_api_start_tx_ba_cb)(void *, struct ieee80211_sub_if_data *, const u8 *, u16);\n\ntypedef void (*btf_trace_api_start_tx_ba_session)(void *, struct ieee80211_sta *, u16);\n\ntypedef void (*btf_trace_api_stop_tx_ba_cb)(void *, struct ieee80211_sub_if_data *, const u8 *, u16);\n\ntypedef void (*btf_trace_api_stop_tx_ba_session)(void *, struct ieee80211_sta *, u16);\n\ntypedef void (*btf_trace_ata_bmdma_setup)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_start)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_status)(void *, struct ata_port *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_stop)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_about_to_do)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_done)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy)(void *, struct ata_device *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy_qc)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_exec_command)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_softreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_softreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_port_freeze)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_port_thaw)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_qc_complete_done)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_failed)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_internal)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_issue)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_prep)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_sff_flush_pio_task)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_sff_hsm_command_complete)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_hsm_state)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_sff_port_intr)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_slave_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_slave_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_slave_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_std_sched_eh)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_tf_load)(void *, struct ata_port *, const struct ata_taskfile *);\n\ntypedef void (*btf_trace_atapi_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_atapi_send_cdb)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_azx_get_position)(void *, struct azx *, struct azx_dev *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_azx_pcm_close)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_hw_params)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_open)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_prepare)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_trigger)(void *, struct azx *, struct azx_dev *, int);\n\ntypedef void (*btf_trace_azx_resume)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_runtime_resume)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_runtime_suspend)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_suspend)(void *, struct azx *);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, struct dirty_throttle_control *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_bl_ext_tree_prepare_commit)(void *, int, size_t, u64, bool);\n\ntypedef void (*btf_trace_bl_pr_key_reg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_reg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_bl_pr_key_unreg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_unreg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_blk_zone_append_update_request_bio)(void *, struct request *);\n\ntypedef void (*btf_trace_blk_zone_wplug_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_blkdev_zone_mgmt)(void *, struct bio *, sector_t);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_io_done)(void *, struct request *);\n\ntypedef void (*btf_trace_block_io_start)(void *, struct request *);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_error)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_merge)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_split)(void *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\ntypedef void (*btf_trace_bpf_trace_printk)(void *, const char *);\n\ntypedef void (*btf_trace_bpf_trigger_tp)(void *, int);\n\ntypedef void (*btf_trace_bpf_xdp_link_attach_failed)(void *, const char *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_cache_entry_expired)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_make_negative)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_no_listener)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_upcall)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_update)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_tag_assign)(void *, struct cache_tag *);\n\ntypedef void (*btf_trace_cache_tag_flush_range)(void *, struct cache_tag *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_cache_tag_flush_range_np)(void *, struct cache_tag *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_cache_tag_unassign)(void *, struct cache_tag *);\n\ntypedef void (*btf_trace_call_function_entry)(void *, int);\n\ntypedef void (*btf_trace_call_function_exit)(void *, int);\n\ntypedef void (*btf_trace_call_function_single_entry)(void *, int);\n\ntypedef void (*btf_trace_call_function_single_exit)(void *, int);\n\ntypedef void (*btf_trace_cap_capable)(void *, const struct cred *, struct user_namespace *, const struct user_namespace *, int, int);\n\ntypedef void (*btf_trace_cdev_update)(void *, struct thermal_cooling_device *, long unsigned int);\n\ntypedef void (*btf_trace_cfg80211_assoc_comeback)(void *, struct wireless_dev *, const u8 *, u32);\n\ntypedef void (*btf_trace_cfg80211_bss_color_notify)(void *, struct net_device *, enum nl80211_commands, u8, u64);\n\ntypedef void (*btf_trace_cfg80211_cac_event)(void *, struct net_device *, enum nl80211_radar_event, unsigned int);\n\ntypedef void (*btf_trace_cfg80211_ch_switch_notify)(void *, struct net_device *, struct cfg80211_chan_def *, unsigned int);\n\ntypedef void (*btf_trace_cfg80211_ch_switch_started_notify)(void *, struct net_device *, struct cfg80211_chan_def *, unsigned int);\n\ntypedef void (*btf_trace_cfg80211_control_port_tx_status)(void *, struct wireless_dev *, u64, bool);\n\ntypedef void (*btf_trace_cfg80211_cqm_pktloss_notify)(void *, struct net_device *, const u8 *, u32);\n\ntypedef void (*btf_trace_cfg80211_cqm_rssi_notify)(void *, struct net_device *, enum nl80211_cqm_rssi_threshold_event, s32);\n\ntypedef void (*btf_trace_cfg80211_del_sta)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_epcs_changed)(void *, struct wireless_dev *, bool);\n\ntypedef void (*btf_trace_cfg80211_ft_event)(void *, struct wiphy *, struct net_device *, struct cfg80211_ft_event_params *);\n\ntypedef void (*btf_trace_cfg80211_get_bss)(void *, struct wiphy *, struct ieee80211_channel *, const u8 *, const u8 *, size_t, enum ieee80211_bss_type, enum ieee80211_privacy);\n\ntypedef void (*btf_trace_cfg80211_gtk_rekey_notify)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_ibss_joined)(void *, struct net_device *, const u8 *, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_cfg80211_inform_bss_frame)(void *, struct wiphy *, struct cfg80211_inform_bss *, struct ieee80211_mgmt *, size_t);\n\ntypedef void (*btf_trace_cfg80211_links_removed)(void *, struct net_device *, u16);\n\ntypedef void (*btf_trace_cfg80211_mgmt_tx_status)(void *, struct wireless_dev *, u64, bool);\n\ntypedef void (*btf_trace_cfg80211_michael_mic_failure)(void *, struct net_device *, const u8 *, enum nl80211_key_type, int, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_mlo_reconf_add_done)(void *, struct net_device *, u16, const u8 *, size_t, bool);\n\ntypedef void (*btf_trace_cfg80211_nan_cluster_joined)(void *, struct wireless_dev *, const u8 *, bool);\n\ntypedef void (*btf_trace_cfg80211_new_sta)(void *, struct net_device *, const u8 *, struct station_info *);\n\ntypedef void (*btf_trace_cfg80211_next_nan_dw_notif)(void *, struct wireless_dev *, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_cfg80211_notify_new_peer_candidate)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_pmksa_candidate_notify)(void *, struct net_device *, int, const u8 *, bool);\n\ntypedef void (*btf_trace_cfg80211_pmsr_complete)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_cfg80211_pmsr_report)(void *, struct wiphy *, struct wireless_dev *, u64, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_probe_status)(void *, struct net_device *, const u8 *, u64, bool);\n\ntypedef void (*btf_trace_cfg80211_radar_event)(void *, struct wiphy *, struct cfg80211_chan_def *, bool);\n\ntypedef void (*btf_trace_cfg80211_ready_on_channel)(void *, struct wireless_dev *, u64, struct ieee80211_channel *, unsigned int);\n\ntypedef void (*btf_trace_cfg80211_ready_on_channel_expired)(void *, struct wireless_dev *, u64, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_cfg80211_reg_can_beacon)(void *, struct wiphy *, struct cfg80211_chan_def *, enum nl80211_iftype, u32, u32);\n\ntypedef void (*btf_trace_cfg80211_report_obss_beacon)(void *, struct wiphy *, const u8 *, size_t, int, int);\n\ntypedef void (*btf_trace_cfg80211_report_wowlan_wakeup)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_wowlan_wakeup *);\n\ntypedef void (*btf_trace_cfg80211_return_bool)(void *, bool);\n\ntypedef void (*btf_trace_cfg80211_return_bss)(void *, struct cfg80211_bss *);\n\ntypedef void (*btf_trace_cfg80211_rx_control_port)(void *, struct net_device *, struct sk_buff *, bool, int);\n\ntypedef void (*btf_trace_cfg80211_rx_mgmt)(void *, struct wireless_dev *, struct cfg80211_rx_info *);\n\ntypedef void (*btf_trace_cfg80211_rx_mlme_mgmt)(void *, struct net_device *, const u8 *, int);\n\ntypedef void (*btf_trace_cfg80211_rx_spurious_frame)(void *, struct net_device *, const u8 *, int);\n\ntypedef void (*btf_trace_cfg80211_rx_unexpected_4addr_frame)(void *, struct net_device *, const u8 *, int);\n\ntypedef void (*btf_trace_cfg80211_rx_unprot_mlme_mgmt)(void *, struct net_device *, const u8 *, int);\n\ntypedef void (*btf_trace_cfg80211_scan_done)(void *, struct cfg80211_scan_request_int *, struct cfg80211_scan_info *);\n\ntypedef void (*btf_trace_cfg80211_sched_scan_results)(void *, struct wiphy *, u64);\n\ntypedef void (*btf_trace_cfg80211_sched_scan_stopped)(void *, struct wiphy *, u64);\n\ntypedef void (*btf_trace_cfg80211_send_assoc_failure)(void *, struct net_device *, struct cfg80211_assoc_failure *);\n\ntypedef void (*btf_trace_cfg80211_send_auth_timeout)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_send_rx_assoc)(void *, struct net_device *, const struct cfg80211_rx_assoc_resp_data *);\n\ntypedef void (*btf_trace_cfg80211_stop_link)(void *, struct wiphy *, struct wireless_dev *, int);\n\ntypedef void (*btf_trace_cfg80211_tdls_oper_request)(void *, struct wiphy *, struct net_device *, const u8 *, enum nl80211_tdls_operation, u16);\n\ntypedef void (*btf_trace_cfg80211_tx_mgmt_expired)(void *, struct wireless_dev *, u64, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_cfg80211_tx_mlme_mgmt)(void *, struct net_device *, const u8 *, int, bool);\n\ntypedef void (*btf_trace_cfg80211_update_owe_info_event)(void *, struct wiphy *, struct net_device *, struct cfg80211_update_owe_info *);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rstat_lock_contended)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_locked)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_unlock)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_contention_begin)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_contention_end)(void *, void *, int);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_idle_miss)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_csd_function_entry)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_function_exit)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_queue_cpu)(void *, const unsigned int, long unsigned int, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_ctime_ns_xchg)(void *, struct inode *, u32, u32, u32);\n\ntypedef void (*btf_trace_ctime_xchg_skip)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_deferred_error_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_deferred_error_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_device_pm_callback_end)(void *, struct device *, int);\n\ntypedef void (*btf_trace_device_pm_callback_start)(void *, struct device *, const char *, int);\n\ntypedef void (*btf_trace_devres_log)(void *, struct device *, const char *, void *, const char *, size_t);\n\ntypedef void (*btf_trace_disk_zone_wplug_add_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_dma_alloc)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt_err)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_buf_detach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_dynamic_attach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_export)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_fd)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_get)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_mmap)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_mmap_internal)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_put)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_free)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_map_phys)(void *, struct device *, phys_addr_t, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg_err)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_sync_sg_for_cpu)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_sg_for_device)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_cpu)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_device)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_unmap_phys)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_unmap_sg)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dql_stall_detected)(void *, short unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_drm_vblank_event)(void *, int, unsigned int, ktime_t, bool);\n\ntypedef void (*btf_trace_drm_vblank_event_delivered)(void *, struct drm_file *, int, unsigned int);\n\ntypedef void (*btf_trace_drm_vblank_event_queued)(void *, struct drm_file *, int, unsigned int);\n\ntypedef void (*btf_trace_drv_abort_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_abort_pmsr)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_add_chanctx)(void *, struct ieee80211_local *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_add_interface)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_add_nan_func)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const struct cfg80211_nan_func *);\n\ntypedef void (*btf_trace_drv_add_twt_setup)(void *, struct ieee80211_local *, struct ieee80211_sta *, struct ieee80211_twt_setup *, struct ieee80211_twt_params *);\n\ntypedef void (*btf_trace_drv_allow_buffered_frames)(void *, struct ieee80211_local *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\ntypedef void (*btf_trace_drv_ampdu_action)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_ampdu_params *);\n\ntypedef void (*btf_trace_drv_assign_vif_chanctx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_can_activate_links)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u16);\n\ntypedef void (*btf_trace_drv_can_neg_ttlm)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_neg_ttlm *);\n\ntypedef void (*btf_trace_drv_cancel_hw_scan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_cancel_remain_on_channel)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_change_chanctx)(void *, struct ieee80211_local *, struct ieee80211_chanctx *, u32);\n\ntypedef void (*btf_trace_drv_change_interface)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, enum nl80211_iftype, bool);\n\ntypedef void (*btf_trace_drv_change_sta_links)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, u16, u16);\n\ntypedef void (*btf_trace_drv_change_vif_links)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u16, u16);\n\ntypedef void (*btf_trace_drv_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel_switch *);\n\ntypedef void (*btf_trace_drv_channel_switch_beacon)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_drv_channel_switch_rx_beacon)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel_switch *);\n\ntypedef void (*btf_trace_drv_conf_tx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, unsigned int, u16, const struct ieee80211_tx_queue_params *);\n\ntypedef void (*btf_trace_drv_config)(void *, struct ieee80211_local *, int, u32);\n\ntypedef void (*btf_trace_drv_config_iface_filter)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_drv_configure_filter)(void *, struct ieee80211_local *, unsigned int, unsigned int *, u64);\n\ntypedef void (*btf_trace_drv_del_nan_func)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u8);\n\ntypedef void (*btf_trace_drv_event_callback)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const struct ieee80211_event *);\n\ntypedef void (*btf_trace_drv_flush)(void *, struct ieee80211_local *, u32, bool);\n\ntypedef void (*btf_trace_drv_flush_sta)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_get_antenna)(void *, struct ieee80211_local *, int, u32, u32, int);\n\ntypedef void (*btf_trace_drv_get_et_sset_count)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_get_et_stats)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_get_et_strings)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_get_expected_throughput)(void *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_get_ftm_responder_stats)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_ftm_responder_stats *);\n\ntypedef void (*btf_trace_drv_get_key_seq)(void *, struct ieee80211_local *, struct ieee80211_key_conf *);\n\ntypedef void (*btf_trace_drv_get_ringparam)(void *, struct ieee80211_local *, u32 *, u32 *, u32 *, u32 *);\n\ntypedef void (*btf_trace_drv_get_stats)(void *, struct ieee80211_local *, struct ieee80211_low_level_stats *, int);\n\ntypedef void (*btf_trace_drv_get_survey)(void *, struct ieee80211_local *, int, struct survey_info *);\n\ntypedef void (*btf_trace_drv_get_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_get_txpower)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, unsigned int, int, int);\n\ntypedef void (*btf_trace_drv_hw_scan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_ipv6_addr_change)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_join_ibss)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *);\n\ntypedef void (*btf_trace_drv_leave_ibss)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_link_info_changed)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *, u64);\n\ntypedef void (*btf_trace_drv_link_sta_rc_update)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_link_sta *, u32);\n\ntypedef void (*btf_trace_drv_link_sta_statistics)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_link_sta *);\n\ntypedef void (*btf_trace_drv_mgd_complete_tx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u16, u16, bool);\n\ntypedef void (*btf_trace_drv_mgd_prepare_tx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u16, u16, bool);\n\ntypedef void (*btf_trace_drv_mgd_protect_tdls_discover)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_nan_change_conf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_nan_conf *, u32);\n\ntypedef void (*btf_trace_drv_neg_ttlm_res)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, enum ieee80211_neg_ttlm_res, struct ieee80211_neg_ttlm *);\n\ntypedef void (*btf_trace_drv_net_fill_forward_path)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_net_setup_tc)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u8);\n\ntypedef void (*btf_trace_drv_offchannel_tx_cancel_wait)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_offset_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, s64);\n\ntypedef void (*btf_trace_drv_post_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_pre_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel_switch *);\n\ntypedef void (*btf_trace_drv_prep_add_interface)(void *, struct ieee80211_local *, enum nl80211_iftype);\n\ntypedef void (*btf_trace_drv_prepare_multicast)(void *, struct ieee80211_local *, int);\n\ntypedef void (*btf_trace_drv_reconfig_complete)(void *, struct ieee80211_local *, enum ieee80211_reconfig_type);\n\ntypedef void (*btf_trace_drv_release_buffered_frames)(void *, struct ieee80211_local *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\ntypedef void (*btf_trace_drv_remain_on_channel)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel *, unsigned int, enum ieee80211_roc_type);\n\ntypedef void (*btf_trace_drv_remove_chanctx)(void *, struct ieee80211_local *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_remove_interface)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_reset_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_resume)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_return_bool)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_drv_return_int)(void *, struct ieee80211_local *, int);\n\ntypedef void (*btf_trace_drv_return_u32)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_return_u64)(void *, struct ieee80211_local *, u64);\n\ntypedef void (*btf_trace_drv_return_void)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_sched_scan_start)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_sched_scan_stop)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_set_antenna)(void *, struct ieee80211_local *, u32, u32, int);\n\ntypedef void (*btf_trace_drv_set_bitrate_mask)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const struct cfg80211_bitrate_mask *);\n\ntypedef void (*btf_trace_drv_set_coverage_class)(void *, struct ieee80211_local *, int, s16);\n\ntypedef void (*btf_trace_drv_set_default_unicast_key)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, int);\n\ntypedef void (*btf_trace_drv_set_eml_op_mode)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, unsigned int, u8, u16);\n\ntypedef void (*btf_trace_drv_set_frag_threshold)(void *, struct ieee80211_local *, int, u32);\n\ntypedef void (*btf_trace_drv_set_key)(void *, struct ieee80211_local *, enum set_key_cmd, struct ieee80211_sub_if_data *, struct ieee80211_sta *, struct ieee80211_key_conf *);\n\ntypedef void (*btf_trace_drv_set_rekey_data)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_gtk_rekey_data *);\n\ntypedef void (*btf_trace_drv_set_ringparam)(void *, struct ieee80211_local *, u32, u32);\n\ntypedef void (*btf_trace_drv_set_rts_threshold)(void *, struct ieee80211_local *, int, u32);\n\ntypedef void (*btf_trace_drv_set_tim)(void *, struct ieee80211_local *, struct ieee80211_sta *, bool);\n\ntypedef void (*btf_trace_drv_set_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u64);\n\ntypedef void (*btf_trace_drv_set_wakeup)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_drv_sta_add)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_notify)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, enum sta_notify_cmd, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_pre_rcu_remove)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_rate_tbl_update)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_remove)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_set_4addr)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, bool);\n\ntypedef void (*btf_trace_drv_sta_set_decap_offload)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, bool);\n\ntypedef void (*btf_trace_drv_sta_set_txpwr)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_state)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, enum ieee80211_sta_state, enum ieee80211_sta_state);\n\ntypedef void (*btf_trace_drv_sta_statistics)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_start)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_start_ap)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *);\n\ntypedef void (*btf_trace_drv_start_nan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_nan_conf *);\n\ntypedef void (*btf_trace_drv_start_pmsr)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_stop)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_drv_stop_ap)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *);\n\ntypedef void (*btf_trace_drv_stop_nan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_suspend)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_sw_scan_complete)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_sw_scan_start)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const u8 *);\n\ntypedef void (*btf_trace_drv_switch_vif_chanctx)(void *, struct ieee80211_local *, struct ieee80211_vif_chanctx_switch *, int, enum ieee80211_chanctx_switch_mode);\n\ntypedef void (*btf_trace_drv_sync_rx_queues)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_tdls_cancel_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_tdls_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, u8, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_drv_tdls_recv_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_tdls_ch_sw_params *);\n\ntypedef void (*btf_trace_drv_twt_teardown_request)(void *, struct ieee80211_local *, struct ieee80211_sta *, u8);\n\ntypedef void (*btf_trace_drv_tx_frames_pending)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_tx_last_beacon)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_unassign_vif_chanctx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_update_tkip_key)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_key_conf *, struct ieee80211_sta *, u32);\n\ntypedef void (*btf_trace_drv_update_vif_offload)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_vif_cfg_changed)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u64);\n\ntypedef void (*btf_trace_drv_wake_tx_queue)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct txq_info *);\n\ntypedef void (*btf_trace_e1000e_trace_mac_register)(void *, uint32_t);\n\ntypedef void (*btf_trace_emulate_vsyscall)(void *, int);\n\ntypedef void (*btf_trace_error_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_error_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_error_report_end)(void *, enum error_detector, long unsigned int);\n\ntypedef void (*btf_trace_exit_mmap)(void *, struct mm_struct *);\n\ntypedef void (*btf_trace_ext4_alloc_da_blocks)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_allocate_blocks)(void *, struct ext4_allocation_request *, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_allocate_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_begin_ordered_truncate)(void *, struct inode *, loff_t);\n\ntypedef void (*btf_trace_ext4_collapse_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_da_release_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_reserve_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_update_reserve_space)(void *, struct inode *, int, int);\n\ntypedef void (*btf_trace_ext4_da_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_end)(void *, struct inode *, loff_t, loff_t, struct writeback_control *, int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_start)(void *, struct inode *, loff_t, loff_t, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages_extent)(void *, struct inode *, struct ext4_map_blocks *);\n\ntypedef void (*btf_trace_ext4_discard_blocks)(void *, struct super_block *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_discard_preallocations)(void *, struct inode *, unsigned int);\n\ntypedef void (*btf_trace_ext4_drop_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_error)(void *, struct super_block *, const char *, unsigned int);\n\ntypedef void (*btf_trace_ext4_es_cache_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_exit)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_insert_delayed_extent)(void *, struct inode *, struct extent_status *, bool, bool);\n\ntypedef void (*btf_trace_ext4_es_insert_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_exit)(void *, struct inode *, struct extent_status *, int);\n\ntypedef void (*btf_trace_ext4_es_remove_extent)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_shrink)(void *, struct super_block *, int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_count)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_enter)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_exit)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_enter)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_fastpath)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_handle_unwritten_extents)(void *, struct inode *, struct ext4_map_blocks *, int, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_load_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space_done)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, struct partial_cluster *, __le16);\n\ntypedef void (*btf_trace_ext4_ext_rm_idx)(void *, struct inode *, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_rm_leaf)(void *, struct inode *, ext4_lblk_t, struct ext4_extent *, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_show_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t, short unsigned int);\n\ntypedef void (*btf_trace_ext4_fallocate_enter)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_fallocate_exit)(void *, struct inode *, loff_t, unsigned int, int);\n\ntypedef void (*btf_trace_ext4_fc_cleanup)(void *, journal_t *, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_start)(void *, struct super_block *, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_stop)(void *, struct super_block *, int, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_replay)(void *, struct super_block *, int, int, int, int);\n\ntypedef void (*btf_trace_ext4_fc_replay_scan)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_fc_stats)(void *, struct super_block *);\n\ntypedef void (*btf_trace_ext4_fc_track_create)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_inode)(void *, handle_t *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_link)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_range)(void *, handle_t *, struct inode *, long int, long int, int);\n\ntypedef void (*btf_trace_ext4_fc_track_unlink)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_forget)(void *, struct inode *, int, __u64);\n\ntypedef void (*btf_trace_ext4_free_blocks)(void *, struct inode *, __u64, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_fsmap_high_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_low_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_mapping)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_get_implied_cluster_alloc_exit)(void *, struct super_block *, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_getfsmap_high_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_low_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_mapping)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_insert_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journal_start_inode)(void *, struct inode *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_reserved)(void *, struct super_block *, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_sb)(void *, struct super_block *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journalled_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_lazy_itable_init)(void *, struct super_block *, ext4_group_t);\n\ntypedef void (*btf_trace_ext4_load_inode)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_load_inode_bitmap)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mark_inode_dirty)(void *, struct inode *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_buddy_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_discard_preallocations)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_mb_new_group_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_new_inode_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_group_pa)(void *, struct super_block *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_inode_pa)(void *, struct ext4_prealloc_space *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_mballoc_alloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_discard)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_free)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_prealloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_move_extent_enter)(void *, struct inode *, struct ext4_map_blocks *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_move_extent_exit)(void *, struct inode *, ext4_lblk_t, struct inode *, ext4_lblk_t, unsigned int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_nfs_commit_metadata)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_other_inode_update_time)(void *, struct inode *, ino_t);\n\ntypedef void (*btf_trace_ext4_prefetch_bitmaps)(void *, struct super_block *, ext4_group_t, ext4_group_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_punch_hole)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_read_block_bitmap_load)(void *, struct super_block *, long unsigned int, bool);\n\ntypedef void (*btf_trace_ext4_read_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_release_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_remove_blocks)(void *, struct inode *, struct ext4_extent *, ext4_lblk_t, ext4_fsblk_t, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_request_blocks)(void *, struct ext4_allocation_request *);\n\ntypedef void (*btf_trace_ext4_request_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_shutdown)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_sync_file_enter)(void *, struct file *, int);\n\ntypedef void (*btf_trace_ext4_sync_file_exit)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_sync_fs)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_trim_all_free)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_trim_extent)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_truncate_enter)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_truncate_exit)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_unlink_enter)(void *, struct inode *, struct dentry *);\n\ntypedef void (*btf_trace_ext4_unlink_exit)(void *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_update_sb)(void *, struct super_block *, ext4_fsblk_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_writepages)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_writepages_result)(void *, struct inode *, struct writeback_control *, int, int);\n\ntypedef void (*btf_trace_ext4_zero_range)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ff_layout_commit_error)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_ff_layout_read_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_ff_layout_write_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_fib6_table_lookup)(void *, const struct net *, const struct fib6_result *, struct fib6_table *, const struct flowi6 *);\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_fill_mg_cmtime)(void *, struct inode *, struct timespec64 *, struct timespec64 *);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_fl_getdevinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, char *);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_folio_wait_writeback)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_free_vmap_area_noflush)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_g4x_wm)(void *, struct intel_crtc *, const struct g4x_wm_values *);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_guest_halt_poll_ns)(void *, bool, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_handshake_cancel)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_busy)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_none)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cmd_accept)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_accept_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_complete)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_destruct)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_notify_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_submit)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_submit_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_hda_get_response)(void *, struct hdac_bus *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_hda_send_cmd)(void *, struct hdac_bus *, unsigned int);\n\ntypedef void (*btf_trace_hda_unsol_event)(void *, struct hdac_bus *, u32, u32);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_setup)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hugetlbfs_alloc_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_hugetlbfs_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_fallocate)(void *, struct inode *, int, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_hugetlbfs_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_setattr)(void *, struct inode *, struct dentry *, struct iattr *);\n\ntypedef void (*btf_trace_hwmon_attr_show)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_hwmon_attr_show_string)(void *, int, const char *, const char *);\n\ntypedef void (*btf_trace_hwmon_attr_store)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_i2c_read)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_reply)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_result)(void *, const struct i2c_adapter *, int, int);\n\ntypedef void (*btf_trace_i2c_write)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i915_context_create)(void *, struct i915_gem_context *);\n\ntypedef void (*btf_trace_i915_context_free)(void *, struct i915_gem_context *);\n\ntypedef void (*btf_trace_i915_gem_evict)(void *, struct i915_address_space *, u64, u64, unsigned int);\n\ntypedef void (*btf_trace_i915_gem_evict_node)(void *, struct i915_address_space *, struct drm_mm_node *, unsigned int);\n\ntypedef void (*btf_trace_i915_gem_evict_vm)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_gem_object_clflush)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_object_create)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_object_destroy)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_object_fault)(void *, struct drm_i915_gem_object *, u64, bool, bool);\n\ntypedef void (*btf_trace_i915_gem_object_pread)(void *, struct drm_i915_gem_object *, u64, u64);\n\ntypedef void (*btf_trace_i915_gem_object_pwrite)(void *, struct drm_i915_gem_object *, u64, u64);\n\ntypedef void (*btf_trace_i915_gem_shrink)(void *, struct drm_i915_private *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_i915_ppgtt_create)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_ppgtt_release)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_reg_rw)(void *, bool, i915_reg_t, u64, int, bool);\n\ntypedef void (*btf_trace_i915_request_add)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_request_queue)(void *, struct i915_request *, u32);\n\ntypedef void (*btf_trace_i915_request_retire)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_request_wait_begin)(void *, struct i915_request *, unsigned int);\n\ntypedef void (*btf_trace_i915_request_wait_end)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_vma_bind)(void *, struct i915_vma *, unsigned int);\n\ntypedef void (*btf_trace_i915_vma_unbind)(void *, struct i915_vma *);\n\ntypedef void (*btf_trace_icmp_send)(void *, const struct sk_buff *, int, int);\n\ntypedef void (*btf_trace_inet_sk_error_report)(void *, const struct sock *);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_inode_set_ctime_to_ts)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_intel_cpu_fifo_underrun)(void *, struct intel_display *, enum pipe);\n\ntypedef void (*btf_trace_intel_crtc_flip_done)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_crtc_vblank_work_end)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_crtc_vblank_work_start)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_fbc_activate)(void *, struct intel_plane *);\n\ntypedef void (*btf_trace_intel_fbc_deactivate)(void *, struct intel_plane *);\n\ntypedef void (*btf_trace_intel_fbc_nuke)(void *, struct intel_plane *);\n\ntypedef void (*btf_trace_intel_frontbuffer_flush)(void *, struct intel_display *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_intel_frontbuffer_invalidate)(void *, struct intel_display *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_intel_memory_cxsr)(void *, struct intel_display *, bool, bool);\n\ntypedef void (*btf_trace_intel_pch_fifo_underrun)(void *, struct intel_display *, enum pipe);\n\ntypedef void (*btf_trace_intel_pipe_crc)(void *, struct intel_crtc *, const u32 *);\n\ntypedef void (*btf_trace_intel_pipe_disable)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_enable)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_scaler_update_arm)(void *, struct intel_crtc *, int, int, int, int, int);\n\ntypedef void (*btf_trace_intel_pipe_update_end)(void *, struct intel_crtc *, u32, int);\n\ntypedef void (*btf_trace_intel_pipe_update_start)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_update_vblank_evaded)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_plane_async_flip)(void *, struct intel_plane *, struct intel_crtc *, bool);\n\ntypedef void (*btf_trace_intel_plane_disable_arm)(void *, struct intel_plane *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_plane_scaler_update_arm)(void *, struct intel_plane *, int, int, int, int, int);\n\ntypedef void (*btf_trace_intel_plane_update_arm)(void *, const struct intel_plane_state *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_plane_update_noarm)(void *, const struct intel_plane_state *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_scaler_disable_arm)(void *, struct intel_crtc *, int);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, struct io_ring_ctx *, void *, struct io_uring_cqe *);\n\ntypedef void (*btf_trace_io_uring_cqe_overflow)(void *, void *, long long unsigned int, s32, u32, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_local_work_run)(void *, void *, int, unsigned int);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, struct io_kiocb *, int, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, struct io_kiocb *, bool);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, long int);\n\ntypedef void (*btf_trace_io_uring_req_failed)(void *, const struct io_uring_sqe *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_short_write)(void *, void *, u64, u64, u64);\n\ntypedef void (*btf_trace_io_uring_submit_req)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_task_work_run)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_iocost_inuse_adjust)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_inuse_shortage)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_inuse_transfer)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u32, u64, u64);\n\ntypedef void (*btf_trace_iocost_ioc_vrate_adj)(void *, struct ioc *, u64, u32 *, u32, int, int);\n\ntypedef void (*btf_trace_iocost_iocg_activate)(void *, struct ioc_gq *, const char *, struct ioc_now *, u64, u64, u64);\n\ntypedef void (*btf_trace_iocost_iocg_forgive_debt)(void *, struct ioc_gq *, const char *, struct ioc_now *, u32, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_iocost_iocg_idle)(void *, struct ioc_gq *, const char *, struct ioc_now *, u64, u64, u64);\n\ntypedef void (*btf_trace_iomap_add_to_ioend)(void *, struct inode *, u64, unsigned int, struct iomap *);\n\ntypedef void (*btf_trace_iomap_dio_complete)(void *, struct kiocb *, int, ssize_t);\n\ntypedef void (*btf_trace_iomap_dio_invalidate_fail)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_dio_rw_begin)(void *, struct kiocb *, struct iov_iter *, unsigned int, size_t);\n\ntypedef void (*btf_trace_iomap_dio_rw_queued)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_invalidate_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_iter)(void *, struct iomap_iter *, const void *, long unsigned int);\n\ntypedef void (*btf_trace_iomap_iter_dstmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_iter_srcmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_release_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_writeback_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_zero_iter)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_ipi_send_cpu)(void *, const unsigned int, long unsigned int, void *);\n\ntypedef void (*btf_trace_ipi_send_cpumask)(void *, const struct cpumask *, long unsigned int, void *);\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_irq_matrix_alloc)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_alloc_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_assign)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_assign_system)(void *, int, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_free)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_offline)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_online)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_remove_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_remove_reserved)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_reserve)(void *, struct irq_matrix *);\n\ntypedef void (*btf_trace_irq_matrix_reserve_managed)(void *, int, unsigned int, struct irq_matrix *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_work_entry)(void *, int);\n\ntypedef void (*btf_trace_irq_work_exit)(void *, int);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_jbd2_checkpoint)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_checkpoint_stats)(void *, dev_t, tid_t, struct transaction_chp_stats_s *);\n\ntypedef void (*btf_trace_jbd2_commit_flushing)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_locking)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_logging)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_drop_transaction)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_end_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_handle_extend)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int);\n\ntypedef void (*btf_trace_jbd2_handle_restart)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_start)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_stats)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int, int, int);\n\ntypedef void (*btf_trace_jbd2_lock_buffer_stall)(void *, dev_t, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_run_stats)(void *, dev_t, tid_t, struct transaction_run_stats_s *);\n\ntypedef void (*btf_trace_jbd2_shrink_checkpoint_list)(void *, journal_t *, tid_t, tid_t, tid_t, long unsigned int, tid_t);\n\ntypedef void (*btf_trace_jbd2_shrink_count)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_enter)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_exit)(void *, journal_t *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_start_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_submit_inode_data)(void *, struct inode *);\n\ntypedef void (*btf_trace_jbd2_update_log_tail)(void *, journal_t *, tid_t, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_write_superblock)(void *, journal_t *, blk_opf_t);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *, enum skb_drop_reason, struct sock *);\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, struct kmem_cache *, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *, const struct kmem_cache *);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, dev_t, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_latency)(void *, dev_t, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, dev_t, const char *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lease *, struct file_lease *);\n\ntypedef void (*btf_trace_local_timer_entry)(void *, int);\n\ntypedef void (*btf_trace_local_timer_exit)(void *, int);\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ma_op)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_read)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_write)(void *, const char *, struct ma_state *, long unsigned int, void *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_mark_victim)(void *, struct task_struct *, uid_t);\n\ntypedef void (*btf_trace_mce_record)(void *, struct mce_hw_err *);\n\ntypedef void (*btf_trace_mdio_access)(void *, struct mii_bus *, char, u8, unsigned int, u16, int);\n\ntypedef void (*btf_trace_mei_pci_cfg_read)(void *, const struct device *, const char *, u32, u32);\n\ntypedef void (*btf_trace_mei_reg_read)(void *, const struct device *, const char *, u32, u32);\n\ntypedef void (*btf_trace_mei_reg_write)(void *, const struct device *, const char *, u32, u32);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_mm_calculate_totalreserve_pages)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, struct compact_control *, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, struct compact_control *, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_fast_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_fault)(void *, struct address_space *, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_get_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_map_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_migrate_pages_start)(void *, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_lowmem_reserve)(void *, struct zone *, struct zone *, long int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_wmarks)(void *, struct zone *);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_clear_hopeless)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_reclaim_fail)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_reclaim_pages)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *);\n\ntypedef void (*btf_trace_mm_vmscan_throttled)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_write_folio)(void *, struct folio *);\n\ntypedef void (*btf_trace_mmap_lock_acquire_returned)(void *, struct mm_struct *, bool, bool);\n\ntypedef void (*btf_trace_mmap_lock_released)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmap_lock_start_locking)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_netfs_collect)(void *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_collect_folio)(void *, const struct netfs_io_request *, const struct folio *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_gap)(void *, const struct netfs_io_request *, const struct netfs_io_stream *, long long unsigned int, char);\n\ntypedef void (*btf_trace_netfs_collect_sreq)(void *, const struct netfs_io_request *, const struct netfs_io_subrequest *);\n\ntypedef void (*btf_trace_netfs_collect_state)(void *, const struct netfs_io_request *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_stream)(void *, const struct netfs_io_request *, const struct netfs_io_stream *);\n\ntypedef void (*btf_trace_netfs_copy2cache)(void *, const struct netfs_io_request *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_failure)(void *, struct netfs_io_request *, struct netfs_io_subrequest *, int, enum netfs_failure);\n\ntypedef void (*btf_trace_netfs_folio)(void *, struct folio *, enum netfs_folio_trace);\n\ntypedef void (*btf_trace_netfs_folioq)(void *, const struct folio_queue *, enum netfs_folioq_trace);\n\ntypedef void (*btf_trace_netfs_read)(void *, struct netfs_io_request *, loff_t, size_t, enum netfs_read_trace);\n\ntypedef void (*btf_trace_netfs_rreq)(void *, struct netfs_io_request *, enum netfs_rreq_trace);\n\ntypedef void (*btf_trace_netfs_rreq_ref)(void *, unsigned int, int, enum netfs_rreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_sreq)(void *, struct netfs_io_subrequest *, enum netfs_sreq_trace);\n\ntypedef void (*btf_trace_netfs_sreq_ref)(void *, unsigned int, unsigned int, int, enum netfs_sreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_write)(void *, const struct netfs_io_request *, enum netfs_write_trace);\n\ntypedef void (*btf_trace_netfs_write_iter)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netlink_extack)(void *, const char *);\n\ntypedef void (*btf_trace_nfs41_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_access)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_bind_conn_to_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_cached_open)(void *, const struct nfs4_state *);\n\ntypedef void (*btf_trace_nfs4_cb_getattr)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_cb_layoutrecall_file)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_offload)(void *, const struct nfs_fh *, const nfs4_stateid *, uint64_t, int, int);\n\ntypedef void (*btf_trace_nfs4_cb_recall)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_seqid_err)(void *, const struct cb_sequenceargs *, __be32);\n\ntypedef void (*btf_trace_nfs4_cb_sequence)(void *, const struct cb_sequenceargs *, const struct cb_sequenceres *, __be32);\n\ntypedef void (*btf_trace_nfs4_close)(void *, const struct nfs4_state *, const struct nfs_closeargs *, const struct nfs_closeres *, int);\n\ntypedef void (*btf_trace_nfs4_close_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_commit)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_create_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn_exit)(void *, const struct nfs4_delegreturnargs *, const struct nfs4_delegreturnres *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_clientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_detach_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_deviceid_free)(void *, const struct nfs_client *, const struct nfs4_deviceid *);\n\ntypedef void (*btf_trace_nfs4_exchange_id)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_find_deviceid)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_fsinfo)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_get_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_get_fs_locations)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_get_lock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_getattr)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_getdeviceinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutcommit)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layouterror)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutget)(void *, const struct nfs_open_context *, const struct pnfs_layout_range *, const struct pnfs_layout_range *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn_on_close)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutstats)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_lookup)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_lookup_root)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_lookupp)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_map_gid_to_group)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_group_to_gid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_name_to_uid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_uid_to_name)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_mkdir)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_mknod)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_open_expired)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_file)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_reclaim)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_skip)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_commit_ds)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_readdir)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_readlink)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_complete)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_remove)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_rename)(void *, const struct inode *, const struct qstr *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_renew)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_renew_async)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_secinfo)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_sequence)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_sequence_done)(void *, const struct nfs4_session *, const struct nfs4_sequence_res *);\n\ntypedef void (*btf_trace_nfs4_set_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_set_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_set_lock)(void *, const struct file_lock *, const struct nfs4_state *, const nfs4_stateid *, int, int);\n\ntypedef void (*btf_trace_nfs4_setattr)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid_confirm)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setup_sequence)(void *, const struct nfs4_session *, const struct nfs4_sequence_args *);\n\ntypedef void (*btf_trace_nfs4_state_lock_reclaim)(void *, const struct nfs4_state *, const struct nfs4_lock_state *);\n\ntypedef void (*btf_trace_nfs4_state_mgr)(void *, const struct nfs_client *);\n\ntypedef void (*btf_trace_nfs4_state_mgr_failed)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_symlink)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_test_delegation_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_lock_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_open_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_trunked_exchange_id)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_unlock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_filehandle)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_operation)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_status)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs_access_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_access_exit)(void *, const struct inode *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readahead)(void *, const struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_nfs_aop_readahead_done)(void *, const struct inode *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readpage)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_aop_readpage_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_async_rename_done)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_atomic_open_enter)(void *, const struct inode *, const struct nfs_open_context *, unsigned int);\n\ntypedef void (*btf_trace_nfs_atomic_open_exit)(void *, const struct inode *, const struct nfs_open_context *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_cb_badprinc)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_cb_no_clp)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_commit_done)(void *, const struct rpc_task *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_commit_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_comp_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_create_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_create_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_delegation_need_return)(void *, const struct nfs_delegation *);\n\ntypedef void (*btf_trace_nfs_direct_commit_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_resched_write)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_completion)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_reschedule_io)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_schedule_iovec)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_do_writepage)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_fh_to_dentry)(void *, const struct super_block *, const struct nfs_fh *, u64, int);\n\ntypedef void (*btf_trace_nfs_file_read)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_file_write)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_fsync_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_fsync_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_getattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_getattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_initiate_commit)(void *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_initiate_read)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_initiate_write)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_invalidate_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_launder_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_link_enter)(void *, const struct inode *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_link_exit)(void *, const struct inode *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_local_open_fh)(void *, const struct nfs_fh *, fmode_t, int);\n\ntypedef void (*btf_trace_nfs_lookup_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_mkdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mkdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mknod_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mknod_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mount_assign)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_nfs_mount_option)(void *, const struct fs_parameter *);\n\ntypedef void (*btf_trace_nfs_mount_path)(void *, const char *);\n\ntypedef void (*btf_trace_nfs_pgio_error)(void *, const struct nfs_pgio_header *, int, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readdir_force_readdirplus)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_readdir_invalidate_cache_range)(void *, const struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_lookup)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate_failed)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readpage_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_readpage_short)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_remove_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_remove_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_rename_enter)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rename_exit)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_rmdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rmdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_set_cache_invalid)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_set_inode_stale)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_sillyrename_unlink)(void *, const struct nfs_unlinkdata *, int);\n\ntypedef void (*btf_trace_nfs_size_grow)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate_folio)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_update)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_wcc)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_symlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_symlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_try_to_update_request)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_try_to_update_request_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_unlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_unlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_update_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_update_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_begin)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_begin_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_end)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_end_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_writeback_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_writeback_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_writeback_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_writepage_setup)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_writepages)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writepages_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_xdr_bad_filehandle)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nfs_xdr_status)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nlmclnt_grant)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_lock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_test)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_unlock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nmi_handler)(void *, void *, s64, int);\n\ntypedef void (*btf_trace_notifier_register)(void *, void *);\n\ntypedef void (*btf_trace_notifier_run)(void *, void *);\n\ntypedef void (*btf_trace_notifier_unregister)(void *, void *);\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_page_cache_async_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_ra_order)(void *, struct inode *, long unsigned int, struct file_ra_state *);\n\ntypedef void (*btf_trace_page_cache_ra_unbounded)(void *, struct inode *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_sync_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_fault_kernel)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\ntypedef void (*btf_trace_page_fault_user)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\ntypedef void (*btf_trace_page_pool_release)(void *, const struct page_pool *, s32, u32, u32);\n\ntypedef void (*btf_trace_page_pool_state_hold)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_state_release)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_update_nid)(void *, const struct page_pool *, int);\n\ntypedef void (*btf_trace_pci_hp_event)(void *, const char *, const char *, const int);\n\ntypedef void (*btf_trace_pcie_link_event)(void *, struct pci_bus *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pelt_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_pelt_dl_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_hw_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_irq_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_rt_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, long unsigned int, bool, bool, size_t, size_t, void *, int, void *, size_t, gfp_t);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pmap_register)(void *, u32, u32, int, short unsigned int);\n\ntypedef void (*btf_trace_pnfs_ds_connect)(void *, char *, int);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_get_mirror_count)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_read)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_write)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_update_layout)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *, enum pnfs_update_layout_reason);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_prq_report)(void *, struct intel_iommu *, struct device *, u64, u64, u64, u64, long unsigned int);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_purge_vmap_area_lazy)(void *, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_enqueue)(void *, struct Qdisc *, const struct netdev_queue *, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qi_submit)(void *, struct intel_iommu *, u64, u64, u64, u64);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_invoke_kvfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_segcb_stats)(void *, struct rcu_segcblist *, const char *);\n\ntypedef void (*btf_trace_rcu_sr_normal)(void *, const char *, struct callback_head *, const char *);\n\ntypedef void (*btf_trace_rcu_stall_warning)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_watching)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_rdev_abort_pmsr)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_abort_scan)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_add_intf_link)(void *, struct wiphy *, struct wireless_dev *, unsigned int);\n\ntypedef void (*btf_trace_rdev_add_key)(void *, struct wiphy *, struct net_device *, int, u8, bool, const u8 *, u8);\n\ntypedef void (*btf_trace_rdev_add_link_station)(void *, struct wiphy *, struct net_device *, struct link_station_parameters *);\n\ntypedef void (*btf_trace_rdev_add_mpath)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_add_nan_func)(void *, struct wiphy *, struct wireless_dev *, const struct cfg80211_nan_func *);\n\ntypedef void (*btf_trace_rdev_add_station)(void *, struct wiphy *, struct net_device *, u8 *, struct station_parameters *);\n\ntypedef void (*btf_trace_rdev_add_tx_ts)(void *, struct wiphy *, struct net_device *, u8, const u8 *, u8, u16);\n\ntypedef void (*btf_trace_rdev_add_virtual_intf)(void *, struct wiphy *, char *, enum nl80211_iftype);\n\ntypedef void (*btf_trace_rdev_assoc)(void *, struct wiphy *, struct net_device *, struct cfg80211_assoc_request *);\n\ntypedef void (*btf_trace_rdev_assoc_ml_reconf)(void *, struct wiphy *, struct net_device *, struct cfg80211_ml_reconf_req *);\n\ntypedef void (*btf_trace_rdev_auth)(void *, struct wiphy *, struct net_device *, struct cfg80211_auth_request *);\n\ntypedef void (*btf_trace_rdev_cancel_remain_on_channel)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_change_beacon)(void *, struct wiphy *, struct net_device *, struct cfg80211_ap_update *);\n\ntypedef void (*btf_trace_rdev_change_bss)(void *, struct wiphy *, struct net_device *, struct bss_parameters *);\n\ntypedef void (*btf_trace_rdev_change_mpath)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_change_station)(void *, struct wiphy *, struct net_device *, u8 *, struct station_parameters *);\n\ntypedef void (*btf_trace_rdev_change_virtual_intf)(void *, struct wiphy *, struct net_device *, enum nl80211_iftype);\n\ntypedef void (*btf_trace_rdev_channel_switch)(void *, struct wiphy *, struct net_device *, struct cfg80211_csa_settings *);\n\ntypedef void (*btf_trace_rdev_color_change)(void *, struct wiphy *, struct net_device *, struct cfg80211_color_change_settings *);\n\ntypedef void (*btf_trace_rdev_connect)(void *, struct wiphy *, struct net_device *, struct cfg80211_connect_params *);\n\ntypedef void (*btf_trace_rdev_crit_proto_start)(void *, struct wiphy *, struct wireless_dev *, enum nl80211_crit_proto_id, u16);\n\ntypedef void (*btf_trace_rdev_crit_proto_stop)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_deauth)(void *, struct wiphy *, struct net_device *, struct cfg80211_deauth_request *);\n\ntypedef void (*btf_trace_rdev_del_intf_link)(void *, struct wiphy *, struct wireless_dev *, unsigned int);\n\ntypedef void (*btf_trace_rdev_del_key)(void *, struct wiphy *, struct net_device *, int, u8, bool, const u8 *);\n\ntypedef void (*btf_trace_rdev_del_link_station)(void *, struct wiphy *, struct net_device *, struct link_station_del_parameters *);\n\ntypedef void (*btf_trace_rdev_del_mpath)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_del_nan_func)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_del_pmk)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_del_pmksa)(void *, struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\ntypedef void (*btf_trace_rdev_del_station)(void *, struct wiphy *, struct net_device *, struct station_del_parameters *);\n\ntypedef void (*btf_trace_rdev_del_tx_ts)(void *, struct wiphy *, struct net_device *, u8, const u8 *);\n\ntypedef void (*btf_trace_rdev_del_virtual_intf)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_disassoc)(void *, struct wiphy *, struct net_device *, struct cfg80211_disassoc_request *);\n\ntypedef void (*btf_trace_rdev_disconnect)(void *, struct wiphy *, struct net_device *, u16);\n\ntypedef void (*btf_trace_rdev_dump_mpath)(void *, struct wiphy *, struct net_device *, int, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_dump_mpp)(void *, struct wiphy *, struct net_device *, int, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_dump_station)(void *, struct wiphy *, struct net_device *, int, u8 *);\n\ntypedef void (*btf_trace_rdev_dump_survey)(void *, struct wiphy *, struct net_device *, int);\n\ntypedef void (*btf_trace_rdev_end_cac)(void *, struct wiphy *, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_rdev_external_auth)(void *, struct wiphy *, struct net_device *, struct cfg80211_external_auth_params *);\n\ntypedef void (*btf_trace_rdev_flush_pmksa)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_get_antenna)(void *, struct wiphy *, int);\n\ntypedef void (*btf_trace_rdev_get_channel)(void *, struct wiphy *, struct wireless_dev *, unsigned int);\n\ntypedef void (*btf_trace_rdev_get_ftm_responder_stats)(void *, struct wiphy *, struct net_device *, struct cfg80211_ftm_responder_stats *);\n\ntypedef void (*btf_trace_rdev_get_key)(void *, struct wiphy *, struct net_device *, int, u8, bool, const u8 *);\n\ntypedef void (*btf_trace_rdev_get_mesh_config)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_get_mpath)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_get_mpp)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_get_station)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_get_tx_power)(void *, struct wiphy *, struct wireless_dev *, int, unsigned int);\n\ntypedef void (*btf_trace_rdev_get_txq_stats)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_inform_bss)(void *, struct wiphy *, struct cfg80211_bss *);\n\ntypedef void (*btf_trace_rdev_join_ibss)(void *, struct wiphy *, struct net_device *, struct cfg80211_ibss_params *);\n\ntypedef void (*btf_trace_rdev_join_mesh)(void *, struct wiphy *, struct net_device *, const struct mesh_config *, const struct mesh_setup *);\n\ntypedef void (*btf_trace_rdev_join_ocb)(void *, struct wiphy *, struct net_device *, const struct ocb_setup *);\n\ntypedef void (*btf_trace_rdev_leave_ibss)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_leave_mesh)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_leave_ocb)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_libertas_set_mesh_channel)(void *, struct wiphy *, struct net_device *, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_rdev_mgmt_tx)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_mgmt_tx_params *);\n\ntypedef void (*btf_trace_rdev_mgmt_tx_cancel_wait)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_mod_link_station)(void *, struct wiphy *, struct net_device *, struct link_station_parameters *);\n\ntypedef void (*btf_trace_rdev_nan_change_conf)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *, u32);\n\ntypedef void (*btf_trace_rdev_probe_client)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_probe_mesh_link)(void *, struct wiphy *, struct net_device *, const u8 *, const u8 *, size_t);\n\ntypedef void (*btf_trace_rdev_remain_on_channel)(void *, struct wiphy *, struct wireless_dev *, struct ieee80211_channel *, unsigned int);\n\ntypedef void (*btf_trace_rdev_reset_tid_config)(void *, struct wiphy *, struct net_device *, const u8 *, u8);\n\ntypedef void (*btf_trace_rdev_resume)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_rdev_return_chandef)(void *, struct wiphy *, int, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_return_int)(void *, struct wiphy *, int);\n\ntypedef void (*btf_trace_rdev_return_int_cookie)(void *, struct wiphy *, int, u64);\n\ntypedef void (*btf_trace_rdev_return_int_int)(void *, struct wiphy *, int, int);\n\ntypedef void (*btf_trace_rdev_return_int_mesh_config)(void *, struct wiphy *, int, struct mesh_config *);\n\ntypedef void (*btf_trace_rdev_return_int_mpath_info)(void *, struct wiphy *, int, struct mpath_info *);\n\ntypedef void (*btf_trace_rdev_return_int_station_info)(void *, struct wiphy *, int, struct station_info *);\n\ntypedef void (*btf_trace_rdev_return_int_survey_info)(void *, struct wiphy *, int, struct survey_info *);\n\ntypedef void (*btf_trace_rdev_return_int_tx_rx)(void *, struct wiphy *, int, u32, u32);\n\ntypedef void (*btf_trace_rdev_return_void)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_rdev_return_void_tx_rx)(void *, struct wiphy *, u32, u32, u32, u32);\n\ntypedef void (*btf_trace_rdev_return_wdev)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_rfkill_poll)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_rdev_scan)(void *, struct wiphy *, struct cfg80211_scan_request_int *);\n\ntypedef void (*btf_trace_rdev_sched_scan_start)(void *, struct wiphy *, struct net_device *, u64);\n\ntypedef void (*btf_trace_rdev_sched_scan_stop)(void *, struct wiphy *, struct net_device *, u64);\n\ntypedef void (*btf_trace_rdev_set_antenna)(void *, struct wiphy *, int, u32, u32);\n\ntypedef void (*btf_trace_rdev_set_ap_chanwidth)(void *, struct wiphy *, struct net_device *, unsigned int, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_set_bitrate_mask)(void *, struct wiphy *, struct net_device *, unsigned int, const u8 *, const struct cfg80211_bitrate_mask *);\n\ntypedef void (*btf_trace_rdev_set_coalesce)(void *, struct wiphy *, struct cfg80211_coalesce *);\n\ntypedef void (*btf_trace_rdev_set_cqm_rssi_config)(void *, struct wiphy *, struct net_device *, s32, u32);\n\ntypedef void (*btf_trace_rdev_set_cqm_rssi_range_config)(void *, struct wiphy *, struct net_device *, s32, s32);\n\ntypedef void (*btf_trace_rdev_set_cqm_txe_config)(void *, struct wiphy *, struct net_device *, u32, u32, u32);\n\ntypedef void (*btf_trace_rdev_set_default_beacon_key)(void *, struct wiphy *, struct net_device *, int, u8);\n\ntypedef void (*btf_trace_rdev_set_default_key)(void *, struct wiphy *, struct net_device *, int, u8, bool, bool);\n\ntypedef void (*btf_trace_rdev_set_default_mgmt_key)(void *, struct wiphy *, struct net_device *, int, u8);\n\ntypedef void (*btf_trace_rdev_set_epcs)(void *, struct wiphy *, struct net_device *, bool);\n\ntypedef void (*btf_trace_rdev_set_fils_aad)(void *, struct wiphy *, struct net_device *, struct cfg80211_fils_aad *);\n\ntypedef void (*btf_trace_rdev_set_hw_timestamp)(void *, struct wiphy *, struct net_device *, struct cfg80211_set_hw_timestamp *);\n\ntypedef void (*btf_trace_rdev_set_mac_acl)(void *, struct wiphy *, struct net_device *, struct cfg80211_acl_data *);\n\ntypedef void (*btf_trace_rdev_set_mcast_rate)(void *, struct wiphy *, struct net_device *, int *);\n\ntypedef void (*btf_trace_rdev_set_monitor_channel)(void *, struct wiphy *, struct net_device *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_set_multicast_to_unicast)(void *, struct wiphy *, struct net_device *, const bool);\n\ntypedef void (*btf_trace_rdev_set_noack_map)(void *, struct wiphy *, struct net_device *, u16);\n\ntypedef void (*btf_trace_rdev_set_pmk)(void *, struct wiphy *, struct net_device *, struct cfg80211_pmk_conf *);\n\ntypedef void (*btf_trace_rdev_set_pmksa)(void *, struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\ntypedef void (*btf_trace_rdev_set_power_mgmt)(void *, struct wiphy *, struct net_device *, bool, int);\n\ntypedef void (*btf_trace_rdev_set_qos_map)(void *, struct wiphy *, struct net_device *, struct cfg80211_qos_map *);\n\ntypedef void (*btf_trace_rdev_set_radar_background)(void *, struct wiphy *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_set_rekey_data)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_set_sar_specs)(void *, struct wiphy *, struct cfg80211_sar_specs *);\n\ntypedef void (*btf_trace_rdev_set_tid_config)(void *, struct wiphy *, struct net_device *, struct cfg80211_tid_config *);\n\ntypedef void (*btf_trace_rdev_set_ttlm)(void *, struct wiphy *, struct net_device *, struct cfg80211_ttlm_params *);\n\ntypedef void (*btf_trace_rdev_set_tx_power)(void *, struct wiphy *, struct wireless_dev *, int, enum nl80211_tx_power_setting, int);\n\ntypedef void (*btf_trace_rdev_set_txq_params)(void *, struct wiphy *, struct net_device *, struct ieee80211_txq_params *);\n\ntypedef void (*btf_trace_rdev_set_wakeup)(void *, struct wiphy *, bool);\n\ntypedef void (*btf_trace_rdev_set_wiphy_params)(void *, struct wiphy *, int, u32);\n\ntypedef void (*btf_trace_rdev_start_ap)(void *, struct wiphy *, struct net_device *, struct cfg80211_ap_settings *);\n\ntypedef void (*btf_trace_rdev_start_nan)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *);\n\ntypedef void (*btf_trace_rdev_start_p2p_device)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_start_pmsr)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_start_radar_detection)(void *, struct wiphy *, struct net_device *, struct cfg80211_chan_def *, u32, int);\n\ntypedef void (*btf_trace_rdev_stop_ap)(void *, struct wiphy *, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_rdev_stop_nan)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_stop_p2p_device)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_suspend)(void *, struct wiphy *, struct cfg80211_wowlan *);\n\ntypedef void (*btf_trace_rdev_tdls_cancel_channel_switch)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_tdls_channel_switch)(void *, struct wiphy *, struct net_device *, const u8 *, u8, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_tdls_mgmt)(void *, struct wiphy *, struct net_device *, u8 *, int, u8, u8, u16, u32, bool, const u8 *, size_t);\n\ntypedef void (*btf_trace_rdev_tdls_oper)(void *, struct wiphy *, struct net_device *, u8 *, enum nl80211_tdls_operation);\n\ntypedef void (*btf_trace_rdev_tx_control_port)(void *, struct wiphy *, struct net_device *, const u8 *, size_t, const u8 *, __be16, bool, int);\n\ntypedef void (*btf_trace_rdev_update_connect_params)(void *, struct wiphy *, struct net_device *, struct cfg80211_connect_params *, u32);\n\ntypedef void (*btf_trace_rdev_update_ft_ies)(void *, struct wiphy *, struct net_device *, struct cfg80211_update_ft_ies_params *);\n\ntypedef void (*btf_trace_rdev_update_mesh_config)(void *, struct wiphy *, struct net_device *, u32, const struct mesh_config *);\n\ntypedef void (*btf_trace_rdev_update_mgmt_frame_registrations)(void *, struct wiphy *, struct wireless_dev *, struct mgmt_frame_regs *);\n\ntypedef void (*btf_trace_rdev_update_owe_info)(void *, struct wiphy *, struct net_device *, struct cfg80211_update_owe_info *);\n\ntypedef void (*btf_trace_rdpmc)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_read_msr)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_regcache_drop_region)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regcache_sync)(void *, struct regmap *, const char *, const char *);\n\ntypedef void (*btf_trace_regmap_async_complete_done)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_start)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_io_complete)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_bulk_read)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_bulk_write)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_cache_bypass)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_cache_only)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_hw_read_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_read_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_reg_read)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read_cache)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_write)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_reschedule_entry)(void *, int);\n\ntypedef void (*btf_trace_reschedule_exit)(void *, int);\n\ntypedef void (*btf_trace_rpc__auth_tooweak)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__bad_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__garbage_args)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__proc_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__stale_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__unparsable)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_callhdr)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_verifier)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_buf_alloc)(void *, const struct rpc_task *, int);\n\ntypedef void (*btf_trace_rpc_call_rpcerror)(void *, const struct rpc_task *, int, int);\n\ntypedef void (*btf_trace_rpc_call_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_clnt_clone_err)(void *, const struct rpc_clnt *, int);\n\ntypedef void (*btf_trace_rpc_clnt_free)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_killall)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_new)(void *, const struct rpc_clnt *, const struct rpc_xprt *, const struct rpc_create_args *);\n\ntypedef void (*btf_trace_rpc_clnt_new_err)(void *, const char *, const char *, int);\n\ntypedef void (*btf_trace_rpc_clnt_release)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt_err)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_shutdown)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_connect_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_request)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_retry_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_socket_close)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_connect)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_error)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_nospace)(void *, const struct rpc_rqst *, const struct sock_xprt *);\n\ntypedef void (*btf_trace_rpc_socket_reset_connection)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_shutdown)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_state_change)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_stats_latency)(void *, const struct rpc_task *, ktime_t, ktime_t, ktime_t);\n\ntypedef void (*btf_trace_rpc_task_begin)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_call_done)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_complete)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_end)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_run_action)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_signalled)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sleep)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_task_sync_sleep)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sync_wake)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_timeout)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_wakeup)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_timeout_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_tls_not_started)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_tls_unavailable)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_xdr_alignment)(void *, const struct xdr_stream *, size_t, unsigned int);\n\ntypedef void (*btf_trace_rpc_xdr_overflow)(void *, const struct xdr_stream *, size_t);\n\ntypedef void (*btf_trace_rpc_xdr_recvfrom)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_reply_pages)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_sendto)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpcb_bind_version_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_getport)(void *, const struct rpc_clnt *, const struct rpc_task *, unsigned int);\n\ntypedef void (*btf_trace_rpcb_prog_unavail_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_register)(void *, u32, u32, const char *, const char *);\n\ntypedef void (*btf_trace_rpcb_setport)(void *, const struct rpc_task *, int, short unsigned int);\n\ntypedef void (*btf_trace_rpcb_timeout_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unreachable_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unrecognized_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unregister)(void *, u32, u32, const char *);\n\ntypedef void (*btf_trace_rpcgss_bad_seqno)(void *, const struct rpc_task *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_context)(void *, u32, long unsigned int, long unsigned int, unsigned int, unsigned int, const u8 *);\n\ntypedef void (*btf_trace_rpcgss_createauth)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rpcgss_ctx_destroy)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_ctx_init)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_get_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_import_ctx)(void *, int);\n\ntypedef void (*btf_trace_rpcgss_need_reencode)(void *, const struct rpc_task *, u32, bool);\n\ntypedef void (*btf_trace_rpcgss_oid_to_mech)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_seqno)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_svc_accept_upcall)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_authenticate)(void *, const struct svc_rqst *, const struct rpc_gss_wire_cred *);\n\ntypedef void (*btf_trace_rpcgss_svc_get_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_bad)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_large)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_low)(void *, const struct svc_rqst *, u32, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_seen)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_unwrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_unwrap_failed)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_upcall_msg)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_upcall_result)(void *, u32, int);\n\ntypedef void (*btf_trace_rpcgss_update_slack)(void *, const struct rpc_task *, const struct rpc_auth *);\n\ntypedef void (*btf_trace_rpcgss_verify_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_wrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpm_idle)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_resume)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_return_int)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_rpm_status)(void *, struct device *, enum rpm_status);\n\ntypedef void (*btf_trace_rpm_suspend)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_usage)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int);\n\ntypedef void (*btf_trace_rtc_alarm_irq_enable)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_freq)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_state)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_read_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_read_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_set_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_timer_dequeue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_enqueue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_fired)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sched_compute_energy_tp)(void *, struct task_struct *, int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_sched_cpu_capacity_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_sched_entry_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_exit_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_ext_bypass_lb)(void *, __u32, __u32, __u32, __u32, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_sched_ext_dump)(void *, const char *);\n\ntypedef void (*btf_trace_sched_ext_event)(void *, const char *, __s64);\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_end)(void *, struct kthread_work *, kthread_work_func_t);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_start)(void *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_kthread_work_queue_work)(void *, struct kthread_worker *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_move_numa)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_overutilized_tp)(void *, struct root_domain *, bool);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_prepare_exec)(void *, struct task_struct *, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_set_need_resched_tp)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_skip_cpuset_numa)(void *, struct task_struct *, nodemask_t *);\n\ntypedef void (*btf_trace_sched_skip_vma_numa)(void *, struct mm_struct *, struct vm_area_struct *, enum numa_vmaskip_reason);\n\ntypedef void (*btf_trace_sched_stat_blocked)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_iowait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_sleep)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_wait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stick_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_swap_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *, unsigned int);\n\ntypedef void (*btf_trace_sched_update_nr_running_tp)(void *, struct rq *, int);\n\ntypedef void (*btf_trace_sched_util_est_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_sched_util_est_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\ntypedef void (*btf_trace_selinux_audited)(void *, struct selinux_audit_data *, char *, char *, const char *);\n\ntypedef void (*btf_trace_set_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sk_data_ready)(void *, const struct sock *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_smbus_read)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int);\n\ntypedef void (*btf_trace_smbus_reply)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *, int);\n\ntypedef void (*btf_trace_smbus_result)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, int);\n\ntypedef void (*btf_trace_smbus_write)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *);\n\ntypedef void (*btf_trace_snd_hdac_stream_start)(void *, struct hdac_bus *, struct hdac_stream *);\n\ntypedef void (*btf_trace_snd_hdac_stream_stop)(void *, struct hdac_bus *, struct hdac_stream *);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_recv_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_sock_send_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\ntypedef void (*btf_trace_spurious_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_spurious_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_stop_queue)(void *, struct ieee80211_local *, u16, enum queue_stop_reason, int);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_svc_alloc_arg_err)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_svc_authenticate)(void *, const struct svc_rqst *, enum svc_auth_status);\n\ntypedef void (*btf_trace_svc_defer)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_defer_drop)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_queue)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_recv)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_drop)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_noregister)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_pool_thread_noidle)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_running)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_wake)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_process)(void *, const struct svc_rqst *, const char *);\n\ntypedef void (*btf_trace_svc_register)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_replace_page_err)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_send)(void *, const struct svc_rqst *, int);\n\ntypedef void (*btf_trace_svc_stats_latency)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_tls_not_started)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_start)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_timed_out)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_unavailable)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_upcall)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_unregister)(void *, const char *, const u32, int);\n\ntypedef void (*btf_trace_svc_xdr_recvfrom)(void *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xdr_sendto)(void *, __be32, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xprt_accept)(void *, const struct svc_xprt *, const char *);\n\ntypedef void (*btf_trace_svc_xprt_close)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_create_err)(void *, const char *, const char *, struct sockaddr *, size_t, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_dequeue)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_xprt_detach)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_enqueue)(void *, const struct svc_xprt *, long unsigned int);\n\ntypedef void (*btf_trace_svc_xprt_free)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_no_write_space)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svcsock_accept_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_data_ready)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_free)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_getpeername_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_marker)(void *, const struct svc_xprt *, __be32);\n\ntypedef void (*btf_trace_svcsock_new)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_tcp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_eagain)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_short)(void *, const struct svc_xprt *, u32, u32);\n\ntypedef void (*btf_trace_svcsock_tcp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_state)(void *, const struct svc_xprt *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_udp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_write_space)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_swiotlb_bounced)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_task_prctl_unknown)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef void (*btf_trace_tasklet_entry)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tasklet_exit)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tcp_ao_handshake_failure)(void *, const struct sock *, const struct sk_buff *, const __u8, const __u8, const __u8);\n\ntypedef void (*btf_trace_tcp_bad_csum)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_cong_state_set)(void *, struct sock *, const u8);\n\ntypedef void (*btf_trace_tcp_cwnd_reduction_tp)(void *, const struct sock *, int, int, int);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_hash_ao_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_bad_header)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_mismatch)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_unexpected)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *, const enum sk_rst_reason);\n\ntypedef void (*btf_trace_tcp_sendmsg_locked)(void *, const struct sock *, const struct msghdr *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_thermal_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_thermal_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_thermal_temperature)(void *, struct thermal_zone_device *);\n\ntypedef void (*btf_trace_thermal_zone_trip)(void *, struct thermal_zone_device *, int, enum thermal_trip_type);\n\ntypedef void (*btf_trace_threshold_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_threshold_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_timer_base_idle)(void *, bool, unsigned int);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_tlb_flush)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_tls_alert_recv)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_alert_send)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_contenttype)(void *, const struct sock *, unsigned char);\n\ntypedef void (*btf_trace_tmigr_connect_child_parent)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_connect_cpu_parent)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_active)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_available)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_unavailable)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_group_set)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_active)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_inactive)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_handle_remote)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_handle_remote_cpu)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_update_events)(void *, struct tmigr_group *, struct tmigr_group *, union tmigr_state, union tmigr_state, u64);\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_usb_alloc_dev)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_usb_set_device_state)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_vector_activate)(void *, unsigned int, bool, bool, bool);\n\ntypedef void (*btf_trace_vector_alloc)(void *, unsigned int, unsigned int, bool, int);\n\ntypedef void (*btf_trace_vector_alloc_managed)(void *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_vector_clear)(void *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_vector_config)(void *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_vector_deactivate)(void *, unsigned int, bool, bool, bool);\n\ntypedef void (*btf_trace_vector_free_moved)(void *, unsigned int, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_vector_reserve)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_vector_reserve_managed)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_vector_setup)(void *, unsigned int, bool, int);\n\ntypedef void (*btf_trace_vector_teardown)(void *, unsigned int, bool, bool);\n\ntypedef void (*btf_trace_vector_update)(void *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_virtio_gpu_cmd_queue)(void *, struct virtqueue *, struct virtio_gpu_ctrl_hdr *, u32);\n\ntypedef void (*btf_trace_virtio_gpu_cmd_response)(void *, struct virtqueue *, struct virtio_gpu_ctrl_hdr *, u32);\n\ntypedef void (*btf_trace_vlv_fifo_size)(void *, struct intel_crtc *, u32, u32, u32);\n\ntypedef void (*btf_trace_vlv_wm)(void *, struct intel_crtc *, const struct vlv_wm_values *);\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\ntypedef void (*btf_trace_wake_queue)(void *, struct ieee80211_local *, u16, enum queue_stop_reason, int);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_wiphy_delayed_work_queue)(void *, struct wiphy *, struct wiphy_work *, long unsigned int);\n\ntypedef void (*btf_trace_wiphy_hrtimer_work_queue)(void *, struct wiphy *, struct wiphy_work *, ktime_t);\n\ntypedef void (*btf_trace_wiphy_work_cancel)(void *, struct wiphy *, struct wiphy_work *);\n\ntypedef void (*btf_trace_wiphy_work_flush)(void *, struct wiphy *, struct wiphy_work *);\n\ntypedef void (*btf_trace_wiphy_work_queue)(void *, struct wiphy *, struct wiphy_work *);\n\ntypedef void (*btf_trace_wiphy_work_run)(void *, struct wiphy *, struct wiphy_work *);\n\ntypedef void (*btf_trace_wiphy_work_worker_start)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_write_msr)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_dirty_folio)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, long unsigned int, int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_x86_fpu_after_save)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_before_save)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_copy_dst)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_dropped)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_regs_activated)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_regs_deactivated)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_xstate_check_failed)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_platform_ipi_entry)(void *, int);\n\ntypedef void (*btf_trace_x86_platform_ipi_exit)(void *, int);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int, struct xdp_cpumap_stats *);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xhci_add_endpoint)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctx)(void *, struct xhci_hcd *, struct xhci_container_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_stream_info_ctx)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_alloc_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_dbc_alloc_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_free_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_gadget_ep_queue)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_giveback_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_queue_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbg_address)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_cancel_urb)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_context_change)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_init)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_quirks)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_reset_ep)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_ring_expansion)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_discover_or_reset_device)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_get_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_cmd_addr_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_config_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_disable_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_stream)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_handle_cmd_stop_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_command)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_hub_status_data)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_inc_deq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_inc_enq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_portsc_writel)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_queue_trb)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_ring_alloc)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_ep_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_ring_expansion)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_free)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_host_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_setup_addressable_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_stop_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_urb_dequeue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_enqueue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_giveback)(void *, struct urb *);\n\ntypedef void (*btf_trace_xprt_connect)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_create)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_destroy)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_auto)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_done)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_force)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_get_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_lookup_rqst)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_ping)(void *, const struct rpc_xprt *, int);\n\ntypedef void (*btf_trace_xprt_put_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_reserve_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_retransmit)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_timer)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_transmit)(void *, const struct rpc_rqst *, int);\n\ntypedef void (*btf_trace_xs_data_ready)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xs_stream_read_data)(void *, struct rpc_xprt *, ssize_t, size_t);\n\ntypedef void (*btf_trace_xs_stream_read_request)(void *, struct sock_xprt *);\n\ntypedef int (*cb_t)(struct param *);\n\ntypedef bool (*check_reserved_t)(u64, u64, enum e820_type);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef struct sk_buff * (*codel_skb_dequeue_t)(struct codel_vars *, void *);\n\ntypedef void (*codel_skb_drop_t)(struct sk_buff *, void *);\n\ntypedef u32 (*codel_skb_len_t)(const struct sk_buff *);\n\ntypedef codel_time_t (*codel_skb_time_t)(const struct sk_buff *);\n\ntypedef void (*companion_fn)(struct pci_dev *, struct usb_hcd *, struct pci_dev *, struct usb_hcd *);\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\ntypedef int (*copy_fn_t)(void *, const void *, u32, struct task_struct *);\n\ntypedef int (*cppc_mode_transition_fn)(int);\n\ntypedef void detailed_cb(const struct detailed_timing *, void *);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef void (*drm_crtc_set_lut_func)(struct drm_crtc *, unsigned int, u16, u16, u16);\n\ntypedef int drm_ioctl_compat_t(struct file *, unsigned int, long unsigned int);\n\ntypedef bool (*drm_vblank_get_scanout_position_func)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\ntypedef int (*efi_memattr_perm_setter)(struct mm_struct *, efi_memory_desc_t *, bool);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\ntypedef void ext4_update_sb_callback(struct ext4_sb_info *, struct ext4_super_block *, const void *);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, struct mm_struct *);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\ntypedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *, const u8 *);\n\ntypedef bool fq_skb_filter_t(struct fq *, struct fq_tin *, struct fq_flow *, struct sk_buff *, void *);\n\ntypedef void fq_skb_free_t(struct fq *, struct fq_tin *, struct fq_flow *, struct sk_buff *);\n\ntypedef struct sk_buff *fq_tin_dequeue_t(struct fq *, struct fq_tin *, struct fq_flow *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef bool (*hid_usage_cmp_t)(struct hid_usage *, unsigned int, unsigned int);\n\ntypedef u32 (*hotplug_enables_func)(struct intel_encoder *);\n\ntypedef u32 (*hotplug_mask_func)(enum hpd_pin);\n\ntypedef bool (*i8042_filter_t)(unsigned char, unsigned char, struct serio *, void *);\n\ntypedef int (*i915_user_extension_fn)(struct i915_user_extension *, void *);\n\ntypedef u32 inet6_ehashfn_t(const struct net *, const struct in6_addr *, const u16, const struct in6_addr *, const __be16);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef int (*ioctl_fn)(struct file *, struct autofs_sb_info *, struct autofs_dev_ioctl *);\n\ntypedef int (*ioctl_fn___2)(struct file *, struct dm_ioctl *, size_t);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *, const struct inet6_skb_parm *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef int (*map_follower_func_t)(struct hda_codec *, void *, struct snd_kcontrol *);\n\ntypedef void (*mapped_f)(struct perf_event *, struct mm_struct *);\n\ntypedef void modeset_stuck_fn(void *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*nlm_host_match_fn_t)(void *, struct nlm_host *);\n\ntypedef void (*nmi_shootdown_cb)(int, struct pt_regs *);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef int (*pcie_callback_t)(struct pcie_device *);\n\ntypedef int (*pcm_transfer_f)(struct snd_pcm_substream *, int, long unsigned int, struct iov_iter *, long unsigned int);\n\ntypedef int (*pcm_copy_f)(struct snd_pcm_substream *, snd_pcm_uframes_t, void *, snd_pcm_uframes_t, snd_pcm_uframes_t, pcm_transfer_f, bool);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\ntypedef int perf_snapshot_branch_stack_t(struct perf_branch_entry *, unsigned int);\n\ntypedef int (*pm_callback_t)(struct device *);\n\ntypedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);\n\ntypedef struct rt6_info * (*pol_lookup_t)(struct net *, struct fib6_table *, struct flowi6 *, const struct sk_buff *, int);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef bool (*pps_check)(struct intel_display *, int);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef int (*pt_level_fn_t)(struct pt_range *, void *, unsigned int, struct pt_table_p *);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\ntypedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\ntypedef int read_block_fn(void *, u8 *, unsigned int, size_t);\n\ntypedef long unsigned int relocate_kernel_fn(long unsigned int, long unsigned int, long unsigned int, unsigned int);\n\ntypedef int (*reset_func)(struct intel_gt *, intel_engine_mask_t, unsigned int);\n\ntypedef void (*rethook_handler_t)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\ntypedef bool (*ring_buffer_cond_fn)(void *);\n\ntypedef void (*rpc_action)(struct rpc_task *);\n\ntypedef irqreturn_t (*rtc_irq_handler)(int, void *);\n\ntypedef void (*rtl_generic_fct)(struct rtl8169_private *);\n\ntypedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *, struct phy_device *);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef void (*set_debug_port_t)(int);\n\ntypedef void (*setup_fn)(struct perf_event *, struct pt_regs *, void *, struct perf_sample_data *, struct pt_regs *);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int (*snd_seq_dump_func_t)(void *, void *, int);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef long int (*sys_call_ptr_t)(const struct pt_regs *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef void text_poke_f(void *, const void *, size_t);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef int (*trace_user_buf_copy)(char *, const char *, size_t, void *);\n\ntypedef struct sk_buff * (*udp_gro_receive_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*uprobe_write_verify_t)(struct page *, long unsigned int, uprobe_opcode_t *, int, void *);\n\ntypedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *);\n\ntypedef u32 * (*wa_bb_func_t)(struct intel_engine_cs *, u32 *);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);\n\ntypedef struct rpc_xprt * (*xprt_switch_find_xprt_t)(struct rpc_xprt_switch *, const struct rpc_xprt *);\n\nstruct nf_bridge_frag_data;\n\nstruct ftrace_regs;\n\nstruct bpf_iter;\n\nstruct fscrypt_inode_info;\n\nstruct virtio_gpu_command;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern void __attribute__((address_space(1))) *bpf_arena_alloc_pages(void *p__map, void __attribute__((address_space(1))) *addr__ign, u32 page_cnt, int node_id, u64 flags) __weak __ksym;\nextern void bpf_arena_free_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern int bpf_arena_reserve_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern struct cgroup *bpf_cgroup_from_id(u64 cgid) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_task_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_ct_change_status(struct nf_conn *nfct, u32 status) __weak __ksym;\nextern int bpf_ct_change_timeout(struct nf_conn *nfct, u32 timeout) __weak __ksym;\nextern struct nf_conn *bpf_ct_insert_entry(struct nf_conn___init *nfct_i) __weak __ksym;\nextern void bpf_ct_release(struct nf_conn *nfct) __weak __ksym;\nextern int bpf_ct_set_nat_info(struct nf_conn___init *nfct, union nf_inet_addr *addr, int port, enum nf_nat_manip_type manip) __weak __ksym;\nextern int bpf_ct_set_status(const struct nf_conn___init *nfct, u32 status) __weak __ksym;\nextern void bpf_ct_set_timeout(struct nf_conn___init *nfct, u32 timeout) __weak __ksym;\nextern int bpf_dynptr_adjust(const struct bpf_dynptr *p, u64 start, u64 end) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_copy(struct bpf_dynptr *dst_ptr, u64 dst_off, struct bpf_dynptr *src_ptr, u64 src_off, u64 size) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb(struct __sk_buff *s, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb_meta(struct __sk_buff *skb_, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_xdp(struct xdp_md *x, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_dynptr_memset(struct bpf_dynptr *p, u64 offset, u64 size, u8 val) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern void *bpf_dynptr_slice(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern void *bpf_dynptr_slice_rdwr(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern struct kmem_cache *bpf_get_kmem_cache(u64 addr) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern int bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it, struct task_struct *task, u64 addr) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern struct bpf_key *bpf_lookup_system_key(u64 id) __weak __ksym;\nextern struct bpf_key *bpf_lookup_user_key(s32 serial, u64 flags) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_percpu_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern int bpf_probe_read_kernel_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_kernel_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_send_signal_task(struct task_struct *task, int sig, enum pid_type type, u64 value) __weak __ksym;\nextern __u64 *bpf_session_cookie(void *ctx) __weak __ksym;\nextern bool bpf_session_is_return(void *ctx) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern struct nf_conn___init *bpf_skb_ct_alloc(struct __sk_buff *skb_ctx, struct bpf_sock_tuple *bpf_tuple, u32 tuple__sz, struct bpf_ct_opts *opts, u32 opts__sz) __weak __ksym;\nextern struct nf_conn *bpf_skb_ct_lookup(struct __sk_buff *skb_ctx, struct bpf_sock_tuple *bpf_tuple, u32 tuple__sz, struct bpf_ct_opts *opts, u32 opts__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_sock_ops_enable_tx_tstamp(struct bpf_sock_ops_kern *skops, u64 flags) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern void bpf_throw(u64 cookie) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_verify_pkcs7_signature(struct bpf_dynptr *data_p, struct bpf_dynptr *sig_p, struct bpf_key *trusted_keyring) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern struct nf_conn___init *bpf_xdp_ct_alloc(struct xdp_md *xdp_ctx, struct bpf_sock_tuple *bpf_tuple, u32 tuple__sz, struct bpf_ct_opts *opts, u32 opts__sz) __weak __ksym;\nextern struct nf_conn *bpf_xdp_ct_lookup(struct xdp_md *xdp_ctx, struct bpf_sock_tuple *bpf_tuple, u32 tuple__sz, struct bpf_ct_opts *opts, u32 opts__sz) __weak __ksym;\nextern struct xfrm_state *bpf_xdp_get_xfrm_state(struct xdp_md *ctx, struct bpf_xfrm_state_opts *opts, u32 opts__sz) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void bpf_xdp_xfrm_state_release(struct xfrm_state *x) __weak __ksym;\nextern void crash_kexec(struct pt_regs *regs) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __weak __ksym;\nextern void scx_bpf_destroy_dsq(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_insert___v2(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local(u64 dsq_id) __weak __ksym;\nextern bool scx_bpf_dsq_move_vtime(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __weak __ksym;\nextern struct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern void scx_bpf_exit_bstr(s64 exit_code, char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern void scx_bpf_kick_cpu(s32 cpu, u64 flags) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern s32 scx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags, const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __weak __ksym;\nextern bool scx_bpf_sub_dispatch(u64 cgroup_id) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime) __weak __ksym;\nextern bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n#pragma clang diagnostic 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\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x000000000\x000000000\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wmissing-declarations\"\n#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tACOMP_WALK_SLEEP = 1,\n\tACOMP_WALK_SRC_LINEAR = 2,\n\tACOMP_WALK_DST_LINEAR = 4,\n};\n\nenum {\n\tACPI_BATTERY_ALARM_PRESENT = 0,\n\tACPI_BATTERY_XINFO_PRESENT = 1,\n\tACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY = 2,\n\tACPI_BATTERY_QUIRK_THINKPAD_MAH = 3,\n\tACPI_BATTERY_QUIRK_DEGRADED_FULL_CHARGE = 4,\n};\n\nenum {\n\tACPI_BUTTON_LID_INIT_IGNORE = 0,\n\tACPI_BUTTON_LID_INIT_OPEN = 1,\n\tACPI_BUTTON_LID_INIT_METHOD = 2,\n\tACPI_BUTTON_LID_INIT_DISABLED = 3,\n};\n\nenum {\n\tACPI_GENL_ATTR_UNSPEC = 0,\n\tACPI_GENL_ATTR_EVENT = 1,\n\t__ACPI_GENL_ATTR_MAX = 2,\n};\n\nenum {\n\tACPI_GENL_CMD_UNSPEC = 0,\n\tACPI_GENL_CMD_EVENT = 1,\n\t__ACPI_GENL_CMD_MAX = 2,\n};\n\nenum {\n\tACPI_REFCLASS_LOCAL = 0,\n\tACPI_REFCLASS_ARG = 1,\n\tACPI_REFCLASS_REFOF = 2,\n\tACPI_REFCLASS_INDEX = 3,\n\tACPI_REFCLASS_TABLE = 4,\n\tACPI_REFCLASS_NAME = 5,\n\tACPI_REFCLASS_DEBUG = 6,\n\tACPI_REFCLASS_MAX = 6,\n};\n\nenum {\n\tACPI_RSC_INITGET = 0,\n\tACPI_RSC_INITSET = 1,\n\tACPI_RSC_FLAGINIT = 2,\n\tACPI_RSC_1BITFLAG = 3,\n\tACPI_RSC_2BITFLAG = 4,\n\tACPI_RSC_3BITFLAG = 5,\n\tACPI_RSC_6BITFLAG = 6,\n\tACPI_RSC_ADDRESS = 7,\n\tACPI_RSC_BITMASK = 8,\n\tACPI_RSC_BITMASK16 = 9,\n\tACPI_RSC_COUNT = 10,\n\tACPI_RSC_COUNT16 = 11,\n\tACPI_RSC_COUNT_GPIO_PIN = 12,\n\tACPI_RSC_COUNT_GPIO_RES = 13,\n\tACPI_RSC_COUNT_GPIO_VEN = 14,\n\tACPI_RSC_COUNT_SERIAL_RES = 15,\n\tACPI_RSC_COUNT_SERIAL_VEN = 16,\n\tACPI_RSC_DATA8 = 17,\n\tACPI_RSC_EXIT_EQ = 18,\n\tACPI_RSC_EXIT_LE = 19,\n\tACPI_RSC_EXIT_NE = 20,\n\tACPI_RSC_LENGTH = 21,\n\tACPI_RSC_MOVE_GPIO_PIN = 22,\n\tACPI_RSC_MOVE_GPIO_RES = 23,\n\tACPI_RSC_MOVE_SERIAL_RES = 24,\n\tACPI_RSC_MOVE_SERIAL_VEN = 25,\n\tACPI_RSC_MOVE8 = 26,\n\tACPI_RSC_MOVE16 = 27,\n\tACPI_RSC_MOVE32 = 28,\n\tACPI_RSC_MOVE64 = 29,\n\tACPI_RSC_SET8 = 30,\n\tACPI_RSC_SOURCE = 31,\n\tACPI_RSC_SOURCEX = 32,\n};\n\nenum {\n\tACPI_RSD_TITLE = 0,\n\tACPI_RSD_1BITFLAG = 1,\n\tACPI_RSD_2BITFLAG = 2,\n\tACPI_RSD_3BITFLAG = 3,\n\tACPI_RSD_6BITFLAG = 4,\n\tACPI_RSD_ADDRESS = 5,\n\tACPI_RSD_DWORDLIST = 6,\n\tACPI_RSD_LITERAL = 7,\n\tACPI_RSD_LONGLIST = 8,\n\tACPI_RSD_SHORTLIST = 9,\n\tACPI_RSD_SHORTLISTX = 10,\n\tACPI_RSD_SOURCE = 11,\n\tACPI_RSD_STRING = 12,\n\tACPI_RSD_UINT8 = 13,\n\tACPI_RSD_UINT16 = 14,\n\tACPI_RSD_UINT32 = 15,\n\tACPI_RSD_UINT64 = 16,\n\tACPI_RSD_WORDLIST = 17,\n\tACPI_RSD_LABEL = 18,\n\tACPI_RSD_SOURCE_LABEL = 19,\n};\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DMPS = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_CPD = 1048576,\n\tPORT_CMD_MPSP = 524288,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_CMD_CAP = 8126464,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_SUSPEND_PHYS = 33554432,\n\tAHCI_HFLAG_NO_SXS = 67108864,\n\tAHCI_HFLAG_43BIT_ONLY = 134217728,\n\tAHCI_HFLAG_INTEL_PCS_QUIRK = 268435456,\n\tAHCI_HFLAG_ATAPI_DMA_QUIRK = 536870912,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 15,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum {\n\tALE_ENT_VID_MEMBER_LIST = 0,\n\tALE_ENT_VID_UNREG_MCAST_MSK = 1,\n\tALE_ENT_VID_REG_MCAST_MSK = 2,\n\tALE_ENT_VID_FORCE_UNTAGGED_MSK = 3,\n\tALE_ENT_VID_UNREG_MCAST_IDX = 4,\n\tALE_ENT_VID_REG_MCAST_IDX = 5,\n\tALE_ENT_VID_LAST = 6,\n};\n\nenum {\n\tAM62A7_EFUSE_M_MPU_OPP = 13,\n\tAM62A7_EFUSE_N_MPU_OPP = 14,\n\tAM62A7_EFUSE_O_MPU_OPP = 15,\n\tAM62A7_EFUSE_P_MPU_OPP = 16,\n\tAM62A7_EFUSE_Q_MPU_OPP = 17,\n\tAM62A7_EFUSE_R_MPU_OPP = 18,\n\tAM62A7_EFUSE_S_MPU_OPP = 19,\n\tAM62A7_EFUSE_V_MPU_OPP = 20,\n\tAM62A7_EFUSE_U_MPU_OPP = 21,\n\tAM62A7_EFUSE_T_MPU_OPP = 22,\n};\n\nenum {\n\tAM65_CPSW_REGDUMP_MOD_NUSS = 1,\n\tAM65_CPSW_REGDUMP_MOD_RGMII_STATUS = 2,\n\tAM65_CPSW_REGDUMP_MOD_MDIO = 3,\n\tAM65_CPSW_REGDUMP_MOD_CPSW = 4,\n\tAM65_CPSW_REGDUMP_MOD_CPSW_P0 = 5,\n\tAM65_CPSW_REGDUMP_MOD_CPSW_P1 = 6,\n\tAM65_CPSW_REGDUMP_MOD_CPSW_CPTS = 7,\n\tAM65_CPSW_REGDUMP_MOD_CPSW_ALE = 8,\n\tAM65_CPSW_REGDUMP_MOD_CPSW_ALE_TBL = 9,\n\tAM65_CPSW_REGDUMP_MOD_LAST = 10,\n};\n\nenum {\n\tAML_FIELD_ACCESS_ANY = 0,\n\tAML_FIELD_ACCESS_BYTE = 1,\n\tAML_FIELD_ACCESS_WORD = 2,\n\tAML_FIELD_ACCESS_DWORD = 3,\n\tAML_FIELD_ACCESS_QWORD = 4,\n\tAML_FIELD_ACCESS_BUFFER = 5,\n};\n\nenum {\n\tAML_FIELD_ATTRIB_QUICK = 2,\n\tAML_FIELD_ATTRIB_SEND_RECEIVE = 4,\n\tAML_FIELD_ATTRIB_BYTE = 6,\n\tAML_FIELD_ATTRIB_WORD = 8,\n\tAML_FIELD_ATTRIB_BLOCK = 10,\n\tAML_FIELD_ATTRIB_BYTES = 11,\n\tAML_FIELD_ATTRIB_PROCESS_CALL = 12,\n\tAML_FIELD_ATTRIB_BLOCK_PROCESS_CALL = 13,\n\tAML_FIELD_ATTRIB_RAW_BYTES = 14,\n\tAML_FIELD_ATTRIB_RAW_PROCESS_BYTES = 15,\n};\n\nenum {\n\tAML_FIELD_UPDATE_PRESERVE = 0,\n\tAML_FIELD_UPDATE_WRITE_AS_ONES = 32,\n\tAML_FIELD_UPDATE_WRITE_AS_ZEROS = 64,\n};\n\nenum {\n\tARB_TIMER = 0,\n\tARB_BP_CAP_CLR = 1,\n\tARB_BP_CAP_HI_ADDR = 2,\n\tARB_BP_CAP_ADDR = 3,\n\tARB_BP_CAP_STATUS = 4,\n\tARB_BP_CAP_MASTER = 5,\n\tARB_ERR_CAP_CLR = 6,\n\tARB_ERR_CAP_HI_ADDR = 7,\n\tARB_ERR_CAP_ADDR = 8,\n\tARB_ERR_CAP_STATUS = 9,\n\tARB_ERR_CAP_MASTER = 10,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tASSUME_PERFECT = 255,\n\tASSUME_VALID_DTB = 1,\n\tASSUME_VALID_INPUT = 2,\n\tASSUME_LATEST = 4,\n\tASSUME_NO_ROLLBACK = 8,\n\tASSUME_LIBFDT_ORDER = 16,\n\tASSUME_LIBFDT_FLAWLESS = 32,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = -2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = -2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_CDL = 24,\n\tATA_LOG_CDL_SIZE = 512,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SENSE_NCQ = 15,\n\tATA_LOG_SENSE_NCQ_SIZE = 1024,\n\tATA_LOG_CONCURRENT_POSITIONING_RANGES = 71,\n\tATA_LOG_SUPPORTED_CAPABILITIES = 3,\n\tATA_LOG_CURRENT_SETTINGS = 4,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSETFEATURES_CDL = 13,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tSETFEATURE_SENSE_DATA_SUCC_NCQ = 196,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum {\n\tATA_QUIRK_DIAGNOSTIC = 1,\n\tATA_QUIRK_NODMA = 2,\n\tATA_QUIRK_NONCQ = 4,\n\tATA_QUIRK_BROKEN_HPA = 8,\n\tATA_QUIRK_DISABLE = 16,\n\tATA_QUIRK_HPA_SIZE = 32,\n\tATA_QUIRK_IVB = 64,\n\tATA_QUIRK_STUCK_ERR = 128,\n\tATA_QUIRK_BRIDGE_OK = 256,\n\tATA_QUIRK_ATAPI_MOD16_DMA = 512,\n\tATA_QUIRK_FIRMWARE_WARN = 1024,\n\tATA_QUIRK_1_5_GBPS = 2048,\n\tATA_QUIRK_NOSETXFER = 4096,\n\tATA_QUIRK_BROKEN_FPDMA_AA = 8192,\n\tATA_QUIRK_DUMP_ID = 16384,\n\tATA_QUIRK_MAX_SEC_LBA48 = 32768,\n\tATA_QUIRK_ATAPI_DMADIR = 65536,\n\tATA_QUIRK_NO_NCQ_TRIM = 131072,\n\tATA_QUIRK_NOLPM = 262144,\n\tATA_QUIRK_WD_BROKEN_LPM = 524288,\n\tATA_QUIRK_ZERO_AFTER_TRIM = 1048576,\n\tATA_QUIRK_NO_DMA_LOG = 2097152,\n\tATA_QUIRK_NOTRIM = 4194304,\n\tATA_QUIRK_MAX_SEC = 8388608,\n\tATA_QUIRK_MAX_TRIM_128M = 16777216,\n\tATA_QUIRK_NO_NCQ_ON_ATI = 33554432,\n\tATA_QUIRK_NO_LPM_ON_ATI = 67108864,\n\tATA_QUIRK_NO_ID_DEV_LOG = 134217728,\n\tATA_QUIRK_NO_LOG_DIR = 268435456,\n\tATA_QUIRK_NO_FUA = 536870912,\n};\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = -2147483648,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAUTOFS_DEV_IOCTL_VERSION_CMD = 113,\n\tAUTOFS_DEV_IOCTL_PROTOVER_CMD = 114,\n\tAUTOFS_DEV_IOCTL_PROTOSUBVER_CMD = 115,\n\tAUTOFS_DEV_IOCTL_OPENMOUNT_CMD = 116,\n\tAUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD = 117,\n\tAUTOFS_DEV_IOCTL_READY_CMD = 118,\n\tAUTOFS_DEV_IOCTL_FAIL_CMD = 119,\n\tAUTOFS_DEV_IOCTL_SETPIPEFD_CMD = 120,\n\tAUTOFS_DEV_IOCTL_CATATONIC_CMD = 121,\n\tAUTOFS_DEV_IOCTL_TIMEOUT_CMD = 122,\n\tAUTOFS_DEV_IOCTL_REQUESTER_CMD = 123,\n\tAUTOFS_DEV_IOCTL_EXPIRE_CMD = 124,\n\tAUTOFS_DEV_IOCTL_ASKUMOUNT_CMD = 125,\n\tAUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD = 126,\n};\n\nenum {\n\tAUTOFS_IOC_EXPIRE_MULTI_CMD = 102,\n\tAUTOFS_IOC_PROTOSUBVER_CMD = 103,\n\tAUTOFS_IOC_ASKUMOUNT_CMD = 112,\n};\n\nenum {\n\tAUTOFS_IOC_READY_CMD = 96,\n\tAUTOFS_IOC_FAIL_CMD = 97,\n\tAUTOFS_IOC_CATATONIC_CMD = 98,\n\tAUTOFS_IOC_PROTOVER_CMD = 99,\n\tAUTOFS_IOC_SETTIMEOUT_CMD = 100,\n\tAUTOFS_IOC_EXPIRE_CMD = 101,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tAXP15060_DCDC1 = 0,\n\tAXP15060_DCDC2 = 1,\n\tAXP15060_DCDC3 = 2,\n\tAXP15060_DCDC4 = 3,\n\tAXP15060_DCDC5 = 4,\n\tAXP15060_DCDC6 = 5,\n\tAXP15060_ALDO1 = 6,\n\tAXP15060_ALDO2 = 7,\n\tAXP15060_ALDO3 = 8,\n\tAXP15060_ALDO4 = 9,\n\tAXP15060_ALDO5 = 10,\n\tAXP15060_BLDO1 = 11,\n\tAXP15060_BLDO2 = 12,\n\tAXP15060_BLDO3 = 13,\n\tAXP15060_BLDO4 = 14,\n\tAXP15060_BLDO5 = 15,\n\tAXP15060_CLDO1 = 16,\n\tAXP15060_CLDO2 = 17,\n\tAXP15060_CLDO3 = 18,\n\tAXP15060_CLDO4 = 19,\n\tAXP15060_CPUSLDO = 20,\n\tAXP15060_SW = 21,\n\tAXP15060_RTC_LDO = 22,\n\tAXP15060_REG_ID_MAX = 23,\n};\n\nenum {\n\tAXP152_IRQ_LDO0IN_CONNECT = 1,\n\tAXP152_IRQ_LDO0IN_REMOVAL = 2,\n\tAXP152_IRQ_ALDO0IN_CONNECT = 3,\n\tAXP152_IRQ_ALDO0IN_REMOVAL = 4,\n\tAXP152_IRQ_DCDC1_V_LOW = 5,\n\tAXP152_IRQ_DCDC2_V_LOW = 6,\n\tAXP152_IRQ_DCDC3_V_LOW = 7,\n\tAXP152_IRQ_DCDC4_V_LOW = 8,\n\tAXP152_IRQ_PEK_SHORT = 9,\n\tAXP152_IRQ_PEK_LONG = 10,\n\tAXP152_IRQ_TIMER = 11,\n\tAXP152_IRQ_PEK_FAL_EDGE = 12,\n\tAXP152_IRQ_PEK_RIS_EDGE = 13,\n\tAXP152_IRQ_GPIO3_INPUT = 14,\n\tAXP152_IRQ_GPIO2_INPUT = 15,\n\tAXP152_IRQ_GPIO1_INPUT = 16,\n\tAXP152_IRQ_GPIO0_INPUT = 17,\n};\n\nenum {\n\tAXP20X_IRQ_ACIN_OVER_V = 1,\n\tAXP20X_IRQ_ACIN_PLUGIN = 2,\n\tAXP20X_IRQ_ACIN_REMOVAL = 3,\n\tAXP20X_IRQ_VBUS_OVER_V = 4,\n\tAXP20X_IRQ_VBUS_PLUGIN = 5,\n\tAXP20X_IRQ_VBUS_REMOVAL = 6,\n\tAXP20X_IRQ_VBUS_V_LOW = 7,\n\tAXP20X_IRQ_BATT_PLUGIN = 8,\n\tAXP20X_IRQ_BATT_REMOVAL = 9,\n\tAXP20X_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP20X_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP20X_IRQ_CHARG = 12,\n\tAXP20X_IRQ_CHARG_DONE = 13,\n\tAXP20X_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP20X_IRQ_BATT_TEMP_LOW = 15,\n\tAXP20X_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP20X_IRQ_CHARG_I_LOW = 17,\n\tAXP20X_IRQ_DCDC1_V_LONG = 18,\n\tAXP20X_IRQ_DCDC2_V_LONG = 19,\n\tAXP20X_IRQ_DCDC3_V_LONG = 20,\n\tAXP20X_IRQ_PEK_SHORT = 22,\n\tAXP20X_IRQ_PEK_LONG = 23,\n\tAXP20X_IRQ_N_OE_PWR_ON = 24,\n\tAXP20X_IRQ_N_OE_PWR_OFF = 25,\n\tAXP20X_IRQ_VBUS_VALID = 26,\n\tAXP20X_IRQ_VBUS_NOT_VALID = 27,\n\tAXP20X_IRQ_VBUS_SESS_VALID = 28,\n\tAXP20X_IRQ_VBUS_SESS_END = 29,\n\tAXP20X_IRQ_LOW_PWR_LVL1 = 30,\n\tAXP20X_IRQ_LOW_PWR_LVL2 = 31,\n\tAXP20X_IRQ_TIMER = 32,\n\tAXP20X_IRQ_PEK_FAL_EDGE = 33,\n\tAXP20X_IRQ_PEK_RIS_EDGE = 34,\n\tAXP20X_IRQ_GPIO3_INPUT = 35,\n\tAXP20X_IRQ_GPIO2_INPUT = 36,\n\tAXP20X_IRQ_GPIO1_INPUT = 37,\n\tAXP20X_IRQ_GPIO0_INPUT = 38,\n};\n\nenum {\n\tAXP20X_LDO1 = 0,\n\tAXP20X_LDO2 = 1,\n\tAXP20X_LDO3 = 2,\n\tAXP20X_LDO4 = 3,\n\tAXP20X_LDO5 = 4,\n\tAXP20X_DCDC2 = 5,\n\tAXP20X_DCDC3 = 6,\n\tAXP20X_REG_ID_MAX = 7,\n};\n\nenum {\n\tAXP22X_DCDC1 = 0,\n\tAXP22X_DCDC2 = 1,\n\tAXP22X_DCDC3 = 2,\n\tAXP22X_DCDC4 = 3,\n\tAXP22X_DCDC5 = 4,\n\tAXP22X_DC1SW = 5,\n\tAXP22X_DC5LDO = 6,\n\tAXP22X_ALDO1 = 7,\n\tAXP22X_ALDO2 = 8,\n\tAXP22X_ALDO3 = 9,\n\tAXP22X_ELDO1 = 10,\n\tAXP22X_ELDO2 = 11,\n\tAXP22X_ELDO3 = 12,\n\tAXP22X_DLDO1 = 13,\n\tAXP22X_DLDO2 = 14,\n\tAXP22X_DLDO3 = 15,\n\tAXP22X_DLDO4 = 16,\n\tAXP22X_RTC_LDO = 17,\n\tAXP22X_LDO_IO0 = 18,\n\tAXP22X_LDO_IO1 = 19,\n\tAXP22X_REG_ID_MAX = 20,\n};\n\nenum {\n\tAXP313A_DCDC1 = 0,\n\tAXP313A_DCDC2 = 1,\n\tAXP313A_DCDC3 = 2,\n\tAXP313A_ALDO1 = 3,\n\tAXP313A_DLDO1 = 4,\n\tAXP313A_RTC_LDO = 5,\n\tAXP313A_REG_ID_MAX = 6,\n};\n\nenum {\n\tAXP717_DCDC1 = 0,\n\tAXP717_DCDC2 = 1,\n\tAXP717_DCDC3 = 2,\n\tAXP717_DCDC4 = 3,\n\tAXP717_ALDO1 = 4,\n\tAXP717_ALDO2 = 5,\n\tAXP717_ALDO3 = 6,\n\tAXP717_ALDO4 = 7,\n\tAXP717_BLDO1 = 8,\n\tAXP717_BLDO2 = 9,\n\tAXP717_BLDO3 = 10,\n\tAXP717_BLDO4 = 11,\n\tAXP717_CLDO1 = 12,\n\tAXP717_CLDO2 = 13,\n\tAXP717_CLDO3 = 14,\n\tAXP717_CLDO4 = 15,\n\tAXP717_CPUSLDO = 16,\n\tAXP717_BOOST = 17,\n\tAXP717_REG_ID_MAX = 18,\n};\n\nenum {\n\tAXP803_DCDC1 = 0,\n\tAXP803_DCDC2 = 1,\n\tAXP803_DCDC3 = 2,\n\tAXP803_DCDC4 = 3,\n\tAXP803_DCDC5 = 4,\n\tAXP803_DCDC6 = 5,\n\tAXP803_DC1SW = 6,\n\tAXP803_ALDO1 = 7,\n\tAXP803_ALDO2 = 8,\n\tAXP803_ALDO3 = 9,\n\tAXP803_DLDO1 = 10,\n\tAXP803_DLDO2 = 11,\n\tAXP803_DLDO3 = 12,\n\tAXP803_DLDO4 = 13,\n\tAXP803_ELDO1 = 14,\n\tAXP803_ELDO2 = 15,\n\tAXP803_ELDO3 = 16,\n\tAXP803_FLDO1 = 17,\n\tAXP803_FLDO2 = 18,\n\tAXP803_RTC_LDO = 19,\n\tAXP803_LDO_IO0 = 20,\n\tAXP803_LDO_IO1 = 21,\n\tAXP803_REG_ID_MAX = 22,\n};\n\nenum {\n\tAXP806_DCDCA = 0,\n\tAXP806_DCDCB = 1,\n\tAXP806_DCDCC = 2,\n\tAXP806_DCDCD = 3,\n\tAXP806_DCDCE = 4,\n\tAXP806_ALDO1 = 5,\n\tAXP806_ALDO2 = 6,\n\tAXP806_ALDO3 = 7,\n\tAXP806_BLDO1 = 8,\n\tAXP806_BLDO2 = 9,\n\tAXP806_BLDO3 = 10,\n\tAXP806_BLDO4 = 11,\n\tAXP806_CLDO1 = 12,\n\tAXP806_CLDO2 = 13,\n\tAXP806_CLDO3 = 14,\n\tAXP806_SW = 15,\n\tAXP806_REG_ID_MAX = 16,\n};\n\nenum {\n\tAXP809_DCDC1 = 0,\n\tAXP809_DCDC2 = 1,\n\tAXP809_DCDC3 = 2,\n\tAXP809_DCDC4 = 3,\n\tAXP809_DCDC5 = 4,\n\tAXP809_DC1SW = 5,\n\tAXP809_DC5LDO = 6,\n\tAXP809_ALDO1 = 7,\n\tAXP809_ALDO2 = 8,\n\tAXP809_ALDO3 = 9,\n\tAXP809_ELDO1 = 10,\n\tAXP809_ELDO2 = 11,\n\tAXP809_ELDO3 = 12,\n\tAXP809_DLDO1 = 13,\n\tAXP809_DLDO2 = 14,\n\tAXP809_RTC_LDO = 15,\n\tAXP809_LDO_IO0 = 16,\n\tAXP809_LDO_IO1 = 17,\n\tAXP809_SW = 18,\n\tAXP809_REG_ID_MAX = 19,\n};\n\nenum {\n\tAXP813_DCDC1 = 0,\n\tAXP813_DCDC2 = 1,\n\tAXP813_DCDC3 = 2,\n\tAXP813_DCDC4 = 3,\n\tAXP813_DCDC5 = 4,\n\tAXP813_DCDC6 = 5,\n\tAXP813_DCDC7 = 6,\n\tAXP813_ALDO1 = 7,\n\tAXP813_ALDO2 = 8,\n\tAXP813_ALDO3 = 9,\n\tAXP813_DLDO1 = 10,\n\tAXP813_DLDO2 = 11,\n\tAXP813_DLDO3 = 12,\n\tAXP813_DLDO4 = 13,\n\tAXP813_ELDO1 = 14,\n\tAXP813_ELDO2 = 15,\n\tAXP813_ELDO3 = 16,\n\tAXP813_FLDO1 = 17,\n\tAXP813_FLDO2 = 18,\n\tAXP813_FLDO3 = 19,\n\tAXP813_RTC_LDO = 20,\n\tAXP813_LDO_IO0 = 21,\n\tAXP813_LDO_IO1 = 22,\n\tAXP813_SW = 23,\n\tAXP813_REG_ID_MAX = 24,\n};\n\nenum {\n\tAudit_equal = 0,\n\tAudit_not_equal = 1,\n\tAudit_bitmask = 2,\n\tAudit_bittest = 3,\n\tAudit_lt = 4,\n\tAudit_gt = 5,\n\tAudit_le = 6,\n\tAudit_ge = 7,\n\tAudit_bad = 8,\n};\n\nenum {\n\tB28_DPT_INI = 3584,\n\tB28_DPT_VAL = 3588,\n\tB28_DPT_CTRL = 3592,\n\tB28_DPT_TST = 3594,\n};\n\nenum {\n\tB28_Y2_SMB_CONFIG = 3648,\n\tB28_Y2_SMB_CSD_REG = 3652,\n\tB28_Y2_ASF_IRQ_V_BASE = 3680,\n\tB28_Y2_ASF_STAT_CMD = 3688,\n\tB28_Y2_ASF_HOST_COM = 3692,\n\tB28_Y2_DATA_REG_1 = 3696,\n\tB28_Y2_DATA_REG_2 = 3700,\n\tB28_Y2_DATA_REG_3 = 3704,\n\tB28_Y2_DATA_REG_4 = 3708,\n};\n\nenum {\n\tB6_EXT_REG = 768,\n\tB7_CFG_SPC = 896,\n\tB8_RQ1_REGS = 1024,\n\tB8_RQ2_REGS = 1152,\n\tB8_TS1_REGS = 1536,\n\tB8_TA1_REGS = 1664,\n\tB8_TS2_REGS = 1792,\n\tB8_TA2_REGS = 1920,\n\tB16_RAM_REGS = 2048,\n};\n\nenum {\n\tB8_Q_REGS = 1024,\n\tQ_D = 0,\n\tQ_VLAN = 32,\n\tQ_DONE = 36,\n\tQ_AC_L = 40,\n\tQ_AC_H = 44,\n\tQ_BC = 48,\n\tQ_CSR = 52,\n\tQ_TEST = 56,\n\tQ_WM = 64,\n\tQ_AL = 66,\n\tQ_RSP = 68,\n\tQ_RSL = 70,\n\tQ_RP = 72,\n\tQ_RL = 74,\n\tQ_WP = 76,\n\tQ_WSP = 77,\n\tQ_WL = 78,\n\tQ_WSL = 79,\n};\n\nenum {\n\tBASE_GMAC_1 = 10240,\n\tBASE_GMAC_2 = 14336,\n};\n\nenum {\n\tBCM_MSG_FUNC_LINK_START = 0,\n\tBCM_MSG_FUNC_LINK_STOP = 1,\n\tBCM_MSG_FUNC_SHMEM_TX = 2,\n\tBCM_MSG_FUNC_SHMEM_RX = 3,\n\tBCM_MSG_FUNC_SHMEM_STOP = 4,\n\tBCM_MSG_FUNC_MAX = 5,\n};\n\nenum {\n\tBCM_MSG_SVC_INIT = 0,\n\tBCM_MSG_SVC_PMC = 1,\n\tBCM_MSG_SVC_SCMI = 2,\n\tBCM_MSG_SVC_DPFE = 3,\n\tBCM_MSG_SVC_MAX = 4,\n};\n\nenum {\n\tBD71837_REG_BUCK3_CTRL = 7,\n\tBD71837_REG_BUCK4_CTRL = 8,\n\tBD71837_REG_BUCK3_VOLT_RUN = 18,\n\tBD71837_REG_BUCK4_VOLT_RUN = 19,\n\tBD71837_REG_LDO7_VOLT = 30,\n};\n\nenum {\n\tBD718XX_BUCK1 = 0,\n\tBD718XX_BUCK2 = 1,\n\tBD718XX_BUCK3 = 2,\n\tBD718XX_BUCK4 = 3,\n\tBD718XX_BUCK5 = 4,\n\tBD718XX_BUCK6 = 5,\n\tBD718XX_BUCK7 = 6,\n\tBD718XX_BUCK8 = 7,\n\tBD718XX_LDO1 = 8,\n\tBD718XX_LDO2 = 9,\n\tBD718XX_LDO3 = 10,\n\tBD718XX_LDO4 = 11,\n\tBD718XX_LDO5 = 12,\n\tBD718XX_LDO6 = 13,\n\tBD718XX_LDO7 = 14,\n\tBD718XX_REGULATOR_AMOUNT = 15,\n};\n\nenum {\n\tBD718XX_INT_STBY_REQ = 0,\n\tBD718XX_INT_ON_REQ = 1,\n\tBD718XX_INT_WDOG = 2,\n\tBD718XX_INT_PWRBTN = 3,\n\tBD718XX_INT_PWRBTN_L = 4,\n\tBD718XX_INT_PWRBTN_S = 5,\n\tBD718XX_INT_SWRST = 6,\n};\n\nenum {\n\tBD718XX_REG_REV = 0,\n\tBD718XX_REG_SWRESET = 1,\n\tBD718XX_REG_I2C_DEV = 2,\n\tBD718XX_REG_PWRCTRL0 = 3,\n\tBD718XX_REG_PWRCTRL1 = 4,\n\tBD718XX_REG_BUCK1_CTRL = 5,\n\tBD718XX_REG_BUCK2_CTRL = 6,\n\tBD718XX_REG_1ST_NODVS_BUCK_CTRL = 9,\n\tBD718XX_REG_2ND_NODVS_BUCK_CTRL = 10,\n\tBD718XX_REG_3RD_NODVS_BUCK_CTRL = 11,\n\tBD718XX_REG_4TH_NODVS_BUCK_CTRL = 12,\n\tBD718XX_REG_BUCK1_VOLT_RUN = 13,\n\tBD718XX_REG_BUCK1_VOLT_IDLE = 14,\n\tBD718XX_REG_BUCK1_VOLT_SUSP = 15,\n\tBD718XX_REG_BUCK2_VOLT_RUN = 16,\n\tBD718XX_REG_BUCK2_VOLT_IDLE = 17,\n\tBD718XX_REG_1ST_NODVS_BUCK_VOLT = 20,\n\tBD718XX_REG_2ND_NODVS_BUCK_VOLT = 21,\n\tBD718XX_REG_3RD_NODVS_BUCK_VOLT = 22,\n\tBD718XX_REG_4TH_NODVS_BUCK_VOLT = 23,\n\tBD718XX_REG_LDO1_VOLT = 24,\n\tBD718XX_REG_LDO2_VOLT = 25,\n\tBD718XX_REG_LDO3_VOLT = 26,\n\tBD718XX_REG_LDO4_VOLT = 27,\n\tBD718XX_REG_LDO5_VOLT = 28,\n\tBD718XX_REG_LDO6_VOLT = 29,\n\tBD718XX_REG_TRANS_COND0 = 31,\n\tBD718XX_REG_TRANS_COND1 = 32,\n\tBD718XX_REG_VRFAULTEN = 33,\n\tBD718XX_REG_MVRFLTMASK0 = 34,\n\tBD718XX_REG_MVRFLTMASK1 = 35,\n\tBD718XX_REG_MVRFLTMASK2 = 36,\n\tBD718XX_REG_RCVCFG = 37,\n\tBD718XX_REG_RCVNUM = 38,\n\tBD718XX_REG_PWRONCONFIG0 = 39,\n\tBD718XX_REG_PWRONCONFIG1 = 40,\n\tBD718XX_REG_RESETSRC = 41,\n\tBD718XX_REG_MIRQ = 42,\n\tBD718XX_REG_IRQ = 43,\n\tBD718XX_REG_IN_MON = 44,\n\tBD718XX_REG_POW_STATE = 45,\n\tBD718XX_REG_OUT32K = 46,\n\tBD718XX_REG_REGLOCK = 47,\n\tBD718XX_REG_OTPVER = 255,\n\tBD718XX_MAX_REGISTER = 256,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLINK_42MS = 0,\n\tBLINK_84MS = 1,\n\tBLINK_170MS = 2,\n\tBLINK_340MS = 3,\n\tBLINK_670MS = 4,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nenum {\n\tBMC_NPCM7XX = 0,\n\tBMC_NPCM8XX = 1,\n};\n\nenum {\n\tBMU_IDLE = -2147483648,\n\tBMU_RX_TCP_PKT = 1073741824,\n\tBMU_RX_IP_PKT = 536870912,\n\tBMU_ENA_RX_RSS_HASH = 32768,\n\tBMU_DIS_RX_RSS_HASH = 16384,\n\tBMU_ENA_RX_CHKSUM = 8192,\n\tBMU_DIS_RX_CHKSUM = 4096,\n\tBMU_CLR_IRQ_PAR = 2048,\n\tBMU_CLR_IRQ_TCP = 2048,\n\tBMU_CLR_IRQ_CHK = 1024,\n\tBMU_STOP = 512,\n\tBMU_START = 256,\n\tBMU_FIFO_OP_ON = 128,\n\tBMU_FIFO_OP_OFF = 64,\n\tBMU_FIFO_ENA = 32,\n\tBMU_FIFO_RST = 16,\n\tBMU_OP_ON = 8,\n\tBMU_OP_OFF = 4,\n\tBMU_RST_CLR = 2,\n\tBMU_RST_SET = 1,\n\tBMU_CLR_RESET = 22,\n\tBMU_OPER_INIT = 3368,\n\tBMU_WM_DEFAULT = 1536,\n\tBMU_WM_PEX = 128,\n};\n\nenum {\n\tBOOST_ILMIN_75MA = 0,\n\tBOOST_ILMIN_100MA = 1,\n\tBOOST_ILMIN_125MA = 2,\n\tBOOST_ILMIN_150MA = 3,\n\tBOOST_ILMIN_175MA = 4,\n\tBOOST_ILMIN_200MA = 5,\n\tBOOST_ILMIN_225MA = 6,\n\tBOOST_ILMIN_250MA = 7,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\nenum {\n\tBPF_F_SYSCTL_BASE_NAME = 1,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 38,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBPF_WRITE_HDR_TCP_CURRENT_MSS = 1,\n\tBPF_WRITE_HDR_TCP_SYNACK_COOKIE = 2,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tBUCK_ILMIN_50MA = 0,\n\tBUCK_ILMIN_100MA = 1,\n\tBUCK_ILMIN_150MA = 2,\n\tBUCK_ILMIN_200MA = 3,\n\tBUCK_ILMIN_250MA = 4,\n\tBUCK_ILMIN_300MA = 5,\n\tBUCK_ILMIN_350MA = 6,\n\tBUCK_ILMIN_400MA = 7,\n};\n\nenum {\n\tCACHE_VALID = 0,\n\tCACHE_NEGATIVE = 1,\n\tCACHE_PENDING = 2,\n\tCACHE_CLEANED = 3,\n};\n\nenum {\n\tCAP_HWCAP = 1,\n\tCAP_COMPAT_HWCAP = 2,\n\tCAP_COMPAT_HWCAP2 = 3,\n};\n\nenum {\n\tCBF_XO_INDEX = 0,\n\tCBF_PLL_INDEX = 1,\n\tCBF_DIV_INDEX = 2,\n\tCBF_APCS_AUX_INDEX = 3,\n};\n\nenum {\n\tCFG_CHIP_R_MSK = 240,\n\tCFG_DIS_M2_CLK = 2,\n\tCFG_SNG_MAC = 1,\n};\n\nenum {\n\tCFG_LED_MODE_MSK = 28,\n\tCFG_LINK_2_AVAIL = 2,\n\tCFG_LINK_1_AVAIL = 1,\n};\n\nenum {\n\tCFG_POST_HIBERN8_ENTER = 0,\n\tCFG_PRE_HIBERN8_EXIT = 1,\n};\n\nenum {\n\tCFG_PRE_INIT = 0,\n\tCFG_POST_INIT = 1,\n\tCFG_PRE_PWR_HS = 2,\n\tCFG_POST_PWR_HS = 3,\n\tCFG_TAG_MAX = 4,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGROUPSTATS_CMD_ATTR_UNSPEC = 0,\n\tCGROUPSTATS_CMD_ATTR_FD = 1,\n\t__CGROUPSTATS_CMD_ATTR_MAX = 2,\n};\n\nenum {\n\tCGROUPSTATS_CMD_UNSPEC = 3,\n\tCGROUPSTATS_CMD_GET = 4,\n\tCGROUPSTATS_CMD_NEW = 5,\n\t__CGROUPSTATS_CMD_MAX = 6,\n};\n\nenum {\n\tCGROUPSTATS_TYPE_UNSPEC = 0,\n\tCGROUPSTATS_TYPE_CGROUP_STATS = 1,\n\t__CGROUPSTATS_TYPE_MAX = 2,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCHIP_ID_YUKON_XL = 179,\n\tCHIP_ID_YUKON_EC_U = 180,\n\tCHIP_ID_YUKON_EX = 181,\n\tCHIP_ID_YUKON_EC = 182,\n\tCHIP_ID_YUKON_FE = 183,\n\tCHIP_ID_YUKON_FE_P = 184,\n\tCHIP_ID_YUKON_SUPR = 185,\n\tCHIP_ID_YUKON_UL_2 = 186,\n\tCHIP_ID_YUKON_OPT = 188,\n\tCHIP_ID_YUKON_PRM = 189,\n\tCHIP_ID_YUKON_OP_2 = 190,\n};\n\nenum {\n\tCLK_ALPHA_PLL_TYPE_DEFAULT = 0,\n\tCLK_ALPHA_PLL_TYPE_HUAYRA = 1,\n\tCLK_ALPHA_PLL_TYPE_HUAYRA_APSS = 2,\n\tCLK_ALPHA_PLL_TYPE_HUAYRA_2290 = 3,\n\tCLK_ALPHA_PLL_TYPE_BRAMMO = 4,\n\tCLK_ALPHA_PLL_TYPE_FABIA = 5,\n\tCLK_ALPHA_PLL_TYPE_TRION = 6,\n\tCLK_ALPHA_PLL_TYPE_LUCID = 6,\n\tCLK_ALPHA_PLL_TYPE_AGERA = 7,\n\tCLK_ALPHA_PLL_TYPE_ZONDA = 8,\n\tCLK_ALPHA_PLL_TYPE_REGERA = 8,\n\tCLK_ALPHA_PLL_TYPE_ZONDA_OLE = 9,\n\tCLK_ALPHA_PLL_TYPE_LUCID_EVO = 10,\n\tCLK_ALPHA_PLL_TYPE_LUCID_OLE = 11,\n\tCLK_ALPHA_PLL_TYPE_PONGO_ELU = 12,\n\tCLK_ALPHA_PLL_TYPE_PONGO_EKO_T = 12,\n\tCLK_ALPHA_PLL_TYPE_TAYCAN_ELU = 13,\n\tCLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = 13,\n\tCLK_ALPHA_PLL_TYPE_RIVIAN_EVO = 14,\n\tCLK_ALPHA_PLL_TYPE_RIVIAN_ELU = 15,\n\tCLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T = 15,\n\tCLK_ALPHA_PLL_TYPE_DEFAULT_EVO = 16,\n\tCLK_ALPHA_PLL_TYPE_BRAMMO_EVO = 17,\n\tCLK_ALPHA_PLL_TYPE_STROMER = 18,\n\tCLK_ALPHA_PLL_TYPE_STROMER_PLUS = 19,\n\tCLK_ALPHA_PLL_TYPE_NSS_HUAYRA = 20,\n\tCLK_ALPHA_PLL_TYPE_MAX = 21,\n};\n\nenum {\n\tCLK_GATE = 0,\n\tCLK_DIVIDER = 1,\n\tCLK_MUX = 2,\n};\n\nenum {\n\tCLK_QSPI_REF = 0,\n\tCLK_QSPI_APB = 1,\n\tCLK_QSPI_AHB = 2,\n\tCLK_QSPI_NUM = 3,\n};\n\nenum {\n\tCMD_CLK_GET_RATE = 1,\n\tCMD_CLK_SET_RATE = 2,\n\tCMD_CLK_ROUND_RATE = 3,\n\tCMD_CLK_GET_PARENT = 4,\n\tCMD_CLK_SET_PARENT = 5,\n\tCMD_CLK_IS_ENABLED = 6,\n\tCMD_CLK_ENABLE = 7,\n\tCMD_CLK_DISABLE = 8,\n\tCMD_CLK_PROPERTIES = 9,\n\tCMD_CLK_POSSIBLE_PARENTS = 10,\n\tCMD_CLK_NUM_POSSIBLE_PARENTS = 11,\n\tCMD_CLK_GET_POSSIBLE_PARENT = 12,\n\tCMD_CLK_RESET_REFCOUNTS = 13,\n\tCMD_CLK_GET_ALL_INFO = 14,\n\tCMD_CLK_GET_MAX_CLK_ID = 15,\n\tCMD_CLK_GET_FMAX_AT_VMIN = 16,\n\tCMD_CLK_MAX = 17,\n};\n\nenum {\n\tCMD_I2C_XFER = 1,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCP110_CLK_TYPE_CORE = 0,\n\tCP110_CLK_TYPE_GATABLE = 1,\n};\n\nenum {\n\tCPER_SEV_RECOVERABLE = 0,\n\tCPER_SEV_FATAL = 1,\n\tCPER_SEV_CORRECTED = 2,\n\tCPER_SEV_INFORMATIONAL = 3,\n};\n\nenum {\n\tCPORT_IDLE = 0,\n\tCPORT_CONNECTED = 1,\n};\n\nenum {\n\tCPSW_ALE_F_STATUS_REG = 1,\n\tCPSW_ALE_F_HW_AUTOAGING = 2,\n\tCPSW_ALE_F_COUNT = 3,\n};\n\nenum {\n\tCPSW_SL_CTL_FULLDUPLEX = 1,\n\tCPSW_SL_CTL_LOOPBACK = 2,\n\tCPSW_SL_CTL_MTEST = 4,\n\tCPSW_SL_CTL_RX_FLOW_EN = 8,\n\tCPSW_SL_CTL_TX_FLOW_EN = 16,\n\tCPSW_SL_CTL_GMII_EN = 32,\n\tCPSW_SL_CTL_TX_PACE = 64,\n\tCPSW_SL_CTL_GIG = 128,\n\tCPSW_SL_CTL_XGIG = 256,\n\tCPSW_SL_CTL_TX_SHORT_GAP_EN = 1024,\n\tCPSW_SL_CTL_CMD_IDLE = 2048,\n\tCPSW_SL_CTL_CRC_TYPE = 4096,\n\tCPSW_SL_CTL_XGMII_EN = 8192,\n\tCPSW_SL_CTL_IFCTL_A = 32768,\n\tCPSW_SL_CTL_IFCTL_B = 65536,\n\tCPSW_SL_CTL_GIG_FORCE = 131072,\n\tCPSW_SL_CTL_EXT_EN = 262144,\n\tCPSW_SL_CTL_EXT_EN_RX_FLO = 524288,\n\tCPSW_SL_CTL_EXT_EN_TX_FLO = 1048576,\n\tCPSW_SL_CTL_TX_SG_LIM_EN = 2097152,\n\tCPSW_SL_CTL_RX_CEF_EN = 4194304,\n\tCPSW_SL_CTL_RX_CSF_EN = 8388608,\n\tCPSW_SL_CTL_RX_CMF_EN = 16777216,\n\tCPSW_SL_CTL_EXT_EN_XGIG = 33554432,\n\tCPSW_SL_CTL_FUNCS_COUNT = 33554433,\n};\n\nenum {\n\tCPU_WDOG = 3656,\n\tCPU_CNTR = 3660,\n\tCPU_TIM = 3664,\n\tCPU_AHB_ADDR = 3668,\n\tCPU_AHB_WDATA = 3672,\n\tCPU_AHB_RDATA = 3676,\n\tHCU_MAP_BASE = 3680,\n\tCPU_AHB_CTRL = 3684,\n\tHCU_CCSR = 3688,\n\tHCU_HCSR = 3692,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 250,\n\tCRNG_RESEED_INTERVAL = 15000,\n};\n\nenum {\n\tCROS_EC_SENSOR_LAST_TS = 0,\n\tCROS_EC_SENSOR_NEW_TS = 1,\n\tCROS_EC_SENSOR_ALL_TS = 2,\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\t__CRYPTOA_MAX = 3,\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nenum {\n\tCRYPTO_MSG_BASE = 16,\n\tCRYPTO_MSG_NEWALG = 16,\n\tCRYPTO_MSG_DELALG = 17,\n\tCRYPTO_MSG_UPDATEALG = 18,\n\tCRYPTO_MSG_GETALG = 19,\n\tCRYPTO_MSG_DELRNG = 20,\n\tCRYPTO_MSG_GETSTAT = 21,\n\t__CRYPTO_MSG_MAX = 22,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEVLINK_ATTR_STATS_RX_PACKETS = 0,\n\tDEVLINK_ATTR_STATS_RX_BYTES = 1,\n\tDEVLINK_ATTR_STATS_RX_DROPPED = 2,\n\t__DEVLINK_ATTR_STATS_MAX = 3,\n\tDEVLINK_ATTR_STATS_MAX = 2,\n};\n\nenum {\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_IN_PORT = 0,\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_FA_COOKIE = 1,\n};\n\nenum {\n\tDEV_ENERGYMODEL_A_PERF_DOMAIN_PAD = 1,\n\tDEV_ENERGYMODEL_A_PERF_DOMAIN_PERF_DOMAIN_ID = 2,\n\tDEV_ENERGYMODEL_A_PERF_DOMAIN_FLAGS = 3,\n\tDEV_ENERGYMODEL_A_PERF_DOMAIN_CPUS = 4,\n\t__DEV_ENERGYMODEL_A_PERF_DOMAIN_MAX = 5,\n\tDEV_ENERGYMODEL_A_PERF_DOMAIN_MAX = 4,\n};\n\nenum {\n\tDEV_ENERGYMODEL_A_PERF_STATE_PAD = 1,\n\tDEV_ENERGYMODEL_A_PERF_STATE_PERFORMANCE = 2,\n\tDEV_ENERGYMODEL_A_PERF_STATE_FREQUENCY = 3,\n\tDEV_ENERGYMODEL_A_PERF_STATE_POWER = 4,\n\tDEV_ENERGYMODEL_A_PERF_STATE_COST = 5,\n\tDEV_ENERGYMODEL_A_PERF_STATE_FLAGS = 6,\n\t__DEV_ENERGYMODEL_A_PERF_STATE_MAX = 7,\n\tDEV_ENERGYMODEL_A_PERF_STATE_MAX = 6,\n};\n\nenum {\n\tDEV_ENERGYMODEL_A_PERF_TABLE_PERF_DOMAIN_ID = 1,\n\tDEV_ENERGYMODEL_A_PERF_TABLE_PERF_STATE = 2,\n\t__DEV_ENERGYMODEL_A_PERF_TABLE_MAX = 3,\n\tDEV_ENERGYMODEL_A_PERF_TABLE_MAX = 2,\n};\n\nenum {\n\tDEV_ENERGYMODEL_CMD_GET_PERF_DOMAINS = 1,\n\tDEV_ENERGYMODEL_CMD_GET_PERF_TABLE = 2,\n\tDEV_ENERGYMODEL_CMD_PERF_DOMAIN_CREATED = 3,\n\tDEV_ENERGYMODEL_CMD_PERF_DOMAIN_UPDATED = 4,\n\tDEV_ENERGYMODEL_CMD_PERF_DOMAIN_DELETED = 5,\n\t__DEV_ENERGYMODEL_CMD_MAX = 6,\n\tDEV_ENERGYMODEL_CMD_MAX = 5,\n};\n\nenum {\n\tDEV_ENERGYMODEL_NLGRP_EVENT = 0,\n};\n\nenum {\n\tDEV_ID = 0,\n\tPEER_DEV_ID = 1,\n\tPEER_CPORT_ID = 0,\n\tTRAFFIC_CLASS = 0,\n};\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDMA_TX_ERR_BASE = 0,\n\tDMA_RX_ERR_BASE = 256,\n\tTRANS_TX_FAIL_BASE = 512,\n\tTRANS_RX_FAIL_BASE = 768,\n\tDMA_TX_DIF_CRC_ERR = 0,\n\tDMA_TX_DIF_APP_ERR = 1,\n\tDMA_TX_DIF_RPP_ERR = 2,\n\tDMA_TX_AXI_BUS_ERR = 3,\n\tDMA_TX_DATA_SGL_OVERFLOW_ERR = 4,\n\tDMA_TX_DIF_SGL_OVERFLOW_ERR = 5,\n\tDMA_TX_UNEXP_XFER_RDY_ERR = 6,\n\tDMA_TX_XFER_RDY_OFFSET_ERR = 7,\n\tDMA_TX_DATA_UNDERFLOW_ERR = 8,\n\tDMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR = 9,\n\tDMA_RX_BUFFER_ECC_ERR = 256,\n\tDMA_RX_DIF_CRC_ERR = 257,\n\tDMA_RX_DIF_APP_ERR = 258,\n\tDMA_RX_DIF_RPP_ERR = 259,\n\tDMA_RX_RESP_BUFFER_OVERFLOW_ERR = 260,\n\tDMA_RX_AXI_BUS_ERR = 261,\n\tDMA_RX_DATA_SGL_OVERFLOW_ERR = 262,\n\tDMA_RX_DIF_SGL_OVERFLOW_ERR = 263,\n\tDMA_RX_DATA_OFFSET_ERR = 264,\n\tDMA_RX_UNEXP_RX_DATA_ERR = 265,\n\tDMA_RX_DATA_OVERFLOW_ERR = 266,\n\tDMA_RX_DATA_UNDERFLOW_ERR = 267,\n\tDMA_RX_UNEXP_RETRANS_RESP_ERR = 268,\n\tTRANS_TX_RSVD0_ERR = 512,\n\tTRANS_TX_PHY_NOT_ENABLE_ERR = 513,\n\tTRANS_TX_OPEN_REJCT_WRONG_DEST_ERR = 514,\n\tTRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR = 515,\n\tTRANS_TX_OPEN_REJCT_BY_OTHER_ERR = 516,\n\tTRANS_TX_RSVD1_ERR = 517,\n\tTRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR = 518,\n\tTRANS_TX_OPEN_REJCT_STP_BUSY_ERR = 519,\n\tTRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR = 520,\n\tTRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR = 521,\n\tTRANS_TX_OPEN_REJCT_BAD_DEST_ERR = 522,\n\tTRANS_TX_OPEN_BREAK_RECEIVE_ERR = 523,\n\tTRANS_TX_LOW_PHY_POWER_ERR = 524,\n\tTRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR = 525,\n\tTRANS_TX_OPEN_TIMEOUT_ERR = 526,\n\tTRANS_TX_OPEN_REJCT_NO_DEST_ERR = 527,\n\tTRANS_TX_OPEN_RETRY_ERR = 528,\n\tTRANS_TX_RSVD2_ERR = 529,\n\tTRANS_TX_BREAK_TIMEOUT_ERR = 530,\n\tTRANS_TX_BREAK_REQUEST_ERR = 531,\n\tTRANS_TX_BREAK_RECEIVE_ERR = 532,\n\tTRANS_TX_CLOSE_TIMEOUT_ERR = 533,\n\tTRANS_TX_CLOSE_NORMAL_ERR = 534,\n\tTRANS_TX_CLOSE_PHYRESET_ERR = 535,\n\tTRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR = 536,\n\tTRANS_TX_WITH_CLOSE_COMINIT_ERR = 537,\n\tTRANS_TX_NAK_RECEIVE_ERR = 538,\n\tTRANS_TX_ACK_NAK_TIMEOUT_ERR = 539,\n\tTRANS_TX_CREDIT_TIMEOUT_ERR = 540,\n\tTRANS_TX_IPTT_CONFLICT_ERR = 541,\n\tTRANS_TX_TXFRM_TYPE_ERR = 542,\n\tTRANS_TX_TXSMP_LENGTH_ERR = 543,\n\tTRANS_RX_FRAME_CRC_ERR = 768,\n\tTRANS_RX_FRAME_DONE_ERR = 769,\n\tTRANS_RX_FRAME_ERRPRM_ERR = 770,\n\tTRANS_RX_FRAME_NO_CREDIT_ERR = 771,\n\tTRANS_RX_RSVD0_ERR = 772,\n\tTRANS_RX_FRAME_OVERRUN_ERR = 773,\n\tTRANS_RX_FRAME_NO_EOF_ERR = 774,\n\tTRANS_RX_LINK_BUF_OVERRUN_ERR = 775,\n\tTRANS_RX_BREAK_TIMEOUT_ERR = 776,\n\tTRANS_RX_BREAK_REQUEST_ERR = 777,\n\tTRANS_RX_BREAK_RECEIVE_ERR = 778,\n\tTRANS_RX_CLOSE_TIMEOUT_ERR = 779,\n\tTRANS_RX_CLOSE_NORMAL_ERR = 780,\n\tTRANS_RX_CLOSE_PHYRESET_ERR = 781,\n\tTRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR = 782,\n\tTRANS_RX_WITH_CLOSE_COMINIT_ERR = 783,\n\tTRANS_RX_DATA_LENGTH0_ERR = 784,\n\tTRANS_RX_BAD_HASH_ERR = 785,\n\tTRANS_RX_XRDY_ZERO_ERR = 786,\n\tTRANS_RX_SSP_FRAME_LEN_ERR = 787,\n\tTRANS_RX_TRANS_RX_RSVD1_ERR = 788,\n\tTRANS_RX_NO_BALANCE_ERR = 789,\n\tTRANS_RX_TRANS_RX_RSVD2_ERR = 790,\n\tTRANS_RX_TRANS_RX_RSVD3_ERR = 791,\n\tTRANS_RX_BAD_FRAME_TYPE_ERR = 792,\n\tTRANS_RX_SMP_FRAME_LEN_ERR = 793,\n\tTRANS_RX_SMP_RESP_TIMEOUT_ERR = 794,\n};\n\nenum {\n\tDMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = 1,\n\tDMI_QUIRK_SD_NO_WRITE_PROTECT = 2,\n\tDMI_QUIRK_SD_CD_ACTIVE_HIGH = 4,\n\tDMI_QUIRK_SD_CD_ENABLE_PULL_UP = 8,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDOWN = 0,\n\tUP = 1,\n};\n\nenum {\n\tDP83867_PORT_MIRROING_KEEP = 0,\n\tDP83867_PORT_MIRROING_EN = 1,\n\tDP83867_PORT_MIRROING_DIS = 2,\n};\n\nenum {\n\tDPT_START = 2,\n\tDPT_STOP = 1,\n};\n\nenum {\n\tDQF_INFO_DIRTY_B = 17,\n};\n\nenum {\n\tDQF_ROOT_SQUASH_B = 0,\n\tDQF_SYS_FILE_B = 16,\n\tDQF_PRIVATE = 17,\n};\n\nenum {\n\tDQST_LOOKUPS = 0,\n\tDQST_DROPS = 1,\n\tDQST_READS = 2,\n\tDQST_WRITES = 3,\n\tDQST_CACHE_HITS = 4,\n\tDQST_ALLOC_DQUOTS = 5,\n\tDQST_FREE_DQUOTS = 6,\n\tDQST_SYNCS = 7,\n\t_DQST_DQSTAT_LAST = 8,\n};\n\nenum {\n\tDRV_FIXED = 0,\n\tDRV_GRP0 = 1,\n\tDRV_GRP1 = 2,\n\tDRV_GRP2 = 3,\n\tDRV_GRP3 = 4,\n\tDRV_GRP4 = 5,\n\tDRV_GRP_MAX = 6,\n};\n\nenum {\n\tDSM_FUNC_ERR_HANDLE_MSI = 0,\n};\n\nenum {\n\tDSPI_REGMAP = 0,\n\tS32G_DSPI_REGMAP = 1,\n\tDSPI_XSPI_REGMAP = 2,\n\tS32G_DSPI_XSPI_REGMAP = 3,\n\tDSPI_PUSHR = 4,\n};\n\nenum {\n\tDT_BI_TCXO = 0,\n\tDT_SLEEP_CLK = 1,\n\tDT_UFS_PHY_RX_SYMBOL_0_CLK = 2,\n\tDT_UFS_PHY_RX_SYMBOL_1_CLK = 3,\n\tDT_UFS_PHY_TX_SYMBOL_0_CLK = 4,\n\tDT_UFS_CARD_RX_SYMBOL_0_CLK = 5,\n\tDT_UFS_CARD_RX_SYMBOL_1_CLK = 6,\n\tDT_UFS_CARD_TX_SYMBOL_0_CLK = 7,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK = 8,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK = 9,\n\tDT_PCIE_0_PIPE_CLK = 10,\n\tDT_PCIE_1_PIPE_CLK = 11,\n\tDT_PCIE_PHY_AUX_CLK = 12,\n\tDT_RXC0_REF_CLK = 13,\n\tDT_RXC1_REF_CLK = 14,\n};\n\nenum {\n\tDT_BI_TCXO___2 = 0,\n\tDT_SLEEP_CLK___2 = 1,\n\tDT_PCIE_0_PIPE_CLK___2 = 2,\n\tDT_PCIE_1_PIPE_CLK___2 = 3,\n\tDT_PCIE_PHY_AUX_CLK___2 = 4,\n\tDT_RXC0_REF_CLK___2 = 5,\n\tDT_UFS_PHY_RX_SYMBOL_0_CLK___2 = 6,\n\tDT_UFS_PHY_RX_SYMBOL_1_CLK___2 = 7,\n\tDT_UFS_PHY_TX_SYMBOL_0_CLK___2 = 8,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK___2 = 9,\n};\n\nenum {\n\tDT_BI_TCXO___3 = 0,\n\tDT_SLEEP_CLK___3 = 1,\n\tDT_PCIE_3_PIPE = 2,\n\tDT_PCIE_4_PIPE = 3,\n\tDT_PCIE_5_PIPE = 4,\n\tDT_PCIE_6A_PIPE = 5,\n\tDT_PCIE_6B_PIPE = 6,\n\tDT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE = 7,\n\tDT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE = 8,\n\tDT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE = 9,\n\tDT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC = 10,\n\tDT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC = 11,\n\tDT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC = 12,\n\tDT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC = 13,\n\tDT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC = 14,\n\tDT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC = 15,\n\tDT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC = 16,\n\tDT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC = 17,\n\tDT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC = 18,\n\tDT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC = 19,\n\tDT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC = 20,\n\tDT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC = 21,\n\tDT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC = 22,\n\tDT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC = 23,\n\tDT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC = 24,\n\tDT_QUSB4PHY_0_GCC_USB4_RX0_CLK = 25,\n\tDT_QUSB4PHY_0_GCC_USB4_RX1_CLK = 26,\n\tDT_QUSB4PHY_1_GCC_USB4_RX0_CLK = 27,\n\tDT_QUSB4PHY_1_GCC_USB4_RX1_CLK = 28,\n\tDT_QUSB4PHY_2_GCC_USB4_RX0_CLK = 29,\n\tDT_QUSB4PHY_2_GCC_USB4_RX1_CLK = 30,\n\tDT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK = 31,\n\tDT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 32,\n\tDT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK = 33,\n\tDT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 34,\n\tDT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK = 35,\n\tDT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 36,\n\tDT_UFS_PHY_RX_SYMBOL_0_CLK___3 = 37,\n\tDT_UFS_PHY_RX_SYMBOL_1_CLK___3 = 38,\n\tDT_UFS_PHY_TX_SYMBOL_0_CLK___3 = 39,\n};\n\nenum {\n\tDT_BI_TCXO___4 = 0,\n\tDT_SLEEP_CLK___4 = 1,\n\tDT_EMAC0_SGMIIPHY_MAC_RCLK = 2,\n\tDT_EMAC0_SGMIIPHY_MAC_TCLK = 3,\n\tDT_EMAC0_SGMIIPHY_RCLK = 4,\n\tDT_EMAC0_SGMIIPHY_TCLK = 5,\n\tDT_EMAC1_SGMIIPHY_MAC_RCLK = 6,\n\tDT_EMAC1_SGMIIPHY_MAC_TCLK = 7,\n\tDT_EMAC1_SGMIIPHY_RCLK = 8,\n\tDT_EMAC1_SGMIIPHY_TCLK = 9,\n\tDT_PCIE20_PHY_AUX_CLK = 10,\n\tDT_PCIE_1_PIPE_CLK___3 = 11,\n\tDT_PCIE_2_PIPE_CLK = 12,\n\tDT_PCIE_PIPE_CLK = 13,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK = 14,\n};\n\nenum {\n\tDT_BI_TCXO___5 = 0,\n\tDT_SLEEP_CLK___5 = 1,\n\tDT_PCIE_0_PIPE = 2,\n\tDT_PCIE_1_PIPE = 3,\n\tDT_PCIE_1_PHY_AUX = 4,\n\tDT_UFS_PHY_RX_SYMBOL_0 = 5,\n\tDT_UFS_PHY_RX_SYMBOL_1 = 6,\n\tDT_UFS_PHY_TX_SYMBOL_0 = 7,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PIPE = 8,\n};\n\nenum {\n\tDT_BI_TCXO___6 = 0,\n\tDT_SLEEP_CLK___6 = 1,\n\tDT_PCIE_0_PIPE___2 = 2,\n\tDT_PCIE_1_PIPE___2 = 3,\n\tDT_UFS_PHY_RX_SYMBOL_0___2 = 4,\n\tDT_UFS_PHY_RX_SYMBOL_1___2 = 5,\n\tDT_UFS_PHY_TX_SYMBOL_0___2 = 6,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PIPE___2 = 7,\n};\n\nenum {\n\tDT_BI_TCXO___7 = 0,\n\tDT_SLEEP_CLK___7 = 1,\n\tDT_UFS_PHY_RX_SYMBOL_0_CLK___4 = 2,\n\tDT_UFS_PHY_RX_SYMBOL_1_CLK___4 = 3,\n\tDT_UFS_PHY_TX_SYMBOL_0_CLK___4 = 4,\n\tDT_UFS_CARD_RX_SYMBOL_0_CLK___2 = 5,\n\tDT_UFS_CARD_RX_SYMBOL_1_CLK___2 = 6,\n\tDT_UFS_CARD_TX_SYMBOL_0_CLK___2 = 7,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___2 = 8,\n\tDT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC = 9,\n\tDT_GCC_USB4_PHY_DP_GMUX_CLK_SRC = 10,\n\tDT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC = 11,\n\tDT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK = 12,\n\tDT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 13,\n\tDT_QUSB4PHY_GCC_USB4_RX0_CLK = 14,\n\tDT_QUSB4PHY_GCC_USB4_RX1_CLK = 15,\n\tDT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK = 16,\n\tDT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC___2 = 17,\n\tDT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC = 18,\n\tDT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC___2 = 19,\n\tDT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK___2 = 20,\n\tDT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK___2 = 21,\n\tDT_QUSB4PHY_1_GCC_USB4_RX0_CLK___2 = 22,\n\tDT_QUSB4PHY_1_GCC_USB4_RX1_CLK___2 = 23,\n\tDT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK = 24,\n\tDT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK = 25,\n\tDT_PCIE_2A_PIPE_CLK = 26,\n\tDT_PCIE_2B_PIPE_CLK = 27,\n\tDT_PCIE_3A_PIPE_CLK = 28,\n\tDT_PCIE_3B_PIPE_CLK = 29,\n\tDT_PCIE_4_PIPE_CLK = 30,\n\tDT_RXC0_REF_CLK___3 = 31,\n\tDT_RXC1_REF_CLK___2 = 32,\n};\n\nenum {\n\tDT_BI_TCXO___8 = 0,\n\tDT_BI_TCXO_AO = 1,\n\tDT_SLEEP_CLK___8 = 2,\n\tDT_PCIE_0_PIPE_CLK___3 = 3,\n\tDT_UFS_PHY_RX_SYMBOL_0_CLK___5 = 4,\n\tDT_UFS_PHY_RX_SYMBOL_1_CLK___5 = 5,\n\tDT_UFS_PHY_TX_SYMBOL_0_CLK___5 = 6,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___3 = 7,\n};\n\nenum {\n\tDT_BI_TCXO___9 = 0,\n\tDT_BI_TCXO_AO___2 = 1,\n\tDT_SLEEP_CLK___9 = 2,\n\tDT_PCIE_0_PIPE___3 = 3,\n\tDT_PCIE_1_PIPE___3 = 4,\n\tDT_PCIE_1_PHY_AUX___2 = 5,\n\tDT_UFS_PHY_RX_SYMBOL_0___3 = 6,\n\tDT_UFS_PHY_RX_SYMBOL_1___3 = 7,\n\tDT_UFS_PHY_TX_SYMBOL_0___3 = 8,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PIPE___3 = 9,\n};\n\nenum {\n\tDT_BI_TCXO___10 = 0,\n\tDT_SLEEP_CLK___10 = 1,\n\tDT_PCIE_0_PIPE_CLK___4 = 2,\n\tDT_UFS_PHY_RX_SYMBOL_0_CLK___6 = 3,\n\tDT_UFS_PHY_RX_SYMBOL_1_CLK___6 = 4,\n\tDT_UFS_PHY_TX_SYMBOL_0_CLK___6 = 5,\n\tDT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___4 = 6,\n};\n\nenum {\n\tDT_BI_TCXO___11 = 0,\n\tDT_BI_TCXO_AO___3 = 1,\n\tDT_SLEEP_CLK___11 = 2,\n};\n\nenum {\n\tDT_BI_TCXO_PAD = 0,\n};\n\nenum {\n\tDT_TCXO_IDX = 0,\n\tDT_SLEEP_CLK_IDX = 1,\n\tDT_PCIE_0_PIPE_CLK_IDX = 2,\n\tDT_PCIE_0_PHY_AUX_CLK_IDX = 3,\n\tDT_USB3_PHY_WRAPPER_PIPE_CLK_IDX = 4,\n};\n\nenum {\n\tDT_XO = 0,\n\tDT_CLK_REF = 1,\n};\n\nenum {\n\tDT_XO___2 = 0,\n\tDT_APCS_AUX = 1,\n};\n\nenum {\n\tDT_XO___3 = 0,\n\tDT_SLEEP_CLK___12 = 1,\n\tDT_PCIE20_PHY0_PIPE_CLK = 2,\n\tDT_PCIE20_PHY1_PIPE_CLK = 3,\n\tDT_USB3_PHY0_CC_PIPE_CLK = 4,\n\tDT_GEPHY_RX_CLK = 5,\n\tDT_GEPHY_TX_CLK = 6,\n\tDT_UNIPHY_RX_CLK = 7,\n\tDT_UNIPHY_TX_CLK = 8,\n};\n\nenum {\n\tDT_XO___4 = 0,\n\tDT_SLEEP_CLK___13 = 1,\n\tDT_PCIE30_PHY0_PIPE_CLK = 2,\n\tDT_PCIE30_PHY1_PIPE_CLK = 3,\n\tDT_PCIE30_PHY2_PIPE_CLK = 4,\n\tDT_PCIE30_PHY3_PIPE_CLK = 5,\n\tDT_USB_PCIE_WRAPPER_PIPE_CLK = 6,\n};\n\nenum {\n\tDT_XO___5 = 0,\n\tDT_SLEEP_CLK___14 = 1,\n\tDT_PCIE_0_PIPE_CLK___5 = 2,\n\tDT_DSI0_PHY_PLL_OUT_DSICLK = 3,\n\tDT_DSI0_PHY_PLL_OUT_BYTECLK = 4,\n\tDT_HDMI_PHY_PLL_CLK = 5,\n};\n\nenum {\n\tDT_XO___6 = 0,\n\tDT_SLEEP_CLK___15 = 1,\n\tDT_BIAS_PLL_UBI_NC_CLK = 2,\n\tDT_PCIE30_PHY0_PIPE_CLK___2 = 3,\n\tDT_PCIE30_PHY1_PIPE_CLK___2 = 4,\n\tDT_PCIE30_PHY2_PIPE_CLK___2 = 5,\n\tDT_PCIE30_PHY3_PIPE_CLK___2 = 6,\n\tDT_USB3PHY_0_CC_PIPE_CLK = 7,\n};\n\nenum {\n\tDT_XO___7 = 0,\n\tDT_SLEEP_CLK___16 = 1,\n\tDT_PCIE_2LANE_PHY_PIPE_CLK = 2,\n\tDT_PCIE_2LANE_PHY_PIPE_CLK_X1 = 3,\n\tDT_USB_PCIE_WRAPPER_PIPE_CLK___2 = 4,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tEC_MSG_TX_HEADER_BYTES = 3,\n\tEC_MSG_TX_TRAILER_BYTES = 1,\n\tEC_MSG_TX_PROTO_BYTES = 4,\n\tEC_MSG_RX_PROTO_BYTES = 3,\n\tEC_PROTO2_MSG_BYTES = 256,\n\tEC_MAX_MSG_BYTES = 65536,\n};\n\nenum {\n\tEDSR = 0,\n\tEDMR = 1,\n\tEDTRR = 2,\n\tEDRRR = 3,\n\tEESR = 4,\n\tEESIPR = 5,\n\tTDLAR = 6,\n\tTDFAR = 7,\n\tTDFXR = 8,\n\tTDFFR = 9,\n\tRDLAR = 10,\n\tRDFAR = 11,\n\tRDFXR = 12,\n\tRDFFR = 13,\n\tTRSCER = 14,\n\tRMFCR = 15,\n\tTFTR = 16,\n\tFDR = 17,\n\tRMCR = 18,\n\tEDOCR = 19,\n\tTFUCR = 20,\n\tRFOCR = 21,\n\tRMIIMODE = 22,\n\tFCFTR = 23,\n\tRPADIR = 24,\n\tTRIMD = 25,\n\tRBWAR = 26,\n\tTBRAR = 27,\n\tECMR = 28,\n\tECSR = 29,\n\tECSIPR = 30,\n\tPIR = 31,\n\tPSR = 32,\n\tRDMLR = 33,\n\tPIPR = 34,\n\tRFLR = 35,\n\tIPGR = 36,\n\tAPR = 37,\n\tMPR = 38,\n\tPFTCR = 39,\n\tPFRCR = 40,\n\tRFCR = 41,\n\tRFCF = 42,\n\tTPAUSER = 43,\n\tTPAUSECR = 44,\n\tBCFR = 45,\n\tBCFRR = 46,\n\tGECMR = 47,\n\tBCULR = 48,\n\tMAHR = 49,\n\tMALR = 50,\n\tTROCR = 51,\n\tCDCR = 52,\n\tLCCR = 53,\n\tCNDCR = 54,\n\tCEFCR = 55,\n\tFRECR = 56,\n\tTSFRCR = 57,\n\tTLFRCR = 58,\n\tCERCR = 59,\n\tCEECR = 60,\n\tMAFCR = 61,\n\tRTRATE = 62,\n\tCSMR = 63,\n\tRMII_MII = 64,\n\tARSTR = 65,\n\tTSU_CTRST = 66,\n\tTSU_FWEN0 = 67,\n\tTSU_FWEN1 = 68,\n\tTSU_FCM = 69,\n\tTSU_BSYSL0 = 70,\n\tTSU_BSYSL1 = 71,\n\tTSU_PRISL0 = 72,\n\tTSU_PRISL1 = 73,\n\tTSU_FWSL0 = 74,\n\tTSU_FWSL1 = 75,\n\tTSU_FWSLC = 76,\n\tTSU_QTAG0 = 77,\n\tTSU_QTAG1 = 78,\n\tTSU_QTAGM0 = 79,\n\tTSU_QTAGM1 = 80,\n\tTSU_FWSR = 81,\n\tTSU_FWINMK = 82,\n\tTSU_ADQT0 = 83,\n\tTSU_ADQT1 = 84,\n\tTSU_VTAG0 = 85,\n\tTSU_VTAG1 = 86,\n\tTSU_ADSBSY = 87,\n\tTSU_TEN = 88,\n\tTSU_POST1 = 89,\n\tTSU_POST2 = 90,\n\tTSU_POST3 = 91,\n\tTSU_POST4 = 92,\n\tTSU_ADRH0 = 93,\n\tTXNLCR0 = 94,\n\tTXALCR0 = 95,\n\tRXNLCR0 = 96,\n\tRXALCR0 = 97,\n\tFWNLCR0 = 98,\n\tFWALCR0 = 99,\n\tTXNLCR1 = 100,\n\tTXALCR1 = 101,\n\tRXNLCR1 = 102,\n\tRXALCR1 = 103,\n\tFWNLCR1 = 104,\n\tFWALCR1 = 105,\n\tSH_ETH_MAX_REGISTER_OFFSET = 106,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_CODE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_CODE_OK = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE_OPEN = 2,\n\tETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT = 3,\n\tETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT = 4,\n\tETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH = 5,\n\tETHTOOL_A_CABLE_RESULT_CODE_NOISE = 6,\n\tETHTOOL_A_CABLE_RESULT_CODE_RESOLUTION_NOT_POSSIBLE = 7,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_STAT_EEE_WAKEUP = 0,\n\tETHTOOL_STAT_SKB_ALLOC_ERR = 1,\n\tETHTOOL_STAT_REFILL_ERR = 2,\n\tETHTOOL_XDP_REDIRECT = 3,\n\tETHTOOL_XDP_PASS = 4,\n\tETHTOOL_XDP_DROP = 5,\n\tETHTOOL_XDP_TX = 6,\n\tETHTOOL_XDP_TX_ERR = 7,\n\tETHTOOL_XDP_XMIT = 8,\n\tETHTOOL_XDP_XMIT_ERR = 9,\n\tETHTOOL_MAX_STATS = 10,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_XDP_REDIRECT___2 = 0,\n\tETHTOOL_XDP_PASS___2 = 1,\n\tETHTOOL_XDP_DROP___2 = 2,\n\tETHTOOL_XDP_TX___2 = 3,\n\tETHTOOL_XDP_TX_ERR___2 = 4,\n\tETHTOOL_XDP_XMIT___2 = 5,\n\tETHTOOL_XDP_XMIT_ERR___2 = 6,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENTFS_SAVE_MODE = 65536,\n\tEVENTFS_SAVE_UID = 131072,\n\tEVENTFS_SAVE_GID = 262144,\n};\n\nenum {\n\tEVENT_CMD_COMPLETE = 0,\n\tEVENT_XFER_COMPLETE = 1,\n\tEVENT_DATA_COMPLETE = 2,\n\tEVENT_DATA_ERROR = 3,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_DISABLED = 32,\n\tEVENT_FILE_FL_TRIGGER_MODE = 64,\n\tEVENT_FILE_FL_TRIGGER_COND = 128,\n\tEVENT_FILE_FL_PID_FILTER = 256,\n\tEVENT_FILE_FL_WAS_ENABLED = 512,\n\tEVENT_FILE_FL_FREED = 1024,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEVENT_TRIGGER_FL_PROBE = 1,\n\tEVENT_TRIGGER_FL_COUNT = 2,\n};\n\nenum {\n\tEXT4_FC_REASON_XATTR = 0,\n\tEXT4_FC_REASON_CROSS_RENAME = 1,\n\tEXT4_FC_REASON_JOURNAL_FLAG_CHANGE = 2,\n\tEXT4_FC_REASON_NOMEM = 3,\n\tEXT4_FC_REASON_SWAP_BOOT = 4,\n\tEXT4_FC_REASON_RESIZE = 5,\n\tEXT4_FC_REASON_RENAME_DIR = 6,\n\tEXT4_FC_REASON_FALLOC_RANGE = 7,\n\tEXT4_FC_REASON_INODE_JOURNAL_DATA = 8,\n\tEXT4_FC_REASON_ENCRYPTED_FILENAME = 9,\n\tEXT4_FC_REASON_MIGRATE = 10,\n\tEXT4_FC_REASON_VERITY = 11,\n\tEXT4_FC_REASON_MOVE_EXT = 12,\n\tEXT4_FC_REASON_MAX = 13,\n};\n\nenum {\n\tEXT4_FC_STATUS_OK = 0,\n\tEXT4_FC_STATUS_INELIGIBLE = 1,\n\tEXT4_FC_STATUS_SKIPPED = 2,\n\tEXT4_FC_STATUS_FAILED = 3,\n};\n\nenum {\n\tEXT4_FLAGS_RESIZING = 0,\n\tEXT4_FLAGS_SHUTDOWN = 1,\n\tEXT4_FLAGS_BDEV_IS_DAX = 2,\n\tEXT4_FLAGS_EMERGENCY_RO = 3,\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nenum {\n\tEXT4_MF_MNTDIR_SAMPLED = 0,\n\tEXT4_MF_FC_INELIGIBLE = 1,\n\tEXT4_MF_JOURNAL_DESTROY = 2,\n};\n\nenum {\n\tEXT4_STATE_NEW = 0,\n\tEXT4_STATE_XATTR = 1,\n\tEXT4_STATE_NO_EXPAND = 2,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 3,\n\tEXT4_STATE_EXT_MIGRATE = 4,\n\tEXT4_STATE_NEWENTRY = 5,\n\tEXT4_STATE_MAY_INLINE_DATA = 6,\n\tEXT4_STATE_EXT_PRECACHED = 7,\n\tEXT4_STATE_LUSTRE_EA_INODE = 8,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 9,\n\tEXT4_STATE_FC_COMMITTING = 10,\n\tEXT4_STATE_FC_FLUSHING_DATA = 11,\n\tEXT4_STATE_ORPHAN_FILE = 12,\n};\n\nenum {\n\tFAN53526_CHIP_ID_01 = 1,\n};\n\nenum {\n\tFAN53526_CHIP_REV_08 = 8,\n};\n\nenum {\n\tFAN53555_CHIP_ID_00 = 0,\n\tFAN53555_CHIP_ID_01 = 1,\n\tFAN53555_CHIP_ID_02 = 2,\n\tFAN53555_CHIP_ID_03 = 3,\n\tFAN53555_CHIP_ID_04 = 4,\n\tFAN53555_CHIP_ID_05 = 5,\n\tFAN53555_CHIP_ID_08 = 8,\n};\n\nenum {\n\tFAN53555_CHIP_REV_00 = 3,\n\tFAN53555_CHIP_REV_13 = 15,\n};\n\nenum {\n\tFAN53555_VSEL_ID_0 = 0,\n\tFAN53555_VSEL_ID_1 = 1,\n};\n\nenum {\n\tFAN_EVENT_INIT = 0,\n\tFAN_EVENT_REPORTED = 1,\n\tFAN_EVENT_ANSWERED = 2,\n\tFAN_EVENT_CANCELED = 3,\n};\n\nenum {\n\tFATTR4_CLONE_BLKSIZE = 77,\n\tFATTR4_SPACE_FREED = 78,\n\tFATTR4_CHANGE_ATTR_TYPE = 79,\n\tFATTR4_SEC_LABEL = 80,\n};\n\nenum {\n\tFATTR4_DIR_NOTIF_DELAY = 56,\n\tFATTR4_DIRENT_NOTIF_DELAY = 57,\n\tFATTR4_DACL = 58,\n\tFATTR4_SACL = 59,\n\tFATTR4_CHANGE_POLICY = 60,\n\tFATTR4_FS_STATUS = 61,\n\tFATTR4_FS_LAYOUT_TYPES = 62,\n\tFATTR4_LAYOUT_HINT = 63,\n\tFATTR4_LAYOUT_TYPES = 64,\n\tFATTR4_LAYOUT_BLKSIZE = 65,\n\tFATTR4_LAYOUT_ALIGNMENT = 66,\n\tFATTR4_FS_LOCATIONS_INFO = 67,\n\tFATTR4_MDSTHRESHOLD = 68,\n\tFATTR4_RETENTION_GET = 69,\n\tFATTR4_RETENTION_SET = 70,\n\tFATTR4_RETENTEVT_GET = 71,\n\tFATTR4_RETENTEVT_SET = 72,\n\tFATTR4_RETENTION_HOLD = 73,\n\tFATTR4_MODE_SET_MASKED = 74,\n\tFATTR4_SUPPATTR_EXCLCREAT = 75,\n\tFATTR4_FS_CHARSET_CAP = 76,\n};\n\nenum {\n\tFATTR4_MODE_UMASK = 81,\n};\n\nenum {\n\tFATTR4_OPEN_ARGUMENTS = 86,\n};\n\nenum {\n\tFATTR4_SUPPORTED_ATTRS = 0,\n\tFATTR4_TYPE = 1,\n\tFATTR4_FH_EXPIRE_TYPE = 2,\n\tFATTR4_CHANGE = 3,\n\tFATTR4_SIZE = 4,\n\tFATTR4_LINK_SUPPORT = 5,\n\tFATTR4_SYMLINK_SUPPORT = 6,\n\tFATTR4_NAMED_ATTR = 7,\n\tFATTR4_FSID = 8,\n\tFATTR4_UNIQUE_HANDLES = 9,\n\tFATTR4_LEASE_TIME = 10,\n\tFATTR4_RDATTR_ERROR = 11,\n\tFATTR4_ACL = 12,\n\tFATTR4_ACLSUPPORT = 13,\n\tFATTR4_ARCHIVE = 14,\n\tFATTR4_CANSETTIME = 15,\n\tFATTR4_CASE_INSENSITIVE = 16,\n\tFATTR4_CASE_PRESERVING = 17,\n\tFATTR4_CHOWN_RESTRICTED = 18,\n\tFATTR4_FILEHANDLE = 19,\n\tFATTR4_FILEID = 20,\n\tFATTR4_FILES_AVAIL = 21,\n\tFATTR4_FILES_FREE = 22,\n\tFATTR4_FILES_TOTAL = 23,\n\tFATTR4_FS_LOCATIONS = 24,\n\tFATTR4_HIDDEN = 25,\n\tFATTR4_HOMOGENEOUS = 26,\n\tFATTR4_MAXFILESIZE = 27,\n\tFATTR4_MAXLINK = 28,\n\tFATTR4_MAXNAME = 29,\n\tFATTR4_MAXREAD = 30,\n\tFATTR4_MAXWRITE = 31,\n\tFATTR4_MIMETYPE = 32,\n\tFATTR4_MODE = 33,\n\tFATTR4_NO_TRUNC = 34,\n\tFATTR4_NUMLINKS = 35,\n\tFATTR4_OWNER = 36,\n\tFATTR4_OWNER_GROUP = 37,\n\tFATTR4_QUOTA_AVAIL_HARD = 38,\n\tFATTR4_QUOTA_AVAIL_SOFT = 39,\n\tFATTR4_QUOTA_USED = 40,\n\tFATTR4_RAWDEV = 41,\n\tFATTR4_SPACE_AVAIL = 42,\n\tFATTR4_SPACE_FREE = 43,\n\tFATTR4_SPACE_TOTAL = 44,\n\tFATTR4_SPACE_USED = 45,\n\tFATTR4_SYSTEM = 46,\n\tFATTR4_TIME_ACCESS = 47,\n\tFATTR4_TIME_ACCESS_SET = 48,\n\tFATTR4_TIME_BACKUP = 49,\n\tFATTR4_TIME_CREATE = 50,\n\tFATTR4_TIME_DELTA = 51,\n\tFATTR4_TIME_METADATA = 52,\n\tFATTR4_TIME_MODIFY = 53,\n\tFATTR4_TIME_MODIFY_SET = 54,\n\tFATTR4_MOUNTED_ON_FILEID = 55,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_ACCESS = 84,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_MODIFY = 85,\n};\n\nenum {\n\tFATTR4_XATTR_SUPPORT = 82,\n};\n\nenum {\n\tFBCON_LOGO_CANSHOW = -1,\n\tFBCON_LOGO_DRAW = -2,\n\tFBCON_LOGO_DONTSHOW = -3,\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nenum {\n\tFILEID_HIGH_OFF = 0,\n\tFILEID_LOW_OFF = 1,\n\tFILE_I_TYPE_OFF = 2,\n\tEMBED_FH_OFF = 3,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_RDYN_STRING = 3,\n\tFILTER_PTR_STRING = 4,\n\tFILTER_TRACE_FN = 5,\n\tFILTER_CPUMASK = 6,\n\tFILTER_COMM = 7,\n\tFILTER_CPU = 8,\n\tFILTER_STACKTRACE = 9,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_MISSING_BRACE_OPEN = 5,\n\tFILT_ERR_MISSING_BRACE_CLOSE = 6,\n\tFILT_ERR_OPERAND_TOO_LONG = 7,\n\tFILT_ERR_EXPECT_STRING = 8,\n\tFILT_ERR_EXPECT_DIGIT = 9,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 10,\n\tFILT_ERR_FIELD_NOT_FOUND = 11,\n\tFILT_ERR_ILLEGAL_INTVAL = 12,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 13,\n\tFILT_ERR_TOO_MANY_PREDS = 14,\n\tFILT_ERR_INVALID_FILTER = 15,\n\tFILT_ERR_INVALID_CPULIST = 16,\n\tFILT_ERR_IP_FIELD_ONLY = 17,\n\tFILT_ERR_INVALID_VALUE = 18,\n\tFILT_ERR_NO_FUNCTION = 19,\n\tFILT_ERR_ERRNO = 20,\n\tFILT_ERR_NO_FILTER = 21,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tF_TX_CHK_AUTO_OFF = -2147483648,\n\tF_TX_CHK_AUTO_ON = 1073741824,\n\tF_M_RX_RAM_DIS = 16777216,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGHES_SEV_NO = 0,\n\tGHES_SEV_CORRECTED = 1,\n\tGHES_SEV_RECOVERABLE = 2,\n\tGHES_SEV_PANIC = 3,\n};\n\nenum {\n\tGLB_GPIO_CLK_DEB_ENA = -2147483648,\n\tGLB_GPIO_CLK_DBG_MSK = 1006632960,\n\tGLB_GPIO_INT_RST_D3_DIS = 32768,\n\tGLB_GPIO_LED_PAD_SPEED_UP = 16384,\n\tGLB_GPIO_STAT_RACE_DIS = 8192,\n\tGLB_GPIO_TEST_SEL_MSK = 6144,\n\tGLB_GPIO_TEST_SEL_BASE = 2048,\n\tGLB_GPIO_RAND_ENA = 1024,\n\tGLB_GPIO_RAND_BIT_1 = 512,\n};\n\nenum {\n\tGMAC_CTRL = 3840,\n\tGPHY_CTRL = 3844,\n\tGMAC_IRQ_SRC = 3848,\n\tGMAC_IRQ_MSK = 3852,\n\tGMAC_LINK_CTRL = 3856,\n\tWOL_CTRL_STAT = 3872,\n\tWOL_MATCH_CTL = 3874,\n\tWOL_MATCH_RES = 3875,\n\tWOL_MAC_ADDR = 3876,\n\tWOL_PATT_RPTR = 3884,\n\tWOL_PATT_LEN_LO = 3888,\n\tWOL_PATT_LEN_HI = 3892,\n\tWOL_PATT_CNT_0 = 3896,\n\tWOL_PATT_CNT_4 = 3900,\n};\n\nenum {\n\tGMAC_TI_ST_VAL = 3604,\n\tGMAC_TI_ST_CTRL = 3608,\n\tGMAC_TI_ST_TST = 3610,\n};\n\nenum {\n\tGMC_SET_RST = 32768,\n\tGMC_SEC_RST_OFF = 16384,\n\tGMC_BYP_MACSECRX_ON = 8192,\n\tGMC_BYP_MACSECRX_OFF = 4096,\n\tGMC_BYP_MACSECTX_ON = 2048,\n\tGMC_BYP_MACSECTX_OFF = 1024,\n\tGMC_BYP_RETR_ON = 512,\n\tGMC_BYP_RETR_OFF = 256,\n\tGMC_H_BURST_ON = 128,\n\tGMC_H_BURST_OFF = 64,\n\tGMC_F_LOOPB_ON = 32,\n\tGMC_F_LOOPB_OFF = 16,\n\tGMC_PAUSE_ON = 8,\n\tGMC_PAUSE_OFF = 4,\n\tGMC_RST_CLR = 2,\n\tGMC_RST_SET = 1,\n};\n\nenum {\n\tGMLC_RST_CLR = 2,\n\tGMLC_RST_SET = 1,\n};\n\nenum {\n\tGMR_FS_LEN = 2147418112,\n\tGMR_FS_VLAN = 8192,\n\tGMR_FS_JABBER = 4096,\n\tGMR_FS_UN_SIZE = 2048,\n\tGMR_FS_MC = 1024,\n\tGMR_FS_BC = 512,\n\tGMR_FS_RX_OK = 256,\n\tGMR_FS_GOOD_FC = 128,\n\tGMR_FS_BAD_FC = 64,\n\tGMR_FS_MII_ERR = 32,\n\tGMR_FS_LONG_ERR = 16,\n\tGMR_FS_FRAGMENT = 8,\n\tGMR_FS_CRC_ERR = 2,\n\tGMR_FS_RX_FF_OV = 1,\n\tGMR_FS_ANY_ERR = 6267,\n};\n\nenum {\n\tGMT_ST_START = 4,\n\tGMT_ST_STOP = 2,\n\tGMT_ST_CLR_IRQ = 1,\n};\n\nenum {\n\tGM_GPCR_PROM_ENA = 16384,\n\tGM_GPCR_FC_TX_DIS = 8192,\n\tGM_GPCR_TX_ENA = 4096,\n\tGM_GPCR_RX_ENA = 2048,\n\tGM_GPCR_BURST_ENA = 1024,\n\tGM_GPCR_LOOP_ENA = 512,\n\tGM_GPCR_PART_ENA = 256,\n\tGM_GPCR_GIGS_ENA = 128,\n\tGM_GPCR_FL_PASS = 64,\n\tGM_GPCR_DUP_FULL = 32,\n\tGM_GPCR_FC_RX_DIS = 16,\n\tGM_GPCR_SPEED_100 = 8,\n\tGM_GPCR_AU_DUP_DIS = 4,\n\tGM_GPCR_AU_FCT_DIS = 2,\n\tGM_GPCR_AU_SPD_DIS = 1,\n};\n\nenum {\n\tGM_GP_STAT = 0,\n\tGM_GP_CTRL = 4,\n\tGM_TX_CTRL = 8,\n\tGM_RX_CTRL = 12,\n\tGM_TX_FLOW_CTRL = 16,\n\tGM_TX_PARAM = 20,\n\tGM_SERIAL_MODE = 24,\n\tGM_SRC_ADDR_1L = 28,\n\tGM_SRC_ADDR_1M = 32,\n\tGM_SRC_ADDR_1H = 36,\n\tGM_SRC_ADDR_2L = 40,\n\tGM_SRC_ADDR_2M = 44,\n\tGM_SRC_ADDR_2H = 48,\n\tGM_MC_ADDR_H1 = 52,\n\tGM_MC_ADDR_H2 = 56,\n\tGM_MC_ADDR_H3 = 60,\n\tGM_MC_ADDR_H4 = 64,\n\tGM_TX_IRQ_SRC = 68,\n\tGM_RX_IRQ_SRC = 72,\n\tGM_TR_IRQ_SRC = 76,\n\tGM_TX_IRQ_MSK = 80,\n\tGM_RX_IRQ_MSK = 84,\n\tGM_TR_IRQ_MSK = 88,\n\tGM_SMI_CTRL = 128,\n\tGM_SMI_DATA = 132,\n\tGM_PHY_ADDR = 136,\n\tGM_MIB_CNT_BASE = 256,\n\tGM_MIB_CNT_END = 604,\n};\n\nenum {\n\tGM_IS_TX_CO_OV = 32,\n\tGM_IS_RX_CO_OV = 16,\n\tGM_IS_TX_FF_UR = 8,\n\tGM_IS_TX_COMPL = 4,\n\tGM_IS_RX_FF_OR = 2,\n\tGM_IS_RX_COMPL = 1,\n};\n\nenum {\n\tGM_PAR_MIB_CLR = 32,\n\tGM_PAR_MIB_TST = 16,\n};\n\nenum {\n\tGM_RXCR_UCF_ENA = 32768,\n\tGM_RXCR_MCF_ENA = 16384,\n\tGM_RXCR_CRC_DIS = 8192,\n\tGM_RXCR_PASS_FC = 4096,\n};\n\nenum {\n\tGM_RXF_UC_OK = 256,\n\tGM_RXF_BC_OK = 264,\n\tGM_RXF_MPAUSE = 272,\n\tGM_RXF_MC_OK = 280,\n\tGM_RXF_FCS_ERR = 288,\n\tGM_RXO_OK_LO = 304,\n\tGM_RXO_OK_HI = 312,\n\tGM_RXO_ERR_LO = 320,\n\tGM_RXO_ERR_HI = 328,\n\tGM_RXF_SHT = 336,\n\tGM_RXE_FRAG = 344,\n\tGM_RXF_64B = 352,\n\tGM_RXF_127B = 360,\n\tGM_RXF_255B = 368,\n\tGM_RXF_511B = 376,\n\tGM_RXF_1023B = 384,\n\tGM_RXF_1518B = 392,\n\tGM_RXF_MAX_SZ = 400,\n\tGM_RXF_LNG_ERR = 408,\n\tGM_RXF_JAB_PKT = 416,\n\tGM_RXE_FIFO_OV = 432,\n\tGM_TXF_UC_OK = 448,\n\tGM_TXF_BC_OK = 456,\n\tGM_TXF_MPAUSE = 464,\n\tGM_TXF_MC_OK = 472,\n\tGM_TXO_OK_LO = 480,\n\tGM_TXO_OK_HI = 488,\n\tGM_TXF_64B = 496,\n\tGM_TXF_127B = 504,\n\tGM_TXF_255B = 512,\n\tGM_TXF_511B = 520,\n\tGM_TXF_1023B = 528,\n\tGM_TXF_1518B = 536,\n\tGM_TXF_MAX_SZ = 544,\n\tGM_TXF_COL = 560,\n\tGM_TXF_LAT_COL = 568,\n\tGM_TXF_ABO_COL = 576,\n\tGM_TXF_MUL_COL = 584,\n\tGM_TXF_SNG_COL = 592,\n\tGM_TXE_FIFO_UR = 600,\n};\n\nenum {\n\tGM_SMI_CT_PHY_A_MSK = 63488,\n\tGM_SMI_CT_REG_A_MSK = 1984,\n\tGM_SMI_CT_OP_RD = 32,\n\tGM_SMI_CT_RD_VAL = 16,\n\tGM_SMI_CT_BUSY = 8,\n};\n\nenum {\n\tGM_SMOD_DATABL_MSK = 63488,\n\tGM_SMOD_LIMIT_4 = 1024,\n\tGM_SMOD_VLAN_ENA = 512,\n\tGM_SMOD_JUMBO_ENA = 256,\n\tGM_NEW_FLOW_CTRL = 64,\n\tGM_SMOD_IPG_MSK = 31,\n};\n\nenum {\n\tGM_TXCR_FORCE_JAM = 32768,\n\tGM_TXCR_CRC_DIS = 16384,\n\tGM_TXCR_PAD_DIS = 8192,\n\tGM_TXCR_COL_THR_MSK = 7168,\n};\n\nenum {\n\tGM_TXPA_JAMLEN_MSK = 49152,\n\tGM_TXPA_JAMIPG_MSK = 15872,\n\tGM_TXPA_JAMDAT_MSK = 496,\n\tGM_TXPA_BO_LIM_MSK = 15,\n\tTX_JAM_LEN_DEF = 3,\n\tTX_JAM_IPG_DEF = 11,\n\tTX_IPG_JAM_DEF = 28,\n\tTX_BOF_LIM_DEF = 4,\n};\n\nenum {\n\tGPC_TX_PAUSE = 1073741824,\n\tGPC_RX_PAUSE = 536870912,\n\tGPC_SPEED = 402653184,\n\tGPC_LINK = 67108864,\n\tGPC_DUPLEX = 33554432,\n\tGPC_CLOCK = 16777216,\n\tGPC_PDOWN = 8388608,\n\tGPC_TSTMODE = 4194304,\n\tGPC_REG18 = 2097152,\n\tGPC_REG12SEL = 1572864,\n\tGPC_REG18SEL = 393216,\n\tGPC_SPILOCK = 65536,\n\tGPC_LEDMUX = 49152,\n\tGPC_INTPOL = 8192,\n\tGPC_DETECT = 4096,\n\tGPC_1000HD = 2048,\n\tGPC_SLAVE = 1024,\n\tGPC_PAUSE = 512,\n\tGPC_LEDCTL = 192,\n\tGPC_RST_CLR = 2,\n\tGPC_RST_SET = 1,\n};\n\nenum {\n\tGPIO_BASE = 0,\n\tIOCFG_RT_BASE = 1,\n\tIOCFG_RB_BASE = 2,\n\tIOCFG_LT_BASE = 3,\n\tIOCFG_LB_BASE = 4,\n\tIOCFG_TR_BASE = 5,\n\tIOCFG_TL_BASE = 6,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tGP_LAST = 174,\n\tPIN_DCUTCK_LPDCLK = 175,\n\tPIN_DCUTDI_LPDI = 176,\n\tPIN_DCUTMS = 177,\n\tPIN_DCUTRST_N = 178,\n\tPIN_DU_DOTCLKIN = 179,\n\tPIN_EXTALR = 180,\n\tPIN_FSCLKST = 181,\n\tPIN_FSCLKST_N = 182,\n\tPIN_PRESETOUT_N = 183,\n\tPIN_VDDQ_AVB = 184,\n\tPIN_VDDQ_GE = 185,\n};\n\nenum {\n\tGP_LAST___2 = 209,\n\tPIN_ASEBRK = 210,\n\tPIN_AVB_MDC = 211,\n\tPIN_AVB_MDIO = 212,\n\tPIN_AVB_TD0 = 213,\n\tPIN_AVB_TD1 = 214,\n\tPIN_AVB_TD2 = 215,\n\tPIN_AVB_TD3 = 216,\n\tPIN_AVB_TXC = 217,\n\tPIN_AVB_TX_CTL = 218,\n\tPIN_FSCLKST_N___2 = 219,\n\tPIN_MLB_REF = 220,\n\tPIN_PRESETOUT_N___2 = 221,\n\tPIN_TCK = 222,\n\tPIN_TDI = 223,\n\tPIN_TMS = 224,\n\tPIN_TRST_N = 225,\n\tPIN_VDDQ_AVB0 = 226,\n};\n\nenum {\n\tGP_LAST___3 = 227,\n\tPIN_ASEBRK___2 = 228,\n\tPIN_AVB_MDIO___2 = 229,\n\tPIN_AVB_RD0 = 230,\n\tPIN_AVB_RD1 = 231,\n\tPIN_AVB_RD2 = 232,\n\tPIN_AVB_RD3 = 233,\n\tPIN_AVB_RXC = 234,\n\tPIN_AVB_RX_CTL = 235,\n\tPIN_AVB_TD0___2 = 236,\n\tPIN_AVB_TD1___2 = 237,\n\tPIN_AVB_TD2___2 = 238,\n\tPIN_AVB_TD3___2 = 239,\n\tPIN_AVB_TXC___2 = 240,\n\tPIN_AVB_TXCREFCLK = 241,\n\tPIN_AVB_TX_CTL___2 = 242,\n\tPIN_DU_DOTCLKIN0 = 243,\n\tPIN_DU_DOTCLKIN1 = 244,\n\tPIN_DU_DOTCLKIN2 = 245,\n\tPIN_EXTALR___2 = 246,\n\tPIN_FSCLKST___2 = 247,\n\tPIN_MLB_REF___2 = 248,\n\tPIN_PRESETOUT_N___3 = 249,\n\tPIN_QSPI0_IO2 = 250,\n\tPIN_QSPI0_IO3 = 251,\n\tPIN_QSPI0_MISO_IO1 = 252,\n\tPIN_QSPI0_MOSI_IO0 = 253,\n\tPIN_QSPI0_SPCLK = 254,\n\tPIN_QSPI0_SSL = 255,\n\tPIN_QSPI1_IO2 = 256,\n\tPIN_QSPI1_IO3 = 257,\n\tPIN_QSPI1_MISO_IO1 = 258,\n\tPIN_QSPI1_MOSI_IO0 = 259,\n\tPIN_QSPI1_SPCLK = 260,\n\tPIN_QSPI1_SSL = 261,\n\tPIN_PRESET_N = 262,\n\tPIN_RPC_INT_N = 263,\n\tPIN_RPC_RESET_N = 264,\n\tPIN_RPC_WP_N = 265,\n\tPIN_TCK___2 = 266,\n\tPIN_TDI___2 = 267,\n\tPIN_TDO = 268,\n\tPIN_TMS___2 = 269,\n\tPIN_TRST_N___2 = 270,\n};\n\nenum {\n\tGP_LAST___4 = 244,\n\tPIN_VDDQ_AVB0___2 = 245,\n\tPIN_VDDQ_AVB1 = 246,\n\tPIN_VDDQ_AVB2 = 247,\n};\n\nenum {\n\tGP_LAST___5 = 227,\n\tPIN_ASEBRK___3 = 228,\n\tPIN_AVB_MDIO___3 = 229,\n\tPIN_AVB_RD0___2 = 230,\n\tPIN_AVB_RD1___2 = 231,\n\tPIN_AVB_RD2___2 = 232,\n\tPIN_AVB_RD3___2 = 233,\n\tPIN_AVB_RXC___2 = 234,\n\tPIN_AVB_RX_CTL___2 = 235,\n\tPIN_AVB_TD0___3 = 236,\n\tPIN_AVB_TD1___3 = 237,\n\tPIN_AVB_TD2___3 = 238,\n\tPIN_AVB_TD3___3 = 239,\n\tPIN_AVB_TXC___3 = 240,\n\tPIN_AVB_TXCREFCLK___2 = 241,\n\tPIN_AVB_TX_CTL___3 = 242,\n\tPIN_DU_DOTCLKIN0___2 = 243,\n\tPIN_DU_DOTCLKIN1___2 = 244,\n\tPIN_DU_DOTCLKIN2___2 = 245,\n\tPIN_DU_DOTCLKIN3 = 246,\n\tPIN_EXTALR___3 = 247,\n\tPIN_FSCLKST_N___3 = 248,\n\tPIN_MLB_REF___3 = 249,\n\tPIN_PRESETOUT_N___4 = 250,\n\tPIN_QSPI0_IO2___2 = 251,\n\tPIN_QSPI0_IO3___2 = 252,\n\tPIN_QSPI0_MISO_IO1___2 = 253,\n\tPIN_QSPI0_MOSI_IO0___2 = 254,\n\tPIN_QSPI0_SPCLK___2 = 255,\n\tPIN_QSPI0_SSL___2 = 256,\n\tPIN_QSPI1_IO2___2 = 257,\n\tPIN_QSPI1_IO3___2 = 258,\n\tPIN_QSPI1_MISO_IO1___2 = 259,\n\tPIN_QSPI1_MOSI_IO0___2 = 260,\n\tPIN_QSPI1_SPCLK___2 = 261,\n\tPIN_QSPI1_SSL___2 = 262,\n\tPIN_RPC_INT_N___2 = 263,\n\tPIN_RPC_RESET_N___2 = 264,\n\tPIN_RPC_WP_N___2 = 265,\n\tPIN_TCK___3 = 266,\n\tPIN_TDI___3 = 267,\n\tPIN_TDO___2 = 268,\n\tPIN_TMS___3 = 269,\n\tPIN_TRST_N___3 = 270,\n};\n\nenum {\n\tGP_LAST___6 = 269,\n\tPIN_VDDQ_AVB0___3 = 270,\n\tPIN_VDDQ_AVB1___2 = 271,\n\tPIN_VDDQ_AVB2___2 = 272,\n\tPIN_VDDQ_TSN0 = 273,\n};\n\nenum {\n\tGP_LAST___7 = 227,\n\tPIN_ASEBRK___4 = 228,\n\tPIN_AVB_MDIO___4 = 229,\n\tPIN_AVB_RD0___3 = 230,\n\tPIN_AVB_RD1___3 = 231,\n\tPIN_AVB_RD2___3 = 232,\n\tPIN_AVB_RD3___3 = 233,\n\tPIN_AVB_RXC___3 = 234,\n\tPIN_AVB_RX_CTL___3 = 235,\n\tPIN_AVB_TD0___4 = 236,\n\tPIN_AVB_TD1___4 = 237,\n\tPIN_AVB_TD2___4 = 238,\n\tPIN_AVB_TD3___4 = 239,\n\tPIN_AVB_TXC___4 = 240,\n\tPIN_AVB_TXCREFCLK___3 = 241,\n\tPIN_AVB_TX_CTL___4 = 242,\n\tPIN_DU_DOTCLKIN0___3 = 243,\n\tPIN_DU_DOTCLKIN1___3 = 244,\n\tPIN_DU_DOTCLKIN3___2 = 245,\n\tPIN_EXTALR___4 = 246,\n\tPIN_FSCLKST___3 = 247,\n\tPIN_MLB_REF___4 = 248,\n\tPIN_PRESETOUT_N___5 = 249,\n\tPIN_QSPI0_IO2___3 = 250,\n\tPIN_QSPI0_IO3___3 = 251,\n\tPIN_QSPI0_MISO_IO1___3 = 252,\n\tPIN_QSPI0_MOSI_IO0___3 = 253,\n\tPIN_QSPI0_SPCLK___3 = 254,\n\tPIN_QSPI0_SSL___3 = 255,\n\tPIN_QSPI1_IO2___3 = 256,\n\tPIN_QSPI1_IO3___3 = 257,\n\tPIN_QSPI1_MISO_IO1___3 = 258,\n\tPIN_QSPI1_MOSI_IO0___3 = 259,\n\tPIN_QSPI1_SPCLK___3 = 260,\n\tPIN_QSPI1_SSL___3 = 261,\n\tPIN_RPC_INT_N___3 = 262,\n\tPIN_RPC_RESET_N___3 = 263,\n\tPIN_RPC_WP_N___3 = 264,\n\tPIN_TCK___4 = 265,\n\tPIN_TDI___4 = 266,\n\tPIN_TDO___3 = 267,\n\tPIN_TMS___4 = 268,\n\tPIN_TRST_N___4 = 269,\n};\n\nenum {\n\tGP_LAST___8 = 205,\n\tPIN_DU_DOTCLKIN0___4 = 206,\n\tPIN_FSCLKST_N___4 = 207,\n\tPIN_MLB_REF___5 = 208,\n\tPIN_PRESETOUT_N___6 = 209,\n\tPIN_TCK___5 = 210,\n\tPIN_TDI___5 = 211,\n\tPIN_TMS___5 = 212,\n\tPIN_TRST_N___5 = 213,\n\tPIN_VDDQ_AVB0___4 = 214,\n};\n\nenum {\n\tGP_LAST___9 = 174,\n\tPIN_DU_DOTCLKIN___2 = 175,\n\tPIN_EXTALR___5 = 176,\n\tPIN_FSCLKST_N___5 = 177,\n\tPIN_PRESETOUT_N___7 = 178,\n\tPIN_TCK___6 = 179,\n\tPIN_TDI___6 = 180,\n\tPIN_TMS___6 = 181,\n\tPIN_TRST_N___6 = 182,\n\tPIN_VDDQ_AVB0___5 = 183,\n};\n\nenum {\n\tGSSX_NULL = 0,\n\tGSSX_INDICATE_MECHS = 1,\n\tGSSX_GET_CALL_CONTEXT = 2,\n\tGSSX_IMPORT_AND_CANON_NAME = 3,\n\tGSSX_EXPORT_CRED = 4,\n\tGSSX_IMPORT_CRED = 5,\n\tGSSX_ACQUIRE_CRED = 6,\n\tGSSX_STORE_CRED = 7,\n\tGSSX_INIT_SEC_CONTEXT = 8,\n\tGSSX_ACCEPT_SEC_CONTEXT = 9,\n\tGSSX_RELEASE_HANDLE = 10,\n\tGSSX_GET_MIC = 11,\n\tGSSX_VERIFY = 12,\n\tGSSX_WRAP = 13,\n\tGSSX_UNWRAP = 14,\n\tGSSX_WRAP_SIZE_LIMIT = 15,\n};\n\nenum {\n\tHANDSHAKE_A_ACCEPT_SOCKFD = 1,\n\tHANDSHAKE_A_ACCEPT_HANDLER_CLASS = 2,\n\tHANDSHAKE_A_ACCEPT_MESSAGE_TYPE = 3,\n\tHANDSHAKE_A_ACCEPT_TIMEOUT = 4,\n\tHANDSHAKE_A_ACCEPT_AUTH_MODE = 5,\n\tHANDSHAKE_A_ACCEPT_PEER_IDENTITY = 6,\n\tHANDSHAKE_A_ACCEPT_CERTIFICATE = 7,\n\tHANDSHAKE_A_ACCEPT_PEERNAME = 8,\n\tHANDSHAKE_A_ACCEPT_KEYRING = 9,\n\t__HANDSHAKE_A_ACCEPT_MAX = 10,\n\tHANDSHAKE_A_ACCEPT_MAX = 9,\n};\n\nenum {\n\tHANDSHAKE_A_DONE_STATUS = 1,\n\tHANDSHAKE_A_DONE_SOCKFD = 2,\n\tHANDSHAKE_A_DONE_REMOTE_AUTH = 3,\n\t__HANDSHAKE_A_DONE_MAX = 4,\n\tHANDSHAKE_A_DONE_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_A_X509_CERT = 1,\n\tHANDSHAKE_A_X509_PRIVKEY = 2,\n\t__HANDSHAKE_A_X509_MAX = 3,\n\tHANDSHAKE_A_X509_MAX = 2,\n};\n\nenum {\n\tHANDSHAKE_CMD_READY = 1,\n\tHANDSHAKE_CMD_ACCEPT = 2,\n\tHANDSHAKE_CMD_DONE = 3,\n\t__HANDSHAKE_CMD_MAX = 4,\n\tHANDSHAKE_CMD_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_NLGRP_NONE = 0,\n\tHANDSHAKE_NLGRP_TLSHD = 1,\n};\n\nenum {\n\tHASH_SIZE = 128,\n};\n\nenum {\n\tHASH_TCP_IPV6_EX_CTRL = 32,\n\tHASH_IPV6_EX_CTRL = 16,\n\tHASH_TCP_IPV6_CTRL = 8,\n\tHASH_IPV6_CTRL = 4,\n\tHASH_TCP_IPV4_CTRL = 2,\n\tHASH_IPV4_CTRL = 1,\n\tHASH_ALL = 63,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHCU_CCSR_SMBALERT_MONITOR = 134217728,\n\tHCU_CCSR_CPU_SLEEP = 67108864,\n\tHCU_CCSR_CS_TO = 33554432,\n\tHCU_CCSR_WDOG = 16777216,\n\tHCU_CCSR_CLR_IRQ_HOST = 131072,\n\tHCU_CCSR_SET_IRQ_HCU = 65536,\n\tHCU_CCSR_AHB_RST = 512,\n\tHCU_CCSR_CPU_RST_MODE = 256,\n\tHCU_CCSR_SET_SYNC_CPU = 32,\n\tHCU_CCSR_CPU_CLK_DIVIDE_MSK = 24,\n\tHCU_CCSR_CPU_CLK_DIVIDE_BASE = 8,\n\tHCU_CCSR_OS_PRSNT = 4,\n\tHCU_CCSR_UC_STATE_MSK = 3,\n\tHCU_CCSR_UC_STATE_BASE = 1,\n\tHCU_CCSR_ASF_RESET = 0,\n\tHCU_CCSR_ASF_HALTED = 2,\n\tHCU_CCSR_ASF_RUNNING = 1,\n};\n\nenum {\n\tHIBERNATION_INVALID = 0,\n\tHIBERNATION_PLATFORM = 1,\n\tHIBERNATION_SHUTDOWN = 2,\n\tHIBERNATION_REBOOT = 3,\n\tHIBERNATION_SUSPEND = 4,\n\tHIBERNATION_TEST_RESUME = 5,\n\t__HIBERNATION_AFTER_LAST = 6,\n};\n\nenum {\n\tHISI_SAS_BIST_CODE_MODE_PRBS7 = 0,\n\tHISI_SAS_BIST_CODE_MODE_PRBS23 = 1,\n\tHISI_SAS_BIST_CODE_MODE_PRBS31 = 2,\n\tHISI_SAS_BIST_CODE_MODE_JTPAT = 3,\n\tHISI_SAS_BIST_CODE_MODE_CJTPAT = 4,\n\tHISI_SAS_BIST_CODE_MODE_SCRAMBED_0 = 5,\n\tHISI_SAS_BIST_CODE_MODE_TRAIN = 6,\n\tHISI_SAS_BIST_CODE_MODE_TRAIN_DONE = 7,\n\tHISI_SAS_BIST_CODE_MODE_HFTP = 8,\n\tHISI_SAS_BIST_CODE_MODE_MFTP = 9,\n\tHISI_SAS_BIST_CODE_MODE_LFTP = 10,\n\tHISI_SAS_BIST_CODE_MODE_FIXED_DATA = 11,\n};\n\nenum {\n\tHISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,\n\tHISI_SAS_BIST_LOOPBACK_MODE_SERDES = 1,\n\tHISI_SAS_BIST_LOOPBACK_MODE_REMOTE = 2,\n};\n\nenum {\n\tHISI_SAS_PHY_BCAST_ACK = 0,\n\tHISI_SAS_PHY_SL_PHY_ENABLED = 1,\n\tHISI_SAS_PHY_INT_ABNORMAL = 2,\n\tHISI_SAS_PHY_INT_NR = 3,\n};\n\nenum {\n\tHISI_SAS_PHY_PHY_UPDOWN = 0,\n\tHISI_SAS_PHY_CHNL_INT = 1,\n\tHISI_SAS_PHY_INT_NR___2 = 2,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHSE = 0,\n\tHSI = 1,\n\tMSI = 2,\n\tLSE = 3,\n\tLSI = 4,\n\tHSE_DIV2 = 5,\n\tICN_HS_MCU = 6,\n\tICN_LS_MCU = 7,\n\tICN_SDMMC = 8,\n\tICN_DDR = 9,\n\tICN_DISPLAY = 10,\n\tICN_HSL = 11,\n\tICN_NIC = 12,\n\tFLEXGEN_07 = 13,\n\tFLEXGEN_08 = 14,\n\tFLEXGEN_09 = 15,\n\tFLEXGEN_10 = 16,\n\tFLEXGEN_11 = 17,\n\tFLEXGEN_12 = 18,\n\tFLEXGEN_13 = 19,\n\tFLEXGEN_14 = 20,\n\tFLEXGEN_16 = 21,\n\tFLEXGEN_17 = 22,\n\tFLEXGEN_18 = 23,\n\tFLEXGEN_19 = 24,\n\tFLEXGEN_20 = 25,\n\tFLEXGEN_21 = 26,\n\tFLEXGEN_22 = 27,\n\tFLEXGEN_23 = 28,\n\tFLEXGEN_24 = 29,\n\tFLEXGEN_25 = 30,\n\tFLEXGEN_26 = 31,\n\tFLEXGEN_27 = 32,\n\tFLEXGEN_29 = 33,\n\tFLEXGEN_30 = 34,\n\tFLEXGEN_31 = 35,\n\tFLEXGEN_33 = 36,\n\tFLEXGEN_36 = 37,\n\tFLEXGEN_37 = 38,\n\tFLEXGEN_38 = 39,\n\tFLEXGEN_39 = 40,\n\tFLEXGEN_40 = 41,\n\tFLEXGEN_41 = 42,\n\tFLEXGEN_42 = 43,\n\tFLEXGEN_43 = 44,\n\tFLEXGEN_44 = 45,\n\tFLEXGEN_45 = 46,\n\tFLEXGEN_46 = 47,\n\tFLEXGEN_47 = 48,\n\tFLEXGEN_48 = 49,\n\tFLEXGEN_50 = 50,\n\tFLEXGEN_51 = 51,\n\tFLEXGEN_52 = 52,\n\tFLEXGEN_53 = 53,\n\tFLEXGEN_54 = 54,\n\tFLEXGEN_55 = 55,\n\tFLEXGEN_56 = 56,\n\tFLEXGEN_57 = 57,\n\tFLEXGEN_58 = 58,\n\tFLEXGEN_61 = 59,\n\tFLEXGEN_62 = 60,\n\tFLEXGEN_63 = 61,\n\tICN_APB1 = 62,\n\tICN_APB2 = 63,\n\tICN_APB3 = 64,\n\tICN_APB4 = 65,\n\tICN_APB5 = 66,\n\tICN_APBDBG = 67,\n\tTIMG1 = 68,\n\tTIMG2 = 69,\n};\n\nenum {\n\tHSE___2 = 0,\n\tHSI___2 = 1,\n\tMSI___2 = 2,\n\tLSE___2 = 3,\n\tLSI___2 = 4,\n\tHSE_DIV2___2 = 5,\n\tICN_HS_MCU___2 = 6,\n\tICN_LS_MCU___2 = 7,\n\tICN_SDMMC___2 = 8,\n\tICN_DDR___2 = 9,\n\tICN_DISPLAY___2 = 10,\n\tICN_HSL___2 = 11,\n\tICN_NIC___2 = 12,\n\tICN_VID = 13,\n\tFLEXGEN_07___2 = 14,\n\tFLEXGEN_08___2 = 15,\n\tFLEXGEN_09___2 = 16,\n\tFLEXGEN_10___2 = 17,\n\tFLEXGEN_11___2 = 18,\n\tFLEXGEN_12___2 = 19,\n\tFLEXGEN_13___2 = 20,\n\tFLEXGEN_14___2 = 21,\n\tFLEXGEN_15 = 22,\n\tFLEXGEN_16___2 = 23,\n\tFLEXGEN_17___2 = 24,\n\tFLEXGEN_18___2 = 25,\n\tFLEXGEN_19___2 = 26,\n\tFLEXGEN_20___2 = 27,\n\tFLEXGEN_21___2 = 28,\n\tFLEXGEN_22___2 = 29,\n\tFLEXGEN_23___2 = 30,\n\tFLEXGEN_24___2 = 31,\n\tFLEXGEN_25___2 = 32,\n\tFLEXGEN_26___2 = 33,\n\tFLEXGEN_27___2 = 34,\n\tFLEXGEN_28 = 35,\n\tFLEXGEN_29___2 = 36,\n\tFLEXGEN_30___2 = 37,\n\tFLEXGEN_31___2 = 38,\n\tFLEXGEN_32 = 39,\n\tFLEXGEN_33___2 = 40,\n\tFLEXGEN_34 = 41,\n\tFLEXGEN_35 = 42,\n\tFLEXGEN_36___2 = 43,\n\tFLEXGEN_37___2 = 44,\n\tFLEXGEN_38___2 = 45,\n\tFLEXGEN_39___2 = 46,\n\tFLEXGEN_40___2 = 47,\n\tFLEXGEN_41___2 = 48,\n\tFLEXGEN_42___2 = 49,\n\tFLEXGEN_43___2 = 50,\n\tFLEXGEN_44___2 = 51,\n\tFLEXGEN_45___2 = 52,\n\tFLEXGEN_46___2 = 53,\n\tFLEXGEN_47___2 = 54,\n\tFLEXGEN_48___2 = 55,\n\tFLEXGEN_49 = 56,\n\tFLEXGEN_50___2 = 57,\n\tFLEXGEN_51___2 = 58,\n\tFLEXGEN_52___2 = 59,\n\tFLEXGEN_53___2 = 60,\n\tFLEXGEN_54___2 = 61,\n\tFLEXGEN_55___2 = 62,\n\tFLEXGEN_56___2 = 63,\n\tFLEXGEN_57___2 = 64,\n\tFLEXGEN_58___2 = 65,\n\tFLEXGEN_59 = 66,\n\tFLEXGEN_60 = 67,\n\tFLEXGEN_61___2 = 68,\n\tFLEXGEN_62___2 = 69,\n\tFLEXGEN_63___2 = 70,\n\tICN_APB1___2 = 71,\n\tICN_APB2___2 = 72,\n\tICN_APB3___2 = 73,\n\tICN_APB4___2 = 74,\n\tICN_APBDBG___2 = 75,\n\tTIMG1___2 = 76,\n\tTIMG2___2 = 77,\n\tPLL3 = 78,\n\tDSI_TXBYTE = 79,\n};\n\nenum {\n\tHTE_TS_REGISTERED = 0,\n\tHTE_TS_REQ = 1,\n\tHTE_TS_DISABLE = 2,\n\tHTE_TS_QUEUE_WK = 3,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tHW_BREAKPOINT_EMPTY = 0,\n\tHW_BREAKPOINT_R = 1,\n\tHW_BREAKPOINT_W = 2,\n\tHW_BREAKPOINT_RW = 3,\n\tHW_BREAKPOINT_X = 4,\n\tHW_BREAKPOINT_INVALID = 7,\n};\n\nenum {\n\tHW_BREAKPOINT_LEN_1 = 1,\n\tHW_BREAKPOINT_LEN_2 = 2,\n\tHW_BREAKPOINT_LEN_3 = 3,\n\tHW_BREAKPOINT_LEN_4 = 4,\n\tHW_BREAKPOINT_LEN_5 = 5,\n\tHW_BREAKPOINT_LEN_6 = 6,\n\tHW_BREAKPOINT_LEN_7 = 7,\n\tHW_BREAKPOINT_LEN_8 = 8,\n};\n\nenum {\n\tHW_OWNER = 128,\n\tOP_TCPWRITE = 17,\n\tOP_TCPSTART = 18,\n\tOP_TCPINIT = 20,\n\tOP_TCPLCK = 24,\n\tOP_TCPCHKSUM = 18,\n\tOP_TCPIS = 22,\n\tOP_TCPLW = 25,\n\tOP_TCPLSW = 27,\n\tOP_TCPLISW = 31,\n\tOP_ADDR64 = 33,\n\tOP_VLAN = 34,\n\tOP_ADDR64VLAN = 35,\n\tOP_LRGLEN = 36,\n\tOP_LRGLENVLAN = 38,\n\tOP_MSS = 40,\n\tOP_MSSVLAN = 42,\n\tOP_BUFFER = 64,\n\tOP_PACKET = 65,\n\tOP_LARGESEND = 67,\n\tOP_LSOV2 = 69,\n\tOP_RXSTAT = 96,\n\tOP_RXTIMESTAMP = 97,\n\tOP_RXVLAN = 98,\n\tOP_RXCHKS = 100,\n\tOP_RXCHKSVLAN = 102,\n\tOP_RXTIMEVLAN = 99,\n\tOP_RSS_HASH = 101,\n\tOP_TXINDEXLE = 104,\n\tOP_MACSEC = 108,\n\tOP_PUTIDX = 112,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tICQ_EXITED = 4,\n\tICQ_DESTROYED = 8,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_TUN_UNSPEC = 0,\n\tIFLA_TUN_OWNER = 1,\n\tIFLA_TUN_GROUP = 2,\n\tIFLA_TUN_TYPE = 3,\n\tIFLA_TUN_PI = 4,\n\tIFLA_TUN_VNET_HDR = 5,\n\tIFLA_TUN_PERSIST = 6,\n\tIFLA_TUN_MULTI_QUEUE = 7,\n\tIFLA_TUN_NUM_QUEUES = 8,\n\tIFLA_TUN_NUM_DISABLED_QUEUES = 9,\n\t__IFLA_TUN_MAX = 10,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_LINK_STATE_AUTO = 0,\n\tIFLA_VF_LINK_STATE_ENABLE = 1,\n\tIFLA_VF_LINK_STATE_DISABLE = 2,\n\t__IFLA_VF_LINK_STATE_MAX = 3,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_ACT_NONE = -1,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nenum {\n\tINET_DIAG_BC_NOP = 0,\n\tINET_DIAG_BC_JMP = 1,\n\tINET_DIAG_BC_S_GE = 2,\n\tINET_DIAG_BC_S_LE = 3,\n\tINET_DIAG_BC_D_GE = 4,\n\tINET_DIAG_BC_D_LE = 5,\n\tINET_DIAG_BC_AUTO = 6,\n\tINET_DIAG_BC_S_COND = 7,\n\tINET_DIAG_BC_D_COND = 8,\n\tINET_DIAG_BC_DEV_COND = 9,\n\tINET_DIAG_BC_MARK_COND = 10,\n\tINET_DIAG_BC_S_EQ = 11,\n\tINET_DIAG_BC_D_EQ = 12,\n\tINET_DIAG_BC_CGROUP_COND = 13,\n};\n\nenum {\n\tINET_DIAG_NONE = 0,\n\tINET_DIAG_MEMINFO = 1,\n\tINET_DIAG_INFO = 2,\n\tINET_DIAG_VEGASINFO = 3,\n\tINET_DIAG_CONG = 4,\n\tINET_DIAG_TOS = 5,\n\tINET_DIAG_TCLASS = 6,\n\tINET_DIAG_SKMEMINFO = 7,\n\tINET_DIAG_SHUTDOWN = 8,\n\tINET_DIAG_DCTCPINFO = 9,\n\tINET_DIAG_PROTOCOL = 10,\n\tINET_DIAG_SKV6ONLY = 11,\n\tINET_DIAG_LOCALS = 12,\n\tINET_DIAG_PEERS = 13,\n\tINET_DIAG_PAD = 14,\n\tINET_DIAG_MARK = 15,\n\tINET_DIAG_BBRINFO = 16,\n\tINET_DIAG_CLASS_ID = 17,\n\tINET_DIAG_MD5SIG = 18,\n\tINET_DIAG_ULP_INFO = 19,\n\tINET_DIAG_SK_BPF_STORAGES = 20,\n\tINET_DIAG_CGROUP_ID = 21,\n\tINET_DIAG_SOCKOPT = 22,\n\t__INET_DIAG_MAX = 23,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINET_ULP_INFO_UNSPEC = 0,\n\tINET_ULP_INFO_NAME = 1,\n\tINET_ULP_INFO_TLS = 2,\n\tINET_ULP_INFO_MPTCP = 3,\n\t__INET_ULP_INFO_MAX = 4,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINTEL_DSM_FNS = 0,\n\tINTEL_DSM_V18_SWITCH = 3,\n\tINTEL_DSM_V33_SWITCH = 4,\n\tINTEL_DSM_HS_CAPS = 8,\n};\n\nenum {\n\tINTERRUPT_MASK_ALL_VER_11 = 204799,\n\tINTERRUPT_MASK_ALL_VER_21 = 466943,\n};\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOMMUFD_ACCESS_RW_READ = 0,\n\tIOMMUFD_ACCESS_RW_WRITE = 1,\n\tIOMMUFD_ACCESS_RW_KTHREAD = 2,\n\t__IOMMUFD_ACCESS_RW_SLOW_PATH = 4,\n};\n\nenum {\n\tIOMMU_PASID_ARRAY_DOMAIN = 0,\n\tIOMMU_PASID_ARRAY_HANDLE = 1,\n};\n\nenum {\n\tIOMMU_SET_DOMAIN_MUST_SUCCEED = 1,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIP_VER_MT6983 = 271974400,\n\tIP_VER_MT6878 = 272761344,\n\tIP_VER_MT6897 = 272891904,\n\tIP_VER_MT6989 = 272957440,\n\tIP_VER_MT6899 = 272957696,\n\tIP_VER_MT6991_A0 = 273022976,\n\tIP_VER_MT6991_B0 = 273088512,\n\tIP_VER_MT6993 = 273154048,\n\tIP_VER_NONE = 4294967295,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_POLL_F_SCHED = 0,\n\tIRQ_POLL_F_DISABLE = 1,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tI_DATA_SEM_NORMAL = 0,\n\tI_DATA_SEM_OTHER = 1,\n\tI_DATA_SEM_QUOTA = 2,\n\tI_DATA_SEM_EA = 3,\n};\n\nenum {\n\tK3_UDMA_GLUE_SRC_TAG_LO_KEEP = 0,\n\tK3_UDMA_GLUE_SRC_TAG_LO_USE_FLOW_REG = 1,\n\tK3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_FLOW_ID = 2,\n\tK3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG = 4,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKPARAM_MEM = 0,\n\tKPARAM_WIDTH = 1,\n\tKPARAM_HEIGHT = 2,\n\tKPARAM_CNT = 3,\n};\n\nenum {\n\tKPARAM_X = 0,\n\tKPARAM_Y = 1,\n\tKPARAM_CNT___2 = 2,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0,\n\tKVM_REG_ARM_STD_BMAP_BIT_COUNT = 1,\n};\n\nenum {\n\tKVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0,\n\tKVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT = 1,\n};\n\nenum {\n\tKVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_VER = 0,\n\tKVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_CPUS = 1,\n\tKVM_REG_ARM_VENDOR_HYP_BMAP_2_BIT_COUNT = 2,\n};\n\nenum {\n\tKVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0,\n\tKVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1,\n\tKVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT = 2,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLANE_0 = 0,\n\tLANE_1 = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLED_PAR_CTRL_COLX = 0,\n\tLED_PAR_CTRL_ERROR = 1,\n\tLED_PAR_CTRL_DUPLEX = 2,\n\tLED_PAR_CTRL_DP_COL = 3,\n\tLED_PAR_CTRL_SPEED = 4,\n\tLED_PAR_CTRL_LINK = 5,\n\tLED_PAR_CTRL_TX = 6,\n\tLED_PAR_CTRL_RX = 7,\n\tLED_PAR_CTRL_ACT = 8,\n\tLED_PAR_CTRL_LNK_RX = 9,\n\tLED_PAR_CTRL_LNK_AC = 10,\n\tLED_PAR_CTRL_ACT_BL = 11,\n\tLED_PAR_CTRL_TX_BL = 12,\n\tLED_PAR_CTRL_RX_BL = 13,\n\tLED_PAR_CTRL_COL_BL = 14,\n\tLED_PAR_CTRL_INACT = 15,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = -1,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_FUA = 512,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_NCQ_SEND_RECV = 2048,\n\tATA_DFLAG_NCQ_PRIO = 4096,\n\tATA_DFLAG_CDL = 8192,\n\tATA_DFLAG_CFG_MASK = 16383,\n\tATA_DFLAG_PIO = 16384,\n\tATA_DFLAG_NCQ_OFF = 32768,\n\tATA_DFLAG_SLEEPING = 65536,\n\tATA_DFLAG_DUBIOUS_XFER = 131072,\n\tATA_DFLAG_NO_UNLOAD = 262144,\n\tATA_DFLAG_UNLOCK_HPA = 524288,\n\tATA_DFLAG_INIT_MASK = 1048575,\n\tATA_DFLAG_NCQ_PRIO_ENABLED = 1048576,\n\tATA_DFLAG_CDL_ENABLED = 2097152,\n\tATA_DFLAG_RESUMING = 4194304,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_FEATURES_MASK = 201341696,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DEBOUNCE_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_RESUMING = 65536,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_RTF_FILLED = 4,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_HAS_CDL = 256,\n\tATA_QCFLAG_EH = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_QCFLAG_EH_SUCCESS_CMD = 524288,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_HOST_NO_PART = 16,\n\tATA_HOST_NO_SSC = 32,\n\tATA_HOST_NO_DEVSLP = 64,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 10000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_GET_SUCCESS_SENSE = 64,\n\tATA_EH_SET_ACTIVE = 128,\n\tATA_EH_PERDEV_MASK = 225,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_PRINT_QUIRKS = 2097152,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum {\n\tLINKLED_OFF = 1,\n\tLINKLED_ON = 2,\n\tLINKLED_LINKSYNC_OFF = 4,\n\tLINKLED_LINKSYNC_ON = 8,\n\tLINKLED_BLINK_OFF = 16,\n\tLINKLED_BLINK_ON = 32,\n};\n\nenum {\n\tLINK_CAPA_10HD = 0,\n\tLINK_CAPA_10FD = 1,\n\tLINK_CAPA_100HD = 2,\n\tLINK_CAPA_100FD = 3,\n\tLINK_CAPA_1000HD = 4,\n\tLINK_CAPA_1000FD = 5,\n\tLINK_CAPA_2500FD = 6,\n\tLINK_CAPA_5000FD = 7,\n\tLINK_CAPA_10000FD = 8,\n\tLINK_CAPA_20000FD = 9,\n\tLINK_CAPA_25000FD = 10,\n\tLINK_CAPA_40000FD = 11,\n\tLINK_CAPA_50000FD = 12,\n\tLINK_CAPA_56000FD = 13,\n\tLINK_CAPA_80000FD = 14,\n\tLINK_CAPA_100000FD = 15,\n\tLINK_CAPA_200000FD = 16,\n\tLINK_CAPA_400000FD = 17,\n\tLINK_CAPA_800000FD = 18,\n\tLINK_CAPA_1600000FD = 19,\n\t__LINK_CAPA_MAX = 20,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLK_STATE_IN_USE = 0,\n\tNFS_DELEGATED_STATE = 1,\n\tNFS_OPEN_STATE = 2,\n\tNFS_O_RDONLY_STATE = 3,\n\tNFS_O_WRONLY_STATE = 4,\n\tNFS_O_RDWR_STATE = 5,\n\tNFS_STATE_RECLAIM_REBOOT = 6,\n\tNFS_STATE_RECLAIM_NOGRACE = 7,\n\tNFS_STATE_POSIX_LOCKS = 8,\n\tNFS_STATE_RECOVERY_FAILED = 9,\n\tNFS_STATE_MAY_NOTIFY_LOCK = 10,\n\tNFS_STATE_CHANGE_WAIT = 11,\n\tNFS_CLNT_DST_SSC_COPY_STATE = 12,\n\tNFS_CLNT_SRC_SSC_COPY_STATE = 13,\n\tNFS_SRV_SSC_COPY_STATE = 14,\n};\n\nenum {\n\tLNK_SYNC_INI = 3120,\n\tLNK_SYNC_VAL = 3124,\n\tLNK_SYNC_CTRL = 3128,\n\tLNK_SYNC_TST = 3129,\n\tLNK_LED_REG = 3132,\n\tRX_GMF_EA = 3136,\n\tRX_GMF_AF_THR = 3140,\n\tRX_GMF_CTRL_T = 3144,\n\tRX_GMF_FL_MSK = 3148,\n\tRX_GMF_FL_THR = 3152,\n\tRX_GMF_FL_CTRL = 3154,\n\tRX_GMF_TR_THR = 3156,\n\tRX_GMF_UP_THR = 3160,\n\tRX_GMF_LP_THR = 3162,\n\tRX_GMF_VLAN = 3164,\n\tRX_GMF_WP = 3168,\n\tRX_GMF_WLEV = 3176,\n\tRX_GMF_RP = 3184,\n\tRX_GMF_RLEV = 3192,\n};\n\nenum {\n\tLOCKD_A_SERVER_GRACETIME = 1,\n\tLOCKD_A_SERVER_TCP_PORT = 2,\n\tLOCKD_A_SERVER_UDP_PORT = 3,\n\t__LOCKD_A_SERVER_MAX = 4,\n\tLOCKD_A_SERVER_MAX = 3,\n};\n\nenum {\n\tLOCKD_CMD_SERVER_SET = 1,\n\tLOCKD_CMD_SERVER_GET = 2,\n\t__LOCKD_CMD_MAX = 3,\n\tLOCKD_CMD_MAX = 2,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nenum {\n\tLS1021A = 0,\n\tLS1012A = 1,\n\tLS1028A = 2,\n\tLS1043A = 3,\n\tLS1046A = 4,\n\tLS2080A = 5,\n\tLS2085A = 6,\n\tLX2160A = 7,\n\tMCF5441X = 8,\n\tVF610 = 9,\n\tS32G = 10,\n\tS32G_TARGET = 11,\n};\n\nenum {\n\tLTSSM_DETECT_QUIET = 0,\n\tLTSSM_DETECT_ACTIVE = 1,\n\tLTSSM_POLLING_ACTIVE = 2,\n\tLTSSM_POLLING_COMPLIANCE = 3,\n\tLTSSM_POLLING_CONFIGURATION = 4,\n\tLTSSM_CONFIG_LINKWIDTH_START = 5,\n\tLTSSM_CONFIG_LINKWIDTH_ACCEPT = 6,\n\tLTSSM_CONFIG_LANENUM_ACCEPT = 7,\n\tLTSSM_CONFIG_LANENUM_WAIT = 8,\n\tLTSSM_CONFIG_COMPLETE = 9,\n\tLTSSM_CONFIG_IDLE = 10,\n\tLTSSM_RECOVERY_RCVR_LOCK = 11,\n\tLTSSM_RECOVERY_SPEED = 12,\n\tLTSSM_RECOVERY_RCVR_CFG = 13,\n\tLTSSM_RECOVERY_IDLE = 14,\n\tLTSSM_L0 = 16,\n\tLTSSM_RX_L0S_ENTRY = 17,\n\tLTSSM_RX_L0S_IDLE = 18,\n\tLTSSM_RX_L0S_FTS = 19,\n\tLTSSM_TX_L0S_ENTRY = 20,\n\tLTSSM_TX_L0S_IDLE = 21,\n\tLTSSM_TX_L0S_FTS = 22,\n\tLTSSM_L1_ENTRY = 23,\n\tLTSSM_L1_IDLE = 24,\n\tLTSSM_L2_IDLE = 25,\n\tLTSSM_L2_TRANSMIT_WAKE = 26,\n\tLTSSM_DISABLED = 32,\n\tLTSSM_LOOPBACK_ENTRY_MASTER = 33,\n\tLTSSM_LOOPBACK_ACTIVE_MASTER = 34,\n\tLTSSM_LOOPBACK_EXIT_MASTER = 35,\n\tLTSSM_LOOPBACK_ENTRY_SLAVE = 36,\n\tLTSSM_LOOPBACK_ACTIVE_SLAVE = 37,\n\tLTSSM_LOOPBACK_EXIT_SLAVE = 38,\n\tLTSSM_HOT_RESET = 39,\n\tLTSSM_RECOVERY_EQUALIZATION_PHASE0 = 40,\n\tLTSSM_RECOVERY_EQUALIZATION_PHASE1 = 41,\n\tLTSSM_RECOVERY_EQUALIZATION_PHASE2 = 42,\n\tLTSSM_RECOVERY_EQUALIZATION_PHASE3 = 43,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n\tLo_deleting = 3,\n};\n\nenum {\n\tMAC_TX_CLK_0_MHZ = 2,\n\tMAC_TX_CLK_2_5_MHZ = 6,\n\tMAC_TX_CLK_25_MHZ = 7,\n};\n\nenum {\n\tMAGNITUDE_STRONG = 2,\n\tMAGNITUDE_WEAK = 3,\n\tMAGNITUDE_NUM = 4,\n};\n\nenum {\n\tMASK_EE_STATUS = 65535,\n\tMASK_EE_DYNCAP_EVENT = 1,\n\tMASK_EE_SYSPOOL_EVENT = 2,\n\tMASK_EE_URGENT_BKOPS = 4,\n\tMASK_EE_TOO_HIGH_TEMP = 8,\n\tMASK_EE_TOO_LOW_TEMP = 16,\n\tMASK_EE_WRITEBOOSTER_EVENT = 32,\n\tMASK_EE_PERFORMANCE_THROTTLING = 64,\n\tMASK_EE_DEV_LVL_EXCEPTION = 128,\n\tMASK_EE_HEALTH_CRITICAL = 512,\n};\n\nenum {\n\tMASK_OCS = 15,\n};\n\nenum {\n\tMASK_TM_SERVICE_RESP = 255,\n};\n\nenum {\n\tMASK_TRANSFER_REQUESTS_SLOTS_SDB = 31,\n\tMASK_TRANSFER_REQUESTS_SLOTS_MCQ = 255,\n\tMASK_NUMBER_OUTSTANDING_RTT = 65280,\n\tMASK_TASK_MANAGEMENT_REQUEST_SLOTS = 458752,\n\tMASK_EHSLUTRD_SUPPORTED = 4194304,\n\tMASK_AUTO_HIBERN8_SUPPORT = 8388608,\n\tMASK_64_ADDRESSING_SUPPORT = 16777216,\n\tMASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 33554432,\n\tMASK_UIC_DME_TEST_MODE_SUPPORT = 67108864,\n\tMASK_CRYPTO_SUPPORT = 268435456,\n\tMASK_LSDB_SUPPORT = 536870912,\n\tMASK_MCQ_SUPPORT = 1073741824,\n};\n\nenum {\n\tMATCH_MTR = 0,\n\tMATCH_MEQ = 1,\n\tMATCH_MLE = 2,\n\tMATCH_MLT = 3,\n\tMATCH_MGE = 4,\n\tMATCH_MGT = 5,\n};\n\nenum {\n\tMAX7319 = 0,\n\tMAX7320 = 1,\n\tMAX7321 = 2,\n\tMAX7322 = 3,\n\tMAX7323 = 4,\n\tMAX7324 = 5,\n\tMAX7325 = 6,\n\tMAX7326 = 7,\n\tMAX7327 = 8,\n};\n\nenum {\n\tMAX77620_GPIO0 = 0,\n\tMAX77620_GPIO1 = 1,\n\tMAX77620_GPIO2 = 2,\n\tMAX77620_GPIO3 = 3,\n\tMAX77620_GPIO4 = 4,\n\tMAX77620_GPIO5 = 5,\n\tMAX77620_GPIO6 = 6,\n\tMAX77620_GPIO7 = 7,\n\tMAX77620_GPIO_NR = 8,\n};\n\nenum {\n\tMAX77620_IRQ_TOP_GLBL = 0,\n\tMAX77620_IRQ_TOP_SD = 1,\n\tMAX77620_IRQ_TOP_LDO = 2,\n\tMAX77620_IRQ_TOP_GPIO = 3,\n\tMAX77620_IRQ_TOP_RTC = 4,\n\tMAX77620_IRQ_TOP_32K = 5,\n\tMAX77620_IRQ_TOP_ONOFF = 6,\n\tMAX77620_IRQ_LBT_MBATLOW = 7,\n\tMAX77620_IRQ_LBT_TJALRM1 = 8,\n\tMAX77620_IRQ_LBT_TJALRM2 = 9,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMBE_REFERENCED_B = 0,\n\tMBE_REUSABLE_B = 1,\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nenum {\n\tMCT_INT_SPI = 0,\n\tMCT_INT_PPI = 1,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMEGASAS_HBA_OPERATIONAL = 0,\n\tMEGASAS_ADPRESET_SM_INFAULT = 1,\n\tMEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,\n\tMEGASAS_ADPRESET_SM_OPERATIONAL = 3,\n\tMEGASAS_HW_CRITICAL_ERROR = 4,\n\tMEGASAS_ADPRESET_SM_POLLING = 5,\n\tMEGASAS_ADPRESET_INPROG_SIGN = 3735936685,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMMAP_ON_MEMORY_DISABLE = 0,\n\tMEMMAP_ON_MEMORY_ENABLE = 1,\n\tMEMMAP_ON_MEMORY_FORCE = 2,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMICRON_ON_DIE_UNSUPPORTED = 0,\n\tMICRON_ON_DIE_SUPPORTED = 1,\n\tMICRON_ON_DIE_MANDATORY = 2,\n};\n\nenum {\n\tMIIM_CMD_IDLE = 0,\n\tMIIM_CMD_LEGACY_WRITE = 1,\n\tMIIM_CMD_LEGACY_READ = 2,\n};\n\nenum {\n\tMIPI_DCS_NOP = 0,\n\tMIPI_DCS_SOFT_RESET = 1,\n\tMIPI_DCS_GET_COMPRESSION_MODE = 3,\n\tMIPI_DCS_GET_DISPLAY_ID = 4,\n\tMIPI_DCS_GET_ERROR_COUNT_ON_DSI = 5,\n\tMIPI_DCS_GET_RED_CHANNEL = 6,\n\tMIPI_DCS_GET_GREEN_CHANNEL = 7,\n\tMIPI_DCS_GET_BLUE_CHANNEL = 8,\n\tMIPI_DCS_GET_DISPLAY_STATUS = 9,\n\tMIPI_DCS_GET_POWER_MODE = 10,\n\tMIPI_DCS_GET_ADDRESS_MODE = 11,\n\tMIPI_DCS_GET_PIXEL_FORMAT = 12,\n\tMIPI_DCS_GET_DISPLAY_MODE = 13,\n\tMIPI_DCS_GET_SIGNAL_MODE = 14,\n\tMIPI_DCS_GET_DIAGNOSTIC_RESULT = 15,\n\tMIPI_DCS_ENTER_SLEEP_MODE = 16,\n\tMIPI_DCS_EXIT_SLEEP_MODE = 17,\n\tMIPI_DCS_ENTER_PARTIAL_MODE = 18,\n\tMIPI_DCS_ENTER_NORMAL_MODE = 19,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 20,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_CT = 21,\n\tMIPI_DCS_EXIT_INVERT_MODE = 32,\n\tMIPI_DCS_ENTER_INVERT_MODE = 33,\n\tMIPI_DCS_SET_GAMMA_CURVE = 38,\n\tMIPI_DCS_SET_DISPLAY_OFF = 40,\n\tMIPI_DCS_SET_DISPLAY_ON = 41,\n\tMIPI_DCS_SET_COLUMN_ADDRESS = 42,\n\tMIPI_DCS_SET_PAGE_ADDRESS = 43,\n\tMIPI_DCS_WRITE_MEMORY_START = 44,\n\tMIPI_DCS_WRITE_LUT = 45,\n\tMIPI_DCS_READ_MEMORY_START = 46,\n\tMIPI_DCS_SET_PARTIAL_ROWS = 48,\n\tMIPI_DCS_SET_PARTIAL_COLUMNS = 49,\n\tMIPI_DCS_SET_SCROLL_AREA = 51,\n\tMIPI_DCS_SET_TEAR_OFF = 52,\n\tMIPI_DCS_SET_TEAR_ON = 53,\n\tMIPI_DCS_SET_ADDRESS_MODE = 54,\n\tMIPI_DCS_SET_SCROLL_START = 55,\n\tMIPI_DCS_EXIT_IDLE_MODE = 56,\n\tMIPI_DCS_ENTER_IDLE_MODE = 57,\n\tMIPI_DCS_SET_PIXEL_FORMAT = 58,\n\tMIPI_DCS_WRITE_MEMORY_CONTINUE = 60,\n\tMIPI_DCS_SET_3D_CONTROL = 61,\n\tMIPI_DCS_READ_MEMORY_CONTINUE = 62,\n\tMIPI_DCS_GET_3D_CONTROL = 63,\n\tMIPI_DCS_SET_VSYNC_TIMING = 64,\n\tMIPI_DCS_SET_TEAR_SCANLINE = 68,\n\tMIPI_DCS_GET_SCANLINE = 69,\n\tMIPI_DCS_SET_DISPLAY_BRIGHTNESS = 81,\n\tMIPI_DCS_GET_DISPLAY_BRIGHTNESS = 82,\n\tMIPI_DCS_WRITE_CONTROL_DISPLAY = 83,\n\tMIPI_DCS_GET_CONTROL_DISPLAY = 84,\n\tMIPI_DCS_WRITE_POWER_SAVE = 85,\n\tMIPI_DCS_GET_POWER_SAVE = 86,\n\tMIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 94,\n\tMIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 95,\n\tMIPI_DCS_READ_DDB_START = 161,\n\tMIPI_DCS_READ_PPS_START = 162,\n\tMIPI_DCS_READ_DDB_CONTINUE = 168,\n\tMIPI_DCS_READ_PPS_CONTINUE = 169,\n};\n\nenum {\n\tMIPI_DSI_V_SYNC_START = 1,\n\tMIPI_DSI_V_SYNC_END = 17,\n\tMIPI_DSI_H_SYNC_START = 33,\n\tMIPI_DSI_H_SYNC_END = 49,\n\tMIPI_DSI_COMPRESSION_MODE = 7,\n\tMIPI_DSI_END_OF_TRANSMISSION = 8,\n\tMIPI_DSI_COLOR_MODE_OFF = 2,\n\tMIPI_DSI_COLOR_MODE_ON = 18,\n\tMIPI_DSI_SHUTDOWN_PERIPHERAL = 34,\n\tMIPI_DSI_TURN_ON_PERIPHERAL = 50,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 3,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 19,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 35,\n\tMIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 4,\n\tMIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 20,\n\tMIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 36,\n\tMIPI_DSI_DCS_SHORT_WRITE = 5,\n\tMIPI_DSI_DCS_SHORT_WRITE_PARAM = 21,\n\tMIPI_DSI_DCS_READ = 6,\n\tMIPI_DSI_EXECUTE_QUEUE = 22,\n\tMIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 55,\n\tMIPI_DSI_NULL_PACKET = 9,\n\tMIPI_DSI_BLANKING_PACKET = 25,\n\tMIPI_DSI_GENERIC_LONG_WRITE = 41,\n\tMIPI_DSI_DCS_LONG_WRITE = 57,\n\tMIPI_DSI_PICTURE_PARAMETER_SET = 10,\n\tMIPI_DSI_COMPRESSED_PIXEL_STREAM = 11,\n\tMIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 12,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 28,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 44,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_30 = 13,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_36 = 29,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 61,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_16 = 14,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_18 = 30,\n\tMIPI_DSI_PIXEL_STREAM_3BYTE_18 = 46,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_24 = 62,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMLO_PAUSE_NONE = 0,\n\tMLO_PAUSE_RX = 1,\n\tMLO_PAUSE_TX = 2,\n\tMLO_PAUSE_TXRX_MASK = 3,\n\tMLO_PAUSE_AN = 4,\n\tMLO_AN_PHY = 0,\n\tMLO_AN_FIXED = 1,\n\tMLO_AN_INBAND = 2,\n\tPHYLINK_PCS_NEG_NONE = 0,\n\tPHYLINK_PCS_NEG_ENABLED = 16,\n\tPHYLINK_PCS_NEG_OUTBAND = 32,\n\tPHYLINK_PCS_NEG_INBAND = 64,\n\tPHYLINK_PCS_NEG_INBAND_DISABLED = 64,\n\tPHYLINK_PCS_NEG_INBAND_ENABLED = 80,\n\tMAC_SYM_PAUSE = 1,\n\tMAC_ASYM_PAUSE = 2,\n\tMAC_10HD = 4,\n\tMAC_10FD = 8,\n\tMAC_10 = 12,\n\tMAC_100HD = 16,\n\tMAC_100FD = 32,\n\tMAC_100 = 48,\n\tMAC_1000HD = 64,\n\tMAC_1000FD = 128,\n\tMAC_1000 = 192,\n\tMAC_2500FD = 256,\n\tMAC_5000FD = 512,\n\tMAC_10000FD = 1024,\n\tMAC_20000FD = 2048,\n\tMAC_25000FD = 4096,\n\tMAC_40000FD = 8192,\n\tMAC_50000FD = 16384,\n\tMAC_56000FD = 32768,\n\tMAC_80000FD = 65536,\n\tMAC_100000FD = 131072,\n\tMAC_200000FD = 262144,\n\tMAC_400000FD = 524288,\n};\n\nenum {\n\tMMOP_OFFLINE = 0,\n\tMMOP_ONLINE = 1,\n\tMMOP_ONLINE_KERNEL = 2,\n\tMMOP_ONLINE_MOVABLE = 3,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMOUNTPROC3_NULL = 0,\n\tMOUNTPROC3_MNT = 1,\n\tMOUNTPROC3_DUMP = 2,\n\tMOUNTPROC3_UMNT = 3,\n\tMOUNTPROC3_UMNTALL = 4,\n\tMOUNTPROC3_EXPORT = 5,\n};\n\nenum {\n\tMOUNTPROC_NULL = 0,\n\tMOUNTPROC_MNT = 1,\n\tMOUNTPROC_DUMP = 2,\n\tMOUNTPROC_UMNT = 3,\n\tMOUNTPROC_UMNTALL = 4,\n\tMOUNTPROC_EXPORT = 5,\n};\n\nenum {\n\tMOXA_SUPP_RS232 = 1,\n\tMOXA_SUPP_RS422 = 2,\n\tMOXA_SUPP_RS485 = 4,\n};\n\nenum {\n\tMPOL_DEFAULT = 0,\n\tMPOL_PREFERRED = 1,\n\tMPOL_BIND = 2,\n\tMPOL_INTERLEAVE = 3,\n\tMPOL_LOCAL = 4,\n\tMPOL_PREFERRED_MANY = 5,\n\tMPOL_WEIGHTED_INTERLEAVE = 6,\n\tMPOL_MAX = 7,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tMSM8953_MASTER_AMPSS_M0 = 1,\n\tMSM8953_MASTER_GRAPHICS_3D = 2,\n\tMSM8953_SNOC_BIMC_0_MAS = 3,\n\tMSM8953_SNOC_BIMC_2_MAS = 4,\n\tMSM8953_SNOC_BIMC_1_MAS = 5,\n\tMSM8953_MASTER_TCU_0 = 6,\n\tMSM8953_SLAVE_EBI_CH0 = 7,\n\tMSM8953_BIMC_SNOC_SLV = 8,\n\tMSM8953_MASTER_SPDM = 9,\n\tMSM8953_MASTER_BLSP_1 = 10,\n\tMSM8953_MASTER_BLSP_2 = 11,\n\tMSM8953_MASTER_USB3 = 12,\n\tMSM8953_MASTER_CRYPTO_CORE0 = 13,\n\tMSM8953_MASTER_SDCC_1 = 14,\n\tMSM8953_MASTER_SDCC_2 = 15,\n\tMSM8953_SNOC_PNOC_MAS = 16,\n\tMSM8953_PNOC_M_0 = 17,\n\tMSM8953_PNOC_M_1 = 18,\n\tMSM8953_PNOC_INT_1 = 19,\n\tMSM8953_PNOC_INT_2 = 20,\n\tMSM8953_PNOC_SLV_0 = 21,\n\tMSM8953_PNOC_SLV_1 = 22,\n\tMSM8953_PNOC_SLV_2 = 23,\n\tMSM8953_PNOC_SLV_3 = 24,\n\tMSM8953_PNOC_SLV_4 = 25,\n\tMSM8953_PNOC_SLV_6 = 26,\n\tMSM8953_PNOC_SLV_7 = 27,\n\tMSM8953_PNOC_SLV_8 = 28,\n\tMSM8953_PNOC_SLV_9 = 29,\n\tMSM8953_SLAVE_SPDM_WRAPPER = 30,\n\tMSM8953_SLAVE_PDM = 31,\n\tMSM8953_SLAVE_TCSR = 32,\n\tMSM8953_SLAVE_SNOC_CFG = 33,\n\tMSM8953_SLAVE_TLMM = 34,\n\tMSM8953_SLAVE_MESSAGE_RAM = 35,\n\tMSM8953_SLAVE_BLSP_1 = 36,\n\tMSM8953_SLAVE_BLSP_2 = 37,\n\tMSM8953_SLAVE_PRNG = 38,\n\tMSM8953_SLAVE_CAMERA_CFG = 39,\n\tMSM8953_SLAVE_DISPLAY_CFG = 40,\n\tMSM8953_SLAVE_VENUS_CFG = 41,\n\tMSM8953_SLAVE_GRAPHICS_3D_CFG = 42,\n\tMSM8953_SLAVE_SDCC_1 = 43,\n\tMSM8953_SLAVE_SDCC_2 = 44,\n\tMSM8953_SLAVE_CRYPTO_0_CFG = 45,\n\tMSM8953_SLAVE_PMIC_ARB = 46,\n\tMSM8953_SLAVE_USB3 = 47,\n\tMSM8953_SLAVE_IPA_CFG = 48,\n\tMSM8953_SLAVE_TCU = 49,\n\tMSM8953_PNOC_SNOC_SLV = 50,\n\tMSM8953_MASTER_QDSS_BAM = 51,\n\tMSM8953_BIMC_SNOC_MAS = 52,\n\tMSM8953_PNOC_SNOC_MAS = 53,\n\tMSM8953_MASTER_IPA = 54,\n\tMSM8953_MASTER_QDSS_ETR = 55,\n\tMSM8953_SNOC_QDSS_INT = 56,\n\tMSM8953_SNOC_INT_0 = 57,\n\tMSM8953_SNOC_INT_1 = 58,\n\tMSM8953_SNOC_INT_2 = 59,\n\tMSM8953_SLAVE_APPSS = 60,\n\tMSM8953_SLAVE_WCSS = 61,\n\tMSM8953_SNOC_BIMC_1_SLV = 62,\n\tMSM8953_SLAVE_OCIMEM = 63,\n\tMSM8953_SNOC_PNOC_SLV = 64,\n\tMSM8953_SLAVE_QDSS_STM = 65,\n\tMSM8953_SLAVE_OCMEM_64 = 66,\n\tMSM8953_SLAVE_LPASS = 67,\n\tMSM8953_MASTER_JPEG = 68,\n\tMSM8953_MASTER_MDP_PORT0 = 69,\n\tMSM8953_MASTER_VIDEO_P0 = 70,\n\tMSM8953_MASTER_VFE = 71,\n\tMSM8953_MASTER_VFE1 = 72,\n\tMSM8953_MASTER_CPP = 73,\n\tMSM8953_SNOC_BIMC_0_SLV = 74,\n\tMSM8953_SNOC_BIMC_2_SLV = 75,\n\tMSM8953_SLAVE_CATS_128 = 76,\n};\n\nenum {\n\tMSPI_DONE = 1,\n\tBSPI_DONE = 2,\n\tBSPI_ERR = 4,\n\tMSPI_BSPI_DONE = 7,\n};\n\nenum {\n\tMT6357_ID_VCORE = 0,\n\tMT6357_ID_VMODEM = 1,\n\tMT6357_ID_VPA = 2,\n\tMT6357_ID_VPROC = 3,\n\tMT6357_ID_VS1 = 4,\n\tMT6357_ID_VAUX18 = 5,\n\tMT6357_ID_VAUD28 = 6,\n\tMT6357_ID_VCAMA = 7,\n\tMT6357_ID_VCAMD = 8,\n\tMT6357_ID_VCAMIO = 9,\n\tMT6357_ID_VCN18 = 10,\n\tMT6357_ID_VCN28 = 11,\n\tMT6357_ID_VCN33_BT = 12,\n\tMT6357_ID_VCN33_WIFI = 13,\n\tMT6357_ID_VDRAM = 14,\n\tMT6357_ID_VEFUSE = 15,\n\tMT6357_ID_VEMC = 16,\n\tMT6357_ID_VFE28 = 17,\n\tMT6357_ID_VIBR = 18,\n\tMT6357_ID_VIO18 = 19,\n\tMT6357_ID_VIO28 = 20,\n\tMT6357_ID_VLDO28 = 21,\n\tMT6357_ID_VMC = 22,\n\tMT6357_ID_VMCH = 23,\n\tMT6357_ID_VRF12 = 24,\n\tMT6357_ID_VRF18 = 25,\n\tMT6357_ID_VSIM1 = 26,\n\tMT6357_ID_VSIM2 = 27,\n\tMT6357_ID_VSRAM_OTHERS = 28,\n\tMT6357_ID_VSRAM_PROC = 29,\n\tMT6357_ID_VUSB33 = 30,\n\tMT6357_ID_VXO22 = 31,\n\tMT6357_ID_RG_MAX = 32,\n};\n\nenum {\n\tMT6358_ID_VDRAM1 = 0,\n\tMT6358_ID_VCORE = 1,\n\tMT6358_ID_VPA = 2,\n\tMT6358_ID_VPROC11 = 3,\n\tMT6358_ID_VPROC12 = 4,\n\tMT6358_ID_VGPU = 5,\n\tMT6358_ID_VS2 = 6,\n\tMT6358_ID_VMODEM = 7,\n\tMT6358_ID_VS1 = 8,\n\tMT6358_ID_VDRAM2 = 9,\n\tMT6358_ID_VSIM1 = 10,\n\tMT6358_ID_VIBR = 11,\n\tMT6358_ID_VRF12 = 12,\n\tMT6358_ID_VIO18 = 13,\n\tMT6358_ID_VUSB = 14,\n\tMT6358_ID_VCAMIO = 15,\n\tMT6358_ID_VCAMD = 16,\n\tMT6358_ID_VCN18 = 17,\n\tMT6358_ID_VFE28 = 18,\n\tMT6358_ID_VSRAM_PROC11 = 19,\n\tMT6358_ID_VCN28 = 20,\n\tMT6358_ID_VSRAM_OTHERS = 21,\n\tMT6358_ID_VSRAM_GPU = 22,\n\tMT6358_ID_VXO22 = 23,\n\tMT6358_ID_VEFUSE = 24,\n\tMT6358_ID_VAUX18 = 25,\n\tMT6358_ID_VMCH = 26,\n\tMT6358_ID_VBIF28 = 27,\n\tMT6358_ID_VSRAM_PROC12 = 28,\n\tMT6358_ID_VCAMA1 = 29,\n\tMT6358_ID_VEMC = 30,\n\tMT6358_ID_VIO28 = 31,\n\tMT6358_ID_VA12 = 32,\n\tMT6358_ID_VRF18 = 33,\n\tMT6358_ID_VCN33 = 34,\n\tMT6358_ID_VCAMA2 = 35,\n\tMT6358_ID_VMC = 36,\n\tMT6358_ID_VLDO28 = 37,\n\tMT6358_ID_VAUD28 = 38,\n\tMT6358_ID_VSIM2 = 39,\n\tMT6358_ID_RG_MAX = 40,\n};\n\nenum {\n\tMT6359_ID_VS1 = 0,\n\tMT6359_ID_VGPU11 = 1,\n\tMT6359_ID_VMODEM = 2,\n\tMT6359_ID_VPU = 3,\n\tMT6359_ID_VCORE = 4,\n\tMT6359_ID_VS2 = 5,\n\tMT6359_ID_VPA = 6,\n\tMT6359_ID_VPROC2 = 7,\n\tMT6359_ID_VPROC1 = 8,\n\tMT6359_ID_VCORE_SSHUB = 9,\n\tMT6359_ID_VGPU11_SSHUB = 9,\n\tMT6359_ID_VAUD18 = 10,\n\tMT6359_ID_VSIM1 = 11,\n\tMT6359_ID_VIBR = 12,\n\tMT6359_ID_VRF12 = 13,\n\tMT6359_ID_VUSB = 14,\n\tMT6359_ID_VSRAM_PROC2 = 15,\n\tMT6359_ID_VIO18 = 16,\n\tMT6359_ID_VCAMIO = 17,\n\tMT6359_ID_VCN18 = 18,\n\tMT6359_ID_VFE28 = 19,\n\tMT6359_ID_VCN13 = 20,\n\tMT6359_ID_VCN33_1_BT = 21,\n\tMT6359_ID_VCN33_1_WIFI = 22,\n\tMT6359_ID_VAUX18 = 23,\n\tMT6359_ID_VSRAM_OTHERS = 24,\n\tMT6359_ID_VEFUSE = 25,\n\tMT6359_ID_VXO22 = 26,\n\tMT6359_ID_VRFCK = 27,\n\tMT6359_ID_VBIF28 = 28,\n\tMT6359_ID_VIO28 = 29,\n\tMT6359_ID_VEMC = 30,\n\tMT6359_ID_VCN33_2_BT = 31,\n\tMT6359_ID_VCN33_2_WIFI = 32,\n\tMT6359_ID_VA12 = 33,\n\tMT6359_ID_VA09 = 34,\n\tMT6359_ID_VRF18 = 35,\n\tMT6359_ID_VSRAM_MD = 36,\n\tMT6359_ID_VUFS = 37,\n\tMT6359_ID_VM18 = 38,\n\tMT6359_ID_VBBCK = 39,\n\tMT6359_ID_VSRAM_PROC1 = 40,\n\tMT6359_ID_VSIM2 = 41,\n\tMT6359_ID_VSRAM_OTHERS_SSHUB = 42,\n\tMT6359_ID_RG_MAX = 43,\n};\n\nenum {\n\tMT6360_REGULATOR_BUCK1 = 0,\n\tMT6360_REGULATOR_BUCK2 = 1,\n\tMT6360_REGULATOR_LDO6 = 2,\n\tMT6360_REGULATOR_LDO7 = 3,\n\tMT6360_REGULATOR_LDO1 = 4,\n\tMT6360_REGULATOR_LDO2 = 5,\n\tMT6360_REGULATOR_LDO3 = 6,\n\tMT6360_REGULATOR_LDO5 = 7,\n\tMT6360_REGULATOR_MAX = 8,\n};\n\nenum {\n\tMT6360_SLAVE_TCPC = 0,\n\tMT6360_SLAVE_PMIC = 1,\n\tMT6360_SLAVE_LDO = 2,\n\tMT6360_SLAVE_PMU = 3,\n\tMT6360_SLAVE_MAX = 4,\n};\n\nenum {\n\tMT6366_ID_VDRAM1 = 0,\n\tMT6366_ID_VCORE = 1,\n\tMT6366_ID_VPA = 2,\n\tMT6366_ID_VPROC11 = 3,\n\tMT6366_ID_VPROC12 = 4,\n\tMT6366_ID_VGPU = 5,\n\tMT6366_ID_VS2 = 6,\n\tMT6366_ID_VMODEM = 7,\n\tMT6366_ID_VS1 = 8,\n\tMT6366_ID_VDRAM2 = 9,\n\tMT6366_ID_VSIM1 = 10,\n\tMT6366_ID_VIBR = 11,\n\tMT6366_ID_VRF12 = 12,\n\tMT6366_ID_VIO18 = 13,\n\tMT6366_ID_VUSB = 14,\n\tMT6366_ID_VCN18 = 15,\n\tMT6366_ID_VFE28 = 16,\n\tMT6366_ID_VSRAM_PROC11 = 17,\n\tMT6366_ID_VCN28 = 18,\n\tMT6366_ID_VSRAM_OTHERS = 19,\n\tMT6366_ID_VSRAM_GPU = 20,\n\tMT6366_ID_VXO22 = 21,\n\tMT6366_ID_VEFUSE = 22,\n\tMT6366_ID_VAUX18 = 23,\n\tMT6366_ID_VMCH = 24,\n\tMT6366_ID_VBIF28 = 25,\n\tMT6366_ID_VSRAM_PROC12 = 26,\n\tMT6366_ID_VEMC = 27,\n\tMT6366_ID_VIO28 = 28,\n\tMT6366_ID_VA12 = 29,\n\tMT6366_ID_VRF18 = 30,\n\tMT6366_ID_VCN33 = 31,\n\tMT6366_ID_VMC = 32,\n\tMT6366_ID_VAUD28 = 33,\n\tMT6366_ID_VSIM2 = 34,\n\tMT6366_ID_VM18 = 35,\n\tMT6366_ID_VMDDR = 36,\n\tMT6366_ID_VSRAM_CORE = 37,\n\tMT6366_ID_RG_MAX = 38,\n};\n\nenum {\n\tMT6397_ID_VPCA15 = 0,\n\tMT6397_ID_VPCA7 = 1,\n\tMT6397_ID_VSRAMCA15 = 2,\n\tMT6397_ID_VSRAMCA7 = 3,\n\tMT6397_ID_VCORE = 4,\n\tMT6397_ID_VGPU = 5,\n\tMT6397_ID_VDRM = 6,\n\tMT6397_ID_VIO18 = 7,\n\tMT6397_ID_VTCXO = 8,\n\tMT6397_ID_VA28 = 9,\n\tMT6397_ID_VCAMA = 10,\n\tMT6397_ID_VIO28 = 11,\n\tMT6397_ID_VUSB = 12,\n\tMT6397_ID_VMC = 13,\n\tMT6397_ID_VMCH = 14,\n\tMT6397_ID_VEMC3V3 = 15,\n\tMT6397_ID_VGP1 = 16,\n\tMT6397_ID_VGP2 = 17,\n\tMT6397_ID_VGP3 = 18,\n\tMT6397_ID_VGP4 = 19,\n\tMT6397_ID_VGP5 = 20,\n\tMT6397_ID_VGP6 = 21,\n\tMT6397_ID_VIBR = 22,\n\tMT6397_ID_RG_MAX = 23,\n};\n\nenum {\n\tMTD_OPS_PLACE_OOB = 0,\n\tMTD_OPS_AUTO_OOB = 1,\n\tMTD_OPS_RAW = 2,\n};\n\nenum {\n\tMTK_UART_FC_NONE = 0,\n\tMTK_UART_FC_SW = 1,\n\tMTK_UART_FC_HW = 2,\n};\n\nenum {\n\tMUSB_CONTROLLER_MHDRC = 0,\n\tMUSB_CONTROLLER_HDRC = 1,\n};\n\nenum {\n\tMV64XXX_I2C_ACTION_INVALID = 0,\n\tMV64XXX_I2C_ACTION_CONTINUE = 1,\n\tMV64XXX_I2C_ACTION_SEND_RESTART = 2,\n\tMV64XXX_I2C_ACTION_SEND_ADDR_1 = 3,\n\tMV64XXX_I2C_ACTION_SEND_ADDR_2 = 4,\n\tMV64XXX_I2C_ACTION_SEND_DATA = 5,\n\tMV64XXX_I2C_ACTION_RCV_DATA = 6,\n\tMV64XXX_I2C_ACTION_RCV_DATA_STOP = 7,\n\tMV64XXX_I2C_ACTION_SEND_STOP = 8,\n};\n\nenum {\n\tMV64XXX_I2C_STATE_INVALID = 0,\n\tMV64XXX_I2C_STATE_IDLE = 1,\n\tMV64XXX_I2C_STATE_WAITING_FOR_START_COND = 2,\n\tMV64XXX_I2C_STATE_WAITING_FOR_RESTART = 3,\n\tMV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK = 4,\n\tMV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK = 5,\n\tMV64XXX_I2C_STATE_WAITING_FOR_TARGET_ACK = 6,\n\tMV64XXX_I2C_STATE_WAITING_FOR_TARGET_DATA = 7,\n};\n\nenum {\n\tMV_PMA_FW_VER0 = 49169,\n\tMV_PMA_FW_VER1 = 49170,\n\tMV_PMA_21X0_PORT_CTRL = 49226,\n\tMV_PMA_21X0_PORT_CTRL_SWRST = 32768,\n\tMV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 7,\n\tMV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0,\n\tMV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 1,\n\tMV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 2,\n\tMV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 4,\n\tMV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 5,\n\tMV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 6,\n\tMV_PMA_BOOT = 49232,\n\tMV_PMA_BOOT_FATAL = 1,\n\tMV_PCS_BASE_T = 0,\n\tMV_PCS_BASE_R = 4096,\n\tMV_PCS_1000BASEX = 8192,\n\tMV_PCS_CSCR1 = 32768,\n\tMV_PCS_CSCR1_ED_MASK = 768,\n\tMV_PCS_CSCR1_ED_OFF = 0,\n\tMV_PCS_CSCR1_ED_RX = 512,\n\tMV_PCS_CSCR1_ED_NLP = 768,\n\tMV_PCS_CSCR1_MDIX_MASK = 96,\n\tMV_PCS_CSCR1_MDIX_MDI = 0,\n\tMV_PCS_CSCR1_MDIX_MDIX = 32,\n\tMV_PCS_CSCR1_MDIX_AUTO = 96,\n\tMV_PCS_DSC1 = 32771,\n\tMV_PCS_DSC1_ENABLE = 512,\n\tMV_PCS_DSC1_10GBT = 448,\n\tMV_PCS_DSC1_1GBR = 56,\n\tMV_PCS_DSC1_100BTX = 7,\n\tMV_PCS_DSC2 = 32772,\n\tMV_PCS_DSC2_2P5G = 61440,\n\tMV_PCS_DSC2_5G = 3840,\n\tMV_PCS_CSSR1 = 32776,\n\tMV_PCS_CSSR1_SPD1_MASK = 49152,\n\tMV_PCS_CSSR1_SPD1_SPD2 = 49152,\n\tMV_PCS_CSSR1_SPD1_1000 = 32768,\n\tMV_PCS_CSSR1_SPD1_100 = 16384,\n\tMV_PCS_CSSR1_SPD1_10 = 0,\n\tMV_PCS_CSSR1_DUPLEX_FULL = 8192,\n\tMV_PCS_CSSR1_RESOLVED = 2048,\n\tMV_PCS_CSSR1_MDIX = 64,\n\tMV_PCS_CSSR1_SPD2_MASK = 12,\n\tMV_PCS_CSSR1_SPD2_5000 = 8,\n\tMV_PCS_CSSR1_SPD2_2500 = 4,\n\tMV_PCS_CSSR1_SPD2_10000 = 0,\n\tMV_PCS_TEMP = 32834,\n\tMV_PCS_PORT_INFO = 53261,\n\tMV_PCS_PORT_INFO_NPORTS_MASK = 896,\n\tMV_PCS_PORT_INFO_NPORTS_SHIFT = 7,\n\tMV_AN_21X0_SERDES_CTRL2 = 32783,\n\tMV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = 8192,\n\tMV_AN_21X0_SERDES_CTRL2_RUN_INIT = 32768,\n\tMV_AN_CTRL1000 = 32768,\n\tMV_AN_STAT1000 = 32769,\n\tMV_V2_PORT_CTRL = 61441,\n\tMV_V2_PORT_CTRL_PWRDOWN = 2048,\n\tMV_V2_33X0_PORT_CTRL_SWRST = 32768,\n\tMV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 7,\n\tMV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0,\n\tMV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 1,\n\tMV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 1,\n\tMV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 2,\n\tMV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 3,\n\tMV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 4,\n\tMV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 5,\n\tMV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 6,\n\tMV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 7,\n\tMV_V2_PORT_INTR_STS = 61504,\n\tMV_V2_PORT_INTR_MASK = 61507,\n\tMV_V2_PORT_INTR_STS_WOL_EN = 256,\n\tMV_V2_MAGIC_PKT_WORD0 = 61547,\n\tMV_V2_MAGIC_PKT_WORD1 = 61548,\n\tMV_V2_MAGIC_PKT_WORD2 = 61549,\n\tMV_V2_WOL_CTRL = 61550,\n\tMV_V2_WOL_CTRL_CLEAR_STS = 32768,\n\tMV_V2_WOL_CTRL_MAGIC_PKT_EN = 1,\n\tMV_V2_TEMP_CTRL = 61578,\n\tMV_V2_TEMP_CTRL_MASK = 49152,\n\tMV_V2_TEMP_CTRL_SAMPLE = 0,\n\tMV_V2_TEMP_CTRL_DISABLE = 49152,\n\tMV_V2_TEMP = 61580,\n\tMV_V2_TEMP_UNKNOWN = 38400,\n};\n\nenum {\n\tM_I17 = 0,\n\tM_I20 = 1,\n\tM_I20_SR = 2,\n\tM_I24 = 3,\n\tM_I24_8_1 = 4,\n\tM_I24_10_1 = 5,\n\tM_I27_11_1 = 6,\n\tM_MINI = 7,\n\tM_MINI_3_1 = 8,\n\tM_MINI_4_1 = 9,\n\tM_MB = 10,\n\tM_MB_2 = 11,\n\tM_MB_3 = 12,\n\tM_MB_5_1 = 13,\n\tM_MB_6_1 = 14,\n\tM_MB_7_1 = 15,\n\tM_MB_SR = 16,\n\tM_MBA = 17,\n\tM_MBA_3 = 18,\n\tM_MBP = 19,\n\tM_MBP_2 = 20,\n\tM_MBP_2_2 = 21,\n\tM_MBP_SR = 22,\n\tM_MBP_4 = 23,\n\tM_MBP_5_1 = 24,\n\tM_MBP_5_2 = 25,\n\tM_MBP_5_3 = 26,\n\tM_MBP_6_1 = 27,\n\tM_MBP_6_2 = 28,\n\tM_MBP_7_1 = 29,\n\tM_MBP_8_2 = 30,\n\tM_UNKNOWN = 31,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETDEV_STATS = 0,\n\tE1000_STATS = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNFSPROC4_CLNT_NULL = 0,\n\tNFSPROC4_CLNT_READ = 1,\n\tNFSPROC4_CLNT_WRITE = 2,\n\tNFSPROC4_CLNT_COMMIT = 3,\n\tNFSPROC4_CLNT_OPEN = 4,\n\tNFSPROC4_CLNT_OPEN_CONFIRM = 5,\n\tNFSPROC4_CLNT_OPEN_NOATTR = 6,\n\tNFSPROC4_CLNT_OPEN_DOWNGRADE = 7,\n\tNFSPROC4_CLNT_CLOSE = 8,\n\tNFSPROC4_CLNT_SETATTR = 9,\n\tNFSPROC4_CLNT_FSINFO = 10,\n\tNFSPROC4_CLNT_RENEW = 11,\n\tNFSPROC4_CLNT_SETCLIENTID = 12,\n\tNFSPROC4_CLNT_SETCLIENTID_CONFIRM = 13,\n\tNFSPROC4_CLNT_LOCK = 14,\n\tNFSPROC4_CLNT_LOCKT = 15,\n\tNFSPROC4_CLNT_LOCKU = 16,\n\tNFSPROC4_CLNT_ACCESS = 17,\n\tNFSPROC4_CLNT_GETATTR = 18,\n\tNFSPROC4_CLNT_LOOKUP = 19,\n\tNFSPROC4_CLNT_LOOKUP_ROOT = 20,\n\tNFSPROC4_CLNT_REMOVE = 21,\n\tNFSPROC4_CLNT_RENAME = 22,\n\tNFSPROC4_CLNT_LINK = 23,\n\tNFSPROC4_CLNT_SYMLINK = 24,\n\tNFSPROC4_CLNT_CREATE = 25,\n\tNFSPROC4_CLNT_PATHCONF = 26,\n\tNFSPROC4_CLNT_STATFS = 27,\n\tNFSPROC4_CLNT_READLINK = 28,\n\tNFSPROC4_CLNT_READDIR = 29,\n\tNFSPROC4_CLNT_SERVER_CAPS = 30,\n\tNFSPROC4_CLNT_DELEGRETURN = 31,\n\tNFSPROC4_CLNT_GETACL = 32,\n\tNFSPROC4_CLNT_SETACL = 33,\n\tNFSPROC4_CLNT_FS_LOCATIONS = 34,\n\tNFSPROC4_CLNT_RELEASE_LOCKOWNER = 35,\n\tNFSPROC4_CLNT_SECINFO = 36,\n\tNFSPROC4_CLNT_FSID_PRESENT = 37,\n\tNFSPROC4_CLNT_EXCHANGE_ID = 38,\n\tNFSPROC4_CLNT_CREATE_SESSION = 39,\n\tNFSPROC4_CLNT_DESTROY_SESSION = 40,\n\tNFSPROC4_CLNT_SEQUENCE = 41,\n\tNFSPROC4_CLNT_GET_LEASE_TIME = 42,\n\tNFSPROC4_CLNT_RECLAIM_COMPLETE = 43,\n\tNFSPROC4_CLNT_LAYOUTGET = 44,\n\tNFSPROC4_CLNT_GETDEVICEINFO = 45,\n\tNFSPROC4_CLNT_LAYOUTCOMMIT = 46,\n\tNFSPROC4_CLNT_LAYOUTRETURN = 47,\n\tNFSPROC4_CLNT_SECINFO_NO_NAME = 48,\n\tNFSPROC4_CLNT_TEST_STATEID = 49,\n\tNFSPROC4_CLNT_FREE_STATEID = 50,\n\tNFSPROC4_CLNT_GETDEVICELIST = 51,\n\tNFSPROC4_CLNT_BIND_CONN_TO_SESSION = 52,\n\tNFSPROC4_CLNT_DESTROY_CLIENTID = 53,\n\tNFSPROC4_CLNT_SEEK = 54,\n\tNFSPROC4_CLNT_ALLOCATE = 55,\n\tNFSPROC4_CLNT_DEALLOCATE = 56,\n\tNFSPROC4_CLNT_ZERO_RANGE = 57,\n\tNFSPROC4_CLNT_LAYOUTSTATS = 58,\n\tNFSPROC4_CLNT_CLONE = 59,\n\tNFSPROC4_CLNT_COPY = 60,\n\tNFSPROC4_CLNT_OFFLOAD_CANCEL = 61,\n\tNFSPROC4_CLNT_LOOKUPP = 62,\n\tNFSPROC4_CLNT_LAYOUTERROR = 63,\n\tNFSPROC4_CLNT_COPY_NOTIFY = 64,\n\tNFSPROC4_CLNT_GETXATTR = 65,\n\tNFSPROC4_CLNT_SETXATTR = 66,\n\tNFSPROC4_CLNT_LISTXATTRS = 67,\n\tNFSPROC4_CLNT_REMOVEXATTR = 68,\n\tNFSPROC4_CLNT_READ_PLUS = 69,\n\tNFSPROC4_CLNT_OFFLOAD_STATUS = 70,\n};\n\nenum {\n\tNFS_DELEGATION_NEED_RECLAIM = 0,\n\tNFS_DELEGATION_RETURN_IF_CLOSED = 1,\n\tNFS_DELEGATION_REFERENCED = 2,\n\tNFS_DELEGATION_RETURNING = 3,\n\tNFS_DELEGATION_REVOKED = 4,\n\tNFS_DELEGATION_TEST_EXPIRED = 5,\n\tNFS_DELEGATION_DELEGTIME = 6,\n};\n\nenum {\n\tNFS_DEVICEID_INVALID = 0,\n\tNFS_DEVICEID_UNAVAILABLE = 1,\n\tNFS_DEVICEID_NOCACHE = 2,\n};\n\nenum {\n\tNFS_IOHDR_ERROR = 0,\n\tNFS_IOHDR_EOF = 1,\n\tNFS_IOHDR_REDO = 2,\n\tNFS_IOHDR_STAT = 3,\n\tNFS_IOHDR_RESEND_PNFS = 4,\n\tNFS_IOHDR_RESEND_MDS = 5,\n\tNFS_IOHDR_UNSTABLE_WRITES = 6,\n\tNFS_IOHDR_ODIRECT = 7,\n};\n\nenum {\n\tNFS_LAYOUT_RO_FAILED = 0,\n\tNFS_LAYOUT_RW_FAILED = 1,\n\tNFS_LAYOUT_BULK_RECALL = 2,\n\tNFS_LAYOUT_RETURN = 3,\n\tNFS_LAYOUT_RETURN_LOCK = 4,\n\tNFS_LAYOUT_RETURN_REQUESTED = 5,\n\tNFS_LAYOUT_INVALID_STID = 6,\n\tNFS_LAYOUT_FIRST_LAYOUTGET = 7,\n\tNFS_LAYOUT_INODE_FREEING = 8,\n\tNFS_LAYOUT_HASHED = 9,\n\tNFS_LAYOUT_DRAIN = 10,\n};\n\nenum {\n\tNFS_LSEG_VALID = 0,\n\tNFS_LSEG_ROC = 1,\n\tNFS_LSEG_LAYOUTCOMMIT = 2,\n\tNFS_LSEG_LAYOUTRETURN = 3,\n\tNFS_LSEG_UNAVAILABLE = 4,\n};\n\nenum {\n\tNFS_OWNER_RECLAIM_REBOOT = 0,\n\tNFS_OWNER_RECLAIM_NOGRACE = 1,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNLM_LCK_GRANTED = 0,\n\tNLM_LCK_DENIED = 1,\n\tNLM_LCK_DENIED_NOLOCKS = 2,\n\tNLM_LCK_BLOCKED = 3,\n\tNLM_LCK_DENIED_GRACE_PERIOD = 4,\n\tNLM_DEADLCK = 5,\n\tNLM_ROFS = 6,\n\tNLM_STALE_FH = 7,\n\tNLM_FBIG = 8,\n\tNLM_FAILED = 9,\n};\n\nenum {\n\tNODE_ACCESS_CLASS_GENPORT_SINK_LOCAL = 2,\n\tNODE_ACCESS_CLASS_GENPORT_SINK_CPU = 3,\n\tNODE_ACCESS_CLASS_MAX = 4,\n};\n\nenum {\n\tNORTH = 0,\n\tSOUTH = 1,\n\tEAST = 2,\n};\n\nenum {\n\tNORTH___2 = 0,\n\tSOUTH___2 = 1,\n\tWEST = 2,\n};\n\nenum {\n\tNORTH___3 = 0,\n\tCENTER = 1,\n\tSOUTH___3 = 2,\n};\n\nenum {\n\tNORTH___4 = 0,\n\tSOUTH___4 = 1,\n\tEAST___2 = 2,\n\tWEST___2 = 3,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNSMPROC_NULL = 0,\n\tNSMPROC_STAT = 1,\n\tNSMPROC_MON = 2,\n\tNSMPROC_UNMON = 3,\n\tNSMPROC_UNMON_ALL = 4,\n\tNSMPROC_SIMU_CRASH = 5,\n\tNSMPROC_NOTIFY = 6,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 16,\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n\tNVMEM_LAYOUT_ADD = 5,\n\tNVMEM_LAYOUT_REMOVE = 6,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tOD_NORMAL_SAMPLE = 0,\n\tOD_SUB_SAMPLE = 1,\n};\n\nenum {\n\tOMAP_I2C_REV_REG = 0,\n\tOMAP_I2C_IE_REG = 1,\n\tOMAP_I2C_STAT_REG = 2,\n\tOMAP_I2C_IV_REG = 3,\n\tOMAP_I2C_WE_REG = 4,\n\tOMAP_I2C_SYSS_REG = 5,\n\tOMAP_I2C_BUF_REG = 6,\n\tOMAP_I2C_CNT_REG = 7,\n\tOMAP_I2C_DATA_REG = 8,\n\tOMAP_I2C_SYSC_REG = 9,\n\tOMAP_I2C_CON_REG = 10,\n\tOMAP_I2C_OA_REG = 11,\n\tOMAP_I2C_SA_REG = 12,\n\tOMAP_I2C_PSC_REG = 13,\n\tOMAP_I2C_SCLL_REG = 14,\n\tOMAP_I2C_SCLH_REG = 15,\n\tOMAP_I2C_SYSTEST_REG = 16,\n\tOMAP_I2C_BUFSTAT_REG = 17,\n\tOMAP_I2C_IP_V2_REVNB_LO = 18,\n\tOMAP_I2C_IP_V2_REVNB_HI = 19,\n\tOMAP_I2C_IP_V2_IRQSTATUS_RAW = 20,\n\tOMAP_I2C_IP_V2_IRQENABLE_SET = 21,\n\tOMAP_I2C_IP_V2_IRQENABLE_CLR = 22,\n};\n\nenum {\n\tONLINE_POLICY_CONTIG_ZONES = 0,\n\tONLINE_POLICY_AUTO_MOVABLE = 1,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOUTSIDE_GUEST_MODE = 0,\n\tIN_GUEST_MODE = 1,\n\tEXITING_GUEST_MODE = 2,\n\tREADING_SHADOW_PAGE_TABLES = 3,\n};\n\nenum {\n\tOVERRIDE_NONE = 0,\n\tOVERRIDE_BASE = 1,\n\tOVERRIDE_STRIDE = 2,\n\tOVERRIDE_HEIGHT = 4,\n\tOVERRIDE_WIDTH = 8,\n};\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid = 2,\n\tOpt_nogrpid = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb = 6,\n\tOpt_nouid32 = 7,\n\tOpt_debug = 8,\n\tOpt_removed = 9,\n\tOpt_user_xattr = 10,\n\tOpt_acl = 11,\n\tOpt_auto_da_alloc = 12,\n\tOpt_noauto_da_alloc = 13,\n\tOpt_noload = 14,\n\tOpt_commit = 15,\n\tOpt_min_batch_time = 16,\n\tOpt_max_batch_time = 17,\n\tOpt_journal_dev = 18,\n\tOpt_journal_path = 19,\n\tOpt_journal_checksum = 20,\n\tOpt_journal_async_commit = 21,\n\tOpt_abort = 22,\n\tOpt_data_journal = 23,\n\tOpt_data_ordered = 24,\n\tOpt_data_writeback = 25,\n\tOpt_data_err_abort = 26,\n\tOpt_data_err_ignore = 27,\n\tOpt_test_dummy_encryption = 28,\n\tOpt_inlinecrypt = 29,\n\tOpt_usrjquota = 30,\n\tOpt_grpjquota = 31,\n\tOpt_quota = 32,\n\tOpt_noquota = 33,\n\tOpt_barrier = 34,\n\tOpt_nobarrier = 35,\n\tOpt_err = 36,\n\tOpt_usrquota = 37,\n\tOpt_grpquota = 38,\n\tOpt_prjquota = 39,\n\tOpt_dax = 40,\n\tOpt_dax_always = 41,\n\tOpt_dax_inode = 42,\n\tOpt_dax_never = 43,\n\tOpt_stripe = 44,\n\tOpt_delalloc = 45,\n\tOpt_nodelalloc = 46,\n\tOpt_warn_on_error = 47,\n\tOpt_nowarn_on_error = 48,\n\tOpt_mblk_io_submit = 49,\n\tOpt_debug_want_extra_isize = 50,\n\tOpt_nomblk_io_submit = 51,\n\tOpt_block_validity = 52,\n\tOpt_noblock_validity = 53,\n\tOpt_inode_readahead_blks = 54,\n\tOpt_journal_ioprio = 55,\n\tOpt_dioread_nolock = 56,\n\tOpt_dioread_lock = 57,\n\tOpt_discard = 58,\n\tOpt_nodiscard = 59,\n\tOpt_init_itable = 60,\n\tOpt_noinit_itable = 61,\n\tOpt_max_dir_size_kb = 62,\n\tOpt_nojournal_checksum = 63,\n\tOpt_nombcache = 64,\n\tOpt_no_prefetch_block_bitmaps = 65,\n\tOpt_mb_optimize_scan = 66,\n\tOpt_errors = 67,\n\tOpt_data = 68,\n\tOpt_data_err = 69,\n\tOpt_jqfmt = 70,\n\tOpt_dax_type = 71,\n};\n\nenum {\n\tOpt_check = 0,\n\tOpt_uid = 1,\n\tOpt_gid = 2,\n\tOpt_umask = 3,\n\tOpt_dmask = 4,\n\tOpt_fmask = 5,\n\tOpt_allow_utime = 6,\n\tOpt_codepage = 7,\n\tOpt_usefree = 8,\n\tOpt_nocase = 9,\n\tOpt_quiet = 10,\n\tOpt_showexec = 11,\n\tOpt_debug___2 = 12,\n\tOpt_immutable = 13,\n\tOpt_dots = 14,\n\tOpt_dotsOK = 15,\n\tOpt_charset = 16,\n\tOpt_shortname = 17,\n\tOpt_utf8 = 18,\n\tOpt_utf8_bool = 19,\n\tOpt_uni_xl = 20,\n\tOpt_uni_xl_bool = 21,\n\tOpt_nonumtail = 22,\n\tOpt_nonumtail_bool = 23,\n\tOpt_obsolete = 24,\n\tOpt_flush = 25,\n\tOpt_tz = 26,\n\tOpt_rodir = 27,\n\tOpt_errors___2 = 28,\n\tOpt_discard___2 = 29,\n\tOpt_nfs = 30,\n\tOpt_nfs_enum = 31,\n\tOpt_time_offset = 32,\n\tOpt_dos1xfloppy = 33,\n};\n\nenum {\n\tOpt_direct = 0,\n\tOpt_fd = 1,\n\tOpt_gid___2 = 2,\n\tOpt_ignore = 3,\n\tOpt_indirect = 4,\n\tOpt_maxproto = 5,\n\tOpt_minproto = 6,\n\tOpt_offset = 7,\n\tOpt_pgrp = 8,\n\tOpt_strictexpire = 9,\n\tOpt_uid___2 = 10,\n};\n\nenum {\n\tOpt_err___2 = 0,\n\tOpt_enc = 1,\n\tOpt_hash = 2,\n};\n\nenum {\n\tOpt_fatal_neterrors_default = 0,\n\tOpt_fatal_neterrors_enetunreach = 1,\n\tOpt_fatal_neterrors_none = 2,\n};\n\nenum {\n\tOpt_find_uid = 0,\n\tOpt_find_gid = 1,\n\tOpt_find_user = 2,\n\tOpt_find_group = 3,\n\tOpt_find_err = 4,\n};\n\nenum {\n\tOpt_kmsg_bytes = 0,\n};\n\nenum {\n\tOpt_local_lock_all = 0,\n\tOpt_local_lock_flock = 1,\n\tOpt_local_lock_none = 2,\n\tOpt_local_lock_posix = 3,\n};\n\nenum {\n\tOpt_lookupcache_all = 0,\n\tOpt_lookupcache_none = 1,\n\tOpt_lookupcache_positive = 2,\n};\n\nenum {\n\tOpt_sec_krb5 = 0,\n\tOpt_sec_krb5i = 1,\n\tOpt_sec_krb5p = 2,\n\tOpt_sec_lkey = 3,\n\tOpt_sec_lkeyi = 4,\n\tOpt_sec_lkeyp = 5,\n\tOpt_sec_none = 6,\n\tOpt_sec_spkm = 7,\n\tOpt_sec_spkmi = 8,\n\tOpt_sec_spkmp = 9,\n\tOpt_sec_sys = 10,\n\tnr__Opt_sec = 11,\n};\n\nenum {\n\tOpt_source = 0,\n\tOpt_debug___3 = 1,\n\tOpt_dfltuid = 2,\n\tOpt_dfltgid = 3,\n\tOpt_afid = 4,\n\tOpt_uname = 5,\n\tOpt_remotename = 6,\n\tOpt_cache = 7,\n\tOpt_cachetag = 8,\n\tOpt_nodevmap = 9,\n\tOpt_noxattr = 10,\n\tOpt_directio = 11,\n\tOpt_ignoreqv = 12,\n\tOpt_access = 13,\n\tOpt_posixacl = 14,\n\tOpt_locktimeout = 15,\n\tOpt_msize = 16,\n\tOpt_trans = 17,\n\tOpt_legacy = 18,\n\tOpt_version = 19,\n\tOpt_rfdno = 20,\n\tOpt_wfdno = 21,\n\tOpt_rq_depth = 22,\n\tOpt_sq_depth = 23,\n\tOpt_timeout = 24,\n\tOpt_port = 25,\n\tOpt_privport = 26,\n};\n\nenum {\n\tOpt_uid___3 = 0,\n\tOpt_gid___3 = 1,\n};\n\nenum {\n\tOpt_uid___4 = 0,\n\tOpt_gid___4 = 1,\n\tOpt_mode = 2,\n};\n\nenum {\n\tOpt_uid___5 = 0,\n\tOpt_gid___5 = 1,\n\tOpt_mode___2 = 2,\n\tOpt_source___2 = 3,\n};\n\nenum {\n\tOpt_uid___6 = 0,\n\tOpt_gid___6 = 1,\n\tOpt_mode___3 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___3 = 6,\n};\n\nenum {\n\tOpt_vers_2 = 0,\n\tOpt_vers_3 = 1,\n\tOpt_vers_4 = 2,\n\tOpt_vers_4_0 = 3,\n\tOpt_vers_4_1 = 4,\n\tOpt_vers_4_2 = 5,\n};\n\nenum {\n\tOpt_write_lazy = 0,\n\tOpt_write_eager = 1,\n\tOpt_write_wait = 2,\n};\n\nenum {\n\tOpt_xprt_rdma = 0,\n\tOpt_xprt_rdma6 = 1,\n\tOpt_xprt_tcp = 2,\n\tOpt_xprt_tcp6 = 3,\n\tOpt_xprt_udp = 4,\n\tOpt_xprt_udp6 = 5,\n\tnr__Opt_xprt = 6,\n};\n\nenum {\n\tOpt_xprtsec_none = 0,\n\tOpt_xprtsec_tls = 1,\n\tOpt_xprtsec_mtls = 2,\n\tnr__Opt_xprtsec = 3,\n};\n\nenum {\n\tPAGE_REPORTING_IDLE = 0,\n\tPAGE_REPORTING_REQUESTED = 1,\n\tPAGE_REPORTING_ACTIVE = 2,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPARSE_INVALID = 1,\n\tPARSE_NOT_LONGNAME = 2,\n\tPARSE_EOF = 3,\n};\n\nenum {\n\tPCA9450_BUCK1 = 0,\n\tPCA9450_BUCK2 = 1,\n\tPCA9450_BUCK3 = 2,\n\tPCA9450_BUCK4 = 3,\n\tPCA9450_BUCK5 = 4,\n\tPCA9450_BUCK6 = 5,\n\tPCA9450_LDO1 = 6,\n\tPCA9450_LDO2 = 7,\n\tPCA9450_LDO3 = 8,\n\tPCA9450_LDO4 = 9,\n\tPCA9450_LDO5 = 10,\n\tPCA9450_REGULATOR_CNT = 11,\n};\n\nenum {\n\tPCA9450_DVS_LEVEL_RUN = 0,\n\tPCA9450_DVS_LEVEL_STANDBY = 1,\n\tPCA9450_DVS_LEVEL_MAX = 2,\n};\n\nenum {\n\tPCA9450_REG_DEV_ID = 0,\n\tPCA9450_REG_INT1 = 1,\n\tPCA9450_REG_INT1_MSK = 2,\n\tPCA9450_REG_STATUS1 = 3,\n\tPCA9450_REG_STATUS2 = 4,\n\tPCA9450_REG_PWRON_STAT = 5,\n\tPCA9450_REG_SWRST = 6,\n\tPCA9450_REG_PWRCTRL = 7,\n\tPCA9450_REG_RESET_CTRL = 8,\n\tPCA9450_REG_CONFIG1 = 9,\n\tPCA9450_REG_CONFIG2 = 10,\n\tPCA9450_REG_BUCK123_DVS = 12,\n\tPCA9450_REG_BUCK1OUT_LIMIT = 13,\n\tPCA9450_REG_BUCK2OUT_LIMIT = 14,\n\tPCA9450_REG_BUCK3OUT_LIMIT = 15,\n\tPCA9450_REG_BUCK1CTRL = 16,\n\tPCA9450_REG_BUCK1OUT_DVS0 = 17,\n\tPCA9450_REG_BUCK1OUT_DVS1 = 18,\n\tPCA9450_REG_BUCK2CTRL = 19,\n\tPCA9450_REG_BUCK2OUT_DVS0 = 20,\n\tPCA9450_REG_BUCK2OUT_DVS1 = 21,\n\tPCA9450_REG_BUCK3CTRL = 22,\n\tPCA9450_REG_BUCK3OUT_DVS0 = 23,\n\tPCA9450_REG_BUCK3OUT_DVS1 = 24,\n\tPCA9450_REG_BUCK4CTRL = 25,\n\tPCA9450_REG_BUCK4OUT = 26,\n\tPCA9450_REG_BUCK5CTRL = 27,\n\tPCA9450_REG_BUCK5OUT = 28,\n\tPCA9450_REG_BUCK6CTRL = 29,\n\tPCA9450_REG_BUCK6OUT = 30,\n\tPCA9450_REG_LDO_AD_CTRL = 32,\n\tPCA9450_REG_LDO1CTRL = 33,\n\tPCA9450_REG_LDO2CTRL = 34,\n\tPCA9450_REG_LDO3CTRL = 35,\n\tPCA9450_REG_LDO4CTRL = 36,\n\tPCA9450_REG_LDO5CTRL_L = 37,\n\tPCA9450_REG_LDO5CTRL_H = 38,\n\tPCA9450_REG_LOADSW_CTRL = 42,\n\tPCA9450_REG_VRFLT1_STS = 43,\n\tPCA9450_REG_VRFLT2_STS = 44,\n\tPCA9450_REG_VRFLT1_MASK = 45,\n\tPCA9450_REG_VRFLT2_MASK = 46,\n\tPCA9450_MAX_REGISTER = 47,\n};\n\nenum {\n\tPCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = 1,\n\tPCI_BRIDGE_EMUL_NO_IO_FORWARD = 2,\n};\n\nenum {\n\tPCI_DEV_REG1 = 64,\n\tPCI_DEV_REG2 = 68,\n\tPCI_DEV_STATUS = 124,\n\tPCI_DEV_REG3 = 128,\n\tPCI_DEV_REG4 = 132,\n\tPCI_DEV_REG5 = 136,\n\tPCI_CFG_REG_0 = 144,\n\tPCI_CFG_REG_1 = 148,\n\tPSM_CONFIG_REG0 = 152,\n\tPSM_CONFIG_REG1 = 156,\n\tPSM_CONFIG_REG2 = 352,\n\tPSM_CONFIG_REG3 = 356,\n\tPSM_CONFIG_REG4 = 360,\n\tPCI_LDO_CTRL = 188,\n};\n\nenum {\n\tPCI_ID_F_VFIO_DRIVER_OVERRIDE = 1,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_IOV_RESOURCES = 7,\n\tPCI_IOV_RESOURCE_END = 12,\n\tPCI_BRIDGE_RESOURCES = 13,\n\tPCI_BRIDGE_RESOURCE_END = 16,\n\tPCI_NUM_RESOURCES = 17,\n\tDEVICE_COUNT_RESOURCE = 17,\n};\n\nenum {\n\tPC_VAUX_ENA = 128,\n\tPC_VAUX_DIS = 64,\n\tPC_VCC_ENA = 32,\n\tPC_VCC_DIS = 16,\n\tPC_VAUX_ON = 8,\n\tPC_VAUX_OFF = 4,\n\tPC_VCC_ON = 2,\n\tPC_VCC_OFF = 1,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPERF_BR_NEW_FAULT_ALGN = 0,\n\tPERF_BR_NEW_FAULT_DATA = 1,\n\tPERF_BR_NEW_FAULT_INST = 2,\n\tPERF_BR_NEW_ARCH_1 = 3,\n\tPERF_BR_NEW_ARCH_2 = 4,\n\tPERF_BR_NEW_ARCH_3 = 5,\n\tPERF_BR_NEW_ARCH_4 = 6,\n\tPERF_BR_NEW_ARCH_5 = 7,\n\tPERF_BR_NEW_MAX = 8,\n};\n\nenum {\n\tPERF_BR_PRIV_UNKNOWN = 0,\n\tPERF_BR_PRIV_USER = 1,\n\tPERF_BR_PRIV_KERNEL = 2,\n\tPERF_BR_PRIV_HV = 3,\n};\n\nenum {\n\tPERF_BR_SPEC_NA = 0,\n\tPERF_BR_SPEC_WRONG_PATH = 1,\n\tPERF_BR_NON_SPEC_CORRECT_PATH = 2,\n\tPERF_BR_SPEC_CORRECT_PATH = 3,\n\tPERF_BR_SPEC_MAX = 4,\n};\n\nenum {\n\tPERF_BR_UNKNOWN = 0,\n\tPERF_BR_COND = 1,\n\tPERF_BR_UNCOND = 2,\n\tPERF_BR_IND = 3,\n\tPERF_BR_CALL = 4,\n\tPERF_BR_IND_CALL = 5,\n\tPERF_BR_RET = 6,\n\tPERF_BR_SYSCALL = 7,\n\tPERF_BR_SYSRET = 8,\n\tPERF_BR_COND_CALL = 9,\n\tPERF_BR_COND_RET = 10,\n\tPERF_BR_ERET = 11,\n\tPERF_BR_IRQ = 12,\n\tPERF_BR_SERROR = 13,\n\tPERF_BR_NO_TX = 14,\n\tPERF_BR_EXTEND_ABI = 15,\n\tPERF_BR_MAX = 16,\n};\n\nenum {\n\tPERF_FC_LEVEL = 0,\n\tPERF_FC_LIMIT = 1,\n\tPERF_FC_MAX = 2,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPEX_RD_ACCESS = -2147483648,\n\tPEX_DB_ACCESS = 1073741824,\n};\n\nenum {\n\tPG_BUSY = 0,\n\tPG_MAPPED = 1,\n\tPG_FOLIO = 2,\n\tPG_CLEAN = 3,\n\tPG_COMMIT_TO_DS = 4,\n\tPG_INODE_REF = 5,\n\tPG_HEADLOCK = 6,\n\tPG_TEARDOWN = 7,\n\tPG_UNLOCKPAGE = 8,\n\tPG_UPTODATE = 9,\n\tPG_WB_END = 10,\n\tPG_REMOVE = 11,\n\tPG_CONTENDED1 = 12,\n\tPG_CONTENDED2 = 13,\n};\n\nenum {\n\tPHYLINK_DISABLE_STOPPED = 0,\n\tPHYLINK_DISABLE_LINK = 1,\n\tPHYLINK_DISABLE_MAC_WOL = 2,\n\tPHYLINK_DISABLE_REPLAY = 3,\n\tPCS_STATE_DOWN = 0,\n\tPCS_STATE_STARTING = 1,\n\tPCS_STATE_STARTED = 2,\n};\n\nenum {\n\tPHY_ADDR_MARV = 0,\n};\n\nenum {\n\tPHY_AN_NXT_PG = 32768,\n\tPHY_AN_ACK = 16384,\n\tPHY_AN_RF = 8192,\n\tPHY_AN_PAUSE_ASYM = 2048,\n\tPHY_AN_PAUSE_CAP = 1024,\n\tPHY_AN_100BASE4 = 512,\n\tPHY_AN_100FULL = 256,\n\tPHY_AN_100HALF = 128,\n\tPHY_AN_10FULL = 64,\n\tPHY_AN_10HALF = 32,\n\tPHY_AN_CSMA = 1,\n\tPHY_AN_SEL = 31,\n\tPHY_AN_FULL = 321,\n\tPHY_AN_ALL = 480,\n};\n\nenum {\n\tPHY_CT_RESET = 32768,\n\tPHY_CT_LOOP = 16384,\n\tPHY_CT_SPS_LSB = 8192,\n\tPHY_CT_ANE = 4096,\n\tPHY_CT_PDOWN = 2048,\n\tPHY_CT_ISOL = 1024,\n\tPHY_CT_RE_CFG = 512,\n\tPHY_CT_DUP_MD = 256,\n\tPHY_CT_COL_TST = 128,\n\tPHY_CT_SPS_MSB = 64,\n};\n\nenum {\n\tPHY_CT_SP1000 = 64,\n\tPHY_CT_SP100 = 8192,\n\tPHY_CT_SP10 = 0,\n};\n\nenum {\n\tPHY_GMII_SEL_PORT_MODE = 0,\n\tPHY_GMII_SEL_RGMII_ID_MODE = 1,\n\tPHY_GMII_SEL_RMII_IO_CLK_EN = 2,\n\tPHY_GMII_SEL_FIXED_TX_DELAY = 3,\n\tPHY_GMII_SEL_LAST = 4,\n};\n\nenum {\n\tPHY_MARV_CTRL = 0,\n\tPHY_MARV_STAT = 1,\n\tPHY_MARV_ID0 = 2,\n\tPHY_MARV_ID1 = 3,\n\tPHY_MARV_AUNE_ADV = 4,\n\tPHY_MARV_AUNE_LP = 5,\n\tPHY_MARV_AUNE_EXP = 6,\n\tPHY_MARV_NEPG = 7,\n\tPHY_MARV_NEPG_LP = 8,\n\tPHY_MARV_1000T_CTRL = 9,\n\tPHY_MARV_1000T_STAT = 10,\n\tPHY_MARV_EXT_STAT = 15,\n\tPHY_MARV_PHY_CTRL = 16,\n\tPHY_MARV_PHY_STAT = 17,\n\tPHY_MARV_INT_MASK = 18,\n\tPHY_MARV_INT_STAT = 19,\n\tPHY_MARV_EXT_CTRL = 20,\n\tPHY_MARV_RXE_CNT = 21,\n\tPHY_MARV_EXT_ADR = 22,\n\tPHY_MARV_PORT_IRQ = 23,\n\tPHY_MARV_LED_CTRL = 24,\n\tPHY_MARV_LED_OVER = 25,\n\tPHY_MARV_EXT_CTRL_2 = 26,\n\tPHY_MARV_EXT_P_STAT = 27,\n\tPHY_MARV_CABLE_DIAG = 28,\n\tPHY_MARV_PAGE_ADDR = 29,\n\tPHY_MARV_PAGE_DATA = 30,\n\tPHY_MARV_FE_LED_PAR = 22,\n\tPHY_MARV_FE_LED_SER = 23,\n\tPHY_MARV_FE_VCT_TX = 26,\n\tPHY_MARV_FE_VCT_RX = 27,\n\tPHY_MARV_FE_SPEC_2 = 28,\n};\n\nenum {\n\tPHY_MARV_ID0_VAL = 321,\n\tPHY_BCOM_ID1_A1 = 24641,\n\tPHY_BCOM_ID1_B2 = 24643,\n\tPHY_BCOM_ID1_C0 = 24644,\n\tPHY_BCOM_ID1_C5 = 24647,\n\tPHY_MARV_ID1_B0 = 3107,\n\tPHY_MARV_ID1_B2 = 3109,\n\tPHY_MARV_ID1_C2 = 3266,\n\tPHY_MARV_ID1_Y2 = 3217,\n\tPHY_MARV_ID1_FE = 3203,\n\tPHY_MARV_ID1_ECU = 3248,\n};\n\nenum {\n\tPHY_M_1000C_TEST = 57344,\n\tPHY_M_1000C_MSE = 4096,\n\tPHY_M_1000C_MSC = 2048,\n\tPHY_M_1000C_MPD = 1024,\n\tPHY_M_1000C_AFD = 512,\n\tPHY_M_1000C_AHD = 256,\n};\n\nenum {\n\tPHY_M_AN_ASP_X = 256,\n\tPHY_M_AN_PC_X = 128,\n\tPHY_M_AN_1000X_AHD = 64,\n\tPHY_M_AN_1000X_AFD = 32,\n};\n\nenum {\n\tPHY_M_AN_NXT_PG = 32768,\n\tPHY_M_AN_ACK = 16384,\n\tPHY_M_AN_RF = 8192,\n\tPHY_M_AN_ASP = 2048,\n\tPHY_M_AN_PC = 1024,\n\tPHY_M_AN_100_T4 = 512,\n\tPHY_M_AN_100_FD = 256,\n\tPHY_M_AN_100_HD = 128,\n\tPHY_M_AN_10_FD = 64,\n\tPHY_M_AN_10_HD = 32,\n\tPHY_M_AN_SEL_MSK = 496,\n};\n\nenum {\n\tPHY_M_EC_ENA_BC_EXT = 32768,\n\tPHY_M_EC_ENA_LIN_LB = 16384,\n\tPHY_M_EC_DIS_LINK_P = 4096,\n\tPHY_M_EC_M_DSC_MSK = 3072,\n\tPHY_M_EC_S_DSC_MSK = 768,\n\tPHY_M_EC_M_DSC_MSK2 = 3584,\n\tPHY_M_EC_DOWN_S_ENA = 256,\n\tPHY_M_EC_RX_TIM_CT = 128,\n\tPHY_M_EC_MAC_S_MSK = 112,\n\tPHY_M_EC_FIB_AN_ENA = 8,\n\tPHY_M_EC_DTE_D_ENA = 4,\n\tPHY_M_EC_TX_TIM_CT = 2,\n\tPHY_M_EC_TRANS_DIS = 1,\n\tPHY_M_10B_TE_ENABLE = 128,\n};\n\nenum {\n\tPHY_M_FC_AUTO_SEL = 32768,\n\tPHY_M_FC_AN_REG_ACC = 16384,\n\tPHY_M_FC_RESOLUTION = 8192,\n\tPHY_M_SER_IF_AN_BP = 4096,\n\tPHY_M_SER_IF_BP_ST = 2048,\n\tPHY_M_IRQ_POLARITY = 1024,\n\tPHY_M_DIS_AUT_MED = 512,\n\tPHY_M_UNDOC1 = 128,\n\tPHY_M_DTE_POW_STAT = 16,\n\tPHY_M_MODE_MASK = 15,\n};\n\nenum {\n\tPHY_M_FELP_LED2_MSK = 3840,\n\tPHY_M_FELP_LED1_MSK = 240,\n\tPHY_M_FELP_LED0_MSK = 15,\n};\n\nenum {\n\tPHY_M_FESC_DIS_WAIT = 4,\n\tPHY_M_FESC_ENA_MCLK = 2,\n\tPHY_M_FESC_SEL_CL_A = 1,\n};\n\nenum {\n\tPHY_M_FIB_FORCE_LNK = 1024,\n\tPHY_M_FIB_SIGD_POL = 512,\n\tPHY_M_FIB_TX_DIS = 8,\n};\n\nenum {\n\tPHY_M_IS_AN_ERROR = 32768,\n\tPHY_M_IS_LSP_CHANGE = 16384,\n\tPHY_M_IS_DUP_CHANGE = 8192,\n\tPHY_M_IS_AN_PR = 4096,\n\tPHY_M_IS_AN_COMPL = 2048,\n\tPHY_M_IS_LST_CHANGE = 1024,\n\tPHY_M_IS_SYMB_ERROR = 512,\n\tPHY_M_IS_FALSE_CARR = 256,\n\tPHY_M_IS_FIFO_ERROR = 128,\n\tPHY_M_IS_MDI_CHANGE = 64,\n\tPHY_M_IS_DOWNSH_DET = 32,\n\tPHY_M_IS_END_CHANGE = 16,\n\tPHY_M_IS_DTE_CHANGE = 4,\n\tPHY_M_IS_POL_CHANGE = 2,\n\tPHY_M_IS_JABBER = 1,\n\tPHY_M_DEF_MSK = 25600,\n\tPHY_M_AN_MSK = 34816,\n};\n\nenum {\n\tPHY_M_LEDC_DIS_LED = 32768,\n\tPHY_M_LEDC_PULS_MSK = 28672,\n\tPHY_M_LEDC_F_INT = 2048,\n\tPHY_M_LEDC_BL_R_MSK = 1792,\n\tPHY_M_LEDC_DP_C_LSB = 128,\n\tPHY_M_LEDC_TX_C_LSB = 64,\n\tPHY_M_LEDC_LK_C_MSK = 56,\n};\n\nenum {\n\tPHY_M_LEDC_LINK_MSK = 24,\n\tPHY_M_LEDC_DP_CTRL = 4,\n\tPHY_M_LEDC_DP_C_MSB = 4,\n\tPHY_M_LEDC_RX_CTRL = 2,\n\tPHY_M_LEDC_TX_CTRL = 1,\n\tPHY_M_LEDC_TX_C_MSB = 1,\n};\n\nenum {\n\tPHY_M_LEDC_LOS_MSK = 61440,\n\tPHY_M_LEDC_INIT_MSK = 3840,\n\tPHY_M_LEDC_STA1_MSK = 240,\n\tPHY_M_LEDC_STA0_MSK = 15,\n};\n\nenum {\n\tPHY_M_MAC_MD_MSK = 896,\n\tPHY_M_MAC_GMIF_PUP = 8,\n\tPHY_M_MAC_MD_AUTO = 3,\n\tPHY_M_MAC_MD_COPPER = 5,\n\tPHY_M_MAC_MD_1000BX = 7,\n};\n\nenum {\n\tPHY_M_PC_COP_TX_DIS = 8,\n\tPHY_M_PC_POW_D_ENA = 4,\n};\n\nenum {\n\tPHY_M_PC_DIS_LINK_Pa = 32768,\n\tPHY_M_PC_DSC_MSK = 28672,\n\tPHY_M_PC_DOWN_S_ENA = 2048,\n};\n\nenum {\n\tPHY_M_PC_ENA_DTE_DT = 32768,\n\tPHY_M_PC_ENA_ENE_DT = 16384,\n\tPHY_M_PC_DIS_NLP_CK = 8192,\n\tPHY_M_PC_ENA_LIP_NP = 4096,\n\tPHY_M_PC_DIS_NLP_GN = 2048,\n\tPHY_M_PC_DIS_SCRAMB = 512,\n\tPHY_M_PC_DIS_FEFI = 256,\n\tPHY_M_PC_SH_TP_SEL = 64,\n\tPHY_M_PC_RX_FD_MSK = 12,\n};\n\nenum {\n\tPHY_M_PC_MAN_MDI = 0,\n\tPHY_M_PC_MAN_MDIX = 1,\n\tPHY_M_PC_ENA_AUTO = 3,\n};\n\nenum {\n\tPHY_M_PC_TX_FFD_MSK = 49152,\n\tPHY_M_PC_RX_FFD_MSK = 12288,\n\tPHY_M_PC_ASS_CRS_TX = 2048,\n\tPHY_M_PC_FL_GOOD = 1024,\n\tPHY_M_PC_EN_DET_MSK = 768,\n\tPHY_M_PC_ENA_EXT_D = 128,\n\tPHY_M_PC_MDIX_MSK = 96,\n\tPHY_M_PC_DIS_125CLK = 16,\n\tPHY_M_PC_MAC_POW_UP = 8,\n\tPHY_M_PC_SQE_T_ENA = 4,\n\tPHY_M_PC_POL_R_DIS = 2,\n\tPHY_M_PC_DIS_JABBER = 1,\n};\n\nenum {\n\tPHY_M_POLC_LS1M_MSK = 61440,\n\tPHY_M_POLC_IS0M_MSK = 3840,\n\tPHY_M_POLC_LOS_MSK = 192,\n\tPHY_M_POLC_INIT_MSK = 48,\n\tPHY_M_POLC_STA1_MSK = 12,\n\tPHY_M_POLC_STA0_MSK = 3,\n};\n\nenum {\n\tPHY_M_PS_SPEED_MSK = 49152,\n\tPHY_M_PS_SPEED_1000 = 32768,\n\tPHY_M_PS_SPEED_100 = 16384,\n\tPHY_M_PS_SPEED_10 = 0,\n\tPHY_M_PS_FULL_DUP = 8192,\n\tPHY_M_PS_PAGE_REC = 4096,\n\tPHY_M_PS_SPDUP_RES = 2048,\n\tPHY_M_PS_LINK_UP = 1024,\n\tPHY_M_PS_CABLE_MSK = 896,\n\tPHY_M_PS_MDI_X_STAT = 64,\n\tPHY_M_PS_DOWNS_STAT = 32,\n\tPHY_M_PS_ENDET_STAT = 16,\n\tPHY_M_PS_TX_P_EN = 8,\n\tPHY_M_PS_RX_P_EN = 4,\n\tPHY_M_PS_POL_REV = 2,\n\tPHY_M_PS_JABBER = 1,\n};\n\nenum {\n\tPHY_M_P_NO_PAUSE_X = 0,\n\tPHY_M_P_SYM_MD_X = 128,\n\tPHY_M_P_ASYM_MD_X = 256,\n\tPHY_M_P_BOTH_MD_X = 384,\n};\n\nenum {\n\tPINCTRL_PIN_REG_MODE = 0,\n\tPINCTRL_PIN_REG_DIR = 1,\n\tPINCTRL_PIN_REG_DI = 2,\n\tPINCTRL_PIN_REG_DO = 3,\n\tPINCTRL_PIN_REG_SR = 4,\n\tPINCTRL_PIN_REG_SMT = 5,\n\tPINCTRL_PIN_REG_PD = 6,\n\tPINCTRL_PIN_REG_PU = 7,\n\tPINCTRL_PIN_REG_E4 = 8,\n\tPINCTRL_PIN_REG_E8 = 9,\n\tPINCTRL_PIN_REG_TDSEL = 10,\n\tPINCTRL_PIN_REG_RDSEL = 11,\n\tPINCTRL_PIN_REG_DRV = 12,\n\tPINCTRL_PIN_REG_PUPD = 13,\n\tPINCTRL_PIN_REG_R0 = 14,\n\tPINCTRL_PIN_REG_R1 = 15,\n\tPINCTRL_PIN_REG_IES = 16,\n\tPINCTRL_PIN_REG_PULLEN = 17,\n\tPINCTRL_PIN_REG_PULLSEL = 18,\n\tPINCTRL_PIN_REG_DRV_EN = 19,\n\tPINCTRL_PIN_REG_DRV_E0 = 20,\n\tPINCTRL_PIN_REG_DRV_E1 = 21,\n\tPINCTRL_PIN_REG_DRV_ADV = 22,\n\tPINCTRL_PIN_REG_RSEL = 23,\n\tPINCTRL_PIN_REG_MAX = 24,\n};\n\nenum {\n\tPINMUX_RESERVED = 0,\n\tPINMUX_DATA_BEGIN = 1,\n\tGP_0_0_DATA = 2,\n\tGP_0_1_DATA = 3,\n\tGP_0_2_DATA = 4,\n\tGP_0_3_DATA = 5,\n\tGP_0_4_DATA = 6,\n\tGP_0_5_DATA = 7,\n\tGP_0_6_DATA = 8,\n\tGP_0_7_DATA = 9,\n\tGP_0_8_DATA = 10,\n\tGP_0_9_DATA = 11,\n\tGP_0_10_DATA = 12,\n\tGP_0_11_DATA = 13,\n\tGP_0_12_DATA = 14,\n\tGP_0_13_DATA = 15,\n\tGP_0_14_DATA = 16,\n\tGP_0_15_DATA = 17,\n\tGP_0_16_DATA = 18,\n\tGP_0_17_DATA = 19,\n\tGP_0_18_DATA = 20,\n\tGP_1_0_DATA = 21,\n\tGP_1_1_DATA = 22,\n\tGP_1_2_DATA = 23,\n\tGP_1_3_DATA = 24,\n\tGP_1_4_DATA = 25,\n\tGP_1_5_DATA = 26,\n\tGP_1_6_DATA = 27,\n\tGP_1_7_DATA = 28,\n\tGP_1_8_DATA = 29,\n\tGP_1_9_DATA = 30,\n\tGP_1_10_DATA = 31,\n\tGP_1_11_DATA = 32,\n\tGP_1_12_DATA = 33,\n\tGP_1_13_DATA = 34,\n\tGP_1_14_DATA = 35,\n\tGP_1_15_DATA = 36,\n\tGP_1_16_DATA = 37,\n\tGP_1_17_DATA = 38,\n\tGP_1_18_DATA = 39,\n\tGP_1_19_DATA = 40,\n\tGP_1_20_DATA = 41,\n\tGP_1_21_DATA = 42,\n\tGP_1_22_DATA = 43,\n\tGP_1_23_DATA = 44,\n\tGP_1_24_DATA = 45,\n\tGP_1_25_DATA = 46,\n\tGP_1_26_DATA = 47,\n\tGP_1_27_DATA = 48,\n\tGP_1_28_DATA = 49,\n\tGP_2_0_DATA = 50,\n\tGP_2_1_DATA = 51,\n\tGP_2_2_DATA = 52,\n\tGP_2_3_DATA = 53,\n\tGP_2_4_DATA = 54,\n\tGP_2_5_DATA = 55,\n\tGP_2_6_DATA = 56,\n\tGP_2_7_DATA = 57,\n\tGP_2_8_DATA = 58,\n\tGP_2_9_DATA = 59,\n\tGP_2_10_DATA = 60,\n\tGP_2_11_DATA = 61,\n\tGP_2_12_DATA = 62,\n\tGP_2_13_DATA = 63,\n\tGP_2_14_DATA = 64,\n\tGP_2_15_DATA = 65,\n\tGP_2_16_DATA = 66,\n\tGP_2_17_DATA = 67,\n\tGP_2_18_DATA = 68,\n\tGP_2_19_DATA = 69,\n\tGP_3_0_DATA = 70,\n\tGP_3_1_DATA = 71,\n\tGP_3_2_DATA = 72,\n\tGP_3_3_DATA = 73,\n\tGP_3_4_DATA = 74,\n\tGP_3_5_DATA = 75,\n\tGP_3_6_DATA = 76,\n\tGP_3_7_DATA = 77,\n\tGP_3_8_DATA = 78,\n\tGP_3_9_DATA = 79,\n\tGP_3_10_DATA = 80,\n\tGP_3_11_DATA = 81,\n\tGP_3_12_DATA = 82,\n\tGP_3_13_DATA = 83,\n\tGP_3_14_DATA = 84,\n\tGP_3_15_DATA = 85,\n\tGP_3_16_DATA = 86,\n\tGP_3_17_DATA = 87,\n\tGP_3_18_DATA = 88,\n\tGP_3_19_DATA = 89,\n\tGP_3_20_DATA = 90,\n\tGP_3_21_DATA = 91,\n\tGP_3_22_DATA = 92,\n\tGP_3_23_DATA = 93,\n\tGP_3_24_DATA = 94,\n\tGP_3_25_DATA = 95,\n\tGP_3_26_DATA = 96,\n\tGP_3_27_DATA = 97,\n\tGP_3_28_DATA = 98,\n\tGP_3_29_DATA = 99,\n\tGP_4_0_DATA = 100,\n\tGP_4_1_DATA = 101,\n\tGP_4_2_DATA = 102,\n\tGP_4_3_DATA = 103,\n\tGP_4_4_DATA = 104,\n\tGP_4_5_DATA = 105,\n\tGP_4_6_DATA = 106,\n\tGP_4_7_DATA = 107,\n\tGP_4_8_DATA = 108,\n\tGP_4_9_DATA = 109,\n\tGP_4_10_DATA = 110,\n\tGP_4_11_DATA = 111,\n\tGP_4_12_DATA = 112,\n\tGP_4_13_DATA = 113,\n\tGP_4_14_DATA = 114,\n\tGP_4_15_DATA = 115,\n\tGP_4_16_DATA = 116,\n\tGP_4_17_DATA = 117,\n\tGP_4_18_DATA = 118,\n\tGP_4_19_DATA = 119,\n\tGP_4_20_DATA = 120,\n\tGP_4_21_DATA = 121,\n\tGP_4_22_DATA = 122,\n\tGP_4_23_DATA = 123,\n\tGP_4_24_DATA = 124,\n\tGP_5_0_DATA = 125,\n\tGP_5_1_DATA = 126,\n\tGP_5_2_DATA = 127,\n\tGP_5_3_DATA = 128,\n\tGP_5_4_DATA = 129,\n\tGP_5_5_DATA = 130,\n\tGP_5_6_DATA = 131,\n\tGP_5_7_DATA = 132,\n\tGP_5_8_DATA = 133,\n\tGP_5_9_DATA = 134,\n\tGP_5_10_DATA = 135,\n\tGP_5_11_DATA = 136,\n\tGP_5_12_DATA = 137,\n\tGP_5_13_DATA = 138,\n\tGP_5_14_DATA = 139,\n\tGP_5_15_DATA = 140,\n\tGP_5_16_DATA = 141,\n\tGP_5_17_DATA = 142,\n\tGP_5_18_DATA = 143,\n\tGP_5_19_DATA = 144,\n\tGP_5_20_DATA = 145,\n\tGP_6_0_DATA = 146,\n\tGP_6_1_DATA = 147,\n\tGP_6_2_DATA = 148,\n\tGP_6_3_DATA = 149,\n\tGP_6_4_DATA = 150,\n\tGP_6_5_DATA = 151,\n\tGP_6_6_DATA = 152,\n\tGP_6_7_DATA = 153,\n\tGP_6_8_DATA = 154,\n\tGP_6_9_DATA = 155,\n\tGP_6_10_DATA = 156,\n\tGP_6_11_DATA = 157,\n\tGP_6_12_DATA = 158,\n\tGP_6_13_DATA = 159,\n\tGP_6_14_DATA = 160,\n\tGP_6_15_DATA = 161,\n\tGP_6_16_DATA = 162,\n\tGP_6_17_DATA = 163,\n\tGP_6_18_DATA = 164,\n\tGP_6_19_DATA = 165,\n\tGP_6_20_DATA = 166,\n\tGP_7_0_DATA = 167,\n\tGP_7_1_DATA = 168,\n\tGP_7_2_DATA = 169,\n\tGP_7_3_DATA = 170,\n\tGP_7_4_DATA = 171,\n\tGP_7_5_DATA = 172,\n\tGP_7_6_DATA = 173,\n\tGP_7_7_DATA = 174,\n\tGP_7_8_DATA = 175,\n\tGP_7_9_DATA = 176,\n\tGP_7_10_DATA = 177,\n\tGP_7_11_DATA = 178,\n\tGP_7_12_DATA = 179,\n\tGP_7_13_DATA = 180,\n\tGP_7_14_DATA = 181,\n\tGP_7_15_DATA = 182,\n\tGP_7_16_DATA = 183,\n\tGP_7_17_DATA = 184,\n\tGP_7_18_DATA = 185,\n\tGP_7_19_DATA = 186,\n\tGP_7_20_DATA = 187,\n\tGP_8_0_DATA = 188,\n\tGP_8_1_DATA = 189,\n\tGP_8_2_DATA = 190,\n\tGP_8_3_DATA = 191,\n\tGP_8_4_DATA = 192,\n\tGP_8_5_DATA = 193,\n\tGP_8_6_DATA = 194,\n\tGP_8_7_DATA = 195,\n\tGP_8_8_DATA = 196,\n\tGP_8_9_DATA = 197,\n\tGP_8_10_DATA = 198,\n\tGP_8_11_DATA = 199,\n\tGP_8_12_DATA = 200,\n\tGP_8_13_DATA = 201,\n\tPINMUX_DATA_END = 202,\n\tPINMUX_FUNCTION_BEGIN = 203,\n\tGP_0_0_FN = 204,\n\tGP_0_1_FN = 205,\n\tGP_0_2_FN = 206,\n\tGP_0_3_FN = 207,\n\tGP_0_4_FN = 208,\n\tGP_0_5_FN = 209,\n\tGP_0_6_FN = 210,\n\tGP_0_7_FN = 211,\n\tGP_0_8_FN = 212,\n\tGP_0_9_FN = 213,\n\tGP_0_10_FN = 214,\n\tGP_0_11_FN = 215,\n\tGP_0_12_FN = 216,\n\tGP_0_13_FN = 217,\n\tGP_0_14_FN = 218,\n\tGP_0_15_FN = 219,\n\tGP_0_16_FN = 220,\n\tGP_0_17_FN = 221,\n\tGP_0_18_FN = 222,\n\tGP_1_0_FN = 223,\n\tGP_1_1_FN = 224,\n\tGP_1_2_FN = 225,\n\tGP_1_3_FN = 226,\n\tGP_1_4_FN = 227,\n\tGP_1_5_FN = 228,\n\tGP_1_6_FN = 229,\n\tGP_1_7_FN = 230,\n\tGP_1_8_FN = 231,\n\tGP_1_9_FN = 232,\n\tGP_1_10_FN = 233,\n\tGP_1_11_FN = 234,\n\tGP_1_12_FN = 235,\n\tGP_1_13_FN = 236,\n\tGP_1_14_FN = 237,\n\tGP_1_15_FN = 238,\n\tGP_1_16_FN = 239,\n\tGP_1_17_FN = 240,\n\tGP_1_18_FN = 241,\n\tGP_1_19_FN = 242,\n\tGP_1_20_FN = 243,\n\tGP_1_21_FN = 244,\n\tGP_1_22_FN = 245,\n\tGP_1_23_FN = 246,\n\tGP_1_24_FN = 247,\n\tGP_1_25_FN = 248,\n\tGP_1_26_FN = 249,\n\tGP_1_27_FN = 250,\n\tGP_1_28_FN = 251,\n\tGP_2_0_FN = 252,\n\tGP_2_1_FN = 253,\n\tGP_2_2_FN = 254,\n\tGP_2_3_FN = 255,\n\tGP_2_4_FN = 256,\n\tGP_2_5_FN = 257,\n\tGP_2_6_FN = 258,\n\tGP_2_7_FN = 259,\n\tGP_2_8_FN = 260,\n\tGP_2_9_FN = 261,\n\tGP_2_10_FN = 262,\n\tGP_2_11_FN = 263,\n\tGP_2_12_FN = 264,\n\tGP_2_13_FN = 265,\n\tGP_2_14_FN = 266,\n\tGP_2_15_FN = 267,\n\tGP_2_16_FN = 268,\n\tGP_2_17_FN = 269,\n\tGP_2_18_FN = 270,\n\tGP_2_19_FN = 271,\n\tGP_3_0_FN = 272,\n\tGP_3_1_FN = 273,\n\tGP_3_2_FN = 274,\n\tGP_3_3_FN = 275,\n\tGP_3_4_FN = 276,\n\tGP_3_5_FN = 277,\n\tGP_3_6_FN = 278,\n\tGP_3_7_FN = 279,\n\tGP_3_8_FN = 280,\n\tGP_3_9_FN = 281,\n\tGP_3_10_FN = 282,\n\tGP_3_11_FN = 283,\n\tGP_3_12_FN = 284,\n\tGP_3_13_FN = 285,\n\tGP_3_14_FN = 286,\n\tGP_3_15_FN = 287,\n\tGP_3_16_FN = 288,\n\tGP_3_17_FN = 289,\n\tGP_3_18_FN = 290,\n\tGP_3_19_FN = 291,\n\tGP_3_20_FN = 292,\n\tGP_3_21_FN = 293,\n\tGP_3_22_FN = 294,\n\tGP_3_23_FN = 295,\n\tGP_3_24_FN = 296,\n\tGP_3_25_FN = 297,\n\tGP_3_26_FN = 298,\n\tGP_3_27_FN = 299,\n\tGP_3_28_FN = 300,\n\tGP_3_29_FN = 301,\n\tGP_4_0_FN = 302,\n\tGP_4_1_FN = 303,\n\tGP_4_2_FN = 304,\n\tGP_4_3_FN = 305,\n\tGP_4_4_FN = 306,\n\tGP_4_5_FN = 307,\n\tGP_4_6_FN = 308,\n\tGP_4_7_FN = 309,\n\tGP_4_8_FN = 310,\n\tGP_4_9_FN = 311,\n\tGP_4_10_FN = 312,\n\tGP_4_11_FN = 313,\n\tGP_4_12_FN = 314,\n\tGP_4_13_FN = 315,\n\tGP_4_14_FN = 316,\n\tGP_4_15_FN = 317,\n\tGP_4_16_FN = 318,\n\tGP_4_17_FN = 319,\n\tGP_4_18_FN = 320,\n\tGP_4_19_FN = 321,\n\tGP_4_20_FN = 322,\n\tGP_4_21_FN = 323,\n\tGP_4_22_FN = 324,\n\tGP_4_23_FN = 325,\n\tGP_4_24_FN = 326,\n\tGP_5_0_FN = 327,\n\tGP_5_1_FN = 328,\n\tGP_5_2_FN = 329,\n\tGP_5_3_FN = 330,\n\tGP_5_4_FN = 331,\n\tGP_5_5_FN = 332,\n\tGP_5_6_FN = 333,\n\tGP_5_7_FN = 334,\n\tGP_5_8_FN = 335,\n\tGP_5_9_FN = 336,\n\tGP_5_10_FN = 337,\n\tGP_5_11_FN = 338,\n\tGP_5_12_FN = 339,\n\tGP_5_13_FN = 340,\n\tGP_5_14_FN = 341,\n\tGP_5_15_FN = 342,\n\tGP_5_16_FN = 343,\n\tGP_5_17_FN = 344,\n\tGP_5_18_FN = 345,\n\tGP_5_19_FN = 346,\n\tGP_5_20_FN = 347,\n\tGP_6_0_FN = 348,\n\tGP_6_1_FN = 349,\n\tGP_6_2_FN = 350,\n\tGP_6_3_FN = 351,\n\tGP_6_4_FN = 352,\n\tGP_6_5_FN = 353,\n\tGP_6_6_FN = 354,\n\tGP_6_7_FN = 355,\n\tGP_6_8_FN = 356,\n\tGP_6_9_FN = 357,\n\tGP_6_10_FN = 358,\n\tGP_6_11_FN = 359,\n\tGP_6_12_FN = 360,\n\tGP_6_13_FN = 361,\n\tGP_6_14_FN = 362,\n\tGP_6_15_FN = 363,\n\tGP_6_16_FN = 364,\n\tGP_6_17_FN = 365,\n\tGP_6_18_FN = 366,\n\tGP_6_19_FN = 367,\n\tGP_6_20_FN = 368,\n\tGP_7_0_FN = 369,\n\tGP_7_1_FN = 370,\n\tGP_7_2_FN = 371,\n\tGP_7_3_FN = 372,\n\tGP_7_4_FN = 373,\n\tGP_7_5_FN = 374,\n\tGP_7_6_FN = 375,\n\tGP_7_7_FN = 376,\n\tGP_7_8_FN = 377,\n\tGP_7_9_FN = 378,\n\tGP_7_10_FN = 379,\n\tGP_7_11_FN = 380,\n\tGP_7_12_FN = 381,\n\tGP_7_13_FN = 382,\n\tGP_7_14_FN = 383,\n\tGP_7_15_FN = 384,\n\tGP_7_16_FN = 385,\n\tGP_7_17_FN = 386,\n\tGP_7_18_FN = 387,\n\tGP_7_19_FN = 388,\n\tGP_7_20_FN = 389,\n\tGP_8_0_FN = 390,\n\tGP_8_1_FN = 391,\n\tGP_8_2_FN = 392,\n\tGP_8_3_FN = 393,\n\tGP_8_4_FN = 394,\n\tGP_8_5_FN = 395,\n\tGP_8_6_FN = 396,\n\tGP_8_7_FN = 397,\n\tGP_8_8_FN = 398,\n\tGP_8_9_FN = 399,\n\tGP_8_10_FN = 400,\n\tGP_8_11_FN = 401,\n\tGP_8_12_FN = 402,\n\tGP_8_13_FN = 403,\n\tFN_IP0SR0_3_0 = 404,\n\tFN_ERROROUTC_N_B = 405,\n\tFN_TCLK2_B = 406,\n\tFN_IP1SR0_3_0 = 407,\n\tFN_MSIOF5_SS1 = 408,\n\tFN_IP2SR0_3_0 = 409,\n\tFN_MSIOF2_TXD = 410,\n\tFN_HCTS1_N_A = 411,\n\tFN_CTS1_N_A = 412,\n\tFN_IP0SR0_7_4 = 413,\n\tFN_MSIOF3_SS1 = 414,\n\tFN_IP1SR0_7_4 = 415,\n\tFN_MSIOF5_SYNC = 416,\n\tFN_IP2SR0_7_4 = 417,\n\tFN_MSIOF2_SCK = 418,\n\tFN_HRTS1_N_A = 419,\n\tFN_RTS1_N_A = 420,\n\tFN_IP0SR0_11_8 = 421,\n\tFN_MSIOF3_SS2 = 422,\n\tFN_IP1SR0_11_8 = 423,\n\tFN_MSIOF5_TXD = 424,\n\tFN_IP2SR0_11_8 = 425,\n\tFN_MSIOF2_RXD = 426,\n\tFN_HSCK1_A = 427,\n\tFN_SCK1_A = 428,\n\tFN_IP0SR0_15_12 = 429,\n\tFN_IRQ3_A = 430,\n\tFN_MSIOF3_SCK = 431,\n\tFN_IP1SR0_15_12 = 432,\n\tFN_MSIOF5_SCK = 433,\n\tFN_IP0SR0_19_16 = 434,\n\tFN_IRQ2_A = 435,\n\tFN_MSIOF3_TXD = 436,\n\tFN_IP1SR0_19_16 = 437,\n\tFN_MSIOF5_RXD = 438,\n\tFN_IP0SR0_23_20 = 439,\n\tFN_IRQ1_A = 440,\n\tFN_MSIOF3_RXD = 441,\n\tFN_IP1SR0_23_20 = 442,\n\tFN_MSIOF2_SS2 = 443,\n\tFN_TCLK1_A = 444,\n\tFN_IRQ2_B = 445,\n\tFN_IP0SR0_27_24 = 446,\n\tFN_IRQ0_A = 447,\n\tFN_MSIOF3_SYNC = 448,\n\tFN_IP1SR0_27_24 = 449,\n\tFN_MSIOF2_SS1 = 450,\n\tFN_HTX1_A = 451,\n\tFN_TX1_A = 452,\n\tFN_IP0SR0_31_28 = 453,\n\tFN_MSIOF5_SS2 = 454,\n\tFN_IP1SR0_31_28 = 455,\n\tFN_MSIOF2_SYNC = 456,\n\tFN_HRX1_A = 457,\n\tFN_RX1_A = 458,\n\tFN_IP0SR1_3_0 = 459,\n\tFN_MSIOF1_SS2 = 460,\n\tFN_HTX3_B = 461,\n\tFN_TX3_B = 462,\n\tFN_IP1SR1_3_0 = 463,\n\tFN_MSIOF0_SYNC = 464,\n\tFN_HCTS1_N_B = 465,\n\tFN_CTS1_N_B = 466,\n\tFN_CANFD5_TX_B = 467,\n\tFN_IP2SR1_3_0 = 468,\n\tFN_HRX0 = 469,\n\tFN_RX0 = 470,\n\tFN_IP3SR1_3_0 = 471,\n\tFN_HRX3_A = 472,\n\tFN_SCK3_A = 473,\n\tFN_MSIOF4_SS2 = 474,\n\tFN_IP0SR1_7_4 = 475,\n\tFN_MSIOF1_SS1 = 476,\n\tFN_HCTS3_N_B = 477,\n\tFN_RX3_B = 478,\n\tFN_IP1SR1_7_4 = 479,\n\tFN_MSIOF0_TXD = 480,\n\tFN_HRTS1_N_B = 481,\n\tFN_RTS1_N_B = 482,\n\tFN_CANFD5_RX_B = 483,\n\tFN_IP2SR1_7_4 = 484,\n\tFN_SCIF_CLK = 485,\n\tFN_IRQ4_A = 486,\n\tFN_IP3SR1_7_4 = 487,\n\tFN_HSCK3_A = 488,\n\tFN_CTS3_N_A = 489,\n\tFN_MSIOF4_SCK = 490,\n\tFN_TPU0TO0_B = 491,\n\tFN_IP0SR1_11_8 = 492,\n\tFN_MSIOF1_SYNC = 493,\n\tFN_HRTS3_N_B = 494,\n\tFN_RTS3_N_B = 495,\n\tFN_IP1SR1_11_8 = 496,\n\tFN_MSIOF0_SCK = 497,\n\tFN_HSCK1_B = 498,\n\tFN_SCK1_B = 499,\n\tFN_IP2SR1_11_8 = 500,\n\tFN_SSI_SCK = 501,\n\tFN_TCLK3_B = 502,\n\tFN_IP3SR1_11_8 = 503,\n\tFN_HRTS3_N_A = 504,\n\tFN_RTS3_N_A = 505,\n\tFN_MSIOF4_TXD = 506,\n\tFN_TPU0TO1_B = 507,\n\tFN_IP0SR1_15_12 = 508,\n\tFN_MSIOF1_SCK = 509,\n\tFN_HSCK3_B = 510,\n\tFN_CTS3_N_B = 511,\n\tFN_IP1SR1_15_12 = 512,\n\tFN_MSIOF0_RXD = 513,\n\tFN_IP2SR1_15_12 = 514,\n\tFN_SSI_WS = 515,\n\tFN_TCLK4_B = 516,\n\tFN_IP3SR1_15_12 = 517,\n\tFN_HCTS3_N_A = 518,\n\tFN_RX3_A = 519,\n\tFN_MSIOF4_RXD = 520,\n\tFN_IP0SR1_19_16 = 521,\n\tFN_MSIOF1_TXD = 522,\n\tFN_HRX3_B = 523,\n\tFN_SCK3_B = 524,\n\tFN_IP1SR1_19_16 = 525,\n\tFN_HTX0 = 526,\n\tFN_TX0 = 527,\n\tFN_IP2SR1_19_16 = 528,\n\tFN_SSI_SD = 529,\n\tFN_IRQ0_B = 530,\n\tFN_IP3SR1_19_16 = 531,\n\tFN_HTX3_A = 532,\n\tFN_TX3_A = 533,\n\tFN_MSIOF4_SYNC = 534,\n\tFN_IP0SR1_23_20 = 535,\n\tFN_MSIOF1_RXD = 536,\n\tFN_IP1SR1_23_20 = 537,\n\tFN_HCTS0_N = 538,\n\tFN_CTS0_N = 539,\n\tFN_PWM8 = 540,\n\tFN_IP2SR1_23_20 = 541,\n\tFN_AUDIO_CLKOUT = 542,\n\tFN_IRQ1_B = 543,\n\tFN_IP0SR1_27_24 = 544,\n\tFN_MSIOF0_SS2 = 545,\n\tFN_HTX1_B = 546,\n\tFN_TX1_B = 547,\n\tFN_IP1SR1_27_24 = 548,\n\tFN_HRTS0_N = 549,\n\tFN_RTS0_N = 550,\n\tFN_PWM9 = 551,\n\tFN_IP2SR1_27_24 = 552,\n\tFN_AUDIO_CLKIN = 553,\n\tFN_PWM3_A = 554,\n\tFN_IP0SR1_31_28 = 555,\n\tFN_MSIOF0_SS1 = 556,\n\tFN_HRX1_B = 557,\n\tFN_RX1_B = 558,\n\tFN_IP1SR1_31_28 = 559,\n\tFN_HSCK0 = 560,\n\tFN_SCK0 = 561,\n\tFN_PWM0 = 562,\n\tFN_IP2SR1_31_28 = 563,\n\tFN_TCLK2_A = 564,\n\tFN_MSIOF4_SS1 = 565,\n\tFN_IRQ3_B = 566,\n\tFN_IP0SR2_3_0 = 567,\n\tFN_FXR_TXDA = 568,\n\tFN_CANFD1_TX = 569,\n\tFN_TPU0TO2_B = 570,\n\tFN_IP1SR2_3_0 = 571,\n\tFN_TPU0TO0_A = 572,\n\tFN_CANFD6_RX = 573,\n\tFN_TCLK1_B = 574,\n\tFN_IP2SR2_3_0 = 575,\n\tFN_CANFD4_TX = 576,\n\tFN_PWM4 = 577,\n\tFN_IP0SR2_7_4 = 578,\n\tFN_FXR_TXENA_N_A = 579,\n\tFN_CANFD1_RX = 580,\n\tFN_TPU0TO3_B = 581,\n\tFN_IP1SR2_7_4 = 582,\n\tFN_CAN_CLK = 583,\n\tFN_FXR_TXENA_N_B = 584,\n\tFN_IP2SR2_7_4 = 585,\n\tFN_CANFD4_RX = 586,\n\tFN_PWM5 = 587,\n\tFN_IP0SR2_11_8 = 588,\n\tFN_RXDA_EXTFXR = 589,\n\tFN_CANFD5_TX_A = 590,\n\tFN_IRQ5 = 591,\n\tFN_IP1SR2_11_8 = 592,\n\tFN_CANFD0_TX = 593,\n\tFN_FXR_TXENB_N_B = 594,\n\tFN_IP2SR2_11_8 = 595,\n\tFN_CANFD7_TX = 596,\n\tFN_PWM6 = 597,\n\tFN_IP0SR2_15_12 = 598,\n\tFN_CLK_EXTFXR = 599,\n\tFN_CANFD5_RX_A = 600,\n\tFN_IRQ4_B = 601,\n\tFN_IP1SR2_15_12 = 602,\n\tFN_CANFD0_RX = 603,\n\tFN_IP2SR2_15_12 = 604,\n\tFN_CANFD7_RX = 605,\n\tFN_PWM7 = 606,\n\tFN_IP0SR2_19_16 = 607,\n\tFN_RXDB_EXTFXR = 608,\n\tFN_IP1SR2_19_16 = 609,\n\tFN_CANFD2_TX = 610,\n\tFN_TPU0TO2_A = 611,\n\tFN_TCLK3_C = 612,\n\tFN_IP0SR2_23_20 = 613,\n\tFN_FXR_TXENB_N_A = 614,\n\tFN_IP1SR2_23_20 = 615,\n\tFN_CANFD2_RX = 616,\n\tFN_TPU0TO3_A = 617,\n\tFN_PWM1_B = 618,\n\tFN_TCLK4_C = 619,\n\tFN_IP0SR2_27_24 = 620,\n\tFN_FXR_TXDB = 621,\n\tFN_IP1SR2_27_24 = 622,\n\tFN_CANFD3_TX = 623,\n\tFN_PWM2 = 624,\n\tFN_IP0SR2_31_28 = 625,\n\tFN_TPU0TO1_A = 626,\n\tFN_CANFD6_TX = 627,\n\tFN_TCLK2_C = 628,\n\tFN_IP1SR2_31_28 = 629,\n\tFN_CANFD3_RX = 630,\n\tFN_PWM3_B = 631,\n\tFN_IP0SR3_3_0 = 632,\n\tFN_MMC_SD_D1 = 633,\n\tFN_IP1SR3_3_0 = 634,\n\tFN_MMC_D7 = 635,\n\tFN_IP2SR3_3_0 = 636,\n\tFN_QSPI0_IO3 = 637,\n\tFN_IP3SR3_3_0 = 638,\n\tFN_QSPI1_IO2 = 639,\n\tFN_IP0SR3_7_4 = 640,\n\tFN_MMC_SD_D0 = 641,\n\tFN_IP1SR3_7_4 = 642,\n\tFN_MMC_D6 = 643,\n\tFN_IP2SR3_7_4 = 644,\n\tFN_QSPI0_IO2 = 645,\n\tFN_IP3SR3_7_4 = 646,\n\tFN_QSPI1_SSL = 647,\n\tFN_IP0SR3_11_8 = 648,\n\tFN_MMC_SD_D2 = 649,\n\tFN_IP1SR3_11_8 = 650,\n\tFN_MMC_SD_CMD = 651,\n\tFN_IP2SR3_11_8 = 652,\n\tFN_QSPI0_MISO_IO1 = 653,\n\tFN_IP3SR3_11_8 = 654,\n\tFN_QSPI1_IO3 = 655,\n\tFN_IP0SR3_15_12 = 656,\n\tFN_MMC_SD_CLK = 657,\n\tFN_IP1SR3_15_12 = 658,\n\tFN_SD_CD = 659,\n\tFN_IP2SR3_15_12 = 660,\n\tFN_QSPI0_MOSI_IO0 = 661,\n\tFN_IP3SR3_15_12 = 662,\n\tFN_RPC_RESET_N = 663,\n\tFN_IP0SR3_19_16 = 664,\n\tFN_MMC_DS = 665,\n\tFN_IP1SR3_19_16 = 666,\n\tFN_SD_WP = 667,\n\tFN_IP2SR3_19_16 = 668,\n\tFN_QSPI0_SPCLK = 669,\n\tFN_IP3SR3_19_16 = 670,\n\tFN_RPC_WP_N = 671,\n\tFN_IP0SR3_23_20 = 672,\n\tFN_MMC_SD_D3 = 673,\n\tFN_IP1SR3_23_20 = 674,\n\tFN_IPC_CLKIN = 675,\n\tFN_IPC_CLKEN_IN = 676,\n\tFN_PWM1_A = 677,\n\tFN_TCLK3_A = 678,\n\tFN_IP2SR3_23_20 = 679,\n\tFN_QSPI1_MOSI_IO0 = 680,\n\tFN_IP3SR3_23_20 = 681,\n\tFN_RPC_INT_N = 682,\n\tFN_IP0SR3_27_24 = 683,\n\tFN_MMC_D5 = 684,\n\tFN_IP1SR3_27_24 = 685,\n\tFN_IPC_CLKOUT = 686,\n\tFN_IPC_CLKEN_OUT = 687,\n\tFN_ERROROUTC_N_A = 688,\n\tFN_TCLK4_A = 689,\n\tFN_IP2SR3_27_24 = 690,\n\tFN_QSPI1_SPCLK = 691,\n\tFN_IP0SR3_31_28 = 692,\n\tFN_MMC_D4 = 693,\n\tFN_IP1SR3_31_28 = 694,\n\tFN_QSPI0_SSL = 695,\n\tFN_IP2SR3_31_28 = 696,\n\tFN_QSPI1_MISO_IO1 = 697,\n\tFN_IP0SR4_3_0 = 698,\n\tFN_TSN0_MDIO = 699,\n\tFN_IP1SR4_3_0 = 700,\n\tFN_TSN0_AVTP_PPS0 = 701,\n\tFN_IP2SR4_3_0 = 702,\n\tFN_TSN0_RD3 = 703,\n\tFN_IP3SR4_3_0 = 704,\n\tFN_AVS1 = 705,\n\tFN_IP0SR4_7_4 = 706,\n\tFN_TSN0_MDC = 707,\n\tFN_IP1SR4_7_4 = 708,\n\tFN_TSN0_TX_CTL = 709,\n\tFN_IP2SR4_7_4 = 710,\n\tFN_TSN0_RD2 = 711,\n\tFN_IP0SR4_11_8 = 712,\n\tFN_TSN0_AVTP_PPS1 = 713,\n\tFN_IP1SR4_11_8 = 714,\n\tFN_TSN0_RD0 = 715,\n\tFN_IP2SR4_11_8 = 716,\n\tFN_TSN0_TD3 = 717,\n\tFN_IP0SR4_15_12 = 718,\n\tFN_TSN0_PHY_INT = 719,\n\tFN_IP1SR4_15_12 = 720,\n\tFN_TSN0_RXC = 721,\n\tFN_IP2SR4_15_12 = 722,\n\tFN_TSN0_TD2 = 723,\n\tFN_IP0SR4_19_16 = 724,\n\tFN_TSN0_LINK = 725,\n\tFN_IP1SR4_19_16 = 726,\n\tFN_TSN0_TXC = 727,\n\tFN_IP2SR4_19_16 = 728,\n\tFN_TSN0_TXCREFCLK = 729,\n\tFN_IP0SR4_23_20 = 730,\n\tFN_TSN0_AVTP_MATCH = 731,\n\tFN_IP1SR4_23_20 = 732,\n\tFN_TSN0_RD1 = 733,\n\tFN_IP2SR4_23_20 = 734,\n\tFN_PCIE0_CLKREQ_N = 735,\n\tFN_IP0SR4_27_24 = 736,\n\tFN_TSN0_AVTP_CAPTURE = 737,\n\tFN_IP1SR4_27_24 = 738,\n\tFN_TSN0_TD1 = 739,\n\tFN_IP2SR4_27_24 = 740,\n\tFN_PCIE1_CLKREQ_N = 741,\n\tFN_IP0SR4_31_28 = 742,\n\tFN_TSN0_RX_CTL = 743,\n\tFN_IP1SR4_31_28 = 744,\n\tFN_TSN0_TD0 = 745,\n\tFN_IP2SR4_31_28 = 746,\n\tFN_AVS0 = 747,\n\tFN_IP0SR5_3_0 = 748,\n\tFN_AVB2_AVTP_PPS = 749,\n\tFN_IP1SR5_3_0 = 750,\n\tFN_AVB2_TD3 = 751,\n\tFN_IP2SR5_3_0 = 752,\n\tFN_AVB2_TXC = 753,\n\tFN_IP0SR5_7_4 = 754,\n\tFN_AVB2_AVTP_CAPTURE = 755,\n\tFN_IP1SR5_7_4 = 756,\n\tFN_AVB2_RD3 = 757,\n\tFN_IP2SR5_7_4 = 758,\n\tFN_AVB2_RD0 = 759,\n\tFN_IP0SR5_11_8 = 760,\n\tFN_AVB2_AVTP_MATCH = 761,\n\tFN_IP1SR5_11_8 = 762,\n\tFN_AVB2_MDIO = 763,\n\tFN_IP2SR5_11_8 = 764,\n\tFN_AVB2_RXC = 765,\n\tFN_IP0SR5_15_12 = 766,\n\tFN_AVB2_LINK = 767,\n\tFN_IP1SR5_15_12 = 768,\n\tFN_AVB2_TD2 = 769,\n\tFN_IP2SR5_15_12 = 770,\n\tFN_AVB2_TX_CTL = 771,\n\tFN_IP0SR5_19_16 = 772,\n\tFN_AVB2_PHY_INT = 773,\n\tFN_IP1SR5_19_16 = 774,\n\tFN_AVB2_TD1 = 775,\n\tFN_IP2SR5_19_16 = 776,\n\tFN_AVB2_RX_CTL = 777,\n\tFN_IP0SR5_23_20 = 778,\n\tFN_AVB2_MAGIC = 779,\n\tFN_IP1SR5_23_20 = 780,\n\tFN_AVB2_RD2 = 781,\n\tFN_IP0SR5_27_24 = 782,\n\tFN_AVB2_MDC = 783,\n\tFN_IP1SR5_27_24 = 784,\n\tFN_AVB2_RD1 = 785,\n\tFN_IP0SR5_31_28 = 786,\n\tFN_AVB2_TXCREFCLK = 787,\n\tFN_IP1SR5_31_28 = 788,\n\tFN_AVB2_TD0 = 789,\n\tFN_IP0SR6_3_0 = 790,\n\tFN_AVB1_MDIO = 791,\n\tFN_IP1SR6_3_0 = 792,\n\tFN_AVB1_RXC = 793,\n\tFN_IP2SR6_3_0 = 794,\n\tFN_AVB1_TD2 = 795,\n\tFN_IP0SR6_7_4 = 796,\n\tFN_AVB1_MAGIC = 797,\n\tFN_IP1SR6_7_4 = 798,\n\tFN_AVB1_RX_CTL = 799,\n\tFN_IP2SR6_7_4 = 800,\n\tFN_AVB1_RD2 = 801,\n\tFN_IP0SR6_11_8 = 802,\n\tFN_AVB1_MDC = 803,\n\tFN_IP1SR6_11_8 = 804,\n\tFN_AVB1_AVTP_PPS = 805,\n\tFN_IP2SR6_11_8 = 806,\n\tFN_AVB1_TD3 = 807,\n\tFN_IP0SR6_15_12 = 808,\n\tFN_AVB1_PHY_INT = 809,\n\tFN_IP1SR6_15_12 = 810,\n\tFN_AVB1_AVTP_CAPTURE = 811,\n\tFN_IP2SR6_15_12 = 812,\n\tFN_AVB1_RD3 = 813,\n\tFN_IP0SR6_19_16 = 814,\n\tFN_AVB1_LINK = 815,\n\tFN_IP1SR6_19_16 = 816,\n\tFN_AVB1_TD1 = 817,\n\tFN_IP2SR6_19_16 = 818,\n\tFN_AVB1_TXCREFCLK = 819,\n\tFN_IP0SR6_23_20 = 820,\n\tFN_AVB1_AVTP_MATCH = 821,\n\tFN_IP1SR6_23_20 = 822,\n\tFN_AVB1_TD0 = 823,\n\tFN_IP0SR6_27_24 = 824,\n\tFN_AVB1_TXC = 825,\n\tFN_IP1SR6_27_24 = 826,\n\tFN_AVB1_RD1 = 827,\n\tFN_IP0SR6_31_28 = 828,\n\tFN_AVB1_TX_CTL = 829,\n\tFN_IP1SR6_31_28 = 830,\n\tFN_AVB1_RD0 = 831,\n\tFN_IP0SR7_3_0 = 832,\n\tFN_AVB0_AVTP_PPS = 833,\n\tFN_IP1SR7_3_0 = 834,\n\tFN_AVB0_RD3 = 835,\n\tFN_IP2SR7_3_0 = 836,\n\tFN_AVB0_TX_CTL = 837,\n\tFN_IP0SR7_7_4 = 838,\n\tFN_AVB0_AVTP_CAPTURE = 839,\n\tFN_IP1SR7_7_4 = 840,\n\tFN_AVB0_TXCREFCLK = 841,\n\tFN_IP2SR7_7_4 = 842,\n\tFN_AVB0_RD1 = 843,\n\tFN_IP0SR7_11_8 = 844,\n\tFN_AVB0_AVTP_MATCH = 845,\n\tFN_IP1SR7_11_8 = 846,\n\tFN_AVB0_MAGIC = 847,\n\tFN_IP2SR7_11_8 = 848,\n\tFN_AVB0_RD0 = 849,\n\tFN_IP0SR7_15_12 = 850,\n\tFN_AVB0_TD3 = 851,\n\tFN_IP1SR7_15_12 = 852,\n\tFN_AVB0_TD0 = 853,\n\tFN_IP2SR7_15_12 = 854,\n\tFN_AVB0_RXC = 855,\n\tFN_IP0SR7_19_16 = 856,\n\tFN_AVB0_LINK = 857,\n\tFN_IP1SR7_19_16 = 858,\n\tFN_AVB0_RD2 = 859,\n\tFN_IP2SR7_19_16 = 860,\n\tFN_AVB0_RX_CTL = 861,\n\tFN_IP0SR7_23_20 = 862,\n\tFN_AVB0_PHY_INT = 863,\n\tFN_IP1SR7_23_20 = 864,\n\tFN_AVB0_MDC = 865,\n\tFN_IP0SR7_27_24 = 866,\n\tFN_AVB0_TD2 = 867,\n\tFN_IP1SR7_27_24 = 868,\n\tFN_AVB0_MDIO = 869,\n\tFN_IP0SR7_31_28 = 870,\n\tFN_AVB0_TD1 = 871,\n\tFN_IP1SR7_31_28 = 872,\n\tFN_AVB0_TXC = 873,\n\tFN_IP0SR8_3_0 = 874,\n\tFN_SCL0 = 875,\n\tFN_IP1SR8_3_0 = 876,\n\tFN_SCL4 = 877,\n\tFN_HRX2 = 878,\n\tFN_SCK4 = 879,\n\tFN_IP0SR8_7_4 = 880,\n\tFN_SDA0 = 881,\n\tFN_IP1SR8_7_4 = 882,\n\tFN_SDA4 = 883,\n\tFN_HTX2 = 884,\n\tFN_CTS4_N = 885,\n\tFN_IP0SR8_11_8 = 886,\n\tFN_SCL1 = 887,\n\tFN_IP1SR8_11_8 = 888,\n\tFN_SCL5 = 889,\n\tFN_HRTS2_N = 890,\n\tFN_RTS4_N = 891,\n\tFN_IP0SR8_15_12 = 892,\n\tFN_SDA1 = 893,\n\tFN_IP1SR8_15_12 = 894,\n\tFN_SDA5 = 895,\n\tFN_SCIF_CLK2 = 896,\n\tFN_IP0SR8_19_16 = 897,\n\tFN_SCL2 = 898,\n\tFN_IP1SR8_19_16 = 899,\n\tFN_HCTS2_N = 900,\n\tFN_TX4 = 901,\n\tFN_IP0SR8_23_20 = 902,\n\tFN_SDA2 = 903,\n\tFN_IP1SR8_23_20 = 904,\n\tFN_HSCK2 = 905,\n\tFN_RX4 = 906,\n\tFN_IP0SR8_27_24 = 907,\n\tFN_SCL3 = 908,\n\tFN_IP0SR8_31_28 = 909,\n\tFN_SDA3 = 910,\n\tFN_SEL_SDA5_0 = 911,\n\tFN_SEL_SDA5_1 = 912,\n\tFN_SEL_SCL5_0 = 913,\n\tFN_SEL_SCL5_1 = 914,\n\tFN_SEL_SDA4_0 = 915,\n\tFN_SEL_SDA4_1 = 916,\n\tFN_SEL_SCL4_0 = 917,\n\tFN_SEL_SCL4_1 = 918,\n\tFN_SEL_SDA3_0 = 919,\n\tFN_SEL_SDA3_1 = 920,\n\tFN_SEL_SCL3_0 = 921,\n\tFN_SEL_SCL3_1 = 922,\n\tFN_SEL_SDA2_0 = 923,\n\tFN_SEL_SDA2_1 = 924,\n\tFN_SEL_SCL2_0 = 925,\n\tFN_SEL_SCL2_1 = 926,\n\tFN_SEL_SDA1_0 = 927,\n\tFN_SEL_SDA1_1 = 928,\n\tFN_SEL_SCL1_0 = 929,\n\tFN_SEL_SCL1_1 = 930,\n\tFN_SEL_SDA0_0 = 931,\n\tFN_SEL_SDA0_1 = 932,\n\tFN_SEL_SCL0_0 = 933,\n\tFN_SEL_SCL0_1 = 934,\n\tPINMUX_FUNCTION_END = 935,\n\tPINMUX_MARK_BEGIN = 936,\n\tIP0SR0_3_0_MARK = 937,\n\tERROROUTC_N_B_MARK = 938,\n\tTCLK2_B_MARK = 939,\n\tIP1SR0_3_0_MARK = 940,\n\tMSIOF5_SS1_MARK = 941,\n\tIP2SR0_3_0_MARK = 942,\n\tMSIOF2_TXD_MARK = 943,\n\tHCTS1_N_A_MARK = 944,\n\tCTS1_N_A_MARK = 945,\n\tIP0SR0_7_4_MARK = 946,\n\tMSIOF3_SS1_MARK = 947,\n\tIP1SR0_7_4_MARK = 948,\n\tMSIOF5_SYNC_MARK = 949,\n\tIP2SR0_7_4_MARK = 950,\n\tMSIOF2_SCK_MARK = 951,\n\tHRTS1_N_A_MARK = 952,\n\tRTS1_N_A_MARK = 953,\n\tIP0SR0_11_8_MARK = 954,\n\tMSIOF3_SS2_MARK = 955,\n\tIP1SR0_11_8_MARK = 956,\n\tMSIOF5_TXD_MARK = 957,\n\tIP2SR0_11_8_MARK = 958,\n\tMSIOF2_RXD_MARK = 959,\n\tHSCK1_A_MARK = 960,\n\tSCK1_A_MARK = 961,\n\tIP0SR0_15_12_MARK = 962,\n\tIRQ3_A_MARK = 963,\n\tMSIOF3_SCK_MARK = 964,\n\tIP1SR0_15_12_MARK = 965,\n\tMSIOF5_SCK_MARK = 966,\n\tIP0SR0_19_16_MARK = 967,\n\tIRQ2_A_MARK = 968,\n\tMSIOF3_TXD_MARK = 969,\n\tIP1SR0_19_16_MARK = 970,\n\tMSIOF5_RXD_MARK = 971,\n\tIP0SR0_23_20_MARK = 972,\n\tIRQ1_A_MARK = 973,\n\tMSIOF3_RXD_MARK = 974,\n\tIP1SR0_23_20_MARK = 975,\n\tMSIOF2_SS2_MARK = 976,\n\tTCLK1_A_MARK = 977,\n\tIRQ2_B_MARK = 978,\n\tIP0SR0_27_24_MARK = 979,\n\tIRQ0_A_MARK = 980,\n\tMSIOF3_SYNC_MARK = 981,\n\tIP1SR0_27_24_MARK = 982,\n\tMSIOF2_SS1_MARK = 983,\n\tHTX1_A_MARK = 984,\n\tTX1_A_MARK = 985,\n\tIP0SR0_31_28_MARK = 986,\n\tMSIOF5_SS2_MARK = 987,\n\tIP1SR0_31_28_MARK = 988,\n\tMSIOF2_SYNC_MARK = 989,\n\tHRX1_A_MARK = 990,\n\tRX1_A_MARK = 991,\n\tIP0SR1_3_0_MARK = 992,\n\tMSIOF1_SS2_MARK = 993,\n\tHTX3_B_MARK = 994,\n\tTX3_B_MARK = 995,\n\tIP1SR1_3_0_MARK = 996,\n\tMSIOF0_SYNC_MARK = 997,\n\tHCTS1_N_B_MARK = 998,\n\tCTS1_N_B_MARK = 999,\n\tCANFD5_TX_B_MARK = 1000,\n\tIP2SR1_3_0_MARK = 1001,\n\tHRX0_MARK = 1002,\n\tRX0_MARK = 1003,\n\tIP3SR1_3_0_MARK = 1004,\n\tHRX3_A_MARK = 1005,\n\tSCK3_A_MARK = 1006,\n\tMSIOF4_SS2_MARK = 1007,\n\tIP0SR1_7_4_MARK = 1008,\n\tMSIOF1_SS1_MARK = 1009,\n\tHCTS3_N_B_MARK = 1010,\n\tRX3_B_MARK = 1011,\n\tIP1SR1_7_4_MARK = 1012,\n\tMSIOF0_TXD_MARK = 1013,\n\tHRTS1_N_B_MARK = 1014,\n\tRTS1_N_B_MARK = 1015,\n\tCANFD5_RX_B_MARK = 1016,\n\tIP2SR1_7_4_MARK = 1017,\n\tSCIF_CLK_MARK = 1018,\n\tIRQ4_A_MARK = 1019,\n\tIP3SR1_7_4_MARK = 1020,\n\tHSCK3_A_MARK = 1021,\n\tCTS3_N_A_MARK = 1022,\n\tMSIOF4_SCK_MARK = 1023,\n\tTPU0TO0_B_MARK = 1024,\n\tIP0SR1_11_8_MARK = 1025,\n\tMSIOF1_SYNC_MARK = 1026,\n\tHRTS3_N_B_MARK = 1027,\n\tRTS3_N_B_MARK = 1028,\n\tIP1SR1_11_8_MARK = 1029,\n\tMSIOF0_SCK_MARK = 1030,\n\tHSCK1_B_MARK = 1031,\n\tSCK1_B_MARK = 1032,\n\tIP2SR1_11_8_MARK = 1033,\n\tSSI_SCK_MARK = 1034,\n\tTCLK3_B_MARK = 1035,\n\tIP3SR1_11_8_MARK = 1036,\n\tHRTS3_N_A_MARK = 1037,\n\tRTS3_N_A_MARK = 1038,\n\tMSIOF4_TXD_MARK = 1039,\n\tTPU0TO1_B_MARK = 1040,\n\tIP0SR1_15_12_MARK = 1041,\n\tMSIOF1_SCK_MARK = 1042,\n\tHSCK3_B_MARK = 1043,\n\tCTS3_N_B_MARK = 1044,\n\tIP1SR1_15_12_MARK = 1045,\n\tMSIOF0_RXD_MARK = 1046,\n\tIP2SR1_15_12_MARK = 1047,\n\tSSI_WS_MARK = 1048,\n\tTCLK4_B_MARK = 1049,\n\tIP3SR1_15_12_MARK = 1050,\n\tHCTS3_N_A_MARK = 1051,\n\tRX3_A_MARK = 1052,\n\tMSIOF4_RXD_MARK = 1053,\n\tIP0SR1_19_16_MARK = 1054,\n\tMSIOF1_TXD_MARK = 1055,\n\tHRX3_B_MARK = 1056,\n\tSCK3_B_MARK = 1057,\n\tIP1SR1_19_16_MARK = 1058,\n\tHTX0_MARK = 1059,\n\tTX0_MARK = 1060,\n\tIP2SR1_19_16_MARK = 1061,\n\tSSI_SD_MARK = 1062,\n\tIRQ0_B_MARK = 1063,\n\tIP3SR1_19_16_MARK = 1064,\n\tHTX3_A_MARK = 1065,\n\tTX3_A_MARK = 1066,\n\tMSIOF4_SYNC_MARK = 1067,\n\tIP0SR1_23_20_MARK = 1068,\n\tMSIOF1_RXD_MARK = 1069,\n\tIP1SR1_23_20_MARK = 1070,\n\tHCTS0_N_MARK = 1071,\n\tCTS0_N_MARK = 1072,\n\tPWM8_MARK = 1073,\n\tIP2SR1_23_20_MARK = 1074,\n\tAUDIO_CLKOUT_MARK = 1075,\n\tIRQ1_B_MARK = 1076,\n\tIP0SR1_27_24_MARK = 1077,\n\tMSIOF0_SS2_MARK = 1078,\n\tHTX1_B_MARK = 1079,\n\tTX1_B_MARK = 1080,\n\tIP1SR1_27_24_MARK = 1081,\n\tHRTS0_N_MARK = 1082,\n\tRTS0_N_MARK = 1083,\n\tPWM9_MARK = 1084,\n\tIP2SR1_27_24_MARK = 1085,\n\tAUDIO_CLKIN_MARK = 1086,\n\tPWM3_A_MARK = 1087,\n\tIP0SR1_31_28_MARK = 1088,\n\tMSIOF0_SS1_MARK = 1089,\n\tHRX1_B_MARK = 1090,\n\tRX1_B_MARK = 1091,\n\tIP1SR1_31_28_MARK = 1092,\n\tHSCK0_MARK = 1093,\n\tSCK0_MARK = 1094,\n\tPWM0_MARK = 1095,\n\tIP2SR1_31_28_MARK = 1096,\n\tTCLK2_A_MARK = 1097,\n\tMSIOF4_SS1_MARK = 1098,\n\tIRQ3_B_MARK = 1099,\n\tIP0SR2_3_0_MARK = 1100,\n\tFXR_TXDA_MARK = 1101,\n\tCANFD1_TX_MARK = 1102,\n\tTPU0TO2_B_MARK = 1103,\n\tIP1SR2_3_0_MARK = 1104,\n\tTPU0TO0_A_MARK = 1105,\n\tCANFD6_RX_MARK = 1106,\n\tTCLK1_B_MARK = 1107,\n\tIP2SR2_3_0_MARK = 1108,\n\tCANFD4_TX_MARK = 1109,\n\tPWM4_MARK = 1110,\n\tIP0SR2_7_4_MARK = 1111,\n\tFXR_TXENA_N_A_MARK = 1112,\n\tCANFD1_RX_MARK = 1113,\n\tTPU0TO3_B_MARK = 1114,\n\tIP1SR2_7_4_MARK = 1115,\n\tCAN_CLK_MARK = 1116,\n\tFXR_TXENA_N_B_MARK = 1117,\n\tIP2SR2_7_4_MARK = 1118,\n\tCANFD4_RX_MARK = 1119,\n\tPWM5_MARK = 1120,\n\tIP0SR2_11_8_MARK = 1121,\n\tRXDA_EXTFXR_MARK = 1122,\n\tCANFD5_TX_A_MARK = 1123,\n\tIRQ5_MARK = 1124,\n\tIP1SR2_11_8_MARK = 1125,\n\tCANFD0_TX_MARK = 1126,\n\tFXR_TXENB_N_B_MARK = 1127,\n\tIP2SR2_11_8_MARK = 1128,\n\tCANFD7_TX_MARK = 1129,\n\tPWM6_MARK = 1130,\n\tIP0SR2_15_12_MARK = 1131,\n\tCLK_EXTFXR_MARK = 1132,\n\tCANFD5_RX_A_MARK = 1133,\n\tIRQ4_B_MARK = 1134,\n\tIP1SR2_15_12_MARK = 1135,\n\tCANFD0_RX_MARK = 1136,\n\tIP2SR2_15_12_MARK = 1137,\n\tCANFD7_RX_MARK = 1138,\n\tPWM7_MARK = 1139,\n\tIP0SR2_19_16_MARK = 1140,\n\tRXDB_EXTFXR_MARK = 1141,\n\tIP1SR2_19_16_MARK = 1142,\n\tCANFD2_TX_MARK = 1143,\n\tTPU0TO2_A_MARK = 1144,\n\tTCLK3_C_MARK = 1145,\n\tIP0SR2_23_20_MARK = 1146,\n\tFXR_TXENB_N_A_MARK = 1147,\n\tIP1SR2_23_20_MARK = 1148,\n\tCANFD2_RX_MARK = 1149,\n\tTPU0TO3_A_MARK = 1150,\n\tPWM1_B_MARK = 1151,\n\tTCLK4_C_MARK = 1152,\n\tIP0SR2_27_24_MARK = 1153,\n\tFXR_TXDB_MARK = 1154,\n\tIP1SR2_27_24_MARK = 1155,\n\tCANFD3_TX_MARK = 1156,\n\tPWM2_MARK = 1157,\n\tIP0SR2_31_28_MARK = 1158,\n\tTPU0TO1_A_MARK = 1159,\n\tCANFD6_TX_MARK = 1160,\n\tTCLK2_C_MARK = 1161,\n\tIP1SR2_31_28_MARK = 1162,\n\tCANFD3_RX_MARK = 1163,\n\tPWM3_B_MARK = 1164,\n\tIP0SR3_3_0_MARK = 1165,\n\tMMC_SD_D1_MARK = 1166,\n\tIP1SR3_3_0_MARK = 1167,\n\tMMC_D7_MARK = 1168,\n\tIP2SR3_3_0_MARK = 1169,\n\tQSPI0_IO3_MARK = 1170,\n\tIP3SR3_3_0_MARK = 1171,\n\tQSPI1_IO2_MARK = 1172,\n\tIP0SR3_7_4_MARK = 1173,\n\tMMC_SD_D0_MARK = 1174,\n\tIP1SR3_7_4_MARK = 1175,\n\tMMC_D6_MARK = 1176,\n\tIP2SR3_7_4_MARK = 1177,\n\tQSPI0_IO2_MARK = 1178,\n\tIP3SR3_7_4_MARK = 1179,\n\tQSPI1_SSL_MARK = 1180,\n\tIP0SR3_11_8_MARK = 1181,\n\tMMC_SD_D2_MARK = 1182,\n\tIP1SR3_11_8_MARK = 1183,\n\tMMC_SD_CMD_MARK = 1184,\n\tIP2SR3_11_8_MARK = 1185,\n\tQSPI0_MISO_IO1_MARK = 1186,\n\tIP3SR3_11_8_MARK = 1187,\n\tQSPI1_IO3_MARK = 1188,\n\tIP0SR3_15_12_MARK = 1189,\n\tMMC_SD_CLK_MARK = 1190,\n\tIP1SR3_15_12_MARK = 1191,\n\tSD_CD_MARK = 1192,\n\tIP2SR3_15_12_MARK = 1193,\n\tQSPI0_MOSI_IO0_MARK = 1194,\n\tIP3SR3_15_12_MARK = 1195,\n\tRPC_RESET_N_MARK = 1196,\n\tIP0SR3_19_16_MARK = 1197,\n\tMMC_DS_MARK = 1198,\n\tIP1SR3_19_16_MARK = 1199,\n\tSD_WP_MARK = 1200,\n\tIP2SR3_19_16_MARK = 1201,\n\tQSPI0_SPCLK_MARK = 1202,\n\tIP3SR3_19_16_MARK = 1203,\n\tRPC_WP_N_MARK = 1204,\n\tIP0SR3_23_20_MARK = 1205,\n\tMMC_SD_D3_MARK = 1206,\n\tIP1SR3_23_20_MARK = 1207,\n\tIPC_CLKIN_MARK = 1208,\n\tIPC_CLKEN_IN_MARK = 1209,\n\tPWM1_A_MARK = 1210,\n\tTCLK3_A_MARK = 1211,\n\tIP2SR3_23_20_MARK = 1212,\n\tQSPI1_MOSI_IO0_MARK = 1213,\n\tIP3SR3_23_20_MARK = 1214,\n\tRPC_INT_N_MARK = 1215,\n\tIP0SR3_27_24_MARK = 1216,\n\tMMC_D5_MARK = 1217,\n\tIP1SR3_27_24_MARK = 1218,\n\tIPC_CLKOUT_MARK = 1219,\n\tIPC_CLKEN_OUT_MARK = 1220,\n\tERROROUTC_N_A_MARK = 1221,\n\tTCLK4_A_MARK = 1222,\n\tIP2SR3_27_24_MARK = 1223,\n\tQSPI1_SPCLK_MARK = 1224,\n\tIP0SR3_31_28_MARK = 1225,\n\tMMC_D4_MARK = 1226,\n\tIP1SR3_31_28_MARK = 1227,\n\tQSPI0_SSL_MARK = 1228,\n\tIP2SR3_31_28_MARK = 1229,\n\tQSPI1_MISO_IO1_MARK = 1230,\n\tIP0SR4_3_0_MARK = 1231,\n\tTSN0_MDIO_MARK = 1232,\n\tIP1SR4_3_0_MARK = 1233,\n\tTSN0_AVTP_PPS0_MARK = 1234,\n\tIP2SR4_3_0_MARK = 1235,\n\tTSN0_RD3_MARK = 1236,\n\tIP3SR4_3_0_MARK = 1237,\n\tAVS1_MARK = 1238,\n\tIP0SR4_7_4_MARK = 1239,\n\tTSN0_MDC_MARK = 1240,\n\tIP1SR4_7_4_MARK = 1241,\n\tTSN0_TX_CTL_MARK = 1242,\n\tIP2SR4_7_4_MARK = 1243,\n\tTSN0_RD2_MARK = 1244,\n\tIP0SR4_11_8_MARK = 1245,\n\tTSN0_AVTP_PPS1_MARK = 1246,\n\tIP1SR4_11_8_MARK = 1247,\n\tTSN0_RD0_MARK = 1248,\n\tIP2SR4_11_8_MARK = 1249,\n\tTSN0_TD3_MARK = 1250,\n\tIP0SR4_15_12_MARK = 1251,\n\tTSN0_PHY_INT_MARK = 1252,\n\tIP1SR4_15_12_MARK = 1253,\n\tTSN0_RXC_MARK = 1254,\n\tIP2SR4_15_12_MARK = 1255,\n\tTSN0_TD2_MARK = 1256,\n\tIP0SR4_19_16_MARK = 1257,\n\tTSN0_LINK_MARK = 1258,\n\tIP1SR4_19_16_MARK = 1259,\n\tTSN0_TXC_MARK = 1260,\n\tIP2SR4_19_16_MARK = 1261,\n\tTSN0_TXCREFCLK_MARK = 1262,\n\tIP0SR4_23_20_MARK = 1263,\n\tTSN0_AVTP_MATCH_MARK = 1264,\n\tIP1SR4_23_20_MARK = 1265,\n\tTSN0_RD1_MARK = 1266,\n\tIP2SR4_23_20_MARK = 1267,\n\tPCIE0_CLKREQ_N_MARK = 1268,\n\tIP0SR4_27_24_MARK = 1269,\n\tTSN0_AVTP_CAPTURE_MARK = 1270,\n\tIP1SR4_27_24_MARK = 1271,\n\tTSN0_TD1_MARK = 1272,\n\tIP2SR4_27_24_MARK = 1273,\n\tPCIE1_CLKREQ_N_MARK = 1274,\n\tIP0SR4_31_28_MARK = 1275,\n\tTSN0_RX_CTL_MARK = 1276,\n\tIP1SR4_31_28_MARK = 1277,\n\tTSN0_TD0_MARK = 1278,\n\tIP2SR4_31_28_MARK = 1279,\n\tAVS0_MARK = 1280,\n\tIP0SR5_3_0_MARK = 1281,\n\tAVB2_AVTP_PPS_MARK = 1282,\n\tIP1SR5_3_0_MARK = 1283,\n\tAVB2_TD3_MARK = 1284,\n\tIP2SR5_3_0_MARK = 1285,\n\tAVB2_TXC_MARK = 1286,\n\tIP0SR5_7_4_MARK = 1287,\n\tAVB2_AVTP_CAPTURE_MARK = 1288,\n\tIP1SR5_7_4_MARK = 1289,\n\tAVB2_RD3_MARK = 1290,\n\tIP2SR5_7_4_MARK = 1291,\n\tAVB2_RD0_MARK = 1292,\n\tIP0SR5_11_8_MARK = 1293,\n\tAVB2_AVTP_MATCH_MARK = 1294,\n\tIP1SR5_11_8_MARK = 1295,\n\tAVB2_MDIO_MARK = 1296,\n\tIP2SR5_11_8_MARK = 1297,\n\tAVB2_RXC_MARK = 1298,\n\tIP0SR5_15_12_MARK = 1299,\n\tAVB2_LINK_MARK = 1300,\n\tIP1SR5_15_12_MARK = 1301,\n\tAVB2_TD2_MARK = 1302,\n\tIP2SR5_15_12_MARK = 1303,\n\tAVB2_TX_CTL_MARK = 1304,\n\tIP0SR5_19_16_MARK = 1305,\n\tAVB2_PHY_INT_MARK = 1306,\n\tIP1SR5_19_16_MARK = 1307,\n\tAVB2_TD1_MARK = 1308,\n\tIP2SR5_19_16_MARK = 1309,\n\tAVB2_RX_CTL_MARK = 1310,\n\tIP0SR5_23_20_MARK = 1311,\n\tAVB2_MAGIC_MARK = 1312,\n\tIP1SR5_23_20_MARK = 1313,\n\tAVB2_RD2_MARK = 1314,\n\tIP0SR5_27_24_MARK = 1315,\n\tAVB2_MDC_MARK = 1316,\n\tIP1SR5_27_24_MARK = 1317,\n\tAVB2_RD1_MARK = 1318,\n\tIP0SR5_31_28_MARK = 1319,\n\tAVB2_TXCREFCLK_MARK = 1320,\n\tIP1SR5_31_28_MARK = 1321,\n\tAVB2_TD0_MARK = 1322,\n\tIP0SR6_3_0_MARK = 1323,\n\tAVB1_MDIO_MARK = 1324,\n\tIP1SR6_3_0_MARK = 1325,\n\tAVB1_RXC_MARK = 1326,\n\tIP2SR6_3_0_MARK = 1327,\n\tAVB1_TD2_MARK = 1328,\n\tIP0SR6_7_4_MARK = 1329,\n\tAVB1_MAGIC_MARK = 1330,\n\tIP1SR6_7_4_MARK = 1331,\n\tAVB1_RX_CTL_MARK = 1332,\n\tIP2SR6_7_4_MARK = 1333,\n\tAVB1_RD2_MARK = 1334,\n\tIP0SR6_11_8_MARK = 1335,\n\tAVB1_MDC_MARK = 1336,\n\tIP1SR6_11_8_MARK = 1337,\n\tAVB1_AVTP_PPS_MARK = 1338,\n\tIP2SR6_11_8_MARK = 1339,\n\tAVB1_TD3_MARK = 1340,\n\tIP0SR6_15_12_MARK = 1341,\n\tAVB1_PHY_INT_MARK = 1342,\n\tIP1SR6_15_12_MARK = 1343,\n\tAVB1_AVTP_CAPTURE_MARK = 1344,\n\tIP2SR6_15_12_MARK = 1345,\n\tAVB1_RD3_MARK = 1346,\n\tIP0SR6_19_16_MARK = 1347,\n\tAVB1_LINK_MARK = 1348,\n\tIP1SR6_19_16_MARK = 1349,\n\tAVB1_TD1_MARK = 1350,\n\tIP2SR6_19_16_MARK = 1351,\n\tAVB1_TXCREFCLK_MARK = 1352,\n\tIP0SR6_23_20_MARK = 1353,\n\tAVB1_AVTP_MATCH_MARK = 1354,\n\tIP1SR6_23_20_MARK = 1355,\n\tAVB1_TD0_MARK = 1356,\n\tIP0SR6_27_24_MARK = 1357,\n\tAVB1_TXC_MARK = 1358,\n\tIP1SR6_27_24_MARK = 1359,\n\tAVB1_RD1_MARK = 1360,\n\tIP0SR6_31_28_MARK = 1361,\n\tAVB1_TX_CTL_MARK = 1362,\n\tIP1SR6_31_28_MARK = 1363,\n\tAVB1_RD0_MARK = 1364,\n\tIP0SR7_3_0_MARK = 1365,\n\tAVB0_AVTP_PPS_MARK = 1366,\n\tIP1SR7_3_0_MARK = 1367,\n\tAVB0_RD3_MARK = 1368,\n\tIP2SR7_3_0_MARK = 1369,\n\tAVB0_TX_CTL_MARK = 1370,\n\tIP0SR7_7_4_MARK = 1371,\n\tAVB0_AVTP_CAPTURE_MARK = 1372,\n\tIP1SR7_7_4_MARK = 1373,\n\tAVB0_TXCREFCLK_MARK = 1374,\n\tIP2SR7_7_4_MARK = 1375,\n\tAVB0_RD1_MARK = 1376,\n\tIP0SR7_11_8_MARK = 1377,\n\tAVB0_AVTP_MATCH_MARK = 1378,\n\tIP1SR7_11_8_MARK = 1379,\n\tAVB0_MAGIC_MARK = 1380,\n\tIP2SR7_11_8_MARK = 1381,\n\tAVB0_RD0_MARK = 1382,\n\tIP0SR7_15_12_MARK = 1383,\n\tAVB0_TD3_MARK = 1384,\n\tIP1SR7_15_12_MARK = 1385,\n\tAVB0_TD0_MARK = 1386,\n\tIP2SR7_15_12_MARK = 1387,\n\tAVB0_RXC_MARK = 1388,\n\tIP0SR7_19_16_MARK = 1389,\n\tAVB0_LINK_MARK = 1390,\n\tIP1SR7_19_16_MARK = 1391,\n\tAVB0_RD2_MARK = 1392,\n\tIP2SR7_19_16_MARK = 1393,\n\tAVB0_RX_CTL_MARK = 1394,\n\tIP0SR7_23_20_MARK = 1395,\n\tAVB0_PHY_INT_MARK = 1396,\n\tIP1SR7_23_20_MARK = 1397,\n\tAVB0_MDC_MARK = 1398,\n\tIP0SR7_27_24_MARK = 1399,\n\tAVB0_TD2_MARK = 1400,\n\tIP1SR7_27_24_MARK = 1401,\n\tAVB0_MDIO_MARK = 1402,\n\tIP0SR7_31_28_MARK = 1403,\n\tAVB0_TD1_MARK = 1404,\n\tIP1SR7_31_28_MARK = 1405,\n\tAVB0_TXC_MARK = 1406,\n\tIP0SR8_3_0_MARK = 1407,\n\tSCL0_MARK = 1408,\n\tIP1SR8_3_0_MARK = 1409,\n\tSCL4_MARK = 1410,\n\tHRX2_MARK = 1411,\n\tSCK4_MARK = 1412,\n\tIP0SR8_7_4_MARK = 1413,\n\tSDA0_MARK = 1414,\n\tIP1SR8_7_4_MARK = 1415,\n\tSDA4_MARK = 1416,\n\tHTX2_MARK = 1417,\n\tCTS4_N_MARK = 1418,\n\tIP0SR8_11_8_MARK = 1419,\n\tSCL1_MARK = 1420,\n\tIP1SR8_11_8_MARK = 1421,\n\tSCL5_MARK = 1422,\n\tHRTS2_N_MARK = 1423,\n\tRTS4_N_MARK = 1424,\n\tIP0SR8_15_12_MARK = 1425,\n\tSDA1_MARK = 1426,\n\tIP1SR8_15_12_MARK = 1427,\n\tSDA5_MARK = 1428,\n\tSCIF_CLK2_MARK = 1429,\n\tIP0SR8_19_16_MARK = 1430,\n\tSCL2_MARK = 1431,\n\tIP1SR8_19_16_MARK = 1432,\n\tHCTS2_N_MARK = 1433,\n\tTX4_MARK = 1434,\n\tIP0SR8_23_20_MARK = 1435,\n\tSDA2_MARK = 1436,\n\tIP1SR8_23_20_MARK = 1437,\n\tHSCK2_MARK = 1438,\n\tRX4_MARK = 1439,\n\tIP0SR8_27_24_MARK = 1440,\n\tSCL3_MARK = 1441,\n\tIP0SR8_31_28_MARK = 1442,\n\tSDA3_MARK = 1443,\n\tSEL_SDA5_0_MARK = 1444,\n\tSEL_SDA5_1_MARK = 1445,\n\tSEL_SCL5_0_MARK = 1446,\n\tSEL_SCL5_1_MARK = 1447,\n\tSEL_SDA4_0_MARK = 1448,\n\tSEL_SDA4_1_MARK = 1449,\n\tSEL_SCL4_0_MARK = 1450,\n\tSEL_SCL4_1_MARK = 1451,\n\tSEL_SDA3_0_MARK = 1452,\n\tSEL_SDA3_1_MARK = 1453,\n\tSEL_SCL3_0_MARK = 1454,\n\tSEL_SCL3_1_MARK = 1455,\n\tSEL_SDA2_0_MARK = 1456,\n\tSEL_SDA2_1_MARK = 1457,\n\tSEL_SCL2_0_MARK = 1458,\n\tSEL_SCL2_1_MARK = 1459,\n\tSEL_SDA1_0_MARK = 1460,\n\tSEL_SDA1_1_MARK = 1461,\n\tSEL_SCL1_0_MARK = 1462,\n\tSEL_SCL1_1_MARK = 1463,\n\tSEL_SDA0_0_MARK = 1464,\n\tSEL_SDA0_1_MARK = 1465,\n\tSEL_SCL0_0_MARK = 1466,\n\tSEL_SCL0_1_MARK = 1467,\n\tPINMUX_MARK_END = 1468,\n};\n\nenum {\n\tPINMUX_RESERVED___2 = 0,\n\tPINMUX_DATA_BEGIN___2 = 1,\n\tGP_0_0_DATA___2 = 2,\n\tGP_0_1_DATA___2 = 3,\n\tGP_0_2_DATA___2 = 4,\n\tGP_0_3_DATA___2 = 5,\n\tGP_0_4_DATA___2 = 6,\n\tGP_0_5_DATA___2 = 7,\n\tGP_0_6_DATA___2 = 8,\n\tGP_0_7_DATA___2 = 9,\n\tGP_0_8_DATA___2 = 10,\n\tGP_0_9_DATA___2 = 11,\n\tGP_0_10_DATA___2 = 12,\n\tGP_0_11_DATA___2 = 13,\n\tGP_0_12_DATA___2 = 14,\n\tGP_0_13_DATA___2 = 15,\n\tGP_0_14_DATA___2 = 16,\n\tGP_0_15_DATA___2 = 17,\n\tGP_1_0_DATA___2 = 18,\n\tGP_1_1_DATA___2 = 19,\n\tGP_1_2_DATA___2 = 20,\n\tGP_1_3_DATA___2 = 21,\n\tGP_1_4_DATA___2 = 22,\n\tGP_1_5_DATA___2 = 23,\n\tGP_1_6_DATA___2 = 24,\n\tGP_1_7_DATA___2 = 25,\n\tGP_1_8_DATA___2 = 26,\n\tGP_1_9_DATA___2 = 27,\n\tGP_1_10_DATA___2 = 28,\n\tGP_1_11_DATA___2 = 29,\n\tGP_1_12_DATA___2 = 30,\n\tGP_1_13_DATA___2 = 31,\n\tGP_1_14_DATA___2 = 32,\n\tGP_1_15_DATA___2 = 33,\n\tGP_1_16_DATA___2 = 34,\n\tGP_1_17_DATA___2 = 35,\n\tGP_1_18_DATA___2 = 36,\n\tGP_1_19_DATA___2 = 37,\n\tGP_1_20_DATA___2 = 38,\n\tGP_1_21_DATA___2 = 39,\n\tGP_1_22_DATA___2 = 40,\n\tGP_1_23_DATA___2 = 41,\n\tGP_1_24_DATA___2 = 42,\n\tGP_1_25_DATA___2 = 43,\n\tGP_1_26_DATA___2 = 44,\n\tGP_1_27_DATA___2 = 45,\n\tGP_1_28_DATA___2 = 46,\n\tGP_2_0_DATA___2 = 47,\n\tGP_2_1_DATA___2 = 48,\n\tGP_2_2_DATA___2 = 49,\n\tGP_2_3_DATA___2 = 50,\n\tGP_2_4_DATA___2 = 51,\n\tGP_2_5_DATA___2 = 52,\n\tGP_2_6_DATA___2 = 53,\n\tGP_2_7_DATA___2 = 54,\n\tGP_2_8_DATA___2 = 55,\n\tGP_2_9_DATA___2 = 56,\n\tGP_2_10_DATA___2 = 57,\n\tGP_2_11_DATA___2 = 58,\n\tGP_2_12_DATA___2 = 59,\n\tGP_2_13_DATA___2 = 60,\n\tGP_2_14_DATA___2 = 61,\n\tGP_3_0_DATA___2 = 62,\n\tGP_3_1_DATA___2 = 63,\n\tGP_3_2_DATA___2 = 64,\n\tGP_3_3_DATA___2 = 65,\n\tGP_3_4_DATA___2 = 66,\n\tGP_3_5_DATA___2 = 67,\n\tGP_3_6_DATA___2 = 68,\n\tGP_3_7_DATA___2 = 69,\n\tGP_3_8_DATA___2 = 70,\n\tGP_3_9_DATA___2 = 71,\n\tGP_3_10_DATA___2 = 72,\n\tGP_3_11_DATA___2 = 73,\n\tGP_3_12_DATA___2 = 74,\n\tGP_3_13_DATA___2 = 75,\n\tGP_3_14_DATA___2 = 76,\n\tGP_3_15_DATA___2 = 77,\n\tGP_4_0_DATA___2 = 78,\n\tGP_4_1_DATA___2 = 79,\n\tGP_4_2_DATA___2 = 80,\n\tGP_4_3_DATA___2 = 81,\n\tGP_4_4_DATA___2 = 82,\n\tGP_4_5_DATA___2 = 83,\n\tGP_4_6_DATA___2 = 84,\n\tGP_4_7_DATA___2 = 85,\n\tGP_4_8_DATA___2 = 86,\n\tGP_4_9_DATA___2 = 87,\n\tGP_4_10_DATA___2 = 88,\n\tGP_4_11_DATA___2 = 89,\n\tGP_4_12_DATA___2 = 90,\n\tGP_4_13_DATA___2 = 91,\n\tGP_4_14_DATA___2 = 92,\n\tGP_4_15_DATA___2 = 93,\n\tGP_4_16_DATA___2 = 94,\n\tGP_4_17_DATA___2 = 95,\n\tGP_5_0_DATA___2 = 96,\n\tGP_5_1_DATA___2 = 97,\n\tGP_5_2_DATA___2 = 98,\n\tGP_5_3_DATA___2 = 99,\n\tGP_5_4_DATA___2 = 100,\n\tGP_5_5_DATA___2 = 101,\n\tGP_5_6_DATA___2 = 102,\n\tGP_5_7_DATA___2 = 103,\n\tGP_5_8_DATA___2 = 104,\n\tGP_5_9_DATA___2 = 105,\n\tGP_5_10_DATA___2 = 106,\n\tGP_5_11_DATA___2 = 107,\n\tGP_5_12_DATA___2 = 108,\n\tGP_5_13_DATA___2 = 109,\n\tGP_5_14_DATA___2 = 110,\n\tGP_5_15_DATA___2 = 111,\n\tGP_5_16_DATA___2 = 112,\n\tGP_5_17_DATA___2 = 113,\n\tGP_5_18_DATA___2 = 114,\n\tGP_5_19_DATA___2 = 115,\n\tGP_5_20_DATA___2 = 116,\n\tGP_5_21_DATA = 117,\n\tGP_5_22_DATA = 118,\n\tGP_5_23_DATA = 119,\n\tGP_5_24_DATA = 120,\n\tGP_5_25_DATA = 121,\n\tGP_6_0_DATA___2 = 122,\n\tGP_6_1_DATA___2 = 123,\n\tGP_6_2_DATA___2 = 124,\n\tGP_6_3_DATA___2 = 125,\n\tGP_6_4_DATA___2 = 126,\n\tGP_6_5_DATA___2 = 127,\n\tGP_6_6_DATA___2 = 128,\n\tGP_6_7_DATA___2 = 129,\n\tGP_6_8_DATA___2 = 130,\n\tGP_6_9_DATA___2 = 131,\n\tGP_6_10_DATA___2 = 132,\n\tGP_6_11_DATA___2 = 133,\n\tGP_6_12_DATA___2 = 134,\n\tGP_6_13_DATA___2 = 135,\n\tGP_6_14_DATA___2 = 136,\n\tGP_6_15_DATA___2 = 137,\n\tGP_6_16_DATA___2 = 138,\n\tGP_6_17_DATA___2 = 139,\n\tGP_6_18_DATA___2 = 140,\n\tGP_6_19_DATA___2 = 141,\n\tGP_6_20_DATA___2 = 142,\n\tGP_6_21_DATA = 143,\n\tGP_6_22_DATA = 144,\n\tGP_6_23_DATA = 145,\n\tGP_6_24_DATA = 146,\n\tGP_6_25_DATA = 147,\n\tGP_6_26_DATA = 148,\n\tGP_6_27_DATA = 149,\n\tGP_6_28_DATA = 150,\n\tGP_6_29_DATA = 151,\n\tGP_6_30_DATA = 152,\n\tGP_6_31_DATA = 153,\n\tGP_7_0_DATA___2 = 154,\n\tGP_7_1_DATA___2 = 155,\n\tGP_7_2_DATA___2 = 156,\n\tGP_7_3_DATA___2 = 157,\n\tPINMUX_DATA_END___2 = 158,\n\tPINMUX_FUNCTION_BEGIN___2 = 159,\n\tGP_0_0_FN___2 = 160,\n\tGP_0_1_FN___2 = 161,\n\tGP_0_2_FN___2 = 162,\n\tGP_0_3_FN___2 = 163,\n\tGP_0_4_FN___2 = 164,\n\tGP_0_5_FN___2 = 165,\n\tGP_0_6_FN___2 = 166,\n\tGP_0_7_FN___2 = 167,\n\tGP_0_8_FN___2 = 168,\n\tGP_0_9_FN___2 = 169,\n\tGP_0_10_FN___2 = 170,\n\tGP_0_11_FN___2 = 171,\n\tGP_0_12_FN___2 = 172,\n\tGP_0_13_FN___2 = 173,\n\tGP_0_14_FN___2 = 174,\n\tGP_0_15_FN___2 = 175,\n\tGP_1_0_FN___2 = 176,\n\tGP_1_1_FN___2 = 177,\n\tGP_1_2_FN___2 = 178,\n\tGP_1_3_FN___2 = 179,\n\tGP_1_4_FN___2 = 180,\n\tGP_1_5_FN___2 = 181,\n\tGP_1_6_FN___2 = 182,\n\tGP_1_7_FN___2 = 183,\n\tGP_1_8_FN___2 = 184,\n\tGP_1_9_FN___2 = 185,\n\tGP_1_10_FN___2 = 186,\n\tGP_1_11_FN___2 = 187,\n\tGP_1_12_FN___2 = 188,\n\tGP_1_13_FN___2 = 189,\n\tGP_1_14_FN___2 = 190,\n\tGP_1_15_FN___2 = 191,\n\tGP_1_16_FN___2 = 192,\n\tGP_1_17_FN___2 = 193,\n\tGP_1_18_FN___2 = 194,\n\tGP_1_19_FN___2 = 195,\n\tGP_1_20_FN___2 = 196,\n\tGP_1_21_FN___2 = 197,\n\tGP_1_22_FN___2 = 198,\n\tGP_1_23_FN___2 = 199,\n\tGP_1_24_FN___2 = 200,\n\tGP_1_25_FN___2 = 201,\n\tGP_1_26_FN___2 = 202,\n\tGP_1_27_FN___2 = 203,\n\tGP_1_28_FN___2 = 204,\n\tGP_2_0_FN___2 = 205,\n\tGP_2_1_FN___2 = 206,\n\tGP_2_2_FN___2 = 207,\n\tGP_2_3_FN___2 = 208,\n\tGP_2_4_FN___2 = 209,\n\tGP_2_5_FN___2 = 210,\n\tGP_2_6_FN___2 = 211,\n\tGP_2_7_FN___2 = 212,\n\tGP_2_8_FN___2 = 213,\n\tGP_2_9_FN___2 = 214,\n\tGP_2_10_FN___2 = 215,\n\tGP_2_11_FN___2 = 216,\n\tGP_2_12_FN___2 = 217,\n\tGP_2_13_FN___2 = 218,\n\tGP_2_14_FN___2 = 219,\n\tGP_3_0_FN___2 = 220,\n\tGP_3_1_FN___2 = 221,\n\tGP_3_2_FN___2 = 222,\n\tGP_3_3_FN___2 = 223,\n\tGP_3_4_FN___2 = 224,\n\tGP_3_5_FN___2 = 225,\n\tGP_3_6_FN___2 = 226,\n\tGP_3_7_FN___2 = 227,\n\tGP_3_8_FN___2 = 228,\n\tGP_3_9_FN___2 = 229,\n\tGP_3_10_FN___2 = 230,\n\tGP_3_11_FN___2 = 231,\n\tGP_3_12_FN___2 = 232,\n\tGP_3_13_FN___2 = 233,\n\tGP_3_14_FN___2 = 234,\n\tGP_3_15_FN___2 = 235,\n\tGP_4_0_FN___2 = 236,\n\tGP_4_1_FN___2 = 237,\n\tGP_4_2_FN___2 = 238,\n\tGP_4_3_FN___2 = 239,\n\tGP_4_4_FN___2 = 240,\n\tGP_4_5_FN___2 = 241,\n\tGP_4_6_FN___2 = 242,\n\tGP_4_7_FN___2 = 243,\n\tGP_4_8_FN___2 = 244,\n\tGP_4_9_FN___2 = 245,\n\tGP_4_10_FN___2 = 246,\n\tGP_4_11_FN___2 = 247,\n\tGP_4_12_FN___2 = 248,\n\tGP_4_13_FN___2 = 249,\n\tGP_4_14_FN___2 = 250,\n\tGP_4_15_FN___2 = 251,\n\tGP_4_16_FN___2 = 252,\n\tGP_4_17_FN___2 = 253,\n\tGP_5_0_FN___2 = 254,\n\tGP_5_1_FN___2 = 255,\n\tGP_5_2_FN___2 = 256,\n\tGP_5_3_FN___2 = 257,\n\tGP_5_4_FN___2 = 258,\n\tGP_5_5_FN___2 = 259,\n\tGP_5_6_FN___2 = 260,\n\tGP_5_7_FN___2 = 261,\n\tGP_5_8_FN___2 = 262,\n\tGP_5_9_FN___2 = 263,\n\tGP_5_10_FN___2 = 264,\n\tGP_5_11_FN___2 = 265,\n\tGP_5_12_FN___2 = 266,\n\tGP_5_13_FN___2 = 267,\n\tGP_5_14_FN___2 = 268,\n\tGP_5_15_FN___2 = 269,\n\tGP_5_16_FN___2 = 270,\n\tGP_5_17_FN___2 = 271,\n\tGP_5_18_FN___2 = 272,\n\tGP_5_19_FN___2 = 273,\n\tGP_5_20_FN___2 = 274,\n\tGP_5_21_FN = 275,\n\tGP_5_22_FN = 276,\n\tGP_5_23_FN = 277,\n\tGP_5_24_FN = 278,\n\tGP_5_25_FN = 279,\n\tGP_6_0_FN___2 = 280,\n\tGP_6_1_FN___2 = 281,\n\tGP_6_2_FN___2 = 282,\n\tGP_6_3_FN___2 = 283,\n\tGP_6_4_FN___2 = 284,\n\tGP_6_5_FN___2 = 285,\n\tGP_6_6_FN___2 = 286,\n\tGP_6_7_FN___2 = 287,\n\tGP_6_8_FN___2 = 288,\n\tGP_6_9_FN___2 = 289,\n\tGP_6_10_FN___2 = 290,\n\tGP_6_11_FN___2 = 291,\n\tGP_6_12_FN___2 = 292,\n\tGP_6_13_FN___2 = 293,\n\tGP_6_14_FN___2 = 294,\n\tGP_6_15_FN___2 = 295,\n\tGP_6_16_FN___2 = 296,\n\tGP_6_17_FN___2 = 297,\n\tGP_6_18_FN___2 = 298,\n\tGP_6_19_FN___2 = 299,\n\tGP_6_20_FN___2 = 300,\n\tGP_6_21_FN = 301,\n\tGP_6_22_FN = 302,\n\tGP_6_23_FN = 303,\n\tGP_6_24_FN = 304,\n\tGP_6_25_FN = 305,\n\tGP_6_26_FN = 306,\n\tGP_6_27_FN = 307,\n\tGP_6_28_FN = 308,\n\tGP_6_29_FN = 309,\n\tGP_6_30_FN = 310,\n\tGP_6_31_FN = 311,\n\tGP_7_0_FN___2 = 312,\n\tGP_7_1_FN___2 = 313,\n\tGP_7_2_FN___2 = 314,\n\tGP_7_3_FN___2 = 315,\n\tFN_CLKOUT = 316,\n\tFN_MSIOF0_RXD___2 = 317,\n\tFN_MSIOF0_TXD___2 = 318,\n\tFN_MSIOF0_SCK___2 = 319,\n\tFN_SSI_SDATA5 = 320,\n\tFN_SSI_WS5 = 321,\n\tFN_SSI_SCK5 = 322,\n\tFN_GP7_03 = 323,\n\tFN_GP7_02 = 324,\n\tFN_AVS2 = 325,\n\tFN_AVS1___2 = 326,\n\tFN_IP0_3_0 = 327,\n\tFN_AVB_MDC = 328,\n\tFN_MSIOF2_SS2_C = 329,\n\tFN_IP1_3_0 = 330,\n\tFN_IRQ2 = 331,\n\tFN_QCPV_QDE = 332,\n\tFN_DU_EXODDF_DU_ODDF_DISP_CDE = 333,\n\tFN_VI4_DATA2_B = 334,\n\tFN_MSIOF3_SYNC_E = 335,\n\tFN_PWM3_B___2 = 336,\n\tFN_IP2_3_0 = 337,\n\tFN_A1 = 338,\n\tFN_LCDOUT17 = 339,\n\tFN_MSIOF3_TXD_B = 340,\n\tFN_VI4_DATA9 = 341,\n\tFN_DU_DB1 = 342,\n\tFN_PWM4_A = 343,\n\tFN_IP3_3_0 = 344,\n\tFN_A9 = 345,\n\tFN_MSIOF2_SCK_A = 346,\n\tFN_CTS4_N_B = 347,\n\tFN_VI5_VSYNC_N = 348,\n\tFN_IP0_7_4 = 349,\n\tFN_AVB_MAGIC = 350,\n\tFN_MSIOF2_SS1_C = 351,\n\tFN_SCK4_A = 352,\n\tFN_IP1_7_4 = 353,\n\tFN_IRQ3 = 354,\n\tFN_QSTVB_QVE = 355,\n\tFN_DU_DOTCLKOUT1 = 356,\n\tFN_VI4_DATA3_B = 357,\n\tFN_MSIOF3_SCK_E = 358,\n\tFN_PWM4_B = 359,\n\tFN_IP2_7_4 = 360,\n\tFN_A2 = 361,\n\tFN_LCDOUT18 = 362,\n\tFN_MSIOF3_SCK_B = 363,\n\tFN_VI4_DATA10 = 364,\n\tFN_DU_DB2 = 365,\n\tFN_PWM5_A = 366,\n\tFN_IP3_7_4 = 367,\n\tFN_A10 = 368,\n\tFN_MSIOF2_RXD_A = 369,\n\tFN_RTS4_N_B = 370,\n\tFN_VI5_HSYNC_N = 371,\n\tFN_IP0_11_8 = 372,\n\tFN_AVB_PHY_INT = 373,\n\tFN_MSIOF2_SYNC_C = 374,\n\tFN_RX4_A = 375,\n\tFN_IP1_11_8 = 376,\n\tFN_IRQ4 = 377,\n\tFN_QSTH_QHS = 378,\n\tFN_DU_EXHSYNC_DU_HSYNC = 379,\n\tFN_VI4_DATA4_B = 380,\n\tFN_MSIOF3_RXD_E = 381,\n\tFN_PWM5_B = 382,\n\tFN_IP2_11_8 = 383,\n\tFN_A3 = 384,\n\tFN_LCDOUT19 = 385,\n\tFN_MSIOF3_RXD_B = 386,\n\tFN_VI4_DATA11 = 387,\n\tFN_DU_DB3 = 388,\n\tFN_PWM6_A = 389,\n\tFN_IP3_11_8 = 390,\n\tFN_A11 = 391,\n\tFN_TX3_B___2 = 392,\n\tFN_MSIOF2_TXD_A = 393,\n\tFN_HTX4_B = 394,\n\tFN_HSCK4 = 395,\n\tFN_VI5_FIELD = 396,\n\tFN_SCL6_A = 397,\n\tFN_AVB_AVTP_CAPTURE_B = 398,\n\tFN_PWM2_B = 399,\n\tFN_IP0_15_12 = 400,\n\tFN_AVB_LINK = 401,\n\tFN_MSIOF2_SCK_C = 402,\n\tFN_TX4_A = 403,\n\tFN_IP1_15_12 = 404,\n\tFN_IRQ5___2 = 405,\n\tFN_QSTB_QHE = 406,\n\tFN_DU_EXVSYNC_DU_VSYNC = 407,\n\tFN_VI4_DATA5_B = 408,\n\tFN_MSIOF3_TXD_E = 409,\n\tFN_PWM6_B = 410,\n\tFN_IP2_15_12 = 411,\n\tFN_A4 = 412,\n\tFN_LCDOUT20 = 413,\n\tFN_MSIOF3_SS1_B = 414,\n\tFN_VI4_DATA12 = 415,\n\tFN_VI5_DATA12 = 416,\n\tFN_DU_DB4 = 417,\n\tFN_IP3_15_12 = 418,\n\tFN_A12 = 419,\n\tFN_LCDOUT12 = 420,\n\tFN_MSIOF3_SCK_C = 421,\n\tFN_HRX4_A = 422,\n\tFN_VI5_DATA8 = 423,\n\tFN_DU_DG4 = 424,\n\tFN_IP0_19_16 = 425,\n\tFN_AVB_AVTP_MATCH_A = 426,\n\tFN_MSIOF2_RXD_C = 427,\n\tFN_CTS4_N_A = 428,\n\tFN_IP1_19_16 = 429,\n\tFN_PWM0___2 = 430,\n\tFN_AVB_AVTP_PPS = 431,\n\tFN_VI4_DATA6_B = 432,\n\tFN_IECLK_B = 433,\n\tFN_IP2_19_16 = 434,\n\tFN_A5 = 435,\n\tFN_LCDOUT21 = 436,\n\tFN_MSIOF3_SS2_B = 437,\n\tFN_SCK4_B = 438,\n\tFN_VI4_DATA13 = 439,\n\tFN_VI5_DATA13 = 440,\n\tFN_DU_DB5 = 441,\n\tFN_IP3_19_16 = 442,\n\tFN_A13 = 443,\n\tFN_LCDOUT13 = 444,\n\tFN_MSIOF3_SYNC_C = 445,\n\tFN_HTX4_A = 446,\n\tFN_VI5_DATA9 = 447,\n\tFN_DU_DG5 = 448,\n\tFN_IP0_23_20 = 449,\n\tFN_AVB_AVTP_CAPTURE_A = 450,\n\tFN_MSIOF2_TXD_C = 451,\n\tFN_RTS4_N_A = 452,\n\tFN_IP1_23_20 = 453,\n\tFN_PWM1_A___2 = 454,\n\tFN_HRX3_D = 455,\n\tFN_VI4_DATA7_B = 456,\n\tFN_IERX_B = 457,\n\tFN_IP2_23_20 = 458,\n\tFN_A6 = 459,\n\tFN_LCDOUT22 = 460,\n\tFN_MSIOF2_SS1_A = 461,\n\tFN_RX4_B = 462,\n\tFN_VI4_DATA14 = 463,\n\tFN_VI5_DATA14 = 464,\n\tFN_DU_DB6 = 465,\n\tFN_IP3_23_20 = 466,\n\tFN_A14 = 467,\n\tFN_LCDOUT14 = 468,\n\tFN_MSIOF3_RXD_C = 469,\n\tFN_HCTS4_N = 470,\n\tFN_VI5_DATA10 = 471,\n\tFN_DU_DG6 = 472,\n\tFN_IP0_27_24 = 473,\n\tFN_IRQ0 = 474,\n\tFN_QPOLB = 475,\n\tFN_DU_CDE = 476,\n\tFN_VI4_DATA0_B = 477,\n\tFN_CAN0_TX_B = 478,\n\tFN_CANFD0_TX_B = 479,\n\tFN_MSIOF3_SS2_E = 480,\n\tFN_IP1_27_24 = 481,\n\tFN_PWM2_A = 482,\n\tFN_HTX3_D = 483,\n\tFN_IETX_B = 484,\n\tFN_IP2_27_24 = 485,\n\tFN_A7 = 486,\n\tFN_LCDOUT23 = 487,\n\tFN_MSIOF2_SS2_A = 488,\n\tFN_TX4_B = 489,\n\tFN_VI4_DATA15 = 490,\n\tFN_VI5_DATA15 = 491,\n\tFN_DU_DB7 = 492,\n\tFN_IP3_27_24 = 493,\n\tFN_A15 = 494,\n\tFN_LCDOUT15 = 495,\n\tFN_MSIOF3_TXD_C = 496,\n\tFN_HRTS4_N = 497,\n\tFN_VI5_DATA11 = 498,\n\tFN_DU_DG7 = 499,\n\tFN_IP0_31_28 = 500,\n\tFN_IRQ1 = 501,\n\tFN_QPOLA = 502,\n\tFN_DU_DISP = 503,\n\tFN_VI4_DATA1_B = 504,\n\tFN_CAN0_RX_B = 505,\n\tFN_CANFD0_RX_B = 506,\n\tFN_MSIOF3_SS1_E = 507,\n\tFN_IP1_31_28 = 508,\n\tFN_A0 = 509,\n\tFN_LCDOUT16 = 510,\n\tFN_MSIOF3_SYNC_B = 511,\n\tFN_VI4_DATA8 = 512,\n\tFN_DU_DB0 = 513,\n\tFN_PWM3_A___2 = 514,\n\tFN_IP2_31_28 = 515,\n\tFN_A8 = 516,\n\tFN_RX3_B___2 = 517,\n\tFN_MSIOF2_SYNC_A = 518,\n\tFN_HRX4_B = 519,\n\tFN_SDA6_A = 520,\n\tFN_AVB_AVTP_MATCH_B = 521,\n\tFN_PWM1_B___2 = 522,\n\tFN_IP3_31_28 = 523,\n\tFN_A16 = 524,\n\tFN_LCDOUT8 = 525,\n\tFN_VI4_FIELD = 526,\n\tFN_DU_DG0 = 527,\n\tFN_IP4_3_0 = 528,\n\tFN_A17 = 529,\n\tFN_LCDOUT9 = 530,\n\tFN_VI4_VSYNC_N = 531,\n\tFN_DU_DG1 = 532,\n\tFN_IP5_3_0 = 533,\n\tFN_WE0_N = 534,\n\tFN_MSIOF3_TXD_D = 535,\n\tFN_CTS3_N = 536,\n\tFN_HCTS3_N = 537,\n\tFN_SCL6_B = 538,\n\tFN_CAN_CLK___2 = 539,\n\tFN_IECLK_A = 540,\n\tFN_IP6_3_0 = 541,\n\tFN_D5 = 542,\n\tFN_MSIOF2_SYNC_B = 543,\n\tFN_VI4_DATA21 = 544,\n\tFN_VI5_DATA5 = 545,\n\tFN_IP7_3_0 = 546,\n\tFN_D13 = 547,\n\tFN_LCDOUT5 = 548,\n\tFN_MSIOF2_SS2_D = 549,\n\tFN_TX4_C = 550,\n\tFN_VI4_DATA5_A = 551,\n\tFN_DU_DR5 = 552,\n\tFN_IP4_7_4 = 553,\n\tFN_A18 = 554,\n\tFN_LCDOUT10 = 555,\n\tFN_VI4_HSYNC_N = 556,\n\tFN_DU_DG2 = 557,\n\tFN_IP5_7_4 = 558,\n\tFN_WE1_N = 559,\n\tFN_MSIOF3_SS1_D = 560,\n\tFN_RTS3_N = 561,\n\tFN_HRTS3_N = 562,\n\tFN_SDA6_B = 563,\n\tFN_CAN1_RX = 564,\n\tFN_CANFD1_RX___2 = 565,\n\tFN_IERX_A = 566,\n\tFN_IP6_7_4 = 567,\n\tFN_D6 = 568,\n\tFN_MSIOF2_RXD_B = 569,\n\tFN_VI4_DATA22 = 570,\n\tFN_VI5_DATA6 = 571,\n\tFN_IP7_7_4 = 572,\n\tFN_D14 = 573,\n\tFN_LCDOUT6 = 574,\n\tFN_MSIOF3_SS1_A = 575,\n\tFN_HRX3_C = 576,\n\tFN_VI4_DATA6_A = 577,\n\tFN_DU_DR6 = 578,\n\tFN_SCL6_C = 579,\n\tFN_IP4_11_8 = 580,\n\tFN_A19 = 581,\n\tFN_LCDOUT11 = 582,\n\tFN_VI4_CLKENB = 583,\n\tFN_DU_DG3 = 584,\n\tFN_IP5_11_8 = 585,\n\tFN_EX_WAIT0_A = 586,\n\tFN_QCLK = 587,\n\tFN_VI4_CLK = 588,\n\tFN_DU_DOTCLKOUT0 = 589,\n\tFN_IP6_11_8 = 590,\n\tFN_D7 = 591,\n\tFN_MSIOF2_TXD_B = 592,\n\tFN_VI4_DATA23 = 593,\n\tFN_VI5_DATA7 = 594,\n\tFN_IP7_11_8 = 595,\n\tFN_D15 = 596,\n\tFN_LCDOUT7 = 597,\n\tFN_MSIOF3_SS2_A = 598,\n\tFN_HTX3_C = 599,\n\tFN_VI4_DATA7_A = 600,\n\tFN_DU_DR7 = 601,\n\tFN_SDA6_C = 602,\n\tFN_IP4_15_12 = 603,\n\tFN_CS0_N = 604,\n\tFN_VI5_CLKENB = 605,\n\tFN_IP5_15_12 = 606,\n\tFN_D0 = 607,\n\tFN_MSIOF2_SS1_B = 608,\n\tFN_MSIOF3_SCK_A = 609,\n\tFN_VI4_DATA16 = 610,\n\tFN_VI5_DATA0 = 611,\n\tFN_IP6_15_12 = 612,\n\tFN_D8 = 613,\n\tFN_LCDOUT0 = 614,\n\tFN_MSIOF2_SCK_D = 615,\n\tFN_SCK4_C = 616,\n\tFN_VI4_DATA0_A = 617,\n\tFN_DU_DR0 = 618,\n\tFN_IP4_19_16 = 619,\n\tFN_CS1_N = 620,\n\tFN_VI5_CLK = 621,\n\tFN_EX_WAIT0_B = 622,\n\tFN_IP5_19_16 = 623,\n\tFN_D1 = 624,\n\tFN_MSIOF2_SS2_B = 625,\n\tFN_MSIOF3_SYNC_A = 626,\n\tFN_VI4_DATA17 = 627,\n\tFN_VI5_DATA1 = 628,\n\tFN_IP6_19_16 = 629,\n\tFN_D9 = 630,\n\tFN_LCDOUT1 = 631,\n\tFN_MSIOF2_SYNC_D = 632,\n\tFN_VI4_DATA1_A = 633,\n\tFN_DU_DR1 = 634,\n\tFN_IP7_19_16 = 635,\n\tFN_SD0_CLK = 636,\n\tFN_MSIOF1_SCK_E = 637,\n\tFN_STP_OPWM_0_B = 638,\n\tFN_IP4_23_20 = 639,\n\tFN_BS_N = 640,\n\tFN_QSTVA_QVS = 641,\n\tFN_MSIOF3_SCK_D = 642,\n\tFN_SCK3 = 643,\n\tFN_HSCK3 = 644,\n\tFN_CAN1_TX = 645,\n\tFN_CANFD1_TX___2 = 646,\n\tFN_IETX_A = 647,\n\tFN_IP5_23_20 = 648,\n\tFN_D2 = 649,\n\tFN_MSIOF3_RXD_A = 650,\n\tFN_VI4_DATA18 = 651,\n\tFN_VI5_DATA2 = 652,\n\tFN_IP6_23_20 = 653,\n\tFN_D10 = 654,\n\tFN_LCDOUT2 = 655,\n\tFN_MSIOF2_RXD_D = 656,\n\tFN_HRX3_B___2 = 657,\n\tFN_VI4_DATA2_A = 658,\n\tFN_CTS4_N_C = 659,\n\tFN_DU_DR2 = 660,\n\tFN_IP7_23_20 = 661,\n\tFN_SD0_CMD = 662,\n\tFN_MSIOF1_SYNC_E = 663,\n\tFN_STP_IVCXO27_0_B = 664,\n\tFN_IP4_27_24 = 665,\n\tFN_RD_N = 666,\n\tFN_MSIOF3_SYNC_D = 667,\n\tFN_RX3_A___2 = 668,\n\tFN_HRX3_A___2 = 669,\n\tFN_CAN0_TX_A = 670,\n\tFN_CANFD0_TX_A = 671,\n\tFN_IP5_27_24 = 672,\n\tFN_D3 = 673,\n\tFN_MSIOF3_TXD_A = 674,\n\tFN_VI4_DATA19 = 675,\n\tFN_VI5_DATA3 = 676,\n\tFN_IP6_27_24 = 677,\n\tFN_D11 = 678,\n\tFN_LCDOUT3 = 679,\n\tFN_MSIOF2_TXD_D = 680,\n\tFN_HTX3_B___2 = 681,\n\tFN_VI4_DATA3_A = 682,\n\tFN_RTS4_N_C = 683,\n\tFN_DU_DR3 = 684,\n\tFN_IP7_27_24 = 685,\n\tFN_SD0_DAT0 = 686,\n\tFN_MSIOF1_RXD_E = 687,\n\tFN_TS_SCK0_B = 688,\n\tFN_STP_ISCLK_0_B = 689,\n\tFN_IP4_31_28 = 690,\n\tFN_RD_WR_N = 691,\n\tFN_MSIOF3_RXD_D = 692,\n\tFN_TX3_A___2 = 693,\n\tFN_HTX3_A___2 = 694,\n\tFN_CAN0_RX_A = 695,\n\tFN_CANFD0_RX_A = 696,\n\tFN_IP5_31_28 = 697,\n\tFN_D4 = 698,\n\tFN_MSIOF2_SCK_B = 699,\n\tFN_VI4_DATA20 = 700,\n\tFN_VI5_DATA4 = 701,\n\tFN_IP6_31_28 = 702,\n\tFN_D12 = 703,\n\tFN_LCDOUT4 = 704,\n\tFN_MSIOF2_SS1_D = 705,\n\tFN_RX4_C = 706,\n\tFN_VI4_DATA4_A = 707,\n\tFN_DU_DR4 = 708,\n\tFN_IP7_31_28 = 709,\n\tFN_SD0_DAT1 = 710,\n\tFN_MSIOF1_TXD_E = 711,\n\tFN_TS_SPSYNC0_B = 712,\n\tFN_STP_ISSYNC_0_B = 713,\n\tFN_IP8_3_0 = 714,\n\tFN_SD0_DAT2 = 715,\n\tFN_MSIOF1_SS1_E = 716,\n\tFN_TS_SDAT0_B = 717,\n\tFN_STP_ISD_0_B = 718,\n\tFN_IP9_3_0 = 719,\n\tFN_SD2_CLK = 720,\n\tFN_NFDATA8 = 721,\n\tFN_IP10_3_0 = 722,\n\tFN_SD3_CMD = 723,\n\tFN_NFRE_N = 724,\n\tFN_IP11_3_0 = 725,\n\tFN_SD3_DAT7 = 726,\n\tFN_SD3_WP = 727,\n\tFN_NFDATA7 = 728,\n\tFN_IP8_7_4 = 729,\n\tFN_SD0_DAT3 = 730,\n\tFN_MSIOF1_SS2_E = 731,\n\tFN_TS_SDEN0_B = 732,\n\tFN_STP_ISEN_0_B = 733,\n\tFN_IP9_7_4 = 734,\n\tFN_SD2_CMD = 735,\n\tFN_NFDATA9 = 736,\n\tFN_IP10_7_4 = 737,\n\tFN_SD3_DAT0 = 738,\n\tFN_NFDATA0 = 739,\n\tFN_IP11_7_4 = 740,\n\tFN_SD3_DS = 741,\n\tFN_NFCLE = 742,\n\tFN_IP8_11_8 = 743,\n\tFN_SD1_CLK = 744,\n\tFN_MSIOF1_SCK_G = 745,\n\tFN_SIM0_CLK_A = 746,\n\tFN_IP9_11_8 = 747,\n\tFN_SD2_DAT0 = 748,\n\tFN_NFDATA10 = 749,\n\tFN_IP10_11_8 = 750,\n\tFN_SD3_DAT1 = 751,\n\tFN_NFDATA1 = 752,\n\tFN_IP11_11_8 = 753,\n\tFN_SD0_CD = 754,\n\tFN_NFDATA14_A = 755,\n\tFN_SCL2_B = 756,\n\tFN_SIM0_RST_A = 757,\n\tFN_IP8_15_12 = 758,\n\tFN_SD1_CMD = 759,\n\tFN_MSIOF1_SYNC_G = 760,\n\tFN_NFCE_N_B = 761,\n\tFN_SIM0_D_A = 762,\n\tFN_STP_IVCXO27_1_B = 763,\n\tFN_IP9_15_12 = 764,\n\tFN_SD2_DAT1 = 765,\n\tFN_NFDATA11 = 766,\n\tFN_IP10_15_12 = 767,\n\tFN_SD3_DAT2 = 768,\n\tFN_NFDATA2 = 769,\n\tFN_IP11_15_12 = 770,\n\tFN_SD0_WP = 771,\n\tFN_NFDATA15_A = 772,\n\tFN_SDA2_B = 773,\n\tFN_IP8_19_16 = 774,\n\tFN_SD1_DAT0 = 775,\n\tFN_SD2_DAT4 = 776,\n\tFN_MSIOF1_RXD_G = 777,\n\tFN_NFWP_N_B = 778,\n\tFN_TS_SCK1_B = 779,\n\tFN_STP_ISCLK_1_B = 780,\n\tFN_IP9_19_16 = 781,\n\tFN_SD2_DAT2 = 782,\n\tFN_NFDATA12 = 783,\n\tFN_IP10_19_16 = 784,\n\tFN_SD3_DAT3 = 785,\n\tFN_NFDATA3 = 786,\n\tFN_IP11_19_16 = 787,\n\tFN_SD1_CD = 788,\n\tFN_NFRB_N_A = 789,\n\tFN_SIM0_CLK_B = 790,\n\tFN_IP8_23_20 = 791,\n\tFN_SD1_DAT1 = 792,\n\tFN_SD2_DAT5 = 793,\n\tFN_MSIOF1_TXD_G = 794,\n\tFN_NFDATA14_B = 795,\n\tFN_TS_SPSYNC1_B = 796,\n\tFN_STP_ISSYNC_1_B = 797,\n\tFN_IP9_23_20 = 798,\n\tFN_SD2_DAT3 = 799,\n\tFN_NFDATA13 = 800,\n\tFN_IP10_23_20 = 801,\n\tFN_SD3_DAT4 = 802,\n\tFN_SD2_CD_A = 803,\n\tFN_NFDATA4 = 804,\n\tFN_IP11_23_20 = 805,\n\tFN_SD1_WP = 806,\n\tFN_NFCE_N_A = 807,\n\tFN_SIM0_D_B = 808,\n\tFN_IP8_27_24 = 809,\n\tFN_SD1_DAT2 = 810,\n\tFN_SD2_DAT6 = 811,\n\tFN_MSIOF1_SS1_G = 812,\n\tFN_NFDATA15_B = 813,\n\tFN_TS_SDAT1_B = 814,\n\tFN_STP_ISD_1_B = 815,\n\tFN_IP9_27_24 = 816,\n\tFN_SD2_DS = 817,\n\tFN_NFALE = 818,\n\tFN_IP10_27_24 = 819,\n\tFN_SD3_DAT5 = 820,\n\tFN_SD2_WP_A = 821,\n\tFN_NFDATA5 = 822,\n\tFN_IP11_27_24 = 823,\n\tFN_SCK0___2 = 824,\n\tFN_HSCK1_B___2 = 825,\n\tFN_MSIOF1_SS2_B = 826,\n\tFN_AUDIO_CLKC_B = 827,\n\tFN_SDA2_A = 828,\n\tFN_SIM0_RST_B = 829,\n\tFN_STP_OPWM_0_C = 830,\n\tFN_RIF0_CLK_B = 831,\n\tFN_ADICHS2 = 832,\n\tFN_SCK5_B = 833,\n\tFN_IP8_31_28 = 834,\n\tFN_SD1_DAT3 = 835,\n\tFN_SD2_DAT7 = 836,\n\tFN_MSIOF1_SS2_G = 837,\n\tFN_NFRB_N_B = 838,\n\tFN_TS_SDEN1_B = 839,\n\tFN_STP_ISEN_1_B = 840,\n\tFN_IP9_31_28 = 841,\n\tFN_SD3_CLK = 842,\n\tFN_NFWE_N = 843,\n\tFN_IP10_31_28 = 844,\n\tFN_SD3_DAT6 = 845,\n\tFN_SD3_CD = 846,\n\tFN_NFDATA6 = 847,\n\tFN_IP11_31_28 = 848,\n\tFN_RX0___2 = 849,\n\tFN_HRX1_B___2 = 850,\n\tFN_TS_SCK0_C = 851,\n\tFN_STP_ISCLK_0_C = 852,\n\tFN_RIF0_D0_B = 853,\n\tFN_IP12_3_0 = 854,\n\tFN_TX0___2 = 855,\n\tFN_HTX1_B___2 = 856,\n\tFN_TS_SPSYNC0_C = 857,\n\tFN_STP_ISSYNC_0_C = 858,\n\tFN_RIF0_D1_B = 859,\n\tFN_IP13_3_0 = 860,\n\tFN_TX2_A = 861,\n\tFN_SD2_CD_B = 862,\n\tFN_SCL1_A = 863,\n\tFN_FMCLK_A = 864,\n\tFN_RIF1_D1_C = 865,\n\tFN_FSO_CFE_0_N = 866,\n\tFN_IP14_3_0 = 867,\n\tFN_MSIOF0_SS1___2 = 868,\n\tFN_RX5_A = 869,\n\tFN_NFWP_N_A = 870,\n\tFN_AUDIO_CLKA_C = 871,\n\tFN_SSI_SCK2_A = 872,\n\tFN_STP_IVCXO27_0_C = 873,\n\tFN_AUDIO_CLKOUT3_A = 874,\n\tFN_TCLK1_B___2 = 875,\n\tFN_IP15_3_0 = 876,\n\tFN_SSI_SDATA1_A = 877,\n\tFN_IP12_7_4 = 878,\n\tFN_CTS0_N___2 = 879,\n\tFN_HCTS1_N_B___2 = 880,\n\tFN_MSIOF1_SYNC_B = 881,\n\tFN_TS_SPSYNC1_C = 882,\n\tFN_STP_ISSYNC_1_C = 883,\n\tFN_RIF1_SYNC_B = 884,\n\tFN_AUDIO_CLKOUT_C = 885,\n\tFN_ADICS_SAMP = 886,\n\tFN_IP13_7_4 = 887,\n\tFN_RX2_A = 888,\n\tFN_SD2_WP_B = 889,\n\tFN_SDA1_A = 890,\n\tFN_FMIN_A = 891,\n\tFN_RIF1_SYNC_C = 892,\n\tFN_FSO_CFE_1_N = 893,\n\tFN_IP14_7_4 = 894,\n\tFN_MSIOF0_SS2___2 = 895,\n\tFN_TX5_A = 896,\n\tFN_MSIOF1_SS2_D = 897,\n\tFN_AUDIO_CLKC_A = 898,\n\tFN_SSI_WS2_A = 899,\n\tFN_STP_OPWM_0_D = 900,\n\tFN_AUDIO_CLKOUT_D = 901,\n\tFN_SPEEDIN_B = 902,\n\tFN_IP15_7_4 = 903,\n\tFN_SSI_SDATA2_A = 904,\n\tFN_SSI_SCK1_B = 905,\n\tFN_IP12_11_8 = 906,\n\tFN_RTS0_N___2 = 907,\n\tFN_HRTS1_N_B___2 = 908,\n\tFN_MSIOF1_SS1_B = 909,\n\tFN_AUDIO_CLKA_B = 910,\n\tFN_SCL2_A = 911,\n\tFN_STP_IVCXO27_1_C = 912,\n\tFN_RIF0_SYNC_B = 913,\n\tFN_ADICHS1 = 914,\n\tFN_IP13_11_8 = 915,\n\tFN_HSCK0___2 = 916,\n\tFN_MSIOF1_SCK_D = 917,\n\tFN_AUDIO_CLKB_A = 918,\n\tFN_SSI_SDATA1_B = 919,\n\tFN_TS_SCK0_D = 920,\n\tFN_STP_ISCLK_0_D = 921,\n\tFN_RIF0_CLK_C = 922,\n\tFN_RX5_B = 923,\n\tFN_IP14_11_8 = 924,\n\tFN_MLB_CLK = 925,\n\tFN_MSIOF1_SCK_F = 926,\n\tFN_SCL1_B = 927,\n\tFN_IP15_11_8 = 928,\n\tFN_SSI_SCK349 = 929,\n\tFN_MSIOF1_SS1_A = 930,\n\tFN_STP_OPWM_0_A = 931,\n\tFN_IP12_15_12 = 932,\n\tFN_RX1_A___2 = 933,\n\tFN_HRX1_A___2 = 934,\n\tFN_TS_SDAT0_C = 935,\n\tFN_STP_ISD_0_C = 936,\n\tFN_RIF1_CLK_C = 937,\n\tFN_IP13_15_12 = 938,\n\tFN_HRX0___2 = 939,\n\tFN_MSIOF1_RXD_D = 940,\n\tFN_SSI_SDATA2_B = 941,\n\tFN_TS_SDEN0_D = 942,\n\tFN_STP_ISEN_0_D = 943,\n\tFN_RIF0_D0_C = 944,\n\tFN_IP14_15_12 = 945,\n\tFN_MLB_SIG = 946,\n\tFN_RX1_B___2 = 947,\n\tFN_MSIOF1_SYNC_F = 948,\n\tFN_SDA1_B = 949,\n\tFN_IP15_15_12 = 950,\n\tFN_SSI_WS349 = 951,\n\tFN_HCTS2_N_A = 952,\n\tFN_MSIOF1_SS2_A = 953,\n\tFN_STP_IVCXO27_0_A = 954,\n\tFN_IP12_19_16 = 955,\n\tFN_TX1_A___2 = 956,\n\tFN_HTX1_A___2 = 957,\n\tFN_TS_SDEN0_C = 958,\n\tFN_STP_ISEN_0_C = 959,\n\tFN_RIF1_D0_C = 960,\n\tFN_IP13_19_16 = 961,\n\tFN_HTX0___2 = 962,\n\tFN_MSIOF1_TXD_D = 963,\n\tFN_SSI_SDATA9_B = 964,\n\tFN_TS_SDAT0_D = 965,\n\tFN_STP_ISD_0_D = 966,\n\tFN_RIF0_D1_C = 967,\n\tFN_IP14_19_16 = 968,\n\tFN_MLB_DAT = 969,\n\tFN_TX1_B___2 = 970,\n\tFN_MSIOF1_RXD_F = 971,\n\tFN_IP15_19_16 = 972,\n\tFN_SSI_SDATA3 = 973,\n\tFN_HRTS2_N_A = 974,\n\tFN_MSIOF1_TXD_A = 975,\n\tFN_TS_SCK0_A = 976,\n\tFN_STP_ISCLK_0_A = 977,\n\tFN_RIF0_D1_A = 978,\n\tFN_RIF2_D0_A = 979,\n\tFN_IP12_23_20 = 980,\n\tFN_CTS1_N = 981,\n\tFN_HCTS1_N_A___2 = 982,\n\tFN_MSIOF1_RXD_B = 983,\n\tFN_TS_SDEN1_C = 984,\n\tFN_STP_ISEN_1_C = 985,\n\tFN_RIF1_D0_B = 986,\n\tFN_ADIDATA = 987,\n\tFN_IP13_23_20 = 988,\n\tFN_HCTS0_N___2 = 989,\n\tFN_RX2_B = 990,\n\tFN_MSIOF1_SYNC_D = 991,\n\tFN_SSI_SCK9_A = 992,\n\tFN_TS_SPSYNC0_D = 993,\n\tFN_STP_ISSYNC_0_D = 994,\n\tFN_RIF0_SYNC_C = 995,\n\tFN_AUDIO_CLKOUT1_A = 996,\n\tFN_IP14_23_20 = 997,\n\tFN_SSI_SCK01239 = 998,\n\tFN_MSIOF1_TXD_F = 999,\n\tFN_IP15_23_20 = 1000,\n\tFN_SSI_SCK4 = 1001,\n\tFN_HRX2_A = 1002,\n\tFN_MSIOF1_SCK_A = 1003,\n\tFN_TS_SDAT0_A = 1004,\n\tFN_STP_ISD_0_A = 1005,\n\tFN_RIF0_CLK_A = 1006,\n\tFN_RIF2_CLK_A = 1007,\n\tFN_IP12_27_24 = 1008,\n\tFN_RTS1_N = 1009,\n\tFN_HRTS1_N_A___2 = 1010,\n\tFN_MSIOF1_TXD_B = 1011,\n\tFN_TS_SDAT1_C = 1012,\n\tFN_STP_ISD_1_C = 1013,\n\tFN_RIF1_D1_B = 1014,\n\tFN_ADICHS0 = 1015,\n\tFN_IP13_27_24 = 1016,\n\tFN_HRTS0_N___2 = 1017,\n\tFN_TX2_B = 1018,\n\tFN_MSIOF1_SS1_D = 1019,\n\tFN_SSI_WS9_A = 1020,\n\tFN_STP_IVCXO27_0_D = 1021,\n\tFN_BPFCLK_A = 1022,\n\tFN_AUDIO_CLKOUT2_A = 1023,\n\tFN_IP14_27_24 = 1024,\n\tFN_SSI_WS01239 = 1025,\n\tFN_MSIOF1_SS1_F = 1026,\n\tFN_IP15_27_24 = 1027,\n\tFN_SSI_WS4 = 1028,\n\tFN_HTX2_A = 1029,\n\tFN_MSIOF1_SYNC_A = 1030,\n\tFN_TS_SDEN0_A = 1031,\n\tFN_STP_ISEN_0_A = 1032,\n\tFN_RIF0_SYNC_A = 1033,\n\tFN_RIF2_SYNC_A = 1034,\n\tFN_IP12_31_28 = 1035,\n\tFN_SCK2 = 1036,\n\tFN_SCIF_CLK_B = 1037,\n\tFN_MSIOF1_SCK_B = 1038,\n\tFN_TS_SCK1_C = 1039,\n\tFN_STP_ISCLK_1_C = 1040,\n\tFN_RIF1_CLK_B = 1041,\n\tFN_ADICLK = 1042,\n\tFN_IP13_31_28 = 1043,\n\tFN_MSIOF0_SYNC___2 = 1044,\n\tFN_AUDIO_CLKOUT_A = 1045,\n\tFN_TX5_B = 1046,\n\tFN_BPFCLK_D = 1047,\n\tFN_IP14_31_28 = 1048,\n\tFN_SSI_SDATA0 = 1049,\n\tFN_MSIOF1_SS2_F = 1050,\n\tFN_IP15_31_28 = 1051,\n\tFN_SSI_SDATA4 = 1052,\n\tFN_HSCK2_A = 1053,\n\tFN_MSIOF1_RXD_A = 1054,\n\tFN_TS_SPSYNC0_A = 1055,\n\tFN_STP_ISSYNC_0_A = 1056,\n\tFN_RIF0_D0_A = 1057,\n\tFN_RIF2_D1_A = 1058,\n\tFN_IP16_3_0 = 1059,\n\tFN_SSI_SCK6 = 1060,\n\tFN_SIM0_RST_D = 1061,\n\tFN_IP17_3_0 = 1062,\n\tFN_AUDIO_CLKA_A = 1063,\n\tFN_IP18_3_0 = 1064,\n\tFN_GP6_30 = 1065,\n\tFN_AUDIO_CLKOUT2_B = 1066,\n\tFN_SSI_SCK9_B = 1067,\n\tFN_TS_SDEN0_E = 1068,\n\tFN_STP_ISEN_0_E = 1069,\n\tFN_RIF2_D0_B = 1070,\n\tFN_TPU0TO2 = 1071,\n\tFN_FMCLK_C = 1072,\n\tFN_FMCLK_D = 1073,\n\tFN_IP16_7_4 = 1074,\n\tFN_SSI_WS6 = 1075,\n\tFN_SIM0_D_D = 1076,\n\tFN_IP17_7_4 = 1077,\n\tFN_AUDIO_CLKB_B = 1078,\n\tFN_SCIF_CLK_A = 1079,\n\tFN_STP_IVCXO27_1_D = 1080,\n\tFN_REMOCON_A = 1081,\n\tFN_TCLK1_A___2 = 1082,\n\tFN_IP18_7_4 = 1083,\n\tFN_GP6_31 = 1084,\n\tFN_AUDIO_CLKOUT3_B = 1085,\n\tFN_SSI_WS9_B = 1086,\n\tFN_TS_SPSYNC0_E = 1087,\n\tFN_STP_ISSYNC_0_E = 1088,\n\tFN_RIF2_D1_B = 1089,\n\tFN_TPU0TO3 = 1090,\n\tFN_FMIN_C = 1091,\n\tFN_FMIN_D = 1092,\n\tFN_IP16_11_8 = 1093,\n\tFN_SSI_SDATA6 = 1094,\n\tFN_SIM0_CLK_D = 1095,\n\tFN_IP17_11_8 = 1096,\n\tFN_USB0_PWEN = 1097,\n\tFN_SIM0_RST_C = 1098,\n\tFN_TS_SCK1_D = 1099,\n\tFN_STP_ISCLK_1_D = 1100,\n\tFN_BPFCLK_B = 1101,\n\tFN_RIF3_CLK_B = 1102,\n\tFN_HSCK2_C = 1103,\n\tFN_IP16_15_12 = 1104,\n\tFN_SSI_SCK78 = 1105,\n\tFN_HRX2_B = 1106,\n\tFN_MSIOF1_SCK_C = 1107,\n\tFN_TS_SCK1_A = 1108,\n\tFN_STP_ISCLK_1_A = 1109,\n\tFN_RIF1_CLK_A = 1110,\n\tFN_RIF3_CLK_A = 1111,\n\tFN_IP17_15_12 = 1112,\n\tFN_USB0_OVC = 1113,\n\tFN_SIM0_D_C = 1114,\n\tFN_TS_SDAT1_D = 1115,\n\tFN_STP_ISD_1_D = 1116,\n\tFN_RIF3_SYNC_B = 1117,\n\tFN_HRX2_C = 1118,\n\tFN_IP16_19_16 = 1119,\n\tFN_SSI_WS78 = 1120,\n\tFN_HTX2_B = 1121,\n\tFN_MSIOF1_SYNC_C = 1122,\n\tFN_TS_SDAT1_A = 1123,\n\tFN_STP_ISD_1_A = 1124,\n\tFN_RIF1_SYNC_A = 1125,\n\tFN_RIF3_SYNC_A = 1126,\n\tFN_IP17_19_16 = 1127,\n\tFN_USB1_PWEN = 1128,\n\tFN_SIM0_CLK_C = 1129,\n\tFN_SSI_SCK1_A = 1130,\n\tFN_TS_SCK0_E = 1131,\n\tFN_STP_ISCLK_0_E = 1132,\n\tFN_FMCLK_B = 1133,\n\tFN_RIF2_CLK_B = 1134,\n\tFN_SPEEDIN_A = 1135,\n\tFN_HTX2_C = 1136,\n\tFN_IP16_23_20 = 1137,\n\tFN_SSI_SDATA7 = 1138,\n\tFN_HCTS2_N_B = 1139,\n\tFN_MSIOF1_RXD_C = 1140,\n\tFN_TS_SDEN1_A = 1141,\n\tFN_STP_ISEN_1_A = 1142,\n\tFN_RIF1_D0_A = 1143,\n\tFN_RIF3_D0_A = 1144,\n\tFN_TCLK2_A___2 = 1145,\n\tFN_IP17_23_20 = 1146,\n\tFN_USB1_OVC = 1147,\n\tFN_MSIOF1_SS2_C = 1148,\n\tFN_SSI_WS1_A = 1149,\n\tFN_TS_SDAT0_E = 1150,\n\tFN_STP_ISD_0_E = 1151,\n\tFN_FMIN_B = 1152,\n\tFN_RIF2_SYNC_B = 1153,\n\tFN_REMOCON_B = 1154,\n\tFN_HCTS2_N_C = 1155,\n\tFN_IP16_27_24 = 1156,\n\tFN_SSI_SDATA8 = 1157,\n\tFN_HRTS2_N_B = 1158,\n\tFN_MSIOF1_TXD_C = 1159,\n\tFN_TS_SPSYNC1_A = 1160,\n\tFN_STP_ISSYNC_1_A = 1161,\n\tFN_RIF1_D1_A = 1162,\n\tFN_RIF3_D1_A = 1163,\n\tFN_IP17_27_24 = 1164,\n\tFN_USB30_PWEN = 1165,\n\tFN_AUDIO_CLKOUT_B = 1166,\n\tFN_SSI_SCK2_B = 1167,\n\tFN_TS_SDEN1_D = 1168,\n\tFN_STP_ISEN_1_D = 1169,\n\tFN_STP_OPWM_0_E = 1170,\n\tFN_RIF3_D0_B = 1171,\n\tFN_TCLK2_B___2 = 1172,\n\tFN_TPU0TO0 = 1173,\n\tFN_BPFCLK_C = 1174,\n\tFN_HRTS2_N_C = 1175,\n\tFN_IP16_31_28 = 1176,\n\tFN_SSI_SDATA9_A = 1177,\n\tFN_HSCK2_B = 1178,\n\tFN_MSIOF1_SS1_C = 1179,\n\tFN_HSCK1_A___2 = 1180,\n\tFN_SSI_WS1_B = 1181,\n\tFN_SCK1 = 1182,\n\tFN_STP_IVCXO27_1_A = 1183,\n\tFN_SCK5_A = 1184,\n\tFN_IP17_31_28 = 1185,\n\tFN_USB30_OVC = 1186,\n\tFN_AUDIO_CLKOUT1_B = 1187,\n\tFN_SSI_WS2_B = 1188,\n\tFN_TS_SPSYNC1_D = 1189,\n\tFN_STP_ISSYNC_1_D = 1190,\n\tFN_STP_IVCXO27_0_E = 1191,\n\tFN_RIF3_D1_B = 1192,\n\tFN_FSO_TOE_N = 1193,\n\tFN_TPU0TO1 = 1194,\n\tFN_SEL_MSIOF3_0 = 1195,\n\tFN_SEL_MSIOF3_1 = 1196,\n\tFN_SEL_MSIOF3_2 = 1197,\n\tFN_SEL_MSIOF3_3 = 1198,\n\tFN_SEL_MSIOF3_4 = 1199,\n\tFN_SEL_TSIF1_0 = 1200,\n\tFN_SEL_TSIF1_1 = 1201,\n\tFN_SEL_TSIF1_2 = 1202,\n\tFN_SEL_TSIF1_3 = 1203,\n\tFN_I2C_SEL_5_0 = 1204,\n\tFN_I2C_SEL_5_1 = 1205,\n\tFN_I2C_SEL_3_0 = 1206,\n\tFN_I2C_SEL_3_1 = 1207,\n\tFN_SEL_TSIF0_0 = 1208,\n\tFN_SEL_TSIF0_1 = 1209,\n\tFN_SEL_TSIF0_2 = 1210,\n\tFN_SEL_TSIF0_3 = 1211,\n\tFN_SEL_TSIF0_4 = 1212,\n\tFN_I2C_SEL_0_0 = 1213,\n\tFN_I2C_SEL_0_1 = 1214,\n\tFN_SEL_MSIOF2_0 = 1215,\n\tFN_SEL_MSIOF2_1 = 1216,\n\tFN_SEL_MSIOF2_2 = 1217,\n\tFN_SEL_MSIOF2_3 = 1218,\n\tFN_SEL_FM_0 = 1219,\n\tFN_SEL_FM_1 = 1220,\n\tFN_SEL_FM_2 = 1221,\n\tFN_SEL_FM_3 = 1222,\n\tFN_SEL_MSIOF1_0 = 1223,\n\tFN_SEL_MSIOF1_1 = 1224,\n\tFN_SEL_MSIOF1_2 = 1225,\n\tFN_SEL_MSIOF1_3 = 1226,\n\tFN_SEL_MSIOF1_4 = 1227,\n\tFN_SEL_MSIOF1_5 = 1228,\n\tFN_SEL_MSIOF1_6 = 1229,\n\tFN_SEL_TIMER_TMU_0 = 1230,\n\tFN_SEL_TIMER_TMU_1 = 1231,\n\tFN_SEL_SCIF5_0 = 1232,\n\tFN_SEL_SCIF5_1 = 1233,\n\tFN_SEL_SSP1_1_0 = 1234,\n\tFN_SEL_SSP1_1_1 = 1235,\n\tFN_SEL_SSP1_1_2 = 1236,\n\tFN_SEL_SSP1_1_3 = 1237,\n\tFN_SEL_I2C6_0 = 1238,\n\tFN_SEL_I2C6_1 = 1239,\n\tFN_SEL_I2C6_2 = 1240,\n\tFN_SEL_LBSC_0 = 1241,\n\tFN_SEL_LBSC_1 = 1242,\n\tFN_SEL_SSP1_0_0 = 1243,\n\tFN_SEL_SSP1_0_1 = 1244,\n\tFN_SEL_SSP1_0_2 = 1245,\n\tFN_SEL_SSP1_0_3 = 1246,\n\tFN_SEL_SSP1_0_4 = 1247,\n\tFN_SEL_IEBUS_0 = 1248,\n\tFN_SEL_IEBUS_1 = 1249,\n\tFN_SEL_NDF_0 = 1250,\n\tFN_SEL_NDF_1 = 1251,\n\tFN_SEL_I2C2_0 = 1252,\n\tFN_SEL_I2C2_1 = 1253,\n\tFN_SEL_SSI2_0 = 1254,\n\tFN_SEL_SSI2_1 = 1255,\n\tFN_SEL_I2C1_0 = 1256,\n\tFN_SEL_I2C1_1 = 1257,\n\tFN_SEL_SSI1_0 = 1258,\n\tFN_SEL_SSI1_1 = 1259,\n\tFN_SEL_SSI9_0 = 1260,\n\tFN_SEL_SSI9_1 = 1261,\n\tFN_SEL_HSCIF4_0 = 1262,\n\tFN_SEL_HSCIF4_1 = 1263,\n\tFN_SEL_SPEED_PULSE_0 = 1264,\n\tFN_SEL_SPEED_PULSE_1 = 1265,\n\tFN_SEL_TIMER_TMU2_0 = 1266,\n\tFN_SEL_TIMER_TMU2_1 = 1267,\n\tFN_SEL_HSCIF3_0 = 1268,\n\tFN_SEL_HSCIF3_1 = 1269,\n\tFN_SEL_HSCIF3_2 = 1270,\n\tFN_SEL_HSCIF3_3 = 1271,\n\tFN_SEL_SIMCARD_0 = 1272,\n\tFN_SEL_SIMCARD_1 = 1273,\n\tFN_SEL_SIMCARD_2 = 1274,\n\tFN_SEL_SIMCARD_3 = 1275,\n\tFN_SEL_ADGB_0 = 1276,\n\tFN_SEL_ADGB_1 = 1277,\n\tFN_SEL_ADGC_0 = 1278,\n\tFN_SEL_ADGC_1 = 1279,\n\tFN_SEL_HSCIF1_0 = 1280,\n\tFN_SEL_HSCIF1_1 = 1281,\n\tFN_SEL_SDHI2_0 = 1282,\n\tFN_SEL_SDHI2_1 = 1283,\n\tFN_SEL_SCIF4_0 = 1284,\n\tFN_SEL_SCIF4_1 = 1285,\n\tFN_SEL_SCIF4_2 = 1286,\n\tFN_SEL_HSCIF2_0 = 1287,\n\tFN_SEL_HSCIF2_1 = 1288,\n\tFN_SEL_HSCIF2_2 = 1289,\n\tFN_SEL_SCIF3_0 = 1290,\n\tFN_SEL_SCIF3_1 = 1291,\n\tFN_SEL_ETHERAVB_0 = 1292,\n\tFN_SEL_ETHERAVB_1 = 1293,\n\tFN_SEL_SCIF2_0 = 1294,\n\tFN_SEL_SCIF2_1 = 1295,\n\tFN_SEL_DRIF3_0 = 1296,\n\tFN_SEL_DRIF3_1 = 1297,\n\tFN_SEL_SCIF1_0 = 1298,\n\tFN_SEL_SCIF1_1 = 1299,\n\tFN_SEL_DRIF2_0 = 1300,\n\tFN_SEL_DRIF2_1 = 1301,\n\tFN_SEL_SCIF_0 = 1302,\n\tFN_SEL_SCIF_1 = 1303,\n\tFN_SEL_DRIF1_0 = 1304,\n\tFN_SEL_DRIF1_1 = 1305,\n\tFN_SEL_DRIF1_2 = 1306,\n\tFN_SEL_REMOCON_0 = 1307,\n\tFN_SEL_REMOCON_1 = 1308,\n\tFN_SEL_DRIF0_0 = 1309,\n\tFN_SEL_DRIF0_1 = 1310,\n\tFN_SEL_DRIF0_2 = 1311,\n\tFN_SEL_RCAN0_0 = 1312,\n\tFN_SEL_RCAN0_1 = 1313,\n\tFN_SEL_CANFD0_0 = 1314,\n\tFN_SEL_CANFD0_1 = 1315,\n\tFN_SEL_PWM6_0 = 1316,\n\tFN_SEL_PWM6_1 = 1317,\n\tFN_SEL_ADGA_0 = 1318,\n\tFN_SEL_ADGA_1 = 1319,\n\tFN_SEL_ADGA_2 = 1320,\n\tFN_SEL_ADGA_3 = 1321,\n\tFN_SEL_PWM5_0 = 1322,\n\tFN_SEL_PWM5_1 = 1323,\n\tFN_SEL_PWM4_0 = 1324,\n\tFN_SEL_PWM4_1 = 1325,\n\tFN_SEL_PWM3_0 = 1326,\n\tFN_SEL_PWM3_1 = 1327,\n\tFN_SEL_PWM2_0 = 1328,\n\tFN_SEL_PWM2_1 = 1329,\n\tFN_SEL_PWM1_0 = 1330,\n\tFN_SEL_PWM1_1 = 1331,\n\tFN_SEL_VIN4_0 = 1332,\n\tFN_SEL_VIN4_1 = 1333,\n\tPINMUX_FUNCTION_END___2 = 1334,\n\tPINMUX_MARK_BEGIN___2 = 1335,\n\tCLKOUT_MARK = 1336,\n\tMSIOF0_RXD_MARK___2 = 1337,\n\tMSIOF0_TXD_MARK___2 = 1338,\n\tMSIOF0_SCK_MARK___2 = 1339,\n\tSSI_SDATA5_MARK = 1340,\n\tSSI_WS5_MARK = 1341,\n\tSSI_SCK5_MARK = 1342,\n\tGP7_03_MARK = 1343,\n\tGP7_02_MARK = 1344,\n\tAVS2_MARK = 1345,\n\tAVS1_MARK___2 = 1346,\n\tIP0_3_0_MARK = 1347,\n\tAVB_MDC_MARK = 1348,\n\tMSIOF2_SS2_C_MARK = 1349,\n\tIP1_3_0_MARK = 1350,\n\tIRQ2_MARK = 1351,\n\tQCPV_QDE_MARK = 1352,\n\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK = 1353,\n\tVI4_DATA2_B_MARK = 1354,\n\tMSIOF3_SYNC_E_MARK = 1355,\n\tPWM3_B_MARK___2 = 1356,\n\tIP2_3_0_MARK = 1357,\n\tA1_MARK = 1358,\n\tLCDOUT17_MARK = 1359,\n\tMSIOF3_TXD_B_MARK = 1360,\n\tVI4_DATA9_MARK = 1361,\n\tDU_DB1_MARK = 1362,\n\tPWM4_A_MARK = 1363,\n\tIP3_3_0_MARK = 1364,\n\tA9_MARK = 1365,\n\tMSIOF2_SCK_A_MARK = 1366,\n\tCTS4_N_B_MARK = 1367,\n\tVI5_VSYNC_N_MARK = 1368,\n\tIP0_7_4_MARK = 1369,\n\tAVB_MAGIC_MARK = 1370,\n\tMSIOF2_SS1_C_MARK = 1371,\n\tSCK4_A_MARK = 1372,\n\tIP1_7_4_MARK = 1373,\n\tIRQ3_MARK = 1374,\n\tQSTVB_QVE_MARK = 1375,\n\tDU_DOTCLKOUT1_MARK = 1376,\n\tVI4_DATA3_B_MARK = 1377,\n\tMSIOF3_SCK_E_MARK = 1378,\n\tPWM4_B_MARK = 1379,\n\tIP2_7_4_MARK = 1380,\n\tA2_MARK = 1381,\n\tLCDOUT18_MARK = 1382,\n\tMSIOF3_SCK_B_MARK = 1383,\n\tVI4_DATA10_MARK = 1384,\n\tDU_DB2_MARK = 1385,\n\tPWM5_A_MARK = 1386,\n\tIP3_7_4_MARK = 1387,\n\tA10_MARK = 1388,\n\tMSIOF2_RXD_A_MARK = 1389,\n\tRTS4_N_B_MARK = 1390,\n\tVI5_HSYNC_N_MARK = 1391,\n\tIP0_11_8_MARK = 1392,\n\tAVB_PHY_INT_MARK = 1393,\n\tMSIOF2_SYNC_C_MARK = 1394,\n\tRX4_A_MARK = 1395,\n\tIP1_11_8_MARK = 1396,\n\tIRQ4_MARK = 1397,\n\tQSTH_QHS_MARK = 1398,\n\tDU_EXHSYNC_DU_HSYNC_MARK = 1399,\n\tVI4_DATA4_B_MARK = 1400,\n\tMSIOF3_RXD_E_MARK = 1401,\n\tPWM5_B_MARK = 1402,\n\tIP2_11_8_MARK = 1403,\n\tA3_MARK = 1404,\n\tLCDOUT19_MARK = 1405,\n\tMSIOF3_RXD_B_MARK = 1406,\n\tVI4_DATA11_MARK = 1407,\n\tDU_DB3_MARK = 1408,\n\tPWM6_A_MARK = 1409,\n\tIP3_11_8_MARK = 1410,\n\tA11_MARK = 1411,\n\tTX3_B_MARK___2 = 1412,\n\tMSIOF2_TXD_A_MARK = 1413,\n\tHTX4_B_MARK = 1414,\n\tHSCK4_MARK = 1415,\n\tVI5_FIELD_MARK = 1416,\n\tSCL6_A_MARK = 1417,\n\tAVB_AVTP_CAPTURE_B_MARK = 1418,\n\tPWM2_B_MARK = 1419,\n\tIP0_15_12_MARK = 1420,\n\tAVB_LINK_MARK = 1421,\n\tMSIOF2_SCK_C_MARK = 1422,\n\tTX4_A_MARK = 1423,\n\tIP1_15_12_MARK = 1424,\n\tIRQ5_MARK___2 = 1425,\n\tQSTB_QHE_MARK = 1426,\n\tDU_EXVSYNC_DU_VSYNC_MARK = 1427,\n\tVI4_DATA5_B_MARK = 1428,\n\tMSIOF3_TXD_E_MARK = 1429,\n\tPWM6_B_MARK = 1430,\n\tIP2_15_12_MARK = 1431,\n\tA4_MARK = 1432,\n\tLCDOUT20_MARK = 1433,\n\tMSIOF3_SS1_B_MARK = 1434,\n\tVI4_DATA12_MARK = 1435,\n\tVI5_DATA12_MARK = 1436,\n\tDU_DB4_MARK = 1437,\n\tIP3_15_12_MARK = 1438,\n\tA12_MARK = 1439,\n\tLCDOUT12_MARK = 1440,\n\tMSIOF3_SCK_C_MARK = 1441,\n\tHRX4_A_MARK = 1442,\n\tVI5_DATA8_MARK = 1443,\n\tDU_DG4_MARK = 1444,\n\tIP0_19_16_MARK = 1445,\n\tAVB_AVTP_MATCH_A_MARK = 1446,\n\tMSIOF2_RXD_C_MARK = 1447,\n\tCTS4_N_A_MARK = 1448,\n\tIP1_19_16_MARK = 1449,\n\tPWM0_MARK___2 = 1450,\n\tAVB_AVTP_PPS_MARK = 1451,\n\tVI4_DATA6_B_MARK = 1452,\n\tIECLK_B_MARK = 1453,\n\tIP2_19_16_MARK = 1454,\n\tA5_MARK = 1455,\n\tLCDOUT21_MARK = 1456,\n\tMSIOF3_SS2_B_MARK = 1457,\n\tSCK4_B_MARK = 1458,\n\tVI4_DATA13_MARK = 1459,\n\tVI5_DATA13_MARK = 1460,\n\tDU_DB5_MARK = 1461,\n\tIP3_19_16_MARK = 1462,\n\tA13_MARK = 1463,\n\tLCDOUT13_MARK = 1464,\n\tMSIOF3_SYNC_C_MARK = 1465,\n\tHTX4_A_MARK = 1466,\n\tVI5_DATA9_MARK = 1467,\n\tDU_DG5_MARK = 1468,\n\tIP0_23_20_MARK = 1469,\n\tAVB_AVTP_CAPTURE_A_MARK = 1470,\n\tMSIOF2_TXD_C_MARK = 1471,\n\tRTS4_N_A_MARK = 1472,\n\tIP1_23_20_MARK = 1473,\n\tPWM1_A_MARK___2 = 1474,\n\tHRX3_D_MARK = 1475,\n\tVI4_DATA7_B_MARK = 1476,\n\tIERX_B_MARK = 1477,\n\tIP2_23_20_MARK = 1478,\n\tA6_MARK = 1479,\n\tLCDOUT22_MARK = 1480,\n\tMSIOF2_SS1_A_MARK = 1481,\n\tRX4_B_MARK = 1482,\n\tVI4_DATA14_MARK = 1483,\n\tVI5_DATA14_MARK = 1484,\n\tDU_DB6_MARK = 1485,\n\tIP3_23_20_MARK = 1486,\n\tA14_MARK = 1487,\n\tLCDOUT14_MARK = 1488,\n\tMSIOF3_RXD_C_MARK = 1489,\n\tHCTS4_N_MARK = 1490,\n\tVI5_DATA10_MARK = 1491,\n\tDU_DG6_MARK = 1492,\n\tIP0_27_24_MARK = 1493,\n\tIRQ0_MARK = 1494,\n\tQPOLB_MARK = 1495,\n\tDU_CDE_MARK = 1496,\n\tVI4_DATA0_B_MARK = 1497,\n\tCAN0_TX_B_MARK = 1498,\n\tCANFD0_TX_B_MARK = 1499,\n\tMSIOF3_SS2_E_MARK = 1500,\n\tIP1_27_24_MARK = 1501,\n\tPWM2_A_MARK = 1502,\n\tHTX3_D_MARK = 1503,\n\tIETX_B_MARK = 1504,\n\tIP2_27_24_MARK = 1505,\n\tA7_MARK = 1506,\n\tLCDOUT23_MARK = 1507,\n\tMSIOF2_SS2_A_MARK = 1508,\n\tTX4_B_MARK = 1509,\n\tVI4_DATA15_MARK = 1510,\n\tVI5_DATA15_MARK = 1511,\n\tDU_DB7_MARK = 1512,\n\tIP3_27_24_MARK = 1513,\n\tA15_MARK = 1514,\n\tLCDOUT15_MARK = 1515,\n\tMSIOF3_TXD_C_MARK = 1516,\n\tHRTS4_N_MARK = 1517,\n\tVI5_DATA11_MARK = 1518,\n\tDU_DG7_MARK = 1519,\n\tIP0_31_28_MARK = 1520,\n\tIRQ1_MARK = 1521,\n\tQPOLA_MARK = 1522,\n\tDU_DISP_MARK = 1523,\n\tVI4_DATA1_B_MARK = 1524,\n\tCAN0_RX_B_MARK = 1525,\n\tCANFD0_RX_B_MARK = 1526,\n\tMSIOF3_SS1_E_MARK = 1527,\n\tIP1_31_28_MARK = 1528,\n\tA0_MARK = 1529,\n\tLCDOUT16_MARK = 1530,\n\tMSIOF3_SYNC_B_MARK = 1531,\n\tVI4_DATA8_MARK = 1532,\n\tDU_DB0_MARK = 1533,\n\tPWM3_A_MARK___2 = 1534,\n\tIP2_31_28_MARK = 1535,\n\tA8_MARK = 1536,\n\tRX3_B_MARK___2 = 1537,\n\tMSIOF2_SYNC_A_MARK = 1538,\n\tHRX4_B_MARK = 1539,\n\tSDA6_A_MARK = 1540,\n\tAVB_AVTP_MATCH_B_MARK = 1541,\n\tPWM1_B_MARK___2 = 1542,\n\tIP3_31_28_MARK = 1543,\n\tA16_MARK = 1544,\n\tLCDOUT8_MARK = 1545,\n\tVI4_FIELD_MARK = 1546,\n\tDU_DG0_MARK = 1547,\n\tIP4_3_0_MARK = 1548,\n\tA17_MARK = 1549,\n\tLCDOUT9_MARK = 1550,\n\tVI4_VSYNC_N_MARK = 1551,\n\tDU_DG1_MARK = 1552,\n\tIP5_3_0_MARK = 1553,\n\tWE0_N_MARK = 1554,\n\tMSIOF3_TXD_D_MARK = 1555,\n\tCTS3_N_MARK = 1556,\n\tHCTS3_N_MARK = 1557,\n\tSCL6_B_MARK = 1558,\n\tCAN_CLK_MARK___2 = 1559,\n\tIECLK_A_MARK = 1560,\n\tIP6_3_0_MARK = 1561,\n\tD5_MARK = 1562,\n\tMSIOF2_SYNC_B_MARK = 1563,\n\tVI4_DATA21_MARK = 1564,\n\tVI5_DATA5_MARK = 1565,\n\tIP7_3_0_MARK = 1566,\n\tD13_MARK = 1567,\n\tLCDOUT5_MARK = 1568,\n\tMSIOF2_SS2_D_MARK = 1569,\n\tTX4_C_MARK = 1570,\n\tVI4_DATA5_A_MARK = 1571,\n\tDU_DR5_MARK = 1572,\n\tIP4_7_4_MARK = 1573,\n\tA18_MARK = 1574,\n\tLCDOUT10_MARK = 1575,\n\tVI4_HSYNC_N_MARK = 1576,\n\tDU_DG2_MARK = 1577,\n\tIP5_7_4_MARK = 1578,\n\tWE1_N_MARK = 1579,\n\tMSIOF3_SS1_D_MARK = 1580,\n\tRTS3_N_MARK = 1581,\n\tHRTS3_N_MARK = 1582,\n\tSDA6_B_MARK = 1583,\n\tCAN1_RX_MARK = 1584,\n\tCANFD1_RX_MARK___2 = 1585,\n\tIERX_A_MARK = 1586,\n\tIP6_7_4_MARK = 1587,\n\tD6_MARK = 1588,\n\tMSIOF2_RXD_B_MARK = 1589,\n\tVI4_DATA22_MARK = 1590,\n\tVI5_DATA6_MARK = 1591,\n\tIP7_7_4_MARK = 1592,\n\tD14_MARK = 1593,\n\tLCDOUT6_MARK = 1594,\n\tMSIOF3_SS1_A_MARK = 1595,\n\tHRX3_C_MARK = 1596,\n\tVI4_DATA6_A_MARK = 1597,\n\tDU_DR6_MARK = 1598,\n\tSCL6_C_MARK = 1599,\n\tIP4_11_8_MARK = 1600,\n\tA19_MARK = 1601,\n\tLCDOUT11_MARK = 1602,\n\tVI4_CLKENB_MARK = 1603,\n\tDU_DG3_MARK = 1604,\n\tIP5_11_8_MARK = 1605,\n\tEX_WAIT0_A_MARK = 1606,\n\tQCLK_MARK = 1607,\n\tVI4_CLK_MARK = 1608,\n\tDU_DOTCLKOUT0_MARK = 1609,\n\tIP6_11_8_MARK = 1610,\n\tD7_MARK = 1611,\n\tMSIOF2_TXD_B_MARK = 1612,\n\tVI4_DATA23_MARK = 1613,\n\tVI5_DATA7_MARK = 1614,\n\tIP7_11_8_MARK = 1615,\n\tD15_MARK = 1616,\n\tLCDOUT7_MARK = 1617,\n\tMSIOF3_SS2_A_MARK = 1618,\n\tHTX3_C_MARK = 1619,\n\tVI4_DATA7_A_MARK = 1620,\n\tDU_DR7_MARK = 1621,\n\tSDA6_C_MARK = 1622,\n\tIP4_15_12_MARK = 1623,\n\tCS0_N_MARK = 1624,\n\tVI5_CLKENB_MARK = 1625,\n\tIP5_15_12_MARK = 1626,\n\tD0_MARK = 1627,\n\tMSIOF2_SS1_B_MARK = 1628,\n\tMSIOF3_SCK_A_MARK = 1629,\n\tVI4_DATA16_MARK = 1630,\n\tVI5_DATA0_MARK = 1631,\n\tIP6_15_12_MARK = 1632,\n\tD8_MARK = 1633,\n\tLCDOUT0_MARK = 1634,\n\tMSIOF2_SCK_D_MARK = 1635,\n\tSCK4_C_MARK = 1636,\n\tVI4_DATA0_A_MARK = 1637,\n\tDU_DR0_MARK = 1638,\n\tIP4_19_16_MARK = 1639,\n\tCS1_N_MARK = 1640,\n\tVI5_CLK_MARK = 1641,\n\tEX_WAIT0_B_MARK = 1642,\n\tIP5_19_16_MARK = 1643,\n\tD1_MARK = 1644,\n\tMSIOF2_SS2_B_MARK = 1645,\n\tMSIOF3_SYNC_A_MARK = 1646,\n\tVI4_DATA17_MARK = 1647,\n\tVI5_DATA1_MARK = 1648,\n\tIP6_19_16_MARK = 1649,\n\tD9_MARK = 1650,\n\tLCDOUT1_MARK = 1651,\n\tMSIOF2_SYNC_D_MARK = 1652,\n\tVI4_DATA1_A_MARK = 1653,\n\tDU_DR1_MARK = 1654,\n\tIP7_19_16_MARK = 1655,\n\tSD0_CLK_MARK = 1656,\n\tMSIOF1_SCK_E_MARK = 1657,\n\tSTP_OPWM_0_B_MARK = 1658,\n\tIP4_23_20_MARK = 1659,\n\tBS_N_MARK = 1660,\n\tQSTVA_QVS_MARK = 1661,\n\tMSIOF3_SCK_D_MARK = 1662,\n\tSCK3_MARK = 1663,\n\tHSCK3_MARK = 1664,\n\tCAN1_TX_MARK = 1665,\n\tCANFD1_TX_MARK___2 = 1666,\n\tIETX_A_MARK = 1667,\n\tIP5_23_20_MARK = 1668,\n\tD2_MARK = 1669,\n\tMSIOF3_RXD_A_MARK = 1670,\n\tVI4_DATA18_MARK = 1671,\n\tVI5_DATA2_MARK = 1672,\n\tIP6_23_20_MARK = 1673,\n\tD10_MARK = 1674,\n\tLCDOUT2_MARK = 1675,\n\tMSIOF2_RXD_D_MARK = 1676,\n\tHRX3_B_MARK___2 = 1677,\n\tVI4_DATA2_A_MARK = 1678,\n\tCTS4_N_C_MARK = 1679,\n\tDU_DR2_MARK = 1680,\n\tIP7_23_20_MARK = 1681,\n\tSD0_CMD_MARK = 1682,\n\tMSIOF1_SYNC_E_MARK = 1683,\n\tSTP_IVCXO27_0_B_MARK = 1684,\n\tIP4_27_24_MARK = 1685,\n\tRD_N_MARK = 1686,\n\tMSIOF3_SYNC_D_MARK = 1687,\n\tRX3_A_MARK___2 = 1688,\n\tHRX3_A_MARK___2 = 1689,\n\tCAN0_TX_A_MARK = 1690,\n\tCANFD0_TX_A_MARK = 1691,\n\tIP5_27_24_MARK = 1692,\n\tD3_MARK = 1693,\n\tMSIOF3_TXD_A_MARK = 1694,\n\tVI4_DATA19_MARK = 1695,\n\tVI5_DATA3_MARK = 1696,\n\tIP6_27_24_MARK = 1697,\n\tD11_MARK = 1698,\n\tLCDOUT3_MARK = 1699,\n\tMSIOF2_TXD_D_MARK = 1700,\n\tHTX3_B_MARK___2 = 1701,\n\tVI4_DATA3_A_MARK = 1702,\n\tRTS4_N_C_MARK = 1703,\n\tDU_DR3_MARK = 1704,\n\tIP7_27_24_MARK = 1705,\n\tSD0_DAT0_MARK = 1706,\n\tMSIOF1_RXD_E_MARK = 1707,\n\tTS_SCK0_B_MARK = 1708,\n\tSTP_ISCLK_0_B_MARK = 1709,\n\tIP4_31_28_MARK = 1710,\n\tRD_WR_N_MARK = 1711,\n\tMSIOF3_RXD_D_MARK = 1712,\n\tTX3_A_MARK___2 = 1713,\n\tHTX3_A_MARK___2 = 1714,\n\tCAN0_RX_A_MARK = 1715,\n\tCANFD0_RX_A_MARK = 1716,\n\tIP5_31_28_MARK = 1717,\n\tD4_MARK = 1718,\n\tMSIOF2_SCK_B_MARK = 1719,\n\tVI4_DATA20_MARK = 1720,\n\tVI5_DATA4_MARK = 1721,\n\tIP6_31_28_MARK = 1722,\n\tD12_MARK = 1723,\n\tLCDOUT4_MARK = 1724,\n\tMSIOF2_SS1_D_MARK = 1725,\n\tRX4_C_MARK = 1726,\n\tVI4_DATA4_A_MARK = 1727,\n\tDU_DR4_MARK = 1728,\n\tIP7_31_28_MARK = 1729,\n\tSD0_DAT1_MARK = 1730,\n\tMSIOF1_TXD_E_MARK = 1731,\n\tTS_SPSYNC0_B_MARK = 1732,\n\tSTP_ISSYNC_0_B_MARK = 1733,\n\tIP8_3_0_MARK = 1734,\n\tSD0_DAT2_MARK = 1735,\n\tMSIOF1_SS1_E_MARK = 1736,\n\tTS_SDAT0_B_MARK = 1737,\n\tSTP_ISD_0_B_MARK = 1738,\n\tIP9_3_0_MARK = 1739,\n\tSD2_CLK_MARK = 1740,\n\tNFDATA8_MARK = 1741,\n\tIP10_3_0_MARK = 1742,\n\tSD3_CMD_MARK = 1743,\n\tNFRE_N_MARK = 1744,\n\tIP11_3_0_MARK = 1745,\n\tSD3_DAT7_MARK = 1746,\n\tSD3_WP_MARK = 1747,\n\tNFDATA7_MARK = 1748,\n\tIP8_7_4_MARK = 1749,\n\tSD0_DAT3_MARK = 1750,\n\tMSIOF1_SS2_E_MARK = 1751,\n\tTS_SDEN0_B_MARK = 1752,\n\tSTP_ISEN_0_B_MARK = 1753,\n\tIP9_7_4_MARK = 1754,\n\tSD2_CMD_MARK = 1755,\n\tNFDATA9_MARK = 1756,\n\tIP10_7_4_MARK = 1757,\n\tSD3_DAT0_MARK = 1758,\n\tNFDATA0_MARK = 1759,\n\tIP11_7_4_MARK = 1760,\n\tSD3_DS_MARK = 1761,\n\tNFCLE_MARK = 1762,\n\tIP8_11_8_MARK = 1763,\n\tSD1_CLK_MARK = 1764,\n\tMSIOF1_SCK_G_MARK = 1765,\n\tSIM0_CLK_A_MARK = 1766,\n\tIP9_11_8_MARK = 1767,\n\tSD2_DAT0_MARK = 1768,\n\tNFDATA10_MARK = 1769,\n\tIP10_11_8_MARK = 1770,\n\tSD3_DAT1_MARK = 1771,\n\tNFDATA1_MARK = 1772,\n\tIP11_11_8_MARK = 1773,\n\tSD0_CD_MARK = 1774,\n\tNFDATA14_A_MARK = 1775,\n\tSCL2_B_MARK = 1776,\n\tSIM0_RST_A_MARK = 1777,\n\tIP8_15_12_MARK = 1778,\n\tSD1_CMD_MARK = 1779,\n\tMSIOF1_SYNC_G_MARK = 1780,\n\tNFCE_N_B_MARK = 1781,\n\tSIM0_D_A_MARK = 1782,\n\tSTP_IVCXO27_1_B_MARK = 1783,\n\tIP9_15_12_MARK = 1784,\n\tSD2_DAT1_MARK = 1785,\n\tNFDATA11_MARK = 1786,\n\tIP10_15_12_MARK = 1787,\n\tSD3_DAT2_MARK = 1788,\n\tNFDATA2_MARK = 1789,\n\tIP11_15_12_MARK = 1790,\n\tSD0_WP_MARK = 1791,\n\tNFDATA15_A_MARK = 1792,\n\tSDA2_B_MARK = 1793,\n\tIP8_19_16_MARK = 1794,\n\tSD1_DAT0_MARK = 1795,\n\tSD2_DAT4_MARK = 1796,\n\tMSIOF1_RXD_G_MARK = 1797,\n\tNFWP_N_B_MARK = 1798,\n\tTS_SCK1_B_MARK = 1799,\n\tSTP_ISCLK_1_B_MARK = 1800,\n\tIP9_19_16_MARK = 1801,\n\tSD2_DAT2_MARK = 1802,\n\tNFDATA12_MARK = 1803,\n\tIP10_19_16_MARK = 1804,\n\tSD3_DAT3_MARK = 1805,\n\tNFDATA3_MARK = 1806,\n\tIP11_19_16_MARK = 1807,\n\tSD1_CD_MARK = 1808,\n\tNFRB_N_A_MARK = 1809,\n\tSIM0_CLK_B_MARK = 1810,\n\tIP8_23_20_MARK = 1811,\n\tSD1_DAT1_MARK = 1812,\n\tSD2_DAT5_MARK = 1813,\n\tMSIOF1_TXD_G_MARK = 1814,\n\tNFDATA14_B_MARK = 1815,\n\tTS_SPSYNC1_B_MARK = 1816,\n\tSTP_ISSYNC_1_B_MARK = 1817,\n\tIP9_23_20_MARK = 1818,\n\tSD2_DAT3_MARK = 1819,\n\tNFDATA13_MARK = 1820,\n\tIP10_23_20_MARK = 1821,\n\tSD3_DAT4_MARK = 1822,\n\tSD2_CD_A_MARK = 1823,\n\tNFDATA4_MARK = 1824,\n\tIP11_23_20_MARK = 1825,\n\tSD1_WP_MARK = 1826,\n\tNFCE_N_A_MARK = 1827,\n\tSIM0_D_B_MARK = 1828,\n\tIP8_27_24_MARK = 1829,\n\tSD1_DAT2_MARK = 1830,\n\tSD2_DAT6_MARK = 1831,\n\tMSIOF1_SS1_G_MARK = 1832,\n\tNFDATA15_B_MARK = 1833,\n\tTS_SDAT1_B_MARK = 1834,\n\tSTP_ISD_1_B_MARK = 1835,\n\tIP9_27_24_MARK = 1836,\n\tSD2_DS_MARK = 1837,\n\tNFALE_MARK = 1838,\n\tIP10_27_24_MARK = 1839,\n\tSD3_DAT5_MARK = 1840,\n\tSD2_WP_A_MARK = 1841,\n\tNFDATA5_MARK = 1842,\n\tIP11_27_24_MARK = 1843,\n\tSCK0_MARK___2 = 1844,\n\tHSCK1_B_MARK___2 = 1845,\n\tMSIOF1_SS2_B_MARK = 1846,\n\tAUDIO_CLKC_B_MARK = 1847,\n\tSDA2_A_MARK = 1848,\n\tSIM0_RST_B_MARK = 1849,\n\tSTP_OPWM_0_C_MARK = 1850,\n\tRIF0_CLK_B_MARK = 1851,\n\tADICHS2_MARK = 1852,\n\tSCK5_B_MARK = 1853,\n\tIP8_31_28_MARK = 1854,\n\tSD1_DAT3_MARK = 1855,\n\tSD2_DAT7_MARK = 1856,\n\tMSIOF1_SS2_G_MARK = 1857,\n\tNFRB_N_B_MARK = 1858,\n\tTS_SDEN1_B_MARK = 1859,\n\tSTP_ISEN_1_B_MARK = 1860,\n\tIP9_31_28_MARK = 1861,\n\tSD3_CLK_MARK = 1862,\n\tNFWE_N_MARK = 1863,\n\tIP10_31_28_MARK = 1864,\n\tSD3_DAT6_MARK = 1865,\n\tSD3_CD_MARK = 1866,\n\tNFDATA6_MARK = 1867,\n\tIP11_31_28_MARK = 1868,\n\tRX0_MARK___2 = 1869,\n\tHRX1_B_MARK___2 = 1870,\n\tTS_SCK0_C_MARK = 1871,\n\tSTP_ISCLK_0_C_MARK = 1872,\n\tRIF0_D0_B_MARK = 1873,\n\tIP12_3_0_MARK = 1874,\n\tTX0_MARK___2 = 1875,\n\tHTX1_B_MARK___2 = 1876,\n\tTS_SPSYNC0_C_MARK = 1877,\n\tSTP_ISSYNC_0_C_MARK = 1878,\n\tRIF0_D1_B_MARK = 1879,\n\tIP13_3_0_MARK = 1880,\n\tTX2_A_MARK = 1881,\n\tSD2_CD_B_MARK = 1882,\n\tSCL1_A_MARK = 1883,\n\tFMCLK_A_MARK = 1884,\n\tRIF1_D1_C_MARK = 1885,\n\tFSO_CFE_0_N_MARK = 1886,\n\tIP14_3_0_MARK = 1887,\n\tMSIOF0_SS1_MARK___2 = 1888,\n\tRX5_A_MARK = 1889,\n\tNFWP_N_A_MARK = 1890,\n\tAUDIO_CLKA_C_MARK = 1891,\n\tSSI_SCK2_A_MARK = 1892,\n\tSTP_IVCXO27_0_C_MARK = 1893,\n\tAUDIO_CLKOUT3_A_MARK = 1894,\n\tTCLK1_B_MARK___2 = 1895,\n\tIP15_3_0_MARK = 1896,\n\tSSI_SDATA1_A_MARK = 1897,\n\tIP12_7_4_MARK = 1898,\n\tCTS0_N_MARK___2 = 1899,\n\tHCTS1_N_B_MARK___2 = 1900,\n\tMSIOF1_SYNC_B_MARK = 1901,\n\tTS_SPSYNC1_C_MARK = 1902,\n\tSTP_ISSYNC_1_C_MARK = 1903,\n\tRIF1_SYNC_B_MARK = 1904,\n\tAUDIO_CLKOUT_C_MARK = 1905,\n\tADICS_SAMP_MARK = 1906,\n\tIP13_7_4_MARK = 1907,\n\tRX2_A_MARK = 1908,\n\tSD2_WP_B_MARK = 1909,\n\tSDA1_A_MARK = 1910,\n\tFMIN_A_MARK = 1911,\n\tRIF1_SYNC_C_MARK = 1912,\n\tFSO_CFE_1_N_MARK = 1913,\n\tIP14_7_4_MARK = 1914,\n\tMSIOF0_SS2_MARK___2 = 1915,\n\tTX5_A_MARK = 1916,\n\tMSIOF1_SS2_D_MARK = 1917,\n\tAUDIO_CLKC_A_MARK = 1918,\n\tSSI_WS2_A_MARK = 1919,\n\tSTP_OPWM_0_D_MARK = 1920,\n\tAUDIO_CLKOUT_D_MARK = 1921,\n\tSPEEDIN_B_MARK = 1922,\n\tIP15_7_4_MARK = 1923,\n\tSSI_SDATA2_A_MARK = 1924,\n\tSSI_SCK1_B_MARK = 1925,\n\tIP12_11_8_MARK = 1926,\n\tRTS0_N_MARK___2 = 1927,\n\tHRTS1_N_B_MARK___2 = 1928,\n\tMSIOF1_SS1_B_MARK = 1929,\n\tAUDIO_CLKA_B_MARK = 1930,\n\tSCL2_A_MARK = 1931,\n\tSTP_IVCXO27_1_C_MARK = 1932,\n\tRIF0_SYNC_B_MARK = 1933,\n\tADICHS1_MARK = 1934,\n\tIP13_11_8_MARK = 1935,\n\tHSCK0_MARK___2 = 1936,\n\tMSIOF1_SCK_D_MARK = 1937,\n\tAUDIO_CLKB_A_MARK = 1938,\n\tSSI_SDATA1_B_MARK = 1939,\n\tTS_SCK0_D_MARK = 1940,\n\tSTP_ISCLK_0_D_MARK = 1941,\n\tRIF0_CLK_C_MARK = 1942,\n\tRX5_B_MARK = 1943,\n\tIP14_11_8_MARK = 1944,\n\tMLB_CLK_MARK = 1945,\n\tMSIOF1_SCK_F_MARK = 1946,\n\tSCL1_B_MARK = 1947,\n\tIP15_11_8_MARK = 1948,\n\tSSI_SCK349_MARK = 1949,\n\tMSIOF1_SS1_A_MARK = 1950,\n\tSTP_OPWM_0_A_MARK = 1951,\n\tIP12_15_12_MARK = 1952,\n\tRX1_A_MARK___2 = 1953,\n\tHRX1_A_MARK___2 = 1954,\n\tTS_SDAT0_C_MARK = 1955,\n\tSTP_ISD_0_C_MARK = 1956,\n\tRIF1_CLK_C_MARK = 1957,\n\tIP13_15_12_MARK = 1958,\n\tHRX0_MARK___2 = 1959,\n\tMSIOF1_RXD_D_MARK = 1960,\n\tSSI_SDATA2_B_MARK = 1961,\n\tTS_SDEN0_D_MARK = 1962,\n\tSTP_ISEN_0_D_MARK = 1963,\n\tRIF0_D0_C_MARK = 1964,\n\tIP14_15_12_MARK = 1965,\n\tMLB_SIG_MARK = 1966,\n\tRX1_B_MARK___2 = 1967,\n\tMSIOF1_SYNC_F_MARK = 1968,\n\tSDA1_B_MARK = 1969,\n\tIP15_15_12_MARK = 1970,\n\tSSI_WS349_MARK = 1971,\n\tHCTS2_N_A_MARK = 1972,\n\tMSIOF1_SS2_A_MARK = 1973,\n\tSTP_IVCXO27_0_A_MARK = 1974,\n\tIP12_19_16_MARK = 1975,\n\tTX1_A_MARK___2 = 1976,\n\tHTX1_A_MARK___2 = 1977,\n\tTS_SDEN0_C_MARK = 1978,\n\tSTP_ISEN_0_C_MARK = 1979,\n\tRIF1_D0_C_MARK = 1980,\n\tIP13_19_16_MARK = 1981,\n\tHTX0_MARK___2 = 1982,\n\tMSIOF1_TXD_D_MARK = 1983,\n\tSSI_SDATA9_B_MARK = 1984,\n\tTS_SDAT0_D_MARK = 1985,\n\tSTP_ISD_0_D_MARK = 1986,\n\tRIF0_D1_C_MARK = 1987,\n\tIP14_19_16_MARK = 1988,\n\tMLB_DAT_MARK = 1989,\n\tTX1_B_MARK___2 = 1990,\n\tMSIOF1_RXD_F_MARK = 1991,\n\tIP15_19_16_MARK = 1992,\n\tSSI_SDATA3_MARK = 1993,\n\tHRTS2_N_A_MARK = 1994,\n\tMSIOF1_TXD_A_MARK = 1995,\n\tTS_SCK0_A_MARK = 1996,\n\tSTP_ISCLK_0_A_MARK = 1997,\n\tRIF0_D1_A_MARK = 1998,\n\tRIF2_D0_A_MARK = 1999,\n\tIP12_23_20_MARK = 2000,\n\tCTS1_N_MARK = 2001,\n\tHCTS1_N_A_MARK___2 = 2002,\n\tMSIOF1_RXD_B_MARK = 2003,\n\tTS_SDEN1_C_MARK = 2004,\n\tSTP_ISEN_1_C_MARK = 2005,\n\tRIF1_D0_B_MARK = 2006,\n\tADIDATA_MARK = 2007,\n\tIP13_23_20_MARK = 2008,\n\tHCTS0_N_MARK___2 = 2009,\n\tRX2_B_MARK = 2010,\n\tMSIOF1_SYNC_D_MARK = 2011,\n\tSSI_SCK9_A_MARK = 2012,\n\tTS_SPSYNC0_D_MARK = 2013,\n\tSTP_ISSYNC_0_D_MARK = 2014,\n\tRIF0_SYNC_C_MARK = 2015,\n\tAUDIO_CLKOUT1_A_MARK = 2016,\n\tIP14_23_20_MARK = 2017,\n\tSSI_SCK01239_MARK = 2018,\n\tMSIOF1_TXD_F_MARK = 2019,\n\tIP15_23_20_MARK = 2020,\n\tSSI_SCK4_MARK = 2021,\n\tHRX2_A_MARK = 2022,\n\tMSIOF1_SCK_A_MARK = 2023,\n\tTS_SDAT0_A_MARK = 2024,\n\tSTP_ISD_0_A_MARK = 2025,\n\tRIF0_CLK_A_MARK = 2026,\n\tRIF2_CLK_A_MARK = 2027,\n\tIP12_27_24_MARK = 2028,\n\tRTS1_N_MARK = 2029,\n\tHRTS1_N_A_MARK___2 = 2030,\n\tMSIOF1_TXD_B_MARK = 2031,\n\tTS_SDAT1_C_MARK = 2032,\n\tSTP_ISD_1_C_MARK = 2033,\n\tRIF1_D1_B_MARK = 2034,\n\tADICHS0_MARK = 2035,\n\tIP13_27_24_MARK = 2036,\n\tHRTS0_N_MARK___2 = 2037,\n\tTX2_B_MARK = 2038,\n\tMSIOF1_SS1_D_MARK = 2039,\n\tSSI_WS9_A_MARK = 2040,\n\tSTP_IVCXO27_0_D_MARK = 2041,\n\tBPFCLK_A_MARK = 2042,\n\tAUDIO_CLKOUT2_A_MARK = 2043,\n\tIP14_27_24_MARK = 2044,\n\tSSI_WS01239_MARK = 2045,\n\tMSIOF1_SS1_F_MARK = 2046,\n\tIP15_27_24_MARK = 2047,\n\tSSI_WS4_MARK = 2048,\n\tHTX2_A_MARK = 2049,\n\tMSIOF1_SYNC_A_MARK = 2050,\n\tTS_SDEN0_A_MARK = 2051,\n\tSTP_ISEN_0_A_MARK = 2052,\n\tRIF0_SYNC_A_MARK = 2053,\n\tRIF2_SYNC_A_MARK = 2054,\n\tIP12_31_28_MARK = 2055,\n\tSCK2_MARK = 2056,\n\tSCIF_CLK_B_MARK = 2057,\n\tMSIOF1_SCK_B_MARK = 2058,\n\tTS_SCK1_C_MARK = 2059,\n\tSTP_ISCLK_1_C_MARK = 2060,\n\tRIF1_CLK_B_MARK = 2061,\n\tADICLK_MARK = 2062,\n\tIP13_31_28_MARK = 2063,\n\tMSIOF0_SYNC_MARK___2 = 2064,\n\tAUDIO_CLKOUT_A_MARK = 2065,\n\tTX5_B_MARK = 2066,\n\tBPFCLK_D_MARK = 2067,\n\tIP14_31_28_MARK = 2068,\n\tSSI_SDATA0_MARK = 2069,\n\tMSIOF1_SS2_F_MARK = 2070,\n\tIP15_31_28_MARK = 2071,\n\tSSI_SDATA4_MARK = 2072,\n\tHSCK2_A_MARK = 2073,\n\tMSIOF1_RXD_A_MARK = 2074,\n\tTS_SPSYNC0_A_MARK = 2075,\n\tSTP_ISSYNC_0_A_MARK = 2076,\n\tRIF0_D0_A_MARK = 2077,\n\tRIF2_D1_A_MARK = 2078,\n\tIP16_3_0_MARK = 2079,\n\tSSI_SCK6_MARK = 2080,\n\tSIM0_RST_D_MARK = 2081,\n\tIP17_3_0_MARK = 2082,\n\tAUDIO_CLKA_A_MARK = 2083,\n\tIP18_3_0_MARK = 2084,\n\tGP6_30_MARK = 2085,\n\tAUDIO_CLKOUT2_B_MARK = 2086,\n\tSSI_SCK9_B_MARK = 2087,\n\tTS_SDEN0_E_MARK = 2088,\n\tSTP_ISEN_0_E_MARK = 2089,\n\tRIF2_D0_B_MARK = 2090,\n\tTPU0TO2_MARK = 2091,\n\tFMCLK_C_MARK = 2092,\n\tFMCLK_D_MARK = 2093,\n\tIP16_7_4_MARK = 2094,\n\tSSI_WS6_MARK = 2095,\n\tSIM0_D_D_MARK = 2096,\n\tIP17_7_4_MARK = 2097,\n\tAUDIO_CLKB_B_MARK = 2098,\n\tSCIF_CLK_A_MARK = 2099,\n\tSTP_IVCXO27_1_D_MARK = 2100,\n\tREMOCON_A_MARK = 2101,\n\tTCLK1_A_MARK___2 = 2102,\n\tIP18_7_4_MARK = 2103,\n\tGP6_31_MARK = 2104,\n\tAUDIO_CLKOUT3_B_MARK = 2105,\n\tSSI_WS9_B_MARK = 2106,\n\tTS_SPSYNC0_E_MARK = 2107,\n\tSTP_ISSYNC_0_E_MARK = 2108,\n\tRIF2_D1_B_MARK = 2109,\n\tTPU0TO3_MARK = 2110,\n\tFMIN_C_MARK = 2111,\n\tFMIN_D_MARK = 2112,\n\tIP16_11_8_MARK = 2113,\n\tSSI_SDATA6_MARK = 2114,\n\tSIM0_CLK_D_MARK = 2115,\n\tIP17_11_8_MARK = 2116,\n\tUSB0_PWEN_MARK = 2117,\n\tSIM0_RST_C_MARK = 2118,\n\tTS_SCK1_D_MARK = 2119,\n\tSTP_ISCLK_1_D_MARK = 2120,\n\tBPFCLK_B_MARK = 2121,\n\tRIF3_CLK_B_MARK = 2122,\n\tHSCK2_C_MARK = 2123,\n\tIP16_15_12_MARK = 2124,\n\tSSI_SCK78_MARK = 2125,\n\tHRX2_B_MARK = 2126,\n\tMSIOF1_SCK_C_MARK = 2127,\n\tTS_SCK1_A_MARK = 2128,\n\tSTP_ISCLK_1_A_MARK = 2129,\n\tRIF1_CLK_A_MARK = 2130,\n\tRIF3_CLK_A_MARK = 2131,\n\tIP17_15_12_MARK = 2132,\n\tUSB0_OVC_MARK = 2133,\n\tSIM0_D_C_MARK = 2134,\n\tTS_SDAT1_D_MARK = 2135,\n\tSTP_ISD_1_D_MARK = 2136,\n\tRIF3_SYNC_B_MARK = 2137,\n\tHRX2_C_MARK = 2138,\n\tIP16_19_16_MARK = 2139,\n\tSSI_WS78_MARK = 2140,\n\tHTX2_B_MARK = 2141,\n\tMSIOF1_SYNC_C_MARK = 2142,\n\tTS_SDAT1_A_MARK = 2143,\n\tSTP_ISD_1_A_MARK = 2144,\n\tRIF1_SYNC_A_MARK = 2145,\n\tRIF3_SYNC_A_MARK = 2146,\n\tIP17_19_16_MARK = 2147,\n\tUSB1_PWEN_MARK = 2148,\n\tSIM0_CLK_C_MARK = 2149,\n\tSSI_SCK1_A_MARK = 2150,\n\tTS_SCK0_E_MARK = 2151,\n\tSTP_ISCLK_0_E_MARK = 2152,\n\tFMCLK_B_MARK = 2153,\n\tRIF2_CLK_B_MARK = 2154,\n\tSPEEDIN_A_MARK = 2155,\n\tHTX2_C_MARK = 2156,\n\tIP16_23_20_MARK = 2157,\n\tSSI_SDATA7_MARK = 2158,\n\tHCTS2_N_B_MARK = 2159,\n\tMSIOF1_RXD_C_MARK = 2160,\n\tTS_SDEN1_A_MARK = 2161,\n\tSTP_ISEN_1_A_MARK = 2162,\n\tRIF1_D0_A_MARK = 2163,\n\tRIF3_D0_A_MARK = 2164,\n\tTCLK2_A_MARK___2 = 2165,\n\tIP17_23_20_MARK = 2166,\n\tUSB1_OVC_MARK = 2167,\n\tMSIOF1_SS2_C_MARK = 2168,\n\tSSI_WS1_A_MARK = 2169,\n\tTS_SDAT0_E_MARK = 2170,\n\tSTP_ISD_0_E_MARK = 2171,\n\tFMIN_B_MARK = 2172,\n\tRIF2_SYNC_B_MARK = 2173,\n\tREMOCON_B_MARK = 2174,\n\tHCTS2_N_C_MARK = 2175,\n\tIP16_27_24_MARK = 2176,\n\tSSI_SDATA8_MARK = 2177,\n\tHRTS2_N_B_MARK = 2178,\n\tMSIOF1_TXD_C_MARK = 2179,\n\tTS_SPSYNC1_A_MARK = 2180,\n\tSTP_ISSYNC_1_A_MARK = 2181,\n\tRIF1_D1_A_MARK = 2182,\n\tRIF3_D1_A_MARK = 2183,\n\tIP17_27_24_MARK = 2184,\n\tUSB30_PWEN_MARK = 2185,\n\tAUDIO_CLKOUT_B_MARK = 2186,\n\tSSI_SCK2_B_MARK = 2187,\n\tTS_SDEN1_D_MARK = 2188,\n\tSTP_ISEN_1_D_MARK = 2189,\n\tSTP_OPWM_0_E_MARK = 2190,\n\tRIF3_D0_B_MARK = 2191,\n\tTCLK2_B_MARK___2 = 2192,\n\tTPU0TO0_MARK = 2193,\n\tBPFCLK_C_MARK = 2194,\n\tHRTS2_N_C_MARK = 2195,\n\tIP16_31_28_MARK = 2196,\n\tSSI_SDATA9_A_MARK = 2197,\n\tHSCK2_B_MARK = 2198,\n\tMSIOF1_SS1_C_MARK = 2199,\n\tHSCK1_A_MARK___2 = 2200,\n\tSSI_WS1_B_MARK = 2201,\n\tSCK1_MARK = 2202,\n\tSTP_IVCXO27_1_A_MARK = 2203,\n\tSCK5_A_MARK = 2204,\n\tIP17_31_28_MARK = 2205,\n\tUSB30_OVC_MARK = 2206,\n\tAUDIO_CLKOUT1_B_MARK = 2207,\n\tSSI_WS2_B_MARK = 2208,\n\tTS_SPSYNC1_D_MARK = 2209,\n\tSTP_ISSYNC_1_D_MARK = 2210,\n\tSTP_IVCXO27_0_E_MARK = 2211,\n\tRIF3_D1_B_MARK = 2212,\n\tFSO_TOE_N_MARK = 2213,\n\tTPU0TO1_MARK = 2214,\n\tSEL_MSIOF3_0_MARK = 2215,\n\tSEL_MSIOF3_1_MARK = 2216,\n\tSEL_MSIOF3_2_MARK = 2217,\n\tSEL_MSIOF3_3_MARK = 2218,\n\tSEL_MSIOF3_4_MARK = 2219,\n\tSEL_TSIF1_0_MARK = 2220,\n\tSEL_TSIF1_1_MARK = 2221,\n\tSEL_TSIF1_2_MARK = 2222,\n\tSEL_TSIF1_3_MARK = 2223,\n\tI2C_SEL_5_0_MARK = 2224,\n\tI2C_SEL_5_1_MARK = 2225,\n\tI2C_SEL_3_0_MARK = 2226,\n\tI2C_SEL_3_1_MARK = 2227,\n\tSEL_TSIF0_0_MARK = 2228,\n\tSEL_TSIF0_1_MARK = 2229,\n\tSEL_TSIF0_2_MARK = 2230,\n\tSEL_TSIF0_3_MARK = 2231,\n\tSEL_TSIF0_4_MARK = 2232,\n\tI2C_SEL_0_0_MARK = 2233,\n\tI2C_SEL_0_1_MARK = 2234,\n\tSEL_MSIOF2_0_MARK = 2235,\n\tSEL_MSIOF2_1_MARK = 2236,\n\tSEL_MSIOF2_2_MARK = 2237,\n\tSEL_MSIOF2_3_MARK = 2238,\n\tSEL_FM_0_MARK = 2239,\n\tSEL_FM_1_MARK = 2240,\n\tSEL_FM_2_MARK = 2241,\n\tSEL_FM_3_MARK = 2242,\n\tSEL_MSIOF1_0_MARK = 2243,\n\tSEL_MSIOF1_1_MARK = 2244,\n\tSEL_MSIOF1_2_MARK = 2245,\n\tSEL_MSIOF1_3_MARK = 2246,\n\tSEL_MSIOF1_4_MARK = 2247,\n\tSEL_MSIOF1_5_MARK = 2248,\n\tSEL_MSIOF1_6_MARK = 2249,\n\tSEL_TIMER_TMU_0_MARK = 2250,\n\tSEL_TIMER_TMU_1_MARK = 2251,\n\tSEL_SCIF5_0_MARK = 2252,\n\tSEL_SCIF5_1_MARK = 2253,\n\tSEL_SSP1_1_0_MARK = 2254,\n\tSEL_SSP1_1_1_MARK = 2255,\n\tSEL_SSP1_1_2_MARK = 2256,\n\tSEL_SSP1_1_3_MARK = 2257,\n\tSEL_I2C6_0_MARK = 2258,\n\tSEL_I2C6_1_MARK = 2259,\n\tSEL_I2C6_2_MARK = 2260,\n\tSEL_LBSC_0_MARK = 2261,\n\tSEL_LBSC_1_MARK = 2262,\n\tSEL_SSP1_0_0_MARK = 2263,\n\tSEL_SSP1_0_1_MARK = 2264,\n\tSEL_SSP1_0_2_MARK = 2265,\n\tSEL_SSP1_0_3_MARK = 2266,\n\tSEL_SSP1_0_4_MARK = 2267,\n\tSEL_IEBUS_0_MARK = 2268,\n\tSEL_IEBUS_1_MARK = 2269,\n\tSEL_NDF_0_MARK = 2270,\n\tSEL_NDF_1_MARK = 2271,\n\tSEL_I2C2_0_MARK = 2272,\n\tSEL_I2C2_1_MARK = 2273,\n\tSEL_SSI2_0_MARK = 2274,\n\tSEL_SSI2_1_MARK = 2275,\n\tSEL_I2C1_0_MARK = 2276,\n\tSEL_I2C1_1_MARK = 2277,\n\tSEL_SSI1_0_MARK = 2278,\n\tSEL_SSI1_1_MARK = 2279,\n\tSEL_SSI9_0_MARK = 2280,\n\tSEL_SSI9_1_MARK = 2281,\n\tSEL_HSCIF4_0_MARK = 2282,\n\tSEL_HSCIF4_1_MARK = 2283,\n\tSEL_SPEED_PULSE_0_MARK = 2284,\n\tSEL_SPEED_PULSE_1_MARK = 2285,\n\tSEL_TIMER_TMU2_0_MARK = 2286,\n\tSEL_TIMER_TMU2_1_MARK = 2287,\n\tSEL_HSCIF3_0_MARK = 2288,\n\tSEL_HSCIF3_1_MARK = 2289,\n\tSEL_HSCIF3_2_MARK = 2290,\n\tSEL_HSCIF3_3_MARK = 2291,\n\tSEL_SIMCARD_0_MARK = 2292,\n\tSEL_SIMCARD_1_MARK = 2293,\n\tSEL_SIMCARD_2_MARK = 2294,\n\tSEL_SIMCARD_3_MARK = 2295,\n\tSEL_ADGB_0_MARK = 2296,\n\tSEL_ADGB_1_MARK = 2297,\n\tSEL_ADGC_0_MARK = 2298,\n\tSEL_ADGC_1_MARK = 2299,\n\tSEL_HSCIF1_0_MARK = 2300,\n\tSEL_HSCIF1_1_MARK = 2301,\n\tSEL_SDHI2_0_MARK = 2302,\n\tSEL_SDHI2_1_MARK = 2303,\n\tSEL_SCIF4_0_MARK = 2304,\n\tSEL_SCIF4_1_MARK = 2305,\n\tSEL_SCIF4_2_MARK = 2306,\n\tSEL_HSCIF2_0_MARK = 2307,\n\tSEL_HSCIF2_1_MARK = 2308,\n\tSEL_HSCIF2_2_MARK = 2309,\n\tSEL_SCIF3_0_MARK = 2310,\n\tSEL_SCIF3_1_MARK = 2311,\n\tSEL_ETHERAVB_0_MARK = 2312,\n\tSEL_ETHERAVB_1_MARK = 2313,\n\tSEL_SCIF2_0_MARK = 2314,\n\tSEL_SCIF2_1_MARK = 2315,\n\tSEL_DRIF3_0_MARK = 2316,\n\tSEL_DRIF3_1_MARK = 2317,\n\tSEL_SCIF1_0_MARK = 2318,\n\tSEL_SCIF1_1_MARK = 2319,\n\tSEL_DRIF2_0_MARK = 2320,\n\tSEL_DRIF2_1_MARK = 2321,\n\tSEL_SCIF_0_MARK = 2322,\n\tSEL_SCIF_1_MARK = 2323,\n\tSEL_DRIF1_0_MARK = 2324,\n\tSEL_DRIF1_1_MARK = 2325,\n\tSEL_DRIF1_2_MARK = 2326,\n\tSEL_REMOCON_0_MARK = 2327,\n\tSEL_REMOCON_1_MARK = 2328,\n\tSEL_DRIF0_0_MARK = 2329,\n\tSEL_DRIF0_1_MARK = 2330,\n\tSEL_DRIF0_2_MARK = 2331,\n\tSEL_RCAN0_0_MARK = 2332,\n\tSEL_RCAN0_1_MARK = 2333,\n\tSEL_CANFD0_0_MARK = 2334,\n\tSEL_CANFD0_1_MARK = 2335,\n\tSEL_PWM6_0_MARK = 2336,\n\tSEL_PWM6_1_MARK = 2337,\n\tSEL_ADGA_0_MARK = 2338,\n\tSEL_ADGA_1_MARK = 2339,\n\tSEL_ADGA_2_MARK = 2340,\n\tSEL_ADGA_3_MARK = 2341,\n\tSEL_PWM5_0_MARK = 2342,\n\tSEL_PWM5_1_MARK = 2343,\n\tSEL_PWM4_0_MARK = 2344,\n\tSEL_PWM4_1_MARK = 2345,\n\tSEL_PWM3_0_MARK = 2346,\n\tSEL_PWM3_1_MARK = 2347,\n\tSEL_PWM2_0_MARK = 2348,\n\tSEL_PWM2_1_MARK = 2349,\n\tSEL_PWM1_0_MARK = 2350,\n\tSEL_PWM1_1_MARK = 2351,\n\tSEL_VIN4_0_MARK = 2352,\n\tSEL_VIN4_1_MARK = 2353,\n\tQSPI0_SPCLK_MARK___2 = 2354,\n\tQSPI0_SSL_MARK___2 = 2355,\n\tQSPI0_MOSI_IO0_MARK___2 = 2356,\n\tQSPI0_MISO_IO1_MARK___2 = 2357,\n\tQSPI0_IO2_MARK___2 = 2358,\n\tQSPI0_IO3_MARK___2 = 2359,\n\tQSPI1_SPCLK_MARK___2 = 2360,\n\tQSPI1_SSL_MARK___2 = 2361,\n\tQSPI1_MOSI_IO0_MARK___2 = 2362,\n\tQSPI1_MISO_IO1_MARK___2 = 2363,\n\tQSPI1_IO2_MARK___2 = 2364,\n\tQSPI1_IO3_MARK___2 = 2365,\n\tRPC_INT_MARK = 2366,\n\tRPC_WP_MARK = 2367,\n\tRPC_RESET_MARK = 2368,\n\tAVB_TX_CTL_MARK = 2369,\n\tAVB_TXC_MARK = 2370,\n\tAVB_TD0_MARK = 2371,\n\tAVB_TD1_MARK = 2372,\n\tAVB_TD2_MARK = 2373,\n\tAVB_TD3_MARK = 2374,\n\tAVB_RX_CTL_MARK = 2375,\n\tAVB_RXC_MARK = 2376,\n\tAVB_RD0_MARK = 2377,\n\tAVB_RD1_MARK = 2378,\n\tAVB_RD2_MARK = 2379,\n\tAVB_RD3_MARK = 2380,\n\tAVB_TXCREFCLK_MARK = 2381,\n\tAVB_MDIO_MARK = 2382,\n\tPRESETOUT_MARK = 2383,\n\tDU_DOTCLKIN0_MARK = 2384,\n\tDU_DOTCLKIN1_MARK = 2385,\n\tDU_DOTCLKIN2_MARK = 2386,\n\tTMS_MARK = 2387,\n\tTDO_MARK = 2388,\n\tASEBRK_MARK = 2389,\n\tMLB_REF_MARK = 2390,\n\tTDI_MARK = 2391,\n\tTCK_MARK = 2392,\n\tTRST_MARK = 2393,\n\tEXTALR_MARK = 2394,\n\tSCL0_MARK___2 = 2395,\n\tSDA0_MARK___2 = 2396,\n\tSCL3_MARK___2 = 2397,\n\tSDA3_MARK___2 = 2398,\n\tSCL5_MARK___2 = 2399,\n\tSDA5_MARK___2 = 2400,\n\tPINMUX_MARK_END___2 = 2401,\n};\n\nenum {\n\tPINMUX_RESERVED___3 = 0,\n\tPINMUX_DATA_BEGIN___3 = 1,\n\tGP_0_0_DATA___3 = 2,\n\tGP_0_1_DATA___3 = 3,\n\tGP_0_2_DATA___3 = 4,\n\tGP_0_3_DATA___3 = 5,\n\tGP_0_4_DATA___3 = 6,\n\tGP_0_5_DATA___3 = 7,\n\tGP_0_6_DATA___3 = 8,\n\tGP_0_7_DATA___3 = 9,\n\tGP_0_8_DATA___3 = 10,\n\tGP_0_9_DATA___3 = 11,\n\tGP_0_10_DATA___3 = 12,\n\tGP_0_11_DATA___3 = 13,\n\tGP_0_12_DATA___3 = 14,\n\tGP_0_13_DATA___3 = 15,\n\tGP_0_14_DATA___3 = 16,\n\tGP_0_15_DATA___3 = 17,\n\tGP_1_0_DATA___3 = 18,\n\tGP_1_1_DATA___3 = 19,\n\tGP_1_2_DATA___3 = 20,\n\tGP_1_3_DATA___3 = 21,\n\tGP_1_4_DATA___3 = 22,\n\tGP_1_5_DATA___3 = 23,\n\tGP_1_6_DATA___3 = 24,\n\tGP_1_7_DATA___3 = 25,\n\tGP_1_8_DATA___3 = 26,\n\tGP_1_9_DATA___3 = 27,\n\tGP_1_10_DATA___3 = 28,\n\tGP_1_11_DATA___3 = 29,\n\tGP_1_12_DATA___3 = 30,\n\tGP_1_13_DATA___3 = 31,\n\tGP_1_14_DATA___3 = 32,\n\tGP_1_15_DATA___3 = 33,\n\tGP_1_16_DATA___3 = 34,\n\tGP_1_17_DATA___3 = 35,\n\tGP_1_18_DATA___3 = 36,\n\tGP_1_19_DATA___3 = 37,\n\tGP_1_20_DATA___3 = 38,\n\tGP_1_21_DATA___3 = 39,\n\tGP_1_22_DATA___3 = 40,\n\tGP_1_23_DATA___3 = 41,\n\tGP_1_24_DATA___3 = 42,\n\tGP_1_25_DATA___3 = 43,\n\tGP_1_26_DATA___3 = 44,\n\tGP_1_27_DATA___3 = 45,\n\tGP_1_28_DATA___3 = 46,\n\tGP_2_0_DATA___3 = 47,\n\tGP_2_1_DATA___3 = 48,\n\tGP_2_2_DATA___3 = 49,\n\tGP_2_3_DATA___3 = 50,\n\tGP_2_4_DATA___3 = 51,\n\tGP_2_5_DATA___3 = 52,\n\tGP_2_6_DATA___3 = 53,\n\tGP_2_7_DATA___3 = 54,\n\tGP_2_8_DATA___3 = 55,\n\tGP_2_9_DATA___3 = 56,\n\tGP_2_10_DATA___3 = 57,\n\tGP_2_11_DATA___3 = 58,\n\tGP_2_12_DATA___3 = 59,\n\tGP_2_13_DATA___3 = 60,\n\tGP_2_14_DATA___3 = 61,\n\tGP_3_0_DATA___3 = 62,\n\tGP_3_1_DATA___3 = 63,\n\tGP_3_2_DATA___3 = 64,\n\tGP_3_3_DATA___3 = 65,\n\tGP_3_4_DATA___3 = 66,\n\tGP_3_5_DATA___3 = 67,\n\tGP_3_6_DATA___3 = 68,\n\tGP_3_7_DATA___3 = 69,\n\tGP_3_8_DATA___3 = 70,\n\tGP_3_9_DATA___3 = 71,\n\tGP_3_10_DATA___3 = 72,\n\tGP_3_11_DATA___3 = 73,\n\tGP_3_12_DATA___3 = 74,\n\tGP_3_13_DATA___3 = 75,\n\tGP_3_14_DATA___3 = 76,\n\tGP_3_15_DATA___3 = 77,\n\tGP_4_0_DATA___3 = 78,\n\tGP_4_1_DATA___3 = 79,\n\tGP_4_2_DATA___3 = 80,\n\tGP_4_3_DATA___3 = 81,\n\tGP_4_4_DATA___3 = 82,\n\tGP_4_5_DATA___3 = 83,\n\tGP_4_6_DATA___3 = 84,\n\tGP_4_7_DATA___3 = 85,\n\tGP_4_8_DATA___3 = 86,\n\tGP_4_9_DATA___3 = 87,\n\tGP_4_10_DATA___3 = 88,\n\tGP_4_11_DATA___3 = 89,\n\tGP_4_12_DATA___3 = 90,\n\tGP_4_13_DATA___3 = 91,\n\tGP_4_14_DATA___3 = 92,\n\tGP_4_15_DATA___3 = 93,\n\tGP_4_16_DATA___3 = 94,\n\tGP_4_17_DATA___3 = 95,\n\tGP_5_0_DATA___3 = 96,\n\tGP_5_1_DATA___3 = 97,\n\tGP_5_2_DATA___3 = 98,\n\tGP_5_3_DATA___3 = 99,\n\tGP_5_4_DATA___3 = 100,\n\tGP_5_5_DATA___3 = 101,\n\tGP_5_6_DATA___3 = 102,\n\tGP_5_7_DATA___3 = 103,\n\tGP_5_8_DATA___3 = 104,\n\tGP_5_9_DATA___3 = 105,\n\tGP_5_10_DATA___3 = 106,\n\tGP_5_11_DATA___3 = 107,\n\tGP_5_12_DATA___3 = 108,\n\tGP_5_13_DATA___3 = 109,\n\tGP_5_14_DATA___3 = 110,\n\tGP_5_15_DATA___3 = 111,\n\tGP_5_16_DATA___3 = 112,\n\tGP_5_17_DATA___3 = 113,\n\tGP_5_18_DATA___3 = 114,\n\tGP_5_19_DATA___3 = 115,\n\tGP_5_20_DATA___3 = 116,\n\tGP_5_21_DATA___2 = 117,\n\tGP_5_22_DATA___2 = 118,\n\tGP_5_23_DATA___2 = 119,\n\tGP_5_24_DATA___2 = 120,\n\tGP_5_25_DATA___2 = 121,\n\tGP_6_0_DATA___3 = 122,\n\tGP_6_1_DATA___3 = 123,\n\tGP_6_2_DATA___3 = 124,\n\tGP_6_3_DATA___3 = 125,\n\tGP_6_4_DATA___3 = 126,\n\tGP_6_5_DATA___3 = 127,\n\tGP_6_6_DATA___3 = 128,\n\tGP_6_7_DATA___3 = 129,\n\tGP_6_8_DATA___3 = 130,\n\tGP_6_9_DATA___3 = 131,\n\tGP_6_10_DATA___3 = 132,\n\tGP_6_11_DATA___3 = 133,\n\tGP_6_12_DATA___3 = 134,\n\tGP_6_13_DATA___3 = 135,\n\tGP_6_14_DATA___3 = 136,\n\tGP_6_15_DATA___3 = 137,\n\tGP_6_16_DATA___3 = 138,\n\tGP_6_17_DATA___3 = 139,\n\tGP_6_18_DATA___3 = 140,\n\tGP_6_19_DATA___3 = 141,\n\tGP_6_20_DATA___3 = 142,\n\tGP_6_21_DATA___2 = 143,\n\tGP_6_22_DATA___2 = 144,\n\tGP_6_23_DATA___2 = 145,\n\tGP_6_24_DATA___2 = 146,\n\tGP_6_25_DATA___2 = 147,\n\tGP_6_26_DATA___2 = 148,\n\tGP_6_27_DATA___2 = 149,\n\tGP_6_28_DATA___2 = 150,\n\tGP_6_29_DATA___2 = 151,\n\tGP_6_30_DATA___2 = 152,\n\tGP_6_31_DATA___2 = 153,\n\tGP_7_0_DATA___3 = 154,\n\tGP_7_1_DATA___3 = 155,\n\tGP_7_2_DATA___3 = 156,\n\tGP_7_3_DATA___3 = 157,\n\tPINMUX_DATA_END___3 = 158,\n\tPINMUX_FUNCTION_BEGIN___3 = 159,\n\tGP_0_0_FN___3 = 160,\n\tGP_0_1_FN___3 = 161,\n\tGP_0_2_FN___3 = 162,\n\tGP_0_3_FN___3 = 163,\n\tGP_0_4_FN___3 = 164,\n\tGP_0_5_FN___3 = 165,\n\tGP_0_6_FN___3 = 166,\n\tGP_0_7_FN___3 = 167,\n\tGP_0_8_FN___3 = 168,\n\tGP_0_9_FN___3 = 169,\n\tGP_0_10_FN___3 = 170,\n\tGP_0_11_FN___3 = 171,\n\tGP_0_12_FN___3 = 172,\n\tGP_0_13_FN___3 = 173,\n\tGP_0_14_FN___3 = 174,\n\tGP_0_15_FN___3 = 175,\n\tGP_1_0_FN___3 = 176,\n\tGP_1_1_FN___3 = 177,\n\tGP_1_2_FN___3 = 178,\n\tGP_1_3_FN___3 = 179,\n\tGP_1_4_FN___3 = 180,\n\tGP_1_5_FN___3 = 181,\n\tGP_1_6_FN___3 = 182,\n\tGP_1_7_FN___3 = 183,\n\tGP_1_8_FN___3 = 184,\n\tGP_1_9_FN___3 = 185,\n\tGP_1_10_FN___3 = 186,\n\tGP_1_11_FN___3 = 187,\n\tGP_1_12_FN___3 = 188,\n\tGP_1_13_FN___3 = 189,\n\tGP_1_14_FN___3 = 190,\n\tGP_1_15_FN___3 = 191,\n\tGP_1_16_FN___3 = 192,\n\tGP_1_17_FN___3 = 193,\n\tGP_1_18_FN___3 = 194,\n\tGP_1_19_FN___3 = 195,\n\tGP_1_20_FN___3 = 196,\n\tGP_1_21_FN___3 = 197,\n\tGP_1_22_FN___3 = 198,\n\tGP_1_23_FN___3 = 199,\n\tGP_1_24_FN___3 = 200,\n\tGP_1_25_FN___3 = 201,\n\tGP_1_26_FN___3 = 202,\n\tGP_1_27_FN___3 = 203,\n\tGP_1_28_FN___3 = 204,\n\tGP_2_0_FN___3 = 205,\n\tGP_2_1_FN___3 = 206,\n\tGP_2_2_FN___3 = 207,\n\tGP_2_3_FN___3 = 208,\n\tGP_2_4_FN___3 = 209,\n\tGP_2_5_FN___3 = 210,\n\tGP_2_6_FN___3 = 211,\n\tGP_2_7_FN___3 = 212,\n\tGP_2_8_FN___3 = 213,\n\tGP_2_9_FN___3 = 214,\n\tGP_2_10_FN___3 = 215,\n\tGP_2_11_FN___3 = 216,\n\tGP_2_12_FN___3 = 217,\n\tGP_2_13_FN___3 = 218,\n\tGP_2_14_FN___3 = 219,\n\tGP_3_0_FN___3 = 220,\n\tGP_3_1_FN___3 = 221,\n\tGP_3_2_FN___3 = 222,\n\tGP_3_3_FN___3 = 223,\n\tGP_3_4_FN___3 = 224,\n\tGP_3_5_FN___3 = 225,\n\tGP_3_6_FN___3 = 226,\n\tGP_3_7_FN___3 = 227,\n\tGP_3_8_FN___3 = 228,\n\tGP_3_9_FN___3 = 229,\n\tGP_3_10_FN___3 = 230,\n\tGP_3_11_FN___3 = 231,\n\tGP_3_12_FN___3 = 232,\n\tGP_3_13_FN___3 = 233,\n\tGP_3_14_FN___3 = 234,\n\tGP_3_15_FN___3 = 235,\n\tGP_4_0_FN___3 = 236,\n\tGP_4_1_FN___3 = 237,\n\tGP_4_2_FN___3 = 238,\n\tGP_4_3_FN___3 = 239,\n\tGP_4_4_FN___3 = 240,\n\tGP_4_5_FN___3 = 241,\n\tGP_4_6_FN___3 = 242,\n\tGP_4_7_FN___3 = 243,\n\tGP_4_8_FN___3 = 244,\n\tGP_4_9_FN___3 = 245,\n\tGP_4_10_FN___3 = 246,\n\tGP_4_11_FN___3 = 247,\n\tGP_4_12_FN___3 = 248,\n\tGP_4_13_FN___3 = 249,\n\tGP_4_14_FN___3 = 250,\n\tGP_4_15_FN___3 = 251,\n\tGP_4_16_FN___3 = 252,\n\tGP_4_17_FN___3 = 253,\n\tGP_5_0_FN___3 = 254,\n\tGP_5_1_FN___3 = 255,\n\tGP_5_2_FN___3 = 256,\n\tGP_5_3_FN___3 = 257,\n\tGP_5_4_FN___3 = 258,\n\tGP_5_5_FN___3 = 259,\n\tGP_5_6_FN___3 = 260,\n\tGP_5_7_FN___3 = 261,\n\tGP_5_8_FN___3 = 262,\n\tGP_5_9_FN___3 = 263,\n\tGP_5_10_FN___3 = 264,\n\tGP_5_11_FN___3 = 265,\n\tGP_5_12_FN___3 = 266,\n\tGP_5_13_FN___3 = 267,\n\tGP_5_14_FN___3 = 268,\n\tGP_5_15_FN___3 = 269,\n\tGP_5_16_FN___3 = 270,\n\tGP_5_17_FN___3 = 271,\n\tGP_5_18_FN___3 = 272,\n\tGP_5_19_FN___3 = 273,\n\tGP_5_20_FN___3 = 274,\n\tGP_5_21_FN___2 = 275,\n\tGP_5_22_FN___2 = 276,\n\tGP_5_23_FN___2 = 277,\n\tGP_5_24_FN___2 = 278,\n\tGP_5_25_FN___2 = 279,\n\tGP_6_0_FN___3 = 280,\n\tGP_6_1_FN___3 = 281,\n\tGP_6_2_FN___3 = 282,\n\tGP_6_3_FN___3 = 283,\n\tGP_6_4_FN___3 = 284,\n\tGP_6_5_FN___3 = 285,\n\tGP_6_6_FN___3 = 286,\n\tGP_6_7_FN___3 = 287,\n\tGP_6_8_FN___3 = 288,\n\tGP_6_9_FN___3 = 289,\n\tGP_6_10_FN___3 = 290,\n\tGP_6_11_FN___3 = 291,\n\tGP_6_12_FN___3 = 292,\n\tGP_6_13_FN___3 = 293,\n\tGP_6_14_FN___3 = 294,\n\tGP_6_15_FN___3 = 295,\n\tGP_6_16_FN___3 = 296,\n\tGP_6_17_FN___3 = 297,\n\tGP_6_18_FN___3 = 298,\n\tGP_6_19_FN___3 = 299,\n\tGP_6_20_FN___3 = 300,\n\tGP_6_21_FN___2 = 301,\n\tGP_6_22_FN___2 = 302,\n\tGP_6_23_FN___2 = 303,\n\tGP_6_24_FN___2 = 304,\n\tGP_6_25_FN___2 = 305,\n\tGP_6_26_FN___2 = 306,\n\tGP_6_27_FN___2 = 307,\n\tGP_6_28_FN___2 = 308,\n\tGP_6_29_FN___2 = 309,\n\tGP_6_30_FN___2 = 310,\n\tGP_6_31_FN___2 = 311,\n\tGP_7_0_FN___3 = 312,\n\tGP_7_1_FN___3 = 313,\n\tGP_7_2_FN___3 = 314,\n\tGP_7_3_FN___3 = 315,\n\tFN_CLKOUT___2 = 316,\n\tFN_MSIOF0_RXD___3 = 317,\n\tFN_MSIOF0_TXD___3 = 318,\n\tFN_MSIOF0_SCK___3 = 319,\n\tFN_SSI_SDATA5___2 = 320,\n\tFN_SSI_WS5___2 = 321,\n\tFN_SSI_SCK5___2 = 322,\n\tFN_GP7_03___2 = 323,\n\tFN_GP7_02___2 = 324,\n\tFN_AVS2___2 = 325,\n\tFN_AVS1___3 = 326,\n\tFN_IP0_3_0___2 = 327,\n\tFN_AVB_MDC___2 = 328,\n\tFN_MSIOF2_SS2_C___2 = 329,\n\tFN_IP1_3_0___2 = 330,\n\tFN_IRQ2___2 = 331,\n\tFN_QCPV_QDE___2 = 332,\n\tFN_DU_EXODDF_DU_ODDF_DISP_CDE___2 = 333,\n\tFN_VI4_DATA2_B___2 = 334,\n\tFN_MSIOF3_SYNC_E___2 = 335,\n\tFN_PWM3_B___3 = 336,\n\tFN_IP2_3_0___2 = 337,\n\tFN_A1___2 = 338,\n\tFN_LCDOUT17___2 = 339,\n\tFN_MSIOF3_TXD_B___2 = 340,\n\tFN_VI4_DATA9___2 = 341,\n\tFN_DU_DB1___2 = 342,\n\tFN_PWM4_A___2 = 343,\n\tFN_IP3_3_0___2 = 344,\n\tFN_A9___2 = 345,\n\tFN_MSIOF2_SCK_A___2 = 346,\n\tFN_CTS4_N_B___2 = 347,\n\tFN_VI5_VSYNC_N___2 = 348,\n\tFN_IP0_7_4___2 = 349,\n\tFN_AVB_MAGIC___2 = 350,\n\tFN_MSIOF2_SS1_C___2 = 351,\n\tFN_SCK4_A___2 = 352,\n\tFN_IP1_7_4___2 = 353,\n\tFN_IRQ3___2 = 354,\n\tFN_QSTVB_QVE___2 = 355,\n\tFN_DU_DOTCLKOUT1___2 = 356,\n\tFN_VI4_DATA3_B___2 = 357,\n\tFN_MSIOF3_SCK_E___2 = 358,\n\tFN_PWM4_B___2 = 359,\n\tFN_IP2_7_4___2 = 360,\n\tFN_A2___2 = 361,\n\tFN_LCDOUT18___2 = 362,\n\tFN_MSIOF3_SCK_B___2 = 363,\n\tFN_VI4_DATA10___2 = 364,\n\tFN_DU_DB2___2 = 365,\n\tFN_PWM5_A___2 = 366,\n\tFN_IP3_7_4___2 = 367,\n\tFN_A10___2 = 368,\n\tFN_MSIOF2_RXD_A___2 = 369,\n\tFN_RTS4_N_B___2 = 370,\n\tFN_VI5_HSYNC_N___2 = 371,\n\tFN_IP0_11_8___2 = 372,\n\tFN_AVB_PHY_INT___2 = 373,\n\tFN_MSIOF2_SYNC_C___2 = 374,\n\tFN_RX4_A___2 = 375,\n\tFN_IP1_11_8___2 = 376,\n\tFN_IRQ4___2 = 377,\n\tFN_QSTH_QHS___2 = 378,\n\tFN_DU_EXHSYNC_DU_HSYNC___2 = 379,\n\tFN_VI4_DATA4_B___2 = 380,\n\tFN_MSIOF3_RXD_E___2 = 381,\n\tFN_PWM5_B___2 = 382,\n\tFN_IP2_11_8___2 = 383,\n\tFN_A3___2 = 384,\n\tFN_LCDOUT19___2 = 385,\n\tFN_MSIOF3_RXD_B___2 = 386,\n\tFN_VI4_DATA11___2 = 387,\n\tFN_DU_DB3___2 = 388,\n\tFN_PWM6_A___2 = 389,\n\tFN_IP3_11_8___2 = 390,\n\tFN_A11___2 = 391,\n\tFN_TX3_B___3 = 392,\n\tFN_MSIOF2_TXD_A___2 = 393,\n\tFN_HTX4_B___2 = 394,\n\tFN_HSCK4___2 = 395,\n\tFN_VI5_FIELD___2 = 396,\n\tFN_SCL6_A___2 = 397,\n\tFN_AVB_AVTP_CAPTURE_B___2 = 398,\n\tFN_PWM2_B___2 = 399,\n\tFN_IP0_15_12___2 = 400,\n\tFN_AVB_LINK___2 = 401,\n\tFN_MSIOF2_SCK_C___2 = 402,\n\tFN_TX4_A___2 = 403,\n\tFN_IP1_15_12___2 = 404,\n\tFN_IRQ5___3 = 405,\n\tFN_QSTB_QHE___2 = 406,\n\tFN_DU_EXVSYNC_DU_VSYNC___2 = 407,\n\tFN_VI4_DATA5_B___2 = 408,\n\tFN_FSCLKST2_N_B = 409,\n\tFN_MSIOF3_TXD_E___2 = 410,\n\tFN_PWM6_B___2 = 411,\n\tFN_IP2_15_12___2 = 412,\n\tFN_A4___2 = 413,\n\tFN_LCDOUT20___2 = 414,\n\tFN_MSIOF3_SS1_B___2 = 415,\n\tFN_VI4_DATA12___2 = 416,\n\tFN_VI5_DATA12___2 = 417,\n\tFN_DU_DB4___2 = 418,\n\tFN_IP3_15_12___2 = 419,\n\tFN_A12___2 = 420,\n\tFN_LCDOUT12___2 = 421,\n\tFN_MSIOF3_SCK_C___2 = 422,\n\tFN_HRX4_A___2 = 423,\n\tFN_VI5_DATA8___2 = 424,\n\tFN_DU_DG4___2 = 425,\n\tFN_IP0_19_16___2 = 426,\n\tFN_AVB_AVTP_MATCH_A___2 = 427,\n\tFN_MSIOF2_RXD_C___2 = 428,\n\tFN_CTS4_N_A___2 = 429,\n\tFN_FSCLKST2_N_A = 430,\n\tFN_IP1_19_16___2 = 431,\n\tFN_PWM0___3 = 432,\n\tFN_AVB_AVTP_PPS___2 = 433,\n\tFN_VI4_DATA6_B___2 = 434,\n\tFN_IECLK_B___2 = 435,\n\tFN_IP2_19_16___2 = 436,\n\tFN_A5___2 = 437,\n\tFN_LCDOUT21___2 = 438,\n\tFN_MSIOF3_SS2_B___2 = 439,\n\tFN_SCK4_B___2 = 440,\n\tFN_VI4_DATA13___2 = 441,\n\tFN_VI5_DATA13___2 = 442,\n\tFN_DU_DB5___2 = 443,\n\tFN_IP3_19_16___2 = 444,\n\tFN_A13___2 = 445,\n\tFN_LCDOUT13___2 = 446,\n\tFN_MSIOF3_SYNC_C___2 = 447,\n\tFN_HTX4_A___2 = 448,\n\tFN_VI5_DATA9___2 = 449,\n\tFN_DU_DG5___2 = 450,\n\tFN_IP0_23_20___2 = 451,\n\tFN_AVB_AVTP_CAPTURE_A___2 = 452,\n\tFN_MSIOF2_TXD_C___2 = 453,\n\tFN_RTS4_N_A___2 = 454,\n\tFN_IP1_23_20___2 = 455,\n\tFN_PWM1_A___3 = 456,\n\tFN_HRX3_D___2 = 457,\n\tFN_VI4_DATA7_B___2 = 458,\n\tFN_IERX_B___2 = 459,\n\tFN_IP2_23_20___2 = 460,\n\tFN_A6___2 = 461,\n\tFN_LCDOUT22___2 = 462,\n\tFN_MSIOF2_SS1_A___2 = 463,\n\tFN_RX4_B___2 = 464,\n\tFN_VI4_DATA14___2 = 465,\n\tFN_VI5_DATA14___2 = 466,\n\tFN_DU_DB6___2 = 467,\n\tFN_IP3_23_20___2 = 468,\n\tFN_A14___2 = 469,\n\tFN_LCDOUT14___2 = 470,\n\tFN_MSIOF3_RXD_C___2 = 471,\n\tFN_HCTS4_N___2 = 472,\n\tFN_VI5_DATA10___2 = 473,\n\tFN_DU_DG6___2 = 474,\n\tFN_IP0_27_24___2 = 475,\n\tFN_IRQ0___2 = 476,\n\tFN_QPOLB___2 = 477,\n\tFN_DU_CDE___2 = 478,\n\tFN_VI4_DATA0_B___2 = 479,\n\tFN_CAN0_TX_B___2 = 480,\n\tFN_CANFD0_TX_B___2 = 481,\n\tFN_MSIOF3_SS2_E___2 = 482,\n\tFN_IP1_27_24___2 = 483,\n\tFN_PWM2_A___2 = 484,\n\tFN_HTX3_D___2 = 485,\n\tFN_IETX_B___2 = 486,\n\tFN_IP2_27_24___2 = 487,\n\tFN_A7___2 = 488,\n\tFN_LCDOUT23___2 = 489,\n\tFN_MSIOF2_SS2_A___2 = 490,\n\tFN_TX4_B___2 = 491,\n\tFN_VI4_DATA15___2 = 492,\n\tFN_VI5_DATA15___2 = 493,\n\tFN_DU_DB7___2 = 494,\n\tFN_IP3_27_24___2 = 495,\n\tFN_A15___2 = 496,\n\tFN_LCDOUT15___2 = 497,\n\tFN_MSIOF3_TXD_C___2 = 498,\n\tFN_HRTS4_N___2 = 499,\n\tFN_VI5_DATA11___2 = 500,\n\tFN_DU_DG7___2 = 501,\n\tFN_IP0_31_28___2 = 502,\n\tFN_IRQ1___2 = 503,\n\tFN_QPOLA___2 = 504,\n\tFN_DU_DISP___2 = 505,\n\tFN_VI4_DATA1_B___2 = 506,\n\tFN_CAN0_RX_B___2 = 507,\n\tFN_CANFD0_RX_B___2 = 508,\n\tFN_MSIOF3_SS1_E___2 = 509,\n\tFN_IP1_31_28___2 = 510,\n\tFN_A0___2 = 511,\n\tFN_LCDOUT16___2 = 512,\n\tFN_MSIOF3_SYNC_B___2 = 513,\n\tFN_VI4_DATA8___2 = 514,\n\tFN_DU_DB0___2 = 515,\n\tFN_PWM3_A___3 = 516,\n\tFN_IP2_31_28___2 = 517,\n\tFN_A8___2 = 518,\n\tFN_RX3_B___3 = 519,\n\tFN_MSIOF2_SYNC_A___2 = 520,\n\tFN_HRX4_B___2 = 521,\n\tFN_SDA6_A___2 = 522,\n\tFN_AVB_AVTP_MATCH_B___2 = 523,\n\tFN_PWM1_B___3 = 524,\n\tFN_IP3_31_28___2 = 525,\n\tFN_A16___2 = 526,\n\tFN_LCDOUT8___2 = 527,\n\tFN_VI4_FIELD___2 = 528,\n\tFN_DU_DG0___2 = 529,\n\tFN_IP4_3_0___2 = 530,\n\tFN_A17___2 = 531,\n\tFN_LCDOUT9___2 = 532,\n\tFN_VI4_VSYNC_N___2 = 533,\n\tFN_DU_DG1___2 = 534,\n\tFN_IP5_3_0___2 = 535,\n\tFN_WE0_N___2 = 536,\n\tFN_MSIOF3_TXD_D___2 = 537,\n\tFN_CTS3_N___2 = 538,\n\tFN_HCTS3_N___2 = 539,\n\tFN_SCL6_B___2 = 540,\n\tFN_CAN_CLK___3 = 541,\n\tFN_IECLK_A___2 = 542,\n\tFN_IP6_3_0___2 = 543,\n\tFN_D5___2 = 544,\n\tFN_MSIOF2_SYNC_B___2 = 545,\n\tFN_VI4_DATA21___2 = 546,\n\tFN_VI5_DATA5___2 = 547,\n\tFN_IP7_3_0___2 = 548,\n\tFN_D13___2 = 549,\n\tFN_LCDOUT5___2 = 550,\n\tFN_MSIOF2_SS2_D___2 = 551,\n\tFN_TX4_C___2 = 552,\n\tFN_VI4_DATA5_A___2 = 553,\n\tFN_DU_DR5___2 = 554,\n\tFN_IP4_7_4___2 = 555,\n\tFN_A18___2 = 556,\n\tFN_LCDOUT10___2 = 557,\n\tFN_VI4_HSYNC_N___2 = 558,\n\tFN_DU_DG2___2 = 559,\n\tFN_IP5_7_4___2 = 560,\n\tFN_WE1_N___2 = 561,\n\tFN_MSIOF3_SS1_D___2 = 562,\n\tFN_RTS3_N___2 = 563,\n\tFN_HRTS3_N___2 = 564,\n\tFN_SDA6_B___2 = 565,\n\tFN_CAN1_RX___2 = 566,\n\tFN_CANFD1_RX___3 = 567,\n\tFN_IERX_A___2 = 568,\n\tFN_IP6_7_4___2 = 569,\n\tFN_D6___2 = 570,\n\tFN_MSIOF2_RXD_B___2 = 571,\n\tFN_VI4_DATA22___2 = 572,\n\tFN_VI5_DATA6___2 = 573,\n\tFN_IP7_7_4___2 = 574,\n\tFN_D14___2 = 575,\n\tFN_LCDOUT6___2 = 576,\n\tFN_MSIOF3_SS1_A___2 = 577,\n\tFN_HRX3_C___2 = 578,\n\tFN_VI4_DATA6_A___2 = 579,\n\tFN_DU_DR6___2 = 580,\n\tFN_SCL6_C___2 = 581,\n\tFN_IP4_11_8___2 = 582,\n\tFN_A19___2 = 583,\n\tFN_LCDOUT11___2 = 584,\n\tFN_VI4_CLKENB___2 = 585,\n\tFN_DU_DG3___2 = 586,\n\tFN_IP5_11_8___2 = 587,\n\tFN_EX_WAIT0_A___2 = 588,\n\tFN_QCLK___2 = 589,\n\tFN_VI4_CLK___2 = 590,\n\tFN_DU_DOTCLKOUT0___2 = 591,\n\tFN_IP6_11_8___2 = 592,\n\tFN_D7___2 = 593,\n\tFN_MSIOF2_TXD_B___2 = 594,\n\tFN_VI4_DATA23___2 = 595,\n\tFN_VI5_DATA7___2 = 596,\n\tFN_IP7_11_8___2 = 597,\n\tFN_D15___2 = 598,\n\tFN_LCDOUT7___2 = 599,\n\tFN_MSIOF3_SS2_A___2 = 600,\n\tFN_HTX3_C___2 = 601,\n\tFN_VI4_DATA7_A___2 = 602,\n\tFN_DU_DR7___2 = 603,\n\tFN_SDA6_C___2 = 604,\n\tFN_IP4_15_12___2 = 605,\n\tFN_CS0_N___2 = 606,\n\tFN_VI5_CLKENB___2 = 607,\n\tFN_IP5_15_12___2 = 608,\n\tFN_D0___2 = 609,\n\tFN_MSIOF2_SS1_B___2 = 610,\n\tFN_MSIOF3_SCK_A___2 = 611,\n\tFN_VI4_DATA16___2 = 612,\n\tFN_VI5_DATA0___2 = 613,\n\tFN_IP6_15_12___2 = 614,\n\tFN_D8___2 = 615,\n\tFN_LCDOUT0___2 = 616,\n\tFN_MSIOF2_SCK_D___2 = 617,\n\tFN_SCK4_C___2 = 618,\n\tFN_VI4_DATA0_A___2 = 619,\n\tFN_DU_DR0___2 = 620,\n\tFN_IP4_19_16___2 = 621,\n\tFN_CS1_N___2 = 622,\n\tFN_VI5_CLK___2 = 623,\n\tFN_EX_WAIT0_B___2 = 624,\n\tFN_IP5_19_16___2 = 625,\n\tFN_D1___2 = 626,\n\tFN_MSIOF2_SS2_B___2 = 627,\n\tFN_MSIOF3_SYNC_A___2 = 628,\n\tFN_VI4_DATA17___2 = 629,\n\tFN_VI5_DATA1___2 = 630,\n\tFN_IP6_19_16___2 = 631,\n\tFN_D9___2 = 632,\n\tFN_LCDOUT1___2 = 633,\n\tFN_MSIOF2_SYNC_D___2 = 634,\n\tFN_VI4_DATA1_A___2 = 635,\n\tFN_DU_DR1___2 = 636,\n\tFN_IP7_19_16___2 = 637,\n\tFN_SD0_CLK___2 = 638,\n\tFN_MSIOF1_SCK_E___2 = 639,\n\tFN_STP_OPWM_0_B___2 = 640,\n\tFN_IP4_23_20___2 = 641,\n\tFN_BS_N___2 = 642,\n\tFN_QSTVA_QVS___2 = 643,\n\tFN_MSIOF3_SCK_D___2 = 644,\n\tFN_SCK3___2 = 645,\n\tFN_HSCK3___2 = 646,\n\tFN_CAN1_TX___2 = 647,\n\tFN_CANFD1_TX___3 = 648,\n\tFN_IETX_A___2 = 649,\n\tFN_IP5_23_20___2 = 650,\n\tFN_D2___2 = 651,\n\tFN_MSIOF3_RXD_A___2 = 652,\n\tFN_VI4_DATA18___2 = 653,\n\tFN_VI5_DATA2___2 = 654,\n\tFN_IP6_23_20___2 = 655,\n\tFN_D10___2 = 656,\n\tFN_LCDOUT2___2 = 657,\n\tFN_MSIOF2_RXD_D___2 = 658,\n\tFN_HRX3_B___3 = 659,\n\tFN_VI4_DATA2_A___2 = 660,\n\tFN_CTS4_N_C___2 = 661,\n\tFN_DU_DR2___2 = 662,\n\tFN_IP7_23_20___2 = 663,\n\tFN_SD0_CMD___2 = 664,\n\tFN_MSIOF1_SYNC_E___2 = 665,\n\tFN_STP_IVCXO27_0_B___2 = 666,\n\tFN_IP4_27_24___2 = 667,\n\tFN_RD_N___2 = 668,\n\tFN_MSIOF3_SYNC_D___2 = 669,\n\tFN_RX3_A___3 = 670,\n\tFN_HRX3_A___3 = 671,\n\tFN_CAN0_TX_A___2 = 672,\n\tFN_CANFD0_TX_A___2 = 673,\n\tFN_IP5_27_24___2 = 674,\n\tFN_D3___2 = 675,\n\tFN_MSIOF3_TXD_A___2 = 676,\n\tFN_VI4_DATA19___2 = 677,\n\tFN_VI5_DATA3___2 = 678,\n\tFN_IP6_27_24___2 = 679,\n\tFN_D11___2 = 680,\n\tFN_LCDOUT3___2 = 681,\n\tFN_MSIOF2_TXD_D___2 = 682,\n\tFN_HTX3_B___3 = 683,\n\tFN_VI4_DATA3_A___2 = 684,\n\tFN_RTS4_N_C___2 = 685,\n\tFN_DU_DR3___2 = 686,\n\tFN_IP7_27_24___2 = 687,\n\tFN_SD0_DAT0___2 = 688,\n\tFN_MSIOF1_RXD_E___2 = 689,\n\tFN_TS_SCK0_B___2 = 690,\n\tFN_STP_ISCLK_0_B___2 = 691,\n\tFN_IP4_31_28___2 = 692,\n\tFN_RD_WR_N___2 = 693,\n\tFN_MSIOF3_RXD_D___2 = 694,\n\tFN_TX3_A___3 = 695,\n\tFN_HTX3_A___3 = 696,\n\tFN_CAN0_RX_A___2 = 697,\n\tFN_CANFD0_RX_A___2 = 698,\n\tFN_IP5_31_28___2 = 699,\n\tFN_D4___2 = 700,\n\tFN_MSIOF2_SCK_B___2 = 701,\n\tFN_VI4_DATA20___2 = 702,\n\tFN_VI5_DATA4___2 = 703,\n\tFN_IP6_31_28___2 = 704,\n\tFN_D12___2 = 705,\n\tFN_LCDOUT4___2 = 706,\n\tFN_MSIOF2_SS1_D___2 = 707,\n\tFN_RX4_C___2 = 708,\n\tFN_VI4_DATA4_A___2 = 709,\n\tFN_DU_DR4___2 = 710,\n\tFN_IP7_31_28___2 = 711,\n\tFN_SD0_DAT1___2 = 712,\n\tFN_MSIOF1_TXD_E___2 = 713,\n\tFN_TS_SPSYNC0_B___2 = 714,\n\tFN_STP_ISSYNC_0_B___2 = 715,\n\tFN_IP8_3_0___2 = 716,\n\tFN_SD0_DAT2___2 = 717,\n\tFN_MSIOF1_SS1_E___2 = 718,\n\tFN_TS_SDAT0_B___2 = 719,\n\tFN_STP_ISD_0_B___2 = 720,\n\tFN_IP9_3_0___2 = 721,\n\tFN_SD2_CLK___2 = 722,\n\tFN_NFDATA8___2 = 723,\n\tFN_IP10_3_0___2 = 724,\n\tFN_SD3_CMD___2 = 725,\n\tFN_NFRE_N___2 = 726,\n\tFN_IP11_3_0___2 = 727,\n\tFN_SD3_DAT7___2 = 728,\n\tFN_SD3_WP___2 = 729,\n\tFN_NFDATA7___2 = 730,\n\tFN_IP8_7_4___2 = 731,\n\tFN_SD0_DAT3___2 = 732,\n\tFN_MSIOF1_SS2_E___2 = 733,\n\tFN_TS_SDEN0_B___2 = 734,\n\tFN_STP_ISEN_0_B___2 = 735,\n\tFN_IP9_7_4___2 = 736,\n\tFN_SD2_CMD___2 = 737,\n\tFN_NFDATA9___2 = 738,\n\tFN_IP10_7_4___2 = 739,\n\tFN_SD3_DAT0___2 = 740,\n\tFN_NFDATA0___2 = 741,\n\tFN_IP11_7_4___2 = 742,\n\tFN_SD3_DS___2 = 743,\n\tFN_NFCLE___2 = 744,\n\tFN_IP8_11_8___2 = 745,\n\tFN_SD1_CLK___2 = 746,\n\tFN_MSIOF1_SCK_G___2 = 747,\n\tFN_SIM0_CLK_A___2 = 748,\n\tFN_IP9_11_8___2 = 749,\n\tFN_SD2_DAT0___2 = 750,\n\tFN_NFDATA10___2 = 751,\n\tFN_IP10_11_8___2 = 752,\n\tFN_SD3_DAT1___2 = 753,\n\tFN_NFDATA1___2 = 754,\n\tFN_IP11_11_8___2 = 755,\n\tFN_SD0_CD___2 = 756,\n\tFN_NFDATA14_A___2 = 757,\n\tFN_SCL2_B___2 = 758,\n\tFN_SIM0_RST_A___2 = 759,\n\tFN_IP8_15_12___2 = 760,\n\tFN_SD1_CMD___2 = 761,\n\tFN_MSIOF1_SYNC_G___2 = 762,\n\tFN_NFCE_N_B___2 = 763,\n\tFN_SIM0_D_A___2 = 764,\n\tFN_STP_IVCXO27_1_B___2 = 765,\n\tFN_IP9_15_12___2 = 766,\n\tFN_SD2_DAT1___2 = 767,\n\tFN_NFDATA11___2 = 768,\n\tFN_IP10_15_12___2 = 769,\n\tFN_SD3_DAT2___2 = 770,\n\tFN_NFDATA2___2 = 771,\n\tFN_IP11_15_12___2 = 772,\n\tFN_SD0_WP___2 = 773,\n\tFN_NFDATA15_A___2 = 774,\n\tFN_SDA2_B___2 = 775,\n\tFN_IP8_19_16___2 = 776,\n\tFN_SD1_DAT0___2 = 777,\n\tFN_SD2_DAT4___2 = 778,\n\tFN_MSIOF1_RXD_G___2 = 779,\n\tFN_NFWP_N_B___2 = 780,\n\tFN_TS_SCK1_B___2 = 781,\n\tFN_STP_ISCLK_1_B___2 = 782,\n\tFN_IP9_19_16___2 = 783,\n\tFN_SD2_DAT2___2 = 784,\n\tFN_NFDATA12___2 = 785,\n\tFN_IP10_19_16___2 = 786,\n\tFN_SD3_DAT3___2 = 787,\n\tFN_NFDATA3___2 = 788,\n\tFN_IP11_19_16___2 = 789,\n\tFN_SD1_CD___2 = 790,\n\tFN_NFRB_N_A___2 = 791,\n\tFN_SIM0_CLK_B___2 = 792,\n\tFN_IP8_23_20___2 = 793,\n\tFN_SD1_DAT1___2 = 794,\n\tFN_SD2_DAT5___2 = 795,\n\tFN_MSIOF1_TXD_G___2 = 796,\n\tFN_NFDATA14_B___2 = 797,\n\tFN_TS_SPSYNC1_B___2 = 798,\n\tFN_STP_ISSYNC_1_B___2 = 799,\n\tFN_IP9_23_20___2 = 800,\n\tFN_SD2_DAT3___2 = 801,\n\tFN_NFDATA13___2 = 802,\n\tFN_IP10_23_20___2 = 803,\n\tFN_SD3_DAT4___2 = 804,\n\tFN_SD2_CD_A___2 = 805,\n\tFN_NFDATA4___2 = 806,\n\tFN_IP11_23_20___2 = 807,\n\tFN_SD1_WP___2 = 808,\n\tFN_NFCE_N_A___2 = 809,\n\tFN_SIM0_D_B___2 = 810,\n\tFN_IP8_27_24___2 = 811,\n\tFN_SD1_DAT2___2 = 812,\n\tFN_SD2_DAT6___2 = 813,\n\tFN_MSIOF1_SS1_G___2 = 814,\n\tFN_NFDATA15_B___2 = 815,\n\tFN_TS_SDAT1_B___2 = 816,\n\tFN_STP_ISD_1_B___2 = 817,\n\tFN_IP9_27_24___2 = 818,\n\tFN_SD2_DS___2 = 819,\n\tFN_NFALE___2 = 820,\n\tFN_SATA_DEVSLP_B = 821,\n\tFN_IP10_27_24___2 = 822,\n\tFN_SD3_DAT5___2 = 823,\n\tFN_SD2_WP_A___2 = 824,\n\tFN_NFDATA5___2 = 825,\n\tFN_IP11_27_24___2 = 826,\n\tFN_SCK0___3 = 827,\n\tFN_HSCK1_B___3 = 828,\n\tFN_MSIOF1_SS2_B___2 = 829,\n\tFN_AUDIO_CLKC_B___2 = 830,\n\tFN_SDA2_A___2 = 831,\n\tFN_SIM0_RST_B___2 = 832,\n\tFN_STP_OPWM_0_C___2 = 833,\n\tFN_RIF0_CLK_B___2 = 834,\n\tFN_ADICHS2___2 = 835,\n\tFN_SCK5_B___2 = 836,\n\tFN_IP8_31_28___2 = 837,\n\tFN_SD1_DAT3___2 = 838,\n\tFN_SD2_DAT7___2 = 839,\n\tFN_MSIOF1_SS2_G___2 = 840,\n\tFN_NFRB_N_B___2 = 841,\n\tFN_TS_SDEN1_B___2 = 842,\n\tFN_STP_ISEN_1_B___2 = 843,\n\tFN_IP9_31_28___2 = 844,\n\tFN_SD3_CLK___2 = 845,\n\tFN_NFWE_N___2 = 846,\n\tFN_IP10_31_28___2 = 847,\n\tFN_SD3_DAT6___2 = 848,\n\tFN_SD3_CD___2 = 849,\n\tFN_NFDATA6___2 = 850,\n\tFN_IP11_31_28___2 = 851,\n\tFN_RX0___3 = 852,\n\tFN_HRX1_B___3 = 853,\n\tFN_TS_SCK0_C___2 = 854,\n\tFN_STP_ISCLK_0_C___2 = 855,\n\tFN_RIF0_D0_B___2 = 856,\n\tFN_IP12_3_0___2 = 857,\n\tFN_TX0___3 = 858,\n\tFN_HTX1_B___3 = 859,\n\tFN_TS_SPSYNC0_C___2 = 860,\n\tFN_STP_ISSYNC_0_C___2 = 861,\n\tFN_RIF0_D1_B___2 = 862,\n\tFN_IP13_3_0___2 = 863,\n\tFN_TX2_A___2 = 864,\n\tFN_SD2_CD_B___2 = 865,\n\tFN_SCL1_A___2 = 866,\n\tFN_FMCLK_A___2 = 867,\n\tFN_RIF1_D1_C___2 = 868,\n\tFN_FSO_CFE_0_N___2 = 869,\n\tFN_IP14_3_0___2 = 870,\n\tFN_MSIOF0_SS1___3 = 871,\n\tFN_RX5_A___2 = 872,\n\tFN_NFWP_N_A___2 = 873,\n\tFN_AUDIO_CLKA_C___2 = 874,\n\tFN_SSI_SCK2_A___2 = 875,\n\tFN_STP_IVCXO27_0_C___2 = 876,\n\tFN_AUDIO_CLKOUT3_A___2 = 877,\n\tFN_TCLK1_B___3 = 878,\n\tFN_IP15_3_0___2 = 879,\n\tFN_SSI_SDATA1_A___2 = 880,\n\tFN_IP12_7_4___2 = 881,\n\tFN_CTS0_N___3 = 882,\n\tFN_HCTS1_N_B___3 = 883,\n\tFN_MSIOF1_SYNC_B___2 = 884,\n\tFN_TS_SPSYNC1_C___2 = 885,\n\tFN_STP_ISSYNC_1_C___2 = 886,\n\tFN_RIF1_SYNC_B___2 = 887,\n\tFN_AUDIO_CLKOUT_C___2 = 888,\n\tFN_ADICS_SAMP___2 = 889,\n\tFN_IP13_7_4___2 = 890,\n\tFN_RX2_A___2 = 891,\n\tFN_SD2_WP_B___2 = 892,\n\tFN_SDA1_A___2 = 893,\n\tFN_FMIN_A___2 = 894,\n\tFN_RIF1_SYNC_C___2 = 895,\n\tFN_FSO_CFE_1_N___2 = 896,\n\tFN_IP14_7_4___2 = 897,\n\tFN_MSIOF0_SS2___3 = 898,\n\tFN_TX5_A___2 = 899,\n\tFN_MSIOF1_SS2_D___2 = 900,\n\tFN_AUDIO_CLKC_A___2 = 901,\n\tFN_SSI_WS2_A___2 = 902,\n\tFN_STP_OPWM_0_D___2 = 903,\n\tFN_AUDIO_CLKOUT_D___2 = 904,\n\tFN_SPEEDIN_B___2 = 905,\n\tFN_IP15_7_4___2 = 906,\n\tFN_SSI_SDATA2_A___2 = 907,\n\tFN_SSI_SCK1_B___2 = 908,\n\tFN_IP12_11_8___2 = 909,\n\tFN_RTS0_N___3 = 910,\n\tFN_HRTS1_N_B___3 = 911,\n\tFN_MSIOF1_SS1_B___2 = 912,\n\tFN_AUDIO_CLKA_B___2 = 913,\n\tFN_SCL2_A___2 = 914,\n\tFN_STP_IVCXO27_1_C___2 = 915,\n\tFN_RIF0_SYNC_B___2 = 916,\n\tFN_ADICHS1___2 = 917,\n\tFN_IP13_11_8___2 = 918,\n\tFN_HSCK0___3 = 919,\n\tFN_MSIOF1_SCK_D___2 = 920,\n\tFN_AUDIO_CLKB_A___2 = 921,\n\tFN_SSI_SDATA1_B___2 = 922,\n\tFN_TS_SCK0_D___2 = 923,\n\tFN_STP_ISCLK_0_D___2 = 924,\n\tFN_RIF0_CLK_C___2 = 925,\n\tFN_RX5_B___2 = 926,\n\tFN_IP14_11_8___2 = 927,\n\tFN_MLB_CLK___2 = 928,\n\tFN_MSIOF1_SCK_F___2 = 929,\n\tFN_SCL1_B___2 = 930,\n\tFN_IP15_11_8___2 = 931,\n\tFN_SSI_SCK349___2 = 932,\n\tFN_MSIOF1_SS1_A___2 = 933,\n\tFN_STP_OPWM_0_A___2 = 934,\n\tFN_IP12_15_12___2 = 935,\n\tFN_RX1_A___3 = 936,\n\tFN_HRX1_A___3 = 937,\n\tFN_TS_SDAT0_C___2 = 938,\n\tFN_STP_ISD_0_C___2 = 939,\n\tFN_RIF1_CLK_C___2 = 940,\n\tFN_IP13_15_12___2 = 941,\n\tFN_HRX0___3 = 942,\n\tFN_MSIOF1_RXD_D___2 = 943,\n\tFN_SSI_SDATA2_B___2 = 944,\n\tFN_TS_SDEN0_D___2 = 945,\n\tFN_STP_ISEN_0_D___2 = 946,\n\tFN_RIF0_D0_C___2 = 947,\n\tFN_IP14_15_12___2 = 948,\n\tFN_MLB_SIG___2 = 949,\n\tFN_RX1_B___3 = 950,\n\tFN_MSIOF1_SYNC_F___2 = 951,\n\tFN_SDA1_B___2 = 952,\n\tFN_IP15_15_12___2 = 953,\n\tFN_SSI_WS349___2 = 954,\n\tFN_HCTS2_N_A___2 = 955,\n\tFN_MSIOF1_SS2_A___2 = 956,\n\tFN_STP_IVCXO27_0_A___2 = 957,\n\tFN_IP12_19_16___2 = 958,\n\tFN_TX1_A___3 = 959,\n\tFN_HTX1_A___3 = 960,\n\tFN_TS_SDEN0_C___2 = 961,\n\tFN_STP_ISEN_0_C___2 = 962,\n\tFN_RIF1_D0_C___2 = 963,\n\tFN_IP13_19_16___2 = 964,\n\tFN_HTX0___3 = 965,\n\tFN_MSIOF1_TXD_D___2 = 966,\n\tFN_SSI_SDATA9_B___2 = 967,\n\tFN_TS_SDAT0_D___2 = 968,\n\tFN_STP_ISD_0_D___2 = 969,\n\tFN_RIF0_D1_C___2 = 970,\n\tFN_IP14_19_16___2 = 971,\n\tFN_MLB_DAT___2 = 972,\n\tFN_TX1_B___3 = 973,\n\tFN_MSIOF1_RXD_F___2 = 974,\n\tFN_IP15_19_16___2 = 975,\n\tFN_SSI_SDATA3___2 = 976,\n\tFN_HRTS2_N_A___2 = 977,\n\tFN_MSIOF1_TXD_A___2 = 978,\n\tFN_TS_SCK0_A___2 = 979,\n\tFN_STP_ISCLK_0_A___2 = 980,\n\tFN_RIF0_D1_A___2 = 981,\n\tFN_RIF2_D0_A___2 = 982,\n\tFN_IP12_23_20___2 = 983,\n\tFN_CTS1_N___2 = 984,\n\tFN_HCTS1_N_A___3 = 985,\n\tFN_MSIOF1_RXD_B___2 = 986,\n\tFN_TS_SDEN1_C___2 = 987,\n\tFN_STP_ISEN_1_C___2 = 988,\n\tFN_RIF1_D0_B___2 = 989,\n\tFN_ADIDATA___2 = 990,\n\tFN_IP13_23_20___2 = 991,\n\tFN_HCTS0_N___3 = 992,\n\tFN_RX2_B___2 = 993,\n\tFN_MSIOF1_SYNC_D___2 = 994,\n\tFN_SSI_SCK9_A___2 = 995,\n\tFN_TS_SPSYNC0_D___2 = 996,\n\tFN_STP_ISSYNC_0_D___2 = 997,\n\tFN_RIF0_SYNC_C___2 = 998,\n\tFN_AUDIO_CLKOUT1_A___2 = 999,\n\tFN_IP14_23_20___2 = 1000,\n\tFN_SSI_SCK01239___2 = 1001,\n\tFN_MSIOF1_TXD_F___2 = 1002,\n\tFN_IP15_23_20___2 = 1003,\n\tFN_SSI_SCK4___2 = 1004,\n\tFN_HRX2_A___2 = 1005,\n\tFN_MSIOF1_SCK_A___2 = 1006,\n\tFN_TS_SDAT0_A___2 = 1007,\n\tFN_STP_ISD_0_A___2 = 1008,\n\tFN_RIF0_CLK_A___2 = 1009,\n\tFN_RIF2_CLK_A___2 = 1010,\n\tFN_IP12_27_24___2 = 1011,\n\tFN_RTS1_N___2 = 1012,\n\tFN_HRTS1_N_A___3 = 1013,\n\tFN_MSIOF1_TXD_B___2 = 1014,\n\tFN_TS_SDAT1_C___2 = 1015,\n\tFN_STP_ISD_1_C___2 = 1016,\n\tFN_RIF1_D1_B___2 = 1017,\n\tFN_ADICHS0___2 = 1018,\n\tFN_IP13_27_24___2 = 1019,\n\tFN_HRTS0_N___3 = 1020,\n\tFN_TX2_B___2 = 1021,\n\tFN_MSIOF1_SS1_D___2 = 1022,\n\tFN_SSI_WS9_A___2 = 1023,\n\tFN_STP_IVCXO27_0_D___2 = 1024,\n\tFN_BPFCLK_A___2 = 1025,\n\tFN_AUDIO_CLKOUT2_A___2 = 1026,\n\tFN_IP14_27_24___2 = 1027,\n\tFN_SSI_WS01239___2 = 1028,\n\tFN_MSIOF1_SS1_F___2 = 1029,\n\tFN_IP15_27_24___2 = 1030,\n\tFN_SSI_WS4___2 = 1031,\n\tFN_HTX2_A___2 = 1032,\n\tFN_MSIOF1_SYNC_A___2 = 1033,\n\tFN_TS_SDEN0_A___2 = 1034,\n\tFN_STP_ISEN_0_A___2 = 1035,\n\tFN_RIF0_SYNC_A___2 = 1036,\n\tFN_RIF2_SYNC_A___2 = 1037,\n\tFN_IP12_31_28___2 = 1038,\n\tFN_SCK2___2 = 1039,\n\tFN_SCIF_CLK_B___2 = 1040,\n\tFN_MSIOF1_SCK_B___2 = 1041,\n\tFN_TS_SCK1_C___2 = 1042,\n\tFN_STP_ISCLK_1_C___2 = 1043,\n\tFN_RIF1_CLK_B___2 = 1044,\n\tFN_ADICLK___2 = 1045,\n\tFN_IP13_31_28___2 = 1046,\n\tFN_MSIOF0_SYNC___3 = 1047,\n\tFN_AUDIO_CLKOUT_A___2 = 1048,\n\tFN_TX5_B___2 = 1049,\n\tFN_BPFCLK_D___2 = 1050,\n\tFN_IP14_31_28___2 = 1051,\n\tFN_SSI_SDATA0___2 = 1052,\n\tFN_MSIOF1_SS2_F___2 = 1053,\n\tFN_IP15_31_28___2 = 1054,\n\tFN_SSI_SDATA4___2 = 1055,\n\tFN_HSCK2_A___2 = 1056,\n\tFN_MSIOF1_RXD_A___2 = 1057,\n\tFN_TS_SPSYNC0_A___2 = 1058,\n\tFN_STP_ISSYNC_0_A___2 = 1059,\n\tFN_RIF0_D0_A___2 = 1060,\n\tFN_RIF2_D1_A___2 = 1061,\n\tFN_IP16_3_0___2 = 1062,\n\tFN_SSI_SCK6___2 = 1063,\n\tFN_USB2_PWEN = 1064,\n\tFN_SIM0_RST_D___2 = 1065,\n\tFN_IP17_3_0___2 = 1066,\n\tFN_AUDIO_CLKA_A___2 = 1067,\n\tFN_IP18_3_0___2 = 1068,\n\tFN_USB2_CH3_PWEN = 1069,\n\tFN_AUDIO_CLKOUT2_B___2 = 1070,\n\tFN_SSI_SCK9_B___2 = 1071,\n\tFN_TS_SDEN0_E___2 = 1072,\n\tFN_STP_ISEN_0_E___2 = 1073,\n\tFN_RIF2_D0_B___2 = 1074,\n\tFN_TPU0TO2___2 = 1075,\n\tFN_FMCLK_C___2 = 1076,\n\tFN_FMCLK_D___2 = 1077,\n\tFN_IP16_7_4___2 = 1078,\n\tFN_SSI_WS6___2 = 1079,\n\tFN_USB2_OVC = 1080,\n\tFN_SIM0_D_D___2 = 1081,\n\tFN_IP17_7_4___2 = 1082,\n\tFN_AUDIO_CLKB_B___2 = 1083,\n\tFN_SCIF_CLK_A___2 = 1084,\n\tFN_STP_IVCXO27_1_D___2 = 1085,\n\tFN_REMOCON_A___2 = 1086,\n\tFN_TCLK1_A___3 = 1087,\n\tFN_IP18_7_4___2 = 1088,\n\tFN_USB2_CH3_OVC = 1089,\n\tFN_AUDIO_CLKOUT3_B___2 = 1090,\n\tFN_SSI_WS9_B___2 = 1091,\n\tFN_TS_SPSYNC0_E___2 = 1092,\n\tFN_STP_ISSYNC_0_E___2 = 1093,\n\tFN_RIF2_D1_B___2 = 1094,\n\tFN_TPU0TO3___2 = 1095,\n\tFN_FMIN_C___2 = 1096,\n\tFN_FMIN_D___2 = 1097,\n\tFN_IP16_11_8___2 = 1098,\n\tFN_SSI_SDATA6___2 = 1099,\n\tFN_SIM0_CLK_D___2 = 1100,\n\tFN_SATA_DEVSLP_A = 1101,\n\tFN_IP17_11_8___2 = 1102,\n\tFN_USB0_PWEN___2 = 1103,\n\tFN_SIM0_RST_C___2 = 1104,\n\tFN_TS_SCK1_D___2 = 1105,\n\tFN_STP_ISCLK_1_D___2 = 1106,\n\tFN_BPFCLK_B___2 = 1107,\n\tFN_RIF3_CLK_B___2 = 1108,\n\tFN_HSCK2_C___2 = 1109,\n\tFN_IP16_15_12___2 = 1110,\n\tFN_SSI_SCK78___2 = 1111,\n\tFN_HRX2_B___2 = 1112,\n\tFN_MSIOF1_SCK_C___2 = 1113,\n\tFN_TS_SCK1_A___2 = 1114,\n\tFN_STP_ISCLK_1_A___2 = 1115,\n\tFN_RIF1_CLK_A___2 = 1116,\n\tFN_RIF3_CLK_A___2 = 1117,\n\tFN_IP17_15_12___2 = 1118,\n\tFN_USB0_OVC___2 = 1119,\n\tFN_SIM0_D_C___2 = 1120,\n\tFN_TS_SDAT1_D___2 = 1121,\n\tFN_STP_ISD_1_D___2 = 1122,\n\tFN_RIF3_SYNC_B___2 = 1123,\n\tFN_HRX2_C___2 = 1124,\n\tFN_IP16_19_16___2 = 1125,\n\tFN_SSI_WS78___2 = 1126,\n\tFN_HTX2_B___2 = 1127,\n\tFN_MSIOF1_SYNC_C___2 = 1128,\n\tFN_TS_SDAT1_A___2 = 1129,\n\tFN_STP_ISD_1_A___2 = 1130,\n\tFN_RIF1_SYNC_A___2 = 1131,\n\tFN_RIF3_SYNC_A___2 = 1132,\n\tFN_IP17_19_16___2 = 1133,\n\tFN_USB1_PWEN___2 = 1134,\n\tFN_SIM0_CLK_C___2 = 1135,\n\tFN_SSI_SCK1_A___2 = 1136,\n\tFN_TS_SCK0_E___2 = 1137,\n\tFN_STP_ISCLK_0_E___2 = 1138,\n\tFN_FMCLK_B___2 = 1139,\n\tFN_RIF2_CLK_B___2 = 1140,\n\tFN_SPEEDIN_A___2 = 1141,\n\tFN_HTX2_C___2 = 1142,\n\tFN_IP16_23_20___2 = 1143,\n\tFN_SSI_SDATA7___2 = 1144,\n\tFN_HCTS2_N_B___2 = 1145,\n\tFN_MSIOF1_RXD_C___2 = 1146,\n\tFN_TS_SDEN1_A___2 = 1147,\n\tFN_STP_ISEN_1_A___2 = 1148,\n\tFN_RIF1_D0_A___2 = 1149,\n\tFN_RIF3_D0_A___2 = 1150,\n\tFN_TCLK2_A___3 = 1151,\n\tFN_IP17_23_20___2 = 1152,\n\tFN_USB1_OVC___2 = 1153,\n\tFN_MSIOF1_SS2_C___2 = 1154,\n\tFN_SSI_WS1_A___2 = 1155,\n\tFN_TS_SDAT0_E___2 = 1156,\n\tFN_STP_ISD_0_E___2 = 1157,\n\tFN_FMIN_B___2 = 1158,\n\tFN_RIF2_SYNC_B___2 = 1159,\n\tFN_REMOCON_B___2 = 1160,\n\tFN_HCTS2_N_C___2 = 1161,\n\tFN_IP16_27_24___2 = 1162,\n\tFN_SSI_SDATA8___2 = 1163,\n\tFN_HRTS2_N_B___2 = 1164,\n\tFN_MSIOF1_TXD_C___2 = 1165,\n\tFN_TS_SPSYNC1_A___2 = 1166,\n\tFN_STP_ISSYNC_1_A___2 = 1167,\n\tFN_RIF1_D1_A___2 = 1168,\n\tFN_RIF3_D1_A___2 = 1169,\n\tFN_IP17_27_24___2 = 1170,\n\tFN_USB30_PWEN___2 = 1171,\n\tFN_AUDIO_CLKOUT_B___2 = 1172,\n\tFN_SSI_SCK2_B___2 = 1173,\n\tFN_TS_SDEN1_D___2 = 1174,\n\tFN_STP_ISEN_1_D___2 = 1175,\n\tFN_STP_OPWM_0_E___2 = 1176,\n\tFN_RIF3_D0_B___2 = 1177,\n\tFN_TCLK2_B___3 = 1178,\n\tFN_TPU0TO0___2 = 1179,\n\tFN_BPFCLK_C___2 = 1180,\n\tFN_HRTS2_N_C___2 = 1181,\n\tFN_IP16_31_28___2 = 1182,\n\tFN_SSI_SDATA9_A___2 = 1183,\n\tFN_HSCK2_B___2 = 1184,\n\tFN_MSIOF1_SS1_C___2 = 1185,\n\tFN_HSCK1_A___3 = 1186,\n\tFN_SSI_WS1_B___2 = 1187,\n\tFN_SCK1___2 = 1188,\n\tFN_STP_IVCXO27_1_A___2 = 1189,\n\tFN_SCK5_A___2 = 1190,\n\tFN_IP17_31_28___2 = 1191,\n\tFN_USB30_OVC___2 = 1192,\n\tFN_AUDIO_CLKOUT1_B___2 = 1193,\n\tFN_SSI_WS2_B___2 = 1194,\n\tFN_TS_SPSYNC1_D___2 = 1195,\n\tFN_STP_ISSYNC_1_D___2 = 1196,\n\tFN_STP_IVCXO27_0_E___2 = 1197,\n\tFN_RIF3_D1_B___2 = 1198,\n\tFN_FSO_TOE_N___2 = 1199,\n\tFN_TPU0TO1___2 = 1200,\n\tFN_SEL_MSIOF3_0___2 = 1201,\n\tFN_SEL_MSIOF3_1___2 = 1202,\n\tFN_SEL_MSIOF3_2___2 = 1203,\n\tFN_SEL_MSIOF3_3___2 = 1204,\n\tFN_SEL_MSIOF3_4___2 = 1205,\n\tFN_SEL_TSIF1_0___2 = 1206,\n\tFN_SEL_TSIF1_1___2 = 1207,\n\tFN_SEL_TSIF1_2___2 = 1208,\n\tFN_SEL_TSIF1_3___2 = 1209,\n\tFN_I2C_SEL_5_0___2 = 1210,\n\tFN_I2C_SEL_5_1___2 = 1211,\n\tFN_I2C_SEL_3_0___2 = 1212,\n\tFN_I2C_SEL_3_1___2 = 1213,\n\tFN_SEL_TSIF0_0___2 = 1214,\n\tFN_SEL_TSIF0_1___2 = 1215,\n\tFN_SEL_TSIF0_2___2 = 1216,\n\tFN_SEL_TSIF0_3___2 = 1217,\n\tFN_SEL_TSIF0_4___2 = 1218,\n\tFN_I2C_SEL_0_0___2 = 1219,\n\tFN_I2C_SEL_0_1___2 = 1220,\n\tFN_SEL_MSIOF2_0___2 = 1221,\n\tFN_SEL_MSIOF2_1___2 = 1222,\n\tFN_SEL_MSIOF2_2___2 = 1223,\n\tFN_SEL_MSIOF2_3___2 = 1224,\n\tFN_SEL_FM_0___2 = 1225,\n\tFN_SEL_FM_1___2 = 1226,\n\tFN_SEL_FM_2___2 = 1227,\n\tFN_SEL_FM_3___2 = 1228,\n\tFN_SEL_MSIOF1_0___2 = 1229,\n\tFN_SEL_MSIOF1_1___2 = 1230,\n\tFN_SEL_MSIOF1_2___2 = 1231,\n\tFN_SEL_MSIOF1_3___2 = 1232,\n\tFN_SEL_MSIOF1_4___2 = 1233,\n\tFN_SEL_MSIOF1_5___2 = 1234,\n\tFN_SEL_MSIOF1_6___2 = 1235,\n\tFN_SEL_TIMER_TMU1_0 = 1236,\n\tFN_SEL_TIMER_TMU1_1 = 1237,\n\tFN_SEL_SCIF5_0___2 = 1238,\n\tFN_SEL_SCIF5_1___2 = 1239,\n\tFN_SEL_SSP1_1_0___2 = 1240,\n\tFN_SEL_SSP1_1_1___2 = 1241,\n\tFN_SEL_SSP1_1_2___2 = 1242,\n\tFN_SEL_SSP1_1_3___2 = 1243,\n\tFN_SEL_I2C6_0___2 = 1244,\n\tFN_SEL_I2C6_1___2 = 1245,\n\tFN_SEL_I2C6_2___2 = 1246,\n\tFN_SEL_LBSC_0___2 = 1247,\n\tFN_SEL_LBSC_1___2 = 1248,\n\tFN_SEL_SSP1_0_0___2 = 1249,\n\tFN_SEL_SSP1_0_1___2 = 1250,\n\tFN_SEL_SSP1_0_2___2 = 1251,\n\tFN_SEL_SSP1_0_3___2 = 1252,\n\tFN_SEL_SSP1_0_4___2 = 1253,\n\tFN_SEL_IEBUS_0___2 = 1254,\n\tFN_SEL_IEBUS_1___2 = 1255,\n\tFN_SEL_I2C2_0___2 = 1256,\n\tFN_SEL_I2C2_1___2 = 1257,\n\tFN_SEL_SSI2_0___2 = 1258,\n\tFN_SEL_SSI2_1___2 = 1259,\n\tFN_SEL_I2C1_0___2 = 1260,\n\tFN_SEL_I2C1_1___2 = 1261,\n\tFN_SEL_SSI1_0___2 = 1262,\n\tFN_SEL_SSI1_1___2 = 1263,\n\tFN_SEL_SSI9_0___2 = 1264,\n\tFN_SEL_SSI9_1___2 = 1265,\n\tFN_SEL_HSCIF4_0___2 = 1266,\n\tFN_SEL_HSCIF4_1___2 = 1267,\n\tFN_SEL_SPEED_PULSE_0___2 = 1268,\n\tFN_SEL_SPEED_PULSE_1___2 = 1269,\n\tFN_SEL_TIMER_TMU2_0___2 = 1270,\n\tFN_SEL_TIMER_TMU2_1___2 = 1271,\n\tFN_SEL_HSCIF3_0___2 = 1272,\n\tFN_SEL_HSCIF3_1___2 = 1273,\n\tFN_SEL_HSCIF3_2___2 = 1274,\n\tFN_SEL_HSCIF3_3___2 = 1275,\n\tFN_SEL_SIMCARD_0___2 = 1276,\n\tFN_SEL_SIMCARD_1___2 = 1277,\n\tFN_SEL_SIMCARD_2___2 = 1278,\n\tFN_SEL_SIMCARD_3___2 = 1279,\n\tFN_SEL_ADGB_0___2 = 1280,\n\tFN_SEL_ADGB_1___2 = 1281,\n\tFN_SEL_ADGC_0___2 = 1282,\n\tFN_SEL_ADGC_1___2 = 1283,\n\tFN_SEL_HSCIF1_0___2 = 1284,\n\tFN_SEL_HSCIF1_1___2 = 1285,\n\tFN_SEL_SDHI2_0___2 = 1286,\n\tFN_SEL_SDHI2_1___2 = 1287,\n\tFN_SEL_SCIF4_0___2 = 1288,\n\tFN_SEL_SCIF4_1___2 = 1289,\n\tFN_SEL_SCIF4_2___2 = 1290,\n\tFN_SEL_HSCIF2_0___2 = 1291,\n\tFN_SEL_HSCIF2_1___2 = 1292,\n\tFN_SEL_HSCIF2_2___2 = 1293,\n\tFN_SEL_SCIF3_0___2 = 1294,\n\tFN_SEL_SCIF3_1___2 = 1295,\n\tFN_SEL_ETHERAVB_0___2 = 1296,\n\tFN_SEL_ETHERAVB_1___2 = 1297,\n\tFN_SEL_SCIF2_0___2 = 1298,\n\tFN_SEL_SCIF2_1___2 = 1299,\n\tFN_SEL_DRIF3_0___2 = 1300,\n\tFN_SEL_DRIF3_1___2 = 1301,\n\tFN_SEL_SCIF1_0___2 = 1302,\n\tFN_SEL_SCIF1_1___2 = 1303,\n\tFN_SEL_DRIF2_0___2 = 1304,\n\tFN_SEL_DRIF2_1___2 = 1305,\n\tFN_SEL_SCIF_0___2 = 1306,\n\tFN_SEL_SCIF_1___2 = 1307,\n\tFN_SEL_DRIF1_0___2 = 1308,\n\tFN_SEL_DRIF1_1___2 = 1309,\n\tFN_SEL_DRIF1_2___2 = 1310,\n\tFN_SEL_REMOCON_0___2 = 1311,\n\tFN_SEL_REMOCON_1___2 = 1312,\n\tFN_SEL_DRIF0_0___2 = 1313,\n\tFN_SEL_DRIF0_1___2 = 1314,\n\tFN_SEL_DRIF0_2___2 = 1315,\n\tFN_SEL_RCAN0_0___2 = 1316,\n\tFN_SEL_RCAN0_1___2 = 1317,\n\tFN_SEL_CANFD0_0___2 = 1318,\n\tFN_SEL_CANFD0_1___2 = 1319,\n\tFN_SEL_PWM6_0___2 = 1320,\n\tFN_SEL_PWM6_1___2 = 1321,\n\tFN_SEL_ADGA_0___2 = 1322,\n\tFN_SEL_ADGA_1___2 = 1323,\n\tFN_SEL_ADGA_2___2 = 1324,\n\tFN_SEL_ADGA_3___2 = 1325,\n\tFN_SEL_PWM5_0___2 = 1326,\n\tFN_SEL_PWM5_1___2 = 1327,\n\tFN_SEL_PWM4_0___2 = 1328,\n\tFN_SEL_PWM4_1___2 = 1329,\n\tFN_SEL_PWM3_0___2 = 1330,\n\tFN_SEL_PWM3_1___2 = 1331,\n\tFN_SEL_PWM2_0___2 = 1332,\n\tFN_SEL_PWM2_1___2 = 1333,\n\tFN_SEL_PWM1_0___2 = 1334,\n\tFN_SEL_PWM1_1___2 = 1335,\n\tFN_SEL_VIN4_0___2 = 1336,\n\tFN_SEL_VIN4_1___2 = 1337,\n\tPINMUX_FUNCTION_END___3 = 1338,\n\tPINMUX_MARK_BEGIN___3 = 1339,\n\tCLKOUT_MARK___2 = 1340,\n\tMSIOF0_RXD_MARK___3 = 1341,\n\tMSIOF0_TXD_MARK___3 = 1342,\n\tMSIOF0_SCK_MARK___3 = 1343,\n\tSSI_SDATA5_MARK___2 = 1344,\n\tSSI_WS5_MARK___2 = 1345,\n\tSSI_SCK5_MARK___2 = 1346,\n\tGP7_03_MARK___2 = 1347,\n\tGP7_02_MARK___2 = 1348,\n\tAVS2_MARK___2 = 1349,\n\tAVS1_MARK___3 = 1350,\n\tIP0_3_0_MARK___2 = 1351,\n\tAVB_MDC_MARK___2 = 1352,\n\tMSIOF2_SS2_C_MARK___2 = 1353,\n\tIP1_3_0_MARK___2 = 1354,\n\tIRQ2_MARK___2 = 1355,\n\tQCPV_QDE_MARK___2 = 1356,\n\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK___2 = 1357,\n\tVI4_DATA2_B_MARK___2 = 1358,\n\tMSIOF3_SYNC_E_MARK___2 = 1359,\n\tPWM3_B_MARK___3 = 1360,\n\tIP2_3_0_MARK___2 = 1361,\n\tA1_MARK___2 = 1362,\n\tLCDOUT17_MARK___2 = 1363,\n\tMSIOF3_TXD_B_MARK___2 = 1364,\n\tVI4_DATA9_MARK___2 = 1365,\n\tDU_DB1_MARK___2 = 1366,\n\tPWM4_A_MARK___2 = 1367,\n\tIP3_3_0_MARK___2 = 1368,\n\tA9_MARK___2 = 1369,\n\tMSIOF2_SCK_A_MARK___2 = 1370,\n\tCTS4_N_B_MARK___2 = 1371,\n\tVI5_VSYNC_N_MARK___2 = 1372,\n\tIP0_7_4_MARK___2 = 1373,\n\tAVB_MAGIC_MARK___2 = 1374,\n\tMSIOF2_SS1_C_MARK___2 = 1375,\n\tSCK4_A_MARK___2 = 1376,\n\tIP1_7_4_MARK___2 = 1377,\n\tIRQ3_MARK___2 = 1378,\n\tQSTVB_QVE_MARK___2 = 1379,\n\tDU_DOTCLKOUT1_MARK___2 = 1380,\n\tVI4_DATA3_B_MARK___2 = 1381,\n\tMSIOF3_SCK_E_MARK___2 = 1382,\n\tPWM4_B_MARK___2 = 1383,\n\tIP2_7_4_MARK___2 = 1384,\n\tA2_MARK___2 = 1385,\n\tLCDOUT18_MARK___2 = 1386,\n\tMSIOF3_SCK_B_MARK___2 = 1387,\n\tVI4_DATA10_MARK___2 = 1388,\n\tDU_DB2_MARK___2 = 1389,\n\tPWM5_A_MARK___2 = 1390,\n\tIP3_7_4_MARK___2 = 1391,\n\tA10_MARK___2 = 1392,\n\tMSIOF2_RXD_A_MARK___2 = 1393,\n\tRTS4_N_B_MARK___2 = 1394,\n\tVI5_HSYNC_N_MARK___2 = 1395,\n\tIP0_11_8_MARK___2 = 1396,\n\tAVB_PHY_INT_MARK___2 = 1397,\n\tMSIOF2_SYNC_C_MARK___2 = 1398,\n\tRX4_A_MARK___2 = 1399,\n\tIP1_11_8_MARK___2 = 1400,\n\tIRQ4_MARK___2 = 1401,\n\tQSTH_QHS_MARK___2 = 1402,\n\tDU_EXHSYNC_DU_HSYNC_MARK___2 = 1403,\n\tVI4_DATA4_B_MARK___2 = 1404,\n\tMSIOF3_RXD_E_MARK___2 = 1405,\n\tPWM5_B_MARK___2 = 1406,\n\tIP2_11_8_MARK___2 = 1407,\n\tA3_MARK___2 = 1408,\n\tLCDOUT19_MARK___2 = 1409,\n\tMSIOF3_RXD_B_MARK___2 = 1410,\n\tVI4_DATA11_MARK___2 = 1411,\n\tDU_DB3_MARK___2 = 1412,\n\tPWM6_A_MARK___2 = 1413,\n\tIP3_11_8_MARK___2 = 1414,\n\tA11_MARK___2 = 1415,\n\tTX3_B_MARK___3 = 1416,\n\tMSIOF2_TXD_A_MARK___2 = 1417,\n\tHTX4_B_MARK___2 = 1418,\n\tHSCK4_MARK___2 = 1419,\n\tVI5_FIELD_MARK___2 = 1420,\n\tSCL6_A_MARK___2 = 1421,\n\tAVB_AVTP_CAPTURE_B_MARK___2 = 1422,\n\tPWM2_B_MARK___2 = 1423,\n\tIP0_15_12_MARK___2 = 1424,\n\tAVB_LINK_MARK___2 = 1425,\n\tMSIOF2_SCK_C_MARK___2 = 1426,\n\tTX4_A_MARK___2 = 1427,\n\tIP1_15_12_MARK___2 = 1428,\n\tIRQ5_MARK___3 = 1429,\n\tQSTB_QHE_MARK___2 = 1430,\n\tDU_EXVSYNC_DU_VSYNC_MARK___2 = 1431,\n\tVI4_DATA5_B_MARK___2 = 1432,\n\tFSCLKST2_N_B_MARK = 1433,\n\tMSIOF3_TXD_E_MARK___2 = 1434,\n\tPWM6_B_MARK___2 = 1435,\n\tIP2_15_12_MARK___2 = 1436,\n\tA4_MARK___2 = 1437,\n\tLCDOUT20_MARK___2 = 1438,\n\tMSIOF3_SS1_B_MARK___2 = 1439,\n\tVI4_DATA12_MARK___2 = 1440,\n\tVI5_DATA12_MARK___2 = 1441,\n\tDU_DB4_MARK___2 = 1442,\n\tIP3_15_12_MARK___2 = 1443,\n\tA12_MARK___2 = 1444,\n\tLCDOUT12_MARK___2 = 1445,\n\tMSIOF3_SCK_C_MARK___2 = 1446,\n\tHRX4_A_MARK___2 = 1447,\n\tVI5_DATA8_MARK___2 = 1448,\n\tDU_DG4_MARK___2 = 1449,\n\tIP0_19_16_MARK___2 = 1450,\n\tAVB_AVTP_MATCH_A_MARK___2 = 1451,\n\tMSIOF2_RXD_C_MARK___2 = 1452,\n\tCTS4_N_A_MARK___2 = 1453,\n\tFSCLKST2_N_A_MARK = 1454,\n\tIP1_19_16_MARK___2 = 1455,\n\tPWM0_MARK___3 = 1456,\n\tAVB_AVTP_PPS_MARK___2 = 1457,\n\tVI4_DATA6_B_MARK___2 = 1458,\n\tIECLK_B_MARK___2 = 1459,\n\tIP2_19_16_MARK___2 = 1460,\n\tA5_MARK___2 = 1461,\n\tLCDOUT21_MARK___2 = 1462,\n\tMSIOF3_SS2_B_MARK___2 = 1463,\n\tSCK4_B_MARK___2 = 1464,\n\tVI4_DATA13_MARK___2 = 1465,\n\tVI5_DATA13_MARK___2 = 1466,\n\tDU_DB5_MARK___2 = 1467,\n\tIP3_19_16_MARK___2 = 1468,\n\tA13_MARK___2 = 1469,\n\tLCDOUT13_MARK___2 = 1470,\n\tMSIOF3_SYNC_C_MARK___2 = 1471,\n\tHTX4_A_MARK___2 = 1472,\n\tVI5_DATA9_MARK___2 = 1473,\n\tDU_DG5_MARK___2 = 1474,\n\tIP0_23_20_MARK___2 = 1475,\n\tAVB_AVTP_CAPTURE_A_MARK___2 = 1476,\n\tMSIOF2_TXD_C_MARK___2 = 1477,\n\tRTS4_N_A_MARK___2 = 1478,\n\tIP1_23_20_MARK___2 = 1479,\n\tPWM1_A_MARK___3 = 1480,\n\tHRX3_D_MARK___2 = 1481,\n\tVI4_DATA7_B_MARK___2 = 1482,\n\tIERX_B_MARK___2 = 1483,\n\tIP2_23_20_MARK___2 = 1484,\n\tA6_MARK___2 = 1485,\n\tLCDOUT22_MARK___2 = 1486,\n\tMSIOF2_SS1_A_MARK___2 = 1487,\n\tRX4_B_MARK___2 = 1488,\n\tVI4_DATA14_MARK___2 = 1489,\n\tVI5_DATA14_MARK___2 = 1490,\n\tDU_DB6_MARK___2 = 1491,\n\tIP3_23_20_MARK___2 = 1492,\n\tA14_MARK___2 = 1493,\n\tLCDOUT14_MARK___2 = 1494,\n\tMSIOF3_RXD_C_MARK___2 = 1495,\n\tHCTS4_N_MARK___2 = 1496,\n\tVI5_DATA10_MARK___2 = 1497,\n\tDU_DG6_MARK___2 = 1498,\n\tIP0_27_24_MARK___2 = 1499,\n\tIRQ0_MARK___2 = 1500,\n\tQPOLB_MARK___2 = 1501,\n\tDU_CDE_MARK___2 = 1502,\n\tVI4_DATA0_B_MARK___2 = 1503,\n\tCAN0_TX_B_MARK___2 = 1504,\n\tCANFD0_TX_B_MARK___2 = 1505,\n\tMSIOF3_SS2_E_MARK___2 = 1506,\n\tIP1_27_24_MARK___2 = 1507,\n\tPWM2_A_MARK___2 = 1508,\n\tHTX3_D_MARK___2 = 1509,\n\tIETX_B_MARK___2 = 1510,\n\tIP2_27_24_MARK___2 = 1511,\n\tA7_MARK___2 = 1512,\n\tLCDOUT23_MARK___2 = 1513,\n\tMSIOF2_SS2_A_MARK___2 = 1514,\n\tTX4_B_MARK___2 = 1515,\n\tVI4_DATA15_MARK___2 = 1516,\n\tVI5_DATA15_MARK___2 = 1517,\n\tDU_DB7_MARK___2 = 1518,\n\tIP3_27_24_MARK___2 = 1519,\n\tA15_MARK___2 = 1520,\n\tLCDOUT15_MARK___2 = 1521,\n\tMSIOF3_TXD_C_MARK___2 = 1522,\n\tHRTS4_N_MARK___2 = 1523,\n\tVI5_DATA11_MARK___2 = 1524,\n\tDU_DG7_MARK___2 = 1525,\n\tIP0_31_28_MARK___2 = 1526,\n\tIRQ1_MARK___2 = 1527,\n\tQPOLA_MARK___2 = 1528,\n\tDU_DISP_MARK___2 = 1529,\n\tVI4_DATA1_B_MARK___2 = 1530,\n\tCAN0_RX_B_MARK___2 = 1531,\n\tCANFD0_RX_B_MARK___2 = 1532,\n\tMSIOF3_SS1_E_MARK___2 = 1533,\n\tIP1_31_28_MARK___2 = 1534,\n\tA0_MARK___2 = 1535,\n\tLCDOUT16_MARK___2 = 1536,\n\tMSIOF3_SYNC_B_MARK___2 = 1537,\n\tVI4_DATA8_MARK___2 = 1538,\n\tDU_DB0_MARK___2 = 1539,\n\tPWM3_A_MARK___3 = 1540,\n\tIP2_31_28_MARK___2 = 1541,\n\tA8_MARK___2 = 1542,\n\tRX3_B_MARK___3 = 1543,\n\tMSIOF2_SYNC_A_MARK___2 = 1544,\n\tHRX4_B_MARK___2 = 1545,\n\tSDA6_A_MARK___2 = 1546,\n\tAVB_AVTP_MATCH_B_MARK___2 = 1547,\n\tPWM1_B_MARK___3 = 1548,\n\tIP3_31_28_MARK___2 = 1549,\n\tA16_MARK___2 = 1550,\n\tLCDOUT8_MARK___2 = 1551,\n\tVI4_FIELD_MARK___2 = 1552,\n\tDU_DG0_MARK___2 = 1553,\n\tIP4_3_0_MARK___2 = 1554,\n\tA17_MARK___2 = 1555,\n\tLCDOUT9_MARK___2 = 1556,\n\tVI4_VSYNC_N_MARK___2 = 1557,\n\tDU_DG1_MARK___2 = 1558,\n\tIP5_3_0_MARK___2 = 1559,\n\tWE0_N_MARK___2 = 1560,\n\tMSIOF3_TXD_D_MARK___2 = 1561,\n\tCTS3_N_MARK___2 = 1562,\n\tHCTS3_N_MARK___2 = 1563,\n\tSCL6_B_MARK___2 = 1564,\n\tCAN_CLK_MARK___3 = 1565,\n\tIECLK_A_MARK___2 = 1566,\n\tIP6_3_0_MARK___2 = 1567,\n\tD5_MARK___2 = 1568,\n\tMSIOF2_SYNC_B_MARK___2 = 1569,\n\tVI4_DATA21_MARK___2 = 1570,\n\tVI5_DATA5_MARK___2 = 1571,\n\tIP7_3_0_MARK___2 = 1572,\n\tD13_MARK___2 = 1573,\n\tLCDOUT5_MARK___2 = 1574,\n\tMSIOF2_SS2_D_MARK___2 = 1575,\n\tTX4_C_MARK___2 = 1576,\n\tVI4_DATA5_A_MARK___2 = 1577,\n\tDU_DR5_MARK___2 = 1578,\n\tIP4_7_4_MARK___2 = 1579,\n\tA18_MARK___2 = 1580,\n\tLCDOUT10_MARK___2 = 1581,\n\tVI4_HSYNC_N_MARK___2 = 1582,\n\tDU_DG2_MARK___2 = 1583,\n\tIP5_7_4_MARK___2 = 1584,\n\tWE1_N_MARK___2 = 1585,\n\tMSIOF3_SS1_D_MARK___2 = 1586,\n\tRTS3_N_MARK___2 = 1587,\n\tHRTS3_N_MARK___2 = 1588,\n\tSDA6_B_MARK___2 = 1589,\n\tCAN1_RX_MARK___2 = 1590,\n\tCANFD1_RX_MARK___3 = 1591,\n\tIERX_A_MARK___2 = 1592,\n\tIP6_7_4_MARK___2 = 1593,\n\tD6_MARK___2 = 1594,\n\tMSIOF2_RXD_B_MARK___2 = 1595,\n\tVI4_DATA22_MARK___2 = 1596,\n\tVI5_DATA6_MARK___2 = 1597,\n\tIP7_7_4_MARK___2 = 1598,\n\tD14_MARK___2 = 1599,\n\tLCDOUT6_MARK___2 = 1600,\n\tMSIOF3_SS1_A_MARK___2 = 1601,\n\tHRX3_C_MARK___2 = 1602,\n\tVI4_DATA6_A_MARK___2 = 1603,\n\tDU_DR6_MARK___2 = 1604,\n\tSCL6_C_MARK___2 = 1605,\n\tIP4_11_8_MARK___2 = 1606,\n\tA19_MARK___2 = 1607,\n\tLCDOUT11_MARK___2 = 1608,\n\tVI4_CLKENB_MARK___2 = 1609,\n\tDU_DG3_MARK___2 = 1610,\n\tIP5_11_8_MARK___2 = 1611,\n\tEX_WAIT0_A_MARK___2 = 1612,\n\tQCLK_MARK___2 = 1613,\n\tVI4_CLK_MARK___2 = 1614,\n\tDU_DOTCLKOUT0_MARK___2 = 1615,\n\tIP6_11_8_MARK___2 = 1616,\n\tD7_MARK___2 = 1617,\n\tMSIOF2_TXD_B_MARK___2 = 1618,\n\tVI4_DATA23_MARK___2 = 1619,\n\tVI5_DATA7_MARK___2 = 1620,\n\tIP7_11_8_MARK___2 = 1621,\n\tD15_MARK___2 = 1622,\n\tLCDOUT7_MARK___2 = 1623,\n\tMSIOF3_SS2_A_MARK___2 = 1624,\n\tHTX3_C_MARK___2 = 1625,\n\tVI4_DATA7_A_MARK___2 = 1626,\n\tDU_DR7_MARK___2 = 1627,\n\tSDA6_C_MARK___2 = 1628,\n\tIP4_15_12_MARK___2 = 1629,\n\tCS0_N_MARK___2 = 1630,\n\tVI5_CLKENB_MARK___2 = 1631,\n\tIP5_15_12_MARK___2 = 1632,\n\tD0_MARK___2 = 1633,\n\tMSIOF2_SS1_B_MARK___2 = 1634,\n\tMSIOF3_SCK_A_MARK___2 = 1635,\n\tVI4_DATA16_MARK___2 = 1636,\n\tVI5_DATA0_MARK___2 = 1637,\n\tIP6_15_12_MARK___2 = 1638,\n\tD8_MARK___2 = 1639,\n\tLCDOUT0_MARK___2 = 1640,\n\tMSIOF2_SCK_D_MARK___2 = 1641,\n\tSCK4_C_MARK___2 = 1642,\n\tVI4_DATA0_A_MARK___2 = 1643,\n\tDU_DR0_MARK___2 = 1644,\n\tIP4_19_16_MARK___2 = 1645,\n\tCS1_N_MARK___2 = 1646,\n\tVI5_CLK_MARK___2 = 1647,\n\tEX_WAIT0_B_MARK___2 = 1648,\n\tIP5_19_16_MARK___2 = 1649,\n\tD1_MARK___2 = 1650,\n\tMSIOF2_SS2_B_MARK___2 = 1651,\n\tMSIOF3_SYNC_A_MARK___2 = 1652,\n\tVI4_DATA17_MARK___2 = 1653,\n\tVI5_DATA1_MARK___2 = 1654,\n\tIP6_19_16_MARK___2 = 1655,\n\tD9_MARK___2 = 1656,\n\tLCDOUT1_MARK___2 = 1657,\n\tMSIOF2_SYNC_D_MARK___2 = 1658,\n\tVI4_DATA1_A_MARK___2 = 1659,\n\tDU_DR1_MARK___2 = 1660,\n\tIP7_19_16_MARK___2 = 1661,\n\tSD0_CLK_MARK___2 = 1662,\n\tMSIOF1_SCK_E_MARK___2 = 1663,\n\tSTP_OPWM_0_B_MARK___2 = 1664,\n\tIP4_23_20_MARK___2 = 1665,\n\tBS_N_MARK___2 = 1666,\n\tQSTVA_QVS_MARK___2 = 1667,\n\tMSIOF3_SCK_D_MARK___2 = 1668,\n\tSCK3_MARK___2 = 1669,\n\tHSCK3_MARK___2 = 1670,\n\tCAN1_TX_MARK___2 = 1671,\n\tCANFD1_TX_MARK___3 = 1672,\n\tIETX_A_MARK___2 = 1673,\n\tIP5_23_20_MARK___2 = 1674,\n\tD2_MARK___2 = 1675,\n\tMSIOF3_RXD_A_MARK___2 = 1676,\n\tVI4_DATA18_MARK___2 = 1677,\n\tVI5_DATA2_MARK___2 = 1678,\n\tIP6_23_20_MARK___2 = 1679,\n\tD10_MARK___2 = 1680,\n\tLCDOUT2_MARK___2 = 1681,\n\tMSIOF2_RXD_D_MARK___2 = 1682,\n\tHRX3_B_MARK___3 = 1683,\n\tVI4_DATA2_A_MARK___2 = 1684,\n\tCTS4_N_C_MARK___2 = 1685,\n\tDU_DR2_MARK___2 = 1686,\n\tIP7_23_20_MARK___2 = 1687,\n\tSD0_CMD_MARK___2 = 1688,\n\tMSIOF1_SYNC_E_MARK___2 = 1689,\n\tSTP_IVCXO27_0_B_MARK___2 = 1690,\n\tIP4_27_24_MARK___2 = 1691,\n\tRD_N_MARK___2 = 1692,\n\tMSIOF3_SYNC_D_MARK___2 = 1693,\n\tRX3_A_MARK___3 = 1694,\n\tHRX3_A_MARK___3 = 1695,\n\tCAN0_TX_A_MARK___2 = 1696,\n\tCANFD0_TX_A_MARK___2 = 1697,\n\tIP5_27_24_MARK___2 = 1698,\n\tD3_MARK___2 = 1699,\n\tMSIOF3_TXD_A_MARK___2 = 1700,\n\tVI4_DATA19_MARK___2 = 1701,\n\tVI5_DATA3_MARK___2 = 1702,\n\tIP6_27_24_MARK___2 = 1703,\n\tD11_MARK___2 = 1704,\n\tLCDOUT3_MARK___2 = 1705,\n\tMSIOF2_TXD_D_MARK___2 = 1706,\n\tHTX3_B_MARK___3 = 1707,\n\tVI4_DATA3_A_MARK___2 = 1708,\n\tRTS4_N_C_MARK___2 = 1709,\n\tDU_DR3_MARK___2 = 1710,\n\tIP7_27_24_MARK___2 = 1711,\n\tSD0_DAT0_MARK___2 = 1712,\n\tMSIOF1_RXD_E_MARK___2 = 1713,\n\tTS_SCK0_B_MARK___2 = 1714,\n\tSTP_ISCLK_0_B_MARK___2 = 1715,\n\tIP4_31_28_MARK___2 = 1716,\n\tRD_WR_N_MARK___2 = 1717,\n\tMSIOF3_RXD_D_MARK___2 = 1718,\n\tTX3_A_MARK___3 = 1719,\n\tHTX3_A_MARK___3 = 1720,\n\tCAN0_RX_A_MARK___2 = 1721,\n\tCANFD0_RX_A_MARK___2 = 1722,\n\tIP5_31_28_MARK___2 = 1723,\n\tD4_MARK___2 = 1724,\n\tMSIOF2_SCK_B_MARK___2 = 1725,\n\tVI4_DATA20_MARK___2 = 1726,\n\tVI5_DATA4_MARK___2 = 1727,\n\tIP6_31_28_MARK___2 = 1728,\n\tD12_MARK___2 = 1729,\n\tLCDOUT4_MARK___2 = 1730,\n\tMSIOF2_SS1_D_MARK___2 = 1731,\n\tRX4_C_MARK___2 = 1732,\n\tVI4_DATA4_A_MARK___2 = 1733,\n\tDU_DR4_MARK___2 = 1734,\n\tIP7_31_28_MARK___2 = 1735,\n\tSD0_DAT1_MARK___2 = 1736,\n\tMSIOF1_TXD_E_MARK___2 = 1737,\n\tTS_SPSYNC0_B_MARK___2 = 1738,\n\tSTP_ISSYNC_0_B_MARK___2 = 1739,\n\tIP8_3_0_MARK___2 = 1740,\n\tSD0_DAT2_MARK___2 = 1741,\n\tMSIOF1_SS1_E_MARK___2 = 1742,\n\tTS_SDAT0_B_MARK___2 = 1743,\n\tSTP_ISD_0_B_MARK___2 = 1744,\n\tIP9_3_0_MARK___2 = 1745,\n\tSD2_CLK_MARK___2 = 1746,\n\tNFDATA8_MARK___2 = 1747,\n\tIP10_3_0_MARK___2 = 1748,\n\tSD3_CMD_MARK___2 = 1749,\n\tNFRE_N_MARK___2 = 1750,\n\tIP11_3_0_MARK___2 = 1751,\n\tSD3_DAT7_MARK___2 = 1752,\n\tSD3_WP_MARK___2 = 1753,\n\tNFDATA7_MARK___2 = 1754,\n\tIP8_7_4_MARK___2 = 1755,\n\tSD0_DAT3_MARK___2 = 1756,\n\tMSIOF1_SS2_E_MARK___2 = 1757,\n\tTS_SDEN0_B_MARK___2 = 1758,\n\tSTP_ISEN_0_B_MARK___2 = 1759,\n\tIP9_7_4_MARK___2 = 1760,\n\tSD2_CMD_MARK___2 = 1761,\n\tNFDATA9_MARK___2 = 1762,\n\tIP10_7_4_MARK___2 = 1763,\n\tSD3_DAT0_MARK___2 = 1764,\n\tNFDATA0_MARK___2 = 1765,\n\tIP11_7_4_MARK___2 = 1766,\n\tSD3_DS_MARK___2 = 1767,\n\tNFCLE_MARK___2 = 1768,\n\tIP8_11_8_MARK___2 = 1769,\n\tSD1_CLK_MARK___2 = 1770,\n\tMSIOF1_SCK_G_MARK___2 = 1771,\n\tSIM0_CLK_A_MARK___2 = 1772,\n\tIP9_11_8_MARK___2 = 1773,\n\tSD2_DAT0_MARK___2 = 1774,\n\tNFDATA10_MARK___2 = 1775,\n\tIP10_11_8_MARK___2 = 1776,\n\tSD3_DAT1_MARK___2 = 1777,\n\tNFDATA1_MARK___2 = 1778,\n\tIP11_11_8_MARK___2 = 1779,\n\tSD0_CD_MARK___2 = 1780,\n\tNFDATA14_A_MARK___2 = 1781,\n\tSCL2_B_MARK___2 = 1782,\n\tSIM0_RST_A_MARK___2 = 1783,\n\tIP8_15_12_MARK___2 = 1784,\n\tSD1_CMD_MARK___2 = 1785,\n\tMSIOF1_SYNC_G_MARK___2 = 1786,\n\tNFCE_N_B_MARK___2 = 1787,\n\tSIM0_D_A_MARK___2 = 1788,\n\tSTP_IVCXO27_1_B_MARK___2 = 1789,\n\tIP9_15_12_MARK___2 = 1790,\n\tSD2_DAT1_MARK___2 = 1791,\n\tNFDATA11_MARK___2 = 1792,\n\tIP10_15_12_MARK___2 = 1793,\n\tSD3_DAT2_MARK___2 = 1794,\n\tNFDATA2_MARK___2 = 1795,\n\tIP11_15_12_MARK___2 = 1796,\n\tSD0_WP_MARK___2 = 1797,\n\tNFDATA15_A_MARK___2 = 1798,\n\tSDA2_B_MARK___2 = 1799,\n\tIP8_19_16_MARK___2 = 1800,\n\tSD1_DAT0_MARK___2 = 1801,\n\tSD2_DAT4_MARK___2 = 1802,\n\tMSIOF1_RXD_G_MARK___2 = 1803,\n\tNFWP_N_B_MARK___2 = 1804,\n\tTS_SCK1_B_MARK___2 = 1805,\n\tSTP_ISCLK_1_B_MARK___2 = 1806,\n\tIP9_19_16_MARK___2 = 1807,\n\tSD2_DAT2_MARK___2 = 1808,\n\tNFDATA12_MARK___2 = 1809,\n\tIP10_19_16_MARK___2 = 1810,\n\tSD3_DAT3_MARK___2 = 1811,\n\tNFDATA3_MARK___2 = 1812,\n\tIP11_19_16_MARK___2 = 1813,\n\tSD1_CD_MARK___2 = 1814,\n\tNFRB_N_A_MARK___2 = 1815,\n\tSIM0_CLK_B_MARK___2 = 1816,\n\tIP8_23_20_MARK___2 = 1817,\n\tSD1_DAT1_MARK___2 = 1818,\n\tSD2_DAT5_MARK___2 = 1819,\n\tMSIOF1_TXD_G_MARK___2 = 1820,\n\tNFDATA14_B_MARK___2 = 1821,\n\tTS_SPSYNC1_B_MARK___2 = 1822,\n\tSTP_ISSYNC_1_B_MARK___2 = 1823,\n\tIP9_23_20_MARK___2 = 1824,\n\tSD2_DAT3_MARK___2 = 1825,\n\tNFDATA13_MARK___2 = 1826,\n\tIP10_23_20_MARK___2 = 1827,\n\tSD3_DAT4_MARK___2 = 1828,\n\tSD2_CD_A_MARK___2 = 1829,\n\tNFDATA4_MARK___2 = 1830,\n\tIP11_23_20_MARK___2 = 1831,\n\tSD1_WP_MARK___2 = 1832,\n\tNFCE_N_A_MARK___2 = 1833,\n\tSIM0_D_B_MARK___2 = 1834,\n\tIP8_27_24_MARK___2 = 1835,\n\tSD1_DAT2_MARK___2 = 1836,\n\tSD2_DAT6_MARK___2 = 1837,\n\tMSIOF1_SS1_G_MARK___2 = 1838,\n\tNFDATA15_B_MARK___2 = 1839,\n\tTS_SDAT1_B_MARK___2 = 1840,\n\tSTP_ISD_1_B_MARK___2 = 1841,\n\tIP9_27_24_MARK___2 = 1842,\n\tSD2_DS_MARK___2 = 1843,\n\tNFALE_MARK___2 = 1844,\n\tSATA_DEVSLP_B_MARK = 1845,\n\tIP10_27_24_MARK___2 = 1846,\n\tSD3_DAT5_MARK___2 = 1847,\n\tSD2_WP_A_MARK___2 = 1848,\n\tNFDATA5_MARK___2 = 1849,\n\tIP11_27_24_MARK___2 = 1850,\n\tSCK0_MARK___3 = 1851,\n\tHSCK1_B_MARK___3 = 1852,\n\tMSIOF1_SS2_B_MARK___2 = 1853,\n\tAUDIO_CLKC_B_MARK___2 = 1854,\n\tSDA2_A_MARK___2 = 1855,\n\tSIM0_RST_B_MARK___2 = 1856,\n\tSTP_OPWM_0_C_MARK___2 = 1857,\n\tRIF0_CLK_B_MARK___2 = 1858,\n\tADICHS2_MARK___2 = 1859,\n\tSCK5_B_MARK___2 = 1860,\n\tIP8_31_28_MARK___2 = 1861,\n\tSD1_DAT3_MARK___2 = 1862,\n\tSD2_DAT7_MARK___2 = 1863,\n\tMSIOF1_SS2_G_MARK___2 = 1864,\n\tNFRB_N_B_MARK___2 = 1865,\n\tTS_SDEN1_B_MARK___2 = 1866,\n\tSTP_ISEN_1_B_MARK___2 = 1867,\n\tIP9_31_28_MARK___2 = 1868,\n\tSD3_CLK_MARK___2 = 1869,\n\tNFWE_N_MARK___2 = 1870,\n\tIP10_31_28_MARK___2 = 1871,\n\tSD3_DAT6_MARK___2 = 1872,\n\tSD3_CD_MARK___2 = 1873,\n\tNFDATA6_MARK___2 = 1874,\n\tIP11_31_28_MARK___2 = 1875,\n\tRX0_MARK___3 = 1876,\n\tHRX1_B_MARK___3 = 1877,\n\tTS_SCK0_C_MARK___2 = 1878,\n\tSTP_ISCLK_0_C_MARK___2 = 1879,\n\tRIF0_D0_B_MARK___2 = 1880,\n\tIP12_3_0_MARK___2 = 1881,\n\tTX0_MARK___3 = 1882,\n\tHTX1_B_MARK___3 = 1883,\n\tTS_SPSYNC0_C_MARK___2 = 1884,\n\tSTP_ISSYNC_0_C_MARK___2 = 1885,\n\tRIF0_D1_B_MARK___2 = 1886,\n\tIP13_3_0_MARK___2 = 1887,\n\tTX2_A_MARK___2 = 1888,\n\tSD2_CD_B_MARK___2 = 1889,\n\tSCL1_A_MARK___2 = 1890,\n\tFMCLK_A_MARK___2 = 1891,\n\tRIF1_D1_C_MARK___2 = 1892,\n\tFSO_CFE_0_N_MARK___2 = 1893,\n\tIP14_3_0_MARK___2 = 1894,\n\tMSIOF0_SS1_MARK___3 = 1895,\n\tRX5_A_MARK___2 = 1896,\n\tNFWP_N_A_MARK___2 = 1897,\n\tAUDIO_CLKA_C_MARK___2 = 1898,\n\tSSI_SCK2_A_MARK___2 = 1899,\n\tSTP_IVCXO27_0_C_MARK___2 = 1900,\n\tAUDIO_CLKOUT3_A_MARK___2 = 1901,\n\tTCLK1_B_MARK___3 = 1902,\n\tIP15_3_0_MARK___2 = 1903,\n\tSSI_SDATA1_A_MARK___2 = 1904,\n\tIP12_7_4_MARK___2 = 1905,\n\tCTS0_N_MARK___3 = 1906,\n\tHCTS1_N_B_MARK___3 = 1907,\n\tMSIOF1_SYNC_B_MARK___2 = 1908,\n\tTS_SPSYNC1_C_MARK___2 = 1909,\n\tSTP_ISSYNC_1_C_MARK___2 = 1910,\n\tRIF1_SYNC_B_MARK___2 = 1911,\n\tAUDIO_CLKOUT_C_MARK___2 = 1912,\n\tADICS_SAMP_MARK___2 = 1913,\n\tIP13_7_4_MARK___2 = 1914,\n\tRX2_A_MARK___2 = 1915,\n\tSD2_WP_B_MARK___2 = 1916,\n\tSDA1_A_MARK___2 = 1917,\n\tFMIN_A_MARK___2 = 1918,\n\tRIF1_SYNC_C_MARK___2 = 1919,\n\tFSO_CFE_1_N_MARK___2 = 1920,\n\tIP14_7_4_MARK___2 = 1921,\n\tMSIOF0_SS2_MARK___3 = 1922,\n\tTX5_A_MARK___2 = 1923,\n\tMSIOF1_SS2_D_MARK___2 = 1924,\n\tAUDIO_CLKC_A_MARK___2 = 1925,\n\tSSI_WS2_A_MARK___2 = 1926,\n\tSTP_OPWM_0_D_MARK___2 = 1927,\n\tAUDIO_CLKOUT_D_MARK___2 = 1928,\n\tSPEEDIN_B_MARK___2 = 1929,\n\tIP15_7_4_MARK___2 = 1930,\n\tSSI_SDATA2_A_MARK___2 = 1931,\n\tSSI_SCK1_B_MARK___2 = 1932,\n\tIP12_11_8_MARK___2 = 1933,\n\tRTS0_N_MARK___3 = 1934,\n\tHRTS1_N_B_MARK___3 = 1935,\n\tMSIOF1_SS1_B_MARK___2 = 1936,\n\tAUDIO_CLKA_B_MARK___2 = 1937,\n\tSCL2_A_MARK___2 = 1938,\n\tSTP_IVCXO27_1_C_MARK___2 = 1939,\n\tRIF0_SYNC_B_MARK___2 = 1940,\n\tADICHS1_MARK___2 = 1941,\n\tIP13_11_8_MARK___2 = 1942,\n\tHSCK0_MARK___3 = 1943,\n\tMSIOF1_SCK_D_MARK___2 = 1944,\n\tAUDIO_CLKB_A_MARK___2 = 1945,\n\tSSI_SDATA1_B_MARK___2 = 1946,\n\tTS_SCK0_D_MARK___2 = 1947,\n\tSTP_ISCLK_0_D_MARK___2 = 1948,\n\tRIF0_CLK_C_MARK___2 = 1949,\n\tRX5_B_MARK___2 = 1950,\n\tIP14_11_8_MARK___2 = 1951,\n\tMLB_CLK_MARK___2 = 1952,\n\tMSIOF1_SCK_F_MARK___2 = 1953,\n\tSCL1_B_MARK___2 = 1954,\n\tIP15_11_8_MARK___2 = 1955,\n\tSSI_SCK349_MARK___2 = 1956,\n\tMSIOF1_SS1_A_MARK___2 = 1957,\n\tSTP_OPWM_0_A_MARK___2 = 1958,\n\tIP12_15_12_MARK___2 = 1959,\n\tRX1_A_MARK___3 = 1960,\n\tHRX1_A_MARK___3 = 1961,\n\tTS_SDAT0_C_MARK___2 = 1962,\n\tSTP_ISD_0_C_MARK___2 = 1963,\n\tRIF1_CLK_C_MARK___2 = 1964,\n\tIP13_15_12_MARK___2 = 1965,\n\tHRX0_MARK___3 = 1966,\n\tMSIOF1_RXD_D_MARK___2 = 1967,\n\tSSI_SDATA2_B_MARK___2 = 1968,\n\tTS_SDEN0_D_MARK___2 = 1969,\n\tSTP_ISEN_0_D_MARK___2 = 1970,\n\tRIF0_D0_C_MARK___2 = 1971,\n\tIP14_15_12_MARK___2 = 1972,\n\tMLB_SIG_MARK___2 = 1973,\n\tRX1_B_MARK___3 = 1974,\n\tMSIOF1_SYNC_F_MARK___2 = 1975,\n\tSDA1_B_MARK___2 = 1976,\n\tIP15_15_12_MARK___2 = 1977,\n\tSSI_WS349_MARK___2 = 1978,\n\tHCTS2_N_A_MARK___2 = 1979,\n\tMSIOF1_SS2_A_MARK___2 = 1980,\n\tSTP_IVCXO27_0_A_MARK___2 = 1981,\n\tIP12_19_16_MARK___2 = 1982,\n\tTX1_A_MARK___3 = 1983,\n\tHTX1_A_MARK___3 = 1984,\n\tTS_SDEN0_C_MARK___2 = 1985,\n\tSTP_ISEN_0_C_MARK___2 = 1986,\n\tRIF1_D0_C_MARK___2 = 1987,\n\tIP13_19_16_MARK___2 = 1988,\n\tHTX0_MARK___3 = 1989,\n\tMSIOF1_TXD_D_MARK___2 = 1990,\n\tSSI_SDATA9_B_MARK___2 = 1991,\n\tTS_SDAT0_D_MARK___2 = 1992,\n\tSTP_ISD_0_D_MARK___2 = 1993,\n\tRIF0_D1_C_MARK___2 = 1994,\n\tIP14_19_16_MARK___2 = 1995,\n\tMLB_DAT_MARK___2 = 1996,\n\tTX1_B_MARK___3 = 1997,\n\tMSIOF1_RXD_F_MARK___2 = 1998,\n\tIP15_19_16_MARK___2 = 1999,\n\tSSI_SDATA3_MARK___2 = 2000,\n\tHRTS2_N_A_MARK___2 = 2001,\n\tMSIOF1_TXD_A_MARK___2 = 2002,\n\tTS_SCK0_A_MARK___2 = 2003,\n\tSTP_ISCLK_0_A_MARK___2 = 2004,\n\tRIF0_D1_A_MARK___2 = 2005,\n\tRIF2_D0_A_MARK___2 = 2006,\n\tIP12_23_20_MARK___2 = 2007,\n\tCTS1_N_MARK___2 = 2008,\n\tHCTS1_N_A_MARK___3 = 2009,\n\tMSIOF1_RXD_B_MARK___2 = 2010,\n\tTS_SDEN1_C_MARK___2 = 2011,\n\tSTP_ISEN_1_C_MARK___2 = 2012,\n\tRIF1_D0_B_MARK___2 = 2013,\n\tADIDATA_MARK___2 = 2014,\n\tIP13_23_20_MARK___2 = 2015,\n\tHCTS0_N_MARK___3 = 2016,\n\tRX2_B_MARK___2 = 2017,\n\tMSIOF1_SYNC_D_MARK___2 = 2018,\n\tSSI_SCK9_A_MARK___2 = 2019,\n\tTS_SPSYNC0_D_MARK___2 = 2020,\n\tSTP_ISSYNC_0_D_MARK___2 = 2021,\n\tRIF0_SYNC_C_MARK___2 = 2022,\n\tAUDIO_CLKOUT1_A_MARK___2 = 2023,\n\tIP14_23_20_MARK___2 = 2024,\n\tSSI_SCK01239_MARK___2 = 2025,\n\tMSIOF1_TXD_F_MARK___2 = 2026,\n\tIP15_23_20_MARK___2 = 2027,\n\tSSI_SCK4_MARK___2 = 2028,\n\tHRX2_A_MARK___2 = 2029,\n\tMSIOF1_SCK_A_MARK___2 = 2030,\n\tTS_SDAT0_A_MARK___2 = 2031,\n\tSTP_ISD_0_A_MARK___2 = 2032,\n\tRIF0_CLK_A_MARK___2 = 2033,\n\tRIF2_CLK_A_MARK___2 = 2034,\n\tIP12_27_24_MARK___2 = 2035,\n\tRTS1_N_MARK___2 = 2036,\n\tHRTS1_N_A_MARK___3 = 2037,\n\tMSIOF1_TXD_B_MARK___2 = 2038,\n\tTS_SDAT1_C_MARK___2 = 2039,\n\tSTP_ISD_1_C_MARK___2 = 2040,\n\tRIF1_D1_B_MARK___2 = 2041,\n\tADICHS0_MARK___2 = 2042,\n\tIP13_27_24_MARK___2 = 2043,\n\tHRTS0_N_MARK___3 = 2044,\n\tTX2_B_MARK___2 = 2045,\n\tMSIOF1_SS1_D_MARK___2 = 2046,\n\tSSI_WS9_A_MARK___2 = 2047,\n\tSTP_IVCXO27_0_D_MARK___2 = 2048,\n\tBPFCLK_A_MARK___2 = 2049,\n\tAUDIO_CLKOUT2_A_MARK___2 = 2050,\n\tIP14_27_24_MARK___2 = 2051,\n\tSSI_WS01239_MARK___2 = 2052,\n\tMSIOF1_SS1_F_MARK___2 = 2053,\n\tIP15_27_24_MARK___2 = 2054,\n\tSSI_WS4_MARK___2 = 2055,\n\tHTX2_A_MARK___2 = 2056,\n\tMSIOF1_SYNC_A_MARK___2 = 2057,\n\tTS_SDEN0_A_MARK___2 = 2058,\n\tSTP_ISEN_0_A_MARK___2 = 2059,\n\tRIF0_SYNC_A_MARK___2 = 2060,\n\tRIF2_SYNC_A_MARK___2 = 2061,\n\tIP12_31_28_MARK___2 = 2062,\n\tSCK2_MARK___2 = 2063,\n\tSCIF_CLK_B_MARK___2 = 2064,\n\tMSIOF1_SCK_B_MARK___2 = 2065,\n\tTS_SCK1_C_MARK___2 = 2066,\n\tSTP_ISCLK_1_C_MARK___2 = 2067,\n\tRIF1_CLK_B_MARK___2 = 2068,\n\tADICLK_MARK___2 = 2069,\n\tIP13_31_28_MARK___2 = 2070,\n\tMSIOF0_SYNC_MARK___3 = 2071,\n\tAUDIO_CLKOUT_A_MARK___2 = 2072,\n\tTX5_B_MARK___2 = 2073,\n\tBPFCLK_D_MARK___2 = 2074,\n\tIP14_31_28_MARK___2 = 2075,\n\tSSI_SDATA0_MARK___2 = 2076,\n\tMSIOF1_SS2_F_MARK___2 = 2077,\n\tIP15_31_28_MARK___2 = 2078,\n\tSSI_SDATA4_MARK___2 = 2079,\n\tHSCK2_A_MARK___2 = 2080,\n\tMSIOF1_RXD_A_MARK___2 = 2081,\n\tTS_SPSYNC0_A_MARK___2 = 2082,\n\tSTP_ISSYNC_0_A_MARK___2 = 2083,\n\tRIF0_D0_A_MARK___2 = 2084,\n\tRIF2_D1_A_MARK___2 = 2085,\n\tIP16_3_0_MARK___2 = 2086,\n\tSSI_SCK6_MARK___2 = 2087,\n\tUSB2_PWEN_MARK = 2088,\n\tSIM0_RST_D_MARK___2 = 2089,\n\tIP17_3_0_MARK___2 = 2090,\n\tAUDIO_CLKA_A_MARK___2 = 2091,\n\tIP18_3_0_MARK___2 = 2092,\n\tUSB2_CH3_PWEN_MARK = 2093,\n\tAUDIO_CLKOUT2_B_MARK___2 = 2094,\n\tSSI_SCK9_B_MARK___2 = 2095,\n\tTS_SDEN0_E_MARK___2 = 2096,\n\tSTP_ISEN_0_E_MARK___2 = 2097,\n\tRIF2_D0_B_MARK___2 = 2098,\n\tTPU0TO2_MARK___2 = 2099,\n\tFMCLK_C_MARK___2 = 2100,\n\tFMCLK_D_MARK___2 = 2101,\n\tIP16_7_4_MARK___2 = 2102,\n\tSSI_WS6_MARK___2 = 2103,\n\tUSB2_OVC_MARK = 2104,\n\tSIM0_D_D_MARK___2 = 2105,\n\tIP17_7_4_MARK___2 = 2106,\n\tAUDIO_CLKB_B_MARK___2 = 2107,\n\tSCIF_CLK_A_MARK___2 = 2108,\n\tSTP_IVCXO27_1_D_MARK___2 = 2109,\n\tREMOCON_A_MARK___2 = 2110,\n\tTCLK1_A_MARK___3 = 2111,\n\tIP18_7_4_MARK___2 = 2112,\n\tUSB2_CH3_OVC_MARK = 2113,\n\tAUDIO_CLKOUT3_B_MARK___2 = 2114,\n\tSSI_WS9_B_MARK___2 = 2115,\n\tTS_SPSYNC0_E_MARK___2 = 2116,\n\tSTP_ISSYNC_0_E_MARK___2 = 2117,\n\tRIF2_D1_B_MARK___2 = 2118,\n\tTPU0TO3_MARK___2 = 2119,\n\tFMIN_C_MARK___2 = 2120,\n\tFMIN_D_MARK___2 = 2121,\n\tIP16_11_8_MARK___2 = 2122,\n\tSSI_SDATA6_MARK___2 = 2123,\n\tSIM0_CLK_D_MARK___2 = 2124,\n\tSATA_DEVSLP_A_MARK = 2125,\n\tIP17_11_8_MARK___2 = 2126,\n\tUSB0_PWEN_MARK___2 = 2127,\n\tSIM0_RST_C_MARK___2 = 2128,\n\tTS_SCK1_D_MARK___2 = 2129,\n\tSTP_ISCLK_1_D_MARK___2 = 2130,\n\tBPFCLK_B_MARK___2 = 2131,\n\tRIF3_CLK_B_MARK___2 = 2132,\n\tHSCK2_C_MARK___2 = 2133,\n\tIP16_15_12_MARK___2 = 2134,\n\tSSI_SCK78_MARK___2 = 2135,\n\tHRX2_B_MARK___2 = 2136,\n\tMSIOF1_SCK_C_MARK___2 = 2137,\n\tTS_SCK1_A_MARK___2 = 2138,\n\tSTP_ISCLK_1_A_MARK___2 = 2139,\n\tRIF1_CLK_A_MARK___2 = 2140,\n\tRIF3_CLK_A_MARK___2 = 2141,\n\tIP17_15_12_MARK___2 = 2142,\n\tUSB0_OVC_MARK___2 = 2143,\n\tSIM0_D_C_MARK___2 = 2144,\n\tTS_SDAT1_D_MARK___2 = 2145,\n\tSTP_ISD_1_D_MARK___2 = 2146,\n\tRIF3_SYNC_B_MARK___2 = 2147,\n\tHRX2_C_MARK___2 = 2148,\n\tIP16_19_16_MARK___2 = 2149,\n\tSSI_WS78_MARK___2 = 2150,\n\tHTX2_B_MARK___2 = 2151,\n\tMSIOF1_SYNC_C_MARK___2 = 2152,\n\tTS_SDAT1_A_MARK___2 = 2153,\n\tSTP_ISD_1_A_MARK___2 = 2154,\n\tRIF1_SYNC_A_MARK___2 = 2155,\n\tRIF3_SYNC_A_MARK___2 = 2156,\n\tIP17_19_16_MARK___2 = 2157,\n\tUSB1_PWEN_MARK___2 = 2158,\n\tSIM0_CLK_C_MARK___2 = 2159,\n\tSSI_SCK1_A_MARK___2 = 2160,\n\tTS_SCK0_E_MARK___2 = 2161,\n\tSTP_ISCLK_0_E_MARK___2 = 2162,\n\tFMCLK_B_MARK___2 = 2163,\n\tRIF2_CLK_B_MARK___2 = 2164,\n\tSPEEDIN_A_MARK___2 = 2165,\n\tHTX2_C_MARK___2 = 2166,\n\tIP16_23_20_MARK___2 = 2167,\n\tSSI_SDATA7_MARK___2 = 2168,\n\tHCTS2_N_B_MARK___2 = 2169,\n\tMSIOF1_RXD_C_MARK___2 = 2170,\n\tTS_SDEN1_A_MARK___2 = 2171,\n\tSTP_ISEN_1_A_MARK___2 = 2172,\n\tRIF1_D0_A_MARK___2 = 2173,\n\tRIF3_D0_A_MARK___2 = 2174,\n\tTCLK2_A_MARK___3 = 2175,\n\tIP17_23_20_MARK___2 = 2176,\n\tUSB1_OVC_MARK___2 = 2177,\n\tMSIOF1_SS2_C_MARK___2 = 2178,\n\tSSI_WS1_A_MARK___2 = 2179,\n\tTS_SDAT0_E_MARK___2 = 2180,\n\tSTP_ISD_0_E_MARK___2 = 2181,\n\tFMIN_B_MARK___2 = 2182,\n\tRIF2_SYNC_B_MARK___2 = 2183,\n\tREMOCON_B_MARK___2 = 2184,\n\tHCTS2_N_C_MARK___2 = 2185,\n\tIP16_27_24_MARK___2 = 2186,\n\tSSI_SDATA8_MARK___2 = 2187,\n\tHRTS2_N_B_MARK___2 = 2188,\n\tMSIOF1_TXD_C_MARK___2 = 2189,\n\tTS_SPSYNC1_A_MARK___2 = 2190,\n\tSTP_ISSYNC_1_A_MARK___2 = 2191,\n\tRIF1_D1_A_MARK___2 = 2192,\n\tRIF3_D1_A_MARK___2 = 2193,\n\tIP17_27_24_MARK___2 = 2194,\n\tUSB30_PWEN_MARK___2 = 2195,\n\tAUDIO_CLKOUT_B_MARK___2 = 2196,\n\tSSI_SCK2_B_MARK___2 = 2197,\n\tTS_SDEN1_D_MARK___2 = 2198,\n\tSTP_ISEN_1_D_MARK___2 = 2199,\n\tSTP_OPWM_0_E_MARK___2 = 2200,\n\tRIF3_D0_B_MARK___2 = 2201,\n\tTCLK2_B_MARK___3 = 2202,\n\tTPU0TO0_MARK___2 = 2203,\n\tBPFCLK_C_MARK___2 = 2204,\n\tHRTS2_N_C_MARK___2 = 2205,\n\tIP16_31_28_MARK___2 = 2206,\n\tSSI_SDATA9_A_MARK___2 = 2207,\n\tHSCK2_B_MARK___2 = 2208,\n\tMSIOF1_SS1_C_MARK___2 = 2209,\n\tHSCK1_A_MARK___3 = 2210,\n\tSSI_WS1_B_MARK___2 = 2211,\n\tSCK1_MARK___2 = 2212,\n\tSTP_IVCXO27_1_A_MARK___2 = 2213,\n\tSCK5_A_MARK___2 = 2214,\n\tIP17_31_28_MARK___2 = 2215,\n\tUSB30_OVC_MARK___2 = 2216,\n\tAUDIO_CLKOUT1_B_MARK___2 = 2217,\n\tSSI_WS2_B_MARK___2 = 2218,\n\tTS_SPSYNC1_D_MARK___2 = 2219,\n\tSTP_ISSYNC_1_D_MARK___2 = 2220,\n\tSTP_IVCXO27_0_E_MARK___2 = 2221,\n\tRIF3_D1_B_MARK___2 = 2222,\n\tFSO_TOE_N_MARK___2 = 2223,\n\tTPU0TO1_MARK___2 = 2224,\n\tSEL_MSIOF3_0_MARK___2 = 2225,\n\tSEL_MSIOF3_1_MARK___2 = 2226,\n\tSEL_MSIOF3_2_MARK___2 = 2227,\n\tSEL_MSIOF3_3_MARK___2 = 2228,\n\tSEL_MSIOF3_4_MARK___2 = 2229,\n\tSEL_TSIF1_0_MARK___2 = 2230,\n\tSEL_TSIF1_1_MARK___2 = 2231,\n\tSEL_TSIF1_2_MARK___2 = 2232,\n\tSEL_TSIF1_3_MARK___2 = 2233,\n\tI2C_SEL_5_0_MARK___2 = 2234,\n\tI2C_SEL_5_1_MARK___2 = 2235,\n\tI2C_SEL_3_0_MARK___2 = 2236,\n\tI2C_SEL_3_1_MARK___2 = 2237,\n\tSEL_TSIF0_0_MARK___2 = 2238,\n\tSEL_TSIF0_1_MARK___2 = 2239,\n\tSEL_TSIF0_2_MARK___2 = 2240,\n\tSEL_TSIF0_3_MARK___2 = 2241,\n\tSEL_TSIF0_4_MARK___2 = 2242,\n\tI2C_SEL_0_0_MARK___2 = 2243,\n\tI2C_SEL_0_1_MARK___2 = 2244,\n\tSEL_MSIOF2_0_MARK___2 = 2245,\n\tSEL_MSIOF2_1_MARK___2 = 2246,\n\tSEL_MSIOF2_2_MARK___2 = 2247,\n\tSEL_MSIOF2_3_MARK___2 = 2248,\n\tSEL_FM_0_MARK___2 = 2249,\n\tSEL_FM_1_MARK___2 = 2250,\n\tSEL_FM_2_MARK___2 = 2251,\n\tSEL_FM_3_MARK___2 = 2252,\n\tSEL_MSIOF1_0_MARK___2 = 2253,\n\tSEL_MSIOF1_1_MARK___2 = 2254,\n\tSEL_MSIOF1_2_MARK___2 = 2255,\n\tSEL_MSIOF1_3_MARK___2 = 2256,\n\tSEL_MSIOF1_4_MARK___2 = 2257,\n\tSEL_MSIOF1_5_MARK___2 = 2258,\n\tSEL_MSIOF1_6_MARK___2 = 2259,\n\tSEL_TIMER_TMU1_0_MARK = 2260,\n\tSEL_TIMER_TMU1_1_MARK = 2261,\n\tSEL_SCIF5_0_MARK___2 = 2262,\n\tSEL_SCIF5_1_MARK___2 = 2263,\n\tSEL_SSP1_1_0_MARK___2 = 2264,\n\tSEL_SSP1_1_1_MARK___2 = 2265,\n\tSEL_SSP1_1_2_MARK___2 = 2266,\n\tSEL_SSP1_1_3_MARK___2 = 2267,\n\tSEL_I2C6_0_MARK___2 = 2268,\n\tSEL_I2C6_1_MARK___2 = 2269,\n\tSEL_I2C6_2_MARK___2 = 2270,\n\tSEL_LBSC_0_MARK___2 = 2271,\n\tSEL_LBSC_1_MARK___2 = 2272,\n\tSEL_SSP1_0_0_MARK___2 = 2273,\n\tSEL_SSP1_0_1_MARK___2 = 2274,\n\tSEL_SSP1_0_2_MARK___2 = 2275,\n\tSEL_SSP1_0_3_MARK___2 = 2276,\n\tSEL_SSP1_0_4_MARK___2 = 2277,\n\tSEL_IEBUS_0_MARK___2 = 2278,\n\tSEL_IEBUS_1_MARK___2 = 2279,\n\tSEL_I2C2_0_MARK___2 = 2280,\n\tSEL_I2C2_1_MARK___2 = 2281,\n\tSEL_SSI2_0_MARK___2 = 2282,\n\tSEL_SSI2_1_MARK___2 = 2283,\n\tSEL_I2C1_0_MARK___2 = 2284,\n\tSEL_I2C1_1_MARK___2 = 2285,\n\tSEL_SSI1_0_MARK___2 = 2286,\n\tSEL_SSI1_1_MARK___2 = 2287,\n\tSEL_SSI9_0_MARK___2 = 2288,\n\tSEL_SSI9_1_MARK___2 = 2289,\n\tSEL_HSCIF4_0_MARK___2 = 2290,\n\tSEL_HSCIF4_1_MARK___2 = 2291,\n\tSEL_SPEED_PULSE_0_MARK___2 = 2292,\n\tSEL_SPEED_PULSE_1_MARK___2 = 2293,\n\tSEL_TIMER_TMU2_0_MARK___2 = 2294,\n\tSEL_TIMER_TMU2_1_MARK___2 = 2295,\n\tSEL_HSCIF3_0_MARK___2 = 2296,\n\tSEL_HSCIF3_1_MARK___2 = 2297,\n\tSEL_HSCIF3_2_MARK___2 = 2298,\n\tSEL_HSCIF3_3_MARK___2 = 2299,\n\tSEL_SIMCARD_0_MARK___2 = 2300,\n\tSEL_SIMCARD_1_MARK___2 = 2301,\n\tSEL_SIMCARD_2_MARK___2 = 2302,\n\tSEL_SIMCARD_3_MARK___2 = 2303,\n\tSEL_ADGB_0_MARK___2 = 2304,\n\tSEL_ADGB_1_MARK___2 = 2305,\n\tSEL_ADGC_0_MARK___2 = 2306,\n\tSEL_ADGC_1_MARK___2 = 2307,\n\tSEL_HSCIF1_0_MARK___2 = 2308,\n\tSEL_HSCIF1_1_MARK___2 = 2309,\n\tSEL_SDHI2_0_MARK___2 = 2310,\n\tSEL_SDHI2_1_MARK___2 = 2311,\n\tSEL_SCIF4_0_MARK___2 = 2312,\n\tSEL_SCIF4_1_MARK___2 = 2313,\n\tSEL_SCIF4_2_MARK___2 = 2314,\n\tSEL_HSCIF2_0_MARK___2 = 2315,\n\tSEL_HSCIF2_1_MARK___2 = 2316,\n\tSEL_HSCIF2_2_MARK___2 = 2317,\n\tSEL_SCIF3_0_MARK___2 = 2318,\n\tSEL_SCIF3_1_MARK___2 = 2319,\n\tSEL_ETHERAVB_0_MARK___2 = 2320,\n\tSEL_ETHERAVB_1_MARK___2 = 2321,\n\tSEL_SCIF2_0_MARK___2 = 2322,\n\tSEL_SCIF2_1_MARK___2 = 2323,\n\tSEL_DRIF3_0_MARK___2 = 2324,\n\tSEL_DRIF3_1_MARK___2 = 2325,\n\tSEL_SCIF1_0_MARK___2 = 2326,\n\tSEL_SCIF1_1_MARK___2 = 2327,\n\tSEL_DRIF2_0_MARK___2 = 2328,\n\tSEL_DRIF2_1_MARK___2 = 2329,\n\tSEL_SCIF_0_MARK___2 = 2330,\n\tSEL_SCIF_1_MARK___2 = 2331,\n\tSEL_DRIF1_0_MARK___2 = 2332,\n\tSEL_DRIF1_1_MARK___2 = 2333,\n\tSEL_DRIF1_2_MARK___2 = 2334,\n\tSEL_REMOCON_0_MARK___2 = 2335,\n\tSEL_REMOCON_1_MARK___2 = 2336,\n\tSEL_DRIF0_0_MARK___2 = 2337,\n\tSEL_DRIF0_1_MARK___2 = 2338,\n\tSEL_DRIF0_2_MARK___2 = 2339,\n\tSEL_RCAN0_0_MARK___2 = 2340,\n\tSEL_RCAN0_1_MARK___2 = 2341,\n\tSEL_CANFD0_0_MARK___2 = 2342,\n\tSEL_CANFD0_1_MARK___2 = 2343,\n\tSEL_PWM6_0_MARK___2 = 2344,\n\tSEL_PWM6_1_MARK___2 = 2345,\n\tSEL_ADGA_0_MARK___2 = 2346,\n\tSEL_ADGA_1_MARK___2 = 2347,\n\tSEL_ADGA_2_MARK___2 = 2348,\n\tSEL_ADGA_3_MARK___2 = 2349,\n\tSEL_PWM5_0_MARK___2 = 2350,\n\tSEL_PWM5_1_MARK___2 = 2351,\n\tSEL_PWM4_0_MARK___2 = 2352,\n\tSEL_PWM4_1_MARK___2 = 2353,\n\tSEL_PWM3_0_MARK___2 = 2354,\n\tSEL_PWM3_1_MARK___2 = 2355,\n\tSEL_PWM2_0_MARK___2 = 2356,\n\tSEL_PWM2_1_MARK___2 = 2357,\n\tSEL_PWM1_0_MARK___2 = 2358,\n\tSEL_PWM1_1_MARK___2 = 2359,\n\tSEL_VIN4_0_MARK___2 = 2360,\n\tSEL_VIN4_1_MARK___2 = 2361,\n\tQSPI0_SPCLK_MARK___3 = 2362,\n\tQSPI0_SSL_MARK___3 = 2363,\n\tQSPI0_MOSI_IO0_MARK___3 = 2364,\n\tQSPI0_MISO_IO1_MARK___3 = 2365,\n\tQSPI0_IO2_MARK___3 = 2366,\n\tQSPI0_IO3_MARK___3 = 2367,\n\tQSPI1_SPCLK_MARK___3 = 2368,\n\tQSPI1_SSL_MARK___3 = 2369,\n\tQSPI1_MOSI_IO0_MARK___3 = 2370,\n\tQSPI1_MISO_IO1_MARK___3 = 2371,\n\tQSPI1_IO2_MARK___3 = 2372,\n\tQSPI1_IO3_MARK___3 = 2373,\n\tRPC_INT_MARK___2 = 2374,\n\tRPC_WP_MARK___2 = 2375,\n\tRPC_RESET_MARK___2 = 2376,\n\tAVB_TX_CTL_MARK___2 = 2377,\n\tAVB_TXC_MARK___2 = 2378,\n\tAVB_TD0_MARK___2 = 2379,\n\tAVB_TD1_MARK___2 = 2380,\n\tAVB_TD2_MARK___2 = 2381,\n\tAVB_TD3_MARK___2 = 2382,\n\tAVB_RX_CTL_MARK___2 = 2383,\n\tAVB_RXC_MARK___2 = 2384,\n\tAVB_RD0_MARK___2 = 2385,\n\tAVB_RD1_MARK___2 = 2386,\n\tAVB_RD2_MARK___2 = 2387,\n\tAVB_RD3_MARK___2 = 2388,\n\tAVB_TXCREFCLK_MARK___2 = 2389,\n\tAVB_MDIO_MARK___2 = 2390,\n\tPRESETOUT_MARK___2 = 2391,\n\tDU_DOTCLKIN0_MARK___2 = 2392,\n\tDU_DOTCLKIN1_MARK___2 = 2393,\n\tDU_DOTCLKIN2_MARK___2 = 2394,\n\tDU_DOTCLKIN3_MARK = 2395,\n\tTMS_MARK___2 = 2396,\n\tTDO_MARK___2 = 2397,\n\tASEBRK_MARK___2 = 2398,\n\tMLB_REF_MARK___2 = 2399,\n\tTDI_MARK___2 = 2400,\n\tTCK_MARK___2 = 2401,\n\tTRST_MARK___2 = 2402,\n\tEXTALR_MARK___2 = 2403,\n\tSCL0_MARK___3 = 2404,\n\tSDA0_MARK___3 = 2405,\n\tSCL3_MARK___3 = 2406,\n\tSDA3_MARK___3 = 2407,\n\tSCL5_MARK___3 = 2408,\n\tSDA5_MARK___3 = 2409,\n\tPINMUX_MARK_END___3 = 2410,\n};\n\nenum {\n\tPINMUX_RESERVED___4 = 0,\n\tPINMUX_DATA_BEGIN___4 = 1,\n\tGP_0_0_DATA___4 = 2,\n\tGP_0_1_DATA___4 = 3,\n\tGP_0_2_DATA___4 = 4,\n\tGP_0_3_DATA___4 = 5,\n\tGP_0_4_DATA___4 = 6,\n\tGP_0_5_DATA___4 = 7,\n\tGP_0_6_DATA___4 = 8,\n\tGP_0_7_DATA___4 = 9,\n\tGP_0_8_DATA___4 = 10,\n\tGP_0_9_DATA___4 = 11,\n\tGP_0_10_DATA___4 = 12,\n\tGP_0_11_DATA___4 = 13,\n\tGP_0_12_DATA___4 = 14,\n\tGP_0_13_DATA___4 = 15,\n\tGP_0_14_DATA___4 = 16,\n\tGP_0_15_DATA___4 = 17,\n\tGP_0_16_DATA___2 = 18,\n\tGP_0_17_DATA___2 = 19,\n\tGP_0_18_DATA___2 = 20,\n\tGP_0_19_DATA = 21,\n\tGP_0_20_DATA = 22,\n\tGP_0_21_DATA = 23,\n\tGP_1_0_DATA___4 = 24,\n\tGP_1_1_DATA___4 = 25,\n\tGP_1_2_DATA___4 = 26,\n\tGP_1_3_DATA___4 = 27,\n\tGP_1_4_DATA___4 = 28,\n\tGP_1_5_DATA___4 = 29,\n\tGP_1_6_DATA___4 = 30,\n\tGP_1_7_DATA___4 = 31,\n\tGP_1_8_DATA___4 = 32,\n\tGP_1_9_DATA___4 = 33,\n\tGP_1_10_DATA___4 = 34,\n\tGP_1_11_DATA___4 = 35,\n\tGP_1_12_DATA___4 = 36,\n\tGP_1_13_DATA___4 = 37,\n\tGP_1_14_DATA___4 = 38,\n\tGP_1_15_DATA___4 = 39,\n\tGP_1_16_DATA___4 = 40,\n\tGP_1_17_DATA___4 = 41,\n\tGP_1_18_DATA___4 = 42,\n\tGP_1_19_DATA___4 = 43,\n\tGP_1_20_DATA___4 = 44,\n\tGP_1_21_DATA___4 = 45,\n\tGP_1_22_DATA___4 = 46,\n\tGP_1_23_DATA___4 = 47,\n\tGP_1_24_DATA___4 = 48,\n\tGP_1_25_DATA___4 = 49,\n\tGP_1_26_DATA___4 = 50,\n\tGP_1_27_DATA___4 = 51,\n\tGP_2_0_DATA___4 = 52,\n\tGP_2_1_DATA___4 = 53,\n\tGP_2_2_DATA___4 = 54,\n\tGP_2_3_DATA___4 = 55,\n\tGP_2_4_DATA___4 = 56,\n\tGP_2_5_DATA___4 = 57,\n\tGP_2_6_DATA___4 = 58,\n\tGP_2_7_DATA___4 = 59,\n\tGP_2_8_DATA___4 = 60,\n\tGP_2_9_DATA___4 = 61,\n\tGP_2_10_DATA___4 = 62,\n\tGP_2_11_DATA___4 = 63,\n\tGP_2_12_DATA___4 = 64,\n\tGP_2_13_DATA___4 = 65,\n\tGP_2_14_DATA___4 = 66,\n\tGP_2_15_DATA___2 = 67,\n\tGP_2_16_DATA___2 = 68,\n\tGP_2_17_DATA___2 = 69,\n\tGP_2_18_DATA___2 = 70,\n\tGP_2_19_DATA___2 = 71,\n\tGP_2_20_DATA = 72,\n\tGP_2_21_DATA = 73,\n\tGP_2_22_DATA = 74,\n\tGP_2_23_DATA = 75,\n\tGP_2_24_DATA = 76,\n\tGP_2_25_DATA = 77,\n\tGP_2_26_DATA = 78,\n\tGP_2_27_DATA = 79,\n\tGP_2_28_DATA = 80,\n\tGP_2_29_DATA = 81,\n\tGP_3_0_DATA___4 = 82,\n\tGP_3_1_DATA___4 = 83,\n\tGP_3_2_DATA___4 = 84,\n\tGP_3_3_DATA___4 = 85,\n\tGP_3_4_DATA___4 = 86,\n\tGP_3_5_DATA___4 = 87,\n\tGP_3_6_DATA___4 = 88,\n\tGP_3_7_DATA___4 = 89,\n\tGP_3_8_DATA___4 = 90,\n\tGP_3_9_DATA___4 = 91,\n\tGP_3_10_DATA___4 = 92,\n\tGP_3_11_DATA___4 = 93,\n\tGP_3_12_DATA___4 = 94,\n\tGP_3_13_DATA___4 = 95,\n\tGP_3_14_DATA___4 = 96,\n\tGP_3_15_DATA___4 = 97,\n\tGP_3_16_DATA___2 = 98,\n\tGP_4_0_DATA___4 = 99,\n\tGP_4_1_DATA___4 = 100,\n\tGP_4_2_DATA___4 = 101,\n\tGP_4_3_DATA___4 = 102,\n\tGP_4_4_DATA___4 = 103,\n\tGP_4_5_DATA___4 = 104,\n\tGP_4_6_DATA___4 = 105,\n\tGP_4_7_DATA___4 = 106,\n\tGP_4_8_DATA___4 = 107,\n\tGP_4_9_DATA___4 = 108,\n\tGP_4_10_DATA___4 = 109,\n\tGP_4_11_DATA___4 = 110,\n\tGP_4_12_DATA___4 = 111,\n\tGP_4_13_DATA___4 = 112,\n\tGP_4_14_DATA___4 = 113,\n\tGP_4_15_DATA___4 = 114,\n\tGP_4_16_DATA___4 = 115,\n\tGP_4_17_DATA___4 = 116,\n\tGP_4_18_DATA___2 = 117,\n\tGP_4_19_DATA___2 = 118,\n\tGP_4_20_DATA___2 = 119,\n\tGP_4_21_DATA___2 = 120,\n\tGP_4_22_DATA___2 = 121,\n\tGP_4_23_DATA___2 = 122,\n\tGP_4_24_DATA___2 = 123,\n\tGP_5_0_DATA___4 = 124,\n\tGP_5_1_DATA___4 = 125,\n\tGP_5_2_DATA___4 = 126,\n\tGP_5_3_DATA___4 = 127,\n\tGP_5_4_DATA___4 = 128,\n\tGP_5_5_DATA___4 = 129,\n\tGP_5_6_DATA___4 = 130,\n\tGP_5_7_DATA___4 = 131,\n\tGP_5_8_DATA___4 = 132,\n\tGP_5_9_DATA___4 = 133,\n\tGP_5_10_DATA___4 = 134,\n\tGP_5_11_DATA___4 = 135,\n\tGP_5_12_DATA___4 = 136,\n\tGP_5_13_DATA___4 = 137,\n\tGP_5_14_DATA___4 = 138,\n\tPINMUX_DATA_END___4 = 139,\n\tPINMUX_FUNCTION_BEGIN___4 = 140,\n\tGP_0_0_FN___4 = 141,\n\tGP_0_1_FN___4 = 142,\n\tGP_0_2_FN___4 = 143,\n\tGP_0_3_FN___4 = 144,\n\tGP_0_4_FN___4 = 145,\n\tGP_0_5_FN___4 = 146,\n\tGP_0_6_FN___4 = 147,\n\tGP_0_7_FN___4 = 148,\n\tGP_0_8_FN___4 = 149,\n\tGP_0_9_FN___4 = 150,\n\tGP_0_10_FN___4 = 151,\n\tGP_0_11_FN___4 = 152,\n\tGP_0_12_FN___4 = 153,\n\tGP_0_13_FN___4 = 154,\n\tGP_0_14_FN___4 = 155,\n\tGP_0_15_FN___4 = 156,\n\tGP_0_16_FN___2 = 157,\n\tGP_0_17_FN___2 = 158,\n\tGP_0_18_FN___2 = 159,\n\tGP_0_19_FN = 160,\n\tGP_0_20_FN = 161,\n\tGP_0_21_FN = 162,\n\tGP_1_0_FN___4 = 163,\n\tGP_1_1_FN___4 = 164,\n\tGP_1_2_FN___4 = 165,\n\tGP_1_3_FN___4 = 166,\n\tGP_1_4_FN___4 = 167,\n\tGP_1_5_FN___4 = 168,\n\tGP_1_6_FN___4 = 169,\n\tGP_1_7_FN___4 = 170,\n\tGP_1_8_FN___4 = 171,\n\tGP_1_9_FN___4 = 172,\n\tGP_1_10_FN___4 = 173,\n\tGP_1_11_FN___4 = 174,\n\tGP_1_12_FN___4 = 175,\n\tGP_1_13_FN___4 = 176,\n\tGP_1_14_FN___4 = 177,\n\tGP_1_15_FN___4 = 178,\n\tGP_1_16_FN___4 = 179,\n\tGP_1_17_FN___4 = 180,\n\tGP_1_18_FN___4 = 181,\n\tGP_1_19_FN___4 = 182,\n\tGP_1_20_FN___4 = 183,\n\tGP_1_21_FN___4 = 184,\n\tGP_1_22_FN___4 = 185,\n\tGP_1_23_FN___4 = 186,\n\tGP_1_24_FN___4 = 187,\n\tGP_1_25_FN___4 = 188,\n\tGP_1_26_FN___4 = 189,\n\tGP_1_27_FN___4 = 190,\n\tGP_2_0_FN___4 = 191,\n\tGP_2_1_FN___4 = 192,\n\tGP_2_2_FN___4 = 193,\n\tGP_2_3_FN___4 = 194,\n\tGP_2_4_FN___4 = 195,\n\tGP_2_5_FN___4 = 196,\n\tGP_2_6_FN___4 = 197,\n\tGP_2_7_FN___4 = 198,\n\tGP_2_8_FN___4 = 199,\n\tGP_2_9_FN___4 = 200,\n\tGP_2_10_FN___4 = 201,\n\tGP_2_11_FN___4 = 202,\n\tGP_2_12_FN___4 = 203,\n\tGP_2_13_FN___4 = 204,\n\tGP_2_14_FN___4 = 205,\n\tGP_2_15_FN___2 = 206,\n\tGP_2_16_FN___2 = 207,\n\tGP_2_17_FN___2 = 208,\n\tGP_2_18_FN___2 = 209,\n\tGP_2_19_FN___2 = 210,\n\tGP_2_20_FN = 211,\n\tGP_2_21_FN = 212,\n\tGP_2_22_FN = 213,\n\tGP_2_23_FN = 214,\n\tGP_2_24_FN = 215,\n\tGP_2_25_FN = 216,\n\tGP_2_26_FN = 217,\n\tGP_2_27_FN = 218,\n\tGP_2_28_FN = 219,\n\tGP_2_29_FN = 220,\n\tGP_3_0_FN___4 = 221,\n\tGP_3_1_FN___4 = 222,\n\tGP_3_2_FN___4 = 223,\n\tGP_3_3_FN___4 = 224,\n\tGP_3_4_FN___4 = 225,\n\tGP_3_5_FN___4 = 226,\n\tGP_3_6_FN___4 = 227,\n\tGP_3_7_FN___4 = 228,\n\tGP_3_8_FN___4 = 229,\n\tGP_3_9_FN___4 = 230,\n\tGP_3_10_FN___4 = 231,\n\tGP_3_11_FN___4 = 232,\n\tGP_3_12_FN___4 = 233,\n\tGP_3_13_FN___4 = 234,\n\tGP_3_14_FN___4 = 235,\n\tGP_3_15_FN___4 = 236,\n\tGP_3_16_FN___2 = 237,\n\tGP_4_0_FN___4 = 238,\n\tGP_4_1_FN___4 = 239,\n\tGP_4_2_FN___4 = 240,\n\tGP_4_3_FN___4 = 241,\n\tGP_4_4_FN___4 = 242,\n\tGP_4_5_FN___4 = 243,\n\tGP_4_6_FN___4 = 244,\n\tGP_4_7_FN___4 = 245,\n\tGP_4_8_FN___4 = 246,\n\tGP_4_9_FN___4 = 247,\n\tGP_4_10_FN___4 = 248,\n\tGP_4_11_FN___4 = 249,\n\tGP_4_12_FN___4 = 250,\n\tGP_4_13_FN___4 = 251,\n\tGP_4_14_FN___4 = 252,\n\tGP_4_15_FN___4 = 253,\n\tGP_4_16_FN___4 = 254,\n\tGP_4_17_FN___4 = 255,\n\tGP_4_18_FN___2 = 256,\n\tGP_4_19_FN___2 = 257,\n\tGP_4_20_FN___2 = 258,\n\tGP_4_21_FN___2 = 259,\n\tGP_4_22_FN___2 = 260,\n\tGP_4_23_FN___2 = 261,\n\tGP_4_24_FN___2 = 262,\n\tGP_5_0_FN___4 = 263,\n\tGP_5_1_FN___4 = 264,\n\tGP_5_2_FN___4 = 265,\n\tGP_5_3_FN___4 = 266,\n\tGP_5_4_FN___4 = 267,\n\tGP_5_5_FN___4 = 268,\n\tGP_5_6_FN___4 = 269,\n\tGP_5_7_FN___4 = 270,\n\tGP_5_8_FN___4 = 271,\n\tGP_5_9_FN___4 = 272,\n\tGP_5_10_FN___4 = 273,\n\tGP_5_11_FN___4 = 274,\n\tGP_5_12_FN___4 = 275,\n\tGP_5_13_FN___4 = 276,\n\tGP_5_14_FN___4 = 277,\n\tFN_GETHER_LINK_A = 278,\n\tFN_GETHER_PHY_INT_A = 279,\n\tFN_GETHER_MAGIC = 280,\n\tFN_GETHER_MDC_A = 281,\n\tFN_GETHER_MDIO_A = 282,\n\tFN_GETHER_TXCREFCLK_MEGA = 283,\n\tFN_AVB_LINK___3 = 284,\n\tFN_GETHER_TXCREFCLK = 285,\n\tFN_AVB_PHY_INT___3 = 286,\n\tFN_GETHER_TD3 = 287,\n\tFN_AVB_MAGIC___3 = 288,\n\tFN_GETHER_TD2 = 289,\n\tFN_AVB_MDC___3 = 290,\n\tFN_GETHER_TD1 = 291,\n\tFN_AVB_MDIO = 292,\n\tFN_GETHER_TD0 = 293,\n\tFN_RPC_INT_N___2 = 294,\n\tFN_AVB_TXCREFCLK = 295,\n\tFN_GETHER_TXC = 296,\n\tFN_RPC_WP_N___2 = 297,\n\tFN_AVB_TD3 = 298,\n\tFN_GETHER_TX_CTL = 299,\n\tFN_RPC_RESET_N___2 = 300,\n\tFN_AVB_TD2 = 301,\n\tFN_GETHER_RD3 = 302,\n\tFN_QSPI1_SSL___2 = 303,\n\tFN_AVB_TD1 = 304,\n\tFN_GETHER_RD2 = 305,\n\tFN_QSPI1_IO3___2 = 306,\n\tFN_AVB_TD0 = 307,\n\tFN_GETHER_RD1 = 308,\n\tFN_QSPI1_IO2___2 = 309,\n\tFN_AVB_TXC = 310,\n\tFN_GETHER_RD0 = 311,\n\tFN_QSPI1_MISO_IO1___2 = 312,\n\tFN_AVB_TX_CTL = 313,\n\tFN_GETHER_RXC = 314,\n\tFN_QSPI1_MOSI_IO0___2 = 315,\n\tFN_AVB_RD3 = 316,\n\tFN_GETHER_RX_CTL = 317,\n\tFN_QSPI1_SPCLK___2 = 318,\n\tFN_AVB_RD2 = 319,\n\tFN_QSPI0_SSL___2 = 320,\n\tFN_AVB_RD1 = 321,\n\tFN_QSPI0_IO3___2 = 322,\n\tFN_AVB_RD0 = 323,\n\tFN_QSPI0_IO2___2 = 324,\n\tFN_AVB_RXC = 325,\n\tFN_QSPI0_MISO_IO1___2 = 326,\n\tFN_AVB_RX_CTL = 327,\n\tFN_QSPI0_MOSI_IO0___2 = 328,\n\tFN_QSPI0_SPCLK___2 = 329,\n\tFN_IP0_3_0___3 = 330,\n\tFN_DU_DR2___3 = 331,\n\tFN_SCK4___2 = 332,\n\tFN_GETHER_RMII_CRS_DV = 333,\n\tFN_A0___3 = 334,\n\tFN_IP1_3_0___3 = 335,\n\tFN_DU_DG4___3 = 336,\n\tFN_SCL5___2 = 337,\n\tFN_A8___3 = 338,\n\tFN_IP2_3_0___3 = 339,\n\tFN_DU_DB6___3 = 340,\n\tFN_MSIOF3_RXD___2 = 341,\n\tFN_A16___3 = 342,\n\tFN_IP3_3_0___3 = 343,\n\tFN_VI0_CLKENB = 344,\n\tFN_MSIOF2_RXD___2 = 345,\n\tFN_RX3 = 346,\n\tFN_RD_WR_N___3 = 347,\n\tFN_HCTS3_N___3 = 348,\n\tFN_IP0_7_4___3 = 349,\n\tFN_DU_DR3___3 = 350,\n\tFN_RX4___2 = 351,\n\tFN_GETHER_RMII_RX_ER = 352,\n\tFN_A1___3 = 353,\n\tFN_IP1_7_4___3 = 354,\n\tFN_DU_DG5___3 = 355,\n\tFN_SDA5___2 = 356,\n\tFN_GETHER_MDC_B = 357,\n\tFN_A9___3 = 358,\n\tFN_IP2_7_4___3 = 359,\n\tFN_DU_DB7___3 = 360,\n\tFN_MSIOF3_TXD___2 = 361,\n\tFN_A17___3 = 362,\n\tFN_IP3_7_4___3 = 363,\n\tFN_VI0_HSYNC_N = 364,\n\tFN_MSIOF2_TXD___2 = 365,\n\tFN_TX3 = 366,\n\tFN_HRTS3_N___3 = 367,\n\tFN_IP0_11_8___3 = 368,\n\tFN_DU_DR4___3 = 369,\n\tFN_TX4___2 = 370,\n\tFN_GETHER_RMII_RXD0 = 371,\n\tFN_A2___3 = 372,\n\tFN_IP1_11_8___3 = 373,\n\tFN_DU_DG6___3 = 374,\n\tFN_SCIF_CLK_A___3 = 375,\n\tFN_GETHER_MDIO_B = 376,\n\tFN_A10___3 = 377,\n\tFN_IP2_11_8___3 = 378,\n\tFN_DU_DOTCLKOUT = 379,\n\tFN_MSIOF3_SS1___2 = 380,\n\tFN_GETHER_LINK_B = 381,\n\tFN_A18___3 = 382,\n\tFN_IP3_11_8___3 = 383,\n\tFN_VI0_VSYNC_N = 384,\n\tFN_MSIOF2_SYNC___2 = 385,\n\tFN_CTS3_N___3 = 386,\n\tFN_HTX3 = 387,\n\tFN_IP0_15_12___3 = 388,\n\tFN_DU_DR5___3 = 389,\n\tFN_CTS4_N___2 = 390,\n\tFN_GETHER_RMII_RXD1 = 391,\n\tFN_A3___3 = 392,\n\tFN_IP1_15_12___3 = 393,\n\tFN_DU_DG7___3 = 394,\n\tFN_HRX0_A = 395,\n\tFN_A11___3 = 396,\n\tFN_IP2_15_12___3 = 397,\n\tFN_DU_EXHSYNC_DU_HSYNC___3 = 398,\n\tFN_MSIOF3_SS2___2 = 399,\n\tFN_GETHER_PHY_INT_B = 400,\n\tFN_A19___3 = 401,\n\tFN_FXR_TXENA_N = 402,\n\tFN_IP3_15_12___3 = 403,\n\tFN_VI0_DATA0 = 404,\n\tFN_MSIOF2_SS1___2 = 405,\n\tFN_RTS3_N___3 = 406,\n\tFN_HRX3 = 407,\n\tFN_IP0_19_16___3 = 408,\n\tFN_DU_DR6___3 = 409,\n\tFN_RTS4_N___2 = 410,\n\tFN_GETHER_RMII_TXD_EN = 411,\n\tFN_A4___3 = 412,\n\tFN_IP1_19_16___3 = 413,\n\tFN_DU_DB2___3 = 414,\n\tFN_HSCK0_A = 415,\n\tFN_A12___3 = 416,\n\tFN_IRQ1___3 = 417,\n\tFN_IP2_19_16___3 = 418,\n\tFN_DU_EXVSYNC_DU_VSYNC___3 = 419,\n\tFN_MSIOF3_SCK___2 = 420,\n\tFN_FXR_TXENB_N = 421,\n\tFN_IP3_19_16___3 = 422,\n\tFN_VI0_DATA1 = 423,\n\tFN_MSIOF2_SS2___2 = 424,\n\tFN_SCK1___3 = 425,\n\tFN_SPEEDIN_A___3 = 426,\n\tFN_IP0_23_20___3 = 427,\n\tFN_DU_DR7___3 = 428,\n\tFN_GETHER_RMII_TXD0 = 429,\n\tFN_A5___3 = 430,\n\tFN_IP1_23_20___3 = 431,\n\tFN_DU_DB3___3 = 432,\n\tFN_HRTS0_N_A = 433,\n\tFN_A13___3 = 434,\n\tFN_IRQ2___3 = 435,\n\tFN_IP2_23_20___3 = 436,\n\tFN_DU_EXODDF_DU_ODDF_DISP_CDE___3 = 437,\n\tFN_MSIOF3_SYNC___2 = 438,\n\tFN_IP3_23_20___3 = 439,\n\tFN_VI0_DATA2 = 440,\n\tFN_AVB_AVTP_PPS___3 = 441,\n\tFN_IP0_27_24___3 = 442,\n\tFN_DU_DG2___3 = 443,\n\tFN_GETHER_RMII_TXD1 = 444,\n\tFN_A6___3 = 445,\n\tFN_IP1_27_24___3 = 446,\n\tFN_DU_DB4___3 = 447,\n\tFN_HCTS0_N_A = 448,\n\tFN_A14___3 = 449,\n\tFN_IRQ3___3 = 450,\n\tFN_IP2_27_24___3 = 451,\n\tFN_IRQ0___3 = 452,\n\tFN_IP3_27_24___3 = 453,\n\tFN_VI0_DATA3 = 454,\n\tFN_HSCK1 = 455,\n\tFN_IP0_31_28___3 = 456,\n\tFN_DU_DG3___3 = 457,\n\tFN_CPG_CPCKOUT = 458,\n\tFN_GETHER_RMII_REFCLK = 459,\n\tFN_A7___3 = 460,\n\tFN_PWMFSW0 = 461,\n\tFN_IP1_31_28___3 = 462,\n\tFN_DU_DB5___3 = 463,\n\tFN_HTX0_A = 464,\n\tFN_PWM0_A = 465,\n\tFN_A15___3 = 466,\n\tFN_IP2_31_28___3 = 467,\n\tFN_VI0_CLK = 468,\n\tFN_MSIOF2_SCK___2 = 469,\n\tFN_SCK3___3 = 470,\n\tFN_HSCK3___3 = 471,\n\tFN_IP3_31_28___3 = 472,\n\tFN_VI0_DATA4 = 473,\n\tFN_HRTS1_N = 474,\n\tFN_RX1_A___4 = 475,\n\tFN_IP4_3_0___3 = 476,\n\tFN_VI0_DATA5 = 477,\n\tFN_HCTS1_N = 478,\n\tFN_TX1_A___4 = 479,\n\tFN_IP5_3_0___3 = 480,\n\tFN_VI1_CLK = 481,\n\tFN_MSIOF1_RXD___2 = 482,\n\tFN_CS0_N___3 = 483,\n\tFN_IP6_3_0___3 = 484,\n\tFN_VI1_DATA4 = 485,\n\tFN_CANFD_CLK_B = 486,\n\tFN_D7___3 = 487,\n\tFN_MMC_D0 = 488,\n\tFN_IP7_3_0___3 = 489,\n\tFN_VI1_FIELD = 490,\n\tFN_SDA4___2 = 491,\n\tFN_D15___3 = 492,\n\tFN_MMC_D7___2 = 493,\n\tFN_IP4_7_4___3 = 494,\n\tFN_VI0_DATA6 = 495,\n\tFN_HTX1 = 496,\n\tFN_CTS1_N___3 = 497,\n\tFN_IP5_7_4___3 = 498,\n\tFN_VI1_CLKENB = 499,\n\tFN_MSIOF1_TXD___2 = 500,\n\tFN_D0___3 = 501,\n\tFN_IP6_7_4___3 = 502,\n\tFN_VI1_DATA5 = 503,\n\tFN_D8___3 = 504,\n\tFN_MMC_D1 = 505,\n\tFN_IP7_7_4___3 = 506,\n\tFN_SCL0___2 = 507,\n\tFN_CLKOUT___3 = 508,\n\tFN_IP4_11_8___3 = 509,\n\tFN_VI0_DATA7 = 510,\n\tFN_HRX1 = 511,\n\tFN_RTS1_N___3 = 512,\n\tFN_IP5_11_8___3 = 513,\n\tFN_VI1_HSYNC_N = 514,\n\tFN_MSIOF1_SCK___2 = 515,\n\tFN_D1___3 = 516,\n\tFN_IP6_11_8___3 = 517,\n\tFN_VI1_DATA6 = 518,\n\tFN_D9___3 = 519,\n\tFN_MMC_D2 = 520,\n\tFN_IP7_11_8___3 = 521,\n\tFN_SDA0___2 = 522,\n\tFN_BS_N___3 = 523,\n\tFN_SCK0___4 = 524,\n\tFN_HSCK0_B = 525,\n\tFN_IP4_15_12___3 = 526,\n\tFN_VI0_DATA8 = 527,\n\tFN_HSCK2___2 = 528,\n\tFN_IP5_15_12___3 = 529,\n\tFN_VI1_VSYNC_N = 530,\n\tFN_MSIOF1_SYNC___2 = 531,\n\tFN_D2___3 = 532,\n\tFN_IP6_15_12___3 = 533,\n\tFN_VI1_DATA7 = 534,\n\tFN_D10___3 = 535,\n\tFN_MMC_D3 = 536,\n\tFN_IP7_15_12 = 537,\n\tFN_SCL1___2 = 538,\n\tFN_TPU0TO2___3 = 539,\n\tFN_RD_N___3 = 540,\n\tFN_CTS0_N___4 = 541,\n\tFN_HCTS0_N_B = 542,\n\tFN_IP4_19_16___3 = 543,\n\tFN_VI0_DATA9 = 544,\n\tFN_HCTS2_N___2 = 545,\n\tFN_PWM1_A___4 = 546,\n\tFN_IP5_19_16___3 = 547,\n\tFN_VI1_DATA0 = 548,\n\tFN_MSIOF1_SS1___2 = 549,\n\tFN_D3___3 = 550,\n\tFN_MMC_WP = 551,\n\tFN_IP6_19_16___3 = 552,\n\tFN_VI1_DATA8 = 553,\n\tFN_D11___3 = 554,\n\tFN_MMC_CLK = 555,\n\tFN_IP7_19_16___3 = 556,\n\tFN_SDA1___2 = 557,\n\tFN_TPU0TO3___3 = 558,\n\tFN_WE0_N___3 = 559,\n\tFN_RTS0_N___4 = 560,\n\tFN_HRTS0_N_B = 561,\n\tFN_IP4_23_20___3 = 562,\n\tFN_VI0_DATA10 = 563,\n\tFN_HRTS2_N___2 = 564,\n\tFN_PWM2_A___3 = 565,\n\tFN_IP5_23_20___3 = 566,\n\tFN_VI1_DATA1 = 567,\n\tFN_MSIOF1_SS2___2 = 568,\n\tFN_D4___3 = 569,\n\tFN_MMC_CD = 570,\n\tFN_IP6_23_20___3 = 571,\n\tFN_VI1_DATA9 = 572,\n\tFN_TCLK1_A___4 = 573,\n\tFN_D12___3 = 574,\n\tFN_MMC_D4___2 = 575,\n\tFN_IP7_23_20___3 = 576,\n\tFN_SCL2___2 = 577,\n\tFN_WE1_N___3 = 578,\n\tFN_RX0___4 = 579,\n\tFN_HRX0_B = 580,\n\tFN_IP4_27_24___3 = 581,\n\tFN_VI0_DATA11 = 582,\n\tFN_HTX2___2 = 583,\n\tFN_PWM3_A___4 = 584,\n\tFN_IP5_27_24___3 = 585,\n\tFN_VI1_DATA2 = 586,\n\tFN_CANFD0_TX_B___3 = 587,\n\tFN_D5___3 = 588,\n\tFN_MMC_DS___2 = 589,\n\tFN_IP6_27_24___3 = 590,\n\tFN_VI1_DATA10 = 591,\n\tFN_TCLK2_A___4 = 592,\n\tFN_D13___3 = 593,\n\tFN_MMC_D5___2 = 594,\n\tFN_IP7_27_24___3 = 595,\n\tFN_SDA2___2 = 596,\n\tFN_EX_WAIT0 = 597,\n\tFN_TX0___4 = 598,\n\tFN_HTX0_B = 599,\n\tFN_IP4_31_28___3 = 600,\n\tFN_VI0_FIELD = 601,\n\tFN_HRX2___2 = 602,\n\tFN_PWM4_A___3 = 603,\n\tFN_CS1_N___3 = 604,\n\tFN_IP5_31_28___3 = 605,\n\tFN_VI1_DATA3 = 606,\n\tFN_CANFD0_RX_B___3 = 607,\n\tFN_D6___3 = 608,\n\tFN_MMC_CMD = 609,\n\tFN_IP6_31_28___3 = 610,\n\tFN_VI1_DATA11 = 611,\n\tFN_SCL4___2 = 612,\n\tFN_D14___3 = 613,\n\tFN_MMC_D6___2 = 614,\n\tFN_IP7_31_28___3 = 615,\n\tFN_AVB_AVTP_MATCH = 616,\n\tFN_TPU0TO0___3 = 617,\n\tFN_IP8_3_0___3 = 618,\n\tFN_AVB_AVTP_CAPTURE = 619,\n\tFN_TPU0TO1___3 = 620,\n\tFN_IP9_3_0___3 = 621,\n\tFN_IRQ4___3 = 622,\n\tFN_VI0_DATA12 = 623,\n\tFN_IP10_3_0___3 = 624,\n\tFN_SCL3___2 = 625,\n\tFN_VI0_DATA20 = 626,\n\tFN_IP8_7_4___3 = 627,\n\tFN_CANFD0_TX_A___3 = 628,\n\tFN_FXR_TXDA___2 = 629,\n\tFN_PWM0_B = 630,\n\tFN_DU_DISP___3 = 631,\n\tFN_IP9_7_4___3 = 632,\n\tFN_IRQ5___4 = 633,\n\tFN_VI0_DATA13 = 634,\n\tFN_IP10_7_4___3 = 635,\n\tFN_SDA3___2 = 636,\n\tFN_VI0_DATA21 = 637,\n\tFN_IP8_11_8___3 = 638,\n\tFN_CANFD0_RX_A___3 = 639,\n\tFN_RXDA_EXTFXR___2 = 640,\n\tFN_PWM1_B___4 = 641,\n\tFN_DU_CDE___3 = 642,\n\tFN_IP9_11_8___3 = 643,\n\tFN_MSIOF0_RXD___4 = 644,\n\tFN_DU_DR0___3 = 645,\n\tFN_VI0_DATA14 = 646,\n\tFN_IP10_11_8___3 = 647,\n\tFN_FSO_CFE_0_N___3 = 648,\n\tFN_VI0_DATA22 = 649,\n\tFN_IP8_15_12___3 = 650,\n\tFN_CANFD1_TX___4 = 651,\n\tFN_FXR_TXDB___2 = 652,\n\tFN_PWM2_B___3 = 653,\n\tFN_TCLK1_B___4 = 654,\n\tFN_TX1_B___4 = 655,\n\tFN_IP9_15_12___3 = 656,\n\tFN_MSIOF0_TXD___4 = 657,\n\tFN_DU_DR1___3 = 658,\n\tFN_VI0_DATA15 = 659,\n\tFN_IP10_15_12___3 = 660,\n\tFN_FSO_CFE_1_N___3 = 661,\n\tFN_VI0_DATA23 = 662,\n\tFN_IP8_19_16___3 = 663,\n\tFN_CANFD1_RX___4 = 664,\n\tFN_RXDB_EXTFXR___2 = 665,\n\tFN_PWM3_B___4 = 666,\n\tFN_TCLK2_B___4 = 667,\n\tFN_RX1_B___4 = 668,\n\tFN_IP9_19_16___3 = 669,\n\tFN_MSIOF0_SCK___4 = 670,\n\tFN_DU_DG0___3 = 671,\n\tFN_VI0_DATA16 = 672,\n\tFN_IP10_19_16___3 = 673,\n\tFN_FSO_TOE_N___3 = 674,\n\tFN_IP8_23_20___3 = 675,\n\tFN_CANFD_CLK_A = 676,\n\tFN_CLK_EXTFXR___2 = 677,\n\tFN_PWM4_B___3 = 678,\n\tFN_SPEEDIN_B___3 = 679,\n\tFN_SCIF_CLK_B___3 = 680,\n\tFN_IP9_23_20___3 = 681,\n\tFN_MSIOF0_SYNC___4 = 682,\n\tFN_DU_DG1___3 = 683,\n\tFN_VI0_DATA17 = 684,\n\tFN_IP8_27_24___3 = 685,\n\tFN_DIGRF_CLKIN = 686,\n\tFN_DIGRF_CLKEN_IN = 687,\n\tFN_IP9_27_24___3 = 688,\n\tFN_MSIOF0_SS1___4 = 689,\n\tFN_DU_DB0___3 = 690,\n\tFN_TCLK3 = 691,\n\tFN_VI0_DATA18 = 692,\n\tFN_IP8_31_28___3 = 693,\n\tFN_DIGRF_CLKOUT = 694,\n\tFN_DIGRF_CLKEN_OUT = 695,\n\tFN_IP9_31_28___3 = 696,\n\tFN_MSIOF0_SS2___4 = 697,\n\tFN_DU_DB1___3 = 698,\n\tFN_TCLK4 = 699,\n\tFN_VI0_DATA19 = 700,\n\tFN_SEL_CANFD0_0___3 = 701,\n\tFN_SEL_CANFD0_1___3 = 702,\n\tFN_SEL_GETHER_0 = 703,\n\tFN_SEL_GETHER_1 = 704,\n\tFN_SEL_HSCIF0_0 = 705,\n\tFN_SEL_HSCIF0_1 = 706,\n\tFN_SEL_PWM0_0 = 707,\n\tFN_SEL_PWM0_1 = 708,\n\tFN_SEL_PWM1_0___3 = 709,\n\tFN_SEL_PWM1_1___3 = 710,\n\tFN_SEL_PWM2_0___3 = 711,\n\tFN_SEL_PWM2_1___3 = 712,\n\tFN_SEL_PWM3_0___3 = 713,\n\tFN_SEL_PWM3_1___3 = 714,\n\tFN_SEL_PWM4_0___3 = 715,\n\tFN_SEL_PWM4_1___3 = 716,\n\tFN_SEL_RSP_0 = 717,\n\tFN_SEL_RSP_1 = 718,\n\tFN_SEL_SCIF1_0___3 = 719,\n\tFN_SEL_SCIF1_1___3 = 720,\n\tFN_SEL_TMU_0 = 721,\n\tFN_SEL_TMU_1 = 722,\n\tPINMUX_FUNCTION_END___4 = 723,\n\tPINMUX_MARK_BEGIN___4 = 724,\n\tGETHER_LINK_A_MARK = 725,\n\tGETHER_PHY_INT_A_MARK = 726,\n\tGETHER_MAGIC_MARK = 727,\n\tGETHER_MDC_A_MARK = 728,\n\tGETHER_MDIO_A_MARK = 729,\n\tGETHER_TXCREFCLK_MEGA_MARK = 730,\n\tAVB_LINK_MARK___3 = 731,\n\tGETHER_TXCREFCLK_MARK = 732,\n\tAVB_PHY_INT_MARK___3 = 733,\n\tGETHER_TD3_MARK = 734,\n\tAVB_MAGIC_MARK___3 = 735,\n\tGETHER_TD2_MARK = 736,\n\tAVB_MDC_MARK___3 = 737,\n\tGETHER_TD1_MARK = 738,\n\tAVB_MDIO_MARK___3 = 739,\n\tGETHER_TD0_MARK = 740,\n\tRPC_INT_N_MARK___2 = 741,\n\tAVB_TXCREFCLK_MARK___3 = 742,\n\tGETHER_TXC_MARK = 743,\n\tRPC_WP_N_MARK___2 = 744,\n\tAVB_TD3_MARK___3 = 745,\n\tGETHER_TX_CTL_MARK = 746,\n\tRPC_RESET_N_MARK___2 = 747,\n\tAVB_TD2_MARK___3 = 748,\n\tGETHER_RD3_MARK = 749,\n\tQSPI1_SSL_MARK___4 = 750,\n\tAVB_TD1_MARK___3 = 751,\n\tGETHER_RD2_MARK = 752,\n\tQSPI1_IO3_MARK___4 = 753,\n\tAVB_TD0_MARK___3 = 754,\n\tGETHER_RD1_MARK = 755,\n\tQSPI1_IO2_MARK___4 = 756,\n\tAVB_TXC_MARK___3 = 757,\n\tGETHER_RD0_MARK = 758,\n\tQSPI1_MISO_IO1_MARK___4 = 759,\n\tAVB_TX_CTL_MARK___3 = 760,\n\tGETHER_RXC_MARK = 761,\n\tQSPI1_MOSI_IO0_MARK___4 = 762,\n\tAVB_RD3_MARK___3 = 763,\n\tGETHER_RX_CTL_MARK = 764,\n\tQSPI1_SPCLK_MARK___4 = 765,\n\tAVB_RD2_MARK___3 = 766,\n\tQSPI0_SSL_MARK___4 = 767,\n\tAVB_RD1_MARK___3 = 768,\n\tQSPI0_IO3_MARK___4 = 769,\n\tAVB_RD0_MARK___3 = 770,\n\tQSPI0_IO2_MARK___4 = 771,\n\tAVB_RXC_MARK___3 = 772,\n\tQSPI0_MISO_IO1_MARK___4 = 773,\n\tAVB_RX_CTL_MARK___3 = 774,\n\tQSPI0_MOSI_IO0_MARK___4 = 775,\n\tQSPI0_SPCLK_MARK___4 = 776,\n\tIP0_3_0_MARK___3 = 777,\n\tDU_DR2_MARK___3 = 778,\n\tSCK4_MARK___2 = 779,\n\tGETHER_RMII_CRS_DV_MARK = 780,\n\tA0_MARK___3 = 781,\n\tIP1_3_0_MARK___3 = 782,\n\tDU_DG4_MARK___3 = 783,\n\tSCL5_MARK___4 = 784,\n\tA8_MARK___3 = 785,\n\tIP2_3_0_MARK___3 = 786,\n\tDU_DB6_MARK___3 = 787,\n\tMSIOF3_RXD_MARK___2 = 788,\n\tA16_MARK___3 = 789,\n\tIP3_3_0_MARK___3 = 790,\n\tVI0_CLKENB_MARK = 791,\n\tMSIOF2_RXD_MARK___2 = 792,\n\tRX3_MARK = 793,\n\tRD_WR_N_MARK___3 = 794,\n\tHCTS3_N_MARK___3 = 795,\n\tIP0_7_4_MARK___3 = 796,\n\tDU_DR3_MARK___3 = 797,\n\tRX4_MARK___2 = 798,\n\tGETHER_RMII_RX_ER_MARK = 799,\n\tA1_MARK___3 = 800,\n\tIP1_7_4_MARK___3 = 801,\n\tDU_DG5_MARK___3 = 802,\n\tSDA5_MARK___4 = 803,\n\tGETHER_MDC_B_MARK = 804,\n\tA9_MARK___3 = 805,\n\tIP2_7_4_MARK___3 = 806,\n\tDU_DB7_MARK___3 = 807,\n\tMSIOF3_TXD_MARK___2 = 808,\n\tA17_MARK___3 = 809,\n\tIP3_7_4_MARK___3 = 810,\n\tVI0_HSYNC_N_MARK = 811,\n\tMSIOF2_TXD_MARK___2 = 812,\n\tTX3_MARK = 813,\n\tHRTS3_N_MARK___3 = 814,\n\tIP0_11_8_MARK___3 = 815,\n\tDU_DR4_MARK___3 = 816,\n\tTX4_MARK___2 = 817,\n\tGETHER_RMII_RXD0_MARK = 818,\n\tA2_MARK___3 = 819,\n\tIP1_11_8_MARK___3 = 820,\n\tDU_DG6_MARK___3 = 821,\n\tSCIF_CLK_A_MARK___3 = 822,\n\tGETHER_MDIO_B_MARK = 823,\n\tA10_MARK___3 = 824,\n\tIP2_11_8_MARK___3 = 825,\n\tDU_DOTCLKOUT_MARK = 826,\n\tMSIOF3_SS1_MARK___2 = 827,\n\tGETHER_LINK_B_MARK = 828,\n\tA18_MARK___3 = 829,\n\tIP3_11_8_MARK___3 = 830,\n\tVI0_VSYNC_N_MARK = 831,\n\tMSIOF2_SYNC_MARK___2 = 832,\n\tCTS3_N_MARK___3 = 833,\n\tHTX3_MARK = 834,\n\tIP0_15_12_MARK___3 = 835,\n\tDU_DR5_MARK___3 = 836,\n\tCTS4_N_MARK___2 = 837,\n\tGETHER_RMII_RXD1_MARK = 838,\n\tA3_MARK___3 = 839,\n\tIP1_15_12_MARK___3 = 840,\n\tDU_DG7_MARK___3 = 841,\n\tHRX0_A_MARK = 842,\n\tA11_MARK___3 = 843,\n\tIP2_15_12_MARK___3 = 844,\n\tDU_EXHSYNC_DU_HSYNC_MARK___3 = 845,\n\tMSIOF3_SS2_MARK___2 = 846,\n\tGETHER_PHY_INT_B_MARK = 847,\n\tA19_MARK___3 = 848,\n\tFXR_TXENA_N_MARK = 849,\n\tIP3_15_12_MARK___3 = 850,\n\tVI0_DATA0_MARK = 851,\n\tMSIOF2_SS1_MARK___2 = 852,\n\tRTS3_N_MARK___3 = 853,\n\tHRX3_MARK = 854,\n\tIP0_19_16_MARK___3 = 855,\n\tDU_DR6_MARK___3 = 856,\n\tRTS4_N_MARK___2 = 857,\n\tGETHER_RMII_TXD_EN_MARK = 858,\n\tA4_MARK___3 = 859,\n\tIP1_19_16_MARK___3 = 860,\n\tDU_DB2_MARK___3 = 861,\n\tHSCK0_A_MARK = 862,\n\tA12_MARK___3 = 863,\n\tIRQ1_MARK___3 = 864,\n\tIP2_19_16_MARK___3 = 865,\n\tDU_EXVSYNC_DU_VSYNC_MARK___3 = 866,\n\tMSIOF3_SCK_MARK___2 = 867,\n\tFXR_TXENB_N_MARK = 868,\n\tIP3_19_16_MARK___3 = 869,\n\tVI0_DATA1_MARK = 870,\n\tMSIOF2_SS2_MARK___2 = 871,\n\tSCK1_MARK___3 = 872,\n\tSPEEDIN_A_MARK___3 = 873,\n\tIP0_23_20_MARK___3 = 874,\n\tDU_DR7_MARK___3 = 875,\n\tGETHER_RMII_TXD0_MARK = 876,\n\tA5_MARK___3 = 877,\n\tIP1_23_20_MARK___3 = 878,\n\tDU_DB3_MARK___3 = 879,\n\tHRTS0_N_A_MARK = 880,\n\tA13_MARK___3 = 881,\n\tIRQ2_MARK___3 = 882,\n\tIP2_23_20_MARK___3 = 883,\n\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK___3 = 884,\n\tMSIOF3_SYNC_MARK___2 = 885,\n\tIP3_23_20_MARK___3 = 886,\n\tVI0_DATA2_MARK = 887,\n\tAVB_AVTP_PPS_MARK___3 = 888,\n\tIP0_27_24_MARK___3 = 889,\n\tDU_DG2_MARK___3 = 890,\n\tGETHER_RMII_TXD1_MARK = 891,\n\tA6_MARK___3 = 892,\n\tIP1_27_24_MARK___3 = 893,\n\tDU_DB4_MARK___3 = 894,\n\tHCTS0_N_A_MARK = 895,\n\tA14_MARK___3 = 896,\n\tIRQ3_MARK___3 = 897,\n\tIP2_27_24_MARK___3 = 898,\n\tIRQ0_MARK___3 = 899,\n\tIP3_27_24_MARK___3 = 900,\n\tVI0_DATA3_MARK = 901,\n\tHSCK1_MARK = 902,\n\tIP0_31_28_MARK___3 = 903,\n\tDU_DG3_MARK___3 = 904,\n\tCPG_CPCKOUT_MARK = 905,\n\tGETHER_RMII_REFCLK_MARK = 906,\n\tA7_MARK___3 = 907,\n\tPWMFSW0_MARK = 908,\n\tIP1_31_28_MARK___3 = 909,\n\tDU_DB5_MARK___3 = 910,\n\tHTX0_A_MARK = 911,\n\tPWM0_A_MARK = 912,\n\tA15_MARK___3 = 913,\n\tIP2_31_28_MARK___3 = 914,\n\tVI0_CLK_MARK = 915,\n\tMSIOF2_SCK_MARK___2 = 916,\n\tSCK3_MARK___3 = 917,\n\tHSCK3_MARK___3 = 918,\n\tIP3_31_28_MARK___3 = 919,\n\tVI0_DATA4_MARK = 920,\n\tHRTS1_N_MARK = 921,\n\tRX1_A_MARK___4 = 922,\n\tIP4_3_0_MARK___3 = 923,\n\tVI0_DATA5_MARK = 924,\n\tHCTS1_N_MARK = 925,\n\tTX1_A_MARK___4 = 926,\n\tIP5_3_0_MARK___3 = 927,\n\tVI1_CLK_MARK = 928,\n\tMSIOF1_RXD_MARK___2 = 929,\n\tCS0_N_MARK___3 = 930,\n\tIP6_3_0_MARK___3 = 931,\n\tVI1_DATA4_MARK = 932,\n\tCANFD_CLK_B_MARK = 933,\n\tD7_MARK___3 = 934,\n\tMMC_D0_MARK = 935,\n\tIP7_3_0_MARK___3 = 936,\n\tVI1_FIELD_MARK = 937,\n\tSDA4_MARK___2 = 938,\n\tD15_MARK___3 = 939,\n\tMMC_D7_MARK___2 = 940,\n\tIP4_7_4_MARK___3 = 941,\n\tVI0_DATA6_MARK = 942,\n\tHTX1_MARK = 943,\n\tCTS1_N_MARK___3 = 944,\n\tIP5_7_4_MARK___3 = 945,\n\tVI1_CLKENB_MARK = 946,\n\tMSIOF1_TXD_MARK___2 = 947,\n\tD0_MARK___3 = 948,\n\tIP6_7_4_MARK___3 = 949,\n\tVI1_DATA5_MARK = 950,\n\tD8_MARK___3 = 951,\n\tMMC_D1_MARK = 952,\n\tIP7_7_4_MARK___3 = 953,\n\tSCL0_MARK___4 = 954,\n\tCLKOUT_MARK___3 = 955,\n\tIP4_11_8_MARK___3 = 956,\n\tVI0_DATA7_MARK = 957,\n\tHRX1_MARK = 958,\n\tRTS1_N_MARK___3 = 959,\n\tIP5_11_8_MARK___3 = 960,\n\tVI1_HSYNC_N_MARK = 961,\n\tMSIOF1_SCK_MARK___2 = 962,\n\tD1_MARK___3 = 963,\n\tIP6_11_8_MARK___3 = 964,\n\tVI1_DATA6_MARK = 965,\n\tD9_MARK___3 = 966,\n\tMMC_D2_MARK = 967,\n\tIP7_11_8_MARK___3 = 968,\n\tSDA0_MARK___4 = 969,\n\tBS_N_MARK___3 = 970,\n\tSCK0_MARK___4 = 971,\n\tHSCK0_B_MARK = 972,\n\tIP4_15_12_MARK___3 = 973,\n\tVI0_DATA8_MARK = 974,\n\tHSCK2_MARK___2 = 975,\n\tIP5_15_12_MARK___3 = 976,\n\tVI1_VSYNC_N_MARK = 977,\n\tMSIOF1_SYNC_MARK___2 = 978,\n\tD2_MARK___3 = 979,\n\tIP6_15_12_MARK___3 = 980,\n\tVI1_DATA7_MARK = 981,\n\tD10_MARK___3 = 982,\n\tMMC_D3_MARK = 983,\n\tIP7_15_12_MARK = 984,\n\tSCL1_MARK___2 = 985,\n\tTPU0TO2_MARK___3 = 986,\n\tRD_N_MARK___3 = 987,\n\tCTS0_N_MARK___4 = 988,\n\tHCTS0_N_B_MARK = 989,\n\tIP4_19_16_MARK___3 = 990,\n\tVI0_DATA9_MARK = 991,\n\tHCTS2_N_MARK___2 = 992,\n\tPWM1_A_MARK___4 = 993,\n\tIP5_19_16_MARK___3 = 994,\n\tVI1_DATA0_MARK = 995,\n\tMSIOF1_SS1_MARK___2 = 996,\n\tD3_MARK___3 = 997,\n\tMMC_WP_MARK = 998,\n\tIP6_19_16_MARK___3 = 999,\n\tVI1_DATA8_MARK = 1000,\n\tD11_MARK___3 = 1001,\n\tMMC_CLK_MARK = 1002,\n\tIP7_19_16_MARK___3 = 1003,\n\tSDA1_MARK___2 = 1004,\n\tTPU0TO3_MARK___3 = 1005,\n\tWE0_N_MARK___3 = 1006,\n\tRTS0_N_MARK___4 = 1007,\n\tHRTS0_N_B_MARK = 1008,\n\tIP4_23_20_MARK___3 = 1009,\n\tVI0_DATA10_MARK = 1010,\n\tHRTS2_N_MARK___2 = 1011,\n\tPWM2_A_MARK___3 = 1012,\n\tIP5_23_20_MARK___3 = 1013,\n\tVI1_DATA1_MARK = 1014,\n\tMSIOF1_SS2_MARK___2 = 1015,\n\tD4_MARK___3 = 1016,\n\tMMC_CD_MARK = 1017,\n\tIP6_23_20_MARK___3 = 1018,\n\tVI1_DATA9_MARK = 1019,\n\tTCLK1_A_MARK___4 = 1020,\n\tD12_MARK___3 = 1021,\n\tMMC_D4_MARK___2 = 1022,\n\tIP7_23_20_MARK___3 = 1023,\n\tSCL2_MARK___2 = 1024,\n\tWE1_N_MARK___3 = 1025,\n\tRX0_MARK___4 = 1026,\n\tHRX0_B_MARK = 1027,\n\tIP4_27_24_MARK___3 = 1028,\n\tVI0_DATA11_MARK = 1029,\n\tHTX2_MARK___2 = 1030,\n\tPWM3_A_MARK___4 = 1031,\n\tIP5_27_24_MARK___3 = 1032,\n\tVI1_DATA2_MARK = 1033,\n\tCANFD0_TX_B_MARK___3 = 1034,\n\tD5_MARK___3 = 1035,\n\tMMC_DS_MARK___2 = 1036,\n\tIP6_27_24_MARK___3 = 1037,\n\tVI1_DATA10_MARK = 1038,\n\tTCLK2_A_MARK___4 = 1039,\n\tD13_MARK___3 = 1040,\n\tMMC_D5_MARK___2 = 1041,\n\tIP7_27_24_MARK___3 = 1042,\n\tSDA2_MARK___2 = 1043,\n\tEX_WAIT0_MARK = 1044,\n\tTX0_MARK___4 = 1045,\n\tHTX0_B_MARK = 1046,\n\tIP4_31_28_MARK___3 = 1047,\n\tVI0_FIELD_MARK = 1048,\n\tHRX2_MARK___2 = 1049,\n\tPWM4_A_MARK___3 = 1050,\n\tCS1_N_MARK___3 = 1051,\n\tIP5_31_28_MARK___3 = 1052,\n\tVI1_DATA3_MARK = 1053,\n\tCANFD0_RX_B_MARK___3 = 1054,\n\tD6_MARK___3 = 1055,\n\tMMC_CMD_MARK = 1056,\n\tIP6_31_28_MARK___3 = 1057,\n\tVI1_DATA11_MARK = 1058,\n\tSCL4_MARK___2 = 1059,\n\tD14_MARK___3 = 1060,\n\tMMC_D6_MARK___2 = 1061,\n\tIP7_31_28_MARK___3 = 1062,\n\tAVB_AVTP_MATCH_MARK = 1063,\n\tTPU0TO0_MARK___3 = 1064,\n\tIP8_3_0_MARK___3 = 1065,\n\tAVB_AVTP_CAPTURE_MARK = 1066,\n\tTPU0TO1_MARK___3 = 1067,\n\tIP9_3_0_MARK___3 = 1068,\n\tIRQ4_MARK___3 = 1069,\n\tVI0_DATA12_MARK = 1070,\n\tIP10_3_0_MARK___3 = 1071,\n\tSCL3_MARK___4 = 1072,\n\tVI0_DATA20_MARK = 1073,\n\tIP8_7_4_MARK___3 = 1074,\n\tCANFD0_TX_A_MARK___3 = 1075,\n\tFXR_TXDA_MARK___2 = 1076,\n\tPWM0_B_MARK = 1077,\n\tDU_DISP_MARK___3 = 1078,\n\tIP9_7_4_MARK___3 = 1079,\n\tIRQ5_MARK___4 = 1080,\n\tVI0_DATA13_MARK = 1081,\n\tIP10_7_4_MARK___3 = 1082,\n\tSDA3_MARK___4 = 1083,\n\tVI0_DATA21_MARK = 1084,\n\tIP8_11_8_MARK___3 = 1085,\n\tCANFD0_RX_A_MARK___3 = 1086,\n\tRXDA_EXTFXR_MARK___2 = 1087,\n\tPWM1_B_MARK___4 = 1088,\n\tDU_CDE_MARK___3 = 1089,\n\tIP9_11_8_MARK___3 = 1090,\n\tMSIOF0_RXD_MARK___4 = 1091,\n\tDU_DR0_MARK___3 = 1092,\n\tVI0_DATA14_MARK = 1093,\n\tIP10_11_8_MARK___3 = 1094,\n\tFSO_CFE_0_N_MARK___3 = 1095,\n\tVI0_DATA22_MARK = 1096,\n\tIP8_15_12_MARK___3 = 1097,\n\tCANFD1_TX_MARK___4 = 1098,\n\tFXR_TXDB_MARK___2 = 1099,\n\tPWM2_B_MARK___3 = 1100,\n\tTCLK1_B_MARK___4 = 1101,\n\tTX1_B_MARK___4 = 1102,\n\tIP9_15_12_MARK___3 = 1103,\n\tMSIOF0_TXD_MARK___4 = 1104,\n\tDU_DR1_MARK___3 = 1105,\n\tVI0_DATA15_MARK = 1106,\n\tIP10_15_12_MARK___3 = 1107,\n\tFSO_CFE_1_N_MARK___3 = 1108,\n\tVI0_DATA23_MARK = 1109,\n\tIP8_19_16_MARK___3 = 1110,\n\tCANFD1_RX_MARK___4 = 1111,\n\tRXDB_EXTFXR_MARK___2 = 1112,\n\tPWM3_B_MARK___4 = 1113,\n\tTCLK2_B_MARK___4 = 1114,\n\tRX1_B_MARK___4 = 1115,\n\tIP9_19_16_MARK___3 = 1116,\n\tMSIOF0_SCK_MARK___4 = 1117,\n\tDU_DG0_MARK___3 = 1118,\n\tVI0_DATA16_MARK = 1119,\n\tIP10_19_16_MARK___3 = 1120,\n\tFSO_TOE_N_MARK___3 = 1121,\n\tIP8_23_20_MARK___3 = 1122,\n\tCANFD_CLK_A_MARK = 1123,\n\tCLK_EXTFXR_MARK___2 = 1124,\n\tPWM4_B_MARK___3 = 1125,\n\tSPEEDIN_B_MARK___3 = 1126,\n\tSCIF_CLK_B_MARK___3 = 1127,\n\tIP9_23_20_MARK___3 = 1128,\n\tMSIOF0_SYNC_MARK___4 = 1129,\n\tDU_DG1_MARK___3 = 1130,\n\tVI0_DATA17_MARK = 1131,\n\tIP8_27_24_MARK___3 = 1132,\n\tDIGRF_CLKIN_MARK = 1133,\n\tDIGRF_CLKEN_IN_MARK = 1134,\n\tIP9_27_24_MARK___3 = 1135,\n\tMSIOF0_SS1_MARK___4 = 1136,\n\tDU_DB0_MARK___3 = 1137,\n\tTCLK3_MARK = 1138,\n\tVI0_DATA18_MARK = 1139,\n\tIP8_31_28_MARK___3 = 1140,\n\tDIGRF_CLKOUT_MARK = 1141,\n\tDIGRF_CLKEN_OUT_MARK = 1142,\n\tIP9_31_28_MARK___3 = 1143,\n\tMSIOF0_SS2_MARK___4 = 1144,\n\tDU_DB1_MARK___3 = 1145,\n\tTCLK4_MARK = 1146,\n\tVI0_DATA19_MARK = 1147,\n\tSEL_CANFD0_0_MARK___3 = 1148,\n\tSEL_CANFD0_1_MARK___3 = 1149,\n\tSEL_GETHER_0_MARK = 1150,\n\tSEL_GETHER_1_MARK = 1151,\n\tSEL_HSCIF0_0_MARK = 1152,\n\tSEL_HSCIF0_1_MARK = 1153,\n\tSEL_PWM0_0_MARK = 1154,\n\tSEL_PWM0_1_MARK = 1155,\n\tSEL_PWM1_0_MARK___3 = 1156,\n\tSEL_PWM1_1_MARK___3 = 1157,\n\tSEL_PWM2_0_MARK___3 = 1158,\n\tSEL_PWM2_1_MARK___3 = 1159,\n\tSEL_PWM3_0_MARK___3 = 1160,\n\tSEL_PWM3_1_MARK___3 = 1161,\n\tSEL_PWM4_0_MARK___3 = 1162,\n\tSEL_PWM4_1_MARK___3 = 1163,\n\tSEL_RSP_0_MARK = 1164,\n\tSEL_RSP_1_MARK = 1165,\n\tSEL_SCIF1_0_MARK___3 = 1166,\n\tSEL_SCIF1_1_MARK___3 = 1167,\n\tSEL_TMU_0_MARK = 1168,\n\tSEL_TMU_1_MARK = 1169,\n\tPINMUX_MARK_END___4 = 1170,\n};\n\nenum {\n\tPINMUX_RESERVED___5 = 0,\n\tPINMUX_DATA_BEGIN___5 = 1,\n\tGP_0_0_DATA___5 = 2,\n\tGP_0_1_DATA___5 = 3,\n\tGP_0_2_DATA___5 = 4,\n\tGP_0_3_DATA___5 = 5,\n\tGP_0_4_DATA___5 = 6,\n\tGP_0_5_DATA___5 = 7,\n\tGP_0_6_DATA___5 = 8,\n\tGP_0_7_DATA___5 = 9,\n\tGP_0_8_DATA___5 = 10,\n\tGP_0_9_DATA___5 = 11,\n\tGP_0_10_DATA___5 = 12,\n\tGP_0_11_DATA___5 = 13,\n\tGP_0_12_DATA___5 = 14,\n\tGP_0_13_DATA___5 = 15,\n\tGP_0_14_DATA___5 = 16,\n\tGP_0_15_DATA___5 = 17,\n\tGP_1_0_DATA___5 = 18,\n\tGP_1_1_DATA___5 = 19,\n\tGP_1_2_DATA___5 = 20,\n\tGP_1_3_DATA___5 = 21,\n\tGP_1_4_DATA___5 = 22,\n\tGP_1_5_DATA___5 = 23,\n\tGP_1_6_DATA___5 = 24,\n\tGP_1_7_DATA___5 = 25,\n\tGP_1_8_DATA___5 = 26,\n\tGP_1_9_DATA___5 = 27,\n\tGP_1_10_DATA___5 = 28,\n\tGP_1_11_DATA___5 = 29,\n\tGP_1_12_DATA___5 = 30,\n\tGP_1_13_DATA___5 = 31,\n\tGP_1_14_DATA___5 = 32,\n\tGP_1_15_DATA___5 = 33,\n\tGP_1_16_DATA___5 = 34,\n\tGP_1_17_DATA___5 = 35,\n\tGP_1_18_DATA___5 = 36,\n\tGP_1_19_DATA___5 = 37,\n\tGP_1_20_DATA___5 = 38,\n\tGP_1_21_DATA___5 = 39,\n\tGP_1_22_DATA___5 = 40,\n\tGP_1_23_DATA___5 = 41,\n\tGP_1_24_DATA___5 = 42,\n\tGP_1_25_DATA___5 = 43,\n\tGP_1_26_DATA___5 = 44,\n\tGP_1_27_DATA___5 = 45,\n\tGP_1_28_DATA___4 = 46,\n\tGP_2_0_DATA___5 = 47,\n\tGP_2_1_DATA___5 = 48,\n\tGP_2_2_DATA___5 = 49,\n\tGP_2_3_DATA___5 = 50,\n\tGP_2_4_DATA___5 = 51,\n\tGP_2_5_DATA___5 = 52,\n\tGP_2_6_DATA___5 = 53,\n\tGP_2_7_DATA___5 = 54,\n\tGP_2_8_DATA___5 = 55,\n\tGP_2_9_DATA___5 = 56,\n\tGP_2_10_DATA___5 = 57,\n\tGP_2_11_DATA___5 = 58,\n\tGP_2_12_DATA___5 = 59,\n\tGP_2_13_DATA___5 = 60,\n\tGP_2_14_DATA___5 = 61,\n\tGP_3_0_DATA___5 = 62,\n\tGP_3_1_DATA___5 = 63,\n\tGP_3_2_DATA___5 = 64,\n\tGP_3_3_DATA___5 = 65,\n\tGP_3_4_DATA___5 = 66,\n\tGP_3_5_DATA___5 = 67,\n\tGP_3_6_DATA___5 = 68,\n\tGP_3_7_DATA___5 = 69,\n\tGP_3_8_DATA___5 = 70,\n\tGP_3_9_DATA___5 = 71,\n\tGP_3_10_DATA___5 = 72,\n\tGP_3_11_DATA___5 = 73,\n\tGP_3_12_DATA___5 = 74,\n\tGP_3_13_DATA___5 = 75,\n\tGP_3_14_DATA___5 = 76,\n\tGP_3_15_DATA___5 = 77,\n\tGP_4_0_DATA___5 = 78,\n\tGP_4_1_DATA___5 = 79,\n\tGP_4_2_DATA___5 = 80,\n\tGP_4_3_DATA___5 = 81,\n\tGP_4_4_DATA___5 = 82,\n\tGP_4_5_DATA___5 = 83,\n\tGP_4_6_DATA___5 = 84,\n\tGP_4_7_DATA___5 = 85,\n\tGP_4_8_DATA___5 = 86,\n\tGP_4_9_DATA___5 = 87,\n\tGP_4_10_DATA___5 = 88,\n\tGP_4_11_DATA___5 = 89,\n\tGP_4_12_DATA___5 = 90,\n\tGP_4_13_DATA___5 = 91,\n\tGP_4_14_DATA___5 = 92,\n\tGP_4_15_DATA___5 = 93,\n\tGP_4_16_DATA___5 = 94,\n\tGP_4_17_DATA___5 = 95,\n\tGP_5_0_DATA___5 = 96,\n\tGP_5_1_DATA___5 = 97,\n\tGP_5_2_DATA___5 = 98,\n\tGP_5_3_DATA___5 = 99,\n\tGP_5_4_DATA___5 = 100,\n\tGP_5_5_DATA___5 = 101,\n\tGP_5_6_DATA___5 = 102,\n\tGP_5_7_DATA___5 = 103,\n\tGP_5_8_DATA___5 = 104,\n\tGP_5_9_DATA___5 = 105,\n\tGP_5_10_DATA___5 = 106,\n\tGP_5_11_DATA___5 = 107,\n\tGP_5_12_DATA___5 = 108,\n\tGP_5_13_DATA___5 = 109,\n\tGP_5_14_DATA___5 = 110,\n\tGP_5_15_DATA___4 = 111,\n\tGP_5_16_DATA___4 = 112,\n\tGP_5_17_DATA___4 = 113,\n\tGP_5_18_DATA___4 = 114,\n\tGP_5_19_DATA___4 = 115,\n\tGP_5_20_DATA___4 = 116,\n\tGP_5_21_DATA___3 = 117,\n\tGP_5_22_DATA___3 = 118,\n\tGP_5_23_DATA___3 = 119,\n\tGP_5_24_DATA___3 = 120,\n\tGP_5_25_DATA___3 = 121,\n\tGP_6_0_DATA___4 = 122,\n\tGP_6_1_DATA___4 = 123,\n\tGP_6_2_DATA___4 = 124,\n\tGP_6_3_DATA___4 = 125,\n\tGP_6_4_DATA___4 = 126,\n\tGP_6_5_DATA___4 = 127,\n\tGP_6_6_DATA___4 = 128,\n\tGP_6_7_DATA___4 = 129,\n\tGP_6_8_DATA___4 = 130,\n\tGP_6_9_DATA___4 = 131,\n\tGP_6_10_DATA___4 = 132,\n\tGP_6_11_DATA___4 = 133,\n\tGP_6_12_DATA___4 = 134,\n\tGP_6_13_DATA___4 = 135,\n\tGP_6_14_DATA___4 = 136,\n\tGP_6_15_DATA___4 = 137,\n\tGP_6_16_DATA___4 = 138,\n\tGP_6_17_DATA___4 = 139,\n\tGP_6_18_DATA___4 = 140,\n\tGP_6_19_DATA___4 = 141,\n\tGP_6_20_DATA___4 = 142,\n\tGP_6_21_DATA___3 = 143,\n\tGP_6_22_DATA___3 = 144,\n\tGP_6_23_DATA___3 = 145,\n\tGP_6_24_DATA___3 = 146,\n\tGP_6_25_DATA___3 = 147,\n\tGP_6_26_DATA___3 = 148,\n\tGP_6_27_DATA___3 = 149,\n\tGP_6_28_DATA___3 = 150,\n\tGP_6_29_DATA___3 = 151,\n\tGP_6_30_DATA___3 = 152,\n\tGP_6_31_DATA___3 = 153,\n\tGP_7_0_DATA___4 = 154,\n\tGP_7_1_DATA___4 = 155,\n\tGP_7_2_DATA___4 = 156,\n\tGP_7_3_DATA___4 = 157,\n\tPINMUX_DATA_END___5 = 158,\n\tPINMUX_FUNCTION_BEGIN___5 = 159,\n\tGP_0_0_FN___5 = 160,\n\tGP_0_1_FN___5 = 161,\n\tGP_0_2_FN___5 = 162,\n\tGP_0_3_FN___5 = 163,\n\tGP_0_4_FN___5 = 164,\n\tGP_0_5_FN___5 = 165,\n\tGP_0_6_FN___5 = 166,\n\tGP_0_7_FN___5 = 167,\n\tGP_0_8_FN___5 = 168,\n\tGP_0_9_FN___5 = 169,\n\tGP_0_10_FN___5 = 170,\n\tGP_0_11_FN___5 = 171,\n\tGP_0_12_FN___5 = 172,\n\tGP_0_13_FN___5 = 173,\n\tGP_0_14_FN___5 = 174,\n\tGP_0_15_FN___5 = 175,\n\tGP_1_0_FN___5 = 176,\n\tGP_1_1_FN___5 = 177,\n\tGP_1_2_FN___5 = 178,\n\tGP_1_3_FN___5 = 179,\n\tGP_1_4_FN___5 = 180,\n\tGP_1_5_FN___5 = 181,\n\tGP_1_6_FN___5 = 182,\n\tGP_1_7_FN___5 = 183,\n\tGP_1_8_FN___5 = 184,\n\tGP_1_9_FN___5 = 185,\n\tGP_1_10_FN___5 = 186,\n\tGP_1_11_FN___5 = 187,\n\tGP_1_12_FN___5 = 188,\n\tGP_1_13_FN___5 = 189,\n\tGP_1_14_FN___5 = 190,\n\tGP_1_15_FN___5 = 191,\n\tGP_1_16_FN___5 = 192,\n\tGP_1_17_FN___5 = 193,\n\tGP_1_18_FN___5 = 194,\n\tGP_1_19_FN___5 = 195,\n\tGP_1_20_FN___5 = 196,\n\tGP_1_21_FN___5 = 197,\n\tGP_1_22_FN___5 = 198,\n\tGP_1_23_FN___5 = 199,\n\tGP_1_24_FN___5 = 200,\n\tGP_1_25_FN___5 = 201,\n\tGP_1_26_FN___5 = 202,\n\tGP_1_27_FN___5 = 203,\n\tGP_1_28_FN___4 = 204,\n\tGP_2_0_FN___5 = 205,\n\tGP_2_1_FN___5 = 206,\n\tGP_2_2_FN___5 = 207,\n\tGP_2_3_FN___5 = 208,\n\tGP_2_4_FN___5 = 209,\n\tGP_2_5_FN___5 = 210,\n\tGP_2_6_FN___5 = 211,\n\tGP_2_7_FN___5 = 212,\n\tGP_2_8_FN___5 = 213,\n\tGP_2_9_FN___5 = 214,\n\tGP_2_10_FN___5 = 215,\n\tGP_2_11_FN___5 = 216,\n\tGP_2_12_FN___5 = 217,\n\tGP_2_13_FN___5 = 218,\n\tGP_2_14_FN___5 = 219,\n\tGP_3_0_FN___5 = 220,\n\tGP_3_1_FN___5 = 221,\n\tGP_3_2_FN___5 = 222,\n\tGP_3_3_FN___5 = 223,\n\tGP_3_4_FN___5 = 224,\n\tGP_3_5_FN___5 = 225,\n\tGP_3_6_FN___5 = 226,\n\tGP_3_7_FN___5 = 227,\n\tGP_3_8_FN___5 = 228,\n\tGP_3_9_FN___5 = 229,\n\tGP_3_10_FN___5 = 230,\n\tGP_3_11_FN___5 = 231,\n\tGP_3_12_FN___5 = 232,\n\tGP_3_13_FN___5 = 233,\n\tGP_3_14_FN___5 = 234,\n\tGP_3_15_FN___5 = 235,\n\tGP_4_0_FN___5 = 236,\n\tGP_4_1_FN___5 = 237,\n\tGP_4_2_FN___5 = 238,\n\tGP_4_3_FN___5 = 239,\n\tGP_4_4_FN___5 = 240,\n\tGP_4_5_FN___5 = 241,\n\tGP_4_6_FN___5 = 242,\n\tGP_4_7_FN___5 = 243,\n\tGP_4_8_FN___5 = 244,\n\tGP_4_9_FN___5 = 245,\n\tGP_4_10_FN___5 = 246,\n\tGP_4_11_FN___5 = 247,\n\tGP_4_12_FN___5 = 248,\n\tGP_4_13_FN___5 = 249,\n\tGP_4_14_FN___5 = 250,\n\tGP_4_15_FN___5 = 251,\n\tGP_4_16_FN___5 = 252,\n\tGP_4_17_FN___5 = 253,\n\tGP_5_0_FN___5 = 254,\n\tGP_5_1_FN___5 = 255,\n\tGP_5_2_FN___5 = 256,\n\tGP_5_3_FN___5 = 257,\n\tGP_5_4_FN___5 = 258,\n\tGP_5_5_FN___5 = 259,\n\tGP_5_6_FN___5 = 260,\n\tGP_5_7_FN___5 = 261,\n\tGP_5_8_FN___5 = 262,\n\tGP_5_9_FN___5 = 263,\n\tGP_5_10_FN___5 = 264,\n\tGP_5_11_FN___5 = 265,\n\tGP_5_12_FN___5 = 266,\n\tGP_5_13_FN___5 = 267,\n\tGP_5_14_FN___5 = 268,\n\tGP_5_15_FN___4 = 269,\n\tGP_5_16_FN___4 = 270,\n\tGP_5_17_FN___4 = 271,\n\tGP_5_18_FN___4 = 272,\n\tGP_5_19_FN___4 = 273,\n\tGP_5_20_FN___4 = 274,\n\tGP_5_21_FN___3 = 275,\n\tGP_5_22_FN___3 = 276,\n\tGP_5_23_FN___3 = 277,\n\tGP_5_24_FN___3 = 278,\n\tGP_5_25_FN___3 = 279,\n\tGP_6_0_FN___4 = 280,\n\tGP_6_1_FN___4 = 281,\n\tGP_6_2_FN___4 = 282,\n\tGP_6_3_FN___4 = 283,\n\tGP_6_4_FN___4 = 284,\n\tGP_6_5_FN___4 = 285,\n\tGP_6_6_FN___4 = 286,\n\tGP_6_7_FN___4 = 287,\n\tGP_6_8_FN___4 = 288,\n\tGP_6_9_FN___4 = 289,\n\tGP_6_10_FN___4 = 290,\n\tGP_6_11_FN___4 = 291,\n\tGP_6_12_FN___4 = 292,\n\tGP_6_13_FN___4 = 293,\n\tGP_6_14_FN___4 = 294,\n\tGP_6_15_FN___4 = 295,\n\tGP_6_16_FN___4 = 296,\n\tGP_6_17_FN___4 = 297,\n\tGP_6_18_FN___4 = 298,\n\tGP_6_19_FN___4 = 299,\n\tGP_6_20_FN___4 = 300,\n\tGP_6_21_FN___3 = 301,\n\tGP_6_22_FN___3 = 302,\n\tGP_6_23_FN___3 = 303,\n\tGP_6_24_FN___3 = 304,\n\tGP_6_25_FN___3 = 305,\n\tGP_6_26_FN___3 = 306,\n\tGP_6_27_FN___3 = 307,\n\tGP_6_28_FN___3 = 308,\n\tGP_6_29_FN___3 = 309,\n\tGP_6_30_FN___3 = 310,\n\tGP_6_31_FN___3 = 311,\n\tGP_7_0_FN___4 = 312,\n\tGP_7_1_FN___4 = 313,\n\tGP_7_2_FN___4 = 314,\n\tGP_7_3_FN___4 = 315,\n\tFN_CLKOUT___4 = 316,\n\tFN_MSIOF0_RXD___5 = 317,\n\tFN_MSIOF0_TXD___5 = 318,\n\tFN_MSIOF0_SCK___5 = 319,\n\tFN_SSI_SDATA5___3 = 320,\n\tFN_SSI_WS5___3 = 321,\n\tFN_SSI_SCK5___3 = 322,\n\tFN_GP7_03___3 = 323,\n\tFN_GP7_02___3 = 324,\n\tFN_AVS2___3 = 325,\n\tFN_AVS1___4 = 326,\n\tFN_IP0_3_0___4 = 327,\n\tFN_AVB_MDC___4 = 328,\n\tFN_MSIOF2_SS2_C___3 = 329,\n\tFN_IP1_3_0___4 = 330,\n\tFN_IRQ2___4 = 331,\n\tFN_QCPV_QDE___3 = 332,\n\tFN_DU_EXODDF_DU_ODDF_DISP_CDE___4 = 333,\n\tFN_VI4_DATA2_B___3 = 334,\n\tFN_MSIOF3_SYNC_E___3 = 335,\n\tFN_PWM3_B___5 = 336,\n\tFN_IP2_3_0___4 = 337,\n\tFN_A1___4 = 338,\n\tFN_LCDOUT17___3 = 339,\n\tFN_MSIOF3_TXD_B___3 = 340,\n\tFN_VI4_DATA9___3 = 341,\n\tFN_DU_DB1___4 = 342,\n\tFN_PWM4_A___4 = 343,\n\tFN_IP3_3_0___4 = 344,\n\tFN_A9___4 = 345,\n\tFN_MSIOF2_SCK_A___3 = 346,\n\tFN_CTS4_N_B___3 = 347,\n\tFN_VI5_VSYNC_N___3 = 348,\n\tFN_IP0_7_4___4 = 349,\n\tFN_AVB_MAGIC___4 = 350,\n\tFN_MSIOF2_SS1_C___3 = 351,\n\tFN_SCK4_A___3 = 352,\n\tFN_IP1_7_4___4 = 353,\n\tFN_IRQ3___4 = 354,\n\tFN_QSTVB_QVE___3 = 355,\n\tFN_DU_DOTCLKOUT1___3 = 356,\n\tFN_VI4_DATA3_B___3 = 357,\n\tFN_MSIOF3_SCK_E___3 = 358,\n\tFN_PWM4_B___4 = 359,\n\tFN_IP2_7_4___4 = 360,\n\tFN_A2___4 = 361,\n\tFN_LCDOUT18___3 = 362,\n\tFN_MSIOF3_SCK_B___3 = 363,\n\tFN_VI4_DATA10___3 = 364,\n\tFN_DU_DB2___4 = 365,\n\tFN_PWM5_A___3 = 366,\n\tFN_IP3_7_4___4 = 367,\n\tFN_A10___4 = 368,\n\tFN_MSIOF2_RXD_A___3 = 369,\n\tFN_RTS4_N_B___3 = 370,\n\tFN_VI5_HSYNC_N___3 = 371,\n\tFN_IP0_11_8___4 = 372,\n\tFN_AVB_PHY_INT___4 = 373,\n\tFN_MSIOF2_SYNC_C___3 = 374,\n\tFN_RX4_A___3 = 375,\n\tFN_IP1_11_8___4 = 376,\n\tFN_IRQ4___4 = 377,\n\tFN_QSTH_QHS___3 = 378,\n\tFN_DU_EXHSYNC_DU_HSYNC___4 = 379,\n\tFN_VI4_DATA4_B___3 = 380,\n\tFN_MSIOF3_RXD_E___3 = 381,\n\tFN_PWM5_B___3 = 382,\n\tFN_IP2_11_8___4 = 383,\n\tFN_A3___4 = 384,\n\tFN_LCDOUT19___3 = 385,\n\tFN_MSIOF3_RXD_B___3 = 386,\n\tFN_VI4_DATA11___3 = 387,\n\tFN_DU_DB3___4 = 388,\n\tFN_PWM6_A___3 = 389,\n\tFN_IP3_11_8___4 = 390,\n\tFN_A11___4 = 391,\n\tFN_TX3_B___4 = 392,\n\tFN_MSIOF2_TXD_A___3 = 393,\n\tFN_HTX4_B___3 = 394,\n\tFN_HSCK4___3 = 395,\n\tFN_VI5_FIELD___3 = 396,\n\tFN_SCL6_A___3 = 397,\n\tFN_AVB_AVTP_CAPTURE_B___3 = 398,\n\tFN_PWM2_B___4 = 399,\n\tFN_IP0_15_12___4 = 400,\n\tFN_AVB_LINK___4 = 401,\n\tFN_MSIOF2_SCK_C___3 = 402,\n\tFN_TX4_A___3 = 403,\n\tFN_IP1_15_12___4 = 404,\n\tFN_IRQ5___5 = 405,\n\tFN_QSTB_QHE___3 = 406,\n\tFN_DU_EXVSYNC_DU_VSYNC___4 = 407,\n\tFN_VI4_DATA5_B___3 = 408,\n\tFN_FSCLKST2_N_B___2 = 409,\n\tFN_MSIOF3_TXD_E___3 = 410,\n\tFN_PWM6_B___3 = 411,\n\tFN_IP2_15_12___4 = 412,\n\tFN_A4___4 = 413,\n\tFN_LCDOUT20___3 = 414,\n\tFN_MSIOF3_SS1_B___3 = 415,\n\tFN_VI4_DATA12___3 = 416,\n\tFN_VI5_DATA12___3 = 417,\n\tFN_DU_DB4___4 = 418,\n\tFN_IP3_15_12___4 = 419,\n\tFN_A12___4 = 420,\n\tFN_LCDOUT12___3 = 421,\n\tFN_MSIOF3_SCK_C___3 = 422,\n\tFN_HRX4_A___3 = 423,\n\tFN_VI5_DATA8___3 = 424,\n\tFN_DU_DG4___4 = 425,\n\tFN_IP0_19_16___4 = 426,\n\tFN_AVB_AVTP_MATCH_A___3 = 427,\n\tFN_MSIOF2_RXD_C___3 = 428,\n\tFN_CTS4_N_A___3 = 429,\n\tFN_FSCLKST2_N_A___2 = 430,\n\tFN_IP1_19_16___4 = 431,\n\tFN_PWM0___4 = 432,\n\tFN_AVB_AVTP_PPS___4 = 433,\n\tFN_VI4_DATA6_B___3 = 434,\n\tFN_IECLK_B___3 = 435,\n\tFN_IP2_19_16___4 = 436,\n\tFN_A5___4 = 437,\n\tFN_LCDOUT21___3 = 438,\n\tFN_MSIOF3_SS2_B___3 = 439,\n\tFN_SCK4_B___3 = 440,\n\tFN_VI4_DATA13___3 = 441,\n\tFN_VI5_DATA13___3 = 442,\n\tFN_DU_DB5___4 = 443,\n\tFN_IP3_19_16___4 = 444,\n\tFN_A13___4 = 445,\n\tFN_LCDOUT13___3 = 446,\n\tFN_MSIOF3_SYNC_C___3 = 447,\n\tFN_HTX4_A___3 = 448,\n\tFN_VI5_DATA9___3 = 449,\n\tFN_DU_DG5___4 = 450,\n\tFN_IP0_23_20___4 = 451,\n\tFN_AVB_AVTP_CAPTURE_A___3 = 452,\n\tFN_MSIOF2_TXD_C___3 = 453,\n\tFN_RTS4_N_A___3 = 454,\n\tFN_IP1_23_20___4 = 455,\n\tFN_PWM1_A___5 = 456,\n\tFN_HRX3_D___3 = 457,\n\tFN_VI4_DATA7_B___3 = 458,\n\tFN_IERX_B___3 = 459,\n\tFN_IP2_23_20___4 = 460,\n\tFN_A6___4 = 461,\n\tFN_LCDOUT22___3 = 462,\n\tFN_MSIOF2_SS1_A___3 = 463,\n\tFN_RX4_B___3 = 464,\n\tFN_VI4_DATA14___3 = 465,\n\tFN_VI5_DATA14___3 = 466,\n\tFN_DU_DB6___4 = 467,\n\tFN_IP3_23_20___4 = 468,\n\tFN_A14___4 = 469,\n\tFN_LCDOUT14___3 = 470,\n\tFN_MSIOF3_RXD_C___3 = 471,\n\tFN_HCTS4_N___3 = 472,\n\tFN_VI5_DATA10___3 = 473,\n\tFN_DU_DG6___4 = 474,\n\tFN_IP0_27_24___4 = 475,\n\tFN_IRQ0___4 = 476,\n\tFN_QPOLB___3 = 477,\n\tFN_DU_CDE___4 = 478,\n\tFN_VI4_DATA0_B___3 = 479,\n\tFN_CAN0_TX_B___3 = 480,\n\tFN_CANFD0_TX_B___4 = 481,\n\tFN_MSIOF3_SS2_E___3 = 482,\n\tFN_IP1_27_24___4 = 483,\n\tFN_PWM2_A___4 = 484,\n\tFN_HTX3_D___3 = 485,\n\tFN_IETX_B___3 = 486,\n\tFN_IP2_27_24___4 = 487,\n\tFN_A7___4 = 488,\n\tFN_LCDOUT23___3 = 489,\n\tFN_MSIOF2_SS2_A___3 = 490,\n\tFN_TX4_B___3 = 491,\n\tFN_VI4_DATA15___3 = 492,\n\tFN_VI5_DATA15___3 = 493,\n\tFN_DU_DB7___4 = 494,\n\tFN_IP3_27_24___4 = 495,\n\tFN_A15___4 = 496,\n\tFN_LCDOUT15___3 = 497,\n\tFN_MSIOF3_TXD_C___3 = 498,\n\tFN_HRTS4_N___3 = 499,\n\tFN_VI5_DATA11___3 = 500,\n\tFN_DU_DG7___4 = 501,\n\tFN_IP0_31_28___4 = 502,\n\tFN_IRQ1___4 = 503,\n\tFN_QPOLA___3 = 504,\n\tFN_DU_DISP___4 = 505,\n\tFN_VI4_DATA1_B___3 = 506,\n\tFN_CAN0_RX_B___3 = 507,\n\tFN_CANFD0_RX_B___4 = 508,\n\tFN_MSIOF3_SS1_E___3 = 509,\n\tFN_IP1_31_28___4 = 510,\n\tFN_A0___4 = 511,\n\tFN_LCDOUT16___3 = 512,\n\tFN_MSIOF3_SYNC_B___3 = 513,\n\tFN_VI4_DATA8___3 = 514,\n\tFN_DU_DB0___4 = 515,\n\tFN_PWM3_A___5 = 516,\n\tFN_IP2_31_28___4 = 517,\n\tFN_A8___4 = 518,\n\tFN_RX3_B___4 = 519,\n\tFN_MSIOF2_SYNC_A___3 = 520,\n\tFN_HRX4_B___3 = 521,\n\tFN_SDA6_A___3 = 522,\n\tFN_AVB_AVTP_MATCH_B___3 = 523,\n\tFN_PWM1_B___5 = 524,\n\tFN_IP3_31_28___4 = 525,\n\tFN_A16___4 = 526,\n\tFN_LCDOUT8___3 = 527,\n\tFN_VI4_FIELD___3 = 528,\n\tFN_DU_DG0___4 = 529,\n\tFN_IP4_3_0___4 = 530,\n\tFN_A17___4 = 531,\n\tFN_LCDOUT9___3 = 532,\n\tFN_VI4_VSYNC_N___3 = 533,\n\tFN_DU_DG1___4 = 534,\n\tFN_IP5_3_0___4 = 535,\n\tFN_WE0_N___4 = 536,\n\tFN_MSIOF3_TXD_D___3 = 537,\n\tFN_CTS3_N___4 = 538,\n\tFN_HCTS3_N___4 = 539,\n\tFN_SCL6_B___3 = 540,\n\tFN_CAN_CLK___4 = 541,\n\tFN_IECLK_A___3 = 542,\n\tFN_IP6_3_0___4 = 543,\n\tFN_D5___4 = 544,\n\tFN_MSIOF2_SYNC_B___3 = 545,\n\tFN_VI4_DATA21___3 = 546,\n\tFN_VI5_DATA5___3 = 547,\n\tFN_IP7_3_0___4 = 548,\n\tFN_D13___4 = 549,\n\tFN_LCDOUT5___3 = 550,\n\tFN_MSIOF2_SS2_D___3 = 551,\n\tFN_TX4_C___3 = 552,\n\tFN_VI4_DATA5_A___3 = 553,\n\tFN_DU_DR5___4 = 554,\n\tFN_IP4_7_4___4 = 555,\n\tFN_A18___4 = 556,\n\tFN_LCDOUT10___3 = 557,\n\tFN_VI4_HSYNC_N___3 = 558,\n\tFN_DU_DG2___4 = 559,\n\tFN_IP5_7_4___4 = 560,\n\tFN_WE1_N___4 = 561,\n\tFN_MSIOF3_SS1_D___3 = 562,\n\tFN_RTS3_N___4 = 563,\n\tFN_HRTS3_N___4 = 564,\n\tFN_SDA6_B___3 = 565,\n\tFN_CAN1_RX___3 = 566,\n\tFN_CANFD1_RX___5 = 567,\n\tFN_IERX_A___3 = 568,\n\tFN_IP6_7_4___4 = 569,\n\tFN_D6___4 = 570,\n\tFN_MSIOF2_RXD_B___3 = 571,\n\tFN_VI4_DATA22___3 = 572,\n\tFN_VI5_DATA6___3 = 573,\n\tFN_IP7_7_4___4 = 574,\n\tFN_D14___4 = 575,\n\tFN_LCDOUT6___3 = 576,\n\tFN_MSIOF3_SS1_A___3 = 577,\n\tFN_HRX3_C___3 = 578,\n\tFN_VI4_DATA6_A___3 = 579,\n\tFN_DU_DR6___4 = 580,\n\tFN_SCL6_C___3 = 581,\n\tFN_IP4_11_8___4 = 582,\n\tFN_A19___4 = 583,\n\tFN_LCDOUT11___3 = 584,\n\tFN_VI4_CLKENB___3 = 585,\n\tFN_DU_DG3___4 = 586,\n\tFN_IP5_11_8___4 = 587,\n\tFN_EX_WAIT0_A___3 = 588,\n\tFN_QCLK___3 = 589,\n\tFN_VI4_CLK___3 = 590,\n\tFN_DU_DOTCLKOUT0___3 = 591,\n\tFN_IP6_11_8___4 = 592,\n\tFN_D7___4 = 593,\n\tFN_MSIOF2_TXD_B___3 = 594,\n\tFN_VI4_DATA23___3 = 595,\n\tFN_VI5_DATA7___3 = 596,\n\tFN_IP7_11_8___4 = 597,\n\tFN_D15___4 = 598,\n\tFN_LCDOUT7___3 = 599,\n\tFN_MSIOF3_SS2_A___3 = 600,\n\tFN_HTX3_C___3 = 601,\n\tFN_VI4_DATA7_A___3 = 602,\n\tFN_DU_DR7___4 = 603,\n\tFN_SDA6_C___3 = 604,\n\tFN_IP4_15_12___4 = 605,\n\tFN_CS0_N___4 = 606,\n\tFN_VI5_CLKENB___3 = 607,\n\tFN_IP5_15_12___4 = 608,\n\tFN_D0___4 = 609,\n\tFN_MSIOF2_SS1_B___3 = 610,\n\tFN_MSIOF3_SCK_A___3 = 611,\n\tFN_VI4_DATA16___3 = 612,\n\tFN_VI5_DATA0___3 = 613,\n\tFN_IP6_15_12___4 = 614,\n\tFN_D8___4 = 615,\n\tFN_LCDOUT0___3 = 616,\n\tFN_MSIOF2_SCK_D___3 = 617,\n\tFN_SCK4_C___3 = 618,\n\tFN_VI4_DATA0_A___3 = 619,\n\tFN_DU_DR0___4 = 620,\n\tFN_IP4_19_16___4 = 621,\n\tFN_CS1_N___4 = 622,\n\tFN_VI5_CLK___3 = 623,\n\tFN_EX_WAIT0_B___3 = 624,\n\tFN_IP5_19_16___4 = 625,\n\tFN_D1___4 = 626,\n\tFN_MSIOF2_SS2_B___3 = 627,\n\tFN_MSIOF3_SYNC_A___3 = 628,\n\tFN_VI4_DATA17___3 = 629,\n\tFN_VI5_DATA1___3 = 630,\n\tFN_IP6_19_16___4 = 631,\n\tFN_D9___4 = 632,\n\tFN_LCDOUT1___3 = 633,\n\tFN_MSIOF2_SYNC_D___3 = 634,\n\tFN_VI4_DATA1_A___3 = 635,\n\tFN_DU_DR1___4 = 636,\n\tFN_IP7_19_16___4 = 637,\n\tFN_SD0_CLK___3 = 638,\n\tFN_MSIOF1_SCK_E___3 = 639,\n\tFN_STP_OPWM_0_B___3 = 640,\n\tFN_IP4_23_20___4 = 641,\n\tFN_BS_N___4 = 642,\n\tFN_QSTVA_QVS___3 = 643,\n\tFN_MSIOF3_SCK_D___3 = 644,\n\tFN_SCK3___4 = 645,\n\tFN_HSCK3___4 = 646,\n\tFN_CAN1_TX___3 = 647,\n\tFN_CANFD1_TX___5 = 648,\n\tFN_IETX_A___3 = 649,\n\tFN_IP5_23_20___4 = 650,\n\tFN_D2___4 = 651,\n\tFN_MSIOF3_RXD_A___3 = 652,\n\tFN_VI4_DATA18___3 = 653,\n\tFN_VI5_DATA2___3 = 654,\n\tFN_IP6_23_20___4 = 655,\n\tFN_D10___4 = 656,\n\tFN_LCDOUT2___3 = 657,\n\tFN_MSIOF2_RXD_D___3 = 658,\n\tFN_HRX3_B___4 = 659,\n\tFN_VI4_DATA2_A___3 = 660,\n\tFN_CTS4_N_C___3 = 661,\n\tFN_DU_DR2___4 = 662,\n\tFN_IP7_23_20___4 = 663,\n\tFN_SD0_CMD___3 = 664,\n\tFN_MSIOF1_SYNC_E___3 = 665,\n\tFN_STP_IVCXO27_0_B___3 = 666,\n\tFN_IP4_27_24___4 = 667,\n\tFN_RD_N___4 = 668,\n\tFN_MSIOF3_SYNC_D___3 = 669,\n\tFN_RX3_A___4 = 670,\n\tFN_HRX3_A___4 = 671,\n\tFN_CAN0_TX_A___3 = 672,\n\tFN_CANFD0_TX_A___4 = 673,\n\tFN_IP5_27_24___4 = 674,\n\tFN_D3___4 = 675,\n\tFN_MSIOF3_TXD_A___3 = 676,\n\tFN_VI4_DATA19___3 = 677,\n\tFN_VI5_DATA3___3 = 678,\n\tFN_IP6_27_24___4 = 679,\n\tFN_D11___4 = 680,\n\tFN_LCDOUT3___3 = 681,\n\tFN_MSIOF2_TXD_D___3 = 682,\n\tFN_HTX3_B___4 = 683,\n\tFN_VI4_DATA3_A___3 = 684,\n\tFN_RTS4_N_C___3 = 685,\n\tFN_DU_DR3___4 = 686,\n\tFN_IP7_27_24___4 = 687,\n\tFN_SD0_DAT0___3 = 688,\n\tFN_MSIOF1_RXD_E___3 = 689,\n\tFN_TS_SCK0_B___3 = 690,\n\tFN_STP_ISCLK_0_B___3 = 691,\n\tFN_IP4_31_28___4 = 692,\n\tFN_RD_WR_N___4 = 693,\n\tFN_MSIOF3_RXD_D___3 = 694,\n\tFN_TX3_A___4 = 695,\n\tFN_HTX3_A___4 = 696,\n\tFN_CAN0_RX_A___3 = 697,\n\tFN_CANFD0_RX_A___4 = 698,\n\tFN_IP5_31_28___4 = 699,\n\tFN_D4___4 = 700,\n\tFN_MSIOF2_SCK_B___3 = 701,\n\tFN_VI4_DATA20___3 = 702,\n\tFN_VI5_DATA4___3 = 703,\n\tFN_IP6_31_28___4 = 704,\n\tFN_D12___4 = 705,\n\tFN_LCDOUT4___3 = 706,\n\tFN_MSIOF2_SS1_D___3 = 707,\n\tFN_RX4_C___3 = 708,\n\tFN_VI4_DATA4_A___3 = 709,\n\tFN_DU_DR4___4 = 710,\n\tFN_IP7_31_28___4 = 711,\n\tFN_SD0_DAT1___3 = 712,\n\tFN_MSIOF1_TXD_E___3 = 713,\n\tFN_TS_SPSYNC0_B___3 = 714,\n\tFN_STP_ISSYNC_0_B___3 = 715,\n\tFN_IP8_3_0___4 = 716,\n\tFN_SD0_DAT2___3 = 717,\n\tFN_MSIOF1_SS1_E___3 = 718,\n\tFN_TS_SDAT0_B___3 = 719,\n\tFN_STP_ISD_0_B___3 = 720,\n\tFN_IP9_3_0___4 = 721,\n\tFN_SD2_CLK___3 = 722,\n\tFN_NFDATA8___3 = 723,\n\tFN_IP10_3_0___4 = 724,\n\tFN_SD3_CMD___3 = 725,\n\tFN_NFRE_N___3 = 726,\n\tFN_IP11_3_0___3 = 727,\n\tFN_SD3_DAT7___3 = 728,\n\tFN_SD3_WP___3 = 729,\n\tFN_NFDATA7___3 = 730,\n\tFN_IP8_7_4___4 = 731,\n\tFN_SD0_DAT3___3 = 732,\n\tFN_MSIOF1_SS2_E___3 = 733,\n\tFN_TS_SDEN0_B___3 = 734,\n\tFN_STP_ISEN_0_B___3 = 735,\n\tFN_IP9_7_4___4 = 736,\n\tFN_SD2_CMD___3 = 737,\n\tFN_NFDATA9___3 = 738,\n\tFN_IP10_7_4___4 = 739,\n\tFN_SD3_DAT0___3 = 740,\n\tFN_NFDATA0___3 = 741,\n\tFN_IP11_7_4___3 = 742,\n\tFN_SD3_DS___3 = 743,\n\tFN_NFCLE___3 = 744,\n\tFN_IP8_11_8___4 = 745,\n\tFN_SD1_CLK___3 = 746,\n\tFN_MSIOF1_SCK_G___3 = 747,\n\tFN_SIM0_CLK_A___3 = 748,\n\tFN_IP9_11_8___4 = 749,\n\tFN_SD2_DAT0___3 = 750,\n\tFN_NFDATA10___3 = 751,\n\tFN_IP10_11_8___4 = 752,\n\tFN_SD3_DAT1___3 = 753,\n\tFN_NFDATA1___3 = 754,\n\tFN_IP11_11_8___3 = 755,\n\tFN_SD0_CD___3 = 756,\n\tFN_NFDATA14_A___3 = 757,\n\tFN_SCL2_B___3 = 758,\n\tFN_SIM0_RST_A___3 = 759,\n\tFN_IP8_15_12___4 = 760,\n\tFN_SD1_CMD___3 = 761,\n\tFN_MSIOF1_SYNC_G___3 = 762,\n\tFN_NFCE_N_B___3 = 763,\n\tFN_SIM0_D_A___3 = 764,\n\tFN_STP_IVCXO27_1_B___3 = 765,\n\tFN_IP9_15_12___4 = 766,\n\tFN_SD2_DAT1___3 = 767,\n\tFN_NFDATA11___3 = 768,\n\tFN_IP10_15_12___4 = 769,\n\tFN_SD3_DAT2___3 = 770,\n\tFN_NFDATA2___3 = 771,\n\tFN_IP11_15_12___3 = 772,\n\tFN_SD0_WP___3 = 773,\n\tFN_NFDATA15_A___3 = 774,\n\tFN_SDA2_B___3 = 775,\n\tFN_IP8_19_16___4 = 776,\n\tFN_SD1_DAT0___3 = 777,\n\tFN_SD2_DAT4___3 = 778,\n\tFN_MSIOF1_RXD_G___3 = 779,\n\tFN_NFWP_N_B___3 = 780,\n\tFN_TS_SCK1_B___3 = 781,\n\tFN_STP_ISCLK_1_B___3 = 782,\n\tFN_IP9_19_16___4 = 783,\n\tFN_SD2_DAT2___3 = 784,\n\tFN_NFDATA12___3 = 785,\n\tFN_IP10_19_16___4 = 786,\n\tFN_SD3_DAT3___3 = 787,\n\tFN_NFDATA3___3 = 788,\n\tFN_IP11_19_16___3 = 789,\n\tFN_SD1_CD___3 = 790,\n\tFN_NFRB_N_A___3 = 791,\n\tFN_SIM0_CLK_B___3 = 792,\n\tFN_IP8_23_20___4 = 793,\n\tFN_SD1_DAT1___3 = 794,\n\tFN_SD2_DAT5___3 = 795,\n\tFN_MSIOF1_TXD_G___3 = 796,\n\tFN_NFDATA14_B___3 = 797,\n\tFN_TS_SPSYNC1_B___3 = 798,\n\tFN_STP_ISSYNC_1_B___3 = 799,\n\tFN_IP9_23_20___4 = 800,\n\tFN_SD2_DAT3___3 = 801,\n\tFN_NFDATA13___3 = 802,\n\tFN_IP10_23_20___3 = 803,\n\tFN_SD3_DAT4___3 = 804,\n\tFN_SD2_CD_A___3 = 805,\n\tFN_NFDATA4___3 = 806,\n\tFN_IP11_23_20___3 = 807,\n\tFN_SD1_WP___3 = 808,\n\tFN_NFCE_N_A___3 = 809,\n\tFN_SIM0_D_B___3 = 810,\n\tFN_IP8_27_24___4 = 811,\n\tFN_SD1_DAT2___3 = 812,\n\tFN_SD2_DAT6___3 = 813,\n\tFN_MSIOF1_SS1_G___3 = 814,\n\tFN_NFDATA15_B___3 = 815,\n\tFN_TS_SDAT1_B___3 = 816,\n\tFN_STP_ISD_1_B___3 = 817,\n\tFN_IP9_27_24___4 = 818,\n\tFN_SD2_DS___3 = 819,\n\tFN_NFALE___3 = 820,\n\tFN_SATA_DEVSLP_B___2 = 821,\n\tFN_IP10_27_24___3 = 822,\n\tFN_SD3_DAT5___3 = 823,\n\tFN_SD2_WP_A___3 = 824,\n\tFN_NFDATA5___3 = 825,\n\tFN_IP11_27_24___3 = 826,\n\tFN_SCK0___5 = 827,\n\tFN_HSCK1_B___4 = 828,\n\tFN_MSIOF1_SS2_B___3 = 829,\n\tFN_AUDIO_CLKC_B___3 = 830,\n\tFN_SDA2_A___3 = 831,\n\tFN_SIM0_RST_B___3 = 832,\n\tFN_STP_OPWM_0_C___3 = 833,\n\tFN_RIF0_CLK_B___3 = 834,\n\tFN_ADICHS2___3 = 835,\n\tFN_SCK5_B___3 = 836,\n\tFN_IP8_31_28___4 = 837,\n\tFN_SD1_DAT3___3 = 838,\n\tFN_SD2_DAT7___3 = 839,\n\tFN_MSIOF1_SS2_G___3 = 840,\n\tFN_NFRB_N_B___3 = 841,\n\tFN_TS_SDEN1_B___3 = 842,\n\tFN_STP_ISEN_1_B___3 = 843,\n\tFN_IP9_31_28___4 = 844,\n\tFN_SD3_CLK___3 = 845,\n\tFN_NFWE_N___3 = 846,\n\tFN_IP10_31_28___3 = 847,\n\tFN_SD3_DAT6___3 = 848,\n\tFN_SD3_CD___3 = 849,\n\tFN_NFDATA6___3 = 850,\n\tFN_IP11_31_28___3 = 851,\n\tFN_RX0___5 = 852,\n\tFN_HRX1_B___4 = 853,\n\tFN_TS_SCK0_C___3 = 854,\n\tFN_STP_ISCLK_0_C___3 = 855,\n\tFN_RIF0_D0_B___3 = 856,\n\tFN_IP12_3_0___3 = 857,\n\tFN_TX0___5 = 858,\n\tFN_HTX1_B___4 = 859,\n\tFN_TS_SPSYNC0_C___3 = 860,\n\tFN_STP_ISSYNC_0_C___3 = 861,\n\tFN_RIF0_D1_B___3 = 862,\n\tFN_IP13_3_0___3 = 863,\n\tFN_TX2_A___3 = 864,\n\tFN_SD2_CD_B___3 = 865,\n\tFN_SCL1_A___3 = 866,\n\tFN_FMCLK_A___3 = 867,\n\tFN_RIF1_D1_C___3 = 868,\n\tFN_FSO_CFE_0_N___4 = 869,\n\tFN_IP14_3_0___3 = 870,\n\tFN_MSIOF0_SS1___5 = 871,\n\tFN_RX5_A___3 = 872,\n\tFN_NFWP_N_A___3 = 873,\n\tFN_AUDIO_CLKA_C___3 = 874,\n\tFN_SSI_SCK2_A___3 = 875,\n\tFN_STP_IVCXO27_0_C___3 = 876,\n\tFN_AUDIO_CLKOUT3_A___3 = 877,\n\tFN_TCLK1_B___5 = 878,\n\tFN_IP15_3_0___3 = 879,\n\tFN_SSI_SDATA1_A___3 = 880,\n\tFN_IP12_7_4___3 = 881,\n\tFN_CTS0_N___5 = 882,\n\tFN_HCTS1_N_B___4 = 883,\n\tFN_MSIOF1_SYNC_B___3 = 884,\n\tFN_TS_SPSYNC1_C___3 = 885,\n\tFN_STP_ISSYNC_1_C___3 = 886,\n\tFN_RIF1_SYNC_B___3 = 887,\n\tFN_AUDIO_CLKOUT_C___3 = 888,\n\tFN_ADICS_SAMP___3 = 889,\n\tFN_IP13_7_4___3 = 890,\n\tFN_RX2_A___3 = 891,\n\tFN_SD2_WP_B___3 = 892,\n\tFN_SDA1_A___3 = 893,\n\tFN_FMIN_A___3 = 894,\n\tFN_RIF1_SYNC_C___3 = 895,\n\tFN_FSO_CFE_1_N___4 = 896,\n\tFN_IP14_7_4___3 = 897,\n\tFN_MSIOF0_SS2___5 = 898,\n\tFN_TX5_A___3 = 899,\n\tFN_MSIOF1_SS2_D___3 = 900,\n\tFN_AUDIO_CLKC_A___3 = 901,\n\tFN_SSI_WS2_A___3 = 902,\n\tFN_STP_OPWM_0_D___3 = 903,\n\tFN_AUDIO_CLKOUT_D___3 = 904,\n\tFN_SPEEDIN_B___4 = 905,\n\tFN_IP15_7_4___3 = 906,\n\tFN_SSI_SDATA2_A___3 = 907,\n\tFN_SSI_SCK1_B___3 = 908,\n\tFN_IP12_11_8___3 = 909,\n\tFN_RTS0_N___5 = 910,\n\tFN_HRTS1_N_B___4 = 911,\n\tFN_MSIOF1_SS1_B___3 = 912,\n\tFN_AUDIO_CLKA_B___3 = 913,\n\tFN_SCL2_A___3 = 914,\n\tFN_STP_IVCXO27_1_C___3 = 915,\n\tFN_RIF0_SYNC_B___3 = 916,\n\tFN_ADICHS1___3 = 917,\n\tFN_IP13_11_8___3 = 918,\n\tFN_HSCK0___4 = 919,\n\tFN_MSIOF1_SCK_D___3 = 920,\n\tFN_AUDIO_CLKB_A___3 = 921,\n\tFN_SSI_SDATA1_B___3 = 922,\n\tFN_TS_SCK0_D___3 = 923,\n\tFN_STP_ISCLK_0_D___3 = 924,\n\tFN_RIF0_CLK_C___3 = 925,\n\tFN_RX5_B___3 = 926,\n\tFN_IP14_11_8___3 = 927,\n\tFN_MLB_CLK___3 = 928,\n\tFN_MSIOF1_SCK_F___3 = 929,\n\tFN_SCL1_B___3 = 930,\n\tFN_IP15_11_8___3 = 931,\n\tFN_SSI_SCK349___3 = 932,\n\tFN_MSIOF1_SS1_A___3 = 933,\n\tFN_STP_OPWM_0_A___3 = 934,\n\tFN_IP12_15_12___3 = 935,\n\tFN_RX1_A___5 = 936,\n\tFN_HRX1_A___4 = 937,\n\tFN_TS_SDAT0_C___3 = 938,\n\tFN_STP_ISD_0_C___3 = 939,\n\tFN_RIF1_CLK_C___3 = 940,\n\tFN_IP13_15_12___3 = 941,\n\tFN_HRX0___4 = 942,\n\tFN_MSIOF1_RXD_D___3 = 943,\n\tFN_SSI_SDATA2_B___3 = 944,\n\tFN_TS_SDEN0_D___3 = 945,\n\tFN_STP_ISEN_0_D___3 = 946,\n\tFN_RIF0_D0_C___3 = 947,\n\tFN_IP14_15_12___3 = 948,\n\tFN_MLB_SIG___3 = 949,\n\tFN_RX1_B___5 = 950,\n\tFN_MSIOF1_SYNC_F___3 = 951,\n\tFN_SDA1_B___3 = 952,\n\tFN_IP15_15_12___3 = 953,\n\tFN_SSI_WS349___3 = 954,\n\tFN_HCTS2_N_A___3 = 955,\n\tFN_MSIOF1_SS2_A___3 = 956,\n\tFN_STP_IVCXO27_0_A___3 = 957,\n\tFN_IP12_19_16___3 = 958,\n\tFN_TX1_A___5 = 959,\n\tFN_HTX1_A___4 = 960,\n\tFN_TS_SDEN0_C___3 = 961,\n\tFN_STP_ISEN_0_C___3 = 962,\n\tFN_RIF1_D0_C___3 = 963,\n\tFN_IP13_19_16___3 = 964,\n\tFN_HTX0___4 = 965,\n\tFN_MSIOF1_TXD_D___3 = 966,\n\tFN_SSI_SDATA9_B___3 = 967,\n\tFN_TS_SDAT0_D___3 = 968,\n\tFN_STP_ISD_0_D___3 = 969,\n\tFN_RIF0_D1_C___3 = 970,\n\tFN_IP14_19_16___3 = 971,\n\tFN_MLB_DAT___3 = 972,\n\tFN_TX1_B___5 = 973,\n\tFN_MSIOF1_RXD_F___3 = 974,\n\tFN_IP15_19_16___3 = 975,\n\tFN_SSI_SDATA3___3 = 976,\n\tFN_HRTS2_N_A___3 = 977,\n\tFN_MSIOF1_TXD_A___3 = 978,\n\tFN_TS_SCK0_A___3 = 979,\n\tFN_STP_ISCLK_0_A___3 = 980,\n\tFN_RIF0_D1_A___3 = 981,\n\tFN_RIF2_D0_A___3 = 982,\n\tFN_IP12_23_20___3 = 983,\n\tFN_CTS1_N___4 = 984,\n\tFN_HCTS1_N_A___4 = 985,\n\tFN_MSIOF1_RXD_B___3 = 986,\n\tFN_TS_SDEN1_C___3 = 987,\n\tFN_STP_ISEN_1_C___3 = 988,\n\tFN_RIF1_D0_B___3 = 989,\n\tFN_ADIDATA___3 = 990,\n\tFN_IP13_23_20___3 = 991,\n\tFN_HCTS0_N___4 = 992,\n\tFN_RX2_B___3 = 993,\n\tFN_MSIOF1_SYNC_D___3 = 994,\n\tFN_SSI_SCK9_A___3 = 995,\n\tFN_TS_SPSYNC0_D___3 = 996,\n\tFN_STP_ISSYNC_0_D___3 = 997,\n\tFN_RIF0_SYNC_C___3 = 998,\n\tFN_AUDIO_CLKOUT1_A___3 = 999,\n\tFN_IP14_23_20___3 = 1000,\n\tFN_SSI_SCK01239___3 = 1001,\n\tFN_MSIOF1_TXD_F___3 = 1002,\n\tFN_IP15_23_20___3 = 1003,\n\tFN_SSI_SCK4___3 = 1004,\n\tFN_HRX2_A___3 = 1005,\n\tFN_MSIOF1_SCK_A___3 = 1006,\n\tFN_TS_SDAT0_A___3 = 1007,\n\tFN_STP_ISD_0_A___3 = 1008,\n\tFN_RIF0_CLK_A___3 = 1009,\n\tFN_RIF2_CLK_A___3 = 1010,\n\tFN_IP12_27_24___3 = 1011,\n\tFN_RTS1_N___4 = 1012,\n\tFN_HRTS1_N_A___4 = 1013,\n\tFN_MSIOF1_TXD_B___3 = 1014,\n\tFN_TS_SDAT1_C___3 = 1015,\n\tFN_STP_ISD_1_C___3 = 1016,\n\tFN_RIF1_D1_B___3 = 1017,\n\tFN_ADICHS0___3 = 1018,\n\tFN_IP13_27_24___3 = 1019,\n\tFN_HRTS0_N___4 = 1020,\n\tFN_TX2_B___3 = 1021,\n\tFN_MSIOF1_SS1_D___3 = 1022,\n\tFN_SSI_WS9_A___3 = 1023,\n\tFN_STP_IVCXO27_0_D___3 = 1024,\n\tFN_BPFCLK_A___3 = 1025,\n\tFN_AUDIO_CLKOUT2_A___3 = 1026,\n\tFN_IP14_27_24___3 = 1027,\n\tFN_SSI_WS01239___3 = 1028,\n\tFN_MSIOF1_SS1_F___3 = 1029,\n\tFN_IP15_27_24___3 = 1030,\n\tFN_SSI_WS4___3 = 1031,\n\tFN_HTX2_A___3 = 1032,\n\tFN_MSIOF1_SYNC_A___3 = 1033,\n\tFN_TS_SDEN0_A___3 = 1034,\n\tFN_STP_ISEN_0_A___3 = 1035,\n\tFN_RIF0_SYNC_A___3 = 1036,\n\tFN_RIF2_SYNC_A___3 = 1037,\n\tFN_IP12_31_28___3 = 1038,\n\tFN_SCK2___3 = 1039,\n\tFN_SCIF_CLK_B___4 = 1040,\n\tFN_MSIOF1_SCK_B___3 = 1041,\n\tFN_TS_SCK1_C___3 = 1042,\n\tFN_STP_ISCLK_1_C___3 = 1043,\n\tFN_RIF1_CLK_B___3 = 1044,\n\tFN_ADICLK___3 = 1045,\n\tFN_IP13_31_28___3 = 1046,\n\tFN_MSIOF0_SYNC___5 = 1047,\n\tFN_AUDIO_CLKOUT_A___3 = 1048,\n\tFN_TX5_B___3 = 1049,\n\tFN_BPFCLK_D___3 = 1050,\n\tFN_IP14_31_28___3 = 1051,\n\tFN_SSI_SDATA0___3 = 1052,\n\tFN_MSIOF1_SS2_F___3 = 1053,\n\tFN_IP15_31_28___3 = 1054,\n\tFN_SSI_SDATA4___3 = 1055,\n\tFN_HSCK2_A___3 = 1056,\n\tFN_MSIOF1_RXD_A___3 = 1057,\n\tFN_TS_SPSYNC0_A___3 = 1058,\n\tFN_STP_ISSYNC_0_A___3 = 1059,\n\tFN_RIF0_D0_A___3 = 1060,\n\tFN_RIF2_D1_A___3 = 1061,\n\tFN_IP16_3_0___3 = 1062,\n\tFN_SSI_SCK6___3 = 1063,\n\tFN_SIM0_RST_D___3 = 1064,\n\tFN_IP17_3_0___3 = 1065,\n\tFN_AUDIO_CLKA_A___3 = 1066,\n\tFN_IP18_3_0___3 = 1067,\n\tFN_GP6_30___2 = 1068,\n\tFN_AUDIO_CLKOUT2_B___3 = 1069,\n\tFN_SSI_SCK9_B___3 = 1070,\n\tFN_TS_SDEN0_E___3 = 1071,\n\tFN_STP_ISEN_0_E___3 = 1072,\n\tFN_RIF2_D0_B___3 = 1073,\n\tFN_TPU0TO2___4 = 1074,\n\tFN_FMCLK_C___3 = 1075,\n\tFN_FMCLK_D___3 = 1076,\n\tFN_IP16_7_4___3 = 1077,\n\tFN_SSI_WS6___3 = 1078,\n\tFN_SIM0_D_D___3 = 1079,\n\tFN_IP17_7_4___3 = 1080,\n\tFN_AUDIO_CLKB_B___3 = 1081,\n\tFN_SCIF_CLK_A___4 = 1082,\n\tFN_STP_IVCXO27_1_D___3 = 1083,\n\tFN_REMOCON_A___3 = 1084,\n\tFN_TCLK1_A___5 = 1085,\n\tFN_IP18_7_4___3 = 1086,\n\tFN_GP6_31___2 = 1087,\n\tFN_AUDIO_CLKOUT3_B___3 = 1088,\n\tFN_SSI_WS9_B___3 = 1089,\n\tFN_TS_SPSYNC0_E___3 = 1090,\n\tFN_STP_ISSYNC_0_E___3 = 1091,\n\tFN_RIF2_D1_B___3 = 1092,\n\tFN_TPU0TO3___4 = 1093,\n\tFN_FMIN_C___3 = 1094,\n\tFN_FMIN_D___3 = 1095,\n\tFN_IP16_11_8___3 = 1096,\n\tFN_SSI_SDATA6___3 = 1097,\n\tFN_SIM0_CLK_D___3 = 1098,\n\tFN_SATA_DEVSLP_A___2 = 1099,\n\tFN_IP17_11_8___3 = 1100,\n\tFN_USB0_PWEN___3 = 1101,\n\tFN_SIM0_RST_C___3 = 1102,\n\tFN_TS_SCK1_D___3 = 1103,\n\tFN_STP_ISCLK_1_D___3 = 1104,\n\tFN_BPFCLK_B___3 = 1105,\n\tFN_RIF3_CLK_B___3 = 1106,\n\tFN_HSCK2_C___3 = 1107,\n\tFN_IP16_15_12___3 = 1108,\n\tFN_SSI_SCK78___3 = 1109,\n\tFN_HRX2_B___3 = 1110,\n\tFN_MSIOF1_SCK_C___3 = 1111,\n\tFN_TS_SCK1_A___3 = 1112,\n\tFN_STP_ISCLK_1_A___3 = 1113,\n\tFN_RIF1_CLK_A___3 = 1114,\n\tFN_RIF3_CLK_A___3 = 1115,\n\tFN_IP17_15_12___3 = 1116,\n\tFN_USB0_OVC___3 = 1117,\n\tFN_SIM0_D_C___3 = 1118,\n\tFN_TS_SDAT1_D___3 = 1119,\n\tFN_STP_ISD_1_D___3 = 1120,\n\tFN_RIF3_SYNC_B___3 = 1121,\n\tFN_HRX2_C___3 = 1122,\n\tFN_IP16_19_16___3 = 1123,\n\tFN_SSI_WS78___3 = 1124,\n\tFN_HTX2_B___3 = 1125,\n\tFN_MSIOF1_SYNC_C___3 = 1126,\n\tFN_TS_SDAT1_A___3 = 1127,\n\tFN_STP_ISD_1_A___3 = 1128,\n\tFN_RIF1_SYNC_A___3 = 1129,\n\tFN_RIF3_SYNC_A___3 = 1130,\n\tFN_IP17_19_16___3 = 1131,\n\tFN_USB1_PWEN___3 = 1132,\n\tFN_SIM0_CLK_C___3 = 1133,\n\tFN_SSI_SCK1_A___3 = 1134,\n\tFN_TS_SCK0_E___3 = 1135,\n\tFN_STP_ISCLK_0_E___3 = 1136,\n\tFN_FMCLK_B___3 = 1137,\n\tFN_RIF2_CLK_B___3 = 1138,\n\tFN_SPEEDIN_A___4 = 1139,\n\tFN_HTX2_C___3 = 1140,\n\tFN_IP16_23_20___3 = 1141,\n\tFN_SSI_SDATA7___3 = 1142,\n\tFN_HCTS2_N_B___3 = 1143,\n\tFN_MSIOF1_RXD_C___3 = 1144,\n\tFN_TS_SDEN1_A___3 = 1145,\n\tFN_STP_ISEN_1_A___3 = 1146,\n\tFN_RIF1_D0_A___3 = 1147,\n\tFN_RIF3_D0_A___3 = 1148,\n\tFN_TCLK2_A___5 = 1149,\n\tFN_IP17_23_20___3 = 1150,\n\tFN_USB1_OVC___3 = 1151,\n\tFN_MSIOF1_SS2_C___3 = 1152,\n\tFN_SSI_WS1_A___3 = 1153,\n\tFN_TS_SDAT0_E___3 = 1154,\n\tFN_STP_ISD_0_E___3 = 1155,\n\tFN_FMIN_B___3 = 1156,\n\tFN_RIF2_SYNC_B___3 = 1157,\n\tFN_REMOCON_B___3 = 1158,\n\tFN_HCTS2_N_C___3 = 1159,\n\tFN_IP16_27_24___3 = 1160,\n\tFN_SSI_SDATA8___3 = 1161,\n\tFN_HRTS2_N_B___3 = 1162,\n\tFN_MSIOF1_TXD_C___3 = 1163,\n\tFN_TS_SPSYNC1_A___3 = 1164,\n\tFN_STP_ISSYNC_1_A___3 = 1165,\n\tFN_RIF1_D1_A___3 = 1166,\n\tFN_RIF3_D1_A___3 = 1167,\n\tFN_IP17_27_24___3 = 1168,\n\tFN_USB30_PWEN___3 = 1169,\n\tFN_AUDIO_CLKOUT_B___3 = 1170,\n\tFN_SSI_SCK2_B___3 = 1171,\n\tFN_TS_SDEN1_D___3 = 1172,\n\tFN_STP_ISEN_1_D___3 = 1173,\n\tFN_STP_OPWM_0_E___3 = 1174,\n\tFN_RIF3_D0_B___3 = 1175,\n\tFN_TCLK2_B___5 = 1176,\n\tFN_TPU0TO0___4 = 1177,\n\tFN_BPFCLK_C___3 = 1178,\n\tFN_HRTS2_N_C___3 = 1179,\n\tFN_IP16_31_28___3 = 1180,\n\tFN_SSI_SDATA9_A___3 = 1181,\n\tFN_HSCK2_B___3 = 1182,\n\tFN_MSIOF1_SS1_C___3 = 1183,\n\tFN_HSCK1_A___4 = 1184,\n\tFN_SSI_WS1_B___3 = 1185,\n\tFN_SCK1___4 = 1186,\n\tFN_STP_IVCXO27_1_A___3 = 1187,\n\tFN_SCK5_A___3 = 1188,\n\tFN_IP17_31_28___3 = 1189,\n\tFN_USB30_OVC___3 = 1190,\n\tFN_AUDIO_CLKOUT1_B___3 = 1191,\n\tFN_SSI_WS2_B___3 = 1192,\n\tFN_TS_SPSYNC1_D___3 = 1193,\n\tFN_STP_ISSYNC_1_D___3 = 1194,\n\tFN_STP_IVCXO27_0_E___3 = 1195,\n\tFN_RIF3_D1_B___3 = 1196,\n\tFN_FSO_TOE_N___4 = 1197,\n\tFN_TPU0TO1___4 = 1198,\n\tFN_SEL_MSIOF3_0___3 = 1199,\n\tFN_SEL_MSIOF3_1___3 = 1200,\n\tFN_SEL_MSIOF3_2___3 = 1201,\n\tFN_SEL_MSIOF3_3___3 = 1202,\n\tFN_SEL_MSIOF3_4___3 = 1203,\n\tFN_SEL_TSIF1_0___3 = 1204,\n\tFN_SEL_TSIF1_1___3 = 1205,\n\tFN_SEL_TSIF1_2___3 = 1206,\n\tFN_SEL_TSIF1_3___3 = 1207,\n\tFN_I2C_SEL_5_0___3 = 1208,\n\tFN_I2C_SEL_5_1___3 = 1209,\n\tFN_I2C_SEL_3_0___3 = 1210,\n\tFN_I2C_SEL_3_1___3 = 1211,\n\tFN_SEL_TSIF0_0___3 = 1212,\n\tFN_SEL_TSIF0_1___3 = 1213,\n\tFN_SEL_TSIF0_2___3 = 1214,\n\tFN_SEL_TSIF0_3___3 = 1215,\n\tFN_SEL_TSIF0_4___3 = 1216,\n\tFN_I2C_SEL_0_0___3 = 1217,\n\tFN_I2C_SEL_0_1___3 = 1218,\n\tFN_SEL_MSIOF2_0___3 = 1219,\n\tFN_SEL_MSIOF2_1___3 = 1220,\n\tFN_SEL_MSIOF2_2___3 = 1221,\n\tFN_SEL_MSIOF2_3___3 = 1222,\n\tFN_SEL_FM_0___3 = 1223,\n\tFN_SEL_FM_1___3 = 1224,\n\tFN_SEL_FM_2___3 = 1225,\n\tFN_SEL_FM_3___3 = 1226,\n\tFN_SEL_MSIOF1_0___3 = 1227,\n\tFN_SEL_MSIOF1_1___3 = 1228,\n\tFN_SEL_MSIOF1_2___3 = 1229,\n\tFN_SEL_MSIOF1_3___3 = 1230,\n\tFN_SEL_MSIOF1_4___3 = 1231,\n\tFN_SEL_MSIOF1_5___3 = 1232,\n\tFN_SEL_MSIOF1_6___3 = 1233,\n\tFN_SEL_TIMER_TMU_0___2 = 1234,\n\tFN_SEL_TIMER_TMU_1___2 = 1235,\n\tFN_SEL_SCIF5_0___3 = 1236,\n\tFN_SEL_SCIF5_1___3 = 1237,\n\tFN_SEL_SSP1_1_0___3 = 1238,\n\tFN_SEL_SSP1_1_1___3 = 1239,\n\tFN_SEL_SSP1_1_2___3 = 1240,\n\tFN_SEL_SSP1_1_3___3 = 1241,\n\tFN_SEL_I2C6_0___3 = 1242,\n\tFN_SEL_I2C6_1___3 = 1243,\n\tFN_SEL_I2C6_2___3 = 1244,\n\tFN_SEL_LBSC_0___3 = 1245,\n\tFN_SEL_LBSC_1___3 = 1246,\n\tFN_SEL_SSP1_0_0___3 = 1247,\n\tFN_SEL_SSP1_0_1___3 = 1248,\n\tFN_SEL_SSP1_0_2___3 = 1249,\n\tFN_SEL_SSP1_0_3___3 = 1250,\n\tFN_SEL_SSP1_0_4___3 = 1251,\n\tFN_SEL_IEBUS_0___3 = 1252,\n\tFN_SEL_IEBUS_1___3 = 1253,\n\tFN_SEL_NDF_0___2 = 1254,\n\tFN_SEL_NDF_1___2 = 1255,\n\tFN_SEL_I2C2_0___3 = 1256,\n\tFN_SEL_I2C2_1___3 = 1257,\n\tFN_SEL_SSI2_0___3 = 1258,\n\tFN_SEL_SSI2_1___3 = 1259,\n\tFN_SEL_I2C1_0___3 = 1260,\n\tFN_SEL_I2C1_1___3 = 1261,\n\tFN_SEL_SSI1_0___3 = 1262,\n\tFN_SEL_SSI1_1___3 = 1263,\n\tFN_SEL_SSI9_0___3 = 1264,\n\tFN_SEL_SSI9_1___3 = 1265,\n\tFN_SEL_HSCIF4_0___3 = 1266,\n\tFN_SEL_HSCIF4_1___3 = 1267,\n\tFN_SEL_SPEED_PULSE_0___3 = 1268,\n\tFN_SEL_SPEED_PULSE_1___3 = 1269,\n\tFN_SEL_TIMER_TMU2_0___3 = 1270,\n\tFN_SEL_TIMER_TMU2_1___3 = 1271,\n\tFN_SEL_HSCIF3_0___3 = 1272,\n\tFN_SEL_HSCIF3_1___3 = 1273,\n\tFN_SEL_HSCIF3_2___3 = 1274,\n\tFN_SEL_HSCIF3_3___3 = 1275,\n\tFN_SEL_SIMCARD_0___3 = 1276,\n\tFN_SEL_SIMCARD_1___3 = 1277,\n\tFN_SEL_SIMCARD_2___3 = 1278,\n\tFN_SEL_SIMCARD_3___3 = 1279,\n\tFN_SEL_ADGB_0___3 = 1280,\n\tFN_SEL_ADGB_1___3 = 1281,\n\tFN_SEL_ADGC_0___3 = 1282,\n\tFN_SEL_ADGC_1___3 = 1283,\n\tFN_SEL_HSCIF1_0___3 = 1284,\n\tFN_SEL_HSCIF1_1___3 = 1285,\n\tFN_SEL_SDHI2_0___3 = 1286,\n\tFN_SEL_SDHI2_1___3 = 1287,\n\tFN_SEL_SCIF4_0___3 = 1288,\n\tFN_SEL_SCIF4_1___3 = 1289,\n\tFN_SEL_SCIF4_2___3 = 1290,\n\tFN_SEL_HSCIF2_0___3 = 1291,\n\tFN_SEL_HSCIF2_1___3 = 1292,\n\tFN_SEL_HSCIF2_2___3 = 1293,\n\tFN_SEL_SCIF3_0___3 = 1294,\n\tFN_SEL_SCIF3_1___3 = 1295,\n\tFN_SEL_ETHERAVB_0___3 = 1296,\n\tFN_SEL_ETHERAVB_1___3 = 1297,\n\tFN_SEL_SCIF2_0___3 = 1298,\n\tFN_SEL_SCIF2_1___3 = 1299,\n\tFN_SEL_DRIF3_0___3 = 1300,\n\tFN_SEL_DRIF3_1___3 = 1301,\n\tFN_SEL_SCIF1_0___4 = 1302,\n\tFN_SEL_SCIF1_1___4 = 1303,\n\tFN_SEL_DRIF2_0___3 = 1304,\n\tFN_SEL_DRIF2_1___3 = 1305,\n\tFN_SEL_SCIF_0___3 = 1306,\n\tFN_SEL_SCIF_1___3 = 1307,\n\tFN_SEL_DRIF1_0___3 = 1308,\n\tFN_SEL_DRIF1_1___3 = 1309,\n\tFN_SEL_DRIF1_2___3 = 1310,\n\tFN_SEL_REMOCON_0___3 = 1311,\n\tFN_SEL_REMOCON_1___3 = 1312,\n\tFN_SEL_DRIF0_0___3 = 1313,\n\tFN_SEL_DRIF0_1___3 = 1314,\n\tFN_SEL_DRIF0_2___3 = 1315,\n\tFN_SEL_RCAN0_0___3 = 1316,\n\tFN_SEL_RCAN0_1___3 = 1317,\n\tFN_SEL_CANFD0_0___4 = 1318,\n\tFN_SEL_CANFD0_1___4 = 1319,\n\tFN_SEL_PWM6_0___3 = 1320,\n\tFN_SEL_PWM6_1___3 = 1321,\n\tFN_SEL_ADGA_0___3 = 1322,\n\tFN_SEL_ADGA_1___3 = 1323,\n\tFN_SEL_ADGA_2___3 = 1324,\n\tFN_SEL_ADGA_3___3 = 1325,\n\tFN_SEL_PWM5_0___3 = 1326,\n\tFN_SEL_PWM5_1___3 = 1327,\n\tFN_SEL_PWM4_0___4 = 1328,\n\tFN_SEL_PWM4_1___4 = 1329,\n\tFN_SEL_PWM3_0___4 = 1330,\n\tFN_SEL_PWM3_1___4 = 1331,\n\tFN_SEL_PWM2_0___4 = 1332,\n\tFN_SEL_PWM2_1___4 = 1333,\n\tFN_SEL_PWM1_0___4 = 1334,\n\tFN_SEL_PWM1_1___4 = 1335,\n\tFN_SEL_VIN4_0___3 = 1336,\n\tFN_SEL_VIN4_1___3 = 1337,\n\tPINMUX_FUNCTION_END___5 = 1338,\n\tPINMUX_MARK_BEGIN___5 = 1339,\n\tCLKOUT_MARK___4 = 1340,\n\tMSIOF0_RXD_MARK___5 = 1341,\n\tMSIOF0_TXD_MARK___5 = 1342,\n\tMSIOF0_SCK_MARK___5 = 1343,\n\tSSI_SDATA5_MARK___3 = 1344,\n\tSSI_WS5_MARK___3 = 1345,\n\tSSI_SCK5_MARK___3 = 1346,\n\tGP7_03_MARK___3 = 1347,\n\tGP7_02_MARK___3 = 1348,\n\tAVS2_MARK___3 = 1349,\n\tAVS1_MARK___4 = 1350,\n\tIP0_3_0_MARK___4 = 1351,\n\tAVB_MDC_MARK___4 = 1352,\n\tMSIOF2_SS2_C_MARK___3 = 1353,\n\tIP1_3_0_MARK___4 = 1354,\n\tIRQ2_MARK___4 = 1355,\n\tQCPV_QDE_MARK___3 = 1356,\n\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK___4 = 1357,\n\tVI4_DATA2_B_MARK___3 = 1358,\n\tMSIOF3_SYNC_E_MARK___3 = 1359,\n\tPWM3_B_MARK___5 = 1360,\n\tIP2_3_0_MARK___4 = 1361,\n\tA1_MARK___4 = 1362,\n\tLCDOUT17_MARK___3 = 1363,\n\tMSIOF3_TXD_B_MARK___3 = 1364,\n\tVI4_DATA9_MARK___3 = 1365,\n\tDU_DB1_MARK___4 = 1366,\n\tPWM4_A_MARK___4 = 1367,\n\tIP3_3_0_MARK___4 = 1368,\n\tA9_MARK___4 = 1369,\n\tMSIOF2_SCK_A_MARK___3 = 1370,\n\tCTS4_N_B_MARK___3 = 1371,\n\tVI5_VSYNC_N_MARK___3 = 1372,\n\tIP0_7_4_MARK___4 = 1373,\n\tAVB_MAGIC_MARK___4 = 1374,\n\tMSIOF2_SS1_C_MARK___3 = 1375,\n\tSCK4_A_MARK___3 = 1376,\n\tIP1_7_4_MARK___4 = 1377,\n\tIRQ3_MARK___4 = 1378,\n\tQSTVB_QVE_MARK___3 = 1379,\n\tDU_DOTCLKOUT1_MARK___3 = 1380,\n\tVI4_DATA3_B_MARK___3 = 1381,\n\tMSIOF3_SCK_E_MARK___3 = 1382,\n\tPWM4_B_MARK___4 = 1383,\n\tIP2_7_4_MARK___4 = 1384,\n\tA2_MARK___4 = 1385,\n\tLCDOUT18_MARK___3 = 1386,\n\tMSIOF3_SCK_B_MARK___3 = 1387,\n\tVI4_DATA10_MARK___3 = 1388,\n\tDU_DB2_MARK___4 = 1389,\n\tPWM5_A_MARK___3 = 1390,\n\tIP3_7_4_MARK___4 = 1391,\n\tA10_MARK___4 = 1392,\n\tMSIOF2_RXD_A_MARK___3 = 1393,\n\tRTS4_N_B_MARK___3 = 1394,\n\tVI5_HSYNC_N_MARK___3 = 1395,\n\tIP0_11_8_MARK___4 = 1396,\n\tAVB_PHY_INT_MARK___4 = 1397,\n\tMSIOF2_SYNC_C_MARK___3 = 1398,\n\tRX4_A_MARK___3 = 1399,\n\tIP1_11_8_MARK___4 = 1400,\n\tIRQ4_MARK___4 = 1401,\n\tQSTH_QHS_MARK___3 = 1402,\n\tDU_EXHSYNC_DU_HSYNC_MARK___4 = 1403,\n\tVI4_DATA4_B_MARK___3 = 1404,\n\tMSIOF3_RXD_E_MARK___3 = 1405,\n\tPWM5_B_MARK___3 = 1406,\n\tIP2_11_8_MARK___4 = 1407,\n\tA3_MARK___4 = 1408,\n\tLCDOUT19_MARK___3 = 1409,\n\tMSIOF3_RXD_B_MARK___3 = 1410,\n\tVI4_DATA11_MARK___3 = 1411,\n\tDU_DB3_MARK___4 = 1412,\n\tPWM6_A_MARK___3 = 1413,\n\tIP3_11_8_MARK___4 = 1414,\n\tA11_MARK___4 = 1415,\n\tTX3_B_MARK___4 = 1416,\n\tMSIOF2_TXD_A_MARK___3 = 1417,\n\tHTX4_B_MARK___3 = 1418,\n\tHSCK4_MARK___3 = 1419,\n\tVI5_FIELD_MARK___3 = 1420,\n\tSCL6_A_MARK___3 = 1421,\n\tAVB_AVTP_CAPTURE_B_MARK___3 = 1422,\n\tPWM2_B_MARK___4 = 1423,\n\tIP0_15_12_MARK___4 = 1424,\n\tAVB_LINK_MARK___4 = 1425,\n\tMSIOF2_SCK_C_MARK___3 = 1426,\n\tTX4_A_MARK___3 = 1427,\n\tIP1_15_12_MARK___4 = 1428,\n\tIRQ5_MARK___5 = 1429,\n\tQSTB_QHE_MARK___3 = 1430,\n\tDU_EXVSYNC_DU_VSYNC_MARK___4 = 1431,\n\tVI4_DATA5_B_MARK___3 = 1432,\n\tFSCLKST2_N_B_MARK___2 = 1433,\n\tMSIOF3_TXD_E_MARK___3 = 1434,\n\tPWM6_B_MARK___3 = 1435,\n\tIP2_15_12_MARK___4 = 1436,\n\tA4_MARK___4 = 1437,\n\tLCDOUT20_MARK___3 = 1438,\n\tMSIOF3_SS1_B_MARK___3 = 1439,\n\tVI4_DATA12_MARK___3 = 1440,\n\tVI5_DATA12_MARK___3 = 1441,\n\tDU_DB4_MARK___4 = 1442,\n\tIP3_15_12_MARK___4 = 1443,\n\tA12_MARK___4 = 1444,\n\tLCDOUT12_MARK___3 = 1445,\n\tMSIOF3_SCK_C_MARK___3 = 1446,\n\tHRX4_A_MARK___3 = 1447,\n\tVI5_DATA8_MARK___3 = 1448,\n\tDU_DG4_MARK___4 = 1449,\n\tIP0_19_16_MARK___4 = 1450,\n\tAVB_AVTP_MATCH_A_MARK___3 = 1451,\n\tMSIOF2_RXD_C_MARK___3 = 1452,\n\tCTS4_N_A_MARK___3 = 1453,\n\tFSCLKST2_N_A_MARK___2 = 1454,\n\tIP1_19_16_MARK___4 = 1455,\n\tPWM0_MARK___4 = 1456,\n\tAVB_AVTP_PPS_MARK___4 = 1457,\n\tVI4_DATA6_B_MARK___3 = 1458,\n\tIECLK_B_MARK___3 = 1459,\n\tIP2_19_16_MARK___4 = 1460,\n\tA5_MARK___4 = 1461,\n\tLCDOUT21_MARK___3 = 1462,\n\tMSIOF3_SS2_B_MARK___3 = 1463,\n\tSCK4_B_MARK___3 = 1464,\n\tVI4_DATA13_MARK___3 = 1465,\n\tVI5_DATA13_MARK___3 = 1466,\n\tDU_DB5_MARK___4 = 1467,\n\tIP3_19_16_MARK___4 = 1468,\n\tA13_MARK___4 = 1469,\n\tLCDOUT13_MARK___3 = 1470,\n\tMSIOF3_SYNC_C_MARK___3 = 1471,\n\tHTX4_A_MARK___3 = 1472,\n\tVI5_DATA9_MARK___3 = 1473,\n\tDU_DG5_MARK___4 = 1474,\n\tIP0_23_20_MARK___4 = 1475,\n\tAVB_AVTP_CAPTURE_A_MARK___3 = 1476,\n\tMSIOF2_TXD_C_MARK___3 = 1477,\n\tRTS4_N_A_MARK___3 = 1478,\n\tIP1_23_20_MARK___4 = 1479,\n\tPWM1_A_MARK___5 = 1480,\n\tHRX3_D_MARK___3 = 1481,\n\tVI4_DATA7_B_MARK___3 = 1482,\n\tIERX_B_MARK___3 = 1483,\n\tIP2_23_20_MARK___4 = 1484,\n\tA6_MARK___4 = 1485,\n\tLCDOUT22_MARK___3 = 1486,\n\tMSIOF2_SS1_A_MARK___3 = 1487,\n\tRX4_B_MARK___3 = 1488,\n\tVI4_DATA14_MARK___3 = 1489,\n\tVI5_DATA14_MARK___3 = 1490,\n\tDU_DB6_MARK___4 = 1491,\n\tIP3_23_20_MARK___4 = 1492,\n\tA14_MARK___4 = 1493,\n\tLCDOUT14_MARK___3 = 1494,\n\tMSIOF3_RXD_C_MARK___3 = 1495,\n\tHCTS4_N_MARK___3 = 1496,\n\tVI5_DATA10_MARK___3 = 1497,\n\tDU_DG6_MARK___4 = 1498,\n\tIP0_27_24_MARK___4 = 1499,\n\tIRQ0_MARK___4 = 1500,\n\tQPOLB_MARK___3 = 1501,\n\tDU_CDE_MARK___4 = 1502,\n\tVI4_DATA0_B_MARK___3 = 1503,\n\tCAN0_TX_B_MARK___3 = 1504,\n\tCANFD0_TX_B_MARK___4 = 1505,\n\tMSIOF3_SS2_E_MARK___3 = 1506,\n\tIP1_27_24_MARK___4 = 1507,\n\tPWM2_A_MARK___4 = 1508,\n\tHTX3_D_MARK___3 = 1509,\n\tIETX_B_MARK___3 = 1510,\n\tIP2_27_24_MARK___4 = 1511,\n\tA7_MARK___4 = 1512,\n\tLCDOUT23_MARK___3 = 1513,\n\tMSIOF2_SS2_A_MARK___3 = 1514,\n\tTX4_B_MARK___3 = 1515,\n\tVI4_DATA15_MARK___3 = 1516,\n\tVI5_DATA15_MARK___3 = 1517,\n\tDU_DB7_MARK___4 = 1518,\n\tIP3_27_24_MARK___4 = 1519,\n\tA15_MARK___4 = 1520,\n\tLCDOUT15_MARK___3 = 1521,\n\tMSIOF3_TXD_C_MARK___3 = 1522,\n\tHRTS4_N_MARK___3 = 1523,\n\tVI5_DATA11_MARK___3 = 1524,\n\tDU_DG7_MARK___4 = 1525,\n\tIP0_31_28_MARK___4 = 1526,\n\tIRQ1_MARK___4 = 1527,\n\tQPOLA_MARK___3 = 1528,\n\tDU_DISP_MARK___4 = 1529,\n\tVI4_DATA1_B_MARK___3 = 1530,\n\tCAN0_RX_B_MARK___3 = 1531,\n\tCANFD0_RX_B_MARK___4 = 1532,\n\tMSIOF3_SS1_E_MARK___3 = 1533,\n\tIP1_31_28_MARK___4 = 1534,\n\tA0_MARK___4 = 1535,\n\tLCDOUT16_MARK___3 = 1536,\n\tMSIOF3_SYNC_B_MARK___3 = 1537,\n\tVI4_DATA8_MARK___3 = 1538,\n\tDU_DB0_MARK___4 = 1539,\n\tPWM3_A_MARK___5 = 1540,\n\tIP2_31_28_MARK___4 = 1541,\n\tA8_MARK___4 = 1542,\n\tRX3_B_MARK___4 = 1543,\n\tMSIOF2_SYNC_A_MARK___3 = 1544,\n\tHRX4_B_MARK___3 = 1545,\n\tSDA6_A_MARK___3 = 1546,\n\tAVB_AVTP_MATCH_B_MARK___3 = 1547,\n\tPWM1_B_MARK___5 = 1548,\n\tIP3_31_28_MARK___4 = 1549,\n\tA16_MARK___4 = 1550,\n\tLCDOUT8_MARK___3 = 1551,\n\tVI4_FIELD_MARK___3 = 1552,\n\tDU_DG0_MARK___4 = 1553,\n\tIP4_3_0_MARK___4 = 1554,\n\tA17_MARK___4 = 1555,\n\tLCDOUT9_MARK___3 = 1556,\n\tVI4_VSYNC_N_MARK___3 = 1557,\n\tDU_DG1_MARK___4 = 1558,\n\tIP5_3_0_MARK___4 = 1559,\n\tWE0_N_MARK___4 = 1560,\n\tMSIOF3_TXD_D_MARK___3 = 1561,\n\tCTS3_N_MARK___4 = 1562,\n\tHCTS3_N_MARK___4 = 1563,\n\tSCL6_B_MARK___3 = 1564,\n\tCAN_CLK_MARK___4 = 1565,\n\tIECLK_A_MARK___3 = 1566,\n\tIP6_3_0_MARK___4 = 1567,\n\tD5_MARK___4 = 1568,\n\tMSIOF2_SYNC_B_MARK___3 = 1569,\n\tVI4_DATA21_MARK___3 = 1570,\n\tVI5_DATA5_MARK___3 = 1571,\n\tIP7_3_0_MARK___4 = 1572,\n\tD13_MARK___4 = 1573,\n\tLCDOUT5_MARK___3 = 1574,\n\tMSIOF2_SS2_D_MARK___3 = 1575,\n\tTX4_C_MARK___3 = 1576,\n\tVI4_DATA5_A_MARK___3 = 1577,\n\tDU_DR5_MARK___4 = 1578,\n\tIP4_7_4_MARK___4 = 1579,\n\tA18_MARK___4 = 1580,\n\tLCDOUT10_MARK___3 = 1581,\n\tVI4_HSYNC_N_MARK___3 = 1582,\n\tDU_DG2_MARK___4 = 1583,\n\tIP5_7_4_MARK___4 = 1584,\n\tWE1_N_MARK___4 = 1585,\n\tMSIOF3_SS1_D_MARK___3 = 1586,\n\tRTS3_N_MARK___4 = 1587,\n\tHRTS3_N_MARK___4 = 1588,\n\tSDA6_B_MARK___3 = 1589,\n\tCAN1_RX_MARK___3 = 1590,\n\tCANFD1_RX_MARK___5 = 1591,\n\tIERX_A_MARK___3 = 1592,\n\tIP6_7_4_MARK___4 = 1593,\n\tD6_MARK___4 = 1594,\n\tMSIOF2_RXD_B_MARK___3 = 1595,\n\tVI4_DATA22_MARK___3 = 1596,\n\tVI5_DATA6_MARK___3 = 1597,\n\tIP7_7_4_MARK___4 = 1598,\n\tD14_MARK___4 = 1599,\n\tLCDOUT6_MARK___3 = 1600,\n\tMSIOF3_SS1_A_MARK___3 = 1601,\n\tHRX3_C_MARK___3 = 1602,\n\tVI4_DATA6_A_MARK___3 = 1603,\n\tDU_DR6_MARK___4 = 1604,\n\tSCL6_C_MARK___3 = 1605,\n\tIP4_11_8_MARK___4 = 1606,\n\tA19_MARK___4 = 1607,\n\tLCDOUT11_MARK___3 = 1608,\n\tVI4_CLKENB_MARK___3 = 1609,\n\tDU_DG3_MARK___4 = 1610,\n\tIP5_11_8_MARK___4 = 1611,\n\tEX_WAIT0_A_MARK___3 = 1612,\n\tQCLK_MARK___3 = 1613,\n\tVI4_CLK_MARK___3 = 1614,\n\tDU_DOTCLKOUT0_MARK___3 = 1615,\n\tIP6_11_8_MARK___4 = 1616,\n\tD7_MARK___4 = 1617,\n\tMSIOF2_TXD_B_MARK___3 = 1618,\n\tVI4_DATA23_MARK___3 = 1619,\n\tVI5_DATA7_MARK___3 = 1620,\n\tIP7_11_8_MARK___4 = 1621,\n\tD15_MARK___4 = 1622,\n\tLCDOUT7_MARK___3 = 1623,\n\tMSIOF3_SS2_A_MARK___3 = 1624,\n\tHTX3_C_MARK___3 = 1625,\n\tVI4_DATA7_A_MARK___3 = 1626,\n\tDU_DR7_MARK___4 = 1627,\n\tSDA6_C_MARK___3 = 1628,\n\tIP4_15_12_MARK___4 = 1629,\n\tCS0_N_MARK___4 = 1630,\n\tVI5_CLKENB_MARK___3 = 1631,\n\tIP5_15_12_MARK___4 = 1632,\n\tD0_MARK___4 = 1633,\n\tMSIOF2_SS1_B_MARK___3 = 1634,\n\tMSIOF3_SCK_A_MARK___3 = 1635,\n\tVI4_DATA16_MARK___3 = 1636,\n\tVI5_DATA0_MARK___3 = 1637,\n\tIP6_15_12_MARK___4 = 1638,\n\tD8_MARK___4 = 1639,\n\tLCDOUT0_MARK___3 = 1640,\n\tMSIOF2_SCK_D_MARK___3 = 1641,\n\tSCK4_C_MARK___3 = 1642,\n\tVI4_DATA0_A_MARK___3 = 1643,\n\tDU_DR0_MARK___4 = 1644,\n\tIP4_19_16_MARK___4 = 1645,\n\tCS1_N_MARK___4 = 1646,\n\tVI5_CLK_MARK___3 = 1647,\n\tEX_WAIT0_B_MARK___3 = 1648,\n\tIP5_19_16_MARK___4 = 1649,\n\tD1_MARK___4 = 1650,\n\tMSIOF2_SS2_B_MARK___3 = 1651,\n\tMSIOF3_SYNC_A_MARK___3 = 1652,\n\tVI4_DATA17_MARK___3 = 1653,\n\tVI5_DATA1_MARK___3 = 1654,\n\tIP6_19_16_MARK___4 = 1655,\n\tD9_MARK___4 = 1656,\n\tLCDOUT1_MARK___3 = 1657,\n\tMSIOF2_SYNC_D_MARK___3 = 1658,\n\tVI4_DATA1_A_MARK___3 = 1659,\n\tDU_DR1_MARK___4 = 1660,\n\tIP7_19_16_MARK___4 = 1661,\n\tSD0_CLK_MARK___3 = 1662,\n\tMSIOF1_SCK_E_MARK___3 = 1663,\n\tSTP_OPWM_0_B_MARK___3 = 1664,\n\tIP4_23_20_MARK___4 = 1665,\n\tBS_N_MARK___4 = 1666,\n\tQSTVA_QVS_MARK___3 = 1667,\n\tMSIOF3_SCK_D_MARK___3 = 1668,\n\tSCK3_MARK___4 = 1669,\n\tHSCK3_MARK___4 = 1670,\n\tCAN1_TX_MARK___3 = 1671,\n\tCANFD1_TX_MARK___5 = 1672,\n\tIETX_A_MARK___3 = 1673,\n\tIP5_23_20_MARK___4 = 1674,\n\tD2_MARK___4 = 1675,\n\tMSIOF3_RXD_A_MARK___3 = 1676,\n\tVI4_DATA18_MARK___3 = 1677,\n\tVI5_DATA2_MARK___3 = 1678,\n\tIP6_23_20_MARK___4 = 1679,\n\tD10_MARK___4 = 1680,\n\tLCDOUT2_MARK___3 = 1681,\n\tMSIOF2_RXD_D_MARK___3 = 1682,\n\tHRX3_B_MARK___4 = 1683,\n\tVI4_DATA2_A_MARK___3 = 1684,\n\tCTS4_N_C_MARK___3 = 1685,\n\tDU_DR2_MARK___4 = 1686,\n\tIP7_23_20_MARK___4 = 1687,\n\tSD0_CMD_MARK___3 = 1688,\n\tMSIOF1_SYNC_E_MARK___3 = 1689,\n\tSTP_IVCXO27_0_B_MARK___3 = 1690,\n\tIP4_27_24_MARK___4 = 1691,\n\tRD_N_MARK___4 = 1692,\n\tMSIOF3_SYNC_D_MARK___3 = 1693,\n\tRX3_A_MARK___4 = 1694,\n\tHRX3_A_MARK___4 = 1695,\n\tCAN0_TX_A_MARK___3 = 1696,\n\tCANFD0_TX_A_MARK___4 = 1697,\n\tIP5_27_24_MARK___4 = 1698,\n\tD3_MARK___4 = 1699,\n\tMSIOF3_TXD_A_MARK___3 = 1700,\n\tVI4_DATA19_MARK___3 = 1701,\n\tVI5_DATA3_MARK___3 = 1702,\n\tIP6_27_24_MARK___4 = 1703,\n\tD11_MARK___4 = 1704,\n\tLCDOUT3_MARK___3 = 1705,\n\tMSIOF2_TXD_D_MARK___3 = 1706,\n\tHTX3_B_MARK___4 = 1707,\n\tVI4_DATA3_A_MARK___3 = 1708,\n\tRTS4_N_C_MARK___3 = 1709,\n\tDU_DR3_MARK___4 = 1710,\n\tIP7_27_24_MARK___4 = 1711,\n\tSD0_DAT0_MARK___3 = 1712,\n\tMSIOF1_RXD_E_MARK___3 = 1713,\n\tTS_SCK0_B_MARK___3 = 1714,\n\tSTP_ISCLK_0_B_MARK___3 = 1715,\n\tIP4_31_28_MARK___4 = 1716,\n\tRD_WR_N_MARK___4 = 1717,\n\tMSIOF3_RXD_D_MARK___3 = 1718,\n\tTX3_A_MARK___4 = 1719,\n\tHTX3_A_MARK___4 = 1720,\n\tCAN0_RX_A_MARK___3 = 1721,\n\tCANFD0_RX_A_MARK___4 = 1722,\n\tIP5_31_28_MARK___4 = 1723,\n\tD4_MARK___4 = 1724,\n\tMSIOF2_SCK_B_MARK___3 = 1725,\n\tVI4_DATA20_MARK___3 = 1726,\n\tVI5_DATA4_MARK___3 = 1727,\n\tIP6_31_28_MARK___4 = 1728,\n\tD12_MARK___4 = 1729,\n\tLCDOUT4_MARK___3 = 1730,\n\tMSIOF2_SS1_D_MARK___3 = 1731,\n\tRX4_C_MARK___3 = 1732,\n\tVI4_DATA4_A_MARK___3 = 1733,\n\tDU_DR4_MARK___4 = 1734,\n\tIP7_31_28_MARK___4 = 1735,\n\tSD0_DAT1_MARK___3 = 1736,\n\tMSIOF1_TXD_E_MARK___3 = 1737,\n\tTS_SPSYNC0_B_MARK___3 = 1738,\n\tSTP_ISSYNC_0_B_MARK___3 = 1739,\n\tIP8_3_0_MARK___4 = 1740,\n\tSD0_DAT2_MARK___3 = 1741,\n\tMSIOF1_SS1_E_MARK___3 = 1742,\n\tTS_SDAT0_B_MARK___3 = 1743,\n\tSTP_ISD_0_B_MARK___3 = 1744,\n\tIP9_3_0_MARK___4 = 1745,\n\tSD2_CLK_MARK___3 = 1746,\n\tNFDATA8_MARK___3 = 1747,\n\tIP10_3_0_MARK___4 = 1748,\n\tSD3_CMD_MARK___3 = 1749,\n\tNFRE_N_MARK___3 = 1750,\n\tIP11_3_0_MARK___3 = 1751,\n\tSD3_DAT7_MARK___3 = 1752,\n\tSD3_WP_MARK___3 = 1753,\n\tNFDATA7_MARK___3 = 1754,\n\tIP8_7_4_MARK___4 = 1755,\n\tSD0_DAT3_MARK___3 = 1756,\n\tMSIOF1_SS2_E_MARK___3 = 1757,\n\tTS_SDEN0_B_MARK___3 = 1758,\n\tSTP_ISEN_0_B_MARK___3 = 1759,\n\tIP9_7_4_MARK___4 = 1760,\n\tSD2_CMD_MARK___3 = 1761,\n\tNFDATA9_MARK___3 = 1762,\n\tIP10_7_4_MARK___4 = 1763,\n\tSD3_DAT0_MARK___3 = 1764,\n\tNFDATA0_MARK___3 = 1765,\n\tIP11_7_4_MARK___3 = 1766,\n\tSD3_DS_MARK___3 = 1767,\n\tNFCLE_MARK___3 = 1768,\n\tIP8_11_8_MARK___4 = 1769,\n\tSD1_CLK_MARK___3 = 1770,\n\tMSIOF1_SCK_G_MARK___3 = 1771,\n\tSIM0_CLK_A_MARK___3 = 1772,\n\tIP9_11_8_MARK___4 = 1773,\n\tSD2_DAT0_MARK___3 = 1774,\n\tNFDATA10_MARK___3 = 1775,\n\tIP10_11_8_MARK___4 = 1776,\n\tSD3_DAT1_MARK___3 = 1777,\n\tNFDATA1_MARK___3 = 1778,\n\tIP11_11_8_MARK___3 = 1779,\n\tSD0_CD_MARK___3 = 1780,\n\tNFDATA14_A_MARK___3 = 1781,\n\tSCL2_B_MARK___3 = 1782,\n\tSIM0_RST_A_MARK___3 = 1783,\n\tIP8_15_12_MARK___4 = 1784,\n\tSD1_CMD_MARK___3 = 1785,\n\tMSIOF1_SYNC_G_MARK___3 = 1786,\n\tNFCE_N_B_MARK___3 = 1787,\n\tSIM0_D_A_MARK___3 = 1788,\n\tSTP_IVCXO27_1_B_MARK___3 = 1789,\n\tIP9_15_12_MARK___4 = 1790,\n\tSD2_DAT1_MARK___3 = 1791,\n\tNFDATA11_MARK___3 = 1792,\n\tIP10_15_12_MARK___4 = 1793,\n\tSD3_DAT2_MARK___3 = 1794,\n\tNFDATA2_MARK___3 = 1795,\n\tIP11_15_12_MARK___3 = 1796,\n\tSD0_WP_MARK___3 = 1797,\n\tNFDATA15_A_MARK___3 = 1798,\n\tSDA2_B_MARK___3 = 1799,\n\tIP8_19_16_MARK___4 = 1800,\n\tSD1_DAT0_MARK___3 = 1801,\n\tSD2_DAT4_MARK___3 = 1802,\n\tMSIOF1_RXD_G_MARK___3 = 1803,\n\tNFWP_N_B_MARK___3 = 1804,\n\tTS_SCK1_B_MARK___3 = 1805,\n\tSTP_ISCLK_1_B_MARK___3 = 1806,\n\tIP9_19_16_MARK___4 = 1807,\n\tSD2_DAT2_MARK___3 = 1808,\n\tNFDATA12_MARK___3 = 1809,\n\tIP10_19_16_MARK___4 = 1810,\n\tSD3_DAT3_MARK___3 = 1811,\n\tNFDATA3_MARK___3 = 1812,\n\tIP11_19_16_MARK___3 = 1813,\n\tSD1_CD_MARK___3 = 1814,\n\tNFRB_N_A_MARK___3 = 1815,\n\tSIM0_CLK_B_MARK___3 = 1816,\n\tIP8_23_20_MARK___4 = 1817,\n\tSD1_DAT1_MARK___3 = 1818,\n\tSD2_DAT5_MARK___3 = 1819,\n\tMSIOF1_TXD_G_MARK___3 = 1820,\n\tNFDATA14_B_MARK___3 = 1821,\n\tTS_SPSYNC1_B_MARK___3 = 1822,\n\tSTP_ISSYNC_1_B_MARK___3 = 1823,\n\tIP9_23_20_MARK___4 = 1824,\n\tSD2_DAT3_MARK___3 = 1825,\n\tNFDATA13_MARK___3 = 1826,\n\tIP10_23_20_MARK___3 = 1827,\n\tSD3_DAT4_MARK___3 = 1828,\n\tSD2_CD_A_MARK___3 = 1829,\n\tNFDATA4_MARK___3 = 1830,\n\tIP11_23_20_MARK___3 = 1831,\n\tSD1_WP_MARK___3 = 1832,\n\tNFCE_N_A_MARK___3 = 1833,\n\tSIM0_D_B_MARK___3 = 1834,\n\tIP8_27_24_MARK___4 = 1835,\n\tSD1_DAT2_MARK___3 = 1836,\n\tSD2_DAT6_MARK___3 = 1837,\n\tMSIOF1_SS1_G_MARK___3 = 1838,\n\tNFDATA15_B_MARK___3 = 1839,\n\tTS_SDAT1_B_MARK___3 = 1840,\n\tSTP_ISD_1_B_MARK___3 = 1841,\n\tIP9_27_24_MARK___4 = 1842,\n\tSD2_DS_MARK___3 = 1843,\n\tNFALE_MARK___3 = 1844,\n\tSATA_DEVSLP_B_MARK___2 = 1845,\n\tIP10_27_24_MARK___3 = 1846,\n\tSD3_DAT5_MARK___3 = 1847,\n\tSD2_WP_A_MARK___3 = 1848,\n\tNFDATA5_MARK___3 = 1849,\n\tIP11_27_24_MARK___3 = 1850,\n\tSCK0_MARK___5 = 1851,\n\tHSCK1_B_MARK___4 = 1852,\n\tMSIOF1_SS2_B_MARK___3 = 1853,\n\tAUDIO_CLKC_B_MARK___3 = 1854,\n\tSDA2_A_MARK___3 = 1855,\n\tSIM0_RST_B_MARK___3 = 1856,\n\tSTP_OPWM_0_C_MARK___3 = 1857,\n\tRIF0_CLK_B_MARK___3 = 1858,\n\tADICHS2_MARK___3 = 1859,\n\tSCK5_B_MARK___3 = 1860,\n\tIP8_31_28_MARK___4 = 1861,\n\tSD1_DAT3_MARK___3 = 1862,\n\tSD2_DAT7_MARK___3 = 1863,\n\tMSIOF1_SS2_G_MARK___3 = 1864,\n\tNFRB_N_B_MARK___3 = 1865,\n\tTS_SDEN1_B_MARK___3 = 1866,\n\tSTP_ISEN_1_B_MARK___3 = 1867,\n\tIP9_31_28_MARK___4 = 1868,\n\tSD3_CLK_MARK___3 = 1869,\n\tNFWE_N_MARK___3 = 1870,\n\tIP10_31_28_MARK___3 = 1871,\n\tSD3_DAT6_MARK___3 = 1872,\n\tSD3_CD_MARK___3 = 1873,\n\tNFDATA6_MARK___3 = 1874,\n\tIP11_31_28_MARK___3 = 1875,\n\tRX0_MARK___5 = 1876,\n\tHRX1_B_MARK___4 = 1877,\n\tTS_SCK0_C_MARK___3 = 1878,\n\tSTP_ISCLK_0_C_MARK___3 = 1879,\n\tRIF0_D0_B_MARK___3 = 1880,\n\tIP12_3_0_MARK___3 = 1881,\n\tTX0_MARK___5 = 1882,\n\tHTX1_B_MARK___4 = 1883,\n\tTS_SPSYNC0_C_MARK___3 = 1884,\n\tSTP_ISSYNC_0_C_MARK___3 = 1885,\n\tRIF0_D1_B_MARK___3 = 1886,\n\tIP13_3_0_MARK___3 = 1887,\n\tTX2_A_MARK___3 = 1888,\n\tSD2_CD_B_MARK___3 = 1889,\n\tSCL1_A_MARK___3 = 1890,\n\tFMCLK_A_MARK___3 = 1891,\n\tRIF1_D1_C_MARK___3 = 1892,\n\tFSO_CFE_0_N_MARK___4 = 1893,\n\tIP14_3_0_MARK___3 = 1894,\n\tMSIOF0_SS1_MARK___5 = 1895,\n\tRX5_A_MARK___3 = 1896,\n\tNFWP_N_A_MARK___3 = 1897,\n\tAUDIO_CLKA_C_MARK___3 = 1898,\n\tSSI_SCK2_A_MARK___3 = 1899,\n\tSTP_IVCXO27_0_C_MARK___3 = 1900,\n\tAUDIO_CLKOUT3_A_MARK___3 = 1901,\n\tTCLK1_B_MARK___5 = 1902,\n\tIP15_3_0_MARK___3 = 1903,\n\tSSI_SDATA1_A_MARK___3 = 1904,\n\tIP12_7_4_MARK___3 = 1905,\n\tCTS0_N_MARK___5 = 1906,\n\tHCTS1_N_B_MARK___4 = 1907,\n\tMSIOF1_SYNC_B_MARK___3 = 1908,\n\tTS_SPSYNC1_C_MARK___3 = 1909,\n\tSTP_ISSYNC_1_C_MARK___3 = 1910,\n\tRIF1_SYNC_B_MARK___3 = 1911,\n\tAUDIO_CLKOUT_C_MARK___3 = 1912,\n\tADICS_SAMP_MARK___3 = 1913,\n\tIP13_7_4_MARK___3 = 1914,\n\tRX2_A_MARK___3 = 1915,\n\tSD2_WP_B_MARK___3 = 1916,\n\tSDA1_A_MARK___3 = 1917,\n\tFMIN_A_MARK___3 = 1918,\n\tRIF1_SYNC_C_MARK___3 = 1919,\n\tFSO_CFE_1_N_MARK___4 = 1920,\n\tIP14_7_4_MARK___3 = 1921,\n\tMSIOF0_SS2_MARK___5 = 1922,\n\tTX5_A_MARK___3 = 1923,\n\tMSIOF1_SS2_D_MARK___3 = 1924,\n\tAUDIO_CLKC_A_MARK___3 = 1925,\n\tSSI_WS2_A_MARK___3 = 1926,\n\tSTP_OPWM_0_D_MARK___3 = 1927,\n\tAUDIO_CLKOUT_D_MARK___3 = 1928,\n\tSPEEDIN_B_MARK___4 = 1929,\n\tIP15_7_4_MARK___3 = 1930,\n\tSSI_SDATA2_A_MARK___3 = 1931,\n\tSSI_SCK1_B_MARK___3 = 1932,\n\tIP12_11_8_MARK___3 = 1933,\n\tRTS0_N_MARK___5 = 1934,\n\tHRTS1_N_B_MARK___4 = 1935,\n\tMSIOF1_SS1_B_MARK___3 = 1936,\n\tAUDIO_CLKA_B_MARK___3 = 1937,\n\tSCL2_A_MARK___3 = 1938,\n\tSTP_IVCXO27_1_C_MARK___3 = 1939,\n\tRIF0_SYNC_B_MARK___3 = 1940,\n\tADICHS1_MARK___3 = 1941,\n\tIP13_11_8_MARK___3 = 1942,\n\tHSCK0_MARK___4 = 1943,\n\tMSIOF1_SCK_D_MARK___3 = 1944,\n\tAUDIO_CLKB_A_MARK___3 = 1945,\n\tSSI_SDATA1_B_MARK___3 = 1946,\n\tTS_SCK0_D_MARK___3 = 1947,\n\tSTP_ISCLK_0_D_MARK___3 = 1948,\n\tRIF0_CLK_C_MARK___3 = 1949,\n\tRX5_B_MARK___3 = 1950,\n\tIP14_11_8_MARK___3 = 1951,\n\tMLB_CLK_MARK___3 = 1952,\n\tMSIOF1_SCK_F_MARK___3 = 1953,\n\tSCL1_B_MARK___3 = 1954,\n\tIP15_11_8_MARK___3 = 1955,\n\tSSI_SCK349_MARK___3 = 1956,\n\tMSIOF1_SS1_A_MARK___3 = 1957,\n\tSTP_OPWM_0_A_MARK___3 = 1958,\n\tIP12_15_12_MARK___3 = 1959,\n\tRX1_A_MARK___5 = 1960,\n\tHRX1_A_MARK___4 = 1961,\n\tTS_SDAT0_C_MARK___3 = 1962,\n\tSTP_ISD_0_C_MARK___3 = 1963,\n\tRIF1_CLK_C_MARK___3 = 1964,\n\tIP13_15_12_MARK___3 = 1965,\n\tHRX0_MARK___4 = 1966,\n\tMSIOF1_RXD_D_MARK___3 = 1967,\n\tSSI_SDATA2_B_MARK___3 = 1968,\n\tTS_SDEN0_D_MARK___3 = 1969,\n\tSTP_ISEN_0_D_MARK___3 = 1970,\n\tRIF0_D0_C_MARK___3 = 1971,\n\tIP14_15_12_MARK___3 = 1972,\n\tMLB_SIG_MARK___3 = 1973,\n\tRX1_B_MARK___5 = 1974,\n\tMSIOF1_SYNC_F_MARK___3 = 1975,\n\tSDA1_B_MARK___3 = 1976,\n\tIP15_15_12_MARK___3 = 1977,\n\tSSI_WS349_MARK___3 = 1978,\n\tHCTS2_N_A_MARK___3 = 1979,\n\tMSIOF1_SS2_A_MARK___3 = 1980,\n\tSTP_IVCXO27_0_A_MARK___3 = 1981,\n\tIP12_19_16_MARK___3 = 1982,\n\tTX1_A_MARK___5 = 1983,\n\tHTX1_A_MARK___4 = 1984,\n\tTS_SDEN0_C_MARK___3 = 1985,\n\tSTP_ISEN_0_C_MARK___3 = 1986,\n\tRIF1_D0_C_MARK___3 = 1987,\n\tIP13_19_16_MARK___3 = 1988,\n\tHTX0_MARK___4 = 1989,\n\tMSIOF1_TXD_D_MARK___3 = 1990,\n\tSSI_SDATA9_B_MARK___3 = 1991,\n\tTS_SDAT0_D_MARK___3 = 1992,\n\tSTP_ISD_0_D_MARK___3 = 1993,\n\tRIF0_D1_C_MARK___3 = 1994,\n\tIP14_19_16_MARK___3 = 1995,\n\tMLB_DAT_MARK___3 = 1996,\n\tTX1_B_MARK___5 = 1997,\n\tMSIOF1_RXD_F_MARK___3 = 1998,\n\tIP15_19_16_MARK___3 = 1999,\n\tSSI_SDATA3_MARK___3 = 2000,\n\tHRTS2_N_A_MARK___3 = 2001,\n\tMSIOF1_TXD_A_MARK___3 = 2002,\n\tTS_SCK0_A_MARK___3 = 2003,\n\tSTP_ISCLK_0_A_MARK___3 = 2004,\n\tRIF0_D1_A_MARK___3 = 2005,\n\tRIF2_D0_A_MARK___3 = 2006,\n\tIP12_23_20_MARK___3 = 2007,\n\tCTS1_N_MARK___4 = 2008,\n\tHCTS1_N_A_MARK___4 = 2009,\n\tMSIOF1_RXD_B_MARK___3 = 2010,\n\tTS_SDEN1_C_MARK___3 = 2011,\n\tSTP_ISEN_1_C_MARK___3 = 2012,\n\tRIF1_D0_B_MARK___3 = 2013,\n\tADIDATA_MARK___3 = 2014,\n\tIP13_23_20_MARK___3 = 2015,\n\tHCTS0_N_MARK___4 = 2016,\n\tRX2_B_MARK___3 = 2017,\n\tMSIOF1_SYNC_D_MARK___3 = 2018,\n\tSSI_SCK9_A_MARK___3 = 2019,\n\tTS_SPSYNC0_D_MARK___3 = 2020,\n\tSTP_ISSYNC_0_D_MARK___3 = 2021,\n\tRIF0_SYNC_C_MARK___3 = 2022,\n\tAUDIO_CLKOUT1_A_MARK___3 = 2023,\n\tIP14_23_20_MARK___3 = 2024,\n\tSSI_SCK01239_MARK___3 = 2025,\n\tMSIOF1_TXD_F_MARK___3 = 2026,\n\tIP15_23_20_MARK___3 = 2027,\n\tSSI_SCK4_MARK___3 = 2028,\n\tHRX2_A_MARK___3 = 2029,\n\tMSIOF1_SCK_A_MARK___3 = 2030,\n\tTS_SDAT0_A_MARK___3 = 2031,\n\tSTP_ISD_0_A_MARK___3 = 2032,\n\tRIF0_CLK_A_MARK___3 = 2033,\n\tRIF2_CLK_A_MARK___3 = 2034,\n\tIP12_27_24_MARK___3 = 2035,\n\tRTS1_N_MARK___4 = 2036,\n\tHRTS1_N_A_MARK___4 = 2037,\n\tMSIOF1_TXD_B_MARK___3 = 2038,\n\tTS_SDAT1_C_MARK___3 = 2039,\n\tSTP_ISD_1_C_MARK___3 = 2040,\n\tRIF1_D1_B_MARK___3 = 2041,\n\tADICHS0_MARK___3 = 2042,\n\tIP13_27_24_MARK___3 = 2043,\n\tHRTS0_N_MARK___4 = 2044,\n\tTX2_B_MARK___3 = 2045,\n\tMSIOF1_SS1_D_MARK___3 = 2046,\n\tSSI_WS9_A_MARK___3 = 2047,\n\tSTP_IVCXO27_0_D_MARK___3 = 2048,\n\tBPFCLK_A_MARK___3 = 2049,\n\tAUDIO_CLKOUT2_A_MARK___3 = 2050,\n\tIP14_27_24_MARK___3 = 2051,\n\tSSI_WS01239_MARK___3 = 2052,\n\tMSIOF1_SS1_F_MARK___3 = 2053,\n\tIP15_27_24_MARK___3 = 2054,\n\tSSI_WS4_MARK___3 = 2055,\n\tHTX2_A_MARK___3 = 2056,\n\tMSIOF1_SYNC_A_MARK___3 = 2057,\n\tTS_SDEN0_A_MARK___3 = 2058,\n\tSTP_ISEN_0_A_MARK___3 = 2059,\n\tRIF0_SYNC_A_MARK___3 = 2060,\n\tRIF2_SYNC_A_MARK___3 = 2061,\n\tIP12_31_28_MARK___3 = 2062,\n\tSCK2_MARK___3 = 2063,\n\tSCIF_CLK_B_MARK___4 = 2064,\n\tMSIOF1_SCK_B_MARK___3 = 2065,\n\tTS_SCK1_C_MARK___3 = 2066,\n\tSTP_ISCLK_1_C_MARK___3 = 2067,\n\tRIF1_CLK_B_MARK___3 = 2068,\n\tADICLK_MARK___3 = 2069,\n\tIP13_31_28_MARK___3 = 2070,\n\tMSIOF0_SYNC_MARK___5 = 2071,\n\tAUDIO_CLKOUT_A_MARK___3 = 2072,\n\tTX5_B_MARK___3 = 2073,\n\tBPFCLK_D_MARK___3 = 2074,\n\tIP14_31_28_MARK___3 = 2075,\n\tSSI_SDATA0_MARK___3 = 2076,\n\tMSIOF1_SS2_F_MARK___3 = 2077,\n\tIP15_31_28_MARK___3 = 2078,\n\tSSI_SDATA4_MARK___3 = 2079,\n\tHSCK2_A_MARK___3 = 2080,\n\tMSIOF1_RXD_A_MARK___3 = 2081,\n\tTS_SPSYNC0_A_MARK___3 = 2082,\n\tSTP_ISSYNC_0_A_MARK___3 = 2083,\n\tRIF0_D0_A_MARK___3 = 2084,\n\tRIF2_D1_A_MARK___3 = 2085,\n\tIP16_3_0_MARK___3 = 2086,\n\tSSI_SCK6_MARK___3 = 2087,\n\tSIM0_RST_D_MARK___3 = 2088,\n\tIP17_3_0_MARK___3 = 2089,\n\tAUDIO_CLKA_A_MARK___3 = 2090,\n\tIP18_3_0_MARK___3 = 2091,\n\tGP6_30_MARK___2 = 2092,\n\tAUDIO_CLKOUT2_B_MARK___3 = 2093,\n\tSSI_SCK9_B_MARK___3 = 2094,\n\tTS_SDEN0_E_MARK___3 = 2095,\n\tSTP_ISEN_0_E_MARK___3 = 2096,\n\tRIF2_D0_B_MARK___3 = 2097,\n\tTPU0TO2_MARK___4 = 2098,\n\tFMCLK_C_MARK___3 = 2099,\n\tFMCLK_D_MARK___3 = 2100,\n\tIP16_7_4_MARK___3 = 2101,\n\tSSI_WS6_MARK___3 = 2102,\n\tSIM0_D_D_MARK___3 = 2103,\n\tIP17_7_4_MARK___3 = 2104,\n\tAUDIO_CLKB_B_MARK___3 = 2105,\n\tSCIF_CLK_A_MARK___4 = 2106,\n\tSTP_IVCXO27_1_D_MARK___3 = 2107,\n\tREMOCON_A_MARK___3 = 2108,\n\tTCLK1_A_MARK___5 = 2109,\n\tIP18_7_4_MARK___3 = 2110,\n\tGP6_31_MARK___2 = 2111,\n\tAUDIO_CLKOUT3_B_MARK___3 = 2112,\n\tSSI_WS9_B_MARK___3 = 2113,\n\tTS_SPSYNC0_E_MARK___3 = 2114,\n\tSTP_ISSYNC_0_E_MARK___3 = 2115,\n\tRIF2_D1_B_MARK___3 = 2116,\n\tTPU0TO3_MARK___4 = 2117,\n\tFMIN_C_MARK___3 = 2118,\n\tFMIN_D_MARK___3 = 2119,\n\tIP16_11_8_MARK___3 = 2120,\n\tSSI_SDATA6_MARK___3 = 2121,\n\tSIM0_CLK_D_MARK___3 = 2122,\n\tSATA_DEVSLP_A_MARK___2 = 2123,\n\tIP17_11_8_MARK___3 = 2124,\n\tUSB0_PWEN_MARK___3 = 2125,\n\tSIM0_RST_C_MARK___3 = 2126,\n\tTS_SCK1_D_MARK___3 = 2127,\n\tSTP_ISCLK_1_D_MARK___3 = 2128,\n\tBPFCLK_B_MARK___3 = 2129,\n\tRIF3_CLK_B_MARK___3 = 2130,\n\tHSCK2_C_MARK___3 = 2131,\n\tIP16_15_12_MARK___3 = 2132,\n\tSSI_SCK78_MARK___3 = 2133,\n\tHRX2_B_MARK___3 = 2134,\n\tMSIOF1_SCK_C_MARK___3 = 2135,\n\tTS_SCK1_A_MARK___3 = 2136,\n\tSTP_ISCLK_1_A_MARK___3 = 2137,\n\tRIF1_CLK_A_MARK___3 = 2138,\n\tRIF3_CLK_A_MARK___3 = 2139,\n\tIP17_15_12_MARK___3 = 2140,\n\tUSB0_OVC_MARK___3 = 2141,\n\tSIM0_D_C_MARK___3 = 2142,\n\tTS_SDAT1_D_MARK___3 = 2143,\n\tSTP_ISD_1_D_MARK___3 = 2144,\n\tRIF3_SYNC_B_MARK___3 = 2145,\n\tHRX2_C_MARK___3 = 2146,\n\tIP16_19_16_MARK___3 = 2147,\n\tSSI_WS78_MARK___3 = 2148,\n\tHTX2_B_MARK___3 = 2149,\n\tMSIOF1_SYNC_C_MARK___3 = 2150,\n\tTS_SDAT1_A_MARK___3 = 2151,\n\tSTP_ISD_1_A_MARK___3 = 2152,\n\tRIF1_SYNC_A_MARK___3 = 2153,\n\tRIF3_SYNC_A_MARK___3 = 2154,\n\tIP17_19_16_MARK___3 = 2155,\n\tUSB1_PWEN_MARK___3 = 2156,\n\tSIM0_CLK_C_MARK___3 = 2157,\n\tSSI_SCK1_A_MARK___3 = 2158,\n\tTS_SCK0_E_MARK___3 = 2159,\n\tSTP_ISCLK_0_E_MARK___3 = 2160,\n\tFMCLK_B_MARK___3 = 2161,\n\tRIF2_CLK_B_MARK___3 = 2162,\n\tSPEEDIN_A_MARK___4 = 2163,\n\tHTX2_C_MARK___3 = 2164,\n\tIP16_23_20_MARK___3 = 2165,\n\tSSI_SDATA7_MARK___3 = 2166,\n\tHCTS2_N_B_MARK___3 = 2167,\n\tMSIOF1_RXD_C_MARK___3 = 2168,\n\tTS_SDEN1_A_MARK___3 = 2169,\n\tSTP_ISEN_1_A_MARK___3 = 2170,\n\tRIF1_D0_A_MARK___3 = 2171,\n\tRIF3_D0_A_MARK___3 = 2172,\n\tTCLK2_A_MARK___5 = 2173,\n\tIP17_23_20_MARK___3 = 2174,\n\tUSB1_OVC_MARK___3 = 2175,\n\tMSIOF1_SS2_C_MARK___3 = 2176,\n\tSSI_WS1_A_MARK___3 = 2177,\n\tTS_SDAT0_E_MARK___3 = 2178,\n\tSTP_ISD_0_E_MARK___3 = 2179,\n\tFMIN_B_MARK___3 = 2180,\n\tRIF2_SYNC_B_MARK___3 = 2181,\n\tREMOCON_B_MARK___3 = 2182,\n\tHCTS2_N_C_MARK___3 = 2183,\n\tIP16_27_24_MARK___3 = 2184,\n\tSSI_SDATA8_MARK___3 = 2185,\n\tHRTS2_N_B_MARK___3 = 2186,\n\tMSIOF1_TXD_C_MARK___3 = 2187,\n\tTS_SPSYNC1_A_MARK___3 = 2188,\n\tSTP_ISSYNC_1_A_MARK___3 = 2189,\n\tRIF1_D1_A_MARK___3 = 2190,\n\tRIF3_D1_A_MARK___3 = 2191,\n\tIP17_27_24_MARK___3 = 2192,\n\tUSB30_PWEN_MARK___3 = 2193,\n\tAUDIO_CLKOUT_B_MARK___3 = 2194,\n\tSSI_SCK2_B_MARK___3 = 2195,\n\tTS_SDEN1_D_MARK___3 = 2196,\n\tSTP_ISEN_1_D_MARK___3 = 2197,\n\tSTP_OPWM_0_E_MARK___3 = 2198,\n\tRIF3_D0_B_MARK___3 = 2199,\n\tTCLK2_B_MARK___5 = 2200,\n\tTPU0TO0_MARK___4 = 2201,\n\tBPFCLK_C_MARK___3 = 2202,\n\tHRTS2_N_C_MARK___3 = 2203,\n\tIP16_31_28_MARK___3 = 2204,\n\tSSI_SDATA9_A_MARK___3 = 2205,\n\tHSCK2_B_MARK___3 = 2206,\n\tMSIOF1_SS1_C_MARK___3 = 2207,\n\tHSCK1_A_MARK___4 = 2208,\n\tSSI_WS1_B_MARK___3 = 2209,\n\tSCK1_MARK___4 = 2210,\n\tSTP_IVCXO27_1_A_MARK___3 = 2211,\n\tSCK5_A_MARK___3 = 2212,\n\tIP17_31_28_MARK___3 = 2213,\n\tUSB30_OVC_MARK___3 = 2214,\n\tAUDIO_CLKOUT1_B_MARK___3 = 2215,\n\tSSI_WS2_B_MARK___3 = 2216,\n\tTS_SPSYNC1_D_MARK___3 = 2217,\n\tSTP_ISSYNC_1_D_MARK___3 = 2218,\n\tSTP_IVCXO27_0_E_MARK___3 = 2219,\n\tRIF3_D1_B_MARK___3 = 2220,\n\tFSO_TOE_N_MARK___4 = 2221,\n\tTPU0TO1_MARK___4 = 2222,\n\tSEL_MSIOF3_0_MARK___3 = 2223,\n\tSEL_MSIOF3_1_MARK___3 = 2224,\n\tSEL_MSIOF3_2_MARK___3 = 2225,\n\tSEL_MSIOF3_3_MARK___3 = 2226,\n\tSEL_MSIOF3_4_MARK___3 = 2227,\n\tSEL_TSIF1_0_MARK___3 = 2228,\n\tSEL_TSIF1_1_MARK___3 = 2229,\n\tSEL_TSIF1_2_MARK___3 = 2230,\n\tSEL_TSIF1_3_MARK___3 = 2231,\n\tI2C_SEL_5_0_MARK___3 = 2232,\n\tI2C_SEL_5_1_MARK___3 = 2233,\n\tI2C_SEL_3_0_MARK___3 = 2234,\n\tI2C_SEL_3_1_MARK___3 = 2235,\n\tSEL_TSIF0_0_MARK___3 = 2236,\n\tSEL_TSIF0_1_MARK___3 = 2237,\n\tSEL_TSIF0_2_MARK___3 = 2238,\n\tSEL_TSIF0_3_MARK___3 = 2239,\n\tSEL_TSIF0_4_MARK___3 = 2240,\n\tI2C_SEL_0_0_MARK___3 = 2241,\n\tI2C_SEL_0_1_MARK___3 = 2242,\n\tSEL_MSIOF2_0_MARK___3 = 2243,\n\tSEL_MSIOF2_1_MARK___3 = 2244,\n\tSEL_MSIOF2_2_MARK___3 = 2245,\n\tSEL_MSIOF2_3_MARK___3 = 2246,\n\tSEL_FM_0_MARK___3 = 2247,\n\tSEL_FM_1_MARK___3 = 2248,\n\tSEL_FM_2_MARK___3 = 2249,\n\tSEL_FM_3_MARK___3 = 2250,\n\tSEL_MSIOF1_0_MARK___3 = 2251,\n\tSEL_MSIOF1_1_MARK___3 = 2252,\n\tSEL_MSIOF1_2_MARK___3 = 2253,\n\tSEL_MSIOF1_3_MARK___3 = 2254,\n\tSEL_MSIOF1_4_MARK___3 = 2255,\n\tSEL_MSIOF1_5_MARK___3 = 2256,\n\tSEL_MSIOF1_6_MARK___3 = 2257,\n\tSEL_TIMER_TMU_0_MARK___2 = 2258,\n\tSEL_TIMER_TMU_1_MARK___2 = 2259,\n\tSEL_SCIF5_0_MARK___3 = 2260,\n\tSEL_SCIF5_1_MARK___3 = 2261,\n\tSEL_SSP1_1_0_MARK___3 = 2262,\n\tSEL_SSP1_1_1_MARK___3 = 2263,\n\tSEL_SSP1_1_2_MARK___3 = 2264,\n\tSEL_SSP1_1_3_MARK___3 = 2265,\n\tSEL_I2C6_0_MARK___3 = 2266,\n\tSEL_I2C6_1_MARK___3 = 2267,\n\tSEL_I2C6_2_MARK___3 = 2268,\n\tSEL_LBSC_0_MARK___3 = 2269,\n\tSEL_LBSC_1_MARK___3 = 2270,\n\tSEL_SSP1_0_0_MARK___3 = 2271,\n\tSEL_SSP1_0_1_MARK___3 = 2272,\n\tSEL_SSP1_0_2_MARK___3 = 2273,\n\tSEL_SSP1_0_3_MARK___3 = 2274,\n\tSEL_SSP1_0_4_MARK___3 = 2275,\n\tSEL_IEBUS_0_MARK___3 = 2276,\n\tSEL_IEBUS_1_MARK___3 = 2277,\n\tSEL_NDF_0_MARK___2 = 2278,\n\tSEL_NDF_1_MARK___2 = 2279,\n\tSEL_I2C2_0_MARK___3 = 2280,\n\tSEL_I2C2_1_MARK___3 = 2281,\n\tSEL_SSI2_0_MARK___3 = 2282,\n\tSEL_SSI2_1_MARK___3 = 2283,\n\tSEL_I2C1_0_MARK___3 = 2284,\n\tSEL_I2C1_1_MARK___3 = 2285,\n\tSEL_SSI1_0_MARK___3 = 2286,\n\tSEL_SSI1_1_MARK___3 = 2287,\n\tSEL_SSI9_0_MARK___3 = 2288,\n\tSEL_SSI9_1_MARK___3 = 2289,\n\tSEL_HSCIF4_0_MARK___3 = 2290,\n\tSEL_HSCIF4_1_MARK___3 = 2291,\n\tSEL_SPEED_PULSE_0_MARK___3 = 2292,\n\tSEL_SPEED_PULSE_1_MARK___3 = 2293,\n\tSEL_TIMER_TMU2_0_MARK___3 = 2294,\n\tSEL_TIMER_TMU2_1_MARK___3 = 2295,\n\tSEL_HSCIF3_0_MARK___3 = 2296,\n\tSEL_HSCIF3_1_MARK___3 = 2297,\n\tSEL_HSCIF3_2_MARK___3 = 2298,\n\tSEL_HSCIF3_3_MARK___3 = 2299,\n\tSEL_SIMCARD_0_MARK___3 = 2300,\n\tSEL_SIMCARD_1_MARK___3 = 2301,\n\tSEL_SIMCARD_2_MARK___3 = 2302,\n\tSEL_SIMCARD_3_MARK___3 = 2303,\n\tSEL_ADGB_0_MARK___3 = 2304,\n\tSEL_ADGB_1_MARK___3 = 2305,\n\tSEL_ADGC_0_MARK___3 = 2306,\n\tSEL_ADGC_1_MARK___3 = 2307,\n\tSEL_HSCIF1_0_MARK___3 = 2308,\n\tSEL_HSCIF1_1_MARK___3 = 2309,\n\tSEL_SDHI2_0_MARK___3 = 2310,\n\tSEL_SDHI2_1_MARK___3 = 2311,\n\tSEL_SCIF4_0_MARK___3 = 2312,\n\tSEL_SCIF4_1_MARK___3 = 2313,\n\tSEL_SCIF4_2_MARK___3 = 2314,\n\tSEL_HSCIF2_0_MARK___3 = 2315,\n\tSEL_HSCIF2_1_MARK___3 = 2316,\n\tSEL_HSCIF2_2_MARK___3 = 2317,\n\tSEL_SCIF3_0_MARK___3 = 2318,\n\tSEL_SCIF3_1_MARK___3 = 2319,\n\tSEL_ETHERAVB_0_MARK___3 = 2320,\n\tSEL_ETHERAVB_1_MARK___3 = 2321,\n\tSEL_SCIF2_0_MARK___3 = 2322,\n\tSEL_SCIF2_1_MARK___3 = 2323,\n\tSEL_DRIF3_0_MARK___3 = 2324,\n\tSEL_DRIF3_1_MARK___3 = 2325,\n\tSEL_SCIF1_0_MARK___4 = 2326,\n\tSEL_SCIF1_1_MARK___4 = 2327,\n\tSEL_DRIF2_0_MARK___3 = 2328,\n\tSEL_DRIF2_1_MARK___3 = 2329,\n\tSEL_SCIF_0_MARK___3 = 2330,\n\tSEL_SCIF_1_MARK___3 = 2331,\n\tSEL_DRIF1_0_MARK___3 = 2332,\n\tSEL_DRIF1_1_MARK___3 = 2333,\n\tSEL_DRIF1_2_MARK___3 = 2334,\n\tSEL_REMOCON_0_MARK___3 = 2335,\n\tSEL_REMOCON_1_MARK___3 = 2336,\n\tSEL_DRIF0_0_MARK___3 = 2337,\n\tSEL_DRIF0_1_MARK___3 = 2338,\n\tSEL_DRIF0_2_MARK___3 = 2339,\n\tSEL_RCAN0_0_MARK___3 = 2340,\n\tSEL_RCAN0_1_MARK___3 = 2341,\n\tSEL_CANFD0_0_MARK___4 = 2342,\n\tSEL_CANFD0_1_MARK___4 = 2343,\n\tSEL_PWM6_0_MARK___3 = 2344,\n\tSEL_PWM6_1_MARK___3 = 2345,\n\tSEL_ADGA_0_MARK___3 = 2346,\n\tSEL_ADGA_1_MARK___3 = 2347,\n\tSEL_ADGA_2_MARK___3 = 2348,\n\tSEL_ADGA_3_MARK___3 = 2349,\n\tSEL_PWM5_0_MARK___3 = 2350,\n\tSEL_PWM5_1_MARK___3 = 2351,\n\tSEL_PWM4_0_MARK___4 = 2352,\n\tSEL_PWM4_1_MARK___4 = 2353,\n\tSEL_PWM3_0_MARK___4 = 2354,\n\tSEL_PWM3_1_MARK___4 = 2355,\n\tSEL_PWM2_0_MARK___4 = 2356,\n\tSEL_PWM2_1_MARK___4 = 2357,\n\tSEL_PWM1_0_MARK___4 = 2358,\n\tSEL_PWM1_1_MARK___4 = 2359,\n\tSEL_VIN4_0_MARK___3 = 2360,\n\tSEL_VIN4_1_MARK___3 = 2361,\n\tQSPI0_SPCLK_MARK___5 = 2362,\n\tQSPI0_SSL_MARK___5 = 2363,\n\tQSPI0_MOSI_IO0_MARK___5 = 2364,\n\tQSPI0_MISO_IO1_MARK___5 = 2365,\n\tQSPI0_IO2_MARK___5 = 2366,\n\tQSPI0_IO3_MARK___5 = 2367,\n\tQSPI1_SPCLK_MARK___5 = 2368,\n\tQSPI1_SSL_MARK___5 = 2369,\n\tQSPI1_MOSI_IO0_MARK___5 = 2370,\n\tQSPI1_MISO_IO1_MARK___5 = 2371,\n\tQSPI1_IO2_MARK___5 = 2372,\n\tQSPI1_IO3_MARK___5 = 2373,\n\tRPC_INT_MARK___3 = 2374,\n\tRPC_WP_MARK___3 = 2375,\n\tRPC_RESET_MARK___3 = 2376,\n\tAVB_TX_CTL_MARK___4 = 2377,\n\tAVB_TXC_MARK___4 = 2378,\n\tAVB_TD0_MARK___4 = 2379,\n\tAVB_TD1_MARK___4 = 2380,\n\tAVB_TD2_MARK___4 = 2381,\n\tAVB_TD3_MARK___4 = 2382,\n\tAVB_RX_CTL_MARK___4 = 2383,\n\tAVB_RXC_MARK___4 = 2384,\n\tAVB_RD0_MARK___4 = 2385,\n\tAVB_RD1_MARK___4 = 2386,\n\tAVB_RD2_MARK___4 = 2387,\n\tAVB_RD3_MARK___4 = 2388,\n\tAVB_TXCREFCLK_MARK___4 = 2389,\n\tAVB_MDIO_MARK___4 = 2390,\n\tPRESETOUT_MARK___3 = 2391,\n\tDU_DOTCLKIN0_MARK___3 = 2392,\n\tDU_DOTCLKIN1_MARK___3 = 2393,\n\tDU_DOTCLKIN3_MARK___2 = 2394,\n\tTMS_MARK___3 = 2395,\n\tTDO_MARK___3 = 2396,\n\tASEBRK_MARK___3 = 2397,\n\tMLB_REF_MARK___3 = 2398,\n\tTDI_MARK___3 = 2399,\n\tTCK_MARK___3 = 2400,\n\tTRST_MARK___3 = 2401,\n\tEXTALR_MARK___3 = 2402,\n\tSCL0_MARK___5 = 2403,\n\tSDA0_MARK___5 = 2404,\n\tSCL3_MARK___5 = 2405,\n\tSDA3_MARK___5 = 2406,\n\tSCL5_MARK___5 = 2407,\n\tSDA5_MARK___5 = 2408,\n\tPINMUX_MARK_END___5 = 2409,\n};\n\nenum {\n\tPINMUX_RESERVED___6 = 0,\n\tPINMUX_DATA_BEGIN___6 = 1,\n\tGP_0_0_DATA___6 = 2,\n\tGP_0_1_DATA___6 = 3,\n\tGP_0_2_DATA___6 = 4,\n\tGP_0_3_DATA___6 = 5,\n\tGP_0_4_DATA___6 = 6,\n\tGP_0_5_DATA___6 = 7,\n\tGP_0_6_DATA___6 = 8,\n\tGP_0_7_DATA___6 = 9,\n\tGP_0_8_DATA___6 = 10,\n\tGP_0_9_DATA___6 = 11,\n\tGP_0_10_DATA___6 = 12,\n\tGP_0_11_DATA___6 = 13,\n\tGP_0_12_DATA___6 = 14,\n\tGP_0_13_DATA___6 = 15,\n\tGP_0_14_DATA___6 = 16,\n\tGP_0_15_DATA___6 = 17,\n\tGP_0_16_DATA___3 = 18,\n\tGP_0_17_DATA___3 = 19,\n\tGP_0_18_DATA___3 = 20,\n\tGP_0_19_DATA___2 = 21,\n\tGP_0_20_DATA___2 = 22,\n\tGP_1_0_DATA___6 = 23,\n\tGP_1_1_DATA___6 = 24,\n\tGP_1_2_DATA___6 = 25,\n\tGP_1_3_DATA___6 = 26,\n\tGP_1_4_DATA___6 = 27,\n\tGP_1_5_DATA___6 = 28,\n\tGP_1_6_DATA___6 = 29,\n\tGP_1_7_DATA___6 = 30,\n\tGP_1_8_DATA___6 = 31,\n\tGP_1_9_DATA___6 = 32,\n\tGP_1_10_DATA___6 = 33,\n\tGP_1_11_DATA___6 = 34,\n\tGP_1_12_DATA___6 = 35,\n\tGP_1_13_DATA___6 = 36,\n\tGP_1_14_DATA___6 = 37,\n\tGP_1_15_DATA___6 = 38,\n\tGP_1_16_DATA___6 = 39,\n\tGP_1_17_DATA___6 = 40,\n\tGP_1_18_DATA___6 = 41,\n\tGP_1_19_DATA___6 = 42,\n\tGP_1_20_DATA___6 = 43,\n\tGP_1_21_DATA___6 = 44,\n\tGP_1_22_DATA___6 = 45,\n\tGP_1_23_DATA___6 = 46,\n\tGP_1_24_DATA___6 = 47,\n\tGP_2_0_DATA___6 = 48,\n\tGP_2_1_DATA___6 = 49,\n\tGP_2_2_DATA___6 = 50,\n\tGP_2_3_DATA___6 = 51,\n\tGP_2_4_DATA___6 = 52,\n\tGP_2_5_DATA___6 = 53,\n\tGP_2_6_DATA___6 = 54,\n\tGP_2_7_DATA___6 = 55,\n\tGP_2_8_DATA___6 = 56,\n\tGP_2_9_DATA___6 = 57,\n\tGP_2_10_DATA___6 = 58,\n\tGP_2_11_DATA___6 = 59,\n\tGP_2_12_DATA___6 = 60,\n\tGP_2_13_DATA___6 = 61,\n\tGP_2_14_DATA___6 = 62,\n\tGP_2_15_DATA___3 = 63,\n\tGP_2_16_DATA___3 = 64,\n\tGP_3_0_DATA___6 = 65,\n\tGP_3_1_DATA___6 = 66,\n\tGP_3_2_DATA___6 = 67,\n\tGP_3_3_DATA___6 = 68,\n\tGP_3_4_DATA___6 = 69,\n\tGP_3_5_DATA___6 = 70,\n\tGP_3_6_DATA___6 = 71,\n\tGP_3_7_DATA___6 = 72,\n\tGP_3_8_DATA___6 = 73,\n\tGP_3_9_DATA___6 = 74,\n\tGP_3_10_DATA___6 = 75,\n\tGP_3_11_DATA___6 = 76,\n\tGP_3_12_DATA___6 = 77,\n\tGP_3_13_DATA___6 = 78,\n\tGP_3_14_DATA___6 = 79,\n\tGP_3_15_DATA___6 = 80,\n\tGP_3_16_DATA___3 = 81,\n\tGP_3_17_DATA___2 = 82,\n\tGP_3_18_DATA___2 = 83,\n\tPINMUX_DATA_END___6 = 84,\n\tPINMUX_FUNCTION_BEGIN___6 = 85,\n\tGP_0_0_FN___6 = 86,\n\tGP_0_1_FN___6 = 87,\n\tGP_0_2_FN___6 = 88,\n\tGP_0_3_FN___6 = 89,\n\tGP_0_4_FN___6 = 90,\n\tGP_0_5_FN___6 = 91,\n\tGP_0_6_FN___6 = 92,\n\tGP_0_7_FN___6 = 93,\n\tGP_0_8_FN___6 = 94,\n\tGP_0_9_FN___6 = 95,\n\tGP_0_10_FN___6 = 96,\n\tGP_0_11_FN___6 = 97,\n\tGP_0_12_FN___6 = 98,\n\tGP_0_13_FN___6 = 99,\n\tGP_0_14_FN___6 = 100,\n\tGP_0_15_FN___6 = 101,\n\tGP_0_16_FN___3 = 102,\n\tGP_0_17_FN___3 = 103,\n\tGP_0_18_FN___3 = 104,\n\tGP_0_19_FN___2 = 105,\n\tGP_0_20_FN___2 = 106,\n\tGP_1_0_FN___6 = 107,\n\tGP_1_1_FN___6 = 108,\n\tGP_1_2_FN___6 = 109,\n\tGP_1_3_FN___6 = 110,\n\tGP_1_4_FN___6 = 111,\n\tGP_1_5_FN___6 = 112,\n\tGP_1_6_FN___6 = 113,\n\tGP_1_7_FN___6 = 114,\n\tGP_1_8_FN___6 = 115,\n\tGP_1_9_FN___6 = 116,\n\tGP_1_10_FN___6 = 117,\n\tGP_1_11_FN___6 = 118,\n\tGP_1_12_FN___6 = 119,\n\tGP_1_13_FN___6 = 120,\n\tGP_1_14_FN___6 = 121,\n\tGP_1_15_FN___6 = 122,\n\tGP_1_16_FN___6 = 123,\n\tGP_1_17_FN___6 = 124,\n\tGP_1_18_FN___6 = 125,\n\tGP_1_19_FN___6 = 126,\n\tGP_1_20_FN___6 = 127,\n\tGP_1_21_FN___6 = 128,\n\tGP_1_22_FN___6 = 129,\n\tGP_1_23_FN___6 = 130,\n\tGP_1_24_FN___6 = 131,\n\tGP_2_0_FN___6 = 132,\n\tGP_2_1_FN___6 = 133,\n\tGP_2_2_FN___6 = 134,\n\tGP_2_3_FN___6 = 135,\n\tGP_2_4_FN___6 = 136,\n\tGP_2_5_FN___6 = 137,\n\tGP_2_6_FN___6 = 138,\n\tGP_2_7_FN___6 = 139,\n\tGP_2_8_FN___6 = 140,\n\tGP_2_9_FN___6 = 141,\n\tGP_2_10_FN___6 = 142,\n\tGP_2_11_FN___6 = 143,\n\tGP_2_12_FN___6 = 144,\n\tGP_2_13_FN___6 = 145,\n\tGP_2_14_FN___6 = 146,\n\tGP_2_15_FN___3 = 147,\n\tGP_2_16_FN___3 = 148,\n\tGP_3_0_FN___6 = 149,\n\tGP_3_1_FN___6 = 150,\n\tGP_3_2_FN___6 = 151,\n\tGP_3_3_FN___6 = 152,\n\tGP_3_4_FN___6 = 153,\n\tGP_3_5_FN___6 = 154,\n\tGP_3_6_FN___6 = 155,\n\tGP_3_7_FN___6 = 156,\n\tGP_3_8_FN___6 = 157,\n\tGP_3_9_FN___6 = 158,\n\tGP_3_10_FN___6 = 159,\n\tGP_3_11_FN___6 = 160,\n\tGP_3_12_FN___6 = 161,\n\tGP_3_13_FN___6 = 162,\n\tGP_3_14_FN___6 = 163,\n\tGP_3_15_FN___6 = 164,\n\tGP_3_16_FN___3 = 165,\n\tGP_3_17_FN___2 = 166,\n\tGP_3_18_FN___2 = 167,\n\tFN_SD_WP___2 = 168,\n\tFN_SD_CD___2 = 169,\n\tFN_MMC_SD_CMD___2 = 170,\n\tFN_MMC_D7___3 = 171,\n\tFN_MMC_DS___3 = 172,\n\tFN_MMC_D6___3 = 173,\n\tFN_MMC_D4___3 = 174,\n\tFN_TSN0_AVTP_CAPTURE_B = 175,\n\tFN_MMC_D5___3 = 176,\n\tFN_TSN0_AVTP_MATCH_B = 177,\n\tFN_MMC_SD_D3___2 = 178,\n\tFN_PCIE1_CLKREQ_N___2 = 179,\n\tFN_TSN0_AVTP_PPS = 180,\n\tFN_MMC_SD_D2___2 = 181,\n\tFN_PCIE0_CLKREQ_N___2 = 182,\n\tFN_TSN1_AVTP_CAPTURE_B = 183,\n\tFN_MMC_SD_D1___2 = 184,\n\tFN_QSPI0_IO3___3 = 185,\n\tFN_TSN1_AVTP_MATCH_B = 186,\n\tFN_MMC_SD_D0___2 = 187,\n\tFN_QSPI0_SSL___3 = 188,\n\tFN_TSN1_AVTP_PPS = 189,\n\tFN_MMC_SD_CLK___2 = 190,\n\tFN_QSPI0_MISO_IO1___3 = 191,\n\tFN_TSN0_MAGIC_B = 192,\n\tFN_GP1_11 = 193,\n\tFN_QSPI0_IO2___3 = 194,\n\tFN_TSN1_PHY_INT_B = 195,\n\tFN_GP1_10 = 196,\n\tFN_QSPI0_SPCLK___3 = 197,\n\tFN_TSN0_PHY_INT_B = 198,\n\tFN_GP1_09 = 199,\n\tFN_QSPI0_MOSI_IO0___3 = 200,\n\tFN_TSN2_PHY_INT_B = 201,\n\tFN_GP1_08 = 202,\n\tFN_QSPI1_SPCLK___3 = 203,\n\tFN_TSN0_LINK_B = 204,\n\tFN_QSPI1_MOSI_IO0___3 = 205,\n\tFN_TSN2_LINK_B = 206,\n\tFN_QSPI1_IO2___3 = 207,\n\tFN_TSN1_LINK_B = 208,\n\tFN_QSPI1_MISO_IO1___3 = 209,\n\tFN_TSN1_MDC_B = 210,\n\tFN_QSPI1_IO3___3 = 211,\n\tFN_TSN0_MDC_B = 212,\n\tFN_QSPI1_SSL___3 = 213,\n\tFN_TSN2_MDC_B = 214,\n\tFN_RPC_RESET_N___3 = 215,\n\tFN_TSN0_MDIO_B = 216,\n\tFN_RPC_WP_N___3 = 217,\n\tFN_TSN2_MDIO_B = 218,\n\tFN_RPC_INT_N___3 = 219,\n\tFN_TSN1_MDIO_B = 220,\n\tFN_IP0SR0_3_0___2 = 221,\n\tFN_SCIF_CLK___2 = 222,\n\tFN_IP1SR0_3_0___2 = 223,\n\tFN_SCK0___6 = 224,\n\tFN_HSCK1___2 = 225,\n\tFN_MSIOF1_SCK___3 = 226,\n\tFN_IP2SR0_3_0___2 = 227,\n\tFN_MSIOF0_SS2___6 = 228,\n\tFN_TSN2_LINK_A = 229,\n\tFN_IP0SR0_7_4___2 = 230,\n\tFN_HSCK0___5 = 231,\n\tFN_SCK3___5 = 232,\n\tFN_MSIOF3_SCK___3 = 233,\n\tFN_TSN0_AVTP_CAPTURE_A = 234,\n\tFN_IP1SR0_7_4___2 = 235,\n\tFN_RTS0_N___6 = 236,\n\tFN_HRTS1_N___2 = 237,\n\tFN_MSIOF3_SYNC___3 = 238,\n\tFN_TSN1_MDIO_A = 239,\n\tFN_IP2SR0_7_4___2 = 240,\n\tFN_IRQ0___5 = 241,\n\tFN_MSIOF1_SS1___3 = 242,\n\tFN_TSN0_MAGIC_A = 243,\n\tFN_IP0SR0_11_8___2 = 244,\n\tFN_HRX0___5 = 245,\n\tFN_RX3___2 = 246,\n\tFN_MSIOF3_RXD___3 = 247,\n\tFN_TSN0_AVTP_MATCH_A = 248,\n\tFN_IP1SR0_11_8___2 = 249,\n\tFN_CTS0_N___6 = 250,\n\tFN_HCTS1_N___2 = 251,\n\tFN_MSIOF1_SYNC___3 = 252,\n\tFN_TSN1_MDC_A = 253,\n\tFN_IP2SR0_11_8___2 = 254,\n\tFN_IRQ1___5 = 255,\n\tFN_MSIOF1_SS2___3 = 256,\n\tFN_TSN0_PHY_INT_A = 257,\n\tFN_IP0SR0_15_12___2 = 258,\n\tFN_HTX0___5 = 259,\n\tFN_TX3___2 = 260,\n\tFN_MSIOF3_TXD___3 = 261,\n\tFN_IP1SR0_15_12___2 = 262,\n\tFN_MSIOF0_SYNC___6 = 263,\n\tFN_HCTS3_N___5 = 264,\n\tFN_CTS1_N___5 = 265,\n\tFN_IRQ4___5 = 266,\n\tFN_TSN0_LINK_A = 267,\n\tFN_IP2SR0_15_12 = 268,\n\tFN_IRQ2___5 = 269,\n\tFN_TSN1_PHY_INT_A = 270,\n\tFN_IP0SR0_19_16___2 = 271,\n\tFN_HCTS0_N___5 = 272,\n\tFN_CTS3_N___5 = 273,\n\tFN_MSIOF3_SS1___3 = 274,\n\tFN_TSN0_MDC_A = 275,\n\tFN_IP1SR0_19_16___2 = 276,\n\tFN_MSIOF0_RXD___6 = 277,\n\tFN_HRX3___2 = 278,\n\tFN_RX1 = 279,\n\tFN_IP2SR0_19_16 = 280,\n\tFN_IRQ3___5 = 281,\n\tFN_TSN2_PHY_INT_A = 282,\n\tFN_IP0SR0_23_20___2 = 283,\n\tFN_HRTS0_N___5 = 284,\n\tFN_RTS3_N___5 = 285,\n\tFN_MSIOF3_SS2___3 = 286,\n\tFN_TSN0_MDIO_A = 287,\n\tFN_IP1SR0_23_20___2 = 288,\n\tFN_MSIOF0_TXD___6 = 289,\n\tFN_HTX3___2 = 290,\n\tFN_TX1 = 291,\n\tFN_IP0SR0_27_24___2 = 292,\n\tFN_RX0___6 = 293,\n\tFN_HRX1___2 = 294,\n\tFN_MSIOF1_RXD___3 = 295,\n\tFN_TSN1_AVTP_MATCH_A = 296,\n\tFN_IP1SR0_27_24___2 = 297,\n\tFN_MSIOF0_SCK___6 = 298,\n\tFN_HSCK3___5 = 299,\n\tFN_SCK1___5 = 300,\n\tFN_IP0SR0_31_28___2 = 301,\n\tFN_TX0___6 = 302,\n\tFN_HTX1___2 = 303,\n\tFN_MSIOF1_TXD___3 = 304,\n\tFN_TSN1_AVTP_CAPTURE_A = 305,\n\tFN_IP1SR0_31_28___2 = 306,\n\tFN_MSIOF0_SS1___6 = 307,\n\tFN_HRTS3_N___5 = 308,\n\tFN_RTS1_N___5 = 309,\n\tFN_IRQ5___6 = 310,\n\tFN_TSN1_LINK_A = 311,\n\tFN_IP0SR1_3_0___2 = 312,\n\tFN_GP1_00 = 313,\n\tFN_TCLK1 = 314,\n\tFN_HSCK2___3 = 315,\n\tFN_IP0SR1_7_4___2 = 316,\n\tFN_GP1_01 = 317,\n\tFN_TCLK4___2 = 318,\n\tFN_HRX2___3 = 319,\n\tFN_IP0SR1_11_8___2 = 320,\n\tFN_GP1_02 = 321,\n\tFN_HTX2___3 = 322,\n\tFN_MSIOF2_SS1___3 = 323,\n\tFN_TSN2_MDC_A = 324,\n\tFN_IP0SR1_15_12___2 = 325,\n\tFN_GP1_03 = 326,\n\tFN_TCLK2 = 327,\n\tFN_HCTS2_N___3 = 328,\n\tFN_MSIOF2_SS2___3 = 329,\n\tFN_CTS4_N___3 = 330,\n\tFN_TSN2_MDIO_A = 331,\n\tFN_IP0SR1_19_16___2 = 332,\n\tFN_GP1_04 = 333,\n\tFN_TCLK3___2 = 334,\n\tFN_HRTS2_N___3 = 335,\n\tFN_MSIOF2_SYNC___3 = 336,\n\tFN_RTS4_N___3 = 337,\n\tFN_IP0SR1_23_20___2 = 338,\n\tFN_GP1_05 = 339,\n\tFN_MSIOF2_SCK___3 = 340,\n\tFN_SCK4___3 = 341,\n\tFN_IP0SR1_27_24___2 = 342,\n\tFN_GP1_06 = 343,\n\tFN_MSIOF2_RXD___3 = 344,\n\tFN_RX4___3 = 345,\n\tFN_IP0SR1_31_28___2 = 346,\n\tFN_GP1_07 = 347,\n\tFN_MSIOF2_TXD___3 = 348,\n\tFN_TX4___3 = 349,\n\tFN_SEL_I2C5_0 = 350,\n\tFN_SEL_I2C5_3 = 351,\n\tFN_SEL_I2C4_0 = 352,\n\tFN_SEL_I2C4_3 = 353,\n\tFN_SEL_I2C3_0 = 354,\n\tFN_SEL_I2C3_3 = 355,\n\tFN_SEL_I2C2_0___4 = 356,\n\tFN_SEL_I2C2_3 = 357,\n\tFN_SEL_I2C1_0___4 = 358,\n\tFN_SEL_I2C1_3 = 359,\n\tFN_SEL_I2C0_0 = 360,\n\tFN_SEL_I2C0_3 = 361,\n\tPINMUX_FUNCTION_END___6 = 362,\n\tPINMUX_MARK_BEGIN___6 = 363,\n\tSD_WP_MARK___2 = 364,\n\tSD_CD_MARK___2 = 365,\n\tMMC_SD_CMD_MARK___2 = 366,\n\tMMC_D7_MARK___3 = 367,\n\tMMC_DS_MARK___3 = 368,\n\tMMC_D6_MARK___3 = 369,\n\tMMC_D4_MARK___3 = 370,\n\tTSN0_AVTP_CAPTURE_B_MARK = 371,\n\tMMC_D5_MARK___3 = 372,\n\tTSN0_AVTP_MATCH_B_MARK = 373,\n\tMMC_SD_D3_MARK___2 = 374,\n\tPCIE1_CLKREQ_N_MARK___2 = 375,\n\tTSN0_AVTP_PPS_MARK = 376,\n\tMMC_SD_D2_MARK___2 = 377,\n\tPCIE0_CLKREQ_N_MARK___2 = 378,\n\tTSN1_AVTP_CAPTURE_B_MARK = 379,\n\tMMC_SD_D1_MARK___2 = 380,\n\tQSPI0_IO3_MARK___6 = 381,\n\tTSN1_AVTP_MATCH_B_MARK = 382,\n\tMMC_SD_D0_MARK___2 = 383,\n\tQSPI0_SSL_MARK___6 = 384,\n\tTSN1_AVTP_PPS_MARK = 385,\n\tMMC_SD_CLK_MARK___2 = 386,\n\tQSPI0_MISO_IO1_MARK___6 = 387,\n\tTSN0_MAGIC_B_MARK = 388,\n\tGP1_11_MARK = 389,\n\tQSPI0_IO2_MARK___6 = 390,\n\tTSN1_PHY_INT_B_MARK = 391,\n\tGP1_10_MARK = 392,\n\tQSPI0_SPCLK_MARK___6 = 393,\n\tTSN0_PHY_INT_B_MARK = 394,\n\tGP1_09_MARK = 395,\n\tQSPI0_MOSI_IO0_MARK___6 = 396,\n\tTSN2_PHY_INT_B_MARK = 397,\n\tGP1_08_MARK = 398,\n\tQSPI1_SPCLK_MARK___6 = 399,\n\tTSN0_LINK_B_MARK = 400,\n\tQSPI1_MOSI_IO0_MARK___6 = 401,\n\tTSN2_LINK_B_MARK = 402,\n\tQSPI1_IO2_MARK___6 = 403,\n\tTSN1_LINK_B_MARK = 404,\n\tQSPI1_MISO_IO1_MARK___6 = 405,\n\tTSN1_MDC_B_MARK = 406,\n\tQSPI1_IO3_MARK___6 = 407,\n\tTSN0_MDC_B_MARK = 408,\n\tQSPI1_SSL_MARK___6 = 409,\n\tTSN2_MDC_B_MARK = 410,\n\tRPC_RESET_N_MARK___3 = 411,\n\tTSN0_MDIO_B_MARK = 412,\n\tRPC_WP_N_MARK___3 = 413,\n\tTSN2_MDIO_B_MARK = 414,\n\tRPC_INT_N_MARK___3 = 415,\n\tTSN1_MDIO_B_MARK = 416,\n\tIP0SR0_3_0_MARK___2 = 417,\n\tSCIF_CLK_MARK___2 = 418,\n\tIP1SR0_3_0_MARK___2 = 419,\n\tSCK0_MARK___6 = 420,\n\tHSCK1_MARK___2 = 421,\n\tMSIOF1_SCK_MARK___3 = 422,\n\tIP2SR0_3_0_MARK___2 = 423,\n\tMSIOF0_SS2_MARK___6 = 424,\n\tTSN2_LINK_A_MARK = 425,\n\tIP0SR0_7_4_MARK___2 = 426,\n\tHSCK0_MARK___5 = 427,\n\tSCK3_MARK___5 = 428,\n\tMSIOF3_SCK_MARK___3 = 429,\n\tTSN0_AVTP_CAPTURE_A_MARK = 430,\n\tIP1SR0_7_4_MARK___2 = 431,\n\tRTS0_N_MARK___6 = 432,\n\tHRTS1_N_MARK___2 = 433,\n\tMSIOF3_SYNC_MARK___3 = 434,\n\tTSN1_MDIO_A_MARK = 435,\n\tIP2SR0_7_4_MARK___2 = 436,\n\tIRQ0_MARK___5 = 437,\n\tMSIOF1_SS1_MARK___3 = 438,\n\tTSN0_MAGIC_A_MARK = 439,\n\tIP0SR0_11_8_MARK___2 = 440,\n\tHRX0_MARK___5 = 441,\n\tRX3_MARK___2 = 442,\n\tMSIOF3_RXD_MARK___3 = 443,\n\tTSN0_AVTP_MATCH_A_MARK = 444,\n\tIP1SR0_11_8_MARK___2 = 445,\n\tCTS0_N_MARK___6 = 446,\n\tHCTS1_N_MARK___2 = 447,\n\tMSIOF1_SYNC_MARK___3 = 448,\n\tTSN1_MDC_A_MARK = 449,\n\tIP2SR0_11_8_MARK___2 = 450,\n\tIRQ1_MARK___5 = 451,\n\tMSIOF1_SS2_MARK___3 = 452,\n\tTSN0_PHY_INT_A_MARK = 453,\n\tIP0SR0_15_12_MARK___2 = 454,\n\tHTX0_MARK___5 = 455,\n\tTX3_MARK___2 = 456,\n\tMSIOF3_TXD_MARK___3 = 457,\n\tIP1SR0_15_12_MARK___2 = 458,\n\tMSIOF0_SYNC_MARK___6 = 459,\n\tHCTS3_N_MARK___5 = 460,\n\tCTS1_N_MARK___5 = 461,\n\tIRQ4_MARK___5 = 462,\n\tTSN0_LINK_A_MARK = 463,\n\tIP2SR0_15_12_MARK = 464,\n\tIRQ2_MARK___5 = 465,\n\tTSN1_PHY_INT_A_MARK = 466,\n\tIP0SR0_19_16_MARK___2 = 467,\n\tHCTS0_N_MARK___5 = 468,\n\tCTS3_N_MARK___5 = 469,\n\tMSIOF3_SS1_MARK___3 = 470,\n\tTSN0_MDC_A_MARK = 471,\n\tIP1SR0_19_16_MARK___2 = 472,\n\tMSIOF0_RXD_MARK___6 = 473,\n\tHRX3_MARK___2 = 474,\n\tRX1_MARK = 475,\n\tIP2SR0_19_16_MARK = 476,\n\tIRQ3_MARK___5 = 477,\n\tTSN2_PHY_INT_A_MARK = 478,\n\tIP0SR0_23_20_MARK___2 = 479,\n\tHRTS0_N_MARK___5 = 480,\n\tRTS3_N_MARK___5 = 481,\n\tMSIOF3_SS2_MARK___3 = 482,\n\tTSN0_MDIO_A_MARK = 483,\n\tIP1SR0_23_20_MARK___2 = 484,\n\tMSIOF0_TXD_MARK___6 = 485,\n\tHTX3_MARK___2 = 486,\n\tTX1_MARK = 487,\n\tIP0SR0_27_24_MARK___2 = 488,\n\tRX0_MARK___6 = 489,\n\tHRX1_MARK___2 = 490,\n\tMSIOF1_RXD_MARK___3 = 491,\n\tTSN1_AVTP_MATCH_A_MARK = 492,\n\tIP1SR0_27_24_MARK___2 = 493,\n\tMSIOF0_SCK_MARK___6 = 494,\n\tHSCK3_MARK___5 = 495,\n\tSCK1_MARK___5 = 496,\n\tIP0SR0_31_28_MARK___2 = 497,\n\tTX0_MARK___6 = 498,\n\tHTX1_MARK___2 = 499,\n\tMSIOF1_TXD_MARK___3 = 500,\n\tTSN1_AVTP_CAPTURE_A_MARK = 501,\n\tIP1SR0_31_28_MARK___2 = 502,\n\tMSIOF0_SS1_MARK___6 = 503,\n\tHRTS3_N_MARK___5 = 504,\n\tRTS1_N_MARK___5 = 505,\n\tIRQ5_MARK___6 = 506,\n\tTSN1_LINK_A_MARK = 507,\n\tIP0SR1_3_0_MARK___2 = 508,\n\tGP1_00_MARK = 509,\n\tTCLK1_MARK = 510,\n\tHSCK2_MARK___3 = 511,\n\tIP0SR1_7_4_MARK___2 = 512,\n\tGP1_01_MARK = 513,\n\tTCLK4_MARK___2 = 514,\n\tHRX2_MARK___3 = 515,\n\tIP0SR1_11_8_MARK___2 = 516,\n\tGP1_02_MARK = 517,\n\tHTX2_MARK___3 = 518,\n\tMSIOF2_SS1_MARK___3 = 519,\n\tTSN2_MDC_A_MARK = 520,\n\tIP0SR1_15_12_MARK___2 = 521,\n\tGP1_03_MARK = 522,\n\tTCLK2_MARK = 523,\n\tHCTS2_N_MARK___3 = 524,\n\tMSIOF2_SS2_MARK___3 = 525,\n\tCTS4_N_MARK___3 = 526,\n\tTSN2_MDIO_A_MARK = 527,\n\tIP0SR1_19_16_MARK___2 = 528,\n\tGP1_04_MARK = 529,\n\tTCLK3_MARK___2 = 530,\n\tHRTS2_N_MARK___3 = 531,\n\tMSIOF2_SYNC_MARK___3 = 532,\n\tRTS4_N_MARK___3 = 533,\n\tIP0SR1_23_20_MARK___2 = 534,\n\tGP1_05_MARK = 535,\n\tMSIOF2_SCK_MARK___3 = 536,\n\tSCK4_MARK___3 = 537,\n\tIP0SR1_27_24_MARK___2 = 538,\n\tGP1_06_MARK = 539,\n\tMSIOF2_RXD_MARK___3 = 540,\n\tRX4_MARK___3 = 541,\n\tIP0SR1_31_28_MARK___2 = 542,\n\tGP1_07_MARK = 543,\n\tMSIOF2_TXD_MARK___3 = 544,\n\tTX4_MARK___3 = 545,\n\tSEL_I2C5_0_MARK = 546,\n\tSEL_I2C5_3_MARK = 547,\n\tSEL_I2C4_0_MARK = 548,\n\tSEL_I2C4_3_MARK = 549,\n\tSEL_I2C3_0_MARK = 550,\n\tSEL_I2C3_3_MARK = 551,\n\tSEL_I2C2_0_MARK___4 = 552,\n\tSEL_I2C2_3_MARK = 553,\n\tSEL_I2C1_0_MARK___4 = 554,\n\tSEL_I2C1_3_MARK = 555,\n\tSEL_I2C0_0_MARK = 556,\n\tSEL_I2C0_3_MARK = 557,\n\tSCL0_MARK___6 = 558,\n\tSDA0_MARK___6 = 559,\n\tSCL1_MARK___3 = 560,\n\tSDA1_MARK___3 = 561,\n\tSCL2_MARK___3 = 562,\n\tSDA2_MARK___3 = 563,\n\tSCL3_MARK___6 = 564,\n\tSDA3_MARK___6 = 565,\n\tSCL4_MARK___3 = 566,\n\tSDA4_MARK___3 = 567,\n\tSCL5_MARK___6 = 568,\n\tSDA5_MARK___6 = 569,\n\tPINMUX_MARK_END___6 = 570,\n};\n\nenum {\n\tPINMUX_RESERVED___7 = 0,\n\tPINMUX_DATA_BEGIN___7 = 1,\n\tGP_0_0_DATA___7 = 2,\n\tGP_0_1_DATA___7 = 3,\n\tGP_0_2_DATA___7 = 4,\n\tGP_0_3_DATA___7 = 5,\n\tGP_0_4_DATA___7 = 6,\n\tGP_0_5_DATA___7 = 7,\n\tGP_0_6_DATA___7 = 8,\n\tGP_0_7_DATA___7 = 9,\n\tGP_0_8_DATA___7 = 10,\n\tGP_1_0_DATA___7 = 11,\n\tGP_1_1_DATA___7 = 12,\n\tGP_1_2_DATA___7 = 13,\n\tGP_1_3_DATA___7 = 14,\n\tGP_1_4_DATA___7 = 15,\n\tGP_1_5_DATA___7 = 16,\n\tGP_1_6_DATA___7 = 17,\n\tGP_1_7_DATA___7 = 18,\n\tGP_1_8_DATA___7 = 19,\n\tGP_1_9_DATA___7 = 20,\n\tGP_1_10_DATA___7 = 21,\n\tGP_1_11_DATA___7 = 22,\n\tGP_1_12_DATA___7 = 23,\n\tGP_1_13_DATA___7 = 24,\n\tGP_1_14_DATA___7 = 25,\n\tGP_1_15_DATA___7 = 26,\n\tGP_1_16_DATA___7 = 27,\n\tGP_1_17_DATA___7 = 28,\n\tGP_1_18_DATA___7 = 29,\n\tGP_1_19_DATA___7 = 30,\n\tGP_1_20_DATA___7 = 31,\n\tGP_1_21_DATA___7 = 32,\n\tGP_1_22_DATA___7 = 33,\n\tGP_1_23_DATA___7 = 34,\n\tGP_1_24_DATA___7 = 35,\n\tGP_1_25_DATA___6 = 36,\n\tGP_1_26_DATA___6 = 37,\n\tGP_1_27_DATA___6 = 38,\n\tGP_1_28_DATA___5 = 39,\n\tGP_1_29_DATA = 40,\n\tGP_1_30_DATA = 41,\n\tGP_1_31_DATA = 42,\n\tGP_2_0_DATA___7 = 43,\n\tGP_2_1_DATA___7 = 44,\n\tGP_2_2_DATA___7 = 45,\n\tGP_2_3_DATA___7 = 46,\n\tGP_2_4_DATA___7 = 47,\n\tGP_2_5_DATA___7 = 48,\n\tGP_2_6_DATA___7 = 49,\n\tGP_2_7_DATA___7 = 50,\n\tGP_2_8_DATA___7 = 51,\n\tGP_2_9_DATA___7 = 52,\n\tGP_2_10_DATA___7 = 53,\n\tGP_2_11_DATA___7 = 54,\n\tGP_2_12_DATA___7 = 55,\n\tGP_2_13_DATA___7 = 56,\n\tGP_2_14_DATA___7 = 57,\n\tGP_2_15_DATA___4 = 58,\n\tGP_2_16_DATA___4 = 59,\n\tGP_2_17_DATA___3 = 60,\n\tGP_2_18_DATA___3 = 61,\n\tGP_2_19_DATA___3 = 62,\n\tGP_2_20_DATA___2 = 63,\n\tGP_2_21_DATA___2 = 64,\n\tGP_2_22_DATA___2 = 65,\n\tGP_2_23_DATA___2 = 66,\n\tGP_2_24_DATA___2 = 67,\n\tGP_2_25_DATA___2 = 68,\n\tGP_2_26_DATA___2 = 69,\n\tGP_2_27_DATA___2 = 70,\n\tGP_2_28_DATA___2 = 71,\n\tGP_2_29_DATA___2 = 72,\n\tGP_2_30_DATA = 73,\n\tGP_2_31_DATA = 74,\n\tGP_3_0_DATA___7 = 75,\n\tGP_3_1_DATA___7 = 76,\n\tGP_3_2_DATA___7 = 77,\n\tGP_3_3_DATA___7 = 78,\n\tGP_3_4_DATA___7 = 79,\n\tGP_3_5_DATA___7 = 80,\n\tGP_3_6_DATA___7 = 81,\n\tGP_3_7_DATA___7 = 82,\n\tGP_3_8_DATA___7 = 83,\n\tGP_3_9_DATA___7 = 84,\n\tGP_4_0_DATA___6 = 85,\n\tGP_4_1_DATA___6 = 86,\n\tGP_4_2_DATA___6 = 87,\n\tGP_4_3_DATA___6 = 88,\n\tGP_4_4_DATA___6 = 89,\n\tGP_4_5_DATA___6 = 90,\n\tGP_4_6_DATA___6 = 91,\n\tGP_4_7_DATA___6 = 92,\n\tGP_4_8_DATA___6 = 93,\n\tGP_4_9_DATA___6 = 94,\n\tGP_4_10_DATA___6 = 95,\n\tGP_4_11_DATA___6 = 96,\n\tGP_4_12_DATA___6 = 97,\n\tGP_4_13_DATA___6 = 98,\n\tGP_4_14_DATA___6 = 99,\n\tGP_4_15_DATA___6 = 100,\n\tGP_4_16_DATA___6 = 101,\n\tGP_4_17_DATA___6 = 102,\n\tGP_4_18_DATA___3 = 103,\n\tGP_4_19_DATA___3 = 104,\n\tGP_4_20_DATA___3 = 105,\n\tGP_4_21_DATA___3 = 106,\n\tGP_4_22_DATA___3 = 107,\n\tGP_4_23_DATA___3 = 108,\n\tGP_4_24_DATA___3 = 109,\n\tGP_4_25_DATA = 110,\n\tGP_4_26_DATA = 111,\n\tGP_4_27_DATA = 112,\n\tGP_4_28_DATA = 113,\n\tGP_4_29_DATA = 114,\n\tGP_4_30_DATA = 115,\n\tGP_4_31_DATA = 116,\n\tGP_5_0_DATA___6 = 117,\n\tGP_5_1_DATA___6 = 118,\n\tGP_5_2_DATA___6 = 119,\n\tGP_5_3_DATA___6 = 120,\n\tGP_5_4_DATA___6 = 121,\n\tGP_5_5_DATA___6 = 122,\n\tGP_5_6_DATA___6 = 123,\n\tGP_5_7_DATA___6 = 124,\n\tGP_5_8_DATA___6 = 125,\n\tGP_5_9_DATA___6 = 126,\n\tGP_5_10_DATA___6 = 127,\n\tGP_5_11_DATA___6 = 128,\n\tGP_5_12_DATA___6 = 129,\n\tGP_5_13_DATA___6 = 130,\n\tGP_5_14_DATA___6 = 131,\n\tGP_5_15_DATA___5 = 132,\n\tGP_5_16_DATA___5 = 133,\n\tGP_5_17_DATA___5 = 134,\n\tGP_5_18_DATA___5 = 135,\n\tGP_5_19_DATA___5 = 136,\n\tGP_5_20_DATA___5 = 137,\n\tGP_6_0_DATA___5 = 138,\n\tGP_6_1_DATA___5 = 139,\n\tGP_6_2_DATA___5 = 140,\n\tGP_6_3_DATA___5 = 141,\n\tGP_6_4_DATA___5 = 142,\n\tGP_6_5_DATA___5 = 143,\n\tGP_6_6_DATA___5 = 144,\n\tGP_6_7_DATA___5 = 145,\n\tGP_6_8_DATA___5 = 146,\n\tGP_6_9_DATA___5 = 147,\n\tGP_6_10_DATA___5 = 148,\n\tGP_6_11_DATA___5 = 149,\n\tGP_6_12_DATA___5 = 150,\n\tGP_6_13_DATA___5 = 151,\n\tPINMUX_DATA_END___7 = 152,\n\tPINMUX_FUNCTION_BEGIN___7 = 153,\n\tGP_0_0_FN___7 = 154,\n\tGP_0_1_FN___7 = 155,\n\tGP_0_2_FN___7 = 156,\n\tGP_0_3_FN___7 = 157,\n\tGP_0_4_FN___7 = 158,\n\tGP_0_5_FN___7 = 159,\n\tGP_0_6_FN___7 = 160,\n\tGP_0_7_FN___7 = 161,\n\tGP_0_8_FN___7 = 162,\n\tGP_1_0_FN___7 = 163,\n\tGP_1_1_FN___7 = 164,\n\tGP_1_2_FN___7 = 165,\n\tGP_1_3_FN___7 = 166,\n\tGP_1_4_FN___7 = 167,\n\tGP_1_5_FN___7 = 168,\n\tGP_1_6_FN___7 = 169,\n\tGP_1_7_FN___7 = 170,\n\tGP_1_8_FN___7 = 171,\n\tGP_1_9_FN___7 = 172,\n\tGP_1_10_FN___7 = 173,\n\tGP_1_11_FN___7 = 174,\n\tGP_1_12_FN___7 = 175,\n\tGP_1_13_FN___7 = 176,\n\tGP_1_14_FN___7 = 177,\n\tGP_1_15_FN___7 = 178,\n\tGP_1_16_FN___7 = 179,\n\tGP_1_17_FN___7 = 180,\n\tGP_1_18_FN___7 = 181,\n\tGP_1_19_FN___7 = 182,\n\tGP_1_20_FN___7 = 183,\n\tGP_1_21_FN___7 = 184,\n\tGP_1_22_FN___7 = 185,\n\tGP_1_23_FN___7 = 186,\n\tGP_1_24_FN___7 = 187,\n\tGP_1_25_FN___6 = 188,\n\tGP_1_26_FN___6 = 189,\n\tGP_1_27_FN___6 = 190,\n\tGP_1_28_FN___5 = 191,\n\tGP_1_29_FN = 192,\n\tGP_1_30_FN = 193,\n\tGP_1_31_FN = 194,\n\tGP_2_0_FN___7 = 195,\n\tGP_2_1_FN___7 = 196,\n\tGP_2_2_FN___7 = 197,\n\tGP_2_3_FN___7 = 198,\n\tGP_2_4_FN___7 = 199,\n\tGP_2_5_FN___7 = 200,\n\tGP_2_6_FN___7 = 201,\n\tGP_2_7_FN___7 = 202,\n\tGP_2_8_FN___7 = 203,\n\tGP_2_9_FN___7 = 204,\n\tGP_2_10_FN___7 = 205,\n\tGP_2_11_FN___7 = 206,\n\tGP_2_12_FN___7 = 207,\n\tGP_2_13_FN___7 = 208,\n\tGP_2_14_FN___7 = 209,\n\tGP_2_15_FN___4 = 210,\n\tGP_2_16_FN___4 = 211,\n\tGP_2_17_FN___3 = 212,\n\tGP_2_18_FN___3 = 213,\n\tGP_2_19_FN___3 = 214,\n\tGP_2_20_FN___2 = 215,\n\tGP_2_21_FN___2 = 216,\n\tGP_2_22_FN___2 = 217,\n\tGP_2_23_FN___2 = 218,\n\tGP_2_24_FN___2 = 219,\n\tGP_2_25_FN___2 = 220,\n\tGP_2_26_FN___2 = 221,\n\tGP_2_27_FN___2 = 222,\n\tGP_2_28_FN___2 = 223,\n\tGP_2_29_FN___2 = 224,\n\tGP_2_30_FN = 225,\n\tGP_2_31_FN = 226,\n\tGP_3_0_FN___7 = 227,\n\tGP_3_1_FN___7 = 228,\n\tGP_3_2_FN___7 = 229,\n\tGP_3_3_FN___7 = 230,\n\tGP_3_4_FN___7 = 231,\n\tGP_3_5_FN___7 = 232,\n\tGP_3_6_FN___7 = 233,\n\tGP_3_7_FN___7 = 234,\n\tGP_3_8_FN___7 = 235,\n\tGP_3_9_FN___7 = 236,\n\tGP_4_0_FN___6 = 237,\n\tGP_4_1_FN___6 = 238,\n\tGP_4_2_FN___6 = 239,\n\tGP_4_3_FN___6 = 240,\n\tGP_4_4_FN___6 = 241,\n\tGP_4_5_FN___6 = 242,\n\tGP_4_6_FN___6 = 243,\n\tGP_4_7_FN___6 = 244,\n\tGP_4_8_FN___6 = 245,\n\tGP_4_9_FN___6 = 246,\n\tGP_4_10_FN___6 = 247,\n\tGP_4_11_FN___6 = 248,\n\tGP_4_12_FN___6 = 249,\n\tGP_4_13_FN___6 = 250,\n\tGP_4_14_FN___6 = 251,\n\tGP_4_15_FN___6 = 252,\n\tGP_4_16_FN___6 = 253,\n\tGP_4_17_FN___6 = 254,\n\tGP_4_18_FN___3 = 255,\n\tGP_4_19_FN___3 = 256,\n\tGP_4_20_FN___3 = 257,\n\tGP_4_21_FN___3 = 258,\n\tGP_4_22_FN___3 = 259,\n\tGP_4_23_FN___3 = 260,\n\tGP_4_24_FN___3 = 261,\n\tGP_4_25_FN = 262,\n\tGP_4_26_FN = 263,\n\tGP_4_27_FN = 264,\n\tGP_4_28_FN = 265,\n\tGP_4_29_FN = 266,\n\tGP_4_30_FN = 267,\n\tGP_4_31_FN = 268,\n\tGP_5_0_FN___6 = 269,\n\tGP_5_1_FN___6 = 270,\n\tGP_5_2_FN___6 = 271,\n\tGP_5_3_FN___6 = 272,\n\tGP_5_4_FN___6 = 273,\n\tGP_5_5_FN___6 = 274,\n\tGP_5_6_FN___6 = 275,\n\tGP_5_7_FN___6 = 276,\n\tGP_5_8_FN___6 = 277,\n\tGP_5_9_FN___6 = 278,\n\tGP_5_10_FN___6 = 279,\n\tGP_5_11_FN___6 = 280,\n\tGP_5_12_FN___6 = 281,\n\tGP_5_13_FN___6 = 282,\n\tGP_5_14_FN___6 = 283,\n\tGP_5_15_FN___5 = 284,\n\tGP_5_16_FN___5 = 285,\n\tGP_5_17_FN___5 = 286,\n\tGP_5_18_FN___5 = 287,\n\tGP_5_19_FN___5 = 288,\n\tGP_5_20_FN___5 = 289,\n\tGP_6_0_FN___5 = 290,\n\tGP_6_1_FN___5 = 291,\n\tGP_6_2_FN___5 = 292,\n\tGP_6_3_FN___5 = 293,\n\tGP_6_4_FN___5 = 294,\n\tGP_6_5_FN___5 = 295,\n\tGP_6_6_FN___5 = 296,\n\tGP_6_7_FN___5 = 297,\n\tGP_6_8_FN___5 = 298,\n\tGP_6_9_FN___5 = 299,\n\tGP_6_10_FN___5 = 300,\n\tGP_6_11_FN___5 = 301,\n\tGP_6_12_FN___5 = 302,\n\tGP_6_13_FN___5 = 303,\n\tFN_TX2 = 304,\n\tFN_RX2 = 305,\n\tFN_AVB0_LINK___2 = 306,\n\tFN_AVB0_PHY_INT___2 = 307,\n\tFN_AVB0_MAGIC___2 = 308,\n\tFN_AVB0_MDC___2 = 309,\n\tFN_AVB0_MDIO___2 = 310,\n\tFN_MSIOF0_RXD___7 = 311,\n\tFN_AVB0_TXCREFCLK___2 = 312,\n\tFN_MSIOF0_TXD___7 = 313,\n\tFN_AVB0_TD3___2 = 314,\n\tFN_MSIOF0_SYNC___7 = 315,\n\tFN_AVB0_TD2___2 = 316,\n\tFN_RPC_INT_N___4 = 317,\n\tFN_MSIOF0_SCK___7 = 318,\n\tFN_AVB0_TD1___2 = 319,\n\tFN_RPC_RESET_N___4 = 320,\n\tFN_AVB0_TD0___2 = 321,\n\tFN_QSPI1_SSL___4 = 322,\n\tFN_AVB0_TXC___2 = 323,\n\tFN_QSPI1_IO3___4 = 324,\n\tFN_SDA0___3 = 325,\n\tFN_AVB0_TX_CTL___2 = 326,\n\tFN_QSPI1_IO2___4 = 327,\n\tFN_SCL0___3 = 328,\n\tFN_AVB0_RD3___2 = 329,\n\tFN_QSPI1_MISO_IO1___4 = 330,\n\tFN_AVB0_RD2___2 = 331,\n\tFN_QSPI1_MOSI_IO0___4 = 332,\n\tFN_AVB0_RD1___2 = 333,\n\tFN_QSPI1_SPCLK___4 = 334,\n\tFN_VI4_DATA4 = 335,\n\tFN_AVB0_RD0___2 = 336,\n\tFN_QSPI0_SSL___4 = 337,\n\tFN_AVB0_RXC___2 = 338,\n\tFN_QSPI0_IO3___4 = 339,\n\tFN_AVB0_RX_CTL___2 = 340,\n\tFN_QSPI0_IO2___4 = 341,\n\tFN_QSPI0_MISO_IO1___4 = 342,\n\tFN_USB0_OVC___4 = 343,\n\tFN_QSPI0_MOSI_IO0___4 = 344,\n\tFN_USB0_PWEN___4 = 345,\n\tFN_VI4_CLK___4 = 346,\n\tFN_QSPI0_SPCLK___4 = 347,\n\tFN_IP0_3_0___5 = 348,\n\tFN_IRQ0_A___2 = 349,\n\tFN_MSIOF2_SYNC_B___4 = 350,\n\tFN_IP1_3_0___5 = 351,\n\tFN_DU_DB1___5 = 352,\n\tFN_LCDOUT1___4 = 353,\n\tFN_MSIOF3_RXD_B___4 = 354,\n\tFN_IP2_3_0___5 = 355,\n\tFN_DU_DG1___5 = 356,\n\tFN_LCDOUT9___4 = 357,\n\tFN_MSIOF3_SYNC_B___4 = 358,\n\tFN_IP3_3_0___5 = 359,\n\tFN_DU_DR1___5 = 360,\n\tFN_LCDOUT17___4 = 361,\n\tFN_TX4_B___4 = 362,\n\tFN_IP0_7_4___5 = 363,\n\tFN_MSIOF2_SCK___4 = 364,\n\tFN_IP1_7_4___5 = 365,\n\tFN_DU_DB2___5 = 366,\n\tFN_LCDOUT2___4 = 367,\n\tFN_IRQ0_B___2 = 368,\n\tFN_IP2_7_4___5 = 369,\n\tFN_DU_DG2___5 = 370,\n\tFN_LCDOUT10___4 = 371,\n\tFN_IP3_7_4___5 = 372,\n\tFN_DU_DR2___5 = 373,\n\tFN_LCDOUT18___4 = 374,\n\tFN_PWM0_B___2 = 375,\n\tFN_IP0_11_8___5 = 376,\n\tFN_MSIOF2_TXD___4 = 377,\n\tFN_SCL3_A = 378,\n\tFN_IP1_11_8___5 = 379,\n\tFN_DU_DB3___5 = 380,\n\tFN_LCDOUT3___4 = 381,\n\tFN_SCK5_B___4 = 382,\n\tFN_IP2_11_8___5 = 383,\n\tFN_DU_DG3___5 = 384,\n\tFN_LCDOUT11___4 = 385,\n\tFN_IRQ1_A___2 = 386,\n\tFN_IP3_11_8___5 = 387,\n\tFN_DU_DR3___5 = 388,\n\tFN_LCDOUT19___4 = 389,\n\tFN_PWM1_B___6 = 390,\n\tFN_IP0_15_12___5 = 391,\n\tFN_MSIOF2_RXD___4 = 392,\n\tFN_SDA3_A = 393,\n\tFN_IP1_15_12___5 = 394,\n\tFN_DU_DB4___5 = 395,\n\tFN_LCDOUT4___4 = 396,\n\tFN_RX5_B___4 = 397,\n\tFN_IP2_15_12___5 = 398,\n\tFN_DU_DG4___5 = 399,\n\tFN_LCDOUT12___4 = 400,\n\tFN_HSCK3_B___2 = 401,\n\tFN_IP3_15_12___5 = 402,\n\tFN_DU_DR4___5 = 403,\n\tFN_LCDOUT20___4 = 404,\n\tFN_TCLK2_B___6 = 405,\n\tFN_IP0_19_16___5 = 406,\n\tFN_MLB_CLK___4 = 407,\n\tFN_MSIOF2_SYNC_A___4 = 408,\n\tFN_SCK5_A___4 = 409,\n\tFN_IP1_19_16___5 = 410,\n\tFN_DU_DB5___5 = 411,\n\tFN_LCDOUT5___4 = 412,\n\tFN_TX5_B___4 = 413,\n\tFN_IP2_19_16___5 = 414,\n\tFN_DU_DG5___5 = 415,\n\tFN_LCDOUT13___4 = 416,\n\tFN_HTX3_B___5 = 417,\n\tFN_IP3_19_16___5 = 418,\n\tFN_DU_DR5___5 = 419,\n\tFN_LCDOUT21___4 = 420,\n\tFN_NMI = 421,\n\tFN_IP0_23_20___5 = 422,\n\tFN_MLB_DAT___4 = 423,\n\tFN_MSIOF2_SS1___4 = 424,\n\tFN_RX5_A___4 = 425,\n\tFN_SCL3_B = 426,\n\tFN_IP1_23_20___5 = 427,\n\tFN_DU_DB6___5 = 428,\n\tFN_LCDOUT6___4 = 429,\n\tFN_MSIOF3_SS1_B___4 = 430,\n\tFN_IP2_23_20___5 = 431,\n\tFN_DU_DG6___5 = 432,\n\tFN_LCDOUT14___4 = 433,\n\tFN_HRX3_B___5 = 434,\n\tFN_IP3_23_20___5 = 435,\n\tFN_DU_DR6___5 = 436,\n\tFN_LCDOUT22___4 = 437,\n\tFN_PWM2_B___5 = 438,\n\tFN_IP0_27_24___5 = 439,\n\tFN_MLB_SIG___4 = 440,\n\tFN_MSIOF2_SS2___4 = 441,\n\tFN_TX5_A___4 = 442,\n\tFN_SDA3_B = 443,\n\tFN_IP1_27_24___5 = 444,\n\tFN_DU_DB7___5 = 445,\n\tFN_LCDOUT7___4 = 446,\n\tFN_MSIOF3_SS2_B___4 = 447,\n\tFN_IP2_27_24___5 = 448,\n\tFN_DU_DG7___5 = 449,\n\tFN_LCDOUT15___4 = 450,\n\tFN_SCK4_B___4 = 451,\n\tFN_IP3_27_24___5 = 452,\n\tFN_DU_DR7___5 = 453,\n\tFN_LCDOUT23___4 = 454,\n\tFN_TCLK1_B___6 = 455,\n\tFN_IP0_31_28___5 = 456,\n\tFN_DU_DB0___5 = 457,\n\tFN_LCDOUT0___4 = 458,\n\tFN_MSIOF3_TXD_B___4 = 459,\n\tFN_IP1_31_28___5 = 460,\n\tFN_DU_DG0___5 = 461,\n\tFN_LCDOUT8___4 = 462,\n\tFN_MSIOF3_SCK_B___4 = 463,\n\tFN_IP2_31_28___5 = 464,\n\tFN_DU_DR0___5 = 465,\n\tFN_LCDOUT16___4 = 466,\n\tFN_RX4_B___4 = 467,\n\tFN_IP3_31_28___5 = 468,\n\tFN_DU_DOTCLKOUT0___4 = 469,\n\tFN_QCLK___4 = 470,\n\tFN_IP4_3_0___5 = 471,\n\tFN_DU_HSYNC = 472,\n\tFN_QSTH_QHS___4 = 473,\n\tFN_IRQ3_A___2 = 474,\n\tFN_IP5_3_0___5 = 475,\n\tFN_VI4_DATA1 = 476,\n\tFN_PWM1_A___6 = 477,\n\tFN_IP6_3_0___5 = 478,\n\tFN_VI4_DATA10___4 = 479,\n\tFN_RX4_A___4 = 480,\n\tFN_IP7_3_0___5 = 481,\n\tFN_VI4_DATA18___4 = 482,\n\tFN_HSCK3_A___2 = 483,\n\tFN_IP4_7_4___5 = 484,\n\tFN_DU_VSYNC = 485,\n\tFN_QSTVA_QVS___4 = 486,\n\tFN_IRQ4_A___2 = 487,\n\tFN_IP5_7_4___5 = 488,\n\tFN_VI4_DATA2 = 489,\n\tFN_PWM2_A___5 = 490,\n\tFN_IP6_7_4___5 = 491,\n\tFN_VI4_DATA11___4 = 492,\n\tFN_TX4_A___4 = 493,\n\tFN_IP7_7_4___5 = 494,\n\tFN_VI4_DATA19___4 = 495,\n\tFN_SSI_WS4_B = 496,\n\tFN_NFDATA15 = 497,\n\tFN_IP4_11_8___5 = 498,\n\tFN_DU_DISP___5 = 499,\n\tFN_QSTVB_QVE___4 = 500,\n\tFN_PWM3_B___6 = 501,\n\tFN_IP5_11_8___5 = 502,\n\tFN_VI4_DATA3 = 503,\n\tFN_PWM3_A___6 = 504,\n\tFN_IP6_11_8___5 = 505,\n\tFN_VI4_DATA12___4 = 506,\n\tFN_TCLK1_A___6 = 507,\n\tFN_IP7_11_8___5 = 508,\n\tFN_VI4_DATA20___4 = 509,\n\tFN_MSIOF3_SYNC_A___4 = 510,\n\tFN_NFDATA14 = 511,\n\tFN_IP4_15_12___5 = 512,\n\tFN_DU_DISP_CDE = 513,\n\tFN_QCPV_QDE___4 = 514,\n\tFN_IRQ2_B___2 = 515,\n\tFN_DU_DOTCLKIN1 = 516,\n\tFN_IP5_15_12___5 = 517,\n\tFN_VI4_DATA5 = 518,\n\tFN_SCK4_A___4 = 519,\n\tFN_IP6_15_12___5 = 520,\n\tFN_VI4_DATA13___4 = 521,\n\tFN_MSIOF3_SS1_A___4 = 522,\n\tFN_HCTS3_N___6 = 523,\n\tFN_IP7_15_12___2 = 524,\n\tFN_VI4_DATA21___4 = 525,\n\tFN_MSIOF3_TXD_A___4 = 526,\n\tFN_NFDATA13___4 = 527,\n\tFN_IP4_19_16___5 = 528,\n\tFN_DU_CDE___5 = 529,\n\tFN_QSTB_QHE___4 = 530,\n\tFN_SCK3_B___2 = 531,\n\tFN_IP5_19_16___5 = 532,\n\tFN_VI4_DATA6 = 533,\n\tFN_IRQ2_A___2 = 534,\n\tFN_IP6_19_16___5 = 535,\n\tFN_VI4_DATA14___4 = 536,\n\tFN_SSI_SCK4_B = 537,\n\tFN_HRTS3_N___6 = 538,\n\tFN_IP7_19_16___5 = 539,\n\tFN_VI4_DATA22___4 = 540,\n\tFN_MSIOF3_RXD_A___4 = 541,\n\tFN_NFDATA12___4 = 542,\n\tFN_IP4_23_20___5 = 543,\n\tFN_QPOLA___4 = 544,\n\tFN_RX3_B___5 = 545,\n\tFN_IP5_23_20___5 = 546,\n\tFN_VI4_DATA7 = 547,\n\tFN_TCLK2_A___6 = 548,\n\tFN_IP6_23_20___5 = 549,\n\tFN_VI4_DATA15___4 = 550,\n\tFN_SSI_SDATA4_B = 551,\n\tFN_IP7_23_20___5 = 552,\n\tFN_VI4_DATA23___4 = 553,\n\tFN_MSIOF3_SCK_A___4 = 554,\n\tFN_NFDATA11___4 = 555,\n\tFN_IP4_27_24___5 = 556,\n\tFN_QPOLB___4 = 557,\n\tFN_TX3_B___5 = 558,\n\tFN_IP5_27_24___5 = 559,\n\tFN_VI4_DATA8___4 = 560,\n\tFN_IP6_27_24___5 = 561,\n\tFN_VI4_DATA16___4 = 562,\n\tFN_HRX3_A___5 = 563,\n\tFN_IP7_27_24___5 = 564,\n\tFN_VI4_VSYNC_N___4 = 565,\n\tFN_SCK1_B___2 = 566,\n\tFN_NFDATA10___4 = 567,\n\tFN_IP4_31_28___5 = 568,\n\tFN_VI4_DATA0 = 569,\n\tFN_PWM0_A___2 = 570,\n\tFN_IP5_31_28___5 = 571,\n\tFN_VI4_DATA9___4 = 572,\n\tFN_MSIOF3_SS2_A___4 = 573,\n\tFN_IRQ1_B___2 = 574,\n\tFN_IP6_31_28___5 = 575,\n\tFN_VI4_DATA17___4 = 576,\n\tFN_HTX3_A___5 = 577,\n\tFN_IP7_31_28___5 = 578,\n\tFN_VI4_HSYNC_N___4 = 579,\n\tFN_RX1_B___6 = 580,\n\tFN_NFDATA9___4 = 581,\n\tFN_IP8_3_0___5 = 582,\n\tFN_VI4_FIELD___4 = 583,\n\tFN_AUDIO_CLKB = 584,\n\tFN_IRQ5_A = 585,\n\tFN_SCIF_CLK___3 = 586,\n\tFN_NFDATA8___4 = 587,\n\tFN_IP9_3_0___5 = 588,\n\tFN_NFDATA0___4 = 589,\n\tFN_MMC_D0___2 = 590,\n\tFN_IP10_3_0___5 = 591,\n\tFN_AUDIO_CLKA = 592,\n\tFN_DVC_MUTE_B = 593,\n\tFN_IP11_3_0___4 = 594,\n\tFN_SDA1___3 = 595,\n\tFN_RTS1_N___6 = 596,\n\tFN_IP8_7_4___5 = 597,\n\tFN_VI4_CLKENB___4 = 598,\n\tFN_TX1_B___6 = 599,\n\tFN_NFWP_N = 600,\n\tFN_DVC_MUTE_A = 601,\n\tFN_IP9_7_4___5 = 602,\n\tFN_NFDATA1___4 = 603,\n\tFN_MMC_D1___2 = 604,\n\tFN_IP10_7_4___5 = 605,\n\tFN_SSI_SCK34 = 606,\n\tFN_FSO_CFE_0_N_A = 607,\n\tFN_IP11_7_4___4 = 608,\n\tFN_MSIOF1_SCK___4 = 609,\n\tFN_AVB0_AVTP_PPS_B = 610,\n\tFN_IP8_11_8___5 = 611,\n\tFN_NFALE___4 = 612,\n\tFN_SCL2_B___4 = 613,\n\tFN_IRQ3_B___2 = 614,\n\tFN_PWM0_C = 615,\n\tFN_IP9_11_8___5 = 616,\n\tFN_NFDATA2___4 = 617,\n\tFN_MMC_D2___2 = 618,\n\tFN_IP10_11_8___5 = 619,\n\tFN_SSI_SDATA3___4 = 620,\n\tFN_FSO_CFE_1_N_A = 621,\n\tFN_IP11_11_8___4 = 622,\n\tFN_MSIOF1_TXD___4 = 623,\n\tFN_AVB0_AVTP_CAPTURE_B = 624,\n\tFN_IP8_15_12___5 = 625,\n\tFN_NFCLE___4 = 626,\n\tFN_SDA2_B___4 = 627,\n\tFN_SCK3_A___2 = 628,\n\tFN_PWM1_C = 629,\n\tFN_IP9_15_12___5 = 630,\n\tFN_NFDATA3___4 = 631,\n\tFN_MMC_D3___2 = 632,\n\tFN_IP10_15_12___5 = 633,\n\tFN_SSI_WS34 = 634,\n\tFN_FSO_TOE_N_A = 635,\n\tFN_IP11_15_12___4 = 636,\n\tFN_MSIOF1_RXD___4 = 637,\n\tFN_AVB0_AVTP_MATCH_B = 638,\n\tFN_IP8_19_16___5 = 639,\n\tFN_NFCE_N = 640,\n\tFN_RX3_A___5 = 641,\n\tFN_PWM2_C = 642,\n\tFN_IP9_19_16___5 = 643,\n\tFN_NFDATA4___4 = 644,\n\tFN_MMC_D4___4 = 645,\n\tFN_IP10_19_16___5 = 646,\n\tFN_SSI_SCK4_A = 647,\n\tFN_HSCK0___6 = 648,\n\tFN_AUDIO_CLKOUT___2 = 649,\n\tFN_CAN0_RX_B___4 = 650,\n\tFN_IRQ4_B___2 = 651,\n\tFN_IP11_19_16___4 = 652,\n\tFN_SCK0_A = 653,\n\tFN_MSIOF1_SYNC___4 = 654,\n\tFN_FSO_CFE_0_N_B = 655,\n\tFN_IP8_23_20___5 = 656,\n\tFN_NFRB_N = 657,\n\tFN_TX3_A___5 = 658,\n\tFN_PWM3_C = 659,\n\tFN_IP9_23_20___5 = 660,\n\tFN_NFDATA5___4 = 661,\n\tFN_MMC_D5___4 = 662,\n\tFN_IP10_23_20___4 = 663,\n\tFN_SSI_SDATA4_A = 664,\n\tFN_HTX0___6 = 665,\n\tFN_SCL2_A___4 = 666,\n\tFN_CAN1_RX_B = 667,\n\tFN_IP11_23_20___4 = 668,\n\tFN_RX0_A = 669,\n\tFN_MSIOF0_SS1___7 = 670,\n\tFN_FSO_CFE_1_N_B = 671,\n\tFN_IP8_27_24___5 = 672,\n\tFN_NFRE_N___4 = 673,\n\tFN_MMC_CMD___2 = 674,\n\tFN_IP9_27_24___5 = 675,\n\tFN_NFDATA6___4 = 676,\n\tFN_MMC_D6___4 = 677,\n\tFN_IP10_27_24___4 = 678,\n\tFN_SSI_WS4_A = 679,\n\tFN_HRX0___6 = 680,\n\tFN_SDA2_A___4 = 681,\n\tFN_CAN1_TX_B = 682,\n\tFN_IP11_27_24___4 = 683,\n\tFN_TX0_A = 684,\n\tFN_MSIOF0_SS2___7 = 685,\n\tFN_FSO_TOE_N_B = 686,\n\tFN_IP8_31_28___5 = 687,\n\tFN_NFWE_N___4 = 688,\n\tFN_MMC_CLK___2 = 689,\n\tFN_IP9_31_28___5 = 690,\n\tFN_NFDATA7___4 = 691,\n\tFN_MMC_D7___4 = 692,\n\tFN_IP10_31_28___4 = 693,\n\tFN_SCL1___3 = 694,\n\tFN_CTS1_N___6 = 695,\n\tFN_IP11_31_28___4 = 696,\n\tFN_SCK1_A___2 = 697,\n\tFN_MSIOF1_SS2___4 = 698,\n\tFN_TPU0TO2_B___2 = 699,\n\tFN_CAN0_TX_B___4 = 700,\n\tFN_AUDIO_CLKOUT1 = 701,\n\tFN_IP12_3_0___4 = 702,\n\tFN_RX1_A___6 = 703,\n\tFN_CTS0_N___7 = 704,\n\tFN_TPU0TO0_B___2 = 705,\n\tFN_IP13_3_0___4 = 706,\n\tFN_CAN1_RX_A = 707,\n\tFN_CANFD1_RX___6 = 708,\n\tFN_TPU0TO2_A___2 = 709,\n\tFN_IP12_7_4___4 = 710,\n\tFN_TX1_A___6 = 711,\n\tFN_RTS0_N___7 = 712,\n\tFN_TPU0TO1_B___2 = 713,\n\tFN_IP13_7_4___4 = 714,\n\tFN_CAN1_TX_A = 715,\n\tFN_CANFD1_TX___6 = 716,\n\tFN_TPU0TO3_A___2 = 717,\n\tFN_IP12_11_8___4 = 718,\n\tFN_SCK2___4 = 719,\n\tFN_MSIOF1_SS1___4 = 720,\n\tFN_TPU0TO3_B___2 = 721,\n\tFN_IP12_15_12___4 = 722,\n\tFN_TPU0TO0_A___2 = 723,\n\tFN_AVB0_AVTP_CAPTURE_A = 724,\n\tFN_HCTS0_N___6 = 725,\n\tFN_IP12_19_16___4 = 726,\n\tFN_TPU0TO1_A___2 = 727,\n\tFN_AVB0_AVTP_MATCH_A = 728,\n\tFN_HRTS0_N___6 = 729,\n\tFN_IP12_23_20___4 = 730,\n\tFN_CAN_CLK___5 = 731,\n\tFN_AVB0_AVTP_PPS_A = 732,\n\tFN_SCK0_B = 733,\n\tFN_IRQ5_B = 734,\n\tFN_IP12_27_24___4 = 735,\n\tFN_CAN0_RX_A___4 = 736,\n\tFN_CANFD0_RX___2 = 737,\n\tFN_RX0_B = 738,\n\tFN_IP12_31_28___4 = 739,\n\tFN_CAN0_TX_A___4 = 740,\n\tFN_CANFD0_TX___2 = 741,\n\tFN_TX0_B = 742,\n\tFN_SEL_CAN0_0 = 743,\n\tFN_SEL_CAN0_1 = 744,\n\tFN_SEL_MSIOF2_0___4 = 745,\n\tFN_SEL_MSIOF2_1___4 = 746,\n\tFN_SEL_CAN1_0 = 747,\n\tFN_SEL_CAN1_1 = 748,\n\tFN_SEL_I2C3_0___2 = 749,\n\tFN_SEL_I2C3_1 = 750,\n\tFN_SEL_I2C2_0___5 = 751,\n\tFN_SEL_I2C2_1___4 = 752,\n\tFN_SEL_SCIF5_0___4 = 753,\n\tFN_SEL_SCIF5_1___4 = 754,\n\tFN_SEL_ETHERAVB_0___4 = 755,\n\tFN_SEL_ETHERAVB_1___4 = 756,\n\tFN_SEL_MSIOF3_0___4 = 757,\n\tFN_SEL_MSIOF3_1___4 = 758,\n\tFN_SEL_SCIF0_0 = 759,\n\tFN_SEL_SCIF0_1 = 760,\n\tFN_SEL_HSCIF3_0___4 = 761,\n\tFN_SEL_HSCIF3_1___4 = 762,\n\tFN_SEL_SSIF4_0 = 763,\n\tFN_SEL_SSIF4_1 = 764,\n\tFN_SEL_SCIF4_0___4 = 765,\n\tFN_SEL_SCIF4_1___4 = 766,\n\tFN_SEL_PWM0_0___2 = 767,\n\tFN_SEL_PWM0_2 = 768,\n\tFN_SEL_PWM0_1___2 = 769,\n\tFN_SEL_PWM1_0___5 = 770,\n\tFN_SEL_PWM1_2 = 771,\n\tFN_SEL_PWM1_1___5 = 772,\n\tFN_SEL_PWM2_0___5 = 773,\n\tFN_SEL_PWM2_2 = 774,\n\tFN_SEL_PWM2_1___5 = 775,\n\tFN_SEL_PWM3_0___5 = 776,\n\tFN_SEL_PWM3_2 = 777,\n\tFN_SEL_PWM3_1___5 = 778,\n\tFN_SEL_IRQ_0_0 = 779,\n\tFN_SEL_IRQ_0_1 = 780,\n\tFN_SEL_IRQ_1_0 = 781,\n\tFN_SEL_IRQ_1_1 = 782,\n\tFN_SEL_IRQ_2_0 = 783,\n\tFN_SEL_IRQ_2_1 = 784,\n\tFN_SEL_IRQ_3_0 = 785,\n\tFN_SEL_IRQ_3_1 = 786,\n\tFN_SEL_IRQ_4_0 = 787,\n\tFN_SEL_IRQ_4_1 = 788,\n\tFN_SEL_IRQ_5_0 = 789,\n\tFN_SEL_IRQ_5_1 = 790,\n\tFN_SEL_TMU_0_0 = 791,\n\tFN_SEL_TMU_0_1 = 792,\n\tFN_SEL_TMU_1_0 = 793,\n\tFN_SEL_TMU_1_1 = 794,\n\tFN_SEL_SCIF3_0___4 = 795,\n\tFN_SEL_SCIF3_1___4 = 796,\n\tFN_SEL_SCIF1_0___5 = 797,\n\tFN_SEL_SCIF1_1___5 = 798,\n\tFN_SEL_SCU_0 = 799,\n\tFN_SEL_SCU_1 = 800,\n\tFN_SEL_RFSO_0 = 801,\n\tFN_SEL_RFSO_1 = 802,\n\tPINMUX_FUNCTION_END___7 = 803,\n\tPINMUX_MARK_BEGIN___7 = 804,\n\tTX2_MARK = 805,\n\tRX2_MARK = 806,\n\tAVB0_LINK_MARK___2 = 807,\n\tAVB0_PHY_INT_MARK___2 = 808,\n\tAVB0_MAGIC_MARK___2 = 809,\n\tAVB0_MDC_MARK___2 = 810,\n\tAVB0_MDIO_MARK___2 = 811,\n\tMSIOF0_RXD_MARK___7 = 812,\n\tAVB0_TXCREFCLK_MARK___2 = 813,\n\tMSIOF0_TXD_MARK___7 = 814,\n\tAVB0_TD3_MARK___2 = 815,\n\tMSIOF0_SYNC_MARK___7 = 816,\n\tAVB0_TD2_MARK___2 = 817,\n\tRPC_INT_N_MARK___4 = 818,\n\tMSIOF0_SCK_MARK___7 = 819,\n\tAVB0_TD1_MARK___2 = 820,\n\tRPC_RESET_N_MARK___4 = 821,\n\tAVB0_TD0_MARK___2 = 822,\n\tQSPI1_SSL_MARK___7 = 823,\n\tAVB0_TXC_MARK___2 = 824,\n\tQSPI1_IO3_MARK___7 = 825,\n\tSDA0_MARK___7 = 826,\n\tAVB0_TX_CTL_MARK___2 = 827,\n\tQSPI1_IO2_MARK___7 = 828,\n\tSCL0_MARK___7 = 829,\n\tAVB0_RD3_MARK___2 = 830,\n\tQSPI1_MISO_IO1_MARK___7 = 831,\n\tAVB0_RD2_MARK___2 = 832,\n\tQSPI1_MOSI_IO0_MARK___7 = 833,\n\tAVB0_RD1_MARK___2 = 834,\n\tQSPI1_SPCLK_MARK___7 = 835,\n\tVI4_DATA4_MARK = 836,\n\tAVB0_RD0_MARK___2 = 837,\n\tQSPI0_SSL_MARK___7 = 838,\n\tAVB0_RXC_MARK___2 = 839,\n\tQSPI0_IO3_MARK___7 = 840,\n\tAVB0_RX_CTL_MARK___2 = 841,\n\tQSPI0_IO2_MARK___7 = 842,\n\tQSPI0_MISO_IO1_MARK___7 = 843,\n\tUSB0_OVC_MARK___4 = 844,\n\tQSPI0_MOSI_IO0_MARK___7 = 845,\n\tUSB0_PWEN_MARK___4 = 846,\n\tVI4_CLK_MARK___4 = 847,\n\tQSPI0_SPCLK_MARK___7 = 848,\n\tIP0_3_0_MARK___5 = 849,\n\tIRQ0_A_MARK___2 = 850,\n\tMSIOF2_SYNC_B_MARK___4 = 851,\n\tIP1_3_0_MARK___5 = 852,\n\tDU_DB1_MARK___5 = 853,\n\tLCDOUT1_MARK___4 = 854,\n\tMSIOF3_RXD_B_MARK___4 = 855,\n\tIP2_3_0_MARK___5 = 856,\n\tDU_DG1_MARK___5 = 857,\n\tLCDOUT9_MARK___4 = 858,\n\tMSIOF3_SYNC_B_MARK___4 = 859,\n\tIP3_3_0_MARK___5 = 860,\n\tDU_DR1_MARK___5 = 861,\n\tLCDOUT17_MARK___4 = 862,\n\tTX4_B_MARK___4 = 863,\n\tIP0_7_4_MARK___5 = 864,\n\tMSIOF2_SCK_MARK___4 = 865,\n\tIP1_7_4_MARK___5 = 866,\n\tDU_DB2_MARK___5 = 867,\n\tLCDOUT2_MARK___4 = 868,\n\tIRQ0_B_MARK___2 = 869,\n\tIP2_7_4_MARK___5 = 870,\n\tDU_DG2_MARK___5 = 871,\n\tLCDOUT10_MARK___4 = 872,\n\tIP3_7_4_MARK___5 = 873,\n\tDU_DR2_MARK___5 = 874,\n\tLCDOUT18_MARK___4 = 875,\n\tPWM0_B_MARK___2 = 876,\n\tIP0_11_8_MARK___5 = 877,\n\tMSIOF2_TXD_MARK___4 = 878,\n\tSCL3_A_MARK = 879,\n\tIP1_11_8_MARK___5 = 880,\n\tDU_DB3_MARK___5 = 881,\n\tLCDOUT3_MARK___4 = 882,\n\tSCK5_B_MARK___4 = 883,\n\tIP2_11_8_MARK___5 = 884,\n\tDU_DG3_MARK___5 = 885,\n\tLCDOUT11_MARK___4 = 886,\n\tIRQ1_A_MARK___2 = 887,\n\tIP3_11_8_MARK___5 = 888,\n\tDU_DR3_MARK___5 = 889,\n\tLCDOUT19_MARK___4 = 890,\n\tPWM1_B_MARK___6 = 891,\n\tIP0_15_12_MARK___5 = 892,\n\tMSIOF2_RXD_MARK___4 = 893,\n\tSDA3_A_MARK = 894,\n\tIP1_15_12_MARK___5 = 895,\n\tDU_DB4_MARK___5 = 896,\n\tLCDOUT4_MARK___4 = 897,\n\tRX5_B_MARK___4 = 898,\n\tIP2_15_12_MARK___5 = 899,\n\tDU_DG4_MARK___5 = 900,\n\tLCDOUT12_MARK___4 = 901,\n\tHSCK3_B_MARK___2 = 902,\n\tIP3_15_12_MARK___5 = 903,\n\tDU_DR4_MARK___5 = 904,\n\tLCDOUT20_MARK___4 = 905,\n\tTCLK2_B_MARK___6 = 906,\n\tIP0_19_16_MARK___5 = 907,\n\tMLB_CLK_MARK___4 = 908,\n\tMSIOF2_SYNC_A_MARK___4 = 909,\n\tSCK5_A_MARK___4 = 910,\n\tIP1_19_16_MARK___5 = 911,\n\tDU_DB5_MARK___5 = 912,\n\tLCDOUT5_MARK___4 = 913,\n\tTX5_B_MARK___4 = 914,\n\tIP2_19_16_MARK___5 = 915,\n\tDU_DG5_MARK___5 = 916,\n\tLCDOUT13_MARK___4 = 917,\n\tHTX3_B_MARK___5 = 918,\n\tIP3_19_16_MARK___5 = 919,\n\tDU_DR5_MARK___5 = 920,\n\tLCDOUT21_MARK___4 = 921,\n\tNMI_MARK = 922,\n\tIP0_23_20_MARK___5 = 923,\n\tMLB_DAT_MARK___4 = 924,\n\tMSIOF2_SS1_MARK___4 = 925,\n\tRX5_A_MARK___4 = 926,\n\tSCL3_B_MARK = 927,\n\tIP1_23_20_MARK___5 = 928,\n\tDU_DB6_MARK___5 = 929,\n\tLCDOUT6_MARK___4 = 930,\n\tMSIOF3_SS1_B_MARK___4 = 931,\n\tIP2_23_20_MARK___5 = 932,\n\tDU_DG6_MARK___5 = 933,\n\tLCDOUT14_MARK___4 = 934,\n\tHRX3_B_MARK___5 = 935,\n\tIP3_23_20_MARK___5 = 936,\n\tDU_DR6_MARK___5 = 937,\n\tLCDOUT22_MARK___4 = 938,\n\tPWM2_B_MARK___5 = 939,\n\tIP0_27_24_MARK___5 = 940,\n\tMLB_SIG_MARK___4 = 941,\n\tMSIOF2_SS2_MARK___4 = 942,\n\tTX5_A_MARK___4 = 943,\n\tSDA3_B_MARK = 944,\n\tIP1_27_24_MARK___5 = 945,\n\tDU_DB7_MARK___5 = 946,\n\tLCDOUT7_MARK___4 = 947,\n\tMSIOF3_SS2_B_MARK___4 = 948,\n\tIP2_27_24_MARK___5 = 949,\n\tDU_DG7_MARK___5 = 950,\n\tLCDOUT15_MARK___4 = 951,\n\tSCK4_B_MARK___4 = 952,\n\tIP3_27_24_MARK___5 = 953,\n\tDU_DR7_MARK___5 = 954,\n\tLCDOUT23_MARK___4 = 955,\n\tTCLK1_B_MARK___6 = 956,\n\tIP0_31_28_MARK___5 = 957,\n\tDU_DB0_MARK___5 = 958,\n\tLCDOUT0_MARK___4 = 959,\n\tMSIOF3_TXD_B_MARK___4 = 960,\n\tIP1_31_28_MARK___5 = 961,\n\tDU_DG0_MARK___5 = 962,\n\tLCDOUT8_MARK___4 = 963,\n\tMSIOF3_SCK_B_MARK___4 = 964,\n\tIP2_31_28_MARK___5 = 965,\n\tDU_DR0_MARK___5 = 966,\n\tLCDOUT16_MARK___4 = 967,\n\tRX4_B_MARK___4 = 968,\n\tIP3_31_28_MARK___5 = 969,\n\tDU_DOTCLKOUT0_MARK___4 = 970,\n\tQCLK_MARK___4 = 971,\n\tIP4_3_0_MARK___5 = 972,\n\tDU_HSYNC_MARK = 973,\n\tQSTH_QHS_MARK___4 = 974,\n\tIRQ3_A_MARK___2 = 975,\n\tIP5_3_0_MARK___5 = 976,\n\tVI4_DATA1_MARK = 977,\n\tPWM1_A_MARK___6 = 978,\n\tIP6_3_0_MARK___5 = 979,\n\tVI4_DATA10_MARK___4 = 980,\n\tRX4_A_MARK___4 = 981,\n\tIP7_3_0_MARK___5 = 982,\n\tVI4_DATA18_MARK___4 = 983,\n\tHSCK3_A_MARK___2 = 984,\n\tIP4_7_4_MARK___5 = 985,\n\tDU_VSYNC_MARK = 986,\n\tQSTVA_QVS_MARK___4 = 987,\n\tIRQ4_A_MARK___2 = 988,\n\tIP5_7_4_MARK___5 = 989,\n\tVI4_DATA2_MARK = 990,\n\tPWM2_A_MARK___5 = 991,\n\tIP6_7_4_MARK___5 = 992,\n\tVI4_DATA11_MARK___4 = 993,\n\tTX4_A_MARK___4 = 994,\n\tIP7_7_4_MARK___5 = 995,\n\tVI4_DATA19_MARK___4 = 996,\n\tSSI_WS4_B_MARK = 997,\n\tNFDATA15_MARK = 998,\n\tIP4_11_8_MARK___5 = 999,\n\tDU_DISP_MARK___5 = 1000,\n\tQSTVB_QVE_MARK___4 = 1001,\n\tPWM3_B_MARK___6 = 1002,\n\tIP5_11_8_MARK___5 = 1003,\n\tVI4_DATA3_MARK = 1004,\n\tPWM3_A_MARK___6 = 1005,\n\tIP6_11_8_MARK___5 = 1006,\n\tVI4_DATA12_MARK___4 = 1007,\n\tTCLK1_A_MARK___6 = 1008,\n\tIP7_11_8_MARK___5 = 1009,\n\tVI4_DATA20_MARK___4 = 1010,\n\tMSIOF3_SYNC_A_MARK___4 = 1011,\n\tNFDATA14_MARK = 1012,\n\tIP4_15_12_MARK___5 = 1013,\n\tDU_DISP_CDE_MARK = 1014,\n\tQCPV_QDE_MARK___4 = 1015,\n\tIRQ2_B_MARK___2 = 1016,\n\tDU_DOTCLKIN1_MARK___4 = 1017,\n\tIP5_15_12_MARK___5 = 1018,\n\tVI4_DATA5_MARK = 1019,\n\tSCK4_A_MARK___4 = 1020,\n\tIP6_15_12_MARK___5 = 1021,\n\tVI4_DATA13_MARK___4 = 1022,\n\tMSIOF3_SS1_A_MARK___4 = 1023,\n\tHCTS3_N_MARK___6 = 1024,\n\tIP7_15_12_MARK___2 = 1025,\n\tVI4_DATA21_MARK___4 = 1026,\n\tMSIOF3_TXD_A_MARK___4 = 1027,\n\tNFDATA13_MARK___4 = 1028,\n\tIP4_19_16_MARK___5 = 1029,\n\tDU_CDE_MARK___5 = 1030,\n\tQSTB_QHE_MARK___4 = 1031,\n\tSCK3_B_MARK___2 = 1032,\n\tIP5_19_16_MARK___5 = 1033,\n\tVI4_DATA6_MARK = 1034,\n\tIRQ2_A_MARK___2 = 1035,\n\tIP6_19_16_MARK___5 = 1036,\n\tVI4_DATA14_MARK___4 = 1037,\n\tSSI_SCK4_B_MARK = 1038,\n\tHRTS3_N_MARK___6 = 1039,\n\tIP7_19_16_MARK___5 = 1040,\n\tVI4_DATA22_MARK___4 = 1041,\n\tMSIOF3_RXD_A_MARK___4 = 1042,\n\tNFDATA12_MARK___4 = 1043,\n\tIP4_23_20_MARK___5 = 1044,\n\tQPOLA_MARK___4 = 1045,\n\tRX3_B_MARK___5 = 1046,\n\tIP5_23_20_MARK___5 = 1047,\n\tVI4_DATA7_MARK = 1048,\n\tTCLK2_A_MARK___6 = 1049,\n\tIP6_23_20_MARK___5 = 1050,\n\tVI4_DATA15_MARK___4 = 1051,\n\tSSI_SDATA4_B_MARK = 1052,\n\tIP7_23_20_MARK___5 = 1053,\n\tVI4_DATA23_MARK___4 = 1054,\n\tMSIOF3_SCK_A_MARK___4 = 1055,\n\tNFDATA11_MARK___4 = 1056,\n\tIP4_27_24_MARK___5 = 1057,\n\tQPOLB_MARK___4 = 1058,\n\tTX3_B_MARK___5 = 1059,\n\tIP5_27_24_MARK___5 = 1060,\n\tVI4_DATA8_MARK___4 = 1061,\n\tIP6_27_24_MARK___5 = 1062,\n\tVI4_DATA16_MARK___4 = 1063,\n\tHRX3_A_MARK___5 = 1064,\n\tIP7_27_24_MARK___5 = 1065,\n\tVI4_VSYNC_N_MARK___4 = 1066,\n\tSCK1_B_MARK___2 = 1067,\n\tNFDATA10_MARK___4 = 1068,\n\tIP4_31_28_MARK___5 = 1069,\n\tVI4_DATA0_MARK = 1070,\n\tPWM0_A_MARK___2 = 1071,\n\tIP5_31_28_MARK___5 = 1072,\n\tVI4_DATA9_MARK___4 = 1073,\n\tMSIOF3_SS2_A_MARK___4 = 1074,\n\tIRQ1_B_MARK___2 = 1075,\n\tIP6_31_28_MARK___5 = 1076,\n\tVI4_DATA17_MARK___4 = 1077,\n\tHTX3_A_MARK___5 = 1078,\n\tIP7_31_28_MARK___5 = 1079,\n\tVI4_HSYNC_N_MARK___4 = 1080,\n\tRX1_B_MARK___6 = 1081,\n\tNFDATA9_MARK___4 = 1082,\n\tIP8_3_0_MARK___5 = 1083,\n\tVI4_FIELD_MARK___4 = 1084,\n\tAUDIO_CLKB_MARK = 1085,\n\tIRQ5_A_MARK = 1086,\n\tSCIF_CLK_MARK___3 = 1087,\n\tNFDATA8_MARK___4 = 1088,\n\tIP9_3_0_MARK___5 = 1089,\n\tNFDATA0_MARK___4 = 1090,\n\tMMC_D0_MARK___2 = 1091,\n\tIP10_3_0_MARK___5 = 1092,\n\tAUDIO_CLKA_MARK = 1093,\n\tDVC_MUTE_B_MARK = 1094,\n\tIP11_3_0_MARK___4 = 1095,\n\tSDA1_MARK___4 = 1096,\n\tRTS1_N_MARK___6 = 1097,\n\tIP8_7_4_MARK___5 = 1098,\n\tVI4_CLKENB_MARK___4 = 1099,\n\tTX1_B_MARK___6 = 1100,\n\tNFWP_N_MARK = 1101,\n\tDVC_MUTE_A_MARK = 1102,\n\tIP9_7_4_MARK___5 = 1103,\n\tNFDATA1_MARK___4 = 1104,\n\tMMC_D1_MARK___2 = 1105,\n\tIP10_7_4_MARK___5 = 1106,\n\tSSI_SCK34_MARK = 1107,\n\tFSO_CFE_0_N_A_MARK = 1108,\n\tIP11_7_4_MARK___4 = 1109,\n\tMSIOF1_SCK_MARK___4 = 1110,\n\tAVB0_AVTP_PPS_B_MARK = 1111,\n\tIP8_11_8_MARK___5 = 1112,\n\tNFALE_MARK___4 = 1113,\n\tSCL2_B_MARK___4 = 1114,\n\tIRQ3_B_MARK___2 = 1115,\n\tPWM0_C_MARK = 1116,\n\tIP9_11_8_MARK___5 = 1117,\n\tNFDATA2_MARK___4 = 1118,\n\tMMC_D2_MARK___2 = 1119,\n\tIP10_11_8_MARK___5 = 1120,\n\tSSI_SDATA3_MARK___4 = 1121,\n\tFSO_CFE_1_N_A_MARK = 1122,\n\tIP11_11_8_MARK___4 = 1123,\n\tMSIOF1_TXD_MARK___4 = 1124,\n\tAVB0_AVTP_CAPTURE_B_MARK = 1125,\n\tIP8_15_12_MARK___5 = 1126,\n\tNFCLE_MARK___4 = 1127,\n\tSDA2_B_MARK___4 = 1128,\n\tSCK3_A_MARK___2 = 1129,\n\tPWM1_C_MARK = 1130,\n\tIP9_15_12_MARK___5 = 1131,\n\tNFDATA3_MARK___4 = 1132,\n\tMMC_D3_MARK___2 = 1133,\n\tIP10_15_12_MARK___5 = 1134,\n\tSSI_WS34_MARK = 1135,\n\tFSO_TOE_N_A_MARK = 1136,\n\tIP11_15_12_MARK___4 = 1137,\n\tMSIOF1_RXD_MARK___4 = 1138,\n\tAVB0_AVTP_MATCH_B_MARK = 1139,\n\tIP8_19_16_MARK___5 = 1140,\n\tNFCE_N_MARK = 1141,\n\tRX3_A_MARK___5 = 1142,\n\tPWM2_C_MARK = 1143,\n\tIP9_19_16_MARK___5 = 1144,\n\tNFDATA4_MARK___4 = 1145,\n\tMMC_D4_MARK___4 = 1146,\n\tIP10_19_16_MARK___5 = 1147,\n\tSSI_SCK4_A_MARK = 1148,\n\tHSCK0_MARK___6 = 1149,\n\tAUDIO_CLKOUT_MARK___2 = 1150,\n\tCAN0_RX_B_MARK___4 = 1151,\n\tIRQ4_B_MARK___2 = 1152,\n\tIP11_19_16_MARK___4 = 1153,\n\tSCK0_A_MARK = 1154,\n\tMSIOF1_SYNC_MARK___4 = 1155,\n\tFSO_CFE_0_N_B_MARK = 1156,\n\tIP8_23_20_MARK___5 = 1157,\n\tNFRB_N_MARK = 1158,\n\tTX3_A_MARK___5 = 1159,\n\tPWM3_C_MARK = 1160,\n\tIP9_23_20_MARK___5 = 1161,\n\tNFDATA5_MARK___4 = 1162,\n\tMMC_D5_MARK___4 = 1163,\n\tIP10_23_20_MARK___4 = 1164,\n\tSSI_SDATA4_A_MARK = 1165,\n\tHTX0_MARK___6 = 1166,\n\tSCL2_A_MARK___4 = 1167,\n\tCAN1_RX_B_MARK = 1168,\n\tIP11_23_20_MARK___4 = 1169,\n\tRX0_A_MARK = 1170,\n\tMSIOF0_SS1_MARK___7 = 1171,\n\tFSO_CFE_1_N_B_MARK = 1172,\n\tIP8_27_24_MARK___5 = 1173,\n\tNFRE_N_MARK___4 = 1174,\n\tMMC_CMD_MARK___2 = 1175,\n\tIP9_27_24_MARK___5 = 1176,\n\tNFDATA6_MARK___4 = 1177,\n\tMMC_D6_MARK___4 = 1178,\n\tIP10_27_24_MARK___4 = 1179,\n\tSSI_WS4_A_MARK = 1180,\n\tHRX0_MARK___6 = 1181,\n\tSDA2_A_MARK___4 = 1182,\n\tCAN1_TX_B_MARK = 1183,\n\tIP11_27_24_MARK___4 = 1184,\n\tTX0_A_MARK = 1185,\n\tMSIOF0_SS2_MARK___7 = 1186,\n\tFSO_TOE_N_B_MARK = 1187,\n\tIP8_31_28_MARK___5 = 1188,\n\tNFWE_N_MARK___4 = 1189,\n\tMMC_CLK_MARK___2 = 1190,\n\tIP9_31_28_MARK___5 = 1191,\n\tNFDATA7_MARK___4 = 1192,\n\tMMC_D7_MARK___4 = 1193,\n\tIP10_31_28_MARK___4 = 1194,\n\tSCL1_MARK___4 = 1195,\n\tCTS1_N_MARK___6 = 1196,\n\tIP11_31_28_MARK___4 = 1197,\n\tSCK1_A_MARK___2 = 1198,\n\tMSIOF1_SS2_MARK___4 = 1199,\n\tTPU0TO2_B_MARK___2 = 1200,\n\tCAN0_TX_B_MARK___4 = 1201,\n\tAUDIO_CLKOUT1_MARK = 1202,\n\tIP12_3_0_MARK___4 = 1203,\n\tRX1_A_MARK___6 = 1204,\n\tCTS0_N_MARK___7 = 1205,\n\tTPU0TO0_B_MARK___2 = 1206,\n\tIP13_3_0_MARK___4 = 1207,\n\tCAN1_RX_A_MARK = 1208,\n\tCANFD1_RX_MARK___6 = 1209,\n\tTPU0TO2_A_MARK___2 = 1210,\n\tIP12_7_4_MARK___4 = 1211,\n\tTX1_A_MARK___6 = 1212,\n\tRTS0_N_MARK___7 = 1213,\n\tTPU0TO1_B_MARK___2 = 1214,\n\tIP13_7_4_MARK___4 = 1215,\n\tCAN1_TX_A_MARK = 1216,\n\tCANFD1_TX_MARK___6 = 1217,\n\tTPU0TO3_A_MARK___2 = 1218,\n\tIP12_11_8_MARK___4 = 1219,\n\tSCK2_MARK___4 = 1220,\n\tMSIOF1_SS1_MARK___4 = 1221,\n\tTPU0TO3_B_MARK___2 = 1222,\n\tIP12_15_12_MARK___4 = 1223,\n\tTPU0TO0_A_MARK___2 = 1224,\n\tAVB0_AVTP_CAPTURE_A_MARK = 1225,\n\tHCTS0_N_MARK___6 = 1226,\n\tIP12_19_16_MARK___4 = 1227,\n\tTPU0TO1_A_MARK___2 = 1228,\n\tAVB0_AVTP_MATCH_A_MARK = 1229,\n\tHRTS0_N_MARK___6 = 1230,\n\tIP12_23_20_MARK___4 = 1231,\n\tCAN_CLK_MARK___5 = 1232,\n\tAVB0_AVTP_PPS_A_MARK = 1233,\n\tSCK0_B_MARK = 1234,\n\tIRQ5_B_MARK = 1235,\n\tIP12_27_24_MARK___4 = 1236,\n\tCAN0_RX_A_MARK___4 = 1237,\n\tCANFD0_RX_MARK___2 = 1238,\n\tRX0_B_MARK = 1239,\n\tIP12_31_28_MARK___4 = 1240,\n\tCAN0_TX_A_MARK___4 = 1241,\n\tCANFD0_TX_MARK___2 = 1242,\n\tTX0_B_MARK = 1243,\n\tSEL_CAN0_0_MARK = 1244,\n\tSEL_CAN0_1_MARK = 1245,\n\tSEL_MSIOF2_0_MARK___4 = 1246,\n\tSEL_MSIOF2_1_MARK___4 = 1247,\n\tSEL_CAN1_0_MARK = 1248,\n\tSEL_CAN1_1_MARK = 1249,\n\tSEL_I2C3_0_MARK___2 = 1250,\n\tSEL_I2C3_1_MARK = 1251,\n\tSEL_I2C2_0_MARK___5 = 1252,\n\tSEL_I2C2_1_MARK___4 = 1253,\n\tSEL_SCIF5_0_MARK___4 = 1254,\n\tSEL_SCIF5_1_MARK___4 = 1255,\n\tSEL_ETHERAVB_0_MARK___4 = 1256,\n\tSEL_ETHERAVB_1_MARK___4 = 1257,\n\tSEL_MSIOF3_0_MARK___4 = 1258,\n\tSEL_MSIOF3_1_MARK___4 = 1259,\n\tSEL_SCIF0_0_MARK = 1260,\n\tSEL_SCIF0_1_MARK = 1261,\n\tSEL_HSCIF3_0_MARK___4 = 1262,\n\tSEL_HSCIF3_1_MARK___4 = 1263,\n\tSEL_SSIF4_0_MARK = 1264,\n\tSEL_SSIF4_1_MARK = 1265,\n\tSEL_SCIF4_0_MARK___4 = 1266,\n\tSEL_SCIF4_1_MARK___4 = 1267,\n\tSEL_PWM0_0_MARK___2 = 1268,\n\tSEL_PWM0_2_MARK = 1269,\n\tSEL_PWM0_1_MARK___2 = 1270,\n\tSEL_PWM1_0_MARK___5 = 1271,\n\tSEL_PWM1_2_MARK = 1272,\n\tSEL_PWM1_1_MARK___5 = 1273,\n\tSEL_PWM2_0_MARK___5 = 1274,\n\tSEL_PWM2_2_MARK = 1275,\n\tSEL_PWM2_1_MARK___5 = 1276,\n\tSEL_PWM3_0_MARK___5 = 1277,\n\tSEL_PWM3_2_MARK = 1278,\n\tSEL_PWM3_1_MARK___5 = 1279,\n\tSEL_IRQ_0_0_MARK = 1280,\n\tSEL_IRQ_0_1_MARK = 1281,\n\tSEL_IRQ_1_0_MARK = 1282,\n\tSEL_IRQ_1_1_MARK = 1283,\n\tSEL_IRQ_2_0_MARK = 1284,\n\tSEL_IRQ_2_1_MARK = 1285,\n\tSEL_IRQ_3_0_MARK = 1286,\n\tSEL_IRQ_3_1_MARK = 1287,\n\tSEL_IRQ_4_0_MARK = 1288,\n\tSEL_IRQ_4_1_MARK = 1289,\n\tSEL_IRQ_5_0_MARK = 1290,\n\tSEL_IRQ_5_1_MARK = 1291,\n\tSEL_TMU_0_0_MARK = 1292,\n\tSEL_TMU_0_1_MARK = 1293,\n\tSEL_TMU_1_0_MARK = 1294,\n\tSEL_TMU_1_1_MARK = 1295,\n\tSEL_SCIF3_0_MARK___4 = 1296,\n\tSEL_SCIF3_1_MARK___4 = 1297,\n\tSEL_SCIF1_0_MARK___5 = 1298,\n\tSEL_SCIF1_1_MARK___5 = 1299,\n\tSEL_SCU_0_MARK = 1300,\n\tSEL_SCU_1_MARK = 1301,\n\tSEL_RFSO_0_MARK = 1302,\n\tSEL_RFSO_1_MARK = 1303,\n\tPINMUX_MARK_END___7 = 1304,\n};\n\nenum {\n\tPINMUX_RESERVED___8 = 0,\n\tPINMUX_DATA_BEGIN___8 = 1,\n\tGP_0_0_DATA___8 = 2,\n\tGP_0_1_DATA___8 = 3,\n\tGP_0_2_DATA___8 = 4,\n\tGP_0_3_DATA___8 = 5,\n\tGP_0_4_DATA___8 = 6,\n\tGP_0_5_DATA___8 = 7,\n\tGP_0_6_DATA___8 = 8,\n\tGP_0_7_DATA___8 = 9,\n\tGP_0_8_DATA___8 = 10,\n\tGP_0_9_DATA___7 = 11,\n\tGP_0_10_DATA___7 = 12,\n\tGP_0_11_DATA___7 = 13,\n\tGP_0_12_DATA___7 = 14,\n\tGP_0_13_DATA___7 = 15,\n\tGP_0_14_DATA___7 = 16,\n\tGP_0_15_DATA___7 = 17,\n\tGP_0_16_DATA___4 = 18,\n\tGP_0_17_DATA___4 = 19,\n\tGP_1_0_DATA___8 = 20,\n\tGP_1_1_DATA___8 = 21,\n\tGP_1_2_DATA___8 = 22,\n\tGP_1_3_DATA___8 = 23,\n\tGP_1_4_DATA___8 = 24,\n\tGP_1_5_DATA___8 = 25,\n\tGP_1_6_DATA___8 = 26,\n\tGP_1_7_DATA___8 = 27,\n\tGP_1_8_DATA___8 = 28,\n\tGP_1_9_DATA___8 = 29,\n\tGP_1_10_DATA___8 = 30,\n\tGP_1_11_DATA___8 = 31,\n\tGP_1_12_DATA___8 = 32,\n\tGP_1_13_DATA___8 = 33,\n\tGP_1_14_DATA___8 = 34,\n\tGP_1_15_DATA___8 = 35,\n\tGP_1_16_DATA___8 = 36,\n\tGP_1_17_DATA___8 = 37,\n\tGP_1_18_DATA___8 = 38,\n\tGP_1_19_DATA___8 = 39,\n\tGP_1_20_DATA___8 = 40,\n\tGP_1_21_DATA___8 = 41,\n\tGP_1_22_DATA___8 = 42,\n\tGP_2_0_DATA___8 = 43,\n\tGP_2_1_DATA___8 = 44,\n\tGP_2_2_DATA___8 = 45,\n\tGP_2_3_DATA___8 = 46,\n\tGP_2_4_DATA___8 = 47,\n\tGP_2_5_DATA___8 = 48,\n\tGP_2_6_DATA___8 = 49,\n\tGP_2_7_DATA___8 = 50,\n\tGP_2_8_DATA___8 = 51,\n\tGP_2_9_DATA___8 = 52,\n\tGP_2_10_DATA___8 = 53,\n\tGP_2_11_DATA___8 = 54,\n\tGP_2_12_DATA___8 = 55,\n\tGP_2_13_DATA___8 = 56,\n\tGP_2_14_DATA___8 = 57,\n\tGP_2_15_DATA___5 = 58,\n\tGP_2_16_DATA___5 = 59,\n\tGP_2_17_DATA___4 = 60,\n\tGP_2_18_DATA___4 = 61,\n\tGP_2_19_DATA___4 = 62,\n\tGP_2_20_DATA___3 = 63,\n\tGP_2_21_DATA___3 = 64,\n\tGP_2_22_DATA___3 = 65,\n\tGP_2_23_DATA___3 = 66,\n\tGP_2_24_DATA___3 = 67,\n\tGP_2_25_DATA___3 = 68,\n\tGP_3_0_DATA___8 = 69,\n\tGP_3_1_DATA___8 = 70,\n\tGP_3_2_DATA___8 = 71,\n\tGP_3_3_DATA___8 = 72,\n\tGP_3_4_DATA___8 = 73,\n\tGP_3_5_DATA___8 = 74,\n\tGP_3_6_DATA___8 = 75,\n\tGP_3_7_DATA___8 = 76,\n\tGP_3_8_DATA___8 = 77,\n\tGP_3_9_DATA___8 = 78,\n\tGP_3_10_DATA___7 = 79,\n\tGP_3_11_DATA___7 = 80,\n\tGP_3_12_DATA___7 = 81,\n\tGP_3_13_DATA___7 = 82,\n\tGP_3_14_DATA___7 = 83,\n\tGP_3_15_DATA___7 = 84,\n\tGP_4_0_DATA___7 = 85,\n\tGP_4_1_DATA___7 = 86,\n\tGP_4_2_DATA___7 = 87,\n\tGP_4_3_DATA___7 = 88,\n\tGP_4_4_DATA___7 = 89,\n\tGP_4_5_DATA___7 = 90,\n\tGP_4_6_DATA___7 = 91,\n\tGP_4_7_DATA___7 = 92,\n\tGP_4_8_DATA___7 = 93,\n\tGP_4_9_DATA___7 = 94,\n\tGP_4_10_DATA___7 = 95,\n\tGP_5_0_DATA___7 = 96,\n\tGP_5_1_DATA___7 = 97,\n\tGP_5_2_DATA___7 = 98,\n\tGP_5_3_DATA___7 = 99,\n\tGP_5_4_DATA___7 = 100,\n\tGP_5_5_DATA___7 = 101,\n\tGP_5_6_DATA___7 = 102,\n\tGP_5_7_DATA___7 = 103,\n\tGP_5_8_DATA___7 = 104,\n\tGP_5_9_DATA___7 = 105,\n\tGP_5_10_DATA___7 = 106,\n\tGP_5_11_DATA___7 = 107,\n\tGP_5_12_DATA___7 = 108,\n\tGP_5_13_DATA___7 = 109,\n\tGP_5_14_DATA___7 = 110,\n\tGP_5_15_DATA___6 = 111,\n\tGP_5_16_DATA___6 = 112,\n\tGP_5_17_DATA___6 = 113,\n\tGP_5_18_DATA___6 = 114,\n\tGP_5_19_DATA___6 = 115,\n\tGP_6_0_DATA___6 = 116,\n\tGP_6_1_DATA___6 = 117,\n\tGP_6_2_DATA___6 = 118,\n\tGP_6_3_DATA___6 = 119,\n\tGP_6_4_DATA___6 = 120,\n\tGP_6_5_DATA___6 = 121,\n\tGP_6_6_DATA___6 = 122,\n\tGP_6_7_DATA___6 = 123,\n\tGP_6_8_DATA___6 = 124,\n\tGP_6_9_DATA___6 = 125,\n\tGP_6_10_DATA___6 = 126,\n\tGP_6_11_DATA___6 = 127,\n\tGP_6_12_DATA___6 = 128,\n\tGP_6_13_DATA___6 = 129,\n\tGP_6_14_DATA___5 = 130,\n\tGP_6_15_DATA___5 = 131,\n\tGP_6_16_DATA___5 = 132,\n\tGP_6_17_DATA___5 = 133,\n\tPINMUX_DATA_END___8 = 134,\n\tPINMUX_FUNCTION_BEGIN___8 = 135,\n\tGP_0_0_FN___8 = 136,\n\tGP_0_1_FN___8 = 137,\n\tGP_0_2_FN___8 = 138,\n\tGP_0_3_FN___8 = 139,\n\tGP_0_4_FN___8 = 140,\n\tGP_0_5_FN___8 = 141,\n\tGP_0_6_FN___8 = 142,\n\tGP_0_7_FN___8 = 143,\n\tGP_0_8_FN___8 = 144,\n\tGP_0_9_FN___7 = 145,\n\tGP_0_10_FN___7 = 146,\n\tGP_0_11_FN___7 = 147,\n\tGP_0_12_FN___7 = 148,\n\tGP_0_13_FN___7 = 149,\n\tGP_0_14_FN___7 = 150,\n\tGP_0_15_FN___7 = 151,\n\tGP_0_16_FN___4 = 152,\n\tGP_0_17_FN___4 = 153,\n\tGP_1_0_FN___8 = 154,\n\tGP_1_1_FN___8 = 155,\n\tGP_1_2_FN___8 = 156,\n\tGP_1_3_FN___8 = 157,\n\tGP_1_4_FN___8 = 158,\n\tGP_1_5_FN___8 = 159,\n\tGP_1_6_FN___8 = 160,\n\tGP_1_7_FN___8 = 161,\n\tGP_1_8_FN___8 = 162,\n\tGP_1_9_FN___8 = 163,\n\tGP_1_10_FN___8 = 164,\n\tGP_1_11_FN___8 = 165,\n\tGP_1_12_FN___8 = 166,\n\tGP_1_13_FN___8 = 167,\n\tGP_1_14_FN___8 = 168,\n\tGP_1_15_FN___8 = 169,\n\tGP_1_16_FN___8 = 170,\n\tGP_1_17_FN___8 = 171,\n\tGP_1_18_FN___8 = 172,\n\tGP_1_19_FN___8 = 173,\n\tGP_1_20_FN___8 = 174,\n\tGP_1_21_FN___8 = 175,\n\tGP_1_22_FN___8 = 176,\n\tGP_2_0_FN___8 = 177,\n\tGP_2_1_FN___8 = 178,\n\tGP_2_2_FN___8 = 179,\n\tGP_2_3_FN___8 = 180,\n\tGP_2_4_FN___8 = 181,\n\tGP_2_5_FN___8 = 182,\n\tGP_2_6_FN___8 = 183,\n\tGP_2_7_FN___8 = 184,\n\tGP_2_8_FN___8 = 185,\n\tGP_2_9_FN___8 = 186,\n\tGP_2_10_FN___8 = 187,\n\tGP_2_11_FN___8 = 188,\n\tGP_2_12_FN___8 = 189,\n\tGP_2_13_FN___8 = 190,\n\tGP_2_14_FN___8 = 191,\n\tGP_2_15_FN___5 = 192,\n\tGP_2_16_FN___5 = 193,\n\tGP_2_17_FN___4 = 194,\n\tGP_2_18_FN___4 = 195,\n\tGP_2_19_FN___4 = 196,\n\tGP_2_20_FN___3 = 197,\n\tGP_2_21_FN___3 = 198,\n\tGP_2_22_FN___3 = 199,\n\tGP_2_23_FN___3 = 200,\n\tGP_2_24_FN___3 = 201,\n\tGP_2_25_FN___3 = 202,\n\tGP_3_0_FN___8 = 203,\n\tGP_3_1_FN___8 = 204,\n\tGP_3_2_FN___8 = 205,\n\tGP_3_3_FN___8 = 206,\n\tGP_3_4_FN___8 = 207,\n\tGP_3_5_FN___8 = 208,\n\tGP_3_6_FN___8 = 209,\n\tGP_3_7_FN___8 = 210,\n\tGP_3_8_FN___8 = 211,\n\tGP_3_9_FN___8 = 212,\n\tGP_3_10_FN___7 = 213,\n\tGP_3_11_FN___7 = 214,\n\tGP_3_12_FN___7 = 215,\n\tGP_3_13_FN___7 = 216,\n\tGP_3_14_FN___7 = 217,\n\tGP_3_15_FN___7 = 218,\n\tGP_4_0_FN___7 = 219,\n\tGP_4_1_FN___7 = 220,\n\tGP_4_2_FN___7 = 221,\n\tGP_4_3_FN___7 = 222,\n\tGP_4_4_FN___7 = 223,\n\tGP_4_5_FN___7 = 224,\n\tGP_4_6_FN___7 = 225,\n\tGP_4_7_FN___7 = 226,\n\tGP_4_8_FN___7 = 227,\n\tGP_4_9_FN___7 = 228,\n\tGP_4_10_FN___7 = 229,\n\tGP_5_0_FN___7 = 230,\n\tGP_5_1_FN___7 = 231,\n\tGP_5_2_FN___7 = 232,\n\tGP_5_3_FN___7 = 233,\n\tGP_5_4_FN___7 = 234,\n\tGP_5_5_FN___7 = 235,\n\tGP_5_6_FN___7 = 236,\n\tGP_5_7_FN___7 = 237,\n\tGP_5_8_FN___7 = 238,\n\tGP_5_9_FN___7 = 239,\n\tGP_5_10_FN___7 = 240,\n\tGP_5_11_FN___7 = 241,\n\tGP_5_12_FN___7 = 242,\n\tGP_5_13_FN___7 = 243,\n\tGP_5_14_FN___7 = 244,\n\tGP_5_15_FN___6 = 245,\n\tGP_5_16_FN___6 = 246,\n\tGP_5_17_FN___6 = 247,\n\tGP_5_18_FN___6 = 248,\n\tGP_5_19_FN___6 = 249,\n\tGP_6_0_FN___6 = 250,\n\tGP_6_1_FN___6 = 251,\n\tGP_6_2_FN___6 = 252,\n\tGP_6_3_FN___6 = 253,\n\tGP_6_4_FN___6 = 254,\n\tGP_6_5_FN___6 = 255,\n\tGP_6_6_FN___6 = 256,\n\tGP_6_7_FN___6 = 257,\n\tGP_6_8_FN___6 = 258,\n\tGP_6_9_FN___6 = 259,\n\tGP_6_10_FN___6 = 260,\n\tGP_6_11_FN___6 = 261,\n\tGP_6_12_FN___6 = 262,\n\tGP_6_13_FN___6 = 263,\n\tGP_6_14_FN___5 = 264,\n\tGP_6_15_FN___5 = 265,\n\tGP_6_16_FN___5 = 266,\n\tGP_6_17_FN___5 = 267,\n\tFN_AVB_PHY_INT___5 = 268,\n\tFN_CLKOUT___5 = 269,\n\tFN_AVB_RD3___2 = 270,\n\tFN_AVB_RXC___2 = 271,\n\tFN_AVB_RX_CTL___2 = 272,\n\tFN_QSPI0_SSL___5 = 273,\n\tFN_IP0_3_0___6 = 274,\n\tFN_QSPI0_SPCLK___5 = 275,\n\tFN_HSCK4_A = 276,\n\tFN_IP1_3_0___6 = 277,\n\tFN_QSPI1_IO2___5 = 278,\n\tFN_RIF2_D1_A___4 = 279,\n\tFN_HTX3_C___4 = 280,\n\tFN_VI4_DATA3_A___4 = 281,\n\tFN_IP2_3_0___6 = 282,\n\tFN_AVB_TXCREFCLK___2 = 283,\n\tFN_IP3_3_0___6 = 284,\n\tFN_A1___5 = 285,\n\tFN_IRQ1___6 = 286,\n\tFN_PWM3_A___7 = 287,\n\tFN_DU_DOTCLKIN1___2 = 288,\n\tFN_VI5_DATA0_A = 289,\n\tFN_DU_DISP_CDE___2 = 290,\n\tFN_SDA6_B___4 = 291,\n\tFN_IETX = 292,\n\tFN_QCPV_QDE___5 = 293,\n\tFN_IP0_7_4___6 = 294,\n\tFN_QSPI0_MOSI_IO0___5 = 295,\n\tFN_HCTS4_N_A = 296,\n\tFN_IP1_7_4___6 = 297,\n\tFN_QSPI1_IO3___5 = 298,\n\tFN_RIF3_CLK_A___4 = 299,\n\tFN_HRX3_C___4 = 300,\n\tFN_VI4_DATA4_A___4 = 301,\n\tFN_IP2_7_4___6 = 302,\n\tFN_AVB_MDIO___2 = 303,\n\tFN_IP3_7_4___6 = 304,\n\tFN_A2___5 = 305,\n\tFN_IRQ2___6 = 306,\n\tFN_AVB_AVTP_PPS___5 = 307,\n\tFN_VI4_CLKENB___5 = 308,\n\tFN_VI5_DATA1_A = 309,\n\tFN_DU_DISP___6 = 310,\n\tFN_SCL6_B___4 = 311,\n\tFN_QSTVB_QVE___5 = 312,\n\tFN_IP0_11_8___6 = 313,\n\tFN_QSPI0_MISO_IO1___5 = 314,\n\tFN_HRTS4_N_A = 315,\n\tFN_IP1_11_8___6 = 316,\n\tFN_QSPI1_SSL___5 = 317,\n\tFN_RIF3_SYNC_A___4 = 318,\n\tFN_HSCK3_C = 319,\n\tFN_VI4_DATA5_A___4 = 320,\n\tFN_IP2_11_8___6 = 321,\n\tFN_AVB_MDC___5 = 322,\n\tFN_IP3_11_8___6 = 323,\n\tFN_A3___5 = 324,\n\tFN_CTS4_N_A___4 = 325,\n\tFN_PWM4_A___5 = 326,\n\tFN_VI4_DATA12___5 = 327,\n\tFN_DU_DOTCLKOUT0___5 = 328,\n\tFN_HTX3_D___4 = 329,\n\tFN_IECLK = 330,\n\tFN_LCDOUT12___5 = 331,\n\tFN_IP0_15_12___6 = 332,\n\tFN_QSPI0_IO2___5 = 333,\n\tFN_HTX4_A___4 = 334,\n\tFN_IP1_15_12___6 = 335,\n\tFN_RPC_INT_N___5 = 336,\n\tFN_RIF3_D0_A___4 = 337,\n\tFN_HCTS3_N_C = 338,\n\tFN_VI4_DATA6_A___4 = 339,\n\tFN_IP2_15_12___6 = 340,\n\tFN_BS_N___5 = 341,\n\tFN_PWM0_A___3 = 342,\n\tFN_AVB_MAGIC___5 = 343,\n\tFN_VI4_CLK___5 = 344,\n\tFN_TX3_C = 345,\n\tFN_VI5_CLK_B = 346,\n\tFN_IP3_15_12___6 = 347,\n\tFN_A4___5 = 348,\n\tFN_RTS4_N_A___4 = 349,\n\tFN_MSIOF3_SYNC_B___5 = 350,\n\tFN_VI4_DATA8___5 = 351,\n\tFN_PWM2_B___6 = 352,\n\tFN_DU_DG4___6 = 353,\n\tFN_RIF2_CLK_B___4 = 354,\n\tFN_IP0_19_16___6 = 355,\n\tFN_QSPI0_IO3___5 = 356,\n\tFN_HRX4_A___4 = 357,\n\tFN_IP1_19_16___6 = 358,\n\tFN_RPC_RESET_N___5 = 359,\n\tFN_RIF3_D1_A___4 = 360,\n\tFN_HRTS3_N_C = 361,\n\tFN_VI4_DATA7_A___4 = 362,\n\tFN_IP2_19_16___6 = 363,\n\tFN_RD_N___5 = 364,\n\tFN_PWM1_A___7 = 365,\n\tFN_AVB_LINK___5 = 366,\n\tFN_VI4_FIELD___5 = 367,\n\tFN_RX3_C = 368,\n\tFN_FSCLKST2_N_A___3 = 369,\n\tFN_VI5_DATA0_B = 370,\n\tFN_IP3_19_16___6 = 371,\n\tFN_A5___5 = 372,\n\tFN_SCK4_A___5 = 373,\n\tFN_MSIOF3_SCK_B___5 = 374,\n\tFN_VI4_DATA9___5 = 375,\n\tFN_PWM3_B___7 = 376,\n\tFN_RIF2_SYNC_B___4 = 377,\n\tFN_QPOLA___5 = 378,\n\tFN_IP0_23_20___6 = 379,\n\tFN_QSPI1_SPCLK___5 = 380,\n\tFN_RIF2_CLK_A___4 = 381,\n\tFN_HSCK4_B = 382,\n\tFN_VI4_DATA0_A___4 = 383,\n\tFN_IP1_23_20___6 = 384,\n\tFN_AVB_RD0___2 = 385,\n\tFN_IP2_23_20___6 = 386,\n\tFN_RD_WR_N___5 = 387,\n\tFN_SCL7_A = 388,\n\tFN_AVB_AVTP_MATCH___2 = 389,\n\tFN_VI4_VSYNC_N___5 = 390,\n\tFN_TX5_B___5 = 391,\n\tFN_SCK3_C = 392,\n\tFN_PWM5_A___4 = 393,\n\tFN_IP3_23_20___6 = 394,\n\tFN_A6___5 = 395,\n\tFN_RX4_A___5 = 396,\n\tFN_MSIOF3_RXD_B___5 = 397,\n\tFN_VI4_DATA10___5 = 398,\n\tFN_RIF2_D0_B___4 = 399,\n\tFN_IP0_27_24___6 = 400,\n\tFN_QSPI1_MOSI_IO0___5 = 401,\n\tFN_RIF2_SYNC_A___4 = 402,\n\tFN_HTX4_B___4 = 403,\n\tFN_VI4_DATA1_A___4 = 404,\n\tFN_IP1_27_24___6 = 405,\n\tFN_AVB_RD1___2 = 406,\n\tFN_IP2_27_24___6 = 407,\n\tFN_EX_WAIT0___2 = 408,\n\tFN_SDA7_A = 409,\n\tFN_AVB_AVTP_CAPTURE___2 = 410,\n\tFN_VI4_HSYNC_N___5 = 411,\n\tFN_RX5_B___5 = 412,\n\tFN_PWM6_A___4 = 413,\n\tFN_IP3_27_24___6 = 414,\n\tFN_A7___5 = 415,\n\tFN_TX4_A___5 = 416,\n\tFN_MSIOF3_TXD_B___5 = 417,\n\tFN_VI4_DATA11___5 = 418,\n\tFN_RIF2_D1_B___4 = 419,\n\tFN_IP0_31_28___6 = 420,\n\tFN_QSPI1_MISO_IO1___5 = 421,\n\tFN_RIF2_D0_A___4 = 422,\n\tFN_HRX4_B___4 = 423,\n\tFN_VI4_DATA2_A___4 = 424,\n\tFN_IP1_31_28___6 = 425,\n\tFN_AVB_RD2___2 = 426,\n\tFN_IP2_31_28___6 = 427,\n\tFN_A0___5 = 428,\n\tFN_IRQ0___6 = 429,\n\tFN_PWM2_A___6 = 430,\n\tFN_MSIOF3_SS1_B___5 = 431,\n\tFN_VI5_CLK_A = 432,\n\tFN_DU_CDE___6 = 433,\n\tFN_HRX3_D___4 = 434,\n\tFN_IERX = 435,\n\tFN_QSTB_QHE___5 = 436,\n\tFN_IP3_31_28___6 = 437,\n\tFN_A8___5 = 438,\n\tFN_SDA6_A___4 = 439,\n\tFN_RX3_B___6 = 440,\n\tFN_HRX4_C = 441,\n\tFN_VI5_HSYNC_N_A = 442,\n\tFN_DU_HSYNC___2 = 443,\n\tFN_VI4_DATA0_B___4 = 444,\n\tFN_QSTH_QHS___5 = 445,\n\tFN_IP4_3_0___6 = 446,\n\tFN_A9___5 = 447,\n\tFN_TX5_A___5 = 448,\n\tFN_IRQ3___6 = 449,\n\tFN_VI4_DATA16___5 = 450,\n\tFN_VI5_VSYNC_N_A = 451,\n\tFN_DU_DG7___6 = 452,\n\tFN_LCDOUT15___5 = 453,\n\tFN_IP5_3_0___6 = 454,\n\tFN_A17___5 = 455,\n\tFN_MSIOF1_RXD___5 = 456,\n\tFN_VI4_DATA20___5 = 457,\n\tFN_VI5_DATA6_A = 458,\n\tFN_DU_DB6___6 = 459,\n\tFN_LCDOUT6___5 = 460,\n\tFN_IP6_3_0___6 = 461,\n\tFN_D3___5 = 462,\n\tFN_MSIOF3_TXD_A___5 = 463,\n\tFN_TX5_C = 464,\n\tFN_VI5_DATA15_A = 465,\n\tFN_DU_DR4___6 = 466,\n\tFN_TX4_C___4 = 467,\n\tFN_LCDOUT20___5 = 468,\n\tFN_IP7_3_0___6 = 469,\n\tFN_D11___5 = 470,\n\tFN_MSIOF2_TXD_A___4 = 471,\n\tFN_VI5_DATA11_A = 472,\n\tFN_DU_DG2___6 = 473,\n\tFN_RIF3_D1_B___4 = 474,\n\tFN_HRTS3_N_E = 475,\n\tFN_LCDOUT10___5 = 476,\n\tFN_IP4_7_4___6 = 477,\n\tFN_A10___5 = 478,\n\tFN_IRQ4___6 = 479,\n\tFN_MSIOF2_SYNC_B___5 = 480,\n\tFN_VI4_DATA13___5 = 481,\n\tFN_VI5_FIELD_A = 482,\n\tFN_DU_DG5___6 = 483,\n\tFN_FSCLKST2_N_B___3 = 484,\n\tFN_LCDOUT13___5 = 485,\n\tFN_IP5_7_4___6 = 486,\n\tFN_A18___5 = 487,\n\tFN_MSIOF1_TXD___5 = 488,\n\tFN_VI4_DATA21___5 = 489,\n\tFN_VI5_DATA7_A = 490,\n\tFN_DU_DB0___6 = 491,\n\tFN_HRX4_E = 492,\n\tFN_LCDOUT0___5 = 493,\n\tFN_IP6_7_4___6 = 494,\n\tFN_D4___5 = 495,\n\tFN_CANFD1_TX___7 = 496,\n\tFN_HSCK3_B___3 = 497,\n\tFN_CAN1_TX___4 = 498,\n\tFN_RTS3_N_A___2 = 499,\n\tFN_MSIOF3_SS2_A___5 = 500,\n\tFN_VI5_DATA1_B = 501,\n\tFN_IP7_7_4___6 = 502,\n\tFN_D12___5 = 503,\n\tFN_CANFD0_TX___3 = 504,\n\tFN_TX4_B___5 = 505,\n\tFN_CAN0_TX = 506,\n\tFN_VI5_DATA8_A = 507,\n\tFN_VI5_DATA3_B = 508,\n\tFN_IP4_11_8___6 = 509,\n\tFN_A11___5 = 510,\n\tFN_SCL6_A___4 = 511,\n\tFN_TX3_B___6 = 512,\n\tFN_HTX4_C = 513,\n\tFN_DU_VSYNC___2 = 514,\n\tFN_VI4_DATA1_B___4 = 515,\n\tFN_QSTVA_QVS___5 = 516,\n\tFN_IP5_11_8___6 = 517,\n\tFN_A19___5 = 518,\n\tFN_MSIOF1_SCK___5 = 519,\n\tFN_VI4_DATA22___5 = 520,\n\tFN_VI5_DATA2_A = 521,\n\tFN_DU_DB1___6 = 522,\n\tFN_HTX4_E = 523,\n\tFN_LCDOUT1___5 = 524,\n\tFN_IP6_11_8___6 = 525,\n\tFN_D5___5 = 526,\n\tFN_RX3_A___6 = 527,\n\tFN_HRX3_B___6 = 528,\n\tFN_DU_DR5___6 = 529,\n\tFN_VI4_DATA4_B___4 = 530,\n\tFN_LCDOUT21___5 = 531,\n\tFN_IP7_11_8___6 = 532,\n\tFN_D13___5 = 533,\n\tFN_CANFD0_RX___3 = 534,\n\tFN_RX4_B___5 = 535,\n\tFN_CAN0_RX = 536,\n\tFN_VI5_DATA9_A = 537,\n\tFN_SCL7_B = 538,\n\tFN_VI5_DATA4_B = 539,\n\tFN_IP4_15_12___6 = 540,\n\tFN_A12___5 = 541,\n\tFN_RX5_A___5 = 542,\n\tFN_MSIOF2_SS2_B___4 = 543,\n\tFN_VI4_DATA17___5 = 544,\n\tFN_VI5_DATA3_A = 545,\n\tFN_DU_DG6___6 = 546,\n\tFN_LCDOUT14___5 = 547,\n\tFN_IP5_15_12___6 = 548,\n\tFN_CS0_N___5 = 549,\n\tFN_SCL5___3 = 550,\n\tFN_DU_DR0___6 = 551,\n\tFN_VI4_DATA2_B___4 = 552,\n\tFN_LCDOUT16___5 = 553,\n\tFN_IP6_15_12___6 = 554,\n\tFN_D6___5 = 555,\n\tFN_TX3_A___6 = 556,\n\tFN_HTX3_B___6 = 557,\n\tFN_DU_DR6___6 = 558,\n\tFN_VI4_DATA5_B___4 = 559,\n\tFN_LCDOUT22___5 = 560,\n\tFN_IP7_15_12___3 = 561,\n\tFN_D14___5 = 562,\n\tFN_CAN_CLK___6 = 563,\n\tFN_HRX3_A___6 = 564,\n\tFN_MSIOF2_SS2_A___4 = 565,\n\tFN_SDA7_B = 566,\n\tFN_VI5_DATA5_B = 567,\n\tFN_IP4_19_16___6 = 568,\n\tFN_A13___5 = 569,\n\tFN_SCK5_A___5 = 570,\n\tFN_MSIOF2_SCK_B___4 = 571,\n\tFN_VI4_DATA14___5 = 572,\n\tFN_HRX4_D = 573,\n\tFN_DU_DB2___6 = 574,\n\tFN_LCDOUT2___5 = 575,\n\tFN_IP5_19_16___6 = 576,\n\tFN_WE0_N___5 = 577,\n\tFN_SDA5___3 = 578,\n\tFN_DU_DR1___6 = 579,\n\tFN_VI4_DATA3_B___4 = 580,\n\tFN_LCDOUT17___5 = 581,\n\tFN_IP6_19_16___6 = 582,\n\tFN_D7___5 = 583,\n\tFN_CANFD1_RX___7 = 584,\n\tFN_IRQ5___7 = 585,\n\tFN_CAN1_RX___4 = 586,\n\tFN_CTS3_N_A___2 = 587,\n\tFN_VI5_DATA2_B = 588,\n\tFN_IP7_19_16___6 = 589,\n\tFN_D15___5 = 590,\n\tFN_MSIOF2_SS1_A___4 = 591,\n\tFN_HTX3_A___6 = 592,\n\tFN_MSIOF3_SS1_A___5 = 593,\n\tFN_DU_DG3___6 = 594,\n\tFN_LCDOUT11___5 = 595,\n\tFN_IP4_23_20___6 = 596,\n\tFN_A14___5 = 597,\n\tFN_MSIOF1_SS1___5 = 598,\n\tFN_MSIOF2_RXD_B___4 = 599,\n\tFN_VI4_DATA15___5 = 600,\n\tFN_HTX4_D = 601,\n\tFN_DU_DB3___6 = 602,\n\tFN_LCDOUT3___5 = 603,\n\tFN_IP5_23_20___6 = 604,\n\tFN_D0___5 = 605,\n\tFN_MSIOF3_SCK_A___5 = 606,\n\tFN_DU_DR2___6 = 607,\n\tFN_CTS4_N_C___4 = 608,\n\tFN_LCDOUT18___5 = 609,\n\tFN_IP6_23_20___6 = 610,\n\tFN_D8___5 = 611,\n\tFN_MSIOF2_SCK_A___4 = 612,\n\tFN_SCK4_B___5 = 613,\n\tFN_VI5_DATA12_A = 614,\n\tFN_DU_DR7___6 = 615,\n\tFN_RIF3_CLK_B___4 = 616,\n\tFN_HCTS3_N_E = 617,\n\tFN_LCDOUT23___5 = 618,\n\tFN_IP7_23_20___6 = 619,\n\tFN_SCL4___3 = 620,\n\tFN_CS1_N_A26 = 621,\n\tFN_DU_DOTCLKIN0 = 622,\n\tFN_VI4_DATA6_B___4 = 623,\n\tFN_VI5_DATA6_B = 624,\n\tFN_QCLK___5 = 625,\n\tFN_IP4_27_24___6 = 626,\n\tFN_A15___5 = 627,\n\tFN_MSIOF1_SS2___5 = 628,\n\tFN_MSIOF2_TXD_B___4 = 629,\n\tFN_VI4_DATA18___5 = 630,\n\tFN_VI5_DATA4_A = 631,\n\tFN_DU_DB4___6 = 632,\n\tFN_LCDOUT4___5 = 633,\n\tFN_IP5_27_24___6 = 634,\n\tFN_D1___5 = 635,\n\tFN_MSIOF3_SYNC_A___5 = 636,\n\tFN_SCK3_A___3 = 637,\n\tFN_VI4_DATA23___5 = 638,\n\tFN_VI5_CLKENB_A = 639,\n\tFN_DU_DB7___6 = 640,\n\tFN_RTS4_N_C___4 = 641,\n\tFN_LCDOUT7___5 = 642,\n\tFN_IP6_27_24___6 = 643,\n\tFN_D9___5 = 644,\n\tFN_MSIOF2_SYNC_A___5 = 645,\n\tFN_VI5_DATA10_A = 646,\n\tFN_DU_DG0___6 = 647,\n\tFN_RIF3_SYNC_B___4 = 648,\n\tFN_HRX3_E = 649,\n\tFN_LCDOUT8___5 = 650,\n\tFN_IP7_27_24___6 = 651,\n\tFN_SDA4___3 = 652,\n\tFN_WE1_N___5 = 653,\n\tFN_VI4_DATA7_B___4 = 654,\n\tFN_VI5_DATA7_B = 655,\n\tFN_QPOLB___5 = 656,\n\tFN_IP4_31_28___6 = 657,\n\tFN_A16___5 = 658,\n\tFN_MSIOF1_SYNC___5 = 659,\n\tFN_MSIOF2_SS1_B___4 = 660,\n\tFN_VI4_DATA19___5 = 661,\n\tFN_VI5_DATA5_A = 662,\n\tFN_DU_DB5___6 = 663,\n\tFN_LCDOUT5___5 = 664,\n\tFN_IP5_31_28___6 = 665,\n\tFN_D2___5 = 666,\n\tFN_MSIOF3_RXD_A___5 = 667,\n\tFN_RX5_C = 668,\n\tFN_VI5_DATA14_A = 669,\n\tFN_DU_DR3___6 = 670,\n\tFN_RX4_C___4 = 671,\n\tFN_LCDOUT19___5 = 672,\n\tFN_IP6_31_28___6 = 673,\n\tFN_D10___5 = 674,\n\tFN_MSIOF2_RXD_A___4 = 675,\n\tFN_VI5_DATA13_A = 676,\n\tFN_DU_DG1___6 = 677,\n\tFN_RIF3_D0_B___4 = 678,\n\tFN_HTX3_E = 679,\n\tFN_LCDOUT9___5 = 680,\n\tFN_IP7_31_28___6 = 681,\n\tFN_SD0_CLK___4 = 682,\n\tFN_NFDATA8___5 = 683,\n\tFN_SCL1_C = 684,\n\tFN_HSCK1_B___5 = 685,\n\tFN_SDA2_E = 686,\n\tFN_FMCLK_B___4 = 687,\n\tFN_IP8_3_0___6 = 688,\n\tFN_SD0_CMD___4 = 689,\n\tFN_NFDATA9___5 = 690,\n\tFN_HRX1_B___5 = 691,\n\tFN_SPEEDIN_B___5 = 692,\n\tFN_IP9_3_0___6 = 693,\n\tFN_SD1_DAT1___4 = 694,\n\tFN_NFCE_N_B___4 = 695,\n\tFN_IP10_3_0___6 = 696,\n\tFN_SD3_DAT3___4 = 697,\n\tFN_NFDATA3___5 = 698,\n\tFN_IP11_3_0___5 = 699,\n\tFN_SD1_CD___4 = 700,\n\tFN_NFCE_N_A___4 = 701,\n\tFN_SSI_SCK1 = 702,\n\tFN_RIF0_D1_B___4 = 703,\n\tFN_TS_SDEN0 = 704,\n\tFN_IP8_7_4___6 = 705,\n\tFN_SD0_DAT0___4 = 706,\n\tFN_NFDATA10___5 = 707,\n\tFN_HTX1_B___5 = 708,\n\tFN_REMOCON_B___4 = 709,\n\tFN_IP9_7_4___6 = 710,\n\tFN_SD1_DAT2___4 = 711,\n\tFN_NFALE_B = 712,\n\tFN_IP10_7_4___6 = 713,\n\tFN_SD3_DAT4___4 = 714,\n\tFN_NFDATA4___5 = 715,\n\tFN_IP11_7_4___5 = 716,\n\tFN_SD1_WP___4 = 717,\n\tFN_NFWP_N_A___4 = 718,\n\tFN_SSI_WS1 = 719,\n\tFN_RIF0_SYNC_B___4 = 720,\n\tFN_TS_SPSYNC0 = 721,\n\tFN_IP8_11_8___6 = 722,\n\tFN_SD0_DAT1___4 = 723,\n\tFN_NFDATA11___5 = 724,\n\tFN_SDA2_C = 725,\n\tFN_HCTS1_N_B___5 = 726,\n\tFN_FMIN_B___4 = 727,\n\tFN_IP9_11_8___6 = 728,\n\tFN_SD1_DAT3___4 = 729,\n\tFN_NFRB_N_B___4 = 730,\n\tFN_IP10_11_8___6 = 731,\n\tFN_SD3_DAT5___4 = 732,\n\tFN_NFDATA5___5 = 733,\n\tFN_IP11_11_8___5 = 734,\n\tFN_RX0_A___2 = 735,\n\tFN_HRX1_A___5 = 736,\n\tFN_SSI_SCK2_A___4 = 737,\n\tFN_RIF1_SYNC = 738,\n\tFN_TS_SCK1 = 739,\n\tFN_IP8_15_12___6 = 740,\n\tFN_SD0_DAT2___4 = 741,\n\tFN_NFDATA12___5 = 742,\n\tFN_SCL2_C = 743,\n\tFN_HRTS1_N_B___5 = 744,\n\tFN_BPFCLK_B___4 = 745,\n\tFN_IP9_15_12___6 = 746,\n\tFN_SD3_CLK___4 = 747,\n\tFN_NFWE_N___5 = 748,\n\tFN_IP10_15_12___6 = 749,\n\tFN_SD3_DAT6___4 = 750,\n\tFN_NFDATA6___5 = 751,\n\tFN_IP11_15_12___5 = 752,\n\tFN_TX0_A___2 = 753,\n\tFN_HTX1_A___5 = 754,\n\tFN_SSI_WS2_A___4 = 755,\n\tFN_RIF1_D0 = 756,\n\tFN_TS_SDAT1 = 757,\n\tFN_IP8_19_16___6 = 758,\n\tFN_SD0_DAT3___4 = 759,\n\tFN_NFDATA13___5 = 760,\n\tFN_SDA1_C = 761,\n\tFN_SCL2_E = 762,\n\tFN_SPEEDIN_C = 763,\n\tFN_REMOCON_C = 764,\n\tFN_IP9_19_16___6 = 765,\n\tFN_SD3_CMD___4 = 766,\n\tFN_NFRE_N___5 = 767,\n\tFN_IP10_19_16___6 = 768,\n\tFN_SD3_DAT7___4 = 769,\n\tFN_NFDATA7___5 = 770,\n\tFN_IP11_19_16___5 = 771,\n\tFN_CTS0_N_A = 772,\n\tFN_NFDATA14_A___4 = 773,\n\tFN_AUDIO_CLKOUT_A___4 = 774,\n\tFN_RIF1_D1 = 775,\n\tFN_SCIF_CLK_A___5 = 776,\n\tFN_FMCLK_A___4 = 777,\n\tFN_IP8_23_20___6 = 778,\n\tFN_SD1_CLK___4 = 779,\n\tFN_NFDATA14_B___4 = 780,\n\tFN_IP9_23_20___6 = 781,\n\tFN_SD3_DAT0___4 = 782,\n\tFN_NFDATA0___5 = 783,\n\tFN_IP10_23_20___5 = 784,\n\tFN_SD3_DS___4 = 785,\n\tFN_NFCLE___5 = 786,\n\tFN_IP11_23_20___5 = 787,\n\tFN_RTS0_N_A = 788,\n\tFN_NFDATA15_A___4 = 789,\n\tFN_AUDIO_CLKOUT1_A___4 = 790,\n\tFN_RIF1_CLK = 791,\n\tFN_SCL2_A___5 = 792,\n\tFN_FMIN_A___4 = 793,\n\tFN_IP8_27_24___6 = 794,\n\tFN_SD1_CMD___4 = 795,\n\tFN_NFDATA15_B___4 = 796,\n\tFN_IP9_27_24___6 = 797,\n\tFN_SD3_DAT1___4 = 798,\n\tFN_NFDATA1___5 = 799,\n\tFN_IP10_27_24___5 = 800,\n\tFN_SD0_CD___4 = 801,\n\tFN_NFALE_A = 802,\n\tFN_SD3_CD___4 = 803,\n\tFN_RIF0_CLK_B___4 = 804,\n\tFN_SCL2_B___5 = 805,\n\tFN_TCLK1_A___7 = 806,\n\tFN_SSI_SCK2_B___4 = 807,\n\tFN_TS_SCK0 = 808,\n\tFN_IP11_27_24___5 = 809,\n\tFN_SCK0_A___2 = 810,\n\tFN_HSCK1_A___5 = 811,\n\tFN_USB3HS0_ID = 812,\n\tFN_RTS1_N___7 = 813,\n\tFN_SDA2_A___5 = 814,\n\tFN_FMCLK_C___4 = 815,\n\tFN_USB0_ID = 816,\n\tFN_IP8_31_28___6 = 817,\n\tFN_SD1_DAT0___4 = 818,\n\tFN_NFWP_N_B___4 = 819,\n\tFN_IP9_31_28___6 = 820,\n\tFN_SD3_DAT2___4 = 821,\n\tFN_NFDATA2___5 = 822,\n\tFN_IP10_31_28___5 = 823,\n\tFN_SD0_WP___4 = 824,\n\tFN_NFRB_N_A___4 = 825,\n\tFN_SD3_WP___4 = 826,\n\tFN_RIF0_D0_B___4 = 827,\n\tFN_SDA2_B___5 = 828,\n\tFN_TCLK2_A___7 = 829,\n\tFN_SSI_WS2_B___4 = 830,\n\tFN_TS_SDAT0 = 831,\n\tFN_IP11_31_28___5 = 832,\n\tFN_RX1___2 = 833,\n\tFN_HRX2_B___4 = 834,\n\tFN_SSI_SCK9_B___4 = 835,\n\tFN_AUDIO_CLKOUT1_B___4 = 836,\n\tFN_IP12_3_0___5 = 837,\n\tFN_TX1___2 = 838,\n\tFN_HTX2_B___4 = 839,\n\tFN_SSI_WS9_B___4 = 840,\n\tFN_AUDIO_CLKOUT3_B___4 = 841,\n\tFN_IP13_3_0___5 = 842,\n\tFN_MSIOF0_SS1___8 = 843,\n\tFN_HRX2_A___4 = 844,\n\tFN_SSI_SCK4___4 = 845,\n\tFN_HCTS0_N_A___2 = 846,\n\tFN_BPFCLK_C___4 = 847,\n\tFN_SPEEDIN_A___5 = 848,\n\tFN_IP14_3_0___4 = 849,\n\tFN_SSI_SDATA0___4 = 850,\n\tFN_IP15_3_0___4 = 851,\n\tFN_SSI_WS5___4 = 852,\n\tFN_HTX0_B___2 = 853,\n\tFN_USB0_OVC_B = 854,\n\tFN_SDA2_D = 855,\n\tFN_IP12_7_4___5 = 856,\n\tFN_SCK2_A = 857,\n\tFN_HSCK0_A___2 = 858,\n\tFN_AUDIO_CLKB_A___4 = 859,\n\tFN_CTS1_N___7 = 860,\n\tFN_RIF0_CLK_A___4 = 861,\n\tFN_REMOCON_A___4 = 862,\n\tFN_SCIF_CLK_B___5 = 863,\n\tFN_IP13_7_4___5 = 864,\n\tFN_MSIOF0_SS2___8 = 865,\n\tFN_HTX2_A___4 = 866,\n\tFN_SSI_WS4___4 = 867,\n\tFN_HRTS0_N_A___2 = 868,\n\tFN_FMIN_C___4 = 869,\n\tFN_BPFCLK_A___4 = 870,\n\tFN_IP14_7_4___4 = 871,\n\tFN_SSI_SDATA1 = 872,\n\tFN_AUDIO_CLKC_B___4 = 873,\n\tFN_PWM0_B___3 = 874,\n\tFN_IP15_7_4___4 = 875,\n\tFN_SSI_SDATA5___4 = 876,\n\tFN_HSCK0_B___2 = 877,\n\tFN_AUDIO_CLKB_C = 878,\n\tFN_TPU0TO0___5 = 879,\n\tFN_IP12_11_8___5 = 880,\n\tFN_TX2_A___4 = 881,\n\tFN_HRX0_A___2 = 882,\n\tFN_AUDIO_CLKOUT2_A___4 = 883,\n\tFN_SCL1_A___4 = 884,\n\tFN_FSO_CFE_0_N_A___2 = 885,\n\tFN_TS_SDEN1 = 886,\n\tFN_IP13_11_8___4 = 887,\n\tFN_SSI_SDATA9 = 888,\n\tFN_AUDIO_CLKC_A___4 = 889,\n\tFN_SCK1___6 = 890,\n\tFN_IP14_11_8___4 = 891,\n\tFN_SSI_SDATA2 = 892,\n\tFN_AUDIO_CLKOUT2_B___4 = 893,\n\tFN_SSI_SCK9_A___4 = 894,\n\tFN_PWM1_B___7 = 895,\n\tFN_IP15_11_8___4 = 896,\n\tFN_SSI_SCK6___4 = 897,\n\tFN_HSCK2_A___4 = 898,\n\tFN_AUDIO_CLKC_C = 899,\n\tFN_TPU0TO1___5 = 900,\n\tFN_FSO_CFE_0_N_B___2 = 901,\n\tFN_SIM0_RST_B___4 = 902,\n\tFN_IP12_15_12___5 = 903,\n\tFN_RX2_A___4 = 904,\n\tFN_HTX0_A___2 = 905,\n\tFN_AUDIO_CLKOUT3_A___4 = 906,\n\tFN_SDA1_A___4 = 907,\n\tFN_FSO_CFE_1_N_A___2 = 908,\n\tFN_TS_SPSYNC1 = 909,\n\tFN_IP13_15_12___4 = 910,\n\tFN_MLB_CLK___5 = 911,\n\tFN_RX0_B___2 = 912,\n\tFN_RIF0_D0_A___4 = 913,\n\tFN_SCL1_B___4 = 914,\n\tFN_TCLK1_B___7 = 915,\n\tFN_SIM0_RST_A___4 = 916,\n\tFN_IP14_15_12___4 = 917,\n\tFN_SSI_SCK349___4 = 918,\n\tFN_PWM2_C___2 = 919,\n\tFN_IP15_15_12___4 = 920,\n\tFN_SSI_WS6___4 = 921,\n\tFN_HCTS2_N_A___4 = 922,\n\tFN_AUDIO_CLKOUT2_C = 923,\n\tFN_TPU0TO2___5 = 924,\n\tFN_SDA1_D = 925,\n\tFN_FSO_CFE_1_N_B___2 = 926,\n\tFN_SIM0_D_B___4 = 927,\n\tFN_IP12_19_16___5 = 928,\n\tFN_MSIOF0_SCK___8 = 929,\n\tFN_SSI_SCK78___4 = 930,\n\tFN_IP13_19_16___4 = 931,\n\tFN_MLB_SIG___5 = 932,\n\tFN_SCK0_B___2 = 933,\n\tFN_RIF0_D1_A___4 = 934,\n\tFN_SDA1_B___4 = 935,\n\tFN_TCLK2_B___7 = 936,\n\tFN_SIM0_D_A___4 = 937,\n\tFN_IP14_19_16___4 = 938,\n\tFN_SSI_WS349___4 = 939,\n\tFN_PWM3_C___2 = 940,\n\tFN_IP15_19_16___4 = 941,\n\tFN_SSI_SDATA6___4 = 942,\n\tFN_HRTS2_N_A___4 = 943,\n\tFN_AUDIO_CLKOUT3_C = 944,\n\tFN_TPU0TO3___5 = 945,\n\tFN_SCL1_D = 946,\n\tFN_FSO_TOE_N_B___2 = 947,\n\tFN_SIM0_CLK_B___4 = 948,\n\tFN_IP12_23_20___5 = 949,\n\tFN_MSIOF0_RXD___8 = 950,\n\tFN_SSI_WS78___4 = 951,\n\tFN_TX2_B___4 = 952,\n\tFN_IP13_23_20___4 = 953,\n\tFN_MLB_DAT___5 = 954,\n\tFN_TX0_B___2 = 955,\n\tFN_RIF0_SYNC_A___4 = 956,\n\tFN_SIM0_CLK_A___4 = 957,\n\tFN_IP14_23_20___4 = 958,\n\tFN_SSI_SDATA3___5 = 959,\n\tFN_AUDIO_CLKOUT1_C = 960,\n\tFN_AUDIO_CLKB_B___4 = 961,\n\tFN_PWM4_B___5 = 962,\n\tFN_IP15_23_20___4 = 963,\n\tFN_AUDIO_CLKA___2 = 964,\n\tFN_IP12_27_24___5 = 965,\n\tFN_MSIOF0_TXD___8 = 966,\n\tFN_SSI_SDATA7___4 = 967,\n\tFN_RX2_B___4 = 968,\n\tFN_IP13_27_24___4 = 969,\n\tFN_SSI_SCK01239___4 = 970,\n\tFN_IP14_27_24___4 = 971,\n\tFN_SSI_SDATA4___4 = 972,\n\tFN_SSI_WS9_A___4 = 973,\n\tFN_PWM5_B___4 = 974,\n\tFN_IP15_27_24___4 = 975,\n\tFN_USB30_PWEN___4 = 976,\n\tFN_USB0_PWEN_A = 977,\n\tFN_IP12_31_28___5 = 978,\n\tFN_MSIOF0_SYNC___8 = 979,\n\tFN_AUDIO_CLKOUT_B___4 = 980,\n\tFN_SSI_SDATA8___4 = 981,\n\tFN_IP13_31_28___4 = 982,\n\tFN_SSI_WS01239___4 = 983,\n\tFN_IP14_31_28___4 = 984,\n\tFN_SSI_SCK5___4 = 985,\n\tFN_HRX0_B___2 = 986,\n\tFN_USB0_PWEN_B = 987,\n\tFN_SCL2_D = 988,\n\tFN_PWM6_B___4 = 989,\n\tFN_IP15_31_28___4 = 990,\n\tFN_USB30_OVC___4 = 991,\n\tFN_USB0_OVC_A = 992,\n\tFN_FSO_TOE_N_A___2 = 993,\n\tFN_SEL_SIMCARD_0___4 = 994,\n\tFN_SEL_SIMCARD_1___4 = 995,\n\tFN_SEL_ADGB_0___4 = 996,\n\tFN_SEL_ADGB_2 = 997,\n\tFN_SEL_ADGB_1___4 = 998,\n\tFN_SEL_SSI2_0___4 = 999,\n\tFN_SEL_SSI2_1___4 = 1000,\n\tFN_SEL_TIMER_TMU_0___3 = 1001,\n\tFN_SEL_TIMER_TMU_1___3 = 1002,\n\tFN_SEL_DRIF0_0___4 = 1003,\n\tFN_SEL_DRIF0_1___4 = 1004,\n\tFN_SEL_USB_20_CH0_0 = 1005,\n\tFN_SEL_USB_20_CH0_1 = 1006,\n\tFN_SEL_FM_0___4 = 1007,\n\tFN_SEL_FM_2___4 = 1008,\n\tFN_SEL_FM_1___4 = 1009,\n\tFN_SEL_DRIF2_0___4 = 1010,\n\tFN_SEL_DRIF2_1___4 = 1011,\n\tFN_SEL_FSO_0 = 1012,\n\tFN_SEL_FSO_1 = 1013,\n\tFN_SEL_DRIF3_0___4 = 1014,\n\tFN_SEL_DRIF3_1___4 = 1015,\n\tFN_SEL_HSCIF0_0___2 = 1016,\n\tFN_SEL_HSCIF0_1___2 = 1017,\n\tFN_SEL_HSCIF3_0___5 = 1018,\n\tFN_SEL_HSCIF3_4 = 1019,\n\tFN_SEL_HSCIF3_2___4 = 1020,\n\tFN_SEL_HSCIF3_1___5 = 1021,\n\tFN_SEL_HSCIF3_3___4 = 1022,\n\tFN_SEL_HSCIF1_0___4 = 1023,\n\tFN_SEL_HSCIF1_1___4 = 1024,\n\tFN_SEL_HSCIF2_0___4 = 1025,\n\tFN_SEL_HSCIF2_1___4 = 1026,\n\tFN_SEL_I2C1_0___5 = 1027,\n\tFN_SEL_I2C1_2 = 1028,\n\tFN_SEL_I2C1_1___4 = 1029,\n\tFN_SEL_I2C1_3___2 = 1030,\n\tFN_SEL_HSCIF4_0___4 = 1031,\n\tFN_SEL_HSCIF4_4 = 1032,\n\tFN_SEL_HSCIF4_2 = 1033,\n\tFN_SEL_HSCIF4_1___4 = 1034,\n\tFN_SEL_HSCIF4_3 = 1035,\n\tFN_SEL_I2C2_0___6 = 1036,\n\tFN_SEL_I2C2_4 = 1037,\n\tFN_SEL_I2C2_2 = 1038,\n\tFN_SEL_I2C2_1___5 = 1039,\n\tFN_SEL_I2C2_3___2 = 1040,\n\tFN_SEL_I2C6_0___4 = 1041,\n\tFN_SEL_I2C6_1___4 = 1042,\n\tFN_SEL_I2C7_0 = 1043,\n\tFN_SEL_I2C7_1 = 1044,\n\tFN_SEL_NDF_0___3 = 1045,\n\tFN_SEL_NDF_1___3 = 1046,\n\tFN_SEL_MSIOF2_0___5 = 1047,\n\tFN_SEL_MSIOF2_1___5 = 1048,\n\tFN_SEL_PWM0_0___3 = 1049,\n\tFN_SEL_PWM0_1___3 = 1050,\n\tFN_SEL_MSIOF3_0___5 = 1051,\n\tFN_SEL_MSIOF3_1___5 = 1052,\n\tFN_SEL_PWM1_0___6 = 1053,\n\tFN_SEL_PWM1_1___6 = 1054,\n\tFN_SEL_SCIF3_0___5 = 1055,\n\tFN_SEL_SCIF3_2 = 1056,\n\tFN_SEL_SCIF3_1___5 = 1057,\n\tFN_SEL_PWM2_0___6 = 1058,\n\tFN_SEL_PWM2_2___2 = 1059,\n\tFN_SEL_PWM2_1___6 = 1060,\n\tFN_SEL_SCIF4_0___5 = 1061,\n\tFN_SEL_SCIF4_2___4 = 1062,\n\tFN_SEL_SCIF4_1___5 = 1063,\n\tFN_SEL_PWM3_0___6 = 1064,\n\tFN_SEL_PWM3_2___2 = 1065,\n\tFN_SEL_PWM3_1___6 = 1066,\n\tFN_SEL_SCIF5_0___5 = 1067,\n\tFN_SEL_SCIF5_2 = 1068,\n\tFN_SEL_SCIF5_1___5 = 1069,\n\tFN_SEL_PWM4_0___5 = 1070,\n\tFN_SEL_PWM4_1___5 = 1071,\n\tFN_SEL_PWM5_0___4 = 1072,\n\tFN_SEL_PWM5_1___4 = 1073,\n\tFN_SEL_VIN4_0___4 = 1074,\n\tFN_SEL_VIN4_1___4 = 1075,\n\tFN_SEL_PWM6_0___4 = 1076,\n\tFN_SEL_PWM6_1___4 = 1077,\n\tFN_SEL_VIN5_0 = 1078,\n\tFN_SEL_VIN5_1 = 1079,\n\tFN_SEL_REMOCON_0___4 = 1080,\n\tFN_SEL_REMOCON_2 = 1081,\n\tFN_SEL_REMOCON_1___4 = 1082,\n\tFN_SEL_ADGC_0___4 = 1083,\n\tFN_SEL_ADGC_2 = 1084,\n\tFN_SEL_ADGC_1___4 = 1085,\n\tFN_SEL_SCIF_0___4 = 1086,\n\tFN_SEL_SCIF_1___4 = 1087,\n\tFN_SEL_SSI9_0___4 = 1088,\n\tFN_SEL_SSI9_1___4 = 1089,\n\tFN_SEL_SCIF0_0___2 = 1090,\n\tFN_SEL_SCIF0_1___2 = 1091,\n\tFN_SEL_SCIF2_0___4 = 1092,\n\tFN_SEL_SCIF2_1___4 = 1093,\n\tFN_SEL_SPEED_PULSE_IF_0 = 1094,\n\tFN_SEL_SPEED_PULSE_IF_2 = 1095,\n\tFN_SEL_SPEED_PULSE_IF_1 = 1096,\n\tPINMUX_FUNCTION_END___8 = 1097,\n\tPINMUX_MARK_BEGIN___8 = 1098,\n\tAVB_PHY_INT_MARK___5 = 1099,\n\tCLKOUT_MARK___5 = 1100,\n\tAVB_RD3_MARK___5 = 1101,\n\tAVB_RXC_MARK___5 = 1102,\n\tAVB_RX_CTL_MARK___5 = 1103,\n\tQSPI0_SSL_MARK___8 = 1104,\n\tIP0_3_0_MARK___6 = 1105,\n\tQSPI0_SPCLK_MARK___8 = 1106,\n\tHSCK4_A_MARK = 1107,\n\tIP1_3_0_MARK___6 = 1108,\n\tQSPI1_IO2_MARK___8 = 1109,\n\tRIF2_D1_A_MARK___4 = 1110,\n\tHTX3_C_MARK___4 = 1111,\n\tVI4_DATA3_A_MARK___4 = 1112,\n\tIP2_3_0_MARK___6 = 1113,\n\tAVB_TXCREFCLK_MARK___5 = 1114,\n\tIP3_3_0_MARK___6 = 1115,\n\tA1_MARK___5 = 1116,\n\tIRQ1_MARK___6 = 1117,\n\tPWM3_A_MARK___7 = 1118,\n\tDU_DOTCLKIN1_MARK___5 = 1119,\n\tVI5_DATA0_A_MARK = 1120,\n\tDU_DISP_CDE_MARK___2 = 1121,\n\tSDA6_B_MARK___4 = 1122,\n\tIETX_MARK = 1123,\n\tQCPV_QDE_MARK___5 = 1124,\n\tIP0_7_4_MARK___6 = 1125,\n\tQSPI0_MOSI_IO0_MARK___8 = 1126,\n\tHCTS4_N_A_MARK = 1127,\n\tIP1_7_4_MARK___6 = 1128,\n\tQSPI1_IO3_MARK___8 = 1129,\n\tRIF3_CLK_A_MARK___4 = 1130,\n\tHRX3_C_MARK___4 = 1131,\n\tVI4_DATA4_A_MARK___4 = 1132,\n\tIP2_7_4_MARK___6 = 1133,\n\tAVB_MDIO_MARK___5 = 1134,\n\tIP3_7_4_MARK___6 = 1135,\n\tA2_MARK___5 = 1136,\n\tIRQ2_MARK___6 = 1137,\n\tAVB_AVTP_PPS_MARK___5 = 1138,\n\tVI4_CLKENB_MARK___5 = 1139,\n\tVI5_DATA1_A_MARK = 1140,\n\tDU_DISP_MARK___6 = 1141,\n\tSCL6_B_MARK___4 = 1142,\n\tQSTVB_QVE_MARK___5 = 1143,\n\tIP0_11_8_MARK___6 = 1144,\n\tQSPI0_MISO_IO1_MARK___8 = 1145,\n\tHRTS4_N_A_MARK = 1146,\n\tIP1_11_8_MARK___6 = 1147,\n\tQSPI1_SSL_MARK___8 = 1148,\n\tRIF3_SYNC_A_MARK___4 = 1149,\n\tHSCK3_C_MARK = 1150,\n\tVI4_DATA5_A_MARK___4 = 1151,\n\tIP2_11_8_MARK___6 = 1152,\n\tAVB_MDC_MARK___5 = 1153,\n\tIP3_11_8_MARK___6 = 1154,\n\tA3_MARK___5 = 1155,\n\tCTS4_N_A_MARK___4 = 1156,\n\tPWM4_A_MARK___5 = 1157,\n\tVI4_DATA12_MARK___5 = 1158,\n\tDU_DOTCLKOUT0_MARK___5 = 1159,\n\tHTX3_D_MARK___4 = 1160,\n\tIECLK_MARK = 1161,\n\tLCDOUT12_MARK___5 = 1162,\n\tIP0_15_12_MARK___6 = 1163,\n\tQSPI0_IO2_MARK___8 = 1164,\n\tHTX4_A_MARK___4 = 1165,\n\tIP1_15_12_MARK___6 = 1166,\n\tRPC_INT_N_MARK___5 = 1167,\n\tRIF3_D0_A_MARK___4 = 1168,\n\tHCTS3_N_C_MARK = 1169,\n\tVI4_DATA6_A_MARK___4 = 1170,\n\tIP2_15_12_MARK___6 = 1171,\n\tBS_N_MARK___5 = 1172,\n\tPWM0_A_MARK___3 = 1173,\n\tAVB_MAGIC_MARK___5 = 1174,\n\tVI4_CLK_MARK___5 = 1175,\n\tTX3_C_MARK = 1176,\n\tVI5_CLK_B_MARK = 1177,\n\tIP3_15_12_MARK___6 = 1178,\n\tA4_MARK___5 = 1179,\n\tRTS4_N_A_MARK___4 = 1180,\n\tMSIOF3_SYNC_B_MARK___5 = 1181,\n\tVI4_DATA8_MARK___5 = 1182,\n\tPWM2_B_MARK___6 = 1183,\n\tDU_DG4_MARK___6 = 1184,\n\tRIF2_CLK_B_MARK___4 = 1185,\n\tIP0_19_16_MARK___6 = 1186,\n\tQSPI0_IO3_MARK___8 = 1187,\n\tHRX4_A_MARK___4 = 1188,\n\tIP1_19_16_MARK___6 = 1189,\n\tRPC_RESET_N_MARK___5 = 1190,\n\tRIF3_D1_A_MARK___4 = 1191,\n\tHRTS3_N_C_MARK = 1192,\n\tVI4_DATA7_A_MARK___4 = 1193,\n\tIP2_19_16_MARK___6 = 1194,\n\tRD_N_MARK___5 = 1195,\n\tPWM1_A_MARK___7 = 1196,\n\tAVB_LINK_MARK___5 = 1197,\n\tVI4_FIELD_MARK___5 = 1198,\n\tRX3_C_MARK = 1199,\n\tFSCLKST2_N_A_MARK___3 = 1200,\n\tVI5_DATA0_B_MARK = 1201,\n\tIP3_19_16_MARK___6 = 1202,\n\tA5_MARK___5 = 1203,\n\tSCK4_A_MARK___5 = 1204,\n\tMSIOF3_SCK_B_MARK___5 = 1205,\n\tVI4_DATA9_MARK___5 = 1206,\n\tPWM3_B_MARK___7 = 1207,\n\tRIF2_SYNC_B_MARK___4 = 1208,\n\tQPOLA_MARK___5 = 1209,\n\tIP0_23_20_MARK___6 = 1210,\n\tQSPI1_SPCLK_MARK___8 = 1211,\n\tRIF2_CLK_A_MARK___4 = 1212,\n\tHSCK4_B_MARK = 1213,\n\tVI4_DATA0_A_MARK___4 = 1214,\n\tIP1_23_20_MARK___6 = 1215,\n\tAVB_RD0_MARK___5 = 1216,\n\tIP2_23_20_MARK___6 = 1217,\n\tRD_WR_N_MARK___5 = 1218,\n\tSCL7_A_MARK = 1219,\n\tAVB_AVTP_MATCH_MARK___2 = 1220,\n\tVI4_VSYNC_N_MARK___5 = 1221,\n\tTX5_B_MARK___5 = 1222,\n\tSCK3_C_MARK = 1223,\n\tPWM5_A_MARK___4 = 1224,\n\tIP3_23_20_MARK___6 = 1225,\n\tA6_MARK___5 = 1226,\n\tRX4_A_MARK___5 = 1227,\n\tMSIOF3_RXD_B_MARK___5 = 1228,\n\tVI4_DATA10_MARK___5 = 1229,\n\tRIF2_D0_B_MARK___4 = 1230,\n\tIP0_27_24_MARK___6 = 1231,\n\tQSPI1_MOSI_IO0_MARK___8 = 1232,\n\tRIF2_SYNC_A_MARK___4 = 1233,\n\tHTX4_B_MARK___4 = 1234,\n\tVI4_DATA1_A_MARK___4 = 1235,\n\tIP1_27_24_MARK___6 = 1236,\n\tAVB_RD1_MARK___5 = 1237,\n\tIP2_27_24_MARK___6 = 1238,\n\tEX_WAIT0_MARK___2 = 1239,\n\tSDA7_A_MARK = 1240,\n\tAVB_AVTP_CAPTURE_MARK___2 = 1241,\n\tVI4_HSYNC_N_MARK___5 = 1242,\n\tRX5_B_MARK___5 = 1243,\n\tPWM6_A_MARK___4 = 1244,\n\tIP3_27_24_MARK___6 = 1245,\n\tA7_MARK___5 = 1246,\n\tTX4_A_MARK___5 = 1247,\n\tMSIOF3_TXD_B_MARK___5 = 1248,\n\tVI4_DATA11_MARK___5 = 1249,\n\tRIF2_D1_B_MARK___4 = 1250,\n\tIP0_31_28_MARK___6 = 1251,\n\tQSPI1_MISO_IO1_MARK___8 = 1252,\n\tRIF2_D0_A_MARK___4 = 1253,\n\tHRX4_B_MARK___4 = 1254,\n\tVI4_DATA2_A_MARK___4 = 1255,\n\tIP1_31_28_MARK___6 = 1256,\n\tAVB_RD2_MARK___5 = 1257,\n\tIP2_31_28_MARK___6 = 1258,\n\tA0_MARK___5 = 1259,\n\tIRQ0_MARK___6 = 1260,\n\tPWM2_A_MARK___6 = 1261,\n\tMSIOF3_SS1_B_MARK___5 = 1262,\n\tVI5_CLK_A_MARK = 1263,\n\tDU_CDE_MARK___6 = 1264,\n\tHRX3_D_MARK___4 = 1265,\n\tIERX_MARK = 1266,\n\tQSTB_QHE_MARK___5 = 1267,\n\tIP3_31_28_MARK___6 = 1268,\n\tA8_MARK___5 = 1269,\n\tSDA6_A_MARK___4 = 1270,\n\tRX3_B_MARK___6 = 1271,\n\tHRX4_C_MARK = 1272,\n\tVI5_HSYNC_N_A_MARK = 1273,\n\tDU_HSYNC_MARK___2 = 1274,\n\tVI4_DATA0_B_MARK___4 = 1275,\n\tQSTH_QHS_MARK___5 = 1276,\n\tIP4_3_0_MARK___6 = 1277,\n\tA9_MARK___5 = 1278,\n\tTX5_A_MARK___5 = 1279,\n\tIRQ3_MARK___6 = 1280,\n\tVI4_DATA16_MARK___5 = 1281,\n\tVI5_VSYNC_N_A_MARK = 1282,\n\tDU_DG7_MARK___6 = 1283,\n\tLCDOUT15_MARK___5 = 1284,\n\tIP5_3_0_MARK___6 = 1285,\n\tA17_MARK___5 = 1286,\n\tMSIOF1_RXD_MARK___5 = 1287,\n\tVI4_DATA20_MARK___5 = 1288,\n\tVI5_DATA6_A_MARK = 1289,\n\tDU_DB6_MARK___6 = 1290,\n\tLCDOUT6_MARK___5 = 1291,\n\tIP6_3_0_MARK___6 = 1292,\n\tD3_MARK___5 = 1293,\n\tMSIOF3_TXD_A_MARK___5 = 1294,\n\tTX5_C_MARK = 1295,\n\tVI5_DATA15_A_MARK = 1296,\n\tDU_DR4_MARK___6 = 1297,\n\tTX4_C_MARK___4 = 1298,\n\tLCDOUT20_MARK___5 = 1299,\n\tIP7_3_0_MARK___6 = 1300,\n\tD11_MARK___5 = 1301,\n\tMSIOF2_TXD_A_MARK___4 = 1302,\n\tVI5_DATA11_A_MARK = 1303,\n\tDU_DG2_MARK___6 = 1304,\n\tRIF3_D1_B_MARK___4 = 1305,\n\tHRTS3_N_E_MARK = 1306,\n\tLCDOUT10_MARK___5 = 1307,\n\tIP4_7_4_MARK___6 = 1308,\n\tA10_MARK___5 = 1309,\n\tIRQ4_MARK___6 = 1310,\n\tMSIOF2_SYNC_B_MARK___5 = 1311,\n\tVI4_DATA13_MARK___5 = 1312,\n\tVI5_FIELD_A_MARK = 1313,\n\tDU_DG5_MARK___6 = 1314,\n\tFSCLKST2_N_B_MARK___3 = 1315,\n\tLCDOUT13_MARK___5 = 1316,\n\tIP5_7_4_MARK___6 = 1317,\n\tA18_MARK___5 = 1318,\n\tMSIOF1_TXD_MARK___5 = 1319,\n\tVI4_DATA21_MARK___5 = 1320,\n\tVI5_DATA7_A_MARK = 1321,\n\tDU_DB0_MARK___6 = 1322,\n\tHRX4_E_MARK = 1323,\n\tLCDOUT0_MARK___5 = 1324,\n\tIP6_7_4_MARK___6 = 1325,\n\tD4_MARK___5 = 1326,\n\tCANFD1_TX_MARK___7 = 1327,\n\tHSCK3_B_MARK___3 = 1328,\n\tCAN1_TX_MARK___4 = 1329,\n\tRTS3_N_A_MARK___2 = 1330,\n\tMSIOF3_SS2_A_MARK___5 = 1331,\n\tVI5_DATA1_B_MARK = 1332,\n\tIP7_7_4_MARK___6 = 1333,\n\tD12_MARK___5 = 1334,\n\tCANFD0_TX_MARK___3 = 1335,\n\tTX4_B_MARK___5 = 1336,\n\tCAN0_TX_MARK = 1337,\n\tVI5_DATA8_A_MARK = 1338,\n\tVI5_DATA3_B_MARK = 1339,\n\tIP4_11_8_MARK___6 = 1340,\n\tA11_MARK___5 = 1341,\n\tSCL6_A_MARK___4 = 1342,\n\tTX3_B_MARK___6 = 1343,\n\tHTX4_C_MARK = 1344,\n\tDU_VSYNC_MARK___2 = 1345,\n\tVI4_DATA1_B_MARK___4 = 1346,\n\tQSTVA_QVS_MARK___5 = 1347,\n\tIP5_11_8_MARK___6 = 1348,\n\tA19_MARK___5 = 1349,\n\tMSIOF1_SCK_MARK___5 = 1350,\n\tVI4_DATA22_MARK___5 = 1351,\n\tVI5_DATA2_A_MARK = 1352,\n\tDU_DB1_MARK___6 = 1353,\n\tHTX4_E_MARK = 1354,\n\tLCDOUT1_MARK___5 = 1355,\n\tIP6_11_8_MARK___6 = 1356,\n\tD5_MARK___5 = 1357,\n\tRX3_A_MARK___6 = 1358,\n\tHRX3_B_MARK___6 = 1359,\n\tDU_DR5_MARK___6 = 1360,\n\tVI4_DATA4_B_MARK___4 = 1361,\n\tLCDOUT21_MARK___5 = 1362,\n\tIP7_11_8_MARK___6 = 1363,\n\tD13_MARK___5 = 1364,\n\tCANFD0_RX_MARK___3 = 1365,\n\tRX4_B_MARK___5 = 1366,\n\tCAN0_RX_MARK = 1367,\n\tVI5_DATA9_A_MARK = 1368,\n\tSCL7_B_MARK = 1369,\n\tVI5_DATA4_B_MARK = 1370,\n\tIP4_15_12_MARK___6 = 1371,\n\tA12_MARK___5 = 1372,\n\tRX5_A_MARK___5 = 1373,\n\tMSIOF2_SS2_B_MARK___4 = 1374,\n\tVI4_DATA17_MARK___5 = 1375,\n\tVI5_DATA3_A_MARK = 1376,\n\tDU_DG6_MARK___6 = 1377,\n\tLCDOUT14_MARK___5 = 1378,\n\tIP5_15_12_MARK___6 = 1379,\n\tCS0_N_MARK___5 = 1380,\n\tSCL5_MARK___7 = 1381,\n\tDU_DR0_MARK___6 = 1382,\n\tVI4_DATA2_B_MARK___4 = 1383,\n\tLCDOUT16_MARK___5 = 1384,\n\tIP6_15_12_MARK___6 = 1385,\n\tD6_MARK___5 = 1386,\n\tTX3_A_MARK___6 = 1387,\n\tHTX3_B_MARK___6 = 1388,\n\tDU_DR6_MARK___6 = 1389,\n\tVI4_DATA5_B_MARK___4 = 1390,\n\tLCDOUT22_MARK___5 = 1391,\n\tIP7_15_12_MARK___3 = 1392,\n\tD14_MARK___5 = 1393,\n\tCAN_CLK_MARK___6 = 1394,\n\tHRX3_A_MARK___6 = 1395,\n\tMSIOF2_SS2_A_MARK___4 = 1396,\n\tSDA7_B_MARK = 1397,\n\tVI5_DATA5_B_MARK = 1398,\n\tIP4_19_16_MARK___6 = 1399,\n\tA13_MARK___5 = 1400,\n\tSCK5_A_MARK___5 = 1401,\n\tMSIOF2_SCK_B_MARK___4 = 1402,\n\tVI4_DATA14_MARK___5 = 1403,\n\tHRX4_D_MARK = 1404,\n\tDU_DB2_MARK___6 = 1405,\n\tLCDOUT2_MARK___5 = 1406,\n\tIP5_19_16_MARK___6 = 1407,\n\tWE0_N_MARK___5 = 1408,\n\tSDA5_MARK___7 = 1409,\n\tDU_DR1_MARK___6 = 1410,\n\tVI4_DATA3_B_MARK___4 = 1411,\n\tLCDOUT17_MARK___5 = 1412,\n\tIP6_19_16_MARK___6 = 1413,\n\tD7_MARK___5 = 1414,\n\tCANFD1_RX_MARK___7 = 1415,\n\tIRQ5_MARK___7 = 1416,\n\tCAN1_RX_MARK___4 = 1417,\n\tCTS3_N_A_MARK___2 = 1418,\n\tVI5_DATA2_B_MARK = 1419,\n\tIP7_19_16_MARK___6 = 1420,\n\tD15_MARK___5 = 1421,\n\tMSIOF2_SS1_A_MARK___4 = 1422,\n\tHTX3_A_MARK___6 = 1423,\n\tMSIOF3_SS1_A_MARK___5 = 1424,\n\tDU_DG3_MARK___6 = 1425,\n\tLCDOUT11_MARK___5 = 1426,\n\tIP4_23_20_MARK___6 = 1427,\n\tA14_MARK___5 = 1428,\n\tMSIOF1_SS1_MARK___5 = 1429,\n\tMSIOF2_RXD_B_MARK___4 = 1430,\n\tVI4_DATA15_MARK___5 = 1431,\n\tHTX4_D_MARK = 1432,\n\tDU_DB3_MARK___6 = 1433,\n\tLCDOUT3_MARK___5 = 1434,\n\tIP5_23_20_MARK___6 = 1435,\n\tD0_MARK___5 = 1436,\n\tMSIOF3_SCK_A_MARK___5 = 1437,\n\tDU_DR2_MARK___6 = 1438,\n\tCTS4_N_C_MARK___4 = 1439,\n\tLCDOUT18_MARK___5 = 1440,\n\tIP6_23_20_MARK___6 = 1441,\n\tD8_MARK___5 = 1442,\n\tMSIOF2_SCK_A_MARK___4 = 1443,\n\tSCK4_B_MARK___5 = 1444,\n\tVI5_DATA12_A_MARK = 1445,\n\tDU_DR7_MARK___6 = 1446,\n\tRIF3_CLK_B_MARK___4 = 1447,\n\tHCTS3_N_E_MARK = 1448,\n\tLCDOUT23_MARK___5 = 1449,\n\tIP7_23_20_MARK___6 = 1450,\n\tSCL4_MARK___4 = 1451,\n\tCS1_N_A26_MARK = 1452,\n\tDU_DOTCLKIN0_MARK___4 = 1453,\n\tVI4_DATA6_B_MARK___4 = 1454,\n\tVI5_DATA6_B_MARK = 1455,\n\tQCLK_MARK___5 = 1456,\n\tIP4_27_24_MARK___6 = 1457,\n\tA15_MARK___5 = 1458,\n\tMSIOF1_SS2_MARK___5 = 1459,\n\tMSIOF2_TXD_B_MARK___4 = 1460,\n\tVI4_DATA18_MARK___5 = 1461,\n\tVI5_DATA4_A_MARK = 1462,\n\tDU_DB4_MARK___6 = 1463,\n\tLCDOUT4_MARK___5 = 1464,\n\tIP5_27_24_MARK___6 = 1465,\n\tD1_MARK___5 = 1466,\n\tMSIOF3_SYNC_A_MARK___5 = 1467,\n\tSCK3_A_MARK___3 = 1468,\n\tVI4_DATA23_MARK___5 = 1469,\n\tVI5_CLKENB_A_MARK = 1470,\n\tDU_DB7_MARK___6 = 1471,\n\tRTS4_N_C_MARK___4 = 1472,\n\tLCDOUT7_MARK___5 = 1473,\n\tIP6_27_24_MARK___6 = 1474,\n\tD9_MARK___5 = 1475,\n\tMSIOF2_SYNC_A_MARK___5 = 1476,\n\tVI5_DATA10_A_MARK = 1477,\n\tDU_DG0_MARK___6 = 1478,\n\tRIF3_SYNC_B_MARK___4 = 1479,\n\tHRX3_E_MARK = 1480,\n\tLCDOUT8_MARK___5 = 1481,\n\tIP7_27_24_MARK___6 = 1482,\n\tSDA4_MARK___4 = 1483,\n\tWE1_N_MARK___5 = 1484,\n\tVI4_DATA7_B_MARK___4 = 1485,\n\tVI5_DATA7_B_MARK = 1486,\n\tQPOLB_MARK___5 = 1487,\n\tIP4_31_28_MARK___6 = 1488,\n\tA16_MARK___5 = 1489,\n\tMSIOF1_SYNC_MARK___5 = 1490,\n\tMSIOF2_SS1_B_MARK___4 = 1491,\n\tVI4_DATA19_MARK___5 = 1492,\n\tVI5_DATA5_A_MARK = 1493,\n\tDU_DB5_MARK___6 = 1494,\n\tLCDOUT5_MARK___5 = 1495,\n\tIP5_31_28_MARK___6 = 1496,\n\tD2_MARK___5 = 1497,\n\tMSIOF3_RXD_A_MARK___5 = 1498,\n\tRX5_C_MARK = 1499,\n\tVI5_DATA14_A_MARK = 1500,\n\tDU_DR3_MARK___6 = 1501,\n\tRX4_C_MARK___4 = 1502,\n\tLCDOUT19_MARK___5 = 1503,\n\tIP6_31_28_MARK___6 = 1504,\n\tD10_MARK___5 = 1505,\n\tMSIOF2_RXD_A_MARK___4 = 1506,\n\tVI5_DATA13_A_MARK = 1507,\n\tDU_DG1_MARK___6 = 1508,\n\tRIF3_D0_B_MARK___4 = 1509,\n\tHTX3_E_MARK = 1510,\n\tLCDOUT9_MARK___5 = 1511,\n\tIP7_31_28_MARK___6 = 1512,\n\tSD0_CLK_MARK___4 = 1513,\n\tNFDATA8_MARK___5 = 1514,\n\tSCL1_C_MARK = 1515,\n\tHSCK1_B_MARK___5 = 1516,\n\tSDA2_E_MARK = 1517,\n\tFMCLK_B_MARK___4 = 1518,\n\tIP8_3_0_MARK___6 = 1519,\n\tSD0_CMD_MARK___4 = 1520,\n\tNFDATA9_MARK___5 = 1521,\n\tHRX1_B_MARK___5 = 1522,\n\tSPEEDIN_B_MARK___5 = 1523,\n\tIP9_3_0_MARK___6 = 1524,\n\tSD1_DAT1_MARK___4 = 1525,\n\tNFCE_N_B_MARK___4 = 1526,\n\tIP10_3_0_MARK___6 = 1527,\n\tSD3_DAT3_MARK___4 = 1528,\n\tNFDATA3_MARK___5 = 1529,\n\tIP11_3_0_MARK___5 = 1530,\n\tSD1_CD_MARK___4 = 1531,\n\tNFCE_N_A_MARK___4 = 1532,\n\tSSI_SCK1_MARK = 1533,\n\tRIF0_D1_B_MARK___4 = 1534,\n\tTS_SDEN0_MARK = 1535,\n\tIP8_7_4_MARK___6 = 1536,\n\tSD0_DAT0_MARK___4 = 1537,\n\tNFDATA10_MARK___5 = 1538,\n\tHTX1_B_MARK___5 = 1539,\n\tREMOCON_B_MARK___4 = 1540,\n\tIP9_7_4_MARK___6 = 1541,\n\tSD1_DAT2_MARK___4 = 1542,\n\tNFALE_B_MARK = 1543,\n\tIP10_7_4_MARK___6 = 1544,\n\tSD3_DAT4_MARK___4 = 1545,\n\tNFDATA4_MARK___5 = 1546,\n\tIP11_7_4_MARK___5 = 1547,\n\tSD1_WP_MARK___4 = 1548,\n\tNFWP_N_A_MARK___4 = 1549,\n\tSSI_WS1_MARK = 1550,\n\tRIF0_SYNC_B_MARK___4 = 1551,\n\tTS_SPSYNC0_MARK = 1552,\n\tIP8_11_8_MARK___6 = 1553,\n\tSD0_DAT1_MARK___4 = 1554,\n\tNFDATA11_MARK___5 = 1555,\n\tSDA2_C_MARK = 1556,\n\tHCTS1_N_B_MARK___5 = 1557,\n\tFMIN_B_MARK___4 = 1558,\n\tIP9_11_8_MARK___6 = 1559,\n\tSD1_DAT3_MARK___4 = 1560,\n\tNFRB_N_B_MARK___4 = 1561,\n\tIP10_11_8_MARK___6 = 1562,\n\tSD3_DAT5_MARK___4 = 1563,\n\tNFDATA5_MARK___5 = 1564,\n\tIP11_11_8_MARK___5 = 1565,\n\tRX0_A_MARK___2 = 1566,\n\tHRX1_A_MARK___5 = 1567,\n\tSSI_SCK2_A_MARK___4 = 1568,\n\tRIF1_SYNC_MARK = 1569,\n\tTS_SCK1_MARK = 1570,\n\tIP8_15_12_MARK___6 = 1571,\n\tSD0_DAT2_MARK___4 = 1572,\n\tNFDATA12_MARK___5 = 1573,\n\tSCL2_C_MARK = 1574,\n\tHRTS1_N_B_MARK___5 = 1575,\n\tBPFCLK_B_MARK___4 = 1576,\n\tIP9_15_12_MARK___6 = 1577,\n\tSD3_CLK_MARK___4 = 1578,\n\tNFWE_N_MARK___5 = 1579,\n\tIP10_15_12_MARK___6 = 1580,\n\tSD3_DAT6_MARK___4 = 1581,\n\tNFDATA6_MARK___5 = 1582,\n\tIP11_15_12_MARK___5 = 1583,\n\tTX0_A_MARK___2 = 1584,\n\tHTX1_A_MARK___5 = 1585,\n\tSSI_WS2_A_MARK___4 = 1586,\n\tRIF1_D0_MARK = 1587,\n\tTS_SDAT1_MARK = 1588,\n\tIP8_19_16_MARK___6 = 1589,\n\tSD0_DAT3_MARK___4 = 1590,\n\tNFDATA13_MARK___5 = 1591,\n\tSDA1_C_MARK = 1592,\n\tSCL2_E_MARK = 1593,\n\tSPEEDIN_C_MARK = 1594,\n\tREMOCON_C_MARK = 1595,\n\tIP9_19_16_MARK___6 = 1596,\n\tSD3_CMD_MARK___4 = 1597,\n\tNFRE_N_MARK___5 = 1598,\n\tIP10_19_16_MARK___6 = 1599,\n\tSD3_DAT7_MARK___4 = 1600,\n\tNFDATA7_MARK___5 = 1601,\n\tIP11_19_16_MARK___5 = 1602,\n\tCTS0_N_A_MARK = 1603,\n\tNFDATA14_A_MARK___4 = 1604,\n\tAUDIO_CLKOUT_A_MARK___4 = 1605,\n\tRIF1_D1_MARK = 1606,\n\tSCIF_CLK_A_MARK___5 = 1607,\n\tFMCLK_A_MARK___4 = 1608,\n\tIP8_23_20_MARK___6 = 1609,\n\tSD1_CLK_MARK___4 = 1610,\n\tNFDATA14_B_MARK___4 = 1611,\n\tIP9_23_20_MARK___6 = 1612,\n\tSD3_DAT0_MARK___4 = 1613,\n\tNFDATA0_MARK___5 = 1614,\n\tIP10_23_20_MARK___5 = 1615,\n\tSD3_DS_MARK___4 = 1616,\n\tNFCLE_MARK___5 = 1617,\n\tIP11_23_20_MARK___5 = 1618,\n\tRTS0_N_A_MARK = 1619,\n\tNFDATA15_A_MARK___4 = 1620,\n\tAUDIO_CLKOUT1_A_MARK___4 = 1621,\n\tRIF1_CLK_MARK = 1622,\n\tSCL2_A_MARK___5 = 1623,\n\tFMIN_A_MARK___4 = 1624,\n\tIP8_27_24_MARK___6 = 1625,\n\tSD1_CMD_MARK___4 = 1626,\n\tNFDATA15_B_MARK___4 = 1627,\n\tIP9_27_24_MARK___6 = 1628,\n\tSD3_DAT1_MARK___4 = 1629,\n\tNFDATA1_MARK___5 = 1630,\n\tIP10_27_24_MARK___5 = 1631,\n\tSD0_CD_MARK___4 = 1632,\n\tNFALE_A_MARK = 1633,\n\tSD3_CD_MARK___4 = 1634,\n\tRIF0_CLK_B_MARK___4 = 1635,\n\tSCL2_B_MARK___5 = 1636,\n\tTCLK1_A_MARK___7 = 1637,\n\tSSI_SCK2_B_MARK___4 = 1638,\n\tTS_SCK0_MARK = 1639,\n\tIP11_27_24_MARK___5 = 1640,\n\tSCK0_A_MARK___2 = 1641,\n\tHSCK1_A_MARK___5 = 1642,\n\tUSB3HS0_ID_MARK = 1643,\n\tRTS1_N_MARK___7 = 1644,\n\tSDA2_A_MARK___5 = 1645,\n\tFMCLK_C_MARK___4 = 1646,\n\tUSB0_ID_MARK = 1647,\n\tIP8_31_28_MARK___6 = 1648,\n\tSD1_DAT0_MARK___4 = 1649,\n\tNFWP_N_B_MARK___4 = 1650,\n\tIP9_31_28_MARK___6 = 1651,\n\tSD3_DAT2_MARK___4 = 1652,\n\tNFDATA2_MARK___5 = 1653,\n\tIP10_31_28_MARK___5 = 1654,\n\tSD0_WP_MARK___4 = 1655,\n\tNFRB_N_A_MARK___4 = 1656,\n\tSD3_WP_MARK___4 = 1657,\n\tRIF0_D0_B_MARK___4 = 1658,\n\tSDA2_B_MARK___5 = 1659,\n\tTCLK2_A_MARK___7 = 1660,\n\tSSI_WS2_B_MARK___4 = 1661,\n\tTS_SDAT0_MARK = 1662,\n\tIP11_31_28_MARK___5 = 1663,\n\tRX1_MARK___2 = 1664,\n\tHRX2_B_MARK___4 = 1665,\n\tSSI_SCK9_B_MARK___4 = 1666,\n\tAUDIO_CLKOUT1_B_MARK___4 = 1667,\n\tIP12_3_0_MARK___5 = 1668,\n\tTX1_MARK___2 = 1669,\n\tHTX2_B_MARK___4 = 1670,\n\tSSI_WS9_B_MARK___4 = 1671,\n\tAUDIO_CLKOUT3_B_MARK___4 = 1672,\n\tIP13_3_0_MARK___5 = 1673,\n\tMSIOF0_SS1_MARK___8 = 1674,\n\tHRX2_A_MARK___4 = 1675,\n\tSSI_SCK4_MARK___4 = 1676,\n\tHCTS0_N_A_MARK___2 = 1677,\n\tBPFCLK_C_MARK___4 = 1678,\n\tSPEEDIN_A_MARK___5 = 1679,\n\tIP14_3_0_MARK___4 = 1680,\n\tSSI_SDATA0_MARK___4 = 1681,\n\tIP15_3_0_MARK___4 = 1682,\n\tSSI_WS5_MARK___4 = 1683,\n\tHTX0_B_MARK___2 = 1684,\n\tUSB0_OVC_B_MARK = 1685,\n\tSDA2_D_MARK = 1686,\n\tIP12_7_4_MARK___5 = 1687,\n\tSCK2_A_MARK = 1688,\n\tHSCK0_A_MARK___2 = 1689,\n\tAUDIO_CLKB_A_MARK___4 = 1690,\n\tCTS1_N_MARK___7 = 1691,\n\tRIF0_CLK_A_MARK___4 = 1692,\n\tREMOCON_A_MARK___4 = 1693,\n\tSCIF_CLK_B_MARK___5 = 1694,\n\tIP13_7_4_MARK___5 = 1695,\n\tMSIOF0_SS2_MARK___8 = 1696,\n\tHTX2_A_MARK___4 = 1697,\n\tSSI_WS4_MARK___4 = 1698,\n\tHRTS0_N_A_MARK___2 = 1699,\n\tFMIN_C_MARK___4 = 1700,\n\tBPFCLK_A_MARK___4 = 1701,\n\tIP14_7_4_MARK___4 = 1702,\n\tSSI_SDATA1_MARK = 1703,\n\tAUDIO_CLKC_B_MARK___4 = 1704,\n\tPWM0_B_MARK___3 = 1705,\n\tIP15_7_4_MARK___4 = 1706,\n\tSSI_SDATA5_MARK___4 = 1707,\n\tHSCK0_B_MARK___2 = 1708,\n\tAUDIO_CLKB_C_MARK = 1709,\n\tTPU0TO0_MARK___5 = 1710,\n\tIP12_11_8_MARK___5 = 1711,\n\tTX2_A_MARK___4 = 1712,\n\tHRX0_A_MARK___2 = 1713,\n\tAUDIO_CLKOUT2_A_MARK___4 = 1714,\n\tSCL1_A_MARK___4 = 1715,\n\tFSO_CFE_0_N_A_MARK___2 = 1716,\n\tTS_SDEN1_MARK = 1717,\n\tIP13_11_8_MARK___4 = 1718,\n\tSSI_SDATA9_MARK = 1719,\n\tAUDIO_CLKC_A_MARK___4 = 1720,\n\tSCK1_MARK___6 = 1721,\n\tIP14_11_8_MARK___4 = 1722,\n\tSSI_SDATA2_MARK = 1723,\n\tAUDIO_CLKOUT2_B_MARK___4 = 1724,\n\tSSI_SCK9_A_MARK___4 = 1725,\n\tPWM1_B_MARK___7 = 1726,\n\tIP15_11_8_MARK___4 = 1727,\n\tSSI_SCK6_MARK___4 = 1728,\n\tHSCK2_A_MARK___4 = 1729,\n\tAUDIO_CLKC_C_MARK = 1730,\n\tTPU0TO1_MARK___5 = 1731,\n\tFSO_CFE_0_N_B_MARK___2 = 1732,\n\tSIM0_RST_B_MARK___4 = 1733,\n\tIP12_15_12_MARK___5 = 1734,\n\tRX2_A_MARK___4 = 1735,\n\tHTX0_A_MARK___2 = 1736,\n\tAUDIO_CLKOUT3_A_MARK___4 = 1737,\n\tSDA1_A_MARK___4 = 1738,\n\tFSO_CFE_1_N_A_MARK___2 = 1739,\n\tTS_SPSYNC1_MARK = 1740,\n\tIP13_15_12_MARK___4 = 1741,\n\tMLB_CLK_MARK___5 = 1742,\n\tRX0_B_MARK___2 = 1743,\n\tRIF0_D0_A_MARK___4 = 1744,\n\tSCL1_B_MARK___4 = 1745,\n\tTCLK1_B_MARK___7 = 1746,\n\tSIM0_RST_A_MARK___4 = 1747,\n\tIP14_15_12_MARK___4 = 1748,\n\tSSI_SCK349_MARK___4 = 1749,\n\tPWM2_C_MARK___2 = 1750,\n\tIP15_15_12_MARK___4 = 1751,\n\tSSI_WS6_MARK___4 = 1752,\n\tHCTS2_N_A_MARK___4 = 1753,\n\tAUDIO_CLKOUT2_C_MARK = 1754,\n\tTPU0TO2_MARK___5 = 1755,\n\tSDA1_D_MARK = 1756,\n\tFSO_CFE_1_N_B_MARK___2 = 1757,\n\tSIM0_D_B_MARK___4 = 1758,\n\tIP12_19_16_MARK___5 = 1759,\n\tMSIOF0_SCK_MARK___8 = 1760,\n\tSSI_SCK78_MARK___4 = 1761,\n\tIP13_19_16_MARK___4 = 1762,\n\tMLB_SIG_MARK___5 = 1763,\n\tSCK0_B_MARK___2 = 1764,\n\tRIF0_D1_A_MARK___4 = 1765,\n\tSDA1_B_MARK___4 = 1766,\n\tTCLK2_B_MARK___7 = 1767,\n\tSIM0_D_A_MARK___4 = 1768,\n\tIP14_19_16_MARK___4 = 1769,\n\tSSI_WS349_MARK___4 = 1770,\n\tPWM3_C_MARK___2 = 1771,\n\tIP15_19_16_MARK___4 = 1772,\n\tSSI_SDATA6_MARK___4 = 1773,\n\tHRTS2_N_A_MARK___4 = 1774,\n\tAUDIO_CLKOUT3_C_MARK = 1775,\n\tTPU0TO3_MARK___5 = 1776,\n\tSCL1_D_MARK = 1777,\n\tFSO_TOE_N_B_MARK___2 = 1778,\n\tSIM0_CLK_B_MARK___4 = 1779,\n\tIP12_23_20_MARK___5 = 1780,\n\tMSIOF0_RXD_MARK___8 = 1781,\n\tSSI_WS78_MARK___4 = 1782,\n\tTX2_B_MARK___4 = 1783,\n\tIP13_23_20_MARK___4 = 1784,\n\tMLB_DAT_MARK___5 = 1785,\n\tTX0_B_MARK___2 = 1786,\n\tRIF0_SYNC_A_MARK___4 = 1787,\n\tSIM0_CLK_A_MARK___4 = 1788,\n\tIP14_23_20_MARK___4 = 1789,\n\tSSI_SDATA3_MARK___5 = 1790,\n\tAUDIO_CLKOUT1_C_MARK = 1791,\n\tAUDIO_CLKB_B_MARK___4 = 1792,\n\tPWM4_B_MARK___5 = 1793,\n\tIP15_23_20_MARK___4 = 1794,\n\tAUDIO_CLKA_MARK___2 = 1795,\n\tIP12_27_24_MARK___5 = 1796,\n\tMSIOF0_TXD_MARK___8 = 1797,\n\tSSI_SDATA7_MARK___4 = 1798,\n\tRX2_B_MARK___4 = 1799,\n\tIP13_27_24_MARK___4 = 1800,\n\tSSI_SCK01239_MARK___4 = 1801,\n\tIP14_27_24_MARK___4 = 1802,\n\tSSI_SDATA4_MARK___4 = 1803,\n\tSSI_WS9_A_MARK___4 = 1804,\n\tPWM5_B_MARK___4 = 1805,\n\tIP15_27_24_MARK___4 = 1806,\n\tUSB30_PWEN_MARK___4 = 1807,\n\tUSB0_PWEN_A_MARK = 1808,\n\tIP12_31_28_MARK___5 = 1809,\n\tMSIOF0_SYNC_MARK___8 = 1810,\n\tAUDIO_CLKOUT_B_MARK___4 = 1811,\n\tSSI_SDATA8_MARK___4 = 1812,\n\tIP13_31_28_MARK___4 = 1813,\n\tSSI_WS01239_MARK___4 = 1814,\n\tIP14_31_28_MARK___4 = 1815,\n\tSSI_SCK5_MARK___4 = 1816,\n\tHRX0_B_MARK___2 = 1817,\n\tUSB0_PWEN_B_MARK = 1818,\n\tSCL2_D_MARK = 1819,\n\tPWM6_B_MARK___4 = 1820,\n\tIP15_31_28_MARK___4 = 1821,\n\tUSB30_OVC_MARK___4 = 1822,\n\tUSB0_OVC_A_MARK = 1823,\n\tFSO_TOE_N_A_MARK___2 = 1824,\n\tSEL_SIMCARD_0_MARK___4 = 1825,\n\tSEL_SIMCARD_1_MARK___4 = 1826,\n\tSEL_ADGB_0_MARK___4 = 1827,\n\tSEL_ADGB_2_MARK = 1828,\n\tSEL_ADGB_1_MARK___4 = 1829,\n\tSEL_SSI2_0_MARK___4 = 1830,\n\tSEL_SSI2_1_MARK___4 = 1831,\n\tSEL_TIMER_TMU_0_MARK___3 = 1832,\n\tSEL_TIMER_TMU_1_MARK___3 = 1833,\n\tSEL_DRIF0_0_MARK___4 = 1834,\n\tSEL_DRIF0_1_MARK___4 = 1835,\n\tSEL_USB_20_CH0_0_MARK = 1836,\n\tSEL_USB_20_CH0_1_MARK = 1837,\n\tSEL_FM_0_MARK___4 = 1838,\n\tSEL_FM_2_MARK___4 = 1839,\n\tSEL_FM_1_MARK___4 = 1840,\n\tSEL_DRIF2_0_MARK___4 = 1841,\n\tSEL_DRIF2_1_MARK___4 = 1842,\n\tSEL_FSO_0_MARK = 1843,\n\tSEL_FSO_1_MARK = 1844,\n\tSEL_DRIF3_0_MARK___4 = 1845,\n\tSEL_DRIF3_1_MARK___4 = 1846,\n\tSEL_HSCIF0_0_MARK___2 = 1847,\n\tSEL_HSCIF0_1_MARK___2 = 1848,\n\tSEL_HSCIF3_0_MARK___5 = 1849,\n\tSEL_HSCIF3_4_MARK = 1850,\n\tSEL_HSCIF3_2_MARK___4 = 1851,\n\tSEL_HSCIF3_1_MARK___5 = 1852,\n\tSEL_HSCIF3_3_MARK___4 = 1853,\n\tSEL_HSCIF1_0_MARK___4 = 1854,\n\tSEL_HSCIF1_1_MARK___4 = 1855,\n\tSEL_HSCIF2_0_MARK___4 = 1856,\n\tSEL_HSCIF2_1_MARK___4 = 1857,\n\tSEL_I2C1_0_MARK___5 = 1858,\n\tSEL_I2C1_2_MARK = 1859,\n\tSEL_I2C1_1_MARK___4 = 1860,\n\tSEL_I2C1_3_MARK___2 = 1861,\n\tSEL_HSCIF4_0_MARK___4 = 1862,\n\tSEL_HSCIF4_4_MARK = 1863,\n\tSEL_HSCIF4_2_MARK = 1864,\n\tSEL_HSCIF4_1_MARK___4 = 1865,\n\tSEL_HSCIF4_3_MARK = 1866,\n\tSEL_I2C2_0_MARK___6 = 1867,\n\tSEL_I2C2_4_MARK = 1868,\n\tSEL_I2C2_2_MARK = 1869,\n\tSEL_I2C2_1_MARK___5 = 1870,\n\tSEL_I2C2_3_MARK___2 = 1871,\n\tSEL_I2C6_0_MARK___4 = 1872,\n\tSEL_I2C6_1_MARK___4 = 1873,\n\tSEL_I2C7_0_MARK = 1874,\n\tSEL_I2C7_1_MARK = 1875,\n\tSEL_NDF_0_MARK___3 = 1876,\n\tSEL_NDF_1_MARK___3 = 1877,\n\tSEL_MSIOF2_0_MARK___5 = 1878,\n\tSEL_MSIOF2_1_MARK___5 = 1879,\n\tSEL_PWM0_0_MARK___3 = 1880,\n\tSEL_PWM0_1_MARK___3 = 1881,\n\tSEL_MSIOF3_0_MARK___5 = 1882,\n\tSEL_MSIOF3_1_MARK___5 = 1883,\n\tSEL_PWM1_0_MARK___6 = 1884,\n\tSEL_PWM1_1_MARK___6 = 1885,\n\tSEL_SCIF3_0_MARK___5 = 1886,\n\tSEL_SCIF3_2_MARK = 1887,\n\tSEL_SCIF3_1_MARK___5 = 1888,\n\tSEL_PWM2_0_MARK___6 = 1889,\n\tSEL_PWM2_2_MARK___2 = 1890,\n\tSEL_PWM2_1_MARK___6 = 1891,\n\tSEL_SCIF4_0_MARK___5 = 1892,\n\tSEL_SCIF4_2_MARK___4 = 1893,\n\tSEL_SCIF4_1_MARK___5 = 1894,\n\tSEL_PWM3_0_MARK___6 = 1895,\n\tSEL_PWM3_2_MARK___2 = 1896,\n\tSEL_PWM3_1_MARK___6 = 1897,\n\tSEL_SCIF5_0_MARK___5 = 1898,\n\tSEL_SCIF5_2_MARK = 1899,\n\tSEL_SCIF5_1_MARK___5 = 1900,\n\tSEL_PWM4_0_MARK___5 = 1901,\n\tSEL_PWM4_1_MARK___5 = 1902,\n\tSEL_PWM5_0_MARK___4 = 1903,\n\tSEL_PWM5_1_MARK___4 = 1904,\n\tSEL_VIN4_0_MARK___4 = 1905,\n\tSEL_VIN4_1_MARK___4 = 1906,\n\tSEL_PWM6_0_MARK___4 = 1907,\n\tSEL_PWM6_1_MARK___4 = 1908,\n\tSEL_VIN5_0_MARK = 1909,\n\tSEL_VIN5_1_MARK = 1910,\n\tSEL_REMOCON_0_MARK___4 = 1911,\n\tSEL_REMOCON_2_MARK = 1912,\n\tSEL_REMOCON_1_MARK___4 = 1913,\n\tSEL_ADGC_0_MARK___4 = 1914,\n\tSEL_ADGC_2_MARK = 1915,\n\tSEL_ADGC_1_MARK___4 = 1916,\n\tSEL_SCIF_0_MARK___4 = 1917,\n\tSEL_SCIF_1_MARK___4 = 1918,\n\tSEL_SSI9_0_MARK___4 = 1919,\n\tSEL_SSI9_1_MARK___4 = 1920,\n\tSEL_SCIF0_0_MARK___2 = 1921,\n\tSEL_SCIF0_1_MARK___2 = 1922,\n\tSEL_SCIF2_0_MARK___4 = 1923,\n\tSEL_SCIF2_1_MARK___4 = 1924,\n\tSEL_SPEED_PULSE_IF_0_MARK = 1925,\n\tSEL_SPEED_PULSE_IF_2_MARK = 1926,\n\tSEL_SPEED_PULSE_IF_1_MARK = 1927,\n\tAVB_TX_CTL_MARK___5 = 1928,\n\tAVB_TXC_MARK___5 = 1929,\n\tAVB_TD0_MARK___5 = 1930,\n\tAVB_TD1_MARK___5 = 1931,\n\tAVB_TD2_MARK___5 = 1932,\n\tAVB_TD3_MARK___5 = 1933,\n\tPRESETOUT_N_MARK = 1934,\n\tFSCLKST_N_MARK = 1935,\n\tTRST_N_MARK = 1936,\n\tTCK_MARK___4 = 1937,\n\tTMS_MARK___4 = 1938,\n\tTDI_MARK___4 = 1939,\n\tASEBRK_MARK___4 = 1940,\n\tMLB_REF_MARK___4 = 1941,\n\tVDDQ_AVB0_MARK = 1942,\n\tPINMUX_MARK_END___8 = 1943,\n};\n\nenum {\n\tPINMUX_RESERVED___9 = 0,\n\tPINMUX_DATA_BEGIN___9 = 1,\n\tGP_0_0_DATA___9 = 2,\n\tGP_0_1_DATA___9 = 3,\n\tGP_0_2_DATA___9 = 4,\n\tGP_0_3_DATA___9 = 5,\n\tGP_0_4_DATA___9 = 6,\n\tGP_0_5_DATA___9 = 7,\n\tGP_0_6_DATA___9 = 8,\n\tGP_0_7_DATA___9 = 9,\n\tGP_0_8_DATA___9 = 10,\n\tGP_0_9_DATA___8 = 11,\n\tGP_0_10_DATA___8 = 12,\n\tGP_0_11_DATA___8 = 13,\n\tGP_0_12_DATA___8 = 14,\n\tGP_0_13_DATA___8 = 15,\n\tGP_0_14_DATA___8 = 16,\n\tGP_0_15_DATA___8 = 17,\n\tGP_0_16_DATA___5 = 18,\n\tGP_0_17_DATA___5 = 19,\n\tGP_0_18_DATA___4 = 20,\n\tGP_0_19_DATA___3 = 21,\n\tGP_0_20_DATA___3 = 22,\n\tGP_0_21_DATA___2 = 23,\n\tGP_0_22_DATA = 24,\n\tGP_0_23_DATA = 25,\n\tGP_0_24_DATA = 26,\n\tGP_0_25_DATA = 27,\n\tGP_0_26_DATA = 28,\n\tGP_0_27_DATA = 29,\n\tGP_1_0_DATA___9 = 30,\n\tGP_1_1_DATA___9 = 31,\n\tGP_1_2_DATA___9 = 32,\n\tGP_1_3_DATA___9 = 33,\n\tGP_1_4_DATA___9 = 34,\n\tGP_1_5_DATA___9 = 35,\n\tGP_1_6_DATA___9 = 36,\n\tGP_1_7_DATA___9 = 37,\n\tGP_1_8_DATA___9 = 38,\n\tGP_1_9_DATA___9 = 39,\n\tGP_1_10_DATA___9 = 40,\n\tGP_1_11_DATA___9 = 41,\n\tGP_1_12_DATA___9 = 42,\n\tGP_1_13_DATA___9 = 43,\n\tGP_1_14_DATA___9 = 44,\n\tGP_1_15_DATA___9 = 45,\n\tGP_1_16_DATA___9 = 46,\n\tGP_1_17_DATA___9 = 47,\n\tGP_1_18_DATA___9 = 48,\n\tGP_1_19_DATA___9 = 49,\n\tGP_1_20_DATA___9 = 50,\n\tGP_1_21_DATA___9 = 51,\n\tGP_1_22_DATA___9 = 52,\n\tGP_1_23_DATA___8 = 53,\n\tGP_1_24_DATA___8 = 54,\n\tGP_1_25_DATA___7 = 55,\n\tGP_1_26_DATA___7 = 56,\n\tGP_1_27_DATA___7 = 57,\n\tGP_1_28_DATA___6 = 58,\n\tGP_1_29_DATA___2 = 59,\n\tGP_1_30_DATA___2 = 60,\n\tGP_2_0_DATA___9 = 61,\n\tGP_2_1_DATA___9 = 62,\n\tGP_2_2_DATA___9 = 63,\n\tGP_2_3_DATA___9 = 64,\n\tGP_2_4_DATA___9 = 65,\n\tGP_2_5_DATA___9 = 66,\n\tGP_2_6_DATA___9 = 67,\n\tGP_2_7_DATA___9 = 68,\n\tGP_2_8_DATA___9 = 69,\n\tGP_2_9_DATA___9 = 70,\n\tGP_2_10_DATA___9 = 71,\n\tGP_2_11_DATA___9 = 72,\n\tGP_2_12_DATA___9 = 73,\n\tGP_2_13_DATA___9 = 74,\n\tGP_2_14_DATA___9 = 75,\n\tGP_2_15_DATA___6 = 76,\n\tGP_2_16_DATA___6 = 77,\n\tGP_2_17_DATA___5 = 78,\n\tGP_2_18_DATA___5 = 79,\n\tGP_2_19_DATA___5 = 80,\n\tGP_2_20_DATA___4 = 81,\n\tGP_2_21_DATA___4 = 82,\n\tGP_2_22_DATA___4 = 83,\n\tGP_2_23_DATA___4 = 84,\n\tGP_2_24_DATA___4 = 85,\n\tGP_3_0_DATA___9 = 86,\n\tGP_3_1_DATA___9 = 87,\n\tGP_3_2_DATA___9 = 88,\n\tGP_3_3_DATA___9 = 89,\n\tGP_3_4_DATA___9 = 90,\n\tGP_3_5_DATA___9 = 91,\n\tGP_3_6_DATA___9 = 92,\n\tGP_3_7_DATA___9 = 93,\n\tGP_3_8_DATA___9 = 94,\n\tGP_3_9_DATA___9 = 95,\n\tGP_3_10_DATA___8 = 96,\n\tGP_3_11_DATA___8 = 97,\n\tGP_3_12_DATA___8 = 98,\n\tGP_3_13_DATA___8 = 99,\n\tGP_3_14_DATA___8 = 100,\n\tGP_3_15_DATA___8 = 101,\n\tGP_3_16_DATA___4 = 102,\n\tGP_4_0_DATA___8 = 103,\n\tGP_4_1_DATA___8 = 104,\n\tGP_4_2_DATA___8 = 105,\n\tGP_4_3_DATA___8 = 106,\n\tGP_4_4_DATA___8 = 107,\n\tGP_4_5_DATA___8 = 108,\n\tGP_4_6_DATA___8 = 109,\n\tGP_4_7_DATA___8 = 110,\n\tGP_4_8_DATA___8 = 111,\n\tGP_4_9_DATA___8 = 112,\n\tGP_4_10_DATA___8 = 113,\n\tGP_4_11_DATA___7 = 114,\n\tGP_4_12_DATA___7 = 115,\n\tGP_4_13_DATA___7 = 116,\n\tGP_4_14_DATA___7 = 117,\n\tGP_4_15_DATA___7 = 118,\n\tGP_4_16_DATA___7 = 119,\n\tGP_4_17_DATA___7 = 120,\n\tGP_4_18_DATA___4 = 121,\n\tGP_4_19_DATA___4 = 122,\n\tGP_4_20_DATA___4 = 123,\n\tGP_4_21_DATA___4 = 124,\n\tGP_4_22_DATA___4 = 125,\n\tGP_4_23_DATA___4 = 126,\n\tGP_4_24_DATA___4 = 127,\n\tGP_4_25_DATA___2 = 128,\n\tGP_4_26_DATA___2 = 129,\n\tGP_5_0_DATA___8 = 130,\n\tGP_5_1_DATA___8 = 131,\n\tGP_5_2_DATA___8 = 132,\n\tGP_5_3_DATA___8 = 133,\n\tGP_5_4_DATA___8 = 134,\n\tGP_5_5_DATA___8 = 135,\n\tGP_5_6_DATA___8 = 136,\n\tGP_5_7_DATA___8 = 137,\n\tGP_5_8_DATA___8 = 138,\n\tGP_5_9_DATA___8 = 139,\n\tGP_5_10_DATA___8 = 140,\n\tGP_5_11_DATA___8 = 141,\n\tGP_5_12_DATA___8 = 142,\n\tGP_5_13_DATA___8 = 143,\n\tGP_5_14_DATA___8 = 144,\n\tGP_5_15_DATA___7 = 145,\n\tGP_5_16_DATA___7 = 146,\n\tGP_5_17_DATA___7 = 147,\n\tGP_5_18_DATA___7 = 148,\n\tGP_5_19_DATA___7 = 149,\n\tGP_5_20_DATA___6 = 150,\n\tGP_6_0_DATA___7 = 151,\n\tGP_6_1_DATA___7 = 152,\n\tGP_6_2_DATA___7 = 153,\n\tGP_6_3_DATA___7 = 154,\n\tGP_6_4_DATA___7 = 155,\n\tGP_6_5_DATA___7 = 156,\n\tGP_6_6_DATA___7 = 157,\n\tGP_6_7_DATA___7 = 158,\n\tGP_6_8_DATA___7 = 159,\n\tGP_6_9_DATA___7 = 160,\n\tGP_6_10_DATA___7 = 161,\n\tGP_6_11_DATA___7 = 162,\n\tGP_6_12_DATA___7 = 163,\n\tGP_6_13_DATA___7 = 164,\n\tGP_6_14_DATA___6 = 165,\n\tGP_6_15_DATA___6 = 166,\n\tGP_6_16_DATA___6 = 167,\n\tGP_6_17_DATA___6 = 168,\n\tGP_6_18_DATA___5 = 169,\n\tGP_6_19_DATA___5 = 170,\n\tGP_6_20_DATA___5 = 171,\n\tGP_7_0_DATA___5 = 172,\n\tGP_7_1_DATA___5 = 173,\n\tGP_7_2_DATA___5 = 174,\n\tGP_7_3_DATA___5 = 175,\n\tGP_7_4_DATA___2 = 176,\n\tGP_7_5_DATA___2 = 177,\n\tGP_7_6_DATA___2 = 178,\n\tGP_7_7_DATA___2 = 179,\n\tGP_7_8_DATA___2 = 180,\n\tGP_7_9_DATA___2 = 181,\n\tGP_7_10_DATA___2 = 182,\n\tGP_7_11_DATA___2 = 183,\n\tGP_7_12_DATA___2 = 184,\n\tGP_7_13_DATA___2 = 185,\n\tGP_7_14_DATA___2 = 186,\n\tGP_7_15_DATA___2 = 187,\n\tGP_7_16_DATA___2 = 188,\n\tGP_7_17_DATA___2 = 189,\n\tGP_7_18_DATA___2 = 190,\n\tGP_7_19_DATA___2 = 191,\n\tGP_7_20_DATA___2 = 192,\n\tGP_8_0_DATA___2 = 193,\n\tGP_8_1_DATA___2 = 194,\n\tGP_8_2_DATA___2 = 195,\n\tGP_8_3_DATA___2 = 196,\n\tGP_8_4_DATA___2 = 197,\n\tGP_8_5_DATA___2 = 198,\n\tGP_8_6_DATA___2 = 199,\n\tGP_8_7_DATA___2 = 200,\n\tGP_8_8_DATA___2 = 201,\n\tGP_8_9_DATA___2 = 202,\n\tGP_8_10_DATA___2 = 203,\n\tGP_8_11_DATA___2 = 204,\n\tGP_8_12_DATA___2 = 205,\n\tGP_8_13_DATA___2 = 206,\n\tGP_8_14_DATA = 207,\n\tGP_8_15_DATA = 208,\n\tGP_8_16_DATA = 209,\n\tGP_8_17_DATA = 210,\n\tGP_8_18_DATA = 211,\n\tGP_8_19_DATA = 212,\n\tGP_8_20_DATA = 213,\n\tGP_9_0_DATA = 214,\n\tGP_9_1_DATA = 215,\n\tGP_9_2_DATA = 216,\n\tGP_9_3_DATA = 217,\n\tGP_9_4_DATA = 218,\n\tGP_9_5_DATA = 219,\n\tGP_9_6_DATA = 220,\n\tGP_9_7_DATA = 221,\n\tGP_9_8_DATA = 222,\n\tGP_9_9_DATA = 223,\n\tGP_9_10_DATA = 224,\n\tGP_9_11_DATA = 225,\n\tGP_9_12_DATA = 226,\n\tGP_9_13_DATA = 227,\n\tGP_9_14_DATA = 228,\n\tGP_9_15_DATA = 229,\n\tGP_9_16_DATA = 230,\n\tGP_9_17_DATA = 231,\n\tGP_9_18_DATA = 232,\n\tGP_9_19_DATA = 233,\n\tGP_9_20_DATA = 234,\n\tPINMUX_DATA_END___9 = 235,\n\tPINMUX_FUNCTION_BEGIN___9 = 236,\n\tGP_0_0_FN___9 = 237,\n\tGP_0_1_FN___9 = 238,\n\tGP_0_2_FN___9 = 239,\n\tGP_0_3_FN___9 = 240,\n\tGP_0_4_FN___9 = 241,\n\tGP_0_5_FN___9 = 242,\n\tGP_0_6_FN___9 = 243,\n\tGP_0_7_FN___9 = 244,\n\tGP_0_8_FN___9 = 245,\n\tGP_0_9_FN___8 = 246,\n\tGP_0_10_FN___8 = 247,\n\tGP_0_11_FN___8 = 248,\n\tGP_0_12_FN___8 = 249,\n\tGP_0_13_FN___8 = 250,\n\tGP_0_14_FN___8 = 251,\n\tGP_0_15_FN___8 = 252,\n\tGP_0_16_FN___5 = 253,\n\tGP_0_17_FN___5 = 254,\n\tGP_0_18_FN___4 = 255,\n\tGP_0_19_FN___3 = 256,\n\tGP_0_20_FN___3 = 257,\n\tGP_0_21_FN___2 = 258,\n\tGP_0_22_FN = 259,\n\tGP_0_23_FN = 260,\n\tGP_0_24_FN = 261,\n\tGP_0_25_FN = 262,\n\tGP_0_26_FN = 263,\n\tGP_0_27_FN = 264,\n\tGP_1_0_FN___9 = 265,\n\tGP_1_1_FN___9 = 266,\n\tGP_1_2_FN___9 = 267,\n\tGP_1_3_FN___9 = 268,\n\tGP_1_4_FN___9 = 269,\n\tGP_1_5_FN___9 = 270,\n\tGP_1_6_FN___9 = 271,\n\tGP_1_7_FN___9 = 272,\n\tGP_1_8_FN___9 = 273,\n\tGP_1_9_FN___9 = 274,\n\tGP_1_10_FN___9 = 275,\n\tGP_1_11_FN___9 = 276,\n\tGP_1_12_FN___9 = 277,\n\tGP_1_13_FN___9 = 278,\n\tGP_1_14_FN___9 = 279,\n\tGP_1_15_FN___9 = 280,\n\tGP_1_16_FN___9 = 281,\n\tGP_1_17_FN___9 = 282,\n\tGP_1_18_FN___9 = 283,\n\tGP_1_19_FN___9 = 284,\n\tGP_1_20_FN___9 = 285,\n\tGP_1_21_FN___9 = 286,\n\tGP_1_22_FN___9 = 287,\n\tGP_1_23_FN___8 = 288,\n\tGP_1_24_FN___8 = 289,\n\tGP_1_25_FN___7 = 290,\n\tGP_1_26_FN___7 = 291,\n\tGP_1_27_FN___7 = 292,\n\tGP_1_28_FN___6 = 293,\n\tGP_1_29_FN___2 = 294,\n\tGP_1_30_FN___2 = 295,\n\tGP_2_0_FN___9 = 296,\n\tGP_2_1_FN___9 = 297,\n\tGP_2_2_FN___9 = 298,\n\tGP_2_3_FN___9 = 299,\n\tGP_2_4_FN___9 = 300,\n\tGP_2_5_FN___9 = 301,\n\tGP_2_6_FN___9 = 302,\n\tGP_2_7_FN___9 = 303,\n\tGP_2_8_FN___9 = 304,\n\tGP_2_9_FN___9 = 305,\n\tGP_2_10_FN___9 = 306,\n\tGP_2_11_FN___9 = 307,\n\tGP_2_12_FN___9 = 308,\n\tGP_2_13_FN___9 = 309,\n\tGP_2_14_FN___9 = 310,\n\tGP_2_15_FN___6 = 311,\n\tGP_2_16_FN___6 = 312,\n\tGP_2_17_FN___5 = 313,\n\tGP_2_18_FN___5 = 314,\n\tGP_2_19_FN___5 = 315,\n\tGP_2_20_FN___4 = 316,\n\tGP_2_21_FN___4 = 317,\n\tGP_2_22_FN___4 = 318,\n\tGP_2_23_FN___4 = 319,\n\tGP_2_24_FN___4 = 320,\n\tGP_3_0_FN___9 = 321,\n\tGP_3_1_FN___9 = 322,\n\tGP_3_2_FN___9 = 323,\n\tGP_3_3_FN___9 = 324,\n\tGP_3_4_FN___9 = 325,\n\tGP_3_5_FN___9 = 326,\n\tGP_3_6_FN___9 = 327,\n\tGP_3_7_FN___9 = 328,\n\tGP_3_8_FN___9 = 329,\n\tGP_3_9_FN___9 = 330,\n\tGP_3_10_FN___8 = 331,\n\tGP_3_11_FN___8 = 332,\n\tGP_3_12_FN___8 = 333,\n\tGP_3_13_FN___8 = 334,\n\tGP_3_14_FN___8 = 335,\n\tGP_3_15_FN___8 = 336,\n\tGP_3_16_FN___4 = 337,\n\tGP_4_0_FN___8 = 338,\n\tGP_4_1_FN___8 = 339,\n\tGP_4_2_FN___8 = 340,\n\tGP_4_3_FN___8 = 341,\n\tGP_4_4_FN___8 = 342,\n\tGP_4_5_FN___8 = 343,\n\tGP_4_6_FN___8 = 344,\n\tGP_4_7_FN___8 = 345,\n\tGP_4_8_FN___8 = 346,\n\tGP_4_9_FN___8 = 347,\n\tGP_4_10_FN___8 = 348,\n\tGP_4_11_FN___7 = 349,\n\tGP_4_12_FN___7 = 350,\n\tGP_4_13_FN___7 = 351,\n\tGP_4_14_FN___7 = 352,\n\tGP_4_15_FN___7 = 353,\n\tGP_4_16_FN___7 = 354,\n\tGP_4_17_FN___7 = 355,\n\tGP_4_18_FN___4 = 356,\n\tGP_4_19_FN___4 = 357,\n\tGP_4_20_FN___4 = 358,\n\tGP_4_21_FN___4 = 359,\n\tGP_4_22_FN___4 = 360,\n\tGP_4_23_FN___4 = 361,\n\tGP_4_24_FN___4 = 362,\n\tGP_4_25_FN___2 = 363,\n\tGP_4_26_FN___2 = 364,\n\tGP_5_0_FN___8 = 365,\n\tGP_5_1_FN___8 = 366,\n\tGP_5_2_FN___8 = 367,\n\tGP_5_3_FN___8 = 368,\n\tGP_5_4_FN___8 = 369,\n\tGP_5_5_FN___8 = 370,\n\tGP_5_6_FN___8 = 371,\n\tGP_5_7_FN___8 = 372,\n\tGP_5_8_FN___8 = 373,\n\tGP_5_9_FN___8 = 374,\n\tGP_5_10_FN___8 = 375,\n\tGP_5_11_FN___8 = 376,\n\tGP_5_12_FN___8 = 377,\n\tGP_5_13_FN___8 = 378,\n\tGP_5_14_FN___8 = 379,\n\tGP_5_15_FN___7 = 380,\n\tGP_5_16_FN___7 = 381,\n\tGP_5_17_FN___7 = 382,\n\tGP_5_18_FN___7 = 383,\n\tGP_5_19_FN___7 = 384,\n\tGP_5_20_FN___6 = 385,\n\tGP_6_0_FN___7 = 386,\n\tGP_6_1_FN___7 = 387,\n\tGP_6_2_FN___7 = 388,\n\tGP_6_3_FN___7 = 389,\n\tGP_6_4_FN___7 = 390,\n\tGP_6_5_FN___7 = 391,\n\tGP_6_6_FN___7 = 392,\n\tGP_6_7_FN___7 = 393,\n\tGP_6_8_FN___7 = 394,\n\tGP_6_9_FN___7 = 395,\n\tGP_6_10_FN___7 = 396,\n\tGP_6_11_FN___7 = 397,\n\tGP_6_12_FN___7 = 398,\n\tGP_6_13_FN___7 = 399,\n\tGP_6_14_FN___6 = 400,\n\tGP_6_15_FN___6 = 401,\n\tGP_6_16_FN___6 = 402,\n\tGP_6_17_FN___6 = 403,\n\tGP_6_18_FN___5 = 404,\n\tGP_6_19_FN___5 = 405,\n\tGP_6_20_FN___5 = 406,\n\tGP_7_0_FN___5 = 407,\n\tGP_7_1_FN___5 = 408,\n\tGP_7_2_FN___5 = 409,\n\tGP_7_3_FN___5 = 410,\n\tGP_7_4_FN___2 = 411,\n\tGP_7_5_FN___2 = 412,\n\tGP_7_6_FN___2 = 413,\n\tGP_7_7_FN___2 = 414,\n\tGP_7_8_FN___2 = 415,\n\tGP_7_9_FN___2 = 416,\n\tGP_7_10_FN___2 = 417,\n\tGP_7_11_FN___2 = 418,\n\tGP_7_12_FN___2 = 419,\n\tGP_7_13_FN___2 = 420,\n\tGP_7_14_FN___2 = 421,\n\tGP_7_15_FN___2 = 422,\n\tGP_7_16_FN___2 = 423,\n\tGP_7_17_FN___2 = 424,\n\tGP_7_18_FN___2 = 425,\n\tGP_7_19_FN___2 = 426,\n\tGP_7_20_FN___2 = 427,\n\tGP_8_0_FN___2 = 428,\n\tGP_8_1_FN___2 = 429,\n\tGP_8_2_FN___2 = 430,\n\tGP_8_3_FN___2 = 431,\n\tGP_8_4_FN___2 = 432,\n\tGP_8_5_FN___2 = 433,\n\tGP_8_6_FN___2 = 434,\n\tGP_8_7_FN___2 = 435,\n\tGP_8_8_FN___2 = 436,\n\tGP_8_9_FN___2 = 437,\n\tGP_8_10_FN___2 = 438,\n\tGP_8_11_FN___2 = 439,\n\tGP_8_12_FN___2 = 440,\n\tGP_8_13_FN___2 = 441,\n\tGP_8_14_FN = 442,\n\tGP_8_15_FN = 443,\n\tGP_8_16_FN = 444,\n\tGP_8_17_FN = 445,\n\tGP_8_18_FN = 446,\n\tGP_8_19_FN = 447,\n\tGP_8_20_FN = 448,\n\tGP_9_0_FN = 449,\n\tGP_9_1_FN = 450,\n\tGP_9_2_FN = 451,\n\tGP_9_3_FN = 452,\n\tGP_9_4_FN = 453,\n\tGP_9_5_FN = 454,\n\tGP_9_6_FN = 455,\n\tGP_9_7_FN = 456,\n\tGP_9_8_FN = 457,\n\tGP_9_9_FN = 458,\n\tGP_9_10_FN = 459,\n\tGP_9_11_FN = 460,\n\tGP_9_12_FN = 461,\n\tGP_9_13_FN = 462,\n\tGP_9_14_FN = 463,\n\tGP_9_15_FN = 464,\n\tGP_9_16_FN = 465,\n\tGP_9_17_FN = 466,\n\tGP_9_18_FN = 467,\n\tGP_9_19_FN = 468,\n\tGP_9_20_FN = 469,\n\tFN_MMC_D7___5 = 470,\n\tFN_MMC_D6___5 = 471,\n\tFN_AVS1___5 = 472,\n\tFN_MMC_D5___5 = 473,\n\tFN_AVS0___2 = 474,\n\tFN_MMC_D4___5 = 475,\n\tFN_TCLK2_A___8 = 476,\n\tFN_PCIE3_CLKREQ_N = 477,\n\tFN_MMC_SD_CLK___3 = 478,\n\tFN_PCIE2_CLKREQ_N = 479,\n\tFN_MMC_SD_D3___3 = 480,\n\tFN_PCIE1_CLKREQ_N___3 = 481,\n\tFN_MMC_SD_D2___3 = 482,\n\tFN_PCIE0_CLKREQ_N___3 = 483,\n\tFN_MMC_SD_D1___3 = 484,\n\tFN_AVB2_AVTP_PPS___2 = 485,\n\tFN_AVB3_AVTP_PPS = 486,\n\tFN_AVB4_AVTP_PPS = 487,\n\tFN_AVB5_AVTP_PPS = 488,\n\tFN_MMC_SD_D0___3 = 489,\n\tFN_AVB2_AVTP_CAPTURE___2 = 490,\n\tFN_AVB3_AVTP_CAPTURE = 491,\n\tFN_AVB4_AVTP_CAPTURE = 492,\n\tFN_AVB5_AVTP_CAPTURE = 493,\n\tFN_MMC_SD_CMD___3 = 494,\n\tFN_AVB2_AVTP_MATCH___2 = 495,\n\tFN_AVB3_AVTP_MATCH = 496,\n\tFN_AVB4_AVTP_MATCH = 497,\n\tFN_AVB5_AVTP_MATCH = 498,\n\tFN_MMC_DS___4 = 499,\n\tFN_AVB2_LINK___2 = 500,\n\tFN_AVB3_LINK = 501,\n\tFN_AVB4_LINK = 502,\n\tFN_AVB5_LINK = 503,\n\tFN_SD_CD___3 = 504,\n\tFN_CANFD7_RX___2 = 505,\n\tFN_AVB0_PHY_INT___3 = 506,\n\tFN_AVB1_PHY_INT___2 = 507,\n\tFN_AVB2_PHY_INT___2 = 508,\n\tFN_AVB3_PHY_INT = 509,\n\tFN_AVB4_PHY_INT = 510,\n\tFN_AVB5_PHY_INT = 511,\n\tFN_SD_WP___3 = 512,\n\tFN_CANFD7_TX___2 = 513,\n\tFN_AVB2_MAGIC___2 = 514,\n\tFN_AVB3_MAGIC = 515,\n\tFN_AVB4_MAGIC = 516,\n\tFN_AVB5_MAGIC = 517,\n\tFN_RPC_INT_N___6 = 518,\n\tFN_CANFD6_RX___2 = 519,\n\tFN_AVB2_MDC___2 = 520,\n\tFN_AVB3_MDC = 521,\n\tFN_AVB4_MDC = 522,\n\tFN_AVB5_MDC = 523,\n\tFN_RPC_WP_N___4 = 524,\n\tFN_AVB2_MDIO___2 = 525,\n\tFN_AVB3_MDIO = 526,\n\tFN_AVB4_MDIO = 527,\n\tFN_AVB5_MDIO = 528,\n\tFN_RPC_RESET_N___6 = 529,\n\tFN_AVB2_TXCREFCLK___2 = 530,\n\tFN_AVB3_TXCREFCLK = 531,\n\tFN_AVB4_TXCREFCLK = 532,\n\tFN_AVB5_TXCREFCLK = 533,\n\tFN_QSPI1_SSL___6 = 534,\n\tFN_AVB2_TD3___2 = 535,\n\tFN_AVB3_TD3 = 536,\n\tFN_AVB4_TD3 = 537,\n\tFN_AVB5_TD3 = 538,\n\tFN_QSPI1_IO3___6 = 539,\n\tFN_AVB2_TD2___2 = 540,\n\tFN_AVB3_TD2 = 541,\n\tFN_AVB4_TD2 = 542,\n\tFN_AVB5_TD2 = 543,\n\tFN_QSPI1_IO2___6 = 544,\n\tFN_AVB2_TD1___2 = 545,\n\tFN_AVB3_TD1 = 546,\n\tFN_AVB4_TD1 = 547,\n\tFN_AVB5_TD1 = 548,\n\tFN_QSPI1_MISO_IO1___6 = 549,\n\tFN_AVB2_TD0___2 = 550,\n\tFN_AVB3_TD0 = 551,\n\tFN_AVB4_TD0 = 552,\n\tFN_AVB5_TD0 = 553,\n\tFN_QSPI1_MOSI_IO0___6 = 554,\n\tFN_AVB2_TXC___2 = 555,\n\tFN_AVB3_TXC = 556,\n\tFN_AVB4_TXC = 557,\n\tFN_AVB5_TXC = 558,\n\tFN_QSPI1_SPCLK___6 = 559,\n\tFN_AVB2_TX_CTL___2 = 560,\n\tFN_AVB3_TX_CTL = 561,\n\tFN_AVB4_TX_CTL = 562,\n\tFN_AVB5_TX_CTL = 563,\n\tFN_QSPI0_SSL___6 = 564,\n\tFN_AVB2_RD3___2 = 565,\n\tFN_AVB3_RD3 = 566,\n\tFN_AVB4_RD3 = 567,\n\tFN_AVB5_RD3 = 568,\n\tFN_QSPI0_IO3___6 = 569,\n\tFN_CANFD1_RX___8 = 570,\n\tFN_AVB2_RD2___2 = 571,\n\tFN_AVB3_RD2 = 572,\n\tFN_AVB4_RD2 = 573,\n\tFN_AVB5_RD2 = 574,\n\tFN_QSPI0_IO2___6 = 575,\n\tFN_CANFD1_TX___8 = 576,\n\tFN_AVB2_RD1___2 = 577,\n\tFN_AVB3_RD1 = 578,\n\tFN_AVB4_RD1 = 579,\n\tFN_AVB5_RD1 = 580,\n\tFN_QSPI0_MISO_IO1___6 = 581,\n\tFN_AVB2_RD0___2 = 582,\n\tFN_AVB3_RD0 = 583,\n\tFN_AVB4_RD0 = 584,\n\tFN_AVB5_RD0 = 585,\n\tFN_QSPI0_MOSI_IO0___6 = 586,\n\tFN_AVB2_RXC___2 = 587,\n\tFN_AVB3_RXC = 588,\n\tFN_AVB4_RXC = 589,\n\tFN_AVB5_RXC = 590,\n\tFN_QSPI0_SPCLK___6 = 591,\n\tFN_CAN_CLK___7 = 592,\n\tFN_AVB2_RX_CTL___2 = 593,\n\tFN_AVB3_RX_CTL = 594,\n\tFN_AVB4_RX_CTL = 595,\n\tFN_AVB5_RX_CTL = 596,\n\tFN_IP0SR1_3_0___3 = 597,\n\tFN_SCIF_CLK___4 = 598,\n\tFN_A0___6 = 599,\n\tFN_IP1SR1_3_0___2 = 600,\n\tFN_MSIOF0_SCK___9 = 601,\n\tFN_DU_DR4___7 = 602,\n\tFN_A8___6 = 603,\n\tFN_IP2SR1_3_0___2 = 604,\n\tFN_MSIOF1_SS1___6 = 605,\n\tFN_HCTS3_N___7 = 606,\n\tFN_RX3___3 = 607,\n\tFN_DU_DG6___7 = 608,\n\tFN_A16___6 = 609,\n\tFN_IP3SR1_3_0___2 = 610,\n\tFN_IRQ0___7 = 611,\n\tFN_DU_DOTCLKOUT___2 = 612,\n\tFN_A24 = 613,\n\tFN_IP0SR1_7_4___3 = 614,\n\tFN_HRX0___7 = 615,\n\tFN_RX0___7 = 616,\n\tFN_A1___6 = 617,\n\tFN_IP1SR1_7_4___2 = 618,\n\tFN_MSIOF0_SYNC___9 = 619,\n\tFN_DU_DR5___7 = 620,\n\tFN_A9___6 = 621,\n\tFN_IP2SR1_7_4___2 = 622,\n\tFN_MSIOF1_SS2___6 = 623,\n\tFN_HTX3___3 = 624,\n\tFN_TX3___3 = 625,\n\tFN_DU_DG7___7 = 626,\n\tFN_A17___6 = 627,\n\tFN_IP3SR1_7_4___2 = 628,\n\tFN_IRQ1___7 = 629,\n\tFN_DU_HSYNC___3 = 630,\n\tFN_A25 = 631,\n\tFN_IP0SR1_11_8___3 = 632,\n\tFN_HSCK0___7 = 633,\n\tFN_SCK0___7 = 634,\n\tFN_A2___6 = 635,\n\tFN_IP1SR1_11_8___2 = 636,\n\tFN_MSIOF0_SS1___9 = 637,\n\tFN_DU_DR6___7 = 638,\n\tFN_A10___6 = 639,\n\tFN_IP2SR1_11_8___2 = 640,\n\tFN_MSIOF2_RXD___5 = 641,\n\tFN_HSCK1___3 = 642,\n\tFN_SCK1___7 = 643,\n\tFN_DU_DB2___7 = 644,\n\tFN_A18___6 = 645,\n\tFN_IP3SR1_11_8___2 = 646,\n\tFN_IRQ2___7 = 647,\n\tFN_DU_VSYNC___3 = 648,\n\tFN_CS1_N_A26___2 = 649,\n\tFN_IP0SR1_15_12___3 = 650,\n\tFN_HRTS0_N___7 = 651,\n\tFN_RTS0_N___8 = 652,\n\tFN_A3___6 = 653,\n\tFN_IP1SR1_15_12___2 = 654,\n\tFN_MSIOF0_SS2___9 = 655,\n\tFN_DU_DR7___7 = 656,\n\tFN_A11___6 = 657,\n\tFN_IP2SR1_15_12___2 = 658,\n\tFN_MSIOF2_TXD___5 = 659,\n\tFN_HCTS1_N___3 = 660,\n\tFN_CTS1_N___8 = 661,\n\tFN_DU_DB3___7 = 662,\n\tFN_A19___6 = 663,\n\tFN_IP3SR1_15_12___2 = 664,\n\tFN_IRQ3___7 = 665,\n\tFN_DU_ODDF_DISP_CDE = 666,\n\tFN_CS0_N___6 = 667,\n\tFN_IP0SR1_19_16___3 = 668,\n\tFN_HCTS0_N___7 = 669,\n\tFN_CTS0_N___8 = 670,\n\tFN_A4___6 = 671,\n\tFN_IP1SR1_19_16___2 = 672,\n\tFN_MSIOF1_RXD___6 = 673,\n\tFN_DU_DG2___7 = 674,\n\tFN_A12___6 = 675,\n\tFN_IP2SR1_19_16___2 = 676,\n\tFN_MSIOF2_SCK___5 = 677,\n\tFN_HRTS1_N___3 = 678,\n\tFN_RTS1_N___8 = 679,\n\tFN_DU_DB4___7 = 680,\n\tFN_A20 = 681,\n\tFN_IP3SR1_19_16___2 = 682,\n\tFN_GP1_28 = 683,\n\tFN_D0___6 = 684,\n\tFN_IP0SR1_23_20___3 = 685,\n\tFN_HTX0___7 = 686,\n\tFN_TX0___7 = 687,\n\tFN_A5___6 = 688,\n\tFN_IP1SR1_23_20___2 = 689,\n\tFN_MSIOF1_TXD___6 = 690,\n\tFN_HRX3___3 = 691,\n\tFN_SCK3___6 = 692,\n\tFN_DU_DG3___7 = 693,\n\tFN_A13___6 = 694,\n\tFN_IP2SR1_23_20___2 = 695,\n\tFN_MSIOF2_SYNC___4 = 696,\n\tFN_HRX1___3 = 697,\n\tFN_RX1_A___7 = 698,\n\tFN_DU_DB5___7 = 699,\n\tFN_A21 = 700,\n\tFN_IP3SR1_23_20 = 701,\n\tFN_GP1_29 = 702,\n\tFN_D1___6 = 703,\n\tFN_IP0SR1_27_24___3 = 704,\n\tFN_MSIOF0_RXD___9 = 705,\n\tFN_DU_DR2___7 = 706,\n\tFN_A6___6 = 707,\n\tFN_IP1SR1_27_24___2 = 708,\n\tFN_MSIOF1_SCK___6 = 709,\n\tFN_HSCK3___6 = 710,\n\tFN_CTS3_N___6 = 711,\n\tFN_DU_DG4___7 = 712,\n\tFN_A14___6 = 713,\n\tFN_IP2SR1_27_24___2 = 714,\n\tFN_MSIOF2_SS1___5 = 715,\n\tFN_HTX1___3 = 716,\n\tFN_TX1_A___7 = 717,\n\tFN_DU_DB6___7 = 718,\n\tFN_A22 = 719,\n\tFN_IP3SR1_27_24 = 720,\n\tFN_GP1_30 = 721,\n\tFN_D2___6 = 722,\n\tFN_IP0SR1_31_28___3 = 723,\n\tFN_MSIOF0_TXD___9 = 724,\n\tFN_DU_DR3___7 = 725,\n\tFN_A7___6 = 726,\n\tFN_IP1SR1_31_28___2 = 727,\n\tFN_MSIOF1_SYNC___6 = 728,\n\tFN_HRTS3_N___7 = 729,\n\tFN_RTS3_N___6 = 730,\n\tFN_DU_DG5___7 = 731,\n\tFN_A15___6 = 732,\n\tFN_IP2SR1_31_28___2 = 733,\n\tFN_MSIOF2_SS2___5 = 734,\n\tFN_TCLK1_B___8 = 735,\n\tFN_DU_DB7___7 = 736,\n\tFN_A23 = 737,\n\tFN_IP0SR2_3_0___2 = 738,\n\tFN_IPC_CLKIN___2 = 739,\n\tFN_IPC_CLKEN_IN___2 = 740,\n\tFN_DU_DOTCLKIN = 741,\n\tFN_IP1SR2_3_0___2 = 742,\n\tFN_GP2_08 = 743,\n\tFN_HRX2___4 = 744,\n\tFN_MSIOF4_SS1___2 = 745,\n\tFN_RX4___4 = 746,\n\tFN_D9___6 = 747,\n\tFN_IP2SR2_3_0___2 = 748,\n\tFN_FXR_TXDA_A = 749,\n\tFN_MSIOF3_SS1___4 = 750,\n\tFN_IP0SR2_7_4___2 = 751,\n\tFN_IPC_CLKOUT___2 = 752,\n\tFN_IPC_CLKEN_OUT___2 = 753,\n\tFN_IP1SR2_7_4___2 = 754,\n\tFN_GP2_09 = 755,\n\tFN_HTX2___4 = 756,\n\tFN_MSIOF4_SS2___2 = 757,\n\tFN_TX4___4 = 758,\n\tFN_D10___6 = 759,\n\tFN_IP2SR2_7_4___2 = 760,\n\tFN_RXDA_EXTFXR_A = 761,\n\tFN_MSIOF3_SS2___4 = 762,\n\tFN_BS_N___6 = 763,\n\tFN_IP0SR2_11_8___2 = 764,\n\tFN_GP2_02 = 765,\n\tFN_D3___6 = 766,\n\tFN_IP1SR2_11_8___2 = 767,\n\tFN_GP2_10 = 768,\n\tFN_TCLK2_B___8 = 769,\n\tFN_MSIOF5_RXD___2 = 770,\n\tFN_D11___6 = 771,\n\tFN_IP2SR2_11_8___2 = 772,\n\tFN_FXR_TXDB___3 = 773,\n\tFN_MSIOF3_RXD___4 = 774,\n\tFN_RD_N___6 = 775,\n\tFN_IP0SR2_15_12___2 = 776,\n\tFN_GP2_03 = 777,\n\tFN_D4___6 = 778,\n\tFN_IP1SR2_15_12___2 = 779,\n\tFN_GP2_11 = 780,\n\tFN_TCLK3___3 = 781,\n\tFN_MSIOF5_TXD___2 = 782,\n\tFN_D12___6 = 783,\n\tFN_IP2SR2_15_12___2 = 784,\n\tFN_RXDB_EXTFXR___3 = 785,\n\tFN_MSIOF3_TXD___4 = 786,\n\tFN_WE0_N___6 = 787,\n\tFN_IP0SR2_19_16___2 = 788,\n\tFN_GP2_04 = 789,\n\tFN_MSIOF4_RXD___2 = 790,\n\tFN_D5___6 = 791,\n\tFN_IP1SR2_19_16___2 = 792,\n\tFN_GP2_12 = 793,\n\tFN_TCLK4___3 = 794,\n\tFN_MSIOF5_SCK___2 = 795,\n\tFN_D13___6 = 796,\n\tFN_IP2SR2_19_16 = 797,\n\tFN_CLK_EXTFXR___3 = 798,\n\tFN_MSIOF3_SCK___4 = 799,\n\tFN_WE1_N___6 = 800,\n\tFN_IP0SR2_23_20___2 = 801,\n\tFN_GP2_05 = 802,\n\tFN_HSCK2___4 = 803,\n\tFN_MSIOF4_TXD___2 = 804,\n\tFN_SCK4___4 = 805,\n\tFN_D6___6 = 806,\n\tFN_IP1SR2_23_20___2 = 807,\n\tFN_GP2_13 = 808,\n\tFN_MSIOF5_SYNC___2 = 809,\n\tFN_D14___6 = 810,\n\tFN_IP2SR2_23_20 = 811,\n\tFN_TPU0TO0___6 = 812,\n\tFN_MSIOF3_SYNC___4 = 813,\n\tFN_RD_WR_N___6 = 814,\n\tFN_IP0SR2_27_24___2 = 815,\n\tFN_GP2_06 = 816,\n\tFN_HCTS2_N___4 = 817,\n\tFN_MSIOF4_SCK___2 = 818,\n\tFN_CTS4_N___4 = 819,\n\tFN_D7___6 = 820,\n\tFN_IP1SR2_27_24___2 = 821,\n\tFN_GP2_14 = 822,\n\tFN_IRQ4___7 = 823,\n\tFN_MSIOF5_SS1___2 = 824,\n\tFN_D15___6 = 825,\n\tFN_IP2SR2_27_24 = 826,\n\tFN_TPU0TO1___6 = 827,\n\tFN_CLKOUT___6 = 828,\n\tFN_IP0SR2_31_28___2 = 829,\n\tFN_GP2_07 = 830,\n\tFN_HRTS2_N___4 = 831,\n\tFN_MSIOF4_SYNC___2 = 832,\n\tFN_RTS4_N___4 = 833,\n\tFN_D8___6 = 834,\n\tFN_IP1SR2_31_28___2 = 835,\n\tFN_GP2_15 = 836,\n\tFN_IRQ5___8 = 837,\n\tFN_MSIOF5_SS2___2 = 838,\n\tFN_CPG_CPCKOUT___2 = 839,\n\tFN_IP2SR2_31_28 = 840,\n\tFN_TCLK1_A___8 = 841,\n\tFN_EX_WAIT0___3 = 842,\n\tFN_IP1SR3_3_0___2 = 843,\n\tFN_CANFD3_RX___2 = 844,\n\tFN_PWM3 = 845,\n\tFN_IP0SR3_7_4___2 = 846,\n\tFN_CANFD0_TX___4 = 847,\n\tFN_FXR_TXDA_B = 848,\n\tFN_TX1_B___7 = 849,\n\tFN_IP1SR3_7_4___2 = 850,\n\tFN_CANFD4_TX___2 = 851,\n\tFN_PWM4___2 = 852,\n\tFN_FXR_CLKOUT1 = 853,\n\tFN_IP0SR3_11_8___2 = 854,\n\tFN_CANFD0_RX___4 = 855,\n\tFN_RXDA_EXTFXR_B = 856,\n\tFN_RX1_B___7 = 857,\n\tFN_IP1SR3_11_8___2 = 858,\n\tFN_CANFD4_RX___2 = 859,\n\tFN_FXR_CLKOUT2 = 860,\n\tFN_IP1SR3_15_12___2 = 861,\n\tFN_CANFD5_TX = 862,\n\tFN_FXR_TXENA_N___2 = 863,\n\tFN_IP1SR3_19_16___2 = 864,\n\tFN_CANFD5_RX = 865,\n\tFN_FXR_TXENB_N___2 = 866,\n\tFN_IP0SR3_23_20___2 = 867,\n\tFN_CANFD2_TX___2 = 868,\n\tFN_TPU0TO2___6 = 869,\n\tFN_PWM0___5 = 870,\n\tFN_IP1SR3_23_20___2 = 871,\n\tFN_CANFD6_TX___2 = 872,\n\tFN_STPWT_EXTFXR = 873,\n\tFN_IP0SR3_27_24___2 = 874,\n\tFN_CANFD2_RX___2 = 875,\n\tFN_TPU0TO3___6 = 876,\n\tFN_PWM1 = 877,\n\tFN_IP0SR3_31_28___2 = 878,\n\tFN_CANFD3_TX___2 = 879,\n\tFN_PWM2___2 = 880,\n\tFN_IP0SR4_3_0___2 = 881,\n\tFN_AVB0_RX_CTL___3 = 882,\n\tFN_AVB0_MII_RX_DV = 883,\n\tFN_IP1SR4_3_0___2 = 884,\n\tFN_AVB0_TD0___3 = 885,\n\tFN_AVB0_MII_TD0 = 886,\n\tFN_IP0SR4_7_4___2 = 887,\n\tFN_AVB0_RXC___3 = 888,\n\tFN_AVB0_MII_RXC = 889,\n\tFN_IP1SR4_7_4___2 = 890,\n\tFN_AVB0_TD1___3 = 891,\n\tFN_AVB0_MII_TD1 = 892,\n\tFN_IP2SR4_7_4___2 = 893,\n\tFN_AVB0_LINK___3 = 894,\n\tFN_AVB0_MII_TX_ER = 895,\n\tFN_IP0SR4_11_8___2 = 896,\n\tFN_AVB0_RD0___3 = 897,\n\tFN_AVB0_MII_RD0 = 898,\n\tFN_IP1SR4_11_8___2 = 899,\n\tFN_AVB0_TD2___3 = 900,\n\tFN_AVB0_MII_TD2 = 901,\n\tFN_IP2SR4_11_8___2 = 902,\n\tFN_AVB0_AVTP_MATCH___2 = 903,\n\tFN_AVB0_MII_RX_ER = 904,\n\tFN_CC5_OSCOUT = 905,\n\tFN_IP0SR4_15_12___2 = 906,\n\tFN_AVB0_RD1___3 = 907,\n\tFN_AVB0_MII_RD1 = 908,\n\tFN_IP1SR4_15_12___2 = 909,\n\tFN_AVB0_TD3___3 = 910,\n\tFN_AVB0_MII_TD3 = 911,\n\tFN_IP2SR4_15_12___2 = 912,\n\tFN_AVB0_AVTP_CAPTURE___2 = 913,\n\tFN_AVB0_MII_CRS = 914,\n\tFN_IP0SR4_19_16___2 = 915,\n\tFN_AVB0_RD2___3 = 916,\n\tFN_AVB0_MII_RD2 = 917,\n\tFN_IP1SR4_19_16___2 = 918,\n\tFN_AVB0_TXCREFCLK___3 = 919,\n\tFN_IP2SR4_19_16___2 = 920,\n\tFN_AVB0_AVTP_PPS___2 = 921,\n\tFN_AVB0_MII_COL = 922,\n\tFN_IP0SR4_23_20___2 = 923,\n\tFN_AVB0_RD3___3 = 924,\n\tFN_AVB0_MII_RD3 = 925,\n\tFN_IP1SR4_23_20___2 = 926,\n\tFN_AVB0_MDIO___3 = 927,\n\tFN_IP0SR4_27_24___2 = 928,\n\tFN_AVB0_TX_CTL___3 = 929,\n\tFN_AVB0_MII_TX_EN = 930,\n\tFN_IP1SR4_27_24___2 = 931,\n\tFN_AVB0_MDC___3 = 932,\n\tFN_IP0SR4_31_28___2 = 933,\n\tFN_AVB0_TXC___3 = 934,\n\tFN_AVB0_MII_TXC = 935,\n\tFN_IP1SR4_31_28___2 = 936,\n\tFN_AVB0_MAGIC___3 = 937,\n\tFN_IP0SR5_3_0___2 = 938,\n\tFN_AVB1_RX_CTL___2 = 939,\n\tFN_AVB1_MII_RX_DV = 940,\n\tFN_IP1SR5_3_0___2 = 941,\n\tFN_AVB1_TD0___2 = 942,\n\tFN_AVB1_MII_TD0 = 943,\n\tFN_IP0SR5_7_4___2 = 944,\n\tFN_AVB1_RXC___2 = 945,\n\tFN_AVB1_MII_RXC = 946,\n\tFN_IP1SR5_7_4___2 = 947,\n\tFN_AVB1_TD1___2 = 948,\n\tFN_AVB1_MII_TD1 = 949,\n\tFN_IP2SR5_7_4___2 = 950,\n\tFN_AVB1_LINK___2 = 951,\n\tFN_AVB1_MII_TX_ER = 952,\n\tFN_IP0SR5_11_8___2 = 953,\n\tFN_AVB1_RD0___2 = 954,\n\tFN_AVB1_MII_RD0 = 955,\n\tFN_IP1SR5_11_8___2 = 956,\n\tFN_AVB1_TD2___2 = 957,\n\tFN_AVB1_MII_TD2 = 958,\n\tFN_IP2SR5_11_8___2 = 959,\n\tFN_AVB1_AVTP_MATCH___2 = 960,\n\tFN_AVB1_MII_RX_ER = 961,\n\tFN_IP0SR5_15_12___2 = 962,\n\tFN_AVB1_RD1___2 = 963,\n\tFN_AVB1_MII_RD1 = 964,\n\tFN_IP1SR5_15_12___2 = 965,\n\tFN_AVB1_TD3___2 = 966,\n\tFN_AVB1_MII_TD3 = 967,\n\tFN_IP2SR5_15_12___2 = 968,\n\tFN_AVB1_AVTP_CAPTURE___2 = 969,\n\tFN_AVB1_MII_CRS = 970,\n\tFN_IP0SR5_19_16___2 = 971,\n\tFN_AVB1_RD2___2 = 972,\n\tFN_AVB1_MII_RD2 = 973,\n\tFN_IP1SR5_19_16___2 = 974,\n\tFN_AVB1_TXCREFCLK___2 = 975,\n\tFN_IP2SR5_19_16___2 = 976,\n\tFN_AVB1_AVTP_PPS___2 = 977,\n\tFN_AVB1_MII_COL = 978,\n\tFN_IP0SR5_23_20___2 = 979,\n\tFN_AVB1_RD3___2 = 980,\n\tFN_AVB1_MII_RD3 = 981,\n\tFN_IP1SR5_23_20___2 = 982,\n\tFN_AVB1_MDIO___2 = 983,\n\tFN_IP0SR5_27_24___2 = 984,\n\tFN_AVB1_TX_CTL___2 = 985,\n\tFN_AVB1_MII_TX_EN = 986,\n\tFN_IP1SR5_27_24___2 = 987,\n\tFN_AVB1_MDC___2 = 988,\n\tFN_IP0SR5_31_28___2 = 989,\n\tFN_AVB1_TXC___2 = 990,\n\tFN_AVB1_MII_TXC = 991,\n\tFN_IP1SR5_31_28___2 = 992,\n\tFN_AVB1_MAGIC___2 = 993,\n\tFN_SEL_I2C6_0___5 = 994,\n\tFN_SEL_I2C6_3 = 995,\n\tFN_SEL_I2C5_0___2 = 996,\n\tFN_SEL_I2C5_3___2 = 997,\n\tFN_SEL_I2C4_0___2 = 998,\n\tFN_SEL_I2C4_3___2 = 999,\n\tFN_SEL_I2C3_0___3 = 1000,\n\tFN_SEL_I2C3_3___2 = 1001,\n\tFN_SEL_I2C2_0___7 = 1002,\n\tFN_SEL_I2C2_3___3 = 1003,\n\tFN_SEL_I2C1_0___6 = 1004,\n\tFN_SEL_I2C1_3___3 = 1005,\n\tFN_SEL_I2C0_0___2 = 1006,\n\tFN_SEL_I2C0_3___2 = 1007,\n\tPINMUX_FUNCTION_END___9 = 1008,\n\tPINMUX_MARK_BEGIN___9 = 1009,\n\tMMC_D7_MARK___5 = 1010,\n\tMMC_D6_MARK___5 = 1011,\n\tAVS1_MARK___5 = 1012,\n\tMMC_D5_MARK___5 = 1013,\n\tAVS0_MARK___2 = 1014,\n\tMMC_D4_MARK___5 = 1015,\n\tTCLK2_A_MARK___8 = 1016,\n\tPCIE3_CLKREQ_N_MARK = 1017,\n\tMMC_SD_CLK_MARK___3 = 1018,\n\tPCIE2_CLKREQ_N_MARK = 1019,\n\tMMC_SD_D3_MARK___3 = 1020,\n\tPCIE1_CLKREQ_N_MARK___3 = 1021,\n\tMMC_SD_D2_MARK___3 = 1022,\n\tPCIE0_CLKREQ_N_MARK___3 = 1023,\n\tMMC_SD_D1_MARK___3 = 1024,\n\tAVB2_AVTP_PPS_MARK___2 = 1025,\n\tAVB3_AVTP_PPS_MARK = 1026,\n\tAVB4_AVTP_PPS_MARK = 1027,\n\tAVB5_AVTP_PPS_MARK = 1028,\n\tMMC_SD_D0_MARK___3 = 1029,\n\tAVB2_AVTP_CAPTURE_MARK___2 = 1030,\n\tAVB3_AVTP_CAPTURE_MARK = 1031,\n\tAVB4_AVTP_CAPTURE_MARK = 1032,\n\tAVB5_AVTP_CAPTURE_MARK = 1033,\n\tMMC_SD_CMD_MARK___3 = 1034,\n\tAVB2_AVTP_MATCH_MARK___2 = 1035,\n\tAVB3_AVTP_MATCH_MARK = 1036,\n\tAVB4_AVTP_MATCH_MARK = 1037,\n\tAVB5_AVTP_MATCH_MARK = 1038,\n\tMMC_DS_MARK___4 = 1039,\n\tAVB2_LINK_MARK___2 = 1040,\n\tAVB3_LINK_MARK = 1041,\n\tAVB4_LINK_MARK = 1042,\n\tAVB5_LINK_MARK = 1043,\n\tSD_CD_MARK___3 = 1044,\n\tCANFD7_RX_MARK___2 = 1045,\n\tAVB0_PHY_INT_MARK___3 = 1046,\n\tAVB1_PHY_INT_MARK___2 = 1047,\n\tAVB2_PHY_INT_MARK___2 = 1048,\n\tAVB3_PHY_INT_MARK = 1049,\n\tAVB4_PHY_INT_MARK = 1050,\n\tAVB5_PHY_INT_MARK = 1051,\n\tSD_WP_MARK___3 = 1052,\n\tCANFD7_TX_MARK___2 = 1053,\n\tAVB2_MAGIC_MARK___2 = 1054,\n\tAVB3_MAGIC_MARK = 1055,\n\tAVB4_MAGIC_MARK = 1056,\n\tAVB5_MAGIC_MARK = 1057,\n\tRPC_INT_N_MARK___6 = 1058,\n\tCANFD6_RX_MARK___2 = 1059,\n\tAVB2_MDC_MARK___2 = 1060,\n\tAVB3_MDC_MARK = 1061,\n\tAVB4_MDC_MARK = 1062,\n\tAVB5_MDC_MARK = 1063,\n\tRPC_WP_N_MARK___4 = 1064,\n\tAVB2_MDIO_MARK___2 = 1065,\n\tAVB3_MDIO_MARK = 1066,\n\tAVB4_MDIO_MARK = 1067,\n\tAVB5_MDIO_MARK = 1068,\n\tRPC_RESET_N_MARK___6 = 1069,\n\tAVB2_TXCREFCLK_MARK___2 = 1070,\n\tAVB3_TXCREFCLK_MARK = 1071,\n\tAVB4_TXCREFCLK_MARK = 1072,\n\tAVB5_TXCREFCLK_MARK = 1073,\n\tQSPI1_SSL_MARK___9 = 1074,\n\tAVB2_TD3_MARK___2 = 1075,\n\tAVB3_TD3_MARK = 1076,\n\tAVB4_TD3_MARK = 1077,\n\tAVB5_TD3_MARK = 1078,\n\tQSPI1_IO3_MARK___9 = 1079,\n\tAVB2_TD2_MARK___2 = 1080,\n\tAVB3_TD2_MARK = 1081,\n\tAVB4_TD2_MARK = 1082,\n\tAVB5_TD2_MARK = 1083,\n\tQSPI1_IO2_MARK___9 = 1084,\n\tAVB2_TD1_MARK___2 = 1085,\n\tAVB3_TD1_MARK = 1086,\n\tAVB4_TD1_MARK = 1087,\n\tAVB5_TD1_MARK = 1088,\n\tQSPI1_MISO_IO1_MARK___9 = 1089,\n\tAVB2_TD0_MARK___2 = 1090,\n\tAVB3_TD0_MARK = 1091,\n\tAVB4_TD0_MARK = 1092,\n\tAVB5_TD0_MARK = 1093,\n\tQSPI1_MOSI_IO0_MARK___9 = 1094,\n\tAVB2_TXC_MARK___2 = 1095,\n\tAVB3_TXC_MARK = 1096,\n\tAVB4_TXC_MARK = 1097,\n\tAVB5_TXC_MARK = 1098,\n\tQSPI1_SPCLK_MARK___9 = 1099,\n\tAVB2_TX_CTL_MARK___2 = 1100,\n\tAVB3_TX_CTL_MARK = 1101,\n\tAVB4_TX_CTL_MARK = 1102,\n\tAVB5_TX_CTL_MARK = 1103,\n\tQSPI0_SSL_MARK___9 = 1104,\n\tAVB2_RD3_MARK___2 = 1105,\n\tAVB3_RD3_MARK = 1106,\n\tAVB4_RD3_MARK = 1107,\n\tAVB5_RD3_MARK = 1108,\n\tQSPI0_IO3_MARK___9 = 1109,\n\tCANFD1_RX_MARK___8 = 1110,\n\tAVB2_RD2_MARK___2 = 1111,\n\tAVB3_RD2_MARK = 1112,\n\tAVB4_RD2_MARK = 1113,\n\tAVB5_RD2_MARK = 1114,\n\tQSPI0_IO2_MARK___9 = 1115,\n\tCANFD1_TX_MARK___8 = 1116,\n\tAVB2_RD1_MARK___2 = 1117,\n\tAVB3_RD1_MARK = 1118,\n\tAVB4_RD1_MARK = 1119,\n\tAVB5_RD1_MARK = 1120,\n\tQSPI0_MISO_IO1_MARK___9 = 1121,\n\tAVB2_RD0_MARK___2 = 1122,\n\tAVB3_RD0_MARK = 1123,\n\tAVB4_RD0_MARK = 1124,\n\tAVB5_RD0_MARK = 1125,\n\tQSPI0_MOSI_IO0_MARK___9 = 1126,\n\tAVB2_RXC_MARK___2 = 1127,\n\tAVB3_RXC_MARK = 1128,\n\tAVB4_RXC_MARK = 1129,\n\tAVB5_RXC_MARK = 1130,\n\tQSPI0_SPCLK_MARK___9 = 1131,\n\tCAN_CLK_MARK___7 = 1132,\n\tAVB2_RX_CTL_MARK___2 = 1133,\n\tAVB3_RX_CTL_MARK = 1134,\n\tAVB4_RX_CTL_MARK = 1135,\n\tAVB5_RX_CTL_MARK = 1136,\n\tIP0SR1_3_0_MARK___3 = 1137,\n\tSCIF_CLK_MARK___4 = 1138,\n\tA0_MARK___6 = 1139,\n\tIP1SR1_3_0_MARK___2 = 1140,\n\tMSIOF0_SCK_MARK___9 = 1141,\n\tDU_DR4_MARK___7 = 1142,\n\tA8_MARK___6 = 1143,\n\tIP2SR1_3_0_MARK___2 = 1144,\n\tMSIOF1_SS1_MARK___6 = 1145,\n\tHCTS3_N_MARK___7 = 1146,\n\tRX3_MARK___3 = 1147,\n\tDU_DG6_MARK___7 = 1148,\n\tA16_MARK___6 = 1149,\n\tIP3SR1_3_0_MARK___2 = 1150,\n\tIRQ0_MARK___7 = 1151,\n\tDU_DOTCLKOUT_MARK___2 = 1152,\n\tA24_MARK = 1153,\n\tIP0SR1_7_4_MARK___3 = 1154,\n\tHRX0_MARK___7 = 1155,\n\tRX0_MARK___7 = 1156,\n\tA1_MARK___6 = 1157,\n\tIP1SR1_7_4_MARK___2 = 1158,\n\tMSIOF0_SYNC_MARK___9 = 1159,\n\tDU_DR5_MARK___7 = 1160,\n\tA9_MARK___6 = 1161,\n\tIP2SR1_7_4_MARK___2 = 1162,\n\tMSIOF1_SS2_MARK___6 = 1163,\n\tHTX3_MARK___3 = 1164,\n\tTX3_MARK___3 = 1165,\n\tDU_DG7_MARK___7 = 1166,\n\tA17_MARK___6 = 1167,\n\tIP3SR1_7_4_MARK___2 = 1168,\n\tIRQ1_MARK___7 = 1169,\n\tDU_HSYNC_MARK___3 = 1170,\n\tA25_MARK = 1171,\n\tIP0SR1_11_8_MARK___3 = 1172,\n\tHSCK0_MARK___7 = 1173,\n\tSCK0_MARK___7 = 1174,\n\tA2_MARK___6 = 1175,\n\tIP1SR1_11_8_MARK___2 = 1176,\n\tMSIOF0_SS1_MARK___9 = 1177,\n\tDU_DR6_MARK___7 = 1178,\n\tA10_MARK___6 = 1179,\n\tIP2SR1_11_8_MARK___2 = 1180,\n\tMSIOF2_RXD_MARK___5 = 1181,\n\tHSCK1_MARK___3 = 1182,\n\tSCK1_MARK___7 = 1183,\n\tDU_DB2_MARK___7 = 1184,\n\tA18_MARK___6 = 1185,\n\tIP3SR1_11_8_MARK___2 = 1186,\n\tIRQ2_MARK___7 = 1187,\n\tDU_VSYNC_MARK___3 = 1188,\n\tCS1_N_A26_MARK___2 = 1189,\n\tIP0SR1_15_12_MARK___3 = 1190,\n\tHRTS0_N_MARK___7 = 1191,\n\tRTS0_N_MARK___8 = 1192,\n\tA3_MARK___6 = 1193,\n\tIP1SR1_15_12_MARK___2 = 1194,\n\tMSIOF0_SS2_MARK___9 = 1195,\n\tDU_DR7_MARK___7 = 1196,\n\tA11_MARK___6 = 1197,\n\tIP2SR1_15_12_MARK___2 = 1198,\n\tMSIOF2_TXD_MARK___5 = 1199,\n\tHCTS1_N_MARK___3 = 1200,\n\tCTS1_N_MARK___8 = 1201,\n\tDU_DB3_MARK___7 = 1202,\n\tA19_MARK___6 = 1203,\n\tIP3SR1_15_12_MARK___2 = 1204,\n\tIRQ3_MARK___7 = 1205,\n\tDU_ODDF_DISP_CDE_MARK = 1206,\n\tCS0_N_MARK___6 = 1207,\n\tIP0SR1_19_16_MARK___3 = 1208,\n\tHCTS0_N_MARK___7 = 1209,\n\tCTS0_N_MARK___8 = 1210,\n\tA4_MARK___6 = 1211,\n\tIP1SR1_19_16_MARK___2 = 1212,\n\tMSIOF1_RXD_MARK___6 = 1213,\n\tDU_DG2_MARK___7 = 1214,\n\tA12_MARK___6 = 1215,\n\tIP2SR1_19_16_MARK___2 = 1216,\n\tMSIOF2_SCK_MARK___5 = 1217,\n\tHRTS1_N_MARK___3 = 1218,\n\tRTS1_N_MARK___8 = 1219,\n\tDU_DB4_MARK___7 = 1220,\n\tA20_MARK = 1221,\n\tIP3SR1_19_16_MARK___2 = 1222,\n\tGP1_28_MARK = 1223,\n\tD0_MARK___6 = 1224,\n\tIP0SR1_23_20_MARK___3 = 1225,\n\tHTX0_MARK___7 = 1226,\n\tTX0_MARK___7 = 1227,\n\tA5_MARK___6 = 1228,\n\tIP1SR1_23_20_MARK___2 = 1229,\n\tMSIOF1_TXD_MARK___6 = 1230,\n\tHRX3_MARK___3 = 1231,\n\tSCK3_MARK___6 = 1232,\n\tDU_DG3_MARK___7 = 1233,\n\tA13_MARK___6 = 1234,\n\tIP2SR1_23_20_MARK___2 = 1235,\n\tMSIOF2_SYNC_MARK___4 = 1236,\n\tHRX1_MARK___3 = 1237,\n\tRX1_A_MARK___7 = 1238,\n\tDU_DB5_MARK___7 = 1239,\n\tA21_MARK = 1240,\n\tIP3SR1_23_20_MARK = 1241,\n\tGP1_29_MARK = 1242,\n\tD1_MARK___6 = 1243,\n\tIP0SR1_27_24_MARK___3 = 1244,\n\tMSIOF0_RXD_MARK___9 = 1245,\n\tDU_DR2_MARK___7 = 1246,\n\tA6_MARK___6 = 1247,\n\tIP1SR1_27_24_MARK___2 = 1248,\n\tMSIOF1_SCK_MARK___6 = 1249,\n\tHSCK3_MARK___6 = 1250,\n\tCTS3_N_MARK___6 = 1251,\n\tDU_DG4_MARK___7 = 1252,\n\tA14_MARK___6 = 1253,\n\tIP2SR1_27_24_MARK___2 = 1254,\n\tMSIOF2_SS1_MARK___5 = 1255,\n\tHTX1_MARK___3 = 1256,\n\tTX1_A_MARK___7 = 1257,\n\tDU_DB6_MARK___7 = 1258,\n\tA22_MARK = 1259,\n\tIP3SR1_27_24_MARK = 1260,\n\tGP1_30_MARK = 1261,\n\tD2_MARK___6 = 1262,\n\tIP0SR1_31_28_MARK___3 = 1263,\n\tMSIOF0_TXD_MARK___9 = 1264,\n\tDU_DR3_MARK___7 = 1265,\n\tA7_MARK___6 = 1266,\n\tIP1SR1_31_28_MARK___2 = 1267,\n\tMSIOF1_SYNC_MARK___6 = 1268,\n\tHRTS3_N_MARK___7 = 1269,\n\tRTS3_N_MARK___6 = 1270,\n\tDU_DG5_MARK___7 = 1271,\n\tA15_MARK___6 = 1272,\n\tIP2SR1_31_28_MARK___2 = 1273,\n\tMSIOF2_SS2_MARK___5 = 1274,\n\tTCLK1_B_MARK___8 = 1275,\n\tDU_DB7_MARK___7 = 1276,\n\tA23_MARK = 1277,\n\tIP0SR2_3_0_MARK___2 = 1278,\n\tIPC_CLKIN_MARK___2 = 1279,\n\tIPC_CLKEN_IN_MARK___2 = 1280,\n\tDU_DOTCLKIN_MARK = 1281,\n\tIP1SR2_3_0_MARK___2 = 1282,\n\tGP2_08_MARK = 1283,\n\tHRX2_MARK___4 = 1284,\n\tMSIOF4_SS1_MARK___2 = 1285,\n\tRX4_MARK___4 = 1286,\n\tD9_MARK___6 = 1287,\n\tIP2SR2_3_0_MARK___2 = 1288,\n\tFXR_TXDA_A_MARK = 1289,\n\tMSIOF3_SS1_MARK___4 = 1290,\n\tIP0SR2_7_4_MARK___2 = 1291,\n\tIPC_CLKOUT_MARK___2 = 1292,\n\tIPC_CLKEN_OUT_MARK___2 = 1293,\n\tIP1SR2_7_4_MARK___2 = 1294,\n\tGP2_09_MARK = 1295,\n\tHTX2_MARK___4 = 1296,\n\tMSIOF4_SS2_MARK___2 = 1297,\n\tTX4_MARK___4 = 1298,\n\tD10_MARK___6 = 1299,\n\tIP2SR2_7_4_MARK___2 = 1300,\n\tRXDA_EXTFXR_A_MARK = 1301,\n\tMSIOF3_SS2_MARK___4 = 1302,\n\tBS_N_MARK___6 = 1303,\n\tIP0SR2_11_8_MARK___2 = 1304,\n\tGP2_02_MARK = 1305,\n\tD3_MARK___6 = 1306,\n\tIP1SR2_11_8_MARK___2 = 1307,\n\tGP2_10_MARK = 1308,\n\tTCLK2_B_MARK___8 = 1309,\n\tMSIOF5_RXD_MARK___2 = 1310,\n\tD11_MARK___6 = 1311,\n\tIP2SR2_11_8_MARK___2 = 1312,\n\tFXR_TXDB_MARK___3 = 1313,\n\tMSIOF3_RXD_MARK___4 = 1314,\n\tRD_N_MARK___6 = 1315,\n\tIP0SR2_15_12_MARK___2 = 1316,\n\tGP2_03_MARK = 1317,\n\tD4_MARK___6 = 1318,\n\tIP1SR2_15_12_MARK___2 = 1319,\n\tGP2_11_MARK = 1320,\n\tTCLK3_MARK___3 = 1321,\n\tMSIOF5_TXD_MARK___2 = 1322,\n\tD12_MARK___6 = 1323,\n\tIP2SR2_15_12_MARK___2 = 1324,\n\tRXDB_EXTFXR_MARK___3 = 1325,\n\tMSIOF3_TXD_MARK___4 = 1326,\n\tWE0_N_MARK___6 = 1327,\n\tIP0SR2_19_16_MARK___2 = 1328,\n\tGP2_04_MARK = 1329,\n\tMSIOF4_RXD_MARK___2 = 1330,\n\tD5_MARK___6 = 1331,\n\tIP1SR2_19_16_MARK___2 = 1332,\n\tGP2_12_MARK = 1333,\n\tTCLK4_MARK___3 = 1334,\n\tMSIOF5_SCK_MARK___2 = 1335,\n\tD13_MARK___6 = 1336,\n\tIP2SR2_19_16_MARK = 1337,\n\tCLK_EXTFXR_MARK___3 = 1338,\n\tMSIOF3_SCK_MARK___4 = 1339,\n\tWE1_N_MARK___6 = 1340,\n\tIP0SR2_23_20_MARK___2 = 1341,\n\tGP2_05_MARK = 1342,\n\tHSCK2_MARK___4 = 1343,\n\tMSIOF4_TXD_MARK___2 = 1344,\n\tSCK4_MARK___4 = 1345,\n\tD6_MARK___6 = 1346,\n\tIP1SR2_23_20_MARK___2 = 1347,\n\tGP2_13_MARK = 1348,\n\tMSIOF5_SYNC_MARK___2 = 1349,\n\tD14_MARK___6 = 1350,\n\tIP2SR2_23_20_MARK = 1351,\n\tTPU0TO0_MARK___6 = 1352,\n\tMSIOF3_SYNC_MARK___4 = 1353,\n\tRD_WR_N_MARK___6 = 1354,\n\tIP0SR2_27_24_MARK___2 = 1355,\n\tGP2_06_MARK = 1356,\n\tHCTS2_N_MARK___4 = 1357,\n\tMSIOF4_SCK_MARK___2 = 1358,\n\tCTS4_N_MARK___4 = 1359,\n\tD7_MARK___6 = 1360,\n\tIP1SR2_27_24_MARK___2 = 1361,\n\tGP2_14_MARK = 1362,\n\tIRQ4_MARK___7 = 1363,\n\tMSIOF5_SS1_MARK___2 = 1364,\n\tD15_MARK___6 = 1365,\n\tIP2SR2_27_24_MARK = 1366,\n\tTPU0TO1_MARK___6 = 1367,\n\tCLKOUT_MARK___6 = 1368,\n\tIP0SR2_31_28_MARK___2 = 1369,\n\tGP2_07_MARK = 1370,\n\tHRTS2_N_MARK___4 = 1371,\n\tMSIOF4_SYNC_MARK___2 = 1372,\n\tRTS4_N_MARK___4 = 1373,\n\tD8_MARK___6 = 1374,\n\tIP1SR2_31_28_MARK___2 = 1375,\n\tGP2_15_MARK = 1376,\n\tIRQ5_MARK___8 = 1377,\n\tMSIOF5_SS2_MARK___2 = 1378,\n\tCPG_CPCKOUT_MARK___2 = 1379,\n\tIP2SR2_31_28_MARK = 1380,\n\tTCLK1_A_MARK___8 = 1381,\n\tEX_WAIT0_MARK___3 = 1382,\n\tIP1SR3_3_0_MARK___2 = 1383,\n\tCANFD3_RX_MARK___2 = 1384,\n\tPWM3_MARK = 1385,\n\tIP0SR3_7_4_MARK___2 = 1386,\n\tCANFD0_TX_MARK___4 = 1387,\n\tFXR_TXDA_B_MARK = 1388,\n\tTX1_B_MARK___7 = 1389,\n\tIP1SR3_7_4_MARK___2 = 1390,\n\tCANFD4_TX_MARK___2 = 1391,\n\tPWM4_MARK___2 = 1392,\n\tFXR_CLKOUT1_MARK = 1393,\n\tIP0SR3_11_8_MARK___2 = 1394,\n\tCANFD0_RX_MARK___4 = 1395,\n\tRXDA_EXTFXR_B_MARK = 1396,\n\tRX1_B_MARK___7 = 1397,\n\tIP1SR3_11_8_MARK___2 = 1398,\n\tCANFD4_RX_MARK___2 = 1399,\n\tFXR_CLKOUT2_MARK = 1400,\n\tIP1SR3_15_12_MARK___2 = 1401,\n\tCANFD5_TX_MARK = 1402,\n\tFXR_TXENA_N_MARK___2 = 1403,\n\tIP1SR3_19_16_MARK___2 = 1404,\n\tCANFD5_RX_MARK = 1405,\n\tFXR_TXENB_N_MARK___2 = 1406,\n\tIP0SR3_23_20_MARK___2 = 1407,\n\tCANFD2_TX_MARK___2 = 1408,\n\tTPU0TO2_MARK___6 = 1409,\n\tPWM0_MARK___5 = 1410,\n\tIP1SR3_23_20_MARK___2 = 1411,\n\tCANFD6_TX_MARK___2 = 1412,\n\tSTPWT_EXTFXR_MARK = 1413,\n\tIP0SR3_27_24_MARK___2 = 1414,\n\tCANFD2_RX_MARK___2 = 1415,\n\tTPU0TO3_MARK___6 = 1416,\n\tPWM1_MARK = 1417,\n\tIP0SR3_31_28_MARK___2 = 1418,\n\tCANFD3_TX_MARK___2 = 1419,\n\tPWM2_MARK___2 = 1420,\n\tIP0SR4_3_0_MARK___2 = 1421,\n\tAVB0_RX_CTL_MARK___3 = 1422,\n\tAVB0_MII_RX_DV_MARK = 1423,\n\tIP1SR4_3_0_MARK___2 = 1424,\n\tAVB0_TD0_MARK___3 = 1425,\n\tAVB0_MII_TD0_MARK = 1426,\n\tIP0SR4_7_4_MARK___2 = 1427,\n\tAVB0_RXC_MARK___3 = 1428,\n\tAVB0_MII_RXC_MARK = 1429,\n\tIP1SR4_7_4_MARK___2 = 1430,\n\tAVB0_TD1_MARK___3 = 1431,\n\tAVB0_MII_TD1_MARK = 1432,\n\tIP2SR4_7_4_MARK___2 = 1433,\n\tAVB0_LINK_MARK___3 = 1434,\n\tAVB0_MII_TX_ER_MARK = 1435,\n\tIP0SR4_11_8_MARK___2 = 1436,\n\tAVB0_RD0_MARK___3 = 1437,\n\tAVB0_MII_RD0_MARK = 1438,\n\tIP1SR4_11_8_MARK___2 = 1439,\n\tAVB0_TD2_MARK___3 = 1440,\n\tAVB0_MII_TD2_MARK = 1441,\n\tIP2SR4_11_8_MARK___2 = 1442,\n\tAVB0_AVTP_MATCH_MARK___2 = 1443,\n\tAVB0_MII_RX_ER_MARK = 1444,\n\tCC5_OSCOUT_MARK = 1445,\n\tIP0SR4_15_12_MARK___2 = 1446,\n\tAVB0_RD1_MARK___3 = 1447,\n\tAVB0_MII_RD1_MARK = 1448,\n\tIP1SR4_15_12_MARK___2 = 1449,\n\tAVB0_TD3_MARK___3 = 1450,\n\tAVB0_MII_TD3_MARK = 1451,\n\tIP2SR4_15_12_MARK___2 = 1452,\n\tAVB0_AVTP_CAPTURE_MARK___2 = 1453,\n\tAVB0_MII_CRS_MARK = 1454,\n\tIP0SR4_19_16_MARK___2 = 1455,\n\tAVB0_RD2_MARK___3 = 1456,\n\tAVB0_MII_RD2_MARK = 1457,\n\tIP1SR4_19_16_MARK___2 = 1458,\n\tAVB0_TXCREFCLK_MARK___3 = 1459,\n\tIP2SR4_19_16_MARK___2 = 1460,\n\tAVB0_AVTP_PPS_MARK___2 = 1461,\n\tAVB0_MII_COL_MARK = 1462,\n\tIP0SR4_23_20_MARK___2 = 1463,\n\tAVB0_RD3_MARK___3 = 1464,\n\tAVB0_MII_RD3_MARK = 1465,\n\tIP1SR4_23_20_MARK___2 = 1466,\n\tAVB0_MDIO_MARK___3 = 1467,\n\tIP0SR4_27_24_MARK___2 = 1468,\n\tAVB0_TX_CTL_MARK___3 = 1469,\n\tAVB0_MII_TX_EN_MARK = 1470,\n\tIP1SR4_27_24_MARK___2 = 1471,\n\tAVB0_MDC_MARK___3 = 1472,\n\tIP0SR4_31_28_MARK___2 = 1473,\n\tAVB0_TXC_MARK___3 = 1474,\n\tAVB0_MII_TXC_MARK = 1475,\n\tIP1SR4_31_28_MARK___2 = 1476,\n\tAVB0_MAGIC_MARK___3 = 1477,\n\tIP0SR5_3_0_MARK___2 = 1478,\n\tAVB1_RX_CTL_MARK___2 = 1479,\n\tAVB1_MII_RX_DV_MARK = 1480,\n\tIP1SR5_3_0_MARK___2 = 1481,\n\tAVB1_TD0_MARK___2 = 1482,\n\tAVB1_MII_TD0_MARK = 1483,\n\tIP0SR5_7_4_MARK___2 = 1484,\n\tAVB1_RXC_MARK___2 = 1485,\n\tAVB1_MII_RXC_MARK = 1486,\n\tIP1SR5_7_4_MARK___2 = 1487,\n\tAVB1_TD1_MARK___2 = 1488,\n\tAVB1_MII_TD1_MARK = 1489,\n\tIP2SR5_7_4_MARK___2 = 1490,\n\tAVB1_LINK_MARK___2 = 1491,\n\tAVB1_MII_TX_ER_MARK = 1492,\n\tIP0SR5_11_8_MARK___2 = 1493,\n\tAVB1_RD0_MARK___2 = 1494,\n\tAVB1_MII_RD0_MARK = 1495,\n\tIP1SR5_11_8_MARK___2 = 1496,\n\tAVB1_TD2_MARK___2 = 1497,\n\tAVB1_MII_TD2_MARK = 1498,\n\tIP2SR5_11_8_MARK___2 = 1499,\n\tAVB1_AVTP_MATCH_MARK___2 = 1500,\n\tAVB1_MII_RX_ER_MARK = 1501,\n\tIP0SR5_15_12_MARK___2 = 1502,\n\tAVB1_RD1_MARK___2 = 1503,\n\tAVB1_MII_RD1_MARK = 1504,\n\tIP1SR5_15_12_MARK___2 = 1505,\n\tAVB1_TD3_MARK___2 = 1506,\n\tAVB1_MII_TD3_MARK = 1507,\n\tIP2SR5_15_12_MARK___2 = 1508,\n\tAVB1_AVTP_CAPTURE_MARK___2 = 1509,\n\tAVB1_MII_CRS_MARK = 1510,\n\tIP0SR5_19_16_MARK___2 = 1511,\n\tAVB1_RD2_MARK___2 = 1512,\n\tAVB1_MII_RD2_MARK = 1513,\n\tIP1SR5_19_16_MARK___2 = 1514,\n\tAVB1_TXCREFCLK_MARK___2 = 1515,\n\tIP2SR5_19_16_MARK___2 = 1516,\n\tAVB1_AVTP_PPS_MARK___2 = 1517,\n\tAVB1_MII_COL_MARK = 1518,\n\tIP0SR5_23_20_MARK___2 = 1519,\n\tAVB1_RD3_MARK___2 = 1520,\n\tAVB1_MII_RD3_MARK = 1521,\n\tIP1SR5_23_20_MARK___2 = 1522,\n\tAVB1_MDIO_MARK___2 = 1523,\n\tIP0SR5_27_24_MARK___2 = 1524,\n\tAVB1_TX_CTL_MARK___2 = 1525,\n\tAVB1_MII_TX_EN_MARK = 1526,\n\tIP1SR5_27_24_MARK___2 = 1527,\n\tAVB1_MDC_MARK___2 = 1528,\n\tIP0SR5_31_28_MARK___2 = 1529,\n\tAVB1_TXC_MARK___2 = 1530,\n\tAVB1_MII_TXC_MARK = 1531,\n\tIP1SR5_31_28_MARK___2 = 1532,\n\tAVB1_MAGIC_MARK___2 = 1533,\n\tSEL_I2C6_0_MARK___5 = 1534,\n\tSEL_I2C6_3_MARK = 1535,\n\tSEL_I2C5_0_MARK___2 = 1536,\n\tSEL_I2C5_3_MARK___2 = 1537,\n\tSEL_I2C4_0_MARK___2 = 1538,\n\tSEL_I2C4_3_MARK___2 = 1539,\n\tSEL_I2C3_0_MARK___3 = 1540,\n\tSEL_I2C3_3_MARK___2 = 1541,\n\tSEL_I2C2_0_MARK___7 = 1542,\n\tSEL_I2C2_3_MARK___3 = 1543,\n\tSEL_I2C1_0_MARK___6 = 1544,\n\tSEL_I2C1_3_MARK___3 = 1545,\n\tSEL_I2C0_0_MARK___2 = 1546,\n\tSEL_I2C0_3_MARK___2 = 1547,\n\tSCL0_MARK___8 = 1548,\n\tSDA0_MARK___8 = 1549,\n\tSCL1_MARK___5 = 1550,\n\tSDA1_MARK___5 = 1551,\n\tSCL2_MARK___4 = 1552,\n\tSDA2_MARK___4 = 1553,\n\tSCL3_MARK___7 = 1554,\n\tSDA3_MARK___7 = 1555,\n\tSCL4_MARK___5 = 1556,\n\tSDA4_MARK___5 = 1557,\n\tSCL5_MARK___8 = 1558,\n\tSDA5_MARK___8 = 1559,\n\tSCL6_MARK = 1560,\n\tSDA6_MARK = 1561,\n\tPINMUX_MARK_END___9 = 1562,\n};\n\nenum {\n\tPINMUX_RESERVED___10 = 0,\n\tPINMUX_DATA_BEGIN___10 = 1,\n\tGP_0_0_DATA___10 = 2,\n\tGP_0_1_DATA___10 = 3,\n\tGP_0_2_DATA___10 = 4,\n\tGP_0_3_DATA___10 = 5,\n\tGP_0_4_DATA___10 = 6,\n\tGP_0_5_DATA___10 = 7,\n\tGP_0_6_DATA___10 = 8,\n\tGP_0_7_DATA___10 = 9,\n\tGP_0_8_DATA___10 = 10,\n\tGP_0_9_DATA___9 = 11,\n\tGP_0_10_DATA___9 = 12,\n\tGP_0_11_DATA___9 = 13,\n\tGP_0_12_DATA___9 = 14,\n\tGP_0_13_DATA___9 = 15,\n\tGP_0_14_DATA___9 = 16,\n\tGP_0_15_DATA___9 = 17,\n\tGP_0_16_DATA___6 = 18,\n\tGP_0_17_DATA___6 = 19,\n\tGP_0_18_DATA___5 = 20,\n\tGP_0_19_DATA___4 = 21,\n\tGP_0_20_DATA___4 = 22,\n\tGP_0_21_DATA___3 = 23,\n\tGP_1_0_DATA___10 = 24,\n\tGP_1_1_DATA___10 = 25,\n\tGP_1_2_DATA___10 = 26,\n\tGP_1_3_DATA___10 = 27,\n\tGP_1_4_DATA___10 = 28,\n\tGP_1_5_DATA___10 = 29,\n\tGP_1_6_DATA___10 = 30,\n\tGP_1_7_DATA___10 = 31,\n\tGP_1_8_DATA___10 = 32,\n\tGP_1_9_DATA___10 = 33,\n\tGP_1_10_DATA___10 = 34,\n\tGP_1_11_DATA___10 = 35,\n\tGP_1_12_DATA___10 = 36,\n\tGP_1_13_DATA___10 = 37,\n\tGP_1_14_DATA___10 = 38,\n\tGP_1_15_DATA___10 = 39,\n\tGP_1_16_DATA___10 = 40,\n\tGP_1_17_DATA___10 = 41,\n\tGP_1_18_DATA___10 = 42,\n\tGP_1_19_DATA___10 = 43,\n\tGP_1_20_DATA___10 = 44,\n\tGP_1_21_DATA___10 = 45,\n\tGP_1_22_DATA___10 = 46,\n\tGP_1_23_DATA___9 = 47,\n\tGP_1_24_DATA___9 = 48,\n\tGP_1_25_DATA___8 = 49,\n\tGP_1_26_DATA___8 = 50,\n\tGP_1_27_DATA___8 = 51,\n\tGP_2_0_DATA___10 = 52,\n\tGP_2_1_DATA___10 = 53,\n\tGP_2_2_DATA___10 = 54,\n\tGP_2_3_DATA___10 = 55,\n\tGP_2_4_DATA___10 = 56,\n\tGP_2_5_DATA___10 = 57,\n\tGP_2_6_DATA___10 = 58,\n\tGP_2_7_DATA___10 = 59,\n\tGP_2_8_DATA___10 = 60,\n\tGP_2_9_DATA___10 = 61,\n\tGP_2_10_DATA___10 = 62,\n\tGP_2_11_DATA___10 = 63,\n\tGP_2_12_DATA___10 = 64,\n\tGP_2_13_DATA___10 = 65,\n\tGP_2_14_DATA___10 = 66,\n\tGP_2_15_DATA___7 = 67,\n\tGP_2_16_DATA___7 = 68,\n\tGP_3_0_DATA___10 = 69,\n\tGP_3_1_DATA___10 = 70,\n\tGP_3_2_DATA___10 = 71,\n\tGP_3_3_DATA___10 = 72,\n\tGP_3_4_DATA___10 = 73,\n\tGP_3_5_DATA___10 = 74,\n\tGP_3_6_DATA___10 = 75,\n\tGP_3_7_DATA___10 = 76,\n\tGP_3_8_DATA___10 = 77,\n\tGP_3_9_DATA___10 = 78,\n\tGP_3_10_DATA___9 = 79,\n\tGP_3_11_DATA___9 = 80,\n\tGP_3_12_DATA___9 = 81,\n\tGP_3_13_DATA___9 = 82,\n\tGP_3_14_DATA___9 = 83,\n\tGP_3_15_DATA___9 = 84,\n\tGP_3_16_DATA___5 = 85,\n\tGP_4_0_DATA___9 = 86,\n\tGP_4_1_DATA___9 = 87,\n\tGP_4_2_DATA___9 = 88,\n\tGP_4_3_DATA___9 = 89,\n\tGP_4_4_DATA___9 = 90,\n\tGP_4_5_DATA___9 = 91,\n\tGP_5_0_DATA___9 = 92,\n\tGP_5_1_DATA___9 = 93,\n\tGP_5_2_DATA___9 = 94,\n\tGP_5_3_DATA___9 = 95,\n\tGP_5_4_DATA___9 = 96,\n\tGP_5_5_DATA___9 = 97,\n\tGP_5_6_DATA___9 = 98,\n\tGP_5_7_DATA___9 = 99,\n\tGP_5_8_DATA___9 = 100,\n\tGP_5_9_DATA___9 = 101,\n\tGP_5_10_DATA___9 = 102,\n\tGP_5_11_DATA___9 = 103,\n\tGP_5_12_DATA___9 = 104,\n\tGP_5_13_DATA___9 = 105,\n\tGP_5_14_DATA___9 = 106,\n\tPINMUX_DATA_END___10 = 107,\n\tPINMUX_FUNCTION_BEGIN___10 = 108,\n\tGP_0_0_FN___10 = 109,\n\tGP_0_1_FN___10 = 110,\n\tGP_0_2_FN___10 = 111,\n\tGP_0_3_FN___10 = 112,\n\tGP_0_4_FN___10 = 113,\n\tGP_0_5_FN___10 = 114,\n\tGP_0_6_FN___10 = 115,\n\tGP_0_7_FN___10 = 116,\n\tGP_0_8_FN___10 = 117,\n\tGP_0_9_FN___9 = 118,\n\tGP_0_10_FN___9 = 119,\n\tGP_0_11_FN___9 = 120,\n\tGP_0_12_FN___9 = 121,\n\tGP_0_13_FN___9 = 122,\n\tGP_0_14_FN___9 = 123,\n\tGP_0_15_FN___9 = 124,\n\tGP_0_16_FN___6 = 125,\n\tGP_0_17_FN___6 = 126,\n\tGP_0_18_FN___5 = 127,\n\tGP_0_19_FN___4 = 128,\n\tGP_0_20_FN___4 = 129,\n\tGP_0_21_FN___3 = 130,\n\tGP_1_0_FN___10 = 131,\n\tGP_1_1_FN___10 = 132,\n\tGP_1_2_FN___10 = 133,\n\tGP_1_3_FN___10 = 134,\n\tGP_1_4_FN___10 = 135,\n\tGP_1_5_FN___10 = 136,\n\tGP_1_6_FN___10 = 137,\n\tGP_1_7_FN___10 = 138,\n\tGP_1_8_FN___10 = 139,\n\tGP_1_9_FN___10 = 140,\n\tGP_1_10_FN___10 = 141,\n\tGP_1_11_FN___10 = 142,\n\tGP_1_12_FN___10 = 143,\n\tGP_1_13_FN___10 = 144,\n\tGP_1_14_FN___10 = 145,\n\tGP_1_15_FN___10 = 146,\n\tGP_1_16_FN___10 = 147,\n\tGP_1_17_FN___10 = 148,\n\tGP_1_18_FN___10 = 149,\n\tGP_1_19_FN___10 = 150,\n\tGP_1_20_FN___10 = 151,\n\tGP_1_21_FN___10 = 152,\n\tGP_1_22_FN___10 = 153,\n\tGP_1_23_FN___9 = 154,\n\tGP_1_24_FN___9 = 155,\n\tGP_1_25_FN___8 = 156,\n\tGP_1_26_FN___8 = 157,\n\tGP_1_27_FN___8 = 158,\n\tGP_2_0_FN___10 = 159,\n\tGP_2_1_FN___10 = 160,\n\tGP_2_2_FN___10 = 161,\n\tGP_2_3_FN___10 = 162,\n\tGP_2_4_FN___10 = 163,\n\tGP_2_5_FN___10 = 164,\n\tGP_2_6_FN___10 = 165,\n\tGP_2_7_FN___10 = 166,\n\tGP_2_8_FN___10 = 167,\n\tGP_2_9_FN___10 = 168,\n\tGP_2_10_FN___10 = 169,\n\tGP_2_11_FN___10 = 170,\n\tGP_2_12_FN___10 = 171,\n\tGP_2_13_FN___10 = 172,\n\tGP_2_14_FN___10 = 173,\n\tGP_2_15_FN___7 = 174,\n\tGP_2_16_FN___7 = 175,\n\tGP_3_0_FN___10 = 176,\n\tGP_3_1_FN___10 = 177,\n\tGP_3_2_FN___10 = 178,\n\tGP_3_3_FN___10 = 179,\n\tGP_3_4_FN___10 = 180,\n\tGP_3_5_FN___10 = 181,\n\tGP_3_6_FN___10 = 182,\n\tGP_3_7_FN___10 = 183,\n\tGP_3_8_FN___10 = 184,\n\tGP_3_9_FN___10 = 185,\n\tGP_3_10_FN___9 = 186,\n\tGP_3_11_FN___9 = 187,\n\tGP_3_12_FN___9 = 188,\n\tGP_3_13_FN___9 = 189,\n\tGP_3_14_FN___9 = 190,\n\tGP_3_15_FN___9 = 191,\n\tGP_3_16_FN___5 = 192,\n\tGP_4_0_FN___9 = 193,\n\tGP_4_1_FN___9 = 194,\n\tGP_4_2_FN___9 = 195,\n\tGP_4_3_FN___9 = 196,\n\tGP_4_4_FN___9 = 197,\n\tGP_4_5_FN___9 = 198,\n\tGP_5_0_FN___9 = 199,\n\tGP_5_1_FN___9 = 200,\n\tGP_5_2_FN___9 = 201,\n\tGP_5_3_FN___9 = 202,\n\tGP_5_4_FN___9 = 203,\n\tGP_5_5_FN___9 = 204,\n\tGP_5_6_FN___9 = 205,\n\tGP_5_7_FN___9 = 206,\n\tGP_5_8_FN___9 = 207,\n\tGP_5_9_FN___9 = 208,\n\tGP_5_10_FN___9 = 209,\n\tGP_5_11_FN___9 = 210,\n\tGP_5_12_FN___9 = 211,\n\tGP_5_13_FN___9 = 212,\n\tGP_5_14_FN___9 = 213,\n\tFN_AVB0_AVTP_MATCH___3 = 214,\n\tFN_AVB0_LINK___4 = 215,\n\tFN_AVB0_PHY_INT___4 = 216,\n\tFN_AVB0_MAGIC___4 = 217,\n\tFN_AVB0_MDC___4 = 218,\n\tFN_AVB0_MDIO___4 = 219,\n\tFN_RPC_INT_N___7 = 220,\n\tFN_AVB0_TXCREFCLK___4 = 221,\n\tFN_RPC_WP_N___5 = 222,\n\tFN_AVB0_TD3___4 = 223,\n\tFN_RPC_RESET_N___7 = 224,\n\tFN_AVB0_TD2___4 = 225,\n\tFN_QSPI1_SSL___7 = 226,\n\tFN_AVB0_TD1___4 = 227,\n\tFN_QSPI1_IO3___7 = 228,\n\tFN_AVB0_TD0___4 = 229,\n\tFN_QSPI1_IO2___7 = 230,\n\tFN_AVB0_TXC___4 = 231,\n\tFN_QSPI1_MISO_IO1___7 = 232,\n\tFN_AVB0_TX_CTL___4 = 233,\n\tFN_QSPI1_MOSI_IO0___7 = 234,\n\tFN_AVB0_RD3___4 = 235,\n\tFN_QSPI1_SPCLK___7 = 236,\n\tFN_AVB0_RD2___4 = 237,\n\tFN_QSPI0_SSL___7 = 238,\n\tFN_AVB0_RD1___4 = 239,\n\tFN_QSPI0_IO3___7 = 240,\n\tFN_AVB0_RD0___4 = 241,\n\tFN_QSPI0_IO2___7 = 242,\n\tFN_AVB0_RXC___4 = 243,\n\tFN_QSPI0_MISO_IO1___7 = 244,\n\tFN_AVB0_RX_CTL___4 = 245,\n\tFN_QSPI0_MOSI_IO0___7 = 246,\n\tFN_QSPI0_SPCLK___7 = 247,\n\tFN_IP0_3_0___7 = 248,\n\tFN_DU_DR2___8 = 249,\n\tFN_HSCK0___8 = 250,\n\tFN_A0___7 = 251,\n\tFN_IP1_3_0___7 = 252,\n\tFN_DU_DG4___8 = 253,\n\tFN_A8___7 = 254,\n\tFN_FSO_CFE_0_N_A___3 = 255,\n\tFN_IP2_3_0___7 = 256,\n\tFN_DU_DB6___8 = 257,\n\tFN_A16___7 = 258,\n\tFN_FXR_TXENB_N___3 = 259,\n\tFN_IP3_3_0___7 = 260,\n\tFN_VI0_CLKENB___2 = 261,\n\tFN_MSIOF2_RXD___6 = 262,\n\tFN_RX3___4 = 263,\n\tFN_RD_WR_N___7 = 264,\n\tFN_HCTS3_N___8 = 265,\n\tFN_IP0_7_4___7 = 266,\n\tFN_DU_DR3___8 = 267,\n\tFN_HRTS0_N___8 = 268,\n\tFN_A1___7 = 269,\n\tFN_IP1_7_4___7 = 270,\n\tFN_DU_DG5___8 = 271,\n\tFN_A9___7 = 272,\n\tFN_FSO_CFE_1_N_A___3 = 273,\n\tFN_IP2_7_4___7 = 274,\n\tFN_DU_DB7___8 = 275,\n\tFN_A17___7 = 276,\n\tFN_IP3_7_4___7 = 277,\n\tFN_VI0_HSYNC_N___2 = 278,\n\tFN_MSIOF2_TXD___6 = 279,\n\tFN_TX3___4 = 280,\n\tFN_HRTS3_N___8 = 281,\n\tFN_IP0_11_8___7 = 282,\n\tFN_DU_DR4___8 = 283,\n\tFN_HCTS0_N___8 = 284,\n\tFN_A2___7 = 285,\n\tFN_IP1_11_8___7 = 286,\n\tFN_DU_DG6___8 = 287,\n\tFN_A10___7 = 288,\n\tFN_FSO_TOE_N_A___3 = 289,\n\tFN_IP2_11_8___7 = 290,\n\tFN_DU_DOTCLKOUT___3 = 291,\n\tFN_SCIF_CLK_A___6 = 292,\n\tFN_A18___7 = 293,\n\tFN_IP3_11_8___7 = 294,\n\tFN_VI0_VSYNC_N___2 = 295,\n\tFN_MSIOF2_SYNC___5 = 296,\n\tFN_CTS3_N___7 = 297,\n\tFN_HTX3___4 = 298,\n\tFN_IP0_15_12___7 = 299,\n\tFN_DU_DR5___8 = 300,\n\tFN_HTX0___8 = 301,\n\tFN_A3___7 = 302,\n\tFN_IP1_15_12___7 = 303,\n\tFN_DU_DG7___8 = 304,\n\tFN_A11___7 = 305,\n\tFN_IRQ1___8 = 306,\n\tFN_IP2_15_12___7 = 307,\n\tFN_DU_EXHSYNC_DU_HSYNC___5 = 308,\n\tFN_HRX0___8 = 309,\n\tFN_A19___7 = 310,\n\tFN_IRQ3___8 = 311,\n\tFN_IP3_15_12___7 = 312,\n\tFN_VI0_DATA0___2 = 313,\n\tFN_MSIOF2_SS1___6 = 314,\n\tFN_RTS3_N___7 = 315,\n\tFN_HRX3___4 = 316,\n\tFN_IP0_19_16___7 = 317,\n\tFN_DU_DR6___8 = 318,\n\tFN_MSIOF3_RXD___5 = 319,\n\tFN_A4___7 = 320,\n\tFN_IP1_19_16___7 = 321,\n\tFN_DU_DB2___8 = 322,\n\tFN_A12___7 = 323,\n\tFN_IRQ2___8 = 324,\n\tFN_IP2_19_16___7 = 325,\n\tFN_DU_EXVSYNC_DU_VSYNC___5 = 326,\n\tFN_MSIOF3_SCK___5 = 327,\n\tFN_IP3_19_16___7 = 328,\n\tFN_VI0_DATA1___2 = 329,\n\tFN_MSIOF2_SS2___6 = 330,\n\tFN_SCK1___8 = 331,\n\tFN_SPEEDIN_A___6 = 332,\n\tFN_IP0_23_20___7 = 333,\n\tFN_DU_DR7___8 = 334,\n\tFN_MSIOF3_TXD___5 = 335,\n\tFN_A5___7 = 336,\n\tFN_IP1_23_20___7 = 337,\n\tFN_DU_DB3___8 = 338,\n\tFN_A13___7 = 339,\n\tFN_FXR_CLKOUT1___2 = 340,\n\tFN_IP2_23_20___7 = 341,\n\tFN_DU_EXODDF_DU_ODDF_DISP_CDE___5 = 342,\n\tFN_MSIOF3_SYNC___5 = 343,\n\tFN_IP3_23_20___7 = 344,\n\tFN_VI0_DATA2___2 = 345,\n\tFN_AVB0_AVTP_PPS___3 = 346,\n\tFN_SDA3_A___2 = 347,\n\tFN_IP0_27_24___7 = 348,\n\tFN_DU_DG2___8 = 349,\n\tFN_MSIOF3_SS1___5 = 350,\n\tFN_A6___7 = 351,\n\tFN_IP1_27_24___7 = 352,\n\tFN_DU_DB4___8 = 353,\n\tFN_A14___7 = 354,\n\tFN_FXR_CLKOUT2___2 = 355,\n\tFN_IP2_27_24___7 = 356,\n\tFN_IRQ0___8 = 357,\n\tFN_IP3_27_24___7 = 358,\n\tFN_VI0_DATA3___2 = 359,\n\tFN_HSCK1___4 = 360,\n\tFN_SCL3_A___2 = 361,\n\tFN_IP0_31_28___7 = 362,\n\tFN_DU_DG3___8 = 363,\n\tFN_MSIOF3_SS2___5 = 364,\n\tFN_A7___7 = 365,\n\tFN_PWMFSW0___2 = 366,\n\tFN_IP1_31_28___7 = 367,\n\tFN_DU_DB5___8 = 368,\n\tFN_A15___7 = 369,\n\tFN_FXR_TXENA_N___3 = 370,\n\tFN_IP2_31_28___7 = 371,\n\tFN_VI0_CLK___2 = 372,\n\tFN_MSIOF2_SCK___6 = 373,\n\tFN_SCK3___7 = 374,\n\tFN_HSCK3___7 = 375,\n\tFN_IP3_31_28___7 = 376,\n\tFN_VI0_DATA4___2 = 377,\n\tFN_HRTS1_N___4 = 378,\n\tFN_RX1_A___8 = 379,\n\tFN_IP4_3_0___7 = 380,\n\tFN_VI0_DATA5___2 = 381,\n\tFN_HCTS1_N___4 = 382,\n\tFN_TX1_A___8 = 383,\n\tFN_IP5_3_0___7 = 384,\n\tFN_VI1_CLK___2 = 385,\n\tFN_MSIOF1_RXD___7 = 386,\n\tFN_CS0_N___7 = 387,\n\tFN_IP6_3_0___7 = 388,\n\tFN_VI1_DATA4___2 = 389,\n\tFN_CANFD_CLK_B___2 = 390,\n\tFN_D7___7 = 391,\n\tFN_MMC_D2___3 = 392,\n\tFN_IP7_3_0___7 = 393,\n\tFN_VI1_FIELD___2 = 394,\n\tFN_SDA4___4 = 395,\n\tFN_IRQ5___9 = 396,\n\tFN_D15___7 = 397,\n\tFN_IP4_7_4___7 = 398,\n\tFN_VI0_DATA6___2 = 399,\n\tFN_HTX1___4 = 400,\n\tFN_CTS1_N___9 = 401,\n\tFN_IP5_7_4___7 = 402,\n\tFN_VI1_CLKENB___2 = 403,\n\tFN_MSIOF1_TXD___7 = 404,\n\tFN_D0___7 = 405,\n\tFN_IP6_7_4___7 = 406,\n\tFN_VI1_DATA5___2 = 407,\n\tFN_SCK4___5 = 408,\n\tFN_D8___7 = 409,\n\tFN_MMC_D3___3 = 410,\n\tFN_IP7_7_4___7 = 411,\n\tFN_SCL0___4 = 412,\n\tFN_DU_DR0___7 = 413,\n\tFN_TPU0TO0___7 = 414,\n\tFN_CLKOUT___7 = 415,\n\tFN_MSIOF0_RXD___10 = 416,\n\tFN_IP4_11_8___7 = 417,\n\tFN_VI0_DATA7___2 = 418,\n\tFN_HRX1___4 = 419,\n\tFN_RTS1_N___9 = 420,\n\tFN_IP5_11_8___7 = 421,\n\tFN_VI1_HSYNC_N___2 = 422,\n\tFN_MSIOF1_SCK___7 = 423,\n\tFN_D1___7 = 424,\n\tFN_IP6_11_8___7 = 425,\n\tFN_VI1_DATA6___2 = 426,\n\tFN_RX4___5 = 427,\n\tFN_D9___7 = 428,\n\tFN_MMC_CLK___3 = 429,\n\tFN_IP7_11_8___7 = 430,\n\tFN_SDA0___4 = 431,\n\tFN_DU_DR1___7 = 432,\n\tFN_TPU0TO1___7 = 433,\n\tFN_BS_N___7 = 434,\n\tFN_SCK0___8 = 435,\n\tFN_MSIOF0_TXD___10 = 436,\n\tFN_IP4_15_12___7 = 437,\n\tFN_VI0_DATA8___2 = 438,\n\tFN_HSCK2___5 = 439,\n\tFN_PWM0_A___4 = 440,\n\tFN_A22___2 = 441,\n\tFN_IP5_15_12___7 = 442,\n\tFN_VI1_VSYNC_N___2 = 443,\n\tFN_MSIOF1_SYNC___7 = 444,\n\tFN_D2___7 = 445,\n\tFN_IP6_15_12___7 = 446,\n\tFN_VI1_DATA7___2 = 447,\n\tFN_TX4___5 = 448,\n\tFN_D10___7 = 449,\n\tFN_MMC_D4___6 = 450,\n\tFN_IP7_15_12___4 = 451,\n\tFN_SCL1___4 = 452,\n\tFN_DU_DG0___7 = 453,\n\tFN_TPU0TO2___7 = 454,\n\tFN_RD_N___7 = 455,\n\tFN_CTS0_N___9 = 456,\n\tFN_MSIOF0_SCK___10 = 457,\n\tFN_IP4_19_16___7 = 458,\n\tFN_VI0_DATA9___2 = 459,\n\tFN_HCTS2_N___5 = 460,\n\tFN_PWM1_A___8 = 461,\n\tFN_A23___2 = 462,\n\tFN_FSO_CFE_0_N_B___3 = 463,\n\tFN_IP5_19_16___7 = 464,\n\tFN_VI1_DATA0___2 = 465,\n\tFN_MSIOF1_SS1___7 = 466,\n\tFN_D3___7 = 467,\n\tFN_IP6_19_16___7 = 468,\n\tFN_VI1_DATA8___2 = 469,\n\tFN_CTS4_N___5 = 470,\n\tFN_D11___7 = 471,\n\tFN_MMC_D5___6 = 472,\n\tFN_IP7_19_16___7 = 473,\n\tFN_SDA1___4 = 474,\n\tFN_DU_DG1___7 = 475,\n\tFN_TPU0TO3___7 = 476,\n\tFN_WE0_N___7 = 477,\n\tFN_RTS0_N___9 = 478,\n\tFN_MSIOF0_SYNC___10 = 479,\n\tFN_IP4_23_20___7 = 480,\n\tFN_VI0_DATA10___2 = 481,\n\tFN_HRTS2_N___5 = 482,\n\tFN_PWM2_A___7 = 483,\n\tFN_A24___2 = 484,\n\tFN_FSO_CFE_1_N_B___3 = 485,\n\tFN_IP5_23_20___7 = 486,\n\tFN_VI1_DATA1___2 = 487,\n\tFN_MSIOF1_SS2___7 = 488,\n\tFN_D4___7 = 489,\n\tFN_MMC_CMD___3 = 490,\n\tFN_IP6_23_20___7 = 491,\n\tFN_VI1_DATA9___2 = 492,\n\tFN_RTS4_N___5 = 493,\n\tFN_D12___7 = 494,\n\tFN_MMC_D6___6 = 495,\n\tFN_SCL3_B___2 = 496,\n\tFN_IP7_23_20___7 = 497,\n\tFN_SCL2___3 = 498,\n\tFN_DU_DB0___7 = 499,\n\tFN_TCLK1_A___9 = 500,\n\tFN_WE1_N___7 = 501,\n\tFN_RX0___8 = 502,\n\tFN_MSIOF0_SS1___10 = 503,\n\tFN_IP4_27_24___7 = 504,\n\tFN_VI0_DATA11___2 = 505,\n\tFN_HTX2___5 = 506,\n\tFN_PWM3_A___8 = 507,\n\tFN_A25___2 = 508,\n\tFN_FSO_TOE_N_B___3 = 509,\n\tFN_IP5_27_24___7 = 510,\n\tFN_VI1_DATA2___2 = 511,\n\tFN_CANFD0_TX_B___5 = 512,\n\tFN_D5___7 = 513,\n\tFN_MMC_D0___3 = 514,\n\tFN_IP6_27_24___7 = 515,\n\tFN_VI1_DATA10___2 = 516,\n\tFN_D13___7 = 517,\n\tFN_MMC_D7___6 = 518,\n\tFN_SDA3_B___2 = 519,\n\tFN_IP7_27_24___7 = 520,\n\tFN_SDA2___3 = 521,\n\tFN_DU_DB1___7 = 522,\n\tFN_TCLK2_A___9 = 523,\n\tFN_EX_WAIT0___4 = 524,\n\tFN_TX0___8 = 525,\n\tFN_MSIOF0_SS2___10 = 526,\n\tFN_IP4_31_28___7 = 527,\n\tFN_VI0_FIELD___2 = 528,\n\tFN_HRX2___5 = 529,\n\tFN_PWM4_A___6 = 530,\n\tFN_CS1_N___5 = 531,\n\tFN_FSCLKST2_N_A___4 = 532,\n\tFN_IP5_31_28___7 = 533,\n\tFN_VI1_DATA3___2 = 534,\n\tFN_CANFD0_RX_B___5 = 535,\n\tFN_D6___7 = 536,\n\tFN_MMC_D1___3 = 537,\n\tFN_IP6_31_28___7 = 538,\n\tFN_VI1_DATA11___2 = 539,\n\tFN_SCL4___4 = 540,\n\tFN_IRQ4___8 = 541,\n\tFN_D14___7 = 542,\n\tFN_IP7_31_28___7 = 543,\n\tFN_AVB0_AVTP_CAPTURE___3 = 544,\n\tFN_FSCLKST2_N_B___4 = 545,\n\tFN_IP8_3_0___7 = 546,\n\tFN_CANFD0_TX_A___5 = 547,\n\tFN_FXR_TXDA___3 = 548,\n\tFN_PWM0_B___4 = 549,\n\tFN_DU_DISP___7 = 550,\n\tFN_FSCLKST2_N_C = 551,\n\tFN_IP8_7_4___7 = 552,\n\tFN_CANFD0_RX_A___5 = 553,\n\tFN_RXDA_EXTFXR___3 = 554,\n\tFN_PWM1_B___8 = 555,\n\tFN_DU_CDE___7 = 556,\n\tFN_IP8_11_8___7 = 557,\n\tFN_CANFD1_TX___9 = 558,\n\tFN_FXR_TXDB___4 = 559,\n\tFN_PWM2_B___7 = 560,\n\tFN_TCLK1_B___9 = 561,\n\tFN_TX1_B___8 = 562,\n\tFN_IP8_15_12___7 = 563,\n\tFN_CANFD1_RX___9 = 564,\n\tFN_RXDB_EXTFXR___4 = 565,\n\tFN_PWM3_B___8 = 566,\n\tFN_TCLK2_B___9 = 567,\n\tFN_RX1_B___8 = 568,\n\tFN_IP8_19_16___7 = 569,\n\tFN_CANFD_CLK_A___2 = 570,\n\tFN_CLK_EXTFXR___4 = 571,\n\tFN_PWM4_B___6 = 572,\n\tFN_SPEEDIN_B___6 = 573,\n\tFN_SCIF_CLK_B___6 = 574,\n\tFN_IP8_23_20___7 = 575,\n\tFN_DIGRF_CLKIN___2 = 576,\n\tFN_DIGRF_CLKEN_IN___2 = 577,\n\tFN_IP8_27_24___7 = 578,\n\tFN_DIGRF_CLKOUT___2 = 579,\n\tFN_DIGRF_CLKEN_OUT___2 = 580,\n\tFN_SEL_I2C3_0___4 = 581,\n\tFN_SEL_I2C3_1___2 = 582,\n\tFN_SEL_HSCIF0_0___3 = 583,\n\tFN_SEL_HSCIF0_1___3 = 584,\n\tFN_SEL_SCIF1_0___6 = 585,\n\tFN_SEL_SCIF1_1___6 = 586,\n\tFN_SEL_CANFD0_0___5 = 587,\n\tFN_SEL_CANFD0_1___5 = 588,\n\tFN_SEL_PWM4_0___6 = 589,\n\tFN_SEL_PWM4_1___6 = 590,\n\tFN_SEL_PWM3_0___7 = 591,\n\tFN_SEL_PWM3_1___7 = 592,\n\tFN_SEL_PWM2_0___7 = 593,\n\tFN_SEL_PWM2_1___7 = 594,\n\tFN_SEL_PWM1_0___7 = 595,\n\tFN_SEL_PWM1_1___7 = 596,\n\tFN_SEL_PWM0_0___4 = 597,\n\tFN_SEL_PWM0_1___4 = 598,\n\tFN_SEL_RFSO_0___2 = 599,\n\tFN_SEL_RFSO_1___2 = 600,\n\tFN_SEL_RSP_0___2 = 601,\n\tFN_SEL_RSP_1___2 = 602,\n\tFN_SEL_TMU_0___2 = 603,\n\tFN_SEL_TMU_1___2 = 604,\n\tPINMUX_FUNCTION_END___10 = 605,\n\tPINMUX_MARK_BEGIN___10 = 606,\n\tAVB0_AVTP_MATCH_MARK___3 = 607,\n\tAVB0_LINK_MARK___4 = 608,\n\tAVB0_PHY_INT_MARK___4 = 609,\n\tAVB0_MAGIC_MARK___4 = 610,\n\tAVB0_MDC_MARK___4 = 611,\n\tAVB0_MDIO_MARK___4 = 612,\n\tRPC_INT_N_MARK___7 = 613,\n\tAVB0_TXCREFCLK_MARK___4 = 614,\n\tRPC_WP_N_MARK___5 = 615,\n\tAVB0_TD3_MARK___4 = 616,\n\tRPC_RESET_N_MARK___7 = 617,\n\tAVB0_TD2_MARK___4 = 618,\n\tQSPI1_SSL_MARK___10 = 619,\n\tAVB0_TD1_MARK___4 = 620,\n\tQSPI1_IO3_MARK___10 = 621,\n\tAVB0_TD0_MARK___4 = 622,\n\tQSPI1_IO2_MARK___10 = 623,\n\tAVB0_TXC_MARK___4 = 624,\n\tQSPI1_MISO_IO1_MARK___10 = 625,\n\tAVB0_TX_CTL_MARK___4 = 626,\n\tQSPI1_MOSI_IO0_MARK___10 = 627,\n\tAVB0_RD3_MARK___4 = 628,\n\tQSPI1_SPCLK_MARK___10 = 629,\n\tAVB0_RD2_MARK___4 = 630,\n\tQSPI0_SSL_MARK___10 = 631,\n\tAVB0_RD1_MARK___4 = 632,\n\tQSPI0_IO3_MARK___10 = 633,\n\tAVB0_RD0_MARK___4 = 634,\n\tQSPI0_IO2_MARK___10 = 635,\n\tAVB0_RXC_MARK___4 = 636,\n\tQSPI0_MISO_IO1_MARK___10 = 637,\n\tAVB0_RX_CTL_MARK___4 = 638,\n\tQSPI0_MOSI_IO0_MARK___10 = 639,\n\tQSPI0_SPCLK_MARK___10 = 640,\n\tIP0_3_0_MARK___7 = 641,\n\tDU_DR2_MARK___8 = 642,\n\tHSCK0_MARK___8 = 643,\n\tA0_MARK___7 = 644,\n\tIP1_3_0_MARK___7 = 645,\n\tDU_DG4_MARK___8 = 646,\n\tA8_MARK___7 = 647,\n\tFSO_CFE_0_N_A_MARK___3 = 648,\n\tIP2_3_0_MARK___7 = 649,\n\tDU_DB6_MARK___8 = 650,\n\tA16_MARK___7 = 651,\n\tFXR_TXENB_N_MARK___3 = 652,\n\tIP3_3_0_MARK___7 = 653,\n\tVI0_CLKENB_MARK___2 = 654,\n\tMSIOF2_RXD_MARK___6 = 655,\n\tRX3_MARK___4 = 656,\n\tRD_WR_N_MARK___7 = 657,\n\tHCTS3_N_MARK___8 = 658,\n\tIP0_7_4_MARK___7 = 659,\n\tDU_DR3_MARK___8 = 660,\n\tHRTS0_N_MARK___8 = 661,\n\tA1_MARK___7 = 662,\n\tIP1_7_4_MARK___7 = 663,\n\tDU_DG5_MARK___8 = 664,\n\tA9_MARK___7 = 665,\n\tFSO_CFE_1_N_A_MARK___3 = 666,\n\tIP2_7_4_MARK___7 = 667,\n\tDU_DB7_MARK___8 = 668,\n\tA17_MARK___7 = 669,\n\tIP3_7_4_MARK___7 = 670,\n\tVI0_HSYNC_N_MARK___2 = 671,\n\tMSIOF2_TXD_MARK___6 = 672,\n\tTX3_MARK___4 = 673,\n\tHRTS3_N_MARK___8 = 674,\n\tIP0_11_8_MARK___7 = 675,\n\tDU_DR4_MARK___8 = 676,\n\tHCTS0_N_MARK___8 = 677,\n\tA2_MARK___7 = 678,\n\tIP1_11_8_MARK___7 = 679,\n\tDU_DG6_MARK___8 = 680,\n\tA10_MARK___7 = 681,\n\tFSO_TOE_N_A_MARK___3 = 682,\n\tIP2_11_8_MARK___7 = 683,\n\tDU_DOTCLKOUT_MARK___3 = 684,\n\tSCIF_CLK_A_MARK___6 = 685,\n\tA18_MARK___7 = 686,\n\tIP3_11_8_MARK___7 = 687,\n\tVI0_VSYNC_N_MARK___2 = 688,\n\tMSIOF2_SYNC_MARK___5 = 689,\n\tCTS3_N_MARK___7 = 690,\n\tHTX3_MARK___4 = 691,\n\tIP0_15_12_MARK___7 = 692,\n\tDU_DR5_MARK___8 = 693,\n\tHTX0_MARK___8 = 694,\n\tA3_MARK___7 = 695,\n\tIP1_15_12_MARK___7 = 696,\n\tDU_DG7_MARK___8 = 697,\n\tA11_MARK___7 = 698,\n\tIRQ1_MARK___8 = 699,\n\tIP2_15_12_MARK___7 = 700,\n\tDU_EXHSYNC_DU_HSYNC_MARK___5 = 701,\n\tHRX0_MARK___8 = 702,\n\tA19_MARK___7 = 703,\n\tIRQ3_MARK___8 = 704,\n\tIP3_15_12_MARK___7 = 705,\n\tVI0_DATA0_MARK___2 = 706,\n\tMSIOF2_SS1_MARK___6 = 707,\n\tRTS3_N_MARK___7 = 708,\n\tHRX3_MARK___4 = 709,\n\tIP0_19_16_MARK___7 = 710,\n\tDU_DR6_MARK___8 = 711,\n\tMSIOF3_RXD_MARK___5 = 712,\n\tA4_MARK___7 = 713,\n\tIP1_19_16_MARK___7 = 714,\n\tDU_DB2_MARK___8 = 715,\n\tA12_MARK___7 = 716,\n\tIRQ2_MARK___8 = 717,\n\tIP2_19_16_MARK___7 = 718,\n\tDU_EXVSYNC_DU_VSYNC_MARK___5 = 719,\n\tMSIOF3_SCK_MARK___5 = 720,\n\tIP3_19_16_MARK___7 = 721,\n\tVI0_DATA1_MARK___2 = 722,\n\tMSIOF2_SS2_MARK___6 = 723,\n\tSCK1_MARK___8 = 724,\n\tSPEEDIN_A_MARK___6 = 725,\n\tIP0_23_20_MARK___7 = 726,\n\tDU_DR7_MARK___8 = 727,\n\tMSIOF3_TXD_MARK___5 = 728,\n\tA5_MARK___7 = 729,\n\tIP1_23_20_MARK___7 = 730,\n\tDU_DB3_MARK___8 = 731,\n\tA13_MARK___7 = 732,\n\tFXR_CLKOUT1_MARK___2 = 733,\n\tIP2_23_20_MARK___7 = 734,\n\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK___5 = 735,\n\tMSIOF3_SYNC_MARK___5 = 736,\n\tIP3_23_20_MARK___7 = 737,\n\tVI0_DATA2_MARK___2 = 738,\n\tAVB0_AVTP_PPS_MARK___3 = 739,\n\tSDA3_A_MARK___2 = 740,\n\tIP0_27_24_MARK___7 = 741,\n\tDU_DG2_MARK___8 = 742,\n\tMSIOF3_SS1_MARK___5 = 743,\n\tA6_MARK___7 = 744,\n\tIP1_27_24_MARK___7 = 745,\n\tDU_DB4_MARK___8 = 746,\n\tA14_MARK___7 = 747,\n\tFXR_CLKOUT2_MARK___2 = 748,\n\tIP2_27_24_MARK___7 = 749,\n\tIRQ0_MARK___8 = 750,\n\tIP3_27_24_MARK___7 = 751,\n\tVI0_DATA3_MARK___2 = 752,\n\tHSCK1_MARK___4 = 753,\n\tSCL3_A_MARK___2 = 754,\n\tIP0_31_28_MARK___7 = 755,\n\tDU_DG3_MARK___8 = 756,\n\tMSIOF3_SS2_MARK___5 = 757,\n\tA7_MARK___7 = 758,\n\tPWMFSW0_MARK___2 = 759,\n\tIP1_31_28_MARK___7 = 760,\n\tDU_DB5_MARK___8 = 761,\n\tA15_MARK___7 = 762,\n\tFXR_TXENA_N_MARK___3 = 763,\n\tIP2_31_28_MARK___7 = 764,\n\tVI0_CLK_MARK___2 = 765,\n\tMSIOF2_SCK_MARK___6 = 766,\n\tSCK3_MARK___7 = 767,\n\tHSCK3_MARK___7 = 768,\n\tIP3_31_28_MARK___7 = 769,\n\tVI0_DATA4_MARK___2 = 770,\n\tHRTS1_N_MARK___4 = 771,\n\tRX1_A_MARK___8 = 772,\n\tIP4_3_0_MARK___7 = 773,\n\tVI0_DATA5_MARK___2 = 774,\n\tHCTS1_N_MARK___4 = 775,\n\tTX1_A_MARK___8 = 776,\n\tIP5_3_0_MARK___7 = 777,\n\tVI1_CLK_MARK___2 = 778,\n\tMSIOF1_RXD_MARK___7 = 779,\n\tCS0_N_MARK___7 = 780,\n\tIP6_3_0_MARK___7 = 781,\n\tVI1_DATA4_MARK___2 = 782,\n\tCANFD_CLK_B_MARK___2 = 783,\n\tD7_MARK___7 = 784,\n\tMMC_D2_MARK___3 = 785,\n\tIP7_3_0_MARK___7 = 786,\n\tVI1_FIELD_MARK___2 = 787,\n\tSDA4_MARK___6 = 788,\n\tIRQ5_MARK___9 = 789,\n\tD15_MARK___7 = 790,\n\tIP4_7_4_MARK___7 = 791,\n\tVI0_DATA6_MARK___2 = 792,\n\tHTX1_MARK___4 = 793,\n\tCTS1_N_MARK___9 = 794,\n\tIP5_7_4_MARK___7 = 795,\n\tVI1_CLKENB_MARK___2 = 796,\n\tMSIOF1_TXD_MARK___7 = 797,\n\tD0_MARK___7 = 798,\n\tIP6_7_4_MARK___7 = 799,\n\tVI1_DATA5_MARK___2 = 800,\n\tSCK4_MARK___5 = 801,\n\tD8_MARK___7 = 802,\n\tMMC_D3_MARK___3 = 803,\n\tIP7_7_4_MARK___7 = 804,\n\tSCL0_MARK___9 = 805,\n\tDU_DR0_MARK___7 = 806,\n\tTPU0TO0_MARK___7 = 807,\n\tCLKOUT_MARK___7 = 808,\n\tMSIOF0_RXD_MARK___10 = 809,\n\tIP4_11_8_MARK___7 = 810,\n\tVI0_DATA7_MARK___2 = 811,\n\tHRX1_MARK___4 = 812,\n\tRTS1_N_MARK___9 = 813,\n\tIP5_11_8_MARK___7 = 814,\n\tVI1_HSYNC_N_MARK___2 = 815,\n\tMSIOF1_SCK_MARK___7 = 816,\n\tD1_MARK___7 = 817,\n\tIP6_11_8_MARK___7 = 818,\n\tVI1_DATA6_MARK___2 = 819,\n\tRX4_MARK___5 = 820,\n\tD9_MARK___7 = 821,\n\tMMC_CLK_MARK___3 = 822,\n\tIP7_11_8_MARK___7 = 823,\n\tSDA0_MARK___9 = 824,\n\tDU_DR1_MARK___7 = 825,\n\tTPU0TO1_MARK___7 = 826,\n\tBS_N_MARK___7 = 827,\n\tSCK0_MARK___8 = 828,\n\tMSIOF0_TXD_MARK___10 = 829,\n\tIP4_15_12_MARK___7 = 830,\n\tVI0_DATA8_MARK___2 = 831,\n\tHSCK2_MARK___5 = 832,\n\tPWM0_A_MARK___4 = 833,\n\tA22_MARK___2 = 834,\n\tIP5_15_12_MARK___7 = 835,\n\tVI1_VSYNC_N_MARK___2 = 836,\n\tMSIOF1_SYNC_MARK___7 = 837,\n\tD2_MARK___7 = 838,\n\tIP6_15_12_MARK___7 = 839,\n\tVI1_DATA7_MARK___2 = 840,\n\tTX4_MARK___5 = 841,\n\tD10_MARK___7 = 842,\n\tMMC_D4_MARK___6 = 843,\n\tIP7_15_12_MARK___4 = 844,\n\tSCL1_MARK___6 = 845,\n\tDU_DG0_MARK___7 = 846,\n\tTPU0TO2_MARK___7 = 847,\n\tRD_N_MARK___7 = 848,\n\tCTS0_N_MARK___9 = 849,\n\tMSIOF0_SCK_MARK___10 = 850,\n\tIP4_19_16_MARK___7 = 851,\n\tVI0_DATA9_MARK___2 = 852,\n\tHCTS2_N_MARK___5 = 853,\n\tPWM1_A_MARK___8 = 854,\n\tA23_MARK___2 = 855,\n\tFSO_CFE_0_N_B_MARK___3 = 856,\n\tIP5_19_16_MARK___7 = 857,\n\tVI1_DATA0_MARK___2 = 858,\n\tMSIOF1_SS1_MARK___7 = 859,\n\tD3_MARK___7 = 860,\n\tIP6_19_16_MARK___7 = 861,\n\tVI1_DATA8_MARK___2 = 862,\n\tCTS4_N_MARK___5 = 863,\n\tD11_MARK___7 = 864,\n\tMMC_D5_MARK___6 = 865,\n\tIP7_19_16_MARK___7 = 866,\n\tSDA1_MARK___6 = 867,\n\tDU_DG1_MARK___7 = 868,\n\tTPU0TO3_MARK___7 = 869,\n\tWE0_N_MARK___7 = 870,\n\tRTS0_N_MARK___9 = 871,\n\tMSIOF0_SYNC_MARK___10 = 872,\n\tIP4_23_20_MARK___7 = 873,\n\tVI0_DATA10_MARK___2 = 874,\n\tHRTS2_N_MARK___5 = 875,\n\tPWM2_A_MARK___7 = 876,\n\tA24_MARK___2 = 877,\n\tFSO_CFE_1_N_B_MARK___3 = 878,\n\tIP5_23_20_MARK___7 = 879,\n\tVI1_DATA1_MARK___2 = 880,\n\tMSIOF1_SS2_MARK___7 = 881,\n\tD4_MARK___7 = 882,\n\tMMC_CMD_MARK___3 = 883,\n\tIP6_23_20_MARK___7 = 884,\n\tVI1_DATA9_MARK___2 = 885,\n\tRTS4_N_MARK___5 = 886,\n\tD12_MARK___7 = 887,\n\tMMC_D6_MARK___6 = 888,\n\tSCL3_B_MARK___2 = 889,\n\tIP7_23_20_MARK___7 = 890,\n\tSCL2_MARK___5 = 891,\n\tDU_DB0_MARK___7 = 892,\n\tTCLK1_A_MARK___9 = 893,\n\tWE1_N_MARK___7 = 894,\n\tRX0_MARK___8 = 895,\n\tMSIOF0_SS1_MARK___10 = 896,\n\tIP4_27_24_MARK___7 = 897,\n\tVI0_DATA11_MARK___2 = 898,\n\tHTX2_MARK___5 = 899,\n\tPWM3_A_MARK___8 = 900,\n\tA25_MARK___2 = 901,\n\tFSO_TOE_N_B_MARK___3 = 902,\n\tIP5_27_24_MARK___7 = 903,\n\tVI1_DATA2_MARK___2 = 904,\n\tCANFD0_TX_B_MARK___5 = 905,\n\tD5_MARK___7 = 906,\n\tMMC_D0_MARK___3 = 907,\n\tIP6_27_24_MARK___7 = 908,\n\tVI1_DATA10_MARK___2 = 909,\n\tD13_MARK___7 = 910,\n\tMMC_D7_MARK___6 = 911,\n\tSDA3_B_MARK___2 = 912,\n\tIP7_27_24_MARK___7 = 913,\n\tSDA2_MARK___5 = 914,\n\tDU_DB1_MARK___7 = 915,\n\tTCLK2_A_MARK___9 = 916,\n\tEX_WAIT0_MARK___4 = 917,\n\tTX0_MARK___8 = 918,\n\tMSIOF0_SS2_MARK___10 = 919,\n\tIP4_31_28_MARK___7 = 920,\n\tVI0_FIELD_MARK___2 = 921,\n\tHRX2_MARK___5 = 922,\n\tPWM4_A_MARK___6 = 923,\n\tCS1_N_MARK___5 = 924,\n\tFSCLKST2_N_A_MARK___4 = 925,\n\tIP5_31_28_MARK___7 = 926,\n\tVI1_DATA3_MARK___2 = 927,\n\tCANFD0_RX_B_MARK___5 = 928,\n\tD6_MARK___7 = 929,\n\tMMC_D1_MARK___3 = 930,\n\tIP6_31_28_MARK___7 = 931,\n\tVI1_DATA11_MARK___2 = 932,\n\tSCL4_MARK___6 = 933,\n\tIRQ4_MARK___8 = 934,\n\tD14_MARK___7 = 935,\n\tIP7_31_28_MARK___7 = 936,\n\tAVB0_AVTP_CAPTURE_MARK___3 = 937,\n\tFSCLKST2_N_B_MARK___4 = 938,\n\tIP8_3_0_MARK___7 = 939,\n\tCANFD0_TX_A_MARK___5 = 940,\n\tFXR_TXDA_MARK___3 = 941,\n\tPWM0_B_MARK___4 = 942,\n\tDU_DISP_MARK___7 = 943,\n\tFSCLKST2_N_C_MARK = 944,\n\tIP8_7_4_MARK___7 = 945,\n\tCANFD0_RX_A_MARK___5 = 946,\n\tRXDA_EXTFXR_MARK___3 = 947,\n\tPWM1_B_MARK___8 = 948,\n\tDU_CDE_MARK___7 = 949,\n\tIP8_11_8_MARK___7 = 950,\n\tCANFD1_TX_MARK___9 = 951,\n\tFXR_TXDB_MARK___4 = 952,\n\tPWM2_B_MARK___7 = 953,\n\tTCLK1_B_MARK___9 = 954,\n\tTX1_B_MARK___8 = 955,\n\tIP8_15_12_MARK___7 = 956,\n\tCANFD1_RX_MARK___9 = 957,\n\tRXDB_EXTFXR_MARK___4 = 958,\n\tPWM3_B_MARK___8 = 959,\n\tTCLK2_B_MARK___9 = 960,\n\tRX1_B_MARK___8 = 961,\n\tIP8_19_16_MARK___7 = 962,\n\tCANFD_CLK_A_MARK___2 = 963,\n\tCLK_EXTFXR_MARK___4 = 964,\n\tPWM4_B_MARK___6 = 965,\n\tSPEEDIN_B_MARK___6 = 966,\n\tSCIF_CLK_B_MARK___6 = 967,\n\tIP8_23_20_MARK___7 = 968,\n\tDIGRF_CLKIN_MARK___2 = 969,\n\tDIGRF_CLKEN_IN_MARK___2 = 970,\n\tIP8_27_24_MARK___7 = 971,\n\tDIGRF_CLKOUT_MARK___2 = 972,\n\tDIGRF_CLKEN_OUT_MARK___2 = 973,\n\tSEL_I2C3_0_MARK___4 = 974,\n\tSEL_I2C3_1_MARK___2 = 975,\n\tSEL_HSCIF0_0_MARK___3 = 976,\n\tSEL_HSCIF0_1_MARK___3 = 977,\n\tSEL_SCIF1_0_MARK___6 = 978,\n\tSEL_SCIF1_1_MARK___6 = 979,\n\tSEL_CANFD0_0_MARK___5 = 980,\n\tSEL_CANFD0_1_MARK___5 = 981,\n\tSEL_PWM4_0_MARK___6 = 982,\n\tSEL_PWM4_1_MARK___6 = 983,\n\tSEL_PWM3_0_MARK___7 = 984,\n\tSEL_PWM3_1_MARK___7 = 985,\n\tSEL_PWM2_0_MARK___7 = 986,\n\tSEL_PWM2_1_MARK___7 = 987,\n\tSEL_PWM1_0_MARK___7 = 988,\n\tSEL_PWM1_1_MARK___7 = 989,\n\tSEL_PWM0_0_MARK___4 = 990,\n\tSEL_PWM0_1_MARK___4 = 991,\n\tSEL_RFSO_0_MARK___2 = 992,\n\tSEL_RFSO_1_MARK___2 = 993,\n\tSEL_RSP_0_MARK___2 = 994,\n\tSEL_RSP_1_MARK___2 = 995,\n\tSEL_TMU_0_MARK___2 = 996,\n\tSEL_TMU_1_MARK___2 = 997,\n\tPINMUX_MARK_END___10 = 998,\n};\n\nenum {\n\tPINMUX_RESERVED___11 = 0,\n\tPINMUX_DATA_BEGIN___11 = 1,\n\tGP_0_0_DATA___11 = 2,\n\tGP_0_1_DATA___11 = 3,\n\tGP_0_2_DATA___11 = 4,\n\tGP_0_3_DATA___11 = 5,\n\tGP_0_4_DATA___11 = 6,\n\tGP_0_5_DATA___11 = 7,\n\tGP_0_6_DATA___11 = 8,\n\tGP_0_7_DATA___11 = 9,\n\tGP_0_8_DATA___11 = 10,\n\tGP_0_9_DATA___10 = 11,\n\tGP_0_10_DATA___10 = 12,\n\tGP_0_11_DATA___10 = 13,\n\tGP_0_12_DATA___10 = 14,\n\tGP_0_13_DATA___10 = 15,\n\tGP_0_14_DATA___10 = 16,\n\tGP_0_15_DATA___10 = 17,\n\tGP_0_16_DATA___7 = 18,\n\tGP_0_17_DATA___7 = 19,\n\tGP_0_18_DATA___6 = 20,\n\tGP_1_0_DATA___11 = 21,\n\tGP_1_1_DATA___11 = 22,\n\tGP_1_2_DATA___11 = 23,\n\tGP_1_3_DATA___11 = 24,\n\tGP_1_4_DATA___11 = 25,\n\tGP_1_5_DATA___11 = 26,\n\tGP_1_6_DATA___11 = 27,\n\tGP_1_7_DATA___11 = 28,\n\tGP_1_8_DATA___11 = 29,\n\tGP_1_9_DATA___11 = 30,\n\tGP_1_10_DATA___11 = 31,\n\tGP_1_11_DATA___11 = 32,\n\tGP_1_12_DATA___11 = 33,\n\tGP_1_13_DATA___11 = 34,\n\tGP_1_14_DATA___11 = 35,\n\tGP_1_15_DATA___11 = 36,\n\tGP_1_16_DATA___11 = 37,\n\tGP_1_17_DATA___11 = 38,\n\tGP_1_18_DATA___11 = 39,\n\tGP_1_19_DATA___11 = 40,\n\tGP_1_20_DATA___11 = 41,\n\tGP_1_21_DATA___11 = 42,\n\tGP_1_22_DATA___11 = 43,\n\tGP_1_23_DATA___10 = 44,\n\tGP_1_24_DATA___10 = 45,\n\tGP_1_25_DATA___9 = 46,\n\tGP_1_26_DATA___9 = 47,\n\tGP_1_27_DATA___9 = 48,\n\tGP_1_28_DATA___7 = 49,\n\tGP_1_29_DATA___3 = 50,\n\tGP_2_0_DATA___11 = 51,\n\tGP_2_1_DATA___11 = 52,\n\tGP_2_2_DATA___11 = 53,\n\tGP_2_3_DATA___11 = 54,\n\tGP_2_4_DATA___11 = 55,\n\tGP_2_5_DATA___11 = 56,\n\tGP_2_6_DATA___11 = 57,\n\tGP_2_7_DATA___11 = 58,\n\tGP_2_8_DATA___11 = 59,\n\tGP_2_9_DATA___11 = 60,\n\tGP_2_10_DATA___11 = 61,\n\tGP_2_11_DATA___11 = 62,\n\tGP_2_12_DATA___11 = 63,\n\tGP_2_13_DATA___11 = 64,\n\tGP_2_14_DATA___11 = 65,\n\tGP_2_15_DATA___8 = 66,\n\tGP_2_17_DATA___6 = 67,\n\tGP_2_19_DATA___6 = 68,\n\tGP_3_0_DATA___11 = 69,\n\tGP_3_1_DATA___11 = 70,\n\tGP_3_2_DATA___11 = 71,\n\tGP_3_3_DATA___11 = 72,\n\tGP_3_4_DATA___11 = 73,\n\tGP_3_5_DATA___11 = 74,\n\tGP_3_6_DATA___11 = 75,\n\tGP_3_7_DATA___11 = 76,\n\tGP_3_8_DATA___11 = 77,\n\tGP_3_9_DATA___11 = 78,\n\tGP_3_10_DATA___10 = 79,\n\tGP_3_11_DATA___10 = 80,\n\tGP_3_12_DATA___10 = 81,\n\tGP_3_13_DATA___10 = 82,\n\tGP_3_14_DATA___10 = 83,\n\tGP_3_15_DATA___10 = 84,\n\tGP_3_16_DATA___6 = 85,\n\tGP_3_17_DATA___3 = 86,\n\tGP_3_18_DATA___3 = 87,\n\tGP_3_19_DATA___2 = 88,\n\tGP_3_20_DATA___2 = 89,\n\tGP_3_21_DATA___2 = 90,\n\tGP_3_22_DATA___2 = 91,\n\tGP_3_23_DATA___2 = 92,\n\tGP_3_24_DATA___2 = 93,\n\tGP_3_25_DATA___2 = 94,\n\tGP_3_26_DATA___2 = 95,\n\tGP_3_27_DATA___2 = 96,\n\tGP_3_28_DATA___2 = 97,\n\tGP_3_29_DATA___2 = 98,\n\tGP_3_30_DATA = 99,\n\tGP_3_31_DATA = 100,\n\tGP_4_0_DATA___10 = 101,\n\tGP_4_1_DATA___10 = 102,\n\tGP_4_2_DATA___10 = 103,\n\tGP_4_3_DATA___10 = 104,\n\tGP_4_4_DATA___10 = 105,\n\tGP_4_5_DATA___10 = 106,\n\tGP_4_6_DATA___9 = 107,\n\tGP_4_7_DATA___9 = 108,\n\tGP_4_8_DATA___9 = 109,\n\tGP_4_9_DATA___9 = 110,\n\tGP_4_10_DATA___9 = 111,\n\tGP_4_11_DATA___8 = 112,\n\tGP_4_12_DATA___8 = 113,\n\tGP_4_13_DATA___8 = 114,\n\tGP_4_14_DATA___8 = 115,\n\tGP_4_15_DATA___8 = 116,\n\tGP_4_21_DATA___5 = 117,\n\tGP_4_23_DATA___5 = 118,\n\tGP_4_24_DATA___5 = 119,\n\tGP_5_0_DATA___10 = 120,\n\tGP_5_1_DATA___10 = 121,\n\tGP_5_2_DATA___10 = 122,\n\tGP_5_3_DATA___10 = 123,\n\tGP_5_4_DATA___10 = 124,\n\tGP_5_5_DATA___10 = 125,\n\tGP_5_6_DATA___10 = 126,\n\tGP_5_7_DATA___10 = 127,\n\tGP_5_8_DATA___10 = 128,\n\tGP_5_9_DATA___10 = 129,\n\tGP_5_10_DATA___10 = 130,\n\tGP_5_11_DATA___10 = 131,\n\tGP_5_12_DATA___10 = 132,\n\tGP_5_13_DATA___10 = 133,\n\tGP_5_14_DATA___10 = 134,\n\tGP_5_15_DATA___8 = 135,\n\tGP_5_16_DATA___8 = 136,\n\tGP_5_17_DATA___8 = 137,\n\tGP_5_18_DATA___8 = 138,\n\tGP_5_19_DATA___8 = 139,\n\tGP_5_20_DATA___7 = 140,\n\tGP_6_0_DATA___8 = 141,\n\tGP_6_1_DATA___8 = 142,\n\tGP_6_2_DATA___8 = 143,\n\tGP_6_3_DATA___8 = 144,\n\tGP_6_4_DATA___8 = 145,\n\tGP_6_5_DATA___8 = 146,\n\tGP_6_6_DATA___8 = 147,\n\tGP_6_7_DATA___8 = 148,\n\tGP_6_8_DATA___8 = 149,\n\tGP_6_9_DATA___8 = 150,\n\tGP_6_10_DATA___8 = 151,\n\tGP_6_11_DATA___8 = 152,\n\tGP_6_12_DATA___8 = 153,\n\tGP_6_13_DATA___8 = 154,\n\tGP_6_14_DATA___7 = 155,\n\tGP_6_15_DATA___7 = 156,\n\tGP_6_16_DATA___7 = 157,\n\tGP_6_17_DATA___7 = 158,\n\tGP_6_18_DATA___6 = 159,\n\tGP_6_19_DATA___6 = 160,\n\tGP_6_20_DATA___6 = 161,\n\tGP_7_0_DATA___6 = 162,\n\tGP_7_1_DATA___6 = 163,\n\tGP_7_2_DATA___6 = 164,\n\tGP_7_3_DATA___6 = 165,\n\tGP_7_4_DATA___3 = 166,\n\tGP_7_5_DATA___3 = 167,\n\tGP_7_6_DATA___3 = 168,\n\tGP_7_7_DATA___3 = 169,\n\tGP_7_8_DATA___3 = 170,\n\tGP_7_9_DATA___3 = 171,\n\tGP_7_10_DATA___3 = 172,\n\tGP_7_11_DATA___3 = 173,\n\tGP_7_12_DATA___3 = 174,\n\tGP_7_13_DATA___3 = 175,\n\tGP_7_14_DATA___3 = 176,\n\tGP_7_15_DATA___3 = 177,\n\tGP_7_16_DATA___3 = 178,\n\tGP_7_17_DATA___3 = 179,\n\tGP_7_18_DATA___3 = 180,\n\tGP_7_19_DATA___3 = 181,\n\tGP_7_20_DATA___3 = 182,\n\tPINMUX_DATA_END___11 = 183,\n\tPINMUX_FUNCTION_BEGIN___11 = 184,\n\tGP_0_0_FN___11 = 185,\n\tGP_0_1_FN___11 = 186,\n\tGP_0_2_FN___11 = 187,\n\tGP_0_3_FN___11 = 188,\n\tGP_0_4_FN___11 = 189,\n\tGP_0_5_FN___11 = 190,\n\tGP_0_6_FN___11 = 191,\n\tGP_0_7_FN___11 = 192,\n\tGP_0_8_FN___11 = 193,\n\tGP_0_9_FN___10 = 194,\n\tGP_0_10_FN___10 = 195,\n\tGP_0_11_FN___10 = 196,\n\tGP_0_12_FN___10 = 197,\n\tGP_0_13_FN___10 = 198,\n\tGP_0_14_FN___10 = 199,\n\tGP_0_15_FN___10 = 200,\n\tGP_0_16_FN___7 = 201,\n\tGP_0_17_FN___7 = 202,\n\tGP_0_18_FN___6 = 203,\n\tGP_1_0_FN___11 = 204,\n\tGP_1_1_FN___11 = 205,\n\tGP_1_2_FN___11 = 206,\n\tGP_1_3_FN___11 = 207,\n\tGP_1_4_FN___11 = 208,\n\tGP_1_5_FN___11 = 209,\n\tGP_1_6_FN___11 = 210,\n\tGP_1_7_FN___11 = 211,\n\tGP_1_8_FN___11 = 212,\n\tGP_1_9_FN___11 = 213,\n\tGP_1_10_FN___11 = 214,\n\tGP_1_11_FN___11 = 215,\n\tGP_1_12_FN___11 = 216,\n\tGP_1_13_FN___11 = 217,\n\tGP_1_14_FN___11 = 218,\n\tGP_1_15_FN___11 = 219,\n\tGP_1_16_FN___11 = 220,\n\tGP_1_17_FN___11 = 221,\n\tGP_1_18_FN___11 = 222,\n\tGP_1_19_FN___11 = 223,\n\tGP_1_20_FN___11 = 224,\n\tGP_1_21_FN___11 = 225,\n\tGP_1_22_FN___11 = 226,\n\tGP_1_23_FN___10 = 227,\n\tGP_1_24_FN___10 = 228,\n\tGP_1_25_FN___9 = 229,\n\tGP_1_26_FN___9 = 230,\n\tGP_1_27_FN___9 = 231,\n\tGP_1_28_FN___7 = 232,\n\tGP_1_29_FN___3 = 233,\n\tGP_2_0_FN___11 = 234,\n\tGP_2_1_FN___11 = 235,\n\tGP_2_2_FN___11 = 236,\n\tGP_2_3_FN___11 = 237,\n\tGP_2_4_FN___11 = 238,\n\tGP_2_5_FN___11 = 239,\n\tGP_2_6_FN___11 = 240,\n\tGP_2_7_FN___11 = 241,\n\tGP_2_8_FN___11 = 242,\n\tGP_2_9_FN___11 = 243,\n\tGP_2_10_FN___11 = 244,\n\tGP_2_11_FN___11 = 245,\n\tGP_2_12_FN___11 = 246,\n\tGP_2_13_FN___11 = 247,\n\tGP_2_14_FN___11 = 248,\n\tGP_2_15_FN___8 = 249,\n\tGP_2_17_FN___6 = 250,\n\tGP_2_19_FN___6 = 251,\n\tGP_3_0_FN___11 = 252,\n\tGP_3_1_FN___11 = 253,\n\tGP_3_2_FN___11 = 254,\n\tGP_3_3_FN___11 = 255,\n\tGP_3_4_FN___11 = 256,\n\tGP_3_5_FN___11 = 257,\n\tGP_3_6_FN___11 = 258,\n\tGP_3_7_FN___11 = 259,\n\tGP_3_8_FN___11 = 260,\n\tGP_3_9_FN___11 = 261,\n\tGP_3_10_FN___10 = 262,\n\tGP_3_11_FN___10 = 263,\n\tGP_3_12_FN___10 = 264,\n\tGP_3_13_FN___10 = 265,\n\tGP_3_14_FN___10 = 266,\n\tGP_3_15_FN___10 = 267,\n\tGP_3_16_FN___6 = 268,\n\tGP_3_17_FN___3 = 269,\n\tGP_3_18_FN___3 = 270,\n\tGP_3_19_FN___2 = 271,\n\tGP_3_20_FN___2 = 272,\n\tGP_3_21_FN___2 = 273,\n\tGP_3_22_FN___2 = 274,\n\tGP_3_23_FN___2 = 275,\n\tGP_3_24_FN___2 = 276,\n\tGP_3_25_FN___2 = 277,\n\tGP_3_26_FN___2 = 278,\n\tGP_3_27_FN___2 = 279,\n\tGP_3_28_FN___2 = 280,\n\tGP_3_29_FN___2 = 281,\n\tGP_3_30_FN = 282,\n\tGP_3_31_FN = 283,\n\tGP_4_0_FN___10 = 284,\n\tGP_4_1_FN___10 = 285,\n\tGP_4_2_FN___10 = 286,\n\tGP_4_3_FN___10 = 287,\n\tGP_4_4_FN___10 = 288,\n\tGP_4_5_FN___10 = 289,\n\tGP_4_6_FN___9 = 290,\n\tGP_4_7_FN___9 = 291,\n\tGP_4_8_FN___9 = 292,\n\tGP_4_9_FN___9 = 293,\n\tGP_4_10_FN___9 = 294,\n\tGP_4_11_FN___8 = 295,\n\tGP_4_12_FN___8 = 296,\n\tGP_4_13_FN___8 = 297,\n\tGP_4_14_FN___8 = 298,\n\tGP_4_15_FN___8 = 299,\n\tGP_4_21_FN___5 = 300,\n\tGP_4_23_FN___5 = 301,\n\tGP_4_24_FN___5 = 302,\n\tGP_5_0_FN___10 = 303,\n\tGP_5_1_FN___10 = 304,\n\tGP_5_2_FN___10 = 305,\n\tGP_5_3_FN___10 = 306,\n\tGP_5_4_FN___10 = 307,\n\tGP_5_5_FN___10 = 308,\n\tGP_5_6_FN___10 = 309,\n\tGP_5_7_FN___10 = 310,\n\tGP_5_8_FN___10 = 311,\n\tGP_5_9_FN___10 = 312,\n\tGP_5_10_FN___10 = 313,\n\tGP_5_11_FN___10 = 314,\n\tGP_5_12_FN___10 = 315,\n\tGP_5_13_FN___10 = 316,\n\tGP_5_14_FN___10 = 317,\n\tGP_5_15_FN___8 = 318,\n\tGP_5_16_FN___8 = 319,\n\tGP_5_17_FN___8 = 320,\n\tGP_5_18_FN___8 = 321,\n\tGP_5_19_FN___8 = 322,\n\tGP_5_20_FN___7 = 323,\n\tGP_6_0_FN___8 = 324,\n\tGP_6_1_FN___8 = 325,\n\tGP_6_2_FN___8 = 326,\n\tGP_6_3_FN___8 = 327,\n\tGP_6_4_FN___8 = 328,\n\tGP_6_5_FN___8 = 329,\n\tGP_6_6_FN___8 = 330,\n\tGP_6_7_FN___8 = 331,\n\tGP_6_8_FN___8 = 332,\n\tGP_6_9_FN___8 = 333,\n\tGP_6_10_FN___8 = 334,\n\tGP_6_11_FN___8 = 335,\n\tGP_6_12_FN___8 = 336,\n\tGP_6_13_FN___8 = 337,\n\tGP_6_14_FN___7 = 338,\n\tGP_6_15_FN___7 = 339,\n\tGP_6_16_FN___7 = 340,\n\tGP_6_17_FN___7 = 341,\n\tGP_6_18_FN___6 = 342,\n\tGP_6_19_FN___6 = 343,\n\tGP_6_20_FN___6 = 344,\n\tGP_7_0_FN___6 = 345,\n\tGP_7_1_FN___6 = 346,\n\tGP_7_2_FN___6 = 347,\n\tGP_7_3_FN___6 = 348,\n\tGP_7_4_FN___3 = 349,\n\tGP_7_5_FN___3 = 350,\n\tGP_7_6_FN___3 = 351,\n\tGP_7_7_FN___3 = 352,\n\tGP_7_8_FN___3 = 353,\n\tGP_7_9_FN___3 = 354,\n\tGP_7_10_FN___3 = 355,\n\tGP_7_11_FN___3 = 356,\n\tGP_7_12_FN___3 = 357,\n\tGP_7_13_FN___3 = 358,\n\tGP_7_14_FN___3 = 359,\n\tGP_7_15_FN___3 = 360,\n\tGP_7_16_FN___3 = 361,\n\tGP_7_17_FN___3 = 362,\n\tGP_7_18_FN___3 = 363,\n\tGP_7_19_FN___3 = 364,\n\tGP_7_20_FN___3 = 365,\n\tFN_IP0SR0_3_0___3 = 366,\n\tFN_ERROROUTC_N_B___2 = 367,\n\tFN_TCLK2_B___10 = 368,\n\tFN_IP1SR0_3_0___3 = 369,\n\tFN_MSIOF5_SS1___3 = 370,\n\tFN_IP2SR0_3_0___3 = 371,\n\tFN_MSIOF2_TXD___7 = 372,\n\tFN_HCTS1_N_A___5 = 373,\n\tFN_CTS1_N_A___2 = 374,\n\tFN_IP0SR0_7_4___3 = 375,\n\tFN_MSIOF3_SS1___6 = 376,\n\tFN_IP1SR0_7_4___3 = 377,\n\tFN_MSIOF5_SYNC___3 = 378,\n\tFN_IP2SR0_7_4___3 = 379,\n\tFN_MSIOF2_SCK___7 = 380,\n\tFN_HRTS1_N_A___5 = 381,\n\tFN_RTS1_N_A___2 = 382,\n\tFN_IP0SR0_11_8___3 = 383,\n\tFN_MSIOF3_SS2___6 = 384,\n\tFN_IP1SR0_11_8___3 = 385,\n\tFN_MSIOF5_TXD___3 = 386,\n\tFN_IP2SR0_11_8___3 = 387,\n\tFN_MSIOF2_RXD___7 = 388,\n\tFN_HSCK1_A___6 = 389,\n\tFN_SCK1_A___3 = 390,\n\tFN_IP0SR0_15_12___3 = 391,\n\tFN_IRQ3_A___3 = 392,\n\tFN_MSIOF3_SCK___6 = 393,\n\tFN_IP1SR0_15_12___3 = 394,\n\tFN_MSIOF5_SCK___3 = 395,\n\tFN_IP0SR0_19_16___3 = 396,\n\tFN_IRQ2_A___3 = 397,\n\tFN_MSIOF3_TXD___6 = 398,\n\tFN_IP1SR0_19_16___3 = 399,\n\tFN_MSIOF5_RXD___3 = 400,\n\tFN_IP0SR0_23_20___3 = 401,\n\tFN_IRQ1_A___3 = 402,\n\tFN_MSIOF3_RXD___6 = 403,\n\tFN_IP1SR0_23_20___3 = 404,\n\tFN_MSIOF2_SS2___7 = 405,\n\tFN_TCLK1_A___10 = 406,\n\tFN_IRQ2_B___3 = 407,\n\tFN_IP0SR0_27_24___3 = 408,\n\tFN_IRQ0_A___3 = 409,\n\tFN_MSIOF3_SYNC___6 = 410,\n\tFN_IP1SR0_27_24___3 = 411,\n\tFN_MSIOF2_SS1___7 = 412,\n\tFN_HTX1_A___6 = 413,\n\tFN_TX1_A___9 = 414,\n\tFN_IP0SR0_31_28___3 = 415,\n\tFN_MSIOF5_SS2___3 = 416,\n\tFN_IP1SR0_31_28___3 = 417,\n\tFN_MSIOF2_SYNC___6 = 418,\n\tFN_HRX1_A___6 = 419,\n\tFN_RX1_A___9 = 420,\n\tFN_IP0SR1_3_0___4 = 421,\n\tFN_MSIOF1_SS2___8 = 422,\n\tFN_HTX3_B___7 = 423,\n\tFN_TX3_B___7 = 424,\n\tFN_IP1SR1_3_0___3 = 425,\n\tFN_MSIOF0_SYNC___11 = 426,\n\tFN_HCTS1_N_B___6 = 427,\n\tFN_CTS1_N_B___2 = 428,\n\tFN_IP2SR1_3_0___3 = 429,\n\tFN_HRX0___9 = 430,\n\tFN_RX0___9 = 431,\n\tFN_IP3SR1_3_0___3 = 432,\n\tFN_HRX3_A___7 = 433,\n\tFN_SCK3_A___4 = 434,\n\tFN_MSIOF4_SS2___3 = 435,\n\tFN_IP0SR1_7_4___4 = 436,\n\tFN_MSIOF1_SS1___8 = 437,\n\tFN_HCTS3_N_B___2 = 438,\n\tFN_RX3_B___7 = 439,\n\tFN_IP1SR1_7_4___3 = 440,\n\tFN_MSIOF0_TXD___11 = 441,\n\tFN_HRTS1_N_B___6 = 442,\n\tFN_RTS1_N_B___2 = 443,\n\tFN_IP2SR1_7_4___3 = 444,\n\tFN_SCIF_CLK___5 = 445,\n\tFN_IRQ4_A___3 = 446,\n\tFN_IP3SR1_7_4___3 = 447,\n\tFN_HSCK3_A___3 = 448,\n\tFN_CTS3_N_A___3 = 449,\n\tFN_MSIOF4_SCK___3 = 450,\n\tFN_TPU0TO0_B___3 = 451,\n\tFN_IP0SR1_11_8___4 = 452,\n\tFN_MSIOF1_SYNC___8 = 453,\n\tFN_HRTS3_N_B___2 = 454,\n\tFN_RTS3_N_B___2 = 455,\n\tFN_IP1SR1_11_8___3 = 456,\n\tFN_MSIOF0_SCK___11 = 457,\n\tFN_HSCK1_B___6 = 458,\n\tFN_SCK1_B___3 = 459,\n\tFN_IP2SR1_11_8___3 = 460,\n\tFN_SSI_SCK___2 = 461,\n\tFN_TCLK3_B___2 = 462,\n\tFN_IP3SR1_11_8___3 = 463,\n\tFN_HRTS3_N_A___2 = 464,\n\tFN_RTS3_N_A___3 = 465,\n\tFN_MSIOF4_TXD___3 = 466,\n\tFN_TPU0TO1_B___3 = 467,\n\tFN_IP0SR1_15_12___4 = 468,\n\tFN_MSIOF1_SCK___8 = 469,\n\tFN_HSCK3_B___4 = 470,\n\tFN_CTS3_N_B___2 = 471,\n\tFN_IP1SR1_15_12___3 = 472,\n\tFN_MSIOF0_RXD___11 = 473,\n\tFN_IP2SR1_15_12___3 = 474,\n\tFN_SSI_WS___2 = 475,\n\tFN_TCLK4_B___2 = 476,\n\tFN_IP3SR1_15_12___3 = 477,\n\tFN_HCTS3_N_A___2 = 478,\n\tFN_RX3_A___7 = 479,\n\tFN_MSIOF4_RXD___3 = 480,\n\tFN_IP0SR1_19_16___4 = 481,\n\tFN_MSIOF1_TXD___8 = 482,\n\tFN_HRX3_B___7 = 483,\n\tFN_SCK3_B___3 = 484,\n\tFN_IP1SR1_19_16___3 = 485,\n\tFN_HTX0___9 = 486,\n\tFN_TX0___9 = 487,\n\tFN_IP2SR1_19_16___3 = 488,\n\tFN_SSI_SD___2 = 489,\n\tFN_IRQ0_B___3 = 490,\n\tFN_IP3SR1_19_16___3 = 491,\n\tFN_HTX3_A___7 = 492,\n\tFN_TX3_A___7 = 493,\n\tFN_MSIOF4_SYNC___3 = 494,\n\tFN_IP0SR1_23_20___4 = 495,\n\tFN_MSIOF1_RXD___8 = 496,\n\tFN_IP1SR1_23_20___3 = 497,\n\tFN_HCTS0_N___9 = 498,\n\tFN_CTS0_N___10 = 499,\n\tFN_IP2SR1_23_20___3 = 500,\n\tFN_AUDIO_CLKOUT___3 = 501,\n\tFN_IRQ1_B___3 = 502,\n\tFN_IP3SR1_23_20___2 = 503,\n\tFN_ERROROUTC_N_A___2 = 504,\n\tFN_IP0SR1_27_24___4 = 505,\n\tFN_MSIOF0_SS2___11 = 506,\n\tFN_HTX1_B___6 = 507,\n\tFN_TX1_B___9 = 508,\n\tFN_IP1SR1_27_24___3 = 509,\n\tFN_HRTS0_N___9 = 510,\n\tFN_RTS0_N___10 = 511,\n\tFN_PWM0_B___5 = 512,\n\tFN_IP2SR1_27_24___3 = 513,\n\tFN_AUDIO_CLKIN___2 = 514,\n\tFN_PWM3_C___3 = 515,\n\tFN_IP0SR1_31_28___4 = 516,\n\tFN_MSIOF0_SS1___11 = 517,\n\tFN_HRX1_B___6 = 518,\n\tFN_RX1_B___9 = 519,\n\tFN_IP1SR1_31_28___3 = 520,\n\tFN_HSCK0___9 = 521,\n\tFN_SCK0___9 = 522,\n\tFN_PWM0_A___5 = 523,\n\tFN_IP2SR1_31_28___3 = 524,\n\tFN_TCLK2_A___10 = 525,\n\tFN_MSIOF4_SS1___3 = 526,\n\tFN_IRQ3_B___3 = 527,\n\tFN_IP0SR2_3_0___3 = 528,\n\tFN_FXR_TXDA___4 = 529,\n\tFN_TPU0TO2_B___3 = 530,\n\tFN_IP1SR2_3_0___3 = 531,\n\tFN_TPU0TO0_A___3 = 532,\n\tFN_TCLK1_B___10 = 533,\n\tFN_IP0SR2_7_4___3 = 534,\n\tFN_FXR_TXENA_N_A___2 = 535,\n\tFN_TPU0TO3_B___3 = 536,\n\tFN_IP1SR2_7_4___3 = 537,\n\tFN_CAN_CLK___8 = 538,\n\tFN_FXR_TXENA_N_B___2 = 539,\n\tFN_IP2SR2_7_4___3 = 540,\n\tFN_CANFD1_TX___10 = 541,\n\tFN_PWM1_C___2 = 542,\n\tFN_IP0SR2_11_8___3 = 543,\n\tFN_RXDA_EXTFXR___4 = 544,\n\tFN_IRQ5___10 = 545,\n\tFN_IP1SR2_11_8___3 = 546,\n\tFN_CANFD0_TX___5 = 547,\n\tFN_FXR_TXENB_N_B___2 = 548,\n\tFN_IP0SR2_15_12___3 = 549,\n\tFN_CLK_EXTFXR___5 = 550,\n\tFN_IRQ4_B___3 = 551,\n\tFN_IP1SR2_15_12___3 = 552,\n\tFN_CANFD0_RX___5 = 553,\n\tFN_IP2SR2_15_12___3 = 554,\n\tFN_CANFD1_RX___10 = 555,\n\tFN_PWM2_C___3 = 556,\n\tFN_IP0SR2_19_16___3 = 557,\n\tFN_RXDB_EXTFXR___5 = 558,\n\tFN_IP1SR2_19_16___3 = 559,\n\tFN_CANFD2_TX___3 = 560,\n\tFN_TPU0TO2_A___3 = 561,\n\tFN_TCLK3_C___2 = 562,\n\tFN_IP0SR2_23_20___3 = 563,\n\tFN_FXR_TXENB_N_A___2 = 564,\n\tFN_IP1SR2_23_20___3 = 565,\n\tFN_CANFD2_RX___3 = 566,\n\tFN_TPU0TO3_A___3 = 567,\n\tFN_PWM1_B___9 = 568,\n\tFN_TCLK4_C___2 = 569,\n\tFN_IP0SR2_27_24___3 = 570,\n\tFN_FXR_TXDB___5 = 571,\n\tFN_IP1SR2_27_24___3 = 572,\n\tFN_CANFD3_TX___3 = 573,\n\tFN_PWM2_B___8 = 574,\n\tFN_IP0SR2_31_28___3 = 575,\n\tFN_TPU0TO1_A___3 = 576,\n\tFN_TCLK2_C___2 = 577,\n\tFN_IP1SR2_31_28___3 = 578,\n\tFN_CANFD3_RX___3 = 579,\n\tFN_PWM3_B___9 = 580,\n\tFN_IP0SR3_3_0___2 = 581,\n\tFN_MMC_SD_D1___4 = 582,\n\tFN_IP1SR3_3_0___3 = 583,\n\tFN_MMC_D7___7 = 584,\n\tFN_IP2SR3_3_0___2 = 585,\n\tFN_QSPI0_IO3___8 = 586,\n\tFN_IP3SR3_3_0___2 = 587,\n\tFN_QSPI1_IO2___8 = 588,\n\tFN_IP0SR3_7_4___3 = 589,\n\tFN_MMC_SD_D0___4 = 590,\n\tFN_IP1SR3_7_4___3 = 591,\n\tFN_MMC_D6___7 = 592,\n\tFN_IP2SR3_7_4___2 = 593,\n\tFN_QSPI0_IO2___8 = 594,\n\tFN_IP3SR3_7_4___2 = 595,\n\tFN_QSPI1_SSL___8 = 596,\n\tFN_IP0SR3_11_8___3 = 597,\n\tFN_MMC_SD_D2___4 = 598,\n\tFN_IP1SR3_11_8___3 = 599,\n\tFN_MMC_SD_CMD___4 = 600,\n\tFN_IP2SR3_11_8___2 = 601,\n\tFN_QSPI0_MISO_IO1___8 = 602,\n\tFN_IP3SR3_11_8___2 = 603,\n\tFN_QSPI1_IO3___8 = 604,\n\tFN_IP0SR3_15_12___2 = 605,\n\tFN_MMC_SD_CLK___4 = 606,\n\tFN_IP1SR3_15_12___3 = 607,\n\tFN_SD_CD___4 = 608,\n\tFN_IP2SR3_15_12___2 = 609,\n\tFN_QSPI0_MOSI_IO0___8 = 610,\n\tFN_IP3SR3_15_12___2 = 611,\n\tFN_RPC_RESET_N___8 = 612,\n\tFN_IP0SR3_19_16___2 = 613,\n\tFN_MMC_DS___5 = 614,\n\tFN_IP1SR3_19_16___3 = 615,\n\tFN_SD_WP___4 = 616,\n\tFN_IP2SR3_19_16___2 = 617,\n\tFN_QSPI0_SPCLK___8 = 618,\n\tFN_IP3SR3_19_16___2 = 619,\n\tFN_RPC_WP_N___6 = 620,\n\tFN_IP0SR3_23_20___3 = 621,\n\tFN_MMC_SD_D3___4 = 622,\n\tFN_IP1SR3_23_20___3 = 623,\n\tFN_PWM1_A___9 = 624,\n\tFN_IP2SR3_23_20___2 = 625,\n\tFN_QSPI1_MOSI_IO0___8 = 626,\n\tFN_IP3SR3_23_20___2 = 627,\n\tFN_RPC_INT_N___8 = 628,\n\tFN_IP0SR3_27_24___3 = 629,\n\tFN_MMC_D5___7 = 630,\n\tFN_IP1SR3_27_24___2 = 631,\n\tFN_PWM2_A___8 = 632,\n\tFN_IP2SR3_27_24___2 = 633,\n\tFN_QSPI1_SPCLK___8 = 634,\n\tFN_IP3SR3_27_24 = 635,\n\tFN_TCLK3_A___2 = 636,\n\tFN_IP0SR3_31_28___3 = 637,\n\tFN_MMC_D4___7 = 638,\n\tFN_IP1SR3_31_28___2 = 639,\n\tFN_QSPI0_SSL___8 = 640,\n\tFN_IP2SR3_31_28___2 = 641,\n\tFN_QSPI1_MISO_IO1___8 = 642,\n\tFN_IP3SR3_31_28 = 643,\n\tFN_TCLK4_A___2 = 644,\n\tFN_IP0SR4_3_0___3 = 645,\n\tFN_SCL0___5 = 646,\n\tFN_IP1SR4_3_0___3 = 647,\n\tFN_HRX2___6 = 648,\n\tFN_SCK4___6 = 649,\n\tFN_IP3SR4_3_0___2 = 650,\n\tFN_AVS1___6 = 651,\n\tFN_IP0SR4_7_4___3 = 652,\n\tFN_SDA0___5 = 653,\n\tFN_IP1SR4_7_4___3 = 654,\n\tFN_HTX2___6 = 655,\n\tFN_CTS4_N___6 = 656,\n\tFN_IP0SR4_11_8___3 = 657,\n\tFN_SCL1___5 = 658,\n\tFN_IP1SR4_11_8___3 = 659,\n\tFN_HRTS2_N___6 = 660,\n\tFN_RTS4_N___6 = 661,\n\tFN_IP0SR4_15_12___3 = 662,\n\tFN_SDA1___5 = 663,\n\tFN_IP1SR4_15_12___3 = 664,\n\tFN_SCIF_CLK2___2 = 665,\n\tFN_IP0SR4_19_16___3 = 666,\n\tFN_SCL2___4 = 667,\n\tFN_IP1SR4_19_16___3 = 668,\n\tFN_HCTS2_N___6 = 669,\n\tFN_TX4___6 = 670,\n\tFN_IP0SR4_23_20___3 = 671,\n\tFN_SDA2___4 = 672,\n\tFN_IP1SR4_23_20___3 = 673,\n\tFN_HSCK2___6 = 674,\n\tFN_RX4___6 = 675,\n\tFN_IP2SR4_23_20___2 = 676,\n\tFN_PCIE0_CLKREQ_N___4 = 677,\n\tFN_IP0SR4_27_24___3 = 678,\n\tFN_SCL3___3 = 679,\n\tFN_IP1SR4_27_24___3 = 680,\n\tFN_PWM3_A___9 = 681,\n\tFN_IP0SR4_31_28___3 = 682,\n\tFN_SDA3___3 = 683,\n\tFN_IP1SR4_31_28___3 = 684,\n\tFN_PWM4___3 = 685,\n\tFN_IP2SR4_31_28___2 = 686,\n\tFN_AVS0___3 = 687,\n\tFN_IP0SR5_3_0___3 = 688,\n\tFN_AVB2_AVTP_PPS___3 = 689,\n\tFN_Ether_GPTP_PPS0 = 690,\n\tFN_IP1SR5_3_0___3 = 691,\n\tFN_AVB2_TD3___3 = 692,\n\tFN_IP2SR5_3_0___2 = 693,\n\tFN_AVB2_TXC___3 = 694,\n\tFN_IP0SR5_7_4___3 = 695,\n\tFN_AVB2_AVTP_CAPTURE___3 = 696,\n\tFN_Ether_GPTP_CAPTURE = 697,\n\tFN_IP1SR5_7_4___3 = 698,\n\tFN_AVB2_RD3___3 = 699,\n\tFN_IP2SR5_7_4___3 = 700,\n\tFN_AVB2_RD0___3 = 701,\n\tFN_IP0SR5_11_8___3 = 702,\n\tFN_AVB2_AVTP_MATCH___3 = 703,\n\tFN_Ether_GPTP_MATCH = 704,\n\tFN_IP1SR5_11_8___3 = 705,\n\tFN_AVB2_MDIO___3 = 706,\n\tFN_IP2SR5_11_8___3 = 707,\n\tFN_AVB2_RXC___3 = 708,\n\tFN_IP0SR5_15_12___3 = 709,\n\tFN_AVB2_LINK___3 = 710,\n\tFN_IP1SR5_15_12___3 = 711,\n\tFN_AVB2_TD2___3 = 712,\n\tFN_IP2SR5_15_12___3 = 713,\n\tFN_AVB2_TX_CTL___3 = 714,\n\tFN_IP0SR5_19_16___3 = 715,\n\tFN_AVB2_PHY_INT___3 = 716,\n\tFN_IP1SR5_19_16___3 = 717,\n\tFN_AVB2_TD1___3 = 718,\n\tFN_IP2SR5_19_16___3 = 719,\n\tFN_AVB2_RX_CTL___3 = 720,\n\tFN_IP0SR5_23_20___3 = 721,\n\tFN_AVB2_MAGIC___3 = 722,\n\tFN_Ether_GPTP_PPS1 = 723,\n\tFN_IP1SR5_23_20___3 = 724,\n\tFN_AVB2_RD2___3 = 725,\n\tFN_IP0SR5_27_24___3 = 726,\n\tFN_AVB2_MDC___3 = 727,\n\tFN_IP1SR5_27_24___3 = 728,\n\tFN_AVB2_RD1___3 = 729,\n\tFN_IP0SR5_31_28___3 = 730,\n\tFN_AVB2_TXCREFCLK___3 = 731,\n\tFN_IP1SR5_31_28___3 = 732,\n\tFN_AVB2_TD0___3 = 733,\n\tFN_IP0SR6_3_0___2 = 734,\n\tFN_AVB1_MDIO___3 = 735,\n\tFN_IP1SR6_3_0___2 = 736,\n\tFN_AVB1_RXC___3 = 737,\n\tFN_AVB1_MII_RXC___2 = 738,\n\tFN_IP2SR6_3_0___2 = 739,\n\tFN_AVB1_TD2___3 = 740,\n\tFN_AVB1_MII_TD2___2 = 741,\n\tFN_IP0SR6_7_4___2 = 742,\n\tFN_AVB1_MAGIC___3 = 743,\n\tFN_IP1SR6_7_4___2 = 744,\n\tFN_AVB1_RX_CTL___3 = 745,\n\tFN_AVB1_MII_RX_DV___2 = 746,\n\tFN_IP2SR6_7_4___2 = 747,\n\tFN_AVB1_RD2___3 = 748,\n\tFN_AVB1_MII_RD2___2 = 749,\n\tFN_IP0SR6_11_8___2 = 750,\n\tFN_AVB1_MDC___3 = 751,\n\tFN_IP1SR6_11_8___2 = 752,\n\tFN_AVB1_AVTP_PPS___3 = 753,\n\tFN_AVB1_MII_COL___2 = 754,\n\tFN_IP2SR6_11_8___2 = 755,\n\tFN_AVB1_TD3___3 = 756,\n\tFN_AVB1_MII_TD3___2 = 757,\n\tFN_IP0SR6_15_12___2 = 758,\n\tFN_AVB1_PHY_INT___3 = 759,\n\tFN_IP1SR6_15_12___2 = 760,\n\tFN_AVB1_AVTP_CAPTURE___3 = 761,\n\tFN_AVB1_MII_CRS___2 = 762,\n\tFN_IP2SR6_15_12___2 = 763,\n\tFN_AVB1_RD3___3 = 764,\n\tFN_AVB1_MII_RD3___2 = 765,\n\tFN_IP0SR6_19_16___2 = 766,\n\tFN_AVB1_LINK___3 = 767,\n\tFN_AVB1_MII_TX_ER___2 = 768,\n\tFN_IP1SR6_19_16___2 = 769,\n\tFN_AVB1_TD1___3 = 770,\n\tFN_AVB1_MII_TD1___2 = 771,\n\tFN_IP2SR6_19_16___2 = 772,\n\tFN_AVB1_TXCREFCLK___3 = 773,\n\tFN_IP0SR6_23_20___2 = 774,\n\tFN_AVB1_AVTP_MATCH___3 = 775,\n\tFN_AVB1_MII_RX_ER___2 = 776,\n\tFN_IP1SR6_23_20___2 = 777,\n\tFN_AVB1_TD0___3 = 778,\n\tFN_AVB1_MII_TD0___2 = 779,\n\tFN_IP0SR6_27_24___2 = 780,\n\tFN_AVB1_TXC___3 = 781,\n\tFN_AVB1_MII_TXC___2 = 782,\n\tFN_IP1SR6_27_24___2 = 783,\n\tFN_AVB1_RD1___3 = 784,\n\tFN_AVB1_MII_RD1___2 = 785,\n\tFN_IP0SR6_31_28___2 = 786,\n\tFN_AVB1_TX_CTL___3 = 787,\n\tFN_AVB1_MII_TX_EN___2 = 788,\n\tFN_IP1SR6_31_28___2 = 789,\n\tFN_AVB1_RD0___3 = 790,\n\tFN_AVB1_MII_RD0___2 = 791,\n\tFN_IP0SR7_3_0___2 = 792,\n\tFN_AVB0_AVTP_PPS___4 = 793,\n\tFN_AVB0_MII_COL___2 = 794,\n\tFN_IP1SR7_3_0___2 = 795,\n\tFN_AVB0_RD3___5 = 796,\n\tFN_AVB0_MII_RD3___2 = 797,\n\tFN_IP2SR7_3_0___2 = 798,\n\tFN_AVB0_TX_CTL___5 = 799,\n\tFN_AVB0_MII_TX_EN___2 = 800,\n\tFN_IP0SR7_7_4___2 = 801,\n\tFN_AVB0_AVTP_CAPTURE___4 = 802,\n\tFN_AVB0_MII_CRS___2 = 803,\n\tFN_IP1SR7_7_4___2 = 804,\n\tFN_AVB0_TXCREFCLK___5 = 805,\n\tFN_IP2SR7_7_4___2 = 806,\n\tFN_AVB0_RD1___5 = 807,\n\tFN_AVB0_MII_RD1___2 = 808,\n\tFN_IP0SR7_11_8___2 = 809,\n\tFN_AVB0_AVTP_MATCH___4 = 810,\n\tFN_AVB0_MII_RX_ER___2 = 811,\n\tFN_IP1SR7_11_8___2 = 812,\n\tFN_AVB0_MAGIC___5 = 813,\n\tFN_IP2SR7_11_8___2 = 814,\n\tFN_AVB0_RD0___5 = 815,\n\tFN_AVB0_MII_RD0___2 = 816,\n\tFN_IP0SR7_15_12___2 = 817,\n\tFN_AVB0_TD3___5 = 818,\n\tFN_AVB0_MII_TD3___2 = 819,\n\tFN_IP1SR7_15_12___2 = 820,\n\tFN_AVB0_TD0___5 = 821,\n\tFN_AVB0_MII_TD0___2 = 822,\n\tFN_IP2SR7_15_12___2 = 823,\n\tFN_AVB0_RXC___5 = 824,\n\tFN_AVB0_MII_RXC___2 = 825,\n\tFN_IP0SR7_19_16___2 = 826,\n\tFN_AVB0_LINK___5 = 827,\n\tFN_AVB0_MII_TX_ER___2 = 828,\n\tFN_IP1SR7_19_16___2 = 829,\n\tFN_AVB0_RD2___5 = 830,\n\tFN_AVB0_MII_RD2___2 = 831,\n\tFN_IP2SR7_19_16___2 = 832,\n\tFN_AVB0_RX_CTL___5 = 833,\n\tFN_AVB0_MII_RX_DV___2 = 834,\n\tFN_IP0SR7_23_20___2 = 835,\n\tFN_AVB0_PHY_INT___5 = 836,\n\tFN_IP1SR7_23_20___2 = 837,\n\tFN_AVB0_MDC___5 = 838,\n\tFN_IP0SR7_27_24___2 = 839,\n\tFN_AVB0_TD2___5 = 840,\n\tFN_AVB0_MII_TD2___2 = 841,\n\tFN_IP1SR7_27_24___2 = 842,\n\tFN_AVB0_MDIO___5 = 843,\n\tFN_IP0SR7_31_28___2 = 844,\n\tFN_AVB0_TD1___5 = 845,\n\tFN_AVB0_MII_TD1___2 = 846,\n\tFN_IP1SR7_31_28___2 = 847,\n\tFN_AVB0_TXC___5 = 848,\n\tFN_AVB0_MII_TXC___2 = 849,\n\tFN_SEL_SDA3_0___2 = 850,\n\tFN_SEL_SDA3_1___2 = 851,\n\tFN_SEL_SCL3_0___2 = 852,\n\tFN_SEL_SCL3_1___2 = 853,\n\tFN_SEL_SDA2_0___2 = 854,\n\tFN_SEL_SDA2_1___2 = 855,\n\tFN_SEL_SCL2_0___2 = 856,\n\tFN_SEL_SCL2_1___2 = 857,\n\tFN_SEL_SDA1_0___2 = 858,\n\tFN_SEL_SDA1_1___2 = 859,\n\tFN_SEL_SCL1_0___2 = 860,\n\tFN_SEL_SCL1_1___2 = 861,\n\tFN_SEL_SDA0_0___2 = 862,\n\tFN_SEL_SDA0_1___2 = 863,\n\tFN_SEL_SCL0_0___2 = 864,\n\tFN_SEL_SCL0_1___2 = 865,\n\tPINMUX_FUNCTION_END___11 = 866,\n\tPINMUX_MARK_BEGIN___11 = 867,\n\tIP0SR0_3_0_MARK___3 = 868,\n\tERROROUTC_N_B_MARK___2 = 869,\n\tTCLK2_B_MARK___10 = 870,\n\tIP1SR0_3_0_MARK___3 = 871,\n\tMSIOF5_SS1_MARK___3 = 872,\n\tIP2SR0_3_0_MARK___3 = 873,\n\tMSIOF2_TXD_MARK___7 = 874,\n\tHCTS1_N_A_MARK___5 = 875,\n\tCTS1_N_A_MARK___2 = 876,\n\tIP0SR0_7_4_MARK___3 = 877,\n\tMSIOF3_SS1_MARK___6 = 878,\n\tIP1SR0_7_4_MARK___3 = 879,\n\tMSIOF5_SYNC_MARK___3 = 880,\n\tIP2SR0_7_4_MARK___3 = 881,\n\tMSIOF2_SCK_MARK___7 = 882,\n\tHRTS1_N_A_MARK___5 = 883,\n\tRTS1_N_A_MARK___2 = 884,\n\tIP0SR0_11_8_MARK___3 = 885,\n\tMSIOF3_SS2_MARK___6 = 886,\n\tIP1SR0_11_8_MARK___3 = 887,\n\tMSIOF5_TXD_MARK___3 = 888,\n\tIP2SR0_11_8_MARK___3 = 889,\n\tMSIOF2_RXD_MARK___7 = 890,\n\tHSCK1_A_MARK___6 = 891,\n\tSCK1_A_MARK___3 = 892,\n\tIP0SR0_15_12_MARK___3 = 893,\n\tIRQ3_A_MARK___3 = 894,\n\tMSIOF3_SCK_MARK___6 = 895,\n\tIP1SR0_15_12_MARK___3 = 896,\n\tMSIOF5_SCK_MARK___3 = 897,\n\tIP0SR0_19_16_MARK___3 = 898,\n\tIRQ2_A_MARK___3 = 899,\n\tMSIOF3_TXD_MARK___6 = 900,\n\tIP1SR0_19_16_MARK___3 = 901,\n\tMSIOF5_RXD_MARK___3 = 902,\n\tIP0SR0_23_20_MARK___3 = 903,\n\tIRQ1_A_MARK___3 = 904,\n\tMSIOF3_RXD_MARK___6 = 905,\n\tIP1SR0_23_20_MARK___3 = 906,\n\tMSIOF2_SS2_MARK___7 = 907,\n\tTCLK1_A_MARK___10 = 908,\n\tIRQ2_B_MARK___3 = 909,\n\tIP0SR0_27_24_MARK___3 = 910,\n\tIRQ0_A_MARK___3 = 911,\n\tMSIOF3_SYNC_MARK___6 = 912,\n\tIP1SR0_27_24_MARK___3 = 913,\n\tMSIOF2_SS1_MARK___7 = 914,\n\tHTX1_A_MARK___6 = 915,\n\tTX1_A_MARK___9 = 916,\n\tIP0SR0_31_28_MARK___3 = 917,\n\tMSIOF5_SS2_MARK___3 = 918,\n\tIP1SR0_31_28_MARK___3 = 919,\n\tMSIOF2_SYNC_MARK___6 = 920,\n\tHRX1_A_MARK___6 = 921,\n\tRX1_A_MARK___9 = 922,\n\tIP0SR1_3_0_MARK___4 = 923,\n\tMSIOF1_SS2_MARK___8 = 924,\n\tHTX3_B_MARK___7 = 925,\n\tTX3_B_MARK___7 = 926,\n\tIP1SR1_3_0_MARK___3 = 927,\n\tMSIOF0_SYNC_MARK___11 = 928,\n\tHCTS1_N_B_MARK___6 = 929,\n\tCTS1_N_B_MARK___2 = 930,\n\tIP2SR1_3_0_MARK___3 = 931,\n\tHRX0_MARK___9 = 932,\n\tRX0_MARK___9 = 933,\n\tIP3SR1_3_0_MARK___3 = 934,\n\tHRX3_A_MARK___7 = 935,\n\tSCK3_A_MARK___4 = 936,\n\tMSIOF4_SS2_MARK___3 = 937,\n\tIP0SR1_7_4_MARK___4 = 938,\n\tMSIOF1_SS1_MARK___8 = 939,\n\tHCTS3_N_B_MARK___2 = 940,\n\tRX3_B_MARK___7 = 941,\n\tIP1SR1_7_4_MARK___3 = 942,\n\tMSIOF0_TXD_MARK___11 = 943,\n\tHRTS1_N_B_MARK___6 = 944,\n\tRTS1_N_B_MARK___2 = 945,\n\tIP2SR1_7_4_MARK___3 = 946,\n\tSCIF_CLK_MARK___5 = 947,\n\tIRQ4_A_MARK___3 = 948,\n\tIP3SR1_7_4_MARK___3 = 949,\n\tHSCK3_A_MARK___3 = 950,\n\tCTS3_N_A_MARK___3 = 951,\n\tMSIOF4_SCK_MARK___3 = 952,\n\tTPU0TO0_B_MARK___3 = 953,\n\tIP0SR1_11_8_MARK___4 = 954,\n\tMSIOF1_SYNC_MARK___8 = 955,\n\tHRTS3_N_B_MARK___2 = 956,\n\tRTS3_N_B_MARK___2 = 957,\n\tIP1SR1_11_8_MARK___3 = 958,\n\tMSIOF0_SCK_MARK___11 = 959,\n\tHSCK1_B_MARK___6 = 960,\n\tSCK1_B_MARK___3 = 961,\n\tIP2SR1_11_8_MARK___3 = 962,\n\tSSI_SCK_MARK___2 = 963,\n\tTCLK3_B_MARK___2 = 964,\n\tIP3SR1_11_8_MARK___3 = 965,\n\tHRTS3_N_A_MARK___2 = 966,\n\tRTS3_N_A_MARK___3 = 967,\n\tMSIOF4_TXD_MARK___3 = 968,\n\tTPU0TO1_B_MARK___3 = 969,\n\tIP0SR1_15_12_MARK___4 = 970,\n\tMSIOF1_SCK_MARK___8 = 971,\n\tHSCK3_B_MARK___4 = 972,\n\tCTS3_N_B_MARK___2 = 973,\n\tIP1SR1_15_12_MARK___3 = 974,\n\tMSIOF0_RXD_MARK___11 = 975,\n\tIP2SR1_15_12_MARK___3 = 976,\n\tSSI_WS_MARK___2 = 977,\n\tTCLK4_B_MARK___2 = 978,\n\tIP3SR1_15_12_MARK___3 = 979,\n\tHCTS3_N_A_MARK___2 = 980,\n\tRX3_A_MARK___7 = 981,\n\tMSIOF4_RXD_MARK___3 = 982,\n\tIP0SR1_19_16_MARK___4 = 983,\n\tMSIOF1_TXD_MARK___8 = 984,\n\tHRX3_B_MARK___7 = 985,\n\tSCK3_B_MARK___3 = 986,\n\tIP1SR1_19_16_MARK___3 = 987,\n\tHTX0_MARK___9 = 988,\n\tTX0_MARK___9 = 989,\n\tIP2SR1_19_16_MARK___3 = 990,\n\tSSI_SD_MARK___2 = 991,\n\tIRQ0_B_MARK___3 = 992,\n\tIP3SR1_19_16_MARK___3 = 993,\n\tHTX3_A_MARK___7 = 994,\n\tTX3_A_MARK___7 = 995,\n\tMSIOF4_SYNC_MARK___3 = 996,\n\tIP0SR1_23_20_MARK___4 = 997,\n\tMSIOF1_RXD_MARK___8 = 998,\n\tIP1SR1_23_20_MARK___3 = 999,\n\tHCTS0_N_MARK___9 = 1000,\n\tCTS0_N_MARK___10 = 1001,\n\tIP2SR1_23_20_MARK___3 = 1002,\n\tAUDIO_CLKOUT_MARK___3 = 1003,\n\tIRQ1_B_MARK___3 = 1004,\n\tIP3SR1_23_20_MARK___2 = 1005,\n\tERROROUTC_N_A_MARK___2 = 1006,\n\tIP0SR1_27_24_MARK___4 = 1007,\n\tMSIOF0_SS2_MARK___11 = 1008,\n\tHTX1_B_MARK___6 = 1009,\n\tTX1_B_MARK___9 = 1010,\n\tIP1SR1_27_24_MARK___3 = 1011,\n\tHRTS0_N_MARK___9 = 1012,\n\tRTS0_N_MARK___10 = 1013,\n\tPWM0_B_MARK___5 = 1014,\n\tIP2SR1_27_24_MARK___3 = 1015,\n\tAUDIO_CLKIN_MARK___2 = 1016,\n\tPWM3_C_MARK___3 = 1017,\n\tIP0SR1_31_28_MARK___4 = 1018,\n\tMSIOF0_SS1_MARK___11 = 1019,\n\tHRX1_B_MARK___6 = 1020,\n\tRX1_B_MARK___9 = 1021,\n\tIP1SR1_31_28_MARK___3 = 1022,\n\tHSCK0_MARK___9 = 1023,\n\tSCK0_MARK___9 = 1024,\n\tPWM0_A_MARK___5 = 1025,\n\tIP2SR1_31_28_MARK___3 = 1026,\n\tTCLK2_A_MARK___10 = 1027,\n\tMSIOF4_SS1_MARK___3 = 1028,\n\tIRQ3_B_MARK___3 = 1029,\n\tIP0SR2_3_0_MARK___3 = 1030,\n\tFXR_TXDA_MARK___4 = 1031,\n\tTPU0TO2_B_MARK___3 = 1032,\n\tIP1SR2_3_0_MARK___3 = 1033,\n\tTPU0TO0_A_MARK___3 = 1034,\n\tTCLK1_B_MARK___10 = 1035,\n\tIP0SR2_7_4_MARK___3 = 1036,\n\tFXR_TXENA_N_A_MARK___2 = 1037,\n\tTPU0TO3_B_MARK___3 = 1038,\n\tIP1SR2_7_4_MARK___3 = 1039,\n\tCAN_CLK_MARK___8 = 1040,\n\tFXR_TXENA_N_B_MARK___2 = 1041,\n\tIP2SR2_7_4_MARK___3 = 1042,\n\tCANFD1_TX_MARK___10 = 1043,\n\tPWM1_C_MARK___2 = 1044,\n\tIP0SR2_11_8_MARK___3 = 1045,\n\tRXDA_EXTFXR_MARK___4 = 1046,\n\tIRQ5_MARK___10 = 1047,\n\tIP1SR2_11_8_MARK___3 = 1048,\n\tCANFD0_TX_MARK___5 = 1049,\n\tFXR_TXENB_N_B_MARK___2 = 1050,\n\tIP0SR2_15_12_MARK___3 = 1051,\n\tCLK_EXTFXR_MARK___5 = 1052,\n\tIRQ4_B_MARK___3 = 1053,\n\tIP1SR2_15_12_MARK___3 = 1054,\n\tCANFD0_RX_MARK___5 = 1055,\n\tIP2SR2_15_12_MARK___3 = 1056,\n\tCANFD1_RX_MARK___10 = 1057,\n\tPWM2_C_MARK___3 = 1058,\n\tIP0SR2_19_16_MARK___3 = 1059,\n\tRXDB_EXTFXR_MARK___5 = 1060,\n\tIP1SR2_19_16_MARK___3 = 1061,\n\tCANFD2_TX_MARK___3 = 1062,\n\tTPU0TO2_A_MARK___3 = 1063,\n\tTCLK3_C_MARK___2 = 1064,\n\tIP0SR2_23_20_MARK___3 = 1065,\n\tFXR_TXENB_N_A_MARK___2 = 1066,\n\tIP1SR2_23_20_MARK___3 = 1067,\n\tCANFD2_RX_MARK___3 = 1068,\n\tTPU0TO3_A_MARK___3 = 1069,\n\tPWM1_B_MARK___9 = 1070,\n\tTCLK4_C_MARK___2 = 1071,\n\tIP0SR2_27_24_MARK___3 = 1072,\n\tFXR_TXDB_MARK___5 = 1073,\n\tIP1SR2_27_24_MARK___3 = 1074,\n\tCANFD3_TX_MARK___3 = 1075,\n\tPWM2_B_MARK___8 = 1076,\n\tIP0SR2_31_28_MARK___3 = 1077,\n\tTPU0TO1_A_MARK___3 = 1078,\n\tTCLK2_C_MARK___2 = 1079,\n\tIP1SR2_31_28_MARK___3 = 1080,\n\tCANFD3_RX_MARK___3 = 1081,\n\tPWM3_B_MARK___9 = 1082,\n\tIP0SR3_3_0_MARK___2 = 1083,\n\tMMC_SD_D1_MARK___4 = 1084,\n\tIP1SR3_3_0_MARK___3 = 1085,\n\tMMC_D7_MARK___7 = 1086,\n\tIP2SR3_3_0_MARK___2 = 1087,\n\tQSPI0_IO3_MARK___11 = 1088,\n\tIP3SR3_3_0_MARK___2 = 1089,\n\tQSPI1_IO2_MARK___11 = 1090,\n\tIP0SR3_7_4_MARK___3 = 1091,\n\tMMC_SD_D0_MARK___4 = 1092,\n\tIP1SR3_7_4_MARK___3 = 1093,\n\tMMC_D6_MARK___7 = 1094,\n\tIP2SR3_7_4_MARK___2 = 1095,\n\tQSPI0_IO2_MARK___11 = 1096,\n\tIP3SR3_7_4_MARK___2 = 1097,\n\tQSPI1_SSL_MARK___11 = 1098,\n\tIP0SR3_11_8_MARK___3 = 1099,\n\tMMC_SD_D2_MARK___4 = 1100,\n\tIP1SR3_11_8_MARK___3 = 1101,\n\tMMC_SD_CMD_MARK___4 = 1102,\n\tIP2SR3_11_8_MARK___2 = 1103,\n\tQSPI0_MISO_IO1_MARK___11 = 1104,\n\tIP3SR3_11_8_MARK___2 = 1105,\n\tQSPI1_IO3_MARK___11 = 1106,\n\tIP0SR3_15_12_MARK___2 = 1107,\n\tMMC_SD_CLK_MARK___4 = 1108,\n\tIP1SR3_15_12_MARK___3 = 1109,\n\tSD_CD_MARK___4 = 1110,\n\tIP2SR3_15_12_MARK___2 = 1111,\n\tQSPI0_MOSI_IO0_MARK___11 = 1112,\n\tIP3SR3_15_12_MARK___2 = 1113,\n\tRPC_RESET_N_MARK___8 = 1114,\n\tIP0SR3_19_16_MARK___2 = 1115,\n\tMMC_DS_MARK___5 = 1116,\n\tIP1SR3_19_16_MARK___3 = 1117,\n\tSD_WP_MARK___4 = 1118,\n\tIP2SR3_19_16_MARK___2 = 1119,\n\tQSPI0_SPCLK_MARK___11 = 1120,\n\tIP3SR3_19_16_MARK___2 = 1121,\n\tRPC_WP_N_MARK___6 = 1122,\n\tIP0SR3_23_20_MARK___3 = 1123,\n\tMMC_SD_D3_MARK___4 = 1124,\n\tIP1SR3_23_20_MARK___3 = 1125,\n\tPWM1_A_MARK___9 = 1126,\n\tIP2SR3_23_20_MARK___2 = 1127,\n\tQSPI1_MOSI_IO0_MARK___11 = 1128,\n\tIP3SR3_23_20_MARK___2 = 1129,\n\tRPC_INT_N_MARK___8 = 1130,\n\tIP0SR3_27_24_MARK___3 = 1131,\n\tMMC_D5_MARK___7 = 1132,\n\tIP1SR3_27_24_MARK___2 = 1133,\n\tPWM2_A_MARK___8 = 1134,\n\tIP2SR3_27_24_MARK___2 = 1135,\n\tQSPI1_SPCLK_MARK___11 = 1136,\n\tIP3SR3_27_24_MARK = 1137,\n\tTCLK3_A_MARK___2 = 1138,\n\tIP0SR3_31_28_MARK___3 = 1139,\n\tMMC_D4_MARK___7 = 1140,\n\tIP1SR3_31_28_MARK___2 = 1141,\n\tQSPI0_SSL_MARK___11 = 1142,\n\tIP2SR3_31_28_MARK___2 = 1143,\n\tQSPI1_MISO_IO1_MARK___11 = 1144,\n\tIP3SR3_31_28_MARK = 1145,\n\tTCLK4_A_MARK___2 = 1146,\n\tIP0SR4_3_0_MARK___3 = 1147,\n\tSCL0_MARK___10 = 1148,\n\tIP1SR4_3_0_MARK___3 = 1149,\n\tHRX2_MARK___6 = 1150,\n\tSCK4_MARK___6 = 1151,\n\tIP3SR4_3_0_MARK___2 = 1152,\n\tAVS1_MARK___6 = 1153,\n\tIP0SR4_7_4_MARK___3 = 1154,\n\tSDA0_MARK___10 = 1155,\n\tIP1SR4_7_4_MARK___3 = 1156,\n\tHTX2_MARK___6 = 1157,\n\tCTS4_N_MARK___6 = 1158,\n\tIP0SR4_11_8_MARK___3 = 1159,\n\tSCL1_MARK___7 = 1160,\n\tIP1SR4_11_8_MARK___3 = 1161,\n\tHRTS2_N_MARK___6 = 1162,\n\tRTS4_N_MARK___6 = 1163,\n\tIP0SR4_15_12_MARK___3 = 1164,\n\tSDA1_MARK___7 = 1165,\n\tIP1SR4_15_12_MARK___3 = 1166,\n\tSCIF_CLK2_MARK___2 = 1167,\n\tIP0SR4_19_16_MARK___3 = 1168,\n\tSCL2_MARK___6 = 1169,\n\tIP1SR4_19_16_MARK___3 = 1170,\n\tHCTS2_N_MARK___6 = 1171,\n\tTX4_MARK___6 = 1172,\n\tIP0SR4_23_20_MARK___3 = 1173,\n\tSDA2_MARK___6 = 1174,\n\tIP1SR4_23_20_MARK___3 = 1175,\n\tHSCK2_MARK___6 = 1176,\n\tRX4_MARK___6 = 1177,\n\tIP2SR4_23_20_MARK___2 = 1178,\n\tPCIE0_CLKREQ_N_MARK___4 = 1179,\n\tIP0SR4_27_24_MARK___3 = 1180,\n\tSCL3_MARK___8 = 1181,\n\tIP1SR4_27_24_MARK___3 = 1182,\n\tPWM3_A_MARK___9 = 1183,\n\tIP0SR4_31_28_MARK___3 = 1184,\n\tSDA3_MARK___8 = 1185,\n\tIP1SR4_31_28_MARK___3 = 1186,\n\tPWM4_MARK___3 = 1187,\n\tIP2SR4_31_28_MARK___2 = 1188,\n\tAVS0_MARK___3 = 1189,\n\tIP0SR5_3_0_MARK___3 = 1190,\n\tAVB2_AVTP_PPS_MARK___3 = 1191,\n\tEther_GPTP_PPS0_MARK = 1192,\n\tIP1SR5_3_0_MARK___3 = 1193,\n\tAVB2_TD3_MARK___3 = 1194,\n\tIP2SR5_3_0_MARK___2 = 1195,\n\tAVB2_TXC_MARK___3 = 1196,\n\tIP0SR5_7_4_MARK___3 = 1197,\n\tAVB2_AVTP_CAPTURE_MARK___3 = 1198,\n\tEther_GPTP_CAPTURE_MARK = 1199,\n\tIP1SR5_7_4_MARK___3 = 1200,\n\tAVB2_RD3_MARK___3 = 1201,\n\tIP2SR5_7_4_MARK___3 = 1202,\n\tAVB2_RD0_MARK___3 = 1203,\n\tIP0SR5_11_8_MARK___3 = 1204,\n\tAVB2_AVTP_MATCH_MARK___3 = 1205,\n\tEther_GPTP_MATCH_MARK = 1206,\n\tIP1SR5_11_8_MARK___3 = 1207,\n\tAVB2_MDIO_MARK___3 = 1208,\n\tIP2SR5_11_8_MARK___3 = 1209,\n\tAVB2_RXC_MARK___3 = 1210,\n\tIP0SR5_15_12_MARK___3 = 1211,\n\tAVB2_LINK_MARK___3 = 1212,\n\tIP1SR5_15_12_MARK___3 = 1213,\n\tAVB2_TD2_MARK___3 = 1214,\n\tIP2SR5_15_12_MARK___3 = 1215,\n\tAVB2_TX_CTL_MARK___3 = 1216,\n\tIP0SR5_19_16_MARK___3 = 1217,\n\tAVB2_PHY_INT_MARK___3 = 1218,\n\tIP1SR5_19_16_MARK___3 = 1219,\n\tAVB2_TD1_MARK___3 = 1220,\n\tIP2SR5_19_16_MARK___3 = 1221,\n\tAVB2_RX_CTL_MARK___3 = 1222,\n\tIP0SR5_23_20_MARK___3 = 1223,\n\tAVB2_MAGIC_MARK___3 = 1224,\n\tEther_GPTP_PPS1_MARK = 1225,\n\tIP1SR5_23_20_MARK___3 = 1226,\n\tAVB2_RD2_MARK___3 = 1227,\n\tIP0SR5_27_24_MARK___3 = 1228,\n\tAVB2_MDC_MARK___3 = 1229,\n\tIP1SR5_27_24_MARK___3 = 1230,\n\tAVB2_RD1_MARK___3 = 1231,\n\tIP0SR5_31_28_MARK___3 = 1232,\n\tAVB2_TXCREFCLK_MARK___3 = 1233,\n\tIP1SR5_31_28_MARK___3 = 1234,\n\tAVB2_TD0_MARK___3 = 1235,\n\tIP0SR6_3_0_MARK___2 = 1236,\n\tAVB1_MDIO_MARK___3 = 1237,\n\tIP1SR6_3_0_MARK___2 = 1238,\n\tAVB1_RXC_MARK___3 = 1239,\n\tAVB1_MII_RXC_MARK___2 = 1240,\n\tIP2SR6_3_0_MARK___2 = 1241,\n\tAVB1_TD2_MARK___3 = 1242,\n\tAVB1_MII_TD2_MARK___2 = 1243,\n\tIP0SR6_7_4_MARK___2 = 1244,\n\tAVB1_MAGIC_MARK___3 = 1245,\n\tIP1SR6_7_4_MARK___2 = 1246,\n\tAVB1_RX_CTL_MARK___3 = 1247,\n\tAVB1_MII_RX_DV_MARK___2 = 1248,\n\tIP2SR6_7_4_MARK___2 = 1249,\n\tAVB1_RD2_MARK___3 = 1250,\n\tAVB1_MII_RD2_MARK___2 = 1251,\n\tIP0SR6_11_8_MARK___2 = 1252,\n\tAVB1_MDC_MARK___3 = 1253,\n\tIP1SR6_11_8_MARK___2 = 1254,\n\tAVB1_AVTP_PPS_MARK___3 = 1255,\n\tAVB1_MII_COL_MARK___2 = 1256,\n\tIP2SR6_11_8_MARK___2 = 1257,\n\tAVB1_TD3_MARK___3 = 1258,\n\tAVB1_MII_TD3_MARK___2 = 1259,\n\tIP0SR6_15_12_MARK___2 = 1260,\n\tAVB1_PHY_INT_MARK___3 = 1261,\n\tIP1SR6_15_12_MARK___2 = 1262,\n\tAVB1_AVTP_CAPTURE_MARK___3 = 1263,\n\tAVB1_MII_CRS_MARK___2 = 1264,\n\tIP2SR6_15_12_MARK___2 = 1265,\n\tAVB1_RD3_MARK___3 = 1266,\n\tAVB1_MII_RD3_MARK___2 = 1267,\n\tIP0SR6_19_16_MARK___2 = 1268,\n\tAVB1_LINK_MARK___3 = 1269,\n\tAVB1_MII_TX_ER_MARK___2 = 1270,\n\tIP1SR6_19_16_MARK___2 = 1271,\n\tAVB1_TD1_MARK___3 = 1272,\n\tAVB1_MII_TD1_MARK___2 = 1273,\n\tIP2SR6_19_16_MARK___2 = 1274,\n\tAVB1_TXCREFCLK_MARK___3 = 1275,\n\tIP0SR6_23_20_MARK___2 = 1276,\n\tAVB1_AVTP_MATCH_MARK___3 = 1277,\n\tAVB1_MII_RX_ER_MARK___2 = 1278,\n\tIP1SR6_23_20_MARK___2 = 1279,\n\tAVB1_TD0_MARK___3 = 1280,\n\tAVB1_MII_TD0_MARK___2 = 1281,\n\tIP0SR6_27_24_MARK___2 = 1282,\n\tAVB1_TXC_MARK___3 = 1283,\n\tAVB1_MII_TXC_MARK___2 = 1284,\n\tIP1SR6_27_24_MARK___2 = 1285,\n\tAVB1_RD1_MARK___3 = 1286,\n\tAVB1_MII_RD1_MARK___2 = 1287,\n\tIP0SR6_31_28_MARK___2 = 1288,\n\tAVB1_TX_CTL_MARK___3 = 1289,\n\tAVB1_MII_TX_EN_MARK___2 = 1290,\n\tIP1SR6_31_28_MARK___2 = 1291,\n\tAVB1_RD0_MARK___3 = 1292,\n\tAVB1_MII_RD0_MARK___2 = 1293,\n\tIP0SR7_3_0_MARK___2 = 1294,\n\tAVB0_AVTP_PPS_MARK___4 = 1295,\n\tAVB0_MII_COL_MARK___2 = 1296,\n\tIP1SR7_3_0_MARK___2 = 1297,\n\tAVB0_RD3_MARK___5 = 1298,\n\tAVB0_MII_RD3_MARK___2 = 1299,\n\tIP2SR7_3_0_MARK___2 = 1300,\n\tAVB0_TX_CTL_MARK___5 = 1301,\n\tAVB0_MII_TX_EN_MARK___2 = 1302,\n\tIP0SR7_7_4_MARK___2 = 1303,\n\tAVB0_AVTP_CAPTURE_MARK___4 = 1304,\n\tAVB0_MII_CRS_MARK___2 = 1305,\n\tIP1SR7_7_4_MARK___2 = 1306,\n\tAVB0_TXCREFCLK_MARK___5 = 1307,\n\tIP2SR7_7_4_MARK___2 = 1308,\n\tAVB0_RD1_MARK___5 = 1309,\n\tAVB0_MII_RD1_MARK___2 = 1310,\n\tIP0SR7_11_8_MARK___2 = 1311,\n\tAVB0_AVTP_MATCH_MARK___4 = 1312,\n\tAVB0_MII_RX_ER_MARK___2 = 1313,\n\tIP1SR7_11_8_MARK___2 = 1314,\n\tAVB0_MAGIC_MARK___5 = 1315,\n\tIP2SR7_11_8_MARK___2 = 1316,\n\tAVB0_RD0_MARK___5 = 1317,\n\tAVB0_MII_RD0_MARK___2 = 1318,\n\tIP0SR7_15_12_MARK___2 = 1319,\n\tAVB0_TD3_MARK___5 = 1320,\n\tAVB0_MII_TD3_MARK___2 = 1321,\n\tIP1SR7_15_12_MARK___2 = 1322,\n\tAVB0_TD0_MARK___5 = 1323,\n\tAVB0_MII_TD0_MARK___2 = 1324,\n\tIP2SR7_15_12_MARK___2 = 1325,\n\tAVB0_RXC_MARK___5 = 1326,\n\tAVB0_MII_RXC_MARK___2 = 1327,\n\tIP0SR7_19_16_MARK___2 = 1328,\n\tAVB0_LINK_MARK___5 = 1329,\n\tAVB0_MII_TX_ER_MARK___2 = 1330,\n\tIP1SR7_19_16_MARK___2 = 1331,\n\tAVB0_RD2_MARK___5 = 1332,\n\tAVB0_MII_RD2_MARK___2 = 1333,\n\tIP2SR7_19_16_MARK___2 = 1334,\n\tAVB0_RX_CTL_MARK___5 = 1335,\n\tAVB0_MII_RX_DV_MARK___2 = 1336,\n\tIP0SR7_23_20_MARK___2 = 1337,\n\tAVB0_PHY_INT_MARK___5 = 1338,\n\tIP1SR7_23_20_MARK___2 = 1339,\n\tAVB0_MDC_MARK___5 = 1340,\n\tIP0SR7_27_24_MARK___2 = 1341,\n\tAVB0_TD2_MARK___5 = 1342,\n\tAVB0_MII_TD2_MARK___2 = 1343,\n\tIP1SR7_27_24_MARK___2 = 1344,\n\tAVB0_MDIO_MARK___5 = 1345,\n\tIP0SR7_31_28_MARK___2 = 1346,\n\tAVB0_TD1_MARK___5 = 1347,\n\tAVB0_MII_TD1_MARK___2 = 1348,\n\tIP1SR7_31_28_MARK___2 = 1349,\n\tAVB0_TXC_MARK___5 = 1350,\n\tAVB0_MII_TXC_MARK___2 = 1351,\n\tSEL_SDA3_0_MARK___2 = 1352,\n\tSEL_SDA3_1_MARK___2 = 1353,\n\tSEL_SCL3_0_MARK___2 = 1354,\n\tSEL_SCL3_1_MARK___2 = 1355,\n\tSEL_SDA2_0_MARK___2 = 1356,\n\tSEL_SDA2_1_MARK___2 = 1357,\n\tSEL_SCL2_0_MARK___2 = 1358,\n\tSEL_SCL2_1_MARK___2 = 1359,\n\tSEL_SDA1_0_MARK___2 = 1360,\n\tSEL_SDA1_1_MARK___2 = 1361,\n\tSEL_SCL1_0_MARK___2 = 1362,\n\tSEL_SCL1_1_MARK___2 = 1363,\n\tSEL_SDA0_0_MARK___2 = 1364,\n\tSEL_SDA0_1_MARK___2 = 1365,\n\tSEL_SCL0_0_MARK___2 = 1366,\n\tSEL_SCL0_1_MARK___2 = 1367,\n\tPINMUX_MARK_END___11 = 1368,\n};\n\nenum {\n\tPINMUX_TYPE_NONE = 0,\n\tPINMUX_TYPE_FUNCTION = 1,\n\tPINMUX_TYPE_GPIO = 2,\n\tPINMUX_TYPE_OUTPUT = 3,\n\tPINMUX_TYPE_INPUT = 4,\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = -1,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nenum {\n\tPLL5_TARGET_DPI = 0,\n\tPLL5_TARGET_DSI = 1,\n};\n\nenum {\n\tPLL_LOCK_DONE = 0,\n\tPLL_DIV_S = 1,\n\tPLL_MOD_EN = 2,\n\tPLL_SDM_EN = 3,\n\tPLL_REFIN = 4,\n\tPLL_IBIAS = 5,\n\tPLL_N = 6,\n\tPLL_NINT = 7,\n\tPLL_KINT = 8,\n\tPLL_PREDIV = 9,\n\tPLL_POSTDIV = 10,\n\tPLL_FACT_MAX = 11,\n};\n\nenum {\n\tPLL_OFF_L_VAL = 0,\n\tPLL_OFF_CAL_L_VAL = 1,\n\tPLL_OFF_ALPHA_VAL = 2,\n\tPLL_OFF_ALPHA_VAL_U = 3,\n\tPLL_OFF_USER_CTL = 4,\n\tPLL_OFF_USER_CTL_U = 5,\n\tPLL_OFF_USER_CTL_U1 = 6,\n\tPLL_OFF_CONFIG_CTL = 7,\n\tPLL_OFF_CONFIG_CTL_U = 8,\n\tPLL_OFF_CONFIG_CTL_U1 = 9,\n\tPLL_OFF_CONFIG_CTL_U2 = 10,\n\tPLL_OFF_TEST_CTL = 11,\n\tPLL_OFF_TEST_CTL_U = 12,\n\tPLL_OFF_TEST_CTL_U1 = 13,\n\tPLL_OFF_TEST_CTL_U2 = 14,\n\tPLL_OFF_TEST_CTL_U3 = 15,\n\tPLL_OFF_STATE = 16,\n\tPLL_OFF_STATUS = 17,\n\tPLL_OFF_OPMODE = 18,\n\tPLL_OFF_FRAC = 19,\n\tPLL_OFF_CAL_VAL = 20,\n\tPLL_OFF_MAX_REGS = 21,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPORT_TYPE_SAS = 2,\n\tPORT_TYPE_SATA = 1,\n};\n\nenum {\n\tPOWERCAP_FC_CAP = 0,\n\tPOWERCAP_FC_PAI = 1,\n\tPOWERCAP_FC_MAX = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_LOW = 2,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_FULL = 5,\n};\n\nenum {\n\tPOWER_SUPPLY_HEALTH_UNKNOWN = 0,\n\tPOWER_SUPPLY_HEALTH_GOOD = 1,\n\tPOWER_SUPPLY_HEALTH_OVERHEAT = 2,\n\tPOWER_SUPPLY_HEALTH_DEAD = 3,\n\tPOWER_SUPPLY_HEALTH_OVERVOLTAGE = 4,\n\tPOWER_SUPPLY_HEALTH_UNDERVOLTAGE = 5,\n\tPOWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 6,\n\tPOWER_SUPPLY_HEALTH_COLD = 7,\n\tPOWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 8,\n\tPOWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 9,\n\tPOWER_SUPPLY_HEALTH_OVERCURRENT = 10,\n\tPOWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 11,\n\tPOWER_SUPPLY_HEALTH_WARM = 12,\n\tPOWER_SUPPLY_HEALTH_COOL = 13,\n\tPOWER_SUPPLY_HEALTH_HOT = 14,\n\tPOWER_SUPPLY_HEALTH_NO_BATTERY = 15,\n\tPOWER_SUPPLY_HEALTH_BLOWN_FUSE = 16,\n\tPOWER_SUPPLY_HEALTH_CELL_IMBALANCE = 17,\n};\n\nenum {\n\tPOWER_SUPPLY_SCOPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_SCOPE_SYSTEM = 1,\n\tPOWER_SUPPLY_SCOPE_DEVICE = 2,\n};\n\nenum {\n\tPOWER_SUPPLY_STATUS_UNKNOWN = 0,\n\tPOWER_SUPPLY_STATUS_CHARGING = 1,\n\tPOWER_SUPPLY_STATUS_DISCHARGING = 2,\n\tPOWER_SUPPLY_STATUS_NOT_CHARGING = 3,\n\tPOWER_SUPPLY_STATUS_FULL = 4,\n};\n\nenum {\n\tPOWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,\n\tPOWER_SUPPLY_TECHNOLOGY_NiMH = 1,\n\tPOWER_SUPPLY_TECHNOLOGY_LION = 2,\n\tPOWER_SUPPLY_TECHNOLOGY_LIPO = 3,\n\tPOWER_SUPPLY_TECHNOLOGY_LiFe = 4,\n\tPOWER_SUPPLY_TECHNOLOGY_NiCd = 5,\n\tPOWER_SUPPLY_TECHNOLOGY_LiMn = 6,\n};\n\nenum {\n\tPREF_UNIT_OP_ON = 8,\n\tPREF_UNIT_OP_OFF = 4,\n\tPREF_UNIT_RST_CLR = 2,\n\tPREF_UNIT_RST_SET = 1,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tPSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 240,\n\tPSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4,\n\tPSM_CONFIG_REG4_DEBUG_TIMER = 2,\n\tPSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1,\n};\n\nenum {\n\tPULS_NO_STR = 0,\n\tPULS_21MS = 1,\n\tPULS_42MS = 2,\n\tPULS_84MS = 3,\n\tPULS_170MS = 4,\n\tPULS_340MS = 5,\n\tPULS_670MS = 6,\n\tPULS_1300MS = 7,\n};\n\nenum {\n\tPWMF_REQUESTED = 0,\n\tPWMF_EXPORTED = 1,\n};\n\nenum {\n\tPWR_DESC_ANY = 0,\n\tPWR_DESC_PWM = 1,\n\tPWR_DESC_HS = 2,\n\tPWR_DESC_SER_A = 1,\n\tPWR_DESC_SER_B = 2,\n\tPWR_DESC_G1 = 1,\n\tPWR_DESC_G2 = 2,\n\tPWR_DESC_G3 = 3,\n\tMD_MASK = 3,\n\tSR_MASK = 3,\n\tGR_MASK = 7,\n};\n\nenum {\n\tPWR_OK = 0,\n\tPWR_LOCAL = 1,\n\tPWR_REMOTE = 2,\n\tPWR_BUSY = 3,\n\tPWR_ERROR_CAP = 4,\n\tPWR_FATAL_ERROR = 5,\n};\n\nenum {\n\tP_AUD_REF_CLK = 0,\n\tP_BI_TCXO = 1,\n\tP_GPLL0_OUT_EVEN = 2,\n\tP_GPLL0_OUT_MAIN = 3,\n\tP_GPLL1_OUT_MAIN = 4,\n\tP_GPLL2_OUT_MAIN = 5,\n\tP_GPLL4_OUT_MAIN = 6,\n\tP_GPLL5_OUT_MAIN = 7,\n\tP_GPLL7_OUT_MAIN = 8,\n\tP_GPLL9_OUT_MAIN = 9,\n\tP_SLEEP_CLK = 10,\n};\n\nenum {\n\tP_AUD_REF_CLK___2 = 0,\n\tP_GPLL0_OUT_MAIN___2 = 1,\n\tP_GPLL4_OUT_MAIN___2 = 2,\n\tP_PLL0_EARLY_DIV_CLK_SRC = 3,\n\tP_SLEEP_CLK___2 = 4,\n\tP_XO = 5,\n};\n\nenum {\n\tP_BI_TCXO___2 = 0,\n\tP_GCC_GPLL0_OUT_EVEN = 1,\n\tP_GCC_GPLL0_OUT_MAIN = 2,\n\tP_GCC_GPLL4_OUT_MAIN = 3,\n\tP_GCC_GPLL7_OUT_MAIN = 4,\n\tP_GCC_GPLL9_OUT_MAIN = 5,\n\tP_PCIE_0_PIPE_CLK = 6,\n\tP_PCIE_1_PHY_AUX_CLK = 7,\n\tP_PCIE_1_PIPE_CLK = 8,\n\tP_SLEEP_CLK___3 = 9,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK = 10,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK = 11,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK = 12,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK = 13,\n};\n\nenum {\n\tP_BI_TCXO___3 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___2 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___2 = 2,\n\tP_GCC_GPLL1_OUT_MAIN = 3,\n\tP_GCC_GPLL4_OUT_MAIN___2 = 4,\n\tP_GCC_GPLL7_OUT_MAIN___2 = 5,\n\tP_GCC_GPLL9_OUT_MAIN___2 = 6,\n\tP_PCIE_0_PIPE_CLK___2 = 7,\n\tP_PCIE_1_PIPE_CLK___2 = 8,\n\tP_PCIE_PHY_AUX_CLK = 9,\n\tP_RXC0_REF_CLK = 10,\n\tP_SLEEP_CLK___4 = 11,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___2 = 12,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___2 = 13,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___2 = 14,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK = 15,\n};\n\nenum {\n\tP_BI_TCXO___4 = 0,\n\tP_AUD_REF_CLK___3 = 1,\n\tP_GPLL0_OUT_EVEN___2 = 2,\n\tP_GPLL0_OUT_MAIN___3 = 3,\n\tP_GPLL4_OUT_MAIN___3 = 4,\n\tP_GPLL6_OUT_MAIN = 5,\n\tP_SLEEP_CLK___5 = 6,\n};\n\nenum {\n\tP_BI_TCXO___5 = 0,\n\tP_AUD_REF_CLK___4 = 1,\n\tP_GPLL0_OUT_EVEN___3 = 2,\n\tP_GPLL0_OUT_MAIN___4 = 3,\n\tP_GPLL4_OUT_MAIN___4 = 4,\n\tP_GPLL9_OUT_MAIN___2 = 5,\n\tP_SLEEP_CLK___6 = 6,\n};\n\nenum {\n\tP_BI_TCXO___6 = 0,\n\tP_AUD_REF_CLK___5 = 1,\n\tP_GPLL0_OUT_EVEN___4 = 2,\n\tP_GPLL0_OUT_MAIN___5 = 3,\n\tP_GPLL7_OUT_MAIN___2 = 4,\n\tP_GPLL9_OUT_MAIN___3 = 5,\n\tP_SLEEP_CLK___7 = 6,\n};\n\nenum {\n\tP_BI_TCXO___7 = 0,\n\tP_VIDEO_PLL0_OUT_MAIN = 1,\n};\n\nenum {\n\tP_BI_TCXO___8 = 0,\n\tP_EMAC0_SGMIIPHY_MAC_RCLK = 1,\n\tP_EMAC0_SGMIIPHY_MAC_TCLK = 2,\n\tP_EMAC0_SGMIIPHY_RCLK = 3,\n\tP_EMAC0_SGMIIPHY_TCLK = 4,\n\tP_EMAC1_SGMIIPHY_MAC_RCLK = 5,\n\tP_EMAC1_SGMIIPHY_MAC_TCLK = 6,\n\tP_EMAC1_SGMIIPHY_RCLK = 7,\n\tP_EMAC1_SGMIIPHY_TCLK = 8,\n\tP_GPLL0_OUT_EVEN___5 = 9,\n\tP_GPLL0_OUT_MAIN___6 = 10,\n\tP_GPLL4_OUT_MAIN___5 = 11,\n\tP_GPLL5_OUT_MAIN___2 = 12,\n\tP_GPLL6_OUT_MAIN___2 = 13,\n\tP_GPLL8_OUT_MAIN = 14,\n\tP_PCIE20_PHY_AUX_CLK = 15,\n\tP_PCIE_1_PIPE_CLK___3 = 16,\n\tP_PCIE_2_PIPE_CLK = 17,\n\tP_PCIE_PIPE_CLK = 18,\n\tP_SLEEP_CLK___8 = 19,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___2 = 20,\n};\n\nenum {\n\tP_BI_TCXO___9 = 0,\n\tP_GPLL0_OUT_EVEN___6 = 1,\n\tP_GPLL0_OUT_MAIN___7 = 2,\n\tP_GPLL1_OUT_MAIN___2 = 3,\n\tP_GPLL4_OUT_MAIN___6 = 4,\n\tP_GPLL6_OUT_MAIN___3 = 5,\n\tP_GPLL7_OUT_MAIN___3 = 6,\n\tP_SLEEP_CLK___9 = 7,\n};\n\nenum {\n\tP_BI_TCXO___10 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___3 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___3 = 2,\n\tP_GCC_GPLL0_OUT_ODD = 3,\n\tP_GCC_GPLL2_OUT_MAIN = 4,\n\tP_GCC_GPLL4_OUT_MAIN___3 = 5,\n\tP_GCC_GPLL6_OUT_MAIN = 6,\n\tP_GCC_GPLL7_OUT_MAIN___3 = 7,\n\tP_GCC_GPLL9_OUT_MAIN___3 = 8,\n\tP_PCIE_0_PIPE_CLK___3 = 9,\n\tP_PCIE_1_PIPE_CLK___4 = 10,\n\tP_SLEEP_CLK___10 = 11,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___3 = 12,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___3 = 13,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___3 = 14,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___3 = 15,\n};\n\nenum {\n\tP_BI_TCXO___11 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___4 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___4 = 2,\n\tP_GCC_GPLL4_OUT_MAIN___4 = 3,\n\tP_GCC_GPLL7_OUT_MAIN___4 = 4,\n\tP_GCC_GPLL8_OUT_MAIN = 5,\n\tP_GCC_GPLL9_OUT_MAIN___4 = 6,\n\tP_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC = 7,\n\tP_GCC_USB3_SEC_PHY_PIPE_CLK_SRC = 8,\n\tP_GCC_USB3_TERT_PHY_PIPE_CLK_SRC = 9,\n\tP_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC = 10,\n\tP_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC = 11,\n\tP_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC = 12,\n\tP_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC = 13,\n\tP_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC = 14,\n\tP_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC = 15,\n\tP_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC = 16,\n\tP_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC = 17,\n\tP_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC = 18,\n\tP_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC = 19,\n\tP_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC = 20,\n\tP_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC = 21,\n\tP_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC = 22,\n\tP_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC = 23,\n\tP_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC = 24,\n\tP_QUSB4PHY_0_GCC_USB4_RX0_CLK = 25,\n\tP_QUSB4PHY_0_GCC_USB4_RX1_CLK = 26,\n\tP_QUSB4PHY_1_GCC_USB4_RX0_CLK = 27,\n\tP_QUSB4PHY_1_GCC_USB4_RX1_CLK = 28,\n\tP_QUSB4PHY_2_GCC_USB4_RX0_CLK = 29,\n\tP_QUSB4PHY_2_GCC_USB4_RX1_CLK = 30,\n\tP_SLEEP_CLK___11 = 31,\n\tP_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK = 32,\n\tP_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK = 33,\n\tP_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK = 34,\n\tP_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK = 35,\n\tP_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 36,\n\tP_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK = 37,\n\tP_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 38,\n\tP_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK = 39,\n\tP_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 40,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___4 = 41,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___4 = 42,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___4 = 43,\n};\n\nenum {\n\tP_BI_TCXO___12 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___5 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___5 = 2,\n\tP_GCC_GPLL0_OUT_ODD___2 = 3,\n\tP_GCC_GPLL1_OUT_MAIN___2 = 4,\n\tP_GCC_GPLL3_OUT_MAIN = 5,\n\tP_GCC_GPLL4_OUT_MAIN___5 = 6,\n\tP_GCC_GPLL9_OUT_MAIN___5 = 7,\n\tP_GCC_GPLL10_OUT_MAIN = 8,\n\tP_SLEEP_CLK___12 = 9,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___5 = 10,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___5 = 11,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___5 = 12,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___4 = 13,\n};\n\nenum {\n\tP_BI_TCXO___13 = 0,\n\tP_GPLL0_OUT_MAIN___8 = 1,\n\tP_GPLL0_OUT_MAIN_DIV = 2,\n\tP_GPU_CC_PLL0_OUT_MAIN = 3,\n\tP_GPU_CC_PLL1_OUT_MAIN = 4,\n};\n\nenum {\n\tP_BI_TCXO___14 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___6 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___6 = 2,\n\tP_GCC_GPLL1_OUT_MAIN___3 = 3,\n\tP_GCC_GPLL2_OUT_MAIN___2 = 4,\n\tP_GCC_GPLL3_OUT_MAIN___2 = 5,\n\tP_GCC_GPLL4_OUT_MAIN___6 = 6,\n\tP_GCC_GPLL5_OUT_MAIN = 7,\n\tP_GCC_GPLL6_OUT_MAIN___2 = 8,\n\tP_GCC_GPLL7_OUT_MAIN___5 = 9,\n\tP_GCC_GPLL8_OUT_MAIN___2 = 10,\n\tP_PCIE_0_PHY_AUX_CLK = 11,\n\tP_PCIE_0_PIPE_CLK___4 = 12,\n\tP_SLEEP_CLK___13 = 13,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___5 = 14,\n};\n\nenum {\n\tP_BI_TCXO___15 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___7 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___7 = 2,\n\tP_GCC_GPLL2_OUT_MAIN___3 = 3,\n\tP_GCC_GPLL4_OUT_MAIN___7 = 4,\n\tP_GCC_GPLL7_OUT_MAIN___6 = 5,\n\tP_GCC_GPLL8_OUT_MAIN___3 = 6,\n\tP_GCC_GPLL9_OUT_MAIN___6 = 7,\n\tP_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC___2 = 8,\n\tP_GCC_USB3_SEC_PHY_PIPE_CLK_SRC___2 = 9,\n\tP_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC = 10,\n\tP_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC = 11,\n\tP_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC___2 = 12,\n\tP_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC___2 = 13,\n\tP_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC___2 = 14,\n\tP_GCC_USB4_PHY_DP_GMUX_CLK_SRC = 15,\n\tP_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC = 16,\n\tP_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC = 17,\n\tP_GCC_USB4_PHY_PIPEGMUX_CLK_SRC = 18,\n\tP_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC = 19,\n\tP_QUSB4PHY_1_GCC_USB4_RX0_CLK___2 = 20,\n\tP_QUSB4PHY_1_GCC_USB4_RX1_CLK___2 = 21,\n\tP_QUSB4PHY_GCC_USB4_RX0_CLK = 22,\n\tP_QUSB4PHY_GCC_USB4_RX1_CLK = 23,\n\tP_RXC0_REF_CLK___2 = 24,\n\tP_RXC1_REF_CLK = 25,\n\tP_SLEEP_CLK___14 = 26,\n\tP_UFS_CARD_RX_SYMBOL_0_CLK = 27,\n\tP_UFS_CARD_RX_SYMBOL_1_CLK = 28,\n\tP_UFS_CARD_TX_SYMBOL_0_CLK = 29,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___6 = 30,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___6 = 31,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___6 = 32,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___6 = 33,\n\tP_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK = 34,\n\tP_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK = 35,\n\tP_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK = 36,\n\tP_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK___2 = 37,\n\tP_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK___2 = 38,\n\tP_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK = 39,\n\tP_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK = 40,\n};\n\nenum {\n\tP_BI_TCXO___16 = 0,\n\tP_GPLL0_OUT_AUX2_DIV = 1,\n\tP_GPLL0_OUT_MAIN___9 = 2,\n\tP_GPLL3_OUT_MAIN = 3,\n\tP_GPLL3_OUT_MAIN_DIV = 4,\n\tP_GPLL4_OUT_MAIN___7 = 5,\n\tP_GPLL6_OUT_MAIN___4 = 6,\n\tP_GPLL7_OUT_MAIN___4 = 7,\n\tP_GPLL8_OUT_MAIN___2 = 8,\n\tP_SLEEP_CLK___15 = 9,\n};\n\nenum {\n\tP_BI_TCXO___17 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___8 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___8 = 2,\n\tP_GCC_GPLL1_OUT_MAIN___4 = 3,\n\tP_GCC_GPLL4_OUT_MAIN___8 = 4,\n\tP_GCC_GPLL7_OUT_MAIN___7 = 5,\n\tP_GCC_GPLL9_OUT_MAIN___7 = 6,\n\tP_PCIE_0_PIPE_CLK___5 = 7,\n\tP_SLEEP_CLK___16 = 8,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___7 = 9,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___7 = 10,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___7 = 11,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___7 = 12,\n};\n\nenum {\n\tP_BI_TCXO___18 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___9 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___9 = 2,\n\tP_GCC_GPLL0_OUT_ODD___3 = 3,\n\tP_GCC_GPLL10_OUT_MAIN___2 = 4,\n\tP_GCC_GPLL4_OUT_MAIN___9 = 5,\n\tP_GCC_GPLL9_OUT_MAIN___8 = 6,\n\tP_PCIE_0_PIPE_CLK___6 = 7,\n\tP_PCIE_1_PIPE_CLK___5 = 8,\n\tP_SLEEP_CLK___17 = 9,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___8 = 10,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___8 = 11,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___8 = 12,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___8 = 13,\n\tP_GCC_MSS_GPLL0_MAIN_DIV_CLK = 14,\n};\n\nenum {\n\tP_BI_TCXO___19 = 0,\n\tP_DISP_CC_PLL0_OUT_MAIN = 1,\n\tP_DISP_CC_PLL1_OUT_EVEN = 2,\n\tP_DISP_CC_PLL1_OUT_MAIN = 3,\n\tP_DP_PHY_PLL_LINK_CLK = 4,\n\tP_DP_PHY_PLL_VCO_DIV_CLK = 5,\n\tP_DPTX1_PHY_PLL_LINK_CLK = 6,\n\tP_DPTX1_PHY_PLL_VCO_DIV_CLK = 7,\n\tP_DPTX2_PHY_PLL_LINK_CLK = 8,\n\tP_DPTX2_PHY_PLL_VCO_DIV_CLK = 9,\n\tP_EDP_PHY_PLL_LINK_CLK = 10,\n\tP_EDP_PHY_PLL_VCO_DIV_CLK = 11,\n\tP_DSI0_PHY_PLL_OUT_BYTECLK = 12,\n\tP_DSI0_PHY_PLL_OUT_DSICLK = 13,\n\tP_DSI1_PHY_PLL_OUT_BYTECLK = 14,\n\tP_DSI1_PHY_PLL_OUT_DSICLK = 15,\n};\n\nenum {\n\tP_BI_TCXO___20 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___10 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___10 = 2,\n\tP_GCC_GPLL1_OUT_MAIN___5 = 3,\n\tP_GCC_GPLL4_OUT_MAIN___10 = 4,\n\tP_GCC_GPLL5_OUT_MAIN___2 = 5,\n\tP_GCC_GPLL7_OUT_MAIN___8 = 6,\n\tP_GCC_GPLL9_OUT_MAIN___9 = 7,\n\tP_PCIE_0_PIPE_CLK___7 = 8,\n\tP_PCIE_1_PIPE_CLK___6 = 9,\n\tP_PCIE_PHY_AUX_CLK___2 = 10,\n\tP_RXC0_REF_CLK___3 = 11,\n\tP_RXC1_REF_CLK___2 = 12,\n\tP_SLEEP_CLK___18 = 13,\n\tP_UFS_CARD_RX_SYMBOL_0_CLK___2 = 14,\n\tP_UFS_CARD_RX_SYMBOL_1_CLK___2 = 15,\n\tP_UFS_CARD_TX_SYMBOL_0_CLK___2 = 16,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___9 = 17,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___9 = 18,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___9 = 19,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK___2 = 20,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK = 21,\n};\n\nenum {\n\tP_BI_TCXO___21 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___11 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___11 = 2,\n\tP_GCC_GPLL1_OUT_MAIN___6 = 3,\n\tP_GCC_GPLL3_OUT_MAIN___3 = 4,\n\tP_GCC_GPLL4_OUT_MAIN___11 = 5,\n\tP_GCC_GPLL6_OUT_MAIN___3 = 6,\n\tP_GCC_GPLL7_OUT_MAIN___9 = 7,\n\tP_GCC_GPLL9_OUT_MAIN___10 = 8,\n\tP_PCIE_0_PIPE_CLK___8 = 9,\n\tP_PCIE_1_PHY_AUX_CLK___2 = 10,\n\tP_PCIE_1_PIPE_CLK___7 = 11,\n\tP_SLEEP_CLK___19 = 12,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___10 = 13,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___10 = 14,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___10 = 15,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___9 = 16,\n};\n\nenum {\n\tP_BI_TCXO___22 = 0,\n\tP_GPLL0_OUT_EVEN___7 = 1,\n\tP_GPLL0_OUT_MAIN___10 = 2,\n\tP_GPLL0_OUT_ODD = 3,\n\tP_GPLL6_OUT_EVEN = 4,\n\tP_GPLL7_OUT_MAIN___5 = 5,\n\tP_SLEEP_CLK___20 = 6,\n};\n\nenum {\n\tP_BI_TCXO___23 = 0,\n\tP_DISP_CC_PLL0_OUT_MAIN___2 = 1,\n\tP_DSI0_PHY_PLL_OUT_BYTECLK___2 = 2,\n\tP_DSI0_PHY_PLL_OUT_DSICLK___2 = 3,\n\tP_DSI1_PHY_PLL_OUT_BYTECLK___2 = 4,\n\tP_DSI1_PHY_PLL_OUT_DSICLK___2 = 5,\n\tP_GPLL0_OUT_MAIN___11 = 6,\n\tP_GPLL0_OUT_MAIN_DIV___2 = 7,\n\tP_DP_PHY_PLL_LINK_CLK___2 = 8,\n\tP_DP_PHY_PLL_VCO_DIV_CLK___2 = 9,\n};\n\nenum {\n\tP_BI_TCXO___24 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___12 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___12 = 2,\n\tP_SM8475_GCC_GPLL2_OUT_EVEN = 3,\n\tP_SM8475_GCC_GPLL3_OUT_EVEN = 4,\n\tP_GCC_GPLL4_OUT_MAIN___12 = 5,\n\tP_GCC_GPLL9_OUT_MAIN___11 = 6,\n\tP_PCIE_1_PHY_AUX_CLK___3 = 7,\n\tP_SLEEP_CLK___21 = 8,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___11 = 9,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___11 = 10,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___11 = 11,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___10 = 12,\n};\n\nenum {\n\tP_BI_TCXO___25 = 0,\n\tP_GPLL0_OUT_AUX2 = 1,\n\tP_GPLL0_OUT_EARLY = 2,\n\tP_GPLL10_OUT_MAIN = 3,\n\tP_GPLL11_OUT_MAIN = 4,\n\tP_GPLL3_OUT_EARLY = 5,\n\tP_GPLL4_OUT_MAIN___8 = 6,\n\tP_GPLL6_OUT_EARLY = 7,\n\tP_GPLL6_OUT_MAIN___5 = 8,\n\tP_GPLL7_OUT_MAIN___6 = 9,\n\tP_GPLL8_OUT_EARLY = 10,\n\tP_GPLL8_OUT_MAIN___3 = 11,\n\tP_GPLL9_OUT_EARLY = 12,\n\tP_GPLL9_OUT_MAIN___4 = 13,\n\tP_SLEEP_CLK___22 = 14,\n};\n\nenum {\n\tP_BI_TCXO___26 = 0,\n\tP_GPLL0_OUT_AUX2___2 = 1,\n\tP_GPLL0_OUT_EARLY___2 = 2,\n\tP_GPLL10_OUT_MAIN___2 = 3,\n\tP_GPLL11_OUT_AUX = 4,\n\tP_GPLL11_OUT_AUX2 = 5,\n\tP_GPLL11_OUT_MAIN___2 = 6,\n\tP_GPLL3_OUT_EARLY___2 = 7,\n\tP_GPLL3_OUT_MAIN___2 = 8,\n\tP_GPLL4_OUT_MAIN___9 = 9,\n\tP_GPLL5_OUT_MAIN___3 = 10,\n\tP_GPLL6_OUT_EARLY___2 = 11,\n\tP_GPLL6_OUT_MAIN___6 = 12,\n\tP_GPLL7_OUT_MAIN___7 = 13,\n\tP_GPLL8_OUT_EARLY___2 = 14,\n\tP_GPLL8_OUT_MAIN___4 = 15,\n\tP_GPLL9_OUT_EARLY___2 = 16,\n\tP_GPLL9_OUT_MAIN___5 = 17,\n\tP_SLEEP_CLK___23 = 18,\n};\n\nenum {\n\tP_BI_TCXO___27 = 0,\n\tP_VIDEO_PLL0_OUT_MAIN___2 = 1,\n\tP_VIDEO_PLL1_OUT_MAIN = 2,\n};\n\nenum {\n\tP_BI_TCXO___28 = 0,\n\tP_GPLL0_OUT_MAIN___12 = 1,\n\tP_GPLL0_OUT_MAIN_DIV___3 = 2,\n\tP_GPU_CC_PLL1_OUT_MAIN___2 = 3,\n};\n\nenum {\n\tP_BI_TCXO___29 = 0,\n\tP_GCC_GPLL0_OUT_EVEN___13 = 1,\n\tP_GCC_GPLL0_OUT_MAIN___13 = 2,\n\tP_GCC_GPLL4_OUT_MAIN___13 = 3,\n\tP_GCC_GPLL9_OUT_MAIN___12 = 4,\n\tP_PCIE_0_PIPE_CLK___9 = 5,\n\tP_PCIE_1_PIPE_CLK___8 = 6,\n\tP_SLEEP_CLK___24 = 7,\n\tP_UFS_CARD_RX_SYMBOL_0_CLK___3 = 8,\n\tP_UFS_CARD_RX_SYMBOL_1_CLK___3 = 9,\n\tP_UFS_CARD_TX_SYMBOL_0_CLK___3 = 10,\n\tP_UFS_PHY_RX_SYMBOL_0_CLK___12 = 11,\n\tP_UFS_PHY_RX_SYMBOL_1_CLK___12 = 12,\n\tP_UFS_PHY_TX_SYMBOL_0_CLK___12 = 13,\n\tP_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK___11 = 14,\n\tP_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK___2 = 15,\n};\n\nenum {\n\tP_DSI0_PHY_PLL_OUT_BYTECLK___3 = 0,\n\tP_DSI0_PHY_PLL_OUT_DSICLK___3 = 1,\n\tP_GPLL0_OUT_MAIN___13 = 2,\n\tP_GPLL1_OUT_MAIN___3 = 3,\n\tP_GPLL3_OUT_MAIN___3 = 4,\n\tP_GPLL4_OUT_MAIN___10 = 5,\n\tP_GPLL6_OUT_AUX = 6,\n\tP_HDMI_PHY_PLL_CLK = 7,\n\tP_PCIE_0_PIPE_CLK___10 = 8,\n\tP_SLEEP_CLK___25 = 9,\n\tP_XO___2 = 10,\n};\n\nenum {\n\tP_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC = 0,\n\tP_GPLL0_OUT_AUX = 1,\n\tP_GPLL0_OUT_MAIN___14 = 2,\n\tP_GPLL2_OUT_AUX = 3,\n\tP_GPLL2_OUT_MAIN___2 = 4,\n\tP_GPLL4_OUT_AUX = 5,\n\tP_GPLL4_OUT_MAIN___11 = 6,\n\tP_SLEEP_CLK___26 = 7,\n\tP_XO___3 = 8,\n\tP_USB3PHY_0_PIPE = 9,\n};\n\nenum {\n\tP_PCIE3X2_PIPE = 0,\n\tP_PCIE3X1_0_PIPE = 1,\n\tP_PCIE3X1_1_PIPE = 2,\n\tP_USB3PHY_0_PIPE___2 = 3,\n\tP_CORE_BI_PLL_TEST_SE = 4,\n\tP_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC___2 = 5,\n\tP_GPLL0_OUT_AUX___2 = 6,\n\tP_GPLL0_OUT_MAIN___15 = 7,\n\tP_GPLL2_OUT_AUX___2 = 8,\n\tP_GPLL2_OUT_MAIN___3 = 9,\n\tP_GPLL4_OUT_AUX___2 = 10,\n\tP_GPLL4_OUT_MAIN___12 = 11,\n\tP_SLEEP_CLK___27 = 12,\n\tP_XO___4 = 13,\n};\n\nenum {\n\tP_XO___5 = 0,\n\tP_GPLL0 = 1,\n\tP_GPLL4 = 2,\n};\n\nenum {\n\tP_XO___6 = 0,\n\tP_PCIE30_PHY0_PIPE = 1,\n\tP_PCIE30_PHY1_PIPE = 2,\n\tP_PCIE30_PHY2_PIPE = 3,\n\tP_PCIE30_PHY3_PIPE = 4,\n\tP_USB3PHY_0_PIPE___3 = 5,\n\tP_GPLL0___2 = 6,\n\tP_GPLL0_DIV2 = 7,\n\tP_GPLL0_OUT_AUX___3 = 8,\n\tP_GPLL2 = 9,\n\tP_GPLL4___2 = 10,\n\tP_PI_SLEEP = 11,\n\tP_BIAS_PLL_UBI_NC_CLK = 12,\n};\n\nenum {\n\tP_XO___7 = 0,\n\tP_GPLL0___3 = 1,\n\tP_APSS_PLL_EARLY = 2,\n};\n\nenum {\n\tP_XO___8 = 0,\n\tP_SLEEP_CLK___28 = 1,\n\tP_GPLL0___4 = 2,\n\tP_GPLL0_DIV2___2 = 3,\n\tP_GPLL2___2 = 4,\n\tP_GPLL3 = 5,\n\tP_GPLL4___3 = 6,\n\tP_GPLL6 = 7,\n\tP_GPLL6_DIV2 = 8,\n\tP_DSI0PLL = 9,\n\tP_DSI0PLL_BYTE = 10,\n\tP_DSI1PLL = 11,\n\tP_DSI1PLL_BYTE = 12,\n};\n\nenum {\n\tP_XO___9 = 0,\n\tP_GPLL0___5 = 1,\n\tP_GPLL0_DIV2___3 = 2,\n\tP_GPLL2___3 = 3,\n\tP_GPLL4___4 = 4,\n\tP_GPLL6___2 = 5,\n\tP_SLEEP_CLK___29 = 6,\n\tP_PCIE20_PHY0_PIPE = 7,\n\tP_PCIE20_PHY1_PIPE = 8,\n\tP_USB3PHY_0_PIPE___4 = 9,\n\tP_USB3PHY_1_PIPE = 10,\n\tP_UBI32_PLL = 11,\n\tP_NSS_CRYPTO_PLL = 12,\n\tP_BIAS_PLL = 13,\n\tP_BIAS_PLL_NSS_NOC = 14,\n\tP_UNIPHY0_RX = 15,\n\tP_UNIPHY0_TX = 16,\n\tP_UNIPHY1_RX = 17,\n\tP_UNIPHY1_TX = 18,\n\tP_UNIPHY2_RX = 19,\n\tP_UNIPHY2_TX = 20,\n};\n\nenum {\n\tP_XO___10 = 0,\n\tP_GPLL0___6 = 1,\n\tP_GPLL0_AUX = 2,\n\tP_BIMC = 3,\n\tP_GPLL1 = 4,\n\tP_GPLL1_AUX = 5,\n\tP_GPLL2___4 = 6,\n\tP_GPLL2_AUX = 7,\n\tP_SLEEP_CLK___30 = 8,\n\tP_DSI0_PHYPLL_BYTE = 9,\n\tP_DSI0_PHYPLL_DSI = 10,\n\tP_EXT_PRI_I2S = 11,\n\tP_EXT_SEC_I2S = 12,\n\tP_EXT_MCLK = 13,\n};\n\nenum {\n\tP_XO___11 = 0,\n\tP_GPLL0___7 = 1,\n\tP_GPLL0_EARLY_DIV = 2,\n\tP_SLEEP_CLK___31 = 3,\n\tP_GPLL4___5 = 4,\n\tP_AUD_REF_CLK___6 = 5,\n};\n\nenum {\n\tP_XO___12 = 0,\n\tP_BIAS_PLL___2 = 1,\n\tP_UNIPHY0_RX___2 = 2,\n\tP_UNIPHY0_TX___2 = 3,\n\tP_UNIPHY1_RX___2 = 4,\n\tP_BIAS_PLL_NSS_NOC___2 = 5,\n\tP_UNIPHY1_TX___2 = 6,\n\tP_PCIE20_PHY0_PIPE___2 = 7,\n\tP_USB3PHY_0_PIPE___5 = 8,\n\tP_GPLL0___8 = 9,\n\tP_GPLL0_DIV2___4 = 10,\n\tP_GPLL2___5 = 11,\n\tP_GPLL4___6 = 12,\n\tP_GPLL6___3 = 13,\n\tP_SLEEP_CLK___32 = 14,\n\tP_UBI32_PLL___2 = 15,\n\tP_NSS_CRYPTO_PLL___2 = 16,\n\tP_PI_SLEEP___2 = 17,\n};\n\nenum {\n\tP_XO___13 = 0,\n\tP_GPLL0___9 = 1,\n\tP_APSS_PLL_EARLY___2 = 2,\n\tP_L3_PLL = 3,\n};\n\nenum {\n\tP_XO___14 = 0,\n\tP_CORE_PI_SLEEP_CLK = 1,\n\tP_PCIE20_PHY0_PIPE___3 = 2,\n\tP_PCIE20_PHY1_PIPE___2 = 3,\n\tP_USB3PHY_0_PIPE___6 = 4,\n\tP_GEPHY_RX = 5,\n\tP_GEPHY_TX = 6,\n\tP_UNIPHY_RX = 7,\n\tP_UNIPHY_TX = 8,\n\tP_GPLL0___10 = 9,\n\tP_GPLL0_DIV2___5 = 10,\n\tP_GPLL2___6 = 11,\n\tP_GPLL4___7 = 12,\n\tP_UBI32_PLL___3 = 13,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQCM2290_MASTER_APPSS_PROC = 1,\n\tQCM2290_MASTER_SNOC_BIMC_RT = 2,\n\tQCM2290_MASTER_SNOC_BIMC_NRT = 3,\n\tQCM2290_MASTER_SNOC_BIMC = 4,\n\tQCM2290_MASTER_TCU_0 = 5,\n\tQCM2290_MASTER_GFX3D = 6,\n\tQCM2290_MASTER_SNOC_CNOC = 7,\n\tQCM2290_MASTER_QDSS_DAP = 8,\n\tQCM2290_MASTER_CRYPTO_CORE0 = 9,\n\tQCM2290_MASTER_SNOC_CFG = 10,\n\tQCM2290_MASTER_TIC = 11,\n\tQCM2290_MASTER_ANOC_SNOC = 12,\n\tQCM2290_MASTER_BIMC_SNOC = 13,\n\tQCM2290_MASTER_PIMEM = 14,\n\tQCM2290_MASTER_QDSS_BAM = 15,\n\tQCM2290_MASTER_QUP_0 = 16,\n\tQCM2290_MASTER_IPA = 17,\n\tQCM2290_MASTER_QDSS_ETR = 18,\n\tQCM2290_MASTER_SDCC_1 = 19,\n\tQCM2290_MASTER_SDCC_2 = 20,\n\tQCM2290_MASTER_QPIC = 21,\n\tQCM2290_MASTER_USB3_0 = 22,\n\tQCM2290_MASTER_QUP_CORE_0 = 23,\n\tQCM2290_MASTER_CAMNOC_SF = 24,\n\tQCM2290_MASTER_VIDEO_P0 = 25,\n\tQCM2290_MASTER_VIDEO_PROC = 26,\n\tQCM2290_MASTER_CAMNOC_HF = 27,\n\tQCM2290_MASTER_MDP0 = 28,\n\tQCM2290_SLAVE_EBI1 = 29,\n\tQCM2290_SLAVE_BIMC_SNOC = 30,\n\tQCM2290_SLAVE_BIMC_CFG = 31,\n\tQCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG = 32,\n\tQCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG = 33,\n\tQCM2290_SLAVE_CAMERA_CFG = 34,\n\tQCM2290_SLAVE_CLK_CTL = 35,\n\tQCM2290_SLAVE_CRYPTO_0_CFG = 36,\n\tQCM2290_SLAVE_DISPLAY_CFG = 37,\n\tQCM2290_SLAVE_DISPLAY_THROTTLE_CFG = 38,\n\tQCM2290_SLAVE_GPU_CFG = 39,\n\tQCM2290_SLAVE_HWKM = 40,\n\tQCM2290_SLAVE_IMEM_CFG = 41,\n\tQCM2290_SLAVE_IPA_CFG = 42,\n\tQCM2290_SLAVE_LPASS = 43,\n\tQCM2290_SLAVE_MESSAGE_RAM = 44,\n\tQCM2290_SLAVE_PDM = 45,\n\tQCM2290_SLAVE_PIMEM_CFG = 46,\n\tQCM2290_SLAVE_PKA_WRAPPER = 47,\n\tQCM2290_SLAVE_PMIC_ARB = 48,\n\tQCM2290_SLAVE_PRNG = 49,\n\tQCM2290_SLAVE_QDSS_CFG = 50,\n\tQCM2290_SLAVE_QM_CFG = 51,\n\tQCM2290_SLAVE_QM_MPU_CFG = 52,\n\tQCM2290_SLAVE_QPIC = 53,\n\tQCM2290_SLAVE_QUP_0 = 54,\n\tQCM2290_SLAVE_SDCC_1 = 55,\n\tQCM2290_SLAVE_SDCC_2 = 56,\n\tQCM2290_SLAVE_SNOC_CFG = 57,\n\tQCM2290_SLAVE_TCSR = 58,\n\tQCM2290_SLAVE_USB3 = 59,\n\tQCM2290_SLAVE_VENUS_CFG = 60,\n\tQCM2290_SLAVE_VENUS_THROTTLE_CFG = 61,\n\tQCM2290_SLAVE_VSENSE_CTRL_CFG = 62,\n\tQCM2290_SLAVE_SERVICE_CNOC = 63,\n\tQCM2290_SLAVE_APPSS = 64,\n\tQCM2290_SLAVE_SNOC_CNOC = 65,\n\tQCM2290_SLAVE_IMEM = 66,\n\tQCM2290_SLAVE_PIMEM = 67,\n\tQCM2290_SLAVE_SNOC_BIMC = 68,\n\tQCM2290_SLAVE_SERVICE_SNOC = 69,\n\tQCM2290_SLAVE_QDSS_STM = 70,\n\tQCM2290_SLAVE_TCU = 71,\n\tQCM2290_SLAVE_ANOC_SNOC = 72,\n\tQCM2290_SLAVE_QUP_CORE_0 = 73,\n\tQCM2290_SLAVE_SNOC_BIMC_NRT = 74,\n\tQCM2290_SLAVE_SNOC_BIMC_RT = 75,\n};\n\nenum {\n\tQIF_BLIMITS_B = 0,\n\tQIF_SPACE_B = 1,\n\tQIF_ILIMITS_B = 2,\n\tQIF_INODES_B = 3,\n\tQIF_BTIME_B = 4,\n\tQIF_ITIME_B = 5,\n};\n\nenum {\n\tQUERY_REQ_TIMEOUT_MIN = 1,\n\tQUERY_REQ_TIMEOUT_DEFAULT = 1500,\n\tQUERY_REQ_TIMEOUT_MAX = 30000,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQ_R1 = 0,\n\tQ_R2 = 128,\n\tQ_XS1 = 512,\n\tQ_XA1 = 640,\n\tQ_XS2 = 768,\n\tQ_XA2 = 896,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tRB_ADD_STAMP_NONE = 0,\n\tRB_ADD_STAMP_EXTEND = 2,\n\tRB_ADD_STAMP_ABSOLUTE = 4,\n\tRB_ADD_STAMP_FORCE = 8,\n};\n\nenum {\n\tRB_CTX_TRANSITION = 0,\n\tRB_CTX_NMI = 1,\n\tRB_CTX_IRQ = 2,\n\tRB_CTX_SOFTIRQ = 3,\n\tRB_CTX_NORMAL = 4,\n\tRB_CTX_MAX = 5,\n};\n\nenum {\n\tRB_ENA_STFWD = 32,\n\tRB_DIS_STFWD = 16,\n\tRB_ENA_OP_MD = 8,\n\tRB_DIS_OP_MD = 4,\n\tRB_RST_CLR = 2,\n\tRB_RST_SET = 1,\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nenum {\n\tRB_START = 0,\n\tRB_END = 4,\n\tRB_WP = 8,\n\tRB_RP = 12,\n\tRB_RX_UTPP = 16,\n\tRB_RX_LTPP = 20,\n\tRB_RX_UTHP = 24,\n\tRB_RX_LTHP = 28,\n\tRB_PC = 32,\n\tRB_LEV = 36,\n\tRB_CTRL = 40,\n\tRB_TST1 = 41,\n\tRB_TST2 = 42,\n};\n\nenum {\n\tRCAR_PCI_ACCESS_READ = 0,\n\tRCAR_PCI_ACCESS_WRITE = 1,\n};\n\nenum {\n\tRCD = 0,\n\tRCH_DP = 1,\n\tDEVICE = 2,\n\tLD = 3,\n\tFMLD = 4,\n\tRP = 5,\n\tDSP = 6,\n\tUSP = 7,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tREGULATOR_ERROR_CLEARED = 0,\n\tREGULATOR_FAILED_RETRY = 1,\n\tREGULATOR_ERROR_ON = 2,\n};\n\nenum {\n\tREG_CONTROLLER_CAPABILITIES = 0,\n\tREG_MCQCAP = 4,\n\tREG_UFS_VERSION = 8,\n\tREG_EXT_CONTROLLER_CAPABILITIES = 12,\n\tREG_CONTROLLER_PID = 16,\n\tREG_CONTROLLER_MID = 20,\n\tREG_AUTO_HIBERNATE_IDLE_TIMER = 24,\n\tREG_INTERRUPT_STATUS = 32,\n\tREG_INTERRUPT_ENABLE = 36,\n\tREG_CONTROLLER_STATUS = 48,\n\tREG_CONTROLLER_ENABLE = 52,\n\tREG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 56,\n\tREG_UIC_ERROR_CODE_DATA_LINK_LAYER = 60,\n\tREG_UIC_ERROR_CODE_NETWORK_LAYER = 64,\n\tREG_UIC_ERROR_CODE_TRANSPORT_LAYER = 68,\n\tREG_UIC_ERROR_CODE_DME = 72,\n\tREG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 76,\n\tREG_UTP_TRANSFER_REQ_LIST_BASE_L = 80,\n\tREG_UTP_TRANSFER_REQ_LIST_BASE_H = 84,\n\tREG_UTP_TRANSFER_REQ_DOOR_BELL = 88,\n\tREG_UTP_TRANSFER_REQ_LIST_CLEAR = 92,\n\tREG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 96,\n\tREG_UTP_TASK_REQ_LIST_BASE_L = 112,\n\tREG_UTP_TASK_REQ_LIST_BASE_H = 116,\n\tREG_UTP_TASK_REQ_DOOR_BELL = 120,\n\tREG_UTP_TASK_REQ_LIST_CLEAR = 124,\n\tREG_UTP_TASK_REQ_LIST_RUN_STOP = 128,\n\tREG_UIC_COMMAND = 144,\n\tREG_UIC_COMMAND_ARG_1 = 148,\n\tREG_UIC_COMMAND_ARG_2 = 152,\n\tREG_UIC_COMMAND_ARG_3 = 156,\n\tUFSHCI_REG_SPACE_SIZE = 160,\n\tREG_UFS_CCAP = 256,\n\tREG_UFS_CRYPTOCAP = 260,\n\tREG_UFS_MEM_CFG = 768,\n\tREG_UFS_MCQ_CFG = 896,\n\tREG_UFS_ESILBA = 900,\n\tREG_UFS_ESIUBA = 904,\n\tUFSHCI_CRYPTO_REG_SPACE_SIZE = 1024,\n};\n\nenum {\n\tREG_CON_MOD_TX = 0,\n\tREG_CON_MOD_REGISTER_TX = 1,\n\tREG_CON_MOD_RX = 2,\n\tREG_CON_MOD_REGISTER_RX = 3,\n};\n\nenum {\n\tREG_CQHP = 0,\n\tREG_CQTP = 4,\n};\n\nenum {\n\tREG_CQIS = 0,\n\tREG_CQIE = 4,\n};\n\nenum {\n\tREG_DR = 0,\n\tREG_ST_DMAWM = 1,\n\tREG_ST_TIMEOUT = 2,\n\tREG_FR = 3,\n\tREG_LCRH_RX = 4,\n\tREG_LCRH_TX = 5,\n\tREG_IBRD = 6,\n\tREG_FBRD = 7,\n\tREG_CR = 8,\n\tREG_IFLS = 9,\n\tREG_IMSC = 10,\n\tREG_RIS = 11,\n\tREG_MIS = 12,\n\tREG_ICR = 13,\n\tREG_DMACR = 14,\n\tREG_ST_XFCR = 15,\n\tREG_ST_XON1 = 16,\n\tREG_ST_XON2 = 17,\n\tREG_ST_XOFF1 = 18,\n\tREG_ST_XOFF2 = 19,\n\tREG_ST_ITCR = 20,\n\tREG_ST_ITIP = 21,\n\tREG_ST_ABCR = 22,\n\tREG_ST_ABIMSC = 23,\n\tREG_ARRAY_SIZE = 24,\n};\n\nenum {\n\tREG_SQATTR = 0,\n\tREG_SQLBA = 4,\n\tREG_SQUBA = 8,\n\tREG_SQDAO = 12,\n\tREG_SQISAO = 16,\n\tREG_CQATTR = 32,\n\tREG_CQLBA = 36,\n\tREG_CQUBA = 40,\n\tREG_CQDAO = 44,\n\tREG_CQISAO = 48,\n};\n\nenum {\n\tREG_SQHP = 0,\n\tREG_SQTP = 4,\n\tREG_SQRTC = 8,\n\tREG_SQCTI = 12,\n\tREG_SQRTS = 16,\n};\n\nenum {\n\tREQUEST_ANY = 0,\n\tREQUEST_BY_ID = 1,\n\tREQUEST_BY_CAP = 2,\n\tREQUEST_BY_NODE = 3,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 1250,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRES_USAGE = 0,\n\tRES_RSVD_USAGE = 1,\n\tRES_LIMIT = 2,\n\tRES_RSVD_LIMIT = 3,\n\tRES_MAX_USAGE = 4,\n\tRES_RSVD_MAX_USAGE = 5,\n\tRES_FAILCNT = 6,\n\tRES_RSVD_FAILCNT = 7,\n};\n\nenum {\n\tRI_CLR_RD_PERR = 512,\n\tRI_CLR_WR_PERR = 256,\n\tRI_RST_CLR = 2,\n\tRI_RST_SET = 1,\n};\n\nenum {\n\tRK801_ID = 32784,\n\tRK805_ID = 32848,\n\tRK806_ID = 32864,\n\tRK808_ID = 0,\n\tRK809_ID = 32912,\n\tRK816_ID = 33120,\n\tRK817_ID = 33136,\n\tRK818_ID = 33152,\n};\n\nenum {\n\tRK805_BUCK1_2_ILMAX_2500MA = 0,\n\tRK805_BUCK1_2_ILMAX_3000MA = 1,\n\tRK805_BUCK1_2_ILMAX_3500MA = 2,\n\tRK805_BUCK1_2_ILMAX_4000MA = 3,\n};\n\nenum {\n\tRK805_BUCK3_ILMAX_1500MA = 0,\n\tRK805_BUCK3_ILMAX_2000MA = 1,\n\tRK805_BUCK3_ILMAX_2500MA = 2,\n\tRK805_BUCK3_ILMAX_3000MA = 3,\n};\n\nenum {\n\tRK805_BUCK4_ILMAX_2000MA = 0,\n\tRK805_BUCK4_ILMAX_2500MA = 1,\n\tRK805_BUCK4_ILMAX_3000MA = 2,\n\tRK805_BUCK4_ILMAX_3500MA = 3,\n};\n\nenum {\n\tRK8600_CHIP_ID_08 = 8,\n};\n\nenum {\n\tRK8602_CHIP_ID_10 = 10,\n};\n\nenum {\n\tRNG_OUTPUT_0_REG = 0,\n\tRNG_OUTPUT_1_REG = 1,\n\tRNG_OUTPUT_2_REG = 2,\n\tRNG_OUTPUT_3_REG = 3,\n\tRNG_STATUS_REG = 4,\n\tRNG_INTMASK_REG = 5,\n\tRNG_INTACK_REG = 6,\n\tRNG_CONTROL_REG = 7,\n\tRNG_CONFIG_REG = 8,\n\tRNG_ALARMCNT_REG = 9,\n\tRNG_FROENABLE_REG = 10,\n\tRNG_FRODETUNE_REG = 11,\n\tRNG_ALARMMASK_REG = 12,\n\tRNG_ALARMSTOP_REG = 13,\n\tRNG_REV_REG = 14,\n\tRNG_SYSCONFIG_REG = 15,\n};\n\nenum {\n\tRPCAUTH_lockd = 0,\n\tRPCAUTH_mount = 1,\n\tRPCAUTH_nfs = 2,\n\tRPCAUTH_portmap = 3,\n\tRPCAUTH_statd = 4,\n\tRPCAUTH_nfsd4_cb = 5,\n\tRPCAUTH_cache = 6,\n\tRPCAUTH_nfsd = 7,\n\tRPCAUTH_RootEOF = 8,\n};\n\nenum {\n\tRPCBPROC_NULL = 0,\n\tRPCBPROC_SET = 1,\n\tRPCBPROC_UNSET = 2,\n\tRPCBPROC_GETPORT = 3,\n\tRPCBPROC_GETADDR = 3,\n\tRPCBPROC_DUMP = 4,\n\tRPCBPROC_CALLIT = 5,\n\tRPCBPROC_BCAST = 5,\n\tRPCBPROC_GETTIME = 6,\n\tRPCBPROC_UADDR2TADDR = 7,\n\tRPCBPROC_TADDR2UADDR = 8,\n\tRPCBPROC_GETVERSADDR = 9,\n\tRPCBPROC_INDIRECT = 10,\n\tRPCBPROC_GETADDRLIST = 11,\n\tRPCBPROC_GETSTAT = 12,\n};\n\nenum {\n\tRPCSVC_MAXPAYLOAD = 4194304,\n\tRPCSVC_MAXPAYLOAD_TCP = 4194304,\n\tRPCSVC_MAXPAYLOAD_UDP = 32768,\n};\n\nenum {\n\tRPC_PIPEFS_MOUNT = 0,\n\tRPC_PIPEFS_UMOUNT = 1,\n};\n\nenum {\n\tRPC_TASK_RUNNING = 0,\n\tRPC_TASK_QUEUED = 1,\n\tRPC_TASK_ACTIVE = 2,\n\tRPC_TASK_NEED_XMIT = 3,\n\tRPC_TASK_NEED_RECV = 4,\n\tRPC_TASK_MSG_PIN_WAIT = 5,\n};\n\nenum {\n\tRQ_SECURE = 0,\n\tRQ_LOCAL = 1,\n\tRQ_USEDEFERRAL = 2,\n\tRQ_DROPME = 3,\n\tRQ_VICTIM = 4,\n\tRQ_DATA = 5,\n};\n\nenum {\n\tRSC_DRV_TCS_OFFSET = 0,\n\tRSC_DRV_CMD_OFFSET = 1,\n\tDRV_SOLVER_CONFIG = 2,\n\tDRV_PRNT_CHLD_CONFIG = 3,\n\tRSC_DRV_IRQ_ENABLE = 4,\n\tRSC_DRV_IRQ_STATUS = 5,\n\tRSC_DRV_IRQ_CLEAR = 6,\n\tRSC_DRV_CMD_WAIT_FOR_CMPL = 7,\n\tRSC_DRV_CONTROL = 8,\n\tRSC_DRV_STATUS = 9,\n\tRSC_DRV_CMD_ENABLE = 10,\n\tRSC_DRV_CMD_MSGID = 11,\n\tRSC_DRV_CMD_ADDR = 12,\n\tRSC_DRV_CMD_DATA = 13,\n\tRSC_DRV_CMD_STATUS = 14,\n\tRSC_DRV_CMD_RESP_DATA = 15,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTC_SEC = 0,\n\tRTC_MIN = 1,\n\tRTC_HOUR = 2,\n\tRTC_WEEKDAY = 3,\n\tRTC_MONTH = 4,\n\tRTC_YEAR = 5,\n\tRTC_MONTHDAY = 6,\n\tRTC_NR_TIME = 7,\n};\n\nenum {\n\tRTC_SEC___2 = 0,\n\tRTC_MIN___2 = 1,\n\tRTC_HOUR___2 = 2,\n\tRTC_WEEKDAY___2 = 3,\n\tRTC_DATE = 4,\n\tRTC_MONTH___2 = 5,\n\tRTC_YEAR1 = 6,\n\tRTC_YEAR2 = 7,\n\tRTC_MAX_NUM_TIME_REGS = 8,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRX_GCLKMAC_ENA = -2147483648,\n\tRX_GCLKMAC_OFF = 1073741824,\n\tRX_STFW_DIS = 536870912,\n\tRX_STFW_ENA = 268435456,\n\tRX_TRUNC_ON = 134217728,\n\tRX_TRUNC_OFF = 67108864,\n\tRX_VLAN_STRIP_ON = 33554432,\n\tRX_VLAN_STRIP_OFF = 16777216,\n\tRX_MACSEC_FLUSH_ON = 8388608,\n\tRX_MACSEC_FLUSH_OFF = 4194304,\n\tRX_MACSEC_ASF_FLUSH_ON = 2097152,\n\tRX_MACSEC_ASF_FLUSH_OFF = 1048576,\n\tGMF_RX_OVER_ON = 524288,\n\tGMF_RX_OVER_OFF = 262144,\n\tGMF_ASF_RX_OVER_ON = 131072,\n\tGMF_ASF_RX_OVER_OFF = 65536,\n\tGMF_WP_TST_ON = 16384,\n\tGMF_WP_TST_OFF = 8192,\n\tGMF_WP_STEP = 4096,\n\tGMF_RP_TST_ON = 1024,\n\tGMF_RP_TST_OFF = 512,\n\tGMF_RP_STEP = 256,\n\tGMF_RX_F_FL_ON = 128,\n\tGMF_RX_F_FL_OFF = 64,\n\tGMF_CLI_RX_FO = 32,\n\tGMF_CLI_RX_C = 16,\n\tGMF_OPER_ON = 8,\n\tGMF_OPER_OFF = 4,\n\tGMF_RST_CLR = 2,\n\tGMF_RST_SET = 1,\n\tRX_GMF_FL_THR_DEF = 10,\n\tGMF_RX_CTRL_DEF = 136,\n};\n\nenum {\n\tRX_IPV6_SA_MOB_ENA = 512,\n\tRX_IPV6_SA_MOB_DIS = 256,\n\tRX_IPV6_DA_MOB_ENA = 128,\n\tRX_IPV6_DA_MOB_DIS = 64,\n\tRX_PTR_SYNCDLY_ENA = 32,\n\tRX_PTR_SYNCDLY_DIS = 16,\n\tRX_ASF_NEWFLAG_ENA = 8,\n\tRX_ASF_NEWFLAG_DIS = 4,\n\tRX_FLSH_MISSPKT_ENA = 2,\n\tRX_FLSH_MISSPKT_DIS = 1,\n};\n\nenum {\n\tRX_SYMBOL_CLK_GATE_EN = 0,\n\tSYS_CLK_GATE_EN = 2,\n\tTX_CLK_GATE_EN = 3,\n};\n\nenum {\n\tRX_XDP_REDIRECT = 0,\n\tRX_XDP_PASS = 1,\n\tRX_XDP_DROP = 2,\n\tRX_XDP_TX = 3,\n\tRX_XDP_TX_ERRORS = 4,\n\tTX_XDP_XMIT = 5,\n\tTX_XDP_XMIT_ERRORS = 6,\n\tXDP_STATS_TOTAL = 7,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tRworksched = 1,\n\tRpending = 2,\n\tWworksched = 4,\n\tWpending = 8,\n};\n\nenum {\n\tS2MPG10_REGULATOR_OPS_STD = 0,\n\tS2MPG10_REGULATOR_OPS_EXTCONTROL = 1,\n};\n\nenum {\n\tSAS_DATAPRES_NO_DATA = 0,\n\tSAS_DATAPRES_RESPONSE_DATA = 1,\n\tSAS_DATAPRES_SENSE_DATA = 2,\n};\n\nenum {\n\tSAS_DEV_GONE = 0,\n\tSAS_DEV_FOUND = 1,\n\tSAS_DEV_DESTROY = 2,\n\tSAS_DEV_EH_PENDING = 3,\n\tSAS_DEV_LU_RESET = 4,\n\tSAS_DEV_RESET = 5,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCIx_ERI_IRQ = 0,\n\tSCIx_RXI_IRQ = 1,\n\tSCIx_TXI_IRQ = 2,\n\tSCIx_BRI_IRQ = 3,\n\tSCIx_DRI_IRQ = 4,\n\tSCIx_TEI_IRQ = 5,\n\tSCIx_NR_IRQS = 6,\n\tSCIx_MUX_IRQ = 6,\n};\n\nenum {\n\tSCIx_PROBE_REGTYPE = 0,\n\tSCIx_SCI_REGTYPE = 1,\n\tSCIx_IRDA_REGTYPE = 2,\n\tSCIx_SCIFA_REGTYPE = 3,\n\tSCIx_SCIFB_REGTYPE = 4,\n\tSCIx_SH2_SCIF_FIFODATA_REGTYPE = 5,\n\tSCIx_SH3_SCIF_REGTYPE = 6,\n\tSCIx_SH4_SCIF_REGTYPE = 7,\n\tSCIx_SH4_SCIF_BRG_REGTYPE = 8,\n\tSCIx_SH4_SCIF_NO_SCSPTR_REGTYPE = 9,\n\tSCIx_SH4_SCIF_FIFODATA_REGTYPE = 10,\n\tSCIx_SH7705_SCIF_REGTYPE = 11,\n\tSCIx_HSCIF_REGTYPE = 12,\n\tSCIx_RZ_SCIFA_REGTYPE = 13,\n\tSCIx_RZV2H_SCIF_REGTYPE = 14,\n\tSCIx_NR_REGTYPES = 15,\n};\n\nenum {\n\tSCMI_RAW_REPLY_QUEUE = 0,\n\tSCMI_RAW_NOTIF_QUEUE = 1,\n\tSCMI_RAW_ERRS_QUEUE = 2,\n\tSCMI_RAW_MAX_QUEUE = 3,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSCSMR = 0,\n\tSCBRR = 1,\n\tSCSCR = 2,\n\tSCxSR = 3,\n\tSCFCR = 4,\n\tSCFDR = 5,\n\tSCxTDR = 6,\n\tSCxRDR = 7,\n\tSCLSR = 8,\n\tSCTFDR = 9,\n\tSCRFDR = 10,\n\tSCSPTR = 11,\n\tHSSRR = 12,\n\tSCPCR = 13,\n\tSCPDR = 14,\n\tSCDL = 15,\n\tSCCKS = 16,\n\tHSRTRGR = 17,\n\tHSTTRGR = 18,\n\tSEMR = 19,\n};\n\nenum {\n\tSC_STAT_CLR_IRQ = 16,\n\tSC_STAT_OP_ON = 8,\n\tSC_STAT_OP_OFF = 4,\n\tSC_STAT_RST_CLR = 2,\n\tSC_STAT_RST_SET = 1,\n};\n\nenum {\n\tSDHCI_ACPI_SD_CD = 1,\n\tSDHCI_ACPI_RUNTIME_PM = 2,\n\tSDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = 4,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSECTION_MARKED_PRESENT_BIT = 0,\n\tSECTION_HAS_MEM_MAP_BIT = 1,\n\tSECTION_IS_ONLINE_BIT = 2,\n\tSECTION_IS_EARLY_BIT = 3,\n\tSECTION_MAP_LAST_BIT = 4,\n};\n\nenum {\n\tSETWA_FLAGS_APICID = 1,\n\tSETWA_FLAGS_MEM = 2,\n\tSETWA_FLAGS_PCIE_SBDF = 4,\n\tSETWA_FLAGS_EINJV2 = 8,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSH_ETH_REG_GIGABIT = 0,\n\tSH_ETH_REG_FAST_RCAR = 1,\n\tSH_ETH_REG_FAST_SH4 = 2,\n\tSH_ETH_REG_FAST_SH3_SH2 = 3,\n};\n\nenum {\n\tSIL24_HOST_BAR = 0,\n\tSIL24_PORT_BAR = 2,\n\tSIL24_PRB_SZ = 64,\n\tSIL24_MAX_SGT = 63,\n\tSIL24_MAX_SGE = 253,\n\tHOST_SLOT_STAT = 0,\n\tHOST_CTRL = 64,\n\tHOST_IRQ_STAT___2 = 68,\n\tHOST_PHY_CFG = 72,\n\tHOST_BIST_CTRL = 80,\n\tHOST_BIST_PTRN = 84,\n\tHOST_BIST_STAT = 88,\n\tHOST_MEM_BIST_STAT = 92,\n\tHOST_FLASH_CMD = 112,\n\tHOST_FLASH_DATA = 116,\n\tHOST_TRANSITION_DETECT = 117,\n\tHOST_GPIO_CTRL = 118,\n\tHOST_I2C_ADDR = 120,\n\tHOST_I2C_DATA = 124,\n\tHOST_I2C_XFER_CNT = 126,\n\tHOST_I2C_CTRL = 127,\n\tHOST_SSTAT_ATTN = -2147483648,\n\tHOST_CTRL_M66EN = 65536,\n\tHOST_CTRL_TRDY = 131072,\n\tHOST_CTRL_STOP = 262144,\n\tHOST_CTRL_DEVSEL = 524288,\n\tHOST_CTRL_REQ64 = 1048576,\n\tHOST_CTRL_GLOBAL_RST = -2147483648,\n\tPORT_REGS_SIZE = 8192,\n\tPORT_LRAM = 0,\n\tPORT_LRAM_SLOT_SZ = 128,\n\tPORT_PMP = 3968,\n\tPORT_PMP_STATUS = 0,\n\tPORT_PMP_QACTIVE = 4,\n\tPORT_PMP_SIZE = 8,\n\tPORT_CTRL_STAT = 4096,\n\tPORT_CTRL_CLR = 4100,\n\tPORT_IRQ_STAT___2 = 4104,\n\tPORT_IRQ_ENABLE_SET = 4112,\n\tPORT_IRQ_ENABLE_CLR = 4116,\n\tPORT_ACTIVATE_UPPER_ADDR = 4124,\n\tPORT_EXEC_FIFO = 4128,\n\tPORT_CMD_ERR = 4132,\n\tPORT_FIS_CFG = 4136,\n\tPORT_FIFO_THRES = 4140,\n\tPORT_DECODE_ERR_CNT = 4160,\n\tPORT_DECODE_ERR_THRESH = 4162,\n\tPORT_CRC_ERR_CNT = 4164,\n\tPORT_CRC_ERR_THRESH = 4166,\n\tPORT_HSHK_ERR_CNT = 4168,\n\tPORT_HSHK_ERR_THRESH = 4170,\n\tPORT_PHY_CFG = 4176,\n\tPORT_SLOT_STAT = 6144,\n\tPORT_CMD_ACTIVATE = 7168,\n\tPORT_CONTEXT = 7684,\n\tPORT_EXEC_DIAG = 7680,\n\tPORT_PSD_DIAG = 7744,\n\tPORT_SCONTROL = 7936,\n\tPORT_SSTATUS = 7940,\n\tPORT_SERROR = 7944,\n\tPORT_SACTIVE = 7948,\n\tPORT_CS_PORT_RST = 1,\n\tPORT_CS_DEV_RST = 2,\n\tPORT_CS_INIT = 4,\n\tPORT_CS_IRQ_WOC = 8,\n\tPORT_CS_CDB16 = 32,\n\tPORT_CS_PMP_RESUME = 64,\n\tPORT_CS_32BIT_ACTV = 1024,\n\tPORT_CS_PMP_EN = 8192,\n\tPORT_CS_RDY = -2147483648,\n\tPORT_IRQ_COMPLETE = 1,\n\tPORT_IRQ_ERROR___2 = 2,\n\tPORT_IRQ_PORTRDY_CHG = 4,\n\tPORT_IRQ_PWR_CHG = 8,\n\tPORT_IRQ_PHYRDY_CHG = 16,\n\tPORT_IRQ_COMWAKE = 32,\n\tPORT_IRQ_UNK_FIS___2 = 64,\n\tPORT_IRQ_DEV_XCHG = 128,\n\tPORT_IRQ_8B10B = 256,\n\tPORT_IRQ_CRC = 512,\n\tPORT_IRQ_HANDSHAKE = 1024,\n\tPORT_IRQ_SDB_NOTIFY = 2048,\n\tDEF_PORT_IRQ___2 = 2259,\n\tPORT_IRQ_RAW_SHIFT = 16,\n\tPORT_IRQ_MASKED_MASK = 2047,\n\tPORT_IRQ_RAW_MASK = 134152192,\n\tPORT_IRQ_STEER_SHIFT = 30,\n\tPORT_IRQ_STEER_MASK = -1073741824,\n\tPORT_CERR_DEV = 1,\n\tPORT_CERR_SDB = 2,\n\tPORT_CERR_DATA = 3,\n\tPORT_CERR_SEND = 4,\n\tPORT_CERR_INCONSISTENT = 5,\n\tPORT_CERR_DIRECTION = 6,\n\tPORT_CERR_UNDERRUN = 7,\n\tPORT_CERR_OVERRUN = 8,\n\tPORT_CERR_PKT_PROT = 11,\n\tPORT_CERR_SGT_BOUNDARY = 16,\n\tPORT_CERR_SGT_TGTABRT = 17,\n\tPORT_CERR_SGT_MSTABRT = 18,\n\tPORT_CERR_SGT_PCIPERR = 19,\n\tPORT_CERR_CMD_BOUNDARY = 24,\n\tPORT_CERR_CMD_TGTABRT = 25,\n\tPORT_CERR_CMD_MSTABRT = 26,\n\tPORT_CERR_CMD_PCIPERR = 27,\n\tPORT_CERR_XFR_UNDEF = 32,\n\tPORT_CERR_XFR_TGTABRT = 33,\n\tPORT_CERR_XFR_MSTABRT = 34,\n\tPORT_CERR_XFR_PCIPERR = 35,\n\tPORT_CERR_SENDSERVICE = 36,\n\tPRB_CTRL_PROTOCOL = 1,\n\tPRB_CTRL_PACKET_READ = 16,\n\tPRB_CTRL_PACKET_WRITE = 32,\n\tPRB_CTRL_NIEN = 64,\n\tPRB_CTRL_SRST = 128,\n\tPRB_PROT_PACKET = 1,\n\tPRB_PROT_TCQ = 2,\n\tPRB_PROT_NCQ = 4,\n\tPRB_PROT_READ = 8,\n\tPRB_PROT_WRITE = 16,\n\tPRB_PROT_TRANSPARENT = 32,\n\tSGE_TRM = -2147483648,\n\tSGE_LNK = 1073741824,\n\tSGE_DRD = 536870912,\n\tSIL24_MAX_CMDS = 31,\n\tBID_SIL3124 = 0,\n\tBID_SIL3132 = 1,\n\tBID_SIL3131 = 2,\n\tSIL24_COMMON_FLAGS = 918658,\n\tSIL24_FLAG_PCIX_IRQ_WOC = 16777216,\n\tIRQ_STAT_4PORTS = 15,\n};\n\nenum {\n\tSILERGY_SYR82X = 8,\n\tSILERGY_SYR83X = 9,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSKCIPHER_WALK_SLOW = 1,\n\tSKCIPHER_WALK_COPY = 2,\n\tSKCIPHER_WALK_DIFF = 4,\n\tSKCIPHER_WALK_SLEEP = 8,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSM6115_MASTER_AMPSS_M0 = 0,\n\tSM6115_MASTER_ANOC_SNOC = 1,\n\tSM6115_MASTER_BIMC_SNOC = 2,\n\tSM6115_MASTER_CAMNOC_HF = 3,\n\tSM6115_MASTER_CAMNOC_SF = 4,\n\tSM6115_MASTER_CRYPTO_CORE0 = 5,\n\tSM6115_MASTER_GRAPHICS_3D = 6,\n\tSM6115_MASTER_IPA = 7,\n\tSM6115_MASTER_MDP_PORT0 = 8,\n\tSM6115_MASTER_PIMEM = 9,\n\tSM6115_MASTER_QDSS_BAM = 10,\n\tSM6115_MASTER_QDSS_DAP = 11,\n\tSM6115_MASTER_QDSS_ETR = 12,\n\tSM6115_MASTER_QPIC = 13,\n\tSM6115_MASTER_QUP_0 = 14,\n\tSM6115_MASTER_QUP_CORE_0 = 15,\n\tSM6115_MASTER_SDCC_1 = 16,\n\tSM6115_MASTER_SDCC_2 = 17,\n\tSM6115_MASTER_SNOC_BIMC_NRT = 18,\n\tSM6115_MASTER_SNOC_BIMC_RT = 19,\n\tSM6115_MASTER_SNOC_BIMC = 20,\n\tSM6115_MASTER_SNOC_CFG = 21,\n\tSM6115_MASTER_SNOC_CNOC = 22,\n\tSM6115_MASTER_TCU_0 = 23,\n\tSM6115_MASTER_TIC = 24,\n\tSM6115_MASTER_USB3 = 25,\n\tSM6115_MASTER_VIDEO_P0 = 26,\n\tSM6115_MASTER_VIDEO_PROC = 27,\n\tSM6115_SLAVE_AHB2PHY_USB = 28,\n\tSM6115_SLAVE_ANOC_SNOC = 29,\n\tSM6115_SLAVE_APPSS = 30,\n\tSM6115_SLAVE_APSS_THROTTLE_CFG = 31,\n\tSM6115_SLAVE_BIMC_CFG = 32,\n\tSM6115_SLAVE_BIMC_SNOC = 33,\n\tSM6115_SLAVE_BOOT_ROM = 34,\n\tSM6115_SLAVE_CAMERA_CFG = 35,\n\tSM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG = 36,\n\tSM6115_SLAVE_CAMERA_RT_THROTTLE_CFG = 37,\n\tSM6115_SLAVE_CLK_CTL = 38,\n\tSM6115_SLAVE_CNOC_MSS = 39,\n\tSM6115_SLAVE_CRYPTO_0_CFG = 40,\n\tSM6115_SLAVE_DCC_CFG = 41,\n\tSM6115_SLAVE_DDR_PHY_CFG = 42,\n\tSM6115_SLAVE_DDR_SS_CFG = 43,\n\tSM6115_SLAVE_DISPLAY_CFG = 44,\n\tSM6115_SLAVE_DISPLAY_THROTTLE_CFG = 45,\n\tSM6115_SLAVE_EBI_CH0 = 46,\n\tSM6115_SLAVE_GPU_CFG = 47,\n\tSM6115_SLAVE_GPU_THROTTLE_CFG = 48,\n\tSM6115_SLAVE_HWKM_CORE = 49,\n\tSM6115_SLAVE_IMEM_CFG = 50,\n\tSM6115_SLAVE_IPA_CFG = 51,\n\tSM6115_SLAVE_LPASS = 52,\n\tSM6115_SLAVE_MAPSS = 53,\n\tSM6115_SLAVE_MDSP_MPU_CFG = 54,\n\tSM6115_SLAVE_MESSAGE_RAM = 55,\n\tSM6115_SLAVE_OCIMEM = 56,\n\tSM6115_SLAVE_PDM = 57,\n\tSM6115_SLAVE_PIMEM_CFG = 58,\n\tSM6115_SLAVE_PIMEM = 59,\n\tSM6115_SLAVE_PKA_CORE = 60,\n\tSM6115_SLAVE_PMIC_ARB = 61,\n\tSM6115_SLAVE_QDSS_CFG = 62,\n\tSM6115_SLAVE_QDSS_STM = 63,\n\tSM6115_SLAVE_QM_CFG = 64,\n\tSM6115_SLAVE_QM_MPU_CFG = 65,\n\tSM6115_SLAVE_QPIC = 66,\n\tSM6115_SLAVE_QUP_0 = 67,\n\tSM6115_SLAVE_QUP_CORE_0 = 68,\n\tSM6115_SLAVE_RBCPR_CX_CFG = 69,\n\tSM6115_SLAVE_RBCPR_MX_CFG = 70,\n\tSM6115_SLAVE_RPM = 71,\n\tSM6115_SLAVE_SDCC_1 = 72,\n\tSM6115_SLAVE_SDCC_2 = 73,\n\tSM6115_SLAVE_SECURITY = 74,\n\tSM6115_SLAVE_SERVICE_CNOC = 75,\n\tSM6115_SLAVE_SERVICE_SNOC = 76,\n\tSM6115_SLAVE_SNOC_BIMC_NRT = 77,\n\tSM6115_SLAVE_SNOC_BIMC_RT = 78,\n\tSM6115_SLAVE_SNOC_BIMC = 79,\n\tSM6115_SLAVE_SNOC_CFG = 80,\n\tSM6115_SLAVE_SNOC_CNOC = 81,\n\tSM6115_SLAVE_TCSR = 82,\n\tSM6115_SLAVE_TCU = 83,\n\tSM6115_SLAVE_TLMM = 84,\n\tSM6115_SLAVE_USB3 = 85,\n\tSM6115_SLAVE_VENUS_CFG = 86,\n\tSM6115_SLAVE_VENUS_THROTTLE_CFG = 87,\n\tSM6115_SLAVE_VSENSE_CTRL_CFG = 88,\n};\n\nenum {\n\tSM_EFUSE_READ = 0,\n\tSM_EFUSE_WRITE = 1,\n\tSM_EFUSE_USER_MAX = 2,\n\tSM_GET_CHIP_ID = 3,\n\tSM_A1_PWRC_SET = 4,\n\tSM_A1_PWRC_GET = 5,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSOUTH___5 = 0,\n\tEAST___3 = 1,\n\tWEST___3 = 2,\n};\n\nenum {\n\tSP_TASK_PENDING = 0,\n\tSP_NEED_VICTIM = 1,\n\tSP_VICTIM_REMAINS = 2,\n\tSP_TASK_STARTING = 3,\n};\n\nenum {\n\tSQ_START = 0,\n\tSQ_STOP = 1,\n\tSQ_ICU = 2,\n};\n\nenum {\n\tSQ_STS = 1,\n\tSQ_CUS = 2,\n};\n\nenum {\n\tSTATE_IDLE = 0,\n\tSTATE_READ = 1,\n\tSTATE_WRITE = 2,\n};\n\nenum {\n\tSTAT_CTRL = 3712,\n\tSTAT_LAST_IDX = 3716,\n\tSTAT_LIST_ADDR_LO = 3720,\n\tSTAT_LIST_ADDR_HI = 3724,\n\tSTAT_TXA1_RIDX = 3728,\n\tSTAT_TXS1_RIDX = 3730,\n\tSTAT_TXA2_RIDX = 3732,\n\tSTAT_TXS2_RIDX = 3734,\n\tSTAT_TX_IDX_TH = 3736,\n\tSTAT_PUT_IDX = 3740,\n\tSTAT_FIFO_WP = 3744,\n\tSTAT_FIFO_RP = 3748,\n\tSTAT_FIFO_RSP = 3750,\n\tSTAT_FIFO_LEVEL = 3752,\n\tSTAT_FIFO_SHLVL = 3754,\n\tSTAT_FIFO_WM = 3756,\n\tSTAT_FIFO_ISR_WM = 3757,\n\tSTAT_LEV_TIMER_INI = 3760,\n\tSTAT_LEV_TIMER_CNT = 3764,\n\tSTAT_LEV_TIMER_CTRL = 3768,\n\tSTAT_LEV_TIMER_TEST = 3769,\n\tSTAT_TX_TIMER_INI = 3776,\n\tSTAT_TX_TIMER_CNT = 3780,\n\tSTAT_TX_TIMER_CTRL = 3784,\n\tSTAT_TX_TIMER_TEST = 3785,\n\tSTAT_ISR_TIMER_INI = 3792,\n\tSTAT_ISR_TIMER_CNT = 3796,\n\tSTAT_ISR_TIMER_CTRL = 3800,\n\tSTAT_ISR_TIMER_TEST = 3801,\n};\n\nenum {\n\tSUNRPC_MAX_UDP_SENDPAGES = 11,\n};\n\nenum {\n\tSUNRPC_PIPEFS_NFS_PRIO = 0,\n\tSUNRPC_PIPEFS_RPC_PRIO = 1,\n};\n\nenum {\n\tSUNXI_SRC_TYPE_LEVEL_LOW = 0,\n\tSUNXI_SRC_TYPE_EDGE_FALLING = 1,\n\tSUNXI_SRC_TYPE_LEVEL_HIGH = 2,\n\tSUNXI_SRC_TYPE_EDGE_RISING = 3,\n};\n\nenum {\n\tSVC_HANDSHAKE_TO = 1250,\n};\n\nenum {\n\tSVC_POOL_AUTO = -1,\n\tSVC_POOL_GLOBAL = 0,\n\tSVC_POOL_PERCPU = 1,\n\tSVC_POOL_PERNODE = 2,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWMII_SPEED_10 = 0,\n\tSWMII_SPEED_100 = 1,\n\tSWMII_SPEED_1000 = 2,\n\tSWMII_DUPLEX_HALF = 0,\n\tSWMII_DUPLEX_FULL = 1,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = -1,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nenum {\n\tSYNC_LEN_G1 = 80000,\n\tSYNC_LEN_G2 = 40000,\n\tSYNC_LEN_G3 = 20000,\n};\n\nenum {\n\tSYSTAB = 0,\n\tMMBASE = 1,\n\tMMSIZE = 2,\n\tDCSIZE = 3,\n\tDCVERS = 4,\n\tPARAMCOUNT = 5,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_ATTR_UNSPEC = 0,\n\tTASKSTATS_CMD_ATTR_PID = 1,\n\tTASKSTATS_CMD_ATTR_TGID = 2,\n\tTASKSTATS_CMD_ATTR_REGISTER_CPUMASK = 3,\n\tTASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK = 4,\n\t__TASKSTATS_CMD_ATTR_MAX = 5,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASKSTATS_TYPE_UNSPEC = 0,\n\tTASKSTATS_TYPE_PID = 1,\n\tTASKSTATS_TYPE_TGID = 2,\n\tTASKSTATS_TYPE_STATS = 3,\n\tTASKSTATS_TYPE_AGGR_PID = 4,\n\tTASKSTATS_TYPE_AGGR_TGID = 5,\n\tTASKSTATS_TYPE_NULL = 6,\n\t__TASKSTATS_TYPE_MAX = 7,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTASK_REQ_UPIU_SIZE_DWORDS = 8,\n\tTASK_RSP_UPIU_SIZE_DWORDS = 8,\n\tALIGNED_UPIU_SIZE = 512,\n};\n\nenum {\n\tTBMU_TEST_BMU_TX_CHK_AUTO_OFF = -2147483648,\n\tTBMU_TEST_BMU_TX_CHK_AUTO_ON = 1073741824,\n\tTBMU_TEST_HOME_ADD_PAD_FIX1_EN = 536870912,\n\tTBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 268435456,\n\tTBMU_TEST_ROUTING_ADD_FIX_EN = 134217728,\n\tTBMU_TEST_ROUTING_ADD_FIX_DIS = 67108864,\n\tTBMU_TEST_HOME_ADD_FIX_EN = 33554432,\n\tTBMU_TEST_HOME_ADD_FIX_DIS = 16777216,\n\tTBMU_TEST_TEST_RSPTR_ON = 4194304,\n\tTBMU_TEST_TEST_RSPTR_OFF = 2097152,\n\tTBMU_TEST_TESTSTEP_RSPTR = 1048576,\n\tTBMU_TEST_TEST_RPTR_ON = 262144,\n\tTBMU_TEST_TEST_RPTR_OFF = 131072,\n\tTBMU_TEST_TESTSTEP_RPTR = 65536,\n\tTBMU_TEST_TEST_WSPTR_ON = 16384,\n\tTBMU_TEST_TEST_WSPTR_OFF = 8192,\n\tTBMU_TEST_TESTSTEP_WSPTR = 4096,\n\tTBMU_TEST_TEST_WPTR_ON = 1024,\n\tTBMU_TEST_TEST_WPTR_OFF = 512,\n\tTBMU_TEST_TESTSTEP_WPTR = 256,\n\tTBMU_TEST_TEST_REQ_NB_ON = 64,\n\tTBMU_TEST_TEST_REQ_NB_OFF = 32,\n\tTBMU_TEST_TESTSTEP_REQ_NB = 16,\n\tTBMU_TEST_TEST_DONE_IDX_ON = 4,\n\tTBMU_TEST_TEST_DONE_IDX_OFF = 2,\n\tTBMU_TEST_TESTSTEP_DONE_IDX = 1,\n};\n\nenum {\n\tTCA_ACT_UNSPEC = 0,\n\tTCA_ACT_KIND = 1,\n\tTCA_ACT_OPTIONS = 2,\n\tTCA_ACT_INDEX = 3,\n\tTCA_ACT_STATS = 4,\n\tTCA_ACT_PAD = 5,\n\tTCA_ACT_COOKIE = 6,\n\tTCA_ACT_FLAGS = 7,\n\tTCA_ACT_HW_STATS = 8,\n\tTCA_ACT_USED_HW_STATS = 9,\n\tTCA_ACT_IN_HW_COUNT = 10,\n\t__TCA_ACT_MAX = 11,\n};\n\nenum {\n\tTCA_FLOWER_KEY_CT_FLAGS_NEW = 1,\n\tTCA_FLOWER_KEY_CT_FLAGS_ESTABLISHED = 2,\n\tTCA_FLOWER_KEY_CT_FLAGS_RELATED = 4,\n\tTCA_FLOWER_KEY_CT_FLAGS_TRACKED = 8,\n\tTCA_FLOWER_KEY_CT_FLAGS_INVALID = 16,\n\tTCA_FLOWER_KEY_CT_FLAGS_REPLY = 32,\n\t__TCA_FLOWER_KEY_CT_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_ROOT_UNSPEC = 0,\n\tTCA_ROOT_TAB = 1,\n\tTCA_ROOT_FLAGS = 2,\n\tTCA_ROOT_COUNT = 3,\n\tTCA_ROOT_TIME_DELTA = 4,\n\tTCA_ROOT_EXT_WARN_MSG = 5,\n\t__TCA_ROOT_MAX = 6,\n};\n\nenum {\n\tTCA_STAB_UNSPEC = 0,\n\tTCA_STAB_BASE = 1,\n\tTCA_STAB_DATA = 2,\n\t__TCA_STAB_MAX = 3,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 1,\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 14,\n\tTCP_DATA_OFFSET = 240,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTCS4525_CHIP_ID_12 = 12,\n};\n\nenum {\n\tTCS4526_CHIP_ID_00 = 0,\n};\n\nenum {\n\tTC_MQPRIO_HW_OFFLOAD_NONE = 0,\n\tTC_MQPRIO_HW_OFFLOAD_TCS = 1,\n\t__TC_MQPRIO_HW_OFFLOAD_MAX = 2,\n};\n\nenum {\n\tTC_MQPRIO_MODE_DCB = 0,\n\tTC_MQPRIO_MODE_CHANNEL = 1,\n\t__TC_MQPRIO_MODE_MAX = 2,\n};\n\nenum {\n\tTC_MQPRIO_SHAPER_DCB = 0,\n\tTC_MQPRIO_SHAPER_BW_RATE = 1,\n\t__TC_MQPRIO_SHAPER_MAX = 2,\n};\n\nenum {\n\tTC_TAPRIO_CMD_SET_GATES = 0,\n\tTC_TAPRIO_CMD_SET_AND_HOLD = 1,\n\tTC_TAPRIO_CMD_SET_AND_RELEASE = 2,\n};\n\nenum {\n\tTEGRA_PIN_CAN0_DOUT_PAA0 = 0,\n\tTEGRA_PIN_CAN0_DIN_PAA1 = 1,\n\tTEGRA_PIN_CAN1_DOUT_PAA2 = 2,\n\tTEGRA_PIN_CAN1_DIN_PAA3 = 3,\n\tTEGRA_PIN_CAN0_STB_PAA4 = 4,\n\tTEGRA_PIN_CAN0_EN_PAA5 = 5,\n\tTEGRA_PIN_SOC_GPIO49_PAA6 = 6,\n\tTEGRA_PIN_CAN0_ERR_PAA7 = 7,\n\tTEGRA_PIN_CAN1_STB_PBB0 = 8,\n\tTEGRA_PIN_CAN1_EN_PBB1 = 9,\n\tTEGRA_PIN_SOC_GPIO50_PBB2 = 10,\n\tTEGRA_PIN_CAN1_ERR_PBB3 = 11,\n\tTEGRA_PIN_SPI2_SCK_PCC0 = 12,\n\tTEGRA_PIN_SPI2_MISO_PCC1 = 13,\n\tTEGRA_PIN_SPI2_MOSI_PCC2 = 14,\n\tTEGRA_PIN_SPI2_CS0_PCC3 = 15,\n\tTEGRA_PIN_TOUCH_CLK_PCC4 = 16,\n\tTEGRA_PIN_UART3_TX_PCC5 = 17,\n\tTEGRA_PIN_UART3_RX_PCC6 = 18,\n\tTEGRA_PIN_GEN2_I2C_SCL_PCC7 = 19,\n\tTEGRA_PIN_GEN2_I2C_SDA_PDD0 = 20,\n\tTEGRA_PIN_GEN8_I2C_SCL_PDD1 = 21,\n\tTEGRA_PIN_GEN8_I2C_SDA_PDD2 = 22,\n\tTEGRA_PIN_SCE_ERROR_PEE0 = 23,\n\tTEGRA_PIN_VCOMP_ALERT_PEE1 = 24,\n\tTEGRA_PIN_AO_RETENTION_N_PEE2 = 25,\n\tTEGRA_PIN_BATT_OC_PEE3 = 26,\n\tTEGRA_PIN_POWER_ON_PEE4 = 27,\n\tTEGRA_PIN_SOC_GPIO26_PEE5 = 28,\n\tTEGRA_PIN_SOC_GPIO27_PEE6 = 29,\n\tTEGRA_PIN_BOOTV_CTL_N_PEE7 = 30,\n\tTEGRA_PIN_HDMI_CEC_PGG0 = 31,\n};\n\nenum {\n\tTEGRA_PIN_CAN1_DOUT_PAA0 = 0,\n\tTEGRA_PIN_CAN1_DIN_PAA1 = 1,\n\tTEGRA_PIN_CAN0_DOUT_PAA2 = 2,\n\tTEGRA_PIN_CAN0_DIN_PAA3 = 3,\n\tTEGRA_PIN_CAN0_STB_PAA4___2 = 4,\n\tTEGRA_PIN_CAN0_EN_PAA5___2 = 5,\n\tTEGRA_PIN_CAN0_WAKE_PAA6 = 6,\n\tTEGRA_PIN_CAN0_ERR_PAA7___2 = 7,\n\tTEGRA_PIN_CAN1_STB_PBB0___2 = 8,\n\tTEGRA_PIN_CAN1_EN_PBB1___2 = 9,\n\tTEGRA_PIN_CAN1_WAKE_PBB2 = 10,\n\tTEGRA_PIN_CAN1_ERR_PBB3___2 = 11,\n\tTEGRA_PIN_SPI2_SCK_PCC0___2 = 12,\n\tTEGRA_PIN_SPI2_MISO_PCC1___2 = 13,\n\tTEGRA_PIN_SPI2_MOSI_PCC2___2 = 14,\n\tTEGRA_PIN_SPI2_CS0_PCC3___2 = 15,\n\tTEGRA_PIN_TOUCH_CLK_PCC4___2 = 16,\n\tTEGRA_PIN_UART3_TX_PCC5___2 = 17,\n\tTEGRA_PIN_UART3_RX_PCC6___2 = 18,\n\tTEGRA_PIN_GEN2_I2C_SCL_PCC7___2 = 19,\n\tTEGRA_PIN_GEN2_I2C_SDA_PDD0___2 = 20,\n\tTEGRA_PIN_GEN8_I2C_SCL_PDD1___2 = 21,\n\tTEGRA_PIN_GEN8_I2C_SDA_PDD2___2 = 22,\n\tTEGRA_PIN_SAFE_STATE_PEE0 = 23,\n\tTEGRA_PIN_VCOMP_ALERT_PEE1___2 = 24,\n\tTEGRA_PIN_AO_RETENTION_N_PEE2___2 = 25,\n\tTEGRA_PIN_BATT_OC_PEE3___2 = 26,\n\tTEGRA_PIN_POWER_ON_PEE4___2 = 27,\n\tTEGRA_PIN_PWR_I2C_SCL_PEE5 = 28,\n\tTEGRA_PIN_PWR_I2C_SDA_PEE6 = 29,\n\tTEGRA_PIN_SYS_RESET_N = 30,\n\tTEGRA_PIN_SHUTDOWN_N = 31,\n\tTEGRA_PIN_PMU_INT_N = 32,\n\tTEGRA_PIN_SOC_PWR_REQ = 33,\n\tTEGRA_PIN_CLK_32K_IN = 34,\n};\n\nenum {\n\tTEGRA_PIN_DAP6_SCLK_PA0 = 0,\n\tTEGRA_PIN_DAP6_DOUT_PA1 = 1,\n\tTEGRA_PIN_DAP6_DIN_PA2 = 2,\n\tTEGRA_PIN_DAP6_FS_PA3 = 3,\n\tTEGRA_PIN_DAP4_SCLK_PA4 = 4,\n\tTEGRA_PIN_DAP4_DOUT_PA5 = 5,\n\tTEGRA_PIN_DAP4_DIN_PA6 = 6,\n\tTEGRA_PIN_DAP4_FS_PA7 = 7,\n\tTEGRA_PIN_SOC_GPIO08_PB0 = 8,\n\tTEGRA_PIN_QSPI0_SCK_PC0 = 9,\n\tTEGRA_PIN_QSPI0_CS_N_PC1 = 10,\n\tTEGRA_PIN_QSPI0_IO0_PC2 = 11,\n\tTEGRA_PIN_QSPI0_IO1_PC3 = 12,\n\tTEGRA_PIN_QSPI0_IO2_PC4 = 13,\n\tTEGRA_PIN_QSPI0_IO3_PC5 = 14,\n\tTEGRA_PIN_QSPI1_SCK_PC6 = 15,\n\tTEGRA_PIN_QSPI1_CS_N_PC7 = 16,\n\tTEGRA_PIN_QSPI1_IO0_PD0 = 17,\n\tTEGRA_PIN_QSPI1_IO1_PD1 = 18,\n\tTEGRA_PIN_QSPI1_IO2_PD2 = 19,\n\tTEGRA_PIN_QSPI1_IO3_PD3 = 20,\n\tTEGRA_PIN_EQOS_TXC_PE0 = 21,\n\tTEGRA_PIN_EQOS_TD0_PE1 = 22,\n\tTEGRA_PIN_EQOS_TD1_PE2 = 23,\n\tTEGRA_PIN_EQOS_TD2_PE3 = 24,\n\tTEGRA_PIN_EQOS_TD3_PE4 = 25,\n\tTEGRA_PIN_EQOS_TX_CTL_PE5 = 26,\n\tTEGRA_PIN_EQOS_RD0_PE6 = 27,\n\tTEGRA_PIN_EQOS_RD1_PE7 = 28,\n\tTEGRA_PIN_EQOS_RD2_PF0 = 29,\n\tTEGRA_PIN_EQOS_RD3_PF1 = 30,\n\tTEGRA_PIN_EQOS_RX_CTL_PF2 = 31,\n\tTEGRA_PIN_EQOS_RXC_PF3 = 32,\n\tTEGRA_PIN_EQOS_SMA_MDIO_PF4 = 33,\n\tTEGRA_PIN_EQOS_SMA_MDC_PF5 = 34,\n\tTEGRA_PIN_SOC_GPIO13_PG0 = 35,\n\tTEGRA_PIN_SOC_GPIO14_PG1 = 36,\n\tTEGRA_PIN_SOC_GPIO15_PG2 = 37,\n\tTEGRA_PIN_SOC_GPIO16_PG3 = 38,\n\tTEGRA_PIN_SOC_GPIO17_PG4 = 39,\n\tTEGRA_PIN_SOC_GPIO18_PG5 = 40,\n\tTEGRA_PIN_SOC_GPIO19_PG6 = 41,\n\tTEGRA_PIN_SOC_GPIO20_PG7 = 42,\n\tTEGRA_PIN_SOC_GPIO21_PH0 = 43,\n\tTEGRA_PIN_SOC_GPIO22_PH1 = 44,\n\tTEGRA_PIN_SOC_GPIO06_PH2 = 45,\n\tTEGRA_PIN_UART4_TX_PH3 = 46,\n\tTEGRA_PIN_UART4_RX_PH4 = 47,\n\tTEGRA_PIN_UART4_RTS_PH5 = 48,\n\tTEGRA_PIN_UART4_CTS_PH6 = 49,\n\tTEGRA_PIN_SOC_GPIO41_PH7 = 50,\n\tTEGRA_PIN_SOC_GPIO42_PI0 = 51,\n\tTEGRA_PIN_SOC_GPIO43_PI1 = 52,\n\tTEGRA_PIN_SOC_GPIO44_PI2 = 53,\n\tTEGRA_PIN_GEN1_I2C_SCL_PI3 = 54,\n\tTEGRA_PIN_GEN1_I2C_SDA_PI4 = 55,\n\tTEGRA_PIN_CPU_PWR_REQ_PI5 = 56,\n\tTEGRA_PIN_SOC_GPIO07_PI6 = 57,\n\tTEGRA_PIN_SDMMC1_CLK_PJ0 = 58,\n\tTEGRA_PIN_SDMMC1_CMD_PJ1 = 59,\n\tTEGRA_PIN_SDMMC1_DAT0_PJ2 = 60,\n\tTEGRA_PIN_SDMMC1_DAT1_PJ3 = 61,\n\tTEGRA_PIN_SDMMC1_DAT2_PJ4 = 62,\n\tTEGRA_PIN_SDMMC1_DAT3_PJ5 = 63,\n\tTEGRA_PIN_PEX_L0_CLKREQ_N_PK0 = 64,\n\tTEGRA_PIN_PEX_L0_RST_N_PK1 = 65,\n\tTEGRA_PIN_PEX_L1_CLKREQ_N_PK2 = 66,\n\tTEGRA_PIN_PEX_L1_RST_N_PK3 = 67,\n\tTEGRA_PIN_PEX_L2_CLKREQ_N_PK4 = 68,\n\tTEGRA_PIN_PEX_L2_RST_N_PK5 = 69,\n\tTEGRA_PIN_PEX_L3_CLKREQ_N_PK6 = 70,\n\tTEGRA_PIN_PEX_L3_RST_N_PK7 = 71,\n\tTEGRA_PIN_PEX_L4_CLKREQ_N_PL0 = 72,\n\tTEGRA_PIN_PEX_L4_RST_N_PL1 = 73,\n\tTEGRA_PIN_PEX_WAKE_N_PL2 = 74,\n\tTEGRA_PIN_SOC_GPIO34_PL3 = 75,\n\tTEGRA_PIN_DP_AUX_CH0_HPD_PM0 = 76,\n\tTEGRA_PIN_DP_AUX_CH1_HPD_PM1 = 77,\n\tTEGRA_PIN_DP_AUX_CH2_HPD_PM2 = 78,\n\tTEGRA_PIN_DP_AUX_CH3_HPD_PM3 = 79,\n\tTEGRA_PIN_SOC_GPIO55_PM4 = 80,\n\tTEGRA_PIN_SOC_GPIO36_PM5 = 81,\n\tTEGRA_PIN_SOC_GPIO53_PM6 = 82,\n\tTEGRA_PIN_SOC_GPIO38_PM7 = 83,\n\tTEGRA_PIN_DP_AUX_CH3_N_PN0 = 84,\n\tTEGRA_PIN_SOC_GPIO39_PN1 = 85,\n\tTEGRA_PIN_SOC_GPIO40_PN2 = 86,\n\tTEGRA_PIN_DP_AUX_CH1_P_PN3 = 87,\n\tTEGRA_PIN_DP_AUX_CH1_N_PN4 = 88,\n\tTEGRA_PIN_DP_AUX_CH2_P_PN5 = 89,\n\tTEGRA_PIN_DP_AUX_CH2_N_PN6 = 90,\n\tTEGRA_PIN_DP_AUX_CH3_P_PN7 = 91,\n\tTEGRA_PIN_EXTPERIPH1_CLK_PP0 = 92,\n\tTEGRA_PIN_EXTPERIPH2_CLK_PP1 = 93,\n\tTEGRA_PIN_CAM_I2C_SCL_PP2 = 94,\n\tTEGRA_PIN_CAM_I2C_SDA_PP3 = 95,\n\tTEGRA_PIN_SOC_GPIO23_PP4 = 96,\n\tTEGRA_PIN_SOC_GPIO24_PP5 = 97,\n\tTEGRA_PIN_SOC_GPIO25_PP6 = 98,\n\tTEGRA_PIN_PWR_I2C_SCL_PP7 = 99,\n\tTEGRA_PIN_PWR_I2C_SDA_PQ0 = 100,\n\tTEGRA_PIN_SOC_GPIO28_PQ1 = 101,\n\tTEGRA_PIN_SOC_GPIO29_PQ2 = 102,\n\tTEGRA_PIN_SOC_GPIO30_PQ3 = 103,\n\tTEGRA_PIN_SOC_GPIO31_PQ4 = 104,\n\tTEGRA_PIN_SOC_GPIO32_PQ5 = 105,\n\tTEGRA_PIN_SOC_GPIO33_PQ6 = 106,\n\tTEGRA_PIN_SOC_GPIO35_PQ7 = 107,\n\tTEGRA_PIN_SOC_GPIO37_PR0 = 108,\n\tTEGRA_PIN_SOC_GPIO56_PR1 = 109,\n\tTEGRA_PIN_UART1_TX_PR2 = 110,\n\tTEGRA_PIN_UART1_RX_PR3 = 111,\n\tTEGRA_PIN_UART1_RTS_PR4 = 112,\n\tTEGRA_PIN_UART1_CTS_PR5 = 113,\n\tTEGRA_PIN_GPU_PWR_REQ_PX0 = 114,\n\tTEGRA_PIN_CV_PWR_REQ_PX1 = 115,\n\tTEGRA_PIN_GP_PWM2_PX2 = 116,\n\tTEGRA_PIN_GP_PWM3_PX3 = 117,\n\tTEGRA_PIN_UART2_TX_PX4 = 118,\n\tTEGRA_PIN_UART2_RX_PX5 = 119,\n\tTEGRA_PIN_UART2_RTS_PX6 = 120,\n\tTEGRA_PIN_UART2_CTS_PX7 = 121,\n\tTEGRA_PIN_SPI3_SCK_PY0 = 122,\n\tTEGRA_PIN_SPI3_MISO_PY1 = 123,\n\tTEGRA_PIN_SPI3_MOSI_PY2 = 124,\n\tTEGRA_PIN_SPI3_CS0_PY3 = 125,\n\tTEGRA_PIN_SPI3_CS1_PY4 = 126,\n\tTEGRA_PIN_UART5_TX_PY5 = 127,\n\tTEGRA_PIN_UART5_RX_PY6 = 128,\n\tTEGRA_PIN_UART5_RTS_PY7 = 129,\n\tTEGRA_PIN_UART5_CTS_PZ0 = 130,\n\tTEGRA_PIN_USB_VBUS_EN0_PZ1 = 131,\n\tTEGRA_PIN_USB_VBUS_EN1_PZ2 = 132,\n\tTEGRA_PIN_SPI1_SCK_PZ3 = 133,\n\tTEGRA_PIN_SPI1_MISO_PZ4 = 134,\n\tTEGRA_PIN_SPI1_MOSI_PZ5 = 135,\n\tTEGRA_PIN_SPI1_CS0_PZ6 = 136,\n\tTEGRA_PIN_SPI1_CS1_PZ7 = 137,\n\tTEGRA_PIN_SPI5_SCK_PAC0 = 138,\n\tTEGRA_PIN_SPI5_MISO_PAC1 = 139,\n\tTEGRA_PIN_SPI5_MOSI_PAC2 = 140,\n\tTEGRA_PIN_SPI5_CS0_PAC3 = 141,\n\tTEGRA_PIN_SOC_GPIO57_PAC4 = 142,\n\tTEGRA_PIN_SOC_GPIO58_PAC5 = 143,\n\tTEGRA_PIN_SOC_GPIO59_PAC6 = 144,\n\tTEGRA_PIN_SOC_GPIO60_PAC7 = 145,\n\tTEGRA_PIN_SOC_GPIO45_PAD0 = 146,\n\tTEGRA_PIN_SOC_GPIO46_PAD1 = 147,\n\tTEGRA_PIN_SOC_GPIO47_PAD2 = 148,\n\tTEGRA_PIN_SOC_GPIO48_PAD3 = 149,\n\tTEGRA_PIN_UFS0_REF_CLK_PAE0 = 150,\n\tTEGRA_PIN_UFS0_RST_N_PAE1 = 151,\n\tTEGRA_PIN_PEX_L5_CLKREQ_N_PAF0 = 152,\n\tTEGRA_PIN_PEX_L5_RST_N_PAF1 = 153,\n\tTEGRA_PIN_PEX_L6_CLKREQ_N_PAF2 = 154,\n\tTEGRA_PIN_PEX_L6_RST_N_PAF3 = 155,\n\tTEGRA_PIN_PEX_L7_CLKREQ_N_PAG0 = 156,\n\tTEGRA_PIN_PEX_L7_RST_N_PAG1 = 157,\n\tTEGRA_PIN_PEX_L8_CLKREQ_N_PAG2 = 158,\n\tTEGRA_PIN_PEX_L8_RST_N_PAG3 = 159,\n\tTEGRA_PIN_PEX_L9_CLKREQ_N_PAG4 = 160,\n\tTEGRA_PIN_PEX_L9_RST_N_PAG5 = 161,\n\tTEGRA_PIN_PEX_L10_CLKREQ_N_PAG6 = 162,\n\tTEGRA_PIN_PEX_L10_RST_N_PAG7 = 163,\n\tTEGRA_PIN_EQOS_COMP = 164,\n\tTEGRA_PIN_QSPI_COMP = 165,\n\tTEGRA_PIN_SDMMC1_COMP = 166,\n};\n\nenum {\n\tTEGRA_PIN_DAP6_SCLK_PA0___2 = 0,\n\tTEGRA_PIN_DAP6_DOUT_PA1___2 = 1,\n\tTEGRA_PIN_DAP6_DIN_PA2___2 = 2,\n\tTEGRA_PIN_DAP6_FS_PA3___2 = 3,\n\tTEGRA_PIN_DAP4_SCLK_PA4___2 = 4,\n\tTEGRA_PIN_DAP4_DOUT_PA5___2 = 5,\n\tTEGRA_PIN_DAP4_DIN_PA6___2 = 6,\n\tTEGRA_PIN_DAP4_FS_PA7___2 = 7,\n\tTEGRA_PIN_CPU_PWR_REQ_0_PB0 = 8,\n\tTEGRA_PIN_CPU_PWR_REQ_1_PB1 = 9,\n\tTEGRA_PIN_QSPI0_SCK_PC0___2 = 10,\n\tTEGRA_PIN_QSPI0_CS_N_PC1___2 = 11,\n\tTEGRA_PIN_QSPI0_IO0_PC2___2 = 12,\n\tTEGRA_PIN_QSPI0_IO1_PC3___2 = 13,\n\tTEGRA_PIN_QSPI0_IO2_PC4___2 = 14,\n\tTEGRA_PIN_QSPI0_IO3_PC5___2 = 15,\n\tTEGRA_PIN_QSPI1_SCK_PC6___2 = 16,\n\tTEGRA_PIN_QSPI1_CS_N_PC7___2 = 17,\n\tTEGRA_PIN_QSPI1_IO0_PD0___2 = 18,\n\tTEGRA_PIN_QSPI1_IO1_PD1___2 = 19,\n\tTEGRA_PIN_QSPI1_IO2_PD2___2 = 20,\n\tTEGRA_PIN_QSPI1_IO3_PD3___2 = 21,\n\tTEGRA_PIN_EQOS_TXC_PE0___2 = 22,\n\tTEGRA_PIN_EQOS_TD0_PE1___2 = 23,\n\tTEGRA_PIN_EQOS_TD1_PE2___2 = 24,\n\tTEGRA_PIN_EQOS_TD2_PE3___2 = 25,\n\tTEGRA_PIN_EQOS_TD3_PE4___2 = 26,\n\tTEGRA_PIN_EQOS_TX_CTL_PE5___2 = 27,\n\tTEGRA_PIN_EQOS_RD0_PE6___2 = 28,\n\tTEGRA_PIN_EQOS_RD1_PE7___2 = 29,\n\tTEGRA_PIN_EQOS_RD2_PF0___2 = 30,\n\tTEGRA_PIN_EQOS_RD3_PF1___2 = 31,\n\tTEGRA_PIN_EQOS_RX_CTL_PF2___2 = 32,\n\tTEGRA_PIN_EQOS_RXC_PF3___2 = 33,\n\tTEGRA_PIN_EQOS_SMA_MDIO_PF4___2 = 34,\n\tTEGRA_PIN_EQOS_SMA_MDC_PF5___2 = 35,\n\tTEGRA_PIN_SOC_GPIO00_PG0 = 36,\n\tTEGRA_PIN_SOC_GPIO01_PG1 = 37,\n\tTEGRA_PIN_SOC_GPIO02_PG2 = 38,\n\tTEGRA_PIN_SOC_GPIO03_PG3 = 39,\n\tTEGRA_PIN_SOC_GPIO08_PG4 = 40,\n\tTEGRA_PIN_SOC_GPIO09_PG5 = 41,\n\tTEGRA_PIN_SOC_GPIO10_PG6 = 42,\n\tTEGRA_PIN_SOC_GPIO11_PG7 = 43,\n\tTEGRA_PIN_SOC_GPIO12_PH0 = 44,\n\tTEGRA_PIN_SOC_GPIO13_PH1 = 45,\n\tTEGRA_PIN_SOC_GPIO14_PH2 = 46,\n\tTEGRA_PIN_UART4_TX_PH3___2 = 47,\n\tTEGRA_PIN_UART4_RX_PH4___2 = 48,\n\tTEGRA_PIN_UART4_RTS_PH5___2 = 49,\n\tTEGRA_PIN_UART4_CTS_PH6___2 = 50,\n\tTEGRA_PIN_DAP2_SCLK_PH7 = 51,\n\tTEGRA_PIN_DAP2_DOUT_PI0 = 52,\n\tTEGRA_PIN_DAP2_DIN_PI1 = 53,\n\tTEGRA_PIN_DAP2_FS_PI2 = 54,\n\tTEGRA_PIN_GEN1_I2C_SCL_PI3___2 = 55,\n\tTEGRA_PIN_GEN1_I2C_SDA_PI4___2 = 56,\n\tTEGRA_PIN_SDMMC1_CLK_PJ0___2 = 57,\n\tTEGRA_PIN_SDMMC1_CMD_PJ1___2 = 58,\n\tTEGRA_PIN_SDMMC1_DAT0_PJ2___2 = 59,\n\tTEGRA_PIN_SDMMC1_DAT1_PJ3___2 = 60,\n\tTEGRA_PIN_SDMMC1_DAT2_PJ4___2 = 61,\n\tTEGRA_PIN_SDMMC1_DAT3_PJ5___2 = 62,\n\tTEGRA_PIN_PEX_L0_CLKREQ_N_PK0___2 = 63,\n\tTEGRA_PIN_PEX_L0_RST_N_PK1___2 = 64,\n\tTEGRA_PIN_PEX_L1_CLKREQ_N_PK2___2 = 65,\n\tTEGRA_PIN_PEX_L1_RST_N_PK3___2 = 66,\n\tTEGRA_PIN_PEX_L2_CLKREQ_N_PK4___2 = 67,\n\tTEGRA_PIN_PEX_L2_RST_N_PK5___2 = 68,\n\tTEGRA_PIN_PEX_L3_CLKREQ_N_PK6___2 = 69,\n\tTEGRA_PIN_PEX_L3_RST_N_PK7___2 = 70,\n\tTEGRA_PIN_PEX_L4_CLKREQ_N_PL0___2 = 71,\n\tTEGRA_PIN_PEX_L4_RST_N_PL1___2 = 72,\n\tTEGRA_PIN_PEX_WAKE_N_PL2___2 = 73,\n\tTEGRA_PIN_SATA_DEV_SLP_PL3 = 74,\n\tTEGRA_PIN_DP_AUX_CH0_HPD_PM0___2 = 75,\n\tTEGRA_PIN_DP_AUX_CH1_HPD_PM1___2 = 76,\n\tTEGRA_PIN_DP_AUX_CH2_HPD_PM2___2 = 77,\n\tTEGRA_PIN_DP_AUX_CH3_HPD_PM3___2 = 78,\n\tTEGRA_PIN_HDMI_CEC_PM4 = 79,\n\tTEGRA_PIN_SOC_GPIO50_PM5 = 80,\n\tTEGRA_PIN_SOC_GPIO51_PM6 = 81,\n\tTEGRA_PIN_SOC_GPIO52_PM7 = 82,\n\tTEGRA_PIN_SOC_GPIO53_PN0 = 83,\n\tTEGRA_PIN_SOC_GPIO54_PN1 = 84,\n\tTEGRA_PIN_SOC_GPIO55_PN2 = 85,\n\tTEGRA_PIN_SDMMC3_CLK_PO0 = 86,\n\tTEGRA_PIN_SDMMC3_CMD_PO1 = 87,\n\tTEGRA_PIN_SDMMC3_DAT0_PO2 = 88,\n\tTEGRA_PIN_SDMMC3_DAT1_PO3 = 89,\n\tTEGRA_PIN_SDMMC3_DAT2_PO4 = 90,\n\tTEGRA_PIN_SDMMC3_DAT3_PO5 = 91,\n\tTEGRA_PIN_EXTPERIPH1_CLK_PP0___2 = 92,\n\tTEGRA_PIN_EXTPERIPH2_CLK_PP1___2 = 93,\n\tTEGRA_PIN_CAM_I2C_SCL_PP2___2 = 94,\n\tTEGRA_PIN_CAM_I2C_SDA_PP3___2 = 95,\n\tTEGRA_PIN_SOC_GPIO04_PP4 = 96,\n\tTEGRA_PIN_SOC_GPIO05_PP5 = 97,\n\tTEGRA_PIN_SOC_GPIO06_PP6 = 98,\n\tTEGRA_PIN_SOC_GPIO07_PP7 = 99,\n\tTEGRA_PIN_SOC_GPIO20_PQ0 = 100,\n\tTEGRA_PIN_SOC_GPIO21_PQ1 = 101,\n\tTEGRA_PIN_SOC_GPIO22_PQ2 = 102,\n\tTEGRA_PIN_SOC_GPIO23_PQ3 = 103,\n\tTEGRA_PIN_SOC_GPIO40_PQ4 = 104,\n\tTEGRA_PIN_SOC_GPIO41_PQ5 = 105,\n\tTEGRA_PIN_SOC_GPIO42_PQ6 = 106,\n\tTEGRA_PIN_SOC_GPIO43_PQ7 = 107,\n\tTEGRA_PIN_SOC_GPIO44_PR0 = 108,\n\tTEGRA_PIN_SOC_GPIO45_PR1 = 109,\n\tTEGRA_PIN_UART1_TX_PR2___2 = 110,\n\tTEGRA_PIN_UART1_RX_PR3___2 = 111,\n\tTEGRA_PIN_UART1_RTS_PR4___2 = 112,\n\tTEGRA_PIN_UART1_CTS_PR5___2 = 113,\n\tTEGRA_PIN_DAP1_SCLK_PS0 = 114,\n\tTEGRA_PIN_DAP1_DOUT_PS1 = 115,\n\tTEGRA_PIN_DAP1_DIN_PS2 = 116,\n\tTEGRA_PIN_DAP1_FS_PS3 = 117,\n\tTEGRA_PIN_AUD_MCLK_PS4 = 118,\n\tTEGRA_PIN_SOC_GPIO30_PS5 = 119,\n\tTEGRA_PIN_SOC_GPIO31_PS6 = 120,\n\tTEGRA_PIN_SOC_GPIO32_PS7 = 121,\n\tTEGRA_PIN_SOC_GPIO33_PT0 = 122,\n\tTEGRA_PIN_DAP3_SCLK_PT1 = 123,\n\tTEGRA_PIN_DAP3_DOUT_PT2 = 124,\n\tTEGRA_PIN_DAP3_DIN_PT3 = 125,\n\tTEGRA_PIN_DAP3_FS_PT4 = 126,\n\tTEGRA_PIN_DAP5_SCLK_PT5 = 127,\n\tTEGRA_PIN_DAP5_DOUT_PT6 = 128,\n\tTEGRA_PIN_DAP5_DIN_PT7 = 129,\n\tTEGRA_PIN_DAP5_FS_PU0 = 130,\n\tTEGRA_PIN_DIRECTDC1_CLK_PV0 = 131,\n\tTEGRA_PIN_DIRECTDC1_IN_PV1 = 132,\n\tTEGRA_PIN_DIRECTDC1_OUT0_PV2 = 133,\n\tTEGRA_PIN_DIRECTDC1_OUT1_PV3 = 134,\n\tTEGRA_PIN_DIRECTDC1_OUT2_PV4 = 135,\n\tTEGRA_PIN_DIRECTDC1_OUT3_PV5 = 136,\n\tTEGRA_PIN_DIRECTDC1_OUT4_PV6 = 137,\n\tTEGRA_PIN_DIRECTDC1_OUT5_PV7 = 138,\n\tTEGRA_PIN_DIRECTDC1_OUT6_PW0 = 139,\n\tTEGRA_PIN_DIRECTDC1_OUT7_PW1 = 140,\n\tTEGRA_PIN_GPU_PWR_REQ_PX0___2 = 141,\n\tTEGRA_PIN_CV_PWR_REQ_PX1___2 = 142,\n\tTEGRA_PIN_GP_PWM2_PX2___2 = 143,\n\tTEGRA_PIN_GP_PWM3_PX3___2 = 144,\n\tTEGRA_PIN_UART2_TX_PX4___2 = 145,\n\tTEGRA_PIN_UART2_RX_PX5___2 = 146,\n\tTEGRA_PIN_UART2_RTS_PX6___2 = 147,\n\tTEGRA_PIN_UART2_CTS_PX7___2 = 148,\n\tTEGRA_PIN_SPI3_SCK_PY0___2 = 149,\n\tTEGRA_PIN_SPI3_MISO_PY1___2 = 150,\n\tTEGRA_PIN_SPI3_MOSI_PY2___2 = 151,\n\tTEGRA_PIN_SPI3_CS0_PY3___2 = 152,\n\tTEGRA_PIN_SPI3_CS1_PY4___2 = 153,\n\tTEGRA_PIN_UART5_TX_PY5___2 = 154,\n\tTEGRA_PIN_UART5_RX_PY6___2 = 155,\n\tTEGRA_PIN_UART5_RTS_PY7___2 = 156,\n\tTEGRA_PIN_UART5_CTS_PZ0___2 = 157,\n\tTEGRA_PIN_USB_VBUS_EN0_PZ1___2 = 158,\n\tTEGRA_PIN_USB_VBUS_EN1_PZ2___2 = 159,\n\tTEGRA_PIN_SPI1_SCK_PZ3___2 = 160,\n\tTEGRA_PIN_SPI1_MISO_PZ4___2 = 161,\n\tTEGRA_PIN_SPI1_MOSI_PZ5___2 = 162,\n\tTEGRA_PIN_SPI1_CS0_PZ6___2 = 163,\n\tTEGRA_PIN_SPI1_CS1_PZ7___2 = 164,\n\tTEGRA_PIN_UFS0_REF_CLK_PFF0 = 165,\n\tTEGRA_PIN_UFS0_RST_PFF1 = 166,\n\tTEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 167,\n\tTEGRA_PIN_PEX_L5_RST_N_PGG1 = 168,\n\tTEGRA_PIN_DIRECTDC_COMP = 169,\n\tTEGRA_PIN_SDMMC4_CLK = 170,\n\tTEGRA_PIN_SDMMC4_CMD = 171,\n\tTEGRA_PIN_SDMMC4_DQS = 172,\n\tTEGRA_PIN_SDMMC4_DAT7 = 173,\n\tTEGRA_PIN_SDMMC4_DAT6 = 174,\n\tTEGRA_PIN_SDMMC4_DAT5 = 175,\n\tTEGRA_PIN_SDMMC4_DAT4 = 176,\n\tTEGRA_PIN_SDMMC4_DAT3 = 177,\n\tTEGRA_PIN_SDMMC4_DAT2 = 178,\n\tTEGRA_PIN_SDMMC4_DAT1 = 179,\n\tTEGRA_PIN_SDMMC4_DAT0 = 180,\n\tTEGRA_PIN_SDMMC1_COMP___2 = 181,\n\tTEGRA_PIN_SDMMC1_HV_TRIM = 182,\n\tTEGRA_PIN_SDMMC3_COMP = 183,\n\tTEGRA_PIN_SDMMC3_HV_TRIM = 184,\n\tTEGRA_PIN_EQOS_COMP___2 = 185,\n\tTEGRA_PIN_QSPI_COMP___2 = 186,\n};\n\nenum {\n\tTEGRA_PIN_PEX_L0_RST_N_PA0 = 0,\n\tTEGRA_PIN_PEX_L0_CLKREQ_N_PA1 = 1,\n\tTEGRA_PIN_PEX_WAKE_N_PA2 = 2,\n\tTEGRA_PIN_PEX_L1_RST_N_PA3 = 3,\n\tTEGRA_PIN_PEX_L1_CLKREQ_N_PA4 = 4,\n\tTEGRA_PIN_PEX_L2_RST_N_PA5 = 5,\n\tTEGRA_PIN_PEX_L2_CLKREQ_N_PA6 = 6,\n\tTEGRA_PIN_UART4_TX_PB0 = 7,\n\tTEGRA_PIN_UART4_RX_PB1 = 8,\n\tTEGRA_PIN_UART4_RTS_PB2 = 9,\n\tTEGRA_PIN_UART4_CTS_PB3 = 10,\n\tTEGRA_PIN_GPIO_WAN1_PB4 = 11,\n\tTEGRA_PIN_GPIO_WAN2_PB5 = 12,\n\tTEGRA_PIN_GPIO_WAN3_PB6 = 13,\n\tTEGRA_PIN_GPIO_WAN4_PC0 = 14,\n\tTEGRA_PIN_DAP2_SCLK_PC1 = 15,\n\tTEGRA_PIN_DAP2_DOUT_PC2 = 16,\n\tTEGRA_PIN_DAP2_DIN_PC3 = 17,\n\tTEGRA_PIN_DAP2_FS_PC4 = 18,\n\tTEGRA_PIN_GEN1_I2C_SCL_PC5 = 19,\n\tTEGRA_PIN_GEN1_I2C_SDA_PC6 = 20,\n\tTEGRA_PIN_SDMMC1_CLK_PD0 = 21,\n\tTEGRA_PIN_SDMMC1_CMD_PD1 = 22,\n\tTEGRA_PIN_SDMMC1_DAT0_PD2 = 23,\n\tTEGRA_PIN_SDMMC1_DAT1_PD3 = 24,\n\tTEGRA_PIN_SDMMC1_DAT2_PD4 = 25,\n\tTEGRA_PIN_SDMMC1_DAT3_PD5 = 26,\n\tTEGRA_PIN_EQOS_TXC_PE0___3 = 27,\n\tTEGRA_PIN_EQOS_TD0_PE1___3 = 28,\n\tTEGRA_PIN_EQOS_TD1_PE2___3 = 29,\n\tTEGRA_PIN_EQOS_TD2_PE3___3 = 30,\n\tTEGRA_PIN_EQOS_TD3_PE4___3 = 31,\n\tTEGRA_PIN_EQOS_TX_CTL_PE5___3 = 32,\n\tTEGRA_PIN_EQOS_RD0_PE6___3 = 33,\n\tTEGRA_PIN_EQOS_RD1_PE7___3 = 34,\n\tTEGRA_PIN_EQOS_RD2_PF0___3 = 35,\n\tTEGRA_PIN_EQOS_RD3_PF1___3 = 36,\n\tTEGRA_PIN_EQOS_RX_CTL_PF2___3 = 37,\n\tTEGRA_PIN_EQOS_RXC_PF3___3 = 38,\n\tTEGRA_PIN_EQOS_MDIO_PF4 = 39,\n\tTEGRA_PIN_EQOS_MDC_PF5 = 40,\n\tTEGRA_PIN_SDMMC3_CLK_PG0 = 41,\n\tTEGRA_PIN_SDMMC3_CMD_PG1 = 42,\n\tTEGRA_PIN_SDMMC3_DAT0_PG2 = 43,\n\tTEGRA_PIN_SDMMC3_DAT1_PG3 = 44,\n\tTEGRA_PIN_SDMMC3_DAT2_PG4 = 45,\n\tTEGRA_PIN_SDMMC3_DAT3_PG5 = 46,\n\tTEGRA_PIN_GPIO_WAN5_PH0 = 47,\n\tTEGRA_PIN_GPIO_WAN6_PH1 = 48,\n\tTEGRA_PIN_GPIO_WAN7_PH2 = 49,\n\tTEGRA_PIN_GPIO_WAN8_PH3 = 50,\n\tTEGRA_PIN_BCPU_PWR_REQ_PH4 = 51,\n\tTEGRA_PIN_MCPU_PWR_REQ_PH5 = 52,\n\tTEGRA_PIN_GPU_PWR_REQ_PH6 = 53,\n\tTEGRA_PIN_GPIO_PQ0_PI0 = 54,\n\tTEGRA_PIN_GPIO_PQ1_PI1 = 55,\n\tTEGRA_PIN_GPIO_PQ2_PI2 = 56,\n\tTEGRA_PIN_GPIO_PQ3_PI3 = 57,\n\tTEGRA_PIN_GPIO_PQ4_PI4 = 58,\n\tTEGRA_PIN_GPIO_PQ5_PI5 = 59,\n\tTEGRA_PIN_GPIO_PQ6_PI6 = 60,\n\tTEGRA_PIN_GPIO_PQ7_PI7 = 61,\n\tTEGRA_PIN_DAP1_SCLK_PJ0 = 62,\n\tTEGRA_PIN_DAP1_DOUT_PJ1 = 63,\n\tTEGRA_PIN_DAP1_DIN_PJ2 = 64,\n\tTEGRA_PIN_DAP1_FS_PJ3 = 65,\n\tTEGRA_PIN_AUD_MCLK_PJ4 = 66,\n\tTEGRA_PIN_GPIO_AUD0_PJ5 = 67,\n\tTEGRA_PIN_GPIO_AUD1_PJ6 = 68,\n\tTEGRA_PIN_GPIO_AUD2_PJ7 = 69,\n\tTEGRA_PIN_GPIO_AUD3_PK0 = 70,\n\tTEGRA_PIN_GEN7_I2C_SCL_PL0 = 71,\n\tTEGRA_PIN_GEN7_I2C_SDA_PL1 = 72,\n\tTEGRA_PIN_GEN9_I2C_SCL_PL2 = 73,\n\tTEGRA_PIN_GEN9_I2C_SDA_PL3 = 74,\n\tTEGRA_PIN_USB_VBUS_EN0_PL4 = 75,\n\tTEGRA_PIN_USB_VBUS_EN1_PL5 = 76,\n\tTEGRA_PIN_GP_PWM6_PL6 = 77,\n\tTEGRA_PIN_GP_PWM7_PL7 = 78,\n\tTEGRA_PIN_DMIC1_DAT_PM0 = 79,\n\tTEGRA_PIN_DMIC1_CLK_PM1 = 80,\n\tTEGRA_PIN_DMIC2_DAT_PM2 = 81,\n\tTEGRA_PIN_DMIC2_CLK_PM3 = 82,\n\tTEGRA_PIN_DMIC4_DAT_PM4 = 83,\n\tTEGRA_PIN_DMIC4_CLK_PM5 = 84,\n\tTEGRA_PIN_GPIO_CAM1_PN0 = 85,\n\tTEGRA_PIN_GPIO_CAM2_PN1 = 86,\n\tTEGRA_PIN_GPIO_CAM3_PN2 = 87,\n\tTEGRA_PIN_GPIO_CAM4_PN3 = 88,\n\tTEGRA_PIN_GPIO_CAM5_PN4 = 89,\n\tTEGRA_PIN_GPIO_CAM6_PN5 = 90,\n\tTEGRA_PIN_GPIO_CAM7_PN6 = 91,\n\tTEGRA_PIN_EXTPERIPH1_CLK_PO0 = 92,\n\tTEGRA_PIN_EXTPERIPH2_CLK_PO1 = 93,\n\tTEGRA_PIN_CAM_I2C_SCL_PO2 = 94,\n\tTEGRA_PIN_CAM_I2C_SDA_PO3 = 95,\n\tTEGRA_PIN_DP_AUX_CH0_HPD_PP0 = 96,\n\tTEGRA_PIN_DP_AUX_CH1_HPD_PP1 = 97,\n\tTEGRA_PIN_HDMI_CEC_PP2 = 98,\n\tTEGRA_PIN_GPIO_EDP0_PP3 = 99,\n\tTEGRA_PIN_GPIO_EDP1_PP4 = 100,\n\tTEGRA_PIN_GPIO_EDP2_PP5 = 101,\n\tTEGRA_PIN_GPIO_EDP3_PP6 = 102,\n\tTEGRA_PIN_DIRECTDC1_CLK_PQ0 = 103,\n\tTEGRA_PIN_DIRECTDC1_IN_PQ1 = 104,\n\tTEGRA_PIN_DIRECTDC1_OUT0_PQ2 = 105,\n\tTEGRA_PIN_DIRECTDC1_OUT1_PQ3 = 106,\n\tTEGRA_PIN_DIRECTDC1_OUT2_PQ4 = 107,\n\tTEGRA_PIN_DIRECTDC1_OUT3_PQ5 = 108,\n\tTEGRA_PIN_QSPI_SCK_PR0 = 109,\n\tTEGRA_PIN_QSPI_IO0_PR1 = 110,\n\tTEGRA_PIN_QSPI_IO1_PR2 = 111,\n\tTEGRA_PIN_QSPI_IO2_PR3 = 112,\n\tTEGRA_PIN_QSPI_IO3_PR4 = 113,\n\tTEGRA_PIN_QSPI_CS_N_PR5 = 114,\n\tTEGRA_PIN_UART1_TX_PT0 = 115,\n\tTEGRA_PIN_UART1_RX_PT1 = 116,\n\tTEGRA_PIN_UART1_RTS_PT2 = 117,\n\tTEGRA_PIN_UART1_CTS_PT3 = 118,\n\tTEGRA_PIN_UART2_TX_PX0 = 119,\n\tTEGRA_PIN_UART2_RX_PX1 = 120,\n\tTEGRA_PIN_UART2_RTS_PX2 = 121,\n\tTEGRA_PIN_UART2_CTS_PX3 = 122,\n\tTEGRA_PIN_UART5_TX_PX4 = 123,\n\tTEGRA_PIN_UART5_RX_PX5 = 124,\n\tTEGRA_PIN_UART5_RTS_PX6 = 125,\n\tTEGRA_PIN_UART5_CTS_PX7 = 126,\n\tTEGRA_PIN_GPIO_MDM1_PY0 = 127,\n\tTEGRA_PIN_GPIO_MDM2_PY1 = 128,\n\tTEGRA_PIN_GPIO_MDM3_PY2 = 129,\n\tTEGRA_PIN_GPIO_MDM4_PY3 = 130,\n\tTEGRA_PIN_GPIO_MDM5_PY4 = 131,\n\tTEGRA_PIN_GPIO_MDM6_PY5 = 132,\n\tTEGRA_PIN_GPIO_MDM7_PY6 = 133,\n\tTEGRA_PIN_UFS0_REF_CLK_PBB0 = 134,\n\tTEGRA_PIN_UFS0_RST_PBB1 = 135,\n\tTEGRA_PIN_DAP4_SCLK_PCC0 = 136,\n\tTEGRA_PIN_DAP4_DOUT_PCC1 = 137,\n\tTEGRA_PIN_DAP4_DIN_PCC2 = 138,\n\tTEGRA_PIN_DAP4_FS_PCC3 = 139,\n\tTEGRA_PIN_DIRECTDC_COMP___2 = 140,\n\tTEGRA_PIN_SDMMC1_COMP___3 = 141,\n\tTEGRA_PIN_EQOS_COMP___3 = 142,\n\tTEGRA_PIN_SDMMC3_COMP___2 = 143,\n\tTEGRA_PIN_QSPI_COMP___3 = 144,\n};\n\nenum {\n\tTEGRA_PIN_PWR_I2C_SCL_PS0 = 0,\n\tTEGRA_PIN_PWR_I2C_SDA_PS1 = 1,\n\tTEGRA_PIN_BATT_OC_PS2 = 2,\n\tTEGRA_PIN_SAFE_STATE_PS3 = 3,\n\tTEGRA_PIN_VCOMP_ALERT_PS4 = 4,\n\tTEGRA_PIN_GPIO_DIS0_PU0 = 5,\n\tTEGRA_PIN_GPIO_DIS1_PU1 = 6,\n\tTEGRA_PIN_GPIO_DIS2_PU2 = 7,\n\tTEGRA_PIN_GPIO_DIS3_PU3 = 8,\n\tTEGRA_PIN_GPIO_DIS4_PU4 = 9,\n\tTEGRA_PIN_GPIO_DIS5_PU5 = 10,\n\tTEGRA_PIN_GPIO_SEN0_PV0 = 11,\n\tTEGRA_PIN_GPIO_SEN1_PV1 = 12,\n\tTEGRA_PIN_GPIO_SEN2_PV2 = 13,\n\tTEGRA_PIN_GPIO_SEN3_PV3 = 14,\n\tTEGRA_PIN_GPIO_SEN4_PV4 = 15,\n\tTEGRA_PIN_GPIO_SEN5_PV5 = 16,\n\tTEGRA_PIN_GPIO_SEN6_PV6 = 17,\n\tTEGRA_PIN_GPIO_SEN7_PV7 = 18,\n\tTEGRA_PIN_GEN8_I2C_SCL_PW0 = 19,\n\tTEGRA_PIN_GEN8_I2C_SDA_PW1 = 20,\n\tTEGRA_PIN_UART3_TX_PW2 = 21,\n\tTEGRA_PIN_UART3_RX_PW3 = 22,\n\tTEGRA_PIN_UART3_RTS_PW4 = 23,\n\tTEGRA_PIN_UART3_CTS_PW5 = 24,\n\tTEGRA_PIN_UART7_TX_PW6 = 25,\n\tTEGRA_PIN_UART7_RX_PW7 = 26,\n\tTEGRA_PIN_CAN1_DOUT_PZ0 = 27,\n\tTEGRA_PIN_CAN1_DIN_PZ1 = 28,\n\tTEGRA_PIN_CAN0_DOUT_PZ2 = 29,\n\tTEGRA_PIN_CAN0_DIN_PZ3 = 30,\n\tTEGRA_PIN_CAN_GPIO0_PAA0 = 31,\n\tTEGRA_PIN_CAN_GPIO1_PAA1 = 32,\n\tTEGRA_PIN_CAN_GPIO2_PAA2 = 33,\n\tTEGRA_PIN_CAN_GPIO3_PAA3 = 34,\n\tTEGRA_PIN_CAN_GPIO4_PAA4 = 35,\n\tTEGRA_PIN_CAN_GPIO5_PAA5 = 36,\n\tTEGRA_PIN_CAN_GPIO6_PAA6 = 37,\n\tTEGRA_PIN_CAN_GPIO7_PAA7 = 38,\n\tTEGRA_PIN_GPIO_SEN8_PEE0 = 39,\n\tTEGRA_PIN_GPIO_SEN9_PEE1 = 40,\n\tTEGRA_PIN_TOUCH_CLK_PEE2 = 41,\n\tTEGRA_PIN_POWER_ON_PFF0 = 42,\n\tTEGRA_PIN_GPIO_SW1_PFF1 = 43,\n\tTEGRA_PIN_GPIO_SW2_PFF2 = 44,\n\tTEGRA_PIN_GPIO_SW3_PFF3 = 45,\n\tTEGRA_PIN_GPIO_SW4_PFF4 = 46,\n\tTEGRA_PIN_SHUTDOWN = 47,\n\tTEGRA_PIN_PMU_INT = 48,\n\tTEGRA_PIN_SOC_PWR_REQ___2 = 49,\n\tTEGRA_PIN_CLK_32K_IN___2 = 50,\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nenum {\n\tTHRESHOLD_INDEX_0 = 0,\n\tTHRESHOLD_INDEX_1 = 1,\n\tTHRESHOLD_INDEX_COUNT = 2,\n};\n\nenum {\n\tTIM_START = 4,\n\tTIM_STOP = 2,\n\tTIM_CLR_IRQ = 1,\n};\n\nenum {\n\tTLS_ALERT_DESC_CLOSE_NOTIFY = 0,\n\tTLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10,\n\tTLS_ALERT_DESC_BAD_RECORD_MAC = 20,\n\tTLS_ALERT_DESC_RECORD_OVERFLOW = 22,\n\tTLS_ALERT_DESC_HANDSHAKE_FAILURE = 40,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE = 42,\n\tTLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43,\n\tTLS_ALERT_DESC_CERTIFICATE_REVOKED = 44,\n\tTLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45,\n\tTLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46,\n\tTLS_ALERT_DESC_ILLEGAL_PARAMETER = 47,\n\tTLS_ALERT_DESC_UNKNOWN_CA = 48,\n\tTLS_ALERT_DESC_ACCESS_DENIED = 49,\n\tTLS_ALERT_DESC_DECODE_ERROR = 50,\n\tTLS_ALERT_DESC_DECRYPT_ERROR = 51,\n\tTLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52,\n\tTLS_ALERT_DESC_PROTOCOL_VERSION = 70,\n\tTLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71,\n\tTLS_ALERT_DESC_INTERNAL_ERROR = 80,\n\tTLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86,\n\tTLS_ALERT_DESC_USER_CANCELED = 90,\n\tTLS_ALERT_DESC_MISSING_EXTENSION = 109,\n\tTLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110,\n\tTLS_ALERT_DESC_UNRECOGNIZED_NAME = 112,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113,\n\tTLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115,\n\tTLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116,\n\tTLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120,\n};\n\nenum {\n\tTLS_ALERT_LEVEL_WARNING = 1,\n\tTLS_ALERT_LEVEL_FATAL = 2,\n};\n\nenum {\n\tTLS_NO_KEYRING = 0,\n\tTLS_NO_PEERID = 0,\n\tTLS_NO_CERT = 0,\n\tTLS_NO_PRIVKEY = 0,\n};\n\nenum {\n\tTLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20,\n\tTLS_RECORD_TYPE_ALERT = 21,\n\tTLS_RECORD_TYPE_HANDSHAKE = 22,\n\tTLS_RECORD_TYPE_DATA = 23,\n\tTLS_RECORD_TYPE_HEARTBEAT = 24,\n\tTLS_RECORD_TYPE_TLS12_CID = 25,\n\tTLS_RECORD_TYPE_ACK = 26,\n};\n\nenum {\n\tTOKEN_END = 0,\n\tTOKEN_START = 1,\n\tTOKEN_SLAVE_ADDR_WRITE = 2,\n\tTOKEN_SLAVE_ADDR_READ = 3,\n\tTOKEN_DATA = 4,\n\tTOKEN_DATA_LAST = 5,\n\tTOKEN_STOP = 6,\n};\n\nenum {\n\tTOO_MANY_CLOSE = -1,\n\tTOO_MANY_OPEN = -2,\n\tMISSING_QUOTE = -3,\n};\n\nenum {\n\tTPS65219_INT_LDO3_SCG = 0,\n\tTPS65219_INT_LDO3_OC = 1,\n\tTPS65219_INT_LDO3_UV = 2,\n\tTPS65219_INT_LDO4_SCG = 3,\n\tTPS65219_INT_LDO4_OC = 4,\n\tTPS65219_INT_LDO4_UV = 5,\n\tTPS65215_INT_LDO1_SCG = 6,\n\tTPS65215_INT_LDO1_OC = 7,\n\tTPS65215_INT_LDO1_UV = 8,\n\tTPS65215_INT_LDO2_SCG = 9,\n\tTPS65215_INT_LDO2_OC = 10,\n\tTPS65215_INT_LDO2_UV = 11,\n\tTPS65219_INT_LDO1_SCG = 12,\n\tTPS65219_INT_LDO1_OC = 13,\n\tTPS65219_INT_LDO1_UV = 14,\n\tTPS65219_INT_LDO2_SCG = 15,\n\tTPS65219_INT_LDO2_OC = 16,\n\tTPS65219_INT_LDO2_UV = 17,\n\tTPS65219_INT_BUCK3_SCG = 18,\n\tTPS65219_INT_BUCK3_OC = 19,\n\tTPS65219_INT_BUCK3_NEG_OC = 20,\n\tTPS65219_INT_BUCK3_UV = 21,\n\tTPS65219_INT_BUCK1_SCG = 22,\n\tTPS65219_INT_BUCK1_OC = 23,\n\tTPS65219_INT_BUCK1_NEG_OC = 24,\n\tTPS65219_INT_BUCK1_UV = 25,\n\tTPS65219_INT_BUCK2_SCG = 26,\n\tTPS65219_INT_BUCK2_OC = 27,\n\tTPS65219_INT_BUCK2_NEG_OC = 28,\n\tTPS65219_INT_BUCK2_UV = 29,\n\tTPS65219_INT_SENSOR_3_WARM = 30,\n\tTPS65219_INT_SENSOR_2_WARM = 31,\n\tTPS65219_INT_SENSOR_1_WARM = 32,\n\tTPS65219_INT_SENSOR_0_WARM = 33,\n\tTPS65219_INT_SENSOR_3_HOT = 34,\n\tTPS65219_INT_SENSOR_2_HOT = 35,\n\tTPS65219_INT_SENSOR_1_HOT = 36,\n\tTPS65219_INT_SENSOR_0_HOT = 37,\n\tTPS65219_INT_BUCK1_RV = 38,\n\tTPS65219_INT_BUCK2_RV = 39,\n\tTPS65219_INT_BUCK3_RV = 40,\n\tTPS65219_INT_LDO1_RV = 41,\n\tTPS65219_INT_LDO2_RV = 42,\n\tTPS65215_INT_LDO2_RV = 43,\n\tTPS65214_INT_LDO2_RV = 44,\n\tTPS65219_INT_LDO3_RV = 45,\n\tTPS65219_INT_LDO4_RV = 46,\n\tTPS65219_INT_BUCK1_RV_SD = 47,\n\tTPS65219_INT_BUCK2_RV_SD = 48,\n\tTPS65219_INT_BUCK3_RV_SD = 49,\n\tTPS65219_INT_LDO1_RV_SD = 50,\n\tTPS65214_INT_LDO1_RV_SD = 51,\n\tTPS65215_INT_LDO2_RV_SD = 52,\n\tTPS65219_INT_LDO2_RV_SD = 53,\n\tTPS65219_INT_LDO3_RV_SD = 54,\n\tTPS65219_INT_LDO4_RV_SD = 55,\n\tTPS65219_INT_TIMEOUT = 56,\n\tTPS65219_INT_PB_FALLING_EDGE_DETECT = 57,\n\tTPS65219_INT_PB_RISING_EDGE_DETECT = 58,\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_BAD_MAXACT_TYPE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_NON_UNIQ_SYMBOL = 10,\n\tTP_ERR_BAD_RETPROBE = 11,\n\tTP_ERR_NO_TRACEPOINT = 12,\n\tTP_ERR_BAD_TP_NAME = 13,\n\tTP_ERR_BAD_ADDR_SUFFIX = 14,\n\tTP_ERR_NO_GROUP_NAME = 15,\n\tTP_ERR_GROUP_TOO_LONG = 16,\n\tTP_ERR_BAD_GROUP_NAME = 17,\n\tTP_ERR_NO_EVENT_NAME = 18,\n\tTP_ERR_EVENT_TOO_LONG = 19,\n\tTP_ERR_BAD_EVENT_NAME = 20,\n\tTP_ERR_EVENT_EXIST = 21,\n\tTP_ERR_RETVAL_ON_PROBE = 22,\n\tTP_ERR_NO_RETVAL = 23,\n\tTP_ERR_BAD_STACK_NUM = 24,\n\tTP_ERR_BAD_ARG_NUM = 25,\n\tTP_ERR_BAD_VAR = 26,\n\tTP_ERR_BAD_REG_NAME = 27,\n\tTP_ERR_BAD_MEM_ADDR = 28,\n\tTP_ERR_BAD_IMM = 29,\n\tTP_ERR_IMMSTR_NO_CLOSE = 30,\n\tTP_ERR_FILE_ON_KPROBE = 31,\n\tTP_ERR_BAD_FILE_OFFS = 32,\n\tTP_ERR_SYM_ON_UPROBE = 33,\n\tTP_ERR_TOO_MANY_OPS = 34,\n\tTP_ERR_DEREF_NEED_BRACE = 35,\n\tTP_ERR_BAD_DEREF_OFFS = 36,\n\tTP_ERR_DEREF_OPEN_BRACE = 37,\n\tTP_ERR_COMM_CANT_DEREF = 38,\n\tTP_ERR_BAD_FETCH_ARG = 39,\n\tTP_ERR_ARRAY_NO_CLOSE = 40,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 41,\n\tTP_ERR_BAD_ARRAY_NUM = 42,\n\tTP_ERR_ARRAY_TOO_BIG = 43,\n\tTP_ERR_BAD_TYPE = 44,\n\tTP_ERR_BAD_STRING = 45,\n\tTP_ERR_BAD_SYMSTRING = 46,\n\tTP_ERR_BAD_BITFIELD = 47,\n\tTP_ERR_ARG_NAME_TOO_LONG = 48,\n\tTP_ERR_NO_ARG_NAME = 49,\n\tTP_ERR_BAD_ARG_NAME = 50,\n\tTP_ERR_USED_ARG_NAME = 51,\n\tTP_ERR_ARG_TOO_LONG = 52,\n\tTP_ERR_NO_ARG_BODY = 53,\n\tTP_ERR_BAD_INSN_BNDRY = 54,\n\tTP_ERR_FAIL_REG_PROBE = 55,\n\tTP_ERR_DIFF_PROBE_TYPE = 56,\n\tTP_ERR_DIFF_ARG_TYPE = 57,\n\tTP_ERR_SAME_PROBE = 58,\n\tTP_ERR_NO_EVENT_INFO = 59,\n\tTP_ERR_BAD_ATTACH_EVENT = 60,\n\tTP_ERR_BAD_ATTACH_ARG = 61,\n\tTP_ERR_NO_EP_FILTER = 62,\n\tTP_ERR_NOSUP_BTFARG = 63,\n\tTP_ERR_NO_BTFARG = 64,\n\tTP_ERR_NO_BTF_ENTRY = 65,\n\tTP_ERR_BAD_VAR_ARGS = 66,\n\tTP_ERR_NOFENTRY_ARGS = 67,\n\tTP_ERR_DOUBLE_ARGS = 68,\n\tTP_ERR_ARGS_2LONG = 69,\n\tTP_ERR_ARGIDX_2BIG = 70,\n\tTP_ERR_NO_PTR_STRCT = 71,\n\tTP_ERR_NOSUP_DAT_ARG = 72,\n\tTP_ERR_BAD_HYPHEN = 73,\n\tTP_ERR_NO_BTF_FIELD = 74,\n\tTP_ERR_BAD_BTF_TID = 75,\n\tTP_ERR_BAD_TYPE4STR = 76,\n\tTP_ERR_NEED_STRING_TYPE = 77,\n\tTP_ERR_TOO_MANY_ARGS = 78,\n\tTP_ERR_TOO_MANY_EARGS = 79,\n};\n\nenum {\n\tTRACEFS_EVENT_INODE = 2,\n\tTRACEFS_GID_PERM_SET = 4,\n\tTRACEFS_UID_PERM_SET = 8,\n\tTRACEFS_INSTANCE_INODE = 16,\n};\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n\tTRACE_ARRAY_FL_BOOT = 2,\n\tTRACE_ARRAY_FL_LAST_BOOT = 4,\n\tTRACE_ARRAY_FL_MOD_INIT = 8,\n\tTRACE_ARRAY_FL_MEMMAP = 16,\n\tTRACE_ARRAY_FL_VMALLOC = 32,\n};\n\nenum {\n\tTRACE_CTX_NMI = 0,\n\tTRACE_CTX_IRQ = 1,\n\tTRACE_CTX_SOFTIRQ = 2,\n\tTRACE_CTX_NORMAL = 3,\n\tTRACE_CTX_TRANSITION = 4,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 4,\n\tTRACE_EVENT_FL_TRACEPOINT = 8,\n\tTRACE_EVENT_FL_DYNAMIC = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n\tTRACE_EVENT_FL_EPROBE = 128,\n\tTRACE_EVENT_FL_FPROBE = 256,\n\tTRACE_EVENT_FL_CUSTOM = 512,\n\tTRACE_EVENT_FL_TEST_STR = 1024,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_FTRACE_BIT = 0,\n\tTRACE_FTRACE_NMI_BIT = 1,\n\tTRACE_FTRACE_IRQ_BIT = 2,\n\tTRACE_FTRACE_SIRQ_BIT = 3,\n\tTRACE_FTRACE_TRANSITION_BIT = 4,\n\tTRACE_INTERNAL_BIT = 5,\n\tTRACE_INTERNAL_NMI_BIT = 6,\n\tTRACE_INTERNAL_IRQ_BIT = 7,\n\tTRACE_INTERNAL_SIRQ_BIT = 8,\n\tTRACE_INTERNAL_TRANSITION_BIT = 9,\n\tTRACE_INTERNAL_EVENT_BIT = 10,\n\tTRACE_INTERNAL_EVENT_NMI_BIT = 11,\n\tTRACE_INTERNAL_EVENT_IRQ_BIT = 12,\n\tTRACE_INTERNAL_EVENT_SIRQ_BIT = 13,\n\tTRACE_INTERNAL_EVENT_TRANSITION_BIT = 14,\n\tTRACE_BRANCH_BIT = 15,\n\tTRACE_IRQ_BIT = 16,\n\tTRACE_RECORD_RECURSION_BIT = 17,\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tTRANS_MODE_PIO = 0,\n\tTRANS_MODE_IDMAC = 1,\n\tTRANS_MODE_EDMAC = 2,\n};\n\nenum {\n\tTRANS_TX_FAIL_BASE___2 = 0,\n\tTRANS_RX_FAIL_BASE___2 = 32,\n\tDMA_TX_ERR_BASE___2 = 64,\n\tSIPC_RX_ERR_BASE = 80,\n\tDMA_RX_ERR_BASE___2 = 96,\n\tTRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = 0,\n\tTRANS_TX_ERR_PHY_NOT_ENABLE = 1,\n\tTRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION = 2,\n\tTRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION = 3,\n\tTRANS_TX_OPEN_CNX_ERR_BY_OTHER = 4,\n\tRESERVED0 = 5,\n\tTRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT = 6,\n\tTRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY = 7,\n\tTRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED = 8,\n\tTRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED = 9,\n\tTRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION = 10,\n\tTRANS_TX_OPEN_CNX_ERR_BREAK_RCVD = 11,\n\tTRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER = 12,\n\tTRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED = 13,\n\tTRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT = 14,\n\tTRANS_TX_OPEN_CNX_ERR_NO_DESTINATION = 15,\n\tTRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED = 16,\n\tTRANS_TX_ERR_FRAME_TXED = 17,\n\tTRANS_TX_ERR_WITH_BREAK_TIMEOUT = 18,\n\tTRANS_TX_ERR_WITH_BREAK_REQUEST = 19,\n\tTRANS_TX_ERR_WITH_BREAK_RECEVIED = 20,\n\tTRANS_TX_ERR_WITH_CLOSE_TIMEOUT = 21,\n\tTRANS_TX_ERR_WITH_CLOSE_NORMAL = 22,\n\tTRANS_TX_ERR_WITH_CLOSE_PHYDISALE = 23,\n\tTRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT = 24,\n\tTRANS_TX_ERR_WITH_CLOSE_COMINIT = 25,\n\tTRANS_TX_ERR_WITH_NAK_RECEVIED = 26,\n\tTRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT = 27,\n\tTRANS_TX_ERR_WITH_CREDIT_TIMEOUT = 28,\n\tTRANS_TX_ERR_WITH_IPTT_CONFLICT = 29,\n\tTRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS = 30,\n\tTRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT = 31,\n\tTRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = 32,\n\tTRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR = 33,\n\tTRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM = 34,\n\tTRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR = 35,\n\tTRANS_RX_ERR_WITH_RXFIS_CRC_ERR = 36,\n\tTRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN = 37,\n\tTRANS_RX_ERR_WITH_RXFIS_RX_SYNCP = 38,\n\tTRANS_RX_ERR_WITH_LINK_BUF_OVERRUN = 39,\n\tTRANS_RX_ERR_WITH_BREAK_TIMEOUT = 40,\n\tTRANS_RX_ERR_WITH_BREAK_REQUEST = 41,\n\tTRANS_RX_ERR_WITH_BREAK_RECEVIED = 42,\n\tRESERVED1 = 43,\n\tTRANS_RX_ERR_WITH_CLOSE_NORMAL = 44,\n\tTRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE = 45,\n\tTRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT = 46,\n\tTRANS_RX_ERR_WITH_CLOSE_COMINIT = 47,\n\tTRANS_RX_ERR_WITH_DATA_LEN0 = 48,\n\tTRANS_RX_ERR_WITH_BAD_HASH = 49,\n\tTRANS_RX_XRDY_WLEN_ZERO_ERR = 50,\n\tTRANS_RX_SSP_FRM_LEN_ERR = 51,\n\tRESERVED2 = 52,\n\tRESERVED3 = 53,\n\tRESERVED4 = 54,\n\tRESERVED5 = 55,\n\tTRANS_RX_ERR_WITH_BAD_FRM_TYPE = 56,\n\tTRANS_RX_SMP_FRM_LEN_ERR = 57,\n\tTRANS_RX_SMP_RESP_TIMEOUT_ERR___2 = 58,\n\tRESERVED6 = 59,\n\tRESERVED7 = 60,\n\tRESERVED8 = 61,\n\tRESERVED9 = 62,\n\tTRANS_RX_R_ERR = 63,\n\tDMA_TX_DIF_CRC_ERR___2 = 64,\n\tDMA_TX_DIF_APP_ERR___2 = 65,\n\tDMA_TX_DIF_RPP_ERR___2 = 66,\n\tDMA_TX_DATA_SGL_OVERFLOW = 67,\n\tDMA_TX_DIF_SGL_OVERFLOW = 68,\n\tDMA_TX_UNEXP_XFER_ERR = 69,\n\tDMA_TX_UNEXP_RETRANS_ERR = 70,\n\tDMA_TX_XFER_LEN_OVERFLOW = 71,\n\tDMA_TX_XFER_OFFSET_ERR = 72,\n\tDMA_TX_RAM_ECC_ERR = 73,\n\tDMA_TX_DIF_LEN_ALIGN_ERR = 74,\n\tDMA_TX_MAX_ERR_CODE = 75,\n\tSIPC_RX_FIS_STATUS_ERR_BIT_VLD = 80,\n\tSIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR = 81,\n\tSIPC_RX_FIS_STATUS_BSY_BIT_ERR = 82,\n\tSIPC_RX_WRSETUP_LEN_ODD_ERR = 83,\n\tSIPC_RX_WRSETUP_LEN_ZERO_ERR = 84,\n\tSIPC_RX_WRDATA_LEN_NOT_MATCH_ERR = 85,\n\tSIPC_RX_NCQ_WRSETUP_OFFSET_ERR = 86,\n\tSIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR = 87,\n\tSIPC_RX_SATA_UNEXP_FIS_ERR = 88,\n\tSIPC_RX_WRSETUP_ESTATUS_ERR = 89,\n\tSIPC_RX_DATA_UNDERFLOW_ERR = 90,\n\tSIPC_RX_MAX_ERR_CODE = 91,\n\tDMA_RX_DIF_CRC_ERR___2 = 96,\n\tDMA_RX_DIF_APP_ERR___2 = 97,\n\tDMA_RX_DIF_RPP_ERR___2 = 98,\n\tDMA_RX_DATA_SGL_OVERFLOW = 99,\n\tDMA_RX_DIF_SGL_OVERFLOW = 100,\n\tDMA_RX_DATA_LEN_OVERFLOW = 101,\n\tDMA_RX_DATA_LEN_UNDERFLOW = 102,\n\tDMA_RX_DATA_OFFSET_ERR___2 = 103,\n\tRESERVED10 = 104,\n\tDMA_RX_SATA_FRAME_TYPE_ERR = 105,\n\tDMA_RX_RESP_BUF_OVERFLOW = 106,\n\tDMA_RX_UNEXP_RETRANS_RESP_ERR___2 = 107,\n\tDMA_RX_UNEXP_NORM_RESP_ERR = 108,\n\tDMA_RX_UNEXP_RDFRAME_ERR = 109,\n\tDMA_RX_PIO_DATA_LEN_ERR = 110,\n\tDMA_RX_RDSETUP_STATUS_ERR = 111,\n\tDMA_RX_RDSETUP_STATUS_DRQ_ERR = 112,\n\tDMA_RX_RDSETUP_STATUS_BSY_ERR = 113,\n\tDMA_RX_RDSETUP_LEN_ODD_ERR = 114,\n\tDMA_RX_RDSETUP_LEN_ZERO_ERR = 115,\n\tDMA_RX_RDSETUP_LEN_OVER_ERR = 116,\n\tDMA_RX_RDSETUP_OFFSET_ERR = 117,\n\tDMA_RX_RDSETUP_ACTIVE_ERR = 118,\n\tDMA_RX_RDSETUP_ESTATUS_ERR = 119,\n\tDMA_RX_RAM_ECC_ERR = 120,\n\tDMA_RX_UNKNOWN_FRM_ERR = 121,\n\tDMA_RX_MAX_ERR_CODE = 122,\n};\n\nenum {\n\tTST_FRC_DPERR_MR = 128,\n\tTST_FRC_DPERR_MW = 64,\n\tTST_FRC_DPERR_TR = 32,\n\tTST_FRC_DPERR_TW = 16,\n\tTST_FRC_APERR_M = 8,\n\tTST_FRC_APERR_T = 4,\n\tTST_CFG_WRITE_ON = 2,\n\tTST_CFG_WRITE_OFF = 1,\n};\n\nenum {\n\tTXA_ENA_FSYNC = 128,\n\tTXA_DIS_FSYNC = 64,\n\tTXA_ENA_ALLOC = 32,\n\tTXA_DIS_ALLOC = 16,\n\tTXA_START_RC = 8,\n\tTXA_STOP_RC = 4,\n\tTXA_ENA_ARB = 2,\n\tTXA_DIS_ARB = 1,\n};\n\nenum {\n\tTXA_ITI_INI = 512,\n\tTXA_ITI_VAL = 516,\n\tTXA_LIM_INI = 520,\n\tTXA_LIM_VAL = 524,\n\tTXA_CTRL = 528,\n\tTXA_TEST = 529,\n\tTXA_STAT = 530,\n\tRSS_KEY = 544,\n\tRSS_CFG = 584,\n};\n\nenum {\n\tTX_DYN_WM_ENA = 3,\n};\n\nenum {\n\tTX_GMF_EA = 3392,\n\tTX_GMF_AE_THR = 3396,\n\tTX_GMF_CTRL_T = 3400,\n\tTX_GMF_WP = 3424,\n\tTX_GMF_WSP = 3428,\n\tTX_GMF_WLEV = 3432,\n\tTX_GMF_RP = 3440,\n\tTX_GMF_RSTP = 3444,\n\tTX_GMF_RLEV = 3448,\n\tECU_AE_THR = 112,\n\tECU_TXFF_LEV = 416,\n\tECU_JUMBO_WM = 128,\n};\n\nenum {\n\tTX_STFW_DIS = -2147483648,\n\tTX_STFW_ENA = 1073741824,\n\tTX_VLAN_TAG_ON = 33554432,\n\tTX_VLAN_TAG_OFF = 16777216,\n\tTX_PCI_JUM_ENA = 8388608,\n\tTX_PCI_JUM_DIS = 4194304,\n\tGMF_WSP_TST_ON = 262144,\n\tGMF_WSP_TST_OFF = 131072,\n\tGMF_WSP_STEP = 65536,\n\tGMF_CLI_TX_FU = 64,\n\tGMF_CLI_TX_FC = 32,\n\tGMF_CLI_TX_PE = 16,\n};\n\nenum {\n\tTX_SYMBOL_CLK_REQ_FORCE = 5,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUARTDM_1P1 = 1,\n\tUARTDM_1P2 = 2,\n\tUARTDM_1P3 = 3,\n\tUARTDM_1P4 = 4,\n};\n\nenum {\n\tUART_IRQ_SUM = 0,\n\tUART_RX_IRQ = 0,\n\tUART_TX_IRQ = 1,\n\tUART_IRQ_COUNT = 2,\n};\n\nenum {\n\tUDPTCP = 1,\n\tCALSUM = 2,\n\tWR_SUM = 4,\n\tINIT_SUM = 8,\n\tLOCK_SUM = 16,\n\tINS_VLAN = 32,\n\tEOP = 128,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUFSHCD_EH_IN_PROGRESS = 1,\n};\n\nenum {\n\tUFSHCD_MAX_CHANNEL = 0,\n\tUFSHCD_MAX_ID = 1,\n};\n\nenum {\n\tUFSHCD_NANO_AMP = 0,\n\tUFSHCD_MICRO_AMP = 1,\n\tUFSHCD_MILI_AMP = 2,\n\tUFSHCD_AMP = 3,\n};\n\nenum {\n\tUFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1,\n};\n\nenum {\n\tUFSHCD_UIC_DL_PA_INIT_ERROR = 1,\n\tUFSHCD_UIC_DL_NAC_RECEIVED_ERROR = 2,\n\tUFSHCD_UIC_DL_TCx_REPLAY_ERROR = 4,\n\tUFSHCD_UIC_NL_ERROR = 8,\n\tUFSHCD_UIC_TL_ERROR = 16,\n\tUFSHCD_UIC_DME_ERROR = 32,\n\tUFSHCD_UIC_PA_GENERIC_ERROR = 64,\n};\n\nenum {\n\tUFS_ABORT_TASK = 1,\n\tUFS_ABORT_TASK_SET = 2,\n\tUFS_CLEAR_TASK_SET = 4,\n\tUFS_LOGICAL_RESET = 8,\n\tUFS_QUERY_TASK = 128,\n\tUFS_QUERY_TASK_SET = 129,\n};\n\nenum {\n\tUFS_DEV_HIGH_TEMP_NOTIF = 16,\n\tUFS_DEV_LOW_TEMP_NOTIF = 32,\n\tUFS_DEV_EXT_TEMP_NOTIF = 64,\n\tUFS_DEV_HPB_SUPPORT = 128,\n\tUFS_DEV_WRITE_BOOSTER_SUP = 256,\n\tUFS_DEV_LVL_EXCEPTION_SUP = 4096,\n\tUFS_DEV_HID_SUPPORT = 8192,\n};\n\nenum {\n\tUFS_DEV_WB_BUF_RESIZE = 1,\n};\n\nenum {\n\tUFS_REG_OCPTHRTL = 192,\n\tUFS_REG_OOCPR = 196,\n\tUFS_REG_CDACFG = 208,\n\tUFS_REG_CDATX1 = 212,\n\tUFS_REG_CDATX2 = 216,\n\tUFS_REG_CDARX1 = 220,\n\tUFS_REG_CDARX2 = 224,\n\tUFS_REG_CDASTA = 228,\n\tUFS_REG_LBMCFG = 240,\n\tUFS_REG_LBMSTA = 244,\n\tUFS_REG_UFSMODE = 248,\n\tUFS_REG_HCLKDIV = 252,\n};\n\nenum {\n\tUFS_UPIU_REPORT_LUNS_WLUN = 129,\n\tUFS_UPIU_UFS_DEVICE_WLUN = 208,\n\tUFS_UPIU_BOOT_WLUN = 176,\n\tUFS_UPIU_RPMB_WLUN = 196,\n};\n\nenum {\n\tUIC_CMD_TIMEOUT_DEFAULT = 500,\n\tUIC_CMD_TIMEOUT_MAX = 5000,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNIPRO_L1_5 = 0,\n\tUNIPRO_L2 = 1,\n\tUNIPRO_L3 = 2,\n\tUNIPRO_L4 = 3,\n\tUNIPRO_DME = 4,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tUPIU_CMD_FLAGS_NONE = 0,\n\tUPIU_CMD_FLAGS_CP = 4,\n\tUPIU_CMD_FLAGS_WRITE = 32,\n\tUPIU_CMD_FLAGS_READ = 64,\n};\n\nenum {\n\tUPIU_COMMAND_SET_TYPE_SCSI = 0,\n\tUPIU_COMMAND_SET_TYPE_UFS = 1,\n\tUPIU_COMMAND_SET_TYPE_QUERY = 2,\n};\n\nenum {\n\tUPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 1,\n\tUPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 129,\n};\n\nenum {\n\tUPIU_RSP_FLAG_UNDERFLOW = 32,\n\tUPIU_RSP_FLAG_OVERFLOW = 64,\n};\n\nenum {\n\tUPIU_TASK_MANAGEMENT_FUNC_COMPL = 0,\n\tUPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 4,\n\tUPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 8,\n\tUPIU_TASK_MANAGEMENT_FUNC_FAILED = 5,\n\tUPIU_INCORRECT_LOGICAL_UNIT_NO = 9,\n};\n\nenum {\n\tUSB_CTRL_SETUP_SCB1_EN_SELECTOR = 0,\n\tUSB_CTRL_SETUP_SCB2_EN_SELECTOR = 1,\n\tUSB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR = 2,\n\tUSB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR = 3,\n\tUSB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR = 4,\n\tUSB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR = 5,\n\tUSB_CTRL_SETUP_OC3_DISABLE_SELECTOR = 6,\n\tUSB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR = 7,\n\tUSB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR = 8,\n\tUSB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR = 9,\n\tUSB_CTRL_USB_PM_USB_PWRDN_SELECTOR = 10,\n\tUSB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR = 11,\n\tUSB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR = 12,\n\tUSB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR = 13,\n\tUSB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR = 14,\n\tUSB_CTRL_USB_PM_SOFT_RESET_SELECTOR = 15,\n\tUSB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR = 16,\n\tUSB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR = 17,\n\tUSB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR = 18,\n\tUSB_CTRL_SETUP_ENDIAN_SELECTOR = 19,\n\tUSB_CTRL_SELECTOR_COUNT = 20,\n};\n\nenum {\n\tUS_FL_SINGLE_LUN = 1,\n\tUS_FL_NEED_OVERRIDE = 2,\n\tUS_FL_SCM_MULT_TARG = 4,\n\tUS_FL_FIX_INQUIRY = 8,\n\tUS_FL_FIX_CAPACITY = 16,\n\tUS_FL_IGNORE_RESIDUE = 32,\n\tUS_FL_BULK32 = 64,\n\tUS_FL_NOT_LOCKABLE = 128,\n\tUS_FL_GO_SLOW = 256,\n\tUS_FL_NO_WP_DETECT = 512,\n\tUS_FL_MAX_SECTORS_64 = 1024,\n\tUS_FL_IGNORE_DEVICE = 2048,\n\tUS_FL_CAPACITY_HEURISTICS = 4096,\n\tUS_FL_MAX_SECTORS_MIN = 8192,\n\tUS_FL_BULK_IGNORE_TAG = 16384,\n\tUS_FL_SANE_SENSE = 32768,\n\tUS_FL_CAPACITY_OK = 65536,\n\tUS_FL_BAD_SENSE = 131072,\n\tUS_FL_NO_READ_DISC_INFO = 262144,\n\tUS_FL_NO_READ_CAPACITY_16 = 524288,\n\tUS_FL_INITIAL_READ10 = 1048576,\n\tUS_FL_WRITE_CACHE = 2097152,\n\tUS_FL_NEEDS_CAP16 = 4194304,\n\tUS_FL_IGNORE_UAS = 8388608,\n\tUS_FL_BROKEN_FUA = 16777216,\n\tUS_FL_NO_ATA_1X = 33554432,\n\tUS_FL_NO_REPORT_OPCODES = 67108864,\n\tUS_FL_MAX_SECTORS_240 = 134217728,\n\tUS_FL_NO_REPORT_LUNS = 268435456,\n\tUS_FL_ALWAYS_SYNC = 536870912,\n\tUS_FL_NO_SAME = 1073741824,\n\tUS_FL_SENSE_AFTER_SYNC = 2147483648,\n};\n\nenum {\n\tUTP_CMD_TYPE_UFS_STORAGE = 1,\n};\n\nenum {\n\tVFIO_DEVICE_NUM_STATES = 8,\n};\n\nenum {\n\tVFIO_PCI_BAR0_REGION_INDEX = 0,\n\tVFIO_PCI_BAR1_REGION_INDEX = 1,\n\tVFIO_PCI_BAR2_REGION_INDEX = 2,\n\tVFIO_PCI_BAR3_REGION_INDEX = 3,\n\tVFIO_PCI_BAR4_REGION_INDEX = 4,\n\tVFIO_PCI_BAR5_REGION_INDEX = 5,\n\tVFIO_PCI_ROM_REGION_INDEX = 6,\n\tVFIO_PCI_CONFIG_REGION_INDEX = 7,\n\tVFIO_PCI_VGA_REGION_INDEX = 8,\n\tVFIO_PCI_NUM_REGIONS = 9,\n};\n\nenum {\n\tVFIO_PCI_INTX_IRQ_INDEX = 0,\n\tVFIO_PCI_MSI_IRQ_INDEX = 1,\n\tVFIO_PCI_MSIX_IRQ_INDEX = 2,\n\tVFIO_PCI_ERR_IRQ_INDEX = 3,\n\tVFIO_PCI_REQ_IRQ_INDEX = 4,\n\tVFIO_PCI_NUM_IRQS = 5,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SHADOW_STACK_BIT = 38,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tVP_MSIX_CONFIG_VECTOR = 0,\n\tVP_MSIX_VQ_VECTOR = 1,\n};\n\nenum {\n\tVS_HCE_RESET = 0,\n\tVS_HCE_BASE = 1,\n\tVS_HCE_OOCPR_WAIT = 2,\n\tVS_HCE_DME_RESET = 3,\n\tVS_HCE_MIDDLE = 4,\n\tVS_HCE_DME_ENABLE = 5,\n\tVS_HCE_DEFAULTS = 6,\n\tVS_HIB_IDLEEN = 7,\n\tVS_HIB_ENTER = 8,\n\tVS_HIB_ENTER_CONF = 9,\n\tVS_HIB_MIDDLE = 10,\n\tVS_HIB_WAITTIMER = 11,\n\tVS_HIB_EXIT_CONF = 12,\n\tVS_HIB_EXIT = 13,\n};\n\nenum {\n\tVS_LINK_DISABLED = 0,\n\tVS_LINK_DOWN = 1,\n\tVS_LINK_UP = 2,\n\tVS_LINK_HIBERN8 = 3,\n\tVS_LINK_LOST = 4,\n\tVS_LINK_CFG = 5,\n};\n\nenum {\n\tV_ARMADA_7K = 1,\n\tV_ARMADA_8K_CPM = 2,\n\tV_ARMADA_8K_CPS = 4,\n\tV_CP115_STANDALONE = 8,\n\tV_ARMADA_7K_8K_CPM = 3,\n\tV_ARMADA_7K_8K_CPS = 5,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tWB_BUF_MODE_LU_DEDICATED = 0,\n\tWB_BUF_MODE_SHARED = 1,\n};\n\nenum {\n\tWEST___4 = 0,\n\tSOUTH___6 = 1,\n\tNORTH___5 = 2,\n};\n\nenum {\n\tWOL_CTL_LINK_CHG_OCC = 32768,\n\tWOL_CTL_MAGIC_PKT_OCC = 16384,\n\tWOL_CTL_PATTERN_OCC = 8192,\n\tWOL_CTL_CLEAR_RESULT = 4096,\n\tWOL_CTL_ENA_PME_ON_LINK_CHG = 2048,\n\tWOL_CTL_DIS_PME_ON_LINK_CHG = 1024,\n\tWOL_CTL_ENA_PME_ON_MAGIC_PKT = 512,\n\tWOL_CTL_DIS_PME_ON_MAGIC_PKT = 256,\n\tWOL_CTL_ENA_PME_ON_PATTERN = 128,\n\tWOL_CTL_DIS_PME_ON_PATTERN = 64,\n\tWOL_CTL_ENA_LINK_CHG_UNIT = 32,\n\tWOL_CTL_DIS_LINK_CHG_UNIT = 16,\n\tWOL_CTL_ENA_MAGIC_PKT_UNIT = 8,\n\tWOL_CTL_DIS_MAGIC_PKT_UNIT = 4,\n\tWOL_CTL_ENA_PATTERN_UNIT = 2,\n\tWOL_CTL_DIS_PATTERN_UNIT = 1,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tXPT_BUSY = 0,\n\tXPT_CONN = 1,\n\tXPT_CLOSE = 2,\n\tXPT_DATA = 3,\n\tXPT_TEMP = 4,\n\tXPT_DEAD = 5,\n\tXPT_CHNGBUF = 6,\n\tXPT_DEFERRED = 7,\n\tXPT_OLD = 8,\n\tXPT_LISTENER = 9,\n\tXPT_CACHE_AUTH = 10,\n\tXPT_LOCAL = 11,\n\tXPT_KILL_TEMP = 12,\n\tXPT_CONG_CTRL = 13,\n\tXPT_HANDSHAKE = 14,\n\tXPT_TLS_SESSION = 15,\n\tXPT_PEER_AUTH = 16,\n\tXPT_PEER_VALID = 17,\n\tXPT_RPCB_UNREG = 18,\n};\n\nenum {\n\tY2_ASF_OS_PRES = 16,\n\tY2_ASF_RESET = 8,\n\tY2_ASF_RUNNING = 4,\n\tY2_ASF_CLR_HSTI = 2,\n\tY2_ASF_IRQ = 1,\n\tY2_ASF_UC_STATE = 12,\n\tY2_ASF_CLK_HALT = 0,\n};\n\nenum {\n\tY2_B8_PREF_REGS = 1104,\n\tPREF_UNIT_CTRL = 0,\n\tPREF_UNIT_LAST_IDX = 4,\n\tPREF_UNIT_ADDR_LO = 8,\n\tPREF_UNIT_ADDR_HI = 12,\n\tPREF_UNIT_GET_IDX = 16,\n\tPREF_UNIT_PUT_IDX = 20,\n\tPREF_UNIT_FIFO_WP = 32,\n\tPREF_UNIT_FIFO_RP = 36,\n\tPREF_UNIT_FIFO_WM = 40,\n\tPREF_UNIT_FIFO_LEV = 44,\n\tPREF_UNIT_MASK_IDX = 4095,\n};\n\nenum {\n\tY2_CLK_DIV_VAL_MSK = 16711680,\n\tY2_CLK_DIV_VAL2_MSK = 14680064,\n\tY2_CLK_SELECT2_MSK = 2031616,\n\tY2_CLK_DIV_ENA = 2,\n\tY2_CLK_DIV_DIS = 1,\n};\n\nenum {\n\tY2_IS_HW_ERR = -2147483648,\n\tY2_IS_STAT_BMU = 1073741824,\n\tY2_IS_ASF = 536870912,\n\tY2_IS_CPU_TO = 268435456,\n\tY2_IS_POLL_CHK = 134217728,\n\tY2_IS_TWSI_RDY = 67108864,\n\tY2_IS_IRQ_SW = 33554432,\n\tY2_IS_TIMINT = 16777216,\n\tY2_IS_IRQ_PHY2 = 4096,\n\tY2_IS_IRQ_MAC2 = 2048,\n\tY2_IS_CHK_RX2 = 1024,\n\tY2_IS_CHK_TXS2 = 512,\n\tY2_IS_CHK_TXA2 = 256,\n\tY2_IS_PSM_ACK = 128,\n\tY2_IS_PTP_TIST = 64,\n\tY2_IS_PHY_QLNK = 32,\n\tY2_IS_IRQ_PHY1 = 16,\n\tY2_IS_IRQ_MAC1 = 8,\n\tY2_IS_CHK_RX1 = 4,\n\tY2_IS_CHK_TXS1 = 2,\n\tY2_IS_CHK_TXA1 = 1,\n\tY2_IS_BASE = -1073741824,\n\tY2_IS_PORT_1 = 29,\n\tY2_IS_PORT_2 = 7424,\n\tY2_IS_ERROR = -2147480307,\n};\n\nenum {\n\tY2_IS_TIST_OV = 536870912,\n\tY2_IS_SENSOR = 268435456,\n\tY2_IS_MST_ERR = 134217728,\n\tY2_IS_IRQ_STAT = 67108864,\n\tY2_IS_PCI_EXP = 33554432,\n\tY2_IS_PCI_NEXP = 16777216,\n\tY2_IS_PAR_RD2 = 8192,\n\tY2_IS_PAR_WR2 = 4096,\n\tY2_IS_PAR_MAC2 = 2048,\n\tY2_IS_PAR_RX2 = 1024,\n\tY2_IS_TCP_TXS2 = 512,\n\tY2_IS_TCP_TXA2 = 256,\n\tY2_IS_PAR_RD1 = 32,\n\tY2_IS_PAR_WR1 = 16,\n\tY2_IS_PAR_MAC1 = 8,\n\tY2_IS_PAR_RX1 = 4,\n\tY2_IS_TCP_TXS1 = 2,\n\tY2_IS_TCP_TXA1 = 1,\n\tY2_HWE_L1_MASK = 63,\n\tY2_HWE_L2_MASK = 16128,\n\tY2_HWE_ALL_MASK = 738213695,\n};\n\nenum {\n\tY2_STATUS_LNK2_INAC = 128,\n\tY2_CLK_GAT_LNK2_DIS = 64,\n\tY2_COR_CLK_LNK2_DIS = 32,\n\tY2_PCI_CLK_LNK2_DIS = 16,\n\tY2_STATUS_LNK1_INAC = 8,\n\tY2_CLK_GAT_LNK1_DIS = 4,\n\tY2_COR_CLK_LNK1_DIS = 2,\n\tY2_PCI_CLK_LNK1_DIS = 1,\n};\n\nenum {\n\tY2_VMAIN_AVAIL = 131072,\n\tY2_VAUX_AVAIL = 65536,\n\tY2_HW_WOL_ON = 32768,\n\tY2_HW_WOL_OFF = 16384,\n\tY2_ASF_ENABLE = 8192,\n\tY2_ASF_DISABLE = 4096,\n\tY2_CLK_RUN_ENA = 2048,\n\tY2_CLK_RUN_DIS = 1024,\n\tY2_LED_STAT_ON = 512,\n\tY2_LED_STAT_OFF = 256,\n\tCS_ST_SW_IRQ = 128,\n\tCS_CL_SW_IRQ = 64,\n\tCS_STOP_DONE = 32,\n\tCS_STOP_MAST = 16,\n\tCS_MRST_CLR = 8,\n\tCS_MRST_SET = 4,\n\tCS_RST_CLR = 2,\n\tCS_RST_SET = 1,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tZONELIST_NOFALLBACK = 1,\n\tMAX_ZONELISTS = 2,\n};\n\nenum {\n\t_DQUOT_USAGE_ENABLED = 0,\n\t_DQUOT_LIMITS_ENABLED = 1,\n\t_DQUOT_SUSPENDED = 2,\n\t_DQUOT_STATE_FLAGS = 3,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 0,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t__MVNETA_DOWN = 0,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 10,\n\t__SCHED_FEAT_HRTICK = 11,\n\t__SCHED_FEAT_HRTICK_DL = 12,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 13,\n\t__SCHED_FEAT_TTWU_QUEUE = 14,\n\t__SCHED_FEAT_SIS_UTIL = 15,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 16,\n\t__SCHED_FEAT_RT_PUSH_IPI = 17,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 18,\n\t__SCHED_FEAT_LB_MIN = 19,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 20,\n\t__SCHED_FEAT_WA_IDLE = 21,\n\t__SCHED_FEAT_WA_WEIGHT = 22,\n\t__SCHED_FEAT_WA_BIAS = 23,\n\t__SCHED_FEAT_UTIL_EST = 24,\n\t__SCHED_FEAT_LATENCY_WARN = 25,\n\t__SCHED_FEAT_NI_RANDOM = 26,\n\t__SCHED_FEAT_NR = 27,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NO_OBJ_EXT_BIT = 24,\n\t___GFP_LAST_BIT = 25,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SKB = 4,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK = 5,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 7,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 8,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 9,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 10,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 11,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 12,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 13,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 14,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 15,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 16,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 17,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 18,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 19,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 20,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_DEVICE = 21,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SYSCTL = 22,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCKOPT = 23,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 24,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 25,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 26,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 27,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 28,\n\t__ctx_convertBPF_PROG_TYPE_NETFILTER = 29,\n\t__ctx_convert_unused = 30,\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_sra_exceeded_retry_limit = 5,\n\tattr_inode_readahead = 6,\n\tattr_trigger_test_error = 7,\n\tattr_first_error_time = 8,\n\tattr_last_error_time = 9,\n\tattr_clusters_in_group = 10,\n\tattr_mb_order = 11,\n\tattr_feature = 12,\n\tattr_pointer_pi = 13,\n\tattr_pointer_ui = 14,\n\tattr_pointer_ul = 15,\n\tattr_pointer_u64 = 16,\n\tattr_pointer_u8 = 17,\n\tattr_pointer_string = 18,\n\tattr_pointer_atomic = 19,\n\tattr_journal_task = 20,\n\tattr_err_report_sec = 21,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\te1000_10_half = 0,\n\te1000_10_full = 1,\n\te1000_100_half = 2,\n\te1000_100_full = 3,\n};\n\nenum {\n\te1000_igp_cable_length_10 = 10,\n\te1000_igp_cable_length_20 = 20,\n\te1000_igp_cable_length_30 = 30,\n\te1000_igp_cable_length_40 = 40,\n\te1000_igp_cable_length_50 = 50,\n\te1000_igp_cable_length_60 = 60,\n\te1000_igp_cable_length_70 = 70,\n\te1000_igp_cable_length_80 = 80,\n\te1000_igp_cable_length_90 = 90,\n\te1000_igp_cable_length_100 = 100,\n\te1000_igp_cable_length_110 = 110,\n\te1000_igp_cable_length_115 = 115,\n\te1000_igp_cable_length_120 = 120,\n\te1000_igp_cable_length_130 = 130,\n\te1000_igp_cable_length_140 = 140,\n\te1000_igp_cable_length_150 = 150,\n\te1000_igp_cable_length_160 = 160,\n\te1000_igp_cable_length_170 = 170,\n\te1000_igp_cable_length_180 = 180,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\thip08 = 0,\n};\n\nenum {\n\tkvm_ioeventfd_flag_nr_datamatch = 0,\n\tkvm_ioeventfd_flag_nr_pio = 1,\n\tkvm_ioeventfd_flag_nr_deassign = 2,\n\tkvm_ioeventfd_flag_nr_virtio_ccw_notify = 3,\n\tkvm_ioeventfd_flag_nr_fast_mmio = 4,\n\tkvm_ioeventfd_flag_nr_max = 5,\n};\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\nenum {\n\tvfio_noiommu = 0,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tEfiPciIoWidthUint8 = 0,\n\tEfiPciIoWidthUint16 = 1,\n\tEfiPciIoWidthUint32 = 2,\n\tEfiPciIoWidthUint64 = 3,\n\tEfiPciIoWidthFifoUint8 = 4,\n\tEfiPciIoWidthFifoUint16 = 5,\n\tEfiPciIoWidthFifoUint32 = 6,\n\tEfiPciIoWidthFifoUint64 = 7,\n\tEfiPciIoWidthFillUint8 = 8,\n\tEfiPciIoWidthFillUint16 = 9,\n\tEfiPciIoWidthFillUint32 = 10,\n\tEfiPciIoWidthFillUint64 = 11,\n\tEfiPciIoWidthMaximum = 12,\n} EFI_PCI_IO_PROTOCOL_WIDTH;\n\ntypedef enum {\n\tEfiTimerCancel = 0,\n\tEfiTimerPeriodic = 1,\n\tEfiTimerRelative = 2,\n} EFI_TIMER_DELAY;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tOSL_GLOBAL_LOCK_HANDLER = 0,\n\tOSL_NOTIFY_HANDLER = 1,\n\tOSL_GPE_HANDLER = 2,\n\tOSL_DEBUGGER_MAIN_THREAD = 3,\n\tOSL_DEBUGGER_EXEC_THREAD = 4,\n\tOSL_EC_POLL_HANDLER = 5,\n\tOSL_EC_BURST_HANDLER = 6,\n} acpi_execute_type;\n\ntypedef enum {\n\tACPI_IMODE_LOAD_PASS1 = 1,\n\tACPI_IMODE_LOAD_PASS2 = 2,\n\tACPI_IMODE_EXECUTE = 3,\n} acpi_interpreter_mode;\n\ntypedef enum {\n\tACPI_TRACE_AML_METHOD = 0,\n\tACPI_TRACE_AML_OPCODE = 1,\n\tACPI_TRACE_AML_REGION = 2,\n} acpi_trace_event_type;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tneed_more = 0,\n\tblock_done = 1,\n\tfinish_started = 2,\n\tfinish_done = 3,\n} block_state;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\ntypedef enum {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok = 1,\n\te1000_1000t_rx_status_undefined = 255,\n} e1000_1000t_rx_status;\n\ntypedef enum {\n\te1000_10bt_ext_dist_enable_normal = 0,\n\te1000_10bt_ext_dist_enable_lower = 1,\n\te1000_10bt_ext_dist_enable_undefined = 255,\n} e1000_10bt_ext_dist_enable;\n\ntypedef enum {\n\te1000_auto_x_mode_manual_mdi = 0,\n\te1000_auto_x_mode_manual_mdix = 1,\n\te1000_auto_x_mode_auto1 = 2,\n\te1000_auto_x_mode_auto2 = 3,\n\te1000_auto_x_mode_undefined = 255,\n} e1000_auto_x_mode;\n\ntypedef enum {\n\te1000_bus_speed_unknown = 0,\n\te1000_bus_speed_33 = 1,\n\te1000_bus_speed_66 = 2,\n\te1000_bus_speed_100 = 3,\n\te1000_bus_speed_120 = 4,\n\te1000_bus_speed_133 = 5,\n\te1000_bus_speed_reserved = 6,\n} e1000_bus_speed;\n\ntypedef enum {\n\te1000_bus_type_unknown = 0,\n\te1000_bus_type_pci = 1,\n\te1000_bus_type_pcix = 2,\n\te1000_bus_type_reserved = 3,\n} e1000_bus_type;\n\ntypedef enum {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_32 = 1,\n\te1000_bus_width_64 = 2,\n\te1000_bus_width_reserved = 3,\n} e1000_bus_width;\n\ntypedef enum {\n\te1000_cable_length_50 = 0,\n\te1000_cable_length_50_80 = 1,\n\te1000_cable_length_80_110 = 2,\n\te1000_cable_length_110_140 = 3,\n\te1000_cable_length_140 = 4,\n\te1000_cable_length_undefined = 255,\n} e1000_cable_length;\n\ntypedef enum {\n\te1000_downshift_normal = 0,\n\te1000_downshift_activated = 1,\n\te1000_downshift_undefined = 255,\n} e1000_downshift;\n\ntypedef enum {\n\te1000_dsp_config_disabled = 0,\n\te1000_dsp_config_enabled = 1,\n\te1000_dsp_config_activated = 2,\n\te1000_dsp_config_undefined = 255,\n} e1000_dsp_config;\n\ntypedef enum {\n\te1000_eeprom_uninitialized = 0,\n\te1000_eeprom_spi = 1,\n\te1000_eeprom_microwire = 2,\n\te1000_eeprom_flash = 3,\n\te1000_eeprom_none = 4,\n\te1000_num_eeprom_types = 5,\n} e1000_eeprom_type;\n\ntypedef enum {\n\tE1000_FC_NONE = 0,\n\tE1000_FC_RX_PAUSE = 1,\n\tE1000_FC_TX_PAUSE = 2,\n\tE1000_FC_FULL = 3,\n\tE1000_FC_DEFAULT = 255,\n} e1000_fc_type;\n\ntypedef enum {\n\te1000_ffe_config_enabled = 0,\n\te1000_ffe_config_active = 1,\n\te1000_ffe_config_blocked = 2,\n} e1000_ffe_config;\n\ntypedef enum {\n\te1000_undefined = 0,\n\te1000_82542_rev2_0 = 1,\n\te1000_82542_rev2_1 = 2,\n\te1000_82543 = 3,\n\te1000_82544 = 4,\n\te1000_82540 = 5,\n\te1000_82545 = 6,\n\te1000_82545_rev_3 = 7,\n\te1000_82546 = 8,\n\te1000_ce4100 = 9,\n\te1000_82546_rev_3 = 10,\n\te1000_82541 = 11,\n\te1000_82541_rev_2 = 12,\n\te1000_82547 = 13,\n\te1000_82547_rev_2 = 14,\n\te1000_num_macs = 15,\n} e1000_mac_type;\n\ntypedef enum {\n\te1000_media_type_copper = 0,\n\te1000_media_type_fiber = 1,\n\te1000_media_type_internal_serdes = 2,\n\te1000_num_media_types = 3,\n} e1000_media_type;\n\ntypedef enum {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master = 1,\n\te1000_ms_force_slave = 2,\n\te1000_ms_auto = 3,\n} e1000_ms_type;\n\ntypedef enum {\n\te1000_phy_m88 = 0,\n\te1000_phy_igp = 1,\n\te1000_phy_8211 = 2,\n\te1000_phy_8201 = 3,\n\te1000_phy_undefined = 255,\n} e1000_phy_type;\n\ntypedef enum {\n\te1000_polarity_reversal_enabled = 0,\n\te1000_polarity_reversal_disabled = 1,\n\te1000_polarity_reversal_undefined = 255,\n} e1000_polarity_reversal;\n\ntypedef enum {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed = 1,\n\te1000_rev_polarity_undefined = 255,\n} e1000_rev_polarity;\n\ntypedef enum {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on = 1,\n\te1000_smart_speed_off = 2,\n} e1000_smart_speed;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n\tEXT4_IGET_BAD = 4,\n\tEXT4_IGET_EA_INODE = 8,\n} ext4_iget_flags;\n\ntypedef enum {\n\tFL_READY = 0,\n\tFL_STATUS = 1,\n\tFL_CFI_QUERY = 2,\n\tFL_JEDEC_QUERY = 3,\n\tFL_ERASING = 4,\n\tFL_ERASE_SUSPENDING = 5,\n\tFL_ERASE_SUSPENDED = 6,\n\tFL_WRITING = 7,\n\tFL_WRITING_TO_BUFFER = 8,\n\tFL_OTP_WRITE = 9,\n\tFL_WRITE_SUSPENDING = 10,\n\tFL_WRITE_SUSPENDED = 11,\n\tFL_PM_SUSPENDED = 12,\n\tFL_SYNCING = 13,\n\tFL_UNLOADING = 14,\n\tFL_LOCKING = 15,\n\tFL_UNLOCKING = 16,\n\tFL_POINT = 17,\n\tFL_XIP_WHILE_ERASING = 18,\n\tFL_XIP_WHILE_WRITING = 19,\n\tFL_SHUTDOWN = 20,\n\tFL_READING = 21,\n\tFL_CACHEDPRG = 22,\n\tFL_RESETTING = 23,\n\tFL_OTPING = 24,\n\tFL_PREPARING_ERASE = 25,\n\tFL_VERIFYING_ERASE = 26,\n\tFL_UNKNOWN = 27,\n} flstate_t;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tMAP_CHG_REUSE = 0,\n\tMAP_CHG_NEEDED = 1,\n\tMAP_CHG_ENFORCED = 2,\n} map_chg_state;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPCI_BRIDGE_EMUL_HANDLED = 0,\n\tPCI_BRIDGE_EMUL_NOT_HANDLED = 1,\n} pci_bridge_emul_read_status_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum APSR_BIT {\n\tAPSR_MEMS = 2,\n\tAPSR_CMSW = 16,\n\tAPSR_RDM = 8192,\n\tAPSR_TDM = 16384,\n\tAPSR_MIISELECT = 16777216,\n};\n\nenum ARSTR_BIT {\n\tARSTR_ARST = 1,\n};\n\nenum CCC_BIT {\n\tCCC_OPC = 3,\n\tCCC_OPC_RESET = 0,\n\tCCC_OPC_CONFIG = 1,\n\tCCC_OPC_OPERATION = 2,\n\tCCC_GAC = 128,\n\tCCC_DTSR = 256,\n\tCCC_CSEL = 196608,\n\tCCC_CSEL_HPB = 65536,\n\tCCC_CSEL_ETH_TX = 131072,\n\tCCC_CSEL_GMII_REF = 196608,\n\tCCC_LBME = 16777216,\n};\n\nenum CIE_BIT {\n\tCIE_CRIE = 1,\n\tCIE_CTIE = 256,\n\tCIE_RQFM = 65536,\n\tCIE_CL0M = 131072,\n\tCIE_RFWL = 262144,\n\tCIE_RFFL = 524288,\n};\n\nenum CMD_RET_VALUES {\n\tREFIRE_CMD = 1,\n\tCOMPLETE_CMD = 2,\n\tRETURN_CMD = 3,\n};\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum CSR0_BIT {\n\tCSR0_TPE = 16,\n\tCSR0_RPE = 32,\n};\n\nenum CSR1_BIT {\n\tCSR1_TIP4 = 1,\n\tCSR1_TTCP4 = 16,\n\tCSR1_TUDP4 = 32,\n\tCSR1_TICMP4 = 64,\n\tCSR1_TTCP6 = 1048576,\n\tCSR1_TUDP6 = 2097152,\n\tCSR1_TICMP6 = 4194304,\n\tCSR1_THOP = 16777216,\n\tCSR1_TROUT = 33554432,\n\tCSR1_TAHD = 67108864,\n\tCSR1_TDHD = 134217728,\n};\n\nenum CSR2_BIT {\n\tCSR2_RIP4 = 1,\n\tCSR2_RTCP4 = 16,\n\tCSR2_RUDP4 = 32,\n\tCSR2_RICMP4 = 64,\n\tCSR2_RTCP6 = 1048576,\n\tCSR2_RUDP6 = 2097152,\n\tCSR2_RICMP6 = 4194304,\n\tCSR2_RHOP = 16777216,\n\tCSR2_RROUT = 33554432,\n\tCSR2_RAHD = 67108864,\n\tCSR2_RDHD = 134217728,\n};\n\nenum CSR_BIT {\n\tCSR_OPS = 15,\n\tCSR_OPS_RESET = 1,\n\tCSR_OPS_CONFIG = 2,\n\tCSR_OPS_OPERATION = 4,\n\tCSR_OPS_STANDBY = 8,\n\tCSR_DTS = 256,\n\tCSR_TPO0 = 65536,\n\tCSR_TPO1 = 131072,\n\tCSR_TPO2 = 262144,\n\tCSR_TPO3 = 524288,\n\tCSR_RPO = 1048576,\n};\n\nenum CXR31_BIT {\n\tCXR31_SEL_LINK0 = 1,\n\tCXR31_SEL_LINK1 = 8,\n};\n\nenum CXR35_BIT {\n\tCXR35_SEL_XMII = 3,\n\tCXR35_SEL_XMII_RGMII = 0,\n\tCXR35_SEL_XMII_MII = 2,\n\tCXR35_HALFCYC_CLKSW = 4294901760,\n};\n\nenum DCMD_RETURN_STATUS {\n\tDCMD_SUCCESS = 0,\n\tDCMD_TIMEOUT = 1,\n\tDCMD_FAILED = 2,\n\tDCMD_BUSY = 3,\n\tDCMD_INIT = 255,\n};\n\nenum DCMD_TIMEOUT_ACTION {\n\tINITIATE_OCR = 0,\n\tKILL_ADAPTER = 1,\n\tIGNORE_TIMEOUT = 2,\n};\n\nenum DIE_DT {\n\tDT_FEMPTY_IS = 16,\n\tDT_FEMPTY_IC = 32,\n\tDT_FEMPTY_ND = 48,\n\tDT_FEMPTY = 64,\n\tDT_FEMPTY_START = 80,\n\tDT_FEMPTY_MID = 96,\n\tDT_FEMPTY_END = 112,\n\tDT_FSINGLE = 128,\n\tDT_FSTART = 144,\n\tDT_FMID = 160,\n\tDT_FEND = 176,\n\tDT_LEMPTY = 192,\n\tDT_EEMPTY = 208,\n\tDT_LINK = 224,\n\tDT_EOS = 240,\n\tDT_MASK = 240,\n\tD_DIE = 8,\n};\n\nenum DIE_DT___2 {\n\tDT_FSINGLE___2 = 128,\n\tDT_FSTART___2 = 144,\n\tDT_FMID___2 = 160,\n\tDT_FEND___2 = 176,\n\tDT_LEMPTY___2 = 192,\n\tDT_EEMPTY___2 = 208,\n\tDT_LINKFIX = 0,\n\tDT_LINK___2 = 224,\n\tDT_EOS___2 = 240,\n\tDT_FEMPTY___2 = 64,\n\tDT_FEMPTY_IS___2 = 16,\n\tDT_FEMPTY_IC___2 = 32,\n\tDT_FEMPTY_ND___2 = 48,\n\tDT_FEMPTY_START___2 = 80,\n\tDT_FEMPTY_MID___2 = 96,\n\tDT_FEMPTY_END___2 = 112,\n\tDT_MASK___2 = 240,\n\tDIE = 8,\n};\n\nenum DIE_DT___3 {\n\tDT_FMID___3 = 64,\n\tDT_FSTART___3 = 80,\n\tDT_FEND___3 = 96,\n\tDT_FSINGLE___3 = 112,\n\tDT_LINK___3 = 128,\n\tDT_LINKFIX___2 = 144,\n\tDT_EOS___3 = 160,\n\tDT_FEMPTY___3 = 192,\n\tDT_FEMPTY_IS___3 = 208,\n\tDT_FEMPTY_IC___3 = 224,\n\tDT_FEMPTY_ND___3 = 240,\n\tDT_LEMPTY___3 = 32,\n\tDT_EEMPTY___3 = 48,\n};\n\nenum DMA_REGS_OFFSET {\n\tOFFSET_INT_FLAG = 0,\n\tOFFSET_INT_EN = 4,\n\tOFFSET_EN = 8,\n\tOFFSET_RST = 12,\n\tOFFSET_CON = 24,\n\tOFFSET_TX_MEM_ADDR = 28,\n\tOFFSET_RX_MEM_ADDR = 32,\n\tOFFSET_TX_LEN = 36,\n\tOFFSET_RX_LEN = 40,\n\tOFFSET_TX_4G_MODE = 84,\n\tOFFSET_RX_4G_MODE = 88,\n};\n\nenum E1000_INVM_STRUCTURE_TYPE {\n\tE1000_INVM_UNINITIALIZED_STRUCTURE = 0,\n\tE1000_INVM_WORD_AUTOLOAD_STRUCTURE = 1,\n\tE1000_INVM_CSR_AUTOLOAD_STRUCTURE = 2,\n\tE1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 3,\n\tE1000_INVM_RSA_KEY_SHA256_STRUCTURE = 4,\n\tE1000_INVM_INVALIDATED_STRUCTURE = 15,\n};\n\nenum ECMR_BIT {\n\tECMR_PRM = 1,\n\tECMR_DM = 2,\n\tECMR_TE = 32,\n\tECMR_RE = 64,\n\tECMR_MPDE = 512,\n\tECMR_TXF = 65536,\n\tECMR_RXF = 131072,\n\tECMR_PFR = 262144,\n\tECMR_ZPF = 524288,\n\tECMR_RZPF = 1048576,\n\tECMR_DPAD = 2097152,\n\tECMR_RCSC = 8388608,\n\tECMR_RCPT = 33554432,\n\tECMR_TRCCM = 67108864,\n};\n\nenum ECMR_BIT___2 {\n\tECMR_TRCCM___2 = 67108864,\n\tECMR_RCSC___2 = 8388608,\n\tECMR_DPAD___2 = 2097152,\n\tECMR_RZPF___2 = 1048576,\n\tECMR_ZPF___2 = 524288,\n\tECMR_PFR___2 = 262144,\n\tECMR_RXF___2 = 131072,\n\tECMR_TXF___2 = 65536,\n\tECMR_MCT = 8192,\n\tECMR_PRCEF = 4096,\n\tECMR_MPDE___2 = 512,\n\tECMR_RE___2 = 64,\n\tECMR_TE___2 = 32,\n\tECMR_RTM = 16,\n\tECMR_ILB = 8,\n\tECMR_ELB = 4,\n\tECMR_DM___2 = 2,\n\tECMR_PRM___2 = 1,\n};\n\nenum ECSIPR_BIT {\n\tECSIPR_ICDIP = 1,\n\tECSIPR_MPDIP = 2,\n\tECSIPR_LCHNGIP = 4,\n};\n\nenum ECSIPR_BIT___2 {\n\tECSIPR_BRCRXIP = 32,\n\tECSIPR_PSRTOIP = 16,\n\tECSIPR_LCHNGIP___2 = 4,\n\tECSIPR_MPDIP___2 = 2,\n\tECSIPR_ICDIP___2 = 1,\n};\n\nenum ECSR_BIT {\n\tECSR_ICD = 1,\n\tECSR_MPD = 2,\n\tECSR_LCHNG = 4,\n\tECSR_PHYI = 8,\n\tECSR_PFRI = 16,\n};\n\nenum ECSR_BIT___2 {\n\tECSR_BRCRX = 32,\n\tECSR_PSRTO = 16,\n\tECSR_LCHNG___2 = 4,\n\tECSR_MPD___2 = 2,\n\tECSR_ICD___2 = 1,\n};\n\nenum EDMR_BIT {\n\tEDMR_NBST = 128,\n\tEDMR_EL = 64,\n\tEDMR_DL1 = 32,\n\tEDMR_DL0 = 16,\n\tEDMR_SRST_GETHER = 3,\n\tEDMR_SRST_ETHER = 1,\n};\n\nenum EDRRR_BIT {\n\tEDRRR_R = 1,\n};\n\nenum EDSR_BIT {\n\tEDSR_ENT = 1,\n\tEDSR_ENR = 2,\n};\n\nenum EDTRR_BIT {\n\tEDTRR_TRNS_GETHER = 3,\n\tEDTRR_TRNS_ETHER = 1,\n};\n\nenum EESIPR_BIT {\n\tEESIPR_TWB1IP = 2147483648,\n\tEESIPR_TWBIP = 1073741824,\n\tEESIPR_TC1IP = 536870912,\n\tEESIPR_TUCIP = 268435456,\n\tEESIPR_ROCIP = 134217728,\n\tEESIPR_TABTIP = 67108864,\n\tEESIPR_RABTIP = 33554432,\n\tEESIPR_RFCOFIP = 16777216,\n\tEESIPR_ADEIP = 8388608,\n\tEESIPR_ECIIP = 4194304,\n\tEESIPR_FTCIP = 2097152,\n\tEESIPR_TDEIP = 1048576,\n\tEESIPR_TFUFIP = 524288,\n\tEESIPR_FRIP = 262144,\n\tEESIPR_RDEIP = 131072,\n\tEESIPR_RFOFIP = 65536,\n\tEESIPR_CNDIP = 2048,\n\tEESIPR_DLCIP = 1024,\n\tEESIPR_CDIP = 512,\n\tEESIPR_TROIP = 256,\n\tEESIPR_RMAFIP = 128,\n\tEESIPR_CEEFIP = 64,\n\tEESIPR_CELFIP = 32,\n\tEESIPR_RRFIP = 16,\n\tEESIPR_RTLFIP = 8,\n\tEESIPR_RTSFIP = 4,\n\tEESIPR_PREIP = 2,\n\tEESIPR_CERFIP = 1,\n};\n\nenum EESR_BIT {\n\tEESR_TWB1 = 2147483648,\n\tEESR_TWB = 1073741824,\n\tEESR_TC1 = 536870912,\n\tEESR_TUC = 268435456,\n\tEESR_ROC = 134217728,\n\tEESR_TABT = 67108864,\n\tEESR_RABT = 33554432,\n\tEESR_RFRMER = 16777216,\n\tEESR_ADE = 8388608,\n\tEESR_ECI = 4194304,\n\tEESR_FTC = 2097152,\n\tEESR_TDE = 1048576,\n\tEESR_TFE = 524288,\n\tEESR_FRC = 262144,\n\tEESR_RDE = 131072,\n\tEESR_RFE = 65536,\n\tEESR_CND = 2048,\n\tEESR_DLC = 1024,\n\tEESR_CD = 512,\n\tEESR_TRO = 256,\n\tEESR_RMAF = 128,\n\tEESR_CEEF = 64,\n\tEESR_CELF = 32,\n\tEESR_RRF = 16,\n\tEESR_RTLF = 8,\n\tEESR_RTSF = 4,\n\tEESR_PRE = 2,\n\tEESR_CERF = 1,\n};\n\nenum EIS_BIT {\n\tEIS_MREF = 1,\n\tEIS_MTEF = 2,\n\tEIS_QEF = 4,\n\tEIS_SEF = 8,\n\tEIS_CLLF0 = 16,\n\tEIS_CLLF1 = 32,\n\tEIS_CULF0 = 64,\n\tEIS_CULF1 = 128,\n\tEIS_TFFF = 256,\n\tEIS_QFS = 65536,\n\tEIS_RESERVED = 4294899712,\n};\n\nenum EXT_INFO_DS_BIT {\n\tTXC = 16384,\n};\n\nenum FCFTR_BIT {\n\tFCFTR_RFF2 = 262144,\n\tFCFTR_RFF1 = 131072,\n\tFCFTR_RFF0 = 65536,\n\tFCFTR_RFD2 = 4,\n\tFCFTR_RFD1 = 2,\n\tFCFTR_RFD0 = 1,\n};\n\nenum FW_BOOT_CONTEXT {\n\tPROBE_CONTEXT = 0,\n\tOCR_CONTEXT = 1,\n};\n\nenum GCCR_BIT {\n\tGCCR_TCR = 3,\n\tGCCR_TCR_NOREQ = 0,\n\tGCCR_TCR_RESET = 1,\n\tGCCR_TCR_CAPTURE = 3,\n\tGCCR_LTO = 4,\n\tGCCR_LTI = 8,\n\tGCCR_LPTC = 16,\n\tGCCR_LMTT = 32,\n\tGCCR_TCSS = 768,\n\tGCCR_TCSS_GPTP = 0,\n\tGCCR_TCSS_ADJGPTP = 256,\n\tGCCR_TCSS_AVTP = 512,\n};\n\nenum GECMR_BIT {\n\tGECMR_10 = 0,\n\tGECMR_100 = 4,\n\tGECMR_1000 = 1,\n};\n\nenum GECMR_BIT___2 {\n\tGECMR_SPEED = 1,\n\tGECMR_SPEED_100 = 0,\n\tGECMR_SPEED_1000 = 1,\n\tGBETH_GECMR_SPEED = 48,\n\tGBETH_GECMR_SPEED_10 = 0,\n\tGBETH_GECMR_SPEED_100 = 16,\n\tGBETH_GECMR_SPEED_1000 = 32,\n};\n\nenum GIC_BIT {\n\tGIC_PTCE = 1,\n\tGIC_PTME = 4,\n};\n\nenum GID_BIT {\n\tGID_PTCD = 1,\n\tGID_PTOD = 2,\n\tGID_PTMD0 = 4,\n\tGID_PTMD1 = 8,\n\tGID_PTMD2 = 16,\n\tGID_PTMD3 = 32,\n\tGID_PTMD4 = 64,\n\tGID_PTMD5 = 128,\n\tGID_PTMD6 = 256,\n\tGID_PTMD7 = 512,\n\tGID_ATCD0 = 65536,\n\tGID_ATCD1 = 131072,\n\tGID_ATCD2 = 262144,\n\tGID_ATCD3 = 524288,\n\tGID_ATCD4 = 1048576,\n\tGID_ATCD5 = 2097152,\n\tGID_ATCD6 = 4194304,\n\tGID_ATCD7 = 8388608,\n\tGID_ATCD8 = 16777216,\n\tGID_ATCD9 = 33554432,\n\tGID_ATCD10 = 67108864,\n\tGID_ATCD11 = 134217728,\n\tGID_ATCD12 = 268435456,\n\tGID_ATCD13 = 536870912,\n\tGID_ATCD14 = 1073741824,\n\tGID_ATCD15 = 2147483648,\n};\n\nenum GIE_BIT {\n\tGIE_PTCS = 1,\n\tGIE_PTOS = 2,\n\tGIE_PTMS0 = 4,\n\tGIE_PTMS1 = 8,\n\tGIE_PTMS2 = 16,\n\tGIE_PTMS3 = 32,\n\tGIE_PTMS4 = 64,\n\tGIE_PTMS5 = 128,\n\tGIE_PTMS6 = 256,\n\tGIE_PTMS7 = 512,\n\tGIE_ATCS0 = 65536,\n\tGIE_ATCS1 = 131072,\n\tGIE_ATCS2 = 262144,\n\tGIE_ATCS3 = 524288,\n\tGIE_ATCS4 = 1048576,\n\tGIE_ATCS5 = 2097152,\n\tGIE_ATCS6 = 4194304,\n\tGIE_ATCS7 = 8388608,\n\tGIE_ATCS8 = 16777216,\n\tGIE_ATCS9 = 33554432,\n\tGIE_ATCS10 = 67108864,\n\tGIE_ATCS11 = 134217728,\n\tGIE_ATCS12 = 268435456,\n\tGIE_ATCS13 = 536870912,\n\tGIE_ATCS14 = 1073741824,\n\tGIE_ATCS15 = 2147483648,\n};\n\nenum GIS_BIT {\n\tGIS_PTCF = 1,\n\tGIS_PTMF = 4,\n\tGIS_RESERVED = 64512,\n};\n\nenum GTI_BIT {\n\tGTI_TIV = 268435455,\n};\n\nenum HCLGE_COMM_API_CAP_BITS {\n\tHCLGE_COMM_API_CAP_FLEX_RSS_TBL_B = 0,\n};\n\nenum HCLGE_COMM_CAP_BITS {\n\tHCLGE_COMM_CAP_UDP_GSO_B = 0,\n\tHCLGE_COMM_CAP_QB_B = 1,\n\tHCLGE_COMM_CAP_FD_FORWARD_TC_B = 2,\n\tHCLGE_COMM_CAP_PTP_B = 3,\n\tHCLGE_COMM_CAP_INT_QL_B = 4,\n\tHCLGE_COMM_CAP_HW_TX_CSUM_B = 5,\n\tHCLGE_COMM_CAP_TX_PUSH_B = 6,\n\tHCLGE_COMM_CAP_PHY_IMP_B = 7,\n\tHCLGE_COMM_CAP_TQP_TXRX_INDEP_B = 8,\n\tHCLGE_COMM_CAP_HW_PAD_B = 9,\n\tHCLGE_COMM_CAP_STASH_B = 10,\n\tHCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B = 11,\n\tHCLGE_COMM_CAP_RAS_IMP_B = 12,\n\tHCLGE_COMM_CAP_FEC_B = 13,\n\tHCLGE_COMM_CAP_PAUSE_B = 14,\n\tHCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,\n\tHCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,\n\tHCLGE_COMM_CAP_CQ_B = 18,\n\tHCLGE_COMM_CAP_GRO_B = 20,\n\tHCLGE_COMM_CAP_FD_B = 21,\n\tHCLGE_COMM_CAP_FEC_STATS_B = 25,\n\tHCLGE_COMM_CAP_VF_FAULT_B = 26,\n\tHCLGE_COMM_CAP_LANE_NUM_B = 27,\n\tHCLGE_COMM_CAP_WOL_B = 28,\n\tHCLGE_COMM_CAP_TM_FLUSH_B = 31,\n\tHCLGE_COMM_CAP_ERR_MOD_GEN_REG_B = 32,\n};\n\nenum HCLGE_DEV_STATE {\n\tHCLGE_STATE_REINITING = 0,\n\tHCLGE_STATE_DOWN = 1,\n\tHCLGE_STATE_DISABLED = 2,\n\tHCLGE_STATE_REMOVING = 3,\n\tHCLGE_STATE_NIC_REGISTERED = 4,\n\tHCLGE_STATE_ROCE_REGISTERED = 5,\n\tHCLGE_STATE_SERVICE_INITED = 6,\n\tHCLGE_STATE_RST_SERVICE_SCHED = 7,\n\tHCLGE_STATE_RST_HANDLING = 8,\n\tHCLGE_STATE_MBX_SERVICE_SCHED = 9,\n\tHCLGE_STATE_MBX_HANDLING = 10,\n\tHCLGE_STATE_ERR_SERVICE_SCHED = 11,\n\tHCLGE_STATE_STATISTICS_UPDATING = 12,\n\tHCLGE_STATE_LINK_UPDATING = 13,\n\tHCLGE_STATE_RST_FAIL = 14,\n\tHCLGE_STATE_FD_TBL_CHANGED = 15,\n\tHCLGE_STATE_FD_CLEAR_ALL = 16,\n\tHCLGE_STATE_FD_USER_DEF_CHANGED = 17,\n\tHCLGE_STATE_PTP_EN = 18,\n\tHCLGE_STATE_PTP_TX_HANDLING = 19,\n\tHCLGE_STATE_FEC_STATS_UPDATING = 20,\n\tHCLGE_STATE_MAX = 21,\n};\n\nenum HCLGE_FD_ACTION {\n\tHCLGE_FD_ACTION_SELECT_QUEUE = 0,\n\tHCLGE_FD_ACTION_DROP_PACKET = 1,\n\tHCLGE_FD_ACTION_SELECT_TC = 2,\n};\n\nenum HCLGE_FD_ACTIVE_RULE_TYPE {\n\tHCLGE_FD_RULE_NONE = 0,\n\tHCLGE_FD_ARFS_ACTIVE = 1,\n\tHCLGE_FD_EP_ACTIVE = 2,\n\tHCLGE_FD_TC_FLOWER_ACTIVE = 3,\n};\n\nenum HCLGE_FD_KEY_OPT {\n\tKEY_OPT_U8 = 0,\n\tKEY_OPT_LE16 = 1,\n\tKEY_OPT_LE32 = 2,\n\tKEY_OPT_MAC = 3,\n\tKEY_OPT_IP = 4,\n\tKEY_OPT_VNI = 5,\n};\n\nenum HCLGE_FD_KEY_TYPE {\n\tHCLGE_FD_KEY_BASE_ON_PTYPE = 0,\n\tHCLGE_FD_KEY_BASE_ON_TUPLE = 1,\n};\n\nenum HCLGE_FD_META_DATA {\n\tPACKET_TYPE_ID = 0,\n\tIP_FRAGEMENT = 1,\n\tROCE_TYPE = 2,\n\tNEXT_KEY = 3,\n\tVLAN_NUMBER = 4,\n\tSRC_VPORT = 5,\n\tDST_VPORT = 6,\n\tTUNNEL_PACKET = 7,\n\tMAX_META_DATA = 8,\n};\n\nenum HCLGE_FD_MODE {\n\tHCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1 = 0,\n\tHCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2 = 1,\n\tHCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1 = 2,\n\tHCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2 = 3,\n};\n\nenum HCLGE_FD_NODE_STATE {\n\tHCLGE_FD_TO_ADD = 0,\n\tHCLGE_FD_TO_DEL = 1,\n\tHCLGE_FD_ACTIVE = 2,\n\tHCLGE_FD_DELETED = 3,\n};\n\nenum HCLGE_FD_PACKET_TYPE {\n\tNIC_PACKET = 0,\n\tROCE_PACKET = 1,\n};\n\nenum HCLGE_FD_STAGE {\n\tHCLGE_FD_STAGE_1 = 0,\n\tHCLGE_FD_STAGE_2 = 1,\n\tMAX_STAGE_NUM = 2,\n};\n\nenum HCLGE_FD_TUPLE {\n\tOUTER_DST_MAC = 0,\n\tOUTER_SRC_MAC = 1,\n\tOUTER_VLAN_TAG_FST = 2,\n\tOUTER_VLAN_TAG_SEC = 3,\n\tOUTER_ETH_TYPE = 4,\n\tOUTER_L2_RSV = 5,\n\tOUTER_IP_TOS = 6,\n\tOUTER_IP_PROTO = 7,\n\tOUTER_SRC_IP = 8,\n\tOUTER_DST_IP = 9,\n\tOUTER_L3_RSV = 10,\n\tOUTER_SRC_PORT = 11,\n\tOUTER_DST_PORT = 12,\n\tOUTER_L4_RSV = 13,\n\tOUTER_TUN_VNI = 14,\n\tOUTER_TUN_FLOW_ID = 15,\n\tINNER_DST_MAC = 16,\n\tINNER_SRC_MAC = 17,\n\tINNER_VLAN_TAG_FST = 18,\n\tINNER_VLAN_TAG_SEC = 19,\n\tINNER_ETH_TYPE = 20,\n\tINNER_L2_RSV = 21,\n\tINNER_IP_TOS = 22,\n\tINNER_IP_PROTO = 23,\n\tINNER_SRC_IP = 24,\n\tINNER_DST_IP = 25,\n\tINNER_L3_RSV = 26,\n\tINNER_SRC_PORT = 27,\n\tINNER_DST_PORT = 28,\n\tINNER_L4_RSV = 29,\n\tMAX_TUPLE = 30,\n};\n\nenum HCLGE_FD_USER_DEF_LAYER {\n\tHCLGE_FD_USER_DEF_NONE = 0,\n\tHCLGE_FD_USER_DEF_L2 = 1,\n\tHCLGE_FD_USER_DEF_L3 = 2,\n\tHCLGE_FD_USER_DEF_L4 = 3,\n};\n\nenum HCLGE_FIRMWARE_MAC_SPEED {\n\tHCLGE_FW_MAC_SPEED_1G = 0,\n\tHCLGE_FW_MAC_SPEED_10G = 1,\n\tHCLGE_FW_MAC_SPEED_25G = 2,\n\tHCLGE_FW_MAC_SPEED_40G = 3,\n\tHCLGE_FW_MAC_SPEED_50G = 4,\n\tHCLGE_FW_MAC_SPEED_100G = 5,\n\tHCLGE_FW_MAC_SPEED_10M = 6,\n\tHCLGE_FW_MAC_SPEED_100M = 7,\n\tHCLGE_FW_MAC_SPEED_200G = 8,\n};\n\nenum HCLGE_MAC_ADDR_TYPE {\n\tHCLGE_MAC_ADDR_UC = 0,\n\tHCLGE_MAC_ADDR_MC = 1,\n};\n\nenum HCLGE_MAC_DUPLEX {\n\tHCLGE_MAC_HALF = 0,\n\tHCLGE_MAC_FULL = 1,\n};\n\nenum HCLGE_MAC_NODE_STATE {\n\tHCLGE_MAC_TO_ADD = 0,\n\tHCLGE_MAC_TO_DEL = 1,\n\tHCLGE_MAC_ACTIVE = 2,\n};\n\nenum HCLGE_MAC_SPEED {\n\tHCLGE_MAC_SPEED_UNKNOWN = 0,\n\tHCLGE_MAC_SPEED_10M = 10,\n\tHCLGE_MAC_SPEED_100M = 100,\n\tHCLGE_MAC_SPEED_1G = 1000,\n\tHCLGE_MAC_SPEED_10G = 10000,\n\tHCLGE_MAC_SPEED_25G = 25000,\n\tHCLGE_MAC_SPEED_40G = 40000,\n\tHCLGE_MAC_SPEED_50G = 50000,\n\tHCLGE_MAC_SPEED_100G = 100000,\n\tHCLGE_MAC_SPEED_200G = 200000,\n};\n\nenum HCLGE_MBX_OPCODE {\n\tHCLGE_MBX_RESET = 1,\n\tHCLGE_MBX_ASSERTING_RESET = 2,\n\tHCLGE_MBX_SET_UNICAST = 3,\n\tHCLGE_MBX_SET_MULTICAST = 4,\n\tHCLGE_MBX_SET_VLAN = 5,\n\tHCLGE_MBX_MAP_RING_TO_VECTOR = 6,\n\tHCLGE_MBX_UNMAP_RING_TO_VECTOR = 7,\n\tHCLGE_MBX_SET_PROMISC_MODE = 8,\n\tHCLGE_MBX_SET_MACVLAN = 9,\n\tHCLGE_MBX_API_NEGOTIATE = 10,\n\tHCLGE_MBX_GET_QINFO = 11,\n\tHCLGE_MBX_GET_QDEPTH = 12,\n\tHCLGE_MBX_GET_BASIC_INFO = 13,\n\tHCLGE_MBX_GET_RETA = 14,\n\tHCLGE_MBX_GET_RSS_KEY = 15,\n\tHCLGE_MBX_GET_MAC_ADDR = 16,\n\tHCLGE_MBX_PF_VF_RESP = 17,\n\tHCLGE_MBX_GET_BDNUM = 18,\n\tHCLGE_MBX_GET_BUFSIZE = 19,\n\tHCLGE_MBX_GET_STREAMID = 20,\n\tHCLGE_MBX_SET_AESTART = 21,\n\tHCLGE_MBX_SET_TSOSTATS = 22,\n\tHCLGE_MBX_LINK_STAT_CHANGE = 23,\n\tHCLGE_MBX_GET_BASE_CONFIG = 24,\n\tHCLGE_MBX_BIND_FUNC_QUEUE = 25,\n\tHCLGE_MBX_GET_LINK_STATUS = 26,\n\tHCLGE_MBX_QUEUE_RESET = 27,\n\tHCLGE_MBX_KEEP_ALIVE = 28,\n\tHCLGE_MBX_SET_ALIVE = 29,\n\tHCLGE_MBX_SET_MTU = 30,\n\tHCLGE_MBX_GET_QID_IN_PF = 31,\n\tHCLGE_MBX_LINK_STAT_MODE = 32,\n\tHCLGE_MBX_GET_LINK_MODE = 33,\n\tHCLGE_MBX_PUSH_VLAN_INFO = 34,\n\tHCLGE_MBX_GET_MEDIA_TYPE = 35,\n\tHCLGE_MBX_PUSH_PROMISC_INFO = 36,\n\tHCLGE_MBX_VF_UNINIT = 37,\n\tHCLGE_MBX_HANDLE_VF_TBL = 38,\n\tHCLGE_MBX_GET_RING_VECTOR_MAP = 39,\n\tHCLGE_MBX_GET_VF_FLR_STATUS = 200,\n\tHCLGE_MBX_PUSH_LINK_STATUS = 201,\n\tHCLGE_MBX_NCSI_ERROR = 202,\n};\n\nenum HCLGE_VPORT_NEED_NOTIFY {\n\tHCLGE_VPORT_NEED_NOTIFY_RESET = 0,\n\tHCLGE_VPORT_NEED_NOTIFY_VF_VLAN = 1,\n};\n\nenum HCLGE_VPORT_STATE {\n\tHCLGE_VPORT_STATE_ALIVE = 0,\n\tHCLGE_VPORT_STATE_MAC_TBL_CHANGE = 1,\n\tHCLGE_VPORT_STATE_PROMISC_CHANGE = 2,\n\tHCLGE_VPORT_STATE_VLAN_FLTR_CHANGE = 3,\n\tHCLGE_VPORT_STATE_INITED = 4,\n\tHCLGE_VPORT_STATE_MAX = 5,\n};\n\nenum HLCGE_PORT_TYPE {\n\tHOST_PORT = 0,\n\tNETWORK_PORT = 1,\n};\n\nenum HNAE3_DEV_CAP_BITS {\n\tHNAE3_DEV_SUPPORT_FD_B = 0,\n\tHNAE3_DEV_SUPPORT_GRO_B = 1,\n\tHNAE3_DEV_SUPPORT_FEC_B = 2,\n\tHNAE3_DEV_SUPPORT_UDP_GSO_B = 3,\n\tHNAE3_DEV_SUPPORT_QB_B = 4,\n\tHNAE3_DEV_SUPPORT_FD_FORWARD_TC_B = 5,\n\tHNAE3_DEV_SUPPORT_PTP_B = 6,\n\tHNAE3_DEV_SUPPORT_INT_QL_B = 7,\n\tHNAE3_DEV_SUPPORT_HW_TX_CSUM_B = 8,\n\tHNAE3_DEV_SUPPORT_TX_PUSH_B = 9,\n\tHNAE3_DEV_SUPPORT_PHY_IMP_B = 10,\n\tHNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B = 11,\n\tHNAE3_DEV_SUPPORT_HW_PAD_B = 12,\n\tHNAE3_DEV_SUPPORT_STASH_B = 13,\n\tHNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B = 14,\n\tHNAE3_DEV_SUPPORT_PAUSE_B = 15,\n\tHNAE3_DEV_SUPPORT_RAS_IMP_B = 16,\n\tHNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B = 17,\n\tHNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B = 18,\n\tHNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B = 19,\n\tHNAE3_DEV_SUPPORT_MC_MAC_MNG_B = 20,\n\tHNAE3_DEV_SUPPORT_CQ_B = 21,\n\tHNAE3_DEV_SUPPORT_FEC_STATS_B = 22,\n\tHNAE3_DEV_SUPPORT_LANE_NUM_B = 23,\n\tHNAE3_DEV_SUPPORT_WOL_B = 24,\n\tHNAE3_DEV_SUPPORT_TM_FLUSH_B = 25,\n\tHNAE3_DEV_SUPPORT_VF_FAULT_B = 26,\n\tHNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B = 27,\n};\n\nenum HNAE3_PF_CAP_BITS {\n\tHNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,\n};\n\nenum I2C_REGS_OFFSET {\n\tOFFSET_DATA_PORT = 0,\n\tOFFSET_SLAVE_ADDR = 1,\n\tOFFSET_INTR_MASK = 2,\n\tOFFSET_INTR_STAT = 3,\n\tOFFSET_CONTROL = 4,\n\tOFFSET_TRANSFER_LEN = 5,\n\tOFFSET_TRANSAC_LEN = 6,\n\tOFFSET_DELAY_LEN = 7,\n\tOFFSET_TIMING = 8,\n\tOFFSET_START = 9,\n\tOFFSET_EXT_CONF = 10,\n\tOFFSET_FIFO_STAT = 11,\n\tOFFSET_FIFO_THRESH = 12,\n\tOFFSET_FIFO_ADDR_CLR = 13,\n\tOFFSET_IO_CONFIG = 14,\n\tOFFSET_RSV_DEBUG = 15,\n\tOFFSET_HS = 16,\n\tOFFSET_SOFTRESET = 17,\n\tOFFSET_DCM_EN = 18,\n\tOFFSET_MULTI_DMA = 19,\n\tOFFSET_PATH_DIR = 20,\n\tOFFSET_DEBUGSTAT = 21,\n\tOFFSET_DEBUGCTRL = 22,\n\tOFFSET_TRANSFER_LEN_AUX = 23,\n\tOFFSET_CLOCK_DIV = 24,\n\tOFFSET_LTIMING = 25,\n\tOFFSET_SCL_HIGH_LOW_RATIO = 26,\n\tOFFSET_HS_SCL_HIGH_LOW_RATIO = 27,\n\tOFFSET_SCL_MIS_COMP_POINT = 28,\n\tOFFSET_STA_STO_AC_TIMING = 29,\n\tOFFSET_HS_STA_STO_AC_TIMING = 30,\n\tOFFSET_SDA_TIMING = 31,\n};\n\nenum ISS_BIT {\n\tISS_FRS = 1,\n\tISS_FTS = 4,\n\tISS_ES = 64,\n\tISS_MS = 128,\n\tISS_TFUS = 256,\n\tISS_TFWS = 512,\n\tISS_RFWS = 4096,\n\tISS_CGIS = 8192,\n\tISS_DPS1 = 131072,\n\tISS_DPS2 = 262144,\n\tISS_DPS3 = 524288,\n\tISS_DPS4 = 1048576,\n\tISS_DPS5 = 2097152,\n\tISS_DPS6 = 4194304,\n\tISS_DPS7 = 8388608,\n\tISS_DPS8 = 16777216,\n\tISS_DPS9 = 33554432,\n\tISS_DPS10 = 67108864,\n\tISS_DPS11 = 134217728,\n\tISS_DPS12 = 268435456,\n\tISS_DPS13 = 536870912,\n\tISS_DPS14 = 1073741824,\n\tISS_DPS15 = 2147483648,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum LMAC_TYPE {\n\tBGX_MODE_SGMII = 0,\n\tBGX_MODE_XAUI = 1,\n\tBGX_MODE_DXAUI = 1,\n\tBGX_MODE_RXAUI = 2,\n\tBGX_MODE_XFI = 3,\n\tBGX_MODE_XLAUI = 4,\n\tBGX_MODE_10G_KR = 3,\n\tBGX_MODE_40G_KR = 4,\n\tBGX_MODE_RGMII = 5,\n\tBGX_MODE_QSGMII = 6,\n\tBGX_MODE_INVALID = 7,\n};\n\nenum MAX77686_RTC_OP {\n\tMAX77686_RTC_WRITE = 0,\n\tMAX77686_RTC_READ = 1,\n};\n\nenum MCAST_MODE {\n\tMCAST_MODE_REJECT = 0,\n\tMCAST_MODE_ACCEPT = 1,\n\tMCAST_MODE_CAM_FILTER = 2,\n\tRSVD = 3,\n};\n\nenum MEGASAS_LD_TARGET_ID_STATUS {\n\tLD_TARGET_ID_INITIAL = 0,\n\tLD_TARGET_ID_ACTIVE = 1,\n\tLD_TARGET_ID_DELETED = 2,\n};\n\nenum MEGASAS_OCR_CAUSE {\n\tFW_FAULT_OCR = 0,\n\tSCSIIO_TIMEOUT_OCR = 1,\n\tMFI_IO_TIMEOUT_OCR = 2,\n};\n\nenum MFI_CMD_OP {\n\tMFI_CMD_INIT = 0,\n\tMFI_CMD_LD_READ = 1,\n\tMFI_CMD_LD_WRITE = 2,\n\tMFI_CMD_LD_SCSI_IO = 3,\n\tMFI_CMD_PD_SCSI_IO = 4,\n\tMFI_CMD_DCMD = 5,\n\tMFI_CMD_ABORT = 6,\n\tMFI_CMD_SMP = 7,\n\tMFI_CMD_STP = 8,\n\tMFI_CMD_NVME = 9,\n\tMFI_CMD_TOOLBOX = 10,\n\tMFI_CMD_OP_COUNT = 11,\n\tMFI_CMD_INVALID = 255,\n};\n\nenum MFI_STAT {\n\tMFI_STAT_OK = 0,\n\tMFI_STAT_INVALID_CMD = 1,\n\tMFI_STAT_INVALID_DCMD = 2,\n\tMFI_STAT_INVALID_PARAMETER = 3,\n\tMFI_STAT_INVALID_SEQUENCE_NUMBER = 4,\n\tMFI_STAT_ABORT_NOT_POSSIBLE = 5,\n\tMFI_STAT_APP_HOST_CODE_NOT_FOUND = 6,\n\tMFI_STAT_APP_IN_USE = 7,\n\tMFI_STAT_APP_NOT_INITIALIZED = 8,\n\tMFI_STAT_ARRAY_INDEX_INVALID = 9,\n\tMFI_STAT_ARRAY_ROW_NOT_EMPTY = 10,\n\tMFI_STAT_CONFIG_RESOURCE_CONFLICT = 11,\n\tMFI_STAT_DEVICE_NOT_FOUND = 12,\n\tMFI_STAT_DRIVE_TOO_SMALL = 13,\n\tMFI_STAT_FLASH_ALLOC_FAIL = 14,\n\tMFI_STAT_FLASH_BUSY = 15,\n\tMFI_STAT_FLASH_ERROR = 16,\n\tMFI_STAT_FLASH_IMAGE_BAD = 17,\n\tMFI_STAT_FLASH_IMAGE_INCOMPLETE = 18,\n\tMFI_STAT_FLASH_NOT_OPEN = 19,\n\tMFI_STAT_FLASH_NOT_STARTED = 20,\n\tMFI_STAT_FLUSH_FAILED = 21,\n\tMFI_STAT_HOST_CODE_NOT_FOUNT = 22,\n\tMFI_STAT_LD_CC_IN_PROGRESS = 23,\n\tMFI_STAT_LD_INIT_IN_PROGRESS = 24,\n\tMFI_STAT_LD_LBA_OUT_OF_RANGE = 25,\n\tMFI_STAT_LD_MAX_CONFIGURED = 26,\n\tMFI_STAT_LD_NOT_OPTIMAL = 27,\n\tMFI_STAT_LD_RBLD_IN_PROGRESS = 28,\n\tMFI_STAT_LD_RECON_IN_PROGRESS = 29,\n\tMFI_STAT_LD_WRONG_RAID_LEVEL = 30,\n\tMFI_STAT_MAX_SPARES_EXCEEDED = 31,\n\tMFI_STAT_MEMORY_NOT_AVAILABLE = 32,\n\tMFI_STAT_MFC_HW_ERROR = 33,\n\tMFI_STAT_NO_HW_PRESENT = 34,\n\tMFI_STAT_NOT_FOUND = 35,\n\tMFI_STAT_NOT_IN_ENCL = 36,\n\tMFI_STAT_PD_CLEAR_IN_PROGRESS = 37,\n\tMFI_STAT_PD_TYPE_WRONG = 38,\n\tMFI_STAT_PR_DISABLED = 39,\n\tMFI_STAT_ROW_INDEX_INVALID = 40,\n\tMFI_STAT_SAS_CONFIG_INVALID_ACTION = 41,\n\tMFI_STAT_SAS_CONFIG_INVALID_DATA = 42,\n\tMFI_STAT_SAS_CONFIG_INVALID_PAGE = 43,\n\tMFI_STAT_SAS_CONFIG_INVALID_TYPE = 44,\n\tMFI_STAT_SCSI_DONE_WITH_ERROR = 45,\n\tMFI_STAT_SCSI_IO_FAILED = 46,\n\tMFI_STAT_SCSI_RESERVATION_CONFLICT = 47,\n\tMFI_STAT_SHUTDOWN_FAILED = 48,\n\tMFI_STAT_TIME_NOT_SET = 49,\n\tMFI_STAT_WRONG_STATE = 50,\n\tMFI_STAT_LD_OFFLINE = 51,\n\tMFI_STAT_PEER_NOTIFICATION_REJECTED = 52,\n\tMFI_STAT_PEER_NOTIFICATION_FAILED = 53,\n\tMFI_STAT_RESERVATION_IN_PROGRESS = 54,\n\tMFI_STAT_I2C_ERRORS_DETECTED = 55,\n\tMFI_STAT_PCI_ERRORS_DETECTED = 56,\n\tMFI_STAT_CONFIG_SEQ_MISMATCH = 103,\n\tMFI_STAT_INVALID_STATUS = 255,\n};\n\nenum MR_ADAPTER_TYPE {\n\tMFI_SERIES = 1,\n\tTHUNDERBOLT_SERIES = 2,\n\tINVADER_SERIES = 3,\n\tVENTURA_SERIES = 4,\n\tAERO_SERIES = 5,\n};\n\nenum MR_EVT_CLASS {\n\tMR_EVT_CLASS_DEBUG = -2,\n\tMR_EVT_CLASS_PROGRESS = -1,\n\tMR_EVT_CLASS_INFO = 0,\n\tMR_EVT_CLASS_WARNING = 1,\n\tMR_EVT_CLASS_CRITICAL = 2,\n\tMR_EVT_CLASS_FATAL = 3,\n\tMR_EVT_CLASS_DEAD = 4,\n};\n\nenum MR_EVT_LOCALE {\n\tMR_EVT_LOCALE_LD = 1,\n\tMR_EVT_LOCALE_PD = 2,\n\tMR_EVT_LOCALE_ENCL = 4,\n\tMR_EVT_LOCALE_BBU = 8,\n\tMR_EVT_LOCALE_SAS = 16,\n\tMR_EVT_LOCALE_CTRL = 32,\n\tMR_EVT_LOCALE_CONFIG = 64,\n\tMR_EVT_LOCALE_CLUSTER = 128,\n\tMR_EVT_LOCALE_ALL = 65535,\n};\n\nenum MR_FW_CRASH_DUMP_STATE {\n\tUNAVAILABLE = 0,\n\tAVAILABLE = 1,\n\tCOPYING = 2,\n\tCOPIED = 3,\n\tCOPY_ERROR = 4,\n};\n\nenum MR_LD_QUERY_TYPE {\n\tMR_LD_QUERY_TYPE_ALL = 0,\n\tMR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,\n\tMR_LD_QUERY_TYPE_USED_TGT_IDS = 2,\n\tMR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,\n\tMR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,\n};\n\nenum MR_PD_QUERY_TYPE {\n\tMR_PD_QUERY_TYPE_ALL = 0,\n\tMR_PD_QUERY_TYPE_STATE = 1,\n\tMR_PD_QUERY_TYPE_POWER_STATE = 2,\n\tMR_PD_QUERY_TYPE_MEDIA_TYPE = 3,\n\tMR_PD_QUERY_TYPE_SPEED = 4,\n\tMR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,\n};\n\nenum MR_PD_STATE {\n\tMR_PD_STATE_UNCONFIGURED_GOOD = 0,\n\tMR_PD_STATE_UNCONFIGURED_BAD = 1,\n\tMR_PD_STATE_HOT_SPARE = 2,\n\tMR_PD_STATE_OFFLINE = 16,\n\tMR_PD_STATE_FAILED = 17,\n\tMR_PD_STATE_REBUILD = 20,\n\tMR_PD_STATE_ONLINE = 24,\n\tMR_PD_STATE_COPYBACK = 32,\n\tMR_PD_STATE_SYSTEM = 64,\n};\n\nenum MR_PD_TYPE {\n\tUNKNOWN_DRIVE = 0,\n\tPARALLEL_SCSI = 1,\n\tSAS_PD = 2,\n\tSATA_PD = 3,\n\tFC_PD = 4,\n\tNVME_PD = 5,\n};\n\nenum MR_PERF_MODE {\n\tMR_BALANCED_PERF_MODE = 0,\n\tMR_IOPS_PERF_MODE = 1,\n\tMR_LATENCY_PERF_MODE = 2,\n};\n\nenum MR_RAID_FLAGS_IO_SUB_TYPE {\n\tMR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,\n\tMR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,\n\tMR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,\n\tMR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,\n\tMR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,\n\tMR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,\n\tMR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7,\n\tMR_RAID_FLAGS_IO_SUB_TYPE_R56_DIV_OFFLOAD = 8,\n};\n\nenum MR_RAID_MAP_DESC_TYPE {\n\tRAID_MAP_DESC_TYPE_DEVHDL_INFO = 0,\n\tRAID_MAP_DESC_TYPE_TGTID_INFO = 1,\n\tRAID_MAP_DESC_TYPE_ARRAY_INFO = 2,\n\tRAID_MAP_DESC_TYPE_SPAN_INFO = 3,\n\tRAID_MAP_DESC_TYPE_COUNT = 4,\n};\n\nenum MR_SCSI_CMD_TYPE {\n\tREAD_WRITE_LDIO = 0,\n\tNON_READ_WRITE_LDIO = 1,\n\tREAD_WRITE_SYSPDIO = 2,\n\tNON_READ_WRITE_SYSPDIO = 3,\n};\n\nenum MSC_BIT {\n\tMSC_CRC = 1,\n\tMSC_RFE = 2,\n\tMSC_RTSF = 4,\n\tMSC_RTLF = 8,\n\tMSC_FRE = 16,\n\tMSC_CRL = 32,\n\tMSC_CEEF = 64,\n\tMSC_MC = 128,\n};\n\nenum MT6323_IRQ_STATUS_numbers {\n\tMT6323_IRQ_STATUS_SPKL_AB = 0,\n\tMT6323_IRQ_STATUS_SPKL = 1,\n\tMT6323_IRQ_STATUS_BAT_L = 2,\n\tMT6323_IRQ_STATUS_BAT_H = 3,\n\tMT6323_IRQ_STATUS_WATCHDOG = 4,\n\tMT6323_IRQ_STATUS_PWRKEY = 5,\n\tMT6323_IRQ_STATUS_THR_L = 6,\n\tMT6323_IRQ_STATUS_THR_H = 7,\n\tMT6323_IRQ_STATUS_VBATON_UNDET = 8,\n\tMT6323_IRQ_STATUS_BVALID_DET = 9,\n\tMT6323_IRQ_STATUS_CHRDET = 10,\n\tMT6323_IRQ_STATUS_OV = 11,\n\tMT6323_IRQ_STATUS_LDO = 16,\n\tMT6323_IRQ_STATUS_FCHRKEY = 17,\n\tMT6323_IRQ_STATUS_ACCDET = 18,\n\tMT6323_IRQ_STATUS_AUDIO = 19,\n\tMT6323_IRQ_STATUS_RTC = 20,\n\tMT6323_IRQ_STATUS_VPROC = 21,\n\tMT6323_IRQ_STATUS_VSYS = 22,\n\tMT6323_IRQ_STATUS_VPA = 23,\n\tMT6323_IRQ_STATUS_NR = 24,\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecPublicKey = 2,\n\tOID_id_prime192v1 = 3,\n\tOID_id_prime256v1 = 4,\n\tOID_id_ecdsa_with_sha1 = 5,\n\tOID_id_ecdsa_with_sha224 = 6,\n\tOID_id_ecdsa_with_sha256 = 7,\n\tOID_id_ecdsa_with_sha384 = 8,\n\tOID_id_ecdsa_with_sha512 = 9,\n\tOID_rsaEncryption = 10,\n\tOID_sha1WithRSAEncryption = 11,\n\tOID_sha256WithRSAEncryption = 12,\n\tOID_sha384WithRSAEncryption = 13,\n\tOID_sha512WithRSAEncryption = 14,\n\tOID_sha224WithRSAEncryption = 15,\n\tOID_data = 16,\n\tOID_signed_data = 17,\n\tOID_email_address = 18,\n\tOID_contentType = 19,\n\tOID_messageDigest = 20,\n\tOID_signingTime = 21,\n\tOID_smimeCapabilites = 22,\n\tOID_smimeAuthenticatedAttrs = 23,\n\tOID_mskrb5 = 24,\n\tOID_krb5 = 25,\n\tOID_krb5u2u = 26,\n\tOID_msIndirectData = 27,\n\tOID_msStatementType = 28,\n\tOID_msSpOpusInfo = 29,\n\tOID_msPeImageDataObjId = 30,\n\tOID_msIndividualSPKeyPurpose = 31,\n\tOID_msOutlookExpress = 32,\n\tOID_ntlmssp = 33,\n\tOID_negoex = 34,\n\tOID_spnego = 35,\n\tOID_IAKerb = 36,\n\tOID_PKU2U = 37,\n\tOID_Scram = 38,\n\tOID_certAuthInfoAccess = 39,\n\tOID_sha1 = 40,\n\tOID_id_ansip384r1 = 41,\n\tOID_id_ansip521r1 = 42,\n\tOID_sha256 = 43,\n\tOID_sha384 = 44,\n\tOID_sha512 = 45,\n\tOID_sha224 = 46,\n\tOID_commonName = 47,\n\tOID_surname = 48,\n\tOID_countryName = 49,\n\tOID_locality = 50,\n\tOID_stateOrProvinceName = 51,\n\tOID_organizationName = 52,\n\tOID_organizationUnitName = 53,\n\tOID_title = 54,\n\tOID_description = 55,\n\tOID_name = 56,\n\tOID_givenName = 57,\n\tOID_initials = 58,\n\tOID_generationalQualifier = 59,\n\tOID_subjectKeyIdentifier = 60,\n\tOID_keyUsage = 61,\n\tOID_subjectAltName = 62,\n\tOID_issuerAltName = 63,\n\tOID_basicConstraints = 64,\n\tOID_crlDistributionPoints = 65,\n\tOID_certPolicies = 66,\n\tOID_authorityKeyIdentifier = 67,\n\tOID_extKeyUsage = 68,\n\tOID_NetlogonMechanism = 69,\n\tOID_appleLocalKdcSupported = 70,\n\tOID_gostCPSignA = 71,\n\tOID_gostCPSignB = 72,\n\tOID_gostCPSignC = 73,\n\tOID_gost2012PKey256 = 74,\n\tOID_gost2012PKey512 = 75,\n\tOID_gost2012Digest256 = 76,\n\tOID_gost2012Digest512 = 77,\n\tOID_gost2012Signature256 = 78,\n\tOID_gost2012Signature512 = 79,\n\tOID_gostTC26Sign256A = 80,\n\tOID_gostTC26Sign256B = 81,\n\tOID_gostTC26Sign256C = 82,\n\tOID_gostTC26Sign256D = 83,\n\tOID_gostTC26Sign512A = 84,\n\tOID_gostTC26Sign512B = 85,\n\tOID_gostTC26Sign512C = 86,\n\tOID_sm2 = 87,\n\tOID_sm3 = 88,\n\tOID_SM2_with_SM3 = 89,\n\tOID_sm3WithRSAEncryption = 90,\n\tOID_TPMLoadableKey = 91,\n\tOID_TPMImportableKey = 92,\n\tOID_TPMSealedData = 93,\n\tOID_sha3_256 = 94,\n\tOID_sha3_384 = 95,\n\tOID_sha3_512 = 96,\n\tOID_id_ecdsa_with_sha3_256 = 97,\n\tOID_id_ecdsa_with_sha3_384 = 98,\n\tOID_id_ecdsa_with_sha3_512 = 99,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102,\n\tOID_id_ml_dsa_44 = 103,\n\tOID_id_ml_dsa_65 = 104,\n\tOID_id_ml_dsa_87 = 105,\n\tOID__NR = 106,\n};\n\nenum Opt_errors {\n\tOpt_errors_continue = 0,\n\tOpt_errors_panic = 1,\n};\n\nenum PIR_BIT {\n\tPIR_MDI = 8,\n\tPIR_MDO = 4,\n\tPIR_MMD = 2,\n\tPIR_MDC = 1,\n};\n\nenum PIR_BIT___2 {\n\tPIR_MDC___2 = 1,\n\tPIR_MMD___2 = 2,\n\tPIR_MDO___2 = 4,\n\tPIR_MDI___2 = 8,\n};\n\nenum PSR_BIT {\n\tPSR_LMON = 1,\n};\n\nenum RAVB_QUEUE {\n\tRAVB_BE = 0,\n\tRAVB_NC = 1,\n};\n\nenum RCR_BIT {\n\tRCR_EFFS = 1,\n\tRCR_ENCF = 2,\n\tRCR_ESF = 12,\n\tRCR_ETS0 = 16,\n\tRCR_ETS2 = 32,\n\tRCR_RFCL = 536805376,\n};\n\nenum RD_LEN_BIT {\n\tRD_RFL = 65535,\n\tRD_RBL = 4294901760,\n};\n\nenum RD_STS_BIT {\n\tRD_RACT = 2147483648,\n\tRD_RDLE = 1073741824,\n\tRD_RFP1 = 536870912,\n\tRD_RFP0 = 268435456,\n\tRD_RFE = 134217728,\n\tRD_RFS10 = 512,\n\tRD_RFS9 = 256,\n\tRD_RFS8 = 128,\n\tRD_RFS7 = 64,\n\tRD_RFS6 = 32,\n\tRD_RFS5 = 16,\n\tRD_RFS4 = 8,\n\tRD_RFS3 = 4,\n\tRD_RFS2 = 2,\n\tRD_RFS1 = 1,\n};\n\nenum REGION_TYPE {\n\tREGION_TYPE_UNUSED = 0,\n\tREGION_TYPE_SHARED_READ = 1,\n\tREGION_TYPE_SHARED_WRITE = 2,\n\tREGION_TYPE_EXCLUSIVE = 3,\n};\n\nenum RIC0_BIT {\n\tRIC0_FRE0 = 1,\n\tRIC0_FRE1 = 2,\n\tRIC0_FRE2 = 4,\n\tRIC0_FRE3 = 8,\n\tRIC0_FRE4 = 16,\n\tRIC0_FRE5 = 32,\n\tRIC0_FRE6 = 64,\n\tRIC0_FRE7 = 128,\n\tRIC0_FRE8 = 256,\n\tRIC0_FRE9 = 512,\n\tRIC0_FRE10 = 1024,\n\tRIC0_FRE11 = 2048,\n\tRIC0_FRE12 = 4096,\n\tRIC0_FRE13 = 8192,\n\tRIC0_FRE14 = 16384,\n\tRIC0_FRE15 = 32768,\n\tRIC0_FRE16 = 65536,\n\tRIC0_FRE17 = 131072,\n};\n\nenum RIC2_BIT {\n\tRIC2_QFE0 = 1,\n\tRIC2_QFE1 = 2,\n\tRIC2_QFE2 = 4,\n\tRIC2_QFE3 = 8,\n\tRIC2_QFE4 = 16,\n\tRIC2_QFE5 = 32,\n\tRIC2_QFE6 = 64,\n\tRIC2_QFE7 = 128,\n\tRIC2_QFE8 = 256,\n\tRIC2_QFE9 = 512,\n\tRIC2_QFE10 = 1024,\n\tRIC2_QFE11 = 2048,\n\tRIC2_QFE12 = 4096,\n\tRIC2_QFE13 = 8192,\n\tRIC2_QFE14 = 16384,\n\tRIC2_QFE15 = 32768,\n\tRIC2_QFE16 = 65536,\n\tRIC2_QFE17 = 131072,\n\tRIC2_RFFE = 2147483648,\n};\n\nenum RIS0_BIT {\n\tRIS0_FRF0 = 1,\n\tRIS0_FRF1 = 2,\n\tRIS0_FRF2 = 4,\n\tRIS0_FRF3 = 8,\n\tRIS0_FRF4 = 16,\n\tRIS0_FRF5 = 32,\n\tRIS0_FRF6 = 64,\n\tRIS0_FRF7 = 128,\n\tRIS0_FRF8 = 256,\n\tRIS0_FRF9 = 512,\n\tRIS0_FRF10 = 1024,\n\tRIS0_FRF11 = 2048,\n\tRIS0_FRF12 = 4096,\n\tRIS0_FRF13 = 8192,\n\tRIS0_FRF14 = 16384,\n\tRIS0_FRF15 = 32768,\n\tRIS0_FRF16 = 65536,\n\tRIS0_FRF17 = 131072,\n\tRIS0_RESERVED = 4294705152,\n};\n\nenum RIS2_BIT {\n\tRIS2_QFF0 = 1,\n\tRIS2_QFF1 = 2,\n\tRIS2_QFF2 = 4,\n\tRIS2_QFF3 = 8,\n\tRIS2_QFF4 = 16,\n\tRIS2_QFF5 = 32,\n\tRIS2_QFF6 = 64,\n\tRIS2_QFF7 = 128,\n\tRIS2_QFF8 = 256,\n\tRIS2_QFF9 = 512,\n\tRIS2_QFF10 = 1024,\n\tRIS2_QFF11 = 2048,\n\tRIS2_QFF12 = 4096,\n\tRIS2_QFF13 = 8192,\n\tRIS2_QFF14 = 16384,\n\tRIS2_QFF15 = 32768,\n\tRIS2_QFF16 = 65536,\n\tRIS2_QFF17 = 131072,\n\tRIS2_RFFF = 2147483648,\n\tRIS2_RESERVED = 2147221504,\n};\n\nenum RMCR_BIT {\n\tRMCR_RNC = 1,\n};\n\nenum RX_DS_CC_BIT {\n\tRX_DS = 4095,\n\tRX_TR = 4096,\n\tRX_EI = 8192,\n\tRX_PS = 49152,\n};\n\nenum S2MPU02_reg {\n\tS2MPU02_REG_ID = 0,\n\tS2MPU02_REG_INT1 = 1,\n\tS2MPU02_REG_INT2 = 2,\n\tS2MPU02_REG_INT3 = 3,\n\tS2MPU02_REG_INT1M = 4,\n\tS2MPU02_REG_INT2M = 5,\n\tS2MPU02_REG_INT3M = 6,\n\tS2MPU02_REG_ST1 = 7,\n\tS2MPU02_REG_ST2 = 8,\n\tS2MPU02_REG_PWRONSRC = 9,\n\tS2MPU02_REG_OFFSRC = 10,\n\tS2MPU02_REG_BU_CHG = 11,\n\tS2MPU02_REG_RTCCTRL = 12,\n\tS2MPU02_REG_PMCTRL1 = 13,\n\tS2MPU02_REG_RSVD1 = 14,\n\tS2MPU02_REG_RSVD2 = 15,\n\tS2MPU02_REG_RSVD3 = 16,\n\tS2MPU02_REG_RSVD4 = 17,\n\tS2MPU02_REG_RSVD5 = 18,\n\tS2MPU02_REG_RSVD6 = 19,\n\tS2MPU02_REG_RSVD7 = 20,\n\tS2MPU02_REG_WRSTEN = 21,\n\tS2MPU02_REG_RSVD8 = 22,\n\tS2MPU02_REG_RSVD9 = 23,\n\tS2MPU02_REG_RSVD10 = 24,\n\tS2MPU02_REG_B1CTRL1 = 25,\n\tS2MPU02_REG_B1CTRL2 = 26,\n\tS2MPU02_REG_B2CTRL1 = 27,\n\tS2MPU02_REG_B2CTRL2 = 28,\n\tS2MPU02_REG_B3CTRL1 = 29,\n\tS2MPU02_REG_B3CTRL2 = 30,\n\tS2MPU02_REG_B4CTRL1 = 31,\n\tS2MPU02_REG_B4CTRL2 = 32,\n\tS2MPU02_REG_B5CTRL1 = 33,\n\tS2MPU02_REG_B5CTRL2 = 34,\n\tS2MPU02_REG_B5CTRL3 = 35,\n\tS2MPU02_REG_B5CTRL4 = 36,\n\tS2MPU02_REG_B5CTRL5 = 37,\n\tS2MPU02_REG_B6CTRL1 = 38,\n\tS2MPU02_REG_B6CTRL2 = 39,\n\tS2MPU02_REG_B7CTRL1 = 40,\n\tS2MPU02_REG_B7CTRL2 = 41,\n\tS2MPU02_REG_RAMP1 = 42,\n\tS2MPU02_REG_RAMP2 = 43,\n\tS2MPU02_REG_L1CTRL = 44,\n\tS2MPU02_REG_L2CTRL1 = 45,\n\tS2MPU02_REG_L2CTRL2 = 46,\n\tS2MPU02_REG_L2CTRL3 = 47,\n\tS2MPU02_REG_L2CTRL4 = 48,\n\tS2MPU02_REG_L3CTRL = 49,\n\tS2MPU02_REG_L4CTRL = 50,\n\tS2MPU02_REG_L5CTRL = 51,\n\tS2MPU02_REG_L6CTRL = 52,\n\tS2MPU02_REG_L7CTRL = 53,\n\tS2MPU02_REG_L8CTRL = 54,\n\tS2MPU02_REG_L9CTRL = 55,\n\tS2MPU02_REG_L10CTRL = 56,\n\tS2MPU02_REG_L11CTRL = 57,\n\tS2MPU02_REG_L12CTRL = 58,\n\tS2MPU02_REG_L13CTRL = 59,\n\tS2MPU02_REG_L14CTRL = 60,\n\tS2MPU02_REG_L15CTRL = 61,\n\tS2MPU02_REG_L16CTRL = 62,\n\tS2MPU02_REG_L17CTRL = 63,\n\tS2MPU02_REG_L18CTRL = 64,\n\tS2MPU02_REG_L19CTRL = 65,\n\tS2MPU02_REG_L20CTRL = 66,\n\tS2MPU02_REG_L21CTRL = 67,\n\tS2MPU02_REG_L22CTRL = 68,\n\tS2MPU02_REG_L23CTRL = 69,\n\tS2MPU02_REG_L24CTRL = 70,\n\tS2MPU02_REG_L25CTRL = 71,\n\tS2MPU02_REG_L26CTRL = 72,\n\tS2MPU02_REG_L27CTRL = 73,\n\tS2MPU02_REG_L28CTRL = 74,\n\tS2MPU02_REG_LDODSCH1 = 75,\n\tS2MPU02_REG_LDODSCH2 = 76,\n\tS2MPU02_REG_LDODSCH3 = 77,\n\tS2MPU02_REG_LDODSCH4 = 78,\n\tS2MPU02_REG_SELMIF = 79,\n\tS2MPU02_REG_RSVD11 = 80,\n\tS2MPU02_REG_RSVD12 = 81,\n\tS2MPU02_REG_RSVD13 = 82,\n\tS2MPU02_REG_DVSSEL = 83,\n\tS2MPU02_REG_DVSPTR = 84,\n\tS2MPU02_REG_DVSDATA = 85,\n};\n\nenum S2MPU02_regulators {\n\tS2MPU02_LDO1 = 0,\n\tS2MPU02_LDO2 = 1,\n\tS2MPU02_LDO3 = 2,\n\tS2MPU02_LDO4 = 3,\n\tS2MPU02_LDO5 = 4,\n\tS2MPU02_LDO6 = 5,\n\tS2MPU02_LDO7 = 6,\n\tS2MPU02_LDO8 = 7,\n\tS2MPU02_LDO9 = 8,\n\tS2MPU02_LDO10 = 9,\n\tS2MPU02_LDO11 = 10,\n\tS2MPU02_LDO12 = 11,\n\tS2MPU02_LDO13 = 12,\n\tS2MPU02_LDO14 = 13,\n\tS2MPU02_LDO15 = 14,\n\tS2MPU02_LDO16 = 15,\n\tS2MPU02_LDO17 = 16,\n\tS2MPU02_LDO18 = 17,\n\tS2MPU02_LDO19 = 18,\n\tS2MPU02_LDO20 = 19,\n\tS2MPU02_LDO21 = 20,\n\tS2MPU02_LDO22 = 21,\n\tS2MPU02_LDO23 = 22,\n\tS2MPU02_LDO24 = 23,\n\tS2MPU02_LDO25 = 24,\n\tS2MPU02_LDO26 = 25,\n\tS2MPU02_LDO27 = 26,\n\tS2MPU02_LDO28 = 27,\n\tS2MPU02_BUCK1 = 28,\n\tS2MPU02_BUCK2 = 29,\n\tS2MPU02_BUCK3 = 30,\n\tS2MPU02_BUCK4 = 31,\n\tS2MPU02_BUCK5 = 32,\n\tS2MPU02_BUCK6 = 33,\n\tS2MPU02_BUCK7 = 34,\n\tS2MPU02_REGULATOR_MAX = 35,\n};\n\nenum S2MPU05_reg {\n\tS2MPU05_REG_ID = 0,\n\tS2MPU05_REG_INT1 = 1,\n\tS2MPU05_REG_INT2 = 2,\n\tS2MPU05_REG_INT3 = 3,\n\tS2MPU05_REG_INT1M = 4,\n\tS2MPU05_REG_INT2M = 5,\n\tS2MPU05_REG_INT3M = 6,\n\tS2MPU05_REG_ST1 = 7,\n\tS2MPU05_REG_ST2 = 8,\n\tS2MPU05_REG_PWRONSRC = 9,\n\tS2MPU05_REG_OFFSRC = 10,\n\tS2MPU05_REG_BU_CHG = 11,\n\tS2MPU05_REG_RTC_BUF = 12,\n\tS2MPU05_REG_CTRL1 = 13,\n\tS2MPU05_REG_CTRL2 = 14,\n\tS2MPU05_REG_ETC_TEST = 15,\n\tS2MPU05_REG_OTP_ADRL = 16,\n\tS2MPU05_REG_OTP_ADRH = 17,\n\tS2MPU05_REG_OTP_DATA = 18,\n\tS2MPU05_REG_MON1SEL = 19,\n\tS2MPU05_REG_MON2SEL = 20,\n\tS2MPU05_REG_CTRL3 = 21,\n\tS2MPU05_REG_ETC_OTP = 22,\n\tS2MPU05_REG_UVLO = 23,\n\tS2MPU05_REG_TIME_CTRL1 = 24,\n\tS2MPU05_REG_TIME_CTRL2 = 25,\n\tS2MPU05_REG_B1CTRL1 = 26,\n\tS2MPU05_REG_B1CTRL2 = 27,\n\tS2MPU05_REG_B2CTRL1 = 28,\n\tS2MPU05_REG_B2CTRL2 = 29,\n\tS2MPU05_REG_B2CTRL3 = 30,\n\tS2MPU05_REG_B2CTRL4 = 31,\n\tS2MPU05_REG_B3CTRL1 = 32,\n\tS2MPU05_REG_B3CTRL2 = 33,\n\tS2MPU05_REG_B3CTRL3 = 34,\n\tS2MPU05_REG_B4CTRL1 = 35,\n\tS2MPU05_REG_B4CTRL2 = 36,\n\tS2MPU05_REG_B5CTRL1 = 37,\n\tS2MPU05_REG_B5CTRL2 = 38,\n\tS2MPU05_REG_BUCK_RAMP = 39,\n\tS2MPU05_REG_LDO_DVS1 = 40,\n\tS2MPU05_REG_LDO_DVS9 = 41,\n\tS2MPU05_REG_LDO_DVS10 = 42,\n\tS2MPU05_REG_L1CTRL = 43,\n\tS2MPU05_REG_L2CTRL = 44,\n\tS2MPU05_REG_L3CTRL = 45,\n\tS2MPU05_REG_L4CTRL = 46,\n\tS2MPU05_REG_L5CTRL = 47,\n\tS2MPU05_REG_L6CTRL = 48,\n\tS2MPU05_REG_L7CTRL = 49,\n\tS2MPU05_REG_L8CTRL = 50,\n\tS2MPU05_REG_L9CTRL1 = 51,\n\tS2MPU05_REG_L9CTRL2 = 52,\n\tS2MPU05_REG_L10CTRL = 53,\n\tS2MPU05_REG_L11CTRL1 = 54,\n\tS2MPU05_REG_L11CTRL2 = 55,\n\tS2MPU05_REG_L12CTRL = 56,\n\tS2MPU05_REG_L13CTRL = 57,\n\tS2MPU05_REG_L14CTRL = 58,\n\tS2MPU05_REG_L15CTRL = 59,\n\tS2MPU05_REG_L16CTRL = 60,\n\tS2MPU05_REG_L17CTRL1 = 61,\n\tS2MPU05_REG_L17CTRL2 = 62,\n\tS2MPU05_REG_L18CTRL1 = 63,\n\tS2MPU05_REG_L18CTRL2 = 64,\n\tS2MPU05_REG_L19CTRL = 65,\n\tS2MPU05_REG_L20CTRL = 66,\n\tS2MPU05_REG_L21CTRL = 67,\n\tS2MPU05_REG_L22CTRL = 68,\n\tS2MPU05_REG_L23CTRL = 69,\n\tS2MPU05_REG_L24CTRL = 70,\n\tS2MPU05_REG_L25CTRL = 71,\n\tS2MPU05_REG_L26CTRL = 72,\n\tS2MPU05_REG_L27CTRL = 73,\n\tS2MPU05_REG_L28CTRL = 74,\n\tS2MPU05_REG_L29CTRL = 75,\n\tS2MPU05_REG_L30CTRL = 76,\n\tS2MPU05_REG_L31CTRL = 77,\n\tS2MPU05_REG_L32CTRL = 78,\n\tS2MPU05_REG_L33CTRL = 79,\n\tS2MPU05_REG_L34CTRL = 80,\n\tS2MPU05_REG_L35CTRL = 81,\n\tS2MPU05_REG_LDO_DSCH1 = 82,\n\tS2MPU05_REG_LDO_DSCH2 = 83,\n\tS2MPU05_REG_LDO_DSCH3 = 84,\n\tS2MPU05_REG_LDO_DSCH4 = 85,\n\tS2MPU05_REG_LDO_DSCH5 = 86,\n\tS2MPU05_REG_LDO_CTRL1 = 87,\n\tS2MPU05_REG_LDO_CTRL2 = 88,\n\tS2MPU05_REG_TCXO_CTRL = 89,\n\tS2MPU05_REG_SELMIF = 90,\n};\n\nenum S2MPU05_regulators {\n\tS2MPU05_LDO1 = 0,\n\tS2MPU05_LDO2 = 1,\n\tS2MPU05_LDO3 = 2,\n\tS2MPU05_LDO4 = 3,\n\tS2MPU05_LDO5 = 4,\n\tS2MPU05_LDO6 = 5,\n\tS2MPU05_LDO7 = 6,\n\tS2MPU05_LDO8 = 7,\n\tS2MPU05_LDO9 = 8,\n\tS2MPU05_LDO10 = 9,\n\tS2MPU05_LDO11 = 10,\n\tS2MPU05_LDO12 = 11,\n\tS2MPU05_LDO13 = 12,\n\tS2MPU05_LDO14 = 13,\n\tS2MPU05_LDO15 = 14,\n\tS2MPU05_LDO16 = 15,\n\tS2MPU05_LDO17 = 16,\n\tS2MPU05_LDO18 = 17,\n\tS2MPU05_LDO19 = 18,\n\tS2MPU05_LDO20 = 19,\n\tS2MPU05_LDO21 = 20,\n\tS2MPU05_LDO22 = 21,\n\tS2MPU05_LDO23 = 22,\n\tS2MPU05_LDO24 = 23,\n\tS2MPU05_LDO25 = 24,\n\tS2MPU05_LDO26 = 25,\n\tS2MPU05_LDO27 = 26,\n\tS2MPU05_LDO28 = 27,\n\tS2MPU05_LDO29 = 28,\n\tS2MPU05_LDO30 = 29,\n\tS2MPU05_LDO31 = 30,\n\tS2MPU05_LDO32 = 31,\n\tS2MPU05_LDO33 = 32,\n\tS2MPU05_LDO34 = 33,\n\tS2MPU05_LDO35 = 34,\n\tS2MPU05_BUCK1 = 35,\n\tS2MPU05_BUCK2 = 36,\n\tS2MPU05_BUCK3 = 37,\n\tS2MPU05_BUCK4 = 38,\n\tS2MPU05_BUCK5 = 39,\n\tS2MPU05_REGULATOR_MAX = 40,\n};\n\nenum SCI_CLKS {\n\tSCI_FCK = 0,\n\tSCI_SCK = 1,\n\tSCI_BRG_INT = 2,\n\tSCI_SCIF_CLK = 3,\n\tSCI_FCK_DIV4 = 4,\n\tSCI_FCK_DIV16 = 5,\n\tSCI_FCK_DIV64 = 6,\n\tSCI_NUM_CLKS = 7,\n};\n\nenum SCI_PORT_TYPE {\n\tRSCI_PORT_SCIF16 = 128,\n\tRSCI_PORT_SCIF32 = 129,\n};\n\nenum SG2000_POWER_DOMAIN {\n\tVDD18A_EPHY = 0,\n\tVDD18A_MIPI = 1,\n\tVDDIO18_1 = 2,\n\tVDDIO_EMMC = 3,\n\tVDDIO_RTC = 4,\n\tVDDIO_SD0 = 5,\n\tVDDIO_SD1 = 6,\n\tVDDIO_VIVO = 7,\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum TCCR_BIT {\n\tTCCR_TSRQ0 = 1,\n\tTCCR_TSRQ1 = 2,\n\tTCCR_TSRQ2 = 4,\n\tTCCR_TSRQ3 = 8,\n\tTCCR_TFEN = 256,\n\tTCCR_TFR = 512,\n};\n\nenum TD_STS_BIT {\n\tTD_TACT = 2147483648,\n\tTD_TDLE = 1073741824,\n\tTD_TFP1 = 536870912,\n\tTD_TFP0 = 268435456,\n\tTD_TFE = 134217728,\n\tTD_TWBI = 67108864,\n};\n\nenum TFA2_BIT {\n\tTFA2_TSV = 65535,\n\tTFA2_TST = 67043328,\n};\n\nenum TGC_BIT {\n\tTGC_TSM0 = 1,\n\tTGC_TSM1 = 2,\n\tTGC_TSM2 = 4,\n\tTGC_TSM3 = 8,\n\tTGC_TQP = 48,\n\tTGC_TQP_NONAVB = 0,\n\tTGC_TQP_AVBMODE1 = 16,\n\tTGC_TQP_AVBMODE2 = 48,\n\tTGC_TBD0 = 768,\n\tTGC_TBD1 = 12288,\n\tTGC_TBD2 = 196608,\n\tTGC_TBD3 = 3145728,\n};\n\nenum TIC_BIT {\n\tTIC_FTE0 = 1,\n\tTIC_FTE1 = 2,\n\tTIC_TFUE = 256,\n\tTIC_TFWE = 512,\n};\n\nenum TIS_BIT {\n\tTIS_FTF0 = 1,\n\tTIS_FTF1 = 2,\n\tTIS_TFUF = 256,\n\tTIS_TFWF = 512,\n\tTIS_RESERVED = 4293980400,\n};\n\nenum TPAUSER_BIT {\n\tTPAUSER_TPAUSE = 65535,\n\tTPAUSER_UNLIMITED = 0,\n};\n\nenum TPM_OPS_FLAGS {\n\tTPM_OPS_AUTO_STARTUP = 1,\n};\n\nenum TRSCER_BIT {\n\tTRSCER_CNDCE = 2048,\n\tTRSCER_DLCCE = 1024,\n\tTRSCER_CDCE = 512,\n\tTRSCER_TROCE = 256,\n\tTRSCER_RMAFCE = 128,\n\tTRSCER_RRFCE = 16,\n\tTRSCER_RTLFCE = 8,\n\tTRSCER_RTSFCE = 4,\n\tTRSCER_PRECE = 2,\n\tTRSCER_CERFCE = 1,\n};\n\nenum TSR_BIT {\n\tTSR_CCS0 = 3,\n\tTSR_CCS1 = 12,\n\tTSR_TFFL = 1792,\n};\n\nenum TSU_ADSBSY_BIT {\n\tTSU_ADSBSY_0 = 1,\n};\n\nenum TSU_FWSLC_BIT {\n\tTSU_FWSLC_POSTENU = 8192,\n\tTSU_FWSLC_POSTENL = 4096,\n\tTSU_FWSLC_CAMSEL03 = 128,\n\tTSU_FWSLC_CAMSEL02 = 64,\n\tTSU_FWSLC_CAMSEL01 = 32,\n\tTSU_FWSLC_CAMSEL00 = 16,\n\tTSU_FWSLC_CAMSEL13 = 8,\n\tTSU_FWSLC_CAMSEL12 = 4,\n\tTSU_FWSLC_CAMSEL11 = 2,\n\tTSU_FWSLC_CAMSEL10 = 1,\n};\n\nenum TX_DS_TAGL_BIT {\n\tTX_DS = 4095,\n\tTX_TAGL = 61440,\n};\n\nenum TX_FS_TAGL_BIT {\n\tTX_DS___2 = 4095,\n\tTX_TAGL___2 = 61440,\n};\n\nenum TX_TAGH_TSR_BIT {\n\tTX_TAGH = 63,\n\tTX_TSR = 64,\n};\n\nenum UART_TX_FLAGS {\n\tUART_TX_NOSTOP = 1,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nenum _MR_CRASH_BUF_STATUS {\n\tMR_CRASH_BUF_TURN_OFF = 0,\n\tMR_CRASH_BUF_TURN_ON = 1,\n};\n\nenum __kvm_host_smccc_func {\n\t__KVM_HOST_SMCCC_FUNC___pkvm_init = 1,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_create_private_mapping = 2,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_cpu_set_vector = 3,\n\t__KVM_HOST_SMCCC_FUNC___kvm_enable_ssbs = 4,\n\t__KVM_HOST_SMCCC_FUNC___vgic_v3_init_lrs = 5,\n\t__KVM_HOST_SMCCC_FUNC___vgic_v3_get_gic_config = 6,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize = 7,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_share_hyp = 8,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_unshare_hyp = 9,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_share_guest = 10,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_unshare_guest = 11,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_relax_perms_guest = 12,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_wrprotect_guest = 13,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_test_clear_young_guest = 14,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_host_mkyoung_guest = 15,\n\t__KVM_HOST_SMCCC_FUNC___kvm_adjust_pc = 16,\n\t__KVM_HOST_SMCCC_FUNC___kvm_vcpu_run = 17,\n\t__KVM_HOST_SMCCC_FUNC___kvm_flush_vm_context = 18,\n\t__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa = 19,\n\t__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa_nsh = 20,\n\t__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid = 21,\n\t__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_range = 22,\n\t__KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context = 23,\n\t__KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff = 24,\n\t__KVM_HOST_SMCCC_FUNC___vgic_v3_save_aprs = 25,\n\t__KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs = 26,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_reserve_vm = 27,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_unreserve_vm = 28,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_init_vm = 29,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_init_vcpu = 30,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_teardown_vm = 31,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_vcpu_load = 32,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_vcpu_put = 33,\n\t__KVM_HOST_SMCCC_FUNC___pkvm_tlb_flush_vmid = 34,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _dsm_op_index {\n\tHNS_OP_RESET_FUNC = 1,\n\tHNS_OP_SERDES_LP_FUNC = 2,\n\tHNS_OP_LED_SET_FUNC = 3,\n\tHNS_OP_GET_PORT_TYPE_FUNC = 4,\n\tHNS_OP_GET_SFP_STAT_FUNC = 5,\n\tHNS_OP_LOCATE_LED_SET_FUNC = 6,\n};\n\nenum _dsm_rst_type {\n\tHNS_DSAF_RESET_FUNC = 1,\n\tHNS_PPE_RESET_FUNC = 2,\n\tHNS_XGE_RESET_FUNC = 4,\n\tHNS_GE_RESET_FUNC = 5,\n\tHNS_DSAF_CHN_RESET_FUNC = 6,\n\tHNS_ROCE_RESET_FUNC = 7,\n};\n\nenum _pmux_input {\n\tSMUX_INDEX = 0,\n\tPLL_INDEX = 1,\n\tACD_INDEX = 2,\n\tALT_INDEX = 3,\n\tNUM_OF_PMUX_INPUTS = 4,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_ACCOUNT = 13,\n\t_SLAB_NO_USER_FLAGS = 14,\n\t_SLAB_RECLAIM_ACCOUNT = 15,\n\t_SLAB_OBJECT_POISON = 16,\n\t_SLAB_CMPXCHG_DOUBLE = 17,\n\t_SLAB_NO_OBJ_EXT = 18,\n\t_SLAB_OBJ_EXT_IN_OBJ = 19,\n\t_SLAB_FLAGS_LAST_BIT = 20,\n};\n\nenum aarch32_map {\n\tAA32_MAP_VECTORS = 0,\n\tAA32_MAP_SIGPAGE = 1,\n\tAA32_MAP_VDSO = 2,\n};\n\nenum aarch64_insn_adr_type {\n\tAARCH64_INSN_ADR_TYPE_ADRP = 0,\n\tAARCH64_INSN_ADR_TYPE_ADR = 1,\n};\n\nenum aarch64_insn_adsb_type {\n\tAARCH64_INSN_ADSB_ADD = 0,\n\tAARCH64_INSN_ADSB_SUB = 1,\n\tAARCH64_INSN_ADSB_ADD_SETFLAGS = 2,\n\tAARCH64_INSN_ADSB_SUB_SETFLAGS = 3,\n};\n\nenum aarch64_insn_bitfield_type {\n\tAARCH64_INSN_BITFIELD_MOVE = 0,\n\tAARCH64_INSN_BITFIELD_MOVE_UNSIGNED = 1,\n\tAARCH64_INSN_BITFIELD_MOVE_SIGNED = 2,\n};\n\nenum aarch64_insn_branch_type {\n\tAARCH64_INSN_BRANCH_NOLINK = 0,\n\tAARCH64_INSN_BRANCH_LINK = 1,\n\tAARCH64_INSN_BRANCH_RETURN = 2,\n\tAARCH64_INSN_BRANCH_COMP_ZERO = 3,\n\tAARCH64_INSN_BRANCH_COMP_NONZERO = 4,\n};\n\nenum aarch64_insn_condition {\n\tAARCH64_INSN_COND_EQ = 0,\n\tAARCH64_INSN_COND_NE = 1,\n\tAARCH64_INSN_COND_CS = 2,\n\tAARCH64_INSN_COND_CC = 3,\n\tAARCH64_INSN_COND_MI = 4,\n\tAARCH64_INSN_COND_PL = 5,\n\tAARCH64_INSN_COND_VS = 6,\n\tAARCH64_INSN_COND_VC = 7,\n\tAARCH64_INSN_COND_HI = 8,\n\tAARCH64_INSN_COND_LS = 9,\n\tAARCH64_INSN_COND_GE = 10,\n\tAARCH64_INSN_COND_LT = 11,\n\tAARCH64_INSN_COND_GT = 12,\n\tAARCH64_INSN_COND_LE = 13,\n\tAARCH64_INSN_COND_AL = 14,\n};\n\nenum aarch64_insn_data1_type {\n\tAARCH64_INSN_DATA1_REVERSE_16 = 0,\n\tAARCH64_INSN_DATA1_REVERSE_32 = 1,\n\tAARCH64_INSN_DATA1_REVERSE_64 = 2,\n};\n\nenum aarch64_insn_data2_type {\n\tAARCH64_INSN_DATA2_UDIV = 0,\n\tAARCH64_INSN_DATA2_SDIV = 1,\n\tAARCH64_INSN_DATA2_LSLV = 2,\n\tAARCH64_INSN_DATA2_LSRV = 3,\n\tAARCH64_INSN_DATA2_ASRV = 4,\n\tAARCH64_INSN_DATA2_RORV = 5,\n};\n\nenum aarch64_insn_data3_type {\n\tAARCH64_INSN_DATA3_MADD = 0,\n\tAARCH64_INSN_DATA3_MSUB = 1,\n};\n\nenum aarch64_insn_hint_cr_op {\n\tAARCH64_INSN_HINT_NOP = 0,\n\tAARCH64_INSN_HINT_YIELD = 32,\n\tAARCH64_INSN_HINT_WFE = 64,\n\tAARCH64_INSN_HINT_WFI = 96,\n\tAARCH64_INSN_HINT_SEV = 128,\n\tAARCH64_INSN_HINT_SEVL = 160,\n\tAARCH64_INSN_HINT_XPACLRI = 224,\n\tAARCH64_INSN_HINT_PACIA_1716 = 256,\n\tAARCH64_INSN_HINT_PACIB_1716 = 320,\n\tAARCH64_INSN_HINT_AUTIA_1716 = 384,\n\tAARCH64_INSN_HINT_AUTIB_1716 = 448,\n\tAARCH64_INSN_HINT_PACIAZ = 768,\n\tAARCH64_INSN_HINT_PACIASP = 800,\n\tAARCH64_INSN_HINT_PACIBZ = 832,\n\tAARCH64_INSN_HINT_PACIBSP = 864,\n\tAARCH64_INSN_HINT_AUTIAZ = 896,\n\tAARCH64_INSN_HINT_AUTIASP = 928,\n\tAARCH64_INSN_HINT_AUTIBZ = 960,\n\tAARCH64_INSN_HINT_AUTIBSP = 992,\n\tAARCH64_INSN_HINT_ESB = 512,\n\tAARCH64_INSN_HINT_PSB = 544,\n\tAARCH64_INSN_HINT_TSB = 576,\n\tAARCH64_INSN_HINT_CSDB = 640,\n\tAARCH64_INSN_HINT_CLEARBHB = 704,\n\tAARCH64_INSN_HINT_BTI = 1024,\n\tAARCH64_INSN_HINT_BTIC = 1088,\n\tAARCH64_INSN_HINT_BTIJ = 1152,\n\tAARCH64_INSN_HINT_BTIJC = 1216,\n};\n\nenum aarch64_insn_imm_type {\n\tAARCH64_INSN_IMM_ADR = 0,\n\tAARCH64_INSN_IMM_26 = 1,\n\tAARCH64_INSN_IMM_19 = 2,\n\tAARCH64_INSN_IMM_16 = 3,\n\tAARCH64_INSN_IMM_14 = 4,\n\tAARCH64_INSN_IMM_12 = 5,\n\tAARCH64_INSN_IMM_9 = 6,\n\tAARCH64_INSN_IMM_7 = 7,\n\tAARCH64_INSN_IMM_6 = 8,\n\tAARCH64_INSN_IMM_S = 9,\n\tAARCH64_INSN_IMM_R = 10,\n\tAARCH64_INSN_IMM_N = 11,\n\tAARCH64_INSN_IMM_MAX = 12,\n};\n\nenum aarch64_insn_ldst_type {\n\tAARCH64_INSN_LDST_LOAD_REG_OFFSET = 0,\n\tAARCH64_INSN_LDST_STORE_REG_OFFSET = 1,\n\tAARCH64_INSN_LDST_LOAD_IMM_OFFSET = 2,\n\tAARCH64_INSN_LDST_STORE_IMM_OFFSET = 3,\n\tAARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX = 4,\n\tAARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX = 5,\n\tAARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX = 6,\n\tAARCH64_INSN_LDST_STORE_PAIR_POST_INDEX = 7,\n\tAARCH64_INSN_LDST_LOAD_ACQ = 8,\n\tAARCH64_INSN_LDST_LOAD_EX = 9,\n\tAARCH64_INSN_LDST_LOAD_ACQ_EX = 10,\n\tAARCH64_INSN_LDST_STORE_REL = 11,\n\tAARCH64_INSN_LDST_STORE_EX = 12,\n\tAARCH64_INSN_LDST_STORE_REL_EX = 13,\n\tAARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET = 14,\n\tAARCH64_INSN_LDST_SIGNED_LOAD_REG_OFFSET = 15,\n};\n\nenum aarch64_insn_logic_type {\n\tAARCH64_INSN_LOGIC_AND = 0,\n\tAARCH64_INSN_LOGIC_BIC = 1,\n\tAARCH64_INSN_LOGIC_ORR = 2,\n\tAARCH64_INSN_LOGIC_ORN = 3,\n\tAARCH64_INSN_LOGIC_EOR = 4,\n\tAARCH64_INSN_LOGIC_EON = 5,\n\tAARCH64_INSN_LOGIC_AND_SETFLAGS = 6,\n\tAARCH64_INSN_LOGIC_BIC_SETFLAGS = 7,\n};\n\nenum aarch64_insn_mb_type {\n\tAARCH64_INSN_MB_SY = 0,\n\tAARCH64_INSN_MB_ST = 1,\n\tAARCH64_INSN_MB_LD = 2,\n\tAARCH64_INSN_MB_ISH = 3,\n\tAARCH64_INSN_MB_ISHST = 4,\n\tAARCH64_INSN_MB_ISHLD = 5,\n\tAARCH64_INSN_MB_NSH = 6,\n\tAARCH64_INSN_MB_NSHST = 7,\n\tAARCH64_INSN_MB_NSHLD = 8,\n\tAARCH64_INSN_MB_OSH = 9,\n\tAARCH64_INSN_MB_OSHST = 10,\n\tAARCH64_INSN_MB_OSHLD = 11,\n};\n\nenum aarch64_insn_mem_atomic_op {\n\tAARCH64_INSN_MEM_ATOMIC_ADD = 0,\n\tAARCH64_INSN_MEM_ATOMIC_CLR = 1,\n\tAARCH64_INSN_MEM_ATOMIC_EOR = 2,\n\tAARCH64_INSN_MEM_ATOMIC_SET = 3,\n\tAARCH64_INSN_MEM_ATOMIC_SWP = 4,\n};\n\nenum aarch64_insn_mem_order_type {\n\tAARCH64_INSN_MEM_ORDER_NONE = 0,\n\tAARCH64_INSN_MEM_ORDER_ACQ = 1,\n\tAARCH64_INSN_MEM_ORDER_REL = 2,\n\tAARCH64_INSN_MEM_ORDER_ACQREL = 3,\n};\n\nenum aarch64_insn_movewide_type {\n\tAARCH64_INSN_MOVEWIDE_ZERO = 0,\n\tAARCH64_INSN_MOVEWIDE_KEEP = 1,\n\tAARCH64_INSN_MOVEWIDE_INVERSE = 2,\n};\n\nenum aarch64_insn_movw_imm_type {\n\tAARCH64_INSN_IMM_MOVNZ = 0,\n\tAARCH64_INSN_IMM_MOVKZ = 1,\n};\n\nenum aarch64_insn_register {\n\tAARCH64_INSN_REG_0 = 0,\n\tAARCH64_INSN_REG_1 = 1,\n\tAARCH64_INSN_REG_2 = 2,\n\tAARCH64_INSN_REG_3 = 3,\n\tAARCH64_INSN_REG_4 = 4,\n\tAARCH64_INSN_REG_5 = 5,\n\tAARCH64_INSN_REG_6 = 6,\n\tAARCH64_INSN_REG_7 = 7,\n\tAARCH64_INSN_REG_8 = 8,\n\tAARCH64_INSN_REG_9 = 9,\n\tAARCH64_INSN_REG_10 = 10,\n\tAARCH64_INSN_REG_11 = 11,\n\tAARCH64_INSN_REG_12 = 12,\n\tAARCH64_INSN_REG_13 = 13,\n\tAARCH64_INSN_REG_14 = 14,\n\tAARCH64_INSN_REG_15 = 15,\n\tAARCH64_INSN_REG_16 = 16,\n\tAARCH64_INSN_REG_17 = 17,\n\tAARCH64_INSN_REG_18 = 18,\n\tAARCH64_INSN_REG_19 = 19,\n\tAARCH64_INSN_REG_20 = 20,\n\tAARCH64_INSN_REG_21 = 21,\n\tAARCH64_INSN_REG_22 = 22,\n\tAARCH64_INSN_REG_23 = 23,\n\tAARCH64_INSN_REG_24 = 24,\n\tAARCH64_INSN_REG_25 = 25,\n\tAARCH64_INSN_REG_26 = 26,\n\tAARCH64_INSN_REG_27 = 27,\n\tAARCH64_INSN_REG_28 = 28,\n\tAARCH64_INSN_REG_29 = 29,\n\tAARCH64_INSN_REG_FP = 29,\n\tAARCH64_INSN_REG_30 = 30,\n\tAARCH64_INSN_REG_LR = 30,\n\tAARCH64_INSN_REG_ZR = 31,\n\tAARCH64_INSN_REG_SP = 31,\n};\n\nenum aarch64_insn_register_type {\n\tAARCH64_INSN_REGTYPE_RT = 0,\n\tAARCH64_INSN_REGTYPE_RN = 1,\n\tAARCH64_INSN_REGTYPE_RT2 = 2,\n\tAARCH64_INSN_REGTYPE_RM = 3,\n\tAARCH64_INSN_REGTYPE_RD = 4,\n\tAARCH64_INSN_REGTYPE_RA = 5,\n\tAARCH64_INSN_REGTYPE_RS = 6,\n};\n\nenum aarch64_insn_size_type {\n\tAARCH64_INSN_SIZE_8 = 0,\n\tAARCH64_INSN_SIZE_16 = 1,\n\tAARCH64_INSN_SIZE_32 = 2,\n\tAARCH64_INSN_SIZE_64 = 3,\n};\n\nenum aarch64_insn_special_register {\n\tAARCH64_INSN_SPCLREG_SPSR_EL1 = 49664,\n\tAARCH64_INSN_SPCLREG_ELR_EL1 = 49665,\n\tAARCH64_INSN_SPCLREG_SP_EL0 = 49672,\n\tAARCH64_INSN_SPCLREG_SPSEL = 49680,\n\tAARCH64_INSN_SPCLREG_CURRENTEL = 49682,\n\tAARCH64_INSN_SPCLREG_DAIF = 55825,\n\tAARCH64_INSN_SPCLREG_NZCV = 55824,\n\tAARCH64_INSN_SPCLREG_FPCR = 55840,\n\tAARCH64_INSN_SPCLREG_DSPSR_EL0 = 55848,\n\tAARCH64_INSN_SPCLREG_DLR_EL0 = 55849,\n\tAARCH64_INSN_SPCLREG_SPSR_EL2 = 57856,\n\tAARCH64_INSN_SPCLREG_ELR_EL2 = 57857,\n\tAARCH64_INSN_SPCLREG_SP_EL1 = 57864,\n\tAARCH64_INSN_SPCLREG_SPSR_INQ = 57880,\n\tAARCH64_INSN_SPCLREG_SPSR_ABT = 57881,\n\tAARCH64_INSN_SPCLREG_SPSR_UND = 57882,\n\tAARCH64_INSN_SPCLREG_SPSR_FIQ = 57883,\n\tAARCH64_INSN_SPCLREG_SPSR_EL3 = 61952,\n\tAARCH64_INSN_SPCLREG_ELR_EL3 = 61953,\n\tAARCH64_INSN_SPCLREG_SP_EL2 = 61968,\n};\n\nenum aarch64_insn_system_register {\n\tAARCH64_INSN_SYSREG_TPIDR_EL1 = 18052,\n\tAARCH64_INSN_SYSREG_TPIDR_EL2 = 26242,\n\tAARCH64_INSN_SYSREG_SP_EL0 = 16904,\n};\n\nenum aarch64_insn_variant {\n\tAARCH64_INSN_VARIANT_32BIT = 0,\n\tAARCH64_INSN_VARIANT_64BIT = 1,\n};\n\nenum aarch64_regset {\n\tREGSET_GPR = 0,\n\tREGSET_FPR = 1,\n\tREGSET_TLS = 2,\n\tREGSET_HW_BREAK = 3,\n\tREGSET_HW_WATCH = 4,\n\tREGSET_FPMR = 5,\n\tREGSET_SYSTEM_CALL = 6,\n\tREGSET_SVE = 7,\n\tREGSET_SSVE = 8,\n\tREGSET_ZA = 9,\n\tREGSET_ZT = 10,\n\tREGSET_PAC_MASK = 11,\n\tREGSET_PAC_ENABLED_KEYS = 12,\n\tREGSET_TAGGED_ADDR_CTRL = 13,\n\tREGSET_POE = 14,\n\tREGSET_GCS = 15,\n};\n\nenum aarch64_reloc_op {\n\tRELOC_OP_NONE = 0,\n\tRELOC_OP_ABS = 1,\n\tRELOC_OP_PREL = 2,\n\tRELOC_OP_PAGE = 3,\n};\n\nenum access_coordinate_class {\n\tACCESS_COORDINATE_LOCAL = 0,\n\tACCESS_COORDINATE_CPU = 1,\n\tACCESS_COORDINATE_MAX = 2,\n};\n\nenum acpi_attr_enum {\n\tACPI_ATTR_LABEL_SHOW = 0,\n\tACPI_ATTR_INDEX_SHOW = 1,\n};\n\nenum acpi_bridge_type {\n\tACPI_BRIDGE_TYPE_PCIE = 1,\n\tACPI_BRIDGE_TYPE_CXL = 2,\n};\n\nenum acpi_bus_device_type {\n\tACPI_BUS_TYPE_DEVICE = 0,\n\tACPI_BUS_TYPE_POWER = 1,\n\tACPI_BUS_TYPE_PROCESSOR = 2,\n\tACPI_BUS_TYPE_THERMAL = 3,\n\tACPI_BUS_TYPE_POWER_BUTTON = 4,\n\tACPI_BUS_TYPE_SLEEP_BUTTON = 5,\n\tACPI_BUS_TYPE_ECDT_EC = 6,\n\tACPI_BUS_DEVICE_TYPE_COUNT = 7,\n};\n\nenum acpi_cdat_type {\n\tACPI_CDAT_TYPE_DSMAS = 0,\n\tACPI_CDAT_TYPE_DSLBIS = 1,\n\tACPI_CDAT_TYPE_DSMSCIS = 2,\n\tACPI_CDAT_TYPE_DSIS = 3,\n\tACPI_CDAT_TYPE_DSEMTS = 4,\n\tACPI_CDAT_TYPE_SSLBIS = 5,\n\tACPI_CDAT_TYPE_RESERVED = 6,\n};\n\nenum acpi_cedt_type {\n\tACPI_CEDT_TYPE_CHBS = 0,\n\tACPI_CEDT_TYPE_CFMWS = 1,\n\tACPI_CEDT_TYPE_CXIMS = 2,\n\tACPI_CEDT_TYPE_RDPAS = 3,\n\tACPI_CEDT_TYPE_RESERVED = 4,\n};\n\nenum acpi_device_swnode_dev_props {\n\tACPI_DEVICE_SWNODE_DEV_ROTATION = 0,\n\tACPI_DEVICE_SWNODE_DEV_CLOCK_FREQUENCY = 1,\n\tACPI_DEVICE_SWNODE_DEV_LED_MAX_MICROAMP = 2,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_MICROAMP = 3,\n\tACPI_DEVICE_SWNODE_DEV_FLASH_MAX_TIMEOUT_US = 4,\n\tACPI_DEVICE_SWNODE_DEV_NUM_OF = 5,\n\tACPI_DEVICE_SWNODE_DEV_NUM_ENTRIES = 6,\n};\n\nenum acpi_device_swnode_ep_props {\n\tACPI_DEVICE_SWNODE_EP_REMOTE_EP = 0,\n\tACPI_DEVICE_SWNODE_EP_BUS_TYPE = 1,\n\tACPI_DEVICE_SWNODE_EP_REG = 2,\n\tACPI_DEVICE_SWNODE_EP_CLOCK_LANES = 3,\n\tACPI_DEVICE_SWNODE_EP_DATA_LANES = 4,\n\tACPI_DEVICE_SWNODE_EP_LANE_POLARITIES = 5,\n\tACPI_DEVICE_SWNODE_EP_LINK_FREQUENCIES = 6,\n\tACPI_DEVICE_SWNODE_EP_NUM_OF = 7,\n\tACPI_DEVICE_SWNODE_EP_NUM_ENTRIES = 8,\n};\n\nenum acpi_device_swnode_port_props {\n\tACPI_DEVICE_SWNODE_PORT_REG = 0,\n\tACPI_DEVICE_SWNODE_PORT_NUM_OF = 1,\n\tACPI_DEVICE_SWNODE_PORT_NUM_ENTRIES = 2,\n};\n\nenum acpi_einj_actions {\n\tACPI_EINJ_BEGIN_OPERATION = 0,\n\tACPI_EINJ_GET_TRIGGER_TABLE = 1,\n\tACPI_EINJ_SET_ERROR_TYPE = 2,\n\tACPI_EINJ_GET_ERROR_TYPE = 3,\n\tACPI_EINJ_END_OPERATION = 4,\n\tACPI_EINJ_EXECUTE_OPERATION = 5,\n\tACPI_EINJ_CHECK_BUSY_STATUS = 6,\n\tACPI_EINJ_GET_COMMAND_STATUS = 7,\n\tACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 8,\n\tACPI_EINJ_GET_EXECUTE_TIMINGS = 9,\n\tACPI_EINJV2_GET_ERROR_TYPE = 17,\n\tACPI_EINJ_ACTION_RESERVED = 18,\n\tACPI_EINJ_TRIGGER_ERROR = 255,\n};\n\nenum acpi_einj_instructions {\n\tACPI_EINJ_READ_REGISTER = 0,\n\tACPI_EINJ_READ_REGISTER_VALUE = 1,\n\tACPI_EINJ_WRITE_REGISTER = 2,\n\tACPI_EINJ_WRITE_REGISTER_VALUE = 3,\n\tACPI_EINJ_NOOP = 4,\n\tACPI_EINJ_FLUSH_CACHELINE = 5,\n\tACPI_EINJ_INSTRUCTION_RESERVED = 6,\n};\n\nenum acpi_erst_actions {\n\tACPI_ERST_BEGIN_WRITE = 0,\n\tACPI_ERST_BEGIN_READ = 1,\n\tACPI_ERST_BEGIN_CLEAR = 2,\n\tACPI_ERST_END = 3,\n\tACPI_ERST_SET_RECORD_OFFSET = 4,\n\tACPI_ERST_EXECUTE_OPERATION = 5,\n\tACPI_ERST_CHECK_BUSY_STATUS = 6,\n\tACPI_ERST_GET_COMMAND_STATUS = 7,\n\tACPI_ERST_GET_RECORD_ID = 8,\n\tACPI_ERST_SET_RECORD_ID = 9,\n\tACPI_ERST_GET_RECORD_COUNT = 10,\n\tACPI_ERST_BEGIN_DUMMY_WRIITE = 11,\n\tACPI_ERST_NOT_USED = 12,\n\tACPI_ERST_GET_ERROR_RANGE = 13,\n\tACPI_ERST_GET_ERROR_LENGTH = 14,\n\tACPI_ERST_GET_ERROR_ATTRIBUTES = 15,\n\tACPI_ERST_EXECUTE_TIMINGS = 16,\n\tACPI_ERST_ACTION_RESERVED = 17,\n};\n\nenum acpi_erst_instructions {\n\tACPI_ERST_READ_REGISTER = 0,\n\tACPI_ERST_READ_REGISTER_VALUE = 1,\n\tACPI_ERST_WRITE_REGISTER = 2,\n\tACPI_ERST_WRITE_REGISTER_VALUE = 3,\n\tACPI_ERST_NOOP = 4,\n\tACPI_ERST_LOAD_VAR1 = 5,\n\tACPI_ERST_LOAD_VAR2 = 6,\n\tACPI_ERST_STORE_VAR1 = 7,\n\tACPI_ERST_ADD = 8,\n\tACPI_ERST_SUBTRACT = 9,\n\tACPI_ERST_ADD_VALUE = 10,\n\tACPI_ERST_SUBTRACT_VALUE = 11,\n\tACPI_ERST_STALL = 12,\n\tACPI_ERST_STALL_WHILE_TRUE = 13,\n\tACPI_ERST_SKIP_NEXT_IF_TRUE = 14,\n\tACPI_ERST_GOTO = 15,\n\tACPI_ERST_SET_SRC_ADDRESS_BASE = 16,\n\tACPI_ERST_SET_DST_ADDRESS_BASE = 17,\n\tACPI_ERST_MOVE_DATA = 18,\n\tACPI_ERST_INSTRUCTION_RESERVED = 19,\n};\n\nenum acpi_gpio_ignore_list {\n\tACPI_GPIO_IGNORE_WAKE = 0,\n\tACPI_GPIO_IGNORE_INTERRUPT = 1,\n};\n\nenum acpi_gtdt_type {\n\tACPI_GTDT_TYPE_TIMER_BLOCK = 0,\n\tACPI_GTDT_TYPE_WATCHDOG = 1,\n\tACPI_GTDT_TYPE_RESERVED = 2,\n};\n\nenum acpi_hest_notify_types {\n\tACPI_HEST_NOTIFY_POLLED = 0,\n\tACPI_HEST_NOTIFY_EXTERNAL = 1,\n\tACPI_HEST_NOTIFY_LOCAL = 2,\n\tACPI_HEST_NOTIFY_SCI = 3,\n\tACPI_HEST_NOTIFY_NMI = 4,\n\tACPI_HEST_NOTIFY_CMCI = 5,\n\tACPI_HEST_NOTIFY_MCE = 6,\n\tACPI_HEST_NOTIFY_GPIO = 7,\n\tACPI_HEST_NOTIFY_SEA = 8,\n\tACPI_HEST_NOTIFY_SEI = 9,\n\tACPI_HEST_NOTIFY_GSIV = 10,\n\tACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11,\n\tACPI_HEST_NOTIFY_RESERVED = 12,\n};\n\nenum acpi_hest_types {\n\tACPI_HEST_TYPE_IA32_CHECK = 0,\n\tACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1,\n\tACPI_HEST_TYPE_IA32_NMI = 2,\n\tACPI_HEST_TYPE_NOT_USED3 = 3,\n\tACPI_HEST_TYPE_NOT_USED4 = 4,\n\tACPI_HEST_TYPE_NOT_USED5 = 5,\n\tACPI_HEST_TYPE_AER_ROOT_PORT = 6,\n\tACPI_HEST_TYPE_AER_ENDPOINT = 7,\n\tACPI_HEST_TYPE_AER_BRIDGE = 8,\n\tACPI_HEST_TYPE_GENERIC_ERROR = 9,\n\tACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10,\n\tACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11,\n\tACPI_HEST_TYPE_RESERVED = 12,\n};\n\nenum acpi_hmat_type {\n\tACPI_HMAT_TYPE_PROXIMITY = 0,\n\tACPI_HMAT_TYPE_LOCALITY = 1,\n\tACPI_HMAT_TYPE_CACHE = 2,\n\tACPI_HMAT_TYPE_RESERVED = 3,\n};\n\nenum acpi_iort_node_type {\n\tACPI_IORT_NODE_ITS_GROUP = 0,\n\tACPI_IORT_NODE_NAMED_COMPONENT = 1,\n\tACPI_IORT_NODE_PCI_ROOT_COMPLEX = 2,\n\tACPI_IORT_NODE_SMMU = 3,\n\tACPI_IORT_NODE_SMMU_V3 = 4,\n\tACPI_IORT_NODE_PMCG = 5,\n\tACPI_IORT_NODE_RMR = 6,\n\tACPI_IORT_NODE_IWB = 7,\n};\n\nenum acpi_irq_model_id {\n\tACPI_IRQ_MODEL_PIC = 0,\n\tACPI_IRQ_MODEL_IOAPIC = 1,\n\tACPI_IRQ_MODEL_IOSAPIC = 2,\n\tACPI_IRQ_MODEL_PLATFORM = 3,\n\tACPI_IRQ_MODEL_GIC = 4,\n\tACPI_IRQ_MODEL_GIC_V5 = 5,\n\tACPI_IRQ_MODEL_LPIC = 6,\n\tACPI_IRQ_MODEL_RINTC = 7,\n\tACPI_IRQ_MODEL_COUNT = 8,\n};\n\nenum acpi_madt_gic_version {\n\tACPI_MADT_GIC_VERSION_NONE = 0,\n\tACPI_MADT_GIC_VERSION_V1 = 1,\n\tACPI_MADT_GIC_VERSION_V2 = 2,\n\tACPI_MADT_GIC_VERSION_V3 = 3,\n\tACPI_MADT_GIC_VERSION_V4 = 4,\n\tACPI_MADT_GIC_VERSION_V5 = 5,\n\tACPI_MADT_GIC_VERSION_RESERVED = 6,\n};\n\nenum acpi_madt_multiproc_wakeup_version {\n\tACPI_MADT_MP_WAKEUP_VERSION_NONE = 0,\n\tACPI_MADT_MP_WAKEUP_VERSION_V1 = 1,\n\tACPI_MADT_MP_WAKEUP_VERSION_RESERVED = 2,\n};\n\nenum acpi_madt_type {\n\tACPI_MADT_TYPE_LOCAL_APIC = 0,\n\tACPI_MADT_TYPE_IO_APIC = 1,\n\tACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,\n\tACPI_MADT_TYPE_NMI_SOURCE = 3,\n\tACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,\n\tACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,\n\tACPI_MADT_TYPE_IO_SAPIC = 6,\n\tACPI_MADT_TYPE_LOCAL_SAPIC = 7,\n\tACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,\n\tACPI_MADT_TYPE_LOCAL_X2APIC = 9,\n\tACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,\n\tACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,\n\tACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,\n\tACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,\n\tACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,\n\tACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,\n\tACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,\n\tACPI_MADT_TYPE_CORE_PIC = 17,\n\tACPI_MADT_TYPE_LIO_PIC = 18,\n\tACPI_MADT_TYPE_HT_PIC = 19,\n\tACPI_MADT_TYPE_EIO_PIC = 20,\n\tACPI_MADT_TYPE_MSI_PIC = 21,\n\tACPI_MADT_TYPE_BIO_PIC = 22,\n\tACPI_MADT_TYPE_LPC_PIC = 23,\n\tACPI_MADT_TYPE_RINTC = 24,\n\tACPI_MADT_TYPE_IMSIC = 25,\n\tACPI_MADT_TYPE_APLIC = 26,\n\tACPI_MADT_TYPE_PLIC = 27,\n\tACPI_MADT_TYPE_GICV5_IRS = 28,\n\tACPI_MADT_TYPE_GICV5_ITS = 29,\n\tACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,\n\tACPI_MADT_TYPE_RESERVED = 31,\n\tACPI_MADT_TYPE_OEM_RESERVED = 128,\n};\n\nenum acpi_pcct_type {\n\tACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2,\n\tACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3,\n\tACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4,\n\tACPI_PCCT_TYPE_HW_REG_COMM_SUBSPACE = 5,\n\tACPI_PCCT_TYPE_RESERVED = 6,\n};\n\nenum acpi_pptt_type {\n\tACPI_PPTT_TYPE_PROCESSOR = 0,\n\tACPI_PPTT_TYPE_CACHE = 1,\n\tACPI_PPTT_TYPE_ID = 2,\n\tACPI_PPTT_TYPE_RESERVED = 3,\n};\n\nenum acpi_predicate {\n\tall_versions = 0,\n\tless_than_or_equal = 1,\n\tequal = 2,\n\tgreater_than_or_equal = 3,\n};\n\nenum acpi_reconfig_event {\n\tACPI_RECONFIG_DEVICE_ADD = 0,\n\tACPI_RECONFIG_DEVICE_REMOVE = 1,\n};\n\nenum acpi_return_package_types {\n\tACPI_PTYPE1_FIXED = 1,\n\tACPI_PTYPE1_VAR = 2,\n\tACPI_PTYPE1_OPTION = 3,\n\tACPI_PTYPE2 = 4,\n\tACPI_PTYPE2_COUNT = 5,\n\tACPI_PTYPE2_PKG_COUNT = 6,\n\tACPI_PTYPE2_FIXED = 7,\n\tACPI_PTYPE2_MIN = 8,\n\tACPI_PTYPE2_REV_FIXED = 9,\n\tACPI_PTYPE2_FIX_VAR = 10,\n\tACPI_PTYPE2_VAR_VAR = 11,\n\tACPI_PTYPE2_UUID_PAIR = 12,\n\tACPI_PTYPE_CUSTOM = 13,\n};\n\nenum acpi_srat_type {\n\tACPI_SRAT_TYPE_CPU_AFFINITY = 0,\n\tACPI_SRAT_TYPE_MEMORY_AFFINITY = 1,\n\tACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2,\n\tACPI_SRAT_TYPE_GICC_AFFINITY = 3,\n\tACPI_SRAT_TYPE_GIC_ITS_AFFINITY = 4,\n\tACPI_SRAT_TYPE_GENERIC_AFFINITY = 5,\n\tACPI_SRAT_TYPE_GENERIC_PORT_AFFINITY = 6,\n\tACPI_SRAT_TYPE_RINTC_AFFINITY = 7,\n\tACPI_SRAT_TYPE_RESERVED = 8,\n};\n\nenum acpi_subtable_type {\n\tACPI_SUBTABLE_COMMON = 0,\n\tACPI_SUBTABLE_HMAT = 1,\n\tACPI_SUBTABLE_PRMT = 2,\n\tACPI_SUBTABLE_CEDT = 3,\n\tCDAT_SUBTABLE = 4,\n};\n\nenum actions {\n\tREGISTER = 0,\n\tDEREGISTER = 1,\n\tCPU_DONT_CARE = 2,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum ahci_qoriq_type {\n\tAHCI_LS1021A = 0,\n\tAHCI_LS1028A = 1,\n\tAHCI_LS1043A = 2,\n\tAHCI_LS2080A = 3,\n\tAHCI_LS1046A = 4,\n\tAHCI_LS1088A = 5,\n\tAHCI_LS2088A = 6,\n\tAHCI_LX2160A = 7,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum ale_fields {\n\tMINOR_VER = 0,\n\tMAJOR_VER = 1,\n\tALE_ENTRIES = 2,\n\tALE_POLICERS = 3,\n\tPOL_PORT_MEN = 4,\n\tPOL_TRUNK_ID = 5,\n\tPOL_PORT_NUM = 6,\n\tPOL_PRI_MEN = 7,\n\tPOL_PRI_VAL = 8,\n\tPOL_OUI_MEN = 9,\n\tPOL_OUI_INDEX = 10,\n\tPOL_DST_MEN = 11,\n\tPOL_DST_INDEX = 12,\n\tPOL_SRC_MEN = 13,\n\tPOL_SRC_INDEX = 14,\n\tPOL_OVLAN_MEN = 15,\n\tPOL_OVLAN_INDEX = 16,\n\tPOL_IVLAN_MEN = 17,\n\tPOL_IVLAN_INDEX = 18,\n\tPOL_ETHERTYPE_MEN = 19,\n\tPOL_ETHERTYPE_INDEX = 20,\n\tPOL_IPSRC_MEN = 21,\n\tPOL_IPSRC_INDEX = 22,\n\tPOL_IPDST_MEN = 23,\n\tPOL_IPDST_INDEX = 24,\n\tPOL_EN = 25,\n\tPOL_RED_DROP_EN = 26,\n\tPOL_YELLOW_DROP_EN = 27,\n\tPOL_YELLOW_THRESH = 28,\n\tPOL_POL_MATCH_MODE = 29,\n\tPOL_PRIORITY_THREAD_EN = 30,\n\tPOL_MAC_ONLY_DEF_DIS = 31,\n\tPOL_TEST_CLR = 32,\n\tPOL_TEST_CLR_RED = 33,\n\tPOL_TEST_CLR_YELLOW = 34,\n\tPOL_TEST_CLR_SELECTED = 35,\n\tPOL_TEST_ENTRY = 36,\n\tPOL_STATUS_HIT = 37,\n\tPOL_STATUS_HIT_RED = 38,\n\tPOL_STATUS_HIT_YELLOW = 39,\n\tALE_DEFAULT_THREAD_EN = 40,\n\tALE_DEFAULT_THREAD_VAL = 41,\n\tALE_THREAD_CLASS_INDEX = 42,\n\tALE_THREAD_ENABLE = 43,\n\tALE_THREAD_VALUE = 44,\n\tALE_FIELDS_MAX = 45,\n};\n\nenum altera_pcie_version {\n\tALTERA_PCIE_V1 = 0,\n\tALTERA_PCIE_V2 = 1,\n\tALTERA_PCIE_V3 = 2,\n};\n\nenum am65_cpsw_tx_buf_type {\n\tAM65_CPSW_TX_BUF_TYPE_SKB = 0,\n\tAM65_CPSW_TX_BUF_TYPE_XDP_TX = 1,\n\tAM65_CPSW_TX_BUF_TYPE_XDP_NDO = 2,\n};\n\nenum aml_pinconf_drv {\n\tPINCONF_DRV_500UA = 0,\n\tPINCONF_DRV_2500UA = 1,\n\tPINCONF_DRV_3000UA = 2,\n\tPINCONF_DRV_4000UA = 3,\n};\n\nenum aqr_fw_src {\n\tAQR_FW_SRC_NVMEM = 0,\n\tAQR_FW_SRC_FS = 1,\n};\n\nenum aqr_rate_adaptation {\n\tAQR_RATE_ADAPT_NONE = 0,\n\tAQR_RATE_ADAPT_USX = 1,\n\tAQR_RATE_ADAPT_PAUSE = 2,\n};\n\nenum arch_timer_access {\n\tPHYS_ACCESS = 0,\n\tVIRT_ACCESS = 1,\n};\n\nenum arch_timer_erratum_match_type {\n\tate_match_dt = 0,\n\tate_match_local_cap_id = 1,\n\tate_match_acpi_oem_info = 2,\n};\n\nenum arch_timer_ppi_nr {\n\tARCH_TIMER_PHYS_SECURE_PPI = 0,\n\tARCH_TIMER_PHYS_NONSECURE_PPI = 1,\n\tARCH_TIMER_VIRT_PPI = 2,\n\tARCH_TIMER_HYP_PPI = 3,\n\tARCH_TIMER_HYP_VIRT_PPI = 4,\n\tARCH_TIMER_MAX_TIMER_PPI = 5,\n};\n\nenum arch_timer_reg {\n\tARCH_TIMER_REG_CTRL = 0,\n\tARCH_TIMER_REG_CVAL = 1,\n};\n\nenum arm64_bp_harden_el1_vectors {\n\tEL1_VECTOR_BHB_LOOP = 0,\n\tEL1_VECTOR_BHB_FW = 1,\n\tEL1_VECTOR_BHB_CLEAR_INSN = 2,\n\tEL1_VECTOR_KPTI = 3,\n};\n\nenum arm64_hyp_spectre_vector {\n\tHYP_VECTOR_DIRECT = 0,\n\tHYP_VECTOR_SPECTRE_DIRECT = 1,\n\tHYP_VECTOR_INDIRECT = 2,\n\tHYP_VECTOR_SPECTRE_INDIRECT = 3,\n};\n\nenum arm_smccc_conduit {\n\tSMCCC_CONDUIT_NONE = 0,\n\tSMCCC_CONDUIT_SMC = 1,\n\tSMCCC_CONDUIT_HVC = 2,\n};\n\nenum arm_smmu_arch_version {\n\tARM_SMMU_V1 = 0,\n\tARM_SMMU_V1_64K = 1,\n\tARM_SMMU_V2 = 2,\n};\n\nenum arm_smmu_cbar_type {\n\tCBAR_TYPE_S2_TRANS = 0,\n\tCBAR_TYPE_S1_TRANS_S2_BYPASS = 1,\n\tCBAR_TYPE_S1_TRANS_S2_FAULT = 2,\n\tCBAR_TYPE_S1_TRANS_S2_TRANS = 3,\n};\n\nenum arm_smmu_context_fmt {\n\tARM_SMMU_CTX_FMT_NONE = 0,\n\tARM_SMMU_CTX_FMT_AARCH64 = 1,\n\tARM_SMMU_CTX_FMT_AARCH32_L = 2,\n\tARM_SMMU_CTX_FMT_AARCH32_S = 3,\n};\n\nenum arm_smmu_domain_stage {\n\tARM_SMMU_DOMAIN_S1 = 0,\n\tARM_SMMU_DOMAIN_S2 = 1,\n};\n\nenum arm_smmu_domain_stage___2 {\n\tARM_SMMU_DOMAIN_S1___2 = 0,\n\tARM_SMMU_DOMAIN_S2___2 = 1,\n\tARM_SMMU_DOMAIN_NESTED = 2,\n};\n\nenum arm_smmu_implementation {\n\tGENERIC_SMMU = 0,\n\tARM_MMU500 = 1,\n\tCAVIUM_SMMUV2 = 2,\n\tQCOM_SMMUV2 = 3,\n};\n\nenum arm_smmu_msi_index {\n\tEVTQ_MSI_INDEX = 0,\n\tGERROR_MSI_INDEX = 1,\n\tPRIQ_MSI_INDEX = 2,\n\tARM_SMMU_MAX_MSIS = 3,\n};\n\nenum arm_smmu_s2cr_privcfg {\n\tS2CR_PRIVCFG_DEFAULT = 0,\n\tS2CR_PRIVCFG_DIPAN = 1,\n\tS2CR_PRIVCFG_UNPRIV = 2,\n\tS2CR_PRIVCFG_PRIV = 3,\n};\n\nenum arm_smmu_s2cr_type {\n\tS2CR_TYPE_TRANS = 0,\n\tS2CR_TYPE_BYPASS = 1,\n\tS2CR_TYPE_FAULT = 2,\n};\n\nenum armpmu_attr_groups {\n\tARMPMU_ATTR_GROUP_COMMON = 0,\n\tARMPMU_ATTR_GROUP_EVENTS = 1,\n\tARMPMU_ATTR_GROUP_FORMATS = 2,\n\tARMPMU_ATTR_GROUP_CAPS = 3,\n\tARMPMU_NR_ATTR_GROUPS = 4,\n};\n\nenum asn1_class {\n\tASN1_UNIV = 0,\n\tASN1_APPL = 1,\n\tASN1_CONT = 2,\n\tASN1_PRIV = 3,\n};\n\nenum asn1_method {\n\tASN1_PRIM = 0,\n\tASN1_CONS = 1,\n};\n\nenum asn1_opcode {\n\tASN1_OP_MATCH = 0,\n\tASN1_OP_MATCH_OR_SKIP = 1,\n\tASN1_OP_MATCH_ACT = 2,\n\tASN1_OP_MATCH_ACT_OR_SKIP = 3,\n\tASN1_OP_MATCH_JUMP = 4,\n\tASN1_OP_MATCH_JUMP_OR_SKIP = 5,\n\tASN1_OP_MATCH_ANY = 8,\n\tASN1_OP_MATCH_ANY_OR_SKIP = 9,\n\tASN1_OP_MATCH_ANY_ACT = 10,\n\tASN1_OP_MATCH_ANY_ACT_OR_SKIP = 11,\n\tASN1_OP_COND_MATCH_OR_SKIP = 17,\n\tASN1_OP_COND_MATCH_ACT_OR_SKIP = 19,\n\tASN1_OP_COND_MATCH_JUMP_OR_SKIP = 21,\n\tASN1_OP_COND_MATCH_ANY = 24,\n\tASN1_OP_COND_MATCH_ANY_OR_SKIP = 25,\n\tASN1_OP_COND_MATCH_ANY_ACT = 26,\n\tASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 27,\n\tASN1_OP_COND_FAIL = 28,\n\tASN1_OP_COMPLETE = 29,\n\tASN1_OP_ACT = 30,\n\tASN1_OP_MAYBE_ACT = 31,\n\tASN1_OP_END_SEQ = 32,\n\tASN1_OP_END_SET = 33,\n\tASN1_OP_END_SEQ_OF = 34,\n\tASN1_OP_END_SET_OF = 35,\n\tASN1_OP_END_SEQ_ACT = 36,\n\tASN1_OP_END_SET_ACT = 37,\n\tASN1_OP_END_SEQ_OF_ACT = 38,\n\tASN1_OP_END_SET_OF_ACT = 39,\n\tASN1_OP_RETURN = 40,\n\tASN1_OP__NR = 41,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\nenum asp_netfilt_reg_type {\n\tASP_NETFILT_MATCH = 0,\n\tASP_NETFILT_MASK = 1,\n\tASP_NETFILT_MAX = 2,\n};\n\nenum asp_rx_filter_id {\n\tASP_RX_FILTER_MDA_PROMISC = 0,\n\tASP_RX_FILTER_MDA_ALLMULTI = 1,\n\tASP_RX_FILTER_MDA_BROADCAST = 2,\n\tASP_RX_FILTER_MDA_OWN_ADDR = 3,\n\tASP_RX_FILTER_MDA_RES_MAX = 4,\n};\n\nenum asp_rx_net_filter_block {\n\tASP_RX_FILTER_NET_L2 = 0,\n\tASP_RX_FILTER_NET_L3_0 = 1,\n\tASP_RX_FILTER_NET_L3_1 = 2,\n\tASP_RX_FILTER_NET_L4 = 3,\n\tASP_RX_FILTER_NET_BLOCK_MAX = 4,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum asymmetric_payload_bits {\n\tasym_crypto = 0,\n\tasym_subtype = 1,\n\tasym_key_ids = 2,\n\tasym_auth = 3,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nenum ata_quirks {\n\t__ATA_QUIRK_DIAGNOSTIC = 0,\n\t__ATA_QUIRK_NODMA = 1,\n\t__ATA_QUIRK_NONCQ = 2,\n\t__ATA_QUIRK_BROKEN_HPA = 3,\n\t__ATA_QUIRK_DISABLE = 4,\n\t__ATA_QUIRK_HPA_SIZE = 5,\n\t__ATA_QUIRK_IVB = 6,\n\t__ATA_QUIRK_STUCK_ERR = 7,\n\t__ATA_QUIRK_BRIDGE_OK = 8,\n\t__ATA_QUIRK_ATAPI_MOD16_DMA = 9,\n\t__ATA_QUIRK_FIRMWARE_WARN = 10,\n\t__ATA_QUIRK_1_5_GBPS = 11,\n\t__ATA_QUIRK_NOSETXFER = 12,\n\t__ATA_QUIRK_BROKEN_FPDMA_AA = 13,\n\t__ATA_QUIRK_DUMP_ID = 14,\n\t__ATA_QUIRK_MAX_SEC_LBA48 = 15,\n\t__ATA_QUIRK_ATAPI_DMADIR = 16,\n\t__ATA_QUIRK_NO_NCQ_TRIM = 17,\n\t__ATA_QUIRK_NOLPM = 18,\n\t__ATA_QUIRK_WD_BROKEN_LPM = 19,\n\t__ATA_QUIRK_ZERO_AFTER_TRIM = 20,\n\t__ATA_QUIRK_NO_DMA_LOG = 21,\n\t__ATA_QUIRK_NOTRIM = 22,\n\t__ATA_QUIRK_MAX_SEC = 23,\n\t__ATA_QUIRK_MAX_TRIM_128M = 24,\n\t__ATA_QUIRK_NO_NCQ_ON_ATI = 25,\n\t__ATA_QUIRK_NO_LPM_ON_ATI = 26,\n\t__ATA_QUIRK_NO_ID_DEV_LOG = 27,\n\t__ATA_QUIRK_NO_LOG_DIR = 28,\n\t__ATA_QUIRK_NO_FUA = 29,\n\t__ATA_QUIRK_MAX = 30,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum attr_idn {\n\tQUERY_ATTR_IDN_BOOT_LU_EN = 0,\n\tQUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 1,\n\tQUERY_ATTR_IDN_POWER_MODE = 2,\n\tQUERY_ATTR_IDN_ACTIVE_ICC_LVL = 3,\n\tQUERY_ATTR_IDN_OOO_DATA_EN = 4,\n\tQUERY_ATTR_IDN_BKOPS_STATUS = 5,\n\tQUERY_ATTR_IDN_PURGE_STATUS = 6,\n\tQUERY_ATTR_IDN_MAX_DATA_IN = 7,\n\tQUERY_ATTR_IDN_MAX_DATA_OUT = 8,\n\tQUERY_ATTR_IDN_DYN_CAP_NEEDED = 9,\n\tQUERY_ATTR_IDN_REF_CLK_FREQ = 10,\n\tQUERY_ATTR_IDN_CONF_DESC_LOCK = 11,\n\tQUERY_ATTR_IDN_MAX_NUM_OF_RTT = 12,\n\tQUERY_ATTR_IDN_EE_CONTROL = 13,\n\tQUERY_ATTR_IDN_EE_STATUS = 14,\n\tQUERY_ATTR_IDN_SECONDS_PASSED = 15,\n\tQUERY_ATTR_IDN_CNTX_CONF = 16,\n\tQUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 17,\n\tQUERY_ATTR_IDN_RESERVED2 = 18,\n\tQUERY_ATTR_IDN_RESERVED3 = 19,\n\tQUERY_ATTR_IDN_FFU_STATUS = 20,\n\tQUERY_ATTR_IDN_PSA_STATE = 21,\n\tQUERY_ATTR_IDN_PSA_DATA_SIZE = 22,\n\tQUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 23,\n\tQUERY_ATTR_IDN_CASE_ROUGH_TEMP = 24,\n\tQUERY_ATTR_IDN_HIGH_TEMP_BOUND = 25,\n\tQUERY_ATTR_IDN_LOW_TEMP_BOUND = 26,\n\tQUERY_ATTR_IDN_WB_FLUSH_STATUS = 28,\n\tQUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 29,\n\tQUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 30,\n\tQUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 31,\n\tQUERY_ATTR_IDN_TIMESTAMP = 48,\n\tQUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID = 52,\n\tQUERY_ATTR_IDN_HID_DEFRAG_OPERATION = 53,\n\tQUERY_ATTR_IDN_HID_AVAILABLE_SIZE = 54,\n\tQUERY_ATTR_IDN_HID_SIZE = 55,\n\tQUERY_ATTR_IDN_HID_PROGRESS_RATIO = 56,\n\tQUERY_ATTR_IDN_HID_STATE = 57,\n\tQUERY_ATTR_IDN_WB_BUF_RESIZE_HINT = 60,\n\tQUERY_ATTR_IDN_WB_BUF_RESIZE_EN = 61,\n\tQUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS = 62,\n};\n\nenum audit_nfcfgop {\n\tAUDIT_XT_OP_REGISTER = 0,\n\tAUDIT_XT_OP_REPLACE = 1,\n\tAUDIT_XT_OP_UNREGISTER = 2,\n\tAUDIT_NFT_OP_TABLE_REGISTER = 3,\n\tAUDIT_NFT_OP_TABLE_UNREGISTER = 4,\n\tAUDIT_NFT_OP_CHAIN_REGISTER = 5,\n\tAUDIT_NFT_OP_CHAIN_UNREGISTER = 6,\n\tAUDIT_NFT_OP_RULE_REGISTER = 7,\n\tAUDIT_NFT_OP_RULE_UNREGISTER = 8,\n\tAUDIT_NFT_OP_SET_REGISTER = 9,\n\tAUDIT_NFT_OP_SET_UNREGISTER = 10,\n\tAUDIT_NFT_OP_SETELEM_REGISTER = 11,\n\tAUDIT_NFT_OP_SETELEM_UNREGISTER = 12,\n\tAUDIT_NFT_OP_GEN_REGISTER = 13,\n\tAUDIT_NFT_OP_OBJ_REGISTER = 14,\n\tAUDIT_NFT_OP_OBJ_UNREGISTER = 15,\n\tAUDIT_NFT_OP_OBJ_RESET = 16,\n\tAUDIT_NFT_OP_FLOWTABLE_REGISTER = 17,\n\tAUDIT_NFT_OP_FLOWTABLE_UNREGISTER = 18,\n\tAUDIT_NFT_OP_SETELEM_RESET = 19,\n\tAUDIT_NFT_OP_RULE_RESET = 20,\n\tAUDIT_NFT_OP_INVALID = 21,\n};\n\nenum audit_nlgrps {\n\tAUDIT_NLGRP_NONE = 0,\n\tAUDIT_NLGRP_READLOG = 1,\n\t__AUDIT_NLGRP_MAX = 2,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum audit_state {\n\tAUDIT_STATE_DISABLED = 0,\n\tAUDIT_STATE_BUILD = 1,\n\tAUDIT_STATE_RECORD = 2,\n};\n\nenum auditsc_class_t {\n\tAUDITSC_NATIVE = 0,\n\tAUDITSC_COMPAT = 1,\n\tAUDITSC_OPEN = 2,\n\tAUDITSC_OPENAT = 3,\n\tAUDITSC_SOCKETCALL = 4,\n\tAUDITSC_EXECVE = 5,\n\tAUDITSC_OPENAT2 = 6,\n\tAUDITSC_NVALS = 7,\n};\n\nenum autofs_notify {\n\tNFY_NONE = 0,\n\tNFY_MOUNT = 1,\n\tNFY_EXPIRE = 2,\n};\n\nenum axp15060_irqs {\n\tAXP15060_IRQ_DIE_TEMP_HIGH_LV1 = 1,\n\tAXP15060_IRQ_DIE_TEMP_HIGH_LV2 = 2,\n\tAXP15060_IRQ_DCDC1_V_LOW = 3,\n\tAXP15060_IRQ_DCDC2_V_LOW = 4,\n\tAXP15060_IRQ_DCDC3_V_LOW = 5,\n\tAXP15060_IRQ_DCDC4_V_LOW = 6,\n\tAXP15060_IRQ_DCDC5_V_LOW = 7,\n\tAXP15060_IRQ_DCDC6_V_LOW = 8,\n\tAXP15060_IRQ_PEK_LONG = 9,\n\tAXP15060_IRQ_PEK_SHORT = 10,\n\tAXP15060_IRQ_GPIO1_INPUT = 11,\n\tAXP15060_IRQ_PEK_FAL_EDGE = 12,\n\tAXP15060_IRQ_PEK_RIS_EDGE = 13,\n\tAXP15060_IRQ_GPIO2_INPUT = 14,\n};\n\nenum axp192_irqs {\n\tAXP192_IRQ_ACIN_OVER_V = 1,\n\tAXP192_IRQ_ACIN_PLUGIN = 2,\n\tAXP192_IRQ_ACIN_REMOVAL = 3,\n\tAXP192_IRQ_VBUS_OVER_V = 4,\n\tAXP192_IRQ_VBUS_PLUGIN = 5,\n\tAXP192_IRQ_VBUS_REMOVAL = 6,\n\tAXP192_IRQ_VBUS_V_LOW = 7,\n\tAXP192_IRQ_BATT_PLUGIN = 8,\n\tAXP192_IRQ_BATT_REMOVAL = 9,\n\tAXP192_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP192_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP192_IRQ_CHARG = 12,\n\tAXP192_IRQ_CHARG_DONE = 13,\n\tAXP192_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP192_IRQ_BATT_TEMP_LOW = 15,\n\tAXP192_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP192_IRQ_CHARG_I_LOW = 17,\n\tAXP192_IRQ_DCDC1_V_LONG = 18,\n\tAXP192_IRQ_DCDC2_V_LONG = 19,\n\tAXP192_IRQ_DCDC3_V_LONG = 20,\n\tAXP192_IRQ_PEK_SHORT = 22,\n\tAXP192_IRQ_PEK_LONG = 23,\n\tAXP192_IRQ_N_OE_PWR_ON = 24,\n\tAXP192_IRQ_N_OE_PWR_OFF = 25,\n\tAXP192_IRQ_VBUS_VALID = 26,\n\tAXP192_IRQ_VBUS_NOT_VALID = 27,\n\tAXP192_IRQ_VBUS_SESS_VALID = 28,\n\tAXP192_IRQ_VBUS_SESS_END = 29,\n\tAXP192_IRQ_LOW_PWR_LVL = 31,\n\tAXP192_IRQ_TIMER = 32,\n\tAXP192_IRQ_GPIO2_INPUT = 37,\n\tAXP192_IRQ_GPIO1_INPUT = 38,\n\tAXP192_IRQ_GPIO0_INPUT = 39,\n};\n\nenum axp20x_variants {\n\tAXP152_ID = 0,\n\tAXP192_ID = 1,\n\tAXP202_ID = 2,\n\tAXP209_ID = 3,\n\tAXP221_ID = 4,\n\tAXP223_ID = 5,\n\tAXP288_ID = 6,\n\tAXP313A_ID = 7,\n\tAXP323_ID = 8,\n\tAXP717_ID = 9,\n\tAXP803_ID = 10,\n\tAXP806_ID = 11,\n\tAXP809_ID = 12,\n\tAXP813_ID = 13,\n\tAXP15060_ID = 14,\n\tNR_AXP20X_VARIANTS = 15,\n};\n\nenum axp22x_irqs {\n\tAXP22X_IRQ_ACIN_OVER_V = 1,\n\tAXP22X_IRQ_ACIN_PLUGIN = 2,\n\tAXP22X_IRQ_ACIN_REMOVAL = 3,\n\tAXP22X_IRQ_VBUS_OVER_V = 4,\n\tAXP22X_IRQ_VBUS_PLUGIN = 5,\n\tAXP22X_IRQ_VBUS_REMOVAL = 6,\n\tAXP22X_IRQ_VBUS_V_LOW = 7,\n\tAXP22X_IRQ_BATT_PLUGIN = 8,\n\tAXP22X_IRQ_BATT_REMOVAL = 9,\n\tAXP22X_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP22X_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP22X_IRQ_CHARG = 12,\n\tAXP22X_IRQ_CHARG_DONE = 13,\n\tAXP22X_IRQ_BATT_TEMP_HIGH = 14,\n\tAXP22X_IRQ_BATT_TEMP_LOW = 15,\n\tAXP22X_IRQ_DIE_TEMP_HIGH = 16,\n\tAXP22X_IRQ_PEK_SHORT = 17,\n\tAXP22X_IRQ_PEK_LONG = 18,\n\tAXP22X_IRQ_LOW_PWR_LVL1 = 19,\n\tAXP22X_IRQ_LOW_PWR_LVL2 = 20,\n\tAXP22X_IRQ_TIMER = 21,\n\tAXP22X_IRQ_PEK_FAL_EDGE = 22,\n\tAXP22X_IRQ_PEK_RIS_EDGE = 23,\n\tAXP22X_IRQ_GPIO1_INPUT = 24,\n\tAXP22X_IRQ_GPIO0_INPUT = 25,\n};\n\nenum axp288_irqs {\n\tAXP288_IRQ_VBUS_FALL = 2,\n\tAXP288_IRQ_VBUS_RISE = 3,\n\tAXP288_IRQ_OV = 4,\n\tAXP288_IRQ_FALLING_ALT = 5,\n\tAXP288_IRQ_RISING_ALT = 6,\n\tAXP288_IRQ_OV_ALT = 7,\n\tAXP288_IRQ_DONE = 10,\n\tAXP288_IRQ_CHARGING = 11,\n\tAXP288_IRQ_SAFE_QUIT = 12,\n\tAXP288_IRQ_SAFE_ENTER = 13,\n\tAXP288_IRQ_ABSENT = 14,\n\tAXP288_IRQ_APPEND = 15,\n\tAXP288_IRQ_QWBTU = 16,\n\tAXP288_IRQ_WBTU = 17,\n\tAXP288_IRQ_QWBTO = 18,\n\tAXP288_IRQ_WBTO = 19,\n\tAXP288_IRQ_QCBTU = 20,\n\tAXP288_IRQ_CBTU = 21,\n\tAXP288_IRQ_QCBTO = 22,\n\tAXP288_IRQ_CBTO = 23,\n\tAXP288_IRQ_WL2 = 24,\n\tAXP288_IRQ_WL1 = 25,\n\tAXP288_IRQ_GPADC = 26,\n\tAXP288_IRQ_OT = 31,\n\tAXP288_IRQ_GPIO0 = 32,\n\tAXP288_IRQ_GPIO1 = 33,\n\tAXP288_IRQ_POKO = 34,\n\tAXP288_IRQ_POKL = 35,\n\tAXP288_IRQ_POKS = 36,\n\tAXP288_IRQ_POKN = 37,\n\tAXP288_IRQ_POKP = 38,\n\tAXP288_IRQ_TIMER = 39,\n\tAXP288_IRQ_MV_CHNG = 40,\n\tAXP288_IRQ_BC_USB_CHNG = 41,\n};\n\nenum axp313a_irqs {\n\tAXP313A_IRQ_DIE_TEMP_HIGH = 0,\n\tAXP313A_IRQ_DCDC2_V_LOW = 2,\n\tAXP313A_IRQ_DCDC3_V_LOW = 3,\n\tAXP313A_IRQ_PEK_LONG = 4,\n\tAXP313A_IRQ_PEK_SHORT = 5,\n\tAXP313A_IRQ_PEK_FAL_EDGE = 6,\n\tAXP313A_IRQ_PEK_RIS_EDGE = 7,\n};\n\nenum axp717_irqs {\n\tAXP717_IRQ_VBUS_FAULT = 0,\n\tAXP717_IRQ_VBUS_OVER_V = 1,\n\tAXP717_IRQ_BOOST_OVER_V = 2,\n\tAXP717_IRQ_GAUGE_NEW_SOC = 4,\n\tAXP717_IRQ_SOC_DROP_LVL1 = 6,\n\tAXP717_IRQ_SOC_DROP_LVL2 = 7,\n\tAXP717_IRQ_PEK_RIS_EDGE = 8,\n\tAXP717_IRQ_PEK_FAL_EDGE = 9,\n\tAXP717_IRQ_PEK_LONG = 10,\n\tAXP717_IRQ_PEK_SHORT = 11,\n\tAXP717_IRQ_BATT_REMOVAL = 12,\n\tAXP717_IRQ_BATT_PLUGIN = 13,\n\tAXP717_IRQ_VBUS_REMOVAL = 14,\n\tAXP717_IRQ_VBUS_PLUGIN = 15,\n\tAXP717_IRQ_BATT_OVER_V = 16,\n\tAXP717_IRQ_CHARG_TIMER = 17,\n\tAXP717_IRQ_DIE_TEMP_HIGH = 18,\n\tAXP717_IRQ_CHARG = 19,\n\tAXP717_IRQ_CHARG_DONE = 20,\n\tAXP717_IRQ_BATT_OVER_CURR = 21,\n\tAXP717_IRQ_LDO_OVER_CURR = 22,\n\tAXP717_IRQ_WDOG_EXPIRE = 23,\n\tAXP717_IRQ_BATT_ACT_TEMP_LOW = 24,\n\tAXP717_IRQ_BATT_ACT_TEMP_HIGH = 25,\n\tAXP717_IRQ_BATT_CHG_TEMP_LOW = 26,\n\tAXP717_IRQ_BATT_CHG_TEMP_HIGH = 27,\n\tAXP717_IRQ_BATT_QUIT_TEMP_HIGH = 28,\n\tAXP717_IRQ_BC_USB_CHNG = 30,\n\tAXP717_IRQ_BC_USB_DONE = 31,\n\tAXP717_IRQ_TYPEC_PLUGIN = 37,\n\tAXP717_IRQ_TYPEC_REMOVE = 38,\n};\n\nenum axp803_irqs {\n\tAXP803_IRQ_ACIN_OVER_V = 1,\n\tAXP803_IRQ_ACIN_PLUGIN = 2,\n\tAXP803_IRQ_ACIN_REMOVAL = 3,\n\tAXP803_IRQ_VBUS_OVER_V = 4,\n\tAXP803_IRQ_VBUS_PLUGIN = 5,\n\tAXP803_IRQ_VBUS_REMOVAL = 6,\n\tAXP803_IRQ_BATT_PLUGIN = 7,\n\tAXP803_IRQ_BATT_REMOVAL = 8,\n\tAXP803_IRQ_BATT_ENT_ACT_MODE = 9,\n\tAXP803_IRQ_BATT_EXIT_ACT_MODE = 10,\n\tAXP803_IRQ_CHARG = 11,\n\tAXP803_IRQ_CHARG_DONE = 12,\n\tAXP803_IRQ_BATT_CHG_TEMP_HIGH = 13,\n\tAXP803_IRQ_BATT_CHG_TEMP_HIGH_END = 14,\n\tAXP803_IRQ_BATT_CHG_TEMP_LOW = 15,\n\tAXP803_IRQ_BATT_CHG_TEMP_LOW_END = 16,\n\tAXP803_IRQ_BATT_ACT_TEMP_HIGH = 17,\n\tAXP803_IRQ_BATT_ACT_TEMP_HIGH_END = 18,\n\tAXP803_IRQ_BATT_ACT_TEMP_LOW = 19,\n\tAXP803_IRQ_BATT_ACT_TEMP_LOW_END = 20,\n\tAXP803_IRQ_DIE_TEMP_HIGH = 21,\n\tAXP803_IRQ_GPADC = 22,\n\tAXP803_IRQ_LOW_PWR_LVL1 = 23,\n\tAXP803_IRQ_LOW_PWR_LVL2 = 24,\n\tAXP803_IRQ_TIMER = 25,\n\tAXP803_IRQ_PEK_FAL_EDGE = 26,\n\tAXP803_IRQ_PEK_RIS_EDGE = 27,\n\tAXP803_IRQ_PEK_SHORT = 28,\n\tAXP803_IRQ_PEK_LONG = 29,\n\tAXP803_IRQ_PEK_OVER_OFF = 30,\n\tAXP803_IRQ_GPIO1_INPUT = 31,\n\tAXP803_IRQ_GPIO0_INPUT = 32,\n\tAXP803_IRQ_BC_USB_CHNG = 33,\n\tAXP803_IRQ_MV_CHNG = 34,\n};\n\nenum axp806_irqs {\n\tAXP806_IRQ_DIE_TEMP_HIGH_LV1 = 0,\n\tAXP806_IRQ_DIE_TEMP_HIGH_LV2 = 1,\n\tAXP806_IRQ_DCDCA_V_LOW = 2,\n\tAXP806_IRQ_DCDCB_V_LOW = 3,\n\tAXP806_IRQ_DCDCC_V_LOW = 4,\n\tAXP806_IRQ_DCDCD_V_LOW = 5,\n\tAXP806_IRQ_DCDCE_V_LOW = 6,\n\tAXP806_IRQ_POK_LONG = 7,\n\tAXP806_IRQ_POK_SHORT = 8,\n\tAXP806_IRQ_WAKEUP = 9,\n\tAXP806_IRQ_POK_FALL = 10,\n\tAXP806_IRQ_POK_RISE = 11,\n};\n\nenum axp809_irqs {\n\tAXP809_IRQ_ACIN_OVER_V = 1,\n\tAXP809_IRQ_ACIN_PLUGIN = 2,\n\tAXP809_IRQ_ACIN_REMOVAL = 3,\n\tAXP809_IRQ_VBUS_OVER_V = 4,\n\tAXP809_IRQ_VBUS_PLUGIN = 5,\n\tAXP809_IRQ_VBUS_REMOVAL = 6,\n\tAXP809_IRQ_VBUS_V_LOW = 7,\n\tAXP809_IRQ_BATT_PLUGIN = 8,\n\tAXP809_IRQ_BATT_REMOVAL = 9,\n\tAXP809_IRQ_BATT_ENT_ACT_MODE = 10,\n\tAXP809_IRQ_BATT_EXIT_ACT_MODE = 11,\n\tAXP809_IRQ_CHARG = 12,\n\tAXP809_IRQ_CHARG_DONE = 13,\n\tAXP809_IRQ_BATT_CHG_TEMP_HIGH = 14,\n\tAXP809_IRQ_BATT_CHG_TEMP_HIGH_END = 15,\n\tAXP809_IRQ_BATT_CHG_TEMP_LOW = 16,\n\tAXP809_IRQ_BATT_CHG_TEMP_LOW_END = 17,\n\tAXP809_IRQ_BATT_ACT_TEMP_HIGH = 18,\n\tAXP809_IRQ_BATT_ACT_TEMP_HIGH_END = 19,\n\tAXP809_IRQ_BATT_ACT_TEMP_LOW = 20,\n\tAXP809_IRQ_BATT_ACT_TEMP_LOW_END = 21,\n\tAXP809_IRQ_DIE_TEMP_HIGH = 22,\n\tAXP809_IRQ_LOW_PWR_LVL1 = 23,\n\tAXP809_IRQ_LOW_PWR_LVL2 = 24,\n\tAXP809_IRQ_TIMER = 25,\n\tAXP809_IRQ_PEK_FAL_EDGE = 26,\n\tAXP809_IRQ_PEK_RIS_EDGE = 27,\n\tAXP809_IRQ_PEK_SHORT = 28,\n\tAXP809_IRQ_PEK_LONG = 29,\n\tAXP809_IRQ_PEK_OVER_OFF = 30,\n\tAXP809_IRQ_GPIO1_INPUT = 31,\n\tAXP809_IRQ_GPIO0_INPUT = 32,\n};\n\nenum bam_command_type {\n\tBAM_WRITE_COMMAND = 0,\n\tBAM_READ_COMMAND = 1,\n};\n\nenum bam_reg {\n\tBAM_CTRL = 0,\n\tBAM_REVISION = 1,\n\tBAM_NUM_PIPES = 2,\n\tBAM_DESC_CNT_TRSHLD = 3,\n\tBAM_IRQ_SRCS = 4,\n\tBAM_IRQ_SRCS_MSK = 5,\n\tBAM_IRQ_SRCS_UNMASKED = 6,\n\tBAM_IRQ_STTS = 7,\n\tBAM_IRQ_CLR = 8,\n\tBAM_IRQ_EN = 9,\n\tBAM_CNFG_BITS = 10,\n\tBAM_IRQ_SRCS_EE = 11,\n\tBAM_IRQ_SRCS_MSK_EE = 12,\n\tBAM_P_CTRL = 13,\n\tBAM_P_RST = 14,\n\tBAM_P_HALT = 15,\n\tBAM_P_IRQ_STTS = 16,\n\tBAM_P_IRQ_CLR = 17,\n\tBAM_P_IRQ_EN = 18,\n\tBAM_P_EVNT_DEST_ADDR = 19,\n\tBAM_P_EVNT_REG = 20,\n\tBAM_P_SW_OFSTS = 21,\n\tBAM_P_DATA_FIFO_ADDR = 22,\n\tBAM_P_DESC_FIFO_ADDR = 23,\n\tBAM_P_EVNT_GEN_TRSHLD = 24,\n\tBAM_P_FIFO_SIZES = 25,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum base_type {\n\tMSPI = 0,\n\tBSPI = 1,\n\tCHIP_SELECT = 2,\n\tBASEMAX = 3,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum bcm2712_funcs {\n\tfunc_gpio = 0,\n\tfunc_alt1 = 1,\n\tfunc_alt2 = 2,\n\tfunc_alt3 = 3,\n\tfunc_alt4 = 4,\n\tfunc_alt5 = 5,\n\tfunc_alt6 = 6,\n\tfunc_alt7 = 7,\n\tfunc_alt8 = 8,\n\tfunc_aon_cpu_standbyb = 9,\n\tfunc_aon_fp_4sec_resetb = 10,\n\tfunc_aon_gpclk = 11,\n\tfunc_aon_pwm = 12,\n\tfunc_arm_jtag = 13,\n\tfunc_aud_fs_clk0 = 14,\n\tfunc_avs_pmu_bsc = 15,\n\tfunc_bsc_m0 = 16,\n\tfunc_bsc_m1 = 17,\n\tfunc_bsc_m2 = 18,\n\tfunc_bsc_m3 = 19,\n\tfunc_clk_observe = 20,\n\tfunc_ctl_hdmi_5v = 21,\n\tfunc_enet0 = 22,\n\tfunc_enet0_mii = 23,\n\tfunc_enet0_rgmii = 24,\n\tfunc_ext_sc_clk = 25,\n\tfunc_fl0 = 26,\n\tfunc_fl1 = 27,\n\tfunc_gpclk0 = 28,\n\tfunc_gpclk1 = 29,\n\tfunc_gpclk2 = 30,\n\tfunc_hdmi_tx0_auto_i2c = 31,\n\tfunc_hdmi_tx0_bsc = 32,\n\tfunc_hdmi_tx1_auto_i2c = 33,\n\tfunc_hdmi_tx1_bsc = 34,\n\tfunc_i2s_in = 35,\n\tfunc_i2s_out = 36,\n\tfunc_ir_in = 37,\n\tfunc_mtsif = 38,\n\tfunc_mtsif_alt = 39,\n\tfunc_mtsif_alt1 = 40,\n\tfunc_pdm = 41,\n\tfunc_pkt = 42,\n\tfunc_pm_led_out = 43,\n\tfunc_sc0 = 44,\n\tfunc_sd0 = 45,\n\tfunc_sd2 = 46,\n\tfunc_sd_card_a = 47,\n\tfunc_sd_card_b = 48,\n\tfunc_sd_card_c = 49,\n\tfunc_sd_card_d = 50,\n\tfunc_sd_card_e = 51,\n\tfunc_sd_card_f = 52,\n\tfunc_sd_card_g = 53,\n\tfunc_spdif_out = 54,\n\tfunc_spi_m = 55,\n\tfunc_spi_s = 56,\n\tfunc_sr_edm_sense = 57,\n\tfunc_te0 = 58,\n\tfunc_te1 = 59,\n\tfunc_tsio = 60,\n\tfunc_uart0 = 61,\n\tfunc_uart1 = 62,\n\tfunc_uart2 = 63,\n\tfunc_usb_pwr = 64,\n\tfunc_usb_vbus = 65,\n\tfunc_uui = 66,\n\tfunc_vc_i2c0 = 67,\n\tfunc_vc_i2c3 = 68,\n\tfunc_vc_i2c4 = 69,\n\tfunc_vc_i2c5 = 70,\n\tfunc_vc_i2csl = 71,\n\tfunc_vc_pcm = 72,\n\tfunc_vc_pwm0 = 73,\n\tfunc_vc_pwm1 = 74,\n\tfunc_vc_spi0 = 75,\n\tfunc_vc_spi3 = 76,\n\tfunc_vc_spi4 = 77,\n\tfunc_vc_spi5 = 78,\n\tfunc_vc_uart0 = 79,\n\tfunc_vc_uart2 = 80,\n\tfunc_vc_uart3 = 81,\n\tfunc_vc_uart4 = 82,\n\tfunc__ = 83,\n\tfunc_count = 83,\n};\n\nenum bcm2835_fsel {\n\tBCM2835_FSEL_COUNT = 8,\n\tBCM2835_FSEL_MASK = 7,\n};\n\nenum bcm_iproc_i2c_type {\n\tIPROC_I2C = 0,\n\tIPROC_I2C_NIC = 1,\n};\n\nenum bcm_usb_phy_ctrl_bits {\n\tCORERDY = 0,\n\tPHY_RESETB = 1,\n\tPHY_PCTL = 2,\n};\n\nenum bcm_usb_phy_reg {\n\tPLL_CTRL = 0,\n\tPHY_CTRL = 1,\n\tPHY_PLL_CTRL = 2,\n};\n\nenum bcm_usb_phy_type {\n\tUSB_HS_PHY = 0,\n\tUSB_SS_PHY = 1,\n};\n\nenum bcm_usb_phy_version {\n\tBCM_SR_USB_COMBO_PHY = 0,\n\tBCM_SR_USB_HS_PHY = 1,\n};\n\nenum bcma_hosttype {\n\tBCMA_HOSTTYPE_PCI = 0,\n\tBCMA_HOSTTYPE_SDIO = 1,\n\tBCMA_HOSTTYPE_SOC = 2,\n};\n\nenum bcmasp_stat_type {\n\tBCMASP_STAT_RX_CTRL = 0,\n\tBCMASP_STAT_RX_CTRL_PER_INTF = 1,\n\tBCMASP_STAT_SOFT = 2,\n};\n\nenum bd9571mwv_irqs {\n\tBD9571MWV_IRQ_MD1 = 0,\n\tBD9571MWV_IRQ_MD2_E1 = 1,\n\tBD9571MWV_IRQ_MD2_E2 = 2,\n\tBD9571MWV_IRQ_PROT_ERR = 3,\n\tBD9571MWV_IRQ_GP = 4,\n\tBD9571MWV_IRQ_128H_OF = 5,\n\tBD9571MWV_IRQ_WDT_OF = 6,\n\tBD9571MWV_IRQ_BKUP_TRG = 7,\n};\n\nenum bd9571mwv_regulators {\n\tVD09 = 0,\n\tVD18 = 1,\n\tVD25 = 2,\n\tVD33 = 3,\n\tDVFS = 4,\n};\n\nenum bdc_ep0_state {\n\tWAIT_FOR_SETUP = 0,\n\tWAIT_FOR_DATA_START = 1,\n\tWAIT_FOR_DATA_XMIT = 2,\n\tWAIT_FOR_STATUS_START = 3,\n\tWAIT_FOR_STATUS_XMIT = 4,\n\tSTATUS_PENDING = 5,\n};\n\nenum bdc_link_state {\n\tBDC_LINK_STATE_U0 = 0,\n\tBDC_LINK_STATE_U3 = 3,\n\tBDC_LINK_STATE_RX_DET = 5,\n\tBDC_LINK_STATE_RESUME = 15,\n};\n\nenum bdcr_cmd_class {\n\tBDCR_CMD_UNSPEC = 0,\n\tBDCR_CMD_MAC_FILTER = 1,\n\tBDCR_CMD_VLAN_FILTER = 2,\n\tBDCR_CMD_RSS = 3,\n\tBDCR_CMD_RFS = 4,\n\tBDCR_CMD_PORT_GCL = 5,\n\tBDCR_CMD_RECV_CLASSIFIER = 6,\n\tBDCR_CMD_STREAM_IDENTIFY = 7,\n\tBDCR_CMD_STREAM_FILTER = 8,\n\tBDCR_CMD_STREAM_GCL = 9,\n\tBDCR_CMD_FLOW_METER = 10,\n\t__BDCR_CMD_MAX_LEN = 11,\n\tBDCR_CMD_MAX_LEN = 10,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bfqq_expiration {\n\tBFQQE_TOO_IDLE = 0,\n\tBFQQE_BUDGET_TIMEOUT = 1,\n\tBFQQE_BUDGET_EXHAUSTED = 2,\n\tBFQQE_NO_MORE_REQUESTS = 3,\n\tBFQQE_PREEMPTED = 4,\n};\n\nenum bfqq_state_flags {\n\tBFQQF_just_created = 0,\n\tBFQQF_busy = 1,\n\tBFQQF_wait_request = 2,\n\tBFQQF_non_blocking_wait_rq = 3,\n\tBFQQF_fifo_expire = 4,\n\tBFQQF_has_short_ttime = 5,\n\tBFQQF_sync = 6,\n\tBFQQF_IO_bound = 7,\n\tBFQQF_in_large_burst = 8,\n\tBFQQF_softrt_update = 9,\n\tBFQQF_coop = 10,\n\tBFQQF_split_coop = 11,\n};\n\nenum bgmac_dma_ring_type {\n\tBGMAC_DMA_RING_TX = 0,\n\tBGMAC_DMA_RING_RX = 1,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bhb_mitigation_bits {\n\tBHB_LOOP = 0,\n\tBHB_FW = 1,\n\tBHB_HW = 2,\n\tBHB_INSN = 3,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nenum bios_platform_class {\n\tBIOS_CLIENT = 0,\n\tBIOS_SERVER = 1,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum bkops_status {\n\tBKOPS_STATUS_NO_OP = 0,\n\tBKOPS_STATUS_NON_CRITICAL = 1,\n\tBKOPS_STATUS_PERF_IMPACT = 2,\n\tBKOPS_STATUS_CRITICAL = 3,\n\tBKOPS_STATUS_MAX = 3,\n};\n\nenum blacklist_hash_type {\n\tBLACKLIST_HASH_X509_TBS = 1,\n\tBLACKLIST_HASH_BINARY = 2,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_req_status {\n\tREQ_PROCESSING = 0,\n\tREQ_WAITING = 1,\n\tREQ_DONE = 2,\n\tREQ_ERROR = 3,\n\tREQ_EOPNOTSUPP = 4,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blkg_iostat_type {\n\tBLKG_IOSTAT_READ = 0,\n\tBLKG_IOSTAT_WRITE = 1,\n\tBLKG_IOSTAT_DISCARD = 2,\n\tBLKG_IOSTAT_NR = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blkif_state {\n\tBLKIF_STATE_DISCONNECTED = 0,\n\tBLKIF_STATE_CONNECTED = 1,\n\tBLKIF_STATE_SUSPENDED = 2,\n\tBLKIF_STATE_ERROR = 3,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum bm_rcr_cmode {\n\tbm_rcr_cci = 0,\n\tbm_rcr_cce = 1,\n};\n\nenum bm_rcr_pmode {\n\tbm_rcr_pci = 0,\n\tbm_rcr_pce = 1,\n\tbm_rcr_pvb = 2,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_43bit_dma = 1,\n\tboard_ahci_ign_iferr = 2,\n\tboard_ahci_no_debounce_delay = 3,\n\tboard_ahci_no_msi = 4,\n\tboard_ahci_pcs_quirk = 5,\n\tboard_ahci_pcs_quirk_no_devslp = 6,\n\tboard_ahci_pcs_quirk_no_sntf = 7,\n\tboard_ahci_yes_fbs = 8,\n\tboard_ahci_yes_fbs_atapi_dma = 9,\n\tboard_ahci_al = 10,\n\tboard_ahci_avn = 11,\n\tboard_ahci_mcp65 = 12,\n\tboard_ahci_mcp77 = 13,\n\tboard_ahci_mcp89 = 14,\n\tboard_ahci_mv = 15,\n\tboard_ahci_sb600 = 16,\n\tboard_ahci_sb700 = 17,\n\tboard_ahci_vt8251 = 18,\n\tboard_ahci_mcp_linux = 12,\n\tboard_ahci_mcp67 = 12,\n\tboard_ahci_mcp73 = 12,\n\tboard_ahci_mcp79 = 13,\n};\n\nenum bp_state {\n\tBP_DONE = 0,\n\tBP_WAIT = 1,\n\tBP_EAGAIN = 2,\n\tBP_ECANCELED = 3,\n};\n\nenum bp_type_idx {\n\tTYPE_INST = 0,\n\tTYPE_DATA = 1,\n\tTYPE_MAX = 2,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_perf_event_type {\n\tBPF_PERF_EVENT_UNSPEC = 0,\n\tBPF_PERF_EVENT_UPROBE = 1,\n\tBPF_PERF_EVENT_URETPROBE = 2,\n\tBPF_PERF_EVENT_KPROBE = 3,\n\tBPF_PERF_EVENT_KRETPROBE = 4,\n\tBPF_PERF_EVENT_TRACEPOINT = 5,\n\tBPF_PERF_EVENT_EVENT = 6,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum bq27xxx_chip {\n\tBQ27000 = 1,\n\tBQ27010 = 2,\n\tBQ2750X = 3,\n\tBQ2751X = 4,\n\tBQ2752X = 5,\n\tBQ27500 = 6,\n\tBQ27510G1 = 7,\n\tBQ27510G2 = 8,\n\tBQ27510G3 = 9,\n\tBQ27520G1 = 10,\n\tBQ27520G2 = 11,\n\tBQ27520G3 = 12,\n\tBQ27520G4 = 13,\n\tBQ27521 = 14,\n\tBQ27530 = 15,\n\tBQ27531 = 16,\n\tBQ27541 = 17,\n\tBQ27542 = 18,\n\tBQ27546 = 19,\n\tBQ27742 = 20,\n\tBQ27545 = 21,\n\tBQ27411 = 22,\n\tBQ27421 = 23,\n\tBQ27425 = 24,\n\tBQ27426 = 25,\n\tBQ27441 = 26,\n\tBQ27621 = 27,\n\tBQ27Z561 = 28,\n\tBQ28Z610 = 29,\n\tBQ34Z100 = 30,\n\tBQ78Z100 = 31,\n};\n\nenum bq27xxx_dm_reg_id {\n\tBQ27XXX_DM_DESIGN_CAPACITY = 0,\n\tBQ27XXX_DM_DESIGN_ENERGY = 1,\n\tBQ27XXX_DM_TERMINATE_VOLTAGE = 2,\n};\n\nenum bq27xxx_reg_index {\n\tBQ27XXX_REG_CTRL = 0,\n\tBQ27XXX_REG_TEMP = 1,\n\tBQ27XXX_REG_INT_TEMP = 2,\n\tBQ27XXX_REG_VOLT = 3,\n\tBQ27XXX_REG_AI = 4,\n\tBQ27XXX_REG_FLAGS = 5,\n\tBQ27XXX_REG_TTE = 6,\n\tBQ27XXX_REG_TTF = 7,\n\tBQ27XXX_REG_TTES = 8,\n\tBQ27XXX_REG_TTECP = 9,\n\tBQ27XXX_REG_NAC = 10,\n\tBQ27XXX_REG_RC = 11,\n\tBQ27XXX_REG_FCC = 12,\n\tBQ27XXX_REG_CYCT = 13,\n\tBQ27XXX_REG_AE = 14,\n\tBQ27XXX_REG_SOC = 15,\n\tBQ27XXX_REG_DCAP = 16,\n\tBQ27XXX_REG_AP = 17,\n\tBQ27XXX_DM_CTRL = 18,\n\tBQ27XXX_DM_CLASS = 19,\n\tBQ27XXX_DM_BLOCK = 20,\n\tBQ27XXX_DM_DATA = 21,\n\tBQ27XXX_DM_CKSUM = 22,\n\tBQ27XXX_REG_SEDVF = 23,\n\tBQ27XXX_REG_PKCFG = 24,\n\tBQ27XXX_REG_MAX = 25,\n};\n\nenum brcm_family_type {\n\tBRCM_FAMILY_3390A0 = 0,\n\tBRCM_FAMILY_4908 = 1,\n\tBRCM_FAMILY_7250B0 = 2,\n\tBRCM_FAMILY_7271A0 = 3,\n\tBRCM_FAMILY_7364A0 = 4,\n\tBRCM_FAMILY_7366C0 = 5,\n\tBRCM_FAMILY_74371A0 = 6,\n\tBRCM_FAMILY_7439B0 = 7,\n\tBRCM_FAMILY_7445D0 = 8,\n\tBRCM_FAMILY_7260A0 = 9,\n\tBRCM_FAMILY_7278A0 = 10,\n\tBRCM_FAMILY_COUNT = 11,\n};\n\nenum brcm_sata_phy_rxaeq_mode {\n\tRXAEQ_MODE_OFF = 0,\n\tRXAEQ_MODE_AUTO = 1,\n\tRXAEQ_MODE_MANUAL = 2,\n};\n\nenum brcm_sata_phy_version {\n\tBRCM_SATA_PHY_STB_16NM = 0,\n\tBRCM_SATA_PHY_STB_28NM = 1,\n\tBRCM_SATA_PHY_STB_40NM = 2,\n\tBRCM_SATA_PHY_IPROC_NS2 = 3,\n\tBRCM_SATA_PHY_IPROC_NSP = 4,\n\tBRCM_SATA_PHY_IPROC_SR = 5,\n\tBRCM_SATA_PHY_DSL_28NM = 6,\n};\n\nenum brcm_usb_phy_id {\n\tBRCM_USB_PHY_2_0 = 0,\n\tBRCM_USB_PHY_3_0 = 1,\n\tBRCM_USB_PHY_ID_MAX = 2,\n};\n\nenum brcmstb_memc_hwtype {\n\tBRCMSTB_MEMC_V21 = 0,\n\tBRCMSTB_MEMC_V20 = 1,\n\tBRCMSTB_MEMC_V1X = 2,\n};\n\nenum brcmusb_reg_sel {\n\tBRCM_REGS_CTRL = 0,\n\tBRCM_REGS_XHCI_EC = 1,\n\tBRCM_REGS_XHCI_GBL = 2,\n\tBRCM_REGS_USB_PHY = 3,\n\tBRCM_REGS_USB_MDIO = 4,\n\tBRCM_REGS_BDC_EC = 5,\n\tBRCM_REGS_MAX = 6,\n};\n\nenum bsc_xfer_cmd {\n\tCMD_WR = 0,\n\tCMD_RD = 1,\n\tCMD_WR_NOACK = 2,\n\tCMD_RD_NOACK = 3,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum buf_type {\n\tTYPE_NETSEC_SKB = 0,\n\tTYPE_NETSEC_XDP_TX = 1,\n\tTYPE_NETSEC_XDP_NDO = 2,\n};\n\nenum buffer_map_state {\n\tUN_MAPPED = 0,\n\tPRE_MAPPED = 1,\n\tMUSB_MAPPED = 2,\n};\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum bus_speeds {\n\tSPD_375K = 0,\n\tSPD_390K = 1,\n\tSPD_187K = 2,\n\tSPD_200K = 3,\n\tSPD_93K = 4,\n\tSPD_97K = 5,\n\tSPD_46K = 6,\n\tSPD_50K = 7,\n};\n\nenum cache_indexing {\n\tNODE_CACHE_DIRECT_MAP = 0,\n\tNODE_CACHE_INDEXED = 1,\n\tNODE_CACHE_OTHER = 2,\n};\n\nenum cache_mode {\n\tNODE_CACHE_ADDR_MODE_RESERVED = 0,\n\tNODE_CACHE_ADDR_MODE_EXTENDED_LINEAR = 1,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum cache_write_policy {\n\tNODE_CACHE_WRITE_BACK = 0,\n\tNODE_CACHE_WRITE_THROUGH = 1,\n\tNODE_CACHE_WRITE_OTHER = 2,\n};\n\nenum cavium_mdiobus_mode {\n\tUNINIT = 0,\n\tC22 = 1,\n\tC45 = 2,\n};\n\nenum cc_attr {\n\tCC_ATTR_MEM_ENCRYPT = 0,\n\tCC_ATTR_HOST_MEM_ENCRYPT = 1,\n\tCC_ATTR_GUEST_MEM_ENCRYPT = 2,\n\tCC_ATTR_GUEST_STATE_ENCRYPT = 3,\n\tCC_ATTR_GUEST_UNROLL_STRING_IO = 4,\n\tCC_ATTR_GUEST_SEV_SNP = 5,\n\tCC_ATTR_GUEST_SNP_SECURE_TSC = 6,\n\tCC_ATTR_HOST_SEV_SNP = 7,\n\tCC_ATTR_SNP_SECURE_AVIC = 8,\n};\n\nenum cd_types {\n\tESDHC_CD_NONE = 0,\n\tESDHC_CD_CONTROLLER = 1,\n\tESDHC_CD_GPIO = 2,\n\tESDHC_CD_PERMANENT = 3,\n};\n\nenum cfg_core_ver {\n\tSDIO_CFG_CORE_V1 = 1,\n\tSDIO_CFG_CORE_V2 = 2,\n};\n\nenum cfi_quirks {\n\tCFI_QUIRK_DQ_TRUE_DATA = 1,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_bpf_attach_type {\n\tCGROUP_BPF_ATTACH_TYPE_INVALID = -1,\n\tCGROUP_INET_INGRESS = 0,\n\tCGROUP_INET_EGRESS = 1,\n\tCGROUP_INET_SOCK_CREATE = 2,\n\tCGROUP_SOCK_OPS = 3,\n\tCGROUP_DEVICE = 4,\n\tCGROUP_INET4_BIND = 5,\n\tCGROUP_INET6_BIND = 6,\n\tCGROUP_INET4_CONNECT = 7,\n\tCGROUP_INET6_CONNECT = 8,\n\tCGROUP_UNIX_CONNECT = 9,\n\tCGROUP_INET4_POST_BIND = 10,\n\tCGROUP_INET6_POST_BIND = 11,\n\tCGROUP_UDP4_SENDMSG = 12,\n\tCGROUP_UDP6_SENDMSG = 13,\n\tCGROUP_UNIX_SENDMSG = 14,\n\tCGROUP_SYSCTL = 15,\n\tCGROUP_UDP4_RECVMSG = 16,\n\tCGROUP_UDP6_RECVMSG = 17,\n\tCGROUP_UNIX_RECVMSG = 18,\n\tCGROUP_GETSOCKOPT = 19,\n\tCGROUP_SETSOCKOPT = 20,\n\tCGROUP_INET4_GETPEERNAME = 21,\n\tCGROUP_INET6_GETPEERNAME = 22,\n\tCGROUP_UNIX_GETPEERNAME = 23,\n\tCGROUP_INET4_GETSOCKNAME = 24,\n\tCGROUP_INET6_GETSOCKNAME = 25,\n\tCGROUP_UNIX_GETSOCKNAME = 26,\n\tCGROUP_INET_SOCK_RELEASE = 27,\n\tCGROUP_LSM_START = 28,\n\tCGROUP_LSM_END = 27,\n\tMAX_CGROUP_BPF_ATTACH_TYPE = 28,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_COUNT = 0,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tio_cgrp_id = 3,\n\tmemory_cgrp_id = 4,\n\tdevices_cgrp_id = 5,\n\tfreezer_cgrp_id = 6,\n\tperf_event_cgrp_id = 7,\n\thugetlb_cgrp_id = 8,\n\tpids_cgrp_id = 9,\n\tCGROUP_SUBSYS_COUNT = 10,\n};\n\nenum cgt_group_id {\n\t__RESERVED__ = 0,\n\tCGT_HCR_TID1 = 1,\n\tCGT_HCR_TID2 = 2,\n\tCGT_HCR_TID3 = 3,\n\tCGT_HCR_IMO = 4,\n\tCGT_HCR_FMO = 5,\n\tCGT_HCR_TIDCP = 6,\n\tCGT_HCR_TACR = 7,\n\tCGT_HCR_TSW = 8,\n\tCGT_HCR_TPC = 9,\n\tCGT_HCR_TPU = 10,\n\tCGT_HCR_TTLB = 11,\n\tCGT_HCR_TVM = 12,\n\tCGT_HCR_TDZ = 13,\n\tCGT_HCR_TRVM = 14,\n\tCGT_HCR_TLOR = 15,\n\tCGT_HCR_TERR = 16,\n\tCGT_HCR_APK = 17,\n\tCGT_HCR_NV = 18,\n\tCGT_HCR_NV_nNV2 = 19,\n\tCGT_HCR_NV1_nNV2 = 20,\n\tCGT_HCR_AT = 21,\n\tCGT_HCR_nFIEN = 22,\n\tCGT_HCR_TID4 = 23,\n\tCGT_HCR_TICAB = 24,\n\tCGT_HCR_TOCU = 25,\n\tCGT_HCR_ENSCXT = 26,\n\tCGT_HCR_TTLBIS = 27,\n\tCGT_HCR_TTLBOS = 28,\n\tCGT_HCR_TID5 = 29,\n\tCGT_MDCR_TPMCR = 30,\n\tCGT_MDCR_TPM = 31,\n\tCGT_MDCR_TDE = 32,\n\tCGT_MDCR_TDA = 33,\n\tCGT_MDCR_TDOSA = 34,\n\tCGT_MDCR_TDRA = 35,\n\tCGT_MDCR_E2PB = 36,\n\tCGT_MDCR_TPMS = 37,\n\tCGT_MDCR_TTRF = 38,\n\tCGT_MDCR_E2TB = 39,\n\tCGT_MDCR_TDCC = 40,\n\tCGT_CPTR_TAM = 41,\n\tCGT_CPTR_TCPAC = 42,\n\tCGT_HCRX_EnFPM = 43,\n\tCGT_HCRX_TCR2En = 44,\n\tCGT_HCRX_SCTLR2En = 45,\n\tCGT_CNTHCTL_EL1TVT = 46,\n\tCGT_CNTHCTL_EL1TVCT = 47,\n\tCGT_ICH_HCR_TC = 48,\n\tCGT_ICH_HCR_TALL0 = 49,\n\tCGT_ICH_HCR_TALL1 = 50,\n\tCGT_ICH_HCR_TDIR = 51,\n\t__MULTIPLE_CONTROL_BITS__ = 52,\n\tCGT_HCR_IMO_FMO_ICH_HCR_TC = 52,\n\tCGT_HCR_TID2_TID4 = 53,\n\tCGT_HCR_TTLB_TTLBIS = 54,\n\tCGT_HCR_TTLB_TTLBOS = 55,\n\tCGT_HCR_TVM_TRVM = 56,\n\tCGT_HCR_TVM_TRVM_HCRX_TCR2En = 57,\n\tCGT_HCR_TVM_TRVM_HCRX_SCTLR2En = 58,\n\tCGT_HCR_TPU_TICAB = 59,\n\tCGT_HCR_TPU_TOCU = 60,\n\tCGT_HCR_NV1_nNV2_ENSCXT = 61,\n\tCGT_MDCR_TPM_TPMCR = 62,\n\tCGT_MDCR_TPM_HPMN = 63,\n\tCGT_MDCR_TDE_TDA = 64,\n\tCGT_MDCR_TDE_TDOSA = 65,\n\tCGT_MDCR_TDE_TDRA = 66,\n\tCGT_MDCR_TDCC_TDE_TDA = 67,\n\tCGT_ICH_HCR_TC_TDIR = 68,\n\t__COMPLEX_CONDITIONS__ = 69,\n\tCGT_CNTHCTL_EL1PCTEN = 69,\n\tCGT_CNTHCTL_EL1PTEN = 70,\n\tCGT_CNTHCTL_EL1NVPCT = 71,\n\tCGT_CNTHCTL_EL1NVVCT = 72,\n\tCGT_CPTR_TTA = 73,\n\tCGT_MDCR_HPMN = 74,\n\t__NR_CGT_GROUP_IDS__ = 75,\n};\n\nenum ch_command {\n\tHIDMA_CH_DISABLE = 0,\n\tHIDMA_CH_ENABLE = 1,\n\tHIDMA_CH_SUSPEND = 2,\n\tHIDMA_CH_RESET = 9,\n};\n\nenum ch_state {\n\tHIDMA_CH_DISABLED = 0,\n\tHIDMA_CH_ENABLED = 1,\n\tHIDMA_CH_RUNNING = 2,\n\tHIDMA_CH_SUSPENDED = 3,\n\tHIDMA_CH_STOPPED = 4,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum chip_id {\n\tMT6323_CHIP_ID = 35,\n\tMT6328_CHIP_ID = 48,\n\tMT6331_CHIP_ID = 32,\n\tMT6332_CHIP_ID = 32,\n\tMT6357_CHIP_ID = 87,\n\tMT6358_CHIP_ID = 88,\n\tMT6359_CHIP_ID = 89,\n\tMT6366_CHIP_ID = 102,\n\tMT6391_CHIP_ID = 145,\n\tMT6397_CHIP_ID = 151,\n};\n\nenum chips {\n\tPFUZE100 = 0,\n\tPFUZE200 = 1,\n\tPFUZE3000 = 3,\n\tPFUZE3001 = 49,\n};\n\nenum ci_hw_regs {\n\tCAP_CAPLENGTH = 0,\n\tCAP_HCCPARAMS = 1,\n\tCAP_DCCPARAMS = 2,\n\tCAP_TESTMODE = 3,\n\tCAP_LAST = 3,\n\tOP_USBCMD = 4,\n\tOP_USBSTS = 5,\n\tOP_USBINTR = 6,\n\tOP_FRINDEX = 7,\n\tOP_DEVICEADDR = 8,\n\tOP_ENDPTLISTADDR = 9,\n\tOP_TTCTRL = 10,\n\tOP_BURSTSIZE = 11,\n\tOP_ULPI_VIEWPORT = 12,\n\tOP_PORTSC = 13,\n\tOP_DEVLC = 14,\n\tOP_OTGSC = 15,\n\tOP_USBMODE = 16,\n\tOP_ENDPTSETUPSTAT = 17,\n\tOP_ENDPTPRIME = 18,\n\tOP_ENDPTFLUSH = 19,\n\tOP_ENDPTSTAT = 20,\n\tOP_ENDPTCOMPLETE = 21,\n\tOP_ENDPTCTRL = 22,\n\tOP_LAST = 38,\n};\n\nenum ci_revision {\n\tCI_REVISION_1X = 10,\n\tCI_REVISION_20 = 20,\n\tCI_REVISION_21 = 21,\n\tCI_REVISION_22 = 22,\n\tCI_REVISION_23 = 23,\n\tCI_REVISION_24 = 24,\n\tCI_REVISION_25 = 25,\n\tCI_REVISION_25_PLUS = 26,\n\tCI_REVISION_UNKNOWN = 99,\n};\n\nenum ci_role {\n\tCI_ROLE_HOST = 0,\n\tCI_ROLE_GADGET = 1,\n\tCI_ROLE_END = 2,\n};\n\nenum cix_mbox_chan_type {\n\tCIX_MBOX_TYPE_DB = 0,\n\tCIX_MBOX_TYPE_REG = 1,\n\tCIX_MBOX_TYPE_FIFO = 2,\n\tCIX_MBOX_TYPE_FAST = 3,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clk_gating_state {\n\tCLKS_OFF = 0,\n\tCLKS_ON = 1,\n\tREQ_CLKS_OFF = 2,\n\tREQ_CLKS_ON = 3,\n};\n\nenum clk_id {\n\ttegra_clk_actmon = 0,\n\ttegra_clk_adx = 1,\n\ttegra_clk_adx1 = 2,\n\ttegra_clk_afi = 3,\n\ttegra_clk_amx = 4,\n\ttegra_clk_amx1 = 5,\n\ttegra_clk_apb2ape = 6,\n\ttegra_clk_ahbdma = 7,\n\ttegra_clk_apbdma = 8,\n\ttegra_clk_apbif = 9,\n\ttegra_clk_ape = 10,\n\ttegra_clk_audio0 = 11,\n\ttegra_clk_audio0_2x = 12,\n\ttegra_clk_audio0_mux = 13,\n\ttegra_clk_audio1 = 14,\n\ttegra_clk_audio1_2x = 15,\n\ttegra_clk_audio1_mux = 16,\n\ttegra_clk_audio2 = 17,\n\ttegra_clk_audio2_2x = 18,\n\ttegra_clk_audio2_mux = 19,\n\ttegra_clk_audio3 = 20,\n\ttegra_clk_audio3_2x = 21,\n\ttegra_clk_audio3_mux = 22,\n\ttegra_clk_audio4 = 23,\n\ttegra_clk_audio4_2x = 24,\n\ttegra_clk_audio4_mux = 25,\n\ttegra_clk_bsea = 26,\n\ttegra_clk_bsev = 27,\n\ttegra_clk_cclk_g = 28,\n\ttegra_clk_cclk_lp = 29,\n\ttegra_clk_cilab = 30,\n\ttegra_clk_cilcd = 31,\n\ttegra_clk_cile = 32,\n\ttegra_clk_clk_32k = 33,\n\ttegra_clk_clk72Mhz = 34,\n\ttegra_clk_clk72Mhz_8 = 35,\n\ttegra_clk_clk_m = 36,\n\ttegra_clk_osc = 37,\n\ttegra_clk_osc_div2 = 38,\n\ttegra_clk_osc_div4 = 39,\n\ttegra_clk_cml0 = 40,\n\ttegra_clk_cml1 = 41,\n\ttegra_clk_csi = 42,\n\ttegra_clk_csite = 43,\n\ttegra_clk_csite_8 = 44,\n\ttegra_clk_csus = 45,\n\ttegra_clk_cve = 46,\n\ttegra_clk_dam0 = 47,\n\ttegra_clk_dam1 = 48,\n\ttegra_clk_dam2 = 49,\n\ttegra_clk_d_audio = 50,\n\ttegra_clk_dbgapb = 51,\n\ttegra_clk_dds = 52,\n\ttegra_clk_dfll_ref = 53,\n\ttegra_clk_dfll_soc = 54,\n\ttegra_clk_disp1 = 55,\n\ttegra_clk_disp1_8 = 56,\n\ttegra_clk_disp2 = 57,\n\ttegra_clk_disp2_8 = 58,\n\ttegra_clk_dp2 = 59,\n\ttegra_clk_dpaux = 60,\n\ttegra_clk_dpaux1 = 61,\n\ttegra_clk_dsialp = 62,\n\ttegra_clk_dsia_mux = 63,\n\ttegra_clk_dsiblp = 64,\n\ttegra_clk_dsib_mux = 65,\n\ttegra_clk_dtv = 66,\n\ttegra_clk_emc = 67,\n\ttegra_clk_entropy = 68,\n\ttegra_clk_entropy_8 = 69,\n\ttegra_clk_epp = 70,\n\ttegra_clk_epp_8 = 71,\n\ttegra_clk_extern1 = 72,\n\ttegra_clk_extern2 = 73,\n\ttegra_clk_extern3 = 74,\n\ttegra_clk_fuse = 75,\n\ttegra_clk_fuse_burn = 76,\n\ttegra_clk_gpu = 77,\n\ttegra_clk_gr2d = 78,\n\ttegra_clk_gr2d_8 = 79,\n\ttegra_clk_gr3d = 80,\n\ttegra_clk_gr3d_8 = 81,\n\ttegra_clk_hclk = 82,\n\ttegra_clk_hda = 83,\n\ttegra_clk_hda_8 = 84,\n\ttegra_clk_hda2codec_2x = 85,\n\ttegra_clk_hda2codec_2x_8 = 86,\n\ttegra_clk_hda2hdmi = 87,\n\ttegra_clk_hdmi = 88,\n\ttegra_clk_hdmi_audio = 89,\n\ttegra_clk_host1x = 90,\n\ttegra_clk_host1x_8 = 91,\n\ttegra_clk_host1x_9 = 92,\n\ttegra_clk_hsic_trk = 93,\n\ttegra_clk_i2c1 = 94,\n\ttegra_clk_i2c2 = 95,\n\ttegra_clk_i2c3 = 96,\n\ttegra_clk_i2c4 = 97,\n\ttegra_clk_i2c5 = 98,\n\ttegra_clk_i2c6 = 99,\n\ttegra_clk_i2cslow = 100,\n\ttegra_clk_i2s0 = 101,\n\ttegra_clk_i2s0_sync = 102,\n\ttegra_clk_i2s1 = 103,\n\ttegra_clk_i2s1_sync = 104,\n\ttegra_clk_i2s2 = 105,\n\ttegra_clk_i2s2_sync = 106,\n\ttegra_clk_i2s3 = 107,\n\ttegra_clk_i2s3_sync = 108,\n\ttegra_clk_i2s4 = 109,\n\ttegra_clk_i2s4_sync = 110,\n\ttegra_clk_isp = 111,\n\ttegra_clk_isp_8 = 112,\n\ttegra_clk_isp_9 = 113,\n\ttegra_clk_ispb = 114,\n\ttegra_clk_kbc = 115,\n\ttegra_clk_kfuse = 116,\n\ttegra_clk_la = 117,\n\ttegra_clk_maud = 118,\n\ttegra_clk_mipi = 119,\n\ttegra_clk_mipibif = 120,\n\ttegra_clk_mipi_cal = 121,\n\ttegra_clk_mpe = 122,\n\ttegra_clk_mselect = 123,\n\ttegra_clk_msenc = 124,\n\ttegra_clk_ndflash = 125,\n\ttegra_clk_ndflash_8 = 126,\n\ttegra_clk_ndspeed = 127,\n\ttegra_clk_ndspeed_8 = 128,\n\ttegra_clk_nor = 129,\n\ttegra_clk_nvdec = 130,\n\ttegra_clk_nvenc = 131,\n\ttegra_clk_nvjpg = 132,\n\ttegra_clk_owr = 133,\n\ttegra_clk_owr_8 = 134,\n\ttegra_clk_pcie = 135,\n\ttegra_clk_pclk = 136,\n\ttegra_clk_pll_a = 137,\n\ttegra_clk_pll_a_out0 = 138,\n\ttegra_clk_pll_a1 = 139,\n\ttegra_clk_pll_c = 140,\n\ttegra_clk_pll_c2 = 141,\n\ttegra_clk_pll_c3 = 142,\n\ttegra_clk_pll_c4 = 143,\n\ttegra_clk_pll_c4_out0 = 144,\n\ttegra_clk_pll_c4_out1 = 145,\n\ttegra_clk_pll_c4_out2 = 146,\n\ttegra_clk_pll_c4_out3 = 147,\n\ttegra_clk_pll_c_out1 = 148,\n\ttegra_clk_pll_d = 149,\n\ttegra_clk_pll_d2 = 150,\n\ttegra_clk_pll_d2_out0 = 151,\n\ttegra_clk_pll_d_out0 = 152,\n\ttegra_clk_pll_dp = 153,\n\ttegra_clk_pll_e_out0 = 154,\n\ttegra_clk_pll_g_ref = 155,\n\ttegra_clk_pll_m = 156,\n\ttegra_clk_pll_m_out1 = 157,\n\ttegra_clk_pll_mb = 158,\n\ttegra_clk_pll_p = 159,\n\ttegra_clk_pll_p_out1 = 160,\n\ttegra_clk_pll_p_out2 = 161,\n\ttegra_clk_pll_p_out2_int = 162,\n\ttegra_clk_pll_p_out3 = 163,\n\ttegra_clk_pll_p_out4 = 164,\n\ttegra_clk_pll_p_out4_cpu = 165,\n\ttegra_clk_pll_p_out5 = 166,\n\ttegra_clk_pll_p_out_hsio = 167,\n\ttegra_clk_pll_p_out_xusb = 168,\n\ttegra_clk_pll_p_out_cpu = 169,\n\ttegra_clk_pll_p_out_adsp = 170,\n\ttegra_clk_pll_ref = 171,\n\ttegra_clk_pll_re_out = 172,\n\ttegra_clk_pll_re_vco = 173,\n\ttegra_clk_pll_u = 174,\n\ttegra_clk_pll_u_out = 175,\n\ttegra_clk_pll_u_out1 = 176,\n\ttegra_clk_pll_u_out2 = 177,\n\ttegra_clk_pll_u_12m = 178,\n\ttegra_clk_pll_u_480m = 179,\n\ttegra_clk_pll_u_48m = 180,\n\ttegra_clk_pll_u_60m = 181,\n\ttegra_clk_pll_x = 182,\n\ttegra_clk_pll_x_out0 = 183,\n\ttegra_clk_pwm = 184,\n\ttegra_clk_qspi = 185,\n\ttegra_clk_rtc = 186,\n\ttegra_clk_sata = 187,\n\ttegra_clk_sata_8 = 188,\n\ttegra_clk_sata_cold = 189,\n\ttegra_clk_sata_oob = 190,\n\ttegra_clk_sata_oob_8 = 191,\n\ttegra_clk_sbc1 = 192,\n\ttegra_clk_sbc1_8 = 193,\n\ttegra_clk_sbc1_9 = 194,\n\ttegra_clk_sbc2 = 195,\n\ttegra_clk_sbc2_8 = 196,\n\ttegra_clk_sbc2_9 = 197,\n\ttegra_clk_sbc3 = 198,\n\ttegra_clk_sbc3_8 = 199,\n\ttegra_clk_sbc3_9 = 200,\n\ttegra_clk_sbc4 = 201,\n\ttegra_clk_sbc4_8 = 202,\n\ttegra_clk_sbc4_9 = 203,\n\ttegra_clk_sbc5 = 204,\n\ttegra_clk_sbc5_8 = 205,\n\ttegra_clk_sbc6 = 206,\n\ttegra_clk_sbc6_8 = 207,\n\ttegra_clk_sclk = 208,\n\ttegra_clk_sdmmc_legacy = 209,\n\ttegra_clk_sdmmc1 = 210,\n\ttegra_clk_sdmmc1_8 = 211,\n\ttegra_clk_sdmmc1_9 = 212,\n\ttegra_clk_sdmmc2 = 213,\n\ttegra_clk_sdmmc2_8 = 214,\n\ttegra_clk_sdmmc3 = 215,\n\ttegra_clk_sdmmc3_8 = 216,\n\ttegra_clk_sdmmc3_9 = 217,\n\ttegra_clk_sdmmc4 = 218,\n\ttegra_clk_sdmmc4_8 = 219,\n\ttegra_clk_se = 220,\n\ttegra_clk_se_10 = 221,\n\ttegra_clk_soc_therm = 222,\n\ttegra_clk_soc_therm_8 = 223,\n\ttegra_clk_sor0 = 224,\n\ttegra_clk_sor0_out = 225,\n\ttegra_clk_sor1 = 226,\n\ttegra_clk_sor1_out = 227,\n\ttegra_clk_spdif = 228,\n\ttegra_clk_spdif_2x = 229,\n\ttegra_clk_spdif_in = 230,\n\ttegra_clk_spdif_in_8 = 231,\n\ttegra_clk_spdif_in_sync = 232,\n\ttegra_clk_spdif_mux = 233,\n\ttegra_clk_spdif_out = 234,\n\ttegra_clk_timer = 235,\n\ttegra_clk_trace = 236,\n\ttegra_clk_tsec = 237,\n\ttegra_clk_tsec_8 = 238,\n\ttegra_clk_tsecb = 239,\n\ttegra_clk_tsensor = 240,\n\ttegra_clk_tvdac = 241,\n\ttegra_clk_tvo = 242,\n\ttegra_clk_uarta = 243,\n\ttegra_clk_uarta_8 = 244,\n\ttegra_clk_uartb = 245,\n\ttegra_clk_uartb_8 = 246,\n\ttegra_clk_uartc = 247,\n\ttegra_clk_uartc_8 = 248,\n\ttegra_clk_uartd = 249,\n\ttegra_clk_uartd_8 = 250,\n\ttegra_clk_uarte = 251,\n\ttegra_clk_uarte_8 = 252,\n\ttegra_clk_uartape = 253,\n\ttegra_clk_usb2 = 254,\n\ttegra_clk_usb2_hsic_trk = 255,\n\ttegra_clk_usb2_trk = 256,\n\ttegra_clk_usb3 = 257,\n\ttegra_clk_usbd = 258,\n\ttegra_clk_vcp = 259,\n\ttegra_clk_vde = 260,\n\ttegra_clk_vde_8 = 261,\n\ttegra_clk_vfir = 262,\n\ttegra_clk_vi = 263,\n\ttegra_clk_vi_8 = 264,\n\ttegra_clk_vi_9 = 265,\n\ttegra_clk_vi_10 = 266,\n\ttegra_clk_vi_i2c = 267,\n\ttegra_clk_vic03 = 268,\n\ttegra_clk_vic03_8 = 269,\n\ttegra_clk_vim2_clk = 270,\n\ttegra_clk_vimclk_sync = 271,\n\ttegra_clk_vi_sensor = 272,\n\ttegra_clk_vi_sensor_8 = 273,\n\ttegra_clk_vi_sensor_9 = 274,\n\ttegra_clk_vi_sensor2 = 275,\n\ttegra_clk_vi_sensor2_8 = 276,\n\ttegra_clk_xusb_dev = 277,\n\ttegra_clk_xusb_dev_src = 278,\n\ttegra_clk_xusb_dev_src_8 = 279,\n\ttegra_clk_xusb_falcon_src = 280,\n\ttegra_clk_xusb_falcon_src_8 = 281,\n\ttegra_clk_xusb_fs_src = 282,\n\ttegra_clk_xusb_gate = 283,\n\ttegra_clk_xusb_host = 284,\n\ttegra_clk_xusb_host_src = 285,\n\ttegra_clk_xusb_host_src_8 = 286,\n\ttegra_clk_xusb_hs_src = 287,\n\ttegra_clk_xusb_hs_src_4 = 288,\n\ttegra_clk_xusb_ss = 289,\n\ttegra_clk_xusb_ss_src = 290,\n\ttegra_clk_xusb_ss_src_8 = 291,\n\ttegra_clk_xusb_ss_div2 = 292,\n\ttegra_clk_xusb_ssp_src = 293,\n\ttegra_clk_sclk_mux = 294,\n\ttegra_clk_sor_safe = 295,\n\ttegra_clk_cec = 296,\n\ttegra_clk_ispa = 297,\n\ttegra_clk_dmic1 = 298,\n\ttegra_clk_dmic2 = 299,\n\ttegra_clk_dmic3 = 300,\n\ttegra_clk_dmic1_sync_clk = 301,\n\ttegra_clk_dmic2_sync_clk = 302,\n\ttegra_clk_dmic3_sync_clk = 303,\n\ttegra_clk_dmic1_sync_clk_mux = 304,\n\ttegra_clk_dmic2_sync_clk_mux = 305,\n\ttegra_clk_dmic3_sync_clk_mux = 306,\n\ttegra_clk_iqc1 = 307,\n\ttegra_clk_iqc2 = 308,\n\ttegra_clk_pll_a_out_adsp = 309,\n\ttegra_clk_pll_a_out0_out_adsp = 310,\n\ttegra_clk_adsp = 311,\n\ttegra_clk_adsp_neon = 312,\n\ttegra_clk_max = 313,\n};\n\nenum clk_id___2 {\n\tCLK_NONE = 0,\n\tCLK_MM = 1,\n\tCLK_MFG = 2,\n\tCLK_VENC = 3,\n\tCLK_VENC_LT = 4,\n\tCLK_ETHIF = 5,\n\tCLK_VDEC = 6,\n\tCLK_HIFSEL = 7,\n\tCLK_JPGDEC = 8,\n\tCLK_AUDIO = 9,\n\tCLK_MAX = 10,\n};\n\nenum clk_ids {\n\tLAST_DT_CORE_CLK = 18,\n\tCLK_EXTAL = 19,\n\tCLK_OSC_DIV1000 = 20,\n\tCLK_PLL1 = 21,\n\tCLK_PLL2 = 22,\n\tCLK_PLL2_DIV2 = 23,\n\tCLK_PLL2_DIV2_8 = 24,\n\tCLK_PLL2_DIV2_10 = 25,\n\tCLK_PLL3 = 26,\n\tCLK_PLL3_400 = 27,\n\tCLK_PLL3_533 = 28,\n\tCLK_PLL3_DIV2 = 29,\n\tCLK_PLL3_DIV2_4 = 30,\n\tCLK_PLL3_DIV2_4_2 = 31,\n\tCLK_SEL_PLL3_3 = 32,\n\tCLK_DIV_PLL3_C = 33,\n\tCLK_M2_DIV2 = 34,\n\tCLK_PLL5 = 35,\n\tCLK_PLL5_500 = 36,\n\tCLK_PLL5_250 = 37,\n\tCLK_PLL5_FOUTPOSTDIV = 38,\n\tCLK_DSI_DIV = 39,\n\tCLK_PLL6 = 40,\n\tCLK_PLL6_250 = 41,\n\tCLK_P1_DIV2 = 42,\n\tCLK_PLL2_800 = 43,\n\tCLK_PLL2_SDHI_533 = 44,\n\tCLK_PLL2_SDHI_400 = 45,\n\tCLK_PLL2_SDHI_266 = 46,\n\tCLK_SD0_DIV4 = 47,\n\tCLK_SD1_DIV4 = 48,\n\tMOD_CLK_BASE = 49,\n};\n\nenum clk_ids___2 {\n\tLAST_DT_CORE_CLK___2 = 43,\n\tCLK_EXTAL___2 = 44,\n\tCLK_EXTALR = 45,\n\tCLK_MAIN = 46,\n\tCLK_PLL1___2 = 47,\n\tCLK_PLL20 = 48,\n\tCLK_PLL21 = 49,\n\tCLK_PLL30 = 50,\n\tCLK_PLL31 = 51,\n\tCLK_PLL4 = 52,\n\tCLK_PLL5___2 = 53,\n\tCLK_PLL1_DIV2 = 54,\n\tCLK_PLL20_DIV2 = 55,\n\tCLK_PLL21_DIV2 = 56,\n\tCLK_PLL30_DIV2 = 57,\n\tCLK_PLL31_DIV2 = 58,\n\tCLK_PLL5_DIV2 = 59,\n\tCLK_PLL5_DIV4 = 60,\n\tCLK_S1 = 61,\n\tCLK_S3 = 62,\n\tCLK_SDSRC = 63,\n\tCLK_RPCSRC = 64,\n\tCLK_OCO = 65,\n\tMOD_CLK_BASE___2 = 66,\n};\n\nenum clk_ids___3 {\n\tLAST_DT_CORE_CLK___3 = 25,\n\tCLK_EXTAL___3 = 26,\n\tCLK_OSC_DIV1000___2 = 27,\n\tCLK_PLL1___3 = 28,\n\tCLK_PLL2___2 = 29,\n\tCLK_PLL2_DIV2___2 = 30,\n\tCLK_PLL2_DIV2_8___2 = 31,\n\tCLK_PLL2_DIV2_10___2 = 32,\n\tCLK_PLL3___2 = 33,\n\tCLK_PLL3_400___2 = 34,\n\tCLK_PLL3_533___2 = 35,\n\tCLK_M2_DIV2___2 = 36,\n\tCLK_PLL3_DIV2___2 = 37,\n\tCLK_PLL3_DIV2_2 = 38,\n\tCLK_PLL3_DIV2_4___2 = 39,\n\tCLK_PLL3_DIV2_4_2___2 = 40,\n\tCLK_SEL_PLL3_3___2 = 41,\n\tCLK_DIV_PLL3_C___2 = 42,\n\tCLK_PLL4___2 = 43,\n\tCLK_PLL5___3 = 44,\n\tCLK_PLL5_FOUTPOSTDIV___2 = 45,\n\tCLK_PLL5_FOUT1PH0 = 46,\n\tCLK_PLL5_FOUT3 = 47,\n\tCLK_PLL5_250___2 = 48,\n\tCLK_PLL6___2 = 49,\n\tCLK_PLL6_250___2 = 50,\n\tCLK_P1_DIV2___2 = 51,\n\tCLK_PLL2_800___2 = 52,\n\tCLK_PLL2_SDHI_533___2 = 53,\n\tCLK_PLL2_SDHI_400___2 = 54,\n\tCLK_PLL2_SDHI_266___2 = 55,\n\tCLK_SD0_DIV4___2 = 56,\n\tCLK_SD1_DIV4___2 = 57,\n\tCLK_SEL_GPU2 = 58,\n\tCLK_SEL_PLL5_4 = 59,\n\tCLK_DSI_DIV___2 = 60,\n\tCLK_PLL2_533 = 61,\n\tCLK_PLL2_533_DIV2 = 62,\n\tCLK_DIV_DSI_LPCLK = 63,\n\tMOD_CLK_BASE___3 = 64,\n};\n\nenum clk_ids___4 {\n\tLAST_DT_CORE_CLK___4 = 30,\n\tCLK_EXTAL___4 = 31,\n\tCLK_EXTALR___2 = 32,\n\tCLK_MAIN___2 = 33,\n\tCLK_PLL0 = 34,\n\tCLK_PLL1___4 = 35,\n\tCLK_PLL3___3 = 36,\n\tCLK_PLL1_DIV2___2 = 37,\n\tCLK_PLL1_DIV4 = 38,\n\tMOD_CLK_BASE___4 = 39,\n};\n\nenum clk_ids___5 {\n\tLAST_DT_CORE_CLK___5 = 77,\n\tCLK_EXTAL___5 = 78,\n\tCLK_EXTALR___3 = 79,\n\tCLK_MAIN___3 = 80,\n\tCLK_PLL1___5 = 81,\n\tCLK_PLL2___3 = 82,\n\tCLK_PLL3___4 = 83,\n\tCLK_PLL4___3 = 84,\n\tCLK_PLL5___4 = 85,\n\tCLK_PLL6___3 = 86,\n\tCLK_PLL1_DIV2___3 = 87,\n\tCLK_PLL2_DIV2___3 = 88,\n\tCLK_PLL3_DIV2___3 = 89,\n\tCLK_PLL4_DIV2 = 90,\n\tCLK_PLL5_DIV2___2 = 91,\n\tCLK_PLL5_DIV4___2 = 92,\n\tCLK_PLL6_DIV2 = 93,\n\tCLK_S0 = 94,\n\tCLK_S0_VIO = 95,\n\tCLK_S0_VC = 96,\n\tCLK_S0_HSC = 97,\n\tCLK_SASYNCPER = 98,\n\tCLK_SV_VIP = 99,\n\tCLK_SV_IR = 100,\n\tCLK_SDSRC___2 = 101,\n\tCLK_RPCSRC___2 = 102,\n\tCLK_VIO = 103,\n\tCLK_VC = 104,\n\tCLK_OCO___2 = 105,\n\tMOD_CLK_BASE___5 = 106,\n};\n\nenum clk_ids___6 {\n\tLAST_DT_CORE_CLK___6 = 17,\n\tCLK_AUDIO_EXTAL = 18,\n\tCLK_RTXIN = 19,\n\tCLK_QEXTAL = 20,\n\tCLK_PLLCM33 = 21,\n\tCLK_PLLCLN = 22,\n\tCLK_PLLDTY = 23,\n\tCLK_PLLCA55 = 24,\n\tCLK_PLLVDO = 25,\n\tCLK_PLLETH = 26,\n\tCLK_PLLDSI = 27,\n\tCLK_PLLGPU = 28,\n\tCLK_PLLCM33_DIV3 = 29,\n\tCLK_PLLCM33_DIV4 = 30,\n\tCLK_PLLCM33_DIV5 = 31,\n\tCLK_PLLCM33_DIV16 = 32,\n\tCLK_PLLCM33_GEAR = 33,\n\tCLK_SMUX2_XSPI_CLK0 = 34,\n\tCLK_SMUX2_XSPI_CLK1 = 35,\n\tCLK_PLLCM33_XSPI = 36,\n\tCLK_PLLCLN_DIV2 = 37,\n\tCLK_PLLCLN_DIV8 = 38,\n\tCLK_PLLCLN_DIV16 = 39,\n\tCLK_PLLCLN_DIV20 = 40,\n\tCLK_PLLCLN_DIV64 = 41,\n\tCLK_PLLCLN_DIV256 = 42,\n\tCLK_PLLCLN_DIV1024 = 43,\n\tCLK_PLLDTY_ACPU = 44,\n\tCLK_PLLDTY_ACPU_DIV2 = 45,\n\tCLK_PLLDTY_ACPU_DIV4 = 46,\n\tCLK_PLLDTY_DIV8 = 47,\n\tCLK_PLLDTY_DIV16 = 48,\n\tCLK_PLLDTY_RCPU = 49,\n\tCLK_PLLDTY_RCPU_DIV4 = 50,\n\tCLK_PLLVDO_CRU0 = 51,\n\tCLK_PLLVDO_CRU1 = 52,\n\tCLK_PLLVDO_CRU2 = 53,\n\tCLK_PLLVDO_CRU3 = 54,\n\tCLK_PLLVDO_ISP = 55,\n\tCLK_PLLETH_DIV_250_FIX = 56,\n\tCLK_PLLETH_DIV_125_FIX = 57,\n\tCLK_CSDIV_PLLETH_GBE0 = 58,\n\tCLK_CSDIV_PLLETH_GBE1 = 59,\n\tCLK_SMUX2_GBE0_TXCLK = 60,\n\tCLK_SMUX2_GBE0_RXCLK = 61,\n\tCLK_SMUX2_GBE1_TXCLK = 62,\n\tCLK_SMUX2_GBE1_RXCLK = 63,\n\tCLK_CDIV4_PLLETH_LPCLK = 64,\n\tCLK_PLLETH_LPCLK_GEAR = 65,\n\tCLK_PLLDSI_GEAR = 66,\n\tCLK_PLLGPU_GEAR = 67,\n\tMOD_CLK_BASE___6 = 68,\n};\n\nenum clk_ids___7 {\n\tLAST_DT_CORE_CLK___7 = 24,\n\tCLK_EXTAL___6 = 25,\n\tCLK_OSC_DIV1000___3 = 26,\n\tCLK_PLL1___6 = 27,\n\tCLK_PLL2___4 = 28,\n\tCLK_PLL2_DIV2___4 = 29,\n\tCLK_PLL2_DIV2_8___3 = 30,\n\tCLK_PLL2_DIV6 = 31,\n\tCLK_PLL3___5 = 32,\n\tCLK_PLL3_DIV2___4 = 33,\n\tCLK_PLL3_DIV2_4___3 = 34,\n\tCLK_PLL3_DIV2_8 = 35,\n\tCLK_PLL3_DIV6 = 36,\n\tCLK_PLL4___4 = 37,\n\tCLK_PLL6___4 = 38,\n\tCLK_PLL6_DIV2___2 = 39,\n\tCLK_SEL_SDHI0 = 40,\n\tCLK_SEL_SDHI1 = 41,\n\tCLK_SEL_SDHI2 = 42,\n\tCLK_SEL_PLL4 = 43,\n\tCLK_P1_DIV2___3 = 44,\n\tCLK_P3_DIV2 = 45,\n\tCLK_SD0_DIV4___3 = 46,\n\tCLK_SD1_DIV4___3 = 47,\n\tCLK_SD2_DIV4 = 48,\n\tMOD_CLK_BASE___7 = 49,\n};\n\nenum clk_ids___8 {\n\tLAST_DT_CORE_CLK___8 = 14,\n\tCLK_AUDIO_EXTAL___2 = 15,\n\tCLK_RTXIN___2 = 16,\n\tCLK_QEXTAL___2 = 17,\n\tCLK_PLLCM33___2 = 18,\n\tCLK_PLLCLN___2 = 19,\n\tCLK_PLLDTY___2 = 20,\n\tCLK_PLLCA55___2 = 21,\n\tCLK_PLLVDO___2 = 22,\n\tCLK_PLLETH___2 = 23,\n\tCLK_PLLDSI___2 = 24,\n\tCLK_PLLGPU___2 = 25,\n\tCLK_PLLCM33_DIV3___2 = 26,\n\tCLK_PLLCM33_DIV4___2 = 27,\n\tCLK_PLLCM33_DIV5___2 = 28,\n\tCLK_PLLCM33_DIV16___2 = 29,\n\tCLK_PLLCM33_GEAR___2 = 30,\n\tCLK_SMUX2_XSPI_CLK0___2 = 31,\n\tCLK_SMUX2_XSPI_CLK1___2 = 32,\n\tCLK_PLLCM33_XSPI___2 = 33,\n\tCLK_PLLCLN_DIV2___2 = 34,\n\tCLK_PLLCLN_DIV8___2 = 35,\n\tCLK_PLLCLN_DIV16___2 = 36,\n\tCLK_PLLCLN_DIV20___2 = 37,\n\tCLK_PLLCLN_DIV64___2 = 38,\n\tCLK_PLLCLN_DIV256___2 = 39,\n\tCLK_PLLCLN_DIV1024___2 = 40,\n\tCLK_PLLDTY_ACPU___2 = 41,\n\tCLK_PLLDTY_ACPU_DIV2___2 = 42,\n\tCLK_PLLDTY_ACPU_DIV4___2 = 43,\n\tCLK_PLLDTY_DIV8___2 = 44,\n\tCLK_PLLDTY_DIV16___2 = 45,\n\tCLK_PLLDTY_RCPU___2 = 46,\n\tCLK_PLLDTY_RCPU_DIV4___2 = 47,\n\tCLK_PLLVDO_CRU0___2 = 48,\n\tCLK_PLLVDO_CRU1___2 = 49,\n\tCLK_PLLVDO_ISP___2 = 50,\n\tCLK_PLLETH_DIV_250_FIX___2 = 51,\n\tCLK_PLLETH_DIV_125_FIX___2 = 52,\n\tCLK_CSDIV_PLLETH_GBE0___2 = 53,\n\tCLK_CSDIV_PLLETH_GBE1___2 = 54,\n\tCLK_SMUX2_GBE0_TXCLK___2 = 55,\n\tCLK_SMUX2_GBE0_RXCLK___2 = 56,\n\tCLK_SMUX2_GBE1_TXCLK___2 = 57,\n\tCLK_SMUX2_GBE1_RXCLK___2 = 58,\n\tCLK_CDIV4_PLLETH_LPCLK___2 = 59,\n\tCLK_PLLETH_LPCLK_GEAR___2 = 60,\n\tCLK_PLLDSI_GEAR___2 = 61,\n\tCLK_PLLGPU_GEAR___2 = 62,\n\tMOD_CLK_BASE___8 = 63,\n};\n\nenum clk_ids___9 {\n\tLAST_DT_CORE_CLK___9 = 24,\n\tCLK_EXTAL___7 = 25,\n\tCLK_LOCO = 26,\n\tCLK_PLL0___2 = 27,\n\tCLK_PLL1___7 = 28,\n\tCLK_PLL2___5 = 29,\n\tCLK_PLL4___5 = 30,\n\tCLK_SEL_CLK_PLL0 = 31,\n\tCLK_SEL_CLK_PLL1 = 32,\n\tCLK_SEL_CLK_PLL2 = 33,\n\tCLK_SEL_CLK_PLL4 = 34,\n\tCLK_PLL4D1 = 35,\n\tCLK_PLL4D1_DIV3 = 36,\n\tCLK_PLL4D1_DIV4 = 37,\n\tCLK_PLL4D3 = 38,\n\tCLK_PLL4D3_DIV10 = 39,\n\tCLK_PLL4D3_DIV20 = 40,\n\tCLK_SCI0ASYNC = 41,\n\tCLK_SCI1ASYNC = 42,\n\tCLK_SCI2ASYNC = 43,\n\tCLK_SCI3ASYNC = 44,\n\tCLK_SCI4ASYNC = 45,\n\tCLK_SCI5ASYNC = 46,\n\tCLK_SPI0ASYNC = 47,\n\tCLK_SPI1ASYNC = 48,\n\tCLK_SPI2ASYNC = 49,\n\tCLK_SPI3ASYNC = 50,\n\tCLK_DIVSELXSPI0_SCKCR = 51,\n\tCLK_DIVSELXSPI1_SCKCR = 52,\n\tMOD_CLK_BASE___9 = 53,\n};\n\nenum clk_ids___10 {\n\tLAST_DT_CORE_CLK___10 = 49,\n\tCLK_EXTAL___8 = 50,\n\tCLK_EXTALR___4 = 51,\n\tCLK_MAIN___4 = 52,\n\tCLK_PLL0___3 = 53,\n\tCLK_PLL1___8 = 54,\n\tCLK_PLL3___6 = 55,\n\tCLK_PLL4___6 = 56,\n\tCLK_PLL1_DIV2___4 = 57,\n\tCLK_PLL1_DIV4___2 = 58,\n\tCLK_S0___2 = 59,\n\tCLK_S1___2 = 60,\n\tCLK_S2 = 61,\n\tCLK_S3___2 = 62,\n\tCLK_SDSRC___3 = 63,\n\tCLK_SSPSRC = 64,\n\tCLK_RPCSRC___3 = 65,\n\tCLK_RINT = 66,\n\tMOD_CLK_BASE___10 = 67,\n};\n\nenum clk_ids___11 {\n\tLAST_DT_CORE_CLK___11 = 41,\n\tCLK_EXTAL___9 = 42,\n\tCLK_MAIN___5 = 43,\n\tCLK_PLL0___4 = 44,\n\tCLK_PLL1___9 = 45,\n\tCLK_PLL3___7 = 46,\n\tCLK_PLL0D2 = 47,\n\tCLK_PLL0D3 = 48,\n\tCLK_PLL0D5 = 49,\n\tCLK_PLL1D2 = 50,\n\tCLK_PE = 51,\n\tCLK_S0___3 = 52,\n\tCLK_S1___3 = 53,\n\tCLK_S2___2 = 54,\n\tCLK_S3___3 = 55,\n\tCLK_SDSRC___4 = 56,\n\tCLK_RPCSRC___4 = 57,\n\tCLK_RINT___2 = 58,\n\tCLK_OCO___3 = 59,\n\tMOD_CLK_BASE___11 = 60,\n};\n\nenum clk_ids___12 {\n\tLAST_DT_CORE_CLK___12 = 51,\n\tCLK_EXTAL___10 = 52,\n\tCLK_EXTALR___5 = 53,\n\tCLK_MAIN___6 = 54,\n\tCLK_PLL0___5 = 55,\n\tCLK_PLL1___10 = 56,\n\tCLK_PLL2___6 = 57,\n\tCLK_PLL3___8 = 58,\n\tCLK_PLL4___7 = 59,\n\tCLK_PLL1_DIV2___5 = 60,\n\tCLK_PLL1_DIV4___3 = 61,\n\tCLK_S0___4 = 62,\n\tCLK_S1___4 = 63,\n\tCLK_S2___3 = 64,\n\tCLK_S3___4 = 65,\n\tCLK_SDSRC___5 = 66,\n\tCLK_SSPSRC___2 = 67,\n\tCLK_RPCSRC___5 = 68,\n\tCLK_RINT___3 = 69,\n\tMOD_CLK_BASE___12 = 70,\n};\n\nenum clk_ids___13 {\n\tLAST_DT_CORE_CLK___13 = 52,\n\tCLK_EXTAL___11 = 53,\n\tCLK_EXTALR___6 = 54,\n\tCLK_MAIN___7 = 55,\n\tCLK_PLL0___6 = 56,\n\tCLK_PLL1___11 = 57,\n\tCLK_PLL2___7 = 58,\n\tCLK_PLL3___9 = 59,\n\tCLK_PLL4___8 = 60,\n\tCLK_PLL1_DIV2___6 = 61,\n\tCLK_PLL1_DIV4___4 = 62,\n\tCLK_S0___5 = 63,\n\tCLK_S1___5 = 64,\n\tCLK_S2___4 = 65,\n\tCLK_S3___5 = 66,\n\tCLK_SDSRC___6 = 67,\n\tCLK_SSPSRC___3 = 68,\n\tCLK_RPCSRC___6 = 69,\n\tCLK_RINT___4 = 70,\n\tMOD_CLK_BASE___13 = 71,\n};\n\nenum clk_ids___14 {\n\tLAST_DT_CORE_CLK___14 = 0,\n\tCLK_EXTAL___12 = 1,\n\tCLK_MAIN___8 = 2,\n\tCLK_MAIN_24 = 3,\n\tCLK_MAIN_2 = 4,\n\tCLK_PLL1___12 = 5,\n\tCLK_PLL2___8 = 6,\n\tCLK_PLL2_800___3 = 7,\n\tCLK_PLL2_400 = 8,\n\tCLK_PLL2_200 = 9,\n\tCLK_PLL2_100 = 10,\n\tCLK_PLL4___9 = 11,\n\tCLK_DIV_A = 12,\n\tCLK_DIV_B = 13,\n\tCLK_DIV_D = 14,\n\tCLK_DIV_E = 15,\n\tCLK_DIV_W = 16,\n\tCLK_SEL_B = 17,\n\tCLK_SEL_B_D2 = 18,\n\tCLK_SEL_CSI0 = 19,\n\tCLK_SEL_CSI4 = 20,\n\tCLK_SEL_D = 21,\n\tCLK_SEL_E = 22,\n\tCLK_SEL_SDI = 23,\n\tCLK_SEL_W0 = 24,\n\tMOD_CLK_BASE___14 = 25,\n};\n\nenum clk_ids___15 {\n\tLAST_DT_CORE_CLK___15 = 48,\n\tCLK_EXTAL___13 = 49,\n\tCLK_MAIN___9 = 50,\n\tCLK_PLL0___7 = 51,\n\tCLK_PLL1___13 = 52,\n\tCLK_PLL3___10 = 53,\n\tCLK_PLL0D4 = 54,\n\tCLK_PLL0D6 = 55,\n\tCLK_PLL0D8 = 56,\n\tCLK_PLL0D20 = 57,\n\tCLK_PLL0D24 = 58,\n\tCLK_PLL1D2___2 = 59,\n\tCLK_PE___2 = 60,\n\tCLK_S0___6 = 61,\n\tCLK_S1___6 = 62,\n\tCLK_S2___5 = 63,\n\tCLK_S3___6 = 64,\n\tCLK_SDSRC___7 = 65,\n\tCLK_RPCSRC___7 = 66,\n\tCLK_RINT___5 = 67,\n\tCLK_OCO___4 = 68,\n\tMOD_CLK_BASE___15 = 69,\n};\n\nenum clk_ids___16 {\n\tLAST_DT_CORE_CLK___16 = 49,\n\tCLK_EXTAL___14 = 50,\n\tCLK_MAIN___10 = 51,\n\tCLK_PLL0___8 = 52,\n\tCLK_PLL1___14 = 53,\n\tCLK_PLL3___11 = 54,\n\tCLK_PLL0D4___2 = 55,\n\tCLK_PLL0D6___2 = 56,\n\tCLK_PLL0D8___2 = 57,\n\tCLK_PLL0D20___2 = 58,\n\tCLK_PLL0D24___2 = 59,\n\tCLK_PLL1D2___3 = 60,\n\tCLK_PE___3 = 61,\n\tCLK_S0___7 = 62,\n\tCLK_S1___7 = 63,\n\tCLK_S2___6 = 64,\n\tCLK_S3___7 = 65,\n\tCLK_SDSRC___8 = 66,\n\tCLK_RPCSRC___8 = 67,\n\tCLK_RINT___6 = 68,\n\tCLK_OCO___5 = 69,\n\tMOD_CLK_BASE___16 = 70,\n};\n\nenum clk_ids___17 {\n\tLAST_DT_CORE_CLK___17 = 50,\n\tCLK_EXTAL___15 = 51,\n\tCLK_EXTALR___7 = 52,\n\tCLK_MAIN___11 = 53,\n\tCLK_PLL1___15 = 54,\n\tCLK_PLL2___9 = 55,\n\tCLK_PLL3___12 = 56,\n\tCLK_PLL5___5 = 57,\n\tCLK_PLL6___5 = 58,\n\tCLK_PLL1_DIV2___7 = 59,\n\tCLK_PLL2_DIV2___5 = 60,\n\tCLK_PLL3_DIV2___5 = 61,\n\tCLK_PLL5_DIV2___3 = 62,\n\tCLK_PLL5_DIV4___3 = 63,\n\tCLK_PLL6_DIV2___3 = 64,\n\tCLK_S0___8 = 65,\n\tCLK_SASYNCPER___2 = 66,\n\tCLK_SDSRC___9 = 67,\n\tCLK_RPCSRC___9 = 68,\n\tCLK_OCO___6 = 69,\n\tMOD_CLK_BASE___17 = 70,\n};\n\nenum clk_ids___18 {\n\tLAST_DT_CORE_CLK___18 = 46,\n\tCLK_EXTAL___16 = 47,\n\tCLK_EXTALR___8 = 48,\n\tCLK_MAIN___12 = 49,\n\tCLK_PLL0___9 = 50,\n\tCLK_PLL1___16 = 51,\n\tCLK_PLL2___10 = 52,\n\tCLK_PLL3___13 = 53,\n\tCLK_PLL4___10 = 54,\n\tCLK_PLL1_DIV2___8 = 55,\n\tCLK_PLL1_DIV4___5 = 56,\n\tCLK_S0___9 = 57,\n\tCLK_S1___8 = 58,\n\tCLK_S2___7 = 59,\n\tCLK_S3___8 = 60,\n\tCLK_SDSRC___10 = 61,\n\tCLK_RPCSRC___10 = 62,\n\tCLK_RINT___7 = 63,\n\tMOD_CLK_BASE___18 = 64,\n};\n\nenum clk_ids___19 {\n\tLAST_DT_CORE_CLK___19 = 37,\n\tCLK_EXTAL___17 = 38,\n\tCLK_EXTALR___9 = 39,\n\tCLK_MAIN___13 = 40,\n\tCLK_PLL1___17 = 41,\n\tCLK_PLL2___11 = 42,\n\tCLK_PLL3___14 = 43,\n\tCLK_PLL1_DIV2___9 = 44,\n\tCLK_PLL1_DIV4___6 = 45,\n\tCLK_S0___10 = 46,\n\tCLK_S1___9 = 47,\n\tCLK_S2___8 = 48,\n\tCLK_S3___9 = 49,\n\tCLK_SDSRC___11 = 50,\n\tCLK_RPCSRC___11 = 51,\n\tCLK_OCO___7 = 52,\n\tMOD_CLK_BASE___19 = 53,\n};\n\nenum clk_ids___20 {\n\tLAST_DT_CORE_CLK___20 = 44,\n\tCLK_EXTAL___18 = 45,\n\tCLK_EXTALR___10 = 46,\n\tCLK_MAIN___14 = 47,\n\tCLK_PLL0___10 = 48,\n\tCLK_PLL1___18 = 49,\n\tCLK_PLL3___15 = 50,\n\tCLK_PLL4___11 = 51,\n\tCLK_PLL1_DIV2___10 = 52,\n\tCLK_PLL1_DIV4___7 = 53,\n\tCLK_S0___11 = 54,\n\tCLK_S1___10 = 55,\n\tCLK_S2___9 = 56,\n\tCLK_S3___10 = 57,\n\tCLK_SDSRC___12 = 58,\n\tCLK_RPCSRC___12 = 59,\n\tCLK_RINT___8 = 60,\n\tMOD_CLK_BASE___20 = 61,\n};\n\nenum clk_ids___21 {\n\tLAST_DT_CORE_CLK___21 = 15,\n\tCLK_AUDIO_EXTAL___3 = 16,\n\tCLK_RTXIN___3 = 17,\n\tCLK_QEXTAL___3 = 18,\n\tCLK_PLLCM33___3 = 19,\n\tCLK_PLLCLN___3 = 20,\n\tCLK_PLLDTY___3 = 21,\n\tCLK_PLLCA55___3 = 22,\n\tCLK_PLLVDO___3 = 23,\n\tCLK_PLLETH___3 = 24,\n\tCLK_PLLCM33_DIV3___3 = 25,\n\tCLK_PLLCM33_DIV4___3 = 26,\n\tCLK_PLLCM33_DIV5___3 = 27,\n\tCLK_PLLCM33_DIV16___3 = 28,\n\tCLK_PLLCM33_GEAR___3 = 29,\n\tCLK_SMUX2_XSPI_CLK0___3 = 30,\n\tCLK_SMUX2_XSPI_CLK1___3 = 31,\n\tCLK_PLLCM33_XSPI___3 = 32,\n\tCLK_PLLCLN_DIV2___3 = 33,\n\tCLK_PLLCLN_DIV8___3 = 34,\n\tCLK_PLLCLN_DIV16___3 = 35,\n\tCLK_PLLCLN_DIV20___3 = 36,\n\tCLK_PLLCLN_DIV64___3 = 37,\n\tCLK_PLLCLN_DIV256___3 = 38,\n\tCLK_PLLCLN_DIV1024___3 = 39,\n\tCLK_PLLDTY_ACPU___3 = 40,\n\tCLK_PLLDTY_ACPU_DIV2___3 = 41,\n\tCLK_PLLDTY_ACPU_DIV4___3 = 42,\n\tCLK_PLLDTY_DIV8___3 = 43,\n\tCLK_PLLDTY_RCPU___3 = 44,\n\tCLK_PLLDTY_RCPU_DIV4___3 = 45,\n\tCLK_PLLETH_DIV_250_FIX___3 = 46,\n\tCLK_PLLETH_DIV_125_FIX___3 = 47,\n\tCLK_CSDIV_PLLETH_GBE0___3 = 48,\n\tCLK_CSDIV_PLLETH_GBE1___3 = 49,\n\tCLK_SMUX2_GBE0_TXCLK___3 = 50,\n\tCLK_SMUX2_GBE0_RXCLK___3 = 51,\n\tCLK_SMUX2_GBE1_TXCLK___3 = 52,\n\tCLK_SMUX2_GBE1_RXCLK___3 = 53,\n\tCLK_PLLDTY_DIV16___3 = 54,\n\tCLK_PLLVDO_CRU0___3 = 55,\n\tCLK_PLLVDO_GPU = 56,\n\tMOD_CLK_BASE___21 = 57,\n};\n\nenum clk_ids___22 {\n\tLAST_DT_CORE_CLK___22 = 82,\n\tCLK_EXTAL___19 = 83,\n\tCLK_EXTALR___11 = 84,\n\tCLK_MAIN___15 = 85,\n\tCLK_PLL1___19 = 86,\n\tCLK_PLL2___12 = 87,\n\tCLK_PLL3___16 = 88,\n\tCLK_PLL4___12 = 89,\n\tCLK_PLL5___6 = 90,\n\tCLK_PLL6___6 = 91,\n\tCLK_PLL1_DIV2___11 = 92,\n\tCLK_PLL3_DIV2___6 = 93,\n\tCLK_PLL4_DIV2___2 = 94,\n\tCLK_PLL4_DIV5 = 95,\n\tCLK_PLL5_DIV2___4 = 96,\n\tCLK_PLL5_DIV4___4 = 97,\n\tCLK_PLL6_DIV2___4 = 98,\n\tCLK_S0___12 = 99,\n\tCLK_S0_VIO___2 = 100,\n\tCLK_S0_VC___2 = 101,\n\tCLK_S0_HSC___2 = 102,\n\tCLK_SASYNCPER___3 = 103,\n\tCLK_SV_VIP___2 = 104,\n\tCLK_SV_IR___2 = 105,\n\tCLK_IMPASRC = 106,\n\tCLK_IMPBSRC = 107,\n\tCLK_VIOSRC = 108,\n\tCLK_VCSRC = 109,\n\tCLK_SDSRC___13 = 110,\n\tCLK_RPCSRC___13 = 111,\n\tCLK_OCO___8 = 112,\n\tMOD_CLK_BASE___22 = 113,\n};\n\nenum clk_reg_layout {\n\tCLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,\n\tCLK_REG_LAYOUT_RZ_A = 1,\n\tCLK_REG_LAYOUT_RCAR_GEN4 = 2,\n\tCLK_REG_LAYOUT_RZ_T2H = 3,\n};\n\nenum clk_sel {\n\tLOW_SPEED_IO_SEL = 0,\n\tNON_IO_SEL = 1,\n\tFAST_SEL = 2,\n\tAUDIO_SEL = 3,\n\tVIDEO_SEL = 4,\n\tTPM_SEL = 5,\n\tCKO1_SEL = 6,\n\tCKO2_SEL = 7,\n\tMISC_SEL = 8,\n\tMAX_SEL = 9,\n};\n\nenum clk_state {\n\tCLK_STATE_DISABLE = 0,\n\tCLK_STATE_ENABLE = 1,\n\tCLK_STATE_RESERVED = 2,\n\tCLK_STATE_UNCHANGED = 3,\n};\n\nenum clk_type {\n\tCLK_TYPE_OUTPUT = 0,\n\tCLK_TYPE_EXTERNAL = 1,\n};\n\nenum clk_type_t {\n\tCLK_EXT_DIFF = 0,\n\tCLK_INT_DIFF = 1,\n\tCLK_INT_SING = 2,\n};\n\nenum clk_types {\n\tCLK_TYPE_IN = 0,\n\tCLK_TYPE_FF = 1,\n\tCLK_TYPE_SAM_PLL = 2,\n\tCLK_TYPE_G3S_PLL = 3,\n\tCLK_TYPE_DIV = 4,\n\tCLK_TYPE_G3S_DIV = 5,\n\tCLK_TYPE_MUX = 6,\n\tCLK_TYPE_SD_MUX = 7,\n\tCLK_TYPE_SIPLL5 = 8,\n\tCLK_TYPE_PLL5_4_MUX = 9,\n\tCLK_TYPE_DSI_DIV = 10,\n};\n\nenum clk_types___2 {\n\tCLK_TYPE_IN___2 = 0,\n\tCLK_TYPE_FF___2 = 1,\n\tCLK_TYPE_FF_MOD_STATUS = 2,\n\tCLK_TYPE_PLL = 3,\n\tCLK_TYPE_DDIV = 4,\n\tCLK_TYPE_SMUX = 5,\n\tCLK_TYPE_PLLDSI = 6,\n\tCLK_TYPE_PLLDSI_DIV = 7,\n};\n\nenum clk_types___3 {\n\tCLK_TYPE_IN___3 = 0,\n\tCLK_TYPE_FF___3 = 1,\n\tCLK_TYPE_DIV6P1 = 2,\n\tCLK_TYPE_DIV6_RO = 3,\n\tCLK_TYPE_FR = 4,\n\tCLK_TYPE_CUSTOM = 5,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum cma_flags {\n\tCMA_RESERVE_PAGES_ON_ERROR = 0,\n\tCMA_ZONES_VALID = 1,\n\tCMA_ZONES_INVALID = 2,\n\tCMA_ACTIVATED = 3,\n};\n\nenum cmd_db_hw_type {\n\tCMD_DB_HW_INVALID = 0,\n\tCMD_DB_HW_MIN = 3,\n\tCMD_DB_HW_ARC = 3,\n\tCMD_DB_HW_VRM = 4,\n\tCMD_DB_HW_BCM = 5,\n\tCMD_DB_HW_MAX = 5,\n\tCMD_DB_HW_ALL = 255,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum cmu_type_t {\n\tREF_CMU = 0,\n\tPHY_CMU = 1,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum compat_regset {\n\tREGSET_COMPAT_GPR = 0,\n\tREGSET_COMPAT_VFP = 1,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cpi_algorithm_type {\n\tCPI_ALG_NONE = 0,\n\tCPI_ALG_VLAN = 1,\n\tCPI_ALG_VLAN16 = 2,\n\tCPI_ALG_DIFF = 3,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cppc_regs {\n\tHIGHEST_PERF = 0,\n\tNOMINAL_PERF = 1,\n\tLOW_NON_LINEAR_PERF = 2,\n\tLOWEST_PERF = 3,\n\tGUARANTEED_PERF = 4,\n\tDESIRED_PERF = 5,\n\tMIN_PERF = 6,\n\tMAX_PERF = 7,\n\tPERF_REDUC_TOLERANCE = 8,\n\tTIME_WINDOW = 9,\n\tCTR_WRAP_TIME = 10,\n\tREFERENCE_CTR = 11,\n\tDELIVERED_CTR = 12,\n\tPERF_LIMITED = 13,\n\tENABLE = 14,\n\tAUTO_SEL_ENABLE = 15,\n\tAUTO_ACT_WINDOW = 16,\n\tENERGY_PERF = 17,\n\tREFERENCE_PERF = 18,\n\tLOWEST_FREQ = 19,\n\tNOMINAL_FREQ = 20,\n};\n\nenum cppi5_tr_event_size {\n\tCPPI5_TR_EVENT_SIZE_COMPLETION = 0,\n\tCPPI5_TR_EVENT_SIZE_ICNT1_DEC = 1,\n\tCPPI5_TR_EVENT_SIZE_ICNT2_DEC = 2,\n\tCPPI5_TR_EVENT_SIZE_ICNT3_DEC = 3,\n\tCPPI5_TR_EVENT_SIZE_MAX = 4,\n};\n\nenum cppi5_tr_trigger {\n\tCPPI5_TR_TRIGGER_NONE = 0,\n\tCPPI5_TR_TRIGGER_GLOBAL0 = 1,\n\tCPPI5_TR_TRIGGER_GLOBAL1 = 2,\n\tCPPI5_TR_TRIGGER_LOCAL_EVENT = 3,\n\tCPPI5_TR_TRIGGER_MAX = 4,\n};\n\nenum cppi5_tr_trigger_type {\n\tCPPI5_TR_TRIGGER_TYPE_ICNT1_DEC = 0,\n\tCPPI5_TR_TRIGGER_TYPE_ICNT2_DEC = 1,\n\tCPPI5_TR_TRIGGER_TYPE_ICNT3_DEC = 2,\n\tCPPI5_TR_TRIGGER_TYPE_ALL = 3,\n\tCPPI5_TR_TRIGGER_TYPE_MAX = 4,\n};\n\nenum cppi5_tr_types {\n\tCPPI5_TR_TYPE0 = 0,\n\tCPPI5_TR_TYPE1 = 1,\n\tCPPI5_TR_TYPE2 = 2,\n\tCPPI5_TR_TYPE3 = 3,\n\tCPPI5_TR_TYPE4 = 4,\n\tCPPI5_TR_TYPE5 = 5,\n\tCPPI5_TR_TYPE8 = 8,\n\tCPPI5_TR_TYPE9 = 9,\n\tCPPI5_TR_TYPE10 = 10,\n\tCPPI5_TR_TYPE11 = 11,\n\tCPPI5_TR_TYPE15 = 15,\n\tCPPI5_TR_TYPE_MAX = 16,\n};\n\nenum cpsw_ale_control {\n\tALE_ENABLE = 0,\n\tALE_CLEAR = 1,\n\tALE_AGEOUT = 2,\n\tALE_P0_UNI_FLOOD = 3,\n\tALE_VLAN_NOLEARN = 4,\n\tALE_NO_PORT_VLAN = 5,\n\tALE_OUI_DENY = 6,\n\tALE_BYPASS = 7,\n\tALE_RATE_LIMIT_TX = 8,\n\tALE_VLAN_AWARE = 9,\n\tALE_AUTH_ENABLE = 10,\n\tALE_RATE_LIMIT = 11,\n\tALE_PORT_STATE = 12,\n\tALE_PORT_DROP_UNTAGGED = 13,\n\tALE_PORT_DROP_UNKNOWN_VLAN = 14,\n\tALE_PORT_NOLEARN = 15,\n\tALE_PORT_NO_SA_UPDATE = 16,\n\tALE_PORT_UNKNOWN_VLAN_MEMBER = 17,\n\tALE_PORT_UNKNOWN_MCAST_FLOOD = 18,\n\tALE_PORT_UNKNOWN_REG_MCAST_FLOOD = 19,\n\tALE_PORT_UNTAGGED_EGRESS = 20,\n\tALE_PORT_MACONLY = 21,\n\tALE_PORT_MACONLY_CAF = 22,\n\tALE_PORT_BCAST_LIMIT = 23,\n\tALE_PORT_MCAST_LIMIT = 24,\n\tALE_DEFAULT_THREAD_ID = 25,\n\tALE_DEFAULT_THREAD_ENABLE = 26,\n\tALE_NUM_CONTROLS = 27,\n};\n\nenum cpsw_ale_port_state {\n\tALE_PORT_STATE_DISABLE = 0,\n\tALE_PORT_STATE_BLOCK = 1,\n\tALE_PORT_STATE_LEARN = 2,\n\tALE_PORT_STATE_FORWARD = 3,\n};\n\nenum cpsw_sl_regs {\n\tCPSW_SL_IDVER = 0,\n\tCPSW_SL_MACCONTROL = 1,\n\tCPSW_SL_MACSTATUS = 2,\n\tCPSW_SL_SOFT_RESET = 3,\n\tCPSW_SL_RX_MAXLEN = 4,\n\tCPSW_SL_BOFFTEST = 5,\n\tCPSW_SL_RX_PAUSE = 6,\n\tCPSW_SL_TX_PAUSE = 7,\n\tCPSW_SL_EMCONTROL = 8,\n\tCPSW_SL_RX_PRI_MAP = 9,\n\tCPSW_SL_TX_GAP = 10,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_led_event {\n\tCPU_LED_IDLE_START = 0,\n\tCPU_LED_IDLE_END = 1,\n\tCPU_LED_START = 2,\n\tCPU_LED_STOP = 3,\n\tCPU_LED_HALTED = 4,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_pm_event {\n\tCPU_PM_ENTER = 0,\n\tCPU_PM_ENTER_FAILED = 1,\n\tCPU_PM_EXIT = 2,\n\tCPU_CLUSTER_PM_ENTER = 3,\n\tCPU_CLUSTER_PM_ENTER_FAILED = 4,\n\tCPU_CLUSTER_PM_EXIT = 5,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tNR_STATS = 10,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nenum cpubiuctrl_regs {\n\tCPU_CREDIT_REG = 0,\n\tCPU_MCP_FLOW_REG = 1,\n\tCPU_WRITEBACK_CTRL_REG = 2,\n\tRAC_CONFIG0_REG = 3,\n\tRAC_CONFIG1_REG = 4,\n\tNUM_CPU_BIUCTRL_REGS = 5,\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum createmode4 {\n\tNFS4_CREATE_UNCHECKED = 0,\n\tNFS4_CREATE_GUARDED = 1,\n\tNFS4_CREATE_EXCLUSIVE = 2,\n\tNFS4_CREATE_EXCLUSIVE4_1 = 3,\n};\n\nenum criteria {\n\tCR_POWER2_ALIGNED = 0,\n\tCR_GOAL_LEN_FAST = 1,\n\tCR_BEST_AVAIL_LEN = 2,\n\tCR_GOAL_LEN_SLOW = 3,\n\tCR_ANY_FREE = 4,\n\tEXT4_MB_NUM_CRS = 5,\n};\n\nenum crypto_attr_type_t {\n\tCRYPTOCFGA_UNSPEC = 0,\n\tCRYPTOCFGA_PRIORITY_VAL = 1,\n\tCRYPTOCFGA_REPORT_LARVAL = 2,\n\tCRYPTOCFGA_REPORT_HASH = 3,\n\tCRYPTOCFGA_REPORT_BLKCIPHER = 4,\n\tCRYPTOCFGA_REPORT_AEAD = 5,\n\tCRYPTOCFGA_REPORT_COMPRESS = 6,\n\tCRYPTOCFGA_REPORT_RNG = 7,\n\tCRYPTOCFGA_REPORT_CIPHER = 8,\n\tCRYPTOCFGA_REPORT_AKCIPHER = 9,\n\tCRYPTOCFGA_REPORT_KPP = 10,\n\tCRYPTOCFGA_REPORT_ACOMP = 11,\n\tCRYPTOCFGA_STAT_LARVAL = 12,\n\tCRYPTOCFGA_STAT_HASH = 13,\n\tCRYPTOCFGA_STAT_BLKCIPHER = 14,\n\tCRYPTOCFGA_STAT_AEAD = 15,\n\tCRYPTOCFGA_STAT_COMPRESS = 16,\n\tCRYPTOCFGA_STAT_RNG = 17,\n\tCRYPTOCFGA_STAT_CIPHER = 18,\n\tCRYPTOCFGA_STAT_AKCIPHER = 19,\n\tCRYPTOCFGA_STAT_KPP = 20,\n\tCRYPTOCFGA_STAT_ACOMP = 21,\n\tCRYPTOCFGA_REPORT_SIG = 22,\n\t__CRYPTOCFGA_MAX = 23,\n};\n\nenum csr_regs {\n\tB0_RAP = 0,\n\tB0_CTST = 4,\n\tB0_POWER_CTRL = 7,\n\tB0_ISRC = 8,\n\tB0_IMSK = 12,\n\tB0_HWE_ISRC = 16,\n\tB0_HWE_IMSK = 20,\n\tB0_Y2_SP_ISRC2 = 28,\n\tB0_Y2_SP_ISRC3 = 32,\n\tB0_Y2_SP_EISR = 36,\n\tB0_Y2_SP_LISR = 40,\n\tB0_Y2_SP_ICR = 44,\n\tB2_MAC_1 = 256,\n\tB2_MAC_2 = 264,\n\tB2_MAC_3 = 272,\n\tB2_CONN_TYP = 280,\n\tB2_PMD_TYP = 281,\n\tB2_MAC_CFG = 282,\n\tB2_CHIP_ID = 283,\n\tB2_E_0 = 284,\n\tB2_Y2_CLK_GATE = 285,\n\tB2_Y2_HW_RES = 286,\n\tB2_E_3 = 287,\n\tB2_Y2_CLK_CTRL = 288,\n\tB2_TI_INI = 304,\n\tB2_TI_VAL = 308,\n\tB2_TI_CTRL = 312,\n\tB2_TI_TEST = 313,\n\tB2_TST_CTRL1 = 344,\n\tB2_TST_CTRL2 = 345,\n\tB2_GP_IO = 348,\n\tB2_I2C_CTRL = 352,\n\tB2_I2C_DATA = 356,\n\tB2_I2C_IRQ = 360,\n\tB2_I2C_SW = 364,\n\tY2_PEX_PHY_DATA = 368,\n\tY2_PEX_PHY_ADDR = 370,\n\tB3_RAM_ADDR = 384,\n\tB3_RAM_DATA_LO = 388,\n\tB3_RAM_DATA_HI = 392,\n\tB3_RI_WTO_R1 = 400,\n\tB3_RI_WTO_XA1 = 401,\n\tB3_RI_WTO_XS1 = 402,\n\tB3_RI_RTO_R1 = 403,\n\tB3_RI_RTO_XA1 = 404,\n\tB3_RI_RTO_XS1 = 405,\n\tB3_RI_WTO_R2 = 406,\n\tB3_RI_WTO_XA2 = 407,\n\tB3_RI_WTO_XS2 = 408,\n\tB3_RI_RTO_R2 = 409,\n\tB3_RI_RTO_XA2 = 410,\n\tB3_RI_RTO_XS2 = 411,\n\tB3_RI_TO_VAL = 412,\n\tB3_RI_CTRL = 416,\n\tB3_RI_TEST = 418,\n\tB3_MA_TOINI_RX1 = 432,\n\tB3_MA_TOINI_RX2 = 433,\n\tB3_MA_TOINI_TX1 = 434,\n\tB3_MA_TOINI_TX2 = 435,\n\tB3_MA_TOVAL_RX1 = 436,\n\tB3_MA_TOVAL_RX2 = 437,\n\tB3_MA_TOVAL_TX1 = 438,\n\tB3_MA_TOVAL_TX2 = 439,\n\tB3_MA_TO_CTRL = 440,\n\tB3_MA_TO_TEST = 442,\n\tB3_MA_RCINI_RX1 = 448,\n\tB3_MA_RCINI_RX2 = 449,\n\tB3_MA_RCINI_TX1 = 450,\n\tB3_MA_RCINI_TX2 = 451,\n\tB3_MA_RCVAL_RX1 = 452,\n\tB3_MA_RCVAL_RX2 = 453,\n\tB3_MA_RCVAL_TX1 = 454,\n\tB3_MA_RCVAL_TX2 = 455,\n\tB3_MA_RC_CTRL = 456,\n\tB3_MA_RC_TEST = 458,\n\tB3_PA_TOINI_RX1 = 464,\n\tB3_PA_TOINI_RX2 = 468,\n\tB3_PA_TOINI_TX1 = 472,\n\tB3_PA_TOINI_TX2 = 476,\n\tB3_PA_TOVAL_RX1 = 480,\n\tB3_PA_TOVAL_RX2 = 484,\n\tB3_PA_TOVAL_TX1 = 488,\n\tB3_PA_TOVAL_TX2 = 492,\n\tB3_PA_CTRL = 496,\n\tB3_PA_TEST = 498,\n\tY2_CFG_SPC = 7168,\n\tY2_CFG_AER = 7424,\n};\n\nenum csr_target {\n\tMACRO_CTRL = 7,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum cti_port_type {\n\tCTI_PORT_TYPE_NONE = 0,\n\tCTI_PORT_TYPE_RS232 = 1,\n\tCTI_PORT_TYPE_RS422_485 = 2,\n\tCTI_PORT_TYPE_RS232_422_485_HW = 3,\n\tCTI_PORT_TYPE_RS232_422_485_SW = 4,\n\tCTI_PORT_TYPE_RS232_422_485_4B = 5,\n\tCTI_PORT_TYPE_RS232_422_485_2B = 6,\n\tCTI_PORT_TYPE_MAX = 7,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum cv1800_pin_io_type {\n\tIO_TYPE_1V8_ONLY = 0,\n\tIO_TYPE_1V8_OR_3V3 = 1,\n\tIO_TYPE_AUDIO = 2,\n\tIO_TYPE_ETH = 3,\n};\n\nenum cxl_event_type {\n\tCXL_CPER_EVENT_GENERIC = 0,\n\tCXL_CPER_EVENT_GEN_MEDIA = 1,\n\tCXL_CPER_EVENT_DRAM = 2,\n\tCXL_CPER_EVENT_MEM_MODULE = 3,\n\tCXL_CPER_EVENT_MEM_SPARING = 4,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum data_content4 {\n\tNFS4_CONTENT_DATA = 0,\n\tNFS4_CONTENT_HOLE = 1,\n};\n\nenum dbc_state {\n\tDS_DISABLED = 0,\n\tDS_INITIALIZED = 1,\n\tDS_ENABLED = 2,\n\tDS_CONNECTED = 3,\n\tDS_CONFIGURED = 4,\n\tDS_MAX = 5,\n};\n\nenum dbg_active_el {\n\tDBG_ACTIVE_EL0 = 0,\n\tDBG_ACTIVE_EL1 = 1,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum debug_counters {\n\tSENT_OK = 0,\n\tSENT_FAIL = 1,\n\tSENT_FAIL_POLLING_UNSUPPORTED = 2,\n\tSENT_FAIL_CHANNEL_NOT_FOUND = 3,\n\tRESPONSE_OK = 4,\n\tNOTIFICATION_OK = 5,\n\tDELAYED_RESPONSE_OK = 6,\n\tXFERS_RESPONSE_TIMEOUT = 7,\n\tXFERS_RESPONSE_POLLED_TIMEOUT = 8,\n\tRESPONSE_POLLED_OK = 9,\n\tERR_MSG_UNEXPECTED = 10,\n\tERR_MSG_INVALID = 11,\n\tERR_MSG_NOMEM = 12,\n\tERR_PROTOCOL = 13,\n\tXFERS_INFLIGHT = 14,\n\tSCMI_DEBUG_COUNTERS_LAST = 15,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum depot_counter_id {\n\tDEPOT_COUNTER_REFD_ALLOCS = 0,\n\tDEPOT_COUNTER_REFD_FREES = 1,\n\tDEPOT_COUNTER_REFD_INUSE = 2,\n\tDEPOT_COUNTER_FREELIST_SIZE = 3,\n\tDEPOT_COUNTER_PERSIST_COUNT = 4,\n\tDEPOT_COUNTER_PERSIST_BYTES = 5,\n\tDEPOT_COUNTER_COUNT = 6,\n};\n\nenum desc_header_offset {\n\tQUERY_DESC_LENGTH_OFFSET = 0,\n\tQUERY_DESC_DESC_TYPE_OFFSET = 1,\n};\n\nenum desc_id {\n\tAVE_DESCID_RX = 0,\n\tAVE_DESCID_TX = 1,\n};\n\nenum desc_idn {\n\tQUERY_DESC_IDN_DEVICE = 0,\n\tQUERY_DESC_IDN_CONFIGURATION = 1,\n\tQUERY_DESC_IDN_UNIT = 2,\n\tQUERY_DESC_IDN_RFU_0 = 3,\n\tQUERY_DESC_IDN_INTERCONNECT = 4,\n\tQUERY_DESC_IDN_STRING = 5,\n\tQUERY_DESC_IDN_RFU_1 = 6,\n\tQUERY_DESC_IDN_GEOMETRY = 7,\n\tQUERY_DESC_IDN_POWER = 8,\n\tQUERY_DESC_IDN_HEALTH = 9,\n\tQUERY_DESC_IDN_MAX = 10,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum desc_state___2 {\n\tAVE_DESC_RX_PERMIT = 0,\n\tAVE_DESC_RX_SUSPEND = 1,\n\tAVE_DESC_START = 2,\n\tAVE_DESC_STOP = 3,\n};\n\nenum desc_status {\n\tFREE = 0,\n\tPREP = 1,\n\tBUSY = 2,\n\tPAUSED = 3,\n\tDONE___2 = 4,\n};\n\nenum dev_cmd_type {\n\tDEV_CMD_TYPE_NOP = 0,\n\tDEV_CMD_TYPE_QUERY = 1,\n\tDEV_CMD_TYPE_RPMB = 2,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_pm_opp_event {\n\tOPP_EVENT_ADD = 0,\n\tOPP_EVENT_REMOVE = 1,\n\tOPP_EVENT_ENABLE = 2,\n\tOPP_EVENT_DISABLE = 3,\n\tOPP_EVENT_ADJUST_VOLTAGE = 4,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum dev_status {\n\tHISI_SAS_DEV_INIT = 0,\n\tHISI_SAS_DEV_NORMAL = 1,\n\tHISI_SAS_DEV_NCQ_ERR = 2,\n};\n\nenum dev_type {\n\tDEV_UNKNOWN = 0,\n\tDEV_X1 = 1,\n\tDEV_X2 = 2,\n\tDEV_X4 = 3,\n\tDEV_X8 = 4,\n\tDEV_X16 = 5,\n\tDEV_X32 = 6,\n\tDEV_X64 = 7,\n};\n\nenum devcg_behavior {\n\tDEVCG_DEFAULT_NONE = 0,\n\tDEVCG_DEFAULT_ALLOW = 1,\n\tDEVCG_DEFAULT_DENY = 2,\n};\n\nenum devfreq_parent_dev_type {\n\tDEVFREQ_PARENT_DEV = 0,\n\tCPUFREQ_PARENT_DEV = 1,\n};\n\nenum devfreq_timer {\n\tDEVFREQ_TIMER_DEFERRABLE = 0,\n\tDEVFREQ_TIMER_DELAYED = 1,\n\tDEVFREQ_TIMER_NUM = 2,\n};\n\nenum device_desc_param {\n\tDEVICE_DESC_PARAM_LEN = 0,\n\tDEVICE_DESC_PARAM_TYPE = 1,\n\tDEVICE_DESC_PARAM_DEVICE_TYPE = 2,\n\tDEVICE_DESC_PARAM_DEVICE_CLASS = 3,\n\tDEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 4,\n\tDEVICE_DESC_PARAM_PRTCL = 5,\n\tDEVICE_DESC_PARAM_NUM_LU = 6,\n\tDEVICE_DESC_PARAM_NUM_WLU = 7,\n\tDEVICE_DESC_PARAM_BOOT_ENBL = 8,\n\tDEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 9,\n\tDEVICE_DESC_PARAM_INIT_PWR_MODE = 10,\n\tDEVICE_DESC_PARAM_HIGH_PR_LUN = 11,\n\tDEVICE_DESC_PARAM_SEC_RMV_TYPE = 12,\n\tDEVICE_DESC_PARAM_SEC_LU = 13,\n\tDEVICE_DESC_PARAM_BKOP_TERM_LT = 14,\n\tDEVICE_DESC_PARAM_ACTVE_ICC_LVL = 15,\n\tDEVICE_DESC_PARAM_SPEC_VER = 16,\n\tDEVICE_DESC_PARAM_MANF_DATE = 18,\n\tDEVICE_DESC_PARAM_MANF_NAME = 20,\n\tDEVICE_DESC_PARAM_PRDCT_NAME = 21,\n\tDEVICE_DESC_PARAM_SN = 22,\n\tDEVICE_DESC_PARAM_OEM_ID = 23,\n\tDEVICE_DESC_PARAM_MANF_ID = 24,\n\tDEVICE_DESC_PARAM_UD_OFFSET = 26,\n\tDEVICE_DESC_PARAM_UD_LEN = 27,\n\tDEVICE_DESC_PARAM_RTT_CAP = 28,\n\tDEVICE_DESC_PARAM_FRQ_RTC = 29,\n\tDEVICE_DESC_PARAM_UFS_FEAT = 31,\n\tDEVICE_DESC_PARAM_FFU_TMT = 32,\n\tDEVICE_DESC_PARAM_Q_DPTH = 33,\n\tDEVICE_DESC_PARAM_DEV_VER = 34,\n\tDEVICE_DESC_PARAM_NUM_SEC_WPA = 36,\n\tDEVICE_DESC_PARAM_PSA_MAX_DATA = 37,\n\tDEVICE_DESC_PARAM_PSA_TMT = 41,\n\tDEVICE_DESC_PARAM_PRDCT_REV = 42,\n\tDEVICE_DESC_PARAM_HPB_VER = 64,\n\tDEVICE_DESC_PARAM_HPB_CONTROL = 66,\n\tDEVICE_DESC_PARAM_EXT_WB_SUP = 77,\n\tDEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 79,\n\tDEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 83,\n\tDEVICE_DESC_PARAM_WB_TYPE = 84,\n\tDEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 85,\n};\n\nenum device_id {\n\tMAX8973 = 0,\n\tMAX77621 = 1,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_attr {\n\tDEVLINK_ATTR_UNSPEC = 0,\n\tDEVLINK_ATTR_BUS_NAME = 1,\n\tDEVLINK_ATTR_DEV_NAME = 2,\n\tDEVLINK_ATTR_PORT_INDEX = 3,\n\tDEVLINK_ATTR_PORT_TYPE = 4,\n\tDEVLINK_ATTR_PORT_DESIRED_TYPE = 5,\n\tDEVLINK_ATTR_PORT_NETDEV_IFINDEX = 6,\n\tDEVLINK_ATTR_PORT_NETDEV_NAME = 7,\n\tDEVLINK_ATTR_PORT_IBDEV_NAME = 8,\n\tDEVLINK_ATTR_PORT_SPLIT_COUNT = 9,\n\tDEVLINK_ATTR_PORT_SPLIT_GROUP = 10,\n\tDEVLINK_ATTR_SB_INDEX = 11,\n\tDEVLINK_ATTR_SB_SIZE = 12,\n\tDEVLINK_ATTR_SB_INGRESS_POOL_COUNT = 13,\n\tDEVLINK_ATTR_SB_EGRESS_POOL_COUNT = 14,\n\tDEVLINK_ATTR_SB_INGRESS_TC_COUNT = 15,\n\tDEVLINK_ATTR_SB_EGRESS_TC_COUNT = 16,\n\tDEVLINK_ATTR_SB_POOL_INDEX = 17,\n\tDEVLINK_ATTR_SB_POOL_TYPE = 18,\n\tDEVLINK_ATTR_SB_POOL_SIZE = 19,\n\tDEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE = 20,\n\tDEVLINK_ATTR_SB_THRESHOLD = 21,\n\tDEVLINK_ATTR_SB_TC_INDEX = 22,\n\tDEVLINK_ATTR_SB_OCC_CUR = 23,\n\tDEVLINK_ATTR_SB_OCC_MAX = 24,\n\tDEVLINK_ATTR_ESWITCH_MODE = 25,\n\tDEVLINK_ATTR_ESWITCH_INLINE_MODE = 26,\n\tDEVLINK_ATTR_DPIPE_TABLES = 27,\n\tDEVLINK_ATTR_DPIPE_TABLE = 28,\n\tDEVLINK_ATTR_DPIPE_TABLE_NAME = 29,\n\tDEVLINK_ATTR_DPIPE_TABLE_SIZE = 30,\n\tDEVLINK_ATTR_DPIPE_TABLE_MATCHES = 31,\n\tDEVLINK_ATTR_DPIPE_TABLE_ACTIONS = 32,\n\tDEVLINK_ATTR_DPIPE_TABLE_COUNTERS_ENABLED = 33,\n\tDEVLINK_ATTR_DPIPE_ENTRIES = 34,\n\tDEVLINK_ATTR_DPIPE_ENTRY = 35,\n\tDEVLINK_ATTR_DPIPE_ENTRY_INDEX = 36,\n\tDEVLINK_ATTR_DPIPE_ENTRY_MATCH_VALUES = 37,\n\tDEVLINK_ATTR_DPIPE_ENTRY_ACTION_VALUES = 38,\n\tDEVLINK_ATTR_DPIPE_ENTRY_COUNTER = 39,\n\tDEVLINK_ATTR_DPIPE_MATCH = 40,\n\tDEVLINK_ATTR_DPIPE_MATCH_VALUE = 41,\n\tDEVLINK_ATTR_DPIPE_MATCH_TYPE = 42,\n\tDEVLINK_ATTR_DPIPE_ACTION = 43,\n\tDEVLINK_ATTR_DPIPE_ACTION_VALUE = 44,\n\tDEVLINK_ATTR_DPIPE_ACTION_TYPE = 45,\n\tDEVLINK_ATTR_DPIPE_VALUE = 46,\n\tDEVLINK_ATTR_DPIPE_VALUE_MASK = 47,\n\tDEVLINK_ATTR_DPIPE_VALUE_MAPPING = 48,\n\tDEVLINK_ATTR_DPIPE_HEADERS = 49,\n\tDEVLINK_ATTR_DPIPE_HEADER = 50,\n\tDEVLINK_ATTR_DPIPE_HEADER_NAME = 51,\n\tDEVLINK_ATTR_DPIPE_HEADER_ID = 52,\n\tDEVLINK_ATTR_DPIPE_HEADER_FIELDS = 53,\n\tDEVLINK_ATTR_DPIPE_HEADER_GLOBAL = 54,\n\tDEVLINK_ATTR_DPIPE_HEADER_INDEX = 55,\n\tDEVLINK_ATTR_DPIPE_FIELD = 56,\n\tDEVLINK_ATTR_DPIPE_FIELD_NAME = 57,\n\tDEVLINK_ATTR_DPIPE_FIELD_ID = 58,\n\tDEVLINK_ATTR_DPIPE_FIELD_BITWIDTH = 59,\n\tDEVLINK_ATTR_DPIPE_FIELD_MAPPING_TYPE = 60,\n\tDEVLINK_ATTR_PAD = 61,\n\tDEVLINK_ATTR_ESWITCH_ENCAP_MODE = 62,\n\tDEVLINK_ATTR_RESOURCE_LIST = 63,\n\tDEVLINK_ATTR_RESOURCE = 64,\n\tDEVLINK_ATTR_RESOURCE_NAME = 65,\n\tDEVLINK_ATTR_RESOURCE_ID = 66,\n\tDEVLINK_ATTR_RESOURCE_SIZE = 67,\n\tDEVLINK_ATTR_RESOURCE_SIZE_NEW = 68,\n\tDEVLINK_ATTR_RESOURCE_SIZE_VALID = 69,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MIN = 70,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MAX = 71,\n\tDEVLINK_ATTR_RESOURCE_SIZE_GRAN = 72,\n\tDEVLINK_ATTR_RESOURCE_UNIT = 73,\n\tDEVLINK_ATTR_RESOURCE_OCC = 74,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID = 75,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS = 76,\n\tDEVLINK_ATTR_PORT_FLAVOUR = 77,\n\tDEVLINK_ATTR_PORT_NUMBER = 78,\n\tDEVLINK_ATTR_PORT_SPLIT_SUBPORT_NUMBER = 79,\n\tDEVLINK_ATTR_PARAM = 80,\n\tDEVLINK_ATTR_PARAM_NAME = 81,\n\tDEVLINK_ATTR_PARAM_GENERIC = 82,\n\tDEVLINK_ATTR_PARAM_TYPE = 83,\n\tDEVLINK_ATTR_PARAM_VALUES_LIST = 84,\n\tDEVLINK_ATTR_PARAM_VALUE = 85,\n\tDEVLINK_ATTR_PARAM_VALUE_DATA = 86,\n\tDEVLINK_ATTR_PARAM_VALUE_CMODE = 87,\n\tDEVLINK_ATTR_REGION_NAME = 88,\n\tDEVLINK_ATTR_REGION_SIZE = 89,\n\tDEVLINK_ATTR_REGION_SNAPSHOTS = 90,\n\tDEVLINK_ATTR_REGION_SNAPSHOT = 91,\n\tDEVLINK_ATTR_REGION_SNAPSHOT_ID = 92,\n\tDEVLINK_ATTR_REGION_CHUNKS = 93,\n\tDEVLINK_ATTR_REGION_CHUNK = 94,\n\tDEVLINK_ATTR_REGION_CHUNK_DATA = 95,\n\tDEVLINK_ATTR_REGION_CHUNK_ADDR = 96,\n\tDEVLINK_ATTR_REGION_CHUNK_LEN = 97,\n\tDEVLINK_ATTR_INFO_DRIVER_NAME = 98,\n\tDEVLINK_ATTR_INFO_SERIAL_NUMBER = 99,\n\tDEVLINK_ATTR_INFO_VERSION_FIXED = 100,\n\tDEVLINK_ATTR_INFO_VERSION_RUNNING = 101,\n\tDEVLINK_ATTR_INFO_VERSION_STORED = 102,\n\tDEVLINK_ATTR_INFO_VERSION_NAME = 103,\n\tDEVLINK_ATTR_INFO_VERSION_VALUE = 104,\n\tDEVLINK_ATTR_SB_POOL_CELL_SIZE = 105,\n\tDEVLINK_ATTR_FMSG = 106,\n\tDEVLINK_ATTR_FMSG_OBJ_NEST_START = 107,\n\tDEVLINK_ATTR_FMSG_PAIR_NEST_START = 108,\n\tDEVLINK_ATTR_FMSG_ARR_NEST_START = 109,\n\tDEVLINK_ATTR_FMSG_NEST_END = 110,\n\tDEVLINK_ATTR_FMSG_OBJ_NAME = 111,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_TYPE = 112,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_DATA = 113,\n\tDEVLINK_ATTR_HEALTH_REPORTER = 114,\n\tDEVLINK_ATTR_HEALTH_REPORTER_NAME = 115,\n\tDEVLINK_ATTR_HEALTH_REPORTER_STATE = 116,\n\tDEVLINK_ATTR_HEALTH_REPORTER_ERR_COUNT = 117,\n\tDEVLINK_ATTR_HEALTH_REPORTER_RECOVER_COUNT = 118,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS = 119,\n\tDEVLINK_ATTR_HEALTH_REPORTER_GRACEFUL_PERIOD = 120,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_RECOVER = 121,\n\tDEVLINK_ATTR_FLASH_UPDATE_FILE_NAME = 122,\n\tDEVLINK_ATTR_FLASH_UPDATE_COMPONENT = 123,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_MSG = 124,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_DONE = 125,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TOTAL = 126,\n\tDEVLINK_ATTR_PORT_PCI_PF_NUMBER = 127,\n\tDEVLINK_ATTR_PORT_PCI_VF_NUMBER = 128,\n\tDEVLINK_ATTR_STATS = 129,\n\tDEVLINK_ATTR_TRAP_NAME = 130,\n\tDEVLINK_ATTR_TRAP_ACTION = 131,\n\tDEVLINK_ATTR_TRAP_TYPE = 132,\n\tDEVLINK_ATTR_TRAP_GENERIC = 133,\n\tDEVLINK_ATTR_TRAP_METADATA = 134,\n\tDEVLINK_ATTR_TRAP_GROUP_NAME = 135,\n\tDEVLINK_ATTR_RELOAD_FAILED = 136,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS_NS = 137,\n\tDEVLINK_ATTR_NETNS_FD = 138,\n\tDEVLINK_ATTR_NETNS_PID = 139,\n\tDEVLINK_ATTR_NETNS_ID = 140,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_DUMP = 141,\n\tDEVLINK_ATTR_TRAP_POLICER_ID = 142,\n\tDEVLINK_ATTR_TRAP_POLICER_RATE = 143,\n\tDEVLINK_ATTR_TRAP_POLICER_BURST = 144,\n\tDEVLINK_ATTR_PORT_FUNCTION = 145,\n\tDEVLINK_ATTR_INFO_BOARD_SERIAL_NUMBER = 146,\n\tDEVLINK_ATTR_PORT_LANES = 147,\n\tDEVLINK_ATTR_PORT_SPLITTABLE = 148,\n\tDEVLINK_ATTR_PORT_EXTERNAL = 149,\n\tDEVLINK_ATTR_PORT_CONTROLLER_NUMBER = 150,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TIMEOUT = 151,\n\tDEVLINK_ATTR_FLASH_UPDATE_OVERWRITE_MASK = 152,\n\tDEVLINK_ATTR_RELOAD_ACTION = 153,\n\tDEVLINK_ATTR_RELOAD_ACTIONS_PERFORMED = 154,\n\tDEVLINK_ATTR_RELOAD_LIMITS = 155,\n\tDEVLINK_ATTR_DEV_STATS = 156,\n\tDEVLINK_ATTR_RELOAD_STATS = 157,\n\tDEVLINK_ATTR_RELOAD_STATS_ENTRY = 158,\n\tDEVLINK_ATTR_RELOAD_STATS_LIMIT = 159,\n\tDEVLINK_ATTR_RELOAD_STATS_VALUE = 160,\n\tDEVLINK_ATTR_REMOTE_RELOAD_STATS = 161,\n\tDEVLINK_ATTR_RELOAD_ACTION_INFO = 162,\n\tDEVLINK_ATTR_RELOAD_ACTION_STATS = 163,\n\tDEVLINK_ATTR_PORT_PCI_SF_NUMBER = 164,\n\tDEVLINK_ATTR_RATE_TYPE = 165,\n\tDEVLINK_ATTR_RATE_TX_SHARE = 166,\n\tDEVLINK_ATTR_RATE_TX_MAX = 167,\n\tDEVLINK_ATTR_RATE_NODE_NAME = 168,\n\tDEVLINK_ATTR_RATE_PARENT_NODE_NAME = 169,\n\tDEVLINK_ATTR_REGION_MAX_SNAPSHOTS = 170,\n\tDEVLINK_ATTR_LINECARD_INDEX = 171,\n\tDEVLINK_ATTR_LINECARD_STATE = 172,\n\tDEVLINK_ATTR_LINECARD_TYPE = 173,\n\tDEVLINK_ATTR_LINECARD_SUPPORTED_TYPES = 174,\n\tDEVLINK_ATTR_NESTED_DEVLINK = 175,\n\tDEVLINK_ATTR_SELFTESTS = 176,\n\tDEVLINK_ATTR_RATE_TX_PRIORITY = 177,\n\tDEVLINK_ATTR_RATE_TX_WEIGHT = 178,\n\tDEVLINK_ATTR_REGION_DIRECT = 179,\n\tDEVLINK_ATTR_RATE_TC_BWS = 180,\n\tDEVLINK_ATTR_HEALTH_REPORTER_BURST_PERIOD = 181,\n\tDEVLINK_ATTR_PARAM_VALUE_DEFAULT = 182,\n\tDEVLINK_ATTR_PARAM_RESET_DEFAULT = 183,\n\t__DEVLINK_ATTR_MAX = 184,\n\tDEVLINK_ATTR_MAX = 183,\n};\n\nenum devlink_attr_selftest_id {\n\tDEVLINK_ATTR_SELFTEST_ID_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_ID_FLASH = 1,\n\t__DEVLINK_ATTR_SELFTEST_ID_MAX = 2,\n\tDEVLINK_ATTR_SELFTEST_ID_MAX = 1,\n};\n\nenum devlink_attr_selftest_result {\n\tDEVLINK_ATTR_SELFTEST_RESULT_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_RESULT = 1,\n\tDEVLINK_ATTR_SELFTEST_RESULT_ID = 2,\n\tDEVLINK_ATTR_SELFTEST_RESULT_STATUS = 3,\n\t__DEVLINK_ATTR_SELFTEST_RESULT_MAX = 4,\n\tDEVLINK_ATTR_SELFTEST_RESULT_MAX = 3,\n};\n\nenum devlink_command {\n\tDEVLINK_CMD_UNSPEC = 0,\n\tDEVLINK_CMD_GET = 1,\n\tDEVLINK_CMD_SET = 2,\n\tDEVLINK_CMD_NEW = 3,\n\tDEVLINK_CMD_DEL = 4,\n\tDEVLINK_CMD_PORT_GET = 5,\n\tDEVLINK_CMD_PORT_SET = 6,\n\tDEVLINK_CMD_PORT_NEW = 7,\n\tDEVLINK_CMD_PORT_DEL = 8,\n\tDEVLINK_CMD_PORT_SPLIT = 9,\n\tDEVLINK_CMD_PORT_UNSPLIT = 10,\n\tDEVLINK_CMD_SB_GET = 11,\n\tDEVLINK_CMD_SB_SET = 12,\n\tDEVLINK_CMD_SB_NEW = 13,\n\tDEVLINK_CMD_SB_DEL = 14,\n\tDEVLINK_CMD_SB_POOL_GET = 15,\n\tDEVLINK_CMD_SB_POOL_SET = 16,\n\tDEVLINK_CMD_SB_POOL_NEW = 17,\n\tDEVLINK_CMD_SB_POOL_DEL = 18,\n\tDEVLINK_CMD_SB_PORT_POOL_GET = 19,\n\tDEVLINK_CMD_SB_PORT_POOL_SET = 20,\n\tDEVLINK_CMD_SB_PORT_POOL_NEW = 21,\n\tDEVLINK_CMD_SB_PORT_POOL_DEL = 22,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_GET = 23,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_SET = 24,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_NEW = 25,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_DEL = 26,\n\tDEVLINK_CMD_SB_OCC_SNAPSHOT = 27,\n\tDEVLINK_CMD_SB_OCC_MAX_CLEAR = 28,\n\tDEVLINK_CMD_ESWITCH_GET = 29,\n\tDEVLINK_CMD_ESWITCH_SET = 30,\n\tDEVLINK_CMD_DPIPE_TABLE_GET = 31,\n\tDEVLINK_CMD_DPIPE_ENTRIES_GET = 32,\n\tDEVLINK_CMD_DPIPE_HEADERS_GET = 33,\n\tDEVLINK_CMD_DPIPE_TABLE_COUNTERS_SET = 34,\n\tDEVLINK_CMD_RESOURCE_SET = 35,\n\tDEVLINK_CMD_RESOURCE_DUMP = 36,\n\tDEVLINK_CMD_RELOAD = 37,\n\tDEVLINK_CMD_PARAM_GET = 38,\n\tDEVLINK_CMD_PARAM_SET = 39,\n\tDEVLINK_CMD_PARAM_NEW = 40,\n\tDEVLINK_CMD_PARAM_DEL = 41,\n\tDEVLINK_CMD_REGION_GET = 42,\n\tDEVLINK_CMD_REGION_SET = 43,\n\tDEVLINK_CMD_REGION_NEW = 44,\n\tDEVLINK_CMD_REGION_DEL = 45,\n\tDEVLINK_CMD_REGION_READ = 46,\n\tDEVLINK_CMD_PORT_PARAM_GET = 47,\n\tDEVLINK_CMD_PORT_PARAM_SET = 48,\n\tDEVLINK_CMD_PORT_PARAM_NEW = 49,\n\tDEVLINK_CMD_PORT_PARAM_DEL = 50,\n\tDEVLINK_CMD_INFO_GET = 51,\n\tDEVLINK_CMD_HEALTH_REPORTER_GET = 52,\n\tDEVLINK_CMD_HEALTH_REPORTER_SET = 53,\n\tDEVLINK_CMD_HEALTH_REPORTER_RECOVER = 54,\n\tDEVLINK_CMD_HEALTH_REPORTER_DIAGNOSE = 55,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_GET = 56,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_CLEAR = 57,\n\tDEVLINK_CMD_FLASH_UPDATE = 58,\n\tDEVLINK_CMD_FLASH_UPDATE_END = 59,\n\tDEVLINK_CMD_FLASH_UPDATE_STATUS = 60,\n\tDEVLINK_CMD_TRAP_GET = 61,\n\tDEVLINK_CMD_TRAP_SET = 62,\n\tDEVLINK_CMD_TRAP_NEW = 63,\n\tDEVLINK_CMD_TRAP_DEL = 64,\n\tDEVLINK_CMD_TRAP_GROUP_GET = 65,\n\tDEVLINK_CMD_TRAP_GROUP_SET = 66,\n\tDEVLINK_CMD_TRAP_GROUP_NEW = 67,\n\tDEVLINK_CMD_TRAP_GROUP_DEL = 68,\n\tDEVLINK_CMD_TRAP_POLICER_GET = 69,\n\tDEVLINK_CMD_TRAP_POLICER_SET = 70,\n\tDEVLINK_CMD_TRAP_POLICER_NEW = 71,\n\tDEVLINK_CMD_TRAP_POLICER_DEL = 72,\n\tDEVLINK_CMD_HEALTH_REPORTER_TEST = 73,\n\tDEVLINK_CMD_RATE_GET = 74,\n\tDEVLINK_CMD_RATE_SET = 75,\n\tDEVLINK_CMD_RATE_NEW = 76,\n\tDEVLINK_CMD_RATE_DEL = 77,\n\tDEVLINK_CMD_LINECARD_GET = 78,\n\tDEVLINK_CMD_LINECARD_SET = 79,\n\tDEVLINK_CMD_LINECARD_NEW = 80,\n\tDEVLINK_CMD_LINECARD_DEL = 81,\n\tDEVLINK_CMD_SELFTESTS_GET = 82,\n\tDEVLINK_CMD_SELFTESTS_RUN = 83,\n\tDEVLINK_CMD_NOTIFY_FILTER_SET = 84,\n\t__DEVLINK_CMD_MAX = 85,\n\tDEVLINK_CMD_MAX = 84,\n};\n\nenum devlink_dpipe_action_type {\n\tDEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY = 0,\n};\n\nenum devlink_dpipe_field_ethernet_id {\n\tDEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC = 0,\n};\n\nenum devlink_dpipe_field_ipv4_id {\n\tDEVLINK_DPIPE_FIELD_IPV4_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_ipv6_id {\n\tDEVLINK_DPIPE_FIELD_IPV6_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_mapping_type {\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0,\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1,\n};\n\nenum devlink_dpipe_header_id {\n\tDEVLINK_DPIPE_HEADER_ETHERNET = 0,\n\tDEVLINK_DPIPE_HEADER_IPV4 = 1,\n\tDEVLINK_DPIPE_HEADER_IPV6 = 2,\n};\n\nenum devlink_dpipe_match_type {\n\tDEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT = 0,\n};\n\nenum devlink_eswitch_encap_mode {\n\tDEVLINK_ESWITCH_ENCAP_MODE_NONE = 0,\n\tDEVLINK_ESWITCH_ENCAP_MODE_BASIC = 1,\n};\n\nenum devlink_health_reporter_state {\n\tDEVLINK_HEALTH_REPORTER_STATE_HEALTHY = 0,\n\tDEVLINK_HEALTH_REPORTER_STATE_ERROR = 1,\n};\n\nenum devlink_info_version_type {\n\tDEVLINK_INFO_VERSION_TYPE_NONE = 0,\n\tDEVLINK_INFO_VERSION_TYPE_COMPONENT = 1,\n};\n\nenum devlink_linecard_state {\n\tDEVLINK_LINECARD_STATE_UNSPEC = 0,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONED = 1,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONING = 2,\n\tDEVLINK_LINECARD_STATE_PROVISIONING = 3,\n\tDEVLINK_LINECARD_STATE_PROVISIONING_FAILED = 4,\n\tDEVLINK_LINECARD_STATE_PROVISIONED = 5,\n\tDEVLINK_LINECARD_STATE_ACTIVE = 6,\n\t__DEVLINK_LINECARD_STATE_MAX = 7,\n\tDEVLINK_LINECARD_STATE_MAX = 6,\n};\n\nenum devlink_multicast_groups {\n\tDEVLINK_MCGRP_CONFIG = 0,\n};\n\nenum devlink_param_cmode {\n\tDEVLINK_PARAM_CMODE_RUNTIME = 0,\n\tDEVLINK_PARAM_CMODE_DRIVERINIT = 1,\n\tDEVLINK_PARAM_CMODE_PERMANENT = 2,\n\t__DEVLINK_PARAM_CMODE_MAX = 3,\n\tDEVLINK_PARAM_CMODE_MAX = 2,\n};\n\nenum devlink_param_generic_id {\n\tDEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET = 0,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MACS = 1,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_SRIOV = 2,\n\tDEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT = 3,\n\tDEVLINK_PARAM_GENERIC_ID_IGNORE_ARI = 4,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX = 5,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN = 6,\n\tDEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY = 7,\n\tDEVLINK_PARAM_GENERIC_ID_RESET_DEV_ON_DRV_PROBE = 8,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE = 9,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_REMOTE_DEV_RESET = 10,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ETH = 11,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA = 12,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_VNET = 13,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_IWARP = 14,\n\tDEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE = 15,\n\tDEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE = 16,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_PHC = 17,\n\tDEVLINK_PARAM_GENERIC_ID_CLOCK_ID = 18,\n\tDEVLINK_PARAM_GENERIC_ID_TOTAL_VFS = 19,\n\tDEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS = 20,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF = 21,\n\t__DEVLINK_PARAM_GENERIC_ID_MAX = 22,\n\tDEVLINK_PARAM_GENERIC_ID_MAX = 21,\n};\n\nenum devlink_param_type {\n\tDEVLINK_PARAM_TYPE_U8 = 1,\n\tDEVLINK_PARAM_TYPE_U16 = 2,\n\tDEVLINK_PARAM_TYPE_U32 = 3,\n\tDEVLINK_PARAM_TYPE_U64 = 4,\n\tDEVLINK_PARAM_TYPE_STRING = 5,\n\tDEVLINK_PARAM_TYPE_BOOL = 6,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_attr_cap {\n\tDEVLINK_PORT_FN_ATTR_CAP_ROCE_BIT = 0,\n\tDEVLINK_PORT_FN_ATTR_CAP_MIGRATABLE_BIT = 1,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_CRYPTO_BIT = 2,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_PACKET_BIT = 3,\n\t__DEVLINK_PORT_FN_ATTR_CAPS_MAX = 4,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_function_attr {\n\tDEVLINK_PORT_FUNCTION_ATTR_UNSPEC = 0,\n\tDEVLINK_PORT_FUNCTION_ATTR_HW_ADDR = 1,\n\tDEVLINK_PORT_FN_ATTR_STATE = 2,\n\tDEVLINK_PORT_FN_ATTR_OPSTATE = 3,\n\tDEVLINK_PORT_FN_ATTR_CAPS = 4,\n\tDEVLINK_PORT_FN_ATTR_DEVLINK = 5,\n\tDEVLINK_PORT_FN_ATTR_MAX_IO_EQS = 6,\n\t__DEVLINK_PORT_FUNCTION_ATTR_MAX = 7,\n\tDEVLINK_PORT_FUNCTION_ATTR_MAX = 6,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_tc_attr {\n\tDEVLINK_RATE_TC_ATTR_UNSPEC = 0,\n\tDEVLINK_RATE_TC_ATTR_INDEX = 1,\n\tDEVLINK_RATE_TC_ATTR_BW = 2,\n\t__DEVLINK_RATE_TC_ATTR_MAX = 3,\n\tDEVLINK_RATE_TC_ATTR_MAX = 2,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devlink_reload_action {\n\tDEVLINK_RELOAD_ACTION_UNSPEC = 0,\n\tDEVLINK_RELOAD_ACTION_DRIVER_REINIT = 1,\n\tDEVLINK_RELOAD_ACTION_FW_ACTIVATE = 2,\n\t__DEVLINK_RELOAD_ACTION_MAX = 3,\n\tDEVLINK_RELOAD_ACTION_MAX = 2,\n};\n\nenum devlink_reload_limit {\n\tDEVLINK_RELOAD_LIMIT_UNSPEC = 0,\n\tDEVLINK_RELOAD_LIMIT_NO_RESET = 1,\n\t__DEVLINK_RELOAD_LIMIT_MAX = 2,\n\tDEVLINK_RELOAD_LIMIT_MAX = 1,\n};\n\nenum devlink_resource_unit {\n\tDEVLINK_RESOURCE_UNIT_ENTRY = 0,\n};\n\nenum devlink_sb_pool_type {\n\tDEVLINK_SB_POOL_TYPE_INGRESS = 0,\n\tDEVLINK_SB_POOL_TYPE_EGRESS = 1,\n};\n\nenum devlink_sb_threshold_type {\n\tDEVLINK_SB_THRESHOLD_TYPE_STATIC = 0,\n\tDEVLINK_SB_THRESHOLD_TYPE_DYNAMIC = 1,\n};\n\nenum devlink_selftest_status {\n\tDEVLINK_SELFTEST_STATUS_SKIP = 0,\n\tDEVLINK_SELFTEST_STATUS_PASS = 1,\n\tDEVLINK_SELFTEST_STATUS_FAIL = 2,\n};\n\nenum devlink_trap_action {\n\tDEVLINK_TRAP_ACTION_DROP = 0,\n\tDEVLINK_TRAP_ACTION_TRAP = 1,\n\tDEVLINK_TRAP_ACTION_MIRROR = 2,\n};\n\nenum devlink_trap_generic_id {\n\tDEVLINK_TRAP_GENERIC_ID_SMAC_MC = 0,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_TAG_MISMATCH = 1,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_VLAN_FILTER = 2,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_STP_FILTER = 3,\n\tDEVLINK_TRAP_GENERIC_ID_EMPTY_TX_LIST = 4,\n\tDEVLINK_TRAP_GENERIC_ID_PORT_LOOPBACK_FILTER = 5,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_ROUTE = 6,\n\tDEVLINK_TRAP_GENERIC_ID_TTL_ERROR = 7,\n\tDEVLINK_TRAP_GENERIC_ID_TAIL_DROP = 8,\n\tDEVLINK_TRAP_GENERIC_ID_NON_IP_PACKET = 9,\n\tDEVLINK_TRAP_GENERIC_ID_UC_DIP_MC_DMAC = 10,\n\tDEVLINK_TRAP_GENERIC_ID_DIP_LB = 11,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_MC = 12,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_LB = 13,\n\tDEVLINK_TRAP_GENERIC_ID_CORRUPTED_IP_HDR = 14,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_SIP_BC = 15,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_RESERVED_SCOPE = 16,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_INTERFACE_LOCAL_SCOPE = 17,\n\tDEVLINK_TRAP_GENERIC_ID_MTU_ERROR = 18,\n\tDEVLINK_TRAP_GENERIC_ID_UNRESOLVED_NEIGH = 19,\n\tDEVLINK_TRAP_GENERIC_ID_RPF = 20,\n\tDEVLINK_TRAP_GENERIC_ID_REJECT_ROUTE = 21,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_LPM_UNICAST_MISS = 22,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_LPM_UNICAST_MISS = 23,\n\tDEVLINK_TRAP_GENERIC_ID_NON_ROUTABLE = 24,\n\tDEVLINK_TRAP_GENERIC_ID_DECAP_ERROR = 25,\n\tDEVLINK_TRAP_GENERIC_ID_OVERLAY_SMAC_MC = 26,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_FLOW_ACTION_DROP = 27,\n\tDEVLINK_TRAP_GENERIC_ID_EGRESS_FLOW_ACTION_DROP = 28,\n\tDEVLINK_TRAP_GENERIC_ID_STP = 29,\n\tDEVLINK_TRAP_GENERIC_ID_LACP = 30,\n\tDEVLINK_TRAP_GENERIC_ID_LLDP = 31,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_QUERY = 32,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V1_REPORT = 33,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_REPORT = 34,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V3_REPORT = 35,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_LEAVE = 36,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_QUERY = 37,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_REPORT = 38,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V2_REPORT = 39,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_DONE = 40,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_DHCP = 41,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DHCP = 42,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_REQUEST = 43,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_RESPONSE = 44,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_OVERLAY = 45,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_SOLICIT = 46,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_ADVERT = 47,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BFD = 48,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BFD = 49,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_OSPF = 50,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_OSPF = 51,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BGP = 52,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BGP = 53,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_VRRP = 54,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_VRRP = 55,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_PIM = 56,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_PIM = 57,\n\tDEVLINK_TRAP_GENERIC_ID_UC_LB = 58,\n\tDEVLINK_TRAP_GENERIC_ID_LOCAL_ROUTE = 59,\n\tDEVLINK_TRAP_GENERIC_ID_EXTERNAL_ROUTE = 60,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_UC_DIP_LINK_LOCAL_SCOPE = 61,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_NODES = 62,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_ROUTERS = 63,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_SOLICIT = 64,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ADVERT = 65,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_REDIRECT = 66,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_ROUTER_ALERT = 67,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ALERT = 68,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_EVENT = 69,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_GENERAL = 70,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_SAMPLE = 71,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_TRAP = 72,\n\tDEVLINK_TRAP_GENERIC_ID_EARLY_DROP = 73,\n\tDEVLINK_TRAP_GENERIC_ID_VXLAN_PARSING = 74,\n\tDEVLINK_TRAP_GENERIC_ID_LLC_SNAP_PARSING = 75,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_PARSING = 76,\n\tDEVLINK_TRAP_GENERIC_ID_PPPOE_PPP_PARSING = 77,\n\tDEVLINK_TRAP_GENERIC_ID_MPLS_PARSING = 78,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_PARSING = 79,\n\tDEVLINK_TRAP_GENERIC_ID_IP_1_PARSING = 80,\n\tDEVLINK_TRAP_GENERIC_ID_IP_N_PARSING = 81,\n\tDEVLINK_TRAP_GENERIC_ID_GRE_PARSING = 82,\n\tDEVLINK_TRAP_GENERIC_ID_UDP_PARSING = 83,\n\tDEVLINK_TRAP_GENERIC_ID_TCP_PARSING = 84,\n\tDEVLINK_TRAP_GENERIC_ID_IPSEC_PARSING = 85,\n\tDEVLINK_TRAP_GENERIC_ID_SCTP_PARSING = 86,\n\tDEVLINK_TRAP_GENERIC_ID_DCCP_PARSING = 87,\n\tDEVLINK_TRAP_GENERIC_ID_GTP_PARSING = 88,\n\tDEVLINK_TRAP_GENERIC_ID_ESP_PARSING = 89,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_NEXTHOP = 90,\n\tDEVLINK_TRAP_GENERIC_ID_DMAC_FILTER = 91,\n\tDEVLINK_TRAP_GENERIC_ID_EAPOL = 92,\n\tDEVLINK_TRAP_GENERIC_ID_LOCKED_PORT = 93,\n\t__DEVLINK_TRAP_GENERIC_ID_MAX = 94,\n\tDEVLINK_TRAP_GENERIC_ID_MAX = 93,\n};\n\nenum devlink_trap_group_generic_id {\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L2_DROPS = 0,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_DROPS = 1,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_EXCEPTIONS = 2,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BUFFER_DROPS = 3,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_TUNNEL_DROPS = 4,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_DROPS = 5,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_STP = 6,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LACP = 7,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LLDP = 8,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MC_SNOOPING = 9,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_DHCP = 10,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_NEIGH_DISCOVERY = 11,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BFD = 12,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_OSPF = 13,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BGP = 14,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_VRRP = 15,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PIM = 16,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_UC_LB = 17,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LOCAL_DELIVERY = 18,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EXTERNAL_DELIVERY = 19,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_IPV6 = 20,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_EVENT = 21,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_GENERAL = 22,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_SAMPLE = 23,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_TRAP = 24,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PARSER_ERROR_DROPS = 25,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EAPOL = 26,\n\t__DEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 27,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 26,\n};\n\nenum devlink_trap_type {\n\tDEVLINK_TRAP_TYPE_DROP = 0,\n\tDEVLINK_TRAP_TYPE_EXCEPTION = 1,\n\tDEVLINK_TRAP_TYPE_CONTROL = 2,\n};\n\nenum devlink_var_attr_type {\n\tDEVLINK_VAR_ATTR_TYPE_U8 = 1,\n\tDEVLINK_VAR_ATTR_TYPE_U16 = 2,\n\tDEVLINK_VAR_ATTR_TYPE_U32 = 3,\n\tDEVLINK_VAR_ATTR_TYPE_U64 = 4,\n\tDEVLINK_VAR_ATTR_TYPE_STRING = 5,\n\tDEVLINK_VAR_ATTR_TYPE_FLAG = 6,\n\tDEVLINK_VAR_ATTR_TYPE_NUL_STRING = 10,\n\tDEVLINK_VAR_ATTR_TYPE_BINARY = 11,\n\t__DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE = 128,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum dew_regs {\n\tPWRAP_DEW_BASE = 0,\n\tPWRAP_DEW_DIO_EN = 1,\n\tPWRAP_DEW_READ_TEST = 2,\n\tPWRAP_DEW_WRITE_TEST = 3,\n\tPWRAP_DEW_CRC_EN = 4,\n\tPWRAP_DEW_CRC_VAL = 5,\n\tPWRAP_DEW_MON_GRP_SEL = 6,\n\tPWRAP_DEW_CIPHER_KEY_SEL = 7,\n\tPWRAP_DEW_CIPHER_IV_SEL = 8,\n\tPWRAP_DEW_CIPHER_RDY = 9,\n\tPWRAP_DEW_CIPHER_MODE = 10,\n\tPWRAP_DEW_CIPHER_SWRST = 11,\n\tPWRAP_DEW_CIPHER_EN = 12,\n\tPWRAP_DEW_RDDMY_NO = 13,\n\tPWRAP_SMT_CON1 = 14,\n\tPWRAP_DRV_CON1 = 15,\n\tPWRAP_FILTER_CON0 = 16,\n\tPWRAP_GPIO_PULLEN0_CLR = 17,\n\tPWRAP_RG_SPI_CON0 = 18,\n\tPWRAP_RG_SPI_RECORD0 = 19,\n\tPWRAP_RG_SPI_CON2 = 20,\n\tPWRAP_RG_SPI_CON3 = 21,\n\tPWRAP_RG_SPI_CON4 = 22,\n\tPWRAP_RG_SPI_CON5 = 23,\n\tPWRAP_RG_SPI_CON6 = 24,\n\tPWRAP_RG_SPI_CON7 = 25,\n\tPWRAP_RG_SPI_CON8 = 26,\n\tPWRAP_RG_SPI_CON13 = 27,\n\tPWRAP_SPISLV_KEY = 28,\n\tPWRAP_DEW_CRC_SWRST = 29,\n\tPWRAP_DEW_RG_EN_RECORD = 30,\n\tPWRAP_DEW_RECORD_CMD0 = 31,\n\tPWRAP_DEW_RECORD_CMD1 = 32,\n\tPWRAP_DEW_RECORD_CMD2 = 33,\n\tPWRAP_DEW_RECORD_CMD3 = 34,\n\tPWRAP_DEW_RECORD_CMD4 = 35,\n\tPWRAP_DEW_RECORD_CMD5 = 36,\n\tPWRAP_DEW_RECORD_WDATA0 = 37,\n\tPWRAP_DEW_RECORD_WDATA1 = 38,\n\tPWRAP_DEW_RECORD_WDATA2 = 39,\n\tPWRAP_DEW_RECORD_WDATA3 = 40,\n\tPWRAP_DEW_RECORD_WDATA4 = 41,\n\tPWRAP_DEW_RECORD_WDATA5 = 42,\n\tPWRAP_DEW_RG_ADDR_TARGET = 43,\n\tPWRAP_DEW_RG_ADDR_MASK = 44,\n\tPWRAP_DEW_RG_WDATA_TARGET = 45,\n\tPWRAP_DEW_RG_WDATA_MASK = 46,\n\tPWRAP_DEW_RG_SPI_RECORD_CLR = 47,\n\tPWRAP_DEW_RG_CMD_ALERT_CLR = 48,\n\tPWRAP_DEW_EVENT_OUT_EN = 49,\n\tPWRAP_DEW_EVENT_SRC_EN = 50,\n\tPWRAP_DEW_EVENT_SRC = 51,\n\tPWRAP_DEW_EVENT_FLAG = 52,\n\tPWRAP_DEW_MON_FLAG_SEL = 53,\n\tPWRAP_DEW_EVENT_TEST = 54,\n\tPWRAP_DEW_CIPHER_LOAD = 55,\n\tPWRAP_DEW_CIPHER_START = 56,\n};\n\nenum dfll_ctrl_mode {\n\tDFLL_UNINITIALIZED = 0,\n\tDFLL_DISABLED = 1,\n\tDFLL_OPEN_LOOP = 2,\n\tDFLL_CLOSED_LOOP = 3,\n};\n\nenum dfll_tune_range {\n\tDFLL_TUNE_UNINITIALIZED = 0,\n\tDFLL_TUNE_LOW = 1,\n};\n\nenum die_val {\n\tDIE_UNUSED = 0,\n\tDIE_OOPS = 1,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum discover_event {\n\tDISCE_DISCOVER_DOMAIN = 0,\n\tDISCE_REVALIDATE_DOMAIN = 1,\n\tDISCE_SUSPEND = 2,\n\tDISCE_RESUME = 3,\n\tDISC_NUM_EVENTS = 4,\n};\n\nenum display_flags {\n\tDISPLAY_FLAGS_HSYNC_LOW = 1,\n\tDISPLAY_FLAGS_HSYNC_HIGH = 2,\n\tDISPLAY_FLAGS_VSYNC_LOW = 4,\n\tDISPLAY_FLAGS_VSYNC_HIGH = 8,\n\tDISPLAY_FLAGS_DE_LOW = 16,\n\tDISPLAY_FLAGS_DE_HIGH = 32,\n\tDISPLAY_FLAGS_PIXDATA_POSEDGE = 64,\n\tDISPLAY_FLAGS_PIXDATA_NEGEDGE = 128,\n\tDISPLAY_FLAGS_INTERLACED = 256,\n\tDISPLAY_FLAGS_DOUBLESCAN = 512,\n\tDISPLAY_FLAGS_DOUBLECLK = 1024,\n\tDISPLAY_FLAGS_SYNC_POSEDGE = 2048,\n\tDISPLAY_FLAGS_SYNC_NEGEDGE = 4096,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dll_reset_type {\n\tPM_DLL_RESET_ASSERT = 0,\n\tPM_DLL_RESET_RELEASE = 1,\n\tPM_DLL_RESET_PULSE = 2,\n};\n\nenum dma_channel_status {\n\tMUSB_DMA_STATUS_UNKNOWN = 0,\n\tMUSB_DMA_STATUS_FREE = 1,\n\tMUSB_DMA_STATUS_BUSY = 2,\n\tMUSB_DMA_STATUS_BUS_ABORT = 3,\n\tMUSB_DMA_STATUS_CORE_ABORT = 4,\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n\tDMA_PREP_REPEAT = 256,\n\tDMA_PREP_LOAD_EOT = 512,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SEQNO64_BIT = 0,\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 1,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 2,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 3,\n\tDMA_FENCE_FLAG_USER_BITS = 4,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nenum dma_resv_usage {\n\tDMA_RESV_USAGE_KERNEL = 0,\n\tDMA_RESV_USAGE_WRITE = 1,\n\tDMA_RESV_USAGE_READ = 2,\n\tDMA_RESV_USAGE_BOOKKEEP = 3,\n};\n\nenum dma_rx_status {\n\tDMA_RX_START = 0,\n\tDMA_RX_RUNNING = 1,\n\tDMA_RX_SHUTDOWN = 2,\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n\tDMA_SLAVE_BUSWIDTH_128_BYTES = 128,\n};\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n\tDMA_OUT_OF_ORDER = 4,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_COMPLETION_NO_ORDER = 13,\n\tDMA_REPEAT = 14,\n\tDMA_LOAD_EOT = 15,\n\tDMA_TX_TYPE_END = 16,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n\tDMAENGINE_ALIGN_128_BYTES = 7,\n\tDMAENGINE_ALIGN_256_BYTES = 8,\n};\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nenum dmamov_dst {\n\tSAR = 0,\n\tCCR = 1,\n\tDAR = 2,\n};\n\nenum dmi_device_type {\n\tDMI_DEV_TYPE_ANY = 0,\n\tDMI_DEV_TYPE_OTHER = 1,\n\tDMI_DEV_TYPE_UNKNOWN = 2,\n\tDMI_DEV_TYPE_VIDEO = 3,\n\tDMI_DEV_TYPE_SCSI = 4,\n\tDMI_DEV_TYPE_ETHERNET = 5,\n\tDMI_DEV_TYPE_TOKENRING = 6,\n\tDMI_DEV_TYPE_SOUND = 7,\n\tDMI_DEV_TYPE_PATA = 8,\n\tDMI_DEV_TYPE_SATA = 9,\n\tDMI_DEV_TYPE_SAS = 10,\n\tDMI_DEV_TYPE_IPMI = -1,\n\tDMI_DEV_TYPE_OEM_STRING = -2,\n\tDMI_DEV_TYPE_DEV_ONBOARD = -3,\n\tDMI_DEV_TYPE_DEV_SLOT = -4,\n};\n\nenum dmi_entry_type {\n\tDMI_ENTRY_BIOS = 0,\n\tDMI_ENTRY_SYSTEM = 1,\n\tDMI_ENTRY_BASEBOARD = 2,\n\tDMI_ENTRY_CHASSIS = 3,\n\tDMI_ENTRY_PROCESSOR = 4,\n\tDMI_ENTRY_MEM_CONTROLLER = 5,\n\tDMI_ENTRY_MEM_MODULE = 6,\n\tDMI_ENTRY_CACHE = 7,\n\tDMI_ENTRY_PORT_CONNECTOR = 8,\n\tDMI_ENTRY_SYSTEM_SLOT = 9,\n\tDMI_ENTRY_ONBOARD_DEVICE = 10,\n\tDMI_ENTRY_OEMSTRINGS = 11,\n\tDMI_ENTRY_SYSCONF = 12,\n\tDMI_ENTRY_BIOS_LANG = 13,\n\tDMI_ENTRY_GROUP_ASSOC = 14,\n\tDMI_ENTRY_SYSTEM_EVENT_LOG = 15,\n\tDMI_ENTRY_PHYS_MEM_ARRAY = 16,\n\tDMI_ENTRY_MEM_DEVICE = 17,\n\tDMI_ENTRY_32_MEM_ERROR = 18,\n\tDMI_ENTRY_MEM_ARRAY_MAPPED_ADDR = 19,\n\tDMI_ENTRY_MEM_DEV_MAPPED_ADDR = 20,\n\tDMI_ENTRY_BUILTIN_POINTING_DEV = 21,\n\tDMI_ENTRY_PORTABLE_BATTERY = 22,\n\tDMI_ENTRY_SYSTEM_RESET = 23,\n\tDMI_ENTRY_HW_SECURITY = 24,\n\tDMI_ENTRY_SYSTEM_POWER_CONTROLS = 25,\n\tDMI_ENTRY_VOLTAGE_PROBE = 26,\n\tDMI_ENTRY_COOLING_DEV = 27,\n\tDMI_ENTRY_TEMP_PROBE = 28,\n\tDMI_ENTRY_ELECTRICAL_CURRENT_PROBE = 29,\n\tDMI_ENTRY_OOB_REMOTE_ACCESS = 30,\n\tDMI_ENTRY_BIS_ENTRY = 31,\n\tDMI_ENTRY_SYSTEM_BOOT = 32,\n\tDMI_ENTRY_MGMT_DEV = 33,\n\tDMI_ENTRY_MGMT_DEV_COMPONENT = 34,\n\tDMI_ENTRY_MGMT_DEV_THRES = 35,\n\tDMI_ENTRY_MEM_CHANNEL = 36,\n\tDMI_ENTRY_IPMI_DEV = 37,\n\tDMI_ENTRY_SYS_POWER_SUPPLY = 38,\n\tDMI_ENTRY_ADDITIONAL = 39,\n\tDMI_ENTRY_ONBOARD_DEV_EXT = 40,\n\tDMI_ENTRY_MGMT_CONTROLLER_HOST = 41,\n\tDMI_ENTRY_INACTIVE = 126,\n\tDMI_ENTRY_END_OF_TABLE = 127,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dpaa2_eth_fq_type {\n\tDPAA2_RX_FQ = 0,\n\tDPAA2_TX_CONF_FQ = 1,\n\tDPAA2_RX_ERR_FQ = 2,\n};\n\nenum dpaa2_eth_rx_dist {\n\tDPAA2_ETH_RX_DIST_HASH = 0,\n\tDPAA2_ETH_RX_DIST_CLS = 1,\n};\n\nenum dpaa2_eth_swa_type {\n\tDPAA2_ETH_SWA_SINGLE = 0,\n\tDPAA2_ETH_SWA_SG = 1,\n\tDPAA2_ETH_SWA_XDP = 2,\n\tDPAA2_ETH_SWA_XSK = 3,\n\tDPAA2_ETH_SWA_SW_TSO = 4,\n};\n\nenum dpaa2_fd_format {\n\tdpaa2_fd_single = 0,\n\tdpaa2_fd_list = 1,\n\tdpaa2_fd_sg = 2,\n};\n\nenum dpaa_fq_type {\n\tFQ_TYPE_RX_DEFAULT = 1,\n\tFQ_TYPE_RX_ERROR = 2,\n\tFQ_TYPE_RX_PCD = 3,\n\tFQ_TYPE_TX = 4,\n\tFQ_TYPE_TX_CONFIRM = 5,\n\tFQ_TYPE_TX_CONF_MQ = 6,\n\tFQ_TYPE_TX_ERROR = 7,\n};\n\nenum dpfe_commands {\n\tDPFE_CMD_GET_INFO = 0,\n\tDPFE_CMD_GET_REFRESH = 1,\n\tDPFE_CMD_GET_VENDOR = 2,\n\tDPFE_CMD_MAX = 3,\n};\n\nenum dpfe_msg_fields {\n\tMSG_HEADER = 0,\n\tMSG_COMMAND = 1,\n\tMSG_ARG_COUNT = 2,\n\tMSG_ARG0 = 3,\n\tMSG_FIELD_MAX = 16,\n};\n\nenum dpio_channel_mode {\n\tDPIO_NO_CHANNEL = 0,\n\tDPIO_LOCAL_CHANNEL = 1,\n};\n\nenum dpkg_extract_from_hdr_type {\n\tDPKG_FROM_HDR = 0,\n\tDPKG_FROM_FIELD = 1,\n\tDPKG_FULL_FIELD = 2,\n};\n\nenum dpkg_extract_type {\n\tDPKG_EXTRACT_FROM_HDR = 0,\n\tDPKG_EXTRACT_FROM_DATA = 1,\n\tDPKG_EXTRACT_FROM_PARSE = 3,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum dpmac_counter_id {\n\tDPMAC_CNT_ING_FRAME_64 = 0,\n\tDPMAC_CNT_ING_FRAME_127 = 1,\n\tDPMAC_CNT_ING_FRAME_255 = 2,\n\tDPMAC_CNT_ING_FRAME_511 = 3,\n\tDPMAC_CNT_ING_FRAME_1023 = 4,\n\tDPMAC_CNT_ING_FRAME_1518 = 5,\n\tDPMAC_CNT_ING_FRAME_1519_MAX = 6,\n\tDPMAC_CNT_ING_FRAG = 7,\n\tDPMAC_CNT_ING_JABBER = 8,\n\tDPMAC_CNT_ING_FRAME_DISCARD = 9,\n\tDPMAC_CNT_ING_ALIGN_ERR = 10,\n\tDPMAC_CNT_EGR_UNDERSIZED = 11,\n\tDPMAC_CNT_ING_OVERSIZED = 12,\n\tDPMAC_CNT_ING_VALID_PAUSE_FRAME = 13,\n\tDPMAC_CNT_EGR_VALID_PAUSE_FRAME = 14,\n\tDPMAC_CNT_ING_BYTE = 15,\n\tDPMAC_CNT_ING_MCAST_FRAME = 16,\n\tDPMAC_CNT_ING_BCAST_FRAME = 17,\n\tDPMAC_CNT_ING_ALL_FRAME = 18,\n\tDPMAC_CNT_ING_UCAST_FRAME = 19,\n\tDPMAC_CNT_ING_ERR_FRAME = 20,\n\tDPMAC_CNT_EGR_BYTE = 21,\n\tDPMAC_CNT_EGR_MCAST_FRAME = 22,\n\tDPMAC_CNT_EGR_BCAST_FRAME = 23,\n\tDPMAC_CNT_EGR_UCAST_FRAME = 24,\n\tDPMAC_CNT_EGR_ERR_FRAME = 25,\n\tDPMAC_CNT_ING_GOOD_FRAME = 26,\n\tDPMAC_CNT_EGR_GOOD_FRAME = 27,\n};\n\nenum dpmac_eth_if {\n\tDPMAC_ETH_IF_MII = 0,\n\tDPMAC_ETH_IF_RMII = 1,\n\tDPMAC_ETH_IF_SMII = 2,\n\tDPMAC_ETH_IF_GMII = 3,\n\tDPMAC_ETH_IF_RGMII = 4,\n\tDPMAC_ETH_IF_SGMII = 5,\n\tDPMAC_ETH_IF_QSGMII = 6,\n\tDPMAC_ETH_IF_XAUI = 7,\n\tDPMAC_ETH_IF_XFI = 8,\n\tDPMAC_ETH_IF_CAUI = 9,\n\tDPMAC_ETH_IF_1000BASEX = 10,\n\tDPMAC_ETH_IF_USXGMII = 11,\n};\n\nenum dpmac_link_type {\n\tDPMAC_LINK_TYPE_NONE = 0,\n\tDPMAC_LINK_TYPE_FIXED = 1,\n\tDPMAC_LINK_TYPE_PHY = 2,\n\tDPMAC_LINK_TYPE_BACKPLANE = 3,\n};\n\nenum dpni_congestion_point {\n\tDPNI_CP_QUEUE = 0,\n\tDPNI_CP_GROUP = 1,\n};\n\nenum dpni_congestion_unit {\n\tDPNI_CONGESTION_UNIT_BYTES = 0,\n\tDPNI_CONGESTION_UNIT_FRAMES = 1,\n};\n\nenum dpni_dest {\n\tDPNI_DEST_NONE = 0,\n\tDPNI_DEST_DPIO = 1,\n\tDPNI_DEST_DPCON = 2,\n};\n\nenum dpni_dist_mode {\n\tDPNI_DIST_MODE_NONE = 0,\n\tDPNI_DIST_MODE_HASH = 1,\n\tDPNI_DIST_MODE_FS = 2,\n};\n\nenum dpni_error_action {\n\tDPNI_ERROR_ACTION_DISCARD = 0,\n\tDPNI_ERROR_ACTION_CONTINUE = 1,\n\tDPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2,\n};\n\nenum dpni_fs_miss_action {\n\tDPNI_FS_MISS_DROP = 0,\n\tDPNI_FS_MISS_EXPLICIT_FLOWID = 1,\n\tDPNI_FS_MISS_HASH = 2,\n};\n\nenum dpni_offload {\n\tDPNI_OFF_RX_L3_CSUM = 0,\n\tDPNI_OFF_RX_L4_CSUM = 1,\n\tDPNI_OFF_TX_L3_CSUM = 2,\n\tDPNI_OFF_TX_L4_CSUM = 3,\n};\n\nenum dpni_queue_type {\n\tDPNI_QUEUE_RX = 0,\n\tDPNI_QUEUE_TX = 1,\n\tDPNI_QUEUE_TX_CONFIRM = 2,\n\tDPNI_QUEUE_RX_ERR = 3,\n};\n\nenum dprc_region_type {\n\tDPRC_REGION_TYPE_MC_PORTAL = 0,\n\tDPRC_REGION_TYPE_QBMAN_PORTAL = 1,\n\tDPRC_REGION_TYPE_QBMAN_MEM_BACKED_PORTAL = 2,\n};\n\nenum drbg_prefixes {\n\tDRBG_PREFIX0 = 0,\n\tDRBG_PREFIX1 = 1,\n\tDRBG_PREFIX2 = 2,\n\tDRBG_PREFIX3 = 3,\n};\n\nenum drbg_seed_state {\n\tDRBG_SEED_STATE_UNSEEDED = 0,\n\tDRBG_SEED_STATE_PARTIAL = 1,\n\tDRBG_SEED_STATE_FULL = 2,\n};\n\nenum drm_panel_orientation {\n\tDRM_MODE_PANEL_ORIENTATION_UNKNOWN = -1,\n\tDRM_MODE_PANEL_ORIENTATION_NORMAL = 0,\n\tDRM_MODE_PANEL_ORIENTATION_BOTTOM_UP = 1,\n\tDRM_MODE_PANEL_ORIENTATION_LEFT_UP = 2,\n\tDRM_MODE_PANEL_ORIENTATION_RIGHT_UP = 3,\n};\n\nenum drvtype {\n\tLEGACY = 0,\n\tSYSCON = 1,\n};\n\nenum dsa_db_type {\n\tDSA_DB_PORT = 0,\n\tDSA_DB_LAG = 1,\n\tDSA_DB_BRIDGE = 2,\n};\n\nenum dsa_tag_protocol {\n\tDSA_TAG_PROTO_NONE = 0,\n\tDSA_TAG_PROTO_BRCM = 1,\n\tDSA_TAG_PROTO_BRCM_LEGACY = 22,\n\tDSA_TAG_PROTO_BRCM_LEGACY_FCS = 29,\n\tDSA_TAG_PROTO_BRCM_PREPEND = 2,\n\tDSA_TAG_PROTO_DSA = 3,\n\tDSA_TAG_PROTO_EDSA = 4,\n\tDSA_TAG_PROTO_GSWIP = 5,\n\tDSA_TAG_PROTO_KSZ9477 = 6,\n\tDSA_TAG_PROTO_KSZ9893 = 7,\n\tDSA_TAG_PROTO_LAN9303 = 8,\n\tDSA_TAG_PROTO_MTK = 9,\n\tDSA_TAG_PROTO_QCA = 10,\n\tDSA_TAG_PROTO_TRAILER = 11,\n\tDSA_TAG_PROTO_8021Q = 12,\n\tDSA_TAG_PROTO_SJA1105 = 13,\n\tDSA_TAG_PROTO_KSZ8795 = 14,\n\tDSA_TAG_PROTO_OCELOT = 15,\n\tDSA_TAG_PROTO_AR9331 = 16,\n\tDSA_TAG_PROTO_RTL4_A = 17,\n\tDSA_TAG_PROTO_HELLCREEK = 18,\n\tDSA_TAG_PROTO_XRS700X = 19,\n\tDSA_TAG_PROTO_OCELOT_8021Q = 20,\n\tDSA_TAG_PROTO_SEVILLE = 21,\n\tDSA_TAG_PROTO_SJA1110 = 23,\n\tDSA_TAG_PROTO_RTL8_4 = 24,\n\tDSA_TAG_PROTO_RTL8_4T = 25,\n\tDSA_TAG_PROTO_RZN1_A5PSW = 26,\n\tDSA_TAG_PROTO_LAN937X = 27,\n\tDSA_TAG_PROTO_VSC73XX_8021Q = 28,\n\tDSA_TAG_PROTO_YT921X = 30,\n\tDSA_TAG_PROTO_MXL_GSW1XX = 31,\n\tDSA_TAG_PROTO_MXL862 = 32,\n};\n\nenum dsaf_mode {\n\tDSAF_MODE_INVALID = 0,\n\tDSAF_MODE_ENABLE_FIX = 1,\n\tDSAF_MODE_ENABLE_0VM = 2,\n\tDSAF_MODE_ENABLE_8VM = 3,\n\tDSAF_MODE_ENABLE_16VM = 4,\n\tDSAF_MODE_ENABLE_32VM = 5,\n\tDSAF_MODE_ENABLE_128VM = 6,\n\tDSAF_MODE_ENABLE = 7,\n\tDSAF_MODE_DISABLE_SP = 8,\n\tDSAF_MODE_DISABLE_FIX = 9,\n\tDSAF_MODE_DISABLE_2PORT_8VM = 10,\n\tDSAF_MODE_DISABLE_2PORT_16VM = 11,\n\tDSAF_MODE_DISABLE_2PORT_64VM = 12,\n\tDSAF_MODE_DISABLE_6PORT_0VM = 13,\n\tDSAF_MODE_DISABLE_6PORT_2VM = 14,\n\tDSAF_MODE_DISABLE_6PORT_4VM = 15,\n\tDSAF_MODE_DISABLE_6PORT_16VM = 16,\n\tDSAF_MODE_MAX = 17,\n};\n\nenum dsaf_port_rate_mode {\n\tDSAF_PORT_RATE_1000 = 0,\n\tDSAF_PORT_RATE_2500 = 1,\n\tDSAF_PORT_RATE_10000 = 2,\n};\n\nenum dsaf_stp_port_type {\n\tDSAF_STP_PORT_TYPE_DISCARD = 0,\n\tDSAF_STP_PORT_TYPE_BLOCK = 1,\n\tDSAF_STP_PORT_TYPE_LISTEN = 2,\n\tDSAF_STP_PORT_TYPE_LEARN = 3,\n\tDSAF_STP_PORT_TYPE_FORWARD = 4,\n};\n\nenum dsaf_sw_port_type {\n\tDSAF_SW_PORT_TYPE_NON_VLAN = 0,\n\tDSAF_SW_PORT_TYPE_ACCESS = 1,\n\tDSAF_SW_PORT_TYPE_TRUNK = 2,\n};\n\nenum dspi_trans_mode {\n\tDSPI_XSPI_MODE = 0,\n\tDSPI_DMA_MODE = 1,\n};\n\nenum dw_edma_chip_flags {\n\tDW_EDMA_CHIP_LOCAL = 1,\n};\n\nenum dw_edma_map_format {\n\tEDMA_MF_EDMA_LEGACY = 0,\n\tEDMA_MF_EDMA_UNROLL = 1,\n\tEDMA_MF_HDMA_COMPAT = 5,\n\tEDMA_MF_HDMA_NATIVE = 7,\n};\n\nenum dw_mci_cookie {\n\tCOOKIE_UNMAPPED = 0,\n\tCOOKIE_PRE_MAPPED = 1,\n\tCOOKIE_MAPPED = 2,\n};\n\nenum dw_mci_exynos_type {\n\tDW_MCI_TYPE_EXYNOS4210 = 0,\n\tDW_MCI_TYPE_EXYNOS4412 = 1,\n\tDW_MCI_TYPE_EXYNOS5250 = 2,\n\tDW_MCI_TYPE_EXYNOS5420 = 3,\n\tDW_MCI_TYPE_EXYNOS5420_SMU = 4,\n\tDW_MCI_TYPE_EXYNOS7 = 5,\n\tDW_MCI_TYPE_EXYNOS7_SMU = 6,\n\tDW_MCI_TYPE_EXYNOS7870 = 7,\n\tDW_MCI_TYPE_EXYNOS7870_SMU = 8,\n\tDW_MCI_TYPE_ARTPEC8 = 9,\n};\n\nenum dw_mci_state {\n\tSTATE_IDLE___2 = 0,\n\tSTATE_SENDING_CMD = 1,\n\tSTATE_SENDING_DATA = 2,\n\tSTATE_DATA_BUSY = 3,\n\tSTATE_SENDING_STOP = 4,\n\tSTATE_DATA_ERROR = 5,\n\tSTATE_SENDING_CMD11 = 6,\n\tSTATE_WAITING_CMD11_DONE = 7,\n};\n\nenum dw_pcie_app_clk {\n\tDW_PCIE_DBI_CLK = 0,\n\tDW_PCIE_MSTR_CLK = 1,\n\tDW_PCIE_SLV_CLK = 2,\n\tDW_PCIE_NUM_APP_CLKS = 3,\n};\n\nenum dw_pcie_app_rst {\n\tDW_PCIE_DBI_RST = 0,\n\tDW_PCIE_MSTR_RST = 1,\n\tDW_PCIE_SLV_RST = 2,\n\tDW_PCIE_NUM_APP_RSTS = 3,\n};\n\nenum dw_pcie_core_clk {\n\tDW_PCIE_PIPE_CLK = 0,\n\tDW_PCIE_CORE_CLK = 1,\n\tDW_PCIE_AUX_CLK = 2,\n\tDW_PCIE_REF_CLK = 3,\n\tDW_PCIE_NUM_CORE_CLKS = 4,\n};\n\nenum dw_pcie_core_rst {\n\tDW_PCIE_NON_STICKY_RST = 0,\n\tDW_PCIE_STICKY_RST = 1,\n\tDW_PCIE_CORE_RST = 2,\n\tDW_PCIE_PIPE_RST = 3,\n\tDW_PCIE_PHY_RST = 4,\n\tDW_PCIE_HOT_RST = 5,\n\tDW_PCIE_PWR_RST = 6,\n\tDW_PCIE_NUM_CORE_RSTS = 7,\n};\n\nenum dw_pcie_device_mode {\n\tDW_PCIE_UNKNOWN_TYPE = 0,\n\tDW_PCIE_EP_TYPE = 1,\n\tDW_PCIE_LEG_EP_TYPE = 2,\n\tDW_PCIE_RC_TYPE = 3,\n};\n\nenum dw_pcie_ltssm {\n\tDW_PCIE_LTSSM_DETECT_QUIET = 0,\n\tDW_PCIE_LTSSM_DETECT_ACT = 1,\n\tDW_PCIE_LTSSM_POLL_ACTIVE = 2,\n\tDW_PCIE_LTSSM_POLL_COMPLIANCE = 3,\n\tDW_PCIE_LTSSM_POLL_CONFIG = 4,\n\tDW_PCIE_LTSSM_PRE_DETECT_QUIET = 5,\n\tDW_PCIE_LTSSM_DETECT_WAIT = 6,\n\tDW_PCIE_LTSSM_CFG_LINKWD_START = 7,\n\tDW_PCIE_LTSSM_CFG_LINKWD_ACEPT = 8,\n\tDW_PCIE_LTSSM_CFG_LANENUM_WAI = 9,\n\tDW_PCIE_LTSSM_CFG_LANENUM_ACEPT = 10,\n\tDW_PCIE_LTSSM_CFG_COMPLETE = 11,\n\tDW_PCIE_LTSSM_CFG_IDLE = 12,\n\tDW_PCIE_LTSSM_RCVRY_LOCK = 13,\n\tDW_PCIE_LTSSM_RCVRY_SPEED = 14,\n\tDW_PCIE_LTSSM_RCVRY_RCVRCFG = 15,\n\tDW_PCIE_LTSSM_RCVRY_IDLE = 16,\n\tDW_PCIE_LTSSM_L0 = 17,\n\tDW_PCIE_LTSSM_L0S = 18,\n\tDW_PCIE_LTSSM_L123_SEND_EIDLE = 19,\n\tDW_PCIE_LTSSM_L1_IDLE = 20,\n\tDW_PCIE_LTSSM_L2_IDLE = 21,\n\tDW_PCIE_LTSSM_L2_WAKE = 22,\n\tDW_PCIE_LTSSM_DISABLED_ENTRY = 23,\n\tDW_PCIE_LTSSM_DISABLED_IDLE = 24,\n\tDW_PCIE_LTSSM_DISABLED = 25,\n\tDW_PCIE_LTSSM_LPBK_ENTRY = 26,\n\tDW_PCIE_LTSSM_LPBK_ACTIVE = 27,\n\tDW_PCIE_LTSSM_LPBK_EXIT = 28,\n\tDW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT = 29,\n\tDW_PCIE_LTSSM_HOT_RESET_ENTRY = 30,\n\tDW_PCIE_LTSSM_HOT_RESET = 31,\n\tDW_PCIE_LTSSM_RCVRY_EQ0 = 32,\n\tDW_PCIE_LTSSM_RCVRY_EQ1 = 33,\n\tDW_PCIE_LTSSM_RCVRY_EQ2 = 34,\n\tDW_PCIE_LTSSM_RCVRY_EQ3 = 35,\n\tDW_PCIE_LTSSM_L1_1 = 321,\n\tDW_PCIE_LTSSM_L1_2 = 322,\n\tDW_PCIE_LTSSM_UNKNOWN = 4294967295,\n};\n\nenum dw_wdt_rmod {\n\tDW_WDT_RMOD_RESET = 1,\n\tDW_WDT_RMOD_IRQ = 2,\n};\n\nenum dwc2_control_phase {\n\tDWC2_CONTROL_SETUP = 0,\n\tDWC2_CONTROL_DATA = 1,\n\tDWC2_CONTROL_STATUS = 2,\n};\n\nenum dwc2_ep0_state {\n\tDWC2_EP0_SETUP = 0,\n\tDWC2_EP0_DATA_IN = 1,\n\tDWC2_EP0_DATA_OUT = 2,\n\tDWC2_EP0_STATUS_IN = 3,\n\tDWC2_EP0_STATUS_OUT = 4,\n};\n\nenum dwc2_halt_status {\n\tDWC2_HC_XFER_NO_HALT_STATUS = 0,\n\tDWC2_HC_XFER_COMPLETE = 1,\n\tDWC2_HC_XFER_URB_COMPLETE = 2,\n\tDWC2_HC_XFER_ACK = 3,\n\tDWC2_HC_XFER_NAK = 4,\n\tDWC2_HC_XFER_NYET = 5,\n\tDWC2_HC_XFER_STALL = 6,\n\tDWC2_HC_XFER_XACT_ERR = 7,\n\tDWC2_HC_XFER_FRAME_OVERRUN = 8,\n\tDWC2_HC_XFER_BABBLE_ERR = 9,\n\tDWC2_HC_XFER_DATA_TOGGLE_ERR = 10,\n\tDWC2_HC_XFER_AHB_ERR = 11,\n\tDWC2_HC_XFER_PERIODIC_INCOMPLETE = 12,\n\tDWC2_HC_XFER_URB_DEQUEUE = 13,\n};\n\nenum dwc2_hsotg_dmamode {\n\tS3C_HSOTG_DMA_NONE = 0,\n\tS3C_HSOTG_DMA_ONLY = 1,\n\tS3C_HSOTG_DMA_DRV = 2,\n};\n\nenum dwc2_lx_state {\n\tDWC2_L0 = 0,\n\tDWC2_L1 = 1,\n\tDWC2_L2 = 2,\n\tDWC2_L3 = 3,\n};\n\nenum dwc2_transaction_type {\n\tDWC2_TRANSACTION_NONE = 0,\n\tDWC2_TRANSACTION_PERIODIC = 1,\n\tDWC2_TRANSACTION_NON_PERIODIC = 2,\n\tDWC2_TRANSACTION_ALL = 3,\n};\n\nenum dwc3_apple_state {\n\tDWC3_APPLE_PROBE_PENDING = 0,\n\tDWC3_APPLE_NO_CABLE = 1,\n\tDWC3_APPLE_HOST = 2,\n\tDWC3_APPLE_DEVICE = 3,\n};\n\nenum dwc3_ep0_next {\n\tDWC3_EP0_UNKNOWN = 0,\n\tDWC3_EP0_COMPLETE = 1,\n\tDWC3_EP0_NRDY_DATA = 2,\n\tDWC3_EP0_NRDY_STATUS = 3,\n};\n\nenum dwc3_ep0_state {\n\tEP0_UNCONNECTED = 0,\n\tEP0_SETUP_PHASE = 1,\n\tEP0_DATA_PHASE = 2,\n\tEP0_STATUS_PHASE = 3,\n};\n\nenum dwc3_link_state {\n\tDWC3_LINK_STATE_U0 = 0,\n\tDWC3_LINK_STATE_U1 = 1,\n\tDWC3_LINK_STATE_U2 = 2,\n\tDWC3_LINK_STATE_U3 = 3,\n\tDWC3_LINK_STATE_SS_DIS = 4,\n\tDWC3_LINK_STATE_RX_DET = 5,\n\tDWC3_LINK_STATE_SS_INACT = 6,\n\tDWC3_LINK_STATE_POLL = 7,\n\tDWC3_LINK_STATE_RECOV = 8,\n\tDWC3_LINK_STATE_HRESET = 9,\n\tDWC3_LINK_STATE_CMPLY = 10,\n\tDWC3_LINK_STATE_LPBK = 11,\n\tDWC3_LINK_STATE_RESET = 14,\n\tDWC3_LINK_STATE_RESUME = 15,\n\tDWC3_LINK_STATE_MASK = 15,\n};\n\nenum dwcmshc_rk_type {\n\tDWCMSHC_RK3568 = 0,\n\tDWCMSHC_RK3588 = 1,\n};\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok___2 = 0,\n\te1000_1000t_rx_status_ok___2 = 1,\n\te1000_1000t_rx_status_undefined___2 = 255,\n};\n\nenum e1000_boards {\n\tboard_82571 = 0,\n\tboard_82572 = 1,\n\tboard_82573 = 2,\n\tboard_82574 = 3,\n\tboard_82583 = 4,\n\tboard_80003es2lan = 5,\n\tboard_ich8lan = 6,\n\tboard_ich9lan = 7,\n\tboard_ich10lan = 8,\n\tboard_pchlan = 9,\n\tboard_pch2lan = 10,\n\tboard_pch_lpt = 11,\n\tboard_pch_spt = 12,\n\tboard_pch_cnp = 13,\n\tboard_pch_tgp = 14,\n\tboard_pch_adp = 15,\n\tboard_pch_mtp = 16,\n\tboard_pch_ptp = 17,\n};\n\nenum e1000_bus_speed {\n\te1000_bus_speed_unknown___2 = 0,\n\te1000_bus_speed_33___2 = 1,\n\te1000_bus_speed_66___2 = 2,\n\te1000_bus_speed_100___2 = 3,\n\te1000_bus_speed_120___2 = 4,\n\te1000_bus_speed_133___2 = 5,\n\te1000_bus_speed_2500 = 6,\n\te1000_bus_speed_5000 = 7,\n\te1000_bus_speed_reserved___2 = 8,\n};\n\nenum e1000_bus_type {\n\te1000_bus_type_unknown___2 = 0,\n\te1000_bus_type_pci___2 = 1,\n\te1000_bus_type_pcix___2 = 2,\n\te1000_bus_type_pci_express = 3,\n\te1000_bus_type_reserved___2 = 4,\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown___2 = 0,\n\te1000_bus_width_pcie_x1 = 1,\n\te1000_bus_width_pcie_x2 = 2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32___2 = 9,\n\te1000_bus_width_64___2 = 10,\n\te1000_bus_width_reserved___2 = 11,\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause = 1,\n\te1000_fc_tx_pause = 2,\n\te1000_fc_full = 3,\n\te1000_fc_default = 255,\n};\n\nenum e1000_mac_type {\n\te1000_undefined___2 = 0,\n\te1000_vfadapt = 1,\n\te1000_vfadapt_i350 = 2,\n\te1000_num_macs___2 = 3,\n};\n\nenum e1000_mac_type___2 {\n\te1000_82571 = 0,\n\te1000_82572 = 1,\n\te1000_82573 = 2,\n\te1000_82574 = 3,\n\te1000_82583 = 4,\n\te1000_80003es2lan = 5,\n\te1000_ich8lan = 6,\n\te1000_ich9lan = 7,\n\te1000_ich10lan = 8,\n\te1000_pchlan = 9,\n\te1000_pch2lan = 10,\n\te1000_pch_lpt = 11,\n\te1000_pch_spt = 12,\n\te1000_pch_cnp = 13,\n\te1000_pch_tgp = 14,\n\te1000_pch_adp = 15,\n\te1000_pch_mtp = 16,\n\te1000_pch_lnp = 17,\n\te1000_pch_ptp = 18,\n\te1000_pch_nvp = 19,\n};\n\nenum e1000_mac_type___3 {\n\te1000_undefined___3 = 0,\n\te1000_82575 = 1,\n\te1000_82576 = 2,\n\te1000_82580 = 3,\n\te1000_i350 = 4,\n\te1000_i354 = 5,\n\te1000_i210 = 6,\n\te1000_i211 = 7,\n\te1000_num_macs___3 = 8,\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper___2 = 1,\n\te1000_media_type_fiber___2 = 2,\n\te1000_media_type_internal_serdes___2 = 3,\n\te1000_num_media_types___2 = 4,\n};\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf = 1,\n\te1000_mng_mode_pt = 2,\n\te1000_mng_mode_ipmi = 3,\n\te1000_mng_mode_host_if_only = 4,\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default___2 = 0,\n\te1000_ms_force_master___2 = 1,\n\te1000_ms_force_slave___2 = 2,\n\te1000_ms_auto___2 = 3,\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small = 1,\n\te1000_nvm_override_spi_large = 2,\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none = 1,\n\te1000_nvm_eeprom_spi = 2,\n\te1000_nvm_flash_hw = 3,\n\te1000_nvm_invm = 4,\n\te1000_nvm_flash_sw = 5,\n};\n\nenum e1000_nvm_type___2 {\n\te1000_nvm_unknown___2 = 0,\n\te1000_nvm_none___2 = 1,\n\te1000_nvm_eeprom_spi___2 = 2,\n\te1000_nvm_flash_hw___2 = 3,\n\te1000_nvm_flash_sw___2 = 4,\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none = 1,\n\te1000_phy_m88___2 = 2,\n\te1000_phy_igp___2 = 3,\n\te1000_phy_igp_2 = 4,\n\te1000_phy_gg82563 = 5,\n\te1000_phy_igp_3 = 6,\n\te1000_phy_ife = 7,\n\te1000_phy_bm = 8,\n\te1000_phy_82578 = 9,\n\te1000_phy_82577 = 10,\n\te1000_phy_82579 = 11,\n\te1000_phy_i217 = 12,\n};\n\nenum e1000_phy_type___2 {\n\te1000_phy_unknown___2 = 0,\n\te1000_phy_none___2 = 1,\n\te1000_phy_m88___3 = 2,\n\te1000_phy_igp___3 = 3,\n\te1000_phy_igp_2___2 = 4,\n\te1000_phy_gg82563___2 = 5,\n\te1000_phy_igp_3___2 = 6,\n\te1000_phy_ife___2 = 7,\n\te1000_phy_82580 = 8,\n\te1000_phy_i210 = 9,\n\te1000_phy_bcm54616 = 10,\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal___2 = 0,\n\te1000_rev_polarity_reversed___2 = 1,\n\te1000_rev_polarity_undefined___2 = 255,\n};\n\nenum e1000_ring_flags_t {\n\tIGB_RING_FLAG_RX_3K_BUFFER = 0,\n\tIGB_RING_FLAG_RX_BUILD_SKB_ENABLED = 1,\n\tIGB_RING_FLAG_RX_SCTP_CSUM = 2,\n\tIGB_RING_FLAG_RX_LB_VLAN_BSWAP = 3,\n\tIGB_RING_FLAG_TX_CTX_IDX = 4,\n\tIGB_RING_FLAG_TX_DETECT_HANG = 5,\n\tIGB_RING_FLAG_TX_DISABLED = 6,\n\tIGB_RING_FLAG_RX_ALLOC_FAILED = 7,\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress = 1,\n\te1000_serdes_link_autoneg_complete = 2,\n\te1000_serdes_link_forced_up = 3,\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default___2 = 0,\n\te1000_smart_speed_on___2 = 1,\n\te1000_smart_speed_off___2 = 2,\n};\n\nenum e1000_state_t {\n\t__E1000_TESTING = 0,\n\t__E1000_RESETTING = 1,\n\t__E1000_ACCESS_SHARED_RESOURCE = 2,\n\t__E1000_DOWN = 3,\n};\n\nenum e1000_state_t___2 {\n\t__E1000_TESTING___2 = 0,\n\t__E1000_RESETTING___2 = 1,\n\t__E1000_DOWN___2 = 2,\n\t__E1000_DISABLED = 3,\n};\n\nenum e1000_state_t___3 {\n\t__IGB_TESTING = 0,\n\t__IGB_RESETTING = 1,\n\t__IGB_DOWN = 2,\n\t__IGB_PTP_TX_IN_PROGRESS = 3,\n};\n\nenum e1000_ulp_state {\n\te1000_ulp_state_unknown = 0,\n\te1000_ulp_state_off = 1,\n\te1000_ulp_state_on = 2,\n};\n\nenum ec_auto_fan_ctrl_cmd {\n\tEC_AUTO_FAN_CONTROL_CMD_SET = 0,\n\tEC_AUTO_FAN_CONTROL_CMD_GET = 1,\n};\n\nenum ec_charge_control_cmd {\n\tEC_CHARGE_CONTROL_CMD_SET = 0,\n\tEC_CHARGE_CONTROL_CMD_GET = 1,\n};\n\nenum ec_charge_control_mode {\n\tCHARGE_CONTROL_NORMAL = 0,\n\tCHARGE_CONTROL_IDLE = 1,\n\tCHARGE_CONTROL_DISCHARGE = 2,\n\tCHARGE_CONTROL_COUNT = 3,\n};\n\nenum ec_comms_status {\n\tEC_COMMS_STATUS_PROCESSING = 1,\n};\n\nenum ec_console_read_subcmd {\n\tCONSOLE_READ_NEXT = 0,\n\tCONSOLE_READ_RECENT = 1,\n};\n\nenum ec_feature_code {\n\tEC_FEATURE_LIMITED = 0,\n\tEC_FEATURE_FLASH = 1,\n\tEC_FEATURE_PWM_FAN = 2,\n\tEC_FEATURE_PWM_KEYB = 3,\n\tEC_FEATURE_LIGHTBAR = 4,\n\tEC_FEATURE_LED = 5,\n\tEC_FEATURE_MOTION_SENSE = 6,\n\tEC_FEATURE_KEYB = 7,\n\tEC_FEATURE_PSTORE = 8,\n\tEC_FEATURE_PORT80 = 9,\n\tEC_FEATURE_THERMAL = 10,\n\tEC_FEATURE_BKLIGHT_SWITCH = 11,\n\tEC_FEATURE_WIFI_SWITCH = 12,\n\tEC_FEATURE_HOST_EVENTS = 13,\n\tEC_FEATURE_GPIO = 14,\n\tEC_FEATURE_I2C = 15,\n\tEC_FEATURE_CHARGER = 16,\n\tEC_FEATURE_BATTERY = 17,\n\tEC_FEATURE_SMART_BATTERY = 18,\n\tEC_FEATURE_HANG_DETECT = 19,\n\tEC_FEATURE_PMU = 20,\n\tEC_FEATURE_SUB_MCU = 21,\n\tEC_FEATURE_USB_PD = 22,\n\tEC_FEATURE_USB_MUX = 23,\n\tEC_FEATURE_MOTION_SENSE_FIFO = 24,\n\tEC_FEATURE_VSTORE = 25,\n\tEC_FEATURE_USBC_SS_MUX_VIRTUAL = 26,\n\tEC_FEATURE_RTC = 27,\n\tEC_FEATURE_FINGERPRINT = 28,\n\tEC_FEATURE_TOUCHPAD = 29,\n\tEC_FEATURE_RWSIG = 30,\n\tEC_FEATURE_DEVICE_EVENT = 31,\n\tEC_FEATURE_UNIFIED_WAKE_MASKS = 32,\n\tEC_FEATURE_HOST_EVENT64 = 33,\n\tEC_FEATURE_EXEC_IN_RAM = 34,\n\tEC_FEATURE_CEC = 35,\n\tEC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36,\n\tEC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37,\n\tEC_FEATURE_SCP = 39,\n\tEC_FEATURE_ISH = 40,\n\tEC_FEATURE_TYPEC_CMD = 41,\n\tEC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42,\n\tEC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,\n\tEC_FEATURE_S4_RESIDENCY = 44,\n\tEC_FEATURE_TYPEC_AP_MUX_SET = 45,\n\tEC_FEATURE_TYPEC_AP_VDM_SEND = 46,\n\tEC_FEATURE_SYSTEM_SAFE_MODE = 47,\n\tEC_FEATURE_ASSERT_REBOOTS = 48,\n\tEC_FEATURE_TOKENIZED_LOGGING = 49,\n\tEC_FEATURE_AMD_STB_DUMP = 50,\n\tEC_FEATURE_MEMORY_DUMP = 51,\n\tEC_FEATURE_TYPEC_DP2_1 = 52,\n\tEC_FEATURE_SCP_C1 = 53,\n\tEC_FEATURE_UCSI_PPM = 54,\n};\n\nenum ec_led_colors {\n\tEC_LED_COLOR_RED = 0,\n\tEC_LED_COLOR_GREEN = 1,\n\tEC_LED_COLOR_BLUE = 2,\n\tEC_LED_COLOR_YELLOW = 3,\n\tEC_LED_COLOR_WHITE = 4,\n\tEC_LED_COLOR_AMBER = 5,\n\tEC_LED_COLOR_COUNT = 6,\n};\n\nenum ec_mkbp_event {\n\tEC_MKBP_EVENT_KEY_MATRIX = 0,\n\tEC_MKBP_EVENT_HOST_EVENT = 1,\n\tEC_MKBP_EVENT_SENSOR_FIFO = 2,\n\tEC_MKBP_EVENT_BUTTON = 3,\n\tEC_MKBP_EVENT_SWITCH = 4,\n\tEC_MKBP_EVENT_FINGERPRINT = 5,\n\tEC_MKBP_EVENT_SYSRQ = 6,\n\tEC_MKBP_EVENT_HOST_EVENT64 = 7,\n\tEC_MKBP_EVENT_CEC_EVENT = 8,\n\tEC_MKBP_EVENT_CEC_MESSAGE = 9,\n\tEC_MKBP_EVENT_PCHG = 12,\n\tEC_MKBP_EVENT_COUNT = 13,\n};\n\nenum ec_mkbp_info_type {\n\tEC_MKBP_INFO_KBD = 0,\n\tEC_MKBP_INFO_SUPPORTED = 1,\n\tEC_MKBP_INFO_CURRENT = 2,\n};\n\nenum ec_reboot_cmd {\n\tEC_REBOOT_CANCEL = 0,\n\tEC_REBOOT_JUMP_RO = 1,\n\tEC_REBOOT_JUMP_RW = 2,\n\tEC_REBOOT_COLD = 4,\n\tEC_REBOOT_DISABLE_JUMP = 5,\n\tEC_REBOOT_HIBERNATE = 6,\n\tEC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7,\n\tEC_REBOOT_COLD_AP_OFF = 8,\n};\n\nenum ec_status {\n\tEC_RES_SUCCESS = 0,\n\tEC_RES_INVALID_COMMAND = 1,\n\tEC_RES_ERROR = 2,\n\tEC_RES_INVALID_PARAM = 3,\n\tEC_RES_ACCESS_DENIED = 4,\n\tEC_RES_INVALID_RESPONSE = 5,\n\tEC_RES_INVALID_VERSION = 6,\n\tEC_RES_INVALID_CHECKSUM = 7,\n\tEC_RES_IN_PROGRESS = 8,\n\tEC_RES_UNAVAILABLE = 9,\n\tEC_RES_TIMEOUT = 10,\n\tEC_RES_OVERFLOW = 11,\n\tEC_RES_INVALID_HEADER = 12,\n\tEC_RES_REQUEST_TRUNCATED = 13,\n\tEC_RES_RESPONSE_TOO_BIG = 14,\n\tEC_RES_BUS_ERROR = 15,\n\tEC_RES_BUSY = 16,\n\tEC_RES_INVALID_HEADER_VERSION = 17,\n\tEC_RES_INVALID_HEADER_CRC = 18,\n\tEC_RES_INVALID_DATA_CRC = 19,\n\tEC_RES_DUP_UNAVAILABLE = 20,\n};\n\nenum ec_temp_thresholds {\n\tEC_TEMP_THRESH_WARN = 0,\n\tEC_TEMP_THRESH_HIGH = 1,\n\tEC_TEMP_THRESH_HALT = 2,\n\tEC_TEMP_THRESH_COUNT = 3,\n};\n\nenum ec_vbnvcontext_op {\n\tEC_VBNV_CONTEXT_OP_READ = 0,\n\tEC_VBNV_CONTEXT_OP_WRITE = 1,\n};\n\nenum edac_dev_feat {\n\tRAS_FEAT_SCRUB = 0,\n\tRAS_FEAT_ECS = 1,\n\tRAS_FEAT_MEM_REPAIR = 2,\n\tRAS_FEAT_MAX = 3,\n};\n\nenum edac_mc_layer_type {\n\tEDAC_MC_LAYER_BRANCH = 0,\n\tEDAC_MC_LAYER_CHANNEL = 1,\n\tEDAC_MC_LAYER_SLOT = 2,\n\tEDAC_MC_LAYER_CHIP_SELECT = 3,\n\tEDAC_MC_LAYER_ALL_MEM = 4,\n};\n\nenum edac_type {\n\tEDAC_UNKNOWN = 0,\n\tEDAC_NONE = 1,\n\tEDAC_RESERVED = 2,\n\tEDAC_PARITY = 3,\n\tEDAC_EC = 4,\n\tEDAC_SECDED = 5,\n\tEDAC_S2ECD2ED = 6,\n\tEDAC_S4ECD4ED = 7,\n\tEDAC_S8ECD8ED = 8,\n\tEDAC_S16ECD16ED = 9,\n};\n\nenum efi_cmdline_option {\n\tEFI_CMDLINE_NONE = 0,\n\tEFI_CMDLINE_MODE_NUM = 1,\n\tEFI_CMDLINE_RES = 2,\n\tEFI_CMDLINE_AUTO = 3,\n\tEFI_CMDLINE_LIST = 4,\n};\n\nenum efi_rts_ids {\n\tEFI_NONE = 0,\n\tEFI_GET_TIME = 1,\n\tEFI_SET_TIME = 2,\n\tEFI_GET_WAKEUP_TIME = 3,\n\tEFI_SET_WAKEUP_TIME = 4,\n\tEFI_GET_VARIABLE = 5,\n\tEFI_GET_NEXT_VARIABLE = 6,\n\tEFI_SET_VARIABLE = 7,\n\tEFI_QUERY_VARIABLE_INFO = 8,\n\tEFI_GET_NEXT_HIGH_MONO_COUNT = 9,\n\tEFI_RESET_SYSTEM = 10,\n\tEFI_UPDATE_CAPSULE = 11,\n\tEFI_QUERY_CAPSULE_CAPS = 12,\n\tEFI_ACPI_PRM_HANDLER = 13,\n};\n\nenum efi_secureboot_mode {\n\tefi_secureboot_mode_unset = 0,\n\tefi_secureboot_mode_unknown = 1,\n\tefi_secureboot_mode_disabled = 2,\n\tefi_secureboot_mode_enabled = 3,\n};\n\nenum efistub_event_type {\n\tEFISTUB_EVT_INITRD = 0,\n\tEFISTUB_EVT_LOAD_OPTIONS = 1,\n\tEFISTUB_EVT_COUNT = 2,\n};\n\nenum ehci_hrtimer_event {\n\tEHCI_HRTIMER_POLL_ASS = 0,\n\tEHCI_HRTIMER_POLL_PSS = 1,\n\tEHCI_HRTIMER_POLL_DEAD = 2,\n\tEHCI_HRTIMER_UNLINK_INTR = 3,\n\tEHCI_HRTIMER_FREE_ITDS = 4,\n\tEHCI_HRTIMER_ACTIVE_UNLINK = 5,\n\tEHCI_HRTIMER_START_UNLINK_INTR = 6,\n\tEHCI_HRTIMER_ASYNC_UNLINKS = 7,\n\tEHCI_HRTIMER_IAA_WATCHDOG = 8,\n\tEHCI_HRTIMER_DISABLE_PERIODIC = 9,\n\tEHCI_HRTIMER_DISABLE_ASYNC = 10,\n\tEHCI_HRTIMER_IO_WATCHDOG = 11,\n\tEHCI_HRTIMER_NUM_EVENTS = 12,\n};\n\nenum ehci_rh_state {\n\tEHCI_RH_HALTED = 0,\n\tEHCI_RH_SUSPENDED = 1,\n\tEHCI_RH_RUNNING = 2,\n\tEHCI_RH_STOPPING = 3,\n};\n\nenum eint_type {\n\tEINT_TYPE_NONE = 0,\n\tEINT_TYPE_GPIO = 1,\n\tEINT_TYPE_WKUP = 2,\n\tEINT_TYPE_WKUP_MUX = 3,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum enetc_active_offloads {\n\tENETC_F_TX_TSTAMP = 1,\n\tENETC_F_TX_ONESTEP_SYNC_TSTAMP = 2,\n\tENETC_F_RX_TSTAMP = 256,\n\tENETC_F_QBV = 512,\n\tENETC_F_QCI = 1024,\n\tENETC_F_QBU = 2048,\n\tENETC_F_TXCSUM = 4096,\n\tENETC_F_LSO = 8192,\n};\n\nenum enetc_bdr_type {\n\tTX = 0,\n\tRX = 1,\n};\n\nenum enetc_errata {\n\tENETC_ERR_VLAN_ISOL = 1,\n\tENETC_ERR_UCMCSWP = 2,\n};\n\nenum enetc_flags_bit {\n\tENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS = 0,\n\tENETC_TX_DOWN = 1,\n};\n\nenum enetc_ic_mode {\n\tENETC_IC_NONE = 0,\n\tENETC_IC_RX_MANUAL = 1,\n\tENETC_IC_TX_MANUAL = 2,\n\tENETC_IC_RX_ADAPTIVE = 4,\n};\n\nenum enetc_mac_addr_type {\n\tUC = 0,\n\tMC = 1,\n\tMADDR_TYPE = 2,\n};\n\nenum enetc_msg_cmd_action_type {\n\tENETC_MSG_CMD_MNG_ADD = 1,\n\tENETC_MSG_CMD_MNG_REMOVE = 2,\n};\n\nenum enetc_msg_cmd_status {\n\tENETC_MSG_CMD_STATUS_OK = 0,\n\tENETC_MSG_CMD_STATUS_FAIL = 1,\n};\n\nenum enetc_msg_cmd_type {\n\tENETC_MSG_CMD_MNG_MAC = 1,\n\tENETC_MSG_CMD_MNG_RX_MAC_FILTER = 2,\n\tENETC_MSG_CMD_MNG_RX_VLAN_FILTER = 3,\n};\n\nenum enetc_txbd_flags {\n\tENETC_TXBD_FLAGS_L4CS = 1,\n\tENETC_TXBD_FLAGS_TSE = 2,\n\tENETC_TXBD_FLAGS_LSO = 2,\n\tENETC_TXBD_FLAGS_W = 4,\n\tENETC_TXBD_FLAGS_CSUM_LSO = 8,\n\tENETC_TXBD_FLAGS_TXSTART = 16,\n\tENETC_TXBD_FLAGS_EX = 64,\n\tENETC_TXBD_FLAGS_F = 128,\n};\n\nenum enetc_vf_flags {\n\tENETC_VF_FLAG_PF_SET_MAC = 1,\n};\n\nenum enum_gate_cfg {\n\tGATE_ADC12 = 0,\n\tGATE_ADC3 = 1,\n\tGATE_ADF1 = 2,\n\tGATE_CCI = 3,\n\tGATE_CRC = 4,\n\tGATE_CRYP1 = 5,\n\tGATE_CRYP2 = 6,\n\tGATE_CSI = 7,\n\tGATE_DCMIPP = 8,\n\tGATE_DSI = 9,\n\tGATE_DTS = 10,\n\tGATE_ETH1 = 11,\n\tGATE_ETH1MAC = 12,\n\tGATE_ETH1RX = 13,\n\tGATE_ETH1STP = 14,\n\tGATE_ETH1TX = 15,\n\tGATE_ETH2 = 16,\n\tGATE_ETH2MAC = 17,\n\tGATE_ETH2RX = 18,\n\tGATE_ETH2STP = 19,\n\tGATE_ETH2TX = 20,\n\tGATE_ETHSW = 21,\n\tGATE_ETHSWACMCFG = 22,\n\tGATE_ETHSWACMMSG = 23,\n\tGATE_ETHSWMAC = 24,\n\tGATE_ETHSWREF = 25,\n\tGATE_FDCAN = 26,\n\tGATE_GPU = 27,\n\tGATE_HASH = 28,\n\tGATE_HDP = 29,\n\tGATE_I2C1 = 30,\n\tGATE_I2C2 = 31,\n\tGATE_I2C3 = 32,\n\tGATE_I2C4 = 33,\n\tGATE_I2C5 = 34,\n\tGATE_I2C6 = 35,\n\tGATE_I2C7 = 36,\n\tGATE_I2C8 = 37,\n\tGATE_I3C1 = 38,\n\tGATE_I3C2 = 39,\n\tGATE_I3C3 = 40,\n\tGATE_I3C4 = 41,\n\tGATE_IS2M = 42,\n\tGATE_IWDG1 = 43,\n\tGATE_IWDG2 = 44,\n\tGATE_IWDG3 = 45,\n\tGATE_IWDG4 = 46,\n\tGATE_IWDG5 = 47,\n\tGATE_LPTIM1 = 48,\n\tGATE_LPTIM2 = 49,\n\tGATE_LPTIM3 = 50,\n\tGATE_LPTIM4 = 51,\n\tGATE_LPTIM5 = 52,\n\tGATE_LPUART1 = 53,\n\tGATE_LTDC = 54,\n\tGATE_LVDS = 55,\n\tGATE_MCO1 = 56,\n\tGATE_MCO2 = 57,\n\tGATE_MDF1 = 58,\n\tGATE_OSPIIOM = 59,\n\tGATE_PCIE = 60,\n\tGATE_PKA = 61,\n\tGATE_RNG = 62,\n\tGATE_SAES = 63,\n\tGATE_SAI1 = 64,\n\tGATE_SAI2 = 65,\n\tGATE_SAI3 = 66,\n\tGATE_SAI4 = 67,\n\tGATE_SDMMC1 = 68,\n\tGATE_SDMMC2 = 69,\n\tGATE_SDMMC3 = 70,\n\tGATE_SERC = 71,\n\tGATE_SPDIFRX = 72,\n\tGATE_SPI1 = 73,\n\tGATE_SPI2 = 74,\n\tGATE_SPI3 = 75,\n\tGATE_SPI4 = 76,\n\tGATE_SPI5 = 77,\n\tGATE_SPI6 = 78,\n\tGATE_SPI7 = 79,\n\tGATE_SPI8 = 80,\n\tGATE_TIM1 = 81,\n\tGATE_TIM10 = 82,\n\tGATE_TIM11 = 83,\n\tGATE_TIM12 = 84,\n\tGATE_TIM13 = 85,\n\tGATE_TIM14 = 86,\n\tGATE_TIM15 = 87,\n\tGATE_TIM16 = 88,\n\tGATE_TIM17 = 89,\n\tGATE_TIM2 = 90,\n\tGATE_TIM20 = 91,\n\tGATE_TIM3 = 92,\n\tGATE_TIM4 = 93,\n\tGATE_TIM5 = 94,\n\tGATE_TIM6 = 95,\n\tGATE_TIM7 = 96,\n\tGATE_TIM8 = 97,\n\tGATE_UART4 = 98,\n\tGATE_UART5 = 99,\n\tGATE_UART7 = 100,\n\tGATE_UART8 = 101,\n\tGATE_UART9 = 102,\n\tGATE_USART1 = 103,\n\tGATE_USART2 = 104,\n\tGATE_USART3 = 105,\n\tGATE_USART6 = 106,\n\tGATE_USBH = 107,\n\tGATE_USB2PHY1 = 108,\n\tGATE_USB2PHY2 = 109,\n\tGATE_USB3DR = 110,\n\tGATE_USB3PCIEPHY = 111,\n\tGATE_USBTC = 112,\n\tGATE_VDEC = 113,\n\tGATE_VENC = 114,\n\tGATE_VREF = 115,\n\tGATE_WWDG1 = 116,\n\tGATE_WWDG2 = 117,\n\tGATE_NB = 118,\n};\n\nenum enum_gate_cfg___2 {\n\tGATE_ADC1 = 0,\n\tGATE_ADC2 = 1,\n\tGATE_CRC___2 = 2,\n\tGATE_CRYP1___2 = 3,\n\tGATE_CRYP2___2 = 4,\n\tGATE_CSI___2 = 5,\n\tGATE_DCMIPP___2 = 6,\n\tGATE_DCMIPSSI = 7,\n\tGATE_DDRPERFM = 8,\n\tGATE_DTS___2 = 9,\n\tGATE_ETH1___2 = 10,\n\tGATE_ETH1MAC___2 = 11,\n\tGATE_ETH1RX___2 = 12,\n\tGATE_ETH1STP___2 = 13,\n\tGATE_ETH1TX___2 = 14,\n\tGATE_ETH2___2 = 15,\n\tGATE_ETH2MAC___2 = 16,\n\tGATE_ETH2RX___2 = 17,\n\tGATE_ETH2STP___2 = 18,\n\tGATE_ETH2TX___2 = 19,\n\tGATE_FDCAN___2 = 20,\n\tGATE_HASH1 = 21,\n\tGATE_HASH2 = 22,\n\tGATE_HDP___2 = 23,\n\tGATE_I2C1___2 = 24,\n\tGATE_I2C2___2 = 25,\n\tGATE_I2C3___2 = 26,\n\tGATE_I3C1___2 = 27,\n\tGATE_I3C2___2 = 28,\n\tGATE_I3C3___2 = 29,\n\tGATE_IWDG1___2 = 30,\n\tGATE_IWDG2___2 = 31,\n\tGATE_IWDG3___2 = 32,\n\tGATE_IWDG4___2 = 33,\n\tGATE_LPTIM1___2 = 34,\n\tGATE_LPTIM2___2 = 35,\n\tGATE_LPTIM3___2 = 36,\n\tGATE_LPTIM4___2 = 37,\n\tGATE_LPTIM5___2 = 38,\n\tGATE_LPUART1___2 = 39,\n\tGATE_LTDC___2 = 40,\n\tGATE_MCO1___2 = 41,\n\tGATE_MCO2___2 = 42,\n\tGATE_MDF1___2 = 43,\n\tGATE_OTG = 44,\n\tGATE_PKA___2 = 45,\n\tGATE_RNG1 = 46,\n\tGATE_RNG2 = 47,\n\tGATE_SAES___2 = 48,\n\tGATE_SAI1___2 = 49,\n\tGATE_SAI2___2 = 50,\n\tGATE_SAI3___2 = 51,\n\tGATE_SAI4___2 = 52,\n\tGATE_SDMMC1___2 = 53,\n\tGATE_SDMMC2___2 = 54,\n\tGATE_SDMMC3___2 = 55,\n\tGATE_SERC___2 = 56,\n\tGATE_SPDIFRX___2 = 57,\n\tGATE_SPI1___2 = 58,\n\tGATE_SPI2___2 = 59,\n\tGATE_SPI3___2 = 60,\n\tGATE_SPI4___2 = 61,\n\tGATE_SPI5___2 = 62,\n\tGATE_SPI6___2 = 63,\n\tGATE_TIM1___2 = 64,\n\tGATE_TIM10___2 = 65,\n\tGATE_TIM11___2 = 66,\n\tGATE_TIM12___2 = 67,\n\tGATE_TIM13___2 = 68,\n\tGATE_TIM14___2 = 69,\n\tGATE_TIM15___2 = 70,\n\tGATE_TIM16___2 = 71,\n\tGATE_TIM17___2 = 72,\n\tGATE_TIM2___2 = 73,\n\tGATE_TIM3___2 = 74,\n\tGATE_TIM4___2 = 75,\n\tGATE_TIM5___2 = 76,\n\tGATE_TIM6___2 = 77,\n\tGATE_TIM7___2 = 78,\n\tGATE_TIM8___2 = 79,\n\tGATE_UART4___2 = 80,\n\tGATE_UART5___2 = 81,\n\tGATE_UART7___2 = 82,\n\tGATE_USART1___2 = 83,\n\tGATE_USART2___2 = 84,\n\tGATE_USART3___2 = 85,\n\tGATE_USART6___2 = 86,\n\tGATE_USB2PHY1___2 = 87,\n\tGATE_USB2PHY2___2 = 88,\n\tGATE_USBH___2 = 89,\n\tGATE_VREF___2 = 90,\n\tGATE_WWDG1___2 = 91,\n\tGATE_NB___2 = 92,\n};\n\nenum enum_mux_cfg {\n\tMUX_ADC1 = 0,\n\tMUX_ADC2 = 1,\n\tMUX_DTS = 2,\n\tMUX_MCO1 = 3,\n\tMUX_MCO2 = 4,\n\tMUX_USB2PHY1 = 5,\n\tMUX_USB2PHY2 = 6,\n\tMUX_NB = 7,\n};\n\nenum enum_mux_cfg___2 {\n\tMUX_ADC12 = 0,\n\tMUX_ADC3 = 1,\n\tMUX_DSIBLANE = 2,\n\tMUX_DSIPHY = 3,\n\tMUX_DTS___2 = 4,\n\tMUX_LVDSPHY = 5,\n\tMUX_MCO1___2 = 6,\n\tMUX_MCO2___2 = 7,\n\tMUX_USB2PHY1___2 = 8,\n\tMUX_USB2PHY2___2 = 9,\n\tMUX_USB3PCIEPHY = 10,\n\tMUX_NB___2 = 11,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum err_code {\n\tHIDMA_EVRE_STATUS_COMPLETE = 1,\n\tHIDMA_EVRE_STATUS_ERROR = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ether_type_algorithm {\n\tETYPE_ALG_NONE = 0,\n\tETYPE_ALG_SKIP = 1,\n\tETYPE_ALG_ENDPARSE = 2,\n\tETYPE_ALG_VLAN = 3,\n\tETYPE_ALG_VLAN_STRIP = 4,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n\tETT_EVENT_EPROBE = 64,\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_FROZEN = 8,\n\tEVENT_CPU = 16,\n\tEVENT_CGROUP = 32,\n\tEVENT_GUEST = 64,\n\tEVENT_FLAGS = 96,\n\tEVENT_ALL = 3,\n\tEVENT_TIME_FROZEN = 12,\n};\n\nenum ex_phy_state {\n\tPHY_EMPTY = 0,\n\tPHY_VACANT = 1,\n\tPHY_NOT_PRESENT = 2,\n\tPHY_DEVICE_DISCOVERED = 3,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum exception_type {\n\texcept_type_sync = 0,\n\texcept_type_irq = 128,\n\texcept_type_fiq = 256,\n\texcept_type_serror = 384,\n};\n\nenum exec_status {\n\tSAS_SAM_STAT_GOOD = 0,\n\tSAS_SAM_STAT_BUSY = 8,\n\tSAS_SAM_STAT_TASK_ABORTED = 64,\n\tSAS_SAM_STAT_CHECK_CONDITION = 2,\n\tSAS_DEV_NO_RESPONSE = 128,\n\tSAS_DATA_UNDERRUN = 129,\n\tSAS_DATA_OVERRUN = 130,\n\tSAS_INTERRUPTED = 131,\n\tSAS_QUEUE_FULL = 132,\n\tSAS_DEVICE_UNKNOWN = 133,\n\tSAS_OPEN_REJECT = 134,\n\tSAS_OPEN_TO = 135,\n\tSAS_PROTO_RESPONSE = 136,\n\tSAS_PHY_DOWN = 137,\n\tSAS_NAK_R_ERR = 138,\n\tSAS_PENDING = 139,\n\tSAS_ABORTED_TASK = 140,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum ext4_journal_trigger_type {\n\tEXT4_JTR_ORPHAN_FILE = 0,\n\tEXT4_JTR_NONE = 1,\n};\n\nenum ext4_li_mode {\n\tEXT4_LI_MODE_PREFETCH_BBITMAP = 0,\n\tEXT4_LI_MODE_ITABLE = 1,\n};\n\nenum exynos_cpuclk_layout {\n\tCPUCLK_LAYOUT_E4210 = 0,\n\tCPUCLK_LAYOUT_E5433 = 1,\n\tCPUCLK_LAYOUT_E850_CL0 = 2,\n\tCPUCLK_LAYOUT_E850_CL1 = 3,\n};\n\nenum exynos_mipi_phy_id {\n\tEXYNOS_MIPI_PHY_ID_NONE = -1,\n\tEXYNOS_MIPI_PHY_ID_CSIS0 = 0,\n\tEXYNOS_MIPI_PHY_ID_DSIM0 = 1,\n\tEXYNOS_MIPI_PHY_ID_CSIS1 = 2,\n\tEXYNOS_MIPI_PHY_ID_DSIM1 = 3,\n\tEXYNOS_MIPI_PHY_ID_CSIS2 = 4,\n\tEXYNOS_MIPI_PHYS_NUM = 5,\n};\n\nenum exynos_mipi_phy_regmap_id {\n\tEXYNOS_MIPI_REGMAP_PMU = 0,\n\tEXYNOS_MIPI_REGMAP_DISP = 1,\n\tEXYNOS_MIPI_REGMAP_CAM0 = 2,\n\tEXYNOS_MIPI_REGMAP_CAM1 = 3,\n\tEXYNOS_MIPI_REGMAPS_NUM = 4,\n};\n\nenum exynos_usi_ver {\n\tUSI_VER1 = 0,\n\tUSI_VER2 = 1,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum fan53555_vendor {\n\tFAN53526_VENDOR_FAIRCHILD = 0,\n\tFAN53555_VENDOR_FAIRCHILD = 1,\n\tFAN53555_VENDOR_ROCKCHIP = 2,\n\tRK8602_VENDOR_ROCKCHIP = 3,\n\tFAN53555_VENDOR_SILERGY = 4,\n\tFAN53526_VENDOR_TCS = 5,\n};\n\nenum fanotify_event_type {\n\tFANOTIFY_EVENT_TYPE_FID = 0,\n\tFANOTIFY_EVENT_TYPE_FID_NAME = 1,\n\tFANOTIFY_EVENT_TYPE_PATH = 2,\n\tFANOTIFY_EVENT_TYPE_PATH_PERM = 3,\n\tFANOTIFY_EVENT_TYPE_OVERFLOW = 4,\n\tFANOTIFY_EVENT_TYPE_FS_ERROR = 5,\n\tFANOTIFY_EVENT_TYPE_MNT = 6,\n\t__FANOTIFY_EVENT_TYPE_NUM = 7,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fec_txbuf_type {\n\tFEC_TXBUF_T_SKB = 0,\n\tFEC_TXBUF_T_XDP_NDO = 1,\n\tFEC_TXBUF_T_XDP_TX = 2,\n\tFEC_TXBUF_T_XSK_XMIT = 3,\n\tFEC_TXBUF_T_XSK_TX = 4,\n};\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_EDATA = 10,\n\tFETCH_OP_DEREF = 11,\n\tFETCH_OP_UDEREF = 12,\n\tFETCH_OP_ST_RAW = 13,\n\tFETCH_OP_ST_MEM = 14,\n\tFETCH_OP_ST_UMEM = 15,\n\tFETCH_OP_ST_STRING = 16,\n\tFETCH_OP_ST_USTRING = 17,\n\tFETCH_OP_ST_SYMSTR = 18,\n\tFETCH_OP_ST_EDATA = 19,\n\tFETCH_OP_MOD_BF = 20,\n\tFETCH_OP_LP_ARRAY = 21,\n\tFETCH_OP_TP_ARG = 22,\n\tFETCH_OP_END = 23,\n\tFETCH_NOP_SYMBOL = 24,\n};\n\nenum fg_filter_id {\n\t__NO_FGF__ = 0,\n\tHCRX_FGTnXS = 1,\n\t__NR_FG_FILTER_IDS__ = 2,\n};\n\nenum fgt_group_id {\n\t__NO_FGT_GROUP__ = 0,\n\tHFGRTR_GROUP = 1,\n\tHFGWTR_GROUP = 1,\n\tHDFGRTR_GROUP = 2,\n\tHDFGWTR_GROUP = 2,\n\tHFGITR_GROUP = 3,\n\tHAFGRTR_GROUP = 4,\n\tHFGRTR2_GROUP = 5,\n\tHFGWTR2_GROUP = 5,\n\tHDFGRTR2_GROUP = 6,\n\tHDFGWTR2_GROUP = 6,\n\tHFGITR2_GROUP = 7,\n\t__NR_FGT_GROUP_IDS__ = 8,\n};\n\nenum fh_pll_id {\n\tFH_ARMCA7PLL = 0,\n\tFH_ARMCA15PLL = 1,\n\tFH_MAINPLL = 2,\n\tFH_MPLL = 3,\n\tFH_MSDCPLL = 4,\n\tFH_MMPLL = 5,\n\tFH_VENCPLL = 6,\n\tFH_TVDPLL = 7,\n\tFH_VCODECPLL = 8,\n\tFH_LVDSPLL = 9,\n\tFH_MSDC2PLL = 10,\n\tFH_NR_FH = 11,\n};\n\nenum fh_pll_id___2 {\n\tFH_CA53PLL_LL = 0,\n\tFH_CA53PLL_BL = 1,\n\tFH_MAINPLL___2 = 2,\n\tFH_MPLL___2 = 3,\n\tFH_MSDCPLL___2 = 4,\n\tFH_MMPLL___2 = 5,\n\tFH_VENCPLL___2 = 6,\n\tFH_TVDPLL___2 = 7,\n\tFH_VCODECPLL___2 = 8,\n\tFH_NR_FH___2 = 9,\n};\n\nenum fh_pll_id___3 {\n\tFH_ARMPLL_LL = 0,\n\tFH_ARMPLL_BL = 1,\n\tFH_MEMPLL = 2,\n\tFH_ADSPPLL = 3,\n\tFH_NNAPLL = 4,\n\tFH_CCIPLL = 5,\n\tFH_MFGPLL = 6,\n\tFH_TVDPLL2 = 7,\n\tFH_MPLL___3 = 8,\n\tFH_MMPLL___3 = 9,\n\tFH_MAINPLL___3 = 10,\n\tFH_MSDCPLL___3 = 11,\n\tFH_IMGPLL = 12,\n\tFH_VDECPLL = 13,\n\tFH_TVDPLL1 = 14,\n\tFH_NR_FH___3 = 15,\n};\n\nenum fh_pll_id___4 {\n\tFH_ARMPLL_LL___2 = 0,\n\tFH_ARMPLL_BL0 = 1,\n\tFH_ARMPLL_BL1 = 2,\n\tFH_ARMPLL_BL2 = 3,\n\tFH_ARMPLL_BL3 = 4,\n\tFH_CCIPLL___2 = 5,\n\tFH_MFGPLL___2 = 6,\n\tFH_MEMPLL___2 = 7,\n\tFH_MPLL___4 = 8,\n\tFH_MMPLL___4 = 9,\n\tFH_MAINPLL___4 = 10,\n\tFH_MSDCPLL___4 = 11,\n\tFH_ADSPPLL___2 = 12,\n\tFH_APUPLL = 13,\n\tFH_TVDPLL___3 = 14,\n\tFH_NR_FH___4 = 15,\n};\n\nenum fh_pll_id___5 {\n\tFH_ARMPLL_LL___3 = 0,\n\tFH_ARMPLL_BL___2 = 1,\n\tFH_CCIPLL___3 = 2,\n\tFH_MAINPLL___5 = 3,\n\tFH_MMPLL___5 = 4,\n\tFH_TVDPLL___4 = 5,\n\tFH_RESERVE6 = 6,\n\tFH_ADSPPLL___3 = 7,\n\tFH_MFGPLL___3 = 8,\n\tFH_NNAPLL___2 = 9,\n\tFH_NNA2PLL = 10,\n\tFH_MSDCPLL___5 = 11,\n\tFH_RESERVE12 = 12,\n\tFH_NR_FH___5 = 13,\n};\n\nenum fhctl_variant {\n\tFHCTL_PLLFH_V1 = 0,\n\tFHCTL_PLLFH_V2 = 1,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum fifo_dump_mode_v3_hw {\n\tFIFO_DUMP_FORVER = 1,\n\tFIFO_DUMP_AFTER_TRIGGER = 2,\n\tFIFO_DUMP_UNTILL_TRIGGER = 4,\n};\n\nenum fifo_trigger_mode_v3_hw {\n\tFIFO_TRIGGER_EDGE = 1,\n\tFIFO_TRIGGER_SAME_LEVEL = 2,\n\tFIFO_TRIGGER_DIFF_LEVEL = 4,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum filter_pred_fn {\n\tFILTER_PRED_FN_NOP = 0,\n\tFILTER_PRED_FN_64 = 1,\n\tFILTER_PRED_FN_64_CPUMASK = 2,\n\tFILTER_PRED_FN_S64 = 3,\n\tFILTER_PRED_FN_U64 = 4,\n\tFILTER_PRED_FN_32 = 5,\n\tFILTER_PRED_FN_32_CPUMASK = 6,\n\tFILTER_PRED_FN_S32 = 7,\n\tFILTER_PRED_FN_U32 = 8,\n\tFILTER_PRED_FN_16 = 9,\n\tFILTER_PRED_FN_16_CPUMASK = 10,\n\tFILTER_PRED_FN_S16 = 11,\n\tFILTER_PRED_FN_U16 = 12,\n\tFILTER_PRED_FN_8 = 13,\n\tFILTER_PRED_FN_8_CPUMASK = 14,\n\tFILTER_PRED_FN_S8 = 15,\n\tFILTER_PRED_FN_U8 = 16,\n\tFILTER_PRED_FN_COMM = 17,\n\tFILTER_PRED_FN_STRING = 18,\n\tFILTER_PRED_FN_STRLOC = 19,\n\tFILTER_PRED_FN_STRRELLOC = 20,\n\tFILTER_PRED_FN_PCHAR_USER = 21,\n\tFILTER_PRED_FN_PCHAR = 22,\n\tFILTER_PRED_FN_CPU = 23,\n\tFILTER_PRED_FN_CPU_CPUMASK = 24,\n\tFILTER_PRED_FN_CPUMASK = 25,\n\tFILTER_PRED_FN_CPUMASK_CPU = 26,\n\tFILTER_PRED_FN_FUNCTION = 27,\n\tFILTER_PRED_FN_ = 28,\n\tFILTER_PRED_TEST_VISITED = 29,\n};\n\nenum fiq_hwirq {\n\tAIC_TMR_EL0_PHYS = 0,\n\tAIC_TMR_EL0_VIRT = 1,\n\tAIC_TMR_EL02_PHYS = 2,\n\tAIC_TMR_EL02_VIRT = 3,\n\tAIC_CPU_PMU_Effi = 4,\n\tAIC_CPU_PMU_Perf = 5,\n\tAIC_VGIC_MI = 6,\n\tAIC_NR_FIQ = 7,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum fixed_addresses {\n\tFIX_HOLE = 0,\n\tFIX_FDT_END = 1,\n\tFIX_FDT = 514,\n\tFIX_EARLYCON_MEM_BASE = 515,\n\tFIX_TEXT_POKE0 = 516,\n\tFIX_VNCR_END = 517,\n\tFIX_VNCR = 1029,\n\tFIX_APEI_GHES_IRQ = 1030,\n\tFIX_APEI_GHES_SEA = 1031,\n\tFIX_APEI_GHES_SDEI_NORMAL = 1032,\n\tFIX_APEI_GHES_SDEI_CRITICAL = 1033,\n\tFIX_ENTRY_TRAMP_TEXT4 = 1034,\n\tFIX_ENTRY_TRAMP_TEXT3 = 1035,\n\tFIX_ENTRY_TRAMP_TEXT2 = 1036,\n\tFIX_ENTRY_TRAMP_TEXT1 = 1037,\n\t__end_of_permanent_fixed_addresses = 1038,\n\tFIX_BTMAP_END = 1038,\n\tFIX_BTMAP_BEGIN = 1485,\n\tFIX_PTE = 1486,\n\tFIX_PMD = 1487,\n\tFIX_PUD = 1488,\n\tFIX_P4D = 1489,\n\tFIX_PGD = 1490,\n\t__end_of_fixed_addresses = 1491,\n};\n\nenum flag_idn {\n\tQUERY_FLAG_IDN_FDEVICEINIT = 1,\n\tQUERY_FLAG_IDN_PERMANENT_WPE = 2,\n\tQUERY_FLAG_IDN_PWR_ON_WPE = 3,\n\tQUERY_FLAG_IDN_BKOPS_EN = 4,\n\tQUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 5,\n\tQUERY_FLAG_IDN_PURGE_ENABLE = 6,\n\tQUERY_FLAG_IDN_RESERVED2 = 7,\n\tQUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 8,\n\tQUERY_FLAG_IDN_BUSY_RTC = 9,\n\tQUERY_FLAG_IDN_RESERVED3 = 10,\n\tQUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 11,\n\tQUERY_FLAG_IDN_WB_EN = 14,\n\tQUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 15,\n\tQUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 16,\n\tQUERY_FLAG_IDN_HPB_RESET = 17,\n\tQUERY_FLAG_IDN_HPB_EN = 18,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_cls_command {\n\tFLOW_CLS_REPLACE = 0,\n\tFLOW_CLS_DESTROY = 1,\n\tFLOW_CLS_STATS = 2,\n\tFLOW_CLS_TMPLT_CREATE = 3,\n\tFLOW_CLS_TMPLT_DESTROY = 4,\n};\n\nenum flow_control {\n\tFC_NONE = 0,\n\tFC_TX = 1,\n\tFC_RX = 2,\n\tFC_BOTH = 3,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum fman_dma_aid_mode {\n\tFMAN_DMA_AID_OUT_PORT_ID = 0,\n\tFMAN_DMA_AID_OUT_TNUM = 1,\n};\n\nenum fman_event_modules {\n\tFMAN_MOD_MAC = 0,\n\tFMAN_MOD_FMAN_CTRL = 1,\n\tFMAN_MOD_DUMMY_LAST = 2,\n};\n\nenum fman_exceptions {\n\tFMAN_EX_DMA_BUS_ERROR = 0,\n\tFMAN_EX_DMA_READ_ECC = 1,\n\tFMAN_EX_DMA_SYSTEM_WRITE_ECC = 2,\n\tFMAN_EX_DMA_FM_WRITE_ECC = 3,\n\tFMAN_EX_DMA_SINGLE_PORT_ECC = 4,\n\tFMAN_EX_FPM_STALL_ON_TASKS = 5,\n\tFMAN_EX_FPM_SINGLE_ECC = 6,\n\tFMAN_EX_FPM_DOUBLE_ECC = 7,\n\tFMAN_EX_QMI_SINGLE_ECC = 8,\n\tFMAN_EX_QMI_DOUBLE_ECC = 9,\n\tFMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID = 10,\n\tFMAN_EX_BMI_LIST_RAM_ECC = 11,\n\tFMAN_EX_BMI_STORAGE_PROFILE_ECC = 12,\n\tFMAN_EX_BMI_STATISTICS_RAM_ECC = 13,\n\tFMAN_EX_BMI_DISPATCH_RAM_ECC = 14,\n\tFMAN_EX_IRAM_ECC = 15,\n\tFMAN_EX_MURAM_ECC = 16,\n};\n\nenum fman_inter_module_event {\n\tFMAN_EV_ERR_MAC0 = 0,\n\tFMAN_EV_ERR_MAC1 = 1,\n\tFMAN_EV_ERR_MAC2 = 2,\n\tFMAN_EV_ERR_MAC3 = 3,\n\tFMAN_EV_ERR_MAC4 = 4,\n\tFMAN_EV_ERR_MAC5 = 5,\n\tFMAN_EV_ERR_MAC6 = 6,\n\tFMAN_EV_ERR_MAC7 = 7,\n\tFMAN_EV_ERR_MAC8 = 8,\n\tFMAN_EV_ERR_MAC9 = 9,\n\tFMAN_EV_MAC0 = 10,\n\tFMAN_EV_MAC1 = 11,\n\tFMAN_EV_MAC2 = 12,\n\tFMAN_EV_MAC3 = 13,\n\tFMAN_EV_MAC4 = 14,\n\tFMAN_EV_MAC5 = 15,\n\tFMAN_EV_MAC6 = 16,\n\tFMAN_EV_MAC7 = 17,\n\tFMAN_EV_MAC8 = 18,\n\tFMAN_EV_MAC9 = 19,\n\tFMAN_EV_FMAN_CTRL_0 = 20,\n\tFMAN_EV_FMAN_CTRL_1 = 21,\n\tFMAN_EV_FMAN_CTRL_2 = 22,\n\tFMAN_EV_FMAN_CTRL_3 = 23,\n\tFMAN_EV_CNT = 24,\n};\n\nenum fman_intr_type {\n\tFMAN_INTR_TYPE_ERR = 0,\n\tFMAN_INTR_TYPE_NORMAL = 1,\n};\n\nenum fman_mac_exceptions {\n\tFM_MAC_EX_10G_MDIO_SCAN_EVENT = 0,\n\tFM_MAC_EX_10G_MDIO_CMD_CMPL = 1,\n\tFM_MAC_EX_10G_REM_FAULT = 2,\n\tFM_MAC_EX_10G_LOC_FAULT = 3,\n\tFM_MAC_EX_10G_TX_ECC_ER = 4,\n\tFM_MAC_EX_10G_TX_FIFO_UNFL = 5,\n\tFM_MAC_EX_10G_TX_FIFO_OVFL = 6,\n\tFM_MAC_EX_10G_TX_ER = 7,\n\tFM_MAC_EX_10G_RX_FIFO_OVFL = 8,\n\tFM_MAC_EX_10G_RX_ECC_ER = 9,\n\tFM_MAC_EX_10G_RX_JAB_FRM = 10,\n\tFM_MAC_EX_10G_RX_OVRSZ_FRM = 11,\n\tFM_MAC_EX_10G_RX_RUNT_FRM = 12,\n\tFM_MAC_EX_10G_RX_FRAG_FRM = 13,\n\tFM_MAC_EX_10G_RX_LEN_ER = 14,\n\tFM_MAC_EX_10G_RX_CRC_ER = 15,\n\tFM_MAC_EX_10G_RX_ALIGN_ER = 16,\n\tFM_MAC_EX_1G_BAB_RX = 17,\n\tFM_MAC_EX_1G_RX_CTL = 18,\n\tFM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET = 19,\n\tFM_MAC_EX_1G_BAB_TX = 20,\n\tFM_MAC_EX_1G_TX_CTL = 21,\n\tFM_MAC_EX_1G_TX_ERR = 22,\n\tFM_MAC_EX_1G_LATE_COL = 23,\n\tFM_MAC_EX_1G_COL_RET_LMT = 24,\n\tFM_MAC_EX_1G_TX_FIFO_UNDRN = 25,\n\tFM_MAC_EX_1G_MAG_PCKT = 26,\n\tFM_MAC_EX_1G_MII_MNG_RD_COMPLET = 27,\n\tFM_MAC_EX_1G_MII_MNG_WR_COMPLET = 28,\n\tFM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET = 29,\n\tFM_MAC_EX_1G_DATA_ERR = 30,\n\tFM_MAC_1G_RX_DATA_ERR = 31,\n\tFM_MAC_EX_1G_1588_TS_RX_ERR = 32,\n\tFM_MAC_EX_1G_RX_MIB_CNT_OVFL = 33,\n\tFM_MAC_EX_TS_FIFO_ECC_ERR = 34,\n\tFM_MAC_EX_MAGIC_PACKET_INDICATION = 26,\n};\n\nenum fman_port_color {\n\tFMAN_PORT_COLOR_GREEN = 0,\n\tFMAN_PORT_COLOR_YELLOW = 1,\n\tFMAN_PORT_COLOR_RED = 2,\n\tFMAN_PORT_COLOR_OVERRIDE = 3,\n};\n\nenum fman_port_deq_prefetch {\n\tFMAN_PORT_DEQ_NO_PREFETCH = 0,\n\tFMAN_PORT_DEQ_PART_PREFETCH = 1,\n\tFMAN_PORT_DEQ_FULL_PREFETCH = 2,\n};\n\nenum fman_port_deq_type {\n\tFMAN_PORT_DEQ_BY_PRI = 0,\n\tFMAN_PORT_DEQ_ACTIVE_FQ = 1,\n\tFMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS = 2,\n};\n\nenum fman_port_dma_swap {\n\tFMAN_PORT_DMA_NO_SWAP = 0,\n\tFMAN_PORT_DMA_SWAP_LE = 1,\n\tFMAN_PORT_DMA_SWAP_BE = 2,\n};\n\nenum fman_port_type {\n\tFMAN_PORT_TYPE_TX = 0,\n\tFMAN_PORT_TYPE_RX = 1,\n};\n\nenum fmp_crypto_algo_mode {\n\tFMP_BYPASS_MODE = 0,\n\tFMP_ALGO_MODE_AES_CBC = 1,\n\tFMP_ALGO_MODE_AES_XTS = 2,\n};\n\nenum fmp_crypto_key_length {\n\tFMP_KEYLEN_256BIT = 1,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum forward_type {\n\tFILTER_ACTION_TYPE_PSFP = 1,\n\tFILTER_ACTION_TYPE_ACL = 2,\n\tFILTER_ACTION_TYPE_BOTH = 3,\n};\n\nenum fp_type {\n\tFP_STATE_CURRENT = 0,\n\tFP_STATE_FPSIMD = 1,\n\tFP_STATE_SVE = 2,\n};\n\nenum fpga_mgr_states {\n\tFPGA_MGR_STATE_UNKNOWN = 0,\n\tFPGA_MGR_STATE_POWER_OFF = 1,\n\tFPGA_MGR_STATE_POWER_UP = 2,\n\tFPGA_MGR_STATE_RESET = 3,\n\tFPGA_MGR_STATE_FIRMWARE_REQ = 4,\n\tFPGA_MGR_STATE_FIRMWARE_REQ_ERR = 5,\n\tFPGA_MGR_STATE_PARSE_HEADER = 6,\n\tFPGA_MGR_STATE_PARSE_HEADER_ERR = 7,\n\tFPGA_MGR_STATE_WRITE_INIT = 8,\n\tFPGA_MGR_STATE_WRITE_INIT_ERR = 9,\n\tFPGA_MGR_STATE_WRITE = 10,\n\tFPGA_MGR_STATE_WRITE_ERR = 11,\n\tFPGA_MGR_STATE_WRITE_COMPLETE = 12,\n\tFPGA_MGR_STATE_WRITE_COMPLETE_ERR = 13,\n\tFPGA_MGR_STATE_OPERATING = 14,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nenum freq_policy {\n\tFLOOR = 0,\n\tCEIL = 1,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fscache_cache_state {\n\tFSCACHE_CACHE_IS_NOT_PRESENT = 0,\n\tFSCACHE_CACHE_IS_PREPARING = 1,\n\tFSCACHE_CACHE_IS_ACTIVE = 2,\n\tFSCACHE_CACHE_GOT_IOERROR = 3,\n\tFSCACHE_CACHE_IS_WITHDRAWN = 4,\n};\n\nenum fscache_cookie_state {\n\tFSCACHE_COOKIE_STATE_QUIESCENT = 0,\n\tFSCACHE_COOKIE_STATE_LOOKING_UP = 1,\n\tFSCACHE_COOKIE_STATE_CREATING = 2,\n\tFSCACHE_COOKIE_STATE_ACTIVE = 3,\n\tFSCACHE_COOKIE_STATE_INVALIDATING = 4,\n\tFSCACHE_COOKIE_STATE_FAILED = 5,\n\tFSCACHE_COOKIE_STATE_LRU_DISCARDING = 6,\n\tFSCACHE_COOKIE_STATE_WITHDRAWING = 7,\n\tFSCACHE_COOKIE_STATE_RELINQUISHING = 8,\n\tFSCACHE_COOKIE_STATE_DROPPED = 9,\n} __attribute__((mode(byte)));\n\nenum fscache_want_state {\n\tFSCACHE_WANT_PARAMS = 0,\n\tFSCACHE_WANT_WRITE = 1,\n\tFSCACHE_WANT_READ = 2,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsl_edma_pm_state {\n\tRUNNING = 0,\n\tSUSPENDED = 1,\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftr_type {\n\tFTR_EXACT = 0,\n\tFTR_LOWER_SAFE = 1,\n\tFTR_HIGHER_SAFE = 2,\n\tFTR_HIGHER_OR_ZERO_SAFE = 3,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n\tFW_OPT_PARTIAL = 128,\n};\n\nenum fw_resource_type {\n\tRSC_CARVEOUT = 0,\n\tRSC_DEVMEM = 1,\n\tRSC_TRACE = 2,\n\tRSC_VDEV = 3,\n\tRSC_LAST = 4,\n\tRSC_VENDOR_START = 128,\n\tRSC_VENDOR_END = 512,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nenum fw_upload_err {\n\tFW_UPLOAD_ERR_NONE = 0,\n\tFW_UPLOAD_ERR_HW_ERROR = 1,\n\tFW_UPLOAD_ERR_TIMEOUT = 2,\n\tFW_UPLOAD_ERR_CANCELED = 3,\n\tFW_UPLOAD_ERR_BUSY = 4,\n\tFW_UPLOAD_ERR_INVALID_SIZE = 5,\n\tFW_UPLOAD_ERR_RW_ERROR = 6,\n\tFW_UPLOAD_ERR_WEAROUT = 7,\n\tFW_UPLOAD_ERR_FW_INVALID = 8,\n\tFW_UPLOAD_ERR_MAX = 9,\n};\n\nenum fw_upload_prog {\n\tFW_UPLOAD_PROG_IDLE = 0,\n\tFW_UPLOAD_PROG_RECEIVING = 1,\n\tFW_UPLOAD_PROG_PREPARING = 2,\n\tFW_UPLOAD_PROG_TRANSFERRING = 3,\n\tFW_UPLOAD_PROG_PROGRAMMING = 4,\n\tFW_UPLOAD_PROG_MAX = 5,\n};\n\nenum fwh_lock_state {\n\tFWH_UNLOCKED = 0,\n\tFWH_DENY_WRITE = 1,\n\tFWH_IMMUTABLE = 2,\n\tFWH_DENY_READ = 4,\n};\n\nenum gddrnf4_status {\n\tGDD4_OK = 0,\n\tGDD4_UNAVAIL = 1,\n};\n\nenum gdsc_status {\n\tGDSC_OFF = 0,\n\tGDSC_ON = 1,\n};\n\nenum geni_icc_path_index {\n\tGENI_TO_CORE = 0,\n\tCPU_TO_GENI = 1,\n\tGENI_TO_DDR = 2,\n};\n\nenum geni_se_protocol_type {\n\tGENI_SE_NONE = 0,\n\tGENI_SE_SPI = 1,\n\tGENI_SE_UART = 2,\n\tGENI_SE_I2C = 3,\n\tGENI_SE_I3C = 4,\n\tGENI_SE_SPI_SLAVE = 5,\n\tGENI_SE_INVALID_PROTO = 255,\n};\n\nenum geni_se_xfer_mode {\n\tGENI_SE_INVALID = 0,\n\tGENI_SE_FIFO = 1,\n\tGENI_SE_DMA = 2,\n\tGENI_GPI_DMA = 3,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum genpd_notication {\n\tGENPD_NOTIFY_PRE_OFF = 0,\n\tGENPD_NOTIFY_OFF = 1,\n\tGENPD_NOTIFY_PRE_ON = 2,\n\tGENPD_NOTIFY_ON = 3,\n};\n\nenum genpd_sync_state {\n\tGENPD_SYNC_STATE_OFF = 0,\n\tGENPD_SYNC_STATE_SIMPLE = 1,\n\tGENPD_SYNC_STATE_ONECELL = 2,\n};\n\nenum geometry_desc_param {\n\tGEOMETRY_DESC_PARAM_LEN = 0,\n\tGEOMETRY_DESC_PARAM_TYPE = 1,\n\tGEOMETRY_DESC_PARAM_DEV_CAP = 4,\n\tGEOMETRY_DESC_PARAM_MAX_NUM_LUN = 12,\n\tGEOMETRY_DESC_PARAM_SEG_SIZE = 13,\n\tGEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 17,\n\tGEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 18,\n\tGEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 19,\n\tGEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 20,\n\tGEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 21,\n\tGEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 22,\n\tGEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 23,\n\tGEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 24,\n\tGEOMETRY_DESC_PARAM_DATA_ORDER = 25,\n\tGEOMETRY_DESC_PARAM_MAX_NUM_CTX = 26,\n\tGEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 27,\n\tGEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 28,\n\tGEOMETRY_DESC_PARAM_SEC_RM_TYPES = 29,\n\tGEOMETRY_DESC_PARAM_MEM_TYPES = 30,\n\tGEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 32,\n\tGEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 36,\n\tGEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 38,\n\tGEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 42,\n\tGEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 44,\n\tGEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 48,\n\tGEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 50,\n\tGEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 54,\n\tGEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 56,\n\tGEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 60,\n\tGEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 62,\n\tGEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 66,\n\tGEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 68,\n\tGEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 72,\n\tGEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 73,\n\tGEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 74,\n\tGEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 75,\n\tGEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 79,\n\tGEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 83,\n\tGEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 84,\n\tGEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 85,\n\tGEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 86,\n};\n\nenum gic_intid_range {\n\tSGI_RANGE = 0,\n\tPPI_RANGE = 1,\n\tSPI_RANGE = 2,\n\tEPPI_RANGE = 3,\n\tESPI_RANGE = 4,\n\tLPI_RANGE = 5,\n\t__INVALID_RANGE__ = 6,\n};\n\nenum gic_type {\n\tGIC_V2 = 0,\n\tGIC_V3 = 1,\n\tGIC_V5 = 2,\n};\n\nenum gio_reg_index {\n\tGIO_REG_ODEN = 0,\n\tGIO_REG_DATA = 1,\n\tGIO_REG_IODIR = 2,\n\tGIO_REG_EC = 3,\n\tGIO_REG_EI = 4,\n\tGIO_REG_MASK = 5,\n\tGIO_REG_LEVEL = 6,\n\tGIO_REG_STAT = 7,\n\tNUMBER_OF_GIO_REGISTERS = 8,\n};\n\nenum gpd_status {\n\tGENPD_STATE_ON = 0,\n\tGENPD_STATE_OFF = 1,\n};\n\nenum gpio_lookup_flags {\n\tGPIO_ACTIVE_HIGH = 0,\n\tGPIO_ACTIVE_LOW = 1,\n\tGPIO_OPEN_DRAIN = 2,\n\tGPIO_OPEN_SOURCE = 4,\n\tGPIO_PERSISTENT = 0,\n\tGPIO_TRANSITORY = 8,\n\tGPIO_PULL_UP = 16,\n\tGPIO_PULL_DOWN = 32,\n\tGPIO_PULL_DISABLE = 64,\n\tGPIO_LOOKUP_FLAGS_DEFAULT = 0,\n};\n\nenum gpio_v2_line_attr_id {\n\tGPIO_V2_LINE_ATTR_ID_FLAGS = 1,\n\tGPIO_V2_LINE_ATTR_ID_OUTPUT_VALUES = 2,\n\tGPIO_V2_LINE_ATTR_ID_DEBOUNCE = 3,\n};\n\nenum gpio_v2_line_changed_type {\n\tGPIO_V2_LINE_CHANGED_REQUESTED = 1,\n\tGPIO_V2_LINE_CHANGED_RELEASED = 2,\n\tGPIO_V2_LINE_CHANGED_CONFIG = 3,\n};\n\nenum gpio_v2_line_event_id {\n\tGPIO_V2_LINE_EVENT_RISING_EDGE = 1,\n\tGPIO_V2_LINE_EVENT_FALLING_EDGE = 2,\n};\n\nenum gpio_v2_line_flag {\n\tGPIO_V2_LINE_FLAG_USED = 1,\n\tGPIO_V2_LINE_FLAG_ACTIVE_LOW = 2,\n\tGPIO_V2_LINE_FLAG_INPUT = 4,\n\tGPIO_V2_LINE_FLAG_OUTPUT = 8,\n\tGPIO_V2_LINE_FLAG_EDGE_RISING = 16,\n\tGPIO_V2_LINE_FLAG_EDGE_FALLING = 32,\n\tGPIO_V2_LINE_FLAG_OPEN_DRAIN = 64,\n\tGPIO_V2_LINE_FLAG_OPEN_SOURCE = 128,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_UP = 256,\n\tGPIO_V2_LINE_FLAG_BIAS_PULL_DOWN = 512,\n\tGPIO_V2_LINE_FLAG_BIAS_DISABLED = 1024,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME = 2048,\n\tGPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE = 4096,\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum hal_dsaf_mode {\n\tHRD_DSAF_NO_DSAF_MODE = 0,\n\tHRD_DSAF_MODE = 1,\n};\n\nenum hal_dsaf_tc_mode {\n\tHRD_DSAF_4TC_MODE = 0,\n\tHRD_DSAF_8TC_MODE = 1,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum handshake_auth {\n\tHANDSHAKE_AUTH_UNSPEC = 0,\n\tHANDSHAKE_AUTH_UNAUTH = 1,\n\tHANDSHAKE_AUTH_PSK = 2,\n\tHANDSHAKE_AUTH_X509 = 3,\n};\n\nenum handshake_handler_class {\n\tHANDSHAKE_HANDLER_CLASS_NONE = 0,\n\tHANDSHAKE_HANDLER_CLASS_TLSHD = 1,\n\tHANDSHAKE_HANDLER_CLASS_MAX = 2,\n};\n\nenum handshake_msg_type {\n\tHANDSHAKE_MSG_TYPE_UNSPEC = 0,\n\tHANDSHAKE_MSG_TYPE_CLIENTHELLO = 1,\n\tHANDSHAKE_MSG_TYPE_SERVERHELLO = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hclge_comm_cmd_return_status {\n\tHCLGE_COMM_CMD_EXEC_SUCCESS = 0,\n\tHCLGE_COMM_CMD_NO_AUTH = 1,\n\tHCLGE_COMM_CMD_NOT_SUPPORTED = 2,\n\tHCLGE_COMM_CMD_QUEUE_FULL = 3,\n\tHCLGE_COMM_CMD_NEXT_ERR = 4,\n\tHCLGE_COMM_CMD_UNEXE_ERR = 5,\n\tHCLGE_COMM_CMD_PARA_ERR = 6,\n\tHCLGE_COMM_CMD_RESULT_ERR = 7,\n\tHCLGE_COMM_CMD_TIMEOUT = 8,\n\tHCLGE_COMM_CMD_HILINK_ERR = 9,\n\tHCLGE_COMM_CMD_QUEUE_ILLEGAL = 10,\n\tHCLGE_COMM_CMD_INVALID = 11,\n};\n\nenum hclge_comm_cmd_state {\n\tHCLGE_COMM_STATE_CMD_DISABLE = 0,\n};\n\nenum hclge_comm_cmd_status {\n\tHCLGE_COMM_STATUS_SUCCESS = 0,\n\tHCLGE_COMM_ERR_CSQ_FULL = -1,\n\tHCLGE_COMM_ERR_CSQ_TIMEOUT = -2,\n\tHCLGE_COMM_ERR_CSQ_ERROR = -3,\n};\n\nenum hclge_err_type_list {\n\tNONE_ERROR = 0,\n\tFIFO_ERROR = 1,\n\tMEMORY_ERROR = 2,\n\tPOISON_ERROR = 3,\n\tMSIX_ECC_ERROR = 4,\n\tTQP_INT_ECC_ERROR = 5,\n\tPF_ABNORMAL_INT_ERROR = 6,\n\tMPF_ABNORMAL_INT_ERROR = 7,\n\tCOMMON_ERROR = 8,\n\tPORT_ERROR = 9,\n\tETS_ERROR = 10,\n\tNCSI_ERROR = 11,\n\tGLB_ERROR = 12,\n\tLINK_ERROR = 13,\n\tPTP_ERROR = 14,\n\tROCEE_NORMAL_ERR = 40,\n\tROCEE_OVF_ERR = 41,\n\tROCEE_BUS_ERR = 42,\n};\n\nenum hclge_evt_cause {\n\tHCLGE_VECTOR0_EVENT_RST = 0,\n\tHCLGE_VECTOR0_EVENT_MBX = 1,\n\tHCLGE_VECTOR0_EVENT_ERR = 2,\n\tHCLGE_VECTOR0_EVENT_PTP = 3,\n\tHCLGE_VECTOR0_EVENT_OTHER = 4,\n};\n\nenum hclge_fc_mode {\n\tHCLGE_FC_NONE = 0,\n\tHCLGE_FC_RX_PAUSE = 1,\n\tHCLGE_FC_TX_PAUSE = 2,\n\tHCLGE_FC_FULL = 3,\n\tHCLGE_FC_PFC = 4,\n\tHCLGE_FC_DEFAULT = 5,\n};\n\nenum hclge_hilink_version {\n\tHCLGE_HILINK_H32 = 0,\n\tHCLGE_HILINK_H60 = 1,\n};\n\nenum hclge_led_status {\n\tHCLGE_LED_OFF = 0,\n\tHCLGE_LED_ON = 1,\n\tHCLGE_LED_NO_CHANGE = 255,\n};\n\nenum hclge_link_fail_code {\n\tHCLGE_LF_NORMAL = 0,\n\tHCLGE_LF_REF_CLOCK_LOST = 1,\n\tHCLGE_LF_XSFP_TX_DISABLE = 2,\n\tHCLGE_LF_XSFP_ABSENT = 3,\n};\n\nenum hclge_mac_vlan_add_resp_code {\n\tHCLGE_ADD_UC_OVERFLOW = 2,\n\tHCLGE_ADD_MC_OVERFLOW = 3,\n};\n\nenum hclge_mac_vlan_cfg_sel {\n\tHCLGE_MAC_VLAN_NIC_SEL = 0,\n\tHCLGE_MAC_VLAN_ROCE_SEL = 1,\n};\n\nenum hclge_mac_vlan_tbl_opcode {\n\tHCLGE_MAC_VLAN_ADD = 0,\n\tHCLGE_MAC_VLAN_UPDATE = 1,\n\tHCLGE_MAC_VLAN_REMOVE = 2,\n\tHCLGE_MAC_VLAN_LKUP = 3,\n};\n\nenum hclge_mbx_mac_vlan_subcode {\n\tHCLGE_MBX_MAC_VLAN_UC_MODIFY = 0,\n\tHCLGE_MBX_MAC_VLAN_UC_ADD = 1,\n\tHCLGE_MBX_MAC_VLAN_UC_REMOVE = 2,\n\tHCLGE_MBX_MAC_VLAN_MC_MODIFY = 3,\n\tHCLGE_MBX_MAC_VLAN_MC_ADD = 4,\n\tHCLGE_MBX_MAC_VLAN_MC_REMOVE = 5,\n};\n\nenum hclge_mbx_tbl_cfg_subcode {\n\tHCLGE_MBX_VPORT_LIST_CLEAR = 0,\n};\n\nenum hclge_mbx_vlan_cfg_subcode {\n\tHCLGE_MBX_VLAN_FILTER = 0,\n\tHCLGE_MBX_VLAN_TX_OFF_CFG = 1,\n\tHCLGE_MBX_VLAN_RX_OFF_CFG = 2,\n\tHCLGE_MBX_PORT_BASE_VLAN_CFG = 3,\n\tHCLGE_MBX_GET_PORT_BASE_VLAN_STATE = 4,\n\tHCLGE_MBX_ENABLE_VLAN_FILTER = 5,\n};\n\nenum hclge_mdio_c22_op_seq {\n\tHCLGE_MDIO_C22_WRITE = 1,\n\tHCLGE_MDIO_C22_READ = 2,\n};\n\nenum hclge_mod_name_list {\n\tMODULE_NONE = 0,\n\tMODULE_BIOS_COMMON = 1,\n\tMODULE_GE = 2,\n\tMODULE_IGU_EGU = 3,\n\tMODULE_LGE = 4,\n\tMODULE_NCSI = 5,\n\tMODULE_PPP = 6,\n\tMODULE_QCN = 7,\n\tMODULE_RCB_RX = 8,\n\tMODULE_RTC = 9,\n\tMODULE_SSU = 10,\n\tMODULE_TM = 11,\n\tMODULE_RCB_TX = 12,\n\tMODULE_TXDMA = 13,\n\tMODULE_MASTER = 14,\n\tMODULE_HIMAC = 15,\n\tMODULE_ROCEE_TOP = 40,\n\tMODULE_ROCEE_TIMER = 41,\n\tMODULE_ROCEE_MDB = 42,\n\tMODULE_ROCEE_TSP = 43,\n\tMODULE_ROCEE_TRP = 44,\n\tMODULE_ROCEE_SCC = 45,\n\tMODULE_ROCEE_CAEP = 46,\n\tMODULE_ROCEE_GEN_AC = 47,\n\tMODULE_ROCEE_QMM = 48,\n\tMODULE_ROCEE_LSAN = 49,\n};\n\nenum hclge_opcode_type {\n\tHCLGE_OPC_QUERY_FW_VER = 1,\n\tHCLGE_OPC_CFG_RST_TRIGGER = 32,\n\tHCLGE_OPC_GBL_RST_STATUS = 33,\n\tHCLGE_OPC_QUERY_FUNC_STATUS = 34,\n\tHCLGE_OPC_QUERY_PF_RSRC = 35,\n\tHCLGE_OPC_QUERY_VF_RSRC = 36,\n\tHCLGE_OPC_GET_CFG_PARAM = 37,\n\tHCLGE_OPC_PF_RST_DONE = 38,\n\tHCLGE_OPC_QUERY_VF_RST_RDY = 39,\n\tHCLGE_OPC_STATS_64_BIT = 48,\n\tHCLGE_OPC_STATS_32_BIT = 49,\n\tHCLGE_OPC_STATS_MAC = 50,\n\tHCLGE_OPC_QUERY_MAC_REG_NUM = 51,\n\tHCLGE_OPC_STATS_MAC_ALL = 52,\n\tHCLGE_OPC_QUERY_REG_NUM = 64,\n\tHCLGE_OPC_QUERY_32_BIT_REG = 65,\n\tHCLGE_OPC_QUERY_64_BIT_REG = 66,\n\tHCLGE_OPC_DFX_BD_NUM = 67,\n\tHCLGE_OPC_DFX_BIOS_COMMON_REG = 68,\n\tHCLGE_OPC_DFX_SSU_REG_0 = 69,\n\tHCLGE_OPC_DFX_SSU_REG_1 = 70,\n\tHCLGE_OPC_DFX_IGU_EGU_REG = 71,\n\tHCLGE_OPC_DFX_RPU_REG_0 = 72,\n\tHCLGE_OPC_DFX_RPU_REG_1 = 73,\n\tHCLGE_OPC_DFX_NCSI_REG = 74,\n\tHCLGE_OPC_DFX_RTC_REG = 75,\n\tHCLGE_OPC_DFX_PPP_REG = 76,\n\tHCLGE_OPC_DFX_RCB_REG = 77,\n\tHCLGE_OPC_DFX_TQP_REG = 78,\n\tHCLGE_OPC_DFX_SSU_REG_2 = 79,\n\tHCLGE_OPC_DFX_GEN_REG = 28728,\n\tHCLGE_OPC_QUERY_DEV_SPECS = 80,\n\tHCLGE_OPC_GET_QUEUE_ERR_VF = 103,\n\tHCLGE_OPC_CONFIG_MAC_MODE = 769,\n\tHCLGE_OPC_CONFIG_AN_MODE = 772,\n\tHCLGE_OPC_QUERY_LINK_STATUS = 775,\n\tHCLGE_OPC_CONFIG_MAX_FRM_SIZE = 776,\n\tHCLGE_OPC_CONFIG_SPEED_DUP = 777,\n\tHCLGE_OPC_QUERY_MAC_TNL_INT = 784,\n\tHCLGE_OPC_MAC_TNL_INT_EN = 785,\n\tHCLGE_OPC_CLEAR_MAC_TNL_INT = 786,\n\tHCLGE_OPC_COMMON_LOOPBACK = 789,\n\tHCLGE_OPC_QUERY_FEC_STATS = 790,\n\tHCLGE_OPC_CONFIG_FEC_MODE = 794,\n\tHCLGE_OPC_QUERY_ROH_TYPE_INFO = 905,\n\tHCLGE_OPC_PTP_INT_EN = 1281,\n\tHCLGE_OPC_PTP_MODE_CFG = 1287,\n\tHCLGE_OPC_CFG_MAC_PAUSE_EN = 1793,\n\tHCLGE_OPC_CFG_PFC_PAUSE_EN = 1794,\n\tHCLGE_OPC_CFG_MAC_PARA = 1795,\n\tHCLGE_OPC_CFG_PFC_PARA = 1796,\n\tHCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 1797,\n\tHCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 1798,\n\tHCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 1799,\n\tHCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 1800,\n\tHCLGE_OPC_PRI_TO_TC_MAPPING = 1801,\n\tHCLGE_OPC_QOS_MAP = 1802,\n\tHCLGE_OPC_TM_PG_TO_PRI_LINK = 2052,\n\tHCLGE_OPC_TM_QS_TO_PRI_LINK = 2053,\n\tHCLGE_OPC_TM_NQ_TO_QS_LINK = 2054,\n\tHCLGE_OPC_TM_RQ_TO_QS_LINK = 2055,\n\tHCLGE_OPC_TM_PORT_WEIGHT = 2056,\n\tHCLGE_OPC_TM_PG_WEIGHT = 2057,\n\tHCLGE_OPC_TM_QS_WEIGHT = 2058,\n\tHCLGE_OPC_TM_PRI_WEIGHT = 2059,\n\tHCLGE_OPC_TM_PRI_C_SHAPPING = 2060,\n\tHCLGE_OPC_TM_PRI_P_SHAPPING = 2061,\n\tHCLGE_OPC_TM_PG_C_SHAPPING = 2062,\n\tHCLGE_OPC_TM_PG_P_SHAPPING = 2063,\n\tHCLGE_OPC_TM_PORT_SHAPPING = 2064,\n\tHCLGE_OPC_TM_PG_SCH_MODE_CFG = 2066,\n\tHCLGE_OPC_TM_PRI_SCH_MODE_CFG = 2067,\n\tHCLGE_OPC_TM_QS_SCH_MODE_CFG = 2068,\n\tHCLGE_OPC_TM_BP_TO_QSET_MAPPING = 2069,\n\tHCLGE_OPC_TM_NODES = 2070,\n\tHCLGE_OPC_ETS_TC_WEIGHT = 2115,\n\tHCLGE_OPC_QSET_DFX_STS = 2116,\n\tHCLGE_OPC_PRI_DFX_STS = 2117,\n\tHCLGE_OPC_PG_DFX_STS = 2118,\n\tHCLGE_OPC_PORT_DFX_STS = 2119,\n\tHCLGE_OPC_SCH_NQ_CNT = 2120,\n\tHCLGE_OPC_SCH_RQ_CNT = 2121,\n\tHCLGE_OPC_TM_INTERNAL_STS = 2128,\n\tHCLGE_OPC_TM_INTERNAL_CNT = 2129,\n\tHCLGE_OPC_TM_INTERNAL_STS_1 = 2130,\n\tHCLGE_OPC_TM_FLUSH = 2162,\n\tHCLGE_OPC_TX_BUFF_ALLOC = 2305,\n\tHCLGE_OPC_RX_PRIV_BUFF_ALLOC = 2306,\n\tHCLGE_OPC_RX_PRIV_WL_ALLOC = 2307,\n\tHCLGE_OPC_RX_COM_THRD_ALLOC = 2308,\n\tHCLGE_OPC_RX_COM_WL_ALLOC = 2309,\n\tHCLGE_OPC_RX_GBL_PKT_CNT = 2310,\n\tHCLGE_OPC_SET_TQP_MAP = 2561,\n\tHCLGE_OPC_CFG_TX_QUEUE = 2817,\n\tHCLGE_OPC_QUERY_TX_POINTER = 2818,\n\tHCLGE_OPC_QUERY_TX_STATS = 2819,\n\tHCLGE_OPC_TQP_TX_QUEUE_TC = 2820,\n\tHCLGE_OPC_CFG_RX_QUEUE = 2833,\n\tHCLGE_OPC_QUERY_RX_POINTER = 2834,\n\tHCLGE_OPC_QUERY_RX_STATS = 2835,\n\tHCLGE_OPC_STASH_RX_QUEUE_LRO = 2838,\n\tHCLGE_OPC_CFG_RX_QUEUE_LRO = 2839,\n\tHCLGE_OPC_CFG_COM_TQP_QUEUE = 2848,\n\tHCLGE_OPC_RESET_TQP_QUEUE = 2850,\n\tHCLGE_OPC_PPU_PF_OTHER_INT_DFX = 2890,\n\tHCLGE_OPC_TSO_GENERIC_CONFIG = 3073,\n\tHCLGE_OPC_GRO_GENERIC_CONFIG = 3088,\n\tHCLGE_OPC_RSS_GENERIC_CONFIG = 3329,\n\tHCLGE_OPC_RSS_INDIR_TABLE = 3335,\n\tHCLGE_OPC_RSS_TC_MODE = 3336,\n\tHCLGE_OPC_RSS_INPUT_TUPLE = 3330,\n\tHCLGE_OPC_CFG_PROMISC_MODE = 3585,\n\tHCLGE_OPC_VLAN_PORT_TX_CFG = 3841,\n\tHCLGE_OPC_VLAN_PORT_RX_CFG = 3842,\n\tHCLGE_OPC_ADD_RING_TO_VECTOR = 5379,\n\tHCLGE_OPC_DEL_RING_TO_VECTOR = 5380,\n\tHCLGE_OPC_MAC_VLAN_ADD = 4096,\n\tHCLGE_OPC_MAC_VLAN_REMOVE = 4097,\n\tHCLGE_OPC_MAC_VLAN_TYPE_ID = 4098,\n\tHCLGE_OPC_MAC_VLAN_INSERT = 4099,\n\tHCLGE_OPC_MAC_VLAN_ALLOCATE = 4100,\n\tHCLGE_OPC_MAC_ETHTYPE_ADD = 4112,\n\tHCLGE_OPC_MAC_ETHTYPE_REMOVE = 4113,\n\tHCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 4147,\n\tHCLGE_OPC_VLAN_FILTER_CTRL = 4352,\n\tHCLGE_OPC_VLAN_FILTER_PF_CFG = 4353,\n\tHCLGE_OPC_VLAN_FILTER_VF_CFG = 4354,\n\tHCLGE_OPC_PORT_VLAN_BYPASS = 4355,\n\tHCLGE_OPC_FD_MODE_CTRL = 4608,\n\tHCLGE_OPC_FD_GET_ALLOCATION = 4609,\n\tHCLGE_OPC_FD_KEY_CONFIG = 4610,\n\tHCLGE_OPC_FD_TCAM_OP = 4611,\n\tHCLGE_OPC_FD_AD_OP = 4612,\n\tHCLGE_OPC_FD_CNT_OP = 4613,\n\tHCLGE_OPC_FD_USER_DEF_OP = 4615,\n\tHCLGE_OPC_FD_QB_CTRL = 4624,\n\tHCLGE_OPC_FD_QB_AD_OP = 4625,\n\tHCLGE_OPC_MDIO_CONFIG = 6400,\n\tHCLGE_OPC_QCN_MOD_CFG = 6657,\n\tHCLGE_OPC_QCN_GRP_TMPLT_CFG = 6658,\n\tHCLGE_OPC_QCN_SHAPPING_CFG = 6659,\n\tHCLGE_OPC_QCN_SHAPPING_BS_CFG = 6660,\n\tHCLGE_OPC_QCN_QSET_LINK_CFG = 6661,\n\tHCLGE_OPC_QCN_RP_STATUS_GET = 6662,\n\tHCLGE_OPC_QCN_AJUST_INIT = 6663,\n\tHCLGE_OPC_QCN_DFX_CNT_STATUS = 6664,\n\tHCLGE_OPC_QUERY_SCC_VER = 6788,\n\tHCLGEVF_OPC_MBX_PF_TO_VF = 8192,\n\tHCLGEVF_OPC_MBX_VF_TO_PF = 8193,\n\tHCLGE_OPC_LED_STATUS_CFG = 45056,\n\tHCLGE_OPC_CLEAR_HW_RESOURCE = 28683,\n\tHCLGE_OPC_QUERY_NCL_CONFIG = 28689,\n\tHCLGE_OPC_IMP_STATS_BD = 28690,\n\tHCLGE_OPC_IMP_STATS_INFO = 28691,\n\tHCLGE_OPC_IMP_COMPAT_CFG = 28698,\n\tHCLGE_OPC_GET_SFP_EEPROM = 28928,\n\tHCLGE_OPC_GET_SFP_EXIST = 28929,\n\tHCLGE_OPC_GET_SFP_INFO = 28932,\n\tHCLGE_MAC_COMMON_INT_EN = 782,\n\tHCLGE_TM_SCH_ECC_INT_EN = 2089,\n\tHCLGE_SSU_ECC_INT_CMD = 2441,\n\tHCLGE_SSU_COMMON_INT_CMD = 2444,\n\tHCLGE_PPU_MPF_ECC_INT_CMD = 2880,\n\tHCLGE_PPU_MPF_OTHER_INT_CMD = 2881,\n\tHCLGE_PPU_PF_OTHER_INT_CMD = 2882,\n\tHCLGE_COMMON_ECC_INT_CFG = 5381,\n\tHCLGE_QUERY_RAS_INT_STS_BD_NUM = 5392,\n\tHCLGE_QUERY_CLEAR_MPF_RAS_INT = 5393,\n\tHCLGE_QUERY_CLEAR_PF_RAS_INT = 5394,\n\tHCLGE_QUERY_MSIX_INT_STS_BD_NUM = 5395,\n\tHCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 5396,\n\tHCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 5397,\n\tHCLGE_QUERY_ALL_ERR_BD_NUM = 5398,\n\tHCLGE_QUERY_ALL_ERR_INFO = 5399,\n\tHCLGE_CONFIG_ROCEE_RAS_INT_EN = 5504,\n\tHCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 5505,\n\tHCLGE_ROCEE_PF_RAS_INT_CMD = 5508,\n\tHCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 5509,\n\tHCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 5510,\n\tHCLGE_IGU_EGU_TNL_INT_EN = 6147,\n\tHCLGE_IGU_COMMON_INT_EN = 6150,\n\tHCLGE_TM_QCN_MEM_INT_CFG = 6676,\n\tHCLGE_PPP_CMD0_INT_CMD = 8448,\n\tHCLGE_PPP_CMD1_INT_CMD = 8449,\n\tHCLGE_MAC_ETHERTYPE_IDX_RD = 8453,\n\tHCLGE_OPC_WOL_GET_SUPPORTED_MODE = 8705,\n\tHCLGE_OPC_WOL_CFG = 8706,\n\tHCLGE_NCSI_INT_EN = 9217,\n\tHCLGE_OPC_MAC_ADDR_CHECK = 36868,\n\tHCLGE_OPC_PHY_LINK_KSETTING = 28709,\n\tHCLGE_OPC_PHY_REG = 28710,\n\tHCLGE_OPC_QUERY_LINK_DIAGNOSIS = 28714,\n};\n\nenum hclge_ptp_msg0_type {\n\tHCLGE_PTP_MSG0_V2_DELAY_REQ = 1,\n\tHCLGE_PTP_MSG0_V2_PDELAY_REQ = 2,\n\tHCLGE_PTP_MSG0_V2_DELAY_RESP = 3,\n\tHCLGE_PTP_MSG0_V2_EVENT = 15,\n};\n\nenum hclge_ptp_msg_type {\n\tHCLGE_PTP_MSG_TYPE_V2_L2 = 0,\n\tHCLGE_PTP_MSG_TYPE_V2 = 1,\n\tHCLGE_PTP_MSG_TYPE_V2_EVENT = 2,\n};\n\nenum hclge_ptp_udp_type {\n\tHCLGE_PTP_UDP_NOT_TYPE = 0,\n\tHCLGE_PTP_UDP_P13F_TYPE = 1,\n\tHCLGE_PTP_UDP_P140_TYPE = 2,\n\tHCLGE_PTP_UDP_FULL_TYPE = 3,\n};\n\nenum hclge_reg_tag {\n\tHCLGE_REG_TAG_CMDQ = 0,\n\tHCLGE_REG_TAG_COMMON = 1,\n\tHCLGE_REG_TAG_RING = 2,\n\tHCLGE_REG_TAG_TQP_INTR = 3,\n\tHCLGE_REG_TAG_QUERY_32_BIT = 4,\n\tHCLGE_REG_TAG_QUERY_64_BIT = 5,\n\tHCLGE_REG_TAG_DFX_BIOS_COMMON = 6,\n\tHCLGE_REG_TAG_DFX_SSU_0 = 7,\n\tHCLGE_REG_TAG_DFX_SSU_1 = 8,\n\tHCLGE_REG_TAG_DFX_IGU_EGU = 9,\n\tHCLGE_REG_TAG_DFX_RPU_0 = 10,\n\tHCLGE_REG_TAG_DFX_RPU_1 = 11,\n\tHCLGE_REG_TAG_DFX_NCSI = 12,\n\tHCLGE_REG_TAG_DFX_RTC = 13,\n\tHCLGE_REG_TAG_DFX_PPP = 14,\n\tHCLGE_REG_TAG_DFX_RCB = 15,\n\tHCLGE_REG_TAG_DFX_TQP = 16,\n\tHCLGE_REG_TAG_DFX_SSU_2 = 17,\n\tHCLGE_REG_TAG_RPU_TNL = 18,\n};\n\nenum hclge_shap_bucket {\n\tHCLGE_TM_SHAP_C_BUCKET = 0,\n\tHCLGE_TM_SHAP_P_BUCKET = 1,\n};\n\nenum hclge_shaper_level {\n\tHCLGE_SHAPER_LVL_PRI = 0,\n\tHCLGE_SHAPER_LVL_PG = 1,\n\tHCLGE_SHAPER_LVL_PORT = 2,\n\tHCLGE_SHAPER_LVL_QSET = 3,\n\tHCLGE_SHAPER_LVL_CNT = 4,\n\tHCLGE_SHAPER_LVL_VF = 0,\n\tHCLGE_SHAPER_LVL_PF = 1,\n};\n\nenum hclge_vlan_fltr_cap {\n\tHCLGE_VLAN_FLTR_DEF = 0,\n\tHCLGE_VLAN_FLTR_CAN_MDF = 1,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum hdmi_3d_structure {\n\tHDMI_3D_STRUCTURE_INVALID = -1,\n\tHDMI_3D_STRUCTURE_FRAME_PACKING = 0,\n\tHDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1,\n\tHDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3,\n\tHDMI_3D_STRUCTURE_L_DEPTH = 4,\n\tHDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5,\n\tHDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8,\n};\n\nenum hdmi_active_aspect {\n\tHDMI_ACTIVE_ASPECT_16_9_TOP = 2,\n\tHDMI_ACTIVE_ASPECT_14_9_TOP = 3,\n\tHDMI_ACTIVE_ASPECT_16_9_CENTER = 4,\n\tHDMI_ACTIVE_ASPECT_PICTURE = 8,\n\tHDMI_ACTIVE_ASPECT_4_3 = 9,\n\tHDMI_ACTIVE_ASPECT_16_9 = 10,\n\tHDMI_ACTIVE_ASPECT_14_9 = 11,\n\tHDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15,\n};\n\nenum hdmi_audio_coding_type {\n\tHDMI_AUDIO_CODING_TYPE_STREAM = 0,\n\tHDMI_AUDIO_CODING_TYPE_PCM = 1,\n\tHDMI_AUDIO_CODING_TYPE_AC3 = 2,\n\tHDMI_AUDIO_CODING_TYPE_MPEG1 = 3,\n\tHDMI_AUDIO_CODING_TYPE_MP3 = 4,\n\tHDMI_AUDIO_CODING_TYPE_MPEG2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_DTS = 7,\n\tHDMI_AUDIO_CODING_TYPE_ATRAC = 8,\n\tHDMI_AUDIO_CODING_TYPE_DSD = 9,\n\tHDMI_AUDIO_CODING_TYPE_EAC3 = 10,\n\tHDMI_AUDIO_CODING_TYPE_DTS_HD = 11,\n\tHDMI_AUDIO_CODING_TYPE_MLP = 12,\n\tHDMI_AUDIO_CODING_TYPE_DST = 13,\n\tHDMI_AUDIO_CODING_TYPE_WMA_PRO = 14,\n\tHDMI_AUDIO_CODING_TYPE_CXT = 15,\n};\n\nenum hdmi_audio_coding_type_ext {\n\tHDMI_AUDIO_CODING_TYPE_EXT_CT = 0,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_EXT_DRA = 7,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10,\n};\n\nenum hdmi_audio_sample_frequency {\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7,\n};\n\nenum hdmi_audio_sample_size {\n\tHDMI_AUDIO_SAMPLE_SIZE_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_SIZE_16 = 1,\n\tHDMI_AUDIO_SAMPLE_SIZE_20 = 2,\n\tHDMI_AUDIO_SAMPLE_SIZE_24 = 3,\n};\n\nenum hdmi_colorimetry {\n\tHDMI_COLORIMETRY_NONE = 0,\n\tHDMI_COLORIMETRY_ITU_601 = 1,\n\tHDMI_COLORIMETRY_ITU_709 = 2,\n\tHDMI_COLORIMETRY_EXTENDED = 3,\n};\n\nenum hdmi_colorspace {\n\tHDMI_COLORSPACE_RGB = 0,\n\tHDMI_COLORSPACE_YUV422 = 1,\n\tHDMI_COLORSPACE_YUV444 = 2,\n\tHDMI_COLORSPACE_YUV420 = 3,\n\tHDMI_COLORSPACE_RESERVED4 = 4,\n\tHDMI_COLORSPACE_RESERVED5 = 5,\n\tHDMI_COLORSPACE_RESERVED6 = 6,\n\tHDMI_COLORSPACE_IDO_DEFINED = 7,\n};\n\nenum hdmi_content_type {\n\tHDMI_CONTENT_TYPE_GRAPHICS = 0,\n\tHDMI_CONTENT_TYPE_PHOTO = 1,\n\tHDMI_CONTENT_TYPE_CINEMA = 2,\n\tHDMI_CONTENT_TYPE_GAME = 3,\n};\n\nenum hdmi_eotf {\n\tHDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0,\n\tHDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1,\n\tHDMI_EOTF_SMPTE_ST2084 = 2,\n\tHDMI_EOTF_BT_2100_HLG = 3,\n};\n\nenum hdmi_extended_colorimetry {\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0,\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1,\n\tHDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2,\n\tHDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3,\n\tHDMI_EXTENDED_COLORIMETRY_OPRGB = 4,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020 = 6,\n\tHDMI_EXTENDED_COLORIMETRY_RESERVED = 7,\n};\n\nenum hdmi_infoframe_type {\n\tHDMI_INFOFRAME_TYPE_VENDOR = 129,\n\tHDMI_INFOFRAME_TYPE_AVI = 130,\n\tHDMI_INFOFRAME_TYPE_SPD = 131,\n\tHDMI_INFOFRAME_TYPE_AUDIO = 132,\n\tHDMI_INFOFRAME_TYPE_DRM = 135,\n};\n\nenum hdmi_metadata_type {\n\tHDMI_STATIC_METADATA_TYPE1 = 0,\n};\n\nenum hdmi_nups {\n\tHDMI_NUPS_UNKNOWN = 0,\n\tHDMI_NUPS_HORIZONTAL = 1,\n\tHDMI_NUPS_VERTICAL = 2,\n\tHDMI_NUPS_BOTH = 3,\n};\n\nenum hdmi_picture_aspect {\n\tHDMI_PICTURE_ASPECT_NONE = 0,\n\tHDMI_PICTURE_ASPECT_4_3 = 1,\n\tHDMI_PICTURE_ASPECT_16_9 = 2,\n\tHDMI_PICTURE_ASPECT_64_27 = 3,\n\tHDMI_PICTURE_ASPECT_256_135 = 4,\n\tHDMI_PICTURE_ASPECT_RESERVED = 5,\n};\n\nenum hdmi_quantization_range {\n\tHDMI_QUANTIZATION_RANGE_DEFAULT = 0,\n\tHDMI_QUANTIZATION_RANGE_LIMITED = 1,\n\tHDMI_QUANTIZATION_RANGE_FULL = 2,\n\tHDMI_QUANTIZATION_RANGE_RESERVED = 3,\n};\n\nenum hdmi_scan_mode {\n\tHDMI_SCAN_MODE_NONE = 0,\n\tHDMI_SCAN_MODE_OVERSCAN = 1,\n\tHDMI_SCAN_MODE_UNDERSCAN = 2,\n\tHDMI_SCAN_MODE_RESERVED = 3,\n};\n\nenum hdmi_spd_sdi {\n\tHDMI_SPD_SDI_UNKNOWN = 0,\n\tHDMI_SPD_SDI_DSTB = 1,\n\tHDMI_SPD_SDI_DVDP = 2,\n\tHDMI_SPD_SDI_DVHS = 3,\n\tHDMI_SPD_SDI_HDDVR = 4,\n\tHDMI_SPD_SDI_DVC = 5,\n\tHDMI_SPD_SDI_DSC = 6,\n\tHDMI_SPD_SDI_VCD = 7,\n\tHDMI_SPD_SDI_GAME = 8,\n\tHDMI_SPD_SDI_PC = 9,\n\tHDMI_SPD_SDI_BD = 10,\n\tHDMI_SPD_SDI_SACD = 11,\n\tHDMI_SPD_SDI_HDDVD = 12,\n\tHDMI_SPD_SDI_PMP = 13,\n};\n\nenum hdmi_ycc_quantization_range {\n\tHDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0,\n\tHDMI_YCC_QUANTIZATION_RANGE_FULL = 1,\n};\n\nenum health_desc_param {\n\tHEALTH_DESC_PARAM_LEN = 0,\n\tHEALTH_DESC_PARAM_TYPE = 1,\n\tHEALTH_DESC_PARAM_EOL_INFO = 2,\n\tHEALTH_DESC_PARAM_LIFE_TIME_EST_A = 3,\n\tHEALTH_DESC_PARAM_LIFE_TIME_EST_B = 4,\n};\n\nenum hest_status {\n\tHEST_ENABLED = 0,\n\tHEST_DISABLED = 1,\n\tHEST_NOT_FOUND = 2,\n};\n\nenum hi6220_reset_ctrl_type {\n\tPERIPHERAL = 0,\n\tMEDIA = 1,\n\tAO = 2,\n};\n\nenum hi6421_type {\n\tHI6421 = 0,\n\tHI6421_V530 = 1,\n};\n\nenum hi6421v530_regulator_id {\n\tHI6421V530_LDO3 = 0,\n\tHI6421V530_LDO9 = 1,\n\tHI6421V530_LDO11 = 2,\n\tHI6421V530_LDO15 = 3,\n\tHI6421V530_LDO16 = 4,\n};\n\nenum hi655x_regulator_id {\n\tHI655X_LDO0 = 0,\n\tHI655X_LDO1 = 1,\n\tHI655X_LDO2 = 2,\n\tHI655X_LDO3 = 3,\n\tHI655X_LDO4 = 4,\n\tHI655X_LDO5 = 5,\n\tHI655X_LDO6 = 6,\n\tHI655X_LDO7 = 7,\n\tHI655X_LDO8 = 8,\n\tHI655X_LDO9 = 9,\n\tHI655X_LDO10 = 10,\n\tHI655X_LDO11 = 11,\n\tHI655X_LDO12 = 12,\n\tHI655X_LDO13 = 13,\n\tHI655X_LDO14 = 14,\n\tHI655X_LDO15 = 15,\n\tHI655X_LDO16 = 16,\n\tHI655X_LDO17 = 17,\n\tHI655X_LDO18 = 18,\n\tHI655X_LDO19 = 19,\n\tHI655X_LDO20 = 20,\n\tHI655X_LDO21 = 21,\n\tHI655X_LDO22 = 22,\n};\n\nenum hid_class_request {\n\tHID_REQ_GET_REPORT = 1,\n\tHID_REQ_GET_IDLE = 2,\n\tHID_REQ_GET_PROTOCOL = 3,\n\tHID_REQ_SET_REPORT = 9,\n\tHID_REQ_SET_IDLE = 10,\n\tHID_REQ_SET_PROTOCOL = 11,\n};\n\nenum hid_report_type {\n\tHID_INPUT_REPORT = 0,\n\tHID_OUTPUT_REPORT = 1,\n\tHID_FEATURE_REPORT = 2,\n\tHID_REPORT_TYPES = 3,\n};\n\nenum hid_type {\n\tHID_TYPE_OTHER = 0,\n\tHID_TYPE_USBMOUSE = 1,\n\tHID_TYPE_USBNONE = 2,\n};\n\nenum hidma_cap {\n\tHIDMA_MSI_CAP = 1,\n\tHIDMA_IDENTITY_CAP = 2,\n};\n\nenum hisi_sas_debugfs_bist_ffe_cfg {\n\tFFE_SAS_1_5_GBPS = 0,\n\tFFE_SAS_3_0_GBPS = 1,\n\tFFE_SAS_6_0_GBPS = 2,\n\tFFE_SAS_12_0_GBPS = 3,\n\tFFE_RESV = 4,\n\tFFE_SATA_1_5_GBPS = 5,\n\tFFE_SATA_3_0_GBPS = 6,\n\tFFE_SATA_6_0_GBPS = 7,\n\tFFE_CFG_MAX = 8,\n};\n\nenum hisi_sas_debugfs_bist_fixed_code {\n\tFIXED_CODE = 0,\n\tFIXED_CODE_1 = 1,\n\tFIXED_CODE_MAX = 2,\n};\n\nenum hisi_sas_debugfs_cache_type {\n\tHISI_SAS_ITCT_CACHE = 0,\n\tHISI_SAS_IOST_CACHE = 1,\n};\n\nenum hisi_sas_debugfs_reg_array_member {\n\tDEBUGFS_GLOBAL = 0,\n\tDEBUGFS_AXI = 1,\n\tDEBUGFS_RAS = 2,\n\tDEBUGFS_REGS_NUM = 3,\n};\n\nenum hisi_sas_dev_type {\n\tHISI_SAS_DEV_TYPE_STP = 0,\n\tHISI_SAS_DEV_TYPE_SSP = 1,\n\tHISI_SAS_DEV_TYPE_SATA = 2,\n};\n\nenum hisi_sas_phy_event {\n\tHISI_PHYE_PHY_UP = 0,\n\tHISI_PHYE_LINK_RESET = 1,\n\tHISI_PHYE_PHY_UP_PM = 2,\n\tHISI_PHYES_NUM = 3,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hn_flags_bits {\n\tHANDSHAKE_F_NET_DRAINING = 0,\n};\n\nenum hnae3_client_type {\n\tHNAE3_CLIENT_KNIC = 0,\n\tHNAE3_CLIENT_ROCE = 1,\n};\n\nenum hnae3_dbg_cmd {\n\tHNAE3_DBG_CMD_TM_NODES = 0,\n\tHNAE3_DBG_CMD_TM_PRI = 1,\n\tHNAE3_DBG_CMD_TM_QSET = 2,\n\tHNAE3_DBG_CMD_TM_MAP = 3,\n\tHNAE3_DBG_CMD_TM_PG = 4,\n\tHNAE3_DBG_CMD_TM_PORT = 5,\n\tHNAE3_DBG_CMD_TC_SCH_INFO = 6,\n\tHNAE3_DBG_CMD_QOS_PAUSE_CFG = 7,\n\tHNAE3_DBG_CMD_QOS_PRI_MAP = 8,\n\tHNAE3_DBG_CMD_QOS_DSCP_MAP = 9,\n\tHNAE3_DBG_CMD_QOS_BUF_CFG = 10,\n\tHNAE3_DBG_CMD_DEV_INFO = 11,\n\tHNAE3_DBG_CMD_TX_BD = 12,\n\tHNAE3_DBG_CMD_RX_BD = 13,\n\tHNAE3_DBG_CMD_MAC_UC = 14,\n\tHNAE3_DBG_CMD_MAC_MC = 15,\n\tHNAE3_DBG_CMD_MNG_TBL = 16,\n\tHNAE3_DBG_CMD_LOOPBACK = 17,\n\tHNAE3_DBG_CMD_PTP_INFO = 18,\n\tHNAE3_DBG_CMD_INTERRUPT_INFO = 19,\n\tHNAE3_DBG_CMD_RESET_INFO = 20,\n\tHNAE3_DBG_CMD_IMP_INFO = 21,\n\tHNAE3_DBG_CMD_NCL_CONFIG = 22,\n\tHNAE3_DBG_CMD_REG_BIOS_COMMON = 23,\n\tHNAE3_DBG_CMD_REG_SSU = 24,\n\tHNAE3_DBG_CMD_REG_IGU_EGU = 25,\n\tHNAE3_DBG_CMD_REG_RPU = 26,\n\tHNAE3_DBG_CMD_REG_NCSI = 27,\n\tHNAE3_DBG_CMD_REG_RTC = 28,\n\tHNAE3_DBG_CMD_REG_PPP = 29,\n\tHNAE3_DBG_CMD_REG_RCB = 30,\n\tHNAE3_DBG_CMD_REG_TQP = 31,\n\tHNAE3_DBG_CMD_REG_MAC = 32,\n\tHNAE3_DBG_CMD_REG_DCB = 33,\n\tHNAE3_DBG_CMD_VLAN_CONFIG = 34,\n\tHNAE3_DBG_CMD_QUEUE_MAP = 35,\n\tHNAE3_DBG_CMD_RX_QUEUE_INFO = 36,\n\tHNAE3_DBG_CMD_TX_QUEUE_INFO = 37,\n\tHNAE3_DBG_CMD_FD_TCAM = 38,\n\tHNAE3_DBG_CMD_FD_COUNTER = 39,\n\tHNAE3_DBG_CMD_MAC_TNL_STATUS = 40,\n\tHNAE3_DBG_CMD_SERV_INFO = 41,\n\tHNAE3_DBG_CMD_UMV_INFO = 42,\n\tHNAE3_DBG_CMD_PAGE_POOL_INFO = 43,\n\tHNAE3_DBG_CMD_COAL_INFO = 44,\n\tHNAE3_DBG_CMD_UNKNOWN = 45,\n};\n\nenum hnae3_fec_mode {\n\tHNAE3_FEC_AUTO = 0,\n\tHNAE3_FEC_BASER = 1,\n\tHNAE3_FEC_RS = 2,\n\tHNAE3_FEC_LLRS = 3,\n\tHNAE3_FEC_NONE = 4,\n\tHNAE3_FEC_USER_DEF = 5,\n};\n\nenum hnae3_hw_error_type {\n\tHNAE3_PPU_POISON_ERROR = 0,\n\tHNAE3_CMDQ_ECC_ERROR = 1,\n\tHNAE3_IMP_RD_POISON_ERROR = 2,\n\tHNAE3_ROCEE_AXI_RESP_ERROR = 3,\n};\n\nenum hnae3_loop {\n\tHNAE3_LOOP_EXTERNAL = 0,\n\tHNAE3_LOOP_APP = 1,\n\tHNAE3_LOOP_SERIAL_SERDES = 2,\n\tHNAE3_LOOP_PARALLEL_SERDES = 3,\n\tHNAE3_LOOP_PHY = 4,\n\tHNAE3_LOOP_NONE = 5,\n};\n\nenum hnae3_media_type {\n\tHNAE3_MEDIA_TYPE_UNKNOWN = 0,\n\tHNAE3_MEDIA_TYPE_FIBER = 1,\n\tHNAE3_MEDIA_TYPE_COPPER = 2,\n\tHNAE3_MEDIA_TYPE_BACKPLANE = 3,\n\tHNAE3_MEDIA_TYPE_NONE = 4,\n};\n\nenum hnae3_module_type {\n\tHNAE3_MODULE_TYPE_UNKNOWN = 0,\n\tHNAE3_MODULE_TYPE_FIBRE_LR = 1,\n\tHNAE3_MODULE_TYPE_FIBRE_SR = 2,\n\tHNAE3_MODULE_TYPE_AOC = 3,\n\tHNAE3_MODULE_TYPE_CR = 4,\n\tHNAE3_MODULE_TYPE_KR = 5,\n\tHNAE3_MODULE_TYPE_TP = 6,\n};\n\nenum hnae3_pflag {\n\tHNAE3_PFLAG_LIMIT_PROMISC = 0,\n\tHNAE3_PFLAG_MAX = 1,\n};\n\nenum hnae3_port_base_vlan_state {\n\tHNAE3_PORT_BASE_VLAN_DISABLE = 0,\n\tHNAE3_PORT_BASE_VLAN_ENABLE = 1,\n\tHNAE3_PORT_BASE_VLAN_MODIFY = 2,\n\tHNAE3_PORT_BASE_VLAN_NOCHANGE = 3,\n};\n\nenum hnae3_reset_notify_type {\n\tHNAE3_UP_CLIENT = 0,\n\tHNAE3_DOWN_CLIENT = 1,\n\tHNAE3_INIT_CLIENT = 2,\n\tHNAE3_UNINIT_CLIENT = 3,\n};\n\nenum hnae3_reset_type {\n\tHNAE3_VF_RESET = 0,\n\tHNAE3_VF_FUNC_RESET = 1,\n\tHNAE3_VF_PF_FUNC_RESET = 2,\n\tHNAE3_VF_FULL_RESET = 3,\n\tHNAE3_FLR_RESET = 4,\n\tHNAE3_FUNC_RESET = 5,\n\tHNAE3_GLOBAL_RESET = 6,\n\tHNAE3_IMP_RESET = 7,\n\tHNAE3_NONE_RESET = 8,\n\tHNAE3_VF_EXP_RESET = 9,\n\tHNAE3_MAX_RESET = 10,\n};\n\nenum hnae3_tc_map_mode {\n\tHNAE3_TC_MAP_MODE_PRIO = 0,\n\tHNAE3_TC_MAP_MODE_DSCP = 1,\n};\n\nenum hnae_led_state {\n\tHNAE_LED_INACTIVE = 0,\n\tHNAE_LED_ACTIVE = 1,\n\tHNAE_LED_ON = 2,\n\tHNAE_LED_OFF = 3,\n};\n\nenum hnae_loop {\n\tMAC_INTERNALLOOP_MAC = 0,\n\tMAC_INTERNALLOOP_SERDES = 1,\n\tMAC_INTERNALLOOP_PHY = 2,\n\tMAC_LOOP_PHY_NONE = 3,\n\tMAC_LOOP_NONE = 4,\n};\n\nenum hnae_media_type {\n\tHNAE_MEDIA_TYPE_UNKNOWN = 0,\n\tHNAE_MEDIA_TYPE_FIBER = 1,\n\tHNAE_MEDIA_TYPE_COPPER = 2,\n\tHNAE_MEDIA_TYPE_BACKPLANE = 3,\n};\n\nenum hnae_port_type {\n\tHNAE_PORT_SERVICE = 0,\n\tHNAE_PORT_DEBUG = 1,\n};\n\nenum hns3_dbg_dentry_type {\n\tHNS3_DBG_DENTRY_TM = 0,\n\tHNS3_DBG_DENTRY_TX_BD = 1,\n\tHNS3_DBG_DENTRY_RX_BD = 2,\n\tHNS3_DBG_DENTRY_MAC = 3,\n\tHNS3_DBG_DENTRY_REG = 4,\n\tHNS3_DBG_DENTRY_QUEUE = 5,\n\tHNS3_DBG_DENTRY_FD = 6,\n\tHNS3_DBG_DENTRY_COMMON = 7,\n};\n\nenum hns3_desc_type {\n\tDESC_TYPE_UNKNOWN = 0,\n\tDESC_TYPE_SKB = 1,\n\tDESC_TYPE_FRAGLIST_SKB = 2,\n\tDESC_TYPE_PAGE = 4,\n\tDESC_TYPE_BOUNCE_ALL = 8,\n\tDESC_TYPE_BOUNCE_HEAD = 16,\n\tDESC_TYPE_SGL_SKB = 32,\n\tDESC_TYPE_PP_FRAG = 64,\n};\n\nenum hns3_flow_level_range {\n\tHNS3_FLOW_LOW = 0,\n\tHNS3_FLOW_MID = 1,\n\tHNS3_FLOW_HIGH = 2,\n\tHNS3_FLOW_ULTRA = 3,\n};\n\nenum hns3_nic_state {\n\tHNS3_NIC_STATE_TESTING = 0,\n\tHNS3_NIC_STATE_RESETTING = 1,\n\tHNS3_NIC_STATE_INITED = 2,\n\tHNS3_NIC_STATE_DOWN = 3,\n\tHNS3_NIC_STATE_DISABLED = 4,\n\tHNS3_NIC_STATE_REMOVING = 5,\n\tHNS3_NIC_STATE_SERVICE_INITED = 6,\n\tHNS3_NIC_STATE_SERVICE_SCHED = 7,\n\tHNS3_NIC_STATE2_RESET_REQUESTED = 8,\n\tHNS3_NIC_STATE_HW_TX_CSUM_ENABLE = 9,\n\tHNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE = 10,\n\tHNS3_NIC_STATE_TX_PUSH_ENABLE = 11,\n\tHNS3_NIC_STATE_MAX = 12,\n};\n\nenum hns3_pkt_l2t_type {\n\tHNS3_L2_TYPE_UNICAST = 0,\n\tHNS3_L2_TYPE_MULTICAST = 1,\n\tHNS3_L2_TYPE_BROADCAST = 2,\n\tHNS3_L2_TYPE_INVALID = 3,\n};\n\nenum hns3_pkt_l3t_type {\n\tHNS3_L3T_NONE = 0,\n\tHNS3_L3T_IPV6 = 1,\n\tHNS3_L3T_IPV4 = 2,\n\tHNS3_L3T_RESERVED = 3,\n};\n\nenum hns3_pkt_l3type {\n\tHNS3_L3_TYPE_IPV4 = 0,\n\tHNS3_L3_TYPE_IPV6 = 1,\n\tHNS3_L3_TYPE_ARP = 2,\n\tHNS3_L3_TYPE_RARP = 3,\n\tHNS3_L3_TYPE_IPV4_OPT = 4,\n\tHNS3_L3_TYPE_IPV6_EXT = 5,\n\tHNS3_L3_TYPE_LLDP = 6,\n\tHNS3_L3_TYPE_BPDU = 7,\n\tHNS3_L3_TYPE_MAC_PAUSE = 8,\n\tHNS3_L3_TYPE_PFC_PAUSE = 9,\n\tHNS3_L3_TYPE_CNM = 12,\n\tHNS3_L3_TYPE_PARSE_FAIL = 15,\n};\n\nenum hns3_pkt_l4t_type {\n\tHNS3_L4T_UNKNOWN = 0,\n\tHNS3_L4T_TCP = 1,\n\tHNS3_L4T_UDP = 2,\n\tHNS3_L4T_SCTP = 3,\n};\n\nenum hns3_pkt_l4type {\n\tHNS3_L4_TYPE_UDP = 0,\n\tHNS3_L4_TYPE_TCP = 1,\n\tHNS3_L4_TYPE_GRE = 2,\n\tHNS3_L4_TYPE_SCTP = 3,\n\tHNS3_L4_TYPE_IGMP = 4,\n\tHNS3_L4_TYPE_ICMP = 5,\n\tHNS3_L4_TYPE_PARSE_FAIL = 15,\n};\n\nenum hns3_pkt_ol3t_type {\n\tHNS3_OL3T_NONE = 0,\n\tHNS3_OL3T_IPV6 = 1,\n\tHNS3_OL3T_IPV4_NO_CSUM = 2,\n\tHNS3_OL3T_IPV4_CSUM = 3,\n};\n\nenum hns3_pkt_ol4type {\n\tHNS3_OL4_TYPE_NO_TUN = 0,\n\tHNS3_OL4_TYPE_MAC_IN_UDP = 1,\n\tHNS3_OL4_TYPE_NVGRE = 2,\n\tHNS3_OL4_TYPE_UNKNOWN = 3,\n};\n\nenum hns3_pkt_tun_type {\n\tHNS3_TUN_NONE = 0,\n\tHNS3_TUN_MAC_IN_UDP = 1,\n\tHNS3_TUN_NVGRE = 2,\n\tHNS3_TUN_OTHER = 3,\n};\n\nenum hns_desc_type {\n\tDESC_TYPE_SKB___2 = 0,\n\tDESC_TYPE_PAGE___2 = 1,\n};\n\nenum hns_gmac_duplex_mdoe {\n\tGMAC_HALF_DUPLEX_MODE = 0,\n\tGMAC_FULL_DUPLEX_MODE = 1,\n};\n\nenum hns_nic_state {\n\tNIC_STATE_TESTING = 0,\n\tNIC_STATE_RESETTING = 1,\n\tNIC_STATE_REINITING = 2,\n\tNIC_STATE_DOWN = 3,\n\tNIC_STATE_DISABLED = 4,\n\tNIC_STATE_REMOVING = 5,\n\tNIC_STATE_SERVICE_INITED = 6,\n\tNIC_STATE_SERVICE_SCHED = 7,\n\tNIC_STATE2_RESET_REQUESTED = 8,\n\tNIC_STATE_MAX = 9,\n};\n\nenum hns_port_mode {\n\tGMAC_10M_MII = 0,\n\tGMAC_100M_MII = 1,\n\tGMAC_1000M_GMII = 2,\n\tGMAC_10M_RGMII = 3,\n\tGMAC_100M_RGMII = 4,\n\tGMAC_1000M_RGMII = 5,\n\tGMAC_10M_SGMII = 6,\n\tGMAC_100M_SGMII = 7,\n\tGMAC_1000M_SGMII = 8,\n\tGMAC_10000M_SGMII = 9,\n};\n\nenum host_event_code {\n\tEC_HOST_EVENT_LID_CLOSED = 1,\n\tEC_HOST_EVENT_LID_OPEN = 2,\n\tEC_HOST_EVENT_POWER_BUTTON = 3,\n\tEC_HOST_EVENT_AC_CONNECTED = 4,\n\tEC_HOST_EVENT_AC_DISCONNECTED = 5,\n\tEC_HOST_EVENT_BATTERY_LOW = 6,\n\tEC_HOST_EVENT_BATTERY_CRITICAL = 7,\n\tEC_HOST_EVENT_BATTERY = 8,\n\tEC_HOST_EVENT_THERMAL_THRESHOLD = 9,\n\tEC_HOST_EVENT_DEVICE = 10,\n\tEC_HOST_EVENT_THERMAL = 11,\n\tEC_HOST_EVENT_USB_CHARGER = 12,\n\tEC_HOST_EVENT_KEY_PRESSED = 13,\n\tEC_HOST_EVENT_INTERFACE_READY = 14,\n\tEC_HOST_EVENT_KEYBOARD_RECOVERY = 15,\n\tEC_HOST_EVENT_THERMAL_SHUTDOWN = 16,\n\tEC_HOST_EVENT_BATTERY_SHUTDOWN = 17,\n\tEC_HOST_EVENT_THROTTLE_START = 18,\n\tEC_HOST_EVENT_THROTTLE_STOP = 19,\n\tEC_HOST_EVENT_HANG_DETECT = 20,\n\tEC_HOST_EVENT_HANG_REBOOT = 21,\n\tEC_HOST_EVENT_PD_MCU = 22,\n\tEC_HOST_EVENT_BATTERY_STATUS = 23,\n\tEC_HOST_EVENT_PANIC = 24,\n\tEC_HOST_EVENT_KEYBOARD_FASTBOOT = 25,\n\tEC_HOST_EVENT_RTC = 26,\n\tEC_HOST_EVENT_MKBP = 27,\n\tEC_HOST_EVENT_USB_MUX = 28,\n\tEC_HOST_EVENT_MODE_CHANGE = 29,\n\tEC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30,\n\tEC_HOST_EVENT_WOV = 31,\n\tEC_HOST_EVENT_INVALID = 32,\n};\n\nenum host_sleep_event {\n\tHOST_SLEEP_EVENT_S3_SUSPEND = 1,\n\tHOST_SLEEP_EVENT_S3_RESUME = 2,\n\tHOST_SLEEP_EVENT_S0IX_SUSPEND = 3,\n\tHOST_SLEEP_EVENT_S0IX_RESUME = 4,\n\tHOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5,\n};\n\nenum hp_flags_bits {\n\tHANDSHAKE_F_PROTO_NOTIFY = 0,\n};\n\nenum hprobe_state {\n\tHPROBE_LEASED = 0,\n\tHPROBE_STABLE = 1,\n\tHPROBE_GONE = 2,\n\tHPROBE_CONSUMED = 3,\n};\n\nenum hpx_type3_cfg_loc {\n\tHPX_CFG_PCICFG = 0,\n\tHPX_CFG_PCIE_CAP = 1,\n\tHPX_CFG_PCIE_CAP_EXT = 2,\n\tHPX_CFG_VEND_CAP = 3,\n\tHPX_CFG_DVSEC = 4,\n\tHPX_CFG_MAX = 5,\n};\n\nenum hpx_type3_dev_type {\n\tHPX_TYPE_ENDPOINT = 1,\n\tHPX_TYPE_LEG_END = 2,\n\tHPX_TYPE_RC_END = 4,\n\tHPX_TYPE_RC_EC = 8,\n\tHPX_TYPE_ROOT_PORT = 16,\n\tHPX_TYPE_UPSTREAM = 32,\n\tHPX_TYPE_DOWNSTREAM = 64,\n\tHPX_TYPE_PCI_BRIDGE = 128,\n\tHPX_TYPE_PCIE_BRIDGE = 256,\n};\n\nenum hpx_type3_fn_type {\n\tHPX_FN_NORMAL = 1,\n\tHPX_FN_SRIOV_PHYS = 2,\n\tHPX_FN_SRIOV_VIRT = 4,\n};\n\nenum hr_flags_bits {\n\tHANDSHAKE_F_REQ_COMPLETED = 0,\n\tHANDSHAKE_F_REQ_SESSION = 1,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nenum hte_edge {\n\tHTE_EDGE_NO_SETUP = 1,\n\tHTE_RISING_EDGE_TS = 2,\n\tHTE_FALLING_EDGE_TS = 4,\n};\n\nenum hte_return {\n\tHTE_CB_HANDLED = 0,\n\tHTE_RUN_SECOND_CB = 1,\n};\n\nenum hub_activation_type {\n\tHUB_INIT = 0,\n\tHUB_INIT2 = 1,\n\tHUB_INIT3 = 2,\n\tHUB_POST_RESET = 3,\n\tHUB_RESUME = 4,\n\tHUB_RESET_RESUME = 5,\n};\n\nenum hub_led_mode {\n\tINDICATOR_AUTO = 0,\n\tINDICATOR_CYCLE = 1,\n\tINDICATOR_GREEN_BLINK = 2,\n\tINDICATOR_GREEN_BLINK_OFF = 3,\n\tINDICATOR_AMBER_BLINK = 4,\n\tINDICATOR_AMBER_BLINK_OFF = 5,\n\tINDICATOR_ALT_BLINK = 6,\n\tINDICATOR_ALT_BLINK_OFF = 7,\n} __attribute__((mode(byte)));\n\nenum hub_quiescing_type {\n\tHUB_DISCONNECT = 0,\n\tHUB_PRE_RESET = 1,\n\tHUB_SUSPEND = 2,\n};\n\nenum hugetlb_memory_event {\n\tHUGETLB_MAX = 0,\n\tHUGETLB_NR_MEMORY_EVENTS = 1,\n};\n\nenum hugetlb_page_flags {\n\tHPG_restore_reserve = 0,\n\tHPG_migratable = 1,\n\tHPG_temporary = 2,\n\tHPG_freed = 3,\n\tHPG_vmemmap_optimized = 4,\n\tHPG_raw_hwp_unreliable = 5,\n\tHPG_cma = 6,\n\t__NR_HPAGEFLAGS = 7,\n};\n\nenum hugetlb_param {\n\tOpt_gid___7 = 0,\n\tOpt_min_size = 1,\n\tOpt_mode___4 = 2,\n\tOpt_nr_inodes = 3,\n\tOpt_pagesize = 4,\n\tOpt_size = 5,\n\tOpt_uid___7 = 6,\n};\n\nenum hugetlbfs_size_type {\n\tNO_SIZE = 0,\n\tSIZE_STD = 1,\n\tSIZE_PERCENT = 2,\n};\n\nenum hw_breakpoint_ops {\n\tHW_BREAKPOINT_INSTALL = 0,\n\tHW_BREAKPOINT_UNINSTALL = 1,\n\tHW_BREAKPOINT_RESTORE = 2,\n};\n\nenum hw_event_mc_err_type {\n\tHW_EVENT_ERR_CORRECTED = 0,\n\tHW_EVENT_ERR_UNCORRECTED = 1,\n\tHW_EVENT_ERR_DEFERRED = 2,\n\tHW_EVENT_ERR_FATAL = 3,\n\tHW_EVENT_ERR_INFO = 4,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwerr_error_type {\n\tHWERR_RECOV_CPU = 0,\n\tHWERR_RECOV_MEMORY = 1,\n\tHWERR_RECOV_PCI = 2,\n\tHWERR_RECOV_CXL = 3,\n\tHWERR_RECOV_OTHERS = 4,\n\tHWERR_RECOV_MAX = 5,\n};\n\nenum hwmon_chip_attributes {\n\thwmon_chip_temp_reset_history = 0,\n\thwmon_chip_in_reset_history = 1,\n\thwmon_chip_curr_reset_history = 2,\n\thwmon_chip_power_reset_history = 3,\n\thwmon_chip_register_tz = 4,\n\thwmon_chip_update_interval = 5,\n\thwmon_chip_alarms = 6,\n\thwmon_chip_samples = 7,\n\thwmon_chip_curr_samples = 8,\n\thwmon_chip_in_samples = 9,\n\thwmon_chip_power_samples = 10,\n\thwmon_chip_temp_samples = 11,\n\thwmon_chip_beep_enable = 12,\n\thwmon_chip_pec = 13,\n};\n\nenum hwmon_curr_attributes {\n\thwmon_curr_enable = 0,\n\thwmon_curr_input = 1,\n\thwmon_curr_min = 2,\n\thwmon_curr_max = 3,\n\thwmon_curr_lcrit = 4,\n\thwmon_curr_crit = 5,\n\thwmon_curr_average = 6,\n\thwmon_curr_lowest = 7,\n\thwmon_curr_highest = 8,\n\thwmon_curr_reset_history = 9,\n\thwmon_curr_label = 10,\n\thwmon_curr_alarm = 11,\n\thwmon_curr_min_alarm = 12,\n\thwmon_curr_max_alarm = 13,\n\thwmon_curr_lcrit_alarm = 14,\n\thwmon_curr_crit_alarm = 15,\n\thwmon_curr_rated_min = 16,\n\thwmon_curr_rated_max = 17,\n\thwmon_curr_beep = 18,\n};\n\nenum hwmon_energy_attributes {\n\thwmon_energy_enable = 0,\n\thwmon_energy_input = 1,\n\thwmon_energy_label = 2,\n};\n\nenum hwmon_fan_attributes {\n\thwmon_fan_enable = 0,\n\thwmon_fan_input = 1,\n\thwmon_fan_label = 2,\n\thwmon_fan_min = 3,\n\thwmon_fan_max = 4,\n\thwmon_fan_div = 5,\n\thwmon_fan_pulses = 6,\n\thwmon_fan_target = 7,\n\thwmon_fan_alarm = 8,\n\thwmon_fan_min_alarm = 9,\n\thwmon_fan_max_alarm = 10,\n\thwmon_fan_fault = 11,\n\thwmon_fan_beep = 12,\n};\n\nenum hwmon_humidity_attributes {\n\thwmon_humidity_enable = 0,\n\thwmon_humidity_input = 1,\n\thwmon_humidity_label = 2,\n\thwmon_humidity_min = 3,\n\thwmon_humidity_min_hyst = 4,\n\thwmon_humidity_max = 5,\n\thwmon_humidity_max_hyst = 6,\n\thwmon_humidity_alarm = 7,\n\thwmon_humidity_fault = 8,\n\thwmon_humidity_rated_min = 9,\n\thwmon_humidity_rated_max = 10,\n\thwmon_humidity_min_alarm = 11,\n\thwmon_humidity_max_alarm = 12,\n};\n\nenum hwmon_in_attributes {\n\thwmon_in_enable = 0,\n\thwmon_in_input = 1,\n\thwmon_in_min = 2,\n\thwmon_in_max = 3,\n\thwmon_in_lcrit = 4,\n\thwmon_in_crit = 5,\n\thwmon_in_average = 6,\n\thwmon_in_lowest = 7,\n\thwmon_in_highest = 8,\n\thwmon_in_reset_history = 9,\n\thwmon_in_label = 10,\n\thwmon_in_alarm = 11,\n\thwmon_in_min_alarm = 12,\n\thwmon_in_max_alarm = 13,\n\thwmon_in_lcrit_alarm = 14,\n\thwmon_in_crit_alarm = 15,\n\thwmon_in_rated_min = 16,\n\thwmon_in_rated_max = 17,\n\thwmon_in_beep = 18,\n\thwmon_in_fault = 19,\n};\n\nenum hwmon_intrusion_attributes {\n\thwmon_intrusion_alarm = 0,\n\thwmon_intrusion_beep = 1,\n};\n\nenum hwmon_power_attributes {\n\thwmon_power_enable = 0,\n\thwmon_power_average = 1,\n\thwmon_power_average_interval = 2,\n\thwmon_power_average_interval_max = 3,\n\thwmon_power_average_interval_min = 4,\n\thwmon_power_average_highest = 5,\n\thwmon_power_average_lowest = 6,\n\thwmon_power_average_max = 7,\n\thwmon_power_average_min = 8,\n\thwmon_power_input = 9,\n\thwmon_power_input_highest = 10,\n\thwmon_power_input_lowest = 11,\n\thwmon_power_reset_history = 12,\n\thwmon_power_accuracy = 13,\n\thwmon_power_cap = 14,\n\thwmon_power_cap_hyst = 15,\n\thwmon_power_cap_max = 16,\n\thwmon_power_cap_min = 17,\n\thwmon_power_min = 18,\n\thwmon_power_max = 19,\n\thwmon_power_crit = 20,\n\thwmon_power_lcrit = 21,\n\thwmon_power_label = 22,\n\thwmon_power_alarm = 23,\n\thwmon_power_cap_alarm = 24,\n\thwmon_power_min_alarm = 25,\n\thwmon_power_max_alarm = 26,\n\thwmon_power_lcrit_alarm = 27,\n\thwmon_power_crit_alarm = 28,\n\thwmon_power_rated_min = 29,\n\thwmon_power_rated_max = 30,\n};\n\nenum hwmon_pwm_attributes {\n\thwmon_pwm_input = 0,\n\thwmon_pwm_enable = 1,\n\thwmon_pwm_mode = 2,\n\thwmon_pwm_freq = 3,\n\thwmon_pwm_auto_channels_temp = 4,\n};\n\nenum hwmon_sensor_types {\n\thwmon_chip = 0,\n\thwmon_temp = 1,\n\thwmon_in = 2,\n\thwmon_curr = 3,\n\thwmon_power = 4,\n\thwmon_energy = 5,\n\thwmon_energy64 = 6,\n\thwmon_humidity = 7,\n\thwmon_fan = 8,\n\thwmon_pwm = 9,\n\thwmon_intrusion = 10,\n\thwmon_max = 11,\n};\n\nenum hwmon_temp_attributes {\n\thwmon_temp_enable = 0,\n\thwmon_temp_input = 1,\n\thwmon_temp_type = 2,\n\thwmon_temp_lcrit = 3,\n\thwmon_temp_lcrit_hyst = 4,\n\thwmon_temp_min = 5,\n\thwmon_temp_min_hyst = 6,\n\thwmon_temp_max = 7,\n\thwmon_temp_max_hyst = 8,\n\thwmon_temp_crit = 9,\n\thwmon_temp_crit_hyst = 10,\n\thwmon_temp_emergency = 11,\n\thwmon_temp_emergency_hyst = 12,\n\thwmon_temp_alarm = 13,\n\thwmon_temp_lcrit_alarm = 14,\n\thwmon_temp_min_alarm = 15,\n\thwmon_temp_max_alarm = 16,\n\thwmon_temp_crit_alarm = 17,\n\thwmon_temp_emergency_alarm = 18,\n\thwmon_temp_fault = 19,\n\thwmon_temp_offset = 20,\n\thwmon_temp_label = 21,\n\thwmon_temp_lowest = 22,\n\thwmon_temp_highest = 23,\n\thwmon_temp_reset_history = 24,\n\thwmon_temp_rated_min = 25,\n\thwmon_temp_rated_max = 26,\n\thwmon_temp_beep = 27,\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nenum i2c_chip_type {\n\tSLB9635 = 0,\n\tSLB9645 = 1,\n\tUNKNOWN = 2,\n};\n\nenum i2c_driver_flags {\n\tI2C_DRV_ACPI_WAIVE_D0_PROBE = 1,\n};\n\nenum i2c_mt65xx_clks {\n\tI2C_MT65XX_CLK_MAIN = 0,\n\tI2C_MT65XX_CLK_DMA = 1,\n\tI2C_MT65XX_CLK_PMIC = 2,\n\tI2C_MT65XX_CLK_ARB = 3,\n\tI2C_MT65XX_CLK_MAX = 4,\n};\n\nenum i2c_slave_event {\n\tI2C_SLAVE_READ_REQUESTED = 0,\n\tI2C_SLAVE_WRITE_REQUESTED = 1,\n\tI2C_SLAVE_READ_PROCESSED = 2,\n\tI2C_SLAVE_WRITE_RECEIVED = 3,\n\tI2C_SLAVE_STOP = 4,\n};\n\nenum i2c_slave_read_status {\n\tI2C_SLAVE_RX_FIFO_EMPTY = 0,\n\tI2C_SLAVE_RX_START = 1,\n\tI2C_SLAVE_RX_DATA = 2,\n\tI2C_SLAVE_RX_END = 3,\n};\n\nenum i2c_type_exynos {\n\tI2C_TYPE_EXYNOS5 = 0,\n\tI2C_TYPE_EXYNOS7 = 1,\n\tI2C_TYPE_EXYNOSAUTOV9 = 2,\n\tI2C_TYPE_EXYNOS8895 = 3,\n};\n\nenum ib_atomic_cap {\n\tIB_ATOMIC_NONE = 0,\n\tIB_ATOMIC_HCA = 1,\n\tIB_ATOMIC_GLOB = 2,\n};\n\nenum ib_cq_notify_flags {\n\tIB_CQ_SOLICITED = 1,\n\tIB_CQ_NEXT_COMP = 2,\n\tIB_CQ_SOLICITED_MASK = 3,\n\tIB_CQ_REPORT_MISSED_EVENTS = 4,\n};\n\nenum ib_event_type {\n\tIB_EVENT_CQ_ERR = 0,\n\tIB_EVENT_QP_FATAL = 1,\n\tIB_EVENT_QP_REQ_ERR = 2,\n\tIB_EVENT_QP_ACCESS_ERR = 3,\n\tIB_EVENT_COMM_EST = 4,\n\tIB_EVENT_SQ_DRAINED = 5,\n\tIB_EVENT_PATH_MIG = 6,\n\tIB_EVENT_PATH_MIG_ERR = 7,\n\tIB_EVENT_DEVICE_FATAL = 8,\n\tIB_EVENT_PORT_ACTIVE = 9,\n\tIB_EVENT_PORT_ERR = 10,\n\tIB_EVENT_LID_CHANGE = 11,\n\tIB_EVENT_PKEY_CHANGE = 12,\n\tIB_EVENT_SM_CHANGE = 13,\n\tIB_EVENT_SRQ_ERR = 14,\n\tIB_EVENT_SRQ_LIMIT_REACHED = 15,\n\tIB_EVENT_QP_LAST_WQE_REACHED = 16,\n\tIB_EVENT_CLIENT_REREGISTER = 17,\n\tIB_EVENT_GID_CHANGE = 18,\n\tIB_EVENT_WQ_FATAL = 19,\n\tIB_EVENT_DEVICE_SPEED_CHANGE = 20,\n};\n\nenum ib_flow_action_type {\n\tIB_FLOW_ACTION_UNSPECIFIED = 0,\n\tIB_FLOW_ACTION_ESP = 1,\n};\n\nenum ib_flow_attr_type {\n\tIB_FLOW_ATTR_NORMAL = 0,\n\tIB_FLOW_ATTR_ALL_DEFAULT = 1,\n\tIB_FLOW_ATTR_MC_DEFAULT = 2,\n\tIB_FLOW_ATTR_SNIFFER = 3,\n};\n\nenum ib_flow_spec_type {\n\tIB_FLOW_SPEC_ETH = 32,\n\tIB_FLOW_SPEC_IB = 34,\n\tIB_FLOW_SPEC_IPV4 = 48,\n\tIB_FLOW_SPEC_IPV6 = 49,\n\tIB_FLOW_SPEC_ESP = 52,\n\tIB_FLOW_SPEC_TCP = 64,\n\tIB_FLOW_SPEC_UDP = 65,\n\tIB_FLOW_SPEC_VXLAN_TUNNEL = 80,\n\tIB_FLOW_SPEC_GRE = 81,\n\tIB_FLOW_SPEC_MPLS = 96,\n\tIB_FLOW_SPEC_INNER = 256,\n\tIB_FLOW_SPEC_ACTION_TAG = 4096,\n\tIB_FLOW_SPEC_ACTION_DROP = 4097,\n\tIB_FLOW_SPEC_ACTION_HANDLE = 4098,\n\tIB_FLOW_SPEC_ACTION_COUNT = 4099,\n};\n\nenum ib_gid_type {\n\tIB_GID_TYPE_IB = 0,\n\tIB_GID_TYPE_ROCE = 1,\n\tIB_GID_TYPE_ROCE_UDP_ENCAP = 2,\n\tIB_GID_TYPE_SIZE = 3,\n};\n\nenum ib_mig_state {\n\tIB_MIG_MIGRATED = 0,\n\tIB_MIG_REARM = 1,\n\tIB_MIG_ARMED = 2,\n};\n\nenum ib_mr_type {\n\tIB_MR_TYPE_MEM_REG = 0,\n\tIB_MR_TYPE_SG_GAPS = 1,\n\tIB_MR_TYPE_DM = 2,\n\tIB_MR_TYPE_USER = 3,\n\tIB_MR_TYPE_DMA = 4,\n\tIB_MR_TYPE_INTEGRITY = 5,\n};\n\nenum ib_mtu {\n\tIB_MTU_256 = 1,\n\tIB_MTU_512 = 2,\n\tIB_MTU_1024 = 3,\n\tIB_MTU_2048 = 4,\n\tIB_MTU_4096 = 5,\n};\n\nenum ib_mw_type {\n\tIB_MW_TYPE_1 = 1,\n\tIB_MW_TYPE_2 = 2,\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nenum ib_port_state {\n\tIB_PORT_NOP = 0,\n\tIB_PORT_DOWN = 1,\n\tIB_PORT_INIT = 2,\n\tIB_PORT_ARMED = 3,\n\tIB_PORT_ACTIVE = 4,\n\tIB_PORT_ACTIVE_DEFER = 5,\n};\n\nenum ib_qp_state {\n\tIB_QPS_RESET = 0,\n\tIB_QPS_INIT = 1,\n\tIB_QPS_RTR = 2,\n\tIB_QPS_RTS = 3,\n\tIB_QPS_SQD = 4,\n\tIB_QPS_SQE = 5,\n\tIB_QPS_ERR = 6,\n};\n\nenum ib_qp_type {\n\tIB_QPT_SMI = 0,\n\tIB_QPT_GSI = 1,\n\tIB_QPT_RC = 2,\n\tIB_QPT_UC = 3,\n\tIB_QPT_UD = 4,\n\tIB_QPT_RAW_IPV6 = 5,\n\tIB_QPT_RAW_ETHERTYPE = 6,\n\tIB_QPT_RAW_PACKET = 8,\n\tIB_QPT_XRC_INI = 9,\n\tIB_QPT_XRC_TGT = 10,\n\tIB_QPT_MAX = 11,\n\tIB_QPT_DRIVER = 255,\n\tIB_QPT_RESERVED1 = 4096,\n\tIB_QPT_RESERVED2 = 4097,\n\tIB_QPT_RESERVED3 = 4098,\n\tIB_QPT_RESERVED4 = 4099,\n\tIB_QPT_RESERVED5 = 4100,\n\tIB_QPT_RESERVED6 = 4101,\n\tIB_QPT_RESERVED7 = 4102,\n\tIB_QPT_RESERVED8 = 4103,\n\tIB_QPT_RESERVED9 = 4104,\n\tIB_QPT_RESERVED10 = 4105,\n};\n\nenum ib_sig_err_type {\n\tIB_SIG_BAD_GUARD = 0,\n\tIB_SIG_BAD_REFTAG = 1,\n\tIB_SIG_BAD_APPTAG = 2,\n};\n\nenum ib_sig_type {\n\tIB_SIGNAL_ALL_WR = 0,\n\tIB_SIGNAL_REQ_WR = 1,\n};\n\nenum ib_signature_type {\n\tIB_SIG_TYPE_NONE = 0,\n\tIB_SIG_TYPE_T10_DIF = 1,\n};\n\nenum ib_srq_attr_mask {\n\tIB_SRQ_MAX_WR = 1,\n\tIB_SRQ_LIMIT = 2,\n};\n\nenum ib_srq_type {\n\tIB_SRQT_BASIC = 0,\n\tIB_SRQT_XRC = 1,\n\tIB_SRQT_TM = 2,\n};\n\nenum ib_t10_dif_bg_type {\n\tIB_T10DIF_CRC = 0,\n\tIB_T10DIF_CSUM = 1,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_FLUSH_GLOBAL = 256,\n\tIB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_advise_mr_advice {\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2,\n};\n\nenum ib_uverbs_device_cap_flags {\n\tIB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL,\n\tIB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL,\n\tIB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL,\n\tIB_UVERBS_DEVICE_RAW_MULTI = 8ULL,\n\tIB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL,\n\tIB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL,\n\tIB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL,\n\tIB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL,\n\tIB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL,\n\tIB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL,\n\tIB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL,\n\tIB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL,\n\tIB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL,\n\tIB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL,\n\tIB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL,\n\tIB_UVERBS_DEVICE_XRC = 1048576ULL,\n\tIB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL,\n\tIB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL,\n\tIB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL,\n\tIB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL,\n\tIB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL,\n\tIB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL,\n\tIB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL,\n\tIB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL,\n\tIB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL,\n};\n\nenum ib_uverbs_gid_type {\n\tIB_UVERBS_GID_TYPE_IB = 0,\n\tIB_UVERBS_GID_TYPE_ROCE_V1 = 1,\n\tIB_UVERBS_GID_TYPE_ROCE_V2 = 2,\n};\n\nenum ib_uverbs_odp_general_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT = 1,\n\tIB_UVERBS_ODP_SUPPORT_IMPLICIT = 2,\n};\n\nenum ib_uverbs_odp_transport_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT_SEND = 1,\n\tIB_UVERBS_ODP_SUPPORT_RECV = 2,\n\tIB_UVERBS_ODP_SUPPORT_WRITE = 4,\n\tIB_UVERBS_ODP_SUPPORT_READ = 8,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC = 16,\n\tIB_UVERBS_ODP_SUPPORT_SRQ_RECV = 32,\n\tIB_UVERBS_ODP_SUPPORT_FLUSH = 64,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 128,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_raw_packet_caps {\n\tIB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2,\n\tIB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4,\n\tIB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wc_opcode {\n\tIB_UVERBS_WC_SEND = 0,\n\tIB_UVERBS_WC_RDMA_WRITE = 1,\n\tIB_UVERBS_WC_RDMA_READ = 2,\n\tIB_UVERBS_WC_COMP_SWAP = 3,\n\tIB_UVERBS_WC_FETCH_ADD = 4,\n\tIB_UVERBS_WC_BIND_MW = 5,\n\tIB_UVERBS_WC_LOCAL_INV = 6,\n\tIB_UVERBS_WC_TSO = 7,\n\tIB_UVERBS_WC_FLUSH = 8,\n\tIB_UVERBS_WC_ATOMIC_WRITE = 9,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_UVERBS_WR_FLUSH = 14,\n\tIB_UVERBS_WR_ATOMIC_WRITE = 15,\n};\n\nenum ib_wc_opcode {\n\tIB_WC_SEND = 0,\n\tIB_WC_RDMA_WRITE = 1,\n\tIB_WC_RDMA_READ = 2,\n\tIB_WC_COMP_SWAP = 3,\n\tIB_WC_FETCH_ADD = 4,\n\tIB_WC_BIND_MW = 5,\n\tIB_WC_LOCAL_INV = 6,\n\tIB_WC_LSO = 7,\n\tIB_WC_ATOMIC_WRITE = 9,\n\tIB_WC_REG_MR = 10,\n\tIB_WC_MASKED_COMP_SWAP = 11,\n\tIB_WC_MASKED_FETCH_ADD = 12,\n\tIB_WC_FLUSH = 8,\n\tIB_WC_RECV = 128,\n\tIB_WC_RECV_RDMA_WITH_IMM = 129,\n};\n\nenum ib_wc_status {\n\tIB_WC_SUCCESS = 0,\n\tIB_WC_LOC_LEN_ERR = 1,\n\tIB_WC_LOC_QP_OP_ERR = 2,\n\tIB_WC_LOC_EEC_OP_ERR = 3,\n\tIB_WC_LOC_PROT_ERR = 4,\n\tIB_WC_WR_FLUSH_ERR = 5,\n\tIB_WC_MW_BIND_ERR = 6,\n\tIB_WC_BAD_RESP_ERR = 7,\n\tIB_WC_LOC_ACCESS_ERR = 8,\n\tIB_WC_REM_INV_REQ_ERR = 9,\n\tIB_WC_REM_ACCESS_ERR = 10,\n\tIB_WC_REM_OP_ERR = 11,\n\tIB_WC_RETRY_EXC_ERR = 12,\n\tIB_WC_RNR_RETRY_EXC_ERR = 13,\n\tIB_WC_LOC_RDD_VIOL_ERR = 14,\n\tIB_WC_REM_INV_RD_REQ_ERR = 15,\n\tIB_WC_REM_ABORT_ERR = 16,\n\tIB_WC_INV_EECN_ERR = 17,\n\tIB_WC_INV_EEC_STATE_ERR = 18,\n\tIB_WC_FATAL_ERR = 19,\n\tIB_WC_RESP_TIMEOUT_ERR = 20,\n\tIB_WC_GENERAL_ERR = 21,\n};\n\nenum ib_wq_state {\n\tIB_WQS_RESET = 0,\n\tIB_WQS_RDY = 1,\n\tIB_WQS_ERR = 2,\n};\n\nenum ib_wq_type {\n\tIB_WQT_RQ = 0,\n};\n\nenum ib_wr_opcode {\n\tIB_WR_RDMA_WRITE = 0,\n\tIB_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_WR_SEND = 2,\n\tIB_WR_SEND_WITH_IMM = 3,\n\tIB_WR_RDMA_READ = 4,\n\tIB_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_WR_BIND_MW = 8,\n\tIB_WR_LSO = 10,\n\tIB_WR_SEND_WITH_INV = 9,\n\tIB_WR_RDMA_READ_WITH_INV = 11,\n\tIB_WR_LOCAL_INV = 7,\n\tIB_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_WR_FLUSH = 14,\n\tIB_WR_ATOMIC_WRITE = 15,\n\tIB_WR_REG_MR = 32,\n\tIB_WR_REG_MR_INTEGRITY = 33,\n\tIB_WR_RESERVED1 = 240,\n\tIB_WR_RESERVED2 = 241,\n\tIB_WR_RESERVED3 = 242,\n\tIB_WR_RESERVED4 = 243,\n\tIB_WR_RESERVED5 = 244,\n\tIB_WR_RESERVED6 = 245,\n\tIB_WR_RESERVED7 = 246,\n\tIB_WR_RESERVED8 = 247,\n\tIB_WR_RESERVED9 = 248,\n\tIB_WR_RESERVED10 = 249,\n};\n\nenum ifc_nand_fir_opcodes {\n\tIFC_FIR_OP_NOP = 0,\n\tIFC_FIR_OP_CA0 = 1,\n\tIFC_FIR_OP_CA1 = 2,\n\tIFC_FIR_OP_CA2 = 3,\n\tIFC_FIR_OP_CA3 = 4,\n\tIFC_FIR_OP_RA0 = 5,\n\tIFC_FIR_OP_RA1 = 6,\n\tIFC_FIR_OP_RA2 = 7,\n\tIFC_FIR_OP_RA3 = 8,\n\tIFC_FIR_OP_CMD0 = 9,\n\tIFC_FIR_OP_CMD1 = 10,\n\tIFC_FIR_OP_CMD2 = 11,\n\tIFC_FIR_OP_CMD3 = 12,\n\tIFC_FIR_OP_CMD4 = 13,\n\tIFC_FIR_OP_CMD5 = 14,\n\tIFC_FIR_OP_CMD6 = 15,\n\tIFC_FIR_OP_CMD7 = 16,\n\tIFC_FIR_OP_CW0 = 17,\n\tIFC_FIR_OP_CW1 = 18,\n\tIFC_FIR_OP_CW2 = 19,\n\tIFC_FIR_OP_CW3 = 20,\n\tIFC_FIR_OP_CW4 = 21,\n\tIFC_FIR_OP_CW5 = 22,\n\tIFC_FIR_OP_CW6 = 23,\n\tIFC_FIR_OP_CW7 = 24,\n\tIFC_FIR_OP_WBCD = 25,\n\tIFC_FIR_OP_RBCD = 26,\n\tIFC_FIR_OP_BTRD = 27,\n\tIFC_FIR_OP_RDSTAT = 28,\n\tIFC_FIR_OP_NWAIT = 29,\n\tIFC_FIR_OP_WFR = 30,\n\tIFC_FIR_OP_SBRD = 31,\n\tIFC_FIR_OP_UA = 32,\n\tIFC_FIR_OP_RB = 33,\n};\n\nenum igb_boards {\n\tboard_82575 = 0,\n};\n\nenum igb_diagnostics_results {\n\tTEST_REG = 0,\n\tTEST_EEP = 1,\n\tTEST_IRQ = 2,\n\tTEST_LOOP = 3,\n\tTEST_LINK = 4,\n};\n\nenum igb_filter_match_flags {\n\tIGB_FILTER_FLAG_ETHER_TYPE = 1,\n\tIGB_FILTER_FLAG_VLAN_TCI = 2,\n\tIGB_FILTER_FLAG_SRC_MAC_ADDR = 4,\n\tIGB_FILTER_FLAG_DST_MAC_ADDR = 8,\n};\n\nenum igb_tx_buf_type {\n\tIGB_TYPE_SKB = 0,\n\tIGB_TYPE_XDP = 1,\n\tIGB_TYPE_XSK = 2,\n};\n\nenum igb_tx_flags {\n\tIGB_TX_FLAGS_VLAN = 1,\n\tIGB_TX_FLAGS_TSO = 2,\n\tIGB_TX_FLAGS_TSTAMP = 4,\n\tIGB_TX_FLAGS_IPV4 = 16,\n\tIGB_TX_FLAGS_CSUM = 32,\n};\n\nenum igbvf_boards {\n\tboard_vf = 0,\n\tboard_i350_vf = 1,\n};\n\nenum igbvf_state_t {\n\t__IGBVF_TESTING = 0,\n\t__IGBVF_RESETTING = 1,\n\t__IGBVF_DOWN = 2,\n};\n\nenum iio_available_type {\n\tIIO_AVAIL_LIST = 0,\n\tIIO_AVAIL_RANGE = 1,\n};\n\nenum iio_buffer_direction {\n\tIIO_BUFFER_DIRECTION_IN = 0,\n\tIIO_BUFFER_DIRECTION_OUT = 1,\n};\n\nenum iio_chan_info_enum {\n\tIIO_CHAN_INFO_RAW = 0,\n\tIIO_CHAN_INFO_PROCESSED = 1,\n\tIIO_CHAN_INFO_SCALE = 2,\n\tIIO_CHAN_INFO_OFFSET = 3,\n\tIIO_CHAN_INFO_CALIBSCALE = 4,\n\tIIO_CHAN_INFO_CALIBBIAS = 5,\n\tIIO_CHAN_INFO_PEAK = 6,\n\tIIO_CHAN_INFO_PEAK_SCALE = 7,\n\tIIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW = 8,\n\tIIO_CHAN_INFO_AVERAGE_RAW = 9,\n\tIIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY = 10,\n\tIIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY = 11,\n\tIIO_CHAN_INFO_SAMP_FREQ = 12,\n\tIIO_CHAN_INFO_FREQUENCY = 13,\n\tIIO_CHAN_INFO_PHASE = 14,\n\tIIO_CHAN_INFO_HARDWAREGAIN = 15,\n\tIIO_CHAN_INFO_HYSTERESIS = 16,\n\tIIO_CHAN_INFO_HYSTERESIS_RELATIVE = 17,\n\tIIO_CHAN_INFO_INT_TIME = 18,\n\tIIO_CHAN_INFO_ENABLE = 19,\n\tIIO_CHAN_INFO_CALIBHEIGHT = 20,\n\tIIO_CHAN_INFO_CALIBWEIGHT = 21,\n\tIIO_CHAN_INFO_DEBOUNCE_COUNT = 22,\n\tIIO_CHAN_INFO_DEBOUNCE_TIME = 23,\n\tIIO_CHAN_INFO_CALIBEMISSIVITY = 24,\n\tIIO_CHAN_INFO_OVERSAMPLING_RATIO = 25,\n\tIIO_CHAN_INFO_THERMOCOUPLE_TYPE = 26,\n\tIIO_CHAN_INFO_CALIBAMBIENT = 27,\n\tIIO_CHAN_INFO_ZEROPOINT = 28,\n\tIIO_CHAN_INFO_TROUGH = 29,\n\tIIO_CHAN_INFO_CONVDELAY = 30,\n\tIIO_CHAN_INFO_POWERFACTOR = 31,\n};\n\nenum iio_chan_type {\n\tIIO_VOLTAGE = 0,\n\tIIO_CURRENT = 1,\n\tIIO_POWER = 2,\n\tIIO_ACCEL = 3,\n\tIIO_ANGL_VEL = 4,\n\tIIO_MAGN = 5,\n\tIIO_LIGHT = 6,\n\tIIO_INTENSITY = 7,\n\tIIO_PROXIMITY = 8,\n\tIIO_TEMP = 9,\n\tIIO_INCLI = 10,\n\tIIO_ROT = 11,\n\tIIO_ANGL = 12,\n\tIIO_TIMESTAMP = 13,\n\tIIO_CAPACITANCE = 14,\n\tIIO_ALTVOLTAGE = 15,\n\tIIO_CCT = 16,\n\tIIO_PRESSURE = 17,\n\tIIO_HUMIDITYRELATIVE = 18,\n\tIIO_ACTIVITY = 19,\n\tIIO_STEPS = 20,\n\tIIO_ENERGY = 21,\n\tIIO_DISTANCE = 22,\n\tIIO_VELOCITY = 23,\n\tIIO_CONCENTRATION = 24,\n\tIIO_RESISTANCE = 25,\n\tIIO_PH = 26,\n\tIIO_UVINDEX = 27,\n\tIIO_ELECTRICALCONDUCTIVITY = 28,\n\tIIO_COUNT = 29,\n\tIIO_INDEX = 30,\n\tIIO_GRAVITY = 31,\n\tIIO_POSITIONRELATIVE = 32,\n\tIIO_PHASE = 33,\n\tIIO_MASSCONCENTRATION = 34,\n\tIIO_DELTA_ANGL = 35,\n\tIIO_DELTA_VELOCITY = 36,\n\tIIO_COLORTEMP = 37,\n\tIIO_CHROMATICITY = 38,\n\tIIO_ATTENTION = 39,\n\tIIO_ALTCURRENT = 40,\n};\n\nenum iio_endian {\n\tIIO_CPU = 0,\n\tIIO_BE = 1,\n\tIIO_LE = 2,\n};\n\nenum iio_event_direction {\n\tIIO_EV_DIR_EITHER = 0,\n\tIIO_EV_DIR_RISING = 1,\n\tIIO_EV_DIR_FALLING = 2,\n\tIIO_EV_DIR_NONE = 3,\n\tIIO_EV_DIR_SINGLETAP = 4,\n\tIIO_EV_DIR_DOUBLETAP = 5,\n\tIIO_EV_DIR_FAULT_OPENWIRE = 6,\n};\n\nenum iio_event_info {\n\tIIO_EV_INFO_ENABLE = 0,\n\tIIO_EV_INFO_VALUE = 1,\n\tIIO_EV_INFO_HYSTERESIS = 2,\n\tIIO_EV_INFO_PERIOD = 3,\n\tIIO_EV_INFO_HIGH_PASS_FILTER_3DB = 4,\n\tIIO_EV_INFO_LOW_PASS_FILTER_3DB = 5,\n\tIIO_EV_INFO_TIMEOUT = 6,\n\tIIO_EV_INFO_RESET_TIMEOUT = 7,\n\tIIO_EV_INFO_TAP2_MIN_DELAY = 8,\n\tIIO_EV_INFO_RUNNING_PERIOD = 9,\n\tIIO_EV_INFO_RUNNING_COUNT = 10,\n};\n\nenum iio_event_type {\n\tIIO_EV_TYPE_THRESH = 0,\n\tIIO_EV_TYPE_MAG = 1,\n\tIIO_EV_TYPE_ROC = 2,\n\tIIO_EV_TYPE_THRESH_ADAPTIVE = 3,\n\tIIO_EV_TYPE_MAG_ADAPTIVE = 4,\n\tIIO_EV_TYPE_CHANGE = 5,\n\tIIO_EV_TYPE_MAG_REFERENCED = 6,\n\tIIO_EV_TYPE_GESTURE = 7,\n\tIIO_EV_TYPE_FAULT = 8,\n};\n\nenum iio_modifier {\n\tIIO_NO_MOD = 0,\n\tIIO_MOD_X = 1,\n\tIIO_MOD_Y = 2,\n\tIIO_MOD_Z = 3,\n\tIIO_MOD_X_AND_Y = 4,\n\tIIO_MOD_X_AND_Z = 5,\n\tIIO_MOD_Y_AND_Z = 6,\n\tIIO_MOD_X_AND_Y_AND_Z = 7,\n\tIIO_MOD_X_OR_Y = 8,\n\tIIO_MOD_X_OR_Z = 9,\n\tIIO_MOD_Y_OR_Z = 10,\n\tIIO_MOD_X_OR_Y_OR_Z = 11,\n\tIIO_MOD_LIGHT_BOTH = 12,\n\tIIO_MOD_LIGHT_IR = 13,\n\tIIO_MOD_ROOT_SUM_SQUARED_X_Y = 14,\n\tIIO_MOD_SUM_SQUARED_X_Y_Z = 15,\n\tIIO_MOD_LIGHT_CLEAR = 16,\n\tIIO_MOD_LIGHT_RED = 17,\n\tIIO_MOD_LIGHT_GREEN = 18,\n\tIIO_MOD_LIGHT_BLUE = 19,\n\tIIO_MOD_QUATERNION = 20,\n\tIIO_MOD_TEMP_AMBIENT = 21,\n\tIIO_MOD_TEMP_OBJECT = 22,\n\tIIO_MOD_NORTH_MAGN = 23,\n\tIIO_MOD_NORTH_TRUE = 24,\n\tIIO_MOD_NORTH_MAGN_TILT_COMP = 25,\n\tIIO_MOD_NORTH_TRUE_TILT_COMP = 26,\n\tIIO_MOD_RUNNING = 27,\n\tIIO_MOD_JOGGING = 28,\n\tIIO_MOD_WALKING = 29,\n\tIIO_MOD_STILL = 30,\n\tIIO_MOD_ROOT_SUM_SQUARED_X_Y_Z = 31,\n\tIIO_MOD_I = 32,\n\tIIO_MOD_Q = 33,\n\tIIO_MOD_CO2 = 34,\n\tIIO_MOD_VOC = 35,\n\tIIO_MOD_LIGHT_UV = 36,\n\tIIO_MOD_LIGHT_DUV = 37,\n\tIIO_MOD_PM1 = 38,\n\tIIO_MOD_PM2P5 = 39,\n\tIIO_MOD_PM4 = 40,\n\tIIO_MOD_PM10 = 41,\n\tIIO_MOD_ETHANOL = 42,\n\tIIO_MOD_H2 = 43,\n\tIIO_MOD_O2 = 44,\n\tIIO_MOD_LINEAR_X = 45,\n\tIIO_MOD_LINEAR_Y = 46,\n\tIIO_MOD_LINEAR_Z = 47,\n\tIIO_MOD_PITCH = 48,\n\tIIO_MOD_YAW = 49,\n\tIIO_MOD_ROLL = 50,\n\tIIO_MOD_LIGHT_UVA = 51,\n\tIIO_MOD_LIGHT_UVB = 52,\n\tIIO_MOD_RMS = 53,\n\tIIO_MOD_ACTIVE = 54,\n\tIIO_MOD_REACTIVE = 55,\n\tIIO_MOD_APPARENT = 56,\n};\n\nenum iio_shared_by {\n\tIIO_SEPARATE = 0,\n\tIIO_SHARED_BY_TYPE = 1,\n\tIIO_SHARED_BY_DIR = 2,\n\tIIO_SHARED_BY_ALL = 3,\n};\n\nenum imx7_src_registers {\n\tSRC_A7RCR0 = 4,\n\tSRC_M4RCR = 12,\n\tSRC_ERCR = 20,\n\tSRC_HSICPHY_RCR = 28,\n\tSRC_USBOPHY1_RCR = 32,\n\tSRC_USBOPHY2_RCR = 36,\n\tSRC_MIPIPHY_RCR = 40,\n\tSRC_PCIEPHY_RCR = 44,\n\tSRC_DDRC_RCR = 4096,\n};\n\nenum imx8_pcie_phy_type {\n\tIMX8MM = 0,\n\tIMX8MP = 1,\n};\n\nenum imx8mm_pads {\n\tMX8MM_PAD_RESERVE0 = 0,\n\tMX8MM_PAD_RESERVE1 = 1,\n\tMX8MM_PAD_RESERVE2 = 2,\n\tMX8MM_PAD_RESERVE3 = 3,\n\tMX8MM_PAD_RESERVE4 = 4,\n\tMX8MM_PAD_RESERVE5 = 5,\n\tMX8MM_PAD_RESERVE6 = 6,\n\tMX8MM_PAD_RESERVE7 = 7,\n\tMX8MM_PAD_RESERVE8 = 8,\n\tMX8MM_PAD_RESERVE9 = 9,\n\tMX8MM_IOMUXC_GPIO1_IO00 = 10,\n\tMX8MM_IOMUXC_GPIO1_IO01 = 11,\n\tMX8MM_IOMUXC_GPIO1_IO02 = 12,\n\tMX8MM_IOMUXC_GPIO1_IO03 = 13,\n\tMX8MM_IOMUXC_GPIO1_IO04 = 14,\n\tMX8MM_IOMUXC_GPIO1_IO05 = 15,\n\tMX8MM_IOMUXC_GPIO1_IO06 = 16,\n\tMX8MM_IOMUXC_GPIO1_IO07 = 17,\n\tMX8MM_IOMUXC_GPIO1_IO08 = 18,\n\tMX8MM_IOMUXC_GPIO1_IO09 = 19,\n\tMX8MM_IOMUXC_GPIO1_IO10 = 20,\n\tMX8MM_IOMUXC_GPIO1_IO11 = 21,\n\tMX8MM_IOMUXC_GPIO1_IO12 = 22,\n\tMX8MM_IOMUXC_GPIO1_IO13 = 23,\n\tMX8MM_IOMUXC_GPIO1_IO14 = 24,\n\tMX8MM_IOMUXC_GPIO1_IO15 = 25,\n\tMX8MM_IOMUXC_ENET_MDC = 26,\n\tMX8MM_IOMUXC_ENET_MDIO = 27,\n\tMX8MM_IOMUXC_ENET_TD3 = 28,\n\tMX8MM_IOMUXC_ENET_TD2 = 29,\n\tMX8MM_IOMUXC_ENET_TD1 = 30,\n\tMX8MM_IOMUXC_ENET_TD0 = 31,\n\tMX8MM_IOMUXC_ENET_TX_CTL = 32,\n\tMX8MM_IOMUXC_ENET_TXC = 33,\n\tMX8MM_IOMUXC_ENET_RX_CTL = 34,\n\tMX8MM_IOMUXC_ENET_RXC = 35,\n\tMX8MM_IOMUXC_ENET_RD0 = 36,\n\tMX8MM_IOMUXC_ENET_RD1 = 37,\n\tMX8MM_IOMUXC_ENET_RD2 = 38,\n\tMX8MM_IOMUXC_ENET_RD3 = 39,\n\tMX8MM_IOMUXC_SD1_CLK = 40,\n\tMX8MM_IOMUXC_SD1_CMD = 41,\n\tMX8MM_IOMUXC_SD1_DATA0 = 42,\n\tMX8MM_IOMUXC_SD1_DATA1 = 43,\n\tMX8MM_IOMUXC_SD1_DATA2 = 44,\n\tMX8MM_IOMUXC_SD1_DATA3 = 45,\n\tMX8MM_IOMUXC_SD1_DATA4 = 46,\n\tMX8MM_IOMUXC_SD1_DATA5 = 47,\n\tMX8MM_IOMUXC_SD1_DATA6 = 48,\n\tMX8MM_IOMUXC_SD1_DATA7 = 49,\n\tMX8MM_IOMUXC_SD1_RESET_B = 50,\n\tMX8MM_IOMUXC_SD1_STROBE = 51,\n\tMX8MM_IOMUXC_SD2_CD_B = 52,\n\tMX8MM_IOMUXC_SD2_CLK = 53,\n\tMX8MM_IOMUXC_SD2_CMD = 54,\n\tMX8MM_IOMUXC_SD2_DATA0 = 55,\n\tMX8MM_IOMUXC_SD2_DATA1 = 56,\n\tMX8MM_IOMUXC_SD2_DATA2 = 57,\n\tMX8MM_IOMUXC_SD2_DATA3 = 58,\n\tMX8MM_IOMUXC_SD2_RESET_B = 59,\n\tMX8MM_IOMUXC_SD2_WP = 60,\n\tMX8MM_IOMUXC_NAND_ALE = 61,\n\tMX8MM_IOMUXC_NAND_CE0 = 62,\n\tMX8MM_IOMUXC_NAND_CE1 = 63,\n\tMX8MM_IOMUXC_NAND_CE2 = 64,\n\tMX8MM_IOMUXC_NAND_CE3 = 65,\n\tMX8MM_IOMUXC_NAND_CLE = 66,\n\tMX8MM_IOMUXC_NAND_DATA00 = 67,\n\tMX8MM_IOMUXC_NAND_DATA01 = 68,\n\tMX8MM_IOMUXC_NAND_DATA02 = 69,\n\tMX8MM_IOMUXC_NAND_DATA03 = 70,\n\tMX8MM_IOMUXC_NAND_DATA04 = 71,\n\tMX8MM_IOMUXC_NAND_DATA05 = 72,\n\tMX8MM_IOMUXC_NAND_DATA06 = 73,\n\tMX8MM_IOMUXC_NAND_DATA07 = 74,\n\tMX8MM_IOMUXC_NAND_DQS = 75,\n\tMX8MM_IOMUXC_NAND_RE_B = 76,\n\tMX8MM_IOMUXC_NAND_READY_B = 77,\n\tMX8MM_IOMUXC_NAND_WE_B = 78,\n\tMX8MM_IOMUXC_NAND_WP_B = 79,\n\tMX8MM_IOMUXC_SAI5_RXFS = 80,\n\tMX8MM_IOMUXC_SAI5_RXC = 81,\n\tMX8MM_IOMUXC_SAI5_RXD0 = 82,\n\tMX8MM_IOMUXC_SAI5_RXD1 = 83,\n\tMX8MM_IOMUXC_SAI5_RXD2 = 84,\n\tMX8MM_IOMUXC_SAI5_RXD3 = 85,\n\tMX8MM_IOMUXC_SAI5_MCLK = 86,\n\tMX8MM_IOMUXC_SAI1_RXFS = 87,\n\tMX8MM_IOMUXC_SAI1_RXC = 88,\n\tMX8MM_IOMUXC_SAI1_RXD0 = 89,\n\tMX8MM_IOMUXC_SAI1_RXD1 = 90,\n\tMX8MM_IOMUXC_SAI1_RXD2 = 91,\n\tMX8MM_IOMUXC_SAI1_RXD3 = 92,\n\tMX8MM_IOMUXC_SAI1_RXD4 = 93,\n\tMX8MM_IOMUXC_SAI1_RXD5 = 94,\n\tMX8MM_IOMUXC_SAI1_RXD6 = 95,\n\tMX8MM_IOMUXC_SAI1_RXD7 = 96,\n\tMX8MM_IOMUXC_SAI1_TXFS = 97,\n\tMX8MM_IOMUXC_SAI1_TXC = 98,\n\tMX8MM_IOMUXC_SAI1_TXD0 = 99,\n\tMX8MM_IOMUXC_SAI1_TXD1 = 100,\n\tMX8MM_IOMUXC_SAI1_TXD2 = 101,\n\tMX8MM_IOMUXC_SAI1_TXD3 = 102,\n\tMX8MM_IOMUXC_SAI1_TXD4 = 103,\n\tMX8MM_IOMUXC_SAI1_TXD5 = 104,\n\tMX8MM_IOMUXC_SAI1_TXD6 = 105,\n\tMX8MM_IOMUXC_SAI1_TXD7 = 106,\n\tMX8MM_IOMUXC_SAI1_MCLK = 107,\n\tMX8MM_IOMUXC_SAI2_RXFS = 108,\n\tMX8MM_IOMUXC_SAI2_RXC = 109,\n\tMX8MM_IOMUXC_SAI2_RXD0 = 110,\n\tMX8MM_IOMUXC_SAI2_TXFS = 111,\n\tMX8MM_IOMUXC_SAI2_TXC = 112,\n\tMX8MM_IOMUXC_SAI2_TXD0 = 113,\n\tMX8MM_IOMUXC_SAI2_MCLK = 114,\n\tMX8MM_IOMUXC_SAI3_RXFS = 115,\n\tMX8MM_IOMUXC_SAI3_RXC = 116,\n\tMX8MM_IOMUXC_SAI3_RXD = 117,\n\tMX8MM_IOMUXC_SAI3_TXFS = 118,\n\tMX8MM_IOMUXC_SAI3_TXC = 119,\n\tMX8MM_IOMUXC_SAI3_TXD = 120,\n\tMX8MM_IOMUXC_SAI3_MCLK = 121,\n\tMX8MM_IOMUXC_SPDIF_TX = 122,\n\tMX8MM_IOMUXC_SPDIF_RX = 123,\n\tMX8MM_IOMUXC_SPDIF_EXT_CLK = 124,\n\tMX8MM_IOMUXC_ECSPI1_SCLK = 125,\n\tMX8MM_IOMUXC_ECSPI1_MOSI = 126,\n\tMX8MM_IOMUXC_ECSPI1_MISO = 127,\n\tMX8MM_IOMUXC_ECSPI1_SS0 = 128,\n\tMX8MM_IOMUXC_ECSPI2_SCLK = 129,\n\tMX8MM_IOMUXC_ECSPI2_MOSI = 130,\n\tMX8MM_IOMUXC_ECSPI2_MISO = 131,\n\tMX8MM_IOMUXC_ECSPI2_SS0 = 132,\n\tMX8MM_IOMUXC_I2C1_SCL = 133,\n\tMX8MM_IOMUXC_I2C1_SDA = 134,\n\tMX8MM_IOMUXC_I2C2_SCL = 135,\n\tMX8MM_IOMUXC_I2C2_SDA = 136,\n\tMX8MM_IOMUXC_I2C3_SCL = 137,\n\tMX8MM_IOMUXC_I2C3_SDA = 138,\n\tMX8MM_IOMUXC_I2C4_SCL = 139,\n\tMX8MM_IOMUXC_I2C4_SDA = 140,\n\tMX8MM_IOMUXC_UART1_RXD = 141,\n\tMX8MM_IOMUXC_UART1_TXD = 142,\n\tMX8MM_IOMUXC_UART2_RXD = 143,\n\tMX8MM_IOMUXC_UART2_TXD = 144,\n\tMX8MM_IOMUXC_UART3_RXD = 145,\n\tMX8MM_IOMUXC_UART3_TXD = 146,\n\tMX8MM_IOMUXC_UART4_RXD = 147,\n\tMX8MM_IOMUXC_UART4_TXD = 148,\n};\n\nenum imx8mn_pads {\n\tMX8MN_PAD_RESERVE0 = 0,\n\tMX8MN_PAD_RESERVE1 = 1,\n\tMX8MN_PAD_RESERVE2 = 2,\n\tMX8MN_PAD_RESERVE3 = 3,\n\tMX8MN_PAD_RESERVE4 = 4,\n\tMX8MN_PAD_RESERVE5 = 5,\n\tMX8MN_PAD_RESERVE6 = 6,\n\tMX8MN_PAD_RESERVE7 = 7,\n\tMX8MN_IOMUXC_BOOT_MODE2 = 8,\n\tMX8MN_IOMUXC_BOOT_MODE3 = 9,\n\tMX8MN_IOMUXC_GPIO1_IO00 = 10,\n\tMX8MN_IOMUXC_GPIO1_IO01 = 11,\n\tMX8MN_IOMUXC_GPIO1_IO02 = 12,\n\tMX8MN_IOMUXC_GPIO1_IO03 = 13,\n\tMX8MN_IOMUXC_GPIO1_IO04 = 14,\n\tMX8MN_IOMUXC_GPIO1_IO05 = 15,\n\tMX8MN_IOMUXC_GPIO1_IO06 = 16,\n\tMX8MN_IOMUXC_GPIO1_IO07 = 17,\n\tMX8MN_IOMUXC_GPIO1_IO08 = 18,\n\tMX8MN_IOMUXC_GPIO1_IO09 = 19,\n\tMX8MN_IOMUXC_GPIO1_IO10 = 20,\n\tMX8MN_IOMUXC_GPIO1_IO11 = 21,\n\tMX8MN_IOMUXC_GPIO1_IO12 = 22,\n\tMX8MN_IOMUXC_GPIO1_IO13 = 23,\n\tMX8MN_IOMUXC_GPIO1_IO14 = 24,\n\tMX8MN_IOMUXC_GPIO1_IO15 = 25,\n\tMX8MN_IOMUXC_ENET_MDC = 26,\n\tMX8MN_IOMUXC_ENET_MDIO = 27,\n\tMX8MN_IOMUXC_ENET_TD3 = 28,\n\tMX8MN_IOMUXC_ENET_TD2 = 29,\n\tMX8MN_IOMUXC_ENET_TD1 = 30,\n\tMX8MN_IOMUXC_ENET_TD0 = 31,\n\tMX8MN_IOMUXC_ENET_TX_CTL = 32,\n\tMX8MN_IOMUXC_ENET_TXC = 33,\n\tMX8MN_IOMUXC_ENET_RX_CTL = 34,\n\tMX8MN_IOMUXC_ENET_RXC = 35,\n\tMX8MN_IOMUXC_ENET_RD0 = 36,\n\tMX8MN_IOMUXC_ENET_RD1 = 37,\n\tMX8MN_IOMUXC_ENET_RD2 = 38,\n\tMX8MN_IOMUXC_ENET_RD3 = 39,\n\tMX8MN_IOMUXC_SD1_CLK = 40,\n\tMX8MN_IOMUXC_SD1_CMD = 41,\n\tMX8MN_IOMUXC_SD1_DATA0 = 42,\n\tMX8MN_IOMUXC_SD1_DATA1 = 43,\n\tMX8MN_IOMUXC_SD1_DATA2 = 44,\n\tMX8MN_IOMUXC_SD1_DATA3 = 45,\n\tMX8MN_IOMUXC_SD1_DATA4 = 46,\n\tMX8MN_IOMUXC_SD1_DATA5 = 47,\n\tMX8MN_IOMUXC_SD1_DATA6 = 48,\n\tMX8MN_IOMUXC_SD1_DATA7 = 49,\n\tMX8MN_IOMUXC_SD1_RESET_B = 50,\n\tMX8MN_IOMUXC_SD1_STROBE = 51,\n\tMX8MN_IOMUXC_SD2_CD_B = 52,\n\tMX8MN_IOMUXC_SD2_CLK = 53,\n\tMX8MN_IOMUXC_SD2_CMD = 54,\n\tMX8MN_IOMUXC_SD2_DATA0 = 55,\n\tMX8MN_IOMUXC_SD2_DATA1 = 56,\n\tMX8MN_IOMUXC_SD2_DATA2 = 57,\n\tMX8MN_IOMUXC_SD2_DATA3 = 58,\n\tMX8MN_IOMUXC_SD2_RESET_B = 59,\n\tMX8MN_IOMUXC_SD2_WP = 60,\n\tMX8MN_IOMUXC_NAND_ALE = 61,\n\tMX8MN_IOMUXC_NAND_CE0 = 62,\n\tMX8MN_IOMUXC_NAND_CE1 = 63,\n\tMX8MN_IOMUXC_NAND_CE2 = 64,\n\tMX8MN_IOMUXC_NAND_CE3 = 65,\n\tMX8MN_IOMUXC_NAND_CLE = 66,\n\tMX8MN_IOMUXC_NAND_DATA00 = 67,\n\tMX8MN_IOMUXC_NAND_DATA01 = 68,\n\tMX8MN_IOMUXC_NAND_DATA02 = 69,\n\tMX8MN_IOMUXC_NAND_DATA03 = 70,\n\tMX8MN_IOMUXC_NAND_DATA04 = 71,\n\tMX8MN_IOMUXC_NAND_DATA05 = 72,\n\tMX8MN_IOMUXC_NAND_DATA06 = 73,\n\tMX8MN_IOMUXC_NAND_DATA07 = 74,\n\tMX8MN_IOMUXC_NAND_DQS = 75,\n\tMX8MN_IOMUXC_NAND_RE_B = 76,\n\tMX8MN_IOMUXC_NAND_READY_B = 77,\n\tMX8MN_IOMUXC_NAND_WE_B = 78,\n\tMX8MN_IOMUXC_NAND_WP_B = 79,\n\tMX8MN_IOMUXC_SAI5_RXFS = 80,\n\tMX8MN_IOMUXC_SAI5_RXC = 81,\n\tMX8MN_IOMUXC_SAI5_RXD0 = 82,\n\tMX8MN_IOMUXC_SAI5_RXD1 = 83,\n\tMX8MN_IOMUXC_SAI5_RXD2 = 84,\n\tMX8MN_IOMUXC_SAI5_RXD3 = 85,\n\tMX8MN_IOMUXC_SAI5_MCLK = 86,\n\tMX8MN_IOMUXC_SAI1_RXFS = 87,\n\tMX8MN_IOMUXC_SAI1_RXC = 88,\n\tMX8MN_IOMUXC_SAI1_RXD0 = 89,\n\tMX8MN_IOMUXC_SAI1_RXD1 = 90,\n\tMX8MN_IOMUXC_SAI1_RXD2 = 91,\n\tMX8MN_IOMUXC_SAI1_RXD3 = 92,\n\tMX8MN_IOMUXC_SAI1_RXD4 = 93,\n\tMX8MN_IOMUXC_SAI1_RXD5 = 94,\n\tMX8MN_IOMUXC_SAI1_RXD6 = 95,\n\tMX8MN_IOMUXC_SAI1_RXD7 = 96,\n\tMX8MN_IOMUXC_SAI1_TXFS = 97,\n\tMX8MN_IOMUXC_SAI1_TXC = 98,\n\tMX8MN_IOMUXC_SAI1_TXD0 = 99,\n\tMX8MN_IOMUXC_SAI1_TXD1 = 100,\n\tMX8MN_IOMUXC_SAI1_TXD2 = 101,\n\tMX8MN_IOMUXC_SAI1_TXD3 = 102,\n\tMX8MN_IOMUXC_SAI1_TXD4 = 103,\n\tMX8MN_IOMUXC_SAI1_TXD5 = 104,\n\tMX8MN_IOMUXC_SAI1_TXD6 = 105,\n\tMX8MN_IOMUXC_SAI1_TXD7 = 106,\n\tMX8MN_IOMUXC_SAI1_MCLK = 107,\n\tMX8MN_IOMUXC_SAI2_RXFS = 108,\n\tMX8MN_IOMUXC_SAI2_RXC = 109,\n\tMX8MN_IOMUXC_SAI2_RXD0 = 110,\n\tMX8MN_IOMUXC_SAI2_TXFS = 111,\n\tMX8MN_IOMUXC_SAI2_TXC = 112,\n\tMX8MN_IOMUXC_SAI2_TXD0 = 113,\n\tMX8MN_IOMUXC_SAI2_MCLK = 114,\n\tMX8MN_IOMUXC_SAI3_RXFS = 115,\n\tMX8MN_IOMUXC_SAI3_RXC = 116,\n\tMX8MN_IOMUXC_SAI3_RXD = 117,\n\tMX8MN_IOMUXC_SAI3_TXFS = 118,\n\tMX8MN_IOMUXC_SAI3_TXC = 119,\n\tMX8MN_IOMUXC_SAI3_TXD = 120,\n\tMX8MN_IOMUXC_SAI3_MCLK = 121,\n\tMX8MN_IOMUXC_SPDIF_TX = 122,\n\tMX8MN_IOMUXC_SPDIF_RX = 123,\n\tMX8MN_IOMUXC_SPDIF_EXT_CLK = 124,\n\tMX8MN_IOMUXC_ECSPI1_SCLK = 125,\n\tMX8MN_IOMUXC_ECSPI1_MOSI = 126,\n\tMX8MN_IOMUXC_ECSPI1_MISO = 127,\n\tMX8MN_IOMUXC_ECSPI1_SS0 = 128,\n\tMX8MN_IOMUXC_ECSPI2_SCLK = 129,\n\tMX8MN_IOMUXC_ECSPI2_MOSI = 130,\n\tMX8MN_IOMUXC_ECSPI2_MISO = 131,\n\tMX8MN_IOMUXC_ECSPI2_SS0 = 132,\n\tMX8MN_IOMUXC_I2C1_SCL = 133,\n\tMX8MN_IOMUXC_I2C1_SDA = 134,\n\tMX8MN_IOMUXC_I2C2_SCL = 135,\n\tMX8MN_IOMUXC_I2C2_SDA = 136,\n\tMX8MN_IOMUXC_I2C3_SCL = 137,\n\tMX8MN_IOMUXC_I2C3_SDA = 138,\n\tMX8MN_IOMUXC_I2C4_SCL = 139,\n\tMX8MN_IOMUXC_I2C4_SDA = 140,\n\tMX8MN_IOMUXC_UART1_RXD = 141,\n\tMX8MN_IOMUXC_UART1_TXD = 142,\n\tMX8MN_IOMUXC_UART2_RXD = 143,\n\tMX8MN_IOMUXC_UART2_TXD = 144,\n\tMX8MN_IOMUXC_UART3_RXD = 145,\n\tMX8MN_IOMUXC_UART3_TXD = 146,\n\tMX8MN_IOMUXC_UART4_RXD = 147,\n\tMX8MN_IOMUXC_UART4_TXD = 148,\n};\n\nenum imx8mp_pads {\n\tMX8MP_IOMUXC_RESERVE0 = 0,\n\tMX8MP_IOMUXC_RESERVE1 = 1,\n\tMX8MP_IOMUXC_RESERVE2 = 2,\n\tMX8MP_IOMUXC_RESERVE3 = 3,\n\tMX8MP_IOMUXC_RESERVE4 = 4,\n\tMX8MP_IOMUXC_GPIO1_IO00 = 5,\n\tMX8MP_IOMUXC_GPIO1_IO01 = 6,\n\tMX8MP_IOMUXC_GPIO1_IO02 = 7,\n\tMX8MP_IOMUXC_GPIO1_IO03 = 8,\n\tMX8MP_IOMUXC_GPIO1_IO04 = 9,\n\tMX8MP_IOMUXC_GPIO1_IO05 = 10,\n\tMX8MP_IOMUXC_GPIO1_IO06 = 11,\n\tMX8MP_IOMUXC_GPIO1_IO07 = 12,\n\tMX8MP_IOMUXC_GPIO1_IO08 = 13,\n\tMX8MP_IOMUXC_GPIO1_IO09 = 14,\n\tMX8MP_IOMUXC_GPIO1_IO10 = 15,\n\tMX8MP_IOMUXC_GPIO1_IO11 = 16,\n\tMX8MP_IOMUXC_GPIO1_IO12 = 17,\n\tMX8MP_IOMUXC_GPIO1_IO13 = 18,\n\tMX8MP_IOMUXC_GPIO1_IO14 = 19,\n\tMX8MP_IOMUXC_GPIO1_IO15 = 20,\n\tMX8MP_IOMUXC_ENET_MDC = 21,\n\tMX8MP_IOMUXC_ENET_MDIO = 22,\n\tMX8MP_IOMUXC_ENET_TD3 = 23,\n\tMX8MP_IOMUXC_ENET_TD2 = 24,\n\tMX8MP_IOMUXC_ENET_TD1 = 25,\n\tMX8MP_IOMUXC_ENET_TD0 = 26,\n\tMX8MP_IOMUXC_ENET_TX_CTL = 27,\n\tMX8MP_IOMUXC_ENET_TXC = 28,\n\tMX8MP_IOMUXC_ENET_RX_CTL = 29,\n\tMX8MP_IOMUXC_ENET_RXC = 30,\n\tMX8MP_IOMUXC_ENET_RD0 = 31,\n\tMX8MP_IOMUXC_ENET_RD1 = 32,\n\tMX8MP_IOMUXC_ENET_RD2 = 33,\n\tMX8MP_IOMUXC_ENET_RD3 = 34,\n\tMX8MP_IOMUXC_SD1_CLK = 35,\n\tMX8MP_IOMUXC_SD1_CMD = 36,\n\tMX8MP_IOMUXC_SD1_DATA0 = 37,\n\tMX8MP_IOMUXC_SD1_DATA1 = 38,\n\tMX8MP_IOMUXC_SD1_DATA2 = 39,\n\tMX8MP_IOMUXC_SD1_DATA3 = 40,\n\tMX8MP_IOMUXC_SD1_DATA4 = 41,\n\tMX8MP_IOMUXC_SD1_DATA5 = 42,\n\tMX8MP_IOMUXC_SD1_DATA6 = 43,\n\tMX8MP_IOMUXC_SD1_DATA7 = 44,\n\tMX8MP_IOMUXC_SD1_RESET_B = 45,\n\tMX8MP_IOMUXC_SD1_STROBE = 46,\n\tMX8MP_IOMUXC_SD2_CD_B = 47,\n\tMX8MP_IOMUXC_SD2_CLK = 48,\n\tMX8MP_IOMUXC_SD2_CMD = 49,\n\tMX8MP_IOMUXC_SD2_DATA0 = 50,\n\tMX8MP_IOMUXC_SD2_DATA1 = 51,\n\tMX8MP_IOMUXC_SD2_DATA2 = 52,\n\tMX8MP_IOMUXC_SD2_DATA3 = 53,\n\tMX8MP_IOMUXC_SD2_RESET_B = 54,\n\tMX8MP_IOMUXC_SD2_WP = 55,\n\tMX8MP_IOMUXC_NAND_ALE = 56,\n\tMX8MP_IOMUXC_NAND_CE0_B = 57,\n\tMX8MP_IOMUXC_NAND_CE1_B = 58,\n\tMX8MP_IOMUXC_NAND_CE2_B = 59,\n\tMX8MP_IOMUXC_NAND_CE3_B = 60,\n\tMX8MP_IOMUXC_NAND_CLE = 61,\n\tMX8MP_IOMUXC_NAND_DATA00 = 62,\n\tMX8MP_IOMUXC_NAND_DATA01 = 63,\n\tMX8MP_IOMUXC_NAND_DATA02 = 64,\n\tMX8MP_IOMUXC_NAND_DATA03 = 65,\n\tMX8MP_IOMUXC_NAND_DATA04 = 66,\n\tMX8MP_IOMUXC_NAND_DATA05 = 67,\n\tMX8MP_IOMUXC_NAND_DATA06 = 68,\n\tMX8MP_IOMUXC_NAND_DATA07 = 69,\n\tMX8MP_IOMUXC_NAND_DQS = 70,\n\tMX8MP_IOMUXC_NAND_RE_B = 71,\n\tMX8MP_IOMUXC_NAND_READY_B = 72,\n\tMX8MP_IOMUXC_NAND_WE_B = 73,\n\tMX8MP_IOMUXC_NAND_WP_B = 74,\n\tMX8MP_IOMUXC_SAI5_RXFS = 75,\n\tMX8MP_IOMUXC_SAI5_RXC = 76,\n\tMX8MP_IOMUXC_SAI5_RXD0 = 77,\n\tMX8MP_IOMUXC_SAI5_RXD1 = 78,\n\tMX8MP_IOMUXC_SAI5_RXD2 = 79,\n\tMX8MP_IOMUXC_SAI5_RXD3 = 80,\n\tMX8MP_IOMUXC_SAI5_MCLK = 81,\n\tMX8MP_IOMUXC_SAI1_RXFS = 82,\n\tMX8MP_IOMUXC_SAI1_RXC = 83,\n\tMX8MP_IOMUXC_SAI1_RXD0 = 84,\n\tMX8MP_IOMUXC_SAI1_RXD1 = 85,\n\tMX8MP_IOMUXC_SAI1_RXD2 = 86,\n\tMX8MP_IOMUXC_SAI1_RXD3 = 87,\n\tMX8MP_IOMUXC_SAI1_RXD4 = 88,\n\tMX8MP_IOMUXC_SAI1_RXD5 = 89,\n\tMX8MP_IOMUXC_SAI1_RXD6 = 90,\n\tMX8MP_IOMUXC_SAI1_RXD7 = 91,\n\tMX8MP_IOMUXC_SAI1_TXFS = 92,\n\tMX8MP_IOMUXC_SAI1_TXC = 93,\n\tMX8MP_IOMUXC_SAI1_TXD0 = 94,\n\tMX8MP_IOMUXC_SAI1_TXD1 = 95,\n\tMX8MP_IOMUXC_SAI1_TXD2 = 96,\n\tMX8MP_IOMUXC_SAI1_TXD3 = 97,\n\tMX8MP_IOMUXC_SAI1_TXD4 = 98,\n\tMX8MP_IOMUXC_SAI1_TXD5 = 99,\n\tMX8MP_IOMUXC_SAI1_TXD6 = 100,\n\tMX8MP_IOMUXC_SAI1_TXD7 = 101,\n\tMX8MP_IOMUXC_SAI1_MCLK = 102,\n\tMX8MP_IOMUXC_SAI2_RXFS = 103,\n\tMX8MP_IOMUXC_SAI2_RXC = 104,\n\tMX8MP_IOMUXC_SAI2_RXD0 = 105,\n\tMX8MP_IOMUXC_SAI2_TXFS = 106,\n\tMX8MP_IOMUXC_SAI2_TXC = 107,\n\tMX8MP_IOMUXC_SAI2_TXD0 = 108,\n\tMX8MP_IOMUXC_SAI2_MCLK = 109,\n\tMX8MP_IOMUXC_SAI3_RXFS = 110,\n\tMX8MP_IOMUXC_SAI3_RXC = 111,\n\tMX8MP_IOMUXC_SAI3_RXD = 112,\n\tMX8MP_IOMUXC_SAI3_TXFS = 113,\n\tMX8MP_IOMUXC_SAI3_TXC = 114,\n\tMX8MP_IOMUXC_SAI3_TXD = 115,\n\tMX8MP_IOMUXC_SAI3_MCLK = 116,\n\tMX8MP_IOMUXC_SPDIF_TX = 117,\n\tMX8MP_IOMUXC_SPDIF_RX = 118,\n\tMX8MP_IOMUXC_SPDIF_EXT_CLK = 119,\n\tMX8MP_IOMUXC_ECSPI1_SCLK = 120,\n\tMX8MP_IOMUXC_ECSPI1_MOSI = 121,\n\tMX8MP_IOMUXC_ECSPI1_MISO = 122,\n\tMX8MP_IOMUXC_ECSPI1_SS0 = 123,\n\tMX8MP_IOMUXC_ECSPI2_SCLK = 124,\n\tMX8MP_IOMUXC_ECSPI2_MOSI = 125,\n\tMX8MP_IOMUXC_ECSPI2_MISO = 126,\n\tMX8MP_IOMUXC_ECSPI2_SS0 = 127,\n\tMX8MP_IOMUXC_I2C1_SCL = 128,\n\tMX8MP_IOMUXC_I2C1_SDA = 129,\n\tMX8MP_IOMUXC_I2C2_SCL = 130,\n\tMX8MP_IOMUXC_I2C2_SDA = 131,\n\tMX8MP_IOMUXC_I2C3_SCL = 132,\n\tMX8MP_IOMUXC_I2C3_SDA = 133,\n\tMX8MP_IOMUXC_I2C4_SCL = 134,\n\tMX8MP_IOMUXC_I2C4_SDA = 135,\n\tMX8MP_IOMUXC_UART1_RXD = 136,\n\tMX8MP_IOMUXC_UART1_TXD = 137,\n\tMX8MP_IOMUXC_UART2_RXD = 138,\n\tMX8MP_IOMUXC_UART2_TXD = 139,\n\tMX8MP_IOMUXC_UART3_RXD = 140,\n\tMX8MP_IOMUXC_UART3_TXD = 141,\n\tMX8MP_IOMUXC_UART4_RXD = 142,\n\tMX8MP_IOMUXC_UART4_TXD = 143,\n\tMX8MP_IOMUXC_HDMI_DDC_SCL = 144,\n\tMX8MP_IOMUXC_HDMI_DDC_SDA = 145,\n\tMX8MP_IOMUXC_HDMI_CEC = 146,\n\tMX8MP_IOMUXC_HDMI_HPD = 147,\n};\n\nenum imx8mp_src_registers {\n\tSRC_SUPERMIX_RCR = 24,\n\tSRC_AUDIOMIX_RCR = 28,\n\tSRC_MLMIX_RCR = 40,\n\tSRC_GPU2D_RCR = 56,\n\tSRC_GPU3D_RCR = 60,\n\tSRC_VPU_G1_RCR = 72,\n\tSRC_VPU_G2_RCR = 76,\n\tSRC_VPUVC8KE_RCR = 80,\n\tSRC_NOC_RCR = 84,\n};\n\nenum imx8mq_pads {\n\tMX8MQ_PAD_RESERVE0 = 0,\n\tMX8MQ_PAD_RESERVE1 = 1,\n\tMX8MQ_PAD_RESERVE2 = 2,\n\tMX8MQ_PAD_RESERVE3 = 3,\n\tMX8MQ_PAD_RESERVE4 = 4,\n\tMX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5,\n\tMX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6,\n\tMX8MQ_IOMUXC_ONOFF_SNVSMIX = 7,\n\tMX8MQ_IOMUXC_POR_B_SNVSMIX = 8,\n\tMX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9,\n\tMX8MQ_IOMUXC_GPIO1_IO00 = 10,\n\tMX8MQ_IOMUXC_GPIO1_IO01 = 11,\n\tMX8MQ_IOMUXC_GPIO1_IO02 = 12,\n\tMX8MQ_IOMUXC_GPIO1_IO03 = 13,\n\tMX8MQ_IOMUXC_GPIO1_IO04 = 14,\n\tMX8MQ_IOMUXC_GPIO1_IO05 = 15,\n\tMX8MQ_IOMUXC_GPIO1_IO06 = 16,\n\tMX8MQ_IOMUXC_GPIO1_IO07 = 17,\n\tMX8MQ_IOMUXC_GPIO1_IO08 = 18,\n\tMX8MQ_IOMUXC_GPIO1_IO09 = 19,\n\tMX8MQ_IOMUXC_GPIO1_IO10 = 20,\n\tMX8MQ_IOMUXC_GPIO1_IO11 = 21,\n\tMX8MQ_IOMUXC_GPIO1_IO12 = 22,\n\tMX8MQ_IOMUXC_GPIO1_IO13 = 23,\n\tMX8MQ_IOMUXC_GPIO1_IO14 = 24,\n\tMX8MQ_IOMUXC_GPIO1_IO15 = 25,\n\tMX8MQ_IOMUXC_ENET_MDC = 26,\n\tMX8MQ_IOMUXC_ENET_MDIO = 27,\n\tMX8MQ_IOMUXC_ENET_TD3 = 28,\n\tMX8MQ_IOMUXC_ENET_TD2 = 29,\n\tMX8MQ_IOMUXC_ENET_TD1 = 30,\n\tMX8MQ_IOMUXC_ENET_TD0 = 31,\n\tMX8MQ_IOMUXC_ENET_TX_CTL = 32,\n\tMX8MQ_IOMUXC_ENET_TXC = 33,\n\tMX8MQ_IOMUXC_ENET_RX_CTL = 34,\n\tMX8MQ_IOMUXC_ENET_RXC = 35,\n\tMX8MQ_IOMUXC_ENET_RD0 = 36,\n\tMX8MQ_IOMUXC_ENET_RD1 = 37,\n\tMX8MQ_IOMUXC_ENET_RD2 = 38,\n\tMX8MQ_IOMUXC_ENET_RD3 = 39,\n\tMX8MQ_IOMUXC_SD1_CLK = 40,\n\tMX8MQ_IOMUXC_SD1_CMD = 41,\n\tMX8MQ_IOMUXC_SD1_DATA0 = 42,\n\tMX8MQ_IOMUXC_SD1_DATA1 = 43,\n\tMX8MQ_IOMUXC_SD1_DATA2 = 44,\n\tMX8MQ_IOMUXC_SD1_DATA3 = 45,\n\tMX8MQ_IOMUXC_SD1_DATA4 = 46,\n\tMX8MQ_IOMUXC_SD1_DATA5 = 47,\n\tMX8MQ_IOMUXC_SD1_DATA6 = 48,\n\tMX8MQ_IOMUXC_SD1_DATA7 = 49,\n\tMX8MQ_IOMUXC_SD1_RESET_B = 50,\n\tMX8MQ_IOMUXC_SD1_STROBE = 51,\n\tMX8MQ_IOMUXC_SD2_CD_B = 52,\n\tMX8MQ_IOMUXC_SD2_CLK = 53,\n\tMX8MQ_IOMUXC_SD2_CMD = 54,\n\tMX8MQ_IOMUXC_SD2_DATA0 = 55,\n\tMX8MQ_IOMUXC_SD2_DATA1 = 56,\n\tMX8MQ_IOMUXC_SD2_DATA2 = 57,\n\tMX8MQ_IOMUXC_SD2_DATA3 = 58,\n\tMX8MQ_IOMUXC_SD2_RESET_B = 59,\n\tMX8MQ_IOMUXC_SD2_WP = 60,\n\tMX8MQ_IOMUXC_NAND_ALE = 61,\n\tMX8MQ_IOMUXC_NAND_CE0_B = 62,\n\tMX8MQ_IOMUXC_NAND_CE1_B = 63,\n\tMX8MQ_IOMUXC_NAND_CE2_B = 64,\n\tMX8MQ_IOMUXC_NAND_CE3_B = 65,\n\tMX8MQ_IOMUXC_NAND_CLE = 66,\n\tMX8MQ_IOMUXC_NAND_DATA00 = 67,\n\tMX8MQ_IOMUXC_NAND_DATA01 = 68,\n\tMX8MQ_IOMUXC_NAND_DATA02 = 69,\n\tMX8MQ_IOMUXC_NAND_DATA03 = 70,\n\tMX8MQ_IOMUXC_NAND_DATA04 = 71,\n\tMX8MQ_IOMUXC_NAND_DATA05 = 72,\n\tMX8MQ_IOMUXC_NAND_DATA06 = 73,\n\tMX8MQ_IOMUXC_NAND_DATA07 = 74,\n\tMX8MQ_IOMUXC_NAND_DQS = 75,\n\tMX8MQ_IOMUXC_NAND_RE_B = 76,\n\tMX8MQ_IOMUXC_NAND_READY_B = 77,\n\tMX8MQ_IOMUXC_NAND_WE_B = 78,\n\tMX8MQ_IOMUXC_NAND_WP_B = 79,\n\tMX8MQ_IOMUXC_SAI5_RXFS = 80,\n\tMX8MQ_IOMUXC_SAI5_RXC = 81,\n\tMX8MQ_IOMUXC_SAI5_RXD0 = 82,\n\tMX8MQ_IOMUXC_SAI5_RXD1 = 83,\n\tMX8MQ_IOMUXC_SAI5_RXD2 = 84,\n\tMX8MQ_IOMUXC_SAI5_RXD3 = 85,\n\tMX8MQ_IOMUXC_SAI5_MCLK = 86,\n\tMX8MQ_IOMUXC_SAI1_RXFS = 87,\n\tMX8MQ_IOMUXC_SAI1_RXC = 88,\n\tMX8MQ_IOMUXC_SAI1_RXD0 = 89,\n\tMX8MQ_IOMUXC_SAI1_RXD1 = 90,\n\tMX8MQ_IOMUXC_SAI1_RXD2 = 91,\n\tMX8MQ_IOMUXC_SAI1_RXD3 = 92,\n\tMX8MQ_IOMUXC_SAI1_RXD4 = 93,\n\tMX8MQ_IOMUXC_SAI1_RXD5 = 94,\n\tMX8MQ_IOMUXC_SAI1_RXD6 = 95,\n\tMX8MQ_IOMUXC_SAI1_RXD7 = 96,\n\tMX8MQ_IOMUXC_SAI1_TXFS = 97,\n\tMX8MQ_IOMUXC_SAI1_TXC = 98,\n\tMX8MQ_IOMUXC_SAI1_TXD0 = 99,\n\tMX8MQ_IOMUXC_SAI1_TXD1 = 100,\n\tMX8MQ_IOMUXC_SAI1_TXD2 = 101,\n\tMX8MQ_IOMUXC_SAI1_TXD3 = 102,\n\tMX8MQ_IOMUXC_SAI1_TXD4 = 103,\n\tMX8MQ_IOMUXC_SAI1_TXD5 = 104,\n\tMX8MQ_IOMUXC_SAI1_TXD6 = 105,\n\tMX8MQ_IOMUXC_SAI1_TXD7 = 106,\n\tMX8MQ_IOMUXC_SAI1_MCLK = 107,\n\tMX8MQ_IOMUXC_SAI2_RXFS = 108,\n\tMX8MQ_IOMUXC_SAI2_RXC = 109,\n\tMX8MQ_IOMUXC_SAI2_RXD0 = 110,\n\tMX8MQ_IOMUXC_SAI2_TXFS = 111,\n\tMX8MQ_IOMUXC_SAI2_TXC = 112,\n\tMX8MQ_IOMUXC_SAI2_TXD0 = 113,\n\tMX8MQ_IOMUXC_SAI2_MCLK = 114,\n\tMX8MQ_IOMUXC_SAI3_RXFS = 115,\n\tMX8MQ_IOMUXC_SAI3_RXC = 116,\n\tMX8MQ_IOMUXC_SAI3_RXD = 117,\n\tMX8MQ_IOMUXC_SAI3_TXFS = 118,\n\tMX8MQ_IOMUXC_SAI3_TXC = 119,\n\tMX8MQ_IOMUXC_SAI3_TXD = 120,\n\tMX8MQ_IOMUXC_SAI3_MCLK = 121,\n\tMX8MQ_IOMUXC_SPDIF_TX = 122,\n\tMX8MQ_IOMUXC_SPDIF_RX = 123,\n\tMX8MQ_IOMUXC_SPDIF_EXT_CLK = 124,\n\tMX8MQ_IOMUXC_ECSPI1_SCLK = 125,\n\tMX8MQ_IOMUXC_ECSPI1_MOSI = 126,\n\tMX8MQ_IOMUXC_ECSPI1_MISO = 127,\n\tMX8MQ_IOMUXC_ECSPI1_SS0 = 128,\n\tMX8MQ_IOMUXC_ECSPI2_SCLK = 129,\n\tMX8MQ_IOMUXC_ECSPI2_MOSI = 130,\n\tMX8MQ_IOMUXC_ECSPI2_MISO = 131,\n\tMX8MQ_IOMUXC_ECSPI2_SS0 = 132,\n\tMX8MQ_IOMUXC_I2C1_SCL = 133,\n\tMX8MQ_IOMUXC_I2C1_SDA = 134,\n\tMX8MQ_IOMUXC_I2C2_SCL = 135,\n\tMX8MQ_IOMUXC_I2C2_SDA = 136,\n\tMX8MQ_IOMUXC_I2C3_SCL = 137,\n\tMX8MQ_IOMUXC_I2C3_SDA = 138,\n\tMX8MQ_IOMUXC_I2C4_SCL = 139,\n\tMX8MQ_IOMUXC_I2C4_SDA = 140,\n\tMX8MQ_IOMUXC_UART1_RXD = 141,\n\tMX8MQ_IOMUXC_UART1_TXD = 142,\n\tMX8MQ_IOMUXC_UART2_RXD = 143,\n\tMX8MQ_IOMUXC_UART2_TXD = 144,\n\tMX8MQ_IOMUXC_UART3_RXD = 145,\n\tMX8MQ_IOMUXC_UART3_TXD = 146,\n\tMX8MQ_IOMUXC_UART4_RXD = 147,\n\tMX8MQ_IOMUXC_UART4_TXD = 148,\n};\n\nenum imx8mq_src_registers {\n\tSRC_A53RCR0 = 4,\n\tSRC_HDMI_RCR = 48,\n\tSRC_DISP_RCR = 52,\n\tSRC_GPU_RCR = 64,\n\tSRC_VPU_RCR = 68,\n\tSRC_PCIE2_RCR = 72,\n\tSRC_MIPIPHY1_RCR = 76,\n\tSRC_MIPIPHY2_RCR = 80,\n\tSRC_DDRC2_RCR = 4100,\n};\n\nenum imx8ulp_pads {\n\tIMX8ULP_PAD_PTD0 = 0,\n\tIMX8ULP_PAD_PTD1 = 1,\n\tIMX8ULP_PAD_PTD2 = 2,\n\tIMX8ULP_PAD_PTD3 = 3,\n\tIMX8ULP_PAD_PTD4 = 4,\n\tIMX8ULP_PAD_PTD5 = 5,\n\tIMX8ULP_PAD_PTD6 = 6,\n\tIMX8ULP_PAD_PTD7 = 7,\n\tIMX8ULP_PAD_PTD8 = 8,\n\tIMX8ULP_PAD_PTD9 = 9,\n\tIMX8ULP_PAD_PTD10 = 10,\n\tIMX8ULP_PAD_PTD11 = 11,\n\tIMX8ULP_PAD_PTD12 = 12,\n\tIMX8ULP_PAD_PTD13 = 13,\n\tIMX8ULP_PAD_PTD14 = 14,\n\tIMX8ULP_PAD_PTD15 = 15,\n\tIMX8ULP_PAD_PTD16 = 16,\n\tIMX8ULP_PAD_PTD17 = 17,\n\tIMX8ULP_PAD_PTD18 = 18,\n\tIMX8ULP_PAD_PTD19 = 19,\n\tIMX8ULP_PAD_PTD20 = 20,\n\tIMX8ULP_PAD_PTD21 = 21,\n\tIMX8ULP_PAD_PTD22 = 22,\n\tIMX8ULP_PAD_PTD23 = 23,\n\tIMX8ULP_PAD_RESERVE0 = 24,\n\tIMX8ULP_PAD_RESERVE1 = 25,\n\tIMX8ULP_PAD_RESERVE2 = 26,\n\tIMX8ULP_PAD_RESERVE3 = 27,\n\tIMX8ULP_PAD_RESERVE4 = 28,\n\tIMX8ULP_PAD_RESERVE5 = 29,\n\tIMX8ULP_PAD_RESERVE6 = 30,\n\tIMX8ULP_PAD_RESERVE7 = 31,\n\tIMX8ULP_PAD_PTE0 = 32,\n\tIMX8ULP_PAD_PTE1 = 33,\n\tIMX8ULP_PAD_PTE2 = 34,\n\tIMX8ULP_PAD_PTE3 = 35,\n\tIMX8ULP_PAD_PTE4 = 36,\n\tIMX8ULP_PAD_PTE5 = 37,\n\tIMX8ULP_PAD_PTE6 = 38,\n\tIMX8ULP_PAD_PTE7 = 39,\n\tIMX8ULP_PAD_PTE8 = 40,\n\tIMX8ULP_PAD_PTE9 = 41,\n\tIMX8ULP_PAD_PTE10 = 42,\n\tIMX8ULP_PAD_PTE11 = 43,\n\tIMX8ULP_PAD_PTE12 = 44,\n\tIMX8ULP_PAD_PTE13 = 45,\n\tIMX8ULP_PAD_PTE14 = 46,\n\tIMX8ULP_PAD_PTE15 = 47,\n\tIMX8ULP_PAD_PTE16 = 48,\n\tIMX8ULP_PAD_PTE17 = 49,\n\tIMX8ULP_PAD_PTE18 = 50,\n\tIMX8ULP_PAD_PTE19 = 51,\n\tIMX8ULP_PAD_PTE20 = 52,\n\tIMX8ULP_PAD_PTE21 = 53,\n\tIMX8ULP_PAD_PTE22 = 54,\n\tIMX8ULP_PAD_PTE23 = 55,\n\tIMX8ULP_PAD_RESERVE8 = 56,\n\tIMX8ULP_PAD_RESERVE9 = 57,\n\tIMX8ULP_PAD_RESERVE10 = 58,\n\tIMX8ULP_PAD_RESERVE11 = 59,\n\tIMX8ULP_PAD_RESERVE12 = 60,\n\tIMX8ULP_PAD_RESERVE13 = 61,\n\tIMX8ULP_PAD_RESERVE14 = 62,\n\tIMX8ULP_PAD_RESERVE15 = 63,\n\tIMX8ULP_PAD_PTF0 = 64,\n\tIMX8ULP_PAD_PTF1 = 65,\n\tIMX8ULP_PAD_PTF2 = 66,\n\tIMX8ULP_PAD_PTF3 = 67,\n\tIMX8ULP_PAD_PTF4 = 68,\n\tIMX8ULP_PAD_PTF5 = 69,\n\tIMX8ULP_PAD_PTF6 = 70,\n\tIMX8ULP_PAD_PTF7 = 71,\n\tIMX8ULP_PAD_PTF8 = 72,\n\tIMX8ULP_PAD_PTF9 = 73,\n\tIMX8ULP_PAD_PTF10 = 74,\n\tIMX8ULP_PAD_PTF11 = 75,\n\tIMX8ULP_PAD_PTF12 = 76,\n\tIMX8ULP_PAD_PTF13 = 77,\n\tIMX8ULP_PAD_PTF14 = 78,\n\tIMX8ULP_PAD_PTF15 = 79,\n\tIMX8ULP_PAD_PTF16 = 80,\n\tIMX8ULP_PAD_PTF17 = 81,\n\tIMX8ULP_PAD_PTF18 = 82,\n\tIMX8ULP_PAD_PTF19 = 83,\n\tIMX8ULP_PAD_PTF20 = 84,\n\tIMX8ULP_PAD_PTF21 = 85,\n\tIMX8ULP_PAD_PTF22 = 86,\n\tIMX8ULP_PAD_PTF23 = 87,\n\tIMX8ULP_PAD_PTF24 = 88,\n\tIMX8ULP_PAD_PTF25 = 89,\n\tIMX8ULP_PAD_PTF26 = 90,\n\tIMX8ULP_PAD_PTF27 = 91,\n\tIMX8ULP_PAD_PTF28 = 92,\n\tIMX8ULP_PAD_PTF29 = 93,\n\tIMX8ULP_PAD_PTF30 = 94,\n\tIMX8ULP_PAD_PTF31 = 95,\n};\n\nenum imx91_pads {\n\tIMX91_PAD_DAP_TDI = 0,\n\tIMX91_PAD_DAP_TMS_SWDIO = 1,\n\tIMX91_PAD_DAP_TCLK_SWCLK = 2,\n\tIMX91_PAD_DAP_TDO_TRACESWO = 3,\n\tIMX91_PAD_GPIO_IO00 = 4,\n\tIMX91_PAD_GPIO_IO01 = 5,\n\tIMX91_PAD_GPIO_IO02 = 6,\n\tIMX91_PAD_GPIO_IO03 = 7,\n\tIMX91_PAD_GPIO_IO04 = 8,\n\tIMX91_PAD_GPIO_IO05 = 9,\n\tIMX91_PAD_GPIO_IO06 = 10,\n\tIMX91_PAD_GPIO_IO07 = 11,\n\tIMX91_PAD_GPIO_IO08 = 12,\n\tIMX91_PAD_GPIO_IO09 = 13,\n\tIMX91_PAD_GPIO_IO10 = 14,\n\tIMX91_PAD_GPIO_IO11 = 15,\n\tIMX91_PAD_GPIO_IO12 = 16,\n\tIMX91_PAD_GPIO_IO13 = 17,\n\tIMX91_PAD_GPIO_IO14 = 18,\n\tIMX91_PAD_GPIO_IO15 = 19,\n\tIMX91_PAD_GPIO_IO16 = 20,\n\tIMX91_PAD_GPIO_IO17 = 21,\n\tIMX91_PAD_GPIO_IO18 = 22,\n\tIMX91_PAD_GPIO_IO19 = 23,\n\tIMX91_PAD_GPIO_IO20 = 24,\n\tIMX91_PAD_GPIO_IO21 = 25,\n\tIMX91_PAD_GPIO_IO22 = 26,\n\tIMX91_PAD_GPIO_IO23 = 27,\n\tIMX91_PAD_GPIO_IO24 = 28,\n\tIMX91_PAD_GPIO_IO25 = 29,\n\tIMX91_PAD_GPIO_IO26 = 30,\n\tIMX91_PAD_GPIO_IO27 = 31,\n\tIMX91_PAD_GPIO_IO28 = 32,\n\tIMX91_PAD_GPIO_IO29 = 33,\n\tIMX91_PAD_CCM_CLKO1 = 34,\n\tIMX91_PAD_CCM_CLKO2 = 35,\n\tIMX91_PAD_CCM_CLKO3 = 36,\n\tIMX91_PAD_CCM_CLKO4 = 37,\n\tIMX91_PAD_ENET1_MDC = 38,\n\tIMX91_PAD_ENET1_MDIO = 39,\n\tIMX91_PAD_ENET1_TD3 = 40,\n\tIMX91_PAD_ENET1_TD2 = 41,\n\tIMX91_PAD_ENET1_TD1 = 42,\n\tIMX91_PAD_ENET1_TD0 = 43,\n\tIMX91_PAD_ENET1_TX_CTL = 44,\n\tIMX91_PAD_ENET1_TXC = 45,\n\tIMX91_PAD_ENET1_RX_CTL = 46,\n\tIMX91_PAD_ENET1_RXC = 47,\n\tIMX91_PAD_ENET1_RD0 = 48,\n\tIMX91_PAD_ENET1_RD1 = 49,\n\tIMX91_PAD_ENET1_RD2 = 50,\n\tIMX91_PAD_ENET1_RD3 = 51,\n\tIMX91_PAD_ENET2_MDC = 52,\n\tIMX91_PAD_ENET2_MDIO = 53,\n\tIMX91_PAD_ENET2_TD3 = 54,\n\tIMX91_PAD_ENET2_TD2 = 55,\n\tIMX91_PAD_ENET2_TD1 = 56,\n\tIMX91_PAD_ENET2_TD0 = 57,\n\tIMX91_PAD_ENET2_TX_CTL = 58,\n\tIMX91_PAD_ENET2_TXC = 59,\n\tIMX91_PAD_ENET2_RX_CTL = 60,\n\tIMX91_PAD_ENET2_RXC = 61,\n\tIMX91_PAD_ENET2_RD0 = 62,\n\tIMX91_PAD_ENET2_RD1 = 63,\n\tIMX91_PAD_ENET2_RD2 = 64,\n\tIMX91_PAD_ENET2_RD3 = 65,\n\tIMX91_PAD_SD1_CLK = 66,\n\tIMX91_PAD_SD1_CMD = 67,\n\tIMX91_PAD_SD1_DATA0 = 68,\n\tIMX91_PAD_SD1_DATA1 = 69,\n\tIMX91_PAD_SD1_DATA2 = 70,\n\tIMX91_PAD_SD1_DATA3 = 71,\n\tIMX91_PAD_SD1_DATA4 = 72,\n\tIMX91_PAD_SD1_DATA5 = 73,\n\tIMX91_PAD_SD1_DATA6 = 74,\n\tIMX91_PAD_SD1_DATA7 = 75,\n\tIMX91_PAD_SD1_STROBE = 76,\n\tIMX91_PAD_SD2_VSELECT = 77,\n\tIMX91_PAD_SD3_CLK = 78,\n\tIMX91_PAD_SD3_CMD = 79,\n\tIMX91_PAD_SD3_DATA0 = 80,\n\tIMX91_PAD_SD3_DATA1 = 81,\n\tIMX91_PAD_SD3_DATA2 = 82,\n\tIMX91_PAD_SD3_DATA3 = 83,\n\tIMX91_PAD_SD2_CD_B = 84,\n\tIMX91_PAD_SD2_CLK = 85,\n\tIMX91_PAD_SD2_CMD = 86,\n\tIMX91_PAD_SD2_DATA0 = 87,\n\tIMX91_PAD_SD2_DATA1 = 88,\n\tIMX91_PAD_SD2_DATA2 = 89,\n\tIMX91_PAD_SD2_DATA3 = 90,\n\tIMX91_PAD_SD2_RESET_B = 91,\n\tIMX91_PAD_I2C1_SCL = 92,\n\tIMX91_PAD_I2C1_SDA = 93,\n\tIMX91_PAD_I2C2_SCL = 94,\n\tIMX91_PAD_I2C2_SDA = 95,\n\tIMX91_PAD_UART1_RXD = 96,\n\tIMX91_PAD_UART1_TXD = 97,\n\tIMX91_PAD_UART2_RXD = 98,\n\tIMX91_PAD_UART2_TXD = 99,\n\tIMX91_PAD_PDM_CLK = 100,\n\tIMX91_PAD_PDM_BIT_STREAM0 = 101,\n\tIMX91_PAD_PDM_BIT_STREAM1 = 102,\n\tIMX91_PAD_SAI1_TXFS = 103,\n\tIMX91_PAD_SAI1_TXC = 104,\n\tIMX91_PAD_SAI1_TXD0 = 105,\n\tIMX91_PAD_SAI1_RXD0 = 106,\n\tIMX91_PAD_WDOG_ANY = 107,\n};\n\nenum imx93_pads {\n\tIMX93_IOMUXC_DAP_TDI = 0,\n\tIMX93_IOMUXC_DAP_TMS_SWDIO = 1,\n\tIMX93_IOMUXC_DAP_TCLK_SWCLK = 2,\n\tIMX93_IOMUXC_DAP_TDO_TRACESWO = 3,\n\tIMX93_IOMUXC_GPIO_IO00 = 4,\n\tIMX93_IOMUXC_GPIO_IO01 = 5,\n\tIMX93_IOMUXC_GPIO_IO02 = 6,\n\tIMX93_IOMUXC_GPIO_IO03 = 7,\n\tIMX93_IOMUXC_GPIO_IO04 = 8,\n\tIMX93_IOMUXC_GPIO_IO05 = 9,\n\tIMX93_IOMUXC_GPIO_IO06 = 10,\n\tIMX93_IOMUXC_GPIO_IO07 = 11,\n\tIMX93_IOMUXC_GPIO_IO08 = 12,\n\tIMX93_IOMUXC_GPIO_IO09 = 13,\n\tIMX93_IOMUXC_GPIO_IO10 = 14,\n\tIMX93_IOMUXC_GPIO_IO11 = 15,\n\tIMX93_IOMUXC_GPIO_IO12 = 16,\n\tIMX93_IOMUXC_GPIO_IO13 = 17,\n\tIMX93_IOMUXC_GPIO_IO14 = 18,\n\tIMX93_IOMUXC_GPIO_IO15 = 19,\n\tIMX93_IOMUXC_GPIO_IO16 = 20,\n\tIMX93_IOMUXC_GPIO_IO17 = 21,\n\tIMX93_IOMUXC_GPIO_IO18 = 22,\n\tIMX93_IOMUXC_GPIO_IO19 = 23,\n\tIMX93_IOMUXC_GPIO_IO20 = 24,\n\tIMX93_IOMUXC_GPIO_IO21 = 25,\n\tIMX93_IOMUXC_GPIO_IO22 = 26,\n\tIMX93_IOMUXC_GPIO_IO23 = 27,\n\tIMX93_IOMUXC_GPIO_IO24 = 28,\n\tIMX93_IOMUXC_GPIO_IO25 = 29,\n\tIMX93_IOMUXC_GPIO_IO26 = 30,\n\tIMX93_IOMUXC_GPIO_IO27 = 31,\n\tIMX93_IOMUXC_GPIO_IO28 = 32,\n\tIMX93_IOMUXC_GPIO_IO29 = 33,\n\tIMX93_IOMUXC_CCM_CLKO1 = 34,\n\tIMX93_IOMUXC_CCM_CLKO2 = 35,\n\tIMX93_IOMUXC_CCM_CLKO3 = 36,\n\tIMX93_IOMUXC_CCM_CLKO4 = 37,\n\tIMX93_IOMUXC_ENET1_MDC = 38,\n\tIMX93_IOMUXC_ENET1_MDIO = 39,\n\tIMX93_IOMUXC_ENET1_TD3 = 40,\n\tIMX93_IOMUXC_ENET1_TD2 = 41,\n\tIMX93_IOMUXC_ENET1_TD1 = 42,\n\tIMX93_IOMUXC_ENET1_TD0 = 43,\n\tIMX93_IOMUXC_ENET1_TX_CTL = 44,\n\tIMX93_IOMUXC_ENET1_TXC = 45,\n\tIMX93_IOMUXC_ENET1_RX_CTL = 46,\n\tIMX93_IOMUXC_ENET1_RXC = 47,\n\tIMX93_IOMUXC_ENET1_RD0 = 48,\n\tIMX93_IOMUXC_ENET1_RD1 = 49,\n\tIMX93_IOMUXC_ENET1_RD2 = 50,\n\tIMX93_IOMUXC_ENET1_RD3 = 51,\n\tIMX93_IOMUXC_ENET2_MDC = 52,\n\tIMX93_IOMUXC_ENET2_MDIO = 53,\n\tIMX93_IOMUXC_ENET2_TD3 = 54,\n\tIMX93_IOMUXC_ENET2_TD2 = 55,\n\tIMX93_IOMUXC_ENET2_TD1 = 56,\n\tIMX93_IOMUXC_ENET2_TD0 = 57,\n\tIMX93_IOMUXC_ENET2_TX_CTL = 58,\n\tIMX93_IOMUXC_ENET2_TXC = 59,\n\tIMX93_IOMUXC_ENET2_RX_CTL = 60,\n\tIMX93_IOMUXC_ENET2_RXC = 61,\n\tIMX93_IOMUXC_ENET2_RD0 = 62,\n\tIMX93_IOMUXC_ENET2_RD1 = 63,\n\tIMX93_IOMUXC_ENET2_RD2 = 64,\n\tIMX93_IOMUXC_ENET2_RD3 = 65,\n\tIMX93_IOMUXC_SD1_CLK = 66,\n\tIMX93_IOMUXC_SD1_CMD = 67,\n\tIMX93_IOMUXC_SD1_DATA0 = 68,\n\tIMX93_IOMUXC_SD1_DATA1 = 69,\n\tIMX93_IOMUXC_SD1_DATA2 = 70,\n\tIMX93_IOMUXC_SD1_DATA3 = 71,\n\tIMX93_IOMUXC_SD1_DATA4 = 72,\n\tIMX93_IOMUXC_SD1_DATA5 = 73,\n\tIMX93_IOMUXC_SD1_DATA6 = 74,\n\tIMX93_IOMUXC_SD1_DATA7 = 75,\n\tIMX93_IOMUXC_SD1_STROBE = 76,\n\tIMX93_IOMUXC_SD2_VSELECT = 77,\n\tIMX93_IOMUXC_SD3_CLK = 78,\n\tIMX93_IOMUXC_SD3_CMD = 79,\n\tIMX93_IOMUXC_SD3_DATA0 = 80,\n\tIMX93_IOMUXC_SD3_DATA1 = 81,\n\tIMX93_IOMUXC_SD3_DATA2 = 82,\n\tIMX93_IOMUXC_SD3_DATA3 = 83,\n\tIMX93_IOMUXC_SD2_CD_B = 84,\n\tIMX93_IOMUXC_SD2_CLK = 85,\n\tIMX93_IOMUXC_SD2_CMD = 86,\n\tIMX93_IOMUXC_SD2_DATA0 = 87,\n\tIMX93_IOMUXC_SD2_DATA1 = 88,\n\tIMX93_IOMUXC_SD2_DATA2 = 89,\n\tIMX93_IOMUXC_SD2_DATA3 = 90,\n\tIMX93_IOMUXC_SD2_RESET_B = 91,\n\tIMX93_IOMUXC_I2C1_SCL = 92,\n\tIMX93_IOMUXC_I2C1_SDA = 93,\n\tIMX93_IOMUXC_I2C2_SCL = 94,\n\tIMX93_IOMUXC_I2C2_SDA = 95,\n\tIMX93_IOMUXC_UART1_RXD = 96,\n\tIMX93_IOMUXC_UART1_TXD = 97,\n\tIMX93_IOMUXC_UART2_RXD = 98,\n\tIMX93_IOMUXC_UART2_TXD = 99,\n\tIMX93_IOMUXC_PDM_CLK = 100,\n\tIMX93_IOMUXC_PDM_BIT_STREAM0 = 101,\n\tIMX93_IOMUXC_PDM_BIT_STREAM1 = 102,\n\tIMX93_IOMUXC_SAI1_TXFS = 103,\n\tIMX93_IOMUXC_SAI1_TXC = 104,\n\tIMX93_IOMUXC_SAI1_TXD0 = 105,\n\tIMX93_IOMUXC_SAI1_RXD0 = 106,\n\tIMX93_IOMUXC_WDOG_ANY = 107,\n};\n\nenum imx_i2c_state {\n\tIMX_I2C_STATE_DONE = 0,\n\tIMX_I2C_STATE_FAILED = 1,\n\tIMX_I2C_STATE_WRITE = 2,\n\tIMX_I2C_STATE_DMA = 3,\n\tIMX_I2C_STATE_READ = 4,\n\tIMX_I2C_STATE_READ_CONTINUE = 5,\n\tIMX_I2C_STATE_READ_BLOCK_DATA = 6,\n\tIMX_I2C_STATE_READ_BLOCK_DATA_LEN = 7,\n};\n\nenum imx_i2c_type {\n\tIMX1_I2C = 0,\n\tIMX21_I2C = 1,\n\tS32G_I2C = 2,\n\tVF610_I2C = 3,\n};\n\nenum imx_misc_func {\n\tIMX_SC_MISC_FUNC_UNKNOWN = 0,\n\tIMX_SC_MISC_FUNC_SET_CONTROL = 1,\n\tIMX_SC_MISC_FUNC_GET_CONTROL = 2,\n\tIMX_SC_MISC_FUNC_SET_MAX_DMA_GROUP = 4,\n\tIMX_SC_MISC_FUNC_SET_DMA_GROUP = 5,\n\tIMX_SC_MISC_FUNC_SECO_IMAGE_LOAD = 8,\n\tIMX_SC_MISC_FUNC_SECO_AUTHENTICATE = 9,\n\tIMX_SC_MISC_FUNC_DEBUG_OUT = 10,\n\tIMX_SC_MISC_FUNC_WAVEFORM_CAPTURE = 6,\n\tIMX_SC_MISC_FUNC_BUILD_INFO = 15,\n\tIMX_SC_MISC_FUNC_UNIQUE_ID = 19,\n\tIMX_SC_MISC_FUNC_SET_ARI = 3,\n\tIMX_SC_MISC_FUNC_BOOT_STATUS = 7,\n\tIMX_SC_MISC_FUNC_BOOT_DONE = 14,\n\tIMX_SC_MISC_FUNC_OTP_FUSE_READ = 11,\n\tIMX_SC_MISC_FUNC_OTP_FUSE_WRITE = 17,\n\tIMX_SC_MISC_FUNC_SET_TEMP = 12,\n\tIMX_SC_MISC_FUNC_GET_TEMP = 13,\n\tIMX_SC_MISC_FUNC_GET_BOOT_DEV = 16,\n\tIMX_SC_MISC_FUNC_GET_BUTTON_STATUS = 18,\n};\n\nenum imx_mu_chan_type {\n\tIMX_MU_TYPE_TX = 0,\n\tIMX_MU_TYPE_RX = 1,\n\tIMX_MU_TYPE_TXDB = 2,\n\tIMX_MU_TYPE_RXDB = 3,\n\tIMX_MU_TYPE_RST = 4,\n\tIMX_MU_TYPE_TXDB_V2 = 5,\n};\n\nenum imx_mu_type {\n\tIMX_MU_V1 = 0,\n\tIMX_MU_V2 = 2,\n\tIMX_MU_V2_S4 = 32768,\n\tIMX_MU_V2_IRQ = 65536,\n};\n\nenum imx_mu_xcr {\n\tIMX_MU_CR = 0,\n\tIMX_MU_GIER = 1,\n\tIMX_MU_GCR = 2,\n\tIMX_MU_TCR = 3,\n\tIMX_MU_RCR = 4,\n\tIMX_MU_xCR_MAX = 5,\n};\n\nenum imx_mu_xsr {\n\tIMX_MU_SR = 0,\n\tIMX_MU_GSR = 1,\n\tIMX_MU_TSR = 2,\n\tIMX_MU_RSR = 3,\n\tIMX_MU_xSR_MAX = 4,\n};\n\nenum imx_pcie_variants {\n\tIMX6Q = 0,\n\tIMX6SX = 1,\n\tIMX6QP = 2,\n\tIMX7D = 3,\n\tIMX8MQ = 4,\n\tIMX8MM___2 = 5,\n\tIMX8MP___2 = 6,\n\tIMX8Q = 7,\n\tIMX95 = 8,\n\tIMX8MQ_EP = 9,\n\tIMX8MM_EP = 10,\n\tIMX8MP_EP = 11,\n\tIMX8Q_EP = 12,\n\tIMX95_EP = 13,\n};\n\nenum imx_pfdv2_type {\n\tIMX_PFDV2_IMX7ULP = 0,\n\tIMX_PFDV2_IMX8ULP = 1,\n};\n\nenum imx_pll14xx_type {\n\tPLL_1416X = 0,\n\tPLL_1443X = 1,\n};\n\nenum imx_pllv1_type {\n\tIMX_PLLV1_IMX1 = 0,\n\tIMX_PLLV1_IMX21 = 1,\n\tIMX_PLLV1_IMX25 = 2,\n\tIMX_PLLV1_IMX27 = 3,\n\tIMX_PLLV1_IMX31 = 4,\n\tIMX_PLLV1_IMX35 = 5,\n};\n\nenum imx_pllv3_type {\n\tIMX_PLLV3_GENERIC = 0,\n\tIMX_PLLV3_SYS = 1,\n\tIMX_PLLV3_USB = 2,\n\tIMX_PLLV3_USB_VF610 = 3,\n\tIMX_PLLV3_AV = 4,\n\tIMX_PLLV3_ENET = 5,\n\tIMX_PLLV3_ENET_IMX7 = 6,\n\tIMX_PLLV3_SYS_VF610 = 7,\n\tIMX_PLLV3_DDR_IMX7 = 8,\n\tIMX_PLLV3_AV_IMX7 = 9,\n};\n\nenum imx_pllv4_type {\n\tIMX_PLLV4_IMX7ULP = 0,\n\tIMX_PLLV4_IMX8ULP = 1,\n\tIMX_PLLV4_IMX8ULP_1GHZ = 2,\n};\n\nenum imx_sc_error_codes {\n\tIMX_SC_ERR_NONE = 0,\n\tIMX_SC_ERR_VERSION = 1,\n\tIMX_SC_ERR_CONFIG = 2,\n\tIMX_SC_ERR_PARM = 3,\n\tIMX_SC_ERR_NOACCESS = 4,\n\tIMX_SC_ERR_LOCKED = 5,\n\tIMX_SC_ERR_UNAVAILABLE = 6,\n\tIMX_SC_ERR_NOTFOUND = 7,\n\tIMX_SC_ERR_NOPOWER = 8,\n\tIMX_SC_ERR_IPC = 9,\n\tIMX_SC_ERR_BUSY = 10,\n\tIMX_SC_ERR_FAIL = 11,\n\tIMX_SC_ERR_LAST = 12,\n};\n\nenum imx_sc_pm_func {\n\tIMX_SC_PM_FUNC_UNKNOWN = 0,\n\tIMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19,\n\tIMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1,\n\tIMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2,\n\tIMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3,\n\tIMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4,\n\tIMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16,\n\tIMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17,\n\tIMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18,\n\tIMX_SC_PM_FUNC_SET_CLOCK_RATE = 5,\n\tIMX_SC_PM_FUNC_GET_CLOCK_RATE = 6,\n\tIMX_SC_PM_FUNC_CLOCK_ENABLE = 7,\n\tIMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14,\n\tIMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15,\n\tIMX_SC_PM_FUNC_RESET = 13,\n\tIMX_SC_PM_FUNC_RESET_REASON = 10,\n\tIMX_SC_PM_FUNC_BOOT = 8,\n\tIMX_SC_PM_FUNC_REBOOT = 9,\n\tIMX_SC_PM_FUNC_REBOOT_PARTITION = 12,\n\tIMX_SC_PM_FUNC_CPU_START = 11,\n};\n\nenum imx_sc_rm_func {\n\tIMX_SC_RM_FUNC_UNKNOWN = 0,\n\tIMX_SC_RM_FUNC_PARTITION_ALLOC = 1,\n\tIMX_SC_RM_FUNC_SET_CONFIDENTIAL = 31,\n\tIMX_SC_RM_FUNC_PARTITION_FREE = 2,\n\tIMX_SC_RM_FUNC_GET_DID = 26,\n\tIMX_SC_RM_FUNC_PARTITION_STATIC = 3,\n\tIMX_SC_RM_FUNC_PARTITION_LOCK = 4,\n\tIMX_SC_RM_FUNC_GET_PARTITION = 5,\n\tIMX_SC_RM_FUNC_SET_PARENT = 6,\n\tIMX_SC_RM_FUNC_MOVE_ALL = 7,\n\tIMX_SC_RM_FUNC_ASSIGN_RESOURCE = 8,\n\tIMX_SC_RM_FUNC_SET_RESOURCE_MOVABLE = 9,\n\tIMX_SC_RM_FUNC_SET_SUBSYS_RSRC_MOVABLE = 28,\n\tIMX_SC_RM_FUNC_SET_MASTER_ATTRIBUTES = 10,\n\tIMX_SC_RM_FUNC_SET_MASTER_SID = 11,\n\tIMX_SC_RM_FUNC_SET_PERIPHERAL_PERMISSIONS = 12,\n\tIMX_SC_RM_FUNC_IS_RESOURCE_OWNED = 13,\n\tIMX_SC_RM_FUNC_GET_RESOURCE_OWNER = 33,\n\tIMX_SC_RM_FUNC_IS_RESOURCE_MASTER = 14,\n\tIMX_SC_RM_FUNC_IS_RESOURCE_PERIPHERAL = 15,\n\tIMX_SC_RM_FUNC_GET_RESOURCE_INFO = 16,\n\tIMX_SC_RM_FUNC_MEMREG_ALLOC = 17,\n\tIMX_SC_RM_FUNC_MEMREG_SPLIT = 29,\n\tIMX_SC_RM_FUNC_MEMREG_FRAG = 32,\n\tIMX_SC_RM_FUNC_MEMREG_FREE = 18,\n\tIMX_SC_RM_FUNC_FIND_MEMREG = 30,\n\tIMX_SC_RM_FUNC_ASSIGN_MEMREG = 19,\n\tIMX_SC_RM_FUNC_SET_MEMREG_PERMISSIONS = 20,\n\tIMX_SC_RM_FUNC_IS_MEMREG_OWNED = 21,\n\tIMX_SC_RM_FUNC_GET_MEMREG_INFO = 22,\n\tIMX_SC_RM_FUNC_ASSIGN_PAD = 23,\n\tIMX_SC_RM_FUNC_SET_PAD_MOVABLE = 24,\n\tIMX_SC_RM_FUNC_IS_PAD_OWNED = 25,\n\tIMX_SC_RM_FUNC_DUMP = 27,\n};\n\nenum imx_sc_rpc_svc {\n\tIMX_SC_RPC_SVC_UNKNOWN = 0,\n\tIMX_SC_RPC_SVC_RETURN = 1,\n\tIMX_SC_RPC_SVC_PM = 2,\n\tIMX_SC_RPC_SVC_RM = 3,\n\tIMX_SC_RPC_SVC_TIMER = 5,\n\tIMX_SC_RPC_SVC_PAD = 6,\n\tIMX_SC_RPC_SVC_MISC = 7,\n\tIMX_SC_RPC_SVC_IRQ = 8,\n};\n\nenum imx_tx_state {\n\tOFF = 0,\n\tWAIT_AFTER_RTS = 1,\n\tSEND = 2,\n\tWAIT_AFTER_SEND = 3,\n};\n\nenum imx_uart_type {\n\tIMX1_UART = 0,\n\tIMX21_UART = 1,\n};\n\nenum inband_type {\n\tINBAND_NONE = 0,\n\tINBAND_CISCO_SGMII = 1,\n\tINBAND_BASEX = 2,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum interconnect_desc_param {\n\tINTERCONNECT_DESC_PARAM_LEN = 0,\n\tINTERCONNECT_DESC_PARAM_TYPE = 1,\n\tINTERCONNECT_DESC_PARAM_UNIPRO_VER = 2,\n\tINTERCONNECT_DESC_PARAM_MPHY_VER = 4,\n};\n\nenum io_pgtable_caps {\n\tIO_PGTABLE_CAP_CUSTOM_ALLOCATOR = 1,\n};\n\nenum io_pgtable_fmt {\n\tARM_32_LPAE_S1 = 0,\n\tARM_32_LPAE_S2 = 1,\n\tARM_64_LPAE_S1 = 2,\n\tARM_64_LPAE_S2 = 3,\n\tARM_V7S = 4,\n\tARM_MALI_LPAE = 5,\n\tAPPLE_DART = 6,\n\tAPPLE_DART2 = 7,\n\tIO_PGTABLE_NUM_FMTS = 8,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioctrl_regs {\n\tPOC0 = 0,\n\tPOC1 = 1,\n\tPOC3 = 2,\n\tPOC4 = 3,\n\tPOC5 = 4,\n\tPOC6 = 5,\n\tPOC7 = 6,\n\tPOC8 = 7,\n};\n\nenum ioctrl_regs___2 {\n\tPOC0___2 = 0,\n\tPOC1___2 = 1,\n\tPOC2 = 2,\n\tPOC4___2 = 3,\n\tPOC5___2 = 4,\n\tPOC6___2 = 5,\n\tPOC7___2 = 6,\n\tPOC8___2 = 7,\n\tPOC9 = 8,\n\tTD1SEL0 = 9,\n};\n\nenum ioctrl_regs___3 {\n\tPOC0___3 = 0,\n\tPOC1___3 = 1,\n\tPOC3___2 = 2,\n\tPOC4___3 = 3,\n\tPOC5___3 = 4,\n\tPOC6___3 = 5,\n\tPOC7___3 = 6,\n};\n\nenum ioctrl_regs___4 {\n\tPOCCTRL = 0,\n\tTDSELCTRL = 1,\n};\n\nenum ioctrl_regs___5 {\n\tPOCCTRL0 = 0,\n\tPOCCTRL1 = 1,\n\tPOCCTRL2 = 2,\n\tPOCCTRL3 = 3,\n\tTDSELCTRL___2 = 4,\n};\n\nenum ioctrl_regs___6 {\n\tPOCCTRL0___2 = 0,\n\tPOCCTRL2___2 = 1,\n\tTDSELCTRL___3 = 2,\n};\n\nenum ioctrl_regs___7 {\n\tPOC0___4 = 0,\n\tPOC1___4 = 1,\n\tPOC3___3 = 2,\n\tTD0SEL1 = 3,\n};\n\nenum ioctrl_regs___8 {\n\tPOCCTRL0___3 = 0,\n\tPOCCTRL1___2 = 1,\n\tPOCCTRL2___3 = 2,\n\tTDSELCTRL___4 = 3,\n};\n\nenum iodev_type {\n\tIODEV_CPUIF = 0,\n\tIODEV_DIST = 1,\n\tIODEV_REDIST = 2,\n\tIODEV_ITS = 3,\n};\n\nenum iommu_atf_cmd {\n\tIOMMU_ATF_CMD_CONFIG_SMI_LARB = 0,\n\tIOMMU_ATF_CMD_CONFIG_INFRA_IOMMU = 1,\n\tIOMMU_ATF_CMD_MAX = 2,\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_NOEXEC = 1,\n\tIOMMU_CAP_PRE_BOOT_PROTECTION = 2,\n\tIOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3,\n\tIOMMU_CAP_DEFERRED_FLUSH = 4,\n\tIOMMU_CAP_DIRTY_TRACKING = 5,\n};\n\nenum iommu_dma_queue_type {\n\tIOMMU_DMA_OPTS_PER_CPU_QUEUE = 0,\n\tIOMMU_DMA_OPTS_SINGLE_QUEUE = 1,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum iommu_fault_type {\n\tIOMMU_FAULT_PAGE_REQ = 1,\n};\n\nenum iommu_hw_info_type {\n\tIOMMU_HW_INFO_TYPE_NONE = 0,\n\tIOMMU_HW_INFO_TYPE_DEFAULT = 0,\n\tIOMMU_HW_INFO_TYPE_INTEL_VTD = 1,\n\tIOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,\n\tIOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,\n\tIOMMU_HW_INFO_TYPE_AMD = 4,\n};\n\nenum iommu_hw_queue_type {\n\tIOMMU_HW_QUEUE_TYPE_DEFAULT = 0,\n\tIOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,\n};\n\nenum iommu_page_response_code {\n\tIOMMU_PAGE_RESP_SUCCESS = 0,\n\tIOMMU_PAGE_RESP_INVALID = 1,\n\tIOMMU_PAGE_RESP_FAILURE = 2,\n};\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nenum iommu_viommu_type {\n\tIOMMU_VIOMMU_TYPE_DEFAULT = 0,\n\tIOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,\n\tIOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,\n};\n\nenum iommufd_hwpt_alloc_flags {\n\tIOMMU_HWPT_ALLOC_NEST_PARENT = 1,\n\tIOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2,\n\tIOMMU_HWPT_FAULT_ID_VALID = 4,\n\tIOMMU_HWPT_ALLOC_PASID = 8,\n};\n\nenum iommufd_object_type {\n\tIOMMUFD_OBJ_NONE = 0,\n\tIOMMUFD_OBJ_ANY = 0,\n\tIOMMUFD_OBJ_DEVICE = 1,\n\tIOMMUFD_OBJ_HWPT_PAGING = 2,\n\tIOMMUFD_OBJ_HWPT_NESTED = 3,\n\tIOMMUFD_OBJ_IOAS = 4,\n\tIOMMUFD_OBJ_ACCESS = 5,\n\tIOMMUFD_OBJ_FAULT = 6,\n\tIOMMUFD_OBJ_VIOMMU = 7,\n\tIOMMUFD_OBJ_VDEVICE = 8,\n\tIOMMUFD_OBJ_VEVENTQ = 9,\n\tIOMMUFD_OBJ_HW_QUEUE = 10,\n\tIOMMUFD_OBJ_MAX = 11,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_conntrack_info {\n\tIP_CT_ESTABLISHED = 0,\n\tIP_CT_RELATED = 1,\n\tIP_CT_NEW = 2,\n\tIP_CT_IS_REPLY = 3,\n\tIP_CT_ESTABLISHED_REPLY = 3,\n\tIP_CT_RELATED_REPLY = 4,\n\tIP_CT_NUMBER = 5,\n\tIP_CT_UNTRACKED = 7,\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum ip_ver_legacy {\n\tIP_LEGACY_VER_MT6781 = 272105472,\n\tIP_LEGACY_VER_MT6879 = 271974400,\n\tIP_LEGACY_VER_MT6893 = 538314502,\n};\n\nenum ipi_msg_type {\n\tIPI_RESCHEDULE = 0,\n\tIPI_CALL_FUNC = 1,\n\tIPI_CPU_STOP = 2,\n\tIPI_CPU_STOP_NMI = 3,\n\tIPI_TIMER = 4,\n\tIPI_IRQ_WORK = 5,\n\tNR_IPI = 6,\n\tIPI_CPU_BACKTRACE = 6,\n\tIPI_KGDB_ROUNDUP = 7,\n\tMAX_IPI = 8,\n};\n\nenum ipi_vector {\n\tXEN_PLACEHOLDER_VECTOR = 0,\n\tXEN_NR_IPIS = 1,\n};\n\nenum ipmi_addr_space {\n\tIPMI_IO_ADDR_SPACE = 0,\n\tIPMI_MEM_ADDR_SPACE = 1,\n};\n\nenum ipmi_addr_src {\n\tSI_INVALID = 0,\n\tSI_HOTMOD = 1,\n\tSI_HARDCODED = 2,\n\tSI_SPMI = 3,\n\tSI_ACPI = 4,\n\tSI_SMBIOS = 5,\n\tSI_PCI = 6,\n\tSI_DEVICETREE = 7,\n\tSI_PLATFORM = 8,\n\tSI_LAST = 9,\n};\n\nenum ipmi_plat_interface_type {\n\tIPMI_PLAT_IF_SI = 0,\n\tIPMI_PLAT_IF_SSIF = 1,\n};\n\nenum ipq5018_functions {\n\tmsm_mux_atest_char = 0,\n\tmsm_mux_audio_pdm0 = 1,\n\tmsm_mux_audio_pdm1 = 2,\n\tmsm_mux_audio_rxbclk = 3,\n\tmsm_mux_audio_rxd = 4,\n\tmsm_mux_audio_rxfsync = 5,\n\tmsm_mux_audio_rxmclk = 6,\n\tmsm_mux_audio_txbclk = 7,\n\tmsm_mux_audio_txd = 8,\n\tmsm_mux_audio_txfsync = 9,\n\tmsm_mux_audio_txmclk = 10,\n\tmsm_mux_blsp0_i2c = 11,\n\tmsm_mux_blsp0_spi = 12,\n\tmsm_mux_blsp0_uart0 = 13,\n\tmsm_mux_blsp0_uart1 = 14,\n\tmsm_mux_blsp1_i2c0 = 15,\n\tmsm_mux_blsp1_i2c1 = 16,\n\tmsm_mux_blsp1_spi0 = 17,\n\tmsm_mux_blsp1_spi1 = 18,\n\tmsm_mux_blsp1_uart0 = 19,\n\tmsm_mux_blsp1_uart1 = 20,\n\tmsm_mux_blsp1_uart2 = 21,\n\tmsm_mux_blsp2_i2c0 = 22,\n\tmsm_mux_blsp2_i2c1 = 23,\n\tmsm_mux_blsp2_spi = 24,\n\tmsm_mux_blsp2_spi0 = 25,\n\tmsm_mux_blsp2_spi1 = 26,\n\tmsm_mux_btss = 27,\n\tmsm_mux_burn0 = 28,\n\tmsm_mux_burn1 = 29,\n\tmsm_mux_cri_trng = 30,\n\tmsm_mux_cri_trng0 = 31,\n\tmsm_mux_cri_trng1 = 32,\n\tmsm_mux_cxc_clk = 33,\n\tmsm_mux_cxc_data = 34,\n\tmsm_mux_dbg_out = 35,\n\tmsm_mux_eud_gpio = 36,\n\tmsm_mux_gcc_plltest = 37,\n\tmsm_mux_gcc_tlmm = 38,\n\tmsm_mux_gpio = 39,\n\tmsm_mux_led0 = 40,\n\tmsm_mux_led2 = 41,\n\tmsm_mux_mac0 = 42,\n\tmsm_mux_mac1 = 43,\n\tmsm_mux_mdc = 44,\n\tmsm_mux_mdio = 45,\n\tmsm_mux_pcie0_clk = 46,\n\tmsm_mux_pcie0_wake = 47,\n\tmsm_mux_pcie1_clk = 48,\n\tmsm_mux_pcie1_wake = 49,\n\tmsm_mux_pll_test = 50,\n\tmsm_mux_prng_rosc = 51,\n\tmsm_mux_pwm0 = 52,\n\tmsm_mux_pwm1 = 53,\n\tmsm_mux_pwm2 = 54,\n\tmsm_mux_pwm3 = 55,\n\tmsm_mux_qdss_cti_trig_in_a0 = 56,\n\tmsm_mux_qdss_cti_trig_in_a1 = 57,\n\tmsm_mux_qdss_cti_trig_in_b0 = 58,\n\tmsm_mux_qdss_cti_trig_in_b1 = 59,\n\tmsm_mux_qdss_cti_trig_out_a0 = 60,\n\tmsm_mux_qdss_cti_trig_out_a1 = 61,\n\tmsm_mux_qdss_cti_trig_out_b0 = 62,\n\tmsm_mux_qdss_cti_trig_out_b1 = 63,\n\tmsm_mux_qdss_traceclk_a = 64,\n\tmsm_mux_qdss_traceclk_b = 65,\n\tmsm_mux_qdss_tracectl_a = 66,\n\tmsm_mux_qdss_tracectl_b = 67,\n\tmsm_mux_qdss_tracedata_a = 68,\n\tmsm_mux_qdss_tracedata_b = 69,\n\tmsm_mux_qspi_clk = 70,\n\tmsm_mux_qspi_cs = 71,\n\tmsm_mux_qspi_data = 72,\n\tmsm_mux_reset_out = 73,\n\tmsm_mux_sdc1_clk = 74,\n\tmsm_mux_sdc1_cmd = 75,\n\tmsm_mux_sdc1_data = 76,\n\tmsm_mux_wci_txd = 77,\n\tmsm_mux_wci_rxd = 78,\n\tmsm_mux_wsa_swrm = 79,\n\tmsm_mux_wsi_clk3 = 80,\n\tmsm_mux_wsi_data3 = 81,\n\tmsm_mux_wsis_reset = 82,\n\tmsm_mux_xfem = 83,\n\tmsm_mux__ = 84,\n};\n\nenum ipq5332_functions {\n\tmsm_mux_atest_char___2 = 0,\n\tmsm_mux_atest_char0 = 1,\n\tmsm_mux_atest_char1 = 2,\n\tmsm_mux_atest_char2 = 3,\n\tmsm_mux_atest_char3 = 4,\n\tmsm_mux_atest_tic = 5,\n\tmsm_mux_audio_pri = 6,\n\tmsm_mux_audio_pri0 = 7,\n\tmsm_mux_audio_pri1 = 8,\n\tmsm_mux_audio_sec = 9,\n\tmsm_mux_audio_sec0 = 10,\n\tmsm_mux_audio_sec1 = 11,\n\tmsm_mux_blsp0_i2c___2 = 12,\n\tmsm_mux_blsp0_spi___2 = 13,\n\tmsm_mux_blsp0_uart0___2 = 14,\n\tmsm_mux_blsp0_uart1___2 = 15,\n\tmsm_mux_blsp1_i2c0___2 = 16,\n\tmsm_mux_blsp1_i2c1___2 = 17,\n\tmsm_mux_blsp1_spi0___2 = 18,\n\tmsm_mux_blsp1_spi1___2 = 19,\n\tmsm_mux_blsp1_uart0___2 = 20,\n\tmsm_mux_blsp1_uart1___2 = 21,\n\tmsm_mux_blsp1_uart2___2 = 22,\n\tmsm_mux_blsp2_i2c0___2 = 23,\n\tmsm_mux_blsp2_i2c1___2 = 24,\n\tmsm_mux_blsp2_spi___2 = 25,\n\tmsm_mux_blsp2_spi0___2 = 26,\n\tmsm_mux_blsp2_spi1___2 = 27,\n\tmsm_mux_core_voltage = 28,\n\tmsm_mux_cri_trng0___2 = 29,\n\tmsm_mux_cri_trng1___2 = 30,\n\tmsm_mux_cri_trng2 = 31,\n\tmsm_mux_cri_trng3 = 32,\n\tmsm_mux_cxc_clk___2 = 33,\n\tmsm_mux_cxc_data___2 = 34,\n\tmsm_mux_dbg_out___2 = 35,\n\tmsm_mux_gcc_plltest___2 = 36,\n\tmsm_mux_gcc_tlmm___2 = 37,\n\tmsm_mux_gpio___2 = 38,\n\tmsm_mux_lock_det = 39,\n\tmsm_mux_mac0___2 = 40,\n\tmsm_mux_mac1___2 = 41,\n\tmsm_mux_mdc0 = 42,\n\tmsm_mux_mdc1 = 43,\n\tmsm_mux_mdio0 = 44,\n\tmsm_mux_mdio1 = 45,\n\tmsm_mux_pc = 46,\n\tmsm_mux_pcie0_clk___2 = 47,\n\tmsm_mux_pcie0_wake___2 = 48,\n\tmsm_mux_pcie1_clk___2 = 49,\n\tmsm_mux_pcie1_wake___2 = 50,\n\tmsm_mux_pcie2_clk = 51,\n\tmsm_mux_pcie2_wake = 52,\n\tmsm_mux_pll_test___2 = 53,\n\tmsm_mux_prng_rosc0 = 54,\n\tmsm_mux_prng_rosc1 = 55,\n\tmsm_mux_prng_rosc2 = 56,\n\tmsm_mux_prng_rosc3 = 57,\n\tmsm_mux_pta = 58,\n\tmsm_mux_pwm0___2 = 59,\n\tmsm_mux_pwm1___2 = 60,\n\tmsm_mux_pwm2___2 = 61,\n\tmsm_mux_pwm3___2 = 62,\n\tmsm_mux_qdss_cti_trig_in_a0___2 = 63,\n\tmsm_mux_qdss_cti_trig_in_a1___2 = 64,\n\tmsm_mux_qdss_cti_trig_in_b0___2 = 65,\n\tmsm_mux_qdss_cti_trig_in_b1___2 = 66,\n\tmsm_mux_qdss_cti_trig_out_a0___2 = 67,\n\tmsm_mux_qdss_cti_trig_out_a1___2 = 68,\n\tmsm_mux_qdss_cti_trig_out_b0___2 = 69,\n\tmsm_mux_qdss_cti_trig_out_b1___2 = 70,\n\tmsm_mux_qdss_traceclk_a___2 = 71,\n\tmsm_mux_qdss_traceclk_b___2 = 72,\n\tmsm_mux_qdss_tracectl_a___2 = 73,\n\tmsm_mux_qdss_tracectl_b___2 = 74,\n\tmsm_mux_qdss_tracedata_a___2 = 75,\n\tmsm_mux_qdss_tracedata_b___2 = 76,\n\tmsm_mux_qspi_data___2 = 77,\n\tmsm_mux_qspi_clk___2 = 78,\n\tmsm_mux_qspi_cs___2 = 79,\n\tmsm_mux_resout = 80,\n\tmsm_mux_rx0 = 81,\n\tmsm_mux_rx1 = 82,\n\tmsm_mux_sdc_data = 83,\n\tmsm_mux_sdc_clk = 84,\n\tmsm_mux_sdc_cmd = 85,\n\tmsm_mux_tsens_max = 86,\n\tmsm_mux_wci_txd___2 = 87,\n\tmsm_mux_wci_rxd___2 = 88,\n\tmsm_mux_wsi_clk = 89,\n\tmsm_mux_wsi_clk3___2 = 90,\n\tmsm_mux_wsi_data = 91,\n\tmsm_mux_wsi_data3___2 = 92,\n\tmsm_mux_wsis_reset___2 = 93,\n\tmsm_mux_xfem___2 = 94,\n\tmsm_mux_____2 = 95,\n};\n\nenum ipq5424_functions {\n\tmsm_mux_atest_char___3 = 0,\n\tmsm_mux_atest_char0___2 = 1,\n\tmsm_mux_atest_char1___2 = 2,\n\tmsm_mux_atest_char2___2 = 3,\n\tmsm_mux_atest_char3___2 = 4,\n\tmsm_mux_atest_tic___2 = 5,\n\tmsm_mux_audio_pri___2 = 6,\n\tmsm_mux_audio_pri0___2 = 7,\n\tmsm_mux_audio_pri1___2 = 8,\n\tmsm_mux_audio_sec___2 = 9,\n\tmsm_mux_audio_sec0___2 = 10,\n\tmsm_mux_audio_sec1___2 = 11,\n\tmsm_mux_core_voltage___2 = 12,\n\tmsm_mux_cri_trng0___3 = 13,\n\tmsm_mux_cri_trng1___3 = 14,\n\tmsm_mux_cri_trng2___2 = 15,\n\tmsm_mux_cri_trng3___2 = 16,\n\tmsm_mux_cxc_clk___3 = 17,\n\tmsm_mux_cxc_data___3 = 18,\n\tmsm_mux_dbg_out___3 = 19,\n\tmsm_mux_gcc_plltest___3 = 20,\n\tmsm_mux_gcc_tlmm___3 = 21,\n\tmsm_mux_gpio___3 = 22,\n\tmsm_mux_i2c0_scl = 23,\n\tmsm_mux_i2c0_sda = 24,\n\tmsm_mux_i2c1_scl = 25,\n\tmsm_mux_i2c1_sda = 26,\n\tmsm_mux_i2c11 = 27,\n\tmsm_mux_mac0___3 = 28,\n\tmsm_mux_mac1___3 = 29,\n\tmsm_mux_mdc_mst = 30,\n\tmsm_mux_mdc_slv = 31,\n\tmsm_mux_mdio_mst = 32,\n\tmsm_mux_mdio_slv = 33,\n\tmsm_mux_pcie0_clk___3 = 34,\n\tmsm_mux_pcie0_wake___3 = 35,\n\tmsm_mux_pcie1_clk___3 = 36,\n\tmsm_mux_pcie1_wake___3 = 37,\n\tmsm_mux_pcie2_clk___2 = 38,\n\tmsm_mux_pcie2_wake___2 = 39,\n\tmsm_mux_pcie3_clk = 40,\n\tmsm_mux_pcie3_wake = 41,\n\tmsm_mux_pll_test___3 = 42,\n\tmsm_mux_prng_rosc0___2 = 43,\n\tmsm_mux_prng_rosc1___2 = 44,\n\tmsm_mux_prng_rosc2___2 = 45,\n\tmsm_mux_prng_rosc3___2 = 46,\n\tmsm_mux_PTA0_0 = 47,\n\tmsm_mux_PTA0_1 = 48,\n\tmsm_mux_PTA0_2 = 49,\n\tmsm_mux_PTA10 = 50,\n\tmsm_mux_PTA11 = 51,\n\tmsm_mux_pwm0___3 = 52,\n\tmsm_mux_pwm1___3 = 53,\n\tmsm_mux_pwm2___3 = 54,\n\tmsm_mux_qdss_cti_trig_in_a0___3 = 55,\n\tmsm_mux_qdss_cti_trig_out_a0___3 = 56,\n\tmsm_mux_qdss_cti_trig_in_a1___3 = 57,\n\tmsm_mux_qdss_cti_trig_out_a1___3 = 58,\n\tmsm_mux_qdss_cti_trig_in_b0___3 = 59,\n\tmsm_mux_qdss_cti_trig_out_b0___3 = 60,\n\tmsm_mux_qdss_cti_trig_in_b1___3 = 61,\n\tmsm_mux_qdss_cti_trig_out_b1___3 = 62,\n\tmsm_mux_qdss_traceclk_a___3 = 63,\n\tmsm_mux_qdss_tracectl_a___3 = 64,\n\tmsm_mux_qdss_tracedata_a___3 = 65,\n\tmsm_mux_qspi_clk___3 = 66,\n\tmsm_mux_qspi_cs___3 = 67,\n\tmsm_mux_qspi_data___3 = 68,\n\tmsm_mux_resout___2 = 69,\n\tmsm_mux_rx0___2 = 70,\n\tmsm_mux_rx1___2 = 71,\n\tmsm_mux_rx2 = 72,\n\tmsm_mux_sdc_clk___2 = 73,\n\tmsm_mux_sdc_cmd___2 = 74,\n\tmsm_mux_sdc_data___2 = 75,\n\tmsm_mux_spi0_clk = 76,\n\tmsm_mux_spi0_cs = 77,\n\tmsm_mux_spi0_miso = 78,\n\tmsm_mux_spi0_mosi = 79,\n\tmsm_mux_spi1 = 80,\n\tmsm_mux_spi10 = 81,\n\tmsm_mux_spi11 = 82,\n\tmsm_mux_tsens_max___2 = 83,\n\tmsm_mux_uart0 = 84,\n\tmsm_mux_uart1 = 85,\n\tmsm_mux_wci_txd___3 = 86,\n\tmsm_mux_wci_rxd___3 = 87,\n\tmsm_mux_wsi_clk___2 = 88,\n\tmsm_mux_wsi_data___2 = 89,\n\tmsm_mux_____3 = 90,\n};\n\nenum ipq6018_functions {\n\tmsm_mux_atest_char___4 = 0,\n\tmsm_mux_atest_char0___3 = 1,\n\tmsm_mux_atest_char1___3 = 2,\n\tmsm_mux_atest_char2___3 = 3,\n\tmsm_mux_atest_char3___3 = 4,\n\tmsm_mux_audio0 = 5,\n\tmsm_mux_audio1 = 6,\n\tmsm_mux_audio2 = 7,\n\tmsm_mux_audio3 = 8,\n\tmsm_mux_audio_rxbclk___2 = 9,\n\tmsm_mux_audio_rxfsync___2 = 10,\n\tmsm_mux_audio_rxmclk___2 = 11,\n\tmsm_mux_audio_rxmclkin = 12,\n\tmsm_mux_audio_txbclk___2 = 13,\n\tmsm_mux_audio_txfsync___2 = 14,\n\tmsm_mux_audio_txmclk___2 = 15,\n\tmsm_mux_audio_txmclkin = 16,\n\tmsm_mux_blsp0_i2c___3 = 17,\n\tmsm_mux_blsp0_spi___3 = 18,\n\tmsm_mux_blsp0_uart = 19,\n\tmsm_mux_blsp1_i2c = 20,\n\tmsm_mux_blsp1_spi = 21,\n\tmsm_mux_blsp1_uart = 22,\n\tmsm_mux_blsp2_i2c = 23,\n\tmsm_mux_blsp2_spi___3 = 24,\n\tmsm_mux_blsp2_uart = 25,\n\tmsm_mux_blsp3_i2c = 26,\n\tmsm_mux_blsp3_spi = 27,\n\tmsm_mux_blsp3_uart = 28,\n\tmsm_mux_blsp4_i2c = 29,\n\tmsm_mux_blsp4_spi = 30,\n\tmsm_mux_blsp4_uart = 31,\n\tmsm_mux_blsp5_i2c = 32,\n\tmsm_mux_blsp5_uart = 33,\n\tmsm_mux_burn0___2 = 34,\n\tmsm_mux_burn1___2 = 35,\n\tmsm_mux_cri_trng___2 = 36,\n\tmsm_mux_cri_trng0___4 = 37,\n\tmsm_mux_cri_trng1___4 = 38,\n\tmsm_mux_cxc0 = 39,\n\tmsm_mux_cxc1 = 40,\n\tmsm_mux_dbg_out___4 = 41,\n\tmsm_mux_gcc_plltest___4 = 42,\n\tmsm_mux_gcc_tlmm___4 = 43,\n\tmsm_mux_gpio___4 = 44,\n\tmsm_mux_lpass_aud = 45,\n\tmsm_mux_lpass_aud0 = 46,\n\tmsm_mux_lpass_aud1 = 47,\n\tmsm_mux_lpass_aud2 = 48,\n\tmsm_mux_lpass_pcm = 49,\n\tmsm_mux_lpass_pdm = 50,\n\tmsm_mux_mac00 = 51,\n\tmsm_mux_mac01 = 52,\n\tmsm_mux_mac10 = 53,\n\tmsm_mux_mac11 = 54,\n\tmsm_mux_mac12 = 55,\n\tmsm_mux_mac13 = 56,\n\tmsm_mux_mac20 = 57,\n\tmsm_mux_mac21 = 58,\n\tmsm_mux_mdc___2 = 59,\n\tmsm_mux_mdio___2 = 60,\n\tmsm_mux_pcie0_clk___4 = 61,\n\tmsm_mux_pcie0_rst = 62,\n\tmsm_mux_pcie0_wake___4 = 63,\n\tmsm_mux_prng_rosc___2 = 64,\n\tmsm_mux_pta1_0 = 65,\n\tmsm_mux_pta1_1 = 66,\n\tmsm_mux_pta1_2 = 67,\n\tmsm_mux_pta2_0 = 68,\n\tmsm_mux_pta2_1 = 69,\n\tmsm_mux_pta2_2 = 70,\n\tmsm_mux_pwm00 = 71,\n\tmsm_mux_pwm01 = 72,\n\tmsm_mux_pwm02 = 73,\n\tmsm_mux_pwm03 = 74,\n\tmsm_mux_pwm04 = 75,\n\tmsm_mux_pwm10 = 76,\n\tmsm_mux_pwm11 = 77,\n\tmsm_mux_pwm12 = 78,\n\tmsm_mux_pwm13 = 79,\n\tmsm_mux_pwm14 = 80,\n\tmsm_mux_pwm20 = 81,\n\tmsm_mux_pwm21 = 82,\n\tmsm_mux_pwm22 = 83,\n\tmsm_mux_pwm23 = 84,\n\tmsm_mux_pwm24 = 85,\n\tmsm_mux_pwm30 = 86,\n\tmsm_mux_pwm31 = 87,\n\tmsm_mux_pwm32 = 88,\n\tmsm_mux_pwm33 = 89,\n\tmsm_mux_qdss_cti_trig_in_a0___4 = 90,\n\tmsm_mux_qdss_cti_trig_in_a1___4 = 91,\n\tmsm_mux_qdss_cti_trig_out_a0___4 = 92,\n\tmsm_mux_qdss_cti_trig_out_a1___4 = 93,\n\tmsm_mux_qdss_cti_trig_in_b0___4 = 94,\n\tmsm_mux_qdss_cti_trig_in_b1___4 = 95,\n\tmsm_mux_qdss_cti_trig_out_b0___4 = 96,\n\tmsm_mux_qdss_cti_trig_out_b1___4 = 97,\n\tmsm_mux_qdss_traceclk_a___4 = 98,\n\tmsm_mux_qdss_tracectl_a___4 = 99,\n\tmsm_mux_qdss_tracedata_a___4 = 100,\n\tmsm_mux_qdss_traceclk_b___3 = 101,\n\tmsm_mux_qdss_tracectl_b___3 = 102,\n\tmsm_mux_qdss_tracedata_b___3 = 103,\n\tmsm_mux_qpic_pad = 104,\n\tmsm_mux_rx0___3 = 105,\n\tmsm_mux_rx1___3 = 106,\n\tmsm_mux_rx_swrm = 107,\n\tmsm_mux_rx_swrm0 = 108,\n\tmsm_mux_rx_swrm1 = 109,\n\tmsm_mux_sd_card = 110,\n\tmsm_mux_sd_write = 111,\n\tmsm_mux_tsens_max___3 = 112,\n\tmsm_mux_tx_swrm = 113,\n\tmsm_mux_tx_swrm0 = 114,\n\tmsm_mux_tx_swrm1 = 115,\n\tmsm_mux_tx_swrm2 = 116,\n\tmsm_mux_wci20 = 117,\n\tmsm_mux_wci21 = 118,\n\tmsm_mux_wci22 = 119,\n\tmsm_mux_wci23 = 120,\n\tmsm_mux_wsa_swrm___2 = 121,\n\tmsm_mux_____4 = 122,\n};\n\nenum ipq806x_versions {\n\tIPQ8062_VERSION = 0,\n\tIPQ8064_VERSION = 1,\n\tIPQ8065_VERSION = 2,\n};\n\nenum ipq8074_functions {\n\tmsm_mux_atest_char___5 = 0,\n\tmsm_mux_atest_char0___4 = 1,\n\tmsm_mux_atest_char1___4 = 2,\n\tmsm_mux_atest_char2___4 = 3,\n\tmsm_mux_atest_char3___4 = 4,\n\tmsm_mux_audio_rxbclk___3 = 5,\n\tmsm_mux_audio_rxd___2 = 6,\n\tmsm_mux_audio_rxfsync___3 = 7,\n\tmsm_mux_audio_rxmclk___3 = 8,\n\tmsm_mux_audio_txbclk___3 = 9,\n\tmsm_mux_audio_txd___2 = 10,\n\tmsm_mux_audio_txfsync___3 = 11,\n\tmsm_mux_audio_txmclk___3 = 12,\n\tmsm_mux_blsp0_i2c___4 = 13,\n\tmsm_mux_blsp0_spi___4 = 14,\n\tmsm_mux_blsp0_uart___2 = 15,\n\tmsm_mux_blsp1_i2c___2 = 16,\n\tmsm_mux_blsp1_spi___2 = 17,\n\tmsm_mux_blsp1_uart___2 = 18,\n\tmsm_mux_blsp2_i2c___2 = 19,\n\tmsm_mux_blsp2_spi___4 = 20,\n\tmsm_mux_blsp2_uart___2 = 21,\n\tmsm_mux_blsp3_i2c___2 = 22,\n\tmsm_mux_blsp3_spi___2 = 23,\n\tmsm_mux_blsp3_spi0 = 24,\n\tmsm_mux_blsp3_spi1 = 25,\n\tmsm_mux_blsp3_spi2 = 26,\n\tmsm_mux_blsp3_spi3 = 27,\n\tmsm_mux_blsp3_uart___2 = 28,\n\tmsm_mux_blsp4_i2c0 = 29,\n\tmsm_mux_blsp4_i2c1 = 30,\n\tmsm_mux_blsp4_spi0 = 31,\n\tmsm_mux_blsp4_spi1 = 32,\n\tmsm_mux_blsp4_uart0 = 33,\n\tmsm_mux_blsp4_uart1 = 34,\n\tmsm_mux_blsp5_i2c___2 = 35,\n\tmsm_mux_blsp5_spi = 36,\n\tmsm_mux_blsp5_uart___2 = 37,\n\tmsm_mux_burn0___3 = 38,\n\tmsm_mux_burn1___3 = 39,\n\tmsm_mux_cri_trng___3 = 40,\n\tmsm_mux_cri_trng0___5 = 41,\n\tmsm_mux_cri_trng1___5 = 42,\n\tmsm_mux_cxc0___2 = 43,\n\tmsm_mux_cxc1___2 = 44,\n\tmsm_mux_dbg_out___5 = 45,\n\tmsm_mux_gcc_plltest___5 = 46,\n\tmsm_mux_gcc_tlmm___5 = 47,\n\tmsm_mux_gpio___5 = 48,\n\tmsm_mux_ldo_en = 49,\n\tmsm_mux_ldo_update = 50,\n\tmsm_mux_led0___2 = 51,\n\tmsm_mux_led1 = 52,\n\tmsm_mux_led2___2 = 53,\n\tmsm_mux_mac0_sa0 = 54,\n\tmsm_mux_mac0_sa1 = 55,\n\tmsm_mux_mac1_sa0 = 56,\n\tmsm_mux_mac1_sa1 = 57,\n\tmsm_mux_mac1_sa2 = 58,\n\tmsm_mux_mac1_sa3 = 59,\n\tmsm_mux_mac2_sa0 = 60,\n\tmsm_mux_mac2_sa1 = 61,\n\tmsm_mux_mdc___3 = 62,\n\tmsm_mux_mdio___3 = 63,\n\tmsm_mux_pcie0_clk___5 = 64,\n\tmsm_mux_pcie0_rst___2 = 65,\n\tmsm_mux_pcie0_wake___5 = 66,\n\tmsm_mux_pcie1_clk___4 = 67,\n\tmsm_mux_pcie1_rst = 68,\n\tmsm_mux_pcie1_wake___4 = 69,\n\tmsm_mux_pcm_drx = 70,\n\tmsm_mux_pcm_dtx = 71,\n\tmsm_mux_pcm_fsync = 72,\n\tmsm_mux_pcm_pclk = 73,\n\tmsm_mux_pcm_zsi0 = 74,\n\tmsm_mux_pcm_zsi1 = 75,\n\tmsm_mux_prng_rosc___3 = 76,\n\tmsm_mux_pta1_0___2 = 77,\n\tmsm_mux_pta1_1___2 = 78,\n\tmsm_mux_pta1_2___2 = 79,\n\tmsm_mux_pta2_0___2 = 80,\n\tmsm_mux_pta2_1___2 = 81,\n\tmsm_mux_pta2_2___2 = 82,\n\tmsm_mux_pwm0___4 = 83,\n\tmsm_mux_pwm1___4 = 84,\n\tmsm_mux_pwm2___4 = 85,\n\tmsm_mux_pwm3___3 = 86,\n\tmsm_mux_qdss_cti_trig_in_a0___5 = 87,\n\tmsm_mux_qdss_cti_trig_in_a1___5 = 88,\n\tmsm_mux_qdss_cti_trig_in_b0___5 = 89,\n\tmsm_mux_qdss_cti_trig_in_b1___5 = 90,\n\tmsm_mux_qdss_cti_trig_out_a0___5 = 91,\n\tmsm_mux_qdss_cti_trig_out_a1___5 = 92,\n\tmsm_mux_qdss_cti_trig_out_b0___5 = 93,\n\tmsm_mux_qdss_cti_trig_out_b1___5 = 94,\n\tmsm_mux_qdss_traceclk_a___5 = 95,\n\tmsm_mux_qdss_traceclk_b___4 = 96,\n\tmsm_mux_qdss_tracectl_a___5 = 97,\n\tmsm_mux_qdss_tracectl_b___4 = 98,\n\tmsm_mux_qdss_tracedata_a___5 = 99,\n\tmsm_mux_qdss_tracedata_b___4 = 100,\n\tmsm_mux_qpic = 101,\n\tmsm_mux_rx0___4 = 102,\n\tmsm_mux_rx1___4 = 103,\n\tmsm_mux_rx2___2 = 104,\n\tmsm_mux_sd_card___2 = 105,\n\tmsm_mux_sd_write___2 = 106,\n\tmsm_mux_tsens_max___4 = 107,\n\tmsm_mux_wci2a = 108,\n\tmsm_mux_wci2b = 109,\n\tmsm_mux_wci2c = 110,\n\tmsm_mux_wci2d = 111,\n\tmsm_mux_NA = 112,\n};\n\nenum ipq8074_versions {\n\tIPQ8074_HAWKEYE_VERSION = 0,\n\tIPQ8074_ACORN_VERSION = 1,\n};\n\nenum ipq9574_functions {\n\tmsm_mux_atest_char___6 = 0,\n\tmsm_mux_atest_char0___5 = 1,\n\tmsm_mux_atest_char1___5 = 2,\n\tmsm_mux_atest_char2___5 = 3,\n\tmsm_mux_atest_char3___5 = 4,\n\tmsm_mux_audio_pdm0___2 = 5,\n\tmsm_mux_audio_pdm1___2 = 6,\n\tmsm_mux_audio_pri___3 = 7,\n\tmsm_mux_audio_sec___3 = 8,\n\tmsm_mux_blsp0_spi___5 = 9,\n\tmsm_mux_blsp0_uart___3 = 10,\n\tmsm_mux_blsp1_i2c___3 = 11,\n\tmsm_mux_blsp1_spi___3 = 12,\n\tmsm_mux_blsp1_uart___3 = 13,\n\tmsm_mux_blsp2_i2c___3 = 14,\n\tmsm_mux_blsp2_spi___5 = 15,\n\tmsm_mux_blsp2_uart___3 = 16,\n\tmsm_mux_blsp3_i2c___3 = 17,\n\tmsm_mux_blsp3_spi___3 = 18,\n\tmsm_mux_blsp3_uart___3 = 19,\n\tmsm_mux_blsp4_i2c___2 = 20,\n\tmsm_mux_blsp4_spi___2 = 21,\n\tmsm_mux_blsp4_uart___2 = 22,\n\tmsm_mux_blsp5_i2c___3 = 23,\n\tmsm_mux_blsp5_uart___3 = 24,\n\tmsm_mux_cri_trng0___6 = 25,\n\tmsm_mux_cri_trng1___6 = 26,\n\tmsm_mux_cri_trng2___3 = 27,\n\tmsm_mux_cri_trng3___3 = 28,\n\tmsm_mux_cxc0___3 = 29,\n\tmsm_mux_cxc1___3 = 30,\n\tmsm_mux_dbg_out___6 = 31,\n\tmsm_mux_dwc_ddrphy = 32,\n\tmsm_mux_gcc_plltest___6 = 33,\n\tmsm_mux_gcc_tlmm___6 = 34,\n\tmsm_mux_gpio___6 = 35,\n\tmsm_mux_mac = 36,\n\tmsm_mux_mdc___4 = 37,\n\tmsm_mux_mdio___4 = 38,\n\tmsm_mux_pcie0_clk___6 = 39,\n\tmsm_mux_pcie0_wake___6 = 40,\n\tmsm_mux_pcie1_clk___5 = 41,\n\tmsm_mux_pcie1_wake___5 = 42,\n\tmsm_mux_pcie2_clk___3 = 43,\n\tmsm_mux_pcie2_wake___3 = 44,\n\tmsm_mux_pcie3_clk___2 = 45,\n\tmsm_mux_pcie3_wake___2 = 46,\n\tmsm_mux_prng_rosc0___3 = 47,\n\tmsm_mux_prng_rosc1___3 = 48,\n\tmsm_mux_prng_rosc2___3 = 49,\n\tmsm_mux_prng_rosc3___3 = 50,\n\tmsm_mux_pta___2 = 51,\n\tmsm_mux_pwm = 52,\n\tmsm_mux_qdss_cti_trig_in_a0___6 = 53,\n\tmsm_mux_qdss_cti_trig_in_a1___6 = 54,\n\tmsm_mux_qdss_cti_trig_in_b0___6 = 55,\n\tmsm_mux_qdss_cti_trig_in_b1___6 = 56,\n\tmsm_mux_qdss_cti_trig_out_a0___6 = 57,\n\tmsm_mux_qdss_cti_trig_out_a1___6 = 58,\n\tmsm_mux_qdss_cti_trig_out_b0___6 = 59,\n\tmsm_mux_qdss_cti_trig_out_b1___6 = 60,\n\tmsm_mux_qdss_traceclk_a___6 = 61,\n\tmsm_mux_qdss_traceclk_b___5 = 62,\n\tmsm_mux_qdss_tracectl_a___6 = 63,\n\tmsm_mux_qdss_tracectl_b___5 = 64,\n\tmsm_mux_qdss_tracedata_a___6 = 65,\n\tmsm_mux_qdss_tracedata_b___5 = 66,\n\tmsm_mux_qspi_data___4 = 67,\n\tmsm_mux_qspi_clk___4 = 68,\n\tmsm_mux_qspi_cs___4 = 69,\n\tmsm_mux_rx0___5 = 70,\n\tmsm_mux_rx1___5 = 71,\n\tmsm_mux_sdc_data___3 = 72,\n\tmsm_mux_sdc_clk___3 = 73,\n\tmsm_mux_sdc_cmd___3 = 74,\n\tmsm_mux_sdc_rclk = 75,\n\tmsm_mux_tsens_max___5 = 76,\n\tmsm_mux_wci20___2 = 77,\n\tmsm_mux_wci21___2 = 78,\n\tmsm_mux_wsa_swrm___3 = 79,\n\tmsm_mux_____5 = 80,\n};\n\nenum iproc_arm_pll_fid {\n\tARM_PLL_FID_CRYSTAL_CLK = 0,\n\tARM_PLL_FID_SYS_CLK = 2,\n\tARM_PLL_FID_CH0_SLOW_CLK = 6,\n\tARM_PLL_FID_CH1_FAST_CLK = 7,\n};\n\nenum iproc_msi_reg {\n\tIPROC_MSI_EQ_PAGE = 0,\n\tIPROC_MSI_EQ_PAGE_UPPER = 1,\n\tIPROC_MSI_PAGE = 2,\n\tIPROC_MSI_PAGE_UPPER = 3,\n\tIPROC_MSI_CTRL = 4,\n\tIPROC_MSI_EQ_HEAD = 5,\n\tIPROC_MSI_EQ_TAIL = 6,\n\tIPROC_MSI_INTS_EN = 7,\n\tIPROC_MSI_REG_SIZE = 8,\n};\n\nenum iproc_pcie_ib_map_type {\n\tIPROC_PCIE_IB_MAP_MEM = 0,\n\tIPROC_PCIE_IB_MAP_IO = 1,\n\tIPROC_PCIE_IB_MAP_INVALID = 2,\n};\n\nenum iproc_pcie_reg {\n\tIPROC_PCIE_CLK_CTRL = 0,\n\tIPROC_PCIE_MSI_GIC_MODE = 1,\n\tIPROC_PCIE_MSI_BASE_ADDR = 2,\n\tIPROC_PCIE_MSI_WINDOW_SIZE = 3,\n\tIPROC_PCIE_MSI_ADDR_LO = 4,\n\tIPROC_PCIE_MSI_ADDR_HI = 5,\n\tIPROC_PCIE_MSI_EN_CFG = 6,\n\tIPROC_PCIE_CFG_IND_ADDR = 7,\n\tIPROC_PCIE_CFG_IND_DATA = 8,\n\tIPROC_PCIE_CFG_ADDR = 9,\n\tIPROC_PCIE_CFG_DATA = 10,\n\tIPROC_PCIE_INTX_EN = 11,\n\tIPROC_PCIE_OARR0 = 12,\n\tIPROC_PCIE_OMAP0 = 13,\n\tIPROC_PCIE_OARR1 = 14,\n\tIPROC_PCIE_OMAP1 = 15,\n\tIPROC_PCIE_OARR2 = 16,\n\tIPROC_PCIE_OMAP2 = 17,\n\tIPROC_PCIE_OARR3 = 18,\n\tIPROC_PCIE_OMAP3 = 19,\n\tIPROC_PCIE_IARR0 = 20,\n\tIPROC_PCIE_IMAP0 = 21,\n\tIPROC_PCIE_IARR1 = 22,\n\tIPROC_PCIE_IMAP1 = 23,\n\tIPROC_PCIE_IARR2 = 24,\n\tIPROC_PCIE_IMAP2 = 25,\n\tIPROC_PCIE_IARR3 = 26,\n\tIPROC_PCIE_IMAP3 = 27,\n\tIPROC_PCIE_IARR4 = 28,\n\tIPROC_PCIE_IMAP4 = 29,\n\tIPROC_PCIE_CFG_RD_STATUS = 30,\n\tIPROC_PCIE_LINK_STATUS = 31,\n\tIPROC_PCIE_APB_ERR_EN = 32,\n\tIPROC_PCIE_MAX_NUM_REG = 33,\n};\n\nenum iproc_pcie_type {\n\tIPROC_PCIE_PAXB_BCMA = 0,\n\tIPROC_PCIE_PAXB = 1,\n\tIPROC_PCIE_PAXB_V2 = 2,\n\tIPROC_PCIE_PAXC = 3,\n\tIPROC_PCIE_PAXC_V2 = 4,\n};\n\nenum iproc_pinconf_ctrl_type {\n\tIOCTRL_TYPE_AON = 1,\n\tIOCTRL_TYPE_CDRU = 2,\n\tIOCTRL_TYPE_INVALID = 3,\n};\n\nenum iproc_pinconf_param {\n\tIPROC_PINCONF_DRIVE_STRENGTH = 0,\n\tIPROC_PINCONF_BIAS_DISABLE = 1,\n\tIPROC_PINCONF_BIAS_PULL_UP = 2,\n\tIPROC_PINCONF_BIAS_PULL_DOWN = 3,\n\tIPROC_PINCON_MAX = 4,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irq_source {\n\tSINGLE_L2 = 0,\n\tMUXED_L1 = 1,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum isp1760_ctrl_state {\n\tISP1760_CTRL_SETUP = 0,\n\tISP1760_CTRL_DATA_IN = 1,\n\tISP1760_CTRL_DATA_OUT = 2,\n\tISP1760_CTRL_STATUS = 3,\n};\n\nenum isp1760_queue_head_types {\n\tQH_CONTROL = 0,\n\tQH_BULK = 1,\n\tQH_INTERRUPT = 2,\n\tQH_END = 3,\n};\n\nenum isp176x_device_controller_fields {\n\tDC_DEVEN = 0,\n\tDC_DEVADDR = 1,\n\tDC_VBUSSTAT = 2,\n\tDC_SFRESET = 3,\n\tDC_GLINTENA = 4,\n\tDC_CDBGMOD_ACK = 5,\n\tDC_DDBGMODIN_ACK = 6,\n\tDC_DDBGMODOUT_ACK = 7,\n\tDC_INTPOL = 8,\n\tDC_IEPRXTX_7 = 9,\n\tDC_IEPRXTX_6 = 10,\n\tDC_IEPRXTX_5 = 11,\n\tDC_IEPRXTX_4 = 12,\n\tDC_IEPRXTX_3 = 13,\n\tDC_IEPRXTX_2 = 14,\n\tDC_IEPRXTX_1 = 15,\n\tDC_IEPRXTX_0 = 16,\n\tDC_IEP0SETUP = 17,\n\tDC_IEVBUS = 18,\n\tDC_IEHS_STA = 19,\n\tDC_IERESM = 20,\n\tDC_IESUSP = 21,\n\tDC_IEBRST = 22,\n\tDC_EP0SETUP = 23,\n\tDC_ENDPIDX = 24,\n\tDC_EPDIR = 25,\n\tDC_CLBUF = 26,\n\tDC_VENDP = 27,\n\tDC_DSEN = 28,\n\tDC_STATUS = 29,\n\tDC_STALL = 30,\n\tDC_BUFLEN = 31,\n\tDC_FFOSZ = 32,\n\tDC_EPENABLE = 33,\n\tDC_ENDPTYP = 34,\n\tDC_FRAMENUM = 35,\n\tDC_UFRAMENUM = 36,\n\tDC_CHIP_ID_HIGH = 37,\n\tDC_CHIP_ID_LOW = 38,\n\tDC_SCRATCH = 39,\n\tDC_FIELD_MAX = 40,\n};\n\nenum isp176x_host_controller_fields {\n\tPORT_OWNER = 0,\n\tPORT_POWER = 1,\n\tPORT_LSTATUS = 2,\n\tPORT_RESET = 3,\n\tPORT_SUSPEND = 4,\n\tPORT_RESUME = 5,\n\tPORT_PE = 6,\n\tPORT_CSC = 7,\n\tPORT_CONNECT = 8,\n\tHCS_PPC = 9,\n\tHCS_N_PORTS = 10,\n\tHCC_ISOC_CACHE = 11,\n\tHCC_ISOC_THRES = 12,\n\tCMD_LRESET = 13,\n\tCMD_RESET = 14,\n\tCMD_RUN = 15,\n\tSTS_PCD = 16,\n\tHC_FRINDEX = 17,\n\tFLAG_CF = 18,\n\tHC_ISO_PTD_DONEMAP = 19,\n\tHC_ISO_PTD_SKIPMAP = 20,\n\tHC_ISO_PTD_LASTPTD = 21,\n\tHC_INT_PTD_DONEMAP = 22,\n\tHC_INT_PTD_SKIPMAP = 23,\n\tHC_INT_PTD_LASTPTD = 24,\n\tHC_ATL_PTD_DONEMAP = 25,\n\tHC_ATL_PTD_SKIPMAP = 26,\n\tHC_ATL_PTD_LASTPTD = 27,\n\tALL_ATX_RESET = 28,\n\tHW_ANA_DIGI_OC = 29,\n\tHW_DEV_DMA = 30,\n\tHW_COMN_IRQ = 31,\n\tHW_COMN_DMA = 32,\n\tHW_DATA_BUS_WIDTH = 33,\n\tHW_DACK_POL_HIGH = 34,\n\tHW_DREQ_POL_HIGH = 35,\n\tHW_INTR_HIGH_ACT = 36,\n\tHW_INTF_LOCK = 37,\n\tHW_INTR_EDGE_TRIG = 38,\n\tHW_GLOBAL_INTR_EN = 39,\n\tHC_CHIP_ID_HIGH = 40,\n\tHC_CHIP_ID_LOW = 41,\n\tHC_CHIP_REV = 42,\n\tHC_SCRATCH = 43,\n\tSW_RESET_RESET_ATX = 44,\n\tSW_RESET_RESET_HC = 45,\n\tSW_RESET_RESET_ALL = 46,\n\tISO_BUF_FILL = 47,\n\tINT_BUF_FILL = 48,\n\tATL_BUF_FILL = 49,\n\tMEM_BANK_SEL = 50,\n\tMEM_START_ADDR = 51,\n\tHC_DATA = 52,\n\tHC_INTERRUPT = 53,\n\tHC_INT_IRQ_ENABLE = 54,\n\tHC_ATL_IRQ_ENABLE = 55,\n\tHC_ISO_IRQ_MASK_OR = 56,\n\tHC_INT_IRQ_MASK_OR = 57,\n\tHC_ATL_IRQ_MASK_OR = 58,\n\tHC_ISO_IRQ_MASK_AND = 59,\n\tHC_INT_IRQ_MASK_AND = 60,\n\tHC_ATL_IRQ_MASK_AND = 61,\n\tHW_OTG_DISABLE = 62,\n\tHW_SW_SEL_HC_DC = 63,\n\tHW_VBUS_DRV = 64,\n\tHW_SEL_CP_EXT = 65,\n\tHW_DM_PULLDOWN = 66,\n\tHW_DP_PULLDOWN = 67,\n\tHW_DP_PULLUP = 68,\n\tHW_HC_2_DIS = 69,\n\tHW_OTG_DISABLE_CLEAR = 70,\n\tHW_SW_SEL_HC_DC_CLEAR = 71,\n\tHW_VBUS_DRV_CLEAR = 72,\n\tHW_SEL_CP_EXT_CLEAR = 73,\n\tHW_DM_PULLDOWN_CLEAR = 74,\n\tHW_DP_PULLDOWN_CLEAR = 75,\n\tHW_DP_PULLUP_CLEAR = 76,\n\tHW_HC_2_DIS_CLEAR = 77,\n\tHC_FIELD_MAX = 78,\n};\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum its_vcpu_info_cmd_type {\n\tMAP_VLPI = 0,\n\tGET_VLPI = 1,\n\tPROP_UPDATE_VLPI = 2,\n\tPROP_UPDATE_AND_INV_VLPI = 3,\n\tSCHEDULE_VPE = 4,\n\tDESCHEDULE_VPE = 5,\n\tCOMMIT_VPE = 6,\n\tINVALL_VPE = 7,\n\tPROP_UPDATE_VSGI = 8,\n};\n\nenum jbd2_shrink_type {\n\tJBD2_SHRINK_DESTROY = 0,\n\tJBD2_SHRINK_BUSY_STOP = 1,\n\tJBD2_SHRINK_BUSY_SKIP = 2,\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 17,\n\tBH_JWrite = 18,\n\tBH_Freed = 19,\n\tBH_Revoked = 20,\n\tBH_RevokeValid = 21,\n\tBH_JBDDirty = 22,\n\tBH_JournalHead = 23,\n\tBH_Shadow = 24,\n\tBH_Verified = 25,\n\tBH_JBDPrivateStart = 26,\n};\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nenum k3_dma_type {\n\tDMA_TYPE_UDMA = 0,\n\tDMA_TYPE_BCDMA = 1,\n\tDMA_TYPE_PKTDMA = 2,\n};\n\nenum k3_ring_mode {\n\tK3_RINGACC_RING_MODE_RING = 0,\n\tK3_RINGACC_RING_MODE_MESSAGE = 1,\n\tK3_RINGACC_RING_MODE_CREDENTIALS = 2,\n\tK3_RINGACC_RING_MODE_INVALID = 3,\n};\n\nenum k3_ring_size {\n\tK3_RINGACC_RING_ELSIZE_4 = 0,\n\tK3_RINGACC_RING_ELSIZE_8 = 1,\n\tK3_RINGACC_RING_ELSIZE_16 = 2,\n\tK3_RINGACC_RING_ELSIZE_32 = 3,\n\tK3_RINGACC_RING_ELSIZE_64 = 4,\n\tK3_RINGACC_RING_ELSIZE_128 = 5,\n\tK3_RINGACC_RING_ELSIZE_256 = 6,\n\tK3_RINGACC_RING_ELSIZE_INVALID = 7,\n};\n\nenum k3_ringacc_access_mode {\n\tK3_RINGACC_ACCESS_MODE_PUSH_HEAD = 0,\n\tK3_RINGACC_ACCESS_MODE_POP_HEAD = 1,\n\tK3_RINGACC_ACCESS_MODE_PUSH_TAIL = 2,\n\tK3_RINGACC_ACCESS_MODE_POP_TAIL = 3,\n\tK3_RINGACC_ACCESS_MODE_PEEK_HEAD = 4,\n\tK3_RINGACC_ACCESS_MODE_PEEK_TAIL = 5,\n};\n\nenum k3_ringacc_proxy_access_mode {\n\tPROXY_ACCESS_MODE_HEAD = 0,\n\tPROXY_ACCESS_MODE_TAIL = 1,\n\tPROXY_ACCESS_MODE_PEEK_HEAD = 2,\n\tPROXY_ACCESS_MODE_PEEK_TAIL = 3,\n};\n\nenum kaanapali_functions {\n\tmsm_mux_gpio___7 = 0,\n\tmsm_mux_aoss_cti = 1,\n\tmsm_mux_atest_char___7 = 2,\n\tmsm_mux_atest_usb = 3,\n\tmsm_mux_audio_ext_mclk0 = 4,\n\tmsm_mux_audio_ext_mclk1 = 5,\n\tmsm_mux_audio_ref_clk = 6,\n\tmsm_mux_cam_asc_mclk2 = 7,\n\tmsm_mux_cam_asc_mclk4 = 8,\n\tmsm_mux_cam_mclk = 9,\n\tmsm_mux_cci_async_in = 10,\n\tmsm_mux_cci_i2c_scl = 11,\n\tmsm_mux_cci_i2c_sda = 12,\n\tmsm_mux_cci_timer = 13,\n\tmsm_mux_cmu_rng = 14,\n\tmsm_mux_coex_uart1_rx = 15,\n\tmsm_mux_coex_uart1_tx = 16,\n\tmsm_mux_coex_uart2_rx = 17,\n\tmsm_mux_coex_uart2_tx = 18,\n\tmsm_mux_dbg_out_clk = 19,\n\tmsm_mux_ddr_bist_complete = 20,\n\tmsm_mux_ddr_bist_fail = 21,\n\tmsm_mux_ddr_bist_start = 22,\n\tmsm_mux_ddr_bist_stop = 23,\n\tmsm_mux_ddr_pxi0 = 24,\n\tmsm_mux_ddr_pxi1 = 25,\n\tmsm_mux_ddr_pxi2 = 26,\n\tmsm_mux_ddr_pxi3 = 27,\n\tmsm_mux_dp_hot = 28,\n\tmsm_mux_egpio = 29,\n\tmsm_mux_gcc_gp1 = 30,\n\tmsm_mux_gcc_gp2 = 31,\n\tmsm_mux_gcc_gp3 = 32,\n\tmsm_mux_gnss_adc0 = 33,\n\tmsm_mux_gnss_adc1 = 34,\n\tmsm_mux_i2chub0_se0 = 35,\n\tmsm_mux_i2chub0_se1 = 36,\n\tmsm_mux_i2chub0_se2 = 37,\n\tmsm_mux_i2chub0_se3 = 38,\n\tmsm_mux_i2chub0_se4 = 39,\n\tmsm_mux_i2s0_data0 = 40,\n\tmsm_mux_i2s0_data1 = 41,\n\tmsm_mux_i2s0_sck = 42,\n\tmsm_mux_i2s0_ws = 43,\n\tmsm_mux_i2s1_data0 = 44,\n\tmsm_mux_i2s1_data1 = 45,\n\tmsm_mux_i2s1_sck = 46,\n\tmsm_mux_i2s1_ws = 47,\n\tmsm_mux_ibi_i3c = 48,\n\tmsm_mux_jitter_bist = 49,\n\tmsm_mux_mdp_esync0_out = 50,\n\tmsm_mux_mdp_esync1_out = 51,\n\tmsm_mux_mdp_vsync = 52,\n\tmsm_mux_mdp_vsync0_out = 53,\n\tmsm_mux_mdp_vsync1_out = 54,\n\tmsm_mux_mdp_vsync2_out = 55,\n\tmsm_mux_mdp_vsync3_out = 56,\n\tmsm_mux_mdp_vsync5_out = 57,\n\tmsm_mux_mdp_vsync_e = 58,\n\tmsm_mux_nav_gpio0 = 59,\n\tmsm_mux_nav_gpio1 = 60,\n\tmsm_mux_nav_gpio2 = 61,\n\tmsm_mux_nav_gpio3 = 62,\n\tmsm_mux_pcie0_clk_req_n = 63,\n\tmsm_mux_phase_flag = 64,\n\tmsm_mux_pll_bist_sync = 65,\n\tmsm_mux_pll_clk_aux = 66,\n\tmsm_mux_prng_rosc0___4 = 67,\n\tmsm_mux_prng_rosc1___4 = 68,\n\tmsm_mux_prng_rosc2___4 = 69,\n\tmsm_mux_prng_rosc3___4 = 70,\n\tmsm_mux_qdss_cti = 71,\n\tmsm_mux_qdss_gpio_traceclk = 72,\n\tmsm_mux_qdss_gpio_tracectl = 73,\n\tmsm_mux_qdss_gpio_tracedata = 74,\n\tmsm_mux_qlink_big_enable = 75,\n\tmsm_mux_qlink_big_request = 76,\n\tmsm_mux_qlink_little_enable = 77,\n\tmsm_mux_qlink_little_request = 78,\n\tmsm_mux_qlink_wmss = 79,\n\tmsm_mux_qspi0 = 80,\n\tmsm_mux_qspi1 = 81,\n\tmsm_mux_qspi2 = 82,\n\tmsm_mux_qspi3 = 83,\n\tmsm_mux_qspi_clk___5 = 84,\n\tmsm_mux_qspi_cs___5 = 85,\n\tmsm_mux_qup1_se0 = 86,\n\tmsm_mux_qup1_se1 = 87,\n\tmsm_mux_qup1_se2 = 88,\n\tmsm_mux_qup1_se3 = 89,\n\tmsm_mux_qup1_se4 = 90,\n\tmsm_mux_qup1_se5 = 91,\n\tmsm_mux_qup1_se6 = 92,\n\tmsm_mux_qup1_se7 = 93,\n\tmsm_mux_qup2_se0 = 94,\n\tmsm_mux_qup2_se1 = 95,\n\tmsm_mux_qup2_se2 = 96,\n\tmsm_mux_qup2_se3 = 97,\n\tmsm_mux_qup2_se4 = 98,\n\tmsm_mux_qup3_se0 = 99,\n\tmsm_mux_qup3_se1 = 100,\n\tmsm_mux_qup3_se2 = 101,\n\tmsm_mux_qup3_se3 = 102,\n\tmsm_mux_qup3_se4 = 103,\n\tmsm_mux_qup3_se5 = 104,\n\tmsm_mux_qup4_se0 = 105,\n\tmsm_mux_qup4_se1 = 106,\n\tmsm_mux_qup4_se2 = 107,\n\tmsm_mux_qup4_se3 = 108,\n\tmsm_mux_qup4_se4 = 109,\n\tmsm_mux_sd_write_protect = 110,\n\tmsm_mux_sdc40 = 111,\n\tmsm_mux_sdc41 = 112,\n\tmsm_mux_sdc42 = 113,\n\tmsm_mux_sdc43 = 114,\n\tmsm_mux_sdc4_clk = 115,\n\tmsm_mux_sdc4_cmd = 116,\n\tmsm_mux_sys_throttle = 117,\n\tmsm_mux_tb_trig_sdc2 = 118,\n\tmsm_mux_tb_trig_sdc4 = 119,\n\tmsm_mux_tmess_prng0 = 120,\n\tmsm_mux_tmess_prng1 = 121,\n\tmsm_mux_tmess_prng2 = 122,\n\tmsm_mux_tmess_prng3 = 123,\n\tmsm_mux_tsense_pwm1 = 124,\n\tmsm_mux_tsense_pwm2 = 125,\n\tmsm_mux_tsense_pwm3 = 126,\n\tmsm_mux_tsense_pwm4 = 127,\n\tmsm_mux_tsense_pwm5 = 128,\n\tmsm_mux_tsense_pwm6 = 129,\n\tmsm_mux_tsense_pwm7 = 130,\n\tmsm_mux_uim0_clk = 131,\n\tmsm_mux_uim0_data = 132,\n\tmsm_mux_uim0_present = 133,\n\tmsm_mux_uim0_reset = 134,\n\tmsm_mux_uim1_clk = 135,\n\tmsm_mux_uim1_data = 136,\n\tmsm_mux_uim1_present = 137,\n\tmsm_mux_uim1_reset = 138,\n\tmsm_mux_usb0_hs = 139,\n\tmsm_mux_usb_phy = 140,\n\tmsm_mux_vfr_0 = 141,\n\tmsm_mux_vfr_1 = 142,\n\tmsm_mux_vsense_trigger_mirnat = 143,\n\tmsm_mux_wcn_sw = 144,\n\tmsm_mux_wcn_sw_ctrl = 145,\n\tmsm_mux_____6 = 146,\n};\n\nenum kcmp_type {\n\tKCMP_FILE = 0,\n\tKCMP_VM = 1,\n\tKCMP_FILES = 2,\n\tKCMP_FS = 3,\n\tKCMP_SIGHAND = 4,\n\tKCMP_IO = 5,\n\tKCMP_SYSVSEM = 6,\n\tKCMP_EPOLL_TFD = 7,\n\tKCMP_TYPES = 8,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_being_used_for {\n\tVERIFYING_MODULE_SIGNATURE = 0,\n\tVERIFYING_FIRMWARE_SIGNATURE = 1,\n\tVERIFYING_KEXEC_PE_SIGNATURE = 2,\n\tVERIFYING_KEY_SIGNATURE = 3,\n\tVERIFYING_KEY_SELF_SIGNATURE = 4,\n\tVERIFYING_UNSPECIFIED_SIGNATURE = 5,\n\tVERIFYING_BPF_SIGNATURE = 6,\n\tNR__KEY_BEING_USED_FOR = 7,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_DMA = 2,\n\tKMALLOC_CGROUP = 3,\n\tNR_KMALLOC_TYPES = 4,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kp_band {\n\tKP_BAND_MID = 0,\n\tKP_BAND_HIGH = 1,\n\tKP_BAND_HIGH_HIGH = 2,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum ksm_advisor_type {\n\tKSM_ADVISOR_NONE = 0,\n\tKSM_ADVISOR_SCAN_TIME = 1,\n};\n\nenum ksm_get_folio_flags {\n\tKSM_GET_FOLIO_NOLOCK = 0,\n\tKSM_GET_FOLIO_LOCK = 1,\n\tKSM_GET_FOLIO_TRYLOCK = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum kunwind_source {\n\tKUNWIND_SOURCE_UNKNOWN = 0,\n\tKUNWIND_SOURCE_FRAME = 1,\n\tKUNWIND_SOURCE_CALLER = 2,\n\tKUNWIND_SOURCE_TASK = 3,\n\tKUNWIND_SOURCE_REGS_PC = 4,\n};\n\nenum kvm_arch_timer_regs {\n\tTIMER_REG_CNT = 0,\n\tTIMER_REG_CVAL = 1,\n\tTIMER_REG_TVAL = 2,\n\tTIMER_REG_CTL = 3,\n\tTIMER_REG_VOFF = 4,\n};\n\nenum kvm_arch_timers {\n\tTIMER_PTIMER = 0,\n\tTIMER_VTIMER = 1,\n\tNR_KVM_EL0_TIMERS = 2,\n\tTIMER_HVTIMER = 2,\n\tTIMER_HPTIMER = 3,\n\tNR_KVM_TIMERS = 4,\n};\n\nenum kvm_bus {\n\tKVM_MMIO_BUS = 0,\n\tKVM_PIO_BUS = 1,\n\tKVM_VIRTIO_CCW_NOTIFY_BUS = 2,\n\tKVM_FAST_MMIO_BUS = 3,\n\tKVM_IOCSR_BUS = 4,\n\tKVM_NR_BUSES = 5,\n};\n\nenum kvm_device_type {\n\tKVM_DEV_TYPE_FSL_MPIC_20 = 1,\n\tKVM_DEV_TYPE_FSL_MPIC_42 = 2,\n\tKVM_DEV_TYPE_XICS = 3,\n\tKVM_DEV_TYPE_VFIO = 4,\n\tKVM_DEV_TYPE_ARM_VGIC_V2 = 5,\n\tKVM_DEV_TYPE_FLIC = 6,\n\tKVM_DEV_TYPE_ARM_VGIC_V3 = 7,\n\tKVM_DEV_TYPE_ARM_VGIC_ITS = 8,\n\tKVM_DEV_TYPE_XIVE = 9,\n\tKVM_DEV_TYPE_ARM_PV_TIME = 10,\n\tKVM_DEV_TYPE_RISCV_AIA = 11,\n\tKVM_DEV_TYPE_LOONGARCH_IPI = 12,\n\tKVM_DEV_TYPE_LOONGARCH_EIOINTC = 13,\n\tKVM_DEV_TYPE_LOONGARCH_PCHPIC = 14,\n\tKVM_DEV_TYPE_MAX = 15,\n};\n\nenum kvm_gfn_range_filter {\n\tKVM_FILTER_SHARED = 1,\n\tKVM_FILTER_PRIVATE = 2,\n};\n\nenum kvm_mode {\n\tKVM_MODE_DEFAULT = 0,\n\tKVM_MODE_PROTECTED = 1,\n\tKVM_MODE_NV = 2,\n\tKVM_MODE_NONE = 3,\n};\n\nenum kvm_mr_change {\n\tKVM_MR_CREATE = 0,\n\tKVM_MR_DELETE = 1,\n\tKVM_MR_MOVE = 2,\n\tKVM_MR_FLAGS_ONLY = 3,\n};\n\nenum kvm_pgtable_prot {\n\tKVM_PGTABLE_PROT_PX = 1ULL,\n\tKVM_PGTABLE_PROT_UX = 2ULL,\n\tKVM_PGTABLE_PROT_X = 3ULL,\n\tKVM_PGTABLE_PROT_W = 4ULL,\n\tKVM_PGTABLE_PROT_R = 8ULL,\n\tKVM_PGTABLE_PROT_DEVICE = 16ULL,\n\tKVM_PGTABLE_PROT_NORMAL_NC = 32ULL,\n\tKVM_PGTABLE_PROT_SW0 = 36028797018963968ULL,\n\tKVM_PGTABLE_PROT_SW1 = 72057594037927936ULL,\n\tKVM_PGTABLE_PROT_SW2 = 144115188075855872ULL,\n\tKVM_PGTABLE_PROT_SW3 = 288230376151711744ULL,\n};\n\nenum kvm_pgtable_stage2_flags {\n\tKVM_PGTABLE_S2_IDMAP = 1,\n\tKVM_PGTABLE_S2_AS_S1 = 2,\n};\n\nenum kvm_pgtable_walk_flags {\n\tKVM_PGTABLE_WALK_LEAF = 1,\n\tKVM_PGTABLE_WALK_TABLE_PRE = 2,\n\tKVM_PGTABLE_WALK_TABLE_POST = 4,\n\tKVM_PGTABLE_WALK_SHARED = 8,\n\tKVM_PGTABLE_WALK_IGNORE_EAGAIN = 16,\n\tKVM_PGTABLE_WALK_SKIP_BBM_TLBI = 32,\n\tKVM_PGTABLE_WALK_SKIP_CMO = 64,\n};\n\nenum kvm_smccc_filter_action {\n\tKVM_SMCCC_FILTER_HANDLE = 0,\n\tKVM_SMCCC_FILTER_DENY = 1,\n\tKVM_SMCCC_FILTER_FWD_TO_USER = 2,\n\tNR_SMCCC_FILTER_ACTIONS = 3,\n};\n\nenum kvm_stat_kind {\n\tKVM_STAT_VM = 0,\n\tKVM_STAT_VCPU = 1,\n};\n\nenum kvm_wfx_trap_policy {\n\tKVM_WFX_NOTRAP_SINGLE_TASK = 0,\n\tKVM_WFX_NOTRAP = 1,\n\tKVM_WFX_TRAP = 2,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum latency_range {\n\tlowest_latency = 0,\n\tlow_latency = 1,\n\tbulk_latency = 2,\n\tlatency_invalid = 255,\n};\n\nenum layoutdriver_policy_flags {\n\tPNFS_LAYOUTRET_ON_SETATTR = 1,\n\tPNFS_LAYOUTRET_ON_ERROR = 2,\n\tPNFS_READ_WHOLE_PAGE = 4,\n\tPNFS_LAYOUTGET_ON_OPEN = 8,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum led_default_state {\n\tLEDS_DEFSTATE_OFF = 0,\n\tLEDS_DEFSTATE_ON = 1,\n\tLEDS_DEFSTATE_KEEP = 2,\n};\n\nenum led_mode {\n\tMO_LED_NORM = 0,\n\tMO_LED_BLINK = 1,\n\tMO_LED_OFF = 2,\n\tMO_LED_ON = 3,\n};\n\nenum led_trigger_netdev_modes {\n\tTRIGGER_NETDEV_LINK = 0,\n\tTRIGGER_NETDEV_LINK_10 = 1,\n\tTRIGGER_NETDEV_LINK_100 = 2,\n\tTRIGGER_NETDEV_LINK_1000 = 3,\n\tTRIGGER_NETDEV_LINK_2500 = 4,\n\tTRIGGER_NETDEV_LINK_5000 = 5,\n\tTRIGGER_NETDEV_LINK_10000 = 6,\n\tTRIGGER_NETDEV_HALF_DUPLEX = 7,\n\tTRIGGER_NETDEV_FULL_DUPLEX = 8,\n\tTRIGGER_NETDEV_TX = 9,\n\tTRIGGER_NETDEV_RX = 10,\n\tTRIGGER_NETDEV_TX_ERR = 11,\n\tTRIGGER_NETDEV_RX_ERR = 12,\n\t__TRIGGER_NETDEV_MAX = 13,\n};\n\nenum legacy_scpi_std_cmd {\n\tLEGACY_SCPI_CMD_INVALID = 0,\n\tLEGACY_SCPI_CMD_SCPI_READY = 1,\n\tLEGACY_SCPI_CMD_SCPI_CAPABILITIES = 2,\n\tLEGACY_SCPI_CMD_EVENT = 3,\n\tLEGACY_SCPI_CMD_SET_CSS_PWR_STATE = 4,\n\tLEGACY_SCPI_CMD_GET_CSS_PWR_STATE = 5,\n\tLEGACY_SCPI_CMD_CFG_PWR_STATE_STAT = 6,\n\tLEGACY_SCPI_CMD_GET_PWR_STATE_STAT = 7,\n\tLEGACY_SCPI_CMD_SYS_PWR_STATE = 8,\n\tLEGACY_SCPI_CMD_L2_READY = 9,\n\tLEGACY_SCPI_CMD_SET_AP_TIMER = 10,\n\tLEGACY_SCPI_CMD_CANCEL_AP_TIME = 11,\n\tLEGACY_SCPI_CMD_DVFS_CAPABILITIES = 12,\n\tLEGACY_SCPI_CMD_GET_DVFS_INFO = 13,\n\tLEGACY_SCPI_CMD_SET_DVFS = 14,\n\tLEGACY_SCPI_CMD_GET_DVFS = 15,\n\tLEGACY_SCPI_CMD_GET_DVFS_STAT = 16,\n\tLEGACY_SCPI_CMD_SET_RTC = 17,\n\tLEGACY_SCPI_CMD_GET_RTC = 18,\n\tLEGACY_SCPI_CMD_CLOCK_CAPABILITIES = 19,\n\tLEGACY_SCPI_CMD_SET_CLOCK_INDEX = 20,\n\tLEGACY_SCPI_CMD_SET_CLOCK_VALUE = 21,\n\tLEGACY_SCPI_CMD_GET_CLOCK_VALUE = 22,\n\tLEGACY_SCPI_CMD_PSU_CAPABILITIES = 23,\n\tLEGACY_SCPI_CMD_SET_PSU = 24,\n\tLEGACY_SCPI_CMD_GET_PSU = 25,\n\tLEGACY_SCPI_CMD_SENSOR_CAPABILITIES = 26,\n\tLEGACY_SCPI_CMD_SENSOR_INFO = 27,\n\tLEGACY_SCPI_CMD_SENSOR_VALUE = 28,\n\tLEGACY_SCPI_CMD_SENSOR_CFG_PERIODIC = 29,\n\tLEGACY_SCPI_CMD_SENSOR_CFG_BOUNDS = 30,\n\tLEGACY_SCPI_CMD_SENSOR_ASYNC_VALUE = 31,\n\tLEGACY_SCPI_CMD_COUNT = 32,\n};\n\nenum lightbar_command {\n\tLIGHTBAR_CMD_DUMP = 0,\n\tLIGHTBAR_CMD_OFF = 1,\n\tLIGHTBAR_CMD_ON = 2,\n\tLIGHTBAR_CMD_INIT = 3,\n\tLIGHTBAR_CMD_SET_BRIGHTNESS = 4,\n\tLIGHTBAR_CMD_SEQ = 5,\n\tLIGHTBAR_CMD_REG = 6,\n\tLIGHTBAR_CMD_SET_RGB = 7,\n\tLIGHTBAR_CMD_GET_SEQ = 8,\n\tLIGHTBAR_CMD_DEMO = 9,\n\tLIGHTBAR_CMD_GET_PARAMS_V0 = 10,\n\tLIGHTBAR_CMD_SET_PARAMS_V0 = 11,\n\tLIGHTBAR_CMD_VERSION = 12,\n\tLIGHTBAR_CMD_GET_BRIGHTNESS = 13,\n\tLIGHTBAR_CMD_GET_RGB = 14,\n\tLIGHTBAR_CMD_GET_DEMO = 15,\n\tLIGHTBAR_CMD_GET_PARAMS_V1 = 16,\n\tLIGHTBAR_CMD_SET_PARAMS_V1 = 17,\n\tLIGHTBAR_CMD_SET_PROGRAM = 18,\n\tLIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19,\n\tLIGHTBAR_CMD_SUSPEND = 20,\n\tLIGHTBAR_CMD_RESUME = 21,\n\tLIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22,\n\tLIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23,\n\tLIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24,\n\tLIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25,\n\tLIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26,\n\tLIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27,\n\tLIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28,\n\tLIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29,\n\tLIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30,\n\tLIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31,\n\tLIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32,\n\tLIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33,\n\tLIGHTBAR_CMD_GET_PARAMS_V3 = 34,\n\tLIGHTBAR_CMD_SET_PROGRAM_EX = 35,\n\tLIGHTBAR_NUM_CMDS = 36,\n};\n\nenum limit_by4 {\n\tNFS4_LIMIT_SIZE = 1,\n\tNFS4_LIMIT_BLOCKS = 2,\n};\n\nenum link_inband_signalling {\n\tLINK_INBAND_DISABLE = 1,\n\tLINK_INBAND_ENABLE = 2,\n\tLINK_INBAND_BYPASS = 4,\n};\n\nenum locality_types {\n\tWRITE_LATENCY = 0,\n\tREAD_LATENCY = 1,\n\tWRITE_BANDWIDTH = 2,\n\tREAD_BANDWIDTH = 3,\n};\n\nenum lock_type4 {\n\tNFS4_UNLOCK_LT = 0,\n\tNFS4_READ_LT = 1,\n\tNFS4_WRITE_LT = 2,\n\tNFS4_READW_LT = 3,\n\tNFS4_WRITEW_LT = 4,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum lpi2c_imx_mode {\n\tSTANDARD = 0,\n\tFAST = 1,\n\tFAST_PLUS = 2,\n\tHS = 3,\n\tULTRA_FAST = 4,\n};\n\nenum lpi2c_imx_pincfg {\n\tTWO_PIN_OD = 0,\n\tTWO_PIN_OO = 1,\n\tTWO_PIN_PP = 2,\n\tFOUR_PIN_PP = 3,\n};\n\nenum lpuart_type {\n\tVF610_LPUART = 0,\n\tLS1021A_LPUART = 1,\n\tLS1028A_LPUART = 2,\n\tIMX7ULP_LPUART = 3,\n\tIMX8ULP_LPUART = 4,\n\tIMX8QXP_LPUART = 5,\n\tIMXRT1050_LPUART = 6,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lsm_event {\n\tLSM_POLICY_CHANGE = 0,\n\tLSM_STARTED_ALL = 1,\n};\n\nenum lsm_integrity_type {\n\tLSM_INT_DMVERITY_SIG_VALID = 0,\n\tLSM_INT_DMVERITY_ROOTHASH = 1,\n\tLSM_INT_FSVERITY_BUILTINSIG_VALID = 2,\n};\n\nenum lsm_order {\n\tLSM_ORDER_FIRST = -1,\n\tLSM_ORDER_MUTABLE = 0,\n\tLSM_ORDER_LAST = 1,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum m1_pmu_events {\n\tM1_PMU_PERFCTR_RETIRE_UOP = 1,\n\tM1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 2,\n\tM1_PMU_PERFCTR_L1I_TLB_FILL = 4,\n\tM1_PMU_PERFCTR_L1D_TLB_FILL = 5,\n\tM1_PMU_PERFCTR_MMU_TABLE_WALK_INSTRUCTION = 7,\n\tM1_PMU_PERFCTR_MMU_TABLE_WALK_DATA = 8,\n\tM1_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 10,\n\tM1_PMU_PERFCTR_L2_TLB_MISS_DATA = 11,\n\tM1_PMU_PERFCTR_MMU_VIRTUAL_MEMORY_FAULT_NONSPEC = 13,\n\tM1_PMU_PERFCTR_SCHEDULE_UOP = 82,\n\tM1_PMU_PERFCTR_INTERRUPT_PENDING = 108,\n\tM1_PMU_PERFCTR_MAP_STALL_DISPATCH = 112,\n\tM1_PMU_PERFCTR_MAP_REWIND = 117,\n\tM1_PMU_PERFCTR_MAP_STALL = 118,\n\tM1_PMU_PERFCTR_MAP_INT_UOP = 124,\n\tM1_PMU_PERFCTR_MAP_LDST_UOP = 125,\n\tM1_PMU_PERFCTR_MAP_SIMD_UOP = 126,\n\tM1_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 132,\n\tM1_PMU_PERFCTR_INST_ALL = 140,\n\tM1_PMU_PERFCTR_INST_BRANCH = 141,\n\tM1_PMU_PERFCTR_INST_BRANCH_CALL = 142,\n\tM1_PMU_PERFCTR_INST_BRANCH_RET = 143,\n\tM1_PMU_PERFCTR_INST_BRANCH_TAKEN = 144,\n\tM1_PMU_PERFCTR_INST_BRANCH_INDIR = 147,\n\tM1_PMU_PERFCTR_INST_BRANCH_COND = 148,\n\tM1_PMU_PERFCTR_INST_INT_LD = 149,\n\tM1_PMU_PERFCTR_INST_INT_ST = 150,\n\tM1_PMU_PERFCTR_INST_INT_ALU = 151,\n\tM1_PMU_PERFCTR_INST_SIMD_LD = 152,\n\tM1_PMU_PERFCTR_INST_SIMD_ST = 153,\n\tM1_PMU_PERFCTR_INST_SIMD_ALU = 154,\n\tM1_PMU_PERFCTR_INST_LDST = 155,\n\tM1_PMU_PERFCTR_INST_BARRIER = 156,\n\tM1_PMU_PERFCTR_UNKNOWN_9f = 159,\n\tM1_PMU_PERFCTR_L1D_TLB_ACCESS = 160,\n\tM1_PMU_PERFCTR_L1D_TLB_MISS = 161,\n\tM1_PMU_PERFCTR_L1D_CACHE_MISS_ST = 162,\n\tM1_PMU_PERFCTR_L1D_CACHE_MISS_LD = 163,\n\tM1_PMU_PERFCTR_LD_UNIT_UOP = 166,\n\tM1_PMU_PERFCTR_ST_UNIT_UOP = 167,\n\tM1_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 168,\n\tM1_PMU_PERFCTR_LDST_X64_UOP = 177,\n\tM1_PMU_PERFCTR_LDST_XPG_UOP = 178,\n\tM1_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 179,\n\tM1_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 180,\n\tM1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 191,\n\tM1_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 192,\n\tM1_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 193,\n\tM1_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 196,\n\tM1_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 197,\n\tM1_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 198,\n\tM1_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 200,\n\tM1_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 202,\n\tM1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 203,\n\tM1_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 212,\n\tM1_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 214,\n\tM1_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 219,\n\tM1_PMU_PERFCTR_FETCH_RESTART = 222,\n\tM1_PMU_PERFCTR_ST_NT_UOP = 229,\n\tM1_PMU_PERFCTR_LD_NT_UOP = 230,\n\tM1_PMU_PERFCTR_UNKNOWN_f5 = 245,\n\tM1_PMU_PERFCTR_UNKNOWN_f6 = 246,\n\tM1_PMU_PERFCTR_UNKNOWN_f7 = 247,\n\tM1_PMU_PERFCTR_UNKNOWN_f8 = 248,\n\tM1_PMU_PERFCTR_UNKNOWN_fd = 253,\n\tM1_PMU_PERFCTR_LAST = 255,\n\tM1_PMU_CFG_COUNT_USER = 256,\n\tM1_PMU_CFG_COUNT_KERNEL = 512,\n\tM1_PMU_CFG_COUNT_HOST = 1024,\n\tM1_PMU_CFG_COUNT_GUEST = 2048,\n};\n\nenum mac_commom_mode {\n\tMAC_COMM_MODE_NONE = 0,\n\tMAC_COMM_MODE_RX = 1,\n\tMAC_COMM_MODE_TX = 2,\n\tMAC_COMM_MODE_RX_AND_TX = 3,\n};\n\nenum mac_intf {\n\tMAC_IF_NONE = 0,\n\tMAC_IF_MII = 65536,\n\tMAC_IF_RMII = 131072,\n\tMAC_IF_SMII = 196608,\n\tMAC_IF_GMII = 262144,\n\tMAC_IF_RGMII = 327680,\n\tMAC_IF_TBI = 393216,\n\tMAC_IF_RTBI = 458752,\n\tMAC_IF_SGMII = 524288,\n\tMAC_IF_XGMII = 589824,\n\tMAC_IF_QSGMII = 655360,\n};\n\nenum mac_mode {\n\tMAC_MODE_INVALID = 0,\n\tMAC_MODE_MII_10 = 65546,\n\tMAC_MODE_MII_100 = 65636,\n\tMAC_MODE_RMII_10 = 131082,\n\tMAC_MODE_RMII_100 = 131172,\n\tMAC_MODE_SMII_10 = 196618,\n\tMAC_MODE_SMII_100 = 196708,\n\tMAC_MODE_GMII_1000 = 263144,\n\tMAC_MODE_RGMII_10 = 327690,\n\tMAC_MODE_RGMII_100 = 327780,\n\tMAC_MODE_RGMII_1000 = 328680,\n\tMAC_MODE_TBI_1000 = 394216,\n\tMAC_MODE_RTBI_1000 = 459752,\n\tMAC_MODE_SGMII_10 = 524298,\n\tMAC_MODE_SGMII_100 = 524388,\n\tMAC_MODE_SGMII_1000 = 525288,\n\tMAC_MODE_XGMII_10000 = 599824,\n\tMAC_MODE_QSGMII_1000 = 656360,\n};\n\nenum mac_speed {\n\tMAC_SPEED_10 = 10,\n\tMAC_SPEED_100 = 100,\n\tMAC_SPEED_1000 = 1000,\n\tMAC_SPEED_10000 = 10000,\n};\n\nenum macb_bd_control {\n\tTSTAMP_DISABLED = 0,\n\tTSTAMP_FRAME_PTP_EVENT_ONLY = 1,\n\tTSTAMP_ALL_PTP_FRAMES = 2,\n\tTSTAMP_ALL_FRAMES = 3,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum max77620_alternate_pinmux_option {\n\tMAX77620_PINMUX_GPIO = 0,\n\tMAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,\n\tMAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,\n\tMAX77620_PINMUX_32K_OUT1 = 3,\n\tMAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,\n\tMAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,\n\tMAX77620_PINMUX_REFERENCE_OUT = 6,\n};\n\nenum max77620_chip_id {\n\tMAX77620 = 0,\n\tMAX20024 = 1,\n\tMAX77663 = 2,\n};\n\nenum max77620_fps_src {\n\tMAX77620_FPS_SRC_0 = 0,\n\tMAX77620_FPS_SRC_1 = 1,\n\tMAX77620_FPS_SRC_2 = 2,\n\tMAX77620_FPS_SRC_NONE = 3,\n\tMAX77620_FPS_SRC_DEF = 4,\n};\n\nenum max77620_pin_ppdrv {\n\tMAX77620_PIN_UNCONFIG_DRV = 0,\n\tMAX77620_PIN_OD_DRV = 1,\n\tMAX77620_PIN_PP_DRV = 2,\n};\n\nenum max77620_regulator_type {\n\tMAX77620_REGULATOR_TYPE_SD = 0,\n\tMAX77620_REGULATOR_TYPE_LDO_N = 1,\n\tMAX77620_REGULATOR_TYPE_LDO_P = 2,\n};\n\nenum max77620_regulators {\n\tMAX77620_REGULATOR_ID_SD0 = 0,\n\tMAX77620_REGULATOR_ID_SD1 = 1,\n\tMAX77620_REGULATOR_ID_SD2 = 2,\n\tMAX77620_REGULATOR_ID_SD3 = 3,\n\tMAX77620_REGULATOR_ID_SD4 = 4,\n\tMAX77620_REGULATOR_ID_LDO0 = 5,\n\tMAX77620_REGULATOR_ID_LDO1 = 6,\n\tMAX77620_REGULATOR_ID_LDO2 = 7,\n\tMAX77620_REGULATOR_ID_LDO3 = 8,\n\tMAX77620_REGULATOR_ID_LDO4 = 9,\n\tMAX77620_REGULATOR_ID_LDO5 = 10,\n\tMAX77620_REGULATOR_ID_LDO6 = 11,\n\tMAX77620_REGULATOR_ID_LDO7 = 12,\n\tMAX77620_REGULATOR_ID_LDO8 = 13,\n\tMAX77620_NUM_REGS = 14,\n};\n\nenum max77686_irq {\n\tMAX77686_PMICIRQ_PWRONF = 0,\n\tMAX77686_PMICIRQ_PWRONR = 1,\n\tMAX77686_PMICIRQ_JIGONBF = 2,\n\tMAX77686_PMICIRQ_JIGONBR = 3,\n\tMAX77686_PMICIRQ_ACOKBF = 4,\n\tMAX77686_PMICIRQ_ACOKBR = 5,\n\tMAX77686_PMICIRQ_ONKEY1S = 6,\n\tMAX77686_PMICIRQ_MRSTB = 7,\n\tMAX77686_PMICIRQ_140C = 8,\n\tMAX77686_PMICIRQ_120C = 9,\n\tMAX77686_RTCIRQ_RTC60S = 0,\n\tMAX77686_RTCIRQ_RTCA1 = 1,\n\tMAX77686_RTCIRQ_RTCA2 = 2,\n\tMAX77686_RTCIRQ_SMPL = 3,\n\tMAX77686_RTCIRQ_RTC1S = 4,\n\tMAX77686_RTCIRQ_WTSR = 5,\n};\n\nenum max77686_irq_source {\n\tPMIC_INT1 = 0,\n\tPMIC_INT2 = 1,\n\tRTC_INT = 2,\n\tMAX77686_IRQ_GROUP_NR = 3,\n};\n\nenum max77686_pmic_reg {\n\tMAX77686_REG_DEVICE_ID = 0,\n\tMAX77686_REG_INTSRC = 1,\n\tMAX77686_REG_INT1 = 2,\n\tMAX77686_REG_INT2 = 3,\n\tMAX77686_REG_INT1MSK = 4,\n\tMAX77686_REG_INT2MSK = 5,\n\tMAX77686_REG_STATUS1 = 6,\n\tMAX77686_REG_STATUS2 = 7,\n\tMAX77686_REG_PWRON = 8,\n\tMAX77686_REG_ONOFF_DELAY = 9,\n\tMAX77686_REG_MRSTB = 10,\n\tMAX77686_REG_BUCK1CTRL = 16,\n\tMAX77686_REG_BUCK1OUT = 17,\n\tMAX77686_REG_BUCK2CTRL1 = 18,\n\tMAX77686_REG_BUCK234FREQ = 19,\n\tMAX77686_REG_BUCK2DVS1 = 20,\n\tMAX77686_REG_BUCK2DVS2 = 21,\n\tMAX77686_REG_BUCK2DVS3 = 22,\n\tMAX77686_REG_BUCK2DVS4 = 23,\n\tMAX77686_REG_BUCK2DVS5 = 24,\n\tMAX77686_REG_BUCK2DVS6 = 25,\n\tMAX77686_REG_BUCK2DVS7 = 26,\n\tMAX77686_REG_BUCK2DVS8 = 27,\n\tMAX77686_REG_BUCK3CTRL1 = 28,\n\tMAX77686_REG_BUCK3DVS1 = 30,\n\tMAX77686_REG_BUCK3DVS2 = 31,\n\tMAX77686_REG_BUCK3DVS3 = 32,\n\tMAX77686_REG_BUCK3DVS4 = 33,\n\tMAX77686_REG_BUCK3DVS5 = 34,\n\tMAX77686_REG_BUCK3DVS6 = 35,\n\tMAX77686_REG_BUCK3DVS7 = 36,\n\tMAX77686_REG_BUCK3DVS8 = 37,\n\tMAX77686_REG_BUCK4CTRL1 = 38,\n\tMAX77686_REG_BUCK4DVS1 = 40,\n\tMAX77686_REG_BUCK4DVS2 = 41,\n\tMAX77686_REG_BUCK4DVS3 = 42,\n\tMAX77686_REG_BUCK4DVS4 = 43,\n\tMAX77686_REG_BUCK4DVS5 = 44,\n\tMAX77686_REG_BUCK4DVS6 = 45,\n\tMAX77686_REG_BUCK4DVS7 = 46,\n\tMAX77686_REG_BUCK4DVS8 = 47,\n\tMAX77686_REG_BUCK5CTRL = 48,\n\tMAX77686_REG_BUCK5OUT = 49,\n\tMAX77686_REG_BUCK6CTRL = 50,\n\tMAX77686_REG_BUCK6OUT = 51,\n\tMAX77686_REG_BUCK7CTRL = 52,\n\tMAX77686_REG_BUCK7OUT = 53,\n\tMAX77686_REG_BUCK8CTRL = 54,\n\tMAX77686_REG_BUCK8OUT = 55,\n\tMAX77686_REG_BUCK9CTRL = 56,\n\tMAX77686_REG_BUCK9OUT = 57,\n\tMAX77686_REG_LDO1CTRL1 = 64,\n\tMAX77686_REG_LDO2CTRL1 = 65,\n\tMAX77686_REG_LDO3CTRL1 = 66,\n\tMAX77686_REG_LDO4CTRL1 = 67,\n\tMAX77686_REG_LDO5CTRL1 = 68,\n\tMAX77686_REG_LDO6CTRL1 = 69,\n\tMAX77686_REG_LDO7CTRL1 = 70,\n\tMAX77686_REG_LDO8CTRL1 = 71,\n\tMAX77686_REG_LDO9CTRL1 = 72,\n\tMAX77686_REG_LDO10CTRL1 = 73,\n\tMAX77686_REG_LDO11CTRL1 = 74,\n\tMAX77686_REG_LDO12CTRL1 = 75,\n\tMAX77686_REG_LDO13CTRL1 = 76,\n\tMAX77686_REG_LDO14CTRL1 = 77,\n\tMAX77686_REG_LDO15CTRL1 = 78,\n\tMAX77686_REG_LDO16CTRL1 = 79,\n\tMAX77686_REG_LDO17CTRL1 = 80,\n\tMAX77686_REG_LDO18CTRL1 = 81,\n\tMAX77686_REG_LDO19CTRL1 = 82,\n\tMAX77686_REG_LDO20CTRL1 = 83,\n\tMAX77686_REG_LDO21CTRL1 = 84,\n\tMAX77686_REG_LDO22CTRL1 = 85,\n\tMAX77686_REG_LDO23CTRL1 = 86,\n\tMAX77686_REG_LDO24CTRL1 = 87,\n\tMAX77686_REG_LDO25CTRL1 = 88,\n\tMAX77686_REG_LDO26CTRL1 = 89,\n\tMAX77686_REG_LDO1CTRL2 = 96,\n\tMAX77686_REG_LDO2CTRL2 = 97,\n\tMAX77686_REG_LDO3CTRL2 = 98,\n\tMAX77686_REG_LDO4CTRL2 = 99,\n\tMAX77686_REG_LDO5CTRL2 = 100,\n\tMAX77686_REG_LDO6CTRL2 = 101,\n\tMAX77686_REG_LDO7CTRL2 = 102,\n\tMAX77686_REG_LDO8CTRL2 = 103,\n\tMAX77686_REG_LDO9CTRL2 = 104,\n\tMAX77686_REG_LDO10CTRL2 = 105,\n\tMAX77686_REG_LDO11CTRL2 = 106,\n\tMAX77686_REG_LDO12CTRL2 = 107,\n\tMAX77686_REG_LDO13CTRL2 = 108,\n\tMAX77686_REG_LDO14CTRL2 = 109,\n\tMAX77686_REG_LDO15CTRL2 = 110,\n\tMAX77686_REG_LDO16CTRL2 = 111,\n\tMAX77686_REG_LDO17CTRL2 = 112,\n\tMAX77686_REG_LDO18CTRL2 = 113,\n\tMAX77686_REG_LDO19CTRL2 = 114,\n\tMAX77686_REG_LDO20CTRL2 = 115,\n\tMAX77686_REG_LDO21CTRL2 = 116,\n\tMAX77686_REG_LDO22CTRL2 = 117,\n\tMAX77686_REG_LDO23CTRL2 = 118,\n\tMAX77686_REG_LDO24CTRL2 = 119,\n\tMAX77686_REG_LDO25CTRL2 = 120,\n\tMAX77686_REG_LDO26CTRL2 = 121,\n\tMAX77686_REG_BBAT_CHG = 126,\n\tMAX77686_REG_32KHZ = 127,\n\tMAX77686_REG_PMIC_END = 128,\n};\n\nenum max77686_rtc_reg {\n\tMAX77686_RTC_INT = 0,\n\tMAX77686_RTC_INTM = 1,\n\tMAX77686_RTC_CONTROLM = 2,\n\tMAX77686_RTC_CONTROL = 3,\n\tMAX77686_RTC_UPDATE0 = 4,\n\tMAX77686_WTSR_SMPL_CNTL = 6,\n\tMAX77686_RTC_SEC = 7,\n\tMAX77686_RTC_MIN = 8,\n\tMAX77686_RTC_HOUR = 9,\n\tMAX77686_RTC_WEEKDAY = 10,\n\tMAX77686_RTC_MONTH = 11,\n\tMAX77686_RTC_YEAR = 12,\n\tMAX77686_RTC_MONTHDAY = 13,\n\tMAX77686_ALARM1_SEC = 14,\n\tMAX77686_ALARM1_MIN = 15,\n\tMAX77686_ALARM1_HOUR = 16,\n\tMAX77686_ALARM1_WEEKDAY = 17,\n\tMAX77686_ALARM1_MONTH = 18,\n\tMAX77686_ALARM1_YEAR = 19,\n\tMAX77686_ALARM1_DATE = 20,\n\tMAX77686_ALARM2_SEC = 21,\n\tMAX77686_ALARM2_MIN = 22,\n\tMAX77686_ALARM2_HOUR = 23,\n\tMAX77686_ALARM2_WEEKDAY = 24,\n\tMAX77686_ALARM2_MONTH = 25,\n\tMAX77686_ALARM2_YEAR = 26,\n\tMAX77686_ALARM2_DATE = 27,\n};\n\nenum max77686_rtc_reg_offset {\n\tREG_RTC_CONTROLM = 0,\n\tREG_RTC_CONTROL = 1,\n\tREG_RTC_UPDATE0 = 2,\n\tREG_WTSR_SMPL_CNTL = 3,\n\tREG_RTC_SEC = 4,\n\tREG_RTC_MIN = 5,\n\tREG_RTC_HOUR = 6,\n\tREG_RTC_WEEKDAY = 7,\n\tREG_RTC_MONTH = 8,\n\tREG_RTC_YEAR = 9,\n\tREG_RTC_MONTHDAY = 10,\n\tREG_ALARM1_SEC = 11,\n\tREG_ALARM1_MIN = 12,\n\tREG_ALARM1_HOUR = 13,\n\tREG_ALARM1_WEEKDAY = 14,\n\tREG_ALARM1_MONTH = 15,\n\tREG_ALARM1_YEAR = 16,\n\tREG_ALARM1_DATE = 17,\n\tREG_ALARM2_SEC = 18,\n\tREG_ALARM2_MIN = 19,\n\tREG_ALARM2_HOUR = 20,\n\tREG_ALARM2_WEEKDAY = 21,\n\tREG_ALARM2_MONTH = 22,\n\tREG_ALARM2_YEAR = 23,\n\tREG_ALARM2_DATE = 24,\n\tREG_RTC_AE1 = 25,\n\tREG_RTC_END = 26,\n};\n\nenum max77802_rtc_reg {\n\tMAX77802_RTC_INT = 192,\n\tMAX77802_RTC_INTM = 193,\n\tMAX77802_RTC_CONTROLM = 194,\n\tMAX77802_RTC_CONTROL = 195,\n\tMAX77802_RTC_UPDATE0 = 196,\n\tMAX77802_RTC_UPDATE1 = 197,\n\tMAX77802_WTSR_SMPL_CNTL = 198,\n\tMAX77802_RTC_SEC = 199,\n\tMAX77802_RTC_MIN = 200,\n\tMAX77802_RTC_HOUR = 201,\n\tMAX77802_RTC_WEEKDAY = 202,\n\tMAX77802_RTC_MONTH = 203,\n\tMAX77802_RTC_YEAR = 204,\n\tMAX77802_RTC_MONTHDAY = 205,\n\tMAX77802_RTC_AE1 = 206,\n\tMAX77802_ALARM1_SEC = 207,\n\tMAX77802_ALARM1_MIN = 208,\n\tMAX77802_ALARM1_HOUR = 209,\n\tMAX77802_ALARM1_WEEKDAY = 210,\n\tMAX77802_ALARM1_MONTH = 211,\n\tMAX77802_ALARM1_YEAR = 212,\n\tMAX77802_ALARM1_DATE = 213,\n\tMAX77802_RTC_AE2 = 214,\n\tMAX77802_ALARM2_SEC = 215,\n\tMAX77802_ALARM2_MIN = 216,\n\tMAX77802_ALARM2_HOUR = 217,\n\tMAX77802_ALARM2_WEEKDAY = 218,\n\tMAX77802_ALARM2_MONTH = 219,\n\tMAX77802_ALARM2_YEAR = 220,\n\tMAX77802_ALARM2_DATE = 221,\n\tMAX77802_RTC_END = 223,\n};\n\nenum mc_cmd_status {\n\tMC_CMD_STATUS_OK = 0,\n\tMC_CMD_STATUS_READY = 1,\n\tMC_CMD_STATUS_AUTH_ERR = 3,\n\tMC_CMD_STATUS_NO_PRIVILEGE = 4,\n\tMC_CMD_STATUS_DMA_ERR = 5,\n\tMC_CMD_STATUS_CONFIG_ERR = 6,\n\tMC_CMD_STATUS_TIMEOUT = 7,\n\tMC_CMD_STATUS_NO_RESOURCE = 8,\n\tMC_CMD_STATUS_NO_MEMORY = 9,\n\tMC_CMD_STATUS_BUSY = 10,\n\tMC_CMD_STATUS_UNSUPPORTED_OP = 11,\n\tMC_CMD_STATUS_INVALID_STATE = 12,\n};\n\nenum mctrl_gpio_idx {\n\tUART_GPIO_CTS = 0,\n\tUART_GPIO_DSR = 1,\n\tUART_GPIO_DCD = 2,\n\tUART_GPIO_RNG = 3,\n\tUART_GPIO_RI = 3,\n\tUART_GPIO_RTS = 4,\n\tUART_GPIO_DTR = 5,\n\tUART_GPIO_MAX = 6,\n};\n\nenum mdio_c22_op_seq {\n\tMDIO_C22_WRITE = 1,\n\tMDIO_C22_READ = 2,\n};\n\nenum mdio_c45_op_seq {\n\tMDIO_C45_WRITE_ADDR = 0,\n\tMDIO_C45_WRITE_DATA = 1,\n\tMDIO_C45_READ_INCREMENT = 2,\n\tMDIO_C45_READ = 3,\n};\n\nenum mdio_st_clause {\n\tMDIO_ST_CLAUSE_45 = 0,\n\tMDIO_ST_CLAUSE_22 = 1,\n};\n\nenum mem_type {\n\tMEM_EMPTY = 0,\n\tMEM_RESERVED = 1,\n\tMEM_UNKNOWN = 2,\n\tMEM_FPM = 3,\n\tMEM_EDO = 4,\n\tMEM_BEDO = 5,\n\tMEM_SDR = 6,\n\tMEM_RDR = 7,\n\tMEM_DDR = 8,\n\tMEM_RDDR = 9,\n\tMEM_RMBS = 10,\n\tMEM_DDR2 = 11,\n\tMEM_FB_DDR2 = 12,\n\tMEM_RDDR2 = 13,\n\tMEM_XDR = 14,\n\tMEM_DDR3 = 15,\n\tMEM_RDDR3 = 16,\n\tMEM_LRDDR3 = 17,\n\tMEM_LPDDR3 = 18,\n\tMEM_DDR4 = 19,\n\tMEM_RDDR4 = 20,\n\tMEM_LRDDR4 = 21,\n\tMEM_LPDDR4 = 22,\n\tMEM_DDR5 = 23,\n\tMEM_RDDR5 = 24,\n\tMEM_LRDDR5 = 25,\n\tMEM_NVDIMM = 26,\n\tMEM_WIO2 = 27,\n\tMEM_HBM2 = 28,\n\tMEM_HBM3 = 29,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 51,\n\tMEMCG_SOCK = 52,\n\tMEMCG_PERCPU_B = 53,\n\tMEMCG_VMALLOC = 54,\n\tMEMCG_KMEM = 55,\n\tMEMCG_ZSWAP_B = 56,\n\tMEMCG_ZSWAPPED = 57,\n\tMEMCG_NR_STAT = 58,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum meson_pinconf_drv {\n\tMESON_PINCONF_DRV_500UA = 0,\n\tMESON_PINCONF_DRV_2500UA = 1,\n\tMESON_PINCONF_DRV_3000UA = 2,\n\tMESON_PINCONF_DRV_4000UA = 3,\n};\n\nenum meson_reg_type {\n\tMESON_REG_PULLEN = 0,\n\tMESON_REG_PULL = 1,\n\tMESON_REG_DIR = 2,\n\tMESON_REG_OUT = 3,\n\tMESON_REG_IN = 4,\n\tMESON_REG_DS = 5,\n\tMESON_NUM_REG = 6,\n};\n\nenum meson_sar_adc_avg_mode {\n\tNO_AVERAGING = 0,\n\tMEAN_AVERAGING = 1,\n\tMEDIAN_AVERAGING = 2,\n};\n\nenum meson_sar_adc_chan7_mux_sel {\n\tCHAN7_MUX_VSS = 0,\n\tCHAN7_MUX_VDD_DIV4 = 1,\n\tCHAN7_MUX_VDD_DIV2 = 2,\n\tCHAN7_MUX_VDD_MUL3_DIV4 = 3,\n\tCHAN7_MUX_VDD = 4,\n\tCHAN7_MUX_CH7_INPUT = 7,\n};\n\nenum meson_sar_adc_channel_index {\n\tNUM_CHAN_0 = 0,\n\tNUM_CHAN_1 = 1,\n\tNUM_CHAN_2 = 2,\n\tNUM_CHAN_3 = 3,\n\tNUM_CHAN_4 = 4,\n\tNUM_CHAN_5 = 5,\n\tNUM_CHAN_6 = 6,\n\tNUM_CHAN_7 = 7,\n\tNUM_CHAN_TEMP = 8,\n\tNUM_MUX_0_VSS = 9,\n\tNUM_MUX_1_VDD_DIV4 = 10,\n\tNUM_MUX_2_VDD_DIV2 = 11,\n\tNUM_MUX_3_VDD_MUL3_DIV4 = 12,\n\tNUM_MUX_4_VDD = 13,\n};\n\nenum meson_sar_adc_num_samples {\n\tONE_SAMPLE = 0,\n\tTWO_SAMPLES = 1,\n\tFOUR_SAMPLES = 2,\n\tEIGHT_SAMPLES = 3,\n};\n\nenum meson_sar_adc_vref_sel {\n\tVREF_CALIBATION_VOLTAGE = 0,\n\tVREF_VDDA = 1,\n};\n\nenum meson_soc_id {\n\tMESON_SOC_G12A = 0,\n\tMESON_SOC_A1 = 1,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mext_move_type {\n\tMEXT_SKIP_EXTENT = 0,\n\tMEXT_MOVE_EXTENT = 1,\n\tMEXT_COPY_DATA = 2,\n};\n\nenum mf_action_page_type {\n\tMF_MSG_KERNEL = 0,\n\tMF_MSG_KERNEL_HIGH_ORDER = 1,\n\tMF_MSG_DIFFERENT_COMPOUND = 2,\n\tMF_MSG_HUGE = 3,\n\tMF_MSG_FREE_HUGE = 4,\n\tMF_MSG_GET_HWPOISON = 5,\n\tMF_MSG_UNMAP_FAILED = 6,\n\tMF_MSG_DIRTY_SWAPCACHE = 7,\n\tMF_MSG_CLEAN_SWAPCACHE = 8,\n\tMF_MSG_DIRTY_MLOCKED_LRU = 9,\n\tMF_MSG_CLEAN_MLOCKED_LRU = 10,\n\tMF_MSG_DIRTY_UNEVICTABLE_LRU = 11,\n\tMF_MSG_CLEAN_UNEVICTABLE_LRU = 12,\n\tMF_MSG_DIRTY_LRU = 13,\n\tMF_MSG_CLEAN_LRU = 14,\n\tMF_MSG_TRUNCATED_LRU = 15,\n\tMF_MSG_BUDDY = 16,\n\tMF_MSG_DAX = 17,\n\tMF_MSG_UNSPLIT_THP = 18,\n\tMF_MSG_ALREADY_POISONED = 19,\n\tMF_MSG_PFN_MAP = 20,\n\tMF_MSG_UNKNOWN = 21,\n};\n\nenum mf_flags {\n\tMF_COUNT_INCREASED = 1,\n\tMF_ACTION_REQUIRED = 2,\n\tMF_MUST_KILL = 4,\n\tMF_SOFT_OFFLINE = 8,\n\tMF_UNPOISON = 16,\n\tMF_SW_SIMULATED = 32,\n\tMF_NO_RETRY = 64,\n\tMF_MEM_PRE_REMOVE = 128,\n};\n\nenum mf_result {\n\tMF_IGNORED = 0,\n\tMF_FAILED = 1,\n\tMF_DELAYED = 2,\n\tMF_RECOVERED = 3,\n};\n\nenum mfi_evt_class {\n\tMFI_EVT_CLASS_DEBUG = -2,\n\tMFI_EVT_CLASS_PROGRESS = -1,\n\tMFI_EVT_CLASS_INFO = 0,\n\tMFI_EVT_CLASS_WARNING = 1,\n\tMFI_EVT_CLASS_CRITICAL = 2,\n\tMFI_EVT_CLASS_FATAL = 3,\n\tMFI_EVT_CLASS_DEAD = 4,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\tMIGRATE_CMA = 4,\n\t__MIGRATE_TYPE_END = 4,\n\tMIGRATE_ISOLATE = 5,\n\tMIGRATE_TYPES = 6,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum milos_functions {\n\tmsm_mux_gpio___8 = 0,\n\tmsm_mux_aoss_cti___2 = 1,\n\tmsm_mux_atest_char___8 = 2,\n\tmsm_mux_atest_usb___2 = 3,\n\tmsm_mux_audio_ext_mclk0___2 = 4,\n\tmsm_mux_audio_ext_mclk1___2 = 5,\n\tmsm_mux_audio_ref_clk___2 = 6,\n\tmsm_mux_cam_mclk___2 = 7,\n\tmsm_mux_cci_async_in0 = 8,\n\tmsm_mux_cci_i2c_scl___2 = 9,\n\tmsm_mux_cci_i2c_sda___2 = 10,\n\tmsm_mux_cci_timer___2 = 11,\n\tmsm_mux_coex_uart1_rx___2 = 12,\n\tmsm_mux_coex_uart1_tx___2 = 13,\n\tmsm_mux_dbg_out_clk___2 = 14,\n\tmsm_mux_ddr_bist_complete___2 = 15,\n\tmsm_mux_ddr_bist_fail___2 = 16,\n\tmsm_mux_ddr_bist_start___2 = 17,\n\tmsm_mux_ddr_bist_stop___2 = 18,\n\tmsm_mux_ddr_pxi0___2 = 19,\n\tmsm_mux_ddr_pxi1___2 = 20,\n\tmsm_mux_dp0_hot = 21,\n\tmsm_mux_egpio___2 = 22,\n\tmsm_mux_gcc_gp1___2 = 23,\n\tmsm_mux_gcc_gp2___2 = 24,\n\tmsm_mux_gcc_gp3___2 = 25,\n\tmsm_mux_host2wlan_sol = 26,\n\tmsm_mux_i2s0_data0___2 = 27,\n\tmsm_mux_i2s0_data1___2 = 28,\n\tmsm_mux_i2s0_sck___2 = 29,\n\tmsm_mux_i2s0_ws___2 = 30,\n\tmsm_mux_ibi_i3c___2 = 31,\n\tmsm_mux_jitter_bist___2 = 32,\n\tmsm_mux_mdp_vsync___2 = 33,\n\tmsm_mux_mdp_vsync0_out___2 = 34,\n\tmsm_mux_mdp_vsync1_out___2 = 35,\n\tmsm_mux_mdp_vsync2_out___2 = 36,\n\tmsm_mux_mdp_vsync3_out___2 = 37,\n\tmsm_mux_mdp_vsync_e___2 = 38,\n\tmsm_mux_nav_gpio0___2 = 39,\n\tmsm_mux_nav_gpio1___2 = 40,\n\tmsm_mux_nav_gpio2___2 = 41,\n\tmsm_mux_pcie0_clk_req_n___2 = 42,\n\tmsm_mux_pcie1_clk_req_n = 43,\n\tmsm_mux_phase_flag___2 = 44,\n\tmsm_mux_pll_bist_sync___2 = 45,\n\tmsm_mux_pll_clk_aux___2 = 46,\n\tmsm_mux_prng_rosc0___5 = 47,\n\tmsm_mux_prng_rosc1___5 = 48,\n\tmsm_mux_prng_rosc2___5 = 49,\n\tmsm_mux_prng_rosc3___5 = 50,\n\tmsm_mux_qdss_cti___2 = 51,\n\tmsm_mux_qdss_gpio = 52,\n\tmsm_mux_qlink0_enable = 53,\n\tmsm_mux_qlink0_request = 54,\n\tmsm_mux_qlink0_wmss = 55,\n\tmsm_mux_qlink1_enable = 56,\n\tmsm_mux_qlink1_request = 57,\n\tmsm_mux_qlink1_wmss = 58,\n\tmsm_mux_qspi0___2 = 59,\n\tmsm_mux_qup0_se0 = 60,\n\tmsm_mux_qup0_se1 = 61,\n\tmsm_mux_qup0_se2 = 62,\n\tmsm_mux_qup0_se3 = 63,\n\tmsm_mux_qup0_se4 = 64,\n\tmsm_mux_qup0_se5 = 65,\n\tmsm_mux_qup0_se6 = 66,\n\tmsm_mux_qup1_se0___2 = 67,\n\tmsm_mux_qup1_se1___2 = 68,\n\tmsm_mux_qup1_se2___2 = 69,\n\tmsm_mux_qup1_se3___2 = 70,\n\tmsm_mux_qup1_se4___2 = 71,\n\tmsm_mux_qup1_se5___2 = 72,\n\tmsm_mux_qup1_se6___2 = 73,\n\tmsm_mux_resout_gpio_n = 74,\n\tmsm_mux_sd_write_protect___2 = 75,\n\tmsm_mux_sdc1_clk___2 = 76,\n\tmsm_mux_sdc1_cmd___2 = 77,\n\tmsm_mux_sdc1_data___2 = 78,\n\tmsm_mux_sdc1_rclk = 79,\n\tmsm_mux_sdc2_clk = 80,\n\tmsm_mux_sdc2_cmd = 81,\n\tmsm_mux_sdc2_data = 82,\n\tmsm_mux_sdc2_fb_clk = 83,\n\tmsm_mux_tb_trig_sdc1 = 84,\n\tmsm_mux_tb_trig_sdc2___2 = 85,\n\tmsm_mux_tgu_ch0_trigout = 86,\n\tmsm_mux_tgu_ch1_trigout = 87,\n\tmsm_mux_tmess_prng0___2 = 88,\n\tmsm_mux_tmess_prng1___2 = 89,\n\tmsm_mux_tmess_prng2___2 = 90,\n\tmsm_mux_tmess_prng3___2 = 91,\n\tmsm_mux_tsense_pwm1___2 = 92,\n\tmsm_mux_tsense_pwm2___2 = 93,\n\tmsm_mux_uim0_clk___2 = 94,\n\tmsm_mux_uim0_data___2 = 95,\n\tmsm_mux_uim0_present___2 = 96,\n\tmsm_mux_uim0_reset___2 = 97,\n\tmsm_mux_uim1_clk_mira = 98,\n\tmsm_mux_uim1_clk_mirb = 99,\n\tmsm_mux_uim1_data_mira = 100,\n\tmsm_mux_uim1_data_mirb = 101,\n\tmsm_mux_uim1_present_mira = 102,\n\tmsm_mux_uim1_present_mirb = 103,\n\tmsm_mux_uim1_reset_mira = 104,\n\tmsm_mux_uim1_reset_mirb = 105,\n\tmsm_mux_usb0_hs___2 = 106,\n\tmsm_mux_usb0_phy_ps = 107,\n\tmsm_mux_vfr_0___2 = 108,\n\tmsm_mux_vfr_1___2 = 109,\n\tmsm_mux_vsense_trigger_mirnat___2 = 110,\n\tmsm_mux_wcn_sw___2 = 111,\n\tmsm_mux_wcn_sw_ctrl___2 = 112,\n\tmsm_mux_____7 = 113,\n};\n\nenum mipi_dsi_compression_algo {\n\tMIPI_DSI_COMPRESSION_DSC = 0,\n\tMIPI_DSI_COMPRESSION_VENDOR = 3,\n};\n\nenum mipi_dsi_dcs_tear_mode {\n\tMIPI_DSI_DCS_TEAR_MODE_VBLANK = 0,\n\tMIPI_DSI_DCS_TEAR_MODE_VHBLANK = 1,\n};\n\nenum mipi_dsi_pixel_format {\n\tMIPI_DSI_FMT_RGB888 = 0,\n\tMIPI_DSI_FMT_RGB666 = 1,\n\tMIPI_DSI_FMT_RGB666_PACKED = 2,\n\tMIPI_DSI_FMT_RGB565 = 3,\n};\n\nenum mitigation_state {\n\tSPECTRE_UNAFFECTED = 0,\n\tSPECTRE_MITIGATED = 1,\n\tSPECTRE_VULNERABLE = 2,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mmc_busy_cmd {\n\tMMC_BUSY_CMD6 = 0,\n\tMMC_BUSY_ERASE = 1,\n\tMMC_BUSY_HPI = 2,\n\tMMC_BUSY_EXTR_SINGLE = 3,\n\tMMC_BUSY_IO = 4,\n};\n\nenum mmc_drv_op {\n\tMMC_DRV_OP_IOCTL = 0,\n\tMMC_DRV_OP_IOCTL_RPMB = 1,\n\tMMC_DRV_OP_BOOT_WP = 2,\n\tMMC_DRV_OP_GET_CARD_STATUS = 3,\n\tMMC_DRV_OP_GET_EXT_CSD = 4,\n};\n\nenum mmc_err_stat {\n\tMMC_ERR_CMD_TIMEOUT = 0,\n\tMMC_ERR_CMD_CRC = 1,\n\tMMC_ERR_DAT_TIMEOUT = 2,\n\tMMC_ERR_DAT_CRC = 3,\n\tMMC_ERR_AUTO_CMD = 4,\n\tMMC_ERR_ADMA = 5,\n\tMMC_ERR_TUNING = 6,\n\tMMC_ERR_CMDQ_RED = 7,\n\tMMC_ERR_CMDQ_GCE = 8,\n\tMMC_ERR_CMDQ_ICCE = 9,\n\tMMC_ERR_REQ_TIMEOUT = 10,\n\tMMC_ERR_CMDQ_REQ_TIMEOUT = 11,\n\tMMC_ERR_ICE_CFG = 12,\n\tMMC_ERR_CTRL_TIMEOUT = 13,\n\tMMC_ERR_UNEXPECTED_IRQ = 14,\n\tMMC_ERR_MAX = 15,\n};\n\nenum mmc_issue_type {\n\tMMC_ISSUE_SYNC = 0,\n\tMMC_ISSUE_DCMD = 1,\n\tMMC_ISSUE_ASYNC = 2,\n\tMMC_ISSUE_MAX = 3,\n};\n\nenum mmc_issued {\n\tMMC_REQ_STARTED = 0,\n\tMMC_REQ_BUSY = 1,\n\tMMC_REQ_FAILED_TO_START = 2,\n\tMMC_REQ_FINISHED = 3,\n};\n\nenum mmc_poweroff_type {\n\tMMC_POWEROFF_SUSPEND = 0,\n\tMMC_POWEROFF_SHUTDOWN = 1,\n\tMMC_POWEROFF_UNDERVOLTAGE = 2,\n\tMMC_POWEROFF_UNBIND = 3,\n};\n\nenum mmci_busy_state {\n\tMMCI_BUSY_WAITING_FOR_START_IRQ = 0,\n\tMMCI_BUSY_WAITING_FOR_END_IRQ = 1,\n\tMMCI_BUSY_DONE = 2,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mmu_notifier_event {\n\tMMU_NOTIFY_UNMAP = 0,\n\tMMU_NOTIFY_CLEAR = 1,\n\tMMU_NOTIFY_PROTECTION_VMA = 2,\n\tMMU_NOTIFY_PROTECTION_PAGE = 3,\n\tMMU_NOTIFY_SOFT_DIRTY = 4,\n\tMMU_NOTIFY_RELEASE = 5,\n\tMMU_NOTIFY_MIGRATE = 6,\n\tMMU_NOTIFY_EXCLUSIVE = 7,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum motionsense_command {\n\tMOTIONSENSE_CMD_DUMP = 0,\n\tMOTIONSENSE_CMD_INFO = 1,\n\tMOTIONSENSE_CMD_EC_RATE = 2,\n\tMOTIONSENSE_CMD_SENSOR_ODR = 3,\n\tMOTIONSENSE_CMD_SENSOR_RANGE = 4,\n\tMOTIONSENSE_CMD_KB_WAKE_ANGLE = 5,\n\tMOTIONSENSE_CMD_DATA = 6,\n\tMOTIONSENSE_CMD_FIFO_INFO = 7,\n\tMOTIONSENSE_CMD_FIFO_FLUSH = 8,\n\tMOTIONSENSE_CMD_FIFO_READ = 9,\n\tMOTIONSENSE_CMD_PERFORM_CALIB = 10,\n\tMOTIONSENSE_CMD_SENSOR_OFFSET = 11,\n\tMOTIONSENSE_CMD_LIST_ACTIVITIES = 12,\n\tMOTIONSENSE_CMD_SET_ACTIVITY = 13,\n\tMOTIONSENSE_CMD_LID_ANGLE = 14,\n\tMOTIONSENSE_CMD_FIFO_INT_ENABLE = 15,\n\tMOTIONSENSE_CMD_SPOOF = 16,\n\tMOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17,\n\tMOTIONSENSE_CMD_SENSOR_SCALE = 18,\n\tMOTIONSENSE_CMD_GET_ACTIVITY = 20,\n\tMOTIONSENSE_NUM_CMDS = 21,\n};\n\nenum motionsensor_type {\n\tMOTIONSENSE_TYPE_ACCEL = 0,\n\tMOTIONSENSE_TYPE_GYRO = 1,\n\tMOTIONSENSE_TYPE_MAG = 2,\n\tMOTIONSENSE_TYPE_PROX = 3,\n\tMOTIONSENSE_TYPE_LIGHT = 4,\n\tMOTIONSENSE_TYPE_ACTIVITY = 5,\n\tMOTIONSENSE_TYPE_BARO = 6,\n\tMOTIONSENSE_TYPE_SYNC = 7,\n\tMOTIONSENSE_TYPE_MAX = 8,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mountstat {\n\tMNT_OK = 0,\n\tMNT_EPERM = 1,\n\tMNT_ENOENT = 2,\n\tMNT_EACCES = 13,\n\tMNT_EINVAL = 22,\n};\n\nenum mountstat3 {\n\tMNT3_OK = 0,\n\tMNT3ERR_PERM = 1,\n\tMNT3ERR_NOENT = 2,\n\tMNT3ERR_IO = 5,\n\tMNT3ERR_ACCES = 13,\n\tMNT3ERR_NOTDIR = 20,\n\tMNT3ERR_INVAL = 22,\n\tMNT3ERR_NAMETOOLONG = 63,\n\tMNT3ERR_NOTSUPP = 10004,\n\tMNT3ERR_SERVERFAULT = 10006,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum mrq_bwmgr_int_cmd {\n\tCMD_BWMGR_INT_QUERY_ABI = 1,\n\tCMD_BWMGR_INT_CALC_AND_SET = 2,\n\tCMD_BWMGR_INT_CAP_SET = 3,\n};\n\nenum mrq_debug_commands {\n\tCMD_DEBUG_OPEN_RO = 0,\n\tCMD_DEBUG_OPEN_WO = 1,\n\tCMD_DEBUG_READ = 2,\n\tCMD_DEBUG_WRITE = 3,\n\tCMD_DEBUG_CLOSE = 4,\n\tCMD_DEBUG_MAX = 5,\n};\n\nenum mrq_debugfs_commands {\n\tCMD_DEBUGFS_READ = 1,\n\tCMD_DEBUGFS_WRITE = 2,\n\tCMD_DEBUGFS_DUMPDIR = 3,\n\tCMD_DEBUGFS_MAX = 4,\n};\n\nenum mrq_pg_cmd {\n\tCMD_PG_QUERY_ABI = 0,\n\tCMD_PG_SET_STATE = 1,\n\tCMD_PG_GET_STATE = 2,\n\tCMD_PG_GET_NAME = 3,\n\tCMD_PG_GET_MAX_ID = 4,\n};\n\nenum mrq_reset_commands {\n\tCMD_RESET_ASSERT = 1,\n\tCMD_RESET_DEASSERT = 2,\n\tCMD_RESET_MODULE = 3,\n\tCMD_RESET_GET_MAX_ID = 4,\n\tCMD_RESET_MAX = 5,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msg_end_type {\n\tMSG_END_STOP = 0,\n\tMSG_END_REPEAT_START = 1,\n\tMSG_END_CONTINUE = 2,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum msm8916_functions {\n\tmsm_mux_adsp_ext = 0,\n\tmsm_mux_alsp_int = 1,\n\tmsm_mux_atest_bbrx0 = 2,\n\tmsm_mux_atest_bbrx1 = 3,\n\tmsm_mux_atest_char___9 = 4,\n\tmsm_mux_atest_char0___6 = 5,\n\tmsm_mux_atest_char1___6 = 6,\n\tmsm_mux_atest_char2___6 = 7,\n\tmsm_mux_atest_char3___6 = 8,\n\tmsm_mux_atest_combodac = 9,\n\tmsm_mux_atest_gpsadc0 = 10,\n\tmsm_mux_atest_gpsadc1 = 11,\n\tmsm_mux_atest_tsens = 12,\n\tmsm_mux_atest_wlan0 = 13,\n\tmsm_mux_atest_wlan1 = 14,\n\tmsm_mux_backlight_en = 15,\n\tmsm_mux_bimc_dte0 = 16,\n\tmsm_mux_bimc_dte1 = 17,\n\tmsm_mux_blsp_i2c1 = 18,\n\tmsm_mux_blsp_i2c2 = 19,\n\tmsm_mux_blsp_i2c3 = 20,\n\tmsm_mux_blsp_i2c4 = 21,\n\tmsm_mux_blsp_i2c5 = 22,\n\tmsm_mux_blsp_i2c6 = 23,\n\tmsm_mux_blsp_spi1 = 24,\n\tmsm_mux_blsp_spi1_cs1 = 25,\n\tmsm_mux_blsp_spi1_cs2 = 26,\n\tmsm_mux_blsp_spi1_cs3 = 27,\n\tmsm_mux_blsp_spi2 = 28,\n\tmsm_mux_blsp_spi2_cs1 = 29,\n\tmsm_mux_blsp_spi2_cs2 = 30,\n\tmsm_mux_blsp_spi2_cs3 = 31,\n\tmsm_mux_blsp_spi3 = 32,\n\tmsm_mux_blsp_spi3_cs1 = 33,\n\tmsm_mux_blsp_spi3_cs2 = 34,\n\tmsm_mux_blsp_spi3_cs3 = 35,\n\tmsm_mux_blsp_spi4 = 36,\n\tmsm_mux_blsp_spi5 = 37,\n\tmsm_mux_blsp_spi6 = 38,\n\tmsm_mux_blsp_uart1 = 39,\n\tmsm_mux_blsp_uart2 = 40,\n\tmsm_mux_blsp_uim1 = 41,\n\tmsm_mux_blsp_uim2 = 42,\n\tmsm_mux_cam1_rst = 43,\n\tmsm_mux_cam1_standby = 44,\n\tmsm_mux_cam_mclk0 = 45,\n\tmsm_mux_cam_mclk1 = 46,\n\tmsm_mux_cci_async = 47,\n\tmsm_mux_cci_i2c = 48,\n\tmsm_mux_cci_timer0 = 49,\n\tmsm_mux_cci_timer1 = 50,\n\tmsm_mux_cci_timer2 = 51,\n\tmsm_mux_cdc_pdm0 = 52,\n\tmsm_mux_codec_mad = 53,\n\tmsm_mux_dbg_out___7 = 54,\n\tmsm_mux_display_5v = 55,\n\tmsm_mux_dmic0_clk = 56,\n\tmsm_mux_dmic0_data = 57,\n\tmsm_mux_dsi_rst = 58,\n\tmsm_mux_ebi0_wrcdc = 59,\n\tmsm_mux_euro_us = 60,\n\tmsm_mux_ext_lpass = 61,\n\tmsm_mux_flash_strobe = 62,\n\tmsm_mux_gcc_gp1_clk_a = 63,\n\tmsm_mux_gcc_gp1_clk_b = 64,\n\tmsm_mux_gcc_gp2_clk_a = 65,\n\tmsm_mux_gcc_gp2_clk_b = 66,\n\tmsm_mux_gcc_gp3_clk_a = 67,\n\tmsm_mux_gcc_gp3_clk_b = 68,\n\tmsm_mux_gpio___9 = 69,\n\tmsm_mux_gsm0_tx0 = 70,\n\tmsm_mux_gsm0_tx1 = 71,\n\tmsm_mux_gsm1_tx0 = 72,\n\tmsm_mux_gsm1_tx1 = 73,\n\tmsm_mux_gyro_accl = 74,\n\tmsm_mux_kpsns0 = 75,\n\tmsm_mux_kpsns1 = 76,\n\tmsm_mux_kpsns2 = 77,\n\tmsm_mux_ldo_en___2 = 78,\n\tmsm_mux_ldo_update___2 = 79,\n\tmsm_mux_mag_int = 80,\n\tmsm_mux_mdp_vsync___3 = 81,\n\tmsm_mux_modem_tsync = 82,\n\tmsm_mux_m_voc = 83,\n\tmsm_mux_nav_pps = 84,\n\tmsm_mux_nav_tsync = 85,\n\tmsm_mux_pa_indicator = 86,\n\tmsm_mux_pbs0 = 87,\n\tmsm_mux_pbs1 = 88,\n\tmsm_mux_pbs2 = 89,\n\tmsm_mux_pri_mi2s = 90,\n\tmsm_mux_pri_mi2s_ws = 91,\n\tmsm_mux_prng_rosc___4 = 92,\n\tmsm_mux_pwr_crypto_enabled_a = 93,\n\tmsm_mux_pwr_crypto_enabled_b = 94,\n\tmsm_mux_pwr_modem_enabled_a = 95,\n\tmsm_mux_pwr_modem_enabled_b = 96,\n\tmsm_mux_pwr_nav_enabled_a = 97,\n\tmsm_mux_pwr_nav_enabled_b = 98,\n\tmsm_mux_qdss_ctitrig_in_a0 = 99,\n\tmsm_mux_qdss_ctitrig_in_a1 = 100,\n\tmsm_mux_qdss_ctitrig_in_b0 = 101,\n\tmsm_mux_qdss_ctitrig_in_b1 = 102,\n\tmsm_mux_qdss_ctitrig_out_a0 = 103,\n\tmsm_mux_qdss_ctitrig_out_a1 = 104,\n\tmsm_mux_qdss_ctitrig_out_b0 = 105,\n\tmsm_mux_qdss_ctitrig_out_b1 = 106,\n\tmsm_mux_qdss_traceclk_a___7 = 107,\n\tmsm_mux_qdss_traceclk_b___6 = 108,\n\tmsm_mux_qdss_tracectl_a___7 = 109,\n\tmsm_mux_qdss_tracectl_b___6 = 110,\n\tmsm_mux_qdss_tracedata_a___7 = 111,\n\tmsm_mux_qdss_tracedata_b___6 = 112,\n\tmsm_mux_reset_n = 113,\n\tmsm_mux_sd_card___3 = 114,\n\tmsm_mux_sd_write___3 = 115,\n\tmsm_mux_sec_mi2s = 116,\n\tmsm_mux_smb_int = 117,\n\tmsm_mux_ssbi_wtr0 = 118,\n\tmsm_mux_ssbi_wtr1 = 119,\n\tmsm_mux_uim1 = 120,\n\tmsm_mux_uim2 = 121,\n\tmsm_mux_uim3 = 122,\n\tmsm_mux_uim_batt = 123,\n\tmsm_mux_wcss_bt = 124,\n\tmsm_mux_wcss_fm = 125,\n\tmsm_mux_wcss_wlan = 126,\n\tmsm_mux_webcam1_rst = 127,\n\tmsm_mux_NA___2 = 128,\n};\n\nenum msm8953_functions {\n\tmsm_mux_accel_int = 0,\n\tmsm_mux_adsp_ext___2 = 1,\n\tmsm_mux_alsp_int___2 = 2,\n\tmsm_mux_atest_bbrx0___2 = 3,\n\tmsm_mux_atest_bbrx1___2 = 4,\n\tmsm_mux_atest_char___10 = 5,\n\tmsm_mux_atest_char0___7 = 6,\n\tmsm_mux_atest_char1___7 = 7,\n\tmsm_mux_atest_char2___7 = 8,\n\tmsm_mux_atest_char3___7 = 9,\n\tmsm_mux_atest_gpsadc_dtest0_native = 10,\n\tmsm_mux_atest_gpsadc_dtest1_native = 11,\n\tmsm_mux_atest_tsens___2 = 12,\n\tmsm_mux_atest_wlan0___2 = 13,\n\tmsm_mux_atest_wlan1___2 = 14,\n\tmsm_mux_bimc_dte0___2 = 15,\n\tmsm_mux_bimc_dte1___2 = 16,\n\tmsm_mux_blsp1_spi___4 = 17,\n\tmsm_mux_blsp3_spi___4 = 18,\n\tmsm_mux_blsp6_spi = 19,\n\tmsm_mux_blsp7_spi = 20,\n\tmsm_mux_blsp_i2c1___2 = 21,\n\tmsm_mux_blsp_i2c2___2 = 22,\n\tmsm_mux_blsp_i2c3___2 = 23,\n\tmsm_mux_blsp_i2c4___2 = 24,\n\tmsm_mux_blsp_i2c5___2 = 25,\n\tmsm_mux_blsp_i2c6___2 = 26,\n\tmsm_mux_blsp_i2c7 = 27,\n\tmsm_mux_blsp_i2c8 = 28,\n\tmsm_mux_blsp_spi1___2 = 29,\n\tmsm_mux_blsp_spi2___2 = 30,\n\tmsm_mux_blsp_spi3___2 = 31,\n\tmsm_mux_blsp_spi4___2 = 32,\n\tmsm_mux_blsp_spi5___2 = 33,\n\tmsm_mux_blsp_spi6___2 = 34,\n\tmsm_mux_blsp_spi7 = 35,\n\tmsm_mux_blsp_spi8 = 36,\n\tmsm_mux_blsp_uart2___2 = 37,\n\tmsm_mux_blsp_uart4 = 38,\n\tmsm_mux_blsp_uart5 = 39,\n\tmsm_mux_blsp_uart6 = 40,\n\tmsm_mux_cam0_ldo = 41,\n\tmsm_mux_cam1_ldo = 42,\n\tmsm_mux_cam1_rst___2 = 43,\n\tmsm_mux_cam1_standby___2 = 44,\n\tmsm_mux_cam2_rst = 45,\n\tmsm_mux_cam2_standby = 46,\n\tmsm_mux_cam3_rst = 47,\n\tmsm_mux_cam3_standby = 48,\n\tmsm_mux_cam_irq = 49,\n\tmsm_mux_cam_mclk___3 = 50,\n\tmsm_mux_cap_int = 51,\n\tmsm_mux_cci_async___2 = 52,\n\tmsm_mux_cci_i2c___2 = 53,\n\tmsm_mux_cci_timer0___2 = 54,\n\tmsm_mux_cci_timer1___2 = 55,\n\tmsm_mux_cci_timer2___2 = 56,\n\tmsm_mux_cci_timer3 = 57,\n\tmsm_mux_cci_timer4 = 58,\n\tmsm_mux_cdc_pdm0___2 = 59,\n\tmsm_mux_codec_int1 = 60,\n\tmsm_mux_codec_int2 = 61,\n\tmsm_mux_codec_reset = 62,\n\tmsm_mux_cri_trng___4 = 63,\n\tmsm_mux_cri_trng0___7 = 64,\n\tmsm_mux_cri_trng1___7 = 65,\n\tmsm_mux_dac_calib0 = 66,\n\tmsm_mux_dac_calib1 = 67,\n\tmsm_mux_dac_calib2 = 68,\n\tmsm_mux_dac_calib3 = 69,\n\tmsm_mux_dac_calib4 = 70,\n\tmsm_mux_dac_calib5 = 71,\n\tmsm_mux_dac_calib6 = 72,\n\tmsm_mux_dac_calib7 = 73,\n\tmsm_mux_dac_calib8 = 74,\n\tmsm_mux_dac_calib9 = 75,\n\tmsm_mux_dac_calib10 = 76,\n\tmsm_mux_dac_calib11 = 77,\n\tmsm_mux_dac_calib12 = 78,\n\tmsm_mux_dac_calib13 = 79,\n\tmsm_mux_dac_calib14 = 80,\n\tmsm_mux_dac_calib15 = 81,\n\tmsm_mux_dac_calib16 = 82,\n\tmsm_mux_dac_calib17 = 83,\n\tmsm_mux_dac_calib18 = 84,\n\tmsm_mux_dac_calib19 = 85,\n\tmsm_mux_dac_calib20 = 86,\n\tmsm_mux_dac_calib21 = 87,\n\tmsm_mux_dac_calib22 = 88,\n\tmsm_mux_dac_calib23 = 89,\n\tmsm_mux_dac_calib24 = 90,\n\tmsm_mux_dac_calib25 = 91,\n\tmsm_mux_dbg_out___8 = 92,\n\tmsm_mux_ddr_bist = 93,\n\tmsm_mux_dmic0_clk___2 = 94,\n\tmsm_mux_dmic0_data___2 = 95,\n\tmsm_mux_ebi_cdc = 96,\n\tmsm_mux_ebi_ch0 = 97,\n\tmsm_mux_ext_lpass___2 = 98,\n\tmsm_mux_flash_strobe___2 = 99,\n\tmsm_mux_fp_int = 100,\n\tmsm_mux_gcc_gp1_clk_a___2 = 101,\n\tmsm_mux_gcc_gp1_clk_b___2 = 102,\n\tmsm_mux_gcc_gp2_clk_a___2 = 103,\n\tmsm_mux_gcc_gp2_clk_b___2 = 104,\n\tmsm_mux_gcc_gp3_clk_a___2 = 105,\n\tmsm_mux_gcc_gp3_clk_b___2 = 106,\n\tmsm_mux_gcc_plltest___7 = 107,\n\tmsm_mux_gcc_tlmm___7 = 108,\n\tmsm_mux_gpio___10 = 109,\n\tmsm_mux_gsm0_tx = 110,\n\tmsm_mux_gsm1_tx = 111,\n\tmsm_mux_gyro_int = 112,\n\tmsm_mux_hall_int = 113,\n\tmsm_mux_hdmi_int = 114,\n\tmsm_mux_key_focus = 115,\n\tmsm_mux_key_home = 116,\n\tmsm_mux_key_snapshot = 117,\n\tmsm_mux_key_volp = 118,\n\tmsm_mux_ldo_en___3 = 119,\n\tmsm_mux_ldo_update___3 = 120,\n\tmsm_mux_lpass_slimbus = 121,\n\tmsm_mux_lpass_slimbus0 = 122,\n\tmsm_mux_lpass_slimbus1 = 123,\n\tmsm_mux_m_voc___2 = 124,\n\tmsm_mux_mag_int___2 = 125,\n\tmsm_mux_mdp_vsync___4 = 126,\n\tmsm_mux_mipi_dsi0 = 127,\n\tmsm_mux_modem_tsync___2 = 128,\n\tmsm_mux_mss_lte = 129,\n\tmsm_mux_nav_pps___2 = 130,\n\tmsm_mux_nav_pps_in_a = 131,\n\tmsm_mux_nav_pps_in_b = 132,\n\tmsm_mux_nav_tsync___2 = 133,\n\tmsm_mux_nfc_disable = 134,\n\tmsm_mux_nfc_dwl = 135,\n\tmsm_mux_nfc_irq = 136,\n\tmsm_mux_ois_sync = 137,\n\tmsm_mux_pa_indicator___2 = 138,\n\tmsm_mux_pbs0___2 = 139,\n\tmsm_mux_pbs1___2 = 140,\n\tmsm_mux_pbs2___2 = 141,\n\tmsm_mux_pressure_int = 142,\n\tmsm_mux_pri_mi2s___2 = 143,\n\tmsm_mux_pri_mi2s_mclk_a = 144,\n\tmsm_mux_pri_mi2s_mclk_b = 145,\n\tmsm_mux_pri_mi2s_ws___2 = 146,\n\tmsm_mux_prng_rosc___5 = 147,\n\tmsm_mux_pwr_crypto_enabled_a___2 = 148,\n\tmsm_mux_pwr_crypto_enabled_b___2 = 149,\n\tmsm_mux_pwr_down = 150,\n\tmsm_mux_pwr_modem_enabled_a___2 = 151,\n\tmsm_mux_pwr_modem_enabled_b___2 = 152,\n\tmsm_mux_pwr_nav_enabled_a___2 = 153,\n\tmsm_mux_pwr_nav_enabled_b___2 = 154,\n\tmsm_mux_qdss_cti_trig_in_a0___7 = 155,\n\tmsm_mux_qdss_cti_trig_in_a1___7 = 156,\n\tmsm_mux_qdss_cti_trig_in_b0___7 = 157,\n\tmsm_mux_qdss_cti_trig_in_b1___7 = 158,\n\tmsm_mux_qdss_cti_trig_out_a0___7 = 159,\n\tmsm_mux_qdss_cti_trig_out_a1___7 = 160,\n\tmsm_mux_qdss_cti_trig_out_b0___7 = 161,\n\tmsm_mux_qdss_cti_trig_out_b1___7 = 162,\n\tmsm_mux_qdss_traceclk_a___8 = 163,\n\tmsm_mux_qdss_traceclk_b___7 = 164,\n\tmsm_mux_qdss_tracectl_a___8 = 165,\n\tmsm_mux_qdss_tracectl_b___7 = 166,\n\tmsm_mux_qdss_tracedata_a___8 = 167,\n\tmsm_mux_qdss_tracedata_b___7 = 168,\n\tmsm_mux_sd_write___4 = 169,\n\tmsm_mux_sdcard_det = 170,\n\tmsm_mux_sec_mi2s___2 = 171,\n\tmsm_mux_sec_mi2s_mclk_a = 172,\n\tmsm_mux_sec_mi2s_mclk_b = 173,\n\tmsm_mux_smb_int___2 = 174,\n\tmsm_mux_ss_switch = 175,\n\tmsm_mux_ssbi_wtr1___2 = 176,\n\tmsm_mux_ts_resout = 177,\n\tmsm_mux_ts_sample = 178,\n\tmsm_mux_ts_xvdd = 179,\n\tmsm_mux_tsens_max___6 = 180,\n\tmsm_mux_uim1_clk___2 = 181,\n\tmsm_mux_uim1_data___2 = 182,\n\tmsm_mux_uim1_present___2 = 183,\n\tmsm_mux_uim1_reset___2 = 184,\n\tmsm_mux_uim2_clk = 185,\n\tmsm_mux_uim2_data = 186,\n\tmsm_mux_uim2_present = 187,\n\tmsm_mux_uim2_reset = 188,\n\tmsm_mux_uim_batt___2 = 189,\n\tmsm_mux_us_emitter = 190,\n\tmsm_mux_us_euro = 191,\n\tmsm_mux_wcss_bt___2 = 192,\n\tmsm_mux_wcss_fm___2 = 193,\n\tmsm_mux_wcss_wlan___2 = 194,\n\tmsm_mux_wcss_wlan0 = 195,\n\tmsm_mux_wcss_wlan1 = 196,\n\tmsm_mux_wcss_wlan2 = 197,\n\tmsm_mux_wsa_en = 198,\n\tmsm_mux_wsa_io = 199,\n\tmsm_mux_wsa_irq = 200,\n\tmsm_mux_____8 = 201,\n};\n\nenum msm8976_functions {\n\tmsm_mux_gpio___11 = 0,\n\tmsm_mux_blsp_uart1___2 = 1,\n\tmsm_mux_blsp_spi1___3 = 2,\n\tmsm_mux_smb_int___3 = 3,\n\tmsm_mux_blsp_i2c1___3 = 4,\n\tmsm_mux_blsp_spi2___3 = 5,\n\tmsm_mux_blsp_uart2___3 = 6,\n\tmsm_mux_blsp_i2c2___3 = 7,\n\tmsm_mux_gcc_gp1_clk_b___3 = 8,\n\tmsm_mux_blsp_spi3___3 = 9,\n\tmsm_mux_qdss_tracedata_b___8 = 10,\n\tmsm_mux_blsp_i2c3___3 = 11,\n\tmsm_mux_gcc_gp2_clk_b___3 = 12,\n\tmsm_mux_gcc_gp3_clk_b___3 = 13,\n\tmsm_mux_blsp_spi4___3 = 14,\n\tmsm_mux_cap_int___2 = 15,\n\tmsm_mux_blsp_i2c4___3 = 16,\n\tmsm_mux_blsp_spi5___3 = 17,\n\tmsm_mux_blsp_uart5___2 = 18,\n\tmsm_mux_qdss_traceclk_a___9 = 19,\n\tmsm_mux_m_voc___3 = 20,\n\tmsm_mux_blsp_i2c5___3 = 21,\n\tmsm_mux_qdss_tracectl_a___9 = 22,\n\tmsm_mux_qdss_tracedata_a___9 = 23,\n\tmsm_mux_blsp_spi6___3 = 24,\n\tmsm_mux_blsp_uart6___2 = 25,\n\tmsm_mux_qdss_tracectl_b___8 = 26,\n\tmsm_mux_blsp_i2c6___3 = 27,\n\tmsm_mux_qdss_traceclk_b___8 = 28,\n\tmsm_mux_mdp_vsync___5 = 29,\n\tmsm_mux_pri_mi2s_mclk_a___2 = 30,\n\tmsm_mux_sec_mi2s_mclk_a___2 = 31,\n\tmsm_mux_cam_mclk___4 = 32,\n\tmsm_mux_cci0_i2c = 33,\n\tmsm_mux_cci1_i2c = 34,\n\tmsm_mux_blsp1_spi___5 = 35,\n\tmsm_mux_blsp3_spi___5 = 36,\n\tmsm_mux_gcc_gp1_clk_a___3 = 37,\n\tmsm_mux_gcc_gp2_clk_a___3 = 38,\n\tmsm_mux_gcc_gp3_clk_a___3 = 39,\n\tmsm_mux_uim_batt___3 = 40,\n\tmsm_mux_sd_write___5 = 41,\n\tmsm_mux_uim1_data___3 = 42,\n\tmsm_mux_uim1_clk___3 = 43,\n\tmsm_mux_uim1_reset___3 = 44,\n\tmsm_mux_uim1_present___3 = 45,\n\tmsm_mux_uim2_data___2 = 46,\n\tmsm_mux_uim2_clk___2 = 47,\n\tmsm_mux_uim2_reset___2 = 48,\n\tmsm_mux_uim2_present___2 = 49,\n\tmsm_mux_ts_xvdd___2 = 50,\n\tmsm_mux_mipi_dsi0___2 = 51,\n\tmsm_mux_us_euro___2 = 52,\n\tmsm_mux_ts_resout___2 = 53,\n\tmsm_mux_ts_sample___2 = 54,\n\tmsm_mux_sec_mi2s_mclk_b___2 = 55,\n\tmsm_mux_pri_mi2s___3 = 56,\n\tmsm_mux_codec_reset___2 = 57,\n\tmsm_mux_cdc_pdm0___3 = 58,\n\tmsm_mux_us_emitter___2 = 59,\n\tmsm_mux_pri_mi2s_mclk_b___2 = 60,\n\tmsm_mux_pri_mi2s_mclk_c = 61,\n\tmsm_mux_lpass_slimbus___2 = 62,\n\tmsm_mux_lpass_slimbus0___2 = 63,\n\tmsm_mux_lpass_slimbus1___2 = 64,\n\tmsm_mux_codec_int1___2 = 65,\n\tmsm_mux_codec_int2___2 = 66,\n\tmsm_mux_wcss_bt___3 = 67,\n\tmsm_mux_sdc3 = 68,\n\tmsm_mux_wcss_wlan2___2 = 69,\n\tmsm_mux_wcss_wlan1___2 = 70,\n\tmsm_mux_wcss_wlan0___2 = 71,\n\tmsm_mux_wcss_wlan___3 = 72,\n\tmsm_mux_wcss_fm___3 = 73,\n\tmsm_mux_key_volp___2 = 74,\n\tmsm_mux_key_snapshot___2 = 75,\n\tmsm_mux_key_focus___2 = 76,\n\tmsm_mux_key_home___2 = 77,\n\tmsm_mux_pwr_down___2 = 78,\n\tmsm_mux_dmic0_clk___3 = 79,\n\tmsm_mux_hdmi_int___2 = 80,\n\tmsm_mux_dmic0_data___3 = 81,\n\tmsm_mux_wsa_vi = 82,\n\tmsm_mux_wsa_en___2 = 83,\n\tmsm_mux_blsp_spi8___2 = 84,\n\tmsm_mux_wsa_irq___2 = 85,\n\tmsm_mux_blsp_i2c8___2 = 86,\n\tmsm_mux_pa_indicator___3 = 87,\n\tmsm_mux_modem_tsync___3 = 88,\n\tmsm_mux_ssbi_wtr1___3 = 89,\n\tmsm_mux_gsm1_tx___2 = 90,\n\tmsm_mux_gsm0_tx___2 = 91,\n\tmsm_mux_sdcard_det___2 = 92,\n\tmsm_mux_sec_mi2s___3 = 93,\n\tmsm_mux_ss_switch___2 = 94,\n\tmsm_mux_NA___3 = 95,\n};\n\nenum msm8994_functions {\n\tmsm_mux_audio_ref_clk___3 = 0,\n\tmsm_mux_blsp_i2c1___4 = 1,\n\tmsm_mux_blsp_i2c2___4 = 2,\n\tmsm_mux_blsp_i2c3___4 = 3,\n\tmsm_mux_blsp_i2c4___4 = 4,\n\tmsm_mux_blsp_i2c5___4 = 5,\n\tmsm_mux_blsp_i2c6___4 = 6,\n\tmsm_mux_blsp_i2c7___2 = 7,\n\tmsm_mux_blsp_i2c8___3 = 8,\n\tmsm_mux_blsp_i2c9 = 9,\n\tmsm_mux_blsp_i2c10 = 10,\n\tmsm_mux_blsp_i2c11 = 11,\n\tmsm_mux_blsp_i2c12 = 12,\n\tmsm_mux_blsp_spi1___4 = 13,\n\tmsm_mux_blsp_spi1_cs1___2 = 14,\n\tmsm_mux_blsp_spi1_cs2___2 = 15,\n\tmsm_mux_blsp_spi1_cs3___2 = 16,\n\tmsm_mux_blsp_spi2___4 = 17,\n\tmsm_mux_blsp_spi2_cs1___2 = 18,\n\tmsm_mux_blsp_spi2_cs2___2 = 19,\n\tmsm_mux_blsp_spi2_cs3___2 = 20,\n\tmsm_mux_blsp_spi3___4 = 21,\n\tmsm_mux_blsp_spi4___4 = 22,\n\tmsm_mux_blsp_spi5___4 = 23,\n\tmsm_mux_blsp_spi6___4 = 24,\n\tmsm_mux_blsp_spi7___2 = 25,\n\tmsm_mux_blsp_spi8___3 = 26,\n\tmsm_mux_blsp_spi9 = 27,\n\tmsm_mux_blsp_spi10 = 28,\n\tmsm_mux_blsp_spi10_cs1 = 29,\n\tmsm_mux_blsp_spi10_cs2 = 30,\n\tmsm_mux_blsp_spi10_cs3 = 31,\n\tmsm_mux_blsp_spi11 = 32,\n\tmsm_mux_blsp_spi12 = 33,\n\tmsm_mux_blsp_uart1___3 = 34,\n\tmsm_mux_blsp_uart2___4 = 35,\n\tmsm_mux_blsp_uart3 = 36,\n\tmsm_mux_blsp_uart4___2 = 37,\n\tmsm_mux_blsp_uart5___3 = 38,\n\tmsm_mux_blsp_uart6___3 = 39,\n\tmsm_mux_blsp_uart7 = 40,\n\tmsm_mux_blsp_uart8 = 41,\n\tmsm_mux_blsp_uart9 = 42,\n\tmsm_mux_blsp_uart10 = 43,\n\tmsm_mux_blsp_uart11 = 44,\n\tmsm_mux_blsp_uart12 = 45,\n\tmsm_mux_blsp_uim1___2 = 46,\n\tmsm_mux_blsp_uim2___2 = 47,\n\tmsm_mux_blsp_uim3 = 48,\n\tmsm_mux_blsp_uim4 = 49,\n\tmsm_mux_blsp_uim5 = 50,\n\tmsm_mux_blsp_uim6 = 51,\n\tmsm_mux_blsp_uim7 = 52,\n\tmsm_mux_blsp_uim8 = 53,\n\tmsm_mux_blsp_uim9 = 54,\n\tmsm_mux_blsp_uim10 = 55,\n\tmsm_mux_blsp_uim11 = 56,\n\tmsm_mux_blsp_uim12 = 57,\n\tmsm_mux_blsp11_i2c_scl_b = 58,\n\tmsm_mux_blsp11_i2c_sda_b = 59,\n\tmsm_mux_blsp11_uart_rx_b = 60,\n\tmsm_mux_blsp11_uart_tx_b = 61,\n\tmsm_mux_cam_mclk0___2 = 62,\n\tmsm_mux_cam_mclk1___2 = 63,\n\tmsm_mux_cam_mclk2 = 64,\n\tmsm_mux_cam_mclk3 = 65,\n\tmsm_mux_cci_async_in0___2 = 66,\n\tmsm_mux_cci_async_in1 = 67,\n\tmsm_mux_cci_async_in2 = 68,\n\tmsm_mux_cci_i2c0 = 69,\n\tmsm_mux_cci_i2c1 = 70,\n\tmsm_mux_cci_timer0___3 = 71,\n\tmsm_mux_cci_timer1___3 = 72,\n\tmsm_mux_cci_timer2___3 = 73,\n\tmsm_mux_cci_timer3___2 = 74,\n\tmsm_mux_cci_timer4___2 = 75,\n\tmsm_mux_gcc_gp1_clk_a___4 = 76,\n\tmsm_mux_gcc_gp1_clk_b___4 = 77,\n\tmsm_mux_gcc_gp2_clk_a___4 = 78,\n\tmsm_mux_gcc_gp2_clk_b___4 = 79,\n\tmsm_mux_gcc_gp3_clk_a___4 = 80,\n\tmsm_mux_gcc_gp3_clk_b___4 = 81,\n\tmsm_mux_gp_mn = 82,\n\tmsm_mux_gp_pdm0 = 83,\n\tmsm_mux_gp_pdm1 = 84,\n\tmsm_mux_gp_pdm2 = 85,\n\tmsm_mux_gp0_clk = 86,\n\tmsm_mux_gp1_clk = 87,\n\tmsm_mux_gps_tx = 88,\n\tmsm_mux_gsm_tx = 89,\n\tmsm_mux_hdmi_cec = 90,\n\tmsm_mux_hdmi_ddc = 91,\n\tmsm_mux_hdmi_hpd = 92,\n\tmsm_mux_hdmi_rcv = 93,\n\tmsm_mux_mdp_vsync___6 = 94,\n\tmsm_mux_mss_lte___2 = 95,\n\tmsm_mux_nav_pps___3 = 96,\n\tmsm_mux_nav_tsync___3 = 97,\n\tmsm_mux_qdss_cti_trig_in_a = 98,\n\tmsm_mux_qdss_cti_trig_in_b = 99,\n\tmsm_mux_qdss_cti_trig_in_c = 100,\n\tmsm_mux_qdss_cti_trig_in_d = 101,\n\tmsm_mux_qdss_cti_trig_out_a = 102,\n\tmsm_mux_qdss_cti_trig_out_b = 103,\n\tmsm_mux_qdss_cti_trig_out_c = 104,\n\tmsm_mux_qdss_cti_trig_out_d = 105,\n\tmsm_mux_qdss_traceclk_a___10 = 106,\n\tmsm_mux_qdss_traceclk_b___9 = 107,\n\tmsm_mux_qdss_tracectl_a___10 = 108,\n\tmsm_mux_qdss_tracectl_b___9 = 109,\n\tmsm_mux_qdss_tracedata_a___10 = 110,\n\tmsm_mux_qdss_tracedata_b___9 = 111,\n\tmsm_mux_qua_mi2s = 112,\n\tmsm_mux_pci_e0 = 113,\n\tmsm_mux_pci_e1 = 114,\n\tmsm_mux_pri_mi2s___4 = 115,\n\tmsm_mux_sdc4 = 116,\n\tmsm_mux_sec_mi2s___4 = 117,\n\tmsm_mux_slimbus = 118,\n\tmsm_mux_spkr_i2s = 119,\n\tmsm_mux_ter_mi2s = 120,\n\tmsm_mux_tsif1 = 121,\n\tmsm_mux_tsif2 = 122,\n\tmsm_mux_uim1___2 = 123,\n\tmsm_mux_uim2___2 = 124,\n\tmsm_mux_uim3___2 = 125,\n\tmsm_mux_uim4 = 126,\n\tmsm_mux_uim_batt_alarm = 127,\n\tmsm_mux_gpio___12 = 128,\n\tmsm_mux_NA___4 = 129,\n};\n\nenum msm8996_functions {\n\tmsm_mux_adsp_ext___3 = 0,\n\tmsm_mux_atest_bbrx0___3 = 1,\n\tmsm_mux_atest_bbrx1___3 = 2,\n\tmsm_mux_atest_char___11 = 3,\n\tmsm_mux_atest_char0___8 = 4,\n\tmsm_mux_atest_char1___8 = 5,\n\tmsm_mux_atest_char2___8 = 6,\n\tmsm_mux_atest_char3___8 = 7,\n\tmsm_mux_atest_gpsadc0___2 = 8,\n\tmsm_mux_atest_gpsadc1___2 = 9,\n\tmsm_mux_atest_tsens___3 = 10,\n\tmsm_mux_atest_tsens2 = 11,\n\tmsm_mux_atest_usb1 = 12,\n\tmsm_mux_atest_usb10 = 13,\n\tmsm_mux_atest_usb11 = 14,\n\tmsm_mux_atest_usb12 = 15,\n\tmsm_mux_atest_usb13 = 16,\n\tmsm_mux_atest_usb2 = 17,\n\tmsm_mux_atest_usb20 = 18,\n\tmsm_mux_atest_usb21 = 19,\n\tmsm_mux_atest_usb22 = 20,\n\tmsm_mux_atest_usb23 = 21,\n\tmsm_mux_audio_ref = 22,\n\tmsm_mux_bimc_dte0___3 = 23,\n\tmsm_mux_bimc_dte1___3 = 24,\n\tmsm_mux_blsp10_spi = 25,\n\tmsm_mux_blsp11_i2c_scl_b___2 = 26,\n\tmsm_mux_blsp11_i2c_sda_b___2 = 27,\n\tmsm_mux_blsp11_uart_rx_b___2 = 28,\n\tmsm_mux_blsp11_uart_tx_b___2 = 29,\n\tmsm_mux_blsp1_spi___6 = 30,\n\tmsm_mux_blsp2_spi___6 = 31,\n\tmsm_mux_blsp_i2c1___5 = 32,\n\tmsm_mux_blsp_i2c10___2 = 33,\n\tmsm_mux_blsp_i2c11___2 = 34,\n\tmsm_mux_blsp_i2c12___2 = 35,\n\tmsm_mux_blsp_i2c2___5 = 36,\n\tmsm_mux_blsp_i2c3___5 = 37,\n\tmsm_mux_blsp_i2c4___5 = 38,\n\tmsm_mux_blsp_i2c5___5 = 39,\n\tmsm_mux_blsp_i2c6___5 = 40,\n\tmsm_mux_blsp_i2c7___3 = 41,\n\tmsm_mux_blsp_i2c8___4 = 42,\n\tmsm_mux_blsp_i2c9___2 = 43,\n\tmsm_mux_blsp_spi1___5 = 44,\n\tmsm_mux_blsp_spi10___2 = 45,\n\tmsm_mux_blsp_spi11___2 = 46,\n\tmsm_mux_blsp_spi12___2 = 47,\n\tmsm_mux_blsp_spi2___5 = 48,\n\tmsm_mux_blsp_spi3___5 = 49,\n\tmsm_mux_blsp_spi4___5 = 50,\n\tmsm_mux_blsp_spi5___5 = 51,\n\tmsm_mux_blsp_spi6___5 = 52,\n\tmsm_mux_blsp_spi7___3 = 53,\n\tmsm_mux_blsp_spi8___4 = 54,\n\tmsm_mux_blsp_spi9___2 = 55,\n\tmsm_mux_blsp_uart1___4 = 56,\n\tmsm_mux_blsp_uart10___2 = 57,\n\tmsm_mux_blsp_uart11___2 = 58,\n\tmsm_mux_blsp_uart12___2 = 59,\n\tmsm_mux_blsp_uart2___5 = 60,\n\tmsm_mux_blsp_uart3___2 = 61,\n\tmsm_mux_blsp_uart4___3 = 62,\n\tmsm_mux_blsp_uart5___4 = 63,\n\tmsm_mux_blsp_uart6___4 = 64,\n\tmsm_mux_blsp_uart7___2 = 65,\n\tmsm_mux_blsp_uart8___2 = 66,\n\tmsm_mux_blsp_uart9___2 = 67,\n\tmsm_mux_blsp_uim1___3 = 68,\n\tmsm_mux_blsp_uim10___2 = 69,\n\tmsm_mux_blsp_uim11___2 = 70,\n\tmsm_mux_blsp_uim12___2 = 71,\n\tmsm_mux_blsp_uim2___3 = 72,\n\tmsm_mux_blsp_uim3___2 = 73,\n\tmsm_mux_blsp_uim4___2 = 74,\n\tmsm_mux_blsp_uim5___2 = 75,\n\tmsm_mux_blsp_uim6___2 = 76,\n\tmsm_mux_blsp_uim7___2 = 77,\n\tmsm_mux_blsp_uim8___2 = 78,\n\tmsm_mux_blsp_uim9___2 = 79,\n\tmsm_mux_btfm_slimbus = 80,\n\tmsm_mux_cam_mclk___5 = 81,\n\tmsm_mux_cci_async___3 = 82,\n\tmsm_mux_cci_i2c___3 = 83,\n\tmsm_mux_cci_timer0___4 = 84,\n\tmsm_mux_cci_timer1___4 = 85,\n\tmsm_mux_cci_timer2___4 = 86,\n\tmsm_mux_cci_timer3___3 = 87,\n\tmsm_mux_cci_timer4___3 = 88,\n\tmsm_mux_cri_trng___5 = 89,\n\tmsm_mux_cri_trng0___8 = 90,\n\tmsm_mux_cri_trng1___8 = 91,\n\tmsm_mux_dac_calib0___2 = 92,\n\tmsm_mux_dac_calib1___2 = 93,\n\tmsm_mux_dac_calib10___2 = 94,\n\tmsm_mux_dac_calib11___2 = 95,\n\tmsm_mux_dac_calib12___2 = 96,\n\tmsm_mux_dac_calib13___2 = 97,\n\tmsm_mux_dac_calib14___2 = 98,\n\tmsm_mux_dac_calib15___2 = 99,\n\tmsm_mux_dac_calib16___2 = 100,\n\tmsm_mux_dac_calib17___2 = 101,\n\tmsm_mux_dac_calib18___2 = 102,\n\tmsm_mux_dac_calib19___2 = 103,\n\tmsm_mux_dac_calib2___2 = 104,\n\tmsm_mux_dac_calib20___2 = 105,\n\tmsm_mux_dac_calib21___2 = 106,\n\tmsm_mux_dac_calib22___2 = 107,\n\tmsm_mux_dac_calib23___2 = 108,\n\tmsm_mux_dac_calib24___2 = 109,\n\tmsm_mux_dac_calib25___2 = 110,\n\tmsm_mux_dac_calib26 = 111,\n\tmsm_mux_dac_calib3___2 = 112,\n\tmsm_mux_dac_calib4___2 = 113,\n\tmsm_mux_dac_calib5___2 = 114,\n\tmsm_mux_dac_calib6___2 = 115,\n\tmsm_mux_dac_calib7___2 = 116,\n\tmsm_mux_dac_calib8___2 = 117,\n\tmsm_mux_dac_calib9___2 = 118,\n\tmsm_mux_dac_gpio = 119,\n\tmsm_mux_dbg_out___9 = 120,\n\tmsm_mux_ddr_bist___2 = 121,\n\tmsm_mux_edp_hot = 122,\n\tmsm_mux_edp_lcd = 123,\n\tmsm_mux_gcc_gp1_clk_a___5 = 124,\n\tmsm_mux_gcc_gp1_clk_b___5 = 125,\n\tmsm_mux_gcc_gp2_clk_a___5 = 126,\n\tmsm_mux_gcc_gp2_clk_b___5 = 127,\n\tmsm_mux_gcc_gp3_clk_a___5 = 128,\n\tmsm_mux_gcc_gp3_clk_b___5 = 129,\n\tmsm_mux_gsm_tx___2 = 130,\n\tmsm_mux_hdmi_cec___2 = 131,\n\tmsm_mux_hdmi_ddc___2 = 132,\n\tmsm_mux_hdmi_hot = 133,\n\tmsm_mux_hdmi_rcv___2 = 134,\n\tmsm_mux_isense_dbg = 135,\n\tmsm_mux_ldo_en___4 = 136,\n\tmsm_mux_ldo_update___4 = 137,\n\tmsm_mux_lpass_slimbus___3 = 138,\n\tmsm_mux_m_voc___4 = 139,\n\tmsm_mux_mdp_vsync___7 = 140,\n\tmsm_mux_mdp_vsync_p_b = 141,\n\tmsm_mux_mdp_vsync_s_b = 142,\n\tmsm_mux_modem_tsync___4 = 143,\n\tmsm_mux_mss_lte___3 = 144,\n\tmsm_mux_nav_dr = 145,\n\tmsm_mux_nav_pps___4 = 146,\n\tmsm_mux_pa_indicator___4 = 147,\n\tmsm_mux_pci_e0___2 = 148,\n\tmsm_mux_pci_e1___2 = 149,\n\tmsm_mux_pci_e2 = 150,\n\tmsm_mux_pll_bypassnl = 151,\n\tmsm_mux_pll_reset = 152,\n\tmsm_mux_pri_mi2s___5 = 153,\n\tmsm_mux_prng_rosc___6 = 154,\n\tmsm_mux_pwr_crypto = 155,\n\tmsm_mux_pwr_modem = 156,\n\tmsm_mux_pwr_nav = 157,\n\tmsm_mux_qdss_cti___3 = 158,\n\tmsm_mux_qdss_cti_trig_in_a___2 = 159,\n\tmsm_mux_qdss_cti_trig_in_b___2 = 160,\n\tmsm_mux_qdss_cti_trig_out_a___2 = 161,\n\tmsm_mux_qdss_cti_trig_out_b___2 = 162,\n\tmsm_mux_qdss_stm0 = 163,\n\tmsm_mux_qdss_stm1 = 164,\n\tmsm_mux_qdss_stm10 = 165,\n\tmsm_mux_qdss_stm11 = 166,\n\tmsm_mux_qdss_stm12 = 167,\n\tmsm_mux_qdss_stm13 = 168,\n\tmsm_mux_qdss_stm14 = 169,\n\tmsm_mux_qdss_stm15 = 170,\n\tmsm_mux_qdss_stm16 = 171,\n\tmsm_mux_qdss_stm17 = 172,\n\tmsm_mux_qdss_stm18 = 173,\n\tmsm_mux_qdss_stm19 = 174,\n\tmsm_mux_qdss_stm2 = 175,\n\tmsm_mux_qdss_stm20 = 176,\n\tmsm_mux_qdss_stm21 = 177,\n\tmsm_mux_qdss_stm22 = 178,\n\tmsm_mux_qdss_stm23 = 179,\n\tmsm_mux_qdss_stm24 = 180,\n\tmsm_mux_qdss_stm25 = 181,\n\tmsm_mux_qdss_stm26 = 182,\n\tmsm_mux_qdss_stm27 = 183,\n\tmsm_mux_qdss_stm28 = 184,\n\tmsm_mux_qdss_stm29 = 185,\n\tmsm_mux_qdss_stm3 = 186,\n\tmsm_mux_qdss_stm30 = 187,\n\tmsm_mux_qdss_stm31 = 188,\n\tmsm_mux_qdss_stm4 = 189,\n\tmsm_mux_qdss_stm5 = 190,\n\tmsm_mux_qdss_stm6 = 191,\n\tmsm_mux_qdss_stm7 = 192,\n\tmsm_mux_qdss_stm8 = 193,\n\tmsm_mux_qdss_stm9 = 194,\n\tmsm_mux_qdss_traceclk_a___11 = 195,\n\tmsm_mux_qdss_traceclk_b___10 = 196,\n\tmsm_mux_qdss_tracectl_a___11 = 197,\n\tmsm_mux_qdss_tracectl_b___10 = 198,\n\tmsm_mux_qdss_tracedata_11 = 199,\n\tmsm_mux_qdss_tracedata_12 = 200,\n\tmsm_mux_qdss_tracedata_a___11 = 201,\n\tmsm_mux_qdss_tracedata_b___10 = 202,\n\tmsm_mux_qspi0___3 = 203,\n\tmsm_mux_qspi1___2 = 204,\n\tmsm_mux_qspi2___2 = 205,\n\tmsm_mux_qspi3___2 = 206,\n\tmsm_mux_qspi_clk___6 = 207,\n\tmsm_mux_qspi_cs___6 = 208,\n\tmsm_mux_qua_mi2s___2 = 209,\n\tmsm_mux_sd_card___4 = 210,\n\tmsm_mux_sd_write___6 = 211,\n\tmsm_mux_sdc40___2 = 212,\n\tmsm_mux_sdc41___2 = 213,\n\tmsm_mux_sdc42___2 = 214,\n\tmsm_mux_sdc43___2 = 215,\n\tmsm_mux_sdc4_clk___2 = 216,\n\tmsm_mux_sdc4_cmd___2 = 217,\n\tmsm_mux_sec_mi2s___5 = 218,\n\tmsm_mux_spkr_i2s___2 = 219,\n\tmsm_mux_ssbi1 = 220,\n\tmsm_mux_ssbi2 = 221,\n\tmsm_mux_ssc_irq = 222,\n\tmsm_mux_ter_mi2s___2 = 223,\n\tmsm_mux_tsense_pwm1___3 = 224,\n\tmsm_mux_tsense_pwm2___3 = 225,\n\tmsm_mux_tsif1_clk = 226,\n\tmsm_mux_tsif1_data = 227,\n\tmsm_mux_tsif1_en = 228,\n\tmsm_mux_tsif1_error = 229,\n\tmsm_mux_tsif1_sync = 230,\n\tmsm_mux_tsif2_clk = 231,\n\tmsm_mux_tsif2_data = 232,\n\tmsm_mux_tsif2_en = 233,\n\tmsm_mux_tsif2_error = 234,\n\tmsm_mux_tsif2_sync = 235,\n\tmsm_mux_uim1___3 = 236,\n\tmsm_mux_uim2___3 = 237,\n\tmsm_mux_uim3___3 = 238,\n\tmsm_mux_uim4___2 = 239,\n\tmsm_mux_uim_batt___4 = 240,\n\tmsm_mux_vfr_1___3 = 241,\n\tmsm_mux_gpio___13 = 242,\n\tmsm_mux_NA___5 = 243,\n};\n\nenum msm8998_functions {\n\tmsm_mux_adsp_ext___4 = 0,\n\tmsm_mux_agera_pll = 1,\n\tmsm_mux_atest_char___12 = 2,\n\tmsm_mux_atest_gpsadc0___3 = 3,\n\tmsm_mux_atest_gpsadc1___3 = 4,\n\tmsm_mux_atest_tsens___4 = 5,\n\tmsm_mux_atest_tsens2___2 = 6,\n\tmsm_mux_atest_usb1___2 = 7,\n\tmsm_mux_atest_usb10___2 = 8,\n\tmsm_mux_atest_usb11___2 = 9,\n\tmsm_mux_atest_usb12___2 = 10,\n\tmsm_mux_atest_usb13___2 = 11,\n\tmsm_mux_audio_ref___2 = 12,\n\tmsm_mux_bimc_dte0___4 = 13,\n\tmsm_mux_bimc_dte1___4 = 14,\n\tmsm_mux_blsp10_spi___2 = 15,\n\tmsm_mux_blsp10_spi_a = 16,\n\tmsm_mux_blsp10_spi_b = 17,\n\tmsm_mux_blsp11_i2c = 18,\n\tmsm_mux_blsp1_spi___7 = 19,\n\tmsm_mux_blsp1_spi_a = 20,\n\tmsm_mux_blsp1_spi_b = 21,\n\tmsm_mux_blsp2_spi___7 = 22,\n\tmsm_mux_blsp9_spi = 23,\n\tmsm_mux_blsp_i2c1___6 = 24,\n\tmsm_mux_blsp_i2c10___3 = 25,\n\tmsm_mux_blsp_i2c11___3 = 26,\n\tmsm_mux_blsp_i2c12___3 = 27,\n\tmsm_mux_blsp_i2c2___6 = 28,\n\tmsm_mux_blsp_i2c3___6 = 29,\n\tmsm_mux_blsp_i2c4___6 = 30,\n\tmsm_mux_blsp_i2c5___6 = 31,\n\tmsm_mux_blsp_i2c6___6 = 32,\n\tmsm_mux_blsp_i2c7___4 = 33,\n\tmsm_mux_blsp_i2c8___5 = 34,\n\tmsm_mux_blsp_i2c9___3 = 35,\n\tmsm_mux_blsp_spi1___6 = 36,\n\tmsm_mux_blsp_spi10___3 = 37,\n\tmsm_mux_blsp_spi11___3 = 38,\n\tmsm_mux_blsp_spi12___3 = 39,\n\tmsm_mux_blsp_spi2___6 = 40,\n\tmsm_mux_blsp_spi3___6 = 41,\n\tmsm_mux_blsp_spi4___6 = 42,\n\tmsm_mux_blsp_spi5___6 = 43,\n\tmsm_mux_blsp_spi6___6 = 44,\n\tmsm_mux_blsp_spi7___4 = 45,\n\tmsm_mux_blsp_spi8___5 = 46,\n\tmsm_mux_blsp_spi9___3 = 47,\n\tmsm_mux_blsp_uart1_a = 48,\n\tmsm_mux_blsp_uart1_b = 49,\n\tmsm_mux_blsp_uart2_a = 50,\n\tmsm_mux_blsp_uart2_b = 51,\n\tmsm_mux_blsp_uart3_a = 52,\n\tmsm_mux_blsp_uart3_b = 53,\n\tmsm_mux_blsp_uart7_a = 54,\n\tmsm_mux_blsp_uart7_b = 55,\n\tmsm_mux_blsp_uart8___3 = 56,\n\tmsm_mux_blsp_uart8_a = 57,\n\tmsm_mux_blsp_uart8_b = 58,\n\tmsm_mux_blsp_uart9_a = 59,\n\tmsm_mux_blsp_uart9_b = 60,\n\tmsm_mux_blsp_uim1_a = 61,\n\tmsm_mux_blsp_uim1_b = 62,\n\tmsm_mux_blsp_uim2_a = 63,\n\tmsm_mux_blsp_uim2_b = 64,\n\tmsm_mux_blsp_uim3_a = 65,\n\tmsm_mux_blsp_uim3_b = 66,\n\tmsm_mux_blsp_uim7_a = 67,\n\tmsm_mux_blsp_uim7_b = 68,\n\tmsm_mux_blsp_uim8_a = 69,\n\tmsm_mux_blsp_uim8_b = 70,\n\tmsm_mux_blsp_uim9_a = 71,\n\tmsm_mux_blsp_uim9_b = 72,\n\tmsm_mux_bt_reset = 73,\n\tmsm_mux_btfm_slimbus___2 = 74,\n\tmsm_mux_cam_mclk___6 = 75,\n\tmsm_mux_cci_async___4 = 76,\n\tmsm_mux_cci_i2c___4 = 77,\n\tmsm_mux_cci_timer0___5 = 78,\n\tmsm_mux_cci_timer1___5 = 79,\n\tmsm_mux_cci_timer2___5 = 80,\n\tmsm_mux_cci_timer3___4 = 81,\n\tmsm_mux_cci_timer4___4 = 82,\n\tmsm_mux_cri_trng___6 = 83,\n\tmsm_mux_cri_trng0___9 = 84,\n\tmsm_mux_cri_trng1___9 = 85,\n\tmsm_mux_dbg_out___10 = 86,\n\tmsm_mux_ddr_bist___3 = 87,\n\tmsm_mux_edp_hot___2 = 88,\n\tmsm_mux_edp_lcd___2 = 89,\n\tmsm_mux_gcc_gp1_a = 90,\n\tmsm_mux_gcc_gp1_b = 91,\n\tmsm_mux_gcc_gp2_a = 92,\n\tmsm_mux_gcc_gp2_b = 93,\n\tmsm_mux_gcc_gp3_a = 94,\n\tmsm_mux_gcc_gp3_b = 95,\n\tmsm_mux_gpio___14 = 96,\n\tmsm_mux_hdmi_cec___3 = 97,\n\tmsm_mux_hdmi_ddc___3 = 98,\n\tmsm_mux_hdmi_hot___2 = 99,\n\tmsm_mux_hdmi_rcv___3 = 100,\n\tmsm_mux_isense_dbg___2 = 101,\n\tmsm_mux_jitter_bist___3 = 102,\n\tmsm_mux_ldo_en___5 = 103,\n\tmsm_mux_ldo_update___5 = 104,\n\tmsm_mux_lpass_slimbus___4 = 105,\n\tmsm_mux_m_voc___5 = 106,\n\tmsm_mux_mdp_vsync___8 = 107,\n\tmsm_mux_mdp_vsync0 = 108,\n\tmsm_mux_mdp_vsync1 = 109,\n\tmsm_mux_mdp_vsync2 = 110,\n\tmsm_mux_mdp_vsync3 = 111,\n\tmsm_mux_mdp_vsync_a = 112,\n\tmsm_mux_mdp_vsync_b = 113,\n\tmsm_mux_modem_tsync___5 = 114,\n\tmsm_mux_mss_lte___4 = 115,\n\tmsm_mux_nav_dr___2 = 116,\n\tmsm_mux_nav_pps___5 = 117,\n\tmsm_mux_pa_indicator___5 = 118,\n\tmsm_mux_pci_e0___3 = 119,\n\tmsm_mux_phase_flag___3 = 120,\n\tmsm_mux_pll_bypassnl___2 = 121,\n\tmsm_mux_pll_reset___2 = 122,\n\tmsm_mux_pri_mi2s___6 = 123,\n\tmsm_mux_pri_mi2s_ws___3 = 124,\n\tmsm_mux_prng_rosc___7 = 125,\n\tmsm_mux_pwr_crypto___2 = 126,\n\tmsm_mux_pwr_modem___2 = 127,\n\tmsm_mux_pwr_nav___2 = 128,\n\tmsm_mux_qdss_cti0_a = 129,\n\tmsm_mux_qdss_cti0_b = 130,\n\tmsm_mux_qdss_cti1_a = 131,\n\tmsm_mux_qdss_cti1_b = 132,\n\tmsm_mux_qdss = 133,\n\tmsm_mux_qlink_enable = 134,\n\tmsm_mux_qlink_request = 135,\n\tmsm_mux_qua_mi2s___3 = 136,\n\tmsm_mux_sd_card___5 = 137,\n\tmsm_mux_sd_write___7 = 138,\n\tmsm_mux_sdc40___3 = 139,\n\tmsm_mux_sdc41___3 = 140,\n\tmsm_mux_sdc42___3 = 141,\n\tmsm_mux_sdc43___3 = 142,\n\tmsm_mux_sdc4_clk___3 = 143,\n\tmsm_mux_sdc4_cmd___3 = 144,\n\tmsm_mux_sec_mi2s___6 = 145,\n\tmsm_mux_sp_cmu = 146,\n\tmsm_mux_spkr_i2s___3 = 147,\n\tmsm_mux_ssbi1___2 = 148,\n\tmsm_mux_ssc_irq___2 = 149,\n\tmsm_mux_ter_mi2s___3 = 150,\n\tmsm_mux_tgu_ch0 = 151,\n\tmsm_mux_tgu_ch1 = 152,\n\tmsm_mux_tsense_pwm1___4 = 153,\n\tmsm_mux_tsense_pwm2___4 = 154,\n\tmsm_mux_tsif0 = 155,\n\tmsm_mux_tsif1___2 = 156,\n\tmsm_mux_uim1_clk___4 = 157,\n\tmsm_mux_uim1_data___4 = 158,\n\tmsm_mux_uim1_present___4 = 159,\n\tmsm_mux_uim1_reset___4 = 160,\n\tmsm_mux_uim2_clk___3 = 161,\n\tmsm_mux_uim2_data___3 = 162,\n\tmsm_mux_uim2_present___3 = 163,\n\tmsm_mux_uim2_reset___3 = 164,\n\tmsm_mux_uim_batt___5 = 165,\n\tmsm_mux_usb_phy___2 = 166,\n\tmsm_mux_vfr_1___4 = 167,\n\tmsm_mux_vsense_clkout = 168,\n\tmsm_mux_vsense_data0 = 169,\n\tmsm_mux_vsense_data1 = 170,\n\tmsm_mux_vsense_mode = 171,\n\tmsm_mux_wlan1_adc0 = 172,\n\tmsm_mux_wlan1_adc1 = 173,\n\tmsm_mux_wlan2_adc0 = 174,\n\tmsm_mux_wlan2_adc1 = 175,\n\tmsm_mux_____9 = 176,\n};\n\nenum mt6328_irq_status_numbers {\n\tMT6328_IRQ_STATUS_PWRKEY = 0,\n\tMT6328_IRQ_STATUS_HOMEKEY = 1,\n\tMT6328_IRQ_STATUS_PWRKEY_R = 2,\n\tMT6328_IRQ_STATUS_HOMEKEY_R = 3,\n\tMT6328_IRQ_STATUS_THR_H = 4,\n\tMT6328_IRQ_STATUS_THR_L = 5,\n\tMT6328_IRQ_STATUS_BAT_H = 6,\n\tMT6328_IRQ_STATUS_BAT_L = 7,\n\tMT6328_IRQ_STATUS_RTC = 8,\n\tMT6328_IRQ_STATUS_AUDIO = 9,\n\tMT6328_IRQ_STATUS_ACCDET = 10,\n\tMT6328_IRQ_STATUS_ACCDET_EINT = 11,\n\tMT6328_IRQ_STATUS_ACCDET_NEGV = 12,\n\tMT6328_IRQ_STATUS_NI_LBAT_INT = 13,\n\tMT6328_IRQ_STATUS_VPROC_OC = 16,\n\tMT6328_IRQ_STATUS_VSYS_OC = 17,\n\tMT6328_IRQ_STATUS_VLTE_OC = 18,\n\tMT6328_IRQ_STATUS_VCORE_OC = 19,\n\tMT6328_IRQ_STATUS_VPA_OC = 20,\n\tMT6328_IRQ_STATUS_LDO_OC = 21,\n\tMT6328_IRQ_STATUS_BAT2_H = 22,\n\tMT6328_IRQ_STATUS_BAT2_L = 23,\n\tMT6328_IRQ_STATUS_VISMPS0_H = 24,\n\tMT6328_IRQ_STATUS_VISMPS0_L = 25,\n\tMT6328_IRQ_STATUS_AUXADC_IMP = 26,\n\tMT6328_IRQ_STATUS_OV = 32,\n\tMT6328_IRQ_STATUS_BVALID_DET = 33,\n\tMT6328_IRQ_STATUS_VBATON_HV = 34,\n\tMT6328_IRQ_STATUS_VBATON_UNDET = 35,\n\tMT6328_IRQ_STATUS_WATCHDOG = 36,\n\tMT6328_IRQ_STATUS_PCHR_CM_VDEC = 37,\n\tMT6328_IRQ_STATUS_CHRDET = 38,\n\tMT6328_IRQ_STATUS_PCHR_CM_VINC = 39,\n\tMT6328_IRQ_STATUS_FG_BAT_H = 40,\n\tMT6328_IRQ_STATUS_FG_BAT_L = 41,\n\tMT6328_IRQ_STATUS_FG_CUR_H = 42,\n\tMT6328_IRQ_STATUS_FG_CUR_L = 43,\n\tMT6328_IRQ_STATUS_FG_ZCV = 44,\n\tMT6328_IRQ_STATUS_SPKL_D = 45,\n\tMT6328_IRQ_STATUS_SPKL_AB = 46,\n};\n\nenum mt6331_irq_status_numbers {\n\tMT6331_IRQ_STATUS_PWRKEY = 0,\n\tMT6331_IRQ_STATUS_HOMEKEY = 1,\n\tMT6331_IRQ_STATUS_CHRDET = 2,\n\tMT6331_IRQ_STATUS_THR_H = 3,\n\tMT6331_IRQ_STATUS_THR_L = 4,\n\tMT6331_IRQ_STATUS_BAT_H = 5,\n\tMT6331_IRQ_STATUS_BAT_L = 6,\n\tMT6331_IRQ_STATUS_RTC = 7,\n\tMT6331_IRQ_STATUS_AUDIO = 8,\n\tMT6331_IRQ_STATUS_MAD = 9,\n\tMT6331_IRQ_STATUS_ACCDET = 10,\n\tMT6331_IRQ_STATUS_ACCDET_EINT = 11,\n\tMT6331_IRQ_STATUS_ACCDET_NEGV = 12,\n\tMT6331_IRQ_STATUS_VDVFS11_OC = 16,\n\tMT6331_IRQ_STATUS_VDVFS12_OC = 17,\n\tMT6331_IRQ_STATUS_VDVFS13_OC = 18,\n\tMT6331_IRQ_STATUS_VDVFS14_OC = 19,\n\tMT6331_IRQ_STATUS_GPU_OC = 20,\n\tMT6331_IRQ_STATUS_VCORE1_OC = 21,\n\tMT6331_IRQ_STATUS_VCORE2_OC = 22,\n\tMT6331_IRQ_STATUS_VIO18_OC = 23,\n\tMT6331_IRQ_STATUS_LDO_OC = 24,\n\tMT6331_IRQ_STATUS_NR = 25,\n};\n\nenum mt6357_irq_numbers {\n\tMT6357_IRQ_VPROC_OC = 0,\n\tMT6357_IRQ_VCORE_OC = 1,\n\tMT6357_IRQ_VMODEM_OC = 2,\n\tMT6357_IRQ_VS1_OC = 3,\n\tMT6357_IRQ_VPA_OC = 4,\n\tMT6357_IRQ_VCORE_PREOC = 5,\n\tMT6357_IRQ_VFE28_OC = 16,\n\tMT6357_IRQ_VXO22_OC = 17,\n\tMT6357_IRQ_VRF18_OC = 18,\n\tMT6357_IRQ_VRF12_OC = 19,\n\tMT6357_IRQ_VEFUSE_OC = 20,\n\tMT6357_IRQ_VCN33_OC = 21,\n\tMT6357_IRQ_VCN28_OC = 22,\n\tMT6357_IRQ_VCN18_OC = 23,\n\tMT6357_IRQ_VCAMA_OC = 24,\n\tMT6357_IRQ_VCAMD_OC = 25,\n\tMT6357_IRQ_VCAMIO_OC = 26,\n\tMT6357_IRQ_VLDO28_OC = 27,\n\tMT6357_IRQ_VUSB33_OC = 28,\n\tMT6357_IRQ_VAUX18_OC = 29,\n\tMT6357_IRQ_VAUD28_OC = 30,\n\tMT6357_IRQ_VIO28_OC = 31,\n\tMT6357_IRQ_VIO18_OC = 32,\n\tMT6357_IRQ_VSRAM_PROC_OC = 33,\n\tMT6357_IRQ_VSRAM_OTHERS_OC = 34,\n\tMT6357_IRQ_VIBR_OC = 35,\n\tMT6357_IRQ_VDRAM_OC = 36,\n\tMT6357_IRQ_VMC_OC = 37,\n\tMT6357_IRQ_VMCH_OC = 38,\n\tMT6357_IRQ_VEMC_OC = 39,\n\tMT6357_IRQ_VSIM1_OC = 40,\n\tMT6357_IRQ_VSIM2_OC = 41,\n\tMT6357_IRQ_PWRKEY = 48,\n\tMT6357_IRQ_HOMEKEY = 49,\n\tMT6357_IRQ_PWRKEY_R = 50,\n\tMT6357_IRQ_HOMEKEY_R = 51,\n\tMT6357_IRQ_NI_LBAT_INT = 52,\n\tMT6357_IRQ_CHRDET = 53,\n\tMT6357_IRQ_CHRDET_EDGE = 54,\n\tMT6357_IRQ_VCDT_HV_DET = 55,\n\tMT6357_IRQ_WATCHDOG = 56,\n\tMT6357_IRQ_VBATON_UNDET = 57,\n\tMT6357_IRQ_BVALID_DET = 58,\n\tMT6357_IRQ_OV = 59,\n\tMT6357_IRQ_RTC = 64,\n\tMT6357_IRQ_FG_BAT0_H = 80,\n\tMT6357_IRQ_FG_BAT0_L = 81,\n\tMT6357_IRQ_FG_CUR_H = 82,\n\tMT6357_IRQ_FG_CUR_L = 83,\n\tMT6357_IRQ_FG_ZCV = 84,\n\tMT6357_IRQ_BATON_LV = 96,\n\tMT6357_IRQ_BATON_HT = 97,\n\tMT6357_IRQ_BAT_H = 112,\n\tMT6357_IRQ_BAT_L = 113,\n\tMT6357_IRQ_AUXADC_IMP = 114,\n\tMT6357_IRQ_NAG_C_DLTV = 115,\n\tMT6357_IRQ_AUDIO = 128,\n\tMT6357_IRQ_ACCDET = 133,\n\tMT6357_IRQ_ACCDET_EINT0 = 134,\n\tMT6357_IRQ_ACCDET_EINT1 = 135,\n\tMT6357_IRQ_SPI_CMD_ALERT = 144,\n\tMT6357_IRQ_NR = 145,\n};\n\nenum mt6357_irq_top_status_shift {\n\tMT6357_BUCK_TOP = 0,\n\tMT6357_LDO_TOP = 1,\n\tMT6357_PSC_TOP = 2,\n\tMT6357_SCK_TOP = 3,\n\tMT6357_BM_TOP = 4,\n\tMT6357_HK_TOP = 5,\n\tMT6357_XPP_TOP = 6,\n\tMT6357_AUD_TOP = 7,\n\tMT6357_MISC_TOP = 8,\n};\n\nenum mt6358_irq_numbers {\n\tMT6358_IRQ_VPROC11_OC = 0,\n\tMT6358_IRQ_VPROC12_OC = 1,\n\tMT6358_IRQ_VCORE_OC = 2,\n\tMT6358_IRQ_VGPU_OC = 3,\n\tMT6358_IRQ_VMODEM_OC = 4,\n\tMT6358_IRQ_VDRAM1_OC = 5,\n\tMT6358_IRQ_VS1_OC = 6,\n\tMT6358_IRQ_VS2_OC = 7,\n\tMT6358_IRQ_VPA_OC = 8,\n\tMT6358_IRQ_VCORE_PREOC = 9,\n\tMT6358_IRQ_VFE28_OC = 16,\n\tMT6358_IRQ_VXO22_OC = 17,\n\tMT6358_IRQ_VRF18_OC = 18,\n\tMT6358_IRQ_VRF12_OC = 19,\n\tMT6358_IRQ_VEFUSE_OC = 20,\n\tMT6358_IRQ_VCN33_OC = 21,\n\tMT6358_IRQ_VCN28_OC = 22,\n\tMT6358_IRQ_VCN18_OC = 23,\n\tMT6358_IRQ_VCAMA1_OC = 24,\n\tMT6358_IRQ_VCAMA2_OC = 25,\n\tMT6358_IRQ_VCAMD_OC = 26,\n\tMT6358_IRQ_VCAMIO_OC = 27,\n\tMT6358_IRQ_VLDO28_OC = 28,\n\tMT6358_IRQ_VA12_OC = 29,\n\tMT6358_IRQ_VAUX18_OC = 30,\n\tMT6358_IRQ_VAUD28_OC = 31,\n\tMT6358_IRQ_VIO28_OC = 32,\n\tMT6358_IRQ_VIO18_OC = 33,\n\tMT6358_IRQ_VSRAM_PROC11_OC = 34,\n\tMT6358_IRQ_VSRAM_PROC12_OC = 35,\n\tMT6358_IRQ_VSRAM_OTHERS_OC = 36,\n\tMT6358_IRQ_VSRAM_GPU_OC = 37,\n\tMT6358_IRQ_VDRAM2_OC = 38,\n\tMT6358_IRQ_VMC_OC = 39,\n\tMT6358_IRQ_VMCH_OC = 40,\n\tMT6358_IRQ_VEMC_OC = 41,\n\tMT6358_IRQ_VSIM1_OC = 42,\n\tMT6358_IRQ_VSIM2_OC = 43,\n\tMT6358_IRQ_VIBR_OC = 44,\n\tMT6358_IRQ_VUSB_OC = 45,\n\tMT6358_IRQ_VBIF28_OC = 46,\n\tMT6358_IRQ_PWRKEY = 48,\n\tMT6358_IRQ_HOMEKEY = 49,\n\tMT6358_IRQ_PWRKEY_R = 50,\n\tMT6358_IRQ_HOMEKEY_R = 51,\n\tMT6358_IRQ_NI_LBAT_INT = 52,\n\tMT6358_IRQ_CHRDET = 53,\n\tMT6358_IRQ_CHRDET_EDGE = 54,\n\tMT6358_IRQ_VCDT_HV_DET = 55,\n\tMT6358_IRQ_RTC = 64,\n\tMT6358_IRQ_FG_BAT0_H = 80,\n\tMT6358_IRQ_FG_BAT0_L = 81,\n\tMT6358_IRQ_FG_CUR_H = 82,\n\tMT6358_IRQ_FG_CUR_L = 83,\n\tMT6358_IRQ_FG_ZCV = 84,\n\tMT6358_IRQ_FG_BAT1_H = 85,\n\tMT6358_IRQ_FG_BAT1_L = 86,\n\tMT6358_IRQ_FG_N_CHARGE_L = 87,\n\tMT6358_IRQ_FG_IAVG_H = 88,\n\tMT6358_IRQ_FG_IAVG_L = 89,\n\tMT6358_IRQ_FG_TIME_H = 90,\n\tMT6358_IRQ_FG_DISCHARGE = 91,\n\tMT6358_IRQ_FG_CHARGE = 92,\n\tMT6358_IRQ_BATON_LV = 96,\n\tMT6358_IRQ_BATON_HT = 97,\n\tMT6358_IRQ_BATON_BAT_IN = 98,\n\tMT6358_IRQ_BATON_BAT_OUT = 99,\n\tMT6358_IRQ_BIF = 100,\n\tMT6358_IRQ_BAT_H = 112,\n\tMT6358_IRQ_BAT_L = 113,\n\tMT6358_IRQ_BAT2_H = 114,\n\tMT6358_IRQ_BAT2_L = 115,\n\tMT6358_IRQ_BAT_TEMP_H = 116,\n\tMT6358_IRQ_BAT_TEMP_L = 117,\n\tMT6358_IRQ_AUXADC_IMP = 118,\n\tMT6358_IRQ_NAG_C_DLTV = 119,\n\tMT6358_IRQ_AUDIO = 128,\n\tMT6358_IRQ_ACCDET = 133,\n\tMT6358_IRQ_ACCDET_EINT0 = 134,\n\tMT6358_IRQ_ACCDET_EINT1 = 135,\n\tMT6358_IRQ_SPI_CMD_ALERT = 144,\n\tMT6358_IRQ_NR = 145,\n};\n\nenum mt6358_irq_top_status_shift {\n\tMT6358_BUCK_TOP = 0,\n\tMT6358_LDO_TOP = 1,\n\tMT6358_PSC_TOP = 2,\n\tMT6358_SCK_TOP = 3,\n\tMT6358_BM_TOP = 4,\n\tMT6358_HK_TOP = 5,\n\tMT6358_AUD_TOP = 6,\n\tMT6358_MISC_TOP = 7,\n};\n\nenum mt6359_irq_numbers {\n\tMT6359_IRQ_VCORE_OC = 1,\n\tMT6359_IRQ_VGPU11_OC = 2,\n\tMT6359_IRQ_VGPU12_OC = 3,\n\tMT6359_IRQ_VMODEM_OC = 4,\n\tMT6359_IRQ_VPROC1_OC = 5,\n\tMT6359_IRQ_VPROC2_OC = 6,\n\tMT6359_IRQ_VS1_OC = 7,\n\tMT6359_IRQ_VS2_OC = 8,\n\tMT6359_IRQ_VPA_OC = 9,\n\tMT6359_IRQ_VFE28_OC = 16,\n\tMT6359_IRQ_VXO22_OC = 17,\n\tMT6359_IRQ_VRF18_OC = 18,\n\tMT6359_IRQ_VRF12_OC = 19,\n\tMT6359_IRQ_VEFUSE_OC = 20,\n\tMT6359_IRQ_VCN33_1_OC = 21,\n\tMT6359_IRQ_VCN33_2_OC = 22,\n\tMT6359_IRQ_VCN13_OC = 23,\n\tMT6359_IRQ_VCN18_OC = 24,\n\tMT6359_IRQ_VA09_OC = 25,\n\tMT6359_IRQ_VCAMIO_OC = 26,\n\tMT6359_IRQ_VA12_OC = 27,\n\tMT6359_IRQ_VAUX18_OC = 28,\n\tMT6359_IRQ_VAUD18_OC = 29,\n\tMT6359_IRQ_VIO18_OC = 30,\n\tMT6359_IRQ_VSRAM_PROC1_OC = 31,\n\tMT6359_IRQ_VSRAM_PROC2_OC = 32,\n\tMT6359_IRQ_VSRAM_OTHERS_OC = 33,\n\tMT6359_IRQ_VSRAM_MD_OC = 34,\n\tMT6359_IRQ_VEMC_OC = 35,\n\tMT6359_IRQ_VSIM1_OC = 36,\n\tMT6359_IRQ_VSIM2_OC = 37,\n\tMT6359_IRQ_VUSB_OC = 38,\n\tMT6359_IRQ_VRFCK_OC = 39,\n\tMT6359_IRQ_VBBCK_OC = 40,\n\tMT6359_IRQ_VBIF28_OC = 41,\n\tMT6359_IRQ_VIBR_OC = 42,\n\tMT6359_IRQ_VIO28_OC = 43,\n\tMT6359_IRQ_VM18_OC = 44,\n\tMT6359_IRQ_VUFS_OC = 45,\n\tMT6359_IRQ_PWRKEY = 48,\n\tMT6359_IRQ_HOMEKEY = 49,\n\tMT6359_IRQ_PWRKEY_R = 50,\n\tMT6359_IRQ_HOMEKEY_R = 51,\n\tMT6359_IRQ_NI_LBAT_INT = 52,\n\tMT6359_IRQ_CHRDET_EDGE = 53,\n\tMT6359_IRQ_RTC = 64,\n\tMT6359_IRQ_FG_BAT_H = 80,\n\tMT6359_IRQ_FG_BAT_L = 81,\n\tMT6359_IRQ_FG_CUR_H = 82,\n\tMT6359_IRQ_FG_CUR_L = 83,\n\tMT6359_IRQ_FG_ZCV = 84,\n\tMT6359_IRQ_FG_N_CHARGE_L = 87,\n\tMT6359_IRQ_FG_IAVG_H = 88,\n\tMT6359_IRQ_FG_IAVG_L = 89,\n\tMT6359_IRQ_FG_DISCHARGE = 91,\n\tMT6359_IRQ_FG_CHARGE = 92,\n\tMT6359_IRQ_BATON_LV = 96,\n\tMT6359_IRQ_BATON_BAT_IN = 98,\n\tMT6359_IRQ_BATON_BAT_OU = 99,\n\tMT6359_IRQ_BIF = 100,\n\tMT6359_IRQ_BAT_H = 112,\n\tMT6359_IRQ_BAT_L = 113,\n\tMT6359_IRQ_BAT2_H = 114,\n\tMT6359_IRQ_BAT2_L = 115,\n\tMT6359_IRQ_BAT_TEMP_H = 116,\n\tMT6359_IRQ_BAT_TEMP_L = 117,\n\tMT6359_IRQ_THR_H = 118,\n\tMT6359_IRQ_THR_L = 119,\n\tMT6359_IRQ_AUXADC_IMP = 120,\n\tMT6359_IRQ_NAG_C_DLTV = 121,\n\tMT6359_IRQ_AUDIO = 128,\n\tMT6359_IRQ_ACCDET = 133,\n\tMT6359_IRQ_ACCDET_EINT0 = 134,\n\tMT6359_IRQ_ACCDET_EINT1 = 135,\n\tMT6359_IRQ_SPI_CMD_ALERT = 144,\n\tMT6359_IRQ_NR = 145,\n};\n\nenum mt6359_irq_top_status_shift {\n\tMT6359_BUCK_TOP = 0,\n\tMT6359_LDO_TOP = 1,\n\tMT6359_PSC_TOP = 2,\n\tMT6359_SCK_TOP = 3,\n\tMT6359_BM_TOP = 4,\n\tMT6359_HK_TOP = 5,\n\tMT6359_AUD_TOP = 7,\n\tMT6359_MISC_TOP = 8,\n};\n\nenum mt6397_irq_numbers {\n\tMT6397_IRQ_SPKL_AB = 0,\n\tMT6397_IRQ_SPKR_AB = 1,\n\tMT6397_IRQ_SPKL = 2,\n\tMT6397_IRQ_SPKR = 3,\n\tMT6397_IRQ_BAT_L = 4,\n\tMT6397_IRQ_BAT_H = 5,\n\tMT6397_IRQ_FG_BAT_L = 6,\n\tMT6397_IRQ_FG_BAT_H = 7,\n\tMT6397_IRQ_WATCHDOG = 8,\n\tMT6397_IRQ_PWRKEY = 9,\n\tMT6397_IRQ_THR_L = 10,\n\tMT6397_IRQ_THR_H = 11,\n\tMT6397_IRQ_VBATON_UNDET = 12,\n\tMT6397_IRQ_BVALID_DET = 13,\n\tMT6397_IRQ_CHRDET = 14,\n\tMT6397_IRQ_OV = 15,\n\tMT6397_IRQ_LDO = 16,\n\tMT6397_IRQ_HOMEKEY = 17,\n\tMT6397_IRQ_ACCDET = 18,\n\tMT6397_IRQ_AUDIO = 19,\n\tMT6397_IRQ_RTC = 20,\n\tMT6397_IRQ_PWRKEY_RSTB = 21,\n\tMT6397_IRQ_HDMI_SIFM = 22,\n\tMT6397_IRQ_HDMI_CEC = 23,\n\tMT6397_IRQ_VCA15 = 24,\n\tMT6397_IRQ_VSRMCA15 = 25,\n\tMT6397_IRQ_VCORE = 26,\n\tMT6397_IRQ_VGPU = 27,\n\tMT6397_IRQ_VIO18 = 28,\n\tMT6397_IRQ_VPCA7 = 29,\n\tMT6397_IRQ_VSRMCA7 = 30,\n\tMT6397_IRQ_VDRM = 31,\n\tMT6397_IRQ_NR = 32,\n};\n\nenum mtd_file_modes {\n\tMTD_FILE_MODE_NORMAL = 0,\n\tMTD_FILE_MODE_OTP_FACTORY = 1,\n\tMTD_FILE_MODE_OTP_USER = 2,\n\tMTD_FILE_MODE_RAW = 3,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum mtk_cirq_regoffs_index {\n\tCIRQ_STA = 0,\n\tCIRQ_ACK = 1,\n\tCIRQ_MASK_SET = 2,\n\tCIRQ_MASK_CLR = 3,\n\tCIRQ_SENS_SET = 4,\n\tCIRQ_SENS_CLR = 5,\n\tCIRQ_POL_SET = 6,\n\tCIRQ_POL_CLR = 7,\n\tCIRQ_CONTROL = 8,\n};\n\nenum mtk_iommu_plat {\n\tM4U_MT2712 = 0,\n\tM4U_MT6779 = 1,\n\tM4U_MT6795 = 2,\n\tM4U_MT8167 = 3,\n\tM4U_MT8173 = 4,\n\tM4U_MT8183 = 5,\n\tM4U_MT8186 = 6,\n\tM4U_MT8188 = 7,\n\tM4U_MT8189 = 8,\n\tM4U_MT8192 = 9,\n\tM4U_MT8195 = 10,\n\tM4U_MT8365 = 11,\n};\n\nenum mtk_mfg_ipi_cmd {\n\tCMD_INIT_SHARED_MEM = 0,\n\tCMD_GET_FREQ_BY_IDX = 1,\n\tCMD_GET_POWER_BY_IDX = 2,\n\tCMD_GET_OPPIDX_BY_FREQ = 3,\n\tCMD_GET_LEAKAGE_POWER = 4,\n\tCMD_SET_LIMIT = 5,\n\tCMD_POWER_CONTROL = 6,\n\tCMD_ACTIVE_SLEEP_CONTROL = 7,\n\tCMD_COMMIT = 8,\n\tCMD_DUAL_COMMIT = 9,\n\tCMD_PDCA_CONFIG = 10,\n\tCMD_UPDATE_DEBUG_OPP_INFO = 11,\n\tCMD_SWITCH_LIMIT = 12,\n\tCMD_FIX_TARGET_OPPIDX = 13,\n\tCMD_FIX_DUAL_TARGET_OPPIDX = 14,\n\tCMD_FIX_CUSTOM_FREQ_VOLT = 15,\n\tCMD_FIX_DUAL_CUSTOM_FREQ_VOLT = 16,\n\tCMD_SET_MFGSYS_CONFIG = 17,\n\tCMD_MSSV_COMMIT = 18,\n\tCMD_NUM = 19,\n};\n\nenum mtk_phy_version {\n\tMTK_PHY_V1 = 1,\n\tMTK_PHY_V2 = 2,\n\tMTK_PHY_V3 = 3,\n};\n\nenum mtk_reset_version {\n\tMTK_RST_SIMPLE = 0,\n\tMTK_RST_SET_CLR = 1,\n\tMTK_RST_MAX = 2,\n};\n\nenum mtk_smi_type {\n\tMTK_SMI_GEN1 = 0,\n\tMTK_SMI_GEN2 = 1,\n\tMTK_SMI_GEN2_SUB_COMM = 2,\n};\n\nenum mtk_trans_op {\n\tI2C_MASTER_WR = 1,\n\tI2C_MASTER_RD = 2,\n\tI2C_MASTER_WRRD = 3,\n};\n\nenum mtu3_dr_force_mode {\n\tMTU3_DR_FORCE_NONE = 0,\n\tMTU3_DR_FORCE_HOST = 1,\n\tMTU3_DR_FORCE_DEVICE = 2,\n};\n\nenum mtu3_g_ep0_state {\n\tMU3D_EP0_STATE_SETUP = 1,\n\tMU3D_EP0_STATE_TX = 2,\n\tMU3D_EP0_STATE_RX = 3,\n\tMU3D_EP0_STATE_TX_END = 4,\n\tMU3D_EP0_STATE_STALL = 5,\n};\n\nenum mtu3_speed {\n\tMTU3_SPEED_INACTIVE = 0,\n\tMTU3_SPEED_FULL = 1,\n\tMTU3_SPEED_HIGH = 3,\n\tMTU3_SPEED_SUPER = 4,\n\tMTU3_SPEED_SUPER_PLUS = 5,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum musb_buf_mode {\n\tBUF_SINGLE = 0,\n\tBUF_DOUBLE = 1,\n} __attribute__((mode(byte)));\n\nenum musb_fifo_style {\n\tFIFO_RXTX = 0,\n\tFIFO_TX = 1,\n\tFIFO_RX = 2,\n} __attribute__((mode(byte)));\n\nenum musb_g_ep0_state {\n\tMUSB_EP0_STAGE_IDLE = 0,\n\tMUSB_EP0_STAGE_SETUP = 1,\n\tMUSB_EP0_STAGE_TX = 2,\n\tMUSB_EP0_STAGE_RX = 3,\n\tMUSB_EP0_STAGE_STATUSIN = 4,\n\tMUSB_EP0_STAGE_STATUSOUT = 5,\n\tMUSB_EP0_STAGE_ACKWAIT = 6,\n} __attribute__((mode(byte)));\n\nenum musb_h_ep0_state {\n\tMUSB_EP0_IDLE = 0,\n\tMUSB_EP0_START = 1,\n\tMUSB_EP0_IN = 2,\n\tMUSB_EP0_OUT = 3,\n\tMUSB_EP0_STATUS = 4,\n} __attribute__((mode(byte)));\n\nenum musb_mode {\n\tMUSB_UNDEFINED = 0,\n\tMUSB_HOST = 1,\n\tMUSB_PERIPHERAL = 2,\n\tMUSB_OTG = 3,\n};\n\nenum musb_vbus_id_status {\n\tMUSB_UNKNOWN = 0,\n\tMUSB_ID_GROUND = 1,\n\tMUSB_ID_FLOAT = 2,\n\tMUSB_VBUS_VALID = 3,\n\tMUSB_VBUS_OFF = 4,\n};\n\nenum muxtype {\n\tpca954x_ismux = 0,\n\tpca954x_isswi = 1,\n};\n\nenum mv_xor_mode {\n\tXOR_MODE_IN_REG = 0,\n\tXOR_MODE_IN_DESC = 1,\n};\n\nenum mv_xor_type {\n\tXOR_ORION = 0,\n\tXOR_ARMADA_38X = 1,\n\tXOR_ARMADA_37XX = 2,\n};\n\nenum mvneta_bm_type {\n\tMVNETA_BM_FREE = 0,\n\tMVNETA_BM_LONG = 1,\n\tMVNETA_BM_SHORT = 2,\n};\n\nenum mvneta_tx_buf_type {\n\tMVNETA_TYPE_TSO = 0,\n\tMVNETA_TYPE_SKB = 1,\n\tMVNETA_TYPE_XDP_TX = 2,\n\tMVNETA_TYPE_XDP_NDO = 3,\n};\n\nenum mvpp22_cls_c2_action {\n\tMVPP22_C2_NO_UPD = 0,\n\tMVPP22_C2_NO_UPD_LOCK = 1,\n\tMVPP22_C2_UPD = 2,\n\tMVPP22_C2_UPD_LOCK = 3,\n};\n\nenum mvpp22_cls_c2_color_action {\n\tMVPP22_C2_COL_NO_UPD = 0,\n\tMVPP22_C2_COL_NO_UPD_LOCK = 1,\n\tMVPP22_C2_COL_GREEN = 2,\n\tMVPP22_C2_COL_GREEN_LOCK = 3,\n\tMVPP22_C2_COL_YELLOW = 4,\n\tMVPP22_C2_COL_YELLOW_LOCK = 5,\n\tMVPP22_C2_COL_RED = 6,\n\tMVPP22_C2_COL_RED_LOCK = 7,\n};\n\nenum mvpp22_cls_c2_fwd_action {\n\tMVPP22_C2_FWD_NO_UPD = 0,\n\tMVPP22_C2_FWD_NO_UPD_LOCK = 1,\n\tMVPP22_C2_FWD_SW = 2,\n\tMVPP22_C2_FWD_SW_LOCK = 3,\n\tMVPP22_C2_FWD_HW = 4,\n\tMVPP22_C2_FWD_HW_LOCK = 5,\n\tMVPP22_C2_FWD_HW_LOW_LAT = 6,\n\tMVPP22_C2_FWD_HW_LOW_LAT_LOCK = 7,\n};\n\nenum mvpp22_ptp_action {\n\tMVPP22_PTP_ACTION_NONE = 0,\n\tMVPP22_PTP_ACTION_FORWARD = 1,\n\tMVPP22_PTP_ACTION_CAPTURE = 3,\n\tMVPP22_PTP_ACTION_ADDTIME = 4,\n\tMVPP22_PTP_ACTION_ADDCORRECTEDTIME = 5,\n\tMVPP22_PTP_ACTION_CAPTUREADDTIME = 6,\n\tMVPP22_PTP_ACTION_CAPTUREADDCORRECTEDTIME = 7,\n\tMVPP22_PTP_ACTION_ADDINGRESSTIME = 8,\n\tMVPP22_PTP_ACTION_CAPTUREADDINGRESSTIME = 9,\n\tMVPP22_PTP_ACTION_CAPTUREINGRESSTIME = 10,\n};\n\nenum mvpp22_ptp_packet_format {\n\tMVPP22_PTP_PKT_FMT_PTPV2 = 0,\n\tMVPP22_PTP_PKT_FMT_PTPV1 = 1,\n\tMVPP22_PTP_PKT_FMT_Y1731 = 2,\n\tMVPP22_PTP_PKT_FMT_NTPTS = 3,\n\tMVPP22_PTP_PKT_FMT_NTPRX = 4,\n\tMVPP22_PTP_PKT_FMT_NTPTX = 5,\n\tMVPP22_PTP_PKT_FMT_TWAMP = 6,\n};\n\nenum mvpp2_bm_pool_log_num {\n\tMVPP2_BM_SHORT = 0,\n\tMVPP2_BM_LONG = 1,\n\tMVPP2_BM_JUMBO = 2,\n\tMVPP2_BM_POOLS_NUM = 3,\n};\n\nenum mvpp2_cls_engine {\n\tMVPP22_CLS_ENGINE_C2 = 1,\n\tMVPP22_CLS_ENGINE_C3A = 2,\n\tMVPP22_CLS_ENGINE_C3B = 3,\n\tMVPP22_CLS_ENGINE_C4 = 4,\n\tMVPP22_CLS_ENGINE_C3HA = 6,\n\tMVPP22_CLS_ENGINE_C3HB = 7,\n};\n\nenum mvpp2_cls_field_id {\n\tMVPP22_CLS_FIELD_MAC_DA = 3,\n\tMVPP22_CLS_FIELD_VLAN_PRI = 5,\n\tMVPP22_CLS_FIELD_VLAN = 6,\n\tMVPP22_CLS_FIELD_L3_PROTO = 15,\n\tMVPP22_CLS_FIELD_IP4SA = 16,\n\tMVPP22_CLS_FIELD_IP4DA = 17,\n\tMVPP22_CLS_FIELD_IP6SA = 23,\n\tMVPP22_CLS_FIELD_IP6DA = 26,\n\tMVPP22_CLS_FIELD_L4SIP = 29,\n\tMVPP22_CLS_FIELD_L4DIP = 30,\n};\n\nenum mvpp2_cls_lu_type {\n\tMVPP22_CLS_LU_TYPE_ALL = 63,\n};\n\nenum mvpp2_prs_flow {\n\tMVPP2_FL_START = 8,\n\tMVPP2_FL_IP4_TCP_NF_UNTAG = 8,\n\tMVPP2_FL_IP4_UDP_NF_UNTAG = 9,\n\tMVPP2_FL_IP4_TCP_NF_TAG = 10,\n\tMVPP2_FL_IP4_UDP_NF_TAG = 11,\n\tMVPP2_FL_IP6_TCP_NF_UNTAG = 12,\n\tMVPP2_FL_IP6_UDP_NF_UNTAG = 13,\n\tMVPP2_FL_IP6_TCP_NF_TAG = 14,\n\tMVPP2_FL_IP6_UDP_NF_TAG = 15,\n\tMVPP2_FL_IP4_TCP_FRAG_UNTAG = 16,\n\tMVPP2_FL_IP4_UDP_FRAG_UNTAG = 17,\n\tMVPP2_FL_IP4_TCP_FRAG_TAG = 18,\n\tMVPP2_FL_IP4_UDP_FRAG_TAG = 19,\n\tMVPP2_FL_IP6_TCP_FRAG_UNTAG = 20,\n\tMVPP2_FL_IP6_UDP_FRAG_UNTAG = 21,\n\tMVPP2_FL_IP6_TCP_FRAG_TAG = 22,\n\tMVPP2_FL_IP6_UDP_FRAG_TAG = 23,\n\tMVPP2_FL_IP4_UNTAG = 24,\n\tMVPP2_FL_IP4_TAG = 25,\n\tMVPP2_FL_IP6_UNTAG = 26,\n\tMVPP2_FL_IP6_TAG = 27,\n\tMVPP2_FL_NON_IP_UNTAG = 28,\n\tMVPP2_FL_NON_IP_TAG = 29,\n\tMVPP2_FL_LAST = 30,\n};\n\nenum mvpp2_prs_l2_cast {\n\tMVPP2_PRS_L2_UNI_CAST = 0,\n\tMVPP2_PRS_L2_MULTI_CAST = 1,\n};\n\nenum mvpp2_prs_l3_cast {\n\tMVPP2_PRS_L3_UNI_CAST = 0,\n\tMVPP2_PRS_L3_MULTI_CAST = 1,\n\tMVPP2_PRS_L3_BROAD_CAST = 2,\n};\n\nenum mvpp2_prs_lookup {\n\tMVPP2_PRS_LU_MH = 0,\n\tMVPP2_PRS_LU_MAC = 1,\n\tMVPP2_PRS_LU_DSA = 2,\n\tMVPP2_PRS_LU_VLAN = 3,\n\tMVPP2_PRS_LU_VID = 4,\n\tMVPP2_PRS_LU_L2 = 5,\n\tMVPP2_PRS_LU_PPPOE = 6,\n\tMVPP2_PRS_LU_IP4 = 7,\n\tMVPP2_PRS_LU_IP6 = 8,\n\tMVPP2_PRS_LU_FLOWS = 9,\n\tMVPP2_PRS_LU_LAST = 10,\n};\n\nenum mvpp2_prs_udf {\n\tMVPP2_PRS_UDF_MAC_DEF = 0,\n\tMVPP2_PRS_UDF_MAC_RANGE = 1,\n\tMVPP2_PRS_UDF_L2_DEF = 2,\n\tMVPP2_PRS_UDF_L2_DEF_COPY = 3,\n\tMVPP2_PRS_UDF_L2_USER = 4,\n};\n\nenum mvpp2_tag_type {\n\tMVPP2_TAG_TYPE_NONE = 0,\n\tMVPP2_TAG_TYPE_MH = 1,\n\tMVPP2_TAG_TYPE_DSA = 2,\n\tMVPP2_TAG_TYPE_EDSA = 3,\n\tMVPP2_TAG_TYPE_VLAN = 4,\n\tMVPP2_TAG_TYPE_LAST = 5,\n};\n\nenum mvpp2_tx_buf_type {\n\tMVPP2_TYPE_SKB = 0,\n\tMVPP2_TYPE_XDP_TX = 1,\n\tMVPP2_TYPE_XDP_NDO = 2,\n};\n\nenum nand_bbt_block_status {\n\tNAND_BBT_BLOCK_STATUS_UNKNOWN = 0,\n\tNAND_BBT_BLOCK_GOOD = 1,\n\tNAND_BBT_BLOCK_WORN = 2,\n\tNAND_BBT_BLOCK_RESERVED = 3,\n\tNAND_BBT_BLOCK_FACTORY_BAD = 4,\n\tNAND_BBT_BLOCK_NUM_STATUS = 5,\n};\n\nenum nand_ecc_algo {\n\tNAND_ECC_ALGO_UNKNOWN = 0,\n\tNAND_ECC_ALGO_HAMMING = 1,\n\tNAND_ECC_ALGO_BCH = 2,\n\tNAND_ECC_ALGO_RS = 3,\n};\n\nenum nand_ecc_engine_integration {\n\tNAND_ECC_ENGINE_INTEGRATION_INVALID = 0,\n\tNAND_ECC_ENGINE_INTEGRATION_PIPELINED = 1,\n\tNAND_ECC_ENGINE_INTEGRATION_EXTERNAL = 2,\n};\n\nenum nand_ecc_engine_type {\n\tNAND_ECC_ENGINE_TYPE_INVALID = 0,\n\tNAND_ECC_ENGINE_TYPE_NONE = 1,\n\tNAND_ECC_ENGINE_TYPE_SOFT = 2,\n\tNAND_ECC_ENGINE_TYPE_ON_HOST = 3,\n\tNAND_ECC_ENGINE_TYPE_ON_DIE = 4,\n};\n\nenum nand_ecc_legacy_mode {\n\tNAND_ECC_INVALID = 0,\n\tNAND_ECC_NONE = 1,\n\tNAND_ECC_SOFT = 2,\n\tNAND_ECC_SOFT_BCH = 3,\n\tNAND_ECC_HW = 4,\n\tNAND_ECC_HW_SYNDROME = 5,\n\tNAND_ECC_ON_DIE = 6,\n};\n\nenum nand_ecc_placement {\n\tNAND_ECC_PLACEMENT_UNKNOWN = 0,\n\tNAND_ECC_PLACEMENT_OOB = 1,\n\tNAND_ECC_PLACEMENT_INTERLEAVED = 2,\n};\n\nenum nand_interface_type {\n\tNAND_SDR_IFACE = 0,\n\tNAND_NVDDR_IFACE = 1,\n};\n\nenum nand_op_instr_type {\n\tNAND_OP_CMD_INSTR = 0,\n\tNAND_OP_ADDR_INSTR = 1,\n\tNAND_OP_DATA_IN_INSTR = 2,\n\tNAND_OP_DATA_OUT_INSTR = 3,\n\tNAND_OP_WAITRDY_INSTR = 4,\n};\n\nenum nand_page_io_req_type {\n\tNAND_PAGE_READ = 0,\n\tNAND_PAGE_WRITE = 1,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum net_prot {\n\tNET_PROT_NONE = 0,\n\tNET_PROT_PAYLOAD = 1,\n\tNET_PROT_ETH = 2,\n\tNET_PROT_VLAN = 3,\n\tNET_PROT_IPV4 = 4,\n\tNET_PROT_IPV6 = 5,\n\tNET_PROT_IP = 6,\n\tNET_PROT_TCP = 7,\n\tNET_PROT_UDP = 8,\n\tNET_PROT_UDP_LITE = 9,\n\tNET_PROT_IPHC = 10,\n\tNET_PROT_SCTP = 11,\n\tNET_PROT_SCTP_CHUNK_DATA = 12,\n\tNET_PROT_PPPOE = 13,\n\tNET_PROT_PPP = 14,\n\tNET_PROT_PPPMUX = 15,\n\tNET_PROT_PPPMUX_SUBFRM = 16,\n\tNET_PROT_L2TPV2 = 17,\n\tNET_PROT_L2TPV3_CTRL = 18,\n\tNET_PROT_L2TPV3_SESS = 19,\n\tNET_PROT_LLC = 20,\n\tNET_PROT_LLC_SNAP = 21,\n\tNET_PROT_NLPID = 22,\n\tNET_PROT_SNAP = 23,\n\tNET_PROT_MPLS = 24,\n\tNET_PROT_IPSEC_AH = 25,\n\tNET_PROT_IPSEC_ESP = 26,\n\tNET_PROT_UDP_ENC_ESP = 27,\n\tNET_PROT_MACSEC = 28,\n\tNET_PROT_GRE = 29,\n\tNET_PROT_MINENCAP = 30,\n\tNET_PROT_DCCP = 31,\n\tNET_PROT_ICMP = 32,\n\tNET_PROT_IGMP = 33,\n\tNET_PROT_ARP = 34,\n\tNET_PROT_CAPWAP_DATA = 35,\n\tNET_PROT_CAPWAP_CTRL = 36,\n\tNET_PROT_RFC2684 = 37,\n\tNET_PROT_ICMPV6 = 38,\n\tNET_PROT_FCOE = 39,\n\tNET_PROT_FIP = 40,\n\tNET_PROT_ISCSI = 41,\n\tNET_PROT_GTP = 42,\n\tNET_PROT_USER_DEFINED_L2 = 43,\n\tNET_PROT_USER_DEFINED_L3 = 44,\n\tNET_PROT_USER_DEFINED_L4 = 45,\n\tNET_PROT_USER_DEFINED_L5 = 46,\n\tNET_PROT_USER_DEFINED_SHIM1 = 47,\n\tNET_PROT_USER_DEFINED_SHIM2 = 48,\n\tNET_PROT_DUMMY_LAST = 49,\n};\n\nenum net_xmit_qdisc_t {\n\t__NET_XMIT_STOLEN = 65536,\n\t__NET_XMIT_BYPASS = 131072,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_lag_hash {\n\tNETDEV_LAG_HASH_NONE = 0,\n\tNETDEV_LAG_HASH_L2 = 1,\n\tNETDEV_LAG_HASH_L34 = 2,\n\tNETDEV_LAG_HASH_L23 = 3,\n\tNETDEV_LAG_HASH_E23 = 4,\n\tNETDEV_LAG_HASH_E34 = 5,\n\tNETDEV_LAG_HASH_VLAN_SRCMAC = 6,\n\tNETDEV_LAG_HASH_UNKNOWN = 7,\n};\n\nenum netdev_lag_tx_type {\n\tNETDEV_LAG_TX_TYPE_UNKNOWN = 0,\n\tNETDEV_LAG_TX_TYPE_RANDOM = 1,\n\tNETDEV_LAG_TX_TYPE_BROADCAST = 2,\n\tNETDEV_LAG_TX_TYPE_ROUNDROBIN = 3,\n\tNETDEV_LAG_TX_TYPE_ACTIVEBACKUP = 4,\n\tNETDEV_LAG_TX_TYPE_HASH = 5,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netfs_collect_contig_trace {\n\tnetfs_contig_trace_collect = 0,\n\tnetfs_contig_trace_jump = 1,\n\tnetfs_contig_trace_unlock = 2,\n} __attribute__((mode(byte)));\n\nenum netfs_donate_trace {\n\tnetfs_trace_donate_tail_to_prev = 0,\n\tnetfs_trace_donate_to_prev = 1,\n\tnetfs_trace_donate_to_next = 2,\n\tnetfs_trace_donate_to_deferred_next = 3,\n} __attribute__((mode(byte)));\n\nenum netfs_failure {\n\tnetfs_fail_check_write_begin = 0,\n\tnetfs_fail_copy_to_cache = 1,\n\tnetfs_fail_dio_read_short = 2,\n\tnetfs_fail_dio_read_zero = 3,\n\tnetfs_fail_read = 4,\n\tnetfs_fail_short_read = 5,\n\tnetfs_fail_prepare_write = 6,\n\tnetfs_fail_write = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_folio_trace {\n\tnetfs_folio_is_uptodate = 0,\n\tnetfs_just_prefetch = 1,\n\tnetfs_whole_folio_modify = 2,\n\tnetfs_modify_and_clear = 3,\n\tnetfs_streaming_write = 4,\n\tnetfs_streaming_write_cont = 5,\n\tnetfs_flush_content = 6,\n\tnetfs_streaming_filled_page = 7,\n\tnetfs_streaming_cont_filled_page = 8,\n\tnetfs_folio_trace_abandon = 9,\n\tnetfs_folio_trace_alloc_buffer = 10,\n\tnetfs_folio_trace_cancel_copy = 11,\n\tnetfs_folio_trace_cancel_store = 12,\n\tnetfs_folio_trace_clear = 13,\n\tnetfs_folio_trace_clear_cc = 14,\n\tnetfs_folio_trace_clear_g = 15,\n\tnetfs_folio_trace_clear_s = 16,\n\tnetfs_folio_trace_copy_to_cache = 17,\n\tnetfs_folio_trace_end_copy = 18,\n\tnetfs_folio_trace_filled_gaps = 19,\n\tnetfs_folio_trace_kill = 20,\n\tnetfs_folio_trace_kill_cc = 21,\n\tnetfs_folio_trace_kill_g = 22,\n\tnetfs_folio_trace_kill_s = 23,\n\tnetfs_folio_trace_mkwrite = 24,\n\tnetfs_folio_trace_mkwrite_plus = 25,\n\tnetfs_folio_trace_not_under_wback = 26,\n\tnetfs_folio_trace_not_locked = 27,\n\tnetfs_folio_trace_put = 28,\n\tnetfs_folio_trace_read = 29,\n\tnetfs_folio_trace_read_done = 30,\n\tnetfs_folio_trace_read_gaps = 31,\n\tnetfs_folio_trace_read_unlock = 32,\n\tnetfs_folio_trace_redirtied = 33,\n\tnetfs_folio_trace_store = 34,\n\tnetfs_folio_trace_store_copy = 35,\n\tnetfs_folio_trace_store_plus = 36,\n\tnetfs_folio_trace_wthru = 37,\n\tnetfs_folio_trace_wthru_plus = 38,\n} __attribute__((mode(byte)));\n\nenum netfs_folioq_trace {\n\tnetfs_trace_folioq_alloc_buffer = 0,\n\tnetfs_trace_folioq_clear = 1,\n\tnetfs_trace_folioq_delete = 2,\n\tnetfs_trace_folioq_make_space = 3,\n\tnetfs_trace_folioq_rollbuf_init = 4,\n\tnetfs_trace_folioq_read_progress = 5,\n} __attribute__((mode(byte)));\n\nenum netfs_io_origin {\n\tNETFS_READAHEAD = 0,\n\tNETFS_READPAGE = 1,\n\tNETFS_READ_GAPS = 2,\n\tNETFS_READ_SINGLE = 3,\n\tNETFS_READ_FOR_WRITE = 4,\n\tNETFS_UNBUFFERED_READ = 5,\n\tNETFS_DIO_READ = 6,\n\tNETFS_WRITEBACK = 7,\n\tNETFS_WRITEBACK_SINGLE = 8,\n\tNETFS_WRITETHROUGH = 9,\n\tNETFS_UNBUFFERED_WRITE = 10,\n\tNETFS_DIO_WRITE = 11,\n\tNETFS_PGPRIV2_COPY_TO_CACHE = 12,\n\tnr__netfs_io_origin = 13,\n} __attribute__((mode(byte)));\n\nenum netfs_io_source {\n\tNETFS_SOURCE_UNKNOWN = 0,\n\tNETFS_FILL_WITH_ZEROES = 1,\n\tNETFS_DOWNLOAD_FROM_SERVER = 2,\n\tNETFS_READ_FROM_CACHE = 3,\n\tNETFS_INVALID_READ = 4,\n\tNETFS_UPLOAD_TO_SERVER = 5,\n\tNETFS_WRITE_TO_CACHE = 6,\n} __attribute__((mode(byte)));\n\nenum netfs_read_from_hole {\n\tNETFS_READ_HOLE_IGNORE = 0,\n\tNETFS_READ_HOLE_FAIL = 1,\n};\n\nenum netfs_read_trace {\n\tnetfs_read_trace_dio_read = 0,\n\tnetfs_read_trace_expanded = 1,\n\tnetfs_read_trace_readahead = 2,\n\tnetfs_read_trace_readpage = 3,\n\tnetfs_read_trace_read_gaps = 4,\n\tnetfs_read_trace_read_single = 5,\n\tnetfs_read_trace_prefetch_for_write = 6,\n\tnetfs_read_trace_write_begin = 7,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_ref_trace {\n\tnetfs_rreq_trace_get_for_outstanding = 0,\n\tnetfs_rreq_trace_get_subreq = 1,\n\tnetfs_rreq_trace_put_complete = 2,\n\tnetfs_rreq_trace_put_discard = 3,\n\tnetfs_rreq_trace_put_failed = 4,\n\tnetfs_rreq_trace_put_no_submit = 5,\n\tnetfs_rreq_trace_put_return = 6,\n\tnetfs_rreq_trace_put_subreq = 7,\n\tnetfs_rreq_trace_put_work_ip = 8,\n\tnetfs_rreq_trace_see_work = 9,\n\tnetfs_rreq_trace_see_work_complete = 10,\n\tnetfs_rreq_trace_new = 11,\n} __attribute__((mode(byte)));\n\nenum netfs_rreq_trace {\n\tnetfs_rreq_trace_assess = 0,\n\tnetfs_rreq_trace_collect = 1,\n\tnetfs_rreq_trace_complete = 2,\n\tnetfs_rreq_trace_copy = 3,\n\tnetfs_rreq_trace_dirty = 4,\n\tnetfs_rreq_trace_done = 5,\n\tnetfs_rreq_trace_end_copy_to_cache = 6,\n\tnetfs_rreq_trace_free = 7,\n\tnetfs_rreq_trace_intr = 8,\n\tnetfs_rreq_trace_ki_complete = 9,\n\tnetfs_rreq_trace_recollect = 10,\n\tnetfs_rreq_trace_redirty = 11,\n\tnetfs_rreq_trace_resubmit = 12,\n\tnetfs_rreq_trace_set_abandon = 13,\n\tnetfs_rreq_trace_set_pause = 14,\n\tnetfs_rreq_trace_unlock = 15,\n\tnetfs_rreq_trace_unlock_pgpriv2 = 16,\n\tnetfs_rreq_trace_unmark = 17,\n\tnetfs_rreq_trace_unpause = 18,\n\tnetfs_rreq_trace_wait_ip = 19,\n\tnetfs_rreq_trace_wait_pause = 20,\n\tnetfs_rreq_trace_wait_quiesce = 21,\n\tnetfs_rreq_trace_waited_ip = 22,\n\tnetfs_rreq_trace_waited_pause = 23,\n\tnetfs_rreq_trace_waited_quiesce = 24,\n\tnetfs_rreq_trace_wake_ip = 25,\n\tnetfs_rreq_trace_wake_queue = 26,\n\tnetfs_rreq_trace_write_done = 27,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_ref_trace {\n\tnetfs_sreq_trace_get_copy_to_cache = 0,\n\tnetfs_sreq_trace_get_resubmit = 1,\n\tnetfs_sreq_trace_get_submit = 2,\n\tnetfs_sreq_trace_get_short_read = 3,\n\tnetfs_sreq_trace_new = 4,\n\tnetfs_sreq_trace_put_abandon = 5,\n\tnetfs_sreq_trace_put_cancel = 6,\n\tnetfs_sreq_trace_put_clear = 7,\n\tnetfs_sreq_trace_put_consumed = 8,\n\tnetfs_sreq_trace_put_done = 9,\n\tnetfs_sreq_trace_put_failed = 10,\n\tnetfs_sreq_trace_put_merged = 11,\n\tnetfs_sreq_trace_put_no_copy = 12,\n\tnetfs_sreq_trace_put_oom = 13,\n\tnetfs_sreq_trace_put_wip = 14,\n\tnetfs_sreq_trace_put_work = 15,\n\tnetfs_sreq_trace_put_terminated = 16,\n\tnetfs_sreq_trace_see_failed = 17,\n} __attribute__((mode(byte)));\n\nenum netfs_sreq_trace {\n\tnetfs_sreq_trace_abandoned = 0,\n\tnetfs_sreq_trace_add_donations = 1,\n\tnetfs_sreq_trace_added = 2,\n\tnetfs_sreq_trace_cache_nowrite = 3,\n\tnetfs_sreq_trace_cache_prepare = 4,\n\tnetfs_sreq_trace_cache_write = 5,\n\tnetfs_sreq_trace_cancel = 6,\n\tnetfs_sreq_trace_clear = 7,\n\tnetfs_sreq_trace_consumed = 8,\n\tnetfs_sreq_trace_discard = 9,\n\tnetfs_sreq_trace_donate_to_prev = 10,\n\tnetfs_sreq_trace_donate_to_next = 11,\n\tnetfs_sreq_trace_download_instead = 12,\n\tnetfs_sreq_trace_fail = 13,\n\tnetfs_sreq_trace_free = 14,\n\tnetfs_sreq_trace_hit_eof = 15,\n\tnetfs_sreq_trace_io_bad = 16,\n\tnetfs_sreq_trace_io_malformed = 17,\n\tnetfs_sreq_trace_io_unknown = 18,\n\tnetfs_sreq_trace_io_progress = 19,\n\tnetfs_sreq_trace_io_req_submitted = 20,\n\tnetfs_sreq_trace_io_retry_needed = 21,\n\tnetfs_sreq_trace_limited = 22,\n\tnetfs_sreq_trace_need_clear = 23,\n\tnetfs_sreq_trace_partial_read = 24,\n\tnetfs_sreq_trace_need_retry = 25,\n\tnetfs_sreq_trace_prepare = 26,\n\tnetfs_sreq_trace_prep_failed = 27,\n\tnetfs_sreq_trace_progress = 28,\n\tnetfs_sreq_trace_reprep_failed = 29,\n\tnetfs_sreq_trace_retry = 30,\n\tnetfs_sreq_trace_short = 31,\n\tnetfs_sreq_trace_split = 32,\n\tnetfs_sreq_trace_submit = 33,\n\tnetfs_sreq_trace_superfluous = 34,\n\tnetfs_sreq_trace_terminated = 35,\n\tnetfs_sreq_trace_wait_for = 36,\n\tnetfs_sreq_trace_write = 37,\n\tnetfs_sreq_trace_write_skip = 38,\n\tnetfs_sreq_trace_write_term = 39,\n} __attribute__((mode(byte)));\n\nenum netfs_write_trace {\n\tnetfs_write_trace_copy_to_cache = 0,\n\tnetfs_write_trace_dio_write = 1,\n\tnetfs_write_trace_unbuffered_write = 2,\n\tnetfs_write_trace_writeback = 3,\n\tnetfs_write_trace_writeback_single = 4,\n\tnetfs_write_trace_writethrough = 5,\n} __attribute__((mode(byte)));\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netloc_type4 {\n\tNL4_NAME = 1,\n\tNL4_URL = 2,\n\tNL4_NETADDR = 3,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_ct_ext_id {\n\tNF_CT_EXT_HELPER = 0,\n\tNF_CT_EXT_SEQADJ = 1,\n\tNF_CT_EXT_ACCT = 2,\n\tNF_CT_EXT_ECACHE = 3,\n\tNF_CT_EXT_NUM = 4,\n};\n\nenum nf_dev_hooks {\n\tNF_NETDEV_INGRESS = 0,\n\tNF_NETDEV_EGRESS = 1,\n\tNF_NETDEV_NUMHOOKS = 2,\n};\n\nenum nf_hook_ops_type {\n\tNF_HOOK_OP_UNDEFINED = 0,\n\tNF_HOOK_OP_NF_TABLES = 1,\n\tNF_HOOK_OP_BPF = 2,\n\tNF_HOOK_OP_NFT_FT = 3,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nf_ip_hook_priorities {\n\tNF_IP_PRI_FIRST = -2147483648,\n\tNF_IP_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP_PRI_RAW = -300,\n\tNF_IP_PRI_SELINUX_FIRST = -225,\n\tNF_IP_PRI_CONNTRACK = -200,\n\tNF_IP_PRI_MANGLE = -150,\n\tNF_IP_PRI_NAT_DST = -100,\n\tNF_IP_PRI_FILTER = 0,\n\tNF_IP_PRI_SECURITY = 50,\n\tNF_IP_PRI_NAT_SRC = 100,\n\tNF_IP_PRI_SELINUX_LAST = 225,\n\tNF_IP_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP_PRI_CONNTRACK_CONFIRM = 2147483647,\n\tNF_IP_PRI_LAST = 2147483647,\n};\n\nenum nf_log_type {\n\tNF_LOG_TYPE_LOG = 0,\n\tNF_LOG_TYPE_ULOG = 1,\n\tNF_LOG_TYPE_MAX = 2,\n};\n\nenum nf_nat_manip_type;\n\nenum nfs3_createmode {\n\tNFS3_CREATE_UNCHECKED = 0,\n\tNFS3_CREATE_GUARDED = 1,\n\tNFS3_CREATE_EXCLUSIVE = 2,\n};\n\nenum nfs3_ftype {\n\tNF3NON = 0,\n\tNF3REG = 1,\n\tNF3DIR = 2,\n\tNF3BLK = 3,\n\tNF3CHR = 4,\n\tNF3LNK = 5,\n\tNF3SOCK = 6,\n\tNF3FIFO = 7,\n\tNF3BAD = 8,\n};\n\nenum nfs3_stable_how {\n\tNFS_UNSTABLE = 0,\n\tNFS_DATA_SYNC = 1,\n\tNFS_FILE_SYNC = 2,\n\tNFS_INVALID_STABLE_HOW = -1,\n};\n\nenum nfs4_acl_type {\n\tNFS4ACL_NONE = 0,\n\tNFS4ACL_ACL = 1,\n\tNFS4ACL_DACL = 2,\n\tNFS4ACL_SACL = 3,\n};\n\nenum nfs4_callback_procnum {\n\tCB_NULL = 0,\n\tCB_COMPOUND = 1,\n};\n\nenum nfs4_change_attr_type {\n\tNFS4_CHANGE_TYPE_IS_MONOTONIC_INCR = 0,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER = 1,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER_NOPNFS = 2,\n\tNFS4_CHANGE_TYPE_IS_TIME_METADATA = 3,\n\tNFS4_CHANGE_TYPE_IS_UNDEFINED = 4,\n};\n\nenum nfs4_client_state {\n\tNFS4CLNT_MANAGER_RUNNING = 0,\n\tNFS4CLNT_CHECK_LEASE = 1,\n\tNFS4CLNT_LEASE_EXPIRED = 2,\n\tNFS4CLNT_RECLAIM_REBOOT = 3,\n\tNFS4CLNT_RECLAIM_NOGRACE = 4,\n\tNFS4CLNT_DELEGRETURN = 5,\n\tNFS4CLNT_SESSION_RESET = 6,\n\tNFS4CLNT_LEASE_CONFIRM = 7,\n\tNFS4CLNT_SERVER_SCOPE_MISMATCH = 8,\n\tNFS4CLNT_PURGE_STATE = 9,\n\tNFS4CLNT_BIND_CONN_TO_SESSION = 10,\n\tNFS4CLNT_MOVED = 11,\n\tNFS4CLNT_LEASE_MOVED = 12,\n\tNFS4CLNT_DELEGATION_EXPIRED = 13,\n\tNFS4CLNT_RUN_MANAGER = 14,\n\tNFS4CLNT_MANAGER_AVAILABLE = 15,\n\tNFS4CLNT_RECALL_RUNNING = 16,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_READ = 17,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_RW = 18,\n\tNFS4CLNT_DELEGRETURN_DELAYED = 19,\n};\n\nenum nfs4_ff_op_type {\n\tNFS4_FF_OP_LAYOUTSTATS = 0,\n\tNFS4_FF_OP_LAYOUTRETURN = 1,\n};\n\nenum nfs4_open_delegation_type4 {\n\tNFS4_OPEN_DELEGATE_NONE = 0,\n\tNFS4_OPEN_DELEGATE_READ = 1,\n\tNFS4_OPEN_DELEGATE_WRITE = 2,\n\tNFS4_OPEN_DELEGATE_NONE_EXT = 3,\n\tNFS4_OPEN_DELEGATE_READ_ATTRS_DELEG = 4,\n\tNFS4_OPEN_DELEGATE_WRITE_ATTRS_DELEG = 5,\n};\n\nenum nfs4_session_state {\n\tNFS4_SESSION_INITING = 0,\n\tNFS4_SESSION_ESTABLISHED = 1,\n};\n\nenum nfs4_setxattr_options {\n\tSETXATTR4_EITHER = 0,\n\tSETXATTR4_CREATE = 1,\n\tSETXATTR4_REPLACE = 2,\n};\n\nenum nfs4_slot_tbl_state {\n\tNFS4_SLOT_TBL_DRAINING = 0,\n};\n\nenum nfs_cb_opnum4 {\n\tOP_CB_GETATTR = 3,\n\tOP_CB_RECALL = 4,\n\tOP_CB_LAYOUTRECALL = 5,\n\tOP_CB_NOTIFY = 6,\n\tOP_CB_PUSH_DELEG = 7,\n\tOP_CB_RECALL_ANY = 8,\n\tOP_CB_RECALLABLE_OBJ_AVAIL = 9,\n\tOP_CB_RECALL_SLOT = 10,\n\tOP_CB_SEQUENCE = 11,\n\tOP_CB_WANTS_CANCELLED = 12,\n\tOP_CB_NOTIFY_LOCK = 13,\n\tOP_CB_NOTIFY_DEVICEID = 14,\n\tOP_CB_OFFLOAD = 15,\n\tOP_CB_ILLEGAL = 10044,\n};\n\nenum nfs_ftype4 {\n\tNF4BAD = 0,\n\tNF4REG = 1,\n\tNF4DIR = 2,\n\tNF4BLK = 3,\n\tNF4CHR = 4,\n\tNF4LNK = 5,\n\tNF4SOCK = 6,\n\tNF4FIFO = 7,\n\tNF4ATTRDIR = 8,\n\tNF4NAMEDATTR = 9,\n};\n\nenum nfs_lock_status {\n\tNFS_LOCK_NOT_SET = 0,\n\tNFS_LOCK_LOCK = 1,\n\tNFS_LOCK_NOLOCK = 2,\n};\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nfs_param {\n\tOpt_ac = 0,\n\tOpt_acdirmax = 1,\n\tOpt_acdirmin = 2,\n\tOpt_acl___2 = 3,\n\tOpt_acregmax = 4,\n\tOpt_acregmin = 5,\n\tOpt_actimeo = 6,\n\tOpt_addr = 7,\n\tOpt_bg = 8,\n\tOpt_bsize = 9,\n\tOpt_clientaddr = 10,\n\tOpt_cto = 11,\n\tOpt_alignwrite = 12,\n\tOpt_fatal_neterrors = 13,\n\tOpt_fg = 14,\n\tOpt_fscache = 15,\n\tOpt_fscache_flag = 16,\n\tOpt_hard = 17,\n\tOpt_intr = 18,\n\tOpt_local_lock = 19,\n\tOpt_lock = 20,\n\tOpt_lookupcache = 21,\n\tOpt_migration = 22,\n\tOpt_minorversion = 23,\n\tOpt_mountaddr = 24,\n\tOpt_mounthost = 25,\n\tOpt_mountport = 26,\n\tOpt_mountproto = 27,\n\tOpt_mountvers = 28,\n\tOpt_namelen = 29,\n\tOpt_nconnect = 30,\n\tOpt_max_connect = 31,\n\tOpt_port___2 = 32,\n\tOpt_posix = 33,\n\tOpt_proto = 34,\n\tOpt_rdirplus = 35,\n\tOpt_rdirplus_none = 36,\n\tOpt_rdirplus_force = 37,\n\tOpt_rdma = 38,\n\tOpt_resvport = 39,\n\tOpt_retrans = 40,\n\tOpt_retry = 41,\n\tOpt_rsize = 42,\n\tOpt_sec = 43,\n\tOpt_sharecache = 44,\n\tOpt_sloppy = 45,\n\tOpt_soft = 46,\n\tOpt_softerr = 47,\n\tOpt_softreval = 48,\n\tOpt_source___3 = 49,\n\tOpt_tcp = 50,\n\tOpt_timeo = 51,\n\tOpt_trunkdiscovery = 52,\n\tOpt_udp = 53,\n\tOpt_v = 54,\n\tOpt_vers = 55,\n\tOpt_wsize = 56,\n\tOpt_write = 57,\n\tOpt_xprtsec = 58,\n\tOpt_cert_serial = 59,\n\tOpt_privkey_serial = 60,\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nenum nfs_stat_bytecounters {\n\tNFSIOS_NORMALREADBYTES = 0,\n\tNFSIOS_NORMALWRITTENBYTES = 1,\n\tNFSIOS_DIRECTREADBYTES = 2,\n\tNFSIOS_DIRECTWRITTENBYTES = 3,\n\tNFSIOS_SERVERREADBYTES = 4,\n\tNFSIOS_SERVERWRITTENBYTES = 5,\n\tNFSIOS_READPAGES = 6,\n\tNFSIOS_WRITEPAGES = 7,\n\t__NFSIOS_BYTESMAX = 8,\n};\n\nenum nfs_stat_eventcounters {\n\tNFSIOS_INODEREVALIDATE = 0,\n\tNFSIOS_DENTRYREVALIDATE = 1,\n\tNFSIOS_DATAINVALIDATE = 2,\n\tNFSIOS_ATTRINVALIDATE = 3,\n\tNFSIOS_VFSOPEN = 4,\n\tNFSIOS_VFSLOOKUP = 5,\n\tNFSIOS_VFSACCESS = 6,\n\tNFSIOS_VFSUPDATEPAGE = 7,\n\tNFSIOS_VFSREADPAGE = 8,\n\tNFSIOS_VFSREADPAGES = 9,\n\tNFSIOS_VFSWRITEPAGE = 10,\n\tNFSIOS_VFSWRITEPAGES = 11,\n\tNFSIOS_VFSGETDENTS = 12,\n\tNFSIOS_VFSSETATTR = 13,\n\tNFSIOS_VFSFLUSH = 14,\n\tNFSIOS_VFSFSYNC = 15,\n\tNFSIOS_VFSLOCK = 16,\n\tNFSIOS_VFSRELEASE = 17,\n\tNFSIOS_CONGESTIONWAIT = 18,\n\tNFSIOS_SETATTRTRUNC = 19,\n\tNFSIOS_EXTENDWRITE = 20,\n\tNFSIOS_SILLYRENAME = 21,\n\tNFSIOS_SHORTREAD = 22,\n\tNFSIOS_SHORTWRITE = 23,\n\tNFSIOS_DELAY = 24,\n\tNFSIOS_PNFS_READ = 25,\n\tNFSIOS_PNFS_WRITE = 26,\n\t__NFSIOS_COUNTSMAX = 27,\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n\tNFS4ERR_NOXATTR = 10095,\n\tNFS4ERR_XATTR2BIG = 10096,\n\tNFS4ERR_FIRST_FREE = 10097,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_IOMMU_PAGES = 39,\n\tNR_SWAPCACHE = 40,\n\tPGPROMOTE_SUCCESS = 41,\n\tPGPROMOTE_CANDIDATE = 42,\n\tPGPROMOTE_CANDIDATE_NRL = 43,\n\tPGDEMOTE_KSWAPD = 44,\n\tPGDEMOTE_DIRECT = 45,\n\tPGDEMOTE_KHUGEPAGED = 46,\n\tPGDEMOTE_PROACTIVE = 47,\n\tNR_HUGETLB = 48,\n\tNR_BALLOON_PAGES = 49,\n\tNR_KERNEL_FILE_PAGES = 50,\n\tNR_VM_NODE_STAT_ITEMS = 51,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 2,\n\tN_MEMORY = 3,\n\tN_CPU = 4,\n\tN_GENERIC_INITIATOR = 5,\n\tNR_NODE_STATES = 6,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum numa_faults_stats {\n\tNUMA_MEM = 0,\n\tNUMA_CPU = 1,\n\tNUMA_MEMBUF = 2,\n\tNUMA_CPUBUF = 3,\n};\n\nenum numa_stat_item {\n\tNUMA_HIT = 0,\n\tNUMA_MISS = 1,\n\tNUMA_FOREIGN = 2,\n\tNUMA_INTERLEAVE_HIT = 3,\n\tNUMA_LOCAL = 4,\n\tNUMA_OTHER = 5,\n\tNR_VM_NUMA_EVENT_ITEMS = 6,\n};\n\nenum numa_topology_type {\n\tNUMA_DIRECT = 0,\n\tNUMA_GLUELESS_MESH = 1,\n\tNUMA_BACKPLANE = 2,\n};\n\nenum numa_type {\n\tnode_has_spare = 0,\n\tnode_fully_busy = 1,\n\tnode_overloaded = 2,\n};\n\nenum numa_vmaskip_reason {\n\tNUMAB_SKIP_UNSUITABLE = 0,\n\tNUMAB_SKIP_SHARED_RO = 1,\n\tNUMAB_SKIP_INACCESSIBLE = 2,\n\tNUMAB_SKIP_SCAN_DELAY = 3,\n\tNUMAB_SKIP_PID_INACTIVE = 4,\n\tNUMAB_SKIP_IGNORE_PID = 5,\n\tNUMAB_SKIP_SEQ_COMPLETED = 6,\n};\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n\tNVMEM_TYPE_FRAM = 4,\n};\n\nenum oatc14_hdd_status {\n\tOATC14_HDD_STATUS_CABLE_OK = 0,\n\tOATC14_HDD_STATUS_OPEN = 1,\n\tOATC14_HDD_STATUS_SHORT = 2,\n\tOATC14_HDD_STATUS_NOT_DETECTABLE = 3,\n};\n\nenum objext_flags {\n\tOBJEXTS_ALLOC_FAIL = 1,\n\t__OBJEXTS_FLAG_UNUSED = 4,\n\t__NR_OBJEXTS_FLAGS = 8,\n};\n\nenum ocotp_devtype {\n\tIMX8QXP = 0,\n\tIMX8QM = 1,\n};\n\nenum of_gpio_flags {\n\tOF_GPIO_ACTIVE_LOW = 1,\n\tOF_GPIO_SINGLE_ENDED = 2,\n\tOF_GPIO_OPEN_DRAIN = 4,\n\tOF_GPIO_TRANSITORY = 8,\n\tOF_GPIO_PULL_UP = 16,\n\tOF_GPIO_PULL_DOWN = 32,\n\tOF_GPIO_PULL_DISABLE = 64,\n};\n\nenum of_overlay_notify_action {\n\tOF_OVERLAY_INIT = 0,\n\tOF_OVERLAY_PRE_APPLY = 1,\n\tOF_OVERLAY_POST_APPLY = 2,\n\tOF_OVERLAY_PRE_REMOVE = 3,\n\tOF_OVERLAY_POST_REMOVE = 4,\n};\n\nenum of_reconfig_change {\n\tOF_RECONFIG_NO_CHANGE = 0,\n\tOF_RECONFIG_CHANGE_ADD = 1,\n\tOF_RECONFIG_CHANGE_REMOVE = 2,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum ohci_rh_state {\n\tOHCI_RH_HALTED = 0,\n\tOHCI_RH_SUSPENDED = 1,\n\tOHCI_RH_RUNNING = 2,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum open_claim_type4 {\n\tNFS4_OPEN_CLAIM_NULL = 0,\n\tNFS4_OPEN_CLAIM_PREVIOUS = 1,\n\tNFS4_OPEN_CLAIM_DELEGATE_CUR = 2,\n\tNFS4_OPEN_CLAIM_DELEGATE_PREV = 3,\n\tNFS4_OPEN_CLAIM_FH = 4,\n\tNFS4_OPEN_CLAIM_DELEG_CUR_FH = 5,\n\tNFS4_OPEN_CLAIM_DELEG_PREV_FH = 6,\n};\n\nenum opentype4 {\n\tNFS4_OPEN_NOCREATE = 0,\n\tNFS4_OPEN_CREATE = 1,\n};\n\nenum opp_table_access {\n\tOPP_TABLE_ACCESS_UNKNOWN = 0,\n\tOPP_TABLE_ACCESS_EXCLUSIVE = 1,\n\tOPP_TABLE_ACCESS_SHARED = 2,\n};\n\nenum orion_ehci_phy_ver {\n\tEHCI_PHY_ORION = 0,\n\tEHCI_PHY_DD = 1,\n\tEHCI_PHY_KW = 2,\n\tEHCI_PHY_NA = 3,\n};\n\nenum orion_mdio_bus_type {\n\tBUS_TYPE_SMI = 0,\n\tBUS_TYPE_XSMI = 1,\n};\n\nenum orion_spi_type {\n\tORION_SPI = 0,\n\tARMADA_SPI = 1,\n};\n\nenum ospi_mux_select_type {\n\tPM_OSPI_MUX_SEL_DMA = 0,\n\tPM_OSPI_MUX_SEL_LINEAR = 1,\n};\n\nenum otg_fsm_timer {\n\tA_WAIT_VRISE = 0,\n\tA_WAIT_VFALL = 1,\n\tA_WAIT_BCON = 2,\n\tA_AIDL_BDIS = 3,\n\tB_ASE0_BRST = 4,\n\tA_BIDL_ADIS = 5,\n\tB_AIDL_BDIS = 6,\n\tB_SE0_SRP = 7,\n\tB_SRP_FAIL = 8,\n\tA_WAIT_ENUM = 9,\n\tB_DATA_PLS = 10,\n\tB_SSEND_SRP = 11,\n\tNUM_OTG_FSM_TIMERS = 12,\n};\n\nenum owl_dma_id {\n\tS900_DMA = 0,\n\tS700_DMA = 1,\n};\n\nenum owl_dmadesc_offsets {\n\tOWL_DMADESC_NEXT_LLI = 0,\n\tOWL_DMADESC_SADDR = 1,\n\tOWL_DMADESC_DADDR = 2,\n\tOWL_DMADESC_FLEN = 3,\n\tOWL_DMADESC_SRC_STRIDE = 4,\n\tOWL_DMADESC_DST_STRIDE = 5,\n\tOWL_DMADESC_CTRLA = 6,\n\tOWL_DMADESC_CTRLB = 7,\n\tOWL_DMADESC_CONST_NUM = 8,\n\tOWL_DMADESC_SIZE = 9,\n};\n\nenum owl_pinconf_drv {\n\tOWL_PINCONF_DRV_2MA = 0,\n\tOWL_PINCONF_DRV_4MA = 1,\n\tOWL_PINCONF_DRV_8MA = 2,\n\tOWL_PINCONF_DRV_12MA = 3,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum p9_cache_bits {\n\tCACHE_NONE = 0,\n\tCACHE_FILE = 1,\n\tCACHE_META = 2,\n\tCACHE_WRITEBACK = 4,\n\tCACHE_LOOSE = 8,\n\tCACHE_FSCACHE = 128,\n};\n\nenum p9_cache_shortcuts {\n\tCACHE_SC_NONE = 0,\n\tCACHE_SC_READAHEAD = 1,\n\tCACHE_SC_MMAP = 5,\n\tCACHE_SC_LOOSE = 15,\n\tCACHE_SC_FSCACHE = 143,\n};\n\nenum p9_fid_reftype {\n\tP9_FID_REF_CREATE = 0,\n\tP9_FID_REF_GET = 1,\n\tP9_FID_REF_PUT = 2,\n\tP9_FID_REF_DESTROY = 3,\n} __attribute__((mode(byte)));\n\nenum p9_msg_t {\n\tP9_TLERROR = 6,\n\tP9_RLERROR = 7,\n\tP9_TSTATFS = 8,\n\tP9_RSTATFS = 9,\n\tP9_TLOPEN = 12,\n\tP9_RLOPEN = 13,\n\tP9_TLCREATE = 14,\n\tP9_RLCREATE = 15,\n\tP9_TSYMLINK = 16,\n\tP9_RSYMLINK = 17,\n\tP9_TMKNOD = 18,\n\tP9_RMKNOD = 19,\n\tP9_TRENAME = 20,\n\tP9_RRENAME = 21,\n\tP9_TREADLINK = 22,\n\tP9_RREADLINK = 23,\n\tP9_TGETATTR = 24,\n\tP9_RGETATTR = 25,\n\tP9_TSETATTR = 26,\n\tP9_RSETATTR = 27,\n\tP9_TXATTRWALK = 30,\n\tP9_RXATTRWALK = 31,\n\tP9_TXATTRCREATE = 32,\n\tP9_RXATTRCREATE = 33,\n\tP9_TREADDIR = 40,\n\tP9_RREADDIR = 41,\n\tP9_TFSYNC = 50,\n\tP9_RFSYNC = 51,\n\tP9_TLOCK = 52,\n\tP9_RLOCK = 53,\n\tP9_TGETLOCK = 54,\n\tP9_RGETLOCK = 55,\n\tP9_TLINK = 70,\n\tP9_RLINK = 71,\n\tP9_TMKDIR = 72,\n\tP9_RMKDIR = 73,\n\tP9_TRENAMEAT = 74,\n\tP9_RRENAMEAT = 75,\n\tP9_TUNLINKAT = 76,\n\tP9_RUNLINKAT = 77,\n\tP9_TVERSION = 100,\n\tP9_RVERSION = 101,\n\tP9_TAUTH = 102,\n\tP9_RAUTH = 103,\n\tP9_TATTACH = 104,\n\tP9_RATTACH = 105,\n\tP9_TERROR = 106,\n\tP9_RERROR = 107,\n\tP9_TFLUSH = 108,\n\tP9_RFLUSH = 109,\n\tP9_TWALK = 110,\n\tP9_RWALK = 111,\n\tP9_TOPEN = 112,\n\tP9_ROPEN = 113,\n\tP9_TCREATE = 114,\n\tP9_RCREATE = 115,\n\tP9_TREAD = 116,\n\tP9_RREAD = 117,\n\tP9_TWRITE = 118,\n\tP9_RWRITE = 119,\n\tP9_TCLUNK = 120,\n\tP9_RCLUNK = 121,\n\tP9_TREMOVE = 122,\n\tP9_RREMOVE = 123,\n\tP9_TSTAT = 124,\n\tP9_RSTAT = 125,\n\tP9_TWSTAT = 126,\n\tP9_RWSTAT = 127,\n};\n\nenum p9_open_mode_t {\n\tP9_OREAD = 0,\n\tP9_OWRITE = 1,\n\tP9_ORDWR = 2,\n\tP9_OEXEC = 3,\n\tP9_OTRUNC = 16,\n\tP9_OREXEC = 32,\n\tP9_ORCLOSE = 64,\n\tP9_OAPPEND = 128,\n\tP9_OEXCL = 4096,\n\tP9L_MODE_MASK = 8191,\n\tP9L_DIRECT = 8192,\n\tP9L_NOWRITECACHE = 16384,\n\tP9L_LOOSE = 32768,\n};\n\nenum p9_perm_t {\n\tP9_DMDIR = 2147483648,\n\tP9_DMAPPEND = 1073741824,\n\tP9_DMEXCL = 536870912,\n\tP9_DMMOUNT = 268435456,\n\tP9_DMAUTH = 134217728,\n\tP9_DMTMP = 67108864,\n\tP9_DMSYMLINK = 33554432,\n\tP9_DMLINK = 16777216,\n\tP9_DMDEVICE = 8388608,\n\tP9_DMNAMEDPIPE = 2097152,\n\tP9_DMSOCKET = 1048576,\n\tP9_DMSETUID = 524288,\n\tP9_DMSETGID = 262144,\n\tP9_DMSETVTX = 65536,\n};\n\nenum p9_proto_versions {\n\tp9_proto_legacy = 0,\n\tp9_proto_2000u = 1,\n\tp9_proto_2000L = 2,\n};\n\nenum p9_req_status_t {\n\tREQ_STATUS_ALLOC = 0,\n\tREQ_STATUS_UNSENT = 1,\n\tREQ_STATUS_SENT = 2,\n\tREQ_STATUS_RCVD = 3,\n\tREQ_STATUS_FLSHD = 4,\n\tREQ_STATUS_ERROR = 5,\n};\n\nenum p9_session_flags {\n\tV9FS_PROTO_2000U = 1,\n\tV9FS_PROTO_2000L = 2,\n\tV9FS_ACCESS_SINGLE = 4,\n\tV9FS_ACCESS_USER = 8,\n\tV9FS_ACCESS_CLIENT = 16,\n\tV9FS_POSIX_ACL = 32,\n\tV9FS_NO_XATTR = 64,\n\tV9FS_IGNORE_QV = 128,\n\tV9FS_DIRECT_IO = 256,\n\tV9FS_SYNC = 512,\n};\n\nenum p9_trans_status {\n\tConnected = 0,\n\tBeginDisconnect = 1,\n\tDisconnected = 2,\n\tHung = 3,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum packing_op {\n\tPACK = 0,\n\tUNPACK = 1,\n};\n\nenum pad_func_e {\n\tIMX_SC_PAD_FUNC_SET = 15,\n\tIMX_SC_PAD_FUNC_GET = 16,\n};\n\nenum page_memcg_data_flags {\n\tMEMCG_DATA_OBJEXTS = 1,\n\tMEMCG_DATA_KMEM = 2,\n\t__NR_MEMCG_DATA_FLAGS = 4,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 4096,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\tPB_migrate_isolate = 4,\n\t__NR_PAGEBLOCK_BITS = 5,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\tPG_hwpoison = 21,\n\tPG_arch_2 = 22,\n\tPG_arch_3 = 23,\n\t__NR_PAGEFLAGS = 24,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_vmemmap_self_hosted = 10,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nenum pb_isolate_mode {\n\tPB_ISOLATE_MODE_MEM_OFFLINE = 0,\n\tPB_ISOLATE_MODE_CMA_ALLOC = 1,\n\tPB_ISOLATE_MODE_OTHER = 2,\n};\n\nenum pca9450_chip_type {\n\tPCA9450_TYPE_PCA9450A = 0,\n\tPCA9450_TYPE_PCA9450BC = 1,\n\tPCA9450_TYPE_PCA9451A = 2,\n\tPCA9450_TYPE_PCA9452 = 3,\n\tPCA9450_TYPE_AMOUNT = 4,\n};\n\nenum pca_type {\n\tmax_7356 = 0,\n\tmax_7357 = 1,\n\tmax_7358 = 2,\n\tmax_7367 = 3,\n\tmax_7368 = 4,\n\tmax_7369 = 5,\n\tpca_9540 = 6,\n\tpca_9542 = 7,\n\tpca_9543 = 8,\n\tpca_9544 = 9,\n\tpca_9545 = 10,\n\tpca_9546 = 11,\n\tpca_9547 = 12,\n\tpca_9548 = 13,\n\tpca_9846 = 14,\n\tpca_9847 = 15,\n\tpca_9848 = 16,\n\tpca_9849 = 17,\n};\n\nenum pce_status {\n\tPCE_STATUS_NONE = 0,\n\tPCE_STATUS_ACQUIRED = 1,\n\tPCE_STATUS_PREPARED = 2,\n\tPCE_STATUS_ENABLED = 3,\n\tPCE_STATUS_ERROR = 4,\n};\n\nenum pchg_state {\n\tPCHG_STATE_RESET = 0,\n\tPCHG_STATE_INITIALIZED = 1,\n\tPCHG_STATE_ENABLED = 2,\n\tPCHG_STATE_DETECTED = 3,\n\tPCHG_STATE_CHARGING = 4,\n\tPCHG_STATE_FULL = 5,\n\tPCHG_STATE_DOWNLOAD = 6,\n\tPCHG_STATE_DOWNLOADING = 7,\n\tPCHG_STATE_CONNECTED = 8,\n\tPCHG_STATE_COUNT = 9,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_barno {\n\tNO_BAR = -1,\n\tBAR_0 = 0,\n\tBAR_1 = 1,\n\tBAR_2 = 2,\n\tBAR_3 = 3,\n\tBAR_4 = 4,\n\tBAR_5 = 5,\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_15625000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_oxsemi = 71,\n\tpbn_oxsemi_1_15625000 = 72,\n\tpbn_oxsemi_2_15625000 = 73,\n\tpbn_oxsemi_4_15625000 = 74,\n\tpbn_oxsemi_8_15625000 = 75,\n\tpbn_intel_i960 = 76,\n\tpbn_sgi_ioc3 = 77,\n\tpbn_computone_4 = 78,\n\tpbn_computone_6 = 79,\n\tpbn_computone_8 = 80,\n\tpbn_sbsxrsio = 81,\n\tpbn_pasemi_1682M = 82,\n\tpbn_ni8430_2 = 83,\n\tpbn_ni8430_4 = 84,\n\tpbn_ni8430_8 = 85,\n\tpbn_ni8430_16 = 86,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 87,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 90,\n\tpbn_ce4100_1_115200 = 91,\n\tpbn_omegapci = 92,\n\tpbn_NETMOS9900_2s_115200 = 93,\n\tpbn_brcm_trumanage = 94,\n\tpbn_fintek_4 = 95,\n\tpbn_fintek_8 = 96,\n\tpbn_fintek_12 = 97,\n\tpbn_fintek_F81504A = 98,\n\tpbn_fintek_F81508A = 99,\n\tpbn_fintek_F81512A = 100,\n\tpbn_wch382_2 = 101,\n\tpbn_wch384_4 = 102,\n\tpbn_wch384_8 = 103,\n\tpbn_sunix_pci_1s = 104,\n\tpbn_sunix_pci_2s = 105,\n\tpbn_sunix_pci_4s = 106,\n\tpbn_sunix_pci_8s = 107,\n\tpbn_sunix_pci_16s = 108,\n\tpbn_titan_1_4000000 = 109,\n\tpbn_titan_2_4000000 = 110,\n\tpbn_titan_4_4000000 = 111,\n\tpbn_titan_8_4000000 = 112,\n\tpbn_moxa_2 = 113,\n\tpbn_moxa_4 = 114,\n\tpbn_moxa_8 = 115,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_dev_reg_1 {\n\tPCI_Y2_PIG_ENA = -2147483648,\n\tPCI_Y2_DLL_DIS = 1073741824,\n\tPCI_SW_PWR_ON_RST = 1073741824,\n\tPCI_Y2_PHY2_COMA = 536870912,\n\tPCI_Y2_PHY1_COMA = 268435456,\n\tPCI_Y2_PHY2_POWD = 134217728,\n\tPCI_Y2_PHY1_POWD = 67108864,\n\tPCI_Y2_PME_LEGACY = 32768,\n\tPCI_PHY_LNK_TIM_MSK = 768,\n\tPCI_ENA_L1_EVENT = 128,\n\tPCI_ENA_GPHY_LNK = 64,\n\tPCI_FORCE_PEX_L1 = 32,\n};\n\nenum pci_dev_reg_2 {\n\tPCI_VPD_WR_THR = 4278190080,\n\tPCI_DEV_SEL = 16646144,\n\tPCI_VPD_ROM_SZ = 114688,\n\tPCI_PATCH_DIR = 3840,\n\tPCI_EXT_PATCHS = 240,\n\tPCI_EN_DUMMY_RD = 8,\n\tPCI_REV_DESC = 4,\n\tPCI_USEDATA64 = 1,\n};\n\nenum pci_dev_reg_3 {\n\tP_CLK_ASF_REGS_DIS = 262144,\n\tP_CLK_COR_REGS_D0_DIS = 131072,\n\tP_CLK_MACSEC_DIS = 131072,\n\tP_CLK_PCI_REGS_D0_DIS = 65536,\n\tP_CLK_COR_YTB_ARB_DIS = 32768,\n\tP_CLK_MAC_LNK1_D3_DIS = 16384,\n\tP_CLK_COR_LNK1_D0_DIS = 8192,\n\tP_CLK_MAC_LNK1_D0_DIS = 4096,\n\tP_CLK_COR_LNK1_D3_DIS = 2048,\n\tP_CLK_PCI_MST_ARB_DIS = 1024,\n\tP_CLK_COR_REGS_D3_DIS = 512,\n\tP_CLK_PCI_REGS_D3_DIS = 256,\n\tP_CLK_REF_LNK1_GM_DIS = 128,\n\tP_CLK_COR_LNK1_GM_DIS = 64,\n\tP_CLK_PCI_COMMON_DIS = 32,\n\tP_CLK_COR_COMMON_DIS = 16,\n\tP_CLK_PCI_LNK1_BMU_DIS = 8,\n\tP_CLK_COR_LNK1_BMU_DIS = 4,\n\tP_CLK_PCI_LNK1_BIU_DIS = 2,\n\tP_CLK_COR_LNK1_BIU_DIS = 1,\n\tPCIE_OUR3_WOL_D3_COLD_SET = 406548,\n};\n\nenum pci_dev_reg_4 {\n\tP_PEX_LTSSM_STAT_MSK = 4261412864,\n\tP_PEX_LTSSM_L1_STAT = 52,\n\tP_PEX_LTSSM_DET_STAT = 1,\n\tP_TIMER_VALUE_MSK = 16711680,\n\tP_FORCE_ASPM_REQUEST = 32768,\n\tP_ASPM_GPHY_LINK_DOWN = 16384,\n\tP_ASPM_INT_FIFO_EMPTY = 8192,\n\tP_ASPM_CLKRUN_REQUEST = 4096,\n\tP_ASPM_FORCE_CLKREQ_ENA = 16,\n\tP_ASPM_CLKREQ_PAD_CTL = 8,\n\tP_ASPM_A1_MODE_SELECT = 4,\n\tP_CLK_GATE_PEX_UNIT_ENA = 2,\n\tP_CLK_GATE_ROOT_COR_ENA = 1,\n\tP_ASPM_CONTROL_MSK = 61440,\n};\n\nenum pci_dev_reg_5 {\n\tP_CTL_DIV_CORE_CLK_ENA = -2147483648,\n\tP_CTL_SRESET_VMAIN_AV = 1073741824,\n\tP_CTL_BYPASS_VMAIN_AV = 536870912,\n\tP_CTL_TIM_VMAIN_AV_MSK = 402653184,\n\tP_REL_PCIE_RST_DE_ASS = 67108864,\n\tP_REL_GPHY_REC_PACKET = 33554432,\n\tP_REL_INT_FIFO_N_EMPTY = 16777216,\n\tP_REL_MAIN_PWR_AVAIL = 8388608,\n\tP_REL_CLKRUN_REQ_REL = 4194304,\n\tP_REL_PCIE_RESET_ASS = 2097152,\n\tP_REL_PME_ASSERTED = 1048576,\n\tP_REL_PCIE_EXIT_L1_ST = 524288,\n\tP_REL_LOADER_NOT_FIN = 262144,\n\tP_REL_PCIE_RX_EX_IDLE = 131072,\n\tP_REL_GPHY_LINK_UP = 65536,\n\tP_GAT_PCIE_RST_ASSERTED = 1024,\n\tP_GAT_GPHY_N_REC_PACKET = 512,\n\tP_GAT_INT_FIFO_EMPTY = 256,\n\tP_GAT_MAIN_PWR_N_AVAIL = 128,\n\tP_GAT_CLKRUN_REQ_REL = 64,\n\tP_GAT_PCIE_RESET_ASS = 32,\n\tP_GAT_PME_DE_ASSERTED = 16,\n\tP_GAT_PCIE_ENTER_L1_ST = 8,\n\tP_GAT_LOADER_FINISHED = 4,\n\tP_GAT_PCIE_RX_EL_IDLE = 2,\n\tP_GAT_GPHY_LINK_DOWN = 1,\n\tPCIE_OUR5_EVENT_CLK_D3_SET = 50987786,\n};\n\nenum pci_epc_bar_type {\n\tBAR_PROGRAMMABLE = 0,\n\tBAR_FIXED = 1,\n\tBAR_RESIZABLE = 2,\n\tBAR_RESERVED = 3,\n};\n\nenum pci_epc_interface_type {\n\tUNKNOWN_INTERFACE = -1,\n\tPRIMARY_INTERFACE = 0,\n\tSECONDARY_INTERFACE = 1,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_hotplug_event {\n\tPCI_HOTPLUG_LINK_UP = 0,\n\tPCI_HOTPLUG_LINK_DOWN = 1,\n\tPCI_HOTPLUG_CARD_PRESENT = 2,\n\tPCI_HOTPLUG_CARD_NOT_PRESENT = 3,\n};\n\nenum pci_interrupt_pin {\n\tPCI_INTERRUPT_UNKNOWN = 0,\n\tPCI_INTERRUPT_INTA = 1,\n\tPCI_INTERRUPT_INTB = 2,\n\tPCI_INTERRUPT_INTC = 3,\n\tPCI_INTERRUPT_INTD = 4,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_kirin_phy_type {\n\tPCIE_KIRIN_INTERNAL_PHY = 0,\n\tPCIE_KIRIN_EXTERNAL_PHY = 1,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum pdc_irq_config_bits {\n\tPDC_LEVEL_LOW = 0,\n\tPDC_EDGE_FALLING = 2,\n\tPDC_LEVEL_HIGH = 4,\n\tPDC_EDGE_RISING = 6,\n\tPDC_EDGE_DUAL = 7,\n};\n\nenum pedit_cmd {\n\tTCA_PEDIT_KEY_EX_CMD_SET = 0,\n\tTCA_PEDIT_KEY_EX_CMD_ADD = 1,\n\t__PEDIT_CMD_MAX = 2,\n};\n\nenum pedit_header_type {\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK = 0,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_ETH = 1,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP4 = 2,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP6 = 3,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_TCP = 4,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_UDP = 5,\n\t__PEDIT_HDR_TYPE_MAX = 6,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE = 262144,\n\tPERF_SAMPLE_BRANCH_COUNTERS = 524288,\n\tPERF_SAMPLE_BRANCH_MAX = 1048576,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 18446744073709551584ULL,\n\tPERF_CONTEXT_KERNEL = 18446744073709551488ULL,\n\tPERF_CONTEXT_USER = 18446744073709551104ULL,\n\tPERF_CONTEXT_USER_DEFERRED = 18446744073709550976ULL,\n\tPERF_CONTEXT_GUEST = 18446744073709549568ULL,\n\tPERF_CONTEXT_GUEST_KERNEL = 18446744073709549440ULL,\n\tPERF_CONTEXT_GUEST_USER = 18446744073709549056ULL,\n\tPERF_CONTEXT_MAX = 18446744073709547521ULL,\n};\n\nenum perf_event_arm_regs {\n\tPERF_REG_ARM64_X0 = 0,\n\tPERF_REG_ARM64_X1 = 1,\n\tPERF_REG_ARM64_X2 = 2,\n\tPERF_REG_ARM64_X3 = 3,\n\tPERF_REG_ARM64_X4 = 4,\n\tPERF_REG_ARM64_X5 = 5,\n\tPERF_REG_ARM64_X6 = 6,\n\tPERF_REG_ARM64_X7 = 7,\n\tPERF_REG_ARM64_X8 = 8,\n\tPERF_REG_ARM64_X9 = 9,\n\tPERF_REG_ARM64_X10 = 10,\n\tPERF_REG_ARM64_X11 = 11,\n\tPERF_REG_ARM64_X12 = 12,\n\tPERF_REG_ARM64_X13 = 13,\n\tPERF_REG_ARM64_X14 = 14,\n\tPERF_REG_ARM64_X15 = 15,\n\tPERF_REG_ARM64_X16 = 16,\n\tPERF_REG_ARM64_X17 = 17,\n\tPERF_REG_ARM64_X18 = 18,\n\tPERF_REG_ARM64_X19 = 19,\n\tPERF_REG_ARM64_X20 = 20,\n\tPERF_REG_ARM64_X21 = 21,\n\tPERF_REG_ARM64_X22 = 22,\n\tPERF_REG_ARM64_X23 = 23,\n\tPERF_REG_ARM64_X24 = 24,\n\tPERF_REG_ARM64_X25 = 25,\n\tPERF_REG_ARM64_X26 = 26,\n\tPERF_REG_ARM64_X27 = 27,\n\tPERF_REG_ARM64_X28 = 28,\n\tPERF_REG_ARM64_X29 = 29,\n\tPERF_REG_ARM64_LR = 30,\n\tPERF_REG_ARM64_SP = 31,\n\tPERF_REG_ARM64_PC = 32,\n\tPERF_REG_ARM64_MAX = 33,\n\tPERF_REG_ARM64_VG = 46,\n\tPERF_REG_ARM64_EXTENDED_MAX = 47,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_LOST = 16,\n\tPERF_FORMAT_MAX = 32,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_DATA_PAGE_SIZE = 4194304,\n\tPERF_SAMPLE_CODE_PAGE_SIZE = 8388608,\n\tPERF_SAMPLE_WEIGHT_STRUCT = 16777216,\n\tPERF_SAMPLE_MAX = 33554432,\n};\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = -5,\n\tPERF_EVENT_STATE_REVOKED = -4,\n\tPERF_EVENT_STATE_EXIT = -3,\n\tPERF_EVENT_STATE_ERROR = -2,\n\tPERF_EVENT_STATE_OFF = -1,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = -1,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_TEXT_POKE = 20,\n\tPERF_RECORD_AUX_OUTPUT_HW_ID = 21,\n\tPERF_RECORD_CALLCHAIN_DEFERRED = 22,\n\tPERF_RECORD_MAX = 23,\n};\n\nenum perf_hw_cache_id {\n\tPERF_COUNT_HW_CACHE_L1D = 0,\n\tPERF_COUNT_HW_CACHE_L1I = 1,\n\tPERF_COUNT_HW_CACHE_LL = 2,\n\tPERF_COUNT_HW_CACHE_DTLB = 3,\n\tPERF_COUNT_HW_CACHE_ITLB = 4,\n\tPERF_COUNT_HW_CACHE_BPU = 5,\n\tPERF_COUNT_HW_CACHE_NODE = 6,\n\tPERF_COUNT_HW_CACHE_MAX = 7,\n};\n\nenum perf_hw_cache_op_id {\n\tPERF_COUNT_HW_CACHE_OP_READ = 0,\n\tPERF_COUNT_HW_CACHE_OP_WRITE = 1,\n\tPERF_COUNT_HW_CACHE_OP_PREFETCH = 2,\n\tPERF_COUNT_HW_CACHE_OP_MAX = 3,\n};\n\nenum perf_hw_cache_op_result_id {\n\tPERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,\n\tPERF_COUNT_HW_CACHE_RESULT_MISS = 1,\n\tPERF_COUNT_HW_CACHE_RESULT_MAX = 2,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_pmu_scope {\n\tPERF_PMU_SCOPE_NONE = 0,\n\tPERF_PMU_SCOPE_CORE = 1,\n\tPERF_PMU_SCOPE_DIE = 2,\n\tPERF_PMU_SCOPE_CLUSTER = 3,\n\tPERF_PMU_SCOPE_PKG = 4,\n\tPERF_PMU_SCOPE_SYS_WIDE = 5,\n\tPERF_PMU_MAX_SCOPE = 6,\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum pf8x00_buck_states {\n\tSW_CONFIG1 = 0,\n\tSW_CONFIG2 = 1,\n\tSW_PWRUP = 2,\n\tSW_MODE1 = 3,\n\tSW_RUN_VOLT = 4,\n\tSW_STBY_VOLT = 5,\n};\n\nenum pf8x00_devid {\n\tPF8100 = 0,\n\tPF8121A = 2,\n\tPF8200 = 8,\n};\n\nenum pf8x00_ldo_states {\n\tLDO_CONFIG1 = 0,\n\tLDO_CONFIG2 = 1,\n\tLDO_PWRUP = 2,\n\tLDO_RUN_VOLT = 3,\n\tLDO_STBY_VOLT = 4,\n};\n\nenum pf8x00_regulators {\n\tPF8X00_LDO1 = 0,\n\tPF8X00_LDO2 = 1,\n\tPF8X00_LDO3 = 2,\n\tPF8X00_LDO4 = 3,\n\tPF8X00_BUCK1 = 4,\n\tPF8X00_BUCK2 = 5,\n\tPF8X00_BUCK3 = 6,\n\tPF8X00_BUCK4 = 7,\n\tPF8X00_BUCK5 = 8,\n\tPF8X00_BUCK6 = 9,\n\tPF8X00_BUCK7 = 10,\n\tPF8X00_VSNVS = 11,\n\tPF8X00_MAX_REGULATORS = 12,\n};\n\nenum pg_states {\n\tPG_STATE_OFF = 0,\n\tPG_STATE_ON = 1,\n\tPG_STATE_RUNNING = 2,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum pgtable_type {\n\tTABLE_PTE = 0,\n\tTABLE_PMD = 1,\n\tTABLE_PUD = 2,\n\tTABLE_P4D = 3,\n};\n\nenum phy_event {\n\tPHYE_LOSS_OF_SIGNAL = 0,\n\tPHYE_OOB_DONE = 1,\n\tPHYE_OOB_ERROR = 2,\n\tPHYE_SPINUP_HOLD = 3,\n\tPHYE_RESUME_TIMEOUT = 4,\n\tPHYE_SHUTDOWN = 5,\n\tPHY_NUM_EVENTS = 6,\n};\n\nenum phy_func {\n\tPHY_FUNC_NOP = 0,\n\tPHY_FUNC_LINK_RESET = 1,\n\tPHY_FUNC_HARD_RESET = 2,\n\tPHY_FUNC_DISABLE = 3,\n\tPHY_FUNC_CLEAR_ERROR_LOG = 5,\n\tPHY_FUNC_CLEAR_AFFIL = 6,\n\tPHY_FUNC_TX_SATA_PS_SIGNAL = 7,\n\tPHY_FUNC_RELEASE_SPINUP_HOLD = 16,\n\tPHY_FUNC_SET_LINK_RATE = 17,\n\tPHY_FUNC_GET_EVENTS = 18,\n};\n\nenum phy_led_modes {\n\tPHY_LED_ACTIVE_HIGH = 0,\n\tPHY_LED_ACTIVE_LOW = 1,\n\tPHY_LED_INACTIVE_HIGH_IMPEDANCE = 2,\n\t__PHY_LED_MODES_NUM = 3,\n};\n\nenum phy_media {\n\tPHY_MEDIA_DEFAULT = 0,\n\tPHY_MEDIA_SR = 1,\n\tPHY_MEDIA_DAC = 2,\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n\tPHY_MODE_HDMI = 20,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_port_parent {\n\tPHY_PORT_PHY = 0,\n};\n\nenum phy_reset_delays {\n\tPRE_DELAY = 0,\n\tPULSE = 1,\n\tPOST_DELAY = 2,\n\tDELAYS_NUM = 3,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_state_work {\n\tPHY_STATE_WORK_NONE = 0,\n\tPHY_STATE_WORK_ANEG = 1,\n\tPHY_STATE_WORK_SUSPEND = 2,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_ufs_state {\n\tPHY_UFS_HIBERN8_ENTER = 0,\n\tPHY_UFS_HIBERN8_EXIT = 1,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum phylink_op_type {\n\tPHYLINK_NETDEV = 0,\n\tPHYLINK_DEV = 1,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidcg_event {\n\tPIDCG_MAX = 0,\n\tPIDCG_FORKFAIL = 1,\n\tNR_PIDCG_EVENTS = 2,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum pin_config_param {\n\tPIN_CONFIG_BIAS_BUS_HOLD = 0,\n\tPIN_CONFIG_BIAS_DISABLE = 1,\n\tPIN_CONFIG_BIAS_HIGH_IMPEDANCE = 2,\n\tPIN_CONFIG_BIAS_PULL_DOWN = 3,\n\tPIN_CONFIG_BIAS_PULL_PIN_DEFAULT = 4,\n\tPIN_CONFIG_BIAS_PULL_UP = 5,\n\tPIN_CONFIG_DRIVE_OPEN_DRAIN = 6,\n\tPIN_CONFIG_DRIVE_OPEN_SOURCE = 7,\n\tPIN_CONFIG_DRIVE_PUSH_PULL = 8,\n\tPIN_CONFIG_DRIVE_STRENGTH = 9,\n\tPIN_CONFIG_DRIVE_STRENGTH_UA = 10,\n\tPIN_CONFIG_INPUT_DEBOUNCE = 11,\n\tPIN_CONFIG_INPUT_ENABLE = 12,\n\tPIN_CONFIG_INPUT_SCHMITT = 13,\n\tPIN_CONFIG_INPUT_SCHMITT_ENABLE = 14,\n\tPIN_CONFIG_INPUT_SCHMITT_UV = 15,\n\tPIN_CONFIG_MODE_LOW_POWER = 16,\n\tPIN_CONFIG_MODE_PWM = 17,\n\tPIN_CONFIG_LEVEL = 18,\n\tPIN_CONFIG_OUTPUT_ENABLE = 19,\n\tPIN_CONFIG_OUTPUT_IMPEDANCE_OHMS = 20,\n\tPIN_CONFIG_PERSIST_STATE = 21,\n\tPIN_CONFIG_POWER_SOURCE = 22,\n\tPIN_CONFIG_SKEW_DELAY = 23,\n\tPIN_CONFIG_SKEW_DELAY_INPUT_PS = 24,\n\tPIN_CONFIG_SKEW_DELAY_OUTPUT_PS = 25,\n\tPIN_CONFIG_SLEEP_HARDWARE_STATE = 26,\n\tPIN_CONFIG_SLEW_RATE = 27,\n\tPIN_CONFIG_END = 127,\n\tPIN_CONFIG_MAX = 255,\n};\n\nenum pincfg_type {\n\tPINCFG_TYPE_FUNC = 0,\n\tPINCFG_TYPE_DAT = 1,\n\tPINCFG_TYPE_PUD = 2,\n\tPINCFG_TYPE_DRV = 3,\n\tPINCFG_TYPE_CON_PDN = 4,\n\tPINCFG_TYPE_PUD_PDN = 5,\n\tPINCFG_TYPE_NUM = 6,\n};\n\nenum pinctrl_map_type {\n\tPIN_MAP_TYPE_INVALID = 0,\n\tPIN_MAP_TYPE_DUMMY_STATE = 1,\n\tPIN_MAP_TYPE_MUX_GROUP = 2,\n\tPIN_MAP_TYPE_CONFIGS_PIN = 3,\n\tPIN_MAP_TYPE_CONFIGS_GROUP = 4,\n};\n\nenum pkcs7_actions {\n\tACT_pkcs7_check_content_type = 0,\n\tACT_pkcs7_extract_cert = 1,\n\tACT_pkcs7_note_OID = 2,\n\tACT_pkcs7_note_certificate_list = 3,\n\tACT_pkcs7_note_content = 4,\n\tACT_pkcs7_note_data = 5,\n\tACT_pkcs7_note_signed_info = 6,\n\tACT_pkcs7_note_signeddata_version = 7,\n\tACT_pkcs7_note_signerinfo_version = 8,\n\tACT_pkcs7_sig_note_authenticated_attr = 9,\n\tACT_pkcs7_sig_note_digest_algo = 10,\n\tACT_pkcs7_sig_note_issuer = 11,\n\tACT_pkcs7_sig_note_pkey_algo = 12,\n\tACT_pkcs7_sig_note_serial = 13,\n\tACT_pkcs7_sig_note_set_of_authattrs = 14,\n\tACT_pkcs7_sig_note_signature = 15,\n\tACT_pkcs7_sig_note_skid = 16,\n\tNR__pkcs7_actions = 17,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum pkvm_component_id {\n\tPKVM_ID_HOST = 0,\n\tPKVM_ID_HYP = 1,\n\tPKVM_ID_FFA = 2,\n};\n\nenum pkvm_page_state {\n\tPKVM_PAGE_OWNED = 0,\n\tPKVM_PAGE_SHARED_OWNED = 1,\n\tPKVM_PAGE_SHARED_BORROWED = 2,\n\tPKVM_NOPAGE = 3,\n};\n\nenum pl011_rs485_tx_state {\n\tOFF___2 = 0,\n\tWAIT_AFTER_RTS___2 = 1,\n\tSEND___2 = 2,\n\tWAIT_AFTER_SEND___2 = 3,\n};\n\nenum pl330_byteswap {\n\tSWAP_NO = 0,\n\tSWAP_2 = 1,\n\tSWAP_4 = 2,\n\tSWAP_8 = 3,\n\tSWAP_16 = 4,\n};\n\nenum pl330_cachectrl {\n\tCCTRL0 = 0,\n\tCCTRL1 = 1,\n\tCCTRL2 = 2,\n\tCCTRL3 = 3,\n\tINVALID1 = 4,\n\tINVALID2 = 5,\n\tCCTRL6 = 6,\n\tCCTRL7 = 7,\n};\n\nenum pl330_cond {\n\tSINGLE = 0,\n\tBURST = 1,\n\tALWAYS = 2,\n};\n\nenum pl330_dmac_state {\n\tUNINIT___2 = 0,\n\tINIT = 1,\n\tDYING = 2,\n};\n\nenum pl330_op_err {\n\tPL330_ERR_NONE = 0,\n\tPL330_ERR_ABORT = 1,\n\tPL330_ERR_FAIL = 2,\n};\n\nenum pll_ctrl_bits {\n\tPLL_RESETB = 0,\n\tSSPLL_SUSPEND_EN = 1,\n\tPLL_SEQ_START = 2,\n\tPLL_LOCK = 3,\n};\n\nenum pll_mode {\n\tPLL_MODE_INT = 0,\n\tPLL_MODE_FRAC = 1,\n\tPLL_MODE_ERROR = 2,\n};\n\nenum pm_api_cb_id {\n\tPM_INIT_SUSPEND_CB = 30,\n\tPM_ACKNOWLEDGE_CB = 31,\n\tPM_NOTIFY_CB = 32,\n};\n\nenum pm_api_id {\n\tPM_API_FEATURES = 0,\n\tPM_GET_API_VERSION = 1,\n\tPM_GET_NODE_STATUS = 3,\n\tPM_REGISTER_NOTIFIER = 5,\n\tPM_FORCE_POWERDOWN = 8,\n\tPM_REQUEST_WAKEUP = 10,\n\tPM_SYSTEM_SHUTDOWN = 12,\n\tPM_REQUEST_NODE = 13,\n\tPM_RELEASE_NODE = 14,\n\tPM_SET_REQUIREMENT = 15,\n\tPM_RESET_ASSERT = 17,\n\tPM_RESET_GET_STATUS = 18,\n\tPM_MMIO_WRITE = 19,\n\tPM_MMIO_READ = 20,\n\tPM_PM_INIT_FINALIZE = 21,\n\tPM_FPGA_LOAD = 22,\n\tPM_FPGA_GET_STATUS = 23,\n\tPM_GET_CHIPID = 24,\n\tPM_SECURE_SHA = 26,\n\tPM_PINCTRL_REQUEST = 28,\n\tPM_PINCTRL_RELEASE = 29,\n\tPM_PINCTRL_SET_FUNCTION = 31,\n\tPM_PINCTRL_CONFIG_PARAM_GET = 32,\n\tPM_PINCTRL_CONFIG_PARAM_SET = 33,\n\tPM_IOCTL = 34,\n\tPM_QUERY_DATA = 35,\n\tPM_CLOCK_ENABLE = 36,\n\tPM_CLOCK_DISABLE = 37,\n\tPM_CLOCK_GETSTATE = 38,\n\tPM_CLOCK_SETDIVIDER = 39,\n\tPM_CLOCK_GETDIVIDER = 40,\n\tPM_CLOCK_SETPARENT = 43,\n\tPM_CLOCK_GETPARENT = 44,\n\tPM_FPGA_READ = 46,\n\tPM_SECURE_AES = 47,\n\tPM_EFUSE_ACCESS = 53,\n\tPM_FEATURE_CHECK = 63,\n};\n\nenum pm_feature_config_id {\n\tPM_FEATURE_INVALID = 0,\n\tPM_FEATURE_OVERTEMP_STATUS = 1,\n\tPM_FEATURE_OVERTEMP_VALUE = 2,\n\tPM_FEATURE_EXTWDT_STATUS = 3,\n\tPM_FEATURE_EXTWDT_VALUE = 4,\n};\n\nenum pm_gem_config_type {\n\tGEM_CONFIG_SGMII_MODE = 1,\n\tGEM_CONFIG_FIXED = 2,\n};\n\nenum pm_ioctl_id {\n\tIOCTL_GET_RPU_OPER_MODE = 0,\n\tIOCTL_SET_RPU_OPER_MODE = 1,\n\tIOCTL_RPU_BOOT_ADDR_CONFIG = 2,\n\tIOCTL_TCM_COMB_CONFIG = 3,\n\tIOCTL_SET_TAPDELAY_BYPASS = 4,\n\tIOCTL_SD_DLL_RESET = 6,\n\tIOCTL_SET_SD_TAPDELAY = 7,\n\tIOCTL_SET_PLL_FRAC_MODE = 8,\n\tIOCTL_GET_PLL_FRAC_MODE = 9,\n\tIOCTL_SET_PLL_FRAC_DATA = 10,\n\tIOCTL_GET_PLL_FRAC_DATA = 11,\n\tIOCTL_WRITE_GGS = 12,\n\tIOCTL_READ_GGS = 13,\n\tIOCTL_WRITE_PGGS = 14,\n\tIOCTL_READ_PGGS = 15,\n\tIOCTL_SET_BOOT_HEALTH_STATUS = 17,\n\tIOCTL_OSPI_MUX_SELECT = 21,\n\tIOCTL_REGISTER_SGI = 25,\n\tIOCTL_SET_FEATURE_CONFIG = 26,\n\tIOCTL_GET_FEATURE_CONFIG = 27,\n\tIOCTL_READ_REG = 28,\n\tIOCTL_MASK_WRITE_REG = 29,\n\tIOCTL_SET_SD_CONFIG = 30,\n\tIOCTL_SET_GEM_CONFIG = 31,\n\tIOCTL_GET_QOS = 34,\n};\n\nenum pm_module_id {\n\tPM_MODULE_ID = 0,\n\tXPM_MODULE_ID = 2,\n\tXSEM_MODULE_ID = 3,\n\tTF_A_MODULE_ID = 10,\n};\n\nenum pm_node_id {\n\tNODE_SD_0 = 39,\n\tNODE_SD_1 = 40,\n};\n\nenum pm_pinctrl_bias_status {\n\tPM_PINCTRL_BIAS_DISABLE = 0,\n\tPM_PINCTRL_BIAS_ENABLE = 1,\n};\n\nenum pm_pinctrl_config_param {\n\tPM_PINCTRL_CONFIG_SLEW_RATE = 0,\n\tPM_PINCTRL_CONFIG_BIAS_STATUS = 1,\n\tPM_PINCTRL_CONFIG_PULL_CTRL = 2,\n\tPM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,\n\tPM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,\n\tPM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,\n\tPM_PINCTRL_CONFIG_TRI_STATE = 6,\n\tPM_PINCTRL_CONFIG_MAX = 7,\n};\n\nenum pm_pinctrl_drive_strength {\n\tPM_PINCTRL_DRIVE_STRENGTH_2MA = 0,\n\tPM_PINCTRL_DRIVE_STRENGTH_4MA = 1,\n\tPM_PINCTRL_DRIVE_STRENGTH_8MA = 2,\n\tPM_PINCTRL_DRIVE_STRENGTH_12MA = 3,\n};\n\nenum pm_pinctrl_pull_ctrl {\n\tPM_PINCTRL_BIAS_PULL_DOWN = 0,\n\tPM_PINCTRL_BIAS_PULL_UP = 1,\n};\n\nenum pm_pinctrl_tri_state {\n\tPM_PINCTRL_TRI_STATE_DISABLE = 0,\n\tPM_PINCTRL_TRI_STATE_ENABLE = 1,\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = -1,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum pm_query_id {\n\tPM_QID_INVALID = 0,\n\tPM_QID_CLOCK_GET_NAME = 1,\n\tPM_QID_CLOCK_GET_TOPOLOGY = 2,\n\tPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,\n\tPM_QID_CLOCK_GET_PARENTS = 4,\n\tPM_QID_CLOCK_GET_ATTRIBUTES = 5,\n\tPM_QID_PINCTRL_GET_NUM_PINS = 6,\n\tPM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,\n\tPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,\n\tPM_QID_PINCTRL_GET_FUNCTION_NAME = 9,\n\tPM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,\n\tPM_QID_PINCTRL_GET_PIN_GROUPS = 11,\n\tPM_QID_CLOCK_GET_NUM_CLOCKS = 12,\n\tPM_QID_CLOCK_GET_MAX_DIVISOR = 13,\n\tPM_QID_PINCTRL_GET_ATTRIBUTES = 15,\n};\n\nenum pm_ret_status {\n\tXST_PM_SUCCESS = 0,\n\tXST_PM_INVALID_VERSION = 4,\n\tXST_PM_NO_FEATURE = 19,\n\tXST_PM_INVALID_CRC = 301,\n\tXST_PM_INTERNAL = 2000,\n\tXST_PM_CONFLICT = 2001,\n\tXST_PM_NO_ACCESS = 2002,\n\tXST_PM_INVALID_NODE = 2003,\n\tXST_PM_DOUBLE_REQ = 2004,\n\tXST_PM_ABORT_SUSPEND = 2005,\n\tXST_PM_MULT_USER = 2008,\n};\n\nenum pm_sd_config_type {\n\tSD_CONFIG_EMMC_SEL = 1,\n\tSD_CONFIG_BASECLK = 2,\n\tSD_CONFIG_8BIT = 3,\n\tSD_CONFIG_FIXED = 4,\n};\n\nenum pm_suspend_mode {\n\tPM_SUSPEND_MODE_FIRST = 0,\n\tPM_SUSPEND_MODE_STD = 0,\n\tPM_SUSPEND_MODE_POWER_OFF = 1,\n};\n\nenum pmic_arb_channel {\n\tPMIC_ARB_CHANNEL_RW = 0,\n\tPMIC_ARB_CHANNEL_OBS = 1,\n};\n\nenum pmic_arb_chnl_status {\n\tPMIC_ARB_STATUS_DONE = 1,\n\tPMIC_ARB_STATUS_FAILURE = 2,\n\tPMIC_ARB_STATUS_DENIED = 4,\n\tPMIC_ARB_STATUS_DROPPED = 8,\n};\n\nenum pmic_arb_cmd_op_code {\n\tPMIC_ARB_OP_EXT_WRITEL = 0,\n\tPMIC_ARB_OP_EXT_READL = 1,\n\tPMIC_ARB_OP_EXT_WRITE = 2,\n\tPMIC_ARB_OP_RESET = 3,\n\tPMIC_ARB_OP_SLEEP = 4,\n\tPMIC_ARB_OP_SHUTDOWN = 5,\n\tPMIC_ARB_OP_WAKEUP = 6,\n\tPMIC_ARB_OP_AUTHENTICATE = 7,\n\tPMIC_ARB_OP_MSTR_READ = 8,\n\tPMIC_ARB_OP_MSTR_WRITE = 9,\n\tPMIC_ARB_OP_EXT_READ = 13,\n\tPMIC_ARB_OP_WRITE = 14,\n\tPMIC_ARB_OP_READ = 15,\n\tPMIC_ARB_OP_ZERO_WRITE = 16,\n};\n\nenum pmic_gpio_func_index {\n\tPMIC_GPIO_FUNC_INDEX_NORMAL = 0,\n\tPMIC_GPIO_FUNC_INDEX_PAIRED = 1,\n\tPMIC_GPIO_FUNC_INDEX_FUNC1 = 2,\n\tPMIC_GPIO_FUNC_INDEX_FUNC2 = 3,\n\tPMIC_GPIO_FUNC_INDEX_FUNC3 = 4,\n\tPMIC_GPIO_FUNC_INDEX_FUNC4 = 5,\n\tPMIC_GPIO_FUNC_INDEX_DTEST1 = 6,\n\tPMIC_GPIO_FUNC_INDEX_DTEST2 = 7,\n\tPMIC_GPIO_FUNC_INDEX_DTEST3 = 8,\n\tPMIC_GPIO_FUNC_INDEX_DTEST4 = 9,\n};\n\nenum pmic_id {\n\tTPS65214 = 0,\n\tTPS65215 = 1,\n\tTPS65219 = 2,\n};\n\nenum pmic_type {\n\tPMIC_MT6323 = 0,\n\tPMIC_MT6331 = 1,\n\tPMIC_MT6332 = 2,\n\tPMIC_MT6351 = 3,\n\tPMIC_MT6357 = 4,\n\tPMIC_MT6358 = 5,\n\tPMIC_MT6359 = 6,\n\tPMIC_MT6380 = 7,\n\tPMIC_MT6397 = 8,\n};\n\nenum pnfs_iomode {\n\tIOMODE_READ = 1,\n\tIOMODE_RW = 2,\n\tIOMODE_ANY = 3,\n};\n\nenum pnfs_layout_destroy_mode {\n\tPNFS_LAYOUT_INVALIDATE = 0,\n\tPNFS_LAYOUT_BULK_RETURN = 1,\n\tPNFS_LAYOUT_FILE_BULK_RETURN = 2,\n};\n\nenum pnfs_layoutreturn_type {\n\tRETURN_FILE = 1,\n\tRETURN_FSID = 2,\n\tRETURN_ALL = 3,\n};\n\nenum pnfs_layouttype {\n\tLAYOUT_NFSV4_1_FILES = 1,\n\tLAYOUT_OSD2_OBJECTS = 2,\n\tLAYOUT_BLOCK_VOLUME = 3,\n\tLAYOUT_FLEX_FILES = 4,\n\tLAYOUT_SCSI = 5,\n\tLAYOUT_TYPE_MAX = 6,\n};\n\nenum pnfs_notify_deviceid_type4 {\n\tNOTIFY_DEVICEID4_CHANGE = 2,\n\tNOTIFY_DEVICEID4_DELETE = 4,\n};\n\nenum pnfs_try_status {\n\tPNFS_ATTEMPTED = 0,\n\tPNFS_NOT_ATTEMPTED = 1,\n\tPNFS_TRY_AGAIN = 2,\n};\n\nenum pnfs_update_layout_reason {\n\tPNFS_UPDATE_LAYOUT_UNKNOWN = 0,\n\tPNFS_UPDATE_LAYOUT_NO_PNFS = 1,\n\tPNFS_UPDATE_LAYOUT_RD_ZEROLEN = 2,\n\tPNFS_UPDATE_LAYOUT_MDSTHRESH = 3,\n\tPNFS_UPDATE_LAYOUT_NOMEM = 4,\n\tPNFS_UPDATE_LAYOUT_BULK_RECALL = 5,\n\tPNFS_UPDATE_LAYOUT_IO_TEST_FAIL = 6,\n\tPNFS_UPDATE_LAYOUT_FOUND_CACHED = 7,\n\tPNFS_UPDATE_LAYOUT_RETURN = 8,\n\tPNFS_UPDATE_LAYOUT_RETRY = 9,\n\tPNFS_UPDATE_LAYOUT_BLOCKED = 10,\n\tPNFS_UPDATE_LAYOUT_INVALID_OPEN = 11,\n\tPNFS_UPDATE_LAYOUT_SEND_LAYOUTGET = 12,\n\tPNFS_UPDATE_LAYOUT_EXIT = 13,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port_event {\n\tPORTE_BYTES_DMAED = 0,\n\tPORTE_BROADCAST_RCVD = 1,\n\tPORTE_LINK_RESET_ERR = 2,\n\tPORTE_TIMER_EVENT = 3,\n\tPORTE_HARD_RESET = 4,\n\tPORT_NUM_EVENTS = 5,\n};\n\nenum port_pkey_state {\n\tIB_PORT_PKEY_NOT_VALID = 0,\n\tIB_PORT_PKEY_VALID = 1,\n\tIB_PORT_PKEY_LISTED = 2,\n};\n\nenum port_type {\n\tRX___2 = 0,\n\tTX___2 = 1,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum power_desc_param_offset {\n\tPWR_DESC_LEN = 0,\n\tPWR_DESC_TYPE = 1,\n\tPWR_DESC_ACTIVE_LVLS_VCC_0 = 2,\n\tPWR_DESC_ACTIVE_LVLS_VCCQ_0 = 34,\n\tPWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 66,\n};\n\nenum power_supply_charge_behaviour {\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO = 0,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE = 1,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE_AWAKE = 2,\n\tPOWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE = 3,\n};\n\nenum power_supply_charge_type {\n\tPOWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_CHARGE_TYPE_NONE = 1,\n\tPOWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2,\n\tPOWER_SUPPLY_CHARGE_TYPE_FAST = 3,\n\tPOWER_SUPPLY_CHARGE_TYPE_STANDARD = 4,\n\tPOWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5,\n\tPOWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6,\n\tPOWER_SUPPLY_CHARGE_TYPE_LONGLIFE = 7,\n\tPOWER_SUPPLY_CHARGE_TYPE_BYPASS = 8,\n};\n\nenum power_supply_notifier_events {\n\tPSY_EVENT_PROP_CHANGED = 0,\n};\n\nenum power_supply_property {\n\tPOWER_SUPPLY_PROP_STATUS = 0,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPE = 1,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPES = 2,\n\tPOWER_SUPPLY_PROP_HEALTH = 3,\n\tPOWER_SUPPLY_PROP_PRESENT = 4,\n\tPOWER_SUPPLY_PROP_ONLINE = 5,\n\tPOWER_SUPPLY_PROP_AUTHENTIC = 6,\n\tPOWER_SUPPLY_PROP_TECHNOLOGY = 7,\n\tPOWER_SUPPLY_PROP_CYCLE_COUNT = 8,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX = 9,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN = 10,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN = 11,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN = 12,\n\tPOWER_SUPPLY_PROP_VOLTAGE_NOW = 13,\n\tPOWER_SUPPLY_PROP_VOLTAGE_AVG = 14,\n\tPOWER_SUPPLY_PROP_VOLTAGE_OCV = 15,\n\tPOWER_SUPPLY_PROP_VOLTAGE_BOOT = 16,\n\tPOWER_SUPPLY_PROP_CURRENT_MAX = 17,\n\tPOWER_SUPPLY_PROP_CURRENT_NOW = 18,\n\tPOWER_SUPPLY_PROP_CURRENT_AVG = 19,\n\tPOWER_SUPPLY_PROP_CURRENT_BOOT = 20,\n\tPOWER_SUPPLY_PROP_POWER_NOW = 21,\n\tPOWER_SUPPLY_PROP_POWER_AVG = 22,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL_DESIGN = 23,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN = 24,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL = 25,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY = 26,\n\tPOWER_SUPPLY_PROP_CHARGE_NOW = 27,\n\tPOWER_SUPPLY_PROP_CHARGE_AVG = 28,\n\tPOWER_SUPPLY_PROP_CHARGE_COUNTER = 29,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT = 30,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX = 31,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE = 32,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX = 33,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT = 34,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX = 35,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD = 36,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD = 37,\n\tPOWER_SUPPLY_PROP_CHARGE_BEHAVIOUR = 38,\n\tPOWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT = 39,\n\tPOWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT = 40,\n\tPOWER_SUPPLY_PROP_INPUT_POWER_LIMIT = 41,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL_DESIGN = 42,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN = 43,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL = 44,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY = 45,\n\tPOWER_SUPPLY_PROP_ENERGY_NOW = 46,\n\tPOWER_SUPPLY_PROP_ENERGY_AVG = 47,\n\tPOWER_SUPPLY_PROP_CAPACITY = 48,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MIN = 49,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MAX = 50,\n\tPOWER_SUPPLY_PROP_CAPACITY_ERROR_MARGIN = 51,\n\tPOWER_SUPPLY_PROP_CAPACITY_LEVEL = 52,\n\tPOWER_SUPPLY_PROP_TEMP = 53,\n\tPOWER_SUPPLY_PROP_TEMP_MAX = 54,\n\tPOWER_SUPPLY_PROP_TEMP_MIN = 55,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MIN = 56,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MAX = 57,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT = 58,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN = 59,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX = 60,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW = 61,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG = 62,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_NOW = 63,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_AVG = 64,\n\tPOWER_SUPPLY_PROP_TYPE = 65,\n\tPOWER_SUPPLY_PROP_USB_TYPE = 66,\n\tPOWER_SUPPLY_PROP_SCOPE = 67,\n\tPOWER_SUPPLY_PROP_PRECHARGE_CURRENT = 68,\n\tPOWER_SUPPLY_PROP_CHARGE_TERM_CURRENT = 69,\n\tPOWER_SUPPLY_PROP_CALIBRATE = 70,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_YEAR = 71,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_MONTH = 72,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_DAY = 73,\n\tPOWER_SUPPLY_PROP_INTERNAL_RESISTANCE = 74,\n\tPOWER_SUPPLY_PROP_STATE_OF_HEALTH = 75,\n\tPOWER_SUPPLY_PROP_MODEL_NAME = 76,\n\tPOWER_SUPPLY_PROP_MANUFACTURER = 77,\n\tPOWER_SUPPLY_PROP_SERIAL_NUMBER = 78,\n};\n\nenum power_supply_type {\n\tPOWER_SUPPLY_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_TYPE_BATTERY = 1,\n\tPOWER_SUPPLY_TYPE_UPS = 2,\n\tPOWER_SUPPLY_TYPE_MAINS = 3,\n\tPOWER_SUPPLY_TYPE_USB = 4,\n\tPOWER_SUPPLY_TYPE_USB_DCP = 5,\n\tPOWER_SUPPLY_TYPE_USB_CDP = 6,\n\tPOWER_SUPPLY_TYPE_USB_ACA = 7,\n\tPOWER_SUPPLY_TYPE_USB_TYPE_C = 8,\n\tPOWER_SUPPLY_TYPE_USB_PD = 9,\n\tPOWER_SUPPLY_TYPE_USB_PD_DRP = 10,\n\tPOWER_SUPPLY_TYPE_APPLE_BRICK_ID = 11,\n\tPOWER_SUPPLY_TYPE_WIRELESS = 12,\n};\n\nenum power_supply_usb_type {\n\tPOWER_SUPPLY_USB_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_USB_TYPE_SDP = 1,\n\tPOWER_SUPPLY_USB_TYPE_DCP = 2,\n\tPOWER_SUPPLY_USB_TYPE_CDP = 3,\n\tPOWER_SUPPLY_USB_TYPE_ACA = 4,\n\tPOWER_SUPPLY_USB_TYPE_C = 5,\n\tPOWER_SUPPLY_USB_TYPE_PD = 6,\n\tPOWER_SUPPLY_USB_TYPE_PD_DRP = 7,\n\tPOWER_SUPPLY_USB_TYPE_PD_PPS = 8,\n\tPOWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID = 9,\n};\n\nenum ppe_common_mode {\n\tPPE_COMMON_MODE_DEBUG = 0,\n\tPPE_COMMON_MODE_SERVICE = 1,\n\tPPE_COMMON_MODE_MAX = 2,\n};\n\nenum ppe_port_mode {\n\tPPE_MODE_GE = 0,\n\tPPE_MODE_XGE = 1,\n};\n\nenum ppe_qid_mode {\n\tPPE_QID_MODE0 = 0,\n\tPPE_QID_MODE1 = 1,\n\tPPE_QID_MODE2 = 2,\n\tPPE_QID_MODE3 = 3,\n\tPPE_QID_MODE4 = 4,\n\tPPE_QID_MODE5 = 5,\n\tPPE_QID_MODE6 = 6,\n\tPPE_QID_MODE7 = 7,\n\tPPE_QID_MODE8 = 8,\n\tPPE_QID_MODE9 = 9,\n\tPPE_QID_MODE10 = 10,\n\tPPE_QID_MODE11 = 11,\n};\n\nenum ppi_reg {\n\tPPI_PENDING = 0,\n\tPPI_ACTIVE = 1,\n\tPPI_HM = 2,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum pri_resp {\n\tPRI_RESP_DENY = 0,\n\tPRI_RESP_FAIL = 1,\n\tPRI_RESP_SUCC = 2,\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_insn {\n\tINSN_REJECTED = 0,\n\tINSN_GOOD_NO_SLOT = 1,\n\tINSN_GOOD = 2,\n};\n\nenum probe_print_type {\n\tPROBE_PRINT_NORMAL = 0,\n\tPROBE_PRINT_RETURN = 1,\n\tPROBE_PRINT_EVENT = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___8 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum ps2_disposition {\n\tPS2_PROCESS = 0,\n\tPS2_IGNORE = 1,\n\tPS2_ERROR = 2,\n};\n\nenum psil_endpoint_type {\n\tPSIL_EP_NATIVE = 0,\n\tPSIL_EP_PDMA_XY = 1,\n\tPSIL_EP_PDMA_MCAN = 2,\n\tPSIL_EP_PDMA_AASRC = 3,\n};\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nenum pstore_type_id {\n\tPSTORE_TYPE_DMESG = 0,\n\tPSTORE_TYPE_MCE = 1,\n\tPSTORE_TYPE_CONSOLE = 2,\n\tPSTORE_TYPE_FTRACE = 3,\n\tPSTORE_TYPE_PPC_RTAS = 4,\n\tPSTORE_TYPE_PPC_OF = 5,\n\tPSTORE_TYPE_PPC_COMMON = 6,\n\tPSTORE_TYPE_PMSG = 7,\n\tPSTORE_TYPE_PPC_OPAL = 8,\n\tPSTORE_TYPE_MAX = 9,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_EXTOFF = 2,\n\tPTP_CLOCK_PPS = 3,\n\tPTP_CLOCK_PPSUSR = 4,\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nenum ptrace_syscall_dir {\n\tPTRACE_SYSCALL_ENTER = 0,\n\tPTRACE_SYSCALL_EXIT = 1,\n};\n\nenum pud_index {\n\tPUD_PULL_DISABLE = 0,\n\tPUD_PULL_DOWN = 1,\n\tPUD_PULL_UP = 2,\n\tPUD_MAX = 3,\n};\n\nenum pwm_polarity {\n\tPWM_POLARITY_NORMAL = 0,\n\tPWM_POLARITY_INVERSED = 1,\n};\n\nenum pwrap_regs {\n\tPWRAP_MUX_SEL = 0,\n\tPWRAP_WRAP_EN = 1,\n\tPWRAP_DIO_EN = 2,\n\tPWRAP_SIDLY = 3,\n\tPWRAP_CSHEXT_WRITE = 4,\n\tPWRAP_CSHEXT_READ = 5,\n\tPWRAP_CSLEXT_START = 6,\n\tPWRAP_CSLEXT_END = 7,\n\tPWRAP_STAUPD_PRD = 8,\n\tPWRAP_STAUPD_GRPEN = 9,\n\tPWRAP_STAUPD_MAN_TRIG = 10,\n\tPWRAP_STAUPD_STA = 11,\n\tPWRAP_WRAP_STA = 12,\n\tPWRAP_HARB_INIT = 13,\n\tPWRAP_HARB_HPRIO = 14,\n\tPWRAP_HIPRIO_ARB_EN = 15,\n\tPWRAP_HARB_STA0 = 16,\n\tPWRAP_HARB_STA1 = 17,\n\tPWRAP_MAN_EN = 18,\n\tPWRAP_MAN_CMD = 19,\n\tPWRAP_MAN_RDATA = 20,\n\tPWRAP_MAN_VLDCLR = 21,\n\tPWRAP_WACS0_EN = 22,\n\tPWRAP_INIT_DONE0 = 23,\n\tPWRAP_WACS0_CMD = 24,\n\tPWRAP_WACS0_RDATA = 25,\n\tPWRAP_WACS0_VLDCLR = 26,\n\tPWRAP_WACS1_EN = 27,\n\tPWRAP_INIT_DONE1 = 28,\n\tPWRAP_WACS1_CMD = 29,\n\tPWRAP_WACS1_RDATA = 30,\n\tPWRAP_WACS1_VLDCLR = 31,\n\tPWRAP_WACS2_EN = 32,\n\tPWRAP_INIT_DONE2 = 33,\n\tPWRAP_WACS2_CMD = 34,\n\tPWRAP_WACS2_RDATA = 35,\n\tPWRAP_WACS2_VLDCLR = 36,\n\tPWRAP_INT_EN = 37,\n\tPWRAP_INT_FLG_RAW = 38,\n\tPWRAP_INT_FLG = 39,\n\tPWRAP_INT_CLR = 40,\n\tPWRAP_SIG_ADR = 41,\n\tPWRAP_SIG_MODE = 42,\n\tPWRAP_SIG_VALUE = 43,\n\tPWRAP_SIG_ERRVAL = 44,\n\tPWRAP_CRC_EN = 45,\n\tPWRAP_TIMER_EN = 46,\n\tPWRAP_TIMER_STA = 47,\n\tPWRAP_WDT_UNIT = 48,\n\tPWRAP_WDT_SRC_EN = 49,\n\tPWRAP_WDT_FLG = 50,\n\tPWRAP_DEBUG_INT_SEL = 51,\n\tPWRAP_CIPHER_KEY_SEL = 52,\n\tPWRAP_CIPHER_IV_SEL = 53,\n\tPWRAP_CIPHER_RDY = 54,\n\tPWRAP_CIPHER_MODE = 55,\n\tPWRAP_CIPHER_SWRST = 56,\n\tPWRAP_DCM_EN = 57,\n\tPWRAP_DCM_DBC_PRD = 58,\n\tPWRAP_EINT_STA0_ADR = 59,\n\tPWRAP_EINT_STA1_ADR = 60,\n\tPWRAP_SWINF_2_WDATA_31_0 = 61,\n\tPWRAP_SWINF_2_RDATA_31_0 = 62,\n\tPWRAP_ADC_CMD_ADDR = 63,\n\tPWRAP_PWRAP_ADC_CMD = 64,\n\tPWRAP_ADC_RDY_ADDR = 65,\n\tPWRAP_ADC_RDATA_ADDR1 = 66,\n\tPWRAP_ADC_RDATA_ADDR2 = 67,\n\tPWRAP_STA = 68,\n\tPWRAP_CLR = 69,\n\tPWRAP_DVFS_ADR8 = 70,\n\tPWRAP_DVFS_WDATA8 = 71,\n\tPWRAP_DVFS_ADR9 = 72,\n\tPWRAP_DVFS_WDATA9 = 73,\n\tPWRAP_DVFS_ADR10 = 74,\n\tPWRAP_DVFS_WDATA10 = 75,\n\tPWRAP_DVFS_ADR11 = 76,\n\tPWRAP_DVFS_WDATA11 = 77,\n\tPWRAP_DVFS_ADR12 = 78,\n\tPWRAP_DVFS_WDATA12 = 79,\n\tPWRAP_DVFS_ADR13 = 80,\n\tPWRAP_DVFS_WDATA13 = 81,\n\tPWRAP_DVFS_ADR14 = 82,\n\tPWRAP_DVFS_WDATA14 = 83,\n\tPWRAP_DVFS_ADR15 = 84,\n\tPWRAP_DVFS_WDATA15 = 85,\n\tPWRAP_EXT_CK = 86,\n\tPWRAP_ADC_RDATA_ADDR = 87,\n\tPWRAP_GPS_STA = 88,\n\tPWRAP_SW_RST = 89,\n\tPWRAP_DVFS_STEP_CTRL0 = 90,\n\tPWRAP_DVFS_STEP_CTRL1 = 91,\n\tPWRAP_DVFS_STEP_CTRL2 = 92,\n\tPWRAP_SPI2_CTRL = 93,\n\tPWRAP_CSHEXT = 94,\n\tPWRAP_EVENT_IN_EN = 95,\n\tPWRAP_EVENT_DST_EN = 96,\n\tPWRAP_RRARB_INIT = 97,\n\tPWRAP_RRARB_EN = 98,\n\tPWRAP_RRARB_STA0 = 99,\n\tPWRAP_RRARB_STA1 = 100,\n\tPWRAP_EVENT_STA = 101,\n\tPWRAP_EVENT_STACLR = 102,\n\tPWRAP_CIPHER_LOAD = 103,\n\tPWRAP_CIPHER_START = 104,\n\tPWRAP_RDDMY = 105,\n\tPWRAP_SI_CK_CON = 106,\n\tPWRAP_DVFS_ADR0 = 107,\n\tPWRAP_DVFS_WDATA0 = 108,\n\tPWRAP_DVFS_ADR1 = 109,\n\tPWRAP_DVFS_WDATA1 = 110,\n\tPWRAP_DVFS_ADR2 = 111,\n\tPWRAP_DVFS_WDATA2 = 112,\n\tPWRAP_DVFS_ADR3 = 113,\n\tPWRAP_DVFS_WDATA3 = 114,\n\tPWRAP_DVFS_ADR4 = 115,\n\tPWRAP_DVFS_WDATA4 = 116,\n\tPWRAP_DVFS_ADR5 = 117,\n\tPWRAP_DVFS_WDATA5 = 118,\n\tPWRAP_DVFS_ADR6 = 119,\n\tPWRAP_DVFS_WDATA6 = 120,\n\tPWRAP_DVFS_ADR7 = 121,\n\tPWRAP_DVFS_WDATA7 = 122,\n\tPWRAP_SPMINF_STA = 123,\n\tPWRAP_CIPHER_EN = 124,\n\tPWRAP_SI_SAMPLE_CTRL = 125,\n\tPWRAP_CSLEXT_WRITE = 126,\n\tPWRAP_CSLEXT_READ = 127,\n\tPWRAP_EXT_CK_WRITE = 128,\n\tPWRAP_STAUPD_CTRL = 129,\n\tPWRAP_WACS_P2P_EN = 130,\n\tPWRAP_INIT_DONE_P2P = 131,\n\tPWRAP_WACS_MD32_EN = 132,\n\tPWRAP_INIT_DONE_MD32 = 133,\n\tPWRAP_INT1_EN = 134,\n\tPWRAP_INT1_FLG = 135,\n\tPWRAP_INT1_CLR = 136,\n\tPWRAP_WDT_SRC_EN_1 = 137,\n\tPWRAP_INT_GPS_AUXADC_CMD_ADDR = 138,\n\tPWRAP_INT_GPS_AUXADC_CMD = 139,\n\tPWRAP_INT_GPS_AUXADC_RDATA_ADDR = 140,\n\tPWRAP_EXT_GPS_AUXADC_RDATA_ADDR = 141,\n\tPWRAP_GPSINF_0_STA = 142,\n\tPWRAP_GPSINF_1_STA = 143,\n\tPWRAP_OP_TYPE = 144,\n\tPWRAP_MSB_FIRST = 145,\n};\n\nenum pwrap_type {\n\tPWRAP_MT2701 = 0,\n\tPWRAP_MT6765 = 1,\n\tPWRAP_MT6779 = 2,\n\tPWRAP_MT6795 = 3,\n\tPWRAP_MT6797 = 4,\n\tPWRAP_MT6873 = 5,\n\tPWRAP_MT7622 = 6,\n\tPWRAP_MT8135 = 7,\n\tPWRAP_MT8173 = 8,\n\tPWRAP_MT8183 = 9,\n\tPWRAP_MT8186 = 10,\n\tPWRAP_MT8195 = 11,\n\tPWRAP_MT8365 = 12,\n\tPWRAP_MT8516 = 13,\n};\n\nenum px30_plls {\n\tapll = 0,\n\tdpll = 1,\n\tcpll = 2,\n\tnpll = 3,\n\tapll_b_h = 4,\n\tapll_b_l = 5,\n};\n\nenum px30_pmu_plls {\n\tgpll = 0,\n};\n\nenum pxa_i2c_types {\n\tREGS_PXA2XX = 0,\n\tREGS_PXA3XX = 1,\n\tREGS_CE4100 = 2,\n\tREGS_PXA910 = 3,\n\tREGS_A3700 = 4,\n};\n\nenum qb_enqueue_commands {\n\tenqueue_empty = 0,\n\tenqueue_response_always = 1,\n\tenqueue_rejects_to_fq = 2,\n};\n\nenum qb_pull_dt_e {\n\tqb_pull_dt_channel = 0,\n\tqb_pull_dt_workqueue = 1,\n\tqb_pull_dt_framequeue = 2,\n};\n\nenum qbman_pull_type_e {\n\tqbman_pull_type_prio = 1,\n\tqbman_pull_type_active = 2,\n\tqbman_pull_type_active_noics = 3,\n};\n\nenum qbman_sdqcr_dct {\n\tqbman_sdqcr_dct_null = 0,\n\tqbman_sdqcr_dct_prio_ics = 1,\n\tqbman_sdqcr_dct_active_ics = 2,\n\tqbman_sdqcr_dct_active = 3,\n};\n\nenum qbman_sdqcr_fc {\n\tqbman_sdqcr_fc_one = 0,\n\tqbman_sdqcr_fc_up_to_3 = 1,\n};\n\nenum qcm2290_functions {\n\tmsm_mux_adsp_ext___5 = 0,\n\tmsm_mux_agera_pll___2 = 1,\n\tmsm_mux_atest = 2,\n\tmsm_mux_cam_mclk___7 = 3,\n\tmsm_mux_cci_async___5 = 4,\n\tmsm_mux_cci_i2c___5 = 5,\n\tmsm_mux_cci_timer0___6 = 6,\n\tmsm_mux_cci_timer1___6 = 7,\n\tmsm_mux_cci_timer2___6 = 8,\n\tmsm_mux_cci_timer3___5 = 9,\n\tmsm_mux_char_exec = 10,\n\tmsm_mux_cri_trng___7 = 11,\n\tmsm_mux_cri_trng0___10 = 12,\n\tmsm_mux_cri_trng1___10 = 13,\n\tmsm_mux_dac_calib = 14,\n\tmsm_mux_dbg_out___11 = 15,\n\tmsm_mux_ddr_bist___4 = 16,\n\tmsm_mux_ddr_pxi0___3 = 17,\n\tmsm_mux_ddr_pxi1___3 = 18,\n\tmsm_mux_ddr_pxi2___2 = 19,\n\tmsm_mux_ddr_pxi3___2 = 20,\n\tmsm_mux_egpio___3 = 21,\n\tmsm_mux_gcc_gp1___3 = 22,\n\tmsm_mux_gcc_gp2___3 = 23,\n\tmsm_mux_gcc_gp3___3 = 24,\n\tmsm_mux_gpio___15 = 25,\n\tmsm_mux_gp_pdm0___2 = 26,\n\tmsm_mux_gp_pdm1___2 = 27,\n\tmsm_mux_gp_pdm2___2 = 28,\n\tmsm_mux_gsm0_tx___3 = 29,\n\tmsm_mux_gsm1_tx___3 = 30,\n\tmsm_mux_jitter_bist___4 = 31,\n\tmsm_mux_mdp_vsync___9 = 32,\n\tmsm_mux_mdp_vsync_out_0 = 33,\n\tmsm_mux_mdp_vsync_out_1 = 34,\n\tmsm_mux_mpm_pwr = 35,\n\tmsm_mux_mss_lte___5 = 36,\n\tmsm_mux_m_voc___6 = 37,\n\tmsm_mux_nav_gpio = 38,\n\tmsm_mux_pa_indicator___6 = 39,\n\tmsm_mux_pbs0___3 = 40,\n\tmsm_mux_pbs1___3 = 41,\n\tmsm_mux_pbs2___3 = 42,\n\tmsm_mux_pbs3 = 43,\n\tmsm_mux_pbs4 = 44,\n\tmsm_mux_pbs5 = 45,\n\tmsm_mux_pbs6 = 46,\n\tmsm_mux_pbs7 = 47,\n\tmsm_mux_pbs8 = 48,\n\tmsm_mux_pbs9 = 49,\n\tmsm_mux_pbs10 = 50,\n\tmsm_mux_pbs11 = 51,\n\tmsm_mux_pbs12 = 52,\n\tmsm_mux_pbs13 = 53,\n\tmsm_mux_pbs14 = 54,\n\tmsm_mux_pbs15 = 55,\n\tmsm_mux_pbs_out = 56,\n\tmsm_mux_phase_flag___4 = 57,\n\tmsm_mux_pll_bist = 58,\n\tmsm_mux_pll_bypassnl___3 = 59,\n\tmsm_mux_pll_reset___3 = 60,\n\tmsm_mux_prng_rosc___8 = 61,\n\tmsm_mux_pwm_0 = 62,\n\tmsm_mux_pwm_1 = 63,\n\tmsm_mux_pwm_2 = 64,\n\tmsm_mux_pwm_3 = 65,\n\tmsm_mux_pwm_4 = 66,\n\tmsm_mux_pwm_5 = 67,\n\tmsm_mux_pwm_6 = 68,\n\tmsm_mux_pwm_7 = 69,\n\tmsm_mux_pwm_8 = 70,\n\tmsm_mux_pwm_9 = 71,\n\tmsm_mux_qdss_cti___4 = 72,\n\tmsm_mux_qdss_gpio___2 = 73,\n\tmsm_mux_qup0 = 74,\n\tmsm_mux_qup1 = 75,\n\tmsm_mux_qup2 = 76,\n\tmsm_mux_qup3 = 77,\n\tmsm_mux_qup4 = 78,\n\tmsm_mux_qup5 = 79,\n\tmsm_mux_sdc1_tb = 80,\n\tmsm_mux_sdc2_tb = 81,\n\tmsm_mux_sd_write___8 = 82,\n\tmsm_mux_ssbi_wtr1___4 = 83,\n\tmsm_mux_tgu_ch0___2 = 84,\n\tmsm_mux_tgu_ch1___2 = 85,\n\tmsm_mux_tgu_ch2 = 86,\n\tmsm_mux_tgu_ch3 = 87,\n\tmsm_mux_tsense_pwm = 88,\n\tmsm_mux_uim1_clk___5 = 89,\n\tmsm_mux_uim1_data___5 = 90,\n\tmsm_mux_uim1_present___5 = 91,\n\tmsm_mux_uim1_reset___5 = 92,\n\tmsm_mux_uim2_clk___4 = 93,\n\tmsm_mux_uim2_data___4 = 94,\n\tmsm_mux_uim2_present___4 = 95,\n\tmsm_mux_uim2_reset___4 = 96,\n\tmsm_mux_usb_phy___3 = 97,\n\tmsm_mux_vfr_1___5 = 98,\n\tmsm_mux_vsense_trigger = 99,\n\tmsm_mux_wlan1_adc0___2 = 100,\n\tmsm_mux_wlan1_adc1___2 = 101,\n\tmsm_mux_____10 = 102,\n};\n\nenum qcom_icc_type {\n\tQCOM_ICC_NOC = 0,\n\tQCOM_ICC_BIMC = 1,\n\tQCOM_ICC_QNOC = 2,\n};\n\nenum qcom_iommu_clk {\n\tCLK_IFACE = 0,\n\tCLK_BUS = 1,\n\tCLK_TBU = 2,\n\tCLK_NUM = 3,\n};\n\nenum qcom_scm_arg_types {\n\tQCOM_SCM_VAL = 0,\n\tQCOM_SCM_RO = 1,\n\tQCOM_SCM_RW = 2,\n\tQCOM_SCM_BUFVAL = 3,\n};\n\nenum qcom_scm_convention {\n\tSMC_CONVENTION_UNKNOWN = 0,\n\tSMC_CONVENTION_LEGACY = 1,\n\tSMC_CONVENTION_ARM_32 = 2,\n\tSMC_CONVENTION_ARM_64 = 3,\n};\n\nenum qcom_scm_ice_cipher {\n\tQCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,\n\tQCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,\n\tQCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,\n\tQCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,\n};\n\nenum qcom_scm_ocmem_client {\n\tQCOM_SCM_OCMEM_UNUSED_ID = 0,\n\tQCOM_SCM_OCMEM_GRAPHICS_ID = 1,\n\tQCOM_SCM_OCMEM_VIDEO_ID = 2,\n\tQCOM_SCM_OCMEM_LP_AUDIO_ID = 3,\n\tQCOM_SCM_OCMEM_SENSORS_ID = 4,\n\tQCOM_SCM_OCMEM_OTHER_OS_ID = 5,\n\tQCOM_SCM_OCMEM_DEBUG_ID = 6,\n};\n\nenum qcom_scm_qseecom_resp_type {\n\tQSEECOM_SCM_RES_APP_ID = 60929,\n\tQSEECOM_SCM_RES_QSEOS_LISTENER_ID = 60930,\n};\n\nenum qcom_scm_qseecom_result {\n\tQSEECOM_RESULT_SUCCESS = 0,\n\tQSEECOM_RESULT_INCOMPLETE = 1,\n\tQSEECOM_RESULT_BLOCKED_ON_LISTENER = 2,\n\tQSEECOM_RESULT_FAILURE = 4294967295,\n};\n\nenum qcom_scm_qseecom_tz_cmd_app {\n\tQSEECOM_TZ_CMD_APP_SEND = 1,\n\tQSEECOM_TZ_CMD_APP_LOOKUP = 3,\n};\n\nenum qcom_scm_qseecom_tz_cmd_info {\n\tQSEECOM_TZ_CMD_INFO_VERSION = 3,\n};\n\nenum qcom_scm_qseecom_tz_owner {\n\tQSEECOM_TZ_OWNER_SIP = 2,\n\tQSEECOM_TZ_OWNER_TZ_APPS = 48,\n\tQSEECOM_TZ_OWNER_QSEE_OS = 50,\n};\n\nenum qcom_scm_qseecom_tz_svc {\n\tQSEECOM_TZ_SVC_APP_ID_PLACEHOLDER = 0,\n\tQSEECOM_TZ_SVC_APP_MGR = 1,\n\tQSEECOM_TZ_SVC_INFO = 6,\n};\n\nenum qcom_smmu_impl_reg_offset {\n\tQCOM_SMMU_TBU_PWR_STATUS = 0,\n\tQCOM_SMMU_STATS_SYNC_INV_TBU_ACK = 1,\n\tQCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR = 2,\n};\n\nenum qcom_socinfo_feature_code {\n\tSOCINFO_FC_UNKNOWN = 0,\n\tSOCINFO_FC_AA = 1,\n\tSOCINFO_FC_AB = 2,\n\tSOCINFO_FC_AC = 3,\n\tSOCINFO_FC_AD = 4,\n\tSOCINFO_FC_AE = 5,\n\tSOCINFO_FC_AF = 6,\n\tSOCINFO_FC_AG = 7,\n\tSOCINFO_FC_AH = 8,\n};\n\nenum qcom_tzmem_policy {\n\tQCOM_TZMEM_POLICY_STATIC = 1,\n\tQCOM_TZMEM_POLICY_MULTIPLIER = 2,\n\tQCOM_TZMEM_POLICY_ON_DEMAND = 3,\n};\n\nenum qcs404_functions {\n\tmsm_mux_gpio___16 = 0,\n\tmsm_mux_hdmi_tx = 1,\n\tmsm_mux_hdmi_ddc___4 = 2,\n\tmsm_mux_blsp_uart_tx_a2 = 3,\n\tmsm_mux_blsp_spi2___7 = 4,\n\tmsm_mux_m_voc___7 = 5,\n\tmsm_mux_qdss_cti_trig_in_a0___8 = 6,\n\tmsm_mux_blsp_uart_rx_a2 = 7,\n\tmsm_mux_qdss_tracectl_a___12 = 8,\n\tmsm_mux_blsp_uart2___6 = 9,\n\tmsm_mux_aud_cdc = 10,\n\tmsm_mux_blsp_i2c_sda_a2 = 11,\n\tmsm_mux_qdss_tracedata_a___12 = 12,\n\tmsm_mux_blsp_i2c_scl_a2 = 13,\n\tmsm_mux_qdss_tracectl_b___11 = 14,\n\tmsm_mux_qdss_cti_trig_in_b0___8 = 15,\n\tmsm_mux_blsp_uart1___5 = 16,\n\tmsm_mux_blsp_spi_mosi_a1 = 17,\n\tmsm_mux_blsp_spi_miso_a1 = 18,\n\tmsm_mux_qdss_tracedata_b___11 = 19,\n\tmsm_mux_blsp_i2c1___7 = 20,\n\tmsm_mux_blsp_spi_cs_n_a1 = 21,\n\tmsm_mux_gcc_plltest___8 = 22,\n\tmsm_mux_blsp_spi_clk_a1 = 23,\n\tmsm_mux_rgb_data0 = 24,\n\tmsm_mux_blsp_uart5___5 = 25,\n\tmsm_mux_blsp_spi5___7 = 26,\n\tmsm_mux_adsp_ext___6 = 27,\n\tmsm_mux_rgb_data1 = 28,\n\tmsm_mux_prng_rosc___9 = 29,\n\tmsm_mux_rgb_data2 = 30,\n\tmsm_mux_blsp_i2c5___7 = 31,\n\tmsm_mux_gcc_gp1_clk_b___6 = 32,\n\tmsm_mux_rgb_data3 = 33,\n\tmsm_mux_gcc_gp2_clk_b___6 = 34,\n\tmsm_mux_blsp_spi0 = 35,\n\tmsm_mux_blsp_uart0 = 36,\n\tmsm_mux_gcc_gp3_clk_b___6 = 37,\n\tmsm_mux_blsp_i2c0 = 38,\n\tmsm_mux_qdss_traceclk_b___11 = 39,\n\tmsm_mux_pcie_clk = 40,\n\tmsm_mux_nfc_irq___2 = 41,\n\tmsm_mux_blsp_spi4___7 = 42,\n\tmsm_mux_nfc_dwl___2 = 43,\n\tmsm_mux_audio_ts = 44,\n\tmsm_mux_rgb_data4 = 45,\n\tmsm_mux_spi_lcd = 46,\n\tmsm_mux_blsp_uart_tx_b2 = 47,\n\tmsm_mux_gcc_gp3_clk_a___6 = 48,\n\tmsm_mux_rgb_data5 = 49,\n\tmsm_mux_blsp_uart_rx_b2 = 50,\n\tmsm_mux_blsp_i2c_sda_b2 = 51,\n\tmsm_mux_blsp_i2c_scl_b2 = 52,\n\tmsm_mux_pwm_led11 = 53,\n\tmsm_mux_i2s_3_data0_a = 54,\n\tmsm_mux_ebi2_lcd = 55,\n\tmsm_mux_i2s_3_data1_a = 56,\n\tmsm_mux_i2s_3_data2_a = 57,\n\tmsm_mux_atest_char___13 = 58,\n\tmsm_mux_pwm_led3 = 59,\n\tmsm_mux_i2s_3_data3_a = 60,\n\tmsm_mux_pwm_led4 = 61,\n\tmsm_mux_i2s_4 = 62,\n\tmsm_mux_ebi2_a = 63,\n\tmsm_mux_dsd_clk_b = 64,\n\tmsm_mux_pwm_led5 = 65,\n\tmsm_mux_pwm_led6 = 66,\n\tmsm_mux_pwm_led7 = 67,\n\tmsm_mux_pwm_led8 = 68,\n\tmsm_mux_pwm_led24 = 69,\n\tmsm_mux_spkr_dac0 = 70,\n\tmsm_mux_blsp_i2c4___7 = 71,\n\tmsm_mux_pwm_led9 = 72,\n\tmsm_mux_pwm_led10 = 73,\n\tmsm_mux_spdifrx_opt = 74,\n\tmsm_mux_pwm_led12 = 75,\n\tmsm_mux_pwm_led13 = 76,\n\tmsm_mux_pwm_led14 = 77,\n\tmsm_mux_wlan1_adc1___3 = 78,\n\tmsm_mux_rgb_data_b0 = 79,\n\tmsm_mux_pwm_led15 = 80,\n\tmsm_mux_blsp_spi_mosi_b1 = 81,\n\tmsm_mux_wlan1_adc0___3 = 82,\n\tmsm_mux_rgb_data_b1 = 83,\n\tmsm_mux_pwm_led16 = 84,\n\tmsm_mux_blsp_spi_miso_b1 = 85,\n\tmsm_mux_qdss_cti_trig_out_b0___8 = 86,\n\tmsm_mux_wlan2_adc1___2 = 87,\n\tmsm_mux_rgb_data_b2 = 88,\n\tmsm_mux_pwm_led17 = 89,\n\tmsm_mux_blsp_spi_cs_n_b1 = 90,\n\tmsm_mux_wlan2_adc0___2 = 91,\n\tmsm_mux_rgb_data_b3 = 92,\n\tmsm_mux_pwm_led18 = 93,\n\tmsm_mux_blsp_spi_clk_b1 = 94,\n\tmsm_mux_rgb_data_b4 = 95,\n\tmsm_mux_pwm_led19 = 96,\n\tmsm_mux_ext_mclk1_b = 97,\n\tmsm_mux_qdss_traceclk_a___12 = 98,\n\tmsm_mux_rgb_data_b5 = 99,\n\tmsm_mux_pwm_led20 = 100,\n\tmsm_mux_atest_char3___9 = 101,\n\tmsm_mux_i2s_3_sck_b = 102,\n\tmsm_mux_ldo_update___6 = 103,\n\tmsm_mux_bimc_dte0___5 = 104,\n\tmsm_mux_rgb_hsync = 105,\n\tmsm_mux_pwm_led21 = 106,\n\tmsm_mux_i2s_3_ws_b = 107,\n\tmsm_mux_dbg_out___12 = 108,\n\tmsm_mux_rgb_vsync = 109,\n\tmsm_mux_i2s_3_data0_b = 110,\n\tmsm_mux_ldo_en___6 = 111,\n\tmsm_mux_hdmi_dtest = 112,\n\tmsm_mux_rgb_de = 113,\n\tmsm_mux_i2s_3_data1_b = 114,\n\tmsm_mux_hdmi_lbk9 = 115,\n\tmsm_mux_rgb_clk = 116,\n\tmsm_mux_atest_char1___9 = 117,\n\tmsm_mux_i2s_3_data2_b = 118,\n\tmsm_mux_ebi_cdc___2 = 119,\n\tmsm_mux_hdmi_lbk8 = 120,\n\tmsm_mux_rgb_mdp = 121,\n\tmsm_mux_atest_char0___9 = 122,\n\tmsm_mux_i2s_3_data3_b = 123,\n\tmsm_mux_hdmi_lbk7 = 124,\n\tmsm_mux_rgb_data_b6 = 125,\n\tmsm_mux_rgb_data_b7 = 126,\n\tmsm_mux_hdmi_lbk6 = 127,\n\tmsm_mux_rgmii_int = 128,\n\tmsm_mux_cri_trng1___11 = 129,\n\tmsm_mux_rgmii_wol = 130,\n\tmsm_mux_cri_trng0___11 = 131,\n\tmsm_mux_gcc_tlmm___8 = 132,\n\tmsm_mux_rgmii_ck = 133,\n\tmsm_mux_rgmii_tx = 134,\n\tmsm_mux_hdmi_lbk5 = 135,\n\tmsm_mux_hdmi_pixel = 136,\n\tmsm_mux_hdmi_rcv___4 = 137,\n\tmsm_mux_hdmi_lbk4 = 138,\n\tmsm_mux_rgmii_ctl = 139,\n\tmsm_mux_ext_lpass___3 = 140,\n\tmsm_mux_rgmii_rx = 141,\n\tmsm_mux_cri_trng___8 = 142,\n\tmsm_mux_hdmi_lbk3 = 143,\n\tmsm_mux_hdmi_lbk2 = 144,\n\tmsm_mux_qdss_cti_trig_out_b1___8 = 145,\n\tmsm_mux_rgmii_mdio = 146,\n\tmsm_mux_hdmi_lbk1 = 147,\n\tmsm_mux_rgmii_mdc = 148,\n\tmsm_mux_hdmi_lbk0 = 149,\n\tmsm_mux_ir_in = 150,\n\tmsm_mux_wsa_en___3 = 151,\n\tmsm_mux_rgb_data6 = 152,\n\tmsm_mux_rgb_data7 = 153,\n\tmsm_mux_atest_char2___9 = 154,\n\tmsm_mux_ebi_ch0___2 = 155,\n\tmsm_mux_blsp_uart3___3 = 156,\n\tmsm_mux_blsp_spi3___7 = 157,\n\tmsm_mux_sd_write___9 = 158,\n\tmsm_mux_blsp_i2c3___7 = 159,\n\tmsm_mux_gcc_gp1_clk_a___6 = 160,\n\tmsm_mux_qdss_cti_trig_in_b1___8 = 161,\n\tmsm_mux_gcc_gp2_clk_a___6 = 162,\n\tmsm_mux_ext_mclk0 = 163,\n\tmsm_mux_mclk_in1 = 164,\n\tmsm_mux_i2s_1 = 165,\n\tmsm_mux_dsd_clk_a = 166,\n\tmsm_mux_qdss_cti_trig_in_a1___8 = 167,\n\tmsm_mux_rgmi_dll1 = 168,\n\tmsm_mux_pwm_led22 = 169,\n\tmsm_mux_pwm_led23 = 170,\n\tmsm_mux_qdss_cti_trig_out_a0___8 = 171,\n\tmsm_mux_rgmi_dll2 = 172,\n\tmsm_mux_pwm_led1 = 173,\n\tmsm_mux_qdss_cti_trig_out_a1___8 = 174,\n\tmsm_mux_pwm_led2 = 175,\n\tmsm_mux_i2s_2 = 176,\n\tmsm_mux_pll_bist___2 = 177,\n\tmsm_mux_ext_mclk1_a = 178,\n\tmsm_mux_mclk_in2 = 179,\n\tmsm_mux_bimc_dte1___5 = 180,\n\tmsm_mux_i2s_3_sck_a = 181,\n\tmsm_mux_i2s_3_ws_a = 182,\n\tmsm_mux_____11 = 183,\n};\n\nenum qcs615_functions {\n\tmsm_mux_gpio___17 = 0,\n\tmsm_mux_adsp_ext___7 = 1,\n\tmsm_mux_agera_pll___3 = 2,\n\tmsm_mux_aoss_cti___3 = 3,\n\tmsm_mux_atest_char___14 = 4,\n\tmsm_mux_atest_tsens___5 = 5,\n\tmsm_mux_atest_usb___3 = 6,\n\tmsm_mux_cam_mclk___8 = 7,\n\tmsm_mux_cci_async___6 = 8,\n\tmsm_mux_cci_i2c___6 = 9,\n\tmsm_mux_cci_timer___3 = 10,\n\tmsm_mux_copy_gp = 11,\n\tmsm_mux_copy_phase = 12,\n\tmsm_mux_cri_trng___9 = 13,\n\tmsm_mux_dbg_out_clk___3 = 14,\n\tmsm_mux_ddr_bist___5 = 15,\n\tmsm_mux_ddr_pxi = 16,\n\tmsm_mux_dp_hot___2 = 17,\n\tmsm_mux_edp_hot___3 = 18,\n\tmsm_mux_edp_lcd___3 = 19,\n\tmsm_mux_emac_gcc = 20,\n\tmsm_mux_emac_phy_intr = 21,\n\tmsm_mux_forced_usb = 22,\n\tmsm_mux_gcc_gp = 23,\n\tmsm_mux_gp_pdm = 24,\n\tmsm_mux_gps_tx___2 = 25,\n\tmsm_mux_hs0_mi2s = 26,\n\tmsm_mux_hs1_mi2s = 27,\n\tmsm_mux_jitter_bist___5 = 28,\n\tmsm_mux_ldo_en___7 = 29,\n\tmsm_mux_ldo_update___7 = 30,\n\tmsm_mux_m_voc___8 = 31,\n\tmsm_mux_mclk1 = 32,\n\tmsm_mux_mclk2 = 33,\n\tmsm_mux_mdp_vsync___10 = 34,\n\tmsm_mux_mdp_vsync0_out___3 = 35,\n\tmsm_mux_mdp_vsync1_out___3 = 36,\n\tmsm_mux_mdp_vsync2_out___3 = 37,\n\tmsm_mux_mdp_vsync3_out___3 = 38,\n\tmsm_mux_mdp_vsync4_out = 39,\n\tmsm_mux_mdp_vsync5_out___2 = 40,\n\tmsm_mux_mi2s_1 = 41,\n\tmsm_mux_mss_lte___6 = 42,\n\tmsm_mux_nav_pps_in = 43,\n\tmsm_mux_nav_pps_out = 44,\n\tmsm_mux_pa_indicator_or = 45,\n\tmsm_mux_pcie_clk_req = 46,\n\tmsm_mux_pcie_ep_rst = 47,\n\tmsm_mux_phase_flag___5 = 48,\n\tmsm_mux_pll_bist___3 = 49,\n\tmsm_mux_pll_bypassnl___4 = 50,\n\tmsm_mux_pll_reset_n = 51,\n\tmsm_mux_prng_rosc___10 = 52,\n\tmsm_mux_qdss_cti___5 = 53,\n\tmsm_mux_qdss_gpio___3 = 54,\n\tmsm_mux_qlink_enable___2 = 55,\n\tmsm_mux_qlink_request___2 = 56,\n\tmsm_mux_qspi = 57,\n\tmsm_mux_qup0___2 = 58,\n\tmsm_mux_qup1___2 = 59,\n\tmsm_mux_rgmii = 60,\n\tmsm_mux_sd_write_protect___3 = 61,\n\tmsm_mux_sp_cmu___2 = 62,\n\tmsm_mux_ter_mi2s___4 = 63,\n\tmsm_mux_tgu_ch = 64,\n\tmsm_mux_uim1___4 = 65,\n\tmsm_mux_uim2___4 = 66,\n\tmsm_mux_usb0_hs___3 = 67,\n\tmsm_mux_usb1_hs = 68,\n\tmsm_mux_usb_phy_ps = 69,\n\tmsm_mux_vfr_1___6 = 70,\n\tmsm_mux_vsense_trigger_mirnat___3 = 71,\n\tmsm_mux_wlan = 72,\n\tmsm_mux_wsa_clk = 73,\n\tmsm_mux_wsa_data = 74,\n\tmsm_mux_____12 = 75,\n};\n\nenum qcs8300_functions {\n\tmsm_mux_gpio___18 = 0,\n\tmsm_mux_aoss_cti___4 = 1,\n\tmsm_mux_atest_char___15 = 2,\n\tmsm_mux_atest_usb2___2 = 3,\n\tmsm_mux_audio_ref___3 = 4,\n\tmsm_mux_cam_mclk___9 = 5,\n\tmsm_mux_cci_async___7 = 6,\n\tmsm_mux_cci_i2c_scl___3 = 7,\n\tmsm_mux_cci_i2c_sda___3 = 8,\n\tmsm_mux_cci_timer___4 = 9,\n\tmsm_mux_cri_trng___10 = 10,\n\tmsm_mux_dbg_out___13 = 11,\n\tmsm_mux_ddr_bist___6 = 12,\n\tmsm_mux_ddr_pxi0___4 = 13,\n\tmsm_mux_ddr_pxi1___4 = 14,\n\tmsm_mux_ddr_pxi2___3 = 15,\n\tmsm_mux_ddr_pxi3___3 = 16,\n\tmsm_mux_edp0_hot = 17,\n\tmsm_mux_edp0_lcd = 18,\n\tmsm_mux_edp1_lcd = 19,\n\tmsm_mux_egpio___4 = 20,\n\tmsm_mux_emac0_mcg0 = 21,\n\tmsm_mux_emac0_mcg1 = 22,\n\tmsm_mux_emac0_mcg2 = 23,\n\tmsm_mux_emac0_mcg3 = 24,\n\tmsm_mux_emac0_mdc = 25,\n\tmsm_mux_emac0_mdio = 26,\n\tmsm_mux_emac0_ptp_aux = 27,\n\tmsm_mux_emac0_ptp_pps = 28,\n\tmsm_mux_gcc_gp1___4 = 29,\n\tmsm_mux_gcc_gp2___4 = 30,\n\tmsm_mux_gcc_gp3___4 = 31,\n\tmsm_mux_gcc_gp4 = 32,\n\tmsm_mux_gcc_gp5 = 33,\n\tmsm_mux_hs0_mi2s___2 = 34,\n\tmsm_mux_hs1_mi2s___2 = 35,\n\tmsm_mux_hs2_mi2s = 36,\n\tmsm_mux_ibi_i3c___3 = 37,\n\tmsm_mux_jitter_bist___6 = 38,\n\tmsm_mux_mdp0_vsync0 = 39,\n\tmsm_mux_mdp0_vsync1 = 40,\n\tmsm_mux_mdp0_vsync3 = 41,\n\tmsm_mux_mdp0_vsync6 = 42,\n\tmsm_mux_mdp0_vsync7 = 43,\n\tmsm_mux_mdp_vsync___11 = 44,\n\tmsm_mux_mi2s1_data0 = 45,\n\tmsm_mux_mi2s1_data1 = 46,\n\tmsm_mux_mi2s1_sck = 47,\n\tmsm_mux_mi2s1_ws = 48,\n\tmsm_mux_mi2s2_data0 = 49,\n\tmsm_mux_mi2s2_data1 = 50,\n\tmsm_mux_mi2s2_sck = 51,\n\tmsm_mux_mi2s2_ws = 52,\n\tmsm_mux_mi2s_mclk0 = 53,\n\tmsm_mux_mi2s_mclk1 = 54,\n\tmsm_mux_pcie0_clkreq = 55,\n\tmsm_mux_pcie1_clkreq = 56,\n\tmsm_mux_phase_flag___6 = 57,\n\tmsm_mux_pll_bist___4 = 58,\n\tmsm_mux_pll_clk = 59,\n\tmsm_mux_prng_rosc0___6 = 60,\n\tmsm_mux_prng_rosc1___6 = 61,\n\tmsm_mux_prng_rosc2___6 = 62,\n\tmsm_mux_prng_rosc3___6 = 63,\n\tmsm_mux_qdss_cti___6 = 64,\n\tmsm_mux_qdss_gpio___4 = 65,\n\tmsm_mux_qup0_se0___2 = 66,\n\tmsm_mux_qup0_se1___2 = 67,\n\tmsm_mux_qup0_se2___2 = 68,\n\tmsm_mux_qup0_se3___2 = 69,\n\tmsm_mux_qup0_se4___2 = 70,\n\tmsm_mux_qup0_se5___2 = 71,\n\tmsm_mux_qup0_se6___2 = 72,\n\tmsm_mux_qup0_se7 = 73,\n\tmsm_mux_qup1_se0___3 = 74,\n\tmsm_mux_qup1_se1___3 = 75,\n\tmsm_mux_qup1_se2___3 = 76,\n\tmsm_mux_qup1_se3___3 = 77,\n\tmsm_mux_qup1_se4___3 = 78,\n\tmsm_mux_qup1_se5___3 = 79,\n\tmsm_mux_qup1_se6___3 = 80,\n\tmsm_mux_qup1_se7___2 = 81,\n\tmsm_mux_qup2_se0___2 = 82,\n\tmsm_mux_sailss_emac0 = 83,\n\tmsm_mux_sailss_ospi = 84,\n\tmsm_mux_sgmii_phy = 85,\n\tmsm_mux_tb_trig = 86,\n\tmsm_mux_tgu_ch0___3 = 87,\n\tmsm_mux_tgu_ch1___3 = 88,\n\tmsm_mux_tgu_ch2___2 = 89,\n\tmsm_mux_tgu_ch3___2 = 90,\n\tmsm_mux_tsense_pwm1___5 = 91,\n\tmsm_mux_tsense_pwm2___5 = 92,\n\tmsm_mux_tsense_pwm3___2 = 93,\n\tmsm_mux_tsense_pwm4___2 = 94,\n\tmsm_mux_usb2phy_ac = 95,\n\tmsm_mux_vsense_trigger___2 = 96,\n\tmsm_mux_____13 = 97,\n};\n\nenum qdisc_class_ops_flags {\n\tQDISC_CLASS_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum qdu1000_functions {\n\tmsm_mux_gpio___19 = 0,\n\tmsm_mux_cmo_pri = 1,\n\tmsm_mux_si5518_int = 2,\n\tmsm_mux_atest_char___16 = 3,\n\tmsm_mux_atest_usb___4 = 4,\n\tmsm_mux_char_exec___2 = 5,\n\tmsm_mux_cmu_rng___2 = 6,\n\tmsm_mux_dbg_out_clk___4 = 7,\n\tmsm_mux_ddr_bist___7 = 8,\n\tmsm_mux_ddr_pxi0___5 = 9,\n\tmsm_mux_ddr_pxi1___5 = 10,\n\tmsm_mux_ddr_pxi2___4 = 11,\n\tmsm_mux_ddr_pxi3___4 = 12,\n\tmsm_mux_ddr_pxi4 = 13,\n\tmsm_mux_ddr_pxi5 = 14,\n\tmsm_mux_ddr_pxi6 = 15,\n\tmsm_mux_ddr_pxi7 = 16,\n\tmsm_mux_eth012_int_n = 17,\n\tmsm_mux_eth345_int_n = 18,\n\tmsm_mux_eth6_int_n = 19,\n\tmsm_mux_gcc_gp1___5 = 20,\n\tmsm_mux_gcc_gp2___5 = 21,\n\tmsm_mux_gcc_gp3___5 = 22,\n\tmsm_mux_gps_pps_in = 23,\n\tmsm_mux_hardsync_pps_in = 24,\n\tmsm_mux_intr_c = 25,\n\tmsm_mux_jitter_bist_ref = 26,\n\tmsm_mux_pcie_clkreqn = 27,\n\tmsm_mux_phase_flag___7 = 28,\n\tmsm_mux_pll_bist___5 = 29,\n\tmsm_mux_pll_clk___2 = 30,\n\tmsm_mux_prng_rosc___11 = 31,\n\tmsm_mux_qdss_cti___7 = 32,\n\tmsm_mux_qdss_gpio___5 = 33,\n\tmsm_mux_qlink0_enable___2 = 34,\n\tmsm_mux_qlink0_request___2 = 35,\n\tmsm_mux_qlink0_wmss___2 = 36,\n\tmsm_mux_qlink1_enable___2 = 37,\n\tmsm_mux_qlink1_request___2 = 38,\n\tmsm_mux_qlink1_wmss___2 = 39,\n\tmsm_mux_qlink2_enable = 40,\n\tmsm_mux_qlink2_request = 41,\n\tmsm_mux_qlink2_wmss = 42,\n\tmsm_mux_qlink3_enable = 43,\n\tmsm_mux_qlink3_request = 44,\n\tmsm_mux_qlink3_wmss = 45,\n\tmsm_mux_qlink4_enable = 46,\n\tmsm_mux_qlink4_request = 47,\n\tmsm_mux_qlink4_wmss = 48,\n\tmsm_mux_qlink5_enable = 49,\n\tmsm_mux_qlink5_request = 50,\n\tmsm_mux_qlink5_wmss = 51,\n\tmsm_mux_qlink6_enable = 52,\n\tmsm_mux_qlink6_request = 53,\n\tmsm_mux_qlink6_wmss = 54,\n\tmsm_mux_qlink7_enable = 55,\n\tmsm_mux_qlink7_request = 56,\n\tmsm_mux_qlink7_wmss = 57,\n\tmsm_mux_qspi_clk___7 = 58,\n\tmsm_mux_qspi_cs___7 = 59,\n\tmsm_mux_qspi0___4 = 60,\n\tmsm_mux_qspi1___3 = 61,\n\tmsm_mux_qspi2___3 = 62,\n\tmsm_mux_qspi3___3 = 63,\n\tmsm_mux_qup00 = 64,\n\tmsm_mux_qup01 = 65,\n\tmsm_mux_qup02 = 66,\n\tmsm_mux_qup03 = 67,\n\tmsm_mux_qup04 = 68,\n\tmsm_mux_qup05 = 69,\n\tmsm_mux_qup06 = 70,\n\tmsm_mux_qup07 = 71,\n\tmsm_mux_qup08 = 72,\n\tmsm_mux_qup10 = 73,\n\tmsm_mux_qup11 = 74,\n\tmsm_mux_qup12 = 75,\n\tmsm_mux_qup13 = 76,\n\tmsm_mux_qup14 = 77,\n\tmsm_mux_qup15 = 78,\n\tmsm_mux_qup16 = 79,\n\tmsm_mux_qup17 = 80,\n\tmsm_mux_qup20 = 81,\n\tmsm_mux_qup21 = 82,\n\tmsm_mux_qup22 = 83,\n\tmsm_mux_smb_alert = 84,\n\tmsm_mux_smb_clk = 85,\n\tmsm_mux_smb_dat = 86,\n\tmsm_mux_tb_trig___2 = 87,\n\tmsm_mux_tgu_ch0___4 = 88,\n\tmsm_mux_tgu_ch1___4 = 89,\n\tmsm_mux_tgu_ch2___3 = 90,\n\tmsm_mux_tgu_ch3___3 = 91,\n\tmsm_mux_tgu_ch4 = 92,\n\tmsm_mux_tgu_ch5 = 93,\n\tmsm_mux_tgu_ch6 = 94,\n\tmsm_mux_tgu_ch7 = 95,\n\tmsm_mux_tmess_prng0___3 = 96,\n\tmsm_mux_tmess_prng1___3 = 97,\n\tmsm_mux_tmess_prng2___3 = 98,\n\tmsm_mux_tmess_prng3___3 = 99,\n\tmsm_mux_tod_pps_in = 100,\n\tmsm_mux_tsense_pwm1___6 = 101,\n\tmsm_mux_tsense_pwm2___6 = 102,\n\tmsm_mux_usb2phy_ac___2 = 103,\n\tmsm_mux_usb_con_det = 104,\n\tmsm_mux_usb_dfp_en = 105,\n\tmsm_mux_usb_phy___4 = 106,\n\tmsm_mux_vfr_0___3 = 107,\n\tmsm_mux_vfr_1___7 = 108,\n\tmsm_mux_vsense_trigger___3 = 109,\n\tmsm_mux_____14 = 110,\n};\n\nenum qm_dc_portal {\n\tqm_dc_portal_fman0 = 0,\n\tqm_dc_portal_fman1 = 1,\n};\n\nenum qm_dqrr_cmode {\n\tqm_dqrr_cci = 0,\n\tqm_dqrr_cce = 1,\n\tqm_dqrr_cdc = 2,\n};\n\nenum qm_dqrr_dmode {\n\tqm_dqrr_dpush = 0,\n\tqm_dqrr_dpull = 1,\n};\n\nenum qm_dqrr_pmode {\n\tqm_dqrr_pci = 0,\n\tqm_dqrr_pce = 1,\n\tqm_dqrr_pvb = 2,\n};\n\nenum qm_eqcr_pmode {\n\tqm_eqcr_pci = 0,\n\tqm_eqcr_pce = 1,\n\tqm_eqcr_pvb = 2,\n};\n\nenum qm_fd_format {\n\tqm_fd_contig = 0,\n\tqm_fd_contig_big = 1073741824,\n\tqm_fd_sg = 2147483648,\n\tqm_fd_sg_big = 3221225472,\n\tqm_fd_compound = 536870912,\n};\n\nenum qm_memory {\n\tqm_memory_fqd = 0,\n\tqm_memory_pfdr = 1,\n};\n\nenum qm_mr_cmode {\n\tqm_mr_cci = 0,\n\tqm_mr_cce = 1,\n};\n\nenum qm_mr_pmode {\n\tqm_mr_pci = 0,\n\tqm_mr_pce = 1,\n\tqm_mr_pvb = 2,\n};\n\nenum qm_wq_class {\n\tqm_wq_portal = 0,\n\tqm_wq_pool = 1,\n\tqm_wq_fman0 = 2,\n\tqm_wq_fman1 = 3,\n\tqm_wq_caam = 4,\n\tqm_wq_pme = 5,\n\tqm_wq_first = 0,\n\tqm_wq_last = 5,\n};\n\nenum qman_cb_dqrr_result {\n\tqman_cb_dqrr_consume = 0,\n\tqman_cb_dqrr_park = 1,\n\tqman_cb_dqrr_defer = 2,\n\tqman_cb_dqrr_stop = 3,\n\tqman_cb_dqrr_consume_stop = 4,\n};\n\nenum qman_fq_state {\n\tqman_fq_state_oos = 0,\n\tqman_fq_state_parked = 1,\n\tqman_fq_state_sched = 2,\n\tqman_fq_state_retired = 3,\n};\n\nenum qos_mode {\n\tNOC_QOS_MODE_INVALID = 0,\n\tNOC_QOS_MODE_FIXED = 1,\n\tNOC_QOS_MODE_BYPASS = 2,\n};\n\nenum qpnpint_regs {\n\tQPNPINT_REG_RT_STS = 16,\n\tQPNPINT_REG_SET_TYPE = 17,\n\tQPNPINT_REG_POLARITY_HIGH = 18,\n\tQPNPINT_REG_POLARITY_LOW = 19,\n\tQPNPINT_REG_LATCHED_CLR = 20,\n\tQPNPINT_REG_EN_SET = 21,\n\tQPNPINT_REG_EN_CLR = 22,\n\tQPNPINT_REG_LATCHED_STS = 24,\n};\n\nenum query_opcode {\n\tUPIU_QUERY_OPCODE_NOP = 0,\n\tUPIU_QUERY_OPCODE_READ_DESC = 1,\n\tUPIU_QUERY_OPCODE_WRITE_DESC = 2,\n\tUPIU_QUERY_OPCODE_READ_ATTR = 3,\n\tUPIU_QUERY_OPCODE_WRITE_ATTR = 4,\n\tUPIU_QUERY_OPCODE_READ_FLAG = 5,\n\tUPIU_QUERY_OPCODE_SET_FLAG = 6,\n\tUPIU_QUERY_OPCODE_CLEAR_FLAG = 7,\n\tUPIU_QUERY_OPCODE_TOGGLE_FLAG = 8,\n};\n\nenum queue_mode {\n\tQUEUE_MODE_STRICT_PRIORITY = 0,\n\tQUEUE_MODE_STREAM_RESERVATION = 1,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum r8a77970_clk_types {\n\tCLK_TYPE_R8A77970_SD0H = 23,\n\tCLK_TYPE_R8A77970_SD0 = 24,\n};\n\nenum ramfs_param {\n\tOpt_mode___5 = 0,\n};\n\nenum ravb_reg {\n\tCCC = 0,\n\tDBAT = 4,\n\tDLR = 8,\n\tCSR = 12,\n\tCDAR0 = 16,\n\tCDAR1 = 20,\n\tCDAR2 = 24,\n\tCDAR3 = 28,\n\tCDAR4 = 32,\n\tCDAR5 = 36,\n\tCDAR6 = 40,\n\tCDAR7 = 44,\n\tCDAR8 = 48,\n\tCDAR9 = 52,\n\tCDAR10 = 56,\n\tCDAR11 = 60,\n\tCDAR12 = 64,\n\tCDAR13 = 68,\n\tCDAR14 = 72,\n\tCDAR15 = 76,\n\tCDAR16 = 80,\n\tCDAR17 = 84,\n\tCDAR18 = 88,\n\tCDAR19 = 92,\n\tCDAR20 = 96,\n\tCDAR21 = 100,\n\tESR = 136,\n\tAPSR = 140,\n\tRCR = 144,\n\tRQC0 = 148,\n\tRQC1 = 152,\n\tRQC2 = 156,\n\tRQC3 = 160,\n\tRQC4 = 164,\n\tRPC = 176,\n\tRTC = 180,\n\tUFCW = 188,\n\tUFCS = 192,\n\tUFCV0 = 196,\n\tUFCV1 = 200,\n\tUFCV2 = 204,\n\tUFCV3 = 208,\n\tUFCV4 = 212,\n\tUFCD0 = 224,\n\tUFCD1 = 228,\n\tUFCD2 = 232,\n\tUFCD3 = 236,\n\tUFCD4 = 240,\n\tSFO = 252,\n\tSFP0 = 256,\n\tSFP1 = 260,\n\tSFP2 = 264,\n\tSFP3 = 268,\n\tSFP4 = 272,\n\tSFP5 = 276,\n\tSFP6 = 280,\n\tSFP7 = 284,\n\tSFP8 = 288,\n\tSFP9 = 292,\n\tSFP10 = 296,\n\tSFP11 = 300,\n\tSFP12 = 304,\n\tSFP13 = 308,\n\tSFP14 = 312,\n\tSFP15 = 316,\n\tSFP16 = 320,\n\tSFP17 = 324,\n\tSFP18 = 328,\n\tSFP19 = 332,\n\tSFP20 = 336,\n\tSFP21 = 340,\n\tSFP22 = 344,\n\tSFP23 = 348,\n\tSFP24 = 352,\n\tSFP25 = 356,\n\tSFP26 = 360,\n\tSFP27 = 364,\n\tSFP28 = 368,\n\tSFP29 = 372,\n\tSFP30 = 376,\n\tSFP31 = 380,\n\tSFM0 = 448,\n\tSFM1 = 452,\n\tTGC = 768,\n\tTCCR = 772,\n\tTSR = 776,\n\tTFA0 = 784,\n\tTFA1 = 788,\n\tTFA2 = 792,\n\tCIVR0 = 800,\n\tCIVR1 = 804,\n\tCDVR0 = 808,\n\tCDVR1 = 812,\n\tCUL0 = 816,\n\tCUL1 = 820,\n\tCLL0 = 824,\n\tCLL1 = 828,\n\tDIC = 848,\n\tDIS = 852,\n\tEIC = 856,\n\tEIS = 860,\n\tRIC0 = 864,\n\tRIS0 = 868,\n\tRIC1 = 872,\n\tRIS1 = 876,\n\tRIC2 = 880,\n\tRIS2 = 884,\n\tTIC = 888,\n\tTIS = 892,\n\tISS = 896,\n\tCIE = 900,\n\tGCCR = 912,\n\tGMTT = 916,\n\tGPTC = 920,\n\tGTI = 924,\n\tGTO0 = 928,\n\tGTO1 = 932,\n\tGTO2 = 936,\n\tGIC = 940,\n\tGIS = 944,\n\tGCPT = 948,\n\tGCT0 = 952,\n\tGCT1 = 956,\n\tGCT2 = 960,\n\tGIE = 972,\n\tGID = 976,\n\tDIL = 1088,\n\tRIE0 = 1120,\n\tRID0 = 1124,\n\tRIE2 = 1136,\n\tRID2 = 1140,\n\tTIE = 1144,\n\tTID = 1148,\n\tECMR___2 = 1280,\n\tRFLR___2 = 1288,\n\tECSR___2 = 1296,\n\tECSIPR___2 = 1304,\n\tPIR___2 = 1312,\n\tPSR___2 = 1320,\n\tPIPR___2 = 1324,\n\tCXR31 = 1328,\n\tCXR35 = 1344,\n\tMPR___2 = 1368,\n\tPFTCR___2 = 1372,\n\tPFRCR___2 = 1376,\n\tGECMR___2 = 1456,\n\tMAHR___2 = 1472,\n\tMALR___2 = 1480,\n\tTROCR___2 = 1792,\n\tCXR41 = 1800,\n\tCXR42 = 1808,\n\tCEFCR___2 = 1856,\n\tFRECR___2 = 1864,\n\tTSFRCR___2 = 1872,\n\tTLFRCR___2 = 1880,\n\tRFCR___2 = 1888,\n\tMAFCR___2 = 1912,\n\tCSR0 = 2048,\n\tCSR1 = 2052,\n\tCSR2 = 2056,\n};\n\nenum rcar_gen3_clk_types {\n\tCLK_TYPE_GEN3_MAIN = 5,\n\tCLK_TYPE_GEN3_PLL0 = 6,\n\tCLK_TYPE_GEN3_PLL1 = 7,\n\tCLK_TYPE_GEN3_PLL2 = 8,\n\tCLK_TYPE_GEN3_PLL3 = 9,\n\tCLK_TYPE_GEN3_PLL4 = 10,\n\tCLK_TYPE_GEN3_SDH = 11,\n\tCLK_TYPE_GEN3_SD = 12,\n\tCLK_TYPE_GEN3_R = 13,\n\tCLK_TYPE_GEN3_MDSEL = 14,\n\tCLK_TYPE_GEN3_Z = 15,\n\tCLK_TYPE_GEN3_ZG = 16,\n\tCLK_TYPE_GEN3_OSC = 17,\n\tCLK_TYPE_GEN3_RCKSEL = 18,\n\tCLK_TYPE_GEN3_RPCSRC = 19,\n\tCLK_TYPE_GEN3_E3_RPCSRC = 20,\n\tCLK_TYPE_GEN3_RPC = 21,\n\tCLK_TYPE_GEN3_RPCD2 = 22,\n\tCLK_TYPE_GEN3_SOC_BASE = 23,\n};\n\nenum rcar_gen3_phy_index {\n\tPHY_INDEX_BOTH_HC = 0,\n\tPHY_INDEX_OHCI = 1,\n\tPHY_INDEX_EHCI = 2,\n\tPHY_INDEX_HSUSB = 3,\n};\n\nenum rcar_gen4_clk_types {\n\tCLK_TYPE_GEN4_MAIN = 5,\n\tCLK_TYPE_GEN4_PLL1 = 6,\n\tCLK_TYPE_GEN4_PLL2X_3X = 7,\n\tCLK_TYPE_GEN4_PLL5 = 8,\n\tCLK_TYPE_GEN4_PLL_F8_25 = 9,\n\tCLK_TYPE_GEN4_PLL_V8_25 = 10,\n\tCLK_TYPE_GEN4_PLL_F9_24 = 11,\n\tCLK_TYPE_GEN4_PLL_V9_24 = 12,\n\tCLK_TYPE_GEN4_SDSRC = 13,\n\tCLK_TYPE_GEN4_SDH = 14,\n\tCLK_TYPE_GEN4_SD = 15,\n\tCLK_TYPE_GEN4_MDSEL = 16,\n\tCLK_TYPE_GEN4_Z = 17,\n\tCLK_TYPE_GEN4_OSC = 18,\n\tCLK_TYPE_GEN4_RPCSRC = 19,\n\tCLK_TYPE_GEN4_RPC = 20,\n\tCLK_TYPE_GEN4_RPCD2 = 21,\n\tCLK_TYPE_GEN4_SOC_BASE = 22,\n};\n\nenum rcar_i2c_type {\n\tI2C_RCAR_GEN1 = 0,\n\tI2C_RCAR_GEN2 = 1,\n\tI2C_RCAR_GEN3 = 2,\n\tI2C_RCAR_GEN4 = 3,\n};\n\nenum rcb_int_flag {\n\tRCB_INT_FLAG_TX = 1,\n\tRCB_INT_FLAG_RX = 2,\n\tRCB_INT_FLAG_MAX = 4,\n};\n\nenum rdma_ah_attr_type {\n\tRDMA_AH_ATTR_TYPE_UNDEFINED = 0,\n\tRDMA_AH_ATTR_TYPE_IB = 1,\n\tRDMA_AH_ATTR_TYPE_ROCE = 2,\n\tRDMA_AH_ATTR_TYPE_OPA = 3,\n};\n\nenum rdma_driver_id {\n\tRDMA_DRIVER_UNKNOWN = 0,\n\tRDMA_DRIVER_MLX5 = 1,\n\tRDMA_DRIVER_MLX4 = 2,\n\tRDMA_DRIVER_CXGB3 = 3,\n\tRDMA_DRIVER_CXGB4 = 4,\n\tRDMA_DRIVER_MTHCA = 5,\n\tRDMA_DRIVER_BNXT_RE = 6,\n\tRDMA_DRIVER_OCRDMA = 7,\n\tRDMA_DRIVER_NES = 8,\n\tRDMA_DRIVER_I40IW = 9,\n\tRDMA_DRIVER_IRDMA = 9,\n\tRDMA_DRIVER_VMW_PVRDMA = 10,\n\tRDMA_DRIVER_QEDR = 11,\n\tRDMA_DRIVER_HNS = 12,\n\tRDMA_DRIVER_USNIC = 13,\n\tRDMA_DRIVER_RXE = 14,\n\tRDMA_DRIVER_HFI1 = 15,\n\tRDMA_DRIVER_QIB = 16,\n\tRDMA_DRIVER_EFA = 17,\n\tRDMA_DRIVER_SIW = 18,\n\tRDMA_DRIVER_ERDMA = 19,\n\tRDMA_DRIVER_MANA = 20,\n\tRDMA_DRIVER_IONIC = 21,\n};\n\nenum rdma_link_layer {\n\tIB_LINK_LAYER_UNSPECIFIED = 0,\n\tIB_LINK_LAYER_INFINIBAND = 1,\n\tIB_LINK_LAYER_ETHERNET = 2,\n};\n\nenum rdma_netdev_t {\n\tRDMA_NETDEV_OPA_VNIC = 0,\n\tRDMA_NETDEV_IPOIB = 1,\n};\n\nenum rdma_nl_counter_mask {\n\tRDMA_COUNTER_MASK_QP_TYPE = 1,\n\tRDMA_COUNTER_MASK_PID = 2,\n};\n\nenum rdma_nl_counter_mode {\n\tRDMA_COUNTER_MODE_NONE = 0,\n\tRDMA_COUNTER_MODE_AUTO = 1,\n\tRDMA_COUNTER_MODE_MANUAL = 2,\n\tRDMA_COUNTER_MODE_MAX = 3,\n};\n\nenum rdma_nl_dev_type {\n\tRDMA_DEVICE_TYPE_SMI = 1,\n};\n\nenum rdma_nl_name_assign_type {\n\tRDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0,\n\tRDMA_NAME_ASSIGN_TYPE_USER = 1,\n};\n\nenum rdma_restrack_type {\n\tRDMA_RESTRACK_PD = 0,\n\tRDMA_RESTRACK_CQ = 1,\n\tRDMA_RESTRACK_QP = 2,\n\tRDMA_RESTRACK_CM_ID = 3,\n\tRDMA_RESTRACK_MR = 4,\n\tRDMA_RESTRACK_CTX = 5,\n\tRDMA_RESTRACK_COUNTER = 6,\n\tRDMA_RESTRACK_SRQ = 7,\n\tRDMA_RESTRACK_DMAH = 8,\n\tRDMA_RESTRACK_MAX = 9,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_FLAT = 2,\n\tREGCACHE_MAPLE = 3,\n\tREGCACHE_FLAT_S = 4,\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum regfield_ids {\n\tVER_MAJOR = 0,\n\tVER_MINOR = 1,\n\tVER_STEP = 2,\n\tTSENS_EN = 3,\n\tTSENS_SW_RST = 4,\n\tSENSOR_EN = 5,\n\tCODE_OR_TEMP = 6,\n\tMAIN_MEASURE_PERIOD = 7,\n\tTRDY = 8,\n\tINT_EN = 9,\n\tLAST_TEMP_0 = 10,\n\tLAST_TEMP_1 = 11,\n\tLAST_TEMP_2 = 12,\n\tLAST_TEMP_3 = 13,\n\tLAST_TEMP_4 = 14,\n\tLAST_TEMP_5 = 15,\n\tLAST_TEMP_6 = 16,\n\tLAST_TEMP_7 = 17,\n\tLAST_TEMP_8 = 18,\n\tLAST_TEMP_9 = 19,\n\tLAST_TEMP_10 = 20,\n\tLAST_TEMP_11 = 21,\n\tLAST_TEMP_12 = 22,\n\tLAST_TEMP_13 = 23,\n\tLAST_TEMP_14 = 24,\n\tLAST_TEMP_15 = 25,\n\tVALID_0 = 26,\n\tVALID_1 = 27,\n\tVALID_2 = 28,\n\tVALID_3 = 29,\n\tVALID_4 = 30,\n\tVALID_5 = 31,\n\tVALID_6 = 32,\n\tVALID_7 = 33,\n\tVALID_8 = 34,\n\tVALID_9 = 35,\n\tVALID_10 = 36,\n\tVALID_11 = 37,\n\tVALID_12 = 38,\n\tVALID_13 = 39,\n\tVALID_14 = 40,\n\tVALID_15 = 41,\n\tLOWER_STATUS_0 = 42,\n\tLOWER_STATUS_1 = 43,\n\tLOWER_STATUS_2 = 44,\n\tLOWER_STATUS_3 = 45,\n\tLOWER_STATUS_4 = 46,\n\tLOWER_STATUS_5 = 47,\n\tLOWER_STATUS_6 = 48,\n\tLOWER_STATUS_7 = 49,\n\tLOWER_STATUS_8 = 50,\n\tLOWER_STATUS_9 = 51,\n\tLOWER_STATUS_10 = 52,\n\tLOWER_STATUS_11 = 53,\n\tLOWER_STATUS_12 = 54,\n\tLOWER_STATUS_13 = 55,\n\tLOWER_STATUS_14 = 56,\n\tLOWER_STATUS_15 = 57,\n\tLOW_INT_STATUS_0 = 58,\n\tLOW_INT_STATUS_1 = 59,\n\tLOW_INT_STATUS_2 = 60,\n\tLOW_INT_STATUS_3 = 61,\n\tLOW_INT_STATUS_4 = 62,\n\tLOW_INT_STATUS_5 = 63,\n\tLOW_INT_STATUS_6 = 64,\n\tLOW_INT_STATUS_7 = 65,\n\tLOW_INT_STATUS_8 = 66,\n\tLOW_INT_STATUS_9 = 67,\n\tLOW_INT_STATUS_10 = 68,\n\tLOW_INT_STATUS_11 = 69,\n\tLOW_INT_STATUS_12 = 70,\n\tLOW_INT_STATUS_13 = 71,\n\tLOW_INT_STATUS_14 = 72,\n\tLOW_INT_STATUS_15 = 73,\n\tLOW_INT_CLEAR_0 = 74,\n\tLOW_INT_CLEAR_1 = 75,\n\tLOW_INT_CLEAR_2 = 76,\n\tLOW_INT_CLEAR_3 = 77,\n\tLOW_INT_CLEAR_4 = 78,\n\tLOW_INT_CLEAR_5 = 79,\n\tLOW_INT_CLEAR_6 = 80,\n\tLOW_INT_CLEAR_7 = 81,\n\tLOW_INT_CLEAR_8 = 82,\n\tLOW_INT_CLEAR_9 = 83,\n\tLOW_INT_CLEAR_10 = 84,\n\tLOW_INT_CLEAR_11 = 85,\n\tLOW_INT_CLEAR_12 = 86,\n\tLOW_INT_CLEAR_13 = 87,\n\tLOW_INT_CLEAR_14 = 88,\n\tLOW_INT_CLEAR_15 = 89,\n\tLOW_INT_MASK_0 = 90,\n\tLOW_INT_MASK_1 = 91,\n\tLOW_INT_MASK_2 = 92,\n\tLOW_INT_MASK_3 = 93,\n\tLOW_INT_MASK_4 = 94,\n\tLOW_INT_MASK_5 = 95,\n\tLOW_INT_MASK_6 = 96,\n\tLOW_INT_MASK_7 = 97,\n\tLOW_INT_MASK_8 = 98,\n\tLOW_INT_MASK_9 = 99,\n\tLOW_INT_MASK_10 = 100,\n\tLOW_INT_MASK_11 = 101,\n\tLOW_INT_MASK_12 = 102,\n\tLOW_INT_MASK_13 = 103,\n\tLOW_INT_MASK_14 = 104,\n\tLOW_INT_MASK_15 = 105,\n\tLOW_THRESH_0 = 106,\n\tLOW_THRESH_1 = 107,\n\tLOW_THRESH_2 = 108,\n\tLOW_THRESH_3 = 109,\n\tLOW_THRESH_4 = 110,\n\tLOW_THRESH_5 = 111,\n\tLOW_THRESH_6 = 112,\n\tLOW_THRESH_7 = 113,\n\tLOW_THRESH_8 = 114,\n\tLOW_THRESH_9 = 115,\n\tLOW_THRESH_10 = 116,\n\tLOW_THRESH_11 = 117,\n\tLOW_THRESH_12 = 118,\n\tLOW_THRESH_13 = 119,\n\tLOW_THRESH_14 = 120,\n\tLOW_THRESH_15 = 121,\n\tUPPER_STATUS_0 = 122,\n\tUPPER_STATUS_1 = 123,\n\tUPPER_STATUS_2 = 124,\n\tUPPER_STATUS_3 = 125,\n\tUPPER_STATUS_4 = 126,\n\tUPPER_STATUS_5 = 127,\n\tUPPER_STATUS_6 = 128,\n\tUPPER_STATUS_7 = 129,\n\tUPPER_STATUS_8 = 130,\n\tUPPER_STATUS_9 = 131,\n\tUPPER_STATUS_10 = 132,\n\tUPPER_STATUS_11 = 133,\n\tUPPER_STATUS_12 = 134,\n\tUPPER_STATUS_13 = 135,\n\tUPPER_STATUS_14 = 136,\n\tUPPER_STATUS_15 = 137,\n\tUP_INT_STATUS_0 = 138,\n\tUP_INT_STATUS_1 = 139,\n\tUP_INT_STATUS_2 = 140,\n\tUP_INT_STATUS_3 = 141,\n\tUP_INT_STATUS_4 = 142,\n\tUP_INT_STATUS_5 = 143,\n\tUP_INT_STATUS_6 = 144,\n\tUP_INT_STATUS_7 = 145,\n\tUP_INT_STATUS_8 = 146,\n\tUP_INT_STATUS_9 = 147,\n\tUP_INT_STATUS_10 = 148,\n\tUP_INT_STATUS_11 = 149,\n\tUP_INT_STATUS_12 = 150,\n\tUP_INT_STATUS_13 = 151,\n\tUP_INT_STATUS_14 = 152,\n\tUP_INT_STATUS_15 = 153,\n\tUP_INT_CLEAR_0 = 154,\n\tUP_INT_CLEAR_1 = 155,\n\tUP_INT_CLEAR_2 = 156,\n\tUP_INT_CLEAR_3 = 157,\n\tUP_INT_CLEAR_4 = 158,\n\tUP_INT_CLEAR_5 = 159,\n\tUP_INT_CLEAR_6 = 160,\n\tUP_INT_CLEAR_7 = 161,\n\tUP_INT_CLEAR_8 = 162,\n\tUP_INT_CLEAR_9 = 163,\n\tUP_INT_CLEAR_10 = 164,\n\tUP_INT_CLEAR_11 = 165,\n\tUP_INT_CLEAR_12 = 166,\n\tUP_INT_CLEAR_13 = 167,\n\tUP_INT_CLEAR_14 = 168,\n\tUP_INT_CLEAR_15 = 169,\n\tUP_INT_MASK_0 = 170,\n\tUP_INT_MASK_1 = 171,\n\tUP_INT_MASK_2 = 172,\n\tUP_INT_MASK_3 = 173,\n\tUP_INT_MASK_4 = 174,\n\tUP_INT_MASK_5 = 175,\n\tUP_INT_MASK_6 = 176,\n\tUP_INT_MASK_7 = 177,\n\tUP_INT_MASK_8 = 178,\n\tUP_INT_MASK_9 = 179,\n\tUP_INT_MASK_10 = 180,\n\tUP_INT_MASK_11 = 181,\n\tUP_INT_MASK_12 = 182,\n\tUP_INT_MASK_13 = 183,\n\tUP_INT_MASK_14 = 184,\n\tUP_INT_MASK_15 = 185,\n\tUP_THRESH_0 = 186,\n\tUP_THRESH_1 = 187,\n\tUP_THRESH_2 = 188,\n\tUP_THRESH_3 = 189,\n\tUP_THRESH_4 = 190,\n\tUP_THRESH_5 = 191,\n\tUP_THRESH_6 = 192,\n\tUP_THRESH_7 = 193,\n\tUP_THRESH_8 = 194,\n\tUP_THRESH_9 = 195,\n\tUP_THRESH_10 = 196,\n\tUP_THRESH_11 = 197,\n\tUP_THRESH_12 = 198,\n\tUP_THRESH_13 = 199,\n\tUP_THRESH_14 = 200,\n\tUP_THRESH_15 = 201,\n\tCRITICAL_STATUS_0 = 202,\n\tCRITICAL_STATUS_1 = 203,\n\tCRITICAL_STATUS_2 = 204,\n\tCRITICAL_STATUS_3 = 205,\n\tCRITICAL_STATUS_4 = 206,\n\tCRITICAL_STATUS_5 = 207,\n\tCRITICAL_STATUS_6 = 208,\n\tCRITICAL_STATUS_7 = 209,\n\tCRITICAL_STATUS_8 = 210,\n\tCRITICAL_STATUS_9 = 211,\n\tCRITICAL_STATUS_10 = 212,\n\tCRITICAL_STATUS_11 = 213,\n\tCRITICAL_STATUS_12 = 214,\n\tCRITICAL_STATUS_13 = 215,\n\tCRITICAL_STATUS_14 = 216,\n\tCRITICAL_STATUS_15 = 217,\n\tCRIT_INT_STATUS_0 = 218,\n\tCRIT_INT_STATUS_1 = 219,\n\tCRIT_INT_STATUS_2 = 220,\n\tCRIT_INT_STATUS_3 = 221,\n\tCRIT_INT_STATUS_4 = 222,\n\tCRIT_INT_STATUS_5 = 223,\n\tCRIT_INT_STATUS_6 = 224,\n\tCRIT_INT_STATUS_7 = 225,\n\tCRIT_INT_STATUS_8 = 226,\n\tCRIT_INT_STATUS_9 = 227,\n\tCRIT_INT_STATUS_10 = 228,\n\tCRIT_INT_STATUS_11 = 229,\n\tCRIT_INT_STATUS_12 = 230,\n\tCRIT_INT_STATUS_13 = 231,\n\tCRIT_INT_STATUS_14 = 232,\n\tCRIT_INT_STATUS_15 = 233,\n\tCRIT_INT_CLEAR_0 = 234,\n\tCRIT_INT_CLEAR_1 = 235,\n\tCRIT_INT_CLEAR_2 = 236,\n\tCRIT_INT_CLEAR_3 = 237,\n\tCRIT_INT_CLEAR_4 = 238,\n\tCRIT_INT_CLEAR_5 = 239,\n\tCRIT_INT_CLEAR_6 = 240,\n\tCRIT_INT_CLEAR_7 = 241,\n\tCRIT_INT_CLEAR_8 = 242,\n\tCRIT_INT_CLEAR_9 = 243,\n\tCRIT_INT_CLEAR_10 = 244,\n\tCRIT_INT_CLEAR_11 = 245,\n\tCRIT_INT_CLEAR_12 = 246,\n\tCRIT_INT_CLEAR_13 = 247,\n\tCRIT_INT_CLEAR_14 = 248,\n\tCRIT_INT_CLEAR_15 = 249,\n\tCRIT_INT_MASK_0 = 250,\n\tCRIT_INT_MASK_1 = 251,\n\tCRIT_INT_MASK_2 = 252,\n\tCRIT_INT_MASK_3 = 253,\n\tCRIT_INT_MASK_4 = 254,\n\tCRIT_INT_MASK_5 = 255,\n\tCRIT_INT_MASK_6 = 256,\n\tCRIT_INT_MASK_7 = 257,\n\tCRIT_INT_MASK_8 = 258,\n\tCRIT_INT_MASK_9 = 259,\n\tCRIT_INT_MASK_10 = 260,\n\tCRIT_INT_MASK_11 = 261,\n\tCRIT_INT_MASK_12 = 262,\n\tCRIT_INT_MASK_13 = 263,\n\tCRIT_INT_MASK_14 = 264,\n\tCRIT_INT_MASK_15 = 265,\n\tCRIT_THRESH_0 = 266,\n\tCRIT_THRESH_1 = 267,\n\tCRIT_THRESH_2 = 268,\n\tCRIT_THRESH_3 = 269,\n\tCRIT_THRESH_4 = 270,\n\tCRIT_THRESH_5 = 271,\n\tCRIT_THRESH_6 = 272,\n\tCRIT_THRESH_7 = 273,\n\tCRIT_THRESH_8 = 274,\n\tCRIT_THRESH_9 = 275,\n\tCRIT_THRESH_10 = 276,\n\tCRIT_THRESH_11 = 277,\n\tCRIT_THRESH_12 = 278,\n\tCRIT_THRESH_13 = 279,\n\tCRIT_THRESH_14 = 280,\n\tCRIT_THRESH_15 = 281,\n\tWDOG_BARK_STATUS = 282,\n\tWDOG_BARK_CLEAR = 283,\n\tWDOG_BARK_MASK = 284,\n\tWDOG_BARK_COUNT = 285,\n\tCC_MON_STATUS = 286,\n\tCC_MON_CLEAR = 287,\n\tCC_MON_MASK = 288,\n\tMIN_STATUS_0 = 289,\n\tMIN_STATUS_1 = 290,\n\tMIN_STATUS_2 = 291,\n\tMIN_STATUS_3 = 292,\n\tMIN_STATUS_4 = 293,\n\tMIN_STATUS_5 = 294,\n\tMIN_STATUS_6 = 295,\n\tMIN_STATUS_7 = 296,\n\tMIN_STATUS_8 = 297,\n\tMIN_STATUS_9 = 298,\n\tMIN_STATUS_10 = 299,\n\tMIN_STATUS_11 = 300,\n\tMIN_STATUS_12 = 301,\n\tMIN_STATUS_13 = 302,\n\tMIN_STATUS_14 = 303,\n\tMIN_STATUS_15 = 304,\n\tMAX_STATUS_0 = 305,\n\tMAX_STATUS_1 = 306,\n\tMAX_STATUS_2 = 307,\n\tMAX_STATUS_3 = 308,\n\tMAX_STATUS_4 = 309,\n\tMAX_STATUS_5 = 310,\n\tMAX_STATUS_6 = 311,\n\tMAX_STATUS_7 = 312,\n\tMAX_STATUS_8 = 313,\n\tMAX_STATUS_9 = 314,\n\tMAX_STATUS_10 = 315,\n\tMAX_STATUS_11 = 316,\n\tMAX_STATUS_12 = 317,\n\tMAX_STATUS_13 = 318,\n\tMAX_STATUS_14 = 319,\n\tMAX_STATUS_15 = 320,\n\tMAX_REGFIELDS = 321,\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nenum regulator_active_discharge {\n\tREGULATOR_ACTIVE_DISCHARGE_DEFAULT = 0,\n\tREGULATOR_ACTIVE_DISCHARGE_DISABLE = 1,\n\tREGULATOR_ACTIVE_DISCHARGE_ENABLE = 2,\n};\n\nenum regulator_detection_severity {\n\tREGULATOR_SEVERITY_PROT = 0,\n\tREGULATOR_SEVERITY_ERR = 1,\n\tREGULATOR_SEVERITY_WARN = 2,\n};\n\nenum regulator_get_type {\n\tNORMAL_GET = 0,\n\tEXCLUSIVE_GET = 1,\n\tOPTIONAL_GET = 2,\n\tMAX_GET_TYPE = 3,\n};\n\nenum regulator_hw_type {\n\tSMPS = 0,\n\tLDO = 1,\n\tBOB = 2,\n\tVS = 3,\n\tNUM_REGULATOR_TYPES = 4,\n};\n\nenum regulator_status {\n\tREGULATOR_STATUS_OFF = 0,\n\tREGULATOR_STATUS_ON = 1,\n\tREGULATOR_STATUS_ERROR = 2,\n\tREGULATOR_STATUS_FAST = 3,\n\tREGULATOR_STATUS_NORMAL = 4,\n\tREGULATOR_STATUS_IDLE = 5,\n\tREGULATOR_STATUS_STANDBY = 6,\n\tREGULATOR_STATUS_BYPASS = 7,\n\tREGULATOR_STATUS_UNDEFINED = 8,\n};\n\nenum regulator_type {\n\tREGULATOR_VOLTAGE = 0,\n\tREGULATOR_CURRENT = 1,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum renesas_sdhi_dma_cookie {\n\tCOOKIE_UNMAPPED___2 = 0,\n\tCOOKIE_PRE_MAPPED___2 = 1,\n\tCOOKIE_MAPPED___2 = 2,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reset_control_flags {\n\tRESET_CONTROL_EXCLUSIVE = 4,\n\tRESET_CONTROL_EXCLUSIVE_DEASSERTED = 12,\n\tRESET_CONTROL_EXCLUSIVE_RELEASED = 0,\n\tRESET_CONTROL_SHARED = 1,\n\tRESET_CONTROL_SHARED_DEASSERTED = 9,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE = 6,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_DEASSERTED = 14,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_RELEASED = 2,\n\tRESET_CONTROL_OPTIONAL_SHARED = 3,\n\tRESET_CONTROL_OPTIONAL_SHARED_DEASSERTED = 11,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum rgmii_clock_delay {\n\tRGMII_CLK_DELAY_0_2_NS = 0,\n\tRGMII_CLK_DELAY_0_8_NS = 1,\n\tRGMII_CLK_DELAY_1_1_NS = 2,\n\tRGMII_CLK_DELAY_1_7_NS = 3,\n\tRGMII_CLK_DELAY_2_0_NS = 4,\n\tRGMII_CLK_DELAY_2_3_NS = 5,\n\tRGMII_CLK_DELAY_2_6_NS = 6,\n\tRGMII_CLK_DELAY_3_4_NS = 7,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum riic_reg_list {\n\tRIIC_ICCR1 = 0,\n\tRIIC_ICCR2 = 1,\n\tRIIC_ICMR1 = 2,\n\tRIIC_ICMR3 = 3,\n\tRIIC_ICFER = 4,\n\tRIIC_ICSER = 5,\n\tRIIC_ICIER = 6,\n\tRIIC_ICSR2 = 7,\n\tRIIC_ICBRL = 8,\n\tRIIC_ICBRH = 9,\n\tRIIC_ICDRT = 10,\n\tRIIC_ICDRR = 11,\n\tRIIC_REG_END = 12,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum ring_id {\n\tNETSEC_RING_TX = 0,\n\tNETSEC_RING_RX = 1,\n};\n\nenum ripas {\n\tRSI_RIPAS_EMPTY = 0,\n\tRSI_RIPAS_RAM = 1,\n\tRSI_RIPAS_DESTROYED = 2,\n\tRSI_RIPAS_DEV = 3,\n};\n\nenum rk3308_plls {\n\tapll___2 = 0,\n\tdpll___2 = 1,\n\tvpll0 = 2,\n\tvpll1 = 3,\n};\n\nenum rk3328_plls {\n\tapll___3 = 0,\n\tdpll___3 = 1,\n\tcpll___2 = 2,\n\tgpll___2 = 3,\n\tnpll___2 = 4,\n};\n\nenum rk3368_plls {\n\tapllb = 0,\n\taplll = 1,\n\tdpll___4 = 2,\n\tcpll___3 = 3,\n\tgpll___3 = 4,\n\tnpll___3 = 5,\n};\n\nenum rk3399_plls {\n\tlpll = 0,\n\tbpll = 1,\n\tdpll___5 = 2,\n\tcpll___4 = 3,\n\tgpll___4 = 4,\n\tnpll___4 = 5,\n\tvpll = 6,\n};\n\nenum rk3399_pmu_plls {\n\tppll = 0,\n};\n\nenum rk3528_plls {\n\tapll___4 = 0,\n\tcpll___5 = 1,\n\tgpll___5 = 2,\n\tppll___2 = 3,\n\tdpll___6 = 4,\n};\n\nenum rk3562_plls {\n\tapll___5 = 0,\n\tgpll___6 = 1,\n\tvpll___2 = 2,\n\thpll = 3,\n\tcpll___6 = 4,\n\tdpll___7 = 5,\n};\n\nenum rk3568_plls {\n\tapll___6 = 0,\n\tdpll___8 = 1,\n\tgpll___7 = 2,\n\tcpll___7 = 3,\n\tnpll___5 = 4,\n\tvpll___3 = 5,\n};\n\nenum rk3568_pmu_plls {\n\tppll___3 = 0,\n\thpll___2 = 1,\n};\n\nenum rk3576_plls {\n\tbpll___2 = 0,\n\tlpll___2 = 1,\n\tvpll___4 = 2,\n\taupll = 3,\n\tcpll___8 = 4,\n\tgpll___8 = 5,\n\tppll___4 = 6,\n};\n\nenum rk3588_plls {\n\tb0pll = 0,\n\tb1pll = 1,\n\tlpll___3 = 2,\n\tv0pll = 3,\n\taupll___2 = 4,\n\tcpll___9 = 5,\n\tgpll___9 = 6,\n\tnpll___6 = 7,\n\tppll___5 = 8,\n};\n\nenum rk3x_i2c_state {\n\tSTATE_IDLE___3 = 0,\n\tSTATE_START = 1,\n\tSTATE_READ___2 = 2,\n\tSTATE_WRITE___2 = 3,\n\tSTATE_STOP = 4,\n};\n\nenum rk801_reg {\n\tRK801_ID_DCDC1 = 0,\n\tRK801_ID_DCDC2 = 1,\n\tRK801_ID_DCDC4 = 2,\n\tRK801_ID_DCDC3 = 3,\n\tRK801_ID_LDO1 = 4,\n\tRK801_ID_LDO2 = 5,\n\tRK801_ID_SWITCH = 6,\n\tRK801_ID_MAX = 7,\n};\n\nenum rk805_reg {\n\tRK805_ID_DCDC1 = 0,\n\tRK805_ID_DCDC2 = 1,\n\tRK805_ID_DCDC3 = 2,\n\tRK805_ID_DCDC4 = 3,\n\tRK805_ID_LDO1 = 4,\n\tRK805_ID_LDO2 = 5,\n\tRK805_ID_LDO3 = 6,\n};\n\nenum rk806_irqs {\n\tRK806_IRQ_PWRON_FALL = 0,\n\tRK806_IRQ_PWRON_RISE = 1,\n\tRK806_IRQ_PWRON = 2,\n\tRK806_IRQ_PWRON_LP = 3,\n\tRK806_IRQ_HOTDIE = 4,\n\tRK806_IRQ_VDC_RISE = 5,\n\tRK806_IRQ_VDC_FALL = 6,\n\tRK806_IRQ_VB_LO = 7,\n\tRK806_IRQ_REV0 = 8,\n\tRK806_IRQ_REV1 = 9,\n\tRK806_IRQ_REV2 = 10,\n\tRK806_IRQ_CRC_ERROR = 11,\n\tRK806_IRQ_SLP3_GPIO = 12,\n\tRK806_IRQ_SLP2_GPIO = 13,\n\tRK806_IRQ_SLP1_GPIO = 14,\n\tRK806_IRQ_WDT = 15,\n};\n\nenum rk806_reg_id {\n\tRK806_ID_DCDC1 = 0,\n\tRK806_ID_DCDC2 = 1,\n\tRK806_ID_DCDC3 = 2,\n\tRK806_ID_DCDC4 = 3,\n\tRK806_ID_DCDC5 = 4,\n\tRK806_ID_DCDC6 = 5,\n\tRK806_ID_DCDC7 = 6,\n\tRK806_ID_DCDC8 = 7,\n\tRK806_ID_DCDC9 = 8,\n\tRK806_ID_DCDC10 = 9,\n\tRK806_ID_NLDO1 = 10,\n\tRK806_ID_NLDO2 = 11,\n\tRK806_ID_NLDO3 = 12,\n\tRK806_ID_NLDO4 = 13,\n\tRK806_ID_NLDO5 = 14,\n\tRK806_ID_PLDO1 = 15,\n\tRK806_ID_PLDO2 = 16,\n\tRK806_ID_PLDO3 = 17,\n\tRK806_ID_PLDO4 = 18,\n\tRK806_ID_PLDO5 = 19,\n\tRK806_ID_PLDO6 = 20,\n\tRK806_ID_END = 21,\n};\n\nenum rk808_reg {\n\tRK808_ID_DCDC1 = 0,\n\tRK808_ID_DCDC2 = 1,\n\tRK808_ID_DCDC3 = 2,\n\tRK808_ID_DCDC4 = 3,\n\tRK808_ID_LDO1 = 4,\n\tRK808_ID_LDO2 = 5,\n\tRK808_ID_LDO3 = 6,\n\tRK808_ID_LDO4 = 7,\n\tRK808_ID_LDO5 = 8,\n\tRK808_ID_LDO6 = 9,\n\tRK808_ID_LDO7 = 10,\n\tRK808_ID_LDO8 = 11,\n\tRK808_ID_SWITCH1 = 12,\n\tRK808_ID_SWITCH2 = 13,\n};\n\nenum rk809_reg_id {\n\tRK809_ID_DCDC5 = 13,\n\tRK809_ID_SW1 = 14,\n\tRK809_ID_SW2 = 15,\n\tRK809_NUM_REGULATORS = 16,\n};\n\nenum rk816_irqs {\n\tRK816_IRQ_PWRON_FALL = 0,\n\tRK816_IRQ_PWRON_RISE = 1,\n\tRK816_IRQ_VB_LOW = 2,\n\tRK816_IRQ_PWRON = 3,\n\tRK816_IRQ_PWRON_LP = 4,\n\tRK816_IRQ_HOTDIE = 5,\n\tRK816_IRQ_RTC_ALARM = 6,\n\tRK816_IRQ_RTC_PERIOD = 7,\n\tRK816_IRQ_USB_OV = 8,\n\tRK816_IRQ_PLUG_IN = 9,\n\tRK816_IRQ_PLUG_OUT = 10,\n\tRK816_IRQ_CHG_OK = 11,\n\tRK816_IRQ_CHG_TE = 12,\n\tRK816_IRQ_CHG_TS = 13,\n\tRK816_IRQ_CHG_CVTLIM = 14,\n\tRK816_IRQ_DISCHG_ILIM = 15,\n};\n\nenum rk816_reg {\n\tRK816_ID_DCDC1 = 0,\n\tRK816_ID_DCDC2 = 1,\n\tRK816_ID_DCDC3 = 2,\n\tRK816_ID_DCDC4 = 3,\n\tRK816_ID_LDO1 = 4,\n\tRK816_ID_LDO2 = 5,\n\tRK816_ID_LDO3 = 6,\n\tRK816_ID_LDO4 = 7,\n\tRK816_ID_LDO5 = 8,\n\tRK816_ID_LDO6 = 9,\n\tRK816_ID_BOOST = 10,\n\tRK816_ID_OTG_SW = 11,\n};\n\nenum rk817_reg_id {\n\tRK817_ID_DCDC1 = 0,\n\tRK817_ID_DCDC2 = 1,\n\tRK817_ID_DCDC3 = 2,\n\tRK817_ID_DCDC4 = 3,\n\tRK817_ID_LDO1 = 4,\n\tRK817_ID_LDO2 = 5,\n\tRK817_ID_LDO3 = 6,\n\tRK817_ID_LDO4 = 7,\n\tRK817_ID_LDO5 = 8,\n\tRK817_ID_LDO6 = 9,\n\tRK817_ID_LDO7 = 10,\n\tRK817_ID_LDO8 = 11,\n\tRK817_ID_LDO9 = 12,\n\tRK817_ID_BOOST = 13,\n\tRK817_ID_BOOST_OTG_SW = 14,\n\tRK817_NUM_REGULATORS = 15,\n};\n\nenum rk818_reg {\n\tRK818_ID_DCDC1 = 0,\n\tRK818_ID_DCDC2 = 1,\n\tRK818_ID_DCDC3 = 2,\n\tRK818_ID_DCDC4 = 3,\n\tRK818_ID_BOOST = 4,\n\tRK818_ID_LDO1 = 5,\n\tRK818_ID_LDO2 = 6,\n\tRK818_ID_LDO3 = 7,\n\tRK818_ID_LDO4 = 8,\n\tRK818_ID_LDO5 = 9,\n\tRK818_ID_LDO6 = 10,\n\tRK818_ID_LDO7 = 11,\n\tRK818_ID_LDO8 = 12,\n\tRK818_ID_LDO9 = 13,\n\tRK818_ID_SWITCH = 14,\n\tRK818_ID_HDMI_SWITCH = 15,\n\tRK818_ID_OTG_SWITCH = 16,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rockchip_clk_branch_type {\n\tbranch_composite = 0,\n\tbranch_mux = 1,\n\tbranch_grf_mux = 2,\n\tbranch_divider = 3,\n\tbranch_fraction_divider = 4,\n\tbranch_gate = 5,\n\tbranch_grf_gate = 6,\n\tbranch_linked_gate = 7,\n\tbranch_mmc = 8,\n\tbranch_grf_mmc = 9,\n\tbranch_inverter = 10,\n\tbranch_factor = 11,\n\tbranch_ddrclk = 12,\n\tbranch_half_divider = 13,\n};\n\nenum rockchip_grf_type {\n\tgrf_type_sys = 0,\n\tgrf_type_pmu0 = 1,\n\tgrf_type_pmu1 = 2,\n\tgrf_type_ioc = 3,\n\tgrf_type_vo = 4,\n\tgrf_type_vpu = 5,\n};\n\nenum rockchip_mux_route_location {\n\tROCKCHIP_ROUTE_SAME = 0,\n\tROCKCHIP_ROUTE_PMU = 1,\n\tROCKCHIP_ROUTE_GRF = 2,\n};\n\nenum rockchip_pin_drv_type {\n\tDRV_TYPE_IO_DEFAULT = 0,\n\tDRV_TYPE_IO_1V8_OR_3V0 = 1,\n\tDRV_TYPE_IO_1V8_ONLY = 2,\n\tDRV_TYPE_IO_1V8_3V0_AUTO = 3,\n\tDRV_TYPE_IO_3V3_ONLY = 4,\n\tDRV_TYPE_IO_LEVEL_2_BIT = 5,\n\tDRV_TYPE_IO_LEVEL_8_BIT = 6,\n\tDRV_TYPE_MAX = 7,\n};\n\nenum rockchip_pin_pull_type {\n\tPULL_TYPE_IO_DEFAULT = 0,\n\tPULL_TYPE_IO_1V8_ONLY = 1,\n\tPULL_TYPE_MAX = 2,\n};\n\nenum rockchip_pinctrl_type {\n\tPX30 = 0,\n\tRV1108 = 1,\n\tRV1126 = 2,\n\tRK2928 = 3,\n\tRK3066B = 4,\n\tRK3128 = 5,\n\tRK3188 = 6,\n\tRK3288 = 7,\n\tRK3308 = 8,\n\tRK3328 = 9,\n\tRK3368 = 10,\n\tRK3399 = 11,\n\tRK3506 = 12,\n\tRK3528 = 13,\n\tRK3562 = 14,\n\tRK3568 = 15,\n\tRK3576 = 16,\n\tRK3588 = 17,\n};\n\nenum rockchip_pll_type {\n\tpll_rk3036 = 0,\n\tpll_rk3066 = 1,\n\tpll_rk3328 = 2,\n\tpll_rk3399 = 3,\n\tpll_rk3588 = 4,\n\tpll_rk3588_core = 5,\n\tpll_rk3588_ddr = 6,\n};\n\nenum rockchip_usb2phy_host_state {\n\tPHY_STATE_HS_ONLINE = 0,\n\tPHY_STATE_DISCONNECT = 1,\n\tPHY_STATE_CONNECT = 2,\n\tPHY_STATE_FS_LS_ONLINE = 4,\n};\n\nenum rockchip_usb2phy_port_id {\n\tUSB2PHY_PORT_OTG = 0,\n\tUSB2PHY_PORT_HOST = 1,\n\tUSB2PHY_NUM_PORTS = 2,\n};\n\nenum rohm_chip_type {\n\tROHM_CHIP_TYPE_BD9571 = 0,\n\tROHM_CHIP_TYPE_BD9573 = 1,\n\tROHM_CHIP_TYPE_BD9574 = 2,\n\tROHM_CHIP_TYPE_BD9576 = 3,\n\tROHM_CHIP_TYPE_BD71815 = 4,\n\tROHM_CHIP_TYPE_BD71828 = 5,\n\tROHM_CHIP_TYPE_BD71837 = 6,\n\tROHM_CHIP_TYPE_BD71847 = 7,\n\tROHM_CHIP_TYPE_BD72720 = 8,\n\tROHM_CHIP_TYPE_BD96801 = 9,\n\tROHM_CHIP_TYPE_BD96802 = 10,\n\tROHM_CHIP_TYPE_BD96805 = 11,\n\tROHM_CHIP_TYPE_BD96806 = 12,\n\tROHM_CHIP_TYPE_AMOUNT = 13,\n};\n\nenum routing_attribute {\n\tDIRECT_ROUTING = 0,\n\tSUBTRACTIVE_ROUTING = 1,\n\tTABLE_ROUTING = 2,\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nenum rpc_accept_stat {\n\tRPC_SUCCESS = 0,\n\tRPC_PROG_UNAVAIL = 1,\n\tRPC_PROG_MISMATCH = 2,\n\tRPC_PROC_UNAVAIL = 3,\n\tRPC_GARBAGE_ARGS = 4,\n\tRPC_SYSTEM_ERR = 5,\n\tRPC_DROP_REPLY = 60000,\n};\n\nenum rpc_auth_flavors {\n\tRPC_AUTH_NULL = 0,\n\tRPC_AUTH_UNIX = 1,\n\tRPC_AUTH_SHORT = 2,\n\tRPC_AUTH_DES = 3,\n\tRPC_AUTH_KRB = 4,\n\tRPC_AUTH_GSS = 6,\n\tRPC_AUTH_TLS = 7,\n\tRPC_AUTH_MAXFLAVOR = 8,\n\tRPC_AUTH_GSS_KRB5 = 390003,\n\tRPC_AUTH_GSS_KRB5I = 390004,\n\tRPC_AUTH_GSS_KRB5P = 390005,\n\tRPC_AUTH_GSS_LKEY = 390006,\n\tRPC_AUTH_GSS_LKEYI = 390007,\n\tRPC_AUTH_GSS_LKEYP = 390008,\n\tRPC_AUTH_GSS_SPKM = 390009,\n\tRPC_AUTH_GSS_SPKMI = 390010,\n\tRPC_AUTH_GSS_SPKMP = 390011,\n};\n\nenum rpc_auth_stat {\n\tRPC_AUTH_OK = 0,\n\tRPC_AUTH_BADCRED = 1,\n\tRPC_AUTH_REJECTEDCRED = 2,\n\tRPC_AUTH_BADVERF = 3,\n\tRPC_AUTH_REJECTEDVERF = 4,\n\tRPC_AUTH_TOOWEAK = 5,\n\tRPC_AUTH_INVALIDRESP = 6,\n\tRPC_AUTH_FAILED = 7,\n\tRPCSEC_GSS_CREDPROBLEM = 13,\n\tRPCSEC_GSS_CTXPROBLEM = 14,\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum rpc_gss_proc {\n\tRPC_GSS_PROC_DATA = 0,\n\tRPC_GSS_PROC_INIT = 1,\n\tRPC_GSS_PROC_CONTINUE_INIT = 2,\n\tRPC_GSS_PROC_DESTROY = 3,\n};\n\nenum rpc_gss_svc {\n\tRPC_GSS_SVC_NONE = 1,\n\tRPC_GSS_SVC_INTEGRITY = 2,\n\tRPC_GSS_SVC_PRIVACY = 3,\n};\n\nenum rpc_msg_type {\n\tRPC_CALL = 0,\n\tRPC_REPLY = 1,\n};\n\nenum rpc_reject_stat {\n\tRPC_MISMATCH = 0,\n\tRPC_AUTH_ERROR = 1,\n};\n\nenum rpc_reply_stat {\n\tRPC_MSG_ACCEPTED = 0,\n\tRPC_MSG_DENIED = 1,\n};\n\nenum rpi_firmware_clk_id {\n\tRPI_FIRMWARE_EMMC_CLK_ID = 1,\n\tRPI_FIRMWARE_UART_CLK_ID = 2,\n\tRPI_FIRMWARE_ARM_CLK_ID = 3,\n\tRPI_FIRMWARE_CORE_CLK_ID = 4,\n\tRPI_FIRMWARE_V3D_CLK_ID = 5,\n\tRPI_FIRMWARE_H264_CLK_ID = 6,\n\tRPI_FIRMWARE_ISP_CLK_ID = 7,\n\tRPI_FIRMWARE_SDRAM_CLK_ID = 8,\n\tRPI_FIRMWARE_PIXEL_CLK_ID = 9,\n\tRPI_FIRMWARE_PWM_CLK_ID = 10,\n\tRPI_FIRMWARE_HEVC_CLK_ID = 11,\n\tRPI_FIRMWARE_EMMC2_CLK_ID = 12,\n\tRPI_FIRMWARE_M2MC_CLK_ID = 13,\n\tRPI_FIRMWARE_PIXEL_BVB_CLK_ID = 14,\n\tRPI_FIRMWARE_VEC_CLK_ID = 15,\n\tRPI_FIRMWARE_DISP_CLK_ID = 16,\n\tRPI_FIRMWARE_NUM_CLK_ID = 17,\n};\n\nenum rpi_firmware_property_status {\n\tRPI_FIRMWARE_STATUS_REQUEST = 0,\n\tRPI_FIRMWARE_STATUS_SUCCESS = 2147483648,\n\tRPI_FIRMWARE_STATUS_ERROR = 2147483649,\n};\n\nenum rpi_firmware_property_tag {\n\tRPI_FIRMWARE_PROPERTY_END = 0,\n\tRPI_FIRMWARE_GET_FIRMWARE_REVISION = 1,\n\tRPI_FIRMWARE_SET_CURSOR_INFO = 32784,\n\tRPI_FIRMWARE_SET_CURSOR_STATE = 32785,\n\tRPI_FIRMWARE_GET_BOARD_MODEL = 65537,\n\tRPI_FIRMWARE_GET_BOARD_REVISION = 65538,\n\tRPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 65539,\n\tRPI_FIRMWARE_GET_BOARD_SERIAL = 65540,\n\tRPI_FIRMWARE_GET_ARM_MEMORY = 65541,\n\tRPI_FIRMWARE_GET_VC_MEMORY = 65542,\n\tRPI_FIRMWARE_GET_CLOCKS = 65543,\n\tRPI_FIRMWARE_GET_POWER_STATE = 131073,\n\tRPI_FIRMWARE_GET_TIMING = 131074,\n\tRPI_FIRMWARE_SET_POWER_STATE = 163841,\n\tRPI_FIRMWARE_GET_CLOCK_STATE = 196609,\n\tRPI_FIRMWARE_GET_CLOCK_RATE = 196610,\n\tRPI_FIRMWARE_GET_VOLTAGE = 196611,\n\tRPI_FIRMWARE_GET_MAX_CLOCK_RATE = 196612,\n\tRPI_FIRMWARE_GET_MAX_VOLTAGE = 196613,\n\tRPI_FIRMWARE_GET_TEMPERATURE = 196614,\n\tRPI_FIRMWARE_GET_MIN_CLOCK_RATE = 196615,\n\tRPI_FIRMWARE_GET_MIN_VOLTAGE = 196616,\n\tRPI_FIRMWARE_GET_TURBO = 196617,\n\tRPI_FIRMWARE_GET_MAX_TEMPERATURE = 196618,\n\tRPI_FIRMWARE_GET_STC = 196619,\n\tRPI_FIRMWARE_ALLOCATE_MEMORY = 196620,\n\tRPI_FIRMWARE_LOCK_MEMORY = 196621,\n\tRPI_FIRMWARE_UNLOCK_MEMORY = 196622,\n\tRPI_FIRMWARE_RELEASE_MEMORY = 196623,\n\tRPI_FIRMWARE_EXECUTE_CODE = 196624,\n\tRPI_FIRMWARE_EXECUTE_QPU = 196625,\n\tRPI_FIRMWARE_SET_ENABLE_QPU = 196626,\n\tRPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 196628,\n\tRPI_FIRMWARE_GET_EDID_BLOCK = 196640,\n\tRPI_FIRMWARE_GET_CUSTOMER_OTP = 196641,\n\tRPI_FIRMWARE_GET_DOMAIN_STATE = 196656,\n\tRPI_FIRMWARE_GET_THROTTLED = 196678,\n\tRPI_FIRMWARE_GET_CLOCK_MEASURED = 196679,\n\tRPI_FIRMWARE_NOTIFY_REBOOT = 196680,\n\tRPI_FIRMWARE_SET_CLOCK_STATE = 229377,\n\tRPI_FIRMWARE_SET_CLOCK_RATE = 229378,\n\tRPI_FIRMWARE_SET_VOLTAGE = 229379,\n\tRPI_FIRMWARE_SET_TURBO = 229385,\n\tRPI_FIRMWARE_SET_CUSTOMER_OTP = 229409,\n\tRPI_FIRMWARE_SET_DOMAIN_STATE = 229424,\n\tRPI_FIRMWARE_GET_GPIO_STATE = 196673,\n\tRPI_FIRMWARE_SET_GPIO_STATE = 229441,\n\tRPI_FIRMWARE_SET_SDHOST_CLOCK = 229442,\n\tRPI_FIRMWARE_GET_GPIO_CONFIG = 196675,\n\tRPI_FIRMWARE_SET_GPIO_CONFIG = 229443,\n\tRPI_FIRMWARE_GET_PERIPH_REG = 196677,\n\tRPI_FIRMWARE_SET_PERIPH_REG = 229445,\n\tRPI_FIRMWARE_GET_POE_HAT_VAL = 196681,\n\tRPI_FIRMWARE_SET_POE_HAT_VAL = 196688,\n\tRPI_FIRMWARE_NOTIFY_XHCI_RESET = 196696,\n\tRPI_FIRMWARE_NOTIFY_DISPLAY_DONE = 196710,\n\tRPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 262145,\n\tRPI_FIRMWARE_FRAMEBUFFER_BLANK = 262146,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 262147,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 262148,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH = 262149,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER = 262150,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE = 262151,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PITCH = 262152,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 262153,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 262154,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 262155,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF = 262159,\n\tRPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF = 262160,\n\tRPI_FIRMWARE_FRAMEBUFFER_RELEASE = 294913,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 278531,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 278532,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH = 278533,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER = 278534,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE = 278535,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 278537,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 278538,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 278539,\n\tRPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC = 278542,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 294915,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 294916,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 294917,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER = 294918,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE = 294919,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 294921,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 294922,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 294923,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_TOUCHBUF = 294943,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF = 294944,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 294926,\n\tRPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT = 294927,\n\tRPI_FIRMWARE_VCHIQ_INIT = 294928,\n\tRPI_FIRMWARE_GET_COMMAND_LINE = 327681,\n\tRPI_FIRMWARE_GET_DMA_CHANNELS = 393217,\n};\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rpmb_type {\n\tRPMB_TYPE_EMMC = 0,\n\tRPMB_TYPE_UFS = 1,\n\tRPMB_TYPE_NVME = 2,\n};\n\nenum rpmb_unit_desc_param {\n\tRPMB_UNIT_DESC_PARAM_LEN = 0,\n\tRPMB_UNIT_DESC_PARAM_TYPE = 1,\n\tRPMB_UNIT_DESC_PARAM_UNIT_INDEX = 2,\n\tRPMB_UNIT_DESC_PARAM_LU_ENABLE = 3,\n\tRPMB_UNIT_DESC_PARAM_BOOT_LUN_ID = 4,\n\tRPMB_UNIT_DESC_PARAM_LU_WR_PROTECT = 5,\n\tRPMB_UNIT_DESC_PARAM_LU_Q_DEPTH = 6,\n\tRPMB_UNIT_DESC_PARAM_PSA_SENSITIVE = 7,\n\tRPMB_UNIT_DESC_PARAM_MEM_TYPE = 8,\n\tRPMB_UNIT_DESC_PARAM_REGION_EN = 9,\n\tRPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 10,\n\tRPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 11,\n\tRPMB_UNIT_DESC_PARAM_REGION0_SIZE = 19,\n\tRPMB_UNIT_DESC_PARAM_REGION1_SIZE = 20,\n\tRPMB_UNIT_DESC_PARAM_REGION2_SIZE = 21,\n\tRPMB_UNIT_DESC_PARAM_REGION3_SIZE = 22,\n\tRPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE = 23,\n\tRPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 24,\n};\n\nenum rpmh_regulator_type {\n\tVRM = 0,\n\tXOB = 1,\n};\n\nenum rpmh_state {\n\tRPMH_SLEEP_STATE = 0,\n\tRPMH_WAKE_ONLY_STATE = 1,\n\tRPMH_ACTIVE_ONLY_STATE = 2,\n};\n\nenum rpmsg_ns_flags {\n\tRPMSG_NS_CREATE = 0,\n\tRPMSG_NS_DESTROY = 1,\n};\n\nenum rproc_crash_type {\n\tRPROC_MMUFAULT = 0,\n\tRPROC_WATCHDOG = 1,\n\tRPROC_FATAL_ERROR = 2,\n};\n\nenum rproc_dump_mechanism {\n\tRPROC_COREDUMP_DISABLED = 0,\n\tRPROC_COREDUMP_ENABLED = 1,\n\tRPROC_COREDUMP_INLINE = 2,\n};\n\nenum rproc_features {\n\tRPROC_FEAT_ATTACH_ON_RECOVERY = 0,\n\tRPROC_MAX_FEATURES = 1,\n};\n\nenum rproc_state {\n\tRPROC_OFFLINE = 0,\n\tRPROC_SUSPENDED = 1,\n\tRPROC_RUNNING = 2,\n\tRPROC_CRASHED = 3,\n\tRPROC_DELETED = 4,\n\tRPROC_ATTACHED = 5,\n\tRPROC_DETACHED = 6,\n\tRPROC_LAST = 7,\n};\n\nenum rpu_oper_mode {\n\tPM_RPU_MODE_LOCKSTEP = 0,\n\tPM_RPU_MODE_SPLIT = 1,\n};\n\nenum rpu_tcm_comb {\n\tPM_RPU_TCM_SPLIT = 0,\n\tPM_RPU_TCM_COMB = 1,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rsaprivkey_actions {\n\tACT_rsa_get_d = 0,\n\tACT_rsa_get_dp = 1,\n\tACT_rsa_get_dq = 2,\n\tACT_rsa_get_e = 3,\n\tACT_rsa_get_n = 4,\n\tACT_rsa_get_p = 5,\n\tACT_rsa_get_q = 6,\n\tACT_rsa_get_qinv = 7,\n\tNR__rsaprivkey_actions = 8,\n};\n\nenum rsapubkey_actions {\n\tACT_rsa_get_e___2 = 0,\n\tACT_rsa_get_n___2 = 1,\n\tNR__rsapubkey_actions = 2,\n};\n\nenum rsc_handling_status {\n\tRSC_HANDLED = 0,\n\tRSC_IGNORED = 1,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rswitch_etha_mode {\n\tEAMC_OPC_RESET = 0,\n\tEAMC_OPC_DISABLE = 1,\n\tEAMC_OPC_CONFIG = 2,\n\tEAMC_OPC_OPERATION = 3,\n};\n\nenum rswitch_gwca_mode {\n\tGWMC_OPC_RESET = 0,\n\tGWMC_OPC_DISABLE = 1,\n\tGWMC_OPC_CONFIG = 2,\n\tGWMC_OPC_OPERATION = 3,\n};\n\nenum rswitch_reg {\n\tFWGC = 0,\n\tFWTTC0 = 16,\n\tFWTTC1 = 20,\n\tFWLBMC = 24,\n\tFWCEPTC = 32,\n\tFWCEPRC0 = 36,\n\tFWCEPRC1 = 40,\n\tFWCEPRC2 = 44,\n\tFWCLPTC = 48,\n\tFWCLPRC = 52,\n\tFWCMPTC = 64,\n\tFWEMPTC = 68,\n\tFWSDMPTC = 80,\n\tFWSDMPVC = 84,\n\tFWLBWMC0 = 128,\n\tFWPC00 = 256,\n\tFWPC10 = 260,\n\tFWPC20 = 264,\n\tFWCTGC00 = 1024,\n\tFWCTGC10 = 1028,\n\tFWCTTC00 = 1032,\n\tFWCTTC10 = 1036,\n\tFWCTTC200 = 1040,\n\tFWCTSC00 = 1056,\n\tFWCTSC10 = 1060,\n\tFWCTSC20 = 1064,\n\tFWCTSC30 = 1068,\n\tFWCTSC40 = 1072,\n\tFWTWBFC0 = 4096,\n\tFWTWBFVC0 = 4100,\n\tFWTHBFC0 = 5120,\n\tFWTHBFV0C0 = 5124,\n\tFWTHBFV1C0 = 5128,\n\tFWFOBFC0 = 6144,\n\tFWFOBFV0C0 = 6148,\n\tFWFOBFV1C0 = 6152,\n\tFWRFC0 = 7168,\n\tFWRFVC0 = 7172,\n\tFWCFC0 = 8192,\n\tFWCFMC00 = 8196,\n\tFWIP4SC = 16392,\n\tFWIP6SC = 16408,\n\tFWIP6OC = 16412,\n\tFWL2SC = 16416,\n\tFWSFHEC = 16432,\n\tFWSHCR0 = 16448,\n\tFWSHCR1 = 16452,\n\tFWSHCR2 = 16456,\n\tFWSHCR3 = 16460,\n\tFWSHCR4 = 16464,\n\tFWSHCR5 = 16468,\n\tFWSHCR6 = 16472,\n\tFWSHCR7 = 16476,\n\tFWSHCR8 = 16480,\n\tFWSHCR9 = 16484,\n\tFWSHCR10 = 16488,\n\tFWSHCR11 = 16492,\n\tFWSHCR12 = 16496,\n\tFWSHCR13 = 16500,\n\tFWSHCRR = 16504,\n\tFWLTHHEC = 16528,\n\tFWLTHHC = 16532,\n\tFWLTHTL0 = 16544,\n\tFWLTHTL1 = 16548,\n\tFWLTHTL2 = 16552,\n\tFWLTHTL3 = 16556,\n\tFWLTHTL4 = 16560,\n\tFWLTHTL5 = 16564,\n\tFWLTHTL6 = 16568,\n\tFWLTHTL7 = 16572,\n\tFWLTHTL80 = 16576,\n\tFWLTHTL9 = 16592,\n\tFWLTHTLR = 16596,\n\tFWLTHTIM = 16608,\n\tFWLTHTEM = 16612,\n\tFWLTHTS0 = 16640,\n\tFWLTHTS1 = 16644,\n\tFWLTHTS2 = 16648,\n\tFWLTHTS3 = 16652,\n\tFWLTHTS4 = 16656,\n\tFWLTHTSR0 = 16672,\n\tFWLTHTSR1 = 16676,\n\tFWLTHTSR2 = 16680,\n\tFWLTHTSR3 = 16684,\n\tFWLTHTSR40 = 16688,\n\tFWLTHTSR5 = 16704,\n\tFWLTHTR = 16720,\n\tFWLTHTRR0 = 16724,\n\tFWLTHTRR1 = 16728,\n\tFWLTHTRR2 = 16732,\n\tFWLTHTRR3 = 16736,\n\tFWLTHTRR4 = 16740,\n\tFWLTHTRR5 = 16744,\n\tFWLTHTRR6 = 16748,\n\tFWLTHTRR7 = 16752,\n\tFWLTHTRR8 = 16756,\n\tFWLTHTRR9 = 16768,\n\tFWLTHTRR10 = 16784,\n\tFWIPHEC = 16916,\n\tFWIPHC = 16920,\n\tFWIPTL0 = 16928,\n\tFWIPTL1 = 16932,\n\tFWIPTL2 = 16936,\n\tFWIPTL3 = 16940,\n\tFWIPTL4 = 16944,\n\tFWIPTL5 = 16948,\n\tFWIPTL6 = 16952,\n\tFWIPTL7 = 16960,\n\tFWIPTL8 = 16976,\n\tFWIPTLR = 16980,\n\tFWIPTIM = 16992,\n\tFWIPTEM = 16996,\n\tFWIPTS0 = 17008,\n\tFWIPTS1 = 17012,\n\tFWIPTS2 = 17016,\n\tFWIPTS3 = 17020,\n\tFWIPTS4 = 17024,\n\tFWIPTSR0 = 17028,\n\tFWIPTSR1 = 17032,\n\tFWIPTSR2 = 17036,\n\tFWIPTSR3 = 17040,\n\tFWIPTSR4 = 17056,\n\tFWIPTR = 17072,\n\tFWIPTRR0 = 17076,\n\tFWIPTRR1 = 17080,\n\tFWIPTRR2 = 17084,\n\tFWIPTRR3 = 17088,\n\tFWIPTRR4 = 17092,\n\tFWIPTRR5 = 17096,\n\tFWIPTRR6 = 17100,\n\tFWIPTRR7 = 17104,\n\tFWIPTRR8 = 17120,\n\tFWIPTRR9 = 17136,\n\tFWIPHLEC = 17152,\n\tFWIPAGUSPC = 17664,\n\tFWIPAGC = 17668,\n\tFWIPAGM0 = 17680,\n\tFWIPAGM1 = 17684,\n\tFWIPAGM2 = 17688,\n\tFWIPAGM3 = 17692,\n\tFWIPAGM4 = 17696,\n\tFWMACHEC = 17952,\n\tFWMACHC = 17956,\n\tFWMACTL0 = 17968,\n\tFWMACTL1 = 17972,\n\tFWMACTL2 = 17976,\n\tFWMACTL3 = 17980,\n\tFWMACTL4 = 17984,\n\tFWMACTL5 = 18000,\n\tFWMACTLR = 18004,\n\tFWMACTIM = 18016,\n\tFWMACTEM = 18020,\n\tFWMACTS0 = 18032,\n\tFWMACTS1 = 18036,\n\tFWMACTSR0 = 18040,\n\tFWMACTSR1 = 18044,\n\tFWMACTSR2 = 18048,\n\tFWMACTSR3 = 18064,\n\tFWMACTR = 18080,\n\tFWMACTRR0 = 18084,\n\tFWMACTRR1 = 18088,\n\tFWMACTRR2 = 18092,\n\tFWMACTRR3 = 18096,\n\tFWMACTRR4 = 18100,\n\tFWMACTRR5 = 18112,\n\tFWMACTRR6 = 18128,\n\tFWMACHLEC = 18176,\n\tFWMACAGUSPC = 18560,\n\tFWMACAGC = 18564,\n\tFWMACAGM0 = 18568,\n\tFWMACAGM1 = 18572,\n\tFWVLANTEC = 18688,\n\tFWVLANTL0 = 18704,\n\tFWVLANTL1 = 18708,\n\tFWVLANTL2 = 18712,\n\tFWVLANTL3 = 18720,\n\tFWVLANTL4 = 18736,\n\tFWVLANTLR = 18740,\n\tFWVLANTIM = 18752,\n\tFWVLANTEM = 18756,\n\tFWVLANTS = 18768,\n\tFWVLANTSR0 = 18772,\n\tFWVLANTSR1 = 18776,\n\tFWVLANTSR2 = 18784,\n\tFWVLANTSR3 = 18800,\n\tFWPBFC0 = 18944,\n\tFWPBFCSDC00 = 18948,\n\tFWL23URL0 = 19968,\n\tFWL23URL1 = 19972,\n\tFWL23URL2 = 19976,\n\tFWL23URL3 = 19980,\n\tFWL23URLR = 19984,\n\tFWL23UTIM = 20000,\n\tFWL23URR = 20016,\n\tFWL23URRR0 = 20020,\n\tFWL23URRR1 = 20024,\n\tFWL23URRR2 = 20028,\n\tFWL23URRR3 = 20032,\n\tFWL23URMC0 = 20224,\n\tFWPMFGC0 = 20480,\n\tFWPGFC0 = 20736,\n\tFWPGFIGSC0 = 20740,\n\tFWPGFENC0 = 20744,\n\tFWPGFENM0 = 20748,\n\tFWPGFCSTC00 = 20752,\n\tFWPGFCSTC10 = 20756,\n\tFWPGFCSTM00 = 20760,\n\tFWPGFCSTM10 = 20764,\n\tFWPGFCTC0 = 20768,\n\tFWPGFCTM0 = 20772,\n\tFWPGFHCC0 = 20776,\n\tFWPGFSM0 = 20780,\n\tFWPGFGC0 = 20784,\n\tFWPGFGL0 = 21760,\n\tFWPGFGL1 = 21764,\n\tFWPGFGLR = 21784,\n\tFWPGFGR = 21776,\n\tFWPGFGRR0 = 21780,\n\tFWPGFGRR1 = 21784,\n\tFWPGFRIM = 21792,\n\tFWPMTRFC0 = 22016,\n\tFWPMTRCBSC0 = 22020,\n\tFWPMTRC0RC0 = 22024,\n\tFWPMTREBSC0 = 22028,\n\tFWPMTREIRC0 = 22032,\n\tFWPMTRFM0 = 22036,\n\tFWFTL0 = 24576,\n\tFWFTL1 = 24580,\n\tFWFTLR = 24584,\n\tFWFTOC = 24592,\n\tFWFTOPC = 24596,\n\tFWFTIM = 24608,\n\tFWFTR = 24624,\n\tFWFTRR0 = 24628,\n\tFWFTRR1 = 24632,\n\tFWFTRR2 = 24636,\n\tFWSEQNGC0 = 24832,\n\tFWSEQNGM0 = 24836,\n\tFWSEQNRC = 25088,\n\tFWCTFDCN0 = 25344,\n\tFWLTHFDCN0 = 25348,\n\tFWIPFDCN0 = 25352,\n\tFWLTWFDCN0 = 25356,\n\tFWPBFDCN0 = 25360,\n\tFWMHLCN0 = 25364,\n\tFWIHLCN0 = 25368,\n\tFWICRDCN0 = 25856,\n\tFWWMRDCN0 = 25860,\n\tFWCTRDCN0 = 25864,\n\tFWLTHRDCN0 = 25868,\n\tFWIPRDCN0 = 25872,\n\tFWLTWRDCN0 = 25876,\n\tFWPBRDCN0 = 25880,\n\tFWPMFDCN0 = 26368,\n\tFWPGFDCN0 = 26496,\n\tFWPMGDCN0 = 26624,\n\tFWPMYDCN0 = 26628,\n\tFWPMRDCN0 = 26632,\n\tFWFRPPCN0 = 27136,\n\tFWFRDPCN0 = 27140,\n\tFWEIS00 = 30976,\n\tFWEIE00 = 30980,\n\tFWEID00 = 30984,\n\tFWEIS1 = 31232,\n\tFWEIE1 = 31236,\n\tFWEID1 = 31240,\n\tFWEIS2 = 31248,\n\tFWEIE2 = 31252,\n\tFWEID2 = 31256,\n\tFWEIS3 = 31264,\n\tFWEIE3 = 31268,\n\tFWEID3 = 31272,\n\tFWEIS4 = 31280,\n\tFWEIE4 = 31284,\n\tFWEID4 = 31288,\n\tFWEIS5 = 31296,\n\tFWEIE5 = 31300,\n\tFWEID5 = 31304,\n\tFWEIS60 = 31312,\n\tFWEIE60 = 31316,\n\tFWEID60 = 31320,\n\tFWEIS61 = 31328,\n\tFWEIE61 = 31332,\n\tFWEID61 = 31336,\n\tFWEIS62 = 31344,\n\tFWEIE62 = 31348,\n\tFWEID62 = 31352,\n\tFWEIS63 = 31360,\n\tFWEIE63 = 31364,\n\tFWEID63 = 31368,\n\tFWEIS70 = 31376,\n\tFWEIE70 = 31380,\n\tFWEID70 = 31384,\n\tFWEIS71 = 31392,\n\tFWEIE71 = 31396,\n\tFWEID71 = 31400,\n\tFWEIS72 = 31408,\n\tFWEIE72 = 31412,\n\tFWEID72 = 31416,\n\tFWEIS73 = 31424,\n\tFWEIE73 = 31428,\n\tFWEID73 = 31432,\n\tFWEIS80 = 31440,\n\tFWEIE80 = 31444,\n\tFWEID80 = 31448,\n\tFWEIS81 = 31456,\n\tFWEIE81 = 31460,\n\tFWEID81 = 31464,\n\tFWEIS82 = 31472,\n\tFWEIE82 = 31476,\n\tFWEID82 = 31480,\n\tFWEIS83 = 31488,\n\tFWEIE83 = 31492,\n\tFWEID83 = 31496,\n\tFWMIS0 = 31744,\n\tFWMIE0 = 31748,\n\tFWMID0 = 31752,\n\tFWSCR0 = 32000,\n\tFWSCR1 = 32004,\n\tFWSCR2 = 32008,\n\tFWSCR3 = 32012,\n\tFWSCR4 = 32016,\n\tFWSCR5 = 32020,\n\tFWSCR6 = 32024,\n\tFWSCR7 = 32028,\n\tFWSCR8 = 32032,\n\tFWSCR9 = 32036,\n\tFWSCR10 = 32040,\n\tFWSCR11 = 32044,\n\tFWSCR12 = 32048,\n\tFWSCR13 = 32052,\n\tFWSCR14 = 32056,\n\tFWSCR15 = 32060,\n\tFWSCR16 = 32064,\n\tFWSCR17 = 32068,\n\tFWSCR18 = 32072,\n\tFWSCR19 = 32076,\n\tFWSCR20 = 32080,\n\tFWSCR21 = 32084,\n\tFWSCR22 = 32088,\n\tFWSCR23 = 32092,\n\tFWSCR24 = 32096,\n\tFWSCR25 = 32100,\n\tFWSCR26 = 32104,\n\tFWSCR27 = 32108,\n\tFWSCR28 = 32112,\n\tFWSCR29 = 32116,\n\tFWSCR30 = 32120,\n\tFWSCR31 = 32124,\n\tFWSCR32 = 32128,\n\tFWSCR33 = 32132,\n\tFWSCR34 = 32136,\n\tFWSCR35 = 32140,\n\tFWSCR36 = 32144,\n\tFWSCR37 = 32148,\n\tFWSCR38 = 32152,\n\tFWSCR39 = 32156,\n\tFWSCR40 = 32160,\n\tFWSCR41 = 32164,\n\tFWSCR42 = 32168,\n\tFWSCR43 = 32172,\n\tFWSCR44 = 32176,\n\tFWSCR45 = 32180,\n\tFWSCR46 = 32184,\n\tTPEMIMC0 = 32768,\n\tTPEMIMC1 = 32772,\n\tTPEMIMC2 = 32776,\n\tTPEMIMC3 = 32780,\n\tTPEMIMC4 = 32784,\n\tTPEMIMC5 = 32788,\n\tTPEMIMC60 = 32896,\n\tTPEMIMC70 = 33024,\n\tTSIM = 34560,\n\tTFIM = 34564,\n\tTCIM = 34568,\n\tTGIM0 = 34576,\n\tTGIM1 = 34580,\n\tTEIM0 = 34592,\n\tTEIM1 = 34596,\n\tTEIM2 = 34600,\n\tRIPV = 36864,\n\tRRC = 36868,\n\tRCEC = 36872,\n\tRCDC = 36876,\n\tRSSIS = 36880,\n\tRSSIE = 36884,\n\tRSSID = 36888,\n\tCABPIBWMC = 36896,\n\tCABPWMLC = 36928,\n\tCABPPFLC0 = 36944,\n\tCABPPWMLC0 = 36960,\n\tCABPPPFLC00 = 37024,\n\tCABPULC = 37120,\n\tCABPIRM = 37184,\n\tCABPPCM = 37188,\n\tCABPLCM = 37192,\n\tCABPCPM = 37248,\n\tCABPMCPM = 37376,\n\tCARDNM = 37504,\n\tCARDMNM = 37508,\n\tCARDCN = 37520,\n\tCAEIS0 = 37632,\n\tCAEIE0 = 37636,\n\tCAEID0 = 37640,\n\tCAEIS1 = 37648,\n\tCAEIE1 = 37652,\n\tCAEID1 = 37656,\n\tCAMIS0 = 37696,\n\tCAMIE0 = 37700,\n\tCAMID0 = 37704,\n\tCAMIS1 = 37712,\n\tCAMIE1 = 37716,\n\tCAMID1 = 37720,\n\tCASCR = 37760,\n\tEAMC = 0,\n\tEAMS = 4,\n\tEAIRC = 16,\n\tEATDQSC = 20,\n\tEATDQC = 24,\n\tEATDQAC = 28,\n\tEATPEC = 32,\n\tEATMFSC0 = 64,\n\tEATDQDC0 = 96,\n\tEATDQM0 = 128,\n\tEATDQMLM0 = 160,\n\tEACTQC = 256,\n\tEACTDQDC = 260,\n\tEACTDQM = 264,\n\tEACTDQMLM = 268,\n\tEAVCC = 304,\n\tEAVTC = 308,\n\tEATTFC = 312,\n\tEACAEC = 512,\n\tEACC = 516,\n\tEACAIVC0 = 544,\n\tEACAULC0 = 576,\n\tEACOEM = 608,\n\tEACOIVM0 = 640,\n\tEACOULM0 = 672,\n\tEACGSM = 704,\n\tEATASC = 768,\n\tEATASENC0 = 800,\n\tEATASCTENC = 832,\n\tEATASENM0 = 864,\n\tEATASCTENM = 896,\n\tEATASCSTC0 = 928,\n\tEATASCSTC1 = 932,\n\tEATASCSTM0 = 936,\n\tEATASCSTM1 = 940,\n\tEATASCTC = 944,\n\tEATASCTM = 948,\n\tEATASGL0 = 960,\n\tEATASGL1 = 964,\n\tEATASGLR = 968,\n\tEATASGR = 976,\n\tEATASGRR = 980,\n\tEATASHCC = 992,\n\tEATASRIRM = 996,\n\tEATASSM = 1000,\n\tEAUSMFSECN = 1024,\n\tEATFECN = 1028,\n\tEAFSECN = 1032,\n\tEADQOECN = 1036,\n\tEADQSECN = 1040,\n\tEACKSECN = 1044,\n\tEAEIS0 = 1280,\n\tEAEIE0 = 1284,\n\tEAEID0 = 1288,\n\tEAEIS1 = 1296,\n\tEAEIE1 = 1300,\n\tEAEID1 = 1304,\n\tEAEIS2 = 1312,\n\tEAEIE2 = 1316,\n\tEAEID2 = 1320,\n\tEASCR = 1408,\n\tMPSM = 4096,\n\tMPIC = 4100,\n\tMPIM = 4104,\n\tMIOC = 4112,\n\tMIOM = 4116,\n\tMXMS = 4120,\n\tMTFFC = 4128,\n\tMTPFC = 4132,\n\tMTPFC2 = 4136,\n\tMTPFC30 = 4144,\n\tMTATC0 = 4176,\n\tMTIM = 4192,\n\tMRGC = 4224,\n\tMRMAC0 = 4228,\n\tMRMAC1 = 4232,\n\tMRAFC = 4236,\n\tMRSCE = 4240,\n\tMRSCP = 4244,\n\tMRSCC = 4248,\n\tMRFSCE = 4252,\n\tMRFSCP = 4256,\n\tMTRC = 4260,\n\tMRIM = 4264,\n\tMRPFM = 4268,\n\tMPFC0 = 4352,\n\tMLVC = 4480,\n\tMEEEC = 4484,\n\tMLBC = 4488,\n\tMXGMIIC = 4496,\n\tMPCH = 4500,\n\tMANC = 4504,\n\tMANM = 4508,\n\tMPLCA1 = 4512,\n\tMPLCA2 = 4516,\n\tMPLCA3 = 4520,\n\tMPLCA4 = 4524,\n\tMPLCAM = 4528,\n\tMHDC1 = 4544,\n\tMHDC2 = 4548,\n\tMEIS = 4608,\n\tMEIE = 4612,\n\tMEID = 4616,\n\tMMIS0 = 4624,\n\tMMIE0 = 4628,\n\tMMID0 = 4632,\n\tMMIS1 = 4640,\n\tMMIE1 = 4644,\n\tMMID1 = 4648,\n\tMMIS2 = 4656,\n\tMMIE2 = 4660,\n\tMMID2 = 4664,\n\tMMPFTCT = 4864,\n\tMAPFTCT = 4868,\n\tMPFRCT = 4872,\n\tMFCICT = 4876,\n\tMEEECT = 4880,\n\tMMPCFTCT0 = 4896,\n\tMAPCFTCT0 = 4912,\n\tMPCFRCT0 = 4928,\n\tMHDCC = 4944,\n\tMROVFC = 4948,\n\tMRHCRCEC = 4952,\n\tMRXBCE = 5120,\n\tMRXBCP = 5124,\n\tMRGFCE = 5128,\n\tMRGFCP = 5132,\n\tMRBFC = 5136,\n\tMRMFC = 5140,\n\tMRUFC = 5144,\n\tMRPEFC = 5148,\n\tMRNEFC = 5152,\n\tMRFMEFC = 5156,\n\tMRFFMEFC = 5160,\n\tMRCFCEFC = 5164,\n\tMRFCEFC = 5168,\n\tMRRCFEFC = 5172,\n\tMRUEFC = 5180,\n\tMROEFC = 5184,\n\tMRBOEC = 5188,\n\tMTXBCE = 5376,\n\tMTXBCP = 5380,\n\tMTGFCE = 5384,\n\tMTGFCP = 5388,\n\tMTBFC = 5392,\n\tMTMFC = 5396,\n\tMTUFC = 5400,\n\tMTEFC = 5404,\n\tGWMC = 65536,\n\tGWMS = 65540,\n\tGWIRC = 65552,\n\tGWRDQSC = 65556,\n\tGWRDQC = 65560,\n\tGWRDQAC = 65564,\n\tGWRGC = 65568,\n\tGWRMFSC0 = 65600,\n\tGWRDQDC0 = 65632,\n\tGWRDQM0 = 65664,\n\tGWRDQMLM0 = 65696,\n\tGWMTIRM = 65792,\n\tGWMSTLS = 65796,\n\tGWMSTLR = 65800,\n\tGWMSTSS = 65804,\n\tGWMSTSR = 65808,\n\tGWMAC0 = 65824,\n\tGWMAC1 = 65828,\n\tGWVCC = 65840,\n\tGWVTC = 65844,\n\tGWTTFC = 65848,\n\tGWTDCAC00 = 65856,\n\tGWTDCAC10 = 65860,\n\tGWTSDCC0 = 65888,\n\tGWTNM = 65920,\n\tGWTMNM = 65924,\n\tGWAC = 65936,\n\tGWDCBAC0 = 65940,\n\tGWDCBAC1 = 65944,\n\tGWIICBSC = 65948,\n\tGWMDNC = 65952,\n\tGWTRC0 = 66048,\n\tGWTPC0 = 66304,\n\tGWARIRM = 66432,\n\tGWDCC0 = 66560,\n\tGWAARSS = 67584,\n\tGWAARSR0 = 67588,\n\tGWAARSR1 = 67592,\n\tGWIDAUAS0 = 67648,\n\tGWIDASM0 = 67712,\n\tGWIDASAM00 = 67840,\n\tGWIDASAM10 = 67844,\n\tGWIDACAM00 = 67968,\n\tGWIDACAM10 = 67972,\n\tGWGRLC = 68096,\n\tGWGRLULC = 68100,\n\tGWRLIVC0 = 68224,\n\tGWRLULC0 = 68228,\n\tGWIDPC = 68352,\n\tGWIDC0 = 68608,\n\tGWDIS0 = 69888,\n\tGWDIE0 = 69892,\n\tGWDID0 = 69896,\n\tGWTSDIS = 70016,\n\tGWTSDIE = 70020,\n\tGWTSDID = 70024,\n\tGWEIS0 = 70032,\n\tGWEIE0 = 70036,\n\tGWEID0 = 70040,\n\tGWEIS1 = 70048,\n\tGWEIE1 = 70052,\n\tGWEID1 = 70056,\n\tGWEIS20 = 70144,\n\tGWEIE20 = 70148,\n\tGWEID20 = 70152,\n\tGWEIS3 = 70272,\n\tGWEIE3 = 70276,\n\tGWEID3 = 70280,\n\tGWEIS4 = 70288,\n\tGWEIE4 = 70292,\n\tGWEID4 = 70296,\n\tGWEIS5 = 70304,\n\tGWEIE5 = 70308,\n\tGWEID5 = 70312,\n\tGWSCR0 = 71680,\n\tGWSCR1 = 71936,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtd13xxd_iso_pins {\n\tRTD1319D_ISO_GPIO_0 = 0,\n\tRTD1319D_ISO_GPIO_1 = 1,\n\tRTD1319D_ISO_GPIO_2 = 2,\n\tRTD1319D_ISO_GPIO_3 = 3,\n\tRTD1319D_ISO_GPIO_4 = 4,\n\tRTD1319D_ISO_GPIO_5 = 5,\n\tRTD1319D_ISO_GPIO_6 = 6,\n\tRTD1319D_ISO_GPIO_7 = 7,\n\tRTD1319D_ISO_GPIO_8 = 8,\n\tRTD1319D_ISO_GPIO_9 = 9,\n\tRTD1319D_ISO_GPIO_10 = 10,\n\tRTD1319D_ISO_GPIO_11 = 11,\n\tRTD1319D_ISO_GPIO_12 = 12,\n\tRTD1319D_ISO_GPIO_13 = 13,\n\tRTD1319D_ISO_GPIO_14 = 14,\n\tRTD1319D_ISO_GPIO_15 = 15,\n\tRTD1319D_ISO_GPIO_16 = 16,\n\tRTD1319D_ISO_GPIO_17 = 17,\n\tRTD1319D_ISO_GPIO_18 = 18,\n\tRTD1319D_ISO_GPIO_19 = 19,\n\tRTD1319D_ISO_GPIO_20 = 20,\n\tRTD1319D_ISO_GPIO_21 = 21,\n\tRTD1319D_ISO_GPIO_22 = 22,\n\tRTD1319D_ISO_GPIO_23 = 23,\n\tRTD1319D_ISO_USB_CC2 = 24,\n\tRTD1319D_ISO_GPIO_25 = 25,\n\tRTD1319D_ISO_GPIO_26 = 26,\n\tRTD1319D_ISO_GPIO_27 = 27,\n\tRTD1319D_ISO_GPIO_28 = 28,\n\tRTD1319D_ISO_GPIO_29 = 29,\n\tRTD1319D_ISO_GPIO_30 = 30,\n\tRTD1319D_ISO_GPIO_31 = 31,\n\tRTD1319D_ISO_GPIO_32 = 32,\n\tRTD1319D_ISO_GPIO_33 = 33,\n\tRTD1319D_ISO_GPIO_34 = 34,\n\tRTD1319D_ISO_GPIO_35 = 35,\n\tRTD1319D_ISO_HIF_DATA = 36,\n\tRTD1319D_ISO_HIF_EN = 37,\n\tRTD1319D_ISO_HIF_RDY = 38,\n\tRTD1319D_ISO_HIF_CLK = 39,\n\tRTD1319D_ISO_GPIO_40 = 40,\n\tRTD1319D_ISO_GPIO_41 = 41,\n\tRTD1319D_ISO_GPIO_42 = 42,\n\tRTD1319D_ISO_GPIO_43 = 43,\n\tRTD1319D_ISO_GPIO_44 = 44,\n\tRTD1319D_ISO_GPIO_45 = 45,\n\tRTD1319D_ISO_GPIO_46 = 46,\n\tRTD1319D_ISO_GPIO_47 = 47,\n\tRTD1319D_ISO_GPIO_48 = 48,\n\tRTD1319D_ISO_GPIO_49 = 49,\n\tRTD1319D_ISO_GPIO_50 = 50,\n\tRTD1319D_ISO_USB_CC1 = 51,\n\tRTD1319D_ISO_GPIO_52 = 52,\n\tRTD1319D_ISO_GPIO_53 = 53,\n\tRTD1319D_ISO_IR_RX = 54,\n\tRTD1319D_ISO_UR0_RX = 55,\n\tRTD1319D_ISO_UR0_TX = 56,\n\tRTD1319D_ISO_GPIO_57 = 57,\n\tRTD1319D_ISO_GPIO_58 = 58,\n\tRTD1319D_ISO_GPIO_59 = 59,\n\tRTD1319D_ISO_GPIO_60 = 60,\n\tRTD1319D_ISO_GPIO_61 = 61,\n\tRTD1319D_ISO_GPIO_62 = 62,\n\tRTD1319D_ISO_GPIO_63 = 63,\n\tRTD1319D_ISO_GPIO_64 = 64,\n\tRTD1319D_ISO_EMMC_RST_N = 65,\n\tRTD1319D_ISO_EMMC_DD_SB = 66,\n\tRTD1319D_ISO_EMMC_CLK = 67,\n\tRTD1319D_ISO_EMMC_CMD = 68,\n\tRTD1319D_ISO_EMMC_DATA_0 = 69,\n\tRTD1319D_ISO_EMMC_DATA_1 = 70,\n\tRTD1319D_ISO_EMMC_DATA_2 = 71,\n\tRTD1319D_ISO_EMMC_DATA_3 = 72,\n\tRTD1319D_ISO_EMMC_DATA_4 = 73,\n\tRTD1319D_ISO_EMMC_DATA_5 = 74,\n\tRTD1319D_ISO_EMMC_DATA_6 = 75,\n\tRTD1319D_ISO_EMMC_DATA_7 = 76,\n\tRTD1319D_ISO_GPIO_DUMMY_77 = 77,\n\tRTD1319D_ISO_GPIO_78 = 78,\n\tRTD1319D_ISO_GPIO_79 = 79,\n\tRTD1319D_ISO_GPIO_80 = 80,\n\tRTD1319D_ISO_GPIO_81 = 81,\n\tRTD1319D_ISO_UR2_LOC = 82,\n\tRTD1319D_ISO_GSPI_LOC = 83,\n\tRTD1319D_ISO_HI_WIDTH = 84,\n\tRTD1319D_ISO_SF_EN = 85,\n\tRTD1319D_ISO_ARM_TRACE_DBG_EN = 86,\n\tRTD1319D_ISO_EJTAG_AUCPU_LOC = 87,\n\tRTD1319D_ISO_EJTAG_ACPU_LOC = 88,\n\tRTD1319D_ISO_EJTAG_VCPU_LOC = 89,\n\tRTD1319D_ISO_EJTAG_SCPU_LOC = 90,\n\tRTD1319D_ISO_DMIC_LOC = 91,\n\tRTD1319D_ISO_EJTAG_SECPU_LOC = 92,\n\tRTD1319D_ISO_VTC_DMIC_LOC = 93,\n\tRTD1319D_ISO_VTC_TDM_LOC = 94,\n\tRTD1319D_ISO_VTC_I2SI_LOC = 95,\n\tRTD1319D_ISO_TDM_AI_LOC = 96,\n\tRTD1319D_ISO_AI_LOC = 97,\n\tRTD1319D_ISO_SPDIF_LOC = 98,\n\tRTD1319D_ISO_HIF_EN_LOC = 99,\n\tRTD1319D_ISO_SC0_LOC = 100,\n\tRTD1319D_ISO_SC1_LOC = 101,\n\tRTD1319D_ISO_SCAN_SWITCH = 102,\n\tRTD1319D_ISO_WD_RSET = 103,\n\tRTD1319D_ISO_BOOT_SEL = 104,\n\tRTD1319D_ISO_RESET_N = 105,\n\tRTD1319D_ISO_TESTMODE = 106,\n};\n\nenum rtd13xxe_iso_pins {\n\tRTD1315E_ISO_GPIO_0 = 0,\n\tRTD1315E_ISO_GPIO_1 = 1,\n\tRTD1315E_ISO_EMMC_RST_N = 2,\n\tRTD1315E_ISO_EMMC_DD_SB = 3,\n\tRTD1315E_ISO_EMMC_CLK = 4,\n\tRTD1315E_ISO_EMMC_CMD = 5,\n\tRTD1315E_ISO_GPIO_6 = 6,\n\tRTD1315E_ISO_GPIO_7 = 7,\n\tRTD1315E_ISO_GPIO_8 = 8,\n\tRTD1315E_ISO_GPIO_9 = 9,\n\tRTD1315E_ISO_GPIO_10 = 10,\n\tRTD1315E_ISO_GPIO_11 = 11,\n\tRTD1315E_ISO_GPIO_12 = 12,\n\tRTD1315E_ISO_GPIO_13 = 13,\n\tRTD1315E_ISO_GPIO_14 = 14,\n\tRTD1315E_ISO_GPIO_15 = 15,\n\tRTD1315E_ISO_GPIO_16 = 16,\n\tRTD1315E_ISO_GPIO_17 = 17,\n\tRTD1315E_ISO_GPIO_18 = 18,\n\tRTD1315E_ISO_GPIO_19 = 19,\n\tRTD1315E_ISO_GPIO_20 = 20,\n\tRTD1315E_ISO_EMMC_DATA_0 = 21,\n\tRTD1315E_ISO_EMMC_DATA_1 = 22,\n\tRTD1315E_ISO_EMMC_DATA_2 = 23,\n\tRTD1315E_ISO_USB_CC2 = 24,\n\tRTD1315E_ISO_GPIO_25 = 25,\n\tRTD1315E_ISO_GPIO_26 = 26,\n\tRTD1315E_ISO_GPIO_27 = 27,\n\tRTD1315E_ISO_GPIO_28 = 28,\n\tRTD1315E_ISO_GPIO_29 = 29,\n\tRTD1315E_ISO_GPIO_30 = 30,\n\tRTD1315E_ISO_GPIO_31 = 31,\n\tRTD1315E_ISO_GPIO_32 = 32,\n\tRTD1315E_ISO_GPIO_33 = 33,\n\tRTD1315E_ISO_GPIO_34 = 34,\n\tRTD1315E_ISO_GPIO_35 = 35,\n\tRTD1315E_ISO_HIF_DATA = 36,\n\tRTD1315E_ISO_HIF_EN = 37,\n\tRTD1315E_ISO_HIF_RDY = 38,\n\tRTD1315E_ISO_HIF_CLK = 39,\n\tRTD1315E_ISO_GPIO_DUMMY_40 = 40,\n\tRTD1315E_ISO_GPIO_DUMMY_41 = 41,\n\tRTD1315E_ISO_GPIO_DUMMY_42 = 42,\n\tRTD1315E_ISO_GPIO_DUMMY_43 = 43,\n\tRTD1315E_ISO_GPIO_DUMMY_44 = 44,\n\tRTD1315E_ISO_GPIO_DUMMY_45 = 45,\n\tRTD1315E_ISO_GPIO_46 = 46,\n\tRTD1315E_ISO_GPIO_47 = 47,\n\tRTD1315E_ISO_GPIO_48 = 48,\n\tRTD1315E_ISO_GPIO_49 = 49,\n\tRTD1315E_ISO_GPIO_50 = 50,\n\tRTD1315E_ISO_USB_CC1 = 51,\n\tRTD1315E_ISO_EMMC_DATA_3 = 52,\n\tRTD1315E_ISO_EMMC_DATA_4 = 53,\n\tRTD1315E_ISO_IR_RX = 54,\n\tRTD1315E_ISO_UR0_RX = 55,\n\tRTD1315E_ISO_UR0_TX = 56,\n\tRTD1315E_ISO_GPIO_57 = 57,\n\tRTD1315E_ISO_GPIO_58 = 58,\n\tRTD1315E_ISO_GPIO_59 = 59,\n\tRTD1315E_ISO_GPIO_60 = 60,\n\tRTD1315E_ISO_GPIO_61 = 61,\n\tRTD1315E_ISO_GPIO_62 = 62,\n\tRTD1315E_ISO_GPIO_DUMMY_63 = 63,\n\tRTD1315E_ISO_GPIO_DUMMY_64 = 64,\n\tRTD1315E_ISO_GPIO_DUMMY_65 = 65,\n\tRTD1315E_ISO_GPIO_66 = 66,\n\tRTD1315E_ISO_GPIO_67 = 67,\n\tRTD1315E_ISO_GPIO_68 = 68,\n\tRTD1315E_ISO_GPIO_69 = 69,\n\tRTD1315E_ISO_GPIO_70 = 70,\n\tRTD1315E_ISO_GPIO_71 = 71,\n\tRTD1315E_ISO_GPIO_72 = 72,\n\tRTD1315E_ISO_GPIO_DUMMY_73 = 73,\n\tRTD1315E_ISO_EMMC_DATA_5 = 74,\n\tRTD1315E_ISO_EMMC_DATA_6 = 75,\n\tRTD1315E_ISO_EMMC_DATA_7 = 76,\n\tRTD1315E_ISO_GPIO_DUMMY_77 = 77,\n\tRTD1315E_ISO_GPIO_78 = 78,\n\tRTD1315E_ISO_GPIO_79 = 79,\n\tRTD1315E_ISO_GPIO_80 = 80,\n\tRTD1315E_ISO_GPIO_81 = 81,\n\tRTD1315E_ISO_UR2_LOC = 82,\n\tRTD1315E_ISO_GSPI_LOC = 83,\n\tRTD1315E_ISO_HI_WIDTH = 84,\n\tRTD1315E_ISO_SF_EN = 85,\n\tRTD1315E_ISO_ARM_TRACE_DBG_EN = 86,\n\tRTD1315E_ISO_EJTAG_AUCPU_LOC = 87,\n\tRTD1315E_ISO_EJTAG_ACPU_LOC = 88,\n\tRTD1315E_ISO_EJTAG_VCPU_LOC = 89,\n\tRTD1315E_ISO_EJTAG_SCPU_LOC = 90,\n\tRTD1315E_ISO_DMIC_LOC = 91,\n\tRTD1315E_ISO_VTC_DMIC_LOC = 92,\n\tRTD1315E_ISO_VTC_TDM_LOC = 93,\n\tRTD1315E_ISO_VTC_I2SI_LOC = 94,\n\tRTD1315E_ISO_TDM_AI_LOC = 95,\n\tRTD1315E_ISO_AI_LOC = 96,\n\tRTD1315E_ISO_SPDIF_LOC = 97,\n\tRTD1315E_ISO_HIF_EN_LOC = 98,\n\tRTD1315E_ISO_SCAN_SWITCH = 99,\n\tRTD1315E_ISO_WD_RSET = 100,\n\tRTD1315E_ISO_BOOT_SEL = 101,\n\tRTD1315E_ISO_RESET_N = 102,\n\tRTD1315E_ISO_TESTMODE = 103,\n};\n\nenum rtd16xxb_iso_pins {\n\tRTD1619B_ISO_GPIO_0 = 0,\n\tRTD1619B_ISO_GPIO_1 = 1,\n\tRTD1619B_ISO_GPIO_2 = 2,\n\tRTD1619B_ISO_GPIO_3 = 3,\n\tRTD1619B_ISO_GPIO_4 = 4,\n\tRTD1619B_ISO_GPIO_5 = 5,\n\tRTD1619B_ISO_GPIO_6 = 6,\n\tRTD1619B_ISO_GPIO_7 = 7,\n\tRTD1619B_ISO_GPIO_8 = 8,\n\tRTD1619B_ISO_GPIO_9 = 9,\n\tRTD1619B_ISO_GPIO_10 = 10,\n\tRTD1619B_ISO_GPIO_11 = 11,\n\tRTD1619B_ISO_GPIO_12 = 12,\n\tRTD1619B_ISO_GPIO_13 = 13,\n\tRTD1619B_ISO_GPIO_14 = 14,\n\tRTD1619B_ISO_GPIO_15 = 15,\n\tRTD1619B_ISO_GPIO_16 = 16,\n\tRTD1619B_ISO_GPIO_17 = 17,\n\tRTD1619B_ISO_GPIO_18 = 18,\n\tRTD1619B_ISO_GPIO_19 = 19,\n\tRTD1619B_ISO_GPIO_20 = 20,\n\tRTD1619B_ISO_GPIO_21 = 21,\n\tRTD1619B_ISO_GPIO_22 = 22,\n\tRTD1619B_ISO_GPIO_23 = 23,\n\tRTD1619B_ISO_USB_CC2 = 24,\n\tRTD1619B_ISO_GPIO_25 = 25,\n\tRTD1619B_ISO_GPIO_26 = 26,\n\tRTD1619B_ISO_GPIO_27 = 27,\n\tRTD1619B_ISO_GPIO_28 = 28,\n\tRTD1619B_ISO_GPIO_29 = 29,\n\tRTD1619B_ISO_GPIO_30 = 30,\n\tRTD1619B_ISO_GPIO_31 = 31,\n\tRTD1619B_ISO_GPIO_32 = 32,\n\tRTD1619B_ISO_GPIO_33 = 33,\n\tRTD1619B_ISO_GPIO_34 = 34,\n\tRTD1619B_ISO_GPIO_35 = 35,\n\tRTD1619B_ISO_HIF_DATA = 36,\n\tRTD1619B_ISO_HIF_EN = 37,\n\tRTD1619B_ISO_HIF_RDY = 38,\n\tRTD1619B_ISO_HIF_CLK = 39,\n\tRTD1619B_ISO_GPIO_40 = 40,\n\tRTD1619B_ISO_GPIO_41 = 41,\n\tRTD1619B_ISO_GPIO_42 = 42,\n\tRTD1619B_ISO_GPIO_43 = 43,\n\tRTD1619B_ISO_GPIO_44 = 44,\n\tRTD1619B_ISO_GPIO_45 = 45,\n\tRTD1619B_ISO_GPIO_46 = 46,\n\tRTD1619B_ISO_GPIO_47 = 47,\n\tRTD1619B_ISO_GPIO_48 = 48,\n\tRTD1619B_ISO_GPIO_49 = 49,\n\tRTD1619B_ISO_GPIO_50 = 50,\n\tRTD1619B_ISO_USB_CC1 = 51,\n\tRTD1619B_ISO_GPIO_52 = 52,\n\tRTD1619B_ISO_GPIO_53 = 53,\n\tRTD1619B_ISO_IR_RX = 54,\n\tRTD1619B_ISO_UR0_RX = 55,\n\tRTD1619B_ISO_UR0_TX = 56,\n\tRTD1619B_ISO_GPIO_57 = 57,\n\tRTD1619B_ISO_GPIO_58 = 58,\n\tRTD1619B_ISO_GPIO_59 = 59,\n\tRTD1619B_ISO_GPIO_60 = 60,\n\tRTD1619B_ISO_GPIO_61 = 61,\n\tRTD1619B_ISO_GPIO_62 = 62,\n\tRTD1619B_ISO_GPIO_63 = 63,\n\tRTD1619B_ISO_GPIO_64 = 64,\n\tRTD1619B_ISO_GPIO_65 = 65,\n\tRTD1619B_ISO_GPIO_66 = 66,\n\tRTD1619B_ISO_GPIO_67 = 67,\n\tRTD1619B_ISO_GPIO_68 = 68,\n\tRTD1619B_ISO_GPIO_69 = 69,\n\tRTD1619B_ISO_GPIO_70 = 70,\n\tRTD1619B_ISO_GPIO_71 = 71,\n\tRTD1619B_ISO_GPIO_72 = 72,\n\tRTD1619B_ISO_GPIO_73 = 73,\n\tRTD1619B_ISO_GPIO_74 = 74,\n\tRTD1619B_ISO_GPIO_75 = 75,\n\tRTD1619B_ISO_GPIO_76 = 76,\n\tRTD1619B_ISO_EMMC_CMD = 77,\n\tRTD1619B_ISO_SPI_CE_N = 78,\n\tRTD1619B_ISO_SPI_SCK = 79,\n\tRTD1619B_ISO_SPI_SO = 80,\n\tRTD1619B_ISO_SPI_SI = 81,\n\tRTD1619B_ISO_EMMC_RST_N = 82,\n\tRTD1619B_ISO_EMMC_DD_SB = 83,\n\tRTD1619B_ISO_EMMC_CLK = 84,\n\tRTD1619B_ISO_EMMC_DATA_0 = 85,\n\tRTD1619B_ISO_EMMC_DATA_1 = 86,\n\tRTD1619B_ISO_EMMC_DATA_2 = 87,\n\tRTD1619B_ISO_EMMC_DATA_3 = 88,\n\tRTD1619B_ISO_EMMC_DATA_4 = 89,\n\tRTD1619B_ISO_EMMC_DATA_5 = 90,\n\tRTD1619B_ISO_EMMC_DATA_6 = 91,\n\tRTD1619B_ISO_EMMC_DATA_7 = 92,\n\tRTD1619B_ISO_UR2_LOC = 93,\n\tRTD1619B_ISO_GSPI_LOC = 94,\n\tRTD1619B_ISO_SDIO_LOC = 95,\n\tRTD1619B_ISO_HI_LOC = 96,\n\tRTD1619B_ISO_HI_WIDTH = 97,\n\tRTD1619B_ISO_SF_EN = 98,\n\tRTD1619B_ISO_ARM_TRACE_DBG_EN = 99,\n\tRTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0 = 100,\n\tRTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0 = 101,\n\tRTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1 = 102,\n\tRTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1 = 103,\n\tRTD1619B_ISO_EJTAG_ACPU_LOC = 104,\n\tRTD1619B_ISO_EJTAG_VCPU_LOC = 105,\n\tRTD1619B_ISO_EJTAG_SCPU_LOC = 106,\n\tRTD1619B_ISO_DMIC_LOC = 107,\n\tRTD1619B_ISO_ISO_GSPI_LOC = 108,\n\tRTD1619B_ISO_EJTAG_VE3_LOC = 109,\n\tRTD1619B_ISO_EJTAG_AUCPU0_LOC = 110,\n\tRTD1619B_ISO_EJTAG_AUCPU1_LOC = 111,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum rtsn_mode {\n\tOCR_OPC_DISABLE = 0,\n\tOCR_OPC_CONFIG = 1,\n\tOCR_OPC_OPERATION = 2,\n};\n\nenum rtsn_reg {\n\tAXIWC = 0,\n\tAXIRC = 4,\n\tTDPC0 = 16,\n\tTFT = 144,\n\tTATLS0 = 160,\n\tTATLS1 = 164,\n\tTATLR = 168,\n\tRATLS0 = 176,\n\tRATLS1 = 180,\n\tRATLR = 184,\n\tTSA0 = 192,\n\tTSS0 = 196,\n\tTRCR0 = 320,\n\tRIDAUAS0 = 384,\n\tRR = 512,\n\tTATS = 528,\n\tTATSR0 = 532,\n\tTATSR1 = 536,\n\tTATSR2 = 540,\n\tRATS = 544,\n\tRATSR0 = 548,\n\tRATSR1 = 552,\n\tRATSR2 = 556,\n\tRIDASM0 = 576,\n\tRIDASAM0 = 580,\n\tRIDACAM0 = 584,\n\tEIS0 = 768,\n\tEIE0 = 772,\n\tEID0 = 776,\n\tEIS1 = 784,\n\tEIE1 = 788,\n\tEID1 = 792,\n\tTCEIS0 = 832,\n\tTCEIE0 = 836,\n\tTCEID0 = 840,\n\tRFSEIS0 = 1216,\n\tRFSEIE0 = 1220,\n\tRFSEID0 = 1224,\n\tRFEIS0 = 1344,\n\tRFEIE0 = 1348,\n\tRFEID0 = 1352,\n\tRCEIS0 = 1472,\n\tRCEIE0 = 1476,\n\tRCEID0 = 1480,\n\tRIDAOIS = 1600,\n\tRIDAOIE = 1604,\n\tRIDAOID = 1608,\n\tTSFEIS = 1728,\n\tTSFEIE = 1732,\n\tTSFEID = 1736,\n\tTSCEIS = 1744,\n\tTSCEIE = 1748,\n\tTSCEID = 1752,\n\tDIS___2 = 2816,\n\tDIE___2 = 2820,\n\tDID = 2824,\n\tTDIS0 = 2832,\n\tTDIE0 = 2836,\n\tTDID0 = 2840,\n\tRDIS0 = 2960,\n\tRDIE0 = 2964,\n\tRDID0 = 2968,\n\tTSDIS = 3088,\n\tTSDIE = 3092,\n\tTSDID = 3096,\n\tGPOUT = 24576,\n\tOCR = 4096,\n\tOSR = 4100,\n\tSWR = 4104,\n\tSIS = 4108,\n\tGIS___2 = 4112,\n\tGIE___2 = 4116,\n\tGID___2 = 4120,\n\tTIS1 = 4128,\n\tTIE1 = 4132,\n\tTID1 = 4136,\n\tTIS2 = 4144,\n\tTIE2 = 4148,\n\tTID2 = 4152,\n\tRIS = 4160,\n\tRIE = 4164,\n\tRID = 4168,\n\tTGC1 = 4176,\n\tTGC2 = 4180,\n\tTFS0 = 4192,\n\tTCF0 = 4208,\n\tTCR1 = 4224,\n\tTCR2 = 4228,\n\tTCR3 = 4232,\n\tTCR4 = 4236,\n\tTMS0 = 4240,\n\tTSR1 = 4272,\n\tTSR2 = 4276,\n\tTSR3 = 4280,\n\tTSR4 = 4284,\n\tTSR5 = 4288,\n\tRGC = 4304,\n\tRDFCR = 4308,\n\tRCFCR = 4312,\n\tREFCNCR = 4316,\n\tRSR1 = 4320,\n\tRSR2 = 4324,\n\tRSR3 = 4328,\n\tTCIS = 4576,\n\tTCIE = 4580,\n\tTCID = 4584,\n\tTPTPC = 4592,\n\tTTML = 4596,\n\tTTJ = 4600,\n\tTCC = 4608,\n\tTCS = 4612,\n\tTGS = 4620,\n\tTACST0 = 4624,\n\tTACST1 = 4628,\n\tTACST2 = 4632,\n\tTALIT0 = 4640,\n\tTALIT1 = 4644,\n\tTALIT2 = 4648,\n\tTAEN0 = 4656,\n\tTAEN1 = 4660,\n\tTASFE = 4672,\n\tTACLL0 = 4688,\n\tTACLL1 = 4692,\n\tTACLL2 = 4696,\n\tCACC = 4704,\n\tCCS = 4708,\n\tCAIV0 = 4720,\n\tCAUL0 = 4752,\n\tTOCST0 = 4864,\n\tTOCST1 = 4868,\n\tTOCST2 = 4872,\n\tTOLIT0 = 4880,\n\tTOLIT1 = 4884,\n\tTOLIT2 = 4888,\n\tTOEN0 = 4896,\n\tTOEN1 = 4900,\n\tTOSFE = 4912,\n\tTCLR0 = 4928,\n\tTCLR1 = 4932,\n\tTCLR2 = 4936,\n\tTSMS = 4944,\n\tCOCC = 4960,\n\tCOIV0 = 5040,\n\tCOUL0 = 5072,\n\tQSTMACU0 = 5120,\n\tQSTMACD0 = 5124,\n\tQSTMAMU0 = 5128,\n\tQSTMAMD0 = 5132,\n\tQSFTVL0 = 5136,\n\tQSFTVLM0 = 5140,\n\tQSFTMSD0 = 5144,\n\tQSFTGMI0 = 5148,\n\tQSFTLS = 5632,\n\tQSFTLIS = 5636,\n\tQSFTLIE = 5640,\n\tQSFTLID = 5644,\n\tQSMSMC = 5648,\n\tQSGTMC = 5652,\n\tQSEIS = 5656,\n\tQSEIE = 5660,\n\tQSEID = 5664,\n\tQGACST0 = 5680,\n\tQGACST1 = 5684,\n\tQGACST2 = 5688,\n\tQGALIT1 = 5696,\n\tQGALIT2 = 5700,\n\tQGAEN0 = 5704,\n\tQGAEN1 = 5964,\n\tQGIGS = 5712,\n\tQGGC = 5716,\n\tQGATL0 = 5732,\n\tQGATL1 = 5736,\n\tQGATL2 = 5740,\n\tQGOCST0 = 5744,\n\tQGOCST1 = 5748,\n\tQGOCST2 = 5752,\n\tQGOLIT0 = 5756,\n\tQGOLIT1 = 5760,\n\tQGOLIT2 = 5764,\n\tQGOEN0 = 5768,\n\tQGOEN1 = 5772,\n\tQGTRO = 5776,\n\tQGTR1 = 5780,\n\tQGTR2 = 5784,\n\tQGFSMS = 5788,\n\tQTMIS = 5856,\n\tQTMIE = 5860,\n\tQTMID = 5864,\n\tQMEC = 5888,\n\tQMMC = 5892,\n\tQRFDC = 5896,\n\tQYFDC = 5900,\n\tQVTCMC0 = 5904,\n\tQMCBSC0 = 5968,\n\tQMCIRC0 = 6032,\n\tQMEBSC0 = 6096,\n\tQMEIRC0 = 5904,\n\tQMCFC = 6224,\n\tQMEIS = 6240,\n\tQMEIE = 6244,\n\tQMEID = 6252,\n\tQSMFC0 = 6256,\n\tQMSPPC0 = 6320,\n\tQMSRPC0 = 6384,\n\tQGPPC0 = 6448,\n\tQGRPC0 = 6480,\n\tQMDPC0 = 6512,\n\tQMGPC0 = 6576,\n\tQMYPC0 = 6640,\n\tQMRPC0 = 6704,\n\tMQSTMACU = 6768,\n\tMQSTMACD = 6772,\n\tMQSTMAMU = 6776,\n\tMQSTMAMD = 6780,\n\tMQSFTVL = 6784,\n\tMQSFTVLM = 6788,\n\tMQSFTMSD = 6792,\n\tMQSFTGMI = 6796,\n\tCFCR0 = 10240,\n\tFMSCR = 11280,\n\tMMC = 14336,\n\tMPSM___2 = 14352,\n\tMPIC___2 = 14356,\n\tMTFFC___2 = 14368,\n\tMTPFC___2 = 14372,\n\tMTATC0___2 = 14400,\n\tMRGC___2 = 14464,\n\tMRMAC0___2 = 14468,\n\tMRMAC1___2 = 14472,\n\tMRAFC___2 = 14476,\n\tMRSCE___2 = 14480,\n\tMRSCP___2 = 14484,\n\tMRSCC___2 = 14488,\n\tMRFSCE___2 = 14492,\n\tMRFSCP___2 = 14496,\n\tMTRC___2 = 14500,\n\tMPFC = 14592,\n\tMLVC___2 = 15168,\n\tMEEEC___2 = 15184,\n\tMLBC___2 = 15200,\n\tMGMR = 15360,\n\tMMPFTCT___2 = 15376,\n\tMAPFTCT___2 = 15380,\n\tMPFRCT___2 = 15384,\n\tMFCICT___2 = 15388,\n\tMEEECT___2 = 15392,\n\tMEIS___2 = 15616,\n\tMEIE___2 = 15620,\n\tMEID___2 = 15624,\n\tMMIS0___2 = 15632,\n\tMMIE0___2 = 15636,\n\tMMID0___2 = 15640,\n\tMMIS1___2 = 15648,\n\tMMIE1___2 = 15652,\n\tMMID1___2 = 15656,\n\tMMIS2___2 = 15664,\n\tMMIE2___2 = 15668,\n\tMMID2___2 = 15672,\n\tMXMS___2 = 15872,\n};\n\nenum rv1126b_plls {\n\tgpll___10 = 0,\n\tcpll___10 = 1,\n\taupll___3 = 2,\n\tdpll___9 = 3,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rwsig_action {\n\tRWSIG_ACTION_ABORT = 0,\n\tRWSIG_ACTION_CONTINUE = 1,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum rx_stats_reg_offset {\n\tRX_OCTS = 0,\n\tRX_UCAST = 1,\n\tRX_BCAST = 2,\n\tRX_MCAST = 3,\n\tRX_RED = 4,\n\tRX_RED_OCTS = 5,\n\tRX_ORUN = 6,\n\tRX_ORUN_OCTS = 7,\n\tRX_FCS = 8,\n\tRX_L2ERR = 9,\n\tRX_DRP_BCAST = 10,\n\tRX_DRP_MCAST = 11,\n\tRX_DRP_L3BCAST = 12,\n\tRX_DRP_L3MCAST = 13,\n\tRX_STATS_ENUM_LAST = 14,\n};\n\nenum rz_dmac_prep_type {\n\tRZ_DMAC_DESC_MEMCPY = 0,\n\tRZ_DMAC_DESC_SLAVE_SG = 1,\n};\n\nenum rz_mtu3_channels {\n\tRZ_MTU3_CHAN_0 = 0,\n\tRZ_MTU3_CHAN_1 = 1,\n\tRZ_MTU3_CHAN_2 = 2,\n\tRZ_MTU3_CHAN_3 = 3,\n\tRZ_MTU3_CHAN_4 = 4,\n\tRZ_MTU3_CHAN_5 = 5,\n\tRZ_MTU3_CHAN_6 = 6,\n\tRZ_MTU3_CHAN_7 = 7,\n\tRZ_MTU3_CHAN_8 = 8,\n\tRZ_MTU_NUM_CHANNELS = 9,\n};\n\nenum rz_wdt_type {\n\tWDT_RZG2L = 0,\n\tWDT_RZV2M = 1,\n};\n\nenum rzg2l_iolh_index {\n\tRZG2L_IOLH_IDX_1V8 = 0,\n\tRZG2L_IOLH_IDX_2V5 = 4,\n\tRZG2L_IOLH_IDX_3V3 = 8,\n\tRZG2L_IOLH_IDX_MAX = 12,\n};\n\nenum rzt2h_clk_types {\n\tCLK_TYPE_RZT2H_DIV = 5,\n\tCLK_TYPE_RZT2H_MUX = 6,\n\tCLK_TYPE_RZT2H_FSELXSPI = 7,\n};\n\nenum rzv2h_wdt_count_source {\n\tCOUNT_SOURCE_LOCO = 0,\n\tCOUNT_SOURCE_PCLK = 1,\n};\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nenum s2mpa01_reg {\n\tS2MPA01_REG_ID = 0,\n\tS2MPA01_REG_INT1 = 1,\n\tS2MPA01_REG_INT2 = 2,\n\tS2MPA01_REG_INT3 = 3,\n\tS2MPA01_REG_INT1M = 4,\n\tS2MPA01_REG_INT2M = 5,\n\tS2MPA01_REG_INT3M = 6,\n\tS2MPA01_REG_ST1 = 7,\n\tS2MPA01_REG_ST2 = 8,\n\tS2MPA01_REG_PWRONSRC = 9,\n\tS2MPA01_REG_OFFSRC = 10,\n\tS2MPA01_REG_RTC_BUF = 11,\n\tS2MPA01_REG_CTRL1 = 12,\n\tS2MPA01_REG_ETC_TEST = 13,\n\tS2MPA01_REG_RSVD1 = 14,\n\tS2MPA01_REG_BU_CHG = 15,\n\tS2MPA01_REG_RAMP1 = 16,\n\tS2MPA01_REG_RAMP2 = 17,\n\tS2MPA01_REG_LDO_DSCH1 = 18,\n\tS2MPA01_REG_LDO_DSCH2 = 19,\n\tS2MPA01_REG_LDO_DSCH3 = 20,\n\tS2MPA01_REG_LDO_DSCH4 = 21,\n\tS2MPA01_REG_OTP_ADRL = 22,\n\tS2MPA01_REG_OTP_ADRH = 23,\n\tS2MPA01_REG_OTP_DATA = 24,\n\tS2MPA01_REG_MON1SEL = 25,\n\tS2MPA01_REG_MON2SEL = 26,\n\tS2MPA01_REG_LEE = 27,\n\tS2MPA01_REG_RSVD2 = 28,\n\tS2MPA01_REG_RSVD3 = 29,\n\tS2MPA01_REG_RSVD4 = 30,\n\tS2MPA01_REG_RSVD5 = 31,\n\tS2MPA01_REG_RSVD6 = 32,\n\tS2MPA01_REG_TOP_RSVD = 33,\n\tS2MPA01_REG_DVS_SEL = 34,\n\tS2MPA01_REG_DVS_PTR = 35,\n\tS2MPA01_REG_DVS_DATA = 36,\n\tS2MPA01_REG_RSVD_NO = 37,\n\tS2MPA01_REG_UVLO = 38,\n\tS2MPA01_REG_LEE_NO = 39,\n\tS2MPA01_REG_B1CTRL1 = 40,\n\tS2MPA01_REG_B1CTRL2 = 41,\n\tS2MPA01_REG_B2CTRL1 = 42,\n\tS2MPA01_REG_B2CTRL2 = 43,\n\tS2MPA01_REG_B3CTRL1 = 44,\n\tS2MPA01_REG_B3CTRL2 = 45,\n\tS2MPA01_REG_B4CTRL1 = 46,\n\tS2MPA01_REG_B4CTRL2 = 47,\n\tS2MPA01_REG_B5CTRL1 = 48,\n\tS2MPA01_REG_B5CTRL2 = 49,\n\tS2MPA01_REG_B5CTRL3 = 50,\n\tS2MPA01_REG_B5CTRL4 = 51,\n\tS2MPA01_REG_B5CTRL5 = 52,\n\tS2MPA01_REG_B5CTRL6 = 53,\n\tS2MPA01_REG_B6CTRL1 = 54,\n\tS2MPA01_REG_B6CTRL2 = 55,\n\tS2MPA01_REG_B7CTRL1 = 56,\n\tS2MPA01_REG_B7CTRL2 = 57,\n\tS2MPA01_REG_B8CTRL1 = 58,\n\tS2MPA01_REG_B8CTRL2 = 59,\n\tS2MPA01_REG_B9CTRL1 = 60,\n\tS2MPA01_REG_B9CTRL2 = 61,\n\tS2MPA01_REG_B10CTRL1 = 62,\n\tS2MPA01_REG_B10CTRL2 = 63,\n\tS2MPA01_REG_L1CTRL = 64,\n\tS2MPA01_REG_L2CTRL = 65,\n\tS2MPA01_REG_L3CTRL = 66,\n\tS2MPA01_REG_L4CTRL = 67,\n\tS2MPA01_REG_L5CTRL = 68,\n\tS2MPA01_REG_L6CTRL = 69,\n\tS2MPA01_REG_L7CTRL = 70,\n\tS2MPA01_REG_L8CTRL = 71,\n\tS2MPA01_REG_L9CTRL = 72,\n\tS2MPA01_REG_L10CTRL = 73,\n\tS2MPA01_REG_L11CTRL = 74,\n\tS2MPA01_REG_L12CTRL = 75,\n\tS2MPA01_REG_L13CTRL = 76,\n\tS2MPA01_REG_L14CTRL = 77,\n\tS2MPA01_REG_L15CTRL = 78,\n\tS2MPA01_REG_L16CTRL = 79,\n\tS2MPA01_REG_L17CTRL = 80,\n\tS2MPA01_REG_L18CTRL = 81,\n\tS2MPA01_REG_L19CTRL = 82,\n\tS2MPA01_REG_L20CTRL = 83,\n\tS2MPA01_REG_L21CTRL = 84,\n\tS2MPA01_REG_L22CTRL = 85,\n\tS2MPA01_REG_L23CTRL = 86,\n\tS2MPA01_REG_L24CTRL = 87,\n\tS2MPA01_REG_L25CTRL = 88,\n\tS2MPA01_REG_L26CTRL = 89,\n\tS2MPA01_REG_LDO_OVCB1 = 90,\n\tS2MPA01_REG_LDO_OVCB2 = 91,\n\tS2MPA01_REG_LDO_OVCB3 = 92,\n\tS2MPA01_REG_LDO_OVCB4 = 93,\n};\n\nenum s2mpg10_common_irq {\n\tS2MPG10_COMMON_IRQ_PMIC = 0,\n\tS2MPG10_COMMON_IRQ_UNUSED = 1,\n};\n\nenum s2mpg10_common_reg {\n\tS2MPG10_COMMON_CHIPID = 0,\n\tS2MPG10_COMMON_INT = 1,\n\tS2MPG10_COMMON_INT_MASK = 2,\n\tS2MPG10_COMMON_SPD_CTRL1 = 10,\n\tS2MPG10_COMMON_SPD_CTRL2 = 11,\n\tS2MPG10_COMMON_SPD_CTRL3 = 12,\n\tS2MPG10_COMMON_MON1SEL = 26,\n\tS2MPG10_COMMON_MON2SEL = 27,\n\tS2MPG10_COMMON_MONR = 28,\n\tS2MPG10_COMMON_DEBUG_CTRL1 = 29,\n\tS2MPG10_COMMON_DEBUG_CTRL2 = 30,\n\tS2MPG10_COMMON_DEBUG_CTRL3 = 31,\n\tS2MPG10_COMMON_DEBUG_CTRL4 = 32,\n\tS2MPG10_COMMON_DEBUG_CTRL5 = 33,\n\tS2MPG10_COMMON_DEBUG_CTRL6 = 34,\n\tS2MPG10_COMMON_DEBUG_CTRL7 = 35,\n\tS2MPG10_COMMON_DEBUG_CTRL8 = 36,\n\tS2MPG10_COMMON_TEST_MODE1 = 37,\n\tS2MPG10_COMMON_TEST_MODE2 = 38,\n\tS2MPG10_COMMON_SPD_DEBUG1 = 39,\n\tS2MPG10_COMMON_SPD_DEBUG2 = 40,\n\tS2MPG10_COMMON_SPD_DEBUG3 = 41,\n\tS2MPG10_COMMON_SPD_DEBUG4 = 42,\n};\n\nenum s2mpg10_irq {\n\tS2MPG10_IRQ_PWRONF = 0,\n\tS2MPG10_IRQ_PWRONR = 1,\n\tS2MPG10_IRQ_JIGONBF = 2,\n\tS2MPG10_IRQ_JIGONBR = 3,\n\tS2MPG10_IRQ_ACOKBF = 4,\n\tS2MPG10_IRQ_ACOKBR = 5,\n\tS2MPG10_IRQ_PWRON1S = 6,\n\tS2MPG10_IRQ_MRB = 7,\n\tS2MPG10_IRQ_RTC60S = 8,\n\tS2MPG10_IRQ_RTCA1 = 9,\n\tS2MPG10_IRQ_RTCA0 = 10,\n\tS2MPG10_IRQ_RTC1S = 11,\n\tS2MPG10_IRQ_WTSR_COLDRST = 12,\n\tS2MPG10_IRQ_WTSR = 13,\n\tS2MPG10_IRQ_WRST = 14,\n\tS2MPG10_IRQ_SMPL = 15,\n\tS2MPG10_IRQ_120C = 16,\n\tS2MPG10_IRQ_140C = 17,\n\tS2MPG10_IRQ_TSD = 18,\n\tS2MPG10_IRQ_PIF_TIMEOUT1 = 19,\n\tS2MPG10_IRQ_PIF_TIMEOUT2 = 20,\n\tS2MPG10_IRQ_SPD_PARITY_ERR = 21,\n\tS2MPG10_IRQ_SPD_ABNORMAL_STOP = 22,\n\tS2MPG10_IRQ_PMETER_OVERF = 23,\n\tS2MPG10_IRQ_OCP_B1M = 24,\n\tS2MPG10_IRQ_OCP_B2M = 25,\n\tS2MPG10_IRQ_OCP_B3M = 26,\n\tS2MPG10_IRQ_OCP_B4M = 27,\n\tS2MPG10_IRQ_OCP_B5M = 28,\n\tS2MPG10_IRQ_OCP_B6M = 29,\n\tS2MPG10_IRQ_OCP_B7M = 30,\n\tS2MPG10_IRQ_OCP_B8M = 31,\n\tS2MPG10_IRQ_OCP_B9M = 32,\n\tS2MPG10_IRQ_OCP_B10M = 33,\n\tS2MPG10_IRQ_WLWP_ACC = 34,\n\tS2MPG10_IRQ_SMPL_TIMEOUT = 35,\n\tS2MPG10_IRQ_WTSR_TIMEOUT = 36,\n\tS2MPG10_IRQ_SPD_SRP_PKT_RST = 37,\n\tS2MPG10_IRQ_PWR_WARN_CH0 = 38,\n\tS2MPG10_IRQ_PWR_WARN_CH1 = 39,\n\tS2MPG10_IRQ_PWR_WARN_CH2 = 40,\n\tS2MPG10_IRQ_PWR_WARN_CH3 = 41,\n\tS2MPG10_IRQ_PWR_WARN_CH4 = 42,\n\tS2MPG10_IRQ_PWR_WARN_CH5 = 43,\n\tS2MPG10_IRQ_PWR_WARN_CH6 = 44,\n\tS2MPG10_IRQ_PWR_WARN_CH7 = 45,\n\tS2MPG10_IRQ_NR = 46,\n};\n\nenum s2mpg10_pmic_reg {\n\tS2MPG10_PMIC_INT1 = 0,\n\tS2MPG10_PMIC_INT2 = 1,\n\tS2MPG10_PMIC_INT3 = 2,\n\tS2MPG10_PMIC_INT4 = 3,\n\tS2MPG10_PMIC_INT5 = 4,\n\tS2MPG10_PMIC_INT6 = 5,\n\tS2MPG10_PMIC_INT1M = 6,\n\tS2MPG10_PMIC_INT2M = 7,\n\tS2MPG10_PMIC_INT3M = 8,\n\tS2MPG10_PMIC_INT4M = 9,\n\tS2MPG10_PMIC_INT5M = 10,\n\tS2MPG10_PMIC_INT6M = 11,\n\tS2MPG10_PMIC_STATUS1 = 12,\n\tS2MPG10_PMIC_STATUS2 = 13,\n\tS2MPG10_PMIC_PWRONSRC = 14,\n\tS2MPG10_PMIC_OFFSRC = 15,\n\tS2MPG10_PMIC_BU_CHG = 16,\n\tS2MPG10_PMIC_RTCBUF = 17,\n\tS2MPG10_PMIC_COMMON_CTRL1 = 18,\n\tS2MPG10_PMIC_COMMON_CTRL2 = 19,\n\tS2MPG10_PMIC_COMMON_CTRL3 = 20,\n\tS2MPG10_PMIC_COMMON_CTRL4 = 21,\n\tS2MPG10_PMIC_SMPL_WARN_CTRL = 22,\n\tS2MPG10_PMIC_MIMICKING_CTRL = 23,\n\tS2MPG10_PMIC_B1M_CTRL = 24,\n\tS2MPG10_PMIC_B1M_OUT1 = 25,\n\tS2MPG10_PMIC_B1M_OUT2 = 26,\n\tS2MPG10_PMIC_B2M_CTRL = 27,\n\tS2MPG10_PMIC_B2M_OUT1 = 28,\n\tS2MPG10_PMIC_B2M_OUT2 = 29,\n\tS2MPG10_PMIC_B3M_CTRL = 30,\n\tS2MPG10_PMIC_B3M_OUT1 = 31,\n\tS2MPG10_PMIC_B3M_OUT2 = 32,\n\tS2MPG10_PMIC_B4M_CTRL = 33,\n\tS2MPG10_PMIC_B4M_OUT1 = 34,\n\tS2MPG10_PMIC_B4M_OUT2 = 35,\n\tS2MPG10_PMIC_B5M_CTRL = 36,\n\tS2MPG10_PMIC_B5M_OUT1 = 37,\n\tS2MPG10_PMIC_B5M_OUT2 = 38,\n\tS2MPG10_PMIC_B6M_CTRL = 39,\n\tS2MPG10_PMIC_B6M_OUT1 = 40,\n\tS2MPG10_PMIC_B6M_OUT2 = 41,\n\tS2MPG10_PMIC_B7M_CTRL = 42,\n\tS2MPG10_PMIC_B7M_OUT1 = 43,\n\tS2MPG10_PMIC_B7M_OUT2 = 44,\n\tS2MPG10_PMIC_B8M_CTRL = 45,\n\tS2MPG10_PMIC_B8M_OUT1 = 46,\n\tS2MPG10_PMIC_B8M_OUT2 = 47,\n\tS2MPG10_PMIC_B9M_CTRL = 48,\n\tS2MPG10_PMIC_B9M_OUT1 = 49,\n\tS2MPG10_PMIC_B9M_OUT2 = 50,\n\tS2MPG10_PMIC_B10M_CTRL = 51,\n\tS2MPG10_PMIC_B10M_OUT1 = 52,\n\tS2MPG10_PMIC_B10M_OUT2 = 53,\n\tS2MPG10_PMIC_BUCK1M_USONIC = 54,\n\tS2MPG10_PMIC_BUCK2M_USONIC = 55,\n\tS2MPG10_PMIC_BUCK3M_USONIC = 56,\n\tS2MPG10_PMIC_BUCK4M_USONIC = 57,\n\tS2MPG10_PMIC_BUCK5M_USONIC = 58,\n\tS2MPG10_PMIC_BUCK6M_USONIC = 59,\n\tS2MPG10_PMIC_BUCK7M_USONIC = 60,\n\tS2MPG10_PMIC_BUCK8M_USONIC = 61,\n\tS2MPG10_PMIC_BUCK9M_USONIC = 62,\n\tS2MPG10_PMIC_BUCK10M_USONIC = 63,\n\tS2MPG10_PMIC_L1M_CTRL = 64,\n\tS2MPG10_PMIC_L2M_CTRL = 65,\n\tS2MPG10_PMIC_L3M_CTRL = 66,\n\tS2MPG10_PMIC_L4M_CTRL = 67,\n\tS2MPG10_PMIC_L5M_CTRL = 68,\n\tS2MPG10_PMIC_L6M_CTRL = 69,\n\tS2MPG10_PMIC_L7M_CTRL = 70,\n\tS2MPG10_PMIC_L8M_CTRL = 71,\n\tS2MPG10_PMIC_L9M_CTRL = 72,\n\tS2MPG10_PMIC_L10M_CTRL = 73,\n\tS2MPG10_PMIC_L11M_CTRL1 = 74,\n\tS2MPG10_PMIC_L11M_CTRL2 = 75,\n\tS2MPG10_PMIC_L12M_CTRL1 = 76,\n\tS2MPG10_PMIC_L12M_CTRL2 = 77,\n\tS2MPG10_PMIC_L13M_CTRL1 = 78,\n\tS2MPG10_PMIC_L13M_CTRL2 = 79,\n\tS2MPG10_PMIC_L14M_CTRL = 80,\n\tS2MPG10_PMIC_L15M_CTRL1 = 81,\n\tS2MPG10_PMIC_L15M_CTRL2 = 82,\n\tS2MPG10_PMIC_L16M_CTRL = 83,\n\tS2MPG10_PMIC_L17M_CTRL = 84,\n\tS2MPG10_PMIC_L18M_CTRL = 85,\n\tS2MPG10_PMIC_L19M_CTRL = 86,\n\tS2MPG10_PMIC_L20M_CTRL = 87,\n\tS2MPG10_PMIC_L21M_CTRL = 88,\n\tS2MPG10_PMIC_L22M_CTRL = 89,\n\tS2MPG10_PMIC_L23M_CTRL = 90,\n\tS2MPG10_PMIC_L24M_CTRL = 91,\n\tS2MPG10_PMIC_L25M_CTRL = 92,\n\tS2MPG10_PMIC_L26M_CTRL = 93,\n\tS2MPG10_PMIC_L27M_CTRL = 94,\n\tS2MPG10_PMIC_L28M_CTRL = 95,\n\tS2MPG10_PMIC_L29M_CTRL = 96,\n\tS2MPG10_PMIC_L30M_CTRL = 97,\n\tS2MPG10_PMIC_L31M_CTRL = 98,\n\tS2MPG10_PMIC_LDO_CTRL1 = 99,\n\tS2MPG10_PMIC_LDO_CTRL2 = 100,\n\tS2MPG10_PMIC_LDO_DSCH1 = 101,\n\tS2MPG10_PMIC_LDO_DSCH2 = 102,\n\tS2MPG10_PMIC_LDO_DSCH3 = 103,\n\tS2MPG10_PMIC_LDO_DSCH4 = 104,\n\tS2MPG10_PMIC_LDO_BUCK7M_HLIMIT = 105,\n\tS2MPG10_PMIC_LDO_BUCK7M_LLIMIT = 106,\n\tS2MPG10_PMIC_LDO_LDO21M_HLIMIT = 107,\n\tS2MPG10_PMIC_LDO_LDO21M_LLIMIT = 108,\n\tS2MPG10_PMIC_LDO_LDO11M_HLIMIT = 109,\n\tS2MPG10_PMIC_DVS_RAMP1 = 110,\n\tS2MPG10_PMIC_DVS_RAMP2 = 111,\n\tS2MPG10_PMIC_DVS_RAMP3 = 112,\n\tS2MPG10_PMIC_DVS_RAMP4 = 113,\n\tS2MPG10_PMIC_DVS_RAMP5 = 114,\n\tS2MPG10_PMIC_DVS_RAMP6 = 115,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL1 = 116,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL2 = 117,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL3 = 118,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL4 = 119,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL5 = 120,\n\tS2MPG10_PMIC_DVS_SYNC_CTRL6 = 121,\n\tS2MPG10_PMIC_OFF_CTRL1 = 122,\n\tS2MPG10_PMIC_OFF_CTRL2 = 123,\n\tS2MPG10_PMIC_OFF_CTRL3 = 124,\n\tS2MPG10_PMIC_OFF_CTRL4 = 125,\n\tS2MPG10_PMIC_SEQ_CTRL1 = 126,\n\tS2MPG10_PMIC_SEQ_CTRL2 = 127,\n\tS2MPG10_PMIC_SEQ_CTRL3 = 128,\n\tS2MPG10_PMIC_SEQ_CTRL4 = 129,\n\tS2MPG10_PMIC_SEQ_CTRL5 = 130,\n\tS2MPG10_PMIC_SEQ_CTRL6 = 131,\n\tS2MPG10_PMIC_SEQ_CTRL7 = 132,\n\tS2MPG10_PMIC_SEQ_CTRL8 = 133,\n\tS2MPG10_PMIC_SEQ_CTRL9 = 134,\n\tS2MPG10_PMIC_SEQ_CTRL10 = 135,\n\tS2MPG10_PMIC_SEQ_CTRL11 = 136,\n\tS2MPG10_PMIC_SEQ_CTRL12 = 137,\n\tS2MPG10_PMIC_SEQ_CTRL13 = 138,\n\tS2MPG10_PMIC_SEQ_CTRL14 = 139,\n\tS2MPG10_PMIC_SEQ_CTRL15 = 140,\n\tS2MPG10_PMIC_SEQ_CTRL16 = 141,\n\tS2MPG10_PMIC_SEQ_CTRL17 = 142,\n\tS2MPG10_PMIC_SEQ_CTRL18 = 143,\n\tS2MPG10_PMIC_SEQ_CTRL19 = 144,\n\tS2MPG10_PMIC_SEQ_CTRL20 = 145,\n\tS2MPG10_PMIC_SEQ_CTRL21 = 146,\n\tS2MPG10_PMIC_SEQ_CTRL22 = 147,\n\tS2MPG10_PMIC_SEQ_CTRL23 = 148,\n\tS2MPG10_PMIC_SEQ_CTRL24 = 149,\n\tS2MPG10_PMIC_SEQ_CTRL25 = 150,\n\tS2MPG10_PMIC_SEQ_CTRL26 = 151,\n\tS2MPG10_PMIC_SEQ_CTRL27 = 152,\n\tS2MPG10_PMIC_SEQ_CTRL28 = 153,\n\tS2MPG10_PMIC_SEQ_CTRL29 = 154,\n\tS2MPG10_PMIC_SEQ_CTRL30 = 155,\n\tS2MPG10_PMIC_SEQ_CTRL31 = 156,\n\tS2MPG10_PMIC_SEQ_CTRL32 = 157,\n\tS2MPG10_PMIC_SEQ_CTRL33 = 158,\n\tS2MPG10_PMIC_SEQ_CTRL34 = 159,\n\tS2MPG10_PMIC_SEQ_CTRL35 = 160,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL1 = 161,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL2 = 162,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL3 = 163,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL4 = 164,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL5 = 165,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL6 = 166,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL7 = 167,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL8 = 168,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL9 = 169,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL10 = 170,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL11 = 171,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL12 = 172,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL13 = 173,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL14 = 174,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL15 = 175,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL16 = 176,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL17 = 177,\n\tS2MPG10_PMIC_OFF_SEQ_CTRL18 = 178,\n\tS2MPG10_PMIC_PCTRLSEL1 = 179,\n\tS2MPG10_PMIC_PCTRLSEL2 = 180,\n\tS2MPG10_PMIC_PCTRLSEL3 = 181,\n\tS2MPG10_PMIC_PCTRLSEL4 = 182,\n\tS2MPG10_PMIC_PCTRLSEL5 = 183,\n\tS2MPG10_PMIC_PCTRLSEL6 = 184,\n\tS2MPG10_PMIC_PCTRLSEL7 = 185,\n\tS2MPG10_PMIC_PCTRLSEL8 = 186,\n\tS2MPG10_PMIC_PCTRLSEL9 = 187,\n\tS2MPG10_PMIC_PCTRLSEL10 = 188,\n\tS2MPG10_PMIC_PCTRLSEL11 = 189,\n\tS2MPG10_PMIC_PCTRLSEL12 = 190,\n\tS2MPG10_PMIC_PCTRLSEL13 = 191,\n\tS2MPG10_PMIC_DCTRLSEL1 = 192,\n\tS2MPG10_PMIC_DCTRLSEL2 = 193,\n\tS2MPG10_PMIC_DCTRLSEL3 = 194,\n\tS2MPG10_PMIC_DCTRLSEL4 = 195,\n\tS2MPG10_PMIC_DCTRLSEL5 = 196,\n\tS2MPG10_PMIC_DCTRLSEL6 = 197,\n\tS2MPG10_PMIC_DCTRLSEL7 = 198,\n\tS2MPG10_PMIC_GPIO_CTRL1 = 199,\n\tS2MPG10_PMIC_GPIO_CTRL2 = 200,\n\tS2MPG10_PMIC_GPIO_CTRL3 = 201,\n\tS2MPG10_PMIC_GPIO_CTRL4 = 202,\n\tS2MPG10_PMIC_GPIO_CTRL5 = 203,\n\tS2MPG10_PMIC_GPIO_CTRL6 = 204,\n\tS2MPG10_PMIC_GPIO_CTRL7 = 205,\n\tS2MPG10_PMIC_B2M_OCP_WARN = 206,\n\tS2MPG10_PMIC_B2M_OCP_WARN_X = 207,\n\tS2MPG10_PMIC_B2M_OCP_WARN_Y = 208,\n\tS2MPG10_PMIC_B2M_OCP_WARN_Z = 209,\n\tS2MPG10_PMIC_B3M_OCP_WARN = 210,\n\tS2MPG10_PMIC_B3M_OCP_WARN_X = 211,\n\tS2MPG10_PMIC_B3M_OCP_WARN_Y = 212,\n\tS2MPG10_PMIC_B3M_OCP_WARN_Z = 213,\n\tS2MPG10_PMIC_B10M_OCP_WARN = 214,\n\tS2MPG10_PMIC_B10M_OCP_WARN_X = 215,\n\tS2MPG10_PMIC_B10M_OCP_WARN_Y = 216,\n\tS2MPG10_PMIC_B10M_OCP_WARN_Z = 217,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN = 218,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN_X = 219,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN_Y = 220,\n\tS2MPG10_PMIC_B2M_SOFT_OCP_WARN_Z = 221,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN = 222,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN_X = 223,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN_Y = 224,\n\tS2MPG10_PMIC_B3M_SOFT_OCP_WARN_Z = 225,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN = 226,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN_X = 227,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN_Y = 228,\n\tS2MPG10_PMIC_B10M_SOFT_OCP_WARN_Z = 229,\n\tS2MPG10_PMIC_BUCK_OCP_EN1 = 230,\n\tS2MPG10_PMIC_BUCK_OCP_EN2 = 231,\n\tS2MPG10_PMIC_BUCK_OCP_PD_EN1 = 232,\n\tS2MPG10_PMIC_BUCK_OCP_PD_EN2 = 233,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL1 = 234,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL2 = 235,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL3 = 236,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL4 = 237,\n\tS2MPG10_PMIC_BUCK_OCP_CTRL5 = 238,\n\tS2MPG10_PMIC_PIF_CTRL = 239,\n\tS2MPG10_PMIC_BUCK_HR_MODE1 = 240,\n\tS2MPG10_PMIC_BUCK_HR_MODE2 = 241,\n\tS2MPG10_PMIC_FAULTOUT_CTRL = 242,\n\tS2MPG10_PMIC_LDO_SENSE1 = 243,\n\tS2MPG10_PMIC_LDO_SENSE2 = 244,\n\tS2MPG10_PMIC_LDO_SENSE3 = 245,\n\tS2MPG10_PMIC_LDO_SENSE4 = 246,\n};\n\nenum s2mpg10_regulators {\n\tS2MPG10_BUCK1 = 0,\n\tS2MPG10_BUCK2 = 1,\n\tS2MPG10_BUCK3 = 2,\n\tS2MPG10_BUCK4 = 3,\n\tS2MPG10_BUCK5 = 4,\n\tS2MPG10_BUCK6 = 5,\n\tS2MPG10_BUCK7 = 6,\n\tS2MPG10_BUCK8 = 7,\n\tS2MPG10_BUCK9 = 8,\n\tS2MPG10_BUCK10 = 9,\n\tS2MPG10_LDO1 = 10,\n\tS2MPG10_LDO2 = 11,\n\tS2MPG10_LDO3 = 12,\n\tS2MPG10_LDO4 = 13,\n\tS2MPG10_LDO5 = 14,\n\tS2MPG10_LDO6 = 15,\n\tS2MPG10_LDO7 = 16,\n\tS2MPG10_LDO8 = 17,\n\tS2MPG10_LDO9 = 18,\n\tS2MPG10_LDO10 = 19,\n\tS2MPG10_LDO11 = 20,\n\tS2MPG10_LDO12 = 21,\n\tS2MPG10_LDO13 = 22,\n\tS2MPG10_LDO14 = 23,\n\tS2MPG10_LDO15 = 24,\n\tS2MPG10_LDO16 = 25,\n\tS2MPG10_LDO17 = 26,\n\tS2MPG10_LDO18 = 27,\n\tS2MPG10_LDO19 = 28,\n\tS2MPG10_LDO20 = 29,\n\tS2MPG10_LDO21 = 30,\n\tS2MPG10_LDO22 = 31,\n\tS2MPG10_LDO23 = 32,\n\tS2MPG10_LDO24 = 33,\n\tS2MPG10_LDO25 = 34,\n\tS2MPG10_LDO26 = 35,\n\tS2MPG10_LDO27 = 36,\n\tS2MPG10_LDO28 = 37,\n\tS2MPG10_LDO29 = 38,\n\tS2MPG10_LDO30 = 39,\n\tS2MPG10_LDO31 = 40,\n\tS2MPG10_REGULATOR_MAX = 41,\n};\n\nenum s2mpg10_rtc_reg {\n\tS2MPG10_RTC_CTRL = 0,\n\tS2MPG10_RTC_UPDATE = 1,\n\tS2MPG10_RTC_SMPL = 2,\n\tS2MPG10_RTC_WTSR = 3,\n\tS2MPG10_RTC_CAP_SEL = 4,\n\tS2MPG10_RTC_MSEC = 5,\n\tS2MPG10_RTC_SEC = 6,\n\tS2MPG10_RTC_MIN = 7,\n\tS2MPG10_RTC_HOUR = 8,\n\tS2MPG10_RTC_WEEK = 9,\n\tS2MPG10_RTC_DAY = 10,\n\tS2MPG10_RTC_MON = 11,\n\tS2MPG10_RTC_YEAR = 12,\n\tS2MPG10_RTC_A0SEC = 13,\n\tS2MPG10_RTC_A0MIN = 14,\n\tS2MPG10_RTC_A0HOUR = 15,\n\tS2MPG10_RTC_A0WEEK = 16,\n\tS2MPG10_RTC_A0DAY = 17,\n\tS2MPG10_RTC_A0MON = 18,\n\tS2MPG10_RTC_A0YEAR = 19,\n\tS2MPG10_RTC_A1SEC = 20,\n\tS2MPG10_RTC_A1MIN = 21,\n\tS2MPG10_RTC_A1HOUR = 22,\n\tS2MPG10_RTC_A1WEEK = 23,\n\tS2MPG10_RTC_A1DAY = 24,\n\tS2MPG10_RTC_A1MON = 25,\n\tS2MPG10_RTC_A1YEAR = 26,\n\tS2MPG10_RTC_OSC_CTRL = 27,\n};\n\nenum s2mpg11_common_irq {\n\tS2MPG11_COMMON_IRQ_PMIC = 0,\n\tS2MPG11_COMMON_IRQ_UNUSED = 1,\n};\n\nenum s2mpg11_common_reg {\n\tS2MPG11_COMMON_CHIPID = 0,\n\tS2MPG11_COMMON_INT = 1,\n\tS2MPG11_COMMON_INT_MASK = 2,\n\tS2MPG11_COMMON_SPD_CTRL1 = 10,\n\tS2MPG11_COMMON_SPD_CTRL2 = 11,\n\tS2MPG11_COMMON_SPD_CTRL3 = 12,\n\tS2MPG11_COMMON_MON1SEL = 26,\n\tS2MPG11_COMMON_MON2SEL = 27,\n\tS2MPG11_COMMON_MONR = 28,\n\tS2MPG11_COMMON_DEBUG_CTRL1 = 29,\n\tS2MPG11_COMMON_DEBUG_CTRL2 = 30,\n\tS2MPG11_COMMON_DEBUG_CTRL3 = 31,\n\tS2MPG11_COMMON_DEBUG_CTRL4 = 32,\n\tS2MPG11_COMMON_DEBUG_CTRL5 = 33,\n\tS2MPG11_COMMON_DEBUG_CTRL6 = 34,\n\tS2MPG11_COMMON_TEST_MODE1 = 35,\n\tS2MPG11_COMMON_SPD_DEBUG1 = 36,\n\tS2MPG11_COMMON_SPD_DEBUG2 = 37,\n\tS2MPG11_COMMON_SPD_DEBUG3 = 38,\n\tS2MPG11_COMMON_SPD_DEBUG4 = 39,\n};\n\nenum s2mpg11_irq {\n\tS2MPG11_IRQ_PWRONF = 0,\n\tS2MPG11_IRQ_PWRONR = 1,\n\tS2MPG11_IRQ_PIF_TIMEOUT_MIF = 2,\n\tS2MPG11_IRQ_PIF_TIMEOUTS = 3,\n\tS2MPG11_IRQ_WTSR = 4,\n\tS2MPG11_IRQ_SPD_ABNORMAL_STOP = 5,\n\tS2MPG11_IRQ_SPD_PARITY_ERR = 6,\n\tS2MPG11_IRQ_140C = 7,\n\tS2MPG11_IRQ_120C = 8,\n\tS2MPG11_IRQ_TSD = 9,\n\tS2MPG11_IRQ_WRST = 10,\n\tS2MPG11_IRQ_NTC_CYCLE_DONE = 11,\n\tS2MPG11_IRQ_PMETER_OVERF = 12,\n\tS2MPG11_IRQ_OCP_B1S = 13,\n\tS2MPG11_IRQ_OCP_B2S = 14,\n\tS2MPG11_IRQ_OCP_B3S = 15,\n\tS2MPG11_IRQ_OCP_B4S = 16,\n\tS2MPG11_IRQ_OCP_B5S = 17,\n\tS2MPG11_IRQ_OCP_B6S = 18,\n\tS2MPG11_IRQ_OCP_B7S = 19,\n\tS2MPG11_IRQ_OCP_B8S = 20,\n\tS2MPG11_IRQ_OCP_B9S = 21,\n\tS2MPG11_IRQ_OCP_B10S = 22,\n\tS2MPG11_IRQ_OCP_BDS = 23,\n\tS2MPG11_IRQ_OCP_BAS = 24,\n\tS2MPG11_IRQ_OCP_BBS = 25,\n\tS2MPG11_IRQ_WLWP_ACC = 26,\n\tS2MPG11_IRQ_SPD_SRP_PKT_RST = 27,\n\tS2MPG11_IRQ_PWR_WARN_CH0 = 28,\n\tS2MPG11_IRQ_PWR_WARN_CH1 = 29,\n\tS2MPG11_IRQ_PWR_WARN_CH2 = 30,\n\tS2MPG11_IRQ_PWR_WARN_CH3 = 31,\n\tS2MPG11_IRQ_PWR_WARN_CH4 = 32,\n\tS2MPG11_IRQ_PWR_WARN_CH5 = 33,\n\tS2MPG11_IRQ_PWR_WARN_CH6 = 34,\n\tS2MPG11_IRQ_PWR_WARN_CH7 = 35,\n\tS2MPG11_IRQ_NTC_WARN_CH0 = 36,\n\tS2MPG11_IRQ_NTC_WARN_CH1 = 37,\n\tS2MPG11_IRQ_NTC_WARN_CH2 = 38,\n\tS2MPG11_IRQ_NTC_WARN_CH3 = 39,\n\tS2MPG11_IRQ_NTC_WARN_CH4 = 40,\n\tS2MPG11_IRQ_NTC_WARN_CH5 = 41,\n\tS2MPG11_IRQ_NTC_WARN_CH6 = 42,\n\tS2MPG11_IRQ_NTC_WARN_CH7 = 43,\n\tS2MPG11_IRQ_NR = 44,\n};\n\nenum s2mpg11_pmic_reg {\n\tS2MPG11_PMIC_INT1 = 0,\n\tS2MPG11_PMIC_INT2 = 1,\n\tS2MPG11_PMIC_INT3 = 2,\n\tS2MPG11_PMIC_INT4 = 3,\n\tS2MPG11_PMIC_INT5 = 4,\n\tS2MPG11_PMIC_INT6 = 5,\n\tS2MPG11_PMIC_INT1M = 6,\n\tS2MPG11_PMIC_INT2M = 7,\n\tS2MPG11_PMIC_INT3M = 8,\n\tS2MPG11_PMIC_INT4M = 9,\n\tS2MPG11_PMIC_INT5M = 10,\n\tS2MPG11_PMIC_INT6M = 11,\n\tS2MPG11_PMIC_STATUS1 = 12,\n\tS2MPG11_PMIC_OFFSRC = 13,\n\tS2MPG11_PMIC_COMMON_CTRL1 = 14,\n\tS2MPG11_PMIC_COMMON_CTRL2 = 15,\n\tS2MPG11_PMIC_COMMON_CTRL3 = 16,\n\tS2MPG11_PMIC_MIMICKING_CTRL = 17,\n\tS2MPG11_PMIC_B1S_CTRL = 18,\n\tS2MPG11_PMIC_B1S_OUT1 = 19,\n\tS2MPG11_PMIC_B1S_OUT2 = 20,\n\tS2MPG11_PMIC_B2S_CTRL = 21,\n\tS2MPG11_PMIC_B2S_OUT1 = 22,\n\tS2MPG11_PMIC_B2S_OUT2 = 23,\n\tS2MPG11_PMIC_B3S_CTRL = 24,\n\tS2MPG11_PMIC_B3S_OUT1 = 25,\n\tS2MPG11_PMIC_B3S_OUT2 = 26,\n\tS2MPG11_PMIC_B4S_CTRL = 27,\n\tS2MPG11_PMIC_B4S_OUT = 28,\n\tS2MPG11_PMIC_B5S_CTRL = 29,\n\tS2MPG11_PMIC_B5S_OUT = 30,\n\tS2MPG11_PMIC_B6S_CTRL = 31,\n\tS2MPG11_PMIC_B6S_OUT1 = 32,\n\tS2MPG11_PMIC_B6S_OUT2 = 33,\n\tS2MPG11_PMIC_B7S_CTRL = 34,\n\tS2MPG11_PMIC_B7S_OUT1 = 35,\n\tS2MPG11_PMIC_B7S_OUT2 = 36,\n\tS2MPG11_PMIC_B8S_CTRL = 37,\n\tS2MPG11_PMIC_B8S_OUT1 = 38,\n\tS2MPG11_PMIC_B8S_OUT2 = 39,\n\tS2MPG11_PMIC_B9S_CTRL = 40,\n\tS2MPG11_PMIC_B9S_OUT1 = 41,\n\tS2MPG11_PMIC_B9S_OUT2 = 42,\n\tS2MPG11_PMIC_B10S_CTRL = 43,\n\tS2MPG11_PMIC_B10S_OUT = 44,\n\tS2MPG11_PMIC_BUCKD_CTRL = 45,\n\tS2MPG11_PMIC_BUCKD_OUT = 46,\n\tS2MPG11_PMIC_BUCKA_CTRL = 47,\n\tS2MPG11_PMIC_BUCKA_OUT = 48,\n\tS2MPG11_PMIC_BB_CTRL = 49,\n\tS2MPG11_PMIC_BB_OUT1 = 50,\n\tS2MPG11_PMIC_BB_OUT2 = 51,\n\tS2MPG11_PMIC_BUCK1S_USONIC = 52,\n\tS2MPG11_PMIC_BUCK2S_USONIC = 53,\n\tS2MPG11_PMIC_BUCK3S_USONIC = 54,\n\tS2MPG11_PMIC_BUCK4S_USONIC = 55,\n\tS2MPG11_PMIC_BUCK5S_USONIC = 56,\n\tS2MPG11_PMIC_BUCK6S_USONIC = 57,\n\tS2MPG11_PMIC_BUCK7S_USONIC = 58,\n\tS2MPG11_PMIC_BUCK8S_USONIC = 59,\n\tS2MPG11_PMIC_BUCK9S_USONIC = 60,\n\tS2MPG11_PMIC_BUCK10S_USONIC = 61,\n\tS2MPG11_PMIC_BUCKD_USONIC = 62,\n\tS2MPG11_PMIC_BUCKA_USONIC = 63,\n\tS2MPG11_PMIC_BB_USONIC = 64,\n\tS2MPG11_PMIC_L1S_CTRL1 = 65,\n\tS2MPG11_PMIC_L1S_CTRL2 = 66,\n\tS2MPG11_PMIC_L2S_CTRL1 = 67,\n\tS2MPG11_PMIC_L2S_CTRL2 = 68,\n\tS2MPG11_PMIC_L3S_CTRL = 69,\n\tS2MPG11_PMIC_L4S_CTRL = 70,\n\tS2MPG11_PMIC_L5S_CTRL = 71,\n\tS2MPG11_PMIC_L6S_CTRL = 72,\n\tS2MPG11_PMIC_L7S_CTRL = 73,\n\tS2MPG11_PMIC_L8S_CTRL = 74,\n\tS2MPG11_PMIC_L9S_CTRL = 75,\n\tS2MPG11_PMIC_L10S_CTRL = 76,\n\tS2MPG11_PMIC_L11S_CTRL = 77,\n\tS2MPG11_PMIC_L12S_CTRL = 78,\n\tS2MPG11_PMIC_L13S_CTRL = 79,\n\tS2MPG11_PMIC_L14S_CTRL = 80,\n\tS2MPG11_PMIC_L15S_CTRL = 81,\n\tS2MPG11_PMIC_LDO_CTRL1 = 82,\n\tS2MPG11_PMIC_LDO_DSCH1 = 83,\n\tS2MPG11_PMIC_LDO_DSCH2 = 84,\n\tS2MPG11_PMIC_DVS_RAMP1 = 85,\n\tS2MPG11_PMIC_DVS_RAMP2 = 86,\n\tS2MPG11_PMIC_DVS_RAMP3 = 87,\n\tS2MPG11_PMIC_DVS_RAMP4 = 88,\n\tS2MPG11_PMIC_DVS_RAMP5 = 89,\n\tS2MPG11_PMIC_DVS_RAMP6 = 90,\n\tS2MPG11_PMIC_DVS_SYNC_CTRL1 = 92,\n\tS2MPG11_PMIC_DVS_SYNC_CTRL2 = 93,\n\tS2MPG11_PMIC_OFF_CTRL1 = 94,\n\tS2MPG11_PMIC_OFF_CTRL2 = 95,\n\tS2MPG11_PMIC_OFF_CTRL3 = 96,\n\tS2MPG11_PMIC_SEQ_CTRL1 = 97,\n\tS2MPG11_PMIC_SEQ_CTRL2 = 98,\n\tS2MPG11_PMIC_SEQ_CTRL3 = 99,\n\tS2MPG11_PMIC_SEQ_CTRL4 = 100,\n\tS2MPG11_PMIC_SEQ_CTRL5 = 101,\n\tS2MPG11_PMIC_SEQ_CTRL6 = 102,\n\tS2MPG11_PMIC_SEQ_CTRL7 = 103,\n\tS2MPG11_PMIC_SEQ_CTRL8 = 104,\n\tS2MPG11_PMIC_SEQ_CTRL9 = 105,\n\tS2MPG11_PMIC_SEQ_CTRL10 = 106,\n\tS2MPG11_PMIC_SEQ_CTRL11 = 107,\n\tS2MPG11_PMIC_SEQ_CTRL12 = 108,\n\tS2MPG11_PMIC_SEQ_CTRL13 = 109,\n\tS2MPG11_PMIC_SEQ_CTRL14 = 110,\n\tS2MPG11_PMIC_SEQ_CTRL15 = 111,\n\tS2MPG11_PMIC_SEQ_CTRL16 = 112,\n\tS2MPG11_PMIC_SEQ_CTRL17 = 113,\n\tS2MPG11_PMIC_SEQ_CTRL18 = 114,\n\tS2MPG11_PMIC_SEQ_CTRL19 = 115,\n\tS2MPG11_PMIC_SEQ_CTRL20 = 116,\n\tS2MPG11_PMIC_SEQ_CTRL21 = 117,\n\tS2MPG11_PMIC_SEQ_CTRL22 = 118,\n\tS2MPG11_PMIC_SEQ_CTRL23 = 119,\n\tS2MPG11_PMIC_SEQ_CTRL24 = 120,\n\tS2MPG11_PMIC_SEQ_CTRL25 = 121,\n\tS2MPG11_PMIC_SEQ_CTRL26 = 122,\n\tS2MPG11_PMIC_SEQ_CTRL27 = 123,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL1 = 124,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL2 = 125,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL3 = 126,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL4 = 127,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL5 = 128,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL6 = 129,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL7 = 130,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL8 = 131,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL9 = 132,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL10 = 133,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL11 = 134,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL12 = 135,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL13 = 136,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL14 = 137,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL15 = 138,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL16 = 139,\n\tS2MPG11_PMIC_OFF_SEQ_CTRL17 = 140,\n\tS2MPG11_PMIC_PCTRLSEL1 = 141,\n\tS2MPG11_PMIC_PCTRLSEL2 = 142,\n\tS2MPG11_PMIC_PCTRLSEL3 = 143,\n\tS2MPG11_PMIC_PCTRLSEL4 = 144,\n\tS2MPG11_PMIC_PCTRLSEL5 = 145,\n\tS2MPG11_PMIC_PCTRLSEL6 = 146,\n\tS2MPG11_PMIC_DCTRLSEL1 = 147,\n\tS2MPG11_PMIC_DCTRLSEL2 = 148,\n\tS2MPG11_PMIC_DCTRLSEL3 = 149,\n\tS2MPG11_PMIC_DCTRLSEL4 = 150,\n\tS2MPG11_PMIC_DCTRLSEL5 = 151,\n\tS2MPG11_PMIC_GPIO_CTRL1 = 152,\n\tS2MPG11_PMIC_GPIO_CTRL2 = 153,\n\tS2MPG11_PMIC_GPIO_CTRL3 = 154,\n\tS2MPG11_PMIC_GPIO_CTRL4 = 155,\n\tS2MPG11_PMIC_GPIO_CTRL5 = 156,\n\tS2MPG11_PMIC_GPIO_CTRL6 = 157,\n\tS2MPG11_PMIC_GPIO_CTRL7 = 158,\n\tS2MPG11_PMIC_B2S_OCP_WARN = 159,\n\tS2MPG11_PMIC_B2S_OCP_WARN_X = 160,\n\tS2MPG11_PMIC_B2S_OCP_WARN_Y = 161,\n\tS2MPG11_PMIC_B2S_OCP_WARN_Z = 162,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN = 163,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN_X = 164,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y = 165,\n\tS2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z = 166,\n\tS2MPG11_PMIC_BUCK_OCP_EN1 = 167,\n\tS2MPG11_PMIC_BUCK_OCP_EN2 = 168,\n\tS2MPG11_PMIC_BUCK_OCP_PD_EN1 = 169,\n\tS2MPG11_PMIC_BUCK_OCP_PD_EN2 = 170,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL1 = 171,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL2 = 172,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL3 = 173,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL4 = 174,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL5 = 175,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL6 = 176,\n\tS2MPG11_PMIC_BUCK_OCP_CTRL7 = 177,\n\tS2MPG11_PMIC_PIF_CTRL = 178,\n\tS2MPG11_PMIC_BUCK_HR_MODE1 = 179,\n\tS2MPG11_PMIC_BUCK_HR_MODE2 = 180,\n\tS2MPG11_PMIC_FAULTOUT_CTRL = 181,\n\tS2MPG11_PMIC_LDO_SENSE1 = 182,\n\tS2MPG11_PMIC_LDO_SENSE2 = 183,\n};\n\nenum s2mpg11_regulators {\n\tS2MPG11_BUCKBOOST = 0,\n\tS2MPG11_BUCK1 = 1,\n\tS2MPG11_BUCK2 = 2,\n\tS2MPG11_BUCK3 = 3,\n\tS2MPG11_BUCK4 = 4,\n\tS2MPG11_BUCK5 = 5,\n\tS2MPG11_BUCK6 = 6,\n\tS2MPG11_BUCK7 = 7,\n\tS2MPG11_BUCK8 = 8,\n\tS2MPG11_BUCK9 = 9,\n\tS2MPG11_BUCK10 = 10,\n\tS2MPG11_BUCKD = 11,\n\tS2MPG11_BUCKA = 12,\n\tS2MPG11_LDO1 = 13,\n\tS2MPG11_LDO2 = 14,\n\tS2MPG11_LDO3 = 15,\n\tS2MPG11_LDO4 = 16,\n\tS2MPG11_LDO5 = 17,\n\tS2MPG11_LDO6 = 18,\n\tS2MPG11_LDO7 = 19,\n\tS2MPG11_LDO8 = 20,\n\tS2MPG11_LDO9 = 21,\n\tS2MPG11_LDO10 = 22,\n\tS2MPG11_LDO11 = 23,\n\tS2MPG11_LDO12 = 24,\n\tS2MPG11_LDO13 = 25,\n\tS2MPG11_LDO14 = 26,\n\tS2MPG11_LDO15 = 27,\n\tS2MPG11_REGULATOR_MAX = 28,\n};\n\nenum s2mps11_irq {\n\tS2MPS11_IRQ_PWRONF = 0,\n\tS2MPS11_IRQ_PWRONR = 1,\n\tS2MPS11_IRQ_JIGONBF = 2,\n\tS2MPS11_IRQ_JIGONBR = 3,\n\tS2MPS11_IRQ_ACOKBF = 4,\n\tS2MPS11_IRQ_ACOKBR = 5,\n\tS2MPS11_IRQ_PWRON1S = 6,\n\tS2MPS11_IRQ_MRB = 7,\n\tS2MPS11_IRQ_RTC60S = 8,\n\tS2MPS11_IRQ_RTCA1 = 9,\n\tS2MPS11_IRQ_RTCA0 = 10,\n\tS2MPS11_IRQ_SMPL = 11,\n\tS2MPS11_IRQ_RTC1S = 12,\n\tS2MPS11_IRQ_WTSR = 13,\n\tS2MPS11_IRQ_INT120C = 14,\n\tS2MPS11_IRQ_INT140C = 15,\n\tS2MPS11_IRQ_NR = 16,\n};\n\nenum s2mps11_reg {\n\tS2MPS11_REG_ID = 0,\n\tS2MPS11_REG_INT1 = 1,\n\tS2MPS11_REG_INT2 = 2,\n\tS2MPS11_REG_INT3 = 3,\n\tS2MPS11_REG_INT1M = 4,\n\tS2MPS11_REG_INT2M = 5,\n\tS2MPS11_REG_INT3M = 6,\n\tS2MPS11_REG_ST1 = 7,\n\tS2MPS11_REG_ST2 = 8,\n\tS2MPS11_REG_OFFSRC = 9,\n\tS2MPS11_REG_PWRONSRC = 10,\n\tS2MPS11_REG_RTC_CTRL = 11,\n\tS2MPS11_REG_CTRL1 = 12,\n\tS2MPS11_REG_ETC_TEST = 13,\n\tS2MPS11_REG_RSVD3 = 14,\n\tS2MPS11_REG_BU_CHG = 15,\n\tS2MPS11_REG_RAMP = 16,\n\tS2MPS11_REG_RAMP_BUCK = 17,\n\tS2MPS11_REG_LDO1_8 = 18,\n\tS2MPS11_REG_LDO9_16 = 19,\n\tS2MPS11_REG_LDO17_24 = 20,\n\tS2MPS11_REG_LDO25_32 = 21,\n\tS2MPS11_REG_LDO33_38 = 22,\n\tS2MPS11_REG_LDO1_8_1 = 23,\n\tS2MPS11_REG_LDO9_16_1 = 24,\n\tS2MPS11_REG_LDO17_24_1 = 25,\n\tS2MPS11_REG_LDO25_32_1 = 26,\n\tS2MPS11_REG_LDO33_38_1 = 27,\n\tS2MPS11_REG_OTP_ADRL = 28,\n\tS2MPS11_REG_OTP_ADRH = 29,\n\tS2MPS11_REG_OTP_DATA = 30,\n\tS2MPS11_REG_MON1SEL = 31,\n\tS2MPS11_REG_MON2SEL = 32,\n\tS2MPS11_REG_LEE = 33,\n\tS2MPS11_REG_RSVD_NO = 34,\n\tS2MPS11_REG_UVLO = 35,\n\tS2MPS11_REG_LEE_NO = 36,\n\tS2MPS11_REG_B1CTRL1 = 37,\n\tS2MPS11_REG_B1CTRL2 = 38,\n\tS2MPS11_REG_B2CTRL1 = 39,\n\tS2MPS11_REG_B2CTRL2 = 40,\n\tS2MPS11_REG_B3CTRL1 = 41,\n\tS2MPS11_REG_B3CTRL2 = 42,\n\tS2MPS11_REG_B4CTRL1 = 43,\n\tS2MPS11_REG_B4CTRL2 = 44,\n\tS2MPS11_REG_B5CTRL1 = 45,\n\tS2MPS11_REG_BUCK5_SW = 46,\n\tS2MPS11_REG_B5CTRL2 = 47,\n\tS2MPS11_REG_B5CTRL3 = 48,\n\tS2MPS11_REG_B5CTRL4 = 49,\n\tS2MPS11_REG_B5CTRL5 = 50,\n\tS2MPS11_REG_B6CTRL1 = 51,\n\tS2MPS11_REG_B6CTRL2 = 52,\n\tS2MPS11_REG_B7CTRL1 = 53,\n\tS2MPS11_REG_B7CTRL2 = 54,\n\tS2MPS11_REG_B8CTRL1 = 55,\n\tS2MPS11_REG_B8CTRL2 = 56,\n\tS2MPS11_REG_B9CTRL1 = 57,\n\tS2MPS11_REG_B9CTRL2 = 58,\n\tS2MPS11_REG_B10CTRL1 = 59,\n\tS2MPS11_REG_B10CTRL2 = 60,\n\tS2MPS11_REG_L1CTRL = 61,\n\tS2MPS11_REG_L2CTRL = 62,\n\tS2MPS11_REG_L3CTRL = 63,\n\tS2MPS11_REG_L4CTRL = 64,\n\tS2MPS11_REG_L5CTRL = 65,\n\tS2MPS11_REG_L6CTRL = 66,\n\tS2MPS11_REG_L7CTRL = 67,\n\tS2MPS11_REG_L8CTRL = 68,\n\tS2MPS11_REG_L9CTRL = 69,\n\tS2MPS11_REG_L10CTRL = 70,\n\tS2MPS11_REG_L11CTRL = 71,\n\tS2MPS11_REG_L12CTRL = 72,\n\tS2MPS11_REG_L13CTRL = 73,\n\tS2MPS11_REG_L14CTRL = 74,\n\tS2MPS11_REG_L15CTRL = 75,\n\tS2MPS11_REG_L16CTRL = 76,\n\tS2MPS11_REG_L17CTRL = 77,\n\tS2MPS11_REG_L18CTRL = 78,\n\tS2MPS11_REG_L19CTRL = 79,\n\tS2MPS11_REG_L20CTRL = 80,\n\tS2MPS11_REG_L21CTRL = 81,\n\tS2MPS11_REG_L22CTRL = 82,\n\tS2MPS11_REG_L23CTRL = 83,\n\tS2MPS11_REG_L24CTRL = 84,\n\tS2MPS11_REG_L25CTRL = 85,\n\tS2MPS11_REG_L26CTRL = 86,\n\tS2MPS11_REG_L27CTRL = 87,\n\tS2MPS11_REG_L28CTRL = 88,\n\tS2MPS11_REG_L29CTRL = 89,\n\tS2MPS11_REG_L30CTRL = 90,\n\tS2MPS11_REG_L31CTRL = 91,\n\tS2MPS11_REG_L32CTRL = 92,\n\tS2MPS11_REG_L33CTRL = 93,\n\tS2MPS11_REG_L34CTRL = 94,\n\tS2MPS11_REG_L35CTRL = 95,\n\tS2MPS11_REG_L36CTRL = 96,\n\tS2MPS11_REG_L37CTRL = 97,\n\tS2MPS11_REG_L38CTRL = 98,\n};\n\nenum s2mps11_regulators {\n\tS2MPS11_LDO1 = 0,\n\tS2MPS11_LDO2 = 1,\n\tS2MPS11_LDO3 = 2,\n\tS2MPS11_LDO4 = 3,\n\tS2MPS11_LDO5 = 4,\n\tS2MPS11_LDO6 = 5,\n\tS2MPS11_LDO7 = 6,\n\tS2MPS11_LDO8 = 7,\n\tS2MPS11_LDO9 = 8,\n\tS2MPS11_LDO10 = 9,\n\tS2MPS11_LDO11 = 10,\n\tS2MPS11_LDO12 = 11,\n\tS2MPS11_LDO13 = 12,\n\tS2MPS11_LDO14 = 13,\n\tS2MPS11_LDO15 = 14,\n\tS2MPS11_LDO16 = 15,\n\tS2MPS11_LDO17 = 16,\n\tS2MPS11_LDO18 = 17,\n\tS2MPS11_LDO19 = 18,\n\tS2MPS11_LDO20 = 19,\n\tS2MPS11_LDO21 = 20,\n\tS2MPS11_LDO22 = 21,\n\tS2MPS11_LDO23 = 22,\n\tS2MPS11_LDO24 = 23,\n\tS2MPS11_LDO25 = 24,\n\tS2MPS11_LDO26 = 25,\n\tS2MPS11_LDO27 = 26,\n\tS2MPS11_LDO28 = 27,\n\tS2MPS11_LDO29 = 28,\n\tS2MPS11_LDO30 = 29,\n\tS2MPS11_LDO31 = 30,\n\tS2MPS11_LDO32 = 31,\n\tS2MPS11_LDO33 = 32,\n\tS2MPS11_LDO34 = 33,\n\tS2MPS11_LDO35 = 34,\n\tS2MPS11_LDO36 = 35,\n\tS2MPS11_LDO37 = 36,\n\tS2MPS11_LDO38 = 37,\n\tS2MPS11_BUCK1 = 38,\n\tS2MPS11_BUCK2 = 39,\n\tS2MPS11_BUCK3 = 40,\n\tS2MPS11_BUCK4 = 41,\n\tS2MPS11_BUCK5 = 42,\n\tS2MPS11_BUCK6 = 43,\n\tS2MPS11_BUCK7 = 44,\n\tS2MPS11_BUCK8 = 45,\n\tS2MPS11_BUCK9 = 46,\n\tS2MPS11_BUCK10 = 47,\n\tS2MPS11_REGULATOR_MAX = 48,\n};\n\nenum s2mps13_reg {\n\tS2MPS13_REG_ID = 0,\n\tS2MPS13_REG_INT1 = 1,\n\tS2MPS13_REG_INT2 = 2,\n\tS2MPS13_REG_INT3 = 3,\n\tS2MPS13_REG_INT1M = 4,\n\tS2MPS13_REG_INT2M = 5,\n\tS2MPS13_REG_INT3M = 6,\n\tS2MPS13_REG_ST1 = 7,\n\tS2MPS13_REG_ST2 = 8,\n\tS2MPS13_REG_PWRONSRC = 9,\n\tS2MPS13_REG_OFFSRC = 10,\n\tS2MPS13_REG_BU_CHG = 11,\n\tS2MPS13_REG_RTCCTRL = 12,\n\tS2MPS13_REG_CTRL1 = 13,\n\tS2MPS13_REG_CTRL2 = 14,\n\tS2MPS13_REG_RSVD1 = 15,\n\tS2MPS13_REG_RSVD2 = 16,\n\tS2MPS13_REG_RSVD3 = 17,\n\tS2MPS13_REG_RSVD4 = 18,\n\tS2MPS13_REG_RSVD5 = 19,\n\tS2MPS13_REG_RSVD6 = 20,\n\tS2MPS13_REG_CTRL3 = 21,\n\tS2MPS13_REG_RSVD7 = 22,\n\tS2MPS13_REG_RSVD8 = 23,\n\tS2MPS13_REG_WRSTBI = 24,\n\tS2MPS13_REG_B1CTRL = 25,\n\tS2MPS13_REG_B1OUT = 26,\n\tS2MPS13_REG_B2CTRL = 27,\n\tS2MPS13_REG_B2OUT = 28,\n\tS2MPS13_REG_B3CTRL = 29,\n\tS2MPS13_REG_B3OUT = 30,\n\tS2MPS13_REG_B4CTRL = 31,\n\tS2MPS13_REG_B4OUT = 32,\n\tS2MPS13_REG_B5CTRL = 33,\n\tS2MPS13_REG_B5OUT = 34,\n\tS2MPS13_REG_B6CTRL = 35,\n\tS2MPS13_REG_B6OUT = 36,\n\tS2MPS13_REG_B7CTRL = 37,\n\tS2MPS13_REG_B7SW = 38,\n\tS2MPS13_REG_B7OUT = 39,\n\tS2MPS13_REG_B8CTRL = 40,\n\tS2MPS13_REG_B8OUT = 41,\n\tS2MPS13_REG_B9CTRL = 42,\n\tS2MPS13_REG_B9OUT = 43,\n\tS2MPS13_REG_B10CTRL = 44,\n\tS2MPS13_REG_B10OUT = 45,\n\tS2MPS13_REG_BB1CTRL = 46,\n\tS2MPS13_REG_BB1OUT = 47,\n\tS2MPS13_REG_BUCK_RAMP1 = 48,\n\tS2MPS13_REG_BUCK_RAMP2 = 49,\n\tS2MPS13_REG_LDO_DVS1 = 50,\n\tS2MPS13_REG_LDO_DVS2 = 51,\n\tS2MPS13_REG_LDO_DVS3 = 52,\n\tS2MPS13_REG_B6OUT2 = 53,\n\tS2MPS13_REG_L1CTRL = 54,\n\tS2MPS13_REG_L2CTRL = 55,\n\tS2MPS13_REG_L3CTRL = 56,\n\tS2MPS13_REG_L4CTRL = 57,\n\tS2MPS13_REG_L5CTRL = 58,\n\tS2MPS13_REG_L6CTRL = 59,\n\tS2MPS13_REG_L7CTRL = 60,\n\tS2MPS13_REG_L8CTRL = 61,\n\tS2MPS13_REG_L9CTRL = 62,\n\tS2MPS13_REG_L10CTRL = 63,\n\tS2MPS13_REG_L11CTRL = 64,\n\tS2MPS13_REG_L12CTRL = 65,\n\tS2MPS13_REG_L13CTRL = 66,\n\tS2MPS13_REG_L14CTRL = 67,\n\tS2MPS13_REG_L15CTRL = 68,\n\tS2MPS13_REG_L16CTRL = 69,\n\tS2MPS13_REG_L17CTRL = 70,\n\tS2MPS13_REG_L18CTRL = 71,\n\tS2MPS13_REG_L19CTRL = 72,\n\tS2MPS13_REG_L20CTRL = 73,\n\tS2MPS13_REG_L21CTRL = 74,\n\tS2MPS13_REG_L22CTRL = 75,\n\tS2MPS13_REG_L23CTRL = 76,\n\tS2MPS13_REG_L24CTRL = 77,\n\tS2MPS13_REG_L25CTRL = 78,\n\tS2MPS13_REG_L26CTRL = 79,\n\tS2MPS13_REG_L27CTRL = 80,\n\tS2MPS13_REG_L28CTRL = 81,\n\tS2MPS13_REG_L29CTRL = 82,\n\tS2MPS13_REG_L30CTRL = 83,\n\tS2MPS13_REG_L31CTRL = 84,\n\tS2MPS13_REG_L32CTRL = 85,\n\tS2MPS13_REG_L33CTRL = 86,\n\tS2MPS13_REG_L34CTRL = 87,\n\tS2MPS13_REG_L35CTRL = 88,\n\tS2MPS13_REG_L36CTRL = 89,\n\tS2MPS13_REG_L37CTRL = 90,\n\tS2MPS13_REG_L38CTRL = 91,\n\tS2MPS13_REG_L39CTRL = 92,\n\tS2MPS13_REG_L40CTRL = 93,\n\tS2MPS13_REG_LDODSCH1 = 94,\n\tS2MPS13_REG_LDODSCH2 = 95,\n\tS2MPS13_REG_LDODSCH3 = 96,\n\tS2MPS13_REG_LDODSCH4 = 97,\n\tS2MPS13_REG_LDODSCH5 = 98,\n};\n\nenum s2mps13_regulators {\n\tS2MPS13_LDO1 = 0,\n\tS2MPS13_LDO2 = 1,\n\tS2MPS13_LDO3 = 2,\n\tS2MPS13_LDO4 = 3,\n\tS2MPS13_LDO5 = 4,\n\tS2MPS13_LDO6 = 5,\n\tS2MPS13_LDO7 = 6,\n\tS2MPS13_LDO8 = 7,\n\tS2MPS13_LDO9 = 8,\n\tS2MPS13_LDO10 = 9,\n\tS2MPS13_LDO11 = 10,\n\tS2MPS13_LDO12 = 11,\n\tS2MPS13_LDO13 = 12,\n\tS2MPS13_LDO14 = 13,\n\tS2MPS13_LDO15 = 14,\n\tS2MPS13_LDO16 = 15,\n\tS2MPS13_LDO17 = 16,\n\tS2MPS13_LDO18 = 17,\n\tS2MPS13_LDO19 = 18,\n\tS2MPS13_LDO20 = 19,\n\tS2MPS13_LDO21 = 20,\n\tS2MPS13_LDO22 = 21,\n\tS2MPS13_LDO23 = 22,\n\tS2MPS13_LDO24 = 23,\n\tS2MPS13_LDO25 = 24,\n\tS2MPS13_LDO26 = 25,\n\tS2MPS13_LDO27 = 26,\n\tS2MPS13_LDO28 = 27,\n\tS2MPS13_LDO29 = 28,\n\tS2MPS13_LDO30 = 29,\n\tS2MPS13_LDO31 = 30,\n\tS2MPS13_LDO32 = 31,\n\tS2MPS13_LDO33 = 32,\n\tS2MPS13_LDO34 = 33,\n\tS2MPS13_LDO35 = 34,\n\tS2MPS13_LDO36 = 35,\n\tS2MPS13_LDO37 = 36,\n\tS2MPS13_LDO38 = 37,\n\tS2MPS13_LDO39 = 38,\n\tS2MPS13_LDO40 = 39,\n\tS2MPS13_BUCK1 = 40,\n\tS2MPS13_BUCK2 = 41,\n\tS2MPS13_BUCK3 = 42,\n\tS2MPS13_BUCK4 = 43,\n\tS2MPS13_BUCK5 = 44,\n\tS2MPS13_BUCK6 = 45,\n\tS2MPS13_BUCK7 = 46,\n\tS2MPS13_BUCK8 = 47,\n\tS2MPS13_BUCK9 = 48,\n\tS2MPS13_BUCK10 = 49,\n\tS2MPS13_REGULATOR_MAX = 50,\n};\n\nenum s2mps14_irq {\n\tS2MPS14_IRQ_PWRONF = 0,\n\tS2MPS14_IRQ_PWRONR = 1,\n\tS2MPS14_IRQ_JIGONBF = 2,\n\tS2MPS14_IRQ_JIGONBR = 3,\n\tS2MPS14_IRQ_ACOKBF = 4,\n\tS2MPS14_IRQ_ACOKBR = 5,\n\tS2MPS14_IRQ_PWRON1S = 6,\n\tS2MPS14_IRQ_MRB = 7,\n\tS2MPS14_IRQ_RTC60S = 8,\n\tS2MPS14_IRQ_RTCA1 = 9,\n\tS2MPS14_IRQ_RTCA0 = 10,\n\tS2MPS14_IRQ_SMPL = 11,\n\tS2MPS14_IRQ_RTC1S = 12,\n\tS2MPS14_IRQ_WTSR = 13,\n\tS2MPS14_IRQ_INT120C = 14,\n\tS2MPS14_IRQ_INT140C = 15,\n\tS2MPS14_IRQ_TSD = 16,\n\tS2MPS14_IRQ_NR = 17,\n};\n\nenum s2mps14_reg {\n\tS2MPS14_REG_ID = 0,\n\tS2MPS14_REG_INT1 = 1,\n\tS2MPS14_REG_INT2 = 2,\n\tS2MPS14_REG_INT3 = 3,\n\tS2MPS14_REG_INT1M = 4,\n\tS2MPS14_REG_INT2M = 5,\n\tS2MPS14_REG_INT3M = 6,\n\tS2MPS14_REG_ST1 = 7,\n\tS2MPS14_REG_ST2 = 8,\n\tS2MPS14_REG_PWRONSRC = 9,\n\tS2MPS14_REG_OFFSRC = 10,\n\tS2MPS14_REG_BU_CHG = 11,\n\tS2MPS14_REG_RTCCTRL = 12,\n\tS2MPS14_REG_CTRL1 = 13,\n\tS2MPS14_REG_CTRL2 = 14,\n\tS2MPS14_REG_RSVD1 = 15,\n\tS2MPS14_REG_RSVD2 = 16,\n\tS2MPS14_REG_RSVD3 = 17,\n\tS2MPS14_REG_RSVD4 = 18,\n\tS2MPS14_REG_RSVD5 = 19,\n\tS2MPS14_REG_RSVD6 = 20,\n\tS2MPS14_REG_CTRL3 = 21,\n\tS2MPS14_REG_RSVD7 = 22,\n\tS2MPS14_REG_RSVD8 = 23,\n\tS2MPS14_REG_WRSTBI = 24,\n\tS2MPS14_REG_B1CTRL1 = 25,\n\tS2MPS14_REG_B1CTRL2 = 26,\n\tS2MPS14_REG_B2CTRL1 = 27,\n\tS2MPS14_REG_B2CTRL2 = 28,\n\tS2MPS14_REG_B3CTRL1 = 29,\n\tS2MPS14_REG_B3CTRL2 = 30,\n\tS2MPS14_REG_B4CTRL1 = 31,\n\tS2MPS14_REG_B4CTRL2 = 32,\n\tS2MPS14_REG_B5CTRL1 = 33,\n\tS2MPS14_REG_B5CTRL2 = 34,\n\tS2MPS14_REG_L1CTRL = 35,\n\tS2MPS14_REG_L2CTRL = 36,\n\tS2MPS14_REG_L3CTRL = 37,\n\tS2MPS14_REG_L4CTRL = 38,\n\tS2MPS14_REG_L5CTRL = 39,\n\tS2MPS14_REG_L6CTRL = 40,\n\tS2MPS14_REG_L7CTRL = 41,\n\tS2MPS14_REG_L8CTRL = 42,\n\tS2MPS14_REG_L9CTRL = 43,\n\tS2MPS14_REG_L10CTRL = 44,\n\tS2MPS14_REG_L11CTRL = 45,\n\tS2MPS14_REG_L12CTRL = 46,\n\tS2MPS14_REG_L13CTRL = 47,\n\tS2MPS14_REG_L14CTRL = 48,\n\tS2MPS14_REG_L15CTRL = 49,\n\tS2MPS14_REG_L16CTRL = 50,\n\tS2MPS14_REG_L17CTRL = 51,\n\tS2MPS14_REG_L18CTRL = 52,\n\tS2MPS14_REG_L19CTRL = 53,\n\tS2MPS14_REG_L20CTRL = 54,\n\tS2MPS14_REG_L21CTRL = 55,\n\tS2MPS14_REG_L22CTRL = 56,\n\tS2MPS14_REG_L23CTRL = 57,\n\tS2MPS14_REG_L24CTRL = 58,\n\tS2MPS14_REG_L25CTRL = 59,\n\tS2MPS14_REG_LDODSCH1 = 60,\n\tS2MPS14_REG_LDODSCH2 = 61,\n\tS2MPS14_REG_LDODSCH3 = 62,\n};\n\nenum s2mps14_regulators {\n\tS2MPS14_LDO1 = 0,\n\tS2MPS14_LDO2 = 1,\n\tS2MPS14_LDO3 = 2,\n\tS2MPS14_LDO4 = 3,\n\tS2MPS14_LDO5 = 4,\n\tS2MPS14_LDO6 = 5,\n\tS2MPS14_LDO7 = 6,\n\tS2MPS14_LDO8 = 7,\n\tS2MPS14_LDO9 = 8,\n\tS2MPS14_LDO10 = 9,\n\tS2MPS14_LDO11 = 10,\n\tS2MPS14_LDO12 = 11,\n\tS2MPS14_LDO13 = 12,\n\tS2MPS14_LDO14 = 13,\n\tS2MPS14_LDO15 = 14,\n\tS2MPS14_LDO16 = 15,\n\tS2MPS14_LDO17 = 16,\n\tS2MPS14_LDO18 = 17,\n\tS2MPS14_LDO19 = 18,\n\tS2MPS14_LDO20 = 19,\n\tS2MPS14_LDO21 = 20,\n\tS2MPS14_LDO22 = 21,\n\tS2MPS14_LDO23 = 22,\n\tS2MPS14_LDO24 = 23,\n\tS2MPS14_LDO25 = 24,\n\tS2MPS14_BUCK1 = 25,\n\tS2MPS14_BUCK2 = 26,\n\tS2MPS14_BUCK3 = 27,\n\tS2MPS14_BUCK4 = 28,\n\tS2MPS14_BUCK5 = 29,\n\tS2MPS14_REGULATOR_MAX = 30,\n};\n\nenum s2mps15_reg {\n\tS2MPS15_REG_ID = 0,\n\tS2MPS15_REG_INT1 = 1,\n\tS2MPS15_REG_INT2 = 2,\n\tS2MPS15_REG_INT3 = 3,\n\tS2MPS15_REG_INT1M = 4,\n\tS2MPS15_REG_INT2M = 5,\n\tS2MPS15_REG_INT3M = 6,\n\tS2MPS15_REG_ST1 = 7,\n\tS2MPS15_REG_ST2 = 8,\n\tS2MPS15_REG_PWRONSRC = 9,\n\tS2MPS15_REG_OFFSRC = 10,\n\tS2MPS15_REG_BU_CHG = 11,\n\tS2MPS15_REG_RTC_BUF = 12,\n\tS2MPS15_REG_CTRL1 = 13,\n\tS2MPS15_REG_CTRL2 = 14,\n\tS2MPS15_REG_RSVD1 = 15,\n\tS2MPS15_REG_RSVD2 = 16,\n\tS2MPS15_REG_RSVD3 = 17,\n\tS2MPS15_REG_RSVD4 = 18,\n\tS2MPS15_REG_RSVD5 = 19,\n\tS2MPS15_REG_RSVD6 = 20,\n\tS2MPS15_REG_CTRL3 = 21,\n\tS2MPS15_REG_RSVD7 = 22,\n\tS2MPS15_REG_RSVD8 = 23,\n\tS2MPS15_REG_RSVD9 = 24,\n\tS2MPS15_REG_B1CTRL1 = 25,\n\tS2MPS15_REG_B1CTRL2 = 26,\n\tS2MPS15_REG_B2CTRL1 = 27,\n\tS2MPS15_REG_B2CTRL2 = 28,\n\tS2MPS15_REG_B3CTRL1 = 29,\n\tS2MPS15_REG_B3CTRL2 = 30,\n\tS2MPS15_REG_B4CTRL1 = 31,\n\tS2MPS15_REG_B4CTRL2 = 32,\n\tS2MPS15_REG_B5CTRL1 = 33,\n\tS2MPS15_REG_B5CTRL2 = 34,\n\tS2MPS15_REG_B6CTRL1 = 35,\n\tS2MPS15_REG_B6CTRL2 = 36,\n\tS2MPS15_REG_B7CTRL1 = 37,\n\tS2MPS15_REG_B7CTRL2 = 38,\n\tS2MPS15_REG_B8CTRL1 = 39,\n\tS2MPS15_REG_B8CTRL2 = 40,\n\tS2MPS15_REG_B9CTRL1 = 41,\n\tS2MPS15_REG_B9CTRL2 = 42,\n\tS2MPS15_REG_B10CTRL1 = 43,\n\tS2MPS15_REG_B10CTRL2 = 44,\n\tS2MPS15_REG_BBCTRL1 = 45,\n\tS2MPS15_REG_BBCTRL2 = 46,\n\tS2MPS15_REG_BRAMP = 47,\n\tS2MPS15_REG_LDODVS1 = 48,\n\tS2MPS15_REG_LDODVS2 = 49,\n\tS2MPS15_REG_LDODVS3 = 50,\n\tS2MPS15_REG_LDODVS4 = 51,\n\tS2MPS15_REG_L1CTRL = 52,\n\tS2MPS15_REG_L2CTRL = 53,\n\tS2MPS15_REG_L3CTRL = 54,\n\tS2MPS15_REG_L4CTRL = 55,\n\tS2MPS15_REG_L5CTRL = 56,\n\tS2MPS15_REG_L6CTRL = 57,\n\tS2MPS15_REG_L7CTRL = 58,\n\tS2MPS15_REG_L8CTRL = 59,\n\tS2MPS15_REG_L9CTRL = 60,\n\tS2MPS15_REG_L10CTRL = 61,\n\tS2MPS15_REG_L11CTRL = 62,\n\tS2MPS15_REG_L12CTRL = 63,\n\tS2MPS15_REG_L13CTRL = 64,\n\tS2MPS15_REG_L14CTRL = 65,\n\tS2MPS15_REG_L15CTRL = 66,\n\tS2MPS15_REG_L16CTRL = 67,\n\tS2MPS15_REG_L17CTRL = 68,\n\tS2MPS15_REG_L18CTRL = 69,\n\tS2MPS15_REG_L19CTRL = 70,\n\tS2MPS15_REG_L20CTRL = 71,\n\tS2MPS15_REG_L21CTRL = 72,\n\tS2MPS15_REG_L22CTRL = 73,\n\tS2MPS15_REG_L23CTRL = 74,\n\tS2MPS15_REG_L24CTRL = 75,\n\tS2MPS15_REG_L25CTRL = 76,\n\tS2MPS15_REG_L26CTRL = 77,\n\tS2MPS15_REG_L27CTRL = 78,\n\tS2MPS15_REG_LDODSCH1 = 79,\n\tS2MPS15_REG_LDODSCH2 = 80,\n\tS2MPS15_REG_LDODSCH3 = 81,\n\tS2MPS15_REG_LDODSCH4 = 82,\n};\n\nenum s2mps15_regulators {\n\tS2MPS15_LDO1 = 0,\n\tS2MPS15_LDO2 = 1,\n\tS2MPS15_LDO3 = 2,\n\tS2MPS15_LDO4 = 3,\n\tS2MPS15_LDO5 = 4,\n\tS2MPS15_LDO6 = 5,\n\tS2MPS15_LDO7 = 6,\n\tS2MPS15_LDO8 = 7,\n\tS2MPS15_LDO9 = 8,\n\tS2MPS15_LDO10 = 9,\n\tS2MPS15_LDO11 = 10,\n\tS2MPS15_LDO12 = 11,\n\tS2MPS15_LDO13 = 12,\n\tS2MPS15_LDO14 = 13,\n\tS2MPS15_LDO15 = 14,\n\tS2MPS15_LDO16 = 15,\n\tS2MPS15_LDO17 = 16,\n\tS2MPS15_LDO18 = 17,\n\tS2MPS15_LDO19 = 18,\n\tS2MPS15_LDO20 = 19,\n\tS2MPS15_LDO21 = 20,\n\tS2MPS15_LDO22 = 21,\n\tS2MPS15_LDO23 = 22,\n\tS2MPS15_LDO24 = 23,\n\tS2MPS15_LDO25 = 24,\n\tS2MPS15_LDO26 = 25,\n\tS2MPS15_LDO27 = 26,\n\tS2MPS15_BUCK1 = 27,\n\tS2MPS15_BUCK2 = 28,\n\tS2MPS15_BUCK3 = 29,\n\tS2MPS15_BUCK4 = 30,\n\tS2MPS15_BUCK5 = 31,\n\tS2MPS15_BUCK6 = 32,\n\tS2MPS15_BUCK7 = 33,\n\tS2MPS15_BUCK8 = 34,\n\tS2MPS15_BUCK9 = 35,\n\tS2MPS15_BUCK10 = 36,\n\tS2MPS15_BUCK11 = 37,\n\tS2MPS15_REGULATOR_MAX = 38,\n};\n\nenum s2mps_rtc_reg {\n\tS2MPS_RTC_CTRL = 0,\n\tS2MPS_WTSR_SMPL_CNTL = 1,\n\tS2MPS_RTC_UDR_CON = 2,\n\tS2MPS_RSVD = 3,\n\tS2MPS_RTC_SEC = 4,\n\tS2MPS_RTC_MIN = 5,\n\tS2MPS_RTC_HOUR = 6,\n\tS2MPS_RTC_WEEKDAY = 7,\n\tS2MPS_RTC_DATE = 8,\n\tS2MPS_RTC_MONTH = 9,\n\tS2MPS_RTC_YEAR = 10,\n\tS2MPS_ALARM0_SEC = 11,\n\tS2MPS_ALARM0_MIN = 12,\n\tS2MPS_ALARM0_HOUR = 13,\n\tS2MPS_ALARM0_WEEKDAY = 14,\n\tS2MPS_ALARM0_DATE = 15,\n\tS2MPS_ALARM0_MONTH = 16,\n\tS2MPS_ALARM0_YEAR = 17,\n\tS2MPS_ALARM1_SEC = 18,\n\tS2MPS_ALARM1_MIN = 19,\n\tS2MPS_ALARM1_HOUR = 20,\n\tS2MPS_ALARM1_WEEKDAY = 21,\n\tS2MPS_ALARM1_DATE = 22,\n\tS2MPS_ALARM1_MONTH = 23,\n\tS2MPS_ALARM1_YEAR = 24,\n\tS2MPS_OFFSRC = 25,\n\tS2MPS_RTC_REG_MAX = 26,\n};\n\nenum s2mpu02_irq {\n\tS2MPU02_IRQ_PWRONF = 0,\n\tS2MPU02_IRQ_PWRONR = 1,\n\tS2MPU02_IRQ_JIGONBF = 2,\n\tS2MPU02_IRQ_JIGONBR = 3,\n\tS2MPU02_IRQ_ACOKBF = 4,\n\tS2MPU02_IRQ_ACOKBR = 5,\n\tS2MPU02_IRQ_PWRON1S = 6,\n\tS2MPU02_IRQ_MRB = 7,\n\tS2MPU02_IRQ_RTC60S = 8,\n\tS2MPU02_IRQ_RTCA1 = 9,\n\tS2MPU02_IRQ_RTCA0 = 10,\n\tS2MPU02_IRQ_SMPL = 11,\n\tS2MPU02_IRQ_RTC1S = 12,\n\tS2MPU02_IRQ_WTSR = 13,\n\tS2MPU02_IRQ_INT120C = 14,\n\tS2MPU02_IRQ_INT140C = 15,\n\tS2MPU02_IRQ_TSD = 16,\n\tS2MPU02_IRQ_NR = 17,\n};\n\nenum s2mpu05_irq {\n\tS2MPU05_IRQ_PWRONF = 0,\n\tS2MPU05_IRQ_PWRONR = 1,\n\tS2MPU05_IRQ_JIGONBF = 2,\n\tS2MPU05_IRQ_JIGONBR = 3,\n\tS2MPU05_IRQ_ACOKF = 4,\n\tS2MPU05_IRQ_ACOKR = 5,\n\tS2MPU05_IRQ_PWRON1S = 6,\n\tS2MPU05_IRQ_MRB = 7,\n\tS2MPU05_IRQ_RTC60S = 8,\n\tS2MPU05_IRQ_RTCA1 = 9,\n\tS2MPU05_IRQ_RTCA0 = 10,\n\tS2MPU05_IRQ_SMPL = 11,\n\tS2MPU05_IRQ_RTC1S = 12,\n\tS2MPU05_IRQ_WTSR = 13,\n\tS2MPU05_IRQ_INT120C = 14,\n\tS2MPU05_IRQ_INT140C = 15,\n\tS2MPU05_IRQ_TSD = 16,\n\tS2MPU05_IRQ_NR = 17,\n};\n\nenum s3c24xx_i2c_state {\n\tSTATE_IDLE___4 = 0,\n\tSTATE_START___2 = 1,\n\tSTATE_READ___3 = 2,\n\tSTATE_WRITE___3 = 3,\n\tSTATE_STOP___2 = 4,\n};\n\nenum s3c24xx_port_type {\n\tTYPE_S3C6400 = 0,\n\tTYPE_APPLE_S5L = 1,\n};\n\nenum s5m8767_irq {\n\tS5M8767_IRQ_PWRR = 0,\n\tS5M8767_IRQ_PWRF = 1,\n\tS5M8767_IRQ_PWR1S = 2,\n\tS5M8767_IRQ_JIGR = 3,\n\tS5M8767_IRQ_JIGF = 4,\n\tS5M8767_IRQ_LOWBAT2 = 5,\n\tS5M8767_IRQ_LOWBAT1 = 6,\n\tS5M8767_IRQ_MRB = 7,\n\tS5M8767_IRQ_DVSOK2 = 8,\n\tS5M8767_IRQ_DVSOK3 = 9,\n\tS5M8767_IRQ_DVSOK4 = 10,\n\tS5M8767_IRQ_RTC60S = 11,\n\tS5M8767_IRQ_RTCA1 = 12,\n\tS5M8767_IRQ_RTCA2 = 13,\n\tS5M8767_IRQ_SMPL = 14,\n\tS5M8767_IRQ_RTC1S = 15,\n\tS5M8767_IRQ_WTSR = 16,\n\tS5M8767_IRQ_NR = 17,\n};\n\nenum s5m8767_reg {\n\tS5M8767_REG_ID = 0,\n\tS5M8767_REG_INT1 = 1,\n\tS5M8767_REG_INT2 = 2,\n\tS5M8767_REG_INT3 = 3,\n\tS5M8767_REG_INT1M = 4,\n\tS5M8767_REG_INT2M = 5,\n\tS5M8767_REG_INT3M = 6,\n\tS5M8767_REG_STATUS1 = 7,\n\tS5M8767_REG_STATUS2 = 8,\n\tS5M8767_REG_STATUS3 = 9,\n\tS5M8767_REG_CTRL1 = 10,\n\tS5M8767_REG_CTRL2 = 11,\n\tS5M8767_REG_LOWBAT1 = 12,\n\tS5M8767_REG_LOWBAT2 = 13,\n\tS5M8767_REG_BUCHG = 14,\n\tS5M8767_REG_DVSRAMP = 15,\n\tS5M8767_REG_DVSTIMER2 = 16,\n\tS5M8767_REG_DVSTIMER3 = 17,\n\tS5M8767_REG_DVSTIMER4 = 18,\n\tS5M8767_REG_LDO1 = 19,\n\tS5M8767_REG_LDO2 = 20,\n\tS5M8767_REG_LDO3 = 21,\n\tS5M8767_REG_LDO4 = 22,\n\tS5M8767_REG_LDO5 = 23,\n\tS5M8767_REG_LDO6 = 24,\n\tS5M8767_REG_LDO7 = 25,\n\tS5M8767_REG_LDO8 = 26,\n\tS5M8767_REG_LDO9 = 27,\n\tS5M8767_REG_LDO10 = 28,\n\tS5M8767_REG_LDO11 = 29,\n\tS5M8767_REG_LDO12 = 30,\n\tS5M8767_REG_LDO13 = 31,\n\tS5M8767_REG_LDO14 = 32,\n\tS5M8767_REG_LDO15 = 33,\n\tS5M8767_REG_LDO16 = 34,\n\tS5M8767_REG_LDO17 = 35,\n\tS5M8767_REG_LDO18 = 36,\n\tS5M8767_REG_LDO19 = 37,\n\tS5M8767_REG_LDO20 = 38,\n\tS5M8767_REG_LDO21 = 39,\n\tS5M8767_REG_LDO22 = 40,\n\tS5M8767_REG_LDO23 = 41,\n\tS5M8767_REG_LDO24 = 42,\n\tS5M8767_REG_LDO25 = 43,\n\tS5M8767_REG_LDO26 = 44,\n\tS5M8767_REG_LDO27 = 45,\n\tS5M8767_REG_LDO28 = 46,\n\tS5M8767_REG_UVLO = 49,\n\tS5M8767_REG_BUCK1CTRL1 = 50,\n\tS5M8767_REG_BUCK1CTRL2 = 51,\n\tS5M8767_REG_BUCK2CTRL = 52,\n\tS5M8767_REG_BUCK2DVS1 = 53,\n\tS5M8767_REG_BUCK2DVS2 = 54,\n\tS5M8767_REG_BUCK2DVS3 = 55,\n\tS5M8767_REG_BUCK2DVS4 = 56,\n\tS5M8767_REG_BUCK2DVS5 = 57,\n\tS5M8767_REG_BUCK2DVS6 = 58,\n\tS5M8767_REG_BUCK2DVS7 = 59,\n\tS5M8767_REG_BUCK2DVS8 = 60,\n\tS5M8767_REG_BUCK3CTRL = 61,\n\tS5M8767_REG_BUCK3DVS1 = 62,\n\tS5M8767_REG_BUCK3DVS2 = 63,\n\tS5M8767_REG_BUCK3DVS3 = 64,\n\tS5M8767_REG_BUCK3DVS4 = 65,\n\tS5M8767_REG_BUCK3DVS5 = 66,\n\tS5M8767_REG_BUCK3DVS6 = 67,\n\tS5M8767_REG_BUCK3DVS7 = 68,\n\tS5M8767_REG_BUCK3DVS8 = 69,\n\tS5M8767_REG_BUCK4CTRL = 70,\n\tS5M8767_REG_BUCK4DVS1 = 71,\n\tS5M8767_REG_BUCK4DVS2 = 72,\n\tS5M8767_REG_BUCK4DVS3 = 73,\n\tS5M8767_REG_BUCK4DVS4 = 74,\n\tS5M8767_REG_BUCK4DVS5 = 75,\n\tS5M8767_REG_BUCK4DVS6 = 76,\n\tS5M8767_REG_BUCK4DVS7 = 77,\n\tS5M8767_REG_BUCK4DVS8 = 78,\n\tS5M8767_REG_BUCK5CTRL1 = 79,\n\tS5M8767_REG_BUCK5CTRL2 = 80,\n\tS5M8767_REG_BUCK5CTRL3 = 81,\n\tS5M8767_REG_BUCK5CTRL4 = 82,\n\tS5M8767_REG_BUCK5CTRL5 = 83,\n\tS5M8767_REG_BUCK6CTRL1 = 84,\n\tS5M8767_REG_BUCK6CTRL2 = 85,\n\tS5M8767_REG_BUCK7CTRL1 = 86,\n\tS5M8767_REG_BUCK7CTRL2 = 87,\n\tS5M8767_REG_BUCK8CTRL1 = 88,\n\tS5M8767_REG_BUCK8CTRL2 = 89,\n\tS5M8767_REG_BUCK9CTRL1 = 90,\n\tS5M8767_REG_BUCK9CTRL2 = 91,\n\tS5M8767_REG_LDO1CTRL = 92,\n\tS5M8767_REG_LDO2_1CTRL = 93,\n\tS5M8767_REG_LDO2_2CTRL = 94,\n\tS5M8767_REG_LDO2_3CTRL = 95,\n\tS5M8767_REG_LDO2_4CTRL = 96,\n\tS5M8767_REG_LDO3CTRL = 97,\n\tS5M8767_REG_LDO4CTRL = 98,\n\tS5M8767_REG_LDO5CTRL = 99,\n\tS5M8767_REG_LDO6CTRL = 100,\n\tS5M8767_REG_LDO7CTRL = 101,\n\tS5M8767_REG_LDO8CTRL = 102,\n\tS5M8767_REG_LDO9CTRL = 103,\n\tS5M8767_REG_LDO10CTRL = 104,\n\tS5M8767_REG_LDO11CTRL = 105,\n\tS5M8767_REG_LDO12CTRL = 106,\n\tS5M8767_REG_LDO13CTRL = 107,\n\tS5M8767_REG_LDO14CTRL = 108,\n\tS5M8767_REG_LDO15CTRL = 109,\n\tS5M8767_REG_LDO16CTRL = 110,\n\tS5M8767_REG_LDO17CTRL = 111,\n\tS5M8767_REG_LDO18CTRL = 112,\n\tS5M8767_REG_LDO19CTRL = 113,\n\tS5M8767_REG_LDO20CTRL = 114,\n\tS5M8767_REG_LDO21CTRL = 115,\n\tS5M8767_REG_LDO22CTRL = 116,\n\tS5M8767_REG_LDO23CTRL = 117,\n\tS5M8767_REG_LDO24CTRL = 118,\n\tS5M8767_REG_LDO25CTRL = 119,\n\tS5M8767_REG_LDO26CTRL = 120,\n\tS5M8767_REG_LDO27CTRL = 121,\n\tS5M8767_REG_LDO28CTRL = 122,\n};\n\nenum s5m_rtc_reg {\n\tS5M_RTC_SEC = 0,\n\tS5M_RTC_MIN = 1,\n\tS5M_RTC_HOUR = 2,\n\tS5M_RTC_WEEKDAY = 3,\n\tS5M_RTC_DATE = 4,\n\tS5M_RTC_MONTH = 5,\n\tS5M_RTC_YEAR1 = 6,\n\tS5M_RTC_YEAR2 = 7,\n\tS5M_ALARM0_SEC = 8,\n\tS5M_ALARM0_MIN = 9,\n\tS5M_ALARM0_HOUR = 10,\n\tS5M_ALARM0_WEEKDAY = 11,\n\tS5M_ALARM0_DATE = 12,\n\tS5M_ALARM0_MONTH = 13,\n\tS5M_ALARM0_YEAR1 = 14,\n\tS5M_ALARM0_YEAR2 = 15,\n\tS5M_ALARM1_SEC = 16,\n\tS5M_ALARM1_MIN = 17,\n\tS5M_ALARM1_HOUR = 18,\n\tS5M_ALARM1_WEEKDAY = 19,\n\tS5M_ALARM1_DATE = 20,\n\tS5M_ALARM1_MONTH = 21,\n\tS5M_ALARM1_YEAR1 = 22,\n\tS5M_ALARM1_YEAR2 = 23,\n\tS5M_ALARM0_CONF = 24,\n\tS5M_ALARM1_CONF = 25,\n\tS5M_RTC_STATUS = 26,\n\tS5M_WTSR_SMPL_CNTL = 27,\n\tS5M_RTC_UDR_CON = 28,\n\tS5M_RTC_REG_MAX = 29,\n};\n\nenum s700_pinconf_pull {\n\tOWL_PINCONF_PULL_DOWN = 0,\n\tOWL_PINCONF_PULL_UP = 1,\n};\n\nenum s700_pinmux_functions {\n\tS700_MUX_NOR = 0,\n\tS700_MUX_ETH_RGMII = 1,\n\tS700_MUX_ETH_SGMII = 2,\n\tS700_MUX_SPI0 = 3,\n\tS700_MUX_SPI1 = 4,\n\tS700_MUX_SPI2 = 5,\n\tS700_MUX_SPI3 = 6,\n\tS700_MUX_SENS0 = 7,\n\tS700_MUX_SENS1 = 8,\n\tS700_MUX_UART0 = 9,\n\tS700_MUX_UART1 = 10,\n\tS700_MUX_UART2 = 11,\n\tS700_MUX_UART3 = 12,\n\tS700_MUX_UART4 = 13,\n\tS700_MUX_UART5 = 14,\n\tS700_MUX_UART6 = 15,\n\tS700_MUX_I2S0 = 16,\n\tS700_MUX_I2S1 = 17,\n\tS700_MUX_PCM1 = 18,\n\tS700_MUX_PCM0 = 19,\n\tS700_MUX_KS = 20,\n\tS700_MUX_JTAG = 21,\n\tS700_MUX_PWM0 = 22,\n\tS700_MUX_PWM1 = 23,\n\tS700_MUX_PWM2 = 24,\n\tS700_MUX_PWM3 = 25,\n\tS700_MUX_PWM4 = 26,\n\tS700_MUX_PWM5 = 27,\n\tS700_MUX_P0 = 28,\n\tS700_MUX_SD0 = 29,\n\tS700_MUX_SD1 = 30,\n\tS700_MUX_SD2 = 31,\n\tS700_MUX_I2C0 = 32,\n\tS700_MUX_I2C1 = 33,\n\tS700_MUX_I2C2 = 34,\n\tS700_MUX_I2C3 = 35,\n\tS700_MUX_DSI = 36,\n\tS700_MUX_LVDS = 37,\n\tS700_MUX_USB30 = 38,\n\tS700_MUX_CLKO_25M = 39,\n\tS700_MUX_MIPI_CSI = 40,\n\tS700_MUX_NAND = 41,\n\tS700_MUX_SPDIF = 42,\n\tS700_MUX_SIRQ0 = 43,\n\tS700_MUX_SIRQ1 = 44,\n\tS700_MUX_SIRQ2 = 45,\n\tS700_MUX_BT = 46,\n\tS700_MUX_LCD0 = 47,\n\tS700_MUX_RESERVED = 48,\n};\n\nenum s900_pinconf_pull {\n\tOWL_PINCONF_PULL_HIZ = 0,\n\tOWL_PINCONF_PULL_DOWN___2 = 1,\n\tOWL_PINCONF_PULL_UP___2 = 2,\n\tOWL_PINCONF_PULL_HOLD = 3,\n};\n\nenum s900_pinmux_functions {\n\tS900_MUX_ERAM = 0,\n\tS900_MUX_ETH_RMII = 1,\n\tS900_MUX_ETH_SMII = 2,\n\tS900_MUX_SPI0 = 3,\n\tS900_MUX_SPI1 = 4,\n\tS900_MUX_SPI2 = 5,\n\tS900_MUX_SPI3 = 6,\n\tS900_MUX_SENS0 = 7,\n\tS900_MUX_UART0 = 8,\n\tS900_MUX_UART1 = 9,\n\tS900_MUX_UART2 = 10,\n\tS900_MUX_UART3 = 11,\n\tS900_MUX_UART4 = 12,\n\tS900_MUX_UART5 = 13,\n\tS900_MUX_UART6 = 14,\n\tS900_MUX_I2S0 = 15,\n\tS900_MUX_I2S1 = 16,\n\tS900_MUX_PCM0 = 17,\n\tS900_MUX_PCM1 = 18,\n\tS900_MUX_JTAG = 19,\n\tS900_MUX_PWM0 = 20,\n\tS900_MUX_PWM1 = 21,\n\tS900_MUX_PWM2 = 22,\n\tS900_MUX_PWM3 = 23,\n\tS900_MUX_PWM4 = 24,\n\tS900_MUX_PWM5 = 25,\n\tS900_MUX_SD0 = 26,\n\tS900_MUX_SD1 = 27,\n\tS900_MUX_SD2 = 28,\n\tS900_MUX_SD3 = 29,\n\tS900_MUX_I2C0 = 30,\n\tS900_MUX_I2C1 = 31,\n\tS900_MUX_I2C2 = 32,\n\tS900_MUX_I2C3 = 33,\n\tS900_MUX_I2C4 = 34,\n\tS900_MUX_I2C5 = 35,\n\tS900_MUX_LVDS = 36,\n\tS900_MUX_USB20 = 37,\n\tS900_MUX_USB30 = 38,\n\tS900_MUX_GPU = 39,\n\tS900_MUX_MIPI_CSI0 = 40,\n\tS900_MUX_MIPI_CSI1 = 41,\n\tS900_MUX_MIPI_DSI = 42,\n\tS900_MUX_NAND0 = 43,\n\tS900_MUX_NAND1 = 44,\n\tS900_MUX_SPDIF = 45,\n\tS900_MUX_SIRQ0 = 46,\n\tS900_MUX_SIRQ1 = 47,\n\tS900_MUX_SIRQ2 = 48,\n\tS900_MUX_AUX_START = 49,\n\tS900_MUX_MAX = 50,\n\tS900_MUX_RESERVED = 51,\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sa8775p_functions {\n\tmsm_mux_gpio___20 = 0,\n\tmsm_mux_atest_char___17 = 1,\n\tmsm_mux_atest_usb2___3 = 2,\n\tmsm_mux_audio_ref___4 = 3,\n\tmsm_mux_cam_mclk___10 = 4,\n\tmsm_mux_cci_async___8 = 5,\n\tmsm_mux_cci_i2c___7 = 6,\n\tmsm_mux_cci_timer0___7 = 7,\n\tmsm_mux_cci_timer1___7 = 8,\n\tmsm_mux_cci_timer2___7 = 9,\n\tmsm_mux_cci_timer3___6 = 10,\n\tmsm_mux_cci_timer4___5 = 11,\n\tmsm_mux_cci_timer5 = 12,\n\tmsm_mux_cci_timer6 = 13,\n\tmsm_mux_cci_timer7 = 14,\n\tmsm_mux_cci_timer8 = 15,\n\tmsm_mux_cci_timer9 = 16,\n\tmsm_mux_cri_trng___11 = 17,\n\tmsm_mux_cri_trng0___12 = 18,\n\tmsm_mux_cri_trng1___12 = 19,\n\tmsm_mux_dbg_out___14 = 20,\n\tmsm_mux_ddr_bist___8 = 21,\n\tmsm_mux_ddr_pxi0___6 = 22,\n\tmsm_mux_ddr_pxi1___6 = 23,\n\tmsm_mux_ddr_pxi2___5 = 24,\n\tmsm_mux_ddr_pxi3___5 = 25,\n\tmsm_mux_ddr_pxi4___2 = 26,\n\tmsm_mux_ddr_pxi5___2 = 27,\n\tmsm_mux_edp0_hot___2 = 28,\n\tmsm_mux_edp0_lcd___2 = 29,\n\tmsm_mux_edp1_hot = 30,\n\tmsm_mux_edp1_lcd___2 = 31,\n\tmsm_mux_edp2_hot = 32,\n\tmsm_mux_edp2_lcd = 33,\n\tmsm_mux_edp3_hot = 34,\n\tmsm_mux_edp3_lcd = 35,\n\tmsm_mux_egpio___5 = 36,\n\tmsm_mux_emac0_mcg0___2 = 37,\n\tmsm_mux_emac0_mcg1___2 = 38,\n\tmsm_mux_emac0_mcg2___2 = 39,\n\tmsm_mux_emac0_mcg3___2 = 40,\n\tmsm_mux_emac0_mdc___2 = 41,\n\tmsm_mux_emac0_mdio___2 = 42,\n\tmsm_mux_emac0_ptp_aux___2 = 43,\n\tmsm_mux_emac0_ptp_pps___2 = 44,\n\tmsm_mux_emac1_mcg0 = 45,\n\tmsm_mux_emac1_mcg1 = 46,\n\tmsm_mux_emac1_mcg2 = 47,\n\tmsm_mux_emac1_mcg3 = 48,\n\tmsm_mux_emac1_mdc = 49,\n\tmsm_mux_emac1_mdio = 50,\n\tmsm_mux_emac1_ptp_aux = 51,\n\tmsm_mux_emac1_ptp_pps = 52,\n\tmsm_mux_gcc_gp1___6 = 53,\n\tmsm_mux_gcc_gp2___6 = 54,\n\tmsm_mux_gcc_gp3___6 = 55,\n\tmsm_mux_gcc_gp4___2 = 56,\n\tmsm_mux_gcc_gp5___2 = 57,\n\tmsm_mux_hs0_mi2s___3 = 58,\n\tmsm_mux_hs1_mi2s___3 = 59,\n\tmsm_mux_hs2_mi2s___2 = 60,\n\tmsm_mux_ibi_i3c___4 = 61,\n\tmsm_mux_jitter_bist___7 = 62,\n\tmsm_mux_mdp0_vsync0___2 = 63,\n\tmsm_mux_mdp0_vsync1___2 = 64,\n\tmsm_mux_mdp0_vsync2 = 65,\n\tmsm_mux_mdp0_vsync3___2 = 66,\n\tmsm_mux_mdp0_vsync4 = 67,\n\tmsm_mux_mdp0_vsync5 = 68,\n\tmsm_mux_mdp0_vsync6___2 = 69,\n\tmsm_mux_mdp0_vsync7___2 = 70,\n\tmsm_mux_mdp0_vsync8 = 71,\n\tmsm_mux_mdp1_vsync0 = 72,\n\tmsm_mux_mdp1_vsync1 = 73,\n\tmsm_mux_mdp1_vsync2 = 74,\n\tmsm_mux_mdp1_vsync3 = 75,\n\tmsm_mux_mdp1_vsync4 = 76,\n\tmsm_mux_mdp1_vsync5 = 77,\n\tmsm_mux_mdp1_vsync6 = 78,\n\tmsm_mux_mdp1_vsync7 = 79,\n\tmsm_mux_mdp1_vsync8 = 80,\n\tmsm_mux_mdp_vsync___12 = 81,\n\tmsm_mux_mi2s1_data0___2 = 82,\n\tmsm_mux_mi2s1_data1___2 = 83,\n\tmsm_mux_mi2s1_sck___2 = 84,\n\tmsm_mux_mi2s1_ws___2 = 85,\n\tmsm_mux_mi2s2_data0___2 = 86,\n\tmsm_mux_mi2s2_data1___2 = 87,\n\tmsm_mux_mi2s2_sck___2 = 88,\n\tmsm_mux_mi2s2_ws___2 = 89,\n\tmsm_mux_mi2s_mclk0___2 = 90,\n\tmsm_mux_mi2s_mclk1___2 = 91,\n\tmsm_mux_pcie0_clkreq___2 = 92,\n\tmsm_mux_pcie1_clkreq___2 = 93,\n\tmsm_mux_phase_flag___8 = 94,\n\tmsm_mux_pll_bist___6 = 95,\n\tmsm_mux_pll_clk___3 = 96,\n\tmsm_mux_prng_rosc0___7 = 97,\n\tmsm_mux_prng_rosc1___7 = 98,\n\tmsm_mux_prng_rosc2___7 = 99,\n\tmsm_mux_prng_rosc3___7 = 100,\n\tmsm_mux_qdss_cti___8 = 101,\n\tmsm_mux_qdss_gpio___6 = 102,\n\tmsm_mux_qup0_se0___3 = 103,\n\tmsm_mux_qup0_se1___3 = 104,\n\tmsm_mux_qup0_se2___3 = 105,\n\tmsm_mux_qup0_se3___3 = 106,\n\tmsm_mux_qup0_se4___3 = 107,\n\tmsm_mux_qup0_se5___3 = 108,\n\tmsm_mux_qup1_se0___4 = 109,\n\tmsm_mux_qup1_se1___4 = 110,\n\tmsm_mux_qup1_se2___4 = 111,\n\tmsm_mux_qup1_se3___4 = 112,\n\tmsm_mux_qup1_se4___4 = 113,\n\tmsm_mux_qup1_se5___4 = 114,\n\tmsm_mux_qup1_se6___4 = 115,\n\tmsm_mux_qup2_se0___3 = 116,\n\tmsm_mux_qup2_se1___2 = 117,\n\tmsm_mux_qup2_se2___2 = 118,\n\tmsm_mux_qup2_se3___2 = 119,\n\tmsm_mux_qup2_se4___2 = 120,\n\tmsm_mux_qup2_se5 = 121,\n\tmsm_mux_qup2_se6 = 122,\n\tmsm_mux_qup3_se0___2 = 123,\n\tmsm_mux_sail_top = 124,\n\tmsm_mux_sailss_emac0___2 = 125,\n\tmsm_mux_sailss_ospi___2 = 126,\n\tmsm_mux_sgmii_phy___2 = 127,\n\tmsm_mux_tb_trig___3 = 128,\n\tmsm_mux_tgu_ch0___5 = 129,\n\tmsm_mux_tgu_ch1___5 = 130,\n\tmsm_mux_tgu_ch2___4 = 131,\n\tmsm_mux_tgu_ch3___4 = 132,\n\tmsm_mux_tgu_ch4___2 = 133,\n\tmsm_mux_tgu_ch5___2 = 134,\n\tmsm_mux_tsense_pwm1___7 = 135,\n\tmsm_mux_tsense_pwm2___7 = 136,\n\tmsm_mux_tsense_pwm3___3 = 137,\n\tmsm_mux_tsense_pwm4___3 = 138,\n\tmsm_mux_usb2phy_ac___3 = 139,\n\tmsm_mux_vsense_trigger___4 = 140,\n\tmsm_mux_____15 = 141,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum samsung_pll_type {\n\tpll_2126 = 0,\n\tpll_3000 = 1,\n\tpll_35xx = 2,\n\tpll_36xx = 3,\n\tpll_2550 = 4,\n\tpll_2650 = 5,\n\tpll_4500 = 6,\n\tpll_4502 = 7,\n\tpll_4508 = 8,\n\tpll_4600 = 9,\n\tpll_4650 = 10,\n\tpll_4650c = 11,\n\tpll_6552 = 12,\n\tpll_6552_s3c2416 = 13,\n\tpll_6553 = 14,\n\tpll_2550x = 15,\n\tpll_2550xx = 16,\n\tpll_2650x = 17,\n\tpll_2650xx = 18,\n\tpll_1417x = 19,\n\tpll_1418x = 20,\n\tpll_1450x = 21,\n\tpll_1451x = 22,\n\tpll_1452x = 23,\n\tpll_1460x = 24,\n\tpll_0818x = 25,\n\tpll_0822x = 26,\n\tpll_0831x = 27,\n\tpll_142xx = 28,\n\tpll_0516x = 29,\n\tpll_0517x = 30,\n\tpll_0518x = 31,\n\tpll_531x = 32,\n\tpll_1051x = 33,\n\tpll_1052x = 34,\n\tpll_0717x = 35,\n\tpll_0718x = 36,\n\tpll_0732x = 37,\n\tpll_4311 = 38,\n\tpll_1017x = 39,\n\tpll_1031x = 40,\n};\n\nenum sas_device_type {\n\tSAS_PHY_UNUSED = 0,\n\tSAS_END_DEVICE = 1,\n\tSAS_EDGE_EXPANDER_DEVICE = 2,\n\tSAS_FANOUT_EXPANDER_DEVICE = 3,\n\tSAS_HA = 4,\n\tSAS_SATA_DEV = 5,\n\tSAS_SATA_PM = 7,\n\tSAS_SATA_PM_PORT = 8,\n\tSAS_SATA_PENDING = 9,\n};\n\nenum sas_gpio_reg_type {\n\tSAS_GPIO_REG_CFG = 0,\n\tSAS_GPIO_REG_RX = 1,\n\tSAS_GPIO_REG_RX_GP = 2,\n\tSAS_GPIO_REG_TX = 3,\n\tSAS_GPIO_REG_TX_GP = 4,\n};\n\nenum sas_ha_state {\n\tSAS_HA_REGISTERED = 0,\n\tSAS_HA_DRAINING = 1,\n\tSAS_HA_ATA_EH_ACTIVE = 2,\n\tSAS_HA_FROZEN = 3,\n\tSAS_HA_RESUMING = 4,\n};\n\nenum sas_internal_abort {\n\tSAS_INTERNAL_ABORT_SINGLE = 0,\n\tSAS_INTERNAL_ABORT_DEV = 1,\n};\n\nenum sas_linkrate {\n\tSAS_LINK_RATE_UNKNOWN = 0,\n\tSAS_PHY_DISABLED = 1,\n\tSAS_PHY_RESET_PROBLEM = 2,\n\tSAS_SATA_SPINUP_HOLD = 3,\n\tSAS_SATA_PORT_SELECTOR = 4,\n\tSAS_PHY_RESET_IN_PROGRESS = 5,\n\tSAS_LINK_RATE_1_5_GBPS = 8,\n\tSAS_LINK_RATE_G1 = 8,\n\tSAS_LINK_RATE_3_0_GBPS = 9,\n\tSAS_LINK_RATE_G2 = 9,\n\tSAS_LINK_RATE_6_0_GBPS = 10,\n\tSAS_LINK_RATE_12_0_GBPS = 11,\n\tSAS_LINK_RATE_22_5_GBPS = 12,\n\tSAS_LINK_RATE_FAILED = 16,\n\tSAS_PHY_VIRTUAL = 17,\n};\n\nenum sas_oob_mode {\n\tOOB_NOT_CONNECTED = 0,\n\tSATA_OOB_MODE = 1,\n\tSAS_OOB_MODE = 2,\n};\n\nenum sas_open_rej_reason {\n\tSAS_OREJ_UNKNOWN = 0,\n\tSAS_OREJ_BAD_DEST = 1,\n\tSAS_OREJ_CONN_RATE = 2,\n\tSAS_OREJ_EPROTO = 3,\n\tSAS_OREJ_RESV_AB0 = 4,\n\tSAS_OREJ_RESV_AB1 = 5,\n\tSAS_OREJ_RESV_AB2 = 6,\n\tSAS_OREJ_RESV_AB3 = 7,\n\tSAS_OREJ_WRONG_DEST = 8,\n\tSAS_OREJ_STP_NORES = 9,\n\tSAS_OREJ_NO_DEST = 10,\n\tSAS_OREJ_PATH_BLOCKED = 11,\n\tSAS_OREJ_RSVD_CONT0 = 12,\n\tSAS_OREJ_RSVD_CONT1 = 13,\n\tSAS_OREJ_RSVD_INIT0 = 14,\n\tSAS_OREJ_RSVD_INIT1 = 15,\n\tSAS_OREJ_RSVD_STOP0 = 16,\n\tSAS_OREJ_RSVD_STOP1 = 17,\n\tSAS_OREJ_RSVD_RETRY = 18,\n};\n\nenum sas_phy_role {\n\tPHY_ROLE_NONE = 0,\n\tPHY_ROLE_TARGET = 64,\n\tPHY_ROLE_INITIATOR = 128,\n};\n\nenum sas_protocol {\n\tSAS_PROTOCOL_NONE = 0,\n\tSAS_PROTOCOL_SATA = 1,\n\tSAS_PROTOCOL_SMP = 2,\n\tSAS_PROTOCOL_STP = 4,\n\tSAS_PROTOCOL_SSP = 8,\n\tSAS_PROTOCOL_ALL = 14,\n\tSAS_PROTOCOL_STP_ALL = 5,\n\tSAS_PROTOCOL_INTERNAL_ABORT = 16,\n};\n\nenum sata_phy_ctrl_regs {\n\tPHY_CTRL_1 = 0,\n\tPHY_CTRL_1_RESET = 1,\n};\n\nenum sata_phy_regs {\n\tBLOCK0_REG_BANK = 0,\n\tBLOCK0_XGXSSTATUS = 129,\n\tBLOCK0_XGXSSTATUS_PLL_LOCK = 4096,\n\tBLOCK0_SPARE = 141,\n\tBLOCK0_SPARE_OOB_CLK_SEL_MASK = 3,\n\tBLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 1,\n\tBLOCK1_REG_BANK = 16,\n\tBLOCK1_TEST_TX = 131,\n\tBLOCK1_TEST_TX_AMP_SHIFT = 12,\n\tPLL_REG_BANK_0 = 80,\n\tPLL_REG_BANK_0_PLLCONTROL_0 = 129,\n\tPLLCONTROL_0_FREQ_DET_RESTART = 8192,\n\tPLLCONTROL_0_FREQ_MONITOR = 4096,\n\tPLLCONTROL_0_SEQ_START = 32768,\n\tPLL_CAP_CHARGE_TIME = 131,\n\tPLL_VCO_CAL_THRESH = 132,\n\tPLL_CAP_CONTROL = 133,\n\tPLL_FREQ_DET_TIME = 134,\n\tPLL_ACTRL2 = 139,\n\tPLL_ACTRL2_SELDIV_MASK = 31,\n\tPLL_ACTRL2_SELDIV_SHIFT = 9,\n\tPLL_ACTRL6 = 134,\n\tPLL1_REG_BANK = 96,\n\tPLL1_ACTRL2 = 130,\n\tPLL1_ACTRL3 = 131,\n\tPLL1_ACTRL4 = 132,\n\tPLL1_ACTRL5 = 133,\n\tPLL1_ACTRL6 = 134,\n\tPLL1_ACTRL7 = 135,\n\tPLL1_ACTRL8 = 136,\n\tTX_REG_BANK = 112,\n\tTX_ACTRL0 = 128,\n\tTX_ACTRL0_TXPOL_FLIP = 64,\n\tTX_ACTRL5 = 133,\n\tTX_ACTRL5_SSC_EN = 2048,\n\tAEQRX_REG_BANK_0 = 208,\n\tAEQ_CONTROL1 = 129,\n\tAEQ_CONTROL1_ENABLE = 4,\n\tAEQ_CONTROL1_FREEZE = 8,\n\tAEQ_FRC_EQ = 131,\n\tAEQ_FRC_EQ_FORCE = 1,\n\tAEQ_FRC_EQ_FORCE_VAL = 2,\n\tAEQ_RFZ_FRC_VAL = 256,\n\tAEQRX_REG_BANK_1 = 224,\n\tAEQRX_SLCAL0_CTRL0 = 130,\n\tAEQRX_SLCAL1_CTRL0 = 134,\n\tOOB_REG_BANK = 336,\n\tOOB1_REG_BANK = 352,\n\tOOB_CTRL1 = 128,\n\tOOB_CTRL1_BURST_MAX_MASK = 15,\n\tOOB_CTRL1_BURST_MAX_SHIFT = 12,\n\tOOB_CTRL1_BURST_MIN_MASK = 15,\n\tOOB_CTRL1_BURST_MIN_SHIFT = 8,\n\tOOB_CTRL1_WAKE_IDLE_MAX_MASK = 15,\n\tOOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,\n\tOOB_CTRL1_WAKE_IDLE_MIN_MASK = 15,\n\tOOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,\n\tOOB_CTRL2 = 129,\n\tOOB_CTRL2_SEL_ENA_SHIFT = 15,\n\tOOB_CTRL2_SEL_ENA_RC_SHIFT = 14,\n\tOOB_CTRL2_RESET_IDLE_MAX_MASK = 63,\n\tOOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,\n\tOOB_CTRL2_BURST_CNT_MASK = 3,\n\tOOB_CTRL2_BURST_CNT_SHIFT = 6,\n\tOOB_CTRL2_RESET_IDLE_MIN_MASK = 63,\n\tOOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,\n\tTXPMD_REG_BANK = 416,\n\tTXPMD_CONTROL1 = 129,\n\tTXPMD_CONTROL1_TX_SSC_EN_FRC = 1,\n\tTXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = 2,\n\tTXPMD_TX_FREQ_CTRL_CONTROL1 = 130,\n\tTXPMD_TX_FREQ_CTRL_CONTROL2 = 131,\n\tTXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 1023,\n\tTXPMD_TX_FREQ_CTRL_CONTROL3 = 132,\n\tTXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 1023,\n\tRXPMD_REG_BANK = 448,\n\tRXPMD_RX_CDR_CONTROL1 = 129,\n\tRXPMD_RX_PPM_VAL_MASK = 511,\n\tRXPMD_RXPMD_EN_FRC = 4096,\n\tRXPMD_RXPMD_EN_FRC_VAL = 8192,\n\tRXPMD_RX_CDR_CDR_PROP_BW = 130,\n\tRXPMD_G_CDR_PROP_BW_MASK = 7,\n\tRXPMD_G1_CDR_PROP_BW_SHIFT = 0,\n\tRXPMD_G2_CDR_PROP_BW_SHIFT = 3,\n\tRXPMD_G3_CDR_PROB_BW_SHIFT = 6,\n\tRXPMD_RX_CDR_CDR_ACQ_INTEG_BW = 131,\n\tRXPMD_G_CDR_ACQ_INT_BW_MASK = 7,\n\tRXPMD_G1_CDR_ACQ_INT_BW_SHIFT = 0,\n\tRXPMD_G2_CDR_ACQ_INT_BW_SHIFT = 3,\n\tRXPMD_G3_CDR_ACQ_INT_BW_SHIFT = 6,\n\tRXPMD_RX_CDR_CDR_LOCK_INTEG_BW = 132,\n\tRXPMD_G_CDR_LOCK_INT_BW_MASK = 7,\n\tRXPMD_G1_CDR_LOCK_INT_BW_SHIFT = 0,\n\tRXPMD_G2_CDR_LOCK_INT_BW_SHIFT = 3,\n\tRXPMD_G3_CDR_LOCK_INT_BW_SHIFT = 6,\n\tRXPMD_RX_FREQ_MON_CONTROL1 = 135,\n\tRXPMD_MON_CORRECT_EN = 256,\n\tRXPMD_MON_MARGIN_VAL_MASK = 255,\n};\n\nenum sata_rcar_type {\n\tRCAR_GEN1_SATA = 0,\n\tRCAR_GEN2_SATA = 1,\n\tRCAR_GEN3_SATA = 2,\n\tRCAR_R8A7790_ES1_SATA = 3,\n};\n\nenum sc7180_functions {\n\tmsm_mux_adsp_ext___8 = 0,\n\tmsm_mux_agera_pll___4 = 1,\n\tmsm_mux_aoss_cti___5 = 2,\n\tmsm_mux_atest_char___18 = 3,\n\tmsm_mux_atest_char0___10 = 4,\n\tmsm_mux_atest_char1___10 = 5,\n\tmsm_mux_atest_char2___10 = 6,\n\tmsm_mux_atest_char3___10 = 7,\n\tmsm_mux_atest_tsens___6 = 8,\n\tmsm_mux_atest_tsens2___3 = 9,\n\tmsm_mux_atest_usb1___3 = 10,\n\tmsm_mux_atest_usb2___4 = 11,\n\tmsm_mux_atest_usb10___3 = 12,\n\tmsm_mux_atest_usb11___3 = 13,\n\tmsm_mux_atest_usb12___3 = 14,\n\tmsm_mux_atest_usb13___3 = 15,\n\tmsm_mux_atest_usb20___2 = 16,\n\tmsm_mux_atest_usb21___2 = 17,\n\tmsm_mux_atest_usb22___2 = 18,\n\tmsm_mux_atest_usb23___2 = 19,\n\tmsm_mux_audio_ref___5 = 20,\n\tmsm_mux_btfm_slimbus___3 = 21,\n\tmsm_mux_cam_mclk___11 = 22,\n\tmsm_mux_cci_async___9 = 23,\n\tmsm_mux_cci_i2c___8 = 24,\n\tmsm_mux_cci_timer0___8 = 25,\n\tmsm_mux_cci_timer1___8 = 26,\n\tmsm_mux_cci_timer2___8 = 27,\n\tmsm_mux_cci_timer3___7 = 28,\n\tmsm_mux_cci_timer4___6 = 29,\n\tmsm_mux_cri_trng___12 = 30,\n\tmsm_mux_dbg_out___15 = 31,\n\tmsm_mux_ddr_bist___9 = 32,\n\tmsm_mux_ddr_pxi0___7 = 33,\n\tmsm_mux_ddr_pxi1___7 = 34,\n\tmsm_mux_ddr_pxi2___6 = 35,\n\tmsm_mux_ddr_pxi3___6 = 36,\n\tmsm_mux_dp_hot___3 = 37,\n\tmsm_mux_edp_lcd___4 = 38,\n\tmsm_mux_gcc_gp1___7 = 39,\n\tmsm_mux_gcc_gp2___7 = 40,\n\tmsm_mux_gcc_gp3___7 = 41,\n\tmsm_mux_gpio___21 = 42,\n\tmsm_mux_gp_pdm0___3 = 43,\n\tmsm_mux_gp_pdm1___3 = 44,\n\tmsm_mux_gp_pdm2___3 = 45,\n\tmsm_mux_gps_tx___3 = 46,\n\tmsm_mux_jitter_bist___8 = 47,\n\tmsm_mux_ldo_en___8 = 48,\n\tmsm_mux_ldo_update___8 = 49,\n\tmsm_mux_lpass_ext = 50,\n\tmsm_mux_mdp_vsync___13 = 51,\n\tmsm_mux_mdp_vsync0___2 = 52,\n\tmsm_mux_mdp_vsync1___2 = 53,\n\tmsm_mux_mdp_vsync2___2 = 54,\n\tmsm_mux_mdp_vsync3___2 = 55,\n\tmsm_mux_mi2s_1___2 = 56,\n\tmsm_mux_mi2s_0 = 57,\n\tmsm_mux_mi2s_2 = 58,\n\tmsm_mux_mss_lte___7 = 59,\n\tmsm_mux_m_voc___9 = 60,\n\tmsm_mux_pa_indicator___7 = 61,\n\tmsm_mux_phase_flag___9 = 62,\n\tmsm_mux_PLL_BIST = 63,\n\tmsm_mux_pll_bypassnl___5 = 64,\n\tmsm_mux_pll_reset___4 = 65,\n\tmsm_mux_prng_rosc___12 = 66,\n\tmsm_mux_qdss___2 = 67,\n\tmsm_mux_qdss_cti___9 = 68,\n\tmsm_mux_qlink_enable___3 = 69,\n\tmsm_mux_qlink_request___3 = 70,\n\tmsm_mux_qspi_clk___8 = 71,\n\tmsm_mux_qspi_cs___8 = 72,\n\tmsm_mux_qspi_data___5 = 73,\n\tmsm_mux_qup00___2 = 74,\n\tmsm_mux_qup01___2 = 75,\n\tmsm_mux_qup02_i2c = 76,\n\tmsm_mux_qup02_uart = 77,\n\tmsm_mux_qup03___2 = 78,\n\tmsm_mux_qup04_i2c = 79,\n\tmsm_mux_qup04_uart = 80,\n\tmsm_mux_qup05___2 = 81,\n\tmsm_mux_qup10___2 = 82,\n\tmsm_mux_qup11_i2c = 83,\n\tmsm_mux_qup11_uart = 84,\n\tmsm_mux_qup12___2 = 85,\n\tmsm_mux_qup13_i2c = 86,\n\tmsm_mux_qup13_uart = 87,\n\tmsm_mux_qup14___2 = 88,\n\tmsm_mux_qup15___2 = 89,\n\tmsm_mux_sdc1_tb___2 = 90,\n\tmsm_mux_sdc2_tb___2 = 91,\n\tmsm_mux_sd_write___10 = 92,\n\tmsm_mux_sp_cmu___3 = 93,\n\tmsm_mux_tgu_ch0___6 = 94,\n\tmsm_mux_tgu_ch1___6 = 95,\n\tmsm_mux_tgu_ch2___5 = 96,\n\tmsm_mux_tgu_ch3___5 = 97,\n\tmsm_mux_tsense_pwm1___8 = 98,\n\tmsm_mux_tsense_pwm2___8 = 99,\n\tmsm_mux_uim1___5 = 100,\n\tmsm_mux_uim2___5 = 101,\n\tmsm_mux_uim_batt___6 = 102,\n\tmsm_mux_usb_phy___5 = 103,\n\tmsm_mux_vfr_1___8 = 104,\n\tmsm_mux__V_GPIO = 105,\n\tmsm_mux__V_PPS_IN = 106,\n\tmsm_mux__V_PPS_OUT = 107,\n\tmsm_mux_vsense_trigger___5 = 108,\n\tmsm_mux_wlan1_adc0___4 = 109,\n\tmsm_mux_wlan1_adc1___4 = 110,\n\tmsm_mux_wlan2_adc0___3 = 111,\n\tmsm_mux_wlan2_adc1___3 = 112,\n\tmsm_mux_____16 = 113,\n};\n\nenum sc7280_functions {\n\tmsm_mux_atest_char___19 = 0,\n\tmsm_mux_atest_char0___11 = 1,\n\tmsm_mux_atest_char1___11 = 2,\n\tmsm_mux_atest_char2___11 = 3,\n\tmsm_mux_atest_char3___11 = 4,\n\tmsm_mux_atest_usb0 = 5,\n\tmsm_mux_atest_usb00 = 6,\n\tmsm_mux_atest_usb01 = 7,\n\tmsm_mux_atest_usb02 = 8,\n\tmsm_mux_atest_usb03 = 9,\n\tmsm_mux_atest_usb1___4 = 10,\n\tmsm_mux_atest_usb10___4 = 11,\n\tmsm_mux_atest_usb11___4 = 12,\n\tmsm_mux_atest_usb12___4 = 13,\n\tmsm_mux_atest_usb13___4 = 14,\n\tmsm_mux_audio_ref___6 = 15,\n\tmsm_mux_cam_mclk___12 = 16,\n\tmsm_mux_cci_async___10 = 17,\n\tmsm_mux_cci_i2c___9 = 18,\n\tmsm_mux_cci_timer0___9 = 19,\n\tmsm_mux_cci_timer1___9 = 20,\n\tmsm_mux_cci_timer2___9 = 21,\n\tmsm_mux_cci_timer3___8 = 22,\n\tmsm_mux_cci_timer4___7 = 23,\n\tmsm_mux_cmu_rng0 = 24,\n\tmsm_mux_cmu_rng1 = 25,\n\tmsm_mux_cmu_rng2 = 26,\n\tmsm_mux_cmu_rng3 = 27,\n\tmsm_mux_coex_uart1 = 28,\n\tmsm_mux_cri_trng___13 = 29,\n\tmsm_mux_cri_trng0___13 = 30,\n\tmsm_mux_cri_trng1___13 = 31,\n\tmsm_mux_dbg_out___16 = 32,\n\tmsm_mux_ddr_bist___10 = 33,\n\tmsm_mux_ddr_pxi0___8 = 34,\n\tmsm_mux_ddr_pxi1___8 = 35,\n\tmsm_mux_dp_hot___4 = 36,\n\tmsm_mux_dp_lcd = 37,\n\tmsm_mux_edp_hot___4 = 38,\n\tmsm_mux_edp_lcd___5 = 39,\n\tmsm_mux_egpio___6 = 40,\n\tmsm_mux_gcc_gp1___8 = 41,\n\tmsm_mux_gcc_gp2___8 = 42,\n\tmsm_mux_gcc_gp3___8 = 43,\n\tmsm_mux_gpio___22 = 44,\n\tmsm_mux_host2wlan_sol___2 = 45,\n\tmsm_mux_ibi_i3c___5 = 46,\n\tmsm_mux_jitter_bist___9 = 47,\n\tmsm_mux_lpass_slimbus___5 = 48,\n\tmsm_mux_mdp_vsync___14 = 49,\n\tmsm_mux_mdp_vsync0___3 = 50,\n\tmsm_mux_mdp_vsync1___3 = 51,\n\tmsm_mux_mdp_vsync2___3 = 52,\n\tmsm_mux_mdp_vsync3___3 = 53,\n\tmsm_mux_mdp_vsync4 = 54,\n\tmsm_mux_mdp_vsync5 = 55,\n\tmsm_mux_mi2s0_data0 = 56,\n\tmsm_mux_mi2s0_data1 = 57,\n\tmsm_mux_mi2s0_sck = 58,\n\tmsm_mux_mi2s0_ws = 59,\n\tmsm_mux_mi2s1_data0___3 = 60,\n\tmsm_mux_mi2s1_data1___3 = 61,\n\tmsm_mux_mi2s1_sck___3 = 62,\n\tmsm_mux_mi2s1_ws___3 = 63,\n\tmsm_mux_mi2s2_data0___3 = 64,\n\tmsm_mux_mi2s2_data1___3 = 65,\n\tmsm_mux_mi2s2_sck___3 = 66,\n\tmsm_mux_mi2s2_ws___3 = 67,\n\tmsm_mux_mss_grfc0 = 68,\n\tmsm_mux_mss_grfc1 = 69,\n\tmsm_mux_mss_grfc10 = 70,\n\tmsm_mux_mss_grfc11 = 71,\n\tmsm_mux_mss_grfc12 = 72,\n\tmsm_mux_mss_grfc2 = 73,\n\tmsm_mux_mss_grfc3 = 74,\n\tmsm_mux_mss_grfc4 = 75,\n\tmsm_mux_mss_grfc5 = 76,\n\tmsm_mux_mss_grfc6 = 77,\n\tmsm_mux_mss_grfc7 = 78,\n\tmsm_mux_mss_grfc8 = 79,\n\tmsm_mux_mss_grfc9 = 80,\n\tmsm_mux_nav_gpio0___3 = 81,\n\tmsm_mux_nav_gpio1___3 = 82,\n\tmsm_mux_nav_gpio2___3 = 83,\n\tmsm_mux_pa_indicator___8 = 84,\n\tmsm_mux_pcie0_clkreqn = 85,\n\tmsm_mux_pcie1_clkreqn = 86,\n\tmsm_mux_phase_flag___10 = 87,\n\tmsm_mux_pll_bist___7 = 88,\n\tmsm_mux_pll_bypassnl___6 = 89,\n\tmsm_mux_pll_clk___4 = 90,\n\tmsm_mux_pll_reset___5 = 91,\n\tmsm_mux_pri_mi2s___7 = 92,\n\tmsm_mux_prng_rosc___13 = 93,\n\tmsm_mux_qdss___3 = 94,\n\tmsm_mux_qdss_cti___10 = 95,\n\tmsm_mux_qlink0_enable___3 = 96,\n\tmsm_mux_qlink0_request___3 = 97,\n\tmsm_mux_qlink0_wmss___3 = 98,\n\tmsm_mux_qlink1_enable___3 = 99,\n\tmsm_mux_qlink1_request___3 = 100,\n\tmsm_mux_qlink1_wmss___3 = 101,\n\tmsm_mux_qspi_clk___9 = 102,\n\tmsm_mux_qspi_cs___9 = 103,\n\tmsm_mux_qspi_data___6 = 104,\n\tmsm_mux_qup00___3 = 105,\n\tmsm_mux_qup01___3 = 106,\n\tmsm_mux_qup02___2 = 107,\n\tmsm_mux_qup03___3 = 108,\n\tmsm_mux_qup04___2 = 109,\n\tmsm_mux_qup05___3 = 110,\n\tmsm_mux_qup06___2 = 111,\n\tmsm_mux_qup07___2 = 112,\n\tmsm_mux_qup10___3 = 113,\n\tmsm_mux_qup11___2 = 114,\n\tmsm_mux_qup12___3 = 115,\n\tmsm_mux_qup13___2 = 116,\n\tmsm_mux_qup14___3 = 117,\n\tmsm_mux_qup15___3 = 118,\n\tmsm_mux_qup16___2 = 119,\n\tmsm_mux_qup17___2 = 120,\n\tmsm_mux_sd_write___11 = 121,\n\tmsm_mux_sdc40___4 = 122,\n\tmsm_mux_sdc41___4 = 123,\n\tmsm_mux_sdc42___4 = 124,\n\tmsm_mux_sdc43___4 = 125,\n\tmsm_mux_sdc4_clk___4 = 126,\n\tmsm_mux_sdc4_cmd___4 = 127,\n\tmsm_mux_sec_mi2s___7 = 128,\n\tmsm_mux_tb_trig___4 = 129,\n\tmsm_mux_tgu_ch0___7 = 130,\n\tmsm_mux_tgu_ch1___7 = 131,\n\tmsm_mux_tsense_pwm1___9 = 132,\n\tmsm_mux_tsense_pwm2___9 = 133,\n\tmsm_mux_uim0_clk___3 = 134,\n\tmsm_mux_uim0_data___3 = 135,\n\tmsm_mux_uim0_present___3 = 136,\n\tmsm_mux_uim0_reset___3 = 137,\n\tmsm_mux_uim1_clk___6 = 138,\n\tmsm_mux_uim1_data___6 = 139,\n\tmsm_mux_uim1_present___6 = 140,\n\tmsm_mux_uim1_reset___6 = 141,\n\tmsm_mux_usb2phy_ac___4 = 142,\n\tmsm_mux_usb_phy___6 = 143,\n\tmsm_mux_vfr_0___4 = 144,\n\tmsm_mux_vfr_1___9 = 145,\n\tmsm_mux_vsense_trigger___6 = 146,\n\tmsm_mux_____17 = 147,\n};\n\nenum sc8180x_functions {\n\tmsm_mux_adsp_ext___9 = 0,\n\tmsm_mux_agera_pll___5 = 1,\n\tmsm_mux_aoss_cti___6 = 2,\n\tmsm_mux_atest_char___20 = 3,\n\tmsm_mux_atest_tsens___7 = 4,\n\tmsm_mux_atest_tsens2___4 = 5,\n\tmsm_mux_atest_usb0___2 = 6,\n\tmsm_mux_atest_usb1___5 = 7,\n\tmsm_mux_atest_usb2___5 = 8,\n\tmsm_mux_atest_usb3 = 9,\n\tmsm_mux_atest_usb4 = 10,\n\tmsm_mux_audio_ref___7 = 11,\n\tmsm_mux_btfm_slimbus___4 = 12,\n\tmsm_mux_cam_mclk___13 = 13,\n\tmsm_mux_cci_async___11 = 14,\n\tmsm_mux_cci_i2c___10 = 15,\n\tmsm_mux_cci_timer0___10 = 16,\n\tmsm_mux_cci_timer1___10 = 17,\n\tmsm_mux_cci_timer2___10 = 18,\n\tmsm_mux_cci_timer3___9 = 19,\n\tmsm_mux_cci_timer4___8 = 20,\n\tmsm_mux_cci_timer5___2 = 21,\n\tmsm_mux_cci_timer6___2 = 22,\n\tmsm_mux_cci_timer7___2 = 23,\n\tmsm_mux_cci_timer8___2 = 24,\n\tmsm_mux_cci_timer9___2 = 25,\n\tmsm_mux_cri_trng___14 = 26,\n\tmsm_mux_dbg_out___17 = 27,\n\tmsm_mux_ddr_bist___11 = 28,\n\tmsm_mux_ddr_pxi___2 = 29,\n\tmsm_mux_debug_hot = 30,\n\tmsm_mux_dp_hot___5 = 31,\n\tmsm_mux_edp_hot___5 = 32,\n\tmsm_mux_edp_lcd___6 = 33,\n\tmsm_mux_emac_phy = 34,\n\tmsm_mux_emac_pps = 35,\n\tmsm_mux_gcc_gp1___9 = 36,\n\tmsm_mux_gcc_gp2___9 = 37,\n\tmsm_mux_gcc_gp3___9 = 38,\n\tmsm_mux_gcc_gp4___3 = 39,\n\tmsm_mux_gcc_gp5___3 = 40,\n\tmsm_mux_gpio___23 = 41,\n\tmsm_mux_gps = 42,\n\tmsm_mux_grfc = 43,\n\tmsm_mux_hs1_mi2s___4 = 44,\n\tmsm_mux_hs2_mi2s___3 = 45,\n\tmsm_mux_hs3_mi2s = 46,\n\tmsm_mux_jitter_bist___10 = 47,\n\tmsm_mux_lpass_slimbus___6 = 48,\n\tmsm_mux_m_voc___10 = 49,\n\tmsm_mux_mdp_vsync___15 = 50,\n\tmsm_mux_mdp_vsync0___4 = 51,\n\tmsm_mux_mdp_vsync1___4 = 52,\n\tmsm_mux_mdp_vsync2___4 = 53,\n\tmsm_mux_mdp_vsync3___4 = 54,\n\tmsm_mux_mdp_vsync4___2 = 55,\n\tmsm_mux_mdp_vsync5___2 = 56,\n\tmsm_mux_mss_lte___8 = 57,\n\tmsm_mux_nav_pps___6 = 58,\n\tmsm_mux_pa_indicator___9 = 59,\n\tmsm_mux_pci_e0___4 = 60,\n\tmsm_mux_pci_e1___3 = 61,\n\tmsm_mux_pci_e2___2 = 62,\n\tmsm_mux_pci_e3 = 63,\n\tmsm_mux_phase_flag___11 = 64,\n\tmsm_mux_pll_bist___8 = 65,\n\tmsm_mux_pll_bypassnl___7 = 66,\n\tmsm_mux_pll_reset___6 = 67,\n\tmsm_mux_pri_mi2s___8 = 68,\n\tmsm_mux_pri_mi2s_ws___4 = 69,\n\tmsm_mux_prng_rosc___14 = 70,\n\tmsm_mux_qdss_cti___11 = 71,\n\tmsm_mux_qdss_gpio___7 = 72,\n\tmsm_mux_qlink = 73,\n\tmsm_mux_qspi0___5 = 74,\n\tmsm_mux_qspi0_clk = 75,\n\tmsm_mux_qspi0_cs = 76,\n\tmsm_mux_qspi1___4 = 77,\n\tmsm_mux_qspi1_clk = 78,\n\tmsm_mux_qspi1_cs = 79,\n\tmsm_mux_qua_mi2s___4 = 80,\n\tmsm_mux_qup0___3 = 81,\n\tmsm_mux_qup1___3 = 82,\n\tmsm_mux_qup2___2 = 83,\n\tmsm_mux_qup3___2 = 84,\n\tmsm_mux_qup4___2 = 85,\n\tmsm_mux_qup5___2 = 86,\n\tmsm_mux_qup6 = 87,\n\tmsm_mux_qup7 = 88,\n\tmsm_mux_qup8 = 89,\n\tmsm_mux_qup9 = 90,\n\tmsm_mux_qup10___4 = 91,\n\tmsm_mux_qup11___3 = 92,\n\tmsm_mux_qup12___4 = 93,\n\tmsm_mux_qup13___3 = 94,\n\tmsm_mux_qup14___4 = 95,\n\tmsm_mux_qup15___4 = 96,\n\tmsm_mux_qup16___3 = 97,\n\tmsm_mux_qup17___3 = 98,\n\tmsm_mux_qup18 = 99,\n\tmsm_mux_qup19 = 100,\n\tmsm_mux_qup_l4 = 101,\n\tmsm_mux_qup_l5 = 102,\n\tmsm_mux_qup_l6 = 103,\n\tmsm_mux_rgmii___2 = 104,\n\tmsm_mux_sd_write___12 = 105,\n\tmsm_mux_sdc4___2 = 106,\n\tmsm_mux_sdc4_clk___5 = 107,\n\tmsm_mux_sdc4_cmd___5 = 108,\n\tmsm_mux_sec_mi2s___8 = 109,\n\tmsm_mux_sp_cmu___4 = 110,\n\tmsm_mux_spkr_i2s___4 = 111,\n\tmsm_mux_ter_mi2s___5 = 112,\n\tmsm_mux_tgu = 113,\n\tmsm_mux_tsense_pwm1___10 = 114,\n\tmsm_mux_tsense_pwm2___10 = 115,\n\tmsm_mux_tsif1___3 = 116,\n\tmsm_mux_tsif2___2 = 117,\n\tmsm_mux_uim1___6 = 118,\n\tmsm_mux_uim2___6 = 119,\n\tmsm_mux_uim_batt___7 = 120,\n\tmsm_mux_usb0_phy = 121,\n\tmsm_mux_usb1_phy = 122,\n\tmsm_mux_usb2phy_ac___5 = 123,\n\tmsm_mux_vfr_1___10 = 124,\n\tmsm_mux_vsense_trigger___7 = 125,\n\tmsm_mux_wlan1_adc = 126,\n\tmsm_mux_wlan2_adc = 127,\n\tmsm_mux_wmss_reset = 128,\n\tmsm_mux_____18 = 129,\n};\n\nenum sc8280xp_functions {\n\tmsm_mux_atest_char___21 = 0,\n\tmsm_mux_atest_usb___5 = 1,\n\tmsm_mux_audio_ref___8 = 2,\n\tmsm_mux_cam_mclk___14 = 3,\n\tmsm_mux_cci_async___12 = 4,\n\tmsm_mux_cci_i2c___11 = 5,\n\tmsm_mux_cci_timer0___11 = 6,\n\tmsm_mux_cci_timer1___11 = 7,\n\tmsm_mux_cci_timer2___11 = 8,\n\tmsm_mux_cci_timer3___10 = 9,\n\tmsm_mux_cci_timer4___9 = 10,\n\tmsm_mux_cci_timer5___3 = 11,\n\tmsm_mux_cci_timer6___3 = 12,\n\tmsm_mux_cci_timer7___3 = 13,\n\tmsm_mux_cci_timer8___3 = 14,\n\tmsm_mux_cci_timer9___3 = 15,\n\tmsm_mux_cmu_rng___3 = 16,\n\tmsm_mux_cri_trng___15 = 17,\n\tmsm_mux_cri_trng0___14 = 18,\n\tmsm_mux_cri_trng1___14 = 19,\n\tmsm_mux_dbg_out___18 = 20,\n\tmsm_mux_ddr_bist___12 = 21,\n\tmsm_mux_ddr_pxi0___9 = 22,\n\tmsm_mux_ddr_pxi1___9 = 23,\n\tmsm_mux_ddr_pxi2___7 = 24,\n\tmsm_mux_ddr_pxi3___7 = 25,\n\tmsm_mux_ddr_pxi4___3 = 26,\n\tmsm_mux_ddr_pxi5___3 = 27,\n\tmsm_mux_ddr_pxi6___2 = 28,\n\tmsm_mux_ddr_pxi7___2 = 29,\n\tmsm_mux_dp2_hot = 30,\n\tmsm_mux_dp3_hot = 31,\n\tmsm_mux_edp0_lcd___3 = 32,\n\tmsm_mux_edp1_lcd___3 = 33,\n\tmsm_mux_edp2_lcd___2 = 34,\n\tmsm_mux_edp3_lcd___2 = 35,\n\tmsm_mux_edp_hot___6 = 36,\n\tmsm_mux_egpio___7 = 37,\n\tmsm_mux_emac0_dll = 38,\n\tmsm_mux_emac0_mcg0___3 = 39,\n\tmsm_mux_emac0_mcg1___3 = 40,\n\tmsm_mux_emac0_mcg2___3 = 41,\n\tmsm_mux_emac0_mcg3___3 = 42,\n\tmsm_mux_emac0_phy = 43,\n\tmsm_mux_emac0_ptp = 44,\n\tmsm_mux_emac1_dll0 = 45,\n\tmsm_mux_emac1_dll1 = 46,\n\tmsm_mux_emac1_mcg0___2 = 47,\n\tmsm_mux_emac1_mcg1___2 = 48,\n\tmsm_mux_emac1_mcg2___2 = 49,\n\tmsm_mux_emac1_mcg3___2 = 50,\n\tmsm_mux_emac1_phy = 51,\n\tmsm_mux_emac1_ptp = 52,\n\tmsm_mux_gcc_gp1___10 = 53,\n\tmsm_mux_gcc_gp2___10 = 54,\n\tmsm_mux_gcc_gp3___10 = 55,\n\tmsm_mux_gcc_gp4___4 = 56,\n\tmsm_mux_gcc_gp5___4 = 57,\n\tmsm_mux_gpio___24 = 58,\n\tmsm_mux_hs1_mi2s___5 = 59,\n\tmsm_mux_hs2_mi2s___4 = 60,\n\tmsm_mux_hs3_mi2s___2 = 61,\n\tmsm_mux_ibi_i3c___6 = 62,\n\tmsm_mux_jitter_bist___11 = 63,\n\tmsm_mux_lpass_slimbus___7 = 64,\n\tmsm_mux_mdp0_vsync0___3 = 65,\n\tmsm_mux_mdp0_vsync1___3 = 66,\n\tmsm_mux_mdp0_vsync2___2 = 67,\n\tmsm_mux_mdp0_vsync3___3 = 68,\n\tmsm_mux_mdp0_vsync4___2 = 69,\n\tmsm_mux_mdp0_vsync5___2 = 70,\n\tmsm_mux_mdp0_vsync6___3 = 71,\n\tmsm_mux_mdp0_vsync7___3 = 72,\n\tmsm_mux_mdp0_vsync8___2 = 73,\n\tmsm_mux_mdp1_vsync0___2 = 74,\n\tmsm_mux_mdp1_vsync1___2 = 75,\n\tmsm_mux_mdp1_vsync2___2 = 76,\n\tmsm_mux_mdp1_vsync3___2 = 77,\n\tmsm_mux_mdp1_vsync4___2 = 78,\n\tmsm_mux_mdp1_vsync5___2 = 79,\n\tmsm_mux_mdp1_vsync6___2 = 80,\n\tmsm_mux_mdp1_vsync7___2 = 81,\n\tmsm_mux_mdp1_vsync8___2 = 82,\n\tmsm_mux_mdp_vsync___16 = 83,\n\tmsm_mux_mi2s0_data0___2 = 84,\n\tmsm_mux_mi2s0_data1___2 = 85,\n\tmsm_mux_mi2s0_sck___2 = 86,\n\tmsm_mux_mi2s0_ws___2 = 87,\n\tmsm_mux_mi2s1_data0___4 = 88,\n\tmsm_mux_mi2s1_data1___4 = 89,\n\tmsm_mux_mi2s1_sck___4 = 90,\n\tmsm_mux_mi2s1_ws___4 = 91,\n\tmsm_mux_mi2s2_data0___4 = 92,\n\tmsm_mux_mi2s2_data1___4 = 93,\n\tmsm_mux_mi2s2_sck___4 = 94,\n\tmsm_mux_mi2s2_ws___4 = 95,\n\tmsm_mux_mi2s_mclk1___3 = 96,\n\tmsm_mux_mi2s_mclk2 = 97,\n\tmsm_mux_pcie2a_clkreq = 98,\n\tmsm_mux_pcie2b_clkreq = 99,\n\tmsm_mux_pcie3a_clkreq = 100,\n\tmsm_mux_pcie3b_clkreq = 101,\n\tmsm_mux_pcie4_clkreq = 102,\n\tmsm_mux_phase_flag___12 = 103,\n\tmsm_mux_pll_bist___9 = 104,\n\tmsm_mux_pll_clk___5 = 105,\n\tmsm_mux_prng_rosc0___8 = 106,\n\tmsm_mux_prng_rosc1___8 = 107,\n\tmsm_mux_prng_rosc2___8 = 108,\n\tmsm_mux_prng_rosc3___8 = 109,\n\tmsm_mux_qdss_cti___12 = 110,\n\tmsm_mux_qdss_gpio___8 = 111,\n\tmsm_mux_qspi___2 = 112,\n\tmsm_mux_qspi_clk___10 = 113,\n\tmsm_mux_qspi_cs___10 = 114,\n\tmsm_mux_qup0___4 = 115,\n\tmsm_mux_qup1___4 = 116,\n\tmsm_mux_qup10___5 = 117,\n\tmsm_mux_qup11___4 = 118,\n\tmsm_mux_qup12___5 = 119,\n\tmsm_mux_qup13___4 = 120,\n\tmsm_mux_qup14___5 = 121,\n\tmsm_mux_qup15___5 = 122,\n\tmsm_mux_qup16___4 = 123,\n\tmsm_mux_qup17___4 = 124,\n\tmsm_mux_qup18___2 = 125,\n\tmsm_mux_qup19___2 = 126,\n\tmsm_mux_qup2___3 = 127,\n\tmsm_mux_qup20___2 = 128,\n\tmsm_mux_qup21___2 = 129,\n\tmsm_mux_qup22___2 = 130,\n\tmsm_mux_qup23 = 131,\n\tmsm_mux_qup3___3 = 132,\n\tmsm_mux_qup4___3 = 133,\n\tmsm_mux_qup5___3 = 134,\n\tmsm_mux_qup6___2 = 135,\n\tmsm_mux_qup7___2 = 136,\n\tmsm_mux_qup8___2 = 137,\n\tmsm_mux_qup9___2 = 138,\n\tmsm_mux_rgmii_0 = 139,\n\tmsm_mux_rgmii_1 = 140,\n\tmsm_mux_sd_write___13 = 141,\n\tmsm_mux_sdc40___5 = 142,\n\tmsm_mux_sdc42___5 = 143,\n\tmsm_mux_sdc43___5 = 144,\n\tmsm_mux_sdc4_clk___6 = 145,\n\tmsm_mux_sdc4_cmd___6 = 146,\n\tmsm_mux_tb_trig___5 = 147,\n\tmsm_mux_tgu___2 = 148,\n\tmsm_mux_tsense_pwm1___11 = 149,\n\tmsm_mux_tsense_pwm2___11 = 150,\n\tmsm_mux_tsense_pwm3___4 = 151,\n\tmsm_mux_tsense_pwm4___4 = 152,\n\tmsm_mux_usb0_dp = 153,\n\tmsm_mux_usb0_phy___2 = 154,\n\tmsm_mux_usb0_sbrx = 155,\n\tmsm_mux_usb0_sbtx = 156,\n\tmsm_mux_usb0_usb4 = 157,\n\tmsm_mux_usb1_dp = 158,\n\tmsm_mux_usb1_phy___2 = 159,\n\tmsm_mux_usb1_sbrx = 160,\n\tmsm_mux_usb1_sbtx = 161,\n\tmsm_mux_usb1_usb4 = 162,\n\tmsm_mux_usb2phy_ac___6 = 163,\n\tmsm_mux_vsense_trigger___8 = 164,\n\tmsm_mux_____19 = 165,\n};\n\nenum scale_freq_source {\n\tSCALE_FREQ_SOURCE_CPUFREQ = 0,\n\tSCALE_FREQ_SOURCE_ARCH = 1,\n\tSCALE_FREQ_SOURCE_CPPC = 2,\n\tSCALE_FREQ_SOURCE_VIRT = 3,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum scan_result {\n\tSCAN_FAIL = 0,\n\tSCAN_SUCCEED = 1,\n\tSCAN_NO_PTE_TABLE = 2,\n\tSCAN_PMD_MAPPED = 3,\n\tSCAN_EXCEED_NONE_PTE = 4,\n\tSCAN_EXCEED_SWAP_PTE = 5,\n\tSCAN_EXCEED_SHARED_PTE = 6,\n\tSCAN_PTE_NON_PRESENT = 7,\n\tSCAN_PTE_UFFD_WP = 8,\n\tSCAN_PTE_MAPPED_HUGEPAGE = 9,\n\tSCAN_LACK_REFERENCED_PAGE = 10,\n\tSCAN_PAGE_NULL = 11,\n\tSCAN_SCAN_ABORT = 12,\n\tSCAN_PAGE_COUNT = 13,\n\tSCAN_PAGE_LRU = 14,\n\tSCAN_PAGE_LOCK = 15,\n\tSCAN_PAGE_ANON = 16,\n\tSCAN_PAGE_COMPOUND = 17,\n\tSCAN_ANY_PROCESS = 18,\n\tSCAN_VMA_NULL = 19,\n\tSCAN_VMA_CHECK = 20,\n\tSCAN_ADDRESS_RANGE = 21,\n\tSCAN_DEL_PAGE_LRU = 22,\n\tSCAN_ALLOC_HUGE_PAGE_FAIL = 23,\n\tSCAN_CGROUP_CHARGE_FAIL = 24,\n\tSCAN_TRUNCATED = 25,\n\tSCAN_PAGE_HAS_PRIVATE = 26,\n\tSCAN_STORE_FAILED = 27,\n\tSCAN_COPY_MC = 28,\n\tSCAN_PAGE_FILLED = 29,\n\tSCAN_PAGE_DIRTY_OR_WRITEBACK = 30,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum scmi_bad_msg {\n\tMSG_UNEXPECTED = -1,\n\tMSG_INVALID = -2,\n\tMSG_UNKNOWN = -3,\n\tMSG_NOMEM = -4,\n\tMSG_MBOX_SPURIOUS = -5,\n};\n\nenum scmi_base_protocol_cmd {\n\tBASE_DISCOVER_VENDOR = 3,\n\tBASE_DISCOVER_SUB_VENDOR = 4,\n\tBASE_DISCOVER_IMPLEMENT_VERSION = 5,\n\tBASE_DISCOVER_LIST_PROTOCOLS = 6,\n\tBASE_DISCOVER_AGENT = 7,\n\tBASE_NOTIFY_ERRORS = 8,\n\tBASE_SET_DEVICE_PERMISSIONS = 9,\n\tBASE_SET_PROTOCOL_PERMISSIONS = 10,\n\tBASE_RESET_AGENT_CONFIGURATION = 11,\n};\n\nenum scmi_clk_feats {\n\tSCMI_CLK_ATOMIC_SUPPORTED = 0,\n\tSCMI_CLK_STATE_CTRL_SUPPORTED = 1,\n\tSCMI_CLK_RATE_CTRL_SUPPORTED = 2,\n\tSCMI_CLK_PARENT_CTRL_SUPPORTED = 3,\n\tSCMI_CLK_DUTY_CYCLE_SUPPORTED = 4,\n\tSCMI_CLK_FEATS_COUNT = 5,\n};\n\nenum scmi_clock_oem_config {\n\tSCMI_CLOCK_CFG_DUTY_CYCLE = 1,\n\tSCMI_CLOCK_CFG_PHASE = 2,\n\tSCMI_CLOCK_CFG_OEM_START = 128,\n\tSCMI_CLOCK_CFG_OEM_END = 255,\n};\n\nenum scmi_clock_protocol_cmd {\n\tCLOCK_ATTRIBUTES = 3,\n\tCLOCK_DESCRIBE_RATES = 4,\n\tCLOCK_RATE_SET = 5,\n\tCLOCK_RATE_GET = 6,\n\tCLOCK_CONFIG_SET = 7,\n\tCLOCK_NAME_GET = 8,\n\tCLOCK_RATE_NOTIFY = 9,\n\tCLOCK_RATE_CHANGE_REQUESTED_NOTIFY = 10,\n\tCLOCK_CONFIG_GET = 11,\n\tCLOCK_POSSIBLE_PARENTS_GET = 12,\n\tCLOCK_PARENT_SET = 13,\n\tCLOCK_PARENT_GET = 14,\n\tCLOCK_GET_PERMISSIONS = 15,\n};\n\nenum scmi_common_cmd {\n\tPROTOCOL_VERSION = 0,\n\tPROTOCOL_ATTRIBUTES = 1,\n\tPROTOCOL_MESSAGE_ATTRIBUTES = 2,\n\tNEGOTIATE_PROTOCOL_VERSION = 16,\n};\n\nenum scmi_error_codes {\n\tSCMI_SUCCESS = 0,\n\tSCMI_ERR_SUPPORT = -1,\n\tSCMI_ERR_PARAMS = -2,\n\tSCMI_ERR_ACCESS = -3,\n\tSCMI_ERR_ENTRY = -4,\n\tSCMI_ERR_RANGE = -5,\n\tSCMI_ERR_BUSY = -6,\n\tSCMI_ERR_COMMS = -7,\n\tSCMI_ERR_GENERIC = -8,\n\tSCMI_ERR_HARDWARE = -9,\n\tSCMI_ERR_PROTOCOL = -10,\n};\n\nenum scmi_imx_bbm_protocol_cmd {\n\tIMX_BBM_GPR_SET = 3,\n\tIMX_BBM_GPR_GET = 4,\n\tIMX_BBM_RTC_ATTRIBUTES = 5,\n\tIMX_BBM_RTC_TIME_SET = 6,\n\tIMX_BBM_RTC_TIME_GET = 7,\n\tIMX_BBM_RTC_ALARM_SET = 8,\n\tIMX_BBM_BUTTON_GET = 9,\n\tIMX_BBM_RTC_NOTIFY = 10,\n\tIMX_BBM_BUTTON_NOTIFY = 11,\n};\n\nenum scmi_imx_cpu_protocol_cmd {\n\tSCMI_IMX_CPU_ATTRIBUTES = 3,\n\tSCMI_IMX_CPU_START = 4,\n\tSCMI_IMX_CPU_STOP = 5,\n\tSCMI_IMX_CPU_RESET_VECTOR_SET = 6,\n\tSCMI_IMX_CPU_INFO_GET = 12,\n};\n\nenum scmi_imx_lmm_op {\n\tSCMI_IMX_LMM_BOOT = 0,\n\tSCMI_IMX_LMM_POWER_ON = 1,\n\tSCMI_IMX_LMM_SHUTDOWN = 2,\n};\n\nenum scmi_imx_lmm_protocol_cmd {\n\tSCMI_IMX_LMM_ATTRIBUTES = 3,\n\tSCMI_IMX_LMM_BOOT___2 = 4,\n\tSCMI_IMX_LMM_RESET = 5,\n\tSCMI_IMX_LMM_SHUTDOWN___2 = 6,\n\tSCMI_IMX_LMM_WAKE = 7,\n\tSCMI_IMX_LMM_SUSPEND = 8,\n\tSCMI_IMX_LMM_NOTIFY = 9,\n\tSCMI_IMX_LMM_RESET_REASON = 10,\n\tSCMI_IMX_LMM_POWER_ON___2 = 11,\n\tSCMI_IMX_LMM_RESET_VECTOR_SET = 12,\n};\n\nenum scmi_imx_lmm_state {\n\tLMM_STATE_LM_OFF = 0,\n\tLMM_STATE_LM_ON = 1,\n\tLMM_STATE_LM_SUSPEND = 2,\n\tLMM_STATE_LM_POWERED = 3,\n};\n\nenum scmi_imx_misc_protocol_cmd {\n\tSCMI_IMX_MISC_CTRL_SET = 3,\n\tSCMI_IMX_MISC_CTRL_GET = 4,\n\tSCMI_IMX_MISC_DISCOVER_BUILD_INFO = 6,\n\tSCMI_IMX_MISC_CTRL_NOTIFY = 8,\n\tSCMI_IMX_MISC_CFG_INFO_GET = 12,\n\tSCMI_IMX_MISC_SYSLOG_GET = 13,\n\tSCMI_IMX_MISC_BOARD_INFO = 14,\n};\n\nenum scmi_notification_events {\n\tSCMI_EVENT_POWER_STATE_CHANGED = 0,\n\tSCMI_EVENT_CLOCK_RATE_CHANGED = 0,\n\tSCMI_EVENT_CLOCK_RATE_CHANGE_REQUESTED = 1,\n\tSCMI_EVENT_PERFORMANCE_LIMITS_CHANGED = 0,\n\tSCMI_EVENT_PERFORMANCE_LEVEL_CHANGED = 1,\n\tSCMI_EVENT_SENSOR_TRIP_POINT_EVENT = 0,\n\tSCMI_EVENT_SENSOR_UPDATE = 1,\n\tSCMI_EVENT_RESET_ISSUED = 0,\n\tSCMI_EVENT_BASE_ERROR_EVENT = 0,\n\tSCMI_EVENT_SYSTEM_POWER_STATE_NOTIFIER = 0,\n\tSCMI_EVENT_POWERCAP_CAP_CHANGED = 0,\n\tSCMI_EVENT_POWERCAP_MEASUREMENTS_CHANGED = 1,\n};\n\nenum scmi_nxp_notification_events {\n\tSCMI_EVENT_IMX_BBM_RTC = 0,\n\tSCMI_EVENT_IMX_BBM_BUTTON = 1,\n\tSCMI_EVENT_IMX_MISC_CONTROL = 0,\n};\n\nenum scmi_optee_pta_cmd {\n\tPTA_SCMI_CMD_CAPABILITIES = 0,\n\tPTA_SCMI_CMD_PROCESS_SMT_CHANNEL = 1,\n\tPTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE = 2,\n\tPTA_SCMI_CMD_GET_CHANNEL = 3,\n\tPTA_SCMI_CMD_PROCESS_MSG_CHANNEL = 4,\n};\n\nenum scmi_performance_protocol_cmd {\n\tPERF_DOMAIN_ATTRIBUTES = 3,\n\tPERF_DESCRIBE_LEVELS = 4,\n\tPERF_LIMITS_SET = 5,\n\tPERF_LIMITS_GET = 6,\n\tPERF_LEVEL_SET = 7,\n\tPERF_LEVEL_GET = 8,\n\tPERF_NOTIFY_LIMITS = 9,\n\tPERF_NOTIFY_LEVEL = 10,\n\tPERF_DESCRIBE_FASTCHANNEL = 11,\n\tPERF_DOMAIN_NAME_GET = 12,\n};\n\nenum scmi_pinctrl_conf_type {\n\tSCMI_PIN_DEFAULT = 0,\n\tSCMI_PIN_BIAS_BUS_HOLD = 1,\n\tSCMI_PIN_BIAS_DISABLE = 2,\n\tSCMI_PIN_BIAS_HIGH_IMPEDANCE = 3,\n\tSCMI_PIN_BIAS_PULL_UP = 4,\n\tSCMI_PIN_BIAS_PULL_DEFAULT = 5,\n\tSCMI_PIN_BIAS_PULL_DOWN = 6,\n\tSCMI_PIN_DRIVE_OPEN_DRAIN = 7,\n\tSCMI_PIN_DRIVE_OPEN_SOURCE = 8,\n\tSCMI_PIN_DRIVE_PUSH_PULL = 9,\n\tSCMI_PIN_DRIVE_STRENGTH = 10,\n\tSCMI_PIN_INPUT_DEBOUNCE = 11,\n\tSCMI_PIN_INPUT_MODE = 12,\n\tSCMI_PIN_PULL_MODE = 13,\n\tSCMI_PIN_INPUT_VALUE = 14,\n\tSCMI_PIN_INPUT_SCHMITT = 15,\n\tSCMI_PIN_LOW_POWER_MODE = 16,\n\tSCMI_PIN_OUTPUT_MODE = 17,\n\tSCMI_PIN_OUTPUT_VALUE = 18,\n\tSCMI_PIN_POWER_SOURCE = 19,\n\tSCMI_PIN_SLEW_RATE = 20,\n\tSCMI_PIN_OEM_START = 192,\n\tSCMI_PIN_OEM_END = 255,\n};\n\nenum scmi_pinctrl_protocol_cmd {\n\tPINCTRL_ATTRIBUTES = 3,\n\tPINCTRL_LIST_ASSOCIATIONS = 4,\n\tPINCTRL_SETTINGS_GET = 5,\n\tPINCTRL_SETTINGS_CONFIGURE = 6,\n\tPINCTRL_REQUEST = 7,\n\tPINCTRL_RELEASE = 8,\n\tPINCTRL_NAME_GET = 9,\n\tPINCTRL_SET_PERMISSIONS = 10,\n};\n\nenum scmi_pinctrl_selector_type {\n\tPIN_TYPE = 0,\n\tGROUP_TYPE = 1,\n\tFUNCTION_TYPE = 2,\n};\n\nenum scmi_power_protocol_cmd {\n\tPOWER_DOMAIN_ATTRIBUTES = 3,\n\tPOWER_STATE_SET = 4,\n\tPOWER_STATE_GET = 5,\n\tPOWER_STATE_NOTIFY = 6,\n\tPOWER_DOMAIN_NAME_GET = 8,\n};\n\nenum scmi_power_scale {\n\tSCMI_POWER_BOGOWATTS = 0,\n\tSCMI_POWER_MILLIWATTS = 1,\n\tSCMI_POWER_MICROWATTS = 2,\n};\n\nenum scmi_powercap_protocol_cmd {\n\tPOWERCAP_DOMAIN_ATTRIBUTES = 3,\n\tPOWERCAP_CAP_GET = 4,\n\tPOWERCAP_CAP_SET = 5,\n\tPOWERCAP_PAI_GET = 6,\n\tPOWERCAP_PAI_SET = 7,\n\tPOWERCAP_DOMAIN_NAME_GET = 8,\n\tPOWERCAP_MEASUREMENTS_GET = 9,\n\tPOWERCAP_CAP_NOTIFY = 10,\n\tPOWERCAP_MEASUREMENTS_NOTIFY = 11,\n\tPOWERCAP_DESCRIBE_FASTCHANNEL = 12,\n};\n\nenum scmi_reset_protocol_cmd {\n\tRESET_DOMAIN_ATTRIBUTES = 3,\n\tRESET = 4,\n\tRESET_NOTIFY = 5,\n\tRESET_DOMAIN_NAME_GET = 6,\n};\n\nenum scmi_sensor_class {\n\tNONE = 0,\n\tUNSPEC = 1,\n\tTEMPERATURE_C = 2,\n\tTEMPERATURE_F = 3,\n\tTEMPERATURE_K = 4,\n\tVOLTAGE = 5,\n\tCURRENT = 6,\n\tPOWER = 7,\n\tENERGY = 8,\n\tCHARGE = 9,\n\tVOLTAMPERE = 10,\n\tNITS = 11,\n\tLUMENS = 12,\n\tLUX = 13,\n\tCANDELAS = 14,\n\tKPA = 15,\n\tPSI = 16,\n\tNEWTON = 17,\n\tCFM = 18,\n\tRPM = 19,\n\tHERTZ = 20,\n\tSECS = 21,\n\tMINS = 22,\n\tHOURS = 23,\n\tDAYS = 24,\n\tWEEKS = 25,\n\tMILS = 26,\n\tINCHES = 27,\n\tFEET = 28,\n\tCUBIC_INCHES = 29,\n\tCUBIC_FEET = 30,\n\tMETERS = 31,\n\tCUBIC_CM = 32,\n\tCUBIC_METERS = 33,\n\tLITERS = 34,\n\tFLUID_OUNCES = 35,\n\tRADIANS = 36,\n\tSTERADIANS = 37,\n\tREVOLUTIONS = 38,\n\tCYCLES = 39,\n\tGRAVITIES = 40,\n\tOUNCES = 41,\n\tPOUNDS = 42,\n\tFOOT_POUNDS = 43,\n\tOUNCE_INCHES = 44,\n\tGAUSS = 45,\n\tGILBERTS = 46,\n\tHENRIES = 47,\n\tFARADS = 48,\n\tOHMS = 49,\n\tSIEMENS = 50,\n\tMOLES = 51,\n\tBECQUERELS = 52,\n\tPPM = 53,\n\tDECIBELS = 54,\n\tDBA = 55,\n\tDBC = 56,\n\tGRAYS = 57,\n\tSIEVERTS = 58,\n\tCOLOR_TEMP_K = 59,\n\tBITS = 60,\n\tBYTES = 61,\n\tWORDS = 62,\n\tDWORDS = 63,\n\tQWORDS = 64,\n\tPERCENTAGE = 65,\n\tPASCALS = 66,\n\tCOUNTS = 67,\n\tGRAMS = 68,\n\tNEWTON_METERS = 69,\n\tHITS = 70,\n\tMISSES = 71,\n\tRETRIES = 72,\n\tOVERRUNS = 73,\n\tUNDERRUNS = 74,\n\tCOLLISIONS = 75,\n\tPACKETS = 76,\n\tMESSAGES = 77,\n\tCHARS = 78,\n\tERRORS = 79,\n\tCORRECTED_ERRS = 80,\n\tUNCORRECTABLE_ERRS = 81,\n\tSQ_MILS = 82,\n\tSQ_INCHES = 83,\n\tSQ_FEET = 84,\n\tSQ_CM = 85,\n\tSQ_METERS = 86,\n\tRADIANS_SEC = 87,\n\tBPM = 88,\n\tMETERS_SEC_SQUARED = 89,\n\tMETERS_SEC = 90,\n\tCUBIC_METERS_SEC = 91,\n\tMM_MERCURY = 92,\n\tRADIANS_SEC_SQUARED = 93,\n\tOEM_UNIT = 255,\n};\n\nenum scmi_sensor_protocol_cmd {\n\tSENSOR_DESCRIPTION_GET = 3,\n\tSENSOR_TRIP_POINT_NOTIFY = 4,\n\tSENSOR_TRIP_POINT_CONFIG = 5,\n\tSENSOR_READING_GET = 6,\n\tSENSOR_AXIS_DESCRIPTION_GET = 7,\n\tSENSOR_LIST_UPDATE_INTERVALS = 8,\n\tSENSOR_CONFIG_GET = 9,\n\tSENSOR_CONFIG_SET = 10,\n\tSENSOR_CONTINUOUS_UPDATE_NOTIFY = 11,\n\tSENSOR_NAME_GET = 12,\n\tSENSOR_AXIS_NAME_GET = 13,\n};\n\nenum scmi_std_protocol {\n\tSCMI_PROTOCOL_BASE = 16,\n\tSCMI_PROTOCOL_POWER = 17,\n\tSCMI_PROTOCOL_SYSTEM = 18,\n\tSCMI_PROTOCOL_PERF = 19,\n\tSCMI_PROTOCOL_CLOCK = 20,\n\tSCMI_PROTOCOL_SENSOR = 21,\n\tSCMI_PROTOCOL_RESET = 22,\n\tSCMI_PROTOCOL_VOLTAGE = 23,\n\tSCMI_PROTOCOL_POWERCAP = 24,\n\tSCMI_PROTOCOL_PINCTRL = 25,\n};\n\nenum scmi_system_events {\n\tSCMI_SYSTEM_SHUTDOWN = 0,\n\tSCMI_SYSTEM_COLDRESET = 1,\n\tSCMI_SYSTEM_WARMRESET = 2,\n\tSCMI_SYSTEM_POWERUP = 3,\n\tSCMI_SYSTEM_SUSPEND = 4,\n\tSCMI_SYSTEM_MAX = 5,\n};\n\nenum scmi_system_protocol_cmd {\n\tSYSTEM_POWER_STATE_NOTIFY = 5,\n};\n\nenum scmi_voltage_level_mode {\n\tSCMI_VOLTAGE_LEVEL_SET_AUTO = 0,\n\tSCMI_VOLTAGE_LEVEL_SET_SYNC = 1,\n};\n\nenum scmi_voltage_protocol_cmd {\n\tVOLTAGE_DOMAIN_ATTRIBUTES = 3,\n\tVOLTAGE_DESCRIBE_LEVELS = 4,\n\tVOLTAGE_CONFIG_SET = 5,\n\tVOLTAGE_CONFIG_GET = 6,\n\tVOLTAGE_LEVEL_SET = 7,\n\tVOLTAGE_LEVEL_GET = 8,\n\tVOLTAGE_DOMAIN_NAME_GET = 9,\n};\n\nenum scpi_drv_cmds {\n\tCMD_SCPI_CAPABILITIES = 0,\n\tCMD_GET_CLOCK_INFO = 1,\n\tCMD_GET_CLOCK_VALUE = 2,\n\tCMD_SET_CLOCK_VALUE = 3,\n\tCMD_GET_DVFS = 4,\n\tCMD_SET_DVFS = 5,\n\tCMD_GET_DVFS_INFO = 6,\n\tCMD_SENSOR_CAPABILITIES = 7,\n\tCMD_SENSOR_INFO = 8,\n\tCMD_SENSOR_VALUE = 9,\n\tCMD_SET_DEVICE_PWR_STATE = 10,\n\tCMD_GET_DEVICE_PWR_STATE = 11,\n\tCMD_MAX_COUNT = 12,\n};\n\nenum scpi_error_codes {\n\tSCPI_SUCCESS = 0,\n\tSCPI_ERR_PARAM = 1,\n\tSCPI_ERR_ALIGN = 2,\n\tSCPI_ERR_SIZE = 3,\n\tSCPI_ERR_HANDLER = 4,\n\tSCPI_ERR_ACCESS = 5,\n\tSCPI_ERR_RANGE = 6,\n\tSCPI_ERR_TIMEOUT = 7,\n\tSCPI_ERR_NOMEM = 8,\n\tSCPI_ERR_PWRSTATE = 9,\n\tSCPI_ERR_SUPPORT = 10,\n\tSCPI_ERR_DEVICE = 11,\n\tSCPI_ERR_BUSY = 12,\n\tSCPI_ERR_MAX = 13,\n};\n\nenum scpi_power_domain_state {\n\tSCPI_PD_STATE_ON = 0,\n\tSCPI_PD_STATE_OFF = 3,\n};\n\nenum scpi_sensor_class {\n\tTEMPERATURE = 0,\n\tVOLTAGE___2 = 1,\n\tCURRENT___2 = 2,\n\tPOWER___2 = 3,\n\tENERGY___2 = 4,\n};\n\nenum scpi_std_cmd {\n\tSCPI_CMD_INVALID = 0,\n\tSCPI_CMD_SCPI_READY = 1,\n\tSCPI_CMD_SCPI_CAPABILITIES = 2,\n\tSCPI_CMD_SET_CSS_PWR_STATE = 3,\n\tSCPI_CMD_GET_CSS_PWR_STATE = 4,\n\tSCPI_CMD_SET_SYS_PWR_STATE = 5,\n\tSCPI_CMD_SET_CPU_TIMER = 6,\n\tSCPI_CMD_CANCEL_CPU_TIMER = 7,\n\tSCPI_CMD_DVFS_CAPABILITIES = 8,\n\tSCPI_CMD_GET_DVFS_INFO = 9,\n\tSCPI_CMD_SET_DVFS = 10,\n\tSCPI_CMD_GET_DVFS = 11,\n\tSCPI_CMD_GET_DVFS_STAT = 12,\n\tSCPI_CMD_CLOCK_CAPABILITIES = 13,\n\tSCPI_CMD_GET_CLOCK_INFO = 14,\n\tSCPI_CMD_SET_CLOCK_VALUE = 15,\n\tSCPI_CMD_GET_CLOCK_VALUE = 16,\n\tSCPI_CMD_PSU_CAPABILITIES = 17,\n\tSCPI_CMD_GET_PSU_INFO = 18,\n\tSCPI_CMD_SET_PSU = 19,\n\tSCPI_CMD_GET_PSU = 20,\n\tSCPI_CMD_SENSOR_CAPABILITIES = 21,\n\tSCPI_CMD_SENSOR_INFO = 22,\n\tSCPI_CMD_SENSOR_VALUE = 23,\n\tSCPI_CMD_SENSOR_CFG_PERIODIC = 24,\n\tSCPI_CMD_SENSOR_CFG_BOUNDS = 25,\n\tSCPI_CMD_SENSOR_ASYNC_VALUE = 26,\n\tSCPI_CMD_SET_DEVICE_PWR_STATE = 27,\n\tSCPI_CMD_GET_DEVICE_PWR_STATE = 28,\n\tSCPI_CMD_COUNT = 29,\n};\n\nenum scpsys_bus_prot_block {\n\tBUS_PROT_BLOCK_INFRA = 0,\n\tBUS_PROT_BLOCK_INFRA_NAO = 1,\n\tBUS_PROT_BLOCK_SMI = 2,\n\tBUS_PROT_BLOCK_SPM = 3,\n\tBUS_PROT_BLOCK_COUNT = 4,\n};\n\nenum scpsys_bus_prot_flags {\n\tBUS_PROT_REG_UPDATE = 2,\n\tBUS_PROT_IGNORE_CLR_ACK = 4,\n\tBUS_PROT_INVERTED = 8,\n};\n\nenum scpsys_mtcmos_type {\n\tSCPSYS_MTCMOS_TYPE_DIRECT_CTL = 0,\n\tSCPSYS_MTCMOS_TYPE_HW_VOTER = 1,\n\tSCPSYS_MTCMOS_TYPE_MAX = 2,\n};\n\nenum scpsys_rtff_type {\n\tSCPSYS_RTFF_NONE = 0,\n\tSCPSYS_RTFF_TYPE_GENERIC = 1,\n\tSCPSYS_RTFF_TYPE_PCIE_PHY = 2,\n\tSCPSYS_RTFF_TYPE_STOR_UFS = 3,\n\tSCPSYS_RTFF_TYPE_MAX = 4,\n};\n\nenum scrub_type {\n\tSCRUB_UNKNOWN = 0,\n\tSCRUB_NONE = 1,\n\tSCRUB_SW_PROG = 2,\n\tSCRUB_SW_SRC = 3,\n\tSCRUB_SW_PROG_SRC = 4,\n\tSCRUB_SW_TUNABLE = 5,\n\tSCRUB_HW_PROG = 6,\n\tSCRUB_HW_SRC = 7,\n\tSCRUB_HW_PROG_SRC = 8,\n\tSCRUB_HW_TUNABLE = 9,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_guard_type {\n\tSHOST_DIX_GUARD_CRC = 1,\n\tSHOST_DIX_GUARD_IP = 2,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 2500,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_conntrack {\n\tSCTP_CONNTRACK_NONE = 0,\n\tSCTP_CONNTRACK_CLOSED = 1,\n\tSCTP_CONNTRACK_COOKIE_WAIT = 2,\n\tSCTP_CONNTRACK_COOKIE_ECHOED = 3,\n\tSCTP_CONNTRACK_ESTABLISHED = 4,\n\tSCTP_CONNTRACK_SHUTDOWN_SENT = 5,\n\tSCTP_CONNTRACK_SHUTDOWN_RECD = 6,\n\tSCTP_CONNTRACK_SHUTDOWN_ACK_SENT = 7,\n\tSCTP_CONNTRACK_HEARTBEAT_SENT = 8,\n\tSCTP_CONNTRACK_HEARTBEAT_ACKED = 9,\n\tSCTP_CONNTRACK_MAX = 10,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 7500,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_HAS_CGROUP_WEIGHT = 65536ULL,\n\tSCX_OPS_ALL_FLAGS = 65663ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1,\n\t__SCX_REENQ_FILTER_MASK = 65535,\n\t__SCX_REENQ_USER_MASK = 1,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum sd_uhs2_operation {\n\tUHS2_PHY_INIT = 0,\n\tUHS2_SET_CONFIG = 1,\n\tUHS2_ENABLE_INT = 2,\n\tUHS2_DISABLE_INT = 3,\n\tUHS2_ENABLE_CLK = 4,\n\tUHS2_DISABLE_CLK = 5,\n\tUHS2_CHECK_DORMANT = 6,\n\tUHS2_SET_IOS = 7,\n};\n\nenum sdhci_cookie {\n\tCOOKIE_UNMAPPED___3 = 0,\n\tCOOKIE_PRE_MAPPED___3 = 1,\n\tCOOKIE_MAPPED___3 = 2,\n};\n\nenum sdhci_reset_reason {\n\tSDHCI_RESET_FOR_INIT = 0,\n\tSDHCI_RESET_FOR_REQUEST_ERROR = 1,\n\tSDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY = 2,\n\tSDHCI_RESET_FOR_TUNING_ABORT = 3,\n\tSDHCI_RESET_FOR_CARD_REMOVED = 4,\n\tSDHCI_RESET_FOR_CQE_RECOVERY = 5,\n};\n\nenum sdm660_functions {\n\tmsm_mux_adsp_ext___10 = 0,\n\tmsm_mux_agera_pll___6 = 1,\n\tmsm_mux_atest_char___22 = 2,\n\tmsm_mux_atest_char0___12 = 3,\n\tmsm_mux_atest_char1___12 = 4,\n\tmsm_mux_atest_char2___12 = 5,\n\tmsm_mux_atest_char3___12 = 6,\n\tmsm_mux_atest_gpsadc0___4 = 7,\n\tmsm_mux_atest_gpsadc1___4 = 8,\n\tmsm_mux_atest_tsens___8 = 9,\n\tmsm_mux_atest_tsens2___5 = 10,\n\tmsm_mux_atest_usb1___6 = 11,\n\tmsm_mux_atest_usb10___5 = 12,\n\tmsm_mux_atest_usb11___5 = 13,\n\tmsm_mux_atest_usb12___5 = 14,\n\tmsm_mux_atest_usb13___5 = 15,\n\tmsm_mux_atest_usb2___6 = 16,\n\tmsm_mux_atest_usb20___3 = 17,\n\tmsm_mux_atest_usb21___3 = 18,\n\tmsm_mux_atest_usb22___3 = 19,\n\tmsm_mux_atest_usb23___3 = 20,\n\tmsm_mux_audio_ref___9 = 21,\n\tmsm_mux_bimc_dte0___6 = 22,\n\tmsm_mux_bimc_dte1___6 = 23,\n\tmsm_mux_blsp_i2c1___8 = 24,\n\tmsm_mux_blsp_i2c2___7 = 25,\n\tmsm_mux_blsp_i2c3___8 = 26,\n\tmsm_mux_blsp_i2c4___8 = 27,\n\tmsm_mux_blsp_i2c5___8 = 28,\n\tmsm_mux_blsp_i2c6___7 = 29,\n\tmsm_mux_blsp_i2c7___5 = 30,\n\tmsm_mux_blsp_i2c8_a = 31,\n\tmsm_mux_blsp_i2c8_b = 32,\n\tmsm_mux_blsp_spi1___7 = 33,\n\tmsm_mux_blsp_spi2___8 = 34,\n\tmsm_mux_blsp_spi3___8 = 35,\n\tmsm_mux_blsp_spi3_cs1___2 = 36,\n\tmsm_mux_blsp_spi3_cs2___2 = 37,\n\tmsm_mux_blsp_spi4___8 = 38,\n\tmsm_mux_blsp_spi5___8 = 39,\n\tmsm_mux_blsp_spi6___7 = 40,\n\tmsm_mux_blsp_spi7___5 = 41,\n\tmsm_mux_blsp_spi8_a = 42,\n\tmsm_mux_blsp_spi8_b = 43,\n\tmsm_mux_blsp_spi8_cs1 = 44,\n\tmsm_mux_blsp_spi8_cs2 = 45,\n\tmsm_mux_blsp_uart1___6 = 46,\n\tmsm_mux_blsp_uart2___7 = 47,\n\tmsm_mux_blsp_uart5___6 = 48,\n\tmsm_mux_blsp_uart6_a = 49,\n\tmsm_mux_blsp_uart6_b = 50,\n\tmsm_mux_blsp_uim1___4 = 51,\n\tmsm_mux_blsp_uim2___4 = 52,\n\tmsm_mux_blsp_uim5___3 = 53,\n\tmsm_mux_blsp_uim6___3 = 54,\n\tmsm_mux_cam_mclk___15 = 55,\n\tmsm_mux_cci_async___13 = 56,\n\tmsm_mux_cci_i2c___12 = 57,\n\tmsm_mux_cri_trng___16 = 58,\n\tmsm_mux_cri_trng0___15 = 59,\n\tmsm_mux_cri_trng1___15 = 60,\n\tmsm_mux_dbg_out___19 = 61,\n\tmsm_mux_ddr_bist___13 = 62,\n\tmsm_mux_gcc_gp1___11 = 63,\n\tmsm_mux_gcc_gp2___11 = 64,\n\tmsm_mux_gcc_gp3___11 = 65,\n\tmsm_mux_gpio___25 = 66,\n\tmsm_mux_gps_tx_a = 67,\n\tmsm_mux_gps_tx_b = 68,\n\tmsm_mux_gps_tx_c = 69,\n\tmsm_mux_isense_dbg___3 = 70,\n\tmsm_mux_jitter_bist___12 = 71,\n\tmsm_mux_ldo_en___9 = 72,\n\tmsm_mux_ldo_update___9 = 73,\n\tmsm_mux_m_voc___11 = 74,\n\tmsm_mux_mdp_vsync___17 = 75,\n\tmsm_mux_mdss_vsync0 = 76,\n\tmsm_mux_mdss_vsync1 = 77,\n\tmsm_mux_mdss_vsync2 = 78,\n\tmsm_mux_mdss_vsync3 = 79,\n\tmsm_mux_mss_lte___9 = 80,\n\tmsm_mux_nav_pps_a = 81,\n\tmsm_mux_nav_pps_b = 82,\n\tmsm_mux_nav_pps_c = 83,\n\tmsm_mux_pa_indicator___10 = 84,\n\tmsm_mux_phase_flag0 = 85,\n\tmsm_mux_phase_flag1 = 86,\n\tmsm_mux_phase_flag2 = 87,\n\tmsm_mux_phase_flag3 = 88,\n\tmsm_mux_phase_flag4 = 89,\n\tmsm_mux_phase_flag5 = 90,\n\tmsm_mux_phase_flag6 = 91,\n\tmsm_mux_phase_flag7 = 92,\n\tmsm_mux_phase_flag8 = 93,\n\tmsm_mux_phase_flag9 = 94,\n\tmsm_mux_phase_flag10 = 95,\n\tmsm_mux_phase_flag11 = 96,\n\tmsm_mux_phase_flag12 = 97,\n\tmsm_mux_phase_flag13 = 98,\n\tmsm_mux_phase_flag14 = 99,\n\tmsm_mux_phase_flag15 = 100,\n\tmsm_mux_phase_flag16 = 101,\n\tmsm_mux_phase_flag17 = 102,\n\tmsm_mux_phase_flag18 = 103,\n\tmsm_mux_phase_flag19 = 104,\n\tmsm_mux_phase_flag20 = 105,\n\tmsm_mux_phase_flag21 = 106,\n\tmsm_mux_phase_flag22 = 107,\n\tmsm_mux_phase_flag23 = 108,\n\tmsm_mux_phase_flag24 = 109,\n\tmsm_mux_phase_flag25 = 110,\n\tmsm_mux_phase_flag26 = 111,\n\tmsm_mux_phase_flag27 = 112,\n\tmsm_mux_phase_flag28 = 113,\n\tmsm_mux_phase_flag29 = 114,\n\tmsm_mux_phase_flag30 = 115,\n\tmsm_mux_phase_flag31 = 116,\n\tmsm_mux_pll_bypassnl___8 = 117,\n\tmsm_mux_pll_reset___7 = 118,\n\tmsm_mux_pri_mi2s___9 = 119,\n\tmsm_mux_pri_mi2s_ws___5 = 120,\n\tmsm_mux_prng_rosc___15 = 121,\n\tmsm_mux_pwr_crypto___3 = 122,\n\tmsm_mux_pwr_modem___3 = 123,\n\tmsm_mux_pwr_nav___3 = 124,\n\tmsm_mux_qdss_cti0_a___2 = 125,\n\tmsm_mux_qdss_cti0_b___2 = 126,\n\tmsm_mux_qdss_cti1_a___2 = 127,\n\tmsm_mux_qdss_cti1_b___2 = 128,\n\tmsm_mux_qdss_gpio___9 = 129,\n\tmsm_mux_qdss_gpio0 = 130,\n\tmsm_mux_qdss_gpio1 = 131,\n\tmsm_mux_qdss_gpio10 = 132,\n\tmsm_mux_qdss_gpio11 = 133,\n\tmsm_mux_qdss_gpio12 = 134,\n\tmsm_mux_qdss_gpio13 = 135,\n\tmsm_mux_qdss_gpio14 = 136,\n\tmsm_mux_qdss_gpio15 = 137,\n\tmsm_mux_qdss_gpio2 = 138,\n\tmsm_mux_qdss_gpio3 = 139,\n\tmsm_mux_qdss_gpio4 = 140,\n\tmsm_mux_qdss_gpio5 = 141,\n\tmsm_mux_qdss_gpio6 = 142,\n\tmsm_mux_qdss_gpio7 = 143,\n\tmsm_mux_qdss_gpio8 = 144,\n\tmsm_mux_qdss_gpio9 = 145,\n\tmsm_mux_qlink_enable___4 = 146,\n\tmsm_mux_qlink_request___4 = 147,\n\tmsm_mux_qspi_clk___11 = 148,\n\tmsm_mux_qspi_cs___11 = 149,\n\tmsm_mux_qspi_data0 = 150,\n\tmsm_mux_qspi_data1 = 151,\n\tmsm_mux_qspi_data2 = 152,\n\tmsm_mux_qspi_data3 = 153,\n\tmsm_mux_qspi_resetn = 154,\n\tmsm_mux_sec_mi2s___9 = 155,\n\tmsm_mux_sndwire_clk = 156,\n\tmsm_mux_sndwire_data = 157,\n\tmsm_mux_sp_cmu___5 = 158,\n\tmsm_mux_ssc_irq___3 = 159,\n\tmsm_mux_tgu_ch0___8 = 160,\n\tmsm_mux_tgu_ch1___8 = 161,\n\tmsm_mux_tsense_pwm1___12 = 162,\n\tmsm_mux_tsense_pwm2___12 = 163,\n\tmsm_mux_uim1_clk___7 = 164,\n\tmsm_mux_uim1_data___7 = 165,\n\tmsm_mux_uim1_present___7 = 166,\n\tmsm_mux_uim1_reset___7 = 167,\n\tmsm_mux_uim2_clk___5 = 168,\n\tmsm_mux_uim2_data___5 = 169,\n\tmsm_mux_uim2_present___5 = 170,\n\tmsm_mux_uim2_reset___5 = 171,\n\tmsm_mux_uim_batt___8 = 172,\n\tmsm_mux_vfr_1___11 = 173,\n\tmsm_mux_vsense_clkout___2 = 174,\n\tmsm_mux_vsense_data0___2 = 175,\n\tmsm_mux_vsense_data1___2 = 176,\n\tmsm_mux_vsense_mode___2 = 177,\n\tmsm_mux_wlan1_adc0___5 = 178,\n\tmsm_mux_wlan1_adc1___5 = 179,\n\tmsm_mux_wlan2_adc0___4 = 180,\n\tmsm_mux_wlan2_adc1___4 = 181,\n\tmsm_mux_____20 = 182,\n};\n\nenum sdm670_functions {\n\tmsm_mux_gpio___26 = 0,\n\tmsm_mux_adsp_ext___11 = 1,\n\tmsm_mux_agera_pll___7 = 2,\n\tmsm_mux_atest_char___23 = 3,\n\tmsm_mux_atest_tsens___9 = 4,\n\tmsm_mux_atest_tsens2___6 = 5,\n\tmsm_mux_atest_usb1___7 = 6,\n\tmsm_mux_atest_usb10___6 = 7,\n\tmsm_mux_atest_usb11___6 = 8,\n\tmsm_mux_atest_usb12___6 = 9,\n\tmsm_mux_atest_usb13___6 = 10,\n\tmsm_mux_atest_usb2___7 = 11,\n\tmsm_mux_atest_usb20___4 = 12,\n\tmsm_mux_atest_usb21___4 = 13,\n\tmsm_mux_atest_usb22___4 = 14,\n\tmsm_mux_atest_usb23___4 = 15,\n\tmsm_mux_cam_mclk___16 = 16,\n\tmsm_mux_cci_async___14 = 17,\n\tmsm_mux_cci_i2c___13 = 18,\n\tmsm_mux_cci_timer0___12 = 19,\n\tmsm_mux_cci_timer1___12 = 20,\n\tmsm_mux_cci_timer2___12 = 21,\n\tmsm_mux_cci_timer3___11 = 22,\n\tmsm_mux_cci_timer4___10 = 23,\n\tmsm_mux_copy_gp___2 = 24,\n\tmsm_mux_copy_phase___2 = 25,\n\tmsm_mux_dbg_out___20 = 26,\n\tmsm_mux_ddr_bist___14 = 27,\n\tmsm_mux_ddr_pxi0___10 = 28,\n\tmsm_mux_ddr_pxi1___10 = 29,\n\tmsm_mux_ddr_pxi2___8 = 30,\n\tmsm_mux_ddr_pxi3___8 = 31,\n\tmsm_mux_edp_hot___7 = 32,\n\tmsm_mux_edp_lcd___7 = 33,\n\tmsm_mux_gcc_gp1___12 = 34,\n\tmsm_mux_gcc_gp2___12 = 35,\n\tmsm_mux_gcc_gp3___12 = 36,\n\tmsm_mux_gp_pdm0___4 = 37,\n\tmsm_mux_gp_pdm1___4 = 38,\n\tmsm_mux_gp_pdm2___4 = 39,\n\tmsm_mux_gps_tx___4 = 40,\n\tmsm_mux_jitter_bist___13 = 41,\n\tmsm_mux_ldo_en___10 = 42,\n\tmsm_mux_ldo_update___10 = 43,\n\tmsm_mux_lpass_slimbus___8 = 44,\n\tmsm_mux_m_voc___12 = 45,\n\tmsm_mux_mdp_vsync___18 = 46,\n\tmsm_mux_mdp_vsync0___5 = 47,\n\tmsm_mux_mdp_vsync1___5 = 48,\n\tmsm_mux_mdp_vsync2___5 = 49,\n\tmsm_mux_mdp_vsync3___5 = 50,\n\tmsm_mux_mss_lte___10 = 51,\n\tmsm_mux_nav_pps___7 = 52,\n\tmsm_mux_pa_indicator___11 = 53,\n\tmsm_mux_pci_e0___5 = 54,\n\tmsm_mux_pci_e1___4 = 55,\n\tmsm_mux_phase_flag___13 = 56,\n\tmsm_mux_pll_bist___10 = 57,\n\tmsm_mux_pll_bypassnl___9 = 58,\n\tmsm_mux_pll_reset___8 = 59,\n\tmsm_mux_pri_mi2s___10 = 60,\n\tmsm_mux_pri_mi2s_ws___6 = 61,\n\tmsm_mux_prng_rosc___16 = 62,\n\tmsm_mux_qdss_cti___13 = 63,\n\tmsm_mux_qdss___4 = 64,\n\tmsm_mux_qlink_enable___5 = 65,\n\tmsm_mux_qlink_request___5 = 66,\n\tmsm_mux_qua_mi2s___5 = 67,\n\tmsm_mux_qup0___5 = 68,\n\tmsm_mux_qup1___5 = 69,\n\tmsm_mux_qup10___6 = 70,\n\tmsm_mux_qup11___5 = 71,\n\tmsm_mux_qup12___6 = 72,\n\tmsm_mux_qup13___5 = 73,\n\tmsm_mux_qup14___6 = 74,\n\tmsm_mux_qup15___6 = 75,\n\tmsm_mux_qup2___4 = 76,\n\tmsm_mux_qup3___4 = 77,\n\tmsm_mux_qup4___4 = 78,\n\tmsm_mux_qup5___4 = 79,\n\tmsm_mux_qup6___3 = 80,\n\tmsm_mux_qup7___3 = 81,\n\tmsm_mux_qup8___3 = 82,\n\tmsm_mux_qup9___3 = 83,\n\tmsm_mux_qup_l4___2 = 84,\n\tmsm_mux_qup_l5___2 = 85,\n\tmsm_mux_qup_l6___2 = 86,\n\tmsm_mux_sd_write___14 = 87,\n\tmsm_mux_sdc4_clk___7 = 88,\n\tmsm_mux_sdc4_cmd___7 = 89,\n\tmsm_mux_sdc4_data = 90,\n\tmsm_mux_sec_mi2s___10 = 91,\n\tmsm_mux_ter_mi2s___6 = 92,\n\tmsm_mux_tgu_ch0___9 = 93,\n\tmsm_mux_tgu_ch1___9 = 94,\n\tmsm_mux_tgu_ch2___6 = 95,\n\tmsm_mux_tgu_ch3___6 = 96,\n\tmsm_mux_tsif1_clk___2 = 97,\n\tmsm_mux_tsif1_data___2 = 98,\n\tmsm_mux_tsif1_en___2 = 99,\n\tmsm_mux_tsif1_error___2 = 100,\n\tmsm_mux_tsif1_sync___2 = 101,\n\tmsm_mux_tsif2_clk___2 = 102,\n\tmsm_mux_tsif2_data___2 = 103,\n\tmsm_mux_tsif2_en___2 = 104,\n\tmsm_mux_tsif2_error___2 = 105,\n\tmsm_mux_tsif2_sync___2 = 106,\n\tmsm_mux_uim1_clk___8 = 107,\n\tmsm_mux_uim1_data___8 = 108,\n\tmsm_mux_uim1_present___8 = 109,\n\tmsm_mux_uim1_reset___8 = 110,\n\tmsm_mux_uim2_clk___6 = 111,\n\tmsm_mux_uim2_data___6 = 112,\n\tmsm_mux_uim2_present___6 = 113,\n\tmsm_mux_uim2_reset___6 = 114,\n\tmsm_mux_uim_batt___9 = 115,\n\tmsm_mux_usb_phy___7 = 116,\n\tmsm_mux_vfr_1___12 = 117,\n\tmsm_mux_vsense_trigger___9 = 118,\n\tmsm_mux_wlan1_adc0___6 = 119,\n\tmsm_mux_wlan1_adc1___6 = 120,\n\tmsm_mux_wlan2_adc0___5 = 121,\n\tmsm_mux_wlan2_adc1___5 = 122,\n\tmsm_mux_wsa_clk___2 = 123,\n\tmsm_mux_wsa_data___2 = 124,\n\tmsm_mux_____21 = 125,\n};\n\nenum sdm845_functions {\n\tmsm_mux_gpio___27 = 0,\n\tmsm_mux_adsp_ext___12 = 1,\n\tmsm_mux_agera_pll___8 = 2,\n\tmsm_mux_atest_char___24 = 3,\n\tmsm_mux_atest_tsens___10 = 4,\n\tmsm_mux_atest_tsens2___7 = 5,\n\tmsm_mux_atest_usb1___8 = 6,\n\tmsm_mux_atest_usb10___7 = 7,\n\tmsm_mux_atest_usb11___7 = 8,\n\tmsm_mux_atest_usb12___7 = 9,\n\tmsm_mux_atest_usb13___7 = 10,\n\tmsm_mux_atest_usb2___8 = 11,\n\tmsm_mux_atest_usb20___5 = 12,\n\tmsm_mux_atest_usb21___5 = 13,\n\tmsm_mux_atest_usb22___5 = 14,\n\tmsm_mux_atest_usb23___5 = 15,\n\tmsm_mux_audio_ref___10 = 16,\n\tmsm_mux_btfm_slimbus___5 = 17,\n\tmsm_mux_cam_mclk___17 = 18,\n\tmsm_mux_cci_async___15 = 19,\n\tmsm_mux_cci_i2c___14 = 20,\n\tmsm_mux_cci_timer0___13 = 21,\n\tmsm_mux_cci_timer1___13 = 22,\n\tmsm_mux_cci_timer2___13 = 23,\n\tmsm_mux_cci_timer3___12 = 24,\n\tmsm_mux_cci_timer4___11 = 25,\n\tmsm_mux_cri_trng___17 = 26,\n\tmsm_mux_cri_trng0___16 = 27,\n\tmsm_mux_cri_trng1___16 = 28,\n\tmsm_mux_dbg_out___21 = 29,\n\tmsm_mux_ddr_bist___15 = 30,\n\tmsm_mux_ddr_pxi0___11 = 31,\n\tmsm_mux_ddr_pxi1___11 = 32,\n\tmsm_mux_ddr_pxi2___9 = 33,\n\tmsm_mux_ddr_pxi3___9 = 34,\n\tmsm_mux_edp_hot___8 = 35,\n\tmsm_mux_edp_lcd___8 = 36,\n\tmsm_mux_gcc_gp1___13 = 37,\n\tmsm_mux_gcc_gp2___13 = 38,\n\tmsm_mux_gcc_gp3___13 = 39,\n\tmsm_mux_jitter_bist___14 = 40,\n\tmsm_mux_ldo_en___11 = 41,\n\tmsm_mux_ldo_update___11 = 42,\n\tmsm_mux_lpass_slimbus___9 = 43,\n\tmsm_mux_m_voc___13 = 44,\n\tmsm_mux_mdp_vsync___19 = 45,\n\tmsm_mux_mdp_vsync0___6 = 46,\n\tmsm_mux_mdp_vsync1___6 = 47,\n\tmsm_mux_mdp_vsync2___6 = 48,\n\tmsm_mux_mdp_vsync3___6 = 49,\n\tmsm_mux_mss_lte___11 = 50,\n\tmsm_mux_nav_pps___8 = 51,\n\tmsm_mux_pa_indicator___12 = 52,\n\tmsm_mux_pci_e0___6 = 53,\n\tmsm_mux_pci_e1___5 = 54,\n\tmsm_mux_phase_flag___14 = 55,\n\tmsm_mux_pll_bist___11 = 56,\n\tmsm_mux_pll_bypassnl___10 = 57,\n\tmsm_mux_pll_reset___9 = 58,\n\tmsm_mux_pri_mi2s___11 = 59,\n\tmsm_mux_pri_mi2s_ws___7 = 60,\n\tmsm_mux_prng_rosc___17 = 61,\n\tmsm_mux_qdss_cti___14 = 62,\n\tmsm_mux_qdss___5 = 63,\n\tmsm_mux_qlink_enable___6 = 64,\n\tmsm_mux_qlink_request___6 = 65,\n\tmsm_mux_qspi_clk___12 = 66,\n\tmsm_mux_qspi_cs___12 = 67,\n\tmsm_mux_qspi_data___7 = 68,\n\tmsm_mux_qua_mi2s___6 = 69,\n\tmsm_mux_qup0___6 = 70,\n\tmsm_mux_qup1___6 = 71,\n\tmsm_mux_qup10___7 = 72,\n\tmsm_mux_qup11___6 = 73,\n\tmsm_mux_qup12___7 = 74,\n\tmsm_mux_qup13___6 = 75,\n\tmsm_mux_qup14___7 = 76,\n\tmsm_mux_qup15___7 = 77,\n\tmsm_mux_qup2___5 = 78,\n\tmsm_mux_qup3___5 = 79,\n\tmsm_mux_qup4___5 = 80,\n\tmsm_mux_qup5___5 = 81,\n\tmsm_mux_qup6___4 = 82,\n\tmsm_mux_qup7___4 = 83,\n\tmsm_mux_qup8___4 = 84,\n\tmsm_mux_qup9___4 = 85,\n\tmsm_mux_qup_l4___3 = 86,\n\tmsm_mux_qup_l5___3 = 87,\n\tmsm_mux_qup_l6___3 = 88,\n\tmsm_mux_sd_write___15 = 89,\n\tmsm_mux_sdc4_clk___8 = 90,\n\tmsm_mux_sdc4_cmd___8 = 91,\n\tmsm_mux_sdc4_data___2 = 92,\n\tmsm_mux_sec_mi2s___11 = 93,\n\tmsm_mux_sp_cmu___6 = 94,\n\tmsm_mux_spkr_i2s___5 = 95,\n\tmsm_mux_ter_mi2s___7 = 96,\n\tmsm_mux_tgu_ch0___10 = 97,\n\tmsm_mux_tgu_ch1___10 = 98,\n\tmsm_mux_tgu_ch2___7 = 99,\n\tmsm_mux_tgu_ch3___7 = 100,\n\tmsm_mux_tsense_pwm1___13 = 101,\n\tmsm_mux_tsense_pwm2___13 = 102,\n\tmsm_mux_tsif1_clk___3 = 103,\n\tmsm_mux_tsif1_data___3 = 104,\n\tmsm_mux_tsif1_en___3 = 105,\n\tmsm_mux_tsif1_error___3 = 106,\n\tmsm_mux_tsif1_sync___3 = 107,\n\tmsm_mux_tsif2_clk___3 = 108,\n\tmsm_mux_tsif2_data___3 = 109,\n\tmsm_mux_tsif2_en___3 = 110,\n\tmsm_mux_tsif2_error___3 = 111,\n\tmsm_mux_tsif2_sync___3 = 112,\n\tmsm_mux_uim1_clk___9 = 113,\n\tmsm_mux_uim1_data___9 = 114,\n\tmsm_mux_uim1_present___9 = 115,\n\tmsm_mux_uim1_reset___9 = 116,\n\tmsm_mux_uim2_clk___7 = 117,\n\tmsm_mux_uim2_data___7 = 118,\n\tmsm_mux_uim2_present___7 = 119,\n\tmsm_mux_uim2_reset___7 = 120,\n\tmsm_mux_uim_batt___10 = 121,\n\tmsm_mux_usb_phy___8 = 122,\n\tmsm_mux_vfr_1___13 = 123,\n\tmsm_mux_vsense_trigger___10 = 124,\n\tmsm_mux_wlan1_adc0___7 = 125,\n\tmsm_mux_wlan1_adc1___7 = 126,\n\tmsm_mux_wlan2_adc0___6 = 127,\n\tmsm_mux_wlan2_adc1___6 = 128,\n\tmsm_mux_____22 = 129,\n};\n\nenum sdx75_functions {\n\tmsm_mux_adsp_ext___13 = 0,\n\tmsm_mux_atest_char___25 = 1,\n\tmsm_mux_audio_ref_clk___4 = 2,\n\tmsm_mux_bimc_dte = 3,\n\tmsm_mux_char_exec___3 = 4,\n\tmsm_mux_coex_uart2 = 5,\n\tmsm_mux_coex_uart = 6,\n\tmsm_mux_cri_trng___18 = 7,\n\tmsm_mux_cri_trng0___17 = 8,\n\tmsm_mux_cri_trng1___17 = 9,\n\tmsm_mux_dbg_out_clk___5 = 10,\n\tmsm_mux_ddr_bist___16 = 11,\n\tmsm_mux_ddr_pxi0___12 = 12,\n\tmsm_mux_ebi0_wrcdc___2 = 13,\n\tmsm_mux_ebi2_a___2 = 14,\n\tmsm_mux_ebi2_lcd___2 = 15,\n\tmsm_mux_ebi2_lcd_te = 16,\n\tmsm_mux_emac0_mcg = 17,\n\tmsm_mux_emac0_ptp___2 = 18,\n\tmsm_mux_emac1_mcg = 19,\n\tmsm_mux_emac1_ptp___2 = 20,\n\tmsm_mux_emac_cdc = 21,\n\tmsm_mux_emac_pps_in = 22,\n\tmsm_mux_eth0_mdc = 23,\n\tmsm_mux_eth0_mdio = 24,\n\tmsm_mux_eth1_mdc = 25,\n\tmsm_mux_eth1_mdio = 26,\n\tmsm_mux_ext_dbg = 27,\n\tmsm_mux_gcc_125_clk = 28,\n\tmsm_mux_gcc_gp1_clk = 29,\n\tmsm_mux_gcc_gp2_clk = 30,\n\tmsm_mux_gcc_gp3_clk = 31,\n\tmsm_mux_gcc_plltest___9 = 32,\n\tmsm_mux_gpio___28 = 33,\n\tmsm_mux_i2s_mclk = 34,\n\tmsm_mux_jitter_bist___15 = 35,\n\tmsm_mux_ldo_en___12 = 36,\n\tmsm_mux_ldo_update___12 = 37,\n\tmsm_mux_m_voc___14 = 38,\n\tmsm_mux_mgpi_clk = 39,\n\tmsm_mux_native_char = 40,\n\tmsm_mux_native_tsens = 41,\n\tmsm_mux_native_tsense = 42,\n\tmsm_mux_nav_dr_sync = 43,\n\tmsm_mux_nav_gpio___2 = 44,\n\tmsm_mux_pa_indicator___13 = 45,\n\tmsm_mux_pci_e = 46,\n\tmsm_mux_pcie0_clkreq_n = 47,\n\tmsm_mux_pcie1_clkreq_n = 48,\n\tmsm_mux_pcie2_clkreq_n = 49,\n\tmsm_mux_pll_bist_sync___3 = 50,\n\tmsm_mux_pll_clk_aux___3 = 51,\n\tmsm_mux_pll_ref_clk = 52,\n\tmsm_mux_pri_mi2s___12 = 53,\n\tmsm_mux_prng_rosc___18 = 54,\n\tmsm_mux_qdss_cti___15 = 55,\n\tmsm_mux_qdss_gpio___10 = 56,\n\tmsm_mux_qlink0_b_en = 57,\n\tmsm_mux_qlink0_b_req = 58,\n\tmsm_mux_qlink0_l_en = 59,\n\tmsm_mux_qlink0_l_req = 60,\n\tmsm_mux_qlink0_wmss___4 = 61,\n\tmsm_mux_qlink1_l_en = 62,\n\tmsm_mux_qlink1_l_req = 63,\n\tmsm_mux_qlink1_wmss___4 = 64,\n\tmsm_mux_qup_se0 = 65,\n\tmsm_mux_qup_se1_l2_mira = 66,\n\tmsm_mux_qup_se1_l2_mirb = 67,\n\tmsm_mux_qup_se1_l3_mira = 68,\n\tmsm_mux_qup_se1_l3_mirb = 69,\n\tmsm_mux_qup_se2 = 70,\n\tmsm_mux_qup_se3 = 71,\n\tmsm_mux_qup_se4 = 72,\n\tmsm_mux_qup_se5 = 73,\n\tmsm_mux_qup_se6 = 74,\n\tmsm_mux_qup_se7 = 75,\n\tmsm_mux_qup_se8 = 76,\n\tmsm_mux_rgmii_rx_ctl = 77,\n\tmsm_mux_rgmii_rxc = 78,\n\tmsm_mux_rgmii_rxd = 79,\n\tmsm_mux_rgmii_tx_ctl = 80,\n\tmsm_mux_rgmii_txc = 81,\n\tmsm_mux_rgmii_txd = 82,\n\tmsm_mux_sd_card___6 = 83,\n\tmsm_mux_sdc1_tb___3 = 84,\n\tmsm_mux_sdc2_tb_trig = 85,\n\tmsm_mux_sec_mi2s___12 = 86,\n\tmsm_mux_sgmii_phy_intr0_n = 87,\n\tmsm_mux_sgmii_phy_intr1_n = 88,\n\tmsm_mux_spmi_coex = 89,\n\tmsm_mux_spmi_vgi = 90,\n\tmsm_mux_tgu_ch0_trigout___2 = 91,\n\tmsm_mux_tmess_prng0___4 = 92,\n\tmsm_mux_tmess_prng1___4 = 93,\n\tmsm_mux_tmess_prng2___4 = 94,\n\tmsm_mux_tmess_prng3___4 = 95,\n\tmsm_mux_tri_mi2s = 96,\n\tmsm_mux_uim1_clk___10 = 97,\n\tmsm_mux_uim1_data___10 = 98,\n\tmsm_mux_uim1_present___10 = 99,\n\tmsm_mux_uim1_reset___10 = 100,\n\tmsm_mux_uim2_clk___8 = 101,\n\tmsm_mux_uim2_data___8 = 102,\n\tmsm_mux_uim2_present___8 = 103,\n\tmsm_mux_uim2_reset___8 = 104,\n\tmsm_mux_usb2phy_ac_en = 105,\n\tmsm_mux_vsense_trigger_mirnat___4 = 106,\n\tmsm_mux_____23 = 107,\n};\n\nenum sec_device_type {\n\tS5M8767X = 0,\n\tS2DOS05 = 1,\n\tS2MPA01 = 2,\n\tS2MPG10 = 3,\n\tS2MPG11 = 4,\n\tS2MPS11X = 5,\n\tS2MPS13X = 6,\n\tS2MPS14X = 7,\n\tS2MPS15X = 8,\n\tS2MPU02 = 9,\n\tS2MPU05 = 10,\n};\n\nenum serdev_parity {\n\tSERDEV_PARITY_NONE = 0,\n\tSERDEV_PARITY_EVEN = 1,\n\tSERDEV_PARITY_ODD = 2,\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nenum service_response {\n\tSAS_TASK_COMPLETE = 0,\n\tSAS_TASK_UNDELIVERED = -1,\n};\n\nenum set_event_iter_type {\n\tSET_EVENT_FILE = 0,\n\tSET_EVENT_MOD = 1,\n};\n\nenum sgmii_speed {\n\tSGMII_SPEED_10 = 0,\n\tSGMII_SPEED_100 = 1,\n\tSGMII_SPEED_1000 = 2,\n\tSGMII_SPEED_2500 = 2,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum sh_cmt_model {\n\tSH_CMT_16BIT = 0,\n\tSH_CMT_32BIT = 1,\n\tSH_CMT_48BIT = 2,\n\tSH_CMT0_RCAR_GEN2 = 3,\n\tSH_CMT1_RCAR_GEN2 = 4,\n};\n\nenum sh_mobile_i2c_op {\n\tOP_START = 0,\n\tOP_TX_FIRST = 1,\n\tOP_TX = 2,\n\tOP_TX_STOP = 3,\n\tOP_TX_TO_RX = 4,\n\tOP_RX = 5,\n\tOP_RX_STOP = 6,\n\tOP_RX_STOP_DATA = 7,\n};\n\nenum sh_tmu_model {\n\tSH_TMU = 0,\n\tSH_TMU_SH3 = 1,\n};\n\nenum shmem_param {\n\tOpt_gid___9 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___6 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes___2 = 5,\n\tOpt_size___2 = 6,\n\tOpt_uid___8 = 7,\n\tOpt_inode32 = 8,\n\tOpt_inode64 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota___2 = 11,\n\tOpt_usrquota___2 = 12,\n\tOpt_grpquota___2 = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum shutdown_state {\n\tSHUTDOWN_INVALID = -1,\n\tSHUTDOWN_POWEROFF = 0,\n\tSHUTDOWN_SUSPEND = 2,\n\tSHUTDOWN_HALT = 4,\n};\n\nenum si_type {\n\tSI_TYPE_INVALID = 0,\n\tSI_KCS = 1,\n\tSI_SMIC = 2,\n\tSI_BT = 3,\n\tSI_TYPE_MAX = 4,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_ext_id {\n\tSKB_EXT_BRIDGE_NF = 0,\n\tSKB_EXT_CAN = 1,\n\tSKB_EXT_NUM = 2,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN___2 = 0,\n\tPARTIAL = 1,\n\tUP___2 = 2,\n\tFULL = 3,\n};\n\nenum sm4450_functions {\n\tmsm_mux_gpio___29 = 0,\n\tmsm_mux_atest_char___26 = 1,\n\tmsm_mux_atest_usb0___3 = 2,\n\tmsm_mux_audio_ref_clk___5 = 3,\n\tmsm_mux_cam_mclk___18 = 4,\n\tmsm_mux_cci_async_in0___3 = 5,\n\tmsm_mux_cci_i2c___15 = 6,\n\tmsm_mux_cci = 7,\n\tmsm_mux_cmu_rng___4 = 8,\n\tmsm_mux_coex_uart1_rx___3 = 9,\n\tmsm_mux_coex_uart1_tx___3 = 10,\n\tmsm_mux_cri_trng___19 = 11,\n\tmsm_mux_dbg_out_clk___6 = 12,\n\tmsm_mux_ddr_bist___17 = 13,\n\tmsm_mux_ddr_pxi0_test = 14,\n\tmsm_mux_ddr_pxi1_test = 15,\n\tmsm_mux_gcc_gp1_clk___2 = 16,\n\tmsm_mux_gcc_gp2_clk___2 = 17,\n\tmsm_mux_gcc_gp3_clk___2 = 18,\n\tmsm_mux_host2wlan_sol___3 = 19,\n\tmsm_mux_ibi_i3c_qup0 = 20,\n\tmsm_mux_ibi_i3c_qup1 = 21,\n\tmsm_mux_jitter_bist_ref___2 = 22,\n\tmsm_mux_mdp_vsync0_out___4 = 23,\n\tmsm_mux_mdp_vsync1_out___4 = 24,\n\tmsm_mux_mdp_vsync2_out___4 = 25,\n\tmsm_mux_mdp_vsync3_out___4 = 26,\n\tmsm_mux_mdp_vsync___20 = 27,\n\tmsm_mux_nav = 28,\n\tmsm_mux_pcie0_clk_req = 29,\n\tmsm_mux_phase_flag___15 = 30,\n\tmsm_mux_pll_bist_sync___4 = 31,\n\tmsm_mux_pll_clk_aux___4 = 32,\n\tmsm_mux_prng_rosc___19 = 33,\n\tmsm_mux_qdss_cti_trig0 = 34,\n\tmsm_mux_qdss_cti_trig1 = 35,\n\tmsm_mux_qdss_gpio___11 = 36,\n\tmsm_mux_qlink0_enable___4 = 37,\n\tmsm_mux_qlink0_request___4 = 38,\n\tmsm_mux_qlink0_wmss_reset = 39,\n\tmsm_mux_qup0_se0___4 = 40,\n\tmsm_mux_qup0_se1___4 = 41,\n\tmsm_mux_qup0_se2___4 = 42,\n\tmsm_mux_qup0_se3___4 = 43,\n\tmsm_mux_qup0_se4___4 = 44,\n\tmsm_mux_qup1_se0___5 = 45,\n\tmsm_mux_qup1_se1___5 = 46,\n\tmsm_mux_qup1_se2___5 = 47,\n\tmsm_mux_qup1_se3___5 = 48,\n\tmsm_mux_qup1_se4___5 = 49,\n\tmsm_mux_sd_write_protect___4 = 50,\n\tmsm_mux_tb_trig_sdc1___2 = 51,\n\tmsm_mux_tb_trig_sdc2___3 = 52,\n\tmsm_mux_tgu_ch0_trigout___3 = 53,\n\tmsm_mux_tgu_ch1_trigout___2 = 54,\n\tmsm_mux_tgu_ch2_trigout = 55,\n\tmsm_mux_tgu_ch3_trigout = 56,\n\tmsm_mux_tmess_prng = 57,\n\tmsm_mux_tsense_pwm1_out = 58,\n\tmsm_mux_tsense_pwm2_out = 59,\n\tmsm_mux_uim0 = 60,\n\tmsm_mux_uim1___7 = 61,\n\tmsm_mux_usb0_hs_ac = 62,\n\tmsm_mux_usb0_phy_ps___2 = 63,\n\tmsm_mux_vfr_0_mira = 64,\n\tmsm_mux_vfr_0_mirb = 65,\n\tmsm_mux_vfr_1___14 = 66,\n\tmsm_mux_vsense_trigger_mirnat___5 = 67,\n\tmsm_mux_wlan1_adc_dtest0 = 68,\n\tmsm_mux_wlan1_adc_dtest1 = 69,\n\tmsm_mux_____24 = 70,\n};\n\nenum sm6115_functions {\n\tmsm_mux_adsp_ext___14 = 0,\n\tmsm_mux_agera_pll___9 = 1,\n\tmsm_mux_atest___2 = 2,\n\tmsm_mux_cam_mclk___19 = 3,\n\tmsm_mux_cci_async___16 = 4,\n\tmsm_mux_cci_i2c___16 = 5,\n\tmsm_mux_cci_timer___5 = 6,\n\tmsm_mux_cri_trng___20 = 7,\n\tmsm_mux_dac_calib___2 = 8,\n\tmsm_mux_dbg_out___22 = 9,\n\tmsm_mux_ddr_bist___18 = 10,\n\tmsm_mux_ddr_pxi0___13 = 11,\n\tmsm_mux_ddr_pxi1___12 = 12,\n\tmsm_mux_ddr_pxi2___10 = 13,\n\tmsm_mux_ddr_pxi3___10 = 14,\n\tmsm_mux_gcc_gp1___14 = 15,\n\tmsm_mux_gcc_gp2___14 = 16,\n\tmsm_mux_gcc_gp3___14 = 17,\n\tmsm_mux_gpio___30 = 18,\n\tmsm_mux_gp_pdm0___5 = 19,\n\tmsm_mux_gp_pdm1___5 = 20,\n\tmsm_mux_gp_pdm2___5 = 21,\n\tmsm_mux_gsm0_tx___4 = 22,\n\tmsm_mux_gsm1_tx___4 = 23,\n\tmsm_mux_jitter_bist___16 = 24,\n\tmsm_mux_mdp_vsync___21 = 25,\n\tmsm_mux_mdp_vsync_out_0___2 = 26,\n\tmsm_mux_mdp_vsync_out_1___2 = 27,\n\tmsm_mux_mpm_pwr___2 = 28,\n\tmsm_mux_mss_lte___12 = 29,\n\tmsm_mux_m_voc___15 = 30,\n\tmsm_mux_nav_gpio___3 = 31,\n\tmsm_mux_pa_indicator___14 = 32,\n\tmsm_mux_pbs = 33,\n\tmsm_mux_pbs_out___2 = 34,\n\tmsm_mux_phase_flag___16 = 35,\n\tmsm_mux_pll_bist___12 = 36,\n\tmsm_mux_pll_bypassnl___11 = 37,\n\tmsm_mux_pll_reset___10 = 38,\n\tmsm_mux_prng_rosc___20 = 39,\n\tmsm_mux_qdss_cti___16 = 40,\n\tmsm_mux_qdss_gpio___12 = 41,\n\tmsm_mux_qup0___7 = 42,\n\tmsm_mux_qup1___7 = 43,\n\tmsm_mux_qup2___6 = 44,\n\tmsm_mux_qup3___6 = 45,\n\tmsm_mux_qup4___6 = 46,\n\tmsm_mux_qup5___6 = 47,\n\tmsm_mux_sdc1_tb___4 = 48,\n\tmsm_mux_sdc2_tb___3 = 49,\n\tmsm_mux_sd_write___16 = 50,\n\tmsm_mux_ssbi_wtr1___5 = 51,\n\tmsm_mux_tgu___3 = 52,\n\tmsm_mux_tsense_pwm___2 = 53,\n\tmsm_mux_uim1_clk___11 = 54,\n\tmsm_mux_uim1_data___11 = 55,\n\tmsm_mux_uim1_present___11 = 56,\n\tmsm_mux_uim1_reset___11 = 57,\n\tmsm_mux_uim2_clk___9 = 58,\n\tmsm_mux_uim2_data___9 = 59,\n\tmsm_mux_uim2_present___9 = 60,\n\tmsm_mux_uim2_reset___9 = 61,\n\tmsm_mux_usb_phy___9 = 62,\n\tmsm_mux_vfr_1___15 = 63,\n\tmsm_mux_vsense_trigger___11 = 64,\n\tmsm_mux_wlan1_adc0___8 = 65,\n\tmsm_mux_wlan1_adc1___8 = 66,\n\tmsm_mux_____25 = 67,\n};\n\nenum sm6125_functions {\n\tmsm_mux_qup00___4 = 0,\n\tmsm_mux_gpio___31 = 1,\n\tmsm_mux_qdss___6 = 2,\n\tmsm_mux_qup01___4 = 3,\n\tmsm_mux_qup02___3 = 4,\n\tmsm_mux_ddr_pxi0___14 = 5,\n\tmsm_mux_ddr_bist___19 = 6,\n\tmsm_mux_atest_tsens2___8 = 7,\n\tmsm_mux_vsense_trigger___12 = 8,\n\tmsm_mux_atest_usb1___9 = 9,\n\tmsm_mux_gp_pdm1___6 = 10,\n\tmsm_mux_phase_flag___17 = 11,\n\tmsm_mux_dbg_out___23 = 12,\n\tmsm_mux_qup14___8 = 13,\n\tmsm_mux_atest_usb11___8 = 14,\n\tmsm_mux_ddr_pxi2___11 = 15,\n\tmsm_mux_atest_usb10___8 = 16,\n\tmsm_mux_jitter_bist___17 = 17,\n\tmsm_mux_ddr_pxi3___11 = 18,\n\tmsm_mux_pll_bypassnl___12 = 19,\n\tmsm_mux_pll_bist___13 = 20,\n\tmsm_mux_qup03___4 = 21,\n\tmsm_mux_pll_reset___11 = 22,\n\tmsm_mux_agera_pll___10 = 23,\n\tmsm_mux_qdss_cti___17 = 24,\n\tmsm_mux_qup04___3 = 25,\n\tmsm_mux_wlan2_adc1___7 = 26,\n\tmsm_mux_wlan2_adc0___7 = 27,\n\tmsm_mux_wsa_clk___3 = 28,\n\tmsm_mux_qup13___7 = 29,\n\tmsm_mux_ter_mi2s___8 = 30,\n\tmsm_mux_wsa_data___3 = 31,\n\tmsm_mux_qup10___8 = 32,\n\tmsm_mux_gcc_gp3___15 = 33,\n\tmsm_mux_qup12___8 = 34,\n\tmsm_mux_sd_write___17 = 35,\n\tmsm_mux_qup11___7 = 36,\n\tmsm_mux_cam_mclk___20 = 37,\n\tmsm_mux_atest_tsens___11 = 38,\n\tmsm_mux_cci_i2c___17 = 39,\n\tmsm_mux_cci_timer2___14 = 40,\n\tmsm_mux_cci_timer1___14 = 41,\n\tmsm_mux_gcc_gp2___15 = 42,\n\tmsm_mux_cci_async___17 = 43,\n\tmsm_mux_cci_timer4___12 = 44,\n\tmsm_mux_cci_timer0___14 = 45,\n\tmsm_mux_gcc_gp1___15 = 46,\n\tmsm_mux_cci_timer3___13 = 47,\n\tmsm_mux_wlan1_adc1___9 = 48,\n\tmsm_mux_wlan1_adc0___9 = 49,\n\tmsm_mux_qlink_request___7 = 50,\n\tmsm_mux_qlink_enable___7 = 51,\n\tmsm_mux_pa_indicator___15 = 52,\n\tmsm_mux_nav_pps___9 = 53,\n\tmsm_mux_gps_tx___5 = 54,\n\tmsm_mux_gp_pdm0___6 = 55,\n\tmsm_mux_atest_usb13___8 = 56,\n\tmsm_mux_ddr_pxi1___13 = 57,\n\tmsm_mux_atest_usb12___8 = 58,\n\tmsm_mux_cri_trng0___18 = 59,\n\tmsm_mux_cri_trng___21 = 60,\n\tmsm_mux_cri_trng1___18 = 61,\n\tmsm_mux_gp_pdm2___6 = 62,\n\tmsm_mux_sp_cmu___7 = 63,\n\tmsm_mux_atest_usb2___9 = 64,\n\tmsm_mux_atest_usb23___6 = 65,\n\tmsm_mux_uim2_data___10 = 66,\n\tmsm_mux_uim2_clk___10 = 67,\n\tmsm_mux_uim2_reset___10 = 68,\n\tmsm_mux_atest_usb22___6 = 69,\n\tmsm_mux_uim2_present___10 = 70,\n\tmsm_mux_atest_usb21___6 = 71,\n\tmsm_mux_uim1_data___12 = 72,\n\tmsm_mux_atest_usb20___6 = 73,\n\tmsm_mux_uim1_clk___12 = 74,\n\tmsm_mux_uim1_reset___12 = 75,\n\tmsm_mux_uim1_present___12 = 76,\n\tmsm_mux_mdp_vsync___22 = 77,\n\tmsm_mux_copy_gp___3 = 78,\n\tmsm_mux_tsense_pwm___3 = 79,\n\tmsm_mux_mpm_pwr___3 = 80,\n\tmsm_mux_tgu_ch3___8 = 81,\n\tmsm_mux_mdp_vsync0___7 = 82,\n\tmsm_mux_mdp_vsync1___7 = 83,\n\tmsm_mux_mdp_vsync2___7 = 84,\n\tmsm_mux_mdp_vsync3___7 = 85,\n\tmsm_mux_mdp_vsync4___3 = 86,\n\tmsm_mux_mdp_vsync5___3 = 87,\n\tmsm_mux_tgu_ch0___11 = 88,\n\tmsm_mux_tgu_ch1___11 = 89,\n\tmsm_mux_atest_char1___13 = 90,\n\tmsm_mux_vfr_1___16 = 91,\n\tmsm_mux_tgu_ch2___8 = 92,\n\tmsm_mux_atest_char0___13 = 93,\n\tmsm_mux_atest_char2___13 = 94,\n\tmsm_mux_atest_char3___13 = 95,\n\tmsm_mux_ldo_en___13 = 96,\n\tmsm_mux_ldo_update___13 = 97,\n\tmsm_mux_prng_rosc___21 = 98,\n\tmsm_mux_dp_hot___6 = 99,\n\tmsm_mux_debug_hot___2 = 100,\n\tmsm_mux_copy_phase___3 = 101,\n\tmsm_mux_usb_phy___10 = 102,\n\tmsm_mux_atest_char___27 = 103,\n\tmsm_mux_unused1 = 104,\n\tmsm_mux_qua_mi2s___7 = 105,\n\tmsm_mux_mss_lte___13 = 106,\n\tmsm_mux_swr_tx = 107,\n\tmsm_mux_aud_sb = 108,\n\tmsm_mux_unused2 = 109,\n\tmsm_mux_swr_rx = 110,\n\tmsm_mux_edp_hot___9 = 111,\n\tmsm_mux_audio_ref___11 = 112,\n\tmsm_mux_pri_mi2s___13 = 113,\n\tmsm_mux_pri_mi2s_ws___8 = 114,\n\tmsm_mux_adsp_ext___15 = 115,\n\tmsm_mux_edp_lcd___9 = 116,\n\tmsm_mux_mclk2___2 = 117,\n\tmsm_mux_m_voc___16 = 118,\n\tmsm_mux_mclk1___2 = 119,\n\tmsm_mux_qca_sb = 120,\n\tmsm_mux_qui_mi2s = 121,\n\tmsm_mux_dmic0_clk___4 = 122,\n\tmsm_mux_sec_mi2s___13 = 123,\n\tmsm_mux_dmic0_data___4 = 124,\n\tmsm_mux_dmic1_clk = 125,\n\tmsm_mux_dmic1_data = 126,\n\tmsm_mux_____26 = 127,\n};\n\nenum sm6350_functions {\n\tmsm_mux_adsp_ext___16 = 0,\n\tmsm_mux_agera_pll___11 = 1,\n\tmsm_mux_atest_char___28 = 2,\n\tmsm_mux_atest_char0___14 = 3,\n\tmsm_mux_atest_char1___14 = 4,\n\tmsm_mux_atest_char2___14 = 5,\n\tmsm_mux_atest_char3___14 = 6,\n\tmsm_mux_atest_tsens___12 = 7,\n\tmsm_mux_atest_tsens2___9 = 8,\n\tmsm_mux_atest_usb___6 = 9,\n\tmsm_mux_audio_ref___12 = 10,\n\tmsm_mux_btfm_slimbus___6 = 11,\n\tmsm_mux_cam_mclk0___3 = 12,\n\tmsm_mux_cam_mclk1___3 = 13,\n\tmsm_mux_cam_mclk2___2 = 14,\n\tmsm_mux_cam_mclk3___2 = 15,\n\tmsm_mux_cam_mclk4 = 16,\n\tmsm_mux_cci_async___18 = 17,\n\tmsm_mux_cci_i2c___18 = 18,\n\tmsm_mux_cci_timer0___15 = 19,\n\tmsm_mux_cci_timer1___15 = 20,\n\tmsm_mux_cci_timer2___15 = 21,\n\tmsm_mux_cci_timer3___14 = 22,\n\tmsm_mux_cci_timer4___13 = 23,\n\tmsm_mux_cri_trng___22 = 24,\n\tmsm_mux_dbg_out___24 = 25,\n\tmsm_mux_ddr_bist___20 = 26,\n\tmsm_mux_ddr_pxi0___15 = 27,\n\tmsm_mux_ddr_pxi1___14 = 28,\n\tmsm_mux_ddr_pxi2___12 = 29,\n\tmsm_mux_ddr_pxi3___12 = 30,\n\tmsm_mux_dp_hot___7 = 31,\n\tmsm_mux_edp_lcd___10 = 32,\n\tmsm_mux_gcc_gp1___16 = 33,\n\tmsm_mux_gcc_gp2___16 = 34,\n\tmsm_mux_gcc_gp3___16 = 35,\n\tmsm_mux_gp_pdm0___7 = 36,\n\tmsm_mux_gp_pdm1___7 = 37,\n\tmsm_mux_gp_pdm2___7 = 38,\n\tmsm_mux_gpio___32 = 39,\n\tmsm_mux_gps_tx___6 = 40,\n\tmsm_mux_ibi_i3c___7 = 41,\n\tmsm_mux_jitter_bist___18 = 42,\n\tmsm_mux_ldo_en___14 = 43,\n\tmsm_mux_ldo_update___14 = 44,\n\tmsm_mux_lpass_ext___2 = 45,\n\tmsm_mux_m_voc___17 = 46,\n\tmsm_mux_mclk = 47,\n\tmsm_mux_mdp_vsync___23 = 48,\n\tmsm_mux_mdp_vsync0___8 = 49,\n\tmsm_mux_mdp_vsync1___8 = 50,\n\tmsm_mux_mdp_vsync2___8 = 51,\n\tmsm_mux_mdp_vsync3___8 = 52,\n\tmsm_mux_mi2s_0___2 = 53,\n\tmsm_mux_mi2s_1___3 = 54,\n\tmsm_mux_mi2s_2___2 = 55,\n\tmsm_mux_mss_lte___14 = 56,\n\tmsm_mux_nav_gpio___4 = 57,\n\tmsm_mux_nav_pps___10 = 58,\n\tmsm_mux_pa_indicator___16 = 59,\n\tmsm_mux_pcie0_clk___7 = 60,\n\tmsm_mux_phase_flag___18 = 61,\n\tmsm_mux_pll_bist___14 = 62,\n\tmsm_mux_pll_bypassnl___13 = 63,\n\tmsm_mux_pll_reset___12 = 64,\n\tmsm_mux_prng_rosc___22 = 65,\n\tmsm_mux_qdss_cti___18 = 66,\n\tmsm_mux_qdss_gpio___13 = 67,\n\tmsm_mux_qdss_gpio0___2 = 68,\n\tmsm_mux_qdss_gpio1___2 = 69,\n\tmsm_mux_qdss_gpio10___2 = 70,\n\tmsm_mux_qdss_gpio11___2 = 71,\n\tmsm_mux_qdss_gpio12___2 = 72,\n\tmsm_mux_qdss_gpio13___2 = 73,\n\tmsm_mux_qdss_gpio14___2 = 74,\n\tmsm_mux_qdss_gpio15___2 = 75,\n\tmsm_mux_qdss_gpio2___2 = 76,\n\tmsm_mux_qdss_gpio3___2 = 77,\n\tmsm_mux_qdss_gpio4___2 = 78,\n\tmsm_mux_qdss_gpio5___2 = 79,\n\tmsm_mux_qdss_gpio6___2 = 80,\n\tmsm_mux_qdss_gpio7___2 = 81,\n\tmsm_mux_qdss_gpio8___2 = 82,\n\tmsm_mux_qdss_gpio9___2 = 83,\n\tmsm_mux_qlink0_enable___5 = 84,\n\tmsm_mux_qlink0_request___5 = 85,\n\tmsm_mux_qlink0_wmss___5 = 86,\n\tmsm_mux_qlink1_enable___4 = 87,\n\tmsm_mux_qlink1_request___4 = 88,\n\tmsm_mux_qlink1_wmss___5 = 89,\n\tmsm_mux_qup00___5 = 90,\n\tmsm_mux_qup01___5 = 91,\n\tmsm_mux_qup02___4 = 92,\n\tmsm_mux_qup10___9 = 93,\n\tmsm_mux_qup11___8 = 94,\n\tmsm_mux_qup12___9 = 95,\n\tmsm_mux_qup13_f1 = 96,\n\tmsm_mux_qup13_f2 = 97,\n\tmsm_mux_qup14___9 = 98,\n\tmsm_mux_rffe0_clk = 99,\n\tmsm_mux_rffe0_data = 100,\n\tmsm_mux_rffe1_clk = 101,\n\tmsm_mux_rffe1_data = 102,\n\tmsm_mux_rffe2_clk = 103,\n\tmsm_mux_rffe2_data = 104,\n\tmsm_mux_rffe3_clk = 105,\n\tmsm_mux_rffe3_data = 106,\n\tmsm_mux_rffe4_clk = 107,\n\tmsm_mux_rffe4_data = 108,\n\tmsm_mux_sd_write___18 = 109,\n\tmsm_mux_sdc1_tb___5 = 110,\n\tmsm_mux_sdc2_tb___4 = 111,\n\tmsm_mux_sp_cmu___8 = 112,\n\tmsm_mux_tgu_ch0___12 = 113,\n\tmsm_mux_tgu_ch1___12 = 114,\n\tmsm_mux_tgu_ch2___9 = 115,\n\tmsm_mux_tgu_ch3___9 = 116,\n\tmsm_mux_tsense_pwm1___14 = 117,\n\tmsm_mux_tsense_pwm2___14 = 118,\n\tmsm_mux_uim1_clk___13 = 119,\n\tmsm_mux_uim1_data___13 = 120,\n\tmsm_mux_uim1_present___13 = 121,\n\tmsm_mux_uim1_reset___13 = 122,\n\tmsm_mux_uim2_clk___11 = 123,\n\tmsm_mux_uim2_data___11 = 124,\n\tmsm_mux_uim2_present___11 = 125,\n\tmsm_mux_uim2_reset___11 = 126,\n\tmsm_mux_usb_phy___11 = 127,\n\tmsm_mux_vfr_1___17 = 128,\n\tmsm_mux_vsense_trigger___13 = 129,\n\tmsm_mux_wlan1_adc0___10 = 130,\n\tmsm_mux_wlan1_adc1___10 = 131,\n\tmsm_mux_wlan2_adc0___8 = 132,\n\tmsm_mux_wlan2_adc1___8 = 133,\n\tmsm_mux_____27 = 134,\n};\n\nenum sm6375_functions {\n\tmsm_mux_adsp_ext___17 = 0,\n\tmsm_mux_agera_pll___12 = 1,\n\tmsm_mux_atest_char___29 = 2,\n\tmsm_mux_atest_char0___15 = 3,\n\tmsm_mux_atest_char1___15 = 4,\n\tmsm_mux_atest_char2___15 = 5,\n\tmsm_mux_atest_char3___15 = 6,\n\tmsm_mux_atest_tsens___13 = 7,\n\tmsm_mux_atest_tsens2___10 = 8,\n\tmsm_mux_atest_usb1___10 = 9,\n\tmsm_mux_atest_usb10___9 = 10,\n\tmsm_mux_atest_usb11___9 = 11,\n\tmsm_mux_atest_usb12___9 = 12,\n\tmsm_mux_atest_usb13___9 = 13,\n\tmsm_mux_atest_usb2___10 = 14,\n\tmsm_mux_atest_usb20___7 = 15,\n\tmsm_mux_atest_usb21___7 = 16,\n\tmsm_mux_atest_usb22___7 = 17,\n\tmsm_mux_atest_usb23___7 = 18,\n\tmsm_mux_audio_ref___13 = 19,\n\tmsm_mux_btfm_slimbus___7 = 20,\n\tmsm_mux_cam_mclk___21 = 21,\n\tmsm_mux_cci_async___19 = 22,\n\tmsm_mux_cci_i2c___19 = 23,\n\tmsm_mux_cci_timer0___16 = 24,\n\tmsm_mux_cci_timer1___16 = 25,\n\tmsm_mux_cci_timer2___16 = 26,\n\tmsm_mux_cci_timer3___15 = 27,\n\tmsm_mux_cci_timer4___14 = 28,\n\tmsm_mux_cri_trng___23 = 29,\n\tmsm_mux_dbg_out___25 = 30,\n\tmsm_mux_ddr_bist___21 = 31,\n\tmsm_mux_ddr_pxi0___16 = 32,\n\tmsm_mux_ddr_pxi1___15 = 33,\n\tmsm_mux_ddr_pxi2___13 = 34,\n\tmsm_mux_ddr_pxi3___13 = 35,\n\tmsm_mux_dp_hot___8 = 36,\n\tmsm_mux_edp_lcd___11 = 37,\n\tmsm_mux_gcc_gp1___17 = 38,\n\tmsm_mux_gcc_gp2___17 = 39,\n\tmsm_mux_gcc_gp3___17 = 40,\n\tmsm_mux_gp_pdm0___8 = 41,\n\tmsm_mux_gp_pdm1___8 = 42,\n\tmsm_mux_gp_pdm2___8 = 43,\n\tmsm_mux_gpio___33 = 44,\n\tmsm_mux_gps_tx___7 = 45,\n\tmsm_mux_ibi_i3c___8 = 46,\n\tmsm_mux_jitter_bist___19 = 47,\n\tmsm_mux_ldo_en___15 = 48,\n\tmsm_mux_ldo_update___15 = 49,\n\tmsm_mux_lpass_ext___3 = 50,\n\tmsm_mux_m_voc___18 = 51,\n\tmsm_mux_mclk___2 = 52,\n\tmsm_mux_mdp_vsync___24 = 53,\n\tmsm_mux_mdp_vsync0___9 = 54,\n\tmsm_mux_mdp_vsync1___9 = 55,\n\tmsm_mux_mdp_vsync2___9 = 56,\n\tmsm_mux_mdp_vsync3___9 = 57,\n\tmsm_mux_mi2s_0___3 = 58,\n\tmsm_mux_mi2s_1___4 = 59,\n\tmsm_mux_mi2s_2___3 = 60,\n\tmsm_mux_mss_lte___15 = 61,\n\tmsm_mux_nav_gpio___5 = 62,\n\tmsm_mux_nav_pps___11 = 63,\n\tmsm_mux_pa_indicator___17 = 64,\n\tmsm_mux_phase_flag0___2 = 65,\n\tmsm_mux_phase_flag1___2 = 66,\n\tmsm_mux_phase_flag10___2 = 67,\n\tmsm_mux_phase_flag11___2 = 68,\n\tmsm_mux_phase_flag12___2 = 69,\n\tmsm_mux_phase_flag13___2 = 70,\n\tmsm_mux_phase_flag14___2 = 71,\n\tmsm_mux_phase_flag15___2 = 72,\n\tmsm_mux_phase_flag16___2 = 73,\n\tmsm_mux_phase_flag17___2 = 74,\n\tmsm_mux_phase_flag18___2 = 75,\n\tmsm_mux_phase_flag19___2 = 76,\n\tmsm_mux_phase_flag2___2 = 77,\n\tmsm_mux_phase_flag20___2 = 78,\n\tmsm_mux_phase_flag21___2 = 79,\n\tmsm_mux_phase_flag22___2 = 80,\n\tmsm_mux_phase_flag23___2 = 81,\n\tmsm_mux_phase_flag24___2 = 82,\n\tmsm_mux_phase_flag25___2 = 83,\n\tmsm_mux_phase_flag26___2 = 84,\n\tmsm_mux_phase_flag27___2 = 85,\n\tmsm_mux_phase_flag28___2 = 86,\n\tmsm_mux_phase_flag29___2 = 87,\n\tmsm_mux_phase_flag3___2 = 88,\n\tmsm_mux_phase_flag30___2 = 89,\n\tmsm_mux_phase_flag31___2 = 90,\n\tmsm_mux_phase_flag4___2 = 91,\n\tmsm_mux_phase_flag5___2 = 92,\n\tmsm_mux_phase_flag6___2 = 93,\n\tmsm_mux_phase_flag7___2 = 94,\n\tmsm_mux_phase_flag8___2 = 95,\n\tmsm_mux_phase_flag9___2 = 96,\n\tmsm_mux_pll_bist___15 = 97,\n\tmsm_mux_pll_bypassnl___14 = 98,\n\tmsm_mux_pll_clk___6 = 99,\n\tmsm_mux_pll_reset___13 = 100,\n\tmsm_mux_prng_rosc0___9 = 101,\n\tmsm_mux_prng_rosc1___9 = 102,\n\tmsm_mux_prng_rosc2___9 = 103,\n\tmsm_mux_prng_rosc3___9 = 104,\n\tmsm_mux_qdss_cti___19 = 105,\n\tmsm_mux_qdss_gpio___14 = 106,\n\tmsm_mux_qdss_gpio0___3 = 107,\n\tmsm_mux_qdss_gpio1___3 = 108,\n\tmsm_mux_qdss_gpio10___3 = 109,\n\tmsm_mux_qdss_gpio11___3 = 110,\n\tmsm_mux_qdss_gpio12___3 = 111,\n\tmsm_mux_qdss_gpio13___3 = 112,\n\tmsm_mux_qdss_gpio14___3 = 113,\n\tmsm_mux_qdss_gpio15___3 = 114,\n\tmsm_mux_qdss_gpio2___3 = 115,\n\tmsm_mux_qdss_gpio3___3 = 116,\n\tmsm_mux_qdss_gpio4___3 = 117,\n\tmsm_mux_qdss_gpio5___3 = 118,\n\tmsm_mux_qdss_gpio6___3 = 119,\n\tmsm_mux_qdss_gpio7___3 = 120,\n\tmsm_mux_qdss_gpio8___3 = 121,\n\tmsm_mux_qdss_gpio9___3 = 122,\n\tmsm_mux_qlink0_enable___6 = 123,\n\tmsm_mux_qlink0_request___6 = 124,\n\tmsm_mux_qlink0_wmss___6 = 125,\n\tmsm_mux_qlink1_enable___5 = 126,\n\tmsm_mux_qlink1_request___5 = 127,\n\tmsm_mux_qlink1_wmss___6 = 128,\n\tmsm_mux_qup00___6 = 129,\n\tmsm_mux_qup01___6 = 130,\n\tmsm_mux_qup02___5 = 131,\n\tmsm_mux_qup10___10 = 132,\n\tmsm_mux_qup11_f1 = 133,\n\tmsm_mux_qup11_f2 = 134,\n\tmsm_mux_qup12___10 = 135,\n\tmsm_mux_qup13_f1___2 = 136,\n\tmsm_mux_qup13_f2___2 = 137,\n\tmsm_mux_qup14___10 = 138,\n\tmsm_mux_sd_write___19 = 139,\n\tmsm_mux_sdc1_tb___6 = 140,\n\tmsm_mux_sdc2_tb___5 = 141,\n\tmsm_mux_sp_cmu___9 = 142,\n\tmsm_mux_tgu_ch0___13 = 143,\n\tmsm_mux_tgu_ch1___13 = 144,\n\tmsm_mux_tgu_ch2___10 = 145,\n\tmsm_mux_tgu_ch3___10 = 146,\n\tmsm_mux_tsense_pwm1___15 = 147,\n\tmsm_mux_tsense_pwm2___15 = 148,\n\tmsm_mux_uim1_clk___14 = 149,\n\tmsm_mux_uim1_data___14 = 150,\n\tmsm_mux_uim1_present___14 = 151,\n\tmsm_mux_uim1_reset___14 = 152,\n\tmsm_mux_uim2_clk___12 = 153,\n\tmsm_mux_uim2_data___12 = 154,\n\tmsm_mux_uim2_present___12 = 155,\n\tmsm_mux_uim2_reset___12 = 156,\n\tmsm_mux_usb2phy_ac___7 = 157,\n\tmsm_mux_usb_phy___12 = 158,\n\tmsm_mux_vfr_1___18 = 159,\n\tmsm_mux_vsense_trigger___14 = 160,\n\tmsm_mux_wlan1_adc0___11 = 161,\n\tmsm_mux_wlan1_adc1___11 = 162,\n\tmsm_mux_wlan2_adc0___9 = 163,\n\tmsm_mux_wlan2_adc1___9 = 164,\n\tmsm_mux_____28 = 165,\n};\n\nenum sm8150_functions {\n\tmsm_mux_adsp_ext___18 = 0,\n\tmsm_mux_agera_pll___13 = 1,\n\tmsm_mux_aoss_cti___7 = 2,\n\tmsm_mux_atest_char___30 = 3,\n\tmsm_mux_atest_char0___16 = 4,\n\tmsm_mux_atest_char1___16 = 5,\n\tmsm_mux_atest_char2___16 = 6,\n\tmsm_mux_atest_char3___16 = 7,\n\tmsm_mux_atest_usb1___11 = 8,\n\tmsm_mux_atest_usb2___11 = 9,\n\tmsm_mux_atest_usb10___10 = 10,\n\tmsm_mux_atest_usb11___10 = 11,\n\tmsm_mux_atest_usb12___10 = 12,\n\tmsm_mux_atest_usb13___10 = 13,\n\tmsm_mux_atest_usb20___8 = 14,\n\tmsm_mux_atest_usb21___8 = 15,\n\tmsm_mux_atest_usb22___8 = 16,\n\tmsm_mux_atest_usb23___8 = 17,\n\tmsm_mux_audio_ref___14 = 18,\n\tmsm_mux_btfm_slimbus___8 = 19,\n\tmsm_mux_cam_mclk___22 = 20,\n\tmsm_mux_cci_async___20 = 21,\n\tmsm_mux_cci_i2c___20 = 22,\n\tmsm_mux_cci_timer0___17 = 23,\n\tmsm_mux_cci_timer1___17 = 24,\n\tmsm_mux_cci_timer2___17 = 25,\n\tmsm_mux_cci_timer3___16 = 26,\n\tmsm_mux_cci_timer4___15 = 27,\n\tmsm_mux_cri_trng___24 = 28,\n\tmsm_mux_cri_trng0___19 = 29,\n\tmsm_mux_cri_trng1___19 = 30,\n\tmsm_mux_dbg_out___26 = 31,\n\tmsm_mux_ddr_bist___22 = 32,\n\tmsm_mux_ddr_pxi0___17 = 33,\n\tmsm_mux_ddr_pxi1___16 = 34,\n\tmsm_mux_ddr_pxi2___14 = 35,\n\tmsm_mux_ddr_pxi3___14 = 36,\n\tmsm_mux_edp_hot___10 = 37,\n\tmsm_mux_edp_lcd___12 = 38,\n\tmsm_mux_emac_phy___2 = 39,\n\tmsm_mux_emac_pps___2 = 40,\n\tmsm_mux_gcc_gp1___18 = 41,\n\tmsm_mux_gcc_gp2___18 = 42,\n\tmsm_mux_gcc_gp3___18 = 43,\n\tmsm_mux_gpio___34 = 44,\n\tmsm_mux_jitter_bist___20 = 45,\n\tmsm_mux_hs1_mi2s___6 = 46,\n\tmsm_mux_hs2_mi2s___5 = 47,\n\tmsm_mux_hs3_mi2s___3 = 48,\n\tmsm_mux_lpass_slimbus___10 = 49,\n\tmsm_mux_mdp_vsync___25 = 50,\n\tmsm_mux_mdp_vsync0___10 = 51,\n\tmsm_mux_mdp_vsync1___10 = 52,\n\tmsm_mux_mdp_vsync2___10 = 53,\n\tmsm_mux_mdp_vsync3___10 = 54,\n\tmsm_mux_mss_lte___16 = 55,\n\tmsm_mux_m_voc___19 = 56,\n\tmsm_mux_nav_pps___12 = 57,\n\tmsm_mux_pa_indicator___18 = 58,\n\tmsm_mux_pci_e0___7 = 59,\n\tmsm_mux_pci_e1___6 = 60,\n\tmsm_mux_phase_flag___19 = 61,\n\tmsm_mux_pll_bist___16 = 62,\n\tmsm_mux_pll_bypassnl___15 = 63,\n\tmsm_mux_pll_reset___14 = 64,\n\tmsm_mux_pri_mi2s___14 = 65,\n\tmsm_mux_pri_mi2s_ws___9 = 66,\n\tmsm_mux_prng_rosc___23 = 67,\n\tmsm_mux_qdss___7 = 68,\n\tmsm_mux_qdss_cti___20 = 69,\n\tmsm_mux_qlink_enable___8 = 70,\n\tmsm_mux_qlink_request___8 = 71,\n\tmsm_mux_qspi0___6 = 72,\n\tmsm_mux_qspi1___5 = 73,\n\tmsm_mux_qspi2___4 = 74,\n\tmsm_mux_qspi3___4 = 75,\n\tmsm_mux_qspi_clk___13 = 76,\n\tmsm_mux_qspi_cs___13 = 77,\n\tmsm_mux_qua_mi2s___8 = 78,\n\tmsm_mux_qup0___8 = 79,\n\tmsm_mux_qup1___8 = 80,\n\tmsm_mux_qup2___7 = 81,\n\tmsm_mux_qup3___7 = 82,\n\tmsm_mux_qup4___7 = 83,\n\tmsm_mux_qup5___7 = 84,\n\tmsm_mux_qup6___5 = 85,\n\tmsm_mux_qup7___5 = 86,\n\tmsm_mux_qup8___5 = 87,\n\tmsm_mux_qup9___5 = 88,\n\tmsm_mux_qup10___11 = 89,\n\tmsm_mux_qup11___9 = 90,\n\tmsm_mux_qup12___11 = 91,\n\tmsm_mux_qup13___8 = 92,\n\tmsm_mux_qup14___11 = 93,\n\tmsm_mux_qup15___8 = 94,\n\tmsm_mux_qup16___5 = 95,\n\tmsm_mux_qup17___5 = 96,\n\tmsm_mux_qup18___3 = 97,\n\tmsm_mux_qup19___3 = 98,\n\tmsm_mux_qup_l4___4 = 99,\n\tmsm_mux_qup_l5___4 = 100,\n\tmsm_mux_qup_l6___4 = 101,\n\tmsm_mux_rgmii___3 = 102,\n\tmsm_mux_sdc4___3 = 103,\n\tmsm_mux_sd_write___20 = 104,\n\tmsm_mux_sec_mi2s___14 = 105,\n\tmsm_mux_spkr_i2s___6 = 106,\n\tmsm_mux_sp_cmu___10 = 107,\n\tmsm_mux_ter_mi2s___9 = 108,\n\tmsm_mux_tgu_ch0___14 = 109,\n\tmsm_mux_tgu_ch2___11 = 110,\n\tmsm_mux_tgu_ch1___14 = 111,\n\tmsm_mux_tgu_ch3___11 = 112,\n\tmsm_mux_tsense_pwm1___16 = 113,\n\tmsm_mux_tsense_pwm2___16 = 114,\n\tmsm_mux_tsif1___4 = 115,\n\tmsm_mux_tsif2___3 = 116,\n\tmsm_mux_uim1___8 = 117,\n\tmsm_mux_uim2___7 = 118,\n\tmsm_mux_uim_batt___11 = 119,\n\tmsm_mux_usb2phy_ac___8 = 120,\n\tmsm_mux_usb_phy___13 = 121,\n\tmsm_mux_vfr_1___19 = 122,\n\tmsm_mux_vsense_trigger___15 = 123,\n\tmsm_mux_wlan1_adc1___12 = 124,\n\tmsm_mux_wlan1_adc0___12 = 125,\n\tmsm_mux_wlan2_adc1___10 = 126,\n\tmsm_mux_wlan2_adc0___10 = 127,\n\tmsm_mux_wmss_reset___2 = 128,\n\tmsm_mux_____29 = 129,\n};\n\nenum sm8250_functions {\n\tmsm_mux_aoss_cti___8 = 0,\n\tmsm_mux_atest___3 = 1,\n\tmsm_mux_audio_ref___15 = 2,\n\tmsm_mux_cam_mclk___23 = 3,\n\tmsm_mux_cci_async___21 = 4,\n\tmsm_mux_cci_i2c___21 = 5,\n\tmsm_mux_cci_timer0___18 = 6,\n\tmsm_mux_cci_timer1___18 = 7,\n\tmsm_mux_cci_timer2___18 = 8,\n\tmsm_mux_cci_timer3___17 = 9,\n\tmsm_mux_cci_timer4___16 = 10,\n\tmsm_mux_cri_trng___25 = 11,\n\tmsm_mux_cri_trng0___20 = 12,\n\tmsm_mux_cri_trng1___20 = 13,\n\tmsm_mux_dbg_out___27 = 14,\n\tmsm_mux_ddr_bist___23 = 15,\n\tmsm_mux_ddr_pxi0___18 = 16,\n\tmsm_mux_ddr_pxi1___17 = 17,\n\tmsm_mux_ddr_pxi2___15 = 18,\n\tmsm_mux_ddr_pxi3___15 = 19,\n\tmsm_mux_dp_hot___9 = 20,\n\tmsm_mux_egpio___8 = 21,\n\tmsm_mux_dp_lcd___2 = 22,\n\tmsm_mux_gcc_gp1___19 = 23,\n\tmsm_mux_gcc_gp2___19 = 24,\n\tmsm_mux_gcc_gp3___19 = 25,\n\tmsm_mux_gpio___35 = 26,\n\tmsm_mux_ibi_i3c___9 = 27,\n\tmsm_mux_jitter_bist___21 = 28,\n\tmsm_mux_lpass_slimbus___11 = 29,\n\tmsm_mux_mdp_vsync___26 = 30,\n\tmsm_mux_mdp_vsync0___11 = 31,\n\tmsm_mux_mdp_vsync1___11 = 32,\n\tmsm_mux_mdp_vsync2___11 = 33,\n\tmsm_mux_mdp_vsync3___11 = 34,\n\tmsm_mux_mi2s0_data0___3 = 35,\n\tmsm_mux_mi2s0_data1___3 = 36,\n\tmsm_mux_mi2s0_sck___3 = 37,\n\tmsm_mux_mi2s0_ws___3 = 38,\n\tmsm_mux_mi2s1_data0___5 = 39,\n\tmsm_mux_mi2s1_data1___5 = 40,\n\tmsm_mux_mi2s1_sck___5 = 41,\n\tmsm_mux_mi2s1_ws___5 = 42,\n\tmsm_mux_mi2s2_data0___5 = 43,\n\tmsm_mux_mi2s2_data1___5 = 44,\n\tmsm_mux_mi2s2_sck___5 = 45,\n\tmsm_mux_mi2s2_ws___5 = 46,\n\tmsm_mux_pci_e0___8 = 47,\n\tmsm_mux_pci_e1___7 = 48,\n\tmsm_mux_pci_e2___3 = 49,\n\tmsm_mux_phase_flag___20 = 50,\n\tmsm_mux_pll_bist___17 = 51,\n\tmsm_mux_pll_bypassnl___16 = 52,\n\tmsm_mux_pll_clk___7 = 53,\n\tmsm_mux_pll_reset___15 = 54,\n\tmsm_mux_pri_mi2s___15 = 55,\n\tmsm_mux_prng_rosc___24 = 56,\n\tmsm_mux_qdss_cti___21 = 57,\n\tmsm_mux_qdss_gpio___15 = 58,\n\tmsm_mux_qspi0___7 = 59,\n\tmsm_mux_qspi1___6 = 60,\n\tmsm_mux_qspi2___5 = 61,\n\tmsm_mux_qspi3___5 = 62,\n\tmsm_mux_qspi_clk___14 = 63,\n\tmsm_mux_qspi_cs___14 = 64,\n\tmsm_mux_qup0___9 = 65,\n\tmsm_mux_qup1___9 = 66,\n\tmsm_mux_qup10___12 = 67,\n\tmsm_mux_qup11___10 = 68,\n\tmsm_mux_qup12___12 = 69,\n\tmsm_mux_qup13___9 = 70,\n\tmsm_mux_qup14___12 = 71,\n\tmsm_mux_qup15___9 = 72,\n\tmsm_mux_qup16___6 = 73,\n\tmsm_mux_qup17___6 = 74,\n\tmsm_mux_qup18___4 = 75,\n\tmsm_mux_qup19___4 = 76,\n\tmsm_mux_qup2___8 = 77,\n\tmsm_mux_qup3___8 = 78,\n\tmsm_mux_qup4___8 = 79,\n\tmsm_mux_qup5___8 = 80,\n\tmsm_mux_qup6___6 = 81,\n\tmsm_mux_qup7___6 = 82,\n\tmsm_mux_qup8___6 = 83,\n\tmsm_mux_qup9___6 = 84,\n\tmsm_mux_qup_l4___5 = 85,\n\tmsm_mux_qup_l5___5 = 86,\n\tmsm_mux_qup_l6___5 = 87,\n\tmsm_mux_sd_write___21 = 88,\n\tmsm_mux_sdc40___6 = 89,\n\tmsm_mux_sdc41___5 = 90,\n\tmsm_mux_sdc42___6 = 91,\n\tmsm_mux_sdc43___6 = 92,\n\tmsm_mux_sdc4_clk___9 = 93,\n\tmsm_mux_sdc4_cmd___9 = 94,\n\tmsm_mux_sec_mi2s___15 = 95,\n\tmsm_mux_sp_cmu___11 = 96,\n\tmsm_mux_tgu_ch0___15 = 97,\n\tmsm_mux_tgu_ch1___15 = 98,\n\tmsm_mux_tgu_ch2___12 = 99,\n\tmsm_mux_tgu_ch3___12 = 100,\n\tmsm_mux_tsense_pwm1___17 = 101,\n\tmsm_mux_tsense_pwm2___17 = 102,\n\tmsm_mux_tsif0_clk = 103,\n\tmsm_mux_tsif0_data = 104,\n\tmsm_mux_tsif0_en = 105,\n\tmsm_mux_tsif0_error = 106,\n\tmsm_mux_tsif0_sync = 107,\n\tmsm_mux_tsif1_clk___4 = 108,\n\tmsm_mux_tsif1_data___4 = 109,\n\tmsm_mux_tsif1_en___4 = 110,\n\tmsm_mux_tsif1_error___4 = 111,\n\tmsm_mux_tsif1_sync___4 = 112,\n\tmsm_mux_usb2phy_ac___9 = 113,\n\tmsm_mux_usb_phy___14 = 114,\n\tmsm_mux_vsense_trigger___16 = 115,\n\tmsm_mux_____30 = 116,\n};\n\nenum sm8350_functions {\n\tmsm_mux_atest_char___31 = 0,\n\tmsm_mux_atest_usb___7 = 1,\n\tmsm_mux_audio_ref___16 = 2,\n\tmsm_mux_cam_mclk___24 = 3,\n\tmsm_mux_cci_async___22 = 4,\n\tmsm_mux_cci_i2c___22 = 5,\n\tmsm_mux_cci_timer___6 = 6,\n\tmsm_mux_cmu_rng___5 = 7,\n\tmsm_mux_coex_uart1___2 = 8,\n\tmsm_mux_coex_uart2___2 = 9,\n\tmsm_mux_cri_trng___26 = 10,\n\tmsm_mux_cri_trng0___21 = 11,\n\tmsm_mux_cri_trng1___21 = 12,\n\tmsm_mux_dbg_out___28 = 13,\n\tmsm_mux_ddr_bist___24 = 14,\n\tmsm_mux_ddr_pxi0___19 = 15,\n\tmsm_mux_ddr_pxi1___18 = 16,\n\tmsm_mux_ddr_pxi2___16 = 17,\n\tmsm_mux_ddr_pxi3___16 = 18,\n\tmsm_mux_dp_hot___10 = 19,\n\tmsm_mux_dp_lcd___3 = 20,\n\tmsm_mux_gcc_gp1___20 = 21,\n\tmsm_mux_gcc_gp2___20 = 22,\n\tmsm_mux_gcc_gp3___20 = 23,\n\tmsm_mux_gpio___36 = 24,\n\tmsm_mux_ibi_i3c___10 = 25,\n\tmsm_mux_jitter_bist___22 = 26,\n\tmsm_mux_lpass_slimbus___12 = 27,\n\tmsm_mux_mdp_vsync___27 = 28,\n\tmsm_mux_mdp_vsync0___12 = 29,\n\tmsm_mux_mdp_vsync1___12 = 30,\n\tmsm_mux_mdp_vsync2___12 = 31,\n\tmsm_mux_mdp_vsync3___12 = 32,\n\tmsm_mux_mi2s0_data0___4 = 33,\n\tmsm_mux_mi2s0_data1___4 = 34,\n\tmsm_mux_mi2s0_sck___4 = 35,\n\tmsm_mux_mi2s0_ws___4 = 36,\n\tmsm_mux_mi2s1_data0___6 = 37,\n\tmsm_mux_mi2s1_data1___6 = 38,\n\tmsm_mux_mi2s1_sck___6 = 39,\n\tmsm_mux_mi2s1_ws___6 = 40,\n\tmsm_mux_mi2s2_data0___6 = 41,\n\tmsm_mux_mi2s2_data1___6 = 42,\n\tmsm_mux_mi2s2_sck___6 = 43,\n\tmsm_mux_mi2s2_ws___6 = 44,\n\tmsm_mux_mss_grfc0___2 = 45,\n\tmsm_mux_mss_grfc1___2 = 46,\n\tmsm_mux_mss_grfc10___2 = 47,\n\tmsm_mux_mss_grfc11___2 = 48,\n\tmsm_mux_mss_grfc12___2 = 49,\n\tmsm_mux_mss_grfc2___2 = 50,\n\tmsm_mux_mss_grfc3___2 = 51,\n\tmsm_mux_mss_grfc4___2 = 52,\n\tmsm_mux_mss_grfc5___2 = 53,\n\tmsm_mux_mss_grfc6___2 = 54,\n\tmsm_mux_mss_grfc7___2 = 55,\n\tmsm_mux_mss_grfc8___2 = 56,\n\tmsm_mux_mss_grfc9___2 = 57,\n\tmsm_mux_nav_gpio___6 = 58,\n\tmsm_mux_pa_indicator___19 = 59,\n\tmsm_mux_pcie0_clkreqn___2 = 60,\n\tmsm_mux_pcie1_clkreqn___2 = 61,\n\tmsm_mux_phase_flag___21 = 62,\n\tmsm_mux_pll_bist___18 = 63,\n\tmsm_mux_pll_clk___8 = 64,\n\tmsm_mux_pri_mi2s___16 = 65,\n\tmsm_mux_prng_rosc___25 = 66,\n\tmsm_mux_qdss_cti___22 = 67,\n\tmsm_mux_qdss_gpio___16 = 68,\n\tmsm_mux_qlink0_enable___7 = 69,\n\tmsm_mux_qlink0_request___7 = 70,\n\tmsm_mux_qlink0_wmss___7 = 71,\n\tmsm_mux_qlink1_enable___6 = 72,\n\tmsm_mux_qlink1_request___6 = 73,\n\tmsm_mux_qlink1_wmss___7 = 74,\n\tmsm_mux_qlink2_enable___2 = 75,\n\tmsm_mux_qlink2_request___2 = 76,\n\tmsm_mux_qlink2_wmss___2 = 77,\n\tmsm_mux_qspi0___8 = 78,\n\tmsm_mux_qspi1___7 = 79,\n\tmsm_mux_qspi2___6 = 80,\n\tmsm_mux_qspi3___6 = 81,\n\tmsm_mux_qspi_clk___15 = 82,\n\tmsm_mux_qspi_cs___15 = 83,\n\tmsm_mux_qup0___10 = 84,\n\tmsm_mux_qup1___10 = 85,\n\tmsm_mux_qup10___13 = 86,\n\tmsm_mux_qup11___11 = 87,\n\tmsm_mux_qup12___13 = 88,\n\tmsm_mux_qup13___10 = 89,\n\tmsm_mux_qup14___13 = 90,\n\tmsm_mux_qup15___10 = 91,\n\tmsm_mux_qup16___7 = 92,\n\tmsm_mux_qup17___7 = 93,\n\tmsm_mux_qup18___5 = 94,\n\tmsm_mux_qup19___5 = 95,\n\tmsm_mux_qup2___9 = 96,\n\tmsm_mux_qup3___9 = 97,\n\tmsm_mux_qup4___9 = 98,\n\tmsm_mux_qup5___9 = 99,\n\tmsm_mux_qup6___7 = 100,\n\tmsm_mux_qup7___7 = 101,\n\tmsm_mux_qup8___7 = 102,\n\tmsm_mux_qup9___7 = 103,\n\tmsm_mux_qup_l4___6 = 104,\n\tmsm_mux_qup_l5___6 = 105,\n\tmsm_mux_qup_l6___6 = 106,\n\tmsm_mux_sd_write___22 = 107,\n\tmsm_mux_sdc40___7 = 108,\n\tmsm_mux_sdc41___6 = 109,\n\tmsm_mux_sdc42___7 = 110,\n\tmsm_mux_sdc43___7 = 111,\n\tmsm_mux_sdc4_clk___10 = 112,\n\tmsm_mux_sdc4_cmd___10 = 113,\n\tmsm_mux_sec_mi2s___16 = 114,\n\tmsm_mux_tb_trig___6 = 115,\n\tmsm_mux_tgu_ch0___16 = 116,\n\tmsm_mux_tgu_ch1___16 = 117,\n\tmsm_mux_tgu_ch2___13 = 118,\n\tmsm_mux_tgu_ch3___13 = 119,\n\tmsm_mux_tsense_pwm1___18 = 120,\n\tmsm_mux_tsense_pwm2___18 = 121,\n\tmsm_mux_uim0_clk___4 = 122,\n\tmsm_mux_uim0_data___4 = 123,\n\tmsm_mux_uim0_present___4 = 124,\n\tmsm_mux_uim0_reset___4 = 125,\n\tmsm_mux_uim1_clk___15 = 126,\n\tmsm_mux_uim1_data___15 = 127,\n\tmsm_mux_uim1_present___15 = 128,\n\tmsm_mux_uim1_reset___15 = 129,\n\tmsm_mux_usb2phy_ac___10 = 130,\n\tmsm_mux_usb_phy___15 = 131,\n\tmsm_mux_vfr_0___5 = 132,\n\tmsm_mux_vfr_1___20 = 133,\n\tmsm_mux_vsense_trigger___17 = 134,\n\tmsm_mux_____31 = 135,\n};\n\nenum sm8450_functions {\n\tmsm_mux_gpio___37 = 0,\n\tmsm_mux_aon_cam = 1,\n\tmsm_mux_atest_char___32 = 2,\n\tmsm_mux_atest_usb___8 = 3,\n\tmsm_mux_audio_ref___17 = 4,\n\tmsm_mux_cam_mclk___25 = 5,\n\tmsm_mux_cci_async___23 = 6,\n\tmsm_mux_cci_i2c___23 = 7,\n\tmsm_mux_cci_timer___7 = 8,\n\tmsm_mux_cmu_rng___6 = 9,\n\tmsm_mux_coex_uart1___3 = 10,\n\tmsm_mux_coex_uart2___3 = 11,\n\tmsm_mux_cri_trng___27 = 12,\n\tmsm_mux_cri_trng0___22 = 13,\n\tmsm_mux_cri_trng1___22 = 14,\n\tmsm_mux_dbg_out___29 = 15,\n\tmsm_mux_ddr_bist___25 = 16,\n\tmsm_mux_ddr_pxi0___20 = 17,\n\tmsm_mux_ddr_pxi1___19 = 18,\n\tmsm_mux_ddr_pxi2___17 = 19,\n\tmsm_mux_ddr_pxi3___17 = 20,\n\tmsm_mux_dp_hot___11 = 21,\n\tmsm_mux_egpio___9 = 22,\n\tmsm_mux_gcc_gp1___21 = 23,\n\tmsm_mux_gcc_gp2___21 = 24,\n\tmsm_mux_gcc_gp3___21 = 25,\n\tmsm_mux_ibi_i3c___11 = 26,\n\tmsm_mux_jitter_bist___23 = 27,\n\tmsm_mux_mdp_vsync___28 = 28,\n\tmsm_mux_mdp_vsync0___13 = 29,\n\tmsm_mux_mdp_vsync1___13 = 30,\n\tmsm_mux_mdp_vsync2___13 = 31,\n\tmsm_mux_mdp_vsync3___13 = 32,\n\tmsm_mux_mi2s0_data0___5 = 33,\n\tmsm_mux_mi2s0_data1___5 = 34,\n\tmsm_mux_mi2s0_sck___5 = 35,\n\tmsm_mux_mi2s0_ws___5 = 36,\n\tmsm_mux_mi2s2_data0___7 = 37,\n\tmsm_mux_mi2s2_data1___7 = 38,\n\tmsm_mux_mi2s2_sck___7 = 39,\n\tmsm_mux_mi2s2_ws___7 = 40,\n\tmsm_mux_mss_grfc0___3 = 41,\n\tmsm_mux_mss_grfc1___3 = 42,\n\tmsm_mux_mss_grfc10___3 = 43,\n\tmsm_mux_mss_grfc11___3 = 44,\n\tmsm_mux_mss_grfc12___3 = 45,\n\tmsm_mux_mss_grfc2___3 = 46,\n\tmsm_mux_mss_grfc3___3 = 47,\n\tmsm_mux_mss_grfc4___3 = 48,\n\tmsm_mux_mss_grfc5___3 = 49,\n\tmsm_mux_mss_grfc6___3 = 50,\n\tmsm_mux_mss_grfc7___3 = 51,\n\tmsm_mux_mss_grfc8___3 = 52,\n\tmsm_mux_mss_grfc9___3 = 53,\n\tmsm_mux_nav___2 = 54,\n\tmsm_mux_pcie0_clkreqn___3 = 55,\n\tmsm_mux_pcie1_clkreqn___3 = 56,\n\tmsm_mux_phase_flag___22 = 57,\n\tmsm_mux_pll_bist___19 = 58,\n\tmsm_mux_pll_clk___9 = 59,\n\tmsm_mux_pri_mi2s___17 = 60,\n\tmsm_mux_prng_rosc___26 = 61,\n\tmsm_mux_qdss_cti___23 = 62,\n\tmsm_mux_qdss_gpio___17 = 63,\n\tmsm_mux_qlink0_enable___8 = 64,\n\tmsm_mux_qlink0_request___8 = 65,\n\tmsm_mux_qlink0_wmss___8 = 66,\n\tmsm_mux_qlink1_enable___7 = 67,\n\tmsm_mux_qlink1_request___7 = 68,\n\tmsm_mux_qlink1_wmss___8 = 69,\n\tmsm_mux_qlink2_enable___3 = 70,\n\tmsm_mux_qlink2_request___3 = 71,\n\tmsm_mux_qlink2_wmss___3 = 72,\n\tmsm_mux_qspi0___9 = 73,\n\tmsm_mux_qspi1___8 = 74,\n\tmsm_mux_qspi2___7 = 75,\n\tmsm_mux_qspi3___7 = 76,\n\tmsm_mux_qspi_clk___16 = 77,\n\tmsm_mux_qspi_cs___16 = 78,\n\tmsm_mux_qup0___11 = 79,\n\tmsm_mux_qup1___11 = 80,\n\tmsm_mux_qup10___14 = 81,\n\tmsm_mux_qup11___12 = 82,\n\tmsm_mux_qup12___14 = 83,\n\tmsm_mux_qup13___11 = 84,\n\tmsm_mux_qup14___14 = 85,\n\tmsm_mux_qup15___11 = 86,\n\tmsm_mux_qup16___8 = 87,\n\tmsm_mux_qup17___8 = 88,\n\tmsm_mux_qup18___6 = 89,\n\tmsm_mux_qup19___6 = 90,\n\tmsm_mux_qup2___10 = 91,\n\tmsm_mux_qup20___3 = 92,\n\tmsm_mux_qup21___3 = 93,\n\tmsm_mux_qup3___10 = 94,\n\tmsm_mux_qup4___10 = 95,\n\tmsm_mux_qup5___10 = 96,\n\tmsm_mux_qup6___8 = 97,\n\tmsm_mux_qup7___8 = 98,\n\tmsm_mux_qup8___8 = 99,\n\tmsm_mux_qup9___8 = 100,\n\tmsm_mux_qup_l4___7 = 101,\n\tmsm_mux_qup_l5___7 = 102,\n\tmsm_mux_qup_l6___7 = 103,\n\tmsm_mux_sd_write___23 = 104,\n\tmsm_mux_sdc40___8 = 105,\n\tmsm_mux_sdc41___7 = 106,\n\tmsm_mux_sdc42___8 = 107,\n\tmsm_mux_sdc43___8 = 108,\n\tmsm_mux_sdc4_clk___11 = 109,\n\tmsm_mux_sdc4_cmd___11 = 110,\n\tmsm_mux_sec_mi2s___17 = 111,\n\tmsm_mux_tb_trig___7 = 112,\n\tmsm_mux_tgu_ch0___17 = 113,\n\tmsm_mux_tgu_ch1___17 = 114,\n\tmsm_mux_tgu_ch2___14 = 115,\n\tmsm_mux_tgu_ch3___14 = 116,\n\tmsm_mux_tmess_prng0___5 = 117,\n\tmsm_mux_tmess_prng1___5 = 118,\n\tmsm_mux_tmess_prng2___5 = 119,\n\tmsm_mux_tmess_prng3___5 = 120,\n\tmsm_mux_tsense_pwm1___19 = 121,\n\tmsm_mux_tsense_pwm2___19 = 122,\n\tmsm_mux_uim0_clk___5 = 123,\n\tmsm_mux_uim0_data___5 = 124,\n\tmsm_mux_uim0_present___5 = 125,\n\tmsm_mux_uim0_reset___5 = 126,\n\tmsm_mux_uim1_clk___16 = 127,\n\tmsm_mux_uim1_data___16 = 128,\n\tmsm_mux_uim1_present___16 = 129,\n\tmsm_mux_uim1_reset___16 = 130,\n\tmsm_mux_usb2phy_ac___11 = 131,\n\tmsm_mux_usb_phy___16 = 132,\n\tmsm_mux_vfr_0___6 = 133,\n\tmsm_mux_vfr_1___21 = 134,\n\tmsm_mux_vsense_trigger___18 = 135,\n\tmsm_mux_____32 = 136,\n};\n\nenum sm8550_functions {\n\tmsm_mux_gpio___38 = 0,\n\tmsm_mux_aon_cci = 1,\n\tmsm_mux_aoss_cti___9 = 2,\n\tmsm_mux_atest_char___33 = 3,\n\tmsm_mux_atest_usb___9 = 4,\n\tmsm_mux_audio_ext_mclk0___3 = 5,\n\tmsm_mux_audio_ext_mclk1___3 = 6,\n\tmsm_mux_audio_ref_clk___6 = 7,\n\tmsm_mux_cam_aon_mclk4 = 8,\n\tmsm_mux_cam_mclk___26 = 9,\n\tmsm_mux_cci_async_in___2 = 10,\n\tmsm_mux_cci_i2c_scl___4 = 11,\n\tmsm_mux_cci_i2c_sda___4 = 12,\n\tmsm_mux_cci_timer___8 = 13,\n\tmsm_mux_cmu_rng___7 = 14,\n\tmsm_mux_coex_uart1_rx___4 = 15,\n\tmsm_mux_coex_uart1_tx___4 = 16,\n\tmsm_mux_coex_uart2_rx___2 = 17,\n\tmsm_mux_coex_uart2_tx___2 = 18,\n\tmsm_mux_cri_trng___28 = 19,\n\tmsm_mux_dbg_out_clk___7 = 20,\n\tmsm_mux_ddr_bist_complete___3 = 21,\n\tmsm_mux_ddr_bist_fail___3 = 22,\n\tmsm_mux_ddr_bist_start___3 = 23,\n\tmsm_mux_ddr_bist_stop___3 = 24,\n\tmsm_mux_ddr_pxi0___21 = 25,\n\tmsm_mux_ddr_pxi1___20 = 26,\n\tmsm_mux_ddr_pxi2___18 = 27,\n\tmsm_mux_ddr_pxi3___18 = 28,\n\tmsm_mux_dp_hot___12 = 29,\n\tmsm_mux_gcc_gp1___22 = 30,\n\tmsm_mux_gcc_gp2___22 = 31,\n\tmsm_mux_gcc_gp3___22 = 32,\n\tmsm_mux_i2chub0_se0___2 = 33,\n\tmsm_mux_i2chub0_se1___2 = 34,\n\tmsm_mux_i2chub0_se2___2 = 35,\n\tmsm_mux_i2chub0_se3___2 = 36,\n\tmsm_mux_i2chub0_se4___2 = 37,\n\tmsm_mux_i2chub0_se5 = 38,\n\tmsm_mux_i2chub0_se6 = 39,\n\tmsm_mux_i2chub0_se7 = 40,\n\tmsm_mux_i2chub0_se8 = 41,\n\tmsm_mux_i2chub0_se9 = 42,\n\tmsm_mux_i2s0_data0___3 = 43,\n\tmsm_mux_i2s0_data1___3 = 44,\n\tmsm_mux_i2s0_sck___3 = 45,\n\tmsm_mux_i2s0_ws___3 = 46,\n\tmsm_mux_i2s1_data0___2 = 47,\n\tmsm_mux_i2s1_data1___2 = 48,\n\tmsm_mux_i2s1_sck___2 = 49,\n\tmsm_mux_i2s1_ws___2 = 50,\n\tmsm_mux_ibi_i3c___12 = 51,\n\tmsm_mux_jitter_bist___24 = 52,\n\tmsm_mux_mdp_vsync___29 = 53,\n\tmsm_mux_mdp_vsync0_out___5 = 54,\n\tmsm_mux_mdp_vsync1_out___5 = 55,\n\tmsm_mux_mdp_vsync2_out___5 = 56,\n\tmsm_mux_mdp_vsync3_out___5 = 57,\n\tmsm_mux_mdp_vsync_e___3 = 58,\n\tmsm_mux_nav_gpio0___4 = 59,\n\tmsm_mux_nav_gpio1___4 = 60,\n\tmsm_mux_nav_gpio2___4 = 61,\n\tmsm_mux_pcie0_clk_req_n___3 = 62,\n\tmsm_mux_pcie1_clk_req_n___2 = 63,\n\tmsm_mux_phase_flag___23 = 64,\n\tmsm_mux_pll_bist_sync___5 = 65,\n\tmsm_mux_pll_clk_aux___5 = 66,\n\tmsm_mux_prng_rosc0___10 = 67,\n\tmsm_mux_prng_rosc1___10 = 68,\n\tmsm_mux_prng_rosc2___10 = 69,\n\tmsm_mux_prng_rosc3___10 = 70,\n\tmsm_mux_qdss_cti___24 = 71,\n\tmsm_mux_qdss_gpio___18 = 72,\n\tmsm_mux_qlink0_enable___9 = 73,\n\tmsm_mux_qlink0_request___9 = 74,\n\tmsm_mux_qlink0_wmss___9 = 75,\n\tmsm_mux_qlink1_enable___8 = 76,\n\tmsm_mux_qlink1_request___8 = 77,\n\tmsm_mux_qlink1_wmss___9 = 78,\n\tmsm_mux_qlink2_enable___4 = 79,\n\tmsm_mux_qlink2_request___4 = 80,\n\tmsm_mux_qlink2_wmss___4 = 81,\n\tmsm_mux_qspi0___10 = 82,\n\tmsm_mux_qspi1___9 = 83,\n\tmsm_mux_qspi2___8 = 84,\n\tmsm_mux_qspi3___8 = 85,\n\tmsm_mux_qspi_clk___17 = 86,\n\tmsm_mux_qspi_cs___17 = 87,\n\tmsm_mux_qup1_se0___6 = 88,\n\tmsm_mux_qup1_se1___6 = 89,\n\tmsm_mux_qup1_se2___6 = 90,\n\tmsm_mux_qup1_se3___6 = 91,\n\tmsm_mux_qup1_se4___6 = 92,\n\tmsm_mux_qup1_se5___5 = 93,\n\tmsm_mux_qup1_se6___5 = 94,\n\tmsm_mux_qup1_se7___3 = 95,\n\tmsm_mux_qup2_se0___4 = 96,\n\tmsm_mux_qup2_se0_l0_mira = 97,\n\tmsm_mux_qup2_se0_l0_mirb = 98,\n\tmsm_mux_qup2_se0_l1_mira = 99,\n\tmsm_mux_qup2_se0_l1_mirb = 100,\n\tmsm_mux_qup2_se0_l2_mira = 101,\n\tmsm_mux_qup2_se0_l2_mirb = 102,\n\tmsm_mux_qup2_se0_l3_mira = 103,\n\tmsm_mux_qup2_se0_l3_mirb = 104,\n\tmsm_mux_qup2_se1___3 = 105,\n\tmsm_mux_qup2_se2___3 = 106,\n\tmsm_mux_qup2_se3___3 = 107,\n\tmsm_mux_qup2_se4___3 = 108,\n\tmsm_mux_qup2_se5___2 = 109,\n\tmsm_mux_qup2_se6___2 = 110,\n\tmsm_mux_qup2_se7 = 111,\n\tmsm_mux_resout_n = 112,\n\tmsm_mux_sd_write_protect___5 = 113,\n\tmsm_mux_sdc40___9 = 114,\n\tmsm_mux_sdc41___8 = 115,\n\tmsm_mux_sdc42___9 = 116,\n\tmsm_mux_sdc43___9 = 117,\n\tmsm_mux_sdc4_clk___12 = 118,\n\tmsm_mux_sdc4_cmd___12 = 119,\n\tmsm_mux_tb_trig_sdc2___4 = 120,\n\tmsm_mux_tb_trig_sdc4___2 = 121,\n\tmsm_mux_tgu_ch0_trigout___4 = 122,\n\tmsm_mux_tgu_ch1_trigout___3 = 123,\n\tmsm_mux_tgu_ch2_trigout___2 = 124,\n\tmsm_mux_tgu_ch3_trigout___2 = 125,\n\tmsm_mux_tmess_prng0___6 = 126,\n\tmsm_mux_tmess_prng1___6 = 127,\n\tmsm_mux_tmess_prng2___6 = 128,\n\tmsm_mux_tmess_prng3___6 = 129,\n\tmsm_mux_tsense_pwm1___20 = 130,\n\tmsm_mux_tsense_pwm2___20 = 131,\n\tmsm_mux_tsense_pwm3___5 = 132,\n\tmsm_mux_uim0_clk___6 = 133,\n\tmsm_mux_uim0_data___6 = 134,\n\tmsm_mux_uim0_present___6 = 135,\n\tmsm_mux_uim0_reset___6 = 136,\n\tmsm_mux_uim1_clk___17 = 137,\n\tmsm_mux_uim1_data___17 = 138,\n\tmsm_mux_uim1_present___17 = 139,\n\tmsm_mux_uim1_reset___17 = 140,\n\tmsm_mux_usb1_hs___2 = 141,\n\tmsm_mux_usb_phy___17 = 142,\n\tmsm_mux_vfr_0___7 = 143,\n\tmsm_mux_vfr_1___22 = 144,\n\tmsm_mux_vsense_trigger_mirnat___6 = 145,\n\tmsm_mux_____33 = 146,\n};\n\nenum sm8650_functions {\n\tmsm_mux_gpio___39 = 0,\n\tmsm_mux_aoss_cti___10 = 1,\n\tmsm_mux_atest_char___34 = 2,\n\tmsm_mux_atest_usb___10 = 3,\n\tmsm_mux_audio_ext_mclk0___4 = 4,\n\tmsm_mux_audio_ext_mclk1___4 = 5,\n\tmsm_mux_audio_ref_clk___7 = 6,\n\tmsm_mux_cam_aon_mclk2 = 7,\n\tmsm_mux_cam_aon_mclk4___2 = 8,\n\tmsm_mux_cam_mclk___27 = 9,\n\tmsm_mux_cci_async_in___3 = 10,\n\tmsm_mux_cci_i2c_scl___5 = 11,\n\tmsm_mux_cci_i2c_sda___5 = 12,\n\tmsm_mux_cci_timer___9 = 13,\n\tmsm_mux_cmu_rng___8 = 14,\n\tmsm_mux_coex_uart1_rx___5 = 15,\n\tmsm_mux_coex_uart1_tx___5 = 16,\n\tmsm_mux_coex_uart2_rx___3 = 17,\n\tmsm_mux_coex_uart2_tx___3 = 18,\n\tmsm_mux_cri_trng___29 = 19,\n\tmsm_mux_dbg_out_clk___8 = 20,\n\tmsm_mux_ddr_bist_complete___4 = 21,\n\tmsm_mux_ddr_bist_fail___4 = 22,\n\tmsm_mux_ddr_bist_start___4 = 23,\n\tmsm_mux_ddr_bist_stop___4 = 24,\n\tmsm_mux_ddr_pxi0___22 = 25,\n\tmsm_mux_ddr_pxi1___21 = 26,\n\tmsm_mux_ddr_pxi2___19 = 27,\n\tmsm_mux_ddr_pxi3___19 = 28,\n\tmsm_mux_do_not = 29,\n\tmsm_mux_dp_hot___13 = 30,\n\tmsm_mux_egpio___10 = 31,\n\tmsm_mux_gcc_gp1___23 = 32,\n\tmsm_mux_gcc_gp2___23 = 33,\n\tmsm_mux_gcc_gp3___23 = 34,\n\tmsm_mux_gnss_adc0___2 = 35,\n\tmsm_mux_gnss_adc1___2 = 36,\n\tmsm_mux_i2chub0_se0___3 = 37,\n\tmsm_mux_i2chub0_se1___3 = 38,\n\tmsm_mux_i2chub0_se2___3 = 39,\n\tmsm_mux_i2chub0_se3___3 = 40,\n\tmsm_mux_i2chub0_se4___3 = 41,\n\tmsm_mux_i2chub0_se5___2 = 42,\n\tmsm_mux_i2chub0_se6___2 = 43,\n\tmsm_mux_i2chub0_se7___2 = 44,\n\tmsm_mux_i2chub0_se8___2 = 45,\n\tmsm_mux_i2chub0_se9___2 = 46,\n\tmsm_mux_i2s0_data0___4 = 47,\n\tmsm_mux_i2s0_data1___4 = 48,\n\tmsm_mux_i2s0_sck___4 = 49,\n\tmsm_mux_i2s0_ws___4 = 50,\n\tmsm_mux_i2s1_data0___3 = 51,\n\tmsm_mux_i2s1_data1___3 = 52,\n\tmsm_mux_i2s1_sck___3 = 53,\n\tmsm_mux_i2s1_ws___3 = 54,\n\tmsm_mux_ibi_i3c___13 = 55,\n\tmsm_mux_jitter_bist___25 = 56,\n\tmsm_mux_mdp_vsync___30 = 57,\n\tmsm_mux_mdp_vsync0_out___6 = 58,\n\tmsm_mux_mdp_vsync1_out___6 = 59,\n\tmsm_mux_mdp_vsync2_out___6 = 60,\n\tmsm_mux_mdp_vsync3_out___6 = 61,\n\tmsm_mux_mdp_vsync_e___4 = 62,\n\tmsm_mux_nav_gpio0___5 = 63,\n\tmsm_mux_nav_gpio1___5 = 64,\n\tmsm_mux_nav_gpio2___5 = 65,\n\tmsm_mux_nav_gpio3___2 = 66,\n\tmsm_mux_pcie0_clk_req_n___4 = 67,\n\tmsm_mux_pcie1_clk_req_n___3 = 68,\n\tmsm_mux_phase_flag___24 = 69,\n\tmsm_mux_pll_bist_sync___6 = 70,\n\tmsm_mux_pll_clk_aux___6 = 71,\n\tmsm_mux_prng_rosc0___11 = 72,\n\tmsm_mux_prng_rosc1___11 = 73,\n\tmsm_mux_prng_rosc2___11 = 74,\n\tmsm_mux_prng_rosc3___11 = 75,\n\tmsm_mux_qdss_cti___25 = 76,\n\tmsm_mux_qdss_gpio___19 = 77,\n\tmsm_mux_qlink_big_enable___2 = 78,\n\tmsm_mux_qlink_big_request___2 = 79,\n\tmsm_mux_qlink_little_enable___2 = 80,\n\tmsm_mux_qlink_little_request___2 = 81,\n\tmsm_mux_qlink_wmss___2 = 82,\n\tmsm_mux_qspi0___11 = 83,\n\tmsm_mux_qspi1___10 = 84,\n\tmsm_mux_qspi2___9 = 85,\n\tmsm_mux_qspi3___9 = 86,\n\tmsm_mux_qspi_clk___18 = 87,\n\tmsm_mux_qspi_cs___18 = 88,\n\tmsm_mux_qup1_se0___7 = 89,\n\tmsm_mux_qup1_se1___7 = 90,\n\tmsm_mux_qup1_se2___7 = 91,\n\tmsm_mux_qup1_se3___7 = 92,\n\tmsm_mux_qup1_se4___7 = 93,\n\tmsm_mux_qup1_se5___6 = 94,\n\tmsm_mux_qup1_se6___6 = 95,\n\tmsm_mux_qup1_se7___4 = 96,\n\tmsm_mux_qup2_se0___5 = 97,\n\tmsm_mux_qup2_se1___4 = 98,\n\tmsm_mux_qup2_se2___4 = 99,\n\tmsm_mux_qup2_se3___4 = 100,\n\tmsm_mux_qup2_se4___4 = 101,\n\tmsm_mux_qup2_se5___3 = 102,\n\tmsm_mux_qup2_se6___3 = 103,\n\tmsm_mux_qup2_se7___2 = 104,\n\tmsm_mux_sd_write_protect___6 = 105,\n\tmsm_mux_sdc40___10 = 106,\n\tmsm_mux_sdc41___9 = 107,\n\tmsm_mux_sdc42___10 = 108,\n\tmsm_mux_sdc43___10 = 109,\n\tmsm_mux_sdc4_clk___13 = 110,\n\tmsm_mux_sdc4_cmd___13 = 111,\n\tmsm_mux_tb_trig_sdc2___5 = 112,\n\tmsm_mux_tb_trig_sdc4___3 = 113,\n\tmsm_mux_tgu_ch0_trigout___5 = 114,\n\tmsm_mux_tgu_ch1_trigout___4 = 115,\n\tmsm_mux_tgu_ch2_trigout___3 = 116,\n\tmsm_mux_tgu_ch3_trigout___3 = 117,\n\tmsm_mux_tmess_prng0___7 = 118,\n\tmsm_mux_tmess_prng1___7 = 119,\n\tmsm_mux_tmess_prng2___7 = 120,\n\tmsm_mux_tmess_prng3___7 = 121,\n\tmsm_mux_tsense_pwm1___21 = 122,\n\tmsm_mux_tsense_pwm2___21 = 123,\n\tmsm_mux_tsense_pwm3___6 = 124,\n\tmsm_mux_uim0_clk___7 = 125,\n\tmsm_mux_uim0_data___7 = 126,\n\tmsm_mux_uim0_present___7 = 127,\n\tmsm_mux_uim0_reset___7 = 128,\n\tmsm_mux_uim1_clk___18 = 129,\n\tmsm_mux_uim1_data___18 = 130,\n\tmsm_mux_uim1_present___18 = 131,\n\tmsm_mux_uim1_reset___18 = 132,\n\tmsm_mux_usb1_hs___3 = 133,\n\tmsm_mux_usb_phy___18 = 134,\n\tmsm_mux_vfr_0___8 = 135,\n\tmsm_mux_vfr_1___23 = 136,\n\tmsm_mux_vsense_trigger_mirnat___7 = 137,\n\tmsm_mux_____34 = 138,\n};\n\nenum sm8750_functions {\n\tmsm_mux_gpio___40 = 0,\n\tmsm_mux_aoss_cti___11 = 1,\n\tmsm_mux_atest_char___35 = 2,\n\tmsm_mux_atest_usb___11 = 3,\n\tmsm_mux_audio_ext_mclk0___5 = 4,\n\tmsm_mux_audio_ext_mclk1___5 = 5,\n\tmsm_mux_audio_ref_clk___8 = 6,\n\tmsm_mux_cam_aon_mclk2___2 = 7,\n\tmsm_mux_cam_aon_mclk4___3 = 8,\n\tmsm_mux_cam_mclk___28 = 9,\n\tmsm_mux_cci_async_in___4 = 10,\n\tmsm_mux_cci_i2c_scl___6 = 11,\n\tmsm_mux_cci_i2c_sda___6 = 12,\n\tmsm_mux_cci_timer___10 = 13,\n\tmsm_mux_cmu_rng___9 = 14,\n\tmsm_mux_coex_uart1_rx___6 = 15,\n\tmsm_mux_coex_uart1_tx___6 = 16,\n\tmsm_mux_coex_uart2_rx___4 = 17,\n\tmsm_mux_coex_uart2_tx___4 = 18,\n\tmsm_mux_dbg_out_clk___9 = 19,\n\tmsm_mux_ddr_bist_complete___5 = 20,\n\tmsm_mux_ddr_bist_fail___5 = 21,\n\tmsm_mux_ddr_bist_start___5 = 22,\n\tmsm_mux_ddr_bist_stop___5 = 23,\n\tmsm_mux_ddr_pxi0___23 = 24,\n\tmsm_mux_ddr_pxi1___22 = 25,\n\tmsm_mux_ddr_pxi2___20 = 26,\n\tmsm_mux_ddr_pxi3___20 = 27,\n\tmsm_mux_dp_hot___14 = 28,\n\tmsm_mux_egpio___11 = 29,\n\tmsm_mux_gcc_gp1___24 = 30,\n\tmsm_mux_gcc_gp2___24 = 31,\n\tmsm_mux_gcc_gp3___24 = 32,\n\tmsm_mux_gnss_adc0___3 = 33,\n\tmsm_mux_gnss_adc1___3 = 34,\n\tmsm_mux_i2chub0_se0___4 = 35,\n\tmsm_mux_i2chub0_se1___4 = 36,\n\tmsm_mux_i2chub0_se2___4 = 37,\n\tmsm_mux_i2chub0_se3___4 = 38,\n\tmsm_mux_i2chub0_se4___4 = 39,\n\tmsm_mux_i2chub0_se5___3 = 40,\n\tmsm_mux_i2chub0_se6___3 = 41,\n\tmsm_mux_i2chub0_se7___3 = 42,\n\tmsm_mux_i2chub0_se8___3 = 43,\n\tmsm_mux_i2chub0_se9___3 = 44,\n\tmsm_mux_i2s0_data0___5 = 45,\n\tmsm_mux_i2s0_data1___5 = 46,\n\tmsm_mux_i2s0_sck___5 = 47,\n\tmsm_mux_i2s0_ws___5 = 48,\n\tmsm_mux_i2s1_data0___4 = 49,\n\tmsm_mux_i2s1_data1___4 = 50,\n\tmsm_mux_i2s1_sck___4 = 51,\n\tmsm_mux_i2s1_ws___4 = 52,\n\tmsm_mux_ibi_i3c___14 = 53,\n\tmsm_mux_jitter_bist___26 = 54,\n\tmsm_mux_mdp_esync0_out___2 = 55,\n\tmsm_mux_mdp_esync1_out___2 = 56,\n\tmsm_mux_mdp_vsync___31 = 57,\n\tmsm_mux_mdp_vsync0_out___7 = 58,\n\tmsm_mux_mdp_vsync1_out___7 = 59,\n\tmsm_mux_mdp_vsync2_out___7 = 60,\n\tmsm_mux_mdp_vsync3_out___7 = 61,\n\tmsm_mux_mdp_vsync5_out___3 = 62,\n\tmsm_mux_mdp_vsync_e___5 = 63,\n\tmsm_mux_nav_gpio0___6 = 64,\n\tmsm_mux_nav_gpio1___6 = 65,\n\tmsm_mux_nav_gpio2___6 = 66,\n\tmsm_mux_nav_gpio3___3 = 67,\n\tmsm_mux_pcie0_clk_req_n___5 = 68,\n\tmsm_mux_phase_flag___25 = 69,\n\tmsm_mux_pll_bist_sync___7 = 70,\n\tmsm_mux_pll_clk_aux___7 = 71,\n\tmsm_mux_prng_rosc0___12 = 72,\n\tmsm_mux_prng_rosc1___12 = 73,\n\tmsm_mux_prng_rosc2___12 = 74,\n\tmsm_mux_prng_rosc3___12 = 75,\n\tmsm_mux_qdss_cti___26 = 76,\n\tmsm_mux_qlink_big_enable___3 = 77,\n\tmsm_mux_qlink_big_request___3 = 78,\n\tmsm_mux_qlink_little_enable___3 = 79,\n\tmsm_mux_qlink_little_request___3 = 80,\n\tmsm_mux_qlink_wmss___3 = 81,\n\tmsm_mux_qspi0___12 = 82,\n\tmsm_mux_qspi1___11 = 83,\n\tmsm_mux_qspi2___10 = 84,\n\tmsm_mux_qspi3___10 = 85,\n\tmsm_mux_qspi_clk___19 = 86,\n\tmsm_mux_qspi_cs___19 = 87,\n\tmsm_mux_qup1_se0___8 = 88,\n\tmsm_mux_qup1_se1___8 = 89,\n\tmsm_mux_qup1_se2___8 = 90,\n\tmsm_mux_qup1_se3___8 = 91,\n\tmsm_mux_qup1_se4___8 = 92,\n\tmsm_mux_qup1_se5___7 = 93,\n\tmsm_mux_qup1_se6___7 = 94,\n\tmsm_mux_qup1_se7___5 = 95,\n\tmsm_mux_qup2_se0___6 = 96,\n\tmsm_mux_qup2_se1___5 = 97,\n\tmsm_mux_qup2_se2___5 = 98,\n\tmsm_mux_qup2_se3___5 = 99,\n\tmsm_mux_qup2_se4___5 = 100,\n\tmsm_mux_qup2_se5___4 = 101,\n\tmsm_mux_qup2_se6___4 = 102,\n\tmsm_mux_qup2_se7___3 = 103,\n\tmsm_mux_sd_write_protect___7 = 104,\n\tmsm_mux_sdc40___11 = 105,\n\tmsm_mux_sdc41___10 = 106,\n\tmsm_mux_sdc42___11 = 107,\n\tmsm_mux_sdc43___11 = 108,\n\tmsm_mux_sdc4_clk___14 = 109,\n\tmsm_mux_sdc4_cmd___14 = 110,\n\tmsm_mux_tb_trig_sdc2___6 = 111,\n\tmsm_mux_tb_trig_sdc4___4 = 112,\n\tmsm_mux_tmess_prng0___8 = 113,\n\tmsm_mux_tmess_prng1___8 = 114,\n\tmsm_mux_tmess_prng2___8 = 115,\n\tmsm_mux_tmess_prng3___8 = 116,\n\tmsm_mux_tsense_pwm1___22 = 117,\n\tmsm_mux_tsense_pwm2___22 = 118,\n\tmsm_mux_tsense_pwm3___7 = 119,\n\tmsm_mux_tsense_pwm4___5 = 120,\n\tmsm_mux_uim0_clk___8 = 121,\n\tmsm_mux_uim0_data___8 = 122,\n\tmsm_mux_uim0_present___8 = 123,\n\tmsm_mux_uim0_reset___8 = 124,\n\tmsm_mux_uim1_clk___19 = 125,\n\tmsm_mux_uim1_data___19 = 126,\n\tmsm_mux_uim1_present___19 = 127,\n\tmsm_mux_uim1_reset___19 = 128,\n\tmsm_mux_usb1_hs___4 = 129,\n\tmsm_mux_usb_phy___19 = 130,\n\tmsm_mux_vfr_0___9 = 131,\n\tmsm_mux_vfr_1___24 = 132,\n\tmsm_mux_vsense_trigger_mirnat___8 = 133,\n\tmsm_mux_wcn_sw___3 = 134,\n\tmsm_mux_wcn_sw_ctrl___3 = 135,\n\tmsm_mux_____35 = 136,\n};\n\nenum smbios_attr_enum {\n\tSMBIOS_ATTR_NONE = 0,\n\tSMBIOS_ATTR_LABEL_SHOW = 1,\n\tSMBIOS_ATTR_INSTANCE_SHOW = 2,\n};\n\nenum smcwd_call {\n\tSMCWD_INIT = 0,\n\tSMCWD_SET_TIMEOUT = 1,\n\tSMCWD_ENABLE = 2,\n\tSMCWD_PET = 3,\n\tSMCWD_GET_TIMELEFT = 4,\n};\n\nenum smd_channel_state {\n\tSMD_CHANNEL_CLOSED = 0,\n\tSMD_CHANNEL_OPENING = 1,\n\tSMD_CHANNEL_OPENED = 2,\n\tSMD_CHANNEL_FLUSHING = 3,\n\tSMD_CHANNEL_CLOSING = 4,\n\tSMD_CHANNEL_RESET = 5,\n\tSMD_CHANNEL_RESET_OPENING = 6,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum snoop_when {\n\tSUBMIT = 0,\n\tCOMPLETE = 1,\n};\n\nenum soc_pad_ctrl_type {\n\tSOC_PAD_SD = 0,\n\tSOC_PAD_FIXED_1_8V = 1,\n};\n\nenum soc_type {\n\tSOC_ARCH_EXYNOS3250 = 1,\n\tSOC_ARCH_EXYNOS4210 = 2,\n\tSOC_ARCH_EXYNOS4412 = 3,\n\tSOC_ARCH_EXYNOS5250 = 4,\n\tSOC_ARCH_EXYNOS5260 = 5,\n\tSOC_ARCH_EXYNOS5420 = 6,\n\tSOC_ARCH_EXYNOS5420_TRIMINFO = 7,\n\tSOC_ARCH_EXYNOS5433 = 8,\n\tSOC_ARCH_EXYNOS7 = 9,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum spectre_v4_policy {\n\tSPECTRE_V4_POLICY_MITIGATION_DYNAMIC = 0,\n\tSPECTRE_V4_POLICY_MITIGATION_ENABLED = 1,\n\tSPECTRE_V4_POLICY_MITIGATION_DISABLED = 2,\n};\n\nenum spi_mem_data_dir {\n\tSPI_MEM_NO_DATA = 0,\n\tSPI_MEM_DATA_IN = 1,\n\tSPI_MEM_DATA_OUT = 2,\n};\n\nenum spi_nor_cmd_ext {\n\tSPI_NOR_EXT_NONE = 0,\n\tSPI_NOR_EXT_REPEAT = 1,\n\tSPI_NOR_EXT_INVERT = 2,\n\tSPI_NOR_EXT_HEX = 3,\n};\n\nenum spi_nor_option_flags {\n\tSNOR_F_HAS_SR_TB = 1,\n\tSNOR_F_NO_OP_CHIP_ERASE = 2,\n\tSNOR_F_BROKEN_RESET = 4,\n\tSNOR_F_4B_OPCODES = 8,\n\tSNOR_F_HAS_4BAIT = 16,\n\tSNOR_F_HAS_LOCK = 32,\n\tSNOR_F_HAS_16BIT_SR = 64,\n\tSNOR_F_NO_READ_CR = 128,\n\tSNOR_F_HAS_SR_TB_BIT6 = 256,\n\tSNOR_F_HAS_4BIT_BP = 512,\n\tSNOR_F_HAS_SR_BP3_BIT6 = 1024,\n\tSNOR_F_IO_MODE_EN_VOLATILE = 2048,\n\tSNOR_F_SOFT_RESET = 4096,\n\tSNOR_F_SWP_IS_VOLATILE = 8192,\n\tSNOR_F_RWW = 16384,\n\tSNOR_F_ECC = 32768,\n\tSNOR_F_NO_WP = 65536,\n\tSNOR_F_SWAP16 = 131072,\n};\n\nenum spi_nor_pp_command_index {\n\tSNOR_CMD_PP = 0,\n\tSNOR_CMD_PP_1_1_4 = 1,\n\tSNOR_CMD_PP_1_4_4 = 2,\n\tSNOR_CMD_PP_4_4_4 = 3,\n\tSNOR_CMD_PP_1_1_8 = 4,\n\tSNOR_CMD_PP_1_8_8 = 5,\n\tSNOR_CMD_PP_8_8_8 = 6,\n\tSNOR_CMD_PP_8_8_8_DTR = 7,\n\tSNOR_CMD_PP_MAX = 8,\n};\n\nenum spi_nor_protocol {\n\tSNOR_PROTO_1_1_1 = 65793,\n\tSNOR_PROTO_1_1_2 = 65794,\n\tSNOR_PROTO_1_1_4 = 65796,\n\tSNOR_PROTO_1_1_8 = 65800,\n\tSNOR_PROTO_1_2_2 = 66050,\n\tSNOR_PROTO_1_4_4 = 66564,\n\tSNOR_PROTO_1_8_8 = 67592,\n\tSNOR_PROTO_2_2_2 = 131586,\n\tSNOR_PROTO_4_4_4 = 263172,\n\tSNOR_PROTO_8_8_8 = 526344,\n\tSNOR_PROTO_1_1_1_DTR = 16843009,\n\tSNOR_PROTO_1_2_2_DTR = 16843266,\n\tSNOR_PROTO_1_4_4_DTR = 16843780,\n\tSNOR_PROTO_1_8_8_DTR = 16844808,\n\tSNOR_PROTO_8_8_8_DTR = 17303560,\n};\n\nenum spi_nor_read_command_index {\n\tSNOR_CMD_READ = 0,\n\tSNOR_CMD_READ_FAST = 1,\n\tSNOR_CMD_READ_1_1_1_DTR = 2,\n\tSNOR_CMD_READ_1_1_2 = 3,\n\tSNOR_CMD_READ_1_2_2 = 4,\n\tSNOR_CMD_READ_2_2_2 = 5,\n\tSNOR_CMD_READ_1_2_2_DTR = 6,\n\tSNOR_CMD_READ_1_1_4 = 7,\n\tSNOR_CMD_READ_1_4_4 = 8,\n\tSNOR_CMD_READ_4_4_4 = 9,\n\tSNOR_CMD_READ_1_4_4_DTR = 10,\n\tSNOR_CMD_READ_1_1_8 = 11,\n\tSNOR_CMD_READ_1_8_8 = 12,\n\tSNOR_CMD_READ_8_8_8 = 13,\n\tSNOR_CMD_READ_1_8_8_DTR = 14,\n\tSNOR_CMD_READ_8_8_8_DTR = 15,\n\tSNOR_CMD_READ_MAX = 16,\n};\n\nenum split_type {\n\tSPLIT_TYPE_UNIFORM = 0,\n\tSPLIT_TYPE_NON_UNIFORM = 1,\n};\n\nenum spmi_boost_byp_registers {\n\tSPMI_BOOST_BYP_REG_CURRENT_LIMIT = 75,\n};\n\nenum spmi_boost_registers {\n\tSPMI_BOOST_REG_CURRENT_LIMIT = 74,\n};\n\nenum spmi_common_control_register_index {\n\tSPMI_COMMON_IDX_VOLTAGE_RANGE = 0,\n\tSPMI_COMMON_IDX_VOLTAGE_SET = 1,\n\tSPMI_COMMON_IDX_MODE = 5,\n\tSPMI_COMMON_IDX_ENABLE = 6,\n};\n\nenum spmi_common_regulator_registers {\n\tSPMI_COMMON_REG_DIG_MAJOR_REV = 1,\n\tSPMI_COMMON_REG_TYPE = 4,\n\tSPMI_COMMON_REG_SUBTYPE = 5,\n\tSPMI_COMMON_REG_VOLTAGE_RANGE = 64,\n\tSPMI_COMMON_REG_VOLTAGE_SET = 65,\n\tSPMI_COMMON_REG_MODE = 69,\n\tSPMI_COMMON_REG_ENABLE = 70,\n\tSPMI_COMMON_REG_PULL_DOWN = 72,\n\tSPMI_COMMON_REG_SOFT_START = 76,\n\tSPMI_COMMON_REG_STEP_CTRL = 97,\n};\n\nenum spmi_ftsmps426_regulator_registers {\n\tSPMI_FTSMPS426_REG_VOLTAGE_LSB = 64,\n\tSPMI_FTSMPS426_REG_VOLTAGE_MSB = 65,\n\tSPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 104,\n\tSPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 105,\n};\n\nenum spmi_hfsmps_regulator_registers {\n\tSPMI_HFSMPS_REG_STEP_CTRL = 60,\n\tSPMI_HFSMPS_REG_PULL_DOWN = 160,\n};\n\nenum spmi_regulator_logical_type {\n\tSPMI_REGULATOR_LOGICAL_TYPE_SMPS = 0,\n\tSPMI_REGULATOR_LOGICAL_TYPE_LDO = 1,\n\tSPMI_REGULATOR_LOGICAL_TYPE_VS = 2,\n\tSPMI_REGULATOR_LOGICAL_TYPE_BOOST = 3,\n\tSPMI_REGULATOR_LOGICAL_TYPE_FTSMPS = 4,\n\tSPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP = 5,\n\tSPMI_REGULATOR_LOGICAL_TYPE_LN_LDO = 6,\n\tSPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS = 7,\n\tSPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS = 8,\n\tSPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO = 9,\n\tSPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426 = 10,\n\tSPMI_REGULATOR_LOGICAL_TYPE_HFS430 = 11,\n\tSPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3 = 12,\n\tSPMI_REGULATOR_LOGICAL_TYPE_LDO_510 = 13,\n\tSPMI_REGULATOR_LOGICAL_TYPE_HFSMPS = 14,\n};\n\nenum spmi_regulator_subtype {\n\tSPMI_REGULATOR_SUBTYPE_GP_CTL = 8,\n\tSPMI_REGULATOR_SUBTYPE_RF_CTL = 9,\n\tSPMI_REGULATOR_SUBTYPE_N50 = 1,\n\tSPMI_REGULATOR_SUBTYPE_N150 = 2,\n\tSPMI_REGULATOR_SUBTYPE_N300 = 3,\n\tSPMI_REGULATOR_SUBTYPE_N600 = 4,\n\tSPMI_REGULATOR_SUBTYPE_N1200 = 5,\n\tSPMI_REGULATOR_SUBTYPE_N600_ST = 6,\n\tSPMI_REGULATOR_SUBTYPE_N1200_ST = 7,\n\tSPMI_REGULATOR_SUBTYPE_N900_ST = 20,\n\tSPMI_REGULATOR_SUBTYPE_N300_ST = 21,\n\tSPMI_REGULATOR_SUBTYPE_P50 = 8,\n\tSPMI_REGULATOR_SUBTYPE_P150 = 9,\n\tSPMI_REGULATOR_SUBTYPE_P300 = 10,\n\tSPMI_REGULATOR_SUBTYPE_P600 = 11,\n\tSPMI_REGULATOR_SUBTYPE_P1200 = 12,\n\tSPMI_REGULATOR_SUBTYPE_LN = 16,\n\tSPMI_REGULATOR_SUBTYPE_LV_P50 = 40,\n\tSPMI_REGULATOR_SUBTYPE_LV_P150 = 41,\n\tSPMI_REGULATOR_SUBTYPE_LV_P300 = 42,\n\tSPMI_REGULATOR_SUBTYPE_LV_P600 = 43,\n\tSPMI_REGULATOR_SUBTYPE_LV_P1200 = 44,\n\tSPMI_REGULATOR_SUBTYPE_LV_P450 = 45,\n\tSPMI_REGULATOR_SUBTYPE_HT_N300_ST = 48,\n\tSPMI_REGULATOR_SUBTYPE_HT_N600_ST = 49,\n\tSPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 50,\n\tSPMI_REGULATOR_SUBTYPE_HT_LVP150 = 59,\n\tSPMI_REGULATOR_SUBTYPE_HT_LVP300 = 60,\n\tSPMI_REGULATOR_SUBTYPE_L660_N300_ST = 66,\n\tSPMI_REGULATOR_SUBTYPE_L660_N600_ST = 67,\n\tSPMI_REGULATOR_SUBTYPE_L660_P50 = 70,\n\tSPMI_REGULATOR_SUBTYPE_L660_P150 = 71,\n\tSPMI_REGULATOR_SUBTYPE_L660_P600 = 73,\n\tSPMI_REGULATOR_SUBTYPE_L660_LVP150 = 77,\n\tSPMI_REGULATOR_SUBTYPE_L660_LVP600 = 79,\n\tSPMI_REGULATOR_SUBTYPE_LV100 = 1,\n\tSPMI_REGULATOR_SUBTYPE_LV300 = 2,\n\tSPMI_REGULATOR_SUBTYPE_MV300 = 8,\n\tSPMI_REGULATOR_SUBTYPE_MV500 = 9,\n\tSPMI_REGULATOR_SUBTYPE_HDMI = 16,\n\tSPMI_REGULATOR_SUBTYPE_OTG = 17,\n\tSPMI_REGULATOR_SUBTYPE_5V_BOOST = 1,\n\tSPMI_REGULATOR_SUBTYPE_FTS_CTL = 8,\n\tSPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 9,\n\tSPMI_REGULATOR_SUBTYPE_FTS426_CTL = 10,\n\tSPMI_REGULATOR_SUBTYPE_BB_2A = 1,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 13,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 14,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 15,\n\tSPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 16,\n\tSPMI_REGULATOR_SUBTYPE_HFS430 = 10,\n\tSPMI_REGULATOR_SUBTYPE_HT_P150 = 53,\n\tSPMI_REGULATOR_SUBTYPE_HT_P600 = 61,\n\tSPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 10,\n\tSPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 11,\n\tSPMI_REGULATOR_SUBTYPE_LV_P150_510 = 113,\n\tSPMI_REGULATOR_SUBTYPE_LV_P300_510 = 114,\n\tSPMI_REGULATOR_SUBTYPE_LV_P600_510 = 115,\n\tSPMI_REGULATOR_SUBTYPE_N300_510 = 106,\n\tSPMI_REGULATOR_SUBTYPE_N600_510 = 107,\n\tSPMI_REGULATOR_SUBTYPE_N1200_510 = 108,\n\tSPMI_REGULATOR_SUBTYPE_MV_P50_510 = 122,\n\tSPMI_REGULATOR_SUBTYPE_MV_P150_510 = 123,\n\tSPMI_REGULATOR_SUBTYPE_MV_P600_510 = 125,\n};\n\nenum spmi_regulator_type {\n\tSPMI_REGULATOR_TYPE_BUCK = 3,\n\tSPMI_REGULATOR_TYPE_LDO = 4,\n\tSPMI_REGULATOR_TYPE_VS = 5,\n\tSPMI_REGULATOR_TYPE_BOOST = 27,\n\tSPMI_REGULATOR_TYPE_FTS = 28,\n\tSPMI_REGULATOR_TYPE_BOOST_BYP = 31,\n\tSPMI_REGULATOR_TYPE_ULT_LDO = 33,\n\tSPMI_REGULATOR_TYPE_ULT_BUCK = 34,\n};\n\nenum spmi_saw3_registers {\n\tSAW3_SECURE = 0,\n\tSAW3_ID = 4,\n\tSAW3_SPM_STS = 12,\n\tSAW3_AVS_STS = 16,\n\tSAW3_PMIC_STS = 20,\n\tSAW3_RST = 24,\n\tSAW3_VCTL = 28,\n\tSAW3_AVS_CTL = 32,\n\tSAW3_AVS_LIMIT = 36,\n\tSAW3_AVS_DLY = 40,\n\tSAW3_AVS_HYSTERESIS = 44,\n\tSAW3_SPM_STS2 = 56,\n\tSAW3_SPM_PMIC_DATA_3 = 76,\n\tSAW3_VERSION = 4048,\n};\n\nenum spmi_vs_registers {\n\tSPMI_VS_REG_OCP = 74,\n\tSPMI_VS_REG_SOFT_START = 76,\n};\n\nenum spmi_vs_soft_start_str {\n\tSPMI_VS_SOFT_START_STR_0P05_UA = 0,\n\tSPMI_VS_SOFT_START_STR_0P25_UA = 1,\n\tSPMI_VS_SOFT_START_STR_0P55_UA = 2,\n\tSPMI_VS_SOFT_START_STR_0P75_UA = 3,\n\tSPMI_VS_SOFT_START_STR_HW_DEFAULT = 4,\n};\n\nenum squashfs_param {\n\tOpt_errors___3 = 0,\n\tOpt_threads = 1,\n};\n\nenum sr_loc_attr {\n\tSR_LOC_MEMORY = 0,\n\tSR_LOC_LOADED = 1,\n\tSR_LOC_MAPPED = 2,\n\tSR_LOC_XLATED = 4,\n\tSR_LOC_SPECIAL = 8,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum ssp_clkdelay {\n\tSSP_FEEDBACK_CLK_DELAY_NONE = 0,\n\tSSP_FEEDBACK_CLK_DELAY_1T = 1,\n\tSSP_FEEDBACK_CLK_DELAY_2T = 2,\n\tSSP_FEEDBACK_CLK_DELAY_3T = 3,\n\tSSP_FEEDBACK_CLK_DELAY_4T = 4,\n\tSSP_FEEDBACK_CLK_DELAY_5T = 5,\n\tSSP_FEEDBACK_CLK_DELAY_6T = 6,\n\tSSP_FEEDBACK_CLK_DELAY_7T = 7,\n};\n\nenum ssp_data_size {\n\tSSP_DATA_BITS_4 = 3,\n\tSSP_DATA_BITS_5 = 4,\n\tSSP_DATA_BITS_6 = 5,\n\tSSP_DATA_BITS_7 = 6,\n\tSSP_DATA_BITS_8 = 7,\n\tSSP_DATA_BITS_9 = 8,\n\tSSP_DATA_BITS_10 = 9,\n\tSSP_DATA_BITS_11 = 10,\n\tSSP_DATA_BITS_12 = 11,\n\tSSP_DATA_BITS_13 = 12,\n\tSSP_DATA_BITS_14 = 13,\n\tSSP_DATA_BITS_15 = 14,\n\tSSP_DATA_BITS_16 = 15,\n\tSSP_DATA_BITS_17 = 16,\n\tSSP_DATA_BITS_18 = 17,\n\tSSP_DATA_BITS_19 = 18,\n\tSSP_DATA_BITS_20 = 19,\n\tSSP_DATA_BITS_21 = 20,\n\tSSP_DATA_BITS_22 = 21,\n\tSSP_DATA_BITS_23 = 22,\n\tSSP_DATA_BITS_24 = 23,\n\tSSP_DATA_BITS_25 = 24,\n\tSSP_DATA_BITS_26 = 25,\n\tSSP_DATA_BITS_27 = 26,\n\tSSP_DATA_BITS_28 = 27,\n\tSSP_DATA_BITS_29 = 28,\n\tSSP_DATA_BITS_30 = 29,\n\tSSP_DATA_BITS_31 = 30,\n\tSSP_DATA_BITS_32 = 31,\n};\n\nenum ssp_duplex {\n\tSSP_MICROWIRE_CHANNEL_FULL_DUPLEX = 0,\n\tSSP_MICROWIRE_CHANNEL_HALF_DUPLEX = 1,\n};\n\nenum ssp_hierarchy {\n\tSSP_MASTER = 0,\n\tSSP_SLAVE = 1,\n};\n\nenum ssp_interface {\n\tSSP_INTERFACE_MOTOROLA_SPI = 0,\n\tSSP_INTERFACE_TI_SYNC_SERIAL = 1,\n\tSSP_INTERFACE_NATIONAL_MICROWIRE = 2,\n\tSSP_INTERFACE_UNIDIRECTIONAL = 3,\n};\n\nenum ssp_loopback {\n\tLOOPBACK_DISABLED = 0,\n\tLOOPBACK_ENABLED = 1,\n};\n\nenum ssp_microwire_ctrl_len {\n\tSSP_BITS_4 = 3,\n\tSSP_BITS_5 = 4,\n\tSSP_BITS_6 = 5,\n\tSSP_BITS_7 = 6,\n\tSSP_BITS_8 = 7,\n\tSSP_BITS_9 = 8,\n\tSSP_BITS_10 = 9,\n\tSSP_BITS_11 = 10,\n\tSSP_BITS_12 = 11,\n\tSSP_BITS_13 = 12,\n\tSSP_BITS_14 = 13,\n\tSSP_BITS_15 = 14,\n\tSSP_BITS_16 = 15,\n\tSSP_BITS_17 = 16,\n\tSSP_BITS_18 = 17,\n\tSSP_BITS_19 = 18,\n\tSSP_BITS_20 = 19,\n\tSSP_BITS_21 = 20,\n\tSSP_BITS_22 = 21,\n\tSSP_BITS_23 = 22,\n\tSSP_BITS_24 = 23,\n\tSSP_BITS_25 = 24,\n\tSSP_BITS_26 = 25,\n\tSSP_BITS_27 = 26,\n\tSSP_BITS_28 = 27,\n\tSSP_BITS_29 = 28,\n\tSSP_BITS_30 = 29,\n\tSSP_BITS_31 = 30,\n\tSSP_BITS_32 = 31,\n};\n\nenum ssp_microwire_wait_state {\n\tSSP_MWIRE_WAIT_ZERO = 0,\n\tSSP_MWIRE_WAIT_ONE = 1,\n};\n\nenum ssp_mode {\n\tINTERRUPT_TRANSFER = 0,\n\tPOLLING_TRANSFER = 1,\n\tDMA_TRANSFER = 2,\n};\n\nenum ssp_reading {\n\tREADING_NULL = 0,\n\tREADING_U8 = 1,\n\tREADING_U16 = 2,\n\tREADING_U32 = 3,\n};\n\nenum ssp_rx_endian {\n\tSSP_RX_MSB = 0,\n\tSSP_RX_LSB = 1,\n};\n\nenum ssp_rx_level_trig {\n\tSSP_RX_1_OR_MORE_ELEM = 0,\n\tSSP_RX_4_OR_MORE_ELEM = 1,\n\tSSP_RX_8_OR_MORE_ELEM = 2,\n\tSSP_RX_16_OR_MORE_ELEM = 3,\n\tSSP_RX_32_OR_MORE_ELEM = 4,\n};\n\nenum ssp_spi_clk_phase {\n\tSSP_CLK_FIRST_EDGE = 0,\n\tSSP_CLK_SECOND_EDGE = 1,\n};\n\nenum ssp_spi_clk_pol {\n\tSSP_CLK_POL_IDLE_LOW = 0,\n\tSSP_CLK_POL_IDLE_HIGH = 1,\n};\n\nenum ssp_tx_endian {\n\tSSP_TX_MSB = 0,\n\tSSP_TX_LSB = 1,\n};\n\nenum ssp_tx_level_trig {\n\tSSP_TX_1_OR_MORE_EMPTY_LOC = 0,\n\tSSP_TX_4_OR_MORE_EMPTY_LOC = 1,\n\tSSP_TX_8_OR_MORE_EMPTY_LOC = 2,\n\tSSP_TX_16_OR_MORE_EMPTY_LOC = 3,\n\tSSP_TX_32_OR_MORE_EMPTY_LOC = 4,\n};\n\nenum ssp_writing {\n\tWRITING_NULL = 0,\n\tWRITING_U8 = 1,\n\tWRITING_U16 = 2,\n\tWRITING_U32 = 3,\n};\n\nenum ssusb_uwk_vers {\n\tSSUSB_UWK_V1 = 1,\n\tSSUSB_UWK_V2 = 2,\n\tSSUSB_UWK_V1_1 = 101,\n\tSSUSB_UWK_V1_2 = 102,\n\tSSUSB_UWK_V1_3 = 103,\n\tSSUSB_UWK_V1_4 = 104,\n\tSSUSB_UWK_V1_5 = 105,\n\tSSUSB_UWK_V1_6 = 106,\n};\n\nenum ssusb_uwk_vers___2 {\n\tSSUSB_UWK_V1___2 = 1,\n\tSSUSB_UWK_V2___2 = 2,\n\tSSUSB_UWK_V1_1___2 = 101,\n\tSSUSB_UWK_V1_2___2 = 102,\n\tSSUSB_UWK_V1_3___2 = 103,\n\tSSUSB_UWK_V1_5___2 = 105,\n\tSSUSB_UWK_V1_6___2 = 106,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum state_protect_how4 {\n\tSP4_NONE = 0,\n\tSP4_MACH_CRED = 1,\n\tSP4_SSV = 2,\n};\n\nenum status_css {\n\tCSS_TCPUDPCSOK = 128,\n\tCSS_ISUDP = 64,\n\tCSS_ISTCP = 32,\n\tCSS_ISIPFRAG = 16,\n\tCSS_ISIPV6 = 8,\n\tCSS_IPV4CSUMOK = 4,\n\tCSS_ISIPV4 = 2,\n\tCSS_LINK_BIT = 1,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum stratix10_svc_command_code {\n\tCOMMAND_NOOP = 0,\n\tCOMMAND_RECONFIG = 1,\n\tCOMMAND_RECONFIG_DATA_SUBMIT = 2,\n\tCOMMAND_RECONFIG_DATA_CLAIM = 3,\n\tCOMMAND_RECONFIG_STATUS = 4,\n\tCOMMAND_RSU_STATUS = 10,\n\tCOMMAND_RSU_UPDATE = 11,\n\tCOMMAND_RSU_NOTIFY = 12,\n\tCOMMAND_RSU_RETRY = 13,\n\tCOMMAND_RSU_MAX_RETRY = 14,\n\tCOMMAND_RSU_DCMF_VERSION = 15,\n\tCOMMAND_RSU_DCMF_STATUS = 16,\n\tCOMMAND_FIRMWARE_VERSION = 17,\n\tCOMMAND_RSU_GET_SPT_TABLE = 18,\n\tCOMMAND_FCS_REQUEST_SERVICE = 20,\n\tCOMMAND_FCS_SEND_CERTIFICATE = 21,\n\tCOMMAND_FCS_GET_PROVISION_DATA = 22,\n\tCOMMAND_FCS_DATA_ENCRYPTION = 23,\n\tCOMMAND_FCS_DATA_DECRYPTION = 24,\n\tCOMMAND_FCS_RANDOM_NUMBER_GEN = 25,\n\tCOMMAND_POLL_SERVICE_STATUS = 40,\n\tCOMMAND_MBOX_SEND_CMD = 100,\n\tCOMMAND_SMC_SVC_VERSION = 200,\n\tCOMMAND_HWMON_READTEMP = 201,\n\tCOMMAND_HWMON_READVOLT = 202,\n};\n\nenum streamid_type {\n\tSTREAMID_TYPE_RESERVED = 0,\n\tSTREAMID_TYPE_NULL = 1,\n\tSTREAMID_TYPE_SMAC = 2,\n};\n\nenum streamid_vlan_tagged {\n\tSTREAMID_VLAN_RESERVED = 0,\n\tSTREAMID_VLAN_TAGGED = 1,\n\tSTREAMID_VLAN_UNTAGGED = 2,\n\tSTREAMID_VLAN_ALL = 3,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum stripetype4 {\n\tSTRIPE_SPARSE = 1,\n\tSTRIPE_DENSE = 2,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\nenum sunxi_desc_bias_voltage {\n\tBIAS_VOLTAGE_NONE = 0,\n\tBIAS_VOLTAGE_GRP_CONFIG = 1,\n\tBIAS_VOLTAGE_PIO_POW_MODE_SEL = 2,\n\tBIAS_VOLTAGE_PIO_POW_MODE_CTL = 3,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum suspend_stat_step {\n\tSUSPEND_WORKING = 0,\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nenum svc_auth_status {\n\tSVC_GARBAGE = 1,\n\tSVC_VALID = 2,\n\tSVC_NEGATIVE = 3,\n\tSVC_OK = 4,\n\tSVC_DROP = 5,\n\tSVC_CLOSE = 6,\n\tSVC_DENIED = 7,\n\tSVC_PENDING = 8,\n\tSVC_COMPLETE = 9,\n};\n\nenum sw_activity {\n\tOFF___3 = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum switchdev_attr_id {\n\tSWITCHDEV_ATTR_ID_UNDEFINED = 0,\n\tSWITCHDEV_ATTR_ID_PORT_STP_STATE = 1,\n\tSWITCHDEV_ATTR_ID_PORT_MST_STATE = 2,\n\tSWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS = 3,\n\tSWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS = 4,\n\tSWITCHDEV_ATTR_ID_PORT_MROUTER = 5,\n\tSWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME = 6,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING = 7,\n\tSWITCHDEV_ATTR_ID_BRIDGE_VLAN_PROTOCOL = 8,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED = 9,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MROUTER = 10,\n\tSWITCHDEV_ATTR_ID_BRIDGE_MST = 11,\n\tSWITCHDEV_ATTR_ID_MRP_PORT_ROLE = 12,\n\tSWITCHDEV_ATTR_ID_VLAN_MSTI = 13,\n};\n\nenum switchdev_notifier_type {\n\tSWITCHDEV_FDB_ADD_TO_BRIDGE = 1,\n\tSWITCHDEV_FDB_DEL_TO_BRIDGE = 2,\n\tSWITCHDEV_FDB_ADD_TO_DEVICE = 3,\n\tSWITCHDEV_FDB_DEL_TO_DEVICE = 4,\n\tSWITCHDEV_FDB_OFFLOADED = 5,\n\tSWITCHDEV_FDB_FLUSH_TO_BRIDGE = 6,\n\tSWITCHDEV_PORT_OBJ_ADD = 7,\n\tSWITCHDEV_PORT_OBJ_DEL = 8,\n\tSWITCHDEV_PORT_ATTR_SET = 9,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_BRIDGE = 10,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_BRIDGE = 11,\n\tSWITCHDEV_VXLAN_FDB_ADD_TO_DEVICE = 12,\n\tSWITCHDEV_VXLAN_FDB_DEL_TO_DEVICE = 13,\n\tSWITCHDEV_VXLAN_FDB_OFFLOADED = 14,\n\tSWITCHDEV_BRPORT_OFFLOADED = 15,\n\tSWITCHDEV_BRPORT_UNOFFLOADED = 16,\n\tSWITCHDEV_BRPORT_REPLAY = 17,\n};\n\nenum switchdev_obj_id {\n\tSWITCHDEV_OBJ_ID_UNDEFINED = 0,\n\tSWITCHDEV_OBJ_ID_PORT_VLAN = 1,\n\tSWITCHDEV_OBJ_ID_PORT_MDB = 2,\n\tSWITCHDEV_OBJ_ID_HOST_MDB = 3,\n\tSWITCHDEV_OBJ_ID_MRP = 4,\n\tSWITCHDEV_OBJ_ID_RING_TEST_MRP = 5,\n\tSWITCHDEV_OBJ_ID_RING_ROLE_MRP = 6,\n\tSWITCHDEV_OBJ_ID_RING_STATE_MRP = 7,\n\tSWITCHDEV_OBJ_ID_IN_TEST_MRP = 8,\n\tSWITCHDEV_OBJ_ID_IN_ROLE_MRP = 9,\n\tSWITCHDEV_OBJ_ID_IN_STATE_MRP = 10,\n};\n\nenum swxilim_bits {\n\tSWXILIM_2100_MA = 0,\n\tSWXILIM_2600_MA = 1,\n\tSWXILIM_3000_MA = 2,\n\tSWXILIM_4500_MA = 3,\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum sys_powerdown {\n\tSYS_AFTR = 0,\n\tSYS_LPA = 1,\n\tSYS_SLEEP = 2,\n\tNUM_SYS_POWERDOWN = 3,\n};\n\nenum sysc_clocks {\n\tSYSC_FCK = 0,\n\tSYSC_ICK = 1,\n\tSYSC_OPTFCK0 = 2,\n\tSYSC_OPTFCK1 = 3,\n\tSYSC_OPTFCK2 = 4,\n\tSYSC_OPTFCK3 = 5,\n\tSYSC_OPTFCK4 = 6,\n\tSYSC_OPTFCK5 = 7,\n\tSYSC_OPTFCK6 = 8,\n\tSYSC_OPTFCK7 = 9,\n\tSYSC_MAX_CLOCKS = 10,\n};\n\nenum sysc_registers {\n\tSYSC_REVISION = 0,\n\tSYSC_SYSCONFIG = 1,\n\tSYSC_SYSSTATUS = 2,\n\tSYSC_MAX_REGS = 3,\n};\n\nenum sysc_soc {\n\tSOC_UNKNOWN = 0,\n\tSOC_2420 = 1,\n\tSOC_2430 = 2,\n\tSOC_AM33 = 3,\n\tSOC_3430 = 4,\n\tSOC_AM35 = 5,\n\tSOC_3630 = 6,\n\tSOC_4430 = 7,\n\tSOC_4460 = 8,\n\tSOC_4470 = 9,\n\tSOC_5430 = 10,\n\tSOC_AM3 = 11,\n\tSOC_AM4 = 12,\n\tSOC_DRA7 = 13,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum t254_cbb_fabric_ids {\n\tT254_DCE_FABRIC_ID = 19,\n\tT254_DISP_CLUSTER_FABRIC_ID = 25,\n\tT254_C2C_FABRIC_ID = 26,\n\tT254_GPU_FABRIC_ID = 27,\n\tT254_DISP_CLUSTER_1_FABRIC_ID = 28,\n\tT254_MAX_FABRIC_ID = 29,\n};\n\nenum ta_cmd {\n\tTA_CMD_BNXT_FASTBOOT = 0,\n\tTA_CMD_BNXT_COPY_COREDUMP = 3,\n};\n\nenum tap_delay_type {\n\tPM_TAPDELAY_INPUT = 0,\n\tPM_TAPDELAY_OUTPUT = 1,\n};\n\nenum task_attribute {\n\tTASK_ATTR_SIMPLE = 0,\n\tTASK_ATTR_HOQ = 1,\n\tTASK_ATTR_ORDERED = 2,\n\tTASK_ATTR_ACA = 4,\n};\n\nenum task_disposition {\n\tTASK_IS_DONE = 0,\n\tTASK_IS_ABORTED = 1,\n\tTASK_IS_AT_LU = 2,\n\tTASK_IS_NOT_AT_LU = 3,\n\tTASK_ABORT_FAILED = 4,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_fifo_command {\n\tTC_FIFO_REPLACE = 0,\n\tTC_FIFO_DESTROY = 1,\n\tTC_FIFO_STATS = 2,\n};\n\nenum tc_link_layer {\n\tTC_LINKLAYER_UNAWARE = 0,\n\tTC_LINKLAYER_ETHERNET = 1,\n\tTC_LINKLAYER_ATM = 2,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_root_command {\n\tTC_ROOT_GRAFT = 0,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tc_taprio_qopt_cmd {\n\tTAPRIO_CMD_REPLACE = 0,\n\tTAPRIO_CMD_DESTROY = 1,\n\tTAPRIO_CMD_STATS = 2,\n\tTAPRIO_CMD_QUEUE_STATS = 3,\n};\n\nenum tc_tbf_command {\n\tTC_TBF_REPLACE = 0,\n\tTC_TBF_DESTROY = 1,\n\tTC_TBF_STATS = 2,\n\tTC_TBF_GRAFT = 3,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcf_proto_ops_flags {\n\tTCF_PROTO_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_conntrack {\n\tTCP_CONNTRACK_NONE = 0,\n\tTCP_CONNTRACK_SYN_SENT = 1,\n\tTCP_CONNTRACK_SYN_RECV = 2,\n\tTCP_CONNTRACK_ESTABLISHED = 3,\n\tTCP_CONNTRACK_FIN_WAIT = 4,\n\tTCP_CONNTRACK_CLOSE_WAIT = 5,\n\tTCP_CONNTRACK_LAST_ACK = 6,\n\tTCP_CONNTRACK_TIME_WAIT = 7,\n\tTCP_CONNTRACK_CLOSE = 8,\n\tTCP_CONNTRACK_LISTEN = 9,\n\tTCP_CONNTRACK_MAX = 10,\n\tTCP_CONNTRACK_IGNORE = 11,\n\tTCP_CONNTRACK_RETRANS = 12,\n\tTCP_CONNTRACK_UNACK = 13,\n\tTCP_CONNTRACK_TIMEOUT_MAX = 14,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nenum tcpa_pc_event_ids {\n\tSMBIOS = 1,\n\tBIS_CERT = 2,\n\tPOST_BIOS_ROM = 3,\n\tESCD = 4,\n\tCMOS = 5,\n\tNVRAM = 6,\n\tOPTION_ROM_EXEC = 7,\n\tOPTION_ROM_CONFIG = 8,\n\tOPTION_ROM_MICROCODE = 10,\n\tS_CRTM_VERSION = 11,\n\tS_CRTM_CONTENTS = 12,\n\tPOST_CONTENTS = 13,\n\tHOST_TABLE_OF_DEVICES = 14,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum tee_dma_heap_id {\n\tTEE_DMA_HEAP_SECURE_VIDEO_PLAY = 1,\n\tTEE_DMA_HEAP_TRUSTED_UI = 2,\n\tTEE_DMA_HEAP_SECURE_VIDEO_RECORD = 3,\n};\n\nenum tegra124_function {\n\tTEGRA124_FUNC_SNPS = 0,\n\tTEGRA124_FUNC_XUSB = 1,\n\tTEGRA124_FUNC_UART = 2,\n\tTEGRA124_FUNC_PCIE = 3,\n\tTEGRA124_FUNC_USB3 = 4,\n\tTEGRA124_FUNC_SATA = 5,\n\tTEGRA124_FUNC_RSVD = 6,\n};\n\nenum tegra234_cbb_fabric_ids {\n\tT234_CBB_FABRIC_ID = 0,\n\tT234_SCE_FABRIC_ID = 1,\n\tT234_RCE_FABRIC_ID = 2,\n\tT234_DCE_FABRIC_ID = 3,\n\tT234_AON_FABRIC_ID = 4,\n\tT234_PSC_FABRIC_ID = 5,\n\tT234_BPMP_FABRIC_ID = 6,\n\tT234_FSI_FABRIC_ID = 7,\n\tT234_MAX_FABRIC_ID = 8,\n};\n\nenum tegra264_cbb_fabric_ids {\n\tT264_SYSTEM_CBB_FABRIC_ID = 0,\n\tT264_TOP_0_CBB_FABRIC_ID = 1,\n\tT264_VISION_CBB_FABRIC_ID = 2,\n\tT264_DISP_USB_CBB_FABRIC_ID = 3,\n\tT264_UPHY0_CBB_FABRIC_ID = 4,\n\tT264_RSVD0_FABRIC_ID = 5,\n\tT264_RSVD1_FABRIC_ID = 6,\n\tT264_RSVD2_FABRIC_ID = 7,\n\tT264_RSVD3_FABRIC_ID = 8,\n\tT264_RSVD4_FABRIC_ID = 9,\n\tT264_RSVD5_FABRIC_ID = 10,\n\tT264_AON_FABRIC_ID = 11,\n\tT264_PSC_FABRIC_ID = 12,\n\tT264_OESP_FABRIC_ID = 13,\n\tT264_APE_FABRIC_ID = 14,\n\tT264_BPMP_FABRIC_ID = 15,\n\tT264_RCE_0_FABRIC_ID = 16,\n\tT264_RCE_1_FABRIC_ID = 17,\n\tT264_RSVD6_FABRIC_ID = 18,\n\tT264_DCE_FABRIC_ID = 19,\n\tT264_FSI_FABRIC_ID = 20,\n\tT264_ISC_FABRIC_ID = 21,\n\tT264_SB_FABRIC_ID = 22,\n\tT264_ISC_CPU_FABRIC_ID = 23,\n\tT264_RSVD7_FABRIC_ID = 24,\n};\n\nenum tegra_dfll_pmu_if {\n\tTEGRA_DFLL_PMU_I2C = 0,\n\tTEGRA_DFLL_PMU_PWM = 1,\n};\n\nenum tegra_hte_type {\n\tHTE_TEGRA_TYPE_GPIO = 1,\n\tHTE_TEGRA_TYPE_LIC = 2,\n};\n\nenum tegra_icc_client_type {\n\tTEGRA_ICC_NONE = 0,\n\tTEGRA_ICC_NISO = 1,\n\tTEGRA_ICC_ISO_DISPLAY = 2,\n\tTEGRA_ICC_ISO_VI = 3,\n\tTEGRA_ICC_ISO_AUDIO = 4,\n\tTEGRA_ICC_ISO_VIFAL = 5,\n};\n\nenum tegra_io_pad {\n\tTEGRA_IO_PAD_AUDIO = 0,\n\tTEGRA_IO_PAD_AUDIO_HV = 1,\n\tTEGRA_IO_PAD_BB = 2,\n\tTEGRA_IO_PAD_CAM = 3,\n\tTEGRA_IO_PAD_COMP = 4,\n\tTEGRA_IO_PAD_CONN = 5,\n\tTEGRA_IO_PAD_CSIA = 6,\n\tTEGRA_IO_PAD_CSIB = 7,\n\tTEGRA_IO_PAD_CSIC = 8,\n\tTEGRA_IO_PAD_CSID = 9,\n\tTEGRA_IO_PAD_CSIE = 10,\n\tTEGRA_IO_PAD_CSIF = 11,\n\tTEGRA_IO_PAD_CSIG = 12,\n\tTEGRA_IO_PAD_CSIH = 13,\n\tTEGRA_IO_PAD_DAP3 = 14,\n\tTEGRA_IO_PAD_DAP5 = 15,\n\tTEGRA_IO_PAD_DBG = 16,\n\tTEGRA_IO_PAD_DEBUG_NONAO = 17,\n\tTEGRA_IO_PAD_DMIC = 18,\n\tTEGRA_IO_PAD_DMIC_HV = 19,\n\tTEGRA_IO_PAD_DP = 20,\n\tTEGRA_IO_PAD_DSI = 21,\n\tTEGRA_IO_PAD_DSIB = 22,\n\tTEGRA_IO_PAD_DSIC = 23,\n\tTEGRA_IO_PAD_DSID = 24,\n\tTEGRA_IO_PAD_EDP = 25,\n\tTEGRA_IO_PAD_EMMC = 26,\n\tTEGRA_IO_PAD_EMMC2 = 27,\n\tTEGRA_IO_PAD_EQOS = 28,\n\tTEGRA_IO_PAD_GPIO = 29,\n\tTEGRA_IO_PAD_GP_PWM2 = 30,\n\tTEGRA_IO_PAD_GP_PWM3 = 31,\n\tTEGRA_IO_PAD_HDMI = 32,\n\tTEGRA_IO_PAD_HDMI_DP0 = 33,\n\tTEGRA_IO_PAD_HDMI_DP1 = 34,\n\tTEGRA_IO_PAD_HDMI_DP2 = 35,\n\tTEGRA_IO_PAD_HDMI_DP3 = 36,\n\tTEGRA_IO_PAD_HSIC = 37,\n\tTEGRA_IO_PAD_HV = 38,\n\tTEGRA_IO_PAD_LVDS = 39,\n\tTEGRA_IO_PAD_MIPI_BIAS = 40,\n\tTEGRA_IO_PAD_NAND = 41,\n\tTEGRA_IO_PAD_PEX_BIAS = 42,\n\tTEGRA_IO_PAD_PEX_CLK_BIAS = 43,\n\tTEGRA_IO_PAD_PEX_CLK1 = 44,\n\tTEGRA_IO_PAD_PEX_CLK2 = 45,\n\tTEGRA_IO_PAD_PEX_CLK3 = 46,\n\tTEGRA_IO_PAD_PEX_CLK_2_BIAS = 47,\n\tTEGRA_IO_PAD_PEX_CLK_2 = 48,\n\tTEGRA_IO_PAD_PEX_CNTRL = 49,\n\tTEGRA_IO_PAD_PEX_CTL2 = 50,\n\tTEGRA_IO_PAD_PEX_L0_RST = 51,\n\tTEGRA_IO_PAD_PEX_L1_RST = 52,\n\tTEGRA_IO_PAD_PEX_L5_RST = 53,\n\tTEGRA_IO_PAD_PWR_CTL = 54,\n\tTEGRA_IO_PAD_SDMMC1 = 55,\n\tTEGRA_IO_PAD_SDMMC1_HV = 56,\n\tTEGRA_IO_PAD_SDMMC2 = 57,\n\tTEGRA_IO_PAD_SDMMC2_HV = 58,\n\tTEGRA_IO_PAD_SDMMC3 = 59,\n\tTEGRA_IO_PAD_SDMMC3_HV = 60,\n\tTEGRA_IO_PAD_SDMMC4 = 61,\n\tTEGRA_IO_PAD_SOC_GPIO10 = 62,\n\tTEGRA_IO_PAD_SOC_GPIO12 = 63,\n\tTEGRA_IO_PAD_SOC_GPIO13 = 64,\n\tTEGRA_IO_PAD_SOC_GPIO53 = 65,\n\tTEGRA_IO_PAD_SPI = 66,\n\tTEGRA_IO_PAD_SPI_HV = 67,\n\tTEGRA_IO_PAD_SYS_DDC = 68,\n\tTEGRA_IO_PAD_UART = 69,\n\tTEGRA_IO_PAD_UART4 = 70,\n\tTEGRA_IO_PAD_UART5 = 71,\n\tTEGRA_IO_PAD_UFS = 72,\n\tTEGRA_IO_PAD_USB0 = 73,\n\tTEGRA_IO_PAD_USB1 = 74,\n\tTEGRA_IO_PAD_USB2 = 75,\n\tTEGRA_IO_PAD_USB3 = 76,\n\tTEGRA_IO_PAD_USB_BIAS = 77,\n\tTEGRA_IO_PAD_AO_HV = 78,\n};\n\nenum tegra_ivc_state {\n\tTEGRA_IVC_STATE_ESTABLISHED = 0,\n\tTEGRA_IVC_STATE_SYNC = 1,\n\tTEGRA_IVC_STATE_ACK = 2,\n};\n\nenum tegra_mux {\n\tTEGRA_MUX_AUD = 0,\n\tTEGRA_MUX_BCL = 1,\n\tTEGRA_MUX_BLINK = 2,\n\tTEGRA_MUX_CCLA = 3,\n\tTEGRA_MUX_CEC = 4,\n\tTEGRA_MUX_CLDVFS = 5,\n\tTEGRA_MUX_CLK = 6,\n\tTEGRA_MUX_CORE = 7,\n\tTEGRA_MUX_CPU = 8,\n\tTEGRA_MUX_DISPLAYA = 9,\n\tTEGRA_MUX_DISPLAYB = 10,\n\tTEGRA_MUX_DMIC1 = 11,\n\tTEGRA_MUX_DMIC2 = 12,\n\tTEGRA_MUX_DMIC3 = 13,\n\tTEGRA_MUX_DP = 14,\n\tTEGRA_MUX_DTV = 15,\n\tTEGRA_MUX_EXTPERIPH3 = 16,\n\tTEGRA_MUX_I2C1 = 17,\n\tTEGRA_MUX_I2C2 = 18,\n\tTEGRA_MUX_I2C3 = 19,\n\tTEGRA_MUX_I2CPMU = 20,\n\tTEGRA_MUX_I2CVI = 21,\n\tTEGRA_MUX_I2S1 = 22,\n\tTEGRA_MUX_I2S2 = 23,\n\tTEGRA_MUX_I2S3 = 24,\n\tTEGRA_MUX_I2S4A = 25,\n\tTEGRA_MUX_I2S4B = 26,\n\tTEGRA_MUX_I2S5A = 27,\n\tTEGRA_MUX_I2S5B = 28,\n\tTEGRA_MUX_IQC0 = 29,\n\tTEGRA_MUX_IQC1 = 30,\n\tTEGRA_MUX_JTAG = 31,\n\tTEGRA_MUX_PE = 32,\n\tTEGRA_MUX_PE0 = 33,\n\tTEGRA_MUX_PE1 = 34,\n\tTEGRA_MUX_PMI = 35,\n\tTEGRA_MUX_PWM0 = 36,\n\tTEGRA_MUX_PWM1 = 37,\n\tTEGRA_MUX_PWM2 = 38,\n\tTEGRA_MUX_PWM3 = 39,\n\tTEGRA_MUX_QSPI = 40,\n\tTEGRA_MUX_RSVD0 = 41,\n\tTEGRA_MUX_RSVD1 = 42,\n\tTEGRA_MUX_RSVD2 = 43,\n\tTEGRA_MUX_RSVD3 = 44,\n\tTEGRA_MUX_SATA = 45,\n\tTEGRA_MUX_SDMMC1 = 46,\n\tTEGRA_MUX_SDMMC3 = 47,\n\tTEGRA_MUX_SHUTDOWN = 48,\n\tTEGRA_MUX_SOC = 49,\n\tTEGRA_MUX_SOR0 = 50,\n\tTEGRA_MUX_SOR1 = 51,\n\tTEGRA_MUX_SPDIF = 52,\n\tTEGRA_MUX_SPI1 = 53,\n\tTEGRA_MUX_SPI2 = 54,\n\tTEGRA_MUX_SPI3 = 55,\n\tTEGRA_MUX_SPI4 = 56,\n\tTEGRA_MUX_SYS = 57,\n\tTEGRA_MUX_TOUCH = 58,\n\tTEGRA_MUX_UART = 59,\n\tTEGRA_MUX_UARTA = 60,\n\tTEGRA_MUX_UARTB = 61,\n\tTEGRA_MUX_UARTC = 62,\n\tTEGRA_MUX_UARTD = 63,\n\tTEGRA_MUX_USB = 64,\n\tTEGRA_MUX_VGP1 = 65,\n\tTEGRA_MUX_VGP2 = 66,\n\tTEGRA_MUX_VGP3 = 67,\n\tTEGRA_MUX_VGP4 = 68,\n\tTEGRA_MUX_VGP5 = 69,\n\tTEGRA_MUX_VGP6 = 70,\n\tTEGRA_MUX_VIMCLK = 71,\n\tTEGRA_MUX_VIMCLK2 = 72,\n};\n\nenum tegra_mux___2 {\n\tTEGRA_MUX_BLINK___2 = 0,\n\tTEGRA_MUX_CCLA___2 = 1,\n\tTEGRA_MUX_CEC___2 = 2,\n\tTEGRA_MUX_CLDVFS___2 = 3,\n\tTEGRA_MUX_CLK___2 = 4,\n\tTEGRA_MUX_CLK12 = 5,\n\tTEGRA_MUX_CPU___2 = 6,\n\tTEGRA_MUX_CSI = 7,\n\tTEGRA_MUX_DAP = 8,\n\tTEGRA_MUX_DAP1 = 9,\n\tTEGRA_MUX_DAP2 = 10,\n\tTEGRA_MUX_DEV3 = 11,\n\tTEGRA_MUX_DISPLAYA___2 = 12,\n\tTEGRA_MUX_DISPLAYA_ALT = 13,\n\tTEGRA_MUX_DISPLAYB___2 = 14,\n\tTEGRA_MUX_DP___2 = 15,\n\tTEGRA_MUX_DSI_B = 16,\n\tTEGRA_MUX_DTV___2 = 17,\n\tTEGRA_MUX_EXTPERIPH1 = 18,\n\tTEGRA_MUX_EXTPERIPH2 = 19,\n\tTEGRA_MUX_EXTPERIPH3___2 = 20,\n\tTEGRA_MUX_GMI = 21,\n\tTEGRA_MUX_GMI_ALT = 22,\n\tTEGRA_MUX_HDA = 23,\n\tTEGRA_MUX_HSI = 24,\n\tTEGRA_MUX_I2C1___2 = 25,\n\tTEGRA_MUX_I2C2___2 = 26,\n\tTEGRA_MUX_I2C3___2 = 27,\n\tTEGRA_MUX_I2C4 = 28,\n\tTEGRA_MUX_I2CPWR = 29,\n\tTEGRA_MUX_I2S0 = 30,\n\tTEGRA_MUX_I2S1___2 = 31,\n\tTEGRA_MUX_I2S2___2 = 32,\n\tTEGRA_MUX_I2S3___2 = 33,\n\tTEGRA_MUX_I2S4 = 34,\n\tTEGRA_MUX_IRDA = 35,\n\tTEGRA_MUX_KBC = 36,\n\tTEGRA_MUX_OWR = 37,\n\tTEGRA_MUX_PE___2 = 38,\n\tTEGRA_MUX_PE0___2 = 39,\n\tTEGRA_MUX_PE1___2 = 40,\n\tTEGRA_MUX_PMI___2 = 41,\n\tTEGRA_MUX_PWM0___2 = 42,\n\tTEGRA_MUX_PWM1___2 = 43,\n\tTEGRA_MUX_PWM2___2 = 44,\n\tTEGRA_MUX_PWM3___2 = 45,\n\tTEGRA_MUX_PWRON = 46,\n\tTEGRA_MUX_RESET_OUT_N = 47,\n\tTEGRA_MUX_RSVD1___2 = 48,\n\tTEGRA_MUX_RSVD2___2 = 49,\n\tTEGRA_MUX_RSVD3___2 = 50,\n\tTEGRA_MUX_RSVD4 = 51,\n\tTEGRA_MUX_RTCK = 52,\n\tTEGRA_MUX_SATA___2 = 53,\n\tTEGRA_MUX_SDMMC1___2 = 54,\n\tTEGRA_MUX_SDMMC2 = 55,\n\tTEGRA_MUX_SDMMC3___2 = 56,\n\tTEGRA_MUX_SDMMC4 = 57,\n\tTEGRA_MUX_SOC___2 = 58,\n\tTEGRA_MUX_SPDIF___2 = 59,\n\tTEGRA_MUX_SPI1___2 = 60,\n\tTEGRA_MUX_SPI2___2 = 61,\n\tTEGRA_MUX_SPI3___2 = 62,\n\tTEGRA_MUX_SPI4___2 = 63,\n\tTEGRA_MUX_SPI5 = 64,\n\tTEGRA_MUX_SPI6 = 65,\n\tTEGRA_MUX_SYS___2 = 66,\n\tTEGRA_MUX_TMDS = 67,\n\tTEGRA_MUX_TRACE = 68,\n\tTEGRA_MUX_UARTA___2 = 69,\n\tTEGRA_MUX_UARTB___2 = 70,\n\tTEGRA_MUX_UARTC___2 = 71,\n\tTEGRA_MUX_UARTD___2 = 72,\n\tTEGRA_MUX_ULPI = 73,\n\tTEGRA_MUX_USB___2 = 74,\n\tTEGRA_MUX_VGP1___2 = 75,\n\tTEGRA_MUX_VGP2___2 = 76,\n\tTEGRA_MUX_VGP3___2 = 77,\n\tTEGRA_MUX_VGP4___2 = 78,\n\tTEGRA_MUX_VGP5___2 = 79,\n\tTEGRA_MUX_VGP6___2 = 80,\n\tTEGRA_MUX_VI = 81,\n\tTEGRA_MUX_VI_ALT1 = 82,\n\tTEGRA_MUX_VI_ALT3 = 83,\n\tTEGRA_MUX_VIMCLK2___2 = 84,\n\tTEGRA_MUX_VIMCLK2_ALT = 85,\n};\n\nenum tegra_mux_dt {\n\tTEGRA_MUX_RSVD0___2 = 0,\n\tTEGRA_MUX_RSVD1___3 = 1,\n\tTEGRA_MUX_RSVD2___3 = 2,\n\tTEGRA_MUX_RSVD3___3 = 3,\n\tTEGRA_MUX_TOUCH___2 = 4,\n\tTEGRA_MUX_UARTC___3 = 5,\n\tTEGRA_MUX_I2C8 = 6,\n\tTEGRA_MUX_UARTG = 7,\n\tTEGRA_MUX_SPI2___3 = 8,\n\tTEGRA_MUX_GP = 9,\n\tTEGRA_MUX_DCA = 10,\n\tTEGRA_MUX_WDT = 11,\n\tTEGRA_MUX_I2C2___3 = 12,\n\tTEGRA_MUX_CAN1 = 13,\n\tTEGRA_MUX_CAN0 = 14,\n\tTEGRA_MUX_DMIC3___2 = 15,\n\tTEGRA_MUX_DMIC5 = 16,\n\tTEGRA_MUX_GPIO = 17,\n\tTEGRA_MUX_DSPK1 = 18,\n\tTEGRA_MUX_DSPK0 = 19,\n\tTEGRA_MUX_SPDIF___3 = 20,\n\tTEGRA_MUX_AUD___2 = 21,\n\tTEGRA_MUX_I2S1___3 = 22,\n\tTEGRA_MUX_DMIC1___2 = 23,\n\tTEGRA_MUX_DMIC2___2 = 24,\n\tTEGRA_MUX_I2S3___3 = 25,\n\tTEGRA_MUX_DMIC4 = 26,\n\tTEGRA_MUX_I2S4___2 = 27,\n\tTEGRA_MUX_EXTPERIPH2___2 = 28,\n\tTEGRA_MUX_EXTPERIPH1___2 = 29,\n\tTEGRA_MUX_I2C3___3 = 30,\n\tTEGRA_MUX_VGP1___3 = 31,\n\tTEGRA_MUX_VGP2___3 = 32,\n\tTEGRA_MUX_VGP3___3 = 33,\n\tTEGRA_MUX_VGP4___3 = 34,\n\tTEGRA_MUX_VGP5___3 = 35,\n\tTEGRA_MUX_VGP6___3 = 36,\n\tTEGRA_MUX_SLVS = 37,\n\tTEGRA_MUX_EXTPERIPH3___3 = 38,\n\tTEGRA_MUX_EXTPERIPH4 = 39,\n\tTEGRA_MUX_I2S2___3 = 40,\n\tTEGRA_MUX_UARTD___3 = 41,\n\tTEGRA_MUX_I2C1___3 = 42,\n\tTEGRA_MUX_UARTA___3 = 43,\n\tTEGRA_MUX_DIRECTDC1 = 44,\n\tTEGRA_MUX_DIRECTDC = 45,\n\tTEGRA_MUX_IQC1___2 = 46,\n\tTEGRA_MUX_IQC2 = 47,\n\tTEGRA_MUX_I2S6 = 48,\n\tTEGRA_MUX_SDMMC3___3 = 49,\n\tTEGRA_MUX_SDMMC1___3 = 50,\n\tTEGRA_MUX_DP___3 = 51,\n\tTEGRA_MUX_HDMI = 52,\n\tTEGRA_MUX_PE2 = 53,\n\tTEGRA_MUX_IGPU = 54,\n\tTEGRA_MUX_SATA___3 = 55,\n\tTEGRA_MUX_PE1___3 = 56,\n\tTEGRA_MUX_PE0___3 = 57,\n\tTEGRA_MUX_PE3 = 58,\n\tTEGRA_MUX_PE4 = 59,\n\tTEGRA_MUX_PE5 = 60,\n\tTEGRA_MUX_SOC___3 = 61,\n\tTEGRA_MUX_EQOS = 62,\n\tTEGRA_MUX_QSPI___2 = 63,\n\tTEGRA_MUX_QSPI0 = 64,\n\tTEGRA_MUX_QSPI1 = 65,\n\tTEGRA_MUX_MIPI = 66,\n\tTEGRA_MUX_SCE = 67,\n\tTEGRA_MUX_I2C5 = 68,\n\tTEGRA_MUX_DISPLAYA___3 = 69,\n\tTEGRA_MUX_DISPLAYB___3 = 70,\n\tTEGRA_MUX_DCB = 71,\n\tTEGRA_MUX_SPI1___3 = 72,\n\tTEGRA_MUX_UARTB___3 = 73,\n\tTEGRA_MUX_UARTE = 74,\n\tTEGRA_MUX_SPI3___3 = 75,\n\tTEGRA_MUX_NV = 76,\n\tTEGRA_MUX_CCLA___3 = 77,\n\tTEGRA_MUX_I2S5 = 78,\n\tTEGRA_MUX_USB___3 = 79,\n\tTEGRA_MUX_UFS0 = 80,\n\tTEGRA_MUX_DGPU = 81,\n\tTEGRA_MUX_SDMMC4___2 = 82,\n};\n\nenum tegra_mux_dt___2 {\n\tTEGRA_MUX_GP___2 = 0,\n\tTEGRA_MUX_UARTC___4 = 1,\n\tTEGRA_MUX_I2C8___2 = 2,\n\tTEGRA_MUX_SPI2___4 = 3,\n\tTEGRA_MUX_I2C2___4 = 4,\n\tTEGRA_MUX_CAN1___2 = 5,\n\tTEGRA_MUX_CAN0___2 = 6,\n\tTEGRA_MUX_RSVD0___3 = 7,\n\tTEGRA_MUX_ETH0 = 8,\n\tTEGRA_MUX_ETH2 = 9,\n\tTEGRA_MUX_ETH1 = 10,\n\tTEGRA_MUX_DP___4 = 11,\n\tTEGRA_MUX_ETH3 = 12,\n\tTEGRA_MUX_I2C4___2 = 13,\n\tTEGRA_MUX_I2C7 = 14,\n\tTEGRA_MUX_I2C9 = 15,\n\tTEGRA_MUX_EQOS___2 = 16,\n\tTEGRA_MUX_PE2___2 = 17,\n\tTEGRA_MUX_PE1___4 = 18,\n\tTEGRA_MUX_PE0___4 = 19,\n\tTEGRA_MUX_PE3___2 = 20,\n\tTEGRA_MUX_PE4___2 = 21,\n\tTEGRA_MUX_PE5___2 = 22,\n\tTEGRA_MUX_PE6 = 23,\n\tTEGRA_MUX_PE10 = 24,\n\tTEGRA_MUX_PE7 = 25,\n\tTEGRA_MUX_PE8 = 26,\n\tTEGRA_MUX_PE9 = 27,\n\tTEGRA_MUX_QSPI0___2 = 28,\n\tTEGRA_MUX_QSPI1___2 = 29,\n\tTEGRA_MUX_QSPI___3 = 30,\n\tTEGRA_MUX_SDMMC1___4 = 31,\n\tTEGRA_MUX_SCE___2 = 32,\n\tTEGRA_MUX_SOC___4 = 33,\n\tTEGRA_MUX_GPIO___2 = 34,\n\tTEGRA_MUX_HDMI___2 = 35,\n\tTEGRA_MUX_UFS0___2 = 36,\n\tTEGRA_MUX_SPI3___4 = 37,\n\tTEGRA_MUX_SPI1___4 = 38,\n\tTEGRA_MUX_UARTB___4 = 39,\n\tTEGRA_MUX_UARTE___2 = 40,\n\tTEGRA_MUX_USB___4 = 41,\n\tTEGRA_MUX_EXTPERIPH2___3 = 42,\n\tTEGRA_MUX_EXTPERIPH1___3 = 43,\n\tTEGRA_MUX_I2C3___4 = 44,\n\tTEGRA_MUX_VI0 = 45,\n\tTEGRA_MUX_I2C5___2 = 46,\n\tTEGRA_MUX_UARTA___4 = 47,\n\tTEGRA_MUX_UARTD___4 = 48,\n\tTEGRA_MUX_I2C1___4 = 49,\n\tTEGRA_MUX_I2S4___3 = 50,\n\tTEGRA_MUX_I2S6___2 = 51,\n\tTEGRA_MUX_AUD___3 = 52,\n\tTEGRA_MUX_SPI5___2 = 53,\n\tTEGRA_MUX_TOUCH___3 = 54,\n\tTEGRA_MUX_UARTJ = 55,\n\tTEGRA_MUX_RSVD1___4 = 56,\n\tTEGRA_MUX_WDT___2 = 57,\n\tTEGRA_MUX_TSC = 58,\n\tTEGRA_MUX_DMIC3___3 = 59,\n\tTEGRA_MUX_LED = 60,\n\tTEGRA_MUX_VI0_ALT = 61,\n\tTEGRA_MUX_I2S5___2 = 62,\n\tTEGRA_MUX_NV___2 = 63,\n\tTEGRA_MUX_EXTPERIPH3___4 = 64,\n\tTEGRA_MUX_EXTPERIPH4___2 = 65,\n\tTEGRA_MUX_SPI4___3 = 66,\n\tTEGRA_MUX_CCLA___4 = 67,\n\tTEGRA_MUX_I2S2___4 = 68,\n\tTEGRA_MUX_I2S1___4 = 69,\n\tTEGRA_MUX_I2S8 = 70,\n\tTEGRA_MUX_I2S3___4 = 71,\n\tTEGRA_MUX_RSVD2___4 = 72,\n\tTEGRA_MUX_DMIC5___2 = 73,\n\tTEGRA_MUX_DCA___2 = 74,\n\tTEGRA_MUX_DISPLAYB___4 = 75,\n\tTEGRA_MUX_DISPLAYA___4 = 76,\n\tTEGRA_MUX_VI1 = 77,\n\tTEGRA_MUX_DCB___2 = 78,\n\tTEGRA_MUX_DMIC1___3 = 79,\n\tTEGRA_MUX_DMIC4___2 = 80,\n\tTEGRA_MUX_I2S7 = 81,\n\tTEGRA_MUX_DMIC2___3 = 82,\n\tTEGRA_MUX_DSPK0___2 = 83,\n\tTEGRA_MUX_RSVD3___4 = 84,\n\tTEGRA_MUX_TSC_ALT = 85,\n\tTEGRA_MUX_ISTCTRL = 86,\n\tTEGRA_MUX_VI1_ALT = 87,\n\tTEGRA_MUX_DSPK1___2 = 88,\n\tTEGRA_MUX_IGPU___2 = 89,\n};\n\nenum tegra_mux_dt___3 {\n\tTEGRA_MUX_RSVD0___4 = 0,\n\tTEGRA_MUX_RSVD1___5 = 1,\n\tTEGRA_MUX_RSVD2___5 = 2,\n\tTEGRA_MUX_RSVD3___5 = 3,\n\tTEGRA_MUX_TOUCH___4 = 4,\n\tTEGRA_MUX_UARTC___5 = 5,\n\tTEGRA_MUX_I2C8___3 = 6,\n\tTEGRA_MUX_UARTG___2 = 7,\n\tTEGRA_MUX_SPI2___5 = 8,\n\tTEGRA_MUX_GP___3 = 9,\n\tTEGRA_MUX_DCA___3 = 10,\n\tTEGRA_MUX_WDT___3 = 11,\n\tTEGRA_MUX_I2C2___5 = 12,\n\tTEGRA_MUX_CAN1___3 = 13,\n\tTEGRA_MUX_CAN0___3 = 14,\n\tTEGRA_MUX_DMIC3___4 = 15,\n\tTEGRA_MUX_DMIC5___3 = 16,\n\tTEGRA_MUX_GPIO___3 = 17,\n\tTEGRA_MUX_DSPK1___3 = 18,\n\tTEGRA_MUX_DSPK0___3 = 19,\n\tTEGRA_MUX_SPDIF___4 = 20,\n\tTEGRA_MUX_AUD___4 = 21,\n\tTEGRA_MUX_I2S1___5 = 22,\n\tTEGRA_MUX_DMIC1___4 = 23,\n\tTEGRA_MUX_DMIC2___4 = 24,\n\tTEGRA_MUX_I2S3___5 = 25,\n\tTEGRA_MUX_DMIC4___3 = 26,\n\tTEGRA_MUX_I2S4___4 = 27,\n\tTEGRA_MUX_EXTPERIPH2___4 = 28,\n\tTEGRA_MUX_EXTPERIPH1___4 = 29,\n\tTEGRA_MUX_I2C3___5 = 30,\n\tTEGRA_MUX_VGP1___4 = 31,\n\tTEGRA_MUX_VGP2___4 = 32,\n\tTEGRA_MUX_VGP3___4 = 33,\n\tTEGRA_MUX_VGP4___4 = 34,\n\tTEGRA_MUX_VGP5___4 = 35,\n\tTEGRA_MUX_VGP6___4 = 36,\n\tTEGRA_MUX_EXTPERIPH3___5 = 37,\n\tTEGRA_MUX_EXTPERIPH4___3 = 38,\n\tTEGRA_MUX_SPI4___4 = 39,\n\tTEGRA_MUX_I2S2___5 = 40,\n\tTEGRA_MUX_UARTD___5 = 41,\n\tTEGRA_MUX_I2C1___5 = 42,\n\tTEGRA_MUX_UARTA___5 = 43,\n\tTEGRA_MUX_DIRECTDC1___2 = 44,\n\tTEGRA_MUX_DIRECTDC___2 = 45,\n\tTEGRA_MUX_IQC0___2 = 46,\n\tTEGRA_MUX_IQC1___3 = 47,\n\tTEGRA_MUX_I2S6___3 = 48,\n\tTEGRA_MUX_DTV___3 = 49,\n\tTEGRA_MUX_UARTF = 50,\n\tTEGRA_MUX_SDMMC3___4 = 51,\n\tTEGRA_MUX_SDMMC4___3 = 52,\n\tTEGRA_MUX_SDMMC1___5 = 53,\n\tTEGRA_MUX_DP___5 = 54,\n\tTEGRA_MUX_HDMI___3 = 55,\n\tTEGRA_MUX_PE2___3 = 56,\n\tTEGRA_MUX_SATA___4 = 57,\n\tTEGRA_MUX_PE___3 = 58,\n\tTEGRA_MUX_PE1___5 = 59,\n\tTEGRA_MUX_PE0___5 = 60,\n\tTEGRA_MUX_SOC___5 = 61,\n\tTEGRA_MUX_EQOS___3 = 62,\n\tTEGRA_MUX_SDMMC2___2 = 63,\n\tTEGRA_MUX_QSPI___4 = 64,\n\tTEGRA_MUX_SCE___3 = 65,\n\tTEGRA_MUX_I2C5___3 = 66,\n\tTEGRA_MUX_DISPLAYA___5 = 67,\n\tTEGRA_MUX_DISPLAYB___5 = 68,\n\tTEGRA_MUX_DCC = 69,\n\tTEGRA_MUX_DCB___3 = 70,\n\tTEGRA_MUX_SPI1___5 = 71,\n\tTEGRA_MUX_UARTB___5 = 72,\n\tTEGRA_MUX_UARTE___3 = 73,\n\tTEGRA_MUX_SPI3___5 = 74,\n\tTEGRA_MUX_NV___3 = 75,\n\tTEGRA_MUX_CCLA___5 = 76,\n\tTEGRA_MUX_I2C7___2 = 77,\n\tTEGRA_MUX_I2C9___2 = 78,\n\tTEGRA_MUX_I2S5___3 = 79,\n\tTEGRA_MUX_USB___5 = 80,\n\tTEGRA_MUX_UFS0___3 = 81,\n};\n\nenum tegra_pinconf_param {\n\tTEGRA_PINCONF_PARAM_PULL = 0,\n\tTEGRA_PINCONF_PARAM_TRISTATE = 1,\n\tTEGRA_PINCONF_PARAM_ENABLE_INPUT = 2,\n\tTEGRA_PINCONF_PARAM_OPEN_DRAIN = 3,\n\tTEGRA_PINCONF_PARAM_LOCK = 4,\n\tTEGRA_PINCONF_PARAM_IORESET = 5,\n\tTEGRA_PINCONF_PARAM_RCV_SEL = 6,\n\tTEGRA_PINCONF_PARAM_HIGH_SPEED_MODE = 7,\n\tTEGRA_PINCONF_PARAM_SCHMITT = 8,\n\tTEGRA_PINCONF_PARAM_LOW_POWER_MODE = 9,\n\tTEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH = 10,\n\tTEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH = 11,\n\tTEGRA_PINCONF_PARAM_SLEW_RATE_FALLING = 12,\n\tTEGRA_PINCONF_PARAM_SLEW_RATE_RISING = 13,\n\tTEGRA_PINCONF_PARAM_DRIVE_TYPE = 14,\n\tTEGRA_PINCONF_PARAM_GPIO_MODE = 15,\n};\n\nenum tegra_platform {\n\tTEGRA_PLATFORM_SILICON = 0,\n\tTEGRA_PLATFORM_QT = 1,\n\tTEGRA_PLATFORM_SYSTEM_FPGA = 2,\n\tTEGRA_PLATFORM_UNIT_FPGA = 3,\n\tTEGRA_PLATFORM_ASIM_QT = 4,\n\tTEGRA_PLATFORM_ASIM_LINSIM = 5,\n\tTEGRA_PLATFORM_DSIM_ASIM_LINSIM = 6,\n\tTEGRA_PLATFORM_VERIFICATION_SIMULATION = 7,\n\tTEGRA_PLATFORM_VDK = 8,\n\tTEGRA_PLATFORM_VSP = 9,\n\tTEGRA_PLATFORM_MAX = 10,\n};\n\nenum tegra_revision {\n\tTEGRA_REVISION_UNKNOWN = 0,\n\tTEGRA_REVISION_A01 = 1,\n\tTEGRA_REVISION_A02 = 2,\n\tTEGRA_REVISION_A03 = 3,\n\tTEGRA_REVISION_A03p = 4,\n\tTEGRA_REVISION_A04 = 5,\n\tTEGRA_REVISION_MAX = 6,\n};\n\nenum tegra_super_gen {\n\tgen4 = 4,\n\tgen5 = 5,\n};\n\nenum tegra_suspend_mode {\n\tTEGRA_SUSPEND_NONE = 0,\n\tTEGRA_SUSPEND_LP2 = 1,\n\tTEGRA_SUSPEND_LP1 = 2,\n\tTEGRA_SUSPEND_LP0 = 3,\n\tTEGRA_MAX_SUSPEND_MODE = 4,\n\tTEGRA_SUSPEND_NOT_READY = 5,\n};\n\nenum tegra_xusb_mbox_cmd {\n\tMBOX_CMD_MSG_ENABLED = 1,\n\tMBOX_CMD_INC_FALC_CLOCK = 2,\n\tMBOX_CMD_DEC_FALC_CLOCK = 3,\n\tMBOX_CMD_INC_SSPI_CLOCK = 4,\n\tMBOX_CMD_DEC_SSPI_CLOCK = 5,\n\tMBOX_CMD_SET_BW = 6,\n\tMBOX_CMD_SET_SS_PWR_GATING = 7,\n\tMBOX_CMD_SET_SS_PWR_UNGATING = 8,\n\tMBOX_CMD_SAVE_DFE_CTLE_CTX = 9,\n\tMBOX_CMD_AIRPLANE_MODE_ENABLED = 10,\n\tMBOX_CMD_AIRPLANE_MODE_DISABLED = 11,\n\tMBOX_CMD_START_HSIC_IDLE = 12,\n\tMBOX_CMD_STOP_HSIC_IDLE = 13,\n\tMBOX_CMD_DBC_WAKE_STACK = 14,\n\tMBOX_CMD_HSIC_PRETEND_CONNECT = 15,\n\tMBOX_CMD_RESET_SSPI = 16,\n\tMBOX_CMD_DISABLE_SS_LFPS_DETECTION = 17,\n\tMBOX_CMD_ENABLE_SS_LFPS_DETECTION = 18,\n\tMBOX_CMD_MAX = 19,\n\tMBOX_CMD_ACK = 128,\n\tMBOX_CMD_NAK = 129,\n};\n\nenum tegra_xusb_padctl_param {\n\tTEGRA_XUSB_PADCTL_IDDQ = 0,\n};\n\nenum thermal_device_mode {\n\tTHERMAL_DEVICE_DISABLED = 0,\n\tTHERMAL_DEVICE_ENABLED = 1,\n};\n\nenum thermal_notify_event {\n\tTHERMAL_EVENT_UNSPECIFIED = 0,\n\tTHERMAL_EVENT_TEMP_SAMPLE = 1,\n\tTHERMAL_TRIP_VIOLATED = 2,\n\tTHERMAL_TRIP_CHANGED = 3,\n\tTHERMAL_DEVICE_DOWN = 4,\n\tTHERMAL_DEVICE_UP = 5,\n\tTHERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6,\n\tTHERMAL_TABLE_CHANGED = 7,\n\tTHERMAL_EVENT_KEEP_ALIVE = 8,\n\tTHERMAL_TZ_BIND_CDEV = 9,\n\tTHERMAL_TZ_UNBIND_CDEV = 10,\n\tTHERMAL_INSTANCE_WEIGHT_CHANGED = 11,\n\tTHERMAL_TZ_RESUME = 12,\n\tTHERMAL_TZ_ADD_THRESHOLD = 13,\n\tTHERMAL_TZ_DEL_THRESHOLD = 14,\n\tTHERMAL_TZ_FLUSH_THRESHOLDS = 15,\n};\n\nenum thermal_trend {\n\tTHERMAL_TREND_STABLE = 0,\n\tTHERMAL_TREND_RAISING = 1,\n\tTHERMAL_TREND_DROPPING = 2,\n};\n\nenum thermal_trip_type {\n\tTHERMAL_TRIP_ACTIVE = 0,\n\tTHERMAL_TRIP_PASSIVE = 1,\n\tTHERMAL_TRIP_HOT = 2,\n\tTHERMAL_TRIP_CRITICAL = 3,\n};\n\nenum ti_sysc_module_type {\n\tTI_SYSC_OMAP2 = 0,\n\tTI_SYSC_OMAP2_TIMER = 1,\n\tTI_SYSC_OMAP3_SHAM = 2,\n\tTI_SYSC_OMAP3_AES = 3,\n\tTI_SYSC_OMAP4 = 4,\n\tTI_SYSC_OMAP4_TIMER = 5,\n\tTI_SYSC_OMAP4_SIMPLE = 6,\n\tTI_SYSC_OMAP34XX_SR = 7,\n\tTI_SYSC_OMAP36XX_SR = 8,\n\tTI_SYSC_OMAP4_SR = 9,\n\tTI_SYSC_OMAP4_MCASP = 10,\n\tTI_SYSC_OMAP4_USB_HOST_FS = 11,\n\tTI_SYSC_DRA7_MCAN = 12,\n\tTI_SYSC_PRUSS = 13,\n};\n\nenum tick_broadcast_mode {\n\tTICK_BROADCAST_OFF = 0,\n\tTICK_BROADCAST_ON = 1,\n\tTICK_BROADCAST_FORCE = 2,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPERS_MAX = 1,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tis_access {\n\tTPM_ACCESS_VALID = 128,\n\tTPM_ACCESS_ACTIVE_LOCALITY = 32,\n\tTPM_ACCESS_REQUEST_PENDING = 4,\n\tTPM_ACCESS_REQUEST_USE = 2,\n};\n\nenum tis_defaults {\n\tTIS_SHORT_TIMEOUT = 750,\n\tTIS_LONG_TIMEOUT = 2000,\n};\n\nenum tis_status {\n\tTPM_STS_VALID = 128,\n\tTPM_STS_COMMAND_READY = 64,\n\tTPM_STS_GO = 32,\n\tTPM_STS_DATA_AVAIL = 16,\n\tTPM_STS_DATA_EXPECT = 8,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum topology_type {\n\tTYPE_INVALID = 0,\n\tTYPE_MUX = 1,\n\tTYPE_PLL = 2,\n\tTYPE_FIXEDFACTOR = 3,\n\tTYPE_DIV1 = 4,\n\tTYPE_DIV2 = 5,\n\tTYPE_GATE = 6,\n};\n\nenum tp_func_state {\n\tTP_FUNC_0 = 0,\n\tTP_FUNC_1 = 1,\n\tTP_FUNC_2 = 2,\n\tTP_FUNC_N = 3,\n};\n\nenum tp_transition_sync {\n\tTP_TRANSITION_SYNC_1_0_1 = 0,\n\tTP_TRANSITION_SYNC_N_2_1 = 1,\n\t_NR_TP_TRANSITION_SYNC = 2,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tph_mem_type {\n\tTPH_MEM_TYPE_VM = 0,\n\tTPH_MEM_TYPE_PM = 1,\n};\n\nenum tpm2_capabilities {\n\tTPM2_CAP_HANDLES = 1,\n\tTPM2_CAP_COMMANDS = 2,\n\tTPM2_CAP_PCRS = 5,\n\tTPM2_CAP_TPM_PROPERTIES = 6,\n};\n\nenum tpm2_cc_attrs {\n\tTPM2_CC_ATTR_CHANDLES = 25,\n\tTPM2_CC_ATTR_RHANDLE = 28,\n\tTPM2_CC_ATTR_VENDOR = 29,\n};\n\nenum tpm2_command_codes {\n\tTPM2_CC_FIRST = 287,\n\tTPM2_CC_HIERARCHY_CONTROL = 289,\n\tTPM2_CC_HIERARCHY_CHANGE_AUTH = 297,\n\tTPM2_CC_CREATE_PRIMARY = 305,\n\tTPM2_CC_SEQUENCE_COMPLETE = 318,\n\tTPM2_CC_SELF_TEST = 323,\n\tTPM2_CC_STARTUP = 324,\n\tTPM2_CC_SHUTDOWN = 325,\n\tTPM2_CC_NV_READ = 334,\n\tTPM2_CC_CREATE = 339,\n\tTPM2_CC_LOAD = 343,\n\tTPM2_CC_SEQUENCE_UPDATE = 348,\n\tTPM2_CC_UNSEAL = 350,\n\tTPM2_CC_CONTEXT_LOAD = 353,\n\tTPM2_CC_CONTEXT_SAVE = 354,\n\tTPM2_CC_FLUSH_CONTEXT = 357,\n\tTPM2_CC_READ_PUBLIC = 371,\n\tTPM2_CC_START_AUTH_SESS = 374,\n\tTPM2_CC_VERIFY_SIGNATURE = 375,\n\tTPM2_CC_GET_CAPABILITY = 378,\n\tTPM2_CC_GET_RANDOM = 379,\n\tTPM2_CC_PCR_READ = 382,\n\tTPM2_CC_PCR_EXTEND = 386,\n\tTPM2_CC_EVENT_SEQUENCE_COMPLETE = 389,\n\tTPM2_CC_HASH_SEQUENCE_START = 390,\n\tTPM2_CC_CREATE_LOADED = 401,\n\tTPM2_CC_LAST = 403,\n};\n\nenum tpm2_const {\n\tTPM2_PLATFORM_PCR = 24,\n\tTPM2_PCR_SELECT_MIN = 3,\n};\n\nenum tpm2_durations {\n\tTPM2_DURATION_SHORT = 20,\n\tTPM2_DURATION_LONG = 2000,\n\tTPM2_DURATION_DEFAULT = 120000,\n};\n\nenum tpm2_handle_types {\n\tTPM2_HT_HMAC_SESSION = 33554432,\n\tTPM2_HT_POLICY_SESSION = 50331648,\n\tTPM2_HT_TRANSIENT = 2147483648,\n};\n\nenum tpm2_permanent_handles {\n\tTPM2_RH_NULL = 1073741831,\n\tTPM2_RS_PW = 1073741833,\n};\n\nenum tpm2_properties {\n\tTPM_PT_TOTAL_COMMANDS = 297,\n};\n\nenum tpm2_return_codes {\n\tTPM2_RC_SUCCESS = 0,\n\tTPM2_RC_HASH = 131,\n\tTPM2_RC_HANDLE = 139,\n\tTPM2_RC_INTEGRITY = 159,\n\tTPM2_RC_INITIALIZE = 256,\n\tTPM2_RC_FAILURE = 257,\n\tTPM2_RC_DISABLED = 288,\n\tTPM2_RC_UPGRADE = 301,\n\tTPM2_RC_COMMAND_CODE = 323,\n\tTPM2_RC_TESTING = 2314,\n\tTPM2_RC_REFERENCE_H0 = 2320,\n\tTPM2_RC_RETRY = 2338,\n\tTPM2_RC_SESSION_MEMORY = 2307,\n};\n\nenum tpm2_session_attributes {\n\tTPM2_SA_CONTINUE_SESSION = 1,\n\tTPM2_SA_AUDIT_EXCLUSIVE = 2,\n\tTPM2_SA_AUDIT_RESET = 8,\n\tTPM2_SA_DECRYPT = 32,\n\tTPM2_SA_ENCRYPT = 64,\n\tTPM2_SA_AUDIT = 128,\n};\n\nenum tpm2_startup_types {\n\tTPM2_SU_CLEAR = 0,\n\tTPM2_SU_STATE = 1,\n};\n\nenum tpm2_structures {\n\tTPM2_ST_NO_SESSIONS = 32769,\n\tTPM2_ST_SESSIONS = 32770,\n\tTPM2_ST_CREATION = 32801,\n};\n\nenum tpm2_timeouts {\n\tTPM2_TIMEOUT_A = 750,\n\tTPM2_TIMEOUT_B = 4000,\n\tTPM2_TIMEOUT_C = 200,\n\tTPM2_TIMEOUT_D = 30,\n};\n\nenum tpm_algorithms {\n\tTPM_ALG_ERROR = 0,\n\tTPM_ALG_SHA1 = 4,\n\tTPM_ALG_AES = 6,\n\tTPM_ALG_KEYEDHASH = 8,\n\tTPM_ALG_SHA256 = 11,\n\tTPM_ALG_SHA384 = 12,\n\tTPM_ALG_SHA512 = 13,\n\tTPM_ALG_NULL = 16,\n\tTPM_ALG_SM3_256 = 18,\n\tTPM_ALG_ECC = 35,\n\tTPM_ALG_CFB = 67,\n};\n\nenum tpm_buf_flags {\n\tTPM_BUF_OVERFLOW = 1,\n\tTPM_BUF_TPM2B = 2,\n\tTPM_BUF_BOUNDARY_ERROR = 4,\n};\n\nenum tpm_capabilities {\n\tTPM_CAP_FLAG = 4,\n\tTPM_CAP_PROP = 5,\n\tTPM_CAP_VERSION_1_1 = 6,\n\tTPM_CAP_VERSION_1_2 = 26,\n};\n\nenum tpm_chip_flags {\n\tTPM_CHIP_FLAG_BOOTSTRAPPED = 1,\n\tTPM_CHIP_FLAG_TPM2 = 2,\n\tTPM_CHIP_FLAG_IRQ = 4,\n\tTPM_CHIP_FLAG_VIRTUAL = 8,\n\tTPM_CHIP_FLAG_HAVE_TIMEOUTS = 16,\n\tTPM_CHIP_FLAG_ALWAYS_POWERED = 32,\n\tTPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED = 64,\n\tTPM_CHIP_FLAG_FIRMWARE_UPGRADE = 128,\n\tTPM_CHIP_FLAG_SUSPENDED = 256,\n\tTPM_CHIP_FLAG_HWRNG_DISABLED = 512,\n\tTPM_CHIP_FLAG_DISABLE = 1024,\n\tTPM_CHIP_FLAG_SYNC = 2048,\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum tpm_sub_capabilities {\n\tTPM_CAP_PROP_PCR = 257,\n\tTPM_CAP_PROP_MANUFACTURER = 259,\n\tTPM_CAP_FLAG_PERM = 264,\n\tTPM_CAP_FLAG_VOL = 265,\n\tTPM_CAP_PROP_OWNER = 273,\n\tTPM_CAP_PROP_TIS_TIMEOUT = 277,\n\tTPM_CAP_PROP_TIS_DURATION = 288,\n};\n\nenum tpm_timeout {\n\tTPM_TIMEOUT = 5,\n\tTPM_TIMEOUT_RETRY = 100,\n\tTPM_TIMEOUT_RANGE_US = 300,\n\tTPM_TIMEOUT_POLL = 1,\n\tTPM_TIMEOUT_USECS_MIN = 100,\n\tTPM_TIMEOUT_USECS_MAX = 500,\n};\n\nenum tps65214_regulator_id {\n\tTPS65214_LDO_1 = 3,\n\tTPS65214_LDO_2 = 4,\n};\n\nenum tps65215_regulator_id {\n\tTPS65215_LDO_2 = 4,\n};\n\nenum tps65219_regulator_id {\n\tTPS65219_BUCK_1 = 0,\n\tTPS65219_BUCK_2 = 1,\n\tTPS65219_BUCK_3 = 2,\n\tTPS65219_LDO_1 = 3,\n\tTPS65219_LDO_2 = 4,\n\tTPS65219_LDO_3 = 5,\n\tTPS65219_LDO_4 = 6,\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_NEED_RESCHED_LAZY = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n\tTRACE_FLAG_BH_OFF = 128,\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n\tTRACE_FILE_PAUSE = 8,\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_FIELDS_BIT = 8,\n\tTRACE_ITER_PRINTK_BIT = 9,\n\tTRACE_ITER_ANNOTATE_BIT = 10,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 11,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 12,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 13,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 14,\n\tTRACE_ITER_LATENCY_FMT_BIT = 15,\n\tTRACE_ITER_RECORD_CMD_BIT = 16,\n\tTRACE_ITER_RECORD_TGID_BIT = 17,\n\tTRACE_ITER_OVERWRITE_BIT = 18,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 19,\n\tTRACE_ITER_IRQ_INFO_BIT = 20,\n\tTRACE_ITER_MARKERS_BIT = 21,\n\tTRACE_ITER_EVENT_FORK_BIT = 22,\n\tTRACE_ITER_TRACE_PRINTK_BIT = 23,\n\tTRACE_ITER_COPY_MARKER_BIT = 24,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 25,\n\tTRACE_ITER_HASH_PTR_BIT = 26,\n\tTRACE_ITER_BITMASK_LIST_BIT = 27,\n\tTRACE_ITER_STACKTRACE_BIT = 28,\n\tTRACE_ITER_LAST_BIT = 29,\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_GRAPH_RETADDR_ENT = 12,\n\tTRACE_USER_STACK = 13,\n\tTRACE_BLK = 14,\n\tTRACE_BPUTS = 15,\n\tTRACE_HWLAT = 16,\n\tTRACE_OSNOISE = 17,\n\tTRACE_TIMERLAT = 18,\n\tTRACE_RAW_DATA = 19,\n\tTRACE_FUNC_REPEATS = 20,\n\t__TRACE_LAST_TYPE = 21,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum trans_regime {\n\tTR_EL10 = 0,\n\tTR_EL20 = 1,\n\tTR_EL2 = 2,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum transparent_hugepage_flag {\n\tTRANSPARENT_HUGEPAGE_UNSUPPORTED = 0,\n\tTRANSPARENT_HUGEPAGE_FLAG = 1,\n\tTRANSPARENT_HUGEPAGE_REQ_MADV_FLAG = 2,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_DIRECT_FLAG = 3,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_FLAG = 4,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_OR_MADV_FLAG = 5,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_REQ_MADV_FLAG = 6,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KHUGEPAGED_FLAG = 7,\n\tTRANSPARENT_HUGEPAGE_USE_ZERO_PAGE_FLAG = 8,\n};\n\nenum trap_behaviour {\n\tBEHAVE_HANDLE_LOCALLY = 0,\n\tBEHAVE_FORWARD_READ = 1,\n\tBEHAVE_FORWARD_WRITE = 2,\n\tBEHAVE_FORWARD_RW = 3,\n\tBEHAVE_FORWARD_IN_HOST_EL0 = 4,\n};\n\nenum tre_type {\n\tHIDMA_TRE_MEMCPY = 3,\n\tHIDMA_TRE_MEMSET = 4,\n};\n\nenum tsens_irq_type {\n\tLOWER = 0,\n\tUPPER = 1,\n\tCRITICAL = 2,\n};\n\nenum tsens_ver {\n\tVER_0 = 0,\n\tVER_0_1 = 1,\n\tVER_1_X = 2,\n\tVER_1_X_NO_RPM = 3,\n\tVER_2_X = 4,\n\tVER_2_X_NO_RPM = 5,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum tx_queue_prio {\n\tTX_QUEUE_PRIO_HIGH = 0,\n\tTX_QUEUE_PRIO_LOW = 1,\n};\n\nenum tx_stats_reg_offset {\n\tTX_OCTS = 0,\n\tTX_UCAST = 1,\n\tTX_BCAST = 2,\n\tTX_MCAST = 3,\n\tTX_DROP = 4,\n\tTX_STATS_ENUM_LAST = 5,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum u2_phy_params {\n\tU2P_EYE_VRT = 0,\n\tU2P_EYE_TERM = 1,\n\tU2P_EFUSE_EN = 2,\n\tU2P_EFUSE_INTR = 3,\n\tU2P_DISCTH = 4,\n\tU2P_PRE_EMPHASIS = 5,\n};\n\nenum u3_phy_params {\n\tU3P_EFUSE_EN = 0,\n\tU3P_EFUSE_INTR = 1,\n\tU3P_EFUSE_TX_IMP = 2,\n\tU3P_EFUSE_RX_IMP = 3,\n};\n\nenum uart_iotype {\n\tUPIO_UNKNOWN = -1,\n\tUPIO_PORT = 0,\n\tUPIO_HUB6 = 1,\n\tUPIO_MEM = 2,\n\tUPIO_MEM32 = 3,\n\tUPIO_AU = 4,\n\tUPIO_TSI = 5,\n\tUPIO_MEM32BE = 6,\n\tUPIO_MEM16 = 7,\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_FANOTIFY_GROUPS = 10,\n\tUCOUNT_FANOTIFY_MARKS = 11,\n\tUCOUNT_COUNTS = 12,\n};\n\nenum udma_chan_state {\n\tUDMA_CHAN_IS_IDLE = 0,\n\tUDMA_CHAN_IS_ACTIVE = 1,\n\tUDMA_CHAN_IS_TERMINATING = 2,\n};\n\nenum udma_mmr {\n\tMMR_GCFG = 0,\n\tMMR_BCHANRT = 1,\n\tMMR_RCHANRT = 2,\n\tMMR_TCHANRT = 3,\n\tMMR_LAST = 4,\n};\n\nenum udma_rm_range {\n\tRM_RANGE_BCHAN = 0,\n\tRM_RANGE_TCHAN = 1,\n\tRM_RANGE_RCHAN = 2,\n\tRM_RANGE_RFLOW = 3,\n\tRM_RANGE_TFLOW = 4,\n\tRM_RANGE_LAST = 5,\n};\n\nenum udma_tp_level {\n\tUDMA_TP_NORMAL = 0,\n\tUDMA_TP_HIGH = 1,\n\tUDMA_TP_ULTRAHIGH = 2,\n\tUDMA_TP_LAST = 3,\n};\n\nenum udp_conntrack {\n\tUDP_CT_UNREPLIED = 0,\n\tUDP_CT_REPLIED = 1,\n\tUDP_CT_MAX = 2,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum ufs_bsg_msg_code {\n\tUPIU_TRANSACTION_UIC_CMD = 31,\n\tUPIU_TRANSACTION_ARPMB_CMD = 32,\n};\n\nenum ufs_crypto_alg {\n\tUFS_CRYPTO_ALG_AES_XTS = 0,\n\tUFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 1,\n\tUFS_CRYPTO_ALG_AES_ECB = 2,\n\tUFS_CRYPTO_ALG_ESSIV_AES_CBC = 3,\n};\n\nenum ufs_crypto_key_size {\n\tUFS_CRYPTO_KEY_SIZE_INVALID = 0,\n\tUFS_CRYPTO_KEY_SIZE_128 = 1,\n\tUFS_CRYPTO_KEY_SIZE_192 = 2,\n\tUFS_CRYPTO_KEY_SIZE_256 = 3,\n\tUFS_CRYPTO_KEY_SIZE_512 = 4,\n};\n\nenum ufs_descr_fmt {\n\tSD_RAW = 0,\n\tSD_ASCII_STD = 1,\n};\n\nenum ufs_dev_pwr_mode {\n\tUFS_ACTIVE_PWR_MODE = 1,\n\tUFS_SLEEP_PWR_MODE = 2,\n\tUFS_POWERDOWN_PWR_MODE = 3,\n\tUFS_DEEPSLEEP_PWR_MODE = 4,\n};\n\nenum ufs_event_type {\n\tUFS_EVT_PA_ERR = 0,\n\tUFS_EVT_DL_ERR = 1,\n\tUFS_EVT_NL_ERR = 2,\n\tUFS_EVT_TL_ERR = 3,\n\tUFS_EVT_DME_ERR = 4,\n\tUFS_EVT_AUTO_HIBERN8_ERR = 5,\n\tUFS_EVT_FATAL_ERR = 6,\n\tUFS_EVT_LINK_STARTUP_FAIL = 7,\n\tUFS_EVT_RESUME_ERR = 8,\n\tUFS_EVT_SUSPEND_ERR = 9,\n\tUFS_EVT_WL_SUSP_ERR = 10,\n\tUFS_EVT_WL_RES_ERR = 11,\n\tUFS_EVT_DEV_RESET = 12,\n\tUFS_EVT_HOST_RESET = 13,\n\tUFS_EVT_ABORT = 14,\n\tUFS_EVT_CNT = 15,\n};\n\nenum ufs_hid_defrag_operation {\n\tHID_ANALYSIS_AND_DEFRAG_DISABLE = 0,\n\tHID_ANALYSIS_ENABLE = 1,\n\tHID_ANALYSIS_AND_DEFRAG_ENABLE = 2,\n};\n\nenum ufs_hid_state {\n\tHID_IDLE = 0,\n\tANALYSIS_IN_PROGRESS = 1,\n\tDEFRAG_REQUIRED = 2,\n\tDEFRAG_IN_PROGRESS = 3,\n\tDEFRAG_COMPLETED = 4,\n\tDEFRAG_NOT_REQUIRED = 5,\n\tNUM_UFS_HID_STATES = 6,\n};\n\nenum ufs_hs_gear_rate {\n\tPA_HS_MODE_A = 1,\n\tPA_HS_MODE_B = 2,\n};\n\nenum ufs_hs_gear_tag {\n\tUFS_HS_DONT_CHANGE = 0,\n\tUFS_HS_G1 = 1,\n\tUFS_HS_G2 = 2,\n\tUFS_HS_G3 = 3,\n\tUFS_HS_G4 = 4,\n\tUFS_HS_G5 = 5,\n};\n\nenum ufs_lanes {\n\tUFS_LANE_DONT_CHANGE = 0,\n\tUFS_LANE_1 = 1,\n\tUFS_LANE_2 = 2,\n};\n\nenum ufs_lu_wp_type {\n\tUFS_LU_NO_WP = 0,\n\tUFS_LU_POWER_ON_WP = 1,\n\tUFS_LU_PERM_WP = 2,\n};\n\nenum ufs_mtk_host_caps {\n\tUFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1,\n\tUFS_MTK_CAP_VA09_PWR_CTRL = 2,\n\tUFS_MTK_CAP_DISABLE_AH8 = 4,\n\tUFS_MTK_CAP_BROKEN_VCC = 8,\n\tUFS_MTK_CAP_ALLOW_VCCQX_LPM = 32,\n\tUFS_MTK_CAP_PMC_VIA_FASTAUTO = 64,\n\tUFS_MTK_CAP_TX_SKEW_FIX = 128,\n\tUFS_MTK_CAP_DISABLE_MCQ = 256,\n\tUFS_MTK_CAP_RTFF_MTCMOS = 512,\n\tUFS_MTK_CAP_MCQ_BROKEN_RTC = 1024,\n};\n\nenum ufs_mtk_mphy_op {\n\tUFS_MPHY_BACKUP = 0,\n\tUFS_MPHY_RESTORE = 1,\n};\n\nenum ufs_mtk_vcc_num {\n\tUFS_VCC_NONE = 0,\n\tUFS_VCC_1 = 1,\n\tUFS_VCC_2 = 2,\n\tUFS_VCC_MAX = 3,\n};\n\nenum ufs_notify_change_status {\n\tPRE_CHANGE = 0,\n\tPOST_CHANGE = 1,\n};\n\nenum ufs_pa_pwr_mode {\n\tFAST_MODE = 1,\n\tSLOW_MODE = 2,\n\tFASTAUTO_MODE = 4,\n\tSLOWAUTO_MODE = 5,\n\tUNCHANGED = 7,\n};\n\nenum ufs_pm_level {\n\tUFS_PM_LVL_0 = 0,\n\tUFS_PM_LVL_1 = 1,\n\tUFS_PM_LVL_2 = 2,\n\tUFS_PM_LVL_3 = 3,\n\tUFS_PM_LVL_4 = 4,\n\tUFS_PM_LVL_5 = 5,\n\tUFS_PM_LVL_6 = 6,\n\tUFS_PM_LVL_MAX = 7,\n};\n\nenum ufs_pm_op {\n\tUFS_RUNTIME_PM = 0,\n\tUFS_SYSTEM_PM = 1,\n\tUFS_SHUTDOWN_PM = 2,\n};\n\nenum ufs_pwm_gear_tag {\n\tUFS_PWM_DONT_CHANGE = 0,\n\tUFS_PWM_G1 = 1,\n\tUFS_PWM_G2 = 2,\n\tUFS_PWM_G3 = 3,\n\tUFS_PWM_G4 = 4,\n\tUFS_PWM_G5 = 5,\n\tUFS_PWM_G6 = 6,\n\tUFS_PWM_G7 = 7,\n};\n\nenum ufs_ref_clk_freq {\n\tREF_CLK_FREQ_19_2_MHZ = 0,\n\tREF_CLK_FREQ_26_MHZ = 1,\n\tREF_CLK_FREQ_38_4_MHZ = 2,\n\tREF_CLK_FREQ_52_MHZ = 3,\n\tREF_CLK_FREQ_INVAL = -1,\n};\n\nenum ufs_rpmb_op_type {\n\tUFS_RPMB_WRITE_KEY = 1,\n\tUFS_RPMB_READ_CNT = 2,\n\tUFS_RPMB_WRITE = 3,\n\tUFS_RPMB_READ = 4,\n\tUFS_RPMB_READ_RESP = 5,\n\tUFS_RPMB_SEC_CONF_WRITE = 6,\n\tUFS_RPMB_SEC_CONF_READ = 7,\n\tUFS_RPMB_PURGE_ENABLE = 8,\n\tUFS_RPMB_PURGE_STATUS_READ = 9,\n};\n\nenum ufs_rtc_time {\n\tUFS_RTC_RELATIVE = 0,\n\tUFS_RTC_ABSOLUTE = 1,\n};\n\nenum ufs_trace_str_t {\n\tUFS_CMD_SEND = 0,\n\tUFS_CMD_COMP = 1,\n\tUFS_QUERY_SEND = 2,\n\tUFS_QUERY_COMP = 3,\n\tUFS_QUERY_ERR = 4,\n\tUFS_TM_SEND = 5,\n\tUFS_TM_COMP = 6,\n\tUFS_TM_ERR = 7,\n};\n\nenum ufs_trace_tsf_t {\n\tUFS_TSF_CDB = 0,\n\tUFS_TSF_OSF = 1,\n\tUFS_TSF_TM_INPUT = 2,\n\tUFS_TSF_TM_OUTPUT = 3,\n};\n\nenum ufs_unipro_ver {\n\tUFS_UNIPRO_VER_RESERVED = 0,\n\tUFS_UNIPRO_VER_1_40 = 1,\n\tUFS_UNIPRO_VER_1_41 = 2,\n\tUFS_UNIPRO_VER_1_6 = 3,\n\tUFS_UNIPRO_VER_1_61 = 4,\n\tUFS_UNIPRO_VER_1_8 = 5,\n\tUFS_UNIPRO_VER_MAX = 6,\n\tUFS_UNIPRO_VER_MASK = 15,\n};\n\nenum ufshcd_caps {\n\tUFSHCD_CAP_CLK_GATING = 1,\n\tUFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 2,\n\tUFSHCD_CAP_CLK_SCALING = 4,\n\tUFSHCD_CAP_AUTO_BKOPS_SUSPEND = 8,\n\tUFSHCD_CAP_INTR_AGGR = 16,\n\tUFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 32,\n\tUFSHCD_CAP_RPM_AUTOSUSPEND = 64,\n\tUFSHCD_CAP_WB_EN = 128,\n\tUFSHCD_CAP_CRYPTO = 256,\n\tUFSHCD_CAP_AGGR_POWER_COLLAPSE = 512,\n\tUFSHCD_CAP_DEEPSLEEP = 1024,\n\tUFSHCD_CAP_TEMP_NOTIF = 2048,\n\tUFSHCD_CAP_WB_WITH_CLK_SCALING = 4096,\n};\n\nenum ufshcd_mcq_opr {\n\tOPR_SQD = 0,\n\tOPR_SQIS = 1,\n\tOPR_CQD = 2,\n\tOPR_CQIS = 3,\n\tOPR_MAX = 4,\n};\n\nenum ufshcd_quirks {\n\tUFSHCD_QUIRK_BROKEN_INTR_AGGR = 1,\n\tUFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 2,\n\tUFSHCD_QUIRK_BROKEN_LCC = 4,\n\tUFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 8,\n\tUFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 16,\n\tUFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 32,\n\tUFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 64,\n\tUFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 128,\n\tUFSHCI_QUIRK_BROKEN_HCE = 256,\n\tUFSHCD_QUIRK_PRDT_BYTE_GRAN = 512,\n\tUFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1024,\n\tUFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 2048,\n\tUFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 4096,\n\tUFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 8192,\n\tUFSHCD_QUIRK_BROKEN_UIC_CMD = 32768,\n\tUFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 65536,\n\tUFSHCD_QUIRK_HIBERN_FASTAUTO = 262144,\n\tUFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 524288,\n\tUFSHCD_QUIRK_MCQ_BROKEN_INTR = 1048576,\n\tUFSHCD_QUIRK_MCQ_BROKEN_RTC = 2097152,\n\tUFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 4194304,\n\tUFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 8388608,\n\tUFSHCD_QUIRK_KEYS_IN_PRDT = 16777216,\n\tUFSHCD_QUIRK_BROKEN_LSDBS_CAP = 33554432,\n\tUFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE = 67108864,\n};\n\nenum ufshcd_state {\n\tUFSHCD_STATE_RESET = 0,\n\tUFSHCD_STATE_OPERATIONAL = 1,\n\tUFSHCD_STATE_EH_SCHEDULED_NON_FATAL = 2,\n\tUFSHCD_STATE_EH_SCHEDULED_FATAL = 3,\n\tUFSHCD_STATE_ERROR = 4,\n};\n\nenum uic_cmd_dme {\n\tUIC_CMD_DME_GET = 1,\n\tUIC_CMD_DME_SET = 2,\n\tUIC_CMD_DME_PEER_GET = 3,\n\tUIC_CMD_DME_PEER_SET = 4,\n\tUIC_CMD_DME_POWERON = 16,\n\tUIC_CMD_DME_POWEROFF = 17,\n\tUIC_CMD_DME_ENABLE = 18,\n\tUIC_CMD_DME_RESET = 20,\n\tUIC_CMD_DME_END_PT_RST = 21,\n\tUIC_CMD_DME_LINK_STARTUP = 22,\n\tUIC_CMD_DME_HIBER_ENTER = 23,\n\tUIC_CMD_DME_HIBER_EXIT = 24,\n\tUIC_CMD_DME_TEST_MODE = 26,\n};\n\nenum uic_link_state {\n\tUIC_LINK_OFF_STATE = 0,\n\tUIC_LINK_ACTIVE_STATE = 1,\n\tUIC_LINK_HIBERN8_STATE = 2,\n\tUIC_LINK_BROKEN_STATE = 3,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum uniphier_clk_type {\n\tUNIPHIER_CLK_TYPE_CPUGEAR = 0,\n\tUNIPHIER_CLK_TYPE_FIXED_FACTOR = 1,\n\tUNIPHIER_CLK_TYPE_FIXED_RATE = 2,\n\tUNIPHIER_CLK_TYPE_GATE = 3,\n\tUNIPHIER_CLK_TYPE_MUX = 4,\n};\n\nenum uniphier_pin_drv_type {\n\tUNIPHIER_PIN_DRV_1BIT = 0,\n\tUNIPHIER_PIN_DRV_2BIT = 1,\n\tUNIPHIER_PIN_DRV_3BIT = 2,\n\tUNIPHIER_PIN_DRV_FIXED4 = 3,\n\tUNIPHIER_PIN_DRV_FIXED5 = 4,\n\tUNIPHIER_PIN_DRV_FIXED8 = 5,\n\tUNIPHIER_PIN_DRV_NONE = 6,\n};\n\nenum uniphier_pin_pull_dir {\n\tUNIPHIER_PIN_PULL_UP = 0,\n\tUNIPHIER_PIN_PULL_DOWN = 1,\n\tUNIPHIER_PIN_PULL_UP_FIXED = 2,\n\tUNIPHIER_PIN_PULL_DOWN_FIXED = 3,\n\tUNIPHIER_PIN_PULL_NONE = 4,\n};\n\nenum unit_desc_param {\n\tUNIT_DESC_PARAM_LEN = 0,\n\tUNIT_DESC_PARAM_TYPE = 1,\n\tUNIT_DESC_PARAM_UNIT_INDEX = 2,\n\tUNIT_DESC_PARAM_LU_ENABLE = 3,\n\tUNIT_DESC_PARAM_BOOT_LUN_ID = 4,\n\tUNIT_DESC_PARAM_LU_WR_PROTECT = 5,\n\tUNIT_DESC_PARAM_LU_Q_DEPTH = 6,\n\tUNIT_DESC_PARAM_PSA_SENSITIVE = 7,\n\tUNIT_DESC_PARAM_MEM_TYPE = 8,\n\tUNIT_DESC_PARAM_DATA_RELIABILITY = 9,\n\tUNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 10,\n\tUNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 11,\n\tUNIT_DESC_PARAM_ERASE_BLK_SIZE = 19,\n\tUNIT_DESC_PARAM_PROVISIONING_TYPE = 23,\n\tUNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 24,\n\tUNIT_DESC_PARAM_CTX_CAPABILITIES = 32,\n\tUNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 34,\n\tUNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 35,\n\tUNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 37,\n\tUNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 39,\n\tUNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 41,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum upiu_request_transaction {\n\tUPIU_TRANSACTION_NOP_OUT = 0,\n\tUPIU_TRANSACTION_COMMAND = 1,\n\tUPIU_TRANSACTION_DATA_OUT = 2,\n\tUPIU_TRANSACTION_TASK_REQ = 4,\n\tUPIU_TRANSACTION_QUERY_REQ = 22,\n};\n\nenum upiu_response_transaction {\n\tUPIU_TRANSACTION_NOP_IN = 32,\n\tUPIU_TRANSACTION_RESPONSE = 33,\n\tUPIU_TRANSACTION_DATA_IN = 34,\n\tUPIU_TRANSACTION_TASK_RSP = 36,\n\tUPIU_TRANSACTION_READY_XFER = 49,\n\tUPIU_TRANSACTION_QUERY_RSP = 54,\n\tUPIU_TRANSACTION_REJECT_UPIU = 63,\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nenum usb3503_mode {\n\tUSB3503_MODE_UNKNOWN = 0,\n\tUSB3503_MODE_HUB = 1,\n\tUSB3503_MODE_STANDBY = 2,\n\tUSB3503_MODE_BYPASS = 3,\n};\n\nenum usb3_link_state {\n\tUSB3_LPM_U0 = 0,\n\tUSB3_LPM_U1 = 1,\n\tUSB3_LPM_U2 = 2,\n\tUSB3_LPM_U3 = 3,\n};\n\nenum usb_charger_state {\n\tUSB_CHARGER_DEFAULT = 0,\n\tUSB_CHARGER_PRESENT = 1,\n\tUSB_CHARGER_ABSENT = 2,\n};\n\nenum usb_charger_type {\n\tUNKNOWN_TYPE = 0,\n\tSDP_TYPE = 1,\n\tDCP_TYPE = 2,\n\tCDP_TYPE = 3,\n\tACA_TYPE = 4,\n};\n\nenum usb_chg_state {\n\tUSB_CHG_STATE_UNDEFINED = 0,\n\tUSB_CHG_STATE_WAIT_FOR_DCD = 1,\n\tUSB_CHG_STATE_DCD_DONE = 2,\n\tUSB_CHG_STATE_PRIMARY_DONE = 3,\n\tUSB_CHG_STATE_SECONDARY_DONE = 4,\n\tUSB_CHG_STATE_DETECTED = 5,\n};\n\nenum usb_chg_type {\n\tUSB_CHG_TYPE_NONE = 0,\n\tUSB_CHG_TYPE_PD = 1,\n\tUSB_CHG_TYPE_C = 2,\n\tUSB_CHG_TYPE_PROPRIETARY = 3,\n\tUSB_CHG_TYPE_BC12_DCP = 4,\n\tUSB_CHG_TYPE_BC12_CDP = 5,\n\tUSB_CHG_TYPE_BC12_SDP = 6,\n\tUSB_CHG_TYPE_OTHER = 7,\n\tUSB_CHG_TYPE_VBUS = 8,\n\tUSB_CHG_TYPE_UNKNOWN = 9,\n\tUSB_CHG_TYPE_DEDICATED = 10,\n};\n\nenum usb_data_roles {\n\tDR_NONE = 0,\n\tDR_HOST = 1,\n\tDR_DEVICE = 2,\n};\n\nenum usb_dev_authorize_policy {\n\tUSB_DEVICE_AUTHORIZE_NONE = 0,\n\tUSB_DEVICE_AUTHORIZE_ALL = 1,\n\tUSB_DEVICE_AUTHORIZE_INTERNAL = 2,\n};\n\nenum usb_device_speed {\n\tUSB_SPEED_UNKNOWN = 0,\n\tUSB_SPEED_LOW = 1,\n\tUSB_SPEED_FULL = 2,\n\tUSB_SPEED_HIGH = 3,\n\tUSB_SPEED_WIRELESS = 4,\n\tUSB_SPEED_SUPER = 5,\n\tUSB_SPEED_SUPER_PLUS = 6,\n};\n\nenum usb_device_state {\n\tUSB_STATE_NOTATTACHED = 0,\n\tUSB_STATE_ATTACHED = 1,\n\tUSB_STATE_POWERED = 2,\n\tUSB_STATE_RECONNECTING = 3,\n\tUSB_STATE_UNAUTHENTICATED = 4,\n\tUSB_STATE_DEFAULT = 5,\n\tUSB_STATE_ADDRESS = 6,\n\tUSB_STATE_CONFIGURED = 7,\n\tUSB_STATE_SUSPENDED = 8,\n};\n\nenum usb_dr_mode {\n\tUSB_DR_MODE_UNKNOWN = 0,\n\tUSB_DR_MODE_HOST = 1,\n\tUSB_DR_MODE_PERIPHERAL = 2,\n\tUSB_DR_MODE_OTG = 3,\n};\n\nenum usb_interface_condition {\n\tUSB_INTERFACE_UNBOUND = 0,\n\tUSB_INTERFACE_BINDING = 1,\n\tUSB_INTERFACE_BOUND = 2,\n\tUSB_INTERFACE_UNBINDING = 3,\n};\n\nenum usb_led_event {\n\tUSB_LED_EVENT_HOST = 0,\n\tUSB_LED_EVENT_GADGET = 1,\n};\n\nenum usb_link_tunnel_mode {\n\tUSB_LINK_UNKNOWN = 0,\n\tUSB_LINK_NATIVE = 1,\n\tUSB_LINK_TUNNELED = 2,\n};\n\nenum usb_otg_state {\n\tOTG_STATE_UNDEFINED = 0,\n\tOTG_STATE_B_IDLE = 1,\n\tOTG_STATE_B_SRP_INIT = 2,\n\tOTG_STATE_B_PERIPHERAL = 3,\n\tOTG_STATE_B_WAIT_ACON = 4,\n\tOTG_STATE_B_HOST = 5,\n\tOTG_STATE_A_IDLE = 6,\n\tOTG_STATE_A_WAIT_VRISE = 7,\n\tOTG_STATE_A_WAIT_BCON = 8,\n\tOTG_STATE_A_HOST = 9,\n\tOTG_STATE_A_SUSPEND = 10,\n\tOTG_STATE_A_PERIPHERAL = 11,\n\tOTG_STATE_A_WAIT_VFALL = 12,\n\tOTG_STATE_A_VBUS_ERR = 13,\n};\n\nenum usb_pd_control_mux {\n\tUSB_PD_CTRL_MUX_NO_CHANGE = 0,\n\tUSB_PD_CTRL_MUX_NONE = 1,\n\tUSB_PD_CTRL_MUX_USB = 2,\n\tUSB_PD_CTRL_MUX_DP = 3,\n\tUSB_PD_CTRL_MUX_DOCK = 4,\n\tUSB_PD_CTRL_MUX_AUTO = 5,\n\tUSB_PD_CTRL_MUX_COUNT = 6,\n};\n\nenum usb_pd_control_role {\n\tUSB_PD_CTRL_ROLE_NO_CHANGE = 0,\n\tUSB_PD_CTRL_ROLE_TOGGLE_ON = 1,\n\tUSB_PD_CTRL_ROLE_TOGGLE_OFF = 2,\n\tUSB_PD_CTRL_ROLE_FORCE_SINK = 3,\n\tUSB_PD_CTRL_ROLE_FORCE_SOURCE = 4,\n\tUSB_PD_CTRL_ROLE_FREEZE = 5,\n\tUSB_PD_CTRL_ROLE_COUNT = 6,\n};\n\nenum usb_pd_control_swap {\n\tUSB_PD_CTRL_SWAP_NONE = 0,\n\tUSB_PD_CTRL_SWAP_DATA = 1,\n\tUSB_PD_CTRL_SWAP_POWER = 2,\n\tUSB_PD_CTRL_SWAP_VCONN = 3,\n\tUSB_PD_CTRL_SWAP_COUNT = 4,\n};\n\nenum usb_phy_events {\n\tUSB_EVENT_NONE = 0,\n\tUSB_EVENT_VBUS = 1,\n\tUSB_EVENT_ID = 2,\n\tUSB_EVENT_CHARGER = 3,\n\tUSB_EVENT_ENUMERATED = 4,\n};\n\nenum usb_phy_interface {\n\tUSBPHY_INTERFACE_MODE_UNKNOWN = 0,\n\tUSBPHY_INTERFACE_MODE_UTMI = 1,\n\tUSBPHY_INTERFACE_MODE_UTMIW = 2,\n\tUSBPHY_INTERFACE_MODE_ULPI = 3,\n\tUSBPHY_INTERFACE_MODE_SERIAL = 4,\n\tUSBPHY_INTERFACE_MODE_HSIC = 5,\n};\n\nenum usb_phy_type {\n\tUSB_PHY_TYPE_UNDEFINED = 0,\n\tUSB_PHY_TYPE_USB2 = 1,\n\tUSB_PHY_TYPE_USB3 = 2,\n};\n\nenum usb_port_connect_type {\n\tUSB_PORT_CONNECT_TYPE_UNKNOWN = 0,\n\tUSB_PORT_CONNECT_TYPE_HOT_PLUG = 1,\n\tUSB_PORT_CONNECT_TYPE_HARD_WIRED = 2,\n\tUSB_PORT_NOT_USED = 3,\n};\n\nenum usb_role {\n\tUSB_ROLE_NONE = 0,\n\tUSB_ROLE_HOST = 1,\n\tUSB_ROLE_DEVICE = 2,\n};\n\nenum usb_ssp_rate {\n\tUSB_SSP_GEN_UNKNOWN = 0,\n\tUSB_SSP_GEN_2x1 = 1,\n\tUSB_SSP_GEN_1x2 = 2,\n\tUSB_SSP_GEN_2x2 = 3,\n};\n\nenum usb_wireless_status {\n\tUSB_WIRELESS_STATUS_NA = 0,\n\tUSB_WIRELESS_STATUS_DISCONNECTED = 1,\n\tUSB_WIRELESS_STATUS_CONNECTED = 2,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum utp_data_direction {\n\tUTP_NO_DATA_TRANSFER = 0,\n\tUTP_HOST_TO_DEVICE = 1,\n\tUTP_DEVICE_TO_HOST = 2,\n};\n\nenum utp_ocs {\n\tOCS_SUCCESS = 0,\n\tOCS_INVALID_CMD_TABLE_ATTR = 1,\n\tOCS_INVALID_PRDT_ATTR = 2,\n\tOCS_MISMATCH_DATA_BUF_SIZE = 3,\n\tOCS_MISMATCH_RESP_UPIU_SIZE = 4,\n\tOCS_PEER_COMM_FAILURE = 5,\n\tOCS_ABORTED = 6,\n\tOCS_FATAL_ERROR = 7,\n\tOCS_DEVICE_FATAL_ERROR = 8,\n\tOCS_INVALID_CRYPTO_CONFIG = 9,\n\tOCS_GENERAL_CRYPTO_ERROR = 10,\n\tOCS_INVALID_COMMAND_STATUS = 15,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum v4l2_av1_segment_feature {\n\tV4L2_AV1_SEG_LVL_ALT_Q = 0,\n\tV4L2_AV1_SEG_LVL_ALT_LF_Y_V = 1,\n\tV4L2_AV1_SEG_LVL_REF_FRAME = 5,\n\tV4L2_AV1_SEG_LVL_REF_SKIP = 6,\n\tV4L2_AV1_SEG_LVL_REF_GLOBALMV = 7,\n\tV4L2_AV1_SEG_LVL_MAX = 8,\n};\n\nenum v4l2_fwnode_bus_type {\n\tV4L2_FWNODE_BUS_TYPE_GUESS = 0,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_CPHY = 1,\n\tV4L2_FWNODE_BUS_TYPE_CSI1 = 2,\n\tV4L2_FWNODE_BUS_TYPE_CCP2 = 3,\n\tV4L2_FWNODE_BUS_TYPE_CSI2_DPHY = 4,\n\tV4L2_FWNODE_BUS_TYPE_PARALLEL = 5,\n\tV4L2_FWNODE_BUS_TYPE_BT656 = 6,\n\tV4L2_FWNODE_BUS_TYPE_DPI = 7,\n\tNR_OF_V4L2_FWNODE_BUS_TYPE = 8,\n};\n\nenum v4l2_preemphasis {\n\tV4L2_PREEMPHASIS_DISABLED = 0,\n\tV4L2_PREEMPHASIS_50_uS = 1,\n\tV4L2_PREEMPHASIS_75_uS = 2,\n};\n\nenum vc3_clk {\n\tVC3_REF = 0,\n\tVC3_SE1 = 1,\n\tVC3_SE2 = 2,\n\tVC3_SE3 = 3,\n\tVC3_DIFF1 = 4,\n\tVC3_DIFF2 = 5,\n};\n\nenum vc3_clk_mux {\n\tVC3_SE1_MUX = 0,\n\tVC3_SE2_MUX = 1,\n\tVC3_SE3_MUX = 2,\n\tVC3_DIFF1_MUX = 3,\n\tVC3_DIFF2_MUX = 4,\n};\n\nenum vc3_div {\n\tVC3_DIV1 = 0,\n\tVC3_DIV2 = 1,\n\tVC3_DIV3 = 2,\n\tVC3_DIV4 = 3,\n\tVC3_DIV5 = 4,\n};\n\nenum vc3_div_mux {\n\tVC3_DIV1_MUX = 0,\n\tVC3_DIV3_MUX = 1,\n\tVC3_DIV4_MUX = 2,\n};\n\nenum vc3_pfd {\n\tVC3_PFD1 = 0,\n\tVC3_PFD2 = 1,\n\tVC3_PFD3 = 2,\n};\n\nenum vc3_pfd_mux {\n\tVC3_PFD2_MUX = 0,\n\tVC3_PFD3_MUX = 1,\n};\n\nenum vc3_pll {\n\tVC3_PLL1 = 0,\n\tVC3_PLL2 = 1,\n\tVC3_PLL3 = 2,\n};\n\nenum vc5_model {\n\tIDT_VC5_5P49V5923 = 0,\n\tIDT_VC5_5P49V5925 = 1,\n\tIDT_VC5_5P49V5933 = 2,\n\tIDT_VC5_5P49V5935 = 3,\n\tIDT_VC6_5P49V60 = 4,\n\tIDT_VC6_5P49V6901 = 5,\n\tIDT_VC6_5P49V6965 = 6,\n\tIDT_VC6_5P49V6975 = 7,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vco_freq_range {\n\tVCO_LOW = 700000000,\n\tVCO_MID = 1200000000,\n\tVCO_HIGH = 2200000000,\n\tVCO_HIGH_HIGH = 3100000000,\n\tVCO_MAX = 4000000000,\n};\n\nenum vcpu_sysreg {\n\t__INVALID_SYSREG__ = 0,\n\tMPIDR_EL1 = 1,\n\tCLIDR_EL1 = 2,\n\tCSSELR_EL1 = 3,\n\tTPIDR_EL0 = 4,\n\tTPIDRRO_EL0 = 5,\n\tTPIDR_EL1 = 6,\n\tCNTKCTL_EL1 = 7,\n\tPAR_EL1 = 8,\n\tMDCCINT_EL1 = 9,\n\tOSLSR_EL1 = 10,\n\tDISR_EL1 = 11,\n\tPMCR_EL0 = 12,\n\tPMSELR_EL0 = 13,\n\tPMEVCNTR0_EL0 = 14,\n\tPMEVCNTR30_EL0 = 44,\n\tPMCCNTR_EL0 = 45,\n\tPMEVTYPER0_EL0 = 46,\n\tPMEVTYPER30_EL0 = 76,\n\tPMCCFILTR_EL0 = 77,\n\tPMCNTENSET_EL0 = 78,\n\tPMINTENSET_EL1 = 79,\n\tPMOVSSET_EL0 = 80,\n\tPMUSERENR_EL0 = 81,\n\tAPIAKEYLO_EL1 = 82,\n\tAPIAKEYHI_EL1 = 83,\n\tAPIBKEYLO_EL1 = 84,\n\tAPIBKEYHI_EL1 = 85,\n\tAPDAKEYLO_EL1 = 86,\n\tAPDAKEYHI_EL1 = 87,\n\tAPDBKEYLO_EL1 = 88,\n\tAPDBKEYHI_EL1 = 89,\n\tAPGAKEYLO_EL1 = 90,\n\tAPGAKEYHI_EL1 = 91,\n\tRGSR_EL1 = 92,\n\tGCR_EL1 = 93,\n\tTFSRE0_EL1 = 94,\n\tPOR_EL0 = 95,\n\tSVCR = 96,\n\tFPMR = 97,\n\tDACR32_EL2 = 98,\n\tIFSR32_EL2 = 99,\n\tFPEXC32_EL2 = 100,\n\tDBGVCR32_EL2 = 101,\n\tACTLR_EL2 = 102,\n\tCPTR_EL2 = 103,\n\tHACR_EL2 = 104,\n\tZCR_EL2 = 105,\n\tTTBR0_EL2 = 106,\n\tTTBR1_EL2 = 107,\n\tTCR_EL2 = 108,\n\tPIRE0_EL2 = 109,\n\tPIR_EL2 = 110,\n\tPOR_EL2 = 111,\n\tSPSR_EL2 = 112,\n\tELR_EL2 = 113,\n\tAFSR0_EL2 = 114,\n\tAFSR1_EL2 = 115,\n\tESR_EL2 = 116,\n\tFAR_EL2 = 117,\n\tHPFAR_EL2 = 118,\n\tMAIR_EL2 = 119,\n\tAMAIR_EL2 = 120,\n\tVBAR_EL2 = 121,\n\tRVBAR_EL2 = 122,\n\tCONTEXTIDR_EL2 = 123,\n\tSP_EL2 = 124,\n\tCNTHP_CTL_EL2 = 125,\n\tCNTHP_CVAL_EL2 = 126,\n\tCNTHV_CTL_EL2 = 127,\n\tCNTHV_CVAL_EL2 = 128,\n\t__SANITISED_REG_START__ = 129,\n\t__after___SANITISED_REG_START__ = 128,\n\tSCTLR_EL2 = 129,\n\tTCR2_EL2 = 130,\n\tSCTLR2_EL2 = 131,\n\tMDCR_EL2 = 132,\n\tCNTHCTL_EL2 = 133,\n\t__VNCR_START__ = 134,\n\t__after___VNCR_START__ = 133,\n\t__before_SCTLR_EL1 = 134,\n\tSCTLR_EL1 = 168,\n\t__after_SCTLR_EL1 = 168,\n\t__before_ACTLR_EL1 = 169,\n\tACTLR_EL1 = 169,\n\t__after_ACTLR_EL1 = 169,\n\t__before_CPACR_EL1 = 170,\n\tCPACR_EL1 = 166,\n\t__after_CPACR_EL1 = 169,\n\t__before_ZCR_EL1 = 170,\n\tZCR_EL1 = 194,\n\t__after_ZCR_EL1 = 194,\n\t__before_TTBR0_EL1 = 195,\n\tTTBR0_EL1 = 198,\n\t__after_TTBR0_EL1 = 198,\n\t__before_TTBR1_EL1 = 199,\n\tTTBR1_EL1 = 200,\n\t__after_TTBR1_EL1 = 200,\n\t__before_TCR_EL1 = 201,\n\tTCR_EL1 = 170,\n\t__after_TCR_EL1 = 200,\n\t__before_TCR2_EL1 = 201,\n\tTCR2_EL1 = 212,\n\t__after_TCR2_EL1 = 212,\n\t__before_SCTLR2_EL1 = 213,\n\tSCTLR2_EL1 = 213,\n\t__after_SCTLR2_EL1 = 213,\n\t__before_ESR_EL1 = 214,\n\tESR_EL1 = 173,\n\t__after_ESR_EL1 = 213,\n\t__before_AFSR0_EL1 = 214,\n\tAFSR0_EL1 = 171,\n\t__after_AFSR0_EL1 = 213,\n\t__before_AFSR1_EL1 = 214,\n\tAFSR1_EL1 = 172,\n\t__after_AFSR1_EL1 = 213,\n\t__before_FAR_EL1 = 214,\n\tFAR_EL1 = 202,\n\t__after_FAR_EL1 = 213,\n\t__before_MAIR_EL1 = 214,\n\tMAIR_EL1 = 174,\n\t__after_MAIR_EL1 = 213,\n\t__before_VBAR_EL1 = 214,\n\tVBAR_EL1 = 208,\n\t__after_VBAR_EL1 = 213,\n\t__before_CONTEXTIDR_EL1 = 214,\n\tCONTEXTIDR_EL1 = 167,\n\t__after_CONTEXTIDR_EL1 = 213,\n\t__before_AMAIR_EL1 = 214,\n\tAMAIR_EL1 = 175,\n\t__after_AMAIR_EL1 = 213,\n\t__before_MDSCR_EL1 = 214,\n\tMDSCR_EL1 = 177,\n\t__after_MDSCR_EL1 = 213,\n\t__before_ELR_EL1 = 214,\n\tELR_EL1 = 204,\n\t__after_ELR_EL1 = 213,\n\t__before_SP_EL1 = 214,\n\tSP_EL1 = 206,\n\t__after_SP_EL1 = 213,\n\t__before_SPSR_EL1 = 214,\n\tSPSR_EL1 = 178,\n\t__after_SPSR_EL1 = 213,\n\t__before_TFSR_EL1 = 214,\n\tTFSR_EL1 = 184,\n\t__after_TFSR_EL1 = 213,\n\t__before_VPIDR_EL2 = 214,\n\tVPIDR_EL2 = 151,\n\t__after_VPIDR_EL2 = 213,\n\t__before_VMPIDR_EL2 = 214,\n\tVMPIDR_EL2 = 144,\n\t__after_VMPIDR_EL2 = 213,\n\t__before_HCR_EL2 = 214,\n\tHCR_EL2 = 149,\n\t__after_HCR_EL2 = 213,\n\t__before_HSTR_EL2 = 214,\n\tHSTR_EL2 = 150,\n\t__after_HSTR_EL2 = 213,\n\t__before_VTTBR_EL2 = 214,\n\tVTTBR_EL2 = 138,\n\t__after_VTTBR_EL2 = 213,\n\t__before_VTCR_EL2 = 214,\n\tVTCR_EL2 = 142,\n\t__after_VTCR_EL2 = 213,\n\t__before_TPIDR_EL2 = 214,\n\tTPIDR_EL2 = 152,\n\t__after_TPIDR_EL2 = 213,\n\t__before_HCRX_EL2 = 214,\n\tHCRX_EL2 = 154,\n\t__after_HCRX_EL2 = 213,\n\t__before_PIR_EL1 = 214,\n\tPIR_EL1 = 218,\n\t__after_PIR_EL1 = 218,\n\t__before_PIRE0_EL1 = 219,\n\tPIRE0_EL1 = 216,\n\t__after_PIRE0_EL1 = 218,\n\t__before_POR_EL1 = 219,\n\tPOR_EL1 = 219,\n\t__after_POR_EL1 = 219,\n\t__before_VDISR_EL2 = 220,\n\tVDISR_EL2 = 294,\n\t__after_VDISR_EL2 = 294,\n\t__before_VSESR_EL2 = 295,\n\tVSESR_EL2 = 295,\n\t__after_VSESR_EL2 = 295,\n\t__before_HFGRTR_EL2 = 296,\n\tHFGRTR_EL2 = 189,\n\t__after_HFGRTR_EL2 = 295,\n\t__before_HFGWTR_EL2 = 296,\n\tHFGWTR_EL2 = 190,\n\t__after_HFGWTR_EL2 = 295,\n\t__before_HFGITR_EL2 = 296,\n\tHFGITR_EL2 = 191,\n\t__after_HFGITR_EL2 = 295,\n\t__before_HDFGRTR_EL2 = 296,\n\tHDFGRTR_EL2 = 192,\n\t__after_HDFGRTR_EL2 = 295,\n\t__before_HDFGWTR_EL2 = 296,\n\tHDFGWTR_EL2 = 193,\n\t__after_HDFGWTR_EL2 = 295,\n\t__before_HAFGRTR_EL2 = 296,\n\tHAFGRTR_EL2 = 195,\n\t__after_HAFGRTR_EL2 = 295,\n\t__before_HFGRTR2_EL2 = 296,\n\tHFGRTR2_EL2 = 222,\n\t__after_HFGRTR2_EL2 = 295,\n\t__before_HFGWTR2_EL2 = 296,\n\tHFGWTR2_EL2 = 223,\n\t__after_HFGWTR2_EL2 = 295,\n\t__before_HFGITR2_EL2 = 296,\n\tHFGITR2_EL2 = 232,\n\t__after_HFGITR2_EL2 = 295,\n\t__before_HDFGRTR2_EL2 = 296,\n\tHDFGRTR2_EL2 = 186,\n\t__after_HDFGRTR2_EL2 = 295,\n\t__before_HDFGWTR2_EL2 = 296,\n\tHDFGWTR2_EL2 = 188,\n\t__after_HDFGWTR2_EL2 = 295,\n\t__before_VNCR_EL2 = 296,\n\tVNCR_EL2 = 156,\n\t__after_VNCR_EL2 = 295,\n\t__before_CNTVOFF_EL2 = 296,\n\tCNTVOFF_EL2 = 146,\n\t__after_CNTVOFF_EL2 = 295,\n\t__before_CNTV_CVAL_EL0 = 296,\n\tCNTV_CVAL_EL0 = 179,\n\t__after_CNTV_CVAL_EL0 = 295,\n\t__before_CNTV_CTL_EL0 = 296,\n\tCNTV_CTL_EL0 = 180,\n\t__after_CNTV_CTL_EL0 = 295,\n\t__before_CNTP_CVAL_EL0 = 296,\n\tCNTP_CVAL_EL0 = 181,\n\t__after_CNTP_CVAL_EL0 = 295,\n\t__before_CNTP_CTL_EL0 = 296,\n\tCNTP_CTL_EL0 = 182,\n\t__after_CNTP_CTL_EL0 = 295,\n\t__before_ICH_LR0_EL2 = 296,\n\tICH_LR0_EL2 = 262,\n\t__after_ICH_LR0_EL2 = 295,\n\t__before_ICH_LR1_EL2 = 296,\n\tICH_LR1_EL2 = 263,\n\t__after_ICH_LR1_EL2 = 295,\n\t__before_ICH_LR2_EL2 = 296,\n\tICH_LR2_EL2 = 264,\n\t__after_ICH_LR2_EL2 = 295,\n\t__before_ICH_LR3_EL2 = 296,\n\tICH_LR3_EL2 = 265,\n\t__after_ICH_LR3_EL2 = 295,\n\t__before_ICH_LR4_EL2 = 296,\n\tICH_LR4_EL2 = 266,\n\t__after_ICH_LR4_EL2 = 295,\n\t__before_ICH_LR5_EL2 = 296,\n\tICH_LR5_EL2 = 267,\n\t__after_ICH_LR5_EL2 = 295,\n\t__before_ICH_LR6_EL2 = 296,\n\tICH_LR6_EL2 = 268,\n\t__after_ICH_LR6_EL2 = 295,\n\t__before_ICH_LR7_EL2 = 296,\n\tICH_LR7_EL2 = 269,\n\t__after_ICH_LR7_EL2 = 295,\n\t__before_ICH_LR8_EL2 = 296,\n\tICH_LR8_EL2 = 270,\n\t__after_ICH_LR8_EL2 = 295,\n\t__before_ICH_LR9_EL2 = 296,\n\tICH_LR9_EL2 = 271,\n\t__after_ICH_LR9_EL2 = 295,\n\t__before_ICH_LR10_EL2 = 296,\n\tICH_LR10_EL2 = 272,\n\t__after_ICH_LR10_EL2 = 295,\n\t__before_ICH_LR11_EL2 = 296,\n\tICH_LR11_EL2 = 273,\n\t__after_ICH_LR11_EL2 = 295,\n\t__before_ICH_LR12_EL2 = 296,\n\tICH_LR12_EL2 = 274,\n\t__after_ICH_LR12_EL2 = 295,\n\t__before_ICH_LR13_EL2 = 296,\n\tICH_LR13_EL2 = 275,\n\t__after_ICH_LR13_EL2 = 295,\n\t__before_ICH_LR14_EL2 = 296,\n\tICH_LR14_EL2 = 276,\n\t__after_ICH_LR14_EL2 = 295,\n\t__before_ICH_LR15_EL2 = 296,\n\tICH_LR15_EL2 = 277,\n\t__after_ICH_LR15_EL2 = 295,\n\t__before_ICH_AP0R0_EL2 = 296,\n\tICH_AP0R0_EL2 = 278,\n\t__after_ICH_AP0R0_EL2 = 295,\n\t__before_ICH_AP0R1_EL2 = 296,\n\tICH_AP0R1_EL2 = 279,\n\t__after_ICH_AP0R1_EL2 = 295,\n\t__before_ICH_AP0R2_EL2 = 296,\n\tICH_AP0R2_EL2 = 280,\n\t__after_ICH_AP0R2_EL2 = 295,\n\t__before_ICH_AP0R3_EL2 = 296,\n\tICH_AP0R3_EL2 = 281,\n\t__after_ICH_AP0R3_EL2 = 295,\n\t__before_ICH_AP1R0_EL2 = 296,\n\tICH_AP1R0_EL2 = 282,\n\t__after_ICH_AP1R0_EL2 = 295,\n\t__before_ICH_AP1R1_EL2 = 296,\n\tICH_AP1R1_EL2 = 283,\n\t__after_ICH_AP1R1_EL2 = 295,\n\t__before_ICH_AP1R2_EL2 = 296,\n\tICH_AP1R2_EL2 = 284,\n\t__after_ICH_AP1R2_EL2 = 295,\n\t__before_ICH_AP1R3_EL2 = 296,\n\tICH_AP1R3_EL2 = 285,\n\t__after_ICH_AP1R3_EL2 = 295,\n\t__before_ICH_HCR_EL2 = 296,\n\tICH_HCR_EL2 = 286,\n\t__after_ICH_HCR_EL2 = 295,\n\t__before_ICH_VMCR_EL2 = 296,\n\tICH_VMCR_EL2 = 287,\n\t__after_ICH_VMCR_EL2 = 295,\n\tNR_SYS_REGS = 296,\n};\n\nenum vdso_abi {\n\tVDSO_ABI_AA64 = 0,\n\tVDSO_ABI_AA32 = 1,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_ARCHTIMER = 1,\n\tVDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT = 2,\n\tVDSO_CLOCKMODE_MAX = 3,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum vec_type {\n\tARM64_VEC_SVE = 0,\n\tARM64_VEC_SME = 1,\n\tARM64_VEC_MAX = 2,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum vfio_device_mig_state {\n\tVFIO_DEVICE_STATE_ERROR = 0,\n\tVFIO_DEVICE_STATE_STOP = 1,\n\tVFIO_DEVICE_STATE_RUNNING = 2,\n\tVFIO_DEVICE_STATE_STOP_COPY = 3,\n\tVFIO_DEVICE_STATE_RESUMING = 4,\n\tVFIO_DEVICE_STATE_RUNNING_P2P = 5,\n\tVFIO_DEVICE_STATE_PRE_COPY = 6,\n\tVFIO_DEVICE_STATE_PRE_COPY_P2P = 7,\n\tVFIO_DEVICE_STATE_NR = 8,\n};\n\nenum vfio_group_type {\n\tVFIO_IOMMU = 0,\n\tVFIO_EMULATED_IOMMU = 1,\n\tVFIO_NO_IOMMU = 2,\n};\n\nenum vfio_pci_io_width {\n\tVFIO_PCI_IO_WIDTH_1 = 1,\n\tVFIO_PCI_IO_WIDTH_2 = 2,\n\tVFIO_PCI_IO_WIDTH_4 = 4,\n\tVFIO_PCI_IO_WIDTH_8 = 8,\n};\n\nenum vgic_irq_config {\n\tVGIC_CONFIG_EDGE = 0,\n\tVGIC_CONFIG_LEVEL = 1,\n};\n\nenum vgic_type {\n\tVGIC_V2 = 0,\n\tVGIC_V3 = 1,\n\tVGIC_V5 = 2,\n};\n\nenum virtio_balloon_config_read {\n\tVIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0,\n};\n\nenum virtio_balloon_vq {\n\tVIRTIO_BALLOON_VQ_INFLATE = 0,\n\tVIRTIO_BALLOON_VQ_DEFLATE = 1,\n\tVIRTIO_BALLOON_VQ_STATS = 2,\n\tVIRTIO_BALLOON_VQ_FREE_PAGE = 3,\n\tVIRTIO_BALLOON_VQ_REPORTING = 4,\n\tVIRTIO_BALLOON_VQ_MAX = 5,\n};\n\nenum virtnet_xmit_type {\n\tVIRTNET_XMIT_TYPE_SKB = 0,\n\tVIRTNET_XMIT_TYPE_SKB_ORPHAN = 1,\n\tVIRTNET_XMIT_TYPE_XDP = 2,\n\tVIRTNET_XMIT_TYPE_XSK = 3,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vlan_flags {\n\tVLAN_FLAG_REORDER_HDR = 1,\n\tVLAN_FLAG_GVRP = 2,\n\tVLAN_FLAG_LOOSE_BINDING = 4,\n\tVLAN_FLAG_MVRP = 8,\n\tVLAN_FLAG_BRIDGE_BINDING = 16,\n};\n\nenum vlan_protos {\n\tVLAN_PROTO_8021Q = 0,\n\tVLAN_PROTO_8021AD = 1,\n\tVLAN_PROTO_NUM = 2,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_DMA = 4,\n\tPGALLOC_DMA32 = 5,\n\tPGALLOC_NORMAL = 6,\n\tPGALLOC_MOVABLE = 7,\n\tALLOCSTALL_DMA = 8,\n\tALLOCSTALL_DMA32 = 9,\n\tALLOCSTALL_NORMAL = 10,\n\tALLOCSTALL_MOVABLE = 11,\n\tPGSCAN_SKIP_DMA = 12,\n\tPGSCAN_SKIP_DMA32 = 13,\n\tPGSCAN_SKIP_NORMAL = 14,\n\tPGSCAN_SKIP_MOVABLE = 15,\n\tPGFREE = 16,\n\tPGACTIVATE = 17,\n\tPGDEACTIVATE = 18,\n\tPGLAZYFREE = 19,\n\tPGFAULT = 20,\n\tPGMAJFAULT = 21,\n\tPGLAZYFREED = 22,\n\tPGREFILL = 23,\n\tPGREUSE = 24,\n\tPGSTEAL_KSWAPD = 25,\n\tPGSTEAL_DIRECT = 26,\n\tPGSTEAL_KHUGEPAGED = 27,\n\tPGSTEAL_PROACTIVE = 28,\n\tPGSCAN_KSWAPD = 29,\n\tPGSCAN_DIRECT = 30,\n\tPGSCAN_KHUGEPAGED = 31,\n\tPGSCAN_PROACTIVE = 32,\n\tPGSCAN_DIRECT_THROTTLE = 33,\n\tPGSCAN_ANON = 34,\n\tPGSCAN_FILE = 35,\n\tPGSTEAL_ANON = 36,\n\tPGSTEAL_FILE = 37,\n\tPGSCAN_ZONE_RECLAIM_SUCCESS = 38,\n\tPGSCAN_ZONE_RECLAIM_FAILED = 39,\n\tPGINODESTEAL = 40,\n\tSLABS_SCANNED = 41,\n\tKSWAPD_INODESTEAL = 42,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 43,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 44,\n\tPAGEOUTRUN = 45,\n\tPGROTATED = 46,\n\tDROP_PAGECACHE = 47,\n\tDROP_SLAB = 48,\n\tOOM_KILL = 49,\n\tNUMA_PTE_UPDATES = 50,\n\tNUMA_HUGE_PTE_UPDATES = 51,\n\tNUMA_HINT_FAULTS = 52,\n\tNUMA_HINT_FAULTS_LOCAL = 53,\n\tNUMA_PAGE_MIGRATE = 54,\n\tPGMIGRATE_SUCCESS = 55,\n\tPGMIGRATE_FAIL = 56,\n\tTHP_MIGRATION_SUCCESS = 57,\n\tTHP_MIGRATION_FAIL = 58,\n\tTHP_MIGRATION_SPLIT = 59,\n\tCOMPACTMIGRATE_SCANNED = 60,\n\tCOMPACTFREE_SCANNED = 61,\n\tCOMPACTISOLATED = 62,\n\tCOMPACTSTALL = 63,\n\tCOMPACTFAIL = 64,\n\tCOMPACTSUCCESS = 65,\n\tKCOMPACTD_WAKE = 66,\n\tKCOMPACTD_MIGRATE_SCANNED = 67,\n\tKCOMPACTD_FREE_SCANNED = 68,\n\tHTLB_BUDDY_PGALLOC = 69,\n\tHTLB_BUDDY_PGALLOC_FAIL = 70,\n\tCMA_ALLOC_SUCCESS = 71,\n\tCMA_ALLOC_FAIL = 72,\n\tUNEVICTABLE_PGCULLED = 73,\n\tUNEVICTABLE_PGSCANNED = 74,\n\tUNEVICTABLE_PGRESCUED = 75,\n\tUNEVICTABLE_PGMLOCKED = 76,\n\tUNEVICTABLE_PGMUNLOCKED = 77,\n\tUNEVICTABLE_PGCLEARED = 78,\n\tUNEVICTABLE_PGSTRANDED = 79,\n\tTHP_FAULT_ALLOC = 80,\n\tTHP_FAULT_FALLBACK = 81,\n\tTHP_FAULT_FALLBACK_CHARGE = 82,\n\tTHP_COLLAPSE_ALLOC = 83,\n\tTHP_COLLAPSE_ALLOC_FAILED = 84,\n\tTHP_FILE_ALLOC = 85,\n\tTHP_FILE_FALLBACK = 86,\n\tTHP_FILE_FALLBACK_CHARGE = 87,\n\tTHP_FILE_MAPPED = 88,\n\tTHP_SPLIT_PAGE = 89,\n\tTHP_SPLIT_PAGE_FAILED = 90,\n\tTHP_DEFERRED_SPLIT_PAGE = 91,\n\tTHP_UNDERUSED_SPLIT_PAGE = 92,\n\tTHP_SPLIT_PMD = 93,\n\tTHP_SCAN_EXCEED_NONE_PTE = 94,\n\tTHP_SCAN_EXCEED_SWAP_PTE = 95,\n\tTHP_SCAN_EXCEED_SHARED_PTE = 96,\n\tTHP_ZERO_PAGE_ALLOC = 97,\n\tTHP_ZERO_PAGE_ALLOC_FAILED = 98,\n\tTHP_SWPOUT = 99,\n\tTHP_SWPOUT_FALLBACK = 100,\n\tBALLOON_INFLATE = 101,\n\tBALLOON_DEFLATE = 102,\n\tBALLOON_MIGRATE = 103,\n\tSWAP_RA = 104,\n\tSWAP_RA_HIT = 105,\n\tSWPIN_ZERO = 106,\n\tSWPOUT_ZERO = 107,\n\tKSM_SWPIN_COPY = 108,\n\tCOW_KSM = 109,\n\tNR_VM_EVENT_ITEMS = 110,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vma_resv_mode {\n\tVMA_NEEDS_RESV = 0,\n\tVMA_COMMIT_RESV = 1,\n\tVMA_END_RESV = 2,\n\tVMA_ADD_RESV = 3,\n\tVMA_DEL_RESV = 4,\n};\n\nenum vmpressure_levels {\n\tVMPRESSURE_LOW = 0,\n\tVMPRESSURE_MEDIUM = 1,\n\tVMPRESSURE_CRITICAL = 2,\n\tVMPRESSURE_NUM_LEVELS = 3,\n};\n\nenum vmpressure_modes {\n\tVMPRESSURE_NO_PASSTHROUGH = 0,\n\tVMPRESSURE_HIERARCHY = 1,\n\tVMPRESSURE_LOCAL = 2,\n\tVMPRESSURE_NUM_MODES = 3,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum voltage_change_dir {\n\tNO_CHANGE = 0,\n\tDOWN___3 = 1,\n\tUP___3 = 2,\n};\n\nenum vp_vq_vector_policy {\n\tVP_VQ_VECTOR_POLICY_EACH = 0,\n\tVP_VQ_VECTOR_POLICY_SHARED_SLOW = 1,\n\tVP_VQ_VECTOR_POLICY_SHARED = 2,\n};\n\nenum vq_layout {\n\tVQ_LAYOUT_SPLIT = 0,\n\tVQ_LAYOUT_PACKED = 1,\n\tVQ_LAYOUT_SPLIT_IN_ORDER = 2,\n\tVQ_LAYOUT_PACKED_IN_ORDER = 3,\n};\n\nenum vsc85xx_global_phy {\n\tVSC88XX_BASE_ADDR = 0,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_resize_en {\n\tWB_RESIZE_EN_IDLE = 0,\n\tWB_RESIZE_EN_DECREASE = 1,\n\tWB_RESIZE_EN_INCREASE = 2,\n};\n\nenum wb_resize_hint {\n\tWB_RESIZE_HINT_KEEP = 0,\n\tWB_RESIZE_HINT_DECREASE = 1,\n\tWB_RESIZE_HINT_INCREASE = 2,\n};\n\nenum wb_resize_status {\n\tWB_RESIZE_STATUS_IDLE = 0,\n\tWB_RESIZE_STATUS_IN_PROGRESS = 1,\n\tWB_RESIZE_STATUS_COMPLETE_SUCCESS = 2,\n\tWB_RESIZE_STATUS_GENERAL_FAILURE = 3,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum why_no_delegation4 {\n\tWND4_NOT_WANTED = 0,\n\tWND4_CONTENTION = 1,\n\tWND4_RESOURCE = 2,\n\tWND4_NOT_SUPP_FTYPE = 3,\n\tWND4_WRITE_DELEG_NOT_SUPP_FTYPE = 4,\n\tWND4_NOT_SUPP_UPGRADE = 5,\n\tWND4_NOT_SUPP_DOWNGRADE = 6,\n\tWND4_CANCELLED = 7,\n\tWND4_IS_DIR = 8,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 43,\n\tWORK_OFFQ_POOL_BITS = 31,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wp_types {\n\tESDHC_WP_NONE = 0,\n\tESDHC_WP_CONTROLLER = 1,\n\tESDHC_WP_GPIO = 2,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 75000,\n\tMAYDAY_INITIAL_TIMEOUT = 2,\n\tMAYDAY_INTERVAL = 25,\n\tCREATE_COOLDOWN = 250,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 512,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum x1e80100_functions {\n\tmsm_mux_gpio___41 = 0,\n\tmsm_mux_RESOUT_GPIO = 1,\n\tmsm_mux_aon_cci___2 = 2,\n\tmsm_mux_aoss_cti___12 = 3,\n\tmsm_mux_atest_char___36 = 4,\n\tmsm_mux_atest_char0___17 = 5,\n\tmsm_mux_atest_char1___17 = 6,\n\tmsm_mux_atest_char2___17 = 7,\n\tmsm_mux_atest_char3___17 = 8,\n\tmsm_mux_atest_usb___12 = 9,\n\tmsm_mux_audio_ext = 10,\n\tmsm_mux_audio_ref___18 = 11,\n\tmsm_mux_cam_aon = 12,\n\tmsm_mux_cam_mclk___29 = 13,\n\tmsm_mux_cci_async___24 = 14,\n\tmsm_mux_cci_i2c___24 = 15,\n\tmsm_mux_cci_timer0___19 = 16,\n\tmsm_mux_cci_timer1___19 = 17,\n\tmsm_mux_cci_timer2___19 = 18,\n\tmsm_mux_cci_timer3___18 = 19,\n\tmsm_mux_cci_timer4___17 = 20,\n\tmsm_mux_cmu_rng0___2 = 21,\n\tmsm_mux_cmu_rng1___2 = 22,\n\tmsm_mux_cmu_rng2___2 = 23,\n\tmsm_mux_cmu_rng3___2 = 24,\n\tmsm_mux_cri_trng___30 = 25,\n\tmsm_mux_dbg_out___30 = 26,\n\tmsm_mux_ddr_bist___26 = 27,\n\tmsm_mux_ddr_pxi0___24 = 28,\n\tmsm_mux_ddr_pxi1___23 = 29,\n\tmsm_mux_ddr_pxi2___21 = 30,\n\tmsm_mux_ddr_pxi3___21 = 31,\n\tmsm_mux_ddr_pxi4___4 = 32,\n\tmsm_mux_ddr_pxi5___4 = 33,\n\tmsm_mux_ddr_pxi6___3 = 34,\n\tmsm_mux_ddr_pxi7___3 = 35,\n\tmsm_mux_edp0_hot___3 = 36,\n\tmsm_mux_edp0_lcd___4 = 37,\n\tmsm_mux_edp1_hot___2 = 38,\n\tmsm_mux_edp1_lcd___4 = 39,\n\tmsm_mux_eusb0_ac = 40,\n\tmsm_mux_eusb1_ac = 41,\n\tmsm_mux_eusb2_ac = 42,\n\tmsm_mux_eusb3_ac = 43,\n\tmsm_mux_eusb5_ac = 44,\n\tmsm_mux_eusb6_ac = 45,\n\tmsm_mux_gcc_gp1___25 = 46,\n\tmsm_mux_gcc_gp2___25 = 47,\n\tmsm_mux_gcc_gp3___25 = 48,\n\tmsm_mux_i2s0_data0___6 = 49,\n\tmsm_mux_i2s0_data1___6 = 50,\n\tmsm_mux_i2s0_sck___6 = 51,\n\tmsm_mux_i2s0_ws___6 = 52,\n\tmsm_mux_i2s1_data0___5 = 53,\n\tmsm_mux_i2s1_data1___5 = 54,\n\tmsm_mux_i2s1_sck___5 = 55,\n\tmsm_mux_i2s1_ws___5 = 56,\n\tmsm_mux_ibi_i3c___15 = 57,\n\tmsm_mux_jitter_bist___27 = 58,\n\tmsm_mux_mdp_vsync0___14 = 59,\n\tmsm_mux_mdp_vsync1___14 = 60,\n\tmsm_mux_mdp_vsync2___14 = 61,\n\tmsm_mux_mdp_vsync3___14 = 62,\n\tmsm_mux_mdp_vsync4___4 = 63,\n\tmsm_mux_mdp_vsync5___4 = 64,\n\tmsm_mux_mdp_vsync6 = 65,\n\tmsm_mux_mdp_vsync7 = 66,\n\tmsm_mux_mdp_vsync8 = 67,\n\tmsm_mux_pcie3_clk___3 = 68,\n\tmsm_mux_pcie4_clk = 69,\n\tmsm_mux_pcie5_clk = 70,\n\tmsm_mux_pcie6a_clk = 71,\n\tmsm_mux_pcie6b_clk = 72,\n\tmsm_mux_phase_flag___26 = 73,\n\tmsm_mux_pll_bist___20 = 74,\n\tmsm_mux_pll_clk___10 = 75,\n\tmsm_mux_prng_rosc0___13 = 76,\n\tmsm_mux_prng_rosc1___13 = 77,\n\tmsm_mux_prng_rosc2___13 = 78,\n\tmsm_mux_prng_rosc3___13 = 79,\n\tmsm_mux_qdss_cti___27 = 80,\n\tmsm_mux_qdss_gpio___20 = 81,\n\tmsm_mux_qspi00 = 82,\n\tmsm_mux_qspi01 = 83,\n\tmsm_mux_qspi02 = 84,\n\tmsm_mux_qspi03 = 85,\n\tmsm_mux_qspi0_clk___2 = 86,\n\tmsm_mux_qspi0_cs0 = 87,\n\tmsm_mux_qspi0_cs1 = 88,\n\tmsm_mux_qup0_se0___5 = 89,\n\tmsm_mux_qup0_se1___5 = 90,\n\tmsm_mux_qup0_se2___5 = 91,\n\tmsm_mux_qup0_se3___5 = 92,\n\tmsm_mux_qup0_se4___5 = 93,\n\tmsm_mux_qup0_se5___4 = 94,\n\tmsm_mux_qup0_se6___3 = 95,\n\tmsm_mux_qup0_se7___2 = 96,\n\tmsm_mux_qup1_se0___9 = 97,\n\tmsm_mux_qup1_se1___9 = 98,\n\tmsm_mux_qup1_se2___9 = 99,\n\tmsm_mux_qup1_se3___9 = 100,\n\tmsm_mux_qup1_se4___9 = 101,\n\tmsm_mux_qup1_se5___8 = 102,\n\tmsm_mux_qup1_se6___8 = 103,\n\tmsm_mux_qup1_se7___6 = 104,\n\tmsm_mux_qup2_se0___7 = 105,\n\tmsm_mux_qup2_se1___6 = 106,\n\tmsm_mux_qup2_se2___6 = 107,\n\tmsm_mux_qup2_se3___6 = 108,\n\tmsm_mux_qup2_se4___6 = 109,\n\tmsm_mux_qup2_se5___5 = 110,\n\tmsm_mux_qup2_se6___5 = 111,\n\tmsm_mux_qup2_se7___4 = 112,\n\tmsm_mux_sd_write___24 = 113,\n\tmsm_mux_sdc4_clk___15 = 114,\n\tmsm_mux_sdc4_cmd___15 = 115,\n\tmsm_mux_sdc4_data0 = 116,\n\tmsm_mux_sdc4_data1 = 117,\n\tmsm_mux_sdc4_data2 = 118,\n\tmsm_mux_sdc4_data3 = 119,\n\tmsm_mux_sys_throttle___2 = 120,\n\tmsm_mux_tb_trig___8 = 121,\n\tmsm_mux_tgu_ch0___18 = 122,\n\tmsm_mux_tgu_ch1___18 = 123,\n\tmsm_mux_tgu_ch2___15 = 124,\n\tmsm_mux_tgu_ch3___15 = 125,\n\tmsm_mux_tgu_ch4___3 = 126,\n\tmsm_mux_tgu_ch5___3 = 127,\n\tmsm_mux_tgu_ch6___2 = 128,\n\tmsm_mux_tgu_ch7___2 = 129,\n\tmsm_mux_tmess_prng0___9 = 130,\n\tmsm_mux_tmess_prng1___9 = 131,\n\tmsm_mux_tmess_prng2___9 = 132,\n\tmsm_mux_tmess_prng3___9 = 133,\n\tmsm_mux_tsense_pwm1___23 = 134,\n\tmsm_mux_tsense_pwm2___23 = 135,\n\tmsm_mux_tsense_pwm3___8 = 136,\n\tmsm_mux_tsense_pwm4___6 = 137,\n\tmsm_mux_usb0_dp___2 = 138,\n\tmsm_mux_usb0_phy___3 = 139,\n\tmsm_mux_usb0_sbrx___2 = 140,\n\tmsm_mux_usb0_sbtx___2 = 141,\n\tmsm_mux_usb1_dp___2 = 142,\n\tmsm_mux_usb1_phy___3 = 143,\n\tmsm_mux_usb1_sbrx___2 = 144,\n\tmsm_mux_usb1_sbtx___2 = 145,\n\tmsm_mux_usb2_dp = 146,\n\tmsm_mux_usb2_phy = 147,\n\tmsm_mux_usb2_sbrx = 148,\n\tmsm_mux_usb2_sbtx = 149,\n\tmsm_mux_vsense_trigger___19 = 150,\n\tmsm_mux_____36 = 151,\n};\n\nenum x509_actions {\n\tACT_x509_extract_key_data = 0,\n\tACT_x509_extract_name_segment = 1,\n\tACT_x509_note_OID = 2,\n\tACT_x509_note_issuer = 3,\n\tACT_x509_note_not_after = 4,\n\tACT_x509_note_not_before = 5,\n\tACT_x509_note_params = 6,\n\tACT_x509_note_serial = 7,\n\tACT_x509_note_sig_algo = 8,\n\tACT_x509_note_signature = 9,\n\tACT_x509_note_subject = 10,\n\tACT_x509_note_tbs_certificate = 11,\n\tACT_x509_process_extension = 12,\n\tNR__x509_actions = 13,\n};\n\nenum x509_akid_actions {\n\tACT_x509_akid_note_kid = 0,\n\tACT_x509_akid_note_name = 1,\n\tACT_x509_akid_note_serial = 2,\n\tACT_x509_extract_name_segment___2 = 3,\n\tACT_x509_note_OID___2 = 4,\n\tNR__x509_akid_actions = 5,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xb_req_state {\n\txb_req_state_queued = 0,\n\txb_req_state_wait_reply = 1,\n\txb_req_state_got_reply = 2,\n\txb_req_state_aborted = 3,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xen_irq_type {\n\tIRQT_UNBOUND = 0,\n\tIRQT_PIRQ = 1,\n\tIRQT_VIRQ = 2,\n\tIRQT_IPI = 3,\n\tIRQT_EVTCHN = 4,\n};\n\nenum xenbus_state {\n\tXenbusStateUnknown = 0,\n\tXenbusStateInitialising = 1,\n\tXenbusStateInitWait = 2,\n\tXenbusStateInitialised = 3,\n\tXenbusStateConnected = 4,\n\tXenbusStateClosing = 5,\n\tXenbusStateClosed = 6,\n\tXenbusStateReconfiguring = 7,\n\tXenbusStateReconfigured = 8,\n};\n\nenum xenon_phy_type_enum {\n\tEMMC_5_0_PHY = 0,\n\tEMMC_5_1_PHY = 1,\n\tNR_PHY_TYPES = 2,\n};\n\nenum xenon_variant {\n\tXENON_A3700 = 0,\n\tXENON_AP806 = 1,\n\tXENON_AP807 = 2,\n\tXENON_CP110 = 3,\n\tXENON_AC5 = 4,\n};\n\nenum xenstore_init {\n\tXS_UNKNOWN = 0,\n\tXS_PV = 1,\n\tXS_HVM = 2,\n\tXS_LOCAL = 3,\n};\n\nenum xfer_buf_dir {\n\tTO_XFER_BUF = 0,\n\tFROM_XFER_BUF = 1,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xgbe_an {\n\tXGBE_AN_READY = 0,\n\tXGBE_AN_PAGE_RECEIVED = 1,\n\tXGBE_AN_INCOMPAT_LINK = 2,\n\tXGBE_AN_COMPLETE = 3,\n\tXGBE_AN_NO_LINK = 4,\n\tXGBE_AN_ERROR = 5,\n};\n\nenum xgbe_an_mode {\n\tXGBE_AN_MODE_CL73 = 0,\n\tXGBE_AN_MODE_CL73_REDRV = 1,\n\tXGBE_AN_MODE_CL37 = 2,\n\tXGBE_AN_MODE_CL37_SGMII = 3,\n\tXGBE_AN_MODE_NONE = 4,\n};\n\nenum xgbe_conn_type {\n\tXGBE_CONN_TYPE_NONE = 0,\n\tXGBE_CONN_TYPE_SFP = 1,\n\tXGBE_CONN_TYPE_MDIO = 2,\n\tXGBE_CONN_TYPE_RSVD1 = 3,\n\tXGBE_CONN_TYPE_BACKPLANE = 4,\n\tXGBE_CONN_TYPE_MAX = 5,\n};\n\nenum xgbe_ecc_sec {\n\tXGBE_ECC_SEC_TX = 0,\n\tXGBE_ECC_SEC_RX = 1,\n\tXGBE_ECC_SEC_DESC = 2,\n};\n\nenum xgbe_i2c_cmd {\n\tXGBE_I2C_CMD_READ = 0,\n\tXGBE_I2C_CMD_WRITE = 1,\n};\n\nenum xgbe_int {\n\tXGMAC_INT_DMA_CH_SR_TI = 0,\n\tXGMAC_INT_DMA_CH_SR_TPS = 1,\n\tXGMAC_INT_DMA_CH_SR_TBU = 2,\n\tXGMAC_INT_DMA_CH_SR_RI = 3,\n\tXGMAC_INT_DMA_CH_SR_RBU = 4,\n\tXGMAC_INT_DMA_CH_SR_RPS = 5,\n\tXGMAC_INT_DMA_CH_SR_TI_RI = 6,\n\tXGMAC_INT_DMA_CH_SR_FBE = 7,\n\tXGMAC_INT_DMA_ALL = 8,\n};\n\nenum xgbe_mb_cmd {\n\tXGBE_MB_CMD_POWER_OFF = 0,\n\tXGBE_MB_CMD_SET_1G = 1,\n\tXGBE_MB_CMD_SET_2_5G = 2,\n\tXGBE_MB_CMD_SET_10G_SFI = 3,\n\tXGBE_MB_CMD_SET_10G_KR = 4,\n\tXGBE_MB_CMD_RRC = 5,\n};\n\nenum xgbe_mb_subcmd {\n\tXGBE_MB_SUBCMD_NONE = 0,\n\tXGBE_MB_SUBCMD_RX_ADAP = 1,\n\tXGBE_MB_SUBCMD_ACTIVE = 0,\n\tXGBE_MB_SUBCMD_PASSIVE_1M = 1,\n\tXGBE_MB_SUBCMD_PASSIVE_3M = 2,\n\tXGBE_MB_SUBCMD_PASSIVE_OTHER = 3,\n\tXGBE_MB_SUBCMD_10MBITS = 0,\n\tXGBE_MB_SUBCMD_100MBITS = 1,\n\tXGBE_MB_SUBCMD_1G_SGMII = 2,\n\tXGBE_MB_SUBCMD_1G_KX = 3,\n};\n\nenum xgbe_mdio_mode {\n\tXGBE_MDIO_MODE_NONE = 0,\n\tXGBE_MDIO_MODE_CL22 = 1,\n\tXGBE_MDIO_MODE_CL45 = 2,\n};\n\nenum xgbe_mdio_reset {\n\tXGBE_MDIO_RESET_NONE = 0,\n\tXGBE_MDIO_RESET_I2C_GPIO = 1,\n\tXGBE_MDIO_RESET_INT_GPIO = 2,\n\tXGBE_MDIO_RESET_MAX = 3,\n};\n\nenum xgbe_mode {\n\tXGBE_MODE_KX_1000 = 0,\n\tXGBE_MODE_KX_2500 = 1,\n\tXGBE_MODE_KR = 2,\n\tXGBE_MODE_X = 3,\n\tXGBE_MODE_SGMII_10 = 4,\n\tXGBE_MODE_SGMII_100 = 5,\n\tXGBE_MODE_SGMII_1000 = 6,\n\tXGBE_MODE_SFI = 7,\n\tXGBE_MODE_UNKNOWN = 8,\n};\n\nenum xgbe_phy_redrv_if {\n\tXGBE_PHY_REDRV_IF_MDIO = 0,\n\tXGBE_PHY_REDRV_IF_I2C = 1,\n\tXGBE_PHY_REDRV_IF_MAX = 2,\n};\n\nenum xgbe_phy_redrv_mode {\n\tXGBE_PHY_REDRV_MODE_CX = 5,\n\tXGBE_PHY_REDRV_MODE_SR = 9,\n};\n\nenum xgbe_phy_redrv_model {\n\tXGBE_PHY_REDRV_MODEL_4223 = 0,\n\tXGBE_PHY_REDRV_MODEL_4227 = 1,\n\tXGBE_PHY_REDRV_MODEL_MAX = 2,\n};\n\nenum xgbe_port_mode {\n\tXGBE_PORT_MODE_RSVD = 0,\n\tXGBE_PORT_MODE_BACKPLANE = 1,\n\tXGBE_PORT_MODE_BACKPLANE_2500 = 2,\n\tXGBE_PORT_MODE_1000BASE_T = 3,\n\tXGBE_PORT_MODE_1000BASE_X = 4,\n\tXGBE_PORT_MODE_NBASE_T = 5,\n\tXGBE_PORT_MODE_10GBASE_T = 6,\n\tXGBE_PORT_MODE_10GBASE_R = 7,\n\tXGBE_PORT_MODE_SFP = 8,\n\tXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG = 9,\n\tXGBE_PORT_MODE_MAX = 10,\n};\n\nenum xgbe_rx {\n\tXGBE_RX_BPA = 0,\n\tXGBE_RX_XNP = 1,\n\tXGBE_RX_COMPLETE = 2,\n\tXGBE_RX_ERROR = 3,\n};\n\nenum xgbe_sfp_base {\n\tXGBE_SFP_BASE_UNKNOWN = 0,\n\tXGBE_SFP_BASE_1000_T = 1,\n\tXGBE_SFP_BASE_1000_SX = 2,\n\tXGBE_SFP_BASE_1000_LX = 3,\n\tXGBE_SFP_BASE_1000_CX = 4,\n\tXGBE_SFP_BASE_10000_SR = 5,\n\tXGBE_SFP_BASE_10000_LR = 6,\n\tXGBE_SFP_BASE_10000_LRM = 7,\n\tXGBE_SFP_BASE_10000_ER = 8,\n\tXGBE_SFP_BASE_10000_CR = 9,\n};\n\nenum xgbe_sfp_cable {\n\tXGBE_SFP_CABLE_UNKNOWN = 0,\n\tXGBE_SFP_CABLE_ACTIVE = 1,\n\tXGBE_SFP_CABLE_PASSIVE = 2,\n\tXGBE_SFP_CABLE_FIBER = 3,\n};\n\nenum xgbe_sfp_comm {\n\tXGBE_SFP_COMM_DIRECT = 0,\n\tXGBE_SFP_COMM_PCA9545 = 1,\n};\n\nenum xgbe_sfp_speed {\n\tXGBE_SFP_SPEED_UNKNOWN = 0,\n\tXGBE_SFP_SPEED_100_1000 = 1,\n\tXGBE_SFP_SPEED_1000 = 2,\n\tXGBE_SFP_SPEED_10000 = 3,\n};\n\nenum xgbe_speed {\n\tXGBE_SPEED_1000 = 0,\n\tXGBE_SPEED_2500 = 1,\n\tXGBE_SPEED_10000 = 2,\n\tXGBE_SPEEDS = 3,\n};\n\nenum xgbe_speedset {\n\tXGBE_SPEEDSET_1000_10000 = 0,\n\tXGBE_SPEEDSET_2500_10000 = 1,\n};\n\nenum xgbe_state {\n\tXGBE_DOWN = 0,\n\tXGBE_LINK_INIT = 1,\n\tXGBE_LINK_ERR = 2,\n\tXGBE_STOPPED = 3,\n};\n\nenum xgbe_xpcs_access {\n\tXGBE_XPCS_ACCESS_V1 = 0,\n\tXGBE_XPCS_ACCESS_V2 = 1,\n\tXGBE_XPCS_ACCESS_V3 = 2,\n};\n\nenum xgene_ahci_version {\n\tXGENE_AHCI_V1 = 1,\n\tXGENE_AHCI_V2 = 2,\n};\n\nenum xgene_cle_byte_store {\n\tNO_BYTE = 0,\n\tFIRST_BYTE = 1,\n\tSECOND_BYTE = 2,\n\tBOTH_BYTES = 3,\n};\n\nenum xgene_cle_cmd_type {\n\tCLE_CMD_WR = 1,\n\tCLE_CMD_RD = 2,\n\tCLE_CMD_AVL_ADD = 8,\n\tCLE_CMD_AVL_DEL = 16,\n\tCLE_CMD_AVL_SRCH = 32,\n};\n\nenum xgene_cle_dram_type {\n\tPKT_RAM = 0,\n\tRSS_IDT = 1,\n\tRSS_IPV4_HASH_SKEY = 2,\n\tPTREE_RAM = 12,\n\tAVL_RAM = 13,\n\tDB_RAM = 14,\n};\n\nenum xgene_cle_ipv4_rss_hashtype {\n\tRSS_IPV4_8B = 0,\n\tRSS_IPV4_12B = 1,\n};\n\nenum xgene_cle_node_type {\n\tINV = 0,\n\tKN = 1,\n\tEWDN = 2,\n\tRES_NODE = 3,\n};\n\nenum xgene_cle_op_type {\n\tEQT = 0,\n\tNEQT = 1,\n\tLTEQT = 2,\n\tGTEQT = 3,\n\tAND = 4,\n\tNAND = 5,\n};\n\nenum xgene_cle_parser {\n\tPARSER0 = 0,\n\tPARSER1 = 1,\n\tPARSER2 = 2,\n\tPARSER_ALL = 3,\n};\n\nenum xgene_cle_prot_type {\n\tXGENE_CLE_TCP = 0,\n\tXGENE_CLE_UDP = 1,\n\tXGENE_CLE_ESP = 2,\n\tXGENE_CLE_OTHER = 3,\n};\n\nenum xgene_cle_prot_version {\n\tXGENE_CLE_IPV4 = 0,\n};\n\nenum xgene_cle_ptree_dbptrs {\n\tDB_RES_DROP = 0,\n\tDB_RES_DEF = 1,\n\tDB_RES_ACCEPT = 2,\n\tDB_MAX_PTRS = 3,\n};\n\nenum xgene_cle_ptree_nodes {\n\tPKT_TYPE_NODE = 0,\n\tPKT_PROT_NODE = 1,\n\tRSS_IPV4_TCP_NODE = 2,\n\tRSS_IPV4_UDP_NODE = 3,\n\tRSS_IPV4_OTHERS_NODE = 4,\n\tLAST_NODE = 5,\n\tMAX_NODES = 6,\n};\n\nenum xgene_enet_buf_len {\n\tSIZE_2K = 2048,\n\tSIZE_4K = 4096,\n\tSIZE_16K = 16384,\n};\n\nenum xgene_enet_cmd {\n\tXGENE_ENET_WR_CMD = 2147483648,\n\tXGENE_ENET_RD_CMD = 1073741824,\n};\n\nenum xgene_enet_err_code {\n\tHBF_READ_DATA = 3,\n\tHBF_LL_READ = 4,\n\tBAD_WORK_MSG = 6,\n\tBUFPOOL_TIMEOUT = 15,\n\tINGRESS_CRC = 16,\n\tINGRESS_CHECKSUM = 17,\n\tINGRESS_TRUNC_FRAME = 18,\n\tINGRESS_PKT_LEN = 19,\n\tINGRESS_PKT_UNDER = 20,\n\tINGRESS_FIFO_OVERRUN = 21,\n\tINGRESS_CHECKSUM_COMPUTE = 26,\n\tERR_CODE_INVALID = 27,\n};\n\nenum xgene_enet_id {\n\tXGENE_ENET1 = 1,\n\tXGENE_ENET2 = 2,\n};\n\nenum xgene_enet_ring_bufnum {\n\tRING_BUFNUM_REGULAR = 0,\n\tRING_BUFNUM_BUFPOOL = 32,\n\tRING_BUFNUM_INVALID = 33,\n};\n\nenum xgene_enet_ring_cfgsize {\n\tRING_CFGSIZE_512B = 0,\n\tRING_CFGSIZE_2KB = 1,\n\tRING_CFGSIZE_16KB = 2,\n\tRING_CFGSIZE_64KB = 3,\n\tRING_CFGSIZE_512KB = 4,\n\tRING_CFGSIZE_INVALID = 5,\n};\n\nenum xgene_enet_ring_type {\n\tRING_DISABLED = 0,\n\tRING_REGULAR = 1,\n\tRING_BUFPOOL = 2,\n};\n\nenum xgene_enet_rm {\n\tRM0 = 0,\n\tRM1 = 1,\n\tRM3 = 3,\n};\n\nenum xgene_mdio_id {\n\tXGENE_MDIO_RGMII = 1,\n\tXGENE_MDIO_XFI = 2,\n};\n\nenum xgene_phy_mode {\n\tMODE_SATA = 0,\n\tMODE_SGMII = 1,\n\tMODE_PCIE = 2,\n\tMODE_USB = 3,\n\tMODE_XFI = 4,\n\tMODE_MAX = 5,\n};\n\nenum xgene_phy_speed {\n\tPHY_SPEED_10 = 0,\n\tPHY_SPEED_100 = 1,\n\tPHY_SPEED_1000 = 2,\n};\n\nenum xgene_pll_type {\n\tPLL_TYPE_PCP = 0,\n\tPLL_TYPE_SOC = 1,\n};\n\nenum xgene_ring_owner {\n\tRING_OWNER_ETH0 = 0,\n\tRING_OWNER_ETH1 = 1,\n\tRING_OWNER_CPU = 15,\n\tRING_OWNER_INVALID = 16,\n};\n\nenum xhci_cancelled_td_status {\n\tTD_DIRTY = 0,\n\tTD_HALTED = 1,\n\tTD_CLEARING_CACHE = 2,\n\tTD_CLEARING_CACHE_DEFERRED = 3,\n\tTD_CLEARED = 4,\n};\n\nenum xhci_ep_reset_type {\n\tEP_HARD_RESET = 0,\n\tEP_SOFT_RESET = 1,\n};\n\nenum xhci_overhead_type {\n\tLS_OVERHEAD_TYPE = 0,\n\tFS_OVERHEAD_TYPE = 1,\n\tHS_OVERHEAD_TYPE = 2,\n};\n\nenum xhci_ring_type {\n\tTYPE_CTRL = 0,\n\tTYPE_ISOC = 1,\n\tTYPE_BULK = 2,\n\tTYPE_INTR = 3,\n\tTYPE_STREAM = 4,\n\tTYPE_COMMAND = 5,\n\tTYPE_EVENT = 6,\n};\n\nenum xhci_setup_dev {\n\tSETUP_CONTEXT_ONLY = 0,\n\tSETUP_CONTEXT_ADDRESS = 1,\n};\n\nenum xhci_sideband_notify_type {\n\tXHCI_SIDEBAND_XFER_RING_FREE = 0,\n};\n\nenum xhci_sideband_type {\n\tXHCI_SIDEBAND_AUDIO = 0,\n\tXHCI_SIDEBAND_VENDOR = 1,\n};\n\nenum xilinx_cpm_version {\n\tCPM = 0,\n\tCPM5 = 1,\n\tCPM5_HOST1 = 2,\n\tCPM5NC_HOST = 3,\n};\n\nenum xilinx_pl_dma_version {\n\tXDMA = 0,\n\tQDMA = 1,\n};\n\nenum xprt_transports {\n\tXPRT_TRANSPORT_UDP = 17,\n\tXPRT_TRANSPORT_TCP = 6,\n\tXPRT_TRANSPORT_BC_TCP = -2147483642,\n\tXPRT_TRANSPORT_RDMA = 256,\n\tXPRT_TRANSPORT_BC_RDMA = -2147483392,\n\tXPRT_TRANSPORT_LOCAL = 257,\n\tXPRT_TRANSPORT_TCP_TLS = 258,\n};\n\nenum xprt_xid_rb_cmp {\n\tXID_RB_EQUAL = 0,\n\tXID_RB_LEFT = 1,\n\tXID_RB_RIGHT = 2,\n};\n\nenum xprtsec_policies {\n\tRPC_XPRTSEC_NONE = 0,\n\tRPC_XPRTSEC_TLS_ANON = 1,\n\tRPC_XPRTSEC_TLS_X509 = 2,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xsd_sockmsg_type {\n\tXS_CONTROL = 0,\n\tXS_DIRECTORY = 1,\n\tXS_READ = 2,\n\tXS_GET_PERMS = 3,\n\tXS_WATCH = 4,\n\tXS_UNWATCH = 5,\n\tXS_TRANSACTION_START = 6,\n\tXS_TRANSACTION_END = 7,\n\tXS_INTRODUCE = 8,\n\tXS_RELEASE = 9,\n\tXS_GET_DOMAIN_PATH = 10,\n\tXS_WRITE = 11,\n\tXS_MKDIR = 12,\n\tXS_RM = 13,\n\tXS_SET_PERMS = 14,\n\tXS_WATCH_EVENT = 15,\n\tXS_ERROR = 16,\n\tXS_IS_DOMAIN_INTRODUCED = 17,\n\tXS_RESUME = 18,\n\tXS_SET_TARGET = 19,\n\tXS_RESET_WATCHES = 21,\n\tXS_DIRECTORY_PART = 22,\n\tXS_TYPE_COUNT = 23,\n\tXS_INVALID = 65535,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum yukon_ec_rev {\n\tCHIP_REV_YU_EC_A1 = 0,\n\tCHIP_REV_YU_EC_A2 = 1,\n\tCHIP_REV_YU_EC_A3 = 2,\n};\n\nenum yukon_ec_u_rev {\n\tCHIP_REV_YU_EC_U_A0 = 1,\n\tCHIP_REV_YU_EC_U_A1 = 2,\n\tCHIP_REV_YU_EC_U_B0 = 3,\n\tCHIP_REV_YU_EC_U_B1 = 5,\n};\n\nenum yukon_ex_rev {\n\tCHIP_REV_YU_EX_A0 = 1,\n\tCHIP_REV_YU_EX_B0 = 2,\n};\n\nenum yukon_fe_p_rev {\n\tCHIP_REV_YU_FE2_A0 = 0,\n};\n\nenum yukon_prm_rev {\n\tCHIP_REV_YU_PRM_Z1 = 1,\n\tCHIP_REV_YU_PRM_A0 = 2,\n};\n\nenum yukon_supr_rev {\n\tCHIP_REV_YU_SU_A0 = 0,\n\tCHIP_REV_YU_SU_B0 = 1,\n\tCHIP_REV_YU_SU_B1 = 3,\n};\n\nenum yukon_xl_rev {\n\tCHIP_REV_YU_XL_A0 = 0,\n\tCHIP_REV_YU_XL_A1 = 1,\n\tCHIP_REV_YU_XL_A2 = 2,\n\tCHIP_REV_YU_XL_A3 = 3,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_FREE_CMA_PAGES = 9,\n\tNR_VM_ZONE_STAT_ITEMS = 10,\n};\n\nenum zone_type {\n\tZONE_DMA = 0,\n\tZONE_DMA32 = 1,\n\tZONE_NORMAL = 2,\n\tZONE_MOVABLE = 3,\n\t__MAX_NR_ZONES = 4,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\nenum zynqmp_pm_request_ack {\n\tZYNQMP_PM_REQUEST_ACK_NO = 1,\n\tZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,\n\tZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,\n};\n\nenum zynqmp_pm_reset {\n\tZYNQMP_PM_RESET_START = 1000,\n\tZYNQMP_PM_RESET_PCIE_CFG = 1000,\n\tZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,\n\tZYNQMP_PM_RESET_PCIE_CTRL = 1002,\n\tZYNQMP_PM_RESET_DP = 1003,\n\tZYNQMP_PM_RESET_SWDT_CRF = 1004,\n\tZYNQMP_PM_RESET_AFI_FM5 = 1005,\n\tZYNQMP_PM_RESET_AFI_FM4 = 1006,\n\tZYNQMP_PM_RESET_AFI_FM3 = 1007,\n\tZYNQMP_PM_RESET_AFI_FM2 = 1008,\n\tZYNQMP_PM_RESET_AFI_FM1 = 1009,\n\tZYNQMP_PM_RESET_AFI_FM0 = 1010,\n\tZYNQMP_PM_RESET_GDMA = 1011,\n\tZYNQMP_PM_RESET_GPU_PP1 = 1012,\n\tZYNQMP_PM_RESET_GPU_PP0 = 1013,\n\tZYNQMP_PM_RESET_GPU = 1014,\n\tZYNQMP_PM_RESET_GT = 1015,\n\tZYNQMP_PM_RESET_SATA = 1016,\n\tZYNQMP_PM_RESET_ACPU3_PWRON = 1017,\n\tZYNQMP_PM_RESET_ACPU2_PWRON = 1018,\n\tZYNQMP_PM_RESET_ACPU1_PWRON = 1019,\n\tZYNQMP_PM_RESET_ACPU0_PWRON = 1020,\n\tZYNQMP_PM_RESET_APU_L2 = 1021,\n\tZYNQMP_PM_RESET_ACPU3 = 1022,\n\tZYNQMP_PM_RESET_ACPU2 = 1023,\n\tZYNQMP_PM_RESET_ACPU1 = 1024,\n\tZYNQMP_PM_RESET_ACPU0 = 1025,\n\tZYNQMP_PM_RESET_DDR = 1026,\n\tZYNQMP_PM_RESET_APM_FPD = 1027,\n\tZYNQMP_PM_RESET_SOFT = 1028,\n\tZYNQMP_PM_RESET_GEM0 = 1029,\n\tZYNQMP_PM_RESET_GEM1 = 1030,\n\tZYNQMP_PM_RESET_GEM2 = 1031,\n\tZYNQMP_PM_RESET_GEM3 = 1032,\n\tZYNQMP_PM_RESET_QSPI = 1033,\n\tZYNQMP_PM_RESET_UART0 = 1034,\n\tZYNQMP_PM_RESET_UART1 = 1035,\n\tZYNQMP_PM_RESET_SPI0 = 1036,\n\tZYNQMP_PM_RESET_SPI1 = 1037,\n\tZYNQMP_PM_RESET_SDIO0 = 1038,\n\tZYNQMP_PM_RESET_SDIO1 = 1039,\n\tZYNQMP_PM_RESET_CAN0 = 1040,\n\tZYNQMP_PM_RESET_CAN1 = 1041,\n\tZYNQMP_PM_RESET_I2C0 = 1042,\n\tZYNQMP_PM_RESET_I2C1 = 1043,\n\tZYNQMP_PM_RESET_TTC0 = 1044,\n\tZYNQMP_PM_RESET_TTC1 = 1045,\n\tZYNQMP_PM_RESET_TTC2 = 1046,\n\tZYNQMP_PM_RESET_TTC3 = 1047,\n\tZYNQMP_PM_RESET_SWDT_CRL = 1048,\n\tZYNQMP_PM_RESET_NAND = 1049,\n\tZYNQMP_PM_RESET_ADMA = 1050,\n\tZYNQMP_PM_RESET_GPIO = 1051,\n\tZYNQMP_PM_RESET_IOU_CC = 1052,\n\tZYNQMP_PM_RESET_TIMESTAMP = 1053,\n\tZYNQMP_PM_RESET_RPU_R50 = 1054,\n\tZYNQMP_PM_RESET_RPU_R51 = 1055,\n\tZYNQMP_PM_RESET_RPU_AMBA = 1056,\n\tZYNQMP_PM_RESET_OCM = 1057,\n\tZYNQMP_PM_RESET_RPU_PGE = 1058,\n\tZYNQMP_PM_RESET_USB0_CORERESET = 1059,\n\tZYNQMP_PM_RESET_USB1_CORERESET = 1060,\n\tZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,\n\tZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,\n\tZYNQMP_PM_RESET_USB0_APB = 1063,\n\tZYNQMP_PM_RESET_USB1_APB = 1064,\n\tZYNQMP_PM_RESET_IPI = 1065,\n\tZYNQMP_PM_RESET_APM_LPD = 1066,\n\tZYNQMP_PM_RESET_RTC = 1067,\n\tZYNQMP_PM_RESET_SYSMON = 1068,\n\tZYNQMP_PM_RESET_AFI_FM6 = 1069,\n\tZYNQMP_PM_RESET_LPD_SWDT = 1070,\n\tZYNQMP_PM_RESET_FPD = 1071,\n\tZYNQMP_PM_RESET_RPU_DBG1 = 1072,\n\tZYNQMP_PM_RESET_RPU_DBG0 = 1073,\n\tZYNQMP_PM_RESET_DBG_LPD = 1074,\n\tZYNQMP_PM_RESET_DBG_FPD = 1075,\n\tZYNQMP_PM_RESET_APLL = 1076,\n\tZYNQMP_PM_RESET_DPLL = 1077,\n\tZYNQMP_PM_RESET_VPLL = 1078,\n\tZYNQMP_PM_RESET_IOPLL = 1079,\n\tZYNQMP_PM_RESET_RPLL = 1080,\n\tZYNQMP_PM_RESET_GPO3_PL_0 = 1081,\n\tZYNQMP_PM_RESET_GPO3_PL_1 = 1082,\n\tZYNQMP_PM_RESET_GPO3_PL_2 = 1083,\n\tZYNQMP_PM_RESET_GPO3_PL_3 = 1084,\n\tZYNQMP_PM_RESET_GPO3_PL_4 = 1085,\n\tZYNQMP_PM_RESET_GPO3_PL_5 = 1086,\n\tZYNQMP_PM_RESET_GPO3_PL_6 = 1087,\n\tZYNQMP_PM_RESET_GPO3_PL_7 = 1088,\n\tZYNQMP_PM_RESET_GPO3_PL_8 = 1089,\n\tZYNQMP_PM_RESET_GPO3_PL_9 = 1090,\n\tZYNQMP_PM_RESET_GPO3_PL_10 = 1091,\n\tZYNQMP_PM_RESET_GPO3_PL_11 = 1092,\n\tZYNQMP_PM_RESET_GPO3_PL_12 = 1093,\n\tZYNQMP_PM_RESET_GPO3_PL_13 = 1094,\n\tZYNQMP_PM_RESET_GPO3_PL_14 = 1095,\n\tZYNQMP_PM_RESET_GPO3_PL_15 = 1096,\n\tZYNQMP_PM_RESET_GPO3_PL_16 = 1097,\n\tZYNQMP_PM_RESET_GPO3_PL_17 = 1098,\n\tZYNQMP_PM_RESET_GPO3_PL_18 = 1099,\n\tZYNQMP_PM_RESET_GPO3_PL_19 = 1100,\n\tZYNQMP_PM_RESET_GPO3_PL_20 = 1101,\n\tZYNQMP_PM_RESET_GPO3_PL_21 = 1102,\n\tZYNQMP_PM_RESET_GPO3_PL_22 = 1103,\n\tZYNQMP_PM_RESET_GPO3_PL_23 = 1104,\n\tZYNQMP_PM_RESET_GPO3_PL_24 = 1105,\n\tZYNQMP_PM_RESET_GPO3_PL_25 = 1106,\n\tZYNQMP_PM_RESET_GPO3_PL_26 = 1107,\n\tZYNQMP_PM_RESET_GPO3_PL_27 = 1108,\n\tZYNQMP_PM_RESET_GPO3_PL_28 = 1109,\n\tZYNQMP_PM_RESET_GPO3_PL_29 = 1110,\n\tZYNQMP_PM_RESET_GPO3_PL_30 = 1111,\n\tZYNQMP_PM_RESET_GPO3_PL_31 = 1112,\n\tZYNQMP_PM_RESET_RPU_LS = 1113,\n\tZYNQMP_PM_RESET_PS_ONLY = 1114,\n\tZYNQMP_PM_RESET_PL = 1115,\n\tZYNQMP_PM_RESET_PS_PL0 = 1116,\n\tZYNQMP_PM_RESET_PS_PL1 = 1117,\n\tZYNQMP_PM_RESET_PS_PL2 = 1118,\n\tZYNQMP_PM_RESET_PS_PL3 = 1119,\n\tZYNQMP_PM_RESET_END = 1119,\n};\n\nenum zynqmp_pm_reset_action {\n\tPM_RESET_ACTION_RELEASE = 0,\n\tPM_RESET_ACTION_ASSERT = 1,\n\tPM_RESET_ACTION_PULSE = 2,\n};\n\nenum zynqmp_pm_shutdown_subtype {\n\tZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,\n\tZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,\n\tZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,\n};\n\nenum zynqmp_pm_shutdown_type {\n\tZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,\n\tZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,\n\tZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,\n};\n\nenum zynqmp_pm_suspend_reason {\n\tSUSPEND_POWER_REQUEST = 201,\n\tSUSPEND_ALERT = 202,\n\tSUSPEND_SYSTEM_SHUTDOWN = 203,\n};\n\ntypedef _Bool bool;\n\ntypedef __int128 unsigned __u128;\n\ntypedef __u128 u128;\n\ntypedef u128 freelist_full_t;\n\ntypedef char acpi_bus_id[8];\n\ntypedef char acpi_device_class[20];\n\ntypedef char acpi_device_name[40];\n\ntypedef char *acpi_string;\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_daddr_t;\n\ntypedef int __kernel_ipc_pid_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_mqd_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __s32;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef __s32 s32;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_daddr_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_key_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_off_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef s32 dma_cookie_t;\n\ntypedef int ext4_grpblk_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef int initcall_entry_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef int kprobe_opcode_t;\n\ntypedef int mhp_t;\n\ntypedef int mm_id_mapcount_t;\n\ntypedef int mpi_size_t;\n\ntypedef __kernel_mqd_t mqd_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef int suspend_state_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef const int tracepoint_ptr_t;\n\ntypedef int vma_flag_t;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_long_t __kernel_ptrdiff_t;\n\ntypedef __kernel_long_t __kernel_ssize_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef long int mpi_limb_signed_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef volatile long int prel64_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 Elf64_Sxword;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef __s64 s64;\n\ntypedef s64 compat_loff_t;\n\ntypedef s64 compat_s64;\n\ntypedef s64 int64_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef long long int qsize_t;\n\ntypedef __s64 time64_t;\n\ntypedef int64_t xen_long_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef __u64 __virtio64;\n\ntypedef u64 acpi_bus_address;\n\ntypedef u64 acpi_integer;\n\ntypedef u64 acpi_io_address;\n\ntypedef u64 acpi_physical_address;\n\ntypedef u64 acpi_size;\n\ntypedef u64 arm_lpae_iopte;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef uint64_t blkif_sector_t;\n\ntypedef u64 clientid4;\n\ntypedef u64 compat_u64;\n\ntypedef u64 dart_iopte;\n\ntypedef u64 dma_addr_t;\n\ntypedef u64 efi_physical_addr_t;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef __be64 fdt64_t;\n\ntypedef u64 gfn_t;\n\ntypedef u64 gpa_t;\n\ntypedef u64 hfn_t;\n\ntypedef u64 hpa_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef hfn_t kvm_pfn_t;\n\ntypedef u64 kvm_pte_t;\n\ntypedef kvm_pte_t *kvm_pteref_t;\n\ntypedef long long unsigned int llu;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 ptdesc_t;\n\ntypedef ptdesc_t p4dval_t;\n\ntypedef u64 pci_bus_addr_t;\n\ntypedef ptdesc_t pgdval_t;\n\ntypedef u64 phys_addr_t;\n\ntypedef u64 phys_cpuid_t;\n\ntypedef ptdesc_t pmdval_t;\n\ntypedef ptdesc_t pteval_t;\n\ntypedef ptdesc_t pudval_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u64 sci_t;\n\ntypedef u64 sector_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef u64 upf_t;\n\ntypedef uint64_t vli_type;\n\ntypedef uint64_t xen_pfn_t;\n\ntypedef uint64_t xen_ulong_t;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef __kernel_ulong_t __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef long unsigned int mpi_limb_t;\n\ntypedef mpi_limb_t UWtype;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int cycles_t;\n\ntypedef long unsigned int dax_entry_t;\n\ntypedef long unsigned int efi_status_t;\n\ntypedef long unsigned int elf_greg_t;\n\ntypedef elf_greg_t elf_gregset_t[34];\n\ntypedef long unsigned int hva_t;\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int kimage_entry_t;\n\ntypedef mpi_limb_t *mpi_ptr_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int old_sigset_t;\n\ntypedef long unsigned int perf_trace_t[1024];\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int u_long;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulg;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef short unsigned int ush;\n\ntypedef ush Pos;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef u16 __compat_gid16_t;\n\ntypedef u16 __compat_gid_t;\n\ntypedef u16 __compat_uid16_t;\n\ntypedef u16 __compat_uid_t;\n\ntypedef __u16 __hc16;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef short unsigned int __kernel_old_gid_t;\n\ntypedef short unsigned int __kernel_old_uid_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __rpmsg16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef u16 acpi_owner_id;\n\ntypedef u16 acpi_rs_length;\n\ntypedef uint16_t blkif_vdev_t;\n\ntypedef __u16 comp_t;\n\ntypedef u16 compat_ipc_pid_t;\n\ntypedef u16 compat_mode_t;\n\ntypedef u16 compat_ushort_t;\n\ntypedef uint16_t domid_t;\n\ntypedef u16 efi_char16_t;\n\ntypedef __kernel_gid16_t gid16_t;\n\ntypedef uint16_t grant_status_t;\n\ntypedef __kernel_old_gid_t old_gid_t;\n\ntypedef __kernel_old_uid_t old_uid_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef __u16 port_id;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef u16 u_int16_t;\n\ntypedef short unsigned int u_short;\n\ntypedef u16 ucs2_char_t;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef u16 wchar_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 acpi_adr_space_type;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef u8 dscp_t;\n\ntypedef u8 efi_bool_t;\n\ntypedef u8 enet_addr_t[6];\n\ntypedef u8 rmap_age_t;\n\ntypedef unsigned char u8___2;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef unsigned char uch;\n\ntypedef __u8 virtio_net_ctrl_ack;\n\ntypedef uint8_t xen_domain_handle_t[16];\n\ntypedef unsigned int __u32;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef __u32 u32;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef unsigned int IPos;\n\ntypedef unsigned int OM_uint32;\n\ntypedef unsigned int RING_IDX;\n\ntypedef unsigned int UHWtype;\n\ntypedef uint32_t XENCONS_RING_IDX;\n\ntypedef uint32_t XENSTORE_RING_IDX;\n\ntypedef __u32 __be32;\n\ntypedef u32 __compat_gid32_t;\n\ntypedef u32 __compat_uid32_t;\n\ntypedef __u32 __dw;\n\ntypedef __u32 __hc32;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_gid_t;\n\ntypedef unsigned int __kernel_mode_t;\n\ntypedef unsigned int __kernel_old_dev_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __rpmsg32;\n\ntypedef __u32 __virtio32;\n\ntypedef __u32 __wsum;\n\ntypedef u32 acpi_event_status;\n\ntypedef u32 acpi_mutex_handle;\n\ntypedef u32 acpi_name;\n\ntypedef u32 acpi_object_type;\n\ntypedef u32 acpi_rsdesc_size;\n\ntypedef u32 acpi_status;\n\ntypedef unsigned int acr_flags_t;\n\ntypedef u32 arm_v7s_iopte;\n\ntypedef unsigned int autofs_wqt_t;\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef u32 compat_aio_context_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_dev_t;\n\ntypedef unsigned int compat_elf_greg_t;\n\ntypedef compat_elf_greg_t compat_elf_gregset_t[18];\n\ntypedef u32 compat_ino_t;\n\ntypedef u32 compat_old_sigset_t;\n\ntypedef u32 compat_sigset_word;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef u32 cppi5_tr_flags_t;\n\ntypedef u32 depot_flags_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef uint32_t drbg_flag_t;\n\ntypedef u32 efi_cc_event_algorithm_bitmap_t;\n\ntypedef u32 efi_cc_event_log_bitmap_t;\n\ntypedef u32 efi_cc_event_log_format_t;\n\ntypedef u32 efi_cc_mr_index_t;\n\ntypedef u32 efi_tcg2_event_log_format;\n\ntypedef u32 errseq_t;\n\ntypedef uint32_t event_word_t;\n\ntypedef uint32_t evtchn_port_t;\n\ntypedef unsigned int ext4_group_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef __be32 fdt32_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef uint32_t grant_handle_t;\n\ntypedef uint32_t grant_ref_t;\n\ntypedef unsigned int ioasid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef unsigned int mm_id_t;\n\ntypedef unsigned int mmc_pm_flag_t;\n\ntypedef __kernel_mode_t mode_t;\n\ntypedef u32 nlink_t;\n\ntypedef u32 note_buf_t[106];\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef unsigned int pipe_index_t;\n\ntypedef unsigned int pkvm_handle_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef __kernel_uid32_t qid_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef u32 rpc_authflavor_t;\n\ntypedef __be32 rpc_fraghdr;\n\ntypedef unsigned int sk_buff_data_t;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int speed_t;\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int tid_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef u32 u_int32_t;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef __le32 uprobe_opcode_t;\n\ntypedef unsigned int upstat_t;\n\ntypedef u32 usb_port_location_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\nstruct buffer_head;\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tunion {\n\t\tchar *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_char;\n\ntypedef struct {\n\tunion {\n\t\tevtchn_port_t *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_evtchn_port_t;\n\ntypedef struct {\n\tunion {\n\t\tint *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_int;\n\ntypedef struct {\n\tunion {\n\t\tunsigned char *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_uchar;\n\ntypedef struct {\n\tunion {\n\t\tuint32_t *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_uint32_t;\n\ntypedef struct {\n\tunion {\n\t\tuint64_t *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_uint64_t;\n\nstruct vcpu_runstate_info;\n\ntypedef struct {\n\tunion {\n\t\tstruct vcpu_runstate_info *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_vcpu_runstate_info;\n\ntypedef struct {\n\tunion {\n\t\tvoid *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_void;\n\ntypedef struct {\n\tunion {\n\t\txen_pfn_t *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_xen_pfn_t;\n\nstruct xen_processor_csd;\n\ntypedef struct {\n\tunion {\n\t\tstruct xen_processor_csd *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_xen_processor_csd;\n\nstruct xen_processor_cx;\n\ntypedef struct {\n\tunion {\n\t\tstruct xen_processor_cx *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_xen_processor_cx;\n\nstruct xen_processor_px;\n\ntypedef struct {\n\tunion {\n\t\tstruct xen_processor_px *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_xen_processor_px;\n\ntypedef struct {\n\tunion {\n\t\txen_ulong_t *p;\n\t\tuint64_t q;\n\t};\n} __guest_handle_xen_ulong_t;\n\ntypedef struct {\n\tlong unsigned int fds_bits[16];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef union {\n} aes_encrypt_arg;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef atomic64_t atomic_long_t;\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\ntypedef struct {\n\t__be64 a;\n\t__be64 b;\n} be128;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\nstruct permanent_flags_t {\n\t__be16 tag;\n\tu8 disable;\n\tu8 ownership;\n\tu8 deactivated;\n\tu8 readPubek;\n\tu8 disableOwnerClear;\n\tu8 allowMaintenance;\n\tu8 physicalPresenceLifetimeLock;\n\tu8 physicalPresenceHWEnable;\n\tu8 physicalPresenceCMDEnable;\n\tu8 CEKPUsed;\n\tu8 TPMpost;\n\tu8 TPMpostLock;\n\tu8 FIPS;\n\tu8 operator;\n\tu8 enableRevokeEK;\n\tu8 nvLocked;\n\tu8 readSRKPub;\n\tu8 tpmEstablished;\n\tu8 maintenanceDone;\n\tu8 disableFullDALogicInfo;\n};\n\nstruct stclear_flags_t {\n\t__be16 tag;\n\tu8 deactivated;\n\tu8 disableForceClear;\n\tu8 physicalPresence;\n\tu8 physicalPresenceLock;\n\tu8 bGlobalLock;\n} __attribute__((packed));\n\nstruct tpm1_version {\n\tu8 major;\n\tu8 minor;\n\tu8 rev_major;\n\tu8 rev_minor;\n};\n\nstruct tpm1_version2 {\n\t__be16 tag;\n\tstruct tpm1_version version;\n};\n\nstruct timeout_t {\n\t__be32 a;\n\t__be32 b;\n\t__be32 c;\n\t__be32 d;\n};\n\nstruct duration_t {\n\t__be32 tpm_short;\n\t__be32 tpm_medium;\n\t__be32 tpm_long;\n};\n\ntypedef union {\n\tstruct permanent_flags_t perm_flags;\n\tstruct stclear_flags_t stclear_flags;\n\t__u8 owned;\n\t__be32 num_pcrs;\n\tstruct tpm1_version version1;\n\tstruct tpm1_version2 version2;\n\t__be32 manufacturer_id;\n\tstruct timeout_t timeout;\n\tstruct duration_t duration;\n} cap_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\traw_spinlock_t *lock2;\n} class_double_raw_spinlock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\nstruct gpio_generic_chip;\n\ntypedef struct {\n\tstruct gpio_generic_chip *lock;\n\tlong unsigned int flags;\n} class_gpio_generic_lock_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\nstruct user_fpsimd_state;\n\ntypedef struct {\n\tstruct user_fpsimd_state *lock;\n} class_ksimd_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_init_t;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\nstruct perf_cpu_context;\n\nstruct perf_event_context;\n\ntypedef struct {\n\tstruct perf_cpu_context *cpuctx;\n\tstruct perf_event_context *ctx;\n} class_perf_ctx_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_notrace_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\nstruct srcu_ctr;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tstruct srcu_ctr *scp;\n} class_srcu_fast_notrace_t;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\nstruct uart_port;\n\ntypedef struct {\n\tstruct uart_port *lock;\n\tlong unsigned int flags;\n} class_uart_port_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_write_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef __kernel_fsid_t compat_fsid_t;\n\ntypedef struct {\n\tcompat_sigset_word sig[2];\n} compat_sigset_t;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\ntypedef struct {\n\tu64 length;\n\tu64 data;\n} efi_capsule_block_desc_t;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 headersize;\n\tu32 flags;\n\tu32 imagesize;\n} efi_capsule_header_t;\n\ntypedef struct {\n\tu8 major;\n\tu8 minor;\n} efi_cc_version_t;\n\ntypedef struct {\n\tu8 type;\n\tu8 sub_type;\n} efi_cc_type_t;\n\ntypedef struct {\n\tu8 size;\n\tefi_cc_version_t structure_version;\n\tefi_cc_version_t protocol_version;\n\tefi_cc_event_algorithm_bitmap_t hash_algorithm_bitmap;\n\tefi_cc_event_log_bitmap_t supported_event_logs;\n\tefi_cc_type_t cc_type;\n} efi_cc_boot_service_cap_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 table;\n} efi_config_table_32_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu64 table;\n} efi_config_table_64_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_guid_t guid;\n\t\tvoid *table;\n\t};\n\tefi_config_table_32_t mixed_mode;\n} efi_config_table_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tlong unsigned int *ptr;\n\tconst char name[16];\n} efi_config_table_type_t;\n\ntypedef struct {\n\tu16 year;\n\tu8 month;\n\tu8 day;\n\tu8 hour;\n\tu8 minute;\n\tu8 second;\n\tu8 pad1;\n\tu32 nanosecond;\n\ts16 timezone;\n\tu8 daylight;\n\tu8 pad2;\n} efi_time_t;\n\ntypedef struct {\n\tu64 size;\n\tu64 file_size;\n\tu64 phys_size;\n\tefi_time_t create_time;\n\tefi_time_t last_access_time;\n\tefi_time_t modification_time;\n\t__u64 attribute;\n\tefi_char16_t filename[0];\n} efi_file_info_t;\n\ntypedef struct {\n\tu32 red_mask;\n\tu32 green_mask;\n\tu32 blue_mask;\n\tu32 reserved_mask;\n} efi_pixel_bitmask_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 horizontal_resolution;\n\tu32 vertical_resolution;\n\tint pixel_format;\n\tefi_pixel_bitmask_t pixel_information;\n\tu32 pixels_per_scan_line;\n} efi_graphics_output_mode_info_t;\n\ntypedef struct {\n\tu16 scan_code;\n\tefi_char16_t unicode_char;\n} efi_input_key_t;\n\ntypedef struct {\n\tu32 attributes;\n\tu16 file_path_list_length;\n\tu8 variable_data[0];\n} __attribute__((packed)) efi_load_option_t;\n\nstruct efi_generic_dev_path;\n\ntypedef struct efi_generic_dev_path efi_device_path_protocol_t;\n\ntypedef struct {\n\tu32 attributes;\n\tu16 file_path_list_length;\n\tconst efi_char16_t *description;\n\tconst efi_device_path_protocol_t *file_path_list;\n\tu32 optional_data_size;\n\tconst void *optional_data;\n} efi_load_option_unpacked_t;\n\ntypedef void *efi_handle_t;\n\ntypedef struct {\n\tu64 signature;\n\tu32 revision;\n\tu32 headersize;\n\tu32 crc32;\n\tu32 reserved;\n} efi_table_hdr_t;\n\ntypedef struct {\n\tu32 resolution;\n\tu32 accuracy;\n\tu8 sets_to_zero;\n} efi_time_cap_t;\n\ntypedef efi_status_t efi_get_time_t(efi_time_t *, efi_time_cap_t *);\n\ntypedef efi_status_t efi_set_time_t(efi_time_t *);\n\ntypedef efi_status_t efi_get_wakeup_time_t(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\ntypedef efi_status_t efi_set_wakeup_time_t(efi_bool_t, efi_time_t *);\n\ntypedef struct {\n\tu32 type;\n\tu32 pad;\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu64 num_pages;\n\tu64 attribute;\n} efi_memory_desc_t;\n\ntypedef efi_status_t efi_set_virtual_address_map_t(long unsigned int, long unsigned int, u32, efi_memory_desc_t *);\n\ntypedef efi_status_t efi_get_variable_t(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\ntypedef efi_status_t efi_get_next_variable_t(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\ntypedef efi_status_t efi_set_variable_t(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\ntypedef efi_status_t efi_get_next_high_mono_count_t(u32 *);\n\ntypedef void efi_reset_system_t(int, efi_status_t, long unsigned int, efi_char16_t *);\n\ntypedef efi_status_t efi_update_capsule_t(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\ntypedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\ntypedef efi_status_t efi_query_variable_info_t(u32, u64 *, u64 *, u64 *);\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 get_time;\n\tu32 set_time;\n\tu32 get_wakeup_time;\n\tu32 set_wakeup_time;\n\tu32 set_virtual_address_map;\n\tu32 convert_pointer;\n\tu32 get_variable;\n\tu32 get_next_variable;\n\tu32 set_variable;\n\tu32 get_next_high_mono_count;\n\tu32 reset_system;\n\tu32 update_capsule;\n\tu32 query_capsule_caps;\n\tu32 query_variable_info;\n} efi_runtime_services_32_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tefi_get_time_t *get_time;\n\t\tefi_set_time_t *set_time;\n\t\tefi_get_wakeup_time_t *get_wakeup_time;\n\t\tefi_set_wakeup_time_t *set_wakeup_time;\n\t\tefi_set_virtual_address_map_t *set_virtual_address_map;\n\t\tvoid *convert_pointer;\n\t\tefi_get_variable_t *get_variable;\n\t\tefi_get_next_variable_t *get_next_variable;\n\t\tefi_set_variable_t *set_variable;\n\t\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\t\tefi_reset_system_t *reset_system;\n\t\tefi_update_capsule_t *update_capsule;\n\t\tefi_query_capsule_caps_t *query_capsule_caps;\n\t\tefi_query_variable_info_t *query_variable_info;\n\t};\n\tefi_runtime_services_32_t mixed_mode;\n} efi_runtime_services_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 fw_vendor;\n\tu32 fw_revision;\n\tu32 con_in_handle;\n\tu32 con_in;\n\tu32 con_out_handle;\n\tu32 con_out;\n\tu32 stderr_handle;\n\tu32 stderr;\n\tu32 runtime;\n\tu32 boottime;\n\tu32 nr_tables;\n\tu32 tables;\n} efi_system_table_32_t;\n\nunion efi_simple_text_input_protocol;\n\ntypedef union efi_simple_text_input_protocol efi_simple_text_input_protocol_t;\n\nunion efi_simple_text_output_protocol;\n\ntypedef union efi_simple_text_output_protocol efi_simple_text_output_protocol_t;\n\nunion efi_boot_services;\n\ntypedef union efi_boot_services efi_boot_services_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tlong unsigned int fw_vendor;\n\t\tu32 fw_revision;\n\t\tlong unsigned int con_in_handle;\n\t\tefi_simple_text_input_protocol_t *con_in;\n\t\tlong unsigned int con_out_handle;\n\t\tefi_simple_text_output_protocol_t *con_out;\n\t\tlong unsigned int stderr_handle;\n\t\tlong unsigned int stderr;\n\t\tefi_runtime_services_t *runtime;\n\t\tefi_boot_services_t *boottime;\n\t\tlong unsigned int nr_tables;\n\t\tlong unsigned int tables;\n\t};\n\tefi_system_table_32_t mixed_mode;\n} efi_system_table_t;\n\ntypedef union {\n\tstruct {\n\t\tu32 revision;\n\t\tefi_handle_t parent_handle;\n\t\tefi_system_table_t *system_table;\n\t\tefi_handle_t device_handle;\n\t\tvoid *file_path;\n\t\tvoid *reserved;\n\t\tu32 load_options_size;\n\t\tvoid *load_options;\n\t\tvoid *image_base;\n\t\t__u64 image_size;\n\t\tunsigned int image_code_type;\n\t\tunsigned int image_data_type;\n\t\tefi_status_t (*unload)(efi_handle_t);\n\t};\n\tstruct {\n\t\tu32 revision;\n\t\tu32 parent_handle;\n\t\tu32 system_table;\n\t\tu32 device_handle;\n\t\tu32 file_path;\n\t\tu32 reserved;\n\t\tu32 load_options_size;\n\t\tu32 load_options;\n\t\tu32 image_base;\n\t\t__u64 image_size;\n\t\tu32 image_code_type;\n\t\tu32 image_data_type;\n\t\tu32 unload;\n\t} mixed_mode;\n} efi_loaded_image_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 num_entries;\n\tu32 desc_size;\n\tu32 flags;\n\tefi_memory_desc_t entry[0];\n} efi_memory_attributes_table_t;\n\ntypedef struct {\n\tu32 read;\n\tu32 write;\n} efi_pci_io_protocol_access_32_t;\n\ntypedef struct {\n\tvoid *read;\n\tvoid *write;\n} efi_pci_io_protocol_access_t;\n\nunion efi_pci_io_protocol;\n\ntypedef union efi_pci_io_protocol efi_pci_io_protocol_t;\n\ntypedef efi_status_t (*efi_pci_io_protocol_cfg_t)(efi_pci_io_protocol_t *, EFI_PCI_IO_PROTOCOL_WIDTH, u32, long unsigned int, void *);\n\ntypedef struct {\n\tefi_pci_io_protocol_cfg_t read;\n\tefi_pci_io_protocol_cfg_t write;\n} efi_pci_io_protocol_config_access_t;\n\ntypedef struct {\n\tu16 version;\n\tu16 length;\n\tu32 runtime_services_supported;\n} efi_rt_properties_table_t;\n\ntypedef struct {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n} ext4_acl_entry;\n\ntypedef struct {\n\t__le32 a_version;\n} ext4_acl_header;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic64_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tunsigned int __softirq_pending;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n} irq_cpustat_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\t__le64 b;\n\t__le64 a;\n} le128;\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef struct {\n\tlocal_t a;\n} local64_t;\n\ntypedef union {\n\tlong unsigned int x[1];\n} map_word;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\ntypedef struct {\n\tatomic64_t id;\n\tvoid *sigpage;\n\trefcount_t pinned;\n\tvoid *vdso;\n\tlong unsigned int flags;\n\tu8 pkey_allocation_map;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[1];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tchar data[8];\n} nfs4_verifier;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\ntypedef struct {\n\tp4dval_t p4d;\n} p4d_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\ntypedef struct {\n\tpgdval_t pgd;\n} pgd_t;\n\ntypedef struct {\n\tptdesc_t pgprot;\n} pgprot_t;\n\ntypedef struct {\n\tpmdval_t pmd;\n} pmd_t;\n\ntypedef struct {\n\tlong unsigned int bits[4];\n} pnp_irq_mask_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tpteval_t pte;\n} pte_t;\n\ntypedef struct {\n\tpudval_t pud;\n} pud_t;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[1];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\nstruct qspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tstruct {\n\t\t\tu8 locked;\n\t\t\tu8 pending;\n\t\t};\n\t\tstruct {\n\t\t\tu16 locked_pending;\n\t\t\tu16 tail;\n\t\t};\n\t};\n};\n\ntypedef struct qspinlock arch_spinlock_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\tlocal64_t v;\n} u64_stats_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\nstruct IOV_111 {\n\tu8 maxVFsSupported;\n\tu8 numVFsEnabled;\n\tu8 requestorId;\n\tu8 reserved[5];\n};\n\nstruct IO_REQUEST_INFO {\n\tu64 ldStartBlock;\n\tu32 numBlocks;\n\tu16 ldTgtId;\n\tu8 isRead;\n\t__le16 devHandle;\n\tu8 pd_interface;\n\tu64 pdBlock;\n\tu8 fpOkForIo;\n\tu8 IoforUnevenSpan;\n\tu8 start_span;\n\tu8 do_fp_rlbypass;\n\tu64 start_row;\n\tu8 span_arm;\n\tu8 pd_after_lb;\n\tu16 r1_alt_dev_handle;\n\tbool ra_capable;\n\tu8 data_arms;\n};\n\nstruct LD_LOAD_BALANCE_INFO {\n\tu8 loadBalanceFlag;\n\tu8 reserved1;\n\tatomic_t scsi_pending_cmds[256];\n\tu64 last_accessed_block[256];\n};\n\nstruct megasas_cmd_fusion;\n\nstruct STREAM_DETECT {\n\tu64 next_seq_lba;\n\tstruct megasas_cmd_fusion *first_cmd_fusion;\n\tstruct megasas_cmd_fusion *last_cmd_fusion;\n\tu32 count_cmds_in_stream;\n\tu16 num_sges_in_group;\n\tu8 is_read;\n\tu8 group_depth;\n\tbool group_flush;\n\tu8 reserved[7];\n};\n\nstruct LD_STREAM_DETECT {\n\tbool write_back;\n\tbool fp_write_enabled;\n\tbool members_ssds;\n\tbool fp_cache_bypass_capable;\n\tu32 mru_bit_map;\n\tstruct STREAM_DETECT stream_track[8];\n};\n\nstruct _LD_SPAN_SET {\n\tu64 log_start_lba;\n\tu64 log_end_lba;\n\tu64 span_row_start;\n\tu64 span_row_end;\n\tu64 data_strip_start;\n\tu64 data_strip_end;\n\tu64 data_row_start;\n\tu64 data_row_end;\n\tu8 strip_offset[8];\n\tu32 span_row_data_width;\n\tu32 diff;\n\tu32 reserved[2];\n};\n\ntypedef struct _LD_SPAN_SET LD_SPAN_SET;\n\nstruct LOG_BLOCK_SPAN_INFO {\n\tLD_SPAN_SET span_set[8];\n};\n\ntypedef struct LOG_BLOCK_SPAN_INFO LD_SPAN_INFO;\n\ntypedef struct LOG_BLOCK_SPAN_INFO *PLD_SPAN_INFO;\n\nstruct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {\n\tu32 RequestFlags: 8;\n\tu32 MessageAddress1: 24;\n\tu32 MessageAddress2;\n};\n\nstruct MPI2_DEFAULT_REQUEST_DESCRIPTOR {\n\tu8 RequestFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le16 LMID;\n\t__le16 DescriptorTypeDependent;\n};\n\nstruct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {\n\tu8 RequestFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le16 LMID;\n\t__le16 Reserved1;\n};\n\nstruct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {\n\tu8 RequestFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le16 LMID;\n\t__le16 DevHandle;\n};\n\nstruct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {\n\tu8 RequestFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le16 LMID;\n\t__le16 IoIndex;\n};\n\nstruct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {\n\tu8 RequestFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le16 LMID;\n\t__le16 Reserved;\n};\n\nunion MEGASAS_REQUEST_DESCRIPTOR_UNION {\n\tstruct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;\n\tstruct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;\n\tstruct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;\n\tstruct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;\n\tstruct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;\n\tstruct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 low;\n\t\t\t__le32 high;\n\t\t} u;\n\t\t__le64 Words;\n\t};\n};\n\nstruct MPI25_IEEE_SGE_CHAIN64 {\n\t__le64 Address;\n\t__le32 Length;\n\t__le16 Reserved1;\n\tu8 NextChainOffset;\n\tu8 Flags;\n};\n\nstruct MPI2_ADDRESS_REPLY_DESCRIPTOR {\n\tu8 ReplyFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le32 ReplyFrameAddress;\n};\n\nstruct MPI2_DEFAULT_REPLY_DESCRIPTOR {\n\tu8 ReplyFlags;\n\tu8 MSIxIndex;\n\t__le16 DescriptorTypeDependent1;\n\t__le32 DescriptorTypeDependent2;\n};\n\nstruct MPI2_IEEE_SGE_CHAIN32 {\n\t__le32 Address;\n\t__le32 FlagsLength;\n};\n\nstruct MPI2_IEEE_SGE_CHAIN64 {\n\t__le64 Address;\n\t__le32 Length;\n\t__le16 Reserved1;\n\tu8 Reserved2;\n\tu8 Flags;\n};\n\nunion MPI2_IEEE_SGE_CHAIN_UNION {\n\tstruct MPI2_IEEE_SGE_CHAIN32 Chain32;\n\tstruct MPI2_IEEE_SGE_CHAIN64 Chain64;\n};\n\nstruct MPI2_IEEE_SGE_SIMPLE32 {\n\t__le32 Address;\n\t__le32 FlagsLength;\n};\n\nstruct MPI2_IEEE_SGE_SIMPLE64 {\n\t__le64 Address;\n\t__le32 Length;\n\t__le16 Reserved1;\n\tu8 Reserved2;\n\tu8 Flags;\n};\n\nunion MPI2_IEEE_SGE_SIMPLE_UNION {\n\tstruct MPI2_IEEE_SGE_SIMPLE32 Simple32;\n\tstruct MPI2_IEEE_SGE_SIMPLE64 Simple64;\n};\n\nstruct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {\n\tu64 RDPQBaseAddress;\n\tu32 Reserved1;\n\tu32 Reserved2;\n};\n\nstruct MPI2_IOC_INIT_REQUEST {\n\tu8 WhoInit;\n\tu8 Reserved1;\n\tu8 ChainOffset;\n\tu8 Function;\n\t__le16 Reserved2;\n\tu8 Reserved3;\n\tu8 MsgFlags;\n\tu8 VP_ID;\n\tu8 VF_ID;\n\t__le16 Reserved4;\n\t__le16 MsgVersion;\n\t__le16 HeaderVersion;\n\tu32 Reserved5;\n\t__le16 Reserved6;\n\tu8 HostPageSize;\n\tu8 HostMSIxVectors;\n\t__le16 Reserved8;\n\t__le16 SystemRequestFrameSize;\n\t__le16 ReplyDescriptorPostQueueDepth;\n\t__le16 ReplyFreeQueueDepth;\n\t__le32 SenseBufferAddressHigh;\n\t__le32 SystemReplyAddressHigh;\n\t__le64 SystemRequestFrameBaseAddress;\n\t__le64 ReplyDescriptorPostQueueAddress;\n\t__le64 ReplyFreeQueueAddress;\n\t__le64 TimeStamp;\n};\n\nstruct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {\n\tu8 ReplyFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le32 Reserved;\n};\n\nstruct MPI2_SCSI_IO_CDB_EEDP32 {\n\tu8 CDB[20];\n\t__be32 PrimaryReferenceTag;\n\t__be16 PrimaryApplicationTag;\n\t__be16 PrimaryApplicationTagMask;\n\t__le32 TransferLength;\n};\n\nstruct MPI2_SGE_SIMPLE_UNION {\n\t__le32 FlagsLength;\n\tunion {\n\t\t__le32 Address32;\n\t\t__le64 Address64;\n\t} u;\n};\n\nunion MPI2_SCSI_IO_CDB_UNION {\n\tu8 CDB32[32];\n\tstruct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;\n\tstruct MPI2_SGE_SIMPLE_UNION SGE;\n};\n\nstruct RAID_CONTEXT {\n\tu8 type: 4;\n\tu8 nseg: 4;\n\tu8 resvd0;\n\t__le16 timeout_value;\n\tu8 reg_lock_flags;\n\tu8 resvd1;\n\t__le16 virtual_disk_tgt_id;\n\t__le64 reg_lock_row_lba;\n\t__le32 reg_lock_length;\n\t__le16 next_lmid;\n\tu8 ex_status;\n\tu8 status;\n\tu8 raid_flags;\n\tu8 num_sge;\n\t__le16 config_seq_num;\n\tu8 span_arm;\n\tu8 priority;\n\tu8 num_sge_ext;\n\tu8 resvd2;\n};\n\nstruct RAID_CONTEXT_G35 {\n\tu16 nseg_type;\n\tu16 timeout_value;\n\tu16 routing_flags;\n\tu16 virtual_disk_tgt_id;\n\t__le64 reg_lock_row_lba;\n\tu32 reg_lock_length;\n\tunion {\n\t\tu16 rmw_op_index;\n\t\tu16 peer_smid;\n\t\tu16 r56_arm_map;\n\t} flow_specific;\n\tu8 ex_status;\n\tu8 status;\n\tu8 raid_flags;\n\tu8 span_arm;\n\tu16 config_seq_num;\n\tunion {\n\t\tstruct {\n\t\t\tu16 num_sge: 12;\n\t\t\tu16 reserved: 3;\n\t\t\tu16 stream_detected: 1;\n\t\t} bits;\n\t\tu8 bytes[2];\n\t} u;\n\tu8 resvd2[2];\n};\n\nunion RAID_CONTEXT_UNION {\n\tstruct RAID_CONTEXT raid_context;\n\tstruct RAID_CONTEXT_G35 raid_context_g35;\n};\n\nstruct MPI2_SGE_CHAIN_UNION {\n\t__le16 Length;\n\tu8 NextChainOffset;\n\tu8 Flags;\n\tunion {\n\t\t__le32 Address32;\n\t\t__le64 Address64;\n\t} u;\n};\n\nunion MPI2_SGE_IO_UNION {\n\tstruct MPI2_SGE_SIMPLE_UNION MpiSimple;\n\tstruct MPI2_SGE_CHAIN_UNION MpiChain;\n\tunion MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;\n\tunion MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;\n};\n\nstruct MPI2_RAID_SCSI_IO_REQUEST {\n\t__le16 DevHandle;\n\tu8 ChainOffset;\n\tu8 Function;\n\t__le16 Reserved1;\n\tu8 Reserved2;\n\tu8 MsgFlags;\n\tu8 VP_ID;\n\tu8 VF_ID;\n\t__le16 Reserved3;\n\t__le32 SenseBufferLowAddress;\n\t__le16 SGLFlags;\n\tu8 SenseBufferLength;\n\tu8 Reserved4;\n\tu8 SGLOffset0;\n\tu8 SGLOffset1;\n\tu8 SGLOffset2;\n\tu8 SGLOffset3;\n\t__le32 SkipCount;\n\t__le32 DataLength;\n\t__le32 BidirectionalDataLength;\n\t__le16 IoFlags;\n\t__le16 EEDPFlags;\n\t__le32 EEDPBlockSize;\n\t__le32 SecondaryReferenceTag;\n\t__le16 SecondaryApplicationTag;\n\t__le16 ApplicationTagTranslationMask;\n\tu8 LUN[8];\n\t__le32 Control;\n\tunion MPI2_SCSI_IO_CDB_UNION CDB;\n\tunion RAID_CONTEXT_UNION RaidContext;\n\tunion {\n\t\tunion MPI2_SGE_IO_UNION SGL;\n\t\tstruct {\n\t\t\tstruct {} __empty_SGLs;\n\t\t\tunion MPI2_SGE_IO_UNION SGLs[0];\n\t\t};\n\t};\n};\n\nstruct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {\n\tu8 ReplyFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\t__le16 TaskTag;\n\t__le16 Reserved1;\n};\n\nstruct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {\n\tu8 ReplyFlags;\n\tu8 MSIxIndex;\n\t__le16 SMID;\n\tu8 SequenceNumber;\n\tu8 Reserved1;\n\t__le16 IoIndex;\n};\n\nstruct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {\n\tu8 ReplyFlags;\n\tu8 MSIxIndex;\n\tu8 VP_ID;\n\tu8 Flags;\n\t__le16 InitiatorDevHandle;\n\t__le16 IoIndex;\n};\n\nunion MPI2_REPLY_DESCRIPTORS_UNION {\n\tstruct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;\n\tstruct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;\n\tstruct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;\n\tstruct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;\n\tstruct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;\n\tstruct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;\n\t__le64 Words;\n};\n\nstruct MPI2_SCSI_TASK_MANAGE_REPLY {\n\tu16 DevHandle;\n\tu8 MsgLength;\n\tu8 Function;\n\tu8 ResponseCode;\n\tu8 TaskType;\n\tu8 Reserved1;\n\tu8 MsgFlags;\n\tu8 VP_ID;\n\tu8 VF_ID;\n\tu16 Reserved2;\n\tu16 Reserved3;\n\tu16 IOCStatus;\n\tu32 IOCLogInfo;\n\tu32 TerminationCount;\n\tu32 ResponseInfo;\n};\n\nstruct MPI2_SCSI_TASK_MANAGE_REQUEST {\n\tu16 DevHandle;\n\tu8 ChainOffset;\n\tu8 Function;\n\tu8 Reserved1;\n\tu8 TaskType;\n\tu8 Reserved2;\n\tu8 MsgFlags;\n\tu8 VP_ID;\n\tu8 VF_ID;\n\tu16 Reserved3;\n\tu8 LUN[8];\n\tu32 Reserved4[7];\n\tu16 TaskMID;\n\tu16 Reserved5;\n};\n\nstruct MR_ARRAY_INFO {\n\t__le16 pd[32];\n};\n\nstruct MR_CPU_AFFINITY_MASK {\n\tunion {\n\t\tstruct {\n\t\t\tu8 hw_path: 1;\n\t\t\tu8 cpu0: 1;\n\t\t\tu8 cpu1: 1;\n\t\t\tu8 cpu2: 1;\n\t\t\tu8 cpu3: 1;\n\t\t\tu8 reserved: 3;\n\t\t};\n\t\tu8 core_mask;\n\t};\n};\n\nstruct MR_CTRL_HB_HOST_MEM {\n\tstruct {\n\t\tu32 fwCounter;\n\t\tstruct {\n\t\t\tu32 debugmode: 1;\n\t\t\tu32 reserved: 31;\n\t\t} debug;\n\t\tu32 reserved_fw[6];\n\t\tu32 driverCounter;\n\t\tu32 reserved_driver[7];\n\t} HB;\n\tu8 pad[960];\n};\n\nstruct MR_DEV_HANDLE_INFO {\n\t__le16 curDevHdl;\n\tu8 validHandles;\n\tu8 interfaceType;\n\t__le16 devHandle[2];\n};\n\nstruct MR_IO_AFFINITY {\n\tunion {\n\t\tstruct {\n\t\t\tstruct MR_CPU_AFFINITY_MASK pdRead;\n\t\t\tstruct MR_CPU_AFFINITY_MASK pdWrite;\n\t\t\tstruct MR_CPU_AFFINITY_MASK ldRead;\n\t\t\tstruct MR_CPU_AFFINITY_MASK ldWrite;\n\t\t};\n\t\tu32 word;\n\t};\n\tu8 maxCores;\n\tu8 reserved[3];\n};\n\nstruct MR_LD_RAID {\n\tstruct {\n\t\tu32 fpCapable: 1;\n\t\tu32 ra_capable: 1;\n\t\tu32 reserved5: 2;\n\t\tu32 ldPiMode: 4;\n\t\tu32 pdPiMode: 4;\n\t\tu32 encryptionType: 8;\n\t\tu32 fpWriteCapable: 1;\n\t\tu32 fpReadCapable: 1;\n\t\tu32 fpWriteAcrossStripe: 1;\n\t\tu32 fpReadAcrossStripe: 1;\n\t\tu32 fpNonRWCapable: 1;\n\t\tu32 tmCapable: 1;\n\t\tu32 fpBypassRegionLock: 1;\n\t\tu32 disable_coalescing: 1;\n\t\tu32 fp_rmw_capable: 1;\n\t\tu32 fp_cache_bypass_capable: 1;\n\t\tu32 reserved4: 2;\n\t} capability;\n\t__le32 reserved6;\n\t__le64 size;\n\tu8 spanDepth;\n\tu8 level;\n\tu8 stripeShift;\n\tu8 rowSize;\n\tu8 rowDataSize;\n\tu8 writeMode;\n\tu8 PRL;\n\tu8 SRL;\n\t__le16 targetId;\n\tu8 ldState;\n\tu8 regTypeReqOnWrite;\n\tu8 modFactor;\n\tu8 regTypeReqOnRead;\n\t__le16 seqNum;\n\tstruct {\n\t\tu32 ldSyncRequired: 1;\n\t\tu32 regTypeReqOnReadIsValid: 1;\n\t\tu32 isEPD: 1;\n\t\tu32 enableSLDOnAllRWIOs: 1;\n\t\tu32 reserved: 28;\n\t} flags;\n\tu8 LUN[8];\n\tu8 fpIoTimeoutForLd;\n\tu8 ld_accept_priority_type;\n\tu8 reserved2[2];\n\tu32 logical_block_length;\n\tstruct {\n\t\tu32 ld_pi_exp: 4;\n\t\tu32 ld_logical_block_exp: 4;\n\t\tu32 reserved1: 24;\n\t};\n\tstruct MR_IO_AFFINITY cpuAffinity;\n\tu8 reserved3[64];\n};\n\nstruct MR_LD_SPAN {\n\t__le64 startBlk;\n\t__le64 numBlks;\n\t__le16 arrayRef;\n\tu8 spanRowSize;\n\tu8 spanRowDataSize;\n\tu8 reserved[4];\n};\n\nstruct MR_QUAD_ELEMENT {\n\t__le64 logStart;\n\t__le64 logEnd;\n\t__le64 offsetInSpan;\n\t__le32 diff;\n\t__le32 reserved1;\n};\n\nstruct MR_SPAN_INFO {\n\t__le32 noElements;\n\t__le32 reserved1;\n\tstruct MR_QUAD_ELEMENT quad[8];\n};\n\nstruct MR_SPAN_BLOCK_INFO {\n\t__le64 num_rows;\n\tstruct MR_LD_SPAN span;\n\tstruct MR_SPAN_INFO block_span_info;\n};\n\nstruct MR_LD_SPAN_MAP {\n\tstruct MR_LD_RAID ldRaid;\n\tu8 dataArmMap[32];\n\tstruct MR_SPAN_BLOCK_INFO spanBlock[8];\n};\n\nstruct MR_DRV_RAID_MAP {\n\t__le32 totalSize;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 maxLd;\n\t\t\t__le32 maxSpanDepth;\n\t\t\t__le32 maxRowSize;\n\t\t\t__le32 maxPdCount;\n\t\t\t__le32 maxArrays;\n\t\t} validationInfo;\n\t\t__le32 version[5];\n\t};\n\tu8 fpPdIoTimeoutSec;\n\tu8 reserved2[7];\n\t__le16 ldCount;\n\t__le16 arCount;\n\t__le16 spanCount;\n\t__le16 reserve3;\n\tstruct MR_DEV_HANDLE_INFO devHndlInfo[512];\n\tu16 ldTgtIdToLd[512];\n\tstruct MR_ARRAY_INFO arMapInfo[512];\n\tstruct MR_LD_SPAN_MAP ldSpanMap[0];\n};\n\nstruct MR_DRV_RAID_MAP_ALL {\n\tunion {\n\t\tstruct MR_DRV_RAID_MAP raidMap;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[37928];\n\t\t\tstruct MR_LD_SPAN_MAP ldSpanMap[512];\n\t\t};\n\t};\n};\n\nstruct MR_DRV_SYSTEM_INFO {\n\tu8 infoVersion;\n\tu8 systemIdLength;\n\tu16 reserved0;\n\tu8 systemId[64];\n\tu8 reserved[1980];\n};\n\nstruct MR_FW_RAID_MAP {\n\t__le32 totalSize;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 maxLd;\n\t\t\t__le32 maxSpanDepth;\n\t\t\t__le32 maxRowSize;\n\t\t\t__le32 maxPdCount;\n\t\t\t__le32 maxArrays;\n\t\t} validationInfo;\n\t\t__le32 version[5];\n\t};\n\t__le32 ldCount;\n\t__le32 Reserved1;\n\tu8 ldTgtIdToLd[128];\n\tu8 fpPdIoTimeoutSec;\n\tu8 reserved2[7];\n\tstruct MR_ARRAY_INFO arMapInfo[128];\n\tstruct MR_DEV_HANDLE_INFO devHndlInfo[256];\n\tstruct MR_LD_SPAN_MAP ldSpanMap[0];\n};\n\nstruct MR_FW_RAID_MAP_ALL {\n\tunion {\n\t\tstruct MR_FW_RAID_MAP raidMap;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[10408];\n\t\t\tstruct MR_LD_SPAN_MAP ldSpanMap[64];\n\t\t};\n\t};\n};\n\nstruct MR_RAID_MAP_DESC_TABLE {\n\tu32 raid_map_desc_type;\n\tu32 raid_map_desc_offset;\n\tu32 raid_map_desc_buffer_size;\n\tu32 raid_map_desc_elements;\n};\n\nstruct MR_FW_RAID_MAP_DYNAMIC {\n\tu32 raid_map_size;\n\tu32 desc_table_offset;\n\tu32 desc_table_size;\n\tu32 desc_table_num_elements;\n\tu64 reserved1;\n\tu32 reserved2[3];\n\tu8 fp_pd_io_timeout_sec;\n\tu8 reserved3[3];\n\tu32 rmw_fp_seq_num;\n\tu16 ld_count;\n\tu16 ar_count;\n\tu16 span_count;\n\tu16 reserved4[3];\n\tunion {\n\t\tstruct {\n\t\t\tstruct MR_DEV_HANDLE_INFO *dev_hndl_info;\n\t\t\tu16 *ld_tgt_id_to_ld;\n\t\t\tstruct MR_ARRAY_INFO *ar_map_info;\n\t\t\tstruct MR_LD_SPAN_MAP *ld_span_map;\n\t\t};\n\t\tu64 ptr_structure_size[4];\n\t};\n\tstruct MR_RAID_MAP_DESC_TABLE raid_map_desc_table[4];\n\tu32 raid_map_desc_data[0];\n};\n\nstruct MR_FW_RAID_MAP_EXT {\n\tu32 reserved;\n\tunion {\n\t\tstruct {\n\t\t\tu32 maxLd;\n\t\t\tu32 maxSpanDepth;\n\t\t\tu32 maxRowSize;\n\t\t\tu32 maxPdCount;\n\t\t\tu32 maxArrays;\n\t\t} validationInfo;\n\t\tu32 version[5];\n\t};\n\tu8 fpPdIoTimeoutSec;\n\tu8 reserved2[7];\n\t__le16 ldCount;\n\t__le16 arCount;\n\t__le16 spanCount;\n\t__le16 reserve3;\n\tstruct MR_DEV_HANDLE_INFO devHndlInfo[256];\n\tu8 ldTgtIdToLd[256];\n\tstruct MR_ARRAY_INFO arMapInfo[256];\n\tstruct MR_LD_SPAN_MAP ldSpanMap[256];\n};\n\nstruct MR_HOST_DEVICE_LIST_ENTRY {\n\tstruct {\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tu8 is_sys_pd: 1;\n\t\t\t\tu8 reserved: 7;\n\t\t\t} bits;\n\t\t\tu8 byte;\n\t\t} u;\n\t} flags;\n\tu8 scsi_type;\n\t__le16 target_id;\n\tu8 reserved[4];\n\t__le64 sas_addr[2];\n};\n\nstruct MR_HOST_DEVICE_LIST {\n\t__le32 size;\n\t__le32 count;\n\t__le32 reserved[2];\n\tstruct MR_HOST_DEVICE_LIST_ENTRY host_device_list[0];\n};\n\nunion MR_LD_REF {\n\tstruct {\n\t\tu8 targetId;\n\t\tu8 reserved;\n\t\t__le16 seqNum;\n\t};\n\t__le32 ref;\n};\n\nstruct MR_LD_LIST {\n\t__le32 ldCount;\n\t__le32 reserved;\n\tstruct {\n\t\tunion MR_LD_REF ref;\n\t\tu8 state;\n\t\tu8 reserved[3];\n\t\t__le64 size;\n\t} ldList[256];\n};\n\nstruct MR_LD_TARGETID_LIST {\n\t__le32 size;\n\t__le32 count;\n\tu8 pad[3];\n\tu8 targetId[256];\n};\n\nstruct MR_LD_TARGET_SYNC {\n\tu8 targetId;\n\tu8 reserved;\n\t__le16 seqNum;\n};\n\nstruct MR_LD_VF_MAP {\n\tu32 size;\n\tunion MR_LD_REF ref;\n\tu8 ldVfCount;\n\tu8 reserved[6];\n\tu8 policy[0];\n};\n\nstruct MR_LD_VF_AFFILIATION {\n\tu32 size;\n\tu8 ldCount;\n\tu8 vfCount;\n\tu8 thisVf;\n\tu8 reserved[9];\n\tstruct MR_LD_VF_MAP map[1];\n};\n\nstruct MR_LD_VF_MAP_111 {\n\tu8 targetId;\n\tu8 reserved[3];\n\tu8 policy[8];\n};\n\nstruct MR_LD_VF_AFFILIATION_111 {\n\tu8 vdCount;\n\tu8 vfCount;\n\tu8 thisVf;\n\tu8 reserved[5];\n\tstruct MR_LD_VF_MAP_111 map[64];\n};\n\nstruct MR_PD_ADDRESS {\n\t__le16 deviceId;\n\tu16 enclDeviceId;\n\tunion {\n\t\tstruct {\n\t\t\tu8 enclIndex;\n\t\t\tu8 slotNumber;\n\t\t} mrPdAddress;\n\t\tstruct {\n\t\t\tu8 enclPosition;\n\t\t\tu8 enclConnectorIndex;\n\t\t} mrEnclAddress;\n\t};\n\tu8 scsiDevType;\n\tunion {\n\t\tu8 connectedPortBitmap;\n\t\tu8 connectedPortNumbers;\n\t};\n\tu64 sasAddr[2];\n};\n\nstruct MR_PD_CFG_SEQ {\n\tu16 seqNum;\n\tu16 devHandle;\n\tstruct {\n\t\tu8 tmCapable: 1;\n\t\tu8 reserved: 7;\n\t} capability;\n\tu8 reserved;\n\tu16 pd_target_id;\n};\n\nstruct MR_PD_CFG_SEQ_NUM_SYNC {\n\t__le32 size;\n\t__le32 count;\n\tstruct MR_PD_CFG_SEQ seq[0];\n};\n\nunion MR_PD_DDF_TYPE {\n\tstruct {\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tu16 forcedPDGUID: 1;\n\t\t\t\tu16 inVD: 1;\n\t\t\t\tu16 isGlobalSpare: 1;\n\t\t\t\tu16 isSpare: 1;\n\t\t\t\tu16 isForeign: 1;\n\t\t\t\tu16 reserved: 7;\n\t\t\t\tu16 intf: 4;\n\t\t\t} pdType;\n\t\t\tu16 type;\n\t\t};\n\t\tu16 reserved;\n\t} ddf;\n\tstruct {\n\t\tu32 reserved;\n\t} nonDisk;\n\tu32 type;\n};\n\nunion MR_PD_REF {\n\tstruct {\n\t\tu16 deviceId;\n\t\tu16 seqNum;\n\t} mrPdRef;\n\tu32 ref;\n};\n\nunion MR_PROGRESS {\n\tstruct {\n\t\tu16 progress;\n\t\tunion {\n\t\t\tu16 elapsedSecs;\n\t\t\tu16 elapsedSecsForLastPercent;\n\t\t};\n\t} mrProgress;\n\tu32 w;\n};\n\nstruct MR_PD_PROGRESS {\n\tstruct {\n\t\tu32 rbld: 1;\n\t\tu32 patrol: 1;\n\t\tu32 clear: 1;\n\t\tu32 copyBack: 1;\n\t\tu32 erase: 1;\n\t\tu32 locate: 1;\n\t\tu32 reserved: 26;\n\t} active;\n\tunion MR_PROGRESS rbld;\n\tunion MR_PROGRESS patrol;\n\tunion {\n\t\tunion MR_PROGRESS clear;\n\t\tunion MR_PROGRESS erase;\n\t};\n\tstruct {\n\t\tu32 rbld: 1;\n\t\tu32 patrol: 1;\n\t\tu32 clear: 1;\n\t\tu32 copyBack: 1;\n\t\tu32 erase: 1;\n\t\tu32 reserved: 27;\n\t} pause;\n\tunion MR_PROGRESS reserved[3];\n};\n\nstruct MR_PD_INFO {\n\tunion MR_PD_REF ref;\n\tu8 inquiryData[96];\n\tu8 vpdPage83[64];\n\tu8 notSupported;\n\tu8 scsiDevType;\n\tunion {\n\t\tu8 connectedPortBitmap;\n\t\tu8 connectedPortNumbers;\n\t};\n\tu8 deviceSpeed;\n\tu32 mediaErrCount;\n\tu32 otherErrCount;\n\tu32 predFailCount;\n\tu32 lastPredFailEventSeqNum;\n\tu16 fwState;\n\tu8 disabledForRemoval;\n\tu8 linkSpeed;\n\tunion MR_PD_DDF_TYPE state;\n\tstruct {\n\t\tu8 count;\n\t\tu8 isPathBroken: 4;\n\t\tu8 reserved3: 3;\n\t\tu8 widePortCapable: 1;\n\t\tu8 connectorIndex[2];\n\t\tu8 reserved[4];\n\t\tu64 sasAddr[2];\n\t\tu8 reserved2[16];\n\t} pathInfo;\n\tu64 rawSize;\n\tu64 nonCoercedSize;\n\tu64 coercedSize;\n\tu16 enclDeviceId;\n\tu8 enclIndex;\n\tunion {\n\t\tu8 slotNumber;\n\t\tu8 enclConnectorIndex;\n\t};\n\tstruct MR_PD_PROGRESS progInfo;\n\tu8 badBlockTableFull;\n\tu8 unusableInCurrentConfig;\n\tu8 vpdPage83Ext[64];\n\tu8 powerState;\n\tu8 enclPosition;\n\tu32 allowedOps;\n\tu16 copyBackPartnerId;\n\tu16 enclPartnerDeviceId;\n\tstruct {\n\t\tu16 fdeCapable: 1;\n\t\tu16 fdeEnabled: 1;\n\t\tu16 secured: 1;\n\t\tu16 locked: 1;\n\t\tu16 foreign: 1;\n\t\tu16 needsEKM: 1;\n\t\tu16 reserved: 10;\n\t} security;\n\tu8 mediaType;\n\tu8 notCertified;\n\tu8 bridgeVendor[8];\n\tu8 bridgeProductIdentification[16];\n\tu8 bridgeProductRevisionLevel[4];\n\tu8 satBridgeExists;\n\tu8 interfaceType;\n\tu8 temperature;\n\tu8 emulatedBlockSize;\n\tu16 userDataBlockSize;\n\tu16 reserved2;\n\tstruct {\n\t\tu32 piType: 3;\n\t\tu32 piFormatted: 1;\n\t\tu32 piEligible: 1;\n\t\tu32 NCQ: 1;\n\t\tu32 WCE: 1;\n\t\tu32 commissionedSpare: 1;\n\t\tu32 emergencySpare: 1;\n\t\tu32 ineligibleForSSCD: 1;\n\t\tu32 ineligibleForLd: 1;\n\t\tu32 useSSEraseType: 1;\n\t\tu32 wceUnchanged: 1;\n\t\tu32 supportScsiUnmap: 1;\n\t\tu32 reserved: 18;\n\t} properties;\n\tu64 shieldDiagCompletionTime;\n\tu8 shieldCounter;\n\tu8 linkSpeedOther;\n\tu8 reserved4[2];\n\tstruct {\n\t\tu32 bbmErrCountSupported: 1;\n\t\tu32 bbmErrCount: 31;\n\t} bbmErr;\n\tu8 reserved1[84];\n} __attribute__((packed));\n\nstruct MR_PD_LIST {\n\t__le32 size;\n\t__le32 count;\n\tstruct MR_PD_ADDRESS addr[1];\n};\n\nstruct MR_PRIV_DEVICE {\n\tbool is_tm_capable;\n\tbool tm_busy;\n\tatomic_t sdev_priv_busy;\n\tatomic_t r1_ldio_hint;\n\tu8 interface_type;\n\tu8 task_abort_tmo;\n\tu8 target_reset_tmo;\n};\n\nstruct MR_SNAPDUMP_PROPERTIES {\n\tu8 offload_num;\n\tu8 max_num_supported;\n\tu8 cur_num_supported;\n\tu8 trigger_min_num_sec_before_ocr;\n\tu8 reserved[12];\n};\n\nstruct MR_TARGET_PROPERTIES {\n\tu32 max_io_size_kb;\n\tu32 device_qdepth;\n\tu32 sector_size;\n\tu8 reset_tmo;\n\tu8 reserved[499];\n};\n\nstruct MR_TM_REQUEST {\n\tchar request[128];\n};\n\nstruct MR_TM_REPLY {\n\tchar reply[128];\n};\n\nstruct MR_TASK_MANAGE_REQUEST {\n\tstruct MR_TM_REQUEST TmRequest;\n\tunion {\n\t\tstruct {\n\t\t\tu32 isTMForLD: 1;\n\t\t\tu32 isTMForPD: 1;\n\t\t\tu32 reserved1: 30;\n\t\t\tu32 reserved2;\n\t\t} tmReqFlags;\n\t\tstruct MR_TM_REPLY TMReply;\n\t};\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lock_class_key {};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong int privdata[0];\n};\n\nstruct Qdisc_class_common {\n\tu32 classid;\n\tunsigned int filter_cnt;\n\tstruct hlist_node hnode;\n};\n\nstruct hlist_head;\n\nstruct Qdisc_class_hash {\n\tstruct hlist_head *hash;\n\tunsigned int hashsize;\n\tunsigned int hashmask;\n\tunsigned int hashelems;\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct lockdep_map {};\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool work_in_progress;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tbool smart_suspend: 1;\n\tbool must_resume: 1;\n\tbool may_skip_resume: 1;\n\tbool out_band_wakeup: 1;\n\tbool strict_midlayer: 1;\n\tstruct hrtimer suspend_timer;\n\tu64 timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tbool idle_notification: 1;\n\tbool request_pending: 1;\n\tbool deferred_resume: 1;\n\tbool needs_force_resume: 1;\n\tbool runtime_auto: 1;\n\tbool ignore_children: 1;\n\tbool no_callbacks: 1;\n\tbool irq_safe: 1;\n\tbool use_autosuspend: 1;\n\tbool timer_autosuspends: 1;\n\tbool memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tenum rpm_status last_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct dev_archdata {};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct em_perf_domain;\n\nstruct dev_pin_info;\n\nstruct dma_map_ops;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct dma_coherent_mem;\n\nstruct cma;\n\nstruct io_tlb_mem;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct em_perf_domain *em_pd;\n\tstruct dev_pin_info *pins;\n\tstruct dev_msi_info msi;\n\tconst struct dma_map_ops *dma_ops;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct dma_coherent_mem *dma_mem;\n\tstruct cma *cma_area;\n\tstruct io_tlb_mem *dma_io_tlb_mem;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tint numa_node;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_coherent: 1;\n\tbool dma_skip_sync: 1;\n\tbool dma_iommu: 1;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n};\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nunion _MFI_CAPABILITIES {\n\tstruct {\n\t\tu32 support_fp_remote_lun: 1;\n\t\tu32 support_additional_msix: 1;\n\t\tu32 support_fastpath_wb: 1;\n\t\tu32 support_max_255lds: 1;\n\t\tu32 support_ndrive_r1_lb: 1;\n\t\tu32 support_core_affinity: 1;\n\t\tu32 security_protocol_cmds_fw: 1;\n\t\tu32 support_ext_queue_depth: 1;\n\t\tu32 support_ext_io_size: 1;\n\t\tu32 support_vfid_in_ioframe: 1;\n\t\tu32 support_fp_rlbypass: 1;\n\t\tu32 support_qd_throttling: 1;\n\t\tu32 support_pd_map_target_id: 1;\n\t\tu32 support_64bit_mode: 1;\n\t\tu32 support_nvme_passthru: 1;\n\t\tu32 support_fw_exposed_dev_list: 1;\n\t\tu32 support_memdump: 1;\n\t\tu32 reserved: 15;\n\t} mfi_capabilities;\n\t__le32 reg;\n};\n\ntypedef union _MFI_CAPABILITIES MFI_CAPABILITIES;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct user_pt_regs {\n\t__u64 regs[31];\n\t__u64 sp;\n\t__u64 pc;\n\t__u64 pstate;\n};\n\nstruct frame_record {\n\tu64 fp;\n\tu64 lr;\n};\n\nstruct frame_record_meta {\n\tstruct frame_record record;\n\tu64 type;\n};\n\nstruct pt_regs {\n\tunion {\n\t\tstruct user_pt_regs user_regs;\n\t\tstruct {\n\t\t\tu64 regs[31];\n\t\t\tu64 sp;\n\t\t\tu64 pc;\n\t\t\tu64 pstate;\n\t\t};\n\t};\n\tu64 orig_x0;\n\ts32 syscallno;\n\tu32 pmr;\n\tu64 sdei_ttbr1;\n\tstruct frame_record_meta stackframe;\n};\n\nstruct __arch_ftrace_regs {\n\tstruct pt_regs regs;\n};\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n\tu16 src;\n\tu16 dst;\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct idr;\n\nstruct __class_idr {\n\tstruct idr *idr;\n\tint id;\n};\n\ntypedef struct __class_idr class_idr_alloc_t;\n\nstruct cpumask;\n\nstruct __cmp_key {\n\tconst struct cpumask *cpus;\n\tstruct cpumask ***masks;\n\tint node;\n\tint cpu;\n\tint w;\n};\n\nstruct __compat_aio_sigset {\n\tcompat_uptr_t sigmask;\n\tcompat_size_t sigsetsize;\n};\n\nstruct __extcon_info {\n\tunsigned int type;\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct __fat_dirent {\n\tlong int d_ino;\n\t__kernel_off_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[256];\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nunion __fpsimd_vreg {\n\t__int128 unsigned raw;\n\tstruct {\n\t\tu64 lo;\n\t\tu64 hi;\n\t};\n};\n\nstruct arm64_ftr_reg;\n\nstruct __ftr_reg_entry {\n\tu32 sys_id;\n\tstruct arm64_ftr_reg *reg;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct pmu;\n\nstruct cgroup;\n\nstruct __group_key {\n\tint cpu;\n\tstruct pmu *pmu;\n\tstruct cgroup *cgroup;\n};\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct sha512_block_state {\n\tu64 h[8];\n};\n\nstruct __sha512_ctx {\n\tstruct sha512_block_state state;\n\tu64 bytecount_lo;\n\tu64 bytecount_hi;\n\tu8 buf[128];\n};\n\nstruct __hmac_sha512_ctx {\n\tstruct __sha512_ctx sha_ctx;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __hmac_sha512_key {\n\tstruct sha512_block_state istate;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct qm_cgr_wr_parm {\n\t__be32 word;\n};\n\nstruct qm_cgr_cs_thres {\n\t__be16 word;\n};\n\nstruct __qm_mc_cgr {\n\tstruct qm_cgr_wr_parm wr_parm_g;\n\tstruct qm_cgr_wr_parm wr_parm_y;\n\tstruct qm_cgr_wr_parm wr_parm_r;\n\tu8 wr_en_g;\n\tu8 wr_en_y;\n\tu8 wr_en_r;\n\tu8 cscn_en;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 cscn_targ_upd_ctrl;\n\t\t\t__be16 cscn_targ_dcp_low;\n\t\t};\n\t\t__be32 cscn_targ;\n\t};\n\tu8 cstd_en;\n\tu8 cs;\n\tstruct qm_cgr_cs_thres cs_thres;\n\tu8 mode;\n} __attribute__((packed));\n\nstruct __qm_mcr_querycongestion {\n\tu32 state[8];\n};\n\nstruct sha3_state {\n\tunion {\n\t\t__le64 words[25];\n\t\tu8 bytes[200];\n\t\tu64 native_words[25];\n\t};\n};\n\nstruct __sha3_ctx {\n\tstruct sha3_state state;\n\tu8 digest_size;\n\tu8 block_size;\n\tu8 absorb_offset;\n\tu8 squeeze_offset;\n};\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[8];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[8];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct dentry;\n\nstruct __track_dentry_update_args {\n\tstruct dentry *dentry;\n\tint op;\n};\n\nstruct __track_range_args {\n\text4_lblk_t start;\n\text4_lblk_t end;\n};\n\nunion __u128_halves {\n\tu128 full;\n\tstruct {\n\t\tu64 low;\n\t\tu64 high;\n\t};\n};\n\nstruct inode;\n\nstruct __uprobe_key {\n\tstruct inode *inode;\n\tloff_t offset;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct __va_list {\n\tvoid *__stack;\n\tvoid *__gr_top;\n\tvoid *__vr_top;\n\tint __gr_offs;\n\tint __vr_offs;\n};\n\ntypedef struct __va_list va_list;\n\nstruct _aarch64_ctx {\n\t__u32 magic;\n\t__u32 size;\n};\n\nstruct _arg_GO {\n\tu8 chan;\n\tu32 addr;\n\tunsigned int ns;\n};\n\nstruct _arg_LPEND {\n\tenum pl330_cond cond;\n\tbool forever;\n\tunsigned int loop;\n\tu8 bjump;\n};\n\nstruct net_device;\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nstruct _ccu_mult {\n\tlong unsigned int mult;\n\tlong unsigned int min;\n\tlong unsigned int max;\n};\n\nstruct _ccu_nk {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n};\n\nstruct _ccu_nkm {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n};\n\nstruct _ccu_nkmp {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int k;\n\tlong unsigned int min_k;\n\tlong unsigned int max_k;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n\tlong unsigned int p;\n\tlong unsigned int min_p;\n\tlong unsigned int max_p;\n};\n\nstruct _ccu_nm {\n\tlong unsigned int n;\n\tlong unsigned int min_n;\n\tlong unsigned int max_n;\n\tlong unsigned int m;\n\tlong unsigned int min_m;\n\tlong unsigned int max_m;\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _gpiochip_for_each_data {\n\tconst char **label;\n\tunsigned int *i;\n};\n\ntypedef struct _gpiochip_for_each_data class__gpiochip_for_each_data_t;\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n} __attribute__((packed));\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct kvm_io_device_ops;\n\nstruct kvm_io_device {\n\tconst struct kvm_io_device_ops *ops;\n};\n\nstruct eventfd_ctx;\n\nstruct _ioeventfd {\n\tstruct list_head list;\n\tu64 addr;\n\tint length;\n\tstruct eventfd_ctx *eventfd;\n\tu64 datamatch;\n\tstruct kvm_io_device dev;\n\tu8 bus_idx;\n\tbool wildcard;\n};\n\nstruct kvm_stats_desc {\n\t__u32 flags;\n\t__s16 exponent;\n\t__u16 size;\n\t__u32 offset;\n\t__u32 bucket_size;\n\tchar name[0];\n};\n\nstruct _kvm_stats_desc {\n\tstruct kvm_stats_desc desc;\n\tchar name[48];\n};\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct dma_pl330_desc;\n\nstruct _pl330_req {\n\tu32 mc_bus;\n\tvoid *mc_cpu;\n\tstruct dma_pl330_desc *desc;\n};\n\nstruct _pl330_tbd {\n\tbool reset_dmac;\n\tbool reset_mngr;\n\tu8 reset_chan;\n};\n\nstruct _scpi_sensor_info {\n\t__le16 sensor_id;\n\tu8 class;\n\tu8 trigger_type;\n\tchar name[20];\n};\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct _xfer_spec {\n\tu32 ccr;\n\tstruct dma_pl330_desc *desc;\n};\n\nstruct spi_controller;\n\nstruct clk;\n\nstruct a3700_spi {\n\tstruct spi_controller *host;\n\tvoid *base;\n\tstruct clk *clk;\n\tunsigned int irq;\n\tunsigned int flags;\n\tbool xmit_data;\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tsize_t buf_len;\n\tu8 byte_len;\n\tu32 wait_mask;\n\tstruct completion done;\n};\n\nstruct a4tech_sc {\n\tlong unsigned int quirks;\n\tunsigned int hw_wheel;\n\t__s32 delayed_value;\n};\n\nstruct aarch64_insn_patch {\n\tvoid **text_addrs;\n\tu32 *new_insns;\n\tint insn_cnt;\n\tatomic_t cpu_count;\n};\n\nstruct reg_sequence;\n\nstruct acc_desc {\n\tunsigned int enable_reg;\n\tu32 enable_mask;\n\tstruct reg_sequence *config;\n\tstruct reg_sequence *settings;\n\tint num_regs_per_fuse;\n};\n\nstruct access_coordinate {\n\tunsigned int read_bandwidth;\n\tunsigned int write_bandwidth;\n\tunsigned int read_latency;\n\tunsigned int write_latency;\n};\n\nstruct acct_v3 {\n\tchar ac_flag;\n\tchar ac_version;\n\t__u16 ac_tty;\n\t__u32 ac_exitcode;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u32 ac_etime;\n\tcomp_t ac_utime;\n\tcomp_t ac_stime;\n\tcomp_t ac_mem;\n\tcomp_t ac_io;\n\tcomp_t ac_rw;\n\tcomp_t ac_minflt;\n\tcomp_t ac_majflt;\n\tcomp_t ac_swaps;\n\tchar ac_comm[16];\n};\n\ntypedef struct acct_v3 acct_t;\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n};\n\nstruct comp_alg_common {\n\tstruct crypto_alg base;\n};\n\nstruct acomp_req;\n\nstruct crypto_acomp;\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\ntypedef void (*crypto_completion_t)(void *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n\tunsigned int dma_length;\n\tunsigned int dma_flags;\n};\n\nstruct acomp_req_chain {\n\tcrypto_completion_t compl;\n\tvoid *data;\n\tstruct scatterlist ssg;\n\tstruct scatterlist dsg;\n\tunion {\n\t\tconst u8 *src;\n\t\tstruct folio *sfolio;\n\t};\n\tunion {\n\t\tu8 *dst;\n\t\tstruct folio *dfolio;\n\t};\n\tu32 flags;\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tunion {\n\t\tstruct scatterlist *dst;\n\t\tu8 *dvirt;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct acomp_req_chain chain;\n\tvoid *__ctx[0];\n};\n\nunion crypto_no_such_thing;\n\nstruct scatter_walk {\n\tunion {\n\t\tvoid * const addr;\n\t\tunion crypto_no_such_thing *__addr;\n\t};\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct acomp_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tint flags;\n};\n\nstruct power_supply;\n\nunion power_supply_propval;\n\nstruct power_supply_desc {\n\tconst char *name;\n\tenum power_supply_type type;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tu32 usb_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, enum power_supply_property);\n\tvoid (*external_power_changed)(struct power_supply *);\n\tbool no_thermal;\n\tint use_for_apm;\n};\n\nstruct notifier_block;\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct acpi_device;\n\nstruct acpi_ac {\n\tstruct power_supply *charger;\n\tstruct power_supply_desc charger_desc;\n\tstruct acpi_device *device;\n\tlong long unsigned int state;\n\tstruct notifier_block battery_nb;\n};\n\nstruct acpi_address16_attribute {\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n};\n\nstruct acpi_address32_attribute {\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n};\n\nstruct acpi_address64_attribute {\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n};\n\nstruct acpi_namespace_node;\n\nstruct acpi_address_range {\n\tstruct acpi_address_range *next;\n\tstruct acpi_namespace_node *region_node;\n\tacpi_physical_address start_address;\n\tacpi_physical_address end_address;\n};\n\nstruct acpi_apmt_node {\n\tu16 length;\n\tu8 flags;\n\tu8 type;\n\tu32 id;\n\tu64 inst_primary;\n\tu32 inst_secondary;\n\tu64 base_address0;\n\tu64 base_address1;\n\tu32 ovflw_irq;\n\tu32 reserved;\n\tu32 ovflw_irq_flags;\n\tu32 proc_affinity;\n\tu32 impl_id;\n} __attribute__((packed));\n\nstruct acpi_battery {\n\tstruct mutex update_lock;\n\tstruct power_supply *bat;\n\tstruct power_supply_desc bat_desc;\n\tstruct acpi_device *device;\n\tstruct notifier_block pm_nb;\n\tstruct list_head list;\n\tlong unsigned int update_time;\n\tint revision;\n\tint rate_now;\n\tint capacity_now;\n\tint voltage_now;\n\tint design_capacity;\n\tint full_charge_capacity;\n\tint technology;\n\tint design_voltage;\n\tint design_capacity_warning;\n\tint design_capacity_low;\n\tint cycle_count;\n\tint measurement_accuracy;\n\tint max_sampling_time;\n\tint min_sampling_time;\n\tint max_averaging_interval;\n\tint min_averaging_interval;\n\tint capacity_granularity_1;\n\tint capacity_granularity_2;\n\tint alarm;\n\tchar model_number[64];\n\tchar serial_number[64];\n\tchar type[64];\n\tchar oem_info[64];\n\tint state;\n\tint power_unit;\n\tlong unsigned int flags;\n};\n\nstruct acpi_battery_hook {\n\tconst char *name;\n\tint (*add_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tint (*remove_battery)(struct power_supply *, struct acpi_battery_hook *);\n\tstruct list_head list;\n};\n\nstruct acpi_bert_region {\n\tu32 block_status;\n\tu32 raw_data_offset;\n\tu32 raw_data_length;\n\tu32 data_length;\n\tu32 error_severity;\n};\n\nstruct acpi_buffer {\n\tacpi_size length;\n\tvoid *pointer;\n};\n\nstruct acpi_bus_event {\n\tstruct list_head node;\n\tacpi_device_class device_class;\n\tacpi_bus_id bus_id;\n\tu32 type;\n\tu32 data;\n};\n\nstruct acpi_bus_type {\n\tstruct list_head list;\n\tconst char *name;\n\tbool (*match)(struct device *);\n\tstruct acpi_device * (*find_companion)(struct device *);\n\tvoid (*setup)(struct device *);\n};\n\nstruct input_dev;\n\nstruct acpi_button {\n\tstruct acpi_device *adev;\n\tstruct device *dev;\n\tunsigned int type;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tlong unsigned int pushed;\n\tint last_state;\n\tktime_t last_time;\n\tbool suspended;\n\tbool lid_state_initialized;\n};\n\nstruct acpi_cdat_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_header {\n\tu8 type;\n\tu8 reserved;\n\tu16 length;\n};\n\nstruct acpi_cedt_cfmws {\n\tstruct acpi_cedt_header header;\n\tu32 reserved1;\n\tu64 base_hpa;\n\tu64 window_size;\n\tu8 interleave_ways;\n\tu8 interleave_arithmetic;\n\tu16 reserved2;\n\tu32 granularity;\n\tu16 restrictions;\n\tu16 qtg_id;\n\tu32 interleave_targets[0];\n} __attribute__((packed));\n\nstruct acpi_comment_node {\n\tchar *comment;\n\tstruct acpi_comment_node *next;\n};\n\nstruct acpi_common_descriptor {\n\tvoid *common_pointer;\n\tu8 descriptor_type;\n};\n\nstruct acpi_common_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n};\n\nstruct acpi_connection_info {\n\tu8 *connection;\n\tu16 length;\n\tu8 access_length;\n};\n\nunion acpi_parse_object;\n\nstruct acpi_control_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu16 opcode;\n\tunion acpi_parse_object *predicate_op;\n\tu8 *aml_predicate_start;\n\tu8 *package_end;\n\tu64 loop_timeout;\n};\n\nstruct acpi_create_field_info {\n\tstruct acpi_namespace_node *region_node;\n\tstruct acpi_namespace_node *field_node;\n\tstruct acpi_namespace_node *register_node;\n\tstruct acpi_namespace_node *data_register_node;\n\tstruct acpi_namespace_node *connection_node;\n\tu8 *resource_buffer;\n\tu32 bank_value;\n\tu32 field_bit_position;\n\tu32 field_bit_length;\n\tu16 resource_length;\n\tu16 pin_number_index;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 field_type;\n\tu8 access_length;\n};\n\nstruct acpi_csrt_group {\n\tu32 length;\n\tu32 vendor_id;\n\tu32 subvendor_id;\n\tu16 device_id;\n\tu16 subdevice_id;\n\tu16 revision;\n\tu16 reserved;\n\tu32 shared_info_length;\n};\n\nstruct acpi_csrt_shared_info {\n\tu16 major_version;\n\tu16 minor_version;\n\tu32 mmio_base_low;\n\tu32 mmio_base_high;\n\tu32 gsi_interrupt;\n\tu8 interrupt_polarity;\n\tu8 interrupt_mode;\n\tu8 num_channels;\n\tu8 dma_address_width;\n\tu16 base_request_line;\n\tu16 num_handshake_signals;\n\tu32 max_block_size;\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct address_space;\n\nstruct file;\n\nstruct vm_area_struct;\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct acpi_data_attr {\n\tstruct bin_attribute attr;\n\tu64 addr;\n};\n\ntypedef void *acpi_handle;\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nunion acpi_object;\n\nstruct acpi_device_data {\n\tconst union acpi_object *pointer;\n\tstruct list_head properties;\n\tconst union acpi_object *of_compatible;\n\tstruct list_head subnodes;\n};\n\nstruct acpi_data_node {\n\tstruct list_head sibling;\n\tconst char *name;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tstruct acpi_device_data data;\n\tstruct kobject kobj;\n\tstruct completion kobj_done;\n};\n\nstruct acpi_data_node_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct acpi_data_node *, char *);\n\tssize_t (*store)(struct acpi_data_node *, const char *, size_t);\n};\n\nstruct acpi_data_obj {\n\tchar *name;\n\tint (*fn)(void *, struct acpi_data_attr *);\n};\n\nstruct acpi_data_table_mapping {\n\tvoid *pointer;\n};\n\nstruct acpi_dep_data {\n\tstruct list_head node;\n\tacpi_handle supplier;\n\tacpi_handle consumer;\n\tbool honor_dep;\n\tbool met;\n\tbool free_when_met;\n};\n\nunion acpi_operand_object;\n\nstruct acpi_object_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n};\n\nstruct acpi_object_integer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 fill[3];\n\tu64 value;\n};\n\nstruct acpi_object_string {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tchar *pointer;\n\tu32 length;\n};\n\nstruct acpi_object_buffer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 *pointer;\n\tu32 length;\n\tu32 aml_length;\n\tu8 *aml_start;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_object_package {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **elements;\n\tu8 *aml_start;\n\tu32 aml_length;\n\tu32 count;\n};\n\nstruct acpi_object_event {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tvoid *os_semaphore;\n};\n\nstruct acpi_walk_state;\n\ntypedef acpi_status (*acpi_internal_method)(struct acpi_walk_state *);\n\nstruct acpi_object_method {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 info_flags;\n\tu8 param_count;\n\tu8 sync_level;\n\tunion acpi_operand_object *mutex;\n\tunion acpi_operand_object *node;\n\tu8 *aml_start;\n\tunion {\n\t\tacpi_internal_method implementation;\n\t\tunion acpi_operand_object *handler;\n\t} dispatch;\n\tu32 aml_length;\n\tacpi_owner_id owner_id;\n\tu8 thread_count;\n};\n\nstruct acpi_thread_state;\n\nstruct acpi_object_mutex {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 sync_level;\n\tu16 acquisition_depth;\n\tvoid *os_mutex;\n\tu64 thread_id;\n\tstruct acpi_thread_state *owner_thread;\n\tunion acpi_operand_object *prev;\n\tunion acpi_operand_object *next;\n\tstruct acpi_namespace_node *node;\n\tu8 original_sync_level;\n};\n\nstruct acpi_object_region {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler;\n\tunion acpi_operand_object *next;\n\tacpi_physical_address address;\n\tu32 length;\n\tvoid *pointer;\n};\n\nstruct acpi_object_notify_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_gpe_block_info;\n\nstruct acpi_object_device {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tstruct acpi_gpe_block_info *gpe_block;\n};\n\nstruct acpi_object_power_resource {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tu32 system_level;\n\tu32 resource_order;\n};\n\nstruct acpi_object_processor {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 proc_id;\n\tu8 length;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tacpi_io_address address;\n};\n\nstruct acpi_object_thermal_zone {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_object_field_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n};\n\nstruct acpi_object_region_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu16 resource_length;\n\tunion acpi_operand_object *region_obj;\n\tu8 *resource_buffer;\n\tu16 pin_number_index;\n\tu8 *internal_pcc_buffer;\n};\n\nstruct acpi_object_buffer_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu8 is_create_field;\n\tunion acpi_operand_object *buffer_obj;\n};\n\nstruct acpi_object_bank_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n\tunion acpi_operand_object *bank_obj;\n};\n\nstruct acpi_object_index_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *index_obj;\n\tunion acpi_operand_object *data_obj;\n};\n\ntypedef void (*acpi_notify_handler)(acpi_handle, u32, void *);\n\nstruct acpi_object_notify_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tu32 handler_type;\n\tacpi_notify_handler handler;\n\tvoid *context;\n\tunion acpi_operand_object *next[2];\n};\n\ntypedef acpi_status (*acpi_adr_space_handler)(u32, acpi_physical_address, u32, u64 *, void *, void *);\n\ntypedef acpi_status (*acpi_adr_space_setup)(acpi_handle, u32, void *, void **);\n\nstruct acpi_object_addr_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tu8 handler_flags;\n\tacpi_adr_space_handler handler;\n\tstruct acpi_namespace_node *node;\n\tvoid *context;\n\tvoid *context_mutex;\n\tacpi_adr_space_setup setup;\n\tunion acpi_operand_object *region_list;\n\tunion acpi_operand_object *next;\n};\n\nstruct acpi_object_reference {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 class;\n\tu8 target_type;\n\tu8 resolved;\n\tvoid *object;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **where;\n\tu8 *index_pointer;\n\tu8 *aml;\n\tu32 value;\n};\n\nstruct acpi_object_extra {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *method_REG;\n\tstruct acpi_namespace_node *scope_node;\n\tvoid *region_context;\n\tu8 *aml_start;\n\tu32 aml_length;\n};\n\ntypedef void (*acpi_object_handler)(acpi_handle, void *);\n\nstruct acpi_object_data {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tacpi_object_handler handler;\n\tvoid *pointer;\n};\n\nstruct acpi_object_cache_list {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *next;\n};\n\nunion acpi_name_union {\n\tu32 integer;\n\tchar ascii[4];\n};\n\nstruct acpi_namespace_node {\n\tunion acpi_operand_object *object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 flags;\n\tunion acpi_name_union name;\n\tstruct acpi_namespace_node *parent;\n\tstruct acpi_namespace_node *child;\n\tstruct acpi_namespace_node *peer;\n\tacpi_owner_id owner_id;\n};\n\nunion acpi_operand_object {\n\tstruct acpi_object_common common;\n\tstruct acpi_object_integer integer;\n\tstruct acpi_object_string string;\n\tstruct acpi_object_buffer buffer;\n\tstruct acpi_object_package package;\n\tstruct acpi_object_event event;\n\tstruct acpi_object_method method;\n\tstruct acpi_object_mutex mutex;\n\tstruct acpi_object_region region;\n\tstruct acpi_object_notify_common common_notify;\n\tstruct acpi_object_device device;\n\tstruct acpi_object_power_resource power_resource;\n\tstruct acpi_object_processor processor;\n\tstruct acpi_object_thermal_zone thermal_zone;\n\tstruct acpi_object_field_common common_field;\n\tstruct acpi_object_region_field field;\n\tstruct acpi_object_buffer_field buffer_field;\n\tstruct acpi_object_bank_field bank_field;\n\tstruct acpi_object_index_field index_field;\n\tstruct acpi_object_notify_handler notify;\n\tstruct acpi_object_addr_handler address_space;\n\tstruct acpi_object_reference reference;\n\tstruct acpi_object_extra extra;\n\tstruct acpi_object_data data;\n\tstruct acpi_object_cache_list cache;\n\tstruct acpi_namespace_node node;\n};\n\nunion acpi_parse_value {\n\tu64 integer;\n\tu32 size;\n\tchar *string;\n\tu8 *buffer;\n\tchar *name;\n\tunion acpi_parse_object *arg;\n};\n\nstruct acpi_parse_obj_common {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n};\n\nstruct acpi_parse_obj_named {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tchar *path;\n\tu8 *data;\n\tu32 length;\n\tu32 name;\n};\n\nstruct acpi_parse_obj_asl {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tu16 disasm_flags;\n\tu8 disasm_opcode;\n\tchar *operator_symbol;\n\tchar aml_op_name[16];\n\tunion acpi_parse_object *child;\n\tunion acpi_parse_object *parent_method;\n\tchar *filename;\n\tu8 file_changed;\n\tchar *parent_filename;\n\tchar *external_name;\n\tchar *namepath;\n\tchar name_seg[4];\n\tu32 extra_value;\n\tu32 column;\n\tu32 line_number;\n\tu32 logical_line_number;\n\tu32 logical_byte_offset;\n\tu32 end_line;\n\tu32 end_logical_line;\n\tu32 acpi_btype;\n\tu32 aml_length;\n\tu32 aml_subtree_length;\n\tu32 final_aml_length;\n\tu32 final_aml_offset;\n\tu32 compile_flags;\n\tu16 parse_opcode;\n\tu8 aml_opcode_length;\n\tu8 aml_pkg_len_bytes;\n\tu8 extra;\n\tchar parse_op_name[20];\n};\n\nunion acpi_parse_object {\n\tstruct acpi_parse_obj_common common;\n\tstruct acpi_parse_obj_named named;\n\tstruct acpi_parse_obj_asl asl;\n};\n\nunion acpi_descriptor {\n\tstruct acpi_common_descriptor common;\n\tunion acpi_operand_object object;\n\tstruct acpi_namespace_node node;\n\tunion acpi_parse_object op;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct acpi_dev_match_info {\n\tstruct acpi_device_id hid[2];\n\tconst char *uid;\n\ts64 hrv;\n};\n\nstruct acpi_dev_walk_context {\n\tint (*fn)(struct acpi_device *, void *);\n\tvoid *data;\n};\n\nstruct acpi_device_status {\n\tu32 present: 1;\n\tu32 enabled: 1;\n\tu32 show_in_ui: 1;\n\tu32 functional: 1;\n\tu32 battery_present: 1;\n\tu32 reserved: 27;\n};\n\nstruct acpi_device_flags {\n\tu32 dynamic_status: 1;\n\tu32 removable: 1;\n\tu32 ejectable: 1;\n\tu32 power_manageable: 1;\n\tu32 match_driver: 1;\n\tu32 initialized: 1;\n\tu32 visited: 1;\n\tu32 hotplug_notify: 1;\n\tu32 is_dock_station: 1;\n\tu32 of_compatible_ok: 1;\n\tu32 coherent_dma: 1;\n\tu32 cca_seen: 1;\n\tu32 enumeration_by_parent: 1;\n\tu32 honor_deps: 1;\n\tu32 reserved: 18;\n};\n\nstruct acpi_pnp_type {\n\tu32 hardware_id: 1;\n\tu32 bus_address: 1;\n\tu32 platform_id: 1;\n\tu32 backlight: 1;\n\tu32 reserved: 28;\n};\n\nstruct acpi_device_pnp {\n\tacpi_bus_id bus_id;\n\tint instance_no;\n\tstruct acpi_pnp_type type;\n\tacpi_bus_address bus_address;\n\tchar *unique_id;\n\tstruct list_head ids;\n\tacpi_device_name device_name;\n\tacpi_device_class device_class;\n};\n\nstruct acpi_device_power_flags {\n\tu32 explicit_get: 1;\n\tu32 power_resources: 1;\n\tu32 inrush_current: 1;\n\tu32 power_removed: 1;\n\tu32 ignore_parent: 1;\n\tu32 dsw_present: 1;\n\tu32 reserved: 26;\n};\n\nstruct acpi_device_power_state {\n\tstruct list_head resources;\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 explicit_set: 1;\n\t\tu8 reserved: 6;\n\t} flags;\n\tint power;\n\tint latency;\n};\n\nstruct acpi_device_power {\n\tint state;\n\tstruct acpi_device_power_flags flags;\n\tstruct acpi_device_power_state states[5];\n\tu8 state_for_enumeration;\n};\n\nstruct acpi_device_wakeup_flags {\n\tu8 valid: 1;\n\tu8 notifier_present: 1;\n};\n\nstruct acpi_device_wakeup_context {\n\tvoid (*func)(struct acpi_device_wakeup_context *);\n\tstruct device *dev;\n};\n\nstruct acpi_device_wakeup {\n\tacpi_handle gpe_device;\n\tu64 gpe_number;\n\tu64 sleep_state;\n\tstruct list_head resources;\n\tstruct acpi_device_wakeup_flags flags;\n\tstruct acpi_device_wakeup_context context;\n\tstruct wakeup_source *ws;\n\tint prepare_count;\n\tint enable_count;\n};\n\nstruct acpi_device_perf_flags {\n\tu8 reserved: 8;\n};\n\nstruct acpi_device_perf_state;\n\nstruct acpi_device_perf {\n\tint state;\n\tstruct acpi_device_perf_flags flags;\n\tint state_count;\n\tstruct acpi_device_perf_state *states;\n};\n\nstruct proc_dir_entry;\n\nstruct acpi_device_dir {\n\tstruct proc_dir_entry *entry;\n};\n\nstruct acpi_scan_handler;\n\nstruct acpi_hotplug_context;\n\nstruct acpi_device_software_nodes;\n\nstruct acpi_gpio_mapping;\n\nstruct acpi_device {\n\tu32 pld_crc;\n\tint device_type;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct list_head wakeup_list;\n\tstruct list_head del_list;\n\tstruct acpi_device_status status;\n\tstruct acpi_device_flags flags;\n\tstruct acpi_device_pnp pnp;\n\tstruct acpi_device_power power;\n\tstruct acpi_device_wakeup wakeup;\n\tstruct acpi_device_perf performance;\n\tstruct acpi_device_dir dir;\n\tstruct acpi_device_data data;\n\tstruct acpi_scan_handler *handler;\n\tstruct acpi_hotplug_context *hp;\n\tstruct acpi_device_software_nodes *swnodes;\n\tconst struct acpi_gpio_mapping *driver_gpios;\n\tvoid *driver_data;\n\tstruct device dev;\n\tunsigned int physical_node_count;\n\tunsigned int dep_unmet;\n\tstruct list_head physical_node_list;\n\tstruct mutex physical_node_lock;\n\tvoid (*remove)(struct acpi_device *);\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct acpi_device_bus_id {\n\tconst char *bus_id;\n\tstruct ida instance_ida;\n\tstruct list_head node;\n};\n\nstruct acpi_pnp_device_id {\n\tu32 length;\n\tchar *string;\n};\n\nstruct acpi_pnp_device_id_list {\n\tu32 count;\n\tu32 list_size;\n\tstruct acpi_pnp_device_id ids[0];\n};\n\nstruct acpi_device_info {\n\tu32 info_size;\n\tu32 name;\n\tacpi_object_type type;\n\tu8 param_count;\n\tu16 valid;\n\tu8 flags;\n\tu8 highest_dstates[4];\n\tu8 lowest_dstates[5];\n\tu64 address;\n\tstruct acpi_pnp_device_id hardware_id;\n\tstruct acpi_pnp_device_id unique_id;\n\tstruct acpi_pnp_device_id class_code;\n\tstruct acpi_pnp_device_id_list compatible_id_list;\n};\n\ntypedef int (*acpi_op_add)(struct acpi_device *);\n\ntypedef void (*acpi_op_remove)(struct acpi_device *);\n\ntypedef void (*acpi_op_notify)(struct acpi_device *, u32);\n\nstruct acpi_device_ops {\n\tacpi_op_add add;\n\tacpi_op_remove remove;\n\tacpi_op_notify notify;\n};\n\nstruct acpi_device_perf_state {\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 reserved: 7;\n\t} flags;\n\tu8 power;\n\tu8 performance;\n\tint latency;\n};\n\nstruct acpi_device_physical_node {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int node_id;\n\tbool put_online: 1;\n};\n\nstruct acpi_device_properties {\n\tstruct list_head list;\n\tconst guid_t *guid;\n\tunion acpi_object *properties;\n\tvoid **bufs;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[1];\n\t\t} value;\n\t};\n};\n\nstruct software_node;\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct acpi_device_software_node_port {\n\tchar port_name[9];\n\tu32 data_lanes[8];\n\tu32 lane_polarities[9];\n\tu64 link_frequencies[8];\n\tunsigned int port_nr;\n\tbool crs_csi2_local;\n\tstruct property_entry port_props[2];\n\tstruct property_entry ep_props[8];\n\tstruct software_node_ref_args remote_ep[1];\n};\n\nstruct acpi_device_software_nodes {\n\tstruct property_entry dev_props[6];\n\tstruct software_node *nodes;\n\tconst struct software_node **nodeptrs;\n\tstruct acpi_device_software_node_port *ports;\n\tunsigned int num_ports;\n};\n\nstruct acpi_table_desc;\n\nstruct acpi_evaluate_info;\n\nstruct acpi_device_walk_info {\n\tstruct acpi_table_desc *table_desc;\n\tstruct acpi_evaluate_info *evaluate_info;\n\tu32 device_count;\n\tu32 num_STA;\n\tu32 num_INI;\n};\n\nstruct acpi_dlayer {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct acpi_dlevel {\n\tconst char *name;\n\tlong unsigned int value;\n};\n\nstruct dma_chan;\n\nstruct acpi_dma_spec;\n\nstruct acpi_dma {\n\tstruct list_head dma_controllers;\n\tstruct device *dev;\n\tstruct dma_chan * (*acpi_dma_xlate)(struct acpi_dma_spec *, struct acpi_dma *);\n\tvoid *data;\n\tshort unsigned int base_request_line;\n\tshort unsigned int end_request_line;\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan *, void *);\n\nstruct acpi_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct acpi_dma_spec {\n\tint chan_id;\n\tint slave_id;\n\tstruct device *dev;\n};\n\nstruct acpi_dma_parser_data {\n\tstruct acpi_dma_spec dma_spec;\n\tsize_t index;\n\tsize_t n;\n};\n\nstruct of_device_id;\n\nstruct dev_pm_ops;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct acpi_driver {\n\tchar name[80];\n\tchar class[80];\n\tconst struct acpi_device_id *ids;\n\tunsigned int flags;\n\tstruct acpi_device_ops ops;\n\tstruct device_driver drv;\n};\n\nstruct acpi_einj_trigger {\n\tu32 header_size;\n\tu32 revision;\n\tu32 table_size;\n\tu32 entry_count;\n};\n\nunion acpi_predefined_info;\n\nstruct acpi_evaluate_info {\n\tstruct acpi_namespace_node *prefix_node;\n\tconst char *relative_pathname;\n\tunion acpi_operand_object **parameters;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *obj_desc;\n\tchar *full_pathname;\n\tconst union acpi_predefined_info *predefined;\n\tunion acpi_operand_object *return_object;\n\tunion acpi_operand_object *parent_package;\n\tu32 return_flags;\n\tu32 return_btype;\n\tu16 param_count;\n\tu16 node_flags;\n\tu8 pass_number;\n\tu8 return_object_type;\n\tu8 flags;\n};\n\nstruct acpi_exception_info {\n\tchar *name;\n};\n\nstruct acpi_exdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n} __attribute__((packed));\n\nstruct acpi_fadt_info {\n\tconst char *name;\n\tu16 address64;\n\tu16 address32;\n\tu16 length;\n\tu8 default_length;\n\tu8 flags;\n};\n\nstruct acpi_generic_address;\n\nstruct acpi_fadt_pm_info {\n\tstruct acpi_generic_address *target;\n\tu16 source;\n\tu8 register_num;\n};\n\nstruct acpi_fan_fif {\n\tu8 revision;\n\tu8 fine_grain_ctrl;\n\tu8 step_size;\n\tu8 low_speed_notification;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct acpi_fan_fps;\n\nstruct thermal_cooling_device;\n\nstruct acpi_fan {\n\tacpi_handle handle;\n\tbool acpi4;\n\tbool has_fst;\n\tstruct acpi_fan_fif fif;\n\tstruct acpi_fan_fps *fps;\n\tint fps_count;\n\tu32 fan_trip_granularity;\n\tstruct device *hdev;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device_attribute fst_speed;\n\tstruct device_attribute fine_grain_control;\n};\n\nstruct acpi_fan_fps {\n\tu64 control;\n\tu64 trip_point;\n\tu64 speed;\n\tu64 noise_level;\n\tu64 power;\n\tchar name[20];\n\tstruct device_attribute dev_attr;\n};\n\nstruct acpi_fan_fst {\n\tu64 revision;\n\tu64 control;\n\tu64 speed;\n};\n\nstruct acpi_ffh_info {\n\tu64 offset;\n\tu64 length;\n};\n\nstruct acpi_ged_device {\n\tstruct device *dev;\n\tstruct list_head event_list;\n};\n\nstruct acpi_ged_event {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int gsi;\n\tunsigned int irq;\n\tacpi_handle handle;\n};\n\nstruct acpi_ged_handler_info {\n\tstruct acpi_ged_handler_info *next;\n\tu32 int_id;\n\tstruct acpi_namespace_node *evt_method;\n};\n\nstruct acpi_generic_address {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_update_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *object;\n};\n\nstruct acpi_scope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_pscope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 arg_count;\n\tunion acpi_parse_object *op;\n\tu8 *arg_end;\n\tu8 *pkg_end;\n\tu32 arg_list;\n};\n\nstruct acpi_pkg_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 index;\n\tunion acpi_operand_object *source_object;\n\tunion acpi_operand_object *dest_object;\n\tstruct acpi_walk_state *walk_state;\n\tvoid *this_target_obj;\n\tu32 num_packages;\n};\n\nstruct acpi_thread_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 current_sync_level;\n\tstruct acpi_walk_state *walk_state_list;\n\tunion acpi_operand_object *acquired_mutex_list;\n\tu64 thread_id;\n};\n\nstruct acpi_result_values {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *obj_desc[8];\n};\n\nstruct acpi_global_notify_handler;\n\nstruct acpi_notify_info {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 handler_list_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler_list_head;\n\tstruct acpi_global_notify_handler *global;\n};\n\nunion acpi_generic_state {\n\tstruct acpi_common_state common;\n\tstruct acpi_control_state control;\n\tstruct acpi_update_state update;\n\tstruct acpi_scope_state scope;\n\tstruct acpi_pscope_state parse_scope;\n\tstruct acpi_pkg_state pkg;\n\tstruct acpi_thread_state thread;\n\tstruct acpi_result_values results;\n\tstruct acpi_notify_info notify;\n};\n\nstruct acpi_genl_event {\n\tacpi_device_class device_class;\n\tchar bus_id[15];\n\tu32 type;\n\tu32 data;\n};\n\ntypedef acpi_status (*acpi_walk_callback)(acpi_handle, u32, void *, void **);\n\nstruct acpi_get_devices_info {\n\tacpi_walk_callback user_function;\n\tvoid *context;\n\tconst char *hid;\n};\n\nstruct acpi_global_notify_handler {\n\tacpi_notify_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_gpe_address {\n\tu8 space_id;\n\tu64 address;\n};\n\nstruct acpi_gpe_xrupt_info;\n\nstruct acpi_gpe_register_info;\n\nstruct acpi_gpe_event_info;\n\nstruct acpi_gpe_block_info {\n\tstruct acpi_namespace_node *node;\n\tstruct acpi_gpe_block_info *previous;\n\tstruct acpi_gpe_block_info *next;\n\tstruct acpi_gpe_xrupt_info *xrupt_block;\n\tstruct acpi_gpe_register_info *register_info;\n\tstruct acpi_gpe_event_info *event_info;\n\tu64 address;\n\tu32 register_count;\n\tu16 gpe_count;\n\tu16 block_base_number;\n\tu8 space_id;\n\tu8 initialized;\n};\n\nstruct acpi_gpe_handler_info;\n\nstruct acpi_gpe_notify_info;\n\nunion acpi_gpe_dispatch_info {\n\tstruct acpi_namespace_node *method_node;\n\tstruct acpi_gpe_handler_info *handler;\n\tstruct acpi_gpe_notify_info *notify_list;\n};\n\nstruct acpi_gpe_event_info {\n\tunion acpi_gpe_dispatch_info dispatch;\n\tstruct acpi_gpe_register_info *register_info;\n\tu8 flags;\n\tu8 gpe_number;\n\tu8 runtime_count;\n\tu8 disable_for_dispatch;\n};\n\ntypedef u32 (*acpi_gpe_handler)(acpi_handle, u32, void *);\n\nstruct acpi_gpe_handler_info {\n\tacpi_gpe_handler address;\n\tvoid *context;\n\tstruct acpi_namespace_node *method_node;\n\tu8 original_flags;\n\tu8 originally_enabled;\n};\n\nstruct acpi_gpe_notify_info {\n\tstruct acpi_namespace_node *device_node;\n\tstruct acpi_gpe_notify_info *next;\n};\n\nstruct acpi_gpe_register_info {\n\tstruct acpi_gpe_address status_address;\n\tstruct acpi_gpe_address enable_address;\n\tu16 base_gpe_number;\n\tu8 enable_for_wake;\n\tu8 enable_for_run;\n\tu8 mask_for_run;\n\tu8 enable_mask;\n};\n\nstruct acpi_gpe_xrupt_info {\n\tstruct acpi_gpe_xrupt_info *previous;\n\tstruct acpi_gpe_xrupt_info *next;\n\tstruct acpi_gpe_block_info *gpe_block_list_head;\n\tu32 interrupt_number;\n};\n\nstruct gpio_chip;\n\nstruct acpi_gpio_chip {\n\tstruct acpi_connection_info conn_info;\n\tstruct list_head conns;\n\tstruct mutex conn_lock;\n\tstruct gpio_chip *chip;\n\tstruct list_head events;\n\tstruct list_head deferred_req_irqs_list_entry;\n};\n\nstruct gpio_desc;\n\nstruct acpi_gpio_connection {\n\tstruct list_head node;\n\tunsigned int pin;\n\tstruct gpio_desc *desc;\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct acpi_gpio_event {\n\tstruct list_head node;\n\tacpi_handle handle;\n\tirq_handler_t handler;\n\tunsigned int pin;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tbool irq_is_wake;\n\tbool irq_requested;\n\tstruct gpio_desc *desc;\n};\n\nstruct acpi_gpio_info {\n\tstruct acpi_device *adev;\n\tenum gpiod_flags flags;\n\tbool gpioint;\n\tbool wake_capable;\n\tint pin_config;\n\tint polarity;\n\tint triggering;\n\tunsigned int debounce;\n\tunsigned int quirks;\n};\n\nstruct acpi_gpio_params {\n\tunsigned int crs_entry_index;\n\tshort unsigned int line_index;\n\tbool active_low;\n};\n\nstruct acpi_gpio_lookup {\n\tstruct acpi_gpio_params params;\n\tstruct acpi_gpio_info *info;\n\tstruct gpio_desc *desc;\n\tint n;\n};\n\nstruct acpi_gpio_mapping {\n\tconst char *name;\n\tconst struct acpi_gpio_params *data;\n\tunsigned int size;\n\tunsigned int quirks;\n};\n\nstruct acpi_gpiolib_dmi_quirk {\n\tbool no_edge_events_on_boot;\n\tchar *ignore_wake;\n\tchar *ignore_interrupt;\n};\n\nstruct acpi_table_gtdt;\n\nstruct acpi_gtdt_descriptor {\n\tstruct acpi_table_gtdt *gtdt;\n\tvoid *gtdt_end;\n\tvoid *platform_timer;\n};\n\nstruct acpi_gtdt_header {\n\tu8 type;\n\tu16 length;\n} __attribute__((packed));\n\nstruct acpi_gtdt_timer_block {\n\tstruct acpi_gtdt_header header;\n\tu8 reserved;\n\tu64 block_address;\n\tu32 timer_count;\n\tu32 timer_offset;\n} __attribute__((packed));\n\nstruct acpi_gtdt_timer_entry {\n\tu8 frame_number;\n\tu8 reserved[3];\n\tu64 base_address;\n\tu64 el0_base_address;\n\tu32 timer_interrupt;\n\tu32 timer_flags;\n\tu32 virtual_timer_interrupt;\n\tu32 virtual_timer_flags;\n\tu32 common_flags;\n} __attribute__((packed));\n\nstruct acpi_gtdt_watchdog {\n\tstruct acpi_gtdt_header header;\n\tu8 reserved;\n\tu64 refresh_frame_address;\n\tu64 control_frame_address;\n\tu32 timer_interrupt;\n\tu32 timer_flags;\n} __attribute__((packed));\n\nstruct acpi_handle_list {\n\tu32 count;\n\tacpi_handle *handles;\n};\n\nstruct acpi_hardware_id {\n\tstruct list_head list;\n\tconst char *id;\n};\n\nstruct acpi_hest_header {\n\tu16 type;\n\tu16 source_id;\n};\n\nstruct acpi_hest_notify {\n\tu8 type;\n\tu8 length;\n\tu16 config_write_enable;\n\tu32 poll_interval;\n\tu32 vector;\n\tu32 polling_threshold_value;\n\tu32 polling_threshold_window;\n\tu32 error_threshold_value;\n\tu32 error_threshold_window;\n};\n\nstruct acpi_hest_generic {\n\tstruct acpi_hest_header header;\n\tu16 related_source_id;\n\tu8 reserved;\n\tu8 enabled;\n\tu32 records_to_preallocate;\n\tu32 max_sections_per_record;\n\tu32 max_raw_data_length;\n\tstruct acpi_generic_address error_status_address;\n\tstruct acpi_hest_notify notify;\n\tu32 error_block_length;\n};\n\nstruct acpi_hest_generic_data {\n\tu8 section_type[16];\n\tu32 error_severity;\n\tu16 revision;\n\tu8 validation_bits;\n\tu8 flags;\n\tu32 error_data_length;\n\tu8 fru_id[16];\n\tu8 fru_text[20];\n};\n\nstruct acpi_hest_generic_data_v300 {\n\tu8 section_type[16];\n\tu32 error_severity;\n\tu16 revision;\n\tu8 validation_bits;\n\tu8 flags;\n\tu32 error_data_length;\n\tu8 fru_id[16];\n\tu8 fru_text[20];\n\tu64 time_stamp;\n};\n\nstruct acpi_hest_generic_status {\n\tu32 block_status;\n\tu32 raw_data_offset;\n\tu32 raw_data_length;\n\tu32 data_length;\n\tu32 error_severity;\n};\n\nstruct acpi_hest_generic_v2 {\n\tstruct acpi_hest_header header;\n\tu16 related_source_id;\n\tu8 reserved;\n\tu8 enabled;\n\tu32 records_to_preallocate;\n\tu32 max_sections_per_record;\n\tu32 max_raw_data_length;\n\tstruct acpi_generic_address error_status_address;\n\tstruct acpi_hest_notify notify;\n\tu32 error_block_length;\n\tstruct acpi_generic_address read_ack_register;\n\tu64 read_ack_preserve;\n\tu64 read_ack_write;\n} __attribute__((packed));\n\nstruct acpi_hest_ia_corrected {\n\tstruct acpi_hest_header header;\n\tu16 reserved1;\n\tu8 flags;\n\tu8 enabled;\n\tu32 records_to_preallocate;\n\tu32 max_sections_per_record;\n\tstruct acpi_hest_notify notify;\n\tu8 num_hardware_banks;\n\tu8 reserved2[3];\n};\n\nstruct acpi_hest_ia_deferred_check {\n\tstruct acpi_hest_header header;\n\tu16 reserved1;\n\tu8 flags;\n\tu8 enabled;\n\tu32 records_to_preallocate;\n\tu32 max_sections_per_record;\n\tstruct acpi_hest_notify notify;\n\tu8 num_hardware_banks;\n\tu8 reserved2[3];\n};\n\nstruct acpi_hest_ia_machine_check {\n\tstruct acpi_hest_header header;\n\tu16 reserved1;\n\tu8 flags;\n\tu8 enabled;\n\tu32 records_to_preallocate;\n\tu32 max_sections_per_record;\n\tu64 global_capability_data;\n\tu64 global_control_data;\n\tu8 num_hardware_banks;\n\tu8 reserved3[7];\n};\n\nstruct acpi_hmat_structure {\n\tu16 type;\n\tu16 reserved;\n\tu32 length;\n};\n\nstruct acpi_hmat_cache {\n\tstruct acpi_hmat_structure header;\n\tu32 memory_PD;\n\tu32 reserved1;\n\tu64 cache_size;\n\tu32 cache_attributes;\n\tu16 address_mode;\n\tu16 number_of_SMBIOShandles;\n};\n\nstruct acpi_hmat_locality {\n\tstruct acpi_hmat_structure header;\n\tu8 flags;\n\tu8 data_type;\n\tu8 min_transfer_size;\n\tu8 reserved1;\n\tu32 number_of_initiator_Pds;\n\tu32 number_of_target_Pds;\n\tu32 reserved2;\n\tu64 entry_base_unit;\n};\n\nstruct acpi_hmat_proximity_domain {\n\tstruct acpi_hmat_structure header;\n\tu16 flags;\n\tu16 reserved1;\n\tu32 processor_PD;\n\tu32 memory_PD;\n\tu32 reserved2;\n\tu64 reserved3;\n\tu64 reserved4;\n};\n\ntypedef int (*acpi_hp_notify)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_uevent)(struct acpi_device *, u32);\n\ntypedef void (*acpi_hp_fixup)(struct acpi_device *);\n\nstruct acpi_hotplug_context {\n\tstruct acpi_device *self;\n\tacpi_hp_notify notify;\n\tacpi_hp_uevent uevent;\n\tacpi_hp_fixup fixup;\n};\n\nstruct acpi_hotplug_profile {\n\tstruct kobject kobj;\n\tint (*scan_dependent)(struct acpi_device *);\n\tvoid (*notify_online)(struct acpi_device *);\n\tbool enabled: 1;\n\tbool demand_offline: 1;\n};\n\nstruct acpi_hp_work {\n\tstruct work_struct work;\n\tstruct acpi_device *adev;\n\tu32 src;\n};\n\nstruct acpi_init_walk_info {\n\tu32 table_index;\n\tu32 object_count;\n\tu32 method_count;\n\tu32 serial_method_count;\n\tu32 non_serial_method_count;\n\tu32 serialized_method_count;\n\tu32 device_count;\n\tu32 op_region_count;\n\tu32 field_count;\n\tu32 buffer_count;\n\tu32 package_count;\n\tu32 op_region_init;\n\tu32 field_init;\n\tu32 buffer_init;\n\tu32 package_init;\n\tacpi_owner_id owner_id;\n};\n\nstruct acpi_interface_info {\n\tchar *name;\n\tstruct acpi_interface_info *next;\n\tu8 flags;\n\tu8 value;\n};\n\nstruct acpi_io_attribute {\n\tu8 range_type;\n\tu8 translation;\n\tu8 translation_type;\n\tu8 reserved1;\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct acpi_ioremap {\n\tstruct list_head list;\n\tvoid *virt;\n\tacpi_physical_address phys;\n\tacpi_size size;\n\tunion {\n\t\tlong unsigned int refcount;\n\t\tstruct rcu_work rwork;\n\t} track;\n};\n\nstruct acpi_iort_id_mapping {\n\tu32 input_base;\n\tu32 id_count;\n\tu32 output_base;\n\tu32 output_reference;\n\tu32 flags;\n};\n\nstruct acpi_iort_its_group {\n\tu32 its_count;\n\tu32 identifiers[0];\n};\n\nstruct acpi_iort_iwb {\n\tu64 base_address;\n\tu16 iwb_index;\n\tchar device_name[0];\n} __attribute__((packed));\n\nstruct acpi_iort_memory_access {\n\tu32 cache_coherency;\n\tu8 hints;\n\tu16 reserved;\n\tu8 memory_flags;\n} __attribute__((packed));\n\nstruct acpi_iort_named_component {\n\tu32 node_flags;\n\tu64 memory_properties;\n\tu8 memory_address_limit;\n\tchar device_name[0];\n} __attribute__((packed));\n\nstruct acpi_iort_node {\n\tu8 type;\n\tu16 length;\n\tu8 revision;\n\tu32 identifier;\n\tu32 mapping_count;\n\tu32 mapping_offset;\n\tchar node_data[0];\n} __attribute__((packed));\n\nstruct acpi_iort_pmcg {\n\tu64 page0_base_address;\n\tu32 overflow_gsiv;\n\tu32 node_reference;\n\tu64 page1_base_address;\n};\n\nstruct acpi_iort_rmr {\n\tu32 flags;\n\tu32 rmr_count;\n\tu32 rmr_offset;\n};\n\nstruct acpi_iort_rmr_desc {\n\tu64 base_address;\n\tu64 length;\n\tu32 reserved;\n} __attribute__((packed));\n\nstruct acpi_iort_root_complex {\n\tu64 memory_properties;\n\tu32 ats_attribute;\n\tu32 pci_segment_number;\n\tu8 memory_address_limit;\n\tu16 pasid_capabilities;\n\tu8 reserved[0];\n} __attribute__((packed));\n\nstruct acpi_iort_smmu {\n\tu64 base_address;\n\tu64 span;\n\tu32 model;\n\tu32 flags;\n\tu32 global_interrupt_offset;\n\tu32 context_interrupt_count;\n\tu32 context_interrupt_offset;\n\tu32 pmu_interrupt_count;\n\tu32 pmu_interrupt_offset;\n\tu64 interrupts[0];\n} __attribute__((packed));\n\nstruct acpi_iort_smmu_v3 {\n\tu64 base_address;\n\tu32 flags;\n\tu32 reserved;\n\tu64 vatos_address;\n\tu32 model;\n\tu32 event_gsiv;\n\tu32 pri_gsiv;\n\tu32 gerr_gsiv;\n\tu32 sync_gsiv;\n\tu32 pxm;\n\tu32 id_mapping_index;\n} __attribute__((packed));\n\nstruct irq_fwspec;\n\nstruct acpi_irq_parse_one_ctx {\n\tint rc;\n\tunsigned int index;\n\tlong unsigned int *res_flags;\n\tstruct irq_fwspec *fwspec;\n};\n\nstruct acpi_lpat {\n\tint temp;\n\tint raw;\n};\n\nstruct acpi_lpat_conversion_table {\n\tstruct acpi_lpat *lpat;\n\tint lpat_count;\n};\n\nstruct acpi_lpi_state {\n\tu32 min_residency;\n\tu32 wake_latency;\n\tu32 flags;\n\tu32 arch_flags;\n\tu32 res_cnt_freq;\n\tu32 enable_parent_state;\n\tu64 address;\n\tu8 index;\n\tu8 entry_method;\n\tchar desc[32];\n};\n\nstruct acpi_lpi_states_array {\n\tunsigned int size;\n\tunsigned int composite_states_size;\n\tstruct acpi_lpi_state *entries;\n\tstruct acpi_lpi_state *composite_states[8];\n};\n\nstruct acpi_subtable_header {\n\tu8 type;\n\tu8 length;\n};\n\nstruct acpi_madt_core_pic {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu32 processor_id;\n\tu32 core_id;\n\tu32 flags;\n} __attribute__((packed));\n\nstruct acpi_madt_generic_distributor {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 gic_id;\n\tu64 base_address;\n\tu32 global_irq_base;\n\tu8 version;\n\tu8 reserved2[3];\n};\n\nstruct acpi_madt_generic_interrupt {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 cpu_interface_number;\n\tu32 uid;\n\tu32 flags;\n\tu32 parking_version;\n\tu32 performance_interrupt;\n\tu64 parked_address;\n\tu64 base_address;\n\tu64 gicv_base_address;\n\tu64 gich_base_address;\n\tu32 vgic_interrupt;\n\tu64 gicr_base_address;\n\tu64 arm_mpidr;\n\tu8 efficiency_class;\n\tu8 reserved2[1];\n\tu16 spe_interrupt;\n\tu16 trbe_interrupt;\n\tu16 iaffid;\n\tu32 irs_id;\n} __attribute__((packed));\n\nstruct acpi_madt_generic_msi_frame {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 msi_frame_id;\n\tu64 base_address;\n\tu32 flags;\n\tu16 spi_count;\n\tu16 spi_base;\n};\n\nstruct acpi_madt_generic_redistributor {\n\tstruct acpi_subtable_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu32 length;\n} __attribute__((packed));\n\nstruct acpi_madt_generic_translator {\n\tstruct acpi_subtable_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu32 translation_id;\n\tu64 base_address;\n\tu32 reserved2;\n} __attribute__((packed));\n\nstruct acpi_madt_gicv5_irs {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 reserved;\n\tu32 irs_id;\n\tu32 flags;\n\tu32 reserved2;\n\tu64 config_base_address;\n\tu64 setlpi_base_address;\n};\n\nstruct acpi_madt_gicv5_translate_frame {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 linked_translator_id;\n\tu32 translate_frame_id;\n\tu32 reserved2;\n\tu64 base_address;\n};\n\nstruct acpi_madt_gicv5_translator {\n\tstruct acpi_subtable_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu32 translator_id;\n\tu64 base_address;\n};\n\nstruct acpi_madt_interrupt_override {\n\tstruct acpi_subtable_header header;\n\tu8 bus;\n\tu8 source_irq;\n\tu32 global_irq;\n\tu16 inti_flags;\n} __attribute__((packed));\n\nstruct acpi_madt_interrupt_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu8 type;\n\tu8 id;\n\tu8 eid;\n\tu8 io_sapic_vector;\n\tu32 global_irq;\n\tu32 flags;\n};\n\nstruct acpi_madt_io_apic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 address;\n\tu32 global_irq_base;\n};\n\nstruct acpi_madt_io_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 global_irq_base;\n\tu64 address;\n};\n\nstruct acpi_madt_local_apic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu32 lapic_flags;\n};\n\nstruct acpi_madt_local_apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu16 inti_flags;\n\tu8 lint;\n} __attribute__((packed));\n\nstruct acpi_madt_local_apic_override {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_madt_local_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu8 eid;\n\tu8 reserved[3];\n\tu32 lapic_flags;\n\tu32 uid;\n\tchar uid_string[0];\n};\n\nstruct acpi_madt_local_x2apic {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 local_apic_id;\n\tu32 lapic_flags;\n\tu32 uid;\n};\n\nstruct acpi_madt_local_x2apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 uid;\n\tu8 lint;\n\tu8 reserved[3];\n};\n\nstruct acpi_madt_multiproc_wakeup {\n\tstruct acpi_subtable_header header;\n\tu16 version;\n\tu32 reserved;\n\tu64 mailbox_address;\n\tu64 reset_vector;\n};\n\nstruct acpi_madt_nmi_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 global_irq;\n};\n\nstruct acpi_madt_rintc {\n\tstruct acpi_subtable_header header;\n\tu8 version;\n\tu8 reserved;\n\tu32 flags;\n\tu64 hart_id;\n\tu32 uid;\n\tu32 ext_intc_id;\n\tu64 imsic_addr;\n\tu32 imsic_size;\n} __attribute__((packed));\n\nstruct acpi_mcfg_allocation {\n\tu64 address;\n\tu16 pci_segment;\n\tu8 start_bus_number;\n\tu8 end_bus_number;\n\tu32 reserved;\n};\n\nstruct acpi_mem_mapping {\n\tacpi_physical_address physical_address;\n\tu8 *logical_address;\n\tacpi_size length;\n\tstruct acpi_mem_mapping *next_mm;\n};\n\nstruct acpi_mem_space_context {\n\tu32 length;\n\tacpi_physical_address address;\n\tstruct acpi_mem_mapping *cur_mm;\n\tstruct acpi_mem_mapping *first_mm;\n};\n\nstruct acpi_memory_attribute {\n\tu8 write_protect;\n\tu8 caching;\n\tu8 range_type;\n\tu8 translation;\n};\n\nstruct acpi_memory_device {\n\tstruct acpi_device *device;\n\tstruct list_head res_list;\n\tint mgid;\n};\n\nstruct acpi_memory_info {\n\tstruct list_head list;\n\tu64 start_addr;\n\tu64 length;\n\tshort unsigned int caching;\n\tshort unsigned int write_protect;\n\tunsigned int enabled: 1;\n};\n\nstruct acpi_mutex_info {\n\tvoid *mutex;\n\tu32 use_count;\n\tu64 thread_id;\n};\n\nstruct acpi_name_info {\n\tchar name[4];\n\tu16 argument_list;\n\tu8 expected_btypes;\n} __attribute__((packed));\n\nstruct acpi_namestring_info {\n\tconst char *external_name;\n\tconst char *next_external_char;\n\tchar *internal_name;\n\tu32 length;\n\tu32 num_segments;\n\tu32 num_carats;\n\tu8 fully_qualified;\n};\n\nunion acpi_object {\n\tacpi_object_type type;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu64 value;\n\t} integer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tchar *pointer;\n\t} string;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tu8 *pointer;\n\t} buffer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 count;\n\t\tunion acpi_object *elements;\n\t} package;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tacpi_object_type actual_type;\n\t\tacpi_handle handle;\n\t} reference;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 proc_id;\n\t\tacpi_io_address pblk_address;\n\t\tu32 pblk_length;\n\t} processor;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 system_level;\n\t\tu32 resource_order;\n\t} power_resource;\n};\n\nstruct acpi_object_list {\n\tu32 count;\n\tunion acpi_object *pointer;\n};\n\nstruct acpi_offsets {\n\tsize_t offset;\n\tu8 mode;\n};\n\nstruct acpi_opcode_info {\n\tchar *name;\n\tu32 parse_args;\n\tu32 runtime_args;\n\tu16 flags;\n\tu8 object_type;\n\tu8 class;\n\tu8 type;\n};\n\ntypedef void (*acpi_osd_exec_callback)(void *);\n\nstruct acpi_os_dpc {\n\tacpi_osd_exec_callback function;\n\tvoid *context;\n\tstruct work_struct work;\n};\n\nstruct acpi_osc_context {\n\tchar *uuid_str;\n\tint rev;\n\tstruct acpi_buffer cap;\n\tstruct acpi_buffer ret;\n};\n\nstruct acpi_osi_config {\n\tu8 default_disabling;\n\tunsigned int linux_enable: 1;\n\tunsigned int linux_dmi: 1;\n\tunsigned int linux_cmdline: 1;\n\tunsigned int darwin_enable: 1;\n\tunsigned int darwin_dmi: 1;\n\tunsigned int darwin_cmdline: 1;\n};\n\nstruct acpi_osi_entry {\n\tchar string[64];\n\tbool enable;\n};\n\nstruct acpi_package_info {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 object_type2;\n\tu8 count2;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info2 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[4];\n\tu8 reserved;\n};\n\nstruct acpi_package_info3 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[2];\n\tu8 tail_object_type;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info4 {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 sub_object_types;\n\tu8 pkg_count;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_parse_state {\n\tu8 *aml_start;\n\tu8 *aml;\n\tu8 *aml_end;\n\tu8 *pkg_start;\n\tu8 *pkg_end;\n\tunion acpi_parse_object *start_op;\n\tstruct acpi_namespace_node *start_node;\n\tunion acpi_generic_state *scope;\n\tunion acpi_parse_object *start_scope;\n\tu32 aml_size;\n};\n\nstruct acpi_pcc_info {\n\tu8 subspace_id;\n\tu16 length;\n\tu8 *internal_buffer;\n};\n\nstruct acpi_pcct_ext_pcc_master {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved1;\n\tu64 base_address;\n\tu32 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu32 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_set_mask;\n\tu64 reserved2;\n\tstruct acpi_generic_address cmd_complete_register;\n\tu64 cmd_complete_mask;\n\tstruct acpi_generic_address cmd_update_register;\n\tu64 cmd_update_preserve_mask;\n\tu64 cmd_update_set_mask;\n\tstruct acpi_generic_address error_status_register;\n\tu64 error_status_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_ext_pcc_shared_memory {\n\tu32 signature;\n\tu32 flags;\n\tu32 length;\n\tu32 command;\n};\n\nstruct acpi_pcct_hw_reduced {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pcct_hw_reduced_type2 {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_write_mask;\n} __attribute__((packed));\n\nstruct acpi_pcct_shared_memory {\n\tu32 signature;\n\tu16 command;\n\tu16 status;\n};\n\nstruct acpi_pcct_subspace {\n\tstruct acpi_subtable_header header;\n\tu8 reserved[6];\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pci_device {\n\tacpi_handle device;\n\tstruct acpi_pci_device *next;\n};\n\nstruct acpi_pci_root;\n\nstruct acpi_pci_root_ops;\n\nstruct acpi_pci_root_info {\n\tstruct acpi_pci_root *root;\n\tstruct acpi_device *bridge;\n\tstruct acpi_pci_root_ops *ops;\n\tstruct list_head resources;\n\tchar name[16];\n};\n\nstruct pci_config_window;\n\nstruct acpi_pci_generic_root_info {\n\tstruct acpi_pci_root_info common;\n\tstruct pci_config_window *cfg;\n};\n\nstruct acpi_pci_id {\n\tu16 segment;\n\tu16 bus;\n\tu16 device;\n\tu16 function;\n};\n\nstruct acpi_pci_link_irq {\n\tu32 active;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 resource_type;\n\tu8 possible_count;\n\tu32 possible[16];\n\tu8 initialized: 1;\n\tu8 reserved: 7;\n};\n\nstruct acpi_pci_link {\n\tstruct list_head list;\n\tstruct acpi_device *device;\n\tstruct acpi_pci_link_irq irq;\n\tint refcnt;\n};\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct pci_bus;\n\nstruct acpi_pci_root {\n\tstruct acpi_device *device;\n\tstruct pci_bus *bus;\n\tu16 segment;\n\tint bridge_type;\n\tstruct resource secondary;\n\tu32 osc_support_set;\n\tu32 osc_control_set;\n\tu32 osc_ext_support_set;\n\tu32 osc_ext_control_set;\n\tphys_addr_t mcfg_addr;\n};\n\nstruct pci_ops;\n\nstruct acpi_pci_root_ops {\n\tstruct pci_ops *pci_ops;\n\tint (*init_info)(struct acpi_pci_root_info *);\n\tvoid (*release_info)(struct acpi_pci_root_info *);\n\tint (*prepare_resources)(struct acpi_pci_root_info *);\n};\n\nstruct acpi_pci_routing_table {\n\tu32 length;\n\tu32 pin;\n\tu64 address;\n\tu32 source_index;\n\tunion {\n\t\tchar pad[4];\n\t\tstruct {\n\t\t\tstruct {} __Empty_source;\n\t\t\tchar source[0];\n\t\t};\n\t};\n};\n\nstruct acpi_pct_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_pkg_info {\n\tu8 *free_space;\n\tacpi_size length;\n\tu32 object_space;\n\tu32 num_packages;\n};\n\nstruct acpi_platform_list {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n\tchar *table;\n\tenum acpi_predicate pred;\n\tchar *reason;\n\tu32 data;\n};\n\nstruct acpi_pld_info {\n\tu8 revision;\n\tu8 ignore_color;\n\tu8 red;\n\tu8 green;\n\tu8 blue;\n\tu16 width;\n\tu16 height;\n\tu8 user_visible;\n\tu8 dock;\n\tu8 lid;\n\tu8 panel;\n\tu8 vertical_position;\n\tu8 horizontal_position;\n\tu8 shape;\n\tu8 group_orientation;\n\tu8 group_token;\n\tu8 group_position;\n\tu8 bay;\n\tu8 ejectable;\n\tu8 ospm_eject_required;\n\tu8 cabinet_number;\n\tu8 card_cage_number;\n\tu8 reference;\n\tu8 rotation;\n\tu8 order;\n\tu8 reserved;\n\tu16 vertical_offset;\n\tu16 horizontal_offset;\n};\n\nstruct acpi_port_info {\n\tchar *name;\n\tu16 start;\n\tu16 end;\n\tu8 osi_dependency;\n};\n\nstruct acpi_power_dependent_device {\n\tstruct device *dev;\n\tstruct list_head node;\n};\n\nstruct acpi_power_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_power_resource {\n\tstruct acpi_device device;\n\tstruct list_head list_node;\n\tu32 system_level;\n\tu32 order;\n\tunsigned int ref_count;\n\tu8 state;\n\tstruct mutex resource_lock;\n\tstruct list_head dependents;\n};\n\nstruct acpi_power_resource_entry {\n\tstruct list_head node;\n\tstruct acpi_power_resource *resource;\n};\n\nstruct acpi_pptt_cache {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 flags;\n\tu32 next_level_of_cache;\n\tu32 size;\n\tu32 number_of_sets;\n\tu8 associativity;\n\tu8 attributes;\n\tu16 line_size;\n};\n\nstruct acpi_pptt_cache_v1_full {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 flags;\n\tu32 next_level_of_cache;\n\tu32 size;\n\tu32 number_of_sets;\n\tu8 associativity;\n\tu8 attributes;\n\tu16 line_size;\n\tu32 cache_id;\n};\n\nstruct acpi_pptt_processor {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 flags;\n\tu32 parent;\n\tu32 acpi_processor_id;\n\tu32 number_of_priv_resources;\n};\n\nunion acpi_predefined_info {\n\tstruct acpi_name_info info;\n\tstruct acpi_package_info ret_info;\n\tstruct acpi_package_info2 ret_info2;\n\tstruct acpi_package_info3 ret_info3;\n\tstruct acpi_package_info4 ret_info4;\n};\n\nstruct acpi_predefined_names {\n\tconst char *name;\n\tu8 type;\n\tchar *val;\n};\n\nstruct acpi_prmt_handler_info {\n\tu16 revision;\n\tu16 length;\n\tu8 handler_guid[16];\n\tu64 handler_address;\n\tu64 static_data_buffer_address;\n\tu64 acpi_param_buffer_address;\n} __attribute__((packed));\n\nstruct acpi_prmt_module_header {\n\tu16 revision;\n\tu16 length;\n};\n\nstruct acpi_prmt_module_info {\n\tu16 revision;\n\tu16 length;\n\tu8 module_guid[16];\n\tu16 major_rev;\n\tu16 minor_rev;\n\tu16 handler_info_count;\n\tu32 handler_info_offset;\n\tu64 mmio_list_pointer;\n} __attribute__((packed));\n\nstruct acpi_probe_entry;\n\ntypedef bool (*acpi_probe_entry_validate_subtbl)(struct acpi_subtable_header *, struct acpi_probe_entry *);\n\nstruct acpi_table_header;\n\ntypedef int (*acpi_tbl_table_handler)(struct acpi_table_header *);\n\nunion acpi_subtable_headers;\n\ntypedef int (*acpi_tbl_entry_handler)(union acpi_subtable_headers *, const long unsigned int);\n\nstruct acpi_probe_entry {\n\t__u8 id[5];\n\t__u8 type;\n\tacpi_probe_entry_validate_subtbl subtable_valid;\n\tunion {\n\t\tacpi_tbl_table_handler probe_table;\n\t\tacpi_tbl_entry_handler probe_subtbl;\n\t};\n\tkernel_ulong_t driver_data;\n};\n\nstruct acpi_processor_flags {\n\tu8 power: 1;\n\tu8 performance: 1;\n\tu8 throttling: 1;\n\tu8 limit: 1;\n\tu8 bm_control: 1;\n\tu8 bm_check: 1;\n\tu8 has_cst: 1;\n\tu8 has_lpi: 1;\n\tu8 power_setup_done: 1;\n\tu8 bm_rld_set: 1;\n\tu8 previously_online: 1;\n};\n\nstruct acpi_processor_cx {\n\tu8 valid;\n\tu8 type;\n\tu32 address;\n\tu8 entry_method;\n\tu8 index;\n\tu32 latency;\n\tu8 bm_sts_skip;\n\tchar desc[32];\n};\n\nstruct acpi_processor_power {\n\tint count;\n\tunion {\n\t\tstruct acpi_processor_cx states[8];\n\t\tstruct acpi_lpi_state lpi_states[8];\n\t};\n\tint timer_broadcast_on_state;\n};\n\nstruct acpi_tsd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\ntypedef struct cpumask *cpumask_var_t;\n\nstruct acpi_processor_tx {\n\tu16 power;\n\tu16 performance;\n};\n\nstruct acpi_processor_tx_tss;\n\nstruct acpi_processor;\n\nstruct acpi_processor_throttling {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_tx_tss *states_tss;\n\tstruct acpi_tsd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tint (*acpi_processor_get_throttling)(struct acpi_processor *);\n\tint (*acpi_processor_set_throttling)(struct acpi_processor *, int, bool);\n\tu32 address;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 tsd_valid_flag;\n\tunsigned int shared_type;\n\tstruct acpi_processor_tx states[16];\n};\n\nstruct acpi_processor_lx {\n\tint px;\n\tint tx;\n};\n\nstruct acpi_processor_limit {\n\tstruct acpi_processor_lx state;\n\tstruct acpi_processor_lx thermal;\n\tstruct acpi_processor_lx user;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct freq_constraints;\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct acpi_processor_performance;\n\nstruct acpi_processor {\n\tacpi_handle handle;\n\tu32 acpi_id;\n\tphys_cpuid_t phys_id;\n\tu32 id;\n\tu32 pblk;\n\tint performance_platform_limit;\n\tint throttling_platform_limit;\n\tstruct acpi_processor_flags flags;\n\tstruct acpi_processor_power power;\n\tstruct acpi_processor_performance *performance;\n\tstruct acpi_processor_throttling throttling;\n\tstruct acpi_processor_limit limit;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device *dev;\n\tstruct freq_qos_request perflib_req;\n\tstruct freq_qos_request thermal_req;\n};\n\nstruct acpi_processor_errata {\n\tu8 smp;\n\tstruct {\n\t\tu8 throttle: 1;\n\t\tu8 fdma: 1;\n\t\tu8 reserved: 6;\n\t\tu32 bmisx;\n\t} piix4;\n};\n\nstruct acpi_psd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_processor_px;\n\nstruct acpi_processor_performance {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tunsigned int state_count;\n\tstruct acpi_processor_px *states;\n\tstruct acpi_psd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tunsigned int shared_type;\n};\n\nstruct acpi_processor_px {\n\tu64 core_frequency;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 bus_master_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_processor_tx_tss {\n\tu64 freqpercentage;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_prt_entry {\n\tstruct acpi_pci_id id;\n\tu8 pin;\n\tacpi_handle link;\n\tu32 index;\n};\n\nstruct acpi_reg_walk_info {\n\tu32 function;\n\tu32 reg_run_count;\n\tacpi_adr_space_type space_id;\n};\n\ntypedef acpi_status (*acpi_repair_function)(struct acpi_evaluate_info *, union acpi_operand_object **);\n\nstruct acpi_repair_info {\n\tchar name[4];\n\tacpi_repair_function repair_function;\n};\n\nstruct acpi_resource_irq {\n\tu8 descriptor_length;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tunion {\n\t\tu8 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu8 interrupts[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_dma {\n\tu8 type;\n\tu8 bus_master;\n\tu8 transfer;\n\tu8 channel_count;\n\tunion {\n\t\tu8 channel;\n\t\tstruct {\n\t\t\tstruct {} __Empty_channels;\n\t\t\tu8 channels[0];\n\t\t};\n\t};\n};\n\nstruct acpi_resource_start_dependent {\n\tu8 descriptor_length;\n\tu8 compatibility_priority;\n\tu8 performance_robustness;\n};\n\nstruct acpi_resource_io {\n\tu8 io_decode;\n\tu8 alignment;\n\tu8 address_length;\n\tu16 minimum;\n\tu16 maximum;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_io {\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_dma {\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct acpi_resource_vendor {\n\tu16 byte_length;\n\tu8 byte_data[0];\n};\n\nstruct acpi_resource_vendor_typed {\n\tu16 byte_length;\n\tu8 uuid_subtype;\n\tu8 uuid[16];\n\tu8 byte_data[0];\n} __attribute__((packed));\n\nstruct acpi_resource_end_tag {\n\tu8 checksum;\n};\n\nstruct acpi_resource_memory24 {\n\tu8 write_protect;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_memory32 {\n\tu8 write_protect;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_memory32 {\n\tu8 write_protect;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nunion acpi_resource_attribute {\n\tstruct acpi_memory_attribute mem;\n\tstruct acpi_io_attribute io;\n\tu8 type_specific;\n};\n\nstruct acpi_resource_source {\n\tu8 index;\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_address16 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address16_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address32 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address32_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address64_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tu8 revision_ID;\n\tstruct acpi_address64_attribute address;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_irq {\n\tu8 producer_consumer;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tstruct acpi_resource_source resource_source;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct acpi_resource_generic_register {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_resource_gpio {\n\tu8 revision_id;\n\tu8 connection_type;\n\tu8 producer_consumer;\n\tu8 pin_config;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 io_restriction;\n\tu8 triggering;\n\tu8 polarity;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_i2c_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 access_mode;\n\tu16 slave_address;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_spi_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 wire_mode;\n\tu8 device_polarity;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_uart_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 endian;\n\tu8 data_bits;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 parity;\n\tu8 lines_enabled;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu32 default_baud_rate;\n} __attribute__((packed));\n\nstruct acpi_resource_csi2_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 local_port_instance;\n\tu8 phy_type;\n} __attribute__((packed));\n\nstruct acpi_resource_common_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_function {\n\tu8 revision_id;\n\tu8 pin_config;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_label {\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tu16 *pin_table;\n\tstruct acpi_resource_label resource_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_function {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_clock_input {\n\tu8 revision_id;\n\tu8 mode;\n\tu8 scale;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n};\n\nunion acpi_resource_data {\n\tstruct acpi_resource_irq irq;\n\tstruct acpi_resource_dma dma;\n\tstruct acpi_resource_start_dependent start_dpf;\n\tstruct acpi_resource_io io;\n\tstruct acpi_resource_fixed_io fixed_io;\n\tstruct acpi_resource_fixed_dma fixed_dma;\n\tstruct acpi_resource_vendor vendor;\n\tstruct acpi_resource_vendor_typed vendor_typed;\n\tstruct acpi_resource_end_tag end_tag;\n\tstruct acpi_resource_memory24 memory24;\n\tstruct acpi_resource_memory32 memory32;\n\tstruct acpi_resource_fixed_memory32 fixed_memory32;\n\tstruct acpi_resource_address16 address16;\n\tstruct acpi_resource_address32 address32;\n\tstruct acpi_resource_address64 address64;\n\tstruct acpi_resource_extended_address64 ext_address64;\n\tstruct acpi_resource_extended_irq extended_irq;\n\tstruct acpi_resource_generic_register generic_reg;\n\tstruct acpi_resource_gpio gpio;\n\tstruct acpi_resource_i2c_serialbus i2c_serial_bus;\n\tstruct acpi_resource_spi_serialbus spi_serial_bus;\n\tstruct acpi_resource_uart_serialbus uart_serial_bus;\n\tstruct acpi_resource_csi2_serialbus csi2_serial_bus;\n\tstruct acpi_resource_common_serialbus common_serial_bus;\n\tstruct acpi_resource_pin_function pin_function;\n\tstruct acpi_resource_pin_config pin_config;\n\tstruct acpi_resource_pin_group pin_group;\n\tstruct acpi_resource_pin_group_function pin_group_function;\n\tstruct acpi_resource_pin_group_config pin_group_config;\n\tstruct acpi_resource_clock_input clock_input;\n\tstruct acpi_resource_address address;\n};\n\nstruct acpi_resource {\n\tu32 type;\n\tu32 length;\n\tunion acpi_resource_data data;\n};\n\nstruct acpi_rsconvert_info {\n\tu8 opcode;\n\tu8 resource_offset;\n\tu8 aml_offset;\n\tu8 value;\n};\n\nstruct acpi_rsdump_info {\n\tu8 opcode;\n\tu8 offset;\n\tconst char *name;\n\tconst char **pointer;\n} __attribute__((packed));\n\nstruct acpi_rw_lock {\n\tvoid *writer_mutex;\n\tvoid *reader_mutex;\n\tu32 num_readers;\n};\n\nstruct acpi_scan_handler {\n\tstruct list_head list_node;\n\tconst struct acpi_device_id *ids;\n\tbool (*match)(const char *, const struct acpi_device_id **);\n\tint (*attach)(struct acpi_device *, const struct acpi_device_id *);\n\tvoid (*detach)(struct acpi_device *);\n\tvoid (*post_eject)(struct acpi_device *);\n\tvoid (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n\tstruct acpi_hotplug_profile hotplug;\n};\n\nstruct acpi_scan_system_dev {\n\tstruct list_head node;\n\tstruct acpi_device *adev;\n};\n\ntypedef u32 (*acpi_sci_handler)(void *);\n\nstruct acpi_sci_handler_info {\n\tstruct acpi_sci_handler_info *next;\n\tacpi_sci_handler address;\n\tvoid *context;\n};\n\nstruct acpi_serdev_lookup {\n\tacpi_handle device_handle;\n\tacpi_handle controller_handle;\n\tint n;\n\tint index;\n};\n\nstruct acpi_signal_fatal_info {\n\tu32 type;\n\tu32 code;\n\tu32 argument;\n};\n\ntypedef acpi_status (*acpi_object_converter)(struct acpi_namespace_node *, union acpi_operand_object *, union acpi_operand_object **);\n\nstruct acpi_simple_repair_info {\n\tchar name[4];\n\tu32 unexpected_btypes;\n\tu32 package_index;\n\tacpi_object_converter object_converter;\n};\n\nstruct acpi_spi_lookup {\n\tstruct spi_controller *ctlr;\n\tu32 max_speed_hz;\n\tu32 mode;\n\tint irq;\n\tu8 bits_per_word;\n\tu8 chip_select;\n\tint n;\n\tint index;\n};\n\nstruct acpi_srat_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 proximity_domain_lo;\n\tu8 apic_id;\n\tu32 flags;\n\tu8 local_sapic_eid;\n\tu8 proximity_domain_hi[3];\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_generic_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 reserved;\n\tu8 device_handle_type;\n\tu32 proximity_domain;\n\tu8 device_handle[16];\n\tu32 flags;\n\tu32 reserved1;\n};\n\nstruct acpi_srat_gic_its_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu16 reserved;\n\tu32 its_id;\n} __attribute__((packed));\n\nstruct acpi_srat_gicc_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n} __attribute__((packed));\n\nstruct acpi_srat_mem_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu16 reserved;\n\tu64 base_address;\n\tu64 length;\n\tu32 reserved1;\n\tu32 flags;\n\tu64 reserved2;\n} __attribute__((packed));\n\nstruct acpi_srat_rintc_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_x2apic_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 apic_id;\n\tu32 flags;\n\tu32 clock_domain;\n\tu32 reserved2;\n};\n\nstruct acpi_subtable_entry {\n\tunion acpi_subtable_headers *hdr;\n\tenum acpi_subtable_type type;\n};\n\nunion acpi_subtable_headers {\n\tstruct acpi_subtable_header common;\n\tstruct acpi_hmat_structure hmat;\n\tstruct acpi_prmt_module_header prmt;\n\tstruct acpi_cedt_header cedt;\n\tstruct acpi_cdat_header cdat;\n};\n\ntypedef int (*acpi_tbl_entry_handler_arg)(union acpi_subtable_headers *, void *, const long unsigned int);\n\nstruct acpi_subtable_proc {\n\tint id;\n\tacpi_tbl_entry_handler handler;\n\tacpi_tbl_entry_handler_arg handler_arg;\n\tvoid *arg;\n\tint count;\n};\n\nstruct acpi_table_header {\n\tchar signature[4];\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tchar oem_id[6];\n\tchar oem_table_id[8];\n\tu32 oem_revision;\n\tchar asl_compiler_id[4];\n\tu32 asl_compiler_revision;\n};\n\nstruct acpi_table_apmt {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_table_attr {\n\tstruct bin_attribute attr;\n\tchar name[4];\n\tint instance;\n\tchar filename[8];\n\tstruct list_head node;\n};\n\nstruct acpi_table_bert {\n\tstruct acpi_table_header header;\n\tu32 region_length;\n\tu64 address;\n};\n\nstruct acpi_table_ccel {\n\tstruct acpi_table_header header;\n\tu8 CCtype;\n\tu8 Ccsub_type;\n\tu16 reserved;\n\tu64 log_area_minimum_length;\n\tu64 log_area_start_address;\n};\n\nstruct acpi_table_cdat {\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tu8 reserved[6];\n\tu32 sequence;\n};\n\nstruct acpi_table_csrt {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_table_desc {\n\tacpi_physical_address address;\n\tstruct acpi_table_header *pointer;\n\tu32 length;\n\tunion acpi_name_union signature;\n\tacpi_owner_id owner_id;\n\tu8 flags;\n\tu16 validation_count;\n};\n\nstruct acpi_table_einj {\n\tstruct acpi_table_header header;\n\tu32 header_length;\n\tu8 flags;\n\tu8 reserved[3];\n\tu32 entries;\n};\n\nstruct acpi_table_erst {\n\tstruct acpi_table_header header;\n\tu32 header_length;\n\tu32 reserved;\n\tu32 entries;\n};\n\nstruct acpi_table_facs {\n\tchar signature[4];\n\tu32 length;\n\tu32 hardware_signature;\n\tu32 firmware_waking_vector;\n\tu32 global_lock;\n\tu32 flags;\n\tu64 xfirmware_waking_vector;\n\tu8 version;\n\tu8 reserved[3];\n\tu32 ospm_flags;\n\tu8 reserved1[24];\n};\n\nstruct acpi_table_fadt {\n\tstruct acpi_table_header header;\n\tu32 facs;\n\tu32 dsdt;\n\tu8 model;\n\tu8 preferred_profile;\n\tu16 sci_interrupt;\n\tu32 smi_command;\n\tu8 acpi_enable;\n\tu8 acpi_disable;\n\tu8 s4_bios_request;\n\tu8 pstate_control;\n\tu32 pm1a_event_block;\n\tu32 pm1b_event_block;\n\tu32 pm1a_control_block;\n\tu32 pm1b_control_block;\n\tu32 pm2_control_block;\n\tu32 pm_timer_block;\n\tu32 gpe0_block;\n\tu32 gpe1_block;\n\tu8 pm1_event_length;\n\tu8 pm1_control_length;\n\tu8 pm2_control_length;\n\tu8 pm_timer_length;\n\tu8 gpe0_block_length;\n\tu8 gpe1_block_length;\n\tu8 gpe1_base;\n\tu8 cst_control;\n\tu16 c2_latency;\n\tu16 c3_latency;\n\tu16 flush_size;\n\tu16 flush_stride;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 day_alarm;\n\tu8 month_alarm;\n\tu8 century;\n\tu16 boot_flags;\n\tu8 reserved;\n\tu32 flags;\n\tstruct acpi_generic_address reset_register;\n\tu8 reset_value;\n\tu16 arm_boot_flags;\n\tu8 minor_revision;\n\tu64 Xfacs;\n\tu64 Xdsdt;\n\tstruct acpi_generic_address xpm1a_event_block;\n\tstruct acpi_generic_address xpm1b_event_block;\n\tstruct acpi_generic_address xpm1a_control_block;\n\tstruct acpi_generic_address xpm1b_control_block;\n\tstruct acpi_generic_address xpm2_control_block;\n\tstruct acpi_generic_address xpm_timer_block;\n\tstruct acpi_generic_address xgpe0_block;\n\tstruct acpi_generic_address xgpe1_block;\n\tstruct acpi_generic_address sleep_control;\n\tstruct acpi_generic_address sleep_status;\n\tu64 hypervisor_id;\n} __attribute__((packed));\n\nstruct acpi_table_gtdt {\n\tstruct acpi_table_header header;\n\tu64 counter_block_addresss;\n\tu32 reserved;\n\tu32 secure_el1_interrupt;\n\tu32 secure_el1_flags;\n\tu32 non_secure_el1_interrupt;\n\tu32 non_secure_el1_flags;\n\tu32 virtual_timer_interrupt;\n\tu32 virtual_timer_flags;\n\tu32 non_secure_el2_interrupt;\n\tu32 non_secure_el2_flags;\n\tu64 counter_read_block_address;\n\tu32 platform_timer_count;\n\tu32 platform_timer_offset;\n} __attribute__((packed));\n\nstruct acpi_table_hest {\n\tstruct acpi_table_header header;\n\tu32 error_source_count;\n};\n\nstruct acpi_table_iort {\n\tstruct acpi_table_header header;\n\tu32 node_count;\n\tu32 node_offset;\n\tu32 reserved;\n};\n\nstruct acpi_table_list {\n\tstruct acpi_table_desc *tables;\n\tu32 current_table_count;\n\tu32 max_table_count;\n\tu8 flags;\n};\n\nstruct acpi_table_madt {\n\tstruct acpi_table_header header;\n\tu32 address;\n\tu32 flags;\n};\n\nstruct acpi_table_mcfg {\n\tstruct acpi_table_header header;\n\tu8 reserved[8];\n};\n\nstruct acpi_table_pcct {\n\tstruct acpi_table_header header;\n\tu32 flags;\n\tu64 reserved;\n};\n\nstruct acpi_table_rsdp {\n\tchar signature[8];\n\tu8 checksum;\n\tchar oem_id[6];\n\tu8 revision;\n\tu32 rsdt_physical_address;\n\tu32 length;\n\tu64 xsdt_physical_address;\n\tu8 extended_checksum;\n\tu8 reserved[3];\n} __attribute__((packed));\n\nstruct acpi_table_slit {\n\tstruct acpi_table_header header;\n\tu64 locality_count;\n\tu8 entry[0];\n} __attribute__((packed));\n\nstruct acpi_table_spcr {\n\tstruct acpi_table_header header;\n\tu8 interface_type;\n\tu8 reserved[3];\n\tstruct acpi_generic_address serial_port;\n\tu8 interrupt_type;\n\tu8 pc_interrupt;\n\tu32 interrupt;\n\tu8 baud_rate;\n\tu8 parity;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 terminal_type;\n\tu8 language;\n\tu16 pci_device_id;\n\tu16 pci_vendor_id;\n\tu8 pci_bus;\n\tu8 pci_device;\n\tu8 pci_function;\n\tu32 pci_flags;\n\tu8 pci_segment;\n\tu32 uart_clk_freq;\n\tu32 precise_baudrate;\n\tu16 name_space_string_length;\n\tu16 name_space_string_offset;\n\tchar name_space_string[0];\n} __attribute__((packed));\n\nstruct acpi_table_srat {\n\tstruct acpi_table_header header;\n\tu32 table_revision;\n\tu64 reserved;\n};\n\nstruct acpi_table_stao {\n\tstruct acpi_table_header header;\n\tu8 ignore_uart;\n} __attribute__((packed));\n\nstruct acpi_table_tpm2 {\n\tstruct acpi_table_header header;\n\tu16 platform_class;\n\tu16 reserved;\n\tu64 control_address;\n\tu32 start_method;\n} __attribute__((packed));\n\nstruct client_hdr {\n\tu32 log_max_len;\n\tu64 log_start_addr;\n} __attribute__((packed));\n\nstruct server_hdr {\n\tu16 reserved;\n\tu64 log_max_len;\n\tu64 log_start_addr;\n} __attribute__((packed));\n\nstruct acpi_tcpa {\n\tstruct acpi_table_header hdr;\n\tu16 platform_class;\n\tunion {\n\t\tstruct client_hdr client;\n\t\tstruct server_hdr server;\n\t};\n};\n\nstruct acpi_thermal_trip {\n\tlong unsigned int temp_dk;\n\tstruct acpi_handle_list devices;\n};\n\nstruct acpi_thermal_passive {\n\tstruct acpi_thermal_trip trip;\n\tlong unsigned int tc1;\n\tlong unsigned int tc2;\n\tlong unsigned int delay;\n};\n\nstruct acpi_thermal_active {\n\tstruct acpi_thermal_trip trip;\n};\n\nstruct acpi_thermal_trips {\n\tstruct acpi_thermal_passive passive;\n\tstruct acpi_thermal_active active[10];\n};\n\nstruct thermal_zone_device;\n\nstruct acpi_thermal {\n\tstruct acpi_device *device;\n\tacpi_bus_id name;\n\tlong unsigned int temp_dk;\n\tlong unsigned int last_temp_dk;\n\tlong unsigned int polling_frequency;\n\tvolatile u8 zombie;\n\tstruct acpi_thermal_trips trips;\n\tstruct thermal_zone_device *thermal_zone;\n\tint kelvin_offset;\n\tstruct work_struct thermal_check_work;\n\tstruct mutex thermal_check_lock;\n\trefcount_t thermal_check_count;\n};\n\nstruct acpi_tpm2_phy {\n\tu8 start_method_specific[12];\n\tu32 log_area_minimum_length;\n\tu64 log_area_start_address;\n};\n\nstruct acpi_vendor_uuid {\n\tu8 subtype;\n\tu8 data[16];\n};\n\nstruct acpi_vendor_walk_info {\n\tstruct acpi_vendor_uuid *uuid;\n\tstruct acpi_buffer *buffer;\n\tacpi_status status;\n};\n\nstruct acpi_wakeup_handler {\n\tstruct list_head list_node;\n\tbool (*wakeup)(void *);\n\tvoid *context;\n};\n\nstruct acpi_walk_info {\n\tu32 debug_level;\n\tu32 count;\n\tacpi_owner_id owner_id;\n\tu8 display_type;\n};\n\ntypedef acpi_status (*acpi_parse_downwards)(struct acpi_walk_state *, union acpi_parse_object **);\n\ntypedef acpi_status (*acpi_parse_upwards)(struct acpi_walk_state *);\n\nstruct acpi_walk_state {\n\tstruct acpi_walk_state *next;\n\tu8 descriptor_type;\n\tu8 walk_type;\n\tu16 opcode;\n\tu8 next_op_info;\n\tu8 num_operands;\n\tu8 operand_index;\n\tacpi_owner_id owner_id;\n\tu8 last_predicate;\n\tu8 current_result;\n\tu8 return_used;\n\tu8 scope_depth;\n\tu8 pass_number;\n\tu8 namespace_override;\n\tu8 result_size;\n\tu8 result_count;\n\tu8 *aml;\n\tu32 arg_types;\n\tu32 method_breakpoint;\n\tu32 user_breakpoint;\n\tu32 parse_flags;\n\tstruct acpi_parse_state parser_state;\n\tu32 prev_arg_types;\n\tu32 arg_count;\n\tu16 method_nesting_depth;\n\tu8 method_is_nested;\n\tstruct acpi_namespace_node arguments[7];\n\tstruct acpi_namespace_node local_variables[8];\n\tunion acpi_operand_object *operands[9];\n\tunion acpi_operand_object **params;\n\tu8 *aml_last_while;\n\tunion acpi_operand_object **caller_return_desc;\n\tunion acpi_generic_state *control_state;\n\tstruct acpi_namespace_node *deferred_node;\n\tunion acpi_operand_object *implicit_return_obj;\n\tstruct acpi_namespace_node *method_call_node;\n\tunion acpi_parse_object *method_call_op;\n\tunion acpi_operand_object *method_desc;\n\tstruct acpi_namespace_node *method_node;\n\tchar *method_pathname;\n\tunion acpi_parse_object *op;\n\tconst struct acpi_opcode_info *op_info;\n\tunion acpi_parse_object *origin;\n\tunion acpi_operand_object *result_obj;\n\tunion acpi_generic_state *results;\n\tunion acpi_operand_object *return_desc;\n\tunion acpi_generic_state *scope_info;\n\tunion acpi_parse_object *prev_op;\n\tunion acpi_parse_object *next_op;\n\tstruct acpi_thread_state *thread;\n\tacpi_parse_downwards descending_callback;\n\tacpi_parse_upwards ascending_callback;\n};\n\nstruct acpi_whea_header {\n\tu8 action;\n\tu8 instruction;\n\tu8 flags;\n\tu8 reserved;\n\tstruct acpi_generic_address register_region;\n\tu64 value;\n\tu64 mask;\n};\n\nstruct hotplug_slot;\n\nstruct acpiphp_attention_info {\n\tint (*set_attn)(struct hotplug_slot *, u8);\n\tint (*get_attn)(struct hotplug_slot *, u8 *);\n\tstruct module *owner;\n};\n\nstruct acpiphp_context;\n\nstruct pci_dev;\n\nstruct acpiphp_bridge {\n\tstruct list_head list;\n\tstruct list_head slots;\n\tstruct kref ref;\n\tstruct acpiphp_context *context;\n\tint nr_slots;\n\tstruct pci_bus *pci_bus;\n\tstruct pci_dev *pci_dev;\n\tbool is_going_away;\n};\n\nstruct acpiphp_slot;\n\nstruct acpiphp_func {\n\tstruct acpiphp_bridge *parent;\n\tstruct acpiphp_slot *slot;\n\tstruct list_head sibling;\n\tu8 function;\n\tu32 flags;\n};\n\nstruct acpiphp_context {\n\tstruct acpi_hotplug_context hp;\n\tstruct acpiphp_func func;\n\tstruct acpiphp_bridge *bridge;\n\tunsigned int refcount;\n};\n\nstruct acpiphp_root_context {\n\tstruct acpi_hotplug_context hp;\n\tstruct acpiphp_bridge *root_bridge;\n};\n\nstruct slot;\n\nstruct acpiphp_slot {\n\tstruct list_head node;\n\tstruct pci_bus *bus;\n\tstruct list_head funcs;\n\tstruct slot *slot;\n\tu8 device;\n\tu32 flags;\n};\n\nstruct pnp_dev;\n\nstruct acpipnp_parse_option_s {\n\tstruct pnp_dev *dev;\n\tunsigned int option_flags;\n};\n\nstruct action_cache {\n\tlong unsigned int allow_native[8];\n\tlong unsigned int allow_compat[8];\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct action_gate_entry {\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n};\n\nstruct actions_fwd {\n\tu64 actions;\n\tu64 keys;\n\tenum forward_type output;\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct audit_ntp_val {\n\tlong long int oldval;\n\tlong long int newval;\n};\n\nstruct audit_ntp_data {\n\tstruct audit_ntp_val vals[6];\n};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n};\n\nstruct adjust_trip_data {\n\tstruct acpi_thermal *tz;\n\tu32 event;\n};\n\nstruct adreno_smmu_fault_info {\n\tu64 far;\n\tu64 ttbr0;\n\tu32 contextidr;\n\tu32 fsr;\n\tu32 fsynr0;\n\tu32 fsynr1;\n\tu32 cbfrsynra;\n};\n\nstruct io_pgtable_cfg;\n\nstruct adreno_smmu_priv {\n\tconst void *cookie;\n\tconst struct io_pgtable_cfg * (*get_ttbr1_cfg)(const void *);\n\tint (*set_ttbr0_cfg)(const void *, const struct io_pgtable_cfg *);\n\tvoid (*get_fault_info)(const void *, struct adreno_smmu_fault_info *);\n\tvoid (*set_stall)(const void *, bool);\n\tvoid (*resume_translation)(const void *, bool);\n\tvoid (*set_prr_bit)(const void *, bool);\n\tvoid (*set_prr_addr)(const void *, phys_addr_t);\n};\n\nstruct advisor_ctx {\n\tktime_t start_scan;\n\tlong unsigned int scan_time;\n\tlong unsigned int change;\n\tlong long unsigned int cpu_time;\n};\n\nstruct irq_data;\n\nstruct seq_file;\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct pci_bridge_emul_conf {\n\t__le16 vendor;\n\t__le16 device;\n\t__le16 command;\n\t__le16 status;\n\t__le32 class_revision;\n\tu8 cache_line_size;\n\tu8 latency_timer;\n\tu8 header_type;\n\tu8 bist;\n\t__le32 bar[2];\n\tu8 primary_bus;\n\tu8 secondary_bus;\n\tu8 subordinate_bus;\n\tu8 secondary_latency_timer;\n\tu8 iobase;\n\tu8 iolimit;\n\t__le16 secondary_status;\n\t__le16 membase;\n\t__le16 memlimit;\n\t__le16 pref_mem_base;\n\t__le16 pref_mem_limit;\n\t__le32 prefbaseupper;\n\t__le32 preflimitupper;\n\t__le16 iobaseupper;\n\t__le16 iolimitupper;\n\tu8 capabilities_pointer;\n\tu8 reserve[3];\n\t__le32 romaddr;\n\tu8 intline;\n\tu8 intpin;\n\t__le16 bridgectrl;\n};\n\nstruct pci_bridge_emul_pcie_conf {\n\tu8 cap_id;\n\tu8 next;\n\t__le16 cap;\n\t__le32 devcap;\n\t__le16 devctl;\n\t__le16 devsta;\n\t__le32 lnkcap;\n\t__le16 lnkctl;\n\t__le16 lnksta;\n\t__le32 slotcap;\n\t__le16 slotctl;\n\t__le16 slotsta;\n\t__le16 rootctl;\n\t__le16 rootcap;\n\t__le32 rootsta;\n\t__le32 devcap2;\n\t__le16 devctl2;\n\t__le16 devsta2;\n\t__le32 lnkcap2;\n\t__le16 lnkctl2;\n\t__le16 lnksta2;\n\t__le32 slotcap2;\n\t__le16 slotctl2;\n\t__le16 slotsta2;\n};\n\nstruct pci_bridge_emul_ops;\n\nstruct pci_bridge_reg_behavior;\n\nstruct pci_bridge_emul {\n\tstruct pci_bridge_emul_conf conf;\n\tstruct pci_bridge_emul_pcie_conf pcie_conf;\n\tconst struct pci_bridge_emul_ops *ops;\n\tstruct pci_bridge_reg_behavior *pci_regs_behavior;\n\tstruct pci_bridge_reg_behavior *pcie_cap_regs_behavior;\n\tvoid *data;\n\tu8 pcie_start;\n\tu8 ssid_start;\n\tbool has_pcie;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_id;\n};\n\nstruct platform_device;\n\nstruct phy;\n\nstruct advk_pcie {\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tstruct {\n\t\tphys_addr_t match;\n\t\tphys_addr_t remap;\n\t\tphys_addr_t mask;\n\t\tu32 actions;\n\t} wins[8];\n\tu8 wins_count;\n\tstruct irq_domain *rp_irq_domain;\n\tstruct irq_domain *irq_domain;\n\tstruct irq_chip irq_chip;\n\traw_spinlock_t irq_lock;\n\tstruct irq_domain *msi_inner_domain;\n\traw_spinlock_t msi_irq_lock;\n\tlong unsigned int msi_used[1];\n\tstruct mutex msi_used_lock;\n\tint link_gen;\n\tstruct pci_bridge_emul bridge;\n\tstruct gpio_desc *reset_gpio;\n\tstruct phy *phy;\n};\n\nstruct crypto_aead;\n\nstruct aead_request;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tstruct crypto_alg base;\n};\n\nstruct aead_geniv_ctx {\n\tspinlock_t lock;\n\tstruct crypto_aead *child;\n\tu8 salt[0];\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tvoid *__ctx[0];\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tvoid *__ctx[0];\n};\n\nstruct pcie_tlp_log {\n\tunion {\n\t\tu32 dw[14];\n\t\tstruct {\n\t\t\tu32 _do_not_use[4];\n\t\t\tu32 prefix[4];\n\t\t};\n\t};\n\tu8 header_len;\n\tbool flit;\n};\n\nstruct aer_capability_regs {\n\tu32 header;\n\tu32 uncor_status;\n\tu32 uncor_mask;\n\tu32 uncor_severity;\n\tu32 cor_status;\n\tu32 cor_mask;\n\tu32 cap_control;\n\tstruct pcie_tlp_log header_log;\n\tu32 root_command;\n\tu32 root_status;\n\tu16 cor_err_source;\n\tu16 uncor_err_source;\n};\n\nstruct aer_err_info {\n\tstruct pci_dev *dev[5];\n\tint ratelimit_print[5];\n\tint error_dev_num;\n\tconst char *level;\n\tunsigned int id: 16;\n\tunsigned int severity: 2;\n\tunsigned int root_ratelimit_print: 1;\n\tunsigned int __pad1: 4;\n\tunsigned int multi_error_valid: 1;\n\tunsigned int first_error: 5;\n\tunsigned int __pad2: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int tlp_header_valid: 1;\n\tunsigned int status;\n\tunsigned int mask;\n\tstruct pcie_tlp_log tlp;\n};\n\nstruct aer_err_source {\n\tu32 status;\n\tu32 id;\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct aer_info {\n\tu64 dev_cor_errs[16];\n\tu64 dev_fatal_errs[32];\n\tu64 dev_nonfatal_errs[32];\n\tu64 dev_total_cor_errs;\n\tu64 dev_total_fatal_errs;\n\tu64 dev_total_nonfatal_errs;\n\tu64 rootport_total_cor_errs;\n\tu64 rootport_total_fatal_errs;\n\tu64 rootport_total_nonfatal_errs;\n\tstruct ratelimit_state correctable_ratelimit;\n\tstruct ratelimit_state nonfatal_ratelimit;\n};\n\nstruct aer_recover_entry {\n\tu8 bus;\n\tu8 devfn;\n\tu16 domain;\n\tint severity;\n\tstruct aer_capability_regs *regs;\n};\n\nstruct aer_rpc {\n\tstruct pci_dev *rpd;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct aer_err_source *type;\n\t\t\tconst struct aer_err_source *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct aer_err_source *ptr;\n\t\t\tconst struct aer_err_source *ptr_const;\n\t\t};\n\t\tstruct aer_err_source buf[128];\n\t} aer_fifo;\n};\n\nstruct aes_block {\n\tu8 b[16];\n};\n\nunion aes_enckey_arch {\n\tu32 rndkeys[60];\n};\n\nstruct aes_enckey {\n\tu32 len;\n\tu32 nrounds;\n\tu32 padding[2];\n\tunion aes_enckey_arch k;\n};\n\nunion aes_invkey_arch {\n\tu32 inv_rndkeys[60];\n};\n\nstruct aes_key {\n\tstruct aes_enckey;\n\tunion aes_invkey_arch inv_k;\n};\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\ntypedef void (*event_cb_func_t)(const u32 *, void *);\n\nstruct agent_cb {\n\tvoid *agent_data;\n\tevent_cb_func_t eve_cb;\n\tstruct list_head list;\n};\n\nstruct aggregate_control {\n\tlong int *aggregate;\n\tlong int *local;\n\tlong int *pending;\n\tlong int *ppending;\n\tlong int *cstat;\n\tlong int *cstat_prev;\n\tint size;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct agilex5_gate_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int gate_reg;\n\tu8 gate_idx;\n\tlong unsigned int div_reg;\n\tu8 div_offset;\n\tu8 div_width;\n\tlong unsigned int bypass_reg;\n\tu8 bypass_shift;\n\tu8 fixed_div;\n};\n\nstruct agilex5_perip_cnt_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 fixed_divider;\n\tlong unsigned int bypass_reg;\n\tlong unsigned int bypass_shift;\n};\n\nstruct agilex5_pll_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request;\n\nstruct crypto_ahash;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*export_core)(struct ahash_request *, void *);\n\tint (*import_core)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_ahash *);\n\tvoid (*exit_tfm)(struct crypto_ahash *);\n\tint (*clone_tfm)(struct crypto_ahash *, struct crypto_ahash *);\n\tstruct hash_alg_common halg;\n};\n\nstruct ahash_hmac_ctx {\n\tstruct crypto_ahash *hash;\n\tu8 pads[0];\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[112];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tu8 *result;\n\tstruct scatterlist sg_head[2];\n\tcrypto_completion_t saved_complete;\n\tvoid *saved_data;\n\tvoid *__ctx[0];\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\nstruct ata_link;\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct clk_bulk_data;\n\nstruct reset_control;\n\nstruct regulator;\n\nstruct ata_port;\n\nstruct ata_host;\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 mask_port_map;\n\tu32 mask_port_ext;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 saved_port_cap[32];\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tunsigned int n_clks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int f_rsts;\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nstruct ahci_mvebu_plat_data {\n\tint (*plat_config)(struct ahci_host_priv *);\n\tunsigned int flags;\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[15];\n\tchar *irq_desc;\n};\n\nstruct ccsr_ahci;\n\nstruct ahci_qoriq_priv {\n\tstruct ccsr_ahci *reg_base;\n\tenum ahci_qoriq_type type;\n\tvoid *ecc_addr;\n\tbool is_dmacoherent;\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nstruct aic_info {\n\tint version;\n\tu32 event;\n\tu32 target_cpu;\n\tu32 irq_cfg;\n\tu32 sw_set;\n\tu32 sw_clr;\n\tu32 mask_set;\n\tu32 mask_clr;\n\tu32 die_stride;\n\tbool fast_ipi;\n\tbool local_fast_ipi;\n};\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct aic_irq_chip {\n\tvoid *base;\n\tvoid *event;\n\tstruct irq_domain *hw_domain;\n\tstruct {\n\t\tcpumask_t aff;\n\t} *fiq_aff[7];\n\tint nr_irq;\n\tint max_irq;\n\tint nr_die;\n\tint max_die;\n\tstruct aic_info info;\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct clk_core;\n\nstruct clk_init_data;\n\nstruct clk_hw {\n\tstruct clk_core *core;\n\tstruct clk *clk;\n\tconst struct clk_init_data *init;\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct gpd_dev_ops {\n\tint (*start)(struct device *);\n\tint (*stop)(struct device *);\n};\n\nstruct dev_power_governor;\n\nstruct genpd_governor_data;\n\nstruct opp_table;\n\nstruct genpd_power_state;\n\nstruct genpd_lock_ops;\n\nstruct generic_pm_domain {\n\tstruct device dev;\n\tstruct dev_pm_domain domain;\n\tstruct list_head gpd_list_node;\n\tstruct list_head parent_links;\n\tstruct list_head child_links;\n\tstruct list_head dev_list;\n\tstruct dev_power_governor *gov;\n\tstruct genpd_governor_data *gd;\n\tstruct work_struct power_off_work;\n\tstruct fwnode_handle *provider;\n\tbool has_provider;\n\tconst char *name;\n\tatomic_t sd_count;\n\tenum gpd_status status;\n\tunsigned int device_count;\n\tunsigned int device_id;\n\tunsigned int suspended_count;\n\tunsigned int prepared_count;\n\tunsigned int performance_state;\n\tcpumask_var_t cpus;\n\tbool synced_poweroff;\n\tbool stay_on;\n\tenum genpd_sync_state sync_state;\n\tint (*power_off)(struct generic_pm_domain *);\n\tint (*power_on)(struct generic_pm_domain *);\n\tstruct raw_notifier_head power_notifiers;\n\tstruct opp_table *opp_table;\n\tint (*set_performance_state)(struct generic_pm_domain *, unsigned int);\n\tstruct gpd_dev_ops dev_ops;\n\tint (*set_hwmode_dev)(struct generic_pm_domain *, struct device *, bool);\n\tbool (*get_hwmode_dev)(struct generic_pm_domain *, struct device *);\n\tint (*attach_dev)(struct generic_pm_domain *, struct device *);\n\tvoid (*detach_dev)(struct generic_pm_domain *, struct device *);\n\tunsigned int flags;\n\tstruct genpd_power_state *states;\n\tvoid (*free_states)(struct genpd_power_state *, unsigned int);\n\tunsigned int state_count;\n\tunsigned int state_idx;\n\tu64 on_time;\n\tu64 accounting_time;\n\tconst struct genpd_lock_ops *lock_ops;\n\tunion {\n\t\tstruct mutex mlock;\n\t\tstruct {\n\t\t\tspinlock_t slock;\n\t\t\tlong unsigned int lock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_slock;\n\t\t\tlong unsigned int raw_lock_flags;\n\t\t};\n\t};\n};\n\nstruct airoha_cpu_pmdomain_priv {\n\tstruct clk_hw hw;\n\tstruct generic_pm_domain pd;\n};\n\nstruct dev_pm_domain_list;\n\nstruct airoha_cpufreq_priv {\n\tint opp_token;\n\tstruct dev_pm_domain_list *pd_list;\n\tstruct platform_device *cpufreq_dt;\n};\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nunion gpio_irq_fwspec;\n\nstruct gpio_irq_chip {\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *parent_domain;\n\tint (*child_to_parent_hwirq)(struct gpio_chip *, unsigned int, unsigned int, unsigned int *, unsigned int *);\n\tint (*populate_parent_alloc_arg)(struct gpio_chip *, union gpio_irq_fwspec *, unsigned int, unsigned int);\n\tunsigned int (*child_offset_to_irq)(struct gpio_chip *, unsigned int);\n\tstruct irq_domain_ops child_irq_domain_ops;\n\tirq_flow_handler_t handler;\n\tunsigned int default_type;\n\tstruct lock_class_key *lock_key;\n\tstruct lock_class_key *request_key;\n\tirq_flow_handler_t parent_handler;\n\tunion {\n\t\tvoid *parent_handler_data;\n\t\tvoid **parent_handler_data_array;\n\t};\n\tunsigned int num_parents;\n\tunsigned int *parents;\n\tunsigned int *map;\n\tbool threaded;\n\tbool per_parent_data;\n\tbool initialized;\n\tbool domain_is_allocated_externally;\n\tint (*init_hw)(struct gpio_chip *);\n\tvoid (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tlong unsigned int *valid_mask;\n\tunsigned int first;\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n};\n\nstruct gpio_device;\n\nstruct of_phandle_args;\n\nstruct gpio_chip {\n\tconst char *label;\n\tstruct gpio_device *gpiodev;\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tstruct module *owner;\n\tint (*request)(struct gpio_chip *, unsigned int);\n\tvoid (*free)(struct gpio_chip *, unsigned int);\n\tint (*get_direction)(struct gpio_chip *, unsigned int);\n\tint (*direction_input)(struct gpio_chip *, unsigned int);\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tint (*get)(struct gpio_chip *, unsigned int);\n\tint (*get_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n\tint (*set_multiple)(struct gpio_chip *, long unsigned int *, long unsigned int *);\n\tint (*set_config)(struct gpio_chip *, unsigned int, long unsigned int);\n\tint (*to_irq)(struct gpio_chip *, unsigned int);\n\tvoid (*dbg_show)(struct seq_file *, struct gpio_chip *);\n\tint (*init_valid_mask)(struct gpio_chip *, long unsigned int *, unsigned int);\n\tint (*add_pin_ranges)(struct gpio_chip *);\n\tint (*en_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint (*dis_hw_timestamp)(struct gpio_chip *, u32, long unsigned int);\n\tint base;\n\tu16 ngpio;\n\tu16 offset;\n\tconst char * const *names;\n\tbool can_sleep;\n\tstruct gpio_irq_chip irq;\n\tunsigned int of_gpio_n_cells;\n\tbool (*of_node_instance_match)(struct gpio_chip *, unsigned int);\n\tint (*of_xlate)(struct gpio_chip *, const struct of_phandle_args *, u32 *);\n};\n\nstruct gpio_generic_chip {\n\tstruct gpio_chip gc;\n\tlong unsigned int (*read_reg)(void *);\n\tvoid (*write_reg)(void *, long unsigned int);\n\tbool be_bits;\n\tvoid *reg_dat;\n\tvoid *reg_set;\n\tvoid *reg_clr;\n\tvoid *reg_dir_out;\n\tvoid *reg_dir_in;\n\tbool dir_unreadable;\n\tbool pinctrl;\n\tint bits;\n\traw_spinlock_t lock;\n\tlong unsigned int sdata;\n\tlong unsigned int sdir;\n};\n\nstruct airoha_gpio_ctrl {\n\tstruct gpio_generic_chip gen_gc;\n\tvoid *data;\n\tvoid *dir[2];\n\tvoid *output;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct airoha_trng {\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tstruct completion rng_op_done;\n};\n\nstruct akcipher_request;\n\nstruct crypto_akcipher;\n\nstruct akcipher_alg {\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[56];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct al_pcie_acpi {\n\tvoid *dbi_base;\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct alarm_regs {\n\tu32 tmr_alarm1_h;\n\tu32 tmr_alarm1_l;\n\tu32 tmr_alarm2_h;\n\tu32 tmr_alarm2_l;\n};\n\nstruct ale_control_info {\n\tconst char *name;\n\tint offset;\n\tint port_offset;\n\tint shift;\n\tint port_shift;\n\tint bits;\n};\n\nstruct ale_entry_fld {\n\tu8 start_bit;\n\tu8 num_bits;\n\tu8 flags;\n};\n\nstruct alert_data {\n\tshort unsigned int addr;\n\tenum i2c_alert_protocol type;\n\tunsigned int data;\n};\n\nstruct alias_prop {\n\tstruct list_head link;\n\tconst char *alias;\n\tstruct device_node *np;\n\tint id;\n\tchar stem[0];\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alpha_pll_config {\n\tu32 l;\n\tu32 cal_l;\n\tu32 alpha;\n\tu32 alpha_hi;\n\tu32 config_ctl_val;\n\tu32 config_ctl_hi_val;\n\tu32 config_ctl_hi1_val;\n\tu32 config_ctl_hi2_val;\n\tu32 user_ctl_val;\n\tu32 user_ctl_hi_val;\n\tu32 user_ctl_hi1_val;\n\tu32 test_ctl_val;\n\tu32 test_ctl_mask;\n\tu32 test_ctl_hi_val;\n\tu32 test_ctl_hi_mask;\n\tu32 test_ctl_hi1_val;\n\tu32 test_ctl_hi2_val;\n\tu32 test_ctl_hi3_val;\n\tu32 main_output_mask;\n\tu32 aux_output_mask;\n\tu32 aux2_output_mask;\n\tu32 early_output_mask;\n\tu32 alpha_en_mask;\n\tu32 alpha_mode_mask;\n\tu32 pre_div_val;\n\tu32 pre_div_mask;\n\tu32 post_div_val;\n\tu32 post_div_mask;\n\tu32 vco_val;\n\tu32 vco_mask;\n\tu32 status_val;\n\tu32 status_mask;\n\tu32 lock_det;\n};\n\nstruct alpine_msix_data {\n\tspinlock_t msi_map_lock;\n\tphys_addr_t addr;\n\tu32 spi_first;\n\tu32 num_spis;\n\tlong unsigned int *msi_map;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct psmouse;\n\nstruct alps_nibble_commands;\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct alt_instr {\n\ts32 orig_offset;\n\ts32 alt_offset;\n\tu16 cpucap;\n\tu8 orig_len;\n\tu8 alt_len;\n};\n\nstruct alt_region {\n\tstruct alt_instr *begin;\n\tstruct alt_instr *end;\n};\n\nstruct altera_msi {\n\tlong unsigned int used[1];\n\tstruct mutex lock;\n\tstruct platform_device *pdev;\n\tstruct irq_domain *inner_domain;\n\tvoid *csr_base;\n\tvoid *vector_base;\n\tphys_addr_t vector_phy;\n\tu32 num_of_vectors;\n\tint irq;\n};\n\nstruct altera_pcie_data;\n\nstruct altera_pcie {\n\tstruct platform_device *pdev;\n\tvoid *cra_base;\n\tvoid *hip_base;\n\tint irq;\n\tu8 root_bus_nr;\n\tstruct irq_domain *irq_domain;\n\tstruct resource bus_range;\n\tconst struct altera_pcie_data *pcie_data;\n};\n\nstruct altera_pcie_ops;\n\nstruct altera_pcie_data {\n\tconst struct altera_pcie_ops *ops;\n\tenum altera_pcie_version version;\n\tu32 cap_offset;\n\tu32 cfgrd0;\n\tu32 cfgrd1;\n\tu32 cfgwr0;\n\tu32 cfgwr1;\n\tu32 port_conf_offset;\n\tu32 port_irq_status_offset;\n\tu32 port_irq_enable_offset;\n};\n\nstruct altera_pcie_ops {\n\tint (*tlp_read_pkt)(struct altera_pcie *, u32 *);\n\tvoid (*tlp_write_pkt)(struct altera_pcie *, u32 *, u32, bool);\n\tbool (*get_link_status)(struct altera_pcie *);\n\tint (*rp_read_cfg)(struct altera_pcie *, int, int, u32 *);\n\tint (*rp_write_cfg)(struct altera_pcie *, u8, int, int, u32);\n\tint (*ep_read_cfg)(struct altera_pcie *, u8, unsigned int, int, int, u32 *);\n\tint (*ep_write_cfg)(struct altera_pcie *, u8, unsigned int, int, int, u32);\n\tvoid (*rp_isr)(struct irq_desc *);\n};\n\nstruct regmap;\n\nstruct altr_sysmgr {\n\tstruct regmap *regmap;\n};\n\nstruct am65_cpsw_ale_ratelimit {\n\tlong unsigned int cookie;\n\tu64 rate_packet_ps;\n};\n\nstruct am65_cpsw_pdata {\n\tu32 quirks;\n\tu64 extra_modes;\n\tenum k3_ring_mode fdqring_mode;\n\tconst char *ale_dev_id;\n};\n\nstruct am65_cpsw_common;\n\nstruct am65_cpsw_host {\n\tstruct am65_cpsw_common *common;\n\tvoid *port_base;\n\tvoid *stat_base;\n\tu32 vid_context;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct napi_config;\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n};\n\nstruct k3_cppi_desc_pool;\n\nstruct k3_udma_glue_tx_channel;\n\nstruct am65_cpsw_tx_chn {\n\tstruct device *dma_dev;\n\tstruct napi_struct napi_tx;\n\tstruct am65_cpsw_common *common;\n\tstruct k3_cppi_desc_pool *desc_pool;\n\tstruct k3_udma_glue_tx_channel *tx_chn;\n\tspinlock_t lock;\n\tstruct hrtimer tx_hrtimer;\n\tlong unsigned int tx_pace_timeout;\n\tint irq;\n\tu32 id;\n\tu32 descs_num;\n\tunsigned char dsize_log2;\n\tchar tx_chn_name[128];\n\tu32 rate_mbps;\n};\n\nstruct page_pool;\n\nstruct am65_cpsw_rx_flow {\n\tu32 id;\n\tstruct napi_struct napi_rx;\n\tstruct am65_cpsw_common *common;\n\tint irq;\n\tbool irq_disabled;\n\tstruct hrtimer rx_hrtimer;\n\tlong unsigned int rx_pace_timeout;\n\tstruct page_pool *page_pool;\n\tchar name[32];\n};\n\nstruct k3_udma_glue_rx_channel;\n\nstruct am65_cpsw_rx_chn {\n\tstruct device *dev;\n\tstruct device *dma_dev;\n\tstruct k3_cppi_desc_pool *desc_pool;\n\tstruct k3_udma_glue_rx_channel *rx_chn;\n\tu32 descs_num;\n\tunsigned char dsize_log2;\n\tstruct am65_cpsw_rx_flow flows[8];\n};\n\nstruct am65_cpts;\n\nstruct am65_cpsw_port;\n\nstruct cpsw_ale;\n\nstruct devlink;\n\nstruct am65_cpsw_common {\n\tstruct device *dev;\n\tstruct device *mdio_dev;\n\tstruct am65_cpsw_pdata pdata;\n\tvoid *ss_base;\n\tvoid *cpsw_base;\n\tu32 port_num;\n\tstruct am65_cpsw_host host;\n\tstruct am65_cpsw_port *ports;\n\tu32 disabled_ports_mask;\n\tstruct net_device *dma_ndev;\n\tint usage_count;\n\tstruct cpsw_ale *ale;\n\tint tx_ch_num;\n\tu32 tx_ch_rate_msk;\n\tu32 rx_flow_id_base;\n\tstruct am65_cpsw_tx_chn tx_chns[8];\n\tstruct completion tdown_complete;\n\tatomic_t tdown_cnt;\n\tint rx_ch_num_flows;\n\tstruct am65_cpsw_rx_chn rx_chns;\n\tu32 nuss_ver;\n\tu32 cpsw_ver;\n\tlong unsigned int bus_freq;\n\tbool pf_p0_rx_ptype_rrobin;\n\tstruct am65_cpts *cpts;\n\tint est_enabled;\n\tbool iet_enabled;\n\tbool is_emac_mode;\n\tu16 br_members;\n\tint default_vlan;\n\tstruct devlink *devlink;\n\tstruct net_device *hw_bridge_dev;\n\tstruct notifier_block am65_cpsw_netdevice_nb;\n\tunsigned char switch_id[32];\n\tu32 *ale_context;\n};\n\nstruct am65_cpsw_devlink {\n\tstruct am65_cpsw_common *common;\n};\n\nstruct tc_taprio_qopt_stats {\n\tu64 window_drops;\n\tu64 tx_overruns;\n};\n\nstruct tc_taprio_qopt_queue_stats {\n\tint queue;\n\tstruct tc_taprio_qopt_stats stats;\n};\n\nstruct tc_mqprio_qopt {\n\t__u8 num_tc;\n\t__u8 prio_tc_map[16];\n\t__u8 hw;\n\t__u16 count[16];\n\t__u16 offset[16];\n};\n\nstruct tc_mqprio_qopt_offload {\n\tstruct tc_mqprio_qopt qopt;\n\tstruct netlink_ext_ack *extack;\n\tu16 mode;\n\tu16 shaper;\n\tu32 flags;\n\tu64 min_rate[16];\n\tu64 max_rate[16];\n\tlong unsigned int preemptible_tcs;\n};\n\nstruct tc_taprio_sched_entry {\n\tu8 command;\n\tu32 gate_mask;\n\tu32 interval;\n};\n\nstruct tc_taprio_qopt_offload {\n\tenum tc_taprio_qopt_cmd cmd;\n\tunion {\n\t\tstruct tc_taprio_qopt_stats stats;\n\t\tstruct tc_taprio_qopt_queue_stats queue_stats;\n\t\tstruct {\n\t\t\tstruct tc_mqprio_qopt_offload mqprio;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t\tktime_t base_time;\n\t\t\tu64 cycle_time;\n\t\t\tu64 cycle_time_extension;\n\t\t\tu32 max_sdu[16];\n\t\t\tsize_t num_entries;\n\t\t\tstruct tc_taprio_sched_entry entries[0];\n\t\t};\n\t};\n};\n\nstruct am65_cpsw_est {\n\tint buf;\n\tstruct tc_taprio_qopt_offload taprio;\n};\n\nstruct am65_cpsw_ethtool_stat {\n\tchar desc[32];\n\tint offset;\n};\n\nstruct am65_cpsw_iet {\n\tu8 preemptible_tcs;\n\tu32 original_max_blks;\n\tint verify_time_ms;\n};\n\nstruct am65_cpsw_mqprio {\n\tstruct tc_mqprio_qopt_offload mqprio_hw;\n\tu64 max_rate_total;\n\tbool shaper_en;\n};\n\nstruct am65_cpsw_ndev_priv {\n\tu32 msg_enable;\n\tstruct am65_cpsw_port *port;\n\tbool offload_fwd_mark;\n\tstruct mutex mm_lock;\n};\n\nstruct phylink_link_state;\n\nstruct phylink_config {\n\tstruct device *dev;\n\tenum phylink_op_type type;\n\tbool poll_fixed_state;\n\tbool mac_managed_pm;\n\tbool mac_requires_rxc;\n\tbool default_an_inband;\n\tbool eee_rx_clk_stop_enable;\n\tvoid (*get_fixed_state)(struct phylink_config *, struct phylink_link_state *);\n\tlong unsigned int supported_interfaces[1];\n\tlong unsigned int lpi_interfaces[1];\n\tlong unsigned int mac_capabilities;\n\tlong unsigned int lpi_capabilities;\n\tu32 lpi_timer_default;\n\tbool eee_enabled_default;\n\tbool wol_phy_legacy;\n\tbool wol_phy_speed_ctrl;\n\tu32 wol_mac_support;\n};\n\nstruct cpsw_sl;\n\nstruct phylink;\n\nstruct am65_cpsw_slave_data {\n\tbool mac_only;\n\tstruct cpsw_sl *mac_sl;\n\tstruct device_node *port_np;\n\tphy_interface_t phy_if;\n\tstruct phy *ifphy;\n\tstruct phy *serdes_phy;\n\tbool rx_pause;\n\tbool tx_pause;\n\tu8 mac_addr[6];\n\tint port_vlan;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n};\n\nstruct am65_cpsw_qos {\n\tstruct am65_cpsw_est *est_admin;\n\tstruct am65_cpsw_est *est_oper;\n\tktime_t link_down_time;\n\tint link_speed;\n\tstruct am65_cpsw_mqprio mqprio;\n\tstruct am65_cpsw_iet iet;\n\tstruct am65_cpsw_ale_ratelimit ale_bc_ratelimit;\n\tstruct am65_cpsw_ale_ratelimit ale_mc_ratelimit;\n};\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_port_ops;\n\nstruct ib_device;\n\nstruct devlink_rate;\n\nstruct devlink_linecard;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_prog;\n\nstruct am65_cpsw_port {\n\tstruct am65_cpsw_common *common;\n\tstruct net_device *ndev;\n\tconst char *name;\n\tu32 port_id;\n\tvoid *port_base;\n\tvoid *sgmii_base;\n\tvoid *stat_base;\n\tvoid *fetch_ram_base;\n\tbool disabled;\n\tstruct am65_cpsw_slave_data slave;\n\tbool tx_ts_enabled;\n\tbool rx_ts_enabled;\n\tstruct am65_cpsw_qos qos;\n\tstruct devlink_port devlink_port;\n\tstruct bpf_prog *xdp_prog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq[8];\n\tu32 vid_context;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct am65_cpsw_regdump_hdr {\n\tu32 module_id;\n\tu32 len;\n};\n\nstruct am65_cpsw_regdump_item {\n\tstruct am65_cpsw_regdump_hdr hdr;\n\tu32 start_ofs;\n\tu32 end_ofs;\n};\n\nstruct am65_cpsw_soc_pdata {\n\tu32 quirks_dis;\n};\n\nstruct am65_cpsw_stats_regs {\n\tu32 rx_good_frames;\n\tu32 rx_broadcast_frames;\n\tu32 rx_multicast_frames;\n\tu32 rx_pause_frames;\n\tu32 rx_crc_errors;\n\tu32 rx_align_code_errors;\n\tu32 rx_oversized_frames;\n\tu32 rx_jabber_frames;\n\tu32 rx_undersized_frames;\n\tu32 rx_fragments;\n\tu32 ale_drop;\n\tu32 ale_overrun_drop;\n\tu32 rx_octets;\n\tu32 tx_good_frames;\n\tu32 tx_broadcast_frames;\n\tu32 tx_multicast_frames;\n\tu32 tx_pause_frames;\n\tu32 tx_deferred_frames;\n\tu32 tx_collision_frames;\n\tu32 tx_single_coll_frames;\n\tu32 tx_mult_coll_frames;\n\tu32 tx_excessive_collisions;\n\tu32 tx_late_collisions;\n\tu32 rx_ipg_error;\n\tu32 tx_carrier_sense_errors;\n\tu32 tx_octets;\n\tu32 tx_64B_frames;\n\tu32 tx_65_to_127B_frames;\n\tu32 tx_128_to_255B_frames;\n\tu32 tx_256_to_511B_frames;\n\tu32 tx_512_to_1023B_frames;\n\tu32 tx_1024B_frames;\n\tu32 net_octets;\n\tu32 rx_bottom_fifo_drop;\n\tu32 rx_port_mask_drop;\n\tu32 rx_top_fifo_drop;\n\tu32 ale_rate_limit_drop;\n\tu32 ale_vid_ingress_drop;\n\tu32 ale_da_eq_sa_drop;\n\tu32 ale_block_drop;\n\tu32 ale_secure_drop;\n\tu32 ale_auth_drop;\n\tu32 ale_unknown_ucast;\n\tu32 ale_unknown_ucast_bytes;\n\tu32 ale_unknown_mcast;\n\tu32 ale_unknown_mcast_bytes;\n\tu32 ale_unknown_bcast;\n\tu32 ale_unknown_bcast_bytes;\n\tu32 ale_pol_match;\n\tu32 ale_pol_match_red;\n\tu32 ale_pol_match_yellow;\n\tu32 ale_mcast_sa_drop;\n\tu32 ale_dual_vlan_drop;\n\tu32 ale_len_err_drop;\n\tu32 ale_ip_next_hdr_drop;\n\tu32 ale_ipv4_frag_drop;\n\tu32 __rsvd_1[24];\n\tu32 iet_rx_assembly_err;\n\tu32 iet_rx_assembly_ok;\n\tu32 iet_rx_smd_err;\n\tu32 iet_rx_frag;\n\tu32 iet_tx_hold;\n\tu32 iet_tx_frag;\n\tu32 __rsvd_2[9];\n\tu32 tx_mem_protect_err;\n\tu32 tx_pri0;\n\tu32 tx_pri1;\n\tu32 tx_pri2;\n\tu32 tx_pri3;\n\tu32 tx_pri4;\n\tu32 tx_pri5;\n\tu32 tx_pri6;\n\tu32 tx_pri7;\n\tu32 tx_pri0_bcnt;\n\tu32 tx_pri1_bcnt;\n\tu32 tx_pri2_bcnt;\n\tu32 tx_pri3_bcnt;\n\tu32 tx_pri4_bcnt;\n\tu32 tx_pri5_bcnt;\n\tu32 tx_pri6_bcnt;\n\tu32 tx_pri7_bcnt;\n\tu32 tx_pri0_drop;\n\tu32 tx_pri1_drop;\n\tu32 tx_pri2_drop;\n\tu32 tx_pri3_drop;\n\tu32 tx_pri4_drop;\n\tu32 tx_pri5_drop;\n\tu32 tx_pri6_drop;\n\tu32 tx_pri7_drop;\n\tu32 tx_pri0_drop_bcnt;\n\tu32 tx_pri1_drop_bcnt;\n\tu32 tx_pri2_drop_bcnt;\n\tu32 tx_pri3_drop_bcnt;\n\tu32 tx_pri4_drop_bcnt;\n\tu32 tx_pri5_drop_bcnt;\n\tu32 tx_pri6_drop_bcnt;\n\tu32 tx_pri7_drop_bcnt;\n};\n\nstruct page;\n\nstruct am65_cpsw_swdata {\n\tu32 flow_id;\n\tstruct page *page;\n};\n\nstruct xdp_frame;\n\nstruct am65_cpsw_tx_swdata {\n\tstruct net_device *ndev;\n\tunion {\n\t\tstruct sk_buff *skb;\n\t\tstruct xdp_frame *xdpf;\n\t};\n};\n\nstruct amba_cs_uci_id {\n\tunsigned int devarch;\n\tunsigned int devarch_mask;\n\tunsigned int devtype;\n\tvoid *data;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct amba_device {\n\tstruct device dev;\n\tstruct resource res;\n\tstruct clk *pclk;\n\tstruct device_dma_parameters dma_parms;\n\tunsigned int periphid;\n\tstruct mutex periphid_lock;\n\tunsigned int cid;\n\tstruct amba_cs_uci_id uci;\n\tunsigned int irq[9];\n\tconst char *driver_override;\n};\n\nstruct amba_id;\n\nstruct amba_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct amba_device *, const struct amba_id *);\n\tvoid (*remove)(struct amba_device *);\n\tvoid (*shutdown)(struct amba_device *);\n\tconst struct amba_id *id_table;\n\tbool driver_managed_dma;\n};\n\nstruct amba_id {\n\tunsigned int id;\n\tunsigned int mask;\n\tvoid *data;\n};\n\nstruct serio;\n\nstruct amba_kmi_port {\n\tstruct serio *io;\n\tstruct clk *clk;\n\tvoid *base;\n\tunsigned int irq;\n\tunsigned int divisor;\n\tunsigned int open;\n};\n\nstruct amba_pl011_data {\n\tbool (*dma_filter)(struct dma_chan *, void *);\n\tvoid *dma_rx_param;\n\tvoid *dma_tx_param;\n\tbool dma_rx_poll_enable;\n\tunsigned int dma_rx_poll_rate;\n\tunsigned int dma_rx_poll_timeout;\n\tvoid (*init)(void);\n\tvoid (*exit)(void);\n};\n\nstruct amd_sdhci_host {\n\tbool tuned_clock;\n\tbool dll_enabled;\n};\n\nstruct aml_pio_control {\n\tu32 gpio_offset;\n\tu32 reg_offset[6];\n\tu32 bit_offset[6];\n};\n\nstruct multi_mux;\n\nstruct aml_gpio_bank {\n\tstruct gpio_chip gpio_chip;\n\tstruct aml_pio_control pc;\n\tu32 bank_id;\n\tu32 mux_bit_offs;\n\tunsigned int pin_base;\n\tstruct regmap *reg_mux;\n\tstruct regmap *reg_gpio;\n\tstruct regmap *reg_ds;\n\tconst struct multi_mux *p_mux;\n};\n\nstruct aml_pctl_data {\n\tunsigned int number;\n\tconst struct multi_mux *p_mux;\n};\n\nstruct aml_pctl_group {\n\tconst char *name;\n\tunsigned int npins;\n\tunsigned int *pins;\n\tunsigned int *func;\n};\n\nstruct pinctrl_dev;\n\nstruct aml_pmx_func;\n\nstruct aml_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct aml_gpio_bank *banks;\n\tint nbanks;\n\tstruct aml_pmx_func *functions;\n\tint nfunctions;\n\tstruct aml_pctl_group *groups;\n\tint ngroups;\n\tconst struct aml_pctl_data *data;\n};\n\nstruct aml_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct aml_resource_small_header {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_large_header {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_irq {\n\tu8 descriptor_type;\n\tu16 irq_mask;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct aml_resource_dma {\n\tu8 descriptor_type;\n\tu8 dma_channel_mask;\n\tu8 flags;\n};\n\nstruct aml_resource_start_dependent {\n\tu8 descriptor_type;\n\tu8 flags;\n};\n\nstruct aml_resource_end_dependent {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_io {\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu8 alignment;\n\tu8 address_length;\n};\n\nstruct aml_resource_fixed_io {\n\tu8 descriptor_type;\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_dma {\n\tu8 descriptor_type;\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_small {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_end_tag {\n\tu8 descriptor_type;\n\tu8 checksum;\n};\n\nstruct aml_resource_memory24 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_generic_register {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 address_space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_large {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address16 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_extended_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu8 revision_ID;\n\tu8 reserved;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct aml_resource_extended_irq {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu8 interrupt_count;\n\tunion {\n\t\tu32 interrupt;\n\t\tstruct {\n\t\t\tstruct {} __Empty_interrupts;\n\t\t\tu32 interrupts[0];\n\t\t};\n\t};\n} __attribute__((packed));\n\nstruct aml_resource_gpio {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 connection_type;\n\tu16 flags;\n\tu16 int_flags;\n\tu8 pin_config;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_i2c_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu16 slave_address;\n} __attribute__((packed));\n\nstruct aml_resource_spi_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n} __attribute__((packed));\n\nstruct aml_resource_uart_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 default_baud_rate;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu8 parity;\n\tu8 lines_enabled;\n} __attribute__((packed));\n\nstruct aml_resource_csi2_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_common_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config;\n\tu16 function_number;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 pin_table_offset;\n\tu16 label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 function_number;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_clock_input {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 frequency_divisor;\n\tu32 frequency_numerator;\n} __attribute__((packed));\n\nstruct aml_resource_address {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n} __attribute__((packed));\n\nunion aml_resource {\n\tu8 descriptor_type;\n\tstruct aml_resource_small_header small_header;\n\tstruct aml_resource_large_header large_header;\n\tstruct aml_resource_irq irq;\n\tstruct aml_resource_dma dma;\n\tstruct aml_resource_start_dependent start_dpf;\n\tstruct aml_resource_end_dependent end_dpf;\n\tstruct aml_resource_io io;\n\tstruct aml_resource_fixed_io fixed_io;\n\tstruct aml_resource_fixed_dma fixed_dma;\n\tstruct aml_resource_vendor_small vendor_small;\n\tstruct aml_resource_end_tag end_tag;\n\tstruct aml_resource_memory24 memory24;\n\tstruct aml_resource_generic_register generic_reg;\n\tstruct aml_resource_vendor_large vendor_large;\n\tstruct aml_resource_memory32 memory32;\n\tstruct aml_resource_fixed_memory32 fixed_memory32;\n\tstruct aml_resource_address16 address16;\n\tstruct aml_resource_address32 address32;\n\tstruct aml_resource_address64 address64;\n\tstruct aml_resource_extended_address64 ext_address64;\n\tstruct aml_resource_extended_irq extended_irq;\n\tstruct aml_resource_gpio gpio;\n\tstruct aml_resource_i2c_serialbus i2c_serial_bus;\n\tstruct aml_resource_spi_serialbus spi_serial_bus;\n\tstruct aml_resource_uart_serialbus uart_serial_bus;\n\tstruct aml_resource_csi2_serialbus csi2_serial_bus;\n\tstruct aml_resource_common_serialbus common_serial_bus;\n\tstruct aml_resource_pin_function pin_function;\n\tstruct aml_resource_pin_config pin_config;\n\tstruct aml_resource_pin_group pin_group;\n\tstruct aml_resource_pin_group_function pin_group_function;\n\tstruct aml_resource_pin_group_config pin_group_config;\n\tstruct aml_resource_clock_input clock_input;\n\tstruct aml_resource_address address;\n\tu32 dword_item;\n\tu16 word_item;\n\tu8 byte_item;\n};\n\nstruct aml_rtc_config {\n\tbool gray_stored;\n};\n\nstruct rtc_device;\n\nstruct aml_rtc_data {\n\tstruct regmap *map;\n\tstruct rtc_device *rtc_dev;\n\tint irq;\n\tstruct clk *rtc_clk;\n\tstruct clk *sys_clk;\n\tint rtc_enabled;\n\tconst struct aml_rtc_config *config;\n};\n\nstruct amlogic_thermal_data;\n\nstruct amlogic_thermal {\n\tstruct platform_device *pdev;\n\tconst struct amlogic_thermal_data *data;\n\tstruct regmap *regmap;\n\tstruct regmap *sec_ao_map;\n\tstruct clk *clk;\n\tstruct thermal_zone_device *tzd;\n\tu32 trim_info;\n};\n\nstruct amlogic_thermal_soc_calib_data;\n\nstruct regmap_config;\n\nstruct amlogic_thermal_data {\n\tint u_efuse_off;\n\tconst struct amlogic_thermal_soc_calib_data *calibration_parameters;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct amlogic_thermal_soc_calib_data {\n\tint A;\n\tint B;\n\tint m;\n\tint n;\n};\n\nstruct amu_cntr_sample {\n\tu64 arch_const_cycles_prev;\n\tu64 arch_core_cycles_prev;\n\tlong unsigned int last_scale_update;\n};\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct ap_list_summary {\n\tunsigned int nr_pend;\n\tunsigned int nr_act;\n\tunsigned int nr_sgi;\n};\n\nstruct ap_reset_log_entry {\n\tuint16_t reset_cause;\n\tuint16_t reserved;\n\tuint32_t reset_time_ms;\n};\n\nstruct apd_private_data;\n\nstruct apd_device_desc {\n\tunsigned int fixed_clk_rate;\n\tstruct property_entry *properties;\n\tint (*setup)(struct apd_private_data *);\n};\n\nstruct apd_private_data {\n\tstruct clk *clk;\n\tstruct acpi_device *adev;\n\tconst struct apd_device_desc *dev_desc;\n};\n\nstruct apei_exec_ins_type;\n\nstruct apei_exec_context {\n\tu32 ip;\n\tu64 value;\n\tu64 var1;\n\tu64 var2;\n\tu64 src_base;\n\tu64 dst_base;\n\tstruct apei_exec_ins_type *ins_table;\n\tu32 instructions;\n\tstruct acpi_whea_header *action_table;\n\tu32 entries;\n};\n\ntypedef int (*apei_exec_ins_func_t)(struct apei_exec_context *, struct acpi_whea_header *);\n\nstruct apei_exec_ins_type {\n\tu32 flags;\n\tapei_exec_ins_func_t run;\n};\n\nstruct apei_res {\n\tstruct list_head list;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct apei_resources {\n\tstruct list_head iomem;\n\tstruct list_head ioport;\n};\n\nstruct aperture_range {\n\tstruct device *dev;\n\tresource_size_t base;\n\tresource_size_t size;\n\tstruct list_head lh;\n\tvoid (*detach)(struct device *);\n};\n\nstruct api_context {\n\tstruct completion done;\n\tint status;\n};\n\nstruct apid_data {\n\tu16 ppid;\n\tu8 write_ee;\n\tu8 irq_ee;\n};\n\nstruct apple_backlight_config_report {\n\tu8 report_id;\n\tu8 version;\n\tu16 backlight_off;\n\tu16 backlight_on_min;\n\tu16 backlight_on_max;\n};\n\nstruct apple_backlight_set_report {\n\tu8 report_id;\n\tu8 version;\n\tu16 backlight;\n\tu16 rate;\n};\n\nstruct apple_key_translation {\n\tu16 from;\n\tu16 to;\n\tlong unsigned int flags;\n};\n\nstruct led_pattern;\n\nstruct led_trigger;\n\nstruct led_hw_trigger_type;\n\nstruct led_classdev {\n\tconst char *name;\n\tunsigned int brightness;\n\tunsigned int max_brightness;\n\tunsigned int color;\n\tint flags;\n\tlong unsigned int work_flags;\n\tvoid (*brightness_set)(struct led_classdev *, enum led_brightness);\n\tint (*brightness_set_blocking)(struct led_classdev *, enum led_brightness);\n\tenum led_brightness (*brightness_get)(struct led_classdev *);\n\tint (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *);\n\tint (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int);\n\tint (*pattern_clear)(struct led_classdev *);\n\tstruct device *dev;\n\tconst struct attribute_group **groups;\n\tstruct list_head node;\n\tconst char *default_trigger;\n\tlong unsigned int blink_delay_on;\n\tlong unsigned int blink_delay_off;\n\tstruct timer_list blink_timer;\n\tint blink_brightness;\n\tint new_blink_brightness;\n\tvoid (*flash_resume)(struct led_classdev *);\n\tstruct workqueue_struct *wq;\n\tstruct work_struct set_brightness_work;\n\tint delayed_set_value;\n\tlong unsigned int delayed_delay_on;\n\tlong unsigned int delayed_delay_off;\n\tstruct rw_semaphore trigger_lock;\n\tstruct led_trigger *trigger;\n\tstruct list_head trig_list;\n\tvoid *trigger_data;\n\tbool activated;\n\tstruct led_hw_trigger_type *trigger_type;\n\tconst char *hw_control_trigger;\n\tint (*hw_control_is_supported)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_set)(struct led_classdev *, long unsigned int);\n\tint (*hw_control_get)(struct led_classdev *, long unsigned int *);\n\tstruct device * (*hw_control_get_device)(struct led_classdev *);\n\tstruct mutex led_access;\n};\n\nstruct hid_report;\n\nstruct apple_magic_backlight {\n\tstruct led_classdev cdev;\n\tstruct hid_report *brightness;\n\tstruct hid_report *power;\n};\n\nstruct apple_non_apple_keyboard {\n\tchar *name;\n};\n\nstruct reset_control_ops;\n\nstruct reset_controller_dev {\n\tconst struct reset_control_ops *ops;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct list_head reset_control_head;\n\tstruct device *dev;\n\tstruct device_node *of_node;\n\tconst struct of_phandle_args *of_args;\n\tint of_reset_n_cells;\n\tint (*of_xlate)(struct reset_controller_dev *, const struct of_phandle_args *);\n\tunsigned int nr_resets;\n};\n\nstruct apple_pmgr_ps {\n\tstruct device *dev;\n\tstruct generic_pm_domain genpd;\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *regmap;\n\tu32 offset;\n\tu32 min_state;\n};\n\nstruct hid_device;\n\nstruct apple_sc_backlight;\n\nstruct apple_sc {\n\tstruct hid_device *hdev;\n\tlong unsigned int quirks;\n\tunsigned int fn_on;\n\tunsigned int fn_found;\n\tlong unsigned int pressed_numlock[12];\n\tstruct timer_list battery_timer;\n\tstruct apple_sc_backlight *backlight;\n};\n\nstruct apple_sc_backlight {\n\tstruct led_classdev cdev;\n\tstruct hid_device *hdev;\n};\n\nstruct apply_range_data {\n\tstruct page **pages;\n\tint i;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct clk_alpha_pll;\n\nstruct apss_pll_data {\n\tint pll_type;\n\tstruct clk_alpha_pll *pll;\n\tconst struct alpha_pll_config *pll_config;\n};\n\nstruct aqr107_hw_stat {\n\tconst char *name;\n\tint reg;\n\tint size;\n};\n\nstruct aqr_global_syscfg {\n\tint speed;\n\tphy_interface_t interface;\n\tenum aqr_rate_adaptation rate_adapt;\n};\n\nstruct aqr107_priv {\n\tu64 sgmii_stats[10];\n\tu64 fingerprint;\n\tlong unsigned int leds_active_low;\n\tlong unsigned int leds_active_high;\n\tbool wait_on_global_cfg;\n\tstruct aqr_global_syscfg global_cfg[6];\n};\n\nstruct arch_elf_state {\n\tint flags;\n};\n\nstruct arch_hibernate_hdr_invariants {\n\tchar uts_version[65];\n};\n\nstruct arch_hibernate_hdr {\n\tstruct arch_hibernate_hdr_invariants invariants;\n\tphys_addr_t ttbr1_el1;\n\tvoid (*reenter_kernel)(void);\n\tphys_addr_t __hyp_stub_vectors;\n\tu64 sleep_cpu_mpidr;\n};\n\nstruct arch_hw_breakpoint_ctrl {\n\tu32 __reserved: 19;\n\tu32 len: 8;\n\tu32 type: 2;\n\tu32 privilege: 2;\n\tu32 enabled: 1;\n};\n\nstruct arch_hw_breakpoint {\n\tu64 address;\n\tu64 trigger;\n\tstruct arch_hw_breakpoint_ctrl ctrl;\n};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct arch_msi_msg_addr_hi {\n\tu32 address_hi;\n};\n\ntypedef struct arch_msi_msg_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct arch_msi_msg_addr_lo {\n\tu32 address_lo;\n};\n\ntypedef struct arch_msi_msg_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct arch_msi_msg_data {\n\tu32 data;\n};\n\ntypedef struct arch_msi_msg_data arch_msi_msg_data_t;\n\ntypedef void probes_handler_t(u32, long int, struct pt_regs *);\n\nstruct arch_probe_insn {\n\tprobes_handler_t *handler;\n};\n\nstruct arch_shared_info {};\n\nstruct arch_specific_insn {\n\tint dummy;\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct module *owner;\n};\n\nstruct arch_timer_mem;\n\nstruct arch_timer {\n\tstruct clock_event_device evt;\n\tstruct clocksource cs;\n\tstruct arch_timer_mem *gt_block;\n\tvoid *base;\n\tenum arch_timer_access access;\n\tu32 rate;\n};\n\nstruct arch_timer_offset {\n\tu64 *vm_offset;\n\tu64 *vcpu_offset;\n};\n\nstruct arch_timer_context {\n\tstruct hrtimer hrtimer;\n\tu64 ns_frac;\n\tstruct arch_timer_offset offset;\n\tbool loaded;\n\tstruct {\n\t\tbool level;\n\t} irq;\n\tenum kvm_arch_timers timer_id;\n\tu32 host_timer_irq;\n};\n\nstruct arch_timer_cpu {\n\tstruct arch_timer_context timers[4];\n\tstruct hrtimer bg_timer;\n\tbool enabled;\n};\n\nstruct arch_timer_erratum_workaround {\n\tenum arch_timer_erratum_match_type match_type;\n\tconst void *id;\n\tconst char *desc;\n\tu64 (*read_cntpct_el0)(void);\n\tu64 (*read_cntvct_el0)(void);\n\tint (*set_next_event_phys)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_event_virt)(long unsigned int, struct clock_event_device *);\n\tbool disable_compat_vdso;\n};\n\nstruct cyclecounter;\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct arch_timer_kvm_info {\n\tstruct timecounter timecounter;\n\tint virtual_irq;\n\tint physical_irq;\n};\n\nstruct arch_timer_mem_frame {\n\tbool valid;\n\tphys_addr_t cntbase;\n\tsize_t size;\n\tint phys_irq;\n\tint virt_irq;\n};\n\nstruct arch_timer_mem {\n\tphys_addr_t cntctlbase;\n\tsize_t size;\n\tstruct arch_timer_mem_frame frame[8];\n};\n\nstruct arch_timer_vm_data {\n\tu64 voffset;\n\tu64 poffset;\n\tu8 ppi[4];\n};\n\nstruct arch_tlbflush_unmap_batch {};\n\nstruct arch_uprobe {\n\tunion {\n\t\t__le32 insn;\n\t\t__le32 ixol;\n\t};\n\tstruct arch_probe_insn api;\n\tbool simulate;\n};\n\nstruct arch_uprobe_task {};\n\nstruct arch_vcpu_info {};\n\nstruct arch_vdso_time_data {};\n\nstruct arena_free_span {\n\tstruct llist_node node;\n\tlong unsigned int uaddr;\n\tu32 page_cnt;\n};\n\nstruct arg_aux {\n\tint args_in_regs;\n\tint regs_for_args;\n\tint bstack_for_args;\n\tint ostack_for_args;\n};\n\nstruct args_askumount {\n\t__u32 may_umount;\n};\n\nstruct args_expire {\n\t__u32 how;\n};\n\nstruct args_fail {\n\t__u32 token;\n\t__s32 status;\n};\n\nstruct args_in {\n\t__u32 type;\n};\n\nstruct args_out {\n\t__u32 devid;\n\t__u32 magic;\n};\n\nstruct args_ismountpoint {\n\tunion {\n\t\tstruct args_in in;\n\t\tstruct args_out out;\n\t};\n};\n\nstruct args_openmount {\n\t__u32 devid;\n};\n\nstruct args_protosubver {\n\t__u32 sub_version;\n};\n\nstruct args_protover {\n\t__u32 version;\n};\n\nstruct args_ready {\n\t__u32 token;\n};\n\nstruct args_requester {\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct args_setpipefd {\n\t__s32 pipefd;\n};\n\nstruct args_timeout {\n\t__u64 timeout;\n};\n\nstruct midr_range {\n\tu32 model;\n\tu32 rv_min;\n\tu32 rv_max;\n};\n\nstruct arm64_midr_revidr;\n\nstruct arm64_cpu_capabilities {\n\tconst char *desc;\n\tu16 capability;\n\tu16 type;\n\tbool (*matches)(const struct arm64_cpu_capabilities *, int);\n\tvoid (*cpu_enable)(const struct arm64_cpu_capabilities *);\n\tunion {\n\t\tstruct {\n\t\t\tstruct midr_range midr_range;\n\t\t\tconst struct arm64_midr_revidr * const fixed_revs;\n\t\t};\n\t\tconst struct midr_range *midr_range_list;\n\t\tstruct {\n\t\t\tu32 sys_reg;\n\t\t\tu8 field_pos;\n\t\t\tu8 field_width;\n\t\t\tu8 min_field_value;\n\t\t\tu8 max_field_value;\n\t\t\tu8 hwcap_type;\n\t\t\tbool sign;\n\t\t\tlong unsigned int hwcap;\n\t\t};\n\t};\n\tconst struct arm64_cpu_capabilities *match_list;\n\tconst struct cpumask *cpus;\n};\n\nstruct arm64_ftr_bits {\n\tbool sign;\n\tbool visible;\n\tbool strict;\n\tenum ftr_type type;\n\tu8 shift;\n\tu8 width;\n\ts64 safe_val;\n};\n\nstruct arm64_ftr_override {\n\tu64 val;\n\tu64 mask;\n};\n\nstruct arm64_ftr_reg {\n\tconst char *name;\n\tu64 strict_mask;\n\tu64 user_mask;\n\tu64 sys_val;\n\tu64 user_val;\n\tstruct arm64_ftr_override *override;\n\tconst struct arm64_ftr_bits *ftr_bits;\n};\n\nstruct arm64_image_header {\n\t__le32 code0;\n\t__le32 code1;\n\t__le64 text_offset;\n\t__le64 image_size;\n\t__le64 flags;\n\t__le64 res2;\n\t__le64 res3;\n\t__le64 res4;\n\t__le32 magic;\n\t__le32 res5;\n};\n\nstruct jit_ctx {\n\tconst struct bpf_prog *prog;\n\tint idx;\n\tint epilogue_offset;\n\tint *offset;\n\tint exentry_idx;\n\tint nr_used_callee_reg;\n\tu8 used_callee_reg[8];\n\t__le32 *image;\n\t__le32 *ro_image;\n\tu32 stack_size;\n\tu64 user_vm_start;\n\tu64 arena_vm_start;\n\tbool fp_used;\n\tbool priv_sp_used;\n\tbool write;\n};\n\nstruct bpf_binary_header;\n\nstruct arm64_jit_data {\n\tstruct bpf_binary_header *header;\n\tu8 *ro_image;\n\tstruct bpf_binary_header *ro_header;\n\tstruct jit_ctx ctx;\n};\n\nstruct arm64_mem_crypt_ops {\n\tint (*encrypt)(long unsigned int, int);\n\tint (*decrypt)(long unsigned int, int);\n};\n\nstruct arm64_midr_revidr {\n\tu32 midr_rv;\n\tu32 revidr_mask;\n};\n\nstruct arm_cpuidle_irq_context {};\n\nstruct arm_ghash_desc_ctx {\n\tu64 digest[2];\n};\n\nstruct iommu_flush_ops;\n\nstruct io_pgtable_cfg {\n\tlong unsigned int quirks;\n\tlong unsigned int pgsize_bitmap;\n\tunsigned int ias;\n\tunsigned int oas;\n\tbool coherent_walk;\n\tconst struct iommu_flush_ops *tlb;\n\tstruct device *iommu_dev;\n\tvoid * (*alloc)(void *, size_t, gfp_t);\n\tvoid (*free)(void *, void *, size_t);\n\tunion {\n\t\tstruct {\n\t\t\tu64 ttbr;\n\t\t\tstruct {\n\t\t\t\tu32 ips: 3;\n\t\t\t\tu32 tg: 2;\n\t\t\t\tu32 sh: 2;\n\t\t\t\tu32 orgn: 2;\n\t\t\t\tu32 irgn: 2;\n\t\t\t\tu32 tsz: 6;\n\t\t\t} tcr;\n\t\t\tu64 mair;\n\t\t} arm_lpae_s1_cfg;\n\t\tstruct {\n\t\t\tu64 vttbr;\n\t\t\tstruct {\n\t\t\t\tu32 ps: 3;\n\t\t\t\tu32 tg: 2;\n\t\t\t\tu32 sh: 2;\n\t\t\t\tu32 orgn: 2;\n\t\t\t\tu32 irgn: 2;\n\t\t\t\tu32 sl: 2;\n\t\t\t\tu32 tsz: 6;\n\t\t\t} vtcr;\n\t\t} arm_lpae_s2_cfg;\n\t\tstruct {\n\t\t\tu32 ttbr;\n\t\t\tu32 tcr;\n\t\t\tu32 nmrr;\n\t\t\tu32 prrr;\n\t\t} arm_v7s_cfg;\n\t\tstruct {\n\t\t\tu64 transtab;\n\t\t\tu64 memattr;\n\t\t} arm_mali_lpae_cfg;\n\t\tstruct {\n\t\t\tu64 ttbr[4];\n\t\t\tu32 n_ttbrs;\n\t\t\tu32 n_levels;\n\t\t} apple_dart_cfg;\n\t\tstruct {\n\t\t\tint nid;\n\t\t} amd;\n\t};\n};\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_dirty_bitmap;\n\nstruct io_pgtable_ops {\n\tint (*map_pages)(struct io_pgtable_ops *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct io_pgtable_ops *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tphys_addr_t (*iova_to_phys)(struct io_pgtable_ops *, long unsigned int);\n\tint (*pgtable_walk)(struct io_pgtable_ops *, long unsigned int, void *);\n\tint (*read_and_clear_dirty)(struct io_pgtable_ops *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct io_pgtable {\n\tenum io_pgtable_fmt fmt;\n\tvoid *cookie;\n\tstruct io_pgtable_cfg cfg;\n\tstruct io_pgtable_ops ops;\n};\n\nstruct arm_lpae_io_pgtable {\n\tstruct io_pgtable iop;\n\tint pgd_bits;\n\tint start_level;\n\tint bits_per_level;\n\tvoid *pgd;\n};\n\nstruct arm_lpae_io_pgtable_walk_data {\n\tu64 ptes[4];\n};\n\nstruct mhu_db_link {\n\tunsigned int irq;\n\tvoid *tx_reg;\n\tvoid *rx_reg;\n};\n\nstruct mbox_chan_ops;\n\nstruct mbox_chan;\n\nstruct fwnode_reference_args;\n\nstruct mbox_controller {\n\tstruct device *dev;\n\tconst struct mbox_chan_ops *ops;\n\tstruct mbox_chan *chans;\n\tint num_chans;\n\tbool txdone_irq;\n\tbool txdone_poll;\n\tunsigned int txpoll_period;\n\tstruct mbox_chan * (*fw_xlate)(struct mbox_controller *, const struct fwnode_reference_args *);\n\tstruct mbox_chan * (*of_xlate)(struct mbox_controller *, const struct of_phandle_args *);\n\tstruct hrtimer poll_hrt;\n\tspinlock_t poll_hrt_lock;\n\tstruct list_head node;\n};\n\nstruct arm_mhu {\n\tvoid *base;\n\tstruct mhu_db_link mlink[3];\n\tstruct mbox_controller mbox;\n\tstruct device *dev;\n};\n\nstruct mhu_link {\n\tunsigned int irq;\n\tvoid *tx_reg;\n\tvoid *rx_reg;\n};\n\nstruct mbox_client;\n\nstruct mbox_chan {\n\tstruct mbox_controller *mbox;\n\tunsigned int txdone_method;\n\tstruct mbox_client *cl;\n\tstruct completion tx_complete;\n\tvoid *active_req;\n\tunsigned int msg_count;\n\tunsigned int msg_free;\n\tvoid *msg_data[20];\n\tspinlock_t lock;\n\tvoid *con_priv;\n};\n\nstruct arm_mhu___2 {\n\tvoid *base;\n\tstruct mhu_link mlink[3];\n\tstruct mbox_chan chan[3];\n\tstruct mbox_controller mbox;\n};\n\nstruct perf_cpu_pmu_context;\n\nstruct perf_event;\n\nstruct mm_struct;\n\nstruct perf_event_pmu_context;\n\nstruct kmem_cache;\n\nstruct perf_output_handle;\n\nstruct pmu {\n\tstruct list_head entry;\n\tspinlock_t events_lock;\n\tstruct list_head events;\n\tstruct module *module;\n\tstruct device *dev;\n\tstruct device *parent;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tunsigned int scope;\n\tstruct perf_cpu_pmu_context **cpu_pmu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tstruct kmem_cache *task_ctx_cache;\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tbool (*filter)(struct pmu *, int);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\nstruct pmu_hw_events;\n\nstruct hw_perf_event;\n\nstruct perf_event_attr;\n\nstruct arm_pmu {\n\tstruct pmu pmu;\n\tcpumask_t supported_cpus;\n\tchar *name;\n\tirqreturn_t (*handle_irq)(struct arm_pmu *);\n\tvoid (*enable)(struct perf_event *);\n\tvoid (*disable)(struct perf_event *);\n\tint (*get_event_idx)(struct pmu_hw_events *, struct perf_event *);\n\tvoid (*clear_event_idx)(struct pmu_hw_events *, struct perf_event *);\n\tint (*set_event_filter)(struct hw_perf_event *, struct perf_event_attr *);\n\tu64 (*read_counter)(struct perf_event *);\n\tvoid (*write_counter)(struct perf_event *, u64);\n\tvoid (*start)(struct arm_pmu *);\n\tvoid (*stop)(struct arm_pmu *);\n\tvoid (*reset)(void *);\n\tint (*map_event)(struct perf_event *);\n\tint (*map_pmuv3_event)(unsigned int);\n\tlong unsigned int cntr_mask[1];\n\tbool secure_access;\n\tstruct platform_device *plat_device;\n\tstruct pmu_hw_events *hw_events;\n\tstruct hlist_node node;\n\tstruct notifier_block cpu_pm_nb;\n\tconst struct attribute_group *attr_groups[5];\n\tint pmuver;\n\tbool has_smt;\n\tu64 reg_pmmir;\n\tu64 reg_brbidr;\n\tlong unsigned int pmceid_bitmap[1];\n\tlong unsigned int pmceid_ext_bitmap[1];\n\tlong unsigned int acpi_cpuid;\n};\n\nstruct arm_pmu_entry {\n\tstruct list_head entry;\n\tstruct arm_pmu *arm_pmu;\n};\n\nstruct arm_smccc_1_2_regs {\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n\tlong unsigned int a3;\n\tlong unsigned int a4;\n\tlong unsigned int a5;\n\tlong unsigned int a6;\n\tlong unsigned int a7;\n\tlong unsigned int a8;\n\tlong unsigned int a9;\n\tlong unsigned int a10;\n\tlong unsigned int a11;\n\tlong unsigned int a12;\n\tlong unsigned int a13;\n\tlong unsigned int a14;\n\tlong unsigned int a15;\n\tlong unsigned int a16;\n\tlong unsigned int a17;\n};\n\nstruct arm_smccc_args {\n\tlong unsigned int args[8];\n};\n\nstruct arm_smccc_quirk {\n\tint id;\n\tunion {\n\t\tlong unsigned int a6;\n\t} state;\n};\n\nstruct arm_smccc_res {\n\tlong unsigned int a0;\n\tlong unsigned int a1;\n\tlong unsigned int a2;\n\tlong unsigned int a3;\n};\n\nstruct iommu_domain;\n\nstruct arm_smmu_master;\n\nstruct arm_smmu_vmaster;\n\nstruct arm_smmu_attach_state {\n\tstruct iommu_domain *old_domain;\n\tstruct arm_smmu_master *master;\n\tbool cd_needs_ats;\n\tbool disable_ats;\n\tioasid_t ssid;\n\tstruct arm_smmu_vmaster *vmaster;\n\tbool ats_enabled;\n};\n\nstruct arm_smmu_cfg;\n\nstruct arm_smmu_cb {\n\tu64 ttbr[2];\n\tu32 tcr[2];\n\tu32 mair[2];\n\tstruct arm_smmu_cfg *cfg;\n};\n\nstruct arm_smmu_cd {\n\t__le64 data[8];\n};\n\nstruct arm_smmu_entry_writer_ops;\n\nstruct arm_smmu_entry_writer {\n\tconst struct arm_smmu_entry_writer_ops *ops;\n\tstruct arm_smmu_master *master;\n};\n\nstruct arm_smmu_cd_writer {\n\tstruct arm_smmu_entry_writer writer;\n\tunsigned int ssid;\n};\n\nstruct arm_smmu_cdtab_l1 {\n\t__le64 l2ptr;\n};\n\nstruct arm_smmu_cdtab_l2 {\n\tstruct arm_smmu_cd cds[1024];\n};\n\nstruct arm_smmu_cfg {\n\tu8 cbndx;\n\tu8 irptndx;\n\tunion {\n\t\tu16 asid;\n\t\tu16 vmid;\n\t};\n\tenum arm_smmu_cbar_type cbar;\n\tenum arm_smmu_context_fmt fmt;\n\tbool flush_walk_prefer_tlbiasid;\n};\n\nstruct arm_smmu_ll_queue {\n\tunion {\n\t\tu64 val;\n\t\tstruct {\n\t\t\tu32 prod;\n\t\t\tu32 cons;\n\t\t};\n\t\tstruct {\n\t\t\tatomic_t prod;\n\t\t\tatomic_t cons;\n\t\t} atomic;\n\t\tu8 __pad[64];\n\t};\n\tu32 max_n_shift;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct arm_smmu_queue {\n\tstruct arm_smmu_ll_queue llq;\n\tint irq;\n\t__le64 *base;\n\tdma_addr_t base_dma;\n\tu64 q_base;\n\tsize_t ent_dwords;\n\tu32 *prod_reg;\n\tu32 *cons_reg;\n\tlong: 64;\n};\n\nstruct arm_smmu_cmdq_ent;\n\nstruct arm_smmu_cmdq {\n\tstruct arm_smmu_queue q;\n\tatomic_long_t *valid_map;\n\tatomic_t owner_prod;\n\tatomic_t lock;\n\tbool (*supports_cmd)(struct arm_smmu_cmdq_ent *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct arm_smmu_cmdq_batch {\n\tu64 cmds[128];\n\tstruct arm_smmu_cmdq *cmdq;\n\tint num;\n};\n\nstruct arm_smmu_cmdq_ent {\n\tu8 opcode;\n\tbool substream_valid;\n\tunion {\n\t\tstruct {\n\t\t\tu32 sid;\n\t\t} prefetch;\n\t\tstruct {\n\t\t\tu32 sid;\n\t\t\tu32 ssid;\n\t\t\tunion {\n\t\t\t\tbool leaf;\n\t\t\t\tu8 span;\n\t\t\t};\n\t\t} cfgi;\n\t\tstruct {\n\t\t\tu8 num;\n\t\t\tu8 scale;\n\t\t\tu16 asid;\n\t\t\tu16 vmid;\n\t\t\tbool leaf;\n\t\t\tu8 ttl;\n\t\t\tu8 tg;\n\t\t\tu64 addr;\n\t\t} tlbi;\n\t\tstruct {\n\t\t\tu32 sid;\n\t\t\tu32 ssid;\n\t\t\tu64 addr;\n\t\t\tu8 size;\n\t\t\tbool global;\n\t\t} atc;\n\t\tstruct {\n\t\t\tu32 sid;\n\t\t\tu32 ssid;\n\t\t\tu16 grpid;\n\t\t\tenum pri_resp resp;\n\t\t} pri;\n\t\tstruct {\n\t\t\tu32 sid;\n\t\t\tu16 stag;\n\t\t\tu8 resp;\n\t\t} resume;\n\t\tstruct {\n\t\t\tu64 msiaddr;\n\t\t} sync;\n\t};\n};\n\nstruct arm_smmu_context_fault_info {\n\tlong unsigned int iova;\n\tu32 fsr;\n\tu32 fsynr;\n\tu32 cbfrsynra;\n};\n\nstruct arm_smmu_ctx_desc {\n\tu16 asid;\n};\n\nstruct arm_smmu_ctx_desc_cfg {\n\tunion {\n\t\tstruct {\n\t\t\tstruct arm_smmu_cd *table;\n\t\t\tunsigned int num_ents;\n\t\t} linear;\n\t\tstruct {\n\t\t\tstruct arm_smmu_cdtab_l1 *l1tab;\n\t\t\tstruct arm_smmu_cdtab_l2 **l2ptrs;\n\t\t\tunsigned int num_l1_ents;\n\t\t} l2;\n\t};\n\tdma_addr_t cdtab_dma;\n\tunsigned int used_ssids;\n\tu8 in_ste;\n\tu8 s1fmt;\n\tu8 s1cdmax;\n};\n\nstruct iopf_queue;\n\nstruct arm_smmu_evtq {\n\tstruct arm_smmu_queue q;\n\tstruct iopf_queue *iopf;\n\tu32 max_stalls;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct arm_smmu_priq {\n\tstruct arm_smmu_queue q;\n};\n\nstruct arm_smmu_ste;\n\nstruct arm_smmu_strtab_l1;\n\nstruct arm_smmu_strtab_l2;\n\nstruct arm_smmu_strtab_cfg {\n\tunion {\n\t\tstruct {\n\t\t\tstruct arm_smmu_ste *table;\n\t\t\tdma_addr_t ste_dma;\n\t\t\tunsigned int num_ents;\n\t\t} linear;\n\t\tstruct {\n\t\t\tstruct arm_smmu_strtab_l1 *l1tab;\n\t\t\tstruct arm_smmu_strtab_l2 **l2ptrs;\n\t\t\tdma_addr_t l1_dma;\n\t\t\tunsigned int num_l1_ents;\n\t\t} l2;\n\t};\n};\n\nstruct iommu_ops;\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n\tstruct iommu_group *singleton_group;\n\tu32 max_pasids;\n\tbool ready;\n};\n\nstruct arm_smmu_impl_ops;\n\nstruct arm_smmu_device {\n\tstruct device *dev;\n\tstruct device *impl_dev;\n\tconst struct arm_smmu_impl_ops *impl_ops;\n\tvoid *base;\n\tvoid *page1;\n\tu32 features;\n\tu32 options;\n\tlong: 64;\n\tlong: 64;\n\tstruct arm_smmu_cmdq cmdq;\n\tstruct arm_smmu_evtq evtq;\n\tstruct arm_smmu_priq priq;\n\tint gerr_irq;\n\tint combined_irq;\n\tlong unsigned int oas;\n\tlong unsigned int pgsize_bitmap;\n\tunsigned int asid_bits;\n\tunsigned int vmid_bits;\n\tstruct ida vmid_map;\n\tunsigned int ssid_bits;\n\tunsigned int sid_bits;\n\tstruct arm_smmu_strtab_cfg strtab_cfg;\n\tstruct iommu_device iommu;\n\tstruct rb_root streams;\n\tstruct mutex streams_mutex;\n\tlong: 64;\n};\n\nstruct arm_smmu_impl;\n\nstruct arm_smmu_smr;\n\nstruct arm_smmu_s2cr;\n\nstruct arm_smmu_device___2 {\n\tstruct device *dev;\n\tvoid *base;\n\tphys_addr_t ioaddr;\n\tunsigned int numpage;\n\tunsigned int pgshift;\n\tu32 features;\n\tenum arm_smmu_arch_version version;\n\tenum arm_smmu_implementation model;\n\tconst struct arm_smmu_impl *impl;\n\tu32 num_context_banks;\n\tu32 num_s2_context_banks;\n\tlong unsigned int context_map[2];\n\tstruct arm_smmu_cb *cbs;\n\tatomic_t irptndx;\n\tu32 num_mapping_groups;\n\tu16 streamid_mask;\n\tu16 smr_mask_mask;\n\tstruct arm_smmu_smr *smrs;\n\tstruct arm_smmu_s2cr *s2crs;\n\tstruct mutex stream_map_mutex;\n\tlong unsigned int va_size;\n\tlong unsigned int ipa_size;\n\tlong unsigned int pa_size;\n\tlong unsigned int pgsize_bitmap;\n\tint num_context_irqs;\n\tint num_clks;\n\tunsigned int *irqs;\n\tstruct clk_bulk_data *clks;\n\tspinlock_t global_sync_lock;\n\tstruct iommu_device iommu;\n};\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommufd_hw_pagetable;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_ops;\n\nstruct iommu_dirty_ops;\n\nstruct iopf_group;\n\nstruct iommu_dma_cookie;\n\nstruct iommu_dma_msi_cookie;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct arm_smmu_domain {\n\tstruct arm_smmu_device___2 *smmu;\n\tstruct io_pgtable_ops *pgtbl_ops;\n\tlong unsigned int pgtbl_quirks;\n\tconst struct iommu_flush_ops *flush_ops;\n\tstruct arm_smmu_cfg cfg;\n\tenum arm_smmu_domain_stage___2 stage;\n\tstruct mutex init_mutex;\n\tspinlock_t cb_lock;\n\tstruct iommu_domain domain;\n};\n\nstruct arm_smmu_s2_cfg {\n\tu16 vmid;\n};\n\nstruct mmu_notifier_ops;\n\nstruct mmu_notifier {\n\tstruct hlist_node hlist;\n\tconst struct mmu_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct callback_head rcu;\n\tunsigned int users;\n};\n\nstruct arm_smmu_domain___2 {\n\tstruct arm_smmu_device *smmu;\n\tstruct io_pgtable_ops *pgtbl_ops;\n\tatomic_t nr_ats_masters;\n\tenum arm_smmu_domain_stage stage;\n\tunion {\n\t\tstruct arm_smmu_ctx_desc cd;\n\t\tstruct arm_smmu_s2_cfg s2_cfg;\n\t};\n\tstruct iommu_domain domain;\n\tstruct list_head devices;\n\tspinlock_t devices_lock;\n\tbool enforce_cache_coherency: 1;\n\tbool nest_parent: 1;\n\tstruct mmu_notifier mmu_notifier;\n};\n\nstruct arm_smmu_entry_writer_ops {\n\tvoid (*get_used)(const __le64 *, __le64 *);\n\tvoid (*get_update_safe)(const __le64 *, const __le64 *, __le64 *);\n\tvoid (*sync)(struct arm_smmu_entry_writer *);\n};\n\nstruct arm_smmu_event {\n\tu8 stall: 1;\n\tu8 ssv: 1;\n\tu8 privileged: 1;\n\tu8 instruction: 1;\n\tu8 s2: 1;\n\tu8 read: 1;\n\tu8 ttrnw: 1;\n\tu8 class_tt: 1;\n\tu8 id;\n\tu8 class;\n\tu16 stag;\n\tu32 sid;\n\tu32 ssid;\n\tu64 iova;\n\tu64 ipa;\n\tu64 fetch_addr;\n\tstruct device *dev;\n};\n\nstruct arm_smmu_impl {\n\tu32 (*read_reg)(struct arm_smmu_device___2 *, int, int);\n\tvoid (*write_reg)(struct arm_smmu_device___2 *, int, int, u32);\n\tu64 (*read_reg64)(struct arm_smmu_device___2 *, int, int);\n\tvoid (*write_reg64)(struct arm_smmu_device___2 *, int, int, u64);\n\tint (*cfg_probe)(struct arm_smmu_device___2 *);\n\tint (*reset)(struct arm_smmu_device___2 *);\n\tint (*init_context)(struct arm_smmu_domain *, struct io_pgtable_cfg *, struct device *);\n\tvoid (*tlb_sync)(struct arm_smmu_device___2 *, int, int, int);\n\tint (*def_domain_type)(struct device *);\n\tirqreturn_t (*global_fault)(int, void *);\n\tirqreturn_t (*context_fault)(int, void *);\n\tbool context_fault_needs_threaded_irq;\n\tint (*alloc_context_bank)(struct arm_smmu_domain *, struct arm_smmu_device___2 *, struct device *, int);\n\tvoid (*write_s2cr)(struct arm_smmu_device___2 *, int);\n\tvoid (*write_sctlr)(struct arm_smmu_device___2 *, int, u32);\n\tvoid (*probe_finalize)(struct arm_smmu_device___2 *, struct device *);\n};\n\nstruct arm_vsmmu;\n\nstruct iommu_user_data;\n\nstruct arm_smmu_impl_ops {\n\tint (*device_reset)(struct arm_smmu_device *);\n\tvoid (*device_remove)(struct arm_smmu_device *);\n\tint (*init_structures)(struct arm_smmu_device *);\n\tstruct arm_smmu_cmdq * (*get_secondary_cmdq)(struct arm_smmu_device *, struct arm_smmu_cmdq_ent *);\n\tvoid * (*hw_info)(struct arm_smmu_device *, u32 *, enum iommu_hw_info_type *);\n\tsize_t (*get_viommu_size)(enum iommu_viommu_type);\n\tint (*vsmmu_init)(struct arm_vsmmu *, const struct iommu_user_data *);\n};\n\nstruct arm_smmu_stream;\n\nstruct arm_smmu_master {\n\tstruct arm_smmu_device *smmu;\n\tstruct device *dev;\n\tstruct arm_smmu_stream *streams;\n\tstruct arm_smmu_vmaster *vmaster;\n\tstruct arm_smmu_ctx_desc_cfg cd_table;\n\tunsigned int num_streams;\n\tbool ats_enabled: 1;\n\tbool ste_ats_enabled: 1;\n\tbool stall_enabled;\n\tunsigned int ssid_bits;\n\tunsigned int iopf_refcount;\n};\n\nstruct arm_smmu_master_cfg {\n\tstruct arm_smmu_device___2 *smmu;\n\ts16 smendx[0];\n};\n\nstruct arm_smmu_master_domain {\n\tstruct list_head devices_elm;\n\tstruct arm_smmu_master *master;\n\tstruct iommu_domain *domain;\n\tioasid_t ssid;\n\tbool nested_ats_flush: 1;\n\tbool using_iopf: 1;\n};\n\nstruct arm_smmu_match_data {\n\tenum arm_smmu_arch_version version;\n\tenum arm_smmu_implementation model;\n};\n\nstruct arm_smmu_nested_domain {\n\tstruct iommu_domain domain;\n\tstruct arm_vsmmu *vsmmu;\n\tbool enable_ats: 1;\n\t__le64 ste[2];\n};\n\nstruct arm_smmu_option_prop {\n\tu32 opt;\n\tconst char *prop;\n};\n\nstruct arm_smmu_queue_poll {\n\tktime_t timeout;\n\tunsigned int delay;\n\tunsigned int spin_cnt;\n\tbool wfe;\n};\n\nstruct arm_smmu_s2cr {\n\tstruct iommu_group *group;\n\tint count;\n\tenum arm_smmu_s2cr_type type;\n\tenum arm_smmu_s2cr_privcfg privcfg;\n\tu8 cbndx;\n};\n\nstruct arm_smmu_smr {\n\tu16 mask;\n\tu16 id;\n\tbool valid;\n\tbool pinned;\n};\n\nstruct arm_smmu_ste {\n\t__le64 data[8];\n};\n\nstruct arm_smmu_ste_writer {\n\tstruct arm_smmu_entry_writer writer;\n\tu32 sid;\n};\n\nstruct arm_smmu_stream {\n\tu32 id;\n\tstruct arm_smmu_master *master;\n\tstruct rb_node node;\n};\n\nstruct arm_smmu_strtab_l1 {\n\t__le64 l2ptr;\n};\n\nstruct arm_smmu_strtab_l2 {\n\tstruct arm_smmu_ste stes[256];\n};\n\nstruct arm_smmu_vmaster {\n\tstruct arm_vsmmu *vsmmu;\n\tlong unsigned int vsid;\n};\n\nstruct arm_v7s_io_pgtable {\n\tstruct io_pgtable iop;\n\tarm_v7s_iopte *pgd;\n\tstruct kmem_cache *l2_tables;\n};\n\nstruct iommufd_object {\n\trefcount_t wait_cnt;\n\trefcount_t users;\n\tenum iommufd_object_type type;\n\tunsigned int id;\n};\n\nstruct iommufd_ctx;\n\nstruct iommufd_hwpt_paging;\n\nstruct iommufd_viommu_ops;\n\nstruct iommufd_viommu {\n\tstruct iommufd_object obj;\n\tstruct iommufd_ctx *ictx;\n\tstruct iommu_device *iommu_dev;\n\tstruct iommufd_hwpt_paging *hwpt;\n\tconst struct iommufd_viommu_ops *ops;\n\tstruct xarray vdevs;\n\tstruct list_head veventqs;\n\tstruct rw_semaphore veventqs_rwsem;\n\tenum iommu_viommu_type type;\n};\n\nstruct arm_vsmmu {\n\tstruct iommufd_viommu core;\n\tstruct arm_smmu_device *smmu;\n\tstruct arm_smmu_domain___2 *s2_parent;\n\tu16 vmid;\n};\n\nstruct armada37xx_cpufreq_state {\n\tstruct platform_device *pdev;\n\tstruct device *cpu_dev;\n\tstruct regmap *regmap;\n\tu32 nb_l0l1;\n\tu32 nb_l2l3;\n\tu32 nb_dyn_mod;\n\tu32 nb_cpu_load;\n};\n\nstruct value_to_freq;\n\nstruct armada38x_rtc_data;\n\nstruct armada38x_rtc {\n\tstruct rtc_device *rtc_dev;\n\tvoid *regs;\n\tvoid *regs_soc;\n\tspinlock_t lock;\n\tint irq;\n\tbool initialized;\n\tstruct value_to_freq *val_to_freq;\n\tconst struct armada38x_rtc_data *data;\n};\n\nstruct armada38x_rtc_data {\n\tvoid (*update_mbus_timing)(struct armada38x_rtc *);\n\tu32 (*read_rtc_reg)(struct armada38x_rtc *, u8);\n\tvoid (*clear_isr)(struct armada38x_rtc *);\n\tvoid (*unmask_interrupt)(struct armada38x_rtc *);\n\tu32 alarm;\n};\n\nstruct dw_pcie;\n\nstruct armada8k_pcie {\n\tstruct dw_pcie *pci;\n\tstruct clk *clk;\n\tstruct clk *clk_reg;\n\tstruct phy *phy[4];\n\tunsigned int phy_count;\n};\n\nstruct armada_37xx_dvfs {\n\tu32 cpu_freq_max;\n\tu8 divider[4];\n\tu32 avs[4];\n};\n\nstruct armada_37xx_pin_group;\n\nstruct armada_37xx_pin_data {\n\tu8 nr_pins;\n\tchar *name;\n\tstruct armada_37xx_pin_group *groups;\n\tint ngroups;\n};\n\nstruct armada_37xx_pin_group {\n\tconst char *name;\n\tunsigned int start_pin;\n\tunsigned int npins;\n\tu32 reg_mask;\n\tu32 val[3];\n\tunsigned int extra_pin;\n\tunsigned int extra_npins;\n\tconst char *funcs[3];\n\tunsigned int *pins;\n};\n\nstruct pinctrl_pin_desc;\n\nstruct pinctrl_ops;\n\nstruct pinmux_ops;\n\nstruct pinconf_ops;\n\nstruct pinconf_generic_params;\n\nstruct pin_config_item;\n\nstruct pinctrl_desc {\n\tconst char *name;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct pinctrl_ops *pctlops;\n\tconst struct pinmux_ops *pmxops;\n\tconst struct pinconf_ops *confops;\n\tstruct module *owner;\n\tunsigned int num_custom_params;\n\tconst struct pinconf_generic_params *custom_params;\n\tconst struct pin_config_item *custom_conf_items;\n\tbool link_consumers;\n};\n\nstruct armada_37xx_pm_state {\n\tu32 out_en_l;\n\tu32 out_en_h;\n\tu32 out_val_l;\n\tu32 out_val_h;\n\tu32 irq_en_l;\n\tu32 irq_en_h;\n\tu32 irq_pol_l;\n\tu32 irq_pol_h;\n\tu32 selection;\n};\n\nstruct armada_37xx_pmx_func;\n\nstruct armada_37xx_pinctrl {\n\tstruct regmap *regmap;\n\tvoid *base;\n\tconst struct armada_37xx_pin_data *data;\n\tstruct device *dev;\n\tstruct gpio_chip gpio_chip;\n\traw_spinlock_t irq_lock;\n\tstruct pinctrl_desc pctl;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct armada_37xx_pin_group *groups;\n\tunsigned int ngroups;\n\tstruct armada_37xx_pmx_func *funcs;\n\tunsigned int nfuncs;\n\tstruct armada_37xx_pm_state pm;\n};\n\nstruct armada_37xx_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct armada_thermal_priv;\n\nstruct armada_drvdata {\n\tenum drvtype type;\n\tunion {\n\t\tstruct armada_thermal_priv *priv;\n\t\tstruct thermal_zone_device *tz;\n\t} data;\n};\n\nstruct armada_thermal_data {\n\tvoid (*init)(struct platform_device *, struct armada_thermal_priv *);\n\ts64 coef_b;\n\ts64 coef_m;\n\tu32 coef_div;\n\tbool inverted;\n\tbool signed_sample;\n\tunsigned int temp_shift;\n\tunsigned int temp_mask;\n\tunsigned int thresh_shift;\n\tunsigned int hyst_shift;\n\tunsigned int hyst_mask;\n\tu32 is_valid_bit;\n\tunsigned int syscon_control0_off;\n\tunsigned int syscon_control1_off;\n\tunsigned int syscon_status_off;\n\tunsigned int dfx_irq_cause_off;\n\tunsigned int dfx_irq_mask_off;\n\tunsigned int dfx_overheat_irq;\n\tunsigned int dfx_server_irq_mask_off;\n\tunsigned int dfx_server_irq_en;\n\tunsigned int cpu_nr;\n};\n\nstruct armada_thermal_priv {\n\tstruct device *dev;\n\tstruct regmap *syscon;\n\tchar zone_name[20];\n\tstruct mutex update_lock;\n\tstruct armada_thermal_data *data;\n\tstruct thermal_zone_device *overheat_sensor;\n\tint interrupt_source;\n\tint current_channel;\n\tlong int current_threshold;\n\tlong int current_hysteresis;\n};\n\nstruct armada_thermal_sensor {\n\tstruct armada_thermal_priv *priv;\n\tint id;\n};\n\nstruct armctrl_ic {\n\tvoid *base;\n\tvoid *pending[3];\n\tvoid *enable[3];\n\tvoid *disable[3];\n\tstruct irq_domain *domain;\n};\n\nstruct armv8pmu_probe_info {\n\tstruct arm_pmu *pmu;\n\tbool present;\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct trace_array;\n\nstruct trace_buffer;\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tu64 time_start;\n\tint cpu;\n};\n\nstruct sas_work {\n\tstruct list_head drain_node;\n\tstruct work_struct work;\n};\n\nstruct asd_sas_phy;\n\nstruct asd_sas_event {\n\tstruct sas_work work;\n\tstruct asd_sas_phy *phy;\n\tint event;\n};\n\nstruct sas_phy;\n\nstruct asd_sas_port;\n\nstruct sas_ha_struct;\n\nstruct asd_sas_phy {\n\tatomic_t event_nr;\n\tint in_shutdown;\n\tint error;\n\tint suspended;\n\tstruct sas_phy *phy;\n\tint enabled;\n\tint id;\n\tenum sas_protocol iproto;\n\tenum sas_protocol tproto;\n\tenum sas_phy_role role;\n\tenum sas_oob_mode oob_mode;\n\tenum sas_linkrate linkrate;\n\tu8 *sas_addr;\n\tu8 attached_sas_addr[8];\n\tspinlock_t frame_rcvd_lock;\n\tu8 *frame_rcvd;\n\tint frame_rcvd_size;\n\tspinlock_t sas_prim_lock;\n\tu32 sas_prim;\n\tstruct list_head port_phy_el;\n\tstruct asd_sas_port *port;\n\tstruct sas_ha_struct *ha;\n\tvoid *lldd_phy;\n};\n\nstruct sas_discovery_event {\n\tstruct sas_work work;\n\tstruct asd_sas_port *port;\n};\n\nstruct sas_discovery {\n\tstruct sas_discovery_event disc_work[4];\n\tlong unsigned int pending;\n\tu8 fanout_sas_addr[8];\n\tu8 eeds_a[8];\n\tu8 eeds_b[8];\n\tint max_level;\n};\n\nstruct domain_device;\n\nstruct sas_port;\n\nstruct asd_sas_port {\n\tstruct sas_discovery disc;\n\tstruct domain_device *port_dev;\n\tspinlock_t dev_list_lock;\n\tstruct list_head dev_list;\n\tstruct list_head disco_list;\n\tstruct list_head destroy_list;\n\tstruct list_head sas_port_del_list;\n\tenum sas_linkrate linkrate;\n\tstruct sas_work work;\n\tint suspended;\n\tint id;\n\tu8 sas_addr[8];\n\tu8 attached_sas_addr[8];\n\tenum sas_protocol iproto;\n\tenum sas_protocol tproto;\n\tenum sas_oob_mode oob_mode;\n\tspinlock_t phy_list_lock;\n\tstruct list_head phy_list;\n\tint num_phys;\n\tu32 phy_mask;\n\tstruct sas_ha_struct *ha;\n\tstruct sas_port *port;\n\tvoid *lldd_port;\n};\n\ntypedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t);\n\nstruct asn1_decoder {\n\tconst unsigned char *machine;\n\tsize_t machlen;\n\tconst asn1_action_t *actions;\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct asymmetric_key_id {\n\tshort unsigned int len;\n\tunsigned char data[0];\n};\n\nstruct asymmetric_key_ids {\n\tvoid *id[3];\n};\n\nstruct key_preparsed_payload;\n\nstruct asymmetric_key_parser {\n\tstruct list_head link;\n\tstruct module *owner;\n\tconst char *name;\n\tint (*parse)(struct key_preparsed_payload *);\n};\n\nstruct key;\n\nstruct kernel_pkey_params;\n\nstruct kernel_pkey_query;\n\nstruct public_key_signature;\n\nstruct asymmetric_key_subtype {\n\tstruct module *owner;\n\tconst char *name;\n\tshort unsigned int name_len;\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tvoid (*destroy)(void *, void *);\n\tint (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*verify_signature)(const struct key *, const struct public_key_signature *);\n};\n\nstruct usb_dev_state;\n\nstruct pid;\n\nstruct urb;\n\nstruct usb_memory;\n\nstruct async {\n\tstruct list_head asynclist;\n\tstruct usb_dev_state *ps;\n\tstruct pid *pid;\n\tconst struct cred *cred;\n\tunsigned int signr;\n\tunsigned int ifnum;\n\tvoid *userbuffer;\n\tvoid *userurb;\n\tsigval_t userurb_sigval;\n\tstruct urb *urb;\n\tstruct usb_memory *usbm;\n\tunsigned int mem_usage;\n\tint status;\n\tu8 bulk_addr;\n\tu8 bulk_status;\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct at803x_context {\n\tu16 bmcr;\n\tu16 advertise;\n\tu16 control1000;\n\tu16 int_enable;\n\tu16 smart_speed;\n\tu16 led_control;\n};\n\nstruct regulator_dev;\n\nstruct at803x_priv {\n\tint flags;\n\tu16 clk_25m_reg;\n\tu16 clk_25m_mask;\n\tu8 smarteee_lpi_tw_1g;\n\tu8 smarteee_lpi_tw_100m;\n\tbool is_fiber;\n\tbool is_1000basex;\n\tstruct regulator_dev *vddio_rdev;\n\tstruct regulator_dev *vddh_rdev;\n};\n\nstruct at803x_ss_mask {\n\tu16 speed_mask;\n\tu8 speed_shift;\n};\n\nstruct ata_acpi_drive {\n\tu32 pio;\n\tu32 dma;\n};\n\nstruct ata_acpi_gtf {\n\tu8 tf[7];\n};\n\nstruct ata_acpi_gtm {\n\tstruct ata_acpi_drive drive[2];\n\tu32 flags;\n};\n\nstruct ata_device;\n\nstruct ata_acpi_hotplug_context {\n\tstruct acpi_hotplug_context hp;\n\tunion {\n\t\tstruct ata_port *ap;\n\t\tstruct ata_device *dev;\n\t} data;\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nstruct ata_cdl {\n\tu8 desc_log_buf[512];\n\tu8 ncq_sense_log_buf[1024];\n};\n\nstruct ata_cpr {\n\tu8 num;\n\tu8 num_storage_elements;\n\tu64 start_lba;\n\tu64 num_lbas;\n};\n\nstruct ata_cpr_log {\n\tu8 nr_cpr;\n\tstruct ata_cpr cpr[0];\n};\n\nstruct ata_dev_quirk_value {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 val;\n};\n\nstruct ata_dev_quirks_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 quirks;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tu64 quirks;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tunion acpi_object *gtf_cache;\n\tunsigned int gtf_filter;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 gp_log_dir[512];\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tstruct ata_cpr_log *cpr_log;\n\tstruct ata_cdl *cdl;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 sector_buf[512];\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst unsigned int *timeouts;\n};\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[16];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tu64 value;\n\tu8 cbl;\n\tu8 spd_limit;\n\tunsigned int xfer_mask;\n\tu64 quirk_on;\n\tu64 quirk_off;\n\tunsigned int pflags_on;\n\tu16 lflags_on;\n\tu16 lflags_off;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tunion {\n\t\tu8 error;\n\t\tu8 feature;\n\t};\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tunion {\n\t\tu8 status;\n\t\tu8 command;\n\t};\n\tu32 auxiliary;\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct scsi_cmnd;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tu64 qc_active;\n\tint nr_active_links;\n\tstruct work_struct deferred_qc_work;\n\tstruct ata_queued_cmd *deferred_qc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct delayed_work scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tunsigned int fastdrain_cnt;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tstruct ata_acpi_gtm __acpi_init_gtm;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nstruct ata_reset_operations {\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tvoid (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tvoid (*qc_ncq_fill_rtf)(struct ata_port *, u64);\n\tint (*cable_detect)(struct ata_port *);\n\tunsigned int (*mode_filter)(struct ata_device *, unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, __le16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tstruct ata_reset_operations reset;\n\tstruct ata_reset_operations pmp_reset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nstruct ata_task_resp {\n\tu16 frame_len;\n\tu8 ending_fis[24];\n};\n\nstruct ata_timing {\n\tshort unsigned int mode;\n\tshort unsigned int setup;\n\tshort unsigned int act8b;\n\tshort unsigned int rec8b;\n\tshort unsigned int cyc8b;\n\tshort unsigned int active;\n\tshort unsigned int recover;\n\tshort unsigned int dmack_hold;\n\tshort unsigned int cycle;\n\tshort unsigned int udma;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ate_acpi_oem_info {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n};\n\nstruct ps2dev;\n\ntypedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int);\n\ntypedef void (*ps2_receive_handler_t)(struct ps2dev *, u8);\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n\tps2_pre_receive_handler_t pre_receive_handler;\n\tps2_receive_handler_t receive_handler;\n};\n\nstruct vivaldi_data {\n\tu32 function_row_physmap[24];\n\tunsigned int num_function_row_keys;\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[8];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tstruct vivaldi_data vdata;\n};\n\nstruct atmel_trng {\n\tstruct clk *clk;\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tbool has_half_rate;\n};\n\nstruct atmel_trng_data {\n\tbool has_half_rate;\n};\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct attr_min {\n\tu32 attr;\n\tu32 min_value;\n};\n\nstruct attr_resp {\n\tu32 attr[1];\n};\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct audit_aux_data {\n\tstruct audit_aux_data *next;\n\tint type;\n};\n\nstruct audit_cap_data {\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n\tunion {\n\t\tunsigned int fE;\n\t\tkernel_cap_t effective;\n\t};\n\tkernel_cap_t ambient;\n\tkuid_t rootid;\n};\n\nstruct audit_aux_data_bprm_fcaps {\n\tstruct audit_aux_data d;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tstruct audit_cap_data old_pcap;\n\tstruct audit_cap_data new_pcap;\n};\n\nstruct lsm_prop_selinux {};\n\nstruct lsm_prop_smack {};\n\nstruct lsm_prop_apparmor {};\n\nstruct lsm_prop_bpf {};\n\nstruct lsm_prop {\n\tstruct lsm_prop_selinux selinux;\n\tstruct lsm_prop_smack smack;\n\tstruct lsm_prop_apparmor apparmor;\n\tstruct lsm_prop_bpf bpf;\n};\n\nstruct audit_aux_data_pids {\n\tstruct audit_aux_data d;\n\tpid_t target_pid[16];\n\tkuid_t target_auid[16];\n\tkuid_t target_uid[16];\n\tunsigned int target_sessionid[16];\n\tstruct lsm_prop target_ref[16];\n\tchar target_comm[256];\n\tint pid_count;\n};\n\nstruct audit_stamp {\n\tstruct timespec64 ctime;\n\tunsigned int serial;\n};\n\nstruct audit_context;\n\nstruct audit_buffer {\n\tstruct sk_buff *skb;\n\tstruct sk_buff_head skb_list;\n\tstruct audit_context *ctx;\n\tstruct audit_stamp stamp;\n\tgfp_t gfp_mask;\n};\n\nstruct audit_tree;\n\nstruct audit_node {\n\tstruct list_head list;\n\tstruct audit_tree *owner;\n\tunsigned int index;\n};\n\nstruct fsnotify_mark;\n\nstruct audit_chunk {\n\tstruct list_head hash;\n\tlong unsigned int key;\n\tstruct fsnotify_mark *mark;\n\tstruct list_head trees;\n\tint count;\n\tatomic_long_t refs;\n\tstruct callback_head head;\n\tstruct audit_node owners[0];\n};\n\nstruct filename;\n\nstruct audit_names {\n\tstruct list_head list;\n\tstruct filename *name;\n\tint name_len;\n\tbool hidden;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tstruct lsm_prop oprop;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tunsigned char type;\n\tbool should_free;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct mq_attr {\n\t__kernel_long_t mq_flags;\n\t__kernel_long_t mq_maxmsg;\n\t__kernel_long_t mq_msgsize;\n\t__kernel_long_t mq_curmsgs;\n\t__kernel_long_t __reserved[4];\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct audit_proctitle {\n\tint len;\n\tchar *value;\n};\n\nstruct audit_tree_refs;\n\nstruct audit_context {\n\tint dummy;\n\tenum {\n\t\tAUDIT_CTX_UNUSED = 0,\n\t\tAUDIT_CTX_SYSCALL = 1,\n\t\tAUDIT_CTX_URING = 2,\n\t} context;\n\tenum audit_state state;\n\tenum audit_state current_state;\n\tstruct audit_stamp stamp;\n\tint major;\n\tint uring_op;\n\tlong unsigned int argv[4];\n\tlong int return_code;\n\tu64 prio;\n\tint return_valid;\n\tstruct audit_names preallocated_names[5];\n\tint name_count;\n\tstruct list_head names_list;\n\tchar *filterkey;\n\tstruct path pwd;\n\tstruct audit_aux_data *aux;\n\tstruct audit_aux_data *aux_pids;\n\tstruct __kernel_sockaddr_storage *sockaddr;\n\tsize_t sockaddr_len;\n\tpid_t ppid;\n\tkuid_t uid;\n\tkuid_t euid;\n\tkuid_t suid;\n\tkuid_t fsuid;\n\tkgid_t gid;\n\tkgid_t egid;\n\tkgid_t sgid;\n\tkgid_t fsgid;\n\tlong unsigned int personality;\n\tint arch;\n\tpid_t target_pid;\n\tkuid_t target_auid;\n\tkuid_t target_uid;\n\tunsigned int target_sessionid;\n\tstruct lsm_prop target_ref;\n\tchar target_comm[16];\n\tstruct audit_tree_refs *trees;\n\tstruct audit_tree_refs *first_trees;\n\tstruct list_head killed_trees;\n\tint tree_count;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tint nargs;\n\t\t\tlong int args[6];\n\t\t} socketcall;\n\t\tstruct {\n\t\t\tkuid_t uid;\n\t\t\tkgid_t gid;\n\t\t\tumode_t mode;\n\t\t\tstruct lsm_prop oprop;\n\t\t\tint has_perm;\n\t\t\tuid_t perm_uid;\n\t\t\tgid_t perm_gid;\n\t\t\tumode_t perm_mode;\n\t\t\tlong unsigned int qbytes;\n\t\t} ipc;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tstruct mq_attr mqstat;\n\t\t} mq_getsetattr;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tint sigev_signo;\n\t\t} mq_notify;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tsize_t msg_len;\n\t\t\tunsigned int msg_prio;\n\t\t\tstruct timespec64 abs_timeout;\n\t\t} mq_sendrecv;\n\t\tstruct {\n\t\t\tint oflag;\n\t\t\tumode_t mode;\n\t\t\tstruct mq_attr attr;\n\t\t} mq_open;\n\t\tstruct {\n\t\t\tpid_t pid;\n\t\t\tstruct audit_cap_data cap;\n\t\t} capset;\n\t\tstruct {\n\t\t\tint fd;\n\t\t\tint flags;\n\t\t} mmap;\n\t\tstruct open_how openat2;\n\t\tstruct {\n\t\t\tint argc;\n\t\t} execve;\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t} module;\n\t\tstruct {\n\t\t\tstruct audit_ntp_data ntp_data;\n\t\t\tstruct timespec64 tk_injoffset;\n\t\t} time;\n\t};\n\tint fds[2];\n\tstruct audit_proctitle proctitle;\n};\n\nstruct audit_ctl_mutex {\n\tstruct mutex lock;\n\tvoid *owner;\n};\n\nstruct audit_field;\n\nstruct audit_watch;\n\nstruct audit_fsnotify_mark;\n\nstruct audit_krule {\n\tu32 pflags;\n\tu32 flags;\n\tu32 listnr;\n\tu32 action;\n\tu32 mask[64];\n\tu32 buflen;\n\tu32 field_count;\n\tchar *filterkey;\n\tstruct audit_field *fields;\n\tstruct audit_field *arch_f;\n\tstruct audit_field *inode_f;\n\tstruct audit_watch *watch;\n\tstruct audit_tree *tree;\n\tstruct audit_fsnotify_mark *exe;\n\tstruct list_head rlist;\n\tstruct list_head list;\n\tu64 prio;\n};\n\nstruct audit_entry {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tstruct audit_krule rule;\n};\n\nstruct audit_features {\n\t__u32 vers;\n\t__u32 mask;\n\t__u32 features;\n\t__u32 lock;\n};\n\nstruct audit_field {\n\tu32 type;\n\tunion {\n\t\tu32 val;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tstruct {\n\t\t\tchar *lsm_str;\n\t\t\tvoid *lsm_rule;\n\t\t};\n\t};\n\tu32 op;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark_connector;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct audit_fsnotify_mark {\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar *path;\n\tstruct fsnotify_mark mark;\n\tstruct audit_krule *rule;\n};\n\nstruct sock;\n\nstruct audit_net {\n\tstruct sock *sk;\n};\n\nstruct audit_netlink_list {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff_head q;\n};\n\nstruct audit_nfcfgop_tab {\n\tenum audit_nfcfgop op;\n\tconst char *s;\n};\n\nstruct audit_parent {\n\tstruct list_head watches;\n\tstruct fsnotify_mark mark;\n};\n\nstruct audit_reply {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff *skb;\n};\n\nstruct audit_rule_data {\n\t__u32 flags;\n\t__u32 action;\n\t__u32 field_count;\n\t__u32 mask[64];\n\t__u32 fields[64];\n\t__u32 values[64];\n\t__u32 fieldflags[64];\n\t__u32 buflen;\n\tchar buf[0];\n};\n\nstruct audit_sig_info {\n\tuid_t uid;\n\tpid_t pid;\n\tchar ctx[0];\n};\n\nstruct audit_status {\n\t__u32 mask;\n\t__u32 enabled;\n\t__u32 failure;\n\t__u32 pid;\n\t__u32 rate_limit;\n\t__u32 backlog_limit;\n\t__u32 lost;\n\t__u32 backlog;\n\tunion {\n\t\t__u32 version;\n\t\t__u32 feature_bitmap;\n\t};\n\t__u32 backlog_wait_time;\n\t__u32 backlog_wait_time_actual;\n};\n\nstruct audit_tree {\n\trefcount_t count;\n\tint goner;\n\tstruct audit_chunk *root;\n\tstruct list_head chunks;\n\tstruct list_head rules;\n\tstruct list_head list;\n\tstruct list_head same_root;\n\tstruct callback_head head;\n\tchar pathname[0];\n};\n\nstruct audit_tree_mark {\n\tstruct fsnotify_mark mark;\n\tstruct audit_chunk *chunk;\n};\n\nstruct audit_tree_refs {\n\tstruct audit_tree_refs *next;\n\tstruct audit_chunk *c[31];\n};\n\nstruct audit_tty_status {\n\t__u32 enabled;\n\t__u32 log_passwd;\n};\n\nstruct audit_watch {\n\trefcount_t count;\n\tdev_t dev;\n\tchar *path;\n\tlong unsigned int ino;\n\tstruct audit_parent *parent;\n\tstruct list_head wlist;\n\tstruct list_head rules;\n};\n\nstruct auditd_connection {\n\tstruct pid *pid;\n\tu32 portid;\n\tstruct net *net;\n\tstruct callback_head rcu;\n};\n\nstruct auth_cred {\n\tconst struct cred *cred;\n\tconst char *principal;\n};\n\nstruct auth_ops;\n\nstruct auth_domain {\n\tstruct kref ref;\n\tstruct hlist_node hash;\n\tchar *name;\n\tstruct auth_ops *flavour;\n\tstruct callback_head callback_head;\n};\n\nstruct svc_rqst;\n\nstruct auth_ops {\n\tchar *name;\n\tstruct module *owner;\n\tint flavour;\n\tenum svc_auth_status (*accept)(struct svc_rqst *);\n\tint (*release)(struct svc_rqst *);\n\tvoid (*domain_release)(struct auth_domain *);\n\tenum svc_auth_status (*set_client)(struct svc_rqst *);\n\trpc_authflavor_t (*pseudoflavor)(struct svc_rqst *);\n};\n\nstruct auto_mode_param {\n\tint qp_type;\n};\n\nstruct auto_movable_group_stats {\n\tlong unsigned int movable_pages;\n\tlong unsigned int req_kernel_early_pages;\n};\n\nstruct auto_movable_stats {\n\tlong unsigned int kernel_early_pages;\n\tlong unsigned int movable_pages;\n};\n\nstruct autofs_dev_ioctl {\n\t__u32 ver_major;\n\t__u32 ver_minor;\n\t__u32 size;\n\t__s32 ioctlfd;\n\tunion {\n\t\tstruct args_protover protover;\n\t\tstruct args_protosubver protosubver;\n\t\tstruct args_openmount openmount;\n\t\tstruct args_ready ready;\n\t\tstruct args_fail fail;\n\t\tstruct args_setpipefd setpipefd;\n\t\tstruct args_timeout timeout;\n\t\tstruct args_requester requester;\n\t\tstruct args_expire expire;\n\t\tstruct args_askumount askumount;\n\t\tstruct args_ismountpoint ismountpoint;\n\t};\n\tchar path[0];\n};\n\nstruct autofs_fs_context {\n\tkuid_t uid;\n\tkgid_t gid;\n\tint pgrp;\n\tbool pgrp_set;\n};\n\nstruct autofs_sb_info;\n\nstruct autofs_info {\n\tstruct dentry *dentry;\n\tint flags;\n\tstruct completion expire_complete;\n\tstruct list_head active;\n\tstruct list_head expiring;\n\tstruct autofs_sb_info *sbi;\n\tlong unsigned int exp_timeout;\n\tlong unsigned int last_used;\n\tint count;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_packet_hdr {\n\tint proto_version;\n\tint type;\n};\n\nstruct autofs_packet_expire {\n\tstruct autofs_packet_hdr hdr;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_expire_multi {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_missing {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nunion autofs_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_packet_missing missing;\n\tstruct autofs_packet_expire expire;\n\tstruct autofs_packet_expire_multi expire_multi;\n};\n\nstruct super_block;\n\nstruct autofs_wait_queue;\n\nstruct autofs_sb_info {\n\tu32 magic;\n\tint pipefd;\n\tstruct file *pipe;\n\tstruct pid *oz_pgrp;\n\tu64 mnt_ns_id;\n\tint version;\n\tint sub_version;\n\tint min_proto;\n\tint max_proto;\n\tunsigned int flags;\n\tlong unsigned int exp_timeout;\n\tunsigned int type;\n\tstruct super_block *sb;\n\tstruct mutex wq_mutex;\n\tstruct mutex pipe_mutex;\n\tspinlock_t fs_lock;\n\tstruct autofs_wait_queue *queues;\n\tspinlock_t lookup_lock;\n\tstruct list_head active_list;\n\tstruct list_head expiring_list;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_v5_packet {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\t__u32 dev;\n\t__u64 ino;\n\t__u32 uid;\n\t__u32 gid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 len;\n\tchar name[256];\n};\n\ntypedef struct autofs_v5_packet autofs_packet_expire_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_expire_indirect_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_indirect_t;\n\nunion autofs_v5_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_v5_packet v5_packet;\n\tautofs_packet_missing_indirect_t missing_indirect;\n\tautofs_packet_expire_indirect_t expire_indirect;\n\tautofs_packet_missing_direct_t missing_direct;\n\tautofs_packet_expire_direct_t expire_direct;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n};\n\nstruct autofs_wait_queue {\n\twait_queue_head_t queue;\n\tstruct autofs_wait_queue *next;\n\tautofs_wqt_t wait_queue_token;\n\tstruct qstr name;\n\tu32 offset;\n\tu32 dev;\n\tu64 ino;\n\tkuid_t uid;\n\tkgid_t gid;\n\tpid_t pid;\n\tpid_t tgid;\n\tint status;\n\tunsigned int wait_ctr;\n};\n\nstruct task_group;\n\nstruct autogroup {\n\tstruct kref kref;\n\tstruct task_group *tg;\n\tstruct rw_semaphore lock;\n\tlong unsigned int id;\n\tint nice;\n};\n\nstruct auxiliary_device {\n\tstruct device dev;\n\tconst char *name;\n\tu32 id;\n\tstruct {\n\t\tstruct xarray irqs;\n\t\tstruct mutex lock;\n\t\tbool irq_dir_exists;\n\t} sysfs;\n};\n\nstruct auxiliary_device_id {\n\tchar name[40];\n\tkernel_ulong_t driver_data;\n};\n\nstruct auxiliary_driver {\n\tint (*probe)(struct auxiliary_device *, const struct auxiliary_device_id *);\n\tvoid (*remove)(struct auxiliary_device *);\n\tvoid (*shutdown)(struct auxiliary_device *);\n\tint (*suspend)(struct auxiliary_device *, pm_message_t);\n\tint (*resume)(struct auxiliary_device *);\n\tconst char *name;\n\tstruct device_driver driver;\n\tconst struct auxiliary_device_id *id_table;\n};\n\nstruct auxiliary_irq_info {\n\tstruct device_attribute sysfs_attr;\n\tchar name[11];\n};\n\nstruct ave_desc {\n\tstruct sk_buff *skbs;\n\tdma_addr_t skbs_dma;\n\tsize_t skbs_dmalen;\n};\n\nstruct ave_desc_info {\n\tu32 ndesc;\n\tu32 daddr;\n\tu32 proc_idx;\n\tu32 done_idx;\n\tstruct ave_desc *desc;\n};\n\nstruct ave_stats {\n\tstruct u64_stats_sync syncp;\n\tu64 packets;\n\tu64 bytes;\n\tu64 errors;\n\tu64 dropped;\n\tu64 collisions;\n\tu64 fifo_errors;\n};\n\nstruct phy_device;\n\nstruct mii_bus;\n\nstruct ave_soc_data;\n\nstruct ave_private {\n\tvoid *base;\n\tint irq;\n\tint phy_id;\n\tunsigned int desc_size;\n\tu32 msg_enable;\n\tint nclks;\n\tstruct clk *clk[4];\n\tint nrsts;\n\tstruct reset_control *rst[2];\n\tphy_interface_t phy_mode;\n\tstruct phy_device *phydev;\n\tstruct mii_bus *mdio;\n\tstruct regmap *regmap;\n\tunsigned int pinmode_mask;\n\tunsigned int pinmode_val;\n\tu32 wolopts;\n\tstruct ave_stats stats_rx;\n\tstruct ave_stats stats_tx;\n\tstruct net_device *ndev;\n\tstruct napi_struct napi_rx;\n\tstruct napi_struct napi_tx;\n\tstruct ave_desc_info rx;\n\tstruct ave_desc_info tx;\n\tint pause_auto;\n\tint pause_rx;\n\tint pause_tx;\n\tconst struct ave_soc_data *data;\n};\n\nstruct ave_soc_data {\n\tbool is_desc_64bit;\n\tconst char *clock_names[4];\n\tconst char *reset_names[2];\n\tint (*get_pinmode)(struct ave_private *, phy_interface_t, u32);\n};\n\nstruct regmap_irq_chip_data;\n\nstruct mfd_cell;\n\nstruct regmap_irq_chip;\n\nstruct axp20x_dev {\n\tstruct device *dev;\n\tint irq;\n\tlong unsigned int irq_flags;\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip_data *regmap_irqc;\n\tenum axp20x_variants variant;\n\tint nr_cells;\n\tconst struct mfd_cell *cells;\n\tconst struct regmap_config *regmap_cfg;\n\tconst struct regmap_irq_chip *regmap_irq_chip;\n};\n\nstruct backing_aio {\n\tstruct kiocb iocb;\n\trefcount_t ref;\n\tstruct kiocb *orig_iocb;\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n\tstruct work_struct work;\n\tlong int res;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct backing_dev_info;\n\nstruct cgroup_subsys_state;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n\tstruct percpu_ref refcnt;\n\tstruct fprop_local_percpu memcg_completions;\n\tstruct cgroup_subsys_state *memcg_css;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct list_head memcg_node;\n\tstruct list_head blkcg_node;\n\tstruct list_head b_attached;\n\tstruct list_head offline_node;\n\tstruct work_struct switch_work;\n\tstruct llist_head switch_wbs_ctxs;\n\tunion {\n\t\tstruct work_struct release_work;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\tstruct xarray cgwb_tree;\n\tstruct mutex cgwb_release_mutex;\n\tstruct rw_semaphore wb_switch_rwsem;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tloff_t prev_pos;\n};\n\nstruct file_operations;\n\nstruct fown_struct;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\tvoid *f_security;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backing_file_ctx {\n\tconst struct cred *cred;\n\tvoid (*accessed)(struct file *);\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct balloon_dev_info {\n\tlong unsigned int isolated_pages;\n\tstruct list_head pages;\n\tint (*migratepage)(struct balloon_dev_info *, struct page *, struct page *, enum migrate_mode);\n\tbool adjust_managed_page_count;\n};\n\nstruct balloon_stats {\n\tlong unsigned int current_pages;\n\tlong unsigned int target_pages;\n\tlong unsigned int target_unpopulated;\n\tlong unsigned int balloon_low;\n\tlong unsigned int balloon_high;\n\tlong unsigned int total_pages;\n\tlong unsigned int schedule_delay;\n\tlong unsigned int max_schedule_delay;\n\tlong unsigned int retry_count;\n\tlong unsigned int max_retry_count;\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nstruct dmaengine_result;\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dmaengine_unmap_data;\n\nstruct dma_descriptor_metadata_ops;\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n\tstruct dma_async_tx_descriptor *next;\n\tstruct dma_async_tx_descriptor *parent;\n\tspinlock_t lock;\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\nstruct virt_dma_desc {\n\tstruct dma_async_tx_descriptor tx;\n\tstruct dmaengine_result tx_result;\n\tstruct list_head node;\n};\n\nstruct bam_desc_hw {\n\t__le32 addr;\n\t__le16 size;\n\t__le16 flags;\n};\n\nstruct bam_async_desc {\n\tstruct virt_dma_desc vd;\n\tu32 num_desc;\n\tu32 xfer_len;\n\tu16 flags;\n\tstruct bam_desc_hw *curr_desc;\n\tstruct list_head desc_node;\n\tenum dma_transfer_direction dir;\n\tsize_t length;\n\tstruct bam_desc_hw desc[0];\n};\n\nstruct dma_device;\n\nstruct dma_chan_dev;\n\nstruct dma_chan_percpu;\n\nstruct dma_router;\n\nstruct dma_chan {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct virt_dma_chan {\n\tstruct dma_chan chan;\n\tstruct tasklet_struct task;\n\tvoid (*desc_free)(struct virt_dma_desc *);\n\tspinlock_t lock;\n\tstruct list_head desc_allocated;\n\tstruct list_head desc_submitted;\n\tstruct list_head desc_issued;\n\tstruct list_head desc_completed;\n\tstruct list_head desc_terminated;\n\tstruct virt_dma_desc *cyclic;\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n};\n\nstruct bam_device;\n\nstruct bam_chan {\n\tstruct virt_dma_chan vc;\n\tstruct bam_device *bdev;\n\tu32 id;\n\tstruct dma_slave_config slave;\n\tstruct bam_desc_hw *fifo_virt;\n\tdma_addr_t fifo_phys;\n\tshort unsigned int head;\n\tshort unsigned int tail;\n\tunsigned int initialized;\n\tunsigned int paused;\n\tunsigned int reconfigure;\n\tstruct list_head desc_list;\n\tstruct list_head node;\n};\n\nstruct bam_cmd_element {\n\t__le32 cmd_and_addr;\n\t__le32 data;\n\t__le32 mask;\n\t__le32 reserved;\n};\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nstruct dma_vec;\n\nstruct dma_interleaved_template;\n\nstruct dma_slave_caps;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan *);\n\tint (*device_router_config)(struct dma_chan *);\n\tvoid (*device_free_chan_resources)(struct dma_chan *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_peripheral_dma_vec)(struct dma_chan *, const struct dma_vec *, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan *, struct dma_interleaved_template *, long unsigned int);\n\tvoid (*device_caps)(struct dma_chan *, struct dma_slave_caps *);\n\tint (*device_config)(struct dma_chan *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan *);\n\tint (*device_resume)(struct dma_chan *);\n\tint (*device_terminate_all)(struct dma_chan *);\n\tvoid (*device_synchronize)(struct dma_chan *);\n\tenum dma_status (*device_tx_status)(struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct reg_offset_data;\n\nstruct bam_device {\n\tvoid *regs;\n\tstruct device *dev;\n\tstruct dma_device common;\n\tstruct bam_chan *channels;\n\tu32 num_channels;\n\tu32 num_ees;\n\tu32 ee;\n\tbool controlled_remotely;\n\tbool powered_remotely;\n\tu32 active_channels;\n\tconst struct reg_offset_data *layout;\n\tstruct clk *bamclk;\n\tint irq;\n\tstruct tasklet_struct task;\n};\n\nstruct bam_transaction {\n\tstruct bam_cmd_element *bam_ce;\n\tstruct scatterlist *cmd_sgl;\n\tstruct scatterlist *data_sgl;\n\tstruct dma_async_tx_descriptor *last_data_desc;\n\tstruct dma_async_tx_descriptor *last_cmd_desc;\n\tstruct completion txn_done;\n\tunsigned int bam_ce_nitems;\n\tunsigned int cmd_sgl_nitems;\n\tunsigned int data_sgl_nitems;\n\tunion {\n\t\tstruct {\n\t\t\tu32 bam_ce_pos;\n\t\t\tu32 bam_ce_start;\n\t\t\tu32 cmd_sgl_pos;\n\t\t\tu32 cmd_sgl_start;\n\t\t\tu32 tx_sgl_pos;\n\t\t\tu32 tx_sgl_start;\n\t\t\tu32 rx_sgl_pos;\n\t\t\tu32 rx_sgl_start;\n\t\t};\n\t\tstruct {\n\t\t\tu32 bam_ce_pos;\n\t\t\tu32 bam_ce_start;\n\t\t\tu32 cmd_sgl_pos;\n\t\t\tu32 cmd_sgl_start;\n\t\t\tu32 tx_sgl_pos;\n\t\t\tu32 tx_sgl_start;\n\t\t\tu32 rx_sgl_pos;\n\t\t\tu32 rx_sgl_start;\n\t\t} bam_positions;\n\t};\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct tcs_cmd;\n\nstruct tcs_request {\n\tenum rpmh_state state;\n\tu32 wait_for_compl;\n\tu32 num_cmds;\n\tstruct tcs_cmd *cmds;\n};\n\nstruct tcs_cmd {\n\tu32 addr;\n\tu32 data;\n\tu32 wait;\n};\n\nstruct rpmh_request {\n\tstruct tcs_request msg;\n\tstruct tcs_cmd cmd[16];\n\tstruct completion *completion;\n\tconst struct device *dev;\n\tbool needs_free;\n};\n\nstruct batch_cache_req {\n\tstruct list_head list;\n\tint count;\n\tstruct rpmh_request rpm_msgs[0];\n};\n\nstruct local_lock {};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct mdiobb_ops;\n\nstruct mdiobb_ctrl {\n\tconst struct mdiobb_ops *ops;\n\tunsigned int override_op_c22;\n\tu8 op_c22_read;\n\tu8 op_c22_write;\n};\n\nstruct bb_info {\n\tvoid (*set_gate)(void *);\n\tstruct mdiobb_ctrl ctrl;\n\tvoid *addr;\n};\n\nstruct bcm2835_dma_cb;\n\nstruct bcm2835_cb_entry {\n\tstruct bcm2835_dma_cb *cb;\n\tdma_addr_t paddr;\n};\n\nstruct bcm2835_desc;\n\nstruct dma_pool;\n\nstruct bcm2835_chan {\n\tstruct virt_dma_chan vc;\n\tstruct dma_slave_config cfg;\n\tunsigned int dreq;\n\tint ch;\n\tstruct bcm2835_desc *desc;\n\tstruct dma_pool *cb_pool;\n\tvoid *chan_base;\n\tint irq_number;\n\tunsigned int irq_flags;\n\tbool is_lite_channel;\n};\n\nstruct bcm2835_cprman;\n\nstruct bcm2835_clk_desc {\n\tstruct clk_hw * (*clk_register)(struct bcm2835_cprman *, const void *);\n\tunsigned int supported;\n\tconst void *data;\n};\n\nstruct bcm2835_clock_data;\n\nstruct bcm2835_clock {\n\tstruct clk_hw hw;\n\tstruct bcm2835_cprman *cprman;\n\tconst struct bcm2835_clock_data *data;\n};\n\nstruct bcm2835_clock_data {\n\tconst char *name;\n\tconst char * const *parents;\n\tint num_mux_parents;\n\tunsigned int set_rate_parent;\n\tu32 ctl_reg;\n\tu32 div_reg;\n\tu32 int_bits;\n\tu32 frac_bits;\n\tu32 flags;\n\tbool is_vpu_clock;\n\tbool is_mash_clock;\n\tbool low_jitter;\n\tu32 tcnt_mux;\n\tbool round_up;\n};\n\nstruct clk_hw_onecell_data {\n\tunsigned int num;\n\tstruct clk_hw *hws[0];\n};\n\nstruct bcm2835_cprman {\n\tstruct device *dev;\n\tvoid *regs;\n\tspinlock_t regs_lock;\n\tunsigned int soc;\n\tconst char *real_parent_names[7];\n\tstruct clk_hw_onecell_data onecell;\n};\n\nstruct bcm2835_desc {\n\tstruct bcm2835_chan *c;\n\tstruct virt_dma_desc vd;\n\tenum dma_transfer_direction dir;\n\tunsigned int frames;\n\tsize_t size;\n\tbool cyclic;\n\tstruct bcm2835_cb_entry cb_list[0];\n};\n\nstruct bcm2835_dma_cb {\n\tuint32_t info;\n\tuint32_t src;\n\tuint32_t dst;\n\tuint32_t length;\n\tuint32_t stride;\n\tuint32_t next;\n\tuint32_t pad[2];\n};\n\nstruct bcm2835_dmadev {\n\tstruct dma_device ddev;\n\tvoid *base;\n\tdma_addr_t zero_page;\n};\n\nstruct bcm2835_gate_data {\n\tconst char *name;\n\tconst char *parent;\n\tu32 ctl_reg;\n};\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct mmc_request;\n\nstruct mmc_command;\n\nstruct mmc_data;\n\nstruct bcm2835_host {\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tvoid *ioaddr;\n\tu32 phys_addr;\n\tstruct clk *clk;\n\tstruct platform_device *pdev;\n\tunsigned int clock;\n\tunsigned int max_clk;\n\tstruct work_struct dma_work;\n\tstruct delayed_work timeout_work;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int blocks;\n\tint irq;\n\tu32 ns_per_fifo_word;\n\tu32 hcfg;\n\tu32 cdiv;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tbool data_complete: 1;\n\tbool use_busy: 1;\n\tbool use_sbc: 1;\n\tbool irq_block;\n\tbool irq_busy;\n\tbool irq_data;\n\tstruct dma_chan *dma_chan_rxtx;\n\tstruct dma_chan *dma_chan;\n\tstruct dma_slave_config dma_cfg_rx;\n\tstruct dma_slave_config dma_cfg_tx;\n\tstruct dma_async_tx_descriptor *dma_desc;\n\tu32 dma_dir;\n\tu32 drain_words;\n\tstruct page *drain_page;\n\tu32 drain_offset;\n\tbool use_dma;\n};\n\nstruct bcm2835_mbox {\n\tvoid *regs;\n\tspinlock_t lock;\n\tstruct mbox_controller controller;\n};\n\nstruct pinctrl_gpio_range {\n\tstruct list_head node;\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int base;\n\tunsigned int pin_base;\n\tunsigned int npins;\n\tconst unsigned int *pins;\n\tstruct gpio_chip *gc;\n};\n\nstruct bcm2835_pinctrl {\n\tstruct device *dev;\n\tvoid *base;\n\tint *wake_irq;\n\tlong unsigned int enabled_irq_map[2];\n\tunsigned int irq_type[58];\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct pinctrl_gpio_range gpio_range;\n\traw_spinlock_t irq_lock[2];\n\tspinlock_t fsel_lock;\n};\n\nstruct bcm2835_pll_data;\n\nstruct bcm2835_pll {\n\tstruct clk_hw hw;\n\tstruct bcm2835_cprman *cprman;\n\tconst struct bcm2835_pll_data *data;\n};\n\nstruct bcm2835_pll_ana_bits {\n\tu32 mask0;\n\tu32 set0;\n\tu32 mask1;\n\tu32 set1;\n\tu32 mask3;\n\tu32 set3;\n\tu32 fb_prediv_mask;\n};\n\nstruct bcm2835_pll_data {\n\tconst char *name;\n\tu32 cm_ctrl_reg;\n\tu32 a2w_ctrl_reg;\n\tu32 frac_reg;\n\tu32 ana_reg_base;\n\tu32 reference_enable_mask;\n\tu32 lock_mask;\n\tu32 flags;\n\tconst struct bcm2835_pll_ana_bits *ana;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int max_fb_rate;\n};\n\nstruct clk_div_table;\n\nstruct clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu16 flags;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct bcm2835_pll_divider_data;\n\nstruct bcm2835_pll_divider {\n\tstruct clk_divider div;\n\tstruct bcm2835_cprman *cprman;\n\tconst struct bcm2835_pll_divider_data *data;\n};\n\nstruct bcm2835_pll_divider_data {\n\tconst char *name;\n\tconst char *source_pll;\n\tu32 cm_reg;\n\tu32 a2w_reg;\n\tu32 load_mask;\n\tu32 hold_mask;\n\tu32 fixed_divider;\n\tu32 flags;\n};\n\nstruct bcm2835_pm {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *asb;\n\tvoid *rpivid_asb;\n};\n\ntypedef struct generic_pm_domain * (*genpd_xlate_t)(const struct of_phandle_args *, void *);\n\nstruct genpd_onecell_data {\n\tstruct generic_pm_domain **domains;\n\tunsigned int num_domains;\n\tgenpd_xlate_t xlate;\n};\n\nstruct bcm2835_power;\n\nstruct bcm2835_power_domain {\n\tstruct generic_pm_domain base;\n\tstruct bcm2835_power *power;\n\tu32 domain;\n\tstruct clk *clk;\n};\n\nstruct bcm2835_power {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *asb;\n\tvoid *rpivid_asb;\n\tstruct genpd_onecell_data pd_xlate;\n\tstruct bcm2835_power_domain domains[13];\n\tstruct reset_controller_dev reset;\n};\n\nstruct bcm2835_rng_of_data {\n\tbool mask_interrupts;\n};\n\nstruct bcm2835_rng_priv {\n\tstruct hwrng rng;\n\tvoid *base;\n\tbool mask_interrupts;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n};\n\nstruct bcm2835_wdt {\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct bcm2835aux_data {\n\tstruct clk *clk;\n\tint line;\n\tu32 cntl;\n};\n\nstruct bcm2836_arm_irqchip_intc {\n\tstruct irq_domain *domain;\n\tvoid *base;\n};\n\nstruct bcm4908_enet_dma_ring_bd;\n\nstruct bcm4908_enet_dma_ring_slot;\n\nstruct bcm4908_enet_dma_ring {\n\tint is_tx;\n\tint read_idx;\n\tint write_idx;\n\tint length;\n\tu16 cfg_block;\n\tu16 st_ram_block;\n\tstruct napi_struct napi;\n\tunion {\n\t\tvoid *cpu_addr;\n\t\tstruct bcm4908_enet_dma_ring_bd *buf_desc;\n\t};\n\tdma_addr_t dma_addr;\n\tstruct bcm4908_enet_dma_ring_slot *slots;\n};\n\nstruct bcm4908_enet {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tvoid *base;\n\tint irq_tx;\n\tstruct bcm4908_enet_dma_ring tx_ring;\n\tstruct bcm4908_enet_dma_ring rx_ring;\n};\n\nstruct bcm4908_enet_dma_ring_bd {\n\t__le32 ctl;\n\t__le32 addr;\n};\n\nstruct bcm4908_enet_dma_ring_slot {\n\tunion {\n\t\tvoid *buf;\n\t\tstruct sk_buff *skb;\n\t};\n\tunsigned int len;\n\tdma_addr_t dma_addr;\n};\n\nstruct bcm4908_pinctrl {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct mutex mutex;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_desc pctldesc;\n};\n\nstruct bcm4908_pinctrl_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tconst unsigned int num_groups;\n};\n\nstruct bcm4908_pinctrl_pin_setup;\n\nstruct bcm4908_pinctrl_grp {\n\tconst char *name;\n\tconst struct bcm4908_pinctrl_pin_setup *pins;\n\tconst unsigned int num_pins;\n};\n\nstruct bcm4908_pinctrl_pin_setup {\n\tunsigned int number;\n\tunsigned int function;\n};\n\nstruct bcm63138_leds;\n\nstruct bcm63138_led {\n\tstruct bcm63138_leds *leds;\n\tstruct led_classdev cdev;\n\tu32 pin;\n\tbool active_low;\n};\n\nstruct bcm63138_leds {\n\tstruct device *dev;\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct bcm7038_l1_cpu;\n\nstruct bcm7038_l1_chip {\n\traw_spinlock_t lock;\n\tunsigned int n_words;\n\tstruct irq_domain *domain;\n\tstruct bcm7038_l1_cpu *cpus[512];\n\tstruct list_head list;\n\tu32 wake_mask[8];\n\tu32 irq_fwd_mask[8];\n\tu8 affinity[256];\n};\n\nstruct bcm7038_l1_cpu {\n\tvoid *map_base;\n\tu32 mask_cache[0];\n};\n\nstruct bcm7120_l2_intc_data;\n\nstruct bcm7120_l1_intc_data {\n\tstruct bcm7120_l2_intc_data *b;\n\tu32 irq_map_mask[4];\n};\n\nstruct bcm7120_l2_intc_data {\n\tunsigned int n_words;\n\tvoid *map_base[8];\n\tvoid *pair_base[4];\n\tint en_offset[4];\n\tint stat_offset[4];\n\tstruct irq_domain *domain;\n\tbool can_wake;\n\tu32 irq_fwd_mask[4];\n\tstruct bcm7120_l1_intc_data *l1_data;\n\tint num_parent_irqs;\n\tconst __be32 *map_mask_prop;\n};\n\nstruct bcm74110_mbox_chan;\n\nstruct bcm74110_mbox {\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tint tx_chan;\n\tint rx_chan;\n\tint rx_irq;\n\tstruct list_head rx_svc_init_list;\n\tspinlock_t rx_svc_list_lock;\n\tstruct mbox_controller controller;\n\tstruct bcm74110_mbox_chan *mbox_chan;\n};\n\nstruct bcm74110_mbox_chan {\n\tstruct bcm74110_mbox *mbox;\n\tbool en;\n\tint slot;\n\tint type;\n};\n\nstruct bcm74110_mbox_msg {\n\tstruct list_head list_entry;\n\tu32 msg;\n};\n\nstruct bcm74110_priv {\n\tvoid *base;\n};\n\nstruct bcm_db {\n\t__le32 unit;\n\t__le16 width;\n\tu8 vcd;\n\tu8 reserved;\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n\tstruct regulator *bus_regulator;\n\tstruct dentry *debugfs;\n\tlong unsigned int addrs_in_instantiation[2];\n};\n\nstruct i2c_msg;\n\nstruct i2c_client;\n\nstruct bcm_iproc_i2c_dev {\n\tstruct device *device;\n\tenum bcm_iproc_i2c_type type;\n\tint irq;\n\tvoid *base;\n\tvoid *idm_base;\n\tu32 ape_addr_mask;\n\tspinlock_t idm_lock;\n\tstruct i2c_adapter adapter;\n\tunsigned int bus_speed;\n\tstruct completion done;\n\tint xfer_is_done;\n\tstruct i2c_msg *msg;\n\tstruct i2c_client *slave;\n\tunsigned int tx_bytes;\n\tunsigned int rx_bytes;\n\tunsigned int thld_bytes;\n\tbool slave_rx_only;\n\tbool rx_start_rcvd;\n\tbool slave_read_complete;\n\tu32 tx_underrun;\n\tu32 slave_int_mask;\n\tstruct tasklet_struct slave_rx_tasklet;\n};\n\nstruct bcm_qspi_soc_intc {\n\tvoid (*bcm_qspi_int_ack)(struct bcm_qspi_soc_intc *, int);\n\tvoid (*bcm_qspi_int_set)(struct bcm_qspi_soc_intc *, int, bool);\n\tu32 (*bcm_qspi_get_int_status)(struct bcm_qspi_soc_intc *);\n};\n\nstruct bcm_iproc_intc {\n\tstruct bcm_qspi_soc_intc soc_intc;\n\tstruct platform_device *pdev;\n\tvoid *int_reg;\n\tvoid *int_status_reg;\n\tspinlock_t soclock;\n\tbool big_endian;\n};\n\nstruct bcm_plat_data {\n\tconst struct gpio_chip *gpio_chip;\n\tconst struct pinctrl_desc *pctl_desc;\n\tconst struct pinctrl_gpio_range *gpio_range;\n};\n\nstruct bcm_pmb {\n\tstruct device *dev;\n\tvoid *base;\n\tspinlock_t lock;\n\tbool little_endian;\n\tstruct genpd_onecell_data genpd_onecell_data;\n};\n\nstruct bcm_pmb_pd_data {\n\tconst char * const name;\n\tint id;\n\tu8 bus;\n\tu8 device;\n};\n\nstruct bcm_pmb_pm_domain {\n\tstruct bcm_pmb *pmb;\n\tconst struct bcm_pmb_pd_data *data;\n\tstruct generic_pm_domain genpd;\n};\n\nstruct bcm_qspi_parms {\n\tu32 speed_hz;\n\tu8 mode;\n\tu8 bits_per_word;\n};\n\nstruct spi_transfer;\n\nstruct qspi_trans {\n\tstruct spi_transfer *trans;\n\tint byte;\n\tbool mspi_last_trans;\n};\n\nstruct bcm_xfer_mode {\n\tbool flex_mode;\n\tunsigned int width;\n\tunsigned int addrlen;\n\tunsigned int hp;\n};\n\nstruct spi_mem_op;\n\nstruct bcm_qspi_dev_id;\n\nstruct bcm_qspi {\n\tstruct platform_device *pdev;\n\tstruct spi_controller *host;\n\tstruct clk *clk;\n\tu32 base_clk;\n\tu32 max_speed_hz;\n\tvoid *base[3];\n\tstruct bcm_qspi_soc_intc *soc_intc;\n\tstruct bcm_qspi_parms last_parms;\n\tstruct qspi_trans trans_pos;\n\tint curr_cs;\n\tint bspi_maj_rev;\n\tint bspi_min_rev;\n\tint bspi_enabled;\n\tconst struct spi_mem_op *bspi_rf_op;\n\tu32 bspi_rf_op_idx;\n\tu32 bspi_rf_op_len;\n\tu32 bspi_rf_op_status;\n\tstruct bcm_xfer_mode xfer_mode;\n\tu32 s3_strap_override_ctrl;\n\tbool bspi_mode;\n\tbool big_endian;\n\tint num_irqs;\n\tstruct bcm_qspi_dev_id *dev_ids;\n\tstruct completion mspi_done;\n\tstruct completion bspi_done;\n\tu8 mspi_maj_rev;\n\tu8 mspi_min_rev;\n\tbool mspi_spcr3_sysclk;\n};\n\nstruct bcm_qspi_data {\n\tbool has_mspi_rev;\n\tbool has_spcr3_sysclk;\n};\n\nstruct bcm_qspi_irq;\n\nstruct bcm_qspi_dev_id {\n\tconst struct bcm_qspi_irq *irqp;\n\tvoid *dev;\n};\n\nstruct bcm_qspi_irq {\n\tconst char *irq_name;\n\tconst irq_handler_t irq_handler;\n\tint irq_source;\n\tu32 mask;\n};\n\nstruct bcm_usb_phy_cfg {\n\tuint32_t type;\n\tuint32_t version;\n\tvoid *regs;\n\tstruct phy *phy;\n\tconst u8 *offset;\n};\n\nstruct bcm_voter {\n\tstruct device *dev;\n\tstruct device_node *np;\n\tstruct mutex lock;\n\tstruct list_head commit_list;\n\tstruct list_head ws_list;\n\tstruct list_head voter_node;\n\tu32 tcs_wait;\n};\n\nstruct bcma_boardinfo {\n\tu16 vendor;\n\tu16 type;\n};\n\nstruct bcma_chipinfo {\n\tu16 id;\n\tu8 rev;\n\tu8 pkg;\n};\n\nstruct bcma_device;\n\nstruct bcma_chipcommon_pmu {\n\tstruct bcma_device *core;\n\tu8 rev;\n\tu32 crystalfreq;\n};\n\nstruct bcma_drv_cc {\n\tstruct bcma_device *core;\n\tu32 status;\n\tu32 capabilities;\n\tu32 capabilities_ext;\n\tu8 setup_done: 1;\n\tu8 early_setup_done: 1;\n\tu16 fast_pwrup_delay;\n\tstruct bcma_chipcommon_pmu pmu;\n\tu32 ticks_per_ms;\n\tstruct platform_device *watchdog;\n\tspinlock_t gpio_lock;\n};\n\nstruct bcma_drv_cc_b {\n\tstruct bcma_device *core;\n\tu8 setup_done: 1;\n\tvoid *mii;\n};\n\nstruct bcma_drv_pci {\n\tstruct bcma_device *core;\n\tu8 early_setup_done: 1;\n\tu8 setup_done: 1;\n\tu8 hostmode: 1;\n};\n\nstruct bcma_drv_pcie2 {\n\tstruct bcma_device *core;\n\tu16 reqsize;\n};\n\nstruct bcma_drv_mips {\n\tstruct bcma_device *core;\n\tu8 setup_done: 1;\n\tu8 early_setup_done: 1;\n};\n\nstruct bcma_drv_gmac_cmn {\n\tstruct bcma_device *core;\n\tstruct mutex phy_mutex;\n};\n\nstruct ssb_sprom_core_pwr_info {\n\tu8 itssi_2g;\n\tu8 itssi_5g;\n\tu8 maxpwr_2g;\n\tu8 maxpwr_5gl;\n\tu8 maxpwr_5g;\n\tu8 maxpwr_5gh;\n\tu16 pa_2g[4];\n\tu16 pa_5gl[4];\n\tu16 pa_5g[4];\n\tu16 pa_5gh[4];\n};\n\nstruct ssb_sprom {\n\tu8 revision;\n\tshort: 0;\n\tu8 il0mac[6];\n\tu8 et0mac[6];\n\tu8 et1mac[6];\n\tu8 et2mac[6];\n\tu8 et0phyaddr;\n\tu8 et1phyaddr;\n\tu8 et2phyaddr;\n\tu8 et0mdcport;\n\tu8 et1mdcport;\n\tu8 et2mdcport;\n\tu16 dev_id;\n\tu16 board_rev;\n\tu16 board_num;\n\tu16 board_type;\n\tu8 country_code;\n\tchar alpha2[2];\n\tu8 leddc_on_time;\n\tu8 leddc_off_time;\n\tu8 ant_available_a;\n\tu8 ant_available_bg;\n\tu16 pa0b0;\n\tu16 pa0b1;\n\tu16 pa0b2;\n\tu16 pa1b0;\n\tu16 pa1b1;\n\tu16 pa1b2;\n\tu16 pa1lob0;\n\tu16 pa1lob1;\n\tu16 pa1lob2;\n\tu16 pa1hib0;\n\tu16 pa1hib1;\n\tu16 pa1hib2;\n\tu8 gpio0;\n\tu8 gpio1;\n\tu8 gpio2;\n\tu8 gpio3;\n\tu8 maxpwr_bg;\n\tu8 maxpwr_al;\n\tu8 maxpwr_a;\n\tu8 maxpwr_ah;\n\tu8 itssi_a;\n\tu8 itssi_bg;\n\tu8 tri2g;\n\tu8 tri5gl;\n\tu8 tri5g;\n\tu8 tri5gh;\n\tu8 txpid2g[4];\n\tu8 txpid5gl[4];\n\tu8 txpid5g[4];\n\tu8 txpid5gh[4];\n\ts8 rxpo2g;\n\ts8 rxpo5g;\n\tu8 rssisav2g;\n\tu8 rssismc2g;\n\tu8 rssismf2g;\n\tu8 bxa2g;\n\tu8 rssisav5g;\n\tu8 rssismc5g;\n\tu8 rssismf5g;\n\tu8 bxa5g;\n\tu16 cck2gpo;\n\tu32 ofdm2gpo;\n\tu32 ofdm5glpo;\n\tu32 ofdm5gpo;\n\tu32 ofdm5ghpo;\n\tu32 boardflags;\n\tu32 boardflags2;\n\tu32 boardflags3;\n\tu16 boardflags_lo;\n\tu16 boardflags_hi;\n\tu16 boardflags2_lo;\n\tu16 boardflags2_hi;\n\tstruct ssb_sprom_core_pwr_info core_pwr_info[4];\n\tstruct {\n\t\ts8 a0;\n\t\ts8 a1;\n\t\ts8 a2;\n\t\ts8 a3;\n\t} antenna_gain;\n\tstruct {\n\t\tstruct {\n\t\t\tu8 tssipos;\n\t\t\tu8 extpa_gain;\n\t\t\tu8 pdet_range;\n\t\t\tu8 tr_iso;\n\t\t\tu8 antswlut;\n\t\t} ghz2;\n\t\tstruct {\n\t\t\tu8 tssipos;\n\t\t\tu8 extpa_gain;\n\t\t\tu8 pdet_range;\n\t\t\tu8 tr_iso;\n\t\t\tu8 antswlut;\n\t\t} ghz5;\n\t} fem;\n\tu16 mcs2gpo[8];\n\tu16 mcs5gpo[8];\n\tu16 mcs5glpo[8];\n\tu16 mcs5ghpo[8];\n\tu8 opo;\n\tu8 rxgainerr2ga[3];\n\tu8 rxgainerr5gla[3];\n\tu8 rxgainerr5gma[3];\n\tu8 rxgainerr5gha[3];\n\tu8 rxgainerr5gua[3];\n\tu8 noiselvl2ga[3];\n\tu8 noiselvl5gla[3];\n\tu8 noiselvl5gma[3];\n\tu8 noiselvl5gha[3];\n\tu8 noiselvl5gua[3];\n\tu8 regrev;\n\tu8 txchain;\n\tu8 rxchain;\n\tu8 antswitch;\n\tu16 cddpo;\n\tu16 stbcpo;\n\tu16 bw40po;\n\tu16 bwduppo;\n\tu8 tempthresh;\n\tu8 tempoffset;\n\tu16 rawtempsense;\n\tu8 measpower;\n\tu8 tempsense_slope;\n\tu8 tempcorrx;\n\tu8 tempsense_option;\n\tu8 freqoffset_corr;\n\tu8 iqcal_swp_dis;\n\tu8 hw_iqcal_en;\n\tu8 elna2g;\n\tu8 elna5g;\n\tu8 phycal_tempdelta;\n\tu8 temps_period;\n\tu8 temps_hysteresis;\n\tu8 measpower1;\n\tu8 measpower2;\n\tu8 pcieingress_war;\n\tu16 cckbw202gpo;\n\tu16 cckbw20ul2gpo;\n\tu32 legofdmbw202gpo;\n\tu32 legofdmbw20ul2gpo;\n\tu32 legofdmbw205glpo;\n\tu32 legofdmbw20ul5glpo;\n\tu32 legofdmbw205gmpo;\n\tu32 legofdmbw20ul5gmpo;\n\tu32 legofdmbw205ghpo;\n\tu32 legofdmbw20ul5ghpo;\n\tu32 mcsbw202gpo;\n\tu32 mcsbw20ul2gpo;\n\tu32 mcsbw402gpo;\n\tu32 mcsbw205glpo;\n\tu32 mcsbw20ul5glpo;\n\tu32 mcsbw405glpo;\n\tu32 mcsbw205gmpo;\n\tu32 mcsbw20ul5gmpo;\n\tu32 mcsbw405gmpo;\n\tu32 mcsbw205ghpo;\n\tu32 mcsbw20ul5ghpo;\n\tu32 mcsbw405ghpo;\n\tu16 mcs32po;\n\tu16 legofdm40duppo;\n\tu8 sar2g;\n\tu8 sar5g;\n};\n\nstruct bcma_host_ops;\n\nstruct bcma_bus {\n\tstruct device *dev;\n\tvoid *mmio;\n\tconst struct bcma_host_ops *ops;\n\tenum bcma_hosttype hosttype;\n\tbool host_is_pcie2;\n\tstruct pci_dev *host_pci;\n\tstruct bcma_chipinfo chipinfo;\n\tstruct bcma_boardinfo boardinfo;\n\tstruct bcma_device *mapped_core;\n\tstruct list_head cores;\n\tu8 nr_cores;\n\tu8 num;\n\tstruct bcma_drv_cc drv_cc;\n\tstruct bcma_drv_cc_b drv_cc_b;\n\tstruct bcma_drv_pci drv_pci[2];\n\tstruct bcma_drv_pcie2 drv_pcie2;\n\tstruct bcma_drv_mips drv_mips;\n\tstruct bcma_drv_gmac_cmn drv_gmac_cmn;\n\tstruct ssb_sprom sprom;\n};\n\nstruct bcma_device_id {\n\t__u16 manuf;\n\t__u16 id;\n\t__u8 rev;\n\t__u8 class;\n};\n\nstruct bcma_device {\n\tstruct bcma_bus *bus;\n\tstruct bcma_device_id id;\n\tstruct device dev;\n\tstruct device *dma_dev;\n\tunsigned int irq;\n\tbool dev_registered;\n\tu8 core_index;\n\tu8 core_unit;\n\tu32 addr;\n\tu32 addr_s[8];\n\tu32 wrap;\n\tvoid *io_addr;\n\tvoid *io_wrap;\n\tvoid *drvdata;\n\tstruct list_head list;\n};\n\nstruct bcma_host_ops {\n\tu8 (*read8)(struct bcma_device *, u16);\n\tu16 (*read16)(struct bcma_device *, u16);\n\tu32 (*read32)(struct bcma_device *, u16);\n\tvoid (*write8)(struct bcma_device *, u16, u8);\n\tvoid (*write16)(struct bcma_device *, u16, u16);\n\tvoid (*write32)(struct bcma_device *, u16, u32);\n\tu32 (*aread32)(struct bcma_device *, u16);\n\tvoid (*awrite32)(struct bcma_device *, u16, u32);\n};\n\nstruct bcmasp_desc {\n\tu64 buf;\n\tu32 size;\n\tu32 flags;\n};\n\nstruct bcmasp_res {\n\tvoid *umac;\n\tvoid *umac2fb;\n\tvoid *rgmii;\n\tvoid *tx_spb_ctrl;\n\tvoid *tx_spb_top;\n\tvoid *tx_epkt_core;\n\tvoid *tx_pause_ctrl;\n};\n\nstruct bcmasp_intf_stats64 {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_errors;\n\tu64_stats_t rx_dropped;\n\tu64_stats_t rx_crc_errs;\n\tu64_stats_t rx_sym_errs;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct bcmasp_mib_counters {\n\tu32 edpkt_ts;\n\tu32 edpkt_rx_pkt_cnt;\n\tu32 edpkt_hdr_ext_cnt;\n\tu32 edpkt_hdr_out_cnt;\n\tu32 umac_frm_cnt;\n\tu32 fb_frm_cnt;\n\tu32 fb_rx_fifo_depth;\n\tu32 fb_out_frm_cnt;\n\tu32 fb_filt_out_frm_cnt;\n\tu32 alloc_rx_skb_failed;\n\tu32 tx_dma_failed;\n\tu32 mc_filters_full_cnt;\n\tu32 uc_filters_full_cnt;\n\tu32 filters_combine_cnt;\n\tu32 promisc_filters_cnt;\n\tu32 tx_realloc_offload_failed;\n\tu32 tx_timeout_cnt;\n};\n\nstruct bcmasp_priv;\n\nstruct bcmasp_tx_cb;\n\nstruct bcmasp_intf {\n\tstruct list_head list;\n\tstruct net_device *ndev;\n\tstruct bcmasp_priv *parent;\n\tint channel;\n\tint port;\n\tint index;\n\tstruct napi_struct tx_napi;\n\tvoid *tx_spb_dma;\n\tint tx_spb_index;\n\tint tx_spb_clean_index;\n\tstruct bcmasp_desc *tx_spb_cpu;\n\tdma_addr_t tx_spb_dma_addr;\n\tdma_addr_t tx_spb_dma_valid;\n\tdma_addr_t tx_spb_dma_read;\n\tstruct bcmasp_tx_cb *tx_cbs;\n\tvoid *rx_edpkt_cfg;\n\tvoid *rx_edpkt_dma;\n\tint rx_edpkt_index;\n\tint rx_buf_order;\n\tstruct bcmasp_desc *rx_edpkt_cpu;\n\tdma_addr_t rx_edpkt_dma_addr;\n\tdma_addr_t rx_edpkt_dma_read;\n\tdma_addr_t rx_edpkt_dma_valid;\n\tvoid *rx_ring_cpu;\n\tdma_addr_t rx_ring_dma;\n\tdma_addr_t rx_ring_dma_valid;\n\tstruct napi_struct rx_napi;\n\tstruct bcmasp_res res;\n\tunsigned int crc_fwd;\n\tstruct device_node *phy_dn;\n\tstruct device_node *ndev_dn;\n\tphy_interface_t phy_interface;\n\tbool internal_phy;\n\tint old_pause;\n\tint old_link;\n\tint old_duplex;\n\tu32 msg_enable;\n\tstruct bcmasp_intf_stats64 stats64;\n\tstruct bcmasp_mib_counters mib;\n\tu32 wolopts;\n\tu8 sopass[6];\n};\n\nstruct bcmasp_mda_filter {\n\tint port;\n\tbool en;\n\tu8 addr[6];\n\tu8 mask[6];\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\t__u64 ring_cookie;\n\t__u32 location;\n};\n\nstruct bcmasp_net_filter {\n\tstruct ethtool_rx_flow_spec fs;\n\tbool claimed;\n\tbool wake_filter;\n\tint port;\n\tint ch;\n\tunsigned int hw_index;\n};\n\nstruct bcmasp_pkt_offload {\n\t__be32 nop;\n\t__be32 header;\n\t__be32 header2;\n\t__be32 epkt;\n\t__be32 end;\n};\n\nstruct bcmasp_plat_data {\n\tvoid (*core_clock_select)(struct bcmasp_priv *, bool);\n\tvoid (*eee_fixup)(struct bcmasp_intf *, bool);\n\tunsigned int num_mda_filters;\n\tunsigned int num_net_filters;\n\tunsigned int tx_chan_offset;\n\tunsigned int rx_ctrl_offset;\n};\n\nstruct bcmasp_priv {\n\tstruct platform_device *pdev;\n\tstruct clk *clk;\n\tint irq;\n\tu32 irq_mask;\n\tstruct mutex wol_lock;\n\tint wol_irq;\n\tlong unsigned int wol_irq_enabled_mask;\n\tvoid (*core_clock_select)(struct bcmasp_priv *, bool);\n\tvoid (*eee_fixup)(struct bcmasp_intf *, bool);\n\tunsigned int num_mda_filters;\n\tunsigned int num_net_filters;\n\tunsigned int tx_chan_offset;\n\tunsigned int rx_ctrl_offset;\n\tvoid *base;\n\tstruct list_head intfs;\n\tstruct bcmasp_mda_filter *mda_filters;\n\tspinlock_t mda_lock;\n\tspinlock_t clk_lock;\n\tstruct bcmasp_net_filter *net_filters;\n\tstruct mutex net_lock;\n};\n\nstruct bcmasp_stats {\n\tchar stat_string[32];\n\tenum bcmasp_stat_type type;\n\tu32 reg_offset;\n};\n\nstruct bcmasp_tx_cb {\n\tstruct sk_buff *skb;\n\tunsigned int bytes_sent;\n\tbool last;\n\tdma_addr_t dma_addr;\n\t__u32 dma_len;\n};\n\nstruct regulator_config;\n\nstruct regulator_ops;\n\nstruct linear_range;\n\nstruct regulator_desc {\n\tconst char *name;\n\tconst char *supply_name;\n\tconst char *of_match;\n\tbool of_match_full_name;\n\tconst char *regulators_node;\n\tint (*of_parse_cb)(struct device_node *, const struct regulator_desc *, struct regulator_config *);\n\tint (*init_cb)(struct regulator_dev *, struct regulator_config *);\n\tint id;\n\tunsigned int continuous_voltage_range: 1;\n\tunsigned int n_voltages;\n\tunsigned int n_current_limits;\n\tconst struct regulator_ops *ops;\n\tint irq;\n\tenum regulator_type type;\n\tstruct module *owner;\n\tunsigned int min_uV;\n\tunsigned int uV_step;\n\tunsigned int linear_min_sel;\n\tint fixed_uV;\n\tunsigned int ramp_delay;\n\tint min_dropout_uV;\n\tconst struct linear_range *linear_ranges;\n\tconst unsigned int *linear_range_selectors_bitfield;\n\tint n_linear_ranges;\n\tconst unsigned int *volt_table;\n\tconst unsigned int *curr_table;\n\tunsigned int vsel_range_reg;\n\tunsigned int vsel_range_mask;\n\tbool range_applied_by_vsel;\n\tunsigned int vsel_reg;\n\tunsigned int vsel_mask;\n\tunsigned int vsel_step;\n\tunsigned int csel_reg;\n\tunsigned int csel_mask;\n\tunsigned int apply_reg;\n\tunsigned int apply_bit;\n\tunsigned int enable_reg;\n\tunsigned int enable_mask;\n\tunsigned int enable_val;\n\tunsigned int disable_val;\n\tbool enable_is_inverted;\n\tunsigned int bypass_reg;\n\tunsigned int bypass_mask;\n\tunsigned int bypass_val_on;\n\tunsigned int bypass_val_off;\n\tunsigned int active_discharge_on;\n\tunsigned int active_discharge_off;\n\tunsigned int active_discharge_mask;\n\tunsigned int active_discharge_reg;\n\tunsigned int soft_start_reg;\n\tunsigned int soft_start_mask;\n\tunsigned int soft_start_val_on;\n\tunsigned int pull_down_reg;\n\tunsigned int pull_down_mask;\n\tunsigned int pull_down_val_on;\n\tunsigned int ramp_reg;\n\tunsigned int ramp_mask;\n\tconst unsigned int *ramp_delay_table;\n\tunsigned int n_ramp_values;\n\tunsigned int enable_time;\n\tunsigned int off_on_delay;\n\tunsigned int poll_enabled_time;\n\tunsigned int (*of_map_mode)(unsigned int);\n};\n\nstruct rohm_dvs_config {\n\tuint64_t level_map;\n\tunsigned int run_reg;\n\tunsigned int run_mask;\n\tunsigned int run_on_mask;\n\tunsigned int idle_reg;\n\tunsigned int idle_mask;\n\tunsigned int idle_on_mask;\n\tunsigned int suspend_reg;\n\tunsigned int suspend_mask;\n\tunsigned int suspend_on_mask;\n\tunsigned int lpsr_reg;\n\tunsigned int lpsr_mask;\n\tunsigned int lpsr_on_mask;\n\tunsigned int snvs_reg;\n\tunsigned int snvs_mask;\n\tunsigned int snvs_on_mask;\n};\n\nstruct reg_init {\n\tunsigned int reg;\n\tunsigned int mask;\n\tunsigned int val;\n};\n\nstruct bd718xx_regulator_data {\n\tstruct regulator_desc desc;\n\tconst struct rohm_dvs_config dvs;\n\tconst struct reg_init init;\n\tconst struct reg_init *additional_inits;\n\tint additional_init_amnt;\n};\n\nstruct bd9571mwv_reg {\n\tstruct regmap *regmap;\n\tu8 bkup_mode_cnt_keepon;\n\tu8 bkup_mode_cnt_saved;\n\tbool bkup_mode_enabled;\n\tbool rstbmode_level;\n\tbool rstbmode_pulse;\n};\n\nstruct bd_holder_disk {\n\tstruct list_head list;\n\tstruct kobject *holder_dir;\n\tint refcnt;\n};\n\nstruct bd_table;\n\nstruct bd_list {\n\tstruct bd_table **bd_table_array;\n\tint num_tabs;\n\tint max_bdi;\n\tint eqp_bdi;\n\tint hwd_bdi;\n\tint num_bds_table;\n};\n\nstruct bdc_bd;\n\nstruct bd_table {\n\tstruct bdc_bd *start_bd;\n\tdma_addr_t dma;\n};\n\nstruct bdc_req;\n\nstruct bd_transfer {\n\tstruct bdc_req *req;\n\tint start_bdi;\n\tint next_hwd_bdi;\n\tint num_bds;\n};\n\nstruct usb_udc;\n\nstruct usb_gadget_ops;\n\nstruct usb_ep;\n\nstruct usb_otg_caps;\n\nstruct usb_gadget {\n\tstruct work_struct work;\n\tstruct usb_udc *udc;\n\tconst struct usb_gadget_ops *ops;\n\tstruct usb_ep *ep0;\n\tstruct list_head ep_list;\n\tenum usb_device_speed speed;\n\tenum usb_device_speed max_speed;\n\tenum usb_ssp_rate ssp_rate;\n\tenum usb_ssp_rate max_ssp_rate;\n\tenum usb_device_state state;\n\tspinlock_t state_lock;\n\tbool teardown;\n\tconst char *name;\n\tstruct device dev;\n\tunsigned int isoch_delay;\n\tunsigned int out_epnum;\n\tunsigned int in_epnum;\n\tunsigned int mA;\n\tstruct usb_otg_caps *otg_caps;\n\tunsigned int sg_supported: 1;\n\tunsigned int is_otg: 1;\n\tunsigned int is_a_peripheral: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int a_hnp_support: 1;\n\tunsigned int a_alt_hnp_support: 1;\n\tunsigned int hnp_polling_support: 1;\n\tunsigned int host_request_flag: 1;\n\tunsigned int quirk_ep_out_aligned_size: 1;\n\tunsigned int quirk_altset_not_supp: 1;\n\tunsigned int quirk_stall_not_supp: 1;\n\tunsigned int quirk_zlp_not_supp: 1;\n\tunsigned int quirk_avoids_skb_reserve: 1;\n\tunsigned int is_selfpowered: 1;\n\tunsigned int deactivated: 1;\n\tunsigned int connected: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int wakeup_capable: 1;\n\tunsigned int wakeup_armed: 1;\n\tint irq;\n\tint id_number;\n};\n\nstruct bdc_scratchpad {\n\tdma_addr_t sp_dma;\n\tvoid *buff;\n\tu32 size;\n};\n\nstruct bdc_sr;\n\nstruct srr {\n\tstruct bdc_sr *sr_bds;\n\tu16 eqp_index;\n\tu16 dqp_index;\n\tdma_addr_t dma_addr;\n};\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_request {\n\tstruct usb_ep *ep;\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tstruct scatterlist *sg;\n\tunsigned int num_sgs;\n\tunsigned int num_mapped_sgs;\n\tunsigned int stream_id: 16;\n\tunsigned int is_last: 1;\n\tunsigned int no_interrupt: 1;\n\tunsigned int zero: 1;\n\tunsigned int short_not_ok: 1;\n\tunsigned int dma_mapped: 1;\n\tunsigned int sg_was_mapped: 1;\n\tvoid (*complete)(struct usb_ep *, struct usb_request *);\n\tvoid *context;\n\tstruct list_head list;\n\tunsigned int frame_number;\n\tint status;\n\tunsigned int actual;\n};\n\nstruct bdc_ep;\n\nstruct bdc_req {\n\tstruct usb_request usb_req;\n\tstruct list_head queue;\n\tstruct bdc_ep *ep;\n\tstruct bd_transfer bd_xfr;\n\tint epnum;\n};\n\nstruct usb_gadget_driver;\n\nstruct bdc {\n\tstruct usb_gadget gadget;\n\tstruct usb_gadget_driver *gadget_driver;\n\tstruct device *dev;\n\tspinlock_t lock;\n\tstruct phy **phys;\n\tint num_phys;\n\tunsigned int num_eps;\n\tstruct bdc_ep **bdc_ep_array;\n\tvoid *regs;\n\tstruct bdc_scratchpad scratchpad;\n\tu32 sp_buff_size;\n\tstruct srr srr;\n\tstruct usb_ctrlrequest setup_pkt;\n\tstruct bdc_req ep0_req;\n\tstruct bdc_req status_req;\n\tenum bdc_ep0_state ep0_state;\n\tbool delayed_status;\n\tbool zlp_needed;\n\tbool reinit;\n\tbool pullup;\n\tu32 devstatus;\n\tint irq;\n\tvoid *mem;\n\tu32 dev_addr;\n\tstruct dma_pool *bd_table_pool;\n\tu8 test_mode;\n\tvoid (*sr_handler[2])(struct bdc *, struct bdc_sr *);\n\tvoid (*sr_xsf_ep0[3])(struct bdc *, struct bdc_sr *);\n\tunsigned char ep0_response_buff[6];\n\tstruct delayed_work func_wake_notify;\n\tstruct clk *clk;\n};\n\nstruct bdc_bd {\n\t__le32 offset[4];\n};\n\nstruct usb_ep_caps {\n\tunsigned int type_control: 1;\n\tunsigned int type_iso: 1;\n\tunsigned int type_bulk: 1;\n\tunsigned int type_int: 1;\n\tunsigned int dir_in: 1;\n\tunsigned int dir_out: 1;\n};\n\nstruct usb_ep_ops;\n\nstruct usb_endpoint_descriptor;\n\nstruct usb_ss_ep_comp_descriptor;\n\nstruct usb_ep {\n\tvoid *driver_data;\n\tconst char *name;\n\tconst struct usb_ep_ops *ops;\n\tconst struct usb_endpoint_descriptor *desc;\n\tconst struct usb_ss_ep_comp_descriptor *comp_desc;\n\tstruct list_head ep_list;\n\tstruct usb_ep_caps caps;\n\tbool claimed;\n\tbool enabled;\n\tunsigned int mult: 2;\n\tunsigned int maxburst: 5;\n\tu8 address;\n\tu16 maxpacket;\n\tu16 maxpacket_limit;\n\tu16 max_streams;\n};\n\nstruct bdc_ep {\n\tstruct usb_ep usb_ep;\n\tstruct list_head queue;\n\tstruct bdc *bdc;\n\tu8 ep_type;\n\tu8 dir;\n\tu8 ep_num;\n\tconst struct usb_ss_ep_comp_descriptor *comp_desc;\n\tconst struct usb_endpoint_descriptor *desc;\n\tunsigned int flags;\n\tchar name[20];\n\tstruct bd_list bd_list;\n\tbool ignore_next_sr;\n};\n\nstruct bdc_sr {\n\t__le32 offset[4];\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tvoid *bd_security;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tvoid *i_security;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct bdi_writeback *i_wb;\n\tint i_wb_frn_winner;\n\tu16 i_wb_frn_avg_time;\n\tu16 i_wb_frn_history;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct berlin2_avpll_channel {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu8 flags;\n\tu8 index;\n};\n\nstruct berlin2_avpll_vco {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu8 flags;\n};\n\nstruct berlin2_div_map {\n\tu16 pll_select_offs;\n\tu16 pll_switch_offs;\n\tu16 div_select_offs;\n\tu16 div_switch_offs;\n\tu16 div3_switch_offs;\n\tu16 gate_offs;\n\tu8 pll_select_shift;\n\tu8 pll_switch_shift;\n\tu8 div_select_shift;\n\tu8 div_switch_shift;\n\tu8 div3_switch_shift;\n\tu8 gate_shift;\n};\n\nstruct berlin2_div {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct berlin2_div_map map;\n\tspinlock_t *lock;\n};\n\nstruct berlin2_pll_map {\n\tconst u8 vcodiv[16];\n\tu8 mult;\n\tu8 fbdiv_shift;\n\tu8 rfdiv_shift;\n\tu8 divsel_shift;\n};\n\nstruct berlin2_pll {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct berlin2_pll_map map;\n};\n\nstruct bfq_sched_data;\n\nstruct bfq_queue;\n\nstruct bfq_entity {\n\tstruct rb_node rb_node;\n\tbool on_st_or_in_serv;\n\tu64 start;\n\tu64 finish;\n\tstruct rb_root *tree;\n\tu64 min_start;\n\tint service;\n\tint budget;\n\tint allocated;\n\tint dev_weight;\n\tint weight;\n\tint new_weight;\n\tint orig_weight;\n\tstruct bfq_entity *parent;\n\tstruct bfq_sched_data *my_sched_data;\n\tstruct bfq_sched_data *sched_data;\n\tint prio_changed;\n\tbool in_groups_with_pending_reqs;\n\tstruct bfq_queue *last_bfqq_created;\n};\n\nstruct bfq_ttime {\n\tu64 last_end_request;\n\tu64 ttime_total;\n\tlong unsigned int ttime_samples;\n\tu64 ttime_mean;\n};\n\nstruct bfq_data;\n\nstruct request;\n\nstruct bfq_weight_counter;\n\nstruct bfq_io_cq;\n\nstruct bfq_queue {\n\tint ref;\n\tint stable_ref;\n\tstruct bfq_data *bfqd;\n\tshort unsigned int ioprio;\n\tshort unsigned int ioprio_class;\n\tshort unsigned int new_ioprio;\n\tshort unsigned int new_ioprio_class;\n\tu64 last_serv_time_ns;\n\tunsigned int inject_limit;\n\tlong unsigned int decrease_time_jif;\n\tstruct bfq_queue *new_bfqq;\n\tstruct rb_node pos_node;\n\tstruct rb_root *pos_root;\n\tstruct rb_root sort_list;\n\tstruct request *next_rq;\n\tint queued[2];\n\tint meta_pending;\n\tstruct list_head fifo;\n\tstruct bfq_entity entity;\n\tstruct bfq_weight_counter *weight_counter;\n\tint max_budget;\n\tlong unsigned int budget_timeout;\n\tint dispatched;\n\tlong unsigned int flags;\n\tstruct list_head bfqq_list;\n\tstruct bfq_ttime ttime;\n\tu64 io_start_time;\n\tu64 tot_idle_time;\n\tu32 seek_history;\n\tstruct hlist_node burst_list_node;\n\tsector_t last_request_pos;\n\tunsigned int requests_within_timer;\n\tpid_t pid;\n\tstruct bfq_io_cq *bic;\n\tlong unsigned int wr_cur_max_time;\n\tlong unsigned int soft_rt_next_start;\n\tlong unsigned int last_wr_start_finish;\n\tunsigned int wr_coeff;\n\tlong unsigned int last_idle_bklogged;\n\tlong unsigned int service_from_backlogged;\n\tlong unsigned int service_from_wr;\n\tlong unsigned int wr_start_at_switch_to_srt;\n\tlong unsigned int split_time;\n\tlong unsigned int first_IO_time;\n\tlong unsigned int creation_time;\n\tstruct bfq_queue *waker_bfqq;\n\tstruct bfq_queue *tentative_waker_bfqq;\n\tunsigned int num_waker_detections;\n\tu64 waker_detection_started;\n\tstruct hlist_node woken_list_node;\n\tstruct hlist_head woken_list;\n\tunsigned int actuator_idx;\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct bfq_group;\n\nstruct bfq_data {\n\tstruct request_queue *queue;\n\tstruct list_head dispatch;\n\tstruct bfq_group *root_group;\n\tstruct rb_root_cached queue_weights_tree;\n\tunsigned int num_groups_with_pending_reqs;\n\tunsigned int busy_queues[3];\n\tint wr_busy_queues;\n\tint queued;\n\tint tot_rq_in_driver;\n\tint rq_in_driver[8];\n\tbool nonrot_with_queueing;\n\tint max_rq_in_driver;\n\tint hw_tag_samples;\n\tint hw_tag;\n\tint budgets_assigned;\n\tstruct hrtimer idle_slice_timer;\n\tstruct bfq_queue *in_service_queue;\n\tsector_t last_position;\n\tsector_t in_serv_last_pos;\n\tu64 last_completion;\n\tstruct bfq_queue *last_completed_rq_bfqq;\n\tstruct bfq_queue *last_bfqq_created;\n\tu64 last_empty_occupied_ns;\n\tbool wait_dispatch;\n\tstruct request *waited_rq;\n\tbool rqs_injected;\n\tu64 first_dispatch;\n\tu64 last_dispatch;\n\tktime_t last_budget_start;\n\tktime_t last_idling_start;\n\tlong unsigned int last_idling_start_jiffies;\n\tint peak_rate_samples;\n\tu32 sequential_samples;\n\tu64 tot_sectors_dispatched;\n\tu32 last_rq_max_size;\n\tu64 delta_from_first;\n\tu32 peak_rate;\n\tint bfq_max_budget;\n\tstruct list_head active_list[8];\n\tstruct list_head idle_list;\n\tu64 bfq_fifo_expire[2];\n\tunsigned int bfq_back_penalty;\n\tunsigned int bfq_back_max;\n\tu32 bfq_slice_idle;\n\tint bfq_user_max_budget;\n\tunsigned int bfq_timeout;\n\tbool strict_guarantees;\n\tlong unsigned int last_ins_in_burst;\n\tlong unsigned int bfq_burst_interval;\n\tint burst_size;\n\tstruct bfq_entity *burst_parent_entity;\n\tlong unsigned int bfq_large_burst_thresh;\n\tbool large_burst;\n\tstruct hlist_head burst_list;\n\tbool low_latency;\n\tunsigned int bfq_wr_coeff;\n\tunsigned int bfq_wr_rt_max_time;\n\tunsigned int bfq_wr_min_idle_time;\n\tlong unsigned int bfq_wr_min_inter_arr_async;\n\tunsigned int bfq_wr_max_softrt_rate;\n\tu64 rate_dur_prod;\n\tstruct bfq_queue oom_bfqq;\n\tspinlock_t lock;\n\tstruct bfq_io_cq *bio_bic;\n\tstruct bfq_queue *bio_bfqq;\n\tunsigned int async_depths[4];\n\tunsigned int num_actuators;\n\tsector_t sector[8];\n\tsector_t nr_sectors[8];\n\tstruct blk_independent_access_range ia_ranges[8];\n\tunsigned int actuator_load_threshold;\n};\n\nstruct blkcg_gq;\n\nstruct blkg_policy_data {\n\tstruct blkcg_gq *blkg;\n\tint plid;\n\tbool online;\n};\n\nstruct bfq_service_tree {\n\tstruct rb_root active;\n\tstruct rb_root idle;\n\tstruct bfq_entity *first_idle;\n\tstruct bfq_entity *last_idle;\n\tu64 vtime;\n\tlong unsigned int wsum;\n};\n\nstruct bfq_sched_data {\n\tstruct bfq_entity *in_service_entity;\n\tstruct bfq_entity *next_in_service;\n\tstruct bfq_service_tree service_tree[3];\n\tlong unsigned int bfq_class_idle_last_service;\n};\n\nstruct blkg_rwstat {\n\tstruct percpu_counter cpu_cnt[5];\n\tatomic64_t aux_cnt[5];\n};\n\nstruct bfqg_stats {\n\tstruct blkg_rwstat bytes;\n\tstruct blkg_rwstat ios;\n};\n\nstruct bfq_group {\n\tstruct blkg_policy_data pd;\n\trefcount_t ref;\n\tstruct bfq_entity entity;\n\tstruct bfq_sched_data sched_data;\n\tstruct bfq_data *bfqd;\n\tstruct bfq_queue *async_bfqq[128];\n\tstruct bfq_queue *async_idle_bfqq[8];\n\tstruct bfq_entity *my_entity;\n\tint active_entities;\n\tint num_queues_with_pending_reqs;\n\tstruct rb_root rq_pos_tree;\n\tstruct bfqg_stats stats;\n};\n\nstruct blkcg;\n\nstruct blkcg_policy_data {\n\tstruct blkcg *blkcg;\n\tint plid;\n};\n\nstruct bfq_group_data {\n\tstruct blkcg_policy_data pd;\n\tunsigned int weight;\n};\n\nstruct io_context;\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct bfq_iocq_bfqq_data {\n\tbool saved_has_short_ttime;\n\tbool saved_IO_bound;\n\tbool saved_in_large_burst;\n\tbool was_in_burst_list;\n\tunsigned int saved_weight;\n\tu64 saved_io_start_time;\n\tu64 saved_tot_idle_time;\n\tlong unsigned int saved_wr_coeff;\n\tlong unsigned int saved_last_wr_start_finish;\n\tlong unsigned int saved_service_from_wr;\n\tlong unsigned int saved_wr_start_at_switch_to_srt;\n\tstruct bfq_ttime saved_ttime;\n\tunsigned int saved_wr_cur_max_time;\n\tunsigned int saved_inject_limit;\n\tlong unsigned int saved_decrease_time_jif;\n\tu64 saved_last_serv_time_ns;\n\tstruct bfq_queue *stable_merge_bfqq;\n\tbool stably_merged;\n};\n\nstruct bfq_io_cq {\n\tstruct io_cq icq;\n\tstruct bfq_queue *bfqq[16];\n\tint ioprio;\n\tuint64_t blkcg_serial_nr;\n\tstruct bfq_iocq_bfqq_data bfqq_data[8];\n\tunsigned int requests;\n};\n\nstruct bfq_weight_counter {\n\tunsigned int weight;\n\tunsigned int num_active;\n\tstruct rb_node weights_node;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bgmac_slot_info {\n\tunion {\n\t\tstruct sk_buff *skb;\n\t\tvoid *buf;\n\t};\n\tdma_addr_t dma_addr;\n};\n\nstruct bgmac_dma_desc;\n\nstruct bgmac_dma_ring {\n\tu32 start;\n\tu32 end;\n\tstruct bgmac_dma_desc *cpu_base;\n\tdma_addr_t dma_base;\n\tu32 index_base;\n\tu16 mmio_base;\n\tbool unaligned;\n\tstruct bgmac_slot_info slots[512];\n};\n\nstruct bgmac {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *base;\n\t\t\tvoid *idm_base;\n\t\t\tvoid *nicpm_base;\n\t\t} plat;\n\t\tstruct {\n\t\t\tstruct bcma_device *core;\n\t\t\tstruct bcma_device *cmn;\n\t\t} bcma;\n\t};\n\tstruct device *dev;\n\tstruct device *dma_dev;\n\tu32 feature_flags;\n\tstruct net_device *net_dev;\n\tstruct napi_struct napi;\n\tstruct mii_bus *mii_bus;\n\tstruct bgmac_dma_ring tx_ring[4];\n\tstruct bgmac_dma_ring rx_ring[1];\n\tbool stats_grabbed;\n\tu32 mib_tx_regs[43];\n\tu32 mib_rx_regs[31];\n\tint irq;\n\tu32 int_mask;\n\tbool in_init;\n\tint mac_speed;\n\tint mac_duplex;\n\tu8 phyaddr;\n\tbool has_robosw;\n\tbool loopback;\n\tu32 (*read)(struct bgmac *, u16);\n\tvoid (*write)(struct bgmac *, u16, u32);\n\tu32 (*idm_read)(struct bgmac *, u16);\n\tvoid (*idm_write)(struct bgmac *, u16, u32);\n\tbool (*clk_enabled)(struct bgmac *);\n\tvoid (*clk_enable)(struct bgmac *, u32);\n\tvoid (*cco_ctl_maskset)(struct bgmac *, u32, u32, u32);\n\tu32 (*get_bus_clock)(struct bgmac *);\n\tvoid (*cmn_maskset32)(struct bgmac *, u16, u32, u32);\n\tint (*phy_connect)(struct bgmac *);\n};\n\nstruct bgmac_dma_desc {\n\t__le32 ctl0;\n\t__le32 ctl1;\n\t__le32 addr_low;\n\t__le32 addr_high;\n};\n\nstruct bgmac_rx_header {\n\t__le16 len;\n\t__le16 flags;\n\t__le16 pad[12];\n};\n\nstruct bgmac_stat {\n\tu8 size;\n\tu32 offset;\n\tconst char *name;\n};\n\nstruct bgx;\n\nstruct dmac_map;\n\nstruct lmac {\n\tstruct bgx *bgx;\n\tu8 dmacs_cfg;\n\tu8 dmacs_count;\n\tstruct dmac_map *dmacs;\n\tu8 mac[6];\n\tu8 lmac_type;\n\tu8 lane_to_sds;\n\tbool use_training;\n\tbool autoneg;\n\tbool link_up;\n\tint lmacid;\n\tint lmacid_bd;\n\tstruct net_device *netdev;\n\tstruct phy_device *phydev;\n\tunsigned int last_duplex;\n\tunsigned int last_link;\n\tunsigned int last_speed;\n\tbool is_sgmii;\n\tstruct delayed_work dwork;\n\tstruct workqueue_struct *check_link;\n};\n\nstruct bgx {\n\tu8 bgx_id;\n\tstruct lmac lmac[4];\n\tu8 lmac_count;\n\tu8 max_lmac;\n\tu8 acpi_lmac_idx;\n\tvoid *reg_base;\n\tstruct pci_dev *pdev;\n\tbool is_dlm;\n\tbool is_rgx;\n};\n\nstruct bgx_link_status {\n\tu8 msg;\n\tu8 mac_type;\n\tu8 link_up;\n\tu8 duplex;\n\tu32 speed;\n};\n\nstruct bgx_stats_msg {\n\tu8 msg;\n\tu8 vf_id;\n\tu8 rx;\n\tu8 idx;\n\tu64 stats;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n} __attribute__((packed));\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct bio_crypt_ctx;\n\nstruct bio_integrity_payload;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tstruct blkcg_gq *bi_blkg;\n\tu64 issue_time_ns;\n\tstruct bio_crypt_ctx *bi_crypt_context;\n\tstruct bio_integrity_payload *bi_integrity;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tu64 bc_dun[4];\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct bio_integrity_alloc {\n\tstruct bio_integrity_payload bip;\n\tstruct bio_vec bvecs[0];\n};\n\nstruct bio_integrity_data {\n\tstruct bio *bio;\n\tstruct bvec_iter saved_bio_iter;\n\tstruct work_struct work;\n\tstruct bio_integrity_payload bip;\n\tstruct bio_vec bvec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec;\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct fsverity_info;\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct fsverity_info *vi;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bl_dev_msg {\n\tint32_t status;\n\tuint32_t major;\n\tuint32_t minor;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_profile;\n\nstruct blk_crypto_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_crypto_profile *, struct blk_crypto_attr *, char *);\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct blk_crypto_generate_key_arg {\n\t__u64 lt_key_ptr;\n\t__u64 lt_key_size;\n\t__u64 reserved[4];\n};\n\nstruct blk_crypto_import_key_arg {\n\t__u64 raw_key_ptr;\n\t__u64 raw_key_size;\n\t__u64 lt_key_ptr;\n\t__u64 lt_key_size;\n\t__u64 reserved[4];\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct blk_crypto_keyslot {\n\tatomic_t slot_refs;\n\tstruct list_head idle_slot_node;\n\tstruct hlist_node hash_node;\n\tconst struct blk_crypto_key *key;\n\tstruct blk_crypto_profile *profile;\n};\n\nstruct blk_crypto_kobj {\n\tstruct kobject kobj;\n\tstruct blk_crypto_profile *profile;\n};\n\nstruct blk_crypto_ll_ops {\n\tint (*keyslot_program)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*keyslot_evict)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*derive_sw_secret)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*import_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*generate_key)(struct blk_crypto_profile *, u8 *);\n\tint (*prepare_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n};\n\nstruct blk_crypto_mode {\n\tconst char *name;\n\tconst char *cipher_str;\n\tunsigned int keysize;\n\tunsigned int security_strength;\n\tunsigned int ivsize;\n};\n\nstruct blk_crypto_prepare_key_arg {\n\t__u64 lt_key_ptr;\n\t__u64 lt_key_size;\n\t__u64 eph_key_ptr;\n\t__u64 eph_key_size;\n\t__u64 reserved[4];\n};\n\nstruct blk_crypto_profile {\n\tstruct blk_crypto_ll_ops ll_ops;\n\tunsigned int max_dun_bytes_supported;\n\tunsigned int key_types_supported;\n\tunsigned int modes_supported[5];\n\tstruct device *dev;\n\tunsigned int num_slots;\n\tstruct rw_semaphore lock;\n\tstruct lock_class_key lockdep_key;\n\twait_queue_head_t idle_slots_wait_queue;\n\tstruct list_head idle_slots;\n\tspinlock_t idle_slots_lock;\n\tstruct hlist_head *slot_hashtable;\n\tunsigned int log_slot_ht_size;\n\tstruct blk_crypto_keyslot *slots;\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_integrity_iter {\n\tvoid *prot_buf;\n\tvoid *data_buf;\n\tsector_t seed;\n\tunsigned int data_size;\n\tshort unsigned int interval;\n\tconst char *disk_name;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 64;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 64;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blkif_request_segment {\n\tgrant_ref_t gref;\n\tuint8_t first_sect;\n\tuint8_t last_sect;\n};\n\nstruct blkif_request_rw {\n\tuint8_t nr_segments;\n\tblkif_vdev_t handle;\n\tuint32_t _pad1;\n\tuint64_t id;\n\tblkif_sector_t sector_number;\n\tstruct blkif_request_segment seg[11];\n} __attribute__((packed));\n\nstruct blkif_request_discard {\n\tuint8_t flag;\n\tblkif_vdev_t _pad1;\n\tuint32_t _pad2;\n\tuint64_t id;\n\tblkif_sector_t sector_number;\n\tuint64_t nr_sectors;\n\tuint8_t _pad3;\n} __attribute__((packed));\n\nstruct blkif_request_other {\n\tuint8_t _pad1;\n\tblkif_vdev_t _pad2;\n\tuint32_t _pad3;\n\tuint64_t id;\n} __attribute__((packed));\n\nstruct blkif_request_indirect {\n\tuint8_t indirect_op;\n\tuint16_t nr_segments;\n\tuint32_t _pad1;\n\tuint64_t id;\n\tblkif_sector_t sector_number;\n\tblkif_vdev_t handle;\n\tuint16_t _pad2;\n\tgrant_ref_t indirect_grefs[8];\n\tuint32_t _pad3;\n} __attribute__((packed));\n\nstruct blkif_request {\n\tuint8_t operation;\n\tunion {\n\t\tstruct blkif_request_rw rw;\n\t\tstruct blkif_request_discard discard;\n\t\tstruct blkif_request_other other;\n\t\tstruct blkif_request_indirect indirect;\n\t} u;\n};\n\nstruct grant;\n\nstruct blk_shadow {\n\tstruct blkif_request req;\n\tstruct request *request;\n\tstruct grant **grants_used;\n\tstruct grant **indirect_grants;\n\tstruct scatterlist *sg;\n\tunsigned int num_sg;\n\tenum blk_req_status status;\n\tlong unsigned int associated_id;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct cgroup_subsys;\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n};\n\nstruct blkcg {\n\tstruct cgroup_subsys_state css;\n\tspinlock_t lock;\n\trefcount_t online_pin;\n\tatomic_t congestion_count;\n\tstruct xarray blkg_tree;\n\tstruct blkcg_gq *blkg_hint;\n\tstruct hlist_head blkg_list;\n\tstruct blkcg_policy_data *cpd[6];\n\tstruct list_head all_blkcgs_node;\n\tstruct llist_head *lhead;\n\tstruct list_head cgwb_list;\n};\n\nstruct blkg_iostat {\n\tu64 bytes[3];\n\tu64 ios[3];\n};\n\nstruct blkg_iostat_set {\n\tstruct u64_stats_sync sync;\n\tstruct blkcg_gq *blkg;\n\tstruct llist_node lnode;\n\tint lqueued;\n\tstruct blkg_iostat cur;\n\tstruct blkg_iostat last;\n};\n\nstruct blkcg_gq {\n\tstruct request_queue *q;\n\tstruct list_head q_node;\n\tstruct hlist_node blkcg_node;\n\tstruct blkcg *blkcg;\n\tstruct blkcg_gq *parent;\n\tstruct percpu_ref refcnt;\n\tbool online;\n\tstruct blkg_iostat_set *iostat_cpu;\n\tstruct blkg_iostat_set iostat;\n\tstruct blkg_policy_data *pd[6];\n\tspinlock_t async_bio_lock;\n\tstruct bio_list async_bios;\n\tunion {\n\t\tstruct work_struct async_bio_work;\n\t\tstruct work_struct free_work;\n\t};\n\tatomic_t use_delay;\n\tatomic64_t delay_nsec;\n\tatomic64_t delay_start;\n\tu64 last_delay;\n\tint last_use;\n\tstruct callback_head callback_head;\n};\n\ntypedef struct blkcg_policy_data *blkcg_pol_alloc_cpd_fn(gfp_t);\n\ntypedef void blkcg_pol_free_cpd_fn(struct blkcg_policy_data *);\n\ntypedef struct blkg_policy_data *blkcg_pol_alloc_pd_fn(struct gendisk *, struct blkcg *, gfp_t);\n\ntypedef void blkcg_pol_init_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_online_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_offline_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_free_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_reset_pd_stats_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_stat_pd_fn(struct blkg_policy_data *, struct seq_file *);\n\nstruct cftype;\n\nstruct blkcg_policy {\n\tint plid;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tblkcg_pol_alloc_cpd_fn *cpd_alloc_fn;\n\tblkcg_pol_free_cpd_fn *cpd_free_fn;\n\tblkcg_pol_alloc_pd_fn *pd_alloc_fn;\n\tblkcg_pol_init_pd_fn *pd_init_fn;\n\tblkcg_pol_online_pd_fn *pd_online_fn;\n\tblkcg_pol_offline_pd_fn *pd_offline_fn;\n\tblkcg_pol_free_pd_fn *pd_free_fn;\n\tblkcg_pol_reset_pd_stats_fn *pd_reset_stats_fn;\n\tblkcg_pol_stat_pd_fn *pd_stat_fn;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bio bio;\n};\n\nstruct xenbus_device;\n\nstruct blkfront_ring_info;\n\nstruct blkfront_info {\n\tstruct mutex mutex;\n\tstruct xenbus_device *xbdev;\n\tstruct gendisk *gd;\n\tu16 sector_size;\n\tunsigned int physical_sector_size;\n\tlong unsigned int vdisk_info;\n\tint vdevice;\n\tblkif_vdev_t handle;\n\tenum blkif_state connected;\n\tunsigned int nr_ring_pages;\n\tstruct request_queue *rq;\n\tunsigned int feature_flush: 1;\n\tunsigned int feature_fua: 1;\n\tunsigned int feature_discard: 1;\n\tunsigned int feature_secdiscard: 1;\n\tunsigned int feature_persistent_parm: 1;\n\tunsigned int feature_persistent: 1;\n\tunsigned int bounce: 1;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int max_indirect_segments;\n\tint is_ready;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct blkfront_ring_info *rinfo;\n\tunsigned int nr_rings;\n\tunsigned int rinfo_size;\n\tstruct list_head requests;\n\tstruct bio_list bio_list;\n\tstruct list_head info_list;\n};\n\nstruct blkif_sring;\n\nstruct blkif_front_ring {\n\tRING_IDX req_prod_pvt;\n\tRING_IDX rsp_cons;\n\tunsigned int nr_ents;\n\tstruct blkif_sring *sring;\n};\n\nstruct gnttab_free_callback {\n\tstruct gnttab_free_callback *next;\n\tvoid (*fn)(void *);\n\tvoid *arg;\n\tu16 count;\n};\n\nstruct blkfront_ring_info {\n\tspinlock_t ring_lock;\n\tstruct blkif_front_ring ring;\n\tunsigned int ring_ref[16];\n\tunsigned int evtchn;\n\tunsigned int irq;\n\tstruct work_struct work;\n\tstruct gnttab_free_callback callback;\n\tstruct list_head indirect_pages;\n\tstruct list_head grants;\n\tunsigned int persistent_gnts_c;\n\tlong unsigned int shadow_free;\n\tstruct blkfront_info *dev_info;\n\tstruct blk_shadow shadow[0];\n};\n\nstruct blkg_conf_ctx {\n\tchar *input;\n\tchar *body;\n\tstruct block_device *bdev;\n\tstruct blkcg_gq *blkg;\n};\n\nstruct blkg_rwstat_sample {\n\tu64 cnt[5];\n};\n\nstruct blkif_req {\n\tblk_status_t error;\n};\n\nstruct blkif_response {\n\tuint64_t id;\n\tuint8_t operation;\n\tint16_t status;\n};\n\nunion blkif_sring_entry {\n\tstruct blkif_request req;\n\tstruct blkif_response rsp;\n};\n\nstruct blkif_sring {\n\tRING_IDX req_prod;\n\tRING_IDX req_event;\n\tRING_IDX rsp_prod;\n\tRING_IDX rsp_event;\n\tuint8_t __pad[48];\n\tunion blkif_sring_entry ring[0];\n};\n\nstruct blkpg_compat_ioctl_arg {\n\tcompat_int_t op;\n\tcompat_int_t flags;\n\tcompat_int_t datalen;\n\tcompat_uptr_t data;\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[128];\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct blzp1600_gpio {\n\tvoid *base;\n\tstruct gpio_generic_chip gen_gc;\n\tint irq;\n};\n\nstruct bm_addr {\n\tvoid *ce;\n\t__be32 *ce_be;\n\tvoid *ci;\n};\n\nstruct bm_buffer {\n\tunion {\n\t\tstruct {\n\t\t\t__be16 bpid;\n\t\t\t__be16 hi;\n\t\t\t__be32 lo;\n\t\t};\n\t\t__be64 data;\n\t};\n};\n\nstruct bm_mc_command;\n\nunion bm_mc_result;\n\nstruct bm_mc {\n\tstruct bm_mc_command *cr;\n\tunion bm_mc_result *rr;\n\tu8 rridx;\n\tu8 vbit;\n};\n\nstruct bm_mc_command {\n\tu8 _ncw_verb;\n\tu8 bpid;\n\tu8 __reserved[62];\n};\n\nunion bm_mc_result {\n\tstruct {\n\t\tu8 verb;\n\t\tu8 bpid;\n\t\tu8 __reserved[62];\n\t};\n\tstruct bm_buffer bufs[8];\n};\n\nstruct bm_rcr_entry;\n\nstruct bm_rcr {\n\tstruct bm_rcr_entry *ring;\n\tstruct bm_rcr_entry *cursor;\n\tu8 ci;\n\tu8 available;\n\tu8 ithresh;\n\tu8 vbit;\n};\n\nstruct bm_portal {\n\tstruct bm_addr addr;\n\tstruct bm_rcr rcr;\n\tstruct bm_mc mc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bm_portal_config {\n\tvoid *addr_virt_ce;\n\tvoid *addr_virt_ci;\n\tstruct list_head list;\n\tstruct device *dev;\n\tint cpu;\n\tint irq;\n};\n\nstruct mem_zone_bm_rtree;\n\nstruct rtree_node;\n\nstruct bm_position {\n\tstruct mem_zone_bm_rtree *zone;\n\tstruct rtree_node *node;\n\tlong unsigned int node_pfn;\n\tlong unsigned int cur_pfn;\n\tint node_bit;\n};\n\nstruct bm_rcr_entry {\n\tunion {\n\t\tstruct {\n\t\t\tu8 _ncw_verb;\n\t\t\tu8 bpid;\n\t\t\tu8 __reserved1[62];\n\t\t};\n\t\tstruct bm_buffer bufs[8];\n\t};\n};\n\nstruct bman_hwerr_txt {\n\tu32 mask;\n\tconst char *txt;\n};\n\nstruct bman_portal;\n\nstruct bman_pool {\n\tu32 bpid;\n\tstruct bman_portal *portal;\n\tstruct bman_pool *next;\n};\n\nstruct bman_portal {\n\tstruct bm_portal p;\n\tlong unsigned int irq_sources;\n\tconst struct bm_portal_config *config;\n\tchar irqname[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct spi_board_info {\n\tchar modalias[32];\n\tconst void *platform_data;\n\tconst struct software_node *swnode;\n\tvoid *controller_data;\n\tint irq;\n\tu32 max_speed_hz;\n\tu16 bus_num;\n\tu16 chip_select;\n\tu32 mode;\n};\n\nstruct boardinfo {\n\tstruct list_head list;\n\tstruct spi_board_info board_info;\n};\n\nstruct boot_triggers {\n\tconst char *event;\n\tchar *trigger;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct bp_slots_histogram {\n\tatomic_t *count;\n};\n\nstruct bp_cpuinfo {\n\tunsigned int cpu_pinned;\n\tstruct bp_slots_histogram tsk_pinned;\n};\n\ntypedef void (*bp_hardening_cb_t)(void);\n\nstruct bp_hardening_data {\n\tenum arm64_hyp_spectre_vector slot;\n\tbp_hardening_cb_t fn;\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct obj_cgroup;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tvoid *security;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tstruct obj_cgroup *objcg;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n};\n\nstruct range_tree {\n\tstruct rb_root_cached it_root;\n\tstruct rb_root_cached range_size_root;\n};\n\ntypedef struct qspinlock rqspinlock_t;\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct vm_struct;\n\nstruct bpf_arena {\n\tstruct bpf_map map;\n\tu64 user_vm_start;\n\tu64 user_vm_end;\n\tstruct vm_struct *kern_vm;\n\tstruct range_tree rt;\n\trqspinlock_t spinlock;\n\tstruct list_head vma_list;\n\tstruct mutex lock;\n\tstruct irq_work free_irq;\n\tstruct work_struct free_work;\n\tstruct llist_head free_spans;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 0;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_cgroup_dev_ctx {\n\t__u32 access_type;\n\t__u32 major;\n\t__u32 minor;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n};\n\nstruct bpf_cgroup_link {\n\tstruct bpf_link link;\n\tstruct cgroup *cgroup;\n};\n\nstruct bpf_cgroup_storage_key {\n\t__u64 cgroup_inode_id;\n\t__u32 attach_type;\n};\n\nstruct bpf_storage_buffer;\n\nstruct bpf_cgroup_storage_map;\n\nstruct bpf_cgroup_storage {\n\tunion {\n\t\tstruct bpf_storage_buffer *buf;\n\t\tvoid *percpu_buf;\n\t};\n\tstruct bpf_cgroup_storage_map *map;\n\tstruct bpf_cgroup_storage_key key;\n\tstruct list_head list_map;\n\tstruct list_head list_cg;\n\tstruct rb_node node;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_cgroup_storage_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tstruct rb_root root;\n\tstruct list_head list;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct skb_ext;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tlong unsigned int _nfct;\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\t__u8 active_extensions;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 ipvs_property: 1;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 ipvs_property: 1;\n\t\t\t__u8 offload_fwd_mark: 1;\n\t\t\t__u8 offload_l3_fwd_mark: 1;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tstruct skb_ext *extensions;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t\tu64 frame_sz_flags_init;\n\t};\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct qrwlock {\n\tunion {\n\t\tatomic_t cnts;\n\t\tstruct {\n\t\t\tu8 wlocked;\n\t\t\tu8 __lstate[3];\n\t\t};\n\t};\n\tarch_spinlock_t wait_lock;\n};\n\ntypedef struct qrwlock arch_rwlock_t;\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n};\n\nstruct sock_cgroup_data {\n\tstruct cgroup *cgroup;\n};\n\nstruct dst_entry;\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct socket;\n\nstruct mem_cgroup;\n\nstruct sock_reuseport;\n\nstruct bpf_local_storage;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\tstruct mem_cgroup *sk_memcg;\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tnetdev_features_t sk_route_caps;\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tktime_t sk_stamp;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tvoid *sk_security;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\ntypedef struct user_pt_regs bpf_user_pt_regs_t;\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_sample_data;\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nstruct bpf_sysctl {\n\t__u32 write;\n\t__u32 file_pos;\n};\n\nstruct ctl_table_header;\n\nstruct ctl_table;\n\nstruct bpf_sysctl_kern {\n\tstruct ctl_table_header *head;\n\tconst struct ctl_table *table;\n\tvoid *cur_val;\n\tsize_t cur_len;\n\tvoid *new_val;\n\tsize_t new_len;\n\tint new_updated;\n\tint write;\n\tloff_t *ppos;\n\tu64 tmp_reg;\n};\n\nstruct bpf_sockopt {\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *optval;\n\t};\n\tunion {\n\t\tvoid *optval_end;\n\t};\n\t__s32 level;\n\t__s32 optname;\n\t__s32 optlen;\n\t__s32 retval;\n};\n\nstruct bpf_sockopt_kern {\n\tstruct sock *sk;\n\tu8 *optval;\n\tu8 *optval_end;\n\ts32 level;\n\ts32 optname;\n\ts32 optlen;\n\tstruct task_struct *current_task;\n\tu64 tmp_reg;\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_CGROUP_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_CGROUP_SKB_kern;\n\tstruct bpf_sock BPF_PROG_TYPE_CGROUP_SOCK_prog;\n\tstruct sock BPF_PROG_TYPE_CGROUP_SOCK_kern;\n\tstruct bpf_sock_addr BPF_PROG_TYPE_CGROUP_SOCK_ADDR_prog;\n\tstruct bpf_sock_addr_kern BPF_PROG_TYPE_CGROUP_SOCK_ADDR_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_prog;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_kern;\n\tstruct bpf_sysctl BPF_PROG_TYPE_CGROUP_SYSCTL_prog;\n\tstruct bpf_sysctl_kern BPF_PROG_TYPE_CGROUP_SYSCTL_kern;\n\tstruct bpf_sockopt BPF_PROG_TYPE_CGROUP_SOCKOPT_prog;\n\tstruct bpf_sockopt_kern BPF_PROG_TYPE_CGROUP_SOCKOPT_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_prog;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_kern;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n};\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n};\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 0;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct dma_buf;\n\nstruct bpf_iter__dmabuf {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct dma_buf *dmabuf;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 0;\n\tint bucket;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n};\n\nstruct bpf_iter_dmabuf {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_dmabuf_kern {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 0;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n};\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tatomic64_t revision;\n\tu32 count;\n};\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\ntypedef unsigned int nf_hookfn(void *, struct sk_buff *, const struct nf_hook_state *);\n\nstruct nf_hook_ops {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tnf_hookfn *hook;\n\tstruct net_device *dev;\n\tvoid *priv;\n\tu8 pf;\n\tenum nf_hook_ops_type hook_ops_type: 8;\n\tunsigned int hooknum;\n\tint priority;\n};\n\nstruct nf_defrag_hook;\n\nstruct bpf_nf_link {\n\tstruct bpf_link link;\n\tstruct nf_hook_ops hook_ops;\n\tnetns_tracker ns_tracker;\n\tstruct net *net;\n\tu32 dead;\n\tconst struct nf_defrag_hook *defrag_hook;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_perf_link {\n\tstruct bpf_link link;\n\tstruct file *perf_file;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_plt {\n\tu32 insn_ldr;\n\tu32 insn_br;\n\tu64 target;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tvoid *security;\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_list {\n\tstruct hlist_node node;\n\tstruct bpf_prog *prog;\n\tstruct bpf_cgroup_link *link;\n\tstruct bpf_cgroup_storage *storage[2];\n\tu32 flags;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct tracepoint;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 64;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\trqspinlock_t spinlock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t busy;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int consumer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct bpf_session_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tbool is_return;\n\tvoid *data;\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_sockopt_buf {\n\tu8 data[32];\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nstruct stack_map_bucket;\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_storage_buffer {\n\tstruct callback_head rcu;\n\tchar data[0];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_dummy_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_ext_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n\tvoid *security;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n};\n\nunion perf_sample_weight {\n\t__u64 full;\n\tstruct {\n\t\t__u32 var1_dw;\n\t\t__u16 var2_w;\n\t\t__u16 var3_w;\n\t};\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_op: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_blk: 3;\n\t\t__u64 mem_hops: 3;\n\t\t__u64 mem_region: 5;\n\t\t__u64 mem_rsvd: 13;\n\t};\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n};\n\nstruct perf_callchain_entry;\n\nstruct perf_raw_record;\n\nstruct perf_branch_stack;\n\nstruct perf_sample_data {\n\tu64 sample_flags;\n\tu64 period;\n\tu64 dyn_size;\n\tu64 type;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tu64 ip;\n\tstruct perf_callchain_entry *callchain;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 *br_stack_cntr;\n\tunion perf_sample_weight weight;\n\tunion perf_mem_data_src data_src;\n\tu64 txn;\n\tstruct perf_regs regs_user;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 stream_id;\n\tu64 cgroup;\n\tu64 addr;\n\tu64 phys_addr;\n\tu64 data_page_size;\n\tu64 code_page_size;\n\tu64 aux_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[38];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct bpf_unwind_consume_entry_data {\n\tbool (*consume_entry)(void *, u64, u64, u64);\n\tvoid *cookie;\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *, __u64 *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *, __u64 *);\n\tbool (*filter)(struct uprobe_consumer *, struct mm_struct *);\n\tstruct list_head cons_node;\n\t__u64 id;\n};\n\nstruct bpf_uprobe_multi_link;\n\nstruct uprobe;\n\nstruct bpf_uprobe {\n\tstruct bpf_uprobe_multi_link *link;\n\tloff_t offset;\n\tlong unsigned int ref_ctr_offset;\n\tu64 cookie;\n\tstruct uprobe *uprobe;\n\tstruct uprobe_consumer consumer;\n\tbool session;\n};\n\nstruct bpf_uprobe_multi_link {\n\tstruct path path;\n\tstruct bpf_link link;\n\tu32 cnt;\n\tstruct bpf_uprobe *uprobes;\n\tstruct task_struct *task;\n};\n\nstruct bpf_uprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tlong unsigned int entry_ip;\n\tstruct bpf_uprobe *uprobe;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nstruct bq27xxx_device_info;\n\nstruct bq27xxx_access_methods {\n\tint (*read)(struct bq27xxx_device_info *, u8, bool);\n\tint (*write)(struct bq27xxx_device_info *, u8, int, bool);\n\tint (*read_bulk)(struct bq27xxx_device_info *, u8, u8 *, int);\n\tint (*write_bulk)(struct bq27xxx_device_info *, u8, u8 *, int);\n};\n\nstruct bq27xxx_reg_cache {\n\tint capacity;\n\tint flags;\n};\n\nunion power_supply_propval {\n\tint intval;\n\tconst char *strval;\n};\n\nstruct bq27xxx_dm_reg;\n\nstruct bq27xxx_device_info {\n\tstruct device *dev;\n\tenum bq27xxx_chip chip;\n\tu32 opts;\n\tconst char *name;\n\tstruct bq27xxx_dm_reg *dm_regs;\n\tu32 unseal_key;\n\tstruct bq27xxx_access_methods bus;\n\tstruct bq27xxx_reg_cache cache;\n\tint charge_design_full;\n\tint voltage_min_design;\n\tint voltage_max_design;\n\tbool removed;\n\tlong unsigned int last_update;\n\tunion power_supply_propval last_status;\n\tstruct delayed_work work;\n\tstruct power_supply *bat;\n\tstruct list_head list;\n\tstruct mutex lock;\n\tu8 *regs;\n};\n\nstruct bq27xxx_dm_buf {\n\tu8 class;\n\tu8 block;\n\tu8 data[32];\n\tbool has_data;\n\tbool dirty;\n};\n\nstruct bq27xxx_dm_reg {\n\tu8 subclass_id;\n\tu8 offset;\n\tu8 bytes;\n\tu16 min;\n\tu16 max;\n};\n\nstruct br_ip {\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t} src;\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t\tunsigned char mac_addr[6];\n\t} dst;\n\t__be16 proto;\n\t__u16 vid;\n};\n\nstruct br_mcast_stats {\n\t__u64 igmp_v1queries[2];\n\t__u64 igmp_v2queries[2];\n\t__u64 igmp_v3queries[2];\n\t__u64 igmp_leaves[2];\n\t__u64 igmp_v1reports[2];\n\t__u64 igmp_v2reports[2];\n\t__u64 igmp_v3reports[2];\n\t__u64 igmp_parse_errors;\n\t__u64 mld_v1queries[2];\n\t__u64 mld_v2queries[2];\n\t__u64 mld_leaves[2];\n\t__u64 mld_v1reports[2];\n\t__u64 mld_v2reports[2];\n\t__u64 mld_parse_errors;\n\t__u64 mcast_bytes[2];\n\t__u64 mcast_packets[2];\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct metadata_dst;\n\nstruct br_tunnel_info {\n\t__be64 tunnel_id;\n\tstruct metadata_dst *tunnel_dst;\n};\n\nstruct brbe_regset {\n\tu64 brbsrc;\n\tu64 brbtgt;\n\tu64 brbinf;\n};\n\nstruct brcm_rescal_reset {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct brcm_sata_phy;\n\nstruct brcm_sata_port {\n\tint portnum;\n\tstruct phy *phy;\n\tstruct brcm_sata_phy *phy_priv;\n\tbool ssc_en;\n\tenum brcm_sata_phy_rxaeq_mode rxaeq_mode;\n\tu32 rxaeq_val;\n\tu32 tx_amplitude_val;\n};\n\nstruct brcm_sata_phy {\n\tstruct device *dev;\n\tvoid *phy_base;\n\tvoid *ctrl_base;\n\tenum brcm_sata_phy_version version;\n\tstruct brcm_sata_port phys[2];\n};\n\nstruct brcm_usb_init_params;\n\nstruct brcm_usb_init_ops {\n\tvoid (*init_ipp)(struct brcm_usb_init_params *);\n\tvoid (*init_common)(struct brcm_usb_init_params *);\n\tvoid (*init_eohci)(struct brcm_usb_init_params *);\n\tvoid (*init_xhci)(struct brcm_usb_init_params *);\n\tvoid (*uninit_common)(struct brcm_usb_init_params *);\n\tvoid (*uninit_eohci)(struct brcm_usb_init_params *);\n\tvoid (*uninit_xhci)(struct brcm_usb_init_params *);\n\tint (*get_dual_select)(struct brcm_usb_init_params *);\n\tvoid (*set_dual_select)(struct brcm_usb_init_params *);\n};\n\nstruct brcm_usb_init_params {\n\tvoid *regs[6];\n\tint ioc;\n\tint ipp;\n\tint supported_port_modes;\n\tint port_mode;\n\tu32 family_id;\n\tu32 product_id;\n\tint selected_family;\n\tconst char *family_name;\n\tconst u32 *usb_reg_bits_map;\n\tconst struct brcm_usb_init_ops *ops;\n\tstruct regmap *syscon_piarbctl;\n\tbool wake_enabled;\n};\n\nstruct brcm_usb_phy {\n\tstruct phy *phy;\n\tunsigned int id;\n\tbool inited;\n};\n\nstruct brcm_usb_phy_data {\n\tstruct brcm_usb_init_params ini;\n\tbool has_eohci;\n\tbool has_xhci;\n\tstruct clk *usb_20_clk;\n\tstruct clk *usb_30_clk;\n\tstruct clk *suspend_clk;\n\tstruct mutex mutex;\n\tint init_count;\n\tint wake_irq;\n\tstruct brcm_usb_phy phys[2];\n\tstruct notifier_block pm_notifier;\n\tbool pm_active;\n};\n\nstruct dpfe_api;\n\nstruct brcmstb_dpfe_priv {\n\tvoid *regs;\n\tvoid *dmem;\n\tvoid *imem;\n\tstruct device *dev;\n\tconst struct dpfe_api *dpfe_api;\n\tstruct mutex lock;\n};\n\nstruct brcmstb_gisb_arb_device {\n\tvoid *base;\n\tconst int *gisb_offsets;\n\tbool big_endian;\n\tstruct mutex lock;\n\tstruct list_head next;\n\tu32 valid_mask;\n\tconst char *master_names[32];\n\tu32 saved_timeout;\n};\n\nstruct brcmstb_gpio_priv;\n\nstruct brcmstb_gpio_bank {\n\tstruct list_head node;\n\tint id;\n\tstruct gpio_generic_chip chip;\n\tstruct brcmstb_gpio_priv *parent_priv;\n\tu32 width;\n\tu32 wake_active;\n\tu32 saved_regs[7];\n};\n\nstruct brcmstb_gpio_priv {\n\tstruct list_head bank_list;\n\tvoid *reg_base;\n\tstruct platform_device *pdev;\n\tstruct irq_domain *irq_domain;\n\tstruct irq_chip irq_chip;\n\tint parent_irq;\n\tint num_gpios;\n\tint parent_wake_irq;\n};\n\nstruct bsc_regs;\n\nstruct brcmstb_i2c_dev {\n\tstruct device *device;\n\tvoid *base;\n\tint irq;\n\tstruct bsc_regs *bsc_regmap;\n\tstruct i2c_adapter adapter;\n\tstruct completion done;\n\tu32 clk_freq_hz;\n\tint data_regsz;\n\tbool atomic;\n};\n\nstruct brcmstb_intc_init_params {\n\tirq_flow_handler_t handler;\n\tint cpu_status;\n\tint cpu_clear;\n\tint cpu_mask_status;\n\tint cpu_mask_set;\n\tint cpu_mask_clear;\n};\n\nstruct irq_chip_generic;\n\nstruct brcmstb_l2_intc_data {\n\tstruct irq_domain *domain;\n\tstruct irq_chip_generic *gc;\n\tint status_offset;\n\tint mask_offset;\n\tbool can_wake;\n\tu32 saved_mask;\n};\n\nstruct sdhci_host;\n\nstruct mmc_host;\n\nstruct mmc_ios;\n\nstruct sdhci_ops;\n\nstruct brcmstb_match_priv {\n\tvoid (*cfginit)(struct sdhci_host *);\n\tvoid (*hs400es)(struct mmc_host *, struct mmc_ios *);\n\tvoid (*save_restore_regs)(struct mmc_host *, int);\n\tstruct sdhci_ops *ops;\n\tconst unsigned int flags;\n};\n\nstruct brcmstb_memc {\n\tstruct device *dev;\n\tvoid *ddr_ctrl;\n\tunsigned int timeout_cycles;\n\tu32 frequency;\n\tu32 srpd_offset;\n};\n\nstruct brcmstb_memc_data {\n\tu32 srpd_offset;\n};\n\nstruct pin_regs;\n\nstruct brcmstb_pin_funcs;\n\nstruct brcmstb_pdata {\n\tconst struct pinctrl_desc *pctl_desc;\n\tconst struct pinctrl_gpio_range *gpio_range;\n\tconst struct pin_regs *pin_regs;\n\tconst struct brcmstb_pin_funcs *pin_funcs;\n\tconst unsigned int func_count;\n\tconst unsigned int func_gpio;\n\tconst char * const *func_names;\n};\n\nstruct brcmstb_pin_funcs {\n\tconst u32 func_mask;\n\tconst u8 *funcs;\n\tconst unsigned int n_funcs;\n};\n\nstruct brcmstb_pinctrl {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct pinctrl_desc pctl_desc;\n\tconst struct pin_regs *pin_regs;\n\tconst struct brcmstb_pin_funcs *pin_funcs;\n\tconst char * const *func_names;\n\tunsigned int func_count;\n\tunsigned int func_gpio;\n\tconst char * const *gpio_groups;\n\tstruct pinctrl_gpio_range gpio_range;\n\tspinlock_t fsel_lock;\n};\n\nstruct brcmstb_reset {\n\tvoid *base;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct in_pin;\n\nstruct out_pin;\n\nstruct brcmstb_usb_pinmap_data {\n\tvoid *regs;\n\tint in_count;\n\tstruct in_pin *in_pins;\n\tint out_count;\n\tstruct out_pin *out_pins;\n};\n\nstruct brcmstb_waketmr {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tvoid *base;\n\tunsigned int wake_irq;\n\tunsigned int alarm_irq;\n\tstruct notifier_block reboot_notifier;\n\tstruct clk *clk;\n\tu32 rate;\n\tlong unsigned int rtc_alarm;\n\tbool alarm_en;\n\tbool alarm_expired;\n};\n\nstruct uart_8250_port;\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_tx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan *rxchan;\n\tstruct dma_chan *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct brcmuart_priv {\n\tint line;\n\tstruct clk *baud_mux_clk;\n\tlong unsigned int default_mux_rate;\n\tu32 real_rates[4];\n\tconst u32 *rate_table;\n\tktime_t char_wait;\n\tstruct uart_port *up;\n\tstruct hrtimer hrt;\n\tbool shutdown;\n\tbool dma_enabled;\n\tstruct uart_8250_dma dma;\n\tvoid *regs[5];\n\tdma_addr_t rx_addr;\n\tvoid *rx_bufs;\n\tsize_t rx_size;\n\tint rx_next_buf;\n\tdma_addr_t tx_addr;\n\tvoid *tx_buf;\n\tsize_t tx_size;\n\tbool tx_running;\n\tbool rx_running;\n\tstruct dentry *debugfs_dir;\n\tu64 dma_rx_partial_buf;\n\tu64 dma_rx_full_buf;\n\tu32 rx_bad_timeout_late_char;\n\tu32 rx_bad_timeout_no_char;\n\tu32 rx_missing_close_timeout;\n\tu32 rx_err;\n\tu32 rx_timeout;\n\tu32 rx_abort;\n\tu32 saved_mctrl;\n};\n\nstruct bridge_id {\n\tunsigned char prio[2];\n\tunsigned char addr[6];\n};\n\ntypedef struct bridge_id bridge_id;\n\nstruct bridge_mcast_other_query {\n\tstruct timer_list timer;\n\tstruct timer_list delay_timer;\n};\n\nstruct bridge_mcast_own_query {\n\tstruct timer_list timer;\n\tu32 startup_sent;\n};\n\nstruct bridge_mcast_querier {\n\tstruct br_ip addr;\n\tint port_ifidx;\n\tseqcount_spinlock_t seq;\n};\n\nstruct bridge_mcast_stats {\n\tstruct br_mcast_stats mstats;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct bridge_stp_xstats {\n\t__u64 transition_blk;\n\t__u64 transition_fwd;\n\t__u64 rx_bpdu;\n\t__u64 tx_bpdu;\n\t__u64 rx_tcn;\n\t__u64 tx_tcn;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct bsc_clk_param {\n\tu32 hz;\n\tu32 scl_mask;\n\tu32 div_mask;\n};\n\nstruct bsc_regs {\n\tu32 chip_address;\n\tu32 data_in[8];\n\tu32 cnt_reg;\n\tu32 ctl_reg;\n\tu32 iic_enable;\n\tu32 data_out[8];\n\tu32 ctlhi_reg;\n\tu32 scl_param;\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct bsd_acct_struct {\n\tstruct fs_pin pin;\n\tatomic_long_t count;\n\tstruct callback_head rcu;\n\tstruct mutex lock;\n\tbool active;\n\tbool check_space;\n\tlong unsigned int needcheck;\n\tstruct file *file;\n\tstruct pid_namespace *ns;\n\tstruct work_struct work;\n\tstruct completion done;\n\tacct_t ac;\n};\n\nstruct bsg_buffer {\n\tunsigned int payload_len;\n\tint sg_cnt;\n\tstruct scatterlist *sg_list;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n};\n\nstruct bsg_job {\n\tstruct device *dev;\n\tstruct kref kref;\n\tunsigned int timeout;\n\tvoid *request;\n\tvoid *reply;\n\tunsigned int request_len;\n\tunsigned int reply_len;\n\tstruct bsg_buffer request_payload;\n\tstruct bsg_buffer reply_payload;\n\tint result;\n\tunsigned int reply_payload_rcv_len;\n\tstruct request *bidi_rq;\n\tstruct bio *bidi_bio;\n\tvoid *dd_data;\n};\n\ntypedef int bsg_job_fn(struct bsg_job *);\n\ntypedef enum blk_eh_timer_return bsg_timeout_fn(struct request *);\n\nstruct bsg_set {\n\tstruct blk_mq_tag_set tag_set;\n\tstruct bsg_device *bd;\n\tbsg_job_fn *job_fn;\n\tbsg_timeout_fn *timeout_fn;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[56];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_ptr {\n\tvoid *ptr;\n\t__u32 type_id;\n\t__u32 flags;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, va_list);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 64;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\nstruct bufdesc {\n\t__le16 cbd_datlen;\n\t__le16 cbd_sc;\n\t__le32 cbd_bufaddr;\n};\n\nstruct bufdesc_ex {\n\tstruct bufdesc desc;\n\t__le32 cbd_esc;\n\t__le32 cbd_prot;\n\t__le32 cbd_bdu;\n\t__le32 ts;\n\t__le16 res0[4];\n};\n\nstruct bufdesc_prop {\n\tint qid;\n\tstruct bufdesc *base;\n\tstruct bufdesc *last;\n\tstruct bufdesc *cur;\n\tvoid *reg_desc_active;\n\tdma_addr_t dma;\n\tshort unsigned int ring_size;\n\tunsigned char dsize;\n\tunsigned char dsize_log2;\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n};\n\nstruct buffer_data_read_page {\n\tunsigned int order;\n\tstruct buffer_data_page *data;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tunsigned int order;\n\tu32 id: 30;\n\tu32 range: 1;\n\tstruct buffer_data_page *page;\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct bug_entry {\n\tint bug_addr_disp;\n\tint file_disp;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct bulk_cb_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 DataTransferLength;\n\t__u8 Flags;\n\t__u8 Lun;\n\t__u8 Length;\n\t__u8 CDB[16];\n};\n\nstruct bulk_cs_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 Residue;\n\t__u8 Status;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct cache_coherency_ops_inst;\n\nstruct cc_inval_params;\n\nstruct cache_coherency_ops {\n\tint (*wbinv)(struct cache_coherency_ops_inst *, struct cc_inval_params *);\n\tint (*done)(struct cache_coherency_ops_inst *);\n};\n\nstruct cache_coherency_ops_inst {\n\tstruct kref kref;\n\tstruct list_head node;\n\tconst struct cache_coherency_ops *ops;\n};\n\nstruct cache_head;\n\nstruct cache_deferred_req {\n\tstruct hlist_node hash;\n\tstruct list_head recent;\n\tstruct cache_head *item;\n\tvoid *owner;\n\tvoid (*revisit)(struct cache_deferred_req *, int);\n};\n\nstruct cache_detail {\n\tstruct module *owner;\n\tint hash_size;\n\tstruct hlist_head *hash_table;\n\tspinlock_t hash_lock;\n\tchar *name;\n\tvoid (*cache_put)(struct kref *);\n\tint (*cache_upcall)(struct cache_detail *, struct cache_head *);\n\tvoid (*cache_request)(struct cache_detail *, struct cache_head *, char **, int *);\n\tint (*cache_parse)(struct cache_detail *, char *, int);\n\tint (*cache_show)(struct seq_file *, struct cache_detail *, struct cache_head *);\n\tvoid (*warn_no_listener)(struct cache_detail *, int);\n\tstruct cache_head * (*alloc)(void);\n\tvoid (*flush)(void);\n\tint (*match)(struct cache_head *, struct cache_head *);\n\tvoid (*init)(struct cache_head *, struct cache_head *);\n\tvoid (*update)(struct cache_head *, struct cache_head *);\n\ttime64_t flush_time;\n\tstruct list_head others;\n\ttime64_t nextcheck;\n\tint entries;\n\tstruct list_head queue;\n\tatomic_t writers;\n\ttime64_t last_close;\n\ttime64_t last_warn;\n\tunion {\n\t\tstruct proc_dir_entry *procfs;\n\t\tstruct dentry *pipefs;\n\t};\n\tstruct net *net;\n};\n\nstruct cache_head {\n\tstruct hlist_node cache_list;\n\ttime64_t expiry_time;\n\ttime64_t last_refresh;\n\tstruct kref ref;\n\tlong unsigned int flags;\n};\n\nstruct cache_queue {\n\tstruct list_head list;\n\tint reader;\n};\n\nstruct cache_reader {\n\tstruct cache_queue q;\n\tint offset;\n};\n\nstruct cache_req {\n\tstruct cache_deferred_req * (*defer)(struct cache_req *);\n\tlong unsigned int thread_wait;\n};\n\nstruct cache_req___2 {\n\tu32 addr;\n\tu32 sleep_val;\n\tu32 wake_val;\n\tstruct list_head list;\n};\n\nstruct cache_request {\n\tstruct cache_queue q;\n\tstruct cache_head *item;\n\tchar *buf;\n\tint len;\n\tint readers;\n};\n\nstruct cache_type_info {\n\tconst char *size_prop;\n\tconst char *line_size_props[2];\n\tconst char *nr_sets_prop;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct cb_process_state;\n\nstruct xdr_stream;\n\nstruct callback_op {\n\t__be32 (*process_op)(void *, void *, struct cb_process_state *);\n\t__be32 (*decode_args)(struct svc_rqst *, struct xdr_stream *, void *);\n\t__be32 (*encode_res)(struct svc_rqst *, struct xdr_stream *, const void *);\n\tlong int res_maxsize;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nstruct capsule_info {\n\tefi_capsule_header_t header;\n\tefi_capsule_header_t *capsule;\n\tint reset_type;\n\tlong int index;\n\tsize_t count;\n\tsize_t total_size;\n\tstruct page **pages;\n\tphys_addr_t *phys;\n\tsize_t page_bytes_remain;\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct cavium_mdiobus {\n\tstruct mii_bus *mii_bus;\n\tvoid *register_base;\n\tenum cavium_mdiobus_mode mode;\n};\n\nstruct cavium_rng {\n\tstruct hwrng ops;\n\tvoid *result;\n\tvoid *pf_regbase;\n\tstruct pci_dev *pdev;\n\tu64 clock_rate;\n\tu64 prev_error;\n\tu64 prev_time;\n};\n\nstruct cavium_rng_pf {\n\tvoid *control_status;\n};\n\nstruct cavium_smmu {\n\tstruct arm_smmu_device___2 smmu;\n\tu32 id_base;\n};\n\nstruct cb_compound_hdr_arg {\n\tunsigned int taglen;\n\tconst char *tag;\n\tunsigned int minorversion;\n\tunsigned int cb_ident;\n\tunsigned int nops;\n};\n\nstruct cb_compound_hdr_res {\n\t__be32 *status;\n\tunsigned int taglen;\n\tconst char *tag;\n\t__be32 *nops;\n};\n\nstruct cb_devicenotifyitem;\n\nstruct cb_devicenotifyargs {\n\tuint32_t ndevs;\n\tstruct cb_devicenotifyitem *devs;\n};\n\nstruct nfs4_deviceid {\n\tchar data[16];\n};\n\nstruct cb_devicenotifyitem {\n\tuint32_t cbd_notify_type;\n\tuint32_t cbd_layout_type;\n\tstruct nfs4_deviceid cbd_dev_id;\n\tuint32_t cbd_immediate;\n};\n\nstruct nfs_fh {\n\tshort unsigned int size;\n\tunsigned char data[128];\n};\n\nstruct cb_getattrargs {\n\tstruct nfs_fh fh;\n\tuint32_t bitmap[3];\n};\n\nstruct cb_getattrres {\n\t__be32 status;\n\tuint32_t bitmap[3];\n\tuint64_t size;\n\tuint64_t change_attr;\n\tstruct timespec64 atime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 mtime;\n};\n\nstruct pnfs_layout_range {\n\tu32 iomode;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct nfs4_stateid_struct {\n\tunion {\n\t\tchar data[16];\n\t\tstruct {\n\t\t\t__be32 seqid;\n\t\t\tchar other[12];\n\t\t};\n\t};\n\tenum {\n\t\tNFS4_INVALID_STATEID_TYPE = 0,\n\t\tNFS4_SPECIAL_STATEID_TYPE = 1,\n\t\tNFS4_OPEN_STATEID_TYPE = 2,\n\t\tNFS4_LOCK_STATEID_TYPE = 3,\n\t\tNFS4_DELEGATION_STATEID_TYPE = 4,\n\t\tNFS4_LAYOUT_STATEID_TYPE = 5,\n\t\tNFS4_PNFS_DS_STATEID_TYPE = 6,\n\t\tNFS4_REVOKED_STATEID_TYPE = 7,\n\t\tNFS4_FREED_STATEID_TYPE = 8,\n\t} type;\n};\n\ntypedef struct nfs4_stateid_struct nfs4_stateid;\n\nstruct nfs_fsid {\n\tuint64_t major;\n\tuint64_t minor;\n};\n\nstruct cb_layoutrecallargs {\n\tuint32_t cbl_recall_type;\n\tuint32_t cbl_layout_type;\n\tuint32_t cbl_layoutchanged;\n\tunion {\n\t\tstruct {\n\t\t\tstruct nfs_fh cbl_fh;\n\t\t\tstruct pnfs_layout_range cbl_range;\n\t\t\tnfs4_stateid cbl_stateid;\n\t\t};\n\t\tstruct nfs_fsid cbl_fsid;\n\t};\n};\n\nstruct nfs_lowner {\n\t__u64 clientid;\n\t__u64 id;\n\tdev_t s_dev;\n};\n\nstruct cb_notify_lock_args {\n\tstruct nfs_fh cbnl_fh;\n\tstruct nfs_lowner cbnl_owner;\n\tbool cbnl_valid;\n};\n\nstruct nfs_write_verifier {\n\tchar data[8];\n};\n\nstruct nfs_writeverf {\n\tstruct nfs_write_verifier verifier;\n\tenum nfs3_stable_how committed;\n};\n\nstruct cb_offloadargs {\n\tstruct nfs_fh coa_fh;\n\tnfs4_stateid coa_stateid;\n\tuint32_t error;\n\tuint64_t wr_count;\n\tstruct nfs_writeverf wr_writeverf;\n};\n\nstruct nfs_client;\n\nstruct nfs4_slot;\n\nstruct cb_process_state {\n\tstruct nfs_client *clp;\n\tstruct nfs4_slot *slot;\n\tstruct net *net;\n\tu32 minorversion;\n\t__be32 drc_status;\n\tunsigned int referring_calls;\n};\n\nstruct cb_recallanyargs {\n\tuint32_t craa_objs_to_keep;\n\tuint32_t craa_type_mask;\n};\n\nstruct cb_recallargs {\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tuint32_t truncate;\n};\n\nstruct cb_recallslotargs {\n\tuint32_t crsa_target_highest_slotid;\n};\n\nstruct nfs4_sessionid {\n\tunsigned char data[16];\n};\n\nstruct referring_call_list;\n\nstruct cb_sequenceargs {\n\tstruct sockaddr *csa_addr;\n\tstruct nfs4_sessionid csa_sessionid;\n\tuint32_t csa_sequenceid;\n\tuint32_t csa_slotid;\n\tuint32_t csa_highestslotid;\n\tuint32_t csa_cachethis;\n\tuint32_t csa_nrclists;\n\tstruct referring_call_list *csa_rclists;\n};\n\nstruct cb_sequenceres {\n\t__be32 csr_status;\n\tstruct nfs4_sessionid csr_sessionid;\n\tuint32_t csr_sequenceid;\n\tuint32_t csr_slotid;\n\tuint32_t csr_highestslotid;\n\tuint32_t csr_target_highestslotid;\n};\n\nstruct cc_inval_params {\n\tphys_addr_t addr;\n\tsize_t size;\n};\n\nstruct ccsr_guts {\n\tu32 porpllsr;\n\tu32 porbmsr;\n\tu32 porimpscr;\n\tu32 pordevsr;\n\tu32 pordbgmsr;\n\tu32 pordevsr2;\n\tu8 res018[8];\n\tu32 porcir;\n\tu8 res024[12];\n\tu32 gpiocr;\n\tu8 res034[12];\n\tu32 gpoutdr;\n\tu8 res044[12];\n\tu32 gpindr;\n\tu8 res054[12];\n\tu32 pmuxcr;\n\tu32 pmuxcr2;\n\tu32 dmuxcr;\n\tu8 res06c[4];\n\tu32 devdisr;\n\tu32 devdisr2;\n\tu8 res078[4];\n\tu32 pmjcr;\n\tu32 powmgtcsr;\n\tu32 pmrccr;\n\tu32 pmpdccr;\n\tu32 pmcdr;\n\tu32 mcpsumr;\n\tu32 rstrscr;\n\tu32 ectrstcr;\n\tu32 autorstsr;\n\tu32 pvr;\n\tu32 svr;\n\tu8 res0a8[8];\n\tu32 rstcr;\n\tu8 res0b4[12];\n\tu32 iovselsr;\n\tu8 res0c4[60];\n\tu32 rcwsr[16];\n\tu8 res140[228];\n\tu32 iodelay1;\n\tu32 iodelay2;\n\tu8 res22c[984];\n\tu32 pamubypenr;\n\tu8 res608[504];\n\tu32 clkdvdr;\n\tu8 res804[252];\n\tu32 ircr;\n\tu8 res904[4];\n\tu32 dmacr;\n\tu8 res90c[8];\n\tu32 elbccr;\n\tu8 res918[520];\n\tu32 ddr1clkdr;\n\tu32 ddr2clkdr;\n\tu32 ddrclkdr;\n\tu8 resb2c[724];\n\tu32 clkocr;\n\tu8 rese04[12];\n\tu32 ddrdllcr;\n\tu8 rese14[12];\n\tu32 lbcdllcr;\n\tu32 cpfor;\n\tu8 rese28[220];\n\tu32 srds1cr0;\n\tu32 srds1cr1;\n\tu8 resf0c[32];\n\tu32 itcr;\n\tu8 resf30[16];\n\tu32 srds2cr0;\n\tu32 srds2cr1;\n};\n\nstruct ccu_common {\n\tvoid *base;\n\tu16 reg;\n\tu16 lock_reg;\n\tu32 prediv;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int features;\n\tspinlock_t *lock;\n\tstruct clk_hw hw;\n};\n\nstruct ccu_div_internal {\n\tu8 shift;\n\tu8 width;\n\tu32 max;\n\tu32 offset;\n\tu32 flags;\n\tstruct clk_div_table *table;\n};\n\nstruct ccu_mux_fixed_prediv;\n\nstruct ccu_mux_var_prediv;\n\nstruct ccu_mux_internal {\n\tu8 shift;\n\tu8 width;\n\tconst u8 *table;\n\tconst struct ccu_mux_fixed_prediv *fixed_predivs;\n\tu8 n_predivs;\n\tconst struct ccu_mux_var_prediv *var_predivs;\n\tu8 n_var_predivs;\n};\n\nstruct ccu_div {\n\tu32 enable;\n\tstruct ccu_div_internal div;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common common;\n\tunsigned int fixed_post_div;\n};\n\nstruct ccu_frac_internal {\n\tu32 enable;\n\tu32 select;\n\tlong unsigned int rates[2];\n};\n\nstruct ccu_gate {\n\tu32 enable;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mp {\n\tu32 enable;\n\tstruct ccu_div_internal m;\n\tstruct ccu_div_internal p;\n\tstruct ccu_mux_internal mux;\n\tunsigned int fixed_post_div;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mult_internal {\n\tu8 offset;\n\tu8 shift;\n\tu8 width;\n\tu8 min;\n\tu8 max;\n};\n\nstruct ccu_mult {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_frac_internal frac;\n\tstruct ccu_mult_internal mult;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mux {\n\tu32 enable;\n\tstruct ccu_mux_internal mux;\n\tstruct ccu_common common;\n};\n\nstruct ccu_mux_fixed_prediv {\n\tu8 index;\n\tu16 div;\n};\n\nstruct ccu_mux_nb {\n\tstruct notifier_block clk_nb;\n\tstruct ccu_common *common;\n\tstruct ccu_mux_internal *cm;\n\tu32 delay_us;\n\tu8 bypass_index;\n\tu8 original_index;\n};\n\nstruct ccu_mux_var_prediv {\n\tu8 index;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct ccu_nk {\n\tu16 reg;\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tunsigned int fixed_post_div;\n\tstruct ccu_common common;\n};\n\nstruct ccu_nkm {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tstruct ccu_div_internal m;\n\tstruct ccu_mux_internal mux;\n\tunsigned int fixed_post_div;\n\tlong unsigned int max_m_n_ratio;\n\tlong unsigned int min_parent_m_ratio;\n\tstruct ccu_common common;\n};\n\nstruct ccu_nkmp {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_mult_internal k;\n\tstruct ccu_div_internal m;\n\tstruct ccu_div_internal p;\n\tunsigned int fixed_post_div;\n\tunsigned int max_rate;\n\tstruct ccu_common common;\n};\n\nstruct ccu_sdm_setting;\n\nstruct ccu_sdm_internal {\n\tstruct ccu_sdm_setting *table;\n\tu32 table_size;\n\tu32 enable;\n\tu32 tuning_enable;\n\tu16 tuning_reg;\n};\n\nstruct ccu_nm {\n\tu32 enable;\n\tu32 lock;\n\tstruct ccu_mult_internal n;\n\tstruct ccu_div_internal m;\n\tstruct ccu_frac_internal frac;\n\tstruct ccu_sdm_internal sdm;\n\tunsigned int fixed_post_div;\n\tunsigned int min_rate;\n\tunsigned int max_rate;\n\tstruct ccu_common common;\n};\n\nstruct ccu_phase {\n\tu8 shift;\n\tu8 width;\n\tstruct ccu_common common;\n};\n\nstruct ccu_pll_nb {\n\tstruct notifier_block clk_nb;\n\tstruct ccu_common *common;\n\tu32 enable;\n\tu32 lock;\n};\n\nstruct ccu_reset_map;\n\nstruct ccu_reset {\n\tvoid *base;\n\tconst struct ccu_reset_map *reset_map;\n\tspinlock_t *lock;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct ccu_reset_map {\n\tu16 reg;\n\tu32 bit;\n};\n\nstruct ccu_sdm_setting {\n\tlong unsigned int rate;\n\tu32 pattern;\n\tu32 m;\n\tu32 n;\n};\n\nstruct cdns_platform_data {\n\tu32 quirks;\n};\n\nstruct cdns_uart {\n\tstruct uart_port *port;\n\tstruct clk *uartclk;\n\tstruct clk *pclk;\n\tunsigned int baud;\n\tstruct notifier_block clk_rate_change_nb;\n\tu32 quirks;\n\tbool cts_override;\n\tstruct gpio_desc *gpiod_rts;\n\tbool rs485_tx_started;\n\tstruct hrtimer tx_timer;\n\tstruct reset_control *rstc;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct ceva_ahci_priv {\n\tstruct platform_device *ahci_pdev;\n\tu32 pp2c[2];\n\tu32 pp3c[2];\n\tu32 pp4c[2];\n\tu32 pp5c[2];\n\tu32 axicc;\n\tbool is_cci_enabled;\n\tint flags;\n};\n\nstruct cfg_param {\n\tconst char *property;\n\tenum tegra_pinconf_param param;\n};\n\nstruct cfi_private;\n\nstruct cfi_early_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct cfi_private *);\n};\n\nstruct cfi_extquery {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n};\n\nstruct mtd_info;\n\nstruct cfi_fixup {\n\tuint16_t mfr;\n\tuint16_t id;\n\tvoid (*fixup)(struct mtd_info *);\n};\n\nstruct cfi_ident {\n\tuint8_t qry[3];\n\tuint16_t P_ID;\n\tuint16_t P_ADR;\n\tuint16_t A_ID;\n\tuint16_t A_ADR;\n\tuint8_t VccMin;\n\tuint8_t VccMax;\n\tuint8_t VppMin;\n\tuint8_t VppMax;\n\tuint8_t WordWriteTimeoutTyp;\n\tuint8_t BufWriteTimeoutTyp;\n\tuint8_t BlockEraseTimeoutTyp;\n\tuint8_t ChipEraseTimeoutTyp;\n\tuint8_t WordWriteTimeoutMax;\n\tuint8_t BufWriteTimeoutMax;\n\tuint8_t BlockEraseTimeoutMax;\n\tuint8_t ChipEraseTimeoutMax;\n\tuint8_t DevSize;\n\tuint16_t InterfaceDesc;\n\tuint16_t MaxBufWriteSize;\n\tuint8_t NumEraseRegions;\n\tuint32_t EraseRegionInfo[0];\n} __attribute__((packed));\n\nstruct cfi_intelext_blockinfo {\n\tuint16_t NumIdentBlocks;\n\tuint16_t BlockSize;\n\tuint16_t MinBlockEraseCycles;\n\tuint8_t BitsPerCell;\n\tuint8_t BlockCap;\n};\n\nstruct cfi_intelext_otpinfo {\n\tuint32_t ProtRegAddr;\n\tuint16_t FactGroups;\n\tuint8_t FactProtRegSize;\n\tuint16_t UserGroups;\n\tuint8_t UserProtRegSize;\n} __attribute__((packed));\n\nstruct cfi_intelext_programming_regioninfo {\n\tuint8_t ProgRegShift;\n\tuint8_t Reserved1;\n\tuint8_t ControlValid;\n\tuint8_t Reserved2;\n\tuint8_t ControlInvalid;\n\tuint8_t Reserved3;\n};\n\nstruct cfi_intelext_regioninfo {\n\tuint16_t NumIdentPartitions;\n\tuint8_t NumOpAllowed;\n\tuint8_t NumOpAllowedSimProgMode;\n\tuint8_t NumOpAllowedSimEraMode;\n\tuint8_t NumBlockTypes;\n\tstruct cfi_intelext_blockinfo BlockTypes[1];\n};\n\nstruct cfi_pri_amdstd {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n\tuint8_t SiliconRevision;\n\tuint8_t EraseSuspend;\n\tuint8_t BlkProt;\n\tuint8_t TmpBlkUnprotect;\n\tuint8_t BlkProtUnprot;\n\tuint8_t SimultaneousOps;\n\tuint8_t BurstMode;\n\tuint8_t PageMode;\n\tuint8_t VppMin;\n\tuint8_t VppMax;\n\tuint8_t TopBottom;\n\tuint8_t ProgramSuspend;\n\tuint8_t UnlockBypass;\n\tuint8_t SecureSiliconSector;\n\tuint8_t SoftwareFeatures;\n};\n\nstruct cfi_pri_atmel {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n\tuint8_t Features;\n\tuint8_t BottomBoot;\n\tuint8_t BurstMode;\n\tuint8_t PageMode;\n};\n\nstruct cfi_pri_intelext {\n\tuint8_t pri[3];\n\tuint8_t MajorVersion;\n\tuint8_t MinorVersion;\n\tuint32_t FeatureSupport;\n\tuint8_t SuspendCmdSupport;\n\tuint16_t BlkStatusRegMask;\n\tuint8_t VccOptimal;\n\tuint8_t VppOptimal;\n\tuint8_t NumProtectionFields;\n\tuint16_t ProtRegAddr;\n\tuint8_t FactProtRegSize;\n\tuint8_t UserProtRegSize;\n\tuint8_t extra[0];\n} __attribute__((packed));\n\nstruct flchip {\n\tlong unsigned int start;\n\tint ref_point_counter;\n\tflstate_t state;\n\tflstate_t oldstate;\n\tunsigned int write_suspended: 1;\n\tunsigned int erase_suspended: 1;\n\tlong unsigned int in_progress_block_addr;\n\tlong unsigned int in_progress_block_mask;\n\tstruct mutex mutex;\n\twait_queue_head_t wq;\n\tint word_write_time;\n\tint buffer_write_time;\n\tint erase_time;\n\tint word_write_time_max;\n\tint buffer_write_time_max;\n\tint erase_time_max;\n\tvoid *priv;\n};\n\nstruct map_info;\n\nstruct cfi_private {\n\tuint16_t cmdset;\n\tvoid *cmdset_priv;\n\tint interleave;\n\tint device_type;\n\tint cfi_mode;\n\tint addr_unlock1;\n\tint addr_unlock2;\n\tstruct mtd_info * (*cmdset_setup)(struct map_info *);\n\tstruct cfi_ident *cfiq;\n\tint mfr;\n\tint id;\n\tint numchips;\n\tmap_word sector_erase_cmd;\n\tlong unsigned int chipshift;\n\tconst char *im_name;\n\tlong unsigned int quirks;\n\tstruct flchip chips[0];\n};\n\nstruct cfs_bandwidth {\n\traw_spinlock_t lock;\n\tktime_t period;\n\tu64 quota;\n\tu64 runtime;\n\tu64 burst;\n\tu64 runtime_snap;\n\ts64 hierarchical_quota;\n\tu8 idle;\n\tu8 period_active;\n\tu8 slack_started;\n\tstruct hrtimer period_timer;\n\tstruct hrtimer slack_timer;\n\tstruct list_head throttled_cfs_rq;\n\tint nr_periods;\n\tint nr_throttled;\n\tint nr_burst;\n\tu64 throttled_time;\n\tu64 burst_time;\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n};\n\nstruct sched_entity;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tint runtime_enabled;\n\ts64 runtime_remaining;\n\tu64 throttled_pelt_idle;\n\tu64 throttled_clock;\n\tu64 throttled_clock_pelt;\n\tu64 throttled_clock_pelt_time;\n\tu64 throttled_clock_self;\n\tu64 throttled_clock_self_time;\n\tbool throttled: 1;\n\tbool pelt_clock_throttled: 1;\n\tint throttle_count;\n\tstruct list_head throttled_list;\n\tstruct list_head throttled_csd_list;\n\tstruct list_head throttled_limbo_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cfs_schedulable_data {\n\tstruct task_group *tg;\n\tu64 period;\n\tu64 quota;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 ntime;\n};\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n};\n\nstruct cgroup_bpf {\n\tstruct bpf_prog_array *effective[28];\n\tstruct hlist_head progs[28];\n\tu8 flags[28];\n\tu64 revisions[28];\n\tstruct list_head storages;\n\tstruct bpf_prog_array *inactive;\n\tstruct percpu_ref refcnt;\n\tstruct work_struct release_work;\n};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[0];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[10];\n\tint nr_dying_subsys[10];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[10];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 64;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct linked_page;\n\nstruct chain_allocator {\n\tstruct linked_page *chain;\n\tunsigned int used_space;\n\tgfp_t gfp_mask;\n\tint safe_needed;\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct cros_ec_dev;\n\nstruct cros_ec_device;\n\nstruct port_data;\n\nstruct charger_data {\n\tstruct device *dev;\n\tstruct cros_ec_dev *ec_dev;\n\tstruct cros_ec_device *ec_device;\n\tint num_registered_psy;\n\tstruct port_data *ports[8];\n\tstruct notifier_block notifier;\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct check_loop_arg {\n\tstruct qdisc_walker w;\n\tstruct Qdisc *p;\n\tint depth;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct check_walk_data {\n\tenum pkvm_page_state desired;\n\tenum pkvm_page_state (*get_page_state)(kvm_pte_t, u64);\n};\n\nstruct mt6397_chip;\n\nstruct chip_data {\n\tu32 cid_addr;\n\tu32 cid_shift;\n\tconst struct mfd_cell *cells;\n\tint cell_size;\n\tint (*irq_init)(struct mt6397_chip *);\n};\n\nstruct chip_data___2 {\n\tu32 ctar_val;\n};\n\nstruct chip_data___3 {\n\tu32 cr0;\n\tu16 cr1;\n\tu16 dmacr;\n\tu16 cpsr;\n\tu8 n_bytes;\n\tbool enable_dma;\n\tenum ssp_reading read;\n\tenum ssp_writing write;\n\tint xfer_type;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct chip_desc {\n\tu8 nchans;\n\tu8 enable;\n\tu8 has_irq;\n\tenum muxtype muxtype;\n\tstruct i2c_device_identity id;\n};\n\nstruct chip_probe {\n\tchar *name;\n\tint (*probe_chip)(struct map_info *, __u32, long unsigned int *, struct cfi_private *);\n};\n\nstruct i2c_of_probe_cfg;\n\nstruct i2c_of_probe_simple_opts;\n\nstruct chromeos_i2c_probe_data {\n\tconst struct i2c_of_probe_cfg *cfg;\n\tconst struct i2c_of_probe_simple_opts *opts;\n};\n\nstruct hw_bank {\n\tunsigned int lpm;\n\tresource_size_t phys;\n\tvoid *abs;\n\tvoid *cap;\n\tvoid *op;\n\tsize_t size;\n\tvoid *regmap[39];\n};\n\nstruct usb_phy;\n\nstruct usb_bus;\n\nstruct usb_otg {\n\tu8 default_a;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_bus *host;\n\tstruct usb_gadget *gadget;\n\tenum usb_otg_state state;\n\tint (*set_host)(struct usb_otg *, struct usb_bus *);\n\tint (*set_peripheral)(struct usb_otg *, struct usb_gadget *);\n\tint (*set_vbus)(struct usb_otg *, bool);\n\tint (*start_srp)(struct usb_otg *);\n\tint (*start_hnp)(struct usb_otg *);\n};\n\nstruct otg_fsm_ops;\n\nstruct otg_fsm {\n\tint id;\n\tint adp_change;\n\tint power_up;\n\tint a_srp_det;\n\tint a_vbus_vld;\n\tint b_conn;\n\tint a_bus_resume;\n\tint a_bus_suspend;\n\tint a_conn;\n\tint b_se0_srp;\n\tint b_ssend_srp;\n\tint b_sess_vld;\n\tint test_device;\n\tint a_bus_drop;\n\tint a_bus_req;\n\tint b_bus_req;\n\tint a_sess_vld;\n\tint b_bus_resume;\n\tint b_bus_suspend;\n\tint drv_vbus;\n\tint loc_conn;\n\tint loc_sof;\n\tint adp_prb;\n\tint adp_sns;\n\tint data_pulse;\n\tint a_set_b_hnp_en;\n\tint b_srp_done;\n\tint b_hnp_enable;\n\tint a_clr_err;\n\tint a_bus_drop_inf;\n\tint a_bus_req_inf;\n\tint a_clr_err_inf;\n\tint b_bus_req_inf;\n\tint a_suspend_req_inf;\n\tint a_wait_vrise_tmout;\n\tint a_wait_vfall_tmout;\n\tint a_wait_bcon_tmout;\n\tint a_aidl_bdis_tmout;\n\tint b_ase0_brst_tmout;\n\tint a_bidl_adis_tmout;\n\tstruct otg_fsm_ops *ops;\n\tstruct usb_otg *otg;\n\tint protocol;\n\tstruct mutex lock;\n\tu8 *host_req_flag;\n\tstruct delayed_work hnp_polling_work;\n\tbool hnp_work_inited;\n\tbool state_changed;\n};\n\nstruct ci_hw_qh;\n\nstruct ci_hdrc;\n\nstruct td_node;\n\nstruct ci_hw_ep {\n\tstruct usb_ep ep;\n\tu8 dir;\n\tu8 num;\n\tu8 type;\n\tchar name[16];\n\tstruct {\n\t\tstruct list_head queue;\n\t\tstruct ci_hw_qh *ptr;\n\t\tdma_addr_t dma;\n\t} qh;\n\tint wedge;\n\tstruct ci_hdrc *ci;\n\tspinlock_t *lock;\n\tstruct dma_pool *td_pool;\n\tstruct td_node *pending_td;\n};\n\nstruct ulpi_ops {\n\tint (*read)(struct device *, u8);\n\tint (*write)(struct device *, u8, u8);\n};\n\nstruct ci_role_driver;\n\nstruct usb_role_switch;\n\nstruct ci_hdrc_platform_data;\n\nstruct ulpi;\n\nstruct usb_hcd;\n\nstruct ci_hdrc {\n\tstruct device *dev;\n\tspinlock_t lock;\n\tstruct hw_bank hw_bank;\n\tint irq;\n\tstruct ci_role_driver *roles[2];\n\tenum ci_role role;\n\tbool is_otg;\n\tstruct usb_otg otg;\n\tstruct otg_fsm fsm;\n\tstruct hrtimer otg_fsm_hrtimer;\n\tktime_t hr_timeouts[12];\n\tunsigned int enabled_otg_timer_bits;\n\tenum otg_fsm_timer next_otg_timer;\n\tstruct usb_role_switch *role_switch;\n\tstruct work_struct work;\n\tstruct work_struct power_lost_work;\n\tstruct workqueue_struct *wq;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *td_pool;\n\tstruct usb_gadget gadget;\n\tstruct usb_gadget_driver *driver;\n\tenum usb_device_state resume_state;\n\tunsigned int hw_ep_max;\n\tstruct ci_hw_ep ci_hw_ep[32];\n\tu32 ep0_dir;\n\tstruct ci_hw_ep *ep0out;\n\tstruct ci_hw_ep *ep0in;\n\tstruct usb_request *status;\n\tbool setaddr;\n\tu8 address;\n\tu8 remote_wakeup;\n\tu8 suspended;\n\tu8 test_mode;\n\tstruct ci_hdrc_platform_data *platdata;\n\tint vbus_active;\n\tstruct ulpi *ulpi;\n\tstruct ulpi_ops ulpi_ops;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_hcd *hcd;\n\tbool id_event;\n\tbool b_sess_valid_event;\n\tbool imx28_write_fix;\n\tbool has_portsc_pec_bug;\n\tbool has_short_pkt_limit;\n\tbool supports_runtime_pm;\n\tbool in_lpm;\n\tbool wakeup_int;\n\tenum ci_revision rev;\n\tstruct mutex mutex;\n};\n\nstruct extcon_dev;\n\nstruct ci_hdrc_cable {\n\tbool connected;\n\tbool changed;\n\tbool enabled;\n\tstruct extcon_dev *edev;\n\tstruct ci_hdrc *ci;\n\tstruct notifier_block nb;\n};\n\nstruct ci_hdrc_dma_aligned_buffer {\n\tvoid *original_buffer;\n\tu8 data[0];\n};\n\nstruct pm_qos_constraints;\n\nstruct pm_qos_request {\n\tstruct plist_node node;\n\tstruct pm_qos_constraints *qos;\n};\n\nstruct imx_usbmisc_data;\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct ci_hdrc_imx_platform_flag;\n\nstruct ci_hdrc_imx_data {\n\tstruct usb_phy *phy;\n\tstruct platform_device *ci_pdev;\n\tstruct clk *clk;\n\tstruct clk *clk_wakeup;\n\tstruct imx_usbmisc_data *usbmisc_data;\n\tint wakeup_irq;\n\tbool supports_runtime_pm;\n\tbool override_phy_control;\n\tbool in_lpm;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pinctrl_hsic_active;\n\tstruct regulator *hsic_pad_regulator;\n\tbool need_three_clks;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_per;\n\tstruct pm_qos_request pm_qos_req;\n\tconst struct ci_hdrc_imx_platform_flag *plat_data;\n};\n\nstruct ci_hdrc_imx_platform_flag {\n\tunsigned int flags;\n};\n\nstruct usb_otg_caps {\n\tu16 otg_rev;\n\tbool hnp_support;\n\tbool srp_support;\n\tbool adp_support;\n};\n\nstruct ci_hdrc_platform_data {\n\tconst char *name;\n\tuintptr_t capoffset;\n\tunsigned int power_budget;\n\tstruct phy *phy;\n\tstruct usb_phy *usb_phy;\n\tenum usb_phy_interface phy_mode;\n\tlong unsigned int flags;\n\tenum usb_dr_mode dr_mode;\n\tint (*notify_event)(struct ci_hdrc *, unsigned int);\n\tstruct regulator *reg_vbus;\n\tstruct usb_otg_caps ci_otg_caps;\n\tbool tpl_support;\n\tu32 itc_setting;\n\tu32 ahb_burst_config;\n\tu32 tx_burst_size;\n\tu32 rx_burst_size;\n\tstruct ci_hdrc_cable vbus_extcon;\n\tstruct ci_hdrc_cable id_extcon;\n\tu32 phy_clkgate_delay_us;\n\tstruct pinctrl *pctl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_host;\n\tstruct pinctrl_state *pins_device;\n\tint (*hub_control)(struct ci_hdrc *, u16, u16, u16, char *, u16, bool *, long unsigned int *);\n\tvoid (*enter_lpm)(struct ci_hdrc *, bool);\n};\n\nstruct ci_hdrc_msm {\n\tstruct platform_device *ci;\n\tstruct clk *core_clk;\n\tstruct clk *iface_clk;\n\tstruct clk *fs_clk;\n\tstruct ci_hdrc_platform_data pdata;\n\tstruct reset_controller_dev rcdev;\n\tbool secondary_phy;\n\tbool hsic;\n\tvoid *base;\n};\n\nstruct ci_hdrc_pci {\n\tstruct platform_device *ci;\n\tstruct platform_device *phy;\n};\n\nstruct ci_hdrc_usb2_priv {\n\tstruct platform_device *ci_pdev;\n\tstruct clk *clk;\n};\n\nstruct ci_hw_td {\n\t__le32 next;\n\t__le32 token;\n\t__le32 page[5];\n};\n\nstruct ci_hw_qh {\n\t__le32 cap;\n\t__le32 curr;\n\tstruct ci_hw_td td;\n\t__le32 RESERVED;\n\tstruct usb_ctrlrequest setup;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct ci_hw_req {\n\tstruct usb_request req;\n\tstruct list_head queue;\n\tstruct list_head tds;\n\tstruct sg_table sgt;\n};\n\nstruct ci_role_driver {\n\tint (*start)(struct ci_hdrc *);\n\tvoid (*stop)(struct ci_hdrc *);\n\tvoid (*suspend)(struct ci_hdrc *);\n\tvoid (*resume)(struct ci_hdrc *, bool);\n\tirqreturn_t (*irq)(struct ci_hdrc *);\n\tconst char *name;\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct circ_buf {\n\tchar *buf;\n\tint head;\n\tint tail;\n};\n\nstruct mmc_card;\n\nstruct sdio_func;\n\ntypedef int tpl_parse_t(struct mmc_card *, struct sdio_func *, const unsigned char *, unsigned int);\n\nstruct cis_tpl {\n\tunsigned char code;\n\tunsigned char min_size;\n\ttpl_parse_t *parse;\n};\n\nstruct cix_mbox_con_priv {\n\tenum cix_mbox_chan_type type;\n\tstruct mbox_chan *chan;\n\tint index;\n};\n\nunion cix_mbox_msg_reg_fifo {\n\tu32 length;\n\tu32 buf[32];\n};\n\nstruct cix_mbox_priv {\n\tstruct device *dev;\n\tint irq;\n\tint dir;\n\tvoid *base;\n\tstruct cix_mbox_con_priv con_priv[11];\n\tstruct mbox_chan mbox_chans[11];\n\tstruct mbox_controller mbox;\n\tbool use_shmem;\n};\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_info {\n\tint class;\n\tchar *class_name;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct cleanup_done_msg {\n\t__le32 version;\n\t__le32 response;\n\t__le32 seq_num;\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct clk {\n\tstruct clk_core *core;\n\tstruct device *dev;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tunsigned int exclusive_count;\n\tstruct hlist_node clks_node;\n};\n\nstruct clk_regmap {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int enable_reg;\n\tunsigned int enable_mask;\n\tbool enable_is_inverted;\n};\n\nstruct pll_vco;\n\nstruct clk_alpha_pll {\n\tu32 offset;\n\tconst u8 *regs;\n\tconst struct alpha_pll_config *config;\n\tconst struct pll_vco *vco_table;\n\tsize_t num_vco;\n\tu8 flags;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_alpha_pll_postdiv {\n\tu32 offset;\n\tu8 width;\n\tconst u8 *regs;\n\tstruct clk_regmap clkr;\n\tint post_div_shift;\n\tconst struct clk_div_table *post_div_table;\n\tsize_t num_post_div;\n};\n\nstruct clk_bit_field {\n\tu8 shift;\n\tu8 width;\n};\n\nstruct clk_branch {\n\tu32 hwcg_reg;\n\tu32 halt_reg;\n\tu8 hwcg_bit;\n\tu8 halt_bit;\n\tu8 halt_check;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct clk_bulk_devres {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct clk_ops;\n\nstruct clk_busy_divider {\n\tstruct clk_divider div;\n\tconst struct clk_ops *div_ops;\n\tvoid *reg;\n\tu8 shift;\n};\n\nstruct clk_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tconst u32 *table;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_busy_mux {\n\tstruct clk_mux mux;\n\tconst struct clk_ops *mux_ops;\n\tvoid *reg;\n\tu8 shift;\n};\n\nstruct clk_cbf_8996_mux {\n\tu32 reg;\n\tstruct notifier_block nb;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_rate_request;\n\nstruct clk_duty;\n\nstruct clk_ops {\n\tint (*prepare)(struct clk_hw *);\n\tvoid (*unprepare)(struct clk_hw *);\n\tint (*is_prepared)(struct clk_hw *);\n\tvoid (*unprepare_unused)(struct clk_hw *);\n\tint (*enable)(struct clk_hw *);\n\tvoid (*disable)(struct clk_hw *);\n\tint (*is_enabled)(struct clk_hw *);\n\tvoid (*disable_unused)(struct clk_hw *);\n\tint (*save_context)(struct clk_hw *);\n\tvoid (*restore_context)(struct clk_hw *);\n\tlong unsigned int (*recalc_rate)(struct clk_hw *, long unsigned int);\n\tlong int (*round_rate)(struct clk_hw *, long unsigned int, long unsigned int *);\n\tint (*determine_rate)(struct clk_hw *, struct clk_rate_request *);\n\tint (*set_parent)(struct clk_hw *, u8);\n\tu8 (*get_parent)(struct clk_hw *);\n\tint (*set_rate)(struct clk_hw *, long unsigned int, long unsigned int);\n\tint (*set_rate_and_parent)(struct clk_hw *, long unsigned int, long unsigned int, u8);\n\tlong unsigned int (*recalc_accuracy)(struct clk_hw *, long unsigned int);\n\tint (*get_phase)(struct clk_hw *);\n\tint (*set_phase)(struct clk_hw *, int);\n\tint (*get_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*set_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*init)(struct clk_hw *);\n\tvoid (*terminate)(struct clk_hw *);\n\tvoid (*debug_init)(struct clk_hw *, struct dentry *);\n};\n\nstruct clk_composite {\n\tstruct clk_hw hw;\n\tstruct clk_ops ops;\n\tstruct clk_hw *mux_hw;\n\tstruct clk_hw *rate_hw;\n\tstruct clk_hw *gate_hw;\n\tconst struct clk_ops *mux_ops;\n\tconst struct clk_ops *rate_ops;\n\tconst struct clk_ops *gate_ops;\n};\n\nstruct clk_duty {\n\tunsigned int num;\n\tunsigned int den;\n};\n\nstruct clk_parent_map;\n\nstruct clk_core {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tstruct clk_hw *hw;\n\tstruct module *owner;\n\tstruct device *dev;\n\tstruct hlist_node rpm_node;\n\tstruct device_node *of_node;\n\tstruct clk_core *parent;\n\tstruct clk_parent_map *parents;\n\tu8 num_parents;\n\tu8 new_parent_index;\n\tlong unsigned int rate;\n\tlong unsigned int req_rate;\n\tlong unsigned int new_rate;\n\tstruct clk_core *new_parent;\n\tstruct clk_core *new_child;\n\tlong unsigned int flags;\n\tbool orphan;\n\tbool rpm_enabled;\n\tunsigned int enable_count;\n\tunsigned int prepare_count;\n\tunsigned int protect_count;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int accuracy;\n\tint phase;\n\tstruct clk_duty duty;\n\tstruct hlist_head children;\n\tstruct hlist_node child_node;\n\tstruct hlist_node hashtable_node;\n\tstruct hlist_head clks;\n\tunsigned int notifier_count;\n\tstruct dentry *dentry;\n\tstruct hlist_node debug_node;\n\tstruct kref ref;\n};\n\nstruct clk_cpu {\n\tstruct clk_hw hw;\n\tstruct clk *div;\n\tstruct clk *mux;\n\tstruct clk *pll;\n\tstruct clk *step;\n};\n\nstruct clk_cpu_8996_pmux {\n\tu32 reg;\n\tstruct notifier_block nb;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_div_table {\n\tunsigned int val;\n\tunsigned int div;\n};\n\nstruct clk_divider_gate {\n\tstruct clk_divider divider;\n\tu32 cached_val;\n};\n\nstruct clk_double_div {\n\tstruct clk_hw hw;\n\tvoid *reg1;\n\tu8 shift1;\n\tvoid *reg2;\n\tu8 shift2;\n};\n\nstruct reset_simple_data {\n\tspinlock_t lock;\n\tvoid *membase;\n\tstruct reset_controller_dev rcdev;\n\tbool active_low;\n\tbool status_active_low;\n\tunsigned int reset_us;\n};\n\nstruct clk_dvp {\n\tstruct clk_hw_onecell_data *data;\n\tstruct reset_simple_data reset;\n};\n\nstruct mn {\n\tu8 mnctr_en_bit;\n\tu8 mnctr_reset_bit;\n\tu8 mnctr_mode_shift;\n\tu8 n_val_shift;\n\tu8 m_val_shift;\n\tu8 width;\n\tbool reset_in_cc;\n};\n\nstruct pre_div {\n\tu8 pre_div_shift;\n\tu8 pre_div_width;\n};\n\nstruct parent_map;\n\nstruct src_sel {\n\tu8 src_sel_shift;\n\tconst struct parent_map *parent_map;\n};\n\nstruct freq_tbl;\n\nstruct clk_dyn_rcg {\n\tu32 ns_reg[2];\n\tu32 md_reg[2];\n\tu32 bank_reg;\n\tu8 mux_sel_bit;\n\tstruct mn mn[2];\n\tstruct pre_div p[2];\n\tstruct src_sel s[2];\n\tconst struct freq_tbl *freq_tbl;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_factor_table {\n\tunsigned int val;\n\tunsigned int mul;\n\tunsigned int div;\n};\n\nstruct clk_fixed_factor {\n\tstruct clk_hw hw;\n\tunsigned int mult;\n\tunsigned int div;\n\tlong unsigned int acc;\n\tunsigned int flags;\n};\n\nstruct clk_fixed_rate {\n\tstruct clk_hw hw;\n\tlong unsigned int fixed_rate;\n\tlong unsigned int fixed_accuracy;\n\tlong unsigned int flags;\n};\n\nstruct clk_fixup_div {\n\tstruct clk_divider divider;\n\tconst struct clk_ops *ops;\n\tvoid (*fixup)(u32 *);\n};\n\nstruct clk_fixup_mux {\n\tstruct clk_mux mux;\n\tconst struct clk_ops *ops;\n\tvoid (*fixup)(u32 *);\n};\n\nstruct clk_frac_pll {\n\tstruct clk_hw hw;\n\tvoid *base;\n};\n\nstruct imx_fracn_gppll_rate_table;\n\nstruct clk_fracn_gppll {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tconst struct imx_fracn_gppll_rate_table *rate_table;\n\tint rate_count;\n\tu32 flags;\n};\n\nstruct clk_fractional_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 mshift;\n\tu8 mwidth;\n\tu8 nshift;\n\tu8 nwidth;\n\tu8 flags;\n\tvoid (*approximation)(struct clk_hw *, long unsigned int, long unsigned int *, long unsigned int *, long unsigned int *);\n\tspinlock_t *lock;\n};\n\nstruct clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_gate2 {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tu8 cgr_val;\n\tu8 cgr_mask;\n\tu8 flags;\n\tspinlock_t *lock;\n\tunsigned int *share_count;\n};\n\nstruct clk_gate_exclusive {\n\tstruct clk_gate gate;\n\tu32 exclusive_mask;\n};\n\nstruct clk_gpio {\n\tstruct clk_hw hw;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct clk_gated_fixed {\n\tstruct clk_gpio clk_gpio;\n\tstruct regulator *supply;\n\tlong unsigned int rate;\n};\n\nstruct clk_get_info {\n\t__le16 id;\n\t__le16 flags;\n\t__le32 min_rate;\n\t__le32 max_rate;\n\tu8 name[20];\n};\n\nstruct clk_gpr_scu {\n\tstruct clk_hw hw;\n\tu16 rsrc_id;\n\tu8 gpr_id;\n\tu8 flags;\n\tbool gate_invert;\n};\n\nstruct hfpll_data;\n\nstruct clk_hfpll {\n\tconst struct hfpll_data *d;\n\tint init_done;\n\tstruct clk_regmap clkr;\n\tspinlock_t lock;\n};\n\nstruct clk_hisi_phase {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu32 *phase_degrees;\n\tu32 *phase_regvals;\n\tu8 phase_num;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_hsio_pll {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n};\n\nstruct rzg2l_cpg_priv;\n\nstruct clk_hw_data {\n\tstruct clk_hw hw;\n\tu32 conf;\n\tu32 sconf;\n\tstruct rzg2l_cpg_priv *priv;\n};\n\nstruct clk_parent_data;\n\nstruct clk_imx8_acm_sel {\n\tconst char *name;\n\tint clkid;\n\tconst struct clk_parent_data *parents;\n\tint num_parents;\n\tu32 reg;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct clk_imx8mp_audiomix_priv {\n\tvoid *base;\n\tu32 regs_save[16];\n\tstruct clk_hw_onecell_data clk_data;\n};\n\nstruct clk_parent_data {\n\tconst struct clk_hw *hw;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_imx8mp_audiomix_sel {\n\tconst char *name;\n\tint clkid;\n\tconst struct clk_parent_data parent;\n\tconst struct clk_parent_data *parents;\n\tint num_parents;\n\tu16 reg;\n\tu8 width;\n\tu8 shift;\n};\n\nstruct clk_imx8ulp_sim_lpav_data {\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tstruct clk_hw_onecell_data clk_data;\n};\n\nstruct clk_imx8ulp_sim_lpav_gate {\n\tconst char *name;\n\tint id;\n\tconst struct clk_parent_data parent;\n\tu8 bit;\n};\n\nstruct device_link;\n\nstruct clk_imx_acm_pm_domains {\n\tstruct device **pd_dev;\n\tstruct device_link **pd_dev_link;\n\tint num_domains;\n};\n\nstruct clk_init_data {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tconst char * const *parent_names;\n\tconst struct clk_parent_data *parent_data;\n\tconst struct clk_hw **parent_hws;\n\tu8 num_parents;\n\tlong unsigned int flags;\n};\n\nstruct clk_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct clk *clk;\n\tstruct clk_hw *clk_hw;\n};\n\nstruct clk_lookup_alloc {\n\tstruct clk_lookup cl;\n\tchar dev_id[24];\n\tchar con_id[16];\n};\n\nstruct clk_lpcg_scu {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tbool hw_gate;\n\tu32 state;\n};\n\nstruct clk_mem_branch {\n\tu32 mem_enable_reg;\n\tu32 mem_ack_reg;\n\tu32 mem_enable_ack_mask;\n\tu32 mem_enable_mask;\n\tbool mem_enable_invert;\n\tstruct clk_branch branch;\n};\n\nstruct clk_multiplier {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct srcu_node;\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[3];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct clk_notifier {\n\tstruct clk *clk;\n\tstruct srcu_notifier_head notifier_head;\n\tstruct list_head node;\n};\n\nstruct clk_notifier_data {\n\tstruct clk *clk;\n\tlong unsigned int old_rate;\n\tlong unsigned int new_rate;\n};\n\nstruct clk_notifier_devres {\n\tstruct clk *clk;\n\tstruct notifier_block *nb;\n};\n\nstruct clk_onecell_data {\n\tstruct clk **clks;\n\tunsigned int clk_num;\n};\n\nstruct clk_parent_map {\n\tconst struct clk_hw *hw;\n\tstruct clk_core *core;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_periph_data {\n\tconst char *name;\n\tconst char * const *parent_names;\n\tint num_parents;\n\tstruct clk_hw *mux_hw;\n\tstruct clk_hw *rate_hw;\n\tstruct clk_hw *gate_hw;\n\tstruct clk_hw *muxrate_hw;\n\tbool is_double_div;\n};\n\nstruct clk_periph_driver_data {\n\tstruct clk_hw_onecell_data *hw_data;\n\tspinlock_t lock;\n\tvoid *reg;\n\tu32 tbg_sel;\n\tu32 div_sel0;\n\tu32 div_sel1;\n\tu32 div_sel2;\n\tu32 clk_sel;\n\tu32 clk_dis;\n};\n\nstruct clk_pfd {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 idx;\n};\n\nstruct clk_pfdv2 {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 gate_bit;\n\tu8 vld_bit;\n\tu8 frac_off;\n};\n\nstruct pll_freq_tbl;\n\nstruct clk_pll {\n\tu32 l_reg;\n\tu32 m_reg;\n\tu32 n_reg;\n\tu32 config_reg;\n\tu32 mode_reg;\n\tu32 status_reg;\n\tu8 status_bit;\n\tu8 post_div_width;\n\tu8 post_div_shift;\n\tconst struct pll_freq_tbl *freq_tbl;\n\tstruct clk_regmap clkr;\n};\n\nstruct imx_pll14xx_rate_table;\n\nstruct clk_pll14xx {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tenum imx_pll14xx_type type;\n\tconst struct imx_pll14xx_rate_table *rate_table;\n\tint rate_count;\n};\n\nstruct clk_pll_table {\n\tunsigned int val;\n\tlong unsigned int rate;\n};\n\nstruct clk_plldig {\n\tstruct clk_hw hw;\n\tvoid *regs;\n\tunsigned int vco_freq;\n};\n\nstruct clk_pllv1 {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tenum imx_pllv1_type type;\n};\n\nstruct clk_pllv2 {\n\tstruct clk_hw hw;\n\tvoid *base;\n};\n\nstruct clk_pllv3 {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu32 power_bit;\n\tbool powerup_set;\n\tu32 div_mask;\n\tu32 div_shift;\n\tlong unsigned int ref_clock;\n\tu32 num_offset;\n\tu32 denom_offset;\n};\n\nstruct clk_pllv3_vf610_mf {\n\tu32 mfi;\n\tu32 mfn;\n\tu32 mfd;\n};\n\nstruct clk_pllv4 {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tu32 cfg_offset;\n\tu32 num_offset;\n\tu32 denom_offset;\n\tbool use_mult_range;\n};\n\nstruct clk_pm_cpu {\n\tstruct clk_hw hw;\n\tvoid *reg_mux;\n\tu8 shift_mux;\n\tu32 mask_mux;\n\tvoid *reg_div;\n\tu8 shift_div;\n\tstruct regmap *nb_pm_base;\n\tlong unsigned int l1_expiration;\n};\n\nstruct pwm_state {\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tbool usage_power;\n};\n\nstruct pwm_device;\n\nstruct clk_pwm {\n\tstruct clk_hw hw;\n\tstruct pwm_device *pwm;\n\tstruct pwm_state state;\n\tu32 fixed_rate;\n};\n\nstruct clk_rate_request {\n\tstruct clk_core *core;\n\tlong unsigned int rate;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int best_parent_rate;\n\tstruct clk_hw *best_parent_hw;\n};\n\nstruct clk_rcg {\n\tu32 ns_reg;\n\tu32 md_reg;\n\tstruct mn mn;\n\tstruct pre_div p;\n\tstruct src_sel s;\n\tconst struct freq_tbl *freq_tbl;\n\tstruct clk_regmap clkr;\n};\n\nstruct freq_multi_tbl;\n\nstruct clk_rcg2 {\n\tu32 cmd_rcgr;\n\tu8 mnd_width;\n\tu8 hid_width;\n\tu8 safe_src_index;\n\tconst struct parent_map *parent_map;\n\tunion {\n\t\tconst struct freq_tbl *freq_tbl;\n\t\tconst struct freq_multi_tbl *freq_multi_tbl;\n\t};\n\tstruct clk_regmap clkr;\n\tu8 cfg_off;\n\tu32 parked_cfg;\n\tbool hw_clk_ctrl;\n};\n\nstruct clk_rcg2_gfx3d {\n\tu8 div;\n\tstruct clk_rcg2 rcg;\n\tstruct clk_hw **hws;\n};\n\nstruct clk_rcg_dfs_data {\n\tstruct clk_rcg2 *rcg;\n\tstruct clk_init_data *init;\n};\n\nstruct clk_regmap___2 {\n\tstruct clk_hw hw;\n\tstruct regmap *map;\n\tvoid *data;\n};\n\nstruct clk_regmap_div {\n\tu32 reg;\n\tu32 shift;\n\tu32 width;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_regmap_div_data {\n\tunsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tconst struct clk_div_table *table;\n};\n\nstruct clk_regmap_gate_data {\n\tunsigned int offset;\n\tu8 bit_idx;\n\tu8 flags;\n};\n\nstruct clk_regmap_mux {\n\tu32 reg;\n\tu32 shift;\n\tu32 width;\n\tconst struct parent_map *parent_map;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_regmap_mux_data {\n\tunsigned int offset;\n\tu32 *table;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n};\n\nstruct clk_regmap_mux_div {\n\tu32 reg_offset;\n\tu32 hid_width;\n\tu32 hid_shift;\n\tu32 src_width;\n\tu32 src_shift;\n\tu32 div;\n\tu32 src;\n\tconst u32 *parent_map;\n\tstruct clk_regmap clkr;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_nb;\n};\n\nstruct clk_regmap_phy_mux {\n\tu32 reg;\n\tstruct clk_regmap clkr;\n};\n\nstruct clk_rk3399_inits {\n\tvoid (*inits)(struct device_node *);\n};\n\nstruct clk_rk3562_inits {\n\tvoid (*inits)(struct device_node *);\n};\n\nstruct clk_rk3568_inits {\n\tvoid (*inits)(struct device_node *);\n};\n\nstruct clk_rk3576_inits {\n\tvoid (*inits)(struct device_node *);\n};\n\nstruct clk_rpmh {\n\tstruct clk_hw hw;\n\tconst char *res_name;\n\tu8 div;\n\tu32 res_addr;\n\tu32 res_on_val;\n\tu32 state;\n\tu32 aggr_state;\n\tu32 last_sent_aggr_state;\n\tu32 valid_state_mask;\n\tu32 unit;\n\tstruct device *dev;\n\tstruct clk_rpmh *peer;\n};\n\nstruct clk_rpmh_desc {\n\tstruct clk_hw **clks;\n\tsize_t num_clks;\n\tbool clka_optional;\n};\n\nstruct clk_rv1126b_inits {\n\tvoid (*inits)(struct device_node *);\n};\n\nstruct clk_scu {\n\tstruct clk_hw hw;\n\tu16 rsrc_id;\n\tu8 clk_type;\n\tstruct clk_hw *parent;\n\tu8 parent_index;\n\tbool is_enabled;\n\tu32 rate;\n};\n\nstruct clk_set_value {\n\t__le16 id;\n\t__le16 reserved;\n\t__le32 rate;\n};\n\nstruct clk_smd_rpm {\n\tconst int rpm_res_type;\n\tconst int rpm_key;\n\tconst int rpm_clk_id;\n\tconst bool active_only;\n\tbool enabled;\n\tbool branch;\n\tstruct clk_smd_rpm *peer;\n\tstruct clk_hw hw;\n\tlong unsigned int rate;\n};\n\nstruct clk_smd_rpm_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct clk_sscg_pll_setup {\n\tint divr1;\n\tint divf1;\n\tint divr2;\n\tint divf2;\n\tint divq;\n\tint bypass;\n\tuint64_t vco1;\n\tuint64_t vco2;\n\tuint64_t fout;\n\tuint64_t ref;\n\tuint64_t ref_div1;\n\tuint64_t ref_div2;\n\tuint64_t fout_request;\n\tint fout_error;\n};\n\nstruct clk_sscg_pll {\n\tstruct clk_hw hw;\n\tconst struct clk_ops ops;\n\tvoid *base;\n\tstruct clk_sscg_pll_setup setup;\n\tu8 parent;\n\tu8 bypass1;\n\tu8 bypass2;\n};\n\nstruct stm32_gate_cfg;\n\nstruct stm32_mux_cfg;\n\nstruct stm32_div_cfg;\n\nstruct clk_stm32_clock_data {\n\tu16 *gate_cpt;\n\tconst struct stm32_gate_cfg *gates;\n\tconst struct stm32_mux_cfg *muxes;\n\tconst struct stm32_div_cfg *dividers;\n\tstruct clk_hw * (*is_multi_mux)(struct clk_hw *);\n};\n\nstruct clk_stm32_composite {\n\tu16 gate_id;\n\tu16 mux_id;\n\tu16 div_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct clk_stm32_div {\n\tu16 div_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct clk_stm32_gate {\n\tu16 gate_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct clk_stm32_mux {\n\tu16 mux_id;\n\tstruct clk_hw hw;\n\tvoid *base;\n\tstruct clk_stm32_clock_data *clock_data;\n\tspinlock_t *lock;\n};\n\nstruct stm32_reset_cfg;\n\nstruct clk_stm32_reset_data {\n\tconst struct reset_control_ops *ops;\n\tconst struct stm32_reset_cfg **reset_lines;\n\tunsigned int nr_lines;\n\tu32 clear_offset;\n};\n\nstruct clkgate_separated {\n\tstruct clk_hw hw;\n\tvoid *enable;\n\tu8 bit_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct stm32_rcc_match_data;\n\nstruct clock_config {\n\tlong unsigned int id;\n\tint sec_id;\n\tvoid *clock_cfg;\n\tstruct clk_hw * (*func)(struct device *, const struct stm32_rcc_match_data *, void *, spinlock_t *, const struct clock_config *);\n};\n\nstruct clock_read_data {\n\tu64 epoch_ns;\n\tu64 epoch_cyc;\n\tu64 sched_clock_mask;\n\tu64 (*read_sched_clock)(void);\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct clock_data {\n\tseqcount_latch_t seq;\n\tstruct clock_read_data read_data[2];\n\tktime_t wrap_kt;\n\tlong unsigned int rate;\n\tu64 (*actual_read_sched_clock)(void);\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct scmi_clock_info;\n\nstruct scmi_protocol_handle;\n\nstruct clock_info {\n\tint num_clocks;\n\tint max_async_req;\n\tbool notify_rate_changed_cmd;\n\tbool notify_rate_change_requested_cmd;\n\tatomic_t cur_async_req;\n\tstruct scmi_clock_info *clk;\n\tint (*clock_config_set)(const struct scmi_protocol_handle *, u32, enum clk_state, enum scmi_clock_oem_config, u32, bool);\n\tint (*clock_config_get)(const struct scmi_protocol_handle *, u32, enum scmi_clock_oem_config, u32 *, bool *, u32 *, bool);\n};\n\nstruct clock_parent {\n\tchar name[50];\n\tint id;\n\tu32 flag;\n};\n\nstruct clock_provider {\n\tvoid (*clk_init_cb)(struct device_node *);\n\tstruct device_node *np;\n\tstruct list_head node;\n};\n\nstruct clock_topology {\n\tu32 type;\n\tu32 flag;\n\tu32 type_flag;\n\tu8 custom_type_flag;\n};\n\nstruct clockgen_muxinfo;\n\nstruct clockgen;\n\nstruct clockgen_chipinfo {\n\tconst char *compat;\n\tconst char *guts_compat;\n\tconst struct clockgen_muxinfo *cmux_groups[2];\n\tconst struct clockgen_muxinfo *hwaccel[5];\n\tvoid (*init_periph)(struct clockgen *);\n\tint cmux_to_group[9];\n\tu32 pll_mask;\n\tu32 flags;\n};\n\nstruct clockgen_pll_div {\n\tstruct clk *clk;\n\tchar name[32];\n};\n\nstruct clockgen_pll {\n\tstruct clockgen_pll_div div[32];\n};\n\nstruct clockgen {\n\tstruct device_node *node;\n\tvoid *regs;\n\tstruct clockgen_chipinfo info;\n\tstruct clk *sysclk;\n\tstruct clk *coreclk;\n\tstruct clockgen_pll pll[6];\n\tstruct clk *cmux[8];\n\tstruct clk *hwaccel[5];\n\tstruct clk *fman[2];\n\tstruct ccsr_guts *guts;\n};\n\nstruct clockgen_sourceinfo {\n\tu32 flags;\n\tint pll;\n\tint div;\n};\n\nstruct clockgen_muxinfo {\n\tstruct clockgen_sourceinfo clksel[16];\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clocksource_mmio {\n\tvoid *reg;\n\tstruct clocksource clksrc;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct l2cache_pmu;\n\nstruct cluster_pmu {\n\tstruct list_head next;\n\tstruct perf_event *events[9];\n\tstruct l2cache_pmu *l2cache_pmu;\n\tlong unsigned int used_counters[1];\n\tlong unsigned int used_groups[1];\n\tint irq;\n\tint cluster_id;\n\tint on_cpu;\n\tcpumask_t cluster_cpus;\n\tspinlock_t pmu_lock;\n};\n\nstruct cma_memrange {\n\tlong unsigned int base_pfn;\n\tlong unsigned int count;\n\tunion {\n\t\tlong unsigned int early_pfn;\n\t\tlong unsigned int *bitmap;\n\t};\n};\n\nstruct cma {\n\tlong unsigned int count;\n\tlong unsigned int available_count;\n\tunsigned int order_per_bit;\n\tspinlock_t lock;\n\tstruct mutex alloc_mutex;\n\tchar name[64];\n\tint nranges;\n\tstruct cma_memrange ranges[8];\n\tlong unsigned int flags;\n\tint nid;\n};\n\nstruct cma_init_memrange {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tstruct list_head list;\n};\n\nstruct cmd_bwmgr_int_calc_and_set_request {\n\tuint32_t client_id;\n\tuint32_t niso_bw;\n\tuint32_t iso_bw;\n\tuint32_t mc_floor;\n\tuint8_t floor_unit;\n} __attribute__((packed));\n\nstruct cmd_bwmgr_int_calc_and_set_response {\n\tuint64_t rate;\n};\n\nstruct cmd_bwmgr_int_cap_set_request {\n\tuint64_t rate;\n};\n\nstruct cmd_bwmgr_int_query_abi_request {\n\tuint32_t type;\n};\n\nstruct cmd_clk_disable_request {};\n\nstruct cmd_clk_enable_request {};\n\nstruct cmd_clk_get_all_info_request {};\n\nstruct cmd_clk_get_all_info_response {\n\tuint32_t flags;\n\tuint32_t parent;\n\tuint32_t parents[16];\n\tuint8_t num_parents;\n\tuint8_t name[40];\n} __attribute__((packed));\n\nstruct cmd_clk_get_fmax_at_vmin_request {};\n\nstruct cmd_clk_get_max_clk_id_request {};\n\nstruct cmd_clk_get_max_clk_id_response {\n\tuint32_t max_id;\n};\n\nstruct cmd_clk_get_parent_request {};\n\nstruct cmd_clk_get_parent_response {\n\tuint32_t parent_id;\n};\n\nstruct cmd_clk_get_possible_parent_request {\n\tuint8_t parent_idx;\n};\n\nstruct cmd_clk_get_rate_request {};\n\nstruct cmd_clk_get_rate_response {\n\tint64_t rate;\n};\n\nstruct cmd_clk_is_enabled_request {};\n\nstruct cmd_clk_is_enabled_response {\n\tint32_t state;\n};\n\nstruct cmd_clk_num_possible_parents_request {};\n\nstruct cmd_clk_possible_parents_request {};\n\nstruct cmd_clk_properties_request {};\n\nstruct cmd_clk_round_rate_request {\n\tint32_t unused;\n\tint64_t rate;\n} __attribute__((packed));\n\nstruct cmd_clk_round_rate_response {\n\tint64_t rate;\n};\n\nstruct cmd_clk_set_parent_request {\n\tuint32_t parent_id;\n};\n\nstruct cmd_clk_set_parent_response {\n\tuint32_t parent_id;\n};\n\nstruct cmd_clk_set_rate_request {\n\tint32_t unused;\n\tint64_t rate;\n} __attribute__((packed));\n\nstruct cmd_clk_set_rate_response {\n\tint64_t rate;\n};\n\nstruct rsc_hdr {\n\t__le16 slv_id;\n\t__le16 header_offset;\n\t__le16 data_offset;\n\t__le16 cnt;\n\t__le16 version;\n\t__le16 reserved[3];\n};\n\nstruct cmd_db_header {\n\t__le32 version;\n\tu8 magic[4];\n\tstruct rsc_hdr header[8];\n\t__le32 checksum;\n\t__le32 reserved;\n\tu8 data[0];\n};\n\nstruct cmd_debug_fclose_request {\n\tuint32_t fd;\n};\n\nstruct cmd_debug_fopen_request {\n\tchar name[116];\n};\n\nstruct cmd_debug_fopen_response {\n\tuint32_t fd;\n\tuint32_t datalen;\n};\n\nstruct cmd_debug_fread_request {\n\tuint32_t fd;\n};\n\nstruct cmd_debug_fread_response {\n\tuint32_t readlen;\n\tchar data[116];\n};\n\nstruct cmd_debug_fwrite_request {\n\tuint32_t fd;\n\tuint32_t datalen;\n\tchar data[108];\n};\n\nstruct cmd_debugfs_dumpdir_request {\n\tuint32_t dataaddr;\n\tuint32_t datalen;\n};\n\nstruct cmd_debugfs_dumpdir_response {\n\tuint32_t reserved;\n\tuint32_t nbytes;\n};\n\nstruct cmd_debugfs_fileop_request {\n\tuint32_t fnameaddr;\n\tuint32_t fnamelen;\n\tuint32_t dataaddr;\n\tuint32_t datalen;\n};\n\nstruct cmd_debugfs_fileop_response {\n\tuint32_t reserved;\n\tuint32_t nbytes;\n};\n\nstruct cmd_i2c_xfer_request {\n\tuint32_t bus_id;\n\tuint32_t data_size;\n\tuint8_t data_buf[108];\n};\n\nstruct cmd_i2c_xfer_response {\n\tuint32_t data_size;\n\tuint8_t data_buf[116];\n};\n\nstruct cmd_pg_get_max_id_response {\n\tuint32_t max_id;\n};\n\nstruct cmd_pg_get_name_response {\n\tuint8_t name[40];\n};\n\nstruct cmd_pg_get_state_response {\n\tuint32_t state;\n};\n\nstruct cmd_pg_query_abi_request {\n\tuint32_t type;\n};\n\nstruct cmd_pg_set_state_request {\n\tuint32_t state;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmp_data {\n\tstruct task_struct *thr;\n\tstruct crypto_acomp *cc;\n\tstruct acomp_req *cr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct cn10k_rng {\n\tvoid *reg_base;\n\tstruct hwrng ops;\n\tstruct pci_dev *pdev;\n\tbool extended_trng_regs;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct collapse_control {\n\tbool is_khugepaged;\n\tu32 node_load[16];\n\tnodemask_t alloc_nmask;\n};\n\nstruct combiner_reg {\n\tvoid *addr;\n\tlong unsigned int enabled;\n};\n\nstruct combiner {\n\tstruct irq_domain *domain;\n\tint parent_irq;\n\tu32 nirqs;\n\tu32 nregs;\n\tstruct combiner_reg regs[0];\n};\n\nstruct command {\n\t__le16 id;\n\t__le16 lcid;\n\t__le32 count;\n\t__le32 size;\n\t__le32 liid;\n};\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n};\n\nstruct common {\n\tu8 verb;\n\tu8 reserved[63];\n};\n\nstruct lsm_network_audit;\n\nstruct lsm_ioctlop_audit;\n\nstruct lsm_ibpkey_audit;\n\nstruct lsm_ibendport_audit;\n\nstruct common_audit_data {\n\tchar type;\n\tunion {\n\t\tstruct path path;\n\t\tstruct dentry *dentry;\n\t\tstruct inode *inode;\n\t\tstruct lsm_network_audit *net;\n\t\tint cap;\n\t\tint ipc_id;\n\t\tstruct task_struct *tsk;\n\t\tstruct {\n\t\t\tkey_serial_t key;\n\t\t\tchar *key_desc;\n\t\t} key_struct;\n\t\tchar *kmod_name;\n\t\tstruct lsm_ioctlop_audit *op;\n\t\tstruct file *file;\n\t\tstruct lsm_ibpkey_audit *ibpkey;\n\t\tstruct lsm_ibendport_audit *ibendport;\n\t\tint reason;\n\t\tconst char *anonclass;\n\t\tu16 nlmsg_type;\n\t} u;\n\tunion {};\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[11];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_user_vfp {\n\tcompat_u64 fpregs[32];\n\tcompat_ulong_t fpscr;\n};\n\nstruct compat_user_vfp_exc {\n\tcompat_ulong_t fpexc;\n\tcompat_ulong_t fpinst;\n\tcompat_ulong_t fpinst2;\n};\n\nstruct compat_vfp_sigframe {\n\tcompat_ulong_t magic;\n\tcompat_ulong_t size;\n\tstruct compat_user_vfp ufp;\n\tstruct compat_user_vfp_exc ufp_exc;\n};\n\nstruct compat_aux_sigframe {\n\tstruct compat_vfp_sigframe vfp;\n\tlong unsigned int end_magic;\n};\n\nstruct compat_blkpg_ioctl_arg {\n\tcompat_int_t op;\n\tcompat_int_t flags;\n\tcompat_int_t datalen;\n\tcompat_caddr_t data;\n};\n\nstruct compat_cdrom_generic_command {\n\tunsigned char cmd[12];\n\tcompat_caddr_t buffer;\n\tcompat_uint_t buflen;\n\tcompat_int_t stat;\n\tcompat_caddr_t sense;\n\tunsigned char data_direction;\n\tunsigned char pad[3];\n\tcompat_int_t quiet;\n\tcompat_int_t timeout;\n\tcompat_caddr_t unused;\n};\n\nstruct compat_cmsghdr {\n\tcompat_size_t cmsg_len;\n\tcompat_int_t cmsg_level;\n\tcompat_int_t cmsg_type;\n};\n\nstruct compat_console_font_op {\n\tcompat_uint_t op;\n\tcompat_uint_t flags;\n\tcompat_uint_t width;\n\tcompat_uint_t height;\n\tcompat_uint_t charcount;\n\tcompat_caddr_t data;\n};\n\nstruct compat_dirent {\n\tu32 d_ino;\n\tcompat_off_t d_off;\n\tu16 d_reclen;\n\tchar d_name[256];\n};\n\nstruct compat_elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tcompat_ulong_t pr_flag;\n\t__compat_uid_t pr_uid;\n\t__compat_gid_t pr_gid;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct compat_elf_siginfo {\n\tcompat_int_t si_signo;\n\tcompat_int_t si_code;\n\tcompat_int_t si_errno;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct compat_elf_prstatus_common {\n\tstruct compat_elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tcompat_ulong_t pr_sigpend;\n\tcompat_ulong_t pr_sighold;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tstruct old_timeval32 pr_utime;\n\tstruct old_timeval32 pr_stime;\n\tstruct old_timeval32 pr_cutime;\n\tstruct old_timeval32 pr_cstime;\n};\n\nstruct compat_elf_prstatus {\n\tstruct compat_elf_prstatus_common common;\n\tcompat_elf_gregset_t pr_reg;\n\tcompat_int_t pr_fpvalid;\n};\n\nstruct compat_ext4_new_group_input {\n\tu32 group;\n\tcompat_u64 block_bitmap;\n\tcompat_u64 inode_bitmap;\n\tcompat_u64 inode_table;\n\tu32 blocks_count;\n\tu16 reserved_blocks;\n\tu16 unused;\n};\n\nstruct compat_flock {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_off_t l_start;\n\tcompat_off_t l_len;\n\tcompat_pid_t l_pid;\n};\n\nstruct compat_flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_loff_t l_start;\n\tcompat_loff_t l_len;\n\tcompat_pid_t l_pid;\n};\n\nstruct compat_frame_tail {\n\tcompat_uptr_t fp;\n\tu32 sp;\n\tu32 lr;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct compat_linux_dirent;\n\nstruct compat_getdents_callback {\n\tstruct dir_context ctx;\n\tstruct compat_linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t} __attribute__((packed));\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n} __attribute__((packed));\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n} __attribute__((packed));\n\nstruct compat_hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tu32 start;\n};\n\nstruct compat_if_dqblk {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 dqb_bsoftlimit;\n\tcompat_u64 dqb_curspace;\n\tcompat_u64 dqb_ihardlimit;\n\tcompat_u64 dqb_isoftlimit;\n\tcompat_u64 dqb_curinodes;\n\tcompat_u64 dqb_btime;\n\tcompat_u64 dqb_itime;\n\tcompat_uint_t dqb_valid;\n};\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_ipc64_perm {\n\tcompat_key_t key;\n\t__compat_uid32_t uid;\n\t__compat_gid32_t gid;\n\t__compat_uid32_t cuid;\n\t__compat_gid32_t cgid;\n\tcompat_mode_t mode;\n\tunsigned char __pad1[2];\n\tcompat_ushort_t seq;\n\tcompat_ushort_t __pad2;\n\tcompat_ulong_t unused1;\n\tcompat_ulong_t unused2;\n};\n\nstruct compat_ipc_perm {\n\tkey_t key;\n\t__compat_uid_t uid;\n\t__compat_gid_t gid;\n\t__compat_uid_t cuid;\n\t__compat_gid_t cgid;\n\tcompat_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct compat_kexec_segment {\n\tcompat_uptr_t buf;\n\tcompat_size_t bufsz;\n\tcompat_ulong_t mem;\n\tcompat_size_t memsz;\n};\n\nstruct compat_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct compat_loop_info {\n\tcompat_int_t lo_number;\n\tcompat_dev_t lo_device;\n\tcompat_ulong_t lo_inode;\n\tcompat_dev_t lo_rdevice;\n\tcompat_int_t lo_offset;\n\tcompat_int_t lo_encrypt_type;\n\tcompat_int_t lo_encrypt_key_size;\n\tcompat_int_t lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tcompat_ulong_t lo_init[2];\n\tchar reserved[4];\n};\n\nstruct megasas_header {\n\tu8 cmd;\n\tu8 sense_len;\n\tu8 cmd_status;\n\tu8 scsi_status;\n\tu8 target_id;\n\tu8 lun;\n\tu8 cdb_len;\n\tu8 sge_count;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 timeout;\n\t__le32 data_xferlen;\n};\n\nstruct compat_megasas_iocpacket {\n\tu16 host_no;\n\tu16 __pad1;\n\tu32 sgl_off;\n\tu32 sge_count;\n\tu32 sense_off;\n\tu32 sense_len;\n\tunion {\n\t\tu8 raw[128];\n\t\tstruct megasas_header hdr;\n\t} frame;\n\tstruct compat_iovec sgl[16];\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_mq_attr {\n\tcompat_long_t mq_flags;\n\tcompat_long_t mq_maxmsg;\n\tcompat_long_t mq_msgsize;\n\tcompat_long_t mq_curmsgs;\n\tcompat_long_t __reserved[4];\n};\n\nstruct compat_msgbuf {\n\tcompat_long_t mtype;\n\tchar mtext[0];\n};\n\nstruct compat_msqid64_ds {\n\tstruct compat_ipc64_perm msg_perm;\n\tcompat_ulong_t msg_stime;\n\tcompat_ulong_t msg_stime_high;\n\tcompat_ulong_t msg_rtime;\n\tcompat_ulong_t msg_rtime_high;\n\tcompat_ulong_t msg_ctime;\n\tcompat_ulong_t msg_ctime_high;\n\tcompat_ulong_t msg_cbytes;\n\tcompat_ulong_t msg_qnum;\n\tcompat_ulong_t msg_qbytes;\n\tcompat_pid_t msg_lspid;\n\tcompat_pid_t msg_lrpid;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_msqid_ds {\n\tstruct compat_ipc_perm msg_perm;\n\tcompat_uptr_t msg_first;\n\tcompat_uptr_t msg_last;\n\told_time32_t msg_stime;\n\told_time32_t msg_rtime;\n\told_time32_t msg_ctime;\n\tcompat_ulong_t msg_lcbytes;\n\tcompat_ulong_t msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\tcompat_ipc_pid_t msg_lspid;\n\tcompat_ipc_pid_t msg_lrpid;\n};\n\nstruct compat_nfs_string {\n\tcompat_uint_t len;\n\tcompat_uptr_t data;\n};\n\nstruct compat_nfs4_mount_data_v1 {\n\tcompat_int_t version;\n\tcompat_int_t flags;\n\tcompat_int_t rsize;\n\tcompat_int_t wsize;\n\tcompat_int_t timeo;\n\tcompat_int_t retrans;\n\tcompat_int_t acregmin;\n\tcompat_int_t acregmax;\n\tcompat_int_t acdirmin;\n\tcompat_int_t acdirmax;\n\tstruct compat_nfs_string client_addr;\n\tstruct compat_nfs_string mnt_path;\n\tstruct compat_nfs_string hostname;\n\tcompat_uint_t host_addrlen;\n\tcompat_uptr_t host_addr;\n\tcompat_int_t proto;\n\tcompat_int_t auth_flavourlen;\n\tcompat_uptr_t auth_flavours;\n};\n\nstruct compat_old_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct compat_old_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_old_sigset_t sa_mask;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n};\n\nstruct compat_readdir_callback {\n\tstruct dir_context ctx;\n\tstruct compat_old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct compat_resume_swap_area {\n\tcompat_loff_t offset;\n\tu32 dev;\n} __attribute__((packed));\n\nstruct compat_rlimit {\n\tcompat_ulong_t rlim_cur;\n\tcompat_ulong_t rlim_max;\n};\n\nstruct compat_robust_list {\n\tcompat_uptr_t next;\n};\n\nstruct compat_robust_list_head {\n\tstruct compat_robust_list list;\n\tcompat_long_t futex_offset;\n\tcompat_uptr_t list_op_pending;\n};\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\nstruct compat_sigaltstack {\n\tcompat_uptr_t ss_sp;\n\tint ss_flags;\n\tcompat_size_t ss_size;\n};\n\ntypedef struct compat_sigaltstack compat_stack_t;\n\nstruct compat_sigcontext {\n\tcompat_ulong_t trap_no;\n\tcompat_ulong_t error_code;\n\tcompat_ulong_t oldmask;\n\tcompat_ulong_t arm_r0;\n\tcompat_ulong_t arm_r1;\n\tcompat_ulong_t arm_r2;\n\tcompat_ulong_t arm_r3;\n\tcompat_ulong_t arm_r4;\n\tcompat_ulong_t arm_r5;\n\tcompat_ulong_t arm_r6;\n\tcompat_ulong_t arm_r7;\n\tcompat_ulong_t arm_r8;\n\tcompat_ulong_t arm_r9;\n\tcompat_ulong_t arm_r10;\n\tcompat_ulong_t arm_fp;\n\tcompat_ulong_t arm_ip;\n\tcompat_ulong_t arm_sp;\n\tcompat_ulong_t arm_lr;\n\tcompat_ulong_t arm_pc;\n\tcompat_ulong_t arm_cpsr;\n\tcompat_ulong_t fault_address;\n};\n\nstruct compat_ucontext {\n\tcompat_ulong_t uc_flags;\n\tcompat_uptr_t uc_link;\n\tcompat_stack_t uc_stack;\n\tstruct compat_sigcontext uc_mcontext;\n\tcompat_sigset_t uc_sigmask;\n\tint __unused[30];\n\tcompat_ulong_t uc_regspace[128];\n};\n\nstruct compat_sigframe {\n\tstruct compat_ucontext uc;\n\tcompat_ulong_t retcode[2];\n};\n\nstruct compat_rt_sigframe {\n\tstruct compat_siginfo info;\n\tstruct compat_sigframe sig;\n};\n\nstruct compat_rtentry {\n\tu32 rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tu32 rt_pad3;\n\tunsigned char rt_tos;\n\tunsigned char rt_class;\n\tshort int rt_pad4;\n\tshort int rt_metric;\n\tcompat_uptr_t rt_dev;\n\tu32 rt_mtu;\n\tu32 rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct compat_rusage {\n\tstruct old_timeval32 ru_utime;\n\tstruct old_timeval32 ru_stime;\n\tcompat_long_t ru_maxrss;\n\tcompat_long_t ru_ixrss;\n\tcompat_long_t ru_idrss;\n\tcompat_long_t ru_isrss;\n\tcompat_long_t ru_minflt;\n\tcompat_long_t ru_majflt;\n\tcompat_long_t ru_nswap;\n\tcompat_long_t ru_inblock;\n\tcompat_long_t ru_oublock;\n\tcompat_long_t ru_msgsnd;\n\tcompat_long_t ru_msgrcv;\n\tcompat_long_t ru_nsignals;\n\tcompat_long_t ru_nvcsw;\n\tcompat_long_t ru_nivcsw;\n};\n\nstruct compat_sel_arg_struct {\n\tcompat_ulong_t n;\n\tcompat_uptr_t inp;\n\tcompat_uptr_t outp;\n\tcompat_uptr_t exp;\n\tcompat_uptr_t tvp;\n};\n\nstruct compat_semid64_ds {\n\tstruct compat_ipc64_perm sem_perm;\n\tcompat_ulong_t sem_otime;\n\tcompat_ulong_t sem_otime_high;\n\tcompat_ulong_t sem_ctime;\n\tcompat_ulong_t sem_ctime_high;\n\tcompat_ulong_t sem_nsems;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_semid_ds {\n\tstruct compat_ipc_perm sem_perm;\n\told_time32_t sem_otime;\n\told_time32_t sem_ctime;\n\tcompat_uptr_t sem_base;\n\tcompat_uptr_t sem_pending;\n\tcompat_uptr_t sem_pending_last;\n\tcompat_uptr_t undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct compat_sg_io_hdr {\n\tcompat_int_t interface_id;\n\tcompat_int_t dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tcompat_uint_t dxfer_len;\n\tcompat_uint_t dxferp;\n\tcompat_uptr_t cmdp;\n\tcompat_uptr_t sbp;\n\tcompat_uint_t timeout;\n\tcompat_uint_t flags;\n\tcompat_int_t pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tcompat_int_t resid;\n\tcompat_uint_t duration;\n\tcompat_uint_t info;\n};\n\nstruct compat_shm_info {\n\tcompat_int_t used_ids;\n\tcompat_ulong_t shm_tot;\n\tcompat_ulong_t shm_rss;\n\tcompat_ulong_t shm_swp;\n\tcompat_ulong_t swap_attempts;\n\tcompat_ulong_t swap_successes;\n};\n\nstruct compat_shmid64_ds {\n\tstruct compat_ipc64_perm shm_perm;\n\tcompat_size_t shm_segsz;\n\tcompat_ulong_t shm_atime;\n\tcompat_ulong_t shm_atime_high;\n\tcompat_ulong_t shm_dtime;\n\tcompat_ulong_t shm_dtime_high;\n\tcompat_ulong_t shm_ctime;\n\tcompat_ulong_t shm_ctime_high;\n\tcompat_pid_t shm_cpid;\n\tcompat_pid_t shm_lpid;\n\tcompat_ulong_t shm_nattch;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct compat_shmid_ds {\n\tstruct compat_ipc_perm shm_perm;\n\tint shm_segsz;\n\told_time32_t shm_atime;\n\told_time32_t shm_dtime;\n\told_time32_t shm_ctime;\n\tcompat_ipc_pid_t shm_cpid;\n\tcompat_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tcompat_uptr_t shm_unused2;\n\tcompat_uptr_t shm_unused3;\n};\n\nstruct compat_shminfo64 {\n\tcompat_ulong_t shmmax;\n\tcompat_ulong_t shmmin;\n\tcompat_ulong_t shmmni;\n\tcompat_ulong_t shmseg;\n\tcompat_ulong_t shmall;\n\tcompat_ulong_t __unused1;\n\tcompat_ulong_t __unused2;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n\tcompat_sigset_t sa_mask;\n};\n\nstruct compat_sigevent {\n\tcompat_sigval_t sigev_value;\n\tcompat_int_t sigev_signo;\n\tcompat_int_t sigev_notify;\n\tunion {\n\t\tcompat_int_t _pad[13];\n\t\tcompat_int_t _tid;\n\t\tstruct {\n\t\t\tcompat_uptr_t _function;\n\t\t\tcompat_uptr_t _attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\ntypedef struct compat_siginfo compat_siginfo_t;\n\nstruct compat_sigset_argpack {\n\tcompat_uptr_t p;\n\tcompat_size_t size;\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct compat_stat {\n\tcompat_dev_t st_dev;\n\tcompat_ino_t st_ino;\n\tcompat_mode_t st_mode;\n\tcompat_ushort_t st_nlink;\n\t__compat_uid16_t st_uid;\n\t__compat_gid16_t st_gid;\n\tcompat_dev_t st_rdev;\n\tcompat_off_t st_size;\n\tcompat_off_t st_blksize;\n\tcompat_off_t st_blocks;\n\told_time32_t st_atime;\n\tcompat_ulong_t st_atime_nsec;\n\told_time32_t st_mtime;\n\tcompat_ulong_t st_mtime_nsec;\n\told_time32_t st_ctime;\n\tcompat_ulong_t st_ctime_nsec;\n\tcompat_ulong_t __unused4[2];\n};\n\nstruct compat_statfs {\n\tint f_type;\n\tint f_bsize;\n\tint f_blocks;\n\tint f_bfree;\n\tint f_bavail;\n\tint f_files;\n\tint f_ffree;\n\tcompat_fsid_t f_fsid;\n\tint f_namelen;\n\tint f_frsize;\n\tint f_flags;\n\tint f_spare[4];\n};\n\nstruct compat_statfs64 {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_frsize;\n\t__u32 f_flags;\n\t__u32 f_spare[4];\n} __attribute__((packed));\n\nstruct compat_sysinfo {\n\ts32 uptime;\n\tu32 loads[3];\n\tu32 totalram;\n\tu32 freeram;\n\tu32 sharedram;\n\tu32 bufferram;\n\tu32 totalswap;\n\tu32 freeswap;\n\tu16 procs;\n\tu16 pad;\n\tu32 totalhigh;\n\tu32 freehigh;\n\tu32 mem_unit;\n\tchar _f[8];\n};\n\nstruct compat_tms {\n\tcompat_clock_t tms_utime;\n\tcompat_clock_t tms_stime;\n\tcompat_clock_t tms_cutime;\n\tcompat_clock_t tms_cstime;\n};\n\nstruct compat_unimapdesc {\n\tshort unsigned int entry_ct;\n\tcompat_caddr_t entries;\n};\n\nstruct compat_ustat {\n\tcompat_daddr_t f_tfree;\n\tcompat_ino_t f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\nstruct compound_hdr {\n\tint32_t status;\n\tuint32_t nops;\n\t__be32 *nops_p;\n\tuint32_t taglen;\n\tchar *tag;\n\tuint32_t replen;\n\tu32 minorversion;\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct config_group;\n\nstruct config_item_type;\n\nstruct config_item {\n\tchar *ci_name;\n\tchar ci_namebuf[20];\n\tstruct kref ci_kref;\n\tstruct list_head ci_entry;\n\tstruct config_item *ci_parent;\n\tstruct config_group *ci_group;\n\tconst struct config_item_type *ci_type;\n\tstruct dentry *ci_dentry;\n};\n\nstruct configfs_subsystem;\n\nstruct config_group {\n\tstruct config_item cg_item;\n\tstruct list_head cg_children;\n\tstruct configfs_subsystem *cg_subsys;\n\tstruct list_head default_groups;\n\tstruct list_head group_entry;\n};\n\nstruct configfs_item_operations;\n\nstruct configfs_group_operations;\n\nstruct configfs_attribute;\n\nstruct configfs_bin_attribute;\n\nstruct config_item_type {\n\tstruct module *ct_owner;\n\tconst struct configfs_item_operations *ct_item_ops;\n\tconst struct configfs_group_operations *ct_group_ops;\n\tstruct configfs_attribute **ct_attrs;\n\tstruct configfs_bin_attribute **ct_bin_attrs;\n};\n\nstruct deflate_state;\n\ntypedef struct deflate_state deflate_state;\n\ntypedef block_state (*compress_func)(deflate_state *, int);\n\nstruct config_s {\n\tush good_length;\n\tush max_lazy;\n\tush nice_length;\n\tush max_chain;\n\tcompress_func func;\n};\n\ntypedef struct config_s config;\n\nstruct configfs_attribute {\n\tconst char *ca_name;\n\tstruct module *ca_owner;\n\tumode_t ca_mode;\n\tssize_t (*show)(struct config_item *, char *);\n\tssize_t (*store)(struct config_item *, const char *, size_t);\n};\n\nstruct configfs_bin_attribute {\n\tstruct configfs_attribute cb_attr;\n\tvoid *cb_private;\n\tsize_t cb_max_size;\n\tssize_t (*read)(struct config_item *, void *, size_t);\n\tssize_t (*write)(struct config_item *, const void *, size_t);\n};\n\nstruct configfs_buffer {\n\tsize_t count;\n\tloff_t pos;\n\tchar *page;\n\tconst struct configfs_item_operations *ops;\n\tstruct mutex mutex;\n\tint needs_read_fill;\n\tbool read_in_progress;\n\tbool write_in_progress;\n\tchar *bin_buffer;\n\tint bin_buffer_size;\n\tint cb_max_size;\n\tstruct config_item *item;\n\tstruct module *owner;\n\tunion {\n\t\tstruct configfs_attribute *attr;\n\t\tstruct configfs_bin_attribute *bin_attr;\n\t};\n};\n\nstruct iattr;\n\nstruct configfs_fragment;\n\nstruct configfs_dirent {\n\tatomic_t s_count;\n\tint s_dependent_count;\n\tstruct list_head s_sibling;\n\tstruct list_head s_children;\n\tint s_links;\n\tvoid *s_element;\n\tint s_type;\n\tumode_t s_mode;\n\tstruct dentry *s_dentry;\n\tstruct iattr *s_iattr;\n\tstruct configfs_fragment *s_frag;\n};\n\nstruct configfs_fragment {\n\tatomic_t frag_count;\n\tstruct rw_semaphore frag_sem;\n\tbool frag_dead;\n};\n\nstruct configfs_group_operations {\n\tstruct config_item * (*make_item)(struct config_group *, const char *);\n\tstruct config_group * (*make_group)(struct config_group *, const char *);\n\tvoid (*disconnect_notify)(struct config_group *, struct config_item *);\n\tvoid (*drop_item)(struct config_group *, struct config_item *);\n\tbool (*is_visible)(struct config_item *, struct configfs_attribute *, int);\n\tbool (*is_bin_visible)(struct config_item *, struct configfs_bin_attribute *, int);\n};\n\nstruct configfs_item_operations {\n\tvoid (*release)(struct config_item *);\n\tint (*allow_link)(struct config_item *, struct config_item *);\n\tvoid (*drop_link)(struct config_item *, struct config_item *);\n};\n\nstruct configfs_subsystem {\n\tstruct config_group su_group;\n\tstruct mutex su_mutex;\n};\n\nstruct connect_timeout_data {\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct console;\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct;\n\nstruct console___2 {\n\tstruct list_head list;\n\tstruct hvc_struct *hvc;\n\tstruct winsize ws;\n\tu32 vtermno;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct log_header;\n\nstruct console_data {\n\tvoid *map_addr;\n\tstruct log_header *hdr;\n\tvoid *start_addr;\n\tvoid *end_addr;\n\tvoid *end_of_data;\n\tvoid *cur_ptr;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n};\n\nstruct context_tracking {\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct virtio_net_ctrl_hdr {\n\t__u8 class;\n\t__u8 cmd;\n};\n\nstruct control_buf {\n\tstruct virtio_net_ctrl_hdr hdr;\n\tvirtio_net_ctrl_ack status;\n};\n\nstruct cooling_spec {\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tunsigned int weight;\n};\n\nstruct copy_from_grant {\n\tconst struct blk_shadow *s;\n\tunsigned int grant_idx;\n\tunsigned int bvec_offset;\n\tchar *bvec_data;\n};\n\nstruct copy_subpage_arg {\n\tstruct folio *dst;\n\tstruct folio *src;\n\tstruct vm_area_struct *vma;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct fuse_corner;\n\nstruct corner {\n\tint min_uV;\n\tint max_uV;\n\tint uV;\n\tint last_uV;\n\tint quot_adjust;\n\tu32 save_ctl;\n\tu32 save_irq;\n\tlong unsigned int freq;\n\tstruct fuse_corner *fuse_corner;\n};\n\nstruct corner_data {\n\tunsigned int fuse_corner;\n\tlong unsigned int freq;\n};\n\nstruct regulator_coupler;\n\nstruct coupling_desc {\n\tstruct regulator_dev **coupled_rdevs;\n\tstruct regulator_coupler *coupler;\n\tint n_resolved;\n\tint n_coupled;\n};\n\nstruct cp110_gate_clk {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu8 bit_idx;\n};\n\nstruct cpc_reg {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct cpc_register_resource {\n\tacpi_object_type type;\n\tu64 *sys_mem_vaddr;\n\tunion {\n\t\tstruct cpc_reg reg;\n\t\tu64 int_value;\n\t} cpc_entry;\n};\n\nstruct cpc_desc {\n\tint num_entries;\n\tint version;\n\tint cpu_id;\n\tint write_cmd_status;\n\tint write_cmd_id;\n\traw_spinlock_t rmw_lock;\n\tstruct cpc_register_resource cpc_regs[21];\n\tstruct acpi_psd_package domain_info;\n\tstruct kobject kobj;\n};\n\nstruct cper_arm_ctx_info {\n\tu16 version;\n\tu16 type;\n\tu32 size;\n};\n\nstruct cper_arm_err_info {\n\tu8 version;\n\tu8 length;\n\tu16 validation_bits;\n\tu8 type;\n\tu16 multiple_error;\n\tu8 flags;\n\tu64 error_info;\n\tu64 virt_fault_addr;\n\tu64 physical_fault_addr;\n} __attribute__((packed));\n\nstruct cper_cxl_event_devid {\n\tu16 vendor_id;\n\tu16 device_id;\n\tu8 func_num;\n\tu8 device_num;\n\tu8 bus_num;\n\tu16 segment_num;\n\tu16 slot_num;\n\tu8 reserved;\n} __attribute__((packed));\n\nstruct cper_cxl_event_sn {\n\tu32 lower_dw;\n\tu32 upper_dw;\n};\n\nstruct cper_mem_err_compact {\n\tu64 validation_bits;\n\tu16 node;\n\tu16 card;\n\tu16 module;\n\tu16 bank;\n\tu16 device;\n\tu16 row;\n\tu16 column;\n\tu16 bit_pos;\n\tu64 requestor_id;\n\tu64 responder_id;\n\tu64 target_id;\n\tu16 rank;\n\tu16 mem_array_handle;\n\tu16 mem_dev_handle;\n\tu8 extended;\n} __attribute__((packed));\n\nstruct cper_record_header {\n\tchar signature[4];\n\tu16 revision;\n\tu32 signature_end;\n\tu16 section_count;\n\tu32 error_severity;\n\tu32 validation_bits;\n\tu32 record_length;\n\tu64 timestamp;\n\tguid_t platform_id;\n\tguid_t partition_id;\n\tguid_t creator_id;\n\tguid_t notification_type;\n\tu64 record_id;\n\tu32 flags;\n\tu64 persistence_information;\n\tu8 reserved[12];\n} __attribute__((packed));\n\nstruct cper_section_descriptor {\n\tu32 section_offset;\n\tu32 section_length;\n\tu16 revision;\n\tu8 validation_bits;\n\tu8 reserved;\n\tu32 flags;\n\tguid_t section_type;\n\tguid_t fru_id;\n\tu32 section_severity;\n\tu8 fru_text[20];\n};\n\nstruct cper_pstore_record {\n\tstruct cper_record_header hdr;\n\tstruct cper_section_descriptor sec_hdr;\n\tchar data[0];\n};\n\nstruct cper_sec_fw_err_rec_ref {\n\tu8 record_type;\n\tu8 revision;\n\tu8 reserved[6];\n\tu64 record_identifier;\n\tguid_t record_identifier_guid;\n};\n\nstruct cper_sec_mem_err {\n\tu64 validation_bits;\n\tu64 error_status;\n\tu64 physical_addr;\n\tu64 physical_addr_mask;\n\tu16 node;\n\tu16 card;\n\tu16 module;\n\tu16 bank;\n\tu16 device;\n\tu16 row;\n\tu16 column;\n\tu16 bit_pos;\n\tu64 requestor_id;\n\tu64 responder_id;\n\tu64 target_id;\n\tu8 error_type;\n\tu8 extended;\n\tu16 rank;\n\tu16 mem_array_handle;\n\tu16 mem_dev_handle;\n};\n\nstruct cper_sec_pcie {\n\tu64 validation_bits;\n\tu32 port_type;\n\tstruct {\n\t\tu8 minor;\n\t\tu8 major;\n\t\tu8 reserved[2];\n\t} version;\n\tu16 command;\n\tu16 status;\n\tu32 reserved;\n\tstruct {\n\t\tu16 vendor_id;\n\t\tu16 device_id;\n\t\tu8 class_code[3];\n\t\tu8 function;\n\t\tu8 device;\n\t\tu16 segment;\n\t\tu8 bus;\n\t\tu8 secondary_bus;\n\t\tu16 slot;\n\t\tu8 reserved;\n\t} __attribute__((packed)) device_id;\n\tstruct {\n\t\tu32 lower;\n\t\tu32 upper;\n\t} serial_number;\n\tstruct {\n\t\tu16 secondary_status;\n\t\tu16 control;\n\t} bridge;\n\tu8 capability[60];\n\tu8 aer_info[96];\n};\n\nstruct cper_sec_proc_arm {\n\tu32 validation_bits;\n\tu16 err_info_num;\n\tu16 context_info_num;\n\tu32 section_length;\n\tu8 affinity_level;\n\tu8 reserved[3];\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n};\n\nstruct cper_sec_proc_generic {\n\tu64 validation_bits;\n\tu8 proc_type;\n\tu8 proc_isa;\n\tu8 proc_error_type;\n\tu8 operation;\n\tu8 flags;\n\tu8 level;\n\tu16 reserved;\n\tu64 cpu_version;\n\tchar cpu_brand[128];\n\tu64 proc_id;\n\tu64 target_addr;\n\tu64 requestor_id;\n\tu64 responder_id;\n\tu64 ip;\n};\n\nstruct ddiv {\n\tunsigned int offset: 11;\n\tunsigned int shift: 4;\n\tunsigned int width: 4;\n\tunsigned int monbit: 5;\n\tunsigned int no_rmw: 1;\n};\n\nstruct rzv2h_pll_limits;\n\nstruct pll {\n\tunsigned int offset: 9;\n\tunsigned int has_clkn: 1;\n\tunsigned int instance: 2;\n\tconst struct rzv2h_pll_limits *limits;\n};\n\nstruct smuxed {\n\tunsigned int offset: 11;\n\tunsigned int shift: 4;\n\tunsigned int width: 4;\n};\n\nstruct fixed_mod_conf {\n\tu8 mon_index;\n\tu8 mon_bit;\n};\n\nstruct cpg_core_clk {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int parent;\n\tunsigned int div;\n\tunsigned int mult;\n\tunsigned int type;\n\tunion {\n\t\tunsigned int conf;\n\t\tstruct ddiv ddiv;\n\t\tstruct pll pll;\n\t\tstruct smuxed smux;\n\t\tstruct fixed_mod_conf fixed_mod;\n\t} cfg;\n\tconst struct clk_div_table *dtable;\n\tconst char * const *parent_names;\n\tunsigned int num_parents;\n\tu8 mux_flags;\n\tu32 flag;\n};\n\nstruct cpg_core_clk___2 {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int type;\n\tunsigned int parent;\n\tunsigned int div;\n\tunsigned int mult;\n\tunsigned int offset;\n\tunion {\n\t\tconst char * const *parent_names;\n\t\tconst struct clk_div_table *dtable;\n\t};\n\tu32 conf;\n\tu16 flag;\n\tu8 mux_flags;\n\tu8 num_parents;\n};\n\nstruct cpg_core_clk___3 {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int parent;\n\tunsigned int div;\n\tunsigned int mult;\n\tunsigned int type;\n\tunsigned int conf;\n\tunsigned int sconf;\n\tconst struct clk_div_table *dtable;\n\tconst u32 *mtable;\n\tconst long unsigned int invalid_rate;\n\tunion {\n\t\tconst long unsigned int max_rate;\n\t\tconst long unsigned int default_rate;\n\t};\n\tconst char * const *parent_names;\n\tnotifier_fn_t notifier;\n\tu32 flag;\n\tu32 mux_flags;\n\tint num_parents;\n};\n\nstruct cpg_mssr_clk_domain {\n\tstruct generic_pm_domain genpd;\n\tunsigned int num_core_pm_clks;\n\tunsigned int core_pm_clks[0];\n};\n\nstruct mssr_mod_clk;\n\nstruct cpg_mssr_pub;\n\nstruct cpg_mssr_info {\n\tconst struct cpg_core_clk___2 *early_core_clks;\n\tunsigned int num_early_core_clks;\n\tconst struct mssr_mod_clk *early_mod_clks;\n\tunsigned int num_early_mod_clks;\n\tconst struct cpg_core_clk___2 *core_clks;\n\tunsigned int num_core_clks;\n\tunsigned int last_dt_core_clk;\n\tunsigned int num_total_core_clks;\n\tenum clk_reg_layout reg_layout;\n\tconst struct mssr_mod_clk *mod_clks;\n\tunsigned int num_mod_clks;\n\tunsigned int num_hw_mod_clks;\n\tconst unsigned int *crit_mod_clks;\n\tunsigned int num_crit_mod_clks;\n\tconst unsigned int *core_pm_clks;\n\tunsigned int num_core_pm_clks;\n\tint (*init)(struct device *);\n\tstruct clk * (*cpg_clk_register)(struct device *, const struct cpg_core_clk___2 *, const struct cpg_mssr_info *, struct cpg_mssr_pub *);\n};\n\nstruct cpg_mssr_pub {\n\tvoid *base0;\n\tvoid *base1;\n\tstruct raw_notifier_head notifiers;\n\tspinlock_t rmw_lock;\n\tstruct clk **clks;\n};\n\nstruct cpg_mssr_priv {\n\tstruct cpg_mssr_pub pub;\n\tstruct reset_controller_dev rcdev;\n\tstruct device *dev;\n\tenum clk_reg_layout reg_layout;\n\tstruct device_node *np;\n\tunsigned int num_core_clks;\n\tunsigned int num_mod_clks;\n\tunsigned int last_dt_core_clk;\n\tconst u16 *status_regs;\n\tconst u16 *control_regs;\n\tconst u16 *reset_regs;\n\tconst u16 *reset_clear_regs;\n\tstruct {\n\t\tu32 mask;\n\t\tu32 val;\n\t} smstpcr_saved[30];\n\tunsigned int *reserved_ids;\n\tunsigned int num_reserved_ids;\n\tstruct clk *clks[0];\n};\n\nstruct cpg_pll_clk {\n\tstruct clk_hw hw;\n\tvoid *pllcr0_reg;\n\tvoid *pllcr1_reg;\n\tvoid *pllecr_reg;\n\tu32 pllecr_pllst_mask;\n};\n\nstruct cpg_pll_clk___2 {\n\tstruct clk_hw hw;\n\tvoid *pllcr_reg;\n\tvoid *pllecr_reg;\n\tunsigned int fixed_mult;\n\tu32 pllecr_pllst_mask;\n};\n\nstruct cpg_simple_notifier {\n\tstruct notifier_block nb;\n\tvoid *reg;\n\tu32 saved;\n};\n\nstruct cpg_z_clk {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tvoid *kick_reg;\n\tlong unsigned int max_rate;\n\tunsigned int fixed_div;\n\tu32 mask;\n};\n\nstruct cpi_cfg_msg {\n\tu8 msg;\n\tu8 vf_id;\n\tu8 rq_cnt;\n\tu8 cpi_alg;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cppc_perf_caps {\n\tu32 guaranteed_perf;\n\tu32 highest_perf;\n\tu32 nominal_perf;\n\tu32 lowest_perf;\n\tu32 lowest_nonlinear_perf;\n\tu32 lowest_freq;\n\tu32 nominal_freq;\n};\n\nstruct cppc_perf_ctrls {\n\tu32 max_perf;\n\tu32 min_perf;\n\tu32 desired_perf;\n\tu32 energy_perf;\n\tbool auto_sel;\n};\n\nstruct cppc_perf_fb_ctrs {\n\tu64 reference;\n\tu64 delivered;\n\tu64 reference_perf;\n\tu64 wraparound_time;\n};\n\nstruct cppc_cpudata {\n\tstruct cppc_perf_caps perf_caps;\n\tstruct cppc_perf_ctrls perf_ctrls;\n\tstruct cppc_perf_fb_ctrs perf_fb_ctrs;\n\tunsigned int shared_type;\n\tcpumask_var_t shared_cpu_map;\n};\n\nstruct pcc_mbox_chan;\n\nstruct cppc_pcc_data {\n\tstruct pcc_mbox_chan *pcc_channel;\n\tbool pcc_channel_acquired;\n\tunsigned int deadline_us;\n\tunsigned int pcc_mpar;\n\tunsigned int pcc_mrtt;\n\tunsigned int pcc_nominal;\n\tbool pending_pcc_write_cmd;\n\tbool platform_owns_pcc;\n\tunsigned int pcc_write_cnt;\n\tstruct rw_semaphore pcc_lock;\n\twait_queue_head_t pcc_write_wait_q;\n\tktime_t last_cmd_cmpl_time;\n\tktime_t last_mpar_reset;\n\tint mpar_count;\n\tint refcount;\n};\n\nstruct cppi5_desc_hdr_t {\n\tu32 pkt_info0;\n\tu32 pkt_info1;\n\tu32 pkt_info2;\n\tu32 src_dst_tag;\n};\n\nstruct cppi5_host_desc_t {\n\tstruct cppi5_desc_hdr_t hdr;\n\tu64 next_desc;\n\tu64 buf_ptr;\n\tu32 buf_info1;\n\tu32 org_buf_len;\n\tu64 org_buf_ptr;\n\tu32 epib[0];\n};\n\nstruct cppi5_tr_resp_t {\n\tu8 status;\n\tu8 _reserved;\n\tu8 cmd_id;\n\tu8 flags;\n};\n\nstruct cppi5_tr_type15_t {\n\tcppi5_tr_flags_t flags;\n\tu16 icnt0;\n\tu16 icnt1;\n\tu64 addr;\n\ts32 dim1;\n\tu16 icnt2;\n\tu16 icnt3;\n\ts32 dim2;\n\ts32 dim3;\n\tu32 _reserved;\n\ts32 ddim1;\n\tu64 daddr;\n\ts32 ddim2;\n\ts32 ddim3;\n\tu16 dicnt0;\n\tu16 dicnt1;\n\tu16 dicnt2;\n\tu16 dicnt3;\n};\n\nstruct cppi5_tr_type1_t {\n\tcppi5_tr_flags_t flags;\n\tu16 icnt0;\n\tu16 icnt1;\n\tu64 addr;\n\ts32 dim1;\n\tlong: 64;\n};\n\nstruct cpr_desc;\n\nstruct cpr_acc_desc {\n\tconst struct cpr_desc *cpr_desc;\n\tconst struct acc_desc *acc_desc;\n};\n\nstruct fuse_corner_data;\n\nstruct cpr_fuses {\n\tint init_voltage_step;\n\tint init_voltage_width;\n\tstruct fuse_corner_data *fuse_corner_data;\n};\n\nstruct cpr_desc {\n\tunsigned int num_fuse_corners;\n\tint min_diff_quot;\n\tint *step_quot;\n\tunsigned int timer_delay_us;\n\tunsigned int timer_cons_up;\n\tunsigned int timer_cons_down;\n\tunsigned int up_threshold;\n\tunsigned int down_threshold;\n\tunsigned int idle_clocks;\n\tunsigned int gcnt_us;\n\tunsigned int vdd_apc_step_up_limit;\n\tunsigned int vdd_apc_step_down_limit;\n\tunsigned int clamp_timer_interval;\n\tstruct cpr_fuses cpr_fuses;\n\tbool reduce_to_fuse_uV;\n\tbool reduce_to_corner_uV;\n};\n\nstruct cpr_fuse;\n\nstruct cpr_drv {\n\tunsigned int num_corners;\n\tunsigned int ref_clk_khz;\n\tstruct generic_pm_domain pd;\n\tstruct device *dev;\n\tstruct device *attached_cpu_dev;\n\tstruct mutex lock;\n\tvoid *base;\n\tstruct corner *corner;\n\tstruct regulator *vdd_apc;\n\tstruct clk *cpu_clk;\n\tstruct regmap *tcsr;\n\tbool loop_disabled;\n\tu32 gcnt;\n\tlong unsigned int flags;\n\tstruct fuse_corner *fuse_corners;\n\tstruct corner *corners;\n\tconst struct cpr_desc *desc;\n\tconst struct acc_desc *acc_desc;\n\tconst struct cpr_fuse *cpr_fuses;\n\tstruct dentry *debugfs;\n};\n\nstruct cpr_fuse {\n\tchar *ring_osc;\n\tchar *init_voltage;\n\tchar *quotient;\n\tchar *quotient_offset;\n};\n\nstruct cprman_plat_data {\n\tunsigned int soc;\n};\n\nstruct reg_field;\n\nstruct cpsw_ale_params {\n\tstruct device *dev;\n\tvoid *ale_regs;\n\tlong unsigned int ale_ageout;\n\tlong unsigned int ale_entries;\n\tlong unsigned int num_policers;\n\tlong unsigned int ale_ports;\n\tbool nu_switch_ale;\n\tconst struct reg_field *reg_fields;\n\tint num_fields;\n\tconst char *dev_id;\n\tlong unsigned int bus_freq;\n};\n\nstruct regmap_field;\n\nstruct cpsw_ale {\n\tstruct cpsw_ale_params params;\n\tstruct timer_list timer;\n\tstruct regmap *regmap;\n\tstruct regmap_field *fields[45];\n\tlong unsigned int ageout;\n\tu32 version;\n\tu32 features;\n\tu32 port_mask_bits;\n\tu32 port_num_bits;\n\tu32 vlan_field_bits;\n\tlong unsigned int *p0_untag_vid_mask;\n\tconst struct ale_entry_fld *vlan_entry_tbl;\n};\n\nstruct cpsw_ale_dev_id {\n\tconst char *dev_id;\n\tu32 features;\n\tu32 tbl_entries;\n\tconst struct reg_field *reg_fields;\n\tint num_fields;\n\tbool nu_switch_ale;\n\tconst struct ale_entry_fld *vlan_entry_tbl;\n};\n\nstruct cpsw_sl {\n\tstruct device *dev;\n\tvoid *sl_base;\n\tconst u16 *regs;\n\tu32 control_features;\n\tu32 idle_mask;\n};\n\nstruct cpsw_sl_dev_id {\n\tconst char *device_id;\n\tconst u16 *regs;\n\tconst u32 control_features;\n\tconst u32 regs_offset;\n\tconst u32 idle_mask;\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct cpu_clk_suspend_context {\n\tu32 clk_csite_src;\n};\n\nstruct cpu_clk_suspend_context___2 {\n\tu32 clk_csite_src;\n\tu32 cclkg_burst;\n\tu32 cclkg_divider;\n};\n\nstruct cpu_context {\n\tlong unsigned int x19;\n\tlong unsigned int x20;\n\tlong unsigned int x21;\n\tlong unsigned int x22;\n\tlong unsigned int x23;\n\tlong unsigned int x24;\n\tlong unsigned int x25;\n\tlong unsigned int x26;\n\tlong unsigned int x27;\n\tlong unsigned int x28;\n\tlong unsigned int fp;\n\tlong unsigned int sp;\n\tlong unsigned int pc;\n};\n\nstruct cpufreq_frequency_table;\n\nstruct cpu_data {\n\tstruct clk **pclk;\n\tstruct cpufreq_frequency_table *table;\n};\n\nstruct update_util_data {\n\tvoid (*func)(struct update_util_data *, u64, unsigned int);\n};\n\nstruct policy_dbs_info;\n\nstruct cpu_dbs_info {\n\tu64 prev_cpu_idle;\n\tu64 prev_update_time;\n\tu64 prev_cpu_nice;\n\tunsigned int prev_load;\n\tstruct update_util_data update_util;\n\tstruct policy_dbs_info *policy_dbs;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct cpu_feature {\n\t__u16 feature;\n};\n\nstruct cpu_fp_state {\n\tstruct user_fpsimd_state *st;\n\tvoid *sve_state;\n\tvoid *sme_state;\n\tu64 *svcr;\n\tu64 *fpmr;\n\tunsigned int sve_vl;\n\tunsigned int sme_vl;\n\tenum fp_type *fp_type;\n\tenum fp_type to_save;\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_lpi_count {\n\tatomic_t managed;\n\tatomic_t unmanaged;\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_operations {\n\tconst char *name;\n\tint (*cpu_init)(unsigned int);\n\tint (*cpu_prepare)(unsigned int);\n\tint (*cpu_boot)(unsigned int);\n\tvoid (*cpu_postboot)(void);\n\tbool (*cpu_can_disable)(unsigned int);\n\tint (*cpu_disable)(unsigned int);\n\tvoid (*cpu_die)(unsigned int);\n\tint (*cpu_kill)(unsigned int);\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_smt_info {\n\tunsigned int thread_num;\n\tint core_id;\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_suspend_ctx {\n\tu64 ctx_regs[14];\n\tu64 sp;\n\tlong: 64;\n};\n\nstruct cpu_sve_state {\n\t__u64 zcr_el1;\n\t__u32 fpsr;\n\t__u32 fpcr;\n\t__u8 sve_regs[0];\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_topology {\n\tint thread_id;\n\tint core_id;\n\tint cluster_id;\n\tint package_id;\n\tcpumask_t thread_sibling;\n\tcpumask_t core_sibling;\n\tcpumask_t cluster_sibling;\n\tcpumask_t llc_sibling;\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct cpu_vhint_data {\n\tuint32_t ref_clk_hz;\n\tuint16_t pdiv;\n\tuint16_t mdiv;\n\tuint16_t ndiv_max;\n\tuint16_t ndiv[80];\n\tuint16_t ndiv_min;\n\tuint16_t vfloor;\n\tuint16_t vceil;\n\tuint16_t vindex_mult;\n\tuint16_t vindex_div;\n\tuint16_t reserved[328];\n};\n\nstruct kernel_cpustat;\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tu64 *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct thermal_cooling_device_ops {\n\tint (*get_max_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*get_cur_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*set_cur_state)(struct thermal_cooling_device *, long unsigned int);\n\tint (*get_requested_power)(struct thermal_cooling_device *, u32 *);\n\tint (*state2power)(struct thermal_cooling_device *, long unsigned int, u32 *);\n\tint (*power2state)(struct thermal_cooling_device *, u32, long unsigned int *);\n};\n\nstruct cpufreq_policy;\n\nstruct cpufreq_cooling_device {\n\tu32 last_load;\n\tunsigned int cpufreq_state;\n\tunsigned int max_level;\n\tstruct em_perf_domain *em;\n\tstruct cpufreq_policy *policy;\n\tstruct thermal_cooling_device_ops cooling_ops;\n\tstruct freq_qos_request qos_req;\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_policy_data;\n\nstruct freq_attr;\n\nstruct cpufreq_driver {\n\tchar name[16];\n\tu16 flags;\n\tvoid *driver_data;\n\tint (*init)(struct cpufreq_policy *);\n\tint (*verify)(struct cpufreq_policy_data *);\n\tint (*setpolicy)(struct cpufreq_policy *);\n\tint (*target)(struct cpufreq_policy *, unsigned int, unsigned int);\n\tint (*target_index)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*fast_switch)(struct cpufreq_policy *, unsigned int);\n\tvoid (*adjust_perf)(unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get)(unsigned int);\n\tvoid (*update_limits)(struct cpufreq_policy *);\n\tint (*bios_limit)(int, unsigned int *);\n\tint (*online)(struct cpufreq_policy *);\n\tint (*offline)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n\tvoid (*ready)(struct cpufreq_policy *);\n\tstruct freq_attr **attr;\n\tbool boost_enabled;\n\tint (*set_boost)(struct cpufreq_policy *, int);\n\tvoid (*register_em)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_dt_platform_data {\n\tbool have_governor_per_policy;\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_freqs {\n\tstruct cpufreq_policy *policy;\n\tunsigned int old;\n\tunsigned int new;\n\tu8 flags;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tstruct list_head governor_list;\n\tstruct module *owner;\n\tu8 flags;\n};\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_read_t;\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_write_t;\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct cpufreq_stats;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tbool strict_target;\n\tbool efficiencies_available;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tbool boost_enabled;\n\tbool boost_supported;\n\tunsigned int cached_target_freq;\n\tunsigned int cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpufreq_policy_data {\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tstruct cpufreq_frequency_table *freq_table;\n\tunsigned int cpu;\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct cpufreq_stats {\n\tunsigned int total_trans;\n\tlong long unsigned int last_time;\n\tunsigned int max_state;\n\tunsigned int state_num;\n\tunsigned int last_index;\n\tu64 *time_in_state;\n\tunsigned int *freq_table;\n\tunsigned int *trans_table;\n\tunsigned int reset_pending;\n\tlong long unsigned int reset_time;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nstruct cpuidle_device;\n\nstruct cpuidle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_device *, char *);\n\tssize_t (*store)(struct cpuidle_device *, const char *, size_t);\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct cpuidle_device_kobj {\n\tstruct cpuidle_device *dev;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct cpuidle_driver_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_driver *, char *);\n\tssize_t (*store)(struct cpuidle_driver *, const char *, size_t);\n};\n\nstruct cpuidle_driver_kobj {\n\tstruct cpuidle_driver *drv;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_governor {\n\tchar name[16];\n\tstruct list_head governor_list;\n\tunsigned int rating;\n\tint (*enable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tvoid (*disable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tint (*select)(struct cpuidle_driver *, struct cpuidle_device *, bool *);\n\tvoid (*reflect)(struct cpuidle_device *, int);\n};\n\nstruct cpuidle_state_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_state *, struct cpuidle_state_usage *, char *);\n\tssize_t (*store)(struct cpuidle_state *, struct cpuidle_state_usage *, const char *, size_t);\n};\n\nstruct cpuidle_state_kobj {\n\tstruct cpuidle_state *state;\n\tstruct cpuidle_state_usage *state_usage;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n\tstruct cpuidle_device *device;\n};\n\nstruct cpuinfo_32bit {\n\tu32 reg_id_dfr0;\n\tu32 reg_id_dfr1;\n\tu32 reg_id_isar0;\n\tu32 reg_id_isar1;\n\tu32 reg_id_isar2;\n\tu32 reg_id_isar3;\n\tu32 reg_id_isar4;\n\tu32 reg_id_isar5;\n\tu32 reg_id_isar6;\n\tu32 reg_id_mmfr0;\n\tu32 reg_id_mmfr1;\n\tu32 reg_id_mmfr2;\n\tu32 reg_id_mmfr3;\n\tu32 reg_id_mmfr4;\n\tu32 reg_id_mmfr5;\n\tu32 reg_id_pfr0;\n\tu32 reg_id_pfr1;\n\tu32 reg_id_pfr2;\n\tu32 reg_mvfr0;\n\tu32 reg_mvfr1;\n\tu32 reg_mvfr2;\n};\n\nstruct cpuinfo_arm64 {\n\tstruct kobject kobj;\n\tu64 reg_ctr;\n\tu64 reg_cntfrq;\n\tu64 reg_dczid;\n\tu64 reg_midr;\n\tu64 reg_revidr;\n\tu64 reg_aidr;\n\tu64 reg_gmid;\n\tu64 reg_smidr;\n\tu64 reg_mpamidr;\n\tu64 reg_id_aa64dfr0;\n\tu64 reg_id_aa64dfr1;\n\tu64 reg_id_aa64isar0;\n\tu64 reg_id_aa64isar1;\n\tu64 reg_id_aa64isar2;\n\tu64 reg_id_aa64isar3;\n\tu64 reg_id_aa64mmfr0;\n\tu64 reg_id_aa64mmfr1;\n\tu64 reg_id_aa64mmfr2;\n\tu64 reg_id_aa64mmfr3;\n\tu64 reg_id_aa64mmfr4;\n\tu64 reg_id_aa64pfr0;\n\tu64 reg_id_aa64pfr1;\n\tu64 reg_id_aa64pfr2;\n\tu64 reg_id_aa64zfr0;\n\tu64 reg_id_aa64smfr0;\n\tu64 reg_id_aa64fpfr0;\n\tstruct cpuinfo_32bit aarch32;\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct cq_entry {\n\t__le64 command_desc_base_addr;\n\t__le16 response_upiu_length;\n\t__le16 response_upiu_offset;\n\t__le16 prd_table_length;\n\t__le16 prd_table_offset;\n\tu8 overall_status;\n\tu8 extended_error_code;\n\t__le16 reserved_1;\n\tu8 task_tag;\n\tu8 lun;\n\tu8 iid: 4;\n\tu8 ext_iid: 4;\n\tu8 reserved_2;\n\t__le32 reserved_3[2];\n};\n\nstruct cqhci_host_ops;\n\nstruct cqhci_slot;\n\nstruct cqhci_host {\n\tconst struct cqhci_host_ops *ops;\n\tvoid *mmio;\n\tstruct mmc_host *mmc;\n\tspinlock_t lock;\n\tunsigned int rca;\n\tbool dma64;\n\tint num_slots;\n\tint qcnt;\n\tu32 dcmd_slot;\n\tu32 caps;\n\tu32 quirks;\n\tbool enabled;\n\tbool halted;\n\tbool init_done;\n\tbool activated;\n\tbool waiting_for_idle;\n\tbool recovery_halt;\n\tsize_t desc_size;\n\tsize_t data_size;\n\tu8 *desc_base;\n\tu8 slot_sz;\n\tu8 task_desc_len;\n\tu8 link_desc_len;\n\tu8 *trans_desc_base;\n\tu8 trans_desc_len;\n\tdma_addr_t desc_dma_base;\n\tdma_addr_t trans_desc_dma_base;\n\tstruct completion halt_comp;\n\twait_queue_head_t wait_queue;\n\tstruct cqhci_slot *slot;\n};\n\nstruct cqhci_host_ops {\n\tvoid (*dumpregs)(struct mmc_host *);\n\tvoid (*write_l)(struct cqhci_host *, u32, int);\n\tu32 (*read_l)(struct cqhci_host *, int);\n\tvoid (*enable)(struct mmc_host *);\n\tvoid (*disable)(struct mmc_host *, bool);\n\tvoid (*update_dcmd_desc)(struct mmc_host *, struct mmc_request *, u64 *);\n\tvoid (*pre_enable)(struct mmc_host *);\n\tvoid (*post_disable)(struct mmc_host *);\n\tvoid (*set_tran_desc)(struct cqhci_host *, u8 **, dma_addr_t, int, bool, bool);\n};\n\nstruct cqhci_slot {\n\tstruct mmc_request *mrq;\n\tunsigned int flags;\n};\n\nstruct cqspi_flash_pdata;\n\nstruct cqspi_st;\n\nstruct cqspi_driver_platdata {\n\tu32 hwcaps_mask;\n\tu16 quirks;\n\tint (*indirect_read_dma)(struct cqspi_flash_pdata *, u_char *, loff_t, size_t);\n\tu32 (*get_dma_status)(struct cqspi_st *);\n};\n\nstruct cqspi_flash_pdata {\n\tstruct cqspi_st *cqspi;\n\tu32 clk_rate;\n\tu32 read_delay;\n\tu32 tshsl_ns;\n\tu32 tsd2d_ns;\n\tu32 tchsh_ns;\n\tu32 tslch_ns;\n\tu8 cs;\n};\n\nstruct cqspi_st {\n\tstruct platform_device *pdev;\n\tstruct spi_controller *host;\n\tstruct clk_bulk_data clks[3];\n\tunsigned int sclk;\n\tvoid *iobase;\n\tvoid *ahb_base;\n\tresource_size_t ahb_size;\n\tstruct completion transfer_complete;\n\tstruct dma_chan *rx_chan;\n\tstruct completion rx_dma_complete;\n\tdma_addr_t mmap_phys_base;\n\tint current_cs;\n\tlong unsigned int master_ref_clk_hz;\n\tbool is_decoded_cs;\n\tu32 fifo_depth;\n\tu32 fifo_width;\n\tu32 num_chipselect;\n\tbool rclk_en;\n\tu32 trigger_address;\n\tu32 wr_delay;\n\tbool use_direct_mode;\n\tbool use_direct_mode_wr;\n\tstruct cqspi_flash_pdata f_pdata[4];\n\tbool use_dma_read;\n\tu32 pd_dev_id;\n\tbool wr_completion;\n\tbool slow_sram;\n\tbool apb_ahb_hazard;\n\tbool is_jh7110;\n\tbool is_rzn1;\n\tbool disable_stig_mode;\n\trefcount_t refcount;\n\trefcount_t inflight_ops;\n\tconst struct cqspi_driver_platdata *ddata;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct crash_mem {\n\tunsigned int max_nr_ranges;\n\tunsigned int nr_ranges;\n\tstruct range ranges[0];\n};\n\nstruct crc64_pi_tuple {\n\t__be64 guard_tag;\n\t__be16 app_tag;\n\t__u8 ref_tag[6];\n};\n\nstruct crc_data {\n\tstruct task_struct *thr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tunsigned int run_threads;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tu32 *crc32;\n\tsize_t **unc_len;\n\tunsigned char **unc;\n};\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tvoid *security;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct power_supply_ext;\n\nstruct cros_chctl_priv {\n\tstruct device *dev;\n\tstruct cros_ec_device *cros_ec;\n\tstruct acpi_battery_hook battery_hook;\n\tstruct power_supply *hooked_battery;\n\tu8 cmd_version;\n\tconst struct power_supply_ext *psy_ext;\n\tstruct mutex lock;\n\tenum power_supply_charge_behaviour current_behaviour;\n\tu8 current_start_threshold;\n\tu8 current_end_threshold;\n};\n\nstruct cros_ec_bs_map {\n\tunsigned int ev_type;\n\tunsigned int code;\n\tu8 bit;\n\tbool inverted;\n};\n\nstruct cros_ec_command {\n\tuint32_t version;\n\tuint32_t command;\n\tuint32_t outsize;\n\tuint32_t insize;\n\tuint32_t result;\n\tuint8_t data[0];\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct cros_ec_debugfs {\n\tstruct cros_ec_dev *ec;\n\tstruct dentry *dir;\n\tstruct circ_buf log_buffer;\n\tstruct cros_ec_command *read_msg;\n\tstruct mutex log_mutex;\n\tstruct delayed_work log_poll_work;\n\tstruct debugfs_blob_wrapper panicinfo_blob;\n\tstruct notifier_block notifier_panic;\n};\n\nstruct ec_response_get_features {\n\tuint32_t flags[2];\n};\n\nstruct cros_ec_dev {\n\tstruct device class_dev;\n\tstruct cros_ec_device *ec_dev;\n\tstruct device *dev;\n\tstruct cros_ec_debugfs *debug_info;\n\tbool has_kb_wake_angle;\n\tu16 cmd_offset;\n\tstruct ec_response_get_features features;\n};\n\nstruct ec_response_motion_sense_fifo_info {\n\tuint16_t size;\n\tuint16_t count;\n\tuint32_t timestamp;\n\tuint16_t total_lost;\n\tuint16_t lost[0];\n} __attribute__((packed));\n\nunion ec_response_get_next_data_v3 {\n\tuint8_t key_matrix[18];\n\tuint32_t host_event;\n\tuint64_t host_event64;\n\tstruct {\n\t\tuint8_t reserved[3];\n\t\tstruct ec_response_motion_sense_fifo_info info;\n\t} sensor_fifo;\n\tuint32_t buttons;\n\tuint32_t switches;\n\tuint32_t fp_events;\n\tuint32_t sysrq;\n\tuint32_t cec_events;\n\tuint8_t cec_message[16];\n};\n\nstruct ec_response_get_next_event_v3 {\n\tuint8_t event_type;\n\tunion ec_response_get_next_data_v3 data;\n};\n\nstruct cros_ec_device {\n\tconst char *phys_name;\n\tstruct device *dev;\n\tstruct class *cros_class;\n\tint (*cmd_readmem)(struct cros_ec_device *, unsigned int, unsigned int, void *);\n\tu16 max_request;\n\tu16 max_response;\n\tu16 max_passthru;\n\tu16 proto_version;\n\tvoid *priv;\n\tint irq;\n\tu8 *din;\n\tu8 *dout;\n\tint din_size;\n\tint dout_size;\n\tbool wake_enabled;\n\tbool suspended;\n\tbool registered;\n\tint (*cmd_xfer)(struct cros_ec_device *, struct cros_ec_command *);\n\tint (*pkt_xfer)(struct cros_ec_device *, struct cros_ec_command *);\n\tstruct lock_class_key lockdep_key;\n\tstruct mutex lock;\n\tu8 mkbp_event_supported;\n\tbool host_sleep_v1;\n\tstruct blocking_notifier_head event_notifier;\n\tstruct ec_response_get_next_event_v3 event_data;\n\tint event_size;\n\tu32 host_event_wake_mask;\n\tu32 last_resume_result;\n\tu16 suspend_timeout_ms;\n\tktime_t last_event_time;\n\tstruct notifier_block notifier_ready;\n\tstruct platform_device *ec;\n\tstruct platform_device *pd;\n\tstruct blocking_notifier_head panic_notifier;\n};\n\nstruct cros_ec_extcon_info {\n\tstruct device *dev;\n\tstruct extcon_dev *edev;\n\tint port_id;\n\tstruct cros_ec_device *ec;\n\tstruct notifier_block notifier;\n\tunsigned int dr;\n\tbool pr;\n\tbool dp;\n\tbool mux;\n\tunsigned int power_type;\n};\n\nstruct cros_ec_hwmon_priv;\n\nstruct cros_ec_hwmon_cooling_priv {\n\tstruct cros_ec_hwmon_priv *hwmon_priv;\n\tu8 index;\n};\n\nstruct cros_ec_hwmon_priv {\n\tstruct cros_ec_device *cros_ec;\n\tconst char *temp_sensor_names[24];\n\tu8 usable_fans;\n\tbool fan_control_supported;\n\tbool temp_threshold_supported;\n\tu8 manual_fans;\n\tu8 manual_fan_pwm[4];\n};\n\nstruct cros_ec_keyb {\n\tunsigned int rows;\n\tunsigned int cols;\n\tint row_shift;\n\tbool ghost_filter;\n\tuint8_t *valid_keys;\n\tuint8_t *old_kb_state;\n\tstruct device *dev;\n\tstruct cros_ec_device *ec;\n\tstruct input_dev *idev;\n\tstruct input_dev *bs_idev;\n\tstruct notifier_block notifier;\n\tstruct vivaldi_data vdata;\n};\n\nstruct cros_ec_platform {\n\tconst char *ec_name;\n\tu16 cmd_offset;\n};\n\nstruct cros_ec_regulator_data {\n\tstruct regulator_desc desc;\n\tstruct regulator_dev *dev;\n\tstruct cros_ec_device *ec_dev;\n\tu32 index;\n\tu16 *voltages_mV;\n\tu16 num_voltages;\n};\n\nstruct cros_ec_rtc {\n\tstruct cros_ec_device *cros_ec;\n\tstruct rtc_device *rtc;\n\tstruct notifier_block notifier;\n\tu32 saved_alarm;\n};\n\nstruct cros_ec_sensor_platform {\n\tu8 sensor_num;\n};\n\nstruct cros_ec_sensors_ec_overflow_state {\n\ts64 offset;\n\ts64 last;\n};\n\nstruct cros_ec_sensors_ts_filter_state {\n\ts64 x_offset;\n\ts64 y_offset;\n\ts64 x_history[64];\n\ts64 y_history[64];\n\ts64 m_history[64];\n\tint history_len;\n\ts64 temp_buf[64];\n\ts64 median_m;\n\ts64 median_error;\n};\n\nstruct ec_params_motion_sense;\n\nstruct ec_response_motion_sense;\n\nstruct cros_ec_sensors_ring_sample;\n\nstruct cros_ec_sensors_ts_batch_state;\n\nstruct cros_ec_sensorhub_sensor_push_data;\n\nstruct cros_ec_sensorhub {\n\tstruct device *dev;\n\tstruct cros_ec_dev *ec;\n\tint sensor_num;\n\tstruct cros_ec_command *msg;\n\tstruct ec_params_motion_sense *params;\n\tstruct ec_response_motion_sense *resp;\n\tstruct mutex cmd_lock;\n\tstruct notifier_block notifier;\n\tstruct cros_ec_sensors_ring_sample *ring;\n\tktime_t fifo_timestamp[2];\n\tstruct ec_response_motion_sense_fifo_info *fifo_info;\n\tint fifo_size;\n\tstruct cros_ec_sensors_ts_batch_state *batch_state;\n\tstruct cros_ec_sensors_ec_overflow_state overflow_a;\n\tstruct cros_ec_sensors_ec_overflow_state overflow_b;\n\tstruct cros_ec_sensors_ts_filter_state filter;\n\tint tight_timestamps;\n\ts32 future_timestamp_count;\n\ts64 future_timestamp_total_ns;\n\tstruct cros_ec_sensorhub_sensor_push_data *push_data;\n};\n\nstruct iio_dev;\n\ntypedef int (*cros_ec_sensorhub_push_data_cb_t)(struct iio_dev *, s16 *, s64);\n\nstruct cros_ec_sensorhub_sensor_push_data {\n\tstruct iio_dev *indio_dev;\n\tcros_ec_sensorhub_push_data_cb_t push_data_cb;\n};\n\nstruct cros_ec_sensors_ring_sample {\n\tu8 sensor_id;\n\tu8 flag;\n\ts16 vector[3];\n\ts64 timestamp;\n};\n\nstruct cros_ec_sensors_ts_batch_state {\n\ts64 penul_ts;\n\tint penul_len;\n\ts64 last_ts;\n\tint last_len;\n\ts64 newest_sensor_event;\n};\n\nstruct spi_device;\n\nstruct kthread_worker;\n\nstruct cros_ec_spi {\n\tstruct spi_device *spi;\n\ts64 last_transfer_ns;\n\tunsigned int start_of_msg_delay;\n\tunsigned int end_of_msg_delay;\n\tstruct kthread_worker *high_pri_worker;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\ntypedef int (*cros_ec_xfer_fn_t)(struct cros_ec_device *, struct cros_ec_command *);\n\nstruct cros_ec_xfer_work_params {\n\tstruct kthread_work work;\n\tcros_ec_xfer_fn_t fn;\n\tstruct cros_ec_device *ec_dev;\n\tstruct cros_ec_command *ec_msg;\n\tint ret;\n};\n\nstruct cros_feature_to_cells {\n\tunsigned int id;\n\tconst struct mfd_cell *mfd_cells;\n\tunsigned int num_cells;\n};\n\nstruct cros_feature_to_name {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *desc;\n};\n\nstruct cros_usbpd_notify_data {\n\tstruct device *dev;\n\tstruct cros_ec_device *ec;\n\tstruct notifier_block nb;\n};\n\nstruct crs_csi2 {\n\tstruct list_head entry;\n\tacpi_handle handle;\n\tstruct acpi_device_software_nodes *swnodes;\n\tstruct list_head connections;\n\tu32 port_count;\n};\n\nstruct crs_csi2_connection {\n\tstruct list_head entry;\n\tstruct acpi_resource_csi2_serialbus csi2_data;\n\tacpi_handle remote_handle;\n\tchar remote_name[0];\n};\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_acomp_stream {\n\tspinlock_t lock;\n\tvoid *ctx;\n};\n\nstruct crypto_acomp_streams {\n\tvoid * (*alloc_ctx)(void);\n\tvoid (*free_ctx)(void *);\n\tstruct crypto_acomp_stream *streams;\n\tstruct work_struct stream_work;\n\tcpumask_t stream_want;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_aes_ctx {\n\tu32 key_enc[60];\n\tu32 key_dec[60];\n\tu32 key_length;\n};\n\nstruct crypto_aes_essiv_cbc_ctx {\n\tstruct crypto_aes_ctx key1;\n\tlong: 0;\n\tstruct crypto_aes_ctx key2;\n\tlong: 0;\n};\n\nstruct crypto_aes_xts_ctx {\n\tstruct crypto_aes_ctx key1;\n\tlong: 0;\n\tstruct crypto_aes_ctx key2;\n\tlong: 0;\n};\n\nstruct crypto_ahash {\n\tbool using_shash;\n\tunsigned int statesize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_akcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_akcipher_sync_data {\n\tstruct crypto_akcipher *tfm;\n\tconst void *src;\n\tvoid *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct akcipher_request *req;\n\tstruct crypto_wait cwait;\n\tstruct scatterlist sg;\n\tu8 *buf;\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_dump_info {\n\tstruct sk_buff *in_skb;\n\tstruct sk_buff *out_skb;\n\tu32 nlmsg_seq;\n\tu16 nlmsg_flags;\n};\n\nstruct crypto_hash_walk {\n\tconst char *data;\n\tunsigned int offset;\n\tunsigned int flags;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n};\n\nstruct crypto_kpp {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_kpp_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n\tbool test_started;\n};\n\nstruct nlmsghdr;\n\nstruct netlink_callback;\n\nstruct crypto_link {\n\tint (*doit)(struct sk_buff *, struct nlmsghdr *, struct nlattr **);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n};\n\nstruct crypto_lskcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_lskcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct crypto_report_acomp {\n\tchar type[64];\n};\n\nstruct crypto_report_aead {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int maxauthsize;\n\tunsigned int ivsize;\n};\n\nstruct crypto_report_akcipher {\n\tchar type[64];\n};\n\nstruct crypto_report_blkcipher {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n};\n\nstruct crypto_report_cipher {\n\tchar type[64];\n\tunsigned int blocksize;\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n};\n\nstruct crypto_report_comp {\n\tchar type[64];\n};\n\nstruct crypto_report_hash {\n\tchar type[64];\n\tunsigned int blocksize;\n\tunsigned int digestsize;\n};\n\nstruct crypto_report_kpp {\n\tchar type[64];\n};\n\nstruct crypto_report_larval {\n\tchar type[64];\n};\n\nstruct crypto_report_rng {\n\tchar type[64];\n\tunsigned int seedsize;\n};\n\nstruct crypto_report_sig {\n\tchar type[64];\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sig {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sig_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sync_aead {\n\tstruct crypto_aead base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct hlist_head dead;\n\tstruct module *module;\n\tstruct work_struct free_work;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tvoid (*destroy)(struct crypto_alg *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n\tunsigned int algsize;\n};\n\nstruct crypto_user_alg {\n\tchar cru_name[64];\n\tchar cru_driver_name[64];\n\tchar cru_module_name[64];\n\t__u32 cru_type;\n\t__u32 cru_mask;\n\t__u32 cru_refcnt;\n\t__u32 cru_flags;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_alg data;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct cs2000_priv {\n\tstruct clk_hw hw;\n\tstruct i2c_client *client;\n\tstruct clk *clk_in;\n\tstruct clk *ref_clk;\n\tstruct regmap *regmap;\n\tbool dynamic_mode;\n\tbool lf_ratio;\n\tbool clk_skip;\n\tlong unsigned int saved_rate;\n\tlong unsigned int saved_parent_rate;\n};\n\nstruct cs_data {\n\tu32 enable_mask;\n\tu16 slow_cfg;\n\tu16 fast_cfg;\n};\n\nstruct csi2_resources_walk_data {\n\tacpi_handle handle;\n\tstruct list_head connections;\n};\n\nstruct mem_ctl_info;\n\nstruct rank_info;\n\nstruct csrow_info {\n\tstruct device dev;\n\tlong unsigned int first_page;\n\tlong unsigned int last_page;\n\tlong unsigned int page_mask;\n\tint csrow_idx;\n\tu32 ue_count;\n\tu32 ce_count;\n\tstruct mem_ctl_info *mci;\n\tu32 nr_channels;\n\tstruct rank_info **channels;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[10];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[10];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ct_data_s {\n\tunion {\n\t\tush freq;\n\t\tush code;\n\t} fc;\n\tunion {\n\t\tush dad;\n\t\tush len;\n\t} dl;\n};\n\ntypedef struct ct_data_s ct_data;\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct edac_device_ctl_info;\n\nstruct ctl_info_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctrl_regs {\n\tu32 tmr_ctrl;\n\tu32 tmr_tevent;\n\tu32 tmr_temask;\n\tu32 tmr_pevent;\n\tu32 tmr_pemask;\n\tu32 tmr_stat;\n\tu32 tmr_cnt_h;\n\tu32 tmr_cnt_l;\n\tu32 tmr_add;\n\tu32 tmr_acc;\n\tu32 tmr_prsc;\n\tu8 res1[4];\n\tu32 tmroff_h;\n\tu32 tmroff_l;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct cv1800_clk_common {\n\tvoid *base;\n\tspinlock_t *lock;\n\tstruct clk_hw hw;\n\tlong unsigned int features;\n};\n\nstruct cv1800_clk_regbit {\n\tu16 reg;\n\ts8 shift;\n};\n\nstruct cv1800_clk_regfield {\n\tu16 reg;\n\tu8 shift;\n\tu8 width;\n\ts16 initval;\n\tlong unsigned int flags;\n};\n\nstruct cv1800_clk_audio {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit src_en;\n\tstruct cv1800_clk_regbit output_en;\n\tstruct cv1800_clk_regbit div_en;\n\tstruct cv1800_clk_regbit div_up;\n\tstruct cv1800_clk_regfield m;\n\tstruct cv1800_clk_regfield n;\n\tu32 target_rate;\n};\n\nstruct cv1800_clk_div {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n\tstruct cv1800_clk_regfield div;\n};\n\nstruct cv1800_clk_bypass_div {\n\tstruct cv1800_clk_div div;\n\tstruct cv1800_clk_regbit bypass;\n};\n\nstruct cv1800_clk_mux {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n\tstruct cv1800_clk_regfield div;\n\tstruct cv1800_clk_regfield mux;\n};\n\nstruct cv1800_clk_bypass_mux {\n\tstruct cv1800_clk_mux mux;\n\tstruct cv1800_clk_regbit bypass;\n};\n\nstruct cv1800_clk_desc;\n\nstruct cv1800_clk_ctrl {\n\tconst struct cv1800_clk_desc *desc;\n\tspinlock_t lock;\n};\n\nstruct cv1800_clk_desc {\n\tstruct clk_hw_onecell_data *clks_data;\n\tint (*pre_init)(struct device *, void *, struct cv1800_clk_ctrl *, const struct cv1800_clk_desc *);\n};\n\nstruct cv1800_clk_gate {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n};\n\nstruct cv1800_clk_mmux {\n\tstruct cv1800_clk_common common;\n\tstruct cv1800_clk_regbit gate;\n\tstruct cv1800_clk_regfield div[2];\n\tstruct cv1800_clk_regfield mux[2];\n\tstruct cv1800_clk_regbit bypass;\n\tstruct cv1800_clk_regbit clk_sel;\n\tconst s8 *parent2sel;\n\tconst u8 *sel2parent[2];\n};\n\nstruct cv1800_clk_pll_limit;\n\nstruct cv1800_clk_pll_synthesizer;\n\nstruct cv1800_clk_pll {\n\tstruct cv1800_clk_common common;\n\tu32 pll_reg;\n\tstruct cv1800_clk_regbit pll_pwd;\n\tstruct cv1800_clk_regbit pll_status;\n\tconst struct cv1800_clk_pll_limit *pll_limit;\n\tstruct cv1800_clk_pll_synthesizer *pll_syn;\n};\n\nstruct cv1800_clk_pll_limit {\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} pre_div;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} div;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} post_div;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} ictrl;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} mode;\n};\n\nstruct cv1800_clk_pll_synthesizer {\n\tstruct cv1800_clk_regbit en;\n\tstruct cv1800_clk_regbit clk_half;\n\tu32 ctrl;\n\tu32 set;\n};\n\nstruct sophgo_pin {\n\tu16 id;\n\tu16 flags;\n};\n\nstruct cv1800_pinmux {\n\tu16 offset;\n\tu8 area;\n\tu8 max;\n};\n\nstruct cv1800_pinmux2 {\n\tu16 offset;\n\tu8 area;\n\tu8 max;\n\tu8 pfunc;\n};\n\nstruct cv1800_pinconf {\n\tu16 offset;\n\tu8 area;\n};\n\nstruct cv1800_pin {\n\tstruct sophgo_pin pin;\n\tu8 power_domain;\n\tstruct cv1800_pinmux mux;\n\tstruct cv1800_pinmux2 mux2;\n\tstruct cv1800_pinconf conf;\n};\n\nstruct cv1800_priv {\n\tu32 *power_cfg;\n\tvoid *regs[2];\n};\n\nstruct cvb_coefficients {\n\tint c0;\n\tint c1;\n\tint c2;\n};\n\nstruct cvb_cpu_dfll_data {\n\tu32 tune0_low;\n\tu32 tune0_high;\n\tu32 tune1;\n\tunsigned int tune_high_min_millivolts;\n};\n\nstruct cvb_table_freq_entry {\n\tlong unsigned int freq;\n\tstruct cvb_coefficients coefficients;\n};\n\nstruct cvb_table {\n\tint speedo_id;\n\tint process_id;\n\tint min_millivolts;\n\tint max_millivolts;\n\tint speedo_scale;\n\tint voltage_scale;\n\tstruct cvb_table_freq_entry entries[40];\n\tstruct cvb_cpu_dfll_data cpu_dfll_data;\n};\n\nstruct cvmx_smix_clk_s {\n\tu64 phase: 8;\n\tu64 sample: 4;\n\tu64 preamble: 1;\n\tu64 clk_idle: 1;\n\tu64 reserved_14_14: 1;\n\tu64 sample_mode: 1;\n\tu64 sample_hi: 5;\n\tu64 reserved_21_23: 3;\n\tu64 mode: 1;\n\tu64 reserved_25_63: 39;\n};\n\nunion cvmx_smix_clk {\n\tu64 u64;\n\tstruct cvmx_smix_clk_s s;\n};\n\nstruct cvmx_smix_cmd_s {\n\tu64 reg_adr: 5;\n\tu64 reserved_5_7: 3;\n\tu64 phy_adr: 5;\n\tu64 reserved_13_15: 3;\n\tu64 phy_op: 2;\n\tu64 reserved_18_63: 46;\n};\n\nunion cvmx_smix_cmd {\n\tu64 u64;\n\tstruct cvmx_smix_cmd_s s;\n};\n\nstruct cvmx_smix_en_s {\n\tu64 en: 1;\n\tu64 reserved_1_63: 63;\n};\n\nunion cvmx_smix_en {\n\tu64 u64;\n\tstruct cvmx_smix_en_s s;\n};\n\nstruct cvmx_smix_rd_dat_s {\n\tu64 dat: 16;\n\tu64 val: 1;\n\tu64 pending: 1;\n\tu64 reserved_18_63: 46;\n};\n\nunion cvmx_smix_rd_dat {\n\tu64 u64;\n\tstruct cvmx_smix_rd_dat_s s;\n};\n\nstruct cvmx_smix_wr_dat_s {\n\tu64 dat: 16;\n\tu64 val: 1;\n\tu64 pending: 1;\n\tu64 reserved_18_63: 46;\n};\n\nunion cvmx_smix_wr_dat {\n\tu64 u64;\n\tstruct cvmx_smix_wr_dat_s s;\n};\n\nstruct cxl_event_record_hdr {\n\tu8 length;\n\tu8 flags[3];\n\t__le16 handle;\n\t__le16 related_handle;\n\t__le64 timestamp;\n\tu8 maint_op_class;\n\tu8 maint_op_sub_class;\n\t__le16 ld_id;\n\tu8 head_id;\n\tu8 reserved[11];\n};\n\nstruct cxl_event_generic {\n\tstruct cxl_event_record_hdr hdr;\n\tu8 data[80];\n};\n\nstruct cxl_event_media_hdr {\n\tstruct cxl_event_record_hdr hdr;\n\t__le64 phys_addr;\n\tu8 descriptor;\n\tu8 type;\n\tu8 transaction_type;\n\tu8 validity_flags[2];\n\tu8 channel;\n\tu8 rank;\n} __attribute__((packed));\n\nstruct cxl_event_gen_media {\n\tstruct cxl_event_media_hdr media_hdr;\n\tu8 device[3];\n\tu8 component_id[16];\n\tu8 cme_threshold_ev_flags;\n\tu8 cme_count[3];\n\tu8 sub_type;\n\tu8 reserved[41];\n};\n\nstruct cxl_event_dram {\n\tstruct cxl_event_media_hdr media_hdr;\n\tu8 nibble_mask[3];\n\tu8 bank_group;\n\tu8 bank;\n\tu8 row[3];\n\tu8 column[2];\n\tu8 correction_mask[32];\n\tu8 component_id[16];\n\tu8 sub_channel;\n\tu8 cme_threshold_ev_flags;\n\tu8 cvme_count[3];\n\tu8 sub_type;\n\tu8 reserved;\n};\n\nstruct cxl_get_health_info {\n\tu8 health_status;\n\tu8 media_status;\n\tu8 add_status;\n\tu8 life_used;\n\tu8 device_temp[2];\n\tu8 dirty_shutdown_cnt[4];\n\tu8 cor_vol_err_cnt[4];\n\tu8 cor_per_err_cnt[4];\n};\n\nstruct cxl_event_mem_module {\n\tstruct cxl_event_record_hdr hdr;\n\tu8 event_type;\n\tstruct cxl_get_health_info info;\n\tu8 validity_flags[2];\n\tu8 component_id[16];\n\tu8 event_sub_type;\n\tu8 reserved[42];\n};\n\nstruct cxl_event_mem_sparing {\n\tstruct cxl_event_record_hdr hdr;\n\tu8 rsv1;\n\tu8 rsv2;\n\tu8 flags;\n\tu8 result;\n\t__le16 validity_flags;\n\tu8 reserved1[6];\n\t__le16 res_avail;\n\tu8 channel;\n\tu8 rank;\n\tu8 nibble_mask[3];\n\tu8 bank_group;\n\tu8 bank;\n\tu8 row[3];\n\t__le16 column;\n\tu8 component_id[16];\n\tu8 sub_channel;\n\tu8 reserved2[37];\n};\n\nunion cxl_event {\n\tstruct cxl_event_generic generic;\n\tstruct cxl_event_gen_media gen_media;\n\tstruct cxl_event_dram dram;\n\tstruct cxl_event_mem_module mem_module;\n\tstruct cxl_event_mem_sparing mem_sparing;\n\tstruct cxl_event_media_hdr media_hdr;\n};\n\nstruct cxl_cper_event_rec {\n\tstruct {\n\t\tu32 length;\n\t\tu64 validation_bits;\n\t\tstruct cper_cxl_event_devid device_id;\n\t\tstruct cper_cxl_event_sn dev_serial_num;\n\t} __attribute__((packed)) hdr;\n\tunion cxl_event event;\n};\n\nstruct cxl_cper_sec_prot_err {\n\tu64 valid_bits;\n\tu8 agent_type;\n\tu8 reserved[7];\n\tunion {\n\t\tu64 rcrb_base_addr;\n\t\tstruct {\n\t\t\tu8 function;\n\t\t\tu8 device;\n\t\t\tu8 bus;\n\t\t\tu16 segment;\n\t\t\tu8 reserved_1[3];\n\t\t} __attribute__((packed));\n\t} agent_addr;\n\tstruct {\n\t\tu16 vendor_id;\n\t\tu16 device_id;\n\t\tu16 subsystem_vendor_id;\n\t\tu16 subsystem_id;\n\t\tu8 class_code[2];\n\t\tu16 slot;\n\t\tu8 reserved_1[4];\n\t} device_id;\n\tstruct {\n\t\tu32 lower_dw;\n\t\tu32 upper_dw;\n\t} dev_serial_num;\n\tu8 capability[60];\n\tu16 dvsec_len;\n\tu16 err_len;\n\tu8 reserved_2[4];\n} __attribute__((packed));\n\nstruct cxl_ras_capability_regs {\n\tu32 uncor_status;\n\tu32 uncor_mask;\n\tu32 uncor_severity;\n\tu32 cor_status;\n\tu32 cor_mask;\n\tu32 cap_control;\n\tu32 header_log[16];\n};\n\nstruct cxl_cper_prot_err_work_data {\n\tstruct cxl_cper_sec_prot_err prot_err;\n\tstruct cxl_ras_capability_regs ras_cap;\n\tint severity;\n};\n\nstruct cxl_cper_work_data {\n\tenum cxl_event_type event_type;\n\tstruct cxl_cper_event_rec rec;\n} __attribute__((packed));\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct dart_io_pgtable {\n\tstruct io_pgtable iop;\n\tint levels;\n\tint tbl_bits;\n\tint bits_per_level;\n\tvoid *pgd[4];\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct mtd_ecc_stats {\n\t__u32 corrected;\n\t__u32 failed;\n\t__u32 badblocks;\n\t__u32 bbtblocks;\n};\n\nstruct mtd_debug_info {\n\tstruct dentry *dfs_dir;\n};\n\nstruct mtd_part {\n\tstruct list_head node;\n\tu64 offset;\n\tu64 size;\n\tu32 flags;\n};\n\nstruct mtd_master {\n\tstruct mutex partitions_lock;\n\tstruct mutex chrdev_lock;\n\tunsigned int suspended: 1;\n};\n\nstruct mtd_ooblayout_ops;\n\nstruct mtd_pairing_scheme;\n\nstruct mtd_erase_region_info;\n\nstruct erase_info;\n\nstruct mtd_oob_ops;\n\nstruct otp_info;\n\nstruct nvmem_device;\n\nstruct mtd_info {\n\tu_char type;\n\tuint32_t flags;\n\tuint64_t size;\n\tuint32_t erasesize;\n\tuint32_t writesize;\n\tuint32_t writebufsize;\n\tuint32_t oobsize;\n\tuint32_t oobavail;\n\tunsigned int erasesize_shift;\n\tunsigned int writesize_shift;\n\tunsigned int erasesize_mask;\n\tunsigned int writesize_mask;\n\tunsigned int bitflip_threshold;\n\tconst char *name;\n\tint index;\n\tconst struct mtd_ooblayout_ops *ooblayout;\n\tconst struct mtd_pairing_scheme *pairing;\n\tunsigned int ecc_step_size;\n\tunsigned int ecc_strength;\n\tint numeraseregions;\n\tstruct mtd_erase_region_info *eraseregions;\n\tint (*_erase)(struct mtd_info *, struct erase_info *);\n\tint (*_point)(struct mtd_info *, loff_t, size_t, size_t *, void **, resource_size_t *);\n\tint (*_unpoint)(struct mtd_info *, loff_t, size_t);\n\tint (*_read)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_panic_write)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_read_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_write_oob)(struct mtd_info *, loff_t, struct mtd_oob_ops *);\n\tint (*_get_fact_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_fact_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_get_user_prot_info)(struct mtd_info *, size_t, size_t *, struct otp_info *);\n\tint (*_read_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, u_char *);\n\tint (*_write_user_prot_reg)(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);\n\tint (*_lock_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_erase_user_prot_reg)(struct mtd_info *, loff_t, size_t);\n\tint (*_writev)(struct mtd_info *, const struct kvec *, long unsigned int, loff_t, size_t *);\n\tvoid (*_sync)(struct mtd_info *);\n\tint (*_lock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_unlock)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_is_locked)(struct mtd_info *, loff_t, uint64_t);\n\tint (*_block_isreserved)(struct mtd_info *, loff_t);\n\tint (*_block_isbad)(struct mtd_info *, loff_t);\n\tint (*_block_markbad)(struct mtd_info *, loff_t);\n\tint (*_max_bad_blocks)(struct mtd_info *, loff_t, size_t);\n\tint (*_suspend)(struct mtd_info *);\n\tvoid (*_resume)(struct mtd_info *);\n\tvoid (*_reboot)(struct mtd_info *);\n\tint (*_get_device)(struct mtd_info *);\n\tvoid (*_put_device)(struct mtd_info *);\n\tbool oops_panic_write;\n\tstruct notifier_block reboot_notifier;\n\tstruct mtd_ecc_stats ecc_stats;\n\tint subpage_sft;\n\tvoid *priv;\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct kref refcnt;\n\tstruct mtd_debug_info dbg;\n\tstruct nvmem_device *nvmem;\n\tstruct nvmem_device *otp_user_nvmem;\n\tstruct nvmem_device *otp_factory_nvmem;\n\tstruct mtd_info *parent;\n\tstruct list_head partitions;\n\tstruct mtd_part part;\n\tstruct mtd_master master;\n};\n\nstruct dataflash {\n\tu8 command[4];\n\tchar name[24];\n\tshort unsigned int page_offset;\n\tunsigned int page_size;\n\tstruct mutex lock;\n\tstruct spi_device *spi;\n\tstruct mtd_info mtd;\n};\n\nstruct davinci_gpio_regs {\n\tu32 dir;\n\tu32 out_data;\n\tu32 set_data;\n\tu32 clr_data;\n\tu32 in_data;\n\tu32 set_rising;\n\tu32 clr_rising;\n\tu32 set_falling;\n\tu32 clr_falling;\n\tu32 intstat;\n};\n\nstruct davinci_gpio_controller {\n\tstruct gpio_chip chip;\n\tstruct irq_domain *irq_domain;\n\tspinlock_t lock;\n\tvoid *regs[5];\n\tint gpio_unbanked;\n\tint irqs[32];\n\tstruct davinci_gpio_regs context[5];\n\tu32 binten_context;\n};\n\nstruct davinci_gpio_irq_data {\n\tvoid *regs;\n\tstruct davinci_gpio_controller *chip;\n\tint bank_num;\n};\n\nstruct mdio_platform_data {\n\tlong unsigned int bus_freq;\n};\n\nstruct davinci_mdio_regs;\n\nstruct davinci_mdio_data {\n\tstruct mdio_platform_data pdata;\n\tstruct mdiobb_ctrl bb_ctrl;\n\tstruct davinci_mdio_regs *regs;\n\tstruct clk *clk;\n\tstruct device *dev;\n\tstruct mii_bus *bus;\n\tbool active_in_suspend;\n\tlong unsigned int access_time;\n\tbool skip_scan;\n\tu32 clk_div;\n\tbool manual_mode;\n};\n\nstruct davinci_mdio_of_param {\n\tint autosuspend_delay_ms;\n\tbool manual_mode;\n};\n\nstruct davinci_mdio_regs {\n\tu32 version;\n\tu32 control;\n\tu32 alive;\n\tu32 link;\n\tu32 linkintraw;\n\tu32 linkintmasked;\n\tu32 __reserved_0[2];\n\tu32 userintraw;\n\tu32 userintmasked;\n\tu32 userintmaskset;\n\tu32 userintmaskclr;\n\tu32 manualif;\n\tu32 poll;\n\tu32 __reserved_1[18];\n\tstruct {\n\t\tu32 access;\n\t\tu32 physel;\n\t} user[0];\n};\n\nstruct dax_device;\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct xhci_dbc;\n\nstruct dbc_driver {\n\tint (*configure)(struct xhci_dbc *);\n\tvoid (*disconnect)(struct xhci_dbc *);\n};\n\nstruct xhci_ring;\n\nstruct dbc_ep {\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tstruct xhci_ring *ring;\n\tunsigned int direction: 1;\n\tunsigned int halted: 1;\n};\n\nstruct dbc_regs {\n\t__le32 capability;\n\t__le32 doorbell;\n\t__le32 ersts;\n\t__le32 __reserved_0;\n\t__le64 erstba;\n\t__le64 erdp;\n\t__le32 control;\n\t__le32 status;\n\t__le32 portsc;\n\t__le32 __reserved_1;\n\t__le64 dccp;\n\t__le32 devinfo1;\n\t__le32 devinfo2;\n};\n\nunion xhci_trb;\n\nstruct dbc_request {\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tvoid (*complete)(struct xhci_dbc *, struct dbc_request *);\n\tstruct list_head list_pool;\n\tint status;\n\tunsigned int actual;\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tdma_addr_t trb_dma;\n\tunion xhci_trb *trb;\n\tunsigned int direction: 1;\n};\n\nstruct dbc_str {\n\tchar manufacturer[127];\n\tchar product[127];\n\tchar serial[127];\n};\n\nstruct dbc_str_descs {\n\tchar string0[254];\n\tchar manufacturer[254];\n\tchar product[254];\n\tchar serial[254];\n};\n\nstruct gov_attr_set {\n\tstruct kobject kobj;\n\tstruct list_head policy_list;\n\tstruct mutex update_lock;\n\tint usage_count;\n};\n\nstruct dbs_governor;\n\nstruct dbs_data {\n\tstruct gov_attr_set attr_set;\n\tstruct dbs_governor *gov;\n\tvoid *tuners;\n\tunsigned int ignore_nice_load;\n\tunsigned int sampling_rate;\n\tunsigned int sampling_down_factor;\n\tunsigned int up_threshold;\n\tunsigned int io_is_busy;\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct dbs_governor {\n\tstruct cpufreq_governor gov;\n\tstruct kobj_type kobj_type;\n\tstruct dbs_data *gdbs_data;\n\tunsigned int (*gov_dbs_update)(struct cpufreq_policy *);\n\tstruct policy_dbs_info * (*alloc)(void);\n\tvoid (*free)(struct policy_dbs_info *);\n\tint (*init)(struct dbs_data *);\n\tvoid (*exit)(struct dbs_data *);\n\tvoid (*start)(struct cpufreq_policy *);\n};\n\nstruct dcb_app {\n\t__u8 selector;\n\t__u8 priority;\n\t__u16 protocol;\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct rzv2h_cpg_priv;\n\nstruct ddiv_clk {\n\tstruct rzv2h_cpg_priv *priv;\n\tstruct clk_divider div;\n\tu8 mon;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct ohci_hcd;\n\nstruct debug_buffer {\n\tssize_t (*fill_func)(struct debug_buffer *);\n\tstruct ohci_hcd *ohci;\n\tstruct mutex mutex;\n\tsize_t count;\n\tchar *page;\n};\n\nstruct debug_info {\n\tint suspended_step;\n\tint bps_disabled;\n\tint wps_disabled;\n\tstruct perf_event *hbp_break[16];\n\tstruct perf_event *hbp_watch[16];\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\nstruct debugfs_info {\n\tstruct dentry *debug_dir;\n\tvoid *rasdes_info;\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct dec_data {\n\tstruct task_struct *thr;\n\tstruct crypto_acomp *cc;\n\tstruct acomp_req *cr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n};\n\nstruct skcipher_request;\n\nstruct decryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tstruct scatterlist frags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct deferred_entry {\n\tstruct list_head list;\n\tgrant_ref_t ref;\n\tuint16_t warn_delay;\n\tstruct page *page;\n};\n\nstruct deferred_split {\n\tspinlock_t split_queue_lock;\n\tstruct list_head split_queue;\n\tlong unsigned int split_queue_len;\n};\n\nstruct z_stream_s;\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct static_tree_desc_s;\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\nstruct tree_desc_s {\n\tct_data *dyn_tree;\n\tint max_code;\n\tstatic_tree_desc *stat_desc;\n};\n\nstruct deflate_state {\n\tz_streamp strm;\n\tint status;\n\tByte *pending_buf;\n\tulg pending_buf_size;\n\tByte *pending_out;\n\tint pending;\n\tint noheader;\n\tByte data_type;\n\tByte method;\n\tint last_flush;\n\tuInt w_size;\n\tuInt w_bits;\n\tuInt w_mask;\n\tByte *window;\n\tulg window_size;\n\tPos *prev;\n\tPos *head;\n\tuInt ins_h;\n\tuInt hash_size;\n\tuInt hash_bits;\n\tuInt hash_mask;\n\tuInt hash_shift;\n\tlong int block_start;\n\tuInt match_length;\n\tIPos prev_match;\n\tint match_available;\n\tuInt strstart;\n\tuInt match_start;\n\tuInt lookahead;\n\tuInt prev_length;\n\tuInt max_chain_length;\n\tuInt max_lazy_match;\n\tint level;\n\tint strategy;\n\tuInt good_match;\n\tint nice_match;\n\tstruct ct_data_s dyn_ltree[573];\n\tstruct ct_data_s dyn_dtree[61];\n\tstruct ct_data_s bl_tree[39];\n\tstruct tree_desc_s l_desc;\n\tstruct tree_desc_s d_desc;\n\tstruct tree_desc_s bl_desc;\n\tush bl_count[16];\n\tint heap[573];\n\tint heap_len;\n\tint heap_max;\n\tuch depth[573];\n\tuch *l_buf;\n\tuInt lit_bufsize;\n\tuInt last_lit;\n\tush *d_buf;\n\tulg opt_len;\n\tulg static_len;\n\tulg compressed_len;\n\tuInt matches;\n\tint last_eob_len;\n\tush bi_buf;\n\tint bi_valid;\n};\n\nstruct deflate_workspace {\n\tdeflate_state deflate_memory;\n\tByte *window_memory;\n\tPos *prev_memory;\n\tPos *head_memory;\n\tchar *overlay_memory;\n};\n\ntypedef struct deflate_workspace deflate_workspace;\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct demotion_nodes {\n\tnodemask_t preferred;\n};\n\nstruct nand_memory_organization {\n\tunsigned int bits_per_cell;\n\tunsigned int pagesize;\n\tunsigned int oobsize;\n\tunsigned int pages_per_eraseblock;\n\tunsigned int eraseblocks_per_lun;\n\tunsigned int max_bad_eraseblocks_per_lun;\n\tunsigned int planes_per_lun;\n\tunsigned int luns_per_target;\n\tunsigned int ntargets;\n};\n\nstruct nand_ecc_props {\n\tenum nand_ecc_engine_type engine_type;\n\tenum nand_ecc_placement placement;\n\tenum nand_ecc_algo algo;\n\tunsigned int strength;\n\tunsigned int step_size;\n\tunsigned int flags;\n};\n\nstruct nand_ecc_context {\n\tstruct nand_ecc_props conf;\n\tunsigned int nsteps;\n\tunsigned int total;\n\tvoid *priv;\n};\n\nstruct nand_ecc_engine;\n\nstruct nand_ecc {\n\tstruct nand_ecc_props defaults;\n\tstruct nand_ecc_props requirements;\n\tstruct nand_ecc_props user_conf;\n\tstruct nand_ecc_context ctx;\n\tstruct nand_ecc_engine *ondie_engine;\n\tstruct nand_ecc_engine *engine;\n};\n\nstruct nand_row_converter {\n\tunsigned int lun_addr_shift;\n\tunsigned int eraseblock_addr_shift;\n};\n\nstruct nand_bbt {\n\tlong unsigned int *cache;\n};\n\nstruct nand_ops;\n\nstruct nand_device {\n\tstruct mtd_info mtd;\n\tstruct nand_memory_organization memorg;\n\tstruct nand_ecc ecc;\n\tstruct nand_row_converter rowconv;\n\tstruct nand_bbt bbt;\n\tconst struct nand_ops *ops;\n};\n\nstruct nand_id {\n\tu8 data[8];\n\tint len;\n};\n\nstruct onfi_params;\n\nstruct nand_parameters {\n\tconst char *model;\n\tbool supports_set_get_features;\n\tbool supports_read_cache;\n\tlong unsigned int set_feature_list[4];\n\tlong unsigned int get_feature_list[4];\n\tstruct onfi_params *onfi;\n};\n\nstruct nand_manufacturer_desc;\n\nstruct nand_manufacturer {\n\tconst struct nand_manufacturer_desc *desc;\n\tvoid *priv;\n};\n\nstruct nand_chip;\n\nstruct nand_interface_config;\n\nstruct nand_chip_ops {\n\tint (*suspend)(struct nand_chip *);\n\tvoid (*resume)(struct nand_chip *);\n\tint (*lock_area)(struct nand_chip *, loff_t, uint64_t);\n\tint (*unlock_area)(struct nand_chip *, loff_t, uint64_t);\n\tint (*setup_read_retry)(struct nand_chip *, int);\n\tint (*choose_interface_config)(struct nand_chip *, struct nand_interface_config *);\n};\n\nstruct nand_controller_ops;\n\nstruct nand_controller {\n\tstruct mutex lock;\n\tconst struct nand_controller_ops *ops;\n\tstruct {\n\t\tunsigned int data_only_read: 1;\n\t\tunsigned int cont_read: 1;\n\t} supported_op;\n\tbool controller_wp;\n};\n\nstruct nand_legacy {\n\tvoid *IO_ADDR_R;\n\tvoid *IO_ADDR_W;\n\tvoid (*select_chip)(struct nand_chip *, int);\n\tu8 (*read_byte)(struct nand_chip *);\n\tvoid (*write_byte)(struct nand_chip *, u8);\n\tvoid (*write_buf)(struct nand_chip *, const u8 *, int);\n\tvoid (*read_buf)(struct nand_chip *, u8 *, int);\n\tvoid (*cmd_ctrl)(struct nand_chip *, int, unsigned int);\n\tvoid (*cmdfunc)(struct nand_chip *, unsigned int, int, int);\n\tint (*dev_ready)(struct nand_chip *);\n\tint (*waitfunc)(struct nand_chip *);\n\tint (*block_bad)(struct nand_chip *, loff_t);\n\tint (*block_markbad)(struct nand_chip *, loff_t);\n\tint (*set_features)(struct nand_chip *, int, u8 *);\n\tint (*get_features)(struct nand_chip *, int, u8 *);\n\tint chip_delay;\n\tstruct nand_controller dummy_controller;\n};\n\nstruct nand_ecc_ctrl {\n\tenum nand_ecc_engine_type engine_type;\n\tenum nand_ecc_placement placement;\n\tenum nand_ecc_algo algo;\n\tint steps;\n\tint size;\n\tint bytes;\n\tint total;\n\tint strength;\n\tint prepad;\n\tint postpad;\n\tunsigned int options;\n\tu8 *calc_buf;\n\tu8 *code_buf;\n\tvoid (*hwctl)(struct nand_chip *, int);\n\tint (*calculate)(struct nand_chip *, const uint8_t *, uint8_t *);\n\tint (*correct)(struct nand_chip *, uint8_t *, uint8_t *, uint8_t *);\n\tint (*read_page_raw)(struct nand_chip *, uint8_t *, int, int);\n\tint (*write_page_raw)(struct nand_chip *, const uint8_t *, int, int);\n\tint (*read_page)(struct nand_chip *, uint8_t *, int, int);\n\tint (*read_subpage)(struct nand_chip *, uint32_t, uint32_t, uint8_t *, int);\n\tint (*write_subpage)(struct nand_chip *, uint32_t, uint32_t, const uint8_t *, int, int);\n\tint (*write_page)(struct nand_chip *, const uint8_t *, int, int);\n\tint (*write_oob_raw)(struct nand_chip *, int);\n\tint (*read_oob_raw)(struct nand_chip *, int);\n\tint (*read_oob)(struct nand_chip *, int);\n\tint (*write_oob)(struct nand_chip *, int);\n};\n\nstruct nand_bbt_descr;\n\nstruct nand_secure_region;\n\nstruct nand_chip {\n\tstruct nand_device base;\n\tstruct nand_id id;\n\tstruct nand_parameters parameters;\n\tstruct nand_manufacturer manufacturer;\n\tstruct nand_chip_ops ops;\n\tstruct nand_legacy legacy;\n\tunsigned int options;\n\tconst struct nand_interface_config *current_interface_config;\n\tstruct nand_interface_config *best_interface_config;\n\tunsigned int bbt_erase_shift;\n\tunsigned int bbt_options;\n\tunsigned int badblockpos;\n\tunsigned int badblockbits;\n\tstruct nand_bbt_descr *bbt_td;\n\tstruct nand_bbt_descr *bbt_md;\n\tstruct nand_bbt_descr *badblock_pattern;\n\tu8 *bbt;\n\tunsigned int page_shift;\n\tunsigned int phys_erase_shift;\n\tunsigned int chip_shift;\n\tunsigned int pagemask;\n\tunsigned int subpagesize;\n\tu8 *data_buf;\n\tu8 *oob_poi;\n\tstruct {\n\t\tunsigned int bitflips;\n\t\tint page;\n\t} pagecache;\n\tlong unsigned int buf_align;\n\tstruct mutex lock;\n\tunsigned int suspended: 1;\n\twait_queue_head_t resume_wq;\n\tint cur_cs;\n\tint read_retries;\n\tstruct nand_secure_region *secure_regions;\n\tu8 nr_secure_regions;\n\tstruct {\n\t\tbool ongoing;\n\t\tunsigned int first_page;\n\t\tunsigned int pause_page;\n\t\tunsigned int last_page;\n\t} cont_read;\n\tstruct nand_controller *controller;\n\tstruct nand_ecc_ctrl ecc;\n\tvoid *priv;\n};\n\nstruct denali_chip_sel {\n\tint bank;\n\tu32 hwhr2_and_we_2_re;\n\tu32 tcwaw_and_addr_2_data;\n\tu32 re_2_we;\n\tu32 acc_clks;\n\tu32 rdwr_en_lo_cnt;\n\tu32 rdwr_en_hi_cnt;\n\tu32 cs_setup_cnt;\n\tu32 re_2_re;\n};\n\nstruct denali_chip {\n\tstruct nand_chip chip;\n\tstruct list_head node;\n\tunsigned int nsels;\n\tstruct denali_chip_sel sels[0];\n};\n\nstruct nand_ecc_caps;\n\nstruct denali_controller {\n\tstruct nand_controller controller;\n\tstruct device *dev;\n\tstruct list_head chips;\n\tlong unsigned int clk_rate;\n\tlong unsigned int clk_x_rate;\n\tvoid *reg;\n\tvoid *host;\n\tstruct completion complete;\n\tint irq;\n\tu32 irq_mask;\n\tu32 irq_status;\n\tspinlock_t irq_lock;\n\tbool dma_avail;\n\tint devs_per_cs;\n\tint oob_skip_bytes;\n\tint active_bank;\n\tint nbanks;\n\tunsigned int revision;\n\tunsigned int caps;\n\tconst struct nand_ecc_caps *ecc_caps;\n\tu32 (*host_read)(struct denali_controller *, u32);\n\tvoid (*host_write)(struct denali_controller *, u32, u32);\n\tvoid (*setup_dma)(struct denali_controller *, dma_addr_t, int, bool);\n};\n\nstruct denali_dt {\n\tstruct denali_controller controller;\n\tstruct clk *clk;\n\tstruct clk *clk_x;\n\tstruct clk *clk_ecc;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_reg;\n};\n\nstruct denali_dt_data {\n\tunsigned int revision;\n\tunsigned int caps;\n\tunsigned int oob_skip_bytes;\n\tconst struct nand_ecc_caps *ecc_caps;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nunion shortname_store {\n\tunsigned char string[40];\n\tlong unsigned int words[5];\n};\n\nstruct lockref {\n\tunion {\n\t\t__u64 lock_count;\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_info_args {\n\tint parent_ino;\n\tint dname_len;\n\tint ino;\n\tint inode_len;\n\tchar *dname;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 64;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct desc_info {\n\tstruct dma_async_tx_descriptor *dma_desc;\n\tstruct list_head node;\n\tunion {\n\t\tstruct scatterlist adm_sgl;\n\t\tstruct {\n\t\t\tstruct scatterlist *bam_sgl;\n\t\t\tint sgl_cnt;\n\t\t};\n\t};\n\tenum dma_data_direction dir;\n};\n\nstruct desc_match {\n\tu64 ipa;\n\tint level;\n};\n\nunion desc_value {\n\t__le64 word;\n\tstruct {\n\t\t__le32 low;\n\t\t__le32 high;\n\t} u;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct dev_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head exceptions;\n\tenum devcg_behavior behavior;\n};\n\nstruct dev_exception_item {\n\tu32 major;\n\tu32 minor;\n\tshort int type;\n\tshort int access;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n\tu32 max_pasids;\n\tu32 attach_deferred: 1;\n\tu32 pci_32bit_workaround: 1;\n\tu32 require_direct: 1;\n\tu32 shadow_on_flush: 1;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct dev_pin_info {\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *default_state;\n\tstruct pinctrl_state *init_state;\n\tstruct pinctrl_state *sleep_state;\n\tstruct pinctrl_state *idle_state;\n};\n\nstruct dev_pm_domain_attach_data {\n\tconst char * const *pd_names;\n\tconst u32 num_pd_names;\n\tconst u32 pd_flags;\n};\n\nstruct dev_pm_domain_list {\n\tstruct device **pd_devs;\n\tstruct device_link **pd_links;\n\tu32 *opp_tokens;\n\tu32 num_pds;\n};\n\nstruct dev_pm_opp_supply;\n\nstruct dev_pm_opp_icc_bw;\n\nstruct dev_pm_opp {\n\tstruct list_head node;\n\tstruct kref kref;\n\tbool available;\n\tbool dynamic;\n\tbool turbo;\n\tbool suspend;\n\tbool removed;\n\tlong unsigned int *rates;\n\tunsigned int level;\n\tstruct dev_pm_opp_supply *supplies;\n\tstruct dev_pm_opp_icc_bw *bandwidth;\n\tlong unsigned int clock_latency_ns;\n\tstruct dev_pm_opp **required_opps;\n\tstruct opp_table *opp_table;\n\tstruct device_node *np;\n\tstruct dentry *dentry;\n\tconst char *of_name;\n};\n\ntypedef int (*config_clks_t)(struct device *, struct opp_table *, struct dev_pm_opp *, void *, bool);\n\ntypedef int (*config_regulators_t)(struct device *, struct dev_pm_opp *, struct dev_pm_opp *, struct regulator **, unsigned int);\n\nstruct dev_pm_opp_config {\n\tconst char * const *clk_names;\n\tconfig_clks_t config_clks;\n\tconst char *prop_name;\n\tconfig_regulators_t config_regulators;\n\tconst unsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char * const *regulator_names;\n\tstruct device *required_dev;\n\tunsigned int required_dev_index;\n};\n\nstruct dev_pm_opp_data {\n\tbool turbo;\n\tunsigned int level;\n\tlong unsigned int freq;\n\tlong unsigned int u_volt;\n};\n\nstruct dev_pm_opp_icc_bw {\n\tu32 avg;\n\tu32 peak;\n};\n\nstruct dev_pm_opp_key {\n\tlong unsigned int freq;\n\tunsigned int level;\n\tu32 bw;\n};\n\nstruct dev_pm_opp_supply {\n\tlong unsigned int u_volt;\n\tlong unsigned int u_volt_min;\n\tlong unsigned int u_volt_max;\n\tlong unsigned int u_amp;\n\tlong unsigned int u_watt;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_power_governor {\n\tbool (*system_power_down_ok)(struct dev_pm_domain *);\n\tbool (*power_down_ok)(struct dev_pm_domain *);\n\tbool (*suspend_ok)(struct device *);\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\nstruct dev_pstate_set {\n\t__le16 dev_id;\n\tu8 pstate;\n} __attribute__((packed));\n\nstruct dev_to_host_fis {\n\tu8 fis_type;\n\tu8 flags;\n\tu8 status;\n\tu8 error;\n\tu8 lbal;\n\tunion {\n\t\tu8 lbam;\n\t\tu8 byte_count_low;\n\t};\n\tunion {\n\t\tu8 lbah;\n\t\tu8 byte_count_high;\n\t};\n\tu8 device;\n\tu8 lbal_exp;\n\tu8 lbam_exp;\n\tu8 lbah_exp;\n\tu8 _r_a;\n\tunion {\n\t\tu8 sector_count;\n\t\tu8 interrupt_reason;\n\t};\n\tu8 sector_count_exp;\n\tu8 _r_b;\n\tu8 _r_c;\n\tu32 _r_d;\n};\n\nstruct devcd_entry {\n\tstruct device devcd_dev;\n\tvoid *data;\n\tsize_t datalen;\n\tstruct mutex mutex;\n\tbool init_completed;\n\tbool deleted;\n\tstruct module *owner;\n\tssize_t (*read)(char *, loff_t, size_t, void *, size_t);\n\tvoid (*free)(void *);\n\tstruct delayed_work del_wk;\n\tstruct device *failing_dev;\n};\n\nstruct devfreq_dev_status {\n\tlong unsigned int total_time;\n\tlong unsigned int busy_time;\n\tlong unsigned int current_frequency;\n\tvoid *private_data;\n};\n\nstruct devfreq_stats {\n\tunsigned int total_trans;\n\tunsigned int *trans_table;\n\tu64 *time_in_state;\n\tu64 last_update;\n};\n\nstruct devfreq_dev_profile;\n\nstruct devfreq_governor;\n\nstruct devfreq {\n\tstruct list_head node;\n\tstruct mutex lock;\n\tstruct device dev;\n\tstruct devfreq_dev_profile *profile;\n\tconst struct devfreq_governor *governor;\n\tstruct opp_table *opp_table;\n\tstruct notifier_block nb;\n\tstruct delayed_work work;\n\tlong unsigned int *freq_table;\n\tunsigned int max_state;\n\tlong unsigned int previous_freq;\n\tstruct devfreq_dev_status last_status;\n\tvoid *data;\n\tvoid *governor_data;\n\tstruct dev_pm_qos_request user_min_freq_req;\n\tstruct dev_pm_qos_request user_max_freq_req;\n\tlong unsigned int scaling_min_freq;\n\tlong unsigned int scaling_max_freq;\n\tbool stop_polling;\n\tlong unsigned int suspend_freq;\n\tlong unsigned int resume_freq;\n\tatomic_t suspend_count;\n\tstruct devfreq_stats stats;\n\tstruct srcu_notifier_head transition_notifier_list;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct devfreq_cooling_power;\n\nstruct devfreq_cooling_device {\n\tstruct thermal_cooling_device *cdev;\n\tstruct thermal_cooling_device_ops cooling_ops;\n\tstruct devfreq *devfreq;\n\tlong unsigned int cooling_state;\n\tu32 *freq_table;\n\tsize_t max_state;\n\tstruct devfreq_cooling_power *power_ops;\n\tu32 res_util;\n\tint capped_state;\n\tstruct dev_pm_qos_request req_max_freq;\n\tstruct em_perf_domain *em_pd;\n};\n\nstruct devfreq_cooling_power {\n\tint (*get_real_power)(struct devfreq *, u32 *, long unsigned int, long unsigned int);\n};\n\nstruct devfreq_dev_profile {\n\tlong unsigned int initial_freq;\n\tunsigned int polling_ms;\n\tenum devfreq_timer timer;\n\tint (*target)(struct device *, long unsigned int *, u32);\n\tint (*get_dev_status)(struct device *, struct devfreq_dev_status *);\n\tint (*get_cur_freq)(struct device *, long unsigned int *);\n\tvoid (*exit)(struct device *);\n\tlong unsigned int *freq_table;\n\tunsigned int max_state;\n\tbool is_cooling_device;\n\tconst struct attribute_group **dev_groups;\n};\n\nstruct devfreq_event_data {\n\tlong unsigned int load_count;\n\tlong unsigned int total_count;\n};\n\nstruct devfreq_event_ops;\n\nstruct devfreq_event_desc {\n\tconst char *name;\n\tu32 event_type;\n\tvoid *driver_data;\n\tconst struct devfreq_event_ops *ops;\n};\n\nstruct devfreq_event_dev {\n\tstruct list_head node;\n\tstruct device dev;\n\tstruct mutex lock;\n\tu32 enable_count;\n\tconst struct devfreq_event_desc *desc;\n};\n\nstruct devfreq_event_ops {\n\tint (*enable)(struct devfreq_event_dev *);\n\tint (*disable)(struct devfreq_event_dev *);\n\tint (*reset)(struct devfreq_event_dev *);\n\tint (*set_event)(struct devfreq_event_dev *);\n\tint (*get_event)(struct devfreq_event_dev *, struct devfreq_event_data *);\n};\n\nstruct devfreq_freqs {\n\tlong unsigned int old;\n\tlong unsigned int new;\n};\n\nstruct devfreq_governor {\n\tstruct list_head node;\n\tconst char name[16];\n\tconst u64 attrs;\n\tconst u64 flags;\n\tint (*get_target_freq)(struct devfreq *, long unsigned int *);\n\tint (*event_handler)(struct devfreq *, unsigned int, void *);\n};\n\nstruct devfreq_notifier_devres {\n\tstruct devfreq *devfreq;\n\tstruct notifier_block *nb;\n\tunsigned int list;\n};\n\nstruct devfreq_passive_data {\n\tstruct devfreq *parent;\n\tint (*get_target_freq)(struct devfreq *, long unsigned int *);\n\tenum devfreq_parent_dev_type parent_type;\n\tstruct devfreq *this;\n\tstruct notifier_block nb;\n\tstruct list_head cpu_data_list;\n};\n\nstruct devfreq_simple_ondemand_data {\n\tunsigned int upthreshold;\n\tunsigned int downdifferential;\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_pm_runtime_active_auto_t;\n\ntypedef class_pm_runtime_active_auto_t class_pm_runtime_active_auto_try_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\ntypedef struct device *class_pm_runtime_noresume_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tstruct kobject kobj;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n};\n\nstruct devlink_dev_stats {\n\tu32 reload_stats[6];\n\tu32 remote_reload_stats[6];\n};\n\nstruct devlink_dpipe_headers;\n\nstruct devlink_ops;\n\nstruct devlink_rel;\n\nstruct devlink {\n\tu32 index;\n\tstruct xarray ports;\n\tstruct list_head rate_list;\n\tstruct list_head sb_list;\n\tstruct list_head dpipe_table_list;\n\tstruct list_head resource_list;\n\tstruct xarray params;\n\tstruct list_head region_list;\n\tstruct list_head reporter_list;\n\tstruct devlink_dpipe_headers *dpipe_headers;\n\tstruct list_head trap_list;\n\tstruct list_head trap_group_list;\n\tstruct list_head trap_policer_list;\n\tstruct list_head linecard_list;\n\tconst struct devlink_ops *ops;\n\tstruct xarray snapshot_ids;\n\tstruct devlink_dev_stats stats;\n\tstruct device *dev;\n\tpossible_net_t _net;\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tu8 reload_failed: 1;\n\trefcount_t refcount;\n\tstruct rcu_work rwork;\n\tstruct devlink_rel *rel;\n\tstruct xarray nested_rels;\n\tchar priv[0];\n};\n\nstruct devlink_dpipe_header;\n\nstruct devlink_dpipe_action {\n\tenum devlink_dpipe_action_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct genl_info;\n\nstruct devlink_dpipe_dump_ctx {\n\tstruct genl_info *info;\n\tenum devlink_command cmd;\n\tstruct sk_buff *skb;\n\tstruct nlattr *nest;\n\tvoid *hdr;\n};\n\nstruct devlink_dpipe_value;\n\nstruct devlink_dpipe_entry {\n\tu64 index;\n\tstruct devlink_dpipe_value *match_values;\n\tunsigned int match_values_count;\n\tstruct devlink_dpipe_value *action_values;\n\tunsigned int action_values_count;\n\tu64 counter;\n\tbool counter_valid;\n};\n\nstruct devlink_dpipe_field {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int bitwidth;\n\tenum devlink_dpipe_field_mapping_type mapping_type;\n};\n\nstruct devlink_dpipe_header {\n\tconst char *name;\n\tunsigned int id;\n\tstruct devlink_dpipe_field *fields;\n\tunsigned int fields_count;\n\tbool global;\n};\n\nstruct devlink_dpipe_headers {\n\tstruct devlink_dpipe_header **headers;\n\tunsigned int headers_count;\n};\n\nstruct devlink_dpipe_match {\n\tenum devlink_dpipe_match_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct devlink_dpipe_table_ops;\n\nstruct devlink_dpipe_table {\n\tvoid *priv;\n\tstruct list_head list;\n\tconst char *name;\n\tbool counters_enabled;\n\tbool counter_control_extern;\n\tbool resource_valid;\n\tu64 resource_id;\n\tu64 resource_units;\n\tconst struct devlink_dpipe_table_ops *table_ops;\n\tstruct callback_head rcu;\n};\n\nstruct devlink_dpipe_table_ops {\n\tint (*actions_dump)(void *, struct sk_buff *);\n\tint (*matches_dump)(void *, struct sk_buff *);\n\tint (*entries_dump)(void *, bool, struct devlink_dpipe_dump_ctx *);\n\tint (*counters_set_update)(void *, bool);\n\tu64 (*size_get)(void *);\n};\n\nstruct devlink_dpipe_value {\n\tunion {\n\t\tstruct devlink_dpipe_action *action;\n\t\tstruct devlink_dpipe_match *match;\n\t};\n\tunsigned int mapping_value;\n\tbool mapping_valid;\n\tunsigned int value_size;\n\tvoid *value;\n\tvoid *mask;\n};\n\nstruct devlink_flash_component_lookup_ctx {\n\tconst char *lookup_name;\n\tbool lookup_name_found;\n};\n\nstruct devlink_flash_notify {\n\tconst char *status_msg;\n\tconst char *component;\n\tlong unsigned int done;\n\tlong unsigned int total;\n\tlong unsigned int timeout;\n};\n\nstruct firmware;\n\nstruct devlink_flash_update_params {\n\tconst struct firmware *fw;\n\tconst char *component;\n\tu32 overwrite_mask;\n};\n\nstruct devlink_fmsg {\n\tstruct list_head item_list;\n\tint err;\n\tbool putting_binary;\n};\n\nstruct devlink_fmsg_item {\n\tstruct list_head list;\n\tint attrtype;\n\tu8 nla_type;\n\tu16 len;\n\tint value[0];\n};\n\nstruct devlink_health_reporter_ops;\n\nstruct devlink_health_reporter {\n\tstruct list_head list;\n\tvoid *priv;\n\tconst struct devlink_health_reporter_ops *ops;\n\tstruct devlink *devlink;\n\tstruct devlink_port *devlink_port;\n\tstruct devlink_fmsg *dump_fmsg;\n\tu64 graceful_period;\n\tu64 burst_period;\n\tbool auto_recover;\n\tbool auto_dump;\n\tu8 health_state;\n\tu64 dump_ts;\n\tu64 dump_real_ts;\n\tu64 error_count;\n\tu64 recovery_count;\n\tu64 last_recovery_ts;\n};\n\nstruct devlink_health_reporter_ops {\n\tchar *name;\n\tint (*recover)(struct devlink_health_reporter *, void *, struct netlink_ext_ack *);\n\tint (*dump)(struct devlink_health_reporter *, struct devlink_fmsg *, void *, struct netlink_ext_ack *);\n\tint (*diagnose)(struct devlink_health_reporter *, struct devlink_fmsg *, struct netlink_ext_ack *);\n\tint (*test)(struct devlink_health_reporter *, struct netlink_ext_ack *);\n\tu64 default_graceful_period;\n\tu64 default_burst_period;\n};\n\nstruct devlink_info_req {\n\tstruct sk_buff *msg;\n\tvoid (*version_cb)(const char *, enum devlink_info_version_type, void *);\n\tvoid *version_cb_priv;\n};\n\nstruct devlink_linecard_ops;\n\nstruct devlink_linecard_type;\n\nstruct devlink_linecard {\n\tstruct list_head list;\n\tstruct devlink *devlink;\n\tunsigned int index;\n\tconst struct devlink_linecard_ops *ops;\n\tvoid *priv;\n\tenum devlink_linecard_state state;\n\tstruct mutex state_lock;\n\tconst char *type;\n\tstruct devlink_linecard_type *types;\n\tunsigned int types_count;\n\tu32 rel_index;\n};\n\nstruct devlink_linecard_ops {\n\tint (*provision)(struct devlink_linecard *, void *, const char *, const void *, struct netlink_ext_ack *);\n\tint (*unprovision)(struct devlink_linecard *, void *, struct netlink_ext_ack *);\n\tbool (*same_provision)(struct devlink_linecard *, void *, const char *, const void *);\n\tunsigned int (*types_count)(struct devlink_linecard *, void *);\n\tvoid (*types_get)(struct devlink_linecard *, void *, unsigned int, const char **, const void **);\n};\n\nstruct devlink_linecard_type {\n\tconst char *type;\n\tconst void *priv;\n};\n\nstruct devlink_nl_dump_state {\n\tlong unsigned int instance;\n\tint idx;\n\tunion {\n\t\tstruct {\n\t\t\tu64 start_offset;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dump_ts;\n\t\t};\n\t};\n};\n\nstruct devlink_obj_desc;\n\nstruct devlink_nl_sock_priv {\n\tstruct devlink_obj_desc *flt;\n\tspinlock_t flt_lock;\n};\n\nstruct devlink_obj_desc {\n\tstruct callback_head rcu;\n\tconst char *bus_name;\n\tconst char *dev_name;\n\tunsigned int port_index;\n\tbool port_index_valid;\n\tlong int data[0];\n};\n\nstruct devlink_sb_pool_info;\n\nstruct devlink_trap;\n\nstruct devlink_trap_group;\n\nstruct devlink_trap_policer;\n\nstruct devlink_port_new_attrs;\n\nstruct devlink_ops {\n\tu32 supported_flash_update_params;\n\tlong unsigned int reload_actions;\n\tlong unsigned int reload_limits;\n\tint (*reload_down)(struct devlink *, bool, enum devlink_reload_action, enum devlink_reload_limit, struct netlink_ext_ack *);\n\tint (*reload_up)(struct devlink *, enum devlink_reload_action, enum devlink_reload_limit, u32 *, struct netlink_ext_ack *);\n\tint (*sb_pool_get)(struct devlink *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*sb_pool_set)(struct devlink *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*sb_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *);\n\tint (*sb_port_pool_set)(struct devlink_port *, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_tc_pool_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*sb_tc_pool_bind_set)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_occ_snapshot)(struct devlink *, unsigned int);\n\tint (*sb_occ_max_clear)(struct devlink *, unsigned int);\n\tint (*sb_occ_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *, u32 *);\n\tint (*sb_occ_tc_port_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*eswitch_mode_get)(struct devlink *, u16 *);\n\tint (*eswitch_mode_set)(struct devlink *, u16, struct netlink_ext_ack *);\n\tint (*eswitch_inline_mode_get)(struct devlink *, u8 *);\n\tint (*eswitch_inline_mode_set)(struct devlink *, u8, struct netlink_ext_ack *);\n\tint (*eswitch_encap_mode_get)(struct devlink *, enum devlink_eswitch_encap_mode *);\n\tint (*eswitch_encap_mode_set)(struct devlink *, enum devlink_eswitch_encap_mode, struct netlink_ext_ack *);\n\tint (*info_get)(struct devlink *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*flash_update)(struct devlink *, struct devlink_flash_update_params *, struct netlink_ext_ack *);\n\tint (*trap_init)(struct devlink *, const struct devlink_trap *, void *);\n\tvoid (*trap_fini)(struct devlink *, const struct devlink_trap *, void *);\n\tint (*trap_action_set)(struct devlink *, const struct devlink_trap *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_group_init)(struct devlink *, const struct devlink_trap_group *);\n\tint (*trap_group_set)(struct devlink *, const struct devlink_trap_group *, const struct devlink_trap_policer *, struct netlink_ext_ack *);\n\tint (*trap_group_action_set)(struct devlink *, const struct devlink_trap_group *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_drop_counter_get)(struct devlink *, const struct devlink_trap *, u64 *);\n\tint (*trap_policer_init)(struct devlink *, const struct devlink_trap_policer *);\n\tvoid (*trap_policer_fini)(struct devlink *, const struct devlink_trap_policer *);\n\tint (*trap_policer_set)(struct devlink *, const struct devlink_trap_policer *, u64, u64, struct netlink_ext_ack *);\n\tint (*trap_policer_counter_get)(struct devlink *, const struct devlink_trap_policer *, u64 *);\n\tint (*port_new)(struct devlink *, const struct devlink_port_new_attrs *, struct netlink_ext_ack *, struct devlink_port **);\n\tint (*rate_leaf_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_new)(struct devlink_rate *, void **, struct netlink_ext_ack *);\n\tint (*rate_node_del)(struct devlink_rate *, void *, struct netlink_ext_ack *);\n\tint (*rate_leaf_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tint (*rate_node_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tbool (*selftest_check)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n\tenum devlink_selftest_status (*selftest_run)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n};\n\nstruct devlink_param_gset_ctx;\n\nunion devlink_param_value;\n\nstruct devlink_param {\n\tu32 id;\n\tconst char *name;\n\tbool generic;\n\tenum devlink_param_type type;\n\tlong unsigned int supported_cmodes;\n\tint (*get)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*set)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*validate)(struct devlink *, u32, union devlink_param_value, struct netlink_ext_ack *);\n\tint (*get_default)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*reset_default)(struct devlink *, u32, enum devlink_param_cmode, struct netlink_ext_ack *);\n};\n\nunion devlink_param_value {\n\tu8 vu8;\n\tu16 vu16;\n\tu32 vu32;\n\tu64 vu64;\n\tchar vstr[32];\n\tbool vbool;\n};\n\nstruct devlink_param_gset_ctx {\n\tunion devlink_param_value val;\n\tenum devlink_param_cmode cmode;\n};\n\nstruct devlink_param_item {\n\tstruct list_head list;\n\tconst struct devlink_param *param;\n\tunion devlink_param_value driverinit_value;\n\tbool driverinit_value_valid;\n\tunion devlink_param_value driverinit_value_new;\n\tbool driverinit_value_new_valid;\n\tunion devlink_param_value driverinit_default;\n};\n\nstruct devlink_port_new_attrs {\n\tenum devlink_port_flavour flavour;\n\tunsigned int port_index;\n\tu32 controller;\n\tu32 sfnum;\n\tu16 pfnum;\n\tu8 port_index_valid: 1;\n\tu8 controller_valid: 1;\n\tu8 sfnum_valid: 1;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_port_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n};\n\nstruct devlink_region_ops;\n\nstruct devlink_region {\n\tstruct devlink *devlink;\n\tstruct devlink_port *port;\n\tstruct list_head list;\n\tunion {\n\t\tconst struct devlink_region_ops *ops;\n\t\tconst struct devlink_port_region_ops *port_ops;\n\t};\n\tstruct mutex snapshot_lock;\n\tstruct list_head snapshot_list;\n\tu32 max_snapshots;\n\tu32 cur_snapshots;\n\tu64 size;\n};\n\nstruct devlink_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\ntypedef void devlink_rel_notify_cb_t(struct devlink *, u32);\n\ntypedef void devlink_rel_cleanup_cb_t(struct devlink *, u32, u32);\n\nstruct devlink_rel {\n\tu32 index;\n\trefcount_t refcount;\n\tu32 devlink_index;\n\tstruct {\n\t\tu32 devlink_index;\n\t\tu32 obj_index;\n\t\tdevlink_rel_notify_cb_t *notify_cb;\n\t\tdevlink_rel_cleanup_cb_t *cleanup_cb;\n\t\tstruct delayed_work notify_work;\n\t} nested_in;\n};\n\nstruct devlink_reload_combination {\n\tenum devlink_reload_action action;\n\tenum devlink_reload_limit limit;\n};\n\nstruct devlink_resource_size_params {\n\tu64 size_min;\n\tu64 size_max;\n\tu64 size_granularity;\n\tenum devlink_resource_unit unit;\n};\n\ntypedef u64 devlink_resource_occ_get_t(void *);\n\nstruct devlink_resource {\n\tconst char *name;\n\tu64 id;\n\tu64 size;\n\tu64 size_new;\n\tbool size_valid;\n\tstruct devlink_resource *parent;\n\tstruct devlink_resource_size_params size_params;\n\tstruct list_head list;\n\tstruct list_head resource_list;\n\tdevlink_resource_occ_get_t *occ_get;\n\tvoid *occ_get_priv;\n};\n\nstruct devlink_sb {\n\tstruct list_head list;\n\tunsigned int index;\n\tu32 size;\n\tu16 ingress_pools_count;\n\tu16 egress_pools_count;\n\tu16 ingress_tc_count;\n\tu16 egress_tc_count;\n};\n\nstruct devlink_sb_pool_info {\n\tenum devlink_sb_pool_type pool_type;\n\tu32 size;\n\tenum devlink_sb_threshold_type threshold_type;\n\tu32 cell_size;\n};\n\nstruct devlink_snapshot {\n\tstruct list_head list;\n\tstruct devlink_region *region;\n\tu8 *data;\n\tu32 id;\n};\n\nstruct devlink_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct devlink_trap {\n\tenum devlink_trap_type type;\n\tenum devlink_trap_action init_action;\n\tbool generic;\n\tu16 id;\n\tconst char *name;\n\tu16 init_group_id;\n\tu32 metadata_cap;\n};\n\nstruct devlink_trap_group {\n\tconst char *name;\n\tu16 id;\n\tbool generic;\n\tu32 init_policer_id;\n};\n\nstruct devlink_trap_policer_item;\n\nstruct devlink_trap_group_item {\n\tconst struct devlink_trap_group *group;\n\tstruct devlink_trap_policer_item *policer_item;\n\tstruct list_head list;\n\tstruct devlink_stats *stats;\n};\n\nstruct devlink_trap_item {\n\tconst struct devlink_trap *trap;\n\tstruct devlink_trap_group_item *group_item;\n\tstruct list_head list;\n\tenum devlink_trap_action action;\n\tstruct devlink_stats *stats;\n\tvoid *priv;\n};\n\nstruct flow_action_cookie;\n\nstruct devlink_trap_metadata {\n\tconst char *trap_name;\n\tconst char *trap_group_name;\n\tstruct net_device *input_dev;\n\tnetdevice_tracker dev_tracker;\n\tconst struct flow_action_cookie *fa_cookie;\n\tenum devlink_trap_type trap_type;\n};\n\nstruct devlink_trap_policer {\n\tu32 id;\n\tu64 init_rate;\n\tu64 init_burst;\n\tu64 max_rate;\n\tu64 min_rate;\n\tu64 max_burst;\n\tu64 min_burst;\n};\n\nstruct devlink_trap_policer_item {\n\tconst struct devlink_trap_policer *policer;\n\tu64 rate;\n\tu64 burst;\n\tstruct list_head list;\n};\n\nstruct devm_clk_state {\n\tstruct clk *clk;\n\tvoid (*exit)(struct clk *);\n};\n\nstruct of_regulator_match;\n\nstruct devm_of_regulator_matches {\n\tstruct of_regulator_match *matches;\n\tunsigned int num_matches;\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nstruct dfll_fcpu_data {\n\tconst long unsigned int *cpu_max_freq_table;\n\tunsigned int cpu_max_freq_table_size;\n\tconst struct cvb_table *cpu_cvb_tables;\n\tunsigned int cpu_cvb_tables_size;\n};\n\nstruct dfll_rate_req {\n\tlong unsigned int rate;\n\tlong unsigned int dvco_target_rate;\n\tint lut_index;\n\tu8 mult_bits;\n\tu8 scale_bits;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\nstruct dimm_info {\n\tstruct device dev;\n\tchar label[32];\n\tunsigned int location[3];\n\tstruct mem_ctl_info *mci;\n\tunsigned int idx;\n\tu32 grain;\n\tenum dev_type dtype;\n\tenum mem_type mtype;\n\tenum edac_type edac_mode;\n\tu32 nr_pages;\n\tunsigned int csrow;\n\tunsigned int cschannel;\n\tu16 smbios_handle;\n\tu32 ce_count;\n\tu32 ue_count;\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\nstruct dio {\n\tint flags;\n\tblk_opf_t opf;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tbool is_pinned;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 64;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n\tu64 cookie;\n\tbool initialized;\n};\n\nstruct wb_domain;\n\nstruct dirty_throttle_control {\n\tstruct wb_domain *dom;\n\tstruct dirty_throttle_control *gdtc;\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct discover_resp {\n\tu8 _r_a[5];\n\tu8 phy_id;\n\t__be16 _r_b;\n\tu8 _r_c: 4;\n\tu8 attached_dev_type: 3;\n\tu8 _r_d: 1;\n\tu8 linkrate: 4;\n\tu8 _r_e: 4;\n\tu8 attached_sata_host: 1;\n\tu8 iproto: 3;\n\tu8 _r_f: 4;\n\tu8 attached_sata_dev: 1;\n\tu8 tproto: 3;\n\tu8 _r_g: 3;\n\tu8 attached_sata_ps: 1;\n\tu8 sas_addr[8];\n\tu8 attached_sas_addr[8];\n\tu8 attached_phy_id;\n\tu8 _r_h[7];\n\tu8 hmin_linkrate: 4;\n\tu8 pmin_linkrate: 4;\n\tu8 hmax_linkrate: 4;\n\tu8 pmax_linkrate: 4;\n\tu8 change_count;\n\tu8 pptv: 4;\n\tu8 _r_i: 3;\n\tu8 virtual: 1;\n\tu8 routing_attr: 4;\n\tu8 _r_j: 4;\n\tu8 conn_type;\n\tu8 conn_el_index;\n\tu8 conn_phy_link;\n\tu8 _r_k[8];\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct timing_entry {\n\tu32 min;\n\tu32 typ;\n\tu32 max;\n};\n\nstruct display_timing {\n\tstruct timing_entry pixelclock;\n\tstruct timing_entry hactive;\n\tstruct timing_entry hfront_porch;\n\tstruct timing_entry hback_porch;\n\tstruct timing_entry hsync_len;\n\tstruct timing_entry vactive;\n\tstruct timing_entry vfront_porch;\n\tstruct timing_entry vback_porch;\n\tstruct timing_entry vsync_len;\n\tenum display_flags flags;\n};\n\nstruct display_timings {\n\tunsigned int num_timings;\n\tunsigned int native_mode;\n\tstruct display_timing **timings;\n};\n\nstruct div6_clock {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tunsigned int div;\n\tu32 src_mask;\n\tstruct notifier_block nb;\n\tu8 parents[0];\n};\n\nstruct div_hw_data {\n\tstruct clk_hw_data hw_data;\n\tconst struct clk_div_table *dtable;\n\tlong unsigned int invalid_rate;\n\tlong unsigned int max_rate;\n\tu32 width;\n};\n\nstruct div_nmp {\n\tu8 divn_shift;\n\tu8 divn_width;\n\tu8 divm_shift;\n\tu8 divm_width;\n\tu8 divp_shift;\n\tu8 divp_width;\n\tu8 override_divn_shift;\n\tu8 override_divm_shift;\n\tu8 override_divp_shift;\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\nstruct dm_kobject_holder {\n\tstruct kobject kobj;\n\tstruct completion completion;\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_resv;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct dma_iova_state;\n\nstruct dma_buf_dma {\n\tstruct sg_table sgt;\n\tstruct dma_iova_state *state;\n\tsize_t size;\n};\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct dma_buf_export_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_import_sync_file {\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_buf_sg_table_wrapper {\n\tstruct sg_table *original;\n\tstruct sg_table wrapper;\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan *chan;\n\tstruct device device;\n\tint dev_id;\n\tbool chan_dma_dev;\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_chan_tbl_ent {\n\tstruct dma_chan *chan;\n};\n\nstruct dma_channel {\n\tvoid *private_data;\n\tsize_t max_len;\n\tsize_t actual_len;\n\tenum dma_channel_status status;\n\tbool desired_mode;\n\tbool rx_packet_done;\n};\n\nstruct dma_coherent_mem {\n\tvoid *virt_base;\n\tdma_addr_t device_base;\n\tlong unsigned int pfn_base;\n\tint size;\n\tlong unsigned int *bitmap;\n\tspinlock_t spinlock;\n\tbool use_dev_dma_pfn_offset;\n};\n\nstruct musb;\n\nstruct musb_hw_ep;\n\nstruct dma_controller {\n\tstruct musb *musb;\n\tstruct dma_channel * (*channel_alloc)(struct dma_controller *, struct musb_hw_ep *, u8);\n\tvoid (*channel_release)(struct dma_channel *);\n\tint (*channel_program)(struct dma_channel *, u16, u8, dma_addr_t, u32);\n\tint (*channel_abort)(struct dma_channel *);\n\tint (*is_compatible)(struct dma_channel *, u16, void *, u32);\n\tvoid (*dma_callback)(struct dma_controller *);\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n};\n\nstruct dma_fence_array;\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n\tstruct dma_fence_array_cb callbacks[0];\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tstruct dma_fence *prev;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tunion {\n\t\tstruct dma_fence_cb cb;\n\t\tstruct irq_work work;\n\t};\n\tspinlock_t lock;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_fence_unwrap {\n\tstruct dma_fence *chain;\n\tstruct dma_fence *array;\n\tunsigned int index;\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct pl330_dmac;\n\nstruct pl330_thread;\n\nstruct dma_pl330_chan {\n\tstruct tasklet_struct task;\n\tstruct dma_chan chan;\n\tstruct list_head submitted_list;\n\tstruct list_head work_list;\n\tstruct list_head completed_list;\n\tstruct pl330_dmac *dmac;\n\tspinlock_t lock;\n\tstruct pl330_thread *thread;\n\tint burst_sz;\n\tint burst_len;\n\tphys_addr_t fifo_addr;\n\tdma_addr_t fifo_dma;\n\tenum dma_data_direction dir;\n\tstruct dma_slave_config slave_config;\n\tbool cyclic;\n\tbool active;\n};\n\nstruct pl330_xfer {\n\tu32 src_addr;\n\tu32 dst_addr;\n\tu32 bytes;\n};\n\nstruct pl330_config;\n\nstruct pl330_reqcfg {\n\tunsigned int dst_inc: 1;\n\tunsigned int src_inc: 1;\n\tbool nonsecure;\n\tbool privileged;\n\tbool insnaccess;\n\tunsigned int brst_len: 5;\n\tunsigned int brst_size: 3;\n\tenum pl330_cachectrl dcctl;\n\tenum pl330_cachectrl scctl;\n\tenum pl330_byteswap swap;\n\tstruct pl330_config *pcfg;\n};\n\nstruct dma_pl330_desc {\n\tstruct list_head node;\n\tstruct dma_async_tx_descriptor txd;\n\tstruct pl330_xfer px;\n\tstruct pl330_reqcfg rqcfg;\n\tenum desc_status status;\n\tint bytes_requested;\n\tbool last;\n\tstruct dma_pl330_chan *pchan;\n\tenum dma_transfer_direction rqtype;\n\tunsigned int peri: 5;\n\tstruct list_head rqd;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct ww_acquire_ctx;\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tstruct dma_resv_list *fences;\n};\n\nstruct dma_resv_iter {\n\tstruct dma_resv *obj;\n\tenum dma_resv_usage usage;\n\tstruct dma_fence *fence;\n\tenum dma_resv_usage fence_usage;\n\tunsigned int index;\n\tstruct dma_resv_list *fences;\n\tunsigned int num_fences;\n\tbool is_restarted;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 num_fences;\n\tu32 max_fences;\n\tstruct dma_fence *table[0];\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_sgt_handle {\n\tstruct sg_table sgt;\n\tstruct page **pages;\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_vec {\n\tdma_addr_t addr;\n\tsize_t len;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct net_devmem_dmabuf_binding;\n\nstruct dmabuf_genpool_chunk_owner {\n\tstruct net_iov_area area;\n\tstruct net_devmem_dmabuf_binding *binding;\n\tdma_addr_t base_dma_addr;\n};\n\nstruct dmabuf_iter_priv {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmac_map {\n\tu64 vf_map;\n\tu64 dmac;\n};\n\nstruct dmaengine_desc_callback {\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n};\n\nstruct dmaengine_unmap_data {\n\tu16 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dmaengine_unmap_pool {\n\tstruct kmem_cache *cache;\n\tconst char *name;\n\tmempool_t *pool;\n\tsize_t size;\n};\n\nstruct dmi_device {\n\tstruct list_head list;\n\tint type;\n\tconst char *name;\n\tvoid *device_data;\n};\n\nstruct dmi_dev_onboard {\n\tstruct dmi_device dev;\n\tint instance;\n\tint segment;\n\tint bus;\n\tint devfn;\n};\n\nstruct dmi_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint field;\n};\n\nstruct dmi_header {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n};\n\nstruct dmi_memdev_info {\n\tconst char *device;\n\tconst char *bank;\n\tu64 size;\n\tu16 handle;\n\tu8 type;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct omap_dm_timer {};\n\nstruct timer_regs {\n\tu32 ocp_cfg;\n\tu32 tidr;\n\tu32 tier;\n\tu32 twer;\n\tu32 tclr;\n\tu32 tcrr;\n\tu32 tldr;\n\tu32 ttrg;\n\tu32 twps;\n\tu32 tmar;\n\tu32 tcar1;\n\tu32 tsicr;\n\tu32 tcar2;\n\tu32 tpir;\n\tu32 tnir;\n\tu32 tcvr;\n\tu32 tocr;\n\tu32 towr;\n};\n\nstruct dmtimer {\n\tstruct omap_dm_timer cookie;\n\tint id;\n\tint irq;\n\tstruct clk *fclk;\n\tvoid *io_base;\n\tint irq_stat;\n\tint irq_ena;\n\tint irq_dis;\n\tvoid *pend;\n\tvoid *func_base;\n\tatomic_t enabled;\n\tunsigned int reserved: 1;\n\tunsigned int posted: 1;\n\tunsigned int omap1: 1;\n\tstruct timer_regs context;\n\tint revision;\n\tu32 capability;\n\tu32 errata;\n\tstruct platform_device *pdev;\n\tstruct list_head node;\n\tstruct notifier_block nb;\n\tstruct notifier_block fclk_nb;\n\tlong unsigned int fclk_rate;\n};\n\nstruct omap_dm_timer_ops;\n\nstruct dmtimer_platform_data {\n\tint (*set_timer_src)(struct platform_device *, int);\n\tu32 timer_capability;\n\tu32 timer_errata;\n\tint (*get_context_loss_count)(struct device *);\n\tconst struct omap_dm_timer_ops *timer_ops;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct do_cleanup_msg {\n\t__le32 version;\n\t__le32 command;\n\t__le32 seq_num;\n\t__le32 name_len;\n\tchar name[32];\n};\n\nstruct dom0_vga_console_info {\n\tuint8_t video_type;\n\tunion {\n\t\tstruct {\n\t\t\tuint16_t font_height;\n\t\t\tuint16_t cursor_x;\n\t\t\tuint16_t cursor_y;\n\t\t\tuint16_t rows;\n\t\t\tuint16_t columns;\n\t\t} text_mode_3;\n\t\tstruct {\n\t\t\tuint16_t width;\n\t\t\tuint16_t height;\n\t\t\tuint16_t bytes_per_line;\n\t\t\tuint16_t bits_per_pixel;\n\t\t\tuint32_t lfb_base;\n\t\t\tuint32_t lfb_size;\n\t\t\tuint8_t red_pos;\n\t\t\tuint8_t red_size;\n\t\t\tuint8_t green_pos;\n\t\t\tuint8_t green_size;\n\t\t\tuint8_t blue_pos;\n\t\t\tuint8_t blue_size;\n\t\t\tuint8_t rsvd_pos;\n\t\t\tuint8_t rsvd_size;\n\t\t\tuint32_t gbl_caps;\n\t\t\tuint16_t mode_attrs;\n\t\t\tuint16_t pad;\n\t\t\tuint32_t ext_lfb_base;\n\t\t} vesa_lfb;\n\t} u;\n};\n\nstruct ex_phy;\n\nstruct expander_device {\n\tstruct list_head children;\n\tint ex_change_count;\n\tu16 max_route_indexes;\n\tu8 num_phys;\n\tu8 t2t_supp: 1;\n\tu8 configuring: 1;\n\tu8 conf_route_table: 1;\n\tu8 enclosure_logical_id[8];\n\tstruct ex_phy *ex_phy;\n\tstruct sas_port *parent_port;\n\tstruct mutex cmd_mutex;\n};\n\nstruct report_phy_sata_resp {\n\tu8 _r_a[5];\n\tu8 phy_id;\n\tu8 _r_b;\n\tu8 affil_valid: 1;\n\tu8 affil_supp: 1;\n\tu8 _r_c: 6;\n\tu32 _r_d;\n\tu8 stp_sas_addr[8];\n\tstruct dev_to_host_fis fis;\n\tu32 _r_e;\n\tu8 affil_stp_ini_addr[8];\n\t__be32 crc;\n};\n\nstruct smp_rps_resp {\n\tu8 frame_type;\n\tu8 function;\n\tu8 result;\n\tu8 reserved;\n\tstruct report_phy_sata_resp rps;\n};\n\nstruct sata_device {\n\tunsigned int class;\n\tu8 port_no;\n\tstruct ata_port *ap;\n\tstruct ata_host *ata_host;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct smp_rps_resp rps_resp;\n\tu8 fis[24];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct ssp_device {\n\tstruct list_head eh_list_node;\n\tstruct scsi_lun reset_lun;\n};\n\nstruct sas_rphy;\n\nstruct domain_device {\n\tspinlock_t done_lock;\n\tenum sas_device_type dev_type;\n\tenum sas_linkrate linkrate;\n\tenum sas_linkrate min_linkrate;\n\tenum sas_linkrate max_linkrate;\n\tint pathways;\n\tstruct domain_device *parent;\n\tstruct list_head siblings;\n\tstruct asd_sas_port *port;\n\tstruct sas_phy *phy;\n\tstruct list_head dev_list_node;\n\tstruct list_head disco_list_node;\n\tenum sas_protocol iproto;\n\tenum sas_protocol tproto;\n\tstruct sas_rphy *rphy;\n\tu8 sas_addr[8];\n\tu8 hashed_sas_addr[3];\n\tu8 frame_rcvd[32];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct expander_device ex_dev;\n\t\tstruct sata_device sata_dev;\n\t\tstruct ssp_device ssp_dev;\n\t};\n\tvoid *lldd_dev;\n\tlong unsigned int state;\n\tstruct kref kref;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dotl_iattr_map {\n\tint iattr_valid;\n\tint p9_iattr_valid;\n};\n\nstruct dotl_openflag_map {\n\tint open_flag;\n\tint dotl_flag;\n};\n\nstruct dp83867_private {\n\tu32 rx_id_delay;\n\tu32 tx_id_delay;\n\tu32 tx_fifo_depth;\n\tu32 rx_fifo_depth;\n\tint io_impedance;\n\tint port_mirroring;\n\tbool rxctrl_strap_quirk;\n\tbool set_clk_output;\n\tu32 clk_output_sel;\n\tbool sgmii_ref_clk_en;\n};\n\nstruct dp83td510_stats {\n\tu64 tx_pkt_cnt;\n\tu64 tx_err_pkt_cnt;\n\tu64 rx_pkt_cnt;\n\tu64 rx_err_pkt_cnt;\n};\n\nstruct dp83td510_priv {\n\tbool alcd_test_active;\n\tstruct dp83td510_stats stats;\n};\n\nstruct dp_sdp_header {\n\tu8 HB0;\n\tu8 HB1;\n\tu8 HB2;\n\tu8 HB3;\n};\n\nstruct dp_sdp {\n\tstruct dp_sdp_header sdp_header;\n\tu8 db[32];\n};\n\nstruct dpaa2_debugfs {\n\tstruct dentry *dir;\n};\n\nstruct dq {\n\tu8 verb;\n\tu8 stat;\n\t__le16 seqnum;\n\t__le16 oprid;\n\tu8 reserved;\n\tu8 tok;\n\t__le32 fqid;\n\tu32 reserved2;\n\t__le32 fq_byte_cnt;\n\t__le32 fq_frm_cnt;\n\t__le64 fqd_ctx;\n\tu8 fd[32];\n};\n\nstruct scn {\n\tu8 verb;\n\tu8 stat;\n\tu8 state;\n\tu8 reserved;\n\t__le32 rid_tok;\n\t__le64 ctx;\n};\n\nstruct dpaa2_dq {\n\tunion {\n\t\tstruct common common;\n\t\tstruct dq dq;\n\t\tstruct scn scn;\n\t};\n};\n\nstruct fsl_mc_device;\n\nstruct dpaa2_eth_bp {\n\tstruct fsl_mc_device *dev;\n\tint bpid;\n};\n\nstruct dpaa2_eth_ch_stats {\n\t__u64 dequeue_portal_busy;\n\t__u64 pull_err;\n\t__u64 cdan;\n\t__u64 xdp_drop;\n\t__u64 xdp_tx;\n\t__u64 xdp_tx_err;\n\t__u64 xdp_redirect;\n\t__u64 frames;\n\t__u64 frames_per_cdan;\n\t__u64 bytes_per_cdan;\n};\n\nstruct dpaa2_eth_ch_xdp {\n\tstruct bpf_prog *prog;\n\tunsigned int res;\n};\n\nstruct dpaa2_io_notification_ctx {\n\tvoid (*cb)(struct dpaa2_io_notification_ctx *);\n\tint is_cdan;\n\tu32 id;\n\tint desired_cpu;\n\tint dpio_id;\n\tu64 qman64;\n\tstruct list_head node;\n\tvoid *dpio_private;\n};\n\nstruct dpaa2_io;\n\nstruct dpaa2_io_store;\n\nstruct dpaa2_eth_priv;\n\nstruct xsk_buff_pool;\n\nstruct dpaa2_eth_channel {\n\tstruct dpaa2_io_notification_ctx nctx;\n\tstruct fsl_mc_device *dpcon;\n\tint dpcon_id;\n\tint ch_id;\n\tstruct napi_struct napi;\n\tstruct dpaa2_io *dpio;\n\tstruct dpaa2_io_store *store;\n\tstruct dpaa2_eth_priv *priv;\n\tint buf_count;\n\tstruct dpaa2_eth_ch_stats stats;\n\tstruct dpaa2_eth_ch_xdp xdp;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct list_head *rx_list;\n\tu64 recycled_bufs[7];\n\tint recycled_bufs_cnt;\n\tbool xsk_zc;\n\tint xsk_tx_pkts_sent;\n\tstruct xsk_buff_pool *xsk_pool;\n\tstruct dpaa2_eth_bp *bp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dpaa2_eth_cls_rule {\n\tstruct ethtool_rx_flow_spec fs;\n\tu8 in_use;\n};\n\nstruct dpaa2_eth_devlink_priv {\n\tstruct dpaa2_eth_priv *dpaa2_priv;\n};\n\nstruct dpaa2_eth_dist_fields {\n\tu64 rxnfc_field;\n\tenum net_prot cls_prot;\n\tint cls_field;\n\tint size;\n\tu64 id;\n};\n\nstruct dpaa2_eth_drv_stats {\n\t__u64 tx_conf_frames;\n\t__u64 tx_conf_bytes;\n\t__u64 tx_sg_frames;\n\t__u64 tx_sg_bytes;\n\t__u64 tx_tso_frames;\n\t__u64 tx_tso_bytes;\n\t__u64 rx_sg_frames;\n\t__u64 rx_sg_bytes;\n\t__u64 tx_converted_sg_frames;\n\t__u64 tx_converted_sg_bytes;\n\t__u64 tx_portal_busy;\n};\n\nstruct dpaa2_fd_simple {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 bpid;\n\t__le16 format_offset;\n\t__le32 frc;\n\t__le32 ctrl;\n\t__le64 flc;\n};\n\nstruct dpaa2_fd {\n\tunion {\n\t\tu32 words[8];\n\t\tstruct dpaa2_fd_simple simple;\n\t};\n};\n\nstruct dpaa2_eth_fds {\n\tstruct dpaa2_fd array[256];\n};\n\nstruct dpaa2_eth_fq;\n\ntypedef void dpaa2_eth_consume_cb_t(struct dpaa2_eth_priv *, struct dpaa2_eth_channel *, const struct dpaa2_fd *, struct dpaa2_eth_fq *);\n\nstruct dpaa2_eth_fq_stats {\n\t__u64 frames;\n};\n\nstruct dpaa2_eth_xdp_fds {\n\tstruct dpaa2_fd fds[16];\n\tssize_t num;\n};\n\nstruct dpaa2_eth_fq {\n\tu32 fqid;\n\tu32 tx_qdbin;\n\tu32 tx_fqid[8];\n\tu16 flowid;\n\tu8 tc;\n\tint target_cpu;\n\tu32 dq_frames;\n\tu32 dq_bytes;\n\tstruct dpaa2_eth_channel *channel;\n\tenum dpaa2_eth_fq_type type;\n\tdpaa2_eth_consume_cb_t *consume;\n\tstruct dpaa2_eth_fq_stats stats;\n\tstruct dpaa2_eth_xdp_fds xdp_redirect_fds;\n\tstruct dpaa2_eth_xdp_fds xdp_tx_fds;\n};\n\nstruct dpni_attr {\n\tu32 options;\n\tu8 num_queues;\n\tu8 num_tcs;\n\tu8 mac_filter_entries;\n\tu8 vlan_filter_entries;\n\tu8 qos_entries;\n\tu16 fs_entries;\n\tu8 qos_key_size;\n\tu8 fs_key_size;\n\tu16 wriop_version;\n};\n\nstruct dpni_link_state {\n\tu32 rate;\n\tu64 options;\n\tint up;\n};\n\nstruct dpaa2_eth_sgt_cache;\n\nstruct fsl_mc_io;\n\nstruct rtnl_link_stats64;\n\nstruct dpaa2_mac;\n\nstruct dpaa2_eth_trap_data;\n\nstruct dpaa2_eth_priv {\n\tstruct net_device *net_dev;\n\tu8 num_fqs;\n\tstruct dpaa2_eth_fq fq[145];\n\tint (*enqueue)(struct dpaa2_eth_priv *, struct dpaa2_eth_fq *, struct dpaa2_fd *, u8, u32, int *);\n\tu8 num_channels;\n\tstruct dpaa2_eth_channel *channel[16];\n\tstruct dpaa2_eth_sgt_cache *sgt_cache;\n\tlong unsigned int features;\n\tstruct dpni_attr dpni_attrs;\n\tu16 dpni_ver_major;\n\tu16 dpni_ver_minor;\n\tu16 tx_data_offset;\n\tvoid *onestep_reg_base;\n\tu8 ptp_correction_off;\n\tvoid (*dpaa2_set_onestep_params_cb)(struct dpaa2_eth_priv *, u32, u8);\n\tu16 rx_buf_size;\n\tstruct iommu_domain *iommu_domain;\n\tenum hwtstamp_tx_types tx_tstamp_type;\n\tbool rx_tstamp;\n\tstruct dpaa2_eth_bp *bp[9];\n\tint num_bps;\n\tu16 tx_qdid;\n\tstruct fsl_mc_io *mc_io;\n\tstruct cpumask dpio_cpumask;\n\tstruct rtnl_link_stats64 *percpu_stats;\n\tstruct dpaa2_eth_drv_stats *percpu_extras;\n\tu16 mc_token;\n\tu8 rx_fqtd_enabled;\n\tu8 rx_cgtd_enabled;\n\tstruct dpni_link_state link_state;\n\tbool do_link_poll;\n\tstruct task_struct *poll_thread;\n\tu64 rx_hash_fields;\n\tu64 rx_cls_fields;\n\tstruct dpaa2_eth_cls_rule *cls_rules;\n\tu8 rx_cls_enabled;\n\tu8 vlan_cls_enabled;\n\tu8 pfc_enabled;\n\tstruct bpf_prog *xdp_prog;\n\tstruct dpaa2_debugfs dbg;\n\tstruct dpaa2_mac *mac;\n\tstruct mutex mac_lock;\n\tstruct workqueue_struct *dpaa2_ptp_wq;\n\tstruct work_struct tx_onestep_tstamp;\n\tstruct sk_buff_head tx_skbs;\n\tstruct mutex onestep_tstamp_lock;\n\tstruct devlink *devlink;\n\tstruct dpaa2_eth_trap_data *trap_data;\n\tstruct devlink_port devlink_port;\n\tu32 rx_copybreak;\n\tstruct dpaa2_eth_fds *fd;\n};\n\nstruct dpaa2_eth_sgt_cache {\n\tvoid *buf[256];\n\tu16 count;\n};\n\nstruct dpaa2_eth_swa {\n\tenum dpaa2_eth_swa_type type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *skb;\n\t\t\tint sgt_size;\n\t\t} single;\n\t\tstruct {\n\t\t\tstruct sk_buff *skb;\n\t\t\tstruct scatterlist *scl;\n\t\t\tint num_sg;\n\t\t\tint sgt_size;\n\t\t} sg;\n\t\tstruct {\n\t\t\tint dma_size;\n\t\t\tstruct xdp_frame *xdpf;\n\t\t} xdp;\n\t\tstruct {\n\t\t\tstruct xdp_buff *xdp_buff;\n\t\t\tint sgt_size;\n\t\t} xsk;\n\t\tstruct {\n\t\t\tstruct sk_buff *skb;\n\t\t\tint num_sg;\n\t\t\tint sgt_size;\n\t\t\tint is_last_fd;\n\t\t} tso;\n\t};\n};\n\nstruct dpaa2_eth_trap_item;\n\nstruct dpaa2_eth_trap_data {\n\tstruct dpaa2_eth_trap_item *trap_items_arr;\n\tstruct dpaa2_eth_priv *priv;\n};\n\nstruct dpaa2_eth_trap_item {\n\tvoid *trap_ctx;\n};\n\nstruct dpaa2_faead {\n\t__le32 conf_fqid;\n\t__le32 ctrl;\n};\n\nstruct dpaa2_faf_error_bit {\n\tint position;\n\tenum devlink_trap_generic_id trap_id;\n};\n\nstruct dpaa2_fapr {\n\t__le32 faf_lo;\n\t__le16 faf_ext;\n\t__le16 nxt_hdr;\n\t__le64 faf_hi;\n\tu8 last_ethertype_offset;\n\tu8 vlan_tci_offset_n;\n\tu8 vlan_tci_offset_1;\n\tu8 llc_snap_offset;\n\tu8 eth_offset;\n\tu8 ip1_pid_offset;\n\tu8 shim_offset_2;\n\tu8 shim_offset_1;\n\tu8 l5_offset;\n\tu8 l4_offset;\n\tu8 gre_offset;\n\tu8 l3_offset_n;\n\tu8 l3_offset_1;\n\tu8 mpls_offset_n;\n\tu8 mpls_offset_1;\n\tu8 pppoe_offset;\n\t__le16 running_sum;\n\t__le16 gross_running_sum;\n\tu8 ipv6_frag_offset;\n\tu8 nxt_hdr_offset;\n\tu8 routing_hdr_offset_2;\n\tu8 routing_hdr_offset_1;\n\tu8 reserved[5];\n\tu8 ip_proto_offset_n;\n\tu8 nxt_hdr_frag_offset;\n\tu8 parse_error_code;\n};\n\nstruct dpaa2_fas {\n\tu8 reserved;\n\tu8 ppid;\n\t__le16 ifpid;\n\t__le32 status;\n};\n\nstruct dpaa2_io_desc {\n\tint receives_notifications;\n\tint has_8prio;\n\tint cpu;\n\tvoid *regs_cena;\n\tvoid *regs_cinh;\n\tint dpio_id;\n\tu32 qman_version;\n\tu32 qman_clk;\n};\n\nstruct qbman_swp_desc {\n\tvoid *cena_bar;\n\tvoid *cinh_bar;\n\tu32 qman_version;\n\tu32 qman_clk;\n\tu32 qman_256_cycles_per_ns;\n};\n\nstruct qbman_swp;\n\nstruct dpaa2_io {\n\tstruct dpaa2_io_desc dpio_desc;\n\tstruct qbman_swp_desc swp_desc;\n\tstruct qbman_swp *swp;\n\tstruct list_head node;\n\tspinlock_t lock_mgmt_cmd;\n\tspinlock_t lock_notifications;\n\tstruct list_head notifications;\n\tstruct device *dev;\n\tstruct dim rx_dim;\n\tspinlock_t dim_lock;\n\tu16 event_ctr;\n\tu64 bytes;\n\tu64 frames;\n};\n\nstruct dpaa2_io_store {\n\tunsigned int max;\n\tdma_addr_t paddr;\n\tstruct dpaa2_dq *vaddr;\n\tvoid *alloced_addr;\n\tunsigned int idx;\n\tstruct qbman_swp *swp;\n\tstruct device *dev;\n};\n\nstruct dpmac_link_state {\n\tu32 rate;\n\tu64 options;\n\tint up;\n\tint state_valid;\n\tu64 supported;\n\tu64 advertising;\n};\n\nstruct dpmac_attr {\n\tu16 id;\n\tu32 max_rate;\n\tenum dpmac_eth_if eth_if;\n\tenum dpmac_link_type link_type;\n};\n\nstruct phylink_pcs;\n\nstruct dpaa2_mac {\n\tstruct fsl_mc_device *mc_dev;\n\tstruct dpmac_link_state state;\n\tstruct net_device *net_dev;\n\tstruct fsl_mc_io *mc_io;\n\tstruct dpmac_attr attr;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tlong unsigned int features;\n\tstruct phylink_config phylink_config;\n\tstruct phylink *phylink;\n\tphy_interface_t if_mode;\n\tenum dpmac_link_type if_link_type;\n\tstruct phylink_pcs *pcs;\n\tstruct fwnode_handle *fw_node;\n\tstruct phy *serdes_phy;\n};\n\nstruct dpaa2_sg_entry {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 bpid;\n\t__le16 format_offset;\n};\n\nstruct dpaa_priv;\n\nstruct dpaa_bp {\n\tstruct dpaa_priv *priv;\n\tint *percpu_count;\n\tsize_t raw_size;\n\tsize_t size;\n\tu16 config_count;\n\tu8 bpid;\n\tstruct bman_pool *pool;\n\tint (*seed_cb)(struct dpaa_bp *);\n\tvoid (*free_buf_cb)(const struct dpaa_bp *, struct bm_buffer *);\n\trefcount_t refs;\n};\n\nstruct dpaa_buffer_layout {\n\tu16 priv_data_size;\n};\n\nstruct dpaa_ern_cnt {\n\tu64 cg_tdrop;\n\tu64 wred;\n\tu64 err_cond;\n\tu64 early_window;\n\tu64 late_window;\n\tu64 fq_tdrop;\n\tu64 fq_retired;\n\tu64 orp_zero;\n};\n\nstruct mac_device;\n\nstruct dpaa_eth_data {\n\tstruct mac_device *mac_dev;\n\tint mac_hw_id;\n\tint fman_hw_id;\n};\n\nstruct dpaa_eth_swbp {\n\tstruct sk_buff *skb;\n\tstruct xdp_frame *xdpf;\n};\n\nstruct qman_portal;\n\nstruct qman_fq;\n\nstruct qm_dqrr_entry;\n\ntypedef enum qman_cb_dqrr_result (*qman_cb_dqrr)(struct qman_portal *, struct qman_fq *, const struct qm_dqrr_entry *, bool);\n\nunion qm_mr_entry;\n\ntypedef void (*qman_cb_mr)(struct qman_portal *, struct qman_fq *, const union qm_mr_entry *);\n\nstruct qman_fq_cb {\n\tqman_cb_dqrr dqrr;\n\tqman_cb_mr ern;\n\tqman_cb_mr fqs;\n};\n\nstruct qman_fq {\n\tstruct qman_fq_cb cb;\n\tu32 fqid;\n\tu32 idx;\n\tlong unsigned int flags;\n\tenum qman_fq_state state;\n\tint cgr_groupid;\n};\n\nstruct dpaa_fq {\n\tstruct qman_fq fq_base;\n\tstruct list_head list;\n\tstruct net_device *net_dev;\n\tbool init;\n\tu32 fqid;\n\tu32 flags;\n\tu16 channel;\n\tu8 wq;\n\tenum dpaa_fq_type fq_type;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n};\n\nstruct dpaa_fq_cbs {\n\tstruct qman_fq rx_defq;\n\tstruct qman_fq tx_defq;\n\tstruct qman_fq rx_errq;\n\tstruct qman_fq tx_errq;\n\tstruct qman_fq egress_ern;\n};\n\nstruct dpaa_napi_portal {\n\tstruct napi_struct napi;\n\tstruct qman_portal *p;\n\tbool down;\n\tint xdp_act;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct dpaa_rx_errors {\n\tu64 dme;\n\tu64 fpe;\n\tu64 fse;\n\tu64 phe;\n};\n\nstruct dpaa_percpu_priv {\n\tstruct net_device *net_dev;\n\tstruct dpaa_napi_portal np;\n\tu64 in_interrupt;\n\tu64 tx_confirm;\n\tu64 tx_frag_skbuffs;\n\tstruct rtnl_link_stats64 stats;\n\tstruct dpaa_rx_errors rx_errors;\n\tstruct dpaa_ern_cnt ern_cnt;\n};\n\nstruct qman_cgr;\n\ntypedef void (*qman_cb_cgr)(struct qman_portal *, struct qman_cgr *, int);\n\nstruct qman_cgr {\n\tu32 cgrid;\n\tqman_cb_cgr cb;\n\tu16 chan;\n\tstruct list_head node;\n};\n\nstruct mac_device___2;\n\nstruct dpaa_priv {\n\tstruct dpaa_percpu_priv *percpu_priv;\n\tstruct dpaa_bp *dpaa_bp;\n\tu16 tx_headroom;\n\tstruct net_device *net_dev;\n\tstruct mac_device___2 *mac_dev;\n\tstruct device *rx_dma_dev;\n\tstruct device *tx_dma_dev;\n\tstruct qman_fq **egress_fqs;\n\tstruct qman_fq **conf_fqs;\n\tu16 channel;\n\tstruct list_head dpaa_fq_list;\n\tu8 num_tc;\n\tbool keygen_in_use;\n\tu32 msg_enable;\n\tstruct {\n\t\tstruct qman_cgr cgr;\n\t\tu32 congestion_start_jiffies;\n\t\tu32 congested_jiffies;\n\t\tu32 cgr_congested_count;\n\t} cgr_data;\n\tbool use_ingress_cgr;\n\tstruct qman_cgr ingress_cgr;\n\tstruct dpaa_buffer_layout buf_layout[2];\n\tu16 rx_headroom;\n\tbool tx_tstamp;\n\tbool rx_tstamp;\n\tstruct bpf_prog *xdp_prog;\n};\n\nstruct dpbp_attr {\n\tint id;\n\tu16 bpid;\n};\n\nstruct dpbp_cmd_open {\n\t__le32 dpbp_id;\n};\n\nstruct dpbp_rsp_get_attributes {\n\t__le16 pad;\n\t__le16 bpid;\n\t__le32 id;\n\t__le16 version_major;\n\t__le16 version_minor;\n};\n\nstruct dpcon_attr {\n\tint id;\n\tu16 qbman_ch_id;\n\tu8 num_priorities;\n};\n\nstruct dpcon_cmd_open {\n\t__le32 dpcon_id;\n};\n\nstruct dpcon_cmd_set_notification {\n\t__le32 dpio_id;\n\tu8 priority;\n\tu8 pad[3];\n\t__le64 user_ctx;\n};\n\nstruct dpcon_notification_cfg {\n\tint dpio_id;\n\tu8 priority;\n\tu64 user_ctx;\n};\n\nstruct dpcon_rsp_get_attr {\n\t__le32 id;\n\t__le16 qbman_ch_id;\n\tu8 num_priorities;\n\tu8 pad;\n};\n\nstruct dpfe_api {\n\tint version;\n\tconst char *fw_name;\n\tconst struct attribute_group **sysfs_attrs;\n\tu32 command[48];\n};\n\nstruct dpfe_firmware_header {\n\tu32 magic;\n\tu32 sequence;\n\tu32 version;\n\tu32 imem_size;\n\tu32 dmem_size;\n};\n\nstruct dpio_attr {\n\tint id;\n\tu64 qbman_portal_ce_offset;\n\tu64 qbman_portal_ci_offset;\n\tu16 qbman_portal_id;\n\tenum dpio_channel_mode channel_mode;\n\tu8 num_priorities;\n\tu32 qbman_version;\n\tu32 clk;\n};\n\nstruct dpio_cmd_open {\n\t__le32 dpio_id;\n};\n\nstruct dpio_priv {\n\tstruct dpaa2_io *io;\n};\n\nstruct dpio_rsp_get_attr {\n\t__le32 id;\n\t__le16 qbman_portal_id;\n\tu8 num_priorities;\n\tu8 channel_mode;\n\t__le64 qbman_portal_ce_addr;\n\t__le64 qbman_portal_ci_addr;\n\t__le32 qbman_version;\n\t__le32 pad1;\n\t__le32 clk;\n};\n\nstruct dpio_stashing_dest {\n\tu8 sdest;\n};\n\nstruct dpkg_mask {\n\tu8 mask;\n\tu8 offset;\n};\n\nstruct dpkg_extract {\n\tenum dpkg_extract_type type;\n\tunion {\n\t\tstruct {\n\t\t\tenum net_prot prot;\n\t\t\tenum dpkg_extract_from_hdr_type type;\n\t\t\tu32 field;\n\t\t\tu8 size;\n\t\t\tu8 offset;\n\t\t\tu8 hdr_index;\n\t\t} from_hdr;\n\t\tstruct {\n\t\t\tu8 size;\n\t\t\tu8 offset;\n\t\t} from_data;\n\t\tstruct {\n\t\t\tu8 size;\n\t\t\tu8 offset;\n\t\t} from_parse;\n\t} extract;\n\tu8 num_of_byte_masks;\n\tstruct dpkg_mask masks[4];\n};\n\nstruct dpkg_profile_cfg {\n\tu8 num_extracts;\n\tstruct dpkg_extract extracts[10];\n};\n\nstruct dpmac_cmd_get_counter {\n\tu8 id;\n};\n\nstruct dpmac_cmd_open {\n\t__le32 dpmac_id;\n};\n\nstruct dpmac_cmd_set_link_state {\n\t__le64 options;\n\t__le32 rate;\n\t__le32 pad0;\n\tu8 state;\n\tu8 pad1[7];\n\t__le64 supported;\n\t__le64 advertising;\n};\n\nstruct dpmac_cmd_set_protocol {\n\tu8 eth_if;\n};\n\nstruct dpmac_rsp_get_api_version {\n\t__le16 major;\n\t__le16 minor;\n};\n\nstruct dpmac_rsp_get_attributes {\n\tu8 eth_if;\n\tu8 link_type;\n\t__le16 id;\n\t__le32 max_rate;\n};\n\nstruct dpmac_rsp_get_counter {\n\t__le64 pad;\n\t__le64 counter;\n};\n\nstruct dpmcp_cmd_open {\n\t__le32 dpmcp_id;\n};\n\nstruct dpmng_rsp_get_version {\n\t__le32 revision;\n\t__le32 version_major;\n\t__le32 version_minor;\n};\n\nstruct dpni_buffer_layout {\n\tu32 options;\n\tint pass_timestamp;\n\tint pass_parser_result;\n\tint pass_frame_status;\n\tu16 private_data_size;\n\tu16 data_align;\n\tu16 data_head_room;\n\tu16 data_tail_room;\n};\n\nstruct dpni_cmd_add_fs_entry {\n\t__le16 options;\n\tu8 tc_id;\n\tu8 key_size;\n\t__le16 index;\n\t__le16 flow_id;\n\t__le64 key_iova;\n\t__le64 mask_iova;\n\t__le64 flc;\n};\n\nstruct dpni_cmd_add_mac_addr {\n\t__le16 pad;\n\tu8 mac_addr[6];\n};\n\nstruct dpni_cmd_add_qos_entry {\n\t__le16 pad;\n\tu8 tc_id;\n\tu8 key_size;\n\t__le16 index;\n\t__le16 pad1;\n\t__le64 key_iova;\n\t__le64 mask_iova;\n};\n\nstruct dpni_cmd_clear_irq_status {\n\t__le32 status;\n\tu8 irq_index;\n};\n\nstruct dpni_cmd_clear_mac_filters {\n\tu8 flags;\n};\n\nstruct dpni_cmd_enable_vlan_filter {\n\tu8 en;\n};\n\nstruct dpni_cmd_get_buffer_layout {\n\tu8 qtype;\n};\n\nstruct dpni_cmd_get_irq_enable {\n\t__le32 pad;\n\tu8 irq_index;\n};\n\nstruct dpni_cmd_get_irq_mask {\n\t__le32 pad;\n\tu8 irq_index;\n};\n\nstruct dpni_cmd_get_irq_status {\n\t__le32 status;\n\tu8 irq_index;\n};\n\nstruct dpni_cmd_get_offload {\n\tu8 pad[3];\n\tu8 dpni_offload;\n};\n\nstruct dpni_cmd_get_qdid {\n\tu8 qtype;\n};\n\nstruct dpni_cmd_get_queue {\n\tu8 qtype;\n\tu8 tc;\n\tu8 index;\n};\n\nstruct dpni_cmd_get_statistics {\n\tu8 page_number;\n};\n\nstruct dpni_cmd_get_taildrop {\n\tu8 congestion_point;\n\tu8 qtype;\n\tu8 tc;\n\tu8 index;\n};\n\nstruct dpni_cmd_link_cfg {\n\t__le64 pad0;\n\t__le32 rate;\n\t__le32 pad1;\n\t__le64 options;\n};\n\nstruct dpni_cmd_open {\n\t__le32 dpni_id;\n};\n\nstruct dpni_cmd_pool {\n\t__le16 dpbp_id;\n\tu8 priority_mask;\n\tu8 pad;\n};\n\nstruct dpni_cmd_remove_fs_entry {\n\t__le16 pad0;\n\tu8 tc_id;\n\tu8 key_size;\n\t__le32 pad1;\n\t__le64 key_iova;\n\t__le64 mask_iova;\n};\n\nstruct dpni_cmd_remove_mac_addr {\n\t__le16 pad;\n\tu8 mac_addr[6];\n};\n\nstruct dpni_cmd_remove_qos_entry {\n\tu8 pad[3];\n\tu8 key_size;\n\t__le32 pad1;\n\t__le64 key_iova;\n\t__le64 mask_iova;\n};\n\nstruct dpni_cmd_set_buffer_layout {\n\tu8 qtype;\n\tu8 pad0[3];\n\t__le16 options;\n\tu8 flags;\n\tu8 pad1;\n\t__le16 private_data_size;\n\t__le16 data_align;\n\t__le16 head_room;\n\t__le16 tail_room;\n};\n\nstruct dpni_cmd_set_congestion_notification {\n\tu8 qtype;\n\tu8 tc;\n\tu8 pad[6];\n\t__le32 dest_id;\n\t__le16 notification_mode;\n\tu8 dest_priority;\n\tu8 type_units;\n\t__le64 message_iova;\n\t__le64 message_ctx;\n\t__le32 threshold_entry;\n\t__le32 threshold_exit;\n};\n\nstruct dpni_cmd_set_errors_behavior {\n\t__le32 errors;\n\tu8 flags;\n};\n\nstruct dpni_cmd_set_irq_enable {\n\tu8 enable;\n\tu8 pad[3];\n\tu8 irq_index;\n};\n\nstruct dpni_cmd_set_irq_mask {\n\t__le32 mask;\n\tu8 irq_index;\n};\n\nstruct dpni_cmd_set_max_frame_length {\n\t__le16 max_frame_length;\n};\n\nstruct dpni_cmd_set_multicast_promisc {\n\tu8 enable;\n};\n\nstruct dpni_cmd_set_offload {\n\tu8 pad[3];\n\tu8 dpni_offload;\n\t__le32 config;\n};\n\nstruct dpni_cmd_set_pools {\n\tu8 num_dpbp;\n\tu8 backup_pool_mask;\n\tu8 pad;\n\tu8 pool_options;\n\tstruct dpni_cmd_pool pool[8];\n\t__le16 buffer_size[8];\n};\n\nstruct dpni_cmd_set_primary_mac_addr {\n\t__le16 pad;\n\tu8 mac_addr[6];\n};\n\nstruct dpni_cmd_set_qos_table {\n\t__le32 pad;\n\tu8 default_tc;\n\tu8 discard_on_miss;\n\t__le16 pad1[21];\n\t__le64 key_cfg_iova;\n};\n\nstruct dpni_cmd_set_queue {\n\tu8 qtype;\n\tu8 tc;\n\tu8 index;\n\tu8 options;\n\t__le32 pad0;\n\t__le32 dest_id;\n\t__le16 pad1;\n\tu8 dest_prio;\n\tu8 flags;\n\t__le64 flc;\n\t__le64 user_context;\n};\n\nstruct dpni_cmd_set_rx_fs_dist {\n\t__le16 dist_size;\n\tu8 enable;\n\tu8 tc;\n\t__le16 miss_flow_id;\n\t__le16 pad;\n\t__le64 key_cfg_iova;\n};\n\nstruct dpni_cmd_set_rx_hash_dist {\n\t__le16 dist_size;\n\tu8 enable;\n\tu8 tc;\n\t__le32 pad;\n\t__le64 key_cfg_iova;\n};\n\nstruct dpni_cmd_set_rx_tc_dist {\n\t__le16 dist_size;\n\tu8 tc_id;\n\tu8 flags;\n\t__le16 pad0;\n\t__le16 default_flow_id;\n\t__le64 pad1[5];\n\t__le64 key_cfg_iova;\n};\n\nstruct dpni_cmd_set_taildrop {\n\tu8 congestion_point;\n\tu8 qtype;\n\tu8 tc;\n\tu8 index;\n\t__le32 pad0;\n\tu8 enable;\n\tu8 pad1;\n\tu8 units;\n\tu8 pad2;\n\t__le32 threshold;\n};\n\nstruct dpni_cmd_set_tx_shaping {\n\t__le16 tx_cr_max_burst_size;\n\t__le16 tx_er_max_burst_size;\n\t__le32 pad;\n\t__le32 tx_cr_rate_limit;\n\t__le32 tx_er_rate_limit;\n\tu8 coupled;\n};\n\nstruct dpni_cmd_set_unicast_promisc {\n\tu8 enable;\n};\n\nstruct dpni_cmd_single_step_cfg {\n\t__le16 flags;\n\t__le16 offset;\n\t__le32 peer_delay;\n\t__le32 ptp_onestep_reg_base;\n\t__le32 pad0;\n};\n\nstruct dpni_cmd_vlan_id {\n\tu8 flags;\n\tu8 tc_id;\n\tu8 flow_id;\n\tu8 pad;\n\t__le16 vlan_id;\n};\n\nstruct dpni_dest_cfg {\n\tenum dpni_dest dest_type;\n\tint dest_id;\n\tu8 priority;\n};\n\nstruct dpni_congestion_notification_cfg {\n\tenum dpni_congestion_unit units;\n\tu32 threshold_entry;\n\tu32 threshold_exit;\n\tu64 message_ctx;\n\tu64 message_iova;\n\tstruct dpni_dest_cfg dest_cfg;\n\tu16 notification_mode;\n};\n\nstruct dpni_mask_cfg {\n\tu8 mask;\n\tu8 offset;\n};\n\nstruct dpni_dist_extract {\n\tu8 prot;\n\tu8 efh_type;\n\tu8 size;\n\tu8 offset;\n\t__le32 field;\n\tu8 hdr_index;\n\tu8 constant;\n\tu8 num_of_repeats;\n\tu8 num_of_byte_masks;\n\tu8 extract_type;\n\tu8 pad[3];\n\tstruct dpni_mask_cfg masks[4];\n};\n\nstruct dpni_error_cfg {\n\tu32 errors;\n\tenum dpni_error_action error_action;\n\tint set_frame_annotation;\n};\n\nstruct dpni_ext_set_rx_tc_dist {\n\tu8 num_extracts;\n\tu8 pad[7];\n\tstruct dpni_dist_extract extracts[10];\n};\n\nstruct dpni_fs_action_cfg {\n\tu64 flc;\n\tu16 flow_id;\n\tu16 options;\n};\n\nstruct dpni_fs_tbl_cfg {\n\tenum dpni_fs_miss_action miss_action;\n\tu16 default_flow_id;\n};\n\nstruct dpni_link_cfg {\n\tu32 rate;\n\tu64 options;\n};\n\nstruct dpni_pools_cfg {\n\tu8 num_dpbp;\n\tu8 pool_options;\n\tstruct {\n\t\tint dpbp_id;\n\t\tu8 priority_mask;\n\t\tu16 buffer_size;\n\t\tint backup_pool;\n\t} pools[8];\n};\n\nstruct dpni_qos_tbl_cfg {\n\tu64 key_cfg_iova;\n\tint discard_on_miss;\n\tu8 default_tc;\n};\n\nstruct dpni_queue {\n\tstruct {\n\t\tu16 id;\n\t\tenum dpni_dest type;\n\t\tchar hold_active;\n\t\tu8 priority;\n\t} destination;\n\tu64 user_context;\n\tstruct {\n\t\tu64 value;\n\t\tchar stash_control;\n\t} flc;\n};\n\nstruct dpni_queue_id {\n\tu32 fqid;\n\tu16 qdbin;\n};\n\nstruct dpni_rsp_get_api_version {\n\t__le16 major;\n\t__le16 minor;\n};\n\nstruct dpni_rsp_get_attr {\n\t__le32 options;\n\tu8 num_queues;\n\tu8 num_tcs;\n\tu8 mac_filter_entries;\n\tu8 pad0;\n\tu8 vlan_filter_entries;\n\tu8 pad1;\n\tu8 qos_entries;\n\tu8 pad2;\n\t__le16 fs_entries;\n\t__le16 pad3;\n\tu8 qos_key_size;\n\tu8 fs_key_size;\n\t__le16 wriop_version;\n};\n\nstruct dpni_rsp_get_buffer_layout {\n\tu8 pad0[6];\n\tu8 flags;\n\tu8 pad1;\n\t__le16 private_data_size;\n\t__le16 data_align;\n\t__le16 head_room;\n\t__le16 tail_room;\n};\n\nstruct dpni_rsp_get_irq_enable {\n\tu8 enabled;\n};\n\nstruct dpni_rsp_get_irq_mask {\n\t__le32 mask;\n};\n\nstruct dpni_rsp_get_irq_status {\n\t__le32 status;\n};\n\nstruct dpni_rsp_get_link_state {\n\t__le32 pad0;\n\tu8 flags;\n\tu8 pad1[3];\n\t__le32 rate;\n\t__le32 pad2;\n\t__le64 options;\n};\n\nstruct dpni_rsp_get_max_frame_length {\n\t__le16 max_frame_length;\n};\n\nstruct dpni_rsp_get_multicast_promisc {\n\tu8 enabled;\n};\n\nstruct dpni_rsp_get_offload {\n\t__le32 pad;\n\t__le32 config;\n};\n\nstruct dpni_rsp_get_port_mac_addr {\n\t__le16 pad;\n\tu8 mac_addr[6];\n};\n\nstruct dpni_rsp_get_primary_mac_addr {\n\t__le16 pad;\n\tu8 mac_addr[6];\n};\n\nstruct dpni_rsp_get_qdid {\n\t__le16 qdid;\n};\n\nstruct dpni_rsp_get_queue {\n\t__le64 pad0;\n\t__le32 dest_id;\n\t__le16 pad1;\n\tu8 dest_prio;\n\tu8 flags;\n\t__le64 flc;\n\t__le64 user_context;\n\t__le32 fqid;\n\t__le16 qdbin;\n};\n\nstruct dpni_rsp_get_statistics {\n\t__le64 counter[7];\n};\n\nstruct dpni_rsp_get_taildrop {\n\t__le64 pad0;\n\tu8 enable;\n\tu8 pad1;\n\tu8 units;\n\tu8 pad2;\n\t__le32 threshold;\n};\n\nstruct dpni_rsp_get_tx_data_offset {\n\t__le16 data_offset;\n};\n\nstruct dpni_rsp_get_unicast_promisc {\n\tu8 enabled;\n};\n\nstruct dpni_rsp_is_enabled {\n\tu8 enabled;\n};\n\nstruct dpni_rsp_single_step_cfg {\n\t__le16 flags;\n\t__le16 offset;\n\t__le32 peer_delay;\n\t__le32 ptp_onestep_reg_base;\n\t__le32 pad0;\n};\n\nstruct dpni_rule_cfg {\n\tu64 key_iova;\n\tu64 mask_iova;\n\tu8 key_size;\n};\n\nstruct dpni_rx_dist_cfg {\n\tu16 dist_size;\n\tu64 key_cfg_iova;\n\tu8 enable;\n\tu8 tc;\n\tu16 fs_miss_flow_id;\n};\n\nstruct dpni_rx_tc_dist_cfg {\n\tu16 dist_size;\n\tenum dpni_dist_mode dist_mode;\n\tu64 key_cfg_iova;\n\tstruct dpni_fs_tbl_cfg fs_cfg;\n};\n\nstruct dpni_single_step_cfg {\n\tu8 en;\n\tu8 ch_update;\n\tu16 offset;\n\tu32 peer_delay;\n\tu32 ptp_onestep_reg_base;\n};\n\nunion dpni_statistics {\n\tstruct {\n\t\tu64 ingress_all_frames;\n\t\tu64 ingress_all_bytes;\n\t\tu64 ingress_multicast_frames;\n\t\tu64 ingress_multicast_bytes;\n\t\tu64 ingress_broadcast_frames;\n\t\tu64 ingress_broadcast_bytes;\n\t} page_0;\n\tstruct {\n\t\tu64 egress_all_frames;\n\t\tu64 egress_all_bytes;\n\t\tu64 egress_multicast_frames;\n\t\tu64 egress_multicast_bytes;\n\t\tu64 egress_broadcast_frames;\n\t\tu64 egress_broadcast_bytes;\n\t} page_1;\n\tstruct {\n\t\tu64 ingress_filtered_frames;\n\t\tu64 ingress_discarded_frames;\n\t\tu64 ingress_nobuffer_discards;\n\t\tu64 egress_discarded_frames;\n\t\tu64 egress_confirmed_frames;\n\t} page_2;\n\tstruct {\n\t\tu64 egress_dequeue_bytes;\n\t\tu64 egress_dequeue_frames;\n\t\tu64 egress_reject_bytes;\n\t\tu64 egress_reject_frames;\n\t} page_3;\n\tstruct {\n\t\tu64 cgr_reject_frames;\n\t\tu64 cgr_reject_bytes;\n\t} page_4;\n\tstruct {\n\t\tu64 policer_cnt_red;\n\t\tu64 policer_cnt_yellow;\n\t\tu64 policer_cnt_green;\n\t\tu64 policer_cnt_re_red;\n\t\tu64 policer_cnt_re_yellow;\n\t} page_5;\n\tstruct {\n\t\tu64 tx_pending_frames;\n\t} page_6;\n\tstruct {\n\t\tu64 counter[7];\n\t} raw;\n};\n\nstruct dpni_taildrop {\n\tchar enable;\n\tenum dpni_congestion_unit units;\n\tu32 threshold;\n};\n\nstruct dpni_tx_shaping_cfg {\n\tu32 rate_limit;\n\tu16 max_burst_size;\n};\n\nstruct dprc_attributes {\n\tint container_id;\n\tu32 icid;\n\tint portal_id;\n\tu64 options;\n};\n\nstruct dprc_cmd_clear_irq_status {\n\t__le32 status;\n\tu8 irq_index;\n};\n\nstruct dprc_cmd_get_connection {\n\t__le32 ep1_id;\n\t__le16 ep1_interface_id;\n\tu8 pad[2];\n\tu8 ep1_type[16];\n};\n\nstruct dprc_cmd_get_irq_status {\n\t__le32 status;\n\tu8 irq_index;\n};\n\nstruct dprc_cmd_get_obj {\n\t__le32 obj_index;\n};\n\nstruct dprc_cmd_get_obj_region {\n\t__le32 obj_id;\n\t__le16 pad0;\n\tu8 region_index;\n\tu8 pad1;\n\t__le64 pad2[2];\n\tu8 obj_type[16];\n};\n\nstruct dprc_cmd_open {\n\t__le32 container_id;\n};\n\nstruct dprc_cmd_reset_container {\n\t__le32 child_container_id;\n\t__le32 options;\n};\n\nstruct dprc_cmd_set_irq {\n\t__le32 irq_val;\n\tu8 irq_index;\n\tu8 pad[3];\n\t__le64 irq_addr;\n\t__le32 irq_num;\n};\n\nstruct dprc_cmd_set_irq_enable {\n\tu8 enable;\n\tu8 pad[3];\n\tu8 irq_index;\n};\n\nstruct dprc_cmd_set_irq_mask {\n\t__le32 mask;\n\tu8 irq_index;\n};\n\nstruct dprc_cmd_set_obj_irq {\n\t__le32 irq_val;\n\tu8 irq_index;\n\tu8 pad[3];\n\t__le64 irq_addr;\n\t__le32 irq_num;\n\t__le32 obj_id;\n\tu8 obj_type[16];\n};\n\nstruct dprc_endpoint {\n\tchar type[16];\n\tint id;\n\tu16 if_id;\n};\n\nstruct dprc_irq_cfg {\n\tphys_addr_t paddr;\n\tu32 val;\n\tint irq_num;\n};\n\nstruct dprc_region_desc {\n\tu32 base_offset;\n\tu32 size;\n\tu32 flags;\n\tenum dprc_region_type type;\n\tu64 base_address;\n};\n\nstruct dprc_rsp_get_attributes {\n\t__le32 container_id;\n\t__le32 icid;\n\t__le32 options;\n\t__le32 portal_id;\n};\n\nstruct dprc_rsp_get_connection {\n\t__le64 pad[3];\n\t__le32 ep2_id;\n\t__le16 ep2_interface_id;\n\t__le16 pad1;\n\tu8 ep2_type[16];\n\t__le32 state;\n};\n\nstruct dprc_rsp_get_irq_status {\n\t__le32 status;\n};\n\nstruct dprc_rsp_get_obj {\n\t__le32 pad0;\n\t__le32 id;\n\t__le16 vendor;\n\tu8 irq_count;\n\tu8 region_count;\n\t__le32 state;\n\t__le16 version_major;\n\t__le16 version_minor;\n\t__le16 flags;\n\t__le16 pad1;\n\tu8 type[16];\n\tu8 label[16];\n};\n\nstruct dprc_rsp_get_obj_count {\n\t__le32 pad;\n\t__le32 obj_count;\n};\n\nstruct dprc_rsp_get_obj_region {\n\t__le64 pad0;\n\t__le64 base_offset;\n\t__le32 size;\n\tu8 type;\n\tu8 pad2[3];\n\t__le32 flags;\n\t__le32 pad3;\n\t__le64 base_addr;\n};\n\nstruct dprtc_cmd_clear_irq_status {\n\t__le32 status;\n\tu8 irq_index;\n} __attribute__((packed));\n\nstruct dprtc_cmd_get_irq {\n\t__le32 pad;\n\tu8 irq_index;\n} __attribute__((packed));\n\nstruct dprtc_cmd_get_irq_status {\n\t__le32 status;\n\tu8 irq_index;\n} __attribute__((packed));\n\nstruct dprtc_cmd_open {\n\t__le32 dprtc_id;\n};\n\nstruct dprtc_cmd_set_irq_enable {\n\tu8 en;\n\tu8 pad[3];\n\tu8 irq_index;\n};\n\nstruct dprtc_cmd_set_irq_mask {\n\t__le32 mask;\n\tu8 irq_index;\n} __attribute__((packed));\n\nstruct dprtc_rsp_get_irq_enable {\n\tu8 en;\n};\n\nstruct dprtc_rsp_get_irq_mask {\n\t__le32 mask;\n};\n\nstruct dprtc_rsp_get_irq_status {\n\t__le32 status;\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 64;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n};\n\nstruct dqstats {\n\tlong unsigned int stat[8];\n\tstruct percpu_counter counter[8];\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct dquot_warn {\n\tstruct super_block *w_sb;\n\tstruct kqid w_dq_id;\n\tshort int w_type;\n};\n\nstruct drbg_core {\n\tdrbg_flag_t flags;\n\t__u8 statelen;\n\t__u8 blocklen_bytes;\n\tchar cra_name[128];\n\tchar backend_cra_name[128];\n};\n\nstruct drbg_string {\n\tconst unsigned char *buf;\n\tsize_t len;\n\tstruct list_head list;\n};\n\nstruct drbg_state_ops;\n\nstruct drbg_state {\n\tstruct mutex drbg_mutex;\n\tunsigned char *V;\n\tunsigned char *Vbuf;\n\tunsigned char *C;\n\tunsigned char *Cbuf;\n\tsize_t reseed_ctr;\n\tsize_t reseed_threshold;\n\tunsigned char *scratchpad;\n\tunsigned char *scratchpadbuf;\n\tvoid *priv_data;\n\tstruct crypto_skcipher *ctr_handle;\n\tstruct skcipher_request *ctr_req;\n\t__u8 *outscratchpadbuf;\n\t__u8 *outscratchpad;\n\tstruct crypto_wait ctr_wait;\n\tstruct scatterlist sg_in;\n\tstruct scatterlist sg_out;\n\tenum drbg_seed_state seeded;\n\tlong unsigned int last_seed_time;\n\tbool pr;\n\tbool fips_primed;\n\tunsigned char *prev;\n\tstruct crypto_rng *jent;\n\tconst struct drbg_state_ops *d_ops;\n\tconst struct drbg_core *core;\n\tstruct drbg_string test_data;\n};\n\nstruct drbg_state_ops {\n\tint (*update)(struct drbg_state *, struct list_head *, int);\n\tint (*generate)(struct drbg_state *, unsigned char *, unsigned int, struct list_head *);\n\tint (*crypto_init)(struct drbg_state *);\n\tint (*crypto_fini)(struct drbg_state *);\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drm_dmi_panel_orientation_data {\n\tint width;\n\tint height;\n\tconst char * const *bios_dates;\n\tint orientation;\n};\n\nstruct drm_dsc_rc_range_parameters {\n\tu8 range_min_qp;\n\tu8 range_max_qp;\n\tu8 range_bpg_offset;\n};\n\nstruct drm_dsc_config {\n\tu8 line_buf_depth;\n\tu8 bits_per_component;\n\tbool convert_rgb;\n\tu8 slice_count;\n\tu16 slice_width;\n\tu16 slice_height;\n\tbool simple_422;\n\tu16 pic_width;\n\tu16 pic_height;\n\tu8 rc_tgt_offset_high;\n\tu8 rc_tgt_offset_low;\n\tu16 bits_per_pixel;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_quant_incr_limit0;\n\tu16 initial_xmit_delay;\n\tu16 initial_dec_delay;\n\tbool block_pred_enable;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu16 rc_buf_thresh[14];\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n\tu16 rc_model_size;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 initial_scale_value;\n\tu16 scale_decrement_interval;\n\tu16 scale_increment_interval;\n\tu16 nfl_bpg_offset;\n\tu16 slice_bpg_offset;\n\tu16 final_offset;\n\tbool vbr_enable;\n\tu8 mux_word_size;\n\tu16 slice_chunk_size;\n\tu16 rc_bits;\n\tu8 dsc_version_minor;\n\tu8 dsc_version_major;\n\tbool native_422;\n\tbool native_420;\n\tu8 second_line_bpg_offset;\n\tu16 nsl_bpg_offset;\n\tu16 second_line_offset_adj;\n};\n\nstruct drm_dsc_picture_parameter_set {\n\tu8 dsc_version;\n\tu8 pps_identifier;\n\tu8 pps_reserved;\n\tu8 pps_3;\n\tu8 pps_4;\n\tu8 bits_per_pixel_low;\n\t__be16 pic_height;\n\t__be16 pic_width;\n\t__be16 slice_height;\n\t__be16 slice_width;\n\t__be16 chunk_size;\n\tu8 initial_xmit_delay_high;\n\tu8 initial_xmit_delay_low;\n\t__be16 initial_dec_delay;\n\tu8 pps20_reserved;\n\tu8 initial_scale_value;\n\t__be16 scale_increment_interval;\n\tu8 scale_decrement_interval_high;\n\tu8 scale_decrement_interval_low;\n\tu8 pps26_reserved;\n\tu8 first_line_bpg_offset;\n\t__be16 nfl_bpg_offset;\n\t__be16 slice_bpg_offset;\n\t__be16 initial_offset;\n\t__be16 final_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\t__be16 rc_model_size;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_tgt_offset;\n\tu8 rc_buf_thresh[14];\n\t__be16 rc_range_parameters[15];\n\tu8 native_422_420;\n\tu8 second_line_bpg_offset;\n\t__be16 nsl_bpg_offset;\n\t__be16 second_line_offset_adj;\n\tu32 pps_long_94_reserved;\n\tu32 pps_long_98_reserved;\n\tu32 pps_long_102_reserved;\n\tu32 pps_long_106_reserved;\n\tu32 pps_long_110_reserved;\n\tu32 pps_long_114_reserved;\n\tu32 pps_long_118_reserved;\n\tu32 pps_long_122_reserved;\n\t__be16 pps_short_126_reserved;\n} __attribute__((packed));\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct pci_driver;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct ds3232 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tint irq;\n\tstruct rtc_device *rtc;\n\tbool suspended;\n};\n\nstruct dsa_bridge {\n\tstruct net_device *dev;\n\tunsigned int num;\n\tbool tx_fwd_offload;\n\trefcount_t refcount;\n};\n\nstruct dsa_chip_data {\n\tstruct device *host_dev;\n\tint sw_addr;\n\tstruct device *netdev[12];\n\tint eeprom_len;\n\tstruct device_node *of_node;\n\tchar *port_names[12];\n\tstruct device_node *port_dn[12];\n\ts8 rtable[4];\n};\n\nstruct dsa_lag {\n\tstruct net_device *dev;\n\tunsigned int id;\n\tstruct mutex fdb_lock;\n\tstruct list_head fdbs;\n\trefcount_t refcount;\n};\n\nstruct dsa_port;\n\nstruct dsa_db {\n\tenum dsa_db_type type;\n\tunion {\n\t\tconst struct dsa_port *dp;\n\t\tstruct dsa_lag lag;\n\t\tstruct dsa_bridge bridge;\n\t};\n};\n\nstruct dsa_switch;\n\nstruct dsa_device_ops {\n\tstruct sk_buff * (*xmit)(struct sk_buff *, struct net_device *);\n\tstruct sk_buff * (*rcv)(struct sk_buff *, struct net_device *);\n\tvoid (*flow_dissect)(const struct sk_buff *, __be16 *, int *);\n\tint (*connect)(struct dsa_switch *);\n\tvoid (*disconnect)(struct dsa_switch *);\n\tunsigned int needed_headroom;\n\tunsigned int needed_tailroom;\n\tconst char *name;\n\tenum dsa_tag_protocol proto;\n\tbool promisc_on_conduit;\n};\n\nstruct dsa_mall_mirror_tc_entry {\n\tu8 to_local_port;\n\tbool ingress;\n};\n\nstruct dsa_platform_data {\n\tstruct device *netdev;\n\tstruct net_device *of_netdev;\n\tint nr_chips;\n\tstruct dsa_chip_data *chip;\n};\n\nstruct dsa_switch_tree;\n\nstruct ethtool_ops;\n\nstruct dsa_port {\n\tunion {\n\t\tstruct net_device *conduit;\n\t\tstruct net_device *user;\n\t};\n\tconst struct dsa_device_ops *tag_ops;\n\tstruct dsa_switch_tree *dst;\n\tstruct sk_buff * (*rcv)(struct sk_buff *, struct net_device *);\n\tstruct dsa_switch *ds;\n\tunsigned int index;\n\tenum {\n\t\tDSA_PORT_TYPE_UNUSED = 0,\n\t\tDSA_PORT_TYPE_CPU = 1,\n\t\tDSA_PORT_TYPE_DSA = 2,\n\t\tDSA_PORT_TYPE_USER = 3,\n\t} type;\n\tconst char *name;\n\tstruct dsa_port *cpu_dp;\n\tu8 mac[6];\n\tu8 stp_state;\n\tu8 vlan_filtering: 1;\n\tu8 learning: 1;\n\tu8 lag_tx_enabled: 1;\n\tu8 conduit_admin_up: 1;\n\tu8 conduit_oper_up: 1;\n\tu8 cpu_port_in_lag: 1;\n\tu8 setup: 1;\n\tstruct device_node *dn;\n\tunsigned int ageing_time;\n\tstruct dsa_bridge *bridge;\n\tstruct devlink_port devlink_port;\n\tstruct phylink *pl;\n\tstruct phylink_config pl_config;\n\tnetdevice_tracker conduit_tracker;\n\tstruct dsa_lag *lag;\n\tstruct net_device *hsr_dev;\n\tstruct list_head list;\n\tconst struct ethtool_ops *orig_ethtool_ops;\n\tstruct mutex addr_lists_lock;\n\tstruct list_head fdbs;\n\tstruct list_head mdbs;\n\tstruct mutex vlans_lock;\n\tunion {\n\t\tstruct list_head vlans;\n\t\tstruct list_head user_vlans;\n\t};\n};\n\nstruct kernel_hwtstamp_config;\n\nstruct dsa_stubs {\n\tint (*conduit_hwtstamp_validate)(struct net_device *, const struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct dsa_8021q_context;\n\nstruct dsa_switch_ops;\n\nstruct phylink_mac_ops;\n\nstruct dsa_switch {\n\tstruct device *dev;\n\tstruct dsa_switch_tree *dst;\n\tunsigned int index;\n\tu32 setup: 1;\n\tu32 vlan_filtering_is_global: 1;\n\tu32 needs_standalone_vlan_filtering: 1;\n\tu32 configure_vlan_while_not_filtering: 1;\n\tu32 untag_bridge_pvid: 1;\n\tu32 untag_vlan_aware_bridge_pvid: 1;\n\tu32 assisted_learning_on_cpu_port: 1;\n\tu32 vlan_filtering: 1;\n\tu32 mtu_enforcement_ingress: 1;\n\tu32 fdb_isolation: 1;\n\tu32 dscp_prio_mapping_is_global: 1;\n\tstruct notifier_block nb;\n\tvoid *priv;\n\tvoid *tagger_data;\n\tstruct dsa_chip_data *cd;\n\tconst struct dsa_switch_ops *ops;\n\tconst struct phylink_mac_ops *phylink_mac_ops;\n\tu32 phys_mii_mask;\n\tstruct mii_bus *user_mii_bus;\n\tunsigned int ageing_time_min;\n\tunsigned int ageing_time_max;\n\tstruct dsa_8021q_context *tag_8021q_ctx;\n\tstruct devlink *devlink;\n\tunsigned int num_tx_queues;\n\tunsigned int num_lag_ids;\n\tunsigned int max_num_bridges;\n\tunsigned int num_ports;\n};\n\ntypedef int dsa_fdb_dump_cb_t(const unsigned char *, u16, bool, void *);\n\nstruct ethtool_eth_phy_stats;\n\nstruct ethtool_eth_mac_stats;\n\nstruct ethtool_eth_ctrl_stats;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ts_stats;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_test;\n\nstruct ethtool_wolinfo;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_mm_state;\n\nstruct ethtool_mm_cfg;\n\nstruct ethtool_mm_stats;\n\nstruct ethtool_keee;\n\nstruct ethtool_eeprom;\n\nstruct ethtool_regs;\n\nstruct netdev_notifier_changeupper_info;\n\nstruct switchdev_mst_state;\n\nstruct switchdev_brport_flags;\n\nstruct switchdev_obj_port_vlan;\n\nstruct switchdev_vlan_msti;\n\nstruct switchdev_obj_port_mdb;\n\nstruct ethtool_rxnfc;\n\nstruct flow_cls_offload;\n\nstruct flow_action_police;\n\nstruct netdev_lag_upper_info;\n\nstruct switchdev_obj_mrp;\n\nstruct switchdev_obj_ring_role_mrp;\n\nstruct dsa_switch_ops {\n\tenum dsa_tag_protocol (*get_tag_protocol)(struct dsa_switch *, int, enum dsa_tag_protocol);\n\tint (*change_tag_protocol)(struct dsa_switch *, enum dsa_tag_protocol);\n\tint (*connect_tag_protocol)(struct dsa_switch *, enum dsa_tag_protocol);\n\tint (*port_change_conduit)(struct dsa_switch *, int, struct net_device *, struct netlink_ext_ack *);\n\tint (*setup)(struct dsa_switch *);\n\tvoid (*teardown)(struct dsa_switch *);\n\tint (*port_setup)(struct dsa_switch *, int);\n\tvoid (*port_teardown)(struct dsa_switch *, int);\n\tu32 (*get_phy_flags)(struct dsa_switch *, int);\n\tint (*phy_read)(struct dsa_switch *, int, int);\n\tint (*phy_write)(struct dsa_switch *, int, int, u16);\n\tvoid (*phylink_get_caps)(struct dsa_switch *, int, struct phylink_config *);\n\tvoid (*phylink_fixed_state)(struct dsa_switch *, int, struct phylink_link_state *);\n\tvoid (*get_strings)(struct dsa_switch *, int, u32, uint8_t *);\n\tvoid (*get_ethtool_stats)(struct dsa_switch *, int, uint64_t *);\n\tint (*get_sset_count)(struct dsa_switch *, int, int);\n\tvoid (*get_ethtool_phy_stats)(struct dsa_switch *, int, uint64_t *);\n\tvoid (*get_eth_phy_stats)(struct dsa_switch *, int, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct dsa_switch *, int, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct dsa_switch *, int, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct dsa_switch *, int, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tvoid (*get_ts_stats)(struct dsa_switch *, int, struct ethtool_ts_stats *);\n\tvoid (*get_stats64)(struct dsa_switch *, int, struct rtnl_link_stats64 *);\n\tvoid (*get_pause_stats)(struct dsa_switch *, int, struct ethtool_pause_stats *);\n\tvoid (*self_test)(struct dsa_switch *, int, struct ethtool_test *, u64 *);\n\tvoid (*get_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *);\n\tint (*get_ts_info)(struct dsa_switch *, int, struct kernel_ethtool_ts_info *);\n\tint (*get_mm)(struct dsa_switch *, int, struct ethtool_mm_state *);\n\tint (*set_mm)(struct dsa_switch *, int, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct dsa_switch *, int, struct ethtool_mm_stats *);\n\tint (*port_get_default_prio)(struct dsa_switch *, int);\n\tint (*port_set_default_prio)(struct dsa_switch *, int, u8);\n\tint (*port_get_dscp_prio)(struct dsa_switch *, int, u8);\n\tint (*port_add_dscp_prio)(struct dsa_switch *, int, u8, u8);\n\tint (*port_del_dscp_prio)(struct dsa_switch *, int, u8, u8);\n\tint (*port_set_apptrust)(struct dsa_switch *, int, const u8 *, int);\n\tint (*port_get_apptrust)(struct dsa_switch *, int, u8 *, int *);\n\tint (*suspend)(struct dsa_switch *);\n\tint (*resume)(struct dsa_switch *);\n\tint (*port_enable)(struct dsa_switch *, int, struct phy_device *);\n\tvoid (*port_disable)(struct dsa_switch *, int);\n\tint (*port_set_mac_address)(struct dsa_switch *, int, const unsigned char *);\n\tstruct dsa_port * (*preferred_default_local_cpu_port)(struct dsa_switch *);\n\tbool (*support_eee)(struct dsa_switch *, int);\n\tint (*set_mac_eee)(struct dsa_switch *, int, struct ethtool_keee *);\n\tint (*get_eeprom_len)(struct dsa_switch *);\n\tint (*get_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *);\n\tint (*get_regs_len)(struct dsa_switch *, int);\n\tvoid (*get_regs)(struct dsa_switch *, int, struct ethtool_regs *, void *);\n\tint (*port_prechangeupper)(struct dsa_switch *, int, struct netdev_notifier_changeupper_info *);\n\tint (*set_ageing_time)(struct dsa_switch *, unsigned int);\n\tint (*port_bridge_join)(struct dsa_switch *, int, struct dsa_bridge, bool *, struct netlink_ext_ack *);\n\tvoid (*port_bridge_leave)(struct dsa_switch *, int, struct dsa_bridge);\n\tvoid (*port_stp_state_set)(struct dsa_switch *, int, u8);\n\tint (*port_mst_state_set)(struct dsa_switch *, int, const struct switchdev_mst_state *);\n\tvoid (*port_fast_age)(struct dsa_switch *, int);\n\tint (*port_vlan_fast_age)(struct dsa_switch *, int, u16);\n\tint (*port_pre_bridge_flags)(struct dsa_switch *, int, struct switchdev_brport_flags, struct netlink_ext_ack *);\n\tint (*port_bridge_flags)(struct dsa_switch *, int, struct switchdev_brport_flags, struct netlink_ext_ack *);\n\tvoid (*port_set_host_flood)(struct dsa_switch *, int, bool, bool);\n\tint (*port_vlan_filtering)(struct dsa_switch *, int, bool, struct netlink_ext_ack *);\n\tint (*port_vlan_add)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *, struct netlink_ext_ack *);\n\tint (*port_vlan_del)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *);\n\tint (*vlan_msti_set)(struct dsa_switch *, struct dsa_bridge, const struct switchdev_vlan_msti *);\n\tint (*port_fdb_add)(struct dsa_switch *, int, const unsigned char *, u16, struct dsa_db);\n\tint (*port_fdb_del)(struct dsa_switch *, int, const unsigned char *, u16, struct dsa_db);\n\tint (*port_fdb_dump)(struct dsa_switch *, int, dsa_fdb_dump_cb_t *, void *);\n\tint (*lag_fdb_add)(struct dsa_switch *, struct dsa_lag, const unsigned char *, u16, struct dsa_db);\n\tint (*lag_fdb_del)(struct dsa_switch *, struct dsa_lag, const unsigned char *, u16, struct dsa_db);\n\tint (*port_mdb_add)(struct dsa_switch *, int, const struct switchdev_obj_port_mdb *, struct dsa_db);\n\tint (*port_mdb_del)(struct dsa_switch *, int, const struct switchdev_obj_port_mdb *, struct dsa_db);\n\tint (*get_rxnfc)(struct dsa_switch *, int, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct dsa_switch *, int, struct ethtool_rxnfc *);\n\tint (*cls_flower_add)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*cls_flower_del)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*cls_flower_stats)(struct dsa_switch *, int, struct flow_cls_offload *, bool);\n\tint (*port_mirror_add)(struct dsa_switch *, int, struct dsa_mall_mirror_tc_entry *, bool, struct netlink_ext_ack *);\n\tvoid (*port_mirror_del)(struct dsa_switch *, int, struct dsa_mall_mirror_tc_entry *);\n\tint (*port_policer_add)(struct dsa_switch *, int, const struct flow_action_police *);\n\tvoid (*port_policer_del)(struct dsa_switch *, int);\n\tint (*port_setup_tc)(struct dsa_switch *, int, enum tc_setup_type, void *);\n\tint (*crosschip_bridge_join)(struct dsa_switch *, int, int, int, struct dsa_bridge, struct netlink_ext_ack *);\n\tvoid (*crosschip_bridge_leave)(struct dsa_switch *, int, int, int, struct dsa_bridge);\n\tint (*crosschip_lag_change)(struct dsa_switch *, int, int);\n\tint (*crosschip_lag_join)(struct dsa_switch *, int, int, struct dsa_lag, struct netdev_lag_upper_info *, struct netlink_ext_ack *);\n\tint (*crosschip_lag_leave)(struct dsa_switch *, int, int, struct dsa_lag);\n\tint (*port_hwtstamp_get)(struct dsa_switch *, int, struct kernel_hwtstamp_config *);\n\tint (*port_hwtstamp_set)(struct dsa_switch *, int, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*port_txtstamp)(struct dsa_switch *, int, struct sk_buff *);\n\tbool (*port_rxtstamp)(struct dsa_switch *, int, struct sk_buff *, unsigned int);\n\tint (*devlink_param_get)(struct dsa_switch *, u32, struct devlink_param_gset_ctx *);\n\tint (*devlink_param_set)(struct dsa_switch *, u32, struct devlink_param_gset_ctx *);\n\tint (*devlink_info_get)(struct dsa_switch *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*devlink_sb_pool_get)(struct dsa_switch *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*devlink_sb_pool_set)(struct dsa_switch *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*devlink_sb_port_pool_get)(struct dsa_switch *, int, unsigned int, u16, u32 *);\n\tint (*devlink_sb_port_pool_set)(struct dsa_switch *, int, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*devlink_sb_tc_pool_bind_get)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*devlink_sb_tc_pool_bind_set)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*devlink_sb_occ_snapshot)(struct dsa_switch *, unsigned int);\n\tint (*devlink_sb_occ_max_clear)(struct dsa_switch *, unsigned int);\n\tint (*devlink_sb_occ_port_pool_get)(struct dsa_switch *, int, unsigned int, u16, u32 *, u32 *);\n\tint (*devlink_sb_occ_tc_port_bind_get)(struct dsa_switch *, int, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*port_change_mtu)(struct dsa_switch *, int, int);\n\tint (*port_max_mtu)(struct dsa_switch *, int);\n\tint (*port_lag_change)(struct dsa_switch *, int);\n\tint (*port_lag_join)(struct dsa_switch *, int, struct dsa_lag, struct netdev_lag_upper_info *, struct netlink_ext_ack *);\n\tint (*port_lag_leave)(struct dsa_switch *, int, struct dsa_lag);\n\tint (*port_hsr_join)(struct dsa_switch *, int, struct net_device *, struct netlink_ext_ack *);\n\tint (*port_hsr_leave)(struct dsa_switch *, int, struct net_device *);\n\tint (*port_mrp_add)(struct dsa_switch *, int, const struct switchdev_obj_mrp *);\n\tint (*port_mrp_del)(struct dsa_switch *, int, const struct switchdev_obj_mrp *);\n\tint (*port_mrp_add_ring_role)(struct dsa_switch *, int, const struct switchdev_obj_ring_role_mrp *);\n\tint (*port_mrp_del_ring_role)(struct dsa_switch *, int, const struct switchdev_obj_ring_role_mrp *);\n\tint (*tag_8021q_vlan_add)(struct dsa_switch *, int, u16, u16);\n\tint (*tag_8021q_vlan_del)(struct dsa_switch *, int, u16);\n\tvoid (*conduit_state_change)(struct dsa_switch *, const struct net_device *, bool);\n};\n\nstruct dsa_switch_tree {\n\tstruct list_head list;\n\tstruct list_head ports;\n\tstruct raw_notifier_head nh;\n\tunsigned int index;\n\tstruct kref refcount;\n\tstruct dsa_lag **lags;\n\tconst struct dsa_device_ops *tag_ops;\n\tenum dsa_tag_protocol default_proto;\n\tbool setup;\n\tstruct dsa_platform_data *pd;\n\tstruct list_head rtable;\n\tunsigned int lags_len;\n\tunsigned int last_switch;\n};\n\nstruct hnae_ae_ops;\n\nstruct hnae_ae_dev {\n\tstruct device cls_dev;\n\tstruct device *dev;\n\tstruct hnae_ae_ops *ops;\n\tstruct list_head node;\n\tstruct module *owner;\n\tint id;\n\tchar name[16];\n\tstruct list_head handle_list;\n\tspinlock_t lock;\n};\n\nstruct dsaf_hw_stats {\n\tu64 pad_drop;\n\tu64 man_pkts;\n\tu64 rx_pkts;\n\tu64 rx_pkt_id;\n\tu64 rx_pause_frame;\n\tu64 release_buf_num;\n\tu64 sbm_drop;\n\tu64 crc_false;\n\tu64 bp_drop;\n\tu64 rslt_drop;\n\tu64 local_addr_false;\n\tu64 vlan_drop;\n\tu64 stp_drop;\n\tu64 rx_pfc[8];\n\tu64 tx_pfc[8];\n\tu64 tx_pkts;\n};\n\nstruct dsaf_int_xge_src {\n\tu32 xid_xge_ecc_err_int_src;\n\tu32 xid_xge_fsm_timout_int_src;\n\tu32 sbm_xge_lnk_fsm_timout_int_src;\n\tu32 sbm_xge_lnk_ecc_2bit_int_src;\n\tu32 sbm_xge_mib_req_failed_int_src;\n\tu32 sbm_xge_mib_req_fsm_timout_int_src;\n\tu32 sbm_xge_mib_rels_fsm_timout_int_src;\n\tu32 sbm_xge_sram_ecc_2bit_int_src;\n\tu32 sbm_xge_mib_buf_sum_err_int_src;\n\tu32 sbm_xge_mib_req_extra_int_src;\n\tu32 sbm_xge_mib_rels_extra_int_src;\n\tu32 voq_xge_start_to_over_0_int_src;\n\tu32 voq_xge_start_to_over_1_int_src;\n\tu32 voq_xge_ecc_err_int_src;\n};\n\nstruct dsaf_int_ppe_src {\n\tu32 xid_ppe_fsm_timout_int_src;\n\tu32 sbm_ppe_lnk_fsm_timout_int_src;\n\tu32 sbm_ppe_lnk_ecc_2bit_int_src;\n\tu32 sbm_ppe_mib_req_failed_int_src;\n\tu32 sbm_ppe_mib_req_fsm_timout_int_src;\n\tu32 sbm_ppe_mib_rels_fsm_timout_int_src;\n\tu32 sbm_ppe_sram_ecc_2bit_int_src;\n\tu32 sbm_ppe_mib_buf_sum_err_int_src;\n\tu32 sbm_ppe_mib_req_extra_int_src;\n\tu32 sbm_ppe_mib_rels_extra_int_src;\n\tu32 voq_ppe_start_to_over_0_int_src;\n\tu32 voq_ppe_ecc_err_int_src;\n\tu32 xod_ppe_fifo_rd_empty_int_src;\n\tu32 xod_ppe_fifo_wr_full_int_src;\n};\n\nstruct dsaf_int_rocee_src {\n\tu32 xid_rocee_fsm_timout_int_src;\n\tu32 sbm_rocee_lnk_fsm_timout_int_src;\n\tu32 sbm_rocee_lnk_ecc_2bit_int_src;\n\tu32 sbm_rocee_mib_req_failed_int_src;\n\tu32 sbm_rocee_mib_req_fsm_timout_int_src;\n\tu32 sbm_rocee_mib_rels_fsm_timout_int_src;\n\tu32 sbm_rocee_sram_ecc_2bit_int_src;\n\tu32 sbm_rocee_mib_buf_sum_err_int_src;\n\tu32 sbm_rocee_mib_req_extra_int_src;\n\tu32 sbm_rocee_mib_rels_extra_int_src;\n\tu32 voq_rocee_start_to_over_0_int_src;\n\tu32 voq_rocee_ecc_err_int_src;\n};\n\nstruct dsaf_int_tbl_src {\n\tu32 tbl_da0_mis_src;\n\tu32 tbl_da1_mis_src;\n\tu32 tbl_da2_mis_src;\n\tu32 tbl_da3_mis_src;\n\tu32 tbl_da4_mis_src;\n\tu32 tbl_da5_mis_src;\n\tu32 tbl_da6_mis_src;\n\tu32 tbl_da7_mis_src;\n\tu32 tbl_sa_mis_src;\n\tu32 tbl_old_sech_end_src;\n\tu32 lram_ecc_err1_src;\n\tu32 lram_ecc_err2_src;\n\tu32 tram_ecc_err1_src;\n\tu32 tram_ecc_err2_src;\n\tu32 tbl_ucast_bcast_xge0_src;\n\tu32 tbl_ucast_bcast_xge1_src;\n\tu32 tbl_ucast_bcast_xge2_src;\n\tu32 tbl_ucast_bcast_xge3_src;\n\tu32 tbl_ucast_bcast_xge4_src;\n\tu32 tbl_ucast_bcast_xge5_src;\n\tu32 tbl_ucast_bcast_ppe_src;\n\tu32 tbl_ucast_bcast_rocee_src;\n};\n\nstruct dsaf_int_stat {\n\tstruct dsaf_int_xge_src dsaf_int_xge_stat[6];\n\tstruct dsaf_int_ppe_src dsaf_int_ppe_stat[6];\n\tstruct dsaf_int_rocee_src dsaf_int_rocee_stat[6];\n\tstruct dsaf_int_tbl_src dsaf_int_tbl_stat[1];\n};\n\nstruct ppe_common_cb;\n\nstruct rcb_common_cb;\n\nstruct hns_mac_cb;\n\nstruct dsaf_misc_op;\n\nstruct dsaf_device {\n\tstruct device *dev;\n\tstruct hnae_ae_dev ae_dev;\n\tu8 *sc_base;\n\tu8 *sds_base;\n\tu8 *ppe_base;\n\tu8 *io_base;\n\tstruct regmap *sub_ctrl;\n\tphys_addr_t ppe_paddr;\n\tu32 desc_num;\n\tu32 buf_size;\n\tu32 reset_offset;\n\tint buf_size_type;\n\tenum dsaf_mode dsaf_mode;\n\tenum hal_dsaf_mode dsaf_en;\n\tenum hal_dsaf_tc_mode dsaf_tc_mode;\n\tu32 dsaf_ver;\n\tu16 tcam_max_num;\n\tstruct ppe_common_cb *ppe_common[1];\n\tstruct rcb_common_cb *rcb_common[1];\n\tstruct hns_mac_cb *mac_cb[6];\n\tstruct dsaf_misc_op *misc_op;\n\tstruct dsaf_hw_stats hw_stats[18];\n\tstruct dsaf_int_stat int_stat;\n\tspinlock_t tcam_lock;\n};\n\nstruct dsaf_drv_mac_single_dest_entry {\n\tu8 addr[6];\n\tu16 in_vlan_id;\n\tu8 in_port_num;\n\tu8 port_num;\n\tu8 rsv[6];\n};\n\nstruct dsaf_drv_soft_mac_tbl;\n\nstruct dsaf_drv_priv {\n\tstruct dsaf_drv_soft_mac_tbl *soft_mac_tbl;\n};\n\nstruct dsaf_drv_tbl_tcam_key {\n\tunion {\n\t\tstruct {\n\t\t\tu8 mac_3;\n\t\t\tu8 mac_2;\n\t\t\tu8 mac_1;\n\t\t\tu8 mac_0;\n\t\t} bits;\n\t\tu32 val;\n\t} high;\n\tunion {\n\t\tstruct {\n\t\t\tu16 port_vlan;\n\t\t\tu8 mac_5;\n\t\t\tu8 mac_4;\n\t\t} bits;\n\t\tu32 val;\n\t} low;\n};\n\nstruct dsaf_drv_soft_mac_tbl {\n\tstruct dsaf_drv_tbl_tcam_key tcam_key;\n\tu16 index;\n};\n\nstruct dsaf_misc_op {\n\tvoid (*cpld_set_led)(struct hns_mac_cb *, int, u16, int);\n\tvoid (*cpld_reset_led)(struct hns_mac_cb *);\n\tint (*cpld_set_led_id)(struct hns_mac_cb *, enum hnae_led_state);\n\tvoid (*dsaf_reset)(struct dsaf_device *, bool);\n\tvoid (*xge_srst)(struct dsaf_device *, u32, bool);\n\tvoid (*ge_srst)(struct dsaf_device *, u32, bool);\n\tvoid (*ppe_srst)(struct dsaf_device *, u32, bool);\n\tvoid (*ppe_comm_srst)(struct dsaf_device *, bool);\n\tphy_interface_t (*get_phy_if)(struct hns_mac_cb *);\n\tint (*get_sfp_prsnt)(struct hns_mac_cb *, int *);\n\tint (*cfg_serdes_loopback)(struct hns_mac_cb *, bool);\n};\n\nstruct dsaf_tbl_line_cfg {\n\tu32 tbl_line_mac_discard;\n\tu32 tbl_line_dvc;\n\tu32 tbl_line_out_port;\n};\n\nstruct dsaf_tbl_tcam_data {\n\tu32 tbl_tcam_data_high;\n\tu32 tbl_tcam_data_low;\n};\n\nstruct dsaf_tbl_tcam_mcast_cfg {\n\tu8 tbl_mcast_old_en;\n\tu8 tbl_mcast_item_vld;\n\tu32 tbl_mcast_port_msk[5];\n};\n\nstruct dsaf_tbl_tcam_ucast_cfg {\n\tu32 tbl_ucast_old_en;\n\tu32 tbl_ucast_item_vld;\n\tu32 tbl_ucast_mac_discard;\n\tu32 tbl_ucast_dvc;\n\tu32 tbl_ucast_out_port;\n};\n\nstruct dsi_div_hw_data {\n\tstruct clk_hw hw;\n\tu32 conf;\n\tlong unsigned int rate;\n\tstruct rzg2l_cpg_priv *priv;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tlocal_lock_t bh_lock;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct dst_ops;\n\nstruct uncached_list;\n\nstruct lwtunnel_state;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tvoid *__pad1;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\trcuref_t __rcuref;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n\tstruct lwtunnel_state *lwtstate;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dtsec_cfg {\n\tu16 halfdup_retransmit;\n\tu16 halfdup_coll_window;\n\tbool tx_pad_crc;\n\tu16 tx_pause_time;\n\tbool ptp_tsu_en;\n\tbool ptp_exception_en;\n\tu32 preamble_len;\n\tu32 rx_prepend;\n\tu16 tx_pause_time_extd;\n\tu16 maximum_frame;\n\tu32 non_back_to_back_ipg1;\n\tu32 non_back_to_back_ipg2;\n\tu32 min_ifg_enforcement;\n\tu32 back_to_back_ipg;\n};\n\nstruct dtsec_regs {\n\tu32 tsec_id;\n\tu32 tsec_id2;\n\tu32 ievent;\n\tu32 imask;\n\tu32 reserved0010[1];\n\tu32 ecntrl;\n\tu32 ptv;\n\tu32 tbipa;\n\tu32 tmr_ctrl;\n\tu32 tmr_pevent;\n\tu32 tmr_pemask;\n\tu32 reserved002c[5];\n\tu32 tctrl;\n\tu32 reserved0044[3];\n\tu32 rctrl;\n\tu32 reserved0054[11];\n\tu32 igaddr[8];\n\tu32 gaddr[8];\n\tu32 reserved00c0[16];\n\tu32 maccfg1;\n\tu32 maccfg2;\n\tu32 ipgifg;\n\tu32 hafdup;\n\tu32 maxfrm;\n\tu32 reserved0114[10];\n\tu32 ifstat;\n\tu32 macstnaddr1;\n\tu32 macstnaddr2;\n\tstruct {\n\t\tu32 exact_match1;\n\t\tu32 exact_match2;\n\t} macaddr[15];\n\tu32 reserved01c0[16];\n\tu32 tr64;\n\tu32 tr127;\n\tu32 tr255;\n\tu32 tr511;\n\tu32 tr1k;\n\tu32 trmax;\n\tu32 trmgv;\n\tu32 rbyt;\n\tu32 rpkt;\n\tu32 rfcs;\n\tu32 rmca;\n\tu32 rbca;\n\tu32 rxcf;\n\tu32 rxpf;\n\tu32 rxuo;\n\tu32 raln;\n\tu32 rflr;\n\tu32 rcde;\n\tu32 rcse;\n\tu32 rund;\n\tu32 rovr;\n\tu32 rfrg;\n\tu32 rjbr;\n\tu32 rdrp;\n\tu32 tbyt;\n\tu32 tpkt;\n\tu32 tmca;\n\tu32 tbca;\n\tu32 txpf;\n\tu32 tdfr;\n\tu32 tedf;\n\tu32 tscl;\n\tu32 tmcl;\n\tu32 tlcl;\n\tu32 txcl;\n\tu32 tncl;\n\tu32 reserved0290[1];\n\tu32 tdrp;\n\tu32 tjbr;\n\tu32 tfcs;\n\tu32 txcf;\n\tu32 tovr;\n\tu32 tund;\n\tu32 tfrg;\n\tu32 car1;\n\tu32 car2;\n\tu32 cam1;\n\tu32 cam2;\n\tu32 reserved02c0[848];\n};\n\nstruct dump_ctx {\n\tint idx;\n\tint start;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct dvfs_info {\n\tu8 domain;\n\tu8 opp_count;\n\t__le16 latency;\n\tstruct {\n\t\t__le32 freq;\n\t\t__le32 m_volt;\n\t} opps[16];\n};\n\nstruct dvfs_set {\n\tu8 domain;\n\tu8 index;\n};\n\nstruct dw8250_port_data {\n\tint line;\n\tstruct uart_8250_dma dma;\n\tu32 cpr_value;\n\tu8 dlf_size;\n\tbool hw_rs485_support;\n};\n\nstruct dw8250_platform_data;\n\nstruct dw8250_data {\n\tstruct dw8250_port_data data;\n\tconst struct dw8250_platform_data *pdata;\n\tu32 msr_mask_on;\n\tu32 msr_mask_off;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_notifier;\n\tstruct work_struct clk_work;\n\tstruct reset_control *rst;\n\tunsigned int skip_autocfg: 1;\n\tunsigned int uart_16550_compatible: 1;\n};\n\nstruct dw8250_platform_data {\n\tu8 usr_reg;\n\tu32 cpr_value;\n\tunsigned int quirks;\n};\n\nstruct dw_apb_timer {\n\tvoid *base;\n\tlong unsigned int freq;\n\tint irq;\n};\n\nstruct dw_apb_clock_event_device {\n\tstruct clock_event_device ced;\n\tstruct dw_apb_timer timer;\n\tvoid (*eoi)(struct dw_apb_timer *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dw_apb_clocksource {\n\tstruct dw_apb_timer timer;\n\tstruct clocksource cs;\n};\n\nstruct dw_edma_region {\n\tu64 paddr;\n\tunion {\n\t\tvoid *mem;\n\t\tvoid *io;\n\t} vaddr;\n\tsize_t sz;\n};\n\nstruct dw_edma;\n\nstruct dw_edma_plat_ops;\n\nstruct dw_edma_chip {\n\tstruct device *dev;\n\tint nr_irqs;\n\tconst struct dw_edma_plat_ops *ops;\n\tu32 flags;\n\tvoid *reg_base;\n\tu16 ll_wr_cnt;\n\tu16 ll_rd_cnt;\n\tstruct dw_edma_region ll_region_wr[8];\n\tstruct dw_edma_region ll_region_rd[8];\n\tstruct dw_edma_region dt_region_wr[8];\n\tstruct dw_edma_region dt_region_rd[8];\n\tenum dw_edma_map_format mf;\n\tstruct dw_edma *dw;\n};\n\nstruct dw_edma_plat_ops {\n\tint (*irq_vector)(struct device *, unsigned int);\n\tu64 (*pci_address)(struct device *, phys_addr_t);\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_gpio;\n};\n\nstruct dw_i2c_dev {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct regmap *sysmap;\n\tvoid *base;\n\tvoid *ext;\n\tstruct completion cmd_complete;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct reset_control *rst;\n\tstruct i2c_client *slave;\n\tu32 (*get_clk_rate_khz)(struct dw_i2c_dev *);\n\tint cmd_err;\n\tstruct i2c_msg *msgs;\n\tint msgs_num;\n\tint msg_write_idx;\n\tu32 tx_buf_len;\n\tu8 *tx_buf;\n\tint msg_read_idx;\n\tu32 rx_buf_len;\n\tu8 *rx_buf;\n\tint msg_err;\n\tunsigned int status;\n\tunsigned int abort_source;\n\tunsigned int sw_mask;\n\tint irq;\n\tu32 flags;\n\tstruct i2c_adapter adapter;\n\tu32 functionality;\n\tu32 master_cfg;\n\tu32 slave_cfg;\n\tunsigned int tx_fifo_depth;\n\tunsigned int rx_fifo_depth;\n\tint rx_outstanding;\n\tstruct i2c_timings timings;\n\tu32 sda_hold_time;\n\tu16 ss_hcnt;\n\tu16 ss_lcnt;\n\tu16 fs_hcnt;\n\tu16 fs_lcnt;\n\tu16 fp_hcnt;\n\tu16 fp_lcnt;\n\tu16 hs_hcnt;\n\tu16 hs_lcnt;\n\tint (*acquire_lock)(void);\n\tvoid (*release_lock)(void);\n\tint semaphore_idx;\n\tbool shared_with_punit;\n\tint (*set_sda_hold_time)(struct dw_i2c_dev *);\n\tint mode;\n\tstruct i2c_bus_recovery_info rinfo;\n\tu32 bus_capacitance_pF;\n\tbool clk_freq_optimized;\n\tbool emptyfifo_hold_master;\n};\n\nstruct uhs2_command;\n\nstruct mmc_command {\n\tu32 opcode;\n\tu32 arg;\n\tu32 resp[4];\n\tunsigned int flags;\n\tunsigned int retries;\n\tint error;\n\tunsigned int busy_timeout;\n\tstruct mmc_data *data;\n\tstruct mmc_request *mrq;\n\tstruct uhs2_command *uhs2_cmd;\n\tbool has_ext_addr;\n\tu8 ext_addr;\n};\n\nstruct dw_mci_dma_ops;\n\nstruct dw_mci_dma_slave;\n\nstruct dw_mci_board;\n\nstruct dw_mci_drv_data;\n\nstruct dw_mci_slot;\n\nstruct dw_mci {\n\tspinlock_t lock;\n\tspinlock_t irq_lock;\n\tvoid *regs;\n\tvoid *fifo_reg;\n\tu32 data_addr_override;\n\tbool wm_aligned;\n\tstruct scatterlist *sg;\n\tstruct sg_mapping_iter sg_miter;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command stop_abort;\n\tunsigned int prev_blksz;\n\tunsigned char timing;\n\tint use_dma;\n\tint using_dma;\n\tint dma_64bit_address;\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tconst struct dw_mci_dma_ops *dma_ops;\n\tunsigned int ring_size;\n\tstruct dw_mci_dma_slave *dms;\n\tresource_size_t phy_regs;\n\tu32 cmd_status;\n\tu32 data_status;\n\tu32 stop_cmdr;\n\tu32 dir_status;\n\tstruct work_struct bh_work;\n\tlong unsigned int pending_events;\n\tlong unsigned int completed_events;\n\tenum dw_mci_state state;\n\tstruct list_head queue;\n\tu32 bus_hz;\n\tu32 current_speed;\n\tu32 minimum_speed;\n\tu32 fifoth_val;\n\tu16 verid;\n\tstruct device *dev;\n\tstruct dw_mci_board *pdata;\n\tconst struct dw_mci_drv_data *drv_data;\n\tvoid *priv;\n\tstruct clk *biu_clk;\n\tstruct clk *ciu_clk;\n\tstruct dw_mci_slot *slot;\n\tint fifo_depth;\n\tint data_shift;\n\tu8 part_buf_start;\n\tu8 part_buf_count;\n\tunion {\n\t\tu16 part_buf16;\n\t\tu32 part_buf32;\n\t\tu64 part_buf;\n\t};\n\tvoid (*push_data)(struct dw_mci *, void *, int);\n\tvoid (*pull_data)(struct dw_mci *, void *, int);\n\tu32 quirks;\n\tbool vqmmc_enabled;\n\tlong unsigned int irq_flags;\n\tint irq;\n\tint sdio_id0;\n\tstruct timer_list cmd11_timer;\n\tstruct timer_list cto_timer;\n\tstruct timer_list dto_timer;\n};\n\nstruct dma_pdata;\n\nstruct dw_mci_board {\n\tunsigned int bus_hz;\n\tu32 caps;\n\tu32 caps2;\n\tu32 pm_caps;\n\tunsigned int fifo_depth;\n\tu32 detect_delay_ms;\n\tstruct reset_control *rstc;\n\tstruct dw_mci_dma_ops *dma_ops;\n\tstruct dma_pdata *data;\n};\n\nstruct dw_mci_dma_ops {\n\tint (*init)(struct dw_mci *);\n\tint (*start)(struct dw_mci *, unsigned int);\n\tvoid (*complete)(void *);\n\tvoid (*stop)(struct dw_mci *);\n\tvoid (*cleanup)(struct dw_mci *);\n\tvoid (*exit)(struct dw_mci *);\n};\n\nstruct dw_mci_dma_slave {\n\tstruct dma_chan *ch;\n\tenum dma_transfer_direction direction;\n};\n\nstruct dw_mci_drv_data {\n\tlong unsigned int *caps;\n\tu32 num_caps;\n\tu32 common_caps;\n\tint (*init)(struct dw_mci *);\n\tvoid (*set_ios)(struct dw_mci *, struct mmc_ios *);\n\tint (*parse_dt)(struct dw_mci *);\n\tint (*execute_tuning)(struct dw_mci_slot *, u32);\n\tint (*prepare_hs400_tuning)(struct dw_mci *, struct mmc_ios *);\n\tint (*switch_voltage)(struct mmc_host *, struct mmc_ios *);\n\tvoid (*set_data_timeout)(struct dw_mci *, unsigned int);\n\tu32 (*get_drto_clks)(struct dw_mci *);\n\tvoid (*hw_reset)(struct dw_mci *);\n};\n\nstruct dw_mci_exynos_compatible {\n\tchar *compatible;\n\tenum dw_mci_exynos_type ctrl_type;\n};\n\nstruct dw_mci_exynos_priv_data {\n\tenum dw_mci_exynos_type ctrl_type;\n\tu8 ciu_div;\n\tu32 sdr_timing;\n\tu32 ddr_timing;\n\tu32 hs400_timing;\n\tu32 tuned_sample;\n\tu32 cur_speed;\n\tu32 dqs_delay;\n\tu32 saved_dqs_en;\n\tu32 saved_strobe_ctrl;\n};\n\nstruct dw_mci_rockchip_priv_data {\n\tstruct clk *drv_clk;\n\tstruct clk *sample_clk;\n\tint default_sample_phase;\n\tint num_phases;\n\tbool internal_phase;\n\tint sample_phase;\n\tint drv_phase;\n};\n\nstruct dw_mci_slot {\n\tstruct mmc_host *mmc;\n\tstruct dw_mci *host;\n\tu32 ctype;\n\tstruct mmc_request *mrq;\n\tstruct list_head queue_node;\n\tunsigned int clock;\n\tunsigned int __clk_old;\n\tlong unsigned int flags;\n\tint id;\n\tint sdio_id;\n};\n\nstruct pci_eq_presets {\n\tu16 eq_presets_8gts[16];\n\tu8 eq_presets_Ngts[48];\n};\n\nstruct dw_pcie_host_ops;\n\nstruct pci_host_bridge;\n\nstruct dw_pcie_rp {\n\tbool use_imsi_rx: 1;\n\tbool cfg0_io_shared: 1;\n\tu64 cfg0_base;\n\tvoid *va_cfg0_base;\n\tu32 cfg0_size;\n\tresource_size_t io_base;\n\tphys_addr_t io_bus_addr;\n\tu32 io_size;\n\tint irq;\n\tconst struct dw_pcie_host_ops *ops;\n\tint msi_irq[8];\n\tstruct irq_domain *irq_domain;\n\tdma_addr_t msi_data;\n\tstruct irq_chip *msi_irq_chip;\n\tu32 num_vectors;\n\tu32 irq_mask[8];\n\tstruct pci_host_bridge *bridge;\n\traw_spinlock_t lock;\n\tlong unsigned int msi_irq_in_use[4];\n\tbool use_atu_msg;\n\tint msg_atu_index;\n\tstruct resource *msg_res;\n\tstruct pci_eq_presets presets;\n\tstruct pci_config_window *cfg;\n\tbool ecam_enabled;\n\tbool native_ecam;\n\tbool skip_l23_ready;\n};\n\nstruct pci_epc;\n\nstruct dw_pcie_ep_ops;\n\nstruct dw_pcie_ep {\n\tstruct pci_epc *epc;\n\tstruct list_head func_list;\n\tconst struct dw_pcie_ep_ops *ops;\n\tphys_addr_t phys_base;\n\tsize_t addr_size;\n\tsize_t page_size;\n\tphys_addr_t *outbound_addr;\n\tlong unsigned int *ib_window_map;\n\tlong unsigned int *ob_window_map;\n\tvoid *msi_mem;\n\tphys_addr_t msi_mem_phys;\n\tbool msi_iatu_mapped;\n\tu64 msi_msg_addr;\n\tsize_t msi_map_size;\n};\n\nstruct reset_control_bulk_data {\n\tconst char *id;\n\tstruct reset_control *rstc;\n};\n\nstruct dw_pcie_ops;\n\nstruct pci_ptm_debugfs;\n\nstruct dw_pcie {\n\tstruct device *dev;\n\tvoid *dbi_base;\n\tresource_size_t dbi_phys_addr;\n\tvoid *dbi_base2;\n\tvoid *atu_base;\n\tvoid *elbi_base;\n\tresource_size_t atu_phys_addr;\n\tsize_t atu_size;\n\tresource_size_t parent_bus_offset;\n\tu32 num_ib_windows;\n\tu32 num_ob_windows;\n\tu32 region_align;\n\tu64 region_limit;\n\tstruct dw_pcie_rp pp;\n\tstruct dw_pcie_ep ep;\n\tconst struct dw_pcie_ops *ops;\n\tu32 version;\n\tu32 type;\n\tlong unsigned int caps;\n\tint num_lanes;\n\tint max_link_speed;\n\tu8 n_fts[2];\n\tstruct dw_edma_chip edma;\n\tbool l1ss_support;\n\tstruct clk_bulk_data app_clks[3];\n\tstruct clk_bulk_data core_clks[4];\n\tstruct reset_control_bulk_data app_rsts[3];\n\tstruct reset_control_bulk_data core_rsts[7];\n\tstruct gpio_desc *pe_rst;\n\tbool suspended;\n\tstruct debugfs_info *debugfs;\n\tenum dw_pcie_device_mode mode;\n\tu16 ptm_vsec_offset;\n\tstruct pci_ptm_debugfs *ptm_debugfs;\n\tbool use_parent_dt_ranges;\n};\n\nstruct pci_epf_bar;\n\nstruct dw_pcie_ep_func {\n\tstruct list_head list;\n\tu8 func_no;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 bar_to_atu[6];\n\tstruct pci_epf_bar *epf_bar[6];\n\tu32 *ib_atu_indexes[6];\n\tunsigned int num_ib_atu_indexes[6];\n};\n\nstruct pci_epc_features;\n\nstruct dw_pcie_ep_ops {\n\tvoid (*pre_init)(struct dw_pcie_ep *);\n\tvoid (*init)(struct dw_pcie_ep *);\n\tint (*raise_irq)(struct dw_pcie_ep *, u8, unsigned int, u16);\n\tconst struct pci_epc_features * (*get_features)(struct dw_pcie_ep *);\n\tunsigned int (*get_dbi_offset)(struct dw_pcie_ep *, u8);\n\tunsigned int (*get_dbi2_offset)(struct dw_pcie_ep *, u8);\n};\n\nstruct dw_pcie_host_ops {\n\tint (*init)(struct dw_pcie_rp *);\n\tvoid (*deinit)(struct dw_pcie_rp *);\n\tvoid (*post_init)(struct dw_pcie_rp *);\n\tint (*msi_init)(struct dw_pcie_rp *);\n\tvoid (*pme_turn_off)(struct dw_pcie_rp *);\n};\n\nstruct dw_pcie_ob_atu_cfg {\n\tint index;\n\tint type;\n\tu8 func_no;\n\tu8 code;\n\tu8 routing;\n\tu32 ctrl2;\n\tu64 parent_bus_addr;\n\tu64 pci_addr;\n\tu64 size;\n};\n\nstruct dw_pcie_ops {\n\tu64 (*cpu_addr_fixup)(struct dw_pcie *, u64);\n\tu32 (*read_dbi)(struct dw_pcie *, void *, u32, size_t);\n\tvoid (*write_dbi)(struct dw_pcie *, void *, u32, size_t, u32);\n\tvoid (*write_dbi2)(struct dw_pcie *, void *, u32, size_t, u32);\n\tbool (*link_up)(struct dw_pcie *);\n\tenum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *);\n\tint (*start_link)(struct dw_pcie *);\n\tvoid (*stop_link)(struct dw_pcie *);\n};\n\nstruct dw_wdt_timeout {\n\tu32 top_val;\n\tunsigned int sec;\n\tunsigned int msec;\n};\n\nstruct watchdog_info;\n\nstruct watchdog_ops;\n\nstruct watchdog_governor;\n\nstruct watchdog_core_data;\n\nstruct watchdog_device {\n\tint id;\n\tstruct device *parent;\n\tconst struct attribute_group **groups;\n\tconst struct watchdog_info *info;\n\tconst struct watchdog_ops *ops;\n\tconst struct watchdog_governor *gov;\n\tunsigned int bootstatus;\n\tunsigned int timeout;\n\tunsigned int pretimeout;\n\tunsigned int min_timeout;\n\tunsigned int max_timeout;\n\tunsigned int min_hw_heartbeat_ms;\n\tunsigned int max_hw_heartbeat_ms;\n\tstruct notifier_block reboot_nb;\n\tstruct notifier_block restart_nb;\n\tstruct notifier_block pm_nb;\n\tvoid *driver_data;\n\tstruct watchdog_core_data *wd_data;\n\tlong unsigned int status;\n\tstruct list_head deferred;\n};\n\nstruct dw_wdt {\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tlong unsigned int rate;\n\tenum dw_wdt_rmod rmod;\n\tstruct dw_wdt_timeout timeouts[16];\n\tstruct watchdog_device wdd;\n\tstruct reset_control *rst;\n\tu32 control;\n\tu32 timeout;\n\tstruct dentry *dbgfs_dir;\n};\n\nstruct dwapb_context {\n\tu32 data;\n\tu32 dir;\n\tu32 ext;\n\tu32 int_en;\n\tu32 int_mask;\n\tu32 int_type;\n\tu32 int_pol;\n\tu32 int_deb;\n\tu32 wake_en;\n};\n\nstruct dwapb_gpio_port;\n\nstruct dwapb_gpio {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct dwapb_gpio_port *ports;\n\tunsigned int nr_ports;\n\tunsigned int flags;\n\tstruct reset_control *rst;\n\tstruct clk_bulk_data clks[2];\n};\n\nstruct dwapb_gpio_port_irqchip;\n\nstruct dwapb_gpio_port {\n\tstruct gpio_generic_chip chip;\n\tstruct dwapb_gpio_port_irqchip *pirq;\n\tstruct dwapb_gpio *gpio;\n\tstruct dwapb_context *ctx;\n\tunsigned int idx;\n};\n\nstruct dwapb_gpio_port_irqchip {\n\tunsigned int nr_irqs;\n\tunsigned int irq[32];\n};\n\nstruct dwapb_port_property;\n\nstruct dwapb_platform_data {\n\tstruct dwapb_port_property *properties;\n\tunsigned int nports;\n};\n\nstruct dwapb_port_property {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int idx;\n\tunsigned int ngpio;\n\tunsigned int gpio_base;\n\tint irq[32];\n};\n\nstruct dwc2_core_params {\n\tstruct usb_otg_caps otg_caps;\n\tu8 phy_type;\n\tu8 speed;\n\tu8 phy_utmi_width;\n\tbool eusb2_disc;\n\tbool phy_ulpi_ddr;\n\tbool phy_ulpi_ext_vbus;\n\tbool enable_dynamic_fifo;\n\tbool en_multiple_tx_fifo;\n\tbool i2c_enable;\n\tbool acg_enable;\n\tbool ulpi_fs_ls;\n\tbool ts_dline;\n\tbool reload_ctl;\n\tbool uframe_sched;\n\tbool external_id_pin_ctl;\n\tint power_down;\n\tbool no_clock_gating;\n\tbool lpm;\n\tbool lpm_clock_gating;\n\tbool besl;\n\tbool hird_threshold_en;\n\tbool service_interval;\n\tu8 hird_threshold;\n\tbool activate_stm_fs_transceiver;\n\tbool activate_stm_id_vb_detection;\n\tbool activate_ingenic_overcurrent_detection;\n\tbool ipg_isoc_en;\n\tu16 max_packet_count;\n\tu32 max_transfer_size;\n\tu32 ahbcfg;\n\tu32 ref_clk_per;\n\tu16 sof_cnt_wkup_alert;\n\tbool host_dma;\n\tbool dma_desc_enable;\n\tbool dma_desc_fs_enable;\n\tbool host_support_fs_ls_low_power;\n\tbool host_ls_low_power_phy_clk;\n\tbool oc_disable;\n\tu8 host_channels;\n\tu16 host_rx_fifo_size;\n\tu16 host_nperio_tx_fifo_size;\n\tu16 host_perio_tx_fifo_size;\n\tbool g_dma;\n\tbool g_dma_desc;\n\tu32 g_rx_fifo_size;\n\tu32 g_np_tx_fifo_size;\n\tu32 g_tx_fifo_size[16];\n\tbool change_speed_quirk;\n};\n\nstruct dwc2_dma_desc {\n\tu32 status;\n\tu32 buf;\n};\n\nstruct dwc2_dregs_backup {\n\tu32 dcfg;\n\tu32 dctl;\n\tu32 daintmsk;\n\tu32 diepmsk;\n\tu32 doepmsk;\n\tu32 diepctl[16];\n\tu32 dieptsiz[16];\n\tu32 diepdma[16];\n\tu32 doepctl[16];\n\tu32 doeptsiz[16];\n\tu32 doepdma[16];\n\tu32 dtxfsiz[16];\n\tbool valid;\n};\n\nstruct dwc2_gregs_backup {\n\tu32 gintsts;\n\tu32 gotgctl;\n\tu32 gintmsk;\n\tu32 gahbcfg;\n\tu32 gusbcfg;\n\tu32 grxfsiz;\n\tu32 gnptxfsiz;\n\tu32 gi2cctl;\n\tu32 glpmcfg;\n\tu32 pcgcctl;\n\tu32 pcgcctl1;\n\tu32 gdfifocfg;\n\tu32 gpwrdn;\n\tbool valid;\n};\n\nunion dwc2_hcd_internal_flags {\n\tu32 d32;\n\tstruct {\n\t\tunsigned int port_connect_status_change: 1;\n\t\tunsigned int port_connect_status: 1;\n\t\tunsigned int port_reset_change: 1;\n\t\tunsigned int port_enable_change: 1;\n\t\tunsigned int port_suspend_change: 1;\n\t\tunsigned int port_over_current_change: 1;\n\t\tunsigned int port_l1_change: 1;\n\t\tunsigned int reserved: 25;\n\t} b;\n};\n\nstruct dwc2_hcd_iso_packet_desc {\n\tu32 offset;\n\tu32 length;\n\tu32 actual_length;\n\tu32 status;\n};\n\nstruct dwc2_hcd_pipe_info {\n\tu8 dev_addr;\n\tu8 ep_num;\n\tu8 pipe_type;\n\tu8 pipe_dir;\n\tu16 maxp;\n\tu16 maxp_mult;\n};\n\nstruct dwc2_qtd;\n\nstruct dwc2_hcd_urb {\n\tvoid *priv;\n\tstruct dwc2_qtd *qtd;\n\tvoid *buf;\n\tdma_addr_t dma;\n\tvoid *setup_packet;\n\tdma_addr_t setup_dma;\n\tu32 length;\n\tu32 actual_length;\n\tu32 status;\n\tu32 error_count;\n\tu32 packet_count;\n\tu32 flags;\n\tu16 interval;\n\tstruct dwc2_hcd_pipe_info pipe_info;\n\tstruct dwc2_hcd_iso_packet_desc iso_descs[0];\n};\n\nstruct dwc2_qh;\n\nstruct dwc2_host_chan {\n\tu8 hc_num;\n\tunsigned int dev_addr: 7;\n\tunsigned int ep_num: 4;\n\tunsigned int ep_is_in: 1;\n\tunsigned int speed: 4;\n\tunsigned int ep_type: 2;\n\tint: 6;\n\tunsigned int max_packet: 11;\n\tunsigned int data_pid_start: 2;\n\tunsigned int multi_count: 2;\n\tu8 *xfer_buf;\n\tdma_addr_t xfer_dma;\n\tdma_addr_t align_buf;\n\tu32 xfer_len;\n\tu32 xfer_count;\n\tu16 start_pkt_count;\n\tu8 xfer_started;\n\tu8 do_ping;\n\tu8 error_state;\n\tu8 halt_on_queue;\n\tu8 halt_pending;\n\tu8 do_split;\n\tu8 complete_split;\n\tu8 hub_addr;\n\tu8 hub_port;\n\tu8 xact_pos;\n\tu8 requests;\n\tu8 schinfo;\n\tu16 ntd;\n\tenum dwc2_halt_status halt_status;\n\tu32 hcint;\n\tstruct dwc2_qh *qh;\n\tstruct list_head hc_list_entry;\n\tdma_addr_t desc_list_addr;\n\tu32 desc_list_sz;\n\tstruct list_head split_order_list_entry;\n};\n\nstruct dwc2_hregs_backup {\n\tu32 hcfg;\n\tu32 hflbaddr;\n\tu32 haintmsk;\n\tu32 hcchar[16];\n\tu32 hcsplt[16];\n\tu32 hcintmsk[16];\n\tu32 hctsiz[16];\n\tu32 hcidma[16];\n\tu32 hcidmab[16];\n\tu32 hprt0;\n\tu32 hfir;\n\tu32 hptxfsiz;\n\tbool valid;\n};\n\nstruct dwc2_hs_transfer_time {\n\tu32 start_schedule_us;\n\tu16 duration_us;\n};\n\nstruct dwc2_hw_params {\n\tunsigned int op_mode: 3;\n\tunsigned int arch: 2;\n\tunsigned int dma_desc_enable: 1;\n\tunsigned int enable_dynamic_fifo: 1;\n\tunsigned int en_multiple_tx_fifo: 1;\n\tunsigned int rx_fifo_size: 16;\n\tint: 8;\n\tunsigned int host_nperio_tx_fifo_size: 16;\n\tunsigned int dev_nperio_tx_fifo_size: 16;\n\tunsigned int host_perio_tx_fifo_size: 16;\n\tunsigned int nperio_tx_q_depth: 3;\n\tunsigned int host_perio_tx_q_depth: 3;\n\tunsigned int dev_token_q_depth: 5;\n\tint: 5;\n\tunsigned int max_transfer_size: 26;\n\tlong: 6;\n\tunsigned int max_packet_count: 11;\n\tunsigned int host_channels: 5;\n\tunsigned int hs_phy_type: 2;\n\tunsigned int fs_phy_type: 2;\n\tunsigned int i2c_enable: 1;\n\tunsigned int acg_enable: 1;\n\tunsigned int num_dev_ep: 4;\n\tunsigned int num_dev_in_eps: 4;\n\tint: 2;\n\tunsigned int num_dev_perio_in_ep: 4;\n\tunsigned int total_fifo_size: 16;\n\tunsigned int power_optimized: 1;\n\tunsigned int hibernation: 1;\n\tunsigned int utmi_phy_data_width: 2;\n\tunsigned int lpm_mode: 1;\n\tunsigned int ipg_isoc_en: 1;\n\tunsigned int service_interval_mode: 1;\n\tu32 snpsid;\n\tu32 dev_ep_dirs;\n\tu32 g_tx_fifo_size[16];\n};\n\nstruct regulator_bulk_data {\n\tconst char *supply;\n\tstruct regulator *consumer;\n\tint init_load_uA;\n\tint ret;\n};\n\nstruct dwc2_hsotg_plat;\n\nstruct dwc2_hsotg_ep;\n\nstruct dwc2_hsotg {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct dwc2_hw_params hw_params;\n\tstruct dwc2_core_params params;\n\tenum usb_otg_state op_state;\n\tenum usb_dr_mode dr_mode;\n\tstruct usb_role_switch *role_sw;\n\tenum usb_dr_mode role_sw_default_mode;\n\tunsigned int hcd_enabled: 1;\n\tunsigned int gadget_enabled: 1;\n\tunsigned int ll_hw_enabled: 1;\n\tunsigned int hibernated: 1;\n\tunsigned int in_ppd: 1;\n\tbool bus_suspended;\n\tunsigned int reset_phy_on_wake: 1;\n\tunsigned int need_phy_for_wake: 1;\n\tunsigned int phy_off_for_suspend: 1;\n\tu16 frame_number;\n\tstruct phy *phy;\n\tstruct usb_phy *uphy;\n\tstruct dwc2_hsotg_plat *plat;\n\tstruct regulator_bulk_data supplies[2];\n\tstruct regulator *vbus_supply;\n\tstruct regulator *usb33d;\n\tspinlock_t lock;\n\tvoid *priv;\n\tint irq;\n\tstruct clk *clk;\n\tstruct clk *utmi_clk;\n\tstruct reset_control *reset;\n\tstruct reset_control *reset_ecc;\n\tunsigned int queuing_high_bandwidth: 1;\n\tunsigned int srp_success: 1;\n\tstruct workqueue_struct *wq_otg;\n\tstruct work_struct wf_otg;\n\tstruct timer_list wkp_timer;\n\tenum dwc2_lx_state lx_state;\n\tstruct dwc2_gregs_backup gr_backup;\n\tstruct dwc2_dregs_backup dr_backup;\n\tstruct dwc2_hregs_backup hr_backup;\n\tstruct dentry *debug_root;\n\tstruct debugfs_regset32 *regset;\n\tbool needs_byte_swap;\n\tunion dwc2_hcd_internal_flags flags;\n\tstruct list_head non_periodic_sched_inactive;\n\tstruct list_head non_periodic_sched_waiting;\n\tstruct list_head non_periodic_sched_active;\n\tstruct list_head *non_periodic_qh_ptr;\n\tstruct list_head periodic_sched_inactive;\n\tstruct list_head periodic_sched_ready;\n\tstruct list_head periodic_sched_assigned;\n\tstruct list_head periodic_sched_queued;\n\tstruct list_head split_order;\n\tu16 periodic_usecs;\n\tlong unsigned int hs_periodic_bitmap[13];\n\tu16 periodic_qh_count;\n\tbool new_connection;\n\tu16 last_frame_num;\n\tstruct list_head free_hc_list;\n\tint periodic_channels;\n\tint non_periodic_channels;\n\tint available_host_channels;\n\tstruct dwc2_host_chan *hc_ptr_array[16];\n\tu8 *status_buf;\n\tdma_addr_t status_buf_dma;\n\tstruct delayed_work start_work;\n\tstruct delayed_work reset_work;\n\tstruct work_struct phy_reset_work;\n\tu8 otg_port;\n\tu32 *frame_list;\n\tdma_addr_t frame_list_dma;\n\tu32 frame_list_sz;\n\tstruct kmem_cache *desc_gen_cache;\n\tstruct kmem_cache *desc_hsisoc_cache;\n\tstruct kmem_cache *unaligned_cache;\n\tstruct usb_gadget_driver *driver;\n\tint fifo_mem;\n\tunsigned int dedicated_fifos: 1;\n\tunsigned char num_of_eps;\n\tu32 fifo_map;\n\tstruct usb_request *ep0_reply;\n\tstruct usb_request *ctrl_req;\n\tvoid *ep0_buff;\n\tvoid *ctrl_buff;\n\tenum dwc2_ep0_state ep0_state;\n\tunsigned int delayed_status: 1;\n\tu8 test_mode;\n\tdma_addr_t setup_desc_dma[2];\n\tstruct dwc2_dma_desc *setup_desc[2];\n\tdma_addr_t ctrl_in_desc_dma;\n\tstruct dwc2_dma_desc *ctrl_in_desc;\n\tdma_addr_t ctrl_out_desc_dma;\n\tstruct dwc2_dma_desc *ctrl_out_desc;\n\tstruct usb_gadget gadget;\n\tunsigned int enabled: 1;\n\tunsigned int connected: 1;\n\tunsigned int remote_wakeup_allowed: 1;\n\tstruct dwc2_hsotg_ep *eps_in[16];\n\tstruct dwc2_hsotg_ep *eps_out[16];\n};\n\nstruct dwc2_hsotg_req;\n\nstruct dwc2_hsotg_ep {\n\tstruct usb_ep ep;\n\tstruct list_head queue;\n\tstruct dwc2_hsotg *parent;\n\tstruct dwc2_hsotg_req *req;\n\tstruct dentry *debugfs;\n\tlong unsigned int total_data;\n\tunsigned int size_loaded;\n\tunsigned int last_load;\n\tunsigned int fifo_load;\n\tshort unsigned int fifo_size;\n\tshort unsigned int fifo_index;\n\tunsigned char dir_in;\n\tunsigned char map_dir;\n\tunsigned char index;\n\tunsigned char mc;\n\tu16 interval;\n\tunsigned int halted: 1;\n\tunsigned int periodic: 1;\n\tunsigned int isochronous: 1;\n\tunsigned int send_zlp: 1;\n\tunsigned int wedged: 1;\n\tunsigned int target_frame;\n\tbool frame_overrun;\n\tdma_addr_t desc_list_dma;\n\tstruct dwc2_dma_desc *desc_list;\n\tu8 desc_count;\n\tunsigned int next_desc;\n\tunsigned int compl_desc;\n\tchar name[10];\n};\n\nstruct dwc2_hsotg_plat {\n\tenum dwc2_hsotg_dmamode dma;\n\tunsigned int is_osc: 1;\n\tint phy_type;\n\tint (*phy_init)(struct platform_device *, int);\n\tint (*phy_exit)(struct platform_device *, int);\n};\n\nstruct dwc2_hsotg_req {\n\tstruct usb_request req;\n\tstruct list_head queue;\n\tvoid *saved_req_buf;\n};\n\nstruct dwc2_tt;\n\nstruct dwc2_qh {\n\tstruct dwc2_hsotg *hsotg;\n\tu8 ep_type;\n\tu8 ep_is_in;\n\tu16 maxp;\n\tu16 maxp_mult;\n\tu8 dev_speed;\n\tu8 data_toggle;\n\tu8 ping_state;\n\tu8 do_split;\n\tu8 td_first;\n\tu8 td_last;\n\tu16 host_us;\n\tu16 device_us;\n\tu16 host_interval;\n\tu16 device_interval;\n\tu16 next_active_frame;\n\tu16 start_active_frame;\n\ts16 num_hs_transfers;\n\tstruct dwc2_hs_transfer_time hs_transfers[8];\n\tu32 ls_start_schedule_slice;\n\tu16 ntd;\n\tu8 *dw_align_buf;\n\tdma_addr_t dw_align_buf_dma;\n\tstruct list_head qtd_list;\n\tstruct dwc2_host_chan *channel;\n\tstruct list_head qh_list_entry;\n\tstruct dwc2_dma_desc *desc_list;\n\tdma_addr_t desc_list_dma;\n\tu32 desc_list_sz;\n\tu32 *n_bytes;\n\tstruct timer_list unreserve_timer;\n\tstruct hrtimer wait_timer;\n\tstruct dwc2_tt *dwc_tt;\n\tint ttport;\n\tunsigned int tt_buffer_dirty: 1;\n\tunsigned int unreserve_pending: 1;\n\tunsigned int schedule_low_speed: 1;\n\tunsigned int want_wait: 1;\n\tunsigned int wait_timer_cancel: 1;\n};\n\nstruct dwc2_qtd {\n\tenum dwc2_control_phase control_phase;\n\tu8 in_process;\n\tu8 data_toggle;\n\tu8 complete_split;\n\tu8 isoc_split_pos;\n\tu16 isoc_frame_index;\n\tu16 isoc_split_offset;\n\tu16 isoc_td_last;\n\tu16 isoc_td_first;\n\tu32 ssplit_out_xfer_count;\n\tu8 error_count;\n\tu8 n_desc;\n\tu16 isoc_frame_index_last;\n\tu16 num_naks;\n\tstruct dwc2_hcd_urb *urb;\n\tstruct dwc2_qh *qh;\n\tstruct list_head qtd_list_entry;\n};\n\nstruct usb_tt;\n\nstruct dwc2_tt {\n\tint refcount;\n\tstruct usb_tt *usb_tt;\n\tlong unsigned int periodic_bitmaps[0];\n};\n\nstruct dwc3_ep;\n\nstruct dwc3_trb;\n\nstruct dwc3_request {\n\tstruct usb_request request;\n\tstruct list_head list;\n\tstruct dwc3_ep *dep;\n\tstruct scatterlist *start_sg;\n\tunsigned int num_pending_sgs;\n\tunsigned int remaining;\n\tunsigned int status;\n\tu8 epnum;\n\tstruct dwc3_trb *trb;\n\tdma_addr_t trb_dma;\n\tunsigned int num_trbs;\n\tunsigned int direction: 1;\n\tunsigned int mapped: 1;\n};\n\nstruct dwc3_hwparams {\n\tu32 hwparams0;\n\tu32 hwparams1;\n\tu32 hwparams2;\n\tu32 hwparams3;\n\tu32 hwparams4;\n\tu32 hwparams5;\n\tu32 hwparams6;\n\tu32 hwparams7;\n\tu32 hwparams8;\n\tu32 hwparams9;\n};\n\nstruct dwc3_event_buffer;\n\nstruct dwc3_glue_ops;\n\nstruct dwc3 {\n\tstruct work_struct drd_work;\n\tstruct dwc3_trb *ep0_trb;\n\tvoid *bounce;\n\tu8 *setup_buf;\n\tdma_addr_t ep0_trb_addr;\n\tdma_addr_t bounce_addr;\n\tstruct dwc3_request ep0_usb_req;\n\tstruct completion ep0_in_setup;\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tstruct device *dev;\n\tstruct device *sysdev;\n\tstruct platform_device *xhci;\n\tstruct resource xhci_resources[2];\n\tstruct dwc3_event_buffer *ev_buf;\n\tstruct dwc3_ep *eps[32];\n\tstruct usb_gadget *gadget;\n\tstruct usb_gadget_driver *gadget_driver;\n\tconst struct dwc3_glue_ops *glue_ops;\n\tstruct clk *bus_clk;\n\tstruct clk *ref_clk;\n\tstruct clk *susp_clk;\n\tstruct clk *utmi_clk;\n\tstruct clk *pipe_clk;\n\tstruct reset_control *reset;\n\tstruct usb_phy *usb2_phy;\n\tstruct usb_phy *usb3_phy;\n\tstruct phy *usb2_generic_phy[15];\n\tstruct phy *usb3_generic_phy[4];\n\tu8 num_usb2_ports;\n\tu8 num_usb3_ports;\n\tbool phys_ready;\n\tstruct ulpi *ulpi;\n\tbool ulpi_ready;\n\tvoid *regs;\n\tsize_t regs_size;\n\tenum usb_dr_mode dr_mode;\n\tu32 current_dr_role;\n\tu32 desired_dr_role;\n\tstruct extcon_dev *edev;\n\tstruct notifier_block edev_nb;\n\tenum usb_phy_interface hsphy_mode;\n\tstruct usb_role_switch *role_sw;\n\tenum usb_dr_mode role_switch_default_mode;\n\tstruct power_supply *usb_psy;\n\tstruct work_struct vbus_draw_work;\n\tunsigned int current_limit;\n\tu32 fladj;\n\tu32 ref_clk_per;\n\tu32 irq_gadget;\n\tu32 otg_irq;\n\tu32 current_otg_role;\n\tu32 desired_otg_role;\n\tbool otg_restart_host;\n\tu32 u1u2;\n\tu32 maximum_speed;\n\tu32 gadget_max_speed;\n\tenum usb_ssp_rate max_ssp_rate;\n\tenum usb_ssp_rate gadget_ssp_rate;\n\tu32 ip;\n\tu32 revision;\n\tu32 version_type;\n\tenum dwc3_ep0_next ep0_next_event;\n\tenum dwc3_ep0_state ep0state;\n\tenum dwc3_link_state link_state;\n\tu16 u2sel;\n\tu16 u2pel;\n\tu8 u1sel;\n\tu8 u1pel;\n\tu8 speed;\n\tu8 num_eps;\n\tstruct dwc3_hwparams hwparams;\n\tstruct debugfs_regset32 *regset;\n\tu32 dbg_lsp_select;\n\tu8 test_mode;\n\tu8 test_mode_nr;\n\tu8 lpm_nyet_threshold;\n\tu8 hird_threshold;\n\tu8 rx_thr_num_pkt;\n\tu8 rx_max_burst;\n\tu8 tx_thr_num_pkt;\n\tu8 tx_max_burst;\n\tu8 rx_thr_num_pkt_prd;\n\tu8 rx_max_burst_prd;\n\tu8 tx_thr_num_pkt_prd;\n\tu8 tx_max_burst_prd;\n\tu8 tx_fifo_resize_max_num;\n\tu8 clear_stall_protocol;\n\tu16 num_hc_interrupters;\n\tconst char *hsphy_interface;\n\tunsigned int connected: 1;\n\tunsigned int softconnect: 1;\n\tunsigned int delayed_status: 1;\n\tunsigned int ep0_bounced: 1;\n\tunsigned int ep0_expect_in: 1;\n\tunsigned int sysdev_is_parent: 1;\n\tunsigned int has_lpm_erratum: 1;\n\tunsigned int is_utmi_l1_suspend: 1;\n\tunsigned int is_fpga: 1;\n\tunsigned int pending_events: 1;\n\tunsigned int do_fifo_resize: 1;\n\tunsigned int pullups_connected: 1;\n\tunsigned int setup_packet_pending: 1;\n\tunsigned int three_stage_setup: 1;\n\tunsigned int dis_start_transfer_quirk: 1;\n\tunsigned int usb3_lpm_capable: 1;\n\tunsigned int usb2_lpm_disable: 1;\n\tunsigned int usb2_gadget_lpm_disable: 1;\n\tunsigned int disable_scramble_quirk: 1;\n\tunsigned int u2exit_lfps_quirk: 1;\n\tunsigned int u2ss_inp3_quirk: 1;\n\tunsigned int req_p1p2p3_quirk: 1;\n\tunsigned int del_p1p2p3_quirk: 1;\n\tunsigned int del_phy_power_chg_quirk: 1;\n\tunsigned int lfps_filter_quirk: 1;\n\tunsigned int rx_detect_poll_quirk: 1;\n\tunsigned int dis_u3_susphy_quirk: 1;\n\tunsigned int dis_u2_susphy_quirk: 1;\n\tunsigned int dis_enblslpm_quirk: 1;\n\tunsigned int dis_u1_entry_quirk: 1;\n\tunsigned int dis_u2_entry_quirk: 1;\n\tunsigned int dis_rxdet_inp3_quirk: 1;\n\tunsigned int dis_u2_freeclk_exists_quirk: 1;\n\tunsigned int dis_del_phy_power_chg_quirk: 1;\n\tunsigned int dis_tx_ipgap_linecheck_quirk: 1;\n\tunsigned int resume_hs_terminations: 1;\n\tunsigned int ulpi_ext_vbus_drv: 1;\n\tunsigned int parkmode_disable_ss_quirk: 1;\n\tunsigned int parkmode_disable_hs_quirk: 1;\n\tunsigned int gfladj_refclk_lpm_sel: 1;\n\tunsigned int tx_de_emphasis_quirk: 1;\n\tunsigned int tx_de_emphasis: 2;\n\tunsigned int dis_metastability_quirk: 1;\n\tunsigned int dis_split_quirk: 1;\n\tunsigned int async_callbacks: 1;\n\tunsigned int sys_wakeup: 1;\n\tunsigned int wakeup_configured: 1;\n\tunsigned int suspended: 1;\n\tunsigned int susphy_state: 1;\n\tu16 imod_interval;\n\tint max_cfg_eps;\n\tint last_fifo_depth;\n\tint num_ep_resized;\n\tstruct dentry *debug_root;\n\tu32 gsbuscfg0_reqinfo;\n\tu32 wakeup_pending_funcs;\n};\n\nstruct dwc3_am62 {\n\tstruct device *dev;\n\tvoid *usbss;\n\tstruct clk *usb2_refclk;\n\tint rate_code;\n\tstruct regmap *syscon;\n\tunsigned int offset;\n\tunsigned int vbus_divider;\n\tu32 wakeup_stat;\n\tvoid *phy_regs;\n};\n\nstruct dwc3_apple {\n\tstruct dwc3 dwc;\n\tstruct device *dev;\n\tstruct resource *mmio_resource;\n\tvoid *apple_regs;\n\tstruct reset_control *reset;\n\tstruct usb_role_switch *role_sw;\n\tstruct mutex lock;\n\tenum dwc3_apple_state state;\n};\n\nstruct dwc3_ep {\n\tstruct usb_ep endpoint;\n\tstruct delayed_work nostream_work;\n\tstruct list_head cancelled_list;\n\tstruct list_head pending_list;\n\tstruct list_head started_list;\n\tstruct dwc3_trb *trb_pool;\n\tdma_addr_t trb_pool_dma;\n\tstruct dwc3 *dwc;\n\tu32 saved_state;\n\tunsigned int flags;\n\tu8 trb_enqueue;\n\tu8 trb_dequeue;\n\tu8 number;\n\tu8 type;\n\tu8 resource_index;\n\tu32 frame_number;\n\tu32 interval;\n\tchar name[20];\n\tunsigned int direction: 1;\n\tunsigned int stream_capable: 1;\n\tu8 combo_num;\n\tint start_cmd_status;\n};\n\nstruct dwc3_ep_file_map {\n\tconst char name[25];\n\tconst struct file_operations * const fops;\n};\n\nstruct dwc3_event_type {\n\tu32 is_devspec: 1;\n\tu32 type: 7;\n\tu32 reserved8_31: 24;\n};\n\nstruct dwc3_event_depevt {\n\tu32 one_bit: 1;\n\tu32 endpoint_number: 5;\n\tu32 endpoint_event: 4;\n\tu32 reserved11_10: 2;\n\tu32 status: 4;\n\tu32 parameters: 16;\n};\n\nstruct dwc3_event_devt {\n\tu32 one_bit: 1;\n\tu32 device_event: 7;\n\tu32 type: 4;\n\tu32 reserved15_12: 4;\n\tu32 event_info: 9;\n\tu32 reserved31_25: 7;\n};\n\nstruct dwc3_event_gevt {\n\tu32 one_bit: 1;\n\tu32 device_event: 7;\n\tu32 phy_port_number: 4;\n\tu32 reserved31_12: 20;\n};\n\nunion dwc3_event {\n\tu32 raw;\n\tstruct dwc3_event_type type;\n\tstruct dwc3_event_depevt depevt;\n\tstruct dwc3_event_devt devt;\n\tstruct dwc3_event_gevt gevt;\n};\n\nstruct dwc3_event_buffer {\n\tvoid *buf;\n\tvoid *cache;\n\tunsigned int length;\n\tunsigned int lpos;\n\tunsigned int count;\n\tunsigned int flags;\n\tdma_addr_t dma;\n\tstruct dwc3 *dwc;\n};\n\nstruct dwc3_exynos {\n\tstruct device *dev;\n\tconst char **clk_names;\n\tstruct clk *clks[4];\n\tint num_clks;\n\tint suspend_clk_idx;\n\tstruct regulator *vdd33;\n\tstruct regulator *vdd10;\n};\n\nstruct dwc3_exynos_driverdata {\n\tconst char *clk_names[4];\n\tint num_clks;\n\tint suspend_clk_idx;\n};\n\nstruct dwc3_gadget_ep_cmd_params {\n\tu32 param2;\n\tu32 param1;\n\tu32 param0;\n};\n\nstruct dwc3_generic {\n\tstruct device *dev;\n\tstruct dwc3 dwc;\n\tstruct clk_bulk_data *clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n};\n\nstruct dwc3_properties {\n\tu32 gsbuscfg0_reqinfo;\n};\n\nstruct dwc3_generic_config {\n\tint (*init)(struct dwc3_generic *);\n\tstruct dwc3_properties properties;\n};\n\nstruct dwc3_glue_ops {\n\tvoid (*pre_set_role)(struct dwc3 *, enum usb_role);\n\tvoid (*pre_run_stop)(struct dwc3 *, bool);\n};\n\nstruct dwc3_haps {\n\tstruct platform_device *dwc3;\n\tstruct pci_dev *pci;\n};\n\nstruct dwc3_imx8mp {\n\tstruct device *dev;\n\tstruct platform_device *dwc3_pdev;\n\tvoid *hsio_blk_base;\n\tvoid *glue_base;\n\tstruct clk *hsio_clk;\n\tstruct clk *suspend_clk;\n\tint irq;\n\tbool pm_suspended;\n\tbool wakeup_pending;\n};\n\nstruct dwc3_keystone {\n\tstruct device *dev;\n\tvoid *usbss;\n\tstruct phy *usb3_phy;\n};\n\ntypedef int (*usb_role_switch_set_t)(struct usb_role_switch *, enum usb_role);\n\ntypedef enum usb_role (*usb_role_switch_get_t)(struct usb_role_switch *);\n\nstruct usb_role_switch_desc {\n\tstruct fwnode_handle *fwnode;\n\tstruct device *usb2_port;\n\tstruct device *usb3_port;\n\tstruct device *udc;\n\tusb_role_switch_set_t set;\n\tusb_role_switch_get_t get;\n\tbool allow_userspace_control;\n\tvoid *driver_data;\n\tconst char *name;\n};\n\nstruct dwc3_meson_g12a_drvdata;\n\nstruct dwc3_meson_g12a {\n\tstruct device *dev;\n\tstruct regmap *u2p_regmap[3];\n\tstruct regmap *usb_glue_regmap;\n\tstruct reset_control *reset;\n\tstruct phy *phys[3];\n\tenum usb_dr_mode otg_mode;\n\tenum phy_mode otg_phy_mode;\n\tunsigned int usb2_ports;\n\tunsigned int usb3_ports;\n\tstruct regulator *vbus;\n\tstruct usb_role_switch_desc switch_desc;\n\tstruct usb_role_switch *role_switch;\n\tconst struct dwc3_meson_g12a_drvdata *drvdata;\n};\n\nstruct dwc3_meson_g12a_drvdata {\n\tbool otg_phy_host_port_disable;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tconst char * const *phy_names;\n\tint num_phys;\n\tint (*setup_regmaps)(struct dwc3_meson_g12a *, void *);\n\tint (*usb2_init_phy)(struct dwc3_meson_g12a *, int, enum phy_mode);\n\tint (*set_phy_mode)(struct dwc3_meson_g12a *, int, enum phy_mode);\n\tint (*usb_init)(struct dwc3_meson_g12a *);\n\tint (*usb_post_init)(struct dwc3_meson_g12a *);\n};\n\nstruct dwc3_of_simple {\n\tstruct device *dev;\n\tstruct clk_bulk_data *clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n\tbool need_reset;\n};\n\nstruct dwc3_pci {\n\tstruct platform_device *dwc3;\n\tstruct pci_dev *pci;\n\tguid_t guid;\n\tunsigned int has_dsm_for_pm: 1;\n\tstruct work_struct wakeup_work;\n};\n\nstruct dwc3_probe_data {\n\tstruct dwc3 *dwc;\n\tstruct resource *res;\n\tbool ignore_clocks_and_resets;\n\tbool skip_core_init_mode;\n\tstruct dwc3_properties properties;\n};\n\nstruct dwc3_qcom_port {\n\tint qusb2_phy_irq;\n\tint dp_hs_phy_irq;\n\tint dm_hs_phy_irq;\n\tint ss_phy_irq;\n\tenum usb_device_speed usb2_speed;\n};\n\nstruct icc_path;\n\nstruct dwc3_qcom {\n\tstruct device *dev;\n\tvoid *qscratch_base;\n\tstruct dwc3 dwc;\n\tstruct clk_bulk_data *clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n\tstruct dwc3_qcom_port ports[4];\n\tu8 num_ports;\n\tenum usb_dr_mode mode;\n\tbool is_suspended;\n\tbool pm_suspended;\n\tstruct icc_path *icc_path_ddr;\n\tstruct icc_path *icc_path_apps;\n\tenum usb_role current_role;\n};\n\nstruct dwc3_qcom___2 {\n\tstruct device *dev;\n\tvoid *qscratch_base;\n\tstruct platform_device *dwc3;\n\tstruct clk **clks;\n\tint num_clocks;\n\tstruct reset_control *resets;\n\tstruct dwc3_qcom_port ports[4];\n\tu8 num_ports;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *host_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block host_nb;\n\tenum usb_dr_mode mode;\n\tbool is_suspended;\n\tbool pm_suspended;\n\tstruct icc_path *icc_path_ddr;\n\tstruct icc_path *icc_path_apps;\n};\n\nstruct dwc3_rtk {\n\tstruct device *dev;\n\tvoid *regs;\n\tsize_t regs_size;\n\tvoid *pm_base;\n\tstruct dwc3 *dwc;\n\tenum usb_role cur_role;\n\tstruct usb_role_switch *role_switch;\n};\n\nstruct dwc3_trb {\n\tu32 bpl;\n\tu32 bph;\n\tu32 size;\n\tu32 ctrl;\n};\n\nstruct dwc3_xlnx {\n\tint num_clocks;\n\tstruct clk_bulk_data *clks;\n\tstruct device *dev;\n\tvoid *regs;\n\tint (*pltfm_init)(struct dwc3_xlnx *);\n\tstruct phy *usb3_phy;\n};\n\nstruct dwc_pcie_vsec_id {\n\tu16 vendor_id;\n\tu16 vsec_id;\n\tu8 vsec_rev;\n};\n\nstruct sdhci_pltfm_data {\n\tconst struct sdhci_ops *ops;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n};\n\nstruct dwcmshc_priv;\n\nstruct dwcmshc_pltfm_data {\n\tconst struct sdhci_pltfm_data pdata;\n\tconst struct cqhci_host_ops *cqhci_host_ops;\n\tint (*init)(struct device *, struct sdhci_host *, struct dwcmshc_priv *);\n\tvoid (*postinit)(struct sdhci_host *, struct dwcmshc_priv *);\n};\n\nstruct dwcmshc_priv {\n\tstruct clk *bus_clk;\n\tint vendor_specific_area1;\n\tint vendor_specific_area2;\n\tint num_other_clks;\n\tstruct clk_bulk_data other_clks[3];\n\tvoid *priv;\n\tu16 delay_line;\n\tu16 flags;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct dyn_event_operations;\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(const char *);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct e1000_eeprom_info {\n\te1000_eeprom_type type;\n\tu16 word_size;\n\tu16 opcode_bits;\n\tu16 address_bits;\n\tu16 delay_usec;\n\tu16 page_size;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\nstruct e1000_shadow_ram;\n\nstruct e1000_hw {\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tvoid *ce4100_gbe_mdio_base_virt;\n\te1000_mac_type mac_type;\n\te1000_phy_type phy_type;\n\tu32 phy_init_script;\n\te1000_media_type media_type;\n\tvoid *back;\n\tstruct e1000_shadow_ram *eeprom_shadow_ram;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\te1000_fc_type fc;\n\te1000_bus_speed bus_speed;\n\te1000_bus_width bus_width;\n\te1000_bus_type bus_type;\n\tstruct e1000_eeprom_info eeprom;\n\te1000_ms_type master_slave;\n\te1000_ms_type original_master_slave;\n\te1000_ffe_config ffe_config_state;\n\tu32 asf_firmware_present;\n\tu32 eeprom_semaphore_present;\n\tlong unsigned int io_base;\n\tu32 phy_id;\n\tu32 phy_revision;\n\tu32 phy_addr;\n\tu32 original_fc;\n\tu32 txcw;\n\tu32 autoneg_failed;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tu32 mc_filter_type;\n\tu32 num_mc_addrs;\n\tu32 collision_delta;\n\tu32 tx_packet_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tbool tx_pkt_filtering;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tu16 phy_spd_default;\n\tu16 autoneg_advertised;\n\tu16 pci_cmd_word;\n\tu16 fc_high_water;\n\tu16 fc_low_water;\n\tu16 fc_pause_time;\n\tu16 current_ifs_val;\n\tu16 ifs_min_val;\n\tu16 ifs_max_val;\n\tu16 ifs_step_size;\n\tu16 ifs_ratio;\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n\tu8 autoneg;\n\tu8 mdix;\n\tu8 forced_speed_duplex;\n\tu8 wait_autoneg_complete;\n\tu8 dma_fairness;\n\tu8 mac_addr[6];\n\tu8 perm_mac_addr[6];\n\tbool disable_polarity_correction;\n\tbool speed_downgraded;\n\te1000_smart_speed smart_speed;\n\te1000_dsp_config dsp_config_state;\n\tbool get_link_status;\n\tbool serdes_has_link;\n\tbool tbi_compatibility_en;\n\tbool tbi_compatibility_on;\n\tbool laa_is_present;\n\tbool phy_reset_disable;\n\tbool initialize_hw_bits_disable;\n\tbool fc_send_xon;\n\tbool fc_strict_ieee;\n\tbool report_tx_early;\n\tbool adaptive_ifs;\n\tbool ifs_params_forced;\n\tbool in_ifs_mode;\n\tbool mng_reg_access_disabled;\n\tbool leave_av_bit_off;\n\tbool bad_tx_carr_stats_fd;\n\tbool has_smbus;\n};\n\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 txerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorcl;\n\tu64 gorch;\n\tu64 gotcl;\n\tu64 gotch;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rlerrc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 torl;\n\tu64 torh;\n\tu64 totl;\n\tu64 toth;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_info {\n\te1000_cable_length cable_length;\n\te1000_10bt_ext_dist_enable extended_10bt_distance;\n\te1000_rev_polarity cable_polarity;\n\te1000_downshift downshift;\n\te1000_polarity_reversal polarity_correction;\n\te1000_auto_x_mode mdix_mode;\n\te1000_1000t_rx_status local_rx;\n\te1000_1000t_rx_status remote_rx;\n};\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_tx_buffer;\n\nstruct e1000_tx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_tx_buffer *buffer_info;\n\tu16 tdh;\n\tu16 tdt;\n\tbool last_tx_tso;\n};\n\nstruct e1000_rx_buffer;\n\nstruct e1000_rx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_rx_buffer *buffer_info;\n\tstruct sk_buff *rx_skb_top;\n\tint cpu;\n\tu16 rdh;\n\tu16 rdt;\n};\n\nstruct e1000_adapter {\n\tlong unsigned int active_vlans[64];\n\tu16 mng_vlan_id;\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu32 wol;\n\tu32 smartspeed;\n\tu32 en_mng_pt;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tspinlock_t stats_lock;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tu8 fc_autoneg;\n\tstruct e1000_tx_ring *tx_ring;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tu32 gotcl;\n\tu64 gotcl_old;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu8 tx_timeout_factor;\n\tatomic_t tx_fifo_stall;\n\tbool pcix_82544;\n\tbool detect_tx_hung;\n\tbool dump_buffers;\n\tbool (*clean_rx)(struct e1000_adapter *, struct e1000_rx_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_adapter *, struct e1000_rx_ring *, int);\n\tstruct e1000_rx_ring *rx_ring;\n\tstruct napi_struct napi;\n\tint num_tx_queues;\n\tint num_rx_queues;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tbool rx_csum;\n\tu32 gorcl;\n\tu64 gorcl_old;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw hw;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_phy_info phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tu32 test_icr;\n\tstruct e1000_tx_ring test_tx_ring;\n\tstruct e1000_rx_ring test_rx_ring;\n\tint msg_enable;\n\tbool tso_force;\n\tbool smart_power_down;\n\tbool quad_port_a;\n\tlong unsigned int flags;\n\tu32 eeprom_wol;\n\tint bars;\n\tint need_ioport;\n\tbool discarding;\n\tstruct work_struct reset_task;\n\tstruct delayed_work watchdog_task;\n\tstruct delayed_work fifo_stall_task;\n\tstruct delayed_work phy_info_task;\n};\n\nstruct e1000_hw___2;\n\nstruct e1000_mac_operations {\n\ts32 (*id_led_init)(struct e1000_hw___2 *);\n\ts32 (*blink_led)(struct e1000_hw___2 *);\n\tbool (*check_mng_mode)(struct e1000_hw___2 *);\n\ts32 (*check_for_link)(struct e1000_hw___2 *);\n\ts32 (*cleanup_led)(struct e1000_hw___2 *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw___2 *);\n\tvoid (*clear_vfta)(struct e1000_hw___2 *);\n\ts32 (*get_bus_info)(struct e1000_hw___2 *);\n\tvoid (*set_lan_id)(struct e1000_hw___2 *);\n\ts32 (*get_link_up_info)(struct e1000_hw___2 *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw___2 *);\n\ts32 (*led_off)(struct e1000_hw___2 *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw___2 *);\n\ts32 (*init_hw)(struct e1000_hw___2 *);\n\ts32 (*setup_link)(struct e1000_hw___2 *);\n\ts32 (*setup_physical_interface)(struct e1000_hw___2 *);\n\ts32 (*setup_led)(struct e1000_hw___2 *);\n\tvoid (*write_vfta)(struct e1000_hw___2 *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw___2 *);\n\tint (*rar_set)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw___2 *);\n\tu32 (*rar_get_count)(struct e1000_hw___2 *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type___2 type;\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tenum e1000_serdes_link_state serdes_link_state;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tu16 refresh_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_phy_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*cfg_on_link_up)(struct e1000_hw___2 *);\n\ts32 (*check_polarity)(struct e1000_hw___2 *);\n\ts32 (*check_reset_block)(struct e1000_hw___2 *);\n\ts32 (*commit)(struct e1000_hw___2 *);\n\ts32 (*force_speed_duplex)(struct e1000_hw___2 *);\n\ts32 (*get_cfg_done)(struct e1000_hw___2 *);\n\ts32 (*get_cable_length)(struct e1000_hw___2 *);\n\ts32 (*get_info)(struct e1000_hw___2 *);\n\ts32 (*set_page)(struct e1000_hw___2 *, u16);\n\ts32 (*read_reg)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw___2 *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\ts32 (*reset)(struct e1000_hw___2 *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*write_reg)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw___2 *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw___2 *);\n\tvoid (*power_down)(struct e1000_hw___2 *);\n};\n\nstruct e1000_phy_info___2 {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tu32 retry_count;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n\tbool retry_enabled;\n};\n\nstruct e1000_nvm_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*read)(struct e1000_hw___2 *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\tvoid (*reload)(struct e1000_hw___2 *);\n\ts32 (*update)(struct e1000_hw___2 *);\n\ts32 (*valid_led_default)(struct e1000_hw___2 *, u16 *);\n\ts32 (*validate)(struct e1000_hw___2 *);\n\ts32 (*write)(struct e1000_hw___2 *, u16, u16, u16 *);\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type___2 type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_width width;\n\tu16 func;\n};\n\nstruct e1000_dev_spec_82571 {\n\tbool laa_is_present;\n\tu32 smb_counter;\n};\n\nstruct e1000_dev_spec_80003es2lan {\n\tbool mdic_wa_enable;\n};\n\nstruct e1000_shadow_ram___2 {\n\tu16 value;\n\tbool modified;\n};\n\nstruct e1000_dev_spec_ich8lan {\n\tbool kmrn_lock_loss_workaround_enabled;\n\tstruct e1000_shadow_ram___2 shadow_ram[2048];\n\tbool nvm_k1_enabled;\n\tbool eee_disable;\n\tu16 eee_lp_ability;\n\tenum e1000_ulp_state ulp_state;\n};\n\nstruct e1000_adapter___2;\n\nstruct e1000_hw___2 {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *hw_addr;\n\tvoid *flash_address;\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info___2 phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82571 e82571;\n\t\tstruct e1000_dev_spec_80003es2lan e80003es2lan;\n\t\tstruct e1000_dev_spec_ich8lan ich8lan;\n\t} dev_spec;\n};\n\nstruct e1000_hw_stats___2 {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_regs {\n\tu16 bmcr;\n\tu16 bmsr;\n\tu16 advertise;\n\tu16 lpa;\n\tu16 expansion;\n\tu16 ctrl1000;\n\tu16 stat1000;\n\tu16 estatus;\n};\n\nstruct e1000_buffer;\n\nstruct e1000_ring {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\tvoid *head;\n\tvoid *tail;\n\tstruct e1000_buffer *buffer_info;\n\tchar name[21];\n\tu32 ims_val;\n\tu32 itr_val;\n\tvoid *itr_register;\n\tint set_itr;\n\tstruct sk_buff *rx_skb_top;\n};\n\nstruct ifreq;\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct ptp_pin_desc;\n\nstruct ptp_system_timestamp;\n\nstruct system_device_crosststamp;\n\nstruct ptp_clock_request;\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[32];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint n_per_lp;\n\tint pps;\n\tunsigned int supported_perout_flags;\n\tunsigned int supported_extts_flags;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\ts32 (*getmaxphase)(struct ptp_clock_info *);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*getcycles64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n\tint (*perout_loopback)(struct ptp_clock_info *, unsigned int, int);\n};\n\nstruct e1000_info;\n\nstruct msix_entry;\n\nstruct ptp_clock;\n\nstruct e1000_adapter___2 {\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tstruct timer_list blink_timer;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tconst struct e1000_info *ei;\n\tlong unsigned int active_vlans[64];\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu16 mng_vlan_id;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu16 eeprom_vers;\n\tlong unsigned int state;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct e1000_ring *tx_ring;\n\tu32 tx_fifo_limit;\n\tstruct napi_struct napi;\n\tunsigned int uncorr_errors;\n\tunsigned int corr_errors;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tbool detect_tx_hung;\n\tbool tx_hang_recheck;\n\tu8 tx_timeout_factor;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 gotc;\n\tu64 gotc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu32 tx_dma_failed;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tlong: 64;\n\tlong: 64;\n\tbool (*clean_rx)(struct e1000_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_ring *, int, gfp_t);\n\tstruct e1000_ring *rx_ring;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu64 rx_hdr_split;\n\tu32 gorc;\n\tu64 gorc_old;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_dma_failed;\n\tu32 rx_hwtstamp_cleared;\n\tunsigned int rx_ps_pages;\n\tu16 rx_ps_bsize0;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw___2 hw;\n\tspinlock_t stats64_lock;\n\tstruct e1000_hw_stats___2 stats;\n\tstruct e1000_phy_info___2 phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tstruct e1000_phy_regs phy_regs;\n\tstruct e1000_ring test_tx_ring;\n\tstruct e1000_ring test_rx_ring;\n\tu32 test_icr;\n\tu32 msg_enable;\n\tunsigned int num_vectors;\n\tstruct msix_entry *msix_entries;\n\tint int_mode;\n\tu32 eiac_mask;\n\tu32 eeprom_wol;\n\tu32 wol;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\tbool fc_autoneg;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tstruct work_struct downshift_task;\n\tstruct work_struct update_phy_task;\n\tstruct work_struct print_hang_task;\n\tint phy_hang_count;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tstruct kernel_hwtstamp_config hwtstamp_config;\n\tstruct delayed_work systim_overflow_work;\n\tstruct sk_buff *tx_hwtstamp_skb;\n\tlong unsigned int tx_hwtstamp_start;\n\tstruct work_struct tx_hwtstamp_work;\n\tspinlock_t systim_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct pm_qos_request pm_qos_req;\n\tlong int ptp_delta;\n\tu16 eee_advert;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion e1000_adv_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr;\n\t\t__le64 hdr_addr;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\t__le16 pkt_info;\n\t\t\t\t__le16 hdr_info;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nunion e1000_adv_rx_desc___2 {\n\tstruct {\n\t\t__le64 pkt_addr;\n\t\t__le64 hdr_addr;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__le32 data;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 pkt_info;\n\t\t\t\t\t__le16 hdr_info;\n\t\t\t\t} hs_rss;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nstruct e1000_adv_tx_context_desc {\n\t__le32 vlan_macip_lens;\n\t__le32 seqnum_seed;\n\t__le32 type_tucmd_mlhl;\n\t__le32 mss_l4len_idx;\n};\n\nunion e1000_adv_tx_desc {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le32 cmd_type_len;\n\t\t__le32 olinfo_status;\n\t} read;\n\tstruct {\n\t\t__le64 rsvd;\n\t\t__le32 nxtseq_seed;\n\t\t__le32 status;\n\t} wb;\n};\n\nstruct e1000_ps_page;\n\nstruct e1000_buffer {\n\tdma_addr_t dma;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int time_stamp;\n\t\t\tu16 length;\n\t\t\tu16 next_to_watch;\n\t\t\tunsigned int segs;\n\t\t\tunsigned int bytecount;\n\t\t\tu16 mapped_as_page;\n\t\t};\n\t\tstruct {\n\t\t\tstruct e1000_ps_page *ps_pages;\n\t\t\tstruct page *page;\n\t\t};\n\t};\n};\n\nstruct e1000_bus_info___2 {\n\tenum e1000_bus_type type;\n\tenum e1000_bus_speed speed;\n\tenum e1000_bus_width width;\n\tu32 snoop;\n\tu16 func;\n\tu16 pci_cmd_word;\n};\n\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss;\n\t\t\tu8 ipcso;\n\t\t\t__le16 ipcse;\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss;\n\t\t\tu8 tucso;\n\t\t\t__le16 tucse;\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 hdr_len;\n\t\t\t__le16 mss;\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\nstruct e1000_sfp_flags {\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e10_base_bx10: 1;\n\tu8 e10_base_px: 1;\n};\n\nstruct e1000_dev_spec_82575 {\n\tbool sgmii_active;\n\tbool global_device_reset;\n\tbool eee_disable;\n\tbool clear_semaphore_once;\n\tstruct e1000_sfp_flags eth_flags;\n\tbool module_plugged;\n\tu8 media_port;\n\tbool media_changed;\n\tbool mas_capable;\n};\n\nstruct e1000_dev_spec_vf {\n\tu32 vf_number;\n\tu32 v2p_mailbox;\n};\n\nstruct e1000_fc_info___2 {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_fw_version {\n\tu32 etrack_id;\n\tu16 eep_major;\n\tu16 eep_minor;\n\tu16 eep_build;\n\tu8 invm_major;\n\tu8 invm_minor;\n\tu8 invm_img_type;\n\tbool or_valid;\n\tu16 or_major;\n\tu16 or_build;\n\tu16 or_patch;\n};\n\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\nstruct e1000_hw___3;\n\nstruct e1000_mac_operations___2 {\n\ts32 (*check_for_link)(struct e1000_hw___3 *);\n\ts32 (*reset_hw)(struct e1000_hw___3 *);\n\ts32 (*init_hw)(struct e1000_hw___3 *);\n\tbool (*check_mng_mode)(struct e1000_hw___3 *);\n\ts32 (*setup_physical_interface)(struct e1000_hw___3 *);\n\tvoid (*rar_set)(struct e1000_hw___3 *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw___3 *);\n\ts32 (*get_speed_and_duplex)(struct e1000_hw___3 *, u16 *, u16 *);\n\ts32 (*acquire_swfw_sync)(struct e1000_hw___3 *, u16);\n\tvoid (*release_swfw_sync)(struct e1000_hw___3 *, u16);\n\ts32 (*get_thermal_sensor_data)(struct e1000_hw___3 *);\n\ts32 (*init_thermal_sensor_thresh)(struct e1000_hw___3 *);\n\tvoid (*write_vfta)(struct e1000_hw___3 *, u32, u32);\n};\n\nstruct e1000_thermal_diode_data {\n\tu8 location;\n\tu8 temp;\n\tu8 caution_thresh;\n\tu8 max_op_thresh;\n};\n\nstruct e1000_thermal_sensor_data {\n\tstruct e1000_thermal_diode_data sensor[3];\n};\n\nstruct e1000_mac_info___2 {\n\tstruct e1000_mac_operations___2 ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type___3 type;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 txcw;\n\tu16 mta_reg_count;\n\tu16 uta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool arc_subsystem_valid;\n\tbool asf_firmware_present;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool disable_hw_init_bits;\n\tbool get_link_status;\n\tbool ifs_params_forced;\n\tbool in_ifs_mode;\n\tbool report_tx_early;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tstruct e1000_thermal_sensor_data thermal_sensor_data;\n};\n\nstruct e1000_phy_operations___2 {\n\ts32 (*acquire)(struct e1000_hw___3 *);\n\ts32 (*check_polarity)(struct e1000_hw___3 *);\n\ts32 (*check_reset_block)(struct e1000_hw___3 *);\n\ts32 (*force_speed_duplex)(struct e1000_hw___3 *);\n\ts32 (*get_cfg_done)(struct e1000_hw___3 *);\n\ts32 (*get_cable_length)(struct e1000_hw___3 *);\n\ts32 (*get_phy_info)(struct e1000_hw___3 *);\n\ts32 (*read_reg)(struct e1000_hw___3 *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw___3 *);\n\ts32 (*reset)(struct e1000_hw___3 *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw___3 *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw___3 *, bool);\n\ts32 (*write_reg)(struct e1000_hw___3 *, u32, u16);\n\ts32 (*read_i2c_byte)(struct e1000_hw___3 *, u8, u8, u8 *);\n\ts32 (*write_i2c_byte)(struct e1000_hw___3 *, u8, u8, u8);\n};\n\nstruct e1000_phy_info___3 {\n\tstruct e1000_phy_operations___2 ops;\n\tenum e1000_phy_type___2 type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu16 pair_length[4];\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool reset_disable;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n};\n\nstruct e1000_nvm_operations___2 {\n\ts32 (*acquire)(struct e1000_hw___3 *);\n\ts32 (*read)(struct e1000_hw___3 *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw___3 *);\n\ts32 (*write)(struct e1000_hw___3 *, u16, u16, u16 *);\n\ts32 (*update)(struct e1000_hw___3 *);\n\ts32 (*validate)(struct e1000_hw___3 *);\n\ts32 (*valid_led_default)(struct e1000_hw___3 *, u16 *);\n};\n\nstruct e1000_nvm_info___2 {\n\tstruct e1000_nvm_operations___2 ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_mbx_operations {\n\ts32 (*init_params)(struct e1000_hw___3 *);\n\ts32 (*read)(struct e1000_hw___3 *, u32 *, u16, u16, bool);\n\ts32 (*write)(struct e1000_hw___3 *, u32 *, u16, u16);\n\ts32 (*read_posted)(struct e1000_hw___3 *, u32 *, u16, u16);\n\ts32 (*write_posted)(struct e1000_hw___3 *, u32 *, u16, u16);\n\ts32 (*check_for_msg)(struct e1000_hw___3 *, u16);\n\ts32 (*check_for_ack)(struct e1000_hw___3 *, u16);\n\ts32 (*check_for_rst)(struct e1000_hw___3 *, u16);\n\ts32 (*unlock)(struct e1000_hw___3 *, u16);\n};\n\nstruct e1000_mbx_stats {\n\tu32 msgs_tx;\n\tu32 msgs_rx;\n\tu32 acks;\n\tu32 reqs;\n\tu32 rsts;\n};\n\nstruct e1000_mbx_info {\n\tstruct e1000_mbx_operations ops;\n\tstruct e1000_mbx_stats stats;\n\tu32 timeout;\n\tu32 usec_delay;\n\tu16 size;\n};\n\nstruct e1000_hw___3 {\n\tvoid *back;\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tlong unsigned int io_base;\n\tstruct e1000_mac_info___2 mac;\n\tstruct e1000_fc_info___2 fc;\n\tstruct e1000_phy_info___3 phy;\n\tstruct e1000_nvm_info___2 nvm;\n\tstruct e1000_bus_info___2 bus;\n\tstruct e1000_mbx_info mbx;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82575 _82575;\n\t} dev_spec;\n\tu16 device_id;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_device_id;\n\tu16 vendor_id;\n\tu8 revision_id;\n};\n\nstruct e1000_hw___4;\n\nstruct e1000_mac_operations___3 {\n\ts32 (*init_params)(struct e1000_hw___4 *);\n\ts32 (*check_for_link)(struct e1000_hw___4 *);\n\tvoid (*clear_vfta)(struct e1000_hw___4 *);\n\ts32 (*get_bus_info)(struct e1000_hw___4 *);\n\ts32 (*get_link_up_info)(struct e1000_hw___4 *, u16 *, u16 *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw___4 *, u8 *, u32, u32, u32);\n\ts32 (*set_uc_addr)(struct e1000_hw___4 *, u32, u8 *);\n\ts32 (*reset_hw)(struct e1000_hw___4 *);\n\ts32 (*init_hw)(struct e1000_hw___4 *);\n\ts32 (*setup_link)(struct e1000_hw___4 *);\n\tvoid (*write_vfta)(struct e1000_hw___4 *, u32, u32);\n\tvoid (*mta_set)(struct e1000_hw___4 *, u32);\n\tvoid (*rar_set)(struct e1000_hw___4 *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw___4 *);\n\ts32 (*set_vfta)(struct e1000_hw___4 *, u16, bool);\n};\n\nstruct e1000_mac_info___3 {\n\tstruct e1000_mac_operations___3 ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type type;\n\tu16 mta_reg_count;\n\tu16 rar_entry_count;\n\tbool get_link_status;\n};\n\nstruct e1000_mbx_operations___2 {\n\ts32 (*init_params)(struct e1000_hw___4 *);\n\ts32 (*read)(struct e1000_hw___4 *, u32 *, u16);\n\ts32 (*write)(struct e1000_hw___4 *, u32 *, u16);\n\ts32 (*read_posted)(struct e1000_hw___4 *, u32 *, u16);\n\ts32 (*write_posted)(struct e1000_hw___4 *, u32 *, u16);\n\ts32 (*check_for_msg)(struct e1000_hw___4 *);\n\ts32 (*check_for_ack)(struct e1000_hw___4 *);\n\ts32 (*check_for_rst)(struct e1000_hw___4 *);\n};\n\nstruct e1000_mbx_info___2 {\n\tstruct e1000_mbx_operations___2 ops;\n\tstruct e1000_mbx_stats stats;\n\tu32 timeout;\n\tu32 usec_delay;\n\tu16 size;\n};\n\nstruct e1000_hw___4 {\n\tvoid *back;\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tlong unsigned int io_base;\n\tstruct e1000_mac_info___3 mac;\n\tstruct e1000_mbx_info___2 mbx;\n\tspinlock_t mbx_lock;\n\tunion {\n\t\tstruct e1000_dev_spec_vf vf;\n\t} dev_spec;\n\tu16 device_id;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_device_id;\n\tu16 vendor_id;\n\tu8 revision_id;\n};\n\nstruct e1000_hw_stats___3 {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n\tu64 cbtmpc;\n\tu64 htdpmc;\n\tu64 cbrdpc;\n\tu64 cbrmpc;\n\tu64 rpthc;\n\tu64 hgptc;\n\tu64 htcbdpc;\n\tu64 hgorc;\n\tu64 hgotc;\n\tu64 lenerrs;\n\tu64 scvpc;\n\tu64 hrmpc;\n\tu64 doosync;\n\tu64 o2bgptc;\n\tu64 o2bspc;\n\tu64 b2ospc;\n\tu64 b2ogprc;\n};\n\nstruct e1000_info___2 {\n\ts32 (*get_invariants)(struct e1000_hw___3 *);\n\tstruct e1000_mac_operations___2 *mac_ops;\n\tconst struct e1000_phy_operations___2 *phy_ops;\n\tstruct e1000_nvm_operations___2 *nvm_ops;\n};\n\nstruct e1000_info {\n\tenum e1000_mac_type___2 mac;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\ts32 (*get_variants)(struct e1000_adapter___2 *);\n\tconst struct e1000_mac_operations *mac_ops;\n\tconst struct e1000_phy_operations *phy_ops;\n\tconst struct e1000_nvm_operations *nvm_ops;\n};\n\nstruct e1000_opt_list {\n\tint i;\n\tchar *str;\n};\n\nstruct e1000_option {\n\tenum {\n\t\tenable_option = 0,\n\t\trange_option = 1,\n\t\tlist_option = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tconst struct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_option___2 {\n\tenum {\n\t\tenable_option___2 = 0,\n\t\trange_option___2 = 1,\n\t\tlist_option___2 = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tstruct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_ps_page {\n\tstruct page *page;\n\tu64 dma;\n};\n\nstruct e1000_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nstruct e1000_rx_buffer {\n\tunion {\n\t\tstruct page *page;\n\t\tu8 *data;\n\t} rxbuf;\n\tdma_addr_t dma;\n};\n\nstruct e1000_rx_desc {\n\t__le64 buffer_addr;\n\t__le16 length;\n\t__le16 csum;\n\tu8 status;\n\tu8 errors;\n\t__le16 special;\n};\n\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t__le64 buffer_addr[4];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length0;\n\t\t\t__le16 vlan;\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t__le16 length[3];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb;\n};\n\nstruct e1000_shadow_ram {\n\tu16 eeprom_word;\n\tbool modified;\n};\n\nstruct e1000_stats {\n\tchar stat_string[32];\n\tint type;\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct e1000_tx_buffer {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n\tlong unsigned int time_stamp;\n\tu16 length;\n\tu16 next_to_watch;\n\tbool mapped_as_page;\n\tshort unsigned int segs;\n\tunsigned int bytecount;\n};\n\nstruct e1000_tx_desc {\n\t__le64 buffer_addr;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length;\n\t\t\tu8 cso;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 css;\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\nstruct e1000_vf_stats {\n\tu64 base_gprc;\n\tu64 base_gptc;\n\tu64 base_gorc;\n\tu64 base_gotc;\n\tu64 base_mprc;\n\tu64 base_gotlbc;\n\tu64 base_gptlbc;\n\tu64 base_gorlbc;\n\tu64 base_gprlbc;\n\tu32 last_gprc;\n\tu32 last_gptc;\n\tu32 last_gorc;\n\tu32 last_gotc;\n\tu32 last_mprc;\n\tu32 last_gotlbc;\n\tu32 last_gptlbc;\n\tu32 last_gorlbc;\n\tu32 last_gprlbc;\n\tu64 gprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 mprc;\n\tu64 gotlbc;\n\tu64 gptlbc;\n\tu64 gorlbc;\n\tu64 gprlbc;\n};\n\nstruct usb_device;\n\nstruct each_dev_arg {\n\tvoid *data;\n\tint (*fn)(struct usb_device *, void *);\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\tunion {\n\t\t__u32 padding[5];\n\t\tstruct {\n\t\t\t__u8 addr_recv;\n\t\t\t__u8 addr_dest;\n\t\t\t__u8 padding0[2];\n\t\t\t__u32 padding1[4];\n\t\t};\n\t};\n};\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct ktermios;\n\nstruct uart_state;\n\nstruct uart_ops;\n\nstruct serial_port_device;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int ctrl_id;\n\tunsigned int port_id;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char quirks;\n\tenum uart_iotype iotype;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tupf_t flags;\n\tupstat_t status;\n\tbool hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int frame_time;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tstruct serial_port_device *port_dev;\n\tlong unsigned int sysrq;\n\tu8 sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tunsigned char console_reinit;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct serial_rs485 rs485_supported;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct gpio_desc *rs485_rx_during_tx_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tstruct uart_port port;\n\tchar options[32];\n\tunsigned int baud;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nstruct ebi2_xmem_prop {\n\tconst char *prop;\n\tu32 max;\n\tbool slowreg;\n\tu16 shift;\n};\n\nstruct ec_host_request {\n\tuint8_t struct_version;\n\tuint8_t checksum;\n\tuint16_t command;\n\tuint8_t command_version;\n\tuint8_t reserved;\n\tuint16_t data_len;\n};\n\nstruct ec_host_request_i2c {\n\tuint8_t command_protocol;\n\tstruct ec_host_request ec_request;\n} __attribute__((packed));\n\nstruct ec_host_response {\n\tuint8_t struct_version;\n\tuint8_t checksum;\n\tuint16_t result;\n\tuint16_t data_len;\n\tuint16_t reserved;\n};\n\nstruct ec_host_response_i2c {\n\tuint8_t result;\n\tuint8_t packet_length;\n\tstruct ec_host_response ec_response;\n};\n\nstruct ec_i2c_device {\n\tstruct device *dev;\n\tstruct i2c_adapter adap;\n\tstruct cros_ec_device *ec;\n\tu16 remote_bus;\n\tu8 request_buf[256];\n\tu8 response_buf[256];\n};\n\nstruct ec_motion_sense_activity {\n\tuint8_t sensor_num;\n\tuint8_t activity;\n\tuint8_t enable;\n\tuint8_t reserved;\n\tuint16_t parameters[3];\n};\n\nstruct ec_params_auto_fan_ctrl_v2 {\n\tuint8_t fan_idx;\n\tuint8_t cmd;\n\tuint8_t set_auto;\n};\n\nstruct ec_params_charge_control {\n\tuint32_t mode;\n\tuint8_t cmd;\n\tuint8_t flags;\n\tstruct {\n\t\tint8_t lower;\n\t\tint8_t upper;\n\t} sustain_soc;\n};\n\nstruct ec_params_console_read_v1 {\n\tuint8_t subcmd;\n};\n\nstruct ec_params_get_cmd_versions {\n\tuint8_t cmd;\n};\n\nstruct ec_params_get_cmd_versions_v1 {\n\tuint16_t cmd;\n};\n\nstruct ec_params_hello {\n\tuint32_t in_data;\n};\n\nstruct ec_params_host_sleep_event {\n\tuint8_t sleep_event;\n};\n\nstruct ec_params_host_sleep_event_v1 {\n\tuint8_t sleep_event;\n\tuint8_t reserved;\n\tunion {\n\t\tstruct {\n\t\t\tuint16_t sleep_timeout_ms;\n\t\t} suspend_params;\n\t};\n};\n\nstruct ec_params_i2c_passthru_msg {\n\tuint16_t addr_flags;\n\tuint16_t len;\n};\n\nstruct ec_params_i2c_passthru {\n\tuint8_t port;\n\tuint8_t num_msgs;\n\tstruct ec_params_i2c_passthru_msg msg[0];\n};\n\nstruct rgb_s {\n\tuint8_t r;\n\tuint8_t g;\n\tuint8_t b;\n};\n\nstruct lightbar_params_v0 {\n\tint32_t google_ramp_up;\n\tint32_t google_ramp_down;\n\tint32_t s3s0_ramp_up;\n\tint32_t s0_tick_delay[2];\n\tint32_t s0a_tick_delay[2];\n\tint32_t s0s3_ramp_down;\n\tint32_t s3_sleep_for;\n\tint32_t s3_ramp_up;\n\tint32_t s3_ramp_down;\n\tuint8_t new_s0;\n\tuint8_t osc_min[2];\n\tuint8_t osc_max[2];\n\tuint8_t w_ofs[2];\n\tuint8_t bright_bl_off_fixed[2];\n\tuint8_t bright_bl_on_min[2];\n\tuint8_t bright_bl_on_max[2];\n\tuint8_t battery_threshold[3];\n\tuint8_t s0_idx[8];\n\tuint8_t s3_idx[8];\n\tstruct rgb_s color[8];\n};\n\nstruct lightbar_params_v1 {\n\tint32_t google_ramp_up;\n\tint32_t google_ramp_down;\n\tint32_t s3s0_ramp_up;\n\tint32_t s0_tick_delay[2];\n\tint32_t s0a_tick_delay[2];\n\tint32_t s0s3_ramp_down;\n\tint32_t s3_sleep_for;\n\tint32_t s3_ramp_up;\n\tint32_t s3_ramp_down;\n\tint32_t s5_ramp_up;\n\tint32_t s5_ramp_down;\n\tint32_t tap_tick_delay;\n\tint32_t tap_gate_delay;\n\tint32_t tap_display_time;\n\tuint8_t tap_pct_red;\n\tuint8_t tap_pct_green;\n\tuint8_t tap_seg_min_on;\n\tuint8_t tap_seg_max_on;\n\tuint8_t tap_seg_osc;\n\tuint8_t tap_idx[3];\n\tuint8_t osc_min[2];\n\tuint8_t osc_max[2];\n\tuint8_t w_ofs[2];\n\tuint8_t bright_bl_off_fixed[2];\n\tuint8_t bright_bl_on_min[2];\n\tuint8_t bright_bl_on_max[2];\n\tuint8_t battery_threshold[3];\n\tuint8_t s0_idx[8];\n\tuint8_t s3_idx[8];\n\tuint8_t s5_idx;\n\tstruct rgb_s color[8];\n};\n\nstruct lightbar_params_v2_timing {\n\tint32_t google_ramp_up;\n\tint32_t google_ramp_down;\n\tint32_t s3s0_ramp_up;\n\tint32_t s0_tick_delay[2];\n\tint32_t s0a_tick_delay[2];\n\tint32_t s0s3_ramp_down;\n\tint32_t s3_sleep_for;\n\tint32_t s3_ramp_up;\n\tint32_t s3_ramp_down;\n\tint32_t s5_ramp_up;\n\tint32_t s5_ramp_down;\n\tint32_t tap_tick_delay;\n\tint32_t tap_gate_delay;\n\tint32_t tap_display_time;\n};\n\nstruct lightbar_params_v2_tap {\n\tuint8_t tap_pct_red;\n\tuint8_t tap_pct_green;\n\tuint8_t tap_seg_min_on;\n\tuint8_t tap_seg_max_on;\n\tuint8_t tap_seg_osc;\n\tuint8_t tap_idx[3];\n};\n\nstruct lightbar_params_v2_oscillation {\n\tuint8_t osc_min[2];\n\tuint8_t osc_max[2];\n\tuint8_t w_ofs[2];\n};\n\nstruct lightbar_params_v2_brightness {\n\tuint8_t bright_bl_off_fixed[2];\n\tuint8_t bright_bl_on_min[2];\n\tuint8_t bright_bl_on_max[2];\n};\n\nstruct lightbar_params_v2_thresholds {\n\tuint8_t battery_threshold[3];\n};\n\nstruct lightbar_params_v2_colors {\n\tuint8_t s0_idx[8];\n\tuint8_t s3_idx[8];\n\tuint8_t s5_idx;\n\tstruct rgb_s color[8];\n};\n\nstruct lightbar_program {\n\tuint8_t size;\n\tuint8_t data[192];\n};\n\nstruct lightbar_program_ex {\n\tuint8_t size;\n\tuint16_t offset;\n\tuint8_t data[0];\n} __attribute__((packed));\n\nstruct ec_params_lightbar {\n\tuint8_t cmd;\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t num;\n\t\t} set_brightness;\n\t\tstruct {\n\t\t\tuint8_t num;\n\t\t} seq;\n\t\tstruct {\n\t\t\tuint8_t num;\n\t\t} demo;\n\t\tstruct {\n\t\t\tuint8_t ctrl;\n\t\t\tuint8_t reg;\n\t\t\tuint8_t value;\n\t\t} reg;\n\t\tstruct {\n\t\t\tuint8_t led;\n\t\t\tuint8_t red;\n\t\t\tuint8_t green;\n\t\t\tuint8_t blue;\n\t\t} set_rgb;\n\t\tstruct {\n\t\t\tuint8_t led;\n\t\t} get_rgb;\n\t\tstruct {\n\t\t\tuint8_t enable;\n\t\t} manual_suspend_ctrl;\n\t\tstruct lightbar_params_v0 set_params_v0;\n\t\tstruct lightbar_params_v1 set_params_v1;\n\t\tstruct lightbar_params_v2_timing set_v2par_timing;\n\t\tstruct lightbar_params_v2_tap set_v2par_tap;\n\t\tstruct lightbar_params_v2_oscillation set_v2par_osc;\n\t\tstruct lightbar_params_v2_brightness set_v2par_bright;\n\t\tstruct lightbar_params_v2_thresholds set_v2par_thlds;\n\t\tstruct lightbar_params_v2_colors set_v2par_colors;\n\t\tstruct lightbar_program set_program;\n\t\tstruct lightbar_program_ex set_program_ex;\n\t};\n};\n\nstruct ec_params_mkbp_info {\n\tuint8_t info_type;\n\tuint8_t event_type;\n};\n\nstruct ec_params_motion_sense {\n\tuint8_t cmd;\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t max_sensor_count;\n\t\t} dump;\n\t\tstruct {\n\t\t\tint16_t data;\n\t\t} kb_wake_angle;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t} info;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t} info_3;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t} data;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t} fifo_flush;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t} list_activities;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t\tuint8_t enable;\n\t\t} perform_calib;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t\tuint8_t roundup;\n\t\t\tuint16_t reserved;\n\t\t\tint32_t data;\n\t\t} ec_rate;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t\tuint8_t roundup;\n\t\t\tuint16_t reserved;\n\t\t\tint32_t data;\n\t\t} sensor_odr;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t\tuint8_t roundup;\n\t\t\tuint16_t reserved;\n\t\t\tint32_t data;\n\t\t} sensor_range;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t\tuint16_t flags;\n\t\t\tint16_t temp;\n\t\t\tint16_t offset[3];\n\t\t} __attribute__((packed)) sensor_offset;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t\tuint16_t flags;\n\t\t\tint16_t temp;\n\t\t\tuint16_t scale[3];\n\t\t} __attribute__((packed)) sensor_scale;\n\t\tstruct {\n\t\t\tuint32_t max_data_vector;\n\t\t} fifo_read;\n\t\tstruct ec_motion_sense_activity set_activity;\n\t\tstruct {\n\t\t\tint8_t enable;\n\t\t} fifo_int_enable;\n\t\tstruct {\n\t\t\tuint8_t sensor_id;\n\t\t\tuint8_t spoof_enable;\n\t\t\tuint8_t reserved;\n\t\t\tint16_t components[3];\n\t\t} __attribute__((packed)) spoof;\n\t\tstruct {\n\t\t\tint16_t lid_angle;\n\t\t\tint16_t hys_degree;\n\t\t} tablet_mode_threshold;\n\t\tstruct {\n\t\t\tuint8_t sensor_num;\n\t\t\tuint8_t activity;\n\t\t} get_activity;\n\t};\n} __attribute__((packed));\n\nstruct ec_params_pchg {\n\tuint8_t port;\n};\n\nstruct ec_params_pwm_get_fan_duty {\n\tuint8_t fan_idx;\n};\n\nstruct ec_params_pwm_set_fan_duty_v1 {\n\tuint32_t percent;\n\tuint8_t fan_idx;\n} __attribute__((packed));\n\nstruct ec_params_read_memmap {\n\tuint8_t offset;\n\tuint8_t size;\n};\n\nstruct ec_params_reboot_ec {\n\tuint8_t cmd;\n\tuint8_t flags;\n};\n\nstruct ec_params_regulator_enable {\n\tuint32_t index;\n\tuint8_t enable;\n} __attribute__((packed));\n\nstruct ec_params_regulator_get_info {\n\tuint32_t index;\n};\n\nstruct ec_params_regulator_get_voltage {\n\tuint32_t index;\n};\n\nstruct ec_params_regulator_is_enabled {\n\tuint32_t index;\n};\n\nstruct ec_params_regulator_set_voltage {\n\tuint32_t index;\n\tuint32_t min_mv;\n\tuint32_t max_mv;\n};\n\nstruct ec_params_rwsig_action {\n\tuint32_t action;\n};\n\nstruct ec_params_temp_sensor_get_info {\n\tuint8_t id;\n};\n\nstruct ec_params_thermal_get_threshold_v1 {\n\tuint32_t sensor_num;\n};\n\nstruct ec_params_usb_pd_control {\n\tuint8_t port;\n\tuint8_t role;\n\tuint8_t mux;\n\tuint8_t swap;\n};\n\nstruct ec_params_usb_pd_mux_info {\n\tuint8_t port;\n};\n\nstruct ec_params_usb_pd_power_info {\n\tuint8_t port;\n};\n\nstruct ec_params_vbnvcontext {\n\tuint32_t op;\n\tuint8_t block[16];\n};\n\nstruct ec_response_activity_data {\n\tuint8_t activity;\n\tuint8_t state;\n};\n\nstruct ec_response_auto_fan_control {\n\tuint8_t is_auto;\n};\n\nstruct ec_response_board_version {\n\tuint16_t board_version;\n};\n\nstruct ec_response_flash_info {\n\tuint32_t flash_size;\n\tuint32_t write_block_size;\n\tuint32_t erase_block_size;\n\tuint32_t protect_block_size;\n};\n\nstruct ec_response_get_chip_info {\n\tchar vendor[32];\n\tchar name[32];\n\tchar revision[32];\n};\n\nstruct ec_response_get_cmd_versions {\n\tuint32_t version_mask;\n};\n\nstruct ec_response_get_comms_status {\n\tuint32_t flags;\n};\n\nunion ec_response_get_next_data {\n\tuint8_t key_matrix[13];\n\tuint32_t host_event;\n\tuint64_t host_event64;\n\tstruct {\n\t\tuint8_t reserved[3];\n\t\tstruct ec_response_motion_sense_fifo_info info;\n\t} sensor_fifo;\n\tuint32_t buttons;\n\tuint32_t switches;\n\tuint32_t fp_events;\n\tuint32_t sysrq;\n\tuint32_t cec_events;\n};\n\nstruct ec_response_get_protocol_info {\n\tuint32_t protocol_versions;\n\tuint16_t max_request_packet_size;\n\tuint16_t max_response_packet_size;\n\tuint32_t flags;\n};\n\nstruct ec_response_get_version {\n\tchar version_string_ro[32];\n\tchar version_string_rw[32];\n\tchar reserved[32];\n\tuint32_t current_image;\n};\n\nstruct ec_response_hello {\n\tuint32_t out_data;\n};\n\nstruct ec_response_host_event_mask {\n\tuint32_t mask;\n};\n\nstruct ec_response_host_event_status {\n\tuint32_t status;\n};\n\nstruct ec_response_host_sleep_event_v1 {\n\tunion {\n\t\tstruct {\n\t\t\tuint32_t sleep_transitions;\n\t\t} resume_response;\n\t};\n};\n\nstruct ec_response_i2c_passthru {\n\tuint8_t i2c_status;\n\tuint8_t num_msgs;\n\tuint8_t data[0];\n};\n\nstruct lightbar_params_v3 {\n\tuint8_t reported_led_num;\n};\n\nstruct ec_response_lightbar {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tuint8_t reg;\n\t\t\t\tuint8_t ic0;\n\t\t\t\tuint8_t ic1;\n\t\t\t} vals[23];\n\t\t} dump;\n\t\tstruct {\n\t\t\tuint8_t num;\n\t\t} get_seq;\n\t\tstruct {\n\t\t\tuint8_t num;\n\t\t} get_brightness;\n\t\tstruct {\n\t\t\tuint8_t num;\n\t\t} get_demo;\n\t\tstruct lightbar_params_v0 get_params_v0;\n\t\tstruct lightbar_params_v1 get_params_v1;\n\t\tstruct lightbar_params_v2_timing get_params_v2_timing;\n\t\tstruct lightbar_params_v2_tap get_params_v2_tap;\n\t\tstruct lightbar_params_v2_oscillation get_params_v2_osc;\n\t\tstruct lightbar_params_v2_brightness get_params_v2_bright;\n\t\tstruct lightbar_params_v2_thresholds get_params_v2_thlds;\n\t\tstruct lightbar_params_v2_colors get_params_v2_colors;\n\t\tstruct lightbar_params_v3 get_params_v3;\n\t\tstruct {\n\t\t\tuint32_t num;\n\t\t\tuint32_t flags;\n\t\t} version;\n\t\tstruct {\n\t\t\tuint8_t red;\n\t\t\tuint8_t green;\n\t\t\tuint8_t blue;\n\t\t} get_rgb;\n\t};\n};\n\nstruct ec_response_motion_sensor_data {\n\tuint8_t flags;\n\tuint8_t sensor_num;\n\tunion {\n\t\tint16_t data[3];\n\t\tstruct {\n\t\t\tuint16_t reserved;\n\t\t\tuint32_t timestamp;\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\tstruct ec_response_activity_data activity_data;\n\t\t\tint16_t add_info[2];\n\t\t};\n\t};\n};\n\nstruct ec_response_motion_sense_fifo_data {\n\tuint32_t number_data;\n\tstruct ec_response_motion_sensor_data data[0];\n};\n\nstruct ec_response_motion_sense {\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t module_flags;\n\t\t\tuint8_t sensor_count;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty_sensor;\n\t\t\t\tstruct ec_response_motion_sensor_data sensor[0];\n\t\t\t};\n\t\t} dump;\n\t\tstruct {\n\t\t\tuint8_t type;\n\t\t\tuint8_t location;\n\t\t\tuint8_t chip;\n\t\t} info;\n\t\tstruct {\n\t\t\tuint8_t type;\n\t\t\tuint8_t location;\n\t\t\tuint8_t chip;\n\t\t\tuint32_t min_frequency;\n\t\t\tuint32_t max_frequency;\n\t\t\tuint32_t fifo_max_event_count;\n\t\t} info_3;\n\t\tstruct ec_response_motion_sensor_data data;\n\t\tstruct {\n\t\t\tint32_t ret;\n\t\t} ec_rate;\n\t\tstruct {\n\t\t\tint32_t ret;\n\t\t} sensor_odr;\n\t\tstruct {\n\t\t\tint32_t ret;\n\t\t} sensor_range;\n\t\tstruct {\n\t\t\tint32_t ret;\n\t\t} kb_wake_angle;\n\t\tstruct {\n\t\t\tint32_t ret;\n\t\t} fifo_int_enable;\n\t\tstruct {\n\t\t\tint32_t ret;\n\t\t} spoof;\n\t\tstruct {\n\t\t\tint16_t temp;\n\t\t\tint16_t offset[3];\n\t\t} sensor_offset;\n\t\tstruct {\n\t\t\tint16_t temp;\n\t\t\tint16_t offset[3];\n\t\t} perform_calib;\n\t\tstruct {\n\t\t\tint16_t temp;\n\t\t\tuint16_t scale[3];\n\t\t} sensor_scale;\n\t\tstruct ec_response_motion_sense_fifo_info fifo_info;\n\t\tstruct ec_response_motion_sense_fifo_info fifo_flush;\n\t\tstruct ec_response_motion_sense_fifo_data fifo_read;\n\t\tstruct {\n\t\t\tuint16_t reserved;\n\t\t\tuint32_t enabled;\n\t\t\tuint32_t disabled;\n\t\t} __attribute__((packed)) list_activities;\n\t\tstruct {\n\t\t\tuint16_t value;\n\t\t} lid_angle;\n\t\tstruct {\n\t\t\tuint16_t lid_angle;\n\t\t\tuint16_t hys_degree;\n\t\t} tablet_mode_threshold;\n\t\tstruct {\n\t\t\tuint8_t state;\n\t\t} get_activity;\n\t};\n};\n\nstruct ec_response_pchg {\n\tuint32_t error;\n\tuint8_t state;\n\tuint8_t battery_percentage;\n\tuint8_t unused0;\n\tuint8_t unused1;\n\tuint32_t fw_version;\n\tuint32_t dropped_event_count;\n};\n\nstruct ec_response_pchg_count {\n\tuint8_t port_count;\n};\n\nstruct ec_response_pwm_get_fan_duty {\n\tuint32_t percent;\n};\n\nstruct ec_response_pwm_get_fan_rpm {\n\tuint32_t rpm;\n};\n\nstruct ec_response_regulator_get_info {\n\tchar name[16];\n\tuint16_t num_voltages;\n\tuint16_t voltages_mv[16];\n};\n\nstruct ec_response_regulator_get_voltage {\n\tuint32_t voltage_mv;\n};\n\nstruct ec_response_regulator_is_enabled {\n\tuint8_t enabled;\n};\n\nstruct ec_response_rtc {\n\tuint32_t time;\n};\n\nstruct ec_response_temp_sensor_get_info {\n\tchar sensor_name[32];\n\tuint8_t sensor_type;\n};\n\nstruct ec_response_uptime_info {\n\tuint32_t time_since_ec_boot_ms;\n\tuint32_t ap_resets_since_ec_boot;\n\tuint32_t ec_reset_flags;\n\tstruct ap_reset_log_entry recent_ap_reset[4];\n};\n\nstruct ec_response_usb_pd_control_v1 {\n\tuint8_t enabled;\n\tuint8_t role;\n\tuint8_t polarity;\n\tchar state[32];\n};\n\nstruct ec_response_usb_pd_mux_info {\n\tuint8_t flags;\n};\n\nstruct ec_response_usb_pd_ports {\n\tuint8_t num_ports;\n};\n\nstruct usb_chg_measures {\n\tuint16_t voltage_max;\n\tuint16_t voltage_now;\n\tuint16_t current_max;\n\tuint16_t current_lim;\n};\n\nstruct ec_response_usb_pd_power_info {\n\tuint8_t role;\n\tuint8_t type;\n\tuint8_t dualrole;\n\tuint8_t reserved1;\n\tstruct usb_chg_measures meas;\n\tuint32_t max_power;\n};\n\nstruct ec_thermal_config {\n\tuint32_t temp_host[3];\n\tuint32_t temp_host_release[3];\n\tuint32_t temp_fan_off;\n\tuint32_t temp_fan_max;\n};\n\nstruct td;\n\nstruct ed {\n\t__hc32 hwINFO;\n\t__hc32 hwTailP;\n\t__hc32 hwHeadP;\n\t__hc32 hwNextED;\n\tdma_addr_t dma;\n\tstruct td *dummy;\n\tstruct ed *ed_next;\n\tstruct ed *ed_prev;\n\tstruct list_head td_list;\n\tstruct list_head in_use_list;\n\tu8 state;\n\tu8 type;\n\tu8 branch;\n\tu16 interval;\n\tu16 load;\n\tu16 last_iso;\n\tu16 tick;\n\tunsigned int takeback_wdh_cnt;\n\tstruct td *pending_td;\n\tlong: 64;\n};\n\nstruct edac_scrub_ops;\n\nstruct edac_ecs_ops;\n\nstruct edac_mem_repair_ops;\n\nstruct edac_dev_data {\n\tunion {\n\t\tconst struct edac_scrub_ops *scrub_ops;\n\t\tconst struct edac_ecs_ops *ecs_ops;\n\t\tconst struct edac_mem_repair_ops *mem_repair_ops;\n\t};\n\tu8 instance;\n\tvoid *private;\n};\n\nstruct edac_dev_feat_ctx {\n\tstruct device dev;\n\tvoid *private;\n\tstruct edac_dev_data *scrub;\n\tstruct edac_dev_data ecs;\n\tstruct edac_dev_data *mem_repair;\n};\n\nstruct edac_ecs_ex_info {\n\tu16 num_media_frus;\n};\n\nstruct edac_dev_feature {\n\tenum edac_dev_feat ft_type;\n\tu8 instance;\n\tunion {\n\t\tconst struct edac_scrub_ops *scrub_ops;\n\t\tconst struct edac_ecs_ops *ecs_ops;\n\t\tconst struct edac_mem_repair_ops *mem_repair_ops;\n\t};\n\tvoid *ctx;\n\tstruct edac_ecs_ex_info ecs_info;\n};\n\nstruct edac_dev_sysfs_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct edac_dev_sysfs_block_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n};\n\nstruct edac_device_counter {\n\tu32 ue_count;\n\tu32 ce_count;\n};\n\nstruct edac_device_instance;\n\nstruct edac_device_block {\n\tstruct edac_device_instance *instance;\n\tchar name[32];\n\tstruct edac_device_counter counters;\n\tint nr_attribs;\n\tstruct edac_dev_sysfs_block_attribute *block_attributes;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_ctl_info {\n\tstruct list_head link;\n\tstruct module *owner;\n\tint dev_idx;\n\tint log_ue;\n\tint log_ce;\n\tint panic_on_ue;\n\tunsigned int poll_msec;\n\tlong unsigned int delay;\n\tstruct edac_dev_sysfs_attribute *sysfs_attributes;\n\tconst struct bus_type *edac_subsys;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_device_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tchar name[32];\n\tu32 nr_instances;\n\tstruct edac_device_instance *instances;\n\tstruct edac_device_block *blocks;\n\tstruct edac_device_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_instance {\n\tstruct edac_device_ctl_info *ctl;\n\tchar name[35];\n\tstruct edac_device_counter counters;\n\tu32 nr_blocks;\n\tstruct edac_device_block *blocks;\n\tstruct kobject kobj;\n};\n\nstruct edac_ecs_ops {\n\tint (*get_log_entry_type)(struct device *, void *, int, u32 *);\n\tint (*set_log_entry_type)(struct device *, void *, int, u32);\n\tint (*get_mode)(struct device *, void *, int, u32 *);\n\tint (*set_mode)(struct device *, void *, int, u32);\n\tint (*reset)(struct device *, void *, int, u32);\n\tint (*get_threshold)(struct device *, void *, int, u32 *);\n\tint (*set_threshold)(struct device *, void *, int, u32);\n};\n\nstruct edac_mc_layer {\n\tenum edac_mc_layer_type type;\n\tunsigned int size;\n\tbool is_virt_csrow;\n};\n\nstruct edac_mem_repair_ops {\n\tint (*get_repair_type)(struct device *, void *, const char **);\n\tint (*get_persist_mode)(struct device *, void *, bool *);\n\tint (*set_persist_mode)(struct device *, void *, bool);\n\tint (*get_repair_safe_when_in_use)(struct device *, void *, bool *);\n\tint (*get_hpa)(struct device *, void *, u64 *);\n\tint (*set_hpa)(struct device *, void *, u64);\n\tint (*get_min_hpa)(struct device *, void *, u64 *);\n\tint (*get_max_hpa)(struct device *, void *, u64 *);\n\tint (*get_dpa)(struct device *, void *, u64 *);\n\tint (*set_dpa)(struct device *, void *, u64);\n\tint (*get_min_dpa)(struct device *, void *, u64 *);\n\tint (*get_max_dpa)(struct device *, void *, u64 *);\n\tint (*get_nibble_mask)(struct device *, void *, u32 *);\n\tint (*set_nibble_mask)(struct device *, void *, u32);\n\tint (*get_bank_group)(struct device *, void *, u32 *);\n\tint (*set_bank_group)(struct device *, void *, u32);\n\tint (*get_bank)(struct device *, void *, u32 *);\n\tint (*set_bank)(struct device *, void *, u32);\n\tint (*get_rank)(struct device *, void *, u32 *);\n\tint (*set_rank)(struct device *, void *, u32);\n\tint (*get_row)(struct device *, void *, u32 *);\n\tint (*set_row)(struct device *, void *, u32);\n\tint (*get_column)(struct device *, void *, u32 *);\n\tint (*set_column)(struct device *, void *, u32);\n\tint (*get_channel)(struct device *, void *, u32 *);\n\tint (*set_channel)(struct device *, void *, u32);\n\tint (*get_sub_channel)(struct device *, void *, u32 *);\n\tint (*set_sub_channel)(struct device *, void *, u32);\n\tint (*do_repair)(struct device *, void *, u32);\n};\n\nstruct edac_pci_counter {\n\tatomic_t pe_count;\n\tatomic_t npe_count;\n};\n\nstruct edac_pci_ctl_info {\n\tstruct list_head link;\n\tint pci_idx;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_pci_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tchar name[32];\n\tstruct edac_pci_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_pci_dev_attribute {\n\tstruct attribute attr;\n\tvoid *value;\n\tssize_t (*show)(void *, char *);\n\tssize_t (*store)(void *, const char *, size_t);\n};\n\nstruct edac_pci_gen_data {\n\tint edac_idx;\n};\n\nstruct edac_raw_error_desc {\n\tchar location[256];\n\tchar label[296];\n\tlong int grain;\n\tu16 error_count;\n\tenum hw_event_mc_err_type type;\n\tint top_layer;\n\tint mid_layer;\n\tint low_layer;\n\tlong unsigned int page_frame_number;\n\tlong unsigned int offset_in_page;\n\tlong unsigned int syndrome;\n\tconst char *msg;\n\tconst char *other_detail;\n};\n\nstruct edac_scrub_ops {\n\tint (*read_addr)(struct device *, void *, u64 *);\n\tint (*read_size)(struct device *, void *, u64 *);\n\tint (*write_addr)(struct device *, void *, u64);\n\tint (*write_size)(struct device *, void *, u64);\n\tint (*get_enabled_bg)(struct device *, void *, bool *);\n\tint (*set_enabled_bg)(struct device *, void *, bool);\n\tint (*get_min_cycle)(struct device *, void *, u32 *);\n\tint (*get_max_cycle)(struct device *, void *, u32 *);\n\tint (*get_cycle_duration)(struct device *, void *, u32 *);\n\tint (*set_cycle_duration)(struct device *, void *, u32);\n};\n\nstruct edid_info {\n\tunsigned char dummy[128];\n};\n\nstruct edma_regs {\n\tvoid *cr;\n\tvoid *es;\n\tvoid *erqh;\n\tvoid *erql;\n\tvoid *eeih;\n\tvoid *eeil;\n\tvoid *seei;\n\tvoid *ceei;\n\tvoid *serq;\n\tvoid *cerq;\n\tvoid *cint;\n\tvoid *cerr;\n\tvoid *ssrt;\n\tvoid *cdne;\n\tvoid *inth;\n\tvoid *intl;\n\tvoid *errh;\n\tvoid *errl;\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[2];\n\tlong unsigned int advertised[2];\n\tlong unsigned int lp_advertised[2];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct eeprom_93cx6 {\n\tvoid *data;\n\tvoid (*register_read)(struct eeprom_93cx6 *);\n\tvoid (*register_write)(struct eeprom_93cx6 *);\n\tint width;\n\tunsigned int quirks;\n\tchar drive_data;\n\tchar reg_data_in;\n\tchar reg_data_out;\n\tchar reg_data_clock;\n\tchar reg_chip_select;\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\nstruct efi_memory_map {\n\tphys_addr_t phys_map;\n\tvoid *map;\n\tvoid *map_end;\n\tint nr_map;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nstruct efi {\n\tconst efi_runtime_services_t *runtime;\n\tunsigned int runtime_version;\n\tunsigned int runtime_supported_mask;\n\tlong unsigned int acpi;\n\tlong unsigned int acpi20;\n\tlong unsigned int smbios;\n\tlong unsigned int smbios3;\n\tlong unsigned int esrt;\n\tlong unsigned int tpm_log;\n\tlong unsigned int tpm_final_log;\n\tlong unsigned int ovmf_debug_log;\n\tlong unsigned int mokvar_table;\n\tlong unsigned int coco_secret;\n\tlong unsigned int unaccepted;\n\tefi_get_time_t *get_time;\n\tefi_set_time_t *set_time;\n\tefi_get_wakeup_time_t *get_wakeup_time;\n\tefi_set_wakeup_time_t *set_wakeup_time;\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_info_t *query_variable_info;\n\tefi_query_variable_info_t *query_variable_info_nonblocking;\n\tefi_update_capsule_t *update_capsule;\n\tefi_query_capsule_caps_t *query_capsule_caps;\n\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\tefi_reset_system_t *reset_system;\n\tstruct efi_memory_map memmap;\n\tlong unsigned int flags;\n};\n\nstruct efi_boot_memmap {\n\tlong unsigned int map_size;\n\tlong unsigned int desc_size;\n\tu32 desc_ver;\n\tlong unsigned int map_key;\n\tlong unsigned int buff_size;\n\tefi_memory_desc_t map[0];\n};\n\ntypedef void *efi_event_t;\n\ntypedef void (*efi_event_notify_t)(efi_event_t, void *);\n\nunion efi_boot_services {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tvoid *raise_tpl;\n\t\tvoid *restore_tpl;\n\t\tefi_status_t (*allocate_pages)(int, int, long unsigned int, efi_physical_addr_t *);\n\t\tefi_status_t (*free_pages)(efi_physical_addr_t, long unsigned int);\n\t\tefi_status_t (*get_memory_map)(long unsigned int *, void *, long unsigned int *, long unsigned int *, u32 *);\n\t\tefi_status_t (*allocate_pool)(int, long unsigned int, void **);\n\t\tefi_status_t (*free_pool)(void *);\n\t\tefi_status_t (*create_event)(u32, long unsigned int, efi_event_notify_t, void *, efi_event_t *);\n\t\tefi_status_t (*set_timer)(efi_event_t, EFI_TIMER_DELAY, u64);\n\t\tefi_status_t (*wait_for_event)(long unsigned int, efi_event_t *, long unsigned int *);\n\t\tvoid *signal_event;\n\t\tefi_status_t (*close_event)(efi_event_t);\n\t\tvoid *check_event;\n\t\tvoid *install_protocol_interface;\n\t\tvoid *reinstall_protocol_interface;\n\t\tvoid *uninstall_protocol_interface;\n\t\tefi_status_t (*handle_protocol)(efi_handle_t, efi_guid_t *, void **);\n\t\tvoid *__reserved;\n\t\tvoid *register_protocol_notify;\n\t\tefi_status_t (*locate_handle)(int, efi_guid_t *, void *, long unsigned int *, efi_handle_t *);\n\t\tefi_status_t (*locate_device_path)(efi_guid_t *, efi_device_path_protocol_t **, efi_handle_t *);\n\t\tefi_status_t (*install_configuration_table)(efi_guid_t *, void *);\n\t\tefi_status_t (*load_image)(bool, efi_handle_t, efi_device_path_protocol_t *, void *, long unsigned int, efi_handle_t *);\n\t\tefi_status_t (*start_image)(efi_handle_t, long unsigned int *, efi_char16_t **);\n\t\tefi_status_t (*exit)(efi_handle_t, efi_status_t, long unsigned int, efi_char16_t *);\n\t\tefi_status_t (*unload_image)(efi_handle_t);\n\t\tefi_status_t (*exit_boot_services)(efi_handle_t, long unsigned int);\n\t\tvoid *get_next_monotonic_count;\n\t\tefi_status_t (*stall)(long unsigned int);\n\t\tvoid *set_watchdog_timer;\n\t\tvoid *connect_controller;\n\t\tefi_status_t (*disconnect_controller)(efi_handle_t, efi_handle_t, efi_handle_t);\n\t\tvoid *open_protocol;\n\t\tvoid *close_protocol;\n\t\tvoid *open_protocol_information;\n\t\tvoid *protocols_per_handle;\n\t\tefi_status_t (*locate_handle_buffer)(int, efi_guid_t *, void *, long unsigned int *, efi_handle_t **);\n\t\tefi_status_t (*locate_protocol)(efi_guid_t *, void *, void **);\n\t\tefi_status_t (*install_multiple_protocol_interfaces)(efi_handle_t *, ...);\n\t\tefi_status_t (*uninstall_multiple_protocol_interfaces)(efi_handle_t, ...);\n\t\tvoid *calculate_crc32;\n\t\tvoid (*copy_mem)(void *, const void *, long unsigned int);\n\t\tvoid (*set_mem)(void *, long unsigned int, unsigned char);\n\t\tvoid *create_event_ex;\n\t};\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tu32 raise_tpl;\n\t\tu32 restore_tpl;\n\t\tu32 allocate_pages;\n\t\tu32 free_pages;\n\t\tu32 get_memory_map;\n\t\tu32 allocate_pool;\n\t\tu32 free_pool;\n\t\tu32 create_event;\n\t\tu32 set_timer;\n\t\tu32 wait_for_event;\n\t\tu32 signal_event;\n\t\tu32 close_event;\n\t\tu32 check_event;\n\t\tu32 install_protocol_interface;\n\t\tu32 reinstall_protocol_interface;\n\t\tu32 uninstall_protocol_interface;\n\t\tu32 handle_protocol;\n\t\tu32 __reserved;\n\t\tu32 register_protocol_notify;\n\t\tu32 locate_handle;\n\t\tu32 locate_device_path;\n\t\tu32 install_configuration_table;\n\t\tu32 load_image;\n\t\tu32 start_image;\n\t\tu32 exit;\n\t\tu32 unload_image;\n\t\tu32 exit_boot_services;\n\t\tu32 get_next_monotonic_count;\n\t\tu32 stall;\n\t\tu32 set_watchdog_timer;\n\t\tu32 connect_controller;\n\t\tu32 disconnect_controller;\n\t\tu32 open_protocol;\n\t\tu32 close_protocol;\n\t\tu32 open_protocol_information;\n\t\tu32 protocols_per_handle;\n\t\tu32 locate_handle_buffer;\n\t\tu32 locate_protocol;\n\t\tu32 install_multiple_protocol_interfaces;\n\t\tu32 uninstall_multiple_protocol_interfaces;\n\t\tu32 calculate_crc32;\n\t\tu32 copy_mem;\n\t\tu32 set_mem;\n\t\tu32 create_event_ex;\n\t} mixed_mode;\n};\n\nstruct efi_cc_event {\n\tu32 event_size;\n\tstruct {\n\t\tu32 header_size;\n\t\tu16 header_version;\n\t\tu32 mr_index;\n\t\tu32 event_type;\n\t} __attribute__((packed)) event_header;\n} __attribute__((packed));\n\ntypedef struct efi_cc_event efi_cc_event_t;\n\nunion efi_cc_protocol;\n\ntypedef union efi_cc_protocol efi_cc_protocol_t;\n\nunion efi_cc_protocol {\n\tstruct {\n\t\tefi_status_t (*get_capability)(efi_cc_protocol_t *, efi_cc_boot_service_cap_t *);\n\t\tefi_status_t (*get_event_log)(efi_cc_protocol_t *, efi_cc_event_log_format_t, efi_physical_addr_t *, efi_physical_addr_t *, efi_bool_t *);\n\t\tefi_status_t (*hash_log_extend_event)(efi_cc_protocol_t *, u64, efi_physical_addr_t, u64, const efi_cc_event_t *);\n\t\tefi_status_t (*map_pcr_to_mr_index)(efi_cc_protocol_t *, u32, efi_cc_mr_index_t *);\n\t};\n\tstruct {\n\t\tu32 get_capability;\n\t\tu32 get_event_log;\n\t\tu32 hash_log_extend_event;\n\t\tu32 map_pcr_to_mr_index;\n\t} mixed_mode;\n};\n\nunion efi_device_path_from_text_protocol {\n\tstruct {\n\t\tefi_device_path_protocol_t * (*convert_text_to_device_node)(const efi_char16_t *);\n\t\tefi_device_path_protocol_t * (*convert_text_to_device_path)(const efi_char16_t *);\n\t};\n\tstruct {\n\t\tu32 convert_text_to_device_node;\n\t\tu32 convert_text_to_device_path;\n\t} mixed_mode;\n};\n\ntypedef union efi_device_path_from_text_protocol efi_device_path_from_text_protocol_t;\n\nunion efi_edid_active_protocol {\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu8 *edid;\n\t};\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu32 edid;\n\t} mixed_mode;\n};\n\ntypedef union efi_edid_active_protocol efi_edid_active_protocol_t;\n\nunion efi_edid_discovered_protocol {\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu8 *edid;\n\t};\n\tstruct {\n\t\tu32 size_of_edid;\n\t\tu32 edid;\n\t} mixed_mode;\n};\n\ntypedef union efi_edid_discovered_protocol efi_edid_discovered_protocol_t;\n\nstruct efi_generic_dev_path {\n\tu8 type;\n\tu8 sub_type;\n\tu16 length;\n};\n\nstruct efi_file_path_dev_path {\n\tstruct efi_generic_dev_path header;\n\tefi_char16_t filename[0];\n};\n\nunion efi_file_protocol;\n\ntypedef union efi_file_protocol efi_file_protocol_t;\n\nunion efi_file_protocol {\n\tstruct {\n\t\tu64 revision;\n\t\tefi_status_t (*open)(efi_file_protocol_t *, efi_file_protocol_t **, efi_char16_t *, u64, u64);\n\t\tefi_status_t (*close)(efi_file_protocol_t *);\n\t\tefi_status_t (*delete)(efi_file_protocol_t *);\n\t\tefi_status_t (*read)(efi_file_protocol_t *, long unsigned int *, void *);\n\t\tefi_status_t (*write)(efi_file_protocol_t *, long unsigned int, void *);\n\t\tefi_status_t (*get_position)(efi_file_protocol_t *, u64 *);\n\t\tefi_status_t (*set_position)(efi_file_protocol_t *, u64);\n\t\tefi_status_t (*get_info)(efi_file_protocol_t *, efi_guid_t *, long unsigned int *, void *);\n\t\tefi_status_t (*set_info)(efi_file_protocol_t *, efi_guid_t *, long unsigned int, void *);\n\t\tefi_status_t (*flush)(efi_file_protocol_t *);\n\t};\n\tstruct {\n\t\tu64 revision;\n\t\tu32 open;\n\t\tu32 close;\n\t\tu32 delete;\n\t\tu32 read;\n\t\tu32 write;\n\t\tu32 get_position;\n\t\tu32 set_position;\n\t\tu32 get_info;\n\t\tu32 set_info;\n\t\tu32 flush;\n\t} mixed_mode;\n};\n\nunion efi_graphics_output_protocol;\n\ntypedef union efi_graphics_output_protocol efi_graphics_output_protocol_t;\n\nunion efi_graphics_output_protocol_mode;\n\ntypedef union efi_graphics_output_protocol_mode efi_graphics_output_protocol_mode_t;\n\nunion efi_graphics_output_protocol {\n\tstruct {\n\t\tefi_status_t (*query_mode)(efi_graphics_output_protocol_t *, u32, long unsigned int *, efi_graphics_output_mode_info_t **);\n\t\tefi_status_t (*set_mode)(efi_graphics_output_protocol_t *, u32);\n\t\tvoid *blt;\n\t\tefi_graphics_output_protocol_mode_t *mode;\n\t};\n\tstruct {\n\t\tu32 query_mode;\n\t\tu32 set_mode;\n\t\tu32 blt;\n\t\tu32 mode;\n\t} mixed_mode;\n};\n\nunion efi_graphics_output_protocol_mode {\n\tstruct {\n\t\tu32 max_mode;\n\t\tu32 mode;\n\t\tefi_graphics_output_mode_info_t *info;\n\t\tlong unsigned int size_of_info;\n\t\tefi_physical_addr_t frame_buffer_base;\n\t\tlong unsigned int frame_buffer_size;\n\t};\n\tstruct {\n\t\tu32 max_mode;\n\t\tu32 mode;\n\t\tu32 info;\n\t\tu32 size_of_info;\n\t\tu64 frame_buffer_base;\n\t\tu32 frame_buffer_size;\n\t} mixed_mode;\n};\n\nunion efi_load_file_protocol;\n\ntypedef union efi_load_file_protocol efi_load_file_protocol_t;\n\nunion efi_load_file_protocol {\n\tstruct {\n\t\tefi_status_t (*load_file)(efi_load_file_protocol_t *, efi_device_path_protocol_t *, bool, long unsigned int *, void *);\n\t};\n\tstruct {\n\t\tu32 load_file;\n\t} mixed_mode;\n};\n\ntypedef union efi_load_file_protocol efi_load_file2_protocol_t;\n\nunion efi_memory_attribute_protocol;\n\ntypedef union efi_memory_attribute_protocol efi_memory_attribute_protocol_t;\n\nunion efi_memory_attribute_protocol {\n\tstruct {\n\t\tefi_status_t (*get_memory_attributes)(efi_memory_attribute_protocol_t *, efi_physical_addr_t, u64, u64 *);\n\t\tefi_status_t (*set_memory_attributes)(efi_memory_attribute_protocol_t *, efi_physical_addr_t, u64, u64);\n\t\tefi_status_t (*clear_memory_attributes)(efi_memory_attribute_protocol_t *, efi_physical_addr_t, u64, u64);\n\t};\n\tstruct {\n\t\tu32 get_memory_attributes;\n\t\tu32 set_memory_attributes;\n\t\tu32 clear_memory_attributes;\n\t} mixed_mode;\n};\n\nstruct efi_memory_map_data {\n\tphys_addr_t phys_map;\n\tlong unsigned int size;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nunion efi_pci_io_protocol {\n\tstruct {\n\t\tvoid *poll_mem;\n\t\tvoid *poll_io;\n\t\tefi_pci_io_protocol_access_t mem;\n\t\tefi_pci_io_protocol_access_t io;\n\t\tefi_pci_io_protocol_config_access_t pci;\n\t\tvoid *copy_mem;\n\t\tvoid *map;\n\t\tvoid *unmap;\n\t\tvoid *allocate_buffer;\n\t\tvoid *free_buffer;\n\t\tvoid *flush;\n\t\tefi_status_t (*get_location)(efi_pci_io_protocol_t *, long unsigned int *, long unsigned int *, long unsigned int *, long unsigned int *);\n\t\tvoid *attributes;\n\t\tvoid *get_bar_attributes;\n\t\tvoid *set_bar_attributes;\n\t\tuint64_t romsize;\n\t\tvoid *romimage;\n\t};\n\tstruct {\n\t\tu32 poll_mem;\n\t\tu32 poll_io;\n\t\tefi_pci_io_protocol_access_32_t mem;\n\t\tefi_pci_io_protocol_access_32_t io;\n\t\tefi_pci_io_protocol_access_32_t pci;\n\t\tu32 copy_mem;\n\t\tu32 map;\n\t\tu32 unmap;\n\t\tu32 allocate_buffer;\n\t\tu32 free_buffer;\n\t\tu32 flush;\n\t\tu32 get_location;\n\t\tu32 attributes;\n\t\tu32 get_bar_attributes;\n\t\tu32 set_bar_attributes;\n\t\tu64 romsize;\n\t\tu32 romimage;\n\t} mixed_mode;\n};\n\nunion efi_rng_protocol;\n\ntypedef union efi_rng_protocol efi_rng_protocol_t;\n\nunion efi_rng_protocol {\n\tstruct {\n\t\tefi_status_t (*get_info)(efi_rng_protocol_t *, long unsigned int *, efi_guid_t *);\n\t\tefi_status_t (*get_rng)(efi_rng_protocol_t *, efi_guid_t *, long unsigned int, u8 *);\n\t};\n\tstruct {\n\t\tu32 get_info;\n\t\tu32 get_rng;\n\t} mixed_mode;\n};\n\nunion efi_rts_args {\n\tstruct {\n\t\tefi_time_t *time;\n\t\tefi_time_cap_t *capabilities;\n\t} GET_TIME;\n\tstruct {\n\t\tefi_time_t *time;\n\t} SET_TIME;\n\tstruct {\n\t\tefi_bool_t *enabled;\n\t\tefi_bool_t *pending;\n\t\tefi_time_t *time;\n\t} GET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_bool_t enable;\n\t\tefi_time_t *time;\n\t} SET_WAKEUP_TIME;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 *attr;\n\t\tlong unsigned int *data_size;\n\t\tvoid *data;\n\t} GET_VARIABLE;\n\tstruct {\n\t\tlong unsigned int *name_size;\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t} GET_NEXT_VARIABLE;\n\tstruct {\n\t\tefi_char16_t *name;\n\t\tefi_guid_t *vendor;\n\t\tu32 attr;\n\t\tlong unsigned int data_size;\n\t\tvoid *data;\n\t} SET_VARIABLE;\n\tstruct {\n\t\tu32 attr;\n\t\tu64 *storage_space;\n\t\tu64 *remaining_space;\n\t\tu64 *max_variable_size;\n\t} QUERY_VARIABLE_INFO;\n\tstruct {\n\t\tu32 *high_count;\n\t} GET_NEXT_HIGH_MONO_COUNT;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tlong unsigned int sg_list;\n\t} UPDATE_CAPSULE;\n\tstruct {\n\t\tefi_capsule_header_t **capsules;\n\t\tlong unsigned int count;\n\t\tu64 *max_size;\n\t\tint *reset_type;\n\t} QUERY_CAPSULE_CAPS;\n\tstruct {\n\t\tefi_status_t (*acpi_prm_handler)(u64, void *);\n\t\tu64 param_buffer_addr;\n\t\tvoid *context;\n\t} ACPI_PRM_HANDLER;\n};\n\nstruct efi_runtime_work {\n\tunion efi_rts_args *args;\n\tefi_status_t status;\n\tstruct work_struct work;\n\tenum efi_rts_ids efi_rts_id;\n\tstruct completion efi_rts_comp;\n\tconst void *caller;\n};\n\nunion efi_simple_file_system_protocol;\n\ntypedef union efi_simple_file_system_protocol efi_simple_file_system_protocol_t;\n\nunion efi_simple_file_system_protocol {\n\tstruct {\n\t\tu64 revision;\n\t\tefi_status_t (*open_volume)(efi_simple_file_system_protocol_t *, efi_file_protocol_t **);\n\t};\n\tstruct {\n\t\tu64 revision;\n\t\tu32 open_volume;\n\t} mixed_mode;\n};\n\nunion efi_simple_text_input_protocol {\n\tstruct {\n\t\tvoid *reset;\n\t\tefi_status_t (*read_keystroke)(efi_simple_text_input_protocol_t *, efi_input_key_t *);\n\t\tefi_event_t wait_for_key;\n\t};\n\tstruct {\n\t\tu32 reset;\n\t\tu32 read_keystroke;\n\t\tu32 wait_for_key;\n\t} mixed_mode;\n};\n\nunion efi_simple_text_output_protocol {\n\tstruct {\n\t\tvoid *reset;\n\t\tefi_status_t (*output_string)(efi_simple_text_output_protocol_t *, efi_char16_t *);\n\t\tvoid *test_string;\n\t};\n\tstruct {\n\t\tu32 reset;\n\t\tu32 output_string;\n\t\tu32 test_string;\n\t} mixed_mode;\n};\n\nunion efi_smbios_protocol;\n\ntypedef union efi_smbios_protocol efi_smbios_protocol_t;\n\nstruct efi_smbios_record;\n\nunion efi_smbios_protocol {\n\tstruct {\n\t\tefi_status_t (*add)(efi_smbios_protocol_t *, efi_handle_t, u16 *, struct efi_smbios_record *);\n\t\tefi_status_t (*update_string)(efi_smbios_protocol_t *, u16 *, long unsigned int *, u8 *);\n\t\tefi_status_t (*remove)(efi_smbios_protocol_t *, u16);\n\t\tefi_status_t (*get_next)(efi_smbios_protocol_t *, u16 *, u8 *, struct efi_smbios_record **, efi_handle_t *);\n\t\tu8 major_version;\n\t\tu8 minor_version;\n\t};\n\tstruct {\n\t\tu32 add;\n\t\tu32 update_string;\n\t\tu32 remove;\n\t\tu32 get_next;\n\t\tu8 major_version;\n\t\tu8 minor_version;\n\t} mixed_mode;\n};\n\nstruct efi_smbios_record {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n};\n\nstruct efi_smbios_type4_record {\n\tstruct efi_smbios_record header;\n\tu8 socket;\n\tu8 processor_type;\n\tu8 processor_family;\n\tu8 processor_manufacturer;\n\tu8 processor_id[8];\n\tu8 processor_version;\n\tu8 voltage;\n\tu16 external_clock;\n\tu16 max_speed;\n\tu16 current_speed;\n\tu8 status;\n\tu8 processor_upgrade;\n\tu16 l1_cache_handle;\n\tu16 l2_cache_handle;\n\tu16 l3_cache_handle;\n\tu8 serial_number;\n\tu8 asset_tag;\n\tu8 part_number;\n\tu8 core_count;\n\tu8 enabled_core_count;\n\tu8 thread_count;\n\tu16 processor_characteristics;\n\tu16 processor_family2;\n\tu16 core_count2;\n\tu16 enabled_core_count2;\n\tu16 thread_count2;\n\tu16 thread_enabled;\n};\n\nstruct efi_system_resource_entry_v1 {\n\tefi_guid_t fw_class;\n\tu32 fw_type;\n\tu32 fw_version;\n\tu32 lowest_supported_fw_version;\n\tu32 capsule_flags;\n\tu32 last_attempt_version;\n\tu32 last_attempt_status;\n};\n\nstruct efi_system_resource_table {\n\tu32 fw_resource_count;\n\tu32 fw_resource_count_max;\n\tu64 fw_resource_version;\n\tu8 entries[0];\n};\n\nstruct efi_tcg2_event {\n\tu32 event_size;\n\tstruct {\n\t\tu32 header_size;\n\t\tu16 header_version;\n\t\tu32 pcr_index;\n\t\tu32 event_type;\n\t} __attribute__((packed)) event_header;\n} __attribute__((packed));\n\ntypedef struct efi_tcg2_event efi_tcg2_event_t;\n\nstruct efi_tcg2_final_events_table {\n\tu64 version;\n\tu64 nr_events;\n\tu8 events[0];\n};\n\nunion efi_tcg2_protocol;\n\ntypedef union efi_tcg2_protocol efi_tcg2_protocol_t;\n\nunion efi_tcg2_protocol {\n\tstruct {\n\t\tvoid *get_capability;\n\t\tefi_status_t (*get_event_log)(efi_tcg2_protocol_t *, efi_tcg2_event_log_format, efi_physical_addr_t *, efi_physical_addr_t *, efi_bool_t *);\n\t\tefi_status_t (*hash_log_extend_event)(efi_tcg2_protocol_t *, u64, efi_physical_addr_t, u64, const efi_tcg2_event_t *);\n\t\tvoid *submit_command;\n\t\tvoid *get_active_pcr_banks;\n\t\tvoid *set_active_pcr_banks;\n\t\tvoid *get_result_of_set_active_pcr_banks;\n\t};\n\tstruct {\n\t\tu32 get_capability;\n\t\tu32 get_event_log;\n\t\tu32 hash_log_extend_event;\n\t\tu32 submit_command;\n\t\tu32 get_active_pcr_banks;\n\t\tu32 set_active_pcr_banks;\n\t\tu32 get_result_of_set_active_pcr_banks;\n\t} mixed_mode;\n};\n\nstruct efi_unaccepted_memory {\n\tu32 version;\n\tu32 unit_size;\n\tu64 phys_base;\n\tu64 size;\n\tlong unsigned int bitmap[0];\n};\n\nstruct efi_variable {\n\tefi_char16_t VariableName[512];\n\tefi_guid_t VendorGuid;\n};\n\nstruct efi_vendor_dev_path {\n\tstruct efi_generic_dev_path header;\n\tefi_guid_t vendorguid;\n\tu8 vendordata[0];\n};\n\nstruct efifb_dmi_info {\n\tchar *optname;\n\tlong unsigned int base;\n\tint stride;\n\tint width;\n\tint height;\n\tint flags;\n};\n\nstruct efifb_mode_fixup {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int linelength;\n};\n\nstruct efifb_par {\n\tu32 pseudo_palette[16];\n\tresource_size_t base;\n\tresource_size_t size;\n};\n\nunion efistub_event {\n\tefi_tcg2_event_t tcg2_data;\n\tefi_cc_event_t cc_data;\n};\n\nstruct tdTCG_PCClientTaggedEvent {\n\tu32 tagged_event_id;\n\tu32 tagged_event_data_size;\n\tu8 tagged_event_data[0];\n};\n\ntypedef struct tdTCG_PCClientTaggedEvent TCG_PCClientTaggedEvent;\n\nstruct efistub_measured_event {\n\tunion efistub_event event_data;\n\tTCG_PCClientTaggedEvent tagged_event;\n} __attribute__((packed));\n\nstruct efivar_entry {\n\tstruct efi_variable var;\n\tstruct inode vfs_inode;\n\tlong unsigned int open_count;\n\tbool removed;\n};\n\ntypedef efi_status_t efi_query_variable_store_t(u32, long unsigned int, bool);\n\nstruct efivar_operations {\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_store_t *query_variable_store;\n\tefi_query_variable_info_t *query_variable_info;\n};\n\nstruct efivarfs_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct efivarfs_fs_info {\n\tstruct efivarfs_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct notifier_block nb;\n};\n\nstruct efivars {\n\tstruct kset *kset;\n\tconst struct efivar_operations *ops;\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_ci_priv {\n\tstruct regulator *reg_vbus;\n\tbool enabled;\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct ehci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\nstruct ehci_qh;\n\nstruct ehci_itd;\n\nstruct ehci_sitd;\n\nstruct ehci_fstn;\n\nunion ehci_shadow {\n\tstruct ehci_qh *qh;\n\tstruct ehci_itd *itd;\n\tstruct ehci_sitd *sitd;\n\tstruct ehci_fstn *fstn;\n\t__le32 *hw_next;\n\tvoid *ptr;\n};\n\nstruct ehci_fstn {\n\t__le32 hw_next;\n\t__le32 hw_prev;\n\tdma_addr_t fstn_dma;\n\tunion ehci_shadow fstn_next;\n\tlong: 64;\n};\n\nstruct ehci_regs;\n\nstruct ehci_hcd {\n\tenum ehci_hrtimer_event next_hrtimer_event;\n\tunsigned int enabled_hrtimer_events;\n\tktime_t hr_timeouts[12];\n\tstruct hrtimer hrtimer;\n\tint PSS_poll_count;\n\tint ASS_poll_count;\n\tint died_poll_count;\n\tstruct ehci_caps *caps;\n\tstruct ehci_regs *regs;\n\tstruct ehci_dbg_port *debug;\n\t__u32 hcs_params;\n\tspinlock_t lock;\n\tenum ehci_rh_state rh_state;\n\tbool scanning: 1;\n\tbool need_rescan: 1;\n\tbool intr_unlinking: 1;\n\tbool iaa_in_progress: 1;\n\tbool async_unlinking: 1;\n\tbool shutdown: 1;\n\tstruct ehci_qh *qh_scan_next;\n\tstruct ehci_qh *async;\n\tstruct ehci_qh *dummy;\n\tstruct list_head async_unlink;\n\tstruct list_head async_idle;\n\tunsigned int async_unlink_cycle;\n\tunsigned int async_count;\n\t__le32 old_current;\n\t__le32 old_token;\n\tunsigned int periodic_size;\n\t__le32 *periodic;\n\tdma_addr_t periodic_dma;\n\tstruct list_head intr_qh_list;\n\tunsigned int i_thresh;\n\tunion ehci_shadow *pshadow;\n\tstruct list_head intr_unlink_wait;\n\tstruct list_head intr_unlink;\n\tunsigned int intr_unlink_wait_cycle;\n\tunsigned int intr_unlink_cycle;\n\tunsigned int now_frame;\n\tunsigned int last_iso_frame;\n\tunsigned int intr_count;\n\tunsigned int isoc_count;\n\tunsigned int periodic_count;\n\tunsigned int uframe_periodic_max;\n\tstruct list_head cached_itd_list;\n\tstruct ehci_itd *last_itd_to_free;\n\tstruct list_head cached_sitd_list;\n\tstruct ehci_sitd *last_sitd_to_free;\n\tlong unsigned int reset_done[15];\n\tlong unsigned int bus_suspended;\n\tlong unsigned int companion_ports;\n\tlong unsigned int owned_ports;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int suspended_ports;\n\tlong unsigned int resuming_ports;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *qtd_pool;\n\tstruct dma_pool *itd_pool;\n\tstruct dma_pool *sitd_pool;\n\tunsigned int random_frame;\n\tlong unsigned int next_statechange;\n\tktime_t last_periodic_enable;\n\tu32 command;\n\tunsigned int no_selective_suspend: 1;\n\tunsigned int has_fsl_port_bug: 1;\n\tunsigned int has_fsl_hs_errata: 1;\n\tunsigned int has_fsl_susp_errata: 1;\n\tunsigned int has_ci_pec_bug: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_capbase: 1;\n\tunsigned int has_amcc_usb23: 1;\n\tunsigned int need_io_watchdog: 1;\n\tunsigned int amd_pll_fix: 1;\n\tunsigned int use_dummy_qh: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int frame_index_bug: 1;\n\tunsigned int need_oc_pp_cycle: 1;\n\tunsigned int imx28_write_fix: 1;\n\tunsigned int spurious_oc: 1;\n\tunsigned int is_aspeed: 1;\n\tunsigned int zx_wakeup_clear_needed: 1;\n\t__le32 *ohci_hcctrl_reg;\n\tunsigned int has_hostpc: 1;\n\tunsigned int has_tdi_phy_lpm: 1;\n\tunsigned int has_ppcd: 1;\n\tu8 sbrn;\n\tu8 bandwidth[64];\n\tu8 tt_budget[64];\n\tstruct list_head tt_list;\n\tlong unsigned int priv[0];\n};\n\nstruct ehci_iso_packet {\n\tu64 bufp;\n\t__le32 transaction;\n\tu8 cross;\n\tu32 buf1;\n};\n\nstruct ehci_iso_sched {\n\tstruct list_head td_list;\n\tunsigned int span;\n\tunsigned int first_packet;\n\tstruct ehci_iso_packet packet[0];\n};\n\nstruct usb_host_endpoint;\n\nstruct ehci_per_sched {\n\tstruct usb_device *udev;\n\tstruct usb_host_endpoint *ep;\n\tstruct list_head ps_list;\n\tu16 tt_usecs;\n\tu16 cs_mask;\n\tu16 period;\n\tu16 phase;\n\tu8 bw_phase;\n\tu8 phase_uf;\n\tu8 usecs;\n\tu8 c_usecs;\n\tu8 bw_uperiod;\n\tu8 bw_period;\n};\n\nstruct ehci_qh_hw;\n\nstruct ehci_iso_stream {\n\tstruct ehci_qh_hw *hw;\n\tu8 bEndpointAddress;\n\tu8 highspeed;\n\tstruct list_head td_list;\n\tstruct list_head free_list;\n\tstruct ehci_per_sched ps;\n\tunsigned int next_uframe;\n\t__le32 splits;\n\tu16 uperiod;\n\tu16 maxp;\n\tunsigned int bandwidth;\n\t__le32 buf0;\n\t__le32 buf1;\n\t__le32 buf2;\n\t__le32 address;\n};\n\nstruct ehci_itd {\n\t__le32 hw_next;\n\t__le32 hw_transaction[8];\n\t__le32 hw_bufp[7];\n\t__le32 hw_bufp_hi[7];\n\tdma_addr_t itd_dma;\n\tunion ehci_shadow itd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head itd_list;\n\tunsigned int frame;\n\tunsigned int pg;\n\tunsigned int index[8];\n\tlong: 64;\n};\n\nstruct ehci_platform_priv {\n\tstruct clk *clks[4];\n\tstruct reset_control *rsts;\n\tbool reset_on_resume;\n\tbool quirk_poll;\n\tstruct timer_list poll_timer;\n\tstruct delayed_work poll_work;\n};\n\nstruct ehci_qtd;\n\nstruct ehci_qh {\n\tstruct ehci_qh_hw *hw;\n\tdma_addr_t qh_dma;\n\tunion ehci_shadow qh_next;\n\tstruct list_head qtd_list;\n\tstruct list_head intr_node;\n\tstruct ehci_qtd *dummy;\n\tstruct list_head unlink_node;\n\tstruct ehci_per_sched ps;\n\tunsigned int unlink_cycle;\n\tu8 qh_state;\n\tu8 xacterrs;\n\tu8 unlink_reason;\n\tu8 gap_uf;\n\tunsigned int is_out: 1;\n\tunsigned int clearing_tt: 1;\n\tunsigned int dequeue_during_giveback: 1;\n\tunsigned int should_be_inactive: 1;\n};\n\nstruct ehci_qh_hw {\n\t__le32 hw_next;\n\t__le32 hw_info1;\n\t__le32 hw_info2;\n\t__le32 hw_current;\n\t__le32 hw_qtd_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ehci_qtd {\n\t__le32 hw_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tdma_addr_t qtd_dma;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tunion {\n\t\tu32 port_status[15];\n\t\tstruct {\n\t\t\tu32 reserved3[9];\n\t\t\tu32 usbmode;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved4;\n\t\t\tu32 hostpc[15];\n\t\t};\n\t\tu32 brcm_insnreg[4];\n\t};\n\tu32 reserved5[2];\n\tu32 usbmode_ex;\n};\n\nstruct ehci_sitd {\n\t__le32 hw_next;\n\t__le32 hw_fullspeed_ep;\n\t__le32 hw_uframe;\n\t__le32 hw_results;\n\t__le32 hw_buf[2];\n\t__le32 hw_backpointer;\n\t__le32 hw_buf_hi[2];\n\tdma_addr_t sitd_dma;\n\tunion ehci_shadow sitd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head sitd_list;\n\tunsigned int frame;\n\tunsigned int index;\n};\n\nstruct ehci_tt {\n\tu16 bandwidth[8];\n\tstruct list_head tt_list;\n\tstruct list_head ps_list;\n\tstruct usb_tt *usb_tt;\n\tint tt_port;\n};\n\nstruct eic7700_priv {\n\tstruct reset_control *reset;\n\tunsigned int drive_impedance;\n};\n\nstruct einj_parameter {\n\tu64 type;\n\tu64 reserved1;\n\tu64 reserved2;\n\tu64 param1;\n\tu64 param2;\n};\n\nstruct syndrome_array {\n\tunion {\n\t\tu8 acpi_id[16];\n\t\tu8 device_id[16];\n\t\tu8 pcie_sbdf[16];\n\t\tu8 vendor_id[16];\n\t} comp_id;\n\tunion {\n\t\tu8 proc_synd[16];\n\t\tu8 mem_synd[16];\n\t\tu8 pcie_synd[16];\n\t\tu8 vendor_synd[16];\n\t} comp_synd;\n};\n\nstruct einjv2_extension_struct {\n\tu32 length;\n\tu16 revision;\n\tu16 component_arr_count;\n\tstruct syndrome_array component_arr[0];\n};\n\nstruct elevator_queue;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf32_shdr {\n\tElf32_Word sh_name;\n\tElf32_Word sh_type;\n\tElf32_Word sh_flags;\n\tElf32_Addr sh_addr;\n\tElf32_Off sh_offset;\n\tElf32_Word sh_size;\n\tElf32_Word sh_link;\n\tElf32_Word sh_info;\n\tElf32_Word sh_addralign;\n\tElf32_Word sh_entsize;\n};\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_note {\n\tElf64_Word n_namesz;\n\tElf64_Word n_descsz;\n\tElf64_Word n_type;\n};\n\ntypedef struct elf64_note Elf64_Nhdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct elf64_rela {\n\tElf64_Addr r_offset;\n\tElf64_Xword r_info;\n\tElf64_Sxword r_addend;\n};\n\ntypedef struct elf64_rela Elf64_Rela;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\ntypedef struct elf64_shdr Elf64_Shdr;\n\nstruct elf64_sym {\n\tElf64_Word st_name;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf64_Half st_shndx;\n\tElf64_Addr st_value;\n\tElf64_Xword st_size;\n};\n\ntypedef struct elf64_sym Elf64_Sym;\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tcompat_siginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info___2;\n\nstruct elf_note_info___2 {\n\tstruct elf_thread_core_info___2 *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info___2 {\n\tstruct elf_thread_core_info___2 *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct compat_elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_data_callback {\n\tint (*active_power)(struct device *, long unsigned int *, long unsigned int *);\n\tint (*get_cost)(struct device *, long unsigned int, long unsigned int *);\n};\n\nstruct em_dbg_info {\n\tstruct em_perf_domain *pd;\n\tint ps_id;\n};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct emc_dvfs_latency {\n\tuint32_t freq;\n\tuint32_t latency;\n};\n\nstruct en_clk_desc {\n\tint id;\n\tconst char *name;\n\tu32 base_reg;\n\tu8 base_bits;\n\tu8 base_shift;\n\tunion {\n\t\tconst unsigned int *base_values;\n\t\tunsigned int base_value;\n\t};\n\tsize_t n_base_values;\n\tu16 div_reg;\n\tu8 div_bits;\n\tu8 div_shift;\n\tu16 div_val0;\n\tu8 div_step;\n\tu8 div_offset;\n};\n\nstruct en_clk_gate {\n\tvoid *base;\n\tstruct clk_hw hw;\n};\n\nstruct en_clk_soc_data {\n\tu32 num_clocks;\n\tconst struct clk_ops pcie_ops;\n\tint (*hw_init)(struct platform_device *, struct clk_hw_onecell_data *);\n};\n\nstruct en_rst_data {\n\tconst u16 *bank_ofs;\n\tconst u16 *idx_map;\n\tvoid *base;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct trace_event_file;\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nunion trap_config {\n\tu64 val;\n\tstruct {\n\t\tlong unsigned int cgt: 10;\n\t\tlong unsigned int fgt: 4;\n\t\tlong unsigned int bit: 6;\n\t\tlong unsigned int pol: 1;\n\t\tlong unsigned int fgf: 5;\n\t\tlong unsigned int sri: 10;\n\t\tlong unsigned int unused: 27;\n\t\tlong unsigned int mbz: 1;\n\t};\n};\n\nstruct encoding_to_trap_config {\n\tconst u32 encoding;\n\tconst u32 end;\n\tconst union trap_config tc;\n\tconst unsigned int line;\n};\n\nstruct xdr_buf;\n\nstruct encryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tint pos;\n\tstruct xdr_buf *outbuf;\n\tstruct page **pages;\n\tstruct scatterlist infrags[4];\n\tstruct scatterlist outfrags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct enetc_xdp_data {\n\tstruct xdp_rxq_info rxq;\n\tstruct bpf_prog *prog;\n\tint xdp_tx_in_flight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct enetc_ring_stats {\n\tlong unsigned int packets;\n\tlong unsigned int bytes;\n\tlong unsigned int rx_alloc_errs;\n\tlong unsigned int xdp_drops;\n\tlong unsigned int xdp_tx;\n\tlong unsigned int xdp_tx_drops;\n\tlong unsigned int xdp_redirect;\n\tlong unsigned int xdp_redirect_failures;\n\tlong unsigned int recycles;\n\tlong unsigned int recycle_failures;\n\tlong unsigned int win_drop;\n};\n\nstruct enetc_tx_swbd;\n\nstruct enetc_rx_swbd;\n\nstruct enetc_bdr {\n\tstruct device *dev;\n\tstruct net_device *ndev;\n\tvoid *bd_base;\n\tunion {\n\t\tvoid *tpir;\n\t\tvoid *rcir;\n\t};\n\tu16 index;\n\tu16 prio;\n\tint bd_count;\n\tint next_to_use;\n\tint next_to_clean;\n\tunion {\n\t\tstruct enetc_tx_swbd *tx_swbd;\n\t\tstruct enetc_rx_swbd *rx_swbd;\n\t};\n\tunion {\n\t\tvoid *tcir;\n\t\tint next_to_alloc;\n\t};\n\tvoid *idr;\n\tint buffer_offset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct enetc_xdp_data xdp;\n\tstruct enetc_ring_stats stats;\n\tdma_addr_t bd_dma_base;\n\tu8 tsd_enable;\n\tbool ext_en;\n\tchar *tso_headers;\n\tdma_addr_t tso_headers_dma;\n\tlong: 64;\n};\n\nstruct enetc_bdr_resource {\n\tstruct device *dev;\n\tsize_t bd_count;\n\tsize_t bd_size;\n\tvoid *bd_base;\n\tdma_addr_t bd_dma_base;\n\tunion {\n\t\tstruct enetc_tx_swbd *tx_swbd;\n\t\tstruct enetc_rx_swbd *rx_swbd;\n\t};\n\tchar *tso_headers;\n\tdma_addr_t tso_headers_dma;\n};\n\nstruct sfi_conf {\n\t__le32 stream_handle;\n\tu8 multi;\n\tu8 res[2];\n\tu8 sthm;\n\t__le16 fm_inst_table_index;\n\t__le16 msdu;\n\t__le16 sg_inst_table_index;\n\tu8 res1[2];\n\t__le32 input_ports;\n\tu8 res2[3];\n\tu8 en;\n};\n\nstruct sgi_table {\n\tu8 res[8];\n\tu8 oipv;\n\tu8 res0[2];\n\tu8 ocgtst;\n\tu8 res1[7];\n\tu8 gset;\n\tu8 oacl_len;\n\tu8 res2[2];\n\tu8 en;\n};\n\nstruct fmi_conf {\n\t__le32 cir;\n\t__le32 cbs;\n\t__le32 eir;\n\t__le32 ebs;\n\tu8 conf;\n\tu8 res1;\n\tu8 ir_fpp;\n\tu8 res2[4];\n\tu8 en;\n};\n\nstruct tgs_gcl_conf {\n\tu8 atc;\n\tu8 res[7];\n\tstruct {\n\t\tu8 res1[4];\n\t\t__le16 acl_len;\n\t\tu8 res2[2];\n\t};\n};\n\nstruct streamid_conf {\n\t__le32 stream_handle;\n\t__le32 iports;\n\tu8 id_type;\n\tu8 oui[3];\n\tu8 res[3];\n\tu8 en;\n};\n\nstruct sgcl_conf {\n\tu8 aipv;\n\tu8 res[2];\n\tu8 agtst;\n\tu8 res1[4];\n\tunion {\n\t\tstruct {\n\t\t\tu8 res2[4];\n\t\t\tu8 acl_len;\n\t\t\tu8 res3[3];\n\t\t};\n\t\tu8 cct[8];\n\t};\n};\n\nstruct enetc_cbd {\n\tunion {\n\t\tstruct sfi_conf sfi_conf;\n\t\tstruct sgi_table sgi_table;\n\t\tstruct fmi_conf fmi_conf;\n\t\tstruct {\n\t\t\t__le32 addr[2];\n\t\t\tunion {\n\t\t\t\t__le32 opt[4];\n\t\t\t\tstruct tgs_gcl_conf gcl_conf;\n\t\t\t\tstruct streamid_conf sid_set;\n\t\t\t\tstruct sgcl_conf sgcl_conf;\n\t\t\t};\n\t\t};\n\t\t__le32 data[6];\n\t};\n\t__le16 index;\n\t__le16 length;\n\tu8 cmd;\n\tu8 cls;\n\tu8 _res;\n\tu8 status_flags;\n};\n\nstruct enetc_cbdr {\n\tvoid *bd_base;\n\tvoid *pir;\n\tvoid *cir;\n\tvoid *mr;\n\tint bd_count;\n\tint next_to_use;\n\tint next_to_clean;\n\tdma_addr_t bd_dma_base;\n\tstruct device *dma_dev;\n};\n\nstruct enetc_cls_rule {\n\tstruct ethtool_rx_flow_spec fs;\n\tint used;\n};\n\nstruct enetc_cmd_rfse {\n\tu8 smac_h[6];\n\tu8 smac_m[6];\n\tu8 dmac_h[6];\n\tu8 dmac_m[6];\n\t__be32 sip_h[4];\n\t__be32 sip_m[4];\n\t__be32 dip_h[4];\n\t__be32 dip_m[4];\n\tu16 ethtype_h;\n\tu16 ethtype_m;\n\tu16 ethtype4_h;\n\tu16 ethtype4_m;\n\tu16 sport_h;\n\tu16 sport_m;\n\tu16 dport_h;\n\tu16 dport_m;\n\tu16 vlan_h;\n\tu16 vlan_m;\n\tu8 proto_h;\n\tu8 proto_m;\n\tu16 flags;\n\tu16 result;\n\tu16 mode;\n};\n\nstruct enetc_drvdata {\n\tu32 pmac_offset;\n\tu8 tx_csum: 1;\n\tu8 max_frags;\n\tu64 sysclk_freq;\n\tconst struct ethtool_ops *eth_ops;\n};\n\nstruct enetc_hw {\n\tvoid *reg;\n\tvoid *port;\n\tvoid *global;\n};\n\nstruct enetc_ierb {\n\tvoid *regs;\n};\n\nstruct enetc_int_vector {\n\tvoid *rbier;\n\tvoid *tbier_base;\n\tvoid *ricr1;\n\tlong unsigned int tx_rings_map;\n\tint count_tx_rings;\n\tu32 rx_ictt;\n\tu16 comp_cnt;\n\tbool rx_dim_en;\n\tbool rx_napi_work;\n\tlong: 64;\n\tlong: 64;\n\tstruct napi_struct napi;\n\tlong: 64;\n\tlong: 64;\n\tstruct dim rx_dim;\n\tchar name[24];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct enetc_bdr rx_ring;\n\tstruct enetc_bdr tx_ring[0];\n};\n\nstruct enetc_lso_t {\n\tbool ipv6;\n\tbool tcp;\n\tu8 l3_hdr_len;\n\tu8 hdr_len;\n\tu8 l3_start;\n\tu16 lso_seg_size;\n\tint total_len;\n};\n\nstruct enetc_mac_filter {\n\tunion {\n\t\tchar mac_addr[6];\n\t\tlong unsigned int mac_hash_table[1];\n\t};\n\tint mac_addr_cnt;\n};\n\nstruct enetc_mdio_priv {\n\tstruct enetc_hw *hw;\n\tint mdio_base;\n};\n\nstruct enetc_msg_cmd_header {\n\tu16 type;\n\tu16 id;\n};\n\nstruct enetc_msg_cmd_set_primary_mac {\n\tstruct enetc_msg_cmd_header header;\n\tstruct sockaddr mac;\n};\n\nstruct enetc_msg_swbd {\n\tvoid *vaddr;\n\tdma_addr_t dma;\n\tint size;\n};\n\nstruct psfp_cap {\n\tu32 max_streamid;\n\tu32 max_psfp_filter;\n\tu32 max_psfp_gate;\n\tu32 max_psfp_gatelist;\n\tu32 max_psfp_meter;\n};\n\nstruct enetc_si;\n\nstruct enetc_ndev_priv {\n\tstruct net_device *ndev;\n\tstruct device *dev;\n\tstruct enetc_si *si;\n\tint bdr_int_num;\n\tstruct enetc_int_vector *int_vector[6];\n\tu16 num_rx_rings;\n\tu16 num_tx_rings;\n\tu16 rx_bd_count;\n\tu16 tx_bd_count;\n\tu16 msg_enable;\n\tu8 preemptible_tcs;\n\tu8 max_frags;\n\tenum enetc_active_offloads active_offloads;\n\tu32 speed;\n\tstruct enetc_bdr **xdp_tx_ring;\n\tstruct enetc_bdr *tx_ring[16];\n\tstruct enetc_bdr *rx_ring[16];\n\tconst struct enetc_bdr_resource *tx_res;\n\tconst struct enetc_bdr_resource *rx_res;\n\tstruct enetc_cls_rule *cls_rules;\n\tstruct psfp_cap psfp_cap;\n\tunsigned int min_num_stack_tx_queues;\n\tstruct phylink *phylink;\n\tint ic_mode;\n\tu32 tx_ictt;\n\tstruct bpf_prog *xdp_prog;\n\tlong unsigned int flags;\n\tstruct work_struct tx_onestep_tstamp;\n\tstruct sk_buff_head tx_skbs;\n\tstruct mutex mm_lock;\n\tstruct clk *ref_clk;\n\tu64 sysclk_freq;\n};\n\nstruct enetc_port_caps {\n\tu32 half_duplex: 1;\n\tint num_vsi;\n\tint num_msix;\n\tint num_rx_bdr;\n\tint num_tx_bdr;\n\tint mac_filter_num;\n};\n\nstruct enetc_vf_state;\n\nstruct enetc_pf_ops;\n\nstruct enetc_pf {\n\tstruct enetc_si *si;\n\tint num_vfs;\n\tint total_vfs;\n\tstruct enetc_vf_state *vf_state;\n\tstruct enetc_mac_filter mac_filter[6];\n\tstruct enetc_msg_swbd rxmsg[2];\n\tstruct work_struct msg_task;\n\tchar msg_int_name[24];\n\tchar vlan_promisc_simap;\n\tlong unsigned int vlan_ht_filter[1];\n\tlong unsigned int active_vlans[64];\n\tstruct mii_bus *mdio;\n\tstruct mii_bus *imdio;\n\tstruct phylink_pcs *pcs;\n\tphy_interface_t if_mode;\n\tstruct phylink_config phylink_config;\n\tstruct enetc_port_caps caps;\n\tconst struct enetc_pf_ops *ops;\n\tint num_mfe;\n};\n\nstruct enetc_pf_ops {\n\tvoid (*set_si_primary_mac)(struct enetc_hw *, int, const u8 *);\n\tvoid (*get_si_primary_mac)(struct enetc_hw *, int, u8 *);\n\tstruct phylink_pcs * (*create_pcs)(struct enetc_pf *, struct mii_bus *);\n\tvoid (*destroy_pcs)(struct phylink_pcs *);\n\tint (*enable_psfp)(struct enetc_ndev_priv *);\n};\n\nstruct enetc_platform_info {\n\tu16 revision;\n\tu16 dev_id;\n\tconst struct enetc_drvdata *data;\n};\n\nstruct enetc_psfp {\n\tlong unsigned int dev_bitmap;\n\tlong unsigned int *psfp_sfi_bitmap;\n\tstruct hlist_head stream_list;\n\tstruct hlist_head psfp_filter_list;\n\tstruct hlist_head psfp_gate_list;\n\tstruct hlist_head psfp_meter_list;\n\tspinlock_t psfp_lock;\n};\n\nstruct enetc_psfp_filter {\n\tu32 index;\n\ts32 handle;\n\ts8 prio;\n\tu32 maxsdu;\n\tu32 gate_id;\n\ts32 meter_id;\n\trefcount_t refcount;\n\tstruct hlist_node node;\n};\n\nstruct enetc_psfp_gate {\n\tu32 index;\n\ts8 init_ipv;\n\tu64 basetime;\n\tu64 cycletime;\n\tu64 cycletimext;\n\tu32 num_entries;\n\trefcount_t refcount;\n\tstruct hlist_node node;\n\tstruct action_gate_entry entries[0];\n};\n\nstruct enetc_psfp_meter {\n\tu32 index;\n\tu32 cir;\n\tu32 cbs;\n\trefcount_t refcount;\n\tstruct hlist_node node;\n};\n\nunion enetc_rx_bd {\n\tstruct {\n\t\t__le64 addr;\n\t\tu8 reserved[8];\n\t} w;\n\tstruct {\n\t\t__le16 inet_csum;\n\t\t__le16 parse_summary;\n\t\t__le32 rss_hash;\n\t\t__le16 buf_len;\n\t\t__le16 vlan_opt;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\t__le16 flags;\n\t\t\t\t__le16 error;\n\t\t\t};\n\t\t\t__le32 lstatus;\n\t\t};\n\t} r;\n\tstruct {\n\t\t__le32 tstamp;\n\t\tu8 reserved[12];\n\t} ext;\n};\n\nstruct enetc_rx_swbd {\n\tdma_addr_t dma;\n\tstruct page *page;\n\tu16 page_offset;\n\tenum dma_data_direction dir;\n\tu16 len;\n};\n\nstruct netc_tbl_vers {\n\tu8 maft_ver;\n\tu8 rsst_ver;\n};\n\nstruct netc_cbdr;\n\nstruct ntmp_user {\n\tint cbdr_num;\n\tstruct device *dev;\n\tstruct netc_cbdr *ring;\n\tstruct netc_tbl_vers tbl;\n};\n\nstruct enetc_si_ops;\n\nstruct enetc_si {\n\tstruct pci_dev *pdev;\n\tstruct enetc_hw hw;\n\tenum enetc_errata errata;\n\tstruct net_device *ndev;\n\tunion {\n\t\tstruct enetc_cbdr cbd_ring;\n\t\tstruct ntmp_user ntmp_user;\n\t};\n\tint num_rx_rings;\n\tint num_tx_rings;\n\tint num_fs_entries;\n\tint num_rss;\n\tshort unsigned int pad;\n\tu16 revision;\n\tint hw_features;\n\tconst struct enetc_drvdata *drvdata;\n\tconst struct enetc_si_ops *ops;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rx_mode_task;\n\tstruct dentry *debugfs_root;\n};\n\nstruct enetc_si_ops {\n\tint (*get_rss_table)(struct enetc_si *, u32 *, int);\n\tint (*set_rss_table)(struct enetc_si *, const u32 *, int);\n};\n\nstruct enetc_skb_cb {\n\tu8 flag;\n\tbool udp;\n\tu16 correction_off;\n\tu16 origin_tstamp_off;\n};\n\nstruct enetc_streamid {\n\tu32 index;\n\tunion {\n\t\tu8 src_mac[6];\n\t\tu8 dst_mac[6];\n\t};\n\tu8 filtertype;\n\tu16 vid;\n\tu8 tagged;\n\ts32 handle;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct enetc_stream_filter {\n\tstruct enetc_streamid sid;\n\tu32 sfi_index;\n\tu32 sgi_index;\n\tu32 flags;\n\tu32 fmi_index;\n\tstruct flow_stats stats;\n\tstruct hlist_node node;\n};\n\nunion enetc_tx_bd {\n\tstruct {\n\t\t__le64 addr;\n\t\tunion {\n\t\t\t__le16 buf_len;\n\t\t\t__le16 hdr_len;\n\t\t};\n\t\t__le16 frm_len;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tu8 l3_aux0;\n\t\t\t\tu8 l3_aux1;\n\t\t\t\tu8 l4_aux;\n\t\t\t\tu8 flags;\n\t\t\t};\n\t\t\t__le32 txstart;\n\t\t\t__le32 lstatus;\n\t\t};\n\t};\n\tstruct {\n\t\t__le32 tstamp;\n\t\t__le16 tpid;\n\t\t__le16 vid;\n\t\t__le16 lso_sg_size;\n\t\t__le16 frm_len_ext;\n\t\tu8 reserved[2];\n\t\tu8 e_flags;\n\t\tu8 flags;\n\t} ext;\n\tstruct {\n\t\t__le32 tstamp;\n\t\tu8 reserved[8];\n\t\t__le16 lso_err_count;\n\t\tu8 status;\n\t\tu8 flags;\n\t} wb;\n};\n\nstruct enetc_tx_swbd {\n\tunion {\n\t\tstruct sk_buff *skb;\n\t\tstruct xdp_frame *xdp_frame;\n\t};\n\tdma_addr_t dma;\n\tstruct page *page;\n\tu16 page_offset;\n\tu16 len;\n\tenum dma_data_direction dir;\n\tu8 is_dma_page: 1;\n\tu8 check_wb: 1;\n\tu8 do_twostep_tstamp: 1;\n\tu8 is_eof: 1;\n\tu8 is_xdp_tx: 1;\n\tu8 is_xdp_redirect: 1;\n\tu8 qbv_en: 1;\n};\n\nstruct enetc_vf_state {\n\tenum enetc_vf_flags flags;\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\nstruct entry_header {\n\tu8 id[8];\n\t__le32 priority[2];\n\t__le32 addr;\n\t__le16 len;\n\t__le16 offset;\n};\n\nstruct ep_device {\n\tstruct usb_endpoint_descriptor *desc;\n\tstruct usb_device *udev;\n\tstruct device dev;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n} __attribute__((packed));\n\nstruct epoll_event {\n\t__poll_t events;\n\t__u64 data;\n};\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct trace_eprobe;\n\nstruct eprobe_data {\n\tstruct trace_event_file *file;\n\tstruct trace_eprobe *ep;\n};\n\nstruct eprobe_trace_entry_head {\n\tstruct trace_entry ent;\n};\n\nstruct equation_set_coef {\n\tint a;\n\tint b;\n};\n\nstruct erase_info {\n\tuint64_t addr;\n\tuint64_t len;\n\tuint64_t fail_addr;\n};\n\nstruct erase_info_user {\n\t__u32 start;\n\t__u32 length;\n};\n\nstruct erase_info_user64 {\n\t__u64 start;\n\t__u64 length;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu16 pos;\n\tu64 ts;\n};\n\nstruct errormap {\n\tchar *name;\n\tint val;\n\tint namelen;\n\tstruct hlist_node list;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct erst_erange {\n\tu64 base;\n\tu64 size;\n\tvoid *vaddr;\n\tu32 attr;\n\tu64 timings;\n};\n\nstruct erst_record_id_cache {\n\tstruct mutex lock;\n\tu64 *entries;\n\tint len;\n\tint size;\n\tint refcount;\n};\n\nstruct esdhc_clk_fixup {\n\tconst unsigned int sd_dflt_max_clk;\n\tconst unsigned int max_clk[11];\n};\n\nstruct esdhc_platform_data {\n\tenum wp_types wp_type;\n\tenum cd_types cd_type;\n\tint max_bus_width;\n\tunsigned int delay_line;\n\tunsigned int tuning_step;\n\tunsigned int tuning_start_tap;\n\tunsigned int strobe_dll_delay_target;\n\tunsigned int saved_tuning_delay_cell;\n\tunsigned int saved_auto_tuning_window;\n};\n\nstruct esdhc_soc_data {\n\tu32 flags;\n\tu32 quirks;\n};\n\nstruct esr_context {\n\tstruct _aarch64_ctx head;\n\t__u64 esr;\n};\n\nstruct esre_entry;\n\nstruct esre_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct esre_entry *, char *);\n};\n\nstruct esre_entry {\n\tunion {\n\t\tstruct efi_system_resource_entry_v1 *esre1;\n\t} esre;\n\tstruct kobject kobj;\n\tstruct list_head list;\n};\n\nstruct eth_hash_entry {\n\tu64 addr;\n\tstruct list_head node;\n};\n\nstruct eth_hash_t {\n\tu16 size;\n\tstruct list_head *lsts;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[2];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[2];\n\t\tlong unsigned int advertising[2];\n\t\tlong unsigned int lp_advertising[2];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct ethtool_tunable;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rx_fs_item {\n\tstruct ethtool_rx_flow_spec fs;\n\tstruct list_head list;\n};\n\nstruct ethtool_rx_fs_list {\n\tstruct list_head list;\n\tunsigned int count;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct etts_regs {\n\tu32 tmr_etts1_h;\n\tu32 tmr_etts1_l;\n\tu32 tmr_etts2_h;\n\tu32 tmr_etts2_l;\n};\n\nstruct input_handler;\n\nstruct input_value;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct fasync_struct;\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct event_trigger_data;\n\nstruct ring_buffer_event;\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*parse)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*trigger)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tbool (*count_func)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_data *);\n};\n\nstruct event_counter {\n\tu32 count;\n\tu32 flags;\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nstruct its_vm;\n\nstruct its_vlpi_map;\n\nstruct event_lpi_map {\n\tlong unsigned int *lpi_map;\n\tu16 *col_map;\n\tirq_hw_number_t lpi_base;\n\tint nr_lpis;\n\traw_spinlock_t vlpi_lock;\n\tstruct its_vm *vm;\n\tstruct its_vlpi_map *vlpi_maps;\n\tint nr_vlpis;\n};\n\nstruct event_mod_load {\n\tstruct list_head list;\n\tchar *module;\n\tchar *match;\n\tchar *system;\n\tchar *event;\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tint flags;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n\tstruct llist_node llist;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventfs_attr {\n\tint mode;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\ntypedef int (*eventfs_callback)(const char *, umode_t *, void **, const struct file_operations **);\n\ntypedef void (*eventfs_release)(const char *, void *);\n\nstruct eventfs_entry {\n\tconst char *name;\n\teventfs_callback callback;\n\teventfs_release release;\n};\n\nstruct eventfs_inode {\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head children;\n\tconst struct eventfs_entry *entries;\n\tconst char *name;\n\tstruct eventfs_attr *entry_attrs;\n\tvoid *data;\n\tstruct eventfs_attr attr;\n\tstruct kref kref;\n\tunsigned int is_freed: 1;\n\tunsigned int is_events: 1;\n\tunsigned int nr_entries: 30;\n\tunsigned int ino;\n};\n\nstruct eventfs_root_inode {\n\tstruct eventfs_inode ei;\n\tstruct dentry *events_dir;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n};\n\nstruct kfifo {\n\tunion {\n\t\tstruct __kfifo kfifo;\n\t\tunsigned char *type;\n\t\tconst unsigned char *const_type;\n\t\tchar (*rectype)[0];\n\t\tvoid *ptr;\n\t\tconst void *ptr_const;\n\t};\n\tunsigned char buf[0];\n};\n\nstruct events_queue {\n\tsize_t sz;\n\tstruct kfifo kfifo;\n\tstruct work_struct notify_work;\n\tstruct workqueue_struct *wq;\n};\n\nstruct evtchn_alloc_unbound {\n\tdomid_t dom;\n\tdomid_t remote_dom;\n\tevtchn_port_t port;\n};\n\nstruct evtchn_bind_interdomain {\n\tdomid_t remote_dom;\n\tevtchn_port_t remote_port;\n\tevtchn_port_t local_port;\n};\n\nstruct evtchn_bind_ipi {\n\tuint32_t vcpu;\n\tevtchn_port_t port;\n};\n\nstruct evtchn_bind_pirq {\n\tuint32_t pirq;\n\tuint32_t flags;\n\tevtchn_port_t port;\n};\n\nstruct evtchn_bind_vcpu {\n\tevtchn_port_t port;\n\tuint32_t vcpu;\n};\n\nstruct evtchn_bind_virq {\n\tuint32_t virq;\n\tuint32_t vcpu;\n\tevtchn_port_t port;\n};\n\nstruct evtchn_close {\n\tevtchn_port_t port;\n};\n\nstruct evtchn_expand_array {\n\tuint64_t array_gfn;\n};\n\nstruct evtchn_fifo_control_block {\n\tuint32_t ready;\n\tuint32_t _rsvd;\n\tevent_word_t head[16];\n};\n\nstruct evtchn_fifo_queue {\n\tuint32_t head[16];\n};\n\nstruct evtchn_init_control {\n\tuint64_t control_gfn;\n\tuint32_t offset;\n\tuint32_t vcpu;\n\tuint8_t link_bits;\n\tuint8_t _pad[7];\n};\n\nstruct evtchn_loop_ctrl {\n\tktime_t timeout;\n\tunsigned int count;\n\tbool defer_eoi;\n};\n\nstruct evtchn_ops {\n\tunsigned int (*max_channels)(void);\n\tunsigned int (*nr_channels)(void);\n\tint (*setup)(evtchn_port_t);\n\tvoid (*remove)(evtchn_port_t, unsigned int);\n\tvoid (*bind_to_cpu)(evtchn_port_t, unsigned int, unsigned int);\n\tvoid (*clear_pending)(evtchn_port_t);\n\tvoid (*set_pending)(evtchn_port_t);\n\tbool (*is_pending)(evtchn_port_t);\n\tvoid (*mask)(evtchn_port_t);\n\tvoid (*unmask)(evtchn_port_t);\n\tvoid (*handle_events)(unsigned int, struct evtchn_loop_ctrl *);\n\tvoid (*resume)(void);\n\tint (*percpu_init)(unsigned int);\n\tint (*percpu_deinit)(unsigned int);\n};\n\nstruct evtchn_send {\n\tevtchn_port_t port;\n};\n\nstruct evtchn_set_priority {\n\tevtchn_port_t port;\n\tuint32_t priority;\n};\n\nstruct evtchn_status {\n\tdomid_t dom;\n\tevtchn_port_t port;\n\tuint32_t status;\n\tuint32_t vcpu;\n\tunion {\n\t\tstruct {\n\t\t\tdomid_t dom;\n\t\t} unbound;\n\t\tstruct {\n\t\t\tdomid_t dom;\n\t\t\tevtchn_port_t port;\n\t\t} interdomain;\n\t\tuint32_t pirq;\n\t\tuint32_t virq;\n\t} u;\n};\n\nstruct evtchn_unmask {\n\tevtchn_port_t port;\n};\n\nstruct ewma_pkt_len {\n\tlong unsigned int internal;\n};\n\nstruct ex_phy {\n\tint phy_id;\n\tenum ex_phy_state phy_state;\n\tenum sas_device_type attached_dev_type;\n\tenum sas_linkrate linkrate;\n\tu8 attached_sata_host: 1;\n\tu8 attached_sata_dev: 1;\n\tu8 attached_sata_ps: 1;\n\tenum sas_protocol attached_tproto;\n\tenum sas_protocol attached_iproto;\n\tu8 attached_sas_addr[8];\n\tu8 attached_phy_id;\n\tint phy_change_count;\n\tenum routing_attribute routing_attr;\n\tu8 virtual: 1;\n\tint last_da_index;\n\tstruct sas_phy *phy;\n\tstruct sas_port *port;\n};\n\nstruct exar8250_board;\n\nstruct exar8250 {\n\tunsigned int nr;\n\tunsigned int osc_freq;\n\tstruct exar8250_board *board;\n\tstruct eeprom_93cx6 eeprom;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tconst struct serial_rs485 *rs485_supported;\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n\tvoid (*unregister_gpio)(struct uart_8250_port *);\n};\n\nstruct exception_table_entry {\n\tint insn;\n\tint fixup;\n\tshort int type;\n\tshort int data;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct exit_boot_struct {\n\tstruct efi_boot_memmap *boot_memmap;\n\tefi_memory_desc_t *runtime_map;\n\tint runtime_entry_count;\n\tvoid *new_fdt_addr;\n};\n\nstruct exiu_irq_data {\n\tvoid *base;\n\tu32 spi_base;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_buddy;\n\nstruct ext4_prealloc_space;\n\nstruct ext4_locality_group;\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\text4_grpblk_t ac_orig_goal_len;\n\text4_group_t ac_prefetch_grp;\n\tunsigned int ac_prefetch_ios;\n\tunsigned int ac_prefetch_nr;\n\tint ac_first_err;\n\t__u32 ac_flags;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_cX_found[5];\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct ext4_buddy *ac_e4b;\n\tstruct folio *ac_bitmap_folio;\n\tstruct folio *ac_buddy_folio;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_group_info;\n\nstruct ext4_buddy {\n\tstruct folio *bd_buddy_folio;\n\tvoid *bd_buddy;\n\tstruct folio *bd_bitmap_folio;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_hash {\n\t__le32 hash;\n\t__le32 minor_hash;\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\nstruct ext4_err_translation {\n\tint code;\n\tint errno;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct extent_status;\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_extent;\n\nstruct ext4_extent_idx;\n\nstruct ext4_extent_header;\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_fc_add_range {\n\t__le32 fc_ino;\n\t__u8 fc_ex[12];\n};\n\nstruct ext4_fc_alloc_region {\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tint ino;\n\tint len;\n};\n\nstruct ext4_fc_del_range {\n\t__le32 fc_ino;\n\t__le32 fc_lblk;\n\t__le32 fc_len;\n};\n\nstruct ext4_fc_dentry_info {\n\t__le32 fc_parent_ino;\n\t__le32 fc_ino;\n\t__u8 fc_dname[0];\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n};\n\nstruct ext4_fc_dentry_update {\n\tint fcd_op;\n\tint fcd_parent;\n\tint fcd_ino;\n\tstruct name_snapshot fcd_name;\n\tstruct list_head fcd_list;\n\tstruct list_head fcd_dilist;\n};\n\nstruct ext4_fc_head {\n\t__le32 fc_features;\n\t__le32 fc_tid;\n};\n\nstruct ext4_fc_inode {\n\t__le32 fc_ino;\n\t__u8 fc_raw_inode[0];\n};\n\nstruct ext4_fc_replay_state {\n\tint fc_replay_num_tags;\n\tint fc_replay_expected_off;\n\tint fc_current_pass;\n\tint fc_cur_tag;\n\tint fc_crc;\n\tstruct ext4_fc_alloc_region *fc_regions;\n\tint fc_regions_size;\n\tint fc_regions_used;\n\tint fc_regions_valid;\n\tint *fc_modified_inodes;\n\tint fc_modified_inodes_used;\n\tint fc_modified_inodes_size;\n};\n\nstruct ext4_fc_stats {\n\tunsigned int fc_ineligible_reason_count[13];\n\tlong unsigned int fc_num_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_failed_commits;\n\tlong unsigned int fc_skipped_commits;\n\tlong unsigned int fc_numblks;\n\tu64 s_fc_avg_commit_time;\n};\n\nstruct ext4_fc_tail {\n\t__le32 fc_tid;\n\t__le32 fc_crc;\n};\n\nstruct ext4_fc_tl {\n\t__le16 fc_tag;\n\t__le16 fc_len;\n};\n\nstruct ext4_fc_tl_mem {\n\tu16 fc_tag;\n\tu16 fc_len;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nstruct fscrypt_dummy_policy {};\n\nstruct ext4_fs_context {\n\tchar *s_qf_names[3];\n\tstruct fscrypt_dummy_policy dummy_enc_policy;\n\tint s_jquota_fmt;\n\tshort unsigned int qname_spec;\n\tlong unsigned int vals_s_flags;\n\tlong unsigned int mask_s_flags;\n\tlong unsigned int journal_devnum;\n\tlong unsigned int s_commit_interval;\n\tlong unsigned int s_stripe;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_want_extra_isize;\n\tunsigned int s_li_wait_mult;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int journal_ioprio;\n\tunsigned int vals_s_mount_opt;\n\tunsigned int mask_s_mount_opt;\n\tunsigned int vals_s_mount_opt2;\n\tunsigned int mask_s_mount_opt2;\n\tunsigned int opt_flags;\n\tunsigned int spec;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\text4_fsblk_t s_sb_block;\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\nstruct ext4_getfsmap_info;\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\tint bb_avg_fragment_size_order;\n\text4_grpblk_t bb_largest_free_order;\n\text4_group_t bb_group;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct jbd2_inode;\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tunion {\n\t\tstruct list_head i_orphan;\n\t\tunsigned int i_orphan_idx;\n\t};\n\tstruct list_head i_fc_dilist;\n\tstruct list_head i_fc_list;\n\text4_lblk_t i_fc_lblk_start;\n\text4_lblk_t i_fc_lblk_len;\n\tspinlock_t i_raw_lock;\n\twait_queue_head_t i_fc_wait;\n\tspinlock_t i_fc_lock;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tstruct timespec64 i_crtime;\n\tatomic_t i_prealloc_active;\n\tunsigned int i_reserved_data_blocks;\n\tstruct rb_root i_prealloc_node;\n\trwlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\tu64 i_es_seq;\n\text4_group_t i_last_alloc_group;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tqsize_t i_reserved_quota;\n\tspinlock_t i_block_reservation_lock;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\tstruct dquot *i_dquot[3];\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\trefcount_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n};\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tsector_t io_next_block;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct ext4_journal_trigger {\n\tstruct jbd2_buffer_trigger_type tr_triggers;\n\tstruct super_block *sb;\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tenum ext4_li_mode lr_mode;\n\text4_group_t lr_first_not_zeroed;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n\tu64 m_seq;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n\tint s_jquota_fmt;\n\tchar *s_qf_names[3];\n};\n\nstruct ext4_new_group_data;\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t resize_bg;\n\text4_group_t count;\n};\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct ext4_orphan_block {\n\tatomic_t ob_free_entries;\n\tstruct buffer_head *ob_bh;\n};\n\nstruct ext4_orphan_block_tail {\n\t__le32 ob_magic;\n\t__le32 ob_checksum;\n};\n\nstruct ext4_orphan_info {\n\tint of_blocks;\n\t__u32 of_csum_seed;\n\tstruct ext4_orphan_block *of_binfo;\n};\n\nstruct ext4_prealloc_space {\n\tunion {\n\t\tstruct rb_node inode_node;\n\t\tstruct list_head lg_list;\n\t} pa_node;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tunion {\n\t\trwlock_t *inode_lock;\n\t\tspinlock_t *lg_lock;\n\t} pa_node_lock;\n\tstruct inode *pa_inode;\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct ext4_super_block;\n\nstruct journal_s;\n\nstruct ext4_system_blocks;\n\nstruct flex_groups;\n\nstruct shrinker;\n\nstruct mb_cache;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tlong unsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\tunsigned int s_def_mount_opt2;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct percpu_counter s_sra_exceeded_retry_limit;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct buffer_head *s_mmp_bh;\n\tstruct journal_s *s_journal;\n\tlong unsigned int s_ext4_flags;\n\tstruct mutex s_orphan_lock;\n\tstruct list_head s_orphan;\n\tstruct ext4_orphan_info s_orphan_info;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct file *s_journal_bdev_file;\n\tchar *s_qf_names[3];\n\tint s_jquota_fmt;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *s_system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tatomic_t s_mb_free_pending;\n\tstruct list_head s_freed_data_list[2];\n\tstruct list_head s_discard_list;\n\tstruct work_struct s_discard_work;\n\tatomic_t s_retry_alloc_pending;\n\tstruct xarray *s_mb_avg_fragment_size;\n\tstruct xarray *s_mb_largest_free_orders;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_max_linear_groups;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int s_mb_prefetch;\n\tunsigned int s_mb_prefetch_limit;\n\tunsigned int s_mb_best_avail_max_trim_order;\n\tunsigned int s_sb_update_sec;\n\tunsigned int s_sb_update_kb;\n\text4_group_t *s_mb_last_groups;\n\tunsigned int s_mb_nr_global_goals;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_cX_ex_scanned[5];\n\tatomic_t s_bal_groups_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_stream_goals;\n\tatomic_t s_bal_len_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tatomic64_t s_bal_cX_groups_considered[5];\n\tatomic64_t s_bal_cX_hits[5];\n\tatomic64_t s_bal_cX_failed[5];\n\tatomic_t s_mb_buddies_generated;\n\tatomic64_t s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tlong unsigned int s_err_report_sec;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tlong unsigned int s_last_trim_minblks;\n\tu16 s_min_folio_order;\n\tu16 s_max_folio_order;\n\t__u32 s_csum_seed;\n\tstruct shrinker *s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache *s_ea_block_cache;\n\tstruct mb_cache *s_ea_inode_cache;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_es_lock;\n\tstruct ext4_journal_trigger s_journal_triggers[1];\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tatomic_t s_warning_count;\n\tatomic_t s_msg_count;\n\tstruct fscrypt_dummy_policy s_dummy_enc_policy;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tu64 s_dax_part_off;\n\terrseq_t s_bdev_wb_err;\n\tspinlock_t s_bdev_wb_lock;\n\tspinlock_t s_error_lock;\n\tint s_add_error_count;\n\tint s_first_error_code;\n\t__u32 s_first_error_line;\n\t__u32 s_first_error_ino;\n\t__u64 s_first_error_block;\n\tconst char *s_first_error_func;\n\ttime64_t s_first_error_time;\n\tint s_last_error_code;\n\t__u32 s_last_error_line;\n\t__u32 s_last_error_ino;\n\t__u64 s_last_error_block;\n\tconst char *s_last_error_func;\n\ttime64_t s_last_error_time;\n\tstruct work_struct s_sb_upd_work;\n\tunsigned int s_awu_min;\n\tunsigned int s_awu_max;\n\tatomic_t s_fc_subtid;\n\tstruct list_head s_fc_q[2];\n\tstruct list_head s_fc_dentry_q[2];\n\tunsigned int s_fc_bytes;\n\tstruct mutex s_fc_lock;\n\tstruct buffer_head *s_fc_bh;\n\tstruct ext4_fc_stats s_fc_stats;\n\ttid_t s_fc_ineligible_tid;\n\tstruct ext4_fc_replay_state s_fc_replay_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_orphan_file_inum;\n\t__le16 s_def_resuid_hi;\n\t__le16 s_def_resgid_hi;\n\t__le32 s_reserved[93];\n\t__le32 s_checksum;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n\tu32 ino;\n};\n\nstruct ext4_tune_sb_params {\n\t__u32 set_flags;\n\t__u32 checkinterval;\n\t__u16 errors_behavior;\n\t__u16 mnt_count;\n\t__u16 max_mnt_count;\n\t__u16 raid_stride;\n\t__u64 last_check_time;\n\t__u64 reserved_blocks;\n\t__u64 blocks_count;\n\t__u32 default_mnt_opts;\n\t__u32 reserved_uid;\n\t__u32 reserved_gid;\n\t__u32 raid_stripe_width;\n\t__u16 encoding;\n\t__u16 encoding_flags;\n\t__u8 def_hash_alg;\n\t__u8 pad_1;\n\t__u16 pad_2;\n\t__u32 feature_compat;\n\t__u32 feature_incompat;\n\t__u32 feature_ro_compat;\n\t__u32 set_feature_compat_mask;\n\t__u32 set_feature_incompat_mask;\n\t__u32 set_feature_ro_compat_mask;\n\t__u32 clear_feature_compat_mask;\n\t__u32 clear_feature_incompat_mask;\n\t__u32 clear_feature_ro_compat_mask;\n\t__u8 mount_opts[64];\n\t__u8 pad[68];\n};\n\nstruct ext4_xattr_entry;\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n};\n\nstruct msg_msg;\n\nstruct ext_wait_queue {\n\tstruct task_struct *task;\n\tstruct list_head list;\n\tstruct msg_msg *msg;\n\tint state;\n};\n\nunion extcon_property_value {\n\tint intval;\n};\n\nstruct extcon_cable {\n\tstruct extcon_dev *edev;\n\tint cable_index;\n\tstruct attribute_group attr_g;\n\tstruct device_attribute attr_name;\n\tstruct device_attribute attr_state;\n\tstruct attribute *attrs[3];\n\tunion extcon_property_value usb_propval[3];\n\tunion extcon_property_value chg_propval[1];\n\tunion extcon_property_value jack_propval[1];\n\tunion extcon_property_value disp_propval[2];\n\tlong unsigned int usb_bits[1];\n\tlong unsigned int chg_bits[1];\n\tlong unsigned int jack_bits[1];\n\tlong unsigned int disp_bits[1];\n};\n\nstruct extcon_dev {\n\tconst char *name;\n\tconst unsigned int *supported_cable;\n\tconst u32 *mutually_exclusive;\n\tstruct device dev;\n\tunsigned int id;\n\tstruct raw_notifier_head nh_all;\n\tstruct raw_notifier_head *nh;\n\tstruct list_head entry;\n\tint max_supported;\n\tspinlock_t lock;\n\tu32 state;\n\tstruct device_type extcon_dev_type;\n\tstruct extcon_cable *cables;\n\tstruct attribute_group attr_g_muex;\n\tstruct attribute **attrs_muex;\n\tstruct device_attribute *d_attrs_muex;\n};\n\nstruct extcon_dev_notifier_devres {\n\tstruct extcon_dev *edev;\n\tunsigned int id;\n\tstruct notifier_block *nb;\n};\n\nstruct extcon_specific_cable_nb {\n\tstruct notifier_block *user_nb;\n\tint cable_index;\n\tstruct extcon_dev *edev;\n\tlong unsigned int previous_value;\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\text4_fsblk_t es_pblk;\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct extra_context {\n\tstruct _aarch64_ctx head;\n\t__u64 datap;\n\t__u32 size;\n\t__u32 __reserved[3];\n};\n\nstruct exynos_hsi2c_variant;\n\nstruct exynos5_i2c {\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *msg;\n\tstruct completion msg_complete;\n\tunsigned int msg_ptr;\n\tunsigned int irq;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct device *dev;\n\tint state;\n\tspinlock_t lock;\n\tint trans_done;\n\tunsigned int atomic;\n\tunsigned int op_clock;\n\tconst struct exynos_hsi2c_variant *variant;\n};\n\nstruct exynos_adc_data;\n\nstruct exynos_adc {\n\tstruct exynos_adc_data *data;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct regmap *pmu_map;\n\tstruct clk *clk;\n\tstruct clk *sclk;\n\tunsigned int irq;\n\tstruct regulator *vdd;\n\tstruct completion completion;\n\tu32 value;\n\tunsigned int version;\n\tstruct mutex lock;\n};\n\nstruct exynos_adc_data {\n\tint num_channels;\n\tbool needs_sclk;\n\tbool needs_adc_phy;\n\tint phy_offset;\n\tu32 mask;\n\tvoid (*init_hw)(struct exynos_adc *);\n\tvoid (*exit_hw)(struct exynos_adc *);\n\tvoid (*clear_irq)(struct exynos_adc *);\n\tvoid (*start_conv)(struct exynos_adc *, long unsigned int);\n};\n\nstruct samsung_clk_reg_dump;\n\nstruct samsung_clk_provider;\n\nstruct exynos_arm64_cmu_data {\n\tstruct samsung_clk_reg_dump *clk_save;\n\tunsigned int nr_clk_save;\n\tconst struct samsung_clk_reg_dump *clk_suspend;\n\tunsigned int nr_clk_suspend;\n\tstruct samsung_clk_reg_dump *clk_sysreg_save;\n\tunsigned int nr_clk_sysreg;\n\tstruct clk *clk;\n\tstruct clk **pclks;\n\tint nr_pclks;\n\tstruct samsung_clk_provider *ctx;\n};\n\nstruct exynos_asv_table {\n\tunsigned int num_rows;\n\tunsigned int num_cols;\n\tu32 *buf;\n};\n\nstruct exynos_asv;\n\nstruct exynos_asv_subsys {\n\tstruct exynos_asv *asv;\n\tconst char *cpu_dt_compat;\n\tint id;\n\tstruct exynos_asv_table table;\n\tunsigned int base_volt;\n\tunsigned int offset_volt_h;\n\tunsigned int offset_volt_l;\n};\n\nstruct exynos_asv {\n\tstruct device *dev;\n\tstruct regmap *chipid_regmap;\n\tstruct exynos_asv_subsys subsys[2];\n\tint (*opp_get_voltage)(const struct exynos_asv_subsys *, int, unsigned int);\n\tunsigned int group;\n\tunsigned int table;\n\tbool use_sg;\n\tint of_bin;\n};\n\nstruct exynos_audss_clk_drvdata {\n\tunsigned int has_adma_clk: 1;\n\tunsigned int has_mst_clk: 1;\n\tunsigned int enable_epll: 1;\n\tunsigned int num_clks;\n};\n\nstruct exynos_chipid_info {\n\tu32 product_id;\n\tu32 revision;\n};\n\nstruct exynos_chipid_variant {\n\tunsigned int main_rev_reg;\n\tunsigned int sub_rev_reg;\n\tunsigned int main_rev_shift;\n\tunsigned int sub_rev_shift;\n\tbool efuse;\n};\n\nstruct exynos_clkout {\n\tstruct clk_gate gate;\n\tstruct clk_mux mux;\n\tspinlock_t slock;\n\tvoid *reg;\n\tstruct device_node *np;\n\tu32 pmu_debug_save;\n\tstruct clk_hw_onecell_data data;\n};\n\nstruct exynos_clkout_variant {\n\tu32 mux_mask;\n};\n\nstruct exynos_cpuclk_cfg_data;\n\nstruct exynos_cpuclk_chip;\n\nstruct exynos_cpuclk {\n\tstruct clk_hw hw;\n\tconst struct clk_hw *alt_parent;\n\tvoid *base;\n\tspinlock_t *lock;\n\tconst struct exynos_cpuclk_cfg_data *cfg;\n\tconst long unsigned int num_cfgs;\n\tstruct notifier_block clk_nb;\n\tlong unsigned int flags;\n\tconst struct exynos_cpuclk_chip *chip;\n};\n\nstruct exynos_cpuclk_cfg_data {\n\tlong unsigned int prate;\n\tlong unsigned int div0;\n\tlong unsigned int div1;\n};\n\ntypedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *, struct exynos_cpuclk *);\n\nstruct exynos_cpuclk_regs;\n\nstruct exynos_cpuclk_chip {\n\tconst struct exynos_cpuclk_regs *regs;\n\texynos_rate_change_fn_t pre_rate_cb;\n\texynos_rate_change_fn_t post_rate_cb;\n};\n\nstruct exynos_cpuclk_regs {\n\tu32 mux_sel;\n\tu32 mux_stat;\n\tu32 div_cpu0;\n\tu32 div_cpu1;\n\tu32 div_stat_cpu0;\n\tu32 div_stat_cpu1;\n\tu32 mux;\n\tu32 divs[4];\n};\n\nstruct exynos_dp_video_phy_drvdata;\n\nstruct exynos_dp_video_phy {\n\tstruct regmap *regs;\n\tconst struct exynos_dp_video_phy_drvdata *drvdata;\n};\n\nstruct exynos_dp_video_phy_drvdata {\n\tu32 phy_ctrl_offset;\n};\n\nstruct exynos_ehci_hcd {\n\tstruct clk *clk;\n\tstruct device_node *of_node;\n\tstruct phy *phy[3];\n\tbool legacy_phy;\n};\n\nstruct exynos_eint_gpio_save {\n\tu32 eint_con;\n\tu32 eint_fltcon0;\n\tu32 eint_fltcon1;\n\tu32 eint_mask;\n};\n\nstruct exynos_hsi2c_variant {\n\tunsigned int fifo_depth;\n\tenum i2c_type_exynos hw;\n};\n\nstruct samsung_pinctrl_drv_data;\n\nstruct exynos_irq_chip {\n\tstruct irq_chip chip;\n\tu32 eint_con;\n\tu32 eint_mask;\n\tu32 eint_pend;\n\tu32 eint_num_wakeup_reg;\n\tu32 eint_wake_mask_reg;\n\tvoid (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *, struct exynos_irq_chip *);\n};\n\nstruct exynos_mipi_phy_desc {\n\tenum exynos_mipi_phy_id coupled_phy_id;\n\tu32 enable_val;\n\tunsigned int enable_reg;\n\tenum exynos_mipi_phy_regmap_id enable_map;\n\tu32 resetn_val;\n\tunsigned int resetn_reg;\n\tenum exynos_mipi_phy_regmap_id resetn_map;\n};\n\nstruct video_phy_desc {\n\tstruct phy *phy;\n\tunsigned int index;\n\tconst struct exynos_mipi_phy_desc *data;\n};\n\nstruct exynos_mipi_video_phy {\n\tstruct regmap *regmaps[4];\n\tint num_phys;\n\tstruct video_phy_desc phys[5];\n\tspinlock_t slock;\n};\n\nstruct samsung_pin_bank;\n\nstruct exynos_muxed_weint_data {\n\tunsigned int nr_banks;\n\tstruct samsung_pin_bank *banks[0];\n};\n\nstruct exynos_ohci_hcd {\n\tstruct clk *clk;\n\tstruct device_node *of_node;\n\tstruct phy *phy[3];\n\tbool legacy_phy;\n};\n\nstruct exynos_pm_domain {\n\tvoid *base;\n\tstruct generic_pm_domain pd;\n\tu32 local_pwr_cfg;\n};\n\nstruct exynos_pm_domain_config {\n\tu32 local_pwr_cfg;\n};\n\nstruct exynos_pmu_conf {\n\tunsigned int offset;\n\tu8 val[3];\n};\n\nstruct exynos_pmu_data;\n\nstruct exynos_pmu_context {\n\tstruct device *dev;\n\tconst struct exynos_pmu_data *pmu_data;\n\tstruct regmap *pmureg;\n\tstruct regmap *pmuintrgen;\n\traw_spinlock_t cpupm_lock;\n\tlong unsigned int *in_cpuhp;\n\tbool sys_insuspend;\n\tbool sys_inreboot;\n};\n\nstruct regmap_access_table;\n\nstruct exynos_pmu_data {\n\tconst struct exynos_pmu_conf *pmu_config;\n\tconst struct exynos_pmu_conf *pmu_config_extra;\n\tbool pmu_secure;\n\tbool pmu_cpuhp;\n\tvoid (*pmu_init)(void);\n\tvoid (*powerdown_conf)(enum sys_powerdown);\n\tvoid (*powerdown_conf_extra)(enum sys_powerdown);\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *wr_table;\n};\n\nstruct exynos_soc_id {\n\tconst char *name;\n\tunsigned int id;\n};\n\nstruct exynos_tmu_data {\n\tvoid *base;\n\tvoid *base_second;\n\tint irq;\n\tenum soc_type soc;\n\tstruct mutex lock;\n\tstruct clk *clk;\n\tstruct clk *clk_sec;\n\tstruct clk *sclk;\n\tu32 cal_type;\n\tu32 efuse_value;\n\tu32 min_efuse_value;\n\tu32 max_efuse_value;\n\tu16 temp_error1;\n\tu16 temp_error2;\n\tu8 gain;\n\tu8 reference_voltage;\n\tstruct thermal_zone_device *tzd;\n\tbool enabled;\n\tvoid (*tmu_set_low_temp)(struct exynos_tmu_data *, u8);\n\tvoid (*tmu_set_high_temp)(struct exynos_tmu_data *, u8);\n\tvoid (*tmu_set_crit_temp)(struct exynos_tmu_data *, u8);\n\tvoid (*tmu_disable_low)(struct exynos_tmu_data *);\n\tvoid (*tmu_disable_high)(struct exynos_tmu_data *);\n\tvoid (*tmu_initialize)(struct platform_device *);\n\tvoid (*tmu_control)(struct platform_device *, bool);\n\tint (*tmu_read)(struct exynos_tmu_data *);\n\tvoid (*tmu_set_emulation)(struct exynos_tmu_data *, int);\n\tvoid (*tmu_clear_irqs)(struct exynos_tmu_data *);\n};\n\nstruct exynos_trng_dev {\n\tstruct device *dev;\n\tvoid *mem;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct hwrng rng;\n\tlong unsigned int flags;\n};\n\nstruct ufs_pa_layer_attr {\n\tu32 gear_rx;\n\tu32 gear_tx;\n\tu32 lane_rx;\n\tu32 lane_tx;\n\tu32 pwr_rx;\n\tu32 pwr_tx;\n\tu32 hs_rate;\n};\n\nstruct ufs_phy_time_cfg {\n\tu32 tx_linereset_p;\n\tu32 tx_linereset_n;\n\tu32 tx_high_z_cnt;\n\tu32 tx_base_n_val;\n\tu32 tx_gran_n_val;\n\tu32 tx_sleep_cnt;\n\tu32 rx_linereset;\n\tu32 rx_hibern8_wait;\n\tu32 rx_base_n_val;\n\tu32 rx_gran_n_val;\n\tu32 rx_sleep_cnt;\n\tu32 rx_stall_cnt;\n};\n\nstruct ufs_hba;\n\nstruct exynos_ufs_drv_data;\n\nstruct exynos_ufs {\n\tstruct ufs_hba *hba;\n\tstruct phy *phy;\n\tvoid *reg_hci;\n\tvoid *reg_unipro;\n\tvoid *reg_ufsp;\n\tstruct clk *clk_hci_core;\n\tstruct clk *clk_unipro_main;\n\tstruct clk *clk_apb;\n\tu32 pclk_rate;\n\tu32 pclk_div;\n\tu32 pclk_avail_min;\n\tu32 pclk_avail_max;\n\tlong unsigned int mclk_rate;\n\tint avail_ln_rx;\n\tint avail_ln_tx;\n\tint rx_sel_idx;\n\tstruct ufs_pa_layer_attr dev_req_params;\n\tstruct ufs_phy_time_cfg t_cfg;\n\tktime_t entry_hibern8_t;\n\tconst struct exynos_ufs_drv_data *drv_data;\n\tstruct regmap *sysreg;\n\tu32 iocc_offset;\n\tu32 iocc_mask;\n\tu32 iocc_val;\n\tu32 opts;\n};\n\nstruct ufs_hba_variant_ops;\n\nstruct exynos_ufs_uic_attr;\n\nstruct exynos_ufs_drv_data {\n\tconst struct ufs_hba_variant_ops *vops;\n\tstruct exynos_ufs_uic_attr *uic_attr;\n\tunsigned int quirks;\n\tunsigned int opts;\n\tu32 iocc_mask;\n\tint (*drv_init)(struct exynos_ufs *);\n\tint (*pre_link)(struct exynos_ufs *);\n\tint (*post_link)(struct exynos_ufs *);\n\tint (*pre_pwr_change)(struct exynos_ufs *, struct ufs_pa_layer_attr *);\n\tint (*post_pwr_change)(struct exynos_ufs *, const struct ufs_pa_layer_attr *);\n\tint (*pre_hce_enable)(struct exynos_ufs *);\n\tint (*post_hce_enable)(struct exynos_ufs *);\n\tint (*suspend)(struct exynos_ufs *);\n};\n\nstruct exynos_ufs_uic_attr {\n\tunsigned int tx_trailingclks;\n\tunsigned int tx_dif_p_nsec;\n\tunsigned int tx_dif_n_nsec;\n\tunsigned int tx_high_z_cnt_nsec;\n\tunsigned int tx_base_unit_nsec;\n\tunsigned int tx_gran_unit_nsec;\n\tunsigned int tx_sleep_cnt;\n\tunsigned int tx_min_activatetime;\n\tunsigned int rx_filler_enable;\n\tunsigned int rx_dif_p_nsec;\n\tunsigned int rx_hibern8_wait_nsec;\n\tunsigned int rx_base_unit_nsec;\n\tunsigned int rx_gran_unit_nsec;\n\tunsigned int rx_sleep_cnt;\n\tunsigned int rx_stall_cnt;\n\tunsigned int rx_hs_g1_sync_len_cap;\n\tunsigned int rx_hs_g2_sync_len_cap;\n\tunsigned int rx_hs_g3_sync_len_cap;\n\tunsigned int rx_hs_g1_prep_sync_len_cap;\n\tunsigned int rx_hs_g2_prep_sync_len_cap;\n\tunsigned int rx_hs_g3_prep_sync_len_cap;\n\tunsigned int cmn_pwm_clk_ctrl;\n\tunsigned int pa_dbg_clk_period_off;\n\tunsigned int pa_dbg_opt_suite1_val;\n\tunsigned int pa_dbg_opt_suite1_off;\n\tunsigned int pa_dbg_opt_suite2_val;\n\tunsigned int pa_dbg_opt_suite2_off;\n\tunsigned int rx_adv_fine_gran_sup_en;\n\tunsigned int rx_adv_fine_gran_step;\n\tunsigned int rx_min_actv_time_cap;\n\tunsigned int rx_hibern8_time_cap;\n\tunsigned int rx_adv_min_actv_time_cap;\n\tunsigned int rx_adv_hibern8_time_cap;\n\tunsigned int pa_granularity;\n\tunsigned int pa_tactivate;\n\tunsigned int pa_hibern8time;\n};\n\nstruct exynos_usi_variant;\n\nstruct exynos_usi {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct clk_bulk_data *clks;\n\tsize_t mode;\n\tbool clkreq_on;\n\tstruct regmap *sysreg;\n\tunsigned int sw_conf;\n\tconst struct exynos_usi_variant *data;\n};\n\nstruct exynos_usi_mode {\n\tconst char *name;\n\tunsigned int val;\n};\n\nstruct exynos_usi_variant {\n\tenum exynos_usi_ver ver;\n\tunsigned int sw_conf_mask;\n\tsize_t min_mode;\n\tsize_t max_mode;\n\tsize_t num_clks;\n\tconst char * const *clk_names;\n};\n\nstruct exynos_weint_data {\n\tunsigned int irq;\n\tstruct samsung_pin_bank *bank;\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct f_sdhost_priv {\n\tstruct clk *clk_iface;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tu32 vendor_hs200;\n\tstruct device *dev;\n\tbool enable_cmd_dat_delay;\n};\n\nstruct failover_ops;\n\nstruct failover {\n\tstruct list_head list;\n\tstruct net_device *failover_dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct failover_ops *ops;\n};\n\nstruct failover_ops {\n\tint (*slave_pre_register)(struct net_device *, struct net_device *);\n\tint (*slave_register)(struct net_device *, struct net_device *);\n\tint (*slave_pre_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_unregister)(struct net_device *, struct net_device *);\n\tint (*slave_link_change)(struct net_device *, struct net_device *);\n\tint (*slave_name_change)(struct net_device *, struct net_device *);\n\trx_handler_result_t (*slave_handle_frame)(struct sk_buff **);\n};\n\nstruct regulator_init_data;\n\nstruct fan53555_device_info {\n\tenum fan53555_vendor vendor;\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct regulator_init_data *regulator;\n\tint chip_id;\n\tint chip_rev;\n\tunsigned int vol_reg;\n\tunsigned int sleep_reg;\n\tunsigned int en_reg;\n\tunsigned int sleep_en_reg;\n\tunsigned int vsel_min;\n\tunsigned int vsel_step;\n\tunsigned int vsel_count;\n\tunsigned int mode_reg;\n\tunsigned int mode_mask;\n\tunsigned int sleep_vol_cache;\n\tunsigned int slew_reg;\n\tunsigned int slew_mask;\n\tconst unsigned int *ramp_delay_table;\n\tunsigned int n_ramp_values;\n\tunsigned int enable_time;\n\tunsigned int slew_rate;\n};\n\nstruct fan53555_platform_data {\n\tstruct regulator_init_data *regulator;\n\tunsigned int slew_rate;\n\tunsigned int sleep_vsel_id;\n};\n\nstruct fan_fsid {\n\tstruct super_block *sb;\n\t__kernel_fsid_t id;\n\tbool weak;\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct fanotify_event {\n\tstruct fsnotify_event fse;\n\tstruct hlist_node merge_list;\n\tu32 mask;\n\tstruct {\n\t\tunsigned int type: 3;\n\t\tunsigned int hash: 29;\n\t};\n\tstruct pid *pid;\n};\n\nstruct fanotify_fh {\n\tu8 type;\n\tu8 len;\n\tu8 flags;\n\tu8 pad;\n};\n\nstruct fanotify_error_event {\n\tstruct fanotify_event fae;\n\ts32 error;\n\tu32 err_count;\n\t__kernel_fsid_t fsid;\n\tstruct {\n\t\tstruct fanotify_fh object_fh;\n\t\tunsigned char _inline_fh_buf[128];\n\t};\n};\n\nstruct fanotify_event_info_header {\n\t__u8 info_type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_event_info_error {\n\tstruct fanotify_event_info_header hdr;\n\t__s32 error;\n\t__u32 error_count;\n};\n\nstruct fanotify_event_info_fid {\n\tstruct fanotify_event_info_header hdr;\n\t__kernel_fsid_t fsid;\n\tunsigned char handle[0];\n};\n\nstruct fanotify_event_info_mnt {\n\tstruct fanotify_event_info_header hdr;\n\t__u64 mnt_id;\n};\n\nstruct fanotify_event_info_pidfd {\n\tstruct fanotify_event_info_header hdr;\n\t__s32 pidfd;\n};\n\nstruct fanotify_event_info_range {\n\tstruct fanotify_event_info_header hdr;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 count;\n};\n\nstruct fanotify_event_metadata {\n\t__u32 event_len;\n\t__u8 vers;\n\t__u8 reserved;\n\t__u16 metadata_len;\n\t__u64 mask;\n\t__s32 fd;\n\t__s32 pid;\n};\n\nstruct fanotify_fid_event {\n\tstruct fanotify_event fae;\n\t__kernel_fsid_t fsid;\n\tstruct {\n\t\tstruct fanotify_fh object_fh;\n\t\tunsigned char _inline_fh_buf[12];\n\t};\n};\n\nstruct fanotify_group_private_data {\n\tstruct hlist_head *merge_hash;\n\tstruct list_head access_list;\n\twait_queue_head_t access_waitq;\n\tint flags;\n\tint f_flags;\n\tstruct ucounts *ucounts;\n\tmempool_t error_events_pool;\n\tstruct list_head perm_grp_list;\n};\n\nstruct fanotify_info {\n\tu8 dir_fh_totlen;\n\tu8 dir2_fh_totlen;\n\tu8 file_fh_totlen;\n\tu8 name_len;\n\tu8 name2_len;\n\tu8 pad[3];\n\tunsigned char buf[0];\n};\n\nstruct fanotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\t__kernel_fsid_t fsid;\n};\n\nstruct fanotify_mnt_event {\n\tstruct fanotify_event fae;\n\tu64 mnt_id;\n};\n\nstruct fanotify_name_event {\n\tstruct fanotify_event fae;\n\t__kernel_fsid_t fsid;\n\tstruct fanotify_info info;\n};\n\nstruct fanotify_path_event {\n\tstruct fanotify_event fae;\n\tstruct path path;\n};\n\nstruct fanotify_response_info_header {\n\t__u8 type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_response_info_audit_rule {\n\tstruct fanotify_response_info_header hdr;\n\t__u32 rule_number;\n\t__u32 subj_trust;\n\t__u32 obj_trust;\n};\n\nstruct fanotify_perm_event {\n\tstruct fanotify_event fae;\n\tstruct path path;\n\tconst loff_t *ppos;\n\tsize_t count;\n\tu32 response;\n\tshort unsigned int state;\n\tshort unsigned int watchdog_cnt;\n\tint fd;\n\tpid_t recv_pid;\n\tunion {\n\t\tstruct fanotify_response_info_header hdr;\n\t\tstruct fanotify_response_info_audit_rule audit_rule;\n\t};\n};\n\nstruct fanotify_response {\n\t__s32 fd;\n\t__u32 response;\n};\n\nstruct fanout_args {\n\t__u16 id;\n\t__u16 type_flags;\n\t__u32 max_num_members;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_bios_param_block {\n\tu16 fat_sector_size;\n\tu8 fat_sec_per_clus;\n\tu16 fat_reserved;\n\tu8 fat_fats;\n\tu16 fat_dir_entries;\n\tu16 fat_sectors;\n\tu16 fat_fat_length;\n\tu32 fat_total_sect;\n\tu8 fat16_state;\n\tu32 fat16_vol_id;\n\tu32 fat32_length;\n\tu32 fat32_root_cluster;\n\tu16 fat32_info_sector;\n\tu8 fat32_state;\n\tu32 fat32_vol_id;\n};\n\nstruct fat_boot_fsinfo {\n\t__le32 signature1;\n\t__le32 reserved1[120];\n\t__le32 signature2;\n\t__le32 free_clusters;\n\t__le32 next_cluster;\n\t__le32 reserved2[4];\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fat_cache {\n\tstruct list_head cache_list;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_cache_id {\n\tunsigned int id;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_entry {\n\tint entry;\n\tunion {\n\t\tu8 *ent12_p[2];\n\t\t__le16 *ent16_p;\n\t\t__le32 *ent32_p;\n\t} u;\n\tint nr_bhs;\n\tstruct buffer_head *bhs[2];\n\tstruct inode *fat_inode;\n};\n\nstruct fat_fid {\n\tu32 i_gen;\n\tu32 i_pos_low;\n\tu16 i_pos_hi;\n\tu16 parent_i_pos_hi;\n\tu32 parent_i_pos_low;\n\tu32 parent_i_gen;\n};\n\nstruct fat_floppy_defaults {\n\tunsigned int nr_sectors;\n\tunsigned int sec_per_clus;\n\tunsigned int dir_entries;\n\tunsigned int media;\n\tunsigned int fat_length;\n};\n\nstruct fat_ioctl_filldir_callback {\n\tstruct dir_context ctx;\n\tvoid *dirent;\n\tint result;\n\tconst char *longname;\n\tint long_len;\n\tconst char *shortname;\n\tint short_len;\n};\n\nstruct fat_mount_options {\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tshort unsigned int fs_fmask;\n\tshort unsigned int fs_dmask;\n\tshort unsigned int codepage;\n\tint time_offset;\n\tchar *iocharset;\n\tshort unsigned int shortname;\n\tunsigned char name_check;\n\tunsigned char errors;\n\tunsigned char nfs;\n\tshort unsigned int allow_utime;\n\tunsigned int quiet: 1;\n\tunsigned int showexec: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int dotsOK: 1;\n\tunsigned int isvfat: 1;\n\tunsigned int utf8: 1;\n\tunsigned int unicode_xlate: 1;\n\tunsigned int numtail: 1;\n\tunsigned int flush: 1;\n\tunsigned int nocase: 1;\n\tunsigned int usefree: 1;\n\tunsigned int tz_set: 1;\n\tunsigned int rodir: 1;\n\tunsigned int discard: 1;\n\tunsigned int dos1xfloppy: 1;\n\tunsigned int debug: 1;\n};\n\nstruct msdos_dir_entry;\n\nstruct fat_slot_info {\n\tloff_t i_pos;\n\tloff_t slot_off;\n\tint nr_slots;\n\tstruct msdos_dir_entry *de;\n\tstruct buffer_head *bh;\n};\n\nstruct fatent_operations {\n\tvoid (*ent_blocknr)(struct super_block *, int, int *, sector_t *);\n\tvoid (*ent_set_ptr)(struct fat_entry *, int);\n\tint (*ent_bread)(struct super_block *, struct fat_entry *, int, sector_t);\n\tint (*ent_get)(struct fat_entry *);\n\tvoid (*ent_put)(struct fat_entry *, int);\n\tint (*ent_next)(struct fat_entry *);\n};\n\nstruct fatent_ra {\n\tsector_t cur;\n\tsector_t limit;\n\tunsigned int ra_blocks;\n\tsector_t ra_advance;\n\tsector_t ra_next;\n\tsector_t ra_limit;\n};\n\nstruct fault_attr {};\n\nstruct fault_info {\n\tint (*fn)(long unsigned int, long unsigned int, struct pt_regs *);\n\tint sig;\n\tint code;\n\tconst char *name;\n};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_address {\n\tvoid *address;\n\tint bits;\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_bitmap4x_iter {\n\tconst u8 *data;\n\tu32 fgxcolor;\n\tu32 bgcolor;\n\tint width;\n\tint i;\n\tconst u32 *expand;\n\tint bpp;\n\tbool top;\n};\n\nstruct fb_bitmap_iter {\n\tconst u8 *data;\n\tlong unsigned int colors[2];\n\tint width;\n\tint i;\n};\n\nstruct fb_blit_caps {\n\tlong unsigned int x[1];\n\tlong unsigned int y[2];\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_cmap32 {\n\tu32 start;\n\tu32 len;\n\tcompat_caddr_t red;\n\tcompat_caddr_t green;\n\tcompat_caddr_t blue;\n\tcompat_caddr_t transp;\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_reverse {\n\tbool byte;\n\tbool pixel;\n};\n\nstruct fb_color_iter {\n\tconst u8 *data;\n\tconst u32 *palette;\n\tstruct fb_reverse reverse;\n\tint shift;\n\tint width;\n\tint i;\n};\n\nstruct fb_con2fbmap {\n\t__u32 console;\n\t__u32 framebuffer;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\nstruct fb_info;\n\nstruct fb_deferred_io {\n\tlong unsigned int delay;\n\tbool sort_pagereflist;\n\tint open_count;\n\tstruct mutex lock;\n\tstruct list_head pagereflist;\n\tstruct address_space *mapping;\n\tstruct page * (*get_page)(struct fb_info *, long unsigned int);\n\tvoid (*deferred_io)(struct fb_info *, struct list_head *);\n};\n\nstruct fb_deferred_io_pageref {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tstruct list_head list;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_fix_screeninfo32 {\n\tchar id[16];\n\tcompat_caddr_t smem_start;\n\tu32 smem_len;\n\tu32 type;\n\tu32 type_aux;\n\tu32 visual;\n\tu16 xpanstep;\n\tu16 ypanstep;\n\tu16 ywrapstep;\n\tu32 line_length;\n\tcompat_caddr_t mmio_start;\n\tu32 mmio_len;\n\tu32 accel;\n\tu16 reserved[3];\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_videomode;\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tlong unsigned int blit_x[1];\n\tlong unsigned int blit_y[2];\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct lcd_device;\n\nstruct fb_ops;\n\nstruct fbcon_par;\n\nstruct fb_info {\n\trefcount_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tint blank;\n\tstruct lcd_device *lcd_dev;\n\tstruct delayed_work deferred_work;\n\tlong unsigned int npagerefs;\n\tstruct fb_deferred_io_pageref *pagerefs;\n\tstruct fb_deferred_io *fbdefio;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tstruct device *dev;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tstruct fbcon_par *fbcon_par;\n\tvoid *par;\n\tbool skip_vt_switch;\n\tbool skip_panic;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n};\n\nstruct fb_pattern {\n\tlong unsigned int pixels;\n\tint left;\n\tint right;\n\tstruct fb_reverse reverse;\n};\n\nstruct fbcon_bitops {\n\tvoid (*bmove)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*clear)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*putcs)(struct vc_data *, struct fb_info *, const short unsigned int *, int, int, int, int, int);\n\tvoid (*clear_margins)(struct vc_data *, struct fb_info *, int, int);\n\tvoid (*cursor)(struct vc_data *, struct fb_info *, bool, int, int);\n\tint (*update_start)(struct fb_info *);\n\tint (*rotate_font)(struct fb_info *, struct vc_data *);\n};\n\nstruct fbcon_display {\n\tconst u_char *fontdata;\n\tint userfont;\n\tshort int yscroll;\n\tint vrows;\n\tint cursor_shape;\n\tint con_rotate;\n\tu32 xres_virtual;\n\tu32 yres_virtual;\n\tu32 height;\n\tu32 width;\n\tu32 bits_per_pixel;\n\tu32 grayscale;\n\tu32 nonstd;\n\tu32 accel_flags;\n\tu32 rotate;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tconst struct fb_videomode *mode;\n};\n\nstruct fbcon_par {\n\tstruct fb_var_screeninfo var;\n\tstruct delayed_work cursor_work;\n\tstruct fb_cursor cursor_state;\n\tstruct fbcon_display *p;\n\tstruct fb_info *info;\n\tint currcon;\n\tint cur_blink_jiffies;\n\tint cursor_flash;\n\tint cursor_reset;\n\tint blank_state;\n\tint graphics;\n\tbool initialized;\n\tint rotate;\n\tint cur_rotate;\n\tchar *cursor_data;\n\tu8 *fontbuffer;\n\tu8 *fontdata;\n\tu8 *cursor_src;\n\tu32 cursor_size;\n\tu32 fd_size;\n\tconst struct fbcon_bitops *bitops;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdt_errtabent {\n\tconst char *str;\n};\n\nstruct fdt_header {\n\tfdt32_t magic;\n\tfdt32_t totalsize;\n\tfdt32_t off_dt_struct;\n\tfdt32_t off_dt_strings;\n\tfdt32_t off_mem_rsvmap;\n\tfdt32_t version;\n\tfdt32_t last_comp_version;\n\tfdt32_t boot_cpuid_phys;\n\tfdt32_t size_dt_strings;\n\tfdt32_t size_dt_struct;\n};\n\nstruct fdt_node_header {\n\tfdt32_t tag;\n\tchar name[0];\n};\n\nstruct fdt_property {\n\tfdt32_t tag;\n\tfdt32_t len;\n\tfdt32_t nameoff;\n\tchar data[0];\n};\n\nstruct fdt_reserve_entry {\n\tfdt64_t address;\n\tfdt64_t size;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_devinfo {\n\tu32 quirks;\n};\n\nstruct fec_dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n};\n\nunion fec_rx_buffer {\n\tvoid *buf_p;\n\tstruct page *page;\n\tstruct xdp_buff *xdp;\n};\n\nstruct fec_enet_priv_rx_q {\n\tstruct bufdesc_prop bd;\n\tunion fec_rx_buffer rx_buf[256];\n\tstruct xsk_buff_pool *xsk_pool;\n\tstruct page_pool *page_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tu32 stats[7];\n\tu8 id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct fec_tx_buffer {\n\tvoid *buf_p;\n\tenum fec_txbuf_type type;\n};\n\nstruct fec_enet_priv_tx_q {\n\tstruct bufdesc_prop bd;\n\tunsigned char *tx_bounce[1024];\n\tstruct fec_tx_buffer tx_buf[1024];\n\tstruct xsk_buff_pool *xsk_pool;\n\tshort unsigned int tx_stop_threshold;\n\tshort unsigned int tx_wake_threshold;\n\tstruct bufdesc *dirty_tx;\n\tchar *tso_hdrs;\n\tdma_addr_t tso_hdrs_dma;\n};\n\nstruct fec_stop_mode_gpr {\n\tstruct regmap *gpr;\n\tu8 reg;\n\tu8 bit;\n};\n\nstruct imx_sc_ipc;\n\nstruct fec_enet_private {\n\tvoid *hwp;\n\tstruct net_device *netdev;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_ref;\n\tstruct clk *clk_enet_out;\n\tstruct clk *clk_ptp;\n\tstruct clk *clk_2x_txclk;\n\tbool ptp_clk_on;\n\tstruct mutex ptp_clk_mutex;\n\tunsigned int num_tx_queues;\n\tunsigned int num_rx_queues;\n\tstruct fec_enet_priv_tx_q *tx_queue[3];\n\tstruct fec_enet_priv_rx_q *rx_queue[3];\n\tunsigned int total_tx_ring_size;\n\tunsigned int total_rx_ring_size;\n\tunsigned int max_buf_size;\n\tunsigned int pagepool_order;\n\tunsigned int rx_frame_size;\n\tstruct platform_device *pdev;\n\tint dev_id;\n\tstruct mii_bus *mii_bus;\n\tuint phy_speed;\n\tphy_interface_t phy_interface;\n\tstruct device_node *phy_node;\n\tbool rgmii_txc_dly;\n\tbool rgmii_rxc_dly;\n\tbool rpm_active;\n\tint link;\n\tint full_duplex;\n\tint speed;\n\tint irq[3];\n\tbool bufdesc_ex;\n\tint pause_flag;\n\tint wol_flag;\n\tint wake_irq;\n\tu32 quirks;\n\tstruct napi_struct napi;\n\tint csum_flags;\n\tstruct work_struct tx_timeout_work;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_caps;\n\tspinlock_t tmreg_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tu32 cycle_speed;\n\tint hwts_rx_en;\n\tint hwts_tx_en;\n\tstruct delayed_work time_keep;\n\tstruct regulator *reg_phy;\n\tstruct fec_stop_mode_gpr stop_gpr;\n\tstruct pm_qos_request pm_qos_req;\n\tunsigned int tx_align;\n\tunsigned int rx_shift;\n\tunsigned int rx_pkts_itr;\n\tunsigned int rx_time_itr;\n\tunsigned int tx_pkts_itr;\n\tunsigned int tx_time_itr;\n\tunsigned int itr_clk_rate;\n\tunsigned int clk_ref_rate;\n\tunsigned int ptp_inc;\n\tint pps_channel;\n\tunsigned int reload_period;\n\tint pps_enable;\n\tunsigned int next_counter;\n\tbool perout_enable;\n\tstruct hrtimer perout_timer;\n\tu64 perout_stime;\n\tstruct imx_sc_ipc *ipc_handle;\n\tstruct bpf_prog *xdp_prog;\n\tstruct {\n\t\tint pps_enable;\n\t\tu64 ns_sys;\n\t\tu64 ns_phc;\n\t\tu32 at_corr;\n\t\tu8 at_inc_corr;\n\t} ptp_saved_state;\n\tu64 ethtool_stats[0];\n};\n\nstruct fec_platform_data {\n\tphy_interface_t phy;\n\tunsigned char mac[6];\n\tvoid (*sleep_mode_enable)(int);\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[2];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct fec_stat {\n\tchar name[32];\n\tu16 offset;\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct trace_seq;\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tbool is_signed;\n\tbool is_string;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[2];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct ff_periodic_effect_compat {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\tcompat_uptr_t custom_data;\n};\n\nstruct ff_effect_compat {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect_compat periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t} u;\n};\n\nstruct ffa_mem_region_addr_range {\n\tu64 address;\n\tu32 pg_cnt;\n\tu32 reserved;\n};\n\nstruct ffa_composite_mem_region {\n\tu32 total_pg_cnt;\n\tu32 addr_range_cnt;\n\tu64 reserved;\n\tstruct ffa_mem_region_addr_range constituents[0];\n};\n\nstruct ffa_device;\n\nstruct ffa_cpu_ops {\n\tint (*run)(struct ffa_device *, u16);\n};\n\nstruct ffa_ops;\n\nstruct ffa_device {\n\tu32 id;\n\tu32 properties;\n\tint vm_id;\n\tbool mode_32bit;\n\tuuid_t uuid;\n\tstruct device dev;\n\tconst struct ffa_ops *ops;\n};\n\nstruct ffa_device_id {\n\tuuid_t uuid;\n};\n\nstruct ffa_driver {\n\tconst char *name;\n\tint (*probe)(struct ffa_device *);\n\tvoid (*remove)(struct ffa_device *);\n\tconst struct ffa_device_id *id_table;\n\tstruct device_driver driver;\n};\n\nstruct ffa_partition_info;\n\nstruct ffa_info_ops {\n\tu32 (*api_version_get)(void);\n\tint (*partition_info_get)(const char *, struct ffa_partition_info *);\n};\n\nstruct ffa_mem_ops_args;\n\nstruct ffa_mem_ops {\n\tint (*memory_reclaim)(u64, u32);\n\tint (*memory_share)(struct ffa_mem_ops_args *);\n\tint (*memory_lend)(struct ffa_mem_ops_args *);\n};\n\nstruct ffa_mem_region_attributes;\n\nstruct ffa_mem_ops_args {\n\tbool use_txbuf;\n\tu32 nattrs;\n\tu32 flags;\n\tu64 tag;\n\tu64 g_handle;\n\tstruct scatterlist *sg;\n\tstruct ffa_mem_region_attributes *attrs;\n};\n\nstruct ffa_mem_region {\n\tu16 sender_id;\n\tu16 attributes;\n\tu32 flags;\n\tu64 handle;\n\tu64 tag;\n\tu32 ep_mem_size;\n\tu32 ep_count;\n\tu32 ep_mem_offset;\n\tu32 reserved[3];\n};\n\nstruct ffa_mem_region_attributes {\n\tu16 receiver;\n\tu8 attrs;\n\tu8 flag;\n\tu32 composite_off;\n\tu8 impdef_val[16];\n\tu64 reserved;\n};\n\nstruct ffa_send_direct_data;\n\nstruct ffa_send_direct_data2;\n\nstruct ffa_msg_ops {\n\tvoid (*mode_32bit_set)(struct ffa_device *);\n\tint (*sync_send_receive)(struct ffa_device *, struct ffa_send_direct_data *);\n\tint (*indirect_send)(struct ffa_device *, void *, size_t);\n\tint (*sync_send_receive2)(struct ffa_device *, struct ffa_send_direct_data2 *);\n};\n\ntypedef void (*ffa_sched_recv_cb)(u16, bool, void *);\n\ntypedef void (*ffa_notifier_cb)(int, void *);\n\ntypedef void (*ffa_fwk_notifier_cb)(int, void *, void *);\n\nstruct ffa_notifier_ops {\n\tint (*sched_recv_cb_register)(struct ffa_device *, ffa_sched_recv_cb, void *);\n\tint (*sched_recv_cb_unregister)(struct ffa_device *);\n\tint (*notify_request)(struct ffa_device *, bool, ffa_notifier_cb, void *, int);\n\tint (*notify_relinquish)(struct ffa_device *, int);\n\tint (*fwk_notify_request)(struct ffa_device *, ffa_fwk_notifier_cb, void *, int);\n\tint (*fwk_notify_relinquish)(struct ffa_device *, int);\n\tint (*notify_send)(struct ffa_device *, int, bool, u16);\n};\n\nstruct ffa_ops {\n\tconst struct ffa_info_ops *info_ops;\n\tconst struct ffa_msg_ops *msg_ops;\n\tconst struct ffa_mem_ops *mem_ops;\n\tconst struct ffa_cpu_ops *cpu_ops;\n\tconst struct ffa_notifier_ops *notifier_ops;\n};\n\nstruct ffa_partition_info {\n\tu16 id;\n\tu16 exec_ctxt;\n\tu32 properties;\n\tuuid_t uuid;\n};\n\nstruct ffa_send_direct_data {\n\tlong unsigned int data0;\n\tlong unsigned int data1;\n\tlong unsigned int data2;\n\tlong unsigned int data3;\n\tlong unsigned int data4;\n};\n\nstruct ffa_send_direct_data2 {\n\tlong unsigned int data[14];\n};\n\nstruct fgt_masks {\n\tconst char *str;\n\tu64 mask;\n\tu64 nmask;\n\tu64 res0;\n\tu64 res1;\n};\n\nstruct mtk_fh;\n\nstruct fh_operation {\n\tint (*hopping)(struct mtk_fh *, unsigned int, unsigned int);\n\tint (*ssc_enable)(struct mtk_fh *, u32);\n};\n\nstruct fh_pll_data {\n\tint pll_id;\n\tint fh_id;\n\tint fh_ver;\n\tu32 fhx_offset;\n\tu32 dds_mask;\n\tu32 slope0_value;\n\tu32 slope1_value;\n\tu32 sfstrx_en;\n\tu32 frddsx_en;\n\tu32 fhctlx_en;\n\tu32 tgl_org;\n\tu32 dvfs_tri;\n\tu32 pcwchg;\n\tu32 dt_val;\n\tu32 df_val;\n\tu32 updnlmt_shft;\n\tu32 msk_frddsx_dys;\n\tu32 msk_frddsx_dts;\n};\n\nstruct fh_pll_regs {\n\tvoid *reg_hp_en;\n\tvoid *reg_clk_con;\n\tvoid *reg_rst_con;\n\tvoid *reg_slope0;\n\tvoid *reg_slope1;\n\tvoid *reg_cfg;\n\tvoid *reg_updnlmt;\n\tvoid *reg_dds;\n\tvoid *reg_dvfs;\n\tvoid *reg_mon;\n};\n\nstruct fh_pll_state {\n\tvoid *base;\n\tu32 fh_enable;\n\tu32 ssc_rate;\n};\n\nstruct fhctl_offset {\n\tu32 offset_hp_en;\n\tu32 offset_clk_con;\n\tu32 offset_rst_con;\n\tu32 offset_slope0;\n\tu32 offset_slope1;\n\tu32 offset_cfg;\n\tu32 offset_updnlmt;\n\tu32 offset_dds;\n\tu32 offset_dvfs;\n\tu32 offset_mon;\n};\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct fib6_node;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tloff_t pos;\n\tt_key key;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} __attribute__((packed)) i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\ntypedef struct file *class_gmem_get_file_t;\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct io_uring_cmd;\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct tpm_chip;\n\nstruct tpm_space;\n\nstruct file_priv {\n\tstruct tpm_chip *chip;\n\tstruct tpm_space *space;\n\tstruct mutex buffer_mutex;\n\tstruct timer_list user_read_timer;\n\tstruct work_struct timeout_work;\n\tstruct work_struct async_work;\n\twait_queue_head_t async_wait;\n\tssize_t response_length;\n\tbool response_read;\n\tbool command_enqueued;\n\tu8 data_buffer[4096];\n};\n\nstruct file_range {\n\tconst struct path *path;\n\tloff_t pos;\n\tsize_t count;\n};\n\nstruct page_counter;\n\nstruct file_region {\n\tstruct list_head link;\n\tlong int from;\n\tlong int to;\n\tstruct page_counter *reservation_counter;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[168];\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct filter_head {\n\tstruct list_head list;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rcu_work rwork;\n\t};\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\nstruct regex;\n\nstruct ftrace_event_field;\n\nstruct filter_pred {\n\tstruct regex *regex;\n\tstruct cpumask *mask;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tu64 val;\n\tu64 val2;\n\tenum filter_pred_fn fn_num;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nstruct find_child_walk_data {\n\tstruct acpi_device *adev;\n\tu64 address;\n\tint score;\n\tbool check_sta;\n\tbool check_children;\n};\n\nstruct find_interface_arg {\n\tint minor;\n\tstruct device_driver *drv;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct finfo {\n\tefi_file_info_t info;\n\tefi_char16_t filename[256];\n};\n\nstruct fiper_regs {\n\tu32 tmr_fiper1;\n\tu32 tmr_fiper2;\n\tu32 tmr_fiper3;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct firmware_fallback_config {\n\tunsigned int force_sysfs_fallback;\n\tunsigned int ignore_sysfs_fallback;\n\tint old_timeout;\n\tint loading_timeout;\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\nstruct fixed_dev_type {\n\tbool has_enable_clock;\n\tbool has_performance_state;\n};\n\nstruct mtd_partition;\n\nstruct fixed_partitions_quirks {\n\tint (*post_parse)(struct mtd_info *, struct mtd_partition *, int);\n};\n\nstruct fixed_phy_status {\n\tint speed;\n\tint duplex;\n\tbool link: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n};\n\nstruct fixed_phy {\n\tstruct phy_device *phydev;\n\tstruct fixed_phy_status status;\n\tint (*link_update)(struct net_device *, struct fixed_phy_status *);\n};\n\nstruct fixed_voltage_config {\n\tconst char *supply_name;\n\tconst char *input_supply;\n\tint microvolts;\n\tunsigned int startup_delay;\n\tunsigned int off_on_delay;\n\tunsigned int enabled_at_boot: 1;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct regulator_state {\n\tint uV;\n\tint min_uV;\n\tint max_uV;\n\tunsigned int mode;\n\tint enabled;\n\tbool changeable;\n};\n\nstruct notification_limit {\n\tint prot;\n\tint err;\n\tint warn;\n};\n\nstruct regulation_constraints {\n\tconst char *name;\n\tint min_uV;\n\tint max_uV;\n\tint uV_offset;\n\tint min_uA;\n\tint max_uA;\n\tint ilim_uA;\n\tint pw_budget_mW;\n\tint system_load;\n\tu32 *max_spread;\n\tint max_uV_step;\n\tunsigned int valid_modes_mask;\n\tunsigned int valid_ops_mask;\n\tint input_uV;\n\tstruct regulator_state state_disk;\n\tstruct regulator_state state_mem;\n\tstruct regulator_state state_standby;\n\tstruct notification_limit over_curr_limits;\n\tstruct notification_limit over_voltage_limits;\n\tstruct notification_limit under_voltage_limits;\n\tstruct notification_limit temp_limits;\n\tsuspend_state_t initial_state;\n\tunsigned int initial_mode;\n\tunsigned int ramp_delay;\n\tunsigned int settling_time;\n\tunsigned int settling_time_up;\n\tunsigned int settling_time_down;\n\tunsigned int enable_time;\n\tunsigned int uv_less_critical_window_ms;\n\tunsigned int active_discharge;\n\tunsigned int always_on: 1;\n\tunsigned int boot_on: 1;\n\tunsigned int apply_uV: 1;\n\tunsigned int ramp_disable: 1;\n\tunsigned int soft_start: 1;\n\tunsigned int pull_down: 1;\n\tunsigned int system_critical: 1;\n\tunsigned int over_current_protection: 1;\n\tunsigned int over_current_detection: 1;\n\tunsigned int over_voltage_detection: 1;\n\tunsigned int under_voltage_detection: 1;\n\tunsigned int over_temp_detection: 1;\n};\n\nstruct regulator_consumer_supply;\n\nstruct regulator_init_data {\n\tconst char *supply_regulator;\n\tstruct regulation_constraints constraints;\n\tint num_consumer_supplies;\n\tstruct regulator_consumer_supply *consumer_supplies;\n\tvoid *driver_data;\n};\n\nstruct pdev_archdata {};\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct fixed_regulator_data {\n\tstruct fixed_voltage_config cfg;\n\tstruct regulator_init_data init_data;\n\tstruct platform_device pdev;\n};\n\nstruct fixed_voltage_data {\n\tstruct regulator_desc desc;\n\tstruct regulator_dev *dev;\n\tstruct clk *enable_clock;\n\tunsigned int enable_counter;\n\tint performance_state;\n};\n\nstruct flash_info {\n\tchar *name;\n\tu64 jedec_id;\n\tunsigned int nr_pages;\n\tu16 pagesize;\n\tu16 pageoffset;\n\tu16 flags;\n};\n\nstruct flash_info___2 {\n\tconst char *name;\n\tuint16_t device_id;\n\tunsigned int page_size;\n\tunsigned int nr_pages;\n\tunsigned int erase_size;\n};\n\nstruct spi_nor_id;\n\nstruct spi_nor_otp_organization;\n\nstruct spi_nor_fixups;\n\nstruct flash_info___3 {\n\tchar *name;\n\tconst struct spi_nor_id *id;\n\tsize_t size;\n\tunsigned int sector_size;\n\tu16 page_size;\n\tu8 n_banks;\n\tu8 addr_nbytes;\n\tu16 flags;\n\tu8 no_sfdp_flags;\n\tu8 fixup_flags;\n\tu8 mfr_flags;\n\tconst struct spi_nor_otp_organization *otp;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct flash_platform_data {\n\tchar *name;\n\tstruct mtd_partition *parts;\n\tunsigned int nr_parts;\n\tchar *type;\n};\n\nstruct flchip_shared {\n\tstruct mutex lock;\n\tstruct flchip *writing;\n\tstruct flchip *erasing;\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct flow_action_police {\n\tu32 burst;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n};\n\nstruct nf_flowtable;\n\nstruct ip_tunnel_info;\n\nstruct psample_group;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_cls_common_offload {\n\tu32 chain_index;\n\t__be16 protocol;\n\tu32 prio;\n\tbool skip_sw;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct flow_cls_offload {\n\tstruct flow_cls_common_offload common;\n\tenum flow_cls_command command;\n\tbool use_act_stats;\n\tlong unsigned int cookie;\n\tstruct flow_rule *rule;\n\tstruct flow_stats stats;\n\tu32 classid;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 0;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct fm_port_fqs {\n\tstruct dpaa_fq *tx_defq;\n\tstruct dpaa_fq *tx_errq;\n\tstruct dpaa_fq *rx_defq;\n\tstruct dpaa_fq *rx_errq;\n\tstruct dpaa_fq *rx_pcdq;\n};\n\nstruct fman_intr_src {\n\tvoid (*isr_cb)(void *);\n\tvoid *src_handle;\n};\n\nstruct fman;\n\ntypedef irqreturn_t fman_exceptions_cb(struct fman *, enum fman_exceptions);\n\ntypedef irqreturn_t fman_bus_error_cb(struct fman *, u8, u64, u8, u16);\n\nstruct fman_dts_params {\n\tvoid *base_addr;\n\tstruct resource *res;\n\tu8 id;\n\tint err_irq;\n\tu16 clk_freq;\n\tu32 qman_channel_base;\n\tu32 num_of_qman_channels;\n\tstruct resource muram_res;\n};\n\nstruct fman_fpm_regs;\n\nstruct fman_bmi_regs;\n\nstruct fman_qmi_regs;\n\nstruct fman_dma_regs;\n\nstruct fman_hwp_regs;\n\nstruct fman_kg_regs;\n\nstruct fman_state_struct;\n\nstruct fman_cfg;\n\nstruct muram_info;\n\nstruct fman_keygen;\n\nstruct fman {\n\tstruct device *dev;\n\tvoid *base_addr;\n\tstruct fman_intr_src intr_mng[24];\n\tstruct fman_fpm_regs *fpm_regs;\n\tstruct fman_bmi_regs *bmi_regs;\n\tstruct fman_qmi_regs *qmi_regs;\n\tstruct fman_dma_regs *dma_regs;\n\tstruct fman_hwp_regs *hwp_regs;\n\tstruct fman_kg_regs *kg_regs;\n\tfman_exceptions_cb *exception_cb;\n\tfman_bus_error_cb *bus_error_cb;\n\tspinlock_t spinlock;\n\tstruct fman_state_struct *state;\n\tstruct fman_cfg *cfg;\n\tstruct muram_info *muram;\n\tstruct fman_keygen *keygen;\n\tlong unsigned int cam_offset;\n\tsize_t cam_size;\n\tlong unsigned int fifo_offset;\n\tsize_t fifo_size;\n\tu32 liodn_base[64];\n\tu32 liodn_offset[64];\n\tstruct fman_dts_params dts_params;\n};\n\nstruct fman_bmi_regs {\n\tu32 fmbm_init;\n\tu32 fmbm_cfg1;\n\tu32 fmbm_cfg2;\n\tu32 res000c[5];\n\tu32 fmbm_ievr;\n\tu32 fmbm_ier;\n\tu32 fmbm_ifr;\n\tu32 res002c[5];\n\tu32 fmbm_arb[8];\n\tu32 res0060[12];\n\tu32 fmbm_dtc[3];\n\tu32 res009c;\n\tu32 fmbm_dcv[12];\n\tu32 fmbm_dcm[12];\n\tu32 fmbm_gde;\n\tu32 fmbm_pp[63];\n\tu32 res0200;\n\tu32 fmbm_pfs[63];\n\tu32 res0300;\n\tu32 fmbm_spliodn[63];\n};\n\nstruct fman_buf_pool_depletion {\n\tbool pools_grp_mode_enable;\n\tu8 num_of_pools;\n\tbool pools_to_consider[64];\n\tbool single_pool_mode_enable;\n\tbool pools_to_consider_for_single_mode[64];\n};\n\nstruct fman_buffer_prefix_content {\n\tu16 priv_data_size;\n\tbool pass_prs_result;\n\tbool pass_time_stamp;\n\tbool pass_hash_result;\n\tu16 data_align;\n};\n\nstruct fman_cfg {\n\tu8 disp_limit_tsh;\n\tu8 prs_disp_tsh;\n\tu8 plcr_disp_tsh;\n\tu8 kg_disp_tsh;\n\tu8 bmi_disp_tsh;\n\tu8 qmi_enq_disp_tsh;\n\tu8 qmi_deq_disp_tsh;\n\tu8 fm_ctl1_disp_tsh;\n\tu8 fm_ctl2_disp_tsh;\n\tint dma_cache_override;\n\tenum fman_dma_aid_mode dma_aid_mode;\n\tu32 dma_axi_dbg_num_of_beats;\n\tu32 dma_cam_num_of_entries;\n\tu32 dma_watchdog;\n\tu8 dma_comm_qtsh_asrt_emer;\n\tu32 dma_write_buf_tsh_asrt_emer;\n\tu32 dma_read_buf_tsh_asrt_emer;\n\tu8 dma_comm_qtsh_clr_emer;\n\tu32 dma_write_buf_tsh_clr_emer;\n\tu32 dma_read_buf_tsh_clr_emer;\n\tu32 dma_sos_emergency;\n\tint dma_dbg_cnt_mode;\n\tint catastrophic_err;\n\tint dma_err;\n\tu32 exceptions;\n\tu16 clk_freq;\n\tu32 cam_base_addr;\n\tu32 fifo_base_addr;\n\tu32 total_fifo_size;\n\tu32 total_num_of_tasks;\n\tu32 qmi_def_tnums_thresh;\n};\n\nstruct fman_dma_regs {\n\tu32 fmdmsr;\n\tu32 fmdmmr;\n\tu32 fmdmtr;\n\tu32 fmdmhy;\n\tu32 fmdmsetr;\n\tu32 fmdmtah;\n\tu32 fmdmtal;\n\tu32 fmdmtcid;\n\tu32 fmdmra;\n\tu32 fmdmrd;\n\tu32 fmdmwcr;\n\tu32 fmdmebcr;\n\tu32 fmdmccqdr;\n\tu32 fmdmccqvr1;\n\tu32 fmdmccqvr2;\n\tu32 fmdmcqvr3;\n\tu32 fmdmcqvr4;\n\tu32 fmdmcqvr5;\n\tu32 fmdmsefrc;\n\tu32 fmdmsqfrc;\n\tu32 fmdmssrc;\n\tu32 fmdmdcr;\n\tu32 fmdmemsr;\n\tu32 res005c;\n\tu32 fmdmplr[32];\n\tu32 res00e0[968];\n};\n\nstruct fman_ext_pool_params {\n\tu8 id;\n\tu16 size;\n};\n\nstruct fman_ext_pools {\n\tu8 num_of_pools_used;\n\tstruct fman_ext_pool_params ext_buf_pool[8];\n};\n\nstruct fman_fpm_regs {\n\tu32 fmfp_tnc;\n\tu32 fmfp_prc;\n\tu32 fmfp_brkc;\n\tu32 fmfp_mxd;\n\tu32 fmfp_dist1;\n\tu32 fmfp_dist2;\n\tu32 fm_epi;\n\tu32 fm_rie;\n\tu32 fmfp_fcev[4];\n\tu32 res0030[4];\n\tu32 fmfp_cee[4];\n\tu32 res0050[4];\n\tu32 fmfp_tsc1;\n\tu32 fmfp_tsc2;\n\tu32 fmfp_tsp;\n\tu32 fmfp_tsf;\n\tu32 fm_rcr;\n\tu32 fmfp_extc;\n\tu32 fmfp_ext1;\n\tu32 fmfp_ext2;\n\tu32 fmfp_drd[16];\n\tu32 fmfp_dra;\n\tu32 fm_ip_rev_1;\n\tu32 fm_ip_rev_2;\n\tu32 fm_rstc;\n\tu32 fm_cld;\n\tu32 fm_npi;\n\tu32 fmfp_exte;\n\tu32 fmfp_ee;\n\tu32 fmfp_cev[4];\n\tu32 res00f0[4];\n\tu32 fmfp_ps[50];\n\tu32 res01c8[14];\n\tu32 fmfp_clfabc;\n\tu32 fmfp_clfcc;\n\tu32 fmfp_clfaval;\n\tu32 fmfp_clfbval;\n\tu32 fmfp_clfcval;\n\tu32 fmfp_clfamsk;\n\tu32 fmfp_clfbmsk;\n\tu32 fmfp_clfcmsk;\n\tu32 fmfp_clfamc;\n\tu32 fmfp_clfbmc;\n\tu32 fmfp_clfcmc;\n\tu32 fmfp_decceh;\n\tu32 res0230[116];\n\tu32 fmfp_ts[128];\n\tu32 res0600[640];\n};\n\nstruct fman_hwp_regs {\n\tu32 res0000[529];\n\tu32 fmprrpimac;\n\tu32 res[494];\n};\n\nstruct fman_iram_regs {\n\tu32 iadd;\n\tu32 idata;\n\tu32 itcfg;\n\tu32 iready;\n};\n\nstruct keygen_scheme {\n\tbool used;\n\tu8 hw_port_id;\n\tu32 base_fqid;\n\tu32 hash_fqid_count;\n\tbool use_hashing;\n\tbool symmetric_hash;\n\tu8 hashShift;\n\tu32 match_vector;\n};\n\nstruct fman_keygen {\n\tstruct keygen_scheme schemes[32];\n\tstruct fman_kg_regs *keygen_regs;\n};\n\nstruct fman_kg_pe_regs {\n\tu32 fmkg_pe_sp;\n\tu32 fmkg_pe_cpp;\n};\n\nstruct fman_kg_scheme_regs {\n\tu32 kgse_mode;\n\tu32 kgse_ekfc;\n\tu32 kgse_ekdv;\n\tu32 kgse_bmch;\n\tu32 kgse_bmcl;\n\tu32 kgse_fqb;\n\tu32 kgse_hc;\n\tu32 kgse_ppc;\n\tu32 kgse_gec[8];\n\tu32 kgse_spc;\n\tu32 kgse_dv0;\n\tu32 kgse_dv1;\n\tu32 kgse_ccbs;\n\tu32 kgse_mv;\n\tu32 kgse_om;\n\tu32 kgse_vsp;\n};\n\nstruct fman_kg_regs {\n\tu32 fmkg_gcr;\n\tu32 res004;\n\tu32 res008;\n\tu32 fmkg_eer;\n\tu32 fmkg_eeer;\n\tu32 res014;\n\tu32 res018;\n\tu32 fmkg_seer;\n\tu32 fmkg_seeer;\n\tu32 fmkg_gsr;\n\tu32 fmkg_tpc;\n\tu32 fmkg_serc;\n\tu32 res030[4];\n\tu32 fmkg_fdor;\n\tu32 fmkg_gdv0r;\n\tu32 fmkg_gdv1r;\n\tu32 res04c[6];\n\tu32 fmkg_feer;\n\tu32 res068[38];\n\tunion {\n\t\tu32 fmkg_indirect[63];\n\t\tstruct fman_kg_scheme_regs fmkg_sch;\n\t\tstruct fman_kg_pe_regs fmkg_pe;\n\t};\n\tu32 fmkg_ar;\n};\n\nstruct mac_device___3;\n\ntypedef void fman_mac_exception_cb(struct mac_device___3 *, enum fman_mac_exceptions);\n\nstruct fman_rev_info {\n\tu8 major;\n\tu8 minor;\n};\n\nstruct memac_regs;\n\nstruct memac_cfg;\n\nstruct fman_mac {\n\tstruct memac_regs *regs;\n\tu64 addr;\n\tstruct mac_device___3 *dev_id;\n\tfman_mac_exception_cb *exception_cb;\n\tfman_mac_exception_cb *event_cb;\n\tstruct eth_hash_t *multicast_addr_hash;\n\tstruct eth_hash_t *unicast_addr_hash;\n\tu8 mac_id;\n\tu32 exceptions;\n\tstruct memac_cfg *memac_drv_param;\n\tvoid *fm;\n\tstruct fman_rev_info fm_rev_info;\n\tstruct phy *serdes;\n\tstruct phylink_pcs *sgmii_pcs;\n\tstruct phylink_pcs *qsgmii_pcs;\n\tstruct phylink_pcs *xfi_pcs;\n\tbool allmulti_enabled;\n\tbool rgmii_no_half_duplex;\n};\n\ntypedef void fman_mac_exception_cb___2(struct mac_device *, enum fman_mac_exceptions);\n\nstruct phylink_pcs_ops;\n\nstruct phylink_pcs {\n\tlong unsigned int supported_interfaces[1];\n\tconst struct phylink_pcs_ops *ops;\n\tstruct phylink *phylink;\n\tbool poll;\n\tbool rxc_always_on;\n};\n\nstruct mdio_device;\n\nstruct fman_mac___2 {\n\tstruct dtsec_regs *regs;\n\tu64 addr;\n\tphy_interface_t phy_if;\n\tu16 max_speed;\n\tstruct mac_device *dev_id;\n\tfman_mac_exception_cb___2 *exception_cb;\n\tfman_mac_exception_cb___2 *event_cb;\n\tu8 num_of_ind_addr_in_regs;\n\tstruct eth_hash_t *multicast_addr_hash;\n\tstruct eth_hash_t *unicast_addr_hash;\n\tu8 mac_id;\n\tu32 exceptions;\n\tbool ptp_tsu_enabled;\n\tbool en_tsu_err_exception;\n\tstruct dtsec_cfg *dtsec_drv_param;\n\tvoid *fm;\n\tstruct fman_rev_info fm_rev_info;\n\tbool basex_if;\n\tstruct mdio_device *tbidev;\n\tstruct phylink_pcs pcs;\n};\n\ntypedef void fman_mac_exception_cb___3(struct mac_device___2 *, enum fman_mac_exceptions);\n\nstruct tgec_regs;\n\nstruct tgec_cfg;\n\nstruct fman_mac___3 {\n\tstruct tgec_regs *regs;\n\tu64 addr;\n\tu16 max_speed;\n\tstruct mac_device___2 *dev_id;\n\tfman_mac_exception_cb___3 *exception_cb;\n\tfman_mac_exception_cb___3 *event_cb;\n\tstruct eth_hash_t *multicast_addr_hash;\n\tstruct eth_hash_t *unicast_addr_hash;\n\tu8 mac_id;\n\tu32 exceptions;\n\tstruct tgec_cfg *cfg;\n\tvoid *fm;\n\tstruct fman_rev_info fm_rev_info;\n\tbool allmulti_enabled;\n};\n\nstruct fman_mac_params {\n\tu8 mac_id;\n\tvoid *fm;\n\tfman_mac_exception_cb___2 *event_cb;\n\tfman_mac_exception_cb___2 *exception_cb;\n};\n\nstruct fman_mac_params___2 {\n\tu8 mac_id;\n\tvoid *fm;\n\tfman_mac_exception_cb *event_cb;\n\tfman_mac_exception_cb *exception_cb;\n};\n\nstruct fman_mac_params___3 {\n\tu8 mac_id;\n\tvoid *fm;\n\tfman_mac_exception_cb___3 *event_cb;\n\tfman_mac_exception_cb___3 *exception_cb;\n};\n\nstruct fman_sp_buffer_offsets {\n\tu32 data_offset;\n\tu32 prs_result_offset;\n\tu32 time_stamp_offset;\n\tu32 hash_result_offset;\n};\n\nstruct fman_port_rsrc {\n\tu32 num;\n\tu32 extra;\n};\n\nstruct fman_port_rx_pools_params {\n\tu8 num_of_pools;\n\tu16 largest_buf_size;\n};\n\nstruct fman_port_dts_params {\n\tvoid *base_addr;\n\tenum fman_port_type type;\n\tu16 speed;\n\tu8 id;\n\tu32 qman_channel_id;\n\tstruct fman *fman;\n};\n\nunion fman_port_bmi_regs;\n\nstruct fman_port_qmi_regs;\n\nstruct fman_port_hwp_regs;\n\nstruct fman_port_cfg;\n\nstruct fman_port {\n\tvoid *fm;\n\tstruct device *dev;\n\tstruct fman_rev_info rev_info;\n\tu8 port_id;\n\tenum fman_port_type port_type;\n\tu16 port_speed;\n\tunion fman_port_bmi_regs *bmi_regs;\n\tstruct fman_port_qmi_regs *qmi_regs;\n\tstruct fman_port_hwp_regs *hwp_regs;\n\tstruct fman_sp_buffer_offsets buffer_offsets;\n\tu8 internal_buf_offset;\n\tstruct fman_ext_pools ext_buf_pools;\n\tu16 max_frame_length;\n\tstruct fman_port_rsrc open_dmas;\n\tstruct fman_port_rsrc tasks;\n\tstruct fman_port_rsrc fifo_bufs;\n\tstruct fman_port_rx_pools_params rx_pools_params;\n\tstruct fman_port_cfg *cfg;\n\tstruct fman_port_dts_params dts_params;\n\tu8 ext_pools_num;\n\tu32 max_port_fifo_size;\n\tu32 max_num_of_ext_pools;\n\tu32 max_num_of_sub_portals;\n\tu32 bm_max_num_of_pools;\n};\n\nstruct fman_port_rx_bmi_regs {\n\tu32 fmbm_rcfg;\n\tu32 fmbm_rst;\n\tu32 fmbm_rda;\n\tu32 fmbm_rfp;\n\tu32 fmbm_rfed;\n\tu32 fmbm_ricp;\n\tu32 fmbm_rim;\n\tu32 fmbm_rebm;\n\tu32 fmbm_rfne;\n\tu32 fmbm_rfca;\n\tu32 fmbm_rfpne;\n\tu32 fmbm_rpso;\n\tu32 fmbm_rpp;\n\tu32 fmbm_rccb;\n\tu32 fmbm_reth;\n\tu32 reserved003c[1];\n\tu32 fmbm_rprai[8];\n\tu32 fmbm_rfqid;\n\tu32 fmbm_refqid;\n\tu32 fmbm_rfsdm;\n\tu32 fmbm_rfsem;\n\tu32 fmbm_rfene;\n\tu32 reserved0074[2];\n\tu32 fmbm_rcmne;\n\tu32 reserved0080[32];\n\tu32 fmbm_ebmpi[8];\n\tu32 fmbm_acnt[8];\n\tu32 reserved0130[8];\n\tu32 fmbm_rcgm[8];\n\tu32 fmbm_mpd;\n\tu32 reserved0184[31];\n\tu32 fmbm_rstc;\n\tu32 fmbm_rfrc;\n\tu32 fmbm_rfbc;\n\tu32 fmbm_rlfc;\n\tu32 fmbm_rffc;\n\tu32 fmbm_rfdc;\n\tu32 fmbm_rfldec;\n\tu32 fmbm_rodc;\n\tu32 fmbm_rbdc;\n\tu32 fmbm_rpec;\n\tu32 reserved0224[22];\n\tu32 fmbm_rpc;\n\tu32 fmbm_rpcp;\n\tu32 fmbm_rccn;\n\tu32 fmbm_rtuc;\n\tu32 fmbm_rrquc;\n\tu32 fmbm_rduc;\n\tu32 fmbm_rfuc;\n\tu32 fmbm_rpac;\n\tu32 reserved02a0[24];\n\tu32 fmbm_rdcfg[3];\n\tu32 fmbm_rgpr;\n\tu32 reserved0310[58];\n};\n\nstruct fman_port_tx_bmi_regs {\n\tu32 fmbm_tcfg;\n\tu32 fmbm_tst;\n\tu32 fmbm_tda;\n\tu32 fmbm_tfp;\n\tu32 fmbm_tfed;\n\tu32 fmbm_ticp;\n\tu32 fmbm_tfdne;\n\tu32 fmbm_tfca;\n\tu32 fmbm_tcfqid;\n\tu32 fmbm_tefqid;\n\tu32 fmbm_tfene;\n\tu32 fmbm_trlmts;\n\tu32 fmbm_trlmt;\n\tu32 reserved0034[14];\n\tu32 fmbm_tccb;\n\tu32 fmbm_tfne;\n\tu32 fmbm_tpfcm[2];\n\tu32 fmbm_tcmne;\n\tu32 reserved0080[96];\n\tu32 fmbm_tstc;\n\tu32 fmbm_tfrc;\n\tu32 fmbm_tfdc;\n\tu32 fmbm_tfledc;\n\tu32 fmbm_tfufdc;\n\tu32 fmbm_tbdc;\n\tu32 reserved0218[26];\n\tu32 fmbm_tpc;\n\tu32 fmbm_tpcp;\n\tu32 fmbm_tccn;\n\tu32 fmbm_ttuc;\n\tu32 fmbm_ttcquc;\n\tu32 fmbm_tduc;\n\tu32 fmbm_tfuc;\n\tu32 reserved029c[16];\n\tu32 fmbm_tdcfg[3];\n\tu32 fmbm_tgpr;\n\tu32 reserved0310[58];\n};\n\nunion fman_port_bmi_regs {\n\tstruct fman_port_rx_bmi_regs rx;\n\tstruct fman_port_tx_bmi_regs tx;\n};\n\nstruct fman_port_bpools {\n\tu8 count;\n\tbool counters_enable;\n\tu8 grp_bp_depleted_num;\n\tstruct {\n\t\tu8 bpid;\n\t\tu16 size;\n\t\tbool is_backup;\n\t\tbool grp_bp_depleted;\n\t\tbool single_bp_depleted;\n\t} bpool[8];\n};\n\nstruct fman_sp_buf_margins {\n\tu16 start_margins;\n\tu16 end_margins;\n};\n\nstruct fman_sp_int_context_data_copy {\n\tu16 ext_buf_offset;\n\tu8 int_context_offset;\n\tu16 size;\n};\n\nstruct fman_port_cfg {\n\tu32 dflt_fqid;\n\tu32 err_fqid;\n\tu32 pcd_base_fqid;\n\tu32 pcd_fqs_count;\n\tu8 deq_sp;\n\tbool deq_high_priority;\n\tenum fman_port_deq_type deq_type;\n\tenum fman_port_deq_prefetch deq_prefetch_option;\n\tu16 deq_byte_cnt;\n\tu8 cheksum_last_bytes_ignore;\n\tu8 rx_cut_end_bytes;\n\tstruct fman_buf_pool_depletion buf_pool_depletion;\n\tstruct fman_ext_pools ext_buf_pools;\n\tu32 tx_fifo_min_level;\n\tu32 tx_fifo_low_comf_level;\n\tu32 rx_pri_elevation;\n\tu32 rx_fifo_thr;\n\tstruct fman_sp_buf_margins buf_margins;\n\tu32 int_buf_start_margin;\n\tstruct fman_sp_int_context_data_copy int_context;\n\tu32 discard_mask;\n\tu32 err_mask;\n\tstruct fman_buffer_prefix_content buffer_prefix_content;\n\tbool dont_release_buf;\n\tu8 rx_fd_bits;\n\tu32 tx_fifo_deq_pipeline_depth;\n\tbool errata_A006320;\n\tbool excessive_threshold_register;\n\tbool fmbm_tfne_has_features;\n\tenum fman_port_dma_swap dma_swap_data;\n\tenum fman_port_color color;\n};\n\nstruct fman_port_hwp_regs {\n\tstruct {\n\t\tu32 ssa;\n\t\tu32 lcv;\n\t} pmda[16];\n\tu32 reserved080[222];\n\tu32 fmpr_pcac;\n};\n\nstruct fman_port_init_params {\n\tu8 port_id;\n\tenum fman_port_type port_type;\n\tu16 port_speed;\n\tu16 liodn_offset;\n\tu8 num_of_tasks;\n\tu8 num_of_extra_tasks;\n\tu8 num_of_open_dmas;\n\tu8 num_of_extra_open_dmas;\n\tu32 size_of_fifo;\n\tu32 extra_size_of_fifo;\n\tu8 deq_pipeline_depth;\n\tu16 max_frame_length;\n\tu16 liodn_base;\n};\n\nstruct fman_port_non_rx_params {\n\tu32 err_fqid;\n\tu32 dflt_fqid;\n};\n\nstruct fman_port_rx_params {\n\tu32 err_fqid;\n\tu32 dflt_fqid;\n\tu32 pcd_base_fqid;\n\tu32 pcd_fqs_count;\n\tstruct fman_ext_pools ext_buf_pools;\n};\n\nunion fman_port_specific_params {\n\tstruct fman_port_rx_params rx_params;\n\tstruct fman_port_non_rx_params non_rx_params;\n};\n\nstruct fman_port_params {\n\tvoid *fm;\n\tunion fman_port_specific_params specific_params;\n};\n\nstruct fman_port_qmi_regs {\n\tu32 fmqm_pnc;\n\tu32 fmqm_pns;\n\tu32 fmqm_pnts;\n\tu32 reserved00c[4];\n\tu32 fmqm_pnen;\n\tu32 fmqm_pnetfc;\n\tu32 reserved024[2];\n\tu32 fmqm_pndn;\n\tu32 fmqm_pndc;\n\tu32 fmqm_pndtfc;\n\tu32 fmqm_pndfdc;\n\tu32 fmqm_pndcc;\n};\n\nstruct fman_prs_result {\n\tu8 lpid;\n\tu8 shimr;\n\t__be16 l2r;\n\t__be16 l3r;\n\tu8 l4r;\n\tu8 cplan;\n\t__be16 nxthdr;\n\t__be16 cksum;\n\t__be16 flags_frag_off;\n\tu8 route_type;\n\tu8 rhp_ip_valid;\n\tu8 shim_off[2];\n\tu8 ip_pid_off;\n\tu8 eth_off;\n\tu8 llc_snap_off;\n\tu8 vlan_off[2];\n\tu8 etype_off;\n\tu8 pppoe_off;\n\tu8 mpls_off[2];\n\tu8 ip_off[2];\n\tu8 gre_off;\n\tu8 l4_off;\n\tu8 nxthdr_off;\n};\n\nstruct fman_qmi_regs {\n\tu32 fmqm_gc;\n\tu32 res0004;\n\tu32 fmqm_eie;\n\tu32 fmqm_eien;\n\tu32 fmqm_eif;\n\tu32 fmqm_ie;\n\tu32 fmqm_ien;\n\tu32 fmqm_if;\n\tu32 fmqm_gs;\n\tu32 fmqm_ts;\n\tu32 fmqm_etfc;\n\tu32 fmqm_dtfc;\n\tu32 fmqm_dc0;\n\tu32 fmqm_dc1;\n\tu32 fmqm_dc2;\n\tu32 fmqm_dc3;\n\tu32 fmqm_dfdc;\n\tu32 fmqm_dfcc;\n\tu32 fmqm_dffc;\n\tu32 fmqm_dcc;\n\tu32 res0050[7];\n\tu32 fmqm_tapc;\n\tu32 fmqm_dmcvc;\n\tu32 fmqm_difdcc;\n\tu32 fmqm_da1v;\n\tu32 res007c;\n\tu32 fmqm_dtc;\n\tu32 fmqm_efddd;\n\tu32 res0088[2];\n\tstruct {\n\t\tu32 fmqm_dtcfg1;\n\t\tu32 fmqm_dtval1;\n\t\tu32 fmqm_dtm1;\n\t\tu32 fmqm_dtc1;\n\t\tu32 fmqm_dtcfg2;\n\t\tu32 fmqm_dtval2;\n\t\tu32 fmqm_dtm2;\n\t\tu32 res001c;\n\t} dbg_traps[3];\n\tu8 res00f0[784];\n};\n\nstruct fman_state_struct {\n\tu8 fm_id;\n\tu16 fm_clk_freq;\n\tstruct fman_rev_info rev_info;\n\tbool enabled_time_stamp;\n\tu8 count1_micro_bit;\n\tu8 total_num_of_tasks;\n\tu8 accumulated_num_of_tasks;\n\tu32 accumulated_fifo_size;\n\tu8 accumulated_num_of_open_dmas;\n\tu8 accumulated_num_of_deq_tnums;\n\tu32 exceptions;\n\tu32 extra_fifo_pool_size;\n\tu8 extra_tasks_pool_size;\n\tu8 extra_open_dmas_pool_size;\n\tu16 port_mfl[10];\n\tu16 mac_mfl[10];\n\tu32 fm_iram_size;\n\tu32 dma_thresh_max_commq;\n\tu32 dma_thresh_max_buf;\n\tu32 max_num_of_open_dmas;\n\tu32 qmi_max_num_of_tnums;\n\tu32 qmi_def_tnums_thresh;\n\tu32 bmi_max_num_of_tasks;\n\tu32 bmi_max_fifo_size;\n\tu32 fm_port_num_of_cg;\n\tu32 num_of_rx_ports;\n\tu32 total_fifo_size;\n\tu32 qman_channel_base;\n\tu32 num_of_qman_channels;\n\tstruct resource *res;\n};\n\nstruct ufshcd_sg_entry {\n\t__le64 addr;\n\t__le32 reserved;\n\t__le32 size;\n};\n\nstruct fmp_sg_entry {\n\tstruct ufshcd_sg_entry base;\n\t__be64 file_iv[2];\n\t__be64 file_enckey[4];\n\t__be64 file_twkey[4];\n\t__be64 disk_iv[2];\n\t__be64 reserved[2];\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t\tlong unsigned int memcg_data;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tatomic_t _entire_mapcount;\n\t\t\t\t\tatomic_t _pincount;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t\tunsigned int _nr_pages;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_or_pfn {\n\tunion {\n\t\tstruct folio *folio;\n\t\tlong unsigned int pfn;\n\t};\n\tbool is_folio;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct font_data {\n\tunsigned int extra[4];\n\tconst unsigned char data[0];\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tconst void *data;\n\tint pref;\n};\n\nstruct memory_block;\n\ntypedef int (*walk_memory_blocks_func_t)(struct memory_block *, void *);\n\nstruct for_each_memory_block_cb_data {\n\twalk_memory_blocks_func_t func;\n\tvoid *arg;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fpga_compat_id {\n\tu64 id_h;\n\tu64 id_l;\n};\n\nstruct fpga_image_info {\n\tu32 flags;\n\tu32 enable_timeout_us;\n\tu32 disable_timeout_us;\n\tu32 config_complete_timeout_us;\n\tchar *firmware_name;\n\tstruct sg_table *sgt;\n\tconst char *buf;\n\tsize_t count;\n\tsize_t header_size;\n\tsize_t data_size;\n\tint region_id;\n\tstruct device *dev;\n\tstruct device_node *overlay;\n};\n\nstruct fpga_manager_ops;\n\nstruct fpga_manager {\n\tconst char *name;\n\tstruct device dev;\n\tstruct mutex ref_mutex;\n\tenum fpga_mgr_states state;\n\tstruct fpga_compat_id *compat_id;\n\tconst struct fpga_manager_ops *mops;\n\tstruct module *mops_owner;\n\tvoid *priv;\n};\n\nstruct fpga_manager_info {\n\tconst char *name;\n\tstruct fpga_compat_id *compat_id;\n\tconst struct fpga_manager_ops *mops;\n\tvoid *priv;\n};\n\nstruct fpga_manager_ops {\n\tsize_t initial_header_size;\n\tbool skip_header;\n\tenum fpga_mgr_states (*state)(struct fpga_manager *);\n\tu64 (*status)(struct fpga_manager *);\n\tint (*parse_header)(struct fpga_manager *, struct fpga_image_info *, const char *, size_t);\n\tint (*write_init)(struct fpga_manager *, struct fpga_image_info *, const char *, size_t);\n\tint (*write)(struct fpga_manager *, const char *, size_t);\n\tint (*write_sg)(struct fpga_manager *, struct sg_table *);\n\tint (*write_complete)(struct fpga_manager *, struct fpga_image_info *);\n\tvoid (*fpga_remove)(struct fpga_manager *);\n\tconst struct attribute_group **groups;\n};\n\nstruct fpga_mgr_devres {\n\tstruct fpga_manager *mgr;\n};\n\nstruct fpmr_context {\n\tstruct _aarch64_ctx head;\n\t__u64 fpmr;\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\nstruct fpsimd_context {\n\tstruct _aarch64_ctx head;\n\t__u32 fpsr;\n\t__u32 fpcr;\n\t__int128 unsigned vregs[32];\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhashtable rhashtable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct frac_entry {\n\tint num;\n\tint den;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct fragment {\n\tstruct device_node *overlay;\n\tstruct device_node *target;\n};\n\nstruct frags_info {\n\t__le32 addr;\n\t__le32 size;\n};\n\nstruct frame_tail {\n\tstruct frame_tail *fp;\n\tlong unsigned int lr;\n};\n\nstruct free_area {\n\tstruct list_head free_list[6];\n\tlong unsigned int nr_free;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t\tshort unsigned int stride;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tfreelist_full_t freelist_counters;\n\t};\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n};\n\nstruct freq_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpufreq_policy *, char *);\n\tssize_t (*store)(struct cpufreq_policy *, const char *, size_t);\n};\n\nstruct freq_conf {\n\tu8 src;\n\tu8 pre_div;\n\tu16 m;\n\tu16 n;\n};\n\nstruct freq_multi_tbl {\n\tlong unsigned int freq;\n\tsize_t num_confs;\n\tconst struct freq_conf *confs;\n};\n\nstruct freq_tbl {\n\tlong unsigned int freq;\n\tu8 src;\n\tu8 pre_div;\n\tu16 m;\n\tu16 n;\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_disk_quota {\n\t__s8 d_version;\n\t__s8 d_flags;\n\t__u16 d_fieldmask;\n\t__u32 d_id;\n\t__u64 d_blk_hardlimit;\n\t__u64 d_blk_softlimit;\n\t__u64 d_ino_hardlimit;\n\t__u64 d_ino_softlimit;\n\t__u64 d_bcount;\n\t__u64 d_icount;\n\t__s32 d_itimer;\n\t__s32 d_btimer;\n\t__u16 d_iwarns;\n\t__u16 d_bwarns;\n\t__s8 d_itimer_hi;\n\t__s8 d_btimer_hi;\n\t__s8 d_rtbtimer_hi;\n\t__s8 d_padding2;\n\t__u64 d_rtb_hardlimit;\n\t__u64 d_rtb_softlimit;\n\t__u64 d_rtbcount;\n\t__s32 d_rtbtimer;\n\t__u16 d_rtbwarns;\n\t__s16 d_padding3;\n\tchar d_padding4[8];\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_qfilestat {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n};\n\ntypedef struct fs_qfilestat fs_qfilestat_t;\n\nstruct fs_qfilestatv {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n\t__u32 qfs_pad;\n};\n\nstruct fs_quota_stat {\n\t__s8 qs_version;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tfs_qfilestat_t qs_uquota;\n\tfs_qfilestat_t qs_gquota;\n\t__u32 qs_incoredqs;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n};\n\nstruct fs_quota_statv {\n\t__s8 qs_version;\n\t__u8 qs_pad1;\n\t__u16 qs_flags;\n\t__u32 qs_incoredqs;\n\tstruct fs_qfilestatv qs_uquota;\n\tstruct fs_qfilestatv qs_gquota;\n\tstruct fs_qfilestatv qs_pquota;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n\t__u16 qs_rtbwarnlimit;\n\t__u16 qs_pad3;\n\t__u32 qs_pad4;\n\t__u64 qs_pad2[7];\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fscache_cache_ops;\n\nstruct fscache_cache {\n\tconst struct fscache_cache_ops *ops;\n\tstruct list_head cache_link;\n\tvoid *cache_priv;\n\trefcount_t ref;\n\tatomic_t n_volumes;\n\tatomic_t n_accesses;\n\tatomic_t object_count;\n\tunsigned int debug_id;\n\tenum fscache_cache_state state;\n\tchar *name;\n};\n\nstruct fscache_volume;\n\nstruct fscache_cookie;\n\nstruct netfs_cache_resources;\n\nstruct fscache_cache_ops {\n\tconst char *name;\n\tvoid (*acquire_volume)(struct fscache_volume *);\n\tvoid (*free_volume)(struct fscache_volume *);\n\tbool (*lookup_cookie)(struct fscache_cookie *);\n\tvoid (*withdraw_cookie)(struct fscache_cookie *);\n\tvoid (*resize_cookie)(struct netfs_cache_resources *, loff_t);\n\tbool (*invalidate_cookie)(struct fscache_cookie *);\n\tbool (*begin_operation)(struct netfs_cache_resources *, enum fscache_want_state);\n\tvoid (*prepare_to_write)(struct fscache_cookie *);\n};\n\nstruct fscache_cookie {\n\trefcount_t ref;\n\tatomic_t n_active;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n\tspinlock_t lock;\n\tstruct fscache_volume *volume;\n\tvoid *cache_priv;\n\tstruct hlist_bl_node hash_link;\n\tstruct list_head proc_link;\n\tstruct list_head commit_link;\n\tstruct work_struct work;\n\tloff_t object_size;\n\tlong unsigned int unused_at;\n\tlong unsigned int flags;\n\tenum fscache_cookie_state state;\n\tu8 advice;\n\tu8 key_len;\n\tu8 aux_len;\n\tu32 key_hash;\n\tunion {\n\t\tvoid *key;\n\t\tu8 inline_key[16];\n\t};\n\tunion {\n\t\tvoid *aux;\n\t\tu8 inline_aux[8];\n\t};\n};\n\nstruct fscache_volume {\n\trefcount_t ref;\n\tatomic_t n_cookies;\n\tatomic_t n_accesses;\n\tunsigned int debug_id;\n\tunsigned int key_hash;\n\tu8 *key;\n\tstruct list_head proc_link;\n\tstruct hlist_bl_node hash_link;\n\tstruct work_struct work;\n\tstruct fscache_cache *cache;\n\tvoid *cache_priv;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu8 coherency_len;\n\tu8 coherency[0];\n};\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_nokey_name;\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsl8250_data {\n\tint line;\n};\n\nstruct spi_message;\n\nstruct fsl_dspi_devtype_data;\n\nstruct fsl_dspi_dma;\n\nstruct fsl_dspi {\n\tstruct spi_controller *ctlr;\n\tstruct platform_device *pdev;\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_pushr;\n\tint irq;\n\tstruct clk *clk;\n\tstruct spi_transfer *cur_transfer;\n\tstruct spi_message *cur_msg;\n\tstruct chip_data___2 *cur_chip;\n\tsize_t progress;\n\tsize_t len;\n\tconst void *tx;\n\tvoid *rx;\n\tu16 tx_cmd;\n\tbool mtf_enabled;\n\tconst struct fsl_dspi_devtype_data *devtype_data;\n\tstruct completion xfer_done;\n\tstruct fsl_dspi_dma *dma;\n\tint oper_word_size;\n\tint oper_bits_per_word;\n\tint words_in_flight;\n\tint pushr_cmd;\n\tint pushr_tx;\n\tvoid (*host_to_dev)(struct fsl_dspi *, u32 *);\n\tvoid (*dev_to_host)(struct fsl_dspi *, u32);\n};\n\nstruct fsl_dspi_devtype_data {\n\tenum dspi_trans_mode trans_mode;\n\tu8 max_clock_factor;\n\tint fifo_size;\n\tconst struct regmap_config *regmap;\n};\n\nstruct fsl_dspi_dma {\n\tu32 *tx_dma_buf;\n\tstruct dma_chan *chan_tx;\n\tdma_addr_t tx_dma_phys;\n\tstruct completion cmd_tx_complete;\n\tstruct dma_async_tx_descriptor *tx_desc;\n\tu32 *rx_dma_buf;\n\tstruct dma_chan *chan_rx;\n\tdma_addr_t rx_dma_phys;\n\tstruct completion cmd_rx_complete;\n\tstruct dma_async_tx_descriptor *rx_desc;\n\tsize_t bufsize;\n};\n\nstruct fsl_dspi_platform_data {\n\tu32 cs_num;\n\tu32 bus_num;\n\tu32 sck_cs_delay;\n\tu32 cs_sck_delay;\n};\n\nstruct fsl_edma_hw_tcd {\n\t__le32 saddr;\n\t__le16 soff;\n\t__le16 attr;\n\t__le32 nbytes;\n\t__le32 slast;\n\t__le32 daddr;\n\t__le16 doff;\n\t__le16 citer;\n\t__le32 dlast_sga;\n\t__le16 csr;\n\t__le16 biter;\n};\n\nstruct fsl_edma_hw_tcd64 {\n\t__le64 saddr;\n\t__le16 soff;\n\t__le16 attr;\n\t__le32 nbytes;\n\t__le64 slast;\n\t__le64 daddr;\n\t__le64 dlast_sga;\n\t__le16 doff;\n\t__le16 citer;\n\t__le16 csr;\n\t__le16 biter;\n};\n\nstruct fsl_edma3_ch_reg {\n\t__le32 ch_csr;\n\t__le32 ch_es;\n\t__le32 ch_int;\n\t__le32 ch_sbr;\n\t__le32 ch_pri;\n\t__le32 ch_mux;\n\t__le32 ch_mattr;\n\t__le32 ch_reserved;\n\tunion {\n\t\tstruct fsl_edma_hw_tcd tcd;\n\t\tstruct fsl_edma_hw_tcd64 tcd64;\n\t};\n};\n\nstruct fsl_edma_engine;\n\nstruct fsl_edma_desc;\n\nstruct fsl_edma_chan {\n\tstruct virt_dma_chan vchan;\n\tenum dma_status status;\n\tenum fsl_edma_pm_state pm_state;\n\tstruct fsl_edma_engine *edma;\n\tstruct fsl_edma_desc *edesc;\n\tstruct dma_slave_config cfg;\n\tu32 attr;\n\tbool is_sw;\n\tstruct dma_pool *tcd_pool;\n\tdma_addr_t dma_dev_addr;\n\tu32 dma_dev_size;\n\tenum dma_data_direction dma_dir;\n\tchar chan_name[32];\n\tchar errirq_name[36];\n\tvoid *tcd;\n\tvoid *mux_addr;\n\tu32 real_count;\n\tstruct work_struct issue_worker;\n\tstruct platform_device *pdev;\n\tstruct device *pd_dev;\n\tstruct device_link *pd_dev_link;\n\tu32 srcid;\n\tstruct clk *clk;\n\tint priority;\n\tint hw_chanid;\n\tint txirq;\n\tint errirq;\n\tirqreturn_t (*irq_handler)(int, void *);\n\tirqreturn_t (*errirq_handler)(int, void *);\n\tbool is_rxchan;\n\tbool is_remote;\n\tbool is_multi_fifo;\n};\n\nstruct fsl_edma_sw_tcd {\n\tdma_addr_t ptcd;\n\tvoid *vtcd;\n};\n\nstruct fsl_edma_desc {\n\tstruct virt_dma_desc vdesc;\n\tstruct fsl_edma_chan *echan;\n\tbool iscyclic;\n\tenum dma_transfer_direction dirn;\n\tunsigned int n_tcds;\n\tstruct fsl_edma_sw_tcd tcd[0];\n};\n\nstruct fsl_edma_drvdata {\n\tu32 dmamuxs;\n\tu32 chreg_off;\n\tu32 chreg_space_sz;\n\tu32 flags;\n\tu32 mux_off;\n\tu32 mux_skip;\n\tint (*setup_irq)(struct platform_device *, struct fsl_edma_engine *);\n};\n\nstruct fsl_edma_engine {\n\tstruct dma_device dma_dev;\n\tvoid *membase;\n\tvoid *muxbase[2];\n\tstruct clk *muxclk[2];\n\tstruct clk *dmaclk;\n\tstruct mutex fsl_edma_mutex;\n\tconst struct fsl_edma_drvdata *drvdata;\n\tu32 n_chans;\n\tint txirq;\n\tint txirq_16_31;\n\tint errirq;\n\tbool big_endian;\n\tstruct edma_regs regs;\n\tu64 chan_masked;\n\tstruct fsl_edma_chan chans[0];\n};\n\nstruct fsl_gpio_soc_data {\n\tbool have_paddr;\n\tbool have_dual_base;\n};\n\nstruct fsl_ifc_global;\n\nstruct fsl_ifc_runtime;\n\nstruct fsl_ifc_ctrl {\n\tstruct device *dev;\n\tstruct fsl_ifc_global *gregs;\n\tstruct fsl_ifc_runtime *rregs;\n\tint irq;\n\tint nand_irq;\n\tspinlock_t lock;\n\tvoid *nand;\n\tint version;\n\tint banks;\n\tu32 nand_stat;\n\twait_queue_head_t nand_wait;\n\tbool little_endian;\n};\n\nstruct fsl_ifc_global {\n\t__be32 ifc_rev;\n\tu32 res1[2];\n\tstruct {\n\t\t__be32 cspr_ext;\n\t\t__be32 cspr;\n\t\tu32 res2;\n\t} cspr_cs[8];\n\tu32 res3[13];\n\tstruct {\n\t\t__be32 amask;\n\t\tu32 res4[2];\n\t} amask_cs[8];\n\tu32 res5[12];\n\tstruct {\n\t\t__be32 csor;\n\t\t__be32 csor_ext;\n\t\tu32 res6;\n\t} csor_cs[8];\n\tu32 res7[12];\n\tstruct {\n\t\t__be32 ftim[4];\n\t\tu32 res8[8];\n\t} ftim_cs[8];\n\tu32 res9[48];\n\t__be32 rb_stat;\n\t__be32 rb_map;\n\t__be32 wb_map;\n\t__be32 ifc_gcr;\n\tu32 res10[2];\n\t__be32 cm_evter_stat;\n\tu32 res11[2];\n\t__be32 cm_evter_en;\n\tu32 res12[2];\n\t__be32 cm_evter_intr_en;\n\tu32 res13[2];\n\t__be32 cm_erattr0;\n\t__be32 cm_erattr1;\n\tu32 res14[2];\n\t__be32 ifc_ccr;\n\t__be32 ifc_csr;\n\t__be32 ddr_ccr_low;\n};\n\nstruct fsl_ifc_gpcm {\n\t__be32 gpcm_evter_stat;\n\tu32 res1[2];\n\t__be32 gpcm_evter_en;\n\tu32 res2[2];\n\t__be32 gpcm_evter_intr_en;\n\tu32 res3[2];\n\t__be32 gpcm_erattr0;\n\t__be32 gpcm_erattr1;\n\t__be32 gpcm_erattr2;\n\t__be32 gpcm_stat;\n};\n\nstruct fsl_ifc_mtd {\n\tstruct nand_chip chip;\n\tstruct fsl_ifc_ctrl *ctrl;\n\tstruct device *dev;\n\tint bank;\n\tunsigned int bufnum_mask;\n\tu8 *vbase;\n};\n\nstruct fsl_ifc_nand {\n\t__be32 ncfgr;\n\tu32 res1[4];\n\t__be32 nand_fcr0;\n\t__be32 nand_fcr1;\n\tu32 res2[8];\n\t__be32 row0;\n\tu32 res3;\n\t__be32 col0;\n\tu32 res4;\n\t__be32 row1;\n\tu32 res5;\n\t__be32 col1;\n\tu32 res6;\n\t__be32 row2;\n\tu32 res7;\n\t__be32 col2;\n\tu32 res8;\n\t__be32 row3;\n\tu32 res9;\n\t__be32 col3;\n\tu32 res10[36];\n\t__be32 nand_fbcr;\n\tu32 res11;\n\t__be32 nand_fir0;\n\t__be32 nand_fir1;\n\t__be32 nand_fir2;\n\tu32 res12[16];\n\t__be32 nand_csel;\n\tu32 res13;\n\t__be32 nandseq_strt;\n\tu32 res14;\n\t__be32 nand_evter_stat;\n\tu32 res15;\n\t__be32 pgrdcmpl_evt_stat;\n\tu32 res16[2];\n\t__be32 nand_evter_en;\n\tu32 res17[2];\n\t__be32 nand_evter_intr_en;\n\t__be32 nand_vol_addr_stat;\n\tu32 res18;\n\t__be32 nand_erattr0;\n\t__be32 nand_erattr1;\n\tu32 res19[16];\n\t__be32 nand_fsr;\n\tu32 res20;\n\t__be32 nand_eccstat[8];\n\tu32 res21[28];\n\t__be32 nanndcr;\n\tu32 res22[2];\n\t__be32 nand_autoboot_trgr;\n\tu32 res23;\n\t__be32 nand_mdr;\n\tu32 res24[28];\n\t__be32 nand_dll_lowcfg0;\n\t__be32 nand_dll_lowcfg1;\n\tu32 res25;\n\t__be32 nand_dll_lowstat;\n\tu32 res26[60];\n};\n\nstruct fsl_ifc_nand_ctrl {\n\tstruct nand_controller controller;\n\tstruct fsl_ifc_mtd *chips[8];\n\tvoid *addr;\n\tunsigned int page;\n\tunsigned int read_bytes;\n\tunsigned int column;\n\tunsigned int index;\n\tunsigned int oob;\n\tunsigned int eccread;\n\tunsigned int counter;\n\tunsigned int max_bitflips;\n};\n\nstruct fsl_ifc_nor {\n\t__be32 nor_evter_stat;\n\tu32 res1[2];\n\t__be32 nor_evter_en;\n\tu32 res2[2];\n\t__be32 nor_evter_intr_en;\n\tu32 res3[2];\n\t__be32 nor_erattr0;\n\t__be32 nor_erattr1;\n\t__be32 nor_erattr2;\n\tu32 res4[4];\n\t__be32 norcr;\n\tu32 res5[239];\n};\n\nstruct fsl_ifc_runtime {\n\tstruct fsl_ifc_nand ifc_nand;\n\tstruct fsl_ifc_nor ifc_nor;\n\tstruct fsl_ifc_gpcm ifc_gpcm;\n};\n\nstruct lpspi_config {\n\tu8 bpw;\n\tu8 chip_select;\n\tu8 prescale;\n\tu16 mode;\n\tu32 speed_hz;\n\tu32 effective_speed_hz;\n};\n\nstruct fsl_lpspi_devtype_data;\n\nstruct fsl_lpspi_data {\n\tstruct device *dev;\n\tvoid *base;\n\tlong unsigned int base_phys;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_per;\n\tbool is_target;\n\tbool is_only_cs1;\n\tbool is_first_byte;\n\tvoid *rx_buf;\n\tconst void *tx_buf;\n\tvoid (*tx)(struct fsl_lpspi_data *);\n\tvoid (*rx)(struct fsl_lpspi_data *);\n\tu32 remain;\n\tu8 watermark;\n\tu8 txfifosize;\n\tu8 rxfifosize;\n\tstruct lpspi_config config;\n\tstruct completion xfer_done;\n\tbool target_aborted;\n\tbool usedma;\n\tstruct completion dma_rx_completion;\n\tstruct completion dma_tx_completion;\n\tconst struct fsl_lpspi_devtype_data *devtype_data;\n};\n\nstruct fsl_lpspi_devtype_data {\n\tu8 prescale_max: 3;\n\tbool query_hw_for_num_cs: 1;\n};\n\nstruct fsl_mc_addr_translation_range;\n\nstruct fsl_mc {\n\tstruct fsl_mc_device *root_mc_bus_dev;\n\tu8 num_translation_ranges;\n\tstruct fsl_mc_addr_translation_range *translation_ranges;\n\tvoid *fsl_mc_regs;\n};\n\nstruct fsl_mc_addr_translation_range {\n\tenum dprc_region_type mc_region_type;\n\tu64 start_mc_offset;\n\tu64 end_mc_offset;\n\tphys_addr_t start_phys_addr;\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu32 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n\tconst char *driver_override;\n};\n\nstruct fsl_mc_bus;\n\nstruct fsl_mc_resource_pool {\n\tenum fsl_mc_pool_type type;\n\tint max_count;\n\tint free_count;\n\tstruct mutex mutex;\n\tstruct list_head free_list;\n\tstruct fsl_mc_bus *mc_bus;\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct fsl_mc_uapi {\n\tstruct miscdevice misc;\n\tstruct device *device;\n\tstruct mutex mutex;\n\tu32 local_instance_in_use;\n\tstruct fsl_mc_io *static_mc_io;\n};\n\nstruct fsl_mc_bus {\n\tstruct fsl_mc_device mc_dev;\n\tstruct fsl_mc_resource_pool resource_pools[4];\n\tstruct fsl_mc_device_irq *irq_resources;\n\tstruct mutex scan_mutex;\n\tstruct dprc_attributes dprc_attr;\n\tstruct fsl_mc_uapi uapi_misc;\n\tint irq_enabled;\n};\n\nstruct fsl_mc_child_objs {\n\tint child_count;\n\tstruct fsl_mc_obj_desc *child_array;\n};\n\nstruct fsl_mc_command {\n\t__le64 header;\n\t__le64 params[7];\n};\n\nstruct fsl_mc_device_id {\n\t__u16 vendor;\n\tconst char obj_type[16];\n};\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tunsigned int virq;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_driver {\n\tstruct device_driver driver;\n\tconst struct fsl_mc_device_id *match_id_table;\n\tint (*probe)(struct fsl_mc_device *);\n\tvoid (*remove)(struct fsl_mc_device *);\n\tvoid (*shutdown)(struct fsl_mc_device *);\n\tint (*suspend)(struct fsl_mc_device *, pm_message_t);\n\tint (*resume)(struct fsl_mc_device *);\n\tbool driver_managed_dma;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\traw_spinlock_t spinlock;\n\t};\n};\n\nstruct fsl_mc_obj_cmd_open {\n\t__le32 obj_id;\n};\n\nstruct fsl_mc_version {\n\tu32 major;\n\tu32 minor;\n\tu32 revision;\n};\n\nstruct fsl_qspi_devtype_data;\n\nstruct fsl_qspi {\n\tvoid *iobase;\n\tvoid *ahb_addr;\n\tconst struct fsl_qspi_devtype_data *devtype_data;\n\tstruct mutex lock;\n\tstruct completion c;\n\tstruct reset_control *resets;\n\tstruct clk *clk;\n\tstruct clk *clk_en;\n\tstruct pm_qos_request pm_qos_req;\n\tstruct device *dev;\n\tint selected;\n\tu32 memmap_phy;\n};\n\nstruct fsl_qspi_devtype_data {\n\tunsigned int rxfifo;\n\tunsigned int txfifo;\n\tint invalid_mstrid;\n\tunsigned int ahb_buf_size;\n\tunsigned int sfa_size;\n\tunsigned int quirks;\n\tbool little_endian;\n};\n\nstruct fsl_sai_clk {\n\tstruct clk_divider div;\n\tstruct clk_gate gate;\n\tspinlock_t lock;\n};\n\nstruct fsl_soc_data {\n\tconst char *sfp_compat;\n\tu32 uid_offset;\n};\n\nstruct fsl_soc_die_attr {\n\tchar *die;\n\tu32 svr;\n\tu32 mask;\n};\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\ntypedef struct fsnotify_group *class_fsnotify_group_t;\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t\tstruct fanotify_group_private_data fanotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct fsuuid {\n\t__u32 fsu_len;\n\t__u32 fsu_flags;\n\t__u8 fsu_uuid[0];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\ntypedef bool filter_t(u64);\n\nstruct ftr_set_desc {\n\tchar name[20];\n\tunion {\n\t\tstruct arm64_ftr_override *override;\n\t\tprel64_t override_prel;\n\t};\n\tstruct {\n\t\tchar name[10];\n\t\tu8 shift;\n\t\tu8 width;\n\t\tunion {\n\t\t\tfilter_t *filter;\n\t\t\tprel64_t filter_prel;\n\t\t};\n\t} fields[0];\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8156];\n};\n\nstruct tracer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tchar *fmt;\n\tunsigned int fmt_size;\n\tatomic_t wait_index;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool closed;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int spare_size;\n\tunsigned int read;\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int args[0];\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tunsigned int is_signed: 1;\n\tunsigned int needs_test: 1;\n\tint len;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct func_repeats_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu16 count;\n\tu16 top_delta_ts;\n\tu32 bottom_delta_ts;\n};\n\nstruct pinfunction;\n\nstruct function_desc {\n\tconst struct pinfunction *func;\n\tvoid *data;\n};\n\nstruct fuse_corner {\n\tint min_uV;\n\tint max_uV;\n\tint uV;\n\tint quot;\n\tint step_quot;\n\tconst struct reg_sequence *accs;\n\tint num_accs;\n\tlong unsigned int max_freq;\n\tu8 ring_osc_idx;\n};\n\nstruct fuse_corner_data {\n\tint ref_uV;\n\tint max_uV;\n\tint min_uV;\n\tint max_volt_scale;\n\tint max_quot_scale;\n\tint quot_offset;\n\tint quot_scale;\n\tint quot_adjust;\n\tint quot_offset_scale;\n\tint quot_offset_adjust;\n};\n\nstruct rdpq_alloc_detail {\n\tstruct dma_pool *dma_pool_ptr;\n\tdma_addr_t pool_entry_phys;\n\tunion MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt;\n};\n\nstruct megasas_cmd;\n\nstruct fusion_context {\n\tstruct megasas_cmd_fusion **cmd_list;\n\tdma_addr_t req_frames_desc_phys;\n\tu8 *req_frames_desc;\n\tstruct dma_pool *io_request_frames_pool;\n\tdma_addr_t io_request_frames_phys;\n\tu8 *io_request_frames;\n\tstruct dma_pool *sg_dma_pool;\n\tstruct dma_pool *sense_dma_pool;\n\tu8 *sense;\n\tdma_addr_t sense_phys_addr;\n\tatomic_t busy_mq_poll[128];\n\tdma_addr_t reply_frames_desc_phys[128];\n\tunion MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[128];\n\tstruct rdpq_alloc_detail rdpq_tracker[8];\n\tstruct dma_pool *reply_frames_desc_pool;\n\tstruct dma_pool *reply_frames_desc_pool_align;\n\tu16 last_reply_idx[128];\n\tu32 reply_q_depth;\n\tu32 request_alloc_sz;\n\tu32 reply_alloc_sz;\n\tu32 io_frames_alloc_sz;\n\tstruct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;\n\tdma_addr_t rdpq_phys;\n\tu16 max_sge_in_main_msg;\n\tu16 max_sge_in_chain;\n\tu8 chain_offset_io_request;\n\tu8 chain_offset_mfi_pthru;\n\tstruct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];\n\tdma_addr_t ld_map_phys[2];\n\tstruct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];\n\tu32 max_map_sz;\n\tu32 current_map_sz;\n\tu32 old_map_sz;\n\tu32 new_map_sz;\n\tu32 drv_map_sz;\n\tu32 drv_map_pages;\n\tstruct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[2];\n\tdma_addr_t pd_seq_phys[2];\n\tu8 fast_path_io;\n\tstruct LD_LOAD_BALANCE_INFO *load_balance_info;\n\tu32 load_balance_info_pages;\n\tLD_SPAN_INFO *log_to_span;\n\tu32 log_to_span_pages;\n\tstruct LD_STREAM_DETECT **stream_detect_by_ld;\n\tdma_addr_t ioc_init_request_phys;\n\tstruct MPI2_IOC_INIT_REQUEST *ioc_init_request;\n\tstruct megasas_cmd *ioc_init_cmd;\n\tbool pcie_bw_limitation;\n\tbool r56_div_offload;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tsize_t offset;\n\tu32 opt_flags;\n\tbool is_paged_buf;\n\tstruct page **pages;\n\tint nr_pages;\n\tint page_array_size;\n\tbool need_uevent;\n\tstruct list_head pending_list;\n\tconst char *fw_name;\n};\n\nstruct fw_rsc_carveout {\n\tu32 da;\n\tu32 pa;\n\tu32 len;\n\tu32 flags;\n\tu32 reserved;\n\tu8 name[32];\n};\n\nstruct fw_rsc_devmem {\n\tu32 da;\n\tu32 pa;\n\tu32 len;\n\tu32 flags;\n\tu32 reserved;\n\tu8 name[32];\n};\n\nstruct fw_rsc_hdr {\n\tu32 type;\n\tu8 data[0];\n};\n\nstruct fw_rsc_trace {\n\tu32 da;\n\tu32 len;\n\tu32 reserved;\n\tu8 name[32];\n};\n\nstruct fw_rsc_vdev_vring {\n\tu32 da;\n\tu32 align;\n\tu32 num;\n\tu32 notifyid;\n\tu32 pa;\n};\n\nstruct fw_rsc_vdev {\n\tu32 id;\n\tu32 notifyid;\n\tu32 dfeatures;\n\tu32 gfeatures;\n\tu32 config_len;\n\tu8 status;\n\tu8 num_of_vrings;\n\tu8 reserved[2];\n\tstruct fw_rsc_vdev_vring vring[0];\n};\n\nstruct fw_sysfs {\n\tbool nowait;\n\tstruct device dev;\n\tstruct fw_priv *fw_priv;\n\tstruct firmware *fw;\n\tvoid *fw_upload_priv;\n};\n\nunion fw_table_header {\n\tstruct acpi_table_header acpi;\n\tstruct acpi_table_cdat cdat;\n};\n\nstruct fw_upload {\n\tvoid *dd_handle;\n\tvoid *priv;\n};\n\nstruct fw_upload_ops {\n\tenum fw_upload_err (*prepare)(struct fw_upload *, const u8 *, u32);\n\tenum fw_upload_err (*write)(struct fw_upload *, const u8 *, u32, u32, u32 *);\n\tenum fw_upload_err (*poll_complete)(struct fw_upload *);\n\tvoid (*cancel)(struct fw_upload *);\n\tvoid (*cleanup)(struct fw_upload *);\n};\n\nstruct fw_upload_priv {\n\tstruct fw_upload *fw_upload;\n\tstruct module *module;\n\tconst char *name;\n\tconst struct fw_upload_ops *ops;\n\tstruct mutex lock;\n\tstruct work_struct work;\n\tconst u8 *data;\n\tu32 remaining_size;\n\tenum fw_upload_prog progress;\n\tenum fw_upload_prog err_progress;\n\tenum fw_upload_err err_code;\n};\n\nstruct fwh_xxlock_thunk {\n\tenum fwh_lock_state val;\n\tflstate_t state;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct meson_clk_hw_data {\n\tstruct clk_hw **hws;\n\tunsigned int num;\n};\n\nstruct meson_clkc_data {\n\tconst struct reg_sequence *init_regs;\n\tunsigned int init_count;\n\tstruct meson_clk_hw_data hw_clks;\n};\n\nstruct g12a_clkc_data {\n\tconst struct meson_clkc_data clkc_data;\n\tint (*dvfs_setup)(struct platform_device *);\n};\n\nstruct g12a_cpu_clk_dyn_nb_data {\n\tstruct notifier_block nb;\n\tstruct clk_hw *xtal;\n\tstruct clk_hw *cpu_clk_dyn;\n\tstruct clk_hw *cpu_clk_postmux0;\n\tstruct clk_hw *cpu_clk_postmux1;\n\tstruct clk_hw *cpu_clk_premux1;\n};\n\nstruct g12a_sys_pll_nb_data {\n\tstruct notifier_block nb;\n\tstruct clk_hw *sys_pll;\n\tstruct clk_hw *cpu_clk;\n\tstruct clk_hw *cpu_clk_dyn;\n};\n\nstruct gbe_phy_init_data_fix {\n\tu16 addr;\n\tu16 value;\n};\n\nstruct gce {\n\t__le32 period;\n\tu8 gate;\n\tu8 res[3];\n};\n\nstruct ghash_key {\n\tbe128 k;\n\tu64 h[0];\n};\n\nstruct gcm_aes_ctx {\n\tstruct aes_enckey aes_key;\n\tu8 nonce[4];\n\tstruct ghash_key ghash_key;\n};\n\nstruct gcry_mpi;\n\ntypedef struct gcry_mpi *MPI;\n\nstruct gcry_mpi {\n\tint alloced;\n\tint nlimbs;\n\tint nbits;\n\tint sign;\n\tunsigned int flags;\n\tmpi_limb_t *d;\n};\n\nstruct gcs_context {\n\tstruct _aarch64_ctx head;\n\t__u64 gcspr;\n\t__u64 features_enabled;\n\t__u64 reserved;\n};\n\nstruct gdsc {\n\tstruct generic_pm_domain pd;\n\tstruct generic_pm_domain *parent;\n\tstruct regmap *regmap;\n\tunsigned int gdscr;\n\tunsigned int collapse_ctrl;\n\tunsigned int collapse_mask;\n\tunsigned int gds_hw_ctrl;\n\tunsigned int clamp_io_ctrl;\n\tunsigned int *cxcs;\n\tunsigned int cxc_count;\n\tunsigned int en_rest_wait_val;\n\tunsigned int en_few_wait_val;\n\tunsigned int clk_dis_wait_val;\n\tconst u8 pwrsts;\n\tconst u16 flags;\n\tstruct reset_controller_dev *rcdev;\n\tunsigned int *resets;\n\tunsigned int reset_count;\n\tconst char *supply;\n\tstruct regulator *rsupply;\n};\n\nstruct gdsc_desc {\n\tstruct device *dev;\n\tstruct gdsc **scs;\n\tsize_t num;\n\tstruct dev_pm_domain_list *pd_list;\n};\n\nstruct gem_statistic {\n\tchar stat_string[32];\n\tint offset;\n\tu32 stat_bits;\n};\n\nstruct gem_stats {\n\tu64 tx_octets;\n\tu64 tx_frames;\n\tu64 tx_broadcast_frames;\n\tu64 tx_multicast_frames;\n\tu64 tx_pause_frames;\n\tu64 tx_64_byte_frames;\n\tu64 tx_65_127_byte_frames;\n\tu64 tx_128_255_byte_frames;\n\tu64 tx_256_511_byte_frames;\n\tu64 tx_512_1023_byte_frames;\n\tu64 tx_1024_1518_byte_frames;\n\tu64 tx_greater_than_1518_byte_frames;\n\tu64 tx_underrun;\n\tu64 tx_single_collision_frames;\n\tu64 tx_multiple_collision_frames;\n\tu64 tx_excessive_collisions;\n\tu64 tx_late_collisions;\n\tu64 tx_deferred_frames;\n\tu64 tx_carrier_sense_errors;\n\tu64 rx_octets;\n\tu64 rx_frames;\n\tu64 rx_broadcast_frames;\n\tu64 rx_multicast_frames;\n\tu64 rx_pause_frames;\n\tu64 rx_64_byte_frames;\n\tu64 rx_65_127_byte_frames;\n\tu64 rx_128_255_byte_frames;\n\tu64 rx_256_511_byte_frames;\n\tu64 rx_512_1023_byte_frames;\n\tu64 rx_1024_1518_byte_frames;\n\tu64 rx_greater_than_1518_byte_frames;\n\tu64 rx_undersized_frames;\n\tu64 rx_oversize_frames;\n\tu64 rx_jabbers;\n\tu64 rx_frame_check_sequence_errors;\n\tu64 rx_length_field_frame_errors;\n\tu64 rx_symbol_errors;\n\tu64 rx_alignment_errors;\n\tu64 rx_resource_errors;\n\tu64 rx_overruns;\n\tu64 rx_ip_header_checksum_errors;\n\tu64 rx_tcp_checksum_errors;\n\tu64 rx_udp_checksum_errors;\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct gen_pool;\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct list_head slave_bdevs;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n};\n\nstruct pm_domain_data {\n\tstruct list_head list_node;\n\tstruct device *dev;\n};\n\nstruct gpd_timing_data;\n\nstruct generic_pm_domain_data {\n\tstruct pm_domain_data base;\n\tstruct gpd_timing_data *td;\n\tstruct notifier_block nb;\n\tstruct notifier_block *power_nb;\n\tint cpu;\n\tunsigned int performance_state;\n\tunsigned int default_pstate;\n\tunsigned int rpm_pstate;\n\tunsigned int opp_token;\n\tbool hw_mode;\n\tbool rpm_always_on;\n\tvoid *data;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct geni_icc_path {\n\tstruct icc_path *path;\n\tunsigned int avg_bw;\n};\n\nstruct geni_wrapper;\n\nstruct geni_se {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct geni_wrapper *wrapper;\n\tstruct clk *clk;\n\tunsigned int num_clk_levels;\n\tlong unsigned int *clk_perf_tbl;\n\tstruct geni_icc_path icc_paths[3];\n};\n\nstruct geni_se_desc {\n\tunsigned int num_clks;\n\tconst char * const *clks;\n};\n\nstruct geni_wrapper {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk_bulk_data clks[2];\n\tunsigned int num_clks;\n};\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpd_governor_data {\n\ts64 max_off_time_ns;\n\tbool max_off_time_changed;\n\tktime_t next_wakeup;\n\tktime_t next_hrtimer;\n\tktime_t last_enter;\n\tbool reflect_residency;\n\tbool cached_power_down_ok;\n\tbool cached_power_down_state_idx;\n};\n\nstruct genpd_lock_ops {\n\tvoid (*lock)(struct generic_pm_domain *);\n\tvoid (*lock_nested)(struct generic_pm_domain *, int);\n\tint (*lock_interruptible)(struct generic_pm_domain *);\n\tvoid (*unlock)(struct generic_pm_domain *);\n};\n\nstruct genpd_power_state {\n\tconst char *name;\n\ts64 power_off_latency_ns;\n\ts64 power_on_latency_ns;\n\ts64 residency_ns;\n\tu64 usage;\n\tu64 rejected;\n\tu64 above;\n\tu64 below;\n\tstruct fwnode_handle *fwnode;\n\tu64 idle_time;\n\tvoid *data;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[64];\n\t\tu8 data[512];\n\t};\n};\n\nstruct get_registers_context {\n\tstruct device *dev;\n\tstruct combiner *combiner;\n\tint err;\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct gf128mul_4k {\n\tbe128 t[256];\n};\n\nstruct gf128mul_64k {\n\tstruct gf128mul_4k *t[16];\n};\n\nstruct kvm_memory_slot;\n\nstruct gfn_to_hva_cache {\n\tu64 generation;\n\tgpa_t gpa;\n\tlong unsigned int hva;\n\tlong unsigned int len;\n\tstruct kvm_memory_slot *memslot;\n};\n\nstruct ghes {\n\tunion {\n\t\tstruct acpi_hest_generic *generic;\n\t\tstruct acpi_hest_generic_v2 *generic_v2;\n\t};\n\tstruct acpi_hest_generic_status *estatus;\n\tunsigned int estatus_length;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct timer_list timer;\n\t\tunsigned int irq;\n\t};\n\tstruct device *dev;\n\tstruct list_head elist;\n\tvoid *error_status_vaddr;\n};\n\nstruct ghes_arr {\n\tstruct platform_device **ghes_devs;\n\tunsigned int count;\n};\n\nstruct ghes_estatus_cache {\n\tu32 estatus_len;\n\tatomic_t count;\n\tstruct acpi_hest_generic *generic;\n\tlong long unsigned int time_in;\n\tstruct callback_head rcu;\n};\n\nstruct ghes_estatus_node {\n\tstruct llist_node llnode;\n\tstruct acpi_hest_generic *generic;\n\tstruct ghes *ghes;\n};\n\nstruct ghes_hw_desc {\n\tint num_dimms;\n\tstruct dimm_info *dimms;\n};\n\nstruct ghes_pvt {\n\tstruct mem_ctl_info *mci;\n\tchar other_detail[400];\n\tchar msg[80];\n};\n\nstruct ghes_task_work {\n\tstruct callback_head twork;\n\tu64 pfn;\n\tint flags;\n};\n\nstruct ghes_vendor_record_entry {\n\tstruct work_struct work;\n\tint error_severity;\n\tchar vendor_record[0];\n};\n\nunion gic_base {\n\tvoid *common_base;\n\tvoid **percpu_base;\n};\n\nstruct rdists {\n\tstruct {\n\t\traw_spinlock_t rd_lock;\n\t\tvoid *rd_base;\n\t\tstruct page *pend_page;\n\t\tphys_addr_t phys_base;\n\t\tu64 flags;\n\t\tcpumask_t *vpe_table_mask;\n\t\tvoid *vpe_l1_base;\n\t} *rdist;\n\tphys_addr_t prop_table_pa;\n\tvoid *prop_table_va;\n\tu64 flags;\n\tu32 gicd_typer;\n\tu32 gicd_typer2;\n\tint cpuhp_memreserve_state;\n\tbool has_vlpis;\n\tbool has_rvpeid;\n\tbool has_direct_lpi;\n\tbool has_vpend_valid_dirty;\n};\n\nstruct redist_region;\n\nstruct partition_affinity;\n\nstruct gic_chip_data {\n\tstruct fwnode_handle *fwnode;\n\tphys_addr_t dist_phys_base;\n\tvoid *dist_base;\n\tstruct redist_region *redist_regions;\n\tstruct rdists rdists;\n\tstruct irq_domain *domain;\n\tu64 redist_stride;\n\tu32 nr_redist_regions;\n\tu64 flags;\n\tbool has_rss;\n\tunsigned int ppi_nr;\n\tstruct partition_affinity *parts;\n\tunsigned int nr_parts;\n};\n\nstruct gic_chip_data___2 {\n\tunion gic_base dist_base;\n\tunion gic_base cpu_base;\n\tvoid *raw_dist_base;\n\tvoid *raw_cpu_base;\n\tu32 percpu_offset;\n\tu32 saved_spi_enable[32];\n\tu32 saved_spi_active[32];\n\tu32 saved_spi_conf[64];\n\tu32 saved_spi_target[255];\n\tu32 *saved_ppi_enable;\n\tu32 *saved_ppi_active;\n\tu32 *saved_ppi_conf;\n\tstruct irq_domain *domain;\n\tunsigned int gic_irqs;\n};\n\nstruct gic_chip_data;\n\nstruct gic_clk_data;\n\nstruct gic_chip_pm {\n\tstruct gic_chip_data *chip_data;\n\tconst struct gic_clk_data *clk_data;\n\tstruct clk_bulk_data *clks;\n};\n\nstruct gic_clk_data {\n\tunsigned int num_clocks;\n\tconst char * const *clocks;\n};\n\nstruct gic_kvm_info {\n\tenum gic_type type;\n\tstruct resource vcpu;\n\tvoid *gicc_base;\n\tunsigned int maint_irq;\n\tbool no_maint_irq_mask;\n\tstruct resource vctrl;\n\tbool has_v4;\n\tbool has_v4_1;\n\tbool no_hw_deactivation;\n};\n\nstruct gic_quirk {\n\tconst char *desc;\n\tconst char *compatible;\n\tconst char *property;\n\tbool (*init)(void *);\n\tu32 iidr;\n\tu32 mask;\n};\n\nstruct gicv5_chip_data {\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *ppi_domain;\n\tstruct irq_domain *spi_domain;\n\tstruct irq_domain *lpi_domain;\n\tstruct irq_domain *ipi_domain;\n\tu32 global_spi_count;\n\tu8 cpuif_pri_bits;\n\tu8 cpuif_id_bits;\n\tu8 irs_pri_bits;\n\tbool virt_capable;\n\tstruct {\n\t\t__le64 *l1ist_addr;\n\t\tu32 l2_size;\n\t\tu8 l2_bits;\n\t\tbool l2;\n\t} ist;\n};\n\nstruct gicv5_irs_chip_data {\n\tstruct list_head entry;\n\tstruct fwnode_handle *fwnode;\n\tvoid *irs_base;\n\tu32 flags;\n\tu32 spi_min;\n\tu32 spi_range;\n\traw_spinlock_t spi_config_lock;\n};\n\nstruct gicv5_its_devtab_cfg {\n\tunion {\n\t\tstruct {\n\t\t\t__le64 *devtab;\n\t\t} linear;\n\t\tstruct {\n\t\t\t__le64 *l1devtab;\n\t\t\t__le64 **l2ptrs;\n\t\t} l2;\n\t};\n\tu32 cfgr;\n};\n\nstruct gicv5_its_chip_data {\n\tstruct xarray its_devices;\n\tstruct mutex dev_alloc_lock;\n\tstruct fwnode_handle *fwnode;\n\tstruct gicv5_its_devtab_cfg devtab_cfgr;\n\tvoid *its_base;\n\tu32 flags;\n\tunsigned int msi_domain_flags;\n};\n\nstruct gicv5_its_itt_cfg {\n\tunion {\n\t\tstruct {\n\t\t\t__le64 *itt;\n\t\t\tunsigned int num_ents;\n\t\t} linear;\n\t\tstruct {\n\t\t\t__le64 *l1itt;\n\t\t\t__le64 **l2ptrs;\n\t\t\tunsigned int num_l1_ents;\n\t\t\tu8 l2sz;\n\t\t} l2;\n\t};\n\tu8 event_id_bits;\n\tbool l2itt;\n};\n\nstruct gicv5_its_dev {\n\tstruct gicv5_its_chip_data *its_node;\n\tstruct gicv5_its_itt_cfg itt_cfg;\n\tlong unsigned int *event_map;\n\tu32 device_id;\n\tu32 num_events;\n\tphys_addr_t its_trans_phys_base;\n};\n\nstruct gicv5_iwb_chip_data {\n\tvoid *iwb_base;\n\tu16 nr_regs;\n};\n\nstruct giveback_urb_bh {\n\tbool running;\n\tbool high_prio;\n\tspinlock_t lock;\n\tstruct list_head head;\n\tstruct work_struct bh;\n\tstruct usb_host_endpoint *completing_ep;\n};\n\nstruct rpmsg_device;\n\ntypedef int (*rpmsg_rx_cb_t)(struct rpmsg_device *, void *, int, void *, u32);\n\ntypedef int (*rpmsg_flowcontrol_cb_t)(struct rpmsg_device *, void *, bool);\n\nstruct rpmsg_endpoint_ops;\n\nstruct rpmsg_endpoint {\n\tstruct rpmsg_device *rpdev;\n\tstruct kref refcount;\n\trpmsg_rx_cb_t cb;\n\trpmsg_flowcontrol_cb_t flow_cb;\n\tstruct mutex cb_lock;\n\tu32 addr;\n\tvoid *priv;\n\tconst struct rpmsg_endpoint_ops *ops;\n};\n\nstruct qcom_glink;\n\nstruct glink_core_rx_intent;\n\nstruct glink_channel {\n\tstruct rpmsg_endpoint ept;\n\tstruct rpmsg_device *rpdev;\n\tstruct qcom_glink *glink;\n\tstruct kref refcount;\n\tspinlock_t recv_lock;\n\tchar *name;\n\tunsigned int lcid;\n\tunsigned int rcid;\n\tspinlock_t intent_lock;\n\tstruct idr liids;\n\tstruct idr riids;\n\tstruct work_struct intent_work;\n\tstruct list_head done_intents;\n\tstruct glink_core_rx_intent *buf;\n\tint buf_offset;\n\tint buf_size;\n\tstruct completion open_ack;\n\tstruct completion open_req;\n\tstruct mutex intent_req_lock;\n\tint intent_req_result;\n\tbool intent_received;\n\twait_queue_head_t intent_req_wq;\n};\n\nstruct glink_core_rx_intent {\n\tvoid *data;\n\tu32 id;\n\tsize_t size;\n\tbool reuse;\n\tbool in_use;\n\tu32 offset;\n\tstruct list_head node;\n};\n\nstruct glink_msg_hdr {\n\t__le16 cmd;\n\t__le16 param1;\n\t__le32 param2;\n};\n\nstruct glink_defer_cmd {\n\tstruct list_head node;\n\tstruct glink_msg_hdr msg;\n\tu8 data[0];\n};\n\nstruct glink_msg {\n\tunion {\n\t\tstruct {\n\t\t\t__le16 cmd;\n\t\t\t__le16 param1;\n\t\t\t__le32 param2;\n\t\t};\n\t\tstruct glink_msg_hdr hdr;\n\t};\n\tu8 data[0];\n};\n\nstruct mbox_client {\n\tstruct device *dev;\n\tbool tx_block;\n\tlong unsigned int tx_tout;\n\tbool knows_txdone;\n\tvoid (*rx_callback)(struct mbox_client *, void *);\n\tvoid (*tx_prepare)(struct mbox_client *, void *);\n\tvoid (*tx_done)(struct mbox_client *, void *, int);\n};\n\nstruct qcom_glink_pipe {\n\tsize_t length;\n\tsize_t (*avail)(struct qcom_glink_pipe *);\n\tvoid (*peek)(struct qcom_glink_pipe *, void *, unsigned int, size_t);\n\tvoid (*advance)(struct qcom_glink_pipe *, size_t);\n\tvoid (*write)(struct qcom_glink_pipe *, const void *, size_t, const void *, size_t);\n\tvoid (*kick)(struct qcom_glink_pipe *);\n};\n\nstruct glink_rpm_pipe {\n\tstruct qcom_glink_pipe native;\n\tvoid *tail;\n\tvoid *head;\n\tvoid *fifo;\n};\n\nstruct glink_rpm {\n\tstruct qcom_glink *glink;\n\tint irq;\n\tstruct mbox_client mbox_client;\n\tstruct mbox_chan *mbox_chan;\n\tstruct glink_rpm_pipe rx_pipe;\n\tstruct glink_rpm_pipe tx_pipe;\n};\n\nstruct glink_ssr {\n\tstruct device *dev;\n\tstruct rpmsg_endpoint *ept;\n\tstruct notifier_block nb;\n\tu32 seq_num;\n\tstruct completion completion;\n};\n\nstruct kvm;\n\nstruct gmem_file {\n\tstruct kvm *kvm;\n\tstruct xarray bindings;\n\tstruct list_head entry;\n};\n\nstruct shared_policy {\n\tstruct rb_root root;\n\trwlock_t lock;\n};\n\nstruct gmem_inode {\n\tstruct shared_policy policy;\n\tstruct inode vfs_inode;\n\tu64 flags;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct gntab_unmap_queue_data;\n\ntypedef void (*gnttab_unmap_refs_done)(int, struct gntab_unmap_queue_data *);\n\nstruct gnttab_unmap_grant_ref;\n\nstruct gntab_unmap_queue_data {\n\tstruct delayed_work gnttab_work;\n\tvoid *data;\n\tgnttab_unmap_refs_done done;\n\tstruct gnttab_unmap_grant_ref *unmap_ops;\n\tstruct gnttab_unmap_grant_ref *kunmap_ops;\n\tstruct page **pages;\n\tunsigned int count;\n\tunsigned int age;\n};\n\nstruct gntalloc_file_private_data {\n\tstruct list_head list;\n\tuint64_t index;\n};\n\nstruct notify_info {\n\tuint16_t pgoff: 12;\n\tuint16_t flags: 2;\n\tint event;\n};\n\nstruct gntalloc_gref {\n\tstruct list_head next_gref;\n\tstruct list_head next_file;\n\tstruct page *page;\n\tuint64_t file_index;\n\tunsigned int users;\n\tgrant_ref_t gref_id;\n\tstruct notify_info notify;\n};\n\nstruct gntalloc_vma_private_data {\n\tstruct gntalloc_gref *gref;\n\tint users;\n\tint count;\n};\n\nstruct gnttab_copy_ptr {\n\tunion {\n\t\tgrant_ref_t ref;\n\t\txen_pfn_t gmfn;\n\t} u;\n\tdomid_t domid;\n\tuint16_t offset;\n};\n\nstruct gnttab_copy {\n\tstruct gnttab_copy_ptr source;\n\tstruct gnttab_copy_ptr dest;\n\tuint16_t len;\n\tuint16_t flags;\n\tint16_t status;\n};\n\nstruct gntdev_copy_batch {\n\tstruct gnttab_copy ops[16];\n\tstruct page *pages[16];\n\ts16 *status[16];\n\tunsigned int nr_ops;\n\tunsigned int nr_pages;\n\tbool writeable;\n\tstruct gntdev_copy_batch *next;\n};\n\nstruct gntdev_grant_copy_segment {\n\tunion {\n\t\tvoid *virt;\n\t\tstruct {\n\t\t\tgrant_ref_t ref;\n\t\t\t__u16 offset;\n\t\t\tdomid_t domid;\n\t\t} foreign;\n\t} source;\n\tunion {\n\t\tvoid *virt;\n\t\tstruct {\n\t\t\tgrant_ref_t ref;\n\t\t\t__u16 offset;\n\t\t\tdomid_t domid;\n\t\t} foreign;\n\t} dest;\n\t__u16 len;\n\t__u16 flags;\n\t__s16 status;\n};\n\nstruct interval_tree_node {\n\tstruct rb_node rb;\n\tlong unsigned int start;\n\tlong unsigned int last;\n\tlong unsigned int __subtree_last;\n};\n\nstruct mmu_interval_notifier_ops;\n\nstruct mmu_interval_notifier {\n\tstruct interval_tree_node interval_tree;\n\tconst struct mmu_interval_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct hlist_node deferred_item;\n\tlong unsigned int invalidate_seq;\n};\n\nstruct gntdev_unmap_notify {\n\tint flags;\n\tint addr;\n\tevtchn_port_t event;\n};\n\nstruct ioctl_gntdev_grant_ref;\n\nstruct gnttab_map_grant_ref;\n\nstruct gntdev_grant_map {\n\tatomic_t in_use;\n\tstruct mmu_interval_notifier notifier;\n\tbool notifier_init;\n\tstruct list_head next;\n\tint index;\n\tint count;\n\tint flags;\n\trefcount_t users;\n\tstruct gntdev_unmap_notify notify;\n\tstruct ioctl_gntdev_grant_ref *grants;\n\tstruct gnttab_map_grant_ref *map_ops;\n\tstruct gnttab_unmap_grant_ref *unmap_ops;\n\tstruct gnttab_map_grant_ref *kmap_ops;\n\tstruct gnttab_unmap_grant_ref *kunmap_ops;\n\tbool *being_removed;\n\tstruct page **pages;\n\tlong unsigned int pages_vm_start;\n\tatomic_t live_grants;\n\tstruct gntab_unmap_queue_data unmap_data;\n};\n\nstruct gntdev_priv {\n\tstruct list_head maps;\n\tstruct mutex lock;\n\tstruct gntdev_copy_batch *batch;\n\tstruct mutex batch_lock;\n};\n\nstruct gnttab_cache_flush {\n\tunion {\n\t\tuint64_t dev_bus_addr;\n\t\tgrant_ref_t ref;\n\t} a;\n\tuint16_t offset;\n\tuint16_t length;\n\tuint32_t op;\n};\n\nstruct gnttab_get_status_frames {\n\tuint32_t nr_frames;\n\tdomid_t dom;\n\tint16_t status;\n\t__guest_handle_uint64_t frame_list;\n};\n\nstruct gnttab_map_grant_ref {\n\tuint64_t host_addr;\n\tuint32_t flags;\n\tgrant_ref_t ref;\n\tdomid_t dom;\n\tint16_t status;\n\tgrant_handle_t handle;\n\tuint64_t dev_bus_addr;\n};\n\nstruct gnttab_ops {\n\tunsigned int version;\n\tunsigned int grefs_per_grant_frame;\n\tint (*map_frames)(xen_pfn_t *, unsigned int);\n\tvoid (*unmap_frames)(void);\n\tvoid (*update_entry)(grant_ref_t, domid_t, long unsigned int, unsigned int);\n\tint (*end_foreign_access_ref)(grant_ref_t);\n\tlong unsigned int (*read_frame)(grant_ref_t);\n};\n\nstruct gnttab_page_cache {\n\tspinlock_t lock;\n\tstruct list_head pages;\n\tunsigned int num_pages;\n};\n\nstruct gnttab_query_size {\n\tdomid_t dom;\n\tuint32_t nr_frames;\n\tuint32_t max_nr_frames;\n\tint16_t status;\n};\n\nstruct gnttab_set_version {\n\tuint32_t version;\n};\n\nstruct gnttab_setup_table {\n\tdomid_t dom;\n\tuint32_t nr_frames;\n\tint16_t status;\n\t__guest_handle_xen_pfn_t frame_list;\n};\n\nstruct gnttab_unmap_grant_ref {\n\tuint64_t host_addr;\n\tuint64_t dev_bus_addr;\n\tgrant_handle_t handle;\n\tint16_t status;\n};\n\nstruct gnu_property {\n\tu32 pr_type;\n\tu32 pr_datasz;\n};\n\nstruct governor_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gov_attr_set *, char *);\n\tssize_t (*store)(struct gov_attr_set *, const char *, size_t);\n};\n\nstruct gpcv2_irqchip_data {\n\tstruct raw_spinlock rlock;\n\tvoid *gpc_base;\n\tu32 wakeup_sources[4];\n\tu32 saved_irq_mask[4];\n\tu32 cpu2wakeup;\n};\n\nstruct gpd_link {\n\tstruct generic_pm_domain *parent;\n\tstruct list_head parent_node;\n\tstruct generic_pm_domain *child;\n\tstruct list_head child_node;\n\tunsigned int performance_state;\n\tunsigned int prev_performance_state;\n};\n\nstruct gpd_timing_data {\n\ts64 suspend_latency_ns;\n\ts64 resume_latency_ns;\n\ts64 effective_constraint_ns;\n\tktime_t next_wakeup;\n\tbool constraint_changed;\n\tbool cached_suspend_ok;\n};\n\nstruct gpio_array {\n\tstruct gpio_desc **desc;\n\tunsigned int size;\n\tstruct gpio_device *gdev;\n\tlong unsigned int *get_mask;\n\tlong unsigned int *set_mask;\n\tlong unsigned int invert_mask[0];\n};\n\nstruct gpio_keys_button;\n\nstruct gpio_button_data {\n\tconst struct gpio_keys_button *button;\n\tstruct input_dev *input;\n\tstruct gpio_desc *gpiod;\n\tshort unsigned int *code;\n\tstruct hrtimer release_timer;\n\tunsigned int release_delay;\n\tstruct delayed_work work;\n\tstruct hrtimer debounce_timer;\n\tunsigned int software_debounce;\n\tunsigned int irq;\n\tunsigned int wakeirq;\n\tunsigned int wakeup_trigger_type;\n\tspinlock_t lock;\n\tbool disabled;\n\tbool key_pressed;\n\tbool suspended;\n\tbool debounce_use_hrtimer;\n};\n\nstruct gpio_v2_line_attribute {\n\t__u32 id;\n\t__u32 padding;\n\tunion {\n\t\t__u64 flags;\n\t\t__u64 values;\n\t\t__u32 debounce_period_us;\n\t};\n};\n\nstruct gpio_v2_line_info {\n\tchar name[32];\n\tchar consumer[32];\n\t__u32 offset;\n\t__u32 num_attrs;\n\t__u64 flags;\n\tstruct gpio_v2_line_attribute attrs[10];\n\t__u32 padding[4];\n};\n\nstruct gpio_v2_line_info_changed {\n\tstruct gpio_v2_line_info info;\n\t__u64 timestamp_ns;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct gpio_chardev_data {\n\tstruct gpio_device *gdev;\n\twait_queue_head_t wait;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_info_changed *type;\n\t\t\tconst struct gpio_v2_line_info_changed *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_info_changed *ptr;\n\t\t\tconst struct gpio_v2_line_info_changed *ptr_const;\n\t\t};\n\t\tstruct gpio_v2_line_info_changed buf[32];\n\t} events;\n\tstruct notifier_block lineinfo_changed_nb;\n\tstruct notifier_block device_unregistered_nb;\n\tlong unsigned int *watched_lines;\n\tatomic_t watch_abi_version;\n\tstruct file *fp;\n};\n\nstruct gpio_chip_guard {\n\tstruct gpio_device *gdev;\n\tstruct gpio_chip *gc;\n\tint idx;\n};\n\ntypedef struct gpio_chip_guard class_gpio_chip_guard_t;\n\nstruct gpio_desc_label;\n\nstruct gpio_desc {\n\tstruct gpio_device *gdev;\n\tlong unsigned int flags;\n\tstruct gpio_desc_label *label;\n\tconst char *name;\n\tstruct device_node *hog;\n\tunsigned int debounce_period_us;\n};\n\nstruct gpio_desc_label {\n\tstruct callback_head rh;\n\tchar str[0];\n};\n\nstruct gpio_descs {\n\tstruct gpio_array *info;\n\tunsigned int ndescs;\n\tstruct gpio_desc *desc[0];\n};\n\nstruct gpio_device {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tstruct module *owner;\n\tstruct gpio_chip *chip;\n\tstruct gpio_desc *descs;\n\tlong unsigned int *valid_mask;\n\tstruct srcu_struct desc_srcu;\n\tunsigned int base;\n\tu16 ngpio;\n\tbool can_sleep;\n\tconst char *label;\n\tvoid *data;\n\tstruct list_head list;\n\tstruct raw_notifier_head line_state_notifier;\n\trwlock_t line_state_lock;\n\tstruct workqueue_struct *line_state_wq;\n\tstruct blocking_notifier_head device_notifier;\n\tstruct srcu_struct srcu;\n\tstruct list_head pin_ranges;\n};\n\nstruct gpio_generic_chip_config {\n\tstruct device *dev;\n\tlong unsigned int sz;\n\tvoid *dat;\n\tvoid *set;\n\tvoid *clr;\n\tvoid *dirout;\n\tvoid *dirin;\n\tlong unsigned int flags;\n};\n\nstruct gpio_get_config {\n\tu32 gpio;\n\tu32 direction;\n\tu32 polarity;\n\tu32 term_en;\n\tu32 term_pull_up;\n};\n\nstruct gpio_get_set_state {\n\tu32 gpio;\n\tu32 state;\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct msi_desc;\n\nstruct msi_alloc_info {\n\tstruct msi_desc *desc;\n\tirq_hw_number_t hwirq;\n\tlong unsigned int flags;\n\tunion {\n\t\tlong unsigned int ul;\n\t\tvoid *ptr;\n\t} scratchpad[2];\n};\n\ntypedef struct msi_alloc_info msi_alloc_info_t;\n\nunion gpio_irq_fwspec {\n\tstruct irq_fwspec fwspec;\n\tmsi_alloc_info_t msiinfo;\n};\n\nstruct gpio_keys_button {\n\tunsigned int code;\n\tint gpio;\n\tint active_low;\n\tconst char *desc;\n\tunsigned int type;\n\tint wakeup;\n\tint wakeup_event_action;\n\tint debounce_interval;\n\tbool can_disable;\n\tint value;\n\tunsigned int irq;\n\tunsigned int wakeirq;\n};\n\nstruct gpio_keys_platform_data;\n\nstruct gpio_keys_drvdata {\n\tconst struct gpio_keys_platform_data *pdata;\n\tstruct input_dev *input;\n\tstruct mutex disable_lock;\n\tshort unsigned int *keymap;\n\tstruct gpio_button_data data[0];\n};\n\nstruct gpio_keys_platform_data {\n\tconst struct gpio_keys_button *buttons;\n\tint nbuttons;\n\tunsigned int poll_interval;\n\tunsigned int rep: 1;\n\tint (*enable)(struct device *);\n\tvoid (*disable)(struct device *);\n\tconst char *name;\n};\n\nstruct gpio_led {\n\tconst char *name;\n\tconst char *default_trigger;\n\tunsigned int gpio;\n\tunsigned int active_low: 1;\n\tunsigned int retain_state_suspended: 1;\n\tunsigned int panic_indicator: 1;\n\tunsigned int default_state: 2;\n\tunsigned int retain_state_shutdown: 1;\n\tstruct gpio_desc *gpiod;\n};\n\ntypedef int (*gpio_blink_set_t)(struct gpio_desc *, int, long unsigned int *, long unsigned int *);\n\nstruct gpio_led_data {\n\tstruct led_classdev cdev;\n\tstruct gpio_desc *gpiod;\n\tu8 can_sleep;\n\tu8 blinking;\n\tgpio_blink_set_t platform_gpio_blink_set;\n};\n\nstruct gpio_led_platform_data {\n\tint num_leds;\n\tconst struct gpio_led *leds;\n\tgpio_blink_set_t gpio_blink_set;\n};\n\nstruct gpio_leds_priv {\n\tint num_leds;\n\tstruct gpio_led_data leds[0];\n};\n\nstruct gpio_pin_range {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_gpio_range range;\n};\n\nstruct gpio_rcar_bank_info {\n\tu32 iointsel;\n\tu32 inoutsel;\n\tu32 outdt;\n\tu32 posneg;\n\tu32 edglevel;\n\tu32 bothedge;\n\tu32 intmsk;\n};\n\nstruct gpio_rcar_info {\n\tbool has_outdtsel;\n\tbool has_both_edge_trigger;\n\tbool has_always_in;\n\tbool has_inen;\n};\n\nstruct gpio_rcar_priv {\n\tvoid *base;\n\traw_spinlock_t lock;\n\tstruct device *dev;\n\tstruct gpio_chip gpio_chip;\n\tunsigned int irq_parent;\n\tatomic_t wakeup_path;\n\tstruct gpio_rcar_info info;\n\tstruct gpio_rcar_bank_info bank_info;\n};\n\nstruct gpio_regulator_state;\n\nstruct gpio_regulator_config {\n\tconst char *supply_name;\n\tconst char *input_supply;\n\tunsigned int enabled_at_boot: 1;\n\tunsigned int startup_delay;\n\tenum gpiod_flags *gflags;\n\tint ngpios;\n\tstruct gpio_regulator_state *states;\n\tint nr_states;\n\tenum regulator_type type;\n\tstruct regulator_init_data *init_data;\n};\n\nstruct gpio_regulator_data {\n\tstruct regulator_desc desc;\n\tstruct gpio_desc **gpiods;\n\tint nr_gpios;\n\tstruct gpio_regulator_state *states;\n\tint nr_states;\n\tint state;\n};\n\nstruct gpio_regulator_state {\n\tint value;\n\tint gpios;\n};\n\nstruct gpio_set_config {\n\tu32 gpio;\n\tu32 direction;\n\tu32 polarity;\n\tu32 term_en;\n\tu32 term_pull_up;\n\tu32 state;\n};\n\nstruct gpio_shared_desc {\n\tstruct gpio_desc *desc;\n\tbool can_sleep;\n\tlong unsigned int cfg;\n\tunsigned int usecnt;\n\tunsigned int highcnt;\n\tunion {\n\t\tstruct mutex mutex;\n\t\tspinlock_t spinlock;\n\t};\n};\n\nstruct gpio_shared_entry {\n\tstruct list_head list;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int offset;\n\tsize_t index;\n\tstruct mutex lock;\n\tstruct gpio_shared_desc *shared_desc;\n\tstruct kref ref;\n\tstruct list_head refs;\n};\n\nstruct gpiod_lookup_table;\n\nstruct gpio_shared_ref {\n\tstruct list_head list;\n\tstruct fwnode_handle *fwnode;\n\tenum gpiod_flags flags;\n\tchar *con_id;\n\tint dev_id;\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tstruct auxiliary_device adev;\n\tstruct gpiod_lookup_table *lookup;\n\tbool is_reset_gpio;\n};\n\nstruct gpio_v2_line_config_attribute {\n\tstruct gpio_v2_line_attribute attr;\n\t__u64 mask;\n};\n\nstruct gpio_v2_line_config {\n\t__u64 flags;\n\t__u32 num_attrs;\n\t__u32 padding[5];\n\tstruct gpio_v2_line_config_attribute attrs[10];\n};\n\nstruct gpio_v2_line_event {\n\t__u64 timestamp_ns;\n\t__u32 id;\n\t__u32 offset;\n\t__u32 seqno;\n\t__u32 line_seqno;\n\t__u32 padding[6];\n};\n\nstruct gpio_v2_line_request {\n\t__u32 offsets[64];\n\tchar consumer[32];\n\tstruct gpio_v2_line_config config;\n\t__u32 num_lines;\n\t__u32 event_buffer_size;\n\t__u32 padding[5];\n\t__s32 fd;\n};\n\nstruct gpio_v2_line_values {\n\t__u64 bits;\n\t__u64 mask;\n};\n\nstruct gpiochip_info {\n\tchar name[32];\n\tchar label[32];\n\t__u32 lines;\n};\n\nstruct gpiod_hog {\n\tstruct list_head list;\n\tconst char *chip_label;\n\tu16 chip_hwnum;\n\tconst char *line_name;\n\tlong unsigned int lflags;\n\tint dflags;\n};\n\nstruct gpiod_lookup {\n\tconst char *key;\n\tu16 chip_hwnum;\n\tconst char *con_id;\n\tunsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct gpiod_lookup_table {\n\tstruct list_head list;\n\tconst char *dev_id;\n\tstruct gpiod_lookup table[0];\n};\n\nstruct gpioevent_data {\n\t__u64 timestamp;\n\t__u32 id;\n};\n\nstruct gpioevent_request {\n\t__u32 lineoffset;\n\t__u32 handleflags;\n\t__u32 eventflags;\n\tchar consumer_label[32];\n\tint fd;\n};\n\nstruct gpiohandle_config {\n\t__u32 flags;\n\t__u8 default_values[64];\n\t__u32 padding[4];\n};\n\nstruct gpiohandle_data {\n\t__u8 values[64];\n};\n\nstruct gpiohandle_request {\n\t__u32 lineoffsets[64];\n\t__u32 flags;\n\t__u8 default_values[64];\n\tchar consumer_label[32];\n\t__u32 lines;\n\tint fd;\n};\n\nstruct gpiolib_seq_priv {\n\tbool newline;\n\tint idx;\n};\n\nstruct gpioline_info {\n\t__u32 line_offset;\n\t__u32 flags;\n\tchar name[32];\n\tchar consumer[32];\n};\n\nstruct gpioline_info_changed {\n\tstruct gpioline_info info;\n\t__u64 timestamp;\n\t__u32 event_type;\n\t__u32 padding[5];\n};\n\nstruct grant {\n\tgrant_ref_t gref;\n\tstruct page *page;\n\tstruct list_head node;\n};\n\nstruct grant_entry_header {\n\tuint16_t flags;\n\tdomid_t domid;\n};\n\nstruct grant_entry_v1 {\n\tuint16_t flags;\n\tdomid_t domid;\n\tuint32_t frame;\n};\n\nunion grant_entry_v2 {\n\tstruct grant_entry_header hdr;\n\tstruct {\n\t\tstruct grant_entry_header hdr;\n\t\tuint32_t pad0;\n\t\tuint64_t frame;\n\t} full_page;\n\tstruct {\n\t\tstruct grant_entry_header hdr;\n\t\tuint16_t page_off;\n\t\tuint16_t length;\n\t\tuint64_t frame;\n\t} sub_page;\n\tstruct {\n\t\tstruct grant_entry_header hdr;\n\t\tdomid_t trans_domid;\n\t\tuint16_t pad0;\n\t\tgrant_ref_t gref;\n\t} transitive;\n\tuint32_t __spacer[4];\n};\n\nstruct grant_frames {\n\txen_pfn_t *pfn;\n\tunsigned int count;\n\tvoid *vaddr;\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n};\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tsize_t npins;\n};\n\nstruct group_desc {\n\tstruct pingroup grp;\n\tvoid *data;\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct gsb_buffer {\n\tu8 status;\n\tu8 len;\n\tunion {\n\t\tu16 wdata;\n\t\tu8 bdata;\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct rpc_clnt;\n\nstruct rpc_pipe_ops;\n\nstruct gss_alloc_pdo {\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tconst struct rpc_pipe_ops *upcall_ops;\n};\n\nstruct rpcsec_gss_oid {\n\tunsigned int len;\n\tu8 data[32];\n};\n\nstruct gss_api_ops;\n\nstruct pf_desc;\n\nstruct gss_api_mech {\n\tstruct list_head gm_list;\n\tstruct module *gm_owner;\n\tstruct rpcsec_gss_oid gm_oid;\n\tchar *gm_name;\n\tconst struct gss_api_ops *gm_ops;\n\tint gm_pf_num;\n\tstruct pf_desc *gm_pfs;\n\tconst char *gm_upcall_enctypes;\n};\n\nstruct gss_ctx;\n\nstruct xdr_netobj;\n\nstruct gss_api_ops {\n\tint (*gss_import_sec_context)(const void *, size_t, struct gss_ctx *, time64_t *, gfp_t);\n\tu32 (*gss_get_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_verify_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_wrap)(struct gss_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*gss_unwrap)(struct gss_ctx *, int, int, struct xdr_buf *);\n\tvoid (*gss_delete_sec_context)(void *);\n};\n\nstruct rpc_authops;\n\nstruct rpc_cred_cache;\n\nstruct rpc_auth {\n\tunsigned int au_cslack;\n\tunsigned int au_rslack;\n\tunsigned int au_verfsize;\n\tunsigned int au_ralign;\n\tlong unsigned int au_flags;\n\tconst struct rpc_authops *au_ops;\n\trpc_authflavor_t au_flavor;\n\trefcount_t au_count;\n\tstruct rpc_cred_cache *au_credcache;\n};\n\nstruct gss_pipe;\n\nstruct gss_auth {\n\tstruct kref kref;\n\tstruct hlist_node hash;\n\tstruct rpc_auth rpc_auth;\n\tstruct gss_api_mech *mech;\n\tenum rpc_gss_svc service;\n\tstruct rpc_clnt *client;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct gss_pipe *gss_pipe[2];\n\tconst char *target_name;\n};\n\nstruct xdr_netobj {\n\tunsigned int len;\n\tu8 *data;\n};\n\nstruct gss_cl_ctx {\n\trefcount_t count;\n\tenum rpc_gss_proc gc_proc;\n\tu32 gc_seq;\n\tu32 gc_seq_xmit;\n\tspinlock_t gc_seq_lock;\n\tstruct gss_ctx *gc_gss_ctx;\n\tstruct xdr_netobj gc_wire_ctx;\n\tstruct xdr_netobj gc_acceptor;\n\tu32 gc_win;\n\tlong unsigned int gc_expiry;\n\tstruct callback_head gc_rcu;\n};\n\nstruct rpc_credops;\n\nstruct rpc_cred {\n\tstruct hlist_node cr_hash;\n\tstruct list_head cr_lru;\n\tstruct callback_head cr_rcu;\n\tstruct rpc_auth *cr_auth;\n\tconst struct rpc_credops *cr_ops;\n\tlong unsigned int cr_expire;\n\tlong unsigned int cr_flags;\n\trefcount_t cr_count;\n\tconst struct cred *cr_cred;\n};\n\nstruct gss_upcall_msg;\n\nstruct gss_cred {\n\tstruct rpc_cred gc_base;\n\tenum rpc_gss_svc gc_service;\n\tstruct gss_cl_ctx *gc_ctx;\n\tstruct gss_upcall_msg *gc_upcall;\n\tconst char *gc_principal;\n\tlong unsigned int gc_upcall_timestamp;\n};\n\nstruct gss_ctx {\n\tstruct gss_api_mech *mech_type;\n\tvoid *internal_ctx_id;\n\tunsigned int slack;\n\tunsigned int align;\n};\n\nstruct gss_domain {\n\tstruct auth_domain h;\n\tu32 pseudoflavor;\n};\n\nstruct krb5_ctx;\n\nstruct gss_krb5_enctype {\n\tconst u32 etype;\n\tconst u32 ctype;\n\tconst char *name;\n\tconst char *encrypt_name;\n\tconst char *aux_cipher;\n\tconst char *cksum_name;\n\tconst u16 signalg;\n\tconst u16 sealalg;\n\tconst u32 cksumlength;\n\tconst u32 keyed_cksum;\n\tconst u32 keybytes;\n\tconst u32 keylength;\n\tconst u32 Kc_length;\n\tconst u32 Ke_length;\n\tconst u32 Ki_length;\n\tint (*derive_key)(const struct gss_krb5_enctype *, const struct xdr_netobj *, struct xdr_netobj *, const struct xdr_netobj *, gfp_t);\n\tu32 (*encrypt)(struct krb5_ctx *, u32, struct xdr_buf *, struct page **);\n\tu32 (*decrypt)(struct krb5_ctx *, u32, u32, struct xdr_buf *, u32 *, u32 *);\n\tu32 (*get_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*verify_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*wrap)(struct krb5_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*unwrap)(struct krb5_ctx *, int, int, struct xdr_buf *, unsigned int *, unsigned int *);\n};\n\nstruct rpc_pipe_dir_object_ops;\n\nstruct rpc_pipe_dir_object {\n\tstruct list_head pdo_head;\n\tconst struct rpc_pipe_dir_object_ops *pdo_ops;\n\tvoid *pdo_data;\n};\n\nstruct rpc_pipe;\n\nstruct gss_pipe {\n\tstruct rpc_pipe_dir_object pdo;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tstruct kref kref;\n};\n\nstruct rpc_gss_wire_cred {\n\tu32 gc_v;\n\tu32 gc_proc;\n\tu32 gc_seq;\n\tu32 gc_svc;\n\tstruct xdr_netobj gc_ctx;\n};\n\nstruct rsc;\n\nstruct gss_svc_data {\n\tstruct rpc_gss_wire_cred clcred;\n\tu32 gsd_databody_offset;\n\tstruct rsc *rsci;\n\t__be32 gsd_seq_num;\n\tu8 gsd_scratch[40];\n};\n\nstruct gss_svc_seq_data {\n\tu32 sd_max;\n\tlong unsigned int sd_win[2];\n\tspinlock_t sd_lock;\n};\n\nstruct rpc_pipe_msg {\n\tstruct list_head list;\n\tvoid *data;\n\tsize_t len;\n\tsize_t copied;\n\tint errno;\n};\n\nstruct rpc_timer {\n\tstruct list_head list;\n\tlong unsigned int expires;\n\tstruct delayed_work dwork;\n};\n\nstruct rpc_wait_queue {\n\tspinlock_t lock;\n\tstruct list_head tasks[4];\n\tunsigned char maxpriority;\n\tunsigned char priority;\n\tunsigned char nr;\n\tunsigned int qlen;\n\tstruct rpc_timer timer_list;\n\tconst char *name;\n};\n\nstruct gss_upcall_msg {\n\trefcount_t count;\n\tkuid_t uid;\n\tconst char *service_name;\n\tstruct rpc_pipe_msg msg;\n\tstruct list_head list;\n\tstruct gss_auth *auth;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_wait_queue rpc_waitqueue;\n\twait_queue_head_t waitqueue;\n\tstruct gss_cl_ctx *ctx;\n\tchar databuf[256];\n};\n\nstruct gssp_in_token {\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n};\n\nstruct svc_cred {\n\tkuid_t cr_uid;\n\tkgid_t cr_gid;\n\tstruct group_info *cr_group_info;\n\tu32 cr_flavor;\n\tchar *cr_raw_principal;\n\tchar *cr_principal;\n\tchar *cr_targ_princ;\n\tstruct gss_api_mech *cr_gss_mech;\n};\n\nstruct gssp_upcall_data {\n\tstruct xdr_netobj in_handle;\n\tstruct gssp_in_token in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tstruct rpcsec_gss_oid mech_oid;\n\tstruct svc_cred creds;\n\tint found_creds;\n\tint major_status;\n\tint minor_status;\n};\n\ntypedef struct xdr_netobj utf8string;\n\ntypedef struct xdr_netobj gssx_buffer;\n\nstruct gssx_option;\n\nstruct gssx_option_array {\n\tu32 count;\n\tstruct gssx_option *data;\n};\n\nstruct gssx_call_ctx {\n\tutf8string locale;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx;\n\nstruct gssx_cred;\n\nstruct gssx_cb;\n\nstruct gssx_arg_accept_sec_context {\n\tstruct gssx_call_ctx call_ctx;\n\tstruct gssx_ctx *context_handle;\n\tstruct gssx_cred *cred_handle;\n\tstruct gssp_in_token input_token;\n\tstruct gssx_cb *input_cb;\n\tu32 ret_deleg_cred;\n\tstruct gssx_option_array options;\n\tstruct page **pages;\n\tunsigned int npages;\n};\n\nstruct gssx_cb {\n\tu64 initiator_addrtype;\n\tgssx_buffer initiator_address;\n\tu64 acceptor_addrtype;\n\tgssx_buffer acceptor_address;\n\tgssx_buffer application_data;\n};\n\nstruct gssx_name {\n\tgssx_buffer display_name;\n};\n\ntypedef struct gssx_name gssx_name;\n\nstruct gssx_cred_element;\n\nstruct gssx_cred_element_array {\n\tu32 count;\n\tstruct gssx_cred_element *data;\n};\n\nstruct gssx_cred {\n\tgssx_name desired_name;\n\tstruct gssx_cred_element_array elements;\n\tgssx_buffer cred_handle_reference;\n\tu32 needs_release;\n};\n\ntypedef struct xdr_netobj gssx_OID;\n\nstruct gssx_cred_element {\n\tgssx_name MN;\n\tgssx_OID mech;\n\tu32 cred_usage;\n\tu64 initiator_time_rec;\n\tu64 acceptor_time_rec;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx {\n\tgssx_buffer exported_context_token;\n\tgssx_buffer state;\n\tu32 need_release;\n\tgssx_OID mech;\n\tgssx_name src_name;\n\tgssx_name targ_name;\n\tu64 lifetime;\n\tu64 ctx_flags;\n\tu32 locally_initiated;\n\tu32 open;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_name_attr {\n\tgssx_buffer attr;\n\tgssx_buffer value;\n\tstruct gssx_option_array extensions;\n};\n\nstruct gssx_name_attr_array {\n\tu32 count;\n\tstruct gssx_name_attr *data;\n};\n\nstruct gssx_option {\n\tgssx_buffer option;\n\tgssx_buffer value;\n};\n\nstruct gssx_status {\n\tu64 major_status;\n\tgssx_OID mech;\n\tu64 minor_status;\n\tutf8string major_status_string;\n\tutf8string minor_status_string;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_res_accept_sec_context {\n\tstruct gssx_status status;\n\tstruct gssx_ctx *context_handle;\n\tgssx_buffer *output_token;\n\tstruct gssx_option_array options;\n};\n\nstruct gti_match_data {\n\tu32 gti_num_timers;\n};\n\nstruct gti_wdt_priv {\n\tstruct watchdog_device wdev;\n\tvoid *base;\n\tu32 clock_freq;\n\tstruct clk *sclk;\n\tu32 wdt_timer_idx;\n\tconst struct gti_match_data *data;\n};\n\nunion handle_parts {\n\tdepot_stack_handle_t handle;\n\tstruct {\n\t\tu32 pool_index_plus_1: 17;\n\t\tu32 offset: 10;\n\t\tu32 extra: 5;\n\t};\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct handshake_net {\n\tspinlock_t hn_lock;\n\tint hn_pending;\n\tint hn_pending_max;\n\tstruct list_head hn_requests;\n\tlong unsigned int hn_flags;\n};\n\nstruct handshake_req;\n\nstruct handshake_proto {\n\tint hp_handler_class;\n\tsize_t hp_privsize;\n\tlong unsigned int hp_flags;\n\tint (*hp_accept)(struct handshake_req *, struct genl_info *, int);\n\tvoid (*hp_done)(struct handshake_req *, unsigned int, struct genl_info *);\n\tvoid (*hp_destroy)(struct handshake_req *);\n};\n\nstruct handshake_req {\n\tstruct list_head hr_list;\n\tstruct rhash_head hr_rhash;\n\tlong unsigned int hr_flags;\n\tconst struct handshake_proto *hr_proto;\n\tstruct sock *hr_sk;\n\tvoid (*hr_odestruct)(struct sock *);\n\tchar hr_priv[0];\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hash_prefix {\n\tconst char *name;\n\tconst u8 *data;\n\tsize_t size;\n};\n\nstruct hc_driver {\n\tconst char *description;\n\tconst char *product_desc;\n\tsize_t hcd_priv_size;\n\tirqreturn_t (*irq)(struct usb_hcd *);\n\tint flags;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*pci_suspend)(struct usb_hcd *, bool);\n\tint (*pci_resume)(struct usb_hcd *, pm_message_t);\n\tint (*pci_poweroff_late)(struct usb_hcd *, bool);\n\tvoid (*stop)(struct usb_hcd *);\n\tvoid (*shutdown)(struct usb_hcd *);\n\tint (*get_frame_number)(struct usb_hcd *);\n\tint (*urb_enqueue)(struct usb_hcd *, struct urb *, gfp_t);\n\tint (*urb_dequeue)(struct usb_hcd *, struct urb *, int);\n\tint (*map_urb_for_dma)(struct usb_hcd *, struct urb *, gfp_t);\n\tvoid (*unmap_urb_for_dma)(struct usb_hcd *, struct urb *);\n\tvoid (*endpoint_disable)(struct usb_hcd *, struct usb_host_endpoint *);\n\tvoid (*endpoint_reset)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*hub_status_data)(struct usb_hcd *, char *);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n\tint (*bus_suspend)(struct usb_hcd *);\n\tint (*bus_resume)(struct usb_hcd *);\n\tint (*start_port_reset)(struct usb_hcd *, unsigned int);\n\tlong unsigned int (*get_resuming_ports)(struct usb_hcd *);\n\tvoid (*relinquish_port)(struct usb_hcd *, int);\n\tint (*port_handed_over)(struct usb_hcd *, int);\n\tvoid (*clear_tt_buffer_complete)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*alloc_dev)(struct usb_hcd *, struct usb_device *);\n\tvoid (*free_dev)(struct usb_hcd *, struct usb_device *);\n\tint (*alloc_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, unsigned int, gfp_t);\n\tint (*free_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, gfp_t);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*address_device)(struct usb_hcd *, struct usb_device *, unsigned int);\n\tint (*enable_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*reset_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_device)(struct usb_hcd *, struct usb_device *);\n\tint (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);\n\tint (*enable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*disable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*find_raw_port_number)(struct usb_hcd *, int);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n\tint (*submit_single_step_set_feature)(struct usb_hcd *, struct urb *, int);\n};\n\nstruct hclge_basic_info {\n\tu8 hw_tc_map;\n\tu8 rsv;\n\t__le16 mbx_api_version;\n\t__le32 pf_caps;\n};\n\nstruct hclge_bp_to_qs_map_cmd {\n\tu8 tc_id;\n\tu8 rsvd[2];\n\tu8 qs_group_id;\n\t__le32 qs_bit_map;\n\tu32 rsvd1;\n};\n\nstruct hclge_cfg {\n\tu8 tc_num;\n\tu8 vlan_fliter_cap;\n\tu16 tqp_desc_num;\n\tu16 rx_buf_len;\n\tu16 vf_rss_size_max;\n\tu16 pf_rss_size_max;\n\tu8 phy_addr;\n\tu8 media_type;\n\tu8 mac_addr[6];\n\tu8 default_speed;\n\tu32 numa_node_map;\n\tu32 tx_spare_buf_size;\n\tu16 speed_ability;\n\tu16 umv_space;\n};\n\nstruct hclge_cfg_com_tqp_queue_cmd {\n\t__le16 tqp_id;\n\t__le16 stream_id;\n\tu8 enable;\n\tu8 rsv[19];\n};\n\nstruct hclge_cfg_gro_status_cmd {\n\tu8 gro_en;\n\tu8 rsv[23];\n};\n\nstruct hclge_cfg_param_cmd {\n\t__le32 offset;\n\t__le32 rsv;\n\t__le32 param[4];\n};\n\nstruct hclge_cfg_pause_param_cmd {\n\tu8 mac_addr[6];\n\tu8 pause_trans_gap;\n\tu8 rsvd;\n\t__le16 pause_trans_time;\n\tu8 rsvd1[6];\n\tu8 mac_addr_extra[6];\n\tu16 rsvd2;\n};\n\nstruct hclge_cfg_tso_status_cmd {\n\t__le16 tso_mss_min;\n\t__le16 tso_mss_max;\n\tu8 rsv[20];\n};\n\nstruct hclge_cmdq_tx_timeout_map {\n\tu32 opcode;\n\tu32 tx_timeout;\n};\n\nstruct hclge_comm_caps_bit_map {\n\tu16 imp_bit;\n\tu16 local_bit;\n};\n\nstruct hclge_desc;\n\nstruct hclge_comm_cmq_ring {\n\tdma_addr_t desc_dma_addr;\n\tstruct hclge_desc *desc;\n\tstruct pci_dev *pdev;\n\tu32 head;\n\tu32 tail;\n\tu16 buf_size;\n\tu16 desc_num;\n\tint next_to_use;\n\tint next_to_clean;\n\tu8 ring_type;\n\tspinlock_t lock;\n};\n\nstruct hclge_comm_hw;\n\nstruct hclge_comm_cmq_ops {\n\tvoid (*trace_cmd_send)(struct hclge_comm_hw *, struct hclge_desc *, int, bool);\n\tvoid (*trace_cmd_get)(struct hclge_comm_hw *, struct hclge_desc *, int, bool);\n};\n\nstruct hclge_comm_cmq {\n\tstruct hclge_comm_cmq_ring csq;\n\tstruct hclge_comm_cmq_ring crq;\n\tu16 tx_timeout;\n\tenum hclge_comm_cmd_status last_status;\n\tstruct hclge_comm_cmq_ops ops;\n};\n\nstruct hclge_comm_errcode {\n\tu32 imp_errcode;\n\tint common_errno;\n};\n\nstruct hclge_comm_firmware_compat_cmd {\n\t__le32 compat;\n\tu8 rsv[20];\n};\n\nstruct hclge_comm_hw {\n\tvoid *io_base;\n\tvoid *mem_base;\n\tstruct hclge_comm_cmq cmq;\n\tlong unsigned int comm_state;\n};\n\nstruct hclge_comm_query_scc_cmd {\n\t__le32 scc_version;\n\tu8 rsv[20];\n};\n\nstruct hclge_comm_query_version_cmd {\n\t__le32 firmware;\n\t__le32 hardware;\n\t__le32 api_caps;\n\t__le32 caps[3];\n};\n\nstruct hclge_comm_rss_tuple_cfg {\n\tu8 ipv4_tcp_en;\n\tu8 ipv4_udp_en;\n\tu8 ipv4_sctp_en;\n\tu8 ipv4_fragment_en;\n\tu8 ipv6_tcp_en;\n\tu8 ipv6_udp_en;\n\tu8 ipv6_sctp_en;\n\tu8 ipv6_fragment_en;\n};\n\nstruct hclge_comm_rss_cfg {\n\tu8 rss_hash_key[40];\n\tu16 *rss_indirection_tbl;\n\tu32 rss_algo;\n\tstruct hclge_comm_rss_tuple_cfg rss_tuple_sets;\n\tu32 rss_size;\n};\n\nstruct hclge_comm_rss_config_cmd {\n\tu8 hash_config;\n\tu8 rsv[7];\n\tu8 hash_key[16];\n};\n\nstruct hclge_comm_rss_ind_tbl_cmd {\n\t__le16 start_table_index;\n\t__le16 rss_set_bitmap;\n\tu8 rss_qid_h[4];\n\tu8 rss_qid_l[16];\n};\n\nstruct hclge_comm_rss_input_tuple_cmd {\n\tu8 ipv4_tcp_en;\n\tu8 ipv4_udp_en;\n\tu8 ipv4_sctp_en;\n\tu8 ipv4_fragment_en;\n\tu8 ipv6_tcp_en;\n\tu8 ipv6_udp_en;\n\tu8 ipv6_sctp_en;\n\tu8 ipv6_fragment_en;\n\tu8 rsv[16];\n};\n\nstruct hclge_comm_rss_tc_mode_cmd {\n\t__le16 rss_tc_mode[8];\n\tu8 rsv[8];\n};\n\nstruct hclge_comm_stats_str {\n\tchar desc[32];\n\tu32 stats_num;\n\tlong unsigned int offset;\n};\n\nstruct hnae3_ae_algo;\n\nstruct hnae3_handle;\n\nstruct hnae3_queue {\n\tvoid *io_base;\n\tvoid *mem_base;\n\tstruct hnae3_ae_algo *ae_algo;\n\tstruct hnae3_handle *handle;\n\tint tqp_index;\n\tu32 buf_size;\n\tu16 tx_desc_num;\n\tu16 rx_desc_num;\n};\n\nstruct hclge_comm_tqp_stats {\n\tu64 rcb_tx_ring_pktnum_rcd;\n\tu64 rcb_rx_ring_pktnum_rcd;\n};\n\nstruct hclge_comm_tqp {\n\tstruct device *dev;\n\tstruct hnae3_queue q;\n\tstruct hclge_comm_tqp_stats tqp_stats;\n\tu16 index;\n\tbool alloced;\n};\n\nstruct hclge_common_lb_cmd {\n\tu8 mask;\n\tu8 enable;\n\tu8 result;\n\tu8 rsv[21];\n};\n\nstruct hclge_config_auto_neg_cmd {\n\t__le32 cfg_an_cmd_flag;\n\tu8 rsv[20];\n};\n\nstruct hclge_config_fec_cmd {\n\tu8 fec_mode;\n\tu8 default_config;\n\tu8 rsv[22];\n};\n\nstruct hclge_config_mac_mode_cmd {\n\t__le32 txrx_pad_fcs_loop_en;\n\tu8 rsv[20];\n};\n\nstruct hclge_config_mac_speed_dup_cmd {\n\tu8 speed_dup;\n\tu8 mac_change_fec_en;\n\tu8 rsv[4];\n\tu8 lane_num;\n\tu8 rsv1[17];\n};\n\nstruct hclge_config_max_frm_size_cmd {\n\t__le16 max_frm_size;\n\tu8 min_frm_size;\n\tu8 rsv[21];\n};\n\nstruct hclge_ctrl_vector_chain_cmd {\n\tu8 int_vector_id_l;\n\tu8 int_cause_num;\n\t__le16 tqp_type_and_id[10];\n\tu8 vfid;\n\tu8 int_vector_id_h;\n};\n\nstruct hclge_dbg_bitmap_cmd {\n\tunion {\n\t\tu8 bitmap;\n\t\tstruct {\n\t\t\tu8 bit0: 1;\n\t\t\tu8 bit1: 1;\n\t\t\tu8 bit2: 1;\n\t\t\tu8 bit3: 1;\n\t\t\tu8 bit4: 1;\n\t\t\tu8 bit5: 1;\n\t\t\tu8 bit6: 1;\n\t\t\tu8 bit7: 1;\n\t\t};\n\t};\n};\n\nstruct hclge_dbg_dfx_message {\n\tint flag;\n\tchar message[60];\n};\n\ntypedef int (*read_func)(struct seq_file *, void *);\n\nstruct hclge_dev;\n\nstruct hclge_dbg_func {\n\tenum hnae3_dbg_cmd cmd;\n\tint (*dbg_dump)(struct hclge_dev *, char *, int);\n\tint (*dbg_dump_reg)(struct hclge_dev *, enum hnae3_dbg_cmd, char *, int);\n\tread_func dbg_read_func;\n};\n\nstruct hclge_dbg_reg_common_msg {\n\tint msg_num;\n\tint offset;\n\tenum hclge_opcode_type cmd;\n};\n\nstruct hclge_dbg_reg_type_info {\n\tenum hnae3_dbg_cmd cmd;\n\tconst struct hclge_dbg_dfx_message *dfx_msg;\n\tstruct hclge_dbg_reg_common_msg reg_msg;\n};\n\nstruct hclge_dbg_status_dfx_info {\n\tu32 offset;\n\tchar message[60];\n};\n\nstruct hclge_dbg_tcam_msg {\n\tu8 stage;\n\tu32 loc;\n};\n\nstruct hclge_dbg_vlan_cfg {\n\tu16 pvid;\n\tu8 accept_tag1;\n\tu8 accept_tag2;\n\tu8 accept_untag1;\n\tu8 accept_untag2;\n\tu8 insert_tag1;\n\tu8 insert_tag2;\n\tu8 shift_tag;\n\tu8 strip_tag1;\n\tu8 strip_tag2;\n\tu8 drop_tag1;\n\tu8 drop_tag2;\n\tu8 pri_only1;\n\tu8 pri_only2;\n};\n\nstruct hclge_desc {\n\t__le16 opcode;\n\t__le16 flag;\n\t__le16 retval;\n\t__le16 rsv;\n\t__le32 data[6];\n};\n\nstruct hclge_wol_info {\n\tu32 wol_support_mode;\n\tu32 wol_current_mode;\n\tu8 wol_sopass[6];\n\tu8 wol_sopass_size;\n};\n\nstruct hclge_mac {\n\tu8 mac_id;\n\tu8 phy_addr;\n\tu8 flag;\n\tu8 media_type;\n\tu8 mac_addr[6];\n\tu8 autoneg;\n\tu8 req_autoneg;\n\tu8 duplex;\n\tu8 req_duplex;\n\tu8 support_autoneg;\n\tu8 speed_type;\n\tu8 lane_num;\n\tu32 speed;\n\tu32 req_speed;\n\tu32 max_speed;\n\tu32 speed_ability;\n\tu32 module_type;\n\tu32 fec_mode;\n\tu32 user_fec_mode;\n\tu32 fec_ability;\n\tint link;\n\tstruct hclge_wol_info wol;\n\tstruct phy_device *phydev;\n\tstruct mii_bus *mdio_bus;\n\tphy_interface_t phy_if;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n};\n\nstruct hclge_hw {\n\tstruct hclge_comm_hw hw;\n\tstruct hclge_mac mac;\n\tint num_vec;\n};\n\nstruct hclge_misc_vector {\n\tu8 *addr;\n\tint vector_irq;\n\tchar name[32];\n};\n\nstruct hclge_mac_stats {\n\tu64 mac_tx_mac_pause_num;\n\tu64 mac_rx_mac_pause_num;\n\tu64 rsv0;\n\tu64 mac_tx_pfc_pri0_pkt_num;\n\tu64 mac_tx_pfc_pri1_pkt_num;\n\tu64 mac_tx_pfc_pri2_pkt_num;\n\tu64 mac_tx_pfc_pri3_pkt_num;\n\tu64 mac_tx_pfc_pri4_pkt_num;\n\tu64 mac_tx_pfc_pri5_pkt_num;\n\tu64 mac_tx_pfc_pri6_pkt_num;\n\tu64 mac_tx_pfc_pri7_pkt_num;\n\tu64 mac_rx_pfc_pri0_pkt_num;\n\tu64 mac_rx_pfc_pri1_pkt_num;\n\tu64 mac_rx_pfc_pri2_pkt_num;\n\tu64 mac_rx_pfc_pri3_pkt_num;\n\tu64 mac_rx_pfc_pri4_pkt_num;\n\tu64 mac_rx_pfc_pri5_pkt_num;\n\tu64 mac_rx_pfc_pri6_pkt_num;\n\tu64 mac_rx_pfc_pri7_pkt_num;\n\tu64 mac_tx_total_pkt_num;\n\tu64 mac_tx_total_oct_num;\n\tu64 mac_tx_good_pkt_num;\n\tu64 mac_tx_bad_pkt_num;\n\tu64 mac_tx_good_oct_num;\n\tu64 mac_tx_bad_oct_num;\n\tu64 mac_tx_uni_pkt_num;\n\tu64 mac_tx_multi_pkt_num;\n\tu64 mac_tx_broad_pkt_num;\n\tu64 mac_tx_undersize_pkt_num;\n\tu64 mac_tx_oversize_pkt_num;\n\tu64 mac_tx_64_oct_pkt_num;\n\tu64 mac_tx_65_127_oct_pkt_num;\n\tu64 mac_tx_128_255_oct_pkt_num;\n\tu64 mac_tx_256_511_oct_pkt_num;\n\tu64 mac_tx_512_1023_oct_pkt_num;\n\tu64 mac_tx_1024_1518_oct_pkt_num;\n\tu64 mac_tx_1519_2047_oct_pkt_num;\n\tu64 mac_tx_2048_4095_oct_pkt_num;\n\tu64 mac_tx_4096_8191_oct_pkt_num;\n\tu64 rsv1;\n\tu64 mac_tx_8192_9216_oct_pkt_num;\n\tu64 mac_tx_9217_12287_oct_pkt_num;\n\tu64 mac_tx_12288_16383_oct_pkt_num;\n\tu64 mac_tx_1519_max_good_oct_pkt_num;\n\tu64 mac_tx_1519_max_bad_oct_pkt_num;\n\tu64 mac_rx_total_pkt_num;\n\tu64 mac_rx_total_oct_num;\n\tu64 mac_rx_good_pkt_num;\n\tu64 mac_rx_bad_pkt_num;\n\tu64 mac_rx_good_oct_num;\n\tu64 mac_rx_bad_oct_num;\n\tu64 mac_rx_uni_pkt_num;\n\tu64 mac_rx_multi_pkt_num;\n\tu64 mac_rx_broad_pkt_num;\n\tu64 mac_rx_undersize_pkt_num;\n\tu64 mac_rx_oversize_pkt_num;\n\tu64 mac_rx_64_oct_pkt_num;\n\tu64 mac_rx_65_127_oct_pkt_num;\n\tu64 mac_rx_128_255_oct_pkt_num;\n\tu64 mac_rx_256_511_oct_pkt_num;\n\tu64 mac_rx_512_1023_oct_pkt_num;\n\tu64 mac_rx_1024_1518_oct_pkt_num;\n\tu64 mac_rx_1519_2047_oct_pkt_num;\n\tu64 mac_rx_2048_4095_oct_pkt_num;\n\tu64 mac_rx_4096_8191_oct_pkt_num;\n\tu64 rsv2;\n\tu64 mac_rx_8192_9216_oct_pkt_num;\n\tu64 mac_rx_9217_12287_oct_pkt_num;\n\tu64 mac_rx_12288_16383_oct_pkt_num;\n\tu64 mac_rx_1519_max_good_oct_pkt_num;\n\tu64 mac_rx_1519_max_bad_oct_pkt_num;\n\tu64 mac_tx_fragment_pkt_num;\n\tu64 mac_tx_undermin_pkt_num;\n\tu64 mac_tx_jabber_pkt_num;\n\tu64 mac_tx_err_all_pkt_num;\n\tu64 mac_tx_from_app_good_pkt_num;\n\tu64 mac_tx_from_app_bad_pkt_num;\n\tu64 mac_rx_fragment_pkt_num;\n\tu64 mac_rx_undermin_pkt_num;\n\tu64 mac_rx_jabber_pkt_num;\n\tu64 mac_rx_fcs_err_pkt_num;\n\tu64 mac_rx_send_app_good_pkt_num;\n\tu64 mac_rx_send_app_bad_pkt_num;\n\tu64 mac_tx_pfc_pause_pkt_num;\n\tu64 mac_rx_pfc_pause_pkt_num;\n\tu64 mac_tx_ctrl_pkt_num;\n\tu64 mac_rx_ctrl_pkt_num;\n\tu64 mac_tx_pfc_pri0_xoff_time;\n\tu64 mac_tx_pfc_pri1_xoff_time;\n\tu64 mac_tx_pfc_pri2_xoff_time;\n\tu64 mac_tx_pfc_pri3_xoff_time;\n\tu64 mac_tx_pfc_pri4_xoff_time;\n\tu64 mac_tx_pfc_pri5_xoff_time;\n\tu64 mac_tx_pfc_pri6_xoff_time;\n\tu64 mac_tx_pfc_pri7_xoff_time;\n\tu64 mac_rx_pfc_pri0_xoff_time;\n\tu64 mac_rx_pfc_pri1_xoff_time;\n\tu64 mac_rx_pfc_pri2_xoff_time;\n\tu64 mac_rx_pfc_pri3_xoff_time;\n\tu64 mac_rx_pfc_pri4_xoff_time;\n\tu64 mac_rx_pfc_pri5_xoff_time;\n\tu64 mac_rx_pfc_pri6_xoff_time;\n\tu64 mac_rx_pfc_pri7_xoff_time;\n\tu64 mac_tx_pause_xoff_time;\n\tu64 mac_rx_pause_xoff_time;\n};\n\nstruct hclge_fec_stats {\n\tu64 rs_corr_blocks;\n\tu64 rs_uncorr_blocks;\n\tu64 rs_error_blocks;\n\tu64 base_r_lane_num;\n\tu64 base_r_corr_blocks;\n\tu64 base_r_uncorr_blocks;\n\tunion {\n\t\tstruct {\n\t\t\tu64 base_r_corr_per_lanes[8];\n\t\t\tu64 base_r_uncorr_per_lanes[8];\n\t\t};\n\t\tu64 per_lanes[16];\n\t};\n};\n\nstruct hclge_rst_stats {\n\tu32 reset_done_cnt;\n\tu32 hw_reset_done_cnt;\n\tu32 pf_rst_cnt;\n\tu32 flr_rst_cnt;\n\tu32 global_rst_cnt;\n\tu32 imp_rst_cnt;\n\tu32 reset_cnt;\n\tu32 reset_fail_cnt;\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct hclge_pg_info {\n\tu8 pg_id;\n\tu8 pg_sch_mode;\n\tu8 tc_bit_map;\n\tu32 bw_limit;\n\tu8 tc_dwrr[8];\n};\n\nstruct hclge_tc_info {\n\tu8 tc_id;\n\tu8 tc_sch_mode;\n\tu8 pgid;\n\tu32 bw_limit;\n};\n\nstruct hclge_tm_info {\n\tu8 num_tc;\n\tu8 num_pg;\n\tu8 pg_dwrr[4];\n\tu8 prio_tc[8];\n\tstruct hclge_pg_info pg_info[4];\n\tstruct hclge_tc_info tc_info[8];\n\tenum hclge_fc_mode fc_mode;\n\tu8 hw_pfc_map;\n\tu8 pfc_en;\n};\n\nstruct hclge_vlan_type_cfg {\n\tu16 rx_ot_fst_vlan_type;\n\tu16 rx_ot_sec_vlan_type;\n\tu16 rx_in_fst_vlan_type;\n\tu16 rx_in_sec_vlan_type;\n\tu16 tx_ot_vlan_type;\n\tu16 tx_in_vlan_type;\n};\n\nstruct hclge_fd_key_cfg {\n\tu8 key_sel;\n\tu8 inner_sipv6_word_en;\n\tu8 inner_dipv6_word_en;\n\tu8 outer_sipv6_word_en;\n\tu8 outer_dipv6_word_en;\n\tu32 tuple_active;\n\tu32 meta_data_active;\n};\n\nstruct hclge_fd_user_def_cfg {\n\tu16 ref_cnt;\n\tu16 offset;\n};\n\nstruct hclge_fd_cfg {\n\tu8 fd_mode;\n\tu16 max_key_length;\n\tu32 rule_num[2];\n\tu16 cnt_num[2];\n\tstruct hclge_fd_key_cfg key_cfg[2];\n\tstruct hclge_fd_user_def_cfg user_def_cfg[3];\n};\n\nstruct hclge_mac_tnl_stats {\n\tu64 time;\n\tu32 status;\n};\n\nstruct hnae3_ae_dev;\n\nstruct hclge_vport;\n\nstruct hnae3_client;\n\nstruct hclge_ptp;\n\nstruct hclge_dev {\n\tstruct pci_dev *pdev;\n\tstruct hnae3_ae_dev *ae_dev;\n\tstruct hclge_hw hw;\n\tstruct hclge_misc_vector misc_vector;\n\tstruct hclge_mac_stats mac_stats;\n\tstruct hclge_fec_stats fec_stats;\n\tlong unsigned int state;\n\tlong unsigned int flr_state;\n\tlong unsigned int last_reset_time;\n\tenum hnae3_reset_type reset_type;\n\tenum hnae3_reset_type reset_level;\n\tlong unsigned int default_reset_request;\n\tlong unsigned int reset_request;\n\tlong unsigned int reset_pending;\n\tstruct hclge_rst_stats rst_stats;\n\tstruct semaphore reset_sem;\n\tu32 fw_version;\n\tu16 num_tqps;\n\tu16 num_req_vfs;\n\tu16 base_tqp_pid;\n\tu16 alloc_rss_size;\n\tu16 vf_rss_size_max;\n\tu16 pf_rss_size_max;\n\tu32 tx_spare_buf_size;\n\tu16 fdir_pf_filter_count;\n\tu16 num_alloc_vport;\n\tnodemask_t numa_node_mask;\n\tu16 rx_buf_len;\n\tu16 num_tx_desc;\n\tu16 num_rx_desc;\n\tu8 hw_tc_map;\n\tenum hclge_fc_mode fc_mode_last_time;\n\tu8 support_sfp_query;\n\tu8 tx_sch_mode;\n\tu8 tc_max;\n\tu8 pfc_max;\n\tu8 default_up;\n\tu8 dcbx_cap;\n\tstruct hclge_tm_info tm_info;\n\tu16 num_msi;\n\tu16 num_msi_left;\n\tu16 num_msi_used;\n\tu16 *vector_status;\n\tint *vector_irq;\n\tu16 num_nic_msi;\n\tu16 num_roce_msi;\n\tlong unsigned int service_timer_period;\n\tlong unsigned int service_timer_previous;\n\tstruct timer_list reset_timer;\n\tstruct delayed_work service_task;\n\tbool cur_promisc;\n\tint num_alloc_vfs;\n\tstruct hclge_comm_tqp *htqp;\n\tstruct hclge_vport *vport;\n\tstruct dentry *hclge_dbgfs;\n\tstruct hnae3_client *nic_client;\n\tstruct hnae3_client *roce_client;\n\tu32 flag;\n\tu32 pkt_buf_size;\n\tu32 tx_buf_size;\n\tu32 dv_buf_size;\n\tu32 mps;\n\tstruct mutex vport_lock;\n\tstruct hclge_vlan_type_cfg vlan_type_cfg;\n\tlong unsigned int vlan_table[16384];\n\tlong unsigned int vf_vlan_full[4];\n\tlong unsigned int vport_config_block[4];\n\tstruct hclge_fd_cfg fd_cfg;\n\tstruct hlist_head fd_rule_list;\n\tspinlock_t fd_rule_lock;\n\tu16 hclge_fd_rule_num;\n\tlong unsigned int serv_processed_cnt;\n\tlong unsigned int last_serv_processed;\n\tlong unsigned int last_rst_scheduled;\n\tlong unsigned int last_mbx_scheduled;\n\tlong unsigned int fd_bmap[64];\n\tenum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;\n\tu8 fd_en;\n\tbool gro_en;\n\tu16 wanted_umv_size;\n\tu16 max_umv_size;\n\tu16 priv_umv_size;\n\tu16 share_umv_size;\n\tu16 used_mc_mac_num;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct hclge_mac_tnl_stats *type;\n\t\t\tconst struct hclge_mac_tnl_stats *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct hclge_mac_tnl_stats *ptr;\n\t\t\tconst struct hclge_mac_tnl_stats *ptr_const;\n\t\t};\n\t\tstruct hclge_mac_tnl_stats buf[8];\n\t} mac_tnl_log;\n\tstruct hclge_ptp *ptp;\n\tstruct devlink *devlink;\n\tstruct hclge_comm_rss_cfg rss_cfg;\n};\n\nstruct hclge_dev_specs_0_cmd {\n\t__le32 rsv0;\n\t__le32 mac_entry_num;\n\t__le32 mng_entry_num;\n\t__le16 rss_ind_tbl_size;\n\t__le16 rss_key_size;\n\t__le16 int_ql_max;\n\tu8 max_non_tso_bd_num;\n\tu8 rsv1;\n\t__le32 max_tm_rate;\n};\n\nstruct hclge_dev_specs_1_cmd {\n\t__le16 max_frm_size;\n\t__le16 max_qset_num;\n\t__le16 max_int_gl;\n\tu8 rsv0[2];\n\t__le16 umv_size;\n\t__le16 mc_mac_size;\n\tu8 rsv1[6];\n\tu8 tnl_num;\n\tu8 hilink_version;\n\tu8 rsv2[4];\n};\n\nstruct hclge_devlink_priv {\n\tstruct hclge_dev *hdev;\n};\n\nstruct hclge_ets_tc_weight_cmd {\n\tu8 tc_weight[8];\n\tu8 weight_offset;\n\tu8 rsvd[15];\n};\n\nstruct hclge_fd_ad_cnt_read_cmd {\n\tu8 rsv0[4];\n\t__le16 index;\n\tu8 rsv1[2];\n\t__le64 cnt;\n\tu8 rsv2[8];\n};\n\nstruct hclge_fd_ad_config_cmd {\n\tu8 stage;\n\tu8 rsv1[3];\n\t__le32 index;\n\t__le64 ad_data;\n\tu8 rsv2[8];\n};\n\nstruct hclge_fd_ad_data {\n\tu16 ad_id;\n\tu8 drop_packet;\n\tu8 forward_to_direct_queue;\n\tu16 queue_id;\n\tu8 use_counter;\n\tu8 counter_id;\n\tu8 use_next_stage;\n\tu8 write_rule_id_to_bd;\n\tu8 next_input_key;\n\tu16 rule_id;\n\tu16 tc_size;\n\tu8 override_tc;\n};\n\nstruct hclge_fd_rule_tuples {\n\tu8 src_mac[6];\n\tu8 dst_mac[6];\n\tu32 src_ip[4];\n\tu32 dst_ip[4];\n\tu16 src_port;\n\tu16 dst_port;\n\tu16 vlan_tag1;\n\tu16 ether_proto;\n\tu16 l2_user_def;\n\tu16 l3_user_def;\n\tu32 l4_user_def;\n\tu8 ip_tos;\n\tu8 ip_proto;\n};\n\nstruct hclge_fd_user_def_info {\n\tenum HCLGE_FD_USER_DEF_LAYER layer;\n\tu16 data;\n\tu16 data_mask;\n\tu16 offset;\n};\n\nstruct hclge_fd_rule {\n\tstruct hlist_node rule_node;\n\tstruct hclge_fd_rule_tuples tuples;\n\tstruct hclge_fd_rule_tuples tuples_mask;\n\tu32 unused_tuple;\n\tu32 flow_type;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu8 tc;\n\t\t} cls_flower;\n\t\tstruct {\n\t\t\tu16 flow_id;\n\t\t} arfs;\n\t\tstruct {\n\t\t\tstruct hclge_fd_user_def_info user_def;\n\t\t} ep;\n\t};\n\tu16 queue_id;\n\tu16 vf_id;\n\tu16 location;\n\tenum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;\n\tenum HCLGE_FD_NODE_STATE state;\n\tu8 action;\n};\n\nstruct hclge_fd_tcam_config_1_cmd {\n\tu8 stage;\n\tu8 xy_sel;\n\tu8 port_info;\n\tu8 rsv1[1];\n\t__le32 index;\n\tu8 entry_vld;\n\tu8 rsv2[7];\n\tu8 tcam_data[8];\n};\n\nstruct hclge_fd_tcam_config_2_cmd {\n\tu8 tcam_data[24];\n};\n\nstruct hclge_fd_tcam_config_3_cmd {\n\tu8 tcam_data[20];\n\tu8 rsv[4];\n};\n\nstruct hclge_fd_user_def_cfg_cmd {\n\t__le16 ol2_cfg;\n\t__le16 l2_cfg;\n\t__le16 ol3_cfg;\n\t__le16 l3_cfg;\n\t__le16 ol4_cfg;\n\t__le16 l4_cfg;\n\tu8 rsv[12];\n};\n\nstruct hclge_func_status_cmd {\n\t__le32 vf_rst_state[4];\n\tu8 pf_state;\n\tu8 mac_id;\n\tu8 rsv1;\n\tu8 pf_cnt_in_mac;\n\tu8 pf_num;\n\tu8 vf_num;\n\tu8 rsv[2];\n};\n\nstruct hclge_get_fd_allocation_cmd {\n\t__le32 stage1_entry_num;\n\t__le32 stage2_entry_num;\n\t__le16 stage1_counter_num;\n\t__le16 stage2_counter_num;\n\tu8 rsv[12];\n};\n\nstruct hclge_get_fd_mode_cmd {\n\tu8 mode;\n\tu8 enable;\n\tu8 rsv[22];\n};\n\nstruct hclge_get_imp_bd_cmd {\n\t__le32 bd_num;\n\tu8 rsv[20];\n};\n\nstruct hclge_hw_blk {\n\tu32 msk;\n\tconst char *name;\n\tint (*config_err_int)(struct hclge_dev *, bool);\n};\n\nstruct hclge_hw_error {\n\tu32 int_msk;\n\tconst char *msg;\n\tenum hnae3_reset_type reset_level;\n};\n\nstruct hclge_hw_module_id {\n\tenum hclge_mod_name_list module_id;\n\tconst char *msg;\n\tvoid (*query_reg_info)(struct hclge_dev *);\n};\n\nstruct hclge_hw_type_id {\n\tenum hclge_err_type_list type_id;\n\tconst char *msg;\n\tbool cause_by_vf;\n};\n\nstruct hclge_link_mode_bmap {\n\tu16 support_bit;\n\tenum ethtool_link_mode_bit_indices link_mode;\n};\n\nstruct hclge_link_status_cmd {\n\tu8 status;\n\tu8 rsv[23];\n};\n\nstruct hclge_mac_ethertype_idx_rd_cmd {\n\tu8 flags;\n\tu8 resp_code;\n\t__le16 vlan_tag;\n\tu8 mac_addr[6];\n\t__le16 index;\n\t__le16 ethter_type;\n\t__le16 egress_port;\n\t__le16 egress_queue;\n\t__le16 rev0;\n\tu8 i_port_bitmap;\n\tu8 i_port_direction;\n\tu8 rev1[2];\n};\n\nstruct hclge_mac_mgr_tbl_entry_cmd {\n\tu8 flags;\n\tu8 resp_code;\n\t__le16 vlan_tag;\n\tu8 mac_addr[6];\n\t__le16 rsv1;\n\t__le16 ethter_type;\n\t__le16 egress_port;\n\t__le16 egress_queue;\n\tu8 sw_port_id_aware;\n\tu8 rsv2;\n\tu8 i_port_bitmap;\n\tu8 i_port_direction;\n\tu8 rsv3[2];\n};\n\nstruct hclge_mac_node {\n\tstruct list_head node;\n\tenum HCLGE_MAC_NODE_STATE state;\n\tu8 mac_addr[6];\n};\n\nstruct hclge_mac_speed_map {\n\tu32 speed_drv;\n\tu32 speed_fw;\n};\n\nstruct hclge_mac_vlan_switch_cmd {\n\tu8 roce_sel;\n\tu8 rsv1[3];\n\t__le32 func_id;\n\tu8 switch_param;\n\tu8 rsv2[3];\n\tu8 param_mask;\n\tu8 rsv3[11];\n};\n\nstruct hclge_mac_vlan_tbl_entry_cmd {\n\tu8 flags;\n\tu8 resp_code;\n\t__le16 vlan_tag;\n\t__le32 mac_addr_hi32;\n\t__le16 mac_addr_lo16;\n\t__le16 rsv1;\n\tu8 entry_type;\n\tu8 mc_mac_en;\n\t__le16 egress_port;\n\t__le16 egress_queue;\n\tu8 rsv2[6];\n};\n\nstruct hclge_mbx_link_mode {\n\t__le16 idx;\n\t__le64 link_mode;\n} __attribute__((packed));\n\nstruct hclge_mbx_link_status {\n\t__le16 link_status;\n\t__le32 speed;\n\t__le16 duplex;\n\tu8 flag;\n} __attribute__((packed));\n\nstruct hclge_mbx_mtu_info {\n\t__le32 mtu;\n};\n\nstruct hclge_mbx_vf_to_pf_cmd;\n\nstruct hclge_respond_to_vf_msg;\n\nstruct hclge_mbx_ops_param {\n\tstruct hclge_vport *vport;\n\tstruct hclge_mbx_vf_to_pf_cmd *req;\n\tstruct hclge_respond_to_vf_msg *resp_msg;\n};\n\nstruct hclge_pf_to_vf_msg {\n\t__le16 code;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 vf_mbx_msg_code;\n\t\t\t__le16 vf_mbx_msg_subcode;\n\t\t\t__le16 resp_status;\n\t\t\tu8 resp_data[8];\n\t\t};\n\t\tstruct {\n\t\t\tu8 msg_data[14];\n\t\t};\n\t};\n};\n\nstruct hclge_mbx_pf_to_vf_cmd {\n\tu8 dest_vfid;\n\tu8 rsv[3];\n\tu8 msg_len;\n\tu8 rsv1;\n\t__le16 match_id;\n\tstruct hclge_pf_to_vf_msg msg;\n};\n\nstruct hclge_mbx_port_base_vlan {\n\t__le16 state;\n\t__le16 vlan_proto;\n\t__le16 qos;\n\t__le16 vlan_tag;\n};\n\nstruct hclge_mbx_vf_queue_depth {\n\t__le16 num_tx_desc;\n\t__le16 num_rx_desc;\n};\n\nstruct hclge_mbx_vf_queue_info {\n\t__le16 num_tqps;\n\t__le16 rss_size;\n\t__le16 rx_buf_len;\n};\n\nstruct hclge_ring_chain_param {\n\tu8 ring_type;\n\tu8 tqp_index;\n\tu8 int_gl_index;\n};\n\nstruct hclge_vf_to_pf_msg {\n\tu8 code;\n\tunion {\n\t\tstruct {\n\t\t\tu8 subcode;\n\t\t\tu8 data[14];\n\t\t};\n\t\tstruct {\n\t\t\tu8 en_bc;\n\t\t\tu8 en_uc;\n\t\t\tu8 en_mc;\n\t\t\tu8 en_limit_promisc;\n\t\t};\n\t\tstruct {\n\t\t\tu8 vector_id;\n\t\t\tu8 ring_num;\n\t\t\tstruct hclge_ring_chain_param param[4];\n\t\t};\n\t};\n};\n\nstruct hclge_mbx_vf_to_pf_cmd {\n\tu8 rsv;\n\tu8 mbx_src_vfid;\n\tu8 mbx_need_resp;\n\tu8 rsv1[1];\n\tu8 msg_len;\n\tu8 rsv2;\n\t__le16 match_id;\n\tstruct hclge_vf_to_pf_msg msg;\n};\n\nstruct hclge_mdio_cfg_cmd {\n\tu8 ctrl_bit;\n\tu8 phyid;\n\tu8 phyad;\n\tu8 rsvd;\n\t__le16 reserve;\n\t__le16 data_wr;\n\t__le16 data_rd;\n\t__le16 sta;\n};\n\nstruct hclge_mod_err_info {\n\tu8 mod_id;\n\tu8 err_num;\n\tu8 rsv[2];\n};\n\nstruct hclge_mod_reg_info;\n\nstruct hclge_mod_reg_common_msg {\n\tenum hclge_opcode_type cmd;\n\tstruct hclge_desc *desc;\n\tu8 bd_num;\n\tbool need_para;\n\tconst struct hclge_mod_reg_info *result_regs;\n\tu16 result_regs_size;\n};\n\nstruct hclge_mod_reg_info {\n\tconst char *reg_name;\n\tbool has_suffix;\n\tu8 reg_offset_group[6];\n\tu8 group_size;\n};\n\nstruct hclge_nq_to_qs_link_cmd {\n\t__le16 nq_id;\n\t__le16 rsvd;\n\t__le16 qset_id;\n};\n\nstruct hclge_pf_res_cmd {\n\t__le16 tqp_num;\n\t__le16 buf_size;\n\t__le16 msixcap_localid_ba_nic;\n\t__le16 msixcap_localid_number_nic;\n\t__le16 pf_intr_vector_number_roce;\n\t__le16 pf_own_fun_number;\n\t__le16 tx_buf_size;\n\t__le16 dv_buf_size;\n\t__le16 ext_tqp_num;\n\tu8 rsv[6];\n};\n\nstruct hclge_pf_rst_done_cmd {\n\tu8 pf_rst_done;\n\tu8 rsv[23];\n};\n\nstruct hclge_pf_rst_sync_cmd {\n\tu8 all_vf_ready;\n\tu8 rsv[23];\n};\n\nstruct hclge_pfc_en_cmd {\n\tu8 tx_rx_en_bitmap;\n\tu8 pri_en_bitmap;\n};\n\nstruct hclge_pg_shapping_cmd {\n\tu8 pg_id;\n\tu8 rsvd[3];\n\t__le32 pg_shapping_para;\n\tu8 flag;\n\tu8 rsvd1[3];\n\t__le32 pg_rate;\n};\n\nstruct hclge_pg_to_pri_link_cmd {\n\tu8 pg_id;\n\tu8 rsvd1[3];\n\tu8 pri_bit_map;\n};\n\nstruct hclge_pg_weight_cmd {\n\tu8 pg_id;\n\tu8 dwrr;\n};\n\nstruct hclge_phy_link_ksetting_0_cmd {\n\t__le32 speed;\n\tu8 duplex;\n\tu8 autoneg;\n\tu8 eth_tp_mdix;\n\tu8 eth_tp_mdix_ctrl;\n\tu8 port;\n\tu8 transceiver;\n\tu8 phy_address;\n\tu8 rsv;\n\t__le32 supported;\n\t__le32 advertising;\n\t__le32 lp_advertising;\n};\n\nstruct hclge_phy_link_ksetting_1_cmd {\n\tu8 master_slave_cfg;\n\tu8 master_slave_state;\n\tu8 rsv[22];\n};\n\nstruct hclge_phy_reg_cmd {\n\t__le16 reg_addr;\n\tu8 rsv0[2];\n\t__le16 reg_val;\n\tu8 rsv1[18];\n};\n\nstruct hclge_waterline {\n\tu32 low;\n\tu32 high;\n};\n\nstruct hclge_priv_buf {\n\tstruct hclge_waterline wl;\n\tu32 buf_size;\n\tu32 tx_buf_size;\n\tu32 enable;\n};\n\nstruct hclge_tc_thrd {\n\tu32 low;\n\tu32 high;\n};\n\nstruct hclge_shared_buf {\n\tstruct hclge_waterline self;\n\tstruct hclge_tc_thrd tc_thrd[8];\n\tu32 buf_size;\n};\n\nstruct hclge_pkt_buf_alloc {\n\tstruct hclge_priv_buf priv_buf[8];\n\tstruct hclge_shared_buf s_buf;\n};\n\nstruct hclge_vlan_info {\n\tu16 vlan_proto;\n\tu16 qos;\n\tu16 vlan_tag;\n};\n\nstruct hclge_port_base_vlan_config {\n\tu16 state;\n\tbool tbl_sta;\n\tstruct hclge_vlan_info vlan_info;\n\tstruct hclge_vlan_info old_vlan_info;\n};\n\nstruct hclge_port_shapping_cmd {\n\t__le32 port_shapping_para;\n\tu8 flag;\n\tu8 rsvd[3];\n\t__le32 port_rate;\n};\n\nstruct hclge_port_vlan_filter_bypass_cmd {\n\tu8 bypass_state;\n\tu8 rsv1[3];\n\tu8 vf_id;\n\tu8 rsv2[19];\n};\n\nstruct hclge_pri_sch_mode_cfg_cmd {\n\tu8 pri_id;\n\tu8 rsvd[3];\n\tu8 sch_mode;\n};\n\nstruct hclge_pri_shapping_cmd {\n\tu8 pri_id;\n\tu8 rsvd[3];\n\t__le32 pri_shapping_para;\n\tu8 flag;\n\tu8 rsvd1[3];\n\t__le32 pri_rate;\n};\n\nstruct hclge_priority_weight_cmd {\n\tu8 pri_id;\n\tu8 dwrr;\n};\n\nstruct hclge_priv_wl {\n\t__le16 high;\n\t__le16 low;\n};\n\nstruct hclge_promisc_cfg_cmd {\n\tu8 promisc;\n\tu8 vf_id;\n\tu8 extend_promisc;\n\tu8 rsv0[21];\n};\n\nstruct hclge_ptp_cycle {\n\tu32 quo;\n\tu32 numer;\n\tu32 den;\n};\n\nstruct hclge_ptp {\n\tstruct hclge_dev *hdev;\n\tstruct ptp_clock *clock;\n\tstruct sk_buff *tx_skb;\n\tlong unsigned int flags;\n\tvoid *io_base;\n\tstruct ptp_clock_info info;\n\tstruct kernel_hwtstamp_config ts_cfg;\n\tspinlock_t lock;\n\tu32 ptp_cfg;\n\tu32 last_tx_seqid;\n\tstruct hclge_ptp_cycle cycle;\n\tlong unsigned int tx_start;\n\tlong unsigned int tx_cnt;\n\tlong unsigned int tx_skipped;\n\tlong unsigned int tx_cleaned;\n\tlong unsigned int last_rx;\n\tlong unsigned int rx_cnt;\n\tlong unsigned int tx_timeout;\n};\n\nstruct hclge_ptp_cfg_cmd {\n\t__le32 cfg;\n\tu8 rsvd[20];\n};\n\nstruct hclge_ptp_int_cmd {\n\tu8 int_en;\n\tu8 rsvd[23];\n};\n\nstruct hclge_qos_pri_map_cmd {\n\tu8 pri0_tc: 4;\n\tu8 pri1_tc: 4;\n\tu8 pri2_tc: 4;\n\tu8 pri3_tc: 4;\n\tu8 pri4_tc: 4;\n\tu8 pri5_tc: 4;\n\tu8 pri6_tc: 4;\n\tu8 pri7_tc: 4;\n\tu8 vlan_pri: 4;\n\tu8 rev: 4;\n};\n\nstruct hclge_qs_sch_mode_cfg_cmd {\n\t__le16 qs_id;\n\tu8 rsvd[2];\n\tu8 sch_mode;\n};\n\nstruct hclge_qs_shapping_cmd {\n\t__le16 qs_id;\n\tu8 rsvd[2];\n\t__le32 qs_shapping_para;\n\tu8 flag;\n\tu8 rsvd1[3];\n\t__le32 qs_rate;\n};\n\nstruct hclge_qs_to_pri_link_cmd {\n\t__le16 qs_id;\n\t__le16 rsvd;\n\tu8 priority;\n\tu8 link_vld;\n};\n\nstruct hclge_qs_weight_cmd {\n\t__le16 qs_id;\n\tu8 dwrr;\n};\n\nstruct hclge_query_fec_stats_cmd {\n\t__le32 rs_fec_corr_blocks;\n\t__le32 rs_fec_uncorr_blocks;\n\t__le32 rs_fec_error_blocks;\n\tu8 base_r_lane_num;\n\tu8 rsv[3];\n\t__le32 base_r_fec_corr_blocks;\n\t__le32 base_r_fec_uncorr_blocks;\n};\n\nstruct hclge_query_ppu_pf_other_int_dfx_cmd {\n\t__le16 over_8bd_no_fe_qid;\n\t__le16 over_8bd_no_fe_vf_id;\n\t__le16 tso_mss_cmp_min_err_qid;\n\t__le16 tso_mss_cmp_min_err_vf_id;\n\t__le16 tso_mss_cmp_max_err_qid;\n\t__le16 tso_mss_cmp_max_err_vf_id;\n\t__le16 tx_rd_fbd_poison_qid;\n\t__le16 tx_rd_fbd_poison_vf_id;\n\t__le16 rx_rd_fbd_poison_qid;\n\t__le16 rx_rd_fbd_poison_vf_id;\n\tu8 rsv[4];\n};\n\nstruct hclge_query_wol_supported_cmd {\n\t__le32 supported_wake_mode;\n\tu8 rsv[20];\n};\n\nstruct hclge_reg_header {\n\tu64 magic_number;\n\tu8 is_vf;\n\tu8 rsv[7];\n};\n\nstruct hclge_reg_tlv {\n\tu16 tag;\n\tu16 len;\n};\n\nstruct hclge_reset_cmd {\n\tu8 mac_func_reset;\n\tu8 fun_reset_vfid;\n\tu8 fun_reset_rcb;\n\tu8 rsv;\n\t__le16 fun_reset_rcb_vqid_start;\n\t__le16 fun_reset_rcb_vqid_num;\n\tu8 fun_reset_rcb_return_status;\n\tu8 rsv1[15];\n};\n\nstruct hclge_reset_tqp_queue_cmd {\n\t__le16 tqp_id;\n\tu8 reset_req;\n\tu8 ready_to_reset;\n\tu8 rsv[20];\n};\n\nstruct hclge_respond_to_vf_msg {\n\tint status;\n\tu8 data[8];\n\tu16 len;\n};\n\nstruct hclge_rx_com_thrd {\n\tstruct hclge_priv_wl com_thrd[4];\n};\n\nstruct hclge_rx_com_wl {\n\tstruct hclge_priv_wl com_wl;\n};\n\nstruct hclge_rx_priv_buff_cmd {\n\t__le16 buf_num[8];\n\t__le16 shared_buf;\n\tu8 rsv[6];\n};\n\nstruct hclge_rx_priv_wl_buf {\n\tstruct hclge_priv_wl tc_wl[4];\n};\n\nstruct hclge_rx_vlan_type_cfg_cmd {\n\t__le16 ot_fst_vlan_type;\n\t__le16 ot_sec_vlan_type;\n\t__le16 in_fst_vlan_type;\n\t__le16 in_sec_vlan_type;\n\tu8 rsv[16];\n};\n\nstruct hclge_rx_vtag_cfg {\n\tbool rx_vlan_offload_en;\n\tbool strip_tag1_en;\n\tbool strip_tag2_en;\n\tbool vlan1_vlan_prionly;\n\tbool vlan2_vlan_prionly;\n\tbool strip_tag1_discard_en;\n\tbool strip_tag2_discard_en;\n};\n\nstruct hclge_set_fd_key_config_cmd {\n\tu8 stage;\n\tu8 key_select;\n\tu8 inner_sipv6_word_en;\n\tu8 inner_dipv6_word_en;\n\tu8 outer_sipv6_word_en;\n\tu8 outer_dipv6_word_en;\n\tu8 rsv1[2];\n\t__le32 tuple_mask;\n\t__le32 meta_data_mask;\n\tu8 rsv2[8];\n};\n\nstruct hclge_set_led_state_cmd {\n\tu8 rsv1[3];\n\tu8 locate_led_config;\n\tu8 rsv2[20];\n};\n\nstruct hclge_sfp_info_bd0_cmd {\n\t__le16 offset;\n\t__le16 read_len;\n\tu8 data[20];\n};\n\nstruct hclge_sfp_info_cmd {\n\t__le32 speed;\n\tu8 query_type;\n\tu8 active_fec;\n\tu8 autoneg;\n\tu8 autoneg_ability;\n\t__le32 speed_ability;\n\t__le32 module_type;\n\tu8 fec_ability;\n\tu8 lane_num;\n\tu8 rsv[6];\n};\n\nstruct hclge_shaper_ir_para {\n\tu8 ir_b;\n\tu8 ir_u;\n\tu8 ir_s;\n};\n\nstruct hclge_speed_bit_map {\n\tu32 speed;\n\tu32 speed_bit;\n};\n\nstruct hclge_sum_err_info {\n\tu8 reset_type;\n\tu8 mod_num;\n\tu8 rsv[2];\n};\n\nstruct hclge_tm_nodes_cmd {\n\tu8 pg_base_id;\n\tu8 pri_base_id;\n\t__le16 qset_base_id;\n\t__le16 queue_base_id;\n\tu8 pg_num;\n\tu8 pri_num;\n\t__le16 qset_num;\n\t__le16 queue_num;\n};\n\nstruct hclge_tm_shaper_para {\n\tu32 rate;\n\tu8 ir_b;\n\tu8 ir_u;\n\tu8 ir_s;\n\tu8 bs_b;\n\tu8 bs_s;\n\tu8 flag;\n};\n\nstruct hclge_tqp_map_cmd {\n\t__le16 tqp_id;\n\tu8 tqp_vf;\n\tu8 tqp_flag;\n\t__le16 tqp_vid;\n\tu8 rsv[18];\n};\n\nstruct hclge_tqp_tx_queue_tc_cmd {\n\t__le16 queue_id;\n\t__le16 rsvd;\n\tu8 tc_id;\n\tu8 rev[3];\n};\n\nstruct hclge_tx_buff_alloc_cmd {\n\t__le16 tx_pkt_buff[8];\n\tu8 tx_buff_rsv[8];\n};\n\nstruct hclge_tx_vlan_type_cfg_cmd {\n\t__le16 ot_vlan_type;\n\t__le16 in_vlan_type;\n\tu8 rsv[20];\n};\n\nstruct hclge_tx_vtag_cfg {\n\tbool accept_tag1;\n\tbool accept_untag1;\n\tbool accept_tag2;\n\tbool accept_untag2;\n\tbool insert_tag1_en;\n\tbool insert_tag2_en;\n\tu16 default_tag1;\n\tu16 default_tag2;\n\tbool tag_shift_mode_en;\n};\n\nstruct hclge_type_reg_err_info {\n\tu8 type_id;\n\tu8 reg_num;\n\tu8 rsv[2];\n\tu32 hclge_reg[256];\n};\n\nstruct hclge_umv_spc_alc_cmd {\n\tu8 allocate;\n\tu8 rsv1[3];\n\t__le32 space_size;\n\tu8 rsv2[16];\n};\n\nstruct hclge_vf_info {\n\tint link_state;\n\tu8 mac[6];\n\tu32 spoofchk;\n\tu32 max_tx_rate;\n\tu32 trusted;\n\tu8 request_uc_en;\n\tu8 request_mc_en;\n\tu8 request_bc_en;\n};\n\nstruct hclge_vf_rst_cmd {\n\tu8 dest_vfid;\n\tu8 vf_rst;\n\tu8 rsv[22];\n};\n\nstruct hclge_vf_vlan_cfg {\n\tu8 mbx_cmd;\n\tu8 subcode;\n\tunion {\n\t\tstruct {\n\t\t\tu8 is_kill;\n\t\t\t__le16 vlan;\n\t\t\t__le16 proto;\n\t\t} __attribute__((packed));\n\t\tu8 enable;\n\t};\n};\n\nstruct hclge_vlan_filter_ctrl_cmd {\n\tu8 vlan_type;\n\tu8 vlan_fe;\n\tu8 rsv1[2];\n\tu8 vf_id;\n\tu8 rsv2[19];\n};\n\nstruct hclge_vlan_filter_pf_cfg_cmd {\n\tu8 vlan_offset;\n\tu8 vlan_cfg;\n\tu8 rsv[2];\n\tu8 vlan_offset_bitmap[20];\n};\n\nstruct hclge_vlan_filter_vf_cfg_cmd {\n\t__le16 vlan_id;\n\tu8 resp_code;\n\tu8 rsv;\n\tu8 vlan_cfg;\n\tu8 rsv1[3];\n\tu8 vf_bitmap[16];\n};\n\nstruct hnae3_tc_info {\n\tu8 prio_tc[8];\n\tu16 tqp_count[8];\n\tu16 tqp_offset[8];\n\tu8 max_tc;\n\tu8 num_tc;\n\tbool mqprio_active;\n\tbool mqprio_destroy;\n\tbool dcb_ets_active;\n};\n\nstruct hnae3_dcb_ops;\n\nstruct hnae3_knic_private_info {\n\tstruct net_device *netdev;\n\tu16 rss_size;\n\tu16 req_rss_size;\n\tu16 rx_buf_len;\n\tu16 num_tx_desc;\n\tu16 num_rx_desc;\n\tu32 tx_spare_buf_size;\n\tstruct hnae3_tc_info tc_info;\n\tu8 tc_map_mode;\n\tu8 dscp_app_cnt;\n\tu8 dscp_prio[64];\n\tu16 num_tqps;\n\tstruct hnae3_queue **tqp;\n\tconst struct hnae3_dcb_ops *dcb_ops;\n\tu16 int_rl_setting;\n\tvoid *io_base;\n};\n\nstruct hnae3_roce_private_info {\n\tstruct net_device *netdev;\n\tvoid *roce_io_base;\n\tvoid *roce_mem_base;\n\tint base_vector;\n\tint num_vectors;\n\tlong unsigned int reset_state;\n\tlong unsigned int instance_state;\n\tlong unsigned int state;\n};\n\nstruct hnae3_handle {\n\tstruct hnae3_client *client;\n\tstruct pci_dev *pdev;\n\tvoid *priv;\n\tstruct hnae3_ae_algo *ae_algo;\n\tu64 flags;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct hnae3_knic_private_info kinfo;\n\t\tstruct hnae3_roce_private_info rinfo;\n\t};\n\tnodemask_t numa_node_mask;\n\tenum hnae3_port_base_vlan_state port_base_vlan_state;\n\tu8 netdev_flags;\n\tstruct dentry *hnae3_dbgfs;\n\tu32 msg_enable;\n\tlong unsigned int supported_pflags;\n\tlong unsigned int priv_flags;\n};\n\nstruct hclge_vport {\n\tu16 alloc_tqps;\n\tu16 qs_offset;\n\tu32 bw_limit;\n\tu8 dwrr;\n\tbool req_vlan_fltr_en;\n\tbool cur_vlan_fltr_en;\n\tlong unsigned int vlan_del_fail_bmap[64];\n\tstruct hclge_port_base_vlan_config port_base_vlan_cfg;\n\tstruct hclge_tx_vtag_cfg txvlan_cfg;\n\tstruct hclge_rx_vtag_cfg rxvlan_cfg;\n\tu16 used_umv_num;\n\tu16 vport_id;\n\tstruct hclge_dev *back;\n\tstruct hnae3_handle nic;\n\tstruct hnae3_handle roce;\n\tlong unsigned int state;\n\tlong unsigned int need_notify;\n\tlong unsigned int last_active_jiffies;\n\tu32 mps;\n\tstruct hclge_vf_info vf_info;\n\tu8 overflow_promisc_flags;\n\tu8 last_promisc_flags;\n\tspinlock_t mac_list_lock;\n\tstruct list_head uc_mac_list;\n\tstruct list_head mc_mac_list;\n\tstruct list_head vlan_list;\n};\n\nstruct hclge_vport_vlan_cfg {\n\tstruct list_head node;\n\tint hd_tbl_status;\n\tu16 vlan_id;\n};\n\nstruct hclge_vport_vtag_rx_cfg_cmd {\n\tu8 vport_vlan_cfg;\n\tu8 vf_offset;\n\tu8 rsv1[6];\n\tu8 vf_bitmap[8];\n\tu8 rsv2[8];\n};\n\nstruct hclge_vport_vtag_tx_cfg_cmd {\n\tu8 vport_vlan_cfg;\n\tu8 vf_offset;\n\tu8 rsv1[2];\n\t__le16 def_vlan_tag1;\n\t__le16 def_vlan_tag2;\n\tu8 vf_bitmap[8];\n\tu8 rsv2[8];\n};\n\nstruct hclge_wol_cfg_cmd {\n\t__le32 wake_on_lan_mode;\n\tu8 sopass[6];\n\tu8 sopass_size;\n\tu8 rsv[13];\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hdmi_any_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n};\n\nstruct hdmi_audio_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned char channels;\n\tenum hdmi_audio_coding_type coding_type;\n\tenum hdmi_audio_sample_size sample_size;\n\tenum hdmi_audio_sample_frequency sample_frequency;\n\tenum hdmi_audio_coding_type_ext coding_type_ext;\n\tunsigned char channel_allocation;\n\tunsigned char level_shift_value;\n\tbool downmix_inhibit;\n};\n\nstruct hdmi_avi_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tbool itc;\n\tunsigned char pixel_repeat;\n\tenum hdmi_colorspace colorspace;\n\tenum hdmi_scan_mode scan_mode;\n\tenum hdmi_colorimetry colorimetry;\n\tenum hdmi_picture_aspect picture_aspect;\n\tenum hdmi_active_aspect active_aspect;\n\tenum hdmi_extended_colorimetry extended_colorimetry;\n\tenum hdmi_quantization_range quantization_range;\n\tenum hdmi_nups nups;\n\tunsigned char video_code;\n\tenum hdmi_ycc_quantization_range ycc_quantization_range;\n\tenum hdmi_content_type content_type;\n\tshort unsigned int top_bar;\n\tshort unsigned int bottom_bar;\n\tshort unsigned int left_bar;\n\tshort unsigned int right_bar;\n};\n\nstruct hdmi_drm_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_eotf eotf;\n\tenum hdmi_metadata_type metadata_type;\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} white_point;\n\tu16 max_display_mastering_luminance;\n\tu16 min_display_mastering_luminance;\n\tu16 max_cll;\n\tu16 max_fall;\n};\n\nstruct hdmi_spd_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tchar vendor[8];\n\tchar product[16];\n\tenum hdmi_spd_sdi sdi;\n};\n\nstruct hdmi_vendor_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned int oui;\n\tu8 vic;\n\tenum hdmi_3d_structure s3d_struct;\n\tunsigned int s3d_ext_data;\n};\n\nunion hdmi_vendor_any_infoframe {\n\tstruct {\n\t\tenum hdmi_infoframe_type type;\n\t\tunsigned char version;\n\t\tunsigned char length;\n\t\tunsigned int oui;\n\t} any;\n\tstruct hdmi_vendor_infoframe hdmi;\n};\n\nunion hdmi_infoframe {\n\tstruct hdmi_any_infoframe any;\n\tstruct hdmi_avi_infoframe avi;\n\tstruct hdmi_spd_infoframe spd;\n\tunion hdmi_vendor_any_infoframe vendor;\n\tstruct hdmi_audio_infoframe audio;\n\tstruct hdmi_drm_infoframe drm;\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct heartbeat_trig_data {\n\tstruct led_classdev *led_cdev;\n\tunsigned int phase;\n\tunsigned int period;\n\tstruct timer_list timer;\n\tunsigned int invert;\n};\n\nstruct hfpll_data {\n\tu32 mode_reg;\n\tu32 l_reg;\n\tu32 m_reg;\n\tu32 n_reg;\n\tu32 user_reg;\n\tu32 droop_reg;\n\tu32 config_reg;\n\tu32 status_reg;\n\tu8 lock_bit;\n\tu32 l_val;\n\tu32 droop_val;\n\tu32 config_val;\n\tu32 user_val;\n\tu32 user_vco_mask;\n\tlong unsigned int low_vco_max_rate;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[12];\n};\n\nstruct hisi_clock_data;\n\nstruct hisi_reset_controller;\n\nstruct hi3519_crg_data {\n\tstruct hisi_clock_data *clk_data;\n\tstruct hisi_reset_controller *rstc;\n};\n\nstruct hi3559av100_clk_pll {\n\tstruct clk_hw hw;\n\tu32 id;\n\tvoid *ctrl_reg1;\n\tu8 frac_shift;\n\tu8 frac_width;\n\tu8 postdiv1_shift;\n\tu8 postdiv1_width;\n\tu8 postdiv2_shift;\n\tu8 postdiv2_width;\n\tvoid *ctrl_reg2;\n\tu8 fbdiv_shift;\n\tu8 fbdiv_width;\n\tu8 refdiv_shift;\n\tu8 refdiv_width;\n};\n\nstruct hi3559av100_pll_clock {\n\tu32 id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst u32 ctrl_reg1;\n\tconst u8 frac_shift;\n\tconst u8 frac_width;\n\tconst u8 postdiv1_shift;\n\tconst u8 postdiv1_width;\n\tconst u8 postdiv2_shift;\n\tconst u8 postdiv2_width;\n\tconst u32 ctrl_reg2;\n\tconst u8 fbdiv_shift;\n\tconst u8 fbdiv_width;\n\tconst u8 refdiv_shift;\n\tconst u8 refdiv_width;\n};\n\nstruct hi3660_chan_info {\n\tunsigned int dst_irq;\n\tunsigned int ack_irq;\n};\n\nstruct hi3660_mbox {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct mbox_chan chan[32];\n\tstruct hi3660_chan_info mchan[32];\n\tstruct mbox_controller controller;\n};\n\nstruct hi3660_pcie_phy {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct regmap *crgctrl;\n\tstruct regmap *sysctrl;\n\tstruct clk *apb_sys_clk;\n\tstruct clk *apb_phy_clk;\n\tstruct clk *phy_ref_clk;\n\tstruct clk *aclk;\n\tstruct clk *aux_clk;\n};\n\nstruct hi3660_reset_controller {\n\tstruct reset_controller_dev rst;\n\tstruct regmap *map;\n};\n\nstruct hi3660_stub_clk {\n\tunsigned int id;\n\tstruct clk_hw hw;\n\tunsigned int cmd;\n\tunsigned int msg[8];\n\tunsigned int rate;\n};\n\nstruct hi3660_stub_clk_chan {\n\tstruct mbox_client cl;\n\tstruct mbox_chan *mbox;\n};\n\nstruct hi3798cv200_priv {\n\tstruct clk *sample_clk;\n\tstruct clk *drive_clk;\n};\n\nstruct hi6220_clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu32 mask;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct hi6220_divider_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu32 mask_bit;\n\tconst char *alias;\n};\n\nstruct hi6220_mbox_chan;\n\nstruct hi6220_mbox {\n\tstruct device *dev;\n\tint irq;\n\tbool tx_irq_mode;\n\tvoid *ipc;\n\tvoid *base;\n\tunsigned int chan_num;\n\tstruct hi6220_mbox_chan *mchan;\n\tvoid *irq_map_chan[32];\n\tstruct mbox_chan *chan;\n\tstruct mbox_controller controller;\n};\n\nstruct hi6220_mbox_chan {\n\tunsigned int dir;\n\tunsigned int dst_irq;\n\tunsigned int ack_irq;\n\tunsigned int slot;\n\tstruct hi6220_mbox *parent;\n};\n\nstruct hi6220_mbox_msg {\n\tunsigned char type;\n\tunsigned char cmd;\n\tunsigned char obj;\n\tunsigned char src;\n\tunsigned char para[4];\n};\n\nunion hi6220_mbox_data {\n\tunsigned int data[8];\n\tstruct hi6220_mbox_msg msg;\n};\n\nstruct hi6220_priv {\n\tstruct regmap *reg;\n\tstruct device *dev;\n};\n\nstruct hi6220_reset_data {\n\tstruct reset_controller_dev rc_dev;\n\tstruct regmap *regmap;\n};\n\nstruct hi6220_stub_clk {\n\tu32 id;\n\tstruct device *dev;\n\tstruct clk_hw hw;\n\tstruct regmap *dfs_map;\n\tstruct mbox_client cl;\n\tstruct mbox_chan *mbox;\n};\n\nstruct hi6421_pmic {\n\tstruct regmap *regmap;\n};\n\nstruct hi6421v530_regulator_info {\n\tstruct regulator_desc rdesc;\n\tu8 mode_mask;\n};\n\nstruct hi655x_pmic;\n\nstruct hi655x_clk {\n\tstruct hi655x_pmic *hi655x;\n\tstruct clk_hw clk_hw;\n};\n\nstruct hi655x_pmic {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct gpio_desc *gpio;\n\tunsigned int ver;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct hi655x_regulator {\n\tunsigned int disable_reg;\n\tunsigned int status_reg;\n\tstruct regulator_desc rdesc;\n};\n\nstruct hib_bio_batch {\n\tatomic_t count;\n\twait_queue_head_t wait;\n\tblk_status_t error;\n\tstruct blk_plug plug;\n};\n\nstruct hid_class_descriptor {\n\t__u8 bDescriptorType;\n\t__le16 wDescriptorLength;\n} __attribute__((packed));\n\nstruct hid_collection {\n\tint parent_idx;\n\tunsigned int type;\n\tunsigned int usage;\n\tunsigned int level;\n};\n\nstruct hid_control_fifo {\n\tunsigned char dir;\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_debug_list {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tchar *type;\n\t\t\tconst char *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tchar *ptr;\n\t\t\tconst char *ptr_const;\n\t\t};\n\t\tchar buf[0];\n\t} hid_debug_fifo;\n\tstruct fasync_struct *fasync;\n\tstruct hid_device *hdev;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct hid_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdHID;\n\t__u8 bCountryCode;\n\t__u8 bNumDescriptors;\n\tstruct hid_class_descriptor rpt_desc;\n\tstruct hid_class_descriptor opt_descs[0];\n} __attribute__((packed));\n\nstruct hid_report_enum {\n\tunsigned int numbered;\n\tstruct list_head report_list;\n\tstruct hid_report *report_id_hash[256];\n};\n\nstruct hid_driver;\n\nstruct hid_ll_driver;\n\nstruct hid_field;\n\nstruct hid_usage;\n\nstruct hid_device {\n\tconst __u8 *dev_rdesc;\n\tconst __u8 *bpf_rdesc;\n\tconst __u8 *rdesc;\n\tunsigned int dev_rsize;\n\tunsigned int bpf_rsize;\n\tunsigned int rsize;\n\tunsigned int collection_size;\n\tstruct hid_collection *collection;\n\tunsigned int maxcollection;\n\tunsigned int maxapplication;\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\t__u32 version;\n\tenum hid_type type;\n\tunsigned int country;\n\tstruct hid_report_enum report_enum[3];\n\tstruct work_struct led_work;\n\tstruct semaphore driver_input_lock;\n\tstruct device dev;\n\tstruct hid_driver *driver;\n\tvoid *devres_group_id;\n\tconst struct hid_ll_driver *ll_driver;\n\tstruct mutex ll_open_lock;\n\tunsigned int ll_open_count;\n\tlong unsigned int status;\n\tunsigned int claimed;\n\tunsigned int quirks;\n\tunsigned int initial_quirks;\n\tbool io_started;\n\tstruct list_head inputs;\n\tvoid *hiddev;\n\tvoid *hidraw;\n\tchar name[128];\n\tchar phys[64];\n\tchar uniq[64];\n\tvoid *driver_data;\n\tint (*ff_init)(struct hid_device *);\n\tint (*hiddev_connect)(struct hid_device *, unsigned int);\n\tvoid (*hiddev_disconnect)(struct hid_device *);\n\tvoid (*hiddev_hid_event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*hiddev_report_event)(struct hid_device *, struct hid_report *);\n\tshort unsigned int debug;\n\tstruct dentry *debug_dir;\n\tstruct dentry *debug_rdesc;\n\tstruct dentry *debug_events;\n\tstruct list_head debug_list;\n\tspinlock_t debug_list_lock;\n\twait_queue_head_t debug_wait;\n\tstruct kref ref;\n\tunsigned int id;\n};\n\nstruct hid_device_id {\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hid_report_id;\n\nstruct hid_usage_id;\n\nstruct hid_input;\n\nstruct hid_driver {\n\tconst char *name;\n\tconst struct hid_device_id *id_table;\n\tstruct list_head dyn_list;\n\tspinlock_t dyn_lock;\n\tbool (*match)(struct hid_device *, bool);\n\tint (*probe)(struct hid_device *, const struct hid_device_id *);\n\tvoid (*remove)(struct hid_device *);\n\tconst struct hid_report_id *report_table;\n\tint (*raw_event)(struct hid_device *, struct hid_report *, u8 *, int);\n\tconst struct hid_usage_id *usage_table;\n\tint (*event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*report)(struct hid_device *, struct hid_report *);\n\tconst __u8 * (*report_fixup)(struct hid_device *, __u8 *, unsigned int *);\n\tint (*input_mapping)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_mapped)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_configured)(struct hid_device *, struct hid_input *);\n\tvoid (*feature_mapping)(struct hid_device *, struct hid_field *, struct hid_usage *);\n\tint (*suspend)(struct hid_device *, pm_message_t);\n\tint (*resume)(struct hid_device *);\n\tint (*reset_resume)(struct hid_device *);\n\tvoid (*on_hid_hw_open)(struct hid_device *);\n\tvoid (*on_hid_hw_close)(struct hid_device *);\n\tstruct device_driver driver;\n};\n\nstruct hid_dynid {\n\tstruct list_head list;\n\tstruct hid_device_id id;\n};\n\nstruct hid_field {\n\tunsigned int physical;\n\tunsigned int logical;\n\tunsigned int application;\n\tstruct hid_usage *usage;\n\tunsigned int maxusage;\n\tunsigned int flags;\n\tunsigned int report_offset;\n\tunsigned int report_size;\n\tunsigned int report_count;\n\tunsigned int report_type;\n\t__s32 *value;\n\t__s32 *new_value;\n\t__s32 *usages_priorities;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tbool ignored;\n\tstruct hid_report *report;\n\tunsigned int index;\n\tstruct hid_input *hidinput;\n\t__u16 dpad;\n\tunsigned int slot_idx;\n};\n\nstruct hid_field_entry {\n\tstruct list_head list;\n\tstruct hid_field *field;\n\tunsigned int index;\n\t__s32 priority;\n};\n\nstruct hid_global {\n\tunsigned int usage_page;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tunsigned int report_id;\n\tunsigned int report_size;\n\tunsigned int report_count;\n};\n\nstruct hid_input {\n\tstruct list_head list;\n\tstruct hid_report *report;\n\tstruct input_dev *input;\n\tconst char *name;\n\tstruct list_head reports;\n\tunsigned int application;\n\tbool registered;\n};\n\nstruct hid_item {\n\tunsigned int format;\n\t__u8 size;\n\t__u8 type;\n\t__u8 tag;\n\tunion {\n\t\t__u8 u8;\n\t\t__s8 s8;\n\t\t__u16 u16;\n\t\t__s16 s16;\n\t\t__u32 u32;\n\t\t__s32 s32;\n\t\tconst __u8 *longdata;\n\t} data;\n};\n\nstruct hid_ll_driver {\n\tint (*start)(struct hid_device *);\n\tvoid (*stop)(struct hid_device *);\n\tint (*open)(struct hid_device *);\n\tvoid (*close)(struct hid_device *);\n\tint (*power)(struct hid_device *, int);\n\tint (*parse)(struct hid_device *);\n\tvoid (*request)(struct hid_device *, struct hid_report *, int);\n\tint (*wait)(struct hid_device *);\n\tint (*raw_request)(struct hid_device *, unsigned char, __u8 *, size_t, unsigned char, int);\n\tint (*output_report)(struct hid_device *, __u8 *, size_t);\n\tint (*idle)(struct hid_device *, int, int, int);\n\tbool (*may_wakeup)(struct hid_device *);\n\tunsigned int max_buffer_size;\n};\n\nstruct hid_local {\n\tunsigned int usage[12288];\n\tu8 usage_size[12288];\n\tunsigned int collection_index[12288];\n\tunsigned int usage_index;\n\tunsigned int usage_minimum;\n\tunsigned int delimiter_depth;\n\tunsigned int delimiter_branch;\n};\n\nstruct hid_output_fifo {\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_parser {\n\tstruct hid_global global;\n\tstruct hid_global global_stack[4];\n\tunsigned int global_stack_ptr;\n\tstruct hid_local local;\n\tunsigned int *collection_stack;\n\tunsigned int collection_stack_ptr;\n\tunsigned int collection_stack_size;\n\tstruct hid_device *device;\n\tunsigned int scan_flags;\n};\n\nstruct hid_report {\n\tstruct list_head list;\n\tstruct list_head hidinput_list;\n\tstruct list_head field_entry_list;\n\tunsigned int id;\n\tenum hid_report_type type;\n\tunsigned int application;\n\tstruct hid_field *field[256];\n\tstruct hid_field_entry *field_entries;\n\tunsigned int maxfield;\n\tunsigned int size;\n\tstruct hid_device *device;\n\tbool tool_active;\n\tunsigned int tool;\n};\n\nstruct hid_report_id {\n\t__u32 report_type;\n};\n\nstruct hid_usage {\n\tunsigned int hid;\n\tunsigned int collection_index;\n\tunsigned int usage_index;\n\t__s8 resolution_multiplier;\n\t__s8 wheel_factor;\n\t__u16 code;\n\t__u8 type;\n\t__s16 hat_min;\n\t__s16 hat_max;\n\t__s16 hat_dir;\n\t__s16 wheel_accumulated;\n};\n\nstruct hid_usage_entry {\n\tunsigned int page;\n\tunsigned int usage;\n\tconst char *description;\n};\n\nstruct hid_usage_id {\n\t__u32 usage_hid;\n\t__u32 usage_type;\n\t__u32 usage_code;\n};\n\nstruct hiddev {\n\tint minor;\n\tint exist;\n\tint open;\n\tstruct mutex existancelock;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tbool initialized;\n};\n\nstruct hidma_dev;\n\nstruct hidma_desc;\n\nstruct hidma_chan {\n\tbool paused;\n\tbool allocated;\n\tchar dbg_name[16];\n\tu32 dma_sig;\n\tdma_cookie_t last_success;\n\tstruct hidma_dev *dmadev;\n\tstruct hidma_desc *running;\n\tstruct dma_chan chan;\n\tstruct list_head free;\n\tstruct list_head prepared;\n\tstruct list_head queued;\n\tstruct list_head active;\n\tstruct list_head completed;\n\tspinlock_t lock;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct hidma_mgmt_dev;\n\nstruct hidma_chan_attr {\n\tstruct hidma_mgmt_dev *mdev;\n\tint index;\n\tstruct kobj_attribute attr;\n};\n\nstruct hidma_desc {\n\tstruct dma_async_tx_descriptor desc;\n\tstruct list_head node;\n\tu32 tre_ch;\n};\n\nstruct hidma_lldev;\n\nstruct hidma_dev {\n\tint irq;\n\tint chidx;\n\tu32 nr_descriptors;\n\tint msi_virqbase;\n\tstruct hidma_lldev *lldev;\n\tvoid *dev_trca;\n\tstruct resource *trca_resource;\n\tvoid *dev_evca;\n\tstruct resource *evca_resource;\n\tspinlock_t lock;\n\tstruct dma_device ddev;\n\tstruct dentry *debugfs;\n\tstruct device_attribute *chid_attrs;\n\tstruct tasklet_struct task;\n};\n\nstruct hidma_tre;\n\nstruct hidma_lldev {\n\tbool msi_support;\n\tbool initialized;\n\tu8 trch_state;\n\tu8 evch_state;\n\tu8 chidx;\n\tu32 nr_tres;\n\tspinlock_t lock;\n\tstruct hidma_tre *trepool;\n\tstruct device *dev;\n\tvoid *trca;\n\tvoid *evca;\n\tstruct hidma_tre **pending_tre_list;\n\tatomic_t pending_tre_count;\n\tvoid *tre_ring;\n\tdma_addr_t tre_dma;\n\tu32 tre_ring_size;\n\tu32 tre_processed_off;\n\tvoid *evre_ring;\n\tdma_addr_t evre_dma;\n\tu32 evre_ring_size;\n\tu32 evre_processed_off;\n\tu32 tre_write_offset;\n\tstruct tasklet_struct task;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct hidma_tre **type;\n\t\t\tconst struct hidma_tre **const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct hidma_tre **ptr;\n\t\t\tstruct hidma_tre * const *ptr_const;\n\t\t};\n\t\tstruct hidma_tre *buf[0];\n\t} handoff_fifo;\n};\n\nstruct hidma_mgmt_dev {\n\tu8 hw_version_major;\n\tu8 hw_version_minor;\n\tu32 max_wr_xactions;\n\tu32 max_rd_xactions;\n\tu32 max_write_request;\n\tu32 max_read_request;\n\tu32 dma_channels;\n\tu32 chreset_timeout_cycles;\n\tu32 hw_version;\n\tu32 *priority;\n\tu32 *weight;\n\tvoid *virtaddr;\n\tresource_size_t addrsize;\n\tstruct kobject **chroots;\n\tstruct platform_device *pdev;\n};\n\nstruct hidma_mgmt_fileinfo {\n\tchar *name;\n\tint mode;\n\tint (*get)(struct hidma_mgmt_dev *);\n\tint (*set)(struct hidma_mgmt_dev *, u64);\n};\n\nstruct hidma_tre {\n\tatomic_t allocated;\n\tbool queued;\n\tu16 status;\n\tu32 idx;\n\tu32 dma_sig;\n\tconst char *dev_name;\n\tvoid (*callback)(void *);\n\tvoid *data;\n\tstruct hidma_lldev *lldev;\n\tu32 tre_local[9];\n\tu32 tre_index;\n\tu32 int_flags;\n\tu8 err_info;\n\tu8 err_code;\n};\n\nstruct hidraw {\n\tunsigned int minor;\n\tint exist;\n\tint open;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct device *dev;\n\tspinlock_t list_lock;\n\tstruct list_head list;\n};\n\nstruct hisi_clock_data {\n\tstruct clk_onecell_data clk_data;\n\tvoid *base;\n};\n\nstruct hisi_crg_funcs;\n\nstruct hisi_crg_dev {\n\tstruct hisi_clock_data *clk_data;\n\tstruct hisi_reset_controller *rstc;\n\tconst struct hisi_crg_funcs *funcs;\n};\n\nstruct hisi_crg_funcs {\n\tstruct hisi_clock_data * (*register_clks)(struct platform_device *);\n\tvoid (*unregister_clks)(struct platform_device *);\n};\n\nstruct hisi_ddrc_pmu_regs {\n\tu32 event_cnt;\n\tu32 event_ctrl;\n\tu32 event_type;\n\tu32 perf_ctrl;\n\tu32 perf_ctrl_en;\n\tu32 int_mask;\n\tu32 int_clear;\n\tu32 int_status;\n};\n\nstruct hisi_divider_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tstruct clk_div_table *table;\n\tconst char *alias;\n};\n\nstruct hisi_fixed_factor_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int mult;\n\tlong unsigned int div;\n\tlong unsigned int flags;\n};\n\nstruct hisi_fixed_rate_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int fixed_rate;\n};\n\nstruct hisi_gate_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 bit_idx;\n\tu8 gate_flags;\n\tconst char *alias;\n};\n\nstruct sas_ha_struct {\n\tstruct list_head defer_q;\n\tstruct mutex drain_mutex;\n\tlong unsigned int state;\n\tspinlock_t lock;\n\tint eh_active;\n\twait_queue_head_t eh_wait_q;\n\tstruct list_head eh_dev_q;\n\tstruct mutex disco_mutex;\n\tstruct Scsi_Host *shost;\n\tchar *sas_ha_name;\n\tstruct device *dev;\n\tstruct workqueue_struct *event_q;\n\tstruct workqueue_struct *disco_q;\n\tu8 *sas_addr;\n\tu8 hashed_sas_addr[3];\n\tspinlock_t phy_port_lock;\n\tstruct asd_sas_phy **sas_phy;\n\tstruct asd_sas_port **sas_port;\n\tint num_phys;\n\tint strict_wide_ports;\n\tvoid *lldd_ha;\n\tstruct list_head eh_done_q;\n\tstruct list_head eh_ata_q;\n\tint event_thres;\n};\n\nstruct hisi_hba;\n\nstruct hisi_sas_cq {\n\tstruct hisi_hba *hisi_hba;\n\tconst struct cpumask *irq_mask;\n\tint rd_point;\n\tint id;\n\tint irq_no;\n\tspinlock_t poll_lock;\n};\n\nstruct hisi_sas_dq {\n\tstruct hisi_hba *hisi_hba;\n\tstruct list_head list;\n\tspinlock_t lock;\n\tint wr_point;\n\tint id;\n};\n\nstruct sas_identify {\n\tenum sas_device_type device_type;\n\tenum sas_protocol initiator_port_protocols;\n\tenum sas_protocol target_port_protocols;\n\tu64 sas_address;\n\tu8 phy_identifier;\n};\n\nstruct hisi_sas_debugfs_fifo {\n\tu32 signal_sel;\n\tu32 dump_msk;\n\tu32 dump_mode;\n\tu32 trigger;\n\tu32 trigger_msk;\n\tu32 trigger_mode;\n\tu32 rd_data[32];\n};\n\nstruct hisi_sas_port;\n\nstruct hisi_sas_phy {\n\tstruct work_struct works[3];\n\tstruct hisi_hba *hisi_hba;\n\tstruct hisi_sas_port *port;\n\tstruct asd_sas_phy sas_phy;\n\tstruct sas_identify identify;\n\tstruct completion *reset_completion;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\tu64 port_id;\n\tu64 frame_rcvd_size;\n\tu8 frame_rcvd[32];\n\tu8 phy_attached;\n\tu8 in_reset;\n\tu8 reserved[2];\n\tu32 phy_type;\n\tu32 code_violation_err_count;\n\tenum sas_linkrate minimum_linkrate;\n\tenum sas_linkrate maximum_linkrate;\n\tint enable;\n\tint wait_phyup_cnt;\n\tatomic_t down_cnt;\n\tstruct hisi_sas_debugfs_fifo fifo;\n};\n\nstruct hisi_sas_port {\n\tstruct asd_sas_port sas_port;\n\tu8 port_attached;\n\tu8 id;\n};\n\nstruct hisi_sas_device {\n\tstruct hisi_hba *hisi_hba;\n\tstruct domain_device *sas_device;\n\tstruct completion *completion;\n\tstruct hisi_sas_dq *dq;\n\tstruct list_head list;\n\tenum sas_device_type dev_type;\n\tenum dev_status dev_status;\n\tint device_id;\n\tint sata_idx;\n\tspinlock_t lock;\n};\n\nstruct hisi_sas_debugfs_regs {\n\tstruct hisi_hba *hisi_hba;\n\tu32 *data;\n};\n\nstruct hisi_sas_debugfs_port {\n\tstruct hisi_sas_phy *phy;\n\tu32 *data;\n};\n\nstruct hisi_sas_debugfs_cq {\n\tstruct hisi_sas_cq *cq;\n\tvoid *complete_hdr;\n};\n\nstruct hisi_sas_cmd_hdr;\n\nstruct hisi_sas_debugfs_dq {\n\tstruct hisi_sas_dq *dq;\n\tstruct hisi_sas_cmd_hdr *hdr;\n};\n\nstruct hisi_sas_iost;\n\nstruct hisi_sas_debugfs_iost {\n\tstruct hisi_sas_iost *iost;\n};\n\nstruct hisi_sas_itct;\n\nstruct hisi_sas_debugfs_itct {\n\tstruct hisi_sas_itct *itct;\n};\n\nstruct hisi_sas_iost_itct_cache;\n\nstruct hisi_sas_debugfs_iost_cache {\n\tstruct hisi_sas_iost_itct_cache *cache;\n};\n\nstruct hisi_sas_debugfs_itct_cache {\n\tstruct hisi_sas_iost_itct_cache *cache;\n};\n\nstruct hisi_sas_initial_fis;\n\nstruct hisi_sas_breakpoint;\n\nstruct hisi_sas_slot;\n\nstruct hisi_sas_hw;\n\nstruct hisi_hba {\n\tstruct sas_ha_struct *p;\n\tstruct platform_device *platform_dev;\n\tstruct pci_dev *pci_dev;\n\tstruct device *dev;\n\tint prot_mask;\n\tvoid *regs;\n\tvoid *sgpio_regs;\n\tstruct regmap *ctrl;\n\tu32 ctrl_reset_reg;\n\tu32 ctrl_reset_sts_reg;\n\tu32 ctrl_clock_ena_reg;\n\tu32 refclk_frequency_mhz;\n\tu8 sas_addr[8];\n\tint *irq_map;\n\tint n_phy;\n\tspinlock_t lock;\n\tstruct semaphore sem;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint slot_index_count;\n\tint last_slot_index;\n\tint last_dev_id;\n\tlong unsigned int *slot_index_tags;\n\tlong unsigned int reject_stp_links_msk;\n\tstruct sas_ha_struct sha;\n\tstruct Scsi_Host *shost;\n\tstruct hisi_sas_cq cq[32];\n\tstruct hisi_sas_dq dq[32];\n\tstruct hisi_sas_phy phy[9];\n\tstruct hisi_sas_port port[9];\n\tint queue_count;\n\tstruct hisi_sas_device devices[1024];\n\tstruct hisi_sas_cmd_hdr *cmd_hdr[32];\n\tdma_addr_t cmd_hdr_dma[32];\n\tvoid *complete_hdr[32];\n\tdma_addr_t complete_hdr_dma[32];\n\tstruct hisi_sas_initial_fis *initial_fis;\n\tdma_addr_t initial_fis_dma;\n\tstruct hisi_sas_itct *itct;\n\tdma_addr_t itct_dma;\n\tstruct hisi_sas_iost *iost;\n\tdma_addr_t iost_dma;\n\tstruct hisi_sas_breakpoint *breakpoint;\n\tdma_addr_t breakpoint_dma;\n\tstruct hisi_sas_breakpoint *sata_breakpoint;\n\tdma_addr_t sata_breakpoint_dma;\n\tstruct hisi_sas_slot *slot_info;\n\tlong unsigned int flags;\n\tconst struct hisi_sas_hw *hw;\n\tlong unsigned int sata_dev_bitmap[16];\n\tstruct work_struct rst_work;\n\tu32 phy_state;\n\tu32 intr_coal_ticks;\n\tu32 intr_coal_count;\n\tint cq_nvecs;\n\tenum sas_linkrate debugfs_bist_linkrate;\n\tint debugfs_bist_code_mode;\n\tint debugfs_bist_phy_no;\n\tint debugfs_bist_mode;\n\tu32 debugfs_bist_cnt;\n\tint debugfs_bist_enable;\n\tu32 debugfs_bist_ffe[72];\n\tu32 debugfs_bist_fixed_code[2];\n\tstruct hisi_sas_debugfs_regs debugfs_regs[150];\n\tstruct hisi_sas_debugfs_port debugfs_port_reg[450];\n\tstruct hisi_sas_debugfs_cq debugfs_cq[1600];\n\tstruct hisi_sas_debugfs_dq debugfs_dq[1600];\n\tstruct hisi_sas_debugfs_iost debugfs_iost[50];\n\tstruct hisi_sas_debugfs_itct debugfs_itct[50];\n\tstruct hisi_sas_debugfs_iost_cache debugfs_iost_cache[50];\n\tstruct hisi_sas_debugfs_itct_cache debugfs_itct_cache[50];\n\tu64 debugfs_timestamp[50];\n\tint debugfs_dump_index;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *debugfs_dump_dentry;\n\tstruct dentry *debugfs_bist_dentry;\n\tstruct dentry *debugfs_fifo_dentry;\n\tint iopoll_q_cnt;\n};\n\nstruct hisi_inno_phy_priv;\n\nstruct hisi_inno_phy_port {\n\tstruct reset_control *utmi_rst;\n\tstruct hisi_inno_phy_priv *priv;\n};\n\nstruct hisi_inno_phy_priv {\n\tvoid *mmio;\n\tstruct clk *ref_clk;\n\tstruct reset_control *por_rst;\n\tunsigned int type;\n\tstruct hisi_inno_phy_port ports[2];\n};\n\nstruct hisi_pmu_hwevents {\n\tstruct perf_event *hw_events[24];\n\tlong unsigned int used_mask[1];\n\tconst struct attribute_group **attr_groups;\n};\n\nstruct hisi_pmu_topology {\n\tunion {\n\t\tint sccl_id;\n\t\tint sicl_id;\n\t\tint scl_id;\n\t};\n\tint ccl_id;\n\tint index_id;\n\tint sub_id;\n};\n\nstruct hisi_uncore_ops;\n\nstruct hisi_pmu_dev_info;\n\nstruct hisi_pmu {\n\tstruct pmu pmu;\n\tconst struct hisi_uncore_ops *ops;\n\tconst struct hisi_pmu_dev_info *dev_info;\n\tstruct hisi_pmu_hwevents pmu_events;\n\tstruct hisi_pmu_topology topo;\n\tcpumask_t associated_cpus;\n\tint on_cpu;\n\tint irq;\n\tstruct device *dev;\n\tstruct hlist_node node;\n\tvoid *base;\n\tint num_counters;\n\tint counter_bits;\n\tint check_event;\n\tu32 identifier;\n};\n\nstruct hisi_l3c_pmu {\n\tstruct hisi_pmu l3c_pmu;\n\tvoid *ext_base[2];\n\tint ext_irq[2];\n\tint ext_num;\n};\n\nstruct hisi_l3c_pmu_ext {\n\tbool support_ext;\n};\n\nstruct platform_device_info;\n\nstruct hisi_lpc_acpi_cell {\n\tconst char *hid;\n\tconst struct platform_device_info *pdevinfo;\n};\n\nstruct logic_pio_hwaddr;\n\nstruct hisi_lpc_dev {\n\tspinlock_t cycle_lock;\n\tvoid *membase;\n\tstruct logic_pio_hwaddr *io_host;\n};\n\nstruct hisi_mn_pmu_regs {\n\tu32 version;\n\tu32 dyn_ctrl;\n\tu32 perf_ctrl;\n\tu32 int_mask;\n\tu32 int_clear;\n\tu32 int_status;\n\tu32 event_ctrl;\n\tu32 event_type0;\n\tu32 event_cntr0;\n};\n\nstruct hisi_mux_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 mux_flags;\n\tconst u32 *table;\n\tconst char *alias;\n};\n\nstruct hisi_noc_pmu_regs {\n\tu32 version;\n\tu32 pmu_ctrl;\n\tu32 event_ctrl0;\n\tu32 event_cntr0;\n\tu32 overflow_status;\n};\n\nstruct hisi_pa_pmu_int_regs {\n\tu32 mask_offset;\n\tu32 clear_offset;\n\tu32 status_offset;\n};\n\nstruct hisi_pcie {\n\tvoid *reg_base;\n};\n\nstruct hisi_phase_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_names;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu32 *phase_degrees;\n\tu32 *phase_regvals;\n\tu8 phase_num;\n};\n\nstruct hisi_pmu_dev_info {\n\tconst char *name;\n\tconst struct attribute_group **attr_groups;\n\tu32 counter_bits;\n\tu32 check_event;\n\tvoid *private;\n};\n\nstruct hisi_reset_controller {\n\tspinlock_t lock;\n\tvoid *membase;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct hisi_rng {\n\tvoid *base;\n\tstruct hwrng rng;\n};\n\nstruct hisi_sas_breakpoint {\n\tu8 data[128];\n};\n\nstruct hisi_sas_cmd_hdr {\n\t__le32 dw0;\n\t__le32 dw1;\n\t__le32 dw2;\n\t__le32 transfer_tags;\n\t__le32 data_transfer_len;\n\t__le32 first_burst_num;\n\t__le32 sg_len;\n\t__le32 dw7;\n\t__le64 cmd_table_addr;\n\t__le64 sts_buffer_addr;\n\t__le64 prd_table_addr;\n\t__le64 dif_prd_table_addr;\n};\n\nstruct hisi_sas_complete_v1_hdr {\n\t__le32 data;\n};\n\nstruct hisi_sas_complete_v2_hdr {\n\t__le32 dw0;\n\t__le32 dw1;\n\t__le32 act;\n\t__le32 dw3;\n};\n\nstruct hisi_sas_complete_v3_hdr {\n\t__le32 dw0;\n\t__le32 dw1;\n\t__le32 act;\n\t__le32 dw3;\n};\n\nstruct hisi_sas_debugfs_reg_lu;\n\nstruct hisi_sas_debugfs_reg {\n\tconst struct hisi_sas_debugfs_reg_lu *lu;\n\tint count;\n\tint base_off;\n};\n\nstruct hisi_sas_debugfs_reg_lu {\n\tchar *name;\n\tint off;\n};\n\nstruct hisi_sas_err_record {\n\tu32 data[4];\n};\n\nstruct hisi_sas_err_record_v1 {\n\t__le32 dma_err_type;\n\t__le32 trans_tx_fail_type;\n\t__le32 trans_rx_fail_type;\n\tu32 rsvd;\n};\n\nstruct hisi_sas_err_record_v2 {\n\t__le32 trans_tx_fail_type;\n\t__le32 trans_rx_fail_type;\n\t__le16 dma_tx_err_type;\n\t__le16 sipc_rx_err_type;\n\t__le32 dma_rx_err_type;\n};\n\nstruct hisi_sas_err_record_v3 {\n\t__le32 trans_tx_fail_type;\n\t__le32 trans_rx_fail_type;\n\t__le16 dma_tx_err_type;\n\t__le16 sipc_rx_err_type;\n\t__le32 dma_rx_err_type;\n};\n\nstruct sas_phy_linkrates;\n\nstruct hisi_sas_hw {\n\tint (*hw_init)(struct hisi_hba *);\n\tint (*fw_info_check)(struct hisi_hba *);\n\tint (*interrupt_preinit)(struct hisi_hba *);\n\tvoid (*setup_itct)(struct hisi_hba *, struct hisi_sas_device *);\n\tint (*slot_index_alloc)(struct hisi_hba *, struct domain_device *);\n\tstruct hisi_sas_device * (*alloc_dev)(struct domain_device *);\n\tvoid (*sl_notify_ssp)(struct hisi_hba *, int);\n\tvoid (*start_delivery)(struct hisi_sas_dq *);\n\tvoid (*prep_ssp)(struct hisi_hba *, struct hisi_sas_slot *);\n\tvoid (*prep_smp)(struct hisi_hba *, struct hisi_sas_slot *);\n\tvoid (*prep_stp)(struct hisi_hba *, struct hisi_sas_slot *);\n\tvoid (*prep_abort)(struct hisi_hba *, struct hisi_sas_slot *);\n\tvoid (*phys_init)(struct hisi_hba *);\n\tvoid (*phy_start)(struct hisi_hba *, int);\n\tvoid (*phy_disable)(struct hisi_hba *, int);\n\tvoid (*phy_hard_reset)(struct hisi_hba *, int);\n\tvoid (*get_events)(struct hisi_hba *, int);\n\tvoid (*phy_set_linkrate)(struct hisi_hba *, int, struct sas_phy_linkrates *);\n\tenum sas_linkrate (*phy_get_max_linkrate)(void);\n\tint (*clear_itct)(struct hisi_hba *, struct hisi_sas_device *);\n\tvoid (*free_device)(struct hisi_sas_device *);\n\tint (*get_wideport_bitmap)(struct hisi_hba *, int);\n\tvoid (*dereg_device)(struct hisi_hba *, struct domain_device *);\n\tint (*soft_reset)(struct hisi_hba *);\n\tu32 (*get_phys_state)(struct hisi_hba *);\n\tint (*write_gpio)(struct hisi_hba *, u8, u8, u8, u8 *);\n\tvoid (*wait_cmds_complete_timeout)(struct hisi_hba *, int, int);\n\tint (*debugfs_snapshot_regs)(struct hisi_hba *);\n\tint complete_hdr_size;\n\tconst struct scsi_host_template *sht;\n};\n\nstruct hisi_sas_hw_error {\n\tu32 irq_msk;\n\tu32 msk;\n\tint shift;\n\tconst char *msg;\n\tint reg;\n\tconst struct hisi_sas_hw_error *sub;\n};\n\nstruct hisi_sas_initial_fis {\n\tstruct hisi_sas_err_record err_record;\n\tstruct dev_to_host_fis fis;\n\tu32 rsvd[3];\n};\n\nstruct hisi_sas_internal_abort_data {\n\tbool rst_ha_timeout;\n};\n\nstruct hisi_sas_iost {\n\t__le64 qw0;\n\t__le64 qw1;\n\t__le64 qw2;\n\t__le64 qw3;\n};\n\nstruct hisi_sas_iost_itct_cache {\n\tu32 data[10];\n};\n\nstruct hisi_sas_itct {\n\t__le64 qw0;\n\t__le64 sas_addr;\n\t__le64 qw2;\n\t__le64 qw3;\n\t__le64 qw4_15[12];\n};\n\nstruct hisi_sas_protect_iu_v3_hw {\n\tu32 dw0;\n\tu32 lbrtcv;\n\tu32 lbrtgv;\n\tu32 dw3;\n\tu32 dw4;\n\tu32 dw5;\n\tu32 rsv;\n};\n\nstruct hisi_sas_rst {\n\tstruct hisi_hba *hisi_hba;\n\tstruct completion *completion;\n\tstruct work_struct work;\n\tbool done;\n};\n\nstruct hisi_sas_sge {\n\t__le64 addr;\n\t__le32 page_ctrl_0;\n\t__le32 page_ctrl_1;\n\t__le32 data_len;\n\t__le32 data_off;\n};\n\nstruct hisi_sas_sge_dif_page {\n\tstruct hisi_sas_sge sge[124];\n};\n\nstruct hisi_sas_sge_page {\n\tstruct hisi_sas_sge sge[124];\n};\n\nstruct sas_task;\n\nstruct sas_tmf_task;\n\nstruct hisi_sas_slot {\n\tstruct list_head entry;\n\tstruct list_head delivery;\n\tstruct sas_task *task;\n\tstruct hisi_sas_port *port;\n\tu64 n_elem;\n\tu64 n_elem_dif;\n\tint dlvry_queue;\n\tint dlvry_queue_slot;\n\tint cmplt_queue;\n\tint cmplt_queue_slot;\n\tint abort;\n\tint ready;\n\tint device_id;\n\tvoid *cmd_hdr;\n\tdma_addr_t cmd_hdr_dma;\n\tstruct timer_list internal_abort_timer;\n\tbool is_internal;\n\tstruct sas_tmf_task *tmf;\n\tvoid *buf;\n\tdma_addr_t buf_dma;\n\tu16 idx;\n};\n\nstruct hisi_sas_status_buffer {\n\tstruct hisi_sas_err_record err;\n\tu8 iu[1024];\n};\n\nstruct hisi_sllc_pmu_regs {\n\tu32 int_mask;\n\tu32 int_clear;\n\tu32 int_status;\n\tu32 perf_ctrl;\n\tu32 srcid_ctrl;\n\tu32 srcid_cmd_shift;\n\tu32 srcid_mask_shift;\n\tu32 tgtid_ctrl;\n\tu32 tgtid_min_shift;\n\tu32 tgtid_max_shift;\n\tu32 event_ctrl;\n\tu32 event_type0;\n\tu32 version;\n\tu32 event_cnt0;\n};\n\nstruct hisi_thermal_ops;\n\nstruct hisi_thermal_sensor;\n\nstruct hisi_thermal_data {\n\tconst struct hisi_thermal_ops *ops;\n\tstruct hisi_thermal_sensor *sensor;\n\tstruct platform_device *pdev;\n\tstruct clk *clk;\n\tvoid *regs;\n\tint nr_sensors;\n};\n\nstruct hisi_thermal_ops {\n\tint (*get_temp)(struct hisi_thermal_sensor *);\n\tint (*enable_sensor)(struct hisi_thermal_sensor *);\n\tint (*disable_sensor)(struct hisi_thermal_sensor *);\n\tint (*irq_handler)(struct hisi_thermal_sensor *);\n\tint (*probe)(struct hisi_thermal_data *);\n};\n\nstruct hisi_thermal_sensor {\n\tstruct hisi_thermal_data *data;\n\tstruct thermal_zone_device *tzd;\n\tconst char *irq_name;\n\tuint32_t id;\n\tuint32_t thres_temp;\n};\n\nstruct hisi_uncore_ops {\n\tint (*check_filter)(struct perf_event *);\n\tvoid (*write_evtype)(struct hisi_pmu *, int, u32);\n\tint (*get_event_idx)(struct perf_event *);\n\tu64 (*read_counter)(struct hisi_pmu *, struct hw_perf_event *);\n\tvoid (*write_counter)(struct hisi_pmu *, struct hw_perf_event *, u64);\n\tvoid (*enable_counter)(struct hisi_pmu *, struct hw_perf_event *);\n\tvoid (*disable_counter)(struct hisi_pmu *, struct hw_perf_event *);\n\tvoid (*enable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);\n\tvoid (*disable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);\n\tvoid (*start_counters)(struct hisi_pmu *);\n\tvoid (*stop_counters)(struct hisi_pmu *);\n\tu32 (*get_int_status)(struct hisi_pmu *);\n\tvoid (*clear_int_status)(struct hisi_pmu *, int);\n\tvoid (*enable_filter)(struct perf_event *);\n\tvoid (*disable_filter)(struct perf_event *);\n};\n\nstruct histb_combphy_mode {\n\tint fixed;\n\tint select;\n\tu32 reg;\n\tu32 shift;\n\tu32 mask;\n};\n\nstruct histb_combphy_priv {\n\tvoid *mmio;\n\tstruct regmap *syscon;\n\tstruct reset_control *por_rst;\n\tstruct clk *ref_clk;\n\tstruct phy *phy;\n\tstruct histb_combphy_mode mode;\n};\n\nstruct histb_pcie {\n\tstruct dw_pcie *pci;\n\tstruct clk *aux_clk;\n\tstruct clk *pipe_clk;\n\tstruct clk *sys_clk;\n\tstruct clk *bus_clk;\n\tstruct phy *phy;\n\tstruct reset_control *soft_reset;\n\tstruct reset_control *sys_reset;\n\tstruct reset_control *bus_reset;\n\tvoid *ctrl;\n\tstruct gpio_desc *reset_gpio;\n\tstruct regulator *vpcie;\n};\n\nstruct histb_rng_priv {\n\tstruct hwrng rng;\n\tvoid *base;\n};\n\nstruct hix5hd2_desc {\n\t__le32 buff_addr;\n\t__le32 cmd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hix5hd2_desc_sw {\n\tstruct hix5hd2_desc *desc;\n\tdma_addr_t phys_addr;\n\tunsigned int count;\n\tunsigned int size;\n};\n\nstruct sg_desc;\n\nstruct hix5hd2_sg_desc_ring {\n\tstruct sg_desc *desc;\n\tdma_addr_t phys_addr;\n};\n\nstruct hix5hd2_priv {\n\tstruct hix5hd2_desc_sw pool[4];\n\tstruct hix5hd2_sg_desc_ring tx_ring;\n\tvoid *base;\n\tvoid *ctrl_base;\n\tstruct sk_buff *tx_skb[1024];\n\tstruct sk_buff *rx_skb[1024];\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct device_node *phy_node;\n\tphy_interface_t phy_mode;\n\tlong unsigned int hw_cap;\n\tunsigned int speed;\n\tunsigned int duplex;\n\tstruct clk *mac_core_clk;\n\tstruct clk *mac_ifc_clk;\n\tstruct reset_control *mac_core_rst;\n\tstruct reset_control *mac_ifc_rst;\n\tstruct reset_control *phy_rst;\n\tu32 phy_reset_delays[3];\n\tstruct mii_bus *bus;\n\tstruct napi_struct napi;\n\tstruct work_struct tx_timeout_task;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct hmac_ctx {\n\tstruct crypto_shash *hash;\n\tu8 pads[0];\n};\n\nstruct sha1_block_state {\n\tu32 h[5];\n};\n\nstruct sha1_ctx {\n\tstruct sha1_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_sha1_ctx {\n\tstruct sha1_ctx sha_ctx;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha1_key {\n\tstruct sha1_block_state istate;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha384_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha384_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hmac_sha512_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha512_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hnae3_ae_ops;\n\nstruct hnae3_ae_algo {\n\tconst struct hnae3_ae_ops *ops;\n\tstruct list_head node;\n\tconst struct pci_device_id *pdev_id_table;\n};\n\nstruct hnae3_dev_specs {\n\tu32 mac_entry_num;\n\tu32 mng_entry_num;\n\tu32 max_tm_rate;\n\tu16 rss_ind_tbl_size;\n\tu16 rss_key_size;\n\tu16 int_ql_max;\n\tu16 max_int_gl;\n\tu8 max_non_tso_bd_num;\n\tu16 max_frm_size;\n\tu16 max_qset_num;\n\tu16 umv_size;\n\tu16 mc_mac_size;\n\tu32 mac_stats_num;\n\tu8 tnl_num;\n\tu8 hilink_version;\n};\n\nstruct hnae3_ae_dev {\n\tstruct pci_dev *pdev;\n\tconst struct hnae3_ae_ops *ops;\n\tstruct list_head node;\n\tu32 flag;\n\tlong unsigned int hw_err_reset_req;\n\tstruct hnae3_dev_specs dev_specs;\n\tu32 dev_version;\n\tlong unsigned int caps[2];\n\tvoid *priv;\n\tstruct hnae3_handle *handle;\n};\n\nstruct hns3_mac_stats;\n\nstruct hnae3_vector_info;\n\nstruct hnae3_ring_chain_node;\n\nstruct ifla_vf_info;\n\nstruct hnae3_ae_ops {\n\tint (*init_ae_dev)(struct hnae3_ae_dev *);\n\tvoid (*uninit_ae_dev)(struct hnae3_ae_dev *);\n\tvoid (*reset_prepare)(struct hnae3_ae_dev *, enum hnae3_reset_type);\n\tvoid (*reset_done)(struct hnae3_ae_dev *);\n\tint (*init_client_instance)(struct hnae3_client *, struct hnae3_ae_dev *);\n\tvoid (*uninit_client_instance)(struct hnae3_client *, struct hnae3_ae_dev *);\n\tint (*start)(struct hnae3_handle *);\n\tvoid (*stop)(struct hnae3_handle *);\n\tint (*client_start)(struct hnae3_handle *);\n\tvoid (*client_stop)(struct hnae3_handle *);\n\tint (*get_status)(struct hnae3_handle *);\n\tvoid (*get_ksettings_an_result)(struct hnae3_handle *, u8 *, u32 *, u8 *, u32 *);\n\tint (*cfg_mac_speed_dup_h)(struct hnae3_handle *, int, u8, u8);\n\tvoid (*get_media_type)(struct hnae3_handle *, u8 *, u8 *);\n\tint (*check_port_speed)(struct hnae3_handle *, u32);\n\tvoid (*get_fec_stats)(struct hnae3_handle *, struct ethtool_fec_stats *);\n\tvoid (*get_fec)(struct hnae3_handle *, u8 *, u8 *);\n\tint (*set_fec)(struct hnae3_handle *, u32);\n\tvoid (*adjust_link)(struct hnae3_handle *, int, int);\n\tint (*set_loopback)(struct hnae3_handle *, enum hnae3_loop, bool);\n\tint (*set_promisc_mode)(struct hnae3_handle *, bool, bool);\n\tvoid (*request_update_promisc_mode)(struct hnae3_handle *);\n\tint (*set_mtu)(struct hnae3_handle *, int);\n\tvoid (*get_pauseparam)(struct hnae3_handle *, u32 *, u32 *, u32 *);\n\tint (*set_pauseparam)(struct hnae3_handle *, u32, u32, u32);\n\tint (*set_autoneg)(struct hnae3_handle *, bool);\n\tint (*get_autoneg)(struct hnae3_handle *);\n\tint (*restart_autoneg)(struct hnae3_handle *);\n\tint (*halt_autoneg)(struct hnae3_handle *, bool);\n\tvoid (*get_coalesce_usecs)(struct hnae3_handle *, u32 *, u32 *);\n\tvoid (*get_rx_max_coalesced_frames)(struct hnae3_handle *, u32 *, u32 *);\n\tint (*set_coalesce_usecs)(struct hnae3_handle *, u32);\n\tint (*set_coalesce_frames)(struct hnae3_handle *, u32);\n\tvoid (*get_coalesce_range)(struct hnae3_handle *, u32 *, u32 *, u32 *, u32 *, u32 *, u32 *, u32 *, u32 *);\n\tvoid (*get_mac_addr)(struct hnae3_handle *, u8 *);\n\tint (*set_mac_addr)(struct hnae3_handle *, const void *, bool);\n\tint (*do_ioctl)(struct hnae3_handle *, struct ifreq *, int);\n\tint (*add_uc_addr)(struct hnae3_handle *, const unsigned char *);\n\tint (*rm_uc_addr)(struct hnae3_handle *, const unsigned char *);\n\tint (*set_mc_addr)(struct hnae3_handle *, void *);\n\tint (*add_mc_addr)(struct hnae3_handle *, const unsigned char *);\n\tint (*rm_mc_addr)(struct hnae3_handle *, const unsigned char *);\n\tvoid (*set_tso_stats)(struct hnae3_handle *, int);\n\tvoid (*update_stats)(struct hnae3_handle *);\n\tvoid (*get_stats)(struct hnae3_handle *, u64 *);\n\tvoid (*get_mac_stats)(struct hnae3_handle *, struct hns3_mac_stats *);\n\tvoid (*get_strings)(struct hnae3_handle *, u32, u8 **);\n\tint (*get_sset_count)(struct hnae3_handle *, int);\n\tvoid (*get_regs)(struct hnae3_handle *, u32 *, void *);\n\tint (*get_regs_len)(struct hnae3_handle *);\n\tu32 (*get_rss_key_size)(struct hnae3_handle *);\n\tint (*get_rss)(struct hnae3_handle *, u32 *, u8 *, u8 *);\n\tint (*set_rss)(struct hnae3_handle *, const u32 *, const u8 *, const u8);\n\tint (*set_rss_tuple)(struct hnae3_handle *, const struct ethtool_rxfh_fields *);\n\tint (*get_rss_tuple)(struct hnae3_handle *, struct ethtool_rxfh_fields *);\n\tint (*get_tc_size)(struct hnae3_handle *);\n\tint (*get_vector)(struct hnae3_handle *, u16, struct hnae3_vector_info *);\n\tint (*put_vector)(struct hnae3_handle *, int);\n\tint (*map_ring_to_vector)(struct hnae3_handle *, int, struct hnae3_ring_chain_node *);\n\tint (*unmap_ring_from_vector)(struct hnae3_handle *, int, struct hnae3_ring_chain_node *);\n\tint (*reset_queue)(struct hnae3_handle *);\n\tu32 (*get_fw_version)(struct hnae3_handle *);\n\tvoid (*get_mdix_mode)(struct hnae3_handle *, u8 *, u8 *);\n\tint (*enable_vlan_filter)(struct hnae3_handle *, bool);\n\tint (*set_vlan_filter)(struct hnae3_handle *, __be16, u16, bool);\n\tint (*set_vf_vlan_filter)(struct hnae3_handle *, int, u16, u8, __be16);\n\tint (*enable_hw_strip_rxvtag)(struct hnae3_handle *, bool);\n\tvoid (*reset_event)(struct pci_dev *, struct hnae3_handle *);\n\tenum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *, long unsigned int *);\n\tvoid (*set_default_reset_request)(struct hnae3_ae_dev *, enum hnae3_reset_type);\n\tvoid (*get_channels)(struct hnae3_handle *, struct ethtool_channels *);\n\tvoid (*get_tqps_and_rss_info)(struct hnae3_handle *, u16 *, u16 *);\n\tint (*set_channels)(struct hnae3_handle *, u32, bool);\n\tvoid (*get_flowctrl_adv)(struct hnae3_handle *, u32 *);\n\tint (*set_led_id)(struct hnae3_handle *, enum ethtool_phys_id_state);\n\tvoid (*get_link_mode)(struct hnae3_handle *, long unsigned int *, long unsigned int *);\n\tint (*add_fd_entry)(struct hnae3_handle *, struct ethtool_rxnfc *);\n\tint (*del_fd_entry)(struct hnae3_handle *, struct ethtool_rxnfc *);\n\tint (*get_fd_rule_cnt)(struct hnae3_handle *, struct ethtool_rxnfc *);\n\tint (*get_fd_rule_info)(struct hnae3_handle *, struct ethtool_rxnfc *);\n\tint (*get_fd_all_rules)(struct hnae3_handle *, struct ethtool_rxnfc *, u32 *);\n\tvoid (*enable_fd)(struct hnae3_handle *, bool);\n\tint (*add_arfs_entry)(struct hnae3_handle *, u16, u16, struct flow_keys *);\n\tpci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *);\n\tbool (*get_hw_reset_stat)(struct hnae3_handle *);\n\tbool (*ae_dev_resetting)(struct hnae3_handle *);\n\tlong unsigned int (*ae_dev_reset_cnt)(struct hnae3_handle *);\n\tint (*set_gro_en)(struct hnae3_handle *, bool);\n\tu16 (*get_global_queue_id)(struct hnae3_handle *, u16);\n\tvoid (*set_timer_task)(struct hnae3_handle *, bool);\n\tint (*mac_connect_phy)(struct hnae3_handle *);\n\tvoid (*mac_disconnect_phy)(struct hnae3_handle *);\n\tint (*get_vf_config)(struct hnae3_handle *, int, struct ifla_vf_info *);\n\tint (*set_vf_link_state)(struct hnae3_handle *, int, int);\n\tint (*set_vf_spoofchk)(struct hnae3_handle *, int, bool);\n\tint (*set_vf_trust)(struct hnae3_handle *, int, bool);\n\tint (*set_vf_rate)(struct hnae3_handle *, int, int, int, bool);\n\tint (*set_vf_mac)(struct hnae3_handle *, int, u8 *);\n\tint (*get_module_eeprom)(struct hnae3_handle *, u32, u32, u8 *);\n\tbool (*get_cmdq_stat)(struct hnae3_handle *);\n\tint (*add_cls_flower)(struct hnae3_handle *, struct flow_cls_offload *, int);\n\tint (*del_cls_flower)(struct hnae3_handle *, struct flow_cls_offload *);\n\tbool (*cls_flower_active)(struct hnae3_handle *);\n\tint (*get_phy_link_ksettings)(struct hnae3_handle *, struct ethtool_link_ksettings *);\n\tint (*set_phy_link_ksettings)(struct hnae3_handle *, const struct ethtool_link_ksettings *);\n\tbool (*set_tx_hwts_info)(struct hnae3_handle *, struct sk_buff *);\n\tvoid (*get_rx_hwts)(struct hnae3_handle *, struct sk_buff *, u32, u32);\n\tint (*get_ts_info)(struct hnae3_handle *, struct kernel_ethtool_ts_info *);\n\tint (*get_link_diagnosis_info)(struct hnae3_handle *, u32 *);\n\tvoid (*clean_vf_config)(struct hnae3_ae_dev *, int);\n\tint (*get_dscp_prio)(struct hnae3_handle *, u8, u8 *, u8 *);\n\tvoid (*get_wol)(struct hnae3_handle *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct hnae3_handle *, struct ethtool_wolinfo *);\n\tint (*dbg_get_read_func)(struct hnae3_handle *, enum hnae3_dbg_cmd, read_func *);\n\tint (*hwtstamp_get)(struct hnae3_handle *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct hnae3_handle *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct hnae3_client_ops;\n\nstruct hnae3_client {\n\tchar name[16];\n\tlong unsigned int state;\n\tenum hnae3_client_type type;\n\tconst struct hnae3_client_ops *ops;\n\tstruct list_head node;\n};\n\nstruct hnae3_client_ops {\n\tint (*init_instance)(struct hnae3_handle *);\n\tvoid (*uninit_instance)(struct hnae3_handle *, bool);\n\tvoid (*link_status_change)(struct hnae3_handle *, bool);\n\tint (*reset_notify)(struct hnae3_handle *, enum hnae3_reset_notify_type);\n\tvoid (*process_hw_error)(struct hnae3_handle *, enum hnae3_hw_error_type);\n};\n\nstruct ieee_ets;\n\nstruct ieee_pfc;\n\nstruct hnae3_dcb_ops {\n\tint (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);\n\tint (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);\n\tint (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);\n\tint (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);\n\tint (*ieee_setapp)(struct hnae3_handle *, struct dcb_app *);\n\tint (*ieee_delapp)(struct hnae3_handle *, struct dcb_app *);\n\tu8 (*getdcbx)(struct hnae3_handle *);\n\tu8 (*setdcbx)(struct hnae3_handle *, u8);\n\tint (*setup_tc)(struct hnae3_handle *, struct tc_mqprio_qopt_offload *);\n};\n\nstruct hnae3_ring_chain_node {\n\tstruct hnae3_ring_chain_node *next;\n\tu32 tqp_index;\n\tu32 flag;\n\tu32 int_gl_idx;\n};\n\nstruct hnae3_vector_info {\n\tu8 *io_addr;\n\tint vector;\n};\n\nstruct hnae_handle;\n\nstruct hnae_queue;\n\nstruct hnae_ring;\n\nstruct net_device_stats;\n\nstruct hnae_ae_ops {\n\tstruct hnae_handle * (*get_handle)(struct hnae_ae_dev *, u32);\n\tvoid (*put_handle)(struct hnae_handle *);\n\tvoid (*init_queue)(struct hnae_queue *);\n\tvoid (*fini_queue)(struct hnae_queue *);\n\tint (*start)(struct hnae_handle *);\n\tvoid (*stop)(struct hnae_handle *);\n\tvoid (*reset)(struct hnae_handle *);\n\tint (*set_opts)(struct hnae_handle *, int, void *);\n\tint (*get_opts)(struct hnae_handle *, int, void **);\n\tint (*get_status)(struct hnae_handle *);\n\tint (*get_info)(struct hnae_handle *, u8 *, u16 *, u8 *);\n\tvoid (*toggle_ring_irq)(struct hnae_ring *, u32);\n\tvoid (*adjust_link)(struct hnae_handle *, int, int);\n\tbool (*need_adjust_link)(struct hnae_handle *, int, int);\n\tint (*set_loopback)(struct hnae_handle *, enum hnae_loop, int);\n\tvoid (*get_ring_bdnum_limit)(struct hnae_queue *, u32 *);\n\tvoid (*get_pauseparam)(struct hnae_handle *, u32 *, u32 *, u32 *);\n\tint (*set_pauseparam)(struct hnae_handle *, u32, u32, u32);\n\tvoid (*get_coalesce_usecs)(struct hnae_handle *, u32 *, u32 *);\n\tvoid (*get_max_coalesced_frames)(struct hnae_handle *, u32 *, u32 *);\n\tint (*set_coalesce_usecs)(struct hnae_handle *, u32);\n\tint (*set_coalesce_frames)(struct hnae_handle *, u32, u32);\n\tvoid (*get_coalesce_range)(struct hnae_handle *, u32 *, u32 *, u32 *, u32 *, u32 *, u32 *, u32 *, u32 *);\n\tvoid (*set_promisc_mode)(struct hnae_handle *, u32);\n\tint (*get_mac_addr)(struct hnae_handle *, void **);\n\tint (*set_mac_addr)(struct hnae_handle *, const void *);\n\tint (*add_uc_addr)(struct hnae_handle *, const unsigned char *);\n\tint (*rm_uc_addr)(struct hnae_handle *, const unsigned char *);\n\tint (*clr_mc_addr)(struct hnae_handle *);\n\tint (*set_mc_addr)(struct hnae_handle *, void *);\n\tint (*set_mtu)(struct hnae_handle *, int);\n\tvoid (*set_tso_stats)(struct hnae_handle *, int);\n\tvoid (*update_stats)(struct hnae_handle *, struct net_device_stats *);\n\tvoid (*get_stats)(struct hnae_handle *, u64 *);\n\tvoid (*get_strings)(struct hnae_handle *, u32, u8 **);\n\tint (*get_sset_count)(struct hnae_handle *, int);\n\tvoid (*update_led_status)(struct hnae_handle *);\n\tint (*set_led_id)(struct hnae_handle *, enum hnae_led_state);\n\tvoid (*get_regs)(struct hnae_handle *, void *);\n\tint (*get_regs_len)(struct hnae_handle *);\n\tu32 (*get_rss_key_size)(struct hnae_handle *);\n\tu32 (*get_rss_indir_size)(struct hnae_handle *);\n\tint (*get_rss)(struct hnae_handle *, u32 *, u8 *, u8 *);\n\tint (*set_rss)(struct hnae_handle *, const u32 *, const u8 *, const u8);\n};\n\nstruct hnae_desc_cb;\n\nstruct hnae_buf_ops {\n\tint (*alloc_buffer)(struct hnae_ring *, struct hnae_desc_cb *);\n\tvoid (*free_buffer)(struct hnae_ring *, struct hnae_desc_cb *);\n\tint (*map_buffer)(struct hnae_ring *, struct hnae_desc_cb *);\n\tvoid (*unmap_buffer)(struct hnae_ring *, struct hnae_desc_cb *);\n};\n\nstruct hnae_desc {\n\t__le64 addr;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__le16 asid_bufnum_pid;\n\t\t\t\t__le16 asid;\n\t\t\t};\n\t\t\t__le16 send_size;\n\t\t\tunion {\n\t\t\t\t__le32 flag_ipoffset;\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 bn_pid;\n\t\t\t\t\t__u8 ra_ri_cs_fe_vld;\n\t\t\t\t\t__u8 ip_offset;\n\t\t\t\t\t__u8 tse_vlan_snap_v6_sctp_nth;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__le16 mss;\n\t\t\t__u8 l4_len;\n\t\t\t__u8 reserved1;\n\t\t\t__le16 paylen;\n\t\t\t__u8 vmid;\n\t\t\t__u8 qid;\n\t\t\t__le32 reserved2[2];\n\t\t} tx;\n\t\tstruct {\n\t\t\t__le32 ipoff_bnum_pid_flag;\n\t\t\t__le16 pkt_len;\n\t\t\t__le16 size;\n\t\t\tunion {\n\t\t\t\t__le32 vlan_pri_asid;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 asid;\n\t\t\t\t\t__le16 vlan_cfi_pri;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__le32 rss_hash;\n\t\t\t__le32 reserved_1[2];\n\t\t} rx;\n\t};\n};\n\nstruct hnae_desc_cb {\n\tdma_addr_t dma;\n\tvoid *buf;\n\tvoid *priv;\n\tu32 page_offset;\n\tu32 length;\n\tu16 reuse_flag;\n\tu16 type;\n};\n\nstruct hnae_handle {\n\tstruct device *owner_dev;\n\tstruct hnae_ae_dev *dev;\n\tstruct phy_device *phy_dev;\n\tphy_interface_t phy_if;\n\tu32 if_support;\n\tint q_num;\n\tint vf_id;\n\tlong unsigned int coal_last_jiffies;\n\tu32 coal_param;\n\tu32 coal_ring_idx;\n\tu32 eport_id;\n\tu32 dport_id;\n\tbool coal_adapt_en;\n\tenum hnae_port_type port_type;\n\tenum hnae_media_type media_type;\n\tstruct list_head node;\n\tstruct hnae_buf_ops *bops;\n\tstruct hnae_queue *qs[0];\n};\n\nstruct ring_stats {\n\tu64 io_err_cnt;\n\tu64 sw_err_cnt;\n\tu64 seg_pkt_cnt;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pkts;\n\t\t\tu64 tx_bytes;\n\t\t\tu64 tx_err_cnt;\n\t\t\tu64 restart_queue;\n\t\t\tu64 tx_busy;\n\t\t};\n\t\tstruct {\n\t\t\tu64 rx_pkts;\n\t\t\tu64 rx_bytes;\n\t\t\tu64 rx_err_cnt;\n\t\t\tu64 reuse_pg_cnt;\n\t\t\tu64 err_pkt_len;\n\t\t\tu64 non_vld_descs;\n\t\t\tu64 err_bd_num;\n\t\t\tu64 l2_err;\n\t\t\tu64 l3l4_csum_err;\n\t\t};\n\t};\n};\n\nstruct hnae_ring {\n\tu8 *io_base;\n\tstruct hnae_desc *desc;\n\tstruct hnae_desc_cb *desc_cb;\n\tstruct hnae_queue *q;\n\tint irq;\n\tchar ring_name[20];\n\tstruct ring_stats stats;\n\tdma_addr_t desc_dma_addr;\n\tu32 buf_size;\n\tu16 desc_num;\n\tu16 max_desc_num_per_pkt;\n\tu16 max_raw_data_sz_per_desc;\n\tu16 max_pkt_size;\n\tint next_to_use;\n\tint next_to_clean;\n\tint flags;\n\tint irq_init_flag;\n\tu64 coal_last_rx_bytes;\n\tlong unsigned int coal_last_jiffies;\n\tu32 coal_param;\n\tu32 coal_rx_rate;\n};\n\nstruct hnae_queue {\n\tu8 *io_base;\n\tphys_addr_t phy_base;\n\tstruct hnae_ae_dev *dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hnae_ring rx_ring;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hnae_ring tx_ring;\n\tstruct hnae_handle *handle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hnae_vf_cb {\n\tu8 port_index;\n\tstruct hns_mac_cb *mac_cb;\n\tstruct dsaf_device *dsaf_dev;\n\tstruct hnae_handle ae_handle;\n};\n\nstruct hns3_dbg_cap_info {\n\tconst char *name;\n\tenum HNAE3_DEV_CAP_BITS cap_bit;\n};\n\nstruct hns3_dbg_cmd_info {\n\tconst char *name;\n\tenum hnae3_dbg_cmd cmd;\n\tenum hns3_dbg_dentry_type dentry;\n\tint (*init)(struct hnae3_handle *, unsigned int);\n};\n\nstruct hns3_dbg_data {\n\tstruct hnae3_handle *handle;\n\tenum hnae3_dbg_cmd cmd;\n\tu16 qid;\n};\n\nstruct hns3_dbg_dentry_info {\n\tconst char *name;\n\tstruct dentry *dentry;\n};\n\nstruct hns3_desc {\n\tunion {\n\t\t__le64 addr;\n\t\t__le16 csum;\n\t\tstruct {\n\t\t\t__le32 ts_nsec;\n\t\t\t__le32 ts_sec;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__le16 vlan_tag;\n\t\t\t__le16 send_size;\n\t\t\tunion {\n\t\t\t\t__le32 type_cs_vlan_tso_len;\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 type_cs_vlan_tso;\n\t\t\t\t\t__u8 l2_len;\n\t\t\t\t\t__u8 l3_len;\n\t\t\t\t\t__u8 l4_len;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__le16 outer_vlan_tag;\n\t\t\t__le16 tv;\n\t\t\tunion {\n\t\t\t\t__le32 ol_type_vlan_len_msec;\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 ol_type_vlan_msec;\n\t\t\t\t\t__u8 ol2_len;\n\t\t\t\t\t__u8 ol3_len;\n\t\t\t\t\t__u8 ol4_len;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__le32 paylen_ol4cs;\n\t\t\t__le16 bdtp_fe_sc_vld_ra_ri;\n\t\t\t__le16 mss_hw_csum;\n\t\t} tx;\n\t\tstruct {\n\t\t\t__le32 l234_info;\n\t\t\t__le16 pkt_len;\n\t\t\t__le16 size;\n\t\t\t__le32 rss_hash;\n\t\t\t__le16 fd_id;\n\t\t\t__le16 vlan_tag;\n\t\t\tunion {\n\t\t\t\t__le32 ol_info;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 o_dm_vlan_id_fb;\n\t\t\t\t\t__le16 ot_vlan_tag;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__le32 bd_base_info;\n\t\t} rx;\n\t};\n};\n\nstruct hns3_desc_cb {\n\tdma_addr_t dma;\n\tvoid *buf;\n\tvoid *priv;\n\tunion {\n\t\tu32 page_offset;\n\t\tu32 send_bytes;\n\t};\n\tu32 length;\n\tu16 reuse_flag;\n\tu16 refill;\n\tu16 type;\n\tu16 pagecnt_bias;\n};\n\nstruct hns3_desc_param {\n\tu32 paylen_ol4cs;\n\tu32 ol_type_vlan_len_msec;\n\tu32 type_cs_vlan_tso;\n\tu16 mss_hw_csum;\n\tu16 inner_vtag;\n\tu16 out_vtag;\n};\n\nstruct hns3_enet_coalesce {\n\tu16 int_gl;\n\tu16 int_ql;\n\tu16 int_ql_max;\n\tu8 adapt_enable: 1;\n\tu8 ql_enable: 1;\n\tu8 unit_1us: 1;\n\tenum hns3_flow_level_range flow_level;\n};\n\nstruct ring_stats___2 {\n\tu64 sw_err_cnt;\n\tu64 seg_pkt_cnt;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pkts;\n\t\t\tu64 tx_bytes;\n\t\t\tu64 tx_more;\n\t\t\tu64 tx_push;\n\t\t\tu64 tx_mem_doorbell;\n\t\t\tu64 restart_queue;\n\t\t\tu64 tx_busy;\n\t\t\tu64 tx_copy;\n\t\t\tu64 tx_vlan_err;\n\t\t\tu64 tx_l4_proto_err;\n\t\t\tu64 tx_l2l3l4_err;\n\t\t\tu64 tx_tso_err;\n\t\t\tu64 over_max_recursion;\n\t\t\tu64 hw_limitation;\n\t\t\tu64 tx_bounce;\n\t\t\tu64 tx_spare_full;\n\t\t\tu64 copy_bits_err;\n\t\t\tu64 tx_sgl;\n\t\t\tu64 skb2sgl_err;\n\t\t\tu64 map_sg_err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 rx_pkts;\n\t\t\tu64 rx_bytes;\n\t\t\tu64 rx_err_cnt;\n\t\t\tu64 reuse_pg_cnt;\n\t\t\tu64 err_pkt_len;\n\t\t\tu64 err_bd_num;\n\t\t\tu64 l2_err;\n\t\t\tu64 l3l4_csum_err;\n\t\t\tu64 csum_complete;\n\t\t\tu64 rx_multicast;\n\t\t\tu64 non_reuse_pg;\n\t\t\tu64 frag_alloc_err;\n\t\t\tu64 frag_alloc;\n\t\t};\n\t\t__le16 csum;\n\t};\n};\n\nstruct hns3_enet_tqp_vector;\n\nstruct hns3_tx_spare;\n\nstruct hns3_enet_ring {\n\tstruct hns3_desc *desc;\n\tstruct hns3_desc_cb *desc_cb;\n\tstruct hns3_enet_ring *next;\n\tstruct hns3_enet_tqp_vector *tqp_vector;\n\tstruct hnae3_queue *tqp;\n\tint queue_index;\n\tstruct device *dev;\n\tstruct page_pool *page_pool;\n\tstruct ring_stats___2 stats;\n\tstruct u64_stats_sync syncp;\n\tdma_addr_t desc_dma_addr;\n\tu32 buf_size;\n\tu16 desc_num;\n\tint next_to_use;\n\tint next_to_clean;\n\tu32 flag;\n\tint pending_buf;\n\tunion {\n\t\tstruct {\n\t\t\tu32 fd_qb_tx_sample;\n\t\t\tint last_to_use;\n\t\t\tu32 tx_copybreak;\n\t\t\tstruct hns3_tx_spare *tx_spare;\n\t\t};\n\t\tstruct {\n\t\t\tu32 pull_len;\n\t\t\tu32 rx_copybreak;\n\t\t\tu32 frag_num;\n\t\t\tunsigned char *va;\n\t\t\tstruct sk_buff *skb;\n\t\t\tstruct sk_buff *tail_skb;\n\t\t};\n\t};\n\tlong: 64;\n};\n\nstruct hns3_enet_ring_group {\n\tstruct hns3_enet_ring *ring;\n\tu64 total_bytes;\n\tu64 total_packets;\n\tu16 count;\n\tstruct hns3_enet_coalesce coal;\n\tstruct dim dim;\n};\n\nstruct hns3_enet_tqp_vector {\n\tstruct hnae3_handle *handle;\n\tu8 *mask_addr;\n\tint vector_irq;\n\tint irq_init_flag;\n\tu16 idx;\n\tstruct napi_struct napi;\n\tstruct hns3_enet_ring_group rx_group;\n\tstruct hns3_enet_ring_group tx_group;\n\tcpumask_t affinity_mask;\n\tu16 num_tqps;\n\tstruct irq_affinity_notify affinity_notify;\n\tchar name[32];\n\tu64 event_cnt;\n\tlong: 64;\n};\n\nstruct hns3_ethtool_link_ext_state_mapping {\n\tu32 status_code;\n\tenum ethtool_link_ext_state link_ext_state;\n\tu8 link_ext_substate;\n};\n\nstruct hns3_hw_error_info {\n\tenum hnae3_hw_error_type type;\n\tconst char *msg;\n};\n\nstruct hns3_mac_stats {\n\tu64 tx_pause_cnt;\n\tu64 rx_pause_cnt;\n};\n\nstruct hns3_nic_priv {\n\tstruct hnae3_handle *ae_handle;\n\tstruct net_device *netdev;\n\tstruct device *dev;\n\tstruct hns3_enet_ring *ring;\n\tstruct hns3_enet_tqp_vector *tqp_vector;\n\tu16 vector_num;\n\tu8 max_non_tso_bd_num;\n\tu64 tx_timeout_count;\n\tlong unsigned int state;\n\tenum dim_cq_period_mode tx_cqe_mode;\n\tenum dim_cq_period_mode rx_cqe_mode;\n\tstruct hns3_enet_coalesce tx_coal;\n\tstruct hns3_enet_coalesce rx_coal;\n\tu32 tx_copybreak;\n\tu32 rx_copybreak;\n\tu32 min_tx_copybreak;\n\tu32 min_tx_spare_buf_size;\n};\n\nstruct hns3_pflag_desc {\n\tchar name[32];\n\tvoid (*handler)(struct net_device *, bool);\n};\n\nstruct hns3_reset_type_map {\n\tenum ethtool_reset_flags rst_flags;\n\tenum hnae3_reset_type rst_type;\n};\n\nstruct hns3_ring_param {\n\tu32 tx_desc_num;\n\tu32 rx_desc_num;\n\tu32 rx_buf_len;\n};\n\nstruct hns3_rx_ptype {\n\tu32 ptype: 8;\n\tu32 csum_level: 2;\n\tu32 ip_summed: 2;\n\tu32 l3_type: 4;\n\tu32 valid: 1;\n\tu32 hash_type: 3;\n};\n\nstruct hns3_sfp_type {\n\tu8 type;\n\tu8 ext_type;\n};\n\nstruct hns3_stats {\n\tchar stats_string[32];\n\tint stats_offset;\n};\n\nstruct hns3_tx_spare {\n\tdma_addr_t dma;\n\tvoid *buf;\n\tu32 next_to_use;\n\tu32 next_to_clean;\n\tu32 last_to_clean;\n\tu32 len;\n};\n\nstruct hns_gmac_port_mode_cfg {\n\tenum hns_port_mode port_mode;\n\tu32 max_frm_size;\n\tu32 short_runts_thr;\n\tu32 pad_enable;\n\tu32 crc_add;\n\tu32 an_enable;\n\tu32 runt_pkt_en;\n\tu32 strip_pad_en;\n};\n\nstruct mac_priv {\n\tvoid *mac;\n};\n\nstruct mac_entry_idx {\n\tu8 addr[6];\n\tu16 vlan_id: 12;\n\tu16 valid: 1;\n\tu16 qos: 3;\n};\n\nstruct mac_hw_stats {\n\tu64 rx_good_pkts;\n\tu64 rx_good_bytes;\n\tu64 rx_total_pkts;\n\tu64 rx_total_bytes;\n\tu64 rx_bad_bytes;\n\tu64 rx_uc_pkts;\n\tu64 rx_mc_pkts;\n\tu64 rx_bc_pkts;\n\tu64 rx_fragment_err;\n\tu64 rx_undersize;\n\tu64 rx_under_min;\n\tu64 rx_minto64;\n\tu64 rx_64bytes;\n\tu64 rx_65to127;\n\tu64 rx_128to255;\n\tu64 rx_256to511;\n\tu64 rx_512to1023;\n\tu64 rx_1024to1518;\n\tu64 rx_1519tomax;\n\tu64 rx_1519tomax_good;\n\tu64 rx_oversize;\n\tu64 rx_jabber_err;\n\tu64 rx_fcs_err;\n\tu64 rx_vlan_pkts;\n\tu64 rx_data_err;\n\tu64 rx_align_err;\n\tu64 rx_long_err;\n\tu64 rx_pfc_tc0;\n\tu64 rx_pfc_tc1;\n\tu64 rx_pfc_tc2;\n\tu64 rx_pfc_tc3;\n\tu64 rx_pfc_tc4;\n\tu64 rx_pfc_tc5;\n\tu64 rx_pfc_tc6;\n\tu64 rx_pfc_tc7;\n\tu64 rx_unknown_ctrl;\n\tu64 rx_filter_pkts;\n\tu64 rx_filter_bytes;\n\tu64 rx_fifo_overrun_err;\n\tu64 rx_len_err;\n\tu64 rx_comma_err;\n\tu64 rx_symbol_err;\n\tu64 tx_good_to_sw;\n\tu64 tx_bad_to_sw;\n\tu64 rx_1731_pkts;\n\tu64 tx_good_bytes;\n\tu64 tx_good_pkts;\n\tu64 tx_total_bytes;\n\tu64 tx_total_pkts;\n\tu64 tx_bad_bytes;\n\tu64 tx_bad_pkts;\n\tu64 tx_uc_pkts;\n\tu64 tx_mc_pkts;\n\tu64 tx_bc_pkts;\n\tu64 tx_undersize;\n\tu64 tx_fragment_err;\n\tu64 tx_under_min_pkts;\n\tu64 tx_64bytes;\n\tu64 tx_65to127;\n\tu64 tx_128to255;\n\tu64 tx_256to511;\n\tu64 tx_512to1023;\n\tu64 tx_1024to1518;\n\tu64 tx_1519tomax;\n\tu64 tx_1519tomax_good;\n\tu64 tx_oversize;\n\tu64 tx_jabber_err;\n\tu64 tx_underrun_err;\n\tu64 tx_vlan;\n\tu64 tx_crc_err;\n\tu64 tx_pfc_tc0;\n\tu64 tx_pfc_tc1;\n\tu64 tx_pfc_tc2;\n\tu64 tx_pfc_tc3;\n\tu64 tx_pfc_tc4;\n\tu64 tx_pfc_tc5;\n\tu64 tx_pfc_tc6;\n\tu64 tx_pfc_tc7;\n\tu64 tx_ctrl;\n\tu64 tx_1731_pkts;\n\tu64 tx_1588_pkts;\n\tu64 rx_good_from_sw;\n\tu64 rx_bad_from_sw;\n};\n\nstruct hns_mac_cb {\n\tstruct device *dev;\n\tstruct dsaf_device *dsaf_dev;\n\tstruct mac_priv priv;\n\tstruct fwnode_handle *fw_port;\n\tu8 *vaddr;\n\tu8 *sys_ctl_vaddr;\n\tu8 *serdes_vaddr;\n\tstruct regmap *serdes_ctrl;\n\tstruct regmap *cpld_ctrl;\n\tchar mc_mask[6];\n\tu32 cpld_ctrl_reg;\n\tu32 port_rst_off;\n\tu32 port_mode_off;\n\tstruct mac_entry_idx addr_entry_idx[128];\n\tu8 sfp_prsnt;\n\tu8 cpld_led_value;\n\tu8 mac_id;\n\tu8 link;\n\tu8 half_duplex;\n\tu16 speed;\n\tu16 max_speed;\n\tu16 max_frm;\n\tu16 tx_pause_frm_time;\n\tu32 if_support;\n\tu64 txpkt_for_led;\n\tu64 rxpkt_for_led;\n\tenum hnae_port_type mac_type;\n\tenum hnae_media_type media_type;\n\tphy_interface_t phy_if;\n\tenum hnae_loop loop_mode;\n\tstruct phy_device *phy_dev;\n\tstruct mac_hw_stats hw_stats;\n};\n\nstruct hns_mdio_sc_reg {\n\tu16 mdio_clk_en;\n\tu16 mdio_clk_dis;\n\tu16 mdio_reset_req;\n\tu16 mdio_reset_dreq;\n\tu16 mdio_clk_st;\n\tu16 mdio_reset_st;\n};\n\nstruct hns_mdio_device {\n\tu8 *vbase;\n\tstruct regmap *subctrl_vbase;\n\tstruct hns_mdio_sc_reg sc_reg;\n};\n\nstruct hns_nic_ops {\n\tvoid (*fill_desc)(struct hnae_ring *, void *, int, dma_addr_t, int, int, enum hns_desc_type, int, bool);\n\tint (*maybe_stop_tx)(struct sk_buff **, int *, struct hnae_ring *);\n\tvoid (*get_rxd_bnum)(u32, int *);\n};\n\nstruct hns_nic_ring_data;\n\nstruct hns_nic_priv {\n\tconst struct fwnode_handle *fwnode;\n\tu32 enet_ver;\n\tu32 port_id;\n\tint phy_mode;\n\tint phy_led_val;\n\tstruct net_device *netdev;\n\tstruct device *dev;\n\tstruct hnae_handle *ae_handle;\n\tstruct hns_nic_ops ops;\n\tstruct hns_nic_ring_data *ring_data;\n\tint link;\n\tu64 tx_timeout_count;\n\tlong unsigned int state;\n\tstruct timer_list service_timer;\n\tstruct work_struct service_task;\n\tstruct notifier_block notifier_block;\n};\n\nstruct hns_nic_ring_data {\n\tstruct hnae_ring *ring;\n\tstruct napi_struct napi;\n\tcpumask_t mask;\n\tu32 queue_index;\n\tint (*poll_one)(struct hns_nic_ring_data *, int, void *);\n\tvoid (*ex_process)(struct hns_nic_ring_data *, struct sk_buff *);\n\tbool (*fini_process)(struct hns_nic_ring_data *);\n};\n\nstruct hns_ppe_hw_stats {\n\tu64 rx_pkts_from_sw;\n\tu64 rx_pkts;\n\tu64 rx_drop_no_bd;\n\tu64 rx_alloc_buf_fail;\n\tu64 rx_alloc_buf_wait;\n\tu64 rx_drop_no_buf;\n\tu64 rx_err_fifo_full;\n\tu64 tx_bd_form_rcb;\n\tu64 tx_pkts_from_rcb;\n\tu64 tx_pkts;\n\tu64 tx_err_fifo_empty;\n\tu64 tx_err_checksum;\n};\n\nstruct hns_ppe_cb {\n\tstruct device *dev;\n\tstruct hns_ppe_cb *next;\n\tstruct ppe_common_cb *ppe_common_cb;\n\tstruct hns_ppe_hw_stats hw_stats;\n\tu8 index;\n\tu8 *io_base;\n\tint virq;\n\tu32 rss_indir_table[256];\n\tu32 rss_key[10];\n};\n\nstruct hns_ring_hw_stats {\n\tu64 tx_pkts;\n\tu64 ppe_tx_ok_pkts;\n\tu64 ppe_tx_drop_pkts;\n\tu64 rx_pkts;\n\tu64 ppe_rx_ok_pkts;\n\tu64 ppe_rx_drop_pkts;\n};\n\nstruct kvm_vmid {\n\tatomic64_t id;\n};\n\nstruct kvm_mmu_memory_cache {\n\tgfp_t gfp_zero;\n\tgfp_t gfp_custom;\n\tu64 init_value;\n\tstruct kmem_cache *kmem_cache;\n\tint capacity;\n\tint nobjs;\n\tvoid **objects;\n};\n\nstruct kvm_pgtable;\n\nstruct kvm_arch;\n\nstruct kvm_s2_mmu {\n\tstruct kvm_vmid vmid;\n\tphys_addr_t pgd_phys;\n\tstruct kvm_pgtable *pgt;\n\tu64 vtcr;\n\tint *last_vcpu_ran;\n\tstruct kvm_mmu_memory_cache split_page_cache;\n\tuint64_t split_page_chunk_size;\n\tstruct kvm_arch *arch;\n\tu64 tlb_vttbr;\n\tu64 tlb_vtcr;\n\tbool nested_stage2_enabled;\n\tbool pending_unmap;\n\tatomic_t refcnt;\n};\n\nstruct kvm_vcpu;\n\nstruct vgic_its;\n\nstruct vgic_register_region;\n\nstruct vgic_io_device {\n\tgpa_t base_addr;\n\tunion {\n\t\tstruct kvm_vcpu *redist_vcpu;\n\t\tstruct vgic_its *its;\n\t};\n\tconst struct vgic_register_region *regions;\n\tenum iodev_type iodev_type;\n\tint nr_regions;\n\tstruct kvm_io_device dev;\n};\n\nstruct its_vpe;\n\nstruct its_vm {\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *domain;\n\tstruct page *vprop_page;\n\tstruct its_vpe **vpes;\n\tint nr_vpes;\n\tirq_hw_number_t db_lpi_base;\n\tlong unsigned int *db_bitmap;\n\tint nr_db_lpis;\n\traw_spinlock_t vmapp_lock;\n\tu32 vlpi_count[16];\n};\n\nstruct vgic_irq;\n\nstruct vgic_dist {\n\tbool in_kernel;\n\tbool ready;\n\tbool initialized;\n\tu32 vgic_model;\n\tu32 implementation_rev;\n\tbool v2_groups_user_writable;\n\tbool msis_require_devid;\n\tint nr_spis;\n\tu32 mi_intid;\n\tatomic_t active_spis;\n\tgpa_t vgic_dist_base;\n\tunion {\n\t\tgpa_t vgic_cpu_base;\n\t\tstruct list_head rd_regions;\n\t};\n\tbool enabled;\n\tbool nassgicap;\n\tbool nassgireq;\n\tstruct vgic_irq *spis;\n\tstruct vgic_io_device dist_iodev;\n\tstruct vgic_io_device cpuif_iodev;\n\tbool has_its;\n\tbool table_write_in_progress;\n\tu64 propbaser;\n\tstruct xarray lpi_xa;\n\tstruct its_vm its_vm;\n};\n\nstruct kvm_smccc_features {\n\tlong unsigned int std_bmap;\n\tlong unsigned int std_hyp_bmap;\n\tlong unsigned int vendor_hyp_bmap;\n\tlong unsigned int vendor_hyp_bmap_2;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct pkvm_mapping;\n\nstruct kvm_hyp_memcache {\n\tphys_addr_t head;\n\tlong unsigned int nr_pages;\n\tstruct pkvm_mapping *mapping;\n\tlong unsigned int flags;\n};\n\nstruct kvm_protected_vm {\n\tpkvm_handle_t handle;\n\tstruct kvm_hyp_memcache teardown_mc;\n\tstruct kvm_hyp_memcache stage2_teardown_mc;\n\tbool is_protected;\n\tbool is_created;\n};\n\nstruct kvm_mpidr_data;\n\nstruct kvm_sysreg_masks;\n\nstruct kvm_arch {\n\tstruct kvm_s2_mmu mmu;\n\tu64 fgu[8];\n\tstruct kvm_s2_mmu *nested_mmus;\n\tsize_t nested_mmus_size;\n\tint nested_mmus_next;\n\tstruct vgic_dist vgic;\n\tstruct arch_timer_vm_data timer_data;\n\tu32 psci_version;\n\tstruct mutex config_lock;\n\tlong unsigned int flags;\n\tlong unsigned int vcpu_features[1];\n\tstruct kvm_mpidr_data *mpidr_data;\n\tlong unsigned int *pmu_filter;\n\tstruct arm_pmu *arm_pmu;\n\tcpumask_var_t supported_cpus;\n\tu8 nr_pmu_counters;\n\tstruct kvm_smccc_features smccc_feat;\n\tstruct maple_tree smccc_filter;\n\tu64 id_regs[56];\n\tu64 midr_el1;\n\tu64 revidr_el1;\n\tu64 aidr_el1;\n\tu64 ctr_el0;\n\tstruct kvm_sysreg_masks *sysreg_masks;\n\tatomic_t vncr_map_count;\n\tstruct kvm_protected_vm pkvm;\n};\n\ntypedef bool (*kvm_pgtable_force_pte_cb_t)(u64, u64, enum kvm_pgtable_prot);\n\nstruct kvm_pgtable_mm_ops;\n\nstruct kvm_pgtable {\n\tunion {\n\t\tstruct rb_root_cached pkvm_mappings;\n\t\tstruct {\n\t\t\tu32 ia_bits;\n\t\t\ts8 start_level;\n\t\t\tkvm_pteref_t pgd;\n\t\t\tstruct kvm_pgtable_mm_ops *mm_ops;\n\t\t\tenum kvm_pgtable_stage2_flags flags;\n\t\t\tkvm_pgtable_force_pte_cb_t force_pte_cb;\n\t\t};\n\t};\n\tstruct kvm_s2_mmu *mmu;\n};\n\nstruct kvm_pgtable_mm_ops {\n\tvoid * (*zalloc_page)(void *);\n\tvoid * (*zalloc_pages_exact)(size_t);\n\tvoid (*free_pages_exact)(void *, size_t);\n\tvoid (*free_unlinked_table)(void *, s8);\n\tvoid (*get_page)(void *);\n\tvoid (*put_page)(void *);\n\tint (*page_count)(void *);\n\tvoid * (*phys_to_virt)(phys_addr_t);\n\tphys_addr_t (*virt_to_phys)(void *);\n\tvoid (*dcache_clean_inval_poc)(void *, size_t);\n\tvoid (*icache_inval_pou)(void *, size_t);\n};\n\nunion hyp_spinlock {\n\tu32 __val;\n\tstruct {\n\t\tu16 owner;\n\t\tu16 next;\n\t};\n};\n\ntypedef union hyp_spinlock hyp_spinlock_t;\n\nstruct host_mmu {\n\tstruct kvm_arch arch;\n\tstruct kvm_pgtable pgt;\n\tstruct kvm_pgtable_mm_ops mm_ops;\n\thyp_spinlock_t lock;\n};\n\nstruct host_to_dev_fis {\n\tu8 fis_type;\n\tu8 flags;\n\tu8 command;\n\tu8 features;\n\tu8 lbal;\n\tunion {\n\t\tu8 lbam;\n\t\tu8 byte_count_low;\n\t};\n\tunion {\n\t\tu8 lbah;\n\t\tu8 byte_count_high;\n\t};\n\tu8 device;\n\tu8 lbal_exp;\n\tu8 lbam_exp;\n\tu8 lbah_exp;\n\tu8 features_exp;\n\tunion {\n\t\tu8 sector_count;\n\t\tu8 interrupt_reason;\n\t};\n\tu8 sector_count_exp;\n\tu8 _r_a;\n\tu8 control;\n\tu32 _r_b;\n};\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct hprobe {\n\tenum hprobe_state state;\n\tint srcu_idx;\n\tstruct uprobe *uprobe;\n};\n\nstruct hpx_type0 {\n\tu32 revision;\n\tu8 cache_line_size;\n\tu8 latency_timer;\n\tu8 enable_serr;\n\tu8 enable_perr;\n};\n\nstruct hpx_type1 {\n\tu32 revision;\n\tu8 max_mem_read;\n\tu8 avg_max_split;\n\tu16 tot_max_split;\n};\n\nstruct hpx_type2 {\n\tu32 revision;\n\tu32 unc_err_mask_and;\n\tu32 unc_err_mask_or;\n\tu32 unc_err_sever_and;\n\tu32 unc_err_sever_or;\n\tu32 cor_err_mask_and;\n\tu32 cor_err_mask_or;\n\tu32 adv_err_cap_and;\n\tu32 adv_err_cap_or;\n\tu16 pci_exp_devctl_and;\n\tu16 pci_exp_devctl_or;\n\tu16 pci_exp_lnkctl_and;\n\tu16 pci_exp_lnkctl_or;\n\tu32 sec_unc_err_sever_and;\n\tu32 sec_unc_err_sever_or;\n\tu32 sec_unc_err_mask_and;\n\tu32 sec_unc_err_mask_or;\n};\n\nstruct hpx_type3 {\n\tu16 device_type;\n\tu16 function_type;\n\tu16 config_space_location;\n\tu16 pci_exp_cap_id;\n\tu16 pci_exp_cap_ver;\n\tu16 pci_exp_vendor_id;\n\tu16 dvsec_id;\n\tu16 dvsec_rev;\n\tu16 match_offset;\n\tu32 match_mask_and;\n\tu32 match_value;\n\tu16 reg_offset;\n\tu32 reg_mask_and;\n\tu32 reg_mask_or;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tktime_t offset;\n\tlong: 64;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tstruct hrtimer_clock_base clock_base[8];\n\tcall_single_data_t csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n};\n\nstruct hs_timing {\n\tu32 drv_phase;\n\tu32 smpl_dly;\n\tu32 smpl_phase_max;\n\tu32 smpl_phase_min;\n};\n\nstruct hsq_slot {\n\tstruct mmc_request *mrq;\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {\n\tstruct mutex resize_lock;\n\tstruct lock_class_key resize_key;\n\tint next_nid_to_alloc;\n\tint next_nid_to_free;\n\tunsigned int order;\n\tunsigned int demote_order;\n\tlong unsigned int mask;\n\tlong unsigned int max_huge_pages;\n\tlong unsigned int nr_huge_pages;\n\tlong unsigned int free_huge_pages;\n\tlong unsigned int resv_huge_pages;\n\tlong unsigned int surplus_huge_pages;\n\tlong unsigned int nr_overcommit_huge_pages;\n\tstruct list_head hugepage_activelist;\n\tstruct list_head hugepage_freelists[16];\n\tunsigned int max_huge_pages_node[16];\n\tunsigned int nr_huge_pages_node[16];\n\tunsigned int free_huge_pages_node[16];\n\tunsigned int surplus_huge_pages_node[16];\n\tchar name[32];\n};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tlong: 0;\n\tchar key[0];\n};\n\nstruct hte_ops;\n\nstruct hte_ts_desc;\n\nstruct hte_device;\n\nstruct hte_chip {\n\tconst char *name;\n\tstruct device *dev;\n\tconst struct hte_ops *ops;\n\tu32 nlines;\n\tint (*xlate_of)(struct hte_chip *, const struct of_phandle_args *, struct hte_ts_desc *, u32 *);\n\tint (*xlate_plat)(struct hte_chip *, struct hte_ts_desc *, u32 *);\n\tbool (*match_from_linedata)(const struct hte_chip *, const struct hte_ts_desc *);\n\tu8 of_hte_n_cells;\n\tstruct hte_device *gdev;\n\tvoid *data;\n};\n\nstruct hte_clk_info {\n\tu64 hz;\n\tclockid_t type;\n};\n\nstruct hte_ts_data;\n\ntypedef enum hte_return (*hte_ts_cb_t)(struct hte_ts_data *, void *);\n\ntypedef enum hte_return (*hte_ts_sec_cb_t)(void *);\n\nstruct hte_ts_info {\n\tu32 xlated_id;\n\tlong unsigned int flags;\n\tlong unsigned int hte_cb_flags;\n\tu64 seq;\n\tchar *line_name;\n\tbool free_attr_name;\n\thte_ts_cb_t cb;\n\thte_ts_sec_cb_t tcb;\n\tatomic_t dropped_ts;\n\tspinlock_t slock;\n\tstruct work_struct cb_work;\n\tstruct mutex req_mlock;\n\tstruct dentry *ts_dbg_root;\n\tstruct hte_device *gdev;\n\tvoid *cl_data;\n};\n\nstruct hte_device {\n\tu32 nlines;\n\tatomic_t ts_req;\n\tstruct device *sdev;\n\tstruct dentry *dbg_root;\n\tstruct list_head list;\n\tstruct hte_chip *chip;\n\tstruct module *owner;\n\tstruct hte_ts_info ei[0];\n};\n\nstruct hte_line_attr {\n\tu32 line_id;\n\tvoid *line_data;\n\tlong unsigned int edge_flags;\n\tconst char *name;\n};\n\nstruct hte_ops {\n\tint (*request)(struct hte_chip *, struct hte_ts_desc *, u32);\n\tint (*release)(struct hte_chip *, struct hte_ts_desc *, u32);\n\tint (*enable)(struct hte_chip *, u32);\n\tint (*disable)(struct hte_chip *, u32);\n\tint (*get_clk_src_info)(struct hte_chip *, struct hte_clk_info *);\n};\n\nstruct hte_slices {\n\tu32 r_val;\n\tlong unsigned int flags;\n\tspinlock_t s_lock;\n};\n\nstruct hte_ts_data {\n\tu64 tsc;\n\tu64 seq;\n\tint raw_level;\n};\n\nstruct hte_ts_desc {\n\tstruct hte_line_attr attr;\n\tvoid *hte_data;\n};\n\nstruct huge_bootmem_page {\n\tstruct list_head list;\n\tstruct hstate *hstate;\n\tlong unsigned int flags;\n\tstruct cma *cma;\n};\n\nstruct hugepage_subpool {\n\tspinlock_t lock;\n\tlong int count;\n\tlong int max_hpages;\n\tlong int used_hpages;\n\tstruct hstate *hstate;\n\tlong int min_hpages;\n\tlong int rsv_hpages;\n};\n\nstruct page_counter {\n\tatomic_long_t usage;\n\tlong unsigned int failcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int emin;\n\tatomic_long_t min_usage;\n\tatomic_long_t children_min_usage;\n\tlong unsigned int elow;\n\tatomic_long_t low_usage;\n\tatomic_long_t children_low_usage;\n\tlong unsigned int watermark;\n\tlong unsigned int local_watermark;\n\tstruct cacheline_padding _pad2_;\n\tbool protection_support;\n\tbool track_failcnt;\n\tlong unsigned int min;\n\tlong unsigned int low;\n\tlong unsigned int high;\n\tlong unsigned int max;\n\tstruct page_counter *parent;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hugetlb_cgroup_per_node;\n\nstruct hugetlb_cgroup {\n\tstruct cgroup_subsys_state css;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter hugepage[4];\n\tstruct page_counter rsvd_hugepage[4];\n\tatomic_long_t events[4];\n\tatomic_long_t events_local[4];\n\tstruct cgroup_file events_file[4];\n\tstruct cgroup_file events_local_file[4];\n\tstruct hugetlb_cgroup_per_node *nodeinfo[0];\n};\n\nstruct hugetlb_cgroup_per_node {\n\tlong unsigned int usage[4];\n};\n\nstruct hugetlb_cmdline {\n\tchar *val;\n\tint (*setup)(char *);\n};\n\nstruct hugetlb_vma_lock {\n\tstruct kref refs;\n\tstruct rw_semaphore rw_sema;\n\tstruct vm_area_struct *vma;\n};\n\nstruct hugetlbfs_fs_context {\n\tstruct hstate *hstate;\n\tlong long unsigned int max_size_opt;\n\tlong long unsigned int min_size_opt;\n\tlong int max_hpages;\n\tlong int nr_inodes;\n\tlong int min_hpages;\n\tenum hugetlbfs_size_type max_val_type;\n\tenum hugetlbfs_size_type min_val_type;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hugetlbfs_inode_info {\n\tstruct inode vfs_inode;\n\tunsigned int seals;\n};\n\nstruct hugetlbfs_sb_info {\n\tlong int max_inodes;\n\tlong int free_inodes;\n\tspinlock_t stat_lock;\n\tstruct hstate *hstate;\n\tstruct hugepage_subpool *spool;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct hw_info {\n\tu8 bgx_cnt;\n\tu8 chans_per_lmac;\n\tu8 chans_per_bgx;\n\tu8 chans_per_rgx;\n\tu8 chans_per_lbk;\n\tu16 cpi_cnt;\n\tu16 rssi_cnt;\n\tu16 rss_ind_tbl_size;\n\tu16 tl4_cnt;\n\tu16 tl3_cnt;\n\tu8 tl2_cnt;\n\tu8 tl1_cnt;\n\tbool tl1_per_bgx;\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 config1;\n\t\t\tu64 last_tag;\n\t\t\tu64 dyn_constraint;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tu64 aux_config;\n\t\t\tunsigned int aux_paused;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tstruct arch_hw_breakpoint info;\n\t\t\tstruct rhlist_head bp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tunion {\n\t\tstruct {\n\t\t\tu64 last_period;\n\t\t\tlocal64_t period_left;\n\t\t};\n\t\tstruct {\n\t\t\tu64 saved_metric;\n\t\t\tu64 saved_slots;\n\t\t};\n\t};\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hw_prober_entry {\n\tconst char *compatible;\n\tint (*prober)(struct device *, const void *);\n\tconst void *data;\n};\n\nstruct hwbm_pool {\n\tint size;\n\tint frag_size;\n\tint buf_num;\n\tint (*construct)(struct hwbm_pool *, void *);\n\tstruct mutex buf_lock;\n\tvoid *priv;\n};\n\nstruct hwerr_info {\n\tatomic_t count;\n\ttime64_t timestamp;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n};\n\nstruct hwmon_attr {\n\tstruct device_attribute dev_attr;\n\tstruct e1000_hw___3 *hw;\n\tstruct e1000_thermal_diode_data *sensor;\n\tchar name[12];\n};\n\nstruct hwmon_buff {\n\tstruct attribute_group group;\n\tconst struct attribute_group *groups[2];\n\tstruct attribute *attrs[13];\n\tstruct hwmon_attr hwmon_list[12];\n\tunsigned int n_hwmon;\n};\n\nstruct hwmon_channel_info {\n\tenum hwmon_sensor_types type;\n\tconst u32 *config;\n};\n\nstruct hwmon_ops;\n\nstruct hwmon_chip_info {\n\tconst struct hwmon_ops *ops;\n\tconst struct hwmon_channel_info * const *info;\n};\n\nstruct hwmon_device {\n\tconst char *name;\n\tconst char *label;\n\tstruct device dev;\n\tconst struct hwmon_chip_info *chip;\n\tstruct mutex lock;\n\tstruct list_head tzdata;\n\tstruct attribute_group group;\n\tconst struct attribute_group **groups;\n};\n\nstruct hwmon_device_attribute {\n\tstruct device_attribute dev_attr;\n\tconst struct hwmon_ops *ops;\n\tenum hwmon_sensor_types type;\n\tu32 attr;\n\tint index;\n\tchar name[32];\n};\n\nstruct hwmon_ops {\n\tumode_t visible;\n\tumode_t (*is_visible)(const void *, enum hwmon_sensor_types, u32, int);\n\tint (*read)(struct device *, enum hwmon_sensor_types, u32, int, long int *);\n\tint (*read_string)(struct device *, enum hwmon_sensor_types, u32, int, const char **);\n\tint (*write)(struct device *, enum hwmon_sensor_types, u32, int, long int);\n};\n\nstruct hwmon_thermal_data {\n\tstruct list_head node;\n\tstruct device *dev;\n\tint index;\n\tstruct thermal_zone_device *tzd;\n};\n\nstruct hwmon_type_attr_list {\n\tconst u32 *attrs;\n\tsize_t n_attrs;\n};\n\nstruct to_kill {\n\tstruct list_head nd;\n\tstruct task_struct *tsk;\n\tlong unsigned int addr;\n\tshort int size_shift;\n};\n\nstruct hwpoison_walk {\n\tstruct to_kill tk;\n\tlong unsigned int pfn;\n\tint flags;\n};\n\nstruct hwspinlock_device;\n\nstruct hwspinlock {\n\tstruct hwspinlock_device *bank;\n\tspinlock_t lock;\n\tvoid *priv;\n};\n\nstruct hwspinlock_ops;\n\nstruct hwspinlock_device {\n\tstruct device *dev;\n\tconst struct hwspinlock_ops *ops;\n\tint base_id;\n\tint num_locks;\n\tstruct hwspinlock lock[0];\n};\n\nstruct hwspinlock_ops {\n\tint (*trylock)(struct hwspinlock *);\n\tvoid (*unlock)(struct hwspinlock *);\n\tint (*bust)(struct hwspinlock *, unsigned int);\n\tvoid (*relax)(struct hwspinlock *);\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct hynix_read_retry;\n\nstruct hynix_nand {\n\tconst struct hynix_read_retry *read_retry;\n};\n\nstruct hynix_read_retry {\n\tint nregs;\n\tconst u8 *regs;\n\tu8 values[0];\n};\n\nstruct hynix_read_retry_otp {\n\tint nregs;\n\tconst u8 *regs;\n\tconst u8 *values;\n\tint page;\n\tint size;\n};\n\nstruct hyp_fixmap_slot {\n\tu64 addr;\n\tkvm_pte_t *ptep;\n};\n\nstruct hyp_map_data {\n\tconst u64 phys;\n\tkvm_pte_t attr;\n};\n\nstruct hyp_page {\n\tu16 refcount;\n\tu8 order;\n\tunsigned int __host_state: 4;\n\tunsigned int __hyp_state_comp: 4;\n\tu32 host_share_guest_count;\n};\n\nstruct hyp_pool {\n\thyp_spinlock_t lock;\n\tstruct list_head free_area[11];\n\tphys_addr_t range_start;\n\tphys_addr_t range_end;\n\tu8 max_order;\n};\n\nstruct hyp_shared_pfn {\n\tu64 pfn;\n\tint count;\n\tstruct rb_node node;\n};\n\nstruct hyp_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct hyp_sysfs_attr *, char *);\n\tssize_t (*store)(struct hyp_sysfs_attr *, const char *, size_t);\n\tunion {\n\t\tvoid *hyp_attr_data;\n\t\tlong unsigned int hyp_attr_value;\n\t};\n};\n\nstruct i2c_acpi_handler_data {\n\tstruct acpi_connection_info info;\n\tstruct i2c_adapter *adapter;\n};\n\nstruct i2c_acpi_irq_context {\n\tint irq;\n\tbool wake_capable;\n};\n\nstruct i2c_board_info;\n\nstruct i2c_acpi_lookup {\n\tstruct i2c_board_info *info;\n\tacpi_handle adapter_handle;\n\tacpi_handle device_handle;\n\tacpi_handle search_handle;\n\tint n;\n\tint index;\n\tu32 speed;\n\tu32 min_speed;\n\tu32 force_speed;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n};\n\nstruct i2c_algo_bit_data {\n\tvoid *data;\n\tvoid (*setsda)(void *, int);\n\tvoid (*setscl)(void *, int);\n\tint (*getsda)(void *);\n\tint (*getscl)(void *);\n\tint (*pre_xfer)(struct i2c_adapter *);\n\tvoid (*post_xfer)(struct i2c_adapter *);\n\tint udelay;\n\tint timeout;\n\tbool can_do_atomic;\n};\n\nunion i2c_smbus_data;\n\nstruct i2c_algorithm {\n\tunion {\n\t\tint (*xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tunion {\n\t\tint (*xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n\tunion {\n\t\tint (*reg_target)(struct i2c_client *);\n\t\tint (*reg_slave)(struct i2c_client *);\n\t};\n\tunion {\n\t\tint (*unreg_target)(struct i2c_client *);\n\t\tint (*unreg_slave)(struct i2c_client *);\n\t};\n};\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\ntypedef int (*i2c_slave_cb_t)(struct i2c_client *, enum i2c_slave_event, u8 *);\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n\ti2c_slave_cb_t slave_cb;\n\tvoid *devres_group_id;\n\tstruct dentry *debugfs;\n};\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct i2c_dev {\n\tstruct list_head list;\n\tstruct i2c_adapter *adap;\n\tstruct device dev;\n\tstruct cdev cdev;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *);\n\tvoid (*remove)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tu32 flags;\n};\n\nstruct i2c_dw_semaphore_callbacks {\n\tint (*probe)(struct dw_i2c_dev *);\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nstruct i2c_msg32 {\n\tu16 addr;\n\tu16 flags;\n\tu16 len;\n\tcompat_caddr_t buf;\n};\n\nstruct i2c_mux_core {\n\tstruct i2c_adapter *parent;\n\tstruct device *dev;\n\tunsigned int mux_locked: 1;\n\tunsigned int arbitrator: 1;\n\tunsigned int gate: 1;\n\tvoid *priv;\n\tint (*select)(struct i2c_mux_core *, u32);\n\tint (*deselect)(struct i2c_mux_core *, u32);\n\tint num_adapters;\n\tint max_adapters;\n\tstruct i2c_adapter *adapter[0];\n};\n\nstruct i2c_mux_priv {\n\tstruct i2c_adapter adap;\n\tstruct i2c_algorithm algo;\n\tstruct i2c_mux_core *muxc;\n\tu32 chan_id;\n};\n\nstruct i2c_of_probe_ops;\n\nstruct i2c_of_probe_cfg {\n\tconst struct i2c_of_probe_ops *ops;\n\tconst char *type;\n};\n\nstruct i2c_of_probe_ops {\n\tint (*enable)(struct device *, struct device_node *, void *);\n\tvoid (*cleanup_early)(struct device *, void *);\n\tvoid (*cleanup)(struct device *, void *);\n};\n\nstruct i2c_of_probe_simple_ctx {\n\tconst struct i2c_of_probe_simple_opts *opts;\n\tstruct regulator *supply;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct i2c_of_probe_simple_opts {\n\tconst char *res_node_compatible;\n\tconst char *supply_name;\n\tconst char *gpio_name;\n\tunsigned int post_power_on_delay_ms;\n\tunsigned int post_gpio_config_delay_ms;\n\tbool gpio_assert_to_enable;\n};\n\nstruct i2c_pxa_platform_data {\n\tunsigned int class;\n\tunsigned int use_pio: 1;\n\tunsigned int fast_mode: 1;\n\tunsigned int high_mode: 1;\n\tunsigned char master_code;\n\tlong unsigned int rate;\n};\n\nstruct i2c_rdwr_ioctl_data {\n\tstruct i2c_msg *msgs;\n\t__u32 nmsgs;\n};\n\nstruct i2c_rdwr_ioctl_data32 {\n\tcompat_caddr_t msgs;\n\tu32 nmsgs;\n};\n\nstruct i2c_slave_host_notify_status {\n\tu8 index;\n\tu8 addr;\n};\n\nstruct i2c_smbus_alert {\n\tstruct work_struct alert;\n\tstruct i2c_client *ara;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct i2c_smbus_ioctl_data {\n\t__u8 read_write;\n\t__u8 command;\n\t__u32 size;\n\tunion i2c_smbus_data *data;\n};\n\nstruct i2c_smbus_ioctl_data32 {\n\tu8 read_write;\n\tu8 command;\n\tu32 size;\n\tcompat_caddr_t data;\n};\n\nstruct i2c_spec_values {\n\tlong unsigned int min_hold_start_ns;\n\tlong unsigned int min_low_ns;\n\tlong unsigned int min_high_ns;\n\tlong unsigned int min_setup_start_ns;\n\tlong unsigned int max_data_hold_ns;\n\tlong unsigned int min_data_setup_ns;\n\tlong unsigned int min_setup_stop_ns;\n\tlong unsigned int min_hold_buffer_ns;\n};\n\nstruct i2c_spec_values___2 {\n\tunsigned int min_low_ns;\n\tunsigned int min_su_sta_ns;\n\tunsigned int max_hd_dat_ns;\n\tunsigned int min_su_dat_ns;\n};\n\nstruct iaffid_entry {\n\tu16 iaffid;\n\tbool valid;\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n};\n\nstruct ib_pd;\n\nstruct ib_uobject;\n\nstruct ib_gid_attr;\n\nstruct ib_ah {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tconst struct ib_gid_attr *sgid_attr;\n\tenum rdma_ah_attr_type type;\n};\n\nstruct ib_ah_attr {\n\tu16 dlid;\n\tu8 src_path_bits;\n};\n\nstruct ib_core_device {\n\tstruct device dev;\n\tpossible_net_t rdma_net;\n\tstruct kobject *ports_kobj;\n\tstruct list_head port_list;\n\tstruct ib_device *owner;\n};\n\nstruct ib_counters {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_counters_read_attr {\n\tu64 *counters_buff;\n\tu32 ncounters;\n\tu32 flags;\n};\n\nstruct ib_ucq_object;\n\nstruct ib_cq;\n\ntypedef void (*ib_comp_handler)(struct ib_cq *, void *);\n\nstruct irq_poll;\n\ntypedef int irq_poll_fn(struct irq_poll *, int);\n\nstruct irq_poll {\n\tstruct list_head list;\n\tlong unsigned int state;\n\tint weight;\n\tirq_poll_fn *poll;\n};\n\nstruct rdma_restrack_entry {\n\tbool valid;\n\tu8 no_track: 1;\n\tstruct kref kref;\n\tstruct completion comp;\n\tstruct task_struct *task;\n\tconst char *kern_name;\n\tenum rdma_restrack_type type;\n\tbool user;\n\tu32 id;\n};\n\nstruct ib_event;\n\nstruct ib_wc;\n\nstruct ib_cq {\n\tstruct ib_device *device;\n\tstruct ib_ucq_object *uobject;\n\tib_comp_handler comp_handler;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *cq_context;\n\tint cqe;\n\tunsigned int cqe_used;\n\tatomic_t usecnt;\n\tenum ib_poll_context poll_ctx;\n\tstruct ib_wc *wc;\n\tstruct list_head pool_entry;\n\tunion {\n\t\tstruct irq_poll iop;\n\t\tstruct work_struct work;\n\t};\n\tstruct workqueue_struct *comp_wq;\n\tstruct dim *dim;\n\tktime_t timestamp;\n\tu8 interrupt: 1;\n\tu8 shared: 1;\n\tunsigned int comp_vector;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_cq_caps {\n\tu16 max_cq_moderation_count;\n\tu16 max_cq_moderation_period;\n};\n\nstruct ib_cq_init_attr {\n\tunsigned int cqe;\n\tu32 comp_vector;\n\tu32 flags;\n};\n\nstruct ib_cqe {\n\tvoid (*done)(struct ib_cq *, struct ib_wc *);\n};\n\nstruct ib_mad;\n\nstruct uverbs_attr_bundle;\n\nstruct ib_umem;\n\nstruct rdma_cm_id;\n\nstruct iw_cm_id;\n\nstruct iw_cm_conn_param;\n\nstruct ib_uverbs_file;\n\nstruct ib_qp;\n\nstruct ib_send_wr;\n\nstruct ib_recv_wr;\n\nstruct ib_srq;\n\nstruct ib_grh;\n\nstruct ib_device_attr;\n\nstruct ib_udata;\n\nstruct ib_device_modify;\n\nstruct ib_port_attr;\n\nstruct ib_port_modify;\n\nstruct ib_port_immutable;\n\nstruct rdma_netdev_alloc_params;\n\nunion ib_gid;\n\nstruct ib_ucontext;\n\nstruct rdma_user_mmap_entry;\n\nstruct phys_vec;\n\nstruct rdma_ah_init_attr;\n\nstruct rdma_ah_attr;\n\nstruct ib_srq_init_attr;\n\nstruct ib_srq_attr;\n\nstruct ib_qp_init_attr;\n\nstruct ib_qp_attr;\n\nstruct ib_mr;\n\nstruct ib_dmah;\n\nstruct ib_sge;\n\nstruct ib_mr_status;\n\nstruct ib_mw;\n\nstruct ib_xrcd;\n\nstruct ib_flow;\n\nstruct ib_flow_attr;\n\nstruct ib_flow_action;\n\nstruct ifla_vf_stats;\n\nstruct ifla_vf_guid;\n\nstruct ib_wq;\n\nstruct ib_wq_init_attr;\n\nstruct ib_wq_attr;\n\nstruct ib_rwq_ind_table;\n\nstruct ib_rwq_ind_table_init_attr;\n\nstruct ib_dm;\n\nstruct ib_dm_alloc_attr;\n\nstruct ib_dm_mr_attr;\n\nstruct rdma_hw_stats;\n\nstruct rdma_counter;\n\nstruct ib_device_ops {\n\tstruct module *owner;\n\tenum rdma_driver_id driver_id;\n\tu32 uverbs_abi_ver;\n\tunsigned int uverbs_no_driver_id_binding: 1;\n\tconst struct attribute_group *device_group;\n\tconst struct attribute_group **port_groups;\n\tint (*post_send)(struct ib_qp *, const struct ib_send_wr *, const struct ib_send_wr **);\n\tint (*post_recv)(struct ib_qp *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tvoid (*drain_rq)(struct ib_qp *);\n\tvoid (*drain_sq)(struct ib_qp *);\n\tint (*poll_cq)(struct ib_cq *, int, struct ib_wc *);\n\tint (*peek_cq)(struct ib_cq *, int);\n\tint (*req_notify_cq)(struct ib_cq *, enum ib_cq_notify_flags);\n\tint (*post_srq_recv)(struct ib_srq *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tint (*process_mad)(struct ib_device *, int, u32, const struct ib_wc *, const struct ib_grh *, const struct ib_mad *, struct ib_mad *, size_t *, u16 *);\n\tint (*query_device)(struct ib_device *, struct ib_device_attr *, struct ib_udata *);\n\tint (*modify_device)(struct ib_device *, int, struct ib_device_modify *);\n\tvoid (*get_dev_fw_str)(struct ib_device *, char *);\n\tconst struct cpumask * (*get_vector_affinity)(struct ib_device *, int);\n\tint (*query_port)(struct ib_device *, u32, struct ib_port_attr *);\n\tint (*query_port_speed)(struct ib_device *, u32, u64 *);\n\tint (*modify_port)(struct ib_device *, u32, int, struct ib_port_modify *);\n\tint (*get_port_immutable)(struct ib_device *, u32, struct ib_port_immutable *);\n\tenum rdma_link_layer (*get_link_layer)(struct ib_device *, u32);\n\tstruct net_device * (*get_netdev)(struct ib_device *, u32);\n\tstruct net_device * (*alloc_rdma_netdev)(struct ib_device *, u32, enum rdma_netdev_t, const char *, unsigned char, void (*)(struct net_device *));\n\tint (*rdma_netdev_get_params)(struct ib_device *, u32, enum rdma_netdev_t, struct rdma_netdev_alloc_params *);\n\tint (*query_gid)(struct ib_device *, u32, int, union ib_gid *);\n\tint (*add_gid)(const struct ib_gid_attr *, void **);\n\tint (*del_gid)(const struct ib_gid_attr *, void **);\n\tint (*query_pkey)(struct ib_device *, u32, u16, u16 *);\n\tint (*alloc_ucontext)(struct ib_ucontext *, struct ib_udata *);\n\tvoid (*dealloc_ucontext)(struct ib_ucontext *);\n\tint (*mmap)(struct ib_ucontext *, struct vm_area_struct *);\n\tvoid (*mmap_free)(struct rdma_user_mmap_entry *);\n\tint (*mmap_get_pfns)(struct rdma_user_mmap_entry *, struct phys_vec *, struct p2pdma_provider **);\n\tstruct rdma_user_mmap_entry * (*pgoff_to_mmap_entry)(struct ib_ucontext *, off_t);\n\tvoid (*disassociate_ucontext)(struct ib_ucontext *);\n\tint (*alloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*dealloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*create_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*create_user_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*modify_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*query_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*destroy_ah)(struct ib_ah *, u32);\n\tint (*create_srq)(struct ib_srq *, struct ib_srq_init_attr *, struct ib_udata *);\n\tint (*modify_srq)(struct ib_srq *, struct ib_srq_attr *, enum ib_srq_attr_mask, struct ib_udata *);\n\tint (*query_srq)(struct ib_srq *, struct ib_srq_attr *);\n\tint (*destroy_srq)(struct ib_srq *, struct ib_udata *);\n\tint (*create_qp)(struct ib_qp *, struct ib_qp_init_attr *, struct ib_udata *);\n\tint (*modify_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);\n\tint (*query_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_qp_init_attr *);\n\tint (*destroy_qp)(struct ib_qp *, struct ib_udata *);\n\tint (*create_cq)(struct ib_cq *, const struct ib_cq_init_attr *, struct uverbs_attr_bundle *);\n\tint (*create_cq_umem)(struct ib_cq *, const struct ib_cq_init_attr *, struct ib_umem *, struct uverbs_attr_bundle *);\n\tint (*modify_cq)(struct ib_cq *, u16, u16);\n\tint (*destroy_cq)(struct ib_cq *, struct ib_udata *);\n\tint (*resize_cq)(struct ib_cq *, int, struct ib_udata *);\n\tint (*pre_destroy_cq)(struct ib_cq *);\n\tvoid (*post_destroy_cq)(struct ib_cq *);\n\tstruct ib_mr * (*get_dma_mr)(struct ib_pd *, int);\n\tstruct ib_mr * (*reg_user_mr)(struct ib_pd *, u64, u64, u64, int, struct ib_dmah *, struct ib_udata *);\n\tstruct ib_mr * (*reg_user_mr_dmabuf)(struct ib_pd *, u64, u64, u64, int, int, struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*rereg_user_mr)(struct ib_mr *, int, u64, u64, u64, int, struct ib_pd *, struct ib_udata *);\n\tint (*dereg_mr)(struct ib_mr *, struct ib_udata *);\n\tstruct ib_mr * (*alloc_mr)(struct ib_pd *, enum ib_mr_type, u32);\n\tstruct ib_mr * (*alloc_mr_integrity)(struct ib_pd *, u32, u32);\n\tint (*advise_mr)(struct ib_pd *, enum ib_uverbs_advise_mr_advice, u32, struct ib_sge *, u32, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg)(struct ib_mr *, struct scatterlist *, int, unsigned int *);\n\tint (*check_mr_status)(struct ib_mr *, u32, struct ib_mr_status *);\n\tint (*alloc_mw)(struct ib_mw *, struct ib_udata *);\n\tint (*dealloc_mw)(struct ib_mw *);\n\tint (*attach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*detach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*alloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tint (*dealloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tstruct ib_flow * (*create_flow)(struct ib_qp *, struct ib_flow_attr *, struct ib_udata *);\n\tint (*destroy_flow)(struct ib_flow *);\n\tint (*destroy_flow_action)(struct ib_flow_action *);\n\tint (*set_vf_link_state)(struct ib_device *, int, u32, int);\n\tint (*get_vf_config)(struct ib_device *, int, u32, struct ifla_vf_info *);\n\tint (*get_vf_stats)(struct ib_device *, int, u32, struct ifla_vf_stats *);\n\tint (*get_vf_guid)(struct ib_device *, int, u32, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*set_vf_guid)(struct ib_device *, int, u32, u64, int);\n\tstruct ib_wq * (*create_wq)(struct ib_pd *, struct ib_wq_init_attr *, struct ib_udata *);\n\tint (*destroy_wq)(struct ib_wq *, struct ib_udata *);\n\tint (*modify_wq)(struct ib_wq *, struct ib_wq_attr *, u32, struct ib_udata *);\n\tint (*create_rwq_ind_table)(struct ib_rwq_ind_table *, struct ib_rwq_ind_table_init_attr *, struct ib_udata *);\n\tint (*destroy_rwq_ind_table)(struct ib_rwq_ind_table *);\n\tstruct ib_dm * (*alloc_dm)(struct ib_device *, struct ib_ucontext *, struct ib_dm_alloc_attr *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dm)(struct ib_dm *, struct uverbs_attr_bundle *);\n\tint (*alloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*reg_dm_mr)(struct ib_pd *, struct ib_dm *, struct ib_dm_mr_attr *, struct uverbs_attr_bundle *);\n\tint (*create_counters)(struct ib_counters *, struct uverbs_attr_bundle *);\n\tint (*destroy_counters)(struct ib_counters *);\n\tint (*read_counters)(struct ib_counters *, struct ib_counters_read_attr *, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg_pi)(struct ib_mr *, struct scatterlist *, int, unsigned int *, struct scatterlist *, int, unsigned int *);\n\tstruct rdma_hw_stats * (*alloc_hw_device_stats)(struct ib_device *);\n\tstruct rdma_hw_stats * (*alloc_hw_port_stats)(struct ib_device *, u32);\n\tint (*get_hw_stats)(struct ib_device *, struct rdma_hw_stats *, u32, int);\n\tint (*modify_hw_stat)(struct ib_device *, u32, unsigned int, bool);\n\tint (*fill_res_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_mr_entry_raw)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_cq_entry)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_cq_entry_raw)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_qp_entry)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_qp_entry_raw)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_cm_id_entry)(struct sk_buff *, struct rdma_cm_id *);\n\tint (*fill_res_srq_entry)(struct sk_buff *, struct ib_srq *);\n\tint (*fill_res_srq_entry_raw)(struct sk_buff *, struct ib_srq *);\n\tint (*enable_driver)(struct ib_device *);\n\tvoid (*dealloc_driver)(struct ib_device *);\n\tvoid (*iw_add_ref)(struct ib_qp *);\n\tvoid (*iw_rem_ref)(struct ib_qp *);\n\tstruct ib_qp * (*iw_get_qp)(struct ib_device *, int);\n\tint (*iw_connect)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_accept)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_reject)(struct iw_cm_id *, const void *, u8);\n\tint (*iw_create_listen)(struct iw_cm_id *, int);\n\tint (*iw_destroy_listen)(struct iw_cm_id *);\n\tint (*counter_bind_qp)(struct rdma_counter *, struct ib_qp *, u32);\n\tint (*counter_unbind_qp)(struct ib_qp *, u32);\n\tint (*counter_dealloc)(struct rdma_counter *);\n\tstruct rdma_hw_stats * (*counter_alloc_stats)(struct rdma_counter *);\n\tint (*counter_update_stats)(struct rdma_counter *);\n\tvoid (*counter_init)(struct rdma_counter *);\n\tint (*fill_stat_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*query_ucontext)(struct ib_ucontext *, struct uverbs_attr_bundle *);\n\tint (*get_numa_node)(struct ib_device *);\n\tstruct ib_device * (*add_sub_dev)(struct ib_device *, enum rdma_nl_dev_type, const char *);\n\tvoid (*del_sub_dev)(struct ib_device *);\n\tvoid (*ufile_hw_cleanup)(struct ib_uverbs_file *);\n\tvoid (*report_port_event)(struct ib_device *, struct net_device *, long unsigned int);\n\tsize_t size_ib_ah;\n\tsize_t size_ib_counters;\n\tsize_t size_ib_cq;\n\tsize_t size_ib_dmah;\n\tsize_t size_ib_mw;\n\tsize_t size_ib_pd;\n\tsize_t size_ib_qp;\n\tsize_t size_ib_rwq_ind_table;\n\tsize_t size_ib_srq;\n\tsize_t size_ib_ucontext;\n\tsize_t size_ib_xrcd;\n\tsize_t size_rdma_counter;\n};\n\nstruct ib_odp_caps {\n\tuint64_t general_caps;\n\tstruct {\n\t\tuint32_t rc_odp_caps;\n\t\tuint32_t uc_odp_caps;\n\t\tuint32_t ud_odp_caps;\n\t\tuint32_t xrc_odp_caps;\n\t} per_transport_caps;\n};\n\nstruct ib_rss_caps {\n\tu32 supported_qpts;\n\tu32 max_rwq_indirection_tables;\n\tu32 max_rwq_indirection_table_size;\n};\n\nstruct ib_tm_caps {\n\tu32 max_rndv_hdr_size;\n\tu32 max_num_tags;\n\tu32 flags;\n\tu32 max_ops;\n\tu32 max_sge;\n};\n\nstruct ib_device_attr {\n\tu64 fw_ver;\n\t__be64 sys_image_guid;\n\tu64 max_mr_size;\n\tu64 page_size_cap;\n\tu32 vendor_id;\n\tu32 vendor_part_id;\n\tu32 hw_ver;\n\tint max_qp;\n\tint max_qp_wr;\n\tu64 device_cap_flags;\n\tu64 kernel_cap_flags;\n\tint max_send_sge;\n\tint max_recv_sge;\n\tint max_sge_rd;\n\tint max_cq;\n\tint max_cqe;\n\tint max_mr;\n\tint max_pd;\n\tint max_qp_rd_atom;\n\tint max_ee_rd_atom;\n\tint max_res_rd_atom;\n\tint max_qp_init_rd_atom;\n\tint max_ee_init_rd_atom;\n\tenum ib_atomic_cap atomic_cap;\n\tenum ib_atomic_cap masked_atomic_cap;\n\tint max_ee;\n\tint max_rdd;\n\tint max_mw;\n\tint max_raw_ipv6_qp;\n\tint max_raw_ethy_qp;\n\tint max_mcast_grp;\n\tint max_mcast_qp_attach;\n\tint max_total_mcast_qp_attach;\n\tint max_ah;\n\tint max_srq;\n\tint max_srq_wr;\n\tint max_srq_sge;\n\tunsigned int max_fast_reg_page_list_len;\n\tunsigned int max_pi_fast_reg_page_list_len;\n\tu16 max_pkeys;\n\tu8 local_ca_ack_delay;\n\tint sig_prot_cap;\n\tint sig_guard_cap;\n\tstruct ib_odp_caps odp_caps;\n\tuint64_t timestamp_mask;\n\tuint64_t hca_core_clock;\n\tstruct ib_rss_caps rss_caps;\n\tu32 max_wq_type_rq;\n\tu32 raw_packet_caps;\n\tstruct ib_tm_caps tm_caps;\n\tstruct ib_cq_caps cq_caps;\n\tu64 max_dm_size;\n\tu32 max_sgl_rd;\n};\n\nstruct hw_stats_device_data;\n\nstruct rdma_restrack_root;\n\nstruct uapi_definition;\n\nstruct ib_port_data;\n\nstruct rdma_link_ops;\n\nstruct ib_device {\n\tstruct device *dma_device;\n\tstruct ib_device_ops ops;\n\tchar name[64];\n\tstruct callback_head callback_head;\n\tstruct list_head event_handler_list;\n\tstruct rw_semaphore event_handler_rwsem;\n\tspinlock_t qp_open_list_lock;\n\tstruct rw_semaphore client_data_rwsem;\n\tstruct xarray client_data;\n\tstruct mutex unregistration_lock;\n\trwlock_t cache_lock;\n\tstruct ib_port_data *port_data;\n\tint num_comp_vectors;\n\tunion {\n\t\tstruct device dev;\n\t\tstruct ib_core_device coredev;\n\t};\n\tconst struct attribute_group *groups[4];\n\tu8 hw_stats_attr_index;\n\tu64 uverbs_cmd_mask;\n\tchar node_desc[64];\n\t__be64 node_guid;\n\tu32 local_dma_lkey;\n\tu16 is_switch: 1;\n\tu16 kverbs_provider: 1;\n\tu16 use_cq_dim: 1;\n\tu8 node_type;\n\tu32 phys_port_cnt;\n\tstruct ib_device_attr attrs;\n\tstruct hw_stats_device_data *hw_stats_data;\n\tu32 index;\n\tspinlock_t cq_pools_lock;\n\tstruct list_head cq_pools[3];\n\tstruct rdma_restrack_root *res;\n\tconst struct uapi_definition *driver_def;\n\trefcount_t refcount;\n\tstruct completion unreg_completion;\n\tstruct work_struct unregistration_work;\n\tconst struct rdma_link_ops *link_ops;\n\tstruct mutex compat_devs_mutex;\n\tstruct xarray compat_devs;\n\tchar iw_ifname[16];\n\tu32 iw_driver_flags;\n\tu32 lag_flags;\n\tstruct mutex subdev_lock;\n\tstruct list_head subdev_list_head;\n\tenum rdma_nl_dev_type type;\n\tstruct ib_device *parent;\n\tstruct list_head subdev_list;\n\tenum rdma_nl_name_assign_type name_assign_type;\n};\n\nstruct ib_device_modify {\n\tu64 sys_image_guid;\n\tchar node_desc[64];\n};\n\nstruct ib_dm {\n\tstruct ib_device *device;\n\tu32 length;\n\tu32 flags;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_dm_alloc_attr {\n\tu64 length;\n\tu32 alignment;\n\tu32 flags;\n};\n\nstruct ib_dm_mr_attr {\n\tu64 length;\n\tu64 offset;\n\tu32 access_flags;\n};\n\nstruct ib_dmah {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tstruct rdma_restrack_entry res;\n\tu32 cpu_id;\n\tenum tph_mem_type mem_type;\n\tatomic_t usecnt;\n\tu8 ph;\n\tu8 valid_fields;\n};\n\nstruct ib_event {\n\tstruct ib_device *device;\n\tunion {\n\t\tstruct ib_cq *cq;\n\t\tstruct ib_qp *qp;\n\t\tstruct ib_srq *srq;\n\t\tstruct ib_wq *wq;\n\t\tu32 port_num;\n\t} element;\n\tenum ib_event_type event;\n};\n\nstruct ib_flow {\n\tstruct ib_qp *qp;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n};\n\nstruct ib_flow_action {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tenum ib_flow_action_type type;\n\tatomic_t usecnt;\n};\n\nstruct ib_flow_eth_filter {\n\tu8 dst_mac[6];\n\tu8 src_mac[6];\n\t__be16 ether_type;\n\t__be16 vlan_tag;\n};\n\nstruct ib_flow_spec_eth {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_eth_filter val;\n\tstruct ib_flow_eth_filter mask;\n};\n\nstruct ib_flow_ib_filter {\n\t__be16 dlid;\n\t__u8 sl;\n};\n\nstruct ib_flow_spec_ib {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ib_filter val;\n\tstruct ib_flow_ib_filter mask;\n};\n\nstruct ib_flow_ipv4_filter {\n\t__be32 src_ip;\n\t__be32 dst_ip;\n\tu8 proto;\n\tu8 tos;\n\tu8 ttl;\n\tu8 flags;\n};\n\nstruct ib_flow_spec_ipv4 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv4_filter val;\n\tstruct ib_flow_ipv4_filter mask;\n};\n\nstruct ib_flow_tcp_udp_filter {\n\t__be16 dst_port;\n\t__be16 src_port;\n};\n\nstruct ib_flow_spec_tcp_udp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tcp_udp_filter val;\n\tstruct ib_flow_tcp_udp_filter mask;\n};\n\nstruct ib_flow_ipv6_filter {\n\tu8 src_ip[16];\n\tu8 dst_ip[16];\n\t__be32 flow_label;\n\tu8 next_hdr;\n\tu8 traffic_class;\n\tu8 hop_limit;\n} __attribute__((packed));\n\nstruct ib_flow_spec_ipv6 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv6_filter val;\n\tstruct ib_flow_ipv6_filter mask;\n};\n\nstruct ib_flow_tunnel_filter {\n\t__be32 tunnel_id;\n};\n\nstruct ib_flow_spec_tunnel {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tunnel_filter val;\n\tstruct ib_flow_tunnel_filter mask;\n};\n\nstruct ib_flow_esp_filter {\n\t__be32 spi;\n\t__be32 seq;\n};\n\nstruct ib_flow_spec_esp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_esp_filter val;\n\tstruct ib_flow_esp_filter mask;\n};\n\nstruct ib_flow_gre_filter {\n\t__be16 c_ks_res0_ver;\n\t__be16 protocol;\n\t__be32 key;\n};\n\nstruct ib_flow_spec_gre {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_gre_filter val;\n\tstruct ib_flow_gre_filter mask;\n};\n\nstruct ib_flow_mpls_filter {\n\t__be32 tag;\n};\n\nstruct ib_flow_spec_mpls {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_mpls_filter val;\n\tstruct ib_flow_mpls_filter mask;\n};\n\nstruct ib_flow_spec_action_tag {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tu32 tag_id;\n};\n\nstruct ib_flow_spec_action_drop {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n};\n\nstruct ib_flow_spec_action_handle {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_flow_action *act;\n};\n\nstruct ib_flow_spec_action_count {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_counters *counters;\n};\n\nunion ib_flow_spec {\n\tstruct {\n\t\tu32 type;\n\t\tu16 size;\n\t};\n\tstruct ib_flow_spec_eth eth;\n\tstruct ib_flow_spec_ib ib;\n\tstruct ib_flow_spec_ipv4 ipv4;\n\tstruct ib_flow_spec_tcp_udp tcp_udp;\n\tstruct ib_flow_spec_ipv6 ipv6;\n\tstruct ib_flow_spec_tunnel tunnel;\n\tstruct ib_flow_spec_esp esp;\n\tstruct ib_flow_spec_gre gre;\n\tstruct ib_flow_spec_mpls mpls;\n\tstruct ib_flow_spec_action_tag flow_tag;\n\tstruct ib_flow_spec_action_drop drop;\n\tstruct ib_flow_spec_action_handle action;\n\tstruct ib_flow_spec_action_count flow_count;\n};\n\nstruct ib_flow_attr {\n\tenum ib_flow_attr_type type;\n\tu16 size;\n\tu16 priority;\n\tu32 flags;\n\tu8 num_of_specs;\n\tu32 port;\n\tunion ib_flow_spec flows[0];\n};\n\nunion ib_gid {\n\tu8 raw[16];\n\tstruct {\n\t\t__be64 subnet_prefix;\n\t\t__be64 interface_id;\n\t} global;\n};\n\nstruct ib_gid_attr {\n\tstruct net_device *ndev;\n\tstruct ib_device *device;\n\tunion ib_gid gid;\n\tenum ib_gid_type gid_type;\n\tu16 index;\n\tu32 port_num;\n};\n\nstruct ib_global_route {\n\tconst struct ib_gid_attr *sgid_attr;\n\tunion ib_gid dgid;\n\tu32 flow_label;\n\tu8 sgid_index;\n\tu8 hop_limit;\n\tu8 traffic_class;\n};\n\nstruct ib_grh {\n\t__be32 version_tclass_flow;\n\t__be16 paylen;\n\tu8 next_hdr;\n\tu8 hop_limit;\n\tunion ib_gid sgid;\n\tunion ib_gid dgid;\n};\n\nstruct ib_sig_attrs;\n\nstruct ib_mr {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tu32 lkey;\n\tu32 rkey;\n\tu64 iova;\n\tu64 length;\n\tunsigned int page_size;\n\tenum ib_mr_type type;\n\tbool need_inval;\n\tunion {\n\t\tstruct ib_uobject *uobject;\n\t\tstruct list_head qp_entry;\n\t};\n\tstruct ib_dm *dm;\n\tstruct ib_sig_attrs *sig_attrs;\n\tstruct ib_dmah *dmah;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_sig_err {\n\tenum ib_sig_err_type err_type;\n\tu32 expected;\n\tu32 actual;\n\tu64 sig_err_offset;\n\tu32 key;\n};\n\nstruct ib_mr_status {\n\tu32 fail_status;\n\tstruct ib_sig_err sig_err;\n};\n\nstruct ib_mw {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tu32 rkey;\n\tenum ib_mw_type type;\n};\n\nstruct ib_pd {\n\tu32 local_dma_lkey;\n\tu32 flags;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 unsafe_global_rkey;\n\tstruct ib_mr *__internal_mr;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_port_attr {\n\tu64 subnet_prefix;\n\tenum ib_port_state state;\n\tenum ib_mtu max_mtu;\n\tenum ib_mtu active_mtu;\n\tu32 phys_mtu;\n\tint gid_tbl_len;\n\tunsigned int ip_gids: 1;\n\tu32 port_cap_flags;\n\tu32 max_msg_sz;\n\tu32 bad_pkey_cntr;\n\tu32 qkey_viol_cntr;\n\tu16 pkey_tbl_len;\n\tu32 sm_lid;\n\tu32 lid;\n\tu8 lmc;\n\tu8 max_vl_num;\n\tu8 sm_sl;\n\tu8 subnet_timeout;\n\tu8 init_type_reply;\n\tu8 active_width;\n\tu16 active_speed;\n\tu8 phys_state;\n\tu16 port_cap_flags2;\n};\n\nstruct ib_pkey_cache;\n\nstruct ib_gid_table;\n\nstruct ib_port_cache {\n\tu64 subnet_prefix;\n\tstruct ib_pkey_cache *pkey;\n\tstruct ib_gid_table *gid;\n\tu8 lmc;\n\tenum ib_port_state port_state;\n\tenum ib_port_state last_port_state;\n};\n\nstruct ib_port_immutable {\n\tint pkey_tbl_len;\n\tint gid_tbl_len;\n\tu32 core_cap_flags;\n\tu32 max_mad_size;\n};\n\nstruct rdma_counter_mode {\n\tenum rdma_nl_counter_mode mode;\n\tenum rdma_nl_counter_mask mask;\n\tstruct auto_mode_param param;\n\tbool bind_opcnt;\n};\n\nstruct rdma_port_counter {\n\tstruct rdma_counter_mode mode;\n\tstruct rdma_hw_stats *hstats;\n\tunsigned int num_counters;\n\tstruct mutex lock;\n};\n\nstruct ib_port;\n\nstruct ib_port_data {\n\tstruct ib_device *ib_dev;\n\tstruct ib_port_immutable immutable;\n\tspinlock_t pkey_list_lock;\n\tspinlock_t netdev_lock;\n\tstruct list_head pkey_list;\n\tstruct ib_port_cache cache;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\tstruct hlist_node ndev_hash_link;\n\tstruct rdma_port_counter port_counter;\n\tstruct ib_port *sysfs;\n};\n\nstruct ib_port_modify {\n\tu32 set_port_cap_mask;\n\tu32 clr_port_cap_mask;\n\tu8 init_type;\n};\n\nstruct ib_qp_security;\n\nstruct ib_port_pkey {\n\tenum port_pkey_state state;\n\tu16 pkey_index;\n\tu32 port_num;\n\tstruct list_head qp_list;\n\tstruct list_head to_error_list;\n\tstruct ib_qp_security *sec;\n};\n\nstruct ib_ports_pkeys {\n\tstruct ib_port_pkey main;\n\tstruct ib_port_pkey alt;\n};\n\nstruct ib_uqp_object;\n\nstruct ib_qp {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tspinlock_t mr_lock;\n\tint mrs_used;\n\tstruct list_head rdma_mrs;\n\tstruct list_head sig_mrs;\n\tstruct ib_srq *srq;\n\tstruct completion srq_completion;\n\tstruct ib_xrcd *xrcd;\n\tstruct list_head xrcd_list;\n\tatomic_t usecnt;\n\tstruct list_head open_list;\n\tstruct ib_qp *real_qp;\n\tstruct ib_uqp_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid (*registered_event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tconst struct ib_gid_attr *av_sgid_attr;\n\tconst struct ib_gid_attr *alt_path_sgid_attr;\n\tu32 qp_num;\n\tu32 max_write_sge;\n\tu32 max_read_sge;\n\tenum ib_qp_type qp_type;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tstruct ib_qp_security *qp_sec;\n\tu32 port;\n\tbool integrity_en;\n\tstruct rdma_restrack_entry res;\n\tstruct rdma_counter *counter;\n};\n\nstruct ib_qp_cap {\n\tu32 max_send_wr;\n\tu32 max_recv_wr;\n\tu32 max_send_sge;\n\tu32 max_recv_sge;\n\tu32 max_inline_data;\n\tu32 max_rdma_ctxs;\n};\n\nstruct roce_ah_attr {\n\tu8 dmac[6];\n};\n\nstruct opa_ah_attr {\n\tu32 dlid;\n\tu8 src_path_bits;\n\tbool make_grd;\n};\n\nstruct rdma_ah_attr {\n\tstruct ib_global_route grh;\n\tu8 sl;\n\tu8 static_rate;\n\tu32 port_num;\n\tu8 ah_flags;\n\tenum rdma_ah_attr_type type;\n\tunion {\n\t\tstruct ib_ah_attr ib;\n\t\tstruct roce_ah_attr roce;\n\t\tstruct opa_ah_attr opa;\n\t};\n};\n\nstruct ib_qp_attr {\n\tenum ib_qp_state qp_state;\n\tenum ib_qp_state cur_qp_state;\n\tenum ib_mtu path_mtu;\n\tenum ib_mig_state path_mig_state;\n\tu32 qkey;\n\tu32 rq_psn;\n\tu32 sq_psn;\n\tu32 dest_qp_num;\n\tint qp_access_flags;\n\tstruct ib_qp_cap cap;\n\tstruct rdma_ah_attr ah_attr;\n\tstruct rdma_ah_attr alt_ah_attr;\n\tu16 pkey_index;\n\tu16 alt_pkey_index;\n\tu8 en_sqd_async_notify;\n\tu8 sq_draining;\n\tu8 max_rd_atomic;\n\tu8 max_dest_rd_atomic;\n\tu8 min_rnr_timer;\n\tu32 port_num;\n\tu8 timeout;\n\tu8 retry_cnt;\n\tu8 rnr_retry;\n\tu32 alt_port_num;\n\tu8 alt_timeout;\n\tu32 rate_limit;\n\tstruct net_device *xmit_slave;\n};\n\nstruct ib_qp_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tstruct ib_srq *srq;\n\tstruct ib_xrcd *xrcd;\n\tstruct ib_qp_cap cap;\n\tenum ib_sig_type sq_sig_type;\n\tenum ib_qp_type qp_type;\n\tu32 create_flags;\n\tu32 port_num;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tu32 source_qpn;\n};\n\nstruct ib_qp_security {\n\tstruct ib_qp *qp;\n\tstruct ib_device *dev;\n\tstruct mutex mutex;\n\tstruct ib_ports_pkeys *ports_pkeys;\n\tstruct list_head shared_qp_list;\n\tvoid *security;\n\tbool destroying;\n\tatomic_t error_list_count;\n\tstruct completion error_complete;\n\tint error_comps_pending;\n};\n\nstruct ib_rdmacg_object {};\n\nstruct ib_recv_wr {\n\tstruct ib_recv_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n};\n\nstruct ib_rwq_ind_table {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 ind_tbl_num;\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_rwq_ind_table_init_attr {\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_send_wr {\n\tstruct ib_send_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n\tenum ib_wr_opcode opcode;\n\tint send_flags;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n};\n\nstruct ib_sge {\n\tu64 addr;\n\tu32 length;\n\tu32 lkey;\n};\n\nstruct ib_t10_dif_domain {\n\tenum ib_t10_dif_bg_type bg_type;\n\tu16 pi_interval;\n\tu16 bg;\n\tu16 app_tag;\n\tu32 ref_tag;\n\tbool ref_remap;\n\tbool app_escape;\n\tbool ref_escape;\n\tu16 apptag_check_mask;\n};\n\nstruct ib_sig_domain {\n\tenum ib_signature_type sig_type;\n\tunion {\n\t\tstruct ib_t10_dif_domain dif;\n\t} sig;\n};\n\nstruct ib_sig_attrs {\n\tu8 check_mask;\n\tstruct ib_sig_domain mem;\n\tstruct ib_sig_domain wire;\n\tint meta_length;\n};\n\nstruct ib_usrq_object;\n\nstruct ib_srq {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_usrq_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tenum ib_srq_type srq_type;\n\tatomic_t usecnt;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t\tu32 srq_num;\n\t\t\t} xrc;\n\t\t};\n\t} ext;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_srq_attr {\n\tu32 max_wr;\n\tu32 max_sge;\n\tu32 srq_limit;\n};\n\nstruct ib_srq_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tstruct ib_srq_attr attr;\n\tenum ib_srq_type srq_type;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t} xrc;\n\t\t\tstruct {\n\t\t\t\tu32 max_num_tags;\n\t\t\t} tag_matching;\n\t\t};\n\t} ext;\n};\n\nstruct ib_ucontext {\n\tstruct ib_device *device;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_rdmacg_object cg_obj;\n\tu64 enabled_caps;\n\tstruct rdma_restrack_entry res;\n\tstruct xarray mmap_xa;\n};\n\nstruct ib_udata {\n\tconst void *inbuf;\n\tvoid *outbuf;\n\tsize_t inlen;\n\tsize_t outlen;\n};\n\nstruct uverbs_api_object;\n\nstruct ib_uobject {\n\tu64 user_handle;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_ucontext *context;\n\tvoid *object;\n\tstruct list_head list;\n\tstruct ib_rdmacg_object cg_obj;\n\tint id;\n\tstruct kref ref;\n\tatomic_t usecnt;\n\tstruct callback_head rcu;\n\tconst struct uverbs_api_object *uapi_object;\n};\n\nstruct ib_wc {\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tenum ib_wc_status status;\n\tenum ib_wc_opcode opcode;\n\tu32 vendor_err;\n\tu32 byte_len;\n\tstruct ib_qp *qp;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tu32 src_qp;\n\tu32 slid;\n\tint wc_flags;\n\tu16 pkey_index;\n\tu8 sl;\n\tu8 dlid_path_bits;\n\tu32 port_num;\n\tu8 smac[6];\n\tu16 vlan_id;\n\tu8 network_hdr_type;\n};\n\nstruct ib_uwq_object;\n\nstruct ib_wq {\n\tstruct ib_device *device;\n\tstruct ib_uwq_object *uobject;\n\tvoid *wq_context;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tstruct ib_pd *pd;\n\tstruct ib_cq *cq;\n\tu32 wq_num;\n\tenum ib_wq_state state;\n\tenum ib_wq_type wq_type;\n\tatomic_t usecnt;\n};\n\nstruct ib_wq_attr {\n\tenum ib_wq_state wq_state;\n\tenum ib_wq_state curr_wq_state;\n\tu32 flags;\n\tu32 flags_mask;\n};\n\nstruct ib_wq_init_attr {\n\tvoid *wq_context;\n\tenum ib_wq_type wq_type;\n\tu32 max_wr;\n\tu32 max_sge;\n\tstruct ib_cq *cq;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tu32 create_flags;\n};\n\nstruct ib_xrcd {\n\tstruct ib_device *device;\n\tatomic_t usecnt;\n\tstruct inode *inode;\n\tstruct rw_semaphore tgt_qps_rwsem;\n\tstruct xarray tgt_qps;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct icc_bulk_data {\n\tstruct icc_path *path;\n\tconst char *name;\n\tu32 avg_bw;\n\tu32 peak_bw;\n};\n\nstruct icc_bulk_devres {\n\tstruct icc_bulk_data *paths;\n\tint num_paths;\n};\n\nstruct icc_clk_data {\n\tstruct clk *clk;\n\tconst char *name;\n\tunsigned int master_id;\n\tunsigned int slave_id;\n};\n\nstruct icc_clk_node {\n\tstruct clk *clk;\n\tbool enabled;\n};\n\nstruct icc_node;\n\nstruct icc_node_data;\n\nstruct icc_provider {\n\tstruct list_head provider_list;\n\tstruct list_head nodes;\n\tint (*set)(struct icc_node *, struct icc_node *);\n\tint (*aggregate)(struct icc_node *, u32, u32, u32, u32 *, u32 *);\n\tvoid (*pre_aggregate)(struct icc_node *);\n\tint (*get_bw)(struct icc_node *, u32 *, u32 *);\n\tstruct icc_node * (*xlate)(const struct of_phandle_args *, void *);\n\tstruct icc_node_data * (*xlate_extended)(const struct of_phandle_args *, void *);\n\tstruct device *dev;\n\tint users;\n\tbool inter_set;\n\tvoid *data;\n};\n\nstruct icc_clk_provider {\n\tstruct icc_provider provider;\n\tint num_clocks;\n\tstruct icc_clk_node clocks[0];\n};\n\nstruct icc_node {\n\tint id;\n\tconst char *name;\n\tstruct icc_node **links;\n\tsize_t num_links;\n\tstruct icc_provider *provider;\n\tstruct list_head node_list;\n\tstruct list_head search_list;\n\tstruct icc_node *reverse;\n\tu8 is_traversed: 1;\n\tstruct hlist_head req_list;\n\tu32 avg_bw;\n\tu32 peak_bw;\n\tu32 init_avg;\n\tu32 init_peak;\n\tvoid *data;\n};\n\nstruct icc_node_data {\n\tstruct icc_node *node;\n\tu32 tag;\n};\n\nstruct icc_onecell_data {\n\tunsigned int num_nodes;\n\tstruct icc_node *nodes[0];\n};\n\nstruct icc_req {\n\tstruct hlist_node req_node;\n\tstruct icc_node *node;\n\tstruct device *dev;\n\tbool enabled;\n\tu32 tag;\n\tu32 avg_bw;\n\tu32 peak_bw;\n};\n\nstruct icc_path {\n\tconst char *name;\n\tsize_t num_nodes;\n\tstruct icc_req reqs[0];\n};\n\nstruct icc_rpm_smd_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct ich8_pr {\n\tu32 base: 13;\n\tu32 reserved1: 2;\n\tu32 rpe: 1;\n\tu32 limit: 13;\n\tu32 reserved2: 2;\n\tu32 wpe: 1;\n};\n\nunion ich8_flash_protected_range {\n\tstruct ich8_pr range;\n\tu32 regval;\n};\n\nstruct ich8_hsflctl {\n\tu16 flcgo: 1;\n\tu16 flcycle: 2;\n\tu16 reserved: 5;\n\tu16 fldbcount: 2;\n\tu16 flockdn: 6;\n};\n\nstruct ich8_hsfsts {\n\tu16 flcdone: 1;\n\tu16 flcerr: 1;\n\tu16 dael: 1;\n\tu16 berasesz: 2;\n\tu16 flcinprog: 1;\n\tu16 reserved1: 2;\n\tu16 reserved2: 6;\n\tu16 fldesvalid: 1;\n\tu16 flockdn: 1;\n};\n\nunion ich8_hws_flash_ctrl {\n\tstruct ich8_hsflctl hsf_ctrl;\n\tu16 regval;\n};\n\nunion ich8_hws_flash_status {\n\tstruct ich8_hsfsts hsf_status;\n\tu16 regval;\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 reserved1: 4;\n\t__u8 version: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[7];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct id_to_type {\n\tu32 id;\n\tint type;\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[16];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n};\n\nstruct idmac_desc {\n\t__le32 des0;\n\t__le32 des1;\n\t__le32 des2;\n\t__le32 des3;\n};\n\nstruct idmac_desc_64addr {\n\tu32 des0;\n\tu32 des1;\n\tu32 des2;\n\tu32 des3;\n\tu32 des4;\n\tu32 des5;\n\tu32 des6;\n\tu32 des7;\n};\n\nstruct idmap_legacy_upcalldata;\n\nstruct idmap {\n\tstruct rpc_pipe_dir_object idmap_pdo;\n\tstruct rpc_pipe *idmap_pipe;\n\tstruct idmap_legacy_upcalldata *idmap_upcall_data;\n\tstruct mutex idmap_mutex;\n\tstruct user_namespace *user_ns;\n};\n\nstruct idmap_key {\n\tbool map_up;\n\tu32 id;\n\tu32 count;\n};\n\nstruct idmap_msg {\n\t__u8 im_type;\n\t__u8 im_conv;\n\tchar im_name[128];\n\t__u32 im_id;\n\t__u8 im_status;\n};\n\nstruct idmap_legacy_upcalldata {\n\tstruct rpc_pipe_msg pipe_msg;\n\tstruct idmap_msg idmap_msg;\n\tstruct key *authkey;\n\tstruct idmap *idmap;\n};\n\nstruct ieee_ets {\n\t__u8 willing;\n\t__u8 ets_cap;\n\t__u8 cbs;\n\t__u8 tc_tx_bw[8];\n\t__u8 tc_rx_bw[8];\n\t__u8 tc_tsa[8];\n\t__u8 prio_tc[8];\n\t__u8 tc_reco_bw[8];\n\t__u8 tc_reco_tsa[8];\n\t__u8 reco_prio_tc[8];\n};\n\nstruct ieee_pfc {\n\t__u8 pfc_cap;\n\t__u8 pfc_en;\n\t__u8 mbc;\n\t__u16 delay;\n\t__u64 requests[8];\n\t__u64 indications[8];\n};\n\nstruct if_dqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n};\n\nstruct if_dqinfo {\n\t__u64 dqi_bgrace;\n\t__u64 dqi_igrace;\n\t__u32 dqi_flags;\n\t__u32 dqi_valid;\n};\n\nstruct if_nextdqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n\t__u32 dqb_id;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct inet6_dev;\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct igb_tx_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 restart_queue;\n\tu64 restart_queue2;\n};\n\nstruct igb_rx_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 drops;\n\tu64 csum_err;\n\tu64 alloc_failed;\n};\n\nstruct igb_q_vector;\n\nstruct igb_tx_buffer;\n\nstruct igb_rx_buffer;\n\nstruct igb_ring {\n\tstruct igb_q_vector *q_vector;\n\tstruct net_device *netdev;\n\tstruct bpf_prog *xdp_prog;\n\tstruct device *dev;\n\tunion {\n\t\tstruct igb_tx_buffer *tx_buffer_info;\n\t\tstruct igb_rx_buffer *rx_buffer_info;\n\t\tstruct xdp_buff **rx_buffer_info_zc;\n\t};\n\tvoid *desc;\n\tlong unsigned int flags;\n\tvoid *tail;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tu16 count;\n\tu8 queue_index;\n\tu8 reg_idx;\n\tbool launchtime_enable;\n\tbool cbs_enable;\n\ts32 idleslope;\n\ts32 sendslope;\n\ts32 hicredit;\n\ts32 locredit;\n\tu16 next_to_clean;\n\tu16 next_to_use;\n\tu16 next_to_alloc;\n\tunion {\n\t\tstruct {\n\t\t\tstruct igb_tx_queue_stats tx_stats;\n\t\t\tstruct u64_stats_sync tx_syncp;\n\t\t\tstruct u64_stats_sync tx_syncp2;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *skb;\n\t\t\tstruct igb_rx_queue_stats rx_stats;\n\t\t\tstruct u64_stats_sync rx_syncp;\n\t\t};\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct vf_mac_filter {\n\tstruct list_head l;\n\tint vf;\n\tbool free;\n\tu8 vf_mac[6];\n};\n\nstruct vf_data_storage;\n\nstruct igb_mac_addr;\n\nstruct igb_adapter {\n\tlong unsigned int active_vlans[64];\n\tstruct net_device *netdev;\n\tstruct bpf_prog *xdp_prog;\n\tlong unsigned int state;\n\tunsigned int flags;\n\tunsigned int num_q_vectors;\n\tstruct msix_entry msix_entries[10];\n\tu32 rx_itr_setting;\n\tu32 tx_itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tu16 tx_work_limit;\n\tu32 tx_timeout_count;\n\tint num_tx_queues;\n\tstruct igb_ring *tx_ring[16];\n\tint num_rx_queues;\n\tstruct igb_ring *rx_ring[16];\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tu16 mng_vlan_id;\n\tu32 bd_number;\n\tu32 wol;\n\tu32 en_mng_pt;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu8 *io_addr;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tbool fc_autoneg;\n\tu8 tx_timeout_factor;\n\tstruct timer_list blink_timer;\n\tlong unsigned int led_status;\n\tstruct pci_dev *pdev;\n\tspinlock_t stats64_lock;\n\tstruct rtnl_link_stats64 stats64;\n\tstruct e1000_hw___3 hw;\n\tstruct e1000_hw_stats___3 stats;\n\tstruct e1000_phy_info___3 phy_info;\n\tu32 test_icr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct igb_ring test_tx_ring;\n\tstruct igb_ring test_rx_ring;\n\tint msg_enable;\n\tstruct igb_q_vector *q_vector[8];\n\tu32 eims_enable_mask;\n\tu32 eims_other;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tunsigned int vfs_allocated_count;\n\tstruct vf_data_storage *vf_data;\n\tint vf_rate_link_speed;\n\tu32 rss_queues;\n\tu32 wvbr;\n\tu32 *shadow_vfta;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_caps;\n\tstruct delayed_work ptp_overflow_work;\n\tstruct work_struct ptp_tx_work;\n\tstruct sk_buff *ptp_tx_skb;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tlong unsigned int ptp_tx_start;\n\tlong unsigned int last_rx_ptp_check;\n\tlong unsigned int last_rx_timestamp;\n\tunsigned int ptp_flags;\n\tspinlock_t tmreg_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tu32 rx_hwtstamp_cleared;\n\tbool pps_sys_wrap_on;\n\tstruct ptp_pin_desc sdp_config[4];\n\tstruct {\n\t\tstruct timespec64 start;\n\t\tstruct timespec64 period;\n\t} perout[2];\n\tchar fw_version[48];\n\tstruct hwmon_buff *igb_hwmon_buff;\n\tbool ets;\n\tstruct i2c_algo_bit_data i2c_algo;\n\tstruct i2c_adapter i2c_adap;\n\tstruct i2c_client *i2c_client;\n\tu32 rss_indir_tbl_init;\n\tu8 rss_indir_tbl[128];\n\tlong unsigned int link_check_timeout;\n\tint copper_tries;\n\tstruct e1000_info___2 ei;\n\tu16 eee_advert;\n\tstruct hlist_head nfc_filter_list;\n\tstruct hlist_head cls_flower_list;\n\tunsigned int nfc_filter_count;\n\tspinlock_t nfc_lock;\n\tbool etype_bitmap[3];\n\tstruct igb_mac_addr *mac_table;\n\tstruct vf_mac_filter vf_macs;\n\tstruct vf_mac_filter *vf_mac_list;\n\tspinlock_t vfs_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct igb_mac_addr {\n\tu8 addr[6];\n\tu8 queue;\n\tu8 state;\n};\n\nstruct igb_nfc_input {\n\tu8 match_flags;\n\t__be16 etype;\n\t__be16 vlan_tci;\n\tu8 src_addr[6];\n\tu8 dst_addr[6];\n};\n\nstruct igb_nfc_filter {\n\tstruct hlist_node nfc_node;\n\tstruct igb_nfc_input filter;\n\tlong unsigned int cookie;\n\tu16 etype_reg_index;\n\tu16 sw_idx;\n\tu16 action;\n};\n\nstruct igb_ring_container {\n\tstruct igb_ring *ring;\n\tunsigned int total_bytes;\n\tunsigned int total_packets;\n\tu16 work_limit;\n\tu8 count;\n\tu8 itr;\n};\n\nstruct igb_q_vector {\n\tstruct igb_adapter *adapter;\n\tint cpu;\n\tu32 eims_value;\n\tu16 itr_val;\n\tu8 set_itr;\n\tvoid *itr_register;\n\tstruct igb_ring_container rx;\n\tstruct igb_ring_container tx;\n\tstruct napi_struct napi;\n\tstruct callback_head rcu;\n\tchar name[25];\n\tlong: 64;\n\tlong: 64;\n\tstruct igb_ring ring[0];\n};\n\nstruct igb_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nstruct igb_reg_test {\n\tu16 reg;\n\tu16 reg_offset;\n\tu16 array_len;\n\tu16 test_type;\n\tu32 mask;\n\tu32 write;\n};\n\nstruct igb_rx_buffer {\n\tdma_addr_t dma;\n\tstruct page *page;\n\t__u32 page_offset;\n\t__u16 pagecnt_bias;\n};\n\nstruct igb_stats {\n\tchar stat_string[32];\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct igb_tx_buffer {\n\tunion e1000_adv_tx_desc *next_to_watch;\n\tlong unsigned int time_stamp;\n\tenum igb_tx_buf_type type;\n\tunion {\n\t\tstruct sk_buff *skb;\n\t\tstruct xdp_frame *xdpf;\n\t};\n\tunsigned int bytecount;\n\tu16 gso_segs;\n\t__be16 protocol;\n\tdma_addr_t dma;\n\t__u32 len;\n\tu32 tx_flags;\n};\n\nstruct igbvf_info;\n\nstruct igbvf_ring;\n\nstruct igbvf_adapter {\n\tstruct timer_list watchdog_timer;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tconst struct igbvf_info *ei;\n\tlong unsigned int active_vlans[64];\n\tu32 rx_buffer_len;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tlong unsigned int state;\n\tu32 requested_itr;\n\tu32 current_itr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct igbvf_ring *tx_ring;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu32 tx_timeout_count;\n\tstruct igbvf_ring *rx_ring;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu64 rx_hdr_split;\n\tu32 alloc_rx_buff_failed;\n\tunsigned int rx_ps_hdr_size;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw___4 hw;\n\tstruct e1000_vf_stats stats;\n\tu64 zero_base;\n\tu32 msg_enable;\n\tstruct msix_entry *msix_entries;\n\tu32 eims_enable_mask;\n\tu32 eims_other;\n\tu32 wol;\n\tu32 pba;\n\tunsigned int flags;\n\tlong unsigned int last_reset;\n};\n\nstruct igbvf_buffer {\n\tdma_addr_t dma;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int time_stamp;\n\t\t\tunion e1000_adv_tx_desc *next_to_watch;\n\t\t\tu16 length;\n\t\t\tu16 mapped_as_page;\n\t\t};\n\t\tstruct {\n\t\t\tstruct page *page;\n\t\t\tu64 page_dma;\n\t\t\tunsigned int page_offset;\n\t\t};\n\t};\n};\n\nunion igbvf_desc {\n\tunion e1000_adv_rx_desc___2 rx_desc;\n\tunion e1000_adv_tx_desc tx_desc;\n\tstruct e1000_adv_tx_context_desc tx_context_desc;\n};\n\nstruct igbvf_info {\n\tenum e1000_mac_type mac;\n\tunsigned int flags;\n\tu32 pba;\n\tvoid (*init_ops)(struct e1000_hw___4 *);\n\ts32 (*get_variants)(struct igbvf_adapter *);\n};\n\nstruct igbvf_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n};\n\nstruct igbvf_ring {\n\tstruct igbvf_adapter *adapter;\n\tunion igbvf_desc *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\tu16 head;\n\tu16 tail;\n\tstruct igbvf_buffer *buffer_info;\n\tstruct napi_struct napi;\n\tchar name[21];\n\tu32 eims_value;\n\tu32 itr_val;\n\tenum latency_range itr_range;\n\tu16 itr_register;\n\tint set_itr;\n\tstruct sk_buff *rx_skb_top;\n\tstruct igbvf_queue_stats stats;\n};\n\nstruct igbvf_stats {\n\tchar stat_string[32];\n\tint sizeof_stat;\n\tint stat_offset;\n\tint base_stat_offset;\n};\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 qrv: 3;\n\t__u8 suppress: 1;\n\t__u8 resv: 4;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct ignore_entry {\n\tu16 vid;\n\tu16 pid;\n\tu16 bcdmin;\n\tu16 bcdmax;\n};\n\nstruct ignore_section {\n\tguid_t guid;\n\tconst char *name;\n};\n\nstruct iio_buffer_access_funcs;\n\nstruct iio_dev_attr;\n\nstruct iio_buffer {\n\tunsigned int length;\n\tlong unsigned int flags;\n\tsize_t bytes_per_datum;\n\tenum iio_buffer_direction direction;\n\tconst struct iio_buffer_access_funcs *access;\n\tlong int *scan_mask;\n\tstruct list_head demux_list;\n\twait_queue_head_t pollq;\n\tunsigned int watermark;\n\tbool scan_timestamp;\n\tstruct list_head buffer_attr_list;\n\tstruct attribute_group buffer_group;\n\tconst struct iio_dev_attr **attrs;\n\tvoid *demux_bounce;\n\tstruct list_head attached_entry;\n\tstruct list_head buffer_list;\n\tstruct kref ref;\n\tstruct list_head dmabufs;\n\tstruct mutex dmabufs_mutex;\n};\n\nstruct iio_dma_buffer_block;\n\nstruct iio_buffer_access_funcs {\n\tint (*store_to)(struct iio_buffer *, const void *);\n\tint (*read)(struct iio_buffer *, size_t, char *);\n\tsize_t (*data_available)(struct iio_buffer *);\n\tint (*remove_from)(struct iio_buffer *, void *);\n\tint (*write)(struct iio_buffer *, size_t, const char *);\n\tsize_t (*space_available)(struct iio_buffer *);\n\tint (*request_update)(struct iio_buffer *);\n\tint (*set_bytes_per_datum)(struct iio_buffer *, size_t);\n\tint (*set_length)(struct iio_buffer *, unsigned int);\n\tint (*enable)(struct iio_buffer *, struct iio_dev *);\n\tint (*disable)(struct iio_buffer *, struct iio_dev *);\n\tvoid (*release)(struct iio_buffer *);\n\tstruct iio_dma_buffer_block * (*attach_dmabuf)(struct iio_buffer *, struct dma_buf_attachment *);\n\tvoid (*detach_dmabuf)(struct iio_buffer *, struct iio_dma_buffer_block *);\n\tint (*enqueue_dmabuf)(struct iio_buffer *, struct iio_dma_buffer_block *, struct dma_fence *, struct sg_table *, size_t, bool);\n\tstruct device * (*get_dma_dev)(struct iio_buffer *);\n\tvoid (*lock_queue)(struct iio_buffer *);\n\tvoid (*unlock_queue)(struct iio_buffer *);\n\tunsigned int modes;\n\tunsigned int flags;\n};\n\nstruct iio_buffer_setup_ops {\n\tint (*preenable)(struct iio_dev *);\n\tint (*postenable)(struct iio_dev *);\n\tint (*predisable)(struct iio_dev *);\n\tint (*postdisable)(struct iio_dev *);\n\tbool (*validate_scan_mask)(struct iio_dev *, const long unsigned int *);\n};\n\nstruct iio_scan_type {\n\tchar sign;\n\tu8 realbits;\n\tu8 storagebits;\n\tu8 shift;\n\tu8 repeat;\n\tenum iio_endian endianness;\n};\n\nstruct iio_event_spec;\n\nstruct iio_chan_spec_ext_info;\n\nstruct iio_chan_spec {\n\tenum iio_chan_type type;\n\tint channel;\n\tint channel2;\n\tlong unsigned int address;\n\tint scan_index;\n\tunion {\n\t\tstruct iio_scan_type scan_type;\n\t\tstruct {\n\t\t\tconst struct iio_scan_type *ext_scan_type;\n\t\t\tunsigned int num_ext_scan_type;\n\t\t};\n\t};\n\tlong unsigned int info_mask_separate;\n\tlong unsigned int info_mask_separate_available;\n\tlong unsigned int info_mask_shared_by_type;\n\tlong unsigned int info_mask_shared_by_type_available;\n\tlong unsigned int info_mask_shared_by_dir;\n\tlong unsigned int info_mask_shared_by_dir_available;\n\tlong unsigned int info_mask_shared_by_all;\n\tlong unsigned int info_mask_shared_by_all_available;\n\tconst struct iio_event_spec *event_spec;\n\tunsigned int num_event_specs;\n\tconst struct iio_chan_spec_ext_info *ext_info;\n\tconst char *extend_name;\n\tconst char *datasheet_name;\n\tunsigned int modified: 1;\n\tunsigned int indexed: 1;\n\tunsigned int output: 1;\n\tunsigned int differential: 1;\n\tunsigned int has_ext_scan_type: 1;\n};\n\nstruct iio_chan_spec_ext_info {\n\tconst char *name;\n\tenum iio_shared_by shared;\n\tssize_t (*read)(struct iio_dev *, uintptr_t, const struct iio_chan_spec *, char *);\n\tssize_t (*write)(struct iio_dev *, uintptr_t, const struct iio_chan_spec *, const char *, size_t);\n\tuintptr_t private;\n};\n\nstruct iio_channel {\n\tstruct iio_dev *indio_dev;\n\tconst struct iio_chan_spec *channel;\n\tvoid *data;\n};\n\nstruct iio_const_attr {\n\tconst char *string;\n\tstruct device_attribute dev_attr;\n};\n\nstruct iio_demux_table {\n\tunsigned int from;\n\tunsigned int to;\n\tunsigned int length;\n\tstruct list_head l;\n};\n\nstruct iio_trigger;\n\nstruct iio_poll_func;\n\nstruct iio_info;\n\nstruct iio_dev {\n\tint modes;\n\tstruct device dev;\n\tstruct iio_buffer *buffer;\n\tint scan_bytes;\n\tconst long unsigned int *available_scan_masks;\n\tunsigned int masklength;\n\tconst long unsigned int *active_scan_mask;\n\tbool scan_timestamp;\n\tstruct iio_trigger *trig;\n\tstruct iio_poll_func *pollfunc;\n\tstruct iio_poll_func *pollfunc_event;\n\tconst struct iio_chan_spec *channels;\n\tint num_channels;\n\tconst char *name;\n\tconst char *label;\n\tconst struct iio_info *info;\n\tconst struct iio_buffer_setup_ops *setup_ops;\n\tvoid *priv;\n};\n\nstruct iio_dev_attr {\n\tstruct device_attribute dev_attr;\n\tu64 address;\n\tstruct list_head l;\n\tconst struct iio_chan_spec *c;\n\tstruct iio_buffer *buffer;\n};\n\nstruct iio_dev_buffer_pair {\n\tstruct iio_dev *indio_dev;\n\tstruct iio_buffer *buffer;\n};\n\nstruct iio_event_interface;\n\nstruct iio_ioctl_handler;\n\nstruct iio_dev_opaque {\n\tstruct iio_dev indio_dev;\n\tint currentmode;\n\tint id;\n\tstruct module *driver_module;\n\tstruct mutex mlock;\n\tstruct lock_class_key mlock_key;\n\tstruct mutex info_exist_lock;\n\tstruct lock_class_key info_exist_key;\n\tbool trig_readonly;\n\tstruct iio_event_interface *event_interface;\n\tstruct iio_buffer **attached_buffers;\n\tunsigned int attached_buffers_cnt;\n\tstruct iio_ioctl_handler *buffer_ioctl_handler;\n\tstruct list_head buffer_list;\n\tstruct list_head channel_attr_list;\n\tstruct attribute_group chan_attr_group;\n\tstruct list_head ioctl_handlers;\n\tconst struct attribute_group **groups;\n\tint groupcounter;\n\tstruct attribute_group legacy_scan_el_group;\n\tstruct attribute_group legacy_buffer_group;\n\tvoid *bounce_buffer;\n\tsize_t bounce_buffer_size;\n\tunsigned int scan_index_timestamp;\n\tclockid_t clock_id;\n\tstruct cdev chrdev;\n\tlong unsigned int flags;\n\tstruct dentry *debugfs_dentry;\n\tunsigned int cached_reg_addr;\n\tchar read_buf[20];\n\tunsigned int read_buf_len;\n};\n\nstruct iio_device_config {\n\tunsigned int mode;\n\tunsigned int watermark;\n\tconst long unsigned int *scan_mask;\n\tunsigned int scan_bytes;\n\tbool scan_timestamp;\n};\n\nstruct iio_dmabuf_priv;\n\nstruct iio_dma_fence {\n\tstruct dma_fence base;\n\tstruct iio_dmabuf_priv *priv;\n\tstruct work_struct work;\n};\n\nstruct iio_dmabuf {\n\t__u32 fd;\n\t__u32 flags;\n\t__u64 bytes_used;\n};\n\nstruct iio_dmabuf_priv {\n\tstruct list_head entry;\n\tstruct kref ref;\n\tstruct iio_buffer *buffer;\n\tstruct iio_dma_buffer_block *block;\n\tu64 context;\n\tspinlock_t lock;\n\tstruct dma_buf_attachment *attach;\n\tstruct sg_table *sgt;\n\tenum dma_data_direction dir;\n\tatomic_t seqno;\n};\n\nstruct iio_enum {\n\tconst char * const *items;\n\tunsigned int num_items;\n\tint (*set)(struct iio_dev *, const struct iio_chan_spec *, unsigned int);\n\tint (*get)(struct iio_dev *, const struct iio_chan_spec *);\n};\n\nstruct iio_event_data {\n\t__u64 id;\n\t__s64 timestamp;\n};\n\nstruct iio_ioctl_handler {\n\tstruct list_head entry;\n\tlong int (*ioctl)(struct iio_dev *, struct file *, unsigned int, long unsigned int);\n};\n\nstruct iio_event_interface {\n\twait_queue_head_t wait;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct iio_event_data *type;\n\t\t\tconst struct iio_event_data *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct iio_event_data *ptr;\n\t\t\tconst struct iio_event_data *ptr_const;\n\t\t};\n\t\tstruct iio_event_data buf[16];\n\t} det_events;\n\tstruct list_head dev_attr_list;\n\tlong unsigned int flags;\n\tstruct attribute_group group;\n\tstruct mutex read_lock;\n\tstruct iio_ioctl_handler ioctl_handler;\n};\n\nstruct iio_event_spec {\n\tenum iio_event_type type;\n\tenum iio_event_direction dir;\n\tlong unsigned int mask_separate;\n\tlong unsigned int mask_shared_by_type;\n\tlong unsigned int mask_shared_by_dir;\n\tlong unsigned int mask_shared_by_all;\n};\n\nstruct iio_info {\n\tconst struct attribute_group *event_attrs;\n\tconst struct attribute_group *attrs;\n\tint (*read_raw)(struct iio_dev *, const struct iio_chan_spec *, int *, int *, long int);\n\tint (*read_raw_multi)(struct iio_dev *, const struct iio_chan_spec *, int, int *, int *, long int);\n\tint (*read_avail)(struct iio_dev *, const struct iio_chan_spec *, const int **, int *, int *, long int);\n\tint (*write_raw)(struct iio_dev *, const struct iio_chan_spec *, int, int, long int);\n\tint (*read_label)(struct iio_dev *, const struct iio_chan_spec *, char *);\n\tint (*write_raw_get_fmt)(struct iio_dev *, const struct iio_chan_spec *, long int);\n\tint (*read_event_config)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction);\n\tint (*write_event_config)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, bool);\n\tint (*read_event_value)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, enum iio_event_info, int *, int *);\n\tint (*write_event_value)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, enum iio_event_info, int, int);\n\tint (*read_event_label)(struct iio_dev *, const struct iio_chan_spec *, enum iio_event_type, enum iio_event_direction, char *);\n\tint (*validate_trigger)(struct iio_dev *, struct iio_trigger *);\n\tint (*get_current_scan_type)(const struct iio_dev *, const struct iio_chan_spec *);\n\tint (*update_scan_mode)(struct iio_dev *, const long unsigned int *);\n\tint (*debugfs_reg_access)(struct iio_dev *, unsigned int, unsigned int, unsigned int *);\n\tint (*fwnode_xlate)(struct iio_dev *, const struct fwnode_reference_args *);\n\tint (*hwfifo_set_watermark)(struct iio_dev *, unsigned int);\n\tint (*hwfifo_flush_to_buffer)(struct iio_dev *, unsigned int);\n};\n\nstruct iio_map {\n\tconst char *adc_channel_label;\n\tconst char *consumer_dev_name;\n\tconst char *consumer_channel;\n\tvoid *consumer_data;\n};\n\nstruct iio_map_internal {\n\tstruct iio_dev *indio_dev;\n\tconst struct iio_map *map;\n\tstruct list_head l;\n};\n\nstruct iio_mount_matrix {\n\tconst char *rotation[9];\n};\n\nstruct iio_poll_func {\n\tstruct iio_dev *indio_dev;\n\tirqreturn_t (*h)(int, void *);\n\tirqreturn_t (*thread)(int, void *);\n\tint type;\n\tchar *name;\n\tint irq;\n\ts64 timestamp;\n};\n\nstruct iio_subirq {\n\tbool enabled;\n};\n\nstruct iio_trigger_ops;\n\nstruct iio_trigger {\n\tconst struct iio_trigger_ops *ops;\n\tstruct module *owner;\n\tint id;\n\tconst char *name;\n\tstruct device dev;\n\tstruct list_head list;\n\tstruct list_head alloc_list;\n\tatomic_t use_count;\n\tstruct irq_chip subirq_chip;\n\tint subirq_base;\n\tstruct iio_subirq subirqs[2];\n\tlong unsigned int pool[1];\n\tstruct mutex pool_lock;\n\tbool attached_own_device;\n\tstruct work_struct reenable_work;\n};\n\nstruct iio_trigger_ops {\n\tint (*set_trigger_state)(struct iio_trigger *, bool);\n\tvoid (*reenable)(struct iio_trigger *);\n\tint (*validate_device)(struct iio_trigger *, struct iio_dev *);\n};\n\nstruct imx2_wdt_data {\n\tbool wdw_supported;\n};\n\nstruct imx2_wdt_device {\n\tstruct clk *clk;\n\tstruct regmap *regmap;\n\tstruct watchdog_device wdog;\n\tconst struct imx2_wdt_data *data;\n\tbool ext_reset;\n\tbool clk_is_on;\n\tbool no_ping;\n\tbool sleep_wait;\n};\n\nstruct imx7_src_signal;\n\nstruct imx7_src {\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *regmap;\n\tconst struct imx7_src_signal *signals;\n};\n\nstruct imx7_src_signal {\n\tunsigned int offset;\n\tunsigned int bit;\n};\n\nstruct reset_control_ops {\n\tint (*reset)(struct reset_controller_dev *, long unsigned int);\n\tint (*assert)(struct reset_controller_dev *, long unsigned int);\n\tint (*deassert)(struct reset_controller_dev *, long unsigned int);\n\tint (*status)(struct reset_controller_dev *, long unsigned int);\n};\n\nstruct imx7_src_variant {\n\tconst struct imx7_src_signal *signals;\n\tunsigned int signals_num;\n\tstruct reset_control_ops ops;\n};\n\nstruct imx8_acm_soc_data;\n\nstruct imx8_acm_priv {\n\tstruct clk_imx_acm_pm_domains dev_pm;\n\tconst struct imx8_acm_soc_data *soc_data;\n\tvoid *reg;\n\tu32 regs[25];\n};\n\nstruct imx8_acm_soc_data {\n\tstruct clk_imx8_acm_sel *sels;\n\tunsigned int num_sels;\n\tstruct clk_parent_data *mclk_sels;\n};\n\nstruct imx8_pcie_phy_drvdata;\n\nstruct imx8_pcie_phy {\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct phy *phy;\n\tstruct regmap *iomuxc_gpr;\n\tstruct reset_control *perst;\n\tstruct reset_control *reset;\n\tu32 refclk_pad_mode;\n\tu32 tx_deemph_gen1;\n\tu32 tx_deemph_gen2;\n\tbool clkreq_unused;\n\tconst struct imx8_pcie_phy_drvdata *drvdata;\n};\n\nstruct imx8_pcie_phy_drvdata {\n\tconst char *gpr;\n\tenum imx8_pcie_phy_type variant;\n};\n\nstruct imx8_soc_data {\n\tchar *name;\n\tconst char *ocotp_compatible;\n\tint (*soc_revision)(struct platform_device *, u32 *);\n\tint (*soc_uid)(struct platform_device *, u64 *);\n};\n\nstruct imx8_soc_drvdata {\n\tvoid *ocotp_base;\n\tstruct clk *clk;\n};\n\nstruct imx8m_blk_ctrl_domain;\n\nstruct imx8m_blk_ctrl {\n\tstruct device *dev;\n\tstruct notifier_block power_nb;\n\tstruct device *bus_power_dev;\n\tstruct regmap *regmap;\n\tstruct imx8m_blk_ctrl_domain *domains;\n\tstruct genpd_onecell_data onecell_data;\n};\n\nstruct imx8m_blk_ctrl_domain_data;\n\nstruct imx8m_blk_ctrl_data {\n\tint max_reg;\n\tnotifier_fn_t power_notifier_fn;\n\tconst struct imx8m_blk_ctrl_domain_data *domains;\n\tint num_domains;\n};\n\nstruct imx8m_blk_ctrl_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct imx8m_blk_ctrl_domain_data *data;\n\tstruct clk_bulk_data clks[4];\n\tstruct icc_bulk_data paths[4];\n\tstruct device *power_dev;\n\tstruct imx8m_blk_ctrl *bc;\n\tint num_paths;\n};\n\nstruct imx8m_blk_ctrl_domain_data {\n\tconst char *name;\n\tconst char * const *clk_names;\n\tconst char * const *path_names;\n\tconst char *gpc_name;\n\tint num_clks;\n\tint num_paths;\n\tu32 rst_mask;\n\tu32 clk_mask;\n\tu32 mipi_phy_rst_mask;\n};\n\nstruct imx8mp_reset_map;\n\nstruct imx8mp_audiomix_reset {\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *regmap;\n\tconst struct imx8mp_reset_map *map;\n};\n\nstruct imx8mp_blk_ctrl_domain;\n\nstruct imx8mp_blk_ctrl {\n\tstruct device *dev;\n\tstruct notifier_block power_nb;\n\tstruct device *bus_power_dev;\n\tstruct regmap *regmap;\n\tstruct imx8mp_blk_ctrl_domain *domains;\n\tstruct genpd_onecell_data onecell_data;\n\tvoid (*power_off)(struct imx8mp_blk_ctrl *, struct imx8mp_blk_ctrl_domain *);\n\tvoid (*power_on)(struct imx8mp_blk_ctrl *, struct imx8mp_blk_ctrl_domain *);\n};\n\nstruct imx8mp_blk_ctrl_domain_data;\n\nstruct imx8mp_blk_ctrl_data {\n\tint max_reg;\n\tint (*probe)(struct imx8mp_blk_ctrl *);\n\tnotifier_fn_t power_notifier_fn;\n\tvoid (*power_off)(struct imx8mp_blk_ctrl *, struct imx8mp_blk_ctrl_domain *);\n\tvoid (*power_on)(struct imx8mp_blk_ctrl *, struct imx8mp_blk_ctrl_domain *);\n\tconst struct imx8mp_blk_ctrl_domain_data *domains;\n\tint num_domains;\n};\n\nstruct imx8mp_blk_ctrl_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct imx8mp_blk_ctrl_domain_data *data;\n\tstruct clk_bulk_data clks[3];\n\tstruct icc_bulk_data paths[3];\n\tstruct device *power_dev;\n\tstruct imx8mp_blk_ctrl *bc;\n\tstruct notifier_block power_nb;\n\tint num_paths;\n\tint id;\n};\n\nstruct imx8mp_blk_ctrl_domain_data {\n\tconst char *name;\n\tconst char * const *clk_names;\n\tint num_clks;\n\tconst char * const *path_names;\n\tint num_paths;\n\tconst char *gpc_name;\n\tconst unsigned int flags;\n};\n\nstruct imx8mp_clock_constraints {\n\tunsigned int clkid;\n\tu32 maxrate;\n};\n\nstruct imx8mp_reset_info {\n\tconst struct imx8mp_reset_map *map;\n\tint num_lines;\n};\n\nstruct imx8mp_reset_map {\n\tunsigned int offset;\n\tunsigned int mask;\n\tbool active_low;\n};\n\nstruct imx8qxp_lpcg_data {\n\tint id;\n\tchar *name;\n\tchar *parent;\n\tlong unsigned int flags;\n\tu32 offset;\n\tu8 bit_idx;\n\tbool hw_gate;\n};\n\nstruct imx8qxp_ss_lpcg {\n\tconst struct imx8qxp_lpcg_data *lpcg;\n\tu8 num_lpcg;\n\tu8 num_max;\n};\n\nstruct imx93_blk_ctrl_domain;\n\nstruct imx93_blk_ctrl {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tint num_clks;\n\tstruct clk_bulk_data clks[4];\n\tstruct imx93_blk_ctrl_domain *domains;\n\tstruct genpd_onecell_data onecell_data;\n};\n\nstruct imx93_blk_ctrl_domain_data;\n\nstruct imx93_blk_ctrl_data {\n\tconst struct imx93_blk_ctrl_domain_data *domains;\n\tu32 skip_mask;\n\tint num_domains;\n\tconst char * const *clk_names;\n\tint num_clks;\n\tconst struct regmap_access_table *reg_access_table;\n};\n\nstruct imx93_blk_ctrl_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct imx93_blk_ctrl_domain_data *data;\n\tstruct clk_bulk_data clks[4];\n\tstruct imx93_blk_ctrl *bc;\n};\n\nstruct imx93_blk_ctrl_qos {\n\tu32 reg;\n\tu32 cfg_off;\n\tu32 default_prio;\n\tu32 cfg_prio;\n};\n\nstruct imx93_blk_ctrl_domain_data {\n\tconst char *name;\n\tconst char * const *clk_names;\n\tint num_clks;\n\tu32 rst_mask;\n\tu32 clk_mask;\n\tint num_qos;\n\tstruct imx93_blk_ctrl_qos qos[4];\n};\n\nstruct imx93_clk_ccgr {\n\tu32 clk;\n\tchar *name;\n\tchar *parent_name;\n\tu32 off;\n\tlong unsigned int flags;\n\tu32 *shared_count;\n\tlong unsigned int plat;\n};\n\nstruct imx93_clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu32 bit_idx;\n\tu32 val;\n\tu32 mask;\n\tspinlock_t *lock;\n\tunsigned int *share_count;\n};\n\nstruct imx93_clk_root {\n\tu32 clk;\n\tchar *name;\n\tu32 off;\n\tenum clk_sel sel;\n\tlong unsigned int flags;\n\tlong unsigned int plat;\n};\n\nstruct imx93_power_domain {\n\tstruct generic_pm_domain genpd;\n\tstruct device *dev;\n\tvoid *addr;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct imx95_blk_ctl_dev_data;\n\nstruct imx95_blk_ctl {\n\tstruct device *dev;\n\tspinlock_t lock;\n\tstruct clk *clk_apb;\n\tvoid *base;\n\tu32 clk_reg_restore;\n\tconst struct imx95_blk_ctl_dev_data *pdata;\n};\n\nstruct imx95_blk_ctl_clk_dev_data {\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu32 num_parents;\n\tu32 reg;\n\tu32 bit_idx;\n\tu32 bit_width;\n\tu32 clk_type;\n\tu32 flags;\n\tu32 flags2;\n\tu32 type;\n};\n\nstruct imx95_blk_ctl_dev_data {\n\tconst struct imx95_blk_ctl_clk_dev_data *clk_dev_data;\n\tu32 num_clks;\n\tbool rpm_enabled;\n\tu32 clk_reg_offset;\n};\n\nstruct imx_bus {\n\tstruct devfreq_dev_profile profile;\n\tstruct devfreq *devfreq;\n\tstruct clk *clk;\n\tstruct platform_device *icc_pdev;\n};\n\nstruct imx_clk_gpr {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 mask;\n\tu32 reg;\n\tconst u32 *mux_table;\n};\n\nstruct imx_clk_scu_rsrc_table {\n\tconst u32 *rsrc;\n\tu8 num;\n};\n\nstruct imx_fracn_gppll_clk {\n\tconst struct imx_fracn_gppll_rate_table *rate_table;\n\tint rate_count;\n\tint flags;\n};\n\nstruct imx_fracn_gppll_rate_table {\n\tunsigned int rate;\n\tunsigned int mfi;\n\tunsigned int mfn;\n\tunsigned int mfd;\n\tunsigned int rdiv;\n\tunsigned int odiv;\n};\n\nstruct imx_i2c_clk_pair {\n\tu16 div;\n\tu16 val;\n};\n\nstruct imx_i2c_dma {\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n\tstruct dma_chan *chan_using;\n\tstruct completion cmd_complete;\n\tdma_addr_t dma_buf;\n\tunsigned int dma_len;\n\tenum dma_transfer_direction dma_transfer_dir;\n\tenum dma_data_direction dma_data_dir;\n};\n\nstruct imx_i2c_hwdata {\n\tenum imx_i2c_type devtype;\n\tunsigned int regshift;\n\tstruct imx_i2c_clk_pair *clk_div;\n\tunsigned int ndivs;\n\tunsigned int i2sr_clr_opcode;\n\tunsigned int i2cr_ien_opcode;\n\tbool has_err007805;\n};\n\nstruct imx_i2c_struct {\n\tstruct i2c_adapter adapter;\n\tstruct clk *clk;\n\tstruct notifier_block clk_change_nb;\n\tvoid *base;\n\twait_queue_head_t queue;\n\tlong unsigned int i2csr;\n\tunsigned int disable_delay;\n\tint stopped;\n\tunsigned int ifdr;\n\tunsigned int cur_clk;\n\tunsigned int bitrate;\n\tconst struct imx_i2c_hwdata *hwdata;\n\tstruct i2c_bus_recovery_info rinfo;\n\tstruct imx_i2c_dma *dma;\n\tstruct i2c_client *slave;\n\tenum i2c_slave_event last_slave_event;\n\tstruct i2c_msg *msg;\n\tunsigned int msg_buf_idx;\n\tint isr_result;\n\tbool is_lastmsg;\n\tenum imx_i2c_state state;\n\tbool multi_master;\n\tspinlock_t slave_lock;\n\tstruct hrtimer slave_timer;\n};\n\nstruct imx_icc_noc_setting {\n\tu32 reg;\n\tu32 prio_level;\n\tu32 mode;\n\tu32 ext_control;\n};\n\nstruct imx_icc_node_desc;\n\nstruct imx_icc_provider;\n\nstruct imx_icc_node {\n\tconst struct imx_icc_node_desc *desc;\n\tconst struct imx_icc_noc_setting *setting;\n\tstruct device *qos_dev;\n\tstruct dev_pm_qos_request qos_req;\n\tstruct imx_icc_provider *imx_provider;\n};\n\nstruct imx_icc_node_adj_desc {\n\tunsigned int bw_mul;\n\tunsigned int bw_div;\n\tconst char *phandle_name;\n\tbool main_noc;\n};\n\nstruct imx_icc_node_desc {\n\tconst char *name;\n\tu16 id;\n\tu16 links[4];\n\tu16 num_links;\n\tconst struct imx_icc_node_adj_desc *adj;\n};\n\nstruct imx_icc_provider {\n\tvoid *noc_base;\n\tstruct icc_provider provider;\n};\n\nstruct imx_lpi2c_hwdata {\n\tbool need_request_free_irq;\n\tbool need_prepare_unprepare_clk;\n};\n\nstruct imx_lut_data {\n\tu32 data1;\n\tu32 data2;\n};\n\nstruct imx_mu_con_priv {\n\tunsigned int idx;\n\tchar irq_desc[32];\n\tenum imx_mu_chan_type type;\n\tstruct mbox_chan *chan;\n\tstruct work_struct txdb_work;\n};\n\nstruct imx_mu_priv;\n\nstruct imx_mu_dcfg {\n\tint (*tx)(struct imx_mu_priv *, struct imx_mu_con_priv *, void *);\n\tint (*rx)(struct imx_mu_priv *, struct imx_mu_con_priv *);\n\tint (*rxdb)(struct imx_mu_priv *, struct imx_mu_con_priv *);\n\tint (*init)(struct imx_mu_priv *);\n\tenum imx_mu_type type;\n\tu32 xTR;\n\tu32 xRR;\n\tu32 xSR[4];\n\tu32 xCR[5];\n\tbool skip_suspend_flag;\n};\n\nstruct imx_mu_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *msg;\n\tspinlock_t xcr_lock;\n\tstruct mbox_controller mbox;\n\tstruct mbox_chan mbox_chans[24];\n\tstruct imx_mu_con_priv con_priv[24];\n\tconst struct imx_mu_dcfg *dcfg;\n\tstruct clk *clk;\n\tint irq[24];\n\tbool suspend;\n\tbool side_b;\n\tu32 xcr[5];\n\tu32 num_tr;\n\tu32 num_rr;\n};\n\nstruct imx_pcie_drvdata;\n\nstruct imx_pcie {\n\tstruct dw_pcie *pci;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tbool supports_clkreq;\n\tbool enable_ext_refclk;\n\tstruct regmap *iomuxc_gpr;\n\tu16 msi_ctrl;\n\tu32 controller_id;\n\tstruct reset_control *pciephy_reset;\n\tstruct reset_control *apps_reset;\n\tu32 tx_deemph_gen1;\n\tu32 tx_deemph_gen2_3p5db;\n\tu32 tx_deemph_gen2_6db;\n\tu32 tx_swing_full;\n\tu32 tx_swing_low;\n\tstruct regulator *vpcie;\n\tstruct regulator *vph;\n\tvoid *phy_base;\n\tstruct imx_lut_data luts[32];\n\tstruct device *pd_pcie;\n\tstruct device *pd_pcie_phy;\n\tstruct phy *phy;\n\tconst struct imx_pcie_drvdata *drvdata;\n\tstruct mutex lock;\n};\n\nstruct imx_pcie_drvdata {\n\tenum imx_pcie_variants variant;\n\tenum dw_pcie_device_mode mode;\n\tu32 flags;\n\tint dbi_length;\n\tconst char *gpr;\n\tconst u32 ltssm_off;\n\tconst u32 ltssm_mask;\n\tconst u32 mode_off[2];\n\tconst u32 mode_mask[2];\n\tconst struct pci_epc_features *epc_features;\n\tint (*init_phy)(struct imx_pcie *);\n\tint (*enable_ref_clk)(struct imx_pcie *, bool);\n\tint (*core_reset)(struct imx_pcie *, bool);\n\tint (*wait_pll_lock)(struct imx_pcie *);\n\tvoid (*clr_clkreq_override)(struct imx_pcie *);\n\tconst struct dw_pcie_host_ops *ops;\n};\n\nstruct imx_pgc_regs;\n\nstruct imx_pgc_domain {\n\tstruct generic_pm_domain genpd;\n\tstruct regmap *regmap;\n\tconst struct imx_pgc_regs *regs;\n\tstruct regulator *regulator;\n\tstruct reset_control *reset;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tlong unsigned int pgc;\n\tconst struct {\n\t\tu32 pxx;\n\t\tu32 map;\n\t\tu32 hskreq;\n\t\tu32 hskack;\n\t} bits;\n\tconst int voltage;\n\tconst bool keep_clocks;\n\tstruct device *dev;\n\tunsigned int pgc_sw_pup_reg;\n\tunsigned int pgc_sw_pdn_reg;\n};\n\nstruct imx_pgc_domain_data {\n\tconst struct imx_pgc_domain *domains;\n\tsize_t domains_num;\n\tconst struct regmap_access_table *reg_access_table;\n\tconst struct imx_pgc_regs *pgc_regs;\n};\n\nstruct imx_pgc_regs {\n\tu16 map;\n\tu16 pup;\n\tu16 pdn;\n\tu16 hsk;\n};\n\nstruct imx_pin_mmio {\n\tunsigned int mux_mode;\n\tu16 input_reg;\n\tunsigned int input_val;\n\tlong unsigned int config;\n};\n\nstruct imx_pin_scu {\n\tunsigned int mux_mode;\n\tlong unsigned int config;\n};\n\nstruct imx_pin {\n\tunsigned int pin;\n\tunion {\n\t\tstruct imx_pin_mmio mmio;\n\t\tstruct imx_pin_scu scu;\n\t} conf;\n};\n\nstruct imx_pin_reg {\n\ts16 mux_reg;\n\ts16 conf_reg;\n};\n\nstruct imx_pinctrl_soc_info;\n\nstruct imx_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tvoid *base;\n\tvoid *input_sel_base;\n\tconst struct imx_pinctrl_soc_info *info;\n\tstruct imx_pin_reg *pin_regs;\n\tunsigned int group_index;\n\tstruct mutex mutex;\n};\n\nstruct imx_pinctrl_soc_info {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tunsigned int flags;\n\tconst char *gpr_compatible;\n\tunsigned int mux_mask;\n\tu8 mux_shift;\n\tint (*gpio_set_direction)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int, bool);\n\tint (*imx_pinconf_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*imx_pinconf_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tvoid (*imx_pinctrl_parse_pin)(struct imx_pinctrl *, unsigned int *, struct imx_pin *, const __be32 **);\n};\n\nstruct imx_pll14xx_clk {\n\tenum imx_pll14xx_type type;\n\tconst struct imx_pll14xx_rate_table *rate_table;\n\tint rate_count;\n\tint flags;\n};\n\nstruct imx_pll14xx_rate_table {\n\tunsigned int rate;\n\tunsigned int pdiv;\n\tunsigned int mdiv;\n\tunsigned int sdiv;\n\tunsigned int kdiv;\n};\n\nstruct imx_uart_data;\n\nstruct mctrl_gpios;\n\nstruct imx_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tunsigned int old_status;\n\tunsigned int have_rtscts: 1;\n\tunsigned int have_rtsgpio: 1;\n\tunsigned int dte_mode: 1;\n\tunsigned int inverted_tx: 1;\n\tunsigned int inverted_rx: 1;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_per;\n\tconst struct imx_uart_data *devdata;\n\tstruct mctrl_gpios *gpios;\n\tint idle_counter;\n\tunsigned int dma_is_enabled: 1;\n\tunsigned int dma_is_rxing: 1;\n\tunsigned int dma_is_txing: 1;\n\tstruct dma_chan *dma_chan_rx;\n\tstruct dma_chan *dma_chan_tx;\n\tstruct scatterlist rx_sgl;\n\tstruct scatterlist tx_sgl[2];\n\tvoid *rx_buf;\n\tstruct circ_buf rx_ring;\n\tunsigned int rx_buf_size;\n\tunsigned int rx_period_length;\n\tunsigned int rx_periods;\n\tdma_cookie_t rx_cookie;\n\tunsigned int tx_bytes;\n\tunsigned int dma_tx_nents;\n\tunsigned int saved_reg[10];\n\tbool context_saved;\n\tbool last_putchar_was_newline;\n\tenum imx_tx_state tx_state;\n\tstruct hrtimer trigger_start_tx;\n\tstruct hrtimer trigger_stop_tx;\n\tunsigned int rxtl;\n};\n\nstruct imx_port_ucrs {\n\tunsigned int ucr1;\n\tunsigned int ucr2;\n\tunsigned int ucr3;\n};\n\nstruct imx_rproc_mem {\n\tvoid *cpu_addr;\n\tphys_addr_t sys_addr;\n\tsize_t size;\n};\n\nstruct rproc;\n\nstruct imx_rproc_dcfg;\n\nstruct imx_rproc_plat_ops;\n\nstruct imx_rproc {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct regmap *gpr;\n\tstruct rproc *rproc;\n\tconst struct imx_rproc_dcfg *dcfg;\n\tstruct imx_rproc_mem mem[32];\n\tstruct clk *clk;\n\tstruct mbox_client cl;\n\tstruct mbox_chan *tx_ch;\n\tstruct mbox_chan *rx_ch;\n\tstruct work_struct rproc_work;\n\tstruct workqueue_struct *workqueue;\n\tvoid *rsc_table;\n\tstruct imx_sc_ipc *ipc_handle;\n\tstruct notifier_block rproc_nb;\n\tu32 rproc_pt;\n\tu32 rsrc_id;\n\tu32 entry;\n\tu32 core_index;\n\tstruct dev_pm_domain_list *pd_list;\n\tconst struct imx_rproc_plat_ops *ops;\n\tu32 flags;\n};\n\nstruct imx_rproc_att {\n\tu32 da;\n\tu32 sa;\n\tu32 size;\n\tint flags;\n};\n\nstruct imx_rproc_dcfg {\n\tu32 src_reg;\n\tu32 src_mask;\n\tu32 src_start;\n\tu32 src_stop;\n\tu32 gpr_reg;\n\tu32 gpr_wait;\n\tconst struct imx_rproc_att *att;\n\tsize_t att_size;\n\tu32 flags;\n\tconst struct imx_rproc_plat_ops *ops;\n\tu32 cpuid;\n\tu32 lmid;\n};\n\nstruct imx_rproc_plat_ops {\n\tint (*start)(struct rproc *);\n\tint (*stop)(struct rproc *);\n\tint (*detach)(struct rproc *);\n\tint (*detect_mode)(struct rproc *);\n\tint (*prepare)(struct rproc *);\n};\n\nstruct imx_s4_rpc_msg {\n\tuint8_t ver;\n\tuint8_t size;\n\tuint8_t cmd;\n\tuint8_t tag;\n};\n\nstruct imx_s4_rpc_msg_max {\n\tstruct imx_s4_rpc_msg hdr;\n\tu32 data[254];\n};\n\nstruct imx_sc_chan {\n\tstruct imx_sc_ipc *sc_ipc;\n\tstruct mbox_client cl;\n\tstruct mbox_chan *ch;\n\tint idx;\n\tstruct completion tx_done;\n};\n\nstruct imx_sc_ipc {\n\tstruct imx_sc_chan chans[8];\n\tstruct device *dev;\n\tstruct mutex lock;\n\tstruct completion done;\n\tbool fast_ipc;\n\tu32 *msg;\n\tu8 rx_size;\n\tu8 count;\n};\n\nstruct imx_sc_rpc_msg {\n\tuint8_t ver;\n\tuint8_t size;\n\tuint8_t svc;\n\tuint8_t func;\n};\n\nstruct req_get_clock_parent {\n\t__le16 resource;\n\tu8 clk;\n};\n\nstruct resp_get_clock_parent {\n\tu8 parent;\n};\n\nstruct imx_sc_msg_get_clock_parent {\n\tstruct imx_sc_rpc_msg hdr;\n\tunion {\n\t\tstruct req_get_clock_parent req;\n\t\tstruct resp_get_clock_parent resp;\n\t} data;\n};\n\nstruct req_get_clock_rate {\n\t__le16 resource;\n\tu8 clk;\n};\n\nstruct resp_get_clock_rate {\n\t__le32 rate;\n};\n\nstruct imx_sc_msg_get_clock_rate {\n\tstruct imx_sc_rpc_msg hdr;\n\tunion {\n\t\tstruct req_get_clock_rate req;\n\t\tstruct resp_get_clock_rate resp;\n\t} data;\n};\n\nstruct imx_sc_msg_gpio_set_pad_wakeup {\n\tstruct imx_sc_rpc_msg hdr;\n\tu16 pad;\n\tu8 wakeup;\n};\n\nstruct imx_sc_msg_irq_enable {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 mask;\n\tu16 resource;\n\tu8 group;\n\tu8 enable;\n};\n\nstruct imx_sc_msg_irq_get_status {\n\tstruct imx_sc_rpc_msg hdr;\n\tunion {\n\t\tstruct {\n\t\t\tu16 resource;\n\t\t\tu8 group;\n\t\t\tu8 reserved;\n\t\t} req;\n\t\tstruct {\n\t\t\tu32 status;\n\t\t} resp;\n\t} data;\n};\n\nstruct imx_sc_msg_misc_fuse_read {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 word;\n};\n\nstruct imx_sc_msg_misc_get_soc_id {\n\tstruct imx_sc_rpc_msg hdr;\n\tunion {\n\t\tstruct {\n\t\t\tu32 control;\n\t\t\tu16 resource;\n\t\t} __attribute__((packed)) req;\n\t\tstruct {\n\t\t\tu32 id;\n\t\t} resp;\n\t} data;\n};\n\nstruct imx_sc_msg_misc_get_soc_uid {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 uid_low;\n\tu32 uid_high;\n};\n\nstruct imx_sc_msg_req_clock_enable {\n\tstruct imx_sc_rpc_msg hdr;\n\t__le16 resource;\n\tu8 clk;\n\tu8 enable;\n\tu8 autog;\n\tint: 0;\n};\n\nstruct imx_sc_msg_req_cpu_start {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 address_hi;\n\tu32 address_lo;\n\tu16 resource;\n\tu8 enable;\n};\n\nstruct req_get_resource_mode {\n\tu16 resource;\n};\n\nstruct resp_get_resource_mode {\n\tu8 mode;\n};\n\nstruct imx_sc_msg_req_get_resource_power_mode {\n\tstruct imx_sc_rpc_msg hdr;\n\tunion {\n\t\tstruct req_get_resource_mode req;\n\t\tstruct resp_get_resource_mode resp;\n\t} data;\n\tlong: 0;\n};\n\nstruct imx_sc_msg_req_misc_get_ctrl {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 ctrl;\n\tu16 resource;\n};\n\nstruct imx_sc_msg_req_misc_set_ctrl {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 ctrl;\n\tu32 val;\n\tu16 resource;\n};\n\nstruct imx_sc_msg_req_pad_get {\n\tstruct imx_sc_rpc_msg hdr;\n\tu16 pad;\n\tlong: 0;\n};\n\nstruct imx_sc_msg_req_pad_set {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 val;\n\tu16 pad;\n};\n\nstruct imx_sc_msg_req_set_clock_rate {\n\tstruct imx_sc_rpc_msg hdr;\n\t__le32 rate;\n\t__le16 resource;\n\tu8 clk;\n};\n\nstruct imx_sc_msg_req_set_resource_power_mode {\n\tstruct imx_sc_rpc_msg hdr;\n\tu16 resource;\n\tu8 mode;\n};\n\nstruct imx_sc_msg_resp_misc_get_ctrl {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 val;\n};\n\nstruct imx_sc_msg_resp_pad_get {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 val;\n};\n\nstruct imx_sc_msg_rm_get_resource_owner {\n\tstruct imx_sc_rpc_msg hdr;\n\tunion {\n\t\tstruct {\n\t\t\tu16 resource;\n\t\t} req;\n\t\tstruct {\n\t\t\tu8 val;\n\t\t} resp;\n\t} data;\n\tlong: 0;\n};\n\nstruct imx_sc_msg_rm_rsrc_owned {\n\tstruct imx_sc_rpc_msg hdr;\n\tu16 resource;\n\tlong: 0;\n};\n\nstruct imx_sc_msg_set_clock_parent {\n\tstruct imx_sc_rpc_msg hdr;\n\t__le16 resource;\n\tu8 clk;\n\tu8 parent;\n};\n\nstruct imx_sc_pd_range {\n\tchar *name;\n\tu32 rsrc;\n\tu8 num;\n\tbool postfix;\n\tu8 start_from;\n};\n\nstruct imx_sc_pd_soc {\n\tconst struct imx_sc_pd_range *pd_ranges;\n\tu8 num_ranges;\n};\n\nstruct imx_sc_pm_domain {\n\tstruct generic_pm_domain pd;\n\tchar name[20];\n\tu32 rsrc;\n};\n\nstruct imx_sc_rpc_msg_max {\n\tstruct imx_sc_rpc_msg hdr;\n\tu32 data[30];\n};\n\nstruct imx_scu_clk_node {\n\tconst char *name;\n\tu32 rsrc;\n\tu8 clk_type;\n\tconst char * const *parents;\n\tint num_parents;\n\tstruct clk_hw *hw;\n\tstruct list_head node;\n};\n\nstruct imx_uart_data {\n\tunsigned int uts_reg;\n\tenum imx_uart_type devtype;\n};\n\nstruct usbmisc_ops;\n\nstruct imx_usbmisc {\n\tvoid *base;\n\tvoid *blkctl;\n\tspinlock_t lock;\n\tconst struct usbmisc_ops *ops;\n};\n\nstruct imx_usbmisc_data {\n\tstruct device *dev;\n\tint index;\n\tunsigned int disable_oc: 1;\n\tunsigned int oc_pol_active_low: 1;\n\tunsigned int oc_pol_configured: 1;\n\tunsigned int pwr_pol: 1;\n\tunsigned int evdo: 1;\n\tunsigned int ulpi: 1;\n\tunsigned int hsic: 1;\n\tunsigned int ext_id: 1;\n\tunsigned int ext_vbus: 1;\n\tstruct usb_phy *usb_phy;\n\tenum usb_dr_mode available_role;\n\tint emp_curr_control;\n\tint dc_vol_level_adjust;\n\tint rise_fall_time_adjust;\n};\n\nstruct imxi2c_platform_data {\n\tu32 bitrate;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[1];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pin {\n\tu32 enable_mask;\n\tu32 value_mask;\n\tstruct gpio_desc *gpiod;\n\tconst char *name;\n\tstruct brcmstb_usb_pinmap_data *pdata;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv6_txoptions;\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n\tu8 dontfrag: 1;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_skb_parm;\n\nstruct inet6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tshort unsigned int addr_type;\n\tstruct in6_addr v6_rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n\tstruct inet6_cork base6;\n};\n\nstruct ipv6_pinfo;\n\nstruct ipv6_fl_socklist;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_diag_bc_op {\n\tunsigned char code;\n\tunsigned char yes;\n\tshort unsigned int no;\n};\n\nstruct inet_diag_dump_data {\n\tstruct nlattr *req_nlas[4];\n\tstruct bpf_sk_storage_diag *bpf_stg_diag;\n\tbool mark_needed;\n\tbool cgroup_needed;\n\tbool userlocks_needed;\n};\n\nstruct inet_diag_entry {\n\tconst __be32 *saddr;\n\tconst __be32 *daddr;\n\tu16 sport;\n\tu16 dport;\n\tu16 family;\n\tu16 userlocks;\n\tu32 ifindex;\n\tu32 mark;\n\tu64 cgroup_id;\n};\n\nstruct inet_diag_req_v2;\n\nstruct inet_diag_msg;\n\nstruct inet_diag_handler {\n\tstruct module *owner;\n\tvoid (*dump)(struct sk_buff *, struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tint (*dump_one)(struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tvoid (*idiag_get_info)(struct sock *, struct inet_diag_msg *, void *);\n\tint (*idiag_get_aux)(struct sock *, bool, struct sk_buff *);\n\tint (*destroy)(struct sk_buff *, const struct inet_diag_req_v2 *);\n\t__u16 idiag_type;\n\t__u16 idiag_info_size;\n};\n\nstruct inet_diag_hostcond {\n\t__u8 family;\n\t__u8 prefix_len;\n\tint port;\n\t__be32 addr[0];\n};\n\nstruct inet_diag_markcond {\n\t__u32 mark;\n\t__u32 mask;\n};\n\nstruct inet_diag_meminfo {\n\t__u32 idiag_rmem;\n\t__u32 idiag_wmem;\n\t__u32 idiag_fmem;\n\t__u32 idiag_tmem;\n};\n\nstruct inet_diag_sockid {\n\t__be16 idiag_sport;\n\t__be16 idiag_dport;\n\t__be32 idiag_src[4];\n\t__be32 idiag_dst[4];\n\t__u32 idiag_if;\n\t__u32 idiag_cookie[2];\n};\n\nstruct inet_diag_msg {\n\t__u8 idiag_family;\n\t__u8 idiag_state;\n\t__u8 idiag_timer;\n\t__u8 idiag_retrans;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_expires;\n\t__u32 idiag_rqueue;\n\t__u32 idiag_wqueue;\n\t__u32 idiag_uid;\n\t__u32 idiag_inode;\n};\n\nstruct inet_diag_req {\n\t__u8 idiag_family;\n\t__u8 idiag_src_len;\n\t__u8 idiag_dst_len;\n\t__u8 idiag_ext;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_states;\n\t__u32 idiag_dbs;\n};\n\nstruct inet_diag_req_v2 {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u8 idiag_ext;\n\t__u8 pad;\n\t__u32 idiag_states;\n\tstruct inet_diag_sockid id;\n};\n\nstruct inet_diag_sockopt {\n\t__u8 recverr: 1;\n\t__u8 is_icsk: 1;\n\t__u8 freebind: 1;\n\t__u8 hdrincl: 1;\n\t__u8 mc_loop: 1;\n\t__u8 transparent: 1;\n\t__u8 mc_all: 1;\n\t__u8 nodefrag: 1;\n\t__u8 bind_address_no_port: 1;\n\t__u8 recverr_rfc4884: 1;\n\t__u8 defer_connect: 1;\n\t__u8 unused: 5;\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct proto_ops;\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\nstruct init_data {\n\tunsigned int dmem_len;\n\tunsigned int imem_len;\n\tunsigned int chksum;\n\tbool is_big_endian;\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inode_switch_wbs_context {\n\tstruct llist_node list;\n\tstruct inode *inodes[0];\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[12];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[1];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[2];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[12];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[12];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[1];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[2];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_event_compat {\n\tcompat_ulong_t sec;\n\tcompat_ulong_t usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_led {\n\tstruct led_classdev cdev;\n\tstruct input_handle *handle;\n\tunsigned int code;\n};\n\nstruct input_leds {\n\tstruct input_handle handle;\n\tunsigned int num_leds;\n\tstruct input_led leds[0];\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nstruct instance_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_instance *, char *);\n\tssize_t (*store)(struct edac_device_instance *, const char *, size_t);\n};\n\nstruct instance_attribute___2 {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_pci_ctl_info *, char *);\n\tssize_t (*store)(struct edac_pci_ctl_info *, const char *, size_t);\n};\n\nstruct intel_host {\n\tu32 dsm_fns;\n\tu32 hs_caps;\n};\n\nstruct intent_pair {\n\t__le32 size;\n\t__le32 iid;\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct intmux_irqchip_data {\n\tu32 saved_reg;\n\tint chanidx;\n\tint irq;\n\tstruct irq_domain *domain;\n};\n\nstruct intmux_data {\n\traw_spinlock_t lock;\n\tvoid *regs;\n\tstruct clk *ipg_clk;\n\tint channum;\n\tstruct intmux_irqchip_data irqchip_data[0];\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n\tspinlock_t lock;\n\tstruct xarray icq_tree;\n\tstruct io_cq *icq_hint;\n\tstruct hlist_head icq_list;\n\tstruct work_struct release_work;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pgtable_init_fns {\n\tstruct io_pgtable * (*alloc)(struct io_pgtable_cfg *, void *);\n\tvoid (*free)(struct io_pgtable *);\n\tu32 caps;\n};\n\nstruct io_pgtable_walk_data {\n\tstruct io_pgtable *iop;\n\tvoid *data;\n\tint (*visit)(struct io_pgtable_walk_data *, int, arm_lpae_iopte *, size_t);\n\tlong unsigned int flags;\n\tu64 addr;\n\tconst u64 end;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[1];\n\tlong unsigned int sqe_op[2];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 64;\n\tlong: 64;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tlb_area {\n\tlong unsigned int used;\n\tunsigned int index;\n\tspinlock_t lock;\n};\n\nstruct io_tlb_slot;\n\nstruct io_tlb_pool {\n\tphys_addr_t start;\n\tphys_addr_t end;\n\tvoid *vaddr;\n\tlong unsigned int nslabs;\n\tbool late_alloc;\n\tunsigned int nareas;\n\tunsigned int area_nslabs;\n\tstruct io_tlb_area *areas;\n\tstruct io_tlb_slot *slots;\n};\n\nstruct io_tlb_mem {\n\tstruct io_tlb_pool defpool;\n\tlong unsigned int nslabs;\n\tstruct dentry *debugfs;\n\tbool force_bounce;\n\tbool for_alloc;\n\tatomic_long_t total_used;\n\tatomic_long_t used_hiwater;\n\tatomic_long_t transient_nslabs;\n};\n\nstruct io_tlb_slot {\n\tphys_addr_t orig_addr;\n\tsize_t alloc_size;\n\tshort unsigned int list;\n\tshort unsigned int pad_slots;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 64;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[64];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n\tlong: 64;\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct ioctl_evtchn_bind {\n\tunsigned int port;\n};\n\nstruct ioctl_evtchn_bind_interdomain {\n\tunsigned int remote_domain;\n\tunsigned int remote_port;\n};\n\nstruct ioctl_evtchn_bind_unbound_port {\n\tunsigned int remote_domain;\n};\n\nstruct ioctl_evtchn_bind_virq {\n\tunsigned int virq;\n};\n\nstruct ioctl_evtchn_notify {\n\tunsigned int port;\n};\n\nstruct ioctl_evtchn_restrict_domid {\n\tdomid_t domid;\n};\n\nstruct ioctl_evtchn_unbind {\n\tunsigned int port;\n};\n\nstruct ioctl_gntalloc_alloc_gref {\n\t__u16 domid;\n\t__u16 flags;\n\t__u32 count;\n\t__u64 index;\n\tunion {\n\t\t__u32 gref_ids[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_gref_ids_flex;\n\t\t\t__u32 gref_ids_flex[0];\n\t\t};\n\t};\n};\n\nstruct ioctl_gntalloc_dealloc_gref {\n\t__u64 index;\n\t__u32 count;\n};\n\nstruct ioctl_gntalloc_unmap_notify {\n\t__u64 index;\n\t__u32 action;\n\t__u32 event_channel_port;\n};\n\nstruct ioctl_gntdev_get_offset_for_vaddr {\n\t__u64 vaddr;\n\t__u64 offset;\n\t__u32 count;\n\t__u32 pad;\n};\n\nstruct ioctl_gntdev_grant_copy {\n\tunsigned int count;\n\tstruct gntdev_grant_copy_segment *segments;\n};\n\nstruct ioctl_gntdev_grant_ref {\n\t__u32 domid;\n\t__u32 ref;\n};\n\nstruct ioctl_gntdev_map_grant_ref {\n\t__u32 count;\n\t__u32 pad;\n\t__u64 index;\n\tstruct ioctl_gntdev_grant_ref refs[1];\n};\n\nstruct ioctl_gntdev_unmap_grant_ref {\n\t__u64 index;\n\t__u32 count;\n\t__u32 pad;\n};\n\nstruct ioctl_gntdev_unmap_notify {\n\t__u64 index;\n\t__u32 action;\n\t__u32 event_channel_port;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tstruct bio io_bio;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n};\n\nstruct iommu_attach_handle {\n\tstruct iommu_domain *domain;\n};\n\nstruct iova_bitmap;\n\nstruct iommu_dirty_bitmap {\n\tstruct iova_bitmap *bitmap;\n\tstruct iommu_iotlb_gather *gather;\n};\n\nstruct iommu_dirty_ops {\n\tint (*set_dirty_tracking)(struct iommu_domain *, bool);\n\tint (*read_and_clear_dirty)(struct iommu_domain *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct iova {\n\tstruct rb_node node;\n\tlong unsigned int pfn_hi;\n\tlong unsigned int pfn_lo;\n};\n\nstruct iova_rcache;\n\nstruct iova_domain {\n\tspinlock_t iova_rbtree_lock;\n\tstruct rb_root rbroot;\n\tstruct rb_node *cached_node;\n\tstruct rb_node *cached32_node;\n\tlong unsigned int granule;\n\tlong unsigned int start_pfn;\n\tlong unsigned int dma_32bit_pfn;\n\tlong unsigned int max32_alloc_size;\n\tstruct iova anchor;\n\tstruct iova_rcache *rcaches;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct iommu_dma_options {\n\tenum iommu_dma_queue_type qt;\n\tsize_t fq_size;\n\tunsigned int fq_timeout;\n};\n\nstruct iova_fq;\n\nstruct iommu_dma_cookie {\n\tstruct iova_domain iovad;\n\tstruct list_head msi_page_list;\n\tunion {\n\t\tstruct iova_fq *single_fq;\n\t\tstruct iova_fq *percpu_fq;\n\t};\n\tatomic64_t fq_flush_start_cnt;\n\tatomic64_t fq_flush_finish_cnt;\n\tstruct timer_list fq_timer;\n\tatomic_t fq_timer_on;\n\tstruct iommu_domain *fq_domain;\n\tstruct iommu_dma_options options;\n};\n\nstruct iommu_dma_msi_cookie {\n\tdma_addr_t msi_iova;\n\tstruct list_head msi_page_list;\n};\n\nstruct iommu_dma_msi_page {\n\tstruct list_head list;\n\tdma_addr_t iova;\n\tphys_addr_t phys;\n};\n\nstruct iommu_user_data_array;\n\nstruct iommu_domain_ops {\n\tint (*attach_dev)(struct iommu_domain *, struct device *, struct iommu_domain *);\n\tint (*set_dev_pasid)(struct iommu_domain *, struct device *, ioasid_t, struct iommu_domain *);\n\tint (*map_pages)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct iommu_domain *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tint (*iotlb_sync_map)(struct iommu_domain *, long unsigned int, size_t);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tint (*cache_invalidate_user)(struct iommu_domain *, struct iommu_user_data_array *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tbool (*enforce_cache_coherency)(struct iommu_domain *);\n\tint (*set_pgtable_quirks)(struct iommu_domain *, long unsigned int);\n\tvoid (*free)(struct iommu_domain *);\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iommu_fault_param {\n\tstruct mutex lock;\n\trefcount_t users;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n\tstruct iopf_queue *queue;\n\tstruct list_head queue_list;\n\tstruct list_head partial;\n\tstruct list_head faults;\n};\n\nstruct iommu_flush_ops {\n\tvoid (*tlb_flush_all)(void *);\n\tvoid (*tlb_flush_walk)(long unsigned int, size_t, size_t, void *);\n\tvoid (*tlb_add_page)(struct iommu_iotlb_gather *, long unsigned int, size_t, void *);\n};\n\nstruct iommu_fwspec {\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct xarray pasid_array;\n\tstruct mutex mutex;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *blocking_domain;\n\tstruct iommu_domain *resetting_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n\tunsigned int owner_cnt;\n\tvoid *owner;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n\tvoid (*free)(struct device *, struct iommu_resv_region *);\n};\n\nstruct iommu_iort_rmr_data {\n\tstruct iommu_resv_region rr;\n\tconst u32 *sids;\n\tu32 num_sids;\n};\n\nstruct iommu_pages_list {\n\tstruct list_head pages;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n\tstruct iommu_pages_list freelist;\n\tbool queued;\n};\n\nstruct iopf_fault;\n\nstruct iommu_page_response;\n\nstruct iommu_ops {\n\tbool (*capable)(struct device *, enum iommu_cap);\n\tvoid * (*hw_info)(struct device *, u32 *, enum iommu_hw_info_type *);\n\tstruct iommu_domain * (*domain_alloc_identity)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_paging_flags)(struct device *, u32, const struct iommu_user_data *);\n\tstruct iommu_domain * (*domain_alloc_paging)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_sva)(struct device *, struct mm_struct *);\n\tstruct iommu_domain * (*domain_alloc_nested)(struct device *, struct iommu_domain *, u32, const struct iommu_user_data *);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tint (*of_xlate)(struct device *, const struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct device *);\n\tvoid (*page_response)(struct device *, struct iopf_fault *, struct iommu_page_response *);\n\tint (*def_domain_type)(struct device *);\n\tsize_t (*get_viommu_size)(struct device *, enum iommu_viommu_type);\n\tint (*viommu_init)(struct iommufd_viommu *, struct iommu_domain *, const struct iommu_user_data *);\n\tconst struct iommu_domain_ops *default_domain_ops;\n\tstruct module *owner;\n\tstruct iommu_domain *identity_domain;\n\tstruct iommu_domain *blocked_domain;\n\tstruct iommu_domain *release_domain;\n\tstruct iommu_domain *default_domain;\n\tu8 user_pasid_table: 1;\n};\n\nstruct iommu_page_response {\n\tu32 pasid;\n\tu32 grpid;\n\tu32 code;\n};\n\nstruct iommu_user_data {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t len;\n};\n\nstruct iommu_user_data_array {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t entry_len;\n\tu32 entry_num;\n};\n\nstruct iommufd_access;\n\nstruct iommufd_hw_queue {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_access *access;\n\tu64 base_addr;\n\tsize_t length;\n\tenum iommu_hw_queue_type type;\n\tvoid (*destroy)(struct iommufd_hw_queue *);\n};\n\nstruct iommufd_device;\n\nstruct iommufd_vdevice {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_device *idev;\n\tu64 virt_id;\n\tvoid (*destroy)(struct iommufd_vdevice *);\n};\n\nstruct iommufd_viommu_ops {\n\tvoid (*destroy)(struct iommufd_viommu *);\n\tstruct iommu_domain * (*alloc_domain_nested)(struct iommufd_viommu *, u32, const struct iommu_user_data *);\n\tint (*cache_invalidate)(struct iommufd_viommu *, struct iommu_user_data_array *);\n\tconst size_t vdevice_size;\n\tint (*vdevice_init)(struct iommufd_vdevice *);\n\tsize_t (*get_hw_queue_size)(struct iommufd_viommu *, enum iommu_hw_queue_type);\n\tint (*hw_queue_init_phys)(struct iommufd_hw_queue *, u32, phys_addr_t);\n};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct iopf_queue {\n\tstruct workqueue_struct *wq;\n\tstruct list_head devices;\n\tstruct mutex lock;\n};\n\nstruct ioptdesc {\n\tlong unsigned int __page_flags;\n\tstruct list_head iopt_freelist_elm;\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tu8 incoherent;\n\t\tlong unsigned int __index;\n\t};\n\tvoid *_private;\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct iort_dev_config {\n\tconst char *name;\n\tint (*dev_init)(struct acpi_iort_node *);\n\tvoid (*dev_dma_configure)(struct device *, struct acpi_iort_node *);\n\tint (*dev_count_resources)(struct acpi_iort_node *);\n\tvoid (*dev_init_resources)(struct resource *, struct acpi_iort_node *);\n\tint (*dev_set_proximity)(struct device *, struct acpi_iort_node *);\n\tint (*dev_add_platdata)(struct platform_device *);\n};\n\nstruct iort_fwnode {\n\tstruct list_head list;\n\tstruct acpi_iort_node *iort_node;\n\tstruct fwnode_handle *fwnode;\n};\n\nstruct iort_its_msi_chip {\n\tstruct list_head list;\n\tstruct fwnode_handle *fw_node;\n\tphys_addr_t base_addr;\n\tu32 translation_id;\n};\n\nstruct iort_pci_alias_info {\n\tstruct device *dev;\n\tstruct acpi_iort_node *node;\n};\n\nstruct iova_magazine;\n\nstruct iova_cpu_rcache {\n\tspinlock_t lock;\n\tstruct iova_magazine *loaded;\n\tstruct iova_magazine *prev;\n};\n\nstruct iova_fq_entry {\n\tlong unsigned int iova_pfn;\n\tlong unsigned int pages;\n\tstruct iommu_pages_list freelist;\n\tu64 counter;\n};\n\nstruct iova_fq {\n\tspinlock_t lock;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int mod_mask;\n\tstruct iova_fq_entry entries[0];\n};\n\nstruct iova_magazine {\n\tunion {\n\t\tlong unsigned int size;\n\t\tstruct iova_magazine *next;\n\t};\n\tlong unsigned int pfns[127];\n};\n\nstruct iova_rcache {\n\tspinlock_t lock;\n\tunsigned int depot_size;\n\tstruct iova_magazine *depot;\n\tstruct iova_cpu_rcache *cpu_rcaches;\n\tstruct iova_domain *iovad;\n\tstruct delayed_work work;\n};\n\nstruct iova_to_phys_data {\n\tarm_lpae_iopte pte;\n\tint lvl;\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct ip6_rt_info {\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\tu_int32_t mark;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap;\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_conntrack_stat {\n\tunsigned int found;\n\tunsigned int invalid;\n\tunsigned int insert;\n\tunsigned int insert_failed;\n\tunsigned int clash_resolve;\n\tunsigned int drop;\n\tunsigned int early_drop;\n\tunsigned int error;\n\tunsigned int expect_new;\n\tunsigned int expect_create;\n\tunsigned int expect_delete;\n\tunsigned int search_restart;\n\tunsigned int chaintoolong;\n};\n\nstruct ip_ct_sctp {\n\tenum sctp_conntrack state;\n\t__be32 vtag[2];\n\tu8 init[2];\n\tu8 last_dir;\n\tu8 flags;\n};\n\nstruct ip_ct_tcp_state {\n\tu_int32_t td_end;\n\tu_int32_t td_maxend;\n\tu_int32_t td_maxwin;\n\tu_int32_t td_maxack;\n\tu_int8_t td_scale;\n\tu_int8_t flags;\n};\n\nstruct ip_ct_tcp {\n\tstruct ip_ct_tcp_state seen[2];\n\tu_int8_t state;\n\tu_int8_t last_dir;\n\tu_int8_t retrans;\n\tu_int8_t last_index;\n\tu_int32_t last_seq;\n\tu_int32_t last_ack;\n\tu_int32_t last_end;\n\tu_int16_t last_win;\n\tu_int8_t last_wscale;\n\tu_int8_t last_flags;\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct unix_domain;\n\nstruct ip_map {\n\tstruct cache_head h;\n\tchar m_class[8];\n\tstruct in6_addr m_addr;\n\tstruct unix_domain *m_client;\n\tstruct callback_head m_rcu;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_rt_info {\n\t__be32 daddr;\n\t__be32 saddr;\n\tu_int8_t tos;\n\tu_int32_t mark;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 0;\n\tu8 options[0];\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned char __pad1[0];\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\t__kernel_ulong_t __unused1;\n\t__kernel_ulong_t __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tstruct rhashtable key_ht;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipi_descs {\n\tstruct irq_desc *descs[8];\n};\n\nstruct ipi_mux_cpu {\n\tatomic_t enable;\n\tatomic_t bits;\n};\n\nstruct ipmi_dmi_info {\n\tenum si_type si_type;\n\tunsigned int space;\n\tlong unsigned int addr;\n\tu8 slave_addr;\n\tstruct ipmi_dmi_info *next;\n};\n\nstruct ipmi_plat_data {\n\tenum ipmi_plat_interface_type iftype;\n\tunsigned int type;\n\tunsigned int space;\n\tlong unsigned int addr;\n\tunsigned int regspacing;\n\tunsigned int regsize;\n\tunsigned int regshift;\n\tunsigned int irq;\n\tunsigned int slave_addr;\n\tenum ipmi_addr_src addr_source;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipq5018_priv {\n\tstruct reset_control *rst;\n\tbool set_short_cable_dac;\n};\n\nstruct iproc_arm_pll {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tlong unsigned int rate;\n};\n\nstruct iproc_asiu_clk;\n\nstruct iproc_asiu {\n\tvoid *div_base;\n\tvoid *gate_base;\n\tstruct clk_hw_onecell_data *clk_data;\n\tstruct iproc_asiu_clk *clks;\n};\n\nstruct iproc_asiu_div {\n\tunsigned int offset;\n\tunsigned int en_shift;\n\tunsigned int high_shift;\n\tunsigned int high_width;\n\tunsigned int low_shift;\n\tunsigned int low_width;\n};\n\nstruct iproc_asiu_gate {\n\tunsigned int offset;\n\tunsigned int en_shift;\n};\n\nstruct iproc_asiu_clk {\n\tstruct clk_hw hw;\n\tconst char *name;\n\tstruct iproc_asiu *asiu;\n\tlong unsigned int rate;\n\tstruct iproc_asiu_div div;\n\tstruct iproc_asiu_gate gate;\n};\n\nstruct iproc_pll;\n\nstruct iproc_clk_ctrl;\n\nstruct iproc_clk {\n\tstruct clk_hw hw;\n\tstruct iproc_pll *pll;\n\tconst struct iproc_clk_ctrl *ctrl;\n};\n\nstruct iproc_clk_enable_ctrl {\n\tunsigned int offset;\n\tunsigned int enable_shift;\n\tunsigned int hold_shift;\n\tunsigned int bypass_shift;\n};\n\nstruct iproc_clk_reg_op {\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int width;\n};\n\nstruct iproc_clk_ctrl {\n\tunsigned int channel;\n\tlong unsigned int flags;\n\tstruct iproc_clk_enable_ctrl enable;\n\tstruct iproc_clk_reg_op mdiv;\n};\n\nstruct iproc_gpio {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *io_ctrl;\n\tenum iproc_pinconf_ctrl_type io_ctrl_type;\n\traw_spinlock_t lock;\n\tstruct gpio_chip gc;\n\tunsigned int num_banks;\n\tbool pinmux_is_supported;\n\tenum pin_config_param *pinconf_disable;\n\tunsigned int nr_pinconf_disable;\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc pctldesc;\n};\n\nstruct iproc_gpio_chip {\n\tstruct gpio_generic_chip gen_gc;\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *intr;\n};\n\nstruct iproc_mdio_priv {\n\tstruct mii_bus *mii_bus;\n\tvoid *base;\n};\n\nstruct iproc_mdiomux_desc {\n\tvoid *mux_handle;\n\tvoid *base;\n\tstruct device *dev;\n\tstruct mii_bus *mii_bus;\n\tstruct clk *core_clk;\n};\n\nstruct iproc_pcie;\n\nstruct iproc_msi_grp;\n\nstruct iproc_msi {\n\tstruct iproc_pcie *pcie;\n\tconst u16 (*reg_offsets)[8];\n\tstruct iproc_msi_grp *grps;\n\tint nr_irqs;\n\tint nr_cpus;\n\tbool has_inten_reg;\n\tlong unsigned int *bitmap;\n\tstruct mutex bitmap_lock;\n\tunsigned int nr_msi_vecs;\n\tstruct irq_domain *inner_domain;\n\tunsigned int nr_eq_region;\n\tunsigned int nr_msi_region;\n\tvoid *eq_cpu;\n\tdma_addr_t eq_dma;\n\tphys_addr_t msi_addr;\n};\n\nstruct iproc_msi_grp {\n\tstruct iproc_msi *msi;\n\tint gic_irq;\n\tunsigned int eq;\n};\n\nstruct iproc_pcie_ob {\n\tresource_size_t axi_offset;\n\tunsigned int nr_windows;\n};\n\nstruct iproc_pcie_ib {\n\tunsigned int nr_regions;\n};\n\nstruct iproc_pcie_ob_map;\n\nstruct iproc_pcie_ib_map;\n\nstruct iproc_pcie {\n\tstruct device *dev;\n\tenum iproc_pcie_type type;\n\tu16 *reg_offsets;\n\tvoid *base;\n\tphys_addr_t base_addr;\n\tstruct resource mem;\n\tstruct phy *phy;\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tbool ep_is_internal;\n\tbool iproc_cfg_read;\n\tbool rej_unconfig_pf;\n\tbool has_apb_err_disable;\n\tbool fix_paxc_cap;\n\tbool need_ob_cfg;\n\tstruct iproc_pcie_ob ob;\n\tconst struct iproc_pcie_ob_map *ob_map;\n\tbool need_ib_cfg;\n\tstruct iproc_pcie_ib ib;\n\tconst struct iproc_pcie_ib_map *ib_map;\n\tbool need_msi_steer;\n\tstruct iproc_msi *msi;\n};\n\nstruct iproc_pcie_ib_map {\n\tenum iproc_pcie_ib_map_type type;\n\tunsigned int size_unit;\n\tresource_size_t region_sizes[9];\n\tunsigned int nr_sizes;\n\tunsigned int nr_windows;\n\tu16 imap_addr_offset;\n\tu16 imap_window_offset;\n};\n\nstruct iproc_pcie_ob_map {\n\tresource_size_t window_sizes[4];\n\tunsigned int nr_sizes;\n};\n\nstruct iproc_pll_ctrl;\n\nstruct iproc_pll_vco_param;\n\nstruct iproc_pll {\n\tvoid *status_base;\n\tvoid *control_base;\n\tvoid *pwr_base;\n\tvoid *asiu_base;\n\tconst struct iproc_pll_ctrl *ctrl;\n\tconst struct iproc_pll_vco_param *vco_param;\n\tunsigned int num_vco_entries;\n};\n\nstruct iproc_pll_aon_pwr_ctrl {\n\tunsigned int offset;\n\tunsigned int pwr_width;\n\tunsigned int pwr_shift;\n\tunsigned int iso_shift;\n};\n\nstruct iproc_pll_reset_ctrl {\n\tunsigned int offset;\n\tunsigned int reset_shift;\n\tunsigned int p_reset_shift;\n};\n\nstruct iproc_pll_dig_filter_ctrl {\n\tunsigned int offset;\n\tunsigned int ki_shift;\n\tunsigned int ki_width;\n\tunsigned int kp_shift;\n\tunsigned int kp_width;\n\tunsigned int ka_shift;\n\tunsigned int ka_width;\n};\n\nstruct iproc_pll_sw_ctrl {\n\tunsigned int offset;\n\tunsigned int shift;\n};\n\nstruct iproc_pll_vco_ctrl {\n\tunsigned int u_offset;\n\tunsigned int l_offset;\n};\n\nstruct iproc_pll_ctrl {\n\tlong unsigned int flags;\n\tstruct iproc_pll_aon_pwr_ctrl aon;\n\tstruct iproc_asiu_gate asiu;\n\tstruct iproc_pll_reset_ctrl reset;\n\tstruct iproc_pll_dig_filter_ctrl dig_filter;\n\tstruct iproc_pll_sw_ctrl sw_ctrl;\n\tstruct iproc_clk_reg_op ndiv_int;\n\tstruct iproc_clk_reg_op ndiv_frac;\n\tstruct iproc_clk_reg_op pdiv;\n\tstruct iproc_pll_vco_ctrl vco_ctrl;\n\tstruct iproc_clk_reg_op status;\n\tstruct iproc_clk_reg_op macro_mode;\n};\n\nstruct iproc_pll_vco_param {\n\tlong unsigned int rate;\n\tunsigned int ndiv_int;\n\tunsigned int ndiv_frac;\n\tunsigned int pdiv;\n};\n\nstruct iproc_pwmc {\n\tvoid *base;\n\tstruct clk *clk;\n};\n\nstruct iproc_rng200_dev {\n\tstruct hwrng rng;\n\tvoid *base;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct irq_bypass_producer;\n\nstruct irq_bypass_consumer {\n\tstruct eventfd_ctx *eventfd;\n\tstruct irq_bypass_producer *producer;\n\tint (*add_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tvoid (*del_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tvoid (*stop)(struct irq_bypass_consumer *);\n\tvoid (*start)(struct irq_bypass_consumer *);\n};\n\nstruct irq_bypass_producer {\n\tstruct eventfd_ctx *eventfd;\n\tstruct irq_bypass_consumer *consumer;\n\tint irq;\n\tint (*add_consumer)(struct irq_bypass_producer *, struct irq_bypass_consumer *);\n\tvoid (*del_consumer)(struct irq_bypass_producer *, struct irq_bypass_consumer *);\n\tvoid (*stop)(struct irq_bypass_producer *);\n\tvoid (*start)(struct irq_bypass_producer *);\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tunsigned int node;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n\tcpumask_var_t effective_affinity;\n\tunsigned int ipi_offset;\n};\n\nstruct meson_gpio_irq_controller;\n\nstruct irq_ctl_ops {\n\tvoid (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *, unsigned int, long unsigned int);\n\tvoid (*gpio_irq_init)(struct meson_gpio_irq_controller *);\n\tint (*gpio_irq_set_type)(struct meson_gpio_irq_controller *, unsigned int, u32 *);\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct hlist_node resend_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_generic_chip_devres {\n\tstruct irq_chip_generic *gc;\n\tu32 msk;\n\tunsigned int clr;\n\tunsigned int set;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_info {\n\tstruct list_head list;\n\tstruct list_head eoi_list;\n\tstruct rcu_work rwork;\n\tshort int refcnt;\n\tu8 spurious_cnt;\n\tu8 is_accounted;\n\tshort int type;\n\tu8 mask_reason;\n\tu8 is_active;\n\tunsigned int irq;\n\tevtchn_port_t evtchn;\n\tshort unsigned int cpu;\n\tshort unsigned int eoi_cpu;\n\tunsigned int irq_epoch;\n\tu64 eoi_time;\n\traw_spinlock_t lock;\n\tbool is_static;\n\tunion {\n\t\tshort unsigned int virq;\n\t\tenum ipi_vector ipi;\n\t\tstruct {\n\t\t\tshort unsigned int pirq;\n\t\t\tshort unsigned int gsi;\n\t\t\tunsigned char vector;\n\t\t\tunsigned char flags;\n\t\t\tuint16_t domid;\n\t\t} pirq;\n\t\tstruct xenbus_device *interdomain;\n\t} u;\n};\n\nstruct irq_info___2 {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\nstruct irq_ops {\n\tlong unsigned int flags;\n\tbool (*get_input_level)(int);\n};\n\nstruct irq_override_cmp {\n\tconst struct dmi_system_id *system;\n\tunsigned char irq;\n\tunsigned char triggering;\n\tunsigned char polarity;\n\tunsigned char shareable;\n\tbool override;\n};\n\nstruct irq_top_t {\n\tint hwirq_base;\n\tunsigned int num_int_regs;\n\tunsigned int en_reg;\n\tunsigned int en_reg_shift;\n\tunsigned int sta_reg;\n\tunsigned int sta_reg_shift;\n\tunsigned int top_offset;\n};\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irqc_priv;\n\nstruct irqc_irq {\n\tint hw_irq;\n\tint requested_irq;\n\tstruct irqc_priv *p;\n};\n\nstruct irqc_priv {\n\tvoid *iomem;\n\tvoid *cpu_int_base;\n\tstruct irqc_irq irq[32];\n\tunsigned int number_of_irqs;\n\tstruct device *dev;\n\tstruct irq_chip_generic *gc;\n\tstruct irq_domain *irq_domain;\n\tatomic_t wakeup_path;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqentry_state {\n\tunion {\n\t\tbool exit_rcu;\n\t\tbool lockdep;\n\t};\n};\n\ntypedef struct irqentry_state irqentry_state_t;\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct irqsteer_data {\n\tvoid *regs;\n\tstruct clk *ipg_clk;\n\tint irq[15];\n\tint irq_count;\n\traw_spinlock_t lock;\n\tint reg_num;\n\tint channel;\n\tstruct irq_domain *domain;\n\tu32 *saved_reg;\n\tstruct device *dev;\n};\n\nstruct irqtime {\n\tu64 total;\n\tu64 tick_delta;\n\tu64 irq_start_time;\n\tstruct u64_stats_sync sync;\n};\n\nstruct isp1760_memory_chunk {\n\tunsigned int start;\n\tunsigned int size;\n\tunsigned int free;\n};\n\nstruct isp1760_memory_layout;\n\nstruct isp1760_slotinfo;\n\nstruct isp1760_hcd {\n\tstruct usb_hcd *hcd;\n\tvoid *base;\n\tstruct regmap *regs;\n\tstruct regmap_field *fields[78];\n\tbool is_isp1763;\n\tconst struct isp1760_memory_layout *memory_layout;\n\tspinlock_t lock;\n\tstruct isp1760_slotinfo *atl_slots;\n\tint atl_done_map;\n\tstruct isp1760_slotinfo *int_slots;\n\tint int_done_map;\n\tstruct isp1760_memory_chunk memory_pool[56];\n\tstruct list_head qh_list[3];\n\tunsigned int periodic_size;\n\tunsigned int i_thresh;\n\tlong unsigned int reset_done;\n\tlong unsigned int next_statechange;\n};\n\nstruct isp1760_udc;\n\nstruct isp1760_ep {\n\tstruct isp1760_udc *udc;\n\tstruct usb_ep ep;\n\tstruct list_head queue;\n\tunsigned int addr;\n\tunsigned int maxpacket;\n\tchar name[7];\n\tconst struct usb_endpoint_descriptor *desc;\n\tbool rx_pending;\n\tbool halted;\n\tbool wedged;\n};\n\nstruct isp1760_device;\n\nstruct isp1760_udc {\n\tstruct isp1760_device *isp;\n\tint irq;\n\tchar *irqname;\n\tstruct regmap *regs;\n\tstruct regmap_field *fields[40];\n\tstruct usb_gadget_driver *driver;\n\tstruct usb_gadget gadget;\n\tspinlock_t lock;\n\tstruct timer_list vbus_timer;\n\tstruct isp1760_ep ep[15];\n\tenum isp1760_ctrl_state ep0_state;\n\tu8 ep0_dir;\n\tu16 ep0_length;\n\tbool connected;\n\tbool is_isp1763;\n\tunsigned int devstatus;\n};\n\nstruct isp1760_device {\n\tstruct device *dev;\n\tunsigned int devflags;\n\tstruct gpio_desc *rst_gpio;\n\tstruct isp1760_hcd hcd;\n\tstruct isp1760_udc udc;\n};\n\nstruct isp1760_memory_layout {\n\tunsigned int blocks[3];\n\tunsigned int blocks_size[3];\n\tunsigned int slot_num;\n\tunsigned int payload_blocks;\n\tunsigned int payload_area_size;\n};\n\nstruct isp1760_qh {\n\tstruct list_head qh_list;\n\tstruct list_head qtd_list;\n\tu32 toggle;\n\tu32 ping;\n\tint slot;\n\tint tt_buffer_dirty;\n};\n\nstruct isp1760_qtd {\n\tu8 packet_type;\n\tvoid *data_buffer;\n\tu32 payload_addr;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n\tsize_t actual_length;\n\tu32 status;\n};\n\nstruct isp1760_request {\n\tstruct usb_request req;\n\tstruct list_head queue;\n\tstruct isp1760_ep *ep;\n\tunsigned int packet_size;\n};\n\nstruct isp1760_slotinfo {\n\tstruct isp1760_qh *qh;\n\tstruct isp1760_qtd *qtd;\n\tlong unsigned int timestamp;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct its_baser {\n\tvoid *base;\n\tu64 val;\n\tu32 order;\n\tu32 psz;\n};\n\nstruct its_cmd_block {\n\tunion {\n\t\tu64 raw_cmd[4];\n\t\t__le64 raw_cmd_le[4];\n\t};\n};\n\nstruct its_device;\n\nstruct its_collection;\n\nstruct its_cmd_desc {\n\tunion {\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_inv_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_clear_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_int_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tint valid;\n\t\t} its_mapd_cmd;\n\t\tstruct {\n\t\t\tstruct its_collection *col;\n\t\t\tint valid;\n\t\t} its_mapc_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 phys_id;\n\t\t\tu32 event_id;\n\t\t} its_mapti_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tstruct its_collection *col;\n\t\t\tu32 event_id;\n\t\t} its_movi_cmd;\n\t\tstruct {\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t} its_discard_cmd;\n\t\tstruct {\n\t\t\tstruct its_collection *col;\n\t\t} its_invall_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t} its_vinvall_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_collection *col;\n\t\t\tbool valid;\n\t\t} its_vmapp_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_device *dev;\n\t\t\tu32 virt_id;\n\t\t\tu32 event_id;\n\t\t\tbool db_enabled;\n\t\t} its_vmapti_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_device *dev;\n\t\t\tu32 event_id;\n\t\t\tbool db_enabled;\n\t\t} its_vmovi_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tstruct its_collection *col;\n\t\t\tu16 seq_num;\n\t\t\tu16 its_list;\n\t\t} its_vmovp_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t} its_invdb_cmd;\n\t\tstruct {\n\t\t\tstruct its_vpe *vpe;\n\t\t\tu8 sgi;\n\t\t\tu8 priority;\n\t\t\tbool enable;\n\t\t\tbool group;\n\t\t\tbool clear;\n\t\t} its_vsgi_cmd;\n\t};\n};\n\nstruct its_cmd_info {\n\tenum its_vcpu_info_cmd_type cmd_type;\n\tunion {\n\t\tstruct its_vlpi_map *map;\n\t\tu8 config;\n\t\tbool req_db;\n\t\tstruct {\n\t\t\tbool g0en;\n\t\t\tbool g1en;\n\t\t};\n\t\tstruct {\n\t\t\tu8 priority;\n\t\t\tbool group;\n\t\t};\n\t};\n};\n\nstruct its_collection___2 {\n\tstruct list_head coll_list;\n\tu32 collection_id;\n\tu32 target_addr;\n};\n\nstruct its_collection {\n\tu64 target_address;\n\tu16 col_id;\n};\n\nstruct its_device___2 {\n\tstruct list_head dev_list;\n\tstruct list_head itt_head;\n\tu32 num_eventid_bits;\n\tgpa_t itt_addr;\n\tu32 device_id;\n};\n\nstruct its_node;\n\nstruct its_device {\n\tstruct list_head entry;\n\tstruct its_node *its;\n\tstruct event_lpi_map event_map;\n\tvoid *itt;\n\tu32 itt_sz;\n\tu32 nr_ites;\n\tu32 device_id;\n\tbool shared;\n};\n\nstruct its_ite {\n\tstruct list_head ite_list;\n\tstruct vgic_irq *irq;\n\tstruct its_collection___2 *collection;\n\tu32 event_id;\n};\n\nstruct its_node {\n\traw_spinlock_t lock;\n\tstruct mutex dev_alloc_lock;\n\tstruct list_head entry;\n\tvoid *base;\n\tvoid *sgir_base;\n\tphys_addr_t phys_base;\n\tstruct its_cmd_block *cmd_base;\n\tstruct its_cmd_block *cmd_write;\n\tstruct its_baser tables[8];\n\tstruct its_collection *collections;\n\tstruct fwnode_handle *fwnode_handle;\n\tu64 (*get_msi_base)(struct its_device *);\n\tu64 typer;\n\tu64 cbaser_save;\n\tu32 ctlr_save;\n\tu32 mpidr;\n\tstruct list_head its_device_list;\n\tu64 flags;\n\tlong unsigned int list_nr;\n\tint numa_node;\n\tunsigned int msi_domain_flags;\n\tu32 pre_its_base;\n\tint vlpi_redist_offset;\n};\n\nstruct its_srat_map {\n\tu32 numa_node;\n\tu32 its_id;\n};\n\nstruct its_vlpi_map {\n\tstruct its_vm *vm;\n\tstruct its_vpe *vpe;\n\tu32 vintid;\n\tu8 properties;\n\tbool db_enabled;\n};\n\nstruct its_vpe {\n\tstruct page *vpt_page;\n\tstruct its_vm *its_vm;\n\tatomic_t vlpi_count;\n\tint irq;\n\tirq_hw_number_t vpe_db_lpi;\n\tbool resident;\n\tbool ready;\n\tunion {\n\t\tstruct {\n\t\t\tint vpe_proxy_event;\n\t\t\tbool idai;\n\t\t};\n\t\tstruct {\n\t\t\tstruct fwnode_handle *fwnode;\n\t\t\tstruct irq_domain *sgi_domain;\n\t\t\tstruct {\n\t\t\t\tu8 priority;\n\t\t\t\tbool enabled;\n\t\t\t\tbool group;\n\t\t\t} sgi_config[16];\n\t\t};\n\t};\n\tatomic_t vmapp_count;\n\traw_spinlock_t vpe_lock;\n\tu16 col_idx;\n\tu16 vpe_id;\n\tbool pending_last;\n};\n\nstruct iw_node_attr {\n\tstruct kobj_attribute kobj_attr;\n\tint nid;\n};\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_s journal_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong long unsigned int blocknr;\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct transaction_stats_s;\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct jedec_ecc_info {\n\tu8 ecc_bits;\n\tu8 codeword_size;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 reserved[2];\n};\n\nstruct rand_data;\n\nstruct shash_desc;\n\nstruct jitterentropy {\n\tspinlock_t jent_lock;\n\tstruct rand_data *entropy_collector;\n\tstruct crypto_shash *tfm;\n\tstruct shash_desc *sdesc;\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\twait_queue_head_t j_fc_wait;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tstruct shrinker *j_shrinker;\n\tstruct percpu_counter j_checkpoint_jh_count;\n\ttransaction_t *j_shrink_transaction;\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tlong unsigned int j_fc_first;\n\tlong unsigned int j_fc_off;\n\tlong unsigned int j_fc_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\terrseq_t j_fs_dev_wb_err;\n\tunsigned int j_total_len;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tint j_transaction_overhead_buffers;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tstruct buffer_head **j_fc_wbuf;\n\tint j_wbufsize;\n\tint j_fc_wbufsize;\n\tpid_t j_last_sync_writer;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tint (*j_submit_inode_data_buffers)(struct jbd2_inode *);\n\tint (*j_finish_inode_data_buffers)(struct jbd2_inode *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\t__u32 j_csum_seed;\n\tstruct lock_class_key jbd2_trans_commit_key;\n\tvoid (*j_fc_cleanup_callback)(struct journal_s *, int, tid_t);\n\tint (*j_fc_replay_callback)(struct journal_s *, struct buffer_head *, enum passtype, int, tid_t);\n\tint (*j_bmap)(struct journal_s *, sector_t *);\n};\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__be32 s_num_fc_blks;\n\t__be32 s_head;\n\t__u32 s_padding[40];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nstruct jump_entry {\n\ts32 code;\n\ts32 target;\n\tlong int key;\n};\n\nstruct k3_cppi_desc_pool {\n\tstruct device *dev;\n\tdma_addr_t dma_addr;\n\tvoid *cpumem;\n\tsize_t desc_size;\n\tsize_t mem_size;\n\tsize_t num_desc;\n\tstruct gen_pool *gen_pool;\n\tvoid **desc_infos;\n};\n\nstruct k3_desc_hw {\n\tu32 lli;\n\tu32 reserved[3];\n\tu32 count;\n\tu32 saddr;\n\tu32 daddr;\n\tu32 config;\n};\n\nstruct k3_dma_phy;\n\nstruct k3_dma_chan {\n\tu32 ccfg;\n\tstruct virt_dma_chan vc;\n\tstruct k3_dma_phy *phy;\n\tstruct list_head node;\n\tdma_addr_t dev_addr;\n\tenum dma_status status;\n\tbool cyclic;\n\tstruct dma_slave_config slave_config;\n};\n\nstruct k3_dma_desc_sw {\n\tstruct virt_dma_desc vd;\n\tdma_addr_t desc_hw_lli;\n\tsize_t desc_num;\n\tsize_t size;\n\tstruct k3_desc_hw *desc_hw;\n};\n\nstruct k3_dma_dev {\n\tstruct dma_device slave;\n\tvoid *base;\n\tstruct tasklet_struct task;\n\tspinlock_t lock;\n\tstruct list_head chan_pending;\n\tstruct k3_dma_phy *phy;\n\tstruct k3_dma_chan *chans;\n\tstruct clk *clk;\n\tstruct dma_pool *pool;\n\tu32 dma_channels;\n\tu32 dma_requests;\n\tu32 dma_channel_mask;\n\tunsigned int irq;\n};\n\nstruct k3_dma_phy {\n\tu32 idx;\n\tvoid *base;\n\tstruct k3_dma_chan *vchan;\n\tstruct k3_dma_desc_sw *ds_run;\n\tstruct k3_dma_desc_sw *ds_done;\n};\n\nstruct k3_event_route_data {\n\tvoid *priv;\n\tint (*set_event)(void *, u32);\n};\n\nstruct k3_mdio_soc_data {\n\tbool manual_mode;\n};\n\nstruct k3_priv {\n\tint ctrl_id;\n\tu32 cur_speed;\n\tstruct regmap *reg;\n};\n\nstruct k3_ring_state {\n\tu32 free;\n\tu32 occ;\n\tu32 windex;\n\tu32 rindex;\n\tu32 tdown_complete: 1;\n};\n\nstruct k3_ring_rt_regs;\n\nstruct k3_ring_fifo_regs;\n\nstruct k3_ringacc_proxy_target_regs;\n\nstruct k3_ring_ops;\n\nstruct k3_ringacc;\n\nstruct k3_ring {\n\tstruct k3_ring_rt_regs *rt;\n\tstruct k3_ring_fifo_regs *fifos;\n\tstruct k3_ringacc_proxy_target_regs *proxy;\n\tdma_addr_t ring_mem_dma;\n\tvoid *ring_mem_virt;\n\tconst struct k3_ring_ops *ops;\n\tu32 size;\n\tenum k3_ring_size elm_size;\n\tenum k3_ring_mode mode;\n\tu32 flags;\n\tstruct k3_ring_state state;\n\tu32 ring_id;\n\tstruct k3_ringacc *parent;\n\tu32 use_count;\n\tint proxy_id;\n\tstruct device *dma_dev;\n\tu32 asel;\n};\n\nstruct k3_ring_cfg {\n\tu32 size;\n\tenum k3_ring_size elm_size;\n\tenum k3_ring_mode mode;\n\tu32 flags;\n\tstruct device *dma_dev;\n\tu32 asel;\n};\n\nstruct k3_ring_fifo_regs {\n\tu32 head_data[128];\n\tu32 tail_data[128];\n\tu32 peek_head_data[128];\n\tu32 peek_tail_data[128];\n};\n\nstruct k3_ring_ops {\n\tint (*push_tail)(struct k3_ring *, void *);\n\tint (*push_head)(struct k3_ring *, void *);\n\tint (*pop_tail)(struct k3_ring *, void *);\n\tint (*pop_head)(struct k3_ring *, void *);\n};\n\nstruct k3_ring_rt_regs {\n\tu32 resv_16[4];\n\tu32 db;\n\tu32 resv_4[1];\n\tu32 occ;\n\tu32 indx;\n\tu32 hwocc;\n\tu32 hwindx;\n};\n\nstruct k3_ringacc_proxy_gcfg_regs;\n\nstruct ti_sci_resource;\n\nstruct ti_sci_handle;\n\nstruct ti_sci_rm_ringacc_ops;\n\nstruct k3_ringacc_ops;\n\nstruct k3_ringacc {\n\tstruct device *dev;\n\tstruct k3_ringacc_proxy_gcfg_regs *proxy_gcfg;\n\tvoid *proxy_target_base;\n\tu32 num_rings;\n\tlong unsigned int *rings_inuse;\n\tstruct ti_sci_resource *rm_gp_range;\n\tbool dma_ring_reset_quirk;\n\tu32 num_proxies;\n\tlong unsigned int *proxy_inuse;\n\tstruct k3_ring *rings;\n\tstruct list_head list;\n\tstruct mutex req_lock;\n\tconst struct ti_sci_handle *tisci;\n\tconst struct ti_sci_rm_ringacc_ops *tisci_ring_ops;\n\tu32 tisci_dev_id;\n\tconst struct k3_ringacc_ops *ops;\n\tbool dma_rings;\n};\n\nstruct k3_ringacc_init_data {\n\tconst struct ti_sci_handle *tisci;\n\tu32 tisci_dev_id;\n\tu32 num_rings;\n};\n\nstruct k3_ringacc_ops {\n\tint (*init)(struct platform_device *, struct k3_ringacc *);\n};\n\nstruct k3_ringacc_proxy_gcfg_regs {\n\tu32 revision;\n\tu32 config;\n};\n\nstruct k3_ringacc_proxy_target_regs {\n\tu32 control;\n\tu32 status;\n\tu8 resv_512[504];\n\tu32 data[128];\n};\n\nstruct k3_ringacc_soc_data {\n\tunsigned int dma_ring_reset_quirk: 1;\n};\n\nstruct k3_soc_id {\n\tunsigned int id;\n\tconst char *family_name;\n};\n\nstruct udma_dev;\n\nstruct udma_tisci_rm;\n\nstruct psil_endpoint_config;\n\nstruct k3_udma_glue_common {\n\tstruct device *dev;\n\tstruct device chan_dev;\n\tstruct udma_dev *udmax;\n\tconst struct udma_tisci_rm *tisci_rm;\n\tstruct k3_ringacc *ringacc;\n\tu32 src_thread;\n\tu32 dst_thread;\n\tu32 hdesc_size;\n\tbool epib;\n\tu32 psdata_size;\n\tu32 swdata_size;\n\tu32 atype_asel;\n\tstruct psil_endpoint_config *ep_config;\n};\n\nstruct udma_rchan;\n\nstruct k3_udma_glue_rx_flow;\n\nstruct k3_udma_glue_rx_channel {\n\tstruct k3_udma_glue_common common;\n\tstruct udma_rchan *udma_rchanx;\n\tint udma_rchan_id;\n\tbool remote;\n\tbool psil_paired;\n\tu32 swdata_size;\n\tint flow_id_base;\n\tstruct k3_udma_glue_rx_flow *flows;\n\tu32 flow_num;\n\tu32 flows_ready;\n\tbool single_fdq;\n};\n\nstruct k3_udma_glue_rx_flow_cfg;\n\nstruct k3_udma_glue_rx_channel_cfg {\n\tu32 swdata_size;\n\tint flow_id_base;\n\tint flow_id_num;\n\tbool flow_id_use_rxchan_id;\n\tbool remote;\n\tstruct k3_udma_glue_rx_flow_cfg *def_flow_cfg;\n};\n\nstruct udma_rflow;\n\nstruct k3_udma_glue_rx_flow {\n\tstruct udma_rflow *udma_rflow;\n\tint udma_rflow_id;\n\tstruct k3_ring *ringrx;\n\tstruct k3_ring *ringrxfdq;\n\tint virq;\n};\n\nstruct k3_udma_glue_rx_flow_cfg {\n\tstruct k3_ring_cfg rx_cfg;\n\tstruct k3_ring_cfg rxfdq_cfg;\n\tint ring_rxq_id;\n\tint ring_rxfdq0_id;\n\tbool rx_error_handling;\n\tint src_tag_lo_sel;\n};\n\nstruct udma_tchan;\n\nstruct k3_udma_glue_tx_channel {\n\tstruct k3_udma_glue_common common;\n\tstruct udma_tchan *udma_tchanx;\n\tint udma_tchan_id;\n\tstruct k3_ring *ringtx;\n\tstruct k3_ring *ringtxcq;\n\tbool psil_paired;\n\tint virq;\n\tatomic_t free_pkts;\n\tbool tx_pause_on_err;\n\tbool tx_filt_einfo;\n\tbool tx_filt_pswords;\n\tbool tx_supr_tdpkt;\n\tint udma_tflow_id;\n};\n\nstruct k3_udma_glue_tx_channel_cfg {\n\tstruct k3_ring_cfg tx_cfg;\n\tstruct k3_ring_cfg txcq_cfg;\n\tbool tx_pause_on_err;\n\tbool tx_filt_einfo;\n\tbool tx_filt_pswords;\n\tbool tx_supr_tdpkt;\n\tu32 swdata_size;\n};\n\nstruct k3dma_soc_data {\n\tlong unsigned int flags;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\ntypedef void __restorefn_t(void);\n\ntypedef __restorefn_t *__sigrestore_t;\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[56];\n\tint exported;\n\tint show_value;\n};\n\nstruct karatsuba_ctx {\n\tstruct karatsuba_ctx *next;\n\tmpi_ptr_t tspace;\n\tmpi_size_t tspace_size;\n\tmpi_ptr_t tp;\n\tmpi_size_t tp_size;\n};\n\nstruct led_trigger {\n\tconst char *name;\n\tint (*activate)(struct led_classdev *);\n\tvoid (*deactivate)(struct led_classdev *);\n\tenum led_brightness brightness;\n\tstruct led_hw_trigger_type *trigger_type;\n\tspinlock_t leddev_list_lock;\n\tstruct list_head led_cdevs;\n\tstruct list_head next_trig;\n\tconst struct attribute_group **groups;\n};\n\nstruct kbd_led_trigger {\n\tstruct led_trigger trigger;\n\tunsigned int mask;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tint: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcmp_epoll_slot {\n\t__u32 efd;\n\t__u32 tfd;\n\t__u32 toff;\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[10];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tint value_offset;\n\tint name_offset;\n\tint namespace_offset;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[1024];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct vm_operations_struct;\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct kimage;\n\nstruct kexec_buf {\n\tstruct kimage *image;\n\tvoid *buffer;\n\tlong unsigned int bufsz;\n\tlong unsigned int mem;\n\tlong unsigned int memsz;\n\tlong unsigned int buf_align;\n\tlong unsigned int buf_min;\n\tlong unsigned int buf_max;\n\tstruct page *cma;\n\tbool top_down;\n\tbool random;\n};\n\ntypedef int kexec_probe_t(const char *, long unsigned int);\n\ntypedef void *kexec_load_t(struct kimage *, char *, long unsigned int, char *, long unsigned int, char *, long unsigned int);\n\ntypedef int kexec_cleanup_t(void *);\n\nstruct kexec_file_ops {\n\tkexec_probe_t *probe;\n\tkexec_load_t *load;\n\tkexec_cleanup_t *cleanup;\n};\n\nstruct kexec_link_entry {\n\tconst char *target;\n\tconst char *name;\n};\n\nstruct kexec_load_limit {\n\tstruct mutex mutex;\n\tint limit;\n};\n\nstruct kexec_segment {\n\tunion {\n\t\tvoid *buf;\n\t\tvoid *kbuf;\n\t};\n\tsize_t bufsz;\n\tlong unsigned int mem;\n\tsize_t memsz;\n};\n\nstruct kexec_sha_region {\n\tlong unsigned int start;\n\tlong unsigned int len;\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[6];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_info {\n\tu8 key_type;\n\tu8 key_length;\n\tenum HCLGE_FD_KEY_OPT key_opt;\n\tint offset;\n\tint moffset;\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\ttime64_t now;\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct mm_slot;\n\nstruct khugepaged_scan {\n\tstruct list_head mm_head;\n\tstruct mm_slot *mm_slot;\n\tlong unsigned int address;\n};\n\nstruct kimage_arch {\n\tvoid *dtb;\n\tphys_addr_t dtb_mem;\n\tphys_addr_t kern_reloc;\n\tphys_addr_t el2_vectors;\n\tphys_addr_t ttbr0;\n\tphys_addr_t ttbr1;\n\tphys_addr_t zero_page;\n\tlong unsigned int phys_offset;\n\tlong unsigned int t0sz;\n};\n\nstruct purgatory_info {\n\tconst Elf64_Ehdr *ehdr;\n\tElf64_Shdr *sechdrs;\n\tvoid *purgatory_buf;\n};\n\nstruct kimage {\n\tkimage_entry_t head;\n\tkimage_entry_t *entry;\n\tkimage_entry_t *last_entry;\n\tlong unsigned int start;\n\tstruct page *control_code_page;\n\tstruct page *swap_page;\n\tvoid *vmcoreinfo_data_copy;\n\tlong unsigned int nr_segments;\n\tstruct kexec_segment segment[16];\n\tstruct page *segment_cma[16];\n\tstruct list_head control_pages;\n\tstruct list_head dest_pages;\n\tstruct list_head unusable_pages;\n\tlong unsigned int control_page;\n\tunsigned int type: 1;\n\tunsigned int preserve_context: 1;\n\tunsigned int file_mode: 1;\n\tunsigned int no_cma: 1;\n\tstruct kimage_arch arch;\n\tvoid *kernel_buf;\n\tlong unsigned int kernel_buf_len;\n\tvoid *initrd_buf;\n\tlong unsigned int initrd_buf_len;\n\tchar *cmdline_buf;\n\tlong unsigned int cmdline_buf_len;\n\tconst struct kexec_file_ops *fops;\n\tvoid *image_loader_data;\n\tstruct purgatory_info purgatory_info;\n\tbool force_dtb;\n\tstruct {\n\t\tstruct kexec_segment *scratch;\n\t\tphys_addr_t fdt;\n\t} kho;\n\tvoid *elf_headers;\n\tlong unsigned int elf_headers_sz;\n\tlong unsigned int elf_load_addr;\n\tlong unsigned int dm_crypt_keys_addr;\n\tlong unsigned int dm_crypt_keys_sz;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct kirin_pcie {\n\tenum pcie_kirin_phy_type type;\n\tstruct dw_pcie *pci;\n\tstruct regmap *apb;\n\tstruct phy *phy;\n\tvoid *phy_priv;\n\tstruct gpio_desc *id_dwc_perst_gpio;\n\tint num_slots;\n\tstruct gpio_desc *id_reset_gpio[3];\n\tconst char *reset_names[3];\n\tint n_gpio_clkreq;\n\tstruct gpio_desc *id_clkreq_gpio[3];\n\tconst char *clkreq_names[3];\n};\n\nstruct kirin_pcie_data {\n\tenum pcie_kirin_phy_type phy_type;\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[4];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {};\n\ntypedef struct kmem_cache *kmem_buckets[14];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tunsigned int remote_node_defrag_ratio;\n\tstruct kmem_cache_node *node[16];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kpp_request;\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tstruct crypto_alg base;\n};\n\nstruct kpp_instance {\n\tvoid (*free)(struct kpp_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[48];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct kpp_alg alg;\n\t};\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct kprobe;\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct krb5_ctx {\n\tint initiate;\n\tu32 enctype;\n\tu32 flags;\n\tconst struct gss_krb5_enctype *gk5e;\n\tstruct crypto_sync_skcipher *enc;\n\tstruct crypto_sync_skcipher *seq;\n\tstruct crypto_sync_skcipher *acceptor_enc;\n\tstruct crypto_sync_skcipher *initiator_enc;\n\tstruct crypto_sync_skcipher *acceptor_enc_aux;\n\tstruct crypto_sync_skcipher *initiator_enc_aux;\n\tstruct crypto_ahash *acceptor_sign;\n\tstruct crypto_ahash *initiator_sign;\n\tstruct crypto_ahash *initiator_integ;\n\tstruct crypto_ahash *acceptor_integ;\n\tu8 Ksess[32];\n\tu8 cksum[32];\n\tatomic_t seq_send;\n\tatomic64_t seq_send64;\n\ttime64_t endtime;\n\tstruct xdr_netobj mech_used;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct mm_slot {\n\tstruct hlist_node hash;\n\tstruct list_head mm_node;\n\tstruct mm_struct *mm;\n};\n\nstruct ksm_rmap_item;\n\nstruct ksm_mm_slot {\n\tstruct mm_slot slot;\n\tstruct ksm_rmap_item *rmap_list;\n};\n\nstruct ksm_next_page_arg {\n\tstruct folio *folio;\n\tstruct page *page;\n\tlong unsigned int addr;\n};\n\nstruct ksm_stable_node;\n\nstruct ksm_rmap_item {\n\tstruct ksm_rmap_item *rmap_list;\n\tunion {\n\t\tstruct anon_vma *anon_vma;\n\t\tint nid;\n\t};\n\tstruct mm_struct *mm;\n\tlong unsigned int address;\n\tunsigned int oldchecksum;\n\trmap_age_t age;\n\trmap_age_t remaining_skips;\n\tunion {\n\t\tstruct rb_node node;\n\t\tstruct {\n\t\t\tstruct ksm_stable_node *head;\n\t\t\tstruct hlist_node hlist;\n\t\t};\n\t};\n};\n\nstruct ksm_scan {\n\tstruct ksm_mm_slot *mm_slot;\n\tlong unsigned int address;\n\tstruct ksm_rmap_item **rmap_list;\n\tlong unsigned int seqnr;\n};\n\nstruct ksm_stable_node {\n\tunion {\n\t\tstruct rb_node node;\n\t\tstruct {\n\t\t\tstruct list_head *head;\n\t\t\tstruct {\n\t\t\t\tstruct hlist_node hlist_dup;\n\t\t\t\tstruct list_head list;\n\t\t\t};\n\t\t};\n\t};\n\tstruct hlist_head hlist;\n\tunion {\n\t\tlong unsigned int kpfn;\n\t\tlong unsigned int chain_prune_time;\n\t};\n\tint rmap_hlist_len;\n\tint nid;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ksz9477_errata_write {\n\tu8 dev_addr;\n\tu8 reg_addr;\n\tu16 val;\n};\n\nstruct kszphy_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct kszphy_phy_stats {\n\tu64 rx_err_pkt_cnt;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct kszphy_ptp_priv {\n\tstruct mii_timestamper mii_ts;\n\tstruct phy_device *phydev;\n\tstruct sk_buff_head tx_queue;\n\tstruct sk_buff_head rx_queue;\n\tstruct list_head rx_ts_list;\n\tspinlock_t rx_ts_lock;\n\tint hwts_tx_type;\n\tenum hwtstamp_rx_filters rx_filter;\n\tint layer;\n\tint version;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct mutex ptp_lock;\n\tstruct ptp_pin_desc *pin_config;\n\ts64 seconds;\n\tspinlock_t seconds_lock;\n};\n\nstruct kszphy_type;\n\nstruct kszphy_priv {\n\tstruct kszphy_ptp_priv ptp_priv;\n\tconst struct kszphy_type *type;\n\tstruct clk *clk;\n\tint led_mode;\n\tu16 vct_ctrl1000;\n\tbool rmii_ref_clk_sel;\n\tbool rmii_ref_clk_sel_val;\n\tbool clk_enable;\n\tbool is_ptp_available;\n\tu64 stats[2];\n\tstruct kszphy_phy_stats phy_stats;\n};\n\nstruct kszphy_type {\n\tu32 led_mode_reg;\n\tu16 interrupt_level_mask;\n\tu16 cable_diag_reg;\n\tlong unsigned int pair_mask;\n\tu16 disable_dll_tx_bit;\n\tu16 disable_dll_rx_bit;\n\tu16 disable_dll_mask;\n\tbool has_broadcast_disable;\n\tbool has_nand_tree_disable;\n\tbool has_rmii_ref_clk_sel;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int);\n\nstruct kunwind_consume_entry_data {\n\tstack_trace_consume_fn consume_entry;\n\tvoid *cookie;\n};\n\nstruct stack_info {\n\tlong unsigned int low;\n\tlong unsigned int high;\n};\n\nstruct unwind_state {\n\tlong unsigned int fp;\n\tlong unsigned int pc;\n\tstruct stack_info stack;\n\tstruct stack_info *stacks;\n\tint nr_stacks;\n};\n\nunion unwind_flags {\n\tlong unsigned int all;\n\tstruct {\n\t\tlong unsigned int fgraph: 1;\n\t\tlong unsigned int kretprobe: 1;\n\t};\n};\n\nstruct kunwind_state {\n\tstruct unwind_state common;\n\tstruct task_struct *task;\n\tint graph_idx;\n\tenum kunwind_source source;\n\tunion unwind_flags flags;\n\tstruct pt_regs *regs;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kvm_memslots {\n\tu64 generation;\n\tatomic_long_t last_used_slot;\n\tstruct rb_root_cached hva_tree;\n\tstruct rb_root gfn_tree;\n\tstruct hlist_head id_hash[128];\n\tint node_idx;\n};\n\nstruct kvm_vm_stat_generic {\n\tu64 remote_tlb_flush;\n\tu64 remote_tlb_flush_requests;\n};\n\nstruct kvm_vm_stat {\n\tstruct kvm_vm_stat_generic generic;\n};\n\nstruct kvm_io_bus;\n\nstruct kvm_coalesced_mmio_ring;\n\nstruct kvm_irq_routing_table;\n\nstruct kvm_stat_data;\n\nstruct kvm {\n\trwlock_t mmu_lock;\n\tstruct mutex slots_lock;\n\tstruct mutex slots_arch_lock;\n\tstruct mm_struct *mm;\n\tlong unsigned int nr_memslot_pages;\n\tstruct kvm_memslots __memslots[2];\n\tstruct kvm_memslots *memslots[1];\n\tstruct xarray vcpu_array;\n\tatomic_t nr_memslots_dirty_logging;\n\tspinlock_t mn_invalidate_lock;\n\tlong unsigned int mn_active_invalidate_count;\n\tstruct rcuwait mn_memslots_update_rcuwait;\n\tspinlock_t gpc_lock;\n\tstruct list_head gpc_list;\n\tatomic_t online_vcpus;\n\tint max_vcpus;\n\tint created_vcpus;\n\tint last_boosted_vcpu;\n\tstruct list_head vm_list;\n\tstruct mutex lock;\n\tstruct kvm_io_bus *buses[5];\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head items;\n\t\tstruct list_head resampler_list;\n\t\tstruct mutex resampler_lock;\n\t} irqfds;\n\tstruct list_head ioeventfds;\n\tstruct kvm_vm_stat stat;\n\tstruct kvm_arch arch;\n\trefcount_t users_count;\n\tstruct kvm_coalesced_mmio_ring *coalesced_mmio_ring;\n\tspinlock_t ring_lock;\n\tstruct list_head coalesced_zones;\n\tstruct mutex irq_lock;\n\tstruct kvm_irq_routing_table *irq_routing;\n\tstruct hlist_head irq_ack_notifier_list;\n\tstruct mmu_notifier mmu_notifier;\n\tlong unsigned int mmu_invalidate_seq;\n\tlong int mmu_invalidate_in_progress;\n\tgfn_t mmu_invalidate_range_start;\n\tgfn_t mmu_invalidate_range_end;\n\tstruct list_head devices;\n\tu64 manual_dirty_log_protect;\n\tstruct dentry *debugfs_dentry;\n\tstruct kvm_stat_data **debugfs_stat_data;\n\tstruct srcu_struct srcu;\n\tstruct srcu_struct irq_srcu;\n\tpid_t userspace_pid;\n\tbool override_halt_poll_ns;\n\tunsigned int max_halt_poll_ns;\n\tu32 dirty_ring_size;\n\tbool dirty_ring_with_bitmap;\n\tbool vm_bugged;\n\tbool vm_dead;\n\tchar stats_id[48];\n};\n\nstruct kvm_arch_memory_slot {};\n\nstruct kvm_arm_copy_mte_tags {\n\t__u64 guest_ipa;\n\t__u64 length;\n\tvoid *addr;\n\t__u64 flags;\n\t__u64 reserved[2];\n};\n\nstruct kvm_arm_counter_offset {\n\t__u64 counter_offset;\n\t__u64 reserved;\n};\n\nstruct kvm_arm_device_addr {\n\t__u64 id;\n\t__u64 addr;\n};\n\nstruct kvm_clear_dirty_log {\n\t__u32 slot;\n\t__u32 num_pages;\n\t__u64 first_page;\n\tunion {\n\t\tvoid *dirty_bitmap;\n\t\t__u64 padding2;\n\t};\n};\n\nstruct kvm_coalesced_mmio {\n\t__u64 phys_addr;\n\t__u32 len;\n\tunion {\n\t\t__u32 pad;\n\t\t__u32 pio;\n\t};\n\t__u8 data[8];\n};\n\nstruct kvm_coalesced_mmio_zone {\n\t__u64 addr;\n\t__u32 size;\n\tunion {\n\t\t__u32 pad;\n\t\t__u32 pio;\n\t};\n};\n\nstruct kvm_coalesced_mmio_dev {\n\tstruct list_head list;\n\tstruct kvm_io_device dev;\n\tstruct kvm *kvm;\n\tstruct kvm_coalesced_mmio_zone zone;\n};\n\nstruct kvm_coalesced_mmio_ring {\n\t__u32 first;\n\t__u32 last;\n\tstruct kvm_coalesced_mmio coalesced_mmio[0];\n};\n\nstruct user_fpsimd_state {\n\t__int128 unsigned vregs[32];\n\t__u32 fpsr;\n\t__u32 fpcr;\n\t__u32 __reserved[2];\n};\n\nstruct kvm_cpu_context {\n\tstruct user_pt_regs regs;\n\tu64 spsr_abt;\n\tu64 spsr_und;\n\tu64 spsr_irq;\n\tu64 spsr_fiq;\n\tstruct user_fpsimd_state fp_regs;\n\tu64 sys_regs[296];\n\tstruct kvm_vcpu *__hyp_running_vcpu;\n\tu64 *vncr_array;\n};\n\nstruct kvm_create_device {\n\t__u32 type;\n\t__u32 fd;\n\t__u32 flags;\n};\n\nstruct kvm_create_guest_memfd {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 reserved[6];\n};\n\nstruct kvm_debug_exit_arch {\n\t__u32 hsr;\n\t__u32 hsr_high;\n\t__u64 far;\n};\n\nstruct kvm_device_ops;\n\nstruct kvm_device {\n\tconst struct kvm_device_ops *ops;\n\tstruct kvm *kvm;\n\tvoid *private;\n\tstruct list_head vm_node;\n};\n\nstruct kvm_device_attr {\n\t__u32 flags;\n\t__u32 group;\n\t__u64 attr;\n\t__u64 addr;\n};\n\nstruct kvm_device_ops {\n\tconst char *name;\n\tint (*create)(struct kvm_device *, u32);\n\tvoid (*init)(struct kvm_device *);\n\tvoid (*destroy)(struct kvm_device *);\n\tvoid (*release)(struct kvm_device *);\n\tint (*set_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*get_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*has_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tlong int (*ioctl)(struct kvm_device *, unsigned int, long unsigned int);\n\tint (*mmap)(struct kvm_device *, struct vm_area_struct *);\n};\n\nstruct kvm_dirty_gfn {\n\t__u32 flags;\n\t__u32 slot;\n\t__u64 offset;\n};\n\nstruct kvm_dirty_log {\n\t__u32 slot;\n\t__u32 padding1;\n\tunion {\n\t\tvoid *dirty_bitmap;\n\t\t__u64 padding2;\n\t};\n};\n\nstruct kvm_dirty_ring {\n\tu32 dirty_index;\n\tu32 reset_index;\n\tu32 size;\n\tu32 soft_limit;\n\tstruct kvm_dirty_gfn *dirty_gfns;\n\tint index;\n};\n\nstruct kvm_enable_cap {\n\t__u32 cap;\n\t__u32 flags;\n\t__u64 args[4];\n\t__u8 pad[64];\n};\n\nstruct kvm_exception_table_entry {\n\tint insn;\n\tint fixup;\n};\n\nstruct kvm_exit_snp_req_certs {\n\t__u64 gpa;\n\t__u64 npages;\n\t__u64 ret;\n};\n\nstruct kvm_ffa_buffers {\n\thyp_spinlock_t lock;\n\tvoid *tx;\n\tvoid *rx;\n};\n\nstruct kvm_ffa_descriptor_buffer {\n\tvoid *buf;\n\tsize_t len;\n};\n\nstruct kvm_follow_pfn {\n\tconst struct kvm_memory_slot *slot;\n\tconst gfn_t gfn;\n\tlong unsigned int hva;\n\tunsigned int flags;\n\tbool pin;\n\tbool *map_writable;\n\tstruct page **refcounted_page;\n};\n\nstruct kvm_fpu {};\n\nunion kvm_mmu_notifier_arg {\n\tlong unsigned int attributes;\n};\n\nstruct kvm_gfn_range {\n\tstruct kvm_memory_slot *slot;\n\tgfn_t start;\n\tgfn_t end;\n\tunion kvm_mmu_notifier_arg arg;\n\tenum kvm_gfn_range_filter attr_filter;\n\tbool may_block;\n\tbool lockless;\n};\n\nstruct kvm_guest_debug_arch {\n\t__u64 dbg_bcr[16];\n\t__u64 dbg_bvr[16];\n\t__u64 dbg_wcr[16];\n\t__u64 dbg_wvr[16];\n};\n\nstruct kvm_guest_debug {\n\t__u32 control;\n\t__u32 pad;\n\tstruct kvm_guest_debug_arch arch;\n};\n\nstruct kvm_host_data {\n\tlong unsigned int flags;\n\tlong: 64;\n\tstruct kvm_cpu_context host_ctxt;\n\tstruct cpu_sve_state *sve_state;\n\tu64 fpmr;\n\tenum {\n\t\tFP_STATE_FREE = 0,\n\t\tFP_STATE_HOST_OWNED = 1,\n\t\tFP_STATE_GUEST_OWNED = 2,\n\t} fp_owner;\n\tstruct {\n\t\tstruct kvm_guest_debug_arch regs;\n\t\tu64 pmscr_el1;\n\t\tu64 trfcr_el1;\n\t\tu64 mdcr_el2;\n\t\tu64 brbcr_el1;\n\t} host_debug_state;\n\tu64 trfcr_while_in_guest;\n\tunsigned int nr_event_counters;\n\tunsigned int debug_brps;\n\tunsigned int debug_wrps;\n};\n\nstruct kvm_host_map {\n\tstruct page *pinned_page;\n\tstruct page *page;\n\tvoid *hva;\n\tkvm_pfn_t pfn;\n\tkvm_pfn_t gfn;\n\tbool writable;\n};\n\nstruct psci_0_1_function_ids {\n\tu32 cpu_suspend;\n\tu32 cpu_on;\n\tu32 cpu_off;\n\tu32 migrate;\n};\n\nstruct kvm_host_psci_config {\n\tu32 version;\n\tu32 smccc_version;\n\tstruct psci_0_1_function_ids function_ids_0_1;\n\tbool psci_0_1_cpu_suspend_implemented;\n\tbool psci_0_1_cpu_on_implemented;\n\tbool psci_0_1_cpu_off_implemented;\n\tbool psci_0_1_migrate_implemented;\n};\n\nstruct kvm_hv_sint {\n\tu32 vcpu;\n\tu32 sint;\n};\n\nstruct kvm_hyperv_exit {\n\t__u32 type;\n\t__u32 pad1;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 evt_page;\n\t\t\t__u64 msg_page;\n\t\t} synic;\n\t\tstruct {\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[2];\n\t\t} hcall;\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 status;\n\t\t\t__u64 send_page;\n\t\t\t__u64 recv_page;\n\t\t\t__u64 pending_page;\n\t\t} syndbg;\n\t} u;\n};\n\nstruct kvm_io_range {\n\tgpa_t addr;\n\tint len;\n\tstruct kvm_io_device *dev;\n};\n\nstruct kvm_io_bus {\n\tint dev_count;\n\tint ioeventfd_count;\n\tstruct callback_head rcu;\n\tstruct kvm_io_range range[0];\n};\n\nstruct kvm_io_device_ops {\n\tint (*read)(struct kvm_vcpu *, struct kvm_io_device *, gpa_t, int, void *);\n\tint (*write)(struct kvm_vcpu *, struct kvm_io_device *, gpa_t, int, const void *);\n\tvoid (*destructor)(struct kvm_io_device *);\n};\n\nstruct kvm_ioctl_cap_map {\n\tunsigned int ioctl;\n\tlong int ext;\n};\n\nstruct kvm_ioeventfd {\n\t__u64 datamatch;\n\t__u64 addr;\n\t__u32 len;\n\t__s32 fd;\n\t__u32 flags;\n\t__u8 pad[36];\n};\n\nstruct kvm_irq_ack_notifier {\n\tstruct hlist_node link;\n\tunsigned int gsi;\n\tvoid (*irq_acked)(struct kvm_irq_ack_notifier *);\n};\n\nstruct kvm_irq_level {\n\tunion {\n\t\t__u32 irq;\n\t\t__s32 status;\n\t};\n\t__u32 level;\n};\n\nstruct kvm_irq_routing_irqchip {\n\t__u32 irqchip;\n\t__u32 pin;\n};\n\nstruct kvm_irq_routing_msi {\n\t__u32 address_lo;\n\t__u32 address_hi;\n\t__u32 data;\n\tunion {\n\t\t__u32 pad;\n\t\t__u32 devid;\n\t};\n};\n\nstruct kvm_irq_routing_s390_adapter {\n\t__u64 ind_addr;\n\t__u64 summary_addr;\n\t__u64 ind_offset;\n\t__u32 summary_offset;\n\t__u32 adapter_id;\n};\n\nstruct kvm_irq_routing_hv_sint {\n\t__u32 vcpu;\n\t__u32 sint;\n};\n\nstruct kvm_irq_routing_xen_evtchn {\n\t__u32 port;\n\t__u32 vcpu;\n\t__u32 priority;\n};\n\nstruct kvm_irq_routing_entry {\n\t__u32 gsi;\n\t__u32 type;\n\t__u32 flags;\n\t__u32 pad;\n\tunion {\n\t\tstruct kvm_irq_routing_irqchip irqchip;\n\t\tstruct kvm_irq_routing_msi msi;\n\t\tstruct kvm_irq_routing_s390_adapter adapter;\n\t\tstruct kvm_irq_routing_hv_sint hv_sint;\n\t\tstruct kvm_irq_routing_xen_evtchn xen_evtchn;\n\t\t__u32 pad[8];\n\t} u;\n};\n\nstruct kvm_irq_routing {\n\t__u32 nr;\n\t__u32 flags;\n\tstruct kvm_irq_routing_entry entries[0];\n};\n\nstruct kvm_irq_routing_table {\n\tint chip[988];\n\tu32 nr_rt_entries;\n\tstruct hlist_head map[0];\n};\n\nstruct kvm_irqfd {\n\t__u32 fd;\n\t__u32 gsi;\n\t__u32 flags;\n\t__u32 resamplefd;\n\t__u8 pad[16];\n};\n\nstruct kvm_kernel_irqfd;\n\nstruct kvm_irqfd_pt {\n\tstruct kvm_kernel_irqfd *irqfd;\n\tstruct kvm *kvm;\n\tpoll_table pt;\n\tint ret;\n};\n\nstruct kvm_s390_adapter_int {\n\tu64 ind_addr;\n\tu64 ind_gaddr;\n\tu64 summary_addr;\n\tu64 summary_gaddr;\n\tu64 ind_offset;\n\tu32 summary_offset;\n\tu32 adapter_id;\n};\n\nstruct kvm_xen_evtchn {\n\tu32 port;\n\tu32 vcpu_id;\n\tint vcpu_idx;\n\tu32 priority;\n};\n\nstruct kvm_kernel_irq_routing_entry {\n\tu32 gsi;\n\tu32 type;\n\tint (*set)(struct kvm_kernel_irq_routing_entry *, struct kvm *, int, int, bool);\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int irqchip;\n\t\t\tunsigned int pin;\n\t\t} irqchip;\n\t\tstruct {\n\t\t\tu32 address_lo;\n\t\t\tu32 address_hi;\n\t\t\tu32 data;\n\t\t\tu32 flags;\n\t\t\tu32 devid;\n\t\t} msi;\n\t\tstruct kvm_s390_adapter_int adapter;\n\t\tstruct kvm_hv_sint hv_sint;\n\t\tstruct kvm_xen_evtchn xen_evtchn;\n\t};\n\tstruct hlist_node link;\n};\n\nstruct kvm_kernel_irqfd_resampler;\n\nstruct kvm_kernel_irqfd {\n\tstruct kvm *kvm;\n\twait_queue_entry_t wait;\n\tstruct kvm_kernel_irq_routing_entry irq_entry;\n\tseqcount_spinlock_t irq_entry_sc;\n\tint gsi;\n\tstruct work_struct inject;\n\tstruct kvm_kernel_irqfd_resampler *resampler;\n\tstruct eventfd_ctx *resamplefd;\n\tstruct list_head resampler_link;\n\tstruct eventfd_ctx *eventfd;\n\tstruct list_head list;\n\tstruct work_struct shutdown;\n\tstruct irq_bypass_consumer consumer;\n\tstruct irq_bypass_producer *producer;\n\tstruct kvm_vcpu *irq_bypass_vcpu;\n\tstruct list_head vcpu_list;\n\tvoid *irq_bypass_data;\n};\n\nstruct kvm_kernel_irqfd_resampler {\n\tstruct kvm *kvm;\n\tstruct list_head list;\n\tstruct kvm_irq_ack_notifier notifier;\n\tstruct list_head link;\n};\n\nstruct kvm_mem_range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct kvm_memory_slot {\n\tstruct hlist_node id_node[2];\n\tstruct interval_tree_node hva_node[2];\n\tstruct rb_node gfn_node[2];\n\tgfn_t base_gfn;\n\tlong unsigned int npages;\n\tlong unsigned int *dirty_bitmap;\n\tstruct kvm_arch_memory_slot arch;\n\tlong unsigned int userspace_addr;\n\tu32 flags;\n\tshort int id;\n\tu16 as_id;\n\tstruct {\n\t\tstruct file *file;\n\t\tlong unsigned int pgoff;\n\t} gmem;\n};\n\nstruct kvm_memslot_iter {\n\tstruct kvm_memslots *slots;\n\tstruct rb_node *node;\n\tstruct kvm_memory_slot *slot;\n};\n\nstruct kvm_mmio_fragment {\n\tgpa_t gpa;\n\tvoid *data;\n\tunsigned int len;\n};\n\ntypedef bool (*gfn_handler_t)(struct kvm *, struct kvm_gfn_range *);\n\ntypedef void (*on_lock_fn_t)(struct kvm *);\n\nstruct kvm_mmu_notifier_range {\n\tu64 start;\n\tu64 end;\n\tunion kvm_mmu_notifier_arg arg;\n\tgfn_handler_t handler;\n\ton_lock_fn_t on_lock;\n\tbool flush_on_ret;\n\tbool may_block;\n\tbool lockless;\n};\n\nstruct kvm_mmu_notifier_return {\n\tbool ret;\n\tbool found_memslot;\n};\n\ntypedef struct kvm_mmu_notifier_return kvm_mn_ret_t;\n\nstruct kvm_mp_state {\n\t__u32 mp_state;\n};\n\nstruct kvm_mpidr_data {\n\tu64 mpidr_mask;\n\tstruct {\n\t\tstruct {} __empty_cmpidr_to_idx;\n\t\tu16 cmpidr_to_idx[0];\n\t};\n};\n\nstruct kvm_msi {\n\t__u32 address_lo;\n\t__u32 address_hi;\n\t__u32 data;\n\t__u32 flags;\n\t__u32 devid;\n\t__u8 pad[12];\n};\n\nstruct kvm_nvhe_init_params {\n\tlong unsigned int mair_el2;\n\tlong unsigned int tcr_el2;\n\tlong unsigned int tpidr_el2;\n\tlong unsigned int stack_hyp_va;\n\tlong unsigned int stack_pa;\n\tphys_addr_t pgd_pa;\n\tlong unsigned int hcr_el2;\n\tlong unsigned int vttbr;\n\tlong unsigned int vtcr;\n\tlong unsigned int tmp;\n};\n\nstruct kvm_nvhe_stacktrace_info {\n\tlong unsigned int stack_base;\n\tlong unsigned int overflow_stack_base;\n\tlong unsigned int fp;\n\tlong unsigned int pc;\n};\n\nstruct kvm_one_reg {\n\t__u64 id;\n\t__u64 addr;\n};\n\nstruct kvm_pgtable_visit_ctx {\n\tkvm_pte_t *ptep;\n\tkvm_pte_t old;\n\tvoid *arg;\n\tstruct kvm_pgtable_mm_ops *mm_ops;\n\tu64 start;\n\tu64 addr;\n\tu64 end;\n\ts8 level;\n\tenum kvm_pgtable_walk_flags flags;\n};\n\nstruct kvm_pgtable_walker;\n\nstruct kvm_pgtable_walk_data {\n\tstruct kvm_pgtable_walker *walker;\n\tconst u64 start;\n\tu64 addr;\n\tconst u64 end;\n};\n\ntypedef int (*kvm_pgtable_visitor_fn_t)(const struct kvm_pgtable_visit_ctx *, enum kvm_pgtable_walk_flags);\n\nstruct kvm_pgtable_walker {\n\tconst kvm_pgtable_visitor_fn_t cb;\n\tvoid * const arg;\n\tconst enum kvm_pgtable_walk_flags flags;\n};\n\nstruct kvm_pmc {\n\tu8 idx;\n\tstruct perf_event *perf_event;\n};\n\nstruct kvm_pmu_events {\n\tu64 events_host;\n\tu64 events_guest;\n};\n\nstruct kvm_pmu {\n\tstruct irq_work overflow_work;\n\tstruct kvm_pmu_events events;\n\tstruct kvm_pmc pmc[32];\n\tint irq_num;\n\tbool created;\n\tbool irq_level;\n};\n\nstruct kvm_pmu_event_filter {\n\t__u16 base_event;\n\t__u16 nevents;\n\t__u8 action;\n\t__u8 pad[3];\n};\n\nstruct kvm_ptp_clock {\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info caps;\n};\n\nstruct kvm_reg_list {\n\t__u64 n;\n\t__u64 reg[0];\n};\n\nstruct kvm_regs {\n\tstruct user_pt_regs regs;\n\t__u64 sp_el1;\n\t__u64 elr_el1;\n\t__u64 spsr[5];\n\tlong: 64;\n\tstruct user_fpsimd_state fp_regs;\n};\n\nstruct kvm_xen_exit {\n\t__u32 type;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 longmode;\n\t\t\t__u32 cpl;\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[6];\n\t\t} hcall;\n\t} u;\n};\n\nstruct kvm_sync_regs {\n\t__u64 device_irq_level;\n};\n\nstruct kvm_run {\n\t__u8 request_interrupt_window;\n\t__u8 immediate_exit__unsafe;\n\t__u8 padding1[6];\n\t__u32 exit_reason;\n\t__u8 ready_for_interrupt_injection;\n\t__u8 if_flag;\n\t__u16 flags;\n\t__u64 cr8;\n\t__u64 apic_base;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 hardware_exit_reason;\n\t\t} hw;\n\t\tstruct {\n\t\t\t__u64 hardware_entry_failure_reason;\n\t\t\t__u32 cpu;\n\t\t} fail_entry;\n\t\tstruct {\n\t\t\t__u32 exception;\n\t\t\t__u32 error_code;\n\t\t} ex;\n\t\tstruct {\n\t\t\t__u8 direction;\n\t\t\t__u8 size;\n\t\t\t__u16 port;\n\t\t\t__u32 count;\n\t\t\t__u64 data_offset;\n\t\t} io;\n\t\tstruct {\n\t\t\tstruct kvm_debug_exit_arch arch;\n\t\t} debug;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} mmio;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} iocsr_io;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u64 ret;\n\t\t\tunion {\n\t\t\t\t__u64 flags;\n\t\t\t};\n\t\t} hypercall;\n\t\tstruct {\n\t\t\t__u64 rip;\n\t\t\t__u32 is_write;\n\t\t\t__u32 pad;\n\t\t} tpr_access;\n\t\tstruct {\n\t\t\t__u8 icptcode;\n\t\t\t__u16 ipa;\n\t\t\t__u32 ipb;\n\t\t} s390_sieic;\n\t\t__u64 s390_reset_flags;\n\t\tstruct {\n\t\t\t__u64 trans_exc_code;\n\t\t\t__u32 pgm_code;\n\t\t} s390_ucontrol;\n\t\tstruct {\n\t\t\t__u32 dcrn;\n\t\t\t__u32 data;\n\t\t\t__u8 is_write;\n\t\t} dcr;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 data[16];\n\t\t} internal;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 flags;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 insn_size;\n\t\t\t\t\t__u8 insn_bytes[15];\n\t\t\t\t};\n\t\t\t};\n\t\t} emulation_failure;\n\t\tstruct {\n\t\t\t__u64 gprs[32];\n\t\t} osi;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 ret;\n\t\t\t__u64 args[9];\n\t\t} papr_hcall;\n\t\tstruct {\n\t\t\t__u16 subchannel_id;\n\t\t\t__u16 subchannel_nr;\n\t\t\t__u32 io_int_parm;\n\t\t\t__u32 io_int_word;\n\t\t\t__u32 ipb;\n\t\t\t__u8 dequeued;\n\t\t} s390_tsch;\n\t\tstruct {\n\t\t\t__u32 epr;\n\t\t} epr;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\t__u32 ndata;\n\t\t\tunion {\n\t\t\t\t__u64 data[16];\n\t\t\t};\n\t\t} system_event;\n\t\tstruct {\n\t\t\t__u64 addr;\n\t\t\t__u8 ar;\n\t\t\t__u8 reserved;\n\t\t\t__u8 fc;\n\t\t\t__u8 sel1;\n\t\t\t__u16 sel2;\n\t\t} s390_stsi;\n\t\tstruct {\n\t\t\t__u8 vector;\n\t\t} eoi;\n\t\tstruct kvm_hyperv_exit hyperv;\n\t\tstruct {\n\t\t\t__u64 esr_iss;\n\t\t\t__u64 fault_ipa;\n\t\t} arm_nisv;\n\t\tstruct {\n\t\t\t__u8 error;\n\t\t\t__u8 pad[7];\n\t\t\t__u32 reason;\n\t\t\t__u32 index;\n\t\t\t__u64 data;\n\t\t} msr;\n\t\tstruct kvm_xen_exit xen;\n\t\tstruct {\n\t\t\tlong unsigned int extension_id;\n\t\t\tlong unsigned int function_id;\n\t\t\tlong unsigned int args[6];\n\t\t\tlong unsigned int ret[2];\n\t\t} riscv_sbi;\n\t\tstruct {\n\t\t\tlong unsigned int csr_num;\n\t\t\tlong unsigned int new_value;\n\t\t\tlong unsigned int write_mask;\n\t\t\tlong unsigned int ret_value;\n\t\t} riscv_csr;\n\t\tstruct {\n\t\t\t__u32 flags;\n\t\t} notify;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 gpa;\n\t\t\t__u64 size;\n\t\t} memory_fault;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 nr;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 data[5];\n\t\t\t\t} unknown;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 gpa;\n\t\t\t\t\t__u64 size;\n\t\t\t\t} get_quote;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 leaf;\n\t\t\t\t\t__u64 r11;\n\t\t\t\t\t__u64 r12;\n\t\t\t\t\t__u64 r13;\n\t\t\t\t\t__u64 r14;\n\t\t\t\t} get_tdvmcall_info;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 vector;\n\t\t\t\t} setup_event_notify;\n\t\t\t};\n\t\t} tdx;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 esr;\n\t\t\t__u64 gva;\n\t\t\t__u64 gpa;\n\t\t} arm_sea;\n\t\tstruct kvm_exit_snp_req_certs snp_req_certs;\n\t\tchar padding[256];\n\t};\n\t__u64 kvm_valid_regs;\n\t__u64 kvm_dirty_regs;\n\tunion {\n\t\tstruct kvm_sync_regs regs;\n\t\tchar padding[2048];\n\t} s;\n};\n\nstruct kvm_s2_trans {\n\tphys_addr_t output;\n\tlong unsigned int block_size;\n\tbool writable;\n\tbool readable;\n\tint level;\n\tu32 esr;\n\tu64 desc;\n};\n\nstruct kvm_signal_mask {\n\t__u32 len;\n\t__u8 sigset[0];\n};\n\nstruct kvm_smccc_filter {\n\t__u32 base;\n\t__u32 nr_functions;\n\t__u8 action;\n\t__u8 pad[15];\n};\n\nstruct kvm_sregs {};\n\nstruct kvm_stat_data {\n\tstruct kvm *kvm;\n\tconst struct _kvm_stats_desc *desc;\n\tenum kvm_stat_kind kind;\n};\n\nstruct kvm_stats_header {\n\t__u32 flags;\n\t__u32 name_size;\n\t__u32 num_desc;\n\t__u32 id_offset;\n\t__u32 desc_offset;\n\t__u32 data_offset;\n};\n\nstruct resx {\n\tu64 res0;\n\tu64 res1;\n};\n\nstruct kvm_sysreg_masks {\n\tstruct resx mask[167];\n};\n\nstruct kvm_translation {\n\t__u64 linear_address;\n\t__u64 physical_address;\n\t__u8 valid;\n\t__u8 writeable;\n\t__u8 usermode;\n\t__u8 pad[5];\n};\n\nstruct kvm_userspace_memory_region {\n\t__u32 slot;\n\t__u32 flags;\n\t__u64 guest_phys_addr;\n\t__u64 memory_size;\n\t__u64 userspace_addr;\n};\n\nstruct kvm_userspace_memory_region2 {\n\t__u32 slot;\n\t__u32 flags;\n\t__u64 guest_phys_addr;\n\t__u64 memory_size;\n\t__u64 userspace_addr;\n\t__u64 guest_memfd_offset;\n\t__u32 guest_memfd;\n\t__u32 pad1;\n\t__u64 pad2[14];\n};\n\nstruct preempt_ops;\n\nstruct preempt_notifier {\n\tstruct hlist_node link;\n\tstruct preempt_ops *ops;\n};\n\nstruct kvm_vcpu_fault_info {\n\tu64 esr_el2;\n\tu64 far_el2;\n\tu64 hpfar_el2;\n\tu64 disr_el1;\n};\n\nstruct vgic_v2_cpu_if {\n\tu32 vgic_hcr;\n\tu32 vgic_vmcr;\n\tu32 vgic_apr;\n\tu32 vgic_lr[64];\n\tunsigned int used_lrs;\n};\n\nstruct vgic_v3_cpu_if {\n\tu32 vgic_hcr;\n\tu32 vgic_vmcr;\n\tu32 vgic_sre;\n\tu32 vgic_ap0r[4];\n\tu32 vgic_ap1r[4];\n\tu64 vgic_lr[16];\n\tstruct its_vpe its_vpe;\n\tunsigned int used_lrs;\n};\n\nstruct vgic_redist_region;\n\nstruct vgic_cpu {\n\tunion {\n\t\tstruct vgic_v2_cpu_if vgic_v2;\n\t\tstruct vgic_v3_cpu_if vgic_v3;\n\t};\n\tstruct vgic_irq *private_irqs;\n\traw_spinlock_t ap_list_lock;\n\tstruct list_head ap_list_head;\n\tstruct vgic_io_device rd_iodev;\n\tstruct vgic_redist_region *rdreg;\n\tu32 rdreg_index;\n\tatomic_t syncr_busy;\n\tu64 pendbaser;\n\tatomic_t ctlr;\n\tu32 num_pri_bits;\n\tu32 num_id_bits;\n};\n\nstruct vcpu_reset_state {\n\tlong unsigned int pc;\n\tlong unsigned int r0;\n\tbool be;\n\tbool reset;\n};\n\nstruct vncr_tlb;\n\nstruct kvm_vcpu_arch {\n\tstruct kvm_cpu_context ctxt;\n\tvoid *sve_state;\n\tenum fp_type fp_type;\n\tunsigned int sve_max_vl;\n\tstruct kvm_s2_mmu *hw_mmu;\n\tu64 hcr_el2;\n\tu64 hcrx_el2;\n\tu64 mdcr_el2;\n\tstruct {\n\t\tu64 r;\n\t\tu64 w;\n\t} fgt[8];\n\tstruct kvm_vcpu_fault_info fault;\n\tu8 cflags;\n\tu8 iflags;\n\tu16 sflags;\n\tbool pause;\n\tstruct kvm_guest_debug_arch vcpu_debug_state;\n\tstruct kvm_guest_debug_arch external_debug_state;\n\tu64 external_mdscr_el1;\n\tenum {\n\t\tVCPU_DEBUG_FREE = 0,\n\t\tVCPU_DEBUG_HOST_OWNED = 1,\n\t\tVCPU_DEBUG_GUEST_OWNED = 2,\n\t} debug_owner;\n\tstruct vgic_cpu vgic_cpu;\n\tstruct arch_timer_cpu timer_cpu;\n\tstruct kvm_pmu pmu;\n\tstruct kvm_mp_state mp_state;\n\tspinlock_t mp_state_lock;\n\tstruct kvm_mmu_memory_cache mmu_page_cache;\n\tstruct kvm_hyp_memcache pkvm_memcache;\n\tu64 vsesr_el2;\n\tstruct vcpu_reset_state reset_state;\n\tstruct {\n\t\tu64 last_steal;\n\t\tgpa_t base;\n\t} steal;\n\tu32 *ccsidr;\n\tstruct vncr_tlb *vncr_tlb;\n\tlong: 64;\n};\n\nstruct kvm_vcpu_stat_generic {\n\tu64 halt_successful_poll;\n\tu64 halt_attempted_poll;\n\tu64 halt_poll_invalid;\n\tu64 halt_wakeup;\n\tu64 halt_poll_success_ns;\n\tu64 halt_poll_fail_ns;\n\tu64 halt_wait_ns;\n\tu64 halt_poll_success_hist[32];\n\tu64 halt_poll_fail_hist[32];\n\tu64 halt_wait_hist[32];\n\tu64 blocking;\n};\n\nstruct kvm_vcpu_stat {\n\tstruct kvm_vcpu_stat_generic generic;\n\tu64 hvc_exit_stat;\n\tu64 wfe_exit_stat;\n\tu64 wfi_exit_stat;\n\tu64 mmio_exit_user;\n\tu64 mmio_exit_kernel;\n\tu64 signal_exits;\n\tu64 exits;\n};\n\nstruct kvm_vcpu {\n\tstruct kvm *kvm;\n\tstruct preempt_notifier preempt_notifier;\n\tint cpu;\n\tint vcpu_id;\n\tint vcpu_idx;\n\tint ____srcu_idx;\n\tint mode;\n\tu64 requests;\n\tlong unsigned int guest_debug;\n\tstruct mutex mutex;\n\tstruct kvm_run *run;\n\tstruct rcuwait wait;\n\tstruct pid *pid;\n\trwlock_t pid_lock;\n\tint sigset_active;\n\tsigset_t sigset;\n\tunsigned int halt_poll_ns;\n\tbool valid_wakeup;\n\tint mmio_needed;\n\tint mmio_read_completed;\n\tint mmio_is_write;\n\tint mmio_cur_fragment;\n\tint mmio_nr_fragments;\n\tstruct kvm_mmio_fragment mmio_fragments[2];\n\tstruct {\n\t\tbool in_spin_loop;\n\t\tbool dy_eligible;\n\t} spin_loop;\n\tbool wants_to_run;\n\tbool preempted;\n\tbool ready;\n\tbool scheduled_out;\n\tstruct kvm_vcpu_arch arch;\n\tstruct kvm_vcpu_stat stat;\n\tchar stats_id[48];\n\tstruct kvm_dirty_ring dirty_ring;\n\tstruct kvm_memory_slot *last_used_slot;\n\tu64 last_used_slot_gen;\n\tlong: 64;\n};\n\nstruct kvm_vcpu_events {\n\tstruct {\n\t\t__u8 serror_pending;\n\t\t__u8 serror_has_esr;\n\t\t__u8 ext_dabt_pending;\n\t\t__u8 pad[5];\n\t\t__u64 serror_esr;\n\t} exception;\n\t__u32 reserved[12];\n};\n\nstruct kvm_vcpu_init {\n\t__u32 target;\n\t__u32 features[7];\n};\n\nstruct kvm_vfio {\n\tstruct list_head file_list;\n\tstruct mutex lock;\n\tbool noncoherent;\n};\n\nstruct kvm_vfio_file {\n\tstruct list_head node;\n\tstruct file *file;\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nstruct l2cache_pmu {\n\tstruct hlist_node node;\n\tu32 num_pmus;\n\tstruct pmu pmu;\n\tint num_counters;\n\tcpumask_t cpumask;\n\tstruct platform_device *pdev;\n\tstruct cluster_pmu **pmu_cluster;\n\tstruct list_head clusters;\n};\n\nunion l3_hdr_info {\n\tstruct iphdr *v4;\n\tstruct ipv6hdr *v6;\n\tunsigned char *hdr;\n};\n\nstruct l3cache_event_ops {\n\tvoid (*start)(struct perf_event *);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*update)(struct perf_event *);\n};\n\nstruct l3cache_pmu {\n\tstruct pmu pmu;\n\tstruct hlist_node node;\n\tvoid *regs;\n\tstruct perf_event *events[8];\n\tlong unsigned int used_mask[1];\n\tcpumask_t cpumask;\n};\n\nstruct tcphdr;\n\nunion l4_hdr_info {\n\tstruct tcphdr *tcp;\n\tstruct udphdr *udp;\n\tstruct gre_base_hdr *gre;\n\tunsigned char *hdr;\n};\n\nstruct lan8814_ptp_rx_ts {\n\tstruct list_head list;\n\tu32 seconds;\n\tu32 nsec;\n\tu16 seq_id;\n};\n\nstruct lan8814_shared_priv {\n\tstruct phy_device *phydev;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct ptp_pin_desc *pin_config;\n\tstruct mutex shared_lock;\n};\n\nstruct lan8842_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_errors;\n};\n\nstruct lan8842_priv {\n\tstruct lan8842_phy_stats phy_stats;\n\tstruct kszphy_ptp_priv ptp_priv;\n\tu16 rev;\n};\n\nstruct lanphy_reg_data {\n\tint page;\n\tu16 addr;\n\tu16 val;\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tu64 val[2];\n};\n\nstruct lateeoi_work {\n\tstruct delayed_work delayed;\n\tspinlock_t eoi_list_lock;\n\tstruct list_head eoi_list;\n};\n\nstruct lazy_mmu_state {\n\tu8 enable_count;\n\tu8 pause_count;\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct lcd_properties {\n\tint max_contrast;\n};\n\nstruct lcd_ops;\n\nstruct lcd_device {\n\tstruct lcd_properties props;\n\tstruct mutex ops_lock;\n\tconst struct lcd_ops *ops;\n\tstruct mutex update_lock;\n\tstruct list_head entry;\n\tstruct device dev;\n};\n\nstruct lcd_ops {\n\tint (*get_power)(struct lcd_device *);\n\tint (*set_power)(struct lcd_device *, int);\n\tint (*get_contrast)(struct lcd_device *);\n\tint (*set_contrast)(struct lcd_device *, int);\n\tint (*set_mode)(struct lcd_device *, u32, u32);\n\tbool (*controls_device)(struct lcd_device *, struct device *);\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct leaf_walk_data {\n\tkvm_pte_t pte;\n\ts8 level;\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct mc_subled;\n\nstruct led_classdev_mc {\n\tstruct led_classdev led_cdev;\n\tunsigned int num_colors;\n\tstruct mc_subled *subled_info;\n};\n\nstruct led_hw_trigger_type {\n\tint dummy;\n};\n\nstruct led_init_data {\n\tstruct fwnode_handle *fwnode;\n\tconst char *default_label;\n\tconst char *devicename;\n\tbool devname_mandatory;\n};\n\nstruct led_lookup_data {\n\tstruct list_head list;\n\tconst char *provider;\n\tconst char *dev_id;\n\tconst char *con_id;\n};\n\nstruct led_pattern {\n\tu32 delta_t;\n\tint brightness;\n};\n\nstruct led_properties {\n\tu32 color;\n\tbool color_present;\n\tconst char *function;\n\tu32 func_enum;\n\tbool func_enum_present;\n\tconst char *label;\n};\n\nstruct led_pwm {\n\tconst char *name;\n\tu8 active_low;\n\tu8 default_state;\n\tunsigned int max_brightness;\n};\n\nstruct led_pwm_data {\n\tstruct gpio_desc *enable_gpio;\n\tstruct led_classdev cdev;\n\tstruct pwm_device *pwm;\n\tstruct pwm_state pwmstate;\n\tunsigned int active_low;\n};\n\nstruct led_pwm_priv {\n\tint num_leds;\n\tstruct led_pwm_data leds[0];\n};\n\nstruct led_trigger_cpu {\n\tbool is_active;\n\tchar name[8];\n\tstruct led_trigger *_trig;\n};\n\nstruct legacy_clk_set_value {\n\t__le32 rate;\n\t__le16 id;\n\t__le16 reserved;\n};\n\nstruct legacy_scpi_shared_mem {\n\t__le32 status;\n\tu8 payload[0];\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linereq;\n\nstruct line {\n\tstruct gpio_desc *desc;\n\tstruct linereq *req;\n\tunsigned int irq;\n\tu64 edflags;\n\tu64 timestamp_ns;\n\tu32 req_seqno;\n\tu32 line_seqno;\n\tstruct delayed_work work;\n\tunsigned int sw_debounced;\n\tunsigned int level;\n\tstruct hte_ts_desc hdesc;\n\tint raw_level;\n\tu32 total_discard_seq;\n\tu32 last_seqno;\n};\n\nstruct linear_range {\n\tunsigned int min;\n\tunsigned int min_sel;\n\tunsigned int max_sel;\n\tunsigned int step;\n};\n\nstruct lineevent_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *desc;\n\tu32 eflags;\n\tint irq;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpioevent_data *type;\n\t\t\tconst struct gpioevent_data *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpioevent_data *ptr;\n\t\t\tconst struct gpioevent_data *ptr_const;\n\t\t};\n\t\tstruct gpioevent_data buf[16];\n\t} events;\n\tu64 timestamp;\n};\n\nstruct linehandle_state {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tstruct gpio_desc *descs[64];\n\tu32 num_descs;\n};\n\nstruct lineinfo_changed_ctx {\n\tstruct work_struct work;\n\tstruct gpio_v2_line_info_changed chg;\n\tstruct gpio_device *gdev;\n\tstruct gpio_chardev_data *cdev;\n};\n\nstruct linereq {\n\tstruct gpio_device *gdev;\n\tconst char *label;\n\tu32 num_lines;\n\twait_queue_head_t wait;\n\tstruct notifier_block device_unregistered_nb;\n\tu32 event_buffer_size;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct gpio_v2_line_event *type;\n\t\t\tconst struct gpio_v2_line_event *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct gpio_v2_line_event *ptr;\n\t\t\tconst struct gpio_v2_line_event *ptr_const;\n\t\t};\n\t\tstruct gpio_v2_line_event buf[0];\n\t} events;\n\tatomic_t seqno;\n\tstruct mutex config_mutex;\n\tstruct line lines[0];\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_capabilities {\n\tint speed;\n\tunsigned int duplex;\n\tlong unsigned int linkmodes[2];\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct linked_page {\n\tstruct linked_page *next;\n\tchar data[4088];\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n};\n\nstruct linux_efi_initrd {\n\tlong unsigned int base;\n\tlong unsigned int size;\n};\n\nstruct linux_efi_memreserve {\n\tint size;\n\tatomic_t count;\n\tphys_addr_t next;\n\tstruct {\n\t\tphys_addr_t base;\n\t\tphys_addr_t size;\n\t} entry[0];\n};\n\nstruct linux_efi_random_seed {\n\tu32 size;\n\tu8 bits[0];\n};\n\nstruct linux_efi_tpm_eventlog {\n\tu32 size;\n\tu32 final_events_preboot_size;\n\tu8 version;\n\tu8 log[0];\n};\n\nstruct linux_logo {\n\tint type;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int clutsize;\n\tconst unsigned char *clut;\n\tconst unsigned char *data;\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n\tstruct list_head list;\n\tint shrinker_id;\n\tbool memcg_aware;\n\tstruct xarray xa;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_memcg {\n\tstruct callback_head rcu;\n\tstruct list_lru_one node[0];\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct listener {\n\tstruct list_head list;\n\tpid_t pid;\n\tchar valid;\n};\n\nstruct listener_list {\n\tstruct rw_semaphore sem;\n\tstruct list_head list;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf64_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct location;\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n\tloff_t idx;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct location {\n\tdepot_stack_handle_t handle;\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong unsigned int waste;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[8];\n\tnodemask_t nodes;\n};\n\nstruct lock_manager {\n\tstruct list_head list;\n\tbool block_opens;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct lockd_net {\n\tunsigned int nlmsvc_users;\n\tlong unsigned int next_gc;\n\tlong unsigned int nrhosts;\n\tu32 gracetime;\n\tu16 tcp_port;\n\tu16 udp_port;\n\tstruct delayed_work grace_period_end;\n\tstruct lock_manager lockd_manager;\n\tstruct list_head nsm_handles;\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tloff_t li_pos;\n};\n\nstruct log_header {\n\t__le32 magic_word;\n\tchar reserved[4];\n\t__le32 buf_start;\n\t__le32 buf_length;\n\t__le32 last_byte;\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct logo_data {\n\tint depth;\n\tint needs_directpalette;\n\tint needs_truepalette;\n\tint needs_cmapreset;\n\tconst struct linux_logo *logo;\n};\n\nstruct loop_cmd {\n\tstruct list_head list_entry;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct cgroup_subsys_state *memcg_css;\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nstruct loop_device {\n\tint lo_number;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tchar lo_file_name[64];\n\tstruct file *lo_backing_file;\n\tunsigned int lo_min_dio_size;\n\tstruct block_device *lo_device;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tspinlock_t lo_work_lock;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rootcg_work;\n\tstruct list_head rootcg_cmd_list;\n\tstruct list_head idle_worker_list;\n\tstruct rb_root worker_tree;\n\tstruct timer_list timer;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n\tstruct mutex lo_mutex;\n\tbool idr_visible;\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_worker {\n\tstruct rb_node rb_node;\n\tstruct work_struct work;\n\tstruct list_head cmd_list;\n\tstruct list_head idle_list;\n\tstruct loop_device *lo;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tlong unsigned int last_ran_at;\n};\n\nunion lower_chunk {\n\tunion lower_chunk *next;\n\tlong unsigned int data[256];\n};\n\nstruct lpc_cycle_para {\n\tunsigned int opflags;\n\tunsigned int csize;\n};\n\nstruct lpi2c_imx_dma {\n\tbool using_pio_mode;\n\tu8 rx_cmd_buf_len;\n\tu8 *dma_buf;\n\tu16 *rx_cmd_buf;\n\tunsigned int dma_len;\n\tunsigned int tx_burst_num;\n\tunsigned int rx_burst_num;\n\tlong unsigned int dma_msg_flag;\n\tresource_size_t phy_addr;\n\tdma_addr_t dma_tx_addr;\n\tdma_addr_t dma_addr;\n\tenum dma_data_direction dma_data_dir;\n\tenum dma_transfer_direction dma_transfer_dir;\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n};\n\nstruct lpi2c_imx_struct {\n\tstruct i2c_adapter adapter;\n\tint num_clks;\n\tstruct clk_bulk_data *clks;\n\tvoid *base;\n\t__u8 *rx_buf;\n\t__u8 *tx_buf;\n\tstruct completion complete;\n\tlong unsigned int rate_per;\n\tunsigned int msglen;\n\tunsigned int delivered;\n\tunsigned int block_data;\n\tunsigned int bitrate;\n\tunsigned int txfifosize;\n\tunsigned int rxfifosize;\n\tenum lpi2c_imx_mode mode;\n\tstruct i2c_bus_recovery_info rinfo;\n\tbool can_use_dma;\n\tstruct lpi2c_imx_dma *dma;\n\tstruct i2c_client *target;\n\tint irq;\n\tconst struct imx_lpi2c_hwdata *hwdata;\n};\n\nstruct lpi_range {\n\tstruct list_head entry;\n\tu32 base_id;\n\tu32 span;\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct lpuart_port {\n\tstruct uart_port port;\n\tenum lpuart_type devtype;\n\tstruct clk *ipg_clk;\n\tstruct clk *baud_clk;\n\tunsigned int txfifo_size;\n\tunsigned int rxfifo_size;\n\tu8 rx_watermark;\n\tbool lpuart_dma_tx_use;\n\tbool lpuart_dma_rx_use;\n\tstruct dma_chan *dma_tx_chan;\n\tstruct dma_chan *dma_rx_chan;\n\tstruct dma_async_tx_descriptor *dma_tx_desc;\n\tstruct dma_async_tx_descriptor *dma_rx_desc;\n\tdma_cookie_t dma_tx_cookie;\n\tdma_cookie_t dma_rx_cookie;\n\tunsigned int dma_tx_bytes;\n\tunsigned int dma_rx_bytes;\n\tbool dma_tx_in_progress;\n\tunsigned int dma_rx_timeout;\n\tstruct timer_list lpuart_timer;\n\tstruct scatterlist rx_sgl;\n\tstruct scatterlist tx_sgl[2];\n\tstruct circ_buf rx_ring;\n\tint rx_dma_rng_buf_len;\n\tint last_residue;\n\tunsigned int dma_tx_nents;\n\twait_queue_head_t dma_wait;\n\tbool is_cs7;\n\tbool dma_idle_int;\n};\n\nstruct lpuart_soc_data {\n\tenum lpuart_type devtype;\n\tchar iotype;\n\tu8 reg_off;\n\tu8 rx_watermark;\n};\n\nstruct zswap_lruvec_state {};\n\nstruct pglist_data;\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct pglist_data *pgdat;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct lruvec_stats {\n\tlong int state[33];\n\tlong int state_local[33];\n\tlong int state_pending[33];\n};\n\nstruct lruvec_stats_percpu {\n\tlong int state[33];\n\tlong int state_prev[33];\n};\n\nstruct ls_extirq_data {\n\tvoid *intpcr;\n\traw_spinlock_t lock;\n\tbool big_endian;\n\tbool is_ls1021a_or_ls1043a;\n\tu32 nirq;\n\tstruct irq_fwspec map[12];\n};\n\nstruct mobiveil_msi {\n\tstruct mutex lock;\n\tstruct irq_domain *dev_domain;\n\tphys_addr_t msi_pages_phys;\n\tint num_of_vectors;\n\tlong unsigned int msi_irq_in_use[1];\n};\n\nstruct mobiveil_rp_ops;\n\nstruct mobiveil_root_port {\n\tvoid *config_axi_slave_base;\n\tstruct resource *ob_io_res;\n\tconst struct mobiveil_rp_ops *ops;\n\tint irq;\n\traw_spinlock_t intx_mask_lock;\n\tstruct irq_domain *intx_domain;\n\tstruct mobiveil_msi msi;\n\tstruct pci_host_bridge *bridge;\n};\n\nstruct mobiveil_pab_ops;\n\nstruct mobiveil_pcie {\n\tstruct platform_device *pdev;\n\tvoid *csr_axi_slave_base;\n\tvoid *apb_csr_base;\n\tphys_addr_t pcie_reg_base;\n\tint apio_wins;\n\tint ppio_wins;\n\tint ob_wins_configured;\n\tint ib_wins_configured;\n\tconst struct mobiveil_pab_ops *ops;\n\tstruct mobiveil_root_port rp;\n};\n\nstruct ls_g4_pcie {\n\tstruct mobiveil_pcie pci;\n\tstruct delayed_work dwork;\n\tint irq;\n};\n\nstruct ls_pcie_drvdata;\n\nstruct ls_pcie {\n\tstruct dw_pcie *pci;\n\tconst struct ls_pcie_drvdata *drvdata;\n\tvoid *pf_lut_base;\n\tstruct regmap *scfg;\n\tint index;\n\tbool big_endian;\n};\n\nstruct ls_pcie_drvdata {\n\tconst u32 pf_lut_off;\n\tconst struct dw_pcie_host_ops *ops;\n\tint (*exit_from_l2)(struct dw_pcie_rp *);\n\tbool scfg_support;\n\tbool pm_support;\n};\n\nstruct ls_scfg_msi_cfg;\n\nstruct ls_scfg_msir;\n\nstruct ls_scfg_msi {\n\tspinlock_t lock;\n\tstruct platform_device *pdev;\n\tstruct irq_domain *parent;\n\tvoid *regs;\n\tphys_addr_t msiir_addr;\n\tstruct ls_scfg_msi_cfg *cfg;\n\tu32 msir_num;\n\tstruct ls_scfg_msir *msir;\n\tu32 irqs_num;\n\tlong unsigned int *used;\n};\n\nstruct ls_scfg_msi_cfg {\n\tu32 ibs_shift;\n\tu32 msir_irqs;\n\tu32 msir_base;\n};\n\nstruct ls_scfg_msir {\n\tstruct ls_scfg_msi *msi_data;\n\tunsigned int index;\n\tunsigned int gic_irq;\n\tunsigned int bit_start;\n\tunsigned int bit_end;\n\tunsigned int srs;\n\tvoid *reg;\n};\n\nstruct skcipher_alg_common {\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct lskcipher_alg {\n\tint (*setkey)(struct crypto_lskcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*decrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*init)(struct crypto_lskcipher *);\n\tvoid (*exit)(struct crypto_lskcipher *);\n\tstruct skcipher_alg_common co;\n};\n\nstruct lskcipher_instance {\n\tvoid (*free)(struct lskcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct lskcipher_alg alg;\n\t};\n};\n\nstruct lsm_blob_sizes {\n\tunsigned int lbs_cred;\n\tunsigned int lbs_file;\n\tunsigned int lbs_ib;\n\tunsigned int lbs_inode;\n\tunsigned int lbs_sock;\n\tunsigned int lbs_superblock;\n\tunsigned int lbs_ipc;\n\tunsigned int lbs_key;\n\tunsigned int lbs_msg_msg;\n\tunsigned int lbs_perf_event;\n\tunsigned int lbs_task;\n\tunsigned int lbs_xattr_count;\n\tunsigned int lbs_tun_dev;\n\tunsigned int lbs_bdev;\n\tunsigned int lbs_bpf_map;\n\tunsigned int lbs_bpf_prog;\n\tunsigned int lbs_bpf_token;\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct lsm_ctx {\n\t__u64 id;\n\t__u64 flags;\n\t__u64 len;\n\t__u64 ctx_len;\n\t__u8 ctx[0];\n};\n\nstruct lsm_ibendport_audit {\n\tconst char *dev_name;\n\tu8 port;\n};\n\nstruct lsm_ibpkey_audit {\n\tu64 subnet_prefix;\n\tu16 pkey;\n};\n\nstruct lsm_id {\n\tconst char *name;\n\tu64 id;\n};\n\nstruct lsm_info {\n\tconst struct lsm_id *id;\n\tenum lsm_order order;\n\tlong unsigned int flags;\n\tstruct lsm_blob_sizes *blobs;\n\tint *enabled;\n\tint (*init)(void);\n\tint (*initcall_pure)(void);\n\tint (*initcall_early)(void);\n\tint (*initcall_core)(void);\n\tint (*initcall_subsys)(void);\n\tint (*initcall_fs)(void);\n\tint (*initcall_device)(void);\n\tint (*initcall_late)(void);\n};\n\nstruct lsm_ioctlop_audit {\n\tstruct path path;\n\tu16 cmd;\n};\n\nstruct lsm_network_audit {\n\tint netif;\n\tconst struct sock *sk;\n\tu16 family;\n\t__be16 dport;\n\t__be16 sport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 daddr;\n\t\t\t__be32 saddr;\n\t\t} v4;\n\t\tstruct {\n\t\t\tstruct in6_addr daddr;\n\t\t\tstruct in6_addr saddr;\n\t\t} v6;\n\t} fam;\n};\n\nstruct static_call_key;\n\nstruct security_hook_list;\n\nstruct static_key_false;\n\nstruct lsm_static_call {\n\tstruct static_call_key *key;\n\tvoid *trampoline;\n\tstruct security_hook_list *hl;\n\tstruct static_key_false *active;\n};\n\nstruct lsm_static_calls_table {\n\tstruct lsm_static_call binder_set_context_mgr[1];\n\tstruct lsm_static_call binder_transaction[1];\n\tstruct lsm_static_call binder_transfer_binder[1];\n\tstruct lsm_static_call binder_transfer_file[1];\n\tstruct lsm_static_call ptrace_access_check[1];\n\tstruct lsm_static_call ptrace_traceme[1];\n\tstruct lsm_static_call capget[1];\n\tstruct lsm_static_call capset[1];\n\tstruct lsm_static_call capable[1];\n\tstruct lsm_static_call quotactl[1];\n\tstruct lsm_static_call quota_on[1];\n\tstruct lsm_static_call syslog[1];\n\tstruct lsm_static_call settime[1];\n\tstruct lsm_static_call vm_enough_memory[1];\n\tstruct lsm_static_call bprm_creds_for_exec[1];\n\tstruct lsm_static_call bprm_creds_from_file[1];\n\tstruct lsm_static_call bprm_check_security[1];\n\tstruct lsm_static_call bprm_committing_creds[1];\n\tstruct lsm_static_call bprm_committed_creds[1];\n\tstruct lsm_static_call fs_context_submount[1];\n\tstruct lsm_static_call fs_context_dup[1];\n\tstruct lsm_static_call fs_context_parse_param[1];\n\tstruct lsm_static_call sb_alloc_security[1];\n\tstruct lsm_static_call sb_delete[1];\n\tstruct lsm_static_call sb_free_security[1];\n\tstruct lsm_static_call sb_free_mnt_opts[1];\n\tstruct lsm_static_call sb_eat_lsm_opts[1];\n\tstruct lsm_static_call sb_mnt_opts_compat[1];\n\tstruct lsm_static_call sb_remount[1];\n\tstruct lsm_static_call sb_kern_mount[1];\n\tstruct lsm_static_call sb_show_options[1];\n\tstruct lsm_static_call sb_statfs[1];\n\tstruct lsm_static_call sb_mount[1];\n\tstruct lsm_static_call sb_umount[1];\n\tstruct lsm_static_call sb_pivotroot[1];\n\tstruct lsm_static_call sb_set_mnt_opts[1];\n\tstruct lsm_static_call sb_clone_mnt_opts[1];\n\tstruct lsm_static_call move_mount[1];\n\tstruct lsm_static_call dentry_init_security[1];\n\tstruct lsm_static_call dentry_create_files_as[1];\n\tstruct lsm_static_call path_notify[1];\n\tstruct lsm_static_call inode_alloc_security[1];\n\tstruct lsm_static_call inode_free_security[1];\n\tstruct lsm_static_call inode_free_security_rcu[1];\n\tstruct lsm_static_call inode_init_security[1];\n\tstruct lsm_static_call inode_init_security_anon[1];\n\tstruct lsm_static_call inode_create[1];\n\tstruct lsm_static_call inode_post_create_tmpfile[1];\n\tstruct lsm_static_call inode_link[1];\n\tstruct lsm_static_call inode_unlink[1];\n\tstruct lsm_static_call inode_symlink[1];\n\tstruct lsm_static_call inode_mkdir[1];\n\tstruct lsm_static_call inode_rmdir[1];\n\tstruct lsm_static_call inode_mknod[1];\n\tstruct lsm_static_call inode_rename[1];\n\tstruct lsm_static_call inode_readlink[1];\n\tstruct lsm_static_call inode_follow_link[1];\n\tstruct lsm_static_call inode_permission[1];\n\tstruct lsm_static_call inode_setattr[1];\n\tstruct lsm_static_call inode_post_setattr[1];\n\tstruct lsm_static_call inode_getattr[1];\n\tstruct lsm_static_call inode_xattr_skipcap[1];\n\tstruct lsm_static_call inode_setxattr[1];\n\tstruct lsm_static_call inode_post_setxattr[1];\n\tstruct lsm_static_call inode_getxattr[1];\n\tstruct lsm_static_call inode_listxattr[1];\n\tstruct lsm_static_call inode_removexattr[1];\n\tstruct lsm_static_call inode_post_removexattr[1];\n\tstruct lsm_static_call inode_file_setattr[1];\n\tstruct lsm_static_call inode_file_getattr[1];\n\tstruct lsm_static_call inode_set_acl[1];\n\tstruct lsm_static_call inode_post_set_acl[1];\n\tstruct lsm_static_call inode_get_acl[1];\n\tstruct lsm_static_call inode_remove_acl[1];\n\tstruct lsm_static_call inode_post_remove_acl[1];\n\tstruct lsm_static_call inode_need_killpriv[1];\n\tstruct lsm_static_call inode_killpriv[1];\n\tstruct lsm_static_call inode_getsecurity[1];\n\tstruct lsm_static_call inode_setsecurity[1];\n\tstruct lsm_static_call inode_listsecurity[1];\n\tstruct lsm_static_call inode_getlsmprop[1];\n\tstruct lsm_static_call inode_copy_up[1];\n\tstruct lsm_static_call inode_copy_up_xattr[1];\n\tstruct lsm_static_call inode_setintegrity[1];\n\tstruct lsm_static_call kernfs_init_security[1];\n\tstruct lsm_static_call file_permission[1];\n\tstruct lsm_static_call file_alloc_security[1];\n\tstruct lsm_static_call file_release[1];\n\tstruct lsm_static_call file_free_security[1];\n\tstruct lsm_static_call file_ioctl[1];\n\tstruct lsm_static_call file_ioctl_compat[1];\n\tstruct lsm_static_call mmap_addr[1];\n\tstruct lsm_static_call mmap_file[1];\n\tstruct lsm_static_call file_mprotect[1];\n\tstruct lsm_static_call file_lock[1];\n\tstruct lsm_static_call file_fcntl[1];\n\tstruct lsm_static_call file_set_fowner[1];\n\tstruct lsm_static_call file_send_sigiotask[1];\n\tstruct lsm_static_call file_receive[1];\n\tstruct lsm_static_call file_open[1];\n\tstruct lsm_static_call file_post_open[1];\n\tstruct lsm_static_call file_truncate[1];\n\tstruct lsm_static_call task_alloc[1];\n\tstruct lsm_static_call task_free[1];\n\tstruct lsm_static_call cred_alloc_blank[1];\n\tstruct lsm_static_call cred_free[1];\n\tstruct lsm_static_call cred_prepare[1];\n\tstruct lsm_static_call cred_transfer[1];\n\tstruct lsm_static_call cred_getsecid[1];\n\tstruct lsm_static_call cred_getlsmprop[1];\n\tstruct lsm_static_call kernel_act_as[1];\n\tstruct lsm_static_call kernel_create_files_as[1];\n\tstruct lsm_static_call kernel_module_request[1];\n\tstruct lsm_static_call kernel_load_data[1];\n\tstruct lsm_static_call kernel_post_load_data[1];\n\tstruct lsm_static_call kernel_read_file[1];\n\tstruct lsm_static_call kernel_post_read_file[1];\n\tstruct lsm_static_call task_fix_setuid[1];\n\tstruct lsm_static_call task_fix_setgid[1];\n\tstruct lsm_static_call task_fix_setgroups[1];\n\tstruct lsm_static_call task_setpgid[1];\n\tstruct lsm_static_call task_getpgid[1];\n\tstruct lsm_static_call task_getsid[1];\n\tstruct lsm_static_call current_getlsmprop_subj[1];\n\tstruct lsm_static_call task_getlsmprop_obj[1];\n\tstruct lsm_static_call task_setnice[1];\n\tstruct lsm_static_call task_setioprio[1];\n\tstruct lsm_static_call task_getioprio[1];\n\tstruct lsm_static_call task_prlimit[1];\n\tstruct lsm_static_call task_setrlimit[1];\n\tstruct lsm_static_call task_setscheduler[1];\n\tstruct lsm_static_call task_getscheduler[1];\n\tstruct lsm_static_call task_movememory[1];\n\tstruct lsm_static_call task_kill[1];\n\tstruct lsm_static_call task_prctl[1];\n\tstruct lsm_static_call task_to_inode[1];\n\tstruct lsm_static_call userns_create[1];\n\tstruct lsm_static_call ipc_permission[1];\n\tstruct lsm_static_call ipc_getlsmprop[1];\n\tstruct lsm_static_call msg_msg_alloc_security[1];\n\tstruct lsm_static_call msg_msg_free_security[1];\n\tstruct lsm_static_call msg_queue_alloc_security[1];\n\tstruct lsm_static_call msg_queue_free_security[1];\n\tstruct lsm_static_call msg_queue_associate[1];\n\tstruct lsm_static_call msg_queue_msgctl[1];\n\tstruct lsm_static_call msg_queue_msgsnd[1];\n\tstruct lsm_static_call msg_queue_msgrcv[1];\n\tstruct lsm_static_call shm_alloc_security[1];\n\tstruct lsm_static_call shm_free_security[1];\n\tstruct lsm_static_call shm_associate[1];\n\tstruct lsm_static_call shm_shmctl[1];\n\tstruct lsm_static_call shm_shmat[1];\n\tstruct lsm_static_call sem_alloc_security[1];\n\tstruct lsm_static_call sem_free_security[1];\n\tstruct lsm_static_call sem_associate[1];\n\tstruct lsm_static_call sem_semctl[1];\n\tstruct lsm_static_call sem_semop[1];\n\tstruct lsm_static_call netlink_send[1];\n\tstruct lsm_static_call d_instantiate[1];\n\tstruct lsm_static_call getselfattr[1];\n\tstruct lsm_static_call setselfattr[1];\n\tstruct lsm_static_call getprocattr[1];\n\tstruct lsm_static_call setprocattr[1];\n\tstruct lsm_static_call ismaclabel[1];\n\tstruct lsm_static_call secid_to_secctx[1];\n\tstruct lsm_static_call lsmprop_to_secctx[1];\n\tstruct lsm_static_call secctx_to_secid[1];\n\tstruct lsm_static_call release_secctx[1];\n\tstruct lsm_static_call inode_invalidate_secctx[1];\n\tstruct lsm_static_call inode_notifysecctx[1];\n\tstruct lsm_static_call inode_setsecctx[1];\n\tstruct lsm_static_call inode_getsecctx[1];\n\tstruct lsm_static_call key_alloc[1];\n\tstruct lsm_static_call key_permission[1];\n\tstruct lsm_static_call key_getsecurity[1];\n\tstruct lsm_static_call key_post_create_or_update[1];\n\tstruct lsm_static_call audit_rule_init[1];\n\tstruct lsm_static_call audit_rule_known[1];\n\tstruct lsm_static_call audit_rule_match[1];\n\tstruct lsm_static_call audit_rule_free[1];\n\tstruct lsm_static_call bpf[1];\n\tstruct lsm_static_call bpf_map[1];\n\tstruct lsm_static_call bpf_prog[1];\n\tstruct lsm_static_call bpf_map_create[1];\n\tstruct lsm_static_call bpf_map_free[1];\n\tstruct lsm_static_call bpf_prog_load[1];\n\tstruct lsm_static_call bpf_prog_free[1];\n\tstruct lsm_static_call bpf_token_create[1];\n\tstruct lsm_static_call bpf_token_free[1];\n\tstruct lsm_static_call bpf_token_cmd[1];\n\tstruct lsm_static_call bpf_token_capable[1];\n\tstruct lsm_static_call locked_down[1];\n\tstruct lsm_static_call perf_event_open[1];\n\tstruct lsm_static_call perf_event_alloc[1];\n\tstruct lsm_static_call perf_event_read[1];\n\tstruct lsm_static_call perf_event_write[1];\n\tstruct lsm_static_call uring_override_creds[1];\n\tstruct lsm_static_call uring_sqpoll[1];\n\tstruct lsm_static_call uring_cmd[1];\n\tstruct lsm_static_call uring_allowed[1];\n\tstruct lsm_static_call initramfs_populated[1];\n\tstruct lsm_static_call bdev_alloc_security[1];\n\tstruct lsm_static_call bdev_free_security[1];\n\tstruct lsm_static_call bdev_setintegrity[1];\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwq_node {\n\tstruct llist_node node;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lynx_pcs {\n\tstruct phylink_pcs pcs;\n\tstruct mdio_device *mdio;\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct ma35d1_adc_clk_div {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu32 mask;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct ma35d1_clk_pll {\n\tstruct clk_hw hw;\n\tu32 id;\n\tu8 mode;\n\tvoid *ctl0_base;\n\tvoid *ctl1_base;\n\tvoid *ctl2_base;\n};\n\nstruct ma35d1_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tstruct notifier_block restart_handler;\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct mac_addr {\n\tunsigned char addr[6];\n};\n\ntypedef struct mac_addr mac_addr;\n\nstruct mac_addr___2 {\n\tu32 mac_addr_l;\n\tu32 mac_addr_u;\n};\n\nstruct mac_desc_ctx {\n\tu8 dg[16];\n};\n\nstruct mac_priv_s;\n\nstruct mac_device {\n\tvoid *vaddr;\n\tstruct device *dev;\n\tstruct resource *res;\n\tu8 addr[6];\n\tstruct fman_port *port[2];\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tphy_interface_t phy_if;\n\tbool promisc;\n\tbool allmulti;\n\tconst struct phylink_mac_ops *phylink_ops;\n\tint (*enable)(struct fman_mac___2 *);\n\tvoid (*disable)(struct fman_mac___2 *);\n\tint (*set_promisc)(struct fman_mac___2 *, bool);\n\tint (*change_addr)(struct fman_mac___2 *, u8(*)[6]);\n\tint (*set_allmulti)(struct fman_mac___2 *, bool);\n\tint (*set_tstamp)(struct fman_mac___2 *, bool);\n\tint (*set_exception)(struct fman_mac___2 *, enum fman_mac_exceptions, bool);\n\tint (*add_hash_mac_addr)(struct fman_mac___2 *, enet_addr_t *);\n\tint (*remove_hash_mac_addr)(struct fman_mac___2 *, enet_addr_t *);\n\tvoid (*get_pause_stats)(struct fman_mac___2 *, struct ethtool_pause_stats *);\n\tvoid (*get_rmon_stats)(struct fman_mac___2 *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tvoid (*get_eth_ctrl_stats)(struct fman_mac___2 *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_eth_mac_stats)(struct fman_mac___2 *, struct ethtool_eth_mac_stats *);\n\tvoid (*update_speed)(struct mac_device *, int);\n\tstruct fman_mac___2 *fman_mac;\n\tstruct mac_priv_s *priv;\n\tstruct device *fman_dev;\n\tstruct device *fman_port_devs[2];\n};\n\nstruct mac_device___3 {\n\tvoid *vaddr;\n\tstruct device *dev;\n\tstruct resource *res;\n\tu8 addr[6];\n\tstruct fman_port *port[2];\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tphy_interface_t phy_if;\n\tbool promisc;\n\tbool allmulti;\n\tconst struct phylink_mac_ops *phylink_ops;\n\tint (*enable)(struct fman_mac *);\n\tvoid (*disable)(struct fman_mac *);\n\tint (*set_promisc)(struct fman_mac *, bool);\n\tint (*change_addr)(struct fman_mac *, u8(*)[6]);\n\tint (*set_allmulti)(struct fman_mac *, bool);\n\tint (*set_tstamp)(struct fman_mac *, bool);\n\tint (*set_exception)(struct fman_mac *, enum fman_mac_exceptions, bool);\n\tint (*add_hash_mac_addr)(struct fman_mac *, enet_addr_t *);\n\tint (*remove_hash_mac_addr)(struct fman_mac *, enet_addr_t *);\n\tvoid (*get_pause_stats)(struct fman_mac *, struct ethtool_pause_stats *);\n\tvoid (*get_rmon_stats)(struct fman_mac *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tvoid (*get_eth_ctrl_stats)(struct fman_mac *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_eth_mac_stats)(struct fman_mac *, struct ethtool_eth_mac_stats *);\n\tvoid (*update_speed)(struct mac_device___3 *, int);\n\tstruct fman_mac *fman_mac;\n\tstruct mac_priv_s *priv;\n\tstruct device *fman_dev;\n\tstruct device *fman_port_devs[2];\n};\n\nstruct mac_device___2 {\n\tvoid *vaddr;\n\tstruct device *dev;\n\tstruct resource *res;\n\tu8 addr[6];\n\tstruct fman_port *port[2];\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tphy_interface_t phy_if;\n\tbool promisc;\n\tbool allmulti;\n\tconst struct phylink_mac_ops *phylink_ops;\n\tint (*enable)(struct fman_mac___3 *);\n\tvoid (*disable)(struct fman_mac___3 *);\n\tint (*set_promisc)(struct fman_mac___3 *, bool);\n\tint (*change_addr)(struct fman_mac___3 *, u8(*)[6]);\n\tint (*set_allmulti)(struct fman_mac___3 *, bool);\n\tint (*set_tstamp)(struct fman_mac___3 *, bool);\n\tint (*set_exception)(struct fman_mac___3 *, enum fman_mac_exceptions, bool);\n\tint (*add_hash_mac_addr)(struct fman_mac___3 *, enet_addr_t *);\n\tint (*remove_hash_mac_addr)(struct fman_mac___3 *, enet_addr_t *);\n\tvoid (*get_pause_stats)(struct fman_mac___3 *, struct ethtool_pause_stats *);\n\tvoid (*get_rmon_stats)(struct fman_mac___3 *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tvoid (*get_eth_ctrl_stats)(struct fman_mac___3 *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_eth_mac_stats)(struct fman_mac___3 *, struct ethtool_eth_mac_stats *);\n\tvoid (*update_speed)(struct mac_device___2 *, int);\n\tstruct fman_mac___3 *fman_mac;\n\tstruct mac_priv_s *priv;\n\tstruct device *fman_dev;\n\tstruct device *fman_port_devs[2];\n};\n\nstruct mac_info;\n\nstruct mac_driver {\n\tvoid (*mac_init)(void *);\n\tvoid (*mac_free)(void *);\n\tvoid (*mac_enable)(void *, enum mac_commom_mode);\n\tvoid (*mac_disable)(void *, enum mac_commom_mode);\n\tvoid (*set_mac_addr)(void *, const char *);\n\tint (*adjust_link)(void *, enum mac_speed, u32);\n\tbool (*need_adjust_link)(void *, enum mac_speed, int);\n\tvoid (*set_an_mode)(void *, u8);\n\tint (*config_loopback)(void *, enum hnae_loop, u8);\n\tvoid (*config_max_frame_length)(void *, u16);\n\tvoid (*config_pad_and_crc)(void *, u8);\n\tvoid (*set_tx_auto_pause_frames)(void *, u16);\n\tvoid (*set_promiscuous)(void *, u8);\n\tvoid (*mac_pausefrm_cfg)(void *, u32, u32);\n\tvoid (*autoneg_stat)(void *, u32 *);\n\tint (*set_pause_enable)(void *, u32, u32);\n\tvoid (*get_pause_enable)(void *, u32 *, u32 *);\n\tvoid (*get_link_status)(void *, u32 *);\n\tvoid (*get_regs)(void *, void *);\n\tint (*get_regs_count)(void);\n\tvoid (*get_strings)(u32, u8 **);\n\tint (*get_sset_count)(int);\n\tvoid (*get_ethtool_stats)(void *, u64 *);\n\tvoid (*get_info)(void *, struct mac_info *);\n\tvoid (*update_stats)(void *);\n\tint (*wait_fifo_clean)(void *);\n\tenum mac_mode mac_mode;\n\tu8 mac_id;\n\tstruct hns_mac_cb *mac_cb;\n\tu8 *io_base;\n\tunsigned int mac_en_flg;\n\tunsigned int virt_dev_num;\n\tstruct device *dev;\n};\n\nstruct mac_info {\n\tu16 speed;\n\tu8 duplex;\n\tu8 auto_neg;\n\tenum hnae_loop loop_mode;\n\tu8 tx_pause_en;\n\tu8 tx_pause_time;\n\tu8 rx_pause_en;\n\tu8 pad_and_crc_en;\n\tu8 promiscuous_en;\n\tu8 port_en;\n};\n\nstruct mac_params {\n\tchar addr[6];\n\tu8 *vaddr;\n\tstruct device *dev;\n\tu8 mac_id;\n\tenum mac_mode mac_mode;\n};\n\nstruct mac_priv_s {\n\tu8 cell_index;\n\tstruct fman *fman;\n\tstruct platform_device *eth_dev;\n\tu16 speed;\n};\n\nstruct mac_stats_string {\n\tconst char desc[32];\n\tlong unsigned int offset;\n};\n\nstruct mac_tfm_ctx {\n\tstruct crypto_aes_ctx key;\n\tlong: 0;\n\tu8 consts[0];\n};\n\nstruct queue_stats {\n\tunion {\n\t\tlong unsigned int first;\n\t\tlong unsigned int rx_packets;\n\t};\n\tlong unsigned int rx_bytes;\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_packets;\n\tlong unsigned int tx_bytes;\n\tlong unsigned int tx_dropped;\n};\n\nstruct macb;\n\nstruct macb_dma_desc;\n\nstruct macb_tx_skb;\n\nstruct macb_queue {\n\tstruct macb *bp;\n\tint irq;\n\tunsigned int ISR;\n\tunsigned int IER;\n\tunsigned int IDR;\n\tunsigned int IMR;\n\tunsigned int TBQP;\n\tunsigned int RBQS;\n\tunsigned int RBQP;\n\tunsigned int ENST_START_TIME;\n\tunsigned int ENST_ON_TIME;\n\tunsigned int ENST_OFF_TIME;\n\tspinlock_t tx_ptr_lock;\n\tunsigned int tx_head;\n\tunsigned int tx_tail;\n\tstruct macb_dma_desc *tx_ring;\n\tstruct macb_tx_skb *tx_skb;\n\tdma_addr_t tx_ring_dma;\n\tstruct work_struct tx_error_task;\n\tbool txubr_pending;\n\tstruct napi_struct napi_tx;\n\tdma_addr_t rx_ring_dma;\n\tdma_addr_t rx_buffers_dma;\n\tunsigned int rx_tail;\n\tunsigned int rx_prepared_head;\n\tstruct macb_dma_desc *rx_ring;\n\tstruct sk_buff **rx_skbuff;\n\tvoid *rx_buffers;\n\tstruct napi_struct napi_rx;\n\tstruct queue_stats stats;\n};\n\nstruct macb_stats {\n\tu64 rx_pause_frames;\n\tu64 tx_ok;\n\tu64 tx_single_cols;\n\tu64 tx_multiple_cols;\n\tu64 rx_ok;\n\tu64 rx_fcs_errors;\n\tu64 rx_align_errors;\n\tu64 tx_deferred;\n\tu64 tx_late_cols;\n\tu64 tx_excessive_cols;\n\tu64 tx_underruns;\n\tu64 tx_carrier_errors;\n\tu64 rx_resource_errors;\n\tu64 rx_overruns;\n\tu64 rx_symbol_errors;\n\tu64 rx_oversize_pkts;\n\tu64 rx_jabbers;\n\tu64 rx_undersize_pkts;\n\tu64 sqe_test_errors;\n\tu64 rx_length_mismatch;\n\tu64 tx_pause_frames;\n};\n\nstruct macb_or_gem_ops {\n\tint (*mog_alloc_rx_buffers)(struct macb *);\n\tvoid (*mog_free_rx_buffers)(struct macb *);\n\tvoid (*mog_init_rings)(struct macb *);\n\tint (*mog_rx)(struct macb_queue *, struct napi_struct *, int);\n};\n\nstruct macb_tx_skb {\n\tstruct sk_buff *skb;\n\tdma_addr_t mapping;\n\tsize_t size;\n\tbool mapped_as_page;\n};\n\nstruct tsu_incr {\n\tu32 sub_ns;\n\tu32 ns;\n};\n\nstruct macb_pm_data {\n\tu32 scrt2;\n\tu32 usrio;\n};\n\nstruct macb_ptp_info;\n\nstruct macb_usrio_config;\n\nstruct macb {\n\tvoid *regs;\n\tbool native_io;\n\tu32 (*macb_reg_readl)(struct macb *, int);\n\tvoid (*macb_reg_writel)(struct macb *, int, u32);\n\tstruct macb_dma_desc *rx_ring_tieoff;\n\tdma_addr_t rx_ring_tieoff_dma;\n\tsize_t rx_buffer_size;\n\tunsigned int rx_ring_size;\n\tunsigned int tx_ring_size;\n\tunsigned int num_queues;\n\tstruct macb_queue queues[8];\n\tspinlock_t lock;\n\tstruct platform_device *pdev;\n\tstruct clk *pclk;\n\tstruct clk *hclk;\n\tstruct clk *tx_clk;\n\tstruct clk *rx_clk;\n\tstruct clk *tsu_clk;\n\tstruct net_device *dev;\n\tspinlock_t stats_lock;\n\tunion {\n\t\tstruct macb_stats macb;\n\t\tstruct gem_stats gem;\n\t} hw_stats;\n\tstruct macb_or_gem_ops macbgem_ops;\n\tstruct mii_bus *mii_bus;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tstruct phylink_pcs phylink_usx_pcs;\n\tstruct phylink_pcs phylink_sgmii_pcs;\n\tu32 caps;\n\tunsigned int dma_burst_length;\n\tphy_interface_t phy_interface;\n\tstruct macb_tx_skb rm9200_txq[2];\n\tunsigned int max_tx_length;\n\tu64 ethtool_stats[91];\n\tunsigned int rx_frm_len_mask;\n\tunsigned int jumbo_max_len;\n\tu32 wol;\n\tu32 wolopts;\n\tu32 rx_watermark;\n\tstruct macb_ptp_info *ptp_info;\n\tstruct phy *phy;\n\tspinlock_t tsu_clk_lock;\n\tunsigned int tsu_rate;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct tsu_incr tsu_incr;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tstruct ethtool_rx_fs_list rx_fs_list;\n\tspinlock_t rx_fs_lock;\n\tunsigned int max_tuples;\n\tstruct work_struct hresp_err_bh_work;\n\tint rx_bd_rd_prefetch;\n\tint tx_bd_rd_prefetch;\n\tu32 rx_intr_mask;\n\tstruct macb_pm_data pm_data;\n\tconst struct macb_usrio_config *usrio;\n};\n\nstruct macb_config {\n\tu32 caps;\n\tunsigned int dma_burst_length;\n\tint (*clk_init)(struct platform_device *, struct clk **, struct clk **, struct clk **, struct clk **, struct clk **);\n\tint (*init)(struct platform_device *);\n\tunsigned int max_tx_length;\n\tint jumbo_max_len;\n\tconst struct macb_usrio_config *usrio;\n};\n\nstruct macb_dma_desc {\n\tu32 addr;\n\tu32 ctrl;\n};\n\nstruct macb_dma_desc_64 {\n\tu32 addrh;\n\tu32 resvd;\n};\n\nstruct macb_dma_desc_ptp {\n\tu32 ts_1;\n\tu32 ts_2;\n};\n\nstruct macb_platform_data {\n\tstruct clk *pclk;\n\tstruct clk *hclk;\n};\n\nstruct macb_ptp_info {\n\tvoid (*ptp_init)(struct net_device *);\n\tvoid (*ptp_remove)(struct net_device *);\n\ts32 (*get_ptp_max_adj)(void);\n\tunsigned int (*get_tsu_rate)(struct macb *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tint (*get_hwtst)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*set_hwtst)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct macb_queue_enst_config {\n\tu32 start_time_mask;\n\tu32 on_time_bytes;\n\tu32 off_time_bytes;\n\tu8 queue_id;\n};\n\nstruct macb_usrio_config {\n\tu32 mii;\n\tu32 rmii;\n\tu32 rgmii;\n\tu32 refclk;\n\tu32 hdfctlen;\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct mafield {\n\tconst char *prefix;\n\tint field;\n};\n\nstruct maft_cfge_data {\n\t__le16 si_bitmap;\n\t__le16 resv;\n};\n\nstruct maft_keye_data {\n\tu8 mac_addr[6];\n\t__le16 resv;\n};\n\nstruct maft_entry_data {\n\tstruct maft_keye_data keye;\n\tstruct maft_cfge_data cfge;\n};\n\nstruct ntmp_cmn_req_data {\n\t__le16 update_act;\n\tu8 dbg_opt;\n\tu8 tblv_qact;\n};\n\nstruct ntmp_req_by_eid {\n\tstruct ntmp_cmn_req_data crd;\n\t__le32 entry_id;\n};\n\nstruct maft_req_add {\n\tstruct ntmp_req_by_eid rbe;\n\tstruct maft_keye_data keye;\n\tstruct maft_cfge_data cfge;\n};\n\nstruct maft_resp_query {\n\t__le32 entry_id;\n\tstruct maft_keye_data keye;\n\tstruct maft_cfge_data cfge;\n};\n\nstruct map_balloon_pages {\n\txen_pfn_t *pfns;\n\tunsigned int idx;\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct map_info___2 {\n\tstruct map_info___2 *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct mtd_chip_driver;\n\nstruct map_info {\n\tconst char *name;\n\tlong unsigned int size;\n\tresource_size_t phys;\n\tvoid *virt;\n\tvoid *cached;\n\tint swap;\n\tint bankwidth;\n\tmap_word (*read)(struct map_info *, long unsigned int);\n\tvoid (*copy_from)(struct map_info *, void *, long unsigned int, ssize_t);\n\tvoid (*write)(struct map_info *, const map_word, long unsigned int);\n\tvoid (*copy_to)(struct map_info *, long unsigned int, const void *, ssize_t);\n\tvoid (*inval_cache)(struct map_info *, long unsigned int, ssize_t);\n\tvoid (*set_vpp)(struct map_info *, int);\n\tlong unsigned int pfow_base;\n\tlong unsigned int map_priv_1;\n\tlong unsigned int map_priv_2;\n\tstruct device_node *device_node;\n\tvoid *fldrv_priv;\n\tstruct mtd_chip_driver *fldrv;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct xenbus_map_node;\n\nstruct map_ring_valloc {\n\tstruct xenbus_map_node *node;\n\tlong unsigned int addrs[16];\n\tphys_addr_t phys_addrs[16];\n\tstruct gnttab_map_grant_ref map[16];\n\tstruct gnttab_unmap_grant_ref unmap[16];\n\tunsigned int idx;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[9];\n\tvoid *slot[10];\n\tlong unsigned int gap[10];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[33];\n\tunion {\n\t\tstruct maple_enode *slot[34];\n\t\tstruct {\n\t\t\tlong unsigned int padding[21];\n\t\t\tlong unsigned int gap[21];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[15];\n\tunion {\n\t\tvoid *slot[16];\n\t\tstruct {\n\t\t\tvoid *pad[15];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[31];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct marvell_hw_ecc_layout {\n\tint writesize;\n\tint chunk;\n\tint strength;\n\tint nchunks;\n\tint full_chunk_cnt;\n\tint data_bytes;\n\tint spare_bytes;\n\tint ecc_bytes;\n\tint last_data_bytes;\n\tint last_spare_bytes;\n\tint last_ecc_bytes;\n};\n\nstruct marvell_nand_chip_sel {\n\tunsigned int cs;\n\tu32 ndcb0_csel;\n\tunsigned int rb;\n};\n\nstruct marvell_nand_chip {\n\tstruct nand_chip chip;\n\tstruct list_head node;\n\tconst struct marvell_hw_ecc_layout *layout;\n\tu32 ndcr;\n\tu32 ndtr0;\n\tu32 ndtr1;\n\tint addr_cyc;\n\tint selected_die;\n\tunsigned int nsels;\n\tstruct marvell_nand_chip_sel sels[0];\n};\n\nstruct marvell_nfc_caps;\n\nstruct marvell_nfc {\n\tstruct nand_controller controller;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct clk *core_clk;\n\tstruct clk *reg_clk;\n\tstruct completion complete;\n\tlong unsigned int assigned_cs;\n\tstruct list_head chips;\n\tstruct nand_chip *selected_chip;\n\tconst struct marvell_nfc_caps *caps;\n\tbool use_dma;\n\tstruct dma_chan *dma_chan;\n\tu8 *dma_buf;\n};\n\nstruct marvell_nfc_caps {\n\tunsigned int max_cs_nb;\n\tunsigned int max_rb_nb;\n\tbool need_system_controller;\n\tbool legacy_of_bindings;\n\tbool is_nfcv2;\n\tbool use_dma;\n\tunsigned int max_mode_number;\n};\n\nstruct nand_op_instr;\n\nstruct marvell_nfc_op {\n\tu32 ndcb[4];\n\tunsigned int cle_ale_delay_ns;\n\tunsigned int rdy_timeout_ms;\n\tunsigned int rdy_delay_ns;\n\tunsigned int data_delay_ns;\n\tunsigned int data_instr_idx;\n\tconst struct nand_op_instr *data_instr;\n};\n\nstruct marvell_nfc_timings {\n\tunsigned int tRP;\n\tunsigned int tRH;\n\tunsigned int tWP;\n\tunsigned int tWH;\n\tunsigned int tCS;\n\tunsigned int tCH;\n\tunsigned int tADL;\n\tunsigned int tAR;\n\tunsigned int tWHR;\n\tunsigned int tRHW;\n\tunsigned int tR;\n};\n\nstruct match {\n\tu32 mode;\n\tu32 area;\n\tu8 depth;\n};\n\nstruct match_chip_info {\n\tvoid (*init_func)(struct brcm_usb_init_params *);\n\tu8 required_regs[7];\n\tu8 optional_reg;\n};\n\nstruct tee_ioctl_version_data;\n\nstruct match_dev_data {\n\tstruct tee_ioctl_version_data *vers;\n\tconst void *data;\n\tint (*match)(struct tee_ioctl_version_data *, const void *);\n};\n\nstruct match_ids_walk_data {\n\tstruct acpi_device_id *ids;\n\tstruct acpi_device *adev;\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct matrix_keymap_data {\n\tconst uint32_t *keymap;\n\tunsigned int keymap_size;\n};\n\nstruct max732x_chip {\n\tstruct gpio_chip gpio_chip;\n\tstruct i2c_client *client;\n\tstruct i2c_client *client_dummy;\n\tstruct i2c_client *client_group_a;\n\tstruct i2c_client *client_group_b;\n\tunsigned int mask_group_a;\n\tunsigned int dir_input;\n\tunsigned int dir_output;\n\tstruct mutex lock;\n\tuint8_t reg_out[2];\n};\n\nstruct max732x_platform_data {\n\tunsigned int gpio_base;\n};\n\nstruct max77620_chip {\n\tstruct device *dev;\n\tstruct regmap *rmap;\n\tint chip_irq;\n\tenum max77620_chip_id chip_id;\n\tbool sleep_enable;\n\tbool enable_global_lpm;\n\tint shutdown_fps_period[3];\n\tint suspend_fps_period[3];\n\tstruct regmap_irq_chip_data *top_irq_data;\n\tstruct regmap_irq_chip_data *gpio_irq_data;\n};\n\nstruct max77620_fps_config {\n\tint active_fps_src;\n\tint active_power_up_slots;\n\tint active_power_down_slots;\n\tint suspend_fps_src;\n\tint suspend_power_up_slots;\n\tint suspend_power_down_slots;\n};\n\nstruct max77620_gpio {\n\tstruct gpio_chip gpio_chip;\n\tstruct regmap *rmap;\n\tstruct device *dev;\n\tstruct mutex buslock;\n\tunsigned int irq_type[8];\n\tbool irq_enabled[8];\n};\n\nstruct max77620_pin_info {\n\tenum max77620_pin_ppdrv drv_type;\n};\n\nstruct max77620_pin_function;\n\nstruct max77620_pingroup;\n\nstruct max77620_pctrl_info {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct regmap *rmap;\n\tconst struct max77620_pin_function *functions;\n\tunsigned int num_functions;\n\tconst struct max77620_pingroup *pin_groups;\n\tint num_pin_groups;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int num_pins;\n\tstruct max77620_pin_info pin_info[8];\n\tstruct max77620_fps_config fps_config[8];\n};\n\nstruct max77620_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n\tint mux_option;\n};\n\nstruct max77620_pingroup {\n\tconst char *name;\n\tconst unsigned int pins[1];\n\tunsigned int npins;\n\tenum max77620_alternate_pinmux_option alt_option;\n};\n\nstruct max77620_regulator_pdata {\n\tint active_fps_src;\n\tint active_fps_pd_slot;\n\tint active_fps_pu_slot;\n\tint suspend_fps_src;\n\tint suspend_fps_pd_slot;\n\tint suspend_fps_pu_slot;\n\tint current_mode;\n\tint power_ok;\n\tint ramp_rate_setting;\n};\n\nstruct max77620_regulator_info;\n\nstruct max77620_regulator {\n\tstruct device *dev;\n\tstruct regmap *rmap;\n\tstruct max77620_regulator_info *rinfo[14];\n\tstruct max77620_regulator_pdata reg_pdata[14];\n\tint enable_power_mode[14];\n\tint current_power_mode[14];\n\tint active_fps_src[14];\n};\n\nstruct max77620_regulator_info {\n\tu8 type;\n\tu8 fps_addr;\n\tu8 volt_addr;\n\tu8 cfg_addr;\n\tu8 power_mode_mask;\n\tu8 power_mode_shift;\n\tu8 remote_sense_addr;\n\tu8 remote_sense_mask;\n\tstruct regulator_desc desc;\n};\n\nstruct max77686_rtc_driver_data {\n\tlong unsigned int delay;\n\tu8 mask;\n\tconst unsigned int *map;\n\tbool alarm_enable_reg;\n\tint rtc_i2c_addr;\n\tbool rtc_irq_from_platform;\n\tint alarm_pending_status_reg;\n\tconst struct regmap_irq_chip *rtc_irq_chip;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct max77686_rtc_info {\n\tstruct device *dev;\n\tstruct rtc_device *rtc_dev;\n\tstruct mutex lock;\n\tstruct regmap *regmap;\n\tstruct regmap *rtc_regmap;\n\tconst struct max77686_rtc_driver_data *drv_data;\n\tstruct regmap_irq_chip_data *rtc_irq_data;\n\tint rtc_irq;\n\tint virq;\n};\n\nstruct regulator_ops {\n\tint (*list_voltage)(struct regulator_dev *, unsigned int);\n\tint (*set_voltage)(struct regulator_dev *, int, int, unsigned int *);\n\tint (*map_voltage)(struct regulator_dev *, int, int);\n\tint (*set_voltage_sel)(struct regulator_dev *, unsigned int);\n\tint (*get_voltage)(struct regulator_dev *);\n\tint (*get_voltage_sel)(struct regulator_dev *);\n\tint (*set_current_limit)(struct regulator_dev *, int, int);\n\tint (*get_current_limit)(struct regulator_dev *);\n\tint (*set_input_current_limit)(struct regulator_dev *, int);\n\tint (*set_over_current_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_over_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_under_voltage_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_thermal_protection)(struct regulator_dev *, int, int, bool);\n\tint (*set_active_discharge)(struct regulator_dev *, bool);\n\tint (*enable)(struct regulator_dev *);\n\tint (*disable)(struct regulator_dev *);\n\tint (*is_enabled)(struct regulator_dev *);\n\tint (*set_mode)(struct regulator_dev *, unsigned int);\n\tunsigned int (*get_mode)(struct regulator_dev *);\n\tint (*get_error_flags)(struct regulator_dev *, unsigned int *);\n\tint (*enable_time)(struct regulator_dev *);\n\tint (*set_ramp_delay)(struct regulator_dev *, int);\n\tint (*set_voltage_time)(struct regulator_dev *, int, int);\n\tint (*set_voltage_time_sel)(struct regulator_dev *, unsigned int, unsigned int);\n\tint (*set_soft_start)(struct regulator_dev *);\n\tint (*get_status)(struct regulator_dev *);\n\tunsigned int (*get_optimum_mode)(struct regulator_dev *, int, int, int);\n\tint (*set_load)(struct regulator_dev *, int);\n\tint (*set_bypass)(struct regulator_dev *, bool);\n\tint (*get_bypass)(struct regulator_dev *, bool *);\n\tint (*set_suspend_voltage)(struct regulator_dev *, int);\n\tint (*set_suspend_enable)(struct regulator_dev *);\n\tint (*set_suspend_disable)(struct regulator_dev *);\n\tint (*set_suspend_mode)(struct regulator_dev *, unsigned int);\n\tint (*resume)(struct regulator_dev *);\n\tint (*set_pull_down)(struct regulator_dev *);\n};\n\nstruct max8973_chip {\n\tstruct device *dev;\n\tstruct regulator_desc desc;\n\tstruct regmap *regmap;\n\tbool enable_external_control;\n\tstruct gpio_desc *dvs_gpiod;\n\tint lru_index[2];\n\tint curr_vout_val[2];\n\tint curr_vout_reg;\n\tint curr_gpio_val;\n\tstruct regulator_ops ops;\n\tenum device_id id;\n\tint junction_temp_warning;\n\tint irq;\n\tstruct thermal_zone_device *tz_device;\n};\n\nstruct max8973_regulator_platform_data {\n\tstruct regulator_init_data *reg_init_data;\n\tlong unsigned int control_flags;\n\tlong unsigned int junction_temp_warning;\n\tbool enable_ext_control;\n\tunsigned int dvs_def_state: 1;\n};\n\nstruct mb86s70_gpio_chip {\n\tstruct gpio_chip gc;\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker *c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tlong unsigned int e_flags;\n\tu64 e_value;\n};\n\nstruct mbi_range {\n\tu32 spi_start;\n\tu32 nr_spis;\n\tlong unsigned int *bm;\n};\n\nstruct mbigen_device {\n\tstruct platform_device *pdev;\n\tvoid *base;\n};\n\nstruct mbox_chan_ops {\n\tint (*send_data)(struct mbox_chan *, void *);\n\tint (*flush)(struct mbox_chan *, long unsigned int);\n\tint (*startup)(struct mbox_chan *);\n\tvoid (*shutdown)(struct mbox_chan *);\n\tbool (*last_tx_done)(struct mbox_chan *);\n\tbool (*peek_data)(struct mbox_chan *);\n};\n\nstruct mbus_dram_window {\n\tu8 cs_index;\n\tu8 mbus_attr;\n\tu64 base;\n\tu64 size;\n};\n\nstruct mbus_dram_target_info {\n\tu8 mbus_dram_target_id;\n\tint num_cs;\n\tstruct mbus_dram_window cs[4];\n};\n\nstruct mc_cmd_header {\n\tu8 src_id;\n\tu8 flags_hw;\n\tu8 status;\n\tu8 flags_sw;\n\t__le16 token;\n\t__le16 cmd_id;\n};\n\nstruct mc_rsp_api_ver {\n\t__le16 major_ver;\n\t__le16 minor_ver;\n};\n\nstruct mc_rsp_create {\n\t__le32 object_id;\n};\n\nstruct mc_subled {\n\tunsigned int color_index;\n\tunsigned int brightness;\n\tunsigned int intensity;\n\tunsigned int channel;\n};\n\nstruct mcfg_entry {\n\tstruct list_head list;\n\tphys_addr_t addr;\n\tu16 segment;\n\tu8 bus_start;\n\tu8 bus_end;\n};\n\nstruct pci_ecam_ops;\n\nstruct mcfg_fixup {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n\tu16 segment;\n\tstruct resource bus_range;\n\tconst struct pci_ecam_ops *ops;\n\tstruct resource cfgres;\n};\n\nstruct mcs_spinlock {\n\tstruct mcs_spinlock *next;\n\tint locked;\n\tint count;\n};\n\nstruct mct_clock_event_device {\n\tstruct clock_event_device evt;\n\tlong unsigned int base;\n\tchar name[11];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mctrl_gpios {\n\tstruct uart_port *port;\n\tstruct gpio_desc *gpio[6];\n\tint irq[6];\n\tunsigned int mctrl_prev;\n\tbool mctrl_on;\n};\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n\tvoid (*shutdown)(struct mdio_device *);\n};\n\nstruct tgec_mdio_controller;\n\nstruct mdio_fsl_priv {\n\tstruct tgec_mdio_controller *mdio_base;\n\tstruct clk *enet_clk;\n\tu32 mdc_freq;\n\tbool is_little_endian;\n\tbool has_a009885;\n\tbool has_a011043;\n};\n\nstruct mdio_gpio_info {\n\tstruct mdiobb_ctrl ctrl;\n\tstruct gpio_desc *mdc;\n\tstruct gpio_desc *mdio;\n\tstruct gpio_desc *mdo;\n};\n\nstruct mdio_gpio_platform_data {\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n};\n\nstruct mdio_mux_parent_bus;\n\nstruct mdio_mux_child_bus {\n\tstruct mii_bus *mii_bus;\n\tstruct mdio_mux_parent_bus *parent;\n\tstruct mdio_mux_child_bus *next;\n\tint bus_number;\n};\n\nstruct mdio_mux_mmioreg_state {\n\tvoid *mux_handle;\n\tphys_addr_t phys;\n\tunsigned int iosize;\n\tunsigned int mask;\n};\n\nstruct mux_control;\n\nstruct mdio_mux_multiplexer_state {\n\tstruct mux_control *muxc;\n\tbool do_deselect;\n\tvoid *mux_handle;\n};\n\nstruct mdio_mux_parent_bus {\n\tstruct mii_bus *mii_bus;\n\tint current_child;\n\tint parent_id;\n\tvoid *switch_data;\n\tint (*switch_fn)(int, int, void *);\n\tstruct mdio_mux_child_bus *children;\n};\n\nstruct mdiobb_ops {\n\tstruct module *owner;\n\tvoid (*set_mdc)(struct mdiobb_ctrl *, int);\n\tvoid (*set_mdio_dir)(struct mdiobb_ctrl *, int);\n\tvoid (*set_mdio_data)(struct mdiobb_ctrl *, int);\n\tint (*get_mdio_data)(struct mdiobb_ctrl *);\n};\n\nstruct mdiobus_devres {\n\tstruct mii_bus *mii;\n};\n\nstruct regulator_coupler {\n\tstruct list_head list;\n\tint (*attach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*detach_regulator)(struct regulator_coupler *, struct regulator_dev *);\n\tint (*balance_voltage)(struct regulator_coupler *, struct regulator_dev *, suspend_state_t);\n};\n\nstruct mediatek_regulator_coupler {\n\tstruct regulator_coupler coupler;\n\tstruct regulator_dev *vsram_rdev;\n};\n\nstruct megasas_abort_frame {\n\tu8 cmd;\n\tu8 reserved_0;\n\tu8 cmd_status;\n\tu8 reserved_1;\n\t__le32 reserved_2;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 reserved_3;\n\t__le32 reserved_4;\n\t__le32 abort_context;\n\t__le32 pad_1;\n\t__le32 abort_mfi_phys_addr_lo;\n\t__le32 abort_mfi_phys_addr_hi;\n\t__le32 reserved_5[6];\n};\n\nstruct megasas_aen {\n\tu16 host_no;\n\tu16 __pad1;\n\tu32 seq_num;\n\tu32 class_locale_word;\n};\n\nstruct megasas_instance;\n\nstruct megasas_aen_event {\n\tstruct delayed_work hotplug_work;\n\tstruct megasas_instance *instance;\n};\n\nunion megasas_frame;\n\nstruct megasas_cmd {\n\tunion megasas_frame *frame;\n\tdma_addr_t frame_phys_addr;\n\tu8 *sense;\n\tdma_addr_t sense_phys_addr;\n\tu32 index;\n\tu8 sync_cmd;\n\tu8 cmd_status_drv;\n\tu8 abort_aen;\n\tu8 retry_for_fw_reset;\n\tstruct list_head list;\n\tstruct scsi_cmnd *scmd;\n\tu8 flags;\n\tstruct megasas_instance *instance;\n\tunion {\n\t\tstruct {\n\t\t\tu16 smid;\n\t\t\tu16 resvd;\n\t\t} context;\n\t\tu32 frame_count;\n\t};\n};\n\nstruct megasas_cmd_fusion {\n\tstruct MPI2_RAID_SCSI_IO_REQUEST *io_request;\n\tdma_addr_t io_request_phys_addr;\n\tunion MPI2_SGE_IO_UNION *sg_frame;\n\tdma_addr_t sg_frame_phys_addr;\n\tu8 *sense;\n\tdma_addr_t sense_phys_addr;\n\tstruct list_head list;\n\tstruct scsi_cmnd *scmd;\n\tstruct megasas_instance *instance;\n\tu8 retry_for_fw_reset;\n\tunion MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;\n\tu32 sync_cmd_idx;\n\tu32 index;\n\tu8 pd_r1_lb;\n\tstruct completion done;\n\tu8 pd_interface;\n\tu16 r1_alt_dev_handle;\n\tbool cmd_completed;\n};\n\nstruct megasas_cmd_priv {\n\tvoid *cmd_priv;\n\tu8 status;\n};\n\nstruct megasas_ctrl_prop {\n\tu16 seq_num;\n\tu16 pred_fail_poll_interval;\n\tu16 intr_throttle_count;\n\tu16 intr_throttle_timeouts;\n\tu8 rebuild_rate;\n\tu8 patrol_read_rate;\n\tu8 bgi_rate;\n\tu8 cc_rate;\n\tu8 recon_rate;\n\tu8 cache_flush_interval;\n\tu8 spinup_drv_count;\n\tu8 spinup_delay;\n\tu8 cluster_enable;\n\tu8 coercion_mode;\n\tu8 alarm_enable;\n\tu8 disable_auto_rebuild;\n\tu8 disable_battery_warn;\n\tu8 ecc_bucket_size;\n\tu16 ecc_bucket_leak_rate;\n\tu8 restore_hotspare_on_insertion;\n\tu8 expose_encl_devices;\n\tu8 maintainPdFailHistory;\n\tu8 disallowHostRequestReordering;\n\tu8 abortCCOnError;\n\tu8 loadBalanceMode;\n\tu8 disableAutoDetectBackplane;\n\tu8 snapVDSpace;\n\tstruct {\n\t\tu32 copyBackDisabled: 1;\n\t\tu32 SMARTerEnabled: 1;\n\t\tu32 prCorrectUnconfiguredAreas: 1;\n\t\tu32 useFdeOnly: 1;\n\t\tu32 disableNCQ: 1;\n\t\tu32 SSDSMARTerEnabled: 1;\n\t\tu32 SSDPatrolReadEnabled: 1;\n\t\tu32 enableSpinDownUnconfigured: 1;\n\t\tu32 autoEnhancedImport: 1;\n\t\tu32 enableSecretKeyControl: 1;\n\t\tu32 disableOnlineCtrlReset: 1;\n\t\tu32 allowBootWithPinnedCache: 1;\n\t\tu32 disableSpinDownHS: 1;\n\t\tu32 enableJBOD: 1;\n\t\tu32 reserved: 18;\n\t} OnOffProperties;\n\tunion {\n\t\tu8 autoSnapVDSpace;\n\t\tu8 viewSpace;\n\t\tstruct {\n\t\t\tu16 reserved1: 4;\n\t\t\tu16 enable_snap_dump: 1;\n\t\t\tu16 reserved2: 1;\n\t\t\tu16 enable_fw_dev_list: 1;\n\t\t\tu16 reserved3: 9;\n\t\t} on_off_properties2;\n\t};\n\t__le16 spinDownTime;\n\tu8 reserved[24];\n};\n\nstruct megasas_ctrl_info {\n\tstruct {\n\t\t__le16 vendor_id;\n\t\t__le16 device_id;\n\t\t__le16 sub_vendor_id;\n\t\t__le16 sub_device_id;\n\t\tu8 reserved[24];\n\t} pci;\n\tstruct {\n\t\tu8 PCIX: 1;\n\t\tu8 PCIE: 1;\n\t\tu8 iSCSI: 1;\n\t\tu8 SAS_3G: 1;\n\t\tu8 SRIOV: 1;\n\t\tu8 reserved_0: 3;\n\t\tu8 reserved_1[6];\n\t\tu8 port_count;\n\t\tu64 port_addr[8];\n\t} host_interface;\n\tstruct {\n\t\tu8 SPI: 1;\n\t\tu8 SAS_3G: 1;\n\t\tu8 SATA_1_5G: 1;\n\t\tu8 SATA_3G: 1;\n\t\tu8 reserved_0: 4;\n\t\tu8 reserved_1[6];\n\t\tu8 port_count;\n\t\tu64 port_addr[8];\n\t} device_interface;\n\t__le32 image_check_word;\n\t__le32 image_component_count;\n\tstruct {\n\t\tchar name[8];\n\t\tchar version[32];\n\t\tchar build_date[16];\n\t\tchar built_time[16];\n\t} image_component[8];\n\t__le32 pending_image_component_count;\n\tstruct {\n\t\tchar name[8];\n\t\tchar version[32];\n\t\tchar build_date[16];\n\t\tchar build_time[16];\n\t} pending_image_component[8];\n\tu8 max_arms;\n\tu8 max_spans;\n\tu8 max_arrays;\n\tu8 max_lds;\n\tchar product_name[80];\n\tchar serial_no[32];\n\tstruct {\n\t\tu32 bbu: 1;\n\t\tu32 alarm: 1;\n\t\tu32 nvram: 1;\n\t\tu32 uart: 1;\n\t\tu32 reserved: 28;\n\t} hw_present;\n\t__le32 current_fw_time;\n\t__le16 max_concurrent_cmds;\n\t__le16 max_sge_count;\n\t__le32 max_request_size;\n\t__le16 ld_present_count;\n\t__le16 ld_degraded_count;\n\t__le16 ld_offline_count;\n\t__le16 pd_present_count;\n\t__le16 pd_disk_present_count;\n\t__le16 pd_disk_pred_failure_count;\n\t__le16 pd_disk_failed_count;\n\t__le16 nvram_size;\n\t__le16 memory_size;\n\t__le16 flash_size;\n\t__le16 mem_correctable_error_count;\n\t__le16 mem_uncorrectable_error_count;\n\tu8 cluster_permitted;\n\tu8 cluster_active;\n\t__le16 max_strips_per_io;\n\tstruct {\n\t\tu32 raid_level_0: 1;\n\t\tu32 raid_level_1: 1;\n\t\tu32 raid_level_5: 1;\n\t\tu32 raid_level_1E: 1;\n\t\tu32 raid_level_6: 1;\n\t\tu32 reserved: 27;\n\t} raid_levels;\n\tstruct {\n\t\tu32 rbld_rate: 1;\n\t\tu32 cc_rate: 1;\n\t\tu32 bgi_rate: 1;\n\t\tu32 recon_rate: 1;\n\t\tu32 patrol_rate: 1;\n\t\tu32 alarm_control: 1;\n\t\tu32 cluster_supported: 1;\n\t\tu32 bbu: 1;\n\t\tu32 spanning_allowed: 1;\n\t\tu32 dedicated_hotspares: 1;\n\t\tu32 revertible_hotspares: 1;\n\t\tu32 foreign_config_import: 1;\n\t\tu32 self_diagnostic: 1;\n\t\tu32 mixed_redundancy_arr: 1;\n\t\tu32 global_hot_spares: 1;\n\t\tu32 reserved: 17;\n\t} adapter_operations;\n\tstruct {\n\t\tu32 read_policy: 1;\n\t\tu32 write_policy: 1;\n\t\tu32 io_policy: 1;\n\t\tu32 access_policy: 1;\n\t\tu32 disk_cache_policy: 1;\n\t\tu32 reserved: 27;\n\t} ld_operations;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t\tu8 reserved[2];\n\t} stripe_sz_ops;\n\tstruct {\n\t\tu32 force_online: 1;\n\t\tu32 force_offline: 1;\n\t\tu32 force_rebuild: 1;\n\t\tu32 reserved: 29;\n\t} pd_operations;\n\tstruct {\n\t\tu32 ctrl_supports_sas: 1;\n\t\tu32 ctrl_supports_sata: 1;\n\t\tu32 allow_mix_in_encl: 1;\n\t\tu32 allow_mix_in_ld: 1;\n\t\tu32 allow_sata_in_cluster: 1;\n\t\tu32 reserved: 27;\n\t} pd_mix_support;\n\tu8 ecc_bucket_count;\n\tu8 reserved_2[11];\n\tstruct megasas_ctrl_prop properties;\n\tchar package_version[96];\n\t__le64 deviceInterfacePortAddr2[8];\n\tu8 reserved3[128];\n\tstruct {\n\t\tu16 minPdRaidLevel_0: 4;\n\t\tu16 maxPdRaidLevel_0: 12;\n\t\tu16 minPdRaidLevel_1: 4;\n\t\tu16 maxPdRaidLevel_1: 12;\n\t\tu16 minPdRaidLevel_5: 4;\n\t\tu16 maxPdRaidLevel_5: 12;\n\t\tu16 minPdRaidLevel_1E: 4;\n\t\tu16 maxPdRaidLevel_1E: 12;\n\t\tu16 minPdRaidLevel_6: 4;\n\t\tu16 maxPdRaidLevel_6: 12;\n\t\tu16 minPdRaidLevel_10: 4;\n\t\tu16 maxPdRaidLevel_10: 12;\n\t\tu16 minPdRaidLevel_50: 4;\n\t\tu16 maxPdRaidLevel_50: 12;\n\t\tu16 minPdRaidLevel_60: 4;\n\t\tu16 maxPdRaidLevel_60: 12;\n\t\tu16 minPdRaidLevel_1E_RLQ0: 4;\n\t\tu16 maxPdRaidLevel_1E_RLQ0: 12;\n\t\tu16 minPdRaidLevel_1E0_RLQ0: 4;\n\t\tu16 maxPdRaidLevel_1E0_RLQ0: 12;\n\t\tu16 reserved[6];\n\t} pdsForRaidLevels;\n\t__le16 maxPds;\n\t__le16 maxDedHSPs;\n\t__le16 maxGlobalHSP;\n\t__le16 ddfSize;\n\tu8 maxLdsPerArray;\n\tu8 partitionsInDDF;\n\tu8 lockKeyBinding;\n\tu8 maxPITsPerLd;\n\tu8 maxViewsPerLd;\n\tu8 maxTargetId;\n\t__le16 maxBvlVdSize;\n\t__le16 maxConfigurableSSCSize;\n\t__le16 currentSSCsize;\n\tchar expanderFwVersion[12];\n\t__le16 PFKTrialTimeRemaining;\n\t__le16 cacheMemorySize;\n\tstruct {\n\t\tu32 supportPIcontroller: 1;\n\t\tu32 supportLdPIType1: 1;\n\t\tu32 supportLdPIType2: 1;\n\t\tu32 supportLdPIType3: 1;\n\t\tu32 supportLdBBMInfo: 1;\n\t\tu32 supportShieldState: 1;\n\t\tu32 blockSSDWriteCacheChange: 1;\n\t\tu32 supportSuspendResumeBGops: 1;\n\t\tu32 supportEmergencySpares: 1;\n\t\tu32 supportSetLinkSpeed: 1;\n\t\tu32 supportBootTimePFKChange: 1;\n\t\tu32 supportJBOD: 1;\n\t\tu32 disableOnlinePFKChange: 1;\n\t\tu32 supportPerfTuning: 1;\n\t\tu32 supportSSDPatrolRead: 1;\n\t\tu32 realTimeScheduler: 1;\n\t\tu32 supportResetNow: 1;\n\t\tu32 supportEmulatedDrives: 1;\n\t\tu32 headlessMode: 1;\n\t\tu32 dedicatedHotSparesLimited: 1;\n\t\tu32 supportUnevenSpans: 1;\n\t\tu32 supportPointInTimeProgress: 1;\n\t\tu32 supportDataLDonSSCArray: 1;\n\t\tu32 mpio: 1;\n\t\tu32 supportConfigAutoBalance: 1;\n\t\tu32 activePassive: 2;\n\t\tu32 reserved: 5;\n\t} adapterOperations2;\n\tu8 driverVersion[32];\n\tu8 maxDAPdCountSpinup60;\n\tu8 temperatureROC;\n\tu8 temperatureCtrl;\n\tu8 reserved4;\n\t__le16 maxConfigurablePds;\n\tu8 reserved5[2];\n\tstruct {\n\t\tu32 peerIsPresent: 1;\n\t\tu32 peerIsIncompatible: 1;\n\t\tu32 hwIncompatible: 1;\n\t\tu32 fwVersionMismatch: 1;\n\t\tu32 ctrlPropIncompatible: 1;\n\t\tu32 premiumFeatureMismatch: 1;\n\t\tu32 passive: 1;\n\t\tu32 reserved: 25;\n\t} cluster;\n\tchar clusterId[16];\n\tstruct {\n\t\tu8 maxVFsSupported;\n\t\tu8 numVFsEnabled;\n\t\tu8 requestorId;\n\t\tu8 reserved;\n\t} iov;\n\tstruct {\n\t\tu32 supportPersonalityChange: 2;\n\t\tu32 supportThermalPollInterval: 1;\n\t\tu32 supportDisableImmediateIO: 1;\n\t\tu32 supportT10RebuildAssist: 1;\n\t\tu32 supportMaxExtLDs: 1;\n\t\tu32 supportCrashDump: 1;\n\t\tu32 supportSwZone: 1;\n\t\tu32 supportDebugQueue: 1;\n\t\tu32 supportNVCacheErase: 1;\n\t\tu32 supportForceTo512e: 1;\n\t\tu32 supportHOQRebuild: 1;\n\t\tu32 supportAllowedOpsforDrvRemoval: 1;\n\t\tu32 supportDrvActivityLEDSetting: 1;\n\t\tu32 supportNVDRAM: 1;\n\t\tu32 supportForceFlash: 1;\n\t\tu32 supportDisableSESMonitoring: 1;\n\t\tu32 supportCacheBypassModes: 1;\n\t\tu32 supportSecurityonJBOD: 1;\n\t\tu32 discardCacheDuringLDDelete: 1;\n\t\tu32 supportTTYLogCompression: 1;\n\t\tu32 supportCPLDUpdate: 1;\n\t\tu32 supportDiskCacheSettingForSysPDs: 1;\n\t\tu32 supportExtendedSSCSize: 1;\n\t\tu32 useSeqNumJbodFP: 1;\n\t\tu32 reserved: 7;\n\t} adapterOperations3;\n\tstruct {\n\t\tu8 cpld_in_flash: 1;\n\t\tu8 reserved: 7;\n\t\tu8 reserved1[3];\n\t\tu8 userCodeDefinition[12];\n\t} cpld;\n\tstruct {\n\t\tu16 ctrl_info_ext_supported: 1;\n\t\tu16 support_ibutton_less: 1;\n\t\tu16 supported_enc_algo: 1;\n\t\tu16 support_encrypted_mfc: 1;\n\t\tu16 image_upload_supported: 1;\n\t\tu16 support_ses_ctrl_in_multipathcfg: 1;\n\t\tu16 support_pd_map_target_id: 1;\n\t\tu16 fw_swaps_bbu_vpd_info: 1;\n\t\tu16 support_ssc_rev3: 1;\n\t\tu16 support_dual_fw_update: 1;\n\t\tu16 support_host_info: 1;\n\t\tu16 support_flash_comp_info: 1;\n\t\tu16 support_pl_debug_info: 1;\n\t\tu16 support_nvme_passthru: 1;\n\t\tu16 reserved: 2;\n\t} adapter_operations4;\n\tu8 pad[2];\n\tu32 size;\n\tu32 pad1;\n\tu8 reserved6[64];\n\tstruct {\n\t\tu32 mr_config_ext2_supported: 1;\n\t\tu32 support_profile_change: 2;\n\t\tu32 support_cvhealth_info: 1;\n\t\tu32 support_pcie: 1;\n\t\tu32 support_ext_mfg_vpd: 1;\n\t\tu32 support_oce_only: 1;\n\t\tu32 support_nvme_tm: 1;\n\t\tu32 support_snap_dump: 1;\n\t\tu32 support_fde_type_mix: 1;\n\t\tu32 support_force_personality_change: 1;\n\t\tu32 support_psoc_update: 1;\n\t\tu32 support_pci_lane_margining: 1;\n\t\tu32 reserved: 19;\n\t} adapter_operations5;\n\tu32 rsvdForAdptOp[63];\n\tu8 reserved7[3];\n\tu8 TaskAbortTO;\n\tu8 MaxResetTO;\n\tu8 reserved8[3];\n};\n\nstruct megasas_sge32 {\n\t__le32 phys_addr;\n\t__le32 length;\n};\n\nstruct megasas_sge64 {\n\t__le64 phys_addr;\n\t__le32 length;\n} __attribute__((packed));\n\nstruct megasas_sge_skinny {\n\t__le64 phys_addr;\n\t__le32 length;\n\t__le32 flag;\n};\n\nunion megasas_sgl {\n\tstruct {\n\t\tstruct {} __empty_sge32;\n\t\tstruct megasas_sge32 sge32[0];\n\t};\n\tstruct {\n\t\tstruct {} __empty_sge64;\n\t\tstruct megasas_sge64 sge64[0];\n\t};\n\tstruct {\n\t\tstruct {} __empty_sge_skinny;\n\t\tstruct megasas_sge_skinny sge_skinny[0];\n\t};\n};\n\nstruct megasas_dcmd_frame {\n\tu8 cmd;\n\tu8 reserved_0;\n\tu8 cmd_status;\n\tu8 reserved_1[4];\n\tu8 sge_count;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 timeout;\n\t__le32 data_xfer_len;\n\t__le32 opcode;\n\tunion {\n\t\tu8 b[12];\n\t\t__le16 s[6];\n\t\t__le32 w[3];\n\t} mbox;\n\tunion megasas_sgl sgl;\n};\n\nstruct megasas_debugfs_buffer {\n\tvoid *buf;\n\tu32 len;\n};\n\nunion megasas_evt_class_locale {\n\tstruct {\n\t\tu16 locale;\n\t\tu8 reserved;\n\t\ts8 class;\n\t} members;\n\tu32 word;\n};\n\nstruct megasas_evtarg_pd {\n\tu16 device_id;\n\tu8 encl_index;\n\tu8 slot_number;\n};\n\nstruct megasas_evtarg_ld {\n\tu16 target_id;\n\tu8 ld_index;\n\tu8 reserved;\n};\n\nstruct megasas_progress {\n\t__le16 progress;\n\t__le16 elapsed_seconds;\n};\n\nstruct megasas_evt_detail {\n\t__le32 seq_num;\n\t__le32 time_stamp;\n\t__le32 code;\n\tunion megasas_evt_class_locale cl;\n\tu8 arg_type;\n\tu8 reserved1[15];\n\tunion {\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_pd pd;\n\t\t\tu8 cdb_length;\n\t\t\tu8 sense_length;\n\t\t\tu8 reserved[2];\n\t\t\tu8 cdb[16];\n\t\t\tu8 sense[64];\n\t\t} cdbSense;\n\t\tstruct megasas_evtarg_ld ld;\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t\t__le64 count;\n\t\t} __attribute__((packed)) ld_count;\n\t\tstruct {\n\t\t\t__le64 lba;\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t} __attribute__((packed)) ld_lba;\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t\t__le32 prevOwner;\n\t\t\t__le32 newOwner;\n\t\t} ld_owner;\n\t\tstruct {\n\t\t\tu64 ld_lba;\n\t\t\tu64 pd_lba;\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t\tstruct megasas_evtarg_pd pd;\n\t\t} ld_lba_pd_lba;\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t\tstruct megasas_progress prog;\n\t\t} ld_prog;\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t\tu32 prev_state;\n\t\t\tu32 new_state;\n\t\t} ld_state;\n\t\tstruct {\n\t\t\tu64 strip;\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t} __attribute__((packed)) ld_strip;\n\t\tstruct megasas_evtarg_pd pd;\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_pd pd;\n\t\t\tu32 err;\n\t\t} pd_err;\n\t\tstruct {\n\t\t\tu64 lba;\n\t\t\tstruct megasas_evtarg_pd pd;\n\t\t} __attribute__((packed)) pd_lba;\n\t\tstruct {\n\t\t\tu64 lba;\n\t\t\tstruct megasas_evtarg_pd pd;\n\t\t\tstruct megasas_evtarg_ld ld;\n\t\t} pd_lba_ld;\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_pd pd;\n\t\t\tstruct megasas_progress prog;\n\t\t} pd_prog;\n\t\tstruct {\n\t\t\tstruct megasas_evtarg_pd pd;\n\t\t\tu32 prevState;\n\t\t\tu32 newState;\n\t\t} pd_state;\n\t\tstruct {\n\t\t\tu16 vendorId;\n\t\t\t__le16 deviceId;\n\t\t\tu16 subVendorId;\n\t\t\tu16 subDeviceId;\n\t\t} pci;\n\t\tu32 rate;\n\t\tchar str[96];\n\t\tstruct {\n\t\t\tu32 rtc;\n\t\t\tu32 elapsedSeconds;\n\t\t} time;\n\t\tstruct {\n\t\t\tu32 ecar;\n\t\t\tu32 elog;\n\t\t\tchar str[64];\n\t\t} ecc;\n\t\tu8 b[96];\n\t\t__le16 s[48];\n\t\t__le32 w[24];\n\t\t__le64 d[12];\n\t} args;\n\tchar description[128];\n};\n\nstruct megasas_evt_log_info {\n\t__le32 newest_seq_num;\n\t__le32 oldest_seq_num;\n\t__le32 clear_seq_num;\n\t__le32 shutdown_seq_num;\n\t__le32 boot_seq_num;\n};\n\nstruct megasas_init_frame {\n\tu8 cmd;\n\tu8 reserved_0;\n\tu8 cmd_status;\n\tu8 reserved_1;\n\tMFI_CAPABILITIES driver_operations;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 replyqueue_mask;\n\t__le32 data_xfer_len;\n\t__le32 queue_info_new_phys_addr_lo;\n\t__le32 queue_info_new_phys_addr_hi;\n\t__le32 queue_info_old_phys_addr_lo;\n\t__le32 queue_info_old_phys_addr_hi;\n\t__le32 reserved_4[2];\n\t__le32 system_info_lo;\n\t__le32 system_info_hi;\n\t__le32 reserved_5[2];\n};\n\nstruct megasas_io_frame {\n\tu8 cmd;\n\tu8 sense_len;\n\tu8 cmd_status;\n\tu8 scsi_status;\n\tu8 target_id;\n\tu8 access_byte;\n\tu8 reserved_0;\n\tu8 sge_count;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 timeout;\n\t__le32 lba_count;\n\t__le32 sense_buf_phys_addr_lo;\n\t__le32 sense_buf_phys_addr_hi;\n\t__le32 start_lba_lo;\n\t__le32 start_lba_hi;\n\tunion megasas_sgl sgl;\n};\n\nstruct megasas_pthru_frame {\n\tu8 cmd;\n\tu8 sense_len;\n\tu8 cmd_status;\n\tu8 scsi_status;\n\tu8 target_id;\n\tu8 lun;\n\tu8 cdb_len;\n\tu8 sge_count;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 timeout;\n\t__le32 data_xfer_len;\n\t__le32 sense_buf_phys_addr_lo;\n\t__le32 sense_buf_phys_addr_hi;\n\tu8 cdb[16];\n\tunion megasas_sgl sgl;\n};\n\nstruct megasas_smp_frame {\n\tu8 cmd;\n\tu8 reserved_1;\n\tu8 cmd_status;\n\tu8 connection_status;\n\tu8 reserved_2[3];\n\tu8 sge_count;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 timeout;\n\t__le32 data_xfer_len;\n\t__le64 sas_addr;\n\tunion {\n\t\tstruct megasas_sge32 sge32[2];\n\t\tstruct megasas_sge64 sge64[2];\n\t} sgl;\n};\n\nstruct megasas_stp_frame {\n\tu8 cmd;\n\tu8 reserved_1;\n\tu8 cmd_status;\n\tu8 reserved_2;\n\tu8 target_id;\n\tu8 reserved_3[2];\n\tu8 sge_count;\n\t__le32 context;\n\t__le32 pad_0;\n\t__le16 flags;\n\t__le16 timeout;\n\t__le32 data_xfer_len;\n\t__le16 fis[10];\n\t__le32 stp_flags;\n\tunion {\n\t\tstruct megasas_sge32 sge32[2];\n\t\tstruct megasas_sge64 sge64[2];\n\t} sgl;\n};\n\nunion megasas_frame {\n\tstruct megasas_header hdr;\n\tstruct megasas_init_frame init;\n\tstruct megasas_io_frame io;\n\tstruct megasas_pthru_frame pthru;\n\tstruct megasas_dcmd_frame dcmd;\n\tstruct megasas_abort_frame abort;\n\tstruct megasas_smp_frame smp;\n\tstruct megasas_stp_frame stp;\n\tu8 raw_bytes[64];\n};\n\nstruct megasas_init_queue_info {\n\t__le32 init_flags;\n\t__le32 reply_queue_entries;\n\t__le32 reply_queue_start_phys_addr_lo;\n\t__le32 reply_queue_start_phys_addr_hi;\n\t__le32 producer_index_phys_addr_lo;\n\t__le32 producer_index_phys_addr_hi;\n\t__le32 consumer_index_phys_addr_lo;\n\t__le32 consumer_index_phys_addr_hi;\n};\n\nstruct megasas_pd_list {\n\tu16 tid;\n\tu8 driveType;\n\tu8 driveState;\n};\n\nstruct megasas_irq_context {\n\tchar name[32];\n\tstruct megasas_instance *instance;\n\tu32 MSIxIndex;\n\tu32 os_irq;\n\tstruct irq_poll irqpoll;\n\tbool irq_poll_scheduled;\n\tbool irq_line_enable;\n\tatomic_t in_used;\n};\n\nstruct megasas_register_set;\n\nstruct megasas_instance_template;\n\nstruct megasas_instance {\n\tunsigned int *reply_map;\n\t__le32 *producer;\n\tdma_addr_t producer_h;\n\t__le32 *consumer;\n\tdma_addr_t consumer_h;\n\tstruct MR_DRV_SYSTEM_INFO *system_info_buf;\n\tdma_addr_t system_info_h;\n\tstruct MR_LD_VF_AFFILIATION *vf_affiliation;\n\tdma_addr_t vf_affiliation_h;\n\tstruct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;\n\tdma_addr_t vf_affiliation_111_h;\n\tstruct MR_CTRL_HB_HOST_MEM *hb_host_mem;\n\tdma_addr_t hb_host_mem_h;\n\tstruct MR_PD_INFO *pd_info;\n\tdma_addr_t pd_info_h;\n\tstruct MR_TARGET_PROPERTIES *tgt_prop;\n\tdma_addr_t tgt_prop_h;\n\t__le32 *reply_queue;\n\tdma_addr_t reply_queue_h;\n\tu32 *crash_dump_buf;\n\tdma_addr_t crash_dump_h;\n\tstruct MR_PD_LIST *pd_list_buf;\n\tdma_addr_t pd_list_buf_h;\n\tstruct megasas_ctrl_info *ctrl_info_buf;\n\tdma_addr_t ctrl_info_buf_h;\n\tstruct MR_LD_LIST *ld_list_buf;\n\tdma_addr_t ld_list_buf_h;\n\tstruct MR_LD_TARGETID_LIST *ld_targetid_list_buf;\n\tdma_addr_t ld_targetid_list_buf_h;\n\tstruct MR_HOST_DEVICE_LIST *host_device_list_buf;\n\tdma_addr_t host_device_list_buf_h;\n\tstruct MR_SNAPDUMP_PROPERTIES *snapdump_prop;\n\tdma_addr_t snapdump_prop_h;\n\tvoid *crash_buf[512];\n\tunsigned int fw_crash_buffer_size;\n\tunsigned int fw_crash_state;\n\tunsigned int fw_crash_buffer_offset;\n\tu32 drv_buf_index;\n\tu32 drv_buf_alloc;\n\tu32 crash_dump_fw_support;\n\tu32 crash_dump_drv_support;\n\tu32 crash_dump_app_support;\n\tu32 secure_jbod_support;\n\tu32 support_morethan256jbod;\n\tbool use_seqnum_jbod_fp;\n\tbool smp_affinity_enable;\n\tstruct mutex crashdump_lock;\n\tstruct megasas_register_set *reg_set;\n\tu32 *reply_post_host_index_addr[16];\n\tstruct megasas_pd_list pd_list[256];\n\tstruct megasas_pd_list local_pd_list[256];\n\tu8 ld_ids[256];\n\tu8 ld_tgtid_status[256];\n\tu8 ld_ids_prev[256];\n\tu8 ld_ids_from_raidmap[256];\n\ts8 init_id;\n\tu16 max_num_sge;\n\tu16 max_fw_cmds;\n\tu16 max_mpt_cmds;\n\tu16 max_mfi_cmds;\n\tu16 max_scsi_cmds;\n\tu16 ldio_threshold;\n\tu16 cur_can_queue;\n\tu32 max_sectors_per_req;\n\tbool msix_load_balance;\n\tstruct megasas_aen_event *ev;\n\tstruct megasas_cmd **cmd_list;\n\tstruct list_head cmd_pool;\n\tspinlock_t mfi_pool_lock;\n\tspinlock_t hba_lock;\n\tspinlock_t stream_lock;\n\tspinlock_t completion_lock;\n\tstruct dma_pool *frame_dma_pool;\n\tstruct dma_pool *sense_dma_pool;\n\tstruct megasas_evt_detail *evt_detail;\n\tdma_addr_t evt_detail_h;\n\tstruct megasas_cmd *aen_cmd;\n\tstruct semaphore ioctl_sem;\n\tstruct Scsi_Host *host;\n\twait_queue_head_t int_cmd_wait_q;\n\twait_queue_head_t abort_cmd_wait_q;\n\tstruct pci_dev *pdev;\n\tu32 unique_id;\n\tu32 fw_support_ieee;\n\tu32 threshold_reply_count;\n\tatomic_t fw_outstanding;\n\tatomic_t ldio_outstanding;\n\tatomic_t fw_reset_no_pci_access;\n\tatomic64_t total_io_count;\n\tatomic64_t high_iops_outstanding;\n\tstruct megasas_instance_template *instancet;\n\tstruct tasklet_struct isr_tasklet;\n\tstruct work_struct work_init;\n\tstruct delayed_work fw_fault_work;\n\tstruct workqueue_struct *fw_fault_work_q;\n\tchar fault_handler_work_q_name[48];\n\tu8 flag;\n\tu8 unload;\n\tu8 flag_ieee;\n\tu8 issuepend_done;\n\tu8 disableOnlineCtrlReset;\n\tu8 UnevenSpanSupport;\n\tu8 supportmax256vd;\n\tu8 pd_list_not_supported;\n\tu16 fw_supported_vd_count;\n\tu16 fw_supported_pd_count;\n\tu16 drv_supported_vd_count;\n\tu16 drv_supported_pd_count;\n\tatomic_t adprecovery;\n\tlong unsigned int last_time;\n\tu32 mfiStatus;\n\tu32 last_seq_num;\n\tstruct list_head internal_reset_pending_q;\n\tvoid *ctrl_context;\n\tunsigned int msix_vectors;\n\tstruct megasas_irq_context irq_context[128];\n\tu64 map_id;\n\tu64 pd_seq_map_id;\n\tstruct megasas_cmd *map_update_cmd;\n\tstruct megasas_cmd *jbod_seq_cmd;\n\tlong unsigned int bar;\n\tlong int reset_flags;\n\tstruct mutex reset_mutex;\n\tstruct timer_list sriov_heartbeat_timer;\n\tchar skip_heartbeat_timer_del;\n\tu8 requestorId;\n\tchar PlasmaFW111;\n\tchar clusterId[16];\n\tu8 peerIsPresent;\n\tu8 passive;\n\tu16 throttlequeuedepth;\n\tu8 mask_interrupts;\n\tu16 max_chain_frame_sz;\n\tu8 is_imr;\n\tu8 is_rdpq;\n\tbool dev_handle;\n\tbool fw_sync_cache_support;\n\tu32 mfi_frame_size;\n\tbool msix_combined;\n\tu16 max_raid_mapsize;\n\tu8 r1_ldio_hint_default;\n\tu32 nvme_page_size;\n\tu8 adapter_type;\n\tbool consistent_mask_64bit;\n\tbool support_nvme_passthru;\n\tbool enable_sdev_max_qd;\n\tu8 task_abort_tmo;\n\tu8 max_reset_tmo;\n\tu8 snapdump_wait_time;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *raidmap_dump;\n\tu8 enable_fw_dev_list;\n\tbool atomic_desc_support;\n\tbool support_seqnum_jbod_fp;\n\tbool support_pci_lane_margining;\n\tu8 low_latency_index_start;\n\tint perf_mode;\n\tint iopoll_q_count;\n};\n\nstruct megasas_instance_template {\n\tvoid (*fire_cmd)(struct megasas_instance *, dma_addr_t, u32, struct megasas_register_set *);\n\tvoid (*enable_intr)(struct megasas_instance *);\n\tvoid (*disable_intr)(struct megasas_instance *);\n\tint (*clear_intr)(struct megasas_instance *);\n\tu32 (*read_fw_status_reg)(struct megasas_instance *);\n\tint (*adp_reset)(struct megasas_instance *, struct megasas_register_set *);\n\tint (*check_reset)(struct megasas_instance *, struct megasas_register_set *);\n\tirqreturn_t (*service_isr)(int, void *);\n\tvoid (*tasklet)(long unsigned int);\n\tu32 (*init_adapter)(struct megasas_instance *);\n\tu32 (*build_and_issue_cmd)(struct megasas_instance *, struct scsi_cmnd *);\n\tvoid (*issue_dcmd)(struct megasas_instance *, struct megasas_cmd *);\n};\n\nstruct megasas_iocpacket {\n\tu16 host_no;\n\tu16 __pad1;\n\tu32 sgl_off;\n\tu32 sge_count;\n\tu32 sense_off;\n\tu32 sense_len;\n\tunion {\n\t\tu8 raw[128];\n\t\tstruct megasas_header hdr;\n\t} frame;\n\tstruct iovec sgl[16];\n} __attribute__((packed));\n\nstruct megasas_mgmt_info {\n\tu16 count;\n\tstruct megasas_instance *instance[1024];\n\tint max_index;\n};\n\nstruct megasas_register_set {\n\tu32 doorbell;\n\tu32 fusion_seq_offset;\n\tu32 fusion_host_diag;\n\tu32 reserved_01;\n\tu32 inbound_msg_0;\n\tu32 inbound_msg_1;\n\tu32 outbound_msg_0;\n\tu32 outbound_msg_1;\n\tu32 inbound_doorbell;\n\tu32 inbound_intr_status;\n\tu32 inbound_intr_mask;\n\tu32 outbound_doorbell;\n\tu32 outbound_intr_status;\n\tu32 outbound_intr_mask;\n\tu32 reserved_1[2];\n\tu32 inbound_queue_port;\n\tu32 outbound_queue_port;\n\tu32 reserved_2[9];\n\tu32 reply_post_host_index;\n\tu32 reserved_2_2[12];\n\tu32 outbound_doorbell_clear;\n\tu32 reserved_3[3];\n\tu32 outbound_scratch_pad_0;\n\tu32 outbound_scratch_pad_1;\n\tu32 outbound_scratch_pad_2;\n\tu32 outbound_scratch_pad_3;\n\tu32 inbound_low_queue_port;\n\tu32 inbound_high_queue_port;\n\tu32 inbound_single_queue_port;\n\tu32 res_6[11];\n\tu32 host_diag;\n\tu32 seq_offset;\n\tu32 index_registers[807];\n};\n\nstruct mem_cgroup_private_id {\n\tint id;\n\trefcount_t ref;\n};\n\nstruct vmpressure {\n\tlong unsigned int scanned;\n\tlong unsigned int reclaimed;\n\tlong unsigned int tree_scanned;\n\tlong unsigned int tree_reclaimed;\n\tspinlock_t sr_lock;\n\tstruct list_head events;\n\tstruct mutex events_lock;\n\tstruct work_struct work;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct memcg_cgwb_frn {\n\tu64 bdi_id;\n\tint memcg_id;\n\tu64 at;\n\tstruct wb_completion done;\n};\n\nstruct memcg_vmstats;\n\nstruct memcg_vmstats_percpu;\n\nstruct mem_cgroup_per_node;\n\nstruct mem_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct mem_cgroup_private_id id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter memory;\n\tunion {\n\t\tstruct page_counter swap;\n\t\tstruct page_counter memsw;\n\t};\n\tstruct list_head memory_peaks;\n\tstruct list_head swap_peaks;\n\tspinlock_t peaks_lock;\n\tstruct work_struct high_work;\n\tstruct vmpressure vmpressure;\n\tbool oom_group;\n\tint swappiness;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct cgroup_file swap_events_file;\n\tstruct memcg_vmstats *vmstats;\n\tatomic_long_t memory_events[10];\n\tatomic_long_t memory_events_local[10];\n\tu64 socket_pressure;\n\tint kmemcg_id;\n\tstruct obj_cgroup *objcg;\n\tstruct obj_cgroup *orig_objcg;\n\tstruct list_head objcg_list;\n\tstruct memcg_vmstats_percpu *vmstats_percpu;\n\tstruct list_head cgwb_list;\n\tstruct wb_domain cgwb_domain;\n\tstruct memcg_cgwb_frn cgwb_frn[4];\n\tstruct deferred_split deferred_split_queue;\n\tstruct mem_cgroup_per_node *nodeinfo[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mem_cgroup_reclaim_iter {\n\tstruct mem_cgroup *position;\n\tatomic_t generation;\n};\n\nstruct shrinker_info;\n\nstruct mem_cgroup_per_node {\n\tstruct mem_cgroup *memcg;\n\tstruct lruvec_stats_percpu *lruvec_stats_percpu;\n\tstruct lruvec_stats *lruvec_stats;\n\tstruct shrinker_info *shrinker_info;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct lruvec lruvec;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int lru_zone_size[20];\n\tstruct mem_cgroup_reclaim_iter iter;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct mcidev_sysfs_attribute;\n\nstruct mem_ctl_info {\n\tstruct device dev;\n\tconst struct bus_type *bus;\n\tstruct list_head link;\n\tstruct module *owner;\n\tlong unsigned int mtype_cap;\n\tlong unsigned int edac_ctl_cap;\n\tlong unsigned int edac_cap;\n\tlong unsigned int scrub_cap;\n\tenum scrub_type scrub_mode;\n\tint (*set_sdram_scrub_rate)(struct mem_ctl_info *, u32);\n\tint (*get_sdram_scrub_rate)(struct mem_ctl_info *);\n\tvoid (*edac_check)(struct mem_ctl_info *);\n\tlong unsigned int (*ctl_page_to_phys)(struct mem_ctl_info *, long unsigned int);\n\tint mc_idx;\n\tstruct csrow_info **csrows;\n\tunsigned int nr_csrows;\n\tunsigned int num_cschannel;\n\tunsigned int n_layers;\n\tstruct edac_mc_layer *layers;\n\tbool csbased;\n\tunsigned int tot_dimms;\n\tstruct dimm_info **dimms;\n\tstruct device *pdev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tu32 ce_noinfo_count;\n\tu32 ue_noinfo_count;\n\tu32 ue_mc;\n\tu32 ce_mc;\n\tstruct completion complete;\n\tconst struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;\n\tstruct delayed_work work;\n\tstruct edac_raw_error_desc error_desc;\n\tint op_state;\n\tstruct dentry *debugfs;\n\tu8 fake_inject_layer[3];\n\tbool fake_inject_ue;\n\tu16 fake_inject_count;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n};\n\nstruct mem_extent {\n\tstruct list_head hook;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mem_section_usage;\n\nstruct mem_section {\n\tlong unsigned int section_mem_map;\n\tstruct mem_section_usage *usage;\n};\n\nstruct mem_section_usage {\n\tstruct callback_head rcu;\n\tlong unsigned int subsection_map[1];\n\tlong unsigned int pageblock_flags[0];\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct mem_zone_bm_rtree {\n\tstruct list_head list;\n\tstruct list_head nodes;\n\tstruct list_head leaves;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tstruct rtree_node *rtree;\n\tint levels;\n\tunsigned int blocks;\n};\n\nstruct memac_cfg {\n\tbool reset_on_init;\n\tbool pause_ignore;\n\tbool promiscuous_mode_enable;\n\tu16 max_frame_length;\n\tu16 pause_quanta;\n\tu32 tx_ipg_length;\n};\n\nstruct memac_regs {\n\tu32 res0000[2];\n\tu32 command_config;\n\tstruct mac_addr___2 mac_addr0;\n\tu32 maxfrm;\n\tu32 res0018[1];\n\tu32 rx_fifo_sections;\n\tu32 tx_fifo_sections;\n\tu32 res0024[2];\n\tu32 hashtable_ctrl;\n\tu32 res0030[4];\n\tu32 ievent;\n\tu32 tx_ipg_length;\n\tu32 res0048;\n\tu32 imask;\n\tu32 res0050;\n\tu32 pause_quanta[4];\n\tu32 pause_thresh[4];\n\tu32 rx_pause_status;\n\tu32 res0078[2];\n\tstruct mac_addr___2 mac_addr[7];\n\tu32 lpwake_timer;\n\tu32 sleep_timer;\n\tu32 res00c0[8];\n\tu32 statn_config;\n\tu32 res00e4[7];\n\tu32 reoct_l;\n\tu32 reoct_u;\n\tu32 roct_l;\n\tu32 roct_u;\n\tu32 raln_l;\n\tu32 raln_u;\n\tu32 rxpf_l;\n\tu32 rxpf_u;\n\tu32 rfrm_l;\n\tu32 rfrm_u;\n\tu32 rfcs_l;\n\tu32 rfcs_u;\n\tu32 rvlan_l;\n\tu32 rvlan_u;\n\tu32 rerr_l;\n\tu32 rerr_u;\n\tu32 ruca_l;\n\tu32 ruca_u;\n\tu32 rmca_l;\n\tu32 rmca_u;\n\tu32 rbca_l;\n\tu32 rbca_u;\n\tu32 rdrp_l;\n\tu32 rdrp_u;\n\tu32 rpkt_l;\n\tu32 rpkt_u;\n\tu32 rund_l;\n\tu32 rund_u;\n\tu32 r64_l;\n\tu32 r64_u;\n\tu32 r127_l;\n\tu32 r127_u;\n\tu32 r255_l;\n\tu32 r255_u;\n\tu32 r511_l;\n\tu32 r511_u;\n\tu32 r1023_l;\n\tu32 r1023_u;\n\tu32 r1518_l;\n\tu32 r1518_u;\n\tu32 r1519x_l;\n\tu32 r1519x_u;\n\tu32 rovr_l;\n\tu32 rovr_u;\n\tu32 rjbr_l;\n\tu32 rjbr_u;\n\tu32 rfrg_l;\n\tu32 rfrg_u;\n\tu32 rcnp_l;\n\tu32 rcnp_u;\n\tu32 rdrntp_l;\n\tu32 rdrntp_u;\n\tu32 res01d0[12];\n\tu32 teoct_l;\n\tu32 teoct_u;\n\tu32 toct_l;\n\tu32 toct_u;\n\tu32 res0210[2];\n\tu32 txpf_l;\n\tu32 txpf_u;\n\tu32 tfrm_l;\n\tu32 tfrm_u;\n\tu32 tfcs_l;\n\tu32 tfcs_u;\n\tu32 tvlan_l;\n\tu32 tvlan_u;\n\tu32 terr_l;\n\tu32 terr_u;\n\tu32 tuca_l;\n\tu32 tuca_u;\n\tu32 tmca_l;\n\tu32 tmca_u;\n\tu32 tbca_l;\n\tu32 tbca_u;\n\tu32 res0258[2];\n\tu32 tpkt_l;\n\tu32 tpkt_u;\n\tu32 tund_l;\n\tu32 tund_u;\n\tu32 t64_l;\n\tu32 t64_u;\n\tu32 t127_l;\n\tu32 t127_u;\n\tu32 t255_l;\n\tu32 t255_u;\n\tu32 t511_l;\n\tu32 t511_u;\n\tu32 t1023_l;\n\tu32 t1023_u;\n\tu32 t1518_l;\n\tu32 t1518_u;\n\tu32 t1519x_l;\n\tu32 t1519x_u;\n\tu32 res02a8[6];\n\tu32 tcnp_l;\n\tu32 tcnp_u;\n\tu32 res02c8[14];\n\tu32 if_mode;\n\tu32 if_status;\n\tu32 res0308[14];\n\tu32 hg_config;\n\tu32 res0344[3];\n\tu32 hg_pause_quanta;\n\tu32 res0354[3];\n\tu32 hg_pause_thresh;\n\tu32 res0364[3];\n\tu32 hgrx_pause_status;\n\tu32 hg_fifos_status;\n\tu32 rhm;\n\tu32 thm;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n\tint nid;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memcg_stock_pcp {\n\tlocal_trylock_t lock;\n\tuint8_t nr_pages[7];\n\tstruct mem_cgroup *cached[7];\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct memcg_vmstats {\n\tlong int state[40];\n\tlong unsigned int events[26];\n\tlong int state_local[40];\n\tlong unsigned int events_local[26];\n\tlong int state_pending[40];\n\tlong unsigned int events_pending[26];\n\tatomic_t stats_updates;\n};\n\nstruct memcg_vmstats_percpu {\n\tunsigned int stats_updates;\n\tstruct memcg_vmstats_percpu *parent_pcpu;\n\tstruct memcg_vmstats *vmstats;\n\tlong int state[40];\n\tlong unsigned int events[26];\n\tlong int state_prev[40];\n\tlong unsigned int events_prev[26];\n\tlong: 64;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct memdev_dmi_entry {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n\tu16 phys_mem_array_handle;\n\tu16 mem_err_info_handle;\n\tu16 total_width;\n\tu16 data_width;\n\tu16 size;\n\tu8 form_factor;\n\tu8 device_set;\n\tu8 device_locator;\n\tu8 bank_locator;\n\tu8 memory_type;\n\tu16 type_detail;\n\tu16 speed;\n\tu8 manufacturer;\n\tu8 serial_number;\n\tu8 asset_tag;\n\tu8 part_number;\n\tu8 attributes;\n\tu32 extended_size;\n\tu16 conf_mem_clk_speed;\n} __attribute__((packed));\n\nstruct memory_bitmap {\n\tstruct list_head zones;\n\tstruct linked_page *p_list;\n\tstruct bm_position cur;\n};\n\nstruct memory_group;\n\nstruct memory_block {\n\tlong unsigned int start_section_nr;\n\tenum memory_block_state state;\n\tint online_type;\n\tint nid;\n\tstruct zone *zone;\n\tstruct device dev;\n\tstruct vmem_altmap *altmap;\n\tstruct memory_group *group;\n\tstruct list_head group_next;\n\tatomic_long_t nr_hwpoison;\n};\n\nstruct memory_dev_type {\n\tstruct list_head tier_sibling;\n\tstruct list_head list;\n\tint adistance;\n\tnodemask_t nodes;\n\tstruct kref kref;\n};\n\nstruct memory_failure_entry {\n\tlong unsigned int pfn;\n\tint flags;\n};\n\nstruct memory_failure_cpu {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct memory_failure_entry *type;\n\t\t\tconst struct memory_failure_entry *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct memory_failure_entry *ptr;\n\t\t\tconst struct memory_failure_entry *ptr_const;\n\t\t};\n\t\tstruct memory_failure_entry buf[16];\n\t} fifo;\n\traw_spinlock_t lock;\n\tstruct work_struct work;\n};\n\nstruct memory_failure_stats {\n\tlong unsigned int total;\n\tlong unsigned int ignored;\n\tlong unsigned int failed;\n\tlong unsigned int delayed;\n\tlong unsigned int recovered;\n};\n\nstruct memory_group {\n\tint nid;\n\tstruct list_head memory_blocks;\n\tlong unsigned int present_kernel_pages;\n\tlong unsigned int present_movable_pages;\n\tbool is_dynamic;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int max_pages;\n\t\t} s;\n\t\tstruct {\n\t\t\tlong unsigned int unit_pages;\n\t\t} d;\n\t};\n};\n\nstruct memory_initiator {\n\tstruct list_head node;\n\tunsigned int processor_pxm;\n\tbool has_cpu;\n};\n\nstruct memory_locality {\n\tstruct list_head node;\n\tstruct acpi_hmat_locality *hmat_loc;\n};\n\nstruct memory_notify {\n\tlong unsigned int start_pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct memory_stat {\n\tconst char *name;\n\tunsigned int idx;\n};\n\nstruct node_cache_attrs {\n\tenum cache_indexing indexing;\n\tenum cache_write_policy write_policy;\n\tu64 size;\n\tu16 line_size;\n\tu8 level;\n\tu16 address_mode;\n};\n\nstruct memory_target {\n\tstruct list_head node;\n\tunsigned int memory_pxm;\n\tunsigned int processor_pxm;\n\tstruct resource memregions;\n\tstruct access_coordinate coord[4];\n\tstruct list_head caches;\n\tstruct node_cache_attrs cache_attrs;\n\tu8 gen_port_device_handle[16];\n\tbool registered;\n};\n\nstruct memory_tier {\n\tstruct list_head list;\n\tstruct list_head memory_types;\n\tint adistance_start;\n\tstruct device dev;\n\tnodemask_t lower_tier_mask;\n};\n\nstruct mempolicy {\n\tatomic_t refcnt;\n\tshort unsigned int mode;\n\tshort unsigned int flags;\n\tnodemask_t nodes;\n\tint home_node;\n\tunion {\n\t\tnodemask_t cpuset_mems_allowed;\n\t\tnodemask_t user_nodemask;\n\t} w;\n};\n\nstruct mempolicy_operations {\n\tint (*create)(struct mempolicy *, const nodemask_t *);\n\tvoid (*rebind)(struct mempolicy *, const nodemask_t *);\n};\n\nstruct menu_device {\n\tint needs_update;\n\tint tick_wakeup;\n\tu64 next_timer_ns;\n\tunsigned int bucket;\n\tunsigned int correction_factor[6];\n\tunsigned int intervals[8];\n\tint interval_ptr;\n};\n\nstruct merge_sched_data {\n\tint can_add_hw;\n\tenum event_type_t event_type;\n};\n\nstruct meson8_pmx_data {\n\tbool is_gpio;\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct meson_aoclk_data {\n\tconst struct meson_clkc_data clkc_data;\n\tconst unsigned int reset_reg;\n\tconst int num_reset;\n\tconst unsigned int *reset;\n};\n\nstruct meson_aoclk_reset_controller {\n\tstruct reset_controller_dev reset;\n\tconst struct meson_aoclk_data *data;\n\tstruct regmap *regmap;\n};\n\nstruct meson_pmx_bank;\n\nstruct meson_axg_pmx_data {\n\tconst struct meson_pmx_bank *pmx_banks;\n\tunsigned int num_pmx_banks;\n};\n\nstruct meson_reg_desc {\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct meson_bank {\n\tconst char *name;\n\tunsigned int first;\n\tunsigned int last;\n\tint irq_first;\n\tint irq_last;\n\tstruct meson_reg_desc regs[6];\n};\n\nstruct parm {\n\tu16 reg_off;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct meson_clk_cpu_dyndiv_data {\n\tstruct parm div;\n\tstruct parm dyn;\n};\n\nstruct meson_clk_dualdiv_param;\n\nstruct meson_clk_dualdiv_data {\n\tstruct parm n1;\n\tstruct parm n2;\n\tstruct parm m1;\n\tstruct parm m2;\n\tstruct parm dual;\n\tconst struct meson_clk_dualdiv_param *table;\n};\n\nstruct meson_clk_dualdiv_param {\n\tunsigned int n1;\n\tunsigned int n2;\n\tunsigned int m1;\n\tunsigned int m2;\n\tunsigned int dual;\n};\n\nstruct meson_clk_mpll_data {\n\tstruct parm sdm;\n\tstruct parm sdm_en;\n\tstruct parm n2;\n\tstruct parm ssen;\n\tstruct parm misc;\n\tconst struct reg_sequence *init_regs;\n\tunsigned int init_count;\n\tu8 flags;\n};\n\nstruct pll_params_table;\n\nstruct pll_mult_range;\n\nstruct meson_clk_pll_data {\n\tstruct parm en;\n\tstruct parm m;\n\tstruct parm n;\n\tstruct parm frac;\n\tstruct parm l;\n\tstruct parm rst;\n\tstruct parm current_en;\n\tstruct parm l_detect;\n\tconst struct reg_sequence *init_regs;\n\tunsigned int init_count;\n\tconst struct pll_params_table *table;\n\tconst struct pll_mult_range *range;\n\tunsigned int frac_max;\n\tu8 flags;\n};\n\nstruct meson_ee_pwrc_domain;\n\nstruct meson_ee_pwrc {\n\tstruct regmap *regmap_ao;\n\tstruct regmap *regmap_hhi;\n\tstruct meson_ee_pwrc_domain *domains;\n\tstruct genpd_onecell_data xlate;\n};\n\nstruct meson_ee_pwrc_top_domain;\n\nstruct meson_ee_pwrc_mem_domain;\n\nstruct meson_ee_pwrc_domain_desc {\n\tchar *name;\n\tunsigned int reset_names_count;\n\tunsigned int clk_names_count;\n\tconst struct meson_ee_pwrc_top_domain *top_pd;\n\tunsigned int mem_pd_count;\n\tconst struct meson_ee_pwrc_mem_domain *mem_pd;\n\tbool (*is_powered_off)(struct meson_ee_pwrc_domain *);\n};\n\nstruct meson_ee_pwrc_domain {\n\tstruct generic_pm_domain base;\n\tbool enabled;\n\tstruct meson_ee_pwrc *pwrc;\n\tstruct meson_ee_pwrc_domain_desc desc;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct reset_control *rstc;\n\tint num_rstc;\n};\n\nstruct meson_ee_pwrc_domain_data {\n\tunsigned int count;\n\tconst struct meson_ee_pwrc_domain_desc *domains;\n};\n\nstruct meson_ee_pwrc_mem_domain {\n\tunsigned int reg;\n\tunsigned int mask;\n};\n\nstruct meson_ee_pwrc_top_domain {\n\tunsigned int sleep_reg;\n\tunsigned int sleep_mask;\n\tunsigned int iso_reg;\n\tunsigned int iso_mask;\n};\n\nstruct meson_gpio_irq_params;\n\nstruct meson_gpio_irq_controller {\n\tconst struct meson_gpio_irq_params *params;\n\tvoid *base;\n\tu32 channel_irqs[64];\n\tlong unsigned int channel_map[1];\n\traw_spinlock_t lock;\n};\n\nstruct meson_gpio_irq_params {\n\tunsigned int nr_hwirq;\n\tunsigned int nr_channels;\n\tbool support_edge_both;\n\tunsigned int edge_both_offset;\n\tunsigned int edge_single_offset;\n\tunsigned int edge_pol_reg;\n\tunsigned int pol_low_offset;\n\tunsigned int pin_sel_mask;\n\tstruct irq_ctl_ops ops;\n};\n\nstruct meson_gx_package_id {\n\tconst char *name;\n\tunsigned int major_id;\n\tunsigned int pack_id;\n\tunsigned int pack_mask;\n};\n\nstruct meson_gx_soc_id {\n\tconst char *name;\n\tunsigned int id;\n};\n\nstruct meson_mmc_data;\n\nstruct sd_emmc_desc;\n\nstruct meson_host {\n\tstruct device *dev;\n\tconst struct meson_mmc_data *data;\n\tstruct mmc_host *mmc;\n\tstruct mmc_command *cmd;\n\tvoid *regs;\n\tstruct clk *mux_clk;\n\tstruct clk *mmc_clk;\n\tlong unsigned int req_rate;\n\tbool ddr;\n\tbool dram_access_quirk;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_clk_gate;\n\tunsigned int bounce_buf_size;\n\tvoid *bounce_buf;\n\tvoid *bounce_iomem_buf;\n\tdma_addr_t bounce_dma_addr;\n\tstruct sd_emmc_desc *descs;\n\tdma_addr_t descs_dma_addr;\n\tint irq;\n\tbool needs_pre_post_req;\n\tspinlock_t lock;\n};\n\nstruct meson_i2c_data;\n\nstruct meson_i2c {\n\tstruct i2c_adapter adap;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct i2c_msg *msg;\n\tint state;\n\tbool last;\n\tint count;\n\tint pos;\n\tint error;\n\tspinlock_t lock;\n\tstruct completion done;\n\tu32 tokens[2];\n\tint num_tokens;\n\tconst struct meson_i2c_data *data;\n};\n\nstruct meson_i2c_data {\n\tvoid (*set_clk_div)(struct meson_i2c *, unsigned int);\n};\n\nstruct meson_mmc_data {\n\tunsigned int tx_delay_mask;\n\tunsigned int rx_delay_mask;\n\tunsigned int always_on;\n\tunsigned int adjust;\n\tunsigned int irq_sdio_sleep;\n};\n\nstruct meson_msr_id;\n\nstruct msr_reg_offset;\n\nstruct meson_msr_data {\n\tstruct meson_msr_id *msr_table;\n\tunsigned int msr_count;\n\tconst struct msr_reg_offset *reg;\n};\n\nstruct meson_msr {\n\tstruct regmap *regmap;\n\tstruct meson_msr_data data;\n};\n\nstruct meson_msr_id {\n\tstruct meson_msr *priv;\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct meson_pinctrl_data;\n\nstruct meson_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pcdev;\n\tstruct pinctrl_desc desc;\n\tstruct meson_pinctrl_data *data;\n\tstruct regmap *reg_mux;\n\tstruct regmap *reg_pullen;\n\tstruct regmap *reg_pull;\n\tstruct regmap *reg_gpio;\n\tstruct regmap *reg_ds;\n\tstruct gpio_chip chip;\n\tstruct fwnode_handle *fwnode;\n};\n\nstruct meson_pmx_group;\n\nstruct meson_pmx_func;\n\nstruct meson_pinctrl_data {\n\tconst char *name;\n\tconst struct pinctrl_pin_desc *pins;\n\tconst struct meson_pmx_group *groups;\n\tconst struct meson_pmx_func *funcs;\n\tunsigned int num_pins;\n\tunsigned int num_groups;\n\tunsigned int num_funcs;\n\tconst struct meson_bank *banks;\n\tunsigned int num_banks;\n\tconst struct pinmux_ops *pmx_ops;\n\tconst void *pmx_data;\n\tint (*parse_dt)(struct meson_pinctrl *);\n};\n\nstruct meson_pmx_axg_data {\n\tunsigned int func;\n};\n\nstruct meson_pmx_bank {\n\tconst char *name;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int reg;\n\tunsigned int offset;\n};\n\nstruct meson_pmx_func {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct meson_pmx_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int num_pins;\n\tconst void *data;\n};\n\nstruct meson_reset_param;\n\nstruct meson_reset {\n\tconst struct meson_reset_param *param;\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *map;\n};\n\nstruct meson_reset_param {\n\tconst struct reset_control_ops *reset_ops;\n\tunsigned int reset_num;\n\tunsigned int reset_offset;\n\tunsigned int level_offset;\n\tbool level_low_reset;\n};\n\nstruct meson_rng_data {\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n};\n\nstruct meson_rng_priv {\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n};\n\nstruct meson_sar_adc_param;\n\nstruct meson_sar_adc_data {\n\tconst struct meson_sar_adc_param *param;\n\tconst char *name;\n};\n\nstruct meson_sar_adc_param {\n\tbool has_bl30_integration;\n\tlong unsigned int clock_rate;\n\tunsigned int resolution;\n\tconst struct regmap_config *regmap_config;\n\tu8 temperature_trimming_bits;\n\tunsigned int temperature_multiplier;\n\tunsigned int temperature_divider;\n\tu8 disable_ring_counter;\n\tbool has_vref_select;\n\tu8 vref_select;\n\tu8 cmv_select;\n\tu8 adc_eoc;\n\tenum meson_sar_adc_vref_sel vref_voltage;\n\tbool enable_mpll_clock_workaround;\n};\n\nstruct meson_sar_adc_priv {\n\tstruct regmap *regmap;\n\tstruct regulator *vref;\n\tconst struct meson_sar_adc_param *param;\n\tstruct clk *clkin;\n\tstruct clk *core_clk;\n\tstruct clk *adc_sel_clk;\n\tstruct clk *adc_clk;\n\tstruct clk_gate clk_gate;\n\tstruct clk *adc_div_clk;\n\tstruct clk_divider clk_div;\n\tstruct completion done;\n\tstruct mutex lock;\n\tint calibbias;\n\tint calibscale;\n\tstruct regmap *tsc_regmap;\n\tbool temperature_sensor_calibrated;\n\tu8 temperature_sensor_coefficient;\n\tu16 temperature_sensor_adc_val;\n\tenum meson_sar_adc_chan7_mux_sel chan7_mux_sel;\n};\n\nstruct meson_secure_pwrc_domain;\n\nstruct meson_sm_firmware;\n\nstruct meson_secure_pwrc {\n\tstruct meson_secure_pwrc_domain *domains;\n\tstruct genpd_onecell_data xlate;\n\tstruct meson_sm_firmware *fw;\n};\n\nstruct meson_secure_pwrc_domain {\n\tstruct generic_pm_domain base;\n\tunsigned int index;\n\tunsigned int parent;\n\tstruct meson_secure_pwrc *pwrc;\n};\n\nstruct meson_secure_pwrc_domain_desc;\n\nstruct meson_secure_pwrc_domain_data {\n\tunsigned int count;\n\tconst struct meson_secure_pwrc_domain_desc *domains;\n};\n\nstruct meson_secure_pwrc_domain_desc {\n\tunsigned int index;\n\tunsigned int parent;\n\tunsigned int flags;\n\tchar *name;\n\tbool (*is_off)(struct meson_secure_pwrc_domain *);\n};\n\nstruct meson_sm_cmd {\n\tunsigned int index;\n\tu32 smc_id;\n};\n\nstruct meson_sm_chip {\n\tunsigned int shmem_size;\n\tu32 cmd_shmem_in_base;\n\tu32 cmd_shmem_out_base;\n\tstruct meson_sm_cmd cmd[0];\n};\n\nstruct meson_sm_firmware {\n\tconst struct meson_sm_chip *chip;\n\tvoid *sm_shmem_in_base;\n\tvoid *sm_shmem_out_base;\n};\n\nstruct uart_driver;\n\nstruct meson_uart_data {\n\tstruct uart_driver *uart_driver;\n\tbool has_xtal_div2;\n};\n\nstruct meson_vclk_div_data {\n\tstruct parm div;\n\tstruct parm enable;\n\tstruct parm reset;\n\tconst struct clk_div_table *table;\n\tu8 flags;\n};\n\nstruct meson_vclk_gate_data {\n\tstruct parm enable;\n\tstruct parm reset;\n\tu8 flags;\n};\n\nstruct meson_vid_pll_div_data {\n\tstruct parm val;\n\tstruct parm sel;\n};\n\nstruct meta_entry {\n\tu64 data_block;\n\tunsigned int index_block;\n\tshort unsigned int offset;\n\tshort unsigned int pad;\n};\n\nstruct meta_index {\n\tunsigned int inode_number;\n\tunsigned int offset;\n\tshort unsigned int entries;\n\tshort unsigned int skip;\n\tshort unsigned int locked;\n\tshort unsigned int pad;\n\tstruct meta_entry meta_entry[127];\n};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mext_data {\n\tstruct inode *orig_inode;\n\tstruct inode *donor_inode;\n\tstruct ext4_map_blocks orig_map;\n\text4_lblk_t donor_lblk;\n};\n\nstruct mfd_cell_acpi_match;\n\nstruct mfd_cell {\n\tconst char *name;\n\tint id;\n\tint level;\n\tint (*suspend)(struct platform_device *);\n\tint (*resume)(struct platform_device *);\n\tconst void *platform_data;\n\tsize_t pdata_size;\n\tconst struct mfd_cell_acpi_match *acpi_match;\n\tconst struct software_node *swnode;\n\tconst char *of_compatible;\n\tu64 of_reg;\n\tbool use_of_reg;\n\tint num_resources;\n\tconst struct resource *resources;\n\tbool ignore_resource_conflicts;\n\tbool pm_runtime_no_callbacks;\n\tint num_parent_supplies;\n\tconst char * const *parent_supplies;\n};\n\nstruct mfd_cell_acpi_match {\n\tconst char *pnpid;\n\tconst long long unsigned int adr;\n};\n\nstruct mfd_of_node_entry {\n\tstruct list_head list;\n\tstruct device *dev;\n\tstruct device_node *np;\n};\n\nstruct mhp_params {\n\tstruct vmem_altmap *altmap;\n\tpgprot_t pgprot;\n\tstruct dev_pagemap *pgmap;\n};\n\nstruct mhu_db_channel {\n\tstruct arm_mhu *mhu;\n\tunsigned int pchan;\n\tunsigned int doorbell;\n};\n\nstruct mi_state {\n\tu16 eisr;\n\tu16 elrsr;\n\tbool pend;\n};\n\nstruct micron_on_die_ecc {\n\tbool forced;\n\tbool enabled;\n\tvoid *rawbuf;\n};\n\nstruct micron_nand {\n\tstruct micron_on_die_ecc ecc;\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_mpol {\n\tstruct mempolicy *pol;\n\tlong unsigned int ilx;\n};\n\nstruct migration_swap_arg {\n\tstruct task_struct *src_task;\n\tstruct task_struct *dst_task;\n\tint src_cpu;\n\tint dst_cpu;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct phy_package_shared;\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n\tstruct phy_package_shared *shared[32];\n};\n\nstruct mii_if_info {\n\tint phy_id;\n\tint advertising;\n\tint phy_id_mask;\n\tint reg_num_mask;\n\tunsigned int full_duplex: 1;\n\tunsigned int force_media: 1;\n\tunsigned int supports_gmii: 1;\n\tstruct net_device *dev;\n\tint (*mdio_read)(struct net_device *, int, int);\n\tvoid (*mdio_write)(struct net_device *, int, int, int);\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct min_heap_callbacks {\n\tbool (*less)(const void *, const void *, void *);\n\tvoid (*swp)(void *, void *, void *);\n};\n\nstruct min_heap_char {\n\tsize_t nr;\n\tsize_t size;\n\tchar *data;\n\tchar preallocated[0];\n};\n\ntypedef struct min_heap_char min_heap_char;\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nstruct tcf_proto;\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct mipi_dsi_host;\n\nstruct mipi_dsi_device {\n\tstruct mipi_dsi_host *host;\n\tstruct device dev;\n\tbool attached;\n\tchar name[20];\n\tunsigned int channel;\n\tunsigned int lanes;\n\tenum mipi_dsi_pixel_format format;\n\tlong unsigned int mode_flags;\n\tlong unsigned int hs_rate;\n\tlong unsigned int lp_rate;\n\tstruct drm_dsc_config *dsc;\n};\n\nstruct mipi_dsi_device_info {\n\tchar type[20];\n\tu32 channel;\n\tstruct device_node *node;\n};\n\nstruct mipi_dsi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct mipi_dsi_device *);\n\tvoid (*remove)(struct mipi_dsi_device *);\n\tvoid (*shutdown)(struct mipi_dsi_device *);\n};\n\nstruct mipi_dsi_host_ops;\n\nstruct mipi_dsi_host {\n\tstruct device *dev;\n\tconst struct mipi_dsi_host_ops *ops;\n\tstruct list_head list;\n};\n\nstruct mipi_dsi_msg;\n\nstruct mipi_dsi_host_ops {\n\tint (*attach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tint (*detach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tssize_t (*transfer)(struct mipi_dsi_host *, const struct mipi_dsi_msg *);\n};\n\nstruct mipi_dsi_msg {\n\tu8 channel;\n\tu8 type;\n\tu16 flags;\n\tsize_t tx_len;\n\tconst void *tx_buf;\n\tsize_t rx_len;\n\tvoid *rx_buf;\n};\n\nstruct mipi_dsi_multi_context {\n\tstruct mipi_dsi_device *dsi;\n\tint accum_err;\n};\n\nstruct mipi_dsi_packet {\n\tsize_t size;\n\tu8 header[4];\n\tsize_t payload_length;\n\tconst u8 *payload;\n};\n\nstruct mipi_phy_device_desc {\n\tint num_phys;\n\tint num_regmaps;\n\tconst char *regmap_names[4];\n\tstruct exynos_mipi_phy_desc phys[5];\n};\n\nstruct ml_effect_state {\n\tstruct ff_effect *effect;\n\tlong unsigned int flags;\n\tint count;\n\tlong unsigned int play_at;\n\tlong unsigned int stop_at;\n\tlong unsigned int adj_at;\n};\n\nstruct ml_device {\n\tvoid *private;\n\tstruct ml_effect_state states[16];\n\tint gain;\n\tstruct timer_list timer;\n\tstruct input_dev *dev;\n\tint (*play_effect)(struct input_dev *, void *, struct ff_effect *);\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tstruct ethtool_mm_stats stats;\n};\n\ntypedef struct mm_struct *class_mmap_read_lock_t;\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n};\n\nstruct mmu_notifier_subscriptions;\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 64;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct rcuwait vma_writer_wait;\n\t\tseqcount_t mm_lock_seq;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[50];\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct task_struct *owner;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tstruct mmu_notifier_subscriptions *notifier_subscriptions;\n\t\tlong unsigned int numa_next_scan;\n\t\tlong unsigned int numa_scan_offset;\n\t\tint numa_scan_seq;\n\t\tatomic_t tlb_flush_pending;\n\t\tatomic_t tlb_flush_batched;\n\t\tstruct uprobes_state uprobes_state;\n\t\tatomic_long_t hugetlb_usage;\n\t\tstruct work_struct async_put_work;\n\t\tlong unsigned int ksm_merging_pages;\n\t\tlong unsigned int ksm_rmap_items;\n\t\tatomic_long_t ksm_zero_pages;\n\t\tmm_id_t mm_id;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n\tstruct task_struct *owner;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct mmap_batch_state {\n\tdomid_t domain;\n\tlong unsigned int va;\n\tstruct vm_area_struct *vma;\n\tint index;\n\tint global_error;\n\tint version;\n\txen_pfn_t *user_gfn;\n\tint *user_err;\n};\n\nstruct mmap_gfn_state {\n\tlong unsigned int va;\n\tstruct vm_area_struct *vma;\n\tdomid_t domain;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mmc_blk_busy_data {\n\tstruct mmc_card *card;\n\tu32 status;\n};\n\nstruct mmc_ctx {\n\tstruct task_struct *task;\n};\n\nstruct mmc_blk_data;\n\nstruct mmc_queue {\n\tstruct mmc_card *card;\n\tstruct mmc_ctx ctx;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct mmc_blk_data *blkdata;\n\tstruct request_queue *queue;\n\tspinlock_t lock;\n\tint in_flight[3];\n\tunsigned int cqe_busy;\n\tbool busy;\n\tbool recovery_needed;\n\tbool in_recovery;\n\tbool rw_wait;\n\tbool waiting;\n\tstruct work_struct recovery_work;\n\twait_queue_head_t wait;\n\tstruct request *recovery_req;\n\tstruct request *complete_req;\n\tstruct mutex complete_lock;\n\tstruct work_struct complete_work;\n};\n\nstruct mmc_blk_data {\n\tstruct device *parent;\n\tstruct gendisk *disk;\n\tstruct mmc_queue queue;\n\tstruct list_head part;\n\tstruct list_head rpmbs;\n\tunsigned int flags;\n\tstruct kref kref;\n\tunsigned int read_only;\n\tunsigned int part_type;\n\tunsigned int reset_done;\n\tunsigned int part_curr;\n\tint area_type;\n\tstruct dentry *status_dentry;\n\tstruct dentry *ext_csd_dentry;\n};\n\nstruct mmc_ioc_cmd {\n\tint write_flag;\n\tint is_acmd;\n\t__u32 opcode;\n\t__u32 arg;\n\t__u32 response[4];\n\tunsigned int flags;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int postsleep_min_us;\n\tunsigned int postsleep_max_us;\n\tunsigned int data_timeout_ns;\n\tunsigned int cmd_timeout_ms;\n\t__u32 __pad;\n\t__u64 data_ptr;\n};\n\nstruct mmc_rpmb_data;\n\nstruct mmc_blk_ioc_data {\n\tstruct mmc_ioc_cmd ic;\n\tunsigned char *buf;\n\tu64 buf_bytes;\n\tunsigned int flags;\n\tstruct mmc_rpmb_data *rpmb;\n};\n\nstruct uhs2_command {\n\tu16 header;\n\tu16 arg;\n\t__be32 payload[2];\n\tu8 payload_len;\n\tu8 packet_len;\n\tu8 tmode_half_duplex;\n\tu8 uhs2_resp[20];\n\tu8 uhs2_resp_len;\n};\n\nstruct mmc_request {\n\tstruct mmc_command *sbc;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tstruct mmc_command *stop;\n\tstruct completion completion;\n\tstruct completion cmd_completion;\n\tvoid (*done)(struct mmc_request *);\n\tvoid (*recovery_notifier)(struct mmc_request *);\n\tstruct mmc_host *host;\n\tbool cap_cmd_during_tfr;\n\tint tag;\n\tstruct uhs2_command uhs2_cmd;\n};\n\nstruct mmc_data {\n\tunsigned int timeout_ns;\n\tunsigned int timeout_clks;\n\tunsigned int blksz;\n\tunsigned int blocks;\n\tunsigned int blk_addr;\n\tint error;\n\tunsigned int flags;\n\tunsigned int bytes_xfered;\n\tstruct mmc_command *stop;\n\tstruct mmc_request *mrq;\n\tunsigned int sg_len;\n\tint sg_count;\n\tstruct scatterlist *sg;\n\ts32 host_cookie;\n};\n\nstruct mmc_blk_request {\n\tstruct mmc_request mrq;\n\tstruct mmc_command sbc;\n\tstruct mmc_command cmd;\n\tstruct mmc_command stop;\n\tstruct mmc_data data;\n};\n\nstruct mmc_bus_ops {\n\tvoid (*remove)(struct mmc_host *);\n\tvoid (*detect)(struct mmc_host *);\n\tint (*pre_suspend)(struct mmc_host *);\n\tint (*suspend)(struct mmc_host *);\n\tint (*resume)(struct mmc_host *);\n\tint (*runtime_suspend)(struct mmc_host *);\n\tint (*runtime_resume)(struct mmc_host *);\n\tint (*alive)(struct mmc_host *);\n\tint (*shutdown)(struct mmc_host *);\n\tint (*hw_reset)(struct mmc_host *);\n\tint (*sw_reset)(struct mmc_host *);\n\tbool (*cache_enabled)(struct mmc_host *);\n\tint (*flush_cache)(struct mmc_host *);\n\tint (*handle_undervoltage)(struct mmc_host *);\n};\n\nstruct mmc_busy_data {\n\tstruct mmc_card *card;\n\tbool retry_crc_err;\n\tenum mmc_busy_cmd busy_cmd;\n};\n\nstruct mmc_cid {\n\tunsigned int manfid;\n\tchar prod_name[8];\n\tunsigned char prv;\n\tunsigned int serial;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char hwrev;\n\tunsigned char fwrev;\n\tunsigned char month;\n};\n\nstruct mmc_csd {\n\tunsigned char structure;\n\tunsigned char mmca_vsn;\n\tshort unsigned int cmdclass;\n\tshort unsigned int taac_clks;\n\tunsigned int taac_ns;\n\tunsigned int c_size;\n\tunsigned int r2w_factor;\n\tunsigned int max_dtr;\n\tunsigned int erase_size;\n\tunsigned int wp_grp_size;\n\tunsigned int read_blkbits;\n\tunsigned int write_blkbits;\n\tsector_t capacity;\n\tunsigned int read_partial: 1;\n\tunsigned int read_misalign: 1;\n\tunsigned int write_partial: 1;\n\tunsigned int write_misalign: 1;\n\tunsigned int dsr_imp: 1;\n};\n\nstruct mmc_ext_csd {\n\tu8 rev;\n\tu8 erase_group_def;\n\tu8 sec_feature_support;\n\tu8 rel_sectors;\n\tu8 rel_param;\n\tbool enhanced_rpmb_supported;\n\tu8 part_config;\n\tu8 cache_ctrl;\n\tu8 rst_n_function;\n\tunsigned int part_time;\n\tunsigned int sa_timeout;\n\tunsigned int generic_cmd6_time;\n\tunsigned int power_off_longtime;\n\tu8 power_off_notification;\n\tunsigned int hs_max_dtr;\n\tunsigned int hs200_max_dtr;\n\tunsigned int sectors;\n\tunsigned int hc_erase_size;\n\tunsigned int hc_erase_timeout;\n\tunsigned int sec_trim_mult;\n\tunsigned int sec_erase_mult;\n\tunsigned int trim_timeout;\n\tbool partition_setting_completed;\n\tlong long unsigned int enhanced_area_offset;\n\tunsigned int enhanced_area_size;\n\tunsigned int cache_size;\n\tbool hpi_en;\n\tbool hpi;\n\tunsigned int hpi_cmd;\n\tbool bkops;\n\tbool man_bkops_en;\n\tbool auto_bkops_en;\n\tunsigned int data_sector_size;\n\tunsigned int data_tag_unit_size;\n\tunsigned int boot_ro_lock;\n\tbool boot_ro_lockable;\n\tbool ffu_capable;\n\tbool cmdq_en;\n\tbool cmdq_support;\n\tunsigned int cmdq_depth;\n\tu8 fwrev[8];\n\tu8 raw_exception_status;\n\tu8 raw_partition_support;\n\tu8 raw_rpmb_size_mult;\n\tu8 raw_erased_mem_count;\n\tu8 strobe_support;\n\tu8 raw_ext_csd_structure;\n\tu8 raw_card_type;\n\tu8 raw_driver_strength;\n\tu8 out_of_int_time;\n\tu8 raw_pwr_cl_52_195;\n\tu8 raw_pwr_cl_26_195;\n\tu8 raw_pwr_cl_52_360;\n\tu8 raw_pwr_cl_26_360;\n\tu8 raw_s_a_timeout;\n\tu8 raw_hc_erase_gap_size;\n\tu8 raw_erase_timeout_mult;\n\tu8 raw_hc_erase_grp_size;\n\tu8 raw_boot_mult;\n\tu8 raw_sec_trim_mult;\n\tu8 raw_sec_erase_mult;\n\tu8 raw_sec_feature_support;\n\tu8 raw_trim_mult;\n\tu8 raw_pwr_cl_200_195;\n\tu8 raw_pwr_cl_200_360;\n\tu8 raw_pwr_cl_ddr_52_195;\n\tu8 raw_pwr_cl_ddr_52_360;\n\tu8 raw_pwr_cl_ddr_200_360;\n\tu8 raw_bkops_status;\n\tu8 raw_sectors[4];\n\tu8 pre_eol_info;\n\tu8 device_life_time_est_typ_a;\n\tu8 device_life_time_est_typ_b;\n\tunsigned int feature_support;\n};\n\nstruct sd_scr {\n\tunsigned char sda_vsn;\n\tunsigned char sda_spec3;\n\tunsigned char sda_spec4;\n\tunsigned char sda_specx;\n\tunsigned char bus_widths;\n\tunsigned char cmds;\n};\n\nstruct sd_ssr {\n\tunsigned int au;\n\tunsigned int erase_timeout;\n\tunsigned int erase_offset;\n};\n\nstruct sd_switch_caps {\n\tunsigned int hs_max_dtr;\n\tunsigned int uhs_max_dtr;\n\tunsigned int sd3_bus_mode;\n\tunsigned int sd3_drv_type;\n\tunsigned int sd3_curr_limit;\n};\n\nstruct sd_ext_reg {\n\tu8 fno;\n\tu8 page;\n\tu16 offset;\n\tu8 rev;\n\tu8 feature_enabled;\n\tu8 feature_support;\n};\n\nstruct sd_uhs2_config {\n\tu32 node_id;\n\tu32 n_fcu;\n\tu32 maxblk_len;\n\tu8 n_lanes;\n\tu8 dadr_len;\n\tu8 app_type;\n\tu8 phy_minor_rev;\n\tu8 phy_major_rev;\n\tu8 can_hibernate;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_minor_rev;\n\tu8 link_major_rev;\n\tu8 dev_type;\n\tu8 n_data_gap;\n\tu32 n_fcu_set;\n\tu32 maxblk_len_set;\n\tu8 n_lanes_set;\n\tu8 speed_range_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct sdio_cccr {\n\tunsigned int sdio_vsn;\n\tunsigned int sd_vsn;\n\tunsigned int multi_block: 1;\n\tunsigned int low_speed: 1;\n\tunsigned int wide_bus: 1;\n\tunsigned int high_power: 1;\n\tunsigned int high_speed: 1;\n\tunsigned int disable_cd: 1;\n\tunsigned int enable_async_irq: 1;\n};\n\nstruct sdio_cis {\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int blksize;\n\tunsigned int max_dtr;\n};\n\nstruct mmc_part {\n\tu64 size;\n\tunsigned int part_cfg;\n\tchar name[20];\n\tbool force_ro;\n\tunsigned int area_type;\n};\n\nstruct sdio_func_tuple;\n\nstruct mmc_card {\n\tstruct mmc_host *host;\n\tstruct device dev;\n\tu32 ocr;\n\tunsigned int rca;\n\tunsigned int type;\n\tunsigned int state;\n\tunsigned int quirks;\n\tunsigned int quirk_max_rate;\n\tbool written_flag;\n\tbool reenable_cmdq;\n\tunsigned int erase_size;\n\tunsigned int erase_shift;\n\tunsigned int pref_erase;\n\tunsigned int eg_boundary;\n\tunsigned int erase_arg;\n\tu8 erased_byte;\n\tunsigned int wp_grp_size;\n\tu32 raw_cid[4];\n\tu32 raw_csd[4];\n\tu32 raw_scr[2];\n\tu32 raw_ssr[16];\n\tstruct mmc_cid cid;\n\tstruct mmc_csd csd;\n\tstruct mmc_ext_csd ext_csd;\n\tstruct sd_scr scr;\n\tstruct sd_ssr ssr;\n\tstruct sd_switch_caps sw_caps;\n\tstruct sd_ext_reg ext_power;\n\tstruct sd_ext_reg ext_perf;\n\tstruct sd_uhs2_config uhs2_config;\n\tunsigned int sdio_funcs;\n\tatomic_t sdio_funcs_probed;\n\tstruct sdio_cccr cccr;\n\tstruct sdio_cis cis;\n\tstruct sdio_func *sdio_func[7];\n\tstruct sdio_func *sdio_single_irq;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n\tunsigned int sd_bus_speed;\n\tunsigned int mmc_avail_type;\n\tunsigned int drive_strength;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_part part[7];\n\tunsigned int nr_parts;\n\tstruct workqueue_struct *complete_wq;\n};\n\nstruct mmc_clk_phase {\n\tbool valid;\n\tu16 in_deg;\n\tu16 out_deg;\n};\n\nstruct mmc_clk_phase_map {\n\tstruct mmc_clk_phase phase[11];\n};\n\nstruct mmc_cqe_ops {\n\tint (*cqe_enable)(struct mmc_host *, struct mmc_card *);\n\tvoid (*cqe_disable)(struct mmc_host *);\n\tint (*cqe_request)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_post_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*cqe_off)(struct mmc_host *);\n\tint (*cqe_wait_for_idle)(struct mmc_host *);\n\tbool (*cqe_timeout)(struct mmc_host *, struct mmc_request *, bool *);\n\tvoid (*cqe_recovery_start)(struct mmc_host *);\n\tvoid (*cqe_recovery_finish)(struct mmc_host *);\n};\n\nstruct mmc_driver {\n\tstruct device_driver drv;\n\tint (*probe)(struct mmc_card *);\n\tvoid (*remove)(struct mmc_card *);\n\tvoid (*shutdown)(struct mmc_card *);\n};\n\nstruct mmc_fixup {\n\tconst char *name;\n\tu64 rev_start;\n\tu64 rev_end;\n\tunsigned int manfid;\n\tshort unsigned int oemid;\n\tshort unsigned int year;\n\tunsigned char month;\n\tu16 cis_vendor;\n\tu16 cis_device;\n\tunsigned int ext_csd_rev;\n\tconst char *of_compatible;\n\tvoid (*vendor_fixup)(struct mmc_card *, int);\n\tint data;\n};\n\nstruct mmc_gpio {\n\tstruct gpio_desc *ro_gpio;\n\tstruct gpio_desc *cd_gpio;\n\tirq_handler_t cd_gpio_isr;\n\tchar *ro_label;\n\tchar *cd_label;\n\tu32 cd_debounce_delay_ms;\n\tint cd_irq;\n};\n\nstruct sd_uhs2_caps {\n\tu32 dap;\n\tu32 gap;\n\tu32 group_desc;\n\tu32 maxblk_len;\n\tu32 n_fcu;\n\tu8 n_lanes;\n\tu8 addr64;\n\tu8 card_type;\n\tu8 phy_rev;\n\tu8 speed_range;\n\tu8 n_lss_sync;\n\tu8 n_lss_dir;\n\tu8 link_rev;\n\tu8 host_type;\n\tu8 n_data_gap;\n\tu32 maxblk_len_set;\n\tu32 n_fcu_set;\n\tu8 n_lanes_set;\n\tu8 n_lss_sync_set;\n\tu8 n_lss_dir_set;\n\tu8 n_data_gap_set;\n\tu8 max_retry_set;\n};\n\nstruct mmc_ios {\n\tunsigned int clock;\n\tshort unsigned int vdd;\n\tunsigned int power_delay_ms;\n\tunsigned char bus_mode;\n\tunsigned char chip_select;\n\tunsigned char power_mode;\n\tunsigned char bus_width;\n\tunsigned char timing;\n\tunsigned char signal_voltage;\n\tunsigned char vqmmc2_voltage;\n\tunsigned char drv_type;\n\tbool enhanced_strobe;\n};\n\nstruct mmc_slot {\n\tint cd_irq;\n\tbool cd_wake_enabled;\n\tvoid *handler_priv;\n};\n\nstruct mmc_supply {\n\tstruct regulator *vmmc;\n\tstruct regulator *vqmmc;\n\tstruct regulator *vqmmc2;\n\tstruct notifier_block vmmc_nb;\n\tstruct work_struct uv_work;\n};\n\nstruct mmc_host_ops;\n\nstruct mmc_pwrseq;\n\nstruct mmc_host {\n\tstruct device *parent;\n\tstruct device class_dev;\n\tint index;\n\tconst struct mmc_host_ops *ops;\n\tstruct mmc_pwrseq *pwrseq;\n\tunsigned int f_min;\n\tunsigned int f_max;\n\tunsigned int f_init;\n\tu32 ocr_avail;\n\tu32 ocr_avail_sdio;\n\tu32 ocr_avail_sd;\n\tu32 ocr_avail_mmc;\n\tstruct wakeup_source *ws;\n\tu32 max_current_330;\n\tu32 max_current_300;\n\tu32 max_current_180;\n\tu32 caps;\n\tu32 caps2;\n\tbool uhs2_sd_tran;\n\tbool uhs2_app_cmd;\n\tstruct sd_uhs2_caps uhs2_caps;\n\tint fixed_drv_type;\n\tmmc_pm_flag_t pm_caps;\n\tunsigned int max_seg_size;\n\tshort unsigned int max_segs;\n\tshort unsigned int unused;\n\tunsigned int max_req_size;\n\tunsigned int max_blk_size;\n\tunsigned int max_blk_count;\n\tunsigned int max_busy_timeout;\n\tspinlock_t lock;\n\tstruct mmc_ios ios;\n\tbool claimed;\n\tunsigned int use_spi_crc: 1;\n\tunsigned int doing_init_tune: 1;\n\tunsigned int doing_retune: 1;\n\tunsigned int retune_crc_disable: 1;\n\tunsigned int can_dma_map_merge: 1;\n\tunsigned int vqmmc_enabled: 1;\n\tunsigned int undervoltage: 1;\n\tint rescan_disable;\n\tint rescan_entered;\n\tbool can_retune;\n\tbool retune_now;\n\tbool retune_paused;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct timer_list retune_timer;\n\tbool trigger_card_event;\n\tstruct mmc_card *card;\n\twait_queue_head_t wq;\n\tstruct mmc_ctx *claimer;\n\tint claim_cnt;\n\tstruct mmc_ctx default_ctx;\n\tstruct delayed_work detect;\n\tint detect_change;\n\tstruct mmc_slot slot;\n\tconst struct mmc_bus_ops *bus_ops;\n\tunsigned int sdio_irqs;\n\tstruct task_struct *sdio_irq_thread;\n\tstruct work_struct sdio_irq_work;\n\tbool sdio_irq_pending;\n\tatomic_t sdio_irq_thread_abort;\n\tmmc_pm_flag_t pm_flags;\n\tstruct led_trigger *led;\n\tbool regulator_enabled;\n\tstruct mmc_supply supply;\n\tstruct dentry *debugfs_root;\n\tstruct mmc_request *ongoing_mrq;\n\tunsigned int actual_clock;\n\tunsigned int slotno;\n\tint dsr_req;\n\tu32 dsr;\n\tconst struct mmc_cqe_ops *cqe_ops;\n\tvoid *cqe_private;\n\tint cqe_qdepth;\n\tbool cqe_enabled;\n\tbool cqe_on;\n\tbool hsq_enabled;\n\tint hsq_depth;\n\tu32 err_stats[15];\n\tu32 max_sd_hs_hz;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct mmc_host_ops {\n\tvoid (*post_req)(struct mmc_host *, struct mmc_request *, int);\n\tvoid (*pre_req)(struct mmc_host *, struct mmc_request *);\n\tvoid (*request)(struct mmc_host *, struct mmc_request *);\n\tint (*request_atomic)(struct mmc_host *, struct mmc_request *);\n\tvoid (*set_ios)(struct mmc_host *, struct mmc_ios *);\n\tint (*get_ro)(struct mmc_host *);\n\tint (*get_cd)(struct mmc_host *);\n\tvoid (*enable_sdio_irq)(struct mmc_host *, int);\n\tvoid (*ack_sdio_irq)(struct mmc_host *);\n\tvoid (*init_card)(struct mmc_host *, struct mmc_card *);\n\tint (*start_signal_voltage_switch)(struct mmc_host *, struct mmc_ios *);\n\tint (*card_busy)(struct mmc_host *);\n\tint (*execute_tuning)(struct mmc_host *, u32);\n\tint (*prepare_hs400_tuning)(struct mmc_host *, struct mmc_ios *);\n\tint (*execute_hs400_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*prepare_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*execute_sd_hs_tuning)(struct mmc_host *, struct mmc_card *);\n\tint (*hs400_prepare_ddr)(struct mmc_host *);\n\tvoid (*hs400_downgrade)(struct mmc_host *);\n\tvoid (*hs400_complete)(struct mmc_host *);\n\tvoid (*hs400_enhanced_strobe)(struct mmc_host *, struct mmc_ios *);\n\tint (*select_drive_strength)(struct mmc_card *, unsigned int, int, int, int *);\n\tvoid (*card_hw_reset)(struct mmc_host *);\n\tvoid (*card_event)(struct mmc_host *);\n\tint (*multi_io_quirk)(struct mmc_card *, unsigned int, int);\n\tint (*init_sd_express)(struct mmc_host *, struct mmc_ios *);\n\tint (*uhs2_control)(struct mmc_host *, enum sd_uhs2_operation);\n};\n\nstruct mmc_hsq {\n\tstruct mmc_host *mmc;\n\tstruct mmc_request *mrq;\n\twait_queue_head_t wait_queue;\n\tstruct hsq_slot *slot;\n\tspinlock_t lock;\n\tstruct work_struct retry_work;\n\tint next_tag;\n\tint num_slots;\n\tint qcnt;\n\tint tail_tag;\n\tint tag_slot[64];\n\tbool enabled;\n\tbool waiting_for_idle;\n\tbool recovery_halt;\n};\n\nstruct mmc_ioc_multi_cmd {\n\t__u64 num_of_cmds;\n\tstruct mmc_ioc_cmd cmds[0];\n};\n\nstruct mmc_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct mmc_pwrseq_ops;\n\nstruct mmc_pwrseq {\n\tconst struct mmc_pwrseq_ops *ops;\n\tstruct device *dev;\n\tstruct list_head pwrseq_node;\n\tstruct module *owner;\n};\n\nstruct mmc_pwrseq_emmc {\n\tstruct mmc_pwrseq pwrseq;\n\tstruct notifier_block reset_nb;\n\tstruct gpio_desc *reset_gpio;\n};\n\nstruct mmc_pwrseq_ops {\n\tvoid (*pre_power_on)(struct mmc_host *);\n\tvoid (*post_power_on)(struct mmc_host *);\n\tvoid (*power_off)(struct mmc_host *);\n\tvoid (*reset)(struct mmc_host *);\n};\n\nstruct mmc_pwrseq_simple {\n\tstruct mmc_pwrseq pwrseq;\n\tbool clk_enabled;\n\tu32 post_power_on_delay_ms;\n\tu32 power_off_delay_us;\n\tstruct clk *ext_clk;\n\tstruct gpio_descs *reset_gpios;\n\tstruct reset_control *reset_ctrl;\n};\n\nstruct mmc_queue_req {\n\tstruct mmc_blk_request brq;\n\tstruct scatterlist *sg;\n\tenum mmc_drv_op drv_op;\n\tint drv_op_result;\n\tvoid *drv_op_data;\n\tunsigned int ioc_count;\n\tint retries;\n};\n\nstruct rpmb_dev;\n\nstruct mmc_rpmb_data {\n\tstruct device dev;\n\tstruct cdev chrdev;\n\tint id;\n\tunsigned int part_index;\n\tstruct mmc_blk_data *md;\n\tstruct rpmb_dev *rdev;\n\tstruct list_head node;\n};\n\nstruct spi_delay {\n\tu16 value;\n\tu8 unit;\n};\n\nstruct spi_transfer {\n\tconst void *tx_buf;\n\tvoid *rx_buf;\n\tunsigned int len;\n\tu16 error;\n\tbool tx_sg_mapped;\n\tbool rx_sg_mapped;\n\tstruct sg_table tx_sg;\n\tstruct sg_table rx_sg;\n\tdma_addr_t tx_dma;\n\tdma_addr_t rx_dma;\n\tunsigned int dummy_data: 1;\n\tunsigned int cs_off: 1;\n\tunsigned int cs_change: 1;\n\tunsigned int tx_nbits: 4;\n\tunsigned int rx_nbits: 4;\n\tunsigned int multi_lane_mode: 2;\n\tunsigned int timestamped: 1;\n\tbool dtr_mode;\n\tu8 bits_per_word;\n\tstruct spi_delay delay;\n\tstruct spi_delay cs_change_delay;\n\tstruct spi_delay word_delay;\n\tu32 speed_hz;\n\tu32 effective_speed_hz;\n\tunsigned int offload_flags;\n\tunsigned int ptp_sts_word_pre;\n\tunsigned int ptp_sts_word_post;\n\tstruct ptp_system_timestamp *ptp_sts;\n\tstruct list_head transfer_list;\n};\n\nstruct spi_offload;\n\nstruct spi_message {\n\tstruct list_head transfers;\n\tstruct spi_device *spi;\n\tbool pre_optimized;\n\tbool optimized;\n\tbool prepared;\n\tint status;\n\tvoid (*complete)(void *);\n\tvoid *context;\n\tunsigned int frame_length;\n\tunsigned int actual_length;\n\tstruct list_head queue;\n\tvoid *state;\n\tvoid *opt_state;\n\tstruct spi_offload *offload;\n\tstruct list_head resources;\n};\n\nstruct mmc_spi_platform_data;\n\nstruct scratch;\n\nstruct mmc_spi_host {\n\tstruct mmc_host *mmc;\n\tstruct spi_device *spi;\n\tunsigned char power_mode;\n\tu16 powerup_msecs;\n\tstruct mmc_spi_platform_data *pdata;\n\tstruct spi_transfer token;\n\tstruct spi_transfer t;\n\tstruct spi_transfer crc;\n\tstruct spi_transfer early_status;\n\tstruct spi_message m;\n\tstruct spi_transfer status;\n\tstruct spi_message readback;\n\tstruct scratch *data;\n\tvoid *ones;\n};\n\nstruct mmc_spi_platform_data {\n\tint (*init)(struct device *, irqreturn_t (*)(int, void *), void *);\n\tvoid (*exit)(struct device *, void *);\n\tlong unsigned int caps;\n\tlong unsigned int caps2;\n\tu16 detect_delay;\n\tu16 powerup_msecs;\n\tu32 ocr_mask;\n\tvoid (*setpower)(struct device *, unsigned int);\n};\n\nstruct mmci_dmae_next {\n\tstruct dma_async_tx_descriptor *desc;\n\tstruct dma_chan *chan;\n};\n\nstruct mmci_dmae_priv {\n\tstruct dma_chan *cur;\n\tstruct dma_chan *rx_channel;\n\tstruct dma_chan *tx_channel;\n\tstruct dma_async_tx_descriptor *desc_current;\n\tstruct mmci_dmae_next next_data;\n};\n\nstruct mmci_platform_data;\n\nstruct mmci_host_ops;\n\nstruct variant_data;\n\nstruct mmci_host {\n\tphys_addr_t phybase;\n\tvoid *base;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_command stop_abort;\n\tstruct mmc_data *data;\n\tstruct mmc_host *mmc;\n\tstruct clk *clk;\n\tu8 singleirq: 1;\n\tstruct reset_control *rst;\n\tspinlock_t lock;\n\tunsigned int mclk;\n\tunsigned int clock_cache;\n\tunsigned int cclk;\n\tu32 pwr_reg;\n\tu32 pwr_reg_add;\n\tu32 clk_reg;\n\tu32 clk_reg_add;\n\tu32 datactrl_reg;\n\tenum mmci_busy_state busy_state;\n\tu32 busy_status;\n\tu32 mask1_reg;\n\tu8 vqmmc_enabled: 1;\n\tstruct mmci_platform_data *plat;\n\tstruct mmc_host_ops *mmc_ops;\n\tstruct mmci_host_ops *ops;\n\tstruct variant_data *variant;\n\tvoid *variant_priv;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_opendrain;\n\tu8 hw_designer;\n\tu8 hw_revision: 4;\n\tstruct timer_list timer;\n\tunsigned int oldstat;\n\tu32 irq_action;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int size;\n\tint (*get_rx_fifocnt)(struct mmci_host *, u32, int);\n\tu8 use_dma: 1;\n\tu8 dma_in_progress: 1;\n\tvoid *dma_priv;\n\ts32 next_cookie;\n\tstruct delayed_work ux500_busy_timeout_work;\n};\n\nstruct mmci_host_ops {\n\tint (*validate_data)(struct mmci_host *, struct mmc_data *);\n\tint (*prep_data)(struct mmci_host *, struct mmc_data *, bool);\n\tvoid (*unprep_data)(struct mmci_host *, struct mmc_data *, int);\n\tu32 (*get_datactrl_cfg)(struct mmci_host *);\n\tvoid (*get_next_data)(struct mmci_host *, struct mmc_data *);\n\tint (*dma_setup)(struct mmci_host *);\n\tvoid (*dma_release)(struct mmci_host *);\n\tint (*dma_start)(struct mmci_host *, unsigned int *);\n\tvoid (*dma_finalize)(struct mmci_host *, struct mmc_data *);\n\tvoid (*dma_error)(struct mmci_host *);\n\tvoid (*set_clkreg)(struct mmci_host *, unsigned int);\n\tvoid (*set_pwrreg)(struct mmci_host *, unsigned int);\n\tbool (*busy_complete)(struct mmci_host *, struct mmc_command *, u32, u32);\n\tvoid (*pre_sig_volt_switch)(struct mmci_host *);\n\tint (*post_sig_volt_switch)(struct mmci_host *, struct mmc_ios *);\n};\n\nstruct mmci_platform_data {\n\tunsigned int ocr_mask;\n\tunsigned int (*status)(struct device *);\n};\n\nstruct mmd_val {\n\tint devad;\n\tu32 regnum;\n\tu16 val;\n};\n\nstruct mminit_pfnnid_cache {\n\tlong unsigned int last_start;\n\tlong unsigned int last_end;\n\tint last_nid;\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct mmu_config {\n\tu64 ttbr0;\n\tu64 ttbr1;\n\tu64 tcr;\n\tu64 mair;\n\tu64 tcr2;\n\tu64 pir;\n\tu64 pire0;\n\tu64 por_el0;\n\tu64 por_el1;\n\tu64 sctlr;\n\tu64 vttbr;\n\tu64 vtcr;\n};\n\nstruct encoded_page;\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct encoded_page *encoded_pages[0];\n};\n\nstruct mmu_table_batch;\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tstruct mmu_table_batch *batch;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n};\n\nstruct mmu_notifier_range;\n\nstruct mmu_interval_notifier_ops {\n\tbool (*invalidate)(struct mmu_interval_notifier *, const struct mmu_notifier_range *, long unsigned int);\n};\n\nstruct mmu_notifier_ops {\n\tvoid (*release)(struct mmu_notifier *, struct mm_struct *);\n\tint (*clear_flush_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*clear_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*test_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int);\n\tint (*invalidate_range_start)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range_end)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*arch_invalidate_secondary_tlbs)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tstruct mmu_notifier * (*alloc_notifier)(struct mm_struct *);\n\tvoid (*free_notifier)(struct mmu_notifier *);\n};\n\nstruct mmu_notifier_range {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int flags;\n\tenum mmu_notifier_event event;\n\tvoid *owner;\n};\n\nstruct mmu_notifier_subscriptions {\n\tstruct hlist_head list;\n\tbool has_itree;\n\tspinlock_t lock;\n\tlong unsigned int invalidate_seq;\n\tlong unsigned int active_invalidate_ranges;\n\tstruct rb_root_cached itree;\n\twait_queue_head_t wq;\n\tstruct hlist_head deferred_list;\n};\n\nstruct mmu_table_batch {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tvoid *tables[0];\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 64;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct mobiveil_pab_ops {\n\tbool (*link_up)(struct mobiveil_pcie *);\n};\n\nstruct mobiveil_rp_ops {\n\tint (*interrupt_init)(struct mobiveil_pcie *);\n};\n\nstruct mod_plt_sec {\n\tint plt_shndx;\n\tint plt_num_entries;\n\tint plt_max_entries;\n};\n\nstruct plt_entry;\n\nstruct mod_arch_specific {\n\tstruct mod_plt_sec core;\n\tstruct mod_plt_sec init;\n\tstruct plt_entry *ftrace_trampolines;\n\tstruct plt_entry *init_ftrace_trampolines;\n};\n\nstruct mod_clock {\n\tstruct rzv2h_cpg_priv *priv;\n\tunsigned int mstop_data;\n\tstruct clk_hw hw;\n\tbool no_pm;\n\tu8 on_index;\n\tu8 on_bit;\n\ts8 mon_index;\n\tu8 mon_bit;\n\ts8 ext_clk_mux_index;\n};\n\nstruct mstop;\n\nstruct mod_clock___2 {\n\tstruct clk_hw hw;\n\tstruct rzg2l_cpg_priv *priv;\n\tstruct mod_clock___2 *sibling;\n\tstruct mstop *mstop;\n\tstruct mod_clock___2 **shared_mstop_clks;\n\tu16 off;\n\tu8 bit;\n\tu8 num_shared_mstop_clks;\n\tbool enabled;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf64_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct mode_info {\n\tconst char *mode;\n\tu32 magic;\n\tstruct list_head list;\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n\tstruct mod_tree_node mtn;\n};\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_event_call;\n\nstruct trace_eval_map;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[56];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_string {\n\tstruct list_head next;\n\tstruct module *module;\n\tchar *str;\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct mountres {\n\tint errno;\n\tstruct nfs_fh *fh;\n\tunsigned int *auth_count;\n\trpc_authflavor_t *auth_flavors;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tunsigned int can_map: 1;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tloff_t end_pos;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n\tunsigned int journalled_more_data: 1;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpc8xxx_gpio_chip {\n\tstruct gpio_generic_chip chip;\n\tvoid *regs;\n\traw_spinlock_t lock;\n\tint (*direction_output)(struct gpio_chip *, unsigned int, int);\n\tstruct irq_domain *irq;\n\tint irqn;\n};\n\nstruct mpc8xxx_gpio_devtype {\n\tint (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);\n\tint (*gpio_get)(struct gpio_chip *, unsigned int);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n};\n\nstruct mpfs_ccc_data {\n\tvoid **pll_base;\n\tstruct device *dev;\n\tstruct clk_hw_onecell_data hw_data;\n};\n\nstruct mpfs_ccc_out_hw_clock {\n\tstruct clk_divider divider;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n};\n\nstruct mpfs_ccc_pll_hw_clock {\n\tvoid *base;\n\tconst char *name;\n\tconst struct clk_parent_data *parents;\n\tunsigned int id;\n\tu32 reg_offset;\n\tu32 shift;\n\tu32 width;\n\tu32 flags;\n\tstruct clk_hw hw;\n\tstruct clk_init_data init;\n};\n\nstruct mpfs_cfg_clock {\n\tstruct regmap *map;\n\tconst struct clk_div_table *table;\n\tu8 map_offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n};\n\nstruct mpfs_cfg_hw_clock {\n\tstruct clk_hw hw;\n\tstruct mpfs_cfg_clock cfg;\n\tunsigned int id;\n};\n\nstruct mpfs_clock_data {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tvoid *base;\n\tvoid *msspll_base;\n\tstruct clk_hw_onecell_data hw_data;\n};\n\nstruct mpfs_msspll_hw_clock {\n\tvoid *base;\n\tstruct clk_hw hw;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n\tu32 shift;\n\tu32 width;\n\tu32 flags;\n};\n\nstruct mpfs_msspll_out_hw_clock {\n\tvoid *base;\n\tstruct clk_divider output;\n\tstruct clk_init_data init;\n\tunsigned int id;\n\tu32 reg_offset;\n};\n\nstruct mpfs_periph_clock {\n\tstruct regmap *map;\n\tu8 map_offset;\n\tu8 shift;\n};\n\nstruct mpfs_periph_hw_clock {\n\tstruct clk_hw hw;\n\tstruct mpfs_periph_clock periph;\n\tunsigned int id;\n};\n\nstruct mpfs_reset {\n\tstruct regmap *regmap;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct mpidr_hash {\n\tu64 mask;\n\tu32 shift_aff[4];\n\tu32 bits;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mpm_gic_map {\n\tint pin;\n\tirq_hw_number_t hwirq;\n};\n\nstruct mptcp_out_options {};\n\nstruct mptcp_sock {};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct mqueue_fs_context {\n\tstruct ipc_namespace *ipc_ns;\n\tbool newns;\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[12];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct posix_msg_tree_node;\n\nstruct mqueue_inode_info {\n\tspinlock_t lock;\n\tstruct inode vfs_inode;\n\twait_queue_head_t wait_q;\n\tstruct rb_root msg_tree;\n\tstruct rb_node *msg_tree_rightmost;\n\tstruct posix_msg_tree_node *node_cache;\n\tstruct mq_attr attr;\n\tstruct sigevent notify;\n\tstruct pid *notify_owner;\n\tu32 notify_self_exec_id;\n\tstruct user_namespace *notify_user_ns;\n\tstruct ucounts *ucounts;\n\tstruct sock *notify_sock;\n\tstruct sk_buff *notify_cookie;\n\tstruct ext_wait_queue e_wait_q[2];\n\tlong unsigned int qsize;\n};\n\nstruct mrq_bwmgr_int_request {\n\tuint32_t cmd;\n\tunion {\n\t\tstruct cmd_bwmgr_int_query_abi_request query_abi;\n\t\tstruct cmd_bwmgr_int_calc_and_set_request bwmgr_calc_set_req;\n\t\tstruct cmd_bwmgr_int_cap_set_request bwmgr_cap_set_req;\n\t};\n} __attribute__((packed));\n\nstruct mrq_bwmgr_int_response {\n\tunion {\n\t\tstruct cmd_bwmgr_int_calc_and_set_response bwmgr_calc_set_resp;\n\t};\n};\n\nstruct mrq_clk_request {\n\tuint32_t cmd_and_id;\n\tunion {\n\t\tstruct cmd_clk_get_rate_request clk_get_rate;\n\t\tstruct cmd_clk_set_rate_request clk_set_rate;\n\t\tstruct cmd_clk_round_rate_request clk_round_rate;\n\t\tstruct cmd_clk_get_parent_request clk_get_parent;\n\t\tstruct cmd_clk_set_parent_request clk_set_parent;\n\t\tstruct cmd_clk_enable_request clk_enable;\n\t\tstruct cmd_clk_disable_request clk_disable;\n\t\tstruct cmd_clk_is_enabled_request clk_is_enabled;\n\t\tstruct cmd_clk_properties_request clk_properties;\n\t\tstruct cmd_clk_possible_parents_request clk_possible_parents;\n\t\tstruct cmd_clk_num_possible_parents_request clk_num_possible_parents;\n\t\tstruct cmd_clk_get_possible_parent_request clk_get_possible_parent;\n\t\tstruct cmd_clk_get_all_info_request clk_get_all_info;\n\t\tstruct cmd_clk_get_max_clk_id_request clk_get_max_clk_id;\n\t\tstruct cmd_clk_get_fmax_at_vmin_request clk_get_fmax_at_vmin;\n\t};\n};\n\nstruct mrq_cpu_ndiv_limits_request {\n\tuint32_t cluster_id;\n};\n\nstruct mrq_cpu_ndiv_limits_response {\n\tuint32_t ref_clk_hz;\n\tuint16_t pdiv;\n\tuint16_t mdiv;\n\tuint16_t ndiv_max;\n\tuint16_t ndiv_min;\n};\n\nstruct mrq_cpu_vhint_request {\n\tuint32_t addr;\n\tuint32_t cluster_id;\n};\n\nstruct mrq_debug_request {\n\tuint32_t cmd;\n\tunion {\n\t\tstruct cmd_debug_fopen_request fop;\n\t\tstruct cmd_debug_fread_request frd;\n\t\tstruct cmd_debug_fwrite_request fwr;\n\t\tstruct cmd_debug_fclose_request fcl;\n\t};\n};\n\nstruct mrq_debug_response {\n\tunion {\n\t\tstruct cmd_debug_fopen_response fop;\n\t\tstruct cmd_debug_fread_response frd;\n\t};\n};\n\nstruct mrq_debugfs_request {\n\tuint32_t cmd;\n\tunion {\n\t\tstruct cmd_debugfs_fileop_request fop;\n\t\tstruct cmd_debugfs_dumpdir_request dumpdir;\n\t};\n};\n\nstruct mrq_debugfs_response {\n\tint32_t reserved;\n\tunion {\n\t\tstruct cmd_debugfs_fileop_response fop;\n\t\tstruct cmd_debugfs_dumpdir_response dumpdir;\n\t};\n};\n\nstruct mrq_emc_dvfs_latency_response {\n\tuint32_t num_pairs;\n\tstruct emc_dvfs_latency pairs[14];\n};\n\nstruct mrq_i2c_request {\n\tuint32_t cmd;\n\tstruct cmd_i2c_xfer_request xfer;\n};\n\nstruct mrq_i2c_response {\n\tstruct cmd_i2c_xfer_response xfer;\n};\n\nstruct mrq_pg_request {\n\tuint32_t cmd;\n\tuint32_t id;\n\tunion {\n\t\tstruct cmd_pg_query_abi_request query_abi;\n\t\tstruct cmd_pg_set_state_request set_state;\n\t};\n};\n\nstruct mrq_pg_response {\n\tunion {\n\t\tstruct cmd_pg_get_state_response get_state;\n\t\tstruct cmd_pg_get_name_response get_name;\n\t\tstruct cmd_pg_get_max_id_response get_max_id;\n\t};\n};\n\nstruct mrq_ping_request {\n\tuint32_t challenge;\n};\n\nstruct mrq_ping_response {\n\tuint32_t reply;\n};\n\nstruct mrq_query_abi_request {\n\tuint32_t mrq;\n};\n\nstruct mrq_query_abi_response {\n\tint32_t status;\n};\n\nstruct mrq_query_fw_tag_response {\n\tuint8_t tag[32];\n};\n\nstruct mrq_query_tag_request {\n\tuint32_t addr;\n};\n\nstruct mrq_reset_request {\n\tuint32_t cmd;\n\tuint32_t reset_id;\n};\n\nstruct ms_data {\n\tlong unsigned int quirks;\n\tstruct hid_device *hdev;\n\tstruct work_struct ff_worker;\n\t__u8 strong;\n\t__u8 weak;\n\tvoid *output_report_dmabuf;\n};\n\nstruct msdc_delay_phase {\n\tu8 maxlen;\n\tu8 start;\n\tu8 final_phase;\n};\n\nstruct mt_gpdma_desc;\n\nstruct mt_bdma_desc;\n\nstruct msdc_dma {\n\tstruct scatterlist *sg;\n\tstruct mt_gpdma_desc *gpd;\n\tstruct mt_bdma_desc *bd;\n\tdma_addr_t gpd_addr;\n\tdma_addr_t bd_addr;\n};\n\nstruct msdc_save_para {\n\tu32 msdc_cfg;\n\tu32 iocon;\n\tu32 sdc_cfg;\n\tu32 pad_tune;\n\tu32 patch_bit0;\n\tu32 patch_bit1;\n\tu32 patch_bit2;\n\tu32 pad_ds_tune;\n\tu32 pad_cmd_tune;\n\tu32 emmc50_cfg0;\n\tu32 emmc50_cfg3;\n\tu32 sdc_fifo_cfg;\n\tu32 emmc_top_control;\n\tu32 emmc_top_cmd;\n\tu32 emmc50_pad_ds_tune;\n\tu32 loop_test_control;\n};\n\nstruct msdc_tune_para {\n\tu32 iocon;\n\tu32 pad_tune;\n\tu32 pad_cmd_tune;\n\tu32 emmc_top_control;\n\tu32 emmc_top_cmd;\n};\n\nstruct mtk_mmc_compatible;\n\nstruct msdc_host {\n\tstruct device *dev;\n\tconst struct mtk_mmc_compatible *dev_comp;\n\tint cmd_rsp;\n\tspinlock_t lock;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tint error;\n\tvoid *base;\n\tvoid *top_base;\n\tstruct msdc_dma dma;\n\tu64 dma_mask;\n\tu32 timeout_ns;\n\tu32 timeout_clks;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_uhs;\n\tstruct pinctrl_state *pins_eint;\n\tstruct delayed_work req_timeout;\n\tint irq;\n\tint eint_irq;\n\tstruct reset_control *reset;\n\tstruct clk *src_clk;\n\tstruct clk *h_clk;\n\tstruct clk *bus_clk;\n\tstruct clk *src_clk_cg;\n\tstruct clk *sys_clk_cg;\n\tstruct clk *crypto_clk;\n\tstruct clk_bulk_data bulk_clks[3];\n\tu32 mclk;\n\tu32 src_clk_freq;\n\tunsigned char timing;\n\tbool vqmmc_enabled;\n\tu32 latch_ck;\n\tu32 hs400_ds_delay;\n\tu32 hs400_ds_dly3;\n\tu32 hs200_cmd_int_delay;\n\tu32 hs400_cmd_int_delay;\n\tu32 tuning_step;\n\tbool hs400_cmd_resp_sel_rising;\n\tbool hs400_mode;\n\tbool hs400_tuning;\n\tbool internal_cd;\n\tbool cqhci;\n\tbool hsq_en;\n\tstruct msdc_save_para save_para;\n\tstruct msdc_tune_para def_tune_para;\n\tstruct msdc_tune_para saved_tune_para;\n\tstruct cqhci_host *cq_host;\n\tu32 cq_ssc1_time;\n};\n\nstruct msdos_dir_entry {\n\t__u8 name[11];\n\t__u8 attr;\n\t__u8 lcase;\n\t__u8 ctime_cs;\n\t__le16 ctime;\n\t__le16 cdate;\n\t__le16 adate;\n\t__le16 starthi;\n\t__le16 time;\n\t__le16 date;\n\t__le16 start;\n\t__le32 size;\n};\n\nstruct msdos_dir_slot {\n\t__u8 id;\n\t__u8 name0_4[10];\n\t__u8 attr;\n\t__u8 reserved;\n\t__u8 alias_checksum;\n\t__u8 name5_10[12];\n\t__le16 start;\n\t__u8 name11_12[4];\n};\n\nstruct msdos_inode_info {\n\tspinlock_t cache_lru_lock;\n\tstruct list_head cache_lru;\n\tint nr_caches;\n\tunsigned int cache_valid_id;\n\tloff_t mmu_private;\n\tint i_start;\n\tint i_logstart;\n\tint i_attrs;\n\tloff_t i_pos;\n\tstruct hlist_node i_fat_hash;\n\tstruct hlist_node i_dir_hash;\n\tstruct rw_semaphore truncate_lock;\n\tstruct timespec64 i_crtime;\n\tstruct inode vfs_inode;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct nls_table;\n\nstruct msdos_sb_info {\n\tshort unsigned int sec_per_clus;\n\tshort unsigned int cluster_bits;\n\tunsigned int cluster_size;\n\tunsigned char fats;\n\tunsigned char fat_bits;\n\tshort unsigned int fat_start;\n\tlong unsigned int fat_length;\n\tlong unsigned int dir_start;\n\tshort unsigned int dir_entries;\n\tlong unsigned int data_start;\n\tlong unsigned int max_cluster;\n\tlong unsigned int root_cluster;\n\tlong unsigned int fsinfo_sector;\n\tstruct mutex fat_lock;\n\tstruct mutex nfs_build_inode_lock;\n\tstruct mutex s_lock;\n\tunsigned int prev_free;\n\tunsigned int free_clusters;\n\tunsigned int free_clus_valid;\n\tstruct fat_mount_options options;\n\tstruct nls_table *nls_disk;\n\tstruct nls_table *nls_io;\n\tconst void *dir_ops;\n\tint dir_per_block;\n\tint dir_per_block_bits;\n\tunsigned int vol_id;\n\tint fatent_shift;\n\tconst struct fatent_operations *fatent_ops;\n\tstruct inode *fat_inode;\n\tstruct inode *fsinfo_inode;\n\tstruct ratelimit_state ratelimit;\n\tspinlock_t inode_hash_lock;\n\tstruct hlist_head inode_hashtable[256];\n\tspinlock_t dir_hash_lock;\n\tstruct hlist_head dir_hashtable[256];\n\tunsigned int dirty;\n\tstruct callback_head rcu;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tu64 iommu_msi_iova: 58;\n\tu64 iommu_msi_shift: 6;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msm_baud_map {\n\tu16 divisor;\n\tu8 code;\n\tu8 rxstale;\n};\n\nstruct msm_dma {\n\tstruct dma_chan *chan;\n\tenum dma_data_direction dir;\n\tunion {\n\t\tstruct {\n\t\t\tdma_addr_t phys;\n\t\t\tunsigned char *virt;\n\t\t\tunsigned int count;\n\t\t} rx;\n\t\tstruct scatterlist tx_sg;\n\t};\n\tdma_cookie_t cookie;\n\tu32 enable_bit;\n\tstruct dma_async_tx_descriptor *desc;\n};\n\nstruct msm_gpio_wakeirq_map {\n\tunsigned int gpio;\n\tunsigned int wakeirq;\n};\n\nstruct msm_pinctrl_soc_data;\n\nstruct msm_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctrl;\n\tstruct gpio_chip chip;\n\tstruct pinctrl_desc desc;\n\tint irq;\n\tbool intr_target_use_scm;\n\traw_spinlock_t lock;\n\tlong unsigned int dual_edge_irqs[5];\n\tlong unsigned int enabled_irqs[5];\n\tlong unsigned int skip_wake_irqs[5];\n\tlong unsigned int disabled_for_mux[5];\n\tlong unsigned int ever_gpio[5];\n\tconst struct msm_pinctrl_soc_data *soc;\n\tvoid *regs[4];\n\tu32 phys_base[4];\n};\n\nstruct msm_pingroup;\n\nstruct msm_pinctrl_soc_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct pinfunction *functions;\n\tunsigned int nfunctions;\n\tconst struct msm_pingroup *groups;\n\tunsigned int ngroups;\n\tunsigned int ngpios;\n\tbool pull_no_keeper;\n\tconst char * const *tiles;\n\tunsigned int ntiles;\n\tconst int *reserved_gpios;\n\tconst struct msm_gpio_wakeirq_map *wakeirq_map;\n\tunsigned int nwakeirq_map;\n\tbool wakeirq_dual_edge_errata;\n\tunsigned int gpio_func;\n\tunsigned int egpio_func;\n};\n\nstruct msm_pingroup {\n\tstruct pingroup grp;\n\tunsigned int *funcs;\n\tunsigned int nfuncs;\n\tu32 ctl_reg;\n\tu32 io_reg;\n\tu32 intr_cfg_reg;\n\tu32 intr_status_reg;\n\tu32 intr_target_reg;\n\tunsigned int tile: 2;\n\tunsigned int mux_bit: 5;\n\tunsigned int pull_bit: 5;\n\tunsigned int drv_bit: 5;\n\tunsigned int i2c_pull_bit: 5;\n\tunsigned int od_bit: 5;\n\tunsigned int egpio_enable: 5;\n\tunsigned int egpio_present: 5;\n\tunsigned int oe_bit: 5;\n\tunsigned int in_bit: 5;\n\tunsigned int out_bit: 5;\n\tunsigned int intr_enable_bit: 5;\n\tunsigned int intr_status_bit: 5;\n\tunsigned int intr_ack_high: 1;\n\tlong: 1;\n\tunsigned int intr_wakeup_present_bit: 5;\n\tunsigned int intr_wakeup_enable_bit: 5;\n\tunsigned int intr_target_bit: 5;\n\tunsigned int intr_target_width: 5;\n\tunsigned int intr_target_kpss_val: 5;\n\tunsigned int intr_raw_status_bit: 5;\n\tint: 2;\n\tunsigned int intr_polarity_bit: 5;\n\tunsigned int intr_detection_bit: 5;\n\tunsigned int intr_detection_width: 5;\n};\n\nstruct msm_port {\n\tstruct uart_port uart;\n\tchar name[16];\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tunsigned int imr;\n\tint is_uartdm;\n\tunsigned int old_snap_state;\n\tbool break_detected;\n\tstruct msm_dma tx_dma;\n\tstruct msm_dma rx_dma;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong int msg_stime;\n\tlong int msg_rtime;\n\tlong int msg_ctime;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct msr_reg_offset {\n\tunsigned int duty_val;\n\tunsigned int freq_ctrl;\n\tunsigned int duty_ctrl;\n\tunsigned int freq_val;\n};\n\nstruct mssr_mod_clk {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int parent;\n};\n\nstruct mst_intc_chip_data {\n\traw_spinlock_t lock;\n\tunsigned int irq_start;\n\tunsigned int nr_irqs;\n\tvoid *base;\n\tbool no_eoi;\n\tstruct list_head entry;\n\tu16 saved_polarity_conf[4];\n};\n\nstruct mstop {\n\tatomic_t usecnt;\n\tu32 conf;\n};\n\nstruct mstp_clock {\n\tstruct clk_hw hw;\n\tu32 index;\n\tstruct cpg_mssr_priv *priv;\n};\n\nstruct mt6357_regulator_info {\n\tstruct regulator_desc desc;\n\tu32 da_vsel_reg;\n\tu32 da_vsel_mask;\n};\n\nstruct mt6358_regulator_info {\n\tstruct regulator_desc desc;\n\tu32 status_reg;\n\tu32 qi;\n\tu32 da_vsel_reg;\n\tu32 da_vsel_mask;\n\tu32 modeset_reg;\n\tu32 modeset_mask;\n};\n\nstruct mt6359_regulator_info {\n\tstruct regulator_desc desc;\n\tu32 status_reg;\n\tu32 qi;\n\tu32 modeset_reg;\n\tu32 modeset_mask;\n\tu32 lp_mode_reg;\n\tu32 lp_mode_mask;\n};\n\nstruct mt6360_ddata {\n\tstruct i2c_client *i2c[4];\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip_data *irq_data;\n\tunsigned int chip_rev;\n\tu8 crc8_tbl[256];\n};\n\nstruct mt6360_irq_mapping {\n\tconst char *name;\n\tirq_handler_t handler;\n};\n\nstruct mt6360_regulator_data {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n};\n\nstruct mt6360_regulator_desc {\n\tconst struct regulator_desc desc;\n\tunsigned int mode_reg;\n\tunsigned int mode_mask;\n\tunsigned int state_reg;\n\tunsigned int state_mask;\n\tconst struct mt6360_irq_mapping *irq_tables;\n\tint irq_table_size;\n};\n\nstruct mt6397_chip {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct notifier_block pm_nb;\n\tint irq;\n\tstruct irq_domain *irq_domain;\n\tstruct mutex irqlock;\n\tu16 wake_mask[3];\n\tu16 irq_masks_cur[3];\n\tu16 irq_masks_cache[3];\n\tu16 int_con[3];\n\tu16 int_status[3];\n\tu16 chip_id;\n\tvoid *irq_data;\n};\n\nstruct mt6397_regulator_info {\n\tstruct regulator_desc desc;\n\tu32 qi;\n\tu32 vselon_reg;\n\tu32 vselctrl_reg;\n\tu32 vselctrl_mask;\n\tu32 modeset_reg;\n\tu32 modeset_mask;\n};\n\nstruct mt_bdma_desc {\n\tu32 bd_info;\n\tu32 next;\n\tu32 ptr;\n\tu32 bd_data_len;\n};\n\nstruct mt_gpdma_desc {\n\tu32 gpd_info;\n\tu32 next;\n\tu32 ptr;\n\tu32 gpd_data_len;\n\tu32 arg;\n\tu32 blknum;\n\tu32 cmd;\n};\n\nstruct mtd_blktrans_ops;\n\nstruct mtd_blktrans_dev {\n\tstruct mtd_blktrans_ops *tr;\n\tstruct list_head list;\n\tstruct mtd_info *mtd;\n\tstruct mutex lock;\n\tint devnum;\n\tbool bg_stop;\n\tlong unsigned int size;\n\tint readonly;\n\tint open;\n\tstruct kref ref;\n\tstruct gendisk *disk;\n\tstruct attribute_group *disk_attributes;\n\tstruct request_queue *rq;\n\tstruct list_head rq_list;\n\tstruct blk_mq_tag_set *tag_set;\n\tspinlock_t queue_lock;\n\tvoid *priv;\n\tbool writable;\n};\n\nstruct mtd_blktrans_ops {\n\tchar *name;\n\tint major;\n\tint part_bits;\n\tint blksize;\n\tint blkshift;\n\tint (*readsect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*writesect)(struct mtd_blktrans_dev *, long unsigned int, char *);\n\tint (*discard)(struct mtd_blktrans_dev *, long unsigned int, unsigned int);\n\tvoid (*background)(struct mtd_blktrans_dev *);\n\tint (*getgeo)(struct mtd_blktrans_dev *, struct hd_geometry *);\n\tint (*flush)(struct mtd_blktrans_dev *);\n\tint (*open)(struct mtd_blktrans_dev *);\n\tvoid (*release)(struct mtd_blktrans_dev *);\n\tvoid (*add_mtd)(struct mtd_blktrans_ops *, struct mtd_info *);\n\tvoid (*remove_dev)(struct mtd_blktrans_dev *);\n\tstruct list_head devs;\n\tstruct list_head list;\n\tstruct module *owner;\n};\n\nstruct mtd_chip_driver {\n\tstruct mtd_info * (*probe)(struct map_info *);\n\tvoid (*destroy)(struct mtd_info *);\n\tstruct module *module;\n\tchar *name;\n\tstruct list_head list;\n};\n\nstruct mtd_concat {\n\tstruct mtd_info mtd;\n\tint num_subdev;\n\tstruct mtd_info **subdev;\n};\n\nstruct mtd_erase_region_info {\n\tuint64_t offset;\n\tuint32_t erasesize;\n\tuint32_t numblocks;\n\tlong unsigned int *lockmap;\n};\n\nstruct mtd_file_info {\n\tstruct mtd_info *mtd;\n\tenum mtd_file_modes mode;\n};\n\nstruct mtd_info_user {\n\t__u8 type;\n\t__u32 flags;\n\t__u32 size;\n\t__u32 erasesize;\n\t__u32 writesize;\n\t__u32 oobsize;\n\t__u64 padding;\n};\n\nstruct mtd_notifier {\n\tvoid (*add)(struct mtd_info *);\n\tvoid (*remove)(struct mtd_info *);\n\tstruct list_head list;\n};\n\nstruct mtd_oob_buf {\n\t__u32 start;\n\t__u32 length;\n\tunsigned char *ptr;\n};\n\nstruct mtd_oob_buf32 {\n\tu_int32_t start;\n\tu_int32_t length;\n\tcompat_caddr_t ptr;\n};\n\nstruct mtd_oob_buf64 {\n\t__u64 start;\n\t__u32 pad;\n\t__u32 length;\n\t__u64 usr_ptr;\n};\n\nstruct mtd_req_stats;\n\nstruct mtd_oob_ops {\n\tunsigned int mode;\n\tsize_t len;\n\tsize_t retlen;\n\tsize_t ooblen;\n\tsize_t oobretlen;\n\tuint32_t ooboffs;\n\tuint8_t *datbuf;\n\tuint8_t *oobbuf;\n\tstruct mtd_req_stats *stats;\n};\n\nstruct mtd_oob_region {\n\tu32 offset;\n\tu32 length;\n};\n\nstruct mtd_ooblayout_ops {\n\tint (*ecc)(struct mtd_info *, int, struct mtd_oob_region *);\n\tint (*free)(struct mtd_info *, int, struct mtd_oob_region *);\n};\n\nstruct mtd_pairing_info {\n\tint pair;\n\tint group;\n};\n\nstruct mtd_pairing_scheme {\n\tint ngroups;\n\tint (*get_info)(struct mtd_info *, int, struct mtd_pairing_info *);\n\tint (*get_wunit)(struct mtd_info *, const struct mtd_pairing_info *);\n};\n\nstruct mtd_part_parser_data;\n\nstruct mtd_part_parser {\n\tstruct list_head list;\n\tstruct module *owner;\n\tconst char *name;\n\tconst struct of_device_id *of_match_table;\n\tint (*parse_fn)(struct mtd_info *, const struct mtd_partition **, struct mtd_part_parser_data *);\n\tvoid (*cleanup)(const struct mtd_partition *, int);\n};\n\nstruct mtd_part_parser_data {\n\tlong unsigned int origin;\n};\n\nstruct mtd_partition {\n\tconst char *name;\n\tconst char * const *types;\n\tuint64_t size;\n\tuint64_t offset;\n\tuint32_t mask_flags;\n\tuint32_t add_flags;\n\tstruct device_node *of_node;\n};\n\nstruct mtd_partitions {\n\tconst struct mtd_partition *parts;\n\tint nr_parts;\n\tconst struct mtd_part_parser *parser;\n};\n\nstruct mtd_read_req_ecc_stats {\n\t__u32 uncorrectable_errors;\n\t__u32 corrected_bitflips;\n\t__u32 max_bitflips;\n};\n\nstruct mtd_read_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n\tstruct mtd_read_req_ecc_stats ecc_stats;\n};\n\nstruct mtd_req_stats {\n\tunsigned int uncorrectable_errors;\n\tunsigned int corrected_bitflips;\n\tunsigned int max_bitflips;\n};\n\nstruct mtd_write_req {\n\t__u64 start;\n\t__u64 len;\n\t__u64 ooblen;\n\t__u64 usr_data;\n\t__u64 usr_oob;\n\t__u8 mode;\n\t__u8 padding[7];\n};\n\nstruct mtdblk_dev {\n\tstruct mtd_blktrans_dev mbd;\n\tint count;\n\tstruct mutex cache_mutex;\n\tunsigned char *cache_data;\n\tlong unsigned int cache_offset;\n\tunsigned int cache_size;\n\tenum {\n\t\tSTATE_EMPTY = 0,\n\t\tSTATE_CLEAN = 1,\n\t\tSTATE_DIRTY = 2,\n\t} cache_state;\n};\n\nstruct mthp_stat {\n\tlong unsigned int stats[170];\n};\n\nstruct mtk8250_data {\n\tint line;\n\tunsigned int rx_pos;\n\tunsigned int clk_count;\n\tstruct clk *uart_clk;\n\tstruct clk *bus_clk;\n\tstruct uart_8250_dma *dma;\n\tenum dma_rx_status rx_status;\n\tint rx_wakeup_irq;\n};\n\nstruct mtk_chip_config {\n\tu32 sample_sel;\n\tu32 tick_delay;\n};\n\nstruct mtk_cirq_chip_data {\n\tvoid *base;\n\tunsigned int ext_irq_start;\n\tunsigned int ext_irq_end;\n\tconst u32 *offsets;\n\tstruct irq_domain *domain;\n};\n\nstruct mtk_clk_cpumux {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 reg;\n\tu32 mask;\n\tu8 shift;\n};\n\nstruct mtk_gate;\n\nstruct mtk_composite;\n\nstruct mtk_clk_divider;\n\nstruct mtk_fixed_clk;\n\nstruct mtk_fixed_factor;\n\nstruct mtk_mux;\n\nstruct mtk_clk_rst_desc;\n\nstruct mtk_clk_desc {\n\tconst struct mtk_gate *clks;\n\tsize_t num_clks;\n\tconst struct mtk_composite *composite_clks;\n\tsize_t num_composite_clks;\n\tconst struct mtk_clk_divider *divider_clks;\n\tsize_t num_divider_clks;\n\tconst struct mtk_fixed_clk *fixed_clks;\n\tsize_t num_fixed_clks;\n\tconst struct mtk_fixed_factor *factor_clks;\n\tsize_t num_factor_clks;\n\tconst struct mtk_mux *mux_clks;\n\tsize_t num_mux_clks;\n\tconst struct mtk_clk_rst_desc *rst_desc;\n\tspinlock_t *clk_lock;\n\tbool shared_io;\n\tint (*clk_notifier_func)(struct device *, struct clk *);\n\tunsigned int mfg_clk_idx;\n\tbool need_runtime_pm;\n};\n\nstruct mtk_clk_divider {\n\tint id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tu32 div_reg;\n\tunsigned char div_shift;\n\tunsigned char div_width;\n\tunsigned char clk_divider_flags;\n\tconst struct clk_div_table *clk_div_table;\n};\n\nstruct mtk_clk_gate {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_hwv;\n\tconst struct mtk_gate *gate;\n};\n\nstruct mtk_clk_mux {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_hwv;\n\tconst struct mtk_mux *data;\n\tspinlock_t *lock;\n\tbool reparent;\n};\n\nstruct mtk_pll_data;\n\nstruct mtk_clk_pll {\n\tstruct device *dev;\n\tstruct clk_hw hw;\n\tvoid *base_addr;\n\tvoid *pd_addr;\n\tvoid *pwr_addr;\n\tvoid *tuner_addr;\n\tvoid *tuner_en_addr;\n\tvoid *pcw_addr;\n\tvoid *pcw_chg_addr;\n\tvoid *en_addr;\n\tvoid *en_set_addr;\n\tvoid *en_clr_addr;\n\tvoid *fenc_addr;\n\tconst struct mtk_pll_data *data;\n};\n\nstruct mtk_clk_rst_data {\n\tstruct regmap *regmap;\n\tstruct reset_controller_dev rcdev;\n\tconst struct mtk_clk_rst_desc *desc;\n};\n\nstruct mtk_clk_rst_desc {\n\tenum mtk_reset_version version;\n\tu16 *rst_bank_ofs;\n\tu32 rst_bank_nr;\n\tu16 *rst_idx_map;\n\tu32 rst_idx_map_nr;\n};\n\nstruct mtk_composite {\n\tint id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tconst char *parent;\n\tunsigned int flags;\n\tuint32_t mux_reg;\n\tuint32_t divider_reg;\n\tuint32_t gate_reg;\n\tsigned char mux_shift;\n\tsigned char mux_width;\n\tsigned char gate_shift;\n\tsigned char divider_shift;\n\tsigned char divider_width;\n\tu8 mux_flags;\n\tsigned char num_parents;\n};\n\nstruct mtk_cpufreq_platform_data;\n\nstruct mtk_cpu_dvfs_info {\n\tstruct cpumask cpus;\n\tstruct device *cpu_dev;\n\tstruct device *cci_dev;\n\tstruct regulator *proc_reg;\n\tstruct regulator *sram_reg;\n\tstruct clk *cpu_clk;\n\tstruct clk *inter_clk;\n\tstruct list_head list_head;\n\tint intermediate_voltage;\n\tbool need_voltage_tracking;\n\tint vproc_on_boot;\n\tint pre_vproc;\n\tstruct mutex reg_lock;\n\tstruct notifier_block opp_nb;\n\tunsigned int opp_cpu;\n\tlong unsigned int current_freq;\n\tconst struct mtk_cpufreq_platform_data *soc_data;\n\tint vtrack_max;\n\tbool ccifreq_bound;\n};\n\nstruct mtk_cpufreq_platform_data {\n\tint min_volt_shift;\n\tint max_volt_shift;\n\tint proc_max_volt;\n\tint sram_min_volt;\n\tint sram_max_volt;\n\tbool ccifreq_supported;\n};\n\nstruct mtk_desc_eint {\n\tunsigned char eintmux;\n\tunsigned char eintnum;\n};\n\nstruct mtk_desc_function {\n\tconst char *name;\n\tunsigned char muxval;\n};\n\nstruct pinctrl_pin_desc {\n\tunsigned int number;\n\tconst char *name;\n\tvoid *drv_data;\n};\n\nstruct mtk_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tconst struct mtk_desc_eint eint;\n\tconst struct mtk_desc_function *functions;\n};\n\nstruct mtk_drive_desc {\n\tu8 min;\n\tu8 max;\n\tu8 step;\n\tu8 scal;\n};\n\nstruct mtk_drv_group_desc {\n\tunsigned char min_drv;\n\tunsigned char max_drv;\n\tunsigned char low_bit;\n\tunsigned char high_bit;\n\tunsigned char step;\n};\n\nstruct mtk_efuse_pdata {\n\tbool uses_post_processing;\n};\n\nstruct mtk_efuse_priv {\n\tvoid *base;\n};\n\nstruct mtk_eint_hw;\n\nstruct mtk_eint_regs;\n\nstruct mtk_eint_pin;\n\nstruct mtk_eint_xt;\n\nstruct mtk_eint {\n\tstruct device *dev;\n\tvoid **base;\n\tint nbase;\n\tu16 *base_pin_num;\n\tstruct irq_domain *domain;\n\tint irq;\n\tint *dual_edge;\n\tu16 **pin_list;\n\tu32 **wake_mask;\n\tu32 **cur_mask;\n\tconst struct mtk_eint_hw *hw;\n\tconst struct mtk_eint_regs *regs;\n\tstruct mtk_eint_pin *pins;\n\tu16 num_db_time;\n\tvoid *pctl;\n\tconst struct mtk_eint_xt *gpio_xlate;\n};\n\nstruct mtk_eint_desc {\n\tu16 eint_m;\n\tu16 eint_n;\n};\n\nstruct mtk_eint_hw {\n\tu8 port_mask;\n\tu8 ports;\n\tunsigned int ap_num;\n\tunsigned int db_cnt;\n\tconst unsigned int *db_time;\n};\n\nstruct mtk_eint_pin {\n\tu16 number;\n\tu8 instance;\n\tu8 index;\n\tbool debounce;\n\tbool dual_edge;\n};\n\nstruct mtk_eint_regs {\n\tunsigned int stat;\n\tunsigned int ack;\n\tunsigned int mask;\n\tunsigned int mask_set;\n\tunsigned int mask_clr;\n\tunsigned int sens;\n\tunsigned int sens_set;\n\tunsigned int sens_clr;\n\tunsigned int soft;\n\tunsigned int soft_set;\n\tunsigned int soft_clr;\n\tunsigned int pol;\n\tunsigned int pol_set;\n\tunsigned int pol_clr;\n\tunsigned int dom_en;\n\tunsigned int dbnc_ctrl;\n\tunsigned int dbnc_set;\n\tunsigned int dbnc_clr;\n};\n\nstruct mtk_eint_xt {\n\tint (*get_gpio_n)(void *, long unsigned int, unsigned int *, struct gpio_chip **);\n\tint (*get_gpio_state)(void *, long unsigned int);\n\tint (*set_gpio_as_eint)(void *, long unsigned int);\n};\n\nstruct mtk_pllfh_data;\n\nstruct mtk_fh {\n\tstruct mtk_clk_pll clk_pll;\n\tstruct fh_pll_regs regs;\n\tstruct mtk_pllfh_data *pllfh_data;\n\tconst struct fh_operation *ops;\n\tspinlock_t *lock;\n};\n\nstruct mtk_fixed_clk {\n\tint id;\n\tconst char *name;\n\tconst char *parent;\n\tlong unsigned int rate;\n};\n\nstruct mtk_fixed_factor {\n\tint id;\n\tconst char *name;\n\tconst char *parent_name;\n\tint mult;\n\tint div;\n\tlong unsigned int flags;\n};\n\nstruct mtk_func_desc {\n\tconst char *name;\n\tu8 muxval;\n};\n\nstruct mtk_gate_regs;\n\nstruct mtk_gate {\n\tint id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst struct mtk_gate_regs *regs;\n\tconst struct mtk_gate_regs *hwv_regs;\n\tint shift;\n\tconst struct clk_ops *ops;\n\tlong unsigned int flags;\n};\n\nstruct mtk_gate_regs {\n\tu32 sta_ofs;\n\tu32 clr_ofs;\n\tu32 set_ofs;\n};\n\nstruct mtk_gpueb_mbox_chan;\n\nstruct mtk_gpueb_mbox_variant;\n\nstruct mtk_gpueb_mbox {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tvoid *mbox_mmio;\n\tvoid *mbox_ctl;\n\tstruct mbox_controller mbox;\n\tstruct mtk_gpueb_mbox_chan *ch;\n\tint irq;\n\tconst struct mtk_gpueb_mbox_variant *v;\n};\n\nstruct mtk_gpueb_mbox_chan_desc;\n\nstruct mtk_gpueb_mbox_chan {\n\tstruct mtk_gpueb_mbox *ebm;\n\tchar *full_name;\n\tu8 num;\n\tatomic_t rx_status;\n\tconst struct mtk_gpueb_mbox_chan_desc *c;\n};\n\nstruct mtk_gpueb_mbox_chan_desc {\n\tconst char *name;\n\tconst u8 num;\n\tconst u16 tx_offset;\n\tconst u8 tx_len;\n\tconst u16 rx_offset;\n\tconst u8 rx_len;\n};\n\nstruct mtk_gpueb_mbox_variant {\n\tconst u8 num_channels;\n\tconst struct mtk_gpueb_mbox_chan_desc channels[0];\n};\n\nstruct mtk_i2c_ac_timing {\n\tu16 htiming;\n\tu16 ltiming;\n\tu16 hs;\n\tu16 ext;\n\tu16 inter_clk_div;\n\tu16 scl_hl_ratio;\n\tu16 hs_scl_hl_ratio;\n\tu16 sta_stop;\n\tu16 hs_sta_stop;\n\tu16 sda_timing;\n};\n\nstruct mtk_i2c_compatible;\n\nstruct mtk_i2c {\n\tstruct i2c_adapter adap;\n\tstruct device *dev;\n\tstruct completion msg_complete;\n\tstruct i2c_timings timing_info;\n\tvoid *base;\n\tvoid *pdmabase;\n\tstruct clk_bulk_data clocks[4];\n\tbool have_pmic;\n\tbool use_push_pull;\n\tu16 irq_stat;\n\tunsigned int clk_src_div;\n\tunsigned int speed_hz;\n\tenum mtk_trans_op op;\n\tu16 timing_reg;\n\tu16 high_speed_reg;\n\tu16 ltiming_reg;\n\tunsigned char auto_restart;\n\tbool ignore_restart_irq;\n\tstruct mtk_i2c_ac_timing ac_timing;\n\tconst struct mtk_i2c_compatible *dev_comp;\n};\n\nstruct mtk_i2c_compatible {\n\tconst struct i2c_adapter_quirks *quirks;\n\tconst u16 *regs;\n\tunsigned char pmic_i2c: 1;\n\tunsigned char dcm: 1;\n\tunsigned char auto_restart: 1;\n\tunsigned char aux_len_reg: 1;\n\tunsigned char timing_adjust: 1;\n\tunsigned char dma_sync: 1;\n\tunsigned char ltiming_adjust: 1;\n\tunsigned char apdma_sync: 1;\n\tunsigned char max_dma_support;\n};\n\nstruct mtk_iommu_data;\n\nstruct mtk_iommu_domain;\n\nstruct mtk_iommu_bank_data {\n\tvoid *base;\n\tint irq;\n\tu8 id;\n\tstruct device *parent_dev;\n\tstruct mtk_iommu_data *parent_data;\n\tspinlock_t tlb_lock;\n\tstruct mtk_iommu_domain *m4u_dom;\n};\n\nstruct mtk_iommu_suspend_reg {\n\tu32 misc_ctrl;\n\tu32 dcm_dis;\n\tu32 ctrl_reg;\n\tu32 vld_pa_rng;\n\tu32 wr_len_ctrl;\n\tu32 int_control[5];\n\tu32 int_main_control[5];\n\tu32 ivrp_paddr[5];\n};\n\nstruct mtk_smi_larb_iommu {\n\tstruct device *dev;\n\tunsigned int mmu;\n\tunsigned char bank[32];\n};\n\nstruct mtk_iommu_plat_data;\n\nstruct mtk_iommu_data {\n\tstruct device *dev;\n\tstruct clk *bclk;\n\tphys_addr_t protect_base;\n\tstruct mtk_iommu_suspend_reg reg;\n\tstruct iommu_group *m4u_group[8];\n\tbool enable_4GB;\n\tstruct iommu_device iommu;\n\tconst struct mtk_iommu_plat_data *plat_data;\n\tstruct device *smicomm_dev;\n\tstruct mtk_iommu_bank_data *bank;\n\tstruct mtk_iommu_domain *share_dom;\n\tstruct regmap *pericfg;\n\tstruct mutex mutex;\n\tstruct list_head *hw_list;\n\tstruct list_head hw_list_head;\n\tstruct list_head list;\n\tstruct mtk_smi_larb_iommu larb_imu[32];\n};\n\nstruct mtk_iommu_domain {\n\tstruct io_pgtable_cfg cfg;\n\tstruct io_pgtable_ops *iop;\n\tstruct mtk_iommu_bank_data *bank;\n\tstruct iommu_domain domain;\n\tstruct mutex mutex;\n};\n\nstruct mtk_iommu_iova_region {\n\tdma_addr_t iova_base;\n\tlong long unsigned int size;\n};\n\nstruct mtk_iommu_plat_data {\n\tenum mtk_iommu_plat m4u_plat;\n\tu32 flags;\n\tu32 inv_sel_reg;\n\tchar *pericfg_comp_str;\n\tstruct list_head *hw_list;\n\tstruct {\n\t\tunsigned int iova_region_nr;\n\t\tconst struct mtk_iommu_iova_region *iova_region;\n\t\tconst u32 (*iova_region_larb_msk)[32];\n\t};\n\tstruct {\n\t\tu8 banks_num;\n\t\tbool banks_enable[5];\n\t\tunsigned int banks_portmsk[5];\n\t};\n\tunsigned char larbid_remap[64];\n};\n\nstruct mtk_mfg_mbox;\n\nstruct mtk_mfg_variant;\n\nstruct mtk_mfg {\n\tstruct generic_pm_domain pd;\n\tstruct platform_device *pdev;\n\tstruct clk *clk_eb;\n\tstruct clk_bulk_data *gpu_clks;\n\tstruct clk_hw clk_core_hw;\n\tstruct clk_hw clk_stack_hw;\n\tstruct regulator_bulk_data *gpu_regs;\n\tvoid *rpc;\n\tvoid *gpr;\n\tvoid *shared_mem;\n\tphys_addr_t shared_mem_phys;\n\tunsigned int shared_mem_size;\n\tu16 ghpm_en_reg;\n\tu32 ipi_magic;\n\tshort unsigned int num_gpu_opps;\n\tshort unsigned int num_stack_opps;\n\tstruct dev_pm_opp_data *gpu_opps;\n\tstruct dev_pm_opp_data *stack_opps;\n\tstruct mtk_mfg_mbox *gf_mbox;\n\tstruct mtk_mfg_mbox *slp_mbox;\n\tconst struct mtk_mfg_variant *variant;\n};\n\nstruct mtk_mfg_ipi_msg {\n\t__le32 magic;\n\t__le32 cmd;\n\t__le32 target;\n\t__le32 reserved;\n\tunion {\n\t\ts32 oppidx;\n\t\ts32 return_value;\n\t\t__le32 freq;\n\t\t__le32 volt;\n\t\t__le32 power;\n\t\t__le32 power_state;\n\t\t__le32 mode;\n\t\t__le32 value;\n\t\tstruct {\n\t\t\t__le64 base;\n\t\t\t__le32 size;\n\t\t} shared_mem;\n\t\tstruct {\n\t\t\t__le32 freq;\n\t\t\t__le32 volt;\n\t\t} custom;\n\t\tstruct {\n\t\t\t__le32 limiter;\n\t\t\ts32 ceiling_info;\n\t\t\ts32 floor_info;\n\t\t} set_limit;\n\t\tstruct {\n\t\t\t__le32 target;\n\t\t\t__le32 val;\n\t\t} mfg_cfg;\n\t\tstruct {\n\t\t\t__le32 target;\n\t\t\t__le32 val;\n\t\t} mssv;\n\t\tstruct {\n\t\t\ts32 gpu_oppidx;\n\t\t\ts32 stack_oppidx;\n\t\t} dual_commit;\n\t\tstruct {\n\t\t\t__le32 fgpu;\n\t\t\t__le32 vgpu;\n\t\t\t__le32 fstack;\n\t\t\t__le32 vstack;\n\t\t} dual_custom;\n\t} u;\n};\n\nstruct mtk_mfg_ipi_sleep_msg {\n\t__le32 event;\n\t__le32 state;\n\t__le32 magic;\n};\n\nstruct mtk_mfg_mbox {\n\tstruct mbox_client cl;\n\tstruct completion rx_done;\n\tstruct mtk_mfg *mfg;\n\tstruct mbox_chan *ch;\n\tvoid *rx_data;\n};\n\nstruct mtk_mfg_opp_entry {\n\t__le32 freq_khz;\n\t__le32 voltage_core;\n\t__le32 voltage_sram;\n\t__le32 posdiv;\n\t__le32 voltage_margin;\n\t__le32 power_mw;\n};\n\nstruct mtk_mfg_variant {\n\tconst char * const *clk_names;\n\tunsigned int num_clks;\n\tconst char * const *regulator_names;\n\tunsigned int num_regulators;\n\tunsigned int turbo_below;\n\tint (*init)(struct mtk_mfg *);\n};\n\nstruct mtk_mmc_compatible {\n\tu8 clk_div_bits;\n\tbool recheck_sdio_irq;\n\tbool hs400_tune;\n\tbool needs_top_base;\n\tu32 pad_tune_reg;\n\tbool async_fifo;\n\tbool data_tune;\n\tbool busy_check;\n\tbool stop_clk_fix;\n\tu8 stop_dly_sel;\n\tu8 pop_en_cnt;\n\tbool enhance_rx;\n\tbool support_64g;\n\tbool use_internal_cd;\n\tbool support_new_tx;\n\tbool support_new_rx;\n};\n\nstruct mtk_mux {\n\tint id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tconst u8 *parent_index;\n\tunsigned int flags;\n\tu32 mux_ofs;\n\tu32 set_ofs;\n\tu32 clr_ofs;\n\tu32 upd_ofs;\n\tu32 hwv_set_ofs;\n\tu32 hwv_clr_ofs;\n\tu32 hwv_sta_ofs;\n\tu32 fenc_sta_mon_ofs;\n\tu8 mux_shift;\n\tu8 mux_width;\n\tu8 gate_shift;\n\ts8 upd_shift;\n\tu8 fenc_shift;\n\tconst struct clk_ops *ops;\n\tsigned char num_parents;\n};\n\nstruct mtk_mux_nb {\n\tstruct notifier_block nb;\n\tconst struct clk_ops *ops;\n\tu8 bypass_index;\n\tu8 original_index;\n};\n\nstruct u2phy_banks {\n\tvoid *misc;\n\tvoid *fmreg;\n\tvoid *com;\n};\n\nstruct u3phy_banks {\n\tvoid *spllc;\n\tvoid *chip;\n\tvoid *phyd;\n\tvoid *phya;\n};\n\nstruct mtk_phy_instance {\n\tstruct phy *phy;\n\tvoid *port_base;\n\tunion {\n\t\tstruct u2phy_banks u2_banks;\n\t\tstruct u3phy_banks u3_banks;\n\t};\n\tstruct clk_bulk_data clks[2];\n\tu32 index;\n\tu32 type;\n\tstruct regmap *type_sw;\n\tu32 type_sw_reg;\n\tu32 type_sw_index;\n\tu32 efuse_sw_en;\n\tu32 efuse_intr;\n\tu32 efuse_tx_imp;\n\tu32 efuse_rx_imp;\n\tint eye_src;\n\tint eye_vrt;\n\tint eye_term;\n\tint intr;\n\tint discth;\n\tint pre_emphasis;\n\tbool bc12_en;\n\tbool type_force_mode;\n};\n\nstruct mtk_phy_pdata {\n\tbool avoid_rx_sen_degradation;\n\tbool sw_pll_48m_to_26m;\n\tbool sw_efuse_supported;\n\tu8 slew_ref_clock_mhz;\n\tu8 slew_rate_coefficient;\n\tenum mtk_phy_version version;\n};\n\nstruct mtk_pin_desc {\n\tunsigned int number;\n\tconst char *name;\n\tstruct mtk_eint_desc eint;\n\tu8 drv_n;\n\tstruct mtk_func_desc *funcs;\n};\n\nstruct mtk_pin_drv_grp {\n\tshort unsigned int pin;\n\tshort unsigned int offset;\n\tunsigned char bit;\n\tunsigned char grp;\n};\n\nstruct mtk_pin_field {\n\tu8 index;\n\tu32 offset;\n\tu32 mask;\n\tu8 bitpos;\n\tu8 next;\n};\n\nstruct mtk_pin_field_calc {\n\tu16 s_pin;\n\tu16 e_pin;\n\tu8 i_base;\n\tu32 s_addr;\n\tu8 x_addrs;\n\tu8 s_bit;\n\tu8 x_bits;\n\tu8 sz_reg;\n\tu8 fixed;\n};\n\nstruct mtk_pin_ies_smt_set {\n\tshort unsigned int start;\n\tshort unsigned int end;\n\tshort unsigned int offset;\n\tunsigned char bit;\n};\n\nstruct mtk_pin_reg_calc {\n\tconst struct mtk_pin_field_calc *range;\n\tunsigned int nranges;\n};\n\nstruct mtk_pin_rsel {\n\tu16 s_pin;\n\tu16 e_pin;\n\tu16 rsel_index;\n\tu32 up_rsel;\n\tu32 down_rsel;\n};\n\nstruct mtk_pinctrl;\n\nstruct mtk_pin_soc {\n\tconst struct mtk_pin_reg_calc *reg_cal;\n\tconst struct mtk_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct group_desc *grps;\n\tunsigned int ngrps;\n\tconst struct pinfunction *funcs;\n\tunsigned int nfuncs;\n\tconst struct mtk_eint_regs *eint_regs;\n\tconst struct mtk_eint_hw *eint_hw;\n\tstruct mtk_eint_pin *eint_pin;\n\tu8 gpio_m;\n\tbool ies_present;\n\tconst char * const *base_names;\n\tunsigned int nbase_names;\n\tconst unsigned int *pull_type;\n\tconst struct mtk_pin_rsel *pin_rsel;\n\tunsigned int npin_rsel;\n\tint (*bias_disable_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *);\n\tint (*bias_disable_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, int *);\n\tint (*bias_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool);\n\tint (*bias_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool, int *);\n\tint (*bias_set_combo)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32, u32);\n\tint (*bias_get_combo)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32 *, u32 *);\n\tint (*drive_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32);\n\tint (*drive_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, int *);\n\tint (*adv_pull_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool, u32);\n\tint (*adv_pull_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, bool, u32 *);\n\tint (*adv_drive_set)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32);\n\tint (*adv_drive_get)(struct mtk_pinctrl *, const struct mtk_pin_desc *, u32 *);\n\tvoid *driver_data;\n};\n\nstruct mtk_pin_spec_pupd_set_samereg {\n\tshort unsigned int pin;\n\tshort unsigned int offset;\n\tunsigned char pupd_bit;\n\tunsigned char r1_bit;\n\tunsigned char r0_bit;\n};\n\nstruct mtk_pinctrl_group;\n\nstruct mtk_pinctrl_devdata;\n\nstruct mtk_pinctrl___2 {\n\tstruct regmap *regmap1;\n\tstruct regmap *regmap2;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct device *dev;\n\tstruct gpio_chip *chip;\n\tstruct mtk_pinctrl_group *groups;\n\tunsigned int ngroups;\n\tconst char **grp_names;\n\tstruct pinctrl_dev *pctl_dev;\n\tconst struct mtk_pinctrl_devdata *devdata;\n\tstruct mtk_eint *eint;\n};\n\nstruct mtk_pinctrl {\n\tstruct pinctrl_dev *pctrl;\n\tvoid **base;\n\tu8 nbase;\n\tstruct device *dev;\n\tstruct gpio_chip chip;\n\tconst struct mtk_pin_soc *soc;\n\tstruct mtk_eint *eint;\n\tstruct mtk_pinctrl_group *groups;\n\tconst char **grp_names;\n\tspinlock_t lock;\n\tbool rsel_si_unit;\n};\n\nstruct mtk_pinctrl_devdata {\n\tconst struct mtk_desc_pin *pins;\n\tunsigned int npins;\n\tconst struct mtk_drv_group_desc *grp_desc;\n\tunsigned int n_grp_cls;\n\tconst struct mtk_pin_drv_grp *pin_drv_grp;\n\tunsigned int n_pin_drv_grps;\n\tconst struct mtk_pin_ies_smt_set *spec_ies;\n\tunsigned int n_spec_ies;\n\tconst struct mtk_pin_spec_pupd_set_samereg *spec_pupd;\n\tunsigned int n_spec_pupd;\n\tconst struct mtk_pin_ies_smt_set *spec_smt;\n\tunsigned int n_spec_smt;\n\tint (*spec_pull_set)(struct regmap *, const struct mtk_pinctrl_devdata *, unsigned int, bool, unsigned int);\n\tint (*spec_ies_smt_set)(struct regmap *, const struct mtk_pinctrl_devdata *, unsigned int, int, enum pin_config_param);\n\tvoid (*spec_pinmux_set)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*spec_dir_set)(unsigned int *, unsigned int);\n\tint (*mt8365_set_clr_mode)(struct regmap *, unsigned int, unsigned int, unsigned int, bool, bool);\n\tunsigned int dir_offset;\n\tunsigned int ies_offset;\n\tunsigned int smt_offset;\n\tunsigned int pullen_offset;\n\tunsigned int pullsel_offset;\n\tunsigned int dout_offset;\n\tunsigned int din_offset;\n\tunsigned int pinmux_offset;\n\tshort unsigned int type1_start;\n\tshort unsigned int type1_end;\n\tunsigned char port_shf;\n\tunsigned char port_mask;\n\tunsigned char port_align;\n\tstruct mtk_eint_hw eint_hw;\n\tstruct mtk_eint_regs *eint_regs;\n\tunsigned int mode_mask;\n\tunsigned int mode_per_reg;\n\tunsigned int mode_shf;\n};\n\nstruct mtk_pinctrl_group {\n\tconst char *name;\n\tlong unsigned int config;\n\tunsigned int pin;\n};\n\nstruct mtk_pll_div_table;\n\nstruct mtk_pll_data {\n\tint id;\n\tconst char *name;\n\tu32 reg;\n\tu32 pwr_reg;\n\tu32 en_mask;\n\tu32 fenc_sta_ofs;\n\tu32 pd_reg;\n\tu32 tuner_reg;\n\tu32 tuner_en_reg;\n\tu8 tuner_en_bit;\n\tint pd_shift;\n\tunsigned int flags;\n\tconst struct clk_ops *ops;\n\tu32 rst_bar_mask;\n\tlong unsigned int fmin;\n\tlong unsigned int fmax;\n\tint pcwbits;\n\tint pcwibits;\n\tu32 pcw_reg;\n\tint pcw_shift;\n\tu32 pcw_chg_reg;\n\tconst struct mtk_pll_div_table *div_table;\n\tconst char *parent_name;\n\tu32 en_reg;\n\tu32 en_set_reg;\n\tu32 en_clr_reg;\n\tu8 pll_en_bit;\n\tu8 pcw_chg_bit;\n\tu8 fenc_sta_bit;\n};\n\nstruct mtk_pll_desc {\n\tconst struct mtk_pll_data *clks;\n\tsize_t num_clks;\n};\n\nstruct mtk_pll_div_table {\n\tu32 div;\n\tlong unsigned int freq;\n};\n\nstruct mtk_pllfh_data {\n\tstruct fh_pll_state state;\n\tconst struct fh_pll_data data;\n};\n\nstruct mtk_ref2usb_tx {\n\tstruct clk_hw hw;\n\tvoid *base_addr;\n};\n\nstruct mtk_rng {\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct hwrng rng;\n\tstruct device *dev;\n};\n\nstruct mtk_smi_common_plat;\n\nstruct mtk_smi {\n\tstruct device *dev;\n\tunsigned int clk_num;\n\tstruct clk_bulk_data clks[4];\n\tstruct clk *clk_async;\n\tunion {\n\t\tvoid *smi_ao_base;\n\t\tvoid *base;\n\t};\n\tstruct device *smi_common_dev;\n\tconst struct mtk_smi_common_plat *plat;\n};\n\nstruct mtk_smi_reg_pair;\n\nstruct mtk_smi_common_plat {\n\tenum mtk_smi_type type;\n\tbool has_gals;\n\tu32 bus_sel;\n\tconst struct mtk_smi_reg_pair *init;\n};\n\nstruct mtk_smi_larb_gen;\n\nstruct mtk_smi_larb {\n\tstruct mtk_smi smi;\n\tvoid *base;\n\tstruct device *smi_common_dev;\n\tconst struct mtk_smi_larb_gen *larb_gen;\n\tint larbid;\n\tu32 *mmu;\n\tunsigned char *bank;\n};\n\nstruct mtk_smi_larb_gen {\n\tint port_in_larb[33];\n\tint (*config_port)(struct device *);\n\tunsigned int larb_direct_to_common_mask;\n\tunsigned int flags_general;\n\tconst u8 (*ostd)[32];\n};\n\nstruct mtk_smi_reg_pair {\n\tunsigned int offset;\n\tu32 value;\n};\n\nstruct name_data;\n\nstruct socinfo_data;\n\nstruct soc_device;\n\nstruct mtk_socinfo {\n\tstruct device *dev;\n\tstruct name_data *name_data;\n\tstruct socinfo_data *socinfo_data;\n\tstruct soc_device *soc_dev;\n};\n\nstruct mtk_spi_compatible;\n\nstruct mtk_spi {\n\tvoid *base;\n\tu32 state;\n\tint pad_num;\n\tu32 *pad_sel;\n\tstruct clk *parent_clk;\n\tstruct clk *sel_clk;\n\tstruct clk *spi_clk;\n\tstruct clk *spi_hclk;\n\tstruct spi_transfer *cur_transfer;\n\tu32 xfer_len;\n\tu32 num_xfered;\n\tstruct scatterlist *tx_sgl;\n\tstruct scatterlist *rx_sgl;\n\tu32 tx_sgl_len;\n\tu32 rx_sgl_len;\n\tconst struct mtk_spi_compatible *dev_comp;\n\tstruct pm_qos_request qos_request;\n\tu32 spi_clk_hz;\n\tstruct completion spimem_done;\n\tbool use_spimem;\n\tstruct device *dev;\n\tdma_addr_t tx_dma;\n\tdma_addr_t rx_dma;\n};\n\nstruct mtk_spi_compatible {\n\tbool need_pad_sel;\n\tbool must_tx;\n\tbool enhance_timing;\n\tbool dma_ext;\n\tbool no_need_unprepare;\n\tbool ipm_design;\n};\n\nstruct mtk_sysirq_chip_data {\n\traw_spinlock_t lock;\n\tu32 nr_intpol_bases;\n\tvoid **intpol_bases;\n\tu32 *intpol_words;\n\tu8 *intpol_idx;\n\tu16 *which_word;\n};\n\nstruct mtk_tphy {\n\tstruct device *dev;\n\tvoid *sif_base;\n\tconst struct mtk_phy_pdata *pdata;\n\tstruct mtk_phy_instance **phys;\n\tint nphys;\n\tint src_ref_clk;\n\tint src_coef;\n};\n\nstruct mtk_wdt_data {\n\tint toprgu_sw_rst_num;\n\tbool has_swsysrst_en;\n};\n\nstruct mtk_wdt_dev {\n\tstruct watchdog_device wdt_dev;\n\tvoid *wdt_base;\n\tspinlock_t lock;\n\tstruct reset_controller_dev rcdev;\n\tbool disable_wdt_extrst;\n\tbool reset_by_toprgu;\n\tbool has_swsysrst_en;\n};\n\nstruct mtu3_fifo_info {\n\tu32 base;\n\tu32 limit;\n\tlong unsigned int bitmap[2];\n};\n\nstruct mtu3_ep;\n\nstruct mtu3;\n\nstruct qmu_gpd;\n\nstruct mtu3_request {\n\tstruct usb_request request;\n\tstruct list_head list;\n\tstruct mtu3_ep *mep;\n\tstruct mtu3 *mtu;\n\tstruct qmu_gpd *gpd;\n\tint epnum;\n};\n\nstruct ssusb_mtk;\n\nstruct mtu3 {\n\tspinlock_t lock;\n\tstruct ssusb_mtk *ssusb;\n\tstruct device *dev;\n\tvoid *mac_base;\n\tvoid *ippc_base;\n\tint irq;\n\tstruct mtu3_fifo_info tx_fifo;\n\tstruct mtu3_fifo_info rx_fifo;\n\tstruct mtu3_ep *ep_array;\n\tstruct mtu3_ep *in_eps;\n\tstruct mtu3_ep *out_eps;\n\tstruct mtu3_ep *ep0;\n\tint num_eps;\n\tint slot;\n\tint active_ep;\n\tstruct dma_pool *qmu_gpd_pool;\n\tenum mtu3_g_ep0_state ep0_state;\n\tstruct usb_gadget g;\n\tstruct usb_gadget_driver *gadget_driver;\n\tstruct mtu3_request ep0_req;\n\tu8 setup_buf[6];\n\tenum usb_device_speed max_speed;\n\tenum usb_device_speed speed;\n\tunsigned int is_active: 1;\n\tunsigned int may_wakeup: 1;\n\tunsigned int is_self_powered: 1;\n\tunsigned int test_mode: 1;\n\tunsigned int softconnect: 1;\n\tunsigned int u1_enable: 1;\n\tunsigned int u2_enable: 1;\n\tunsigned int u3_capable: 1;\n\tunsigned int delayed_status: 1;\n\tunsigned int gen2cp: 1;\n\tunsigned int connected: 1;\n\tunsigned int async_callbacks: 1;\n\tunsigned int separate_fifo: 1;\n\tu8 address;\n\tu8 test_mode_nr;\n\tu32 hw_version;\n};\n\nstruct mtu3_gpd_ring {\n\tdma_addr_t dma;\n\tstruct qmu_gpd *start;\n\tstruct qmu_gpd *end;\n\tstruct qmu_gpd *enqueue;\n\tstruct qmu_gpd *dequeue;\n};\n\nstruct mtu3_ep {\n\tstruct usb_ep ep;\n\tchar name[12];\n\tstruct mtu3 *mtu;\n\tu8 epnum;\n\tu8 type;\n\tu8 is_in;\n\tu16 maxp;\n\tint slot;\n\tu32 fifo_size;\n\tu32 fifo_addr;\n\tu32 fifo_seg_size;\n\tstruct mtu3_fifo_info *fifo;\n\tstruct list_head req_list;\n\tstruct mtu3_gpd_ring gpd_ring;\n\tconst struct usb_ss_ep_comp_descriptor *comp_desc;\n\tconst struct usb_endpoint_descriptor *desc;\n\tint flags;\n};\n\nstruct mtu3_file_map {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct mtu3_regset {\n\tchar name[32];\n\tstruct debugfs_regset32 regset;\n};\n\nstruct mu3c_ippc_regs {\n\t__le32 ip_pw_ctr0;\n\t__le32 ip_pw_ctr1;\n\t__le32 ip_pw_ctr2;\n\t__le32 ip_pw_ctr3;\n\t__le32 ip_pw_sts1;\n\t__le32 ip_pw_sts2;\n\t__le32 reserved0[3];\n\t__le32 ip_xhci_cap;\n\t__le32 reserved1[2];\n\t__le64 u3_ctrl_p[4];\n\t__le64 u2_ctrl_p[5];\n\t__le32 reserved2;\n\t__le32 u2_phy_pll;\n\t__le32 reserved3[33];\n};\n\nstruct mu3h_sch_bw_info {\n\tu32 bus_bw[64];\n};\n\nstruct mu3h_sch_tt;\n\nstruct mu3h_sch_ep_info {\n\tu32 esit;\n\tu32 num_esit;\n\tu32 num_budget_microframes;\n\tstruct list_head endpoint;\n\tstruct hlist_node hentry;\n\tstruct list_head tt_endpoint;\n\tstruct mu3h_sch_bw_info *bw_info;\n\tstruct mu3h_sch_tt *sch_tt;\n\tu32 ep_type;\n\tu32 maxpkt;\n\tstruct usb_host_endpoint *ep;\n\tenum usb_device_speed speed;\n\tbool allocated;\n\tu32 offset;\n\tu32 repeat;\n\tu32 pkts;\n\tu32 cs_count;\n\tu32 burst_mode;\n\tu32 bw_budget_table[0];\n};\n\nstruct mu3h_sch_tt {\n\tu16 fs_bus_bw_out[64];\n\tu16 fs_bus_bw_in[64];\n\tu8 ls_bus_bw[64];\n\tu16 fs_frame_bw[8];\n\tu8 in_ss_cnt[64];\n\tstruct list_head ep_list;\n};\n\nstruct multi_mux {\n\tunsigned int m_bank_id;\n\tunsigned int m_bit_offs;\n\tunsigned int sid;\n\tunsigned int eid;\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multicall_entry {\n\txen_ulong_t op;\n\txen_long_t result;\n\txen_ulong_t args[6];\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct muram_info {\n\tstruct gen_pool *pool;\n\tvoid *vbase;\n\tphys_addr_t pbase;\n};\n\nstruct musb_qh;\n\nstruct musb_io {\n\tu32 (*ep_offset)(u8, u16);\n\tvoid (*ep_select)(void *, u8);\n\tu32 (*fifo_offset)(u8);\n\tvoid (*read_fifo)(struct musb_hw_ep *, u16, u8 *);\n\tvoid (*write_fifo)(struct musb_hw_ep *, u16, const u8 *);\n\tu32 (*busctl_offset)(u8, u16);\n\tu16 (*get_toggle)(struct musb_qh *, int);\n\tu16 (*set_toggle)(struct musb_qh *, int, struct urb *);\n};\n\nstruct musb_csr_regs {\n\tu16 txmaxp;\n\tu16 txcsr;\n\tu16 rxmaxp;\n\tu16 rxcsr;\n\tu16 rxfifoadd;\n\tu16 txfifoadd;\n\tu8 txtype;\n\tu8 txinterval;\n\tu8 rxtype;\n\tu8 rxinterval;\n\tu8 rxfifosz;\n\tu8 txfifosz;\n\tu8 txfunaddr;\n\tu8 txhubaddr;\n\tu8 txhubport;\n\tu8 rxfunaddr;\n\tu8 rxhubaddr;\n\tu8 rxhubport;\n};\n\nstruct musb_context_registers {\n\tu8 power;\n\tu8 intrusbe;\n\tu16 frame;\n\tu8 index;\n\tu8 testmode;\n\tu8 devctl;\n\tu8 busctl;\n\tu8 misc;\n\tu32 otg_interfsel;\n\tstruct musb_csr_regs index_regs[16];\n};\n\nstruct musb_ep {\n\tstruct usb_ep end_point;\n\tchar name[12];\n\tstruct musb_hw_ep *hw_ep;\n\tstruct musb *musb;\n\tu8 current_epnum;\n\tu8 type;\n\tu8 is_in;\n\tu16 packet_sz;\n\tconst struct usb_endpoint_descriptor *desc;\n\tstruct dma_channel *dma;\n\tstruct list_head req_list;\n\tu8 wedged;\n\tu8 busy;\n\tu8 hb_mult;\n};\n\nstruct musb_hw_ep {\n\tstruct musb *musb;\n\tvoid *fifo;\n\tvoid *regs;\n\tu8 epnum;\n\tbool is_shared_fifo;\n\tbool tx_double_buffered;\n\tbool rx_double_buffered;\n\tu16 max_packet_sz_tx;\n\tu16 max_packet_sz_rx;\n\tstruct dma_channel *tx_channel;\n\tstruct dma_channel *rx_channel;\n\tstruct musb_qh *in_qh;\n\tstruct musb_qh *out_qh;\n\tu8 rx_reinit;\n\tu8 tx_reinit;\n\tstruct musb_ep ep_in;\n\tstruct musb_ep ep_out;\n};\n\nstruct musb_platform_ops;\n\nstruct musb_hdrc_config;\n\nstruct musb {\n\tspinlock_t lock;\n\tspinlock_t list_lock;\n\tstruct musb_io io;\n\tconst struct musb_platform_ops *ops;\n\tstruct musb_context_registers context;\n\tirqreturn_t (*isr)(int, void *);\n\tstruct delayed_work irq_work;\n\tstruct delayed_work deassert_reset_work;\n\tstruct delayed_work finish_resume_work;\n\tstruct delayed_work gadget_work;\n\tu16 hwvers;\n\tu16 intrrxe;\n\tu16 intrtxe;\n\tu32 port1_status;\n\tlong unsigned int rh_timer;\n\tenum musb_h_ep0_state ep0_stage;\n\tstruct musb_hw_ep *bulk_ep;\n\tstruct list_head control;\n\tstruct list_head in_bulk;\n\tstruct list_head out_bulk;\n\tstruct list_head pending_list;\n\tstruct timer_list otg_timer;\n\tstruct timer_list dev_timer;\n\tstruct notifier_block nb;\n\tstruct dma_controller *dma_controller;\n\tstruct device *controller;\n\tvoid *ctrl_base;\n\tvoid *mregs;\n\tu8 int_usb;\n\tu16 int_rx;\n\tu16 int_tx;\n\tstruct usb_phy *xceiv;\n\tstruct phy *phy;\n\tenum usb_otg_state otg_state;\n\tint nIrq;\n\tunsigned int irq_wake: 1;\n\tstruct musb_hw_ep endpoints[16];\n\tu16 vbuserr_retry;\n\tu16 epmask;\n\tu8 nr_endpoints;\n\tu8 min_power;\n\tenum musb_mode port_mode;\n\tbool session;\n\tlong unsigned int quirk_retries;\n\tbool is_host;\n\tint a_wait_bcon;\n\tlong unsigned int idle_timeout;\n\tunsigned int is_initialized: 1;\n\tunsigned int is_runtime_suspended: 1;\n\tunsigned int is_active: 1;\n\tunsigned int is_multipoint: 1;\n\tunsigned int hb_iso_rx: 1;\n\tunsigned int hb_iso_tx: 1;\n\tunsigned int dyn_fifo: 1;\n\tunsigned int bulk_split: 1;\n\tunsigned int bulk_combine: 1;\n\tunsigned int is_suspended: 1;\n\tunsigned int may_wakeup: 1;\n\tunsigned int is_self_powered: 1;\n\tunsigned int is_bus_powered: 1;\n\tunsigned int set_address: 1;\n\tunsigned int test_mode: 1;\n\tunsigned int softconnect: 1;\n\tunsigned int flush_irq_work: 1;\n\tu8 address;\n\tu8 test_mode_nr;\n\tu16 ackpend;\n\tenum musb_g_ep0_state ep0_state;\n\tstruct usb_gadget g;\n\tstruct usb_gadget_driver *gadget_driver;\n\tstruct usb_hcd *hcd;\n\tconst struct musb_hdrc_config *config;\n\tint xceiv_old_state;\n\tstruct dentry *debugfs_root;\n};\n\nstruct musb_fifo_cfg {\n\tu8 hw_ep_num;\n\tenum musb_fifo_style style;\n\tenum musb_buf_mode mode;\n\tu16 maxpacket;\n};\n\nstruct musb_hdrc_config {\n\tconst struct musb_fifo_cfg *fifo_cfg;\n\tunsigned int fifo_cfg_size;\n\tunsigned int multipoint: 1;\n\tunsigned int dyn_fifo: 1;\n\tunsigned int host_port_deassert_reset_at_resume: 1;\n\tu8 num_eps;\n\tu8 ram_bits;\n\tu32 maximum_speed;\n};\n\nstruct musb_hdrc_platform_data {\n\tu8 mode;\n\tconst char *clock;\n\tint (*set_vbus)(struct device *, int);\n\tu8 power;\n\tu8 min_power;\n\tu8 potpgt;\n\tunsigned int extvbus: 1;\n\tconst struct musb_hdrc_config *config;\n\tvoid *board_data;\n\tconst void *platform_ops;\n};\n\nstruct musb_pending_work {\n\tint (*callback)(struct musb *, void *);\n\tvoid *data;\n\tstruct list_head node;\n};\n\nstruct musb_platform_ops {\n\tu32 quirks;\n\tint (*init)(struct musb *);\n\tint (*exit)(struct musb *);\n\tvoid (*enable)(struct musb *);\n\tvoid (*disable)(struct musb *);\n\tu32 (*ep_offset)(u8, u16);\n\tvoid (*ep_select)(void *, u8);\n\tu16 fifo_mode;\n\tu32 (*fifo_offset)(u8);\n\tu32 (*busctl_offset)(u8, u16);\n\tu8 (*readb)(void *, u32);\n\tvoid (*writeb)(void *, u32, u8);\n\tu8 (*clearb)(void *, u32);\n\tu16 (*readw)(void *, u32);\n\tvoid (*writew)(void *, u32, u16);\n\tu16 (*clearw)(void *, u32);\n\tvoid (*read_fifo)(struct musb_hw_ep *, u16, u8 *);\n\tvoid (*write_fifo)(struct musb_hw_ep *, u16, const u8 *);\n\tu16 (*get_toggle)(struct musb_qh *, int);\n\tu16 (*set_toggle)(struct musb_qh *, int, struct urb *);\n\tstruct dma_controller * (*dma_init)(struct musb *, void *);\n\tvoid (*dma_exit)(struct dma_controller *);\n\tint (*set_mode)(struct musb *, u8);\n\tvoid (*try_idle)(struct musb *, long unsigned int);\n\tint (*recover)(struct musb *);\n\tint (*vbus_status)(struct musb *);\n\tvoid (*set_vbus)(struct musb *, int);\n\tvoid (*pre_root_reset_end)(struct musb *);\n\tvoid (*post_root_reset_end)(struct musb *);\n\tint (*phy_callback)(enum musb_vbus_id_status);\n\tvoid (*clear_ep_rxintr)(struct musb *, int);\n};\n\nstruct musb_qh {\n\tstruct usb_host_endpoint *hep;\n\tstruct usb_device *dev;\n\tstruct musb_hw_ep *hw_ep;\n\tstruct list_head ring;\n\tu8 mux;\n\tunsigned int offset;\n\tunsigned int segsize;\n\tu8 type_reg;\n\tu8 intv_reg;\n\tu8 addr_reg;\n\tu8 h_addr_reg;\n\tu8 h_port_reg;\n\tu8 is_ready;\n\tu8 type;\n\tu8 epnum;\n\tu8 hb_mult;\n\tu16 maxpacket;\n\tu16 frame;\n\tunsigned int iso_idx;\n\tstruct sg_mapping_iter sg_miter;\n\tbool use_sg;\n};\n\nstruct musb_register_map {\n\tchar *name;\n\tunsigned int offset;\n\tunsigned int size;\n};\n\nstruct musb_request {\n\tstruct usb_request request;\n\tstruct list_head list;\n\tstruct musb_ep *ep;\n\tstruct musb *musb;\n\tu8 tx;\n\tu8 epnum;\n\tenum buffer_map_state map_state;\n};\n\nstruct musb_temp_buffer {\n\tvoid *kmalloc_ptr;\n\tvoid *old_xfer_buffer;\n\tu8 data[0];\n};\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\nstruct mux_chip;\n\nstruct mux_control {\n\tstruct semaphore lock;\n\tstruct mux_chip *chip;\n\tint cached_state;\n\tunsigned int states;\n\tint idle_state;\n\tktime_t last_change;\n};\n\nstruct mux_control_ops;\n\nstruct mux_chip {\n\tunsigned int controllers;\n\tstruct device dev;\n\tint id;\n\tconst struct mux_control_ops *ops;\n\tstruct mux_control mux[0];\n};\n\nstruct mux_control_ops {\n\tint (*set)(struct mux_control *, int);\n};\n\nstruct mux_hwclock {\n\tstruct clk_hw hw;\n\tstruct clockgen *cg;\n\tconst struct clockgen_muxinfo *info;\n\tu32 *reg;\n\tu8 parent_to_clksel[16];\n\ts8 clksel_to_parent[16];\n\tint num_parents;\n};\n\nstruct mux_mmio {\n\tstruct regmap_field **fields;\n\tunsigned int *hardware_states;\n};\n\nstruct mux_state {\n\tstruct mux_control *mux;\n\tunsigned int state;\n};\n\nstruct mv3310_mactype;\n\nstruct mv3310_chip {\n\tbool (*has_downshift)(struct phy_device *);\n\tvoid (*init_supported_interfaces)(long unsigned int *);\n\tint (*get_mactype)(struct phy_device *);\n\tint (*set_mactype)(struct phy_device *, int);\n\tint (*select_mactype)(long unsigned int *);\n\tconst struct mv3310_mactype *mactypes;\n\tsize_t n_mactypes;\n\tint (*hwmon_read_temp_reg)(struct phy_device *);\n};\n\nstruct mv3310_mactype {\n\tbool valid;\n\tbool fixed_interface;\n\tphy_interface_t interface_10g;\n};\n\nstruct mv3310_priv {\n\tlong unsigned int supported_interfaces[1];\n\tconst struct mv3310_mactype *mactype;\n\tu32 firmware_ver;\n\tbool has_downshift;\n\tstruct device *hwmon_dev;\n\tchar *hwmon_name;\n};\n\nstruct mv64xxx_i2c_regs {\n\tu8 addr;\n\tu8 ext_addr;\n\tu8 data;\n\tu8 control;\n\tu8 status;\n\tu8 clock;\n\tu8 soft_reset;\n};\n\nstruct mv64xxx_i2c_data {\n\tstruct i2c_msg *msgs;\n\tint num_msgs;\n\tint irq;\n\tu32 state;\n\tu32 action;\n\tu32 aborting;\n\tu32 cntl_bits;\n\tvoid *reg_base;\n\tstruct mv64xxx_i2c_regs reg_offsets;\n\tu32 addr1;\n\tu32 addr2;\n\tu32 bytes_left;\n\tu32 byte_posn;\n\tu32 send_stop;\n\tu32 block;\n\tint rc;\n\tu32 freq_m;\n\tu32 freq_n;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\twait_queue_head_t waitq;\n\tspinlock_t lock;\n\tstruct i2c_msg *msg;\n\tstruct i2c_adapter adapter;\n\tbool offload_enabled;\n\tbool errata_delay;\n\tstruct reset_control *rstc;\n\tbool irq_clear_inverted;\n\tbool clk_n_base_0;\n\tstruct i2c_bus_recovery_info rinfo;\n\tbool atomic;\n};\n\nstruct mv64xxx_i2c_pdata {\n\tu32 freq_m;\n\tu32 freq_n;\n\tu32 timeout;\n};\n\nstruct mv88q2xxx_priv {\n\tbool enable_led0;\n};\n\nstruct mv_xor_device;\n\nstruct mv_xor_chan {\n\tint pending;\n\tspinlock_t lock;\n\tvoid *mmr_base;\n\tvoid *mmr_high_base;\n\tunsigned int idx;\n\tint irq;\n\tstruct list_head chain;\n\tstruct list_head free_slots;\n\tstruct list_head allocated_slots;\n\tstruct list_head completed_slots;\n\tdma_addr_t dma_desc_pool;\n\tvoid *dma_desc_pool_virt;\n\tsize_t pool_size;\n\tstruct dma_device dmadev;\n\tstruct dma_chan dmachan;\n\tint slots_allocated;\n\tstruct tasklet_struct irq_tasklet;\n\tint op_in_desc;\n\tchar dummy_src[128];\n\tchar dummy_dst[128];\n\tdma_addr_t dummy_src_addr;\n\tdma_addr_t dummy_dst_addr;\n\tu32 saved_config_reg;\n\tu32 saved_int_mask_reg;\n\tstruct mv_xor_device *xordev;\n};\n\nstruct mv_xor_channel_data {\n\tdma_cap_mask_t cap_mask;\n};\n\nstruct mv_xor_desc {\n\tu32 status;\n\tu32 crc32_result;\n\tu32 desc_command;\n\tu32 phy_next_desc;\n\tu32 byte_count;\n\tu32 phy_dest_addr;\n\tu32 phy_src_addr[8];\n\tu32 reserved0;\n\tu32 reserved1;\n};\n\nstruct mv_xor_desc_slot {\n\tstruct list_head node;\n\tstruct list_head sg_tx_list;\n\tenum dma_transaction_type type;\n\tvoid *hw_desc;\n\tu16 idx;\n\tstruct dma_async_tx_descriptor async_tx;\n};\n\nstruct mv_xor_device {\n\tvoid *xor_base;\n\tvoid *xor_high_base;\n\tstruct clk *clk;\n\tstruct mv_xor_chan *channels[2];\n\tint xor_type;\n\tu32 win_start[8];\n\tu32 win_end[8];\n};\n\nstruct mv_xor_platform_data {\n\tstruct mv_xor_channel_data *channels;\n};\n\nstruct mv_xor_v2_descriptor {\n\tu16 desc_id;\n\tu16 flags;\n\tu32 crc32_result;\n\tu32 desc_ctrl;\n\tu32 buff_size;\n\tu32 fill_pattern_src_addr[4];\n\tu32 data_buff_addr[12];\n\tu32 reserved[12];\n};\n\nstruct mv_xor_v2_sw_desc;\n\nstruct mv_xor_v2_device {\n\tspinlock_t lock;\n\tvoid *dma_base;\n\tvoid *glob_base;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\tstruct tasklet_struct irq_tasklet;\n\tstruct list_head free_sw_desc;\n\tstruct dma_device dmadev;\n\tstruct dma_chan dmachan;\n\tdma_addr_t hw_desq;\n\tstruct mv_xor_v2_descriptor *hw_desq_virt;\n\tstruct mv_xor_v2_sw_desc *sw_desq;\n\tint desc_size;\n\tunsigned int npendings;\n\tunsigned int hw_queue_idx;\n\tunsigned int irq;\n};\n\nstruct mv_xor_v2_sw_desc {\n\tint idx;\n\tstruct dma_async_tx_descriptor async_tx;\n\tstruct mv_xor_v2_descriptor hw_desc;\n\tstruct list_head free_list;\n};\n\nstruct mvebu_a3700_comphy_conf {\n\tunsigned int lane;\n\tenum phy_mode mode;\n\tint submode;\n};\n\nstruct mvebu_a3700_comphy_priv;\n\nstruct mvebu_a3700_comphy_lane {\n\tstruct mvebu_a3700_comphy_priv *priv;\n\tstruct device *dev;\n\tunsigned int id;\n\tenum phy_mode mode;\n\tint submode;\n\tbool invert_tx;\n\tbool invert_rx;\n};\n\nstruct mvebu_a3700_comphy_priv {\n\tvoid *comphy_regs;\n\tvoid *lane0_phy_regs;\n\tvoid *lane1_phy_regs;\n\tvoid *lane2_phy_indirect;\n\tspinlock_t lock;\n\tbool xtal_is_40m;\n};\n\nstruct mvebu_a3700_utmi_caps;\n\nstruct mvebu_a3700_utmi {\n\tvoid *regs;\n\tstruct regmap *usb_misc;\n\tconst struct mvebu_a3700_utmi_caps *caps;\n\tstruct phy *phy;\n};\n\nstruct phy_ops;\n\nstruct mvebu_a3700_utmi_caps {\n\tint usb32;\n\tconst struct phy_ops *ops;\n};\n\nstruct mvebu_comphy_conf {\n\tenum phy_mode mode;\n\tint submode;\n\tunsigned int lane;\n\tunsigned int port;\n\tu32 mux;\n\tu32 fw_mode;\n};\n\nstruct mvebu_comphy_priv;\n\nstruct mvebu_comphy_lane {\n\tstruct mvebu_comphy_priv *priv;\n\tunsigned int id;\n\tenum phy_mode mode;\n\tint submode;\n\tint port;\n};\n\nstruct mvebu_comphy_priv {\n\tvoid *base;\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tstruct clk *mg_domain_clk;\n\tstruct clk *mg_core_clk;\n\tstruct clk *axi_clk;\n\tlong unsigned int cp_phys;\n};\n\nstruct mvebu_gicp_spi_range;\n\nstruct mvebu_gicp {\n\tstruct mvebu_gicp_spi_range *spi_ranges;\n\tunsigned int spi_ranges_cnt;\n\tunsigned int spi_cnt;\n\tlong unsigned int *spi_bitmap;\n\tspinlock_t spi_lock;\n\tstruct resource *res;\n\tstruct device *dev;\n};\n\nstruct mvebu_gicp_spi_range {\n\tunsigned int start;\n\tunsigned int count;\n};\n\nstruct mvebu_pwm;\n\nstruct mvebu_gpio_chip {\n\tstruct gpio_chip chip;\n\tstruct regmap *regs;\n\tu32 offset;\n\tstruct regmap *percpu_regs;\n\tint irqbase;\n\tstruct irq_domain *domain;\n\tint soc_variant;\n\tstruct clk *clk;\n\tstruct mvebu_pwm *mvpwm;\n\tu32 out_reg;\n\tu32 io_conf_reg;\n\tu32 blink_en_reg;\n\tu32 in_pol_reg;\n\tu32 edge_mask_regs[4];\n\tu32 level_mask_regs[4];\n};\n\nstruct mvebu_icu {\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct mvebu_icu_subset_data;\n\nstruct mvebu_icu_msi_data {\n\tstruct mvebu_icu *icu;\n\tatomic_t initialized;\n\tconst struct mvebu_icu_subset_data *subset_data;\n};\n\nstruct mvebu_icu_subset_data {\n\tunsigned int icu_group;\n\tunsigned int offset_set_ah;\n\tunsigned int offset_set_al;\n\tunsigned int offset_clr_ah;\n\tunsigned int offset_clr_al;\n};\n\nstruct mvebu_mpp_ctrl_data;\n\nstruct mvebu_mpp_ctrl {\n\tconst char *name;\n\tu8 pid;\n\tu8 npins;\n\tunsigned int *pins;\n\tint (*mpp_get)(struct mvebu_mpp_ctrl_data *, unsigned int, long unsigned int *);\n\tint (*mpp_set)(struct mvebu_mpp_ctrl_data *, unsigned int, long unsigned int);\n\tint (*mpp_gpio_req)(struct mvebu_mpp_ctrl_data *, unsigned int);\n\tint (*mpp_gpio_dir)(struct mvebu_mpp_ctrl_data *, unsigned int, bool);\n};\n\nstruct mvebu_mpp_ctrl_data {\n\tunion {\n\t\tvoid *base;\n\t\tstruct {\n\t\t\tstruct regmap *map;\n\t\t\tu32 offset;\n\t\t} regmap;\n\t};\n};\n\nstruct mvebu_mpp_ctrl_setting {\n\tu8 val;\n\tconst char *name;\n\tconst char *subname;\n\tu8 variant;\n\tu8 flags;\n};\n\nstruct mvebu_mpp_mode {\n\tu8 pid;\n\tstruct mvebu_mpp_ctrl_setting *settings;\n};\n\nstruct mvebu_pic {\n\tvoid *base;\n\tu32 parent_irq;\n\tstruct irq_domain *domain;\n\tstruct platform_device *pdev;\n};\n\nstruct mvebu_pinctrl_group;\n\nstruct mvebu_pinctrl_function;\n\nstruct mvebu_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_desc desc;\n\tstruct mvebu_pinctrl_group *groups;\n\tunsigned int num_groups;\n\tstruct mvebu_pinctrl_function *functions;\n\tunsigned int num_functions;\n\tu8 variant;\n};\n\nstruct mvebu_pinctrl_function {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int num_groups;\n};\n\nstruct mvebu_pinctrl_group {\n\tconst char *name;\n\tconst struct mvebu_mpp_ctrl *ctrl;\n\tstruct mvebu_mpp_ctrl_data *data;\n\tstruct mvebu_mpp_ctrl_setting *settings;\n\tunsigned int num_settings;\n\tunsigned int gid;\n\tunsigned int *pins;\n\tunsigned int npins;\n};\n\nstruct mvebu_pinctrl_soc_info {\n\tu8 variant;\n\tconst struct mvebu_mpp_ctrl *controls;\n\tstruct mvebu_mpp_ctrl_data *control_data;\n\tint ncontrols;\n\tstruct mvebu_mpp_mode *modes;\n\tint nmodes;\n\tstruct pinctrl_gpio_range *gpioranges;\n\tint ngpioranges;\n};\n\nstruct mvebu_pwm {\n\tstruct regmap *regs;\n\tu32 offset;\n\tlong unsigned int clk_rate;\n\tstruct gpio_desc *gpiod;\n\tspinlock_t lock;\n\tstruct mvebu_gpio_chip *mvchip;\n\tu32 blink_select;\n\tu32 blink_on_duration;\n\tu32 blink_off_duration;\n};\n\nstruct mvebu_sei_caps;\n\nstruct mvebu_sei {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct resource *res;\n\tstruct irq_domain *sei_domain;\n\tstruct irq_domain *ap_domain;\n\tstruct irq_domain *cp_domain;\n\tconst struct mvebu_sei_caps *caps;\n\tstruct mutex cp_msi_lock;\n\tlong unsigned int cp_msi_bitmap[1];\n\traw_spinlock_t mask_lock;\n};\n\nstruct mvebu_sei_interrupt_range {\n\tu32 first;\n\tu32 size;\n};\n\nstruct mvebu_sei_caps {\n\tstruct mvebu_sei_interrupt_range ap_range;\n\tstruct mvebu_sei_interrupt_range cp_range;\n};\n\nstruct mvebu_uart_pm_regs {\n\tunsigned int rbr;\n\tunsigned int tsh;\n\tunsigned int ctrl;\n\tunsigned int intr;\n\tunsigned int stat;\n\tunsigned int brdv;\n\tunsigned int osamp;\n};\n\nstruct mvebu_uart_driver_data;\n\nstruct mvebu_uart {\n\tstruct uart_port *port;\n\tstruct clk *clk;\n\tint irq[2];\n\tstruct mvebu_uart_driver_data *data;\n\tstruct mvebu_uart_pm_regs pm_regs;\n};\n\nstruct mvebu_uart_clock {\n\tstruct clk_hw clk_hw;\n\tint clock_idx;\n\tu32 pm_context_reg1;\n\tu32 pm_context_reg2;\n};\n\nstruct mvebu_uart_clock_base {\n\tstruct mvebu_uart_clock clocks[2];\n\tunsigned int parent_rates[5];\n\tint parent_idx;\n\tunsigned int div;\n\tvoid *reg1;\n\tvoid *reg2;\n\tbool configured;\n};\n\nstruct uart_regs_layout {\n\tunsigned int rbr;\n\tunsigned int tsh;\n\tunsigned int ctrl;\n\tunsigned int intr;\n};\n\nstruct uart_flags {\n\tunsigned int ctrl_tx_rdy_int;\n\tunsigned int ctrl_rx_rdy_int;\n\tunsigned int stat_tx_rdy;\n\tunsigned int stat_rx_rdy;\n};\n\nstruct mvebu_uart_driver_data {\n\tbool is_ext;\n\tstruct uart_regs_layout regs;\n\tstruct uart_flags flags;\n};\n\nstruct mvneta_bm_pool;\n\nstruct mvneta_bm {\n\tvoid *reg_base;\n\tstruct clk *clk;\n\tstruct platform_device *pdev;\n\tstruct gen_pool *bppi_pool;\n\tvoid *bppi_virt_addr;\n\tdma_addr_t bppi_phys_addr;\n\tstruct mvneta_bm_pool *bm_pools;\n};\n\nstruct mvneta_bm_pool {\n\tstruct hwbm_pool hwbm_pool;\n\tu8 id;\n\tenum mvneta_bm_type type;\n\tint pkt_size;\n\tu32 buf_size;\n\tu32 *virt_addr;\n\tdma_addr_t phys_addr;\n\tu8 port_map;\n\tstruct mvneta_bm *priv;\n};\n\nstruct mvneta_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 xdp_redirect;\n\tu64 xdp_pass;\n\tu64 xdp_drop;\n\tu64 xdp_xmit;\n\tu64 xdp_xmit_err;\n\tu64 xdp_tx;\n\tu64 xdp_tx_err;\n};\n\nstruct mvneta_ethtool_stats {\n\tstruct mvneta_stats ps;\n\tu64 skb_alloc_error;\n\tu64 refill_error;\n};\n\nstruct mvneta_port;\n\nstruct mvneta_pcpu_port {\n\tstruct mvneta_port *pp;\n\tstruct napi_struct napi;\n\tu32 cause_rx_tx;\n};\n\nstruct mvneta_pcpu_stats {\n\tstruct u64_stats_sync syncp;\n\tstruct mvneta_ethtool_stats es;\n\tu64 rx_dropped;\n\tu64 rx_errors;\n};\n\nstruct mvneta_rx_queue;\n\nstruct mvneta_tx_queue;\n\nstruct mvneta_port {\n\tu8 id;\n\tstruct mvneta_pcpu_port *ports;\n\tstruct mvneta_pcpu_stats *stats;\n\tlong unsigned int state;\n\tint pkt_size;\n\tvoid *base;\n\tstruct mvneta_rx_queue *rxqs;\n\tstruct mvneta_tx_queue *txqs;\n\tstruct net_device *dev;\n\tstruct hlist_node node_online;\n\tstruct hlist_node node_dead;\n\tint rxq_def;\n\tspinlock_t lock;\n\tbool is_stopped;\n\tu32 cause_rx_tx;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tstruct clk *clk;\n\tstruct clk *clk_bus;\n\tu8 mcast_count[256];\n\tu16 tx_ring_size;\n\tu16 rx_ring_size;\n\tphy_interface_t phy_interface;\n\tstruct device_node *dn;\n\tunsigned int tx_csum_limit;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tstruct phylink_pcs phylink_pcs;\n\tstruct phy *comphy;\n\tstruct mvneta_bm *bm_priv;\n\tstruct mvneta_bm_pool *pool_long;\n\tstruct mvneta_bm_pool *pool_short;\n\tint bm_win_id;\n\tu64 ethtool_stats[42];\n\tu32 indir[1];\n\tbool neta_armada3700;\n\tbool neta_ac5;\n\tu16 rx_offset_correction;\n\tconst struct mbus_dram_target_info *dram_target_info;\n};\n\nstruct mvneta_rx_desc {\n\tu32 status;\n\tu16 reserved1;\n\tu16 data_size;\n\tu32 buf_phys_addr;\n\tu32 reserved2;\n\tu32 buf_cookie;\n\tu16 reserved3;\n\tu16 reserved4;\n\tu32 reserved5;\n\tu32 reserved6;\n};\n\nstruct mvneta_rx_queue {\n\tu8 id;\n\tint size;\n\tu32 pkts_coal;\n\tu32 time_coal;\n\tstruct page_pool *page_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tvoid **buf_virt_addr;\n\tstruct mvneta_rx_desc *descs;\n\tdma_addr_t descs_phys;\n\tint last_desc;\n\tint next_desc_to_proc;\n\tint first_to_refill;\n\tu32 refill_num;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mvneta_statistic {\n\tshort unsigned int offset;\n\tshort unsigned int type;\n\tconst char name[32];\n};\n\nstruct mvneta_tx_buf {\n\tenum mvneta_tx_buf_type type;\n\tunion {\n\t\tstruct xdp_frame *xdpf;\n\t\tstruct sk_buff *skb;\n\t};\n};\n\nstruct mvneta_tx_desc {\n\tu32 command;\n\tu16 reserved1;\n\tu16 data_size;\n\tu32 buf_phys_addr;\n\tu32 reserved2;\n\tu32 reserved3[4];\n};\n\nstruct mvneta_tx_queue {\n\tu8 id;\n\tint size;\n\tint count;\n\tint pending;\n\tint tx_stop_threshold;\n\tint tx_wake_threshold;\n\tstruct mvneta_tx_buf *buf;\n\tint txq_put_index;\n\tint txq_get_index;\n\tu32 done_pkts_coal;\n\tstruct mvneta_tx_desc *descs;\n\tdma_addr_t descs_phys;\n\tint last_desc;\n\tint next_desc_to_proc;\n\tchar *tso_hdrs[32];\n\tdma_addr_t tso_hdrs_phys[32];\n\tcpumask_t affinity_mask;\n};\n\nstruct mvpp2_tai;\n\nstruct mvpp2_port;\n\nstruct mvpp2_tx_queue;\n\nstruct mvpp2_bm_pool;\n\nstruct mvpp2_prs_shadow;\n\nstruct mvpp2_dbgfs_entries;\n\nstruct mvpp2_rss_table;\n\nstruct mvpp2 {\n\tvoid *lms_base;\n\tvoid *iface_base;\n\tvoid *cm3_base;\n\tvoid *swth_base[9];\n\tstruct regmap *sysctrl_base;\n\tstruct clk *pp_clk;\n\tstruct clk *gop_clk;\n\tstruct clk *mg_clk;\n\tstruct clk *mg_core_clk;\n\tstruct clk *axi_clk;\n\tint port_count;\n\tstruct mvpp2_port *port_list[4];\n\tlong unsigned int port_map;\n\tstruct mvpp2_tai *tai;\n\tunsigned int nthreads;\n\tlong unsigned int lock_map;\n\tstruct mvpp2_tx_queue *aggr_txqs;\n\tint percpu_pools;\n\tstruct mvpp2_bm_pool *bm_pools;\n\tstruct mvpp2_prs_shadow *prs_shadow;\n\tbool *prs_double_vlans;\n\tu32 tclk;\n\tenum {\n\t\tMVPP21 = 0,\n\t\tMVPP22 = 1,\n\t\tMVPP23 = 2,\n\t} hw_version;\n\tunsigned int max_port_rxqs;\n\tchar queue_name[31];\n\tstruct workqueue_struct *stats_queue;\n\tstruct dentry *dbgfs_dir;\n\tstruct mvpp2_dbgfs_entries *dbgfs_entries;\n\tstruct mvpp2_rss_table *rss_tables[8];\n\tstruct page_pool *page_pool[32];\n\tbool global_tx_fc;\n\tspinlock_t mss_spinlock;\n\tspinlock_t prs_spinlock;\n};\n\nstruct mvpp21_rx_desc {\n\t__le32 status;\n\t__le16 reserved1;\n\t__le16 data_size;\n\t__le32 buf_dma_addr;\n\t__le32 buf_cookie;\n\t__le16 reserved2;\n\t__le16 reserved3;\n\tu8 reserved4;\n\tu8 reserved5;\n\t__le16 reserved6;\n\t__le32 reserved7;\n\t__le32 reserved8;\n};\n\nstruct mvpp21_tx_desc {\n\t__le32 command;\n\tu8 packet_offset;\n\tu8 phys_txq;\n\t__le16 data_size;\n\t__le32 buf_dma_addr;\n\t__le32 buf_cookie;\n\t__le32 reserved1[3];\n\t__le32 reserved2;\n};\n\nstruct mvpp22_rx_desc {\n\t__le32 status;\n\t__le16 reserved1;\n\t__le16 data_size;\n\t__le32 reserved2;\n\t__le32 timestamp;\n\t__le64 buf_dma_addr_key_hash;\n\t__le64 buf_cookie_misc;\n};\n\nstruct mvpp22_tx_desc {\n\t__le32 command;\n\tu8 packet_offset;\n\tu8 phys_txq;\n\t__le16 data_size;\n\t__le32 ptp_descriptor;\n\t__le32 reserved2;\n\t__le64 buf_dma_addr_ptp;\n\t__le64 buf_cookie_misc;\n};\n\nstruct mvpp2_bm_pool {\n\tint id;\n\tint size;\n\tint size_bytes;\n\tint buf_num;\n\tint buf_size;\n\tint pkt_size;\n\tint frag_size;\n\tu32 *virt_addr;\n\tdma_addr_t dma_addr;\n\tu32 port_map;\n};\n\nstruct mvpp2_buff_hdr {\n\t__le32 next_phys_addr;\n\t__le32 next_dma_addr;\n\t__le16 byte_count;\n\t__le16 info;\n\t__le16 reserved1;\n\tu8 next_phys_addr_high;\n\tu8 next_dma_addr_high;\n\t__le16 reserved2;\n\t__le16 reserved3;\n\t__le16 reserved4;\n\t__le16 reserved5;\n};\n\nstruct mvpp2_cls_c2_entry {\n\tu32 index;\n\tu32 tcam[5];\n\tu32 act;\n\tu32 attr[5];\n\tu8 valid;\n};\n\nstruct mvpp2_prs_result_info {\n\tu32 ri;\n\tu32 ri_mask;\n};\n\nstruct mvpp2_cls_flow {\n\tint flow_type;\n\tu16 flow_id;\n\tu16 supported_hash_opts;\n\tstruct mvpp2_prs_result_info prs_ri;\n};\n\nstruct mvpp2_cls_flow_entry {\n\tu32 index;\n\tu32 data[3];\n};\n\nstruct mvpp2_cls_lookup_entry {\n\tu32 lkpid;\n\tu32 way;\n\tu32 data;\n};\n\nstruct mvpp2_dbgfs_c2_entry {\n\tint id;\n\tstruct mvpp2 *priv;\n};\n\nstruct mvpp2_dbgfs_prs_entry {\n\tint tid;\n\tstruct mvpp2 *priv;\n};\n\nstruct mvpp2_dbgfs_flow_tbl_entry {\n\tint id;\n\tstruct mvpp2 *priv;\n};\n\nstruct mvpp2_dbgfs_flow_entry {\n\tint flow;\n\tstruct mvpp2 *priv;\n};\n\nstruct mvpp2_dbgfs_port_flow_entry {\n\tstruct mvpp2_port *port;\n\tstruct mvpp2_dbgfs_flow_entry *dbg_fe;\n};\n\nstruct mvpp2_dbgfs_entries {\n\tstruct mvpp2_dbgfs_prs_entry prs_entries[256];\n\tstruct mvpp2_dbgfs_c2_entry c2_entries[256];\n\tstruct mvpp2_dbgfs_flow_tbl_entry flt_entries[512];\n\tstruct mvpp2_dbgfs_flow_entry flow_entries[52];\n\tstruct mvpp2_dbgfs_port_flow_entry port_flow_entries[4];\n};\n\nstruct mvpp2_ethtool_counter {\n\tunsigned int offset;\n\tconst char string[32];\n\tbool reg_is_64b;\n};\n\nstruct mvpp2_rfs_rule {\n\tint loc;\n\tint flow_type;\n\tint c2_index;\n\tu16 hek_fields;\n\tu8 engine;\n\tu64 c2_tcam;\n\tu64 c2_tcam_mask;\n\tstruct flow_rule *flow;\n};\n\nstruct mvpp2_ethtool_fs {\n\tstruct mvpp2_rfs_rule rule;\n\tstruct ethtool_rxnfc rxnfc;\n};\n\nstruct mvpp2_hwtstamp_queue {\n\tstruct sk_buff *skb[32];\n\tu8 next;\n};\n\nstruct mvpp2_pcpu_stats {\n\tstruct u64_stats_sync syncp;\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 xdp_redirect;\n\tu64 xdp_pass;\n\tu64 xdp_drop;\n\tu64 xdp_xmit;\n\tu64 xdp_xmit_err;\n\tu64 xdp_tx;\n\tu64 xdp_tx_err;\n};\n\nstruct mvpp2_queue_vector {\n\tint irq;\n\tstruct napi_struct napi;\n\tenum {\n\t\tMVPP2_QUEUE_VECTOR_SHARED = 0,\n\t\tMVPP2_QUEUE_VECTOR_PRIVATE = 1,\n\t} type;\n\tint sw_thread_id;\n\tu16 sw_thread_mask;\n\tint first_rxq;\n\tint nrxqs;\n\tu32 pending_cause_rx;\n\tstruct mvpp2_port *port;\n\tstruct cpumask *mask;\n};\n\nstruct mvpp2_rx_queue;\n\nstruct mvpp2_port_pcpu;\n\nstruct mvpp2_port {\n\tu8 id;\n\tint gop_id;\n\tint port_irq;\n\tstruct mvpp2 *priv;\n\tstruct fwnode_handle *fwnode;\n\tvoid *base;\n\tvoid *stats_base;\n\tstruct mvpp2_rx_queue **rxqs;\n\tunsigned int nrxqs;\n\tstruct mvpp2_tx_queue **txqs;\n\tunsigned int ntxqs;\n\tstruct net_device *dev;\n\tstruct bpf_prog *xdp_prog;\n\tint pkt_size;\n\tstruct mvpp2_port_pcpu *pcpu;\n\tspinlock_t bm_lock[9];\n\tspinlock_t tx_lock[9];\n\tlong unsigned int flags;\n\tu16 tx_ring_size;\n\tu16 rx_ring_size;\n\tstruct mvpp2_pcpu_stats *stats;\n\tu64 *ethtool_stats;\n\tlong unsigned int state;\n\tstruct mutex gather_stats_lock;\n\tstruct delayed_work stats_work;\n\tstruct device_node *of_node;\n\tphy_interface_t phy_interface;\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tstruct phylink_pcs pcs_gmac;\n\tstruct phylink_pcs pcs_xlg;\n\tstruct phy *comphy;\n\tstruct mvpp2_bm_pool *pool_long;\n\tstruct mvpp2_bm_pool *pool_short;\n\tu8 first_rxq;\n\tstruct mvpp2_queue_vector qvecs[9];\n\tunsigned int nqvecs;\n\tbool has_tx_irqs;\n\tu32 tx_time_coal;\n\tstruct mvpp2_ethtool_fs *rfs_rules[4];\n\tint n_rfs_rules;\n\tint rss_ctx[8];\n\tbool hwtstamp;\n\tbool rx_hwtstamp;\n\tenum hwtstamp_tx_types tx_hwtstamp_type;\n\tstruct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];\n\tbool tx_fc;\n};\n\nstruct mvpp2_port_pcpu {\n\tstruct hrtimer tx_done_timer;\n\tstruct net_device *dev;\n\tbool timer_scheduled;\n};\n\nstruct mvpp2_prs_entry {\n\tu32 index;\n\tu32 tcam[6];\n\tu32 sram[4];\n};\n\nstruct mvpp2_prs_shadow {\n\tbool valid;\n\tbool finish;\n\tint lu;\n\tint udf;\n\tu32 ri;\n\tu32 ri_mask;\n};\n\nstruct mvpp2_rss_table {\n\tu32 indir[32];\n};\n\nstruct mvpp2_rx_desc {\n\tunion {\n\t\tstruct mvpp21_rx_desc pp21;\n\t\tstruct mvpp22_rx_desc pp22;\n\t};\n};\n\nstruct mvpp2_rx_queue {\n\tu8 id;\n\tint size;\n\tu32 pkts_coal;\n\tu32 time_coal;\n\tstruct mvpp2_rx_desc *descs;\n\tdma_addr_t descs_dma;\n\tint last_desc;\n\tint next_desc_to_proc;\n\tint port;\n\tint logic_rxq;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq_short;\n\tstruct xdp_rxq_info xdp_rxq_long;\n};\n\nstruct mvpp2_tx_desc {\n\tunion {\n\t\tstruct mvpp21_tx_desc pp21;\n\t\tstruct mvpp22_tx_desc pp22;\n\t};\n};\n\nstruct mvpp2_txq_pcpu;\n\nstruct mvpp2_tx_queue {\n\tu8 id;\n\tu8 log_id;\n\tint size;\n\tint count;\n\tstruct mvpp2_txq_pcpu *pcpu;\n\tu32 done_pkts_coal;\n\tstruct mvpp2_tx_desc *descs;\n\tdma_addr_t descs_dma;\n\tint last_desc;\n\tint next_desc_to_proc;\n};\n\nstruct mvpp2_txq_pcpu_buf;\n\nstruct mvpp2_txq_pcpu {\n\tunsigned int thread;\n\tint size;\n\tint count;\n\tint wake_threshold;\n\tint stop_threshold;\n\tint reserved_num;\n\tstruct mvpp2_txq_pcpu_buf *buffs;\n\tint txq_put_index;\n\tint txq_get_index;\n\tchar *tso_headers;\n\tdma_addr_t tso_headers_dma;\n};\n\nstruct mvpp2_txq_pcpu_buf {\n\tenum mvpp2_tx_buf_type type;\n\tunion {\n\t\tstruct xdp_frame *xdpf;\n\t\tstruct sk_buff *skb;\n\t};\n\tdma_addr_t dma;\n\tsize_t size;\n};\n\nstruct mxc_gpio_hwdata {\n\tunsigned int dr_reg;\n\tunsigned int gdir_reg;\n\tunsigned int psr_reg;\n\tunsigned int icr1_reg;\n\tunsigned int icr2_reg;\n\tunsigned int imr_reg;\n\tunsigned int isr_reg;\n\tint edge_sel_reg;\n\tunsigned int low_level;\n\tunsigned int high_level;\n\tunsigned int rise_edge;\n\tunsigned int fall_edge;\n};\n\nstruct mxc_gpio_reg_saved {\n\tu32 icr1;\n\tu32 icr2;\n\tu32 imr;\n\tu32 gdir;\n\tu32 edge_sel;\n\tu32 dr;\n};\n\nstruct mxc_gpio_port {\n\tstruct list_head node;\n\tvoid *base;\n\tstruct clk *clk;\n\tint irq;\n\tint irq_high;\n\tvoid (*mx_irq_handler)(struct irq_desc *);\n\tstruct irq_domain *domain;\n\tstruct gpio_generic_chip gen_gc;\n\tstruct device *dev;\n\tu32 both_edges;\n\tstruct mxc_gpio_reg_saved gpio_saved_reg;\n\tbool power_off;\n\tu32 wakeup_pads;\n\tbool is_pad_wakeup;\n\tu32 pad_type[32];\n\tconst struct mxc_gpio_hwdata *hwdata;\n};\n\nstruct my_u {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u0 {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u1 {\n\t__le64 a;\n\t__le64 b;\n\t__le64 c;\n\t__le64 d;\n};\n\nstruct n5x_perip_c_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tlong unsigned int shift;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[4];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[64];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct name_resp {\n\tchar name[16];\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct nand_bbt_descr {\n\tint options;\n\tint pages[8];\n\tint offs;\n\tint veroffs;\n\tuint8_t version[8];\n\tint len;\n\tint maxblocks;\n\tint reserved_block_code;\n\tuint8_t *pattern;\n};\n\nstruct nand_operation;\n\nstruct nand_controller_ops {\n\tint (*attach_chip)(struct nand_chip *);\n\tvoid (*detach_chip)(struct nand_chip *);\n\tint (*exec_op)(struct nand_chip *, const struct nand_operation *, bool);\n\tint (*setup_interface)(struct nand_chip *, int, const struct nand_interface_config *);\n};\n\nstruct nand_ecc_step_info;\n\nstruct nand_ecc_caps {\n\tconst struct nand_ecc_step_info *stepinfos;\n\tint nstepinfos;\n\tint (*calc_ecc_bytes)(int, int);\n};\n\nstruct nand_ecc_engine_ops;\n\nstruct nand_ecc_engine {\n\tstruct device *dev;\n\tstruct list_head node;\n\tconst struct nand_ecc_engine_ops *ops;\n\tenum nand_ecc_engine_integration integration;\n\tvoid *priv;\n};\n\nstruct nand_page_io_req;\n\nstruct nand_ecc_engine_ops {\n\tint (*init_ctx)(struct nand_device *);\n\tvoid (*cleanup_ctx)(struct nand_device *);\n\tint (*prepare_io_req)(struct nand_device *, struct nand_page_io_req *);\n\tint (*finish_io_req)(struct nand_device *, struct nand_page_io_req *);\n};\n\nstruct nand_pos {\n\tunsigned int target;\n\tunsigned int lun;\n\tunsigned int plane;\n\tunsigned int eraseblock;\n\tunsigned int page;\n};\n\nstruct nand_page_io_req {\n\tenum nand_page_io_req_type type;\n\tstruct nand_pos pos;\n\tunsigned int dataoffs;\n\tunsigned int datalen;\n\tunion {\n\t\tconst void *out;\n\t\tvoid *in;\n\t} databuf;\n\tunsigned int ooboffs;\n\tunsigned int ooblen;\n\tunion {\n\t\tconst void *out;\n\t\tvoid *in;\n\t} oobbuf;\n\tint mode;\n\tbool continuous;\n};\n\nstruct nand_ecc_req_tweak_ctx {\n\tstruct nand_page_io_req orig_req;\n\tstruct nand_device *nand;\n\tunsigned int page_buffer_size;\n\tunsigned int oob_buffer_size;\n\tvoid *spare_databuf;\n\tvoid *spare_oobbuf;\n\tbool bounce_data;\n\tbool bounce_oob;\n};\n\nstruct nand_ecc_step_info {\n\tint stepsize;\n\tconst int *strengths;\n\tint nstrengths;\n};\n\nstruct nand_ecc_sw_hamming_conf {\n\tstruct nand_ecc_req_tweak_ctx req_ctx;\n\tunsigned int code_size;\n\tu8 *calc_buf;\n\tu8 *code_buf;\n\tunsigned int sm_order;\n};\n\nstruct nand_oobfree {\n\t__u32 offset;\n\t__u32 length;\n};\n\nstruct nand_ecclayout_user {\n\t__u32 eccbytes;\n\t__u32 eccpos[64];\n\t__u32 oobavail;\n\tstruct nand_oobfree oobfree[8];\n};\n\nstruct nand_flash_dev {\n\tchar *name;\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t mfr_id;\n\t\t\tuint8_t dev_id;\n\t\t};\n\t\tuint8_t id[8];\n\t};\n\tunsigned int pagesize;\n\tunsigned int chipsize;\n\tunsigned int erasesize;\n\tunsigned int options;\n\tuint16_t id_len;\n\tuint16_t oobsize;\n\tstruct {\n\t\tuint16_t strength_ds;\n\t\tuint16_t step_ds;\n\t} ecc;\n};\n\nstruct nand_sdr_timings {\n\tu64 tBERS_max;\n\tu32 tCCS_min;\n\tu64 tPROG_max;\n\tu64 tR_max;\n\tu32 tALH_min;\n\tu32 tADL_min;\n\tu32 tALS_min;\n\tu32 tAR_min;\n\tu32 tCEA_max;\n\tu32 tCEH_min;\n\tu32 tCH_min;\n\tu32 tCHZ_max;\n\tu32 tCLH_min;\n\tu32 tCLR_min;\n\tu32 tCLS_min;\n\tu32 tCOH_min;\n\tu32 tCS_min;\n\tu32 tDH_min;\n\tu32 tDS_min;\n\tu32 tFEAT_max;\n\tu32 tIR_min;\n\tu32 tITC_max;\n\tu32 tRC_min;\n\tu32 tREA_max;\n\tu32 tREH_min;\n\tu32 tRHOH_min;\n\tu32 tRHW_min;\n\tu32 tRHZ_max;\n\tu32 tRLOH_min;\n\tu32 tRP_min;\n\tu32 tRR_min;\n\tu64 tRST_max;\n\tu32 tWB_max;\n\tu32 tWC_min;\n\tu32 tWH_min;\n\tu32 tWHR_min;\n\tu32 tWP_min;\n\tu32 tWW_min;\n};\n\nstruct nand_nvddr_timings {\n\tu64 tBERS_max;\n\tu32 tCCS_min;\n\tu64 tPROG_max;\n\tu64 tR_max;\n\tu32 tAC_min;\n\tu32 tAC_max;\n\tu32 tADL_min;\n\tu32 tCAD_min;\n\tu32 tCAH_min;\n\tu32 tCALH_min;\n\tu32 tCALS_min;\n\tu32 tCAS_min;\n\tu32 tCEH_min;\n\tu32 tCH_min;\n\tu32 tCK_min;\n\tu32 tCS_min;\n\tu32 tDH_min;\n\tu32 tDQSCK_min;\n\tu32 tDQSCK_max;\n\tu32 tDQSD_min;\n\tu32 tDQSD_max;\n\tu32 tDQSHZ_max;\n\tu32 tDQSQ_max;\n\tu32 tDS_min;\n\tu32 tDSC_min;\n\tu32 tFEAT_max;\n\tu32 tITC_max;\n\tu32 tQHS_max;\n\tu32 tRHW_min;\n\tu32 tRR_min;\n\tu32 tRST_max;\n\tu32 tWB_max;\n\tu32 tWHR_min;\n\tu32 tWRCK_min;\n\tu32 tWW_min;\n};\n\nstruct nand_timings {\n\tunsigned int mode;\n\tunion {\n\t\tstruct nand_sdr_timings sdr;\n\t\tstruct nand_nvddr_timings nvddr;\n\t};\n};\n\nstruct nand_interface_config {\n\tenum nand_interface_type type;\n\tstruct nand_timings timings;\n};\n\nstruct nand_jedec_params {\n\tu8 sig[4];\n\t__le16 revision;\n\t__le16 features;\n\tu8 opt_cmd[3];\n\t__le16 sec_cmd;\n\tu8 num_of_param_pages;\n\tu8 reserved0[18];\n\tchar manufacturer[12];\n\tchar model[20];\n\tu8 jedec_id[6];\n\tu8 reserved1[10];\n\t__le32 byte_per_page;\n\t__le16 spare_bytes_per_page;\n\tu8 reserved2[6];\n\t__le32 pages_per_block;\n\t__le32 blocks_per_lun;\n\tu8 lun_count;\n\tu8 addr_cycles;\n\tu8 bits_per_cell;\n\tu8 programs_per_page;\n\tu8 multi_plane_addr;\n\tu8 multi_plane_op_attr;\n\tu8 reserved3[38];\n\t__le16 async_sdr_speed_grade;\n\t__le16 toggle_ddr_speed_grade;\n\t__le16 sync_ddr_speed_grade;\n\tu8 async_sdr_features;\n\tu8 toggle_ddr_features;\n\tu8 sync_ddr_features;\n\t__le16 t_prog;\n\t__le16 t_bers;\n\t__le16 t_r;\n\t__le16 t_r_multi_plane;\n\t__le16 t_ccs;\n\t__le16 io_pin_capacitance_typ;\n\t__le16 input_pin_capacitance_typ;\n\t__le16 clk_pin_capacitance_typ;\n\tu8 driver_strength_support;\n\t__le16 t_adl;\n\tu8 reserved4[36];\n\tu8 guaranteed_good_blocks;\n\t__le16 guaranteed_block_endurance;\n\tstruct jedec_ecc_info ecc_info[4];\n\tu8 reserved5[29];\n\tu8 reserved6[148];\n\t__le16 vendor_rev_num;\n\tu8 reserved7[88];\n\t__le16 crc;\n} __attribute__((packed));\n\nstruct nand_manufacturer_ops;\n\nstruct nand_manufacturer_desc {\n\tint id;\n\tchar *name;\n\tconst struct nand_manufacturer_ops *ops;\n};\n\nstruct nand_onfi_params;\n\nstruct nand_manufacturer_ops {\n\tvoid (*detect)(struct nand_chip *);\n\tint (*init)(struct nand_chip *);\n\tvoid (*cleanup)(struct nand_chip *);\n\tvoid (*fixup_onfi_param_page)(struct nand_chip *, struct nand_onfi_params *);\n};\n\nstruct nand_onfi_params {\n\tu8 sig[4];\n\t__le16 revision;\n\t__le16 features;\n\t__le16 opt_cmd;\n\tu8 reserved0[2];\n\t__le16 ext_param_page_length;\n\tu8 num_of_param_pages;\n\tu8 reserved1[17];\n\tchar manufacturer[12];\n\tchar model[20];\n\tu8 jedec_id;\n\t__le16 date_code;\n\tu8 reserved2[13];\n\t__le32 byte_per_page;\n\t__le16 spare_bytes_per_page;\n\t__le32 data_bytes_per_ppage;\n\t__le16 spare_bytes_per_ppage;\n\t__le32 pages_per_block;\n\t__le32 blocks_per_lun;\n\tu8 lun_count;\n\tu8 addr_cycles;\n\tu8 bits_per_cell;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 guaranteed_good_blocks;\n\t__le16 guaranteed_block_endurance;\n\tu8 programs_per_page;\n\tu8 ppage_attr;\n\tu8 ecc_bits;\n\tu8 interleaved_bits;\n\tu8 interleaved_ops;\n\tu8 reserved3[13];\n\tu8 io_pin_capacitance_max;\n\t__le16 sdr_timing_modes;\n\t__le16 program_cache_timing_mode;\n\t__le16 t_prog;\n\t__le16 t_bers;\n\t__le16 t_r;\n\t__le16 t_ccs;\n\tu8 nvddr_timing_modes;\n\tu8 nvddr2_timing_modes;\n\tu8 nvddr_nvddr2_features;\n\t__le16 clk_pin_capacitance_typ;\n\t__le16 io_pin_capacitance_typ;\n\t__le16 input_pin_capacitance_typ;\n\tu8 input_pin_capacitance_max;\n\tu8 driver_strength_support;\n\t__le16 t_int_r;\n\t__le16 t_adl;\n\tu8 reserved4[8];\n\t__le16 vendor_revision;\n\tu8 vendor[88];\n\t__le16 crc;\n} __attribute__((packed));\n\nstruct nand_onfi_vendor_macronix {\n\tu8 reserved;\n\tu8 reliability_func;\n};\n\nstruct nand_onfi_vendor_micron {\n\tu8 two_plane_read;\n\tu8 read_cache;\n\tu8 read_unique_id;\n\tu8 dq_imped;\n\tu8 dq_imped_num_settings;\n\tu8 dq_imped_feat_addr;\n\tu8 rb_pulldown_strength;\n\tu8 rb_pulldown_strength_feat_addr;\n\tu8 rb_pulldown_strength_num_settings;\n\tu8 otp_mode;\n\tu8 otp_page_start;\n\tu8 otp_data_prot_addr;\n\tu8 otp_num_pages;\n\tu8 otp_feat_addr;\n\tu8 read_retry_options;\n\tu8 reserved[72];\n\tu8 param_revision;\n};\n\nstruct nand_oobinfo {\n\t__u32 useecc;\n\t__u32 eccbytes;\n\t__u32 oobfree[16];\n\t__u32 eccpos[32];\n};\n\nstruct nand_op_addr_instr {\n\tunsigned int naddrs;\n\tconst u8 *addrs;\n};\n\nstruct nand_op_cmd_instr {\n\tu8 opcode;\n};\n\nstruct nand_op_data_instr {\n\tunsigned int len;\n\tunion {\n\t\tvoid *in;\n\t\tconst void *out;\n\t} buf;\n\tbool force_8bit;\n};\n\nstruct nand_op_waitrdy_instr {\n\tunsigned int timeout_ms;\n};\n\nstruct nand_op_instr {\n\tenum nand_op_instr_type type;\n\tunion {\n\t\tstruct nand_op_cmd_instr cmd;\n\t\tstruct nand_op_addr_instr addr;\n\t\tstruct nand_op_data_instr data;\n\t\tstruct nand_op_waitrdy_instr waitrdy;\n\t} ctx;\n\tunsigned int delay_ns;\n};\n\nstruct nand_op_parser_pattern;\n\nstruct nand_op_parser {\n\tconst struct nand_op_parser_pattern *patterns;\n\tunsigned int npatterns;\n};\n\nstruct nand_op_parser_addr_constraints {\n\tunsigned int maxcycles;\n};\n\nstruct nand_subop {\n\tunsigned int cs;\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n\tunsigned int first_instr_start_off;\n\tunsigned int last_instr_end_off;\n};\n\nstruct nand_op_parser_ctx {\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n\tstruct nand_subop subop;\n};\n\nstruct nand_op_parser_data_constraints {\n\tunsigned int maxlen;\n};\n\nstruct nand_op_parser_pattern_elem;\n\nstruct nand_op_parser_pattern {\n\tconst struct nand_op_parser_pattern_elem *elems;\n\tunsigned int nelems;\n\tint (*exec)(struct nand_chip *, const struct nand_subop *);\n};\n\nstruct nand_op_parser_pattern_elem {\n\tenum nand_op_instr_type type;\n\tbool optional;\n\tunion {\n\t\tstruct nand_op_parser_addr_constraints addr;\n\t\tstruct nand_op_parser_data_constraints data;\n\t} ctx;\n};\n\nstruct nand_operation {\n\tunsigned int cs;\n\tbool deassert_wp;\n\tconst struct nand_op_instr *instrs;\n\tunsigned int ninstrs;\n};\n\nstruct nand_ops {\n\tint (*erase)(struct nand_device *, const struct nand_pos *);\n\tint (*markbad)(struct nand_device *, const struct nand_pos *);\n\tbool (*isbad)(struct nand_device *, const struct nand_pos *);\n};\n\nstruct nand_secure_region {\n\tu64 offset;\n\tu64 size;\n};\n\nstruct nandc_regs {\n\t__le32 cmd;\n\t__le32 addr0;\n\t__le32 addr1;\n\t__le32 chip_sel;\n\t__le32 exec;\n\t__le32 cfg0;\n\t__le32 cfg1;\n\t__le32 ecc_bch_cfg;\n\t__le32 clrflashstatus;\n\t__le32 clrreadstatus;\n\t__le32 cmd1;\n\t__le32 vld;\n\t__le32 orig_cmd1;\n\t__le32 orig_vld;\n\t__le32 ecc_buf_cfg;\n\t__le32 read_location0;\n\t__le32 read_location1;\n\t__le32 read_location2;\n\t__le32 read_location3;\n\t__le32 read_location_last0;\n\t__le32 read_location_last1;\n\t__le32 read_location_last2;\n\t__le32 read_location_last3;\n\t__le32 spi_cfg;\n\t__le32 num_addr_cycle;\n\t__le32 busy_wait_cnt;\n\t__le32 flash_feature;\n\t__le32 erased_cw_detect_cfg_clr;\n\t__le32 erased_cw_detect_cfg_set;\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u32 offset;\n\t__u32 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tlong: 0;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct ref_tracker_dir {};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct udp_mib *udplite_statistics;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 0;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tu32 multipath_hash_fields;\n\tu8 multipath_hash_policy;\n\t__u8 __cacheline_group_begin__sysctl_ipv6_flowlabel[0];\n\tu8 flowlabel_consistency;\n\tu8 auto_flowlabels;\n\tu8 flowlabel_state_ranges;\n\t__u8 __cacheline_group_end__sysctl_ipv6_flowlabel[0];\n\tu8 icmpv6_echo_ignore_all;\n\tu8 icmpv6_echo_ignore_multicast;\n\tu8 icmpv6_echo_ignore_anycast;\n\tint icmpv6_time;\n\tlong unsigned int icmpv6_ratemask[4];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tu8 anycast_src_echo_reply;\n\tu8 bindv6only;\n\tu8 ip_nonlocal_bind;\n\tu8 fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tu32 ioam6_id;\n\tu64 ioam6_id_wide;\n\tu8 skip_notify_on_dev_down;\n\tu8 fib_notify_on_flag_change;\n\tu8 icmpv6_error_anycast_as_unicast;\n\tu8 icmpv6_errors_extension_mask;\n};\n\nstruct ioam6_pernet_data;\n\nstruct rt6_statistics;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct dst_ops ip6_dst_ops;\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tspinlock_t fib_table_hash_lock;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tatomic_t ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned char flowlabel_has_excl;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct hlist_head *inet6_addr_lst;\n\tspinlock_t addrconf_hash_lock;\n\tstruct delayed_work addr_chk_work;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tstruct ioam6_pernet_data *ioam6_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nf_logger;\n\nstruct nf_hook_entries;\n\nstruct netns_nf {\n\tstruct proc_dir_entry *proc_netfilter;\n\tconst struct nf_logger *nf_loggers[11];\n\tstruct ctl_table_header *nf_log_dir_header;\n\tstruct nf_hook_entries *hooks_ipv4[5];\n\tstruct nf_hook_entries *hooks_ipv6[5];\n\tstruct nf_hook_entries *hooks_bridge[5];\n\tunsigned int defrag_ipv4_users;\n\tunsigned int defrag_ipv6_users;\n};\n\nstruct nf_generic_net {\n\tunsigned int timeout;\n};\n\nstruct nf_tcp_net {\n\tunsigned int timeouts[14];\n\tu8 tcp_loose;\n\tu8 tcp_be_liberal;\n\tu8 tcp_max_retrans;\n\tu8 tcp_ignore_invalid_rst;\n};\n\nstruct nf_udp_net {\n\tunsigned int timeouts[2];\n};\n\nstruct nf_icmp_net {\n\tunsigned int timeout;\n};\n\nstruct nf_sctp_net {\n\tunsigned int timeouts[10];\n};\n\nstruct nf_ip_net {\n\tstruct nf_generic_net generic;\n\tstruct nf_tcp_net tcp;\n\tstruct nf_udp_net udp;\n\tstruct nf_icmp_net icmp;\n\tstruct nf_icmp_net icmpv6;\n\tstruct nf_sctp_net sctp;\n};\n\nstruct nf_ct_event_notifier;\n\nstruct netns_ct {\n\tbool ecache_dwork_pending;\n\tu8 sysctl_log_invalid;\n\tu8 sysctl_events;\n\tu8 sysctl_acct;\n\tu8 sysctl_tstamp;\n\tu8 sysctl_checksum;\n\tstruct ip_conntrack_stat *stat;\n\tstruct nf_ct_event_notifier *nf_conntrack_event_cb;\n\tstruct nf_ip_net nf_ct_proto;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct netns_ipvs;\n\nstruct can_dev_rcv_lists;\n\nstruct can_pkg_stats;\n\nstruct can_rcv_lists_stats;\n\nstruct netns_can {\n\tstruct proc_dir_entry *proc_dir;\n\tstruct proc_dir_entry *pde_stats;\n\tstruct proc_dir_entry *pde_reset_stats;\n\tstruct proc_dir_entry *pde_rcvlist_all;\n\tstruct proc_dir_entry *pde_rcvlist_fil;\n\tstruct proc_dir_entry *pde_rcvlist_inv;\n\tstruct proc_dir_entry *pde_rcvlist_sff;\n\tstruct proc_dir_entry *pde_rcvlist_eff;\n\tstruct proc_dir_entry *pde_rcvlist_err;\n\tstruct proc_dir_entry *bcmproc_dir;\n\tstruct can_dev_rcv_lists *rx_alldev_list;\n\tspinlock_t rcvlists_lock;\n\tstruct timer_list stattimer;\n\tstruct can_pkg_stats *pkg_stats;\n\tstruct can_rcv_lists_stats *rcv_lists_stats;\n\tstruct hlist_head cgw_list;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct netns_nf nf;\n\tstruct netns_ct ct;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tu64 net_cookie;\n\tstruct netns_ipvs *ipvs;\n\tstruct netns_can can;\n\tstruct sock *crypto_nlsk;\n\tstruct sock *diag_nlsk;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct net_bridge;\n\nstruct net_bridge_vlan;\n\nstruct net_bridge_mcast {\n\tstruct net_bridge *br;\n\tstruct net_bridge_vlan *vlan;\n\tu32 multicast_last_member_count;\n\tu32 multicast_startup_query_count;\n\tu8 multicast_querier;\n\tu8 multicast_igmp_version;\n\tu8 multicast_router;\n\tu8 multicast_mld_version;\n\tlong unsigned int multicast_last_member_interval;\n\tlong unsigned int multicast_membership_interval;\n\tlong unsigned int multicast_querier_interval;\n\tlong unsigned int multicast_query_interval;\n\tlong unsigned int multicast_query_response_interval;\n\tlong unsigned int multicast_startup_query_interval;\n\tstruct hlist_head ip4_mc_router_list;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct bridge_mcast_other_query ip4_other_query;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct bridge_mcast_querier ip4_querier;\n\tstruct hlist_head ip6_mc_router_list;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct bridge_mcast_other_query ip6_other_query;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct bridge_mcast_querier ip6_querier;\n};\n\nstruct net_bridge_vlan_group;\n\nstruct net_bridge {\n\tspinlock_t lock;\n\tspinlock_t hash_lock;\n\tstruct hlist_head frame_type_list;\n\tstruct net_device *dev;\n\tlong unsigned int options;\n\t__be16 vlan_proto;\n\tu16 default_pvid;\n\tstruct net_bridge_vlan_group *vlgrp;\n\tstruct rhashtable fdb_hash_tbl;\n\tstruct list_head port_list;\n\tunion {\n\t\tstruct rtable fake_rtable;\n\t\tstruct rt6_info fake_rt6_info;\n\t};\n\tu32 metrics[17];\n\tu16 group_fwd_mask;\n\tu16 group_fwd_mask_required;\n\tbridge_id designated_root;\n\tbridge_id bridge_id;\n\tunsigned char topology_change;\n\tunsigned char topology_change_detected;\n\tu16 root_port;\n\tlong unsigned int max_age;\n\tlong unsigned int hello_time;\n\tlong unsigned int forward_delay;\n\tlong unsigned int ageing_time;\n\tlong unsigned int bridge_max_age;\n\tlong unsigned int bridge_hello_time;\n\tlong unsigned int bridge_forward_delay;\n\tlong unsigned int bridge_ageing_time;\n\tu32 root_path_cost;\n\tu8 group_addr[6];\n\tenum {\n\t\tBR_NO_STP = 0,\n\t\tBR_KERNEL_STP = 1,\n\t\tBR_USER_STP = 2,\n\t} stp_enabled;\n\tstruct net_bridge_mcast multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 hash_max;\n\tspinlock_t multicast_lock;\n\tstruct rhashtable mdb_hash_tbl;\n\tstruct rhashtable sg_port_tbl;\n\tstruct hlist_head mcast_gc_list;\n\tstruct hlist_head mdb_list;\n\tstruct work_struct mcast_gc_work;\n\tstruct timer_list hello_timer;\n\tstruct timer_list tcn_timer;\n\tstruct timer_list topology_change_timer;\n\tstruct delayed_work gc_work;\n\tstruct kobject *ifobj;\n\tu32 auto_cnt;\n\tatomic_t fdb_n_learned;\n\tu32 fdb_max_learned;\n\tint last_hwdom;\n\tlong unsigned int busy_hwdoms;\n\tstruct hlist_head fdb_list;\n};\n\nstruct net_bridge_fdb_key {\n\tmac_addr addr;\n\tu16 vlan_id;\n};\n\nstruct net_bridge_port;\n\nstruct net_bridge_fdb_entry {\n\tstruct rhash_head rhnode;\n\tstruct net_bridge_port *dst;\n\tstruct net_bridge_fdb_key key;\n\tstruct hlist_node fdb_node;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_bridge_mcast_port {\n\tstruct net_bridge_port *port;\n\tstruct net_bridge_vlan *vlan;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct hlist_node ip4_rlist;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct hlist_node ip6_rlist;\n\tunsigned char multicast_router;\n\tu32 mdb_n_entries;\n\tu32 mdb_max_entries;\n};\n\nstruct net_bridge_port {\n\tstruct net_bridge *br;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tstruct net_bridge_vlan_group *vlgrp;\n\tstruct net_bridge_port *backup_port;\n\tu32 backup_nhid;\n\tu8 priority;\n\tu8 state;\n\tu16 port_no;\n\tunsigned char topology_change_ack;\n\tunsigned char config_pending;\n\tport_id port_id;\n\tport_id designated_port;\n\tbridge_id designated_root;\n\tbridge_id designated_bridge;\n\tu32 path_cost;\n\tu32 designated_cost;\n\tlong unsigned int designated_age;\n\tstruct timer_list forward_delay_timer;\n\tstruct timer_list hold_timer;\n\tstruct timer_list message_age_timer;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n\tstruct net_bridge_mcast_port multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 multicast_eht_hosts_limit;\n\tu32 multicast_eht_hosts_cnt;\n\tstruct hlist_head mglist;\n\tchar sysfs_name[16];\n\tint hwdom;\n\tint offload_count;\n\tstruct netdev_phys_item_id ppid;\n\tu16 group_fwd_mask;\n\tu16 backup_redirected_cnt;\n\tstruct bridge_stp_xstats stp_xstats;\n};\n\nstruct pcpu_sw_netstats;\n\nstruct net_bridge_vlan {\n\tstruct rhash_head vnode;\n\tstruct rhash_head tnode;\n\tu16 vid;\n\tu16 flags;\n\tu16 priv_flags;\n\tu8 state;\n\tstruct pcpu_sw_netstats *stats;\n\tunion {\n\t\tstruct net_bridge *br;\n\t\tstruct net_bridge_port *port;\n\t};\n\tunion {\n\t\trefcount_t refcnt;\n\t\tstruct net_bridge_vlan *brvlan;\n\t};\n\tstruct br_tunnel_info tinfo;\n\tunion {\n\t\tstruct net_bridge_mcast br_mcast_ctx;\n\t\tstruct net_bridge_mcast_port port_mcast_ctx;\n\t};\n\tu16 msti;\n\tstruct list_head vlist;\n\tstruct callback_head rcu;\n};\n\nstruct net_bridge_vlan_group {\n\tstruct rhashtable vlan_hash;\n\tstruct rhashtable tunnel_hash;\n\tstruct list_head vlan_list;\n\tu16 num_vlans;\n\tu16 pvid;\n\tu8 pvid_state;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct wireless_dev;\n\nstruct garp_port;\n\nstruct mrp_port;\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_dstats;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct vlan_info;\n\nstruct xdp_dev_bulk_queue;\n\nstruct rtnl_link_ops;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct phy_link_topology;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct nf_hook_entries *nf_hooks_egress;\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tstruct vlan_info *vlan_info;\n\tstruct dsa_port *dsa_ptr;\n\tstruct wireless_dev *ieee80211_ptr;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tstruct nf_hook_entries *nf_hooks_ingress;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct hlist_head qdisc_hash[16];\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct garp_port *garp_port;\n\tstruct mrp_port *mrp_port;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct netdev_bpf;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct net_failover_info {\n\tstruct net_device *primary_dev;\n\tstruct net_device *standby_dev;\n\tstruct rtnl_link_stats64 primary_stats;\n\tstruct rtnl_link_stats64 standby_stats;\n\tstruct rtnl_link_stats64 failover_stats;\n\tspinlock_t stats_lock;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct inet6_protocol tcpv6_protocol;\n\tstruct inet6_protocol udpv6_protocol;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_packet_attrs {\n\tconst unsigned char *src;\n\tconst unsigned char *dst;\n\tu32 ip_src;\n\tu32 ip_dst;\n\tbool tcp;\n\tu16 sport;\n\tu16 dport;\n\tint timeout;\n\tint size;\n\tint max_size;\n\tu8 id;\n\tu16 queue_mapping;\n\tbool bad_csum;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct net_test {\n\tchar name[32];\n\tint (*fn)(struct net_device *);\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct net_test_priv {\n\tstruct net_packet_attrs *packet;\n\tstruct packet_type pt;\n\tstruct completion comp;\n\tint double_vlan;\n\tint vlan_id;\n\tint ok;\n};\n\nunion netc_cbd {\n\tstruct {\n\t\t__le64 addr;\n\t\t__le32 len;\n\t\tu8 cmd;\n\t\tu8 access_method;\n\t\tu8 table_id;\n\t\tu8 ver_cci_rr;\n\t\t__le32 resv[3];\n\t\t__le32 npf;\n\t} req_hdr;\n\tstruct {\n\t\t__le32 resv0[3];\n\t\t__le16 num_matched;\n\t\t__le16 error_rr;\n\t\t__le32 resv1[4];\n\t} resp_hdr;\n};\n\nstruct netc_cbdr_regs {\n\tvoid *pir;\n\tvoid *cir;\n\tvoid *mr;\n\tvoid *bar0;\n\tvoid *bar1;\n\tvoid *lenr;\n};\n\nstruct netc_cbdr {\n\tstruct device *dev;\n\tstruct netc_cbdr_regs regs;\n\tint bd_num;\n\tint next_to_use;\n\tint next_to_clean;\n\tint dma_size;\n\tvoid *addr_base;\n\tvoid *addr_base_align;\n\tdma_addr_t dma_base;\n\tdma_addr_t dma_base_align;\n\tspinlock_t ring_lock;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_lag_lower_state_info {\n\tu8 link_up: 1;\n\tu8 tx_enabled: 1;\n};\n\nstruct netdev_lag_upper_info {\n\tenum netdev_lag_tx_type tx_type;\n\tenum netdev_lag_hash hash_type;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tlong: 64;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tint numa_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n\tu8 sched_mirred_nest;\n\tstruct net_device *sched_mirred_dev[4];\n};\n\nstruct netfront_cb {\n\tint pull_to;\n};\n\nstruct netfront_queue;\n\nstruct netfront_stats;\n\nstruct netfront_info {\n\tstruct list_head list;\n\tstruct net_device *netdev;\n\tstruct xenbus_device *xbdev;\n\tstruct netfront_queue *queues;\n\tstruct netfront_stats *rx_stats;\n\tstruct netfront_stats *tx_stats;\n\tbool netback_has_xdp_headroom;\n\tbool netfront_xdp_enabled;\n\tbool broken;\n\tbool bounce;\n\tatomic_t rx_gso_checksum_fixup;\n};\n\nstruct xen_netif_tx_sring;\n\nstruct xen_netif_tx_front_ring {\n\tRING_IDX req_prod_pvt;\n\tRING_IDX rsp_cons;\n\tunsigned int nr_ents;\n\tstruct xen_netif_tx_sring *sring;\n};\n\nstruct xen_netif_rx_sring;\n\nstruct xen_netif_rx_front_ring {\n\tRING_IDX req_prod_pvt;\n\tRING_IDX rsp_cons;\n\tunsigned int nr_ents;\n\tstruct xen_netif_rx_sring *sring;\n};\n\nstruct netfront_queue {\n\tunsigned int id;\n\tchar name[22];\n\tstruct netfront_info *info;\n\tstruct bpf_prog *xdp_prog;\n\tstruct napi_struct napi;\n\tunsigned int tx_evtchn;\n\tunsigned int rx_evtchn;\n\tunsigned int tx_irq;\n\tunsigned int rx_irq;\n\tchar tx_irq_name[25];\n\tchar rx_irq_name[25];\n\tspinlock_t tx_lock;\n\tstruct xen_netif_tx_front_ring tx;\n\tint tx_ring_ref;\n\tstruct sk_buff *tx_skbs[256];\n\tshort unsigned int tx_link[256];\n\tgrant_ref_t gref_tx_head;\n\tgrant_ref_t grant_tx_ref[256];\n\tstruct page *grant_tx_page[256];\n\tunsigned int tx_skb_freelist;\n\tunsigned int tx_pend_queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t rx_lock;\n\tstruct xen_netif_rx_front_ring rx;\n\tint rx_ring_ref;\n\tstruct timer_list rx_refill_timer;\n\tstruct sk_buff *rx_skbs[256];\n\tgrant_ref_t gref_rx_head;\n\tgrant_ref_t grant_rx_ref[256];\n\tunsigned int rx_rsp_unconsumed;\n\tspinlock_t rx_cons_lock;\n\tstruct page_pool *page_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n};\n\nstruct xen_netif_rx_response {\n\tuint16_t id;\n\tuint16_t offset;\n\tuint16_t flags;\n\tint16_t status;\n};\n\nstruct xen_netif_extra_info {\n\tuint8_t type;\n\tuint8_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tuint16_t size;\n\t\t\tuint8_t type;\n\t\t\tuint8_t pad;\n\t\t\tuint16_t features;\n\t\t} gso;\n\t\tstruct {\n\t\t\tuint8_t addr[6];\n\t\t} mcast;\n\t\tstruct {\n\t\t\tuint8_t type;\n\t\t\tuint8_t algorithm;\n\t\t\tuint8_t value[4];\n\t\t} hash;\n\t\tstruct {\n\t\t\tuint16_t headroom;\n\t\t\tuint16_t pad[2];\n\t\t} xdp;\n\t\tuint16_t pad[3];\n\t} u;\n};\n\nstruct netfront_rx_info {\n\tstruct xen_netif_rx_response rx;\n\tstruct xen_netif_extra_info extras[5];\n};\n\nstruct netfront_stats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\ntypedef void (*netfs_io_terminated_t)(void *, ssize_t);\n\nstruct netfs_io_subrequest;\n\nstruct netfs_cache_ops {\n\tvoid (*end_operation)(struct netfs_cache_resources *);\n\tint (*read)(struct netfs_cache_resources *, loff_t, struct iov_iter *, enum netfs_read_from_hole, netfs_io_terminated_t, void *);\n\tint (*write)(struct netfs_cache_resources *, loff_t, struct iov_iter *, netfs_io_terminated_t, void *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_cache_resources *, long long unsigned int *, long long unsigned int *, long long unsigned int);\n\tenum netfs_io_source (*prepare_read)(struct netfs_io_subrequest *, long long unsigned int);\n\tvoid (*prepare_write_subreq)(struct netfs_io_subrequest *);\n\tint (*prepare_write)(struct netfs_cache_resources *, loff_t *, size_t *, size_t, loff_t, bool);\n\tenum netfs_io_source (*prepare_ondemand_read)(struct netfs_cache_resources *, loff_t, size_t *, loff_t, long unsigned int *, ino_t);\n\tint (*query_occupancy)(struct netfs_cache_resources *, loff_t, size_t, size_t, loff_t *, size_t *);\n};\n\nstruct netfs_cache_resources {\n\tconst struct netfs_cache_ops *ops;\n\tvoid *cache_priv;\n\tvoid *cache_priv2;\n\tunsigned int debug_id;\n\tunsigned int inval_counter;\n};\n\nstruct netfs_group;\n\nstruct netfs_folio {\n\tstruct netfs_group *netfs_group;\n\tunsigned int dirty_offset;\n\tunsigned int dirty_len;\n};\n\nstruct netfs_group {\n\trefcount_t ref;\n\tvoid (*free)(struct netfs_group *);\n};\n\nstruct netfs_request_ops;\n\nstruct netfs_inode {\n\tstruct inode inode;\n\tconst struct netfs_request_ops *ops;\n\tstruct mutex wb_lock;\n\tloff_t remote_i_size;\n\tloff_t zero_point;\n\tatomic_t io_count;\n\tlong unsigned int flags;\n};\n\nstruct netfs_io_stream {\n\tstruct netfs_io_subrequest *construct;\n\tsize_t sreq_max_len;\n\tunsigned int sreq_max_segs;\n\tunsigned int submit_off;\n\tunsigned int submit_len;\n\tunsigned int submit_extendable_to;\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tstruct list_head subrequests;\n\tstruct netfs_io_subrequest *front;\n\tlong long unsigned int collected_to;\n\tsize_t transferred;\n\tshort unsigned int error;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tbool avail;\n\tbool active;\n\tbool need_retry;\n\tbool failed;\n\tbool transferred_valid;\n};\n\nstruct rolling_buffer {\n\tstruct folio_queue *head;\n\tstruct folio_queue *tail;\n\tstruct iov_iter iter;\n\tu8 next_head_slot;\n\tu8 first_tail_slot;\n};\n\nstruct netfs_io_request {\n\tunion {\n\t\tstruct work_struct cleanup_work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct work_struct work;\n\tstruct inode *inode;\n\tstruct address_space *mapping;\n\tstruct kiocb *iocb;\n\tstruct netfs_cache_resources cache_resources;\n\tstruct netfs_io_request *copy_to_cache;\n\tstruct list_head proc_link;\n\tstruct netfs_io_stream io_streams[2];\n\tstruct netfs_group *group;\n\tstruct rolling_buffer buffer;\n\twait_queue_head_t waitq;\n\tvoid *netfs_priv;\n\tvoid *netfs_priv2;\n\tstruct bio_vec *direct_bv;\n\tlong long unsigned int submitted;\n\tlong long unsigned int len;\n\tsize_t transferred;\n\tlong int error;\n\tlong long unsigned int i_size;\n\tlong long unsigned int start;\n\tatomic64_t issued_to;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int abandon_to;\n\tlong unsigned int no_unlock_folio;\n\tunsigned int direct_bv_count;\n\tunsigned int debug_id;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tatomic_t subreq_counter;\n\tunsigned int nr_group_rel;\n\tspinlock_t lock;\n\tunsigned char front_folio_order;\n\tenum netfs_io_origin origin;\n\tbool direct_bv_unpin;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tconst struct netfs_request_ops *netfs_ops;\n};\n\nstruct netfs_io_subrequest {\n\tstruct netfs_io_request *rreq;\n\tstruct work_struct work;\n\tstruct list_head rreq_link;\n\tstruct iov_iter io_iter;\n\tlong long unsigned int start;\n\tsize_t len;\n\tsize_t transferred;\n\trefcount_t ref;\n\tshort int error;\n\tshort unsigned int debug_index;\n\tunsigned int nr_segs;\n\tu8 retry_count;\n\tenum netfs_io_source source;\n\tunsigned char stream_nr;\n\tlong unsigned int flags;\n};\n\nstruct netfs_request_ops {\n\tmempool_t *request_pool;\n\tmempool_t *subrequest_pool;\n\tint (*init_request)(struct netfs_io_request *, struct file *);\n\tvoid (*free_request)(struct netfs_io_request *);\n\tvoid (*free_subrequest)(struct netfs_io_subrequest *);\n\tvoid (*expand_readahead)(struct netfs_io_request *);\n\tint (*prepare_read)(struct netfs_io_subrequest *);\n\tvoid (*issue_read)(struct netfs_io_subrequest *);\n\tbool (*is_still_valid)(struct netfs_io_request *);\n\tint (*check_write_begin)(struct file *, loff_t, unsigned int, struct folio **, void **);\n\tvoid (*done)(struct netfs_io_request *);\n\tvoid (*update_i_size)(struct inode *, loff_t);\n\tvoid (*post_modify)(struct inode *);\n\tvoid (*begin_writeback)(struct netfs_io_request *);\n\tvoid (*prepare_write)(struct netfs_io_subrequest *);\n\tvoid (*issue_write)(struct netfs_io_subrequest *);\n\tvoid (*retry_request)(struct netfs_io_request *, struct netfs_io_stream *);\n\tvoid (*invalidate_cache)(struct netfs_io_request *);\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netsec_de {\n\tu32 attr;\n\tu32 data_buf_addr_up;\n\tu32 data_buf_addr_lw;\n\tu32 buf_len_info;\n};\n\nstruct netsec_desc {\n\tunion {\n\t\tstruct sk_buff *skb;\n\t\tstruct xdp_frame *xdpf;\n\t};\n\tdma_addr_t dma_addr;\n\tvoid *addr;\n\tu16 len;\n\tu8 buf_type;\n};\n\nstruct netsec_desc_ring {\n\tdma_addr_t desc_dma;\n\tstruct netsec_desc *desc;\n\tvoid *vaddr;\n\tu16 head;\n\tu16 tail;\n\tu16 xdp_xmit;\n\tstruct page_pool *page_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netsec_priv {\n\tstruct netsec_desc_ring desc_ring[2];\n\tstruct ethtool_coalesce et_coalesce;\n\tstruct bpf_prog *xdp_prog;\n\tspinlock_t reglock;\n\tstruct napi_struct napi;\n\tphy_interface_t phy_interface;\n\tstruct net_device *ndev;\n\tstruct device_node *phy_np;\n\tstruct phy_device *phydev;\n\tstruct mii_bus *mii_bus;\n\tvoid *ioaddr;\n\tvoid *eeprom_base;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tu32 msg_enable;\n\tu32 freq;\n\tu32 phy_addr;\n\tbool rx_cksum_offload_flag;\n\tlong: 64;\n};\n\nstruct netsec_rx_pkt_info {\n\tint rx_cksum_result;\n\tint err_code;\n\tbool err_flag;\n};\n\nstruct netsec_tx_pkt_ctrl {\n\tu16 tcp_seg_len;\n\tbool tcp_seg_offload_flag;\n\tbool cksum_offload_flag;\n};\n\nstruct netsfhdr {\n\t__be32 version;\n\t__be64 magic;\n\tu8 id;\n} __attribute__((packed));\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_bridge_info {\n\tenum {\n\t\tBRNF_PROTO_UNCHANGED = 0,\n\t\tBRNF_PROTO_8021Q = 1,\n\t\tBRNF_PROTO_PPPOE = 2,\n\t} orig_proto: 8;\n\tu8 pkt_otherhost: 1;\n\tu8 in_prerouting: 1;\n\tu8 bridged_dnat: 1;\n\tu8 sabotage_in_done: 1;\n\t__u16 frag_max_size;\n\tint physinif;\n\tstruct net_device *physoutdev;\n\tunion {\n\t\t__be32 ipv4_daddr;\n\t\tstruct in6_addr ipv6_daddr;\n\t\tchar neigh_header[8];\n\t};\n};\n\nstruct nf_conntrack {\n\trefcount_t use;\n};\n\nunion nf_inet_addr {\n\t__u32 all[4];\n\t__be32 ip;\n\t__be32 ip6[4];\n\tstruct in_addr in;\n\tstruct in6_addr in6;\n};\n\nunion nf_conntrack_man_proto {\n\t__be16 all;\n\tstruct {\n\t\t__be16 port;\n\t} tcp;\n\tstruct {\n\t\t__be16 port;\n\t} udp;\n\tstruct {\n\t\t__be16 id;\n\t} icmp;\n\tstruct {\n\t\t__be16 port;\n\t} dccp;\n\tstruct {\n\t\t__be16 port;\n\t} sctp;\n\tstruct {\n\t\t__be16 key;\n\t} gre;\n};\n\nstruct nf_conntrack_man {\n\tunion nf_inet_addr u3;\n\tunion nf_conntrack_man_proto u;\n\tu_int16_t l3num;\n};\n\nstruct nf_conntrack_tuple {\n\tstruct nf_conntrack_man src;\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion {\n\t\t\t__be16 all;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} tcp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} udp;\n\t\t\tstruct {\n\t\t\t\tu_int8_t type;\n\t\t\t\tu_int8_t code;\n\t\t\t} icmp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} dccp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} sctp;\n\t\t\tstruct {\n\t\t\t\t__be16 key;\n\t\t\t} gre;\n\t\t} u;\n\t\tu_int8_t protonum;\n\t\tstruct {} __nfct_hash_offsetend;\n\t\tu_int8_t dir;\n\t} dst;\n};\n\nstruct nf_conntrack_tuple_hash {\n\tstruct hlist_nulls_node hnnode;\n\tstruct nf_conntrack_tuple tuple;\n};\n\nstruct nf_ct_udp {\n\tlong unsigned int stream_ts;\n};\n\nstruct nf_ct_gre {\n\tunsigned int stream_timeout;\n\tunsigned int timeout;\n};\n\nunion nf_conntrack_proto {\n\tstruct ip_ct_sctp sctp;\n\tstruct ip_ct_tcp tcp;\n\tstruct nf_ct_udp udp;\n\tstruct nf_ct_gre gre;\n\tunsigned int tmpl_padto;\n};\n\nstruct nf_ct_ext;\n\nstruct nf_conn {\n\tstruct nf_conntrack ct_general;\n\tspinlock_t lock;\n\tu32 timeout;\n\tstruct nf_conntrack_tuple_hash tuplehash[2];\n\tlong unsigned int status;\n\tpossible_net_t ct_net;\n\tstruct {} __nfct_init_offset;\n\tstruct nf_conn *master;\n\tstruct nf_ct_ext *ext;\n\tunion nf_conntrack_proto proto;\n};\n\nstruct nf_conn___init {\n\tstruct nf_conn ct;\n};\n\nstruct nf_conn_labels {\n\tlong unsigned int bits[2];\n};\n\nstruct nf_conntrack_tuple_mask {\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion nf_conntrack_man_proto u;\n\t} src;\n};\n\nstruct nf_conntrack_helper;\n\nstruct nf_conntrack_expect {\n\tstruct hlist_node lnode;\n\tstruct hlist_node hnode;\n\tstruct nf_conntrack_tuple tuple;\n\tstruct nf_conntrack_tuple_mask mask;\n\trefcount_t use;\n\tunsigned int flags;\n\tunsigned int class;\n\tvoid (*expectfn)(struct nf_conn *, struct nf_conntrack_expect *);\n\tstruct nf_conntrack_helper *helper;\n\tstruct nf_conn *master;\n\tstruct timer_list timeout;\n\tstruct callback_head rcu;\n};\n\nstruct nf_conntrack_zone {\n\tu16 id;\n\tu8 flags;\n\tu8 dir;\n};\n\nstruct nf_ct_event {\n\tstruct nf_conn *ct;\n\tu32 portid;\n\tint report;\n};\n\nstruct nf_exp_event;\n\nstruct nf_ct_event_notifier {\n\tint (*ct_event)(unsigned int, const struct nf_ct_event *);\n\tint (*exp_event)(unsigned int, const struct nf_exp_event *);\n};\n\nstruct nf_ct_ext {\n\tu8 offset[4];\n\tu8 len;\n\tunsigned int gen_id;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct nf_ct_hook {\n\tint (*update)(struct net *, struct sk_buff *);\n\tvoid (*destroy)(struct nf_conntrack *);\n\tbool (*get_tuple_skb)(struct nf_conntrack_tuple *, const struct sk_buff *);\n\tvoid (*attach)(struct sk_buff *, const struct sk_buff *);\n\tvoid (*set_closing)(struct nf_conntrack *);\n\tint (*confirm)(struct sk_buff *);\n\tu32 (*get_id)(const struct nf_conntrack *);\n};\n\nstruct nf_defrag_hook {\n\tstruct module *owner;\n\tint (*enable)(struct net *);\n\tvoid (*disable)(struct net *);\n};\n\nstruct nf_exp_event {\n\tstruct nf_conntrack_expect *exp;\n\tu32 portid;\n\tint report;\n};\n\nstruct nf_hook_entry {\n\tnf_hookfn *hook;\n\tvoid *priv;\n};\n\nstruct nf_hook_entries {\n\tu16 num_hook_entries;\n\tstruct nf_hook_entry hooks[0];\n};\n\nstruct nf_hook_entries_rcu_head {\n\tstruct callback_head head;\n\tvoid *allocation;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nf_bridge_frag_data;\n\nstruct nf_queue_entry;\n\nstruct nf_ipv6_ops {\n\tint (*chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n\tint (*route_me_harder)(struct net *, struct sock *, struct sk_buff *);\n\tint (*dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n\tint (*route)(struct net *, struct dst_entry **, struct flowi *, bool);\n\tu32 (*cookie_init_sequence)(const struct ipv6hdr *, const struct tcphdr *, u16 *);\n\tint (*cookie_v6_check)(const struct ipv6hdr *, const struct tcphdr *);\n\tvoid (*route_input)(struct sk_buff *);\n\tint (*fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tint (*reroute)(struct sk_buff *, const struct nf_queue_entry *);\n\tint (*br_fragment)(struct net *, struct sock *, struct sk_buff *, struct nf_bridge_frag_data *, int (*)(struct net *, struct sock *, const struct nf_bridge_frag_data *, struct sk_buff *));\n};\n\nstruct nf_log_buf {\n\tunsigned int count;\n\tchar buf[1020];\n};\n\nstruct nf_loginfo;\n\ntypedef void nf_logfn(struct net *, u_int8_t, unsigned int, const struct sk_buff *, const struct net_device *, const struct net_device *, const struct nf_loginfo *, const char *);\n\nstruct nf_logger {\n\tchar *name;\n\tenum nf_log_type type;\n\tnf_logfn *logfn;\n\tstruct module *me;\n};\n\nstruct nf_loginfo {\n\tu_int8_t type;\n\tunion {\n\t\tstruct {\n\t\t\tu_int32_t copy_len;\n\t\t\tu_int16_t group;\n\t\t\tu_int16_t qthreshold;\n\t\t\tu_int16_t flags;\n\t\t} ulog;\n\t\tstruct {\n\t\t\tu_int8_t level;\n\t\t\tu_int8_t logflags;\n\t\t} log;\n\t} u;\n};\n\nstruct nf_nat_hook {\n\tint (*parse_nat_setup)(struct nf_conn *, enum nf_nat_manip_type, const struct nlattr *);\n\tvoid (*decode_session)(struct sk_buff *, struct flowi *);\n\tvoid (*remove_nat_bysrc)(struct nf_conn *);\n};\n\nstruct nf_queue_entry {\n\tstruct list_head list;\n\tstruct rhash_head hash_node;\n\tstruct sk_buff *skb;\n\tunsigned int id;\n\tunsigned int hook_index;\n\tstruct net_device *physin;\n\tstruct net_device *physout;\n\tstruct nf_hook_state state;\n\tbool nf_ct_is_unconfirmed;\n\tu16 size;\n\tu16 queue_num;\n};\n\nstruct nf_queue_handler {\n\tint (*outfn)(struct nf_queue_entry *, unsigned int);\n\tvoid (*nf_hook_drop)(struct net *);\n};\n\nstruct nf_sockopt_ops {\n\tstruct list_head list;\n\tu_int8_t pf;\n\tint set_optmin;\n\tint set_optmax;\n\tint (*set)(struct sock *, int, sockptr_t, unsigned int);\n\tint get_optmin;\n\tint get_optmax;\n\tint (*get)(struct sock *, int, void *, int *);\n\tstruct module *owner;\n};\n\nstruct nfnl_ct_hook {\n\tsize_t (*build_size)(const struct nf_conn *);\n\tint (*build)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, u_int16_t, u_int16_t);\n\tint (*parse)(const struct nlattr *, struct nf_conn *);\n\tint (*attach_expect)(const struct nlattr *, struct nf_conn *, u32, u32);\n\tvoid (*seq_adjust)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, s32);\n};\n\nstruct nfs2_fh {\n\tchar data[32];\n};\n\nstruct nfs3_accessargs {\n\tstruct nfs_fh *fh;\n\t__u32 access;\n};\n\nstruct nfs_fattr;\n\nstruct nfs3_accessres {\n\tstruct nfs_fattr *fattr;\n\t__u32 access;\n};\n\nstruct nfs3_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n\tenum nfs3_createmode createmode;\n\t__be32 verifier[2];\n};\n\nstruct rpc_procinfo;\n\nstruct rpc_message {\n\tconst struct rpc_procinfo *rpc_proc;\n\tvoid *rpc_argp;\n\tvoid *rpc_resp;\n\tconst struct cred *rpc_cred;\n};\n\nstruct nfs3_mkdirargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_mknodargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tenum nfs3_ftype type;\n\tstruct iattr *sattr;\n\tdev_t rdev;\n};\n\nstruct nfs3_diropres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs4_string;\n\nstruct nfs4_threshold;\n\nstruct nfs4_label;\n\nstruct nfs_fattr {\n\t__u64 valid;\n\tumode_t mode;\n\t__u32 nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\t__u64 size;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 blocksize;\n\t\t\t__u32 blocks;\n\t\t} nfs2;\n\t\tstruct {\n\t\t\t__u64 used;\n\t\t} nfs3;\n\t} du;\n\tstruct nfs_fsid fsid;\n\t__u64 fileid;\n\t__u64 mounted_on_fileid;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\t__u64 change_attr;\n\t__u64 pre_change_attr;\n\t__u64 pre_size;\n\tstruct timespec64 pre_mtime;\n\tstruct timespec64 pre_ctime;\n\tlong unsigned int time_start;\n\tlong unsigned int gencount;\n\tstruct nfs4_string *owner_name;\n\tstruct nfs4_string *group_name;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs3_createdata {\n\tstruct rpc_message msg;\n\tunion {\n\t\tstruct nfs3_createargs create;\n\t\tstruct nfs3_mkdirargs mkdir;\n\t\tstruct nfs3_symlinkargs symlink;\n\t\tstruct nfs3_mknodargs mknod;\n\t} arg;\n\tstruct nfs3_diropres res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_fattr dir_attr;\n};\n\nstruct nfs3_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs3_fh {\n\tshort unsigned int size;\n\tunsigned char data[64];\n};\n\nstruct nfs3_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs3_linkres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_readdirargs {\n\tstruct nfs_fh *fh;\n\t__u64 cookie;\n\t__be32 verf[2];\n\tbool plus;\n\tunsigned int count;\n\tstruct page **pages;\n};\n\nstruct nfs3_readdirres {\n\tstruct nfs_fattr *dir_attr;\n\t__be32 *verf;\n\tbool plus;\n};\n\nstruct nfs3_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs3_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n\tunsigned int guard;\n\tstruct timespec64 guardtime;\n};\n\nstruct nfs41_bind_conn_to_session_args {\n\tstruct nfs_client *client;\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n\tint retries;\n};\n\nstruct nfs41_bind_conn_to_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n};\n\nstruct nfs4_channel_attrs {\n\tu32 max_rqst_sz;\n\tu32 max_resp_sz;\n\tu32 max_resp_sz_cached;\n\tu32 max_ops;\n\tu32 max_reqs;\n};\n\nstruct nfs41_create_session_args {\n\tstruct nfs_client *client;\n\tu64 clientid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tuint32_t cb_program;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs41_create_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs4_op_map {\n\tunion {\n\t\tlong unsigned int longs[2];\n\t\tu32 words[4];\n\t} u;\n};\n\nstruct nfs41_state_protection {\n\tu32 how;\n\tstruct nfs4_op_map enforce;\n\tstruct nfs4_op_map allow;\n};\n\nstruct nfs41_exchange_id_args {\n\tstruct nfs_client *client;\n\tnfs4_verifier verifier;\n\tu32 flags;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_server_owner;\n\nstruct nfs41_server_scope;\n\nstruct nfs41_impl_id;\n\nstruct nfs41_exchange_id_res {\n\tu64 clientid;\n\tu32 seqid;\n\tu32 flags;\n\tstruct nfs41_server_owner *server_owner;\n\tstruct nfs41_server_scope *server_scope;\n\tstruct nfs41_impl_id *impl_id;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_exchange_id_data {\n\tstruct nfs41_exchange_id_res res;\n\tstruct nfs41_exchange_id_args args;\n};\n\nstruct nfs4_sequence_args {\n\tstruct nfs4_slot *sa_slot;\n\tu8 sa_cache_this: 1;\n\tu8 sa_privileged: 1;\n};\n\nstruct nfs41_free_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_sequence_slot_ops;\n\nstruct nfs4_sequence_res {\n\tconst struct nfs4_sequence_slot_ops *sr_slot_ops;\n\tstruct nfs4_slot *sr_slot;\n\tlong unsigned int sr_timestamp;\n\tint sr_status;\n\tu32 sr_status_flags;\n\tu32 sr_highest_slotid;\n\tu32 sr_target_highest_slotid;\n};\n\nstruct nfs41_free_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfstime4 {\n\tint64_t seconds;\n\tuint32_t nseconds;\n};\n\nstruct nfs41_impl_id {\n\tchar domain[1025];\n\tchar name[1025];\n\tstruct nfstime4 date;\n};\n\nstruct nfs41_reclaim_complete_args {\n\tstruct nfs4_sequence_args seq_args;\n\tunsigned char one_fs: 1;\n};\n\nstruct nfs41_reclaim_complete_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs41_secinfo_no_name_args {\n\tstruct nfs4_sequence_args seq_args;\n\tint style;\n};\n\nstruct nfs41_server_owner {\n\tuint64_t minor_id;\n\tuint32_t major_id_sz;\n\tchar major_id[1024];\n};\n\nstruct nfs41_server_scope {\n\tuint32_t server_scope_sz;\n\tchar server_scope[1024];\n};\n\nstruct nfs41_test_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs41_test_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfs42_clone_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid src_stateid;\n\tnfs4_stateid dst_stateid;\n\t__u64 src_offset;\n\t__u64 dst_offset;\n\t__u64 count;\n\tconst u32 *dst_bitmask;\n};\n\nstruct nfs_server;\n\nstruct nfs42_clone_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int rpc_status;\n\tstruct nfs_fattr *dst_fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nl4_server;\n\nstruct nfs42_copy_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *src_fh;\n\tnfs4_stateid src_stateid;\n\tu64 src_pos;\n\tstruct nfs_fh *dst_fh;\n\tnfs4_stateid dst_stateid;\n\tu64 dst_pos;\n\tu64 count;\n\tbool sync;\n\tstruct nl4_server *cp_src;\n};\n\nstruct nfs42_netaddr {\n\tchar netid[5];\n\tchar addr[58];\n\tu32 netid_len;\n\tu32 addr_len;\n};\n\nstruct nl4_server {\n\tenum netloc_type4 nl4_type;\n\tunion {\n\t\tstruct {\n\t\t\tint nl4_str_sz;\n\t\t\tchar nl4_str[1025];\n\t\t};\n\t\tstruct nfs42_netaddr nl4_addr;\n\t} u;\n};\n\nstruct nfs42_copy_notify_args {\n\tstruct nfs4_sequence_args cna_seq_args;\n\tstruct nfs_fh *cna_src_fh;\n\tnfs4_stateid cna_src_stateid;\n\tstruct nl4_server cna_dst;\n};\n\nstruct nfs42_copy_notify_res {\n\tstruct nfs4_sequence_res cnr_seq_res;\n\tstruct nfstime4 cnr_lease_time;\n\tnfs4_stateid cnr_stateid;\n\tstruct nl4_server cnr_src;\n};\n\nstruct nfs42_write_res {\n\tnfs4_stateid stateid;\n\tu64 count;\n\tstruct nfs_writeverf verifier;\n};\n\nstruct nfs_commitres {\n\tstruct nfs4_sequence_res seq_res;\n\t__u32 op_status;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_writeverf *verf;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs42_copy_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs42_write_res write_res;\n\tbool consecutive;\n\tbool synchronous;\n\tstruct nfs_commitres commit_res;\n};\n\nstruct nfs42_device_error {\n\tstruct nfs4_deviceid dev_id;\n\tint status;\n\tenum nfs_opnum4 opnum;\n};\n\nstruct nfs42_falloc_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *falloc_fh;\n\tnfs4_stateid falloc_stateid;\n\tu64 falloc_offset;\n\tu64 falloc_length;\n\tconst u32 *falloc_bitmask;\n};\n\nstruct nfs42_falloc_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tstruct nfs_fattr *falloc_fattr;\n\tconst struct nfs_server *falloc_server;\n};\n\nstruct nfs42_getxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_getxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tsize_t xattr_len;\n};\n\nstruct nfs42_layout_error {\n\t__u64 offset;\n\t__u64 length;\n\tnfs4_stateid stateid;\n\tstruct nfs42_device_error errors[1];\n};\n\nstruct nfs42_layouterror_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct inode *inode;\n\tunsigned int num_errors;\n\tstruct nfs42_layout_error errors[5];\n};\n\nstruct nfs42_layouterror_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int num_errors;\n\tint rpc_status;\n};\n\nstruct pnfs_layout_segment;\n\nstruct nfs42_layouterror_data {\n\tstruct nfs42_layouterror_args args;\n\tstruct nfs42_layouterror_res res;\n\tstruct inode *inode;\n\tstruct pnfs_layout_segment *lseg;\n};\n\nstruct nfs42_layoutstat_devinfo;\n\nstruct nfs42_layoutstat_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tint num_dev;\n\tstruct nfs42_layoutstat_devinfo *devinfo;\n};\n\nstruct nfs42_layoutstat_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint num_dev;\n\tint rpc_status;\n};\n\nstruct nfs42_layoutstat_data {\n\tstruct inode *inode;\n\tstruct nfs42_layoutstat_args args;\n\tstruct nfs42_layoutstat_res res;\n};\n\nstruct nfs4_xdr_opaque_ops;\n\nstruct nfs4_xdr_opaque_data {\n\tconst struct nfs4_xdr_opaque_ops *ops;\n\tvoid *data;\n};\n\nstruct nfs42_layoutstat_devinfo {\n\tstruct nfs4_deviceid dev_id;\n\t__u64 offset;\n\t__u64 length;\n\t__u64 read_count;\n\t__u64 read_bytes;\n\t__u64 write_count;\n\t__u64 write_bytes;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs42_listxattrsargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tu32 count;\n\tu64 cookie;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_listxattrsres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct folio *scratch;\n\tvoid *xattr_buf;\n\tsize_t xattr_len;\n\tu64 cookie;\n\tbool eof;\n\tsize_t copied;\n};\n\nstruct nfs42_offload_status_args {\n\tstruct nfs4_sequence_args osa_seq_args;\n\tstruct nfs_fh *osa_src_fh;\n\tnfs4_stateid osa_stateid;\n};\n\nstruct nfs42_offload_status_res {\n\tstruct nfs4_sequence_res osr_seq_res;\n\tu64 osr_count;\n\tint complete_count;\n\tu32 osr_complete;\n};\n\nstruct nfs42_offload_data {\n\tstruct nfs_server *seq_server;\n\tstruct nfs42_offload_status_args args;\n\tstruct nfs42_offload_status_res res;\n};\n\nstruct nfs42_removexattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst char *xattr_name;\n};\n\nstruct nfs4_change_info {\n\tu32 atomic;\n\tu64 before;\n\tu64 after;\n};\n\nstruct nfs42_removexattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs42_seek_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *sa_fh;\n\tnfs4_stateid sa_stateid;\n\tu64 sa_offset;\n\tu32 sa_what;\n};\n\nstruct nfs42_seek_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n\tu32 sr_eof;\n\tu64 sr_offset;\n};\n\nstruct nfs42_setxattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tconst char *xattr_name;\n\tu32 xattr_flags;\n\tsize_t xattr_len;\n\tstruct page **xattr_pages;\n};\n\nstruct nfs42_setxattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs4_accessargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tu32 access;\n};\n\nstruct nfs4_accessres {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tu32 supported;\n\tu32 access;\n};\n\nstruct nfs4_add_xprt_data {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct nfs4_cached_acl {\n\tenum nfs4_acl_type type;\n\tint cached;\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct nfs4_call_sync_data {\n\tconst struct nfs_server *seq_server;\n\tstruct nfs4_sequence_args *seq_args;\n\tstruct nfs4_sequence_res *seq_res;\n};\n\nstruct nfs_seqid;\n\nstruct nfs4_layoutreturn_args;\n\nstruct nfs_closeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n\tfmode_t fmode;\n\tu32 share_access;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs4_layoutreturn_res;\n\nstruct nfs_closeres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct pnfs_layout_hdr;\n\nstruct nfs4_layoutreturn_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_layout_hdr *layout;\n\tstruct inode *inode;\n\tstruct pnfs_layout_range range;\n\tnfs4_stateid stateid;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data *ld_private;\n};\n\nstruct nfs4_layoutreturn_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 lrs_present;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_state;\n\nstruct nfs4_closedata {\n\tstruct inode *inode;\n\tstruct nfs4_state *state;\n\tstruct nfs_closeargs arg;\n\tstruct nfs_closeres res;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_copy_state {\n\tstruct list_head copies;\n\tstruct list_head src_copies;\n\tnfs4_stateid stateid;\n\tstruct completion completion;\n\tuint64_t count;\n\tstruct nfs_writeverf verf;\n\tint error;\n\tint flags;\n\tstruct nfs4_state *parent_src_state;\n\tstruct nfs4_state *parent_dst_state;\n};\n\nstruct nfs4_create_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tu32 ftype;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page **pages;\n\t\t\tunsigned int len;\n\t\t} symlink;\n\t\tstruct {\n\t\t\tu32 specdata1;\n\t\t\tu32 specdata2;\n\t\t} device;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst struct iattr *attrs;\n\tconst struct nfs_fh *dir_fh;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n};\n\nstruct nfs4_create_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info dir_cinfo;\n};\n\nstruct nfs4_createdata {\n\tstruct rpc_message msg;\n\tstruct nfs4_create_arg arg;\n\tstruct nfs4_create_res res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n};\n\nstruct nfs4_delegattr {\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tbool atime_set;\n\tbool mtime_set;\n};\n\nstruct nfs4_delegreturnargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fhandle;\n\tconst nfs4_stateid *stateid;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n\tstruct nfs4_delegattr *sattr_args;\n};\n\nstruct nfs4_delegreturnres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n\tbool sattr_res;\n\tint sattr_ret;\n};\n\nstruct nfs4_delegreturndata {\n\tstruct nfs4_delegreturnargs args;\n\tstruct nfs4_delegreturnres res;\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs4_delegattr sattr;\n\tstruct nfs_fattr fattr;\n\tint rpc_status;\n\tstruct inode *inode;\n};\n\nstruct pnfs_layoutdriver_type;\n\nstruct nfs4_deviceid_node {\n\tstruct hlist_node node;\n\tstruct hlist_node tmpnode;\n\tconst struct pnfs_layoutdriver_type *ld;\n\tconst struct nfs_client *nfs_client;\n\tlong unsigned int flags;\n\tlong unsigned int timestamp_unavailable;\n\tstruct nfs4_deviceid deviceid;\n\tstruct callback_head rcu;\n\tatomic_t ref;\n};\n\nstruct nfs4_ds_server {\n\tstruct list_head list;\n\tstruct rpc_clnt *rpc_clnt;\n};\n\nstruct nfs4_exception {\n\tstruct nfs4_state *state;\n\tstruct inode *inode;\n\tnfs4_stateid *stateid;\n\tlong int timeout;\n\tshort unsigned int retrans;\n\tunsigned char task_is_privileged: 1;\n\tunsigned char delay: 1;\n\tunsigned char recovering: 1;\n\tunsigned char retry: 1;\n\tbool interruptible;\n};\n\nstruct nfs4_ff_busy_timer {\n\tktime_t start_time;\n\tatomic_t n_ops;\n};\n\nstruct nfs4_ff_ds_version {\n\tu32 version;\n\tu32 minor_version;\n\tu32 rsize;\n\tu32 wsize;\n\tbool tightly_coupled;\n};\n\nstruct nfs4_ff_io_stat {\n\t__u64 ops_requested;\n\t__u64 bytes_requested;\n\t__u64 ops_completed;\n\t__u64 bytes_completed;\n\t__u64 bytes_not_delivered;\n\tktime_t total_busy_time;\n\tktime_t aggregate_completion_time;\n};\n\nstruct nfs4_pnfs_ds;\n\nstruct nfs4_ff_layout_ds {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 ds_versions_cnt;\n\tstruct nfs4_ff_ds_version *ds_versions;\n\tstruct nfs4_pnfs_ds *ds;\n};\n\nstruct nfs4_ff_layout_ds_err {\n\tstruct list_head list;\n\tu64 offset;\n\tu64 length;\n\tint status;\n\tenum nfs_opnum4 opnum;\n\tnfs4_stateid stateid;\n\tstruct nfs4_deviceid deviceid;\n};\n\nstruct nfsd_file;\n\nstruct nfs_file_localio {\n\tstruct nfsd_file *ro_file;\n\tstruct nfsd_file *rw_file;\n\tstruct list_head list;\n\tvoid *nfs_uuid;\n};\n\nstruct nfs4_ff_layoutstat {\n\tstruct nfs4_ff_io_stat io_stat;\n\tstruct nfs4_ff_busy_timer busy_timer;\n};\n\nstruct nfs4_ff_layout_mirror;\n\nstruct nfs4_ff_layout_ds_stripe {\n\tstruct nfs4_ff_layout_mirror *mirror;\n\tstruct nfs4_deviceid devid;\n\tu32 efficiency;\n\tstruct nfs4_ff_layout_ds *mirror_ds;\n\tu32 fh_versions_cnt;\n\tstruct nfs_fh *fh_versions;\n\tnfs4_stateid stateid;\n\tconst struct cred *ro_cred;\n\tconst struct cred *rw_cred;\n\tstruct nfs_file_localio nfl;\n\tstruct nfs4_ff_layoutstat read_stat;\n\tstruct nfs4_ff_layoutstat write_stat;\n\tktime_t start_time;\n};\n\nstruct nfs4_ff_layout_mirror {\n\tstruct pnfs_layout_hdr *layout;\n\tstruct list_head mirrors;\n\tu32 dss_count;\n\tstruct nfs4_ff_layout_ds_stripe *dss;\n\trefcount_t ref;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu32 report_interval;\n};\n\nstruct pnfs_layout_segment {\n\tstruct list_head pls_list;\n\tstruct list_head pls_lc_list;\n\tstruct list_head pls_commits;\n\tstruct pnfs_layout_range pls_range;\n\trefcount_t pls_refcount;\n\tu32 pls_seq;\n\tlong unsigned int pls_flags;\n\tstruct pnfs_layout_hdr *pls_layout;\n};\n\nstruct nfs4_ff_layout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu64 stripe_unit;\n\tu32 flags;\n\tu32 mirror_array_cnt;\n\tstruct nfs4_ff_layout_mirror *mirror_array[0];\n};\n\nstruct nfs4_file_layout_dsaddr {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 stripe_count;\n\tu8 *stripe_indices;\n\tu32 ds_num;\n\tstruct nfs4_pnfs_ds *ds_list[0];\n};\n\nstruct pnfs_layout_hdr {\n\trefcount_t plh_refcount;\n\tatomic_t plh_outstanding;\n\tstruct list_head plh_layouts;\n\tstruct list_head plh_bulk_destroy;\n\tstruct list_head plh_segs;\n\tstruct list_head plh_return_segs;\n\tlong unsigned int plh_block_lgets;\n\tlong unsigned int plh_retry_timestamp;\n\tlong unsigned int plh_flags;\n\tnfs4_stateid plh_stateid;\n\tu32 plh_barrier;\n\tu32 plh_return_seq;\n\tenum pnfs_iomode plh_return_iomode;\n\tloff_t plh_lwb;\n\tconst struct cred *plh_lc_cred;\n\tstruct inode *plh_inode;\n\tstruct callback_head plh_rcu;\n};\n\nstruct pnfs_commit_ops;\n\nstruct pnfs_ds_commit_info {\n\tstruct list_head commits;\n\tunsigned int nwritten;\n\tunsigned int ncommitting;\n\tconst struct pnfs_commit_ops *ops;\n};\n\nstruct nfs4_filelayout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n};\n\nstruct nfs4_filelayout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu32 stripe_type;\n\tu32 commit_through_mds;\n\tu32 stripe_unit;\n\tu32 first_stripe_index;\n\tu64 pattern_offset;\n\tstruct nfs4_deviceid deviceid;\n\tstruct nfs4_file_layout_dsaddr *dsaddr;\n\tunsigned int num_fh;\n\tstruct nfs_fh **fh_array;\n};\n\nstruct nfs4_flexfile_layout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tstruct list_head mirrors;\n\tstruct list_head error_list;\n\tktime_t last_report_time;\n};\n\nstruct nfs4_flexfile_layoutreturn_args {\n\tstruct list_head errors;\n\tstruct nfs42_layoutstat_devinfo devinfo[4];\n\tunsigned int num_errors;\n\tunsigned int num_dev;\n\tstruct page *pages[1];\n};\n\nstruct nfs4_string {\n\tunsigned int len;\n\tchar *data;\n};\n\nstruct nfs4_pathname {\n\tunsigned int ncomponents;\n\tstruct nfs4_string components[512];\n};\n\nstruct nfs4_fs_location {\n\tunsigned int nservers;\n\tstruct nfs4_string servers[10];\n\tstruct nfs4_pathname rootpath;\n};\n\nstruct nfs4_fs_locations {\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tstruct nfs4_pathname fs_path;\n\tint nlocations;\n\tstruct nfs4_fs_location locations[10];\n};\n\nstruct nfs4_fs_locations_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct nfs_fh *fh;\n\tconst struct qstr *name;\n\tstruct page *page;\n\tconst u32 *bitmask;\n\tclientid4 clientid;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fs_locations_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_fs_locations *fs_locations;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tclientid4 clientid;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fh *fh;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsinfo;\n\nstruct nfs4_fsinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsinfo *fsinfo;\n};\n\nstruct nfs4_gdd_res {\n\tu32 status;\n\tnfs4_stateid deleg;\n};\n\nstruct nfs4_get_lease_time_args {\n\tstruct nfs4_sequence_args la_seq_args;\n};\n\nstruct nfs4_get_lease_time_res;\n\nstruct nfs4_get_lease_time_data {\n\tstruct nfs4_get_lease_time_args *args;\n\tstruct nfs4_get_lease_time_res *res;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_get_lease_time_res {\n\tstruct nfs4_sequence_res lr_seq_res;\n\tstruct nfs_fsinfo *lr_fsinfo;\n};\n\nstruct nfs4_getattr_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tbool get_dir_deleg;\n};\n\nstruct nfs4_getattr_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_gdd_res *gdd_res;\n};\n\nstruct pnfs_device;\n\nstruct nfs4_getdeviceinfo_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_device *pdev;\n\t__u32 notify_types;\n};\n\nstruct nfs4_getdeviceinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct pnfs_device *pdev;\n\t__u32 notification;\n};\n\nstruct nfs4_label {\n\tuint32_t lfs;\n\tuint32_t pi;\n\tu32 lsmid;\n\tu32 len;\n\tchar *label;\n};\n\nstruct nfs4_layoutcommit_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n\t__u64 lastbytewritten;\n\tstruct inode *inode;\n\tconst u32 *bitmask;\n\tsize_t layoutupdate_len;\n\tstruct page *layoutupdate_page;\n\tstruct page **layoutupdate_pages;\n\t__be32 *start_p;\n};\n\nstruct rpc_wait {\n\tstruct list_head list;\n\tstruct list_head links;\n\tstruct list_head timer_list;\n};\n\nstruct rpc_call_ops;\n\nstruct rpc_xprt;\n\nstruct rpc_rqst;\n\nstruct rpc_task {\n\tatomic_t tk_count;\n\tint tk_status;\n\tstruct list_head tk_task;\n\tvoid (*tk_callback)(struct rpc_task *);\n\tvoid (*tk_action)(struct rpc_task *);\n\tlong unsigned int tk_timeout;\n\tlong unsigned int tk_runstate;\n\tstruct rpc_wait_queue *tk_waitqueue;\n\tunion {\n\t\tstruct work_struct tk_work;\n\t\tstruct rpc_wait tk_wait;\n\t} u;\n\tstruct rpc_message tk_msg;\n\tvoid *tk_calldata;\n\tconst struct rpc_call_ops *tk_ops;\n\tstruct rpc_clnt *tk_client;\n\tstruct rpc_xprt *tk_xprt;\n\tstruct rpc_cred *tk_op_cred;\n\tstruct rpc_rqst *tk_rqstp;\n\tstruct workqueue_struct *tk_workqueue;\n\tktime_t tk_start;\n\tpid_t tk_owner;\n\tint tk_rpc_status;\n\tshort unsigned int tk_flags;\n\tshort unsigned int tk_timeouts;\n\tshort unsigned int tk_pid;\n\tunsigned char tk_priority: 2;\n\tunsigned char tk_garb_retry: 2;\n\tunsigned char tk_cred_retry: 2;\n};\n\nstruct nfs4_layoutcommit_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tint status;\n};\n\nstruct nfs4_layoutcommit_data {\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct list_head lseg_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tstruct nfs4_layoutcommit_args args;\n\tstruct nfs4_layoutcommit_res res;\n};\n\nstruct nfs4_layoutdriver_data {\n\tstruct page **pages;\n\t__u32 pglen;\n\t__u32 len;\n};\n\nstruct nfs_open_context;\n\nstruct nfs4_layoutget_args {\n\tstruct nfs4_sequence_args seq_args;\n\t__u32 type;\n\tstruct pnfs_layout_range range;\n\t__u64 minlength;\n\t__u32 maxcount;\n\tstruct inode *inode;\n\tstruct nfs_open_context *ctx;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data layout;\n};\n\nstruct nfs4_layoutget_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint status;\n\t__u32 return_on_close;\n\tstruct pnfs_layout_range range;\n\t__u32 type;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data *layoutp;\n};\n\nstruct nfs4_layoutget {\n\tstruct nfs4_layoutget_args args;\n\tstruct nfs4_layoutget_res res;\n\tconst struct cred *cred;\n\tstruct pnfs_layout_hdr *lo;\n\tgfp_t gfp_flags;\n};\n\nstruct nfs4_layoutreturn {\n\tstruct nfs4_layoutreturn_args args;\n\tstruct nfs4_layoutreturn_res res;\n\tconst struct cred *cred;\n\tstruct nfs_client *clp;\n\tstruct inode *inode;\n\tint rpc_status;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs4_link_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_link_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *dir_attr;\n};\n\nstruct nfs_seqid_counter {\n\tktime_t create_time;\n\tu64 owner_id;\n\tint flags;\n\tu32 counter;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct rpc_wait_queue wait;\n};\n\nstruct nfs4_lock_state {\n\tstruct list_head ls_locks;\n\tstruct nfs4_state *ls_state;\n\tlong unsigned int ls_flags;\n\tstruct nfs_seqid_counter ls_seqid;\n\tnfs4_stateid ls_stateid;\n\trefcount_t ls_count;\n\tfl_owner_t ls_owner;\n};\n\nstruct nfs4_lock_waiter {\n\tstruct inode *inode;\n\tstruct nfs_lowner owner;\n\twait_queue_entry_t wait;\n};\n\nstruct nfs_lock_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *lock_seqid;\n\tnfs4_stateid lock_stateid;\n\tstruct nfs_seqid *open_seqid;\n\tnfs4_stateid open_stateid;\n\tstruct nfs_lowner lock_owner;\n\tunsigned char block: 1;\n\tunsigned char reclaim: 1;\n\tunsigned char new_lock: 1;\n\tunsigned char new_lock_owner: 1;\n};\n\nstruct nfs_lock_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *lock_seqid;\n\tstruct nfs_seqid *open_seqid;\n};\n\nstruct nfs4_lockdata {\n\tstruct nfs_lock_args arg;\n\tstruct nfs_lock_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct file_lock fl;\n\tlong unsigned int timestamp;\n\tint rpc_status;\n\tint cancelled;\n\tstruct nfs_server *server;\n};\n\nstruct nfs4_lookup_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookup_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_lookup_root_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_mig_recovery_ops {\n\tint (*get_locations)(struct nfs_server *, struct nfs_fh *, struct nfs4_fs_locations *, struct page *, const struct cred *);\n\tint (*fsid_present)(struct inode *, const struct cred *);\n};\n\nstruct nfs4_state_recovery_ops;\n\nstruct nfs4_state_maintenance_ops;\n\nstruct nfs4_minor_version_ops {\n\tu32 minor_version;\n\tunsigned int init_caps;\n\tint (*init_client)(struct nfs_client *);\n\tvoid (*shutdown_client)(struct nfs_client *);\n\tbool (*match_stateid)(const nfs4_stateid *, const nfs4_stateid *);\n\tint (*find_root_sec)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *);\n\tvoid (*free_lock_state)(struct nfs_server *, struct nfs4_lock_state *);\n\tint (*test_and_free_expired)(struct nfs_server *, nfs4_stateid *, const struct cred *);\n\tstruct nfs_seqid * (*alloc_seqid)(struct nfs_seqid_counter *, gfp_t);\n\tvoid (*session_trunk)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tconst struct rpc_call_ops *call_sync_ops;\n\tconst struct nfs4_sequence_slot_ops *sequence_slot_ops;\n\tconst struct nfs4_state_recovery_ops *reboot_recovery_ops;\n\tconst struct nfs4_state_recovery_ops *nograce_recovery_ops;\n\tconst struct nfs4_state_maintenance_ops *state_renewal_ops;\n\tconst struct nfs4_mig_recovery_ops *mig_recovery_ops;\n};\n\nstruct nfs_string {\n\tunsigned int len;\n\tconst char *data;\n};\n\nstruct nfs4_mount_data {\n\tint version;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct nfs_string client_addr;\n\tstruct nfs_string mnt_path;\n\tstruct nfs_string hostname;\n\tunsigned int host_addrlen;\n\tstruct sockaddr *host_addr;\n\tint proto;\n\tint auth_flavourlen;\n\tint *auth_flavours;\n};\n\nstruct nfs4_open_caps {\n\tu32 oa_share_access[1];\n\tu32 oa_share_deny[1];\n\tu32 oa_share_access_want[1];\n\tu32 oa_open_claim[1];\n\tu32 oa_createmode[1];\n};\n\nstruct nfs4_open_createattrs {\n\tstruct nfs4_label *label;\n\tstruct iattr *sattr;\n\tconst __u32 verf[2];\n};\n\nstruct nfs4_open_delegation {\n\t__u32 open_delegation_type;\n\tunion {\n\t\tstruct {\n\t\t\tfmode_t type;\n\t\t\t__u32 do_recall;\n\t\t\tnfs4_stateid stateid;\n\t\t\tlong unsigned int pagemod_limit;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 why_no_delegation;\n\t\t\t__u32 will_notify;\n\t\t};\n\t};\n};\n\nstruct stateowner_id {\n\t__u64 create_time;\n\t__u64 uniquifier;\n};\n\nstruct nfs_openargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct nfs_seqid *seqid;\n\tint open_flags;\n\tfmode_t fmode;\n\tu32 share_access;\n\tu32 access;\n\t__u64 clientid;\n\tstruct stateowner_id id;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iattr *attrs;\n\t\t\tnfs4_verifier verifier;\n\t\t};\n\t\tnfs4_stateid delegation;\n\t\t__u32 delegation_type;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst u32 *open_bitmap;\n\tenum open_claim_type4 claim;\n\tenum createmode4 createmode;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n\tstruct nfs4_layoutget_args *lg_args;\n};\n\nstruct nfs_openres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fh fh;\n\tstruct nfs4_change_info cinfo;\n\t__u32 rflags;\n\tstruct nfs_fattr *f_attr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\t__u32 attrset[3];\n\tstruct nfs4_string *owner;\n\tstruct nfs4_string *group_owner;\n\tstruct nfs4_open_delegation delegation;\n\t__u32 access_request;\n\t__u32 access_supported;\n\t__u32 access_result;\n\tstruct nfs4_layoutget_res *lg_res;\n};\n\nstruct nfs_open_confirmargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tnfs4_stateid *stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_open_confirmres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs4_state_owner;\n\nstruct nfs4_opendata {\n\tstruct kref kref;\n\tstruct nfs_openargs o_arg;\n\tstruct nfs_openres o_res;\n\tstruct nfs_open_confirmargs c_arg;\n\tstruct nfs_open_confirmres c_res;\n\tstruct nfs4_string owner_name;\n\tstruct nfs4_string group_name;\n\tstruct nfs4_label *a_label;\n\tstruct nfs_fattr f_attr;\n\tstruct dentry *dir;\n\tstruct dentry *dentry;\n\tstruct nfs4_state_owner *owner;\n\tstruct nfs4_state *state;\n\tstruct iattr attrs;\n\tstruct nfs4_layoutget *lgp;\n\tlong unsigned int timestamp;\n\tbool rpc_done;\n\tbool file_created;\n\tbool is_recover;\n\tbool cancelled;\n\tint rpc_status;\n};\n\nstruct nfs4_pathconf_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_pathconf;\n\nstruct nfs4_pathconf_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_pathconf *pathconf;\n};\n\nstruct nfs4_pnfs_ds {\n\tstruct list_head ds_node;\n\tchar *ds_remotestr;\n\tstruct list_head ds_addrs;\n\tconst struct net *ds_net;\n\tstruct nfs_client *ds_clp;\n\trefcount_t ds_count;\n\tlong unsigned int ds_state;\n};\n\nstruct nfs4_pnfs_ds_addr {\n\tstruct __kernel_sockaddr_storage da_addr;\n\tsize_t da_addrlen;\n\tstruct list_head da_node;\n\tchar *da_remotestr;\n\tconst char *da_netid;\n\tint da_transport;\n};\n\nstruct nfs4_readdir_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tu64 cookie;\n\tnfs4_verifier verifier;\n\tu32 count;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tconst u32 *bitmask;\n\tbool plus;\n};\n\nstruct nfs4_readdir_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_verifier verifier;\n\tunsigned int pgbase;\n};\n\nstruct nfs4_readlink {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs4_readlink_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_reclaim_complete_data {\n\tstruct nfs_client *clp;\n\tstruct nfs41_reclaim_complete_args arg;\n\tstruct nfs41_reclaim_complete_res res;\n};\n\nstruct rpcsec_gss_info {\n\tstruct rpcsec_gss_oid oid;\n\tu32 qop;\n\tu32 service;\n};\n\nstruct nfs4_secinfo4 {\n\tu32 flavor;\n\tstruct rpcsec_gss_info flavor_info;\n};\n\nstruct nfs4_secinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n};\n\nstruct nfs4_secinfo_flavors {\n\tunsigned int num_flavors;\n\tstruct nfs4_secinfo4 flavors[0];\n};\n\nstruct nfs4_secinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_secinfo_flavors *flavors;\n};\n\nstruct nfs4_sequence_data {\n\tstruct nfs_client *clp;\n\tstruct nfs4_sequence_args args;\n\tstruct nfs4_sequence_res res;\n};\n\nstruct nfs4_sequence_slot_ops {\n\tint (*process)(struct rpc_task *, struct nfs4_sequence_res *);\n\tint (*done)(struct rpc_task *, struct nfs4_sequence_res *);\n\tvoid (*free_slot)(struct nfs4_sequence_res *);\n};\n\nstruct nfs4_server_caps_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fhandle;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_server_caps_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 attr_bitmask[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 has_links;\n\tu32 has_symlinks;\n\tu32 fh_expire_type;\n\tu32 case_insensitive;\n\tu32 case_preserving;\n\tstruct nfs4_open_caps open_caps;\n};\n\nstruct nfs4_session;\n\nstruct nfs4_slot_table {\n\tstruct nfs4_session *session;\n\tstruct nfs4_slot *slots;\n\tlong unsigned int used_slots[16];\n\tspinlock_t slot_tbl_lock;\n\tstruct rpc_wait_queue slot_tbl_waitq;\n\twait_queue_head_t slot_waitq;\n\tu32 max_slots;\n\tu32 max_slotid;\n\tu32 highest_used_slotid;\n\tu32 target_highest_slotid;\n\tu32 server_highest_slotid;\n\ts32 d_target_highest_slotid;\n\ts32 d2_target_highest_slotid;\n\tlong unsigned int generation;\n\tstruct completion complete;\n\tlong unsigned int slot_tbl_state;\n};\n\nstruct nfs4_session {\n\tstruct nfs4_sessionid sess_id;\n\tu32 flags;\n\tlong unsigned int session_state;\n\tu32 hash_alg;\n\tu32 ssv_len;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_slot_table fc_slot_table;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tstruct nfs4_slot_table bc_slot_table;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_setclientid {\n\tconst nfs4_verifier *sc_verifier;\n\tu32 sc_prog;\n\tunsigned int sc_netid_len;\n\tchar sc_netid[6];\n\tunsigned int sc_uaddr_len;\n\tchar sc_uaddr[58];\n\tstruct nfs_client *sc_clnt;\n\tstruct rpc_cred *sc_cred;\n};\n\nstruct nfs4_setclientid_res {\n\tu64 clientid;\n\tnfs4_verifier confirm;\n};\n\nstruct nfs4_slot {\n\tstruct nfs4_slot_table *table;\n\tstruct nfs4_slot *next;\n\tlong unsigned int generation;\n\tu32 slot_nr;\n\tu32 seq_nr;\n\tu32 seq_nr_last_acked;\n\tu32 seq_nr_highest_sent;\n\tunsigned int privileged: 1;\n\tunsigned int seq_done: 1;\n};\n\nstruct nfs4_ssc_client_ops {\n\tstruct file * (*sco_open)(struct vfsmount *, struct nfs_fh *, nfs4_stateid *);\n\tvoid (*sco_close)(struct file *);\n};\n\nstruct nfs4_state {\n\tstruct list_head open_states;\n\tstruct list_head inode_states;\n\tstruct list_head lock_states;\n\tstruct nfs4_state_owner *owner;\n\tstruct inode *inode;\n\tlong unsigned int flags;\n\tspinlock_t state_lock;\n\tseqlock_t seqlock;\n\tnfs4_stateid stateid;\n\tnfs4_stateid open_stateid;\n\tunsigned int n_rdonly;\n\tunsigned int n_wronly;\n\tunsigned int n_rdwr;\n\tfmode_t state;\n\trefcount_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs4_state_maintenance_ops {\n\tint (*sched_state_renewal)(struct nfs_client *, const struct cred *, unsigned int);\n\tconst struct cred * (*get_state_renewal_cred)(struct nfs_client *);\n\tint (*renew_lease)(struct nfs_client *, const struct cred *);\n};\n\nstruct nfs4_state_owner {\n\tstruct nfs_server *so_server;\n\tstruct list_head so_lru;\n\tlong unsigned int so_expires;\n\tstruct rb_node so_server_node;\n\tconst struct cred *so_cred;\n\tspinlock_t so_lock;\n\tatomic_t so_count;\n\tlong unsigned int so_flags;\n\tstruct list_head so_states;\n\tstruct nfs_seqid_counter so_seqid;\n\tstruct mutex so_delegreturn_mutex;\n};\n\nstruct nfs4_state_recovery_ops {\n\tint owner_flag_bit;\n\tint state_flag_bit;\n\tint (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);\n\tint (*recover_lock)(struct nfs4_state *, struct file_lock *);\n\tint (*establish_clid)(struct nfs_client *, const struct cred *);\n\tint (*reclaim_complete)(struct nfs_client *, const struct cred *);\n\tint (*detect_trunking)(struct nfs_client *, struct nfs_client **, const struct cred *);\n};\n\nstruct nfs4_statfs_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsstat;\n\nstruct nfs4_statfs_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsstat *fsstat;\n};\n\nstruct nfs4_threshold {\n\t__u32 bm;\n\t__u32 l_type;\n\t__u64 rd_sz;\n\t__u64 wr_sz;\n\t__u64 rd_io_sz;\n\t__u64 wr_io_sz;\n};\n\nstruct nfs_locku_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *seqid;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs_locku_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_lock_context;\n\nstruct nfs4_unlockdata {\n\tstruct nfs_locku_args arg;\n\tstruct nfs_locku_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct file_lock fl;\n\tstruct nfs_server *server;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_xattr_cache;\n\nstruct nfs4_xattr_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n\tstruct nfs4_xattr_cache *cache;\n\tbool draining;\n};\n\nstruct nfs4_xattr_entry;\n\nstruct nfs4_xattr_cache {\n\tstruct kref ref;\n\tstruct nfs4_xattr_bucket buckets[64];\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tatomic_long_t nent;\n\tspinlock_t listxattr_lock;\n\tstruct inode *inode;\n\tstruct nfs4_xattr_entry *listxattr;\n};\n\nstruct nfs4_xattr_entry {\n\tstruct kref ref;\n\tstruct hlist_node hnode;\n\tstruct list_head lru;\n\tstruct list_head dispose;\n\tchar *xattr_name;\n\tvoid *xattr_value;\n\tsize_t xattr_size;\n\tstruct nfs4_xattr_bucket *bucket;\n\tuint32_t flags;\n};\n\nstruct nfs4_xdr_opaque_ops {\n\tvoid (*encode)(struct xdr_stream *, const void *, const struct nfs4_xdr_opaque_data *);\n\tvoid (*free)(struct nfs4_xdr_opaque_data *);\n};\n\nstruct nfs_access_entry {\n\tstruct rb_node rb_node;\n\tstruct list_head lru;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tstruct group_info *group_info;\n\tu64 timestamp;\n\t__u32 mask;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_auth_info {\n\tunsigned int flavor_len;\n\trpc_authflavor_t flavors[12];\n};\n\nstruct nfs_cache_array_entry {\n\tu64 cookie;\n\tu64 ino;\n\tconst char *name;\n\tunsigned int name_len;\n\tunsigned char d_type;\n};\n\nstruct nfs_cache_array {\n\tu64 change_attr;\n\tu64 last_cookie;\n\tunsigned int size;\n\tunsigned char folio_full: 1;\n\tunsigned char folio_is_eof: 1;\n\tunsigned char cookies_are_ordered: 1;\n\tstruct nfs_cache_array_entry array[0];\n};\n\nstruct svc_serv;\n\nstruct nfs_callback_data {\n\tunsigned int users;\n\tstruct svc_serv *serv;\n};\n\nstruct xprtsec_parms {\n\tenum xprtsec_policies policy;\n\tkey_serial_t cert_serial;\n\tkey_serial_t privkey_serial;\n};\n\nstruct nfs_rpc_ops;\n\nstruct nfs_subversion;\n\nstruct nfs_client {\n\trefcount_t cl_count;\n\tatomic_t cl_mds_count;\n\tint cl_cons_state;\n\tlong unsigned int cl_res_state;\n\tlong unsigned int cl_flags;\n\tstruct __kernel_sockaddr_storage cl_addr;\n\tsize_t cl_addrlen;\n\tchar *cl_hostname;\n\tchar *cl_acceptor;\n\tstruct list_head cl_share_link;\n\tstruct list_head cl_superblocks;\n\tstruct rpc_clnt *cl_rpcclient;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tint cl_proto;\n\tstruct nfs_subversion *cl_nfs_mod;\n\tu32 cl_minorversion;\n\tunsigned int cl_nconnect;\n\tunsigned int cl_max_connect;\n\tconst char *cl_principal;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct list_head cl_ds_clients;\n\tu64 cl_clientid;\n\tnfs4_verifier cl_confirm;\n\tlong unsigned int cl_state;\n\tspinlock_t cl_lock;\n\tlong unsigned int cl_lease_time;\n\tlong unsigned int cl_last_renewal;\n\tstruct delayed_work cl_renewd;\n\tstruct rpc_wait_queue cl_rpcwaitq;\n\tstruct idmap *cl_idmap;\n\tconst char *cl_owner_id;\n\tu32 cl_cb_ident;\n\tconst struct nfs4_minor_version_ops *cl_mvops;\n\tlong unsigned int cl_mig_gen;\n\tstruct nfs4_slot_table *cl_slot_tbl;\n\tu32 cl_seqid;\n\tu32 cl_exchange_flags;\n\tstruct nfs4_session *cl_session;\n\tbool cl_preserve_clid;\n\tstruct nfs41_server_owner *cl_serverowner;\n\tstruct nfs41_server_scope *cl_serverscope;\n\tstruct nfs41_impl_id *cl_implid;\n\tlong unsigned int cl_sp4_flags;\n\twait_queue_head_t cl_lock_waitq;\n\tchar cl_ipaddr[48];\n\tstruct net *cl_net;\n\tnetns_tracker cl_ns_tracker;\n\tstruct list_head pending_cb_stateids;\n\tstruct callback_head rcu;\n};\n\nstruct rpc_timeout;\n\nstruct nfs_client_initdata {\n\tlong unsigned int init_flags;\n\tconst char *hostname;\n\tconst struct __kernel_sockaddr_storage *addr;\n\tconst char *nodename;\n\tconst char *ip_addr;\n\tsize_t addrlen;\n\tstruct nfs_subversion *nfs_mod;\n\tint proto;\n\tu32 minorversion;\n\tunsigned int nconnect;\n\tunsigned int max_connect;\n\tstruct net *net;\n\tconst struct rpc_timeout *timeparms;\n\tconst struct cred *cred;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct nfs_clone_mount {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_commit_data;\n\nstruct nfs_commit_info;\n\nstruct nfs_page;\n\nstruct nfs_commit_completion_ops {\n\tvoid (*completion)(struct nfs_commit_data *);\n\tvoid (*resched_write)(struct nfs_commit_info *, struct nfs_page *);\n};\n\nstruct nfs_commitargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\t__u64 offset;\n\t__u32 count;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_direct_req;\n\nstruct nfs_commit_data {\n\tstruct rpc_task task;\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_writeverf verf;\n\tstruct list_head pages;\n\tstruct list_head list;\n\tstruct nfs_direct_req *dreq;\n\tstruct nfs_commitargs args;\n\tstruct nfs_commitres res;\n\tstruct nfs_open_context *context;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_index;\n\tloff_t lwb;\n\tconst struct rpc_call_ops *mds_ops;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n\tint (*commit_done_cb)(struct rpc_task *, struct nfs_commit_data *);\n\tlong unsigned int flags;\n};\n\nstruct nfs_mds_commit_info;\n\nstruct nfs_commit_info {\n\tstruct inode *inode;\n\tstruct nfs_mds_commit_info *mds;\n\tstruct pnfs_ds_commit_info *ds;\n\tstruct nfs_direct_req *dreq;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n};\n\nstruct nfs_delegation {\n\tstruct hlist_node hash;\n\tstruct list_head super_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tfmode_t type;\n\tlong unsigned int pagemod_limit;\n\t__u64 change_attr;\n\tlong unsigned int test_gen;\n\tlong unsigned int flags;\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_mds_commit_info {\n\tatomic_t rpcs_out;\n\tatomic_long_t ncommit;\n\tstruct list_head list;\n};\n\nstruct nfs_direct_req {\n\tstruct kref kref;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct kiocb *iocb;\n\tstruct inode *inode;\n\tatomic_t io_count;\n\tspinlock_t lock;\n\tloff_t io_start;\n\tssize_t count;\n\tssize_t max_count;\n\tssize_t error;\n\tstruct completion completion;\n\tstruct nfs_mds_commit_info mds_cinfo;\n\tstruct pnfs_ds_commit_info ds_cinfo;\n\tstruct work_struct work;\n\tint flags;\n};\n\nstruct nfs_entry {\n\t__u64 ino;\n\t__u64 cookie;\n\tconst char *name;\n\tunsigned int len;\n\tint eof;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tunsigned char d_type;\n\tstruct nfs_server *server;\n};\n\nstruct nfs_find_desc {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_free_stateid_data {\n\tstruct nfs_server *server;\n\tstruct nfs41_free_stateid_args args;\n\tstruct nfs41_free_stateid_res res;\n};\n\nstruct nfs_fs_context {\n\tbool internal;\n\tbool skip_reconfig_option_check;\n\tbool need_mount;\n\tbool sloppy;\n\tunsigned int flags;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tunsigned int timeo;\n\tunsigned int retrans;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namlen;\n\tunsigned int options;\n\tunsigned int bsize;\n\tstruct nfs_auth_info auth_info;\n\trpc_authflavor_t selected_flavor;\n\tstruct xprtsec_parms xprtsec;\n\tchar *client_address;\n\tunsigned int version;\n\tunsigned int minorversion;\n\tchar *fscache_uniq;\n\tshort unsigned int protofamily;\n\tshort unsigned int mountfamily;\n\tbool has_sec_mnt_opts;\n\tint lock_status;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tu32 version;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t} mount_server;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tchar *export_path;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t\tshort unsigned int nconnect;\n\t\tshort unsigned int max_connect;\n\t\tshort unsigned int export_path_len;\n\t} nfs_server;\n\tstruct nfs_fh *mntfh;\n\tstruct nfs_server *server;\n\tstruct nfs_subversion *nfs_mod;\n\tstruct nfs_clone_mount clone_data;\n};\n\nstruct nfs_fsinfo {\n\tstruct nfs_fattr *fattr;\n\t__u32 rtmax;\n\t__u32 rtpref;\n\t__u32 rtmult;\n\t__u32 wtmax;\n\t__u32 wtpref;\n\t__u32 wtmult;\n\t__u32 dtpref;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\t__u32 lease_time;\n\t__u32 nlayouttypes;\n\t__u32 layouttype[8];\n\t__u32 blksize;\n\t__u32 clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\t__u32 xattr_support;\n};\n\nstruct nfs_fsstat {\n\tstruct nfs_fattr *fattr;\n\t__u64 tbytes;\n\t__u64 fbytes;\n\t__u64 abytes;\n\t__u64 tfiles;\n\t__u64 ffiles;\n\t__u64 afiles;\n};\n\nstruct nfs_getaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_getaclres {\n\tstruct nfs4_sequence_res seq_res;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tsize_t acl_data_offset;\n\tint acl_flags;\n\tstruct folio *acl_scratch;\n};\n\nstruct nfs_inode {\n\t__u64 fileid;\n\tstruct nfs_fh fh;\n\tlong unsigned int flags;\n\tlong unsigned int cache_validity;\n\tstruct timespec64 btime;\n\tlong unsigned int read_cache_jiffies;\n\tlong unsigned int attrtimeo;\n\tlong unsigned int attrtimeo_timestamp;\n\tlong unsigned int attr_gencount;\n\tstruct rb_root access_cache;\n\tstruct list_head access_cache_entry_lru;\n\tstruct list_head access_cache_inode_lru;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int cache_change_attribute;\n\t\t\t__be32 cookieverf[2];\n\t\t\tstruct rw_semaphore rmdir_sem;\n\t\t};\n\t\tstruct {\n\t\t\tatomic_long_t nrequests;\n\t\t\tatomic_long_t redirtied_pages;\n\t\t\tstruct nfs_mds_commit_info commit_info;\n\t\t\tstruct mutex commit_mutex;\n\t\t};\n\t};\n\tstruct list_head open_files;\n\tstruct {\n\t\tint cnt;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 end;\n\t\t} gap[16];\n\t} *ooo;\n\tstruct nfs4_cached_acl *nfs4_acl;\n\tstruct list_head open_states;\n\tstruct nfs_delegation *delegation;\n\tstruct rw_semaphore rwsem;\n\tstruct pnfs_layout_hdr *layout;\n\t__u64 write_io;\n\t__u64 read_io;\n\tstruct nfs4_xattr_cache *xattr_cache;\n\tunion {\n\t\tstruct inode vfs_inode;\n\t};\n};\n\nstruct nfs_io_completion {\n\tvoid (*complete)(void *);\n\tvoid *data;\n\tstruct kref refcount;\n};\n\nstruct nfs_iostats {\n\tlong long unsigned int bytes[8];\n\tlong unsigned int events[27];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nfs_lock_context {\n\trefcount_t count;\n\tstruct list_head list;\n\tstruct nfs_open_context *open_context;\n\tfl_owner_t lockowner;\n\tatomic_t io_count;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_lockt_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_lockt_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct file_lock *denied;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct nfs_mount_data {\n\tint version;\n\tint fd;\n\tstruct nfs2_fh old_root;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct sockaddr_in addr;\n\tchar hostname[256];\n\tint namlen;\n\tunsigned int bsize;\n\tstruct nfs3_fh root;\n\tint pseudoflavor;\n\tchar context[257];\n};\n\nstruct nfs_mount_request {\n\tstruct __kernel_sockaddr_storage *sap;\n\tsize_t salen;\n\tchar *hostname;\n\tchar *dirpath;\n\tu32 version;\n\tshort unsigned int protocol;\n\tstruct nfs_fh *fh;\n\tint noresvport;\n\tunsigned int *auth_flav_len;\n\trpc_authflavor_t *auth_flavs;\n\tstruct net *net;\n};\n\nstruct rpc_program;\n\nstruct rpc_stat {\n\tconst struct rpc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int netreconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcretrans;\n\tunsigned int rpcauthrefresh;\n\tunsigned int rpcgarbage;\n};\n\nstruct nfs_netns_client;\n\nstruct nfs_net {\n\tstruct cache_detail *nfs_dns_resolve;\n\tstruct rpc_pipe *bl_device_pipe;\n\tstruct bl_dev_msg bl_mount_reply;\n\twait_queue_head_t bl_wq;\n\tstruct mutex bl_mutex;\n\tstruct list_head nfs_client_list;\n\tstruct list_head nfs_volume_list;\n\tstruct idr cb_ident_idr;\n\tshort unsigned int nfs_callback_tcpport;\n\tshort unsigned int nfs_callback_tcpport6;\n\tint cb_users[3];\n\tstruct list_head nfs4_data_server_cache;\n\tspinlock_t nfs4_data_server_lock;\n\tstruct nfs_netns_client *nfs_client;\n\tspinlock_t nfs_client_lock;\n\tktime_t boot_time;\n\tstruct rpc_stat rpcstats;\n\tstruct proc_dir_entry *proc_nfsfs;\n};\n\nstruct nfs_netns_client {\n\tstruct kobject kobject;\n\tstruct kobject nfs_net_kobj;\n\tstruct net *net;\n\tconst char *identifier;\n};\n\nstruct nfs_open_context {\n\tstruct nfs_lock_context lock_context;\n\tfl_owner_t flock_owner;\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\tstruct rpc_cred *ll_cred;\n\tstruct nfs4_state *state;\n\tfmode_t mode;\n\tint error;\n\tlong unsigned int flags;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tstruct nfs_file_localio nfl;\n};\n\nstruct nfs_open_dir_context {\n\tstruct list_head list;\n\tatomic_t cache_hits;\n\tatomic_t cache_misses;\n\tlong unsigned int attr_gencount;\n\t__be32 verf[2];\n\t__u64 dir_cookie;\n\t__u64 last_cookie;\n\tlong unsigned int page_index;\n\tunsigned int dtsize;\n\tbool force_clear;\n\tbool eof;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_page {\n\tstruct list_head wb_list;\n\tunion {\n\t\tstruct page *wb_page;\n\t\tstruct folio *wb_folio;\n\t};\n\tstruct nfs_lock_context *wb_lock_context;\n\tlong unsigned int wb_index;\n\tunsigned int wb_offset;\n\tunsigned int wb_pgbase;\n\tunsigned int wb_bytes;\n\tstruct kref wb_kref;\n\tlong unsigned int wb_flags;\n\tstruct nfs_write_verifier wb_verf;\n\tstruct nfs_page *wb_this_page;\n\tstruct nfs_page *wb_head;\n\tshort unsigned int wb_nio;\n};\n\nstruct nfs_page_array {\n\tstruct page **pagevec;\n\tunsigned int npages;\n\tstruct page *page_array[8];\n};\n\nstruct nfs_page_iter_page {\n\tconst struct nfs_page *req;\n\tsize_t count;\n};\n\nstruct nfs_pgio_mirror {\n\tstruct list_head pg_list;\n\tlong unsigned int pg_bytes_written;\n\tsize_t pg_count;\n\tsize_t pg_bsize;\n\tunsigned int pg_base;\n\tunsigned char pg_recoalesce: 1;\n};\n\nstruct nfs_pageio_ops;\n\nstruct nfs_rw_ops;\n\nstruct nfs_pgio_completion_ops;\n\nstruct nfs_pageio_descriptor {\n\tstruct inode *pg_inode;\n\tconst struct nfs_pageio_ops *pg_ops;\n\tconst struct nfs_rw_ops *pg_rw_ops;\n\tint pg_ioflags;\n\tint pg_error;\n\tconst struct rpc_call_ops *pg_rpc_callops;\n\tconst struct nfs_pgio_completion_ops *pg_completion_ops;\n\tstruct pnfs_layout_segment *pg_lseg;\n\tstruct nfs_io_completion *pg_io_completion;\n\tstruct nfs_direct_req *pg_dreq;\n\tunsigned int pg_bsize;\n\tu32 pg_mirror_count;\n\tstruct nfs_pgio_mirror *pg_mirrors;\n\tstruct nfs_pgio_mirror pg_mirrors_static[1];\n\tstruct nfs_pgio_mirror *pg_mirrors_dynamic;\n\tu32 pg_mirror_idx;\n\tshort unsigned int pg_maxretrans;\n\tunsigned char pg_moreio: 1;\n};\n\nstruct nfs_pageio_ops {\n\tvoid (*pg_init)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tsize_t (*pg_test)(struct nfs_pageio_descriptor *, struct nfs_page *, struct nfs_page *);\n\tint (*pg_doio)(struct nfs_pageio_descriptor *);\n\tunsigned int (*pg_get_mirror_count)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tvoid (*pg_cleanup)(struct nfs_pageio_descriptor *);\n\tstruct nfs_pgio_mirror * (*pg_get_mirror)(struct nfs_pageio_descriptor *, u32);\n\tu32 (*pg_set_mirror)(struct nfs_pageio_descriptor *, u32);\n};\n\nstruct nfs_pathconf {\n\tstruct nfs_fattr *fattr;\n\t__u32 max_link;\n\t__u32 max_namelen;\n};\n\nstruct nfs_pgio_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct nfs_open_context *context;\n\tstruct nfs_lock_context *lock_context;\n\tnfs4_stateid stateid;\n\t__u64 offset;\n\t__u32 count;\n\tunsigned int pgbase;\n\tstruct page **pages;\n\tunion {\n\t\tunsigned int replen;\n\t\tstruct {\n\t\t\tconst u32 *bitmask;\n\t\t\tu32 bitmask_store[3];\n\t\t\tenum nfs3_stable_how stable;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header;\n\nstruct nfs_pgio_completion_ops {\n\tvoid (*error_cleanup)(struct list_head *, int);\n\tvoid (*init_hdr)(struct nfs_pgio_header *);\n\tvoid (*completion)(struct nfs_pgio_header *);\n\tvoid (*reschedule_io)(struct nfs_pgio_header *);\n};\n\nstruct nfs_pgio_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\t__u64 count;\n\t__u32 op_status;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int replen;\n\t\t\tint eof;\n\t\t\tvoid *scratch;\n\t\t};\n\t\tstruct {\n\t\t\tstruct nfs_writeverf *verf;\n\t\t\tconst struct nfs_server *server;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header {\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct list_head pages;\n\tstruct nfs_page *req;\n\tstruct nfs_writeverf verf;\n\tfmode_t rw_mode;\n\tstruct pnfs_layout_segment *lseg;\n\tloff_t io_start;\n\tconst struct rpc_call_ops *mds_ops;\n\tvoid (*release)(struct nfs_pgio_header *);\n\tconst struct nfs_pgio_completion_ops *completion_ops;\n\tconst struct nfs_rw_ops *rw_ops;\n\tstruct nfs_io_completion *io_completion;\n\tstruct nfs_direct_req *dreq;\n\tshort unsigned int retrans;\n\tint pnfs_error;\n\tint error;\n\tunsigned int good_bytes;\n\tlong unsigned int flags;\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_pgio_args args;\n\tstruct nfs_pgio_res res;\n\tlong unsigned int timestamp;\n\tint (*pgio_done_cb)(struct rpc_task *, struct nfs_pgio_header *);\n\t__u64 mds_offset;\n\tstruct nfs_page_array page_array;\n\tstruct nfs_client *ds_clp;\n\tu32 ds_commit_idx;\n\tu32 pgio_mirror_idx;\n};\n\nstruct nfs_readdir_arg {\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\t__be32 *verf;\n\tu64 cookie;\n\tstruct page **pages;\n\tunsigned int page_len;\n\tbool plus;\n};\n\nstruct nfs_readdir_descriptor {\n\tstruct file *file;\n\tstruct folio *folio;\n\tstruct dir_context *ctx;\n\tlong unsigned int folio_index;\n\tlong unsigned int folio_index_max;\n\tu64 dir_cookie;\n\tu64 last_cookie;\n\tloff_t current_index;\n\t__be32 verf[2];\n\tlong unsigned int dir_verifier;\n\tlong unsigned int timestamp;\n\tlong unsigned int gencount;\n\tlong unsigned int attr_gencount;\n\tunsigned int cache_entry_index;\n\tunsigned int buffer_fills;\n\tunsigned int dtsize;\n\tbool clear_cache;\n\tbool plus;\n\tbool eob;\n\tbool eof;\n};\n\nstruct nfs_readdir_res {\n\t__be32 *verf;\n};\n\nstruct nfs_referral_count {\n\tstruct list_head list;\n\tconst struct task_struct *task;\n\tunsigned int referral_count;\n};\n\nstruct nfs_removeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct qstr name;\n};\n\nstruct nfs_removeres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs_renameargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *old_dir;\n\tconst struct nfs_fh *new_dir;\n\tconst struct qstr *old_name;\n\tconst struct qstr *new_name;\n};\n\nstruct nfs_renameres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs4_change_info old_cinfo;\n\tstruct nfs_fattr *old_fattr;\n\tstruct nfs4_change_info new_cinfo;\n\tstruct nfs_fattr *new_fattr;\n};\n\nstruct nfs_renamedata {\n\tstruct nfs_renameargs args;\n\tstruct nfs_renameres res;\n\tstruct rpc_task task;\n\tconst struct cred *cred;\n\tstruct inode *old_dir;\n\tstruct dentry *old_dentry;\n\tstruct nfs_fattr old_fattr;\n\tstruct inode *new_dir;\n\tstruct dentry *new_dentry;\n\tstruct nfs_fattr new_fattr;\n\tvoid (*complete)(struct rpc_task *, struct nfs_renamedata *);\n\tlong int timeout;\n\tbool cancelled;\n};\n\nstruct nlmclnt_operations;\n\nstruct nfs_unlinkdata;\n\nstruct nfs_rpc_ops {\n\tu32 version;\n\tconst struct dentry_operations *dentry_ops;\n\tconst struct inode_operations *dir_inode_ops;\n\tconst struct inode_operations *file_inode_ops;\n\tconst struct file_operations *file_ops;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tint (*getroot)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*submount)(struct fs_context *, struct nfs_server *);\n\tint (*try_get_tree)(struct fs_context *);\n\tint (*getattr)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, struct inode *);\n\tint (*setattr)(struct dentry *, struct nfs_fattr *, struct iattr *);\n\tint (*lookup)(struct inode *, struct dentry *, const struct qstr *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*lookupp)(struct inode *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*access)(struct inode *, struct nfs_access_entry *, const struct cred *);\n\tint (*readlink)(struct inode *, struct page *, unsigned int, unsigned int);\n\tint (*create)(struct inode *, struct dentry *, struct iattr *, int);\n\tint (*remove)(struct inode *, struct dentry *);\n\tvoid (*unlink_setup)(struct rpc_message *, struct dentry *, struct inode *);\n\tvoid (*unlink_rpc_prepare)(struct rpc_task *, struct nfs_unlinkdata *);\n\tint (*unlink_done)(struct rpc_task *, struct inode *);\n\tvoid (*rename_setup)(struct rpc_message *, struct dentry *, struct dentry *, struct inode *);\n\tvoid (*rename_rpc_prepare)(struct rpc_task *, struct nfs_renamedata *);\n\tint (*rename_done)(struct rpc_task *, struct inode *, struct inode *);\n\tint (*link)(struct inode *, struct inode *, const struct qstr *);\n\tint (*symlink)(struct inode *, struct dentry *, struct folio *, unsigned int, struct iattr *);\n\tstruct dentry * (*mkdir)(struct inode *, struct dentry *, struct iattr *);\n\tint (*rmdir)(struct inode *, const struct qstr *);\n\tint (*readdir)(struct nfs_readdir_arg *, struct nfs_readdir_res *);\n\tint (*mknod)(struct inode *, struct dentry *, struct iattr *, dev_t);\n\tint (*statfs)(struct nfs_server *, struct nfs_fh *, struct nfs_fsstat *);\n\tint (*fsinfo)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*pathconf)(struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *);\n\tint (*set_capabilities)(struct nfs_server *, struct nfs_fh *);\n\tint (*decode_dirent)(struct xdr_stream *, struct nfs_entry *, bool);\n\tint (*pgio_rpc_prepare)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*read_setup)(struct nfs_pgio_header *, struct rpc_message *);\n\tint (*read_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*write_setup)(struct nfs_pgio_header *, struct rpc_message *, struct rpc_clnt **);\n\tint (*write_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*commit_setup)(struct nfs_commit_data *, struct rpc_message *, struct rpc_clnt **);\n\tvoid (*commit_rpc_prepare)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*commit_done)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tint (*lock_check_bounds)(const struct file_lock *);\n\tvoid (*clear_acl_cache)(struct inode *);\n\tvoid (*close_context)(struct nfs_open_context *, int);\n\tstruct inode * (*open_context)(struct inode *, struct nfs_open_context *, int, struct iattr *, int *);\n\tint (*have_delegation)(struct inode *, fmode_t, int);\n\tvoid (*return_delegation)(struct inode *);\n\tstruct nfs_client * (*alloc_client)(const struct nfs_client_initdata *);\n\tstruct nfs_client * (*init_client)(struct nfs_client *, const struct nfs_client_initdata *);\n\tvoid (*free_client)(struct nfs_client *);\n\tstruct nfs_server * (*create_server)(struct fs_context *);\n\tstruct nfs_server * (*clone_server)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, rpc_authflavor_t);\n\tint (*discover_trunking)(struct nfs_server *, struct nfs_fh *);\n\tvoid (*enable_swap)(struct inode *);\n\tvoid (*disable_swap)(struct inode *);\n};\n\nstruct rpc_task_setup;\n\nstruct nfs_rw_ops {\n\tstruct nfs_pgio_header * (*rw_alloc_header)(void);\n\tvoid (*rw_free_header)(struct nfs_pgio_header *);\n\tint (*rw_done)(struct rpc_task *, struct nfs_pgio_header *, struct inode *);\n\tvoid (*rw_result)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*rw_initiate)(struct nfs_pgio_header *, struct rpc_message *, const struct nfs_rpc_ops *, struct rpc_task_setup *, int);\n};\n\nstruct nfs_seqid {\n\tstruct nfs_seqid_counter *sequence;\n\tstruct list_head list;\n\tstruct rpc_task *task;\n};\n\nstruct nlm_host;\n\nstruct nfs_server {\n\tstruct nfs_client *nfs_client;\n\tstruct list_head client_link;\n\tstruct list_head master_link;\n\tstruct rpc_clnt *client;\n\tstruct rpc_clnt *client_acl;\n\tstruct nlm_host *nlm_host;\n\tstruct nfs_iostats *io_stats;\n\twait_queue_head_t write_congestion_wait;\n\tatomic_long_t writeback;\n\tunsigned int write_congested;\n\tunsigned int flags;\n\tunsigned int automount_inherit;\n\tunsigned int caps;\n\t__u64 fattr_valid;\n\tunsigned int rsize;\n\tunsigned int rpages;\n\tunsigned int wsize;\n\tunsigned int wtmult;\n\tunsigned int dtsize;\n\tshort unsigned int port;\n\tunsigned int bsize;\n\tunsigned int gxasize;\n\tunsigned int sxasize;\n\tunsigned int lxasize;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namelen;\n\tunsigned int options;\n\tunsigned int clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\tstruct nfs_fsid fsid;\n\tint s_sysfs_id;\n\t__u64 maxfilesize;\n\tlong unsigned int mount_time;\n\tstruct super_block *super;\n\tdev_t s_dev;\n\tstruct nfs_auth_info auth_info;\n\tu32 fh_expire_type;\n\tu32 pnfs_blksize;\n\tu32 attr_bitmask[3];\n\tu32 attr_bitmask_nl[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 cache_consistency_bitmask[3];\n\tu32 acl_bitmask;\n\tstruct pnfs_layoutdriver_type *pnfs_curr_ld;\n\tstruct rpc_wait_queue roc_rpcwaitq;\n\tstruct rb_root state_owners;\n\tatomic64_t owner_ctr;\n\tstruct list_head state_owners_lru;\n\tstruct list_head layouts;\n\tstruct list_head delegations;\n\tspinlock_t delegations_lock;\n\tstruct list_head delegations_return;\n\tstruct list_head delegations_lru;\n\tstruct list_head delegations_delayed;\n\tatomic_long_t nr_active_delegations;\n\tunsigned int delegation_hash_mask;\n\tstruct hlist_head *delegation_hash_table;\n\tstruct list_head ss_copies;\n\tstruct list_head ss_src_copies;\n\tlong unsigned int delegation_flags;\n\tlong unsigned int delegation_gen;\n\tlong unsigned int mig_gen;\n\tlong unsigned int mig_status;\n\tvoid (*destroy)(struct nfs_server *);\n\tatomic_t active;\n\tstruct __kernel_sockaddr_storage mountd_address;\n\tsize_t mountd_addrlen;\n\tu32 mountd_version;\n\tshort unsigned int mountd_port;\n\tshort unsigned int mountd_protocol;\n\tstruct rpc_wait_queue uoc_rpcwaitq;\n\tunsigned int read_hdrsize;\n\tconst struct cred *cred;\n\tbool has_sec_mnt_opts;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_setaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_setaclres {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs_setattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct iattr *iap;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n};\n\nstruct nfs_setattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs_ssc_client_ops {\n\tvoid (*sco_sb_deactive)(struct super_block *);\n};\n\nstruct nfs_ssc_client_ops_tbl {\n\tconst struct nfs4_ssc_client_ops *ssc_nfs4_ops;\n\tconst struct nfs_ssc_client_ops *ssc_nfs_ops;\n};\n\nstruct rpc_version;\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct nfs_subversion {\n\tstruct module *owner;\n\tstruct file_system_type *nfs_fs;\n\tconst struct rpc_version *rpc_vers;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tconst struct super_operations *sops;\n\tconst struct xattr_handler * const *xattr;\n};\n\nstruct nfs_unlinkdata {\n\tstruct nfs_removeargs args;\n\tstruct nfs_removeres res;\n\tstruct dentry *dentry;\n\twait_queue_head_t wq;\n\tconst struct cred *cred;\n\tstruct nfs_fattr dir_attr;\n\tlong int timeout;\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct nic_cfg_msg {\n\tu8 msg;\n\tu8 vf_id;\n\tu8 node_id;\n\tu8 tns_mode: 1;\n\tu8 sqs_mode: 1;\n\tu8 loopback_supported: 1;\n\tu8 mac_addr[6];\n};\n\nstruct qs_cfg_msg {\n\tu8 msg;\n\tu8 num;\n\tu8 sqs_count;\n\tu64 cfg;\n};\n\nstruct rq_cfg_msg {\n\tu8 msg;\n\tu8 qs_num;\n\tu8 rq_num;\n\tu64 cfg;\n};\n\nstruct sq_cfg_msg {\n\tu8 msg;\n\tu8 qs_num;\n\tu8 sq_num;\n\tbool sqs_mode;\n\tu64 cfg;\n};\n\nstruct set_mac_msg {\n\tu8 msg;\n\tu8 vf_id;\n\tu8 mac_addr[6];\n};\n\nstruct set_frs_msg {\n\tu8 msg;\n\tu8 vf_id;\n\tu16 max_frs;\n};\n\nstruct rss_sz_msg {\n\tu8 msg;\n\tu8 vf_id;\n\tu16 ind_tbl_size;\n};\n\nstruct rss_cfg_msg {\n\tu8 msg;\n\tu8 vf_id;\n\tu8 hash_bits;\n\tu8 tbl_len;\n\tu8 tbl_offset;\n\tu8 ind_tbl[8];\n};\n\nstruct sqs_alloc {\n\tu8 msg;\n\tu8 vf_id;\n\tu8 qs_count;\n};\n\nstruct nicvf_ptr {\n\tu8 msg;\n\tu8 vf_id;\n\tbool sqs_mode;\n\tu8 sqs_id;\n\tu64 nicvf;\n};\n\nstruct set_loopback {\n\tu8 msg;\n\tu8 vf_id;\n\tbool enable;\n};\n\nstruct reset_stat_cfg {\n\tu8 msg;\n\tu16 rx_stat_mask;\n\tu8 tx_stat_mask;\n\tu16 rq_stat_mask;\n\tu16 sq_stat_mask;\n};\n\nstruct pfc {\n\tu8 msg;\n\tu8 get;\n\tu8 autoneg;\n\tu8 fc_rx;\n\tu8 fc_tx;\n};\n\nstruct set_ptp {\n\tu8 msg;\n\tbool enable;\n};\n\nstruct xcast {\n\tu8 msg;\n\tu8 mode;\n\tu64 mac: 48;\n};\n\nunion nic_mbx {\n\tstruct {\n\t\tu8 msg;\n\t} msg;\n\tstruct nic_cfg_msg nic_cfg;\n\tstruct qs_cfg_msg qs;\n\tstruct rq_cfg_msg rq;\n\tstruct sq_cfg_msg sq;\n\tstruct set_mac_msg mac;\n\tstruct set_frs_msg frs;\n\tstruct cpi_cfg_msg cpi_cfg;\n\tstruct rss_sz_msg rss_size;\n\tstruct rss_cfg_msg rss_cfg;\n\tstruct bgx_stats_msg bgx_stats;\n\tstruct bgx_link_status link_status;\n\tstruct sqs_alloc sqs_alloc;\n\tstruct nicvf_ptr nicvf;\n\tstruct set_loopback lbk;\n\tstruct reset_stat_cfg reset_stat;\n\tstruct pfc pfc;\n\tstruct set_ptp ptp;\n\tstruct xcast xcast;\n};\n\nstruct pkind_cfg {\n\tu64 minlen: 16;\n\tu64 maxlen: 16;\n\tu64 reserved_32_32: 1;\n\tu64 lenerr_en: 1;\n\tu64 rx_hdr: 3;\n\tu64 hdr_sl: 5;\n\tu64 reserved_42_63: 22;\n};\n\nstruct nicpf {\n\tstruct pci_dev *pdev;\n\tstruct hw_info *hw;\n\tu8 node;\n\tunsigned int flags;\n\tu8 num_vf_en;\n\tbool vf_enabled[128];\n\tvoid *reg_base;\n\tu8 num_sqs_en;\n\tu64 nicvf[128];\n\tu8 vf_sqs[1408];\n\tu8 pqs_vf[128];\n\tbool sqs_used[128];\n\tstruct pkind_cfg pkind;\n\tu8 *vf_lmac_map;\n\tu16 cpi_base[128];\n\tu16 rssi_base[128];\n\tu8 num_vec;\n\tunsigned int irq_allocated[10];\n\tchar irq_name[200];\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlm_cookie {\n\tunsigned char data[32];\n\tunsigned int len;\n};\n\nstruct nlm_lock {\n\tchar *caller;\n\tunsigned int len;\n\tstruct nfs_fh fh;\n\tstruct xdr_netobj oh;\n\tu32 svid;\n\tu64 lock_start;\n\tu64 lock_len;\n\tstruct file_lock fl;\n};\n\nstruct nlm_args {\n\tstruct nlm_cookie cookie;\n\tstruct nlm_lock lock;\n\tu32 block;\n\tu32 reclaim;\n\tu32 state;\n\tu32 monitor;\n\tu32 fsm_access;\n\tu32 fsm_mode;\n};\n\nstruct nlm_rqst;\n\nstruct nlm_file;\n\nstruct nlm_block {\n\tstruct kref b_count;\n\tstruct list_head b_list;\n\tstruct list_head b_flist;\n\tstruct nlm_rqst *b_call;\n\tstruct svc_serv *b_daemon;\n\tstruct nlm_host *b_host;\n\tlong unsigned int b_when;\n\tunsigned int b_id;\n\tunsigned char b_granted;\n\tstruct nlm_file *b_file;\n\tstruct cache_req *b_cache_req;\n\tstruct cache_deferred_req *b_deferred_req;\n\tunsigned int b_flags;\n};\n\nstruct nlm_share;\n\nstruct nlm_file {\n\tstruct hlist_node f_list;\n\tstruct nfs_fh f_handle;\n\tstruct file *f_file[2];\n\tstruct nlm_share *f_shares;\n\tstruct list_head f_blocks;\n\tunsigned int f_locks;\n\tunsigned int f_count;\n\tstruct mutex f_mutex;\n};\n\nstruct nsm_handle;\n\nstruct nlm_host {\n\tstruct hlist_node h_hash;\n\tstruct __kernel_sockaddr_storage h_addr;\n\tsize_t h_addrlen;\n\tstruct __kernel_sockaddr_storage h_srcaddr;\n\tsize_t h_srcaddrlen;\n\tstruct rpc_clnt *h_rpcclnt;\n\tchar *h_name;\n\tu32 h_version;\n\tshort unsigned int h_proto;\n\tshort unsigned int h_reclaiming: 1;\n\tshort unsigned int h_server: 1;\n\tshort unsigned int h_noresvport: 1;\n\tshort unsigned int h_inuse: 1;\n\twait_queue_head_t h_gracewait;\n\tstruct rw_semaphore h_rwsem;\n\tu32 h_state;\n\tu32 h_nsmstate;\n\tu32 h_pidcount;\n\trefcount_t h_count;\n\tstruct mutex h_mutex;\n\tlong unsigned int h_nextrebind;\n\tlong unsigned int h_expires;\n\tstruct list_head h_lockowners;\n\tspinlock_t h_lock;\n\tstruct list_head h_granted;\n\tstruct list_head h_reclaim;\n\tstruct nsm_handle *h_nsmhandle;\n\tchar *h_addrbuf;\n\tstruct net *net;\n\tconst struct cred *h_cred;\n\tchar nodename[65];\n\tconst struct nlmclnt_operations *h_nlmclnt_ops;\n};\n\nstruct nlm_lockowner {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct nlm_host *host;\n\tfl_owner_t owner;\n\tuint32_t pid;\n};\n\nstruct nlm_lookup_host_info {\n\tconst int server;\n\tconst struct sockaddr *sap;\n\tconst size_t salen;\n\tconst short unsigned int protocol;\n\tconst u32 version;\n\tconst char *hostname;\n\tconst size_t hostname_len;\n\tconst int noresvport;\n\tstruct net *net;\n\tconst struct cred *cred;\n};\n\nstruct nsm_private {\n\tunsigned char data[16];\n};\n\nstruct nlm_reboot {\n\tchar *mon;\n\tunsigned int len;\n\tu32 state;\n\tstruct nsm_private priv;\n};\n\nstruct nlm_res {\n\tstruct nlm_cookie cookie;\n\t__be32 status;\n\tstruct nlm_lock lock;\n};\n\nstruct nlm_rqst {\n\trefcount_t a_count;\n\tunsigned int a_flags;\n\tstruct nlm_host *a_host;\n\tstruct nlm_args a_args;\n\tstruct nlm_res a_res;\n\tstruct nlm_block *a_block;\n\tunsigned int a_retries;\n\tu8 a_owner[74];\n\tvoid *a_callback_data;\n};\n\nstruct nlm_share {\n\tstruct nlm_share *s_next;\n\tstruct nlm_host *s_host;\n\tstruct nlm_file *s_file;\n\tstruct xdr_netobj s_owner;\n\tu32 s_access;\n\tu32 s_mode;\n};\n\nstruct nlm_wait {\n\tstruct list_head b_list;\n\twait_queue_head_t b_wait;\n\tstruct nlm_host *b_host;\n\tstruct file_lock *b_lock;\n\t__be32 b_status;\n};\n\nstruct nlmclnt_initdata {\n\tconst char *hostname;\n\tconst struct sockaddr *address;\n\tsize_t addrlen;\n\tshort unsigned int protocol;\n\tu32 nfs_version;\n\tint noresvport;\n\tstruct net *net;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tconst struct cred *cred;\n};\n\nstruct nlmclnt_operations {\n\tvoid (*nlmclnt_alloc_call)(void *);\n\tbool (*nlmclnt_unlock_prepare)(struct rpc_task *, void *);\n\tvoid (*nlmclnt_release_call)(void *);\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nlmsvc_binding {\n\t__be32 (*fopen)(struct svc_rqst *, struct nfs_fh *, struct file **, int);\n\tvoid (*fclose)(struct file *);\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\nstruct nmi_ctx {\n\tu64 hcr;\n\tunsigned int cnt;\n};\n\nstruct node {\n\tstruct device dev;\n\tstruct list_head access_list;\n\tstruct list_head cache_attrs;\n\tstruct device *cache_dev;\n};\n\nstruct node_access_nodes {\n\tstruct device dev;\n\tstruct list_head list_node;\n\tunsigned int access;\n\tstruct access_coordinate coord;\n};\n\nstruct node_attr {\n\tstruct device_attribute attr;\n\tenum node_states state;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_cache_info {\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct node_cache_attrs cache_attrs;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_hstate {\n\tstruct kobject *hugepages_kobj;\n\tstruct kobject *hstate_kobjs[4];\n};\n\nstruct node_memory_type_map {\n\tstruct memory_dev_type *memtype;\n\tint map_count;\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct nodemask_scratch {\n\tnodemask_t mask1;\n\tnodemask_t mask2;\n};\n\nstruct nosave_region {\n\tstruct list_head list;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n};\n\nstruct notif_entry {\n\tstruct list_head link;\n\tstruct completion c;\n\tu_int key;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct npcm_clock_adev {\n\tvoid *base;\n\tstruct auxiliary_device adev;\n};\n\nstruct npcm_reset_info;\n\nstruct npcm_rc_data {\n\tstruct reset_controller_dev rcdev;\n\tstruct notifier_block restart_nb;\n\tconst struct npcm_reset_info *info;\n\tstruct regmap *gcr_regmap;\n\tu32 sw_reset_number;\n\tstruct device *dev;\n\tvoid *base;\n\tspinlock_t lock;\n};\n\nstruct npcm_reset_info {\n\tu32 bmc_id;\n\tu32 num_ipsrst;\n\tconst u32 *ipsrst;\n};\n\nstruct npcm_rng {\n\tvoid *base;\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tu32 clkp;\n};\n\nstruct npcm_udc_data {\n\tstruct platform_device *ci;\n\tstruct clk *core_clk;\n\tstruct ci_hdrc_platform_data pdata;\n};\n\nstruct npcm_wdt {\n\tstruct watchdog_device wdd;\n\tvoid *reg;\n\tstruct clk *clk;\n};\n\nstruct ns2_mux {\n\tunsigned int base;\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int mask;\n\tunsigned int alt;\n};\n\nstruct ns2_mux_log {\n\tstruct ns2_mux mux;\n\tbool is_configured;\n};\n\nstruct ns2_phy_driver;\n\nstruct ns2_phy_data {\n\tstruct ns2_phy_driver *driver;\n\tstruct phy *phy;\n\tint new_state;\n};\n\nstruct ns2_phy_driver {\n\tvoid *icfgdrd_regs;\n\tvoid *idmdrd_rst_ctrl;\n\tvoid *crmu_usb2_ctrl;\n\tvoid *usb2h_strap_reg;\n\tstruct ns2_phy_data *data;\n\tstruct extcon_dev *edev;\n\tstruct gpio_desc *vbus_gpiod;\n\tstruct gpio_desc *id_gpiod;\n\tint id_irq;\n\tint vbus_irq;\n\tlong unsigned int debounce_jiffies;\n\tstruct delayed_work wq_extcon;\n};\n\nstruct ns2_pinconf {\n\tunsigned int base;\n\tunsigned int offset;\n\tunsigned int src_shift;\n\tunsigned int input_en;\n\tunsigned int pull_shift;\n\tunsigned int drive_shift;\n};\n\nstruct ns2_pin {\n\tunsigned int pin;\n\tchar *name;\n\tstruct ns2_pinconf pin_conf;\n};\n\nstruct ns2_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tconst unsigned int num_groups;\n};\n\nstruct ns2_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tconst unsigned int num_pins;\n\tconst struct ns2_mux mux;\n};\n\nstruct ns2_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct device *dev;\n\tvoid *base0;\n\tvoid *base1;\n\tvoid *pinconf_base;\n\tconst struct ns2_pin_group *groups;\n\tunsigned int num_groups;\n\tconst struct ns2_pin_function *functions;\n\tunsigned int num_functions;\n\tstruct ns2_mux_log *mux_log;\n\tspinlock_t lock;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct nsm_args {\n\tstruct nsm_private *priv;\n\tu32 prog;\n\tu32 vers;\n\tu32 proc;\n\tchar *mon_name;\n\tconst char *nodename;\n};\n\nstruct nsm_handle {\n\tstruct list_head sm_link;\n\trefcount_t sm_count;\n\tchar *sm_mon_name;\n\tchar *sm_name;\n\tstruct __kernel_sockaddr_storage sm_addr;\n\tsize_t sm_addrlen;\n\tunsigned int sm_monitored: 1;\n\tunsigned int sm_sticky: 1;\n\tstruct nsm_private sm_priv;\n\tchar sm_addrbuf[51];\n};\n\nstruct nsm_res {\n\tu32 status;\n\tu32 state;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n} __attribute__((packed));\n\nstruct ntmp_cmn_resp_query {\n\t__le32 entry_id;\n};\n\nstruct ntmp_dma_buf {\n\tstruct device *dev;\n\tsize_t size;\n\tvoid *buf;\n\tdma_addr_t dma;\n};\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t drops1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct numa_group {\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tint nr_tasks;\n\tpid_t gid;\n\tint active_nodes;\n\tstruct callback_head rcu;\n\tlong unsigned int total_faults;\n\tlong unsigned int max_faults_cpu;\n\tlong unsigned int faults[0];\n};\n\nstruct numa_maps {\n\tlong unsigned int pages;\n\tlong unsigned int anon;\n\tlong unsigned int active;\n\tlong unsigned int writeback;\n\tlong unsigned int mapcount_max;\n\tlong unsigned int dirty;\n\tlong unsigned int swapcache;\n\tlong unsigned int node[16];\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n\tbool mmap_locked;\n\tstruct vm_area_struct *locked_vma;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tstruct mempolicy *task_mempolicy;\n};\n\nstruct numa_maps_private {\n\tstruct proc_maps_private proc_maps;\n\tstruct numa_maps md;\n};\n\nstruct numa_memblk {\n\tu64 start;\n\tu64 end;\n\tint nid;\n};\n\nstruct numa_meminfo {\n\tint nr_blks;\n\tstruct numa_memblk blk[32];\n};\n\nstruct numa_stats {\n\tlong unsigned int load;\n\tlong unsigned int runnable;\n\tlong unsigned int util;\n\tlong unsigned int compute_capacity;\n\tunsigned int nr_running;\n\tunsigned int weight;\n\tenum numa_type node_type;\n\tint idle_cpu;\n};\n\nstruct tegra_mc;\n\nstruct nvidia_smmu {\n\tstruct arm_smmu_device___2 smmu;\n\tvoid *bases[2];\n\tunsigned int num_instances;\n\tstruct tegra_mc *mc;\n};\n\nstruct nvmem_cell_entry;\n\nstruct nvmem_cell {\n\tstruct nvmem_cell_entry *entry;\n\tconst char *id;\n\tint index;\n};\n\ntypedef int (*nvmem_cell_post_process_t)(void *, const char *, int, unsigned int, void *, size_t);\n\nstruct nvmem_cell_entry {\n\tconst char *name;\n\tint offset;\n\tsize_t raw_len;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n\tstruct device_node *np;\n\tstruct nvmem_device *nvmem;\n\tstruct list_head node;\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tsize_t raw_len;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n\tstruct device_node *np;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n};\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nstruct nvmem_keepout;\n\nstruct nvmem_layout;\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tbool add_legacy_fixed_of_cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool ignore_wp;\n\tstruct nvmem_layout *layout;\n\tstruct device_node *of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device {\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct list_head node;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tstruct nvmem_layout *layout;\n\tvoid *priv;\n\tbool sysfs_cells_populated;\n};\n\nstruct nvmem_keepout {\n\tunsigned int start;\n\tunsigned int end;\n\tunsigned char value;\n};\n\nstruct nvmem_layout {\n\tstruct device dev;\n\tstruct nvmem_device *nvmem;\n\tint (*add_cells)(struct nvmem_layout *);\n};\n\nstruct nvmem_layout_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct nvmem_layout *);\n\tvoid (*remove)(struct nvmem_layout *);\n};\n\nstruct nvs_region {\n\t__u64 phys_start;\n\t__u64 size;\n\tstruct list_head node;\n};\n\nstruct nwl_msi {\n\tlong unsigned int bitmap[1];\n\tstruct irq_domain *dev_domain;\n\tstruct mutex lock;\n\tint irq_msi0;\n\tint irq_msi1;\n};\n\nstruct nwl_pcie {\n\tstruct device *dev;\n\tvoid *breg_base;\n\tvoid *pcireg_base;\n\tvoid *ecam_base;\n\tstruct phy *phy[4];\n\tphys_addr_t phys_breg_base;\n\tphys_addr_t phys_pcie_reg_base;\n\tphys_addr_t phys_ecam_base;\n\tu32 breg_size;\n\tu32 pcie_reg_size;\n\tu32 ecam_size;\n\tint irq_intx;\n\tint irq_misc;\n\tstruct nwl_msi msi;\n\tstruct irq_domain *intx_irq_domain;\n\tstruct clk *clk;\n\traw_spinlock_t leg_mask_lock;\n};\n\nstruct nxp_fspi_devtype_data;\n\nstruct nxp_fspi {\n\tvoid *iobase;\n\tvoid *ahb_addr;\n\tu32 memmap_phy;\n\tu32 memmap_phy_size;\n\tu32 memmap_start;\n\tu32 memmap_len;\n\tstruct clk *clk;\n\tstruct clk *clk_en;\n\tstruct device *dev;\n\tstruct completion c;\n\tstruct nxp_fspi_devtype_data *devtype_data;\n\tstruct mutex lock;\n\tstruct pm_qos_request pm_qos_req;\n\tint selected;\n\tint flags;\n\tlong unsigned int pre_op_rate;\n\tlong unsigned int max_rate;\n};\n\nstruct nxp_fspi_devtype_data {\n\tunsigned int rxfifo;\n\tunsigned int txfifo;\n\tunsigned int ahb_buf_size;\n\tunsigned int quirks;\n\tunsigned int lut_num;\n\tbool little_endian;\n};\n\nstruct obj_cgroup {\n\tstruct percpu_ref refcnt;\n\tstruct mem_cgroup *memcg;\n\tatomic_t nr_charged_bytes;\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct obj_stock_pcp {\n\tlocal_trylock_t lock;\n\tunsigned int nr_bytes;\n\tstruct obj_cgroup *cached_objcg;\n\tstruct pglist_data *cached_pgdat;\n\tint nr_slab_reclaimable_b;\n\tint nr_slab_unreclaimable_b;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct ocotp_ctrl_reg {\n\tu32 bm_addr;\n\tu32 bm_busy;\n\tu32 bm_error;\n\tu32 bm_rel_shadows;\n};\n\nstruct ocotp_region {\n\tu32 start;\n\tu32 end;\n\tu32 flag;\n};\n\nstruct ocotp_devtype_data {\n\tint devtype;\n\tint nregs;\n\tu32 num_region;\n\tstruct ocotp_region region[0];\n};\n\nstruct ocotp_priv;\n\nstruct ocotp_params {\n\tunsigned int nregs;\n\tunsigned int bank_address_words;\n\tvoid (*set_timing)(struct ocotp_priv *);\n\tstruct ocotp_ctrl_reg ctrl;\n};\n\nstruct ocotp_priv___2 {\n\tstruct device *dev;\n\tconst struct ocotp_devtype_data *data;\n\tstruct imx_sc_ipc *nvmem_ipc;\n};\n\nstruct ocotp_priv {\n\tstruct device *dev;\n\tstruct clk *clk;\n\tvoid *base;\n\tconst struct ocotp_params *params;\n\tstruct nvmem_config *config;\n};\n\nstruct od_dbs_tuners {\n\tunsigned int powersave_bias;\n};\n\nstruct od_ops {\n\tunsigned int (*powersave_bias_target)(struct cpufreq_policy *, unsigned int, unsigned int);\n};\n\nstruct policy_dbs_info {\n\tstruct cpufreq_policy *policy;\n\tstruct mutex update_mutex;\n\tu64 last_sample_time;\n\ts64 sample_delay_ns;\n\tatomic_t work_count;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\tstruct dbs_data *dbs_data;\n\tstruct list_head list;\n\tunsigned int rate_mult;\n\tunsigned int idle_periods;\n\tbool is_shared;\n\tbool work_in_progress;\n};\n\nstruct od_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int freq_lo;\n\tunsigned int freq_lo_delay_us;\n\tunsigned int freq_hi_delay_us;\n\tunsigned int sample_type: 1;\n};\n\nstruct odmi_data {\n\tstruct resource res;\n\tvoid *base;\n\tunsigned int spi_base;\n};\n\nstruct of_bus {\n\tvoid (*count_cells)(const void *, int, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n};\n\nstruct of_bus___2 {\n\tconst char *name;\n\tconst char *addresses;\n\tint (*match)(struct device_node *);\n\tvoid (*count_cells)(struct device_node *, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n\tint flag_cells;\n\tunsigned int (*get_flags)(const __be32 *);\n};\n\nstruct of_changeset {\n\tstruct list_head entries;\n};\n\nstruct of_changeset_entry {\n\tstruct list_head node;\n\tlong unsigned int action;\n\tstruct device_node *np;\n\tstruct property *prop;\n\tstruct property *old_prop;\n};\n\nstruct of_clk_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n\tstruct clk * (*get)(struct of_phandle_args *, void *);\n\tstruct clk_hw * (*get_hw)(struct of_phandle_args *, void *);\n\tvoid *data;\n};\n\nstruct of_dev_auxdata {\n\tchar *compatible;\n\tresource_size_t phys_addr;\n\tchar *name;\n\tvoid *platform_data;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_dma {\n\tstruct list_head of_dma_controllers;\n\tstruct device_node *of_node;\n\tstruct dma_chan * (*of_dma_xlate)(struct of_phandle_args *, struct of_dma *);\n\tvoid * (*of_dma_route_allocate)(struct of_phandle_args *, struct of_dma *);\n\tstruct dma_router *dma_router;\n\tvoid *of_dma_data;\n};\n\nstruct of_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct of_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct device_node *local_node;\n};\n\nstruct of_genpd_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n\tgenpd_xlate_t xlate;\n\tvoid *data;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct of_imap_item {\n\tstruct of_phandle_args parent_args;\n\tu32 child_imap_count;\n\tu32 child_imap[16];\n};\n\nstruct of_imap_parser {\n\tstruct device_node *node;\n\tconst __be32 *imap;\n\tconst __be32 *imap_end;\n\tu32 parent_offset;\n};\n\ntypedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *);\n\nstruct of_intc_desc {\n\tstruct list_head list;\n\tof_irq_init_cb_t irq_init_cb;\n\tstruct device_node *dev;\n\tstruct device_node *interrupt_parent;\n};\n\nstruct of_mmc_spi {\n\tstruct mmc_spi_platform_data pdata;\n\tint detect_irq;\n};\n\nstruct of_overlay_notify_data {\n\tstruct device_node *overlay;\n\tstruct device_node *target;\n};\n\nstruct of_pci_iommu_alias_info {\n\tstruct device *dev;\n\tstruct device_node *np;\n};\n\nstruct of_pci_range {\n\tunion {\n\t\tu64 pci_addr;\n\t\tu64 bus_addr;\n\t};\n\tu64 cpu_addr;\n\tu64 parent_bus_addr;\n\tu64 size;\n\tu32 flags;\n};\n\nstruct of_pci_range_parser {\n\tstruct device_node *node;\n\tconst struct of_bus___2 *bus;\n\tconst __be32 *range;\n\tconst __be32 *end;\n\tint na;\n\tint ns;\n\tint pna;\n\tbool dma;\n};\n\nstruct of_phandle_iterator {\n\tconst char *cells_name;\n\tint cell_count;\n\tconst struct device_node *parent;\n\tconst __be32 *list_end;\n\tconst __be32 *phandle_end;\n\tconst __be32 *cur;\n\tuint32_t cur_count;\n\tphandle phandle;\n\tstruct device_node *node;\n};\n\nstruct of_reconfig_data {\n\tstruct device_node *dn;\n\tstruct property *prop;\n\tstruct property *old_prop;\n};\n\nstruct of_regulator_match {\n\tconst char *name;\n\tvoid *driver_data;\n\tstruct regulator_init_data *init_data;\n\tstruct device_node *of_node;\n\tconst struct regulator_desc *desc;\n};\n\nstruct of_rename_gpio {\n\tconst char *con_id;\n\tconst char *legacy_id;\n\tconst char *compatible;\n};\n\nstruct of_serial_info {\n\tstruct clk *clk;\n\tstruct clk *bus_clk;\n\tstruct reset_control *rst;\n\tint type;\n\tint line;\n\tstruct notifier_block clk_notifier;\n};\n\nstruct of_timer_base {\n\tvoid *base;\n\tconst char *name;\n\tint index;\n};\n\nstruct of_timer_clk {\n\tstruct clk *clk;\n\tconst char *name;\n\tint index;\n\tlong unsigned int rate;\n\tlong unsigned int period;\n};\n\nstruct of_timer_irq {\n\tint irq;\n\tint index;\n\tconst char *name;\n\tlong unsigned int flags;\n\tirq_handler_t handler;\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nstruct ohci_driver_overrides {\n\tconst char *product_desc;\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n};\n\nstruct ohci_hcca {\n\t__hc32 int_table[32];\n\t__hc32 frame_no;\n\t__hc32 done_head;\n\tu8 reserved_for_hc[116];\n\tu8 what[4];\n};\n\nstruct ohci_regs;\n\nstruct ohci_hcd {\n\tspinlock_t lock;\n\tstruct ohci_regs *regs;\n\tstruct ohci_hcca *hcca;\n\tdma_addr_t hcca_dma;\n\tstruct ed *ed_rm_list;\n\tstruct ed *ed_bulktail;\n\tstruct ed *ed_controltail;\n\tstruct ed *periodic[32];\n\tvoid (*start_hnp)(struct ohci_hcd *);\n\tstruct dma_pool *td_cache;\n\tstruct dma_pool *ed_cache;\n\tstruct td *td_hash[64];\n\tstruct td *dl_start;\n\tstruct td *dl_end;\n\tstruct list_head pending;\n\tstruct list_head eds_in_use;\n\tenum ohci_rh_state rh_state;\n\tint num_ports;\n\tint load[32];\n\tu32 hc_control;\n\tlong unsigned int next_statechange;\n\tu32 fminterval;\n\tunsigned int autostop: 1;\n\tunsigned int working: 1;\n\tunsigned int restart_work: 1;\n\tlong unsigned int flags;\n\tunsigned int prev_frame_no;\n\tunsigned int wdh_cnt;\n\tunsigned int prev_wdh_cnt;\n\tu32 prev_donehead;\n\tstruct timer_list io_watchdog;\n\tstruct work_struct nec_work;\n\tstruct dentry *debug_dir;\n\tlong unsigned int priv[0];\n};\n\nstruct ohci_platform_priv {\n\tstruct clk *clks[4];\n\tstruct reset_control *resets;\n};\n\nstruct ohci_roothub_regs {\n\t__hc32 a;\n\t__hc32 b;\n\t__hc32 status;\n\t__hc32 portstatus[15];\n};\n\nstruct ohci_regs {\n\t__hc32 revision;\n\t__hc32 control;\n\t__hc32 cmdstatus;\n\t__hc32 intrstatus;\n\t__hc32 intrenable;\n\t__hc32 intrdisable;\n\t__hc32 hcca;\n\t__hc32 ed_periodcurrent;\n\t__hc32 ed_controlhead;\n\t__hc32 ed_controlcurrent;\n\t__hc32 ed_bulkhead;\n\t__hc32 ed_bulkcurrent;\n\t__hc32 donehead;\n\t__hc32 fminterval;\n\t__hc32 fmremaining;\n\t__hc32 fmnumber;\n\t__hc32 periodicstart;\n\t__hc32 lsthresh;\n\tstruct ohci_roothub_regs roothub;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_itimerval32 {\n\tstruct old_timeval32 it_interval;\n\tstruct old_timeval32 it_value;\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n};\n\nstruct old_timex32 {\n\tu32 modes;\n\ts32 offset;\n\ts32 freq;\n\ts32 maxerror;\n\ts32 esterror;\n\ts32 status;\n\ts32 constant;\n\ts32 precision;\n\ts32 tolerance;\n\tstruct old_timeval32 time;\n\ts32 tick;\n\ts32 ppsfreq;\n\ts32 jitter;\n\ts32 shift;\n\ts32 stabil;\n\ts32 jitcnt;\n\ts32 calcnt;\n\ts32 errcnt;\n\ts32 stbcnt;\n\ts32 tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct old_utimbuf32 {\n\told_time32_t actime;\n\told_time32_t modtime;\n};\n\nstruct omap8250_dma_params {\n\tu32 rx_size;\n\tu8 rx_trigger;\n\tu8 tx_trigger;\n};\n\nstruct omap8250_platdata {\n\tstruct omap8250_dma_params *dma_params;\n\tu8 habit;\n};\n\nstruct omap8250_priv {\n\tvoid *membase;\n\tint line;\n\tu8 habit;\n\tu8 mdr1;\n\tu8 mdr3;\n\tu8 efr;\n\tu8 scr;\n\tu8 wer;\n\tu8 xon;\n\tu8 xoff;\n\tu8 delayed_restore;\n\tu16 quot;\n\tu8 tx_trigger;\n\tu8 rx_trigger;\n\tatomic_t active;\n\tbool is_suspending;\n\tint wakeirq;\n\tu32 latency;\n\tu32 calc_latency;\n\tstruct pm_qos_request pm_qos_request;\n\tstruct work_struct qos_work;\n\tstruct uart_8250_dma omap8250_dma;\n\tspinlock_t rx_dma_lock;\n\tbool rx_dma_broken;\n\tbool throttled;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pinctrl_wakeup;\n};\n\nstruct omap_dm_timer_ops {\n\tstruct omap_dm_timer * (*request_by_node)(struct device_node *);\n\tstruct omap_dm_timer * (*request_specific)(int);\n\tstruct omap_dm_timer * (*request)(void);\n\tint (*free)(struct omap_dm_timer *);\n\tvoid (*enable)(struct omap_dm_timer *);\n\tvoid (*disable)(struct omap_dm_timer *);\n\tint (*get_irq)(struct omap_dm_timer *);\n\tint (*set_int_enable)(struct omap_dm_timer *, unsigned int);\n\tint (*set_int_disable)(struct omap_dm_timer *, u32);\n\tstruct clk * (*get_fclk)(struct omap_dm_timer *);\n\tint (*start)(struct omap_dm_timer *);\n\tint (*stop)(struct omap_dm_timer *);\n\tint (*set_source)(struct omap_dm_timer *, int);\n\tint (*set_load)(struct omap_dm_timer *, unsigned int);\n\tint (*set_match)(struct omap_dm_timer *, int, unsigned int);\n\tint (*set_pwm)(struct omap_dm_timer *, int, int, int, int);\n\tint (*get_pwm_status)(struct omap_dm_timer *);\n\tint (*set_cap)(struct omap_dm_timer *, int, bool);\n\tint (*get_cap_status)(struct omap_dm_timer *);\n\tint (*set_prescaler)(struct omap_dm_timer *, int);\n\tunsigned int (*read_counter)(struct omap_dm_timer *);\n\tunsigned int (*read_cap)(struct omap_dm_timer *, bool);\n\tint (*write_counter)(struct omap_dm_timer *, unsigned int);\n\tunsigned int (*read_status)(struct omap_dm_timer *);\n\tint (*write_status)(struct omap_dm_timer *, unsigned int);\n};\n\nstruct omap_i2c_bus_platform_data {\n\tu32 clkrate;\n\tu32 rev;\n\tu32 flags;\n\tvoid (*set_mpu_wkup_lat)(struct device *, long int);\n};\n\nstruct omap_i2c_dev {\n\tstruct device *dev;\n\tvoid *base;\n\tint irq;\n\tint reg_shift;\n\tstruct completion cmd_complete;\n\tstruct resource *ioarea;\n\tu32 latency;\n\tvoid (*set_mpu_wkup_lat)(struct device *, long int);\n\tu32 speed;\n\tu32 flags;\n\tu16 scheme;\n\tu16 cmd_err;\n\tu8 *buf;\n\tu8 *regs;\n\tsize_t buf_len;\n\tstruct i2c_adapter adapter;\n\tu8 threshold;\n\tu8 fifo_size;\n\tu32 rev;\n\tunsigned int b_hw: 1;\n\tunsigned int bb_valid: 1;\n\tunsigned int receiver: 1;\n\tu16 iestate;\n\tu16 pscstate;\n\tu16 scllstate;\n\tu16 sclhstate;\n\tu16 syscstate;\n\tu16 westate;\n\tu16 errata;\n\tstruct mux_state *mux_state;\n};\n\nstruct omap_rng_pdata;\n\nstruct omap_rng_dev {\n\tvoid *base;\n\tstruct device *dev;\n\tconst struct omap_rng_pdata *pdata;\n\tstruct hwrng rng;\n\tstruct clk *clk;\n\tstruct clk *clk_reg;\n};\n\nstruct omap_rng_pdata {\n\tu16 *regs;\n\tu32 data_size;\n\tu32 (*data_present)(struct omap_rng_dev *);\n\tint (*init)(struct omap_rng_dev *);\n\tvoid (*cleanup)(struct omap_rng_dev *);\n};\n\nstruct onboard_dev_pdata {\n\tlong unsigned int reset_us;\n\tlong unsigned int power_on_delay_us;\n\tunsigned int num_supplies;\n\tconst char * const supply_names[2];\n\tbool is_hub;\n};\n\nstruct static_key_true;\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct onfi_ext_ecc_info {\n\tu8 ecc_bits;\n\tu8 codeword_size;\n\t__le16 bb_per_lun;\n\t__le16 block_endurance;\n\tu8 reserved[2];\n};\n\nstruct onfi_ext_section {\n\tu8 type;\n\tu8 length;\n};\n\nstruct onfi_ext_param_page {\n\t__le16 crc;\n\tu8 sig[4];\n\tu8 reserved0[10];\n\tstruct onfi_ext_section sections[8];\n};\n\nstruct onfi_params {\n\tint version;\n\tu16 tPROG;\n\tu16 tBERS;\n\tu16 tR;\n\tu16 tCCS;\n\tbool fast_tCAD;\n\tu16 sdr_timing_modes;\n\tu16 nvddr_timing_modes;\n\tu16 vendor_revision;\n\tu8 vendor[88];\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct opp_config_data {\n\tstruct opp_table *opp_table;\n\tunsigned int flags;\n\tunsigned int required_dev_index;\n};\n\nstruct opp_device {\n\tstruct list_head node;\n\tconst struct device *dev;\n\tstruct dentry *dentry;\n};\n\nstruct opp_table {\n\tstruct list_head node;\n\tstruct list_head lazy;\n\tstruct blocking_notifier_head head;\n\tstruct list_head dev_list;\n\tstruct list_head opp_list;\n\tstruct kref kref;\n\tstruct mutex lock;\n\tstruct device_node *np;\n\tlong unsigned int clock_latency_ns_max;\n\tunsigned int voltage_tolerance_v1;\n\tunsigned int parsed_static_opps;\n\tenum opp_table_access shared_opp;\n\tlong unsigned int current_rate_single_clk;\n\tstruct dev_pm_opp *current_opp;\n\tstruct dev_pm_opp *suspend_opp;\n\tstruct opp_table **required_opp_tables;\n\tstruct device **required_devs;\n\tunsigned int required_opp_count;\n\tunsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char *prop_name;\n\tconfig_clks_t config_clks;\n\tstruct clk **clks;\n\tstruct clk *clk;\n\tint clk_count;\n\tconfig_regulators_t config_regulators;\n\tstruct regulator **regulators;\n\tint regulator_count;\n\tstruct icc_path **paths;\n\tunsigned int path_count;\n\tbool enabled;\n\tbool is_genpd;\n\tstruct dentry *dentry;\n\tchar dentry_name[255];\n};\n\ntypedef void optee_invoke_fn(long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, struct arm_smccc_res *);\n\nstruct optee_pcpu;\n\nstruct optee_smc {\n\toptee_invoke_fn *invoke_fn;\n\tvoid *memremaped_shm;\n\tu32 sec_caps;\n\tunsigned int notif_irq;\n\tstruct optee_pcpu *optee_pcpu;\n\tstruct workqueue_struct *notif_pcpu_wq;\n\tstruct work_struct notif_pcpu_work;\n\tunsigned int notif_cpuhp_state;\n};\n\nstruct optee_ffa {\n\tstruct ffa_device *ffa_dev;\n\tu32 bottom_half_value;\n\tstruct mutex mutex;\n\tstruct rhashtable global_ids;\n\tstruct workqueue_struct *notif_wq;\n\tstruct work_struct notif_work;\n};\n\nstruct optee_shm_arg_cache {\n\tu32 flags;\n\tstruct mutex mutex;\n\tstruct list_head shm_args;\n};\n\nstruct optee_call_queue {\n\tstruct mutex mutex;\n\tstruct list_head waiters;\n\tint total_thread_count;\n\tint free_thread_count;\n\tint sys_thread_req_count;\n};\n\nstruct optee_notif {\n\tu_int max_key;\n\tspinlock_t lock;\n\tstruct list_head db;\n\tu_long *bitmap;\n};\n\nstruct tee_context;\n\nstruct optee_supp {\n\tstruct mutex mutex;\n\tstruct tee_context *ctx;\n\tint req_id;\n\tstruct list_head reqs;\n\tstruct idr idr;\n\tstruct completion reqs_c;\n};\n\nstruct optee_revision {\n\tu32 os_major;\n\tu32 os_minor;\n\tu64 os_build_id;\n};\n\nstruct tee_device;\n\nstruct optee_ops;\n\nstruct tee_shm_pool;\n\nstruct optee {\n\tstruct tee_device *supp_teedev;\n\tstruct tee_device *teedev;\n\tconst struct optee_ops *ops;\n\tstruct tee_context *ctx;\n\tunion {\n\t\tstruct optee_smc smc;\n\t\tstruct optee_ffa ffa;\n\t};\n\tstruct optee_shm_arg_cache shm_arg_cache;\n\tstruct optee_call_queue call_queue;\n\tstruct optee_notif notif;\n\tstruct optee_supp supp;\n\tstruct tee_shm_pool *pool;\n\tstruct mutex rpmb_dev_mutex;\n\tstruct rpmb_dev *rpmb_dev;\n\tstruct notifier_block rpmb_intf;\n\tunsigned int rpc_param_count;\n\tbool scan_bus_done;\n\tbool rpmb_scan_bus_done;\n\tbool in_kernel_rpmb_routing;\n\tstruct work_struct scan_bus_work;\n\tstruct work_struct rpmb_scan_bus_work;\n\tstruct optee_revision revision;\n};\n\nstruct optee_call_ctx {\n\tvoid *pages_list;\n\tsize_t num_entries;\n};\n\nstruct optee_call_waiter {\n\tstruct list_head list_node;\n\tstruct completion c;\n\tbool sys_thread;\n};\n\nstruct optee_context_data {\n\tstruct mutex mutex;\n\tstruct list_head sess_list;\n};\n\nstruct optee_msg_param_tmem {\n\tu64 buf_ptr;\n\tu64 size;\n\tu64 shm_ref;\n};\n\nstruct optee_msg_param_rmem {\n\tu64 offs;\n\tu64 size;\n\tu64 shm_ref;\n};\n\nstruct optee_msg_param_fmem {\n\tu32 offs_low;\n\tu16 offs_high;\n\tu16 internal_offs;\n\tu64 size;\n\tu64 global_id;\n};\n\nstruct optee_msg_param_value {\n\tu64 a;\n\tu64 b;\n\tu64 c;\n};\n\nstruct optee_msg_param {\n\tu64 attr;\n\tunion {\n\t\tstruct optee_msg_param_tmem tmem;\n\t\tstruct optee_msg_param_rmem rmem;\n\t\tstruct optee_msg_param_fmem fmem;\n\t\tstruct optee_msg_param_value value;\n\t\tu8 octets[24];\n\t} u;\n};\n\nstruct optee_msg_arg {\n\tu32 cmd;\n\tu32 func;\n\tu32 session;\n\tu32 cancel_id;\n\tu32 pad;\n\tu32 ret;\n\tu32 ret_origin;\n\tu32 num_params;\n\tstruct optee_msg_param params[0];\n};\n\nstruct tee_shm;\n\nstruct tee_param;\n\nstruct optee_ops {\n\tint (*do_call_with_arg)(struct tee_context *, struct tee_shm *, u_int, bool);\n\tint (*to_msg_param)(struct optee *, struct optee_msg_param *, size_t, const struct tee_param *);\n\tint (*from_msg_param)(struct optee *, struct tee_param *, size_t, const struct optee_msg_param *);\n\tint (*lend_protmem)(struct optee *, struct tee_shm *, u32 *, unsigned int, u32);\n\tint (*reclaim_protmem)(struct optee *, struct tee_shm *);\n};\n\nstruct optee_pcpu {\n\tstruct optee *optee;\n};\n\nstruct tee_protmem_pool_ops;\n\nstruct tee_protmem_pool {\n\tconst struct tee_protmem_pool_ops *ops;\n};\n\nstruct optee_protmem_dyn_pool {\n\tstruct tee_protmem_pool pool;\n\tstruct gen_pool *gen_pool;\n\tstruct optee *optee;\n\tsize_t page_count;\n\tu32 *mem_attrs;\n\tu_int mem_attr_count;\n\trefcount_t refcount;\n\tu32 use_case;\n\tstruct tee_shm *protmem;\n\tstruct mutex mutex;\n};\n\nstruct optee_rng_private {\n\tstruct device *dev;\n\tstruct tee_context *ctx;\n\tu32 session_id;\n\tu32 data_rate;\n\tstruct tee_shm *entropy_shm_pool;\n\tstruct hwrng optee_rng;\n};\n\nstruct optee_rpc_param {\n\tu32 a0;\n\tu32 a1;\n\tu32 a2;\n\tu32 a3;\n\tu32 a4;\n\tu32 a5;\n\tu32 a6;\n\tu32 a7;\n};\n\nstruct optee_session {\n\tstruct list_head list_node;\n\tu32 session_id;\n\tbool use_sys_thread;\n};\n\nstruct optee_shm_arg_entry {\n\tstruct list_head list_node;\n\tstruct tee_shm *shm;\n\tlong unsigned int map[1];\n};\n\nstruct optee_smc_call_get_os_revision_result {\n\tlong unsigned int major;\n\tlong unsigned int minor;\n\tlong unsigned int build_id;\n\tlong unsigned int reserved1;\n};\n\nstruct optee_smc_calls_revision_result {\n\tlong unsigned int major;\n\tlong unsigned int minor;\n\tlong unsigned int reserved0;\n\tlong unsigned int reserved1;\n};\n\nstruct optee_smc_disable_shm_cache_result {\n\tlong unsigned int status;\n\tlong unsigned int shm_upper32;\n\tlong unsigned int shm_lower32;\n\tlong unsigned int reserved0;\n};\n\nstruct optee_smc_exchange_capabilities_result {\n\tlong unsigned int status;\n\tlong unsigned int capabilities;\n\tlong unsigned int max_notif_value;\n\tlong unsigned int data;\n};\n\nstruct optee_smc_get_shm_config_result {\n\tlong unsigned int status;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int settings;\n};\n\nstruct optee_supp_req {\n\tstruct list_head link;\n\tbool in_queue;\n\tu32 func;\n\tu32 ret;\n\tsize_t num_params;\n\tstruct tee_param *param;\n\tstruct completion c;\n};\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct orion_direct_acc {\n\tvoid *vaddr;\n\tu32 size;\n};\n\nstruct orion_child_options {\n\tstruct orion_direct_acc direct_access;\n};\n\nstruct orion_ehci_data {\n\tenum orion_ehci_phy_ver phy_version;\n};\n\nstruct orion_ehci_hcd {\n\tstruct clk *clk;\n\tstruct phy *phy;\n};\n\nstruct orion_mdio_dev {\n\tvoid *regs;\n\tstruct clk *clk[4];\n\tint err_interrupt;\n\twait_queue_head_t smi_busy_wait;\n};\n\nstruct orion_mdio_ops {\n\tint (*is_done)(struct orion_mdio_dev *);\n};\n\nstruct orion_spi_dev;\n\nstruct orion_spi {\n\tstruct spi_controller *host;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *axi_clk;\n\tconst struct orion_spi_dev *devdata;\n\tstruct device *dev;\n\tstruct orion_child_options child[8];\n};\n\nstruct orion_spi_dev {\n\tenum orion_spi_type typ;\n\tlong unsigned int max_hz;\n\tunsigned int min_divisor;\n\tunsigned int max_divisor;\n\tu32 prescale_mask;\n\tbool is_errata_50mhz_ac;\n};\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\nstruct osnoise_entry {\n\tstruct trace_entry ent;\n\tu64 noise;\n\tu64 runtime;\n\tu64 max_sample;\n\tunsigned int hw_count;\n\tunsigned int nmi_count;\n\tunsigned int irq_count;\n\tunsigned int softirq_count;\n\tunsigned int thread_count;\n};\n\nstruct otg_fsm_ops {\n\tvoid (*chrg_vbus)(struct otg_fsm *, int);\n\tvoid (*drv_vbus)(struct otg_fsm *, int);\n\tvoid (*loc_conn)(struct otg_fsm *, int);\n\tvoid (*loc_sof)(struct otg_fsm *, int);\n\tvoid (*start_pulse)(struct otg_fsm *);\n\tvoid (*start_adp_prb)(struct otg_fsm *);\n\tvoid (*start_adp_sns)(struct otg_fsm *);\n\tvoid (*add_timer)(struct otg_fsm *, enum otg_fsm_timer);\n\tvoid (*del_timer)(struct otg_fsm *, enum otg_fsm_timer);\n\tint (*start_host)(struct otg_fsm *, int);\n\tint (*start_gadget)(struct otg_fsm *, int);\n};\n\nstruct otg_switch_mtk {\n\tstruct regulator *vbus;\n\tstruct extcon_dev *edev;\n\tstruct notifier_block id_nb;\n\tstruct work_struct dr_work;\n\tenum usb_role desired_role;\n\tenum usb_role default_role;\n\tstruct usb_role_switch *role_sw;\n\tbool role_sw_used;\n\tbool is_u3_drd;\n\tbool manual_drd_enabled;\n};\n\nstruct otp_info {\n\t__u32 start;\n\t__u32 length;\n\t__u32 locked;\n};\n\nstruct otpc_map {\n\tu32 otpc_row_size;\n\tu16 data_r_offset[4];\n\tu16 data_w_offset[4];\n};\n\nstruct otpc_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tconst struct otpc_map *map;\n\tstruct nvmem_config *config;\n};\n\nstruct out_pin {\n\tu32 enable_mask;\n\tu32 value_mask;\n\tu32 changed_mask;\n\tu32 clr_changed_mask;\n\tstruct gpio_desc *gpiod;\n\tconst char *name;\n};\n\nstruct overlay_changeset {\n\tint id;\n\tstruct list_head ovcs_list;\n\tconst void *new_fdt;\n\tconst void *overlay_mem;\n\tstruct device_node *overlay_root;\n\tenum of_overlay_notify_action notify_state;\n\tint count;\n\tstruct fragment *fragments;\n\tbool symbols_fragment;\n\tstruct of_changeset cset;\n};\n\nstruct owl_clk_common {\n\tstruct regmap *regmap;\n\tstruct clk_hw hw;\n};\n\nstruct owl_reset_map;\n\nstruct owl_clk_desc {\n\tstruct owl_clk_common **clks;\n\tlong unsigned int num_clks;\n\tstruct clk_hw_onecell_data *hw_clks;\n\tconst struct owl_reset_map *resets;\n\tlong unsigned int num_resets;\n\tstruct regmap *regmap;\n};\n\nstruct owl_mux_hw {\n\tu32 reg;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct owl_gate_hw {\n\tu32 reg;\n\tu8 bit_idx;\n\tu8 gate_flags;\n};\n\nstruct owl_divider_hw {\n\tu32 reg;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tstruct clk_div_table *table;\n};\n\nstruct owl_factor_hw {\n\tu32 reg;\n\tu8 shift;\n\tu8 width;\n\tu8 fct_flags;\n\tstruct clk_factor_table *table;\n};\n\nunion owl_rate {\n\tstruct owl_divider_hw div_hw;\n\tstruct owl_factor_hw factor_hw;\n\tstruct clk_fixed_factor fix_fact_hw;\n};\n\nstruct owl_composite {\n\tstruct owl_mux_hw mux_hw;\n\tstruct owl_gate_hw gate_hw;\n\tunion owl_rate rate;\n\tconst struct clk_ops *fix_fact_ops;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_divider {\n\tstruct owl_divider_hw div_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_dma_pchan;\n\nstruct owl_dma_vchan;\n\nstruct owl_dma {\n\tstruct dma_device dma;\n\tvoid *base;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tstruct dma_pool *lli_pool;\n\tint irq;\n\tunsigned int nr_pchans;\n\tstruct owl_dma_pchan *pchans;\n\tunsigned int nr_vchans;\n\tstruct owl_dma_vchan *vchans;\n\tenum owl_dma_id devid;\n};\n\nstruct owl_dma_lli {\n\tu32 hw[9];\n\tdma_addr_t phys;\n\tstruct list_head node;\n};\n\nstruct owl_dma_pchan {\n\tu32 id;\n\tvoid *base;\n\tstruct owl_dma_vchan *vchan;\n};\n\nstruct owl_dma_txd {\n\tstruct virt_dma_desc vd;\n\tstruct list_head lli_list;\n\tbool cyclic;\n};\n\nstruct owl_dma_vchan {\n\tstruct virt_dma_chan vc;\n\tstruct owl_dma_pchan *pchan;\n\tstruct owl_dma_txd *txd;\n\tstruct dma_slave_config cfg;\n\tu8 drq;\n};\n\nstruct owl_factor {\n\tstruct owl_factor_hw factor_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_gate {\n\tstruct owl_gate_hw gate_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_gpio_port {\n\tunsigned int offset;\n\tunsigned int pins;\n\tunsigned int outen;\n\tunsigned int inen;\n\tunsigned int dat;\n\tunsigned int intc_ctl;\n\tunsigned int intc_pd;\n\tunsigned int intc_msk;\n\tunsigned int intc_type;\n\tu8 shared_ctl_offset;\n};\n\nstruct owl_i2c_dev {\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *msg;\n\tstruct completion msg_complete;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tvoid *base;\n\tlong unsigned int clk_rate;\n\tu32 bus_freq;\n\tu32 msg_ptr;\n\tint err;\n};\n\nstruct owl_mmc_host {\n\tstruct device *dev;\n\tstruct reset_control *reset;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct completion sdc_complete;\n\tspinlock_t lock;\n\tint irq;\n\tu32 clock;\n\tbool ddr_50;\n\tenum dma_data_direction dma_dir;\n\tstruct dma_chan *dma;\n\tstruct dma_async_tx_descriptor *desc;\n\tstruct dma_slave_config dma_cfg;\n\tstruct completion dma_complete;\n\tstruct mmc_host *mmc;\n\tstruct mmc_request *mrq;\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n};\n\nstruct owl_mux {\n\tstruct owl_mux_hw mux_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_pullctl;\n\nstruct owl_st;\n\nstruct owl_padinfo {\n\tint pad;\n\tstruct owl_pullctl *pullctl;\n\tstruct owl_st *st;\n};\n\nstruct owl_pinctrl_soc_data;\n\nstruct owl_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctrldev;\n\tstruct gpio_chip chip;\n\traw_spinlock_t lock;\n\tstruct clk *clk;\n\tconst struct owl_pinctrl_soc_data *soc;\n\tvoid *base;\n\tunsigned int num_irq;\n\tunsigned int *irq;\n};\n\nstruct owl_pinmux_func;\n\nstruct owl_pingroup;\n\nstruct owl_pinctrl_soc_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct owl_pinmux_func *functions;\n\tunsigned int nfunctions;\n\tconst struct owl_pingroup *groups;\n\tunsigned int ngroups;\n\tconst struct owl_padinfo *padinfo;\n\tunsigned int ngpios;\n\tconst struct owl_gpio_port *ports;\n\tunsigned int nports;\n\tint (*padctl_val2arg)(const struct owl_padinfo *, unsigned int, u32 *);\n\tint (*padctl_arg2val)(const struct owl_padinfo *, unsigned int, u32 *);\n};\n\nstruct owl_pingroup {\n\tconst char *name;\n\tunsigned int *pads;\n\tunsigned int npads;\n\tunsigned int *funcs;\n\tunsigned int nfuncs;\n\tint mfpctl_reg;\n\tunsigned int mfpctl_shift;\n\tunsigned int mfpctl_width;\n\tint drv_reg;\n\tunsigned int drv_shift;\n\tunsigned int drv_width;\n\tint sr_reg;\n\tunsigned int sr_shift;\n\tunsigned int sr_width;\n};\n\nstruct owl_pinmux_func {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct owl_pll_hw {\n\tu32 reg;\n\tu32 bfreq;\n\tu8 bit_idx;\n\tu8 shift;\n\tu8 width;\n\tu8 min_mul;\n\tu8 max_mul;\n\tu8 delay;\n\tconst struct clk_pll_table *table;\n};\n\nstruct owl_pll {\n\tstruct owl_pll_hw pll_hw;\n\tstruct owl_clk_common common;\n};\n\nstruct owl_pullctl {\n\tint reg;\n\tunsigned int shift;\n\tunsigned int width;\n};\n\nstruct owl_reset {\n\tstruct reset_controller_dev rcdev;\n\tconst struct owl_reset_map *reset_map;\n\tstruct regmap *regmap;\n};\n\nstruct owl_reset_map {\n\tu32 reg;\n\tu32 bit;\n};\n\nstruct owl_sirq_params;\n\nstruct owl_sirq_chip_data {\n\tconst struct owl_sirq_params *params;\n\tvoid *base;\n\traw_spinlock_t lock;\n\tu32 ext_irqs[3];\n};\n\nstruct owl_sirq_params {\n\tbool reg_shared;\n\tu16 reg_offset[3];\n};\n\nstruct owl_sps_info;\n\nstruct owl_sps {\n\tstruct device *dev;\n\tconst struct owl_sps_info *info;\n\tvoid *base;\n\tstruct genpd_onecell_data genpd_data;\n\tstruct generic_pm_domain *domains[0];\n};\n\nstruct owl_sps_domain_info;\n\nstruct owl_sps_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct owl_sps_domain_info *info;\n\tstruct owl_sps *sps;\n};\n\nstruct owl_sps_domain_info {\n\tconst char *name;\n\tint pwr_bit;\n\tint ack_bit;\n\tunsigned int genpd_flags;\n};\n\nstruct owl_sps_info {\n\tunsigned int num_domains;\n\tconst struct owl_sps_domain_info *domains;\n};\n\nstruct owl_st {\n\tint reg;\n\tunsigned int shift;\n\tunsigned int width;\n};\n\nstruct owl_uart_info {\n\tunsigned int tx_fifosize;\n};\n\nstruct owl_uart_port {\n\tstruct uart_port port;\n\tstruct clk *clk;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tu64 bus_offset;\n};\n\nstruct p9_trans_module;\n\nstruct p9_client {\n\tspinlock_t lock;\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n\tenum p9_trans_status status;\n\tvoid *trans;\n\tstruct kmem_cache *fcall_cache;\n\tunion {\n\t\tstruct {\n\t\t\tint rfd;\n\t\t\tint wfd;\n\t\t} fd;\n\t\tstruct {\n\t\t\tu16 port;\n\t\t\tbool privport;\n\t\t} tcp;\n\t} trans_opts;\n\tstruct idr fids;\n\tstruct idr reqs;\n\tchar name[65];\n};\n\nstruct p9_client_opts {\n\tunsigned int msize;\n\tunsigned char proto_version;\n\tstruct p9_trans_module *trans_mod;\n};\n\nstruct p9_fcall {\n\tu32 size;\n\tu8 id;\n\tu16 tag;\n\tsize_t offset;\n\tsize_t capacity;\n\tstruct kmem_cache *cache;\n\tu8 *sdata;\n\tbool zc;\n};\n\nstruct p9_conn;\n\nstruct p9_poll_wait {\n\tstruct p9_conn *conn;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_addr;\n};\n\nstruct p9_req_t;\n\nstruct p9_conn {\n\tstruct list_head mux_list;\n\tstruct p9_client *client;\n\tint err;\n\tspinlock_t req_lock;\n\tstruct list_head req_list;\n\tstruct list_head unsent_req_list;\n\tstruct p9_req_t *rreq;\n\tstruct p9_req_t *wreq;\n\tchar tmp_buf[7];\n\tstruct p9_fcall rc;\n\tint wpos;\n\tint wsize;\n\tchar *wbuf;\n\tstruct list_head poll_pending_link;\n\tstruct p9_poll_wait poll_wait[2];\n\tpoll_table pt;\n\tstruct work_struct rq;\n\tstruct work_struct wq;\n\tlong unsigned int wsched;\n};\n\nstruct p9_qid {\n\tu8 type;\n\tu32 version;\n\tu64 path;\n};\n\nstruct p9_dirent {\n\tstruct p9_qid qid;\n\tu64 d_off;\n\tunsigned char d_type;\n\tchar d_name[256];\n};\n\nstruct p9_fd_opts {\n\tint rfd;\n\tint wfd;\n\tu16 port;\n\tbool privport;\n};\n\nstruct p9_fid {\n\tstruct p9_client *clnt;\n\tu32 fid;\n\trefcount_t count;\n\tint mode;\n\tstruct p9_qid qid;\n\tu32 iounit;\n\tkuid_t uid;\n\tvoid *rdir;\n\tstruct hlist_node dlist;\n\tstruct hlist_node ilist;\n};\n\nstruct p9_flock {\n\tu8 type;\n\tu32 flags;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_getlock {\n\tu8 type;\n\tu64 start;\n\tu64 length;\n\tu32 proc_id;\n\tchar *client_id;\n};\n\nstruct p9_iattr_dotl {\n\tu32 valid;\n\tu32 mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tu64 size;\n\tu64 atime_sec;\n\tu64 atime_nsec;\n\tu64 mtime_sec;\n\tu64 mtime_nsec;\n};\n\nstruct p9_rdir {\n\tint head;\n\tint tail;\n\tuint8_t buf[0];\n};\n\nstruct p9_rdma_opts {\n\tshort int port;\n\tbool privport;\n\tint sq_depth;\n\tint rq_depth;\n\tlong int timeout;\n};\n\nstruct p9_req_t {\n\tint status;\n\tint t_err;\n\trefcount_t refcount;\n\twait_queue_head_t wq;\n\tstruct p9_fcall tc;\n\tstruct p9_fcall rc;\n\tstruct list_head req_list;\n};\n\nstruct p9_rstatfs {\n\tu32 type;\n\tu32 bsize;\n\tu64 blocks;\n\tu64 bfree;\n\tu64 bavail;\n\tu64 files;\n\tu64 ffree;\n\tu64 fsid;\n\tu32 namelen;\n};\n\nstruct p9_session_opts {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tlong int session_lock_timeout;\n};\n\nstruct p9_stat_dotl {\n\tu64 st_result_mask;\n\tstruct p9_qid qid;\n\tu32 st_mode;\n\tkuid_t st_uid;\n\tkgid_t st_gid;\n\tu64 st_nlink;\n\tu64 st_rdev;\n\tu64 st_size;\n\tu64 st_blksize;\n\tu64 st_blocks;\n\tu64 st_atime_sec;\n\tu64 st_atime_nsec;\n\tu64 st_mtime_sec;\n\tu64 st_mtime_nsec;\n\tu64 st_ctime_sec;\n\tu64 st_ctime_nsec;\n\tu64 st_btime_sec;\n\tu64 st_btime_nsec;\n\tu64 st_gen;\n\tu64 st_data_version;\n};\n\nstruct p9_trans_fd {\n\tstruct file *rd;\n\tstruct file *wr;\n\tstruct p9_conn conn;\n};\n\nstruct p9_trans_module {\n\tstruct list_head list;\n\tchar *name;\n\tint maxsize;\n\tbool pooled_rbuffers;\n\tbool def;\n\tbool supports_vmalloc;\n\tstruct module *owner;\n\tint (*create)(struct p9_client *, struct fs_context *);\n\tvoid (*close)(struct p9_client *);\n\tint (*request)(struct p9_client *, struct p9_req_t *);\n\tint (*cancel)(struct p9_client *, struct p9_req_t *);\n\tint (*cancelled)(struct p9_client *, struct p9_req_t *);\n\tint (*zc_request)(struct p9_client *, struct p9_req_t *, struct iov_iter *, struct iov_iter *, int, int, int);\n\tint (*show_options)(struct seq_file *, struct p9_client *);\n};\n\nstruct p9_wstat {\n\tu16 size;\n\tu16 type;\n\tu32 dev;\n\tstruct p9_qid qid;\n\tu32 mode;\n\tu32 atime;\n\tu32 mtime;\n\tu64 length;\n\tconst char *name;\n\tconst char *uid;\n\tconst char *gid;\n\tconst char *muid;\n\tchar *extension;\n\tkuid_t n_uid;\n\tkgid_t n_gid;\n\tkuid_t n_muid;\n};\n\nstruct pacct_struct {\n\tint ac_flag;\n\tlong int ac_exitcode;\n\tlong unsigned int ac_mem;\n\tu64 ac_utime;\n\tu64 ac_stime;\n\tlong unsigned int ac_minflt;\n\tlong unsigned int ac_majflt;\n};\n\nstruct packed_field_u16 {\n\tu16 startbit;\n\tu16 endbit;\n\tu16 offset;\n\tu16 size;\n};\n\nstruct packed_field_u8 {\n\tu8 startbit;\n\tu8 endbit;\n\tu8 offset;\n\tu8 size;\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 history[16];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t tp_drops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct padata_cpumask {\n\tcpumask_var_t pcpu;\n\tcpumask_var_t cbcpu;\n};\n\nstruct padata_instance {\n\tstruct hlist_node cpu_online_node;\n\tstruct hlist_node cpu_dead_node;\n\tstruct workqueue_struct *parallel_wq;\n\tstruct workqueue_struct *serial_wq;\n\tstruct list_head pslist;\n\tstruct padata_cpumask cpumask;\n\tstruct kobject kobj;\n\tstruct mutex lock;\n\tu8 flags;\n};\n\nstruct padata_list {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct padata_mt_job {\n\tvoid (*thread_fn)(long unsigned int, long unsigned int, void *);\n\tvoid *fn_arg;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int min_chunk;\n\tint max_threads;\n\tbool numa_aware;\n};\n\nstruct padata_mt_job_state {\n\tspinlock_t lock;\n\tstruct completion completion;\n\tstruct padata_mt_job *job;\n\tint nworks;\n\tint nworks_fini;\n\tlong unsigned int chunk_size;\n};\n\nstruct parallel_data;\n\nstruct padata_priv {\n\tstruct list_head list;\n\tstruct parallel_data *pd;\n\tint cb_cpu;\n\tunsigned int seq_nr;\n\tint info;\n\tvoid (*parallel)(struct padata_priv *);\n\tvoid (*serial)(struct padata_priv *);\n};\n\nstruct padata_serial_queue {\n\tstruct padata_list serial;\n\tstruct work_struct work;\n\tstruct parallel_data *pd;\n};\n\nstruct padata_shell {\n\tstruct padata_instance *pinst;\n\tstruct parallel_data *pd;\n\tstruct parallel_data *opd;\n\tstruct list_head list;\n};\n\nstruct padata_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct padata_instance *, const struct attribute *, char *);\n\tssize_t (*store)(struct padata_instance *, const struct attribute *, const char *, size_t);\n};\n\nstruct padata_work {\n\tstruct work_struct pw_work;\n\tstruct list_head pw_list;\n\tvoid *pw_data;\n};\n\ntypedef struct page *pgtable_t;\n\nstruct page_change_data {\n\tpgprot_t set_mask;\n\tpgprot_t clear_mask;\n};\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct page_pool_alloc_stats {\n\tu64 fast;\n\tu64 slow;\n\tu64 slow_high_order;\n\tu64 empty;\n\tu64 refill;\n\tu64 waive;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool_recycle_stats;\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tbool system: 1;\n\tlong: 0;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\tlong: 0;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tstruct page_pool_alloc_stats alloc_stats;\n\tu32 xdp_mem_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pp_alloc_cache alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tstruct page_pool_recycle_stats *recycle_stats;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t} user;\n\tlong: 64;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_pool_recycle_stats {\n\tu64 cached;\n\tu64 cache_full;\n\tu64 ring;\n\tu64 ring_full;\n\tu64 released_refcnt;\n};\n\nstruct page_pool_stats {\n\tstruct page_pool_alloc_stats alloc_stats;\n\tstruct page_pool_recycle_stats recycle_stats;\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_reporting_dev_info {\n\tint (*report)(struct page_reporting_dev_info *, struct scatterlist *, unsigned int);\n\tstruct delayed_work work;\n\tatomic_t state;\n\tunsigned int order;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n\tlong: 64;\n};\n\nstruct page_state {\n\tlong unsigned int mask;\n\tlong unsigned int res;\n\tenum mf_action_page_type type;\n\tint (*action)(struct page_state *, struct page *);\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct parallel_data {\n\tstruct padata_shell *ps;\n\tstruct padata_list *reorder_list;\n\tstruct padata_serial_queue *squeue;\n\trefcount_t refcnt;\n\tunsigned int seq_nr;\n\tunsigned int processed;\n\tint cpu;\n\tstruct padata_cpumask cpumask;\n};\n\nstruct parent_map {\n\tu8 src;\n\tu8 cfg;\n};\n\nstruct parents_resp {\n\tu32 parents[3];\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct partition_affinity {\n\tcpumask_t mask;\n\tstruct fwnode_handle *partition_id;\n};\n\nstruct pata_platform_info {\n\tunsigned int ioport_shift;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct pbe {\n\tvoid *address;\n\tvoid *orig_address;\n\tstruct pbe *next;\n};\n\nstruct pc9450_dvs_config {\n\tunsigned int run_reg;\n\tunsigned int run_mask;\n\tunsigned int standby_reg;\n\tunsigned int standby_mask;\n\tunsigned int mode_reg;\n\tunsigned int mode_mask;\n};\n\nstruct pca9450 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct gpio_desc *sd_vsel_gpio;\n\tenum pca9450_chip_type type;\n\tunsigned int rcnt;\n\tint irq;\n\tbool sd_vsel_fixed_low;\n};\n\nstruct pca9450_regulator_desc {\n\tstruct regulator_desc desc;\n\tconst struct pc9450_dvs_config dvs;\n};\n\nstruct pca953x_reg_config;\n\nstruct pca953x_chip {\n\tunsigned int gpio_start;\n\tstruct mutex i2c_lock;\n\tstruct regmap *regmap;\n\tstruct mutex irq_lock;\n\tlong unsigned int irq_mask[1];\n\tlong unsigned int irq_stat[1];\n\tlong unsigned int irq_trig_raise[1];\n\tlong unsigned int irq_trig_fall[1];\n\tlong unsigned int irq_trig_level_high[1];\n\tlong unsigned int irq_trig_level_low[1];\n\tatomic_t wakeup_path;\n\tstruct i2c_client *client;\n\tstruct gpio_chip gpio_chip;\n\tlong unsigned int driver_data;\n\tstruct regulator *regulator;\n\tconst struct pca953x_reg_config *regs;\n\tu8 (*recalc_addr)(struct pca953x_chip *, int, int);\n\tbool (*check_reg)(struct pca953x_chip *, unsigned int, u32);\n};\n\nstruct pca953x_platform_data {\n\tunsigned int gpio_base;\n\tint irq_base;\n};\n\nstruct pca953x_reg_config {\n\tint direction;\n\tint output;\n\tint input;\n\tint invert;\n};\n\nstruct pca954x {\n\tconst struct chip_desc *chip;\n\tu8 last_chan;\n\ts32 idle_state;\n\tstruct i2c_client *client;\n\tstruct irq_domain *irq;\n\tunsigned int irq_mask;\n\traw_spinlock_t lock;\n\tstruct regulator *supply;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_cont;\n};\n\nstruct pcc_mbox_chan {\n\tstruct mbox_chan *mchan;\n\tu64 shmem_base_addr;\n\tvoid *shmem;\n\tu64 shmem_size;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n};\n\nstruct pcc_chan_reg {\n\tvoid *vaddr;\n\tstruct acpi_generic_address *gas;\n\tu64 preserve_mask;\n\tu64 set_mask;\n\tu64 status_mask;\n};\n\nstruct pcc_chan_info {\n\tstruct pcc_mbox_chan chan;\n\tstruct pcc_chan_reg db;\n\tstruct pcc_chan_reg plat_irq_ack;\n\tstruct pcc_chan_reg cmd_complete;\n\tstruct pcc_chan_reg cmd_update;\n\tstruct pcc_chan_reg error;\n\tint plat_irq;\n\tu8 type;\n\tunsigned int plat_irq_flags;\n\tbool chan_in_use;\n};\n\nstruct pcc_data {\n\tstruct pcc_mbox_chan *pcc_chan;\n\tstruct completion done;\n\tstruct mbox_client cl;\n\tstruct acpi_pcc_info ctx;\n};\n\nstruct pcc_reset_dev {\n\tvoid *base;\n\tstruct reset_controller_dev rcdev;\n\tconst u32 *resets;\n\tspinlock_t *lock;\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nstruct pci_bridge_emul_ops {\n\tpci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *, int, u32 *);\n\tpci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *, int, u32 *);\n\tpci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *, int, u32 *);\n\tvoid (*write_base)(struct pci_bridge_emul *, int, u32, u32, u32);\n\tvoid (*write_pcie)(struct pci_bridge_emul *, int, u32, u32, u32);\n\tvoid (*write_ext)(struct pci_bridge_emul *, int, u32, u32, u32);\n};\n\nstruct pci_bridge_reg_behavior {\n\tu32 ro;\n\tu32 rw;\n\tu32 w1c;\n};\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tint domain_nr;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_config_window {\n\tstruct resource res;\n\tstruct resource busr;\n\tunsigned int bus_shift;\n\tvoid *priv;\n\tconst struct pci_ecam_ops *ops;\n\tunion {\n\t\tvoid *win;\n\t\tvoid **winp;\n\t};\n\tstruct device *parent;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct rcec_ea;\n\nstruct pcie_link_state;\n\nstruct pcie_bwctrl_data;\n\nstruct pci_sriov;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tu16 aer_cap;\n\tstruct aer_info *aer_info;\n\tstruct rcec_ea *rcec_ea;\n\tstruct pci_dev *rcec;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tstruct pcie_link_state *link_state;\n\tunsigned int aspm_l0s_support: 1;\n\tunsigned int aspm_l1_support: 1;\n\tunsigned int ltr_path: 1;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[17];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[17];\n\tstruct bin_attribute *res_attr_wc[17];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tunion {\n\t\tstruct pci_sriov *sriov;\n\t\tstruct pci_dev *physfn;\n\t};\n\tu16 ats_cap;\n\tu8 ats_stu;\n\tu16 pasid_cap;\n\tu16 pasid_features;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct physdev_pci_device {\n\tuint16_t seg;\n\tuint8_t bus;\n\tuint8_t devfn;\n};\n\nstruct pci_device_reset {\n\tstruct physdev_pci_device dev;\n\tuint32_t flags;\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_ecam_ops {\n\tunsigned int bus_shift;\n\tstruct pci_ops pci_ops;\n\tint (*init)(struct pci_config_window *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n};\n\nstruct pci_epc_ops;\n\nstruct pci_epc_mem;\n\nstruct pci_epc {\n\tstruct device dev;\n\tstruct list_head pci_epf;\n\tstruct mutex list_lock;\n\tconst struct pci_epc_ops *ops;\n\tstruct pci_epc_mem **windows;\n\tstruct pci_epc_mem *mem;\n\tunsigned int num_windows;\n\tu8 max_functions;\n\tu8 *max_vfs;\n\tstruct config_group *group;\n\tstruct mutex lock;\n\tlong unsigned int function_num_map;\n\tint domain_nr;\n\tbool init_complete;\n};\n\nstruct pci_epc_bar_desc {\n\tenum pci_epc_bar_type type;\n\tu64 fixed_size;\n\tbool only_64bit;\n};\n\nstruct pci_epf;\n\nstruct pci_epc_event_ops {\n\tint (*epc_init)(struct pci_epf *);\n\tvoid (*epc_deinit)(struct pci_epf *);\n\tint (*link_up)(struct pci_epf *);\n\tint (*link_down)(struct pci_epf *);\n\tint (*bus_master_enable)(struct pci_epf *);\n};\n\nstruct pci_epc_features {\n\tunsigned int linkup_notifier: 1;\n\tunsigned int dynamic_inbound_mapping: 1;\n\tunsigned int subrange_mapping: 1;\n\tunsigned int msi_capable: 1;\n\tunsigned int msix_capable: 1;\n\tunsigned int intx_capable: 1;\n\tstruct pci_epc_bar_desc bar[6];\n\tsize_t align;\n};\n\nstruct pci_epc_group {\n\tstruct config_group group;\n\tstruct pci_epc *epc;\n\tbool start;\n};\n\nstruct pci_epc_map {\n\tu64 pci_addr;\n\tsize_t pci_size;\n\tu64 map_pci_addr;\n\tsize_t map_size;\n\tphys_addr_t phys_base;\n\tphys_addr_t phys_addr;\n\tvoid *virt_base;\n\tvoid *virt_addr;\n};\n\nstruct pci_epc_mem_window {\n\tphys_addr_t phys_base;\n\tsize_t size;\n\tsize_t page_size;\n};\n\nstruct pci_epc_mem {\n\tstruct pci_epc_mem_window window;\n\tlong unsigned int *bitmap;\n\tint pages;\n\tstruct mutex lock;\n};\n\nstruct pci_epf_header;\n\nstruct pci_epc_ops {\n\tint (*write_header)(struct pci_epc *, u8, u8, struct pci_epf_header *);\n\tint (*set_bar)(struct pci_epc *, u8, u8, struct pci_epf_bar *);\n\tvoid (*clear_bar)(struct pci_epc *, u8, u8, struct pci_epf_bar *);\n\tu64 (*align_addr)(struct pci_epc *, u64, size_t *, size_t *);\n\tint (*map_addr)(struct pci_epc *, u8, u8, phys_addr_t, u64, size_t);\n\tvoid (*unmap_addr)(struct pci_epc *, u8, u8, phys_addr_t);\n\tint (*set_msi)(struct pci_epc *, u8, u8, u8);\n\tint (*get_msi)(struct pci_epc *, u8, u8);\n\tint (*set_msix)(struct pci_epc *, u8, u8, u16, enum pci_barno, u32);\n\tint (*get_msix)(struct pci_epc *, u8, u8);\n\tint (*raise_irq)(struct pci_epc *, u8, u8, unsigned int, u16);\n\tint (*map_msi_irq)(struct pci_epc *, u8, u8, phys_addr_t, u8, u32, u32 *, u32 *);\n\tint (*start)(struct pci_epc *);\n\tvoid (*stop)(struct pci_epc *);\n\tconst struct pci_epc_features * (*get_features)(struct pci_epc *, u8, u8);\n\tstruct module *owner;\n};\n\nstruct pci_epf_bar_submap;\n\nstruct pci_epf_bar {\n\tdma_addr_t phys_addr;\n\tvoid *addr;\n\tsize_t size;\n\tsize_t mem_size;\n\tenum pci_barno barno;\n\tint flags;\n\tunsigned int num_submap;\n\tstruct pci_epf_bar_submap *submap;\n};\n\nstruct pci_epf_driver;\n\nstruct pci_epf_device_id;\n\nstruct pci_epf_doorbell_msg;\n\nstruct pci_epf {\n\tstruct device dev;\n\tconst char *name;\n\tstruct pci_epf_header *header;\n\tstruct pci_epf_bar bar[6];\n\tu8 msi_interrupts;\n\tu16 msix_interrupts;\n\tu8 func_no;\n\tu8 vfunc_no;\n\tstruct pci_epc *epc;\n\tstruct pci_epf *epf_pf;\n\tstruct pci_epf_driver *driver;\n\tconst struct pci_epf_device_id *id;\n\tstruct list_head list;\n\tstruct mutex lock;\n\tstruct pci_epc *sec_epc;\n\tstruct list_head sec_epc_list;\n\tstruct pci_epf_bar sec_epc_bar[6];\n\tu8 sec_epc_func_no;\n\tstruct config_group *group;\n\tunsigned int is_bound;\n\tunsigned int is_vf;\n\tlong unsigned int vfunction_num_map;\n\tstruct list_head pci_vepf;\n\tconst struct pci_epc_event_ops *event_ops;\n\tstruct pci_epf_doorbell_msg *db_msg;\n\tu16 num_db;\n};\n\nstruct pci_epf_bar_submap {\n\tdma_addr_t phys_addr;\n\tsize_t size;\n};\n\nstruct pci_epf_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pci_epf_doorbell_msg {\n\tstruct msi_msg msg;\n\tint virq;\n};\n\nstruct pci_epf_ops;\n\nstruct pci_epf_driver {\n\tint (*probe)(struct pci_epf *, const struct pci_epf_device_id *);\n\tvoid (*remove)(struct pci_epf *);\n\tstruct device_driver driver;\n\tconst struct pci_epf_ops *ops;\n\tstruct module *owner;\n\tstruct list_head epf_group;\n\tconst struct pci_epf_device_id *id_table;\n};\n\nstruct pci_epf_group {\n\tstruct config_group group;\n\tstruct config_group primary_epc_group;\n\tstruct config_group secondary_epc_group;\n\tstruct pci_epf *epf;\n\tint index;\n};\n\nstruct pci_epf_header {\n\tu16 vendorid;\n\tu16 deviceid;\n\tu8 revid;\n\tu8 progif_code;\n\tu8 subclass_code;\n\tu8 baseclass_code;\n\tu8 cache_line_size;\n\tu16 subsys_vendor_id;\n\tu16 subsys_id;\n\tenum pci_interrupt_pin interrupt_pin;\n};\n\nstruct pci_epf_msix_tbl {\n\tu64 msg_addr;\n\tu32 msg_data;\n\tu32 vector_ctrl;\n};\n\nstruct pci_epf_ops {\n\tint (*bind)(struct pci_epf *);\n\tvoid (*unbind)(struct pci_epf *);\n\tstruct config_group * (*add_cfs)(struct pci_epf *, struct config_group *);\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tint hook_offset;\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct pci_osc_bit_struct {\n\tu32 bit;\n\tchar *desc;\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pcie_ptm_ops;\n\nstruct pci_ptm_debugfs {\n\tstruct dentry *debugfs;\n\tconst struct pcie_ptm_ops *ops;\n\tstruct mutex lock;\n\tvoid *pdata;\n};\n\nstruct pci_pwrctrl {\n\tstruct device *dev;\n\tint (*power_on)(struct pci_pwrctrl *);\n\tint (*power_off)(struct pci_pwrctrl *);\n\tstruct notifier_block nb;\n\tstruct device_link *link;\n\tstruct work_struct work;\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct serial_private;\n\nstruct pciserial_board;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pci_sriov {\n\tint pos;\n\tint nres;\n\tu32 cap;\n\tu16 ctrl;\n\tu16 total_VFs;\n\tu16 initial_VFs;\n\tu16 num_VFs;\n\tu16 offset;\n\tu16 stride;\n\tu16 vf_device;\n\tu32 pgsz;\n\tu8 link;\n\tu8 max_VF_buses;\n\tu16 driver_max_VFs;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *self;\n\tu32 class;\n\tu8 hdr_type;\n\tu16 subsystem_vendor;\n\tu16 subsystem_device;\n\tresource_size_t barsz[6];\n\tu16 vf_rebar_cap;\n\tbool drivers_autoprobe;\n};\n\nstruct pcie_bwctrl_data {\n\tstruct mutex set_speed_mutex;\n\tstruct thermal_cooling_device *cdev;\n};\n\nstruct pcie_device {\n\tint irq;\n\tstruct pci_dev *port;\n\tu32 service;\n\tvoid *priv_data;\n\tstruct device device;\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tint: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n};\n\nstruct pcie_pme_service_data {\n\tspinlock_t lock;\n\tstruct pcie_device *srv;\n\tstruct work_struct work;\n\tbool noirq;\n};\n\nstruct pcie_port_service_driver {\n\tconst char *name;\n\tint (*probe)(struct pcie_device *);\n\tvoid (*remove)(struct pcie_device *);\n\tint (*suspend)(struct pcie_device *);\n\tint (*resume_noirq)(struct pcie_device *);\n\tint (*resume)(struct pcie_device *);\n\tint (*runtime_suspend)(struct pcie_device *);\n\tint (*runtime_resume)(struct pcie_device *);\n\tint (*slot_reset)(struct pcie_device *);\n\tint port_type;\n\tu32 service;\n\tstruct device_driver driver;\n};\n\nstruct pcie_ptm_ops {\n\tint (*check_capability)(void *);\n\tint (*context_update_write)(void *, u8);\n\tint (*context_update_read)(void *, u8 *);\n\tint (*context_valid_write)(void *, bool);\n\tint (*context_valid_read)(void *, bool *);\n\tint (*local_clock_read)(void *, u64 *);\n\tint (*master_clock_read)(void *, u64 *);\n\tint (*t1_read)(void *, u64 *);\n\tint (*t2_read)(void *, u64 *);\n\tint (*t3_read)(void *, u64 *);\n\tint (*t4_read)(void *, u64 *);\n\tbool (*context_update_visible)(void *);\n\tbool (*context_valid_visible)(void *);\n\tbool (*local_clock_visible)(void *);\n\tbool (*master_clock_visible)(void *);\n\tbool (*t1_visible)(void *);\n\tbool (*t2_visible)(void *);\n\tbool (*t3_visible)(void *);\n\tbool (*t4_visible)(void *);\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[17];\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpuobj_ext;\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tstruct pcpuobj_ext *obj_exts;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpuobj_ext {\n\tstruct obj_cgroup *cgroup;\n};\n\nstruct pcs_conf_type {\n\tconst char *name;\n\tenum pin_config_param param;\n};\n\nstruct pcs_conf_vals {\n\tenum pin_config_param param;\n\tunsigned int val;\n\tunsigned int enable;\n\tunsigned int disable;\n\tunsigned int mask;\n};\n\nstruct pcs_data {\n\tstruct pinctrl_pin_desc *pa;\n\tint cur;\n};\n\nstruct pcs_soc_data {\n\tunsigned int flags;\n\tint irq;\n\tunsigned int irq_enable_mask;\n\tunsigned int irq_status_mask;\n\tvoid (*rearm)(void);\n};\n\nstruct pcs_device {\n\tstruct resource *res;\n\tvoid *base;\n\tvoid *saved_vals;\n\tunsigned int size;\n\tstruct device *dev;\n\tstruct device_node *np;\n\tstruct pinctrl_dev *pctl;\n\tunsigned int flags;\n\tstruct property *missing_nr_pinctrl_cells;\n\tstruct pcs_soc_data socdata;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int width;\n\tunsigned int fmask;\n\tunsigned int fshift;\n\tunsigned int foff;\n\tunsigned int fmax;\n\tbool bits_per_mux;\n\tunsigned int bits_per_pin;\n\tstruct pcs_data pins;\n\tstruct list_head gpiofuncs;\n\tstruct list_head irqs;\n\tstruct irq_chip chip;\n\tstruct irq_domain *domain;\n\tstruct pinctrl_desc desc;\n\tunsigned int (*read)(void *);\n\tvoid (*write)(unsigned int, void *);\n};\n\nstruct pcs_func_vals {\n\tvoid *reg;\n\tunsigned int val;\n\tunsigned int mask;\n};\n\nstruct pcs_function {\n\tconst char *name;\n\tstruct pcs_func_vals *vals;\n\tunsigned int nvals;\n\tstruct pcs_conf_vals *conf;\n\tint nconfs;\n\tstruct list_head node;\n};\n\nstruct pcs_gpiofunc_range {\n\tunsigned int offset;\n\tunsigned int npins;\n\tunsigned int gpiofunc;\n\tstruct list_head node;\n};\n\nstruct pcs_interrupt {\n\tvoid *reg;\n\tirq_hw_number_t hwirq;\n\tunsigned int irq;\n\tstruct list_head node;\n};\n\nstruct pcs_pdata {\n\tint irq;\n\tvoid (*rearm)(void);\n};\n\nstruct pdc_pin_region {\n\tu32 pin_base;\n\tu32 parent_base;\n\tu32 cnt;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pdev_list_entry {\n\tstruct platform_device *pdev;\n\tstruct list_head node;\n};\n\nstruct pdiv_map {\n\tu8 pdiv;\n\tu8 hw_val;\n};\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[51];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tu8 expire;\n\tshort int free_count;\n\tstruct list_head lists[14];\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[10];\n\ts8 stat_threshold;\n\tlong unsigned int vm_numa_event[6];\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\nstruct per_user_data {\n\tstruct mutex bind_mutex;\n\tstruct rb_root evtchns;\n\tunsigned int nr_evtchns;\n\tunsigned int ring_size;\n\tevtchn_port_t *ring;\n\tunsigned int ring_cons;\n\tunsigned int ring_prod;\n\tunsigned int ring_overflow;\n\tstruct mutex ring_cons_mutex;\n\tspinlock_t ring_prod_lock;\n\twait_queue_head_t evtchn_wait;\n\tstruct fasync_struct *evtchn_async_queue;\n\tconst char *name;\n\tdomid_t restrict_domid;\n};\n\nstruct percpu_free_defer {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\ntypedef struct percpu_rw_semaphore *class_percpu_read_t;\n\ntypedef struct percpu_rw_semaphore *class_percpu_write_t;\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[10];\n\tlong unsigned int offset[10];\n\tlocal_lock_t lock;\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu64 hw_id;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___3 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 spec: 2;\n\t__u64 new_type: 4;\n\t__u64 priv: 3;\n\t__u64 reserved: 31;\n};\n\nstruct perf_branch_stack {\n\tu64 nr;\n\tu64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct perf_event_mmap_page;\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\trefcount_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tstruct mutex aux_mutex;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\trefcount_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tint aux_in_pause_resume;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct unwind_stacktrace;\n\nstruct perf_callchain_deferred_event {\n\tstruct unwind_stacktrace *trace;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 cookie;\n\t\tu64 nr;\n\t\tu64 ips[0];\n\t} event;\n};\n\nstruct perf_callchain_entry {\n\tu64 nr;\n\tu64 ip[0];\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nstruct perf_cgroup_info;\n\nstruct perf_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct perf_cgroup_info *info;\n};\n\nstruct perf_cgroup_event {\n\tchar *path;\n\tint path_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 id;\n\t\tchar path[0];\n\t} event_id;\n};\n\nstruct perf_time_ctx {\n\tu64 time;\n\tu64 stamp;\n\tu64 offset;\n};\n\nstruct perf_cgroup_info {\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tint active;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tu64 index;\n};\n\nstruct perf_event_context {\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head pmu_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tint nr_events;\n\tint nr_user;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tstruct perf_event_context *parent_ctx;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tint nr_cgroups;\n\tstruct callback_head callback_head;\n\tlocal_t nr_no_switch_fast;\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint online;\n\tstruct perf_cgroup *cgrp;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_event_pmu_context {\n\tstruct pmu *pmu;\n\tstruct perf_event_context *ctx;\n\tstruct list_head pmu_ctx_entry;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tunsigned int embedded: 1;\n\tunsigned int nr_events;\n\tunsigned int nr_cgroups;\n\tunsigned int nr_freq;\n\tatomic_t refcount;\n\tstruct callback_head callback_head;\n\tint rotate_necessary;\n};\n\nstruct perf_cpu_pmu_context {\n\tstruct perf_event_pmu_context epc;\n\tstruct perf_event_pmu_context *task_epc;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint active_oncpu;\n\tint exclusive;\n\tint pmu_disable_count;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n};\n\nstruct perf_ctx_data {\n\tstruct callback_head callback_head;\n\trefcount_t refcount;\n\tint global;\n\tstruct kmem_cache *ctx_cache;\n\tvoid *data;\n};\n\nstruct scmi_perf_domain_info {\n\tchar name[64];\n\tbool set_perf;\n};\n\nstruct scmi_opp {\n\tu32 perf;\n\tu32 power;\n\tu32 trans_latency_us;\n\tu32 indicative_freq;\n\tu32 level_index;\n\tstruct hlist_node hash;\n};\n\nstruct scmi_fc_info;\n\nstruct perf_dom_info {\n\tu32 id;\n\tbool set_limits;\n\tbool perf_limit_notify;\n\tbool perf_level_notify;\n\tbool perf_fastchannels;\n\tbool level_indexing_mode;\n\tu32 opp_count;\n\tu32 rate_limit_us;\n\tu32 sustained_freq_khz;\n\tu32 sustained_perf_level;\n\tlong unsigned int mult_factor;\n\tstruct scmi_perf_domain_info info;\n\tstruct scmi_opp opp[64];\n\tstruct scmi_fc_info *fc_info;\n\tstruct xarray opps_by_idx;\n\tstruct xarray opps_by_lvl;\n\tstruct hlist_head opps_by_freq[64];\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 text_poke: 1;\n\t__u64 build_id: 1;\n\t__u64 inherit_thread: 1;\n\t__u64 remove_on_exec: 1;\n\t__u64 sigtrap: 1;\n\t__u64 defer_callchain: 1;\n\t__u64 defer_output: 1;\n\t__u64 __reserved_1: 24;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\tunion {\n\t\t__u32 aux_action;\n\t\tstruct {\n\t\t\t__u32 aux_start_paused: 1;\n\t\t\t__u32 aux_pause: 1;\n\t\t\t__u32 aux_resume: 1;\n\t\t\t__u32 __reserved_3: 29;\n\t\t};\n\t};\n\t__u64 sig_data;\n\t__u64 config3;\n\t__u64 config4;\n};\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tunsigned int group_generation;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tstruct perf_event_pmu_context *pmu_ctx;\n\tatomic_long_t refcount;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\trefcount_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tunsigned int pending_wakeup;\n\tunsigned int pending_kill;\n\tunsigned int pending_disable;\n\tlong unsigned int pending_addr;\n\tstruct irq_work pending_irq;\n\tstruct irq_work pending_disable_irq;\n\tstruct callback_head pending_task;\n\tunsigned int pending_work;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tu64 id;\n\tatomic64_t lost_samples;\n\tu64 (*clock)(void);\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tstruct bpf_prog *prog;\n\tu64 bpf_cookie;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tstruct perf_cgroup *cgrp;\n\tvoid *security;\n\tstruct list_head sb_list;\n\tstruct list_head pmu_list;\n\tu32 orig_type;\n};\n\nstruct perf_event_min_heap {\n\tsize_t nr;\n\tsize_t size;\n\tstruct perf_event **data;\n\tstruct perf_event *preallocated[0];\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_user_time_short: 1;\n\t\t\t__u64 cap_____res: 58;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u32 __reserved_1;\n\t__u64 time_cycles;\n\t__u64 time_mask;\n\t__u8 __reserved[928];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct perf_guest_info_callbacks {\n\tunsigned int (*state)(void);\n\tlong unsigned int (*get_ip)(void);\n\tunsigned int (*handle_intel_pt_intr)(void);\n\tvoid (*handle_mediated_pmi)(void);\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tu8 build_id[20];\n\tu32 build_id_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tunion {\n\t\tu64 flags;\n\t\tu64 aux_flags;\n\t\tstruct {\n\t\t\tu64 skip_read: 1;\n\t\t};\n\t};\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n} __attribute__((packed));\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_text_poke_event {\n\tconst void *old_bytes;\n\tconst void *new_bytes;\n\tsize_t pad;\n\tu16 old_len;\n\tu16 new_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t} event_id;\n};\n\nstruct pericom8250 {\n\tvoid *virt;\n\tunsigned int nr;\n\tint line[0];\n};\n\nstruct vfio_pci_core_device;\n\nstruct perm_bits {\n\tu8 *virt;\n\tu8 *write;\n\tint (*readfn)(struct vfio_pci_core_device *, int, int, struct perm_bits *, int, __le32 *);\n\tint (*writefn)(struct vfio_pci_core_device *, int, int, struct perm_bits *, int, __le32);\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct pf8x00_chip {\n\tstruct regmap *regmap;\n\tstruct device *dev;\n};\n\nstruct pf8x00_regulator_data {\n\tstruct regulator_desc desc;\n\tunsigned int suspend_enable_reg;\n\tunsigned int suspend_enable_mask;\n\tunsigned int suspend_voltage_reg;\n\tunsigned int suspend_voltage_cache;\n};\n\nstruct pf_desc {\n\tu32 pseudoflavor;\n\tu32 qop;\n\tu32 service;\n\tchar *name;\n\tchar *auth_domain_name;\n\tstruct auth_domain *domain;\n\tbool datatouch;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct pfn_address_space {\n\tstruct interval_tree_node node;\n\tstruct address_space *mapping;\n\tint (*pfn_to_vma_pgoff)(struct vm_area_struct *, long unsigned int, long unsigned int *);\n};\n\nstruct pfuze_regulator {\n\tstruct regulator_desc desc;\n\tunsigned char stby_reg;\n\tunsigned char stby_mask;\n\tbool sw_reg;\n};\n\nstruct pfuze_chip {\n\tint chip_id;\n\tint flags;\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tstruct pfuze_regulator regulator_descs[16];\n\tstruct regulator_dev *regulators[16];\n\tconst struct pfuze_regulator *pfuze_regulators;\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[4];\n\tint node;\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tlong unsigned int present_early_pages;\n\tlong unsigned int cma_pages;\n\tconst char *name;\n\tlong unsigned int nr_isolate_pageblock;\n\tseqlock_t span_seqlock;\n\tint initialized;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[11];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 0;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[10];\n\tatomic_long_t vm_numa_event[6];\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[65];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[4];\n\tstruct zonelist node_zonelists[2];\n\tint nr_zones;\n\tspinlock_t node_size_lock;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct mutex kswapd_lock;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tlong unsigned int min_unmapped_pages;\n\tlong unsigned int min_slab_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct deferred_split deferred_split_queue;\n\tunsigned int nbp_rl_start;\n\tlong unsigned int nbp_rl_nr_cand;\n\tunsigned int nbp_threshold;\n\tunsigned int nbp_th_start;\n\tlong unsigned int nbp_th_nr_cand;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[51];\n\tstruct memory_tier *memtier;\n\tstruct memory_failure_stats mf_stats;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tu32 max_link_rate;\n\tenum phy_mode mode;\n};\n\nstruct phy {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tstruct lock_class_key lockdep_key;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n\tstruct dentry *debugfs;\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nstruct phy_axg_mipi_pcie_analog_priv {\n\tstruct phy *phy;\n\tstruct regmap *regmap;\n\tbool dsi_configured;\n\tbool dsi_enabled;\n\tbool powered;\n\tstruct phy_configure_opts_mipi_dphy config;\n};\n\nstruct phy_axg_pcie_priv {\n\tstruct phy *phy;\n\tstruct phy *analog;\n\tstruct regmap *regmap;\n\tstruct reset_control *reset;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_lvds {\n\tunsigned int bits_per_lane_and_dclk_cycle;\n\tlong unsigned int differential_clk_rate;\n\tunsigned int lanes;\n\tbool is_slave;\n};\n\nstruct phy_configure_opts_hdmi {\n\tunsigned int bpc;\n\tunion {\n\t\tlong long unsigned int tmds_char_rate;\n\t\tstruct {\n\t\t\tu8 rate_per_lane;\n\t\t\tu8 lanes;\n\t\t} frl;\n\t};\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n\tstruct phy_configure_opts_lvds lvds;\n\tstruct phy_configure_opts_hdmi hdmi;\n};\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[1];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tlong unsigned int adv_old[2];\n\tlong unsigned int supported_eee[2];\n\tlong unsigned int advertising_eee[2];\n\tlong unsigned int eee_disabled_modes[2];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[1];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct phy_package_shared *shared;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct phy_devm {\n\tstruct usb_phy *phy;\n\tstruct notifier_block *nb;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct phy_g12a_mipi_dphy_analog_priv {\n\tstruct phy *phy;\n\tstruct regmap *regmap;\n\tstruct phy_configure_opts_mipi_dphy config;\n};\n\nstruct phy_g12a_usb3_pcie_priv {\n\tstruct regmap *regmap;\n\tstruct regmap *regmap_cr;\n\tstruct clk *clk_ref;\n\tstruct reset_control *reset;\n\tstruct phy *phy;\n\tunsigned int mode;\n};\n\nstruct phy_gmii_sel_priv;\n\nstruct phy_gmii_sel_phy_priv {\n\tstruct phy_gmii_sel_priv *priv;\n\tu32 id;\n\tstruct phy *if_phy;\n\tint rmii_clock_external;\n\tint phy_if_mode;\n\tstruct regmap_field *fields[4];\n};\n\nstruct phy_gmii_sel_soc_data;\n\nstruct phy_provider;\n\nstruct phy_gmii_sel_priv {\n\tstruct device *dev;\n\tconst struct phy_gmii_sel_soc_data *soc_data;\n\tstruct regmap *regmap;\n\tstruct phy_provider *phy_provider;\n\tstruct phy_gmii_sel_phy_priv *if_phys;\n\tu32 num_ports;\n\tu32 reg_offset;\n\tu32 qsgmii_main_ports;\n\tbool no_offset;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct phy_gmii_sel_soc_data {\n\tu32 num_ports;\n\tu32 features;\n\tconst struct reg_field (*regfields)[4];\n\tbool use_of_data;\n\tu64 extra_modes;\n\tu32 num_qsgmii_main_ports;\n};\n\nstruct phy_led {\n\tstruct list_head list;\n\tstruct phy_device *phydev;\n\tstruct led_classdev led_cdev;\n\tu8 index;\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nstruct phy_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct phy *phy;\n};\n\nstruct phy_meson8b_usb2_match_data {\n\tbool host_enable_aca;\n};\n\nstruct phy_meson8b_usb2_priv {\n\tstruct regmap *regmap;\n\tenum usb_dr_mode dr_mode;\n\tstruct clk *clk_usb_general;\n\tstruct clk *clk_usb;\n\tstruct reset_control *reset;\n\tconst struct phy_meson8b_usb2_match_data *match;\n};\n\nstruct phy_meson_axg_mipi_dphy_priv {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tstruct phy *analog;\n\tstruct phy_configure_opts_mipi_dphy config;\n};\n\nstruct phy_meson_g12a_usb2_priv {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tint soc_id;\n};\n\nstruct phy_meson_gxl_usb2_priv {\n\tstruct regmap *regmap;\n\tenum phy_mode mode;\n\tint is_enabled;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n};\n\nunion phy_notify {\n\tenum phy_ufs_state ufs_state;\n};\n\nstruct phy_ops {\n\tint (*init)(struct phy *);\n\tint (*exit)(struct phy *);\n\tint (*power_on)(struct phy *);\n\tint (*power_off)(struct phy *);\n\tint (*set_mode)(struct phy *, enum phy_mode, int);\n\tint (*set_media)(struct phy *, enum phy_media);\n\tint (*set_speed)(struct phy *, int);\n\tint (*configure)(struct phy *, union phy_configure_opts *);\n\tint (*validate)(struct phy *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy *);\n\tint (*calibrate)(struct phy *);\n\tint (*connect)(struct phy *, int);\n\tint (*disconnect)(struct phy *, int);\n\tint (*notify_phystate)(struct phy *, union phy_notify);\n\tvoid (*release)(struct phy *);\n\tstruct module *owner;\n};\n\nstruct phy_package_shared {\n\tu8 base_addr;\n\tstruct device_node *np;\n\trefcount_t refcnt;\n\tlong unsigned int flags;\n\tsize_t priv_size;\n\tvoid *priv;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_port_ops;\n\nstruct phy_port {\n\tstruct list_head head;\n\tenum phy_port_parent parent_type;\n\tunion {\n\t\tstruct phy_device *phy;\n\t};\n\tconst struct phy_port_ops *ops;\n\tint pairs;\n\tlong unsigned int mediums;\n\tlong unsigned int supported[2];\n\tlong unsigned int interfaces[1];\n\tunsigned int not_described: 1;\n\tunsigned int active: 1;\n\tunsigned int is_mii: 1;\n\tunsigned int is_sfp: 1;\n};\n\nstruct phy_port_ops {\n\tvoid (*link_up)(struct phy_port *);\n\tvoid (*link_down)(struct phy_port *);\n\tint (*configure_mii)(struct phy_port *, bool, phy_interface_t);\n};\n\nstruct phy_provider {\n\tstruct device *dev;\n\tstruct device_node *children;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct phy * (*of_xlate)(struct device *, const struct of_phandle_args *);\n};\n\nstruct phy_reg {\n\tu16 value;\n\tu32 addr;\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phylib_stubs {\n\tint (*hwtstamp_get)(struct phy_device *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct phy_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_ext_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n};\n\nstruct phylink_link_state {\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tphy_interface_t interface;\n\tint speed;\n\tint duplex;\n\tint pause;\n\tint rate_matching;\n\tunsigned int link: 1;\n\tunsigned int an_complete: 1;\n};\n\nstruct phylink {\n\tstruct net_device *netdev;\n\tconst struct phylink_mac_ops *mac_ops;\n\tstruct phylink_config *config;\n\tstruct phylink_pcs *pcs;\n\tstruct device *dev;\n\tunsigned int old_link_state: 1;\n\tlong unsigned int phylink_disable_state;\n\tstruct phy_device *phydev;\n\tphy_interface_t link_interface;\n\tu8 cfg_link_an_mode;\n\tu8 req_link_an_mode;\n\tu8 act_link_an_mode;\n\tu8 link_port;\n\tlong unsigned int supported[2];\n\tlong unsigned int supported_lpi[2];\n\tstruct phylink_link_state link_config;\n\tphy_interface_t cur_interface;\n\tstruct gpio_desc *link_gpio;\n\tunsigned int link_irq;\n\tstruct timer_list link_poll;\n\tstruct mutex state_mutex;\n\tstruct mutex phydev_mutex;\n\tstruct phylink_link_state phy_state;\n\tunsigned int phy_ib_mode;\n\tstruct work_struct resolve;\n\tunsigned int pcs_neg_mode;\n\tunsigned int pcs_state;\n\tbool link_failed;\n\tbool suspend_link_up;\n\tbool force_major_config;\n\tbool major_config_failed;\n\tbool mac_supports_eee_ops;\n\tbool mac_supports_eee;\n\tbool phy_enable_tx_lpi;\n\tbool mac_enable_tx_lpi;\n\tbool mac_tx_clk_stop;\n\tu32 mac_tx_lpi_timer;\n\tu8 mac_rx_clk_stop_blocked;\n\tstruct sfp_bus *sfp_bus;\n\tbool sfp_may_have_phy;\n\tlong unsigned int sfp_interfaces[1];\n\tlong unsigned int sfp_support[2];\n\tu8 sfp_port;\n\tstruct eee_config eee_cfg;\n\tu32 wolopts_mac;\n\tu8 wol_sopass[6];\n};\n\nstruct phylink_mac_ops {\n\tlong unsigned int (*mac_get_caps)(struct phylink_config *, phy_interface_t);\n\tstruct phylink_pcs * (*mac_select_pcs)(struct phylink_config *, phy_interface_t);\n\tint (*mac_prepare)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_config)(struct phylink_config *, unsigned int, const struct phylink_link_state *);\n\tint (*mac_finish)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_down)(struct phylink_config *, unsigned int, phy_interface_t);\n\tvoid (*mac_link_up)(struct phylink_config *, struct phy_device *, unsigned int, phy_interface_t, int, int, bool, bool);\n\tvoid (*mac_disable_tx_lpi)(struct phylink_config *);\n\tint (*mac_enable_tx_lpi)(struct phylink_config *, u32, bool);\n\tint (*mac_wol_set)(struct phylink_config *, u32, const u8 *);\n};\n\nstruct phylink_pcs_ops {\n\tint (*pcs_validate)(struct phylink_pcs *, long unsigned int *, const struct phylink_link_state *);\n\tunsigned int (*pcs_inband_caps)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_enable)(struct phylink_pcs *);\n\tvoid (*pcs_disable)(struct phylink_pcs *);\n\tvoid (*pcs_pre_config)(struct phylink_pcs *, phy_interface_t);\n\tint (*pcs_post_config)(struct phylink_pcs *, phy_interface_t);\n\tvoid (*pcs_get_state)(struct phylink_pcs *, unsigned int, struct phylink_link_state *);\n\tint (*pcs_config)(struct phylink_pcs *, unsigned int, phy_interface_t, const long unsigned int *, bool);\n\tvoid (*pcs_an_restart)(struct phylink_pcs *);\n\tvoid (*pcs_link_up)(struct phylink_pcs *, unsigned int, phy_interface_t, int, int);\n\tvoid (*pcs_disable_eee)(struct phylink_pcs *);\n\tvoid (*pcs_enable_eee)(struct phylink_pcs *);\n\tint (*pcs_pre_init)(struct phylink_pcs *);\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct physdev_dbgp_op {\n\tuint8_t op;\n\tuint8_t bus;\n\tunion {\n\t\tstruct physdev_pci_device pci;\n\t} u;\n};\n\nstruct physdev_eoi {\n\tuint32_t irq;\n};\n\nstruct physdev_get_free_pirq {\n\tint type;\n\tuint32_t pirq;\n};\n\nstruct physdev_irq {\n\tuint32_t irq;\n\tuint32_t vector;\n};\n\nstruct physdev_irq_status_query {\n\tuint32_t irq;\n\tuint32_t flags;\n};\n\nstruct physdev_manage_pci {\n\tuint8_t bus;\n\tuint8_t devfn;\n};\n\nstruct physdev_manage_pci_ext {\n\tuint8_t bus;\n\tuint8_t devfn;\n\tunsigned int is_extfn;\n\tunsigned int is_virtfn;\n\tstruct {\n\t\tuint8_t bus;\n\t\tuint8_t devfn;\n\t} physfn;\n};\n\nstruct physdev_map_pirq {\n\tdomid_t domid;\n\tint type;\n\tint index;\n\tint pirq;\n\tint bus;\n\tint devfn;\n\tint entry_nr;\n\tuint64_t table_base;\n};\n\nstruct physdev_pci_device_add {\n\tuint16_t seg;\n\tuint8_t bus;\n\tuint8_t devfn;\n\tuint32_t flags;\n\tstruct {\n\t\tuint8_t bus;\n\t\tuint8_t devfn;\n\t} physfn;\n\tuint32_t optarr[0];\n};\n\nstruct physdev_unmap_pirq {\n\tdomid_t domid;\n\tint pirq;\n};\n\nstruct physmap_flash_data {\n\tunsigned int width;\n\tint (*init)(struct platform_device *);\n\tvoid (*exit)(struct platform_device *);\n\tvoid (*set_vpp)(struct platform_device *, int);\n\tunsigned int nr_parts;\n\tunsigned int pfow_base;\n\tchar *probe_type;\n\tstruct mtd_partition *parts;\n\tconst char * const *part_probe_types;\n};\n\nstruct physmap_flash_info {\n\tunsigned int nmaps;\n\tstruct mtd_info **mtds;\n\tstruct mtd_info *cmtd;\n\tstruct map_info *maps;\n\tspinlock_t vpp_lock;\n\tint vpp_refcnt;\n\tconst char *probe_type;\n\tconst char * const *part_types;\n\tunsigned int nparts;\n\tconst struct mtd_partition *parts;\n\tstruct gpio_descs *gpios;\n\tunsigned int gpio_values;\n\tunsigned int win_order;\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct fs_pin *bacct;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pids_cgroup {\n\tstruct cgroup_subsys_state css;\n\tatomic64_t counter;\n\tatomic64_t limit;\n\tint64_t watermark;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tatomic64_t events[2];\n\tatomic64_t events_local[2];\n};\n\nstruct pin_config {\n\tconst char *property;\n\tenum pincfg_type param;\n};\n\nstruct pin_config_item {\n\tconst enum pin_config_param param;\n\tconst char * const display;\n\tconst char * const format;\n\tbool has_arg;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinctrl_setting_mux;\n\nstruct pin_desc {\n\tstruct pinctrl_dev *pctldev;\n\tconst char *name;\n\tbool dynamic_name;\n\tvoid *drv_data;\n\tunsigned int mux_usecount;\n\tconst char *mux_owner;\n\tconst struct pinctrl_setting_mux *mux_setting;\n\tconst char *gpio_owner;\n\tstruct mutex mux_lock;\n};\n\nstruct pin_regs {\n\tu16 mux_bit;\n\tu16 pad_bit;\n};\n\nstruct pinconf_generic_params {\n\tconst char * const property;\n\tenum pin_config_param param;\n\tu32 default_value;\n\tconst char * const *values;\n\tsize_t num_values;\n};\n\nstruct pinconf_ops {\n\tbool is_generic;\n\tint (*pin_config_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tint (*pin_config_group_get)(struct pinctrl_dev *, unsigned int, long unsigned int *);\n\tint (*pin_config_group_set)(struct pinctrl_dev *, unsigned int, long unsigned int *, unsigned int);\n\tvoid (*pin_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_group_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tvoid (*pin_config_config_dbg_show)(struct pinctrl_dev *, struct seq_file *, long unsigned int);\n};\n\nstruct pinctrl {\n\tstruct list_head node;\n\tstruct device *dev;\n\tstruct list_head states;\n\tstruct pinctrl_state *state;\n\tstruct list_head dt_maps;\n\tstruct kref users;\n};\n\nstruct pinctrl_dev {\n\tstruct list_head node;\n\tconst struct pinctrl_desc *desc;\n\tstruct xarray pin_desc_tree;\n\tstruct xarray pin_group_tree;\n\tunsigned int num_groups;\n\tstruct xarray pin_function_tree;\n\tunsigned int num_functions;\n\tstruct list_head gpio_ranges;\n\tstruct device *dev;\n\tstruct module *owner;\n\tvoid *driver_data;\n\tstruct pinctrl *p;\n\tstruct pinctrl_state *hog_default;\n\tstruct pinctrl_state *hog_sleep;\n\tstruct mutex mutex;\n\tstruct dentry *device_root;\n};\n\nstruct pinctrl_map;\n\nstruct pinctrl_dt_map {\n\tstruct list_head node;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_map *map;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_map_mux {\n\tconst char *group;\n\tconst char *function;\n};\n\nstruct pinctrl_map_configs {\n\tconst char *group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_map {\n\tconst char *dev_name;\n\tconst char *name;\n\tenum pinctrl_map_type type;\n\tconst char *ctrl_dev_name;\n\tunion {\n\t\tstruct pinctrl_map_mux mux;\n\t\tstruct pinctrl_map_configs configs;\n\t} data;\n};\n\nstruct pinctrl_maps {\n\tstruct list_head node;\n\tconst struct pinctrl_map *maps;\n\tunsigned int num_maps;\n};\n\nstruct pinctrl_ops {\n\tint (*get_groups_count)(struct pinctrl_dev *);\n\tconst char * (*get_group_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_group_pins)(struct pinctrl_dev *, unsigned int, const unsigned int **, unsigned int *);\n\tvoid (*pin_dbg_show)(struct pinctrl_dev *, struct seq_file *, unsigned int);\n\tint (*dt_node_to_map)(struct pinctrl_dev *, struct device_node *, struct pinctrl_map **, unsigned int *);\n\tvoid (*dt_free_map)(struct pinctrl_dev *, struct pinctrl_map *, unsigned int);\n};\n\nstruct pinctrl_setting_mux {\n\tunsigned int group;\n\tunsigned int func;\n};\n\nstruct pinctrl_setting_configs {\n\tunsigned int group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_setting {\n\tstruct list_head node;\n\tenum pinctrl_map_type type;\n\tstruct pinctrl_dev *pctldev;\n\tconst char *dev_name;\n\tunion {\n\t\tstruct pinctrl_setting_mux mux;\n\t\tstruct pinctrl_setting_configs configs;\n\t} data;\n};\n\nstruct pinctrl_state {\n\tstruct list_head node;\n\tconst char *name;\n\tstruct list_head settings;\n};\n\nstruct pinfunction {\n\tconst char *name;\n\tconst char * const *groups;\n\tsize_t ngroups;\n\tlong unsigned int flags;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinmux_bias_reg {\n\tu32 puen;\n\tu32 pud;\n\tconst u16 pins[32];\n};\n\nstruct pinmux_cfg_reg {\n\tu32 reg;\n\tu8 reg_width;\n\tu8 field_width;\n\tconst u16 *enum_ids;\n\tconst s8 *var_field_width;\n};\n\nstruct pinmux_data_reg {\n\tu32 reg;\n\tu8 reg_width;\n\tconst u16 *enum_ids;\n};\n\nstruct pinmux_drive_reg_field {\n\tu16 pin;\n\tu8 offset;\n\tu8 size;\n};\n\nstruct pinmux_drive_reg {\n\tu32 reg;\n\tconst struct pinmux_drive_reg_field fields[10];\n};\n\nstruct pinmux_ioctrl_reg {\n\tu32 reg;\n};\n\nstruct pinmux_ops {\n\tint (*request)(struct pinctrl_dev *, unsigned int);\n\tint (*free)(struct pinctrl_dev *, unsigned int);\n\tint (*get_functions_count)(struct pinctrl_dev *);\n\tconst char * (*get_function_name)(struct pinctrl_dev *, unsigned int);\n\tint (*get_function_groups)(struct pinctrl_dev *, unsigned int, const char * const **, unsigned int *);\n\tbool (*function_is_gpio)(struct pinctrl_dev *, unsigned int);\n\tint (*set_mux)(struct pinctrl_dev *, unsigned int, unsigned int);\n\tint (*gpio_request_enable)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tvoid (*gpio_disable_free)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int);\n\tint (*gpio_set_direction)(struct pinctrl_dev *, struct pinctrl_gpio_range *, unsigned int, bool);\n\tbool strict;\n};\n\nstruct pinmux_range {\n\tu16 begin;\n\tu16 end;\n\tu16 force;\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe_buffer;\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct pipe_wait {\n\tstruct trace_iterator *iter;\n\tint wait_index;\n};\n\nstruct pixel_format {\n\tunsigned char bits_per_pixel;\n\tbool indexed;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} alpha;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} red;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} green;\n\t\t\tstruct {\n\t\t\t\tunsigned char offset;\n\t\t\t\tunsigned char length;\n\t\t\t} blue;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char offset;\n\t\t\tunsigned char length;\n\t\t} index;\n\t};\n};\n\nstruct pkcs1pad_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct pkcs1pad_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n};\n\nstruct pkcs1pad_request {\n\tstruct scatterlist in_sg[2];\n\tstruct scatterlist out_sg[1];\n\tuint8_t *in_buf;\n\tuint8_t *out_buf;\n\tstruct akcipher_request child_req;\n};\n\nstruct x509_certificate;\n\nstruct pkcs7_signed_info;\n\nstruct pkcs7_message {\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate *crl;\n\tstruct pkcs7_signed_info *signed_infos;\n\tu8 version;\n\tbool have_authattrs;\n\tenum OID data_type;\n\tsize_t data_len;\n\tsize_t data_hdrlen;\n\tconst void *data;\n};\n\nstruct pkcs7_parse_context {\n\tstruct pkcs7_message *msg;\n\tstruct pkcs7_signed_info *sinfo;\n\tstruct pkcs7_signed_info **ppsinfo;\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate **ppcerts;\n\tlong unsigned int data;\n\tenum OID last_oid;\n\tunsigned int x509_index;\n\tunsigned int sinfo_index;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_skid;\n\tunsigned int raw_skid_size;\n\tbool expect_skid;\n};\n\nstruct pkcs7_signed_info {\n\tstruct pkcs7_signed_info *next;\n\tstruct x509_certificate *signer;\n\tunsigned int index;\n\tbool unsupported_crypto;\n\tbool blacklisted;\n\tconst void *msgdigest;\n\tunsigned int msgdigest_len;\n\tunsigned int authattrs_len;\n\tconst void *authattrs;\n\tlong unsigned int aa_set;\n\ttime64_t signing_time;\n\tstruct public_key_signature *sig;\n};\n\nstruct pkvm_hyp_vcpu {\n\tstruct kvm_vcpu vcpu;\n\tstruct kvm_vcpu *host_vcpu;\n\tstruct pkvm_hyp_vcpu **loaded_hyp_vcpu;\n};\n\nstruct pkvm_hyp_vm {\n\tstruct kvm kvm;\n\tstruct kvm *host_kvm;\n\tstruct kvm_pgtable pgt;\n\tstruct kvm_pgtable_mm_ops mm_ops;\n\tstruct hyp_pool pool;\n\thyp_spinlock_t lock;\n\tstruct pkvm_hyp_vcpu *vcpus[0];\n};\n\nstruct pkvm_mapping {\n\tstruct rb_node node;\n\tu64 gfn;\n\tu64 pfn;\n\tu64 nr_pages;\n\tu64 __subtree_last;\n};\n\nstruct pl011_dmabuf {\n\tdma_addr_t dma;\n\tsize_t len;\n\tchar *buf;\n};\n\nstruct pl011_dmarx_data {\n\tstruct dma_chan *chan;\n\tstruct completion complete;\n\tbool use_buf_b;\n\tstruct pl011_dmabuf dbuf_a;\n\tstruct pl011_dmabuf dbuf_b;\n\tdma_cookie_t cookie;\n\tbool running;\n\tstruct timer_list timer;\n\tunsigned int last_residue;\n\tlong unsigned int last_jiffies;\n\tbool auto_poll_rate;\n\tunsigned int poll_rate;\n\tunsigned int poll_timeout;\n};\n\nstruct pl011_dmatx_data {\n\tstruct dma_chan *chan;\n\tdma_addr_t dma;\n\tsize_t len;\n\tchar *buf;\n\tbool queued;\n};\n\nstruct vendor_data;\n\nstruct pl022_ssp_controller;\n\nstruct pl022 {\n\tstruct amba_device *adev;\n\tstruct vendor_data *vendor;\n\tresource_size_t phybase;\n\tvoid *virtbase;\n\tstruct clk *clk;\n\tstruct spi_controller *host;\n\tstruct pl022_ssp_controller *host_info;\n\tstruct spi_transfer *cur_transfer;\n\tstruct chip_data___3 *cur_chip;\n\tvoid *tx;\n\tvoid *tx_end;\n\tvoid *rx;\n\tvoid *rx_end;\n\tenum ssp_reading read;\n\tenum ssp_writing write;\n\tu32 exp_fifo_level;\n\tenum ssp_rx_level_trig rx_lev_trig;\n\tenum ssp_tx_level_trig tx_lev_trig;\n\tstruct dma_chan *dma_rx_channel;\n\tstruct dma_chan *dma_tx_channel;\n\tstruct sg_table sgt_rx;\n\tstruct sg_table sgt_tx;\n\tchar *dummypage;\n\tbool dma_running;\n\tint cur_cs;\n};\n\nstruct ssp_clock_params {\n\tu8 cpsdvsr;\n\tu8 scr;\n};\n\nstruct pl022_config_chip {\n\tenum ssp_interface iface;\n\tenum ssp_hierarchy hierarchy;\n\tbool slave_tx_disable;\n\tstruct ssp_clock_params clk_freq;\n\tenum ssp_mode com_mode;\n\tenum ssp_rx_level_trig rx_lev_trig;\n\tenum ssp_tx_level_trig tx_lev_trig;\n\tenum ssp_microwire_ctrl_len ctrl_len;\n\tenum ssp_microwire_wait_state wait_state;\n\tenum ssp_duplex duplex;\n\tenum ssp_clkdelay clkdelay;\n};\n\nstruct pl022_ssp_controller {\n\tu16 bus_id;\n\tu8 enable_dma: 1;\n\tdma_filter_fn dma_filter;\n\tvoid *dma_rx_param;\n\tvoid *dma_tx_param;\n\tint autosuspend_delay;\n\tbool rt;\n};\n\nstruct pl031_vendor_data;\n\nstruct pl031_local {\n\tstruct pl031_vendor_data *vendor;\n\tstruct rtc_device *rtc;\n\tvoid *base;\n};\n\nstruct rtc_time;\n\nstruct rtc_wkalrm;\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct pl031_vendor_data {\n\tstruct rtc_class_ops ops;\n\tbool clockwatch;\n\tbool st_weekday;\n\tlong unsigned int irqflags;\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n};\n\nstruct pl061_context_save_regs {\n\tu8 gpio_data;\n\tu8 gpio_dir;\n\tu8 gpio_is;\n\tu8 gpio_ibe;\n\tu8 gpio_iev;\n\tu8 gpio_ie;\n};\n\nstruct pl061 {\n\traw_spinlock_t lock;\n\tvoid *base;\n\tstruct gpio_chip gc;\n\tint parent_irq;\n\tstruct pl061_context_save_regs csave_regs;\n};\n\nstruct pl330_config {\n\tu32 periph_id;\n\tunsigned int mode;\n\tunsigned int data_bus_width: 10;\n\tunsigned int data_buf_dep: 11;\n\tunsigned int num_chan: 4;\n\tunsigned int num_peri: 6;\n\tu32 peri_ns;\n\tunsigned int num_events: 6;\n\tu32 irq_ns;\n};\n\nstruct pl330_dmac {\n\tstruct dma_device ddma;\n\tstruct list_head desc_pool;\n\tspinlock_t pool_lock;\n\tunsigned int mcbufsz;\n\tvoid *base;\n\tstruct pl330_config pcfg;\n\tspinlock_t lock;\n\tint events[32];\n\tdma_addr_t mcode_bus;\n\tvoid *mcode_cpu;\n\tstruct pl330_thread *channels;\n\tstruct pl330_thread *manager;\n\tstruct tasklet_struct tasks;\n\tstruct _pl330_tbd dmac_tbd;\n\tenum pl330_dmac_state state;\n\tstruct list_head req_done;\n\tunsigned int num_peripherals;\n\tstruct dma_pl330_chan *peripherals;\n\tint quirks;\n\tstruct reset_control *rstc;\n\tstruct reset_control *rstc_ocp;\n};\n\nstruct pl330_of_quirks {\n\tchar *quirk;\n\tint id;\n};\n\nstruct pl330_thread {\n\tu8 id;\n\tint ev;\n\tbool free;\n\tstruct pl330_dmac *dmac;\n\tstruct _pl330_req req[2];\n\tunsigned int lstenq;\n\tint req_running;\n};\n\nstruct xilinx_msi {\n\tlong unsigned int *bitmap;\n\tstruct irq_domain *dev_domain;\n\tstruct mutex lock;\n\tint irq_msi0;\n\tint irq_msi1;\n};\n\nstruct xilinx_pl_dma_variant;\n\nstruct pl_dma_pcie {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tvoid *cfg_base;\n\tint irq;\n\tstruct pci_config_window *cfg;\n\tphys_addr_t phys_reg_base;\n\tstruct irq_domain *intx_domain;\n\tstruct irq_domain *pldma_domain;\n\tstruct list_head resources;\n\tstruct xilinx_msi msi;\n\tint intx_irq;\n\traw_spinlock_t lock;\n\tconst struct xilinx_pl_dma_variant *variant;\n};\n\nstruct plat_sci_port_ops;\n\nstruct plat_sci_port {\n\tunsigned int type;\n\tupf_t flags;\n\tunsigned int sampling_rate;\n\tunsigned int scscr;\n\tunsigned char regtype;\n\tstruct plat_sci_port_ops *ops;\n};\n\nstruct plat_sci_port_ops {\n\tvoid (*init_pins)(struct uart_port *, unsigned int);\n};\n\nstruct plat_sci_reg {\n\tu8 offset;\n\tu8 size;\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tunsigned int uartclk;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tunsigned int type;\n\tupf_t flags;\n\tu16 bugs;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_fw_data {\n\tconst u32 family_code;\n};\n\nstruct platform_hibernation_ops {\n\tint (*begin)(pm_message_t);\n\tvoid (*end)(void);\n\tint (*pre_snapshot)(void);\n\tvoid (*finish)(void);\n\tint (*prepare)(void);\n\tint (*enter)(void);\n\tvoid (*leave)(void);\n\tint (*pre_restore)(void);\n\tvoid (*restore_cleanup)(void);\n\tvoid (*recover)(void);\n};\n\nstruct platform_mhu_link {\n\tint irq;\n\tvoid *tx_reg;\n\tvoid *rx_reg;\n};\n\nstruct platform_mhu {\n\tvoid *base;\n\tstruct platform_mhu_link mlink[3];\n\tstruct mbox_chan chan[3];\n\tstruct mbox_controller mbox;\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)(void);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tvoid (*check)(void);\n\tbool (*wake)(void);\n\tvoid (*restore_early)(void);\n\tvoid (*restore)(void);\n\tvoid (*end)(void);\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)(void);\n\tvoid (*finish)(void);\n\tbool (*suspend_again)(void);\n\tvoid (*end)(void);\n\tvoid (*recover)(void);\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct pll5_mux_hw_data {\n\tstruct clk_hw hw;\n\tu32 conf;\n\tlong unsigned int rate;\n\tstruct rzg2l_cpg_priv *priv;\n};\n\nstruct pll_clk {\n\tstruct clk_hw hw;\n\tlong unsigned int default_rate;\n\tunsigned int conf;\n\tunsigned int type;\n\tvoid *base;\n\tstruct rzg2l_cpg_priv *priv;\n};\n\nstruct pll_clk___2 {\n\tstruct rzv2h_cpg_priv *priv;\n\tstruct clk_hw hw;\n\tstruct pll pll;\n};\n\nstruct pll_config {\n\tu16 l;\n\tu32 m;\n\tu32 n;\n\tu32 vco_val;\n\tu32 vco_mask;\n\tu32 pre_div_val;\n\tu32 pre_div_mask;\n\tu32 post_div_val;\n\tu32 post_div_mask;\n\tu32 mn_ena_mask;\n\tu32 main_output_mask;\n\tu32 aux_output_mask;\n};\n\nstruct pll_freq_tbl {\n\tlong unsigned int freq;\n\tu16 l;\n\tu16 m;\n\tu16 n;\n\tu32 ibits;\n};\n\nstruct pll_mult_range {\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct pll_out_data {\n\tchar *div_name;\n\tchar *pll_out_name;\n\tu32 offset;\n\tint clk_id;\n\tu8 div_shift;\n\tu8 div_flags;\n\tu8 rst_shift;\n\tspinlock_t *lock;\n};\n\nstruct pll_params_table {\n\tunsigned int m;\n\tunsigned int n;\n};\n\nstruct pll_vco {\n\tlong unsigned int min_freq;\n\tlong unsigned int max_freq;\n\tu32 val;\n};\n\nstruct plt_entry {\n\t__le32 adrp;\n\t__le32 add;\n\t__le32 br;\n};\n\nstruct pltfm_imx_data {\n\tu32 scratchpad;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_100mhz;\n\tstruct pinctrl_state *pins_200mhz;\n\tconst struct esdhc_soc_data *socdata;\n\tstruct esdhc_platform_data boarddata;\n\tstruct clk *clk_ipg;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_per;\n\tunsigned int actual_clock;\n\tunsigned int init_card_type;\n\tenum {\n\t\tNO_CMD_PENDING = 0,\n\t\tMULTIBLK_IN_PROCESS = 1,\n\t\tWAIT_FOR_INT = 2,\n\t} multiblock_status;\n\tu32 is_ddr;\n\tstruct pm_qos_request pm_qos_req;\n};\n\nstruct pm8941_data {\n\tunsigned int pull_up_bit;\n\tunsigned int status_bit;\n\tbool supports_ps_hold_poff_config;\n\tbool supports_debounce_config;\n\tbool has_pon_pbs;\n\tbool wakeup_source_default;\n\tconst char *name;\n\tconst char *phys;\n};\n\nstruct pm8941_pwrkey {\n\tstruct device *dev;\n\tint irq;\n\tu32 baseaddr;\n\tu32 pon_pbs_baseaddr;\n\tstruct regmap *regmap;\n\tstruct input_dev *input;\n\tunsigned int revision;\n\tunsigned int subtype;\n\tstruct notifier_block reboot_notifier;\n\tu32 code;\n\tu32 sw_debounce_time_us;\n\tktime_t sw_debounce_end_time;\n\tbool last_status;\n\tconst struct pm8941_data *data;\n};\n\nstruct pm_api_feature_data {\n\tu32 pm_api_id;\n\tint feature_status;\n\tstruct hlist_node hentry;\n};\n\nstruct pm_api_info {\n\tu32 api_id;\n\tchar api_name[50];\n\tchar api_name_len;\n};\n\nstruct pm_clk_notifier_block {\n\tstruct notifier_block nb;\n\tstruct dev_pm_domain *pm_domain;\n\tchar *con_ids[0];\n};\n\nstruct pm_clock_entry {\n\tstruct list_head node;\n\tchar *con_id;\n\tstruct clk *clk;\n\tenum pce_status status;\n\tbool enabled_when_prepared;\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n\tunsigned int clock_op_might_sleep;\n\tstruct mutex clock_mutex;\n\tstruct list_head clock_list;\n\tstruct pm_domain_data *domain_data;\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct tegra_pmc;\n\nstruct pmc_clk {\n\tstruct clk_hw hw;\n\tstruct tegra_pmc *pmc;\n\tlong unsigned int offs;\n\tu32 mux_shift;\n\tu32 force_en_shift;\n};\n\nstruct pmc_clk_gate {\n\tstruct clk_hw hw;\n\tstruct tegra_pmc *pmc;\n\tlong unsigned int offs;\n\tu32 shift;\n};\n\nstruct pmc_clk_init_data {\n\tchar *name;\n\tconst char * const *parents;\n\tint num_parents;\n\tint clk_id;\n\tu8 mux_shift;\n\tu8 force_en_shift;\n};\n\nstruct spmi_pmic_arb_bus;\n\nstruct spmi_controller;\n\nstruct pmic_arb_ver_ops {\n\tconst char *ver_str;\n\tint (*get_core_resources)(struct platform_device *, void *);\n\tint (*get_bus_resources)(struct platform_device *, struct device_node *, struct spmi_pmic_arb_bus *);\n\tint (*init_apid)(struct spmi_pmic_arb_bus *, int);\n\tint (*ppid_to_apid)(struct spmi_pmic_arb_bus *, u16);\n\tint (*offset)(struct spmi_pmic_arb_bus *, u8, u16, enum pmic_arb_channel);\n\tu32 (*fmt_cmd)(u8, u8, u16, u8);\n\tint (*non_data_cmd)(struct spmi_controller *, u8, u8);\n\tvoid * (*owner_acc_status)(struct spmi_pmic_arb_bus *, u8, u16);\n\tvoid * (*acc_enable)(struct spmi_pmic_arb_bus *, u16);\n\tvoid * (*irq_status)(struct spmi_pmic_arb_bus *, u16);\n\tvoid * (*irq_clear)(struct spmi_pmic_arb_bus *, u16);\n\tu32 (*apid_map_offset)(u16);\n\tvoid * (*apid_owner)(struct spmi_pmic_arb_bus *, u16);\n};\n\nstruct pmic_gpio_pad {\n\tu16 base;\n\tbool is_enabled;\n\tbool out_value;\n\tbool have_buffer;\n\tbool output_enabled;\n\tbool input_enabled;\n\tbool analog_pass;\n\tbool lv_mv_type;\n\tunsigned int num_sources;\n\tunsigned int power_source;\n\tunsigned int buffer_type;\n\tunsigned int pullup;\n\tunsigned int strength;\n\tunsigned int function;\n\tunsigned int atest;\n\tunsigned int dtest_buffer;\n};\n\nstruct pmic_gpio_state {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct pinctrl_dev *ctrl;\n\tstruct gpio_chip chip;\n\tu8 usid;\n\tu8 pid_base;\n};\n\nstruct pmic_irq_data {\n\tunsigned int num_top;\n\tunsigned int num_pmic_irqs;\n\tshort unsigned int top_int_status_reg;\n\tbool *enable_hwirq;\n\tbool *cache_hwirq;\n\tconst struct irq_top_t *pmic_ints;\n};\n\nstruct pmic_mpp_pad {\n\tu16 base;\n\tbool is_enabled;\n\tbool out_value;\n\tbool output_enabled;\n\tbool input_enabled;\n\tbool paired;\n\tbool has_pullup;\n\tunsigned int num_sources;\n\tunsigned int power_source;\n\tunsigned int amux_input;\n\tunsigned int aout_level;\n\tunsigned int pullup;\n\tunsigned int function;\n\tunsigned int drive_strength;\n\tunsigned int dtest;\n};\n\nstruct pmic_mpp_state {\n\tstruct device *dev;\n\tstruct regmap *map;\n\tstruct pinctrl_dev *ctrl;\n\tstruct gpio_chip chip;\n};\n\nstruct pmic_wrapper_type;\n\nstruct pwrap_slv_type;\n\nstruct pmic_wrapper {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct regmap *regmap;\n\tconst struct pmic_wrapper_type *master;\n\tconst struct pwrap_slv_type *slave;\n\tstruct reset_control *rstc;\n\tstruct reset_control *rstc_bridge;\n\tvoid *bridge_base;\n};\n\nstruct pmic_wrapper_type {\n\tconst int *regs;\n\tenum pwrap_type type;\n\tu32 arb_en_all;\n\tu32 int_en_all;\n\tu32 int1_en_all;\n\tu32 spi_w;\n\tu32 wdt_src;\n\tu32 caps;\n\tint (*init_reg_clock)(struct pmic_wrapper *);\n\tint (*init_soc_specific)(struct pmic_wrapper *);\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pmu_hw_events {\n\tstruct perf_event *events[33];\n\tlong unsigned int used_mask[1];\n\tstruct arm_pmu *percpu_pmu;\n\tint irq;\n\tstruct perf_branch_stack *branch_stack;\n\tunsigned int branch_users;\n};\n\nstruct pmu_irq_ops {\n\tvoid (*enable_pmuirq)(unsigned int);\n\tvoid (*disable_pmuirq)(unsigned int);\n\tvoid (*free_pmuirq)(unsigned int, int, void *);\n};\n\ntypedef int (*armpmu_init_fn)(struct arm_pmu *);\n\nstruct pmu_probe_info {\n\tunsigned int cpuid;\n\tunsigned int mask;\n\tarmpmu_init_fn init;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct pnfs_commit_bucket {\n\tstruct list_head written;\n\tstruct list_head committing;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_writeverf direct_verf;\n};\n\nstruct pnfs_commit_array {\n\tstruct list_head cinfo_list;\n\tstruct list_head lseg_list;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tunsigned int nbuckets;\n\tstruct pnfs_commit_bucket buckets[0];\n};\n\nstruct pnfs_commit_ops {\n\tvoid (*setup_ds_info)(struct pnfs_ds_commit_info *, struct pnfs_layout_segment *);\n\tvoid (*release_ds_info)(struct pnfs_ds_commit_info *, struct inode *);\n\tint (*commit_pagelist)(struct inode *, struct list_head *, int, struct nfs_commit_info *);\n\tvoid (*mark_request_commit)(struct nfs_page *, struct pnfs_layout_segment *, struct nfs_commit_info *, u32);\n\tvoid (*clear_request_commit)(struct nfs_page *, struct nfs_commit_info *);\n\tint (*scan_commit_lists)(struct nfs_commit_info *, int);\n\tvoid (*recover_commit_reqs)(struct list_head *, struct nfs_commit_info *);\n};\n\nstruct pnfs_device {\n\tstruct nfs4_deviceid dev_id;\n\tunsigned int layout_type;\n\tunsigned int mincount;\n\tunsigned int maxcount;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tunsigned char nocache: 1;\n};\n\nstruct pnfs_layoutdriver_type {\n\tstruct list_head pnfs_tblid;\n\tconst u32 id;\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int flags;\n\tunsigned int max_layoutget_response;\n\tint (*set_layoutdriver)(struct nfs_server *, const struct nfs_fh *);\n\tint (*clear_layoutdriver)(struct nfs_server *);\n\tstruct pnfs_layout_hdr * (*alloc_layout_hdr)(struct inode *, gfp_t);\n\tvoid (*free_layout_hdr)(struct pnfs_layout_hdr *);\n\tstruct pnfs_layout_segment * (*alloc_lseg)(struct pnfs_layout_hdr *, struct nfs4_layoutget_res *, gfp_t);\n\tvoid (*free_lseg)(struct pnfs_layout_segment *);\n\tvoid (*add_lseg)(struct pnfs_layout_hdr *, struct pnfs_layout_segment *, struct list_head *);\n\tvoid (*return_range)(struct pnfs_layout_hdr *, struct pnfs_layout_range *);\n\tconst struct nfs_pageio_ops *pg_read_ops;\n\tconst struct nfs_pageio_ops *pg_write_ops;\n\tstruct pnfs_ds_commit_info * (*get_ds_info)(struct inode *);\n\tint (*sync)(struct inode *, bool);\n\tenum pnfs_try_status (*read_pagelist)(struct nfs_pgio_header *);\n\tenum pnfs_try_status (*write_pagelist)(struct nfs_pgio_header *, int);\n\tvoid (*free_deviceid_node)(struct nfs4_deviceid_node *);\n\tstruct nfs4_deviceid_node * (*alloc_deviceid_node)(struct nfs_server *, struct pnfs_device *, gfp_t);\n\tint (*prepare_layoutreturn)(struct nfs4_layoutreturn_args *);\n\tvoid (*cleanup_layoutcommit)(struct nfs4_layoutcommit_data *);\n\tint (*prepare_layoutcommit)(struct nfs4_layoutcommit_args *);\n\tint (*prepare_layoutstats)(struct nfs42_layoutstat_args *);\n\tvoid (*cancel_io)(struct pnfs_layout_segment *);\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_device_id;\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_link;\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_dma {\n\tunsigned char map;\n\tunsigned char flags;\n};\n\nstruct pnp_fixup {\n\tchar id[8];\n\tvoid (*quirk_function)(struct pnp_dev *);\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_info_buffer {\n\tchar *buffer;\n\tchar *curr;\n\tlong unsigned int size;\n\tlong unsigned int len;\n\tint stop;\n\tint error;\n};\n\ntypedef struct pnp_info_buffer pnp_info_buffer_t;\n\nstruct pnp_irq {\n\tpnp_irq_mask_t map;\n\tunsigned char flags;\n};\n\nstruct pnp_mem {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_port {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_option {\n\tstruct list_head list;\n\tunsigned int flags;\n\tlong unsigned int type;\n\tunion {\n\t\tstruct pnp_port port;\n\t\tstruct pnp_irq irq;\n\t\tstruct pnp_dma dma;\n\t\tstruct pnp_mem mem;\n\t} u;\n};\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pnp_resource {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct poe_context {\n\tstruct _aarch64_ctx head;\n\t__u64 por_el0;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[9];\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct port_stats {\n\tlong unsigned int bytes_sent;\n\tlong unsigned int bytes_received;\n\tlong unsigned int bytes_discarded;\n};\n\nstruct ports_device;\n\nstruct port_buffer;\n\nstruct virtqueue;\n\nstruct port {\n\tstruct list_head list;\n\tstruct ports_device *portdev;\n\tstruct port_buffer *inbuf;\n\tspinlock_t inbuf_lock;\n\tspinlock_t outvq_lock;\n\tstruct virtqueue *in_vq;\n\tstruct virtqueue *out_vq;\n\tstruct dentry *debugfs_file;\n\tstruct port_stats stats;\n\tstruct console___2 cons;\n\tstruct cdev *cdev;\n\tstruct device *dev;\n\tstruct kref kref;\n\twait_queue_head_t waitqueue;\n\tchar *name;\n\tstruct fasync_struct *async_queue;\n\tu32 id;\n\tbool outvq_full;\n\tbool host_connected;\n\tbool guest_connected;\n};\n\nstruct port_buffer {\n\tchar *buf;\n\tsize_t size;\n\tsize_t len;\n\tsize_t offset;\n\tdma_addr_t dma;\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int sgpages;\n\tstruct scatterlist sg[0];\n};\n\nstruct port_data {\n\tint port_number;\n\tchar name[12];\n\tstruct power_supply *psy;\n\tstruct power_supply_desc psy_desc;\n\tint psy_status;\n\tint battery_percentage;\n\tint charge_type;\n\tstruct charger_data *charger;\n\tlong unsigned int last_update;\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct portdrv_service_data {\n\tstruct pcie_port_service_driver *drv;\n\tstruct device *dev;\n\tu32 service;\n};\n\nstruct virtio_console_control {\n\t__virtio32 id;\n\t__virtio16 event;\n\t__virtio16 value;\n};\n\nstruct virtio_device;\n\nstruct ports_device {\n\tstruct list_head list;\n\tstruct work_struct control_work;\n\tstruct work_struct config_work;\n\tstruct list_head ports;\n\tspinlock_t ports_lock;\n\tspinlock_t c_ivq_lock;\n\tspinlock_t c_ovq_lock;\n\tu32 max_nr_ports;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *c_ivq;\n\tstruct virtqueue *c_ovq;\n\tstruct virtio_console_control cpkt;\n\tstruct virtqueue **in_vqs;\n\tstruct virtqueue **out_vqs;\n\tint chr_major;\n};\n\nstruct ports_driver_data {\n\tstruct dentry *debugfs_dir;\n\tstruct list_head portdevs;\n\tstruct list_head consoles;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct posix_cputimers_work {\n\tstruct callback_head work;\n\tstruct mutex mutex;\n\tunsigned int scheduled;\n};\n\nstruct posix_msg_tree_node {\n\tstruct rb_node rb_node;\n\tstruct list_head msg_list;\n\tint priority;\n};\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct power_actor {\n\tu32 req_power;\n\tu32 max_power;\n\tu32 granted_power;\n\tu32 extra_actor_power;\n\tu32 weighted_req_power;\n};\n\nstruct thermal_trip;\n\nstruct power_allocator_params {\n\tbool allocated_tzp;\n\tbool update_cdevs;\n\ts64 err_integral;\n\ts32 prev_err;\n\tu32 sustainable_power;\n\tconst struct thermal_trip *trip_switch_on;\n\tconst struct thermal_trip *trip_max;\n\tint total_weight;\n\tunsigned int num_actors;\n\tunsigned int buffer_size;\n\tstruct power_actor *power;\n};\n\nstruct power_dom_info {\n\tbool state_set_sync;\n\tbool state_set_async;\n\tbool state_set_notify;\n\tchar name[64];\n};\n\nstruct power_supply_battery_info;\n\nstruct power_supply {\n\tconst struct power_supply_desc *desc;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tchar **supplied_from;\n\tsize_t num_supplies;\n\tvoid *drv_data;\n\tstruct device dev;\n\tstruct work_struct changed_work;\n\tstruct delayed_work deferred_register_work;\n\tspinlock_t changed_lock;\n\tbool changed;\n\tbool update_groups;\n\tbool initialized;\n\tbool removing;\n\tatomic_t use_cnt;\n\tstruct power_supply_battery_info *battery_info;\n\tstruct rw_semaphore extensions_sem;\n\tstruct list_head extensions;\n\tstruct thermal_zone_device *tzd;\n\tstruct thermal_cooling_device *tcd;\n\tstruct led_trigger *trig;\n\tstruct led_trigger *charging_trig;\n\tstruct led_trigger *full_trig;\n\tstruct led_trigger *charging_blink_full_solid_trig;\n\tstruct led_trigger *charging_orange_full_green_trig;\n};\n\nstruct power_supply_attr {\n\tconst char *prop_name;\n\tchar attr_name[31];\n\tstruct device_attribute dev_attr;\n\tconst char * const *text_values;\n\tint text_values_len;\n};\n\nstruct power_supply_maintenance_charge_table;\n\nstruct power_supply_battery_ocv_table;\n\nstruct power_supply_resistance_temp_table;\n\nstruct power_supply_vbat_ri_table;\n\nstruct power_supply_battery_info {\n\tunsigned int technology;\n\tint energy_full_design_uwh;\n\tint charge_full_design_uah;\n\tint voltage_min_design_uv;\n\tint voltage_max_design_uv;\n\tint tricklecharge_current_ua;\n\tint precharge_current_ua;\n\tint precharge_voltage_max_uv;\n\tint charge_term_current_ua;\n\tint charge_restart_voltage_uv;\n\tint overvoltage_limit_uv;\n\tint constant_charge_current_max_ua;\n\tint constant_charge_voltage_max_uv;\n\tconst struct power_supply_maintenance_charge_table *maintenance_charge;\n\tint maintenance_charge_size;\n\tint alert_low_temp_charge_current_ua;\n\tint alert_low_temp_charge_voltage_uv;\n\tint alert_high_temp_charge_current_ua;\n\tint alert_high_temp_charge_voltage_uv;\n\tint factory_internal_resistance_uohm;\n\tint factory_internal_resistance_charging_uohm;\n\tint ocv_temp[20];\n\tint temp_ambient_alert_min;\n\tint temp_ambient_alert_max;\n\tint temp_alert_min;\n\tint temp_alert_max;\n\tint temp_min;\n\tint temp_max;\n\tconst struct power_supply_battery_ocv_table *ocv_table[20];\n\tint ocv_table_size[20];\n\tconst struct power_supply_resistance_temp_table *resist_table;\n\tint resist_table_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_discharging;\n\tint vbat2ri_discharging_size;\n\tconst struct power_supply_vbat_ri_table *vbat2ri_charging;\n\tint vbat2ri_charging_size;\n\tint bti_resistance_ohm;\n\tint bti_resistance_tolerance;\n};\n\nstruct power_supply_battery_ocv_table {\n\tint ocv;\n\tint capacity;\n};\n\nstruct power_supply_config {\n\tstruct fwnode_handle *fwnode;\n\tvoid *drv_data;\n\tconst struct attribute_group **attr_grp;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tbool no_wakeup_source;\n};\n\nstruct power_supply_ext {\n\tconst char * const name;\n\tu8 charge_behaviours;\n\tu32 charge_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, const struct power_supply_ext *, void *, enum power_supply_property);\n};\n\nstruct power_supply_ext_registration {\n\tstruct list_head list_head;\n\tconst struct power_supply_ext *ext;\n\tstruct device *dev;\n\tvoid *data;\n};\n\nstruct power_supply_hwmon {\n\tstruct power_supply *psy;\n\tlong unsigned int *props;\n};\n\nstruct power_supply_led_trigger {\n\tstruct led_trigger trig;\n\tstruct power_supply *psy;\n};\n\nstruct power_supply_maintenance_charge_table {\n\tint charge_current_max_ua;\n\tint charge_voltage_max_uv;\n\tint charge_safety_timer_minutes;\n};\n\nstruct power_supply_resistance_temp_table {\n\tint temp;\n\tint resistance;\n};\n\nstruct power_supply_vbat_ri_table {\n\tint vbat_uv;\n\tint ri_uohm;\n};\n\nstruct scmi_powercap_state;\n\nstruct scmi_powercap_info;\n\nstruct powercap_info {\n\tint num_domains;\n\tbool notify_cap_cmd;\n\tbool notify_measurements_cmd;\n\tstruct scmi_powercap_state *states;\n\tstruct scmi_powercap_info *powercaps;\n};\n\nstruct ppb_lock {\n\tstruct flchip *chip;\n\tlong unsigned int adr;\n\tint locked;\n};\n\nstruct ppe_common_cb {\n\tstruct device *dev;\n\tstruct dsaf_device *dsaf_dev;\n\tu8 *io_base;\n\tenum ppe_common_mode ppe_mode;\n\tu8 comm_index;\n\tu32 ppe_num;\n\tstruct hns_ppe_cb ppe_cb[0];\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pps_bind_args {\n\tint tsformat;\n\tint edge;\n\tint consumer;\n};\n\nstruct pps_device;\n\nstruct pps_source_info {\n\tchar name[32];\n\tchar path[32];\n\tint mode;\n\tvoid (*echo)(struct pps_device *, int, void *);\n\tstruct module *owner;\n\tstruct device *dev;\n};\n\nstruct pps_ktime {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kparams {\n\tint api_version;\n\tint mode;\n\tstruct pps_ktime assert_off_tu;\n\tstruct pps_ktime clear_off_tu;\n};\n\nstruct pps_device {\n\tstruct pps_source_info info;\n\tstruct pps_kparams params;\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tunsigned int last_ev;\n\tunsigned int last_fetched_ev;\n\twait_queue_head_t queue;\n\tunsigned int id;\n\tconst void *lookup_cookie;\n\tstruct device dev;\n\tstruct fasync_struct *async_queue;\n\tspinlock_t lock;\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct pps_kinfo {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n};\n\nstruct pps_fdata {\n\tstruct pps_kinfo info;\n\tstruct pps_ktime timeout;\n};\n\nstruct pps_ktime_compat {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kinfo_compat {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime_compat assert_tu;\n\tstruct pps_ktime_compat clear_tu;\n\tint current_mode;\n} __attribute__((packed));\n\nstruct pps_fdata_compat {\n\tstruct pps_kinfo_compat info;\n\tstruct pps_ktime_compat timeout;\n} __attribute__((packed));\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n};\n\nstruct pre_voltage_change_data {\n\tlong unsigned int old_uV;\n\tlong unsigned int min_uV;\n\tlong unsigned int max_uV;\n};\n\nstruct preempt_ops {\n\tvoid (*sched_in)(struct preempt_notifier *, int);\n\tvoid (*sched_out)(struct preempt_notifier *, struct task_struct *);\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\tunion {\n\t\t__u8 flags;\n\t\tstruct {\n\t\t\t__u8 reserved: 4;\n\t\t\t__u8 preferpd: 1;\n\t\t\t__u8 routeraddr: 1;\n\t\t\t__u8 autoconf: 1;\n\t\t\t__u8 onlink: 1;\n\t\t};\n\t};\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct private_data {\n\tstruct list_head node;\n\tcpumask_var_t cpus;\n\tstruct device *cpu_dev;\n\tstruct cpufreq_frequency_table *freq_table;\n\tbool have_static_opps;\n\tint opp_token;\n};\n\nstruct privcmd_buf_private {\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct privcmd_buf_vma_private {\n\tstruct privcmd_buf_private *file_priv;\n\tstruct list_head list;\n\tunsigned int users;\n\tunsigned int n_pages;\n\tstruct page *pages[0];\n};\n\nstruct privcmd_data {\n\tdomid_t domid;\n};\n\nstruct privcmd_dm_op_buf;\n\nstruct privcmd_dm_op {\n\tdomid_t dom;\n\t__u16 num;\n\tconst struct privcmd_dm_op_buf *ubufs;\n};\n\nstruct privcmd_dm_op_buf {\n\tvoid *uptr;\n\tsize_t size;\n};\n\nstruct privcmd_hypercall {\n\t__u64 op;\n\t__u64 arg[5];\n};\n\nstruct privcmd_mmap_entry;\n\nstruct privcmd_mmap {\n\tint num;\n\tdomid_t dom;\n\tstruct privcmd_mmap_entry *entry;\n};\n\nstruct privcmd_mmap_entry {\n\t__u64 va;\n\t__u64 mfn;\n\t__u64 npages;\n};\n\nstruct privcmd_mmap_resource {\n\tdomid_t dom;\n\t__u32 type;\n\t__u32 id;\n\t__u32 idx;\n\t__u64 num;\n\t__u64 addr;\n};\n\nstruct privcmd_mmapbatch_v2 {\n\tunsigned int num;\n\tdomid_t dom;\n\t__u64 addr;\n\tconst xen_pfn_t *arr;\n\tint *err;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\nstruct prm_buffer {\n\tu8 prm_status;\n\tu64 efi_status;\n\tu8 prm_cmd;\n\tguid_t handler_guid;\n} __attribute__((packed));\n\nstruct prm_mmio_info;\n\nstruct prm_context_buffer {\n\tchar signature[4];\n\tu16 revision;\n\tu16 reserved;\n\tguid_t identifier;\n\tu64 static_data_buffer;\n\tstruct prm_mmio_info *mmio_ranges;\n};\n\nstruct prm_handler_info {\n\tefi_guid_t guid;\n\tefi_status_t (*handler_addr)(u64, void *);\n\tu64 static_data_buffer_addr;\n\tu64 acpi_param_buffer_addr;\n\tstruct list_head handler_list;\n};\n\nstruct prm_mmio_addr_range {\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu32 length;\n} __attribute__((packed));\n\nstruct prm_mmio_info {\n\tu64 mmio_count;\n\tstruct prm_mmio_addr_range addr_ranges[0];\n};\n\nstruct prm_module_info {\n\tguid_t guid;\n\tu16 major_rev;\n\tu16 minor_rev;\n\tu16 handler_count;\n\tstruct prm_mmio_info *mmio_info;\n\tbool updatable;\n\tstruct list_head module_list;\n\tstruct prm_handler_info handlers[0];\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct probe_entry_arg {\n\tstruct fetch_insn *code;\n\tunsigned int size;\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_nfs_info {\n\tint flag;\n\tconst char *str;\n\tconst char *nostr;\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*proc_compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tstruct timespec64 val;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n\tlong unsigned int _flags;\n\tstruct bin_attribute attr;\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*compat_ioctl)(struct sock *, unsigned int, long unsigned int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct prt_quirk {\n\tconst struct dmi_system_id *system;\n\tunsigned int segment;\n\tunsigned int bus;\n\tunsigned int device;\n\tunsigned char pin;\n\tconst char *source;\n\tconst char *actual_source;\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct psample_group {\n\tstruct list_head list;\n\tstruct net *net;\n\tu32 group_num;\n\tu32 refcount;\n\tu32 seq;\n\tstruct callback_head rcu;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n};\n\nstruct psci_boot_args {\n\tatomic_t lock;\n\tlong unsigned int pc;\n\tlong unsigned int r0;\n};\n\nstruct psci_cpuidle_data {\n\tu32 *psci_states;\n\tstruct device *dev;\n};\n\nstruct psci_cpuidle_domain_state {\n\tstruct generic_pm_domain *pd;\n\tunsigned int state_idx;\n\tu32 state;\n};\n\nstruct psci_operations {\n\tu32 (*get_version)(void);\n\tint (*cpu_suspend)(u32, long unsigned int);\n\tint (*cpu_off)(u32);\n\tint (*cpu_on)(long unsigned int, long unsigned int);\n\tint (*migrate)(long unsigned int);\n\tint (*affinity_info)(long unsigned int, long unsigned int);\n\tint (*migrate_info_type)(void);\n};\n\nstruct psci_pd_provider {\n\tstruct list_head link;\n\tstruct device_node *node;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psfp_streamfilter_counters {\n\tu64 matching_frames_count;\n\tu64 passing_frames_count;\n\tu64 not_passing_frames_count;\n\tu64 passing_sdu_count;\n\tu64 not_passing_sdu_count;\n\tu64 red_frames_count;\n};\n\nstruct psi_group {};\n\nstruct psil_endpoint_config {\n\tenum psil_endpoint_type ep_type;\n\tenum udma_tp_level channel_tpl;\n\tunsigned int pkt_mode: 1;\n\tunsigned int notdpkt: 1;\n\tunsigned int needs_epib: 1;\n\tunsigned int pdma_acc32: 1;\n\tunsigned int pdma_burst: 1;\n\tu32 psd_size;\n\ts16 mapped_channel_id;\n\tu16 flow_start;\n\tu16 flow_num;\n\ts16 default_flow_id;\n};\n\nstruct psil_ep {\n\tu32 thread_id;\n\tstruct psil_endpoint_config ep_config;\n};\n\nstruct psil_ep_map {\n\tchar *name;\n\tstruct psil_ep *src;\n\tint src_count;\n\tstruct psil_ep *dst;\n\tint dst_count;\n};\n\nstruct psmouse_protocol;\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct pstore_context {\n\tunsigned int kmsg_bytes;\n};\n\nstruct pstore_ftrace_record {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu64 ts;\n};\n\nstruct pstore_ftrace_seq_data {\n\tconst void *ptr;\n\tsize_t off;\n\tsize_t size;\n};\n\nstruct pstore_record;\n\nstruct pstore_info {\n\tstruct module *owner;\n\tconst char *name;\n\traw_spinlock_t buf_lock;\n\tchar *buf;\n\tsize_t bufsize;\n\tstruct mutex read_mutex;\n\tint flags;\n\tint max_reason;\n\tvoid *data;\n\tint (*open)(struct pstore_info *);\n\tint (*close)(struct pstore_info *);\n\tssize_t (*read)(struct pstore_record *);\n\tint (*write)(struct pstore_record *);\n\tint (*write_user)(struct pstore_record *, const char *);\n\tint (*erase)(struct pstore_record *);\n};\n\nstruct pstore_private {\n\tstruct list_head list;\n\tstruct dentry *dentry;\n\tstruct pstore_record *record;\n\tsize_t total_size;\n};\n\nstruct pstore_record {\n\tstruct pstore_info *psi;\n\tenum pstore_type_id type;\n\tu64 id;\n\tstruct timespec64 time;\n\tchar *buf;\n\tssize_t size;\n\tssize_t ecc_notice_size;\n\tvoid *priv;\n\tint count;\n\tenum kmsg_dump_reason reason;\n\tunsigned int part;\n\tbool compressed;\n};\n\nstruct psy_am_i_supplied_data {\n\tstruct power_supply *psy;\n\tunsigned int count;\n};\n\nstruct psy_for_each_psy_cb_data {\n\tint (*fn)(struct power_supply *, void *);\n\tvoid *data;\n};\n\nstruct psy_get_supplier_prop_data {\n\tstruct power_supply *psy;\n\tenum power_supply_property psp;\n\tunion power_supply_propval *val;\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\nstruct ptd {\n\t__dw dw0;\n\t__dw dw1;\n\t__dw dw2;\n\t__dw dw3;\n\t__dw dw4;\n\t__dw dw5;\n\t__dw dw6;\n\t__dw dw7;\n};\n\nstruct ptd_le32 {\n\t__le32 dw0;\n\t__le32 dw1;\n\t__le32 dw2;\n\t__le32 dw3;\n\t__le32 dw4;\n\t__le32 dw5;\n\t__le32 dw6;\n\t__le32 dw7;\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t\tatomic_t pt_share_count;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int pt_memcg_data;\n};\n\nstruct ptp_clock {\n\tstruct posix_clock clock;\n\tstruct device dev;\n\tstruct ptp_clock_info *info;\n\tdev_t devid;\n\tint index;\n\tstruct pps_device *pps_source;\n\tlong int dialed_frequency;\n\tstruct list_head tsevqs;\n\tspinlock_t tsevqs_lock;\n\tstruct mutex pincfg_mux;\n\twait_queue_head_t tsev_wq;\n\tint defunct;\n\tstruct device_attribute *pin_dev_attr;\n\tstruct attribute **pin_attr;\n\tstruct attribute_group pin_attr_group;\n\tconst struct attribute_group *pin_attr_groups[2];\n\tstruct kthread_worker *kworker;\n\tstruct kthread_delayed_work aux_work;\n\tunsigned int max_vclocks;\n\tunsigned int n_vclocks;\n\tint *vclock_index;\n\tstruct mutex n_vclocks_mux;\n\tbool is_virtual_clock;\n\tbool has_cycles;\n\tstruct dentry *debugfs_root;\n};\n\nstruct ptp_clock_caps {\n\tint max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint pps;\n\tint n_pins;\n\tint cross_timestamping;\n\tint adjust_phase;\n\tint max_phase_adj;\n\tint rsv[11];\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\ts64 offset;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_perout_request {\n\tunion {\n\t\tstruct ptp_clock_time start;\n\t\tstruct ptp_clock_time phase;\n\t};\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunion {\n\t\tstruct ptp_clock_time on;\n\t\tunsigned int rsv[4];\n\t};\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_dte {\n\tvoid *regs;\n\tstruct ptp_clock *ptp_clk;\n\tstruct ptp_clock_info caps;\n\tstruct device *dev;\n\tu32 ts_ovf_last;\n\tu32 ts_wrap_cnt;\n\tspinlock_t lock;\n\tu32 reg_val[4];\n};\n\nstruct ptp_extts_event {\n\tstruct ptp_clock_time t;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptp_qoriq_registers {\n\tstruct ctrl_regs *ctrl_regs;\n\tstruct alarm_regs *alarm_regs;\n\tstruct fiper_regs *fiper_regs;\n\tstruct etts_regs *etts_regs;\n};\n\nstruct ptp_qoriq {\n\tvoid *base;\n\tstruct ptp_qoriq_registers regs;\n\tspinlock_t lock;\n\tstruct ptp_clock *clock;\n\tstruct ptp_clock_info caps;\n\tstruct resource *rsrc;\n\tstruct device *dev;\n\tbool extts_fifo_support;\n\tbool fiper3_support;\n\tbool etsec;\n\tint irq;\n\tint phc_index;\n\tu32 tclk_period;\n\tu32 tmr_prsc;\n\tu32 tmr_add;\n\tu32 cksel;\n\tu32 tmr_fiper1;\n\tu32 tmr_fiper2;\n\tu32 tmr_fiper3;\n\tu32 (*read)(unsigned int *);\n\tvoid (*write)(unsigned int *, u32);\n};\n\nstruct ptp_sys_offset {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[51];\n};\n\nstruct ptp_sys_offset_extended {\n\tunsigned int n_samples;\n\t__kernel_clockid_t clockid;\n\tunsigned int rsv[2];\n\tstruct ptp_clock_time ts[75];\n};\n\nstruct ptp_sys_offset_precise {\n\tstruct ptp_clock_time device;\n\tstruct ptp_clock_time sys_realtime;\n\tstruct ptp_clock_time sys_monoraw;\n\tunsigned int rsv[4];\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n\tclockid_t clockid;\n};\n\nstruct ptp_tstamp {\n\tu16 sec_msb;\n\tu32 sec_lsb;\n\tu32 nsec;\n};\n\nstruct ptp_vclock {\n\tstruct ptp_clock *pclock;\n\tstruct ptp_clock_info info;\n\tstruct ptp_clock *clock;\n\tstruct hlist_node vclock_hash_node;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct mutex lock;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct ptrauth_key {\n\tlong unsigned int lo;\n\tlong unsigned int hi;\n};\n\nstruct ptrauth_keys_kernel {\n\tstruct ptrauth_key apia;\n};\n\nstruct ptrauth_keys_user {\n\tstruct ptrauth_key apia;\n\tstruct ptrauth_key apib;\n\tstruct ptrauth_key apda;\n\tstruct ptrauth_key apdb;\n\tstruct ptrauth_key apga;\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct public_key {\n\tvoid *key;\n\tu32 keylen;\n\tenum OID algo;\n\tvoid *params;\n\tu32 paramlen;\n\tbool key_is_private;\n\tconst char *id_type;\n\tconst char *pkey_algo;\n\tlong unsigned int key_eflags;\n};\n\nstruct public_key_signature {\n\tstruct asymmetric_key_id *auth_ids[3];\n\tu8 *s;\n\tu8 *m;\n\tu32 s_size;\n\tu32 m_size;\n\tbool m_free;\n\tbool algo_takes_data;\n\tconst char *pkey_algo;\n\tconst char *hash_algo;\n\tconst char *encoding;\n};\n\nstruct pvclock_vcpu_stolen_time;\n\nstruct pv_time_stolen_time_region {\n\tstruct pvclock_vcpu_stolen_time *kaddr;\n};\n\nstruct pvclock_vcpu_stolen_time {\n\t__le32 revision;\n\t__le32 attributes;\n\t__le64 stolen_time;\n\tu8 padding[48];\n};\n\nstruct pvclock_vcpu_time_info {\n\tu32 version;\n\tu32 pad0;\n\tu64 tsc_timestamp;\n\tu64 system_time;\n\tu32 tsc_to_system_mul;\n\ts8 tsc_shift;\n\tu8 flags;\n\tu8 pad[2];\n};\n\nstruct pvclock_wall_clock {\n\tu32 version;\n\tu32 sec;\n\tu32 nsec;\n\tu32 sec_hi;\n};\n\nstruct pvm_ftr_bits {\n\tbool sign;\n\tu8 shift;\n\tu8 width;\n\tu8 max_val;\n\tbool (*vm_supported)(const struct kvm *);\n};\n\nstruct pwm_args {\n\tu64 period;\n\tenum pwm_polarity polarity;\n};\n\nstruct pwm_capture {\n\tunsigned int period;\n\tunsigned int duty_cycle;\n};\n\nstruct pwm_chip;\n\nstruct pwm_cdev_data {\n\tstruct pwm_chip *chip;\n\tstruct pwm_device *pwm[0];\n};\n\ntypedef struct pwm_chip *class_pwmchip_t;\n\nstruct pwm_device {\n\tconst char *label;\n\tlong unsigned int flags;\n\tunsigned int hwpwm;\n\tstruct pwm_chip *chip;\n\tstruct pwm_args args;\n\tstruct pwm_state state;\n\tstruct pwm_state last;\n};\n\nstruct pwm_ops;\n\nstruct pwm_chip {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tconst struct pwm_ops *ops;\n\tstruct module *owner;\n\tunsigned int id;\n\tunsigned int npwm;\n\tstruct pwm_device * (*of_xlate)(struct pwm_chip *, const struct of_phandle_args *);\n\tbool atomic;\n\tstruct gpio_chip gpio;\n\tbool uses_pwmchip_alloc;\n\tbool operational;\n\tunion {\n\t\tstruct mutex nonatomic_lock;\n\t\tspinlock_t atomic_lock;\n\t};\n\tstruct pwm_device pwms[0];\n};\n\nstruct pwm_continuous_reg_data {\n\tunsigned int min_uV_dutycycle;\n\tunsigned int max_uV_dutycycle;\n\tunsigned int dutycycle_unit;\n};\n\nstruct pwm_export {\n\tstruct device pwm_dev;\n\tstruct pwm_device *pwm;\n\tstruct mutex lock;\n\tstruct pwm_state suspend;\n};\n\nstruct pwm_lookup {\n\tstruct list_head list;\n\tconst char *provider;\n\tunsigned int index;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tunsigned int period;\n\tenum pwm_polarity polarity;\n\tconst char *module;\n};\n\nstruct pwm_waveform;\n\nstruct pwm_ops {\n\tint (*request)(struct pwm_chip *, struct pwm_device *);\n\tvoid (*free)(struct pwm_chip *, struct pwm_device *);\n\tint (*capture)(struct pwm_chip *, struct pwm_device *, struct pwm_capture *, long unsigned int);\n\tsize_t sizeof_wfhw;\n\tint (*round_waveform_tohw)(struct pwm_chip *, struct pwm_device *, const struct pwm_waveform *, void *);\n\tint (*round_waveform_fromhw)(struct pwm_chip *, struct pwm_device *, const void *, struct pwm_waveform *);\n\tint (*read_waveform)(struct pwm_chip *, struct pwm_device *, void *);\n\tint (*write_waveform)(struct pwm_chip *, struct pwm_device *, const void *);\n\tint (*apply)(struct pwm_chip *, struct pwm_device *, const struct pwm_state *);\n\tint (*get_state)(struct pwm_chip *, struct pwm_device *, struct pwm_state *);\n};\n\nstruct pwm_voltages;\n\nstruct pwm_regulator_data {\n\tstruct pwm_device *pwm;\n\tstruct pwm_voltages *duty_cycle_table;\n\tstruct pwm_continuous_reg_data continuous;\n\tstruct regulator_desc desc;\n\tint state;\n\tstruct gpio_desc *enb_gpio;\n};\n\nstruct pwm_voltages {\n\tunsigned int uV;\n\tunsigned int dutycycle;\n};\n\nstruct pwm_waveform {\n\tu64 period_length_ns;\n\tu64 duty_length_ns;\n\tu64 duty_offset_ns;\n};\n\nstruct pwmchip_waveform {\n\t__u32 hwpwm;\n\t__u32 __pad;\n\t__u64 period_length_ns;\n\t__u64 duty_length_ns;\n\t__u64 duty_offset_ns;\n};\n\nstruct pwrap_slv_regops {\n\tconst struct regmap_config *regmap;\n\tint (*pwrap_read)(struct pmic_wrapper *, u32, u32 *);\n\tint (*pwrap_write)(struct pmic_wrapper *, u32, u32);\n};\n\nstruct pwrap_slv_type {\n\tconst u32 *dew_regs;\n\tenum pmic_type type;\n\tconst u32 *comp_dew_regs;\n\tenum pmic_type comp_type;\n\tconst struct pwrap_slv_regops *regops;\n\tu32 caps;\n};\n\nstruct pwrseq_device;\n\ntypedef int (*pwrseq_match_func)(struct pwrseq_device *, struct device *);\n\nstruct pwrseq_target_data;\n\nstruct pwrseq_config {\n\tstruct device *parent;\n\tstruct module *owner;\n\tvoid *drvdata;\n\tpwrseq_match_func match;\n\tconst struct pwrseq_target_data **targets;\n};\n\nstruct pwrseq_debugfs_count_ctx {\n\tstruct device *dev;\n\tloff_t index;\n};\n\nstruct pwrseq_target;\n\nstruct pwrseq_desc {\n\tstruct pwrseq_device *pwrseq;\n\tstruct pwrseq_target *target;\n\tbool powered_on;\n};\n\nstruct pwrseq_device {\n\tstruct device dev;\n\tint id;\n\tstruct module *owner;\n\tstruct rw_semaphore rw_lock;\n\tstruct mutex state_lock;\n\tpwrseq_match_func match;\n\tstruct list_head targets;\n\tstruct list_head units;\n};\n\nstruct pwrseq_match_data {\n\tstruct pwrseq_desc *desc;\n\tstruct device *dev;\n\tconst char *target;\n};\n\ntypedef int (*pwrseq_power_state_func)(struct pwrseq_device *);\n\nstruct pwrseq_unit;\n\nstruct pwrseq_target {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct pwrseq_unit *unit;\n\tpwrseq_power_state_func post_enable;\n};\n\nstruct pwrseq_unit_data;\n\nstruct pwrseq_target_data {\n\tconst char *name;\n\tconst struct pwrseq_unit_data *unit;\n\tpwrseq_power_state_func post_enable;\n};\n\nstruct pwrseq_unit {\n\tstruct kref ref;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct list_head deps;\n\tpwrseq_power_state_func enable;\n\tpwrseq_power_state_func disable;\n\tunsigned int enable_count;\n};\n\nstruct pwrseq_unit_data {\n\tconst char *name;\n\tconst struct pwrseq_unit_data **deps;\n\tpwrseq_power_state_func enable;\n\tpwrseq_power_state_func disable;\n};\n\nstruct pwrseq_unit_dep {\n\tstruct list_head list;\n\tstruct pwrseq_unit *unit;\n};\n\nstruct pxa3xx_nand_platform_data {\n\tbool keep_config;\n\tbool flash_bbt;\n\tint ecc_strength;\n\tint ecc_step_size;\n\tconst struct mtd_partition *parts;\n\tunsigned int nr_parts;\n};\n\nstruct pxa_i2c {\n\tspinlock_t lock;\n\twait_queue_head_t wait;\n\tstruct i2c_msg *msg;\n\tunsigned int msg_num;\n\tunsigned int msg_idx;\n\tunsigned int msg_ptr;\n\tunsigned int slave_addr;\n\tunsigned int req_slave_addr;\n\tstruct i2c_adapter adap;\n\tstruct clk *clk;\n\tunsigned int irqlogidx;\n\tu32 isrlog[32];\n\tu32 icrlog[32];\n\tvoid *reg_base;\n\tvoid *reg_ibmr;\n\tvoid *reg_idbr;\n\tvoid *reg_icr;\n\tvoid *reg_isr;\n\tvoid *reg_isar;\n\tvoid *reg_ilcr;\n\tvoid *reg_iwcr;\n\tlong unsigned int iobase;\n\tlong unsigned int iosize;\n\tint irq;\n\tunsigned int use_pio: 1;\n\tunsigned int fast_mode: 1;\n\tunsigned int high_mode: 1;\n\tunsigned char master_code;\n\tlong unsigned int rate;\n\tbool highmode_enter;\n\tu32 fm_mask;\n\tu32 hs_mask;\n\tstruct i2c_bus_recovery_info recovery;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pinctrl_default;\n\tstruct pinctrl_state *pinctrl_recovery;\n};\n\nstruct pxa_reg_layout {\n\tu32 ibmr;\n\tu32 idbr;\n\tu32 icr;\n\tu32 isr;\n\tu32 isar;\n\tu32 ilcr;\n\tu32 iwcr;\n\tu32 fm;\n\tu32 hs;\n};\n\nstruct qbman_acquire_desc {\n\tu8 verb;\n\tu8 reserved;\n\t__le16 bpid;\n\tu8 num;\n\tu8 reserved2[59];\n};\n\nstruct qbman_acquire_rslt {\n\tu8 verb;\n\tu8 rslt;\n\t__le16 reserved;\n\tu8 num;\n\tu8 reserved2[3];\n\t__le64 buf[7];\n};\n\nstruct qbman_alt_fq_state_desc {\n\tu8 verb;\n\tu8 reserved[3];\n\t__le32 fqid;\n\tu8 reserved2[56];\n};\n\nstruct qbman_alt_fq_state_rslt {\n\tu8 verb;\n\tu8 rslt;\n\tu8 reserved[62];\n};\n\nstruct qbman_bp_query_desc {\n\tu8 verb;\n\tu8 reserved;\n\t__le16 bpid;\n\tu8 reserved2[60];\n};\n\nstruct qbman_bp_query_rslt {\n\tu8 verb;\n\tu8 rslt;\n\tu8 reserved[4];\n\tu8 bdi;\n\tu8 state;\n\t__le32 fill;\n\t__le32 hdotr;\n\t__le16 swdet;\n\t__le16 swdxt;\n\t__le16 hwdet;\n\t__le16 hwdxt;\n\t__le16 swset;\n\t__le16 swsxt;\n\t__le16 vbpid;\n\t__le16 icid;\n\t__le64 bpscn_addr;\n\t__le64 bpscn_ctx;\n\t__le16 hw_targ;\n\tu8 dbe;\n\tu8 reserved2;\n\tu8 sdcnt;\n\tu8 hdcnt;\n\tu8 sscnt;\n\tu8 reserved3[9];\n};\n\nstruct qbman_cdan_ctrl_desc {\n\tu8 verb;\n\tu8 reserved;\n\t__le16 ch;\n\tu8 we;\n\tu8 ctrl;\n\t__le16 reserved2;\n\t__le64 cdan_ctx;\n\tu8 reserved3[48];\n};\n\nstruct qbman_cdan_ctrl_rslt {\n\tu8 verb;\n\tu8 rslt;\n\t__le16 ch;\n\tu8 reserved[60];\n};\n\nstruct qbman_eq_desc {\n\tu8 verb;\n\tu8 dca;\n\t__le16 seqnum;\n\t__le16 orpid;\n\t__le16 reserved1;\n\t__le32 tgtid;\n\t__le32 tag;\n\t__le16 qdbin;\n\tu8 qpri;\n\tu8 reserved[3];\n\tu8 wae;\n\tu8 rspid;\n\t__le64 rsp_addr;\n};\n\nstruct qbman_fq_query_desc {\n\tu8 verb;\n\tu8 reserved[3];\n\t__le32 fqid;\n\tu8 reserved2[56];\n};\n\nstruct qbman_fq_query_np_rslt {\n\tu8 verb;\n\tu8 rslt;\n\tu8 st1;\n\tu8 st2;\n\tu8 reserved[2];\n\t__le16 od1_sfdr;\n\t__le16 od2_sfdr;\n\t__le16 od3_sfdr;\n\t__le16 ra1_sfdr;\n\t__le16 ra2_sfdr;\n\t__le32 pfdr_hptr;\n\t__le32 pfdr_tptr;\n\t__le32 frm_cnt;\n\t__le32 byte_cnt;\n\t__le16 ics_surp;\n\tu8 is;\n\tu8 reserved2[29];\n};\n\nstruct qbman_pull_desc {\n\tu8 verb;\n\tu8 numf;\n\tu8 tok;\n\tu8 reserved;\n\t__le32 dq_src;\n\t__le64 rsp_addr;\n\tu64 rsp_addr_virt;\n\tu8 padding[40];\n};\n\nstruct qbman_release_desc {\n\tu8 verb;\n\tu8 reserved;\n\t__le16 bpid;\n\t__le32 reserved2;\n\t__le64 buf[7];\n};\n\nstruct qbman_swp {\n\tconst struct qbman_swp_desc *desc;\n\tvoid *addr_cena;\n\tvoid *addr_cinh;\n\tstruct {\n\t\tu32 valid_bit;\n\t} mc;\n\tstruct {\n\t\tu32 valid_bit;\n\t} mr;\n\tu32 sdq;\n\tstruct {\n\t\tatomic_t available;\n\t\tu32 valid_bit;\n\t\tstruct dpaa2_dq *storage;\n\t} vdq;\n\tstruct {\n\t\tu32 next_idx;\n\t\tu32 valid_bit;\n\t\tu8 dqrr_size;\n\t\tint reset_bug;\n\t} dqrr;\n\tstruct {\n\t\tu32 pi;\n\t\tu32 pi_vb;\n\t\tu32 pi_ring_size;\n\t\tu32 pi_ci_mask;\n\t\tu32 ci;\n\t\tint available;\n\t\tu32 pend;\n\t\tu32 no_pfdr;\n\t} eqcr;\n\tspinlock_t access_spinlock;\n\tu32 irq_threshold;\n\tu32 irq_holdoff;\n\tint use_adaptive_rx_coalesce;\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qcom_adm_peripheral_config {\n\tu32 crci;\n\tu32 mux;\n};\n\nstruct qcom_aoss_reset_map;\n\nstruct qcom_aoss_desc {\n\tconst struct qcom_aoss_reset_map *resets;\n\tsize_t num_resets;\n};\n\nstruct qcom_aoss_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tvoid *base;\n\tconst struct qcom_aoss_desc *desc;\n};\n\nstruct qcom_aoss_reset_map {\n\tunsigned int reg;\n};\n\nstruct qcom_apcs_ipc {\n\tstruct mbox_controller mbox;\n\tstruct mbox_chan mbox_chans[32];\n\tstruct regmap *regmap;\n\tlong unsigned int offset;\n\tstruct platform_device *clk;\n};\n\nstruct qcom_apcs_ipc_data {\n\tint offset;\n\tchar *clk_name;\n};\n\nstruct qcom_reset_map;\n\nstruct qcom_reset_controller {\n\tconst struct qcom_reset_map *reset_map;\n\tstruct regmap *regmap;\n\tstruct reset_controller_dev rcdev;\n};\n\nstruct qcom_cc {\n\tstruct qcom_reset_controller reset;\n\tstruct clk_regmap **rclks;\n\tsize_t num_rclks;\n\tstruct dev_pm_domain_list *pd_list;\n};\n\nstruct qcom_icc_hws_data;\n\nstruct qcom_cc_driver_data;\n\nstruct qcom_cc_desc {\n\tconst struct regmap_config *config;\n\tstruct clk_regmap **clks;\n\tsize_t num_clks;\n\tconst struct qcom_reset_map *resets;\n\tsize_t num_resets;\n\tstruct gdsc **gdscs;\n\tsize_t num_gdscs;\n\tstruct clk_hw **clk_hws;\n\tsize_t num_clk_hws;\n\tconst struct qcom_icc_hws_data *icc_hws;\n\tsize_t num_icc_hws;\n\tunsigned int icc_first_node_id;\n\tbool use_rpm;\n\tstruct qcom_cc_driver_data *driver_data;\n};\n\nstruct qcom_cc_driver_data {\n\tstruct clk_alpha_pll **alpha_plls;\n\tsize_t num_alpha_plls;\n\tu32 *clk_cbcrs;\n\tsize_t num_clk_cbcrs;\n\tconst struct clk_rcg_dfs_data *dfs_rcgs;\n\tsize_t num_dfs_rcgs;\n\tvoid (*clk_regs_configure)(struct device *, struct regmap *);\n};\n\nstruct qcom_cpufreq_data {\n\tvoid *base;\n\tstruct mutex throttle_lock;\n\tint throttle_irq;\n\tchar irq_name[15];\n\tbool cancel_throttle;\n\tstruct delayed_work throttle_work;\n\tstruct cpufreq_policy *policy;\n\tstruct clk_hw cpu_clk;\n\tbool per_core_dcvs;\n};\n\nstruct qcom_cpufreq_drv_cpu {\n\tint opp_token;\n\tstruct dev_pm_domain_list *pd_list;\n};\n\nstruct qcom_cpufreq_match_data;\n\nstruct qcom_cpufreq_drv {\n\tu32 versions;\n\tconst struct qcom_cpufreq_match_data *data;\n\tstruct qcom_cpufreq_drv_cpu cpus[0];\n};\n\nstruct qcom_cpufreq_match_data {\n\tint (*get_version)(struct device *, struct nvmem_cell *, char **, struct qcom_cpufreq_drv *);\n\tconst char **pd_names;\n\tunsigned int num_pd_names;\n};\n\nstruct qcom_cpufreq_soc_data {\n\tu32 reg_enable;\n\tu32 reg_domain_state;\n\tu32 reg_dcvs_ctrl;\n\tu32 reg_freq_lut;\n\tu32 reg_volt_lut;\n\tu32 reg_intr_clr;\n\tu32 reg_current_vote;\n\tu32 reg_perf_state;\n\tu8 lut_row_size;\n};\n\nstruct qcom_geni_device_data {\n\tbool console;\n\tenum geni_se_xfer_mode mode;\n\tstruct dev_pm_domain_attach_data pd_data;\n\tint (*resources_init)(struct uart_port *);\n\tint (*set_rate)(struct uart_port *, unsigned int);\n\tint (*power_state)(struct uart_port *, bool);\n};\n\nstruct qcom_geni_private_data {\n\tstruct uart_driver *drv;\n\tu32 poll_cached_bytes;\n\tunsigned int poll_cached_bytes_cnt;\n\tu32 write_cached_bytes;\n\tunsigned int write_cached_bytes_cnt;\n};\n\nstruct qcom_geni_serial_port {\n\tstruct uart_port uport;\n\tstruct geni_se se;\n\tconst char *name;\n\tu32 tx_fifo_depth;\n\tu32 tx_fifo_width;\n\tu32 rx_fifo_depth;\n\tdma_addr_t tx_dma_addr;\n\tdma_addr_t rx_dma_addr;\n\tbool setup;\n\tlong unsigned int poll_timeout_us;\n\tlong unsigned int clk_rate;\n\tvoid *rx_buf;\n\tu32 loopback;\n\tbool brk;\n\tunsigned int tx_remaining;\n\tunsigned int tx_queued;\n\tint wakeup_irq;\n\tbool rx_tx_swap;\n\tbool cts_rts_swap;\n\tstruct qcom_geni_private_data private_data;\n\tconst struct qcom_geni_device_data *dev_data;\n\tstruct dev_pm_domain_list *pd_list;\n};\n\nstruct qcom_glink {\n\tstruct device *dev;\n\tconst char *label;\n\tstruct qcom_glink_pipe *rx_pipe;\n\tstruct qcom_glink_pipe *tx_pipe;\n\tstruct work_struct rx_work;\n\tspinlock_t rx_lock;\n\tstruct list_head rx_queue;\n\tspinlock_t tx_lock;\n\tspinlock_t idr_lock;\n\tstruct idr lcids;\n\tstruct idr rcids;\n\tlong unsigned int features;\n\tbool intentless;\n\twait_queue_head_t tx_avail_notify;\n\tbool sent_read_notify;\n\tbool abort_tx;\n};\n\nstruct qcom_hwspinlock_of_data {\n\tu32 offset;\n\tu32 stride;\n\tconst struct regmap_config *regmap_config;\n};\n\nstruct qcom_icc_node;\n\nstruct qcom_icc_bcm {\n\tconst char *name;\n\tu32 type;\n\tu32 addr;\n\tu64 vote_x[3];\n\tu64 vote_y[3];\n\tu64 vote_scale;\n\tu32 enable_mask;\n\tbool dirty;\n\tbool keepalive;\n\tstruct bcm_db aux_data;\n\tstruct list_head list;\n\tstruct list_head ws_list;\n\tsize_t num_nodes;\n\tstruct qcom_icc_node *nodes[0];\n};\n\nstruct qcom_icc_node___2;\n\nstruct rpm_clk_resource;\n\nstruct qcom_icc_desc {\n\tstruct qcom_icc_node___2 * const *nodes;\n\tsize_t num_nodes;\n\tconst struct rpm_clk_resource *bus_clk_desc;\n\tconst char * const *intf_clocks;\n\tsize_t num_intf_clocks;\n\tbool keep_alive;\n\tenum qcom_icc_type type;\n\tconst struct regmap_config *regmap_cfg;\n\tunsigned int qos_offset;\n\tu16 ab_coeff;\n\tu16 ib_coeff;\n};\n\nstruct qcom_icc_desc___2 {\n\tconst struct regmap_config *config;\n\tstruct qcom_icc_node * const *nodes;\n\tsize_t num_nodes;\n\tstruct qcom_icc_bcm * const *bcms;\n\tsize_t num_bcms;\n\tbool qos_requires_clocks;\n};\n\nstruct qcom_icc_hws_data {\n\tint master_id;\n\tint slave_id;\n\tint clk_id;\n};\n\nstruct qcom_icc_qosbox;\n\nstruct qcom_icc_node {\n\tconst char *name;\n\tstruct icc_node *node;\n\tu16 num_links;\n\tu16 channels;\n\tu16 buswidth;\n\tu64 sum_avg[3];\n\tu64 max_peak[3];\n\tstruct qcom_icc_bcm *bcms[3];\n\tsize_t num_bcms;\n\tconst struct qcom_icc_qosbox *qosbox;\n\tstruct qcom_icc_node *link_nodes[0];\n};\n\nstruct qcom_icc_qos {\n\tu32 areq_prio;\n\tu32 prio_level;\n\tbool limit_commands;\n\tbool ap_owned;\n\tint qos_mode;\n\tint qos_port;\n\tbool urg_fwd_en;\n};\n\nstruct qcom_icc_node___2 {\n\tunsigned char *name;\n\tu16 id;\n\tconst u16 *links;\n\tu16 num_links;\n\tu16 channels;\n\tu16 buswidth;\n\tconst struct rpm_clk_resource *bus_clk_desc;\n\tu64 sum_avg[2];\n\tu64 max_peak[2];\n\tint mas_rpm_id;\n\tint slv_rpm_id;\n\tstruct qcom_icc_qos qos;\n\tu16 ab_coeff;\n\tu16 ib_coeff;\n\tu32 bus_clk_rate[2];\n};\n\nstruct qcom_icc_provider {\n\tstruct icc_provider provider;\n\tint num_intf_clks;\n\tenum qcom_icc_type type;\n\tstruct regmap *regmap;\n\tunsigned int qos_offset;\n\tu16 ab_coeff;\n\tu16 ib_coeff;\n\tu32 bus_clk_rate[2];\n\tconst struct rpm_clk_resource *bus_clk_desc;\n\tstruct clk *bus_clk;\n\tstruct clk_bulk_data *intf_clks;\n\tbool keep_alive;\n\tbool is_on;\n};\n\nstruct qcom_icc_provider___2 {\n\tstruct icc_provider provider;\n\tstruct device *dev;\n\tstruct qcom_icc_bcm * const *bcms;\n\tsize_t num_bcms;\n\tstruct bcm_voter *voter;\n\tstruct qcom_icc_node * const *nodes;\n\tsize_t num_nodes;\n\tstruct regmap *regmap;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct qcom_icc_qosbox {\n\tconst u32 prio;\n\tconst bool urg_fwd;\n\tconst bool prio_fwd_disable;\n\tconst u32 num_ports;\n\tconst u32 port_offsets[4];\n};\n\nstruct qcom_iommu_ctx {\n\tstruct device *dev;\n\tvoid *base;\n\tbool secure_init;\n\tbool secured_ctx;\n\tu8 asid;\n\tstruct iommu_domain *domain;\n};\n\nstruct qcom_iommu_dev {\n\tstruct iommu_device iommu;\n\tstruct device *dev;\n\tstruct clk_bulk_data clks[3];\n\tvoid *local_base;\n\tu32 sec_id;\n\tu8 max_asid;\n\tstruct qcom_iommu_ctx *ctxs[0];\n};\n\nstruct qcom_iommu_domain {\n\tstruct io_pgtable_ops *pgtbl_ops;\n\tspinlock_t pgtbl_lock;\n\tstruct mutex init_mutex;\n\tstruct iommu_domain domain;\n\tstruct qcom_iommu_dev *iommu;\n\tstruct iommu_fwspec *fwspec;\n};\n\nstruct qcom_ipcc_chan_info;\n\nstruct qcom_ipcc {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct irq_domain *irq_domain;\n\tstruct mbox_chan *chans;\n\tstruct qcom_ipcc_chan_info *mchan;\n\tstruct mbox_controller mbox;\n\tint num_chans;\n\tint irq;\n};\n\nstruct qcom_ipcc_chan_info {\n\tu16 client_id;\n\tu16 signal_id;\n};\n\nstruct qcom_mpm_priv {\n\tvoid *base;\n\traw_spinlock_t lock;\n\tstruct mbox_client mbox_client;\n\tstruct mbox_chan *mbox_chan;\n\tstruct mpm_gic_map *maps;\n\tunsigned int map_cnt;\n\tunsigned int reg_stride;\n\tstruct irq_domain *domain;\n\tstruct generic_pm_domain genpd;\n};\n\nstruct qcom_nand_boot_partition {\n\tu32 page_offset;\n\tu32 page_size;\n};\n\nstruct qpic_spi_nand;\n\nstruct qcom_nandc_props;\n\nstruct qcom_nand_controller {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *core_clk;\n\tstruct clk *aon_clk;\n\tstruct nandc_regs *regs;\n\tstruct bam_transaction *bam_txn;\n\tconst struct qcom_nandc_props *props;\n\tstruct nand_controller *controller;\n\tstruct qpic_spi_nand *qspi;\n\tstruct list_head host_list;\n\tunion {\n\t\tstruct {\n\t\t\tstruct dma_chan *tx_chan;\n\t\t\tstruct dma_chan *rx_chan;\n\t\t\tstruct dma_chan *cmd_chan;\n\t\t};\n\t\tstruct {\n\t\t\tstruct dma_chan *chan;\n\t\t\tunsigned int cmd_crci;\n\t\t\tunsigned int data_crci;\n\t\t};\n\t};\n\tstruct list_head desc_list;\n\tu8 *data_buffer;\n\t__le32 *reg_read_buf;\n\tphys_addr_t base_phys;\n\tdma_addr_t base_dma;\n\tdma_addr_t reg_read_dma;\n\tint buf_size;\n\tint buf_count;\n\tint buf_start;\n\tunsigned int max_cwperpage;\n\tint reg_read_pos;\n\tu32 cmd1;\n\tu32 vld;\n\tbool exec_opwrite;\n};\n\nstruct qcom_nand_host {\n\tstruct qcom_nand_boot_partition *boot_partitions;\n\tstruct nand_chip chip;\n\tstruct list_head node;\n\tint nr_boot_partitions;\n\tint cs;\n\tint cw_size;\n\tint cw_data;\n\tint ecc_bytes_hw;\n\tint spare_bytes;\n\tint bbm_size;\n\tint last_command;\n\tu32 cfg0;\n\tu32 cfg1;\n\tu32 cfg0_raw;\n\tu32 cfg1_raw;\n\tu32 ecc_buf_cfg;\n\tu32 ecc_bch_cfg;\n\tu32 clrflashstatus;\n\tu32 clrreadstatus;\n\tu8 status;\n\tbool codeword_fixup;\n\tbool use_ecc;\n\tbool bch_enabled;\n};\n\nstruct qcom_nandc_props {\n\tu32 ecc_modes;\n\tu32 dev_cmd_reg_start;\n\tu32 bam_offset;\n\tbool supports_bam;\n\tbool nandc_part_of_qpic;\n\tbool qpic_version2;\n\tbool use_codeword_fixup;\n};\n\nstruct qcom_op {\n\tconst struct nand_op_instr *data_instr;\n\tunsigned int data_instr_idx;\n\tunsigned int rdy_timeout_ms;\n\tunsigned int rdy_delay_ns;\n\t__le32 addr1_reg;\n\t__le32 addr2_reg;\n\t__le32 cmd_reg;\n\tu8 flag;\n};\n\nstruct qcom_pcie_resources_1_0_0 {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct reset_control *core;\n\tstruct regulator *vdda;\n};\n\nstruct qcom_pcie_resources_2_1_0 {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct reset_control_bulk_data resets[6];\n\tint num_resets;\n\tstruct regulator_bulk_data supplies[3];\n};\n\nstruct qcom_pcie_resources_2_3_2 {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct regulator_bulk_data supplies[2];\n};\n\nstruct qcom_pcie_resources_2_3_3 {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct reset_control_bulk_data rst[7];\n};\n\nstruct qcom_pcie_resources_2_4_0 {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct reset_control_bulk_data resets[12];\n\tint num_resets;\n};\n\nstruct qcom_pcie_resources_2_7_0 {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct regulator_bulk_data supplies[2];\n\tstruct reset_control *rst;\n};\n\nstruct qcom_pcie_resources_2_9_0 {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct reset_control *rst;\n};\n\nunion qcom_pcie_resources {\n\tstruct qcom_pcie_resources_1_0_0 v1_0_0;\n\tstruct qcom_pcie_resources_2_1_0 v2_1_0;\n\tstruct qcom_pcie_resources_2_3_2 v2_3_2;\n\tstruct qcom_pcie_resources_2_3_3 v2_3_3;\n\tstruct qcom_pcie_resources_2_4_0 v2_4_0;\n\tstruct qcom_pcie_resources_2_7_0 v2_7_0;\n\tstruct qcom_pcie_resources_2_9_0 v2_9_0;\n};\n\nstruct qcom_pcie_cfg;\n\nstruct qcom_pcie {\n\tstruct dw_pcie *pci;\n\tvoid *parf;\n\tvoid *mhi;\n\tunion qcom_pcie_resources res;\n\tstruct icc_path *icc_mem;\n\tstruct icc_path *icc_cpu;\n\tconst struct qcom_pcie_cfg *cfg;\n\tstruct dentry *debugfs;\n\tstruct list_head ports;\n\tbool suspended;\n\tbool use_pm_opp;\n};\n\nstruct qcom_pcie_ops;\n\nstruct qcom_pcie_cfg {\n\tconst struct qcom_pcie_ops *ops;\n\tbool override_no_snoop;\n\tbool firmware_managed;\n\tbool no_l0s;\n};\n\nstruct qcom_pcie_ops {\n\tint (*get_resources)(struct qcom_pcie *);\n\tint (*init)(struct qcom_pcie *);\n\tint (*post_init)(struct qcom_pcie *);\n\tvoid (*host_post_init)(struct qcom_pcie *);\n\tvoid (*deinit)(struct qcom_pcie *);\n\tvoid (*ltssm_enable)(struct qcom_pcie *);\n\tint (*config_sid)(struct qcom_pcie *);\n};\n\nstruct qcom_pcie_perst {\n\tstruct list_head list;\n\tstruct gpio_desc *desc;\n};\n\nstruct qcom_pcie_port {\n\tstruct list_head list;\n\tstruct phy *phy;\n\tstruct list_head perst;\n};\n\nstruct qcom_phy_hw_stats {\n\tu64 rx_pkts;\n\tu64 rx_err_pkts;\n\tu64 tx_pkts;\n\tu64 tx_err_pkts;\n};\n\nstruct qcom_reset_map {\n\tunsigned int reg;\n\tu8 bit;\n\tu16 udelay;\n\tu32 bitmask;\n};\n\nstruct qcom_rpm_header {\n\t__le32 service_type;\n\t__le32 length;\n};\n\nstruct qcom_rpm_message {\n\t__le32 msg_type;\n\t__le32 length;\n\tunion {\n\t\t__le32 msg_id;\n\t\tstruct {\n\t\t\tstruct {} __empty_message;\n\t\t\tu8 message[0];\n\t\t};\n\t};\n};\n\nstruct qcom_rpm_reg {\n\tstruct device *dev;\n\tu32 type;\n\tu32 id;\n\tstruct regulator_desc desc;\n\tint is_enabled;\n\tint uV;\n\tu32 load;\n\tunsigned int enabled_updated: 1;\n\tunsigned int uv_updated: 1;\n\tunsigned int load_updated: 1;\n};\n\nstruct qcom_rpm_request {\n\t__le32 msg_id;\n\t__le32 flags;\n\t__le32 type;\n\t__le32 id;\n\t__le32 data_len;\n};\n\nstruct qcom_tzmem_pool;\n\nstruct qcom_scm {\n\tstruct device *dev;\n\tstruct clk *core_clk;\n\tstruct clk *iface_clk;\n\tstruct clk *bus_clk;\n\tstruct icc_path *path;\n\tstruct completion *waitq_comps;\n\tstruct reset_controller_dev reset;\n\tstruct mutex scm_bw_lock;\n\tint scm_vote_count;\n\tu64 dload_mode_addr;\n\tstruct qcom_tzmem_pool *mempool;\n\tunsigned int wq_cnt;\n};\n\nstruct qcom_scm_current_perm_info {\n\t__le32 vmid;\n\t__le32 perm;\n\t__le64 ctx;\n\t__le32 ctx_size;\n\t__le32 unused;\n};\n\nstruct qcom_scm_desc {\n\tu32 svc;\n\tu32 cmd;\n\tu32 arginfo;\n\tu64 args[10];\n\tu32 owner;\n};\n\nstruct qcom_scm_hdcp_req {\n\tu32 addr;\n\tu32 val;\n};\n\nstruct qcom_scm_mem_map_info {\n\t__le64 mem_addr;\n\t__le64 mem_size;\n};\n\nstruct qcom_scm_pas_context {\n\tstruct device *dev;\n\tu32 pas_id;\n\tphys_addr_t mem_phys;\n\tsize_t mem_size;\n\tvoid *ptr;\n\tdma_addr_t phys;\n\tssize_t size;\n\tbool use_tzmem;\n};\n\nstruct qcom_scm_qseecom_resp {\n\tu64 result;\n\tu64 resp_type;\n\tu64 data;\n};\n\nstruct qcom_scm_res {\n\tu64 result[3];\n};\n\nstruct qcom_scm_vmperm {\n\tint vmid;\n\tint perm;\n};\n\nstruct qcom_smd_alloc_entry {\n\tu8 name[20];\n\t__le32 cid;\n\t__le32 flags;\n\t__le32 ref_count;\n};\n\nstruct qcom_smd_edge;\n\nstruct qcom_smd_endpoint;\n\nstruct smd_channel_info_pair;\n\nstruct smd_channel_info_word_pair;\n\nstruct qcom_smd_channel {\n\tstruct qcom_smd_edge *edge;\n\tstruct qcom_smd_endpoint *qsept;\n\tbool registered;\n\tchar *name;\n\tenum smd_channel_state state;\n\tenum smd_channel_state remote_state;\n\twait_queue_head_t state_change_event;\n\tstruct smd_channel_info_pair *info;\n\tstruct smd_channel_info_word_pair *info_word;\n\tspinlock_t tx_lock;\n\twait_queue_head_t fblockread_event;\n\tvoid *tx_fifo;\n\tvoid *rx_fifo;\n\tint fifo_size;\n\tvoid *bounce_buffer;\n\tspinlock_t recv_lock;\n\tint pkt_size;\n\tvoid *drvdata;\n\tstruct list_head list;\n};\n\nstruct rpmsg_device_id {\n\tchar name[32];\n\tkernel_ulong_t driver_data;\n};\n\nstruct rpmsg_device_ops;\n\nstruct rpmsg_device {\n\tstruct device dev;\n\tstruct rpmsg_device_id id;\n\tconst char *driver_override;\n\tu32 src;\n\tu32 dst;\n\tstruct rpmsg_endpoint *ept;\n\tbool announce;\n\tbool little_endian;\n\tconst struct rpmsg_device_ops *ops;\n};\n\nstruct qcom_smd_device {\n\tstruct rpmsg_device rpdev;\n\tstruct qcom_smd_edge *edge;\n};\n\nstruct qcom_smd_edge {\n\tstruct device dev;\n\tconst char *name;\n\tstruct device_node *of_node;\n\tunsigned int edge_id;\n\tunsigned int remote_pid;\n\tint irq;\n\tstruct regmap *ipc_regmap;\n\tint ipc_offset;\n\tint ipc_bit;\n\tstruct mbox_client mbox_client;\n\tstruct mbox_chan *mbox_chan;\n\tstruct list_head channels;\n\tspinlock_t channels_lock;\n\tlong unsigned int allocated[2];\n\tunsigned int smem_available;\n\twait_queue_head_t new_channel_event;\n\tstruct work_struct scan_work;\n\tstruct work_struct state_work;\n};\n\nstruct qcom_smd_endpoint {\n\tstruct rpmsg_endpoint ept;\n\tstruct qcom_smd_channel *qsch;\n};\n\nstruct qcom_smd_rpm {\n\tstruct rpmsg_endpoint *rpm_channel;\n\tstruct device *dev;\n\tstruct completion ack;\n\tstruct mutex lock;\n\tint ack_status;\n};\n\nstruct smem_partition {\n\tvoid *virt_base;\n\tphys_addr_t phys_base;\n\tsize_t cacheline;\n\tsize_t size;\n};\n\nstruct smem_region {\n\tphys_addr_t aux_base;\n\tvoid *virt_base;\n\tsize_t size;\n};\n\nstruct smem_ptable;\n\nstruct qcom_smem {\n\tstruct device *dev;\n\tstruct hwspinlock *hwlock;\n\tu32 item_count;\n\tstruct platform_device *socinfo;\n\tstruct smem_ptable *ptable;\n\tstruct smem_partition global_partition;\n\tstruct smem_partition partitions[25];\n\tunsigned int num_regions;\n\tstruct smem_region regions[0];\n};\n\nstruct qcom_smem_state_ops {\n\tint (*update_bits)(void *, u32, u32);\n};\n\nstruct qcom_smem_state {\n\tstruct kref refcount;\n\tbool orphan;\n\tstruct list_head list;\n\tstruct device_node *of_node;\n\tvoid *priv;\n\tstruct qcom_smem_state_ops ops;\n};\n\nstruct qcom_smmu_match_data;\n\nstruct qcom_smmu {\n\tstruct arm_smmu_device___2 smmu;\n\tconst struct qcom_smmu_match_data *data;\n\tbool bypass_quirk;\n\tu8 bypass_cbndx;\n\tu32 stall_enabled;\n};\n\nstruct qcom_smmu_config {\n\tconst u32 *reg_offset;\n};\n\nstruct qcom_smmu_match_data {\n\tconst struct qcom_smmu_config *cfg;\n\tconst struct arm_smmu_impl *impl;\n\tconst struct arm_smmu_impl *adreno_impl;\n\tconst struct of_device_id * const client_match;\n};\n\nstruct smp2p_smem_item;\n\nstruct qcom_smp2p {\n\tstruct device *dev;\n\tstruct smp2p_smem_item *in;\n\tstruct smp2p_smem_item *out;\n\tunsigned int smem_items[2];\n\tunsigned int valid_entries;\n\tbool ssr_ack_enabled;\n\tbool ssr_ack;\n\tbool negotiation_done;\n\tunsigned int local_pid;\n\tunsigned int remote_pid;\n\tstruct regmap *ipc_regmap;\n\tint ipc_offset;\n\tint ipc_bit;\n\tstruct mbox_client mbox_client;\n\tstruct mbox_chan *mbox_chan;\n\tstruct list_head inbound;\n\tstruct list_head outbound;\n};\n\nstruct smsm_entry;\n\nstruct smsm_host;\n\nstruct qcom_smsm {\n\tstruct device *dev;\n\tu32 local_host;\n\tu32 num_hosts;\n\tu32 num_entries;\n\tu32 *local_state;\n\tu32 *subscription;\n\tstruct qcom_smem_state *state;\n\tspinlock_t lock;\n\tstruct smsm_entry *entries;\n\tstruct smsm_host *hosts;\n\tstruct mbox_client mbox_client;\n};\n\nstruct qcom_spmi_pmic {\n\tunsigned int type;\n\tunsigned int subtype;\n\tunsigned int major;\n\tunsigned int minor;\n\tunsigned int rev2;\n\tunsigned int fab_id;\n\tconst char *name;\n};\n\nstruct qcom_spmi_dev {\n\tint num_usids;\n\tstruct qcom_spmi_pmic pmic;\n};\n\nstruct qcom_tzmem_area {\n\tstruct list_head list;\n\tvoid *vaddr;\n\tdma_addr_t paddr;\n\tsize_t size;\n\tvoid *priv;\n};\n\nstruct qcom_tzmem_chunk {\n\tsize_t size;\n\tstruct qcom_tzmem_pool *owner;\n};\n\nstruct qcom_tzmem_pool {\n\tstruct gen_pool *genpool;\n\tstruct list_head areas;\n\tenum qcom_tzmem_policy policy;\n\tsize_t increment;\n\tsize_t max_size;\n\tspinlock_t lock;\n};\n\nstruct qcom_tzmem_pool_config {\n\tsize_t initial_size;\n\tenum qcom_tzmem_policy policy;\n\tsize_t increment;\n\tsize_t max_size;\n};\n\nstruct qseecom_client;\n\nstruct qcuefi_client {\n\tstruct qseecom_client *client;\n\tstruct efivars efivars;\n\tstruct qcom_tzmem_pool *mempool;\n};\n\nstruct qdisc_dump_args {\n\tstruct qdisc_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct qdisc_rate_table {\n\tstruct tc_ratespec rate;\n\tu32 data[256];\n\tstruct qdisc_rate_table *next;\n\tint refcnt;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_watchdog {\n\tstruct hrtimer timer;\n\tstruct Qdisc *qdisc;\n};\n\nstruct qfprom_soc_data;\n\nstruct qfprom_priv {\n\tvoid *qfpraw;\n\tvoid *qfpconf;\n\tvoid *qfpcorrected;\n\tvoid *qfpsecurity;\n\tstruct device *dev;\n\tstruct clk *secclk;\n\tstruct regulator *vcc;\n\tconst struct qfprom_soc_data *soc_data;\n};\n\nstruct qfprom_soc_compatible_data {\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n};\n\nstruct qfprom_soc_data {\n\tu32 accel_value;\n\tu32 qfprom_blow_timer_value;\n\tu32 qfprom_blow_set_freq;\n\tint qfprom_blow_uV;\n};\n\nstruct qfprom_touched_values {\n\tlong unsigned int clk_rate;\n\tu32 accel_val;\n\tu32 timer_val;\n};\n\nstruct qm_addr {\n\tvoid *ce;\n\t__be32 *ce_be;\n\tvoid *ci;\n};\n\nstruct qm_dqrr {\n\tconst struct qm_dqrr_entry *ring;\n\tconst struct qm_dqrr_entry *cursor;\n\tu8 pi;\n\tu8 ci;\n\tu8 fill;\n\tu8 ithresh;\n\tu8 vbit;\n};\n\nstruct qm_fd {\n\tunion {\n\t\tstruct {\n\t\t\tu8 cfg8b_w1;\n\t\t\tu8 bpid;\n\t\t\tu8 cfg8b_w3;\n\t\t\tu8 addr_hi;\n\t\t\t__be32 addr_lo;\n\t\t};\n\t\t__be64 data;\n\t};\n\t__be32 cfg;\n\tunion {\n\t\t__be32 cmd;\n\t\t__be32 status;\n\t};\n};\n\nstruct qm_dqrr_entry {\n\tu8 verb;\n\tu8 stat;\n\t__be16 seqnum;\n\tu8 tok;\n\tu8 __reserved2[3];\n\t__be32 fqid;\n\t__be32 context_b;\n\tstruct qm_fd fd;\n\tu8 __reserved4[32];\n};\n\nstruct qm_eadr {\n\tu32 info;\n};\n\nstruct qm_ecir {\n\tu32 info;\n};\n\nstruct qm_ecir2 {\n\tu32 info;\n};\n\nstruct qm_eqcr_entry;\n\nstruct qm_eqcr {\n\tstruct qm_eqcr_entry *ring;\n\tstruct qm_eqcr_entry *cursor;\n\tu8 ci;\n\tu8 available;\n\tu8 ithresh;\n\tu8 vbit;\n};\n\nstruct qm_eqcr_entry {\n\tu8 _ncw_verb;\n\tu8 dca;\n\t__be16 seqnum;\n\tu8 __reserved[4];\n\t__be32 fqid;\n\t__be32 tag;\n\tstruct qm_fd fd;\n\tu8 __reserved3[32];\n};\n\nstruct qm_fqd_oac {\n\tu8 oac;\n\ts8 oal;\n};\n\nstruct qm_fqd_stashing {\n\tu8 exclusive;\n\tu8 cl;\n};\n\nstruct qm_fqd {\n\tu8 orpc;\n\tu8 cgid;\n\t__be16 fq_ctrl;\n\t__be16 dest_wq;\n\t__be16 ics_cred;\n\tunion {\n\t\t__be16 td;\n\t\tstruct qm_fqd_oac oac_init;\n\t};\n\t__be32 context_b;\n\tunion {\n\t\t__be64 opaque;\n\t\tstruct {\n\t\t\t__be32 hi;\n\t\t\t__be32 lo;\n\t\t};\n\t\tstruct {\n\t\t\tstruct qm_fqd_stashing stashing;\n\t\t\t__be16 context_hi;\n\t\t\t__be32 context_lo;\n\t\t};\n\t} context_a;\n\tstruct qm_fqd_oac oac_query;\n} __attribute__((packed));\n\nunion qm_mc_command;\n\nunion qm_mc_result;\n\nstruct qm_mc {\n\tunion qm_mc_command *cr;\n\tunion qm_mc_result *rr;\n\tu8 rridx;\n\tu8 vbit;\n};\n\nstruct qm_mcc_initfq {\n\tu8 __reserved1[2];\n\t__be16 we_mask;\n\t__be32 fqid;\n\t__be16 count;\n\tstruct qm_fqd fqd;\n\tu8 __reserved2[30];\n};\n\nstruct qm_mcc_initcgr {\n\tu8 __reserve1[2];\n\t__be16 we_mask;\n\tstruct __qm_mc_cgr cgr;\n\tu8 __reserved2[2];\n\tu8 cgid;\n\tu8 __reserved3[32];\n};\n\nstruct qm_mcc_fq {\n\tu8 _ncw_verb;\n\tu8 __reserved1[3];\n\t__be32 fqid;\n\tu8 __reserved2[56];\n};\n\nstruct qm_mcc_cgr {\n\tu8 _ncw_verb;\n\tu8 __reserved1[30];\n\tu8 cgid;\n\tu8 __reserved2[32];\n};\n\nunion qm_mc_command {\n\tstruct {\n\t\tu8 _ncw_verb;\n\t\tu8 __reserved[63];\n\t};\n\tstruct qm_mcc_initfq initfq;\n\tstruct qm_mcc_initcgr initcgr;\n\tstruct qm_mcc_fq fq;\n\tstruct qm_mcc_cgr cgr;\n};\n\nstruct qm_mcr_queryfq {\n\tu8 verb;\n\tu8 result;\n\tu8 __reserved1[8];\n\tstruct qm_fqd fqd;\n\tu8 __reserved2[30];\n};\n\nstruct qm_mcr_alterfq {\n\tu8 verb;\n\tu8 result;\n\tu8 fqs;\n\tu8 __reserved1[61];\n};\n\nstruct qm_mcr_querycgr {\n\tu8 verb;\n\tu8 result;\n\tu16 __reserved1;\n\tstruct __qm_mc_cgr cgr;\n\tu8 __reserved2[6];\n\tu8 i_bcnt_hi;\n\t__be32 i_bcnt_lo;\n\tu8 __reserved3[3];\n\tu8 a_bcnt_hi;\n\t__be32 a_bcnt_lo;\n\t__be32 cscn_targ_swp[4];\n};\n\nstruct qm_mcr_querycongestion {\n\tu8 verb;\n\tu8 result;\n\tu8 __reserved[30];\n\tstruct __qm_mcr_querycongestion state;\n};\n\nstruct qm_mcr_querywq {\n\tu8 verb;\n\tu8 result;\n\tu16 channel_wq;\n\tu8 __reserved[28];\n\tu32 wq_len[8];\n};\n\nstruct qm_mcr_queryfq_np {\n\tu8 verb;\n\tu8 result;\n\tu8 __reserved1;\n\tu8 state;\n\tu32 fqd_link;\n\tu16 odp_seq;\n\tu16 orp_nesn;\n\tu16 orp_ea_hseq;\n\tu16 orp_ea_tseq;\n\tu32 orp_ea_hptr;\n\tu32 orp_ea_tptr;\n\tu32 pfdr_hptr;\n\tu32 pfdr_tptr;\n\tu8 __reserved2[5];\n\tu8 is;\n\tu16 ics_surp;\n\tu32 byte_cnt;\n\tu32 frm_cnt;\n\tu32 __reserved3;\n\tu16 ra1_sfdr;\n\tu16 ra2_sfdr;\n\tu16 __reserved4;\n\tu16 od1_sfdr;\n\tu16 od2_sfdr;\n\tu16 od3_sfdr;\n};\n\nunion qm_mc_result {\n\tstruct {\n\t\tu8 verb;\n\t\tu8 result;\n\t\tu8 __reserved1[62];\n\t};\n\tstruct qm_mcr_queryfq queryfq;\n\tstruct qm_mcr_alterfq alterfq;\n\tstruct qm_mcr_querycgr querycgr;\n\tstruct qm_mcr_querycongestion querycongestion;\n\tstruct qm_mcr_querywq querywq;\n\tstruct qm_mcr_queryfq_np queryfq_np;\n};\n\nstruct qm_mr {\n\tunion qm_mr_entry *ring;\n\tunion qm_mr_entry *cursor;\n\tu8 pi;\n\tu8 ci;\n\tu8 fill;\n\tu8 ithresh;\n\tu8 vbit;\n};\n\nunion qm_mr_entry {\n\tstruct {\n\t\tu8 verb;\n\t\tu8 __reserved[63];\n\t};\n\tstruct {\n\t\tu8 verb;\n\t\tu8 dca;\n\t\t__be16 seqnum;\n\t\tu8 rc;\n\t\tu8 __reserved[3];\n\t\t__be32 fqid;\n\t\t__be32 tag;\n\t\tstruct qm_fd fd;\n\t\tu8 __reserved1[32];\n\t} ern;\n\tstruct {\n\t\tu8 verb;\n\t\tu8 fqs;\n\t\tu8 __reserved1[6];\n\t\t__be32 fqid;\n\t\t__be32 context_b;\n\t\tu8 __reserved2[48];\n\t} fq;\n};\n\nstruct qm_portal {\n\tstruct qm_addr addr;\n\tstruct qm_eqcr eqcr;\n\tstruct qm_dqrr dqrr;\n\tstruct qm_mr mr;\n\tstruct qm_mc mc;\n\tlong: 64;\n};\n\nstruct qm_portal_config {\n\tvoid *addr_virt_ce;\n\tvoid *addr_virt_ci;\n\tstruct device *dev;\n\tstruct iommu_domain *iommu_domain;\n\tstruct list_head list;\n\tint cpu;\n\tint irq;\n\tu16 channel;\n\tu32 pools;\n};\n\nstruct qm_sg_entry {\n\tunion {\n\t\tstruct {\n\t\t\tu8 __reserved1[3];\n\t\t\tu8 addr_hi;\n\t\t\t__be32 addr_lo;\n\t\t};\n\t\t__be64 data;\n\t};\n\t__be32 cfg;\n\tu8 __reserved2;\n\tu8 bpid;\n\t__be16 offset;\n};\n\nstruct qman_cgrs {\n\tstruct __qm_mcr_querycongestion q;\n};\n\nstruct qman_error_info_mdata {\n\tu16 addr_mask;\n\tu16 bits;\n\tconst char *txt;\n};\n\nstruct qman_hwerr_txt {\n\tu32 mask;\n\tconst char *txt;\n};\n\nstruct qman_portal {\n\tstruct qm_portal p;\n\tlong unsigned int bits;\n\tlong unsigned int irq_sources;\n\tu32 use_eqcr_ci_stashing;\n\tstruct qman_fq *vdqcr_owned;\n\tu32 sdqcr;\n\tconst struct qm_portal_config *config;\n\tstruct qman_cgrs *cgrs;\n\tstruct list_head cgr_cbs;\n\traw_spinlock_t cgr_lock;\n\tstruct work_struct congestion_work;\n\tstruct work_struct mr_work;\n\tchar irqname[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct qmp_cooling_device;\n\nstruct qmp {\n\tvoid *msgram;\n\tstruct device *dev;\n\tstruct mbox_client mbox_client;\n\tstruct mbox_chan *mbox_chan;\n\tsize_t offset;\n\tsize_t size;\n\twait_queue_head_t event;\n\tstruct mutex tx_lock;\n\tstruct clk_hw qdss_clk;\n\tstruct qmp_cooling_device *cooling_devs;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_files[4];\n};\n\nstruct qmp_cooling_device {\n\tstruct thermal_cooling_device *cdev;\n\tstruct qmp *qmp;\n\tchar *name;\n\tbool state;\n};\n\nstruct qmp_debugfs_entry {\n\tconst char *name;\n\tconst char *fmt;\n\tbool is_bool;\n\tconst char *true_val;\n\tconst char *false_val;\n};\n\nstruct qmu_gpd {\n\t__le32 dw0_info;\n\t__le32 next_gpd;\n\t__le32 buffer;\n\t__le32 dw3_info;\n};\n\nstruct qnode {\n\tstruct mcs_spinlock mcs;\n};\n\nstruct qsee_req_uefi_get_next_variable {\n\tu32 command_id;\n\tu32 length;\n\tu32 guid_offset;\n\tu32 guid_size;\n\tu32 name_offset;\n\tu32 name_size;\n};\n\nstruct qsee_req_uefi_get_variable {\n\tu32 command_id;\n\tu32 length;\n\tu32 name_offset;\n\tu32 name_size;\n\tu32 guid_offset;\n\tu32 guid_size;\n\tu32 data_size;\n};\n\nstruct qsee_req_uefi_query_variable_info {\n\tu32 command_id;\n\tu32 length;\n\tu32 attributes;\n};\n\nstruct qsee_req_uefi_set_variable {\n\tu32 command_id;\n\tu32 length;\n\tu32 name_offset;\n\tu32 name_size;\n\tu32 guid_offset;\n\tu32 guid_size;\n\tu32 attributes;\n\tu32 data_offset;\n\tu32 data_size;\n};\n\nstruct qsee_rsp_uefi_get_next_variable {\n\tu32 command_id;\n\tu32 length;\n\tu32 status;\n\tu32 guid_offset;\n\tu32 guid_size;\n\tu32 name_offset;\n\tu32 name_size;\n};\n\nstruct qsee_rsp_uefi_get_variable {\n\tu32 command_id;\n\tu32 length;\n\tu32 status;\n\tu32 attributes;\n\tu32 data_offset;\n\tu32 data_size;\n};\n\nstruct qsee_rsp_uefi_query_variable_info {\n\tu32 command_id;\n\tu32 length;\n\tu32 status;\n\tu32 _pad;\n\tu64 storage_space;\n\tu64 remaining_space;\n\tu64 max_variable_size;\n};\n\nstruct qsee_rsp_uefi_set_variable {\n\tu32 command_id;\n\tu32 length;\n\tu32 status;\n\tu32 _unknown1;\n\tu32 _unknown2;\n};\n\nstruct qseecom_app_desc {\n\tconst char *app_name;\n\tconst char *dev_name;\n};\n\nstruct qseecom_client {\n\tstruct auxiliary_device aux_dev;\n\tu32 app_id;\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct queue_pages {\n\tstruct list_head *pagelist;\n\tlong unsigned int flags;\n\tnodemask_t *nmask;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct vm_area_struct *first;\n\tstruct folio *large;\n\tlong int nr_failed;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quirk_entry {\n\tu16 vid;\n\tu16 pid;\n\tu32 flags;\n};\n\nstruct quirks_list_struct {\n\tstruct hid_device_id hid_bl_item;\n\tstruct list_head node;\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n};\n\nstruct quota_module_name {\n\tint qm_fmt_id;\n\tchar *qm_mod_name;\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct qup_i2c_tag {\n\tu8 *start;\n\tdma_addr_t addr;\n};\n\nstruct qup_i2c_bam {\n\tstruct qup_i2c_tag tag;\n\tstruct dma_chan *dma;\n\tstruct scatterlist *sg;\n\tunsigned int sg_cnt;\n};\n\nstruct qup_i2c_block {\n\tint count;\n\tint pos;\n\tint tx_tag_len;\n\tint rx_tag_len;\n\tint data_len;\n\tint cur_blk_len;\n\tint total_tx_len;\n\tint total_rx_len;\n\tint tx_fifo_data_pos;\n\tint tx_fifo_free;\n\tint rx_fifo_data_pos;\n\tint fifo_available;\n\tu32 tx_fifo_data;\n\tu32 rx_fifo_data;\n\tu8 *cur_data;\n\tu8 *cur_tx_tags;\n\tbool tx_tags_sent;\n\tbool send_last_word;\n\tbool rx_tags_fetched;\n\tbool rx_bytes_read;\n\tbool is_tx_blk_mode;\n\tbool is_rx_blk_mode;\n\tu8 tags[6];\n};\n\nstruct qup_i2c_dev {\n\tstruct device *dev;\n\tvoid *base;\n\tint irq;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct icc_path *icc_path;\n\tstruct i2c_adapter adap;\n\tint clk_ctl;\n\tint out_fifo_sz;\n\tint in_fifo_sz;\n\tint out_blk_sz;\n\tint in_blk_sz;\n\tint blk_xfer_limit;\n\tlong unsigned int one_byte_t;\n\tlong unsigned int xfer_timeout;\n\tstruct qup_i2c_block blk;\n\tstruct i2c_msg *msg;\n\tint pos;\n\tu32 bus_err;\n\tu32 qup_err;\n\tbool is_last;\n\tbool is_smbus_read;\n\tu32 config_run;\n\tu32 src_clk_freq;\n\tu32 cur_bw_clk_freq;\n\tbool is_dma;\n\tbool use_dma;\n\tunsigned int max_xfer_sg_len;\n\tunsigned int tag_buf_pos;\n\tunsigned int blk_mode_threshold;\n\tstruct dma_pool *dpool;\n\tstruct qup_i2c_tag start_tag;\n\tstruct qup_i2c_bam brx;\n\tstruct qup_i2c_bam btx;\n\tstruct completion xfer;\n\tvoid (*write_tx_fifo)(struct qup_i2c_dev *);\n\tvoid (*read_rx_fifo)(struct qup_i2c_dev *);\n\tvoid (*write_rx_tags)(struct qup_i2c_dev *);\n};\n\nstruct r8a779f0_eth_serdes_drv_data;\n\nstruct r8a779f0_eth_serdes_channel {\n\tstruct r8a779f0_eth_serdes_drv_data *dd;\n\tstruct phy *phy;\n\tvoid *addr;\n\tphy_interface_t phy_interface;\n\tint speed;\n\tint index;\n};\n\nstruct r8a779f0_eth_serdes_drv_data {\n\tvoid *addr;\n\tstruct platform_device *pdev;\n\tstruct reset_control *reset;\n\tstruct r8a779f0_eth_serdes_channel channel[3];\n\tbool initialized;\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct rail_alignment {\n\tint offset_uv;\n\tint step_uv;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct rand_data {\n\tvoid *hash_state;\n\t__u64 prev_time;\n\t__u64 last_delta;\n\t__s64 last_delta2;\n\tunsigned int flags;\n\tunsigned int osr;\n\tunsigned char *mem;\n\tunsigned int memlocation;\n\tunsigned int memblocks;\n\tunsigned int memblocksize;\n\tunsigned int memaccessloops;\n\tunsigned int rct_count;\n\tunsigned int apt_cutoff;\n\tunsigned int apt_cutoff_permanent;\n\tunsigned int apt_observations;\n\tunsigned int apt_count;\n\tunsigned int apt_base;\n\tunsigned int health_failure;\n\tunsigned int apt_base_set: 1;\n};\n\nstruct range_node {\n\tstruct rb_node rn_rbnode;\n\tstruct rb_node rb_range_size;\n\tu32 rn_start;\n\tu32 rn_last;\n\tu32 __rn_subtree_last;\n};\n\nstruct range_t {\n\tint start;\n\tint end;\n};\n\nstruct rank_info {\n\tint chan_idx;\n\tstruct csrow_info *csrow;\n\tstruct dimm_info *dimm;\n\tu32 ce_count;\n};\n\nstruct rpi_firmware;\n\nstruct raspberrypi_clk {\n\tstruct device *dev;\n\tstruct rpi_firmware *firmware;\n\tstruct platform_device *cpufreq;\n};\n\nstruct raspberrypi_clk_variant;\n\nstruct raspberrypi_clk_data {\n\tstruct clk_hw hw;\n\tunsigned int id;\n\tstruct raspberrypi_clk_variant *variant;\n\tstruct raspberrypi_clk *rpi;\n};\n\nstruct raspberrypi_clk_variant {\n\tbool export;\n\tchar *clkdev;\n\tlong unsigned int min_rate;\n\tbool minimize;\n\tbool maximize;\n\tu32 flags;\n};\n\nstruct raspberrypi_firmware_prop {\n\t__le32 id;\n\t__le32 val;\n\t__le32 disable_turbo;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n};\n\nstruct ravb_desc {\n\t__le16 ds;\n\tu8 cc;\n\tu8 die_dt;\n\t__le32 dptr;\n};\n\nstruct ravb_ex_rx_desc {\n\t__le16 ds_cc;\n\tu8 msc;\n\tu8 die_dt;\n\t__le32 dptr;\n\t__le32 ts_n;\n\t__le32 ts_sl;\n\t__le16 ts_sh;\n\t__le16 res;\n};\n\nstruct ravb_hw_info {\n\tint (*receive)(struct net_device *, int, int);\n\tvoid (*set_rate)(struct net_device *);\n\tint (*set_feature)(struct net_device *, netdev_features_t);\n\tint (*dmac_init)(struct net_device *);\n\tvoid (*emac_init)(struct net_device *);\n\tconst char (*gstrings_stats)[32];\n\tsize_t gstrings_size;\n\tnetdev_features_t net_hw_features;\n\tnetdev_features_t net_features;\n\tnetdev_features_t vlan_features;\n\tint stats_len;\n\tu32 tccr_mask;\n\tu32 tx_max_frame_size;\n\tu32 rx_max_frame_size;\n\tu32 rx_buffer_size;\n\tu32 rx_desc_size;\n\tu32 dbat_entry_num;\n\tunsigned int aligned_tx: 1;\n\tunsigned int coalesce_irqs: 1;\n\tunsigned int internal_delay: 1;\n\tunsigned int tx_counters: 1;\n\tunsigned int carrier_counters: 1;\n\tunsigned int multi_irqs: 1;\n\tunsigned int irq_en_dis: 1;\n\tunsigned int err_mgmt_irqs: 1;\n\tunsigned int gptp: 1;\n\tunsigned int ccc_gac: 1;\n\tunsigned int gptp_ref_clk: 1;\n\tunsigned int nc_queues: 1;\n\tunsigned int magic_pkt: 1;\n\tunsigned int half_duplex: 1;\n};\n\nstruct ravb_ptp_perout {\n\tu32 target;\n\tu32 period;\n};\n\nstruct ravb_ptp {\n\tstruct ptp_clock *clock;\n\tstruct ptp_clock_info info;\n\tu32 default_addend;\n\tu32 current_addend;\n\tint extts[1];\n\tstruct ravb_ptp_perout perout[1];\n};\n\nstruct ravb_rx_desc;\n\nstruct ravb_tx_desc;\n\nstruct ravb_rx_buffer;\n\nstruct ravb_private {\n\tstruct net_device *ndev;\n\tstruct platform_device *pdev;\n\tvoid *addr;\n\tstruct clk *clk;\n\tstruct clk *refclk;\n\tstruct clk *gptp_clk;\n\tstruct mdiobb_ctrl mdiobb;\n\tu32 num_rx_ring[2];\n\tu32 num_tx_ring[2];\n\tu32 desc_bat_size;\n\tdma_addr_t desc_bat_dma;\n\tstruct ravb_desc *desc_bat;\n\tdma_addr_t rx_desc_dma[2];\n\tdma_addr_t tx_desc_dma[2];\n\tunion {\n\t\tstruct ravb_rx_desc *desc;\n\t\tstruct ravb_ex_rx_desc *ex_desc;\n\t\tvoid *raw;\n\t} rx_ring[2];\n\tstruct ravb_tx_desc *tx_ring[2];\n\tvoid *tx_align[2];\n\tstruct sk_buff *rx_1st_skb;\n\tstruct page_pool *rx_pool[2];\n\tstruct ravb_rx_buffer *rx_buffers[2];\n\tstruct sk_buff **tx_skb[2];\n\tu32 rx_over_errors;\n\tu32 rx_fifo_errors;\n\tstruct net_device_stats stats[2];\n\tenum hwtstamp_tx_types tstamp_tx_ctrl;\n\tenum hwtstamp_rx_filters tstamp_rx_ctrl;\n\tstruct list_head ts_skb_list;\n\tu32 ts_skb_tag;\n\tstruct ravb_ptp ptp;\n\tspinlock_t lock;\n\tu32 cur_rx[2];\n\tu32 dirty_rx[2];\n\tu32 cur_tx[2];\n\tu32 dirty_tx[2];\n\tstruct napi_struct napi[2];\n\tstruct work_struct work;\n\tstruct mii_bus *mii_bus;\n\tint link;\n\tphy_interface_t phy_interface;\n\tint msg_enable;\n\tint speed;\n\tint emac_irq;\n\tunsigned int no_avb_link: 1;\n\tunsigned int avb_link_active_low: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int rxcidm: 1;\n\tunsigned int txcidm: 1;\n\tunsigned int rgmii_override: 1;\n\tunsigned int num_tx_desc;\n\tint duplex;\n\tconst struct ravb_hw_info *info;\n\tstruct reset_control *rstc;\n\tu32 gti_tiv;\n};\n\nstruct ravb_rx_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n};\n\nstruct ravb_rx_desc {\n\t__le16 ds_cc;\n\tu8 msc;\n\tu8 die_dt;\n\t__le32 dptr;\n};\n\nstruct ravb_tstamp_skb {\n\tstruct list_head list;\n\tstruct sk_buff *skb;\n\tu16 tag;\n};\n\nstruct ravb_tx_desc {\n\t__le16 ds_tagl;\n\tu8 tagh_tsr;\n\tu8 die_dt;\n\t__le32 dptr;\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_hwp_page {\n\tstruct llist_node node;\n\tstruct page *page;\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tu64 before;\n\tu64 after;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tatomic_t seq;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rb_time_struct {\n\tlocal64_t time;\n};\n\ntypedef struct rb_time_struct rb_time_t;\n\nstruct rb_wait_data {\n\tstruct rb_irq_work *irq_work;\n\tint seq;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct rcar_dmac_chan;\n\nstruct rcar_dmac {\n\tstruct dma_device engine;\n\tstruct device *dev;\n\tvoid *dmac_base;\n\tvoid *chan_base;\n\tunsigned int n_channels;\n\tstruct rcar_dmac_chan *channels;\n\tu32 channels_mask;\n\tlong unsigned int modules[4];\n};\n\nstruct rcar_dmac_chan_slave {\n\tphys_addr_t slave_addr;\n\tunsigned int xfer_size;\n};\n\nstruct rcar_dmac_chan_map {\n\tdma_addr_t addr;\n\tenum dma_data_direction dir;\n\tstruct rcar_dmac_chan_slave slave;\n};\n\nstruct rcar_dmac_desc;\n\nstruct rcar_dmac_chan {\n\tstruct dma_chan chan;\n\tvoid *iomem;\n\tunsigned int index;\n\tint irq;\n\tstruct rcar_dmac_chan_slave src;\n\tstruct rcar_dmac_chan_slave dst;\n\tstruct rcar_dmac_chan_map map;\n\tint mid_rid;\n\tspinlock_t lock;\n\tstruct {\n\t\tstruct list_head free;\n\t\tstruct list_head pending;\n\t\tstruct list_head active;\n\t\tstruct list_head done;\n\t\tstruct list_head wait;\n\t\tstruct rcar_dmac_desc *running;\n\t\tstruct list_head chunks_free;\n\t\tstruct list_head pages;\n\t} desc;\n};\n\nstruct rcar_dmac_xfer_chunk;\n\nstruct rcar_dmac_hw_desc;\n\nstruct rcar_dmac_desc {\n\tstruct dma_async_tx_descriptor async_tx;\n\tenum dma_transfer_direction direction;\n\tunsigned int xfer_shift;\n\tu32 chcr;\n\tstruct list_head node;\n\tstruct list_head chunks;\n\tstruct rcar_dmac_xfer_chunk *running;\n\tunsigned int nchunks;\n\tstruct {\n\t\tbool use;\n\t\tstruct rcar_dmac_hw_desc *mem;\n\t\tdma_addr_t dma;\n\t\tsize_t size;\n\t} hwdescs;\n\tunsigned int size;\n\tbool cyclic;\n};\n\nstruct rcar_dmac_xfer_chunk {\n\tstruct list_head node;\n\tdma_addr_t src_addr;\n\tdma_addr_t dst_addr;\n\tu32 size;\n};\n\nstruct rcar_dmac_desc_page {\n\tstruct list_head node;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_descs;\n\t\t\tstruct rcar_dmac_desc descs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_chunks;\n\t\t\tstruct rcar_dmac_xfer_chunk chunks[0];\n\t\t};\n\t};\n};\n\nstruct rcar_dmac_hw_desc {\n\tu32 sar;\n\tu32 dar;\n\tu32 tcr;\n\tu32 reserved;\n};\n\nstruct rcar_dmac_of_data {\n\tu32 chan_offset_base;\n\tu32 chan_offset_stride;\n};\n\nstruct rcar_gen3_chan;\n\nstruct rcar_gen3_phy {\n\tstruct phy *phy;\n\tstruct rcar_gen3_chan *ch;\n\tu32 int_enable_bits;\n\tbool initialized;\n\tbool powered;\n};\n\nstruct rcar_gen3_phy_drv_data;\n\nstruct rcar_gen3_chan {\n\tvoid *base;\n\tstruct device *dev;\n\tconst struct rcar_gen3_phy_drv_data *phy_data;\n\tstruct extcon_dev *extcon;\n\tstruct reset_control *rstc;\n\tstruct rcar_gen3_phy rphys[4];\n\tstruct regulator *vbus;\n\tstruct work_struct work;\n\tspinlock_t lock;\n\tenum usb_dr_mode dr_mode;\n\tbool extcon_host;\n\tbool is_otg_channel;\n\tbool uses_otg_pins;\n\tbool otg_internal_reg;\n};\n\nstruct rcar_gen3_cpg_pll_config {\n\tu8 extal_div;\n\tu8 pll1_mult;\n\tu8 pll1_div;\n\tu8 pll3_mult;\n\tu8 pll3_div;\n\tu8 osc_prediv;\n};\n\nstruct rcar_gen3_phy___2 {\n\tstruct phy *phy;\n\tspinlock_t lock;\n\tvoid *base;\n};\n\nstruct rcar_gen3_phy_drv_data {\n\tconst struct phy_ops *phy_usb2_ops;\n\tbool no_adp_ctrl;\n\tbool init_bus;\n\tbool utmi_ctrl;\n\tbool vblvl_ctrl;\n\tu32 obint_enable_bits;\n};\n\nstruct rcar_gen3_thermal_fuse_default {\n\tu32 ptat[3];\n\tu32 thcodes[15];\n};\n\nstruct rcar_gen3_thermal_fuse_info {\n\tu32 ptat[3];\n\tu32 thcode[3];\n\tu32 mask;\n};\n\nstruct thermal_zone_device_ops {\n\tbool (*should_bind)(struct thermal_zone_device *, const struct thermal_trip *, struct thermal_cooling_device *, struct cooling_spec *);\n\tint (*get_temp)(struct thermal_zone_device *, int *);\n\tint (*set_trips)(struct thermal_zone_device *, int, int);\n\tint (*change_mode)(struct thermal_zone_device *, enum thermal_device_mode);\n\tint (*set_trip_temp)(struct thermal_zone_device *, const struct thermal_trip *, int);\n\tint (*get_crit_temp)(struct thermal_zone_device *, int *);\n\tint (*set_emul_temp)(struct thermal_zone_device *, int);\n\tint (*get_trend)(struct thermal_zone_device *, const struct thermal_trip *, enum thermal_trend *);\n\tvoid (*hot)(struct thermal_zone_device *);\n\tvoid (*critical)(struct thermal_zone_device *);\n};\n\nstruct rcar_gen3_thermal_tsc;\n\nstruct rcar_thermal_info;\n\nstruct rcar_gen3_thermal_priv {\n\tstruct rcar_gen3_thermal_tsc *tscs[5];\n\tstruct thermal_zone_device_ops ops;\n\tunsigned int num_tscs;\n\tint ptat[3];\n\tint tj_t;\n\tconst struct rcar_thermal_info *info;\n};\n\nstruct rcar_gen3_thermal_tsc {\n\tstruct rcar_gen3_thermal_priv *priv;\n\tvoid *base;\n\tstruct thermal_zone_device *zone;\n\tstruct {\n\t\tstruct equation_set_coef below;\n\t\tstruct equation_set_coef above;\n\t} coef;\n\tint thcode[3];\n};\n\nstruct rcar_gen4_cpg_pll_config {\n\tu8 extal_div;\n\tu8 pll1_mult;\n\tu8 pll1_div;\n\tu8 pll5_mult;\n\tu8 pll5_div;\n\tu8 osc_prediv;\n};\n\nstruct rcar_gen4_pm_domains {\n\tstruct genpd_onecell_data onecell_data;\n\tstruct generic_pm_domain *domains[65];\n};\n\nstruct rcar_gen4_ptp_private {\n\tvoid *addr;\n\tstruct ptp_clock *clock;\n\tstruct ptp_clock_info info;\n\tspinlock_t lock;\n\ts64 default_addend;\n\tbool initialized;\n};\n\nstruct rcar_gen4_sysc_area {\n\tconst char *name;\n\tu8 pdr;\n\ts8 parent;\n\tu8 flags;\n};\n\nstruct rcar_gen4_sysc_info {\n\tconst struct rcar_gen4_sysc_area *areas;\n\tunsigned int num_areas;\n};\n\nstruct rcar_gen4_sysc_pd {\n\tstruct generic_pm_domain genpd;\n\tu8 pdr;\n\tunsigned int flags;\n\tchar name[0];\n};\n\nstruct rcar_i2c_priv {\n\tu32 flags;\n\tvoid *io;\n\tstruct i2c_adapter adap;\n\tstruct i2c_msg *msg;\n\tint msgs_left;\n\tstruct clk *clk;\n\twait_queue_head_t wait;\n\tint pos;\n\tu32 icccr;\n\tu16 schd;\n\tu16 scld;\n\tu8 smd;\n\tu8 recovery_icmcr;\n\tenum rcar_i2c_type devtype;\n\tstruct i2c_client *slave;\n\tstruct resource *res;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tstruct scatterlist sg;\n\tenum dma_data_direction dma_direction;\n\tstruct reset_control *rstc;\n\tint irq;\n\tstruct i2c_client *host_notify_client;\n\tu8 slave_flags;\n};\n\nstruct rcar_msi {\n\tlong unsigned int used[1];\n\tstruct irq_domain *domain;\n\tstruct mutex map_lock;\n\traw_spinlock_t mask_lock;\n\tint irq1;\n\tint irq2;\n};\n\nstruct rcar_pcie {\n\tstruct device *dev;\n\tvoid *base;\n};\n\nstruct rcar_pcie_endpoint {\n\tstruct rcar_pcie pcie;\n\tphys_addr_t *ob_mapped_addr;\n\tstruct pci_epc_mem_window *ob_window;\n\tu8 max_functions;\n\tunsigned int bar_to_atu[6];\n\tlong unsigned int *ib_window_map;\n\tu32 num_ib_windows;\n\tu32 num_ob_windows;\n};\n\nstruct rcar_pcie_host {\n\tstruct rcar_pcie pcie;\n\tstruct phy *phy;\n\tstruct clk *bus_clk;\n\tstruct rcar_msi msi;\n\tint (*phy_init_fn)(struct rcar_pcie_host *);\n};\n\nstruct rcar_pm_domains {\n\tstruct genpd_onecell_data onecell_data;\n\tstruct generic_pm_domain *domains[33];\n};\n\nstruct rcar_sysc_area {\n\tconst char *name;\n\tu16 chan_offs;\n\tu8 chan_bit;\n\tu8 isr_bit;\n\ts8 parent;\n\tu8 flags;\n};\n\nstruct rcar_sysc_info {\n\tint (*init)(void);\n\tconst struct rcar_sysc_area *areas;\n\tunsigned int num_areas;\n\tu32 extmask_offs;\n\tu32 extmask_val;\n};\n\nstruct rcar_sysc_pd {\n\tstruct generic_pm_domain genpd;\n\tu16 chan_offs;\n\tu8 chan_bit;\n\tu8 isr_bit;\n\tunsigned int flags;\n\tchar name[0];\n};\n\nstruct rcar_thermal_chip {\n\tunsigned int use_of_thermal: 1;\n\tunsigned int has_filonoff: 1;\n\tunsigned int irq_per_ch: 1;\n\tunsigned int needs_suspend_resume: 1;\n\tunsigned int nirqs;\n\tunsigned int ctemp_bands;\n};\n\nstruct rcar_thermal_common {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rcar_thermal_info {\n\tint scale;\n\tint adj_below;\n\tint adj_above;\n\tconst struct rcar_gen3_thermal_fuse_info *fuses;\n\tconst struct rcar_gen3_thermal_fuse_default *fuse_defaults;\n};\n\nstruct rcar_thermal_priv {\n\tvoid *base;\n\tstruct rcar_thermal_common *common;\n\tstruct thermal_zone_device *zone;\n\tconst struct rcar_thermal_chip *chip;\n\tstruct delayed_work work;\n\tstruct mutex lock;\n\tstruct list_head list;\n\tint id;\n};\n\nstruct ring_pair_cb {\n\tstruct rcb_common_cb *rcb_common;\n\tstruct device *dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hnae_queue q;\n\tu16 index;\n\tu16 buf_size;\n\tint virq[2];\n\tu8 port_id_in_comm;\n\tu8 used_by_vf;\n\tstruct hns_ring_hw_stats hw_stats;\n};\n\nstruct rcb_common_cb {\n\tu8 *io_base;\n\tphys_addr_t phy_base;\n\tstruct dsaf_device *dsaf_dev;\n\tu16 max_vfn;\n\tu16 max_q_per_vf;\n\tu8 comm_index;\n\tu32 ring_num;\n\tu32 desc_num;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ring_pair_cb ring_pair_cb[0];\n};\n\nstruct rcec_ea {\n\tu8 nextbusn;\n\tu8 lastbusn;\n\tu32 bitmap;\n};\n\nstruct rcpm {\n\tunsigned int wakeup_cells;\n\tvoid *ippdexpcr_base;\n\tbool little_endian;\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t fqslock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion rcu_special {\n\tstruct {\n\t\tu8 blocked;\n\t\tu8 need_qs;\n\t\tu8 exp_hint;\n\t\tu8 need_mb;\n\t} b;\n\tu32 s;\n};\n\nstruct rcu_stall_chk_rdr {\n\tint nesting;\n\tunion rcu_special rs;\n\tbool on_blkd_list;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[33];\n\tstruct rcu_node *level[3];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rcu_tasks;\n\ntypedef void (*rcu_tasks_gp_func_t)(struct rcu_tasks *);\n\ntypedef void (*pregp_func_t)(struct list_head *);\n\ntypedef void (*pertask_func_t)(struct task_struct *, struct list_head *);\n\ntypedef void (*postscan_func_t)(struct list_head *);\n\ntypedef void (*holdouts_func_t)(struct list_head *, bool, bool *);\n\ntypedef void (*postgp_func_t)(struct rcu_tasks *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\nstruct rcu_tasks_percpu;\n\nstruct rcu_tasks {\n\tstruct rcuwait cbs_wait;\n\traw_spinlock_t cbs_gbl_lock;\n\tstruct mutex tasks_gp_mutex;\n\tint gp_state;\n\tint gp_sleep;\n\tint init_fract;\n\tlong unsigned int gp_jiffies;\n\tlong unsigned int gp_start;\n\tlong unsigned int tasks_gp_seq;\n\tlong unsigned int n_ipis;\n\tlong unsigned int n_ipis_fails;\n\tstruct task_struct *kthread_ptr;\n\tlong unsigned int lazy_jiffies;\n\trcu_tasks_gp_func_t gp_func;\n\tpregp_func_t pregp_func;\n\tpertask_func_t pertask_func;\n\tpostscan_func_t postscan_func;\n\tholdouts_func_t holdouts_func;\n\tpostgp_func_t postgp_func;\n\tcall_rcu_func_t call_func;\n\tunsigned int wait_state;\n\tstruct rcu_tasks_percpu *rtpcpu;\n\tstruct rcu_tasks_percpu **rtpcp_array;\n\tint percpu_enqueue_shift;\n\tint percpu_enqueue_lim;\n\tint percpu_dequeue_lim;\n\tlong unsigned int percpu_dequeue_gpseq;\n\tstruct mutex barrier_q_mutex;\n\tatomic_t barrier_q_count;\n\tstruct completion barrier_q_completion;\n\tlong unsigned int barrier_q_seq;\n\tlong unsigned int barrier_q_start;\n\tchar *name;\n\tchar *kname;\n};\n\nstruct rcu_tasks_percpu {\n\tstruct rcu_segcblist cblist;\n\traw_spinlock_t lock;\n\tlong unsigned int rtp_jiffies;\n\tlong unsigned int rtp_n_lock_retries;\n\tstruct timer_list lazy_timer;\n\tunsigned int urgent_gp;\n\tstruct work_struct rtp_work;\n\tstruct irq_work rtp_irq_work;\n\tstruct callback_head barrier_q_head;\n\tstruct list_head rtp_blkd_tasks;\n\tstruct list_head rtp_exit_list;\n\tint cpu;\n\tint index;\n\tstruct rcu_tasks *rtpp;\n};\n\nstruct rdma_ah_init_attr {\n\tstruct rdma_ah_attr *ah_attr;\n\tu32 flags;\n\tstruct net_device *xmit_slave;\n};\n\nstruct rdma_counter {\n\tstruct rdma_restrack_entry res;\n\tstruct ib_device *device;\n\tuint32_t id;\n\tstruct kref kref;\n\tstruct rdma_counter_mode mode;\n\tstruct mutex lock;\n\tstruct rdma_hw_stats *stats;\n\tu32 port;\n};\n\nstruct rdma_stat_desc;\n\nstruct rdma_hw_stats {\n\tstruct mutex lock;\n\tlong unsigned int timestamp;\n\tlong unsigned int lifespan;\n\tconst struct rdma_stat_desc *descs;\n\tlong unsigned int *is_disabled;\n\tint num_counters;\n\tu64 value[0];\n};\n\nstruct rdma_link_ops {\n\tstruct list_head list;\n\tconst char *type;\n\tint (*newlink)(const char *, struct net_device *);\n};\n\nstruct rdma_netdev_alloc_params {\n\tsize_t sizeof_priv;\n\tunsigned int txqs;\n\tunsigned int rxqs;\n\tvoid *param;\n\tint (*initialize_rdma_netdev)(struct ib_device *, u32, struct net_device *, void *);\n};\n\nstruct rdma_stat_desc {\n\tconst char *name;\n\tunsigned int flags;\n\tconst void *priv;\n};\n\nstruct rdma_user_mmap_entry {\n\tstruct kref ref;\n\tstruct ib_ucontext *ucontext;\n\tlong unsigned int start_pgoff;\n\tsize_t npages;\n\tbool driver_removed;\n\tstruct mutex dmabufs_lock;\n\tstruct list_head dmabufs;\n};\n\nstruct read_buffer {\n\tstruct list_head list;\n\tunsigned int cons;\n\tunsigned int len;\n\tchar msg[0];\n};\n\nstruct tegra_cpu_ctr {\n\tu32 cpu;\n\tu32 coreclk_cnt;\n\tu32 last_coreclk_cnt;\n\tu32 refclk_cnt;\n\tu32 last_refclk_cnt;\n};\n\nstruct read_counters_work {\n\tstruct work_struct work;\n\tstruct tegra_cpu_ctr c;\n};\n\nstruct read_plus_segment {\n\tenum data_content4 type;\n\tuint64_t offset;\n\tunion {\n\t\tstruct {\n\t\t\tuint64_t length;\n\t\t} hole;\n\t\tstruct {\n\t\t\tuint32_t length;\n\t\t\tunsigned int from;\n\t\t} data;\n\t};\n};\n\nstruct read_stats {\n\t__le32 flash;\n\t__le32 buffer;\n\t__le32 erased_cw;\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct realm_config {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int ipa_bits;\n\t\t\tlong unsigned int hash_algo;\n\t\t};\n\t\tu8 pad[512];\n\t};\n\tunion {\n\t\tu8 rpv[64];\n\t\tu8 pad2[3584];\n\t};\n};\n\nstruct reboot_mode_bits {\n\tu32 offset;\n\tu32 mask;\n\tu32 value;\n\tbool valid;\n};\n\nstruct reboot_data {\n\tstruct reboot_mode_bits mode_bits[4];\n\tstruct reboot_mode_bits catchall;\n};\n\nstruct reboot_mode_driver {\n\tstruct device *dev;\n\tstruct list_head head;\n\tint (*write)(struct reboot_mode_driver *, unsigned int);\n\tstruct notifier_block reboot_notifier;\n};\n\nstruct virtnet_rq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t drops;\n\tu64_stats_t xdp_packets;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_redirects;\n\tu64_stats_t xdp_drops;\n\tu64_stats_t kicks;\n};\n\nstruct virtnet_interrupt_coalesce {\n\tu32 max_packets;\n\tu32 max_usecs;\n};\n\nstruct virtnet_rq_dma;\n\nstruct receive_queue {\n\tstruct virtqueue *vq;\n\tstruct napi_struct napi;\n\tstruct bpf_prog *xdp_prog;\n\tstruct virtnet_rq_stats stats;\n\tu16 calls;\n\tbool dim_enabled;\n\tstruct mutex dim_lock;\n\tstruct dim dim;\n\tu32 packets_in_napi;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct page *pages;\n\tstruct ewma_pkt_len mrg_avg_pkt_len;\n\tstruct page_frag alloc_frag;\n\tstruct scatterlist sg[19];\n\tunsigned int min_buf_len;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct virtnet_rq_dma *last_dma;\n\tstruct xsk_buff_pool *xsk_pool;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xsk_rxq_info;\n\tstruct xdp_buff **xsk_buffs;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tlong unsigned int head_block;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\nstruct redist_region {\n\tvoid *redist_base;\n\tphys_addr_t phys_base;\n\tbool single_redist;\n};\n\nstruct referring_call {\n\tuint32_t rc_sequenceid;\n\tuint32_t rc_slotid;\n};\n\nstruct referring_call_list {\n\tstruct nfs4_sessionid rcl_sessionid;\n\tuint32_t rcl_nrefcalls;\n\tstruct referring_call *rcl_refcalls;\n};\n\nstruct reg_bits_to_feat_map {\n\tunion {\n\t\tu64 bits;\n\t\tstruct fgt_masks *masks;\n\t};\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct {\n\t\t\tu8 regidx;\n\t\t\tu8 shift;\n\t\t\tu8 width;\n\t\t\tbool sign;\n\t\t\ts8 lo_lim;\n\t\t};\n\t\tbool (*match)(struct kvm *);\n\t};\n};\n\nstruct reg_cfg {\n\tu32 val;\n\tu32 msk;\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_feat_map_desc {\n\tconst char *name;\n\tconst struct reg_bits_to_feat_map feat_map;\n\tconst struct reg_bits_to_feat_map *bit_feat_map;\n\tconst unsigned int bit_feat_map_sz;\n};\n\nstruct reg_mask_range {\n\t__u64 addr;\n\t__u32 range;\n\t__u32 reserved[13];\n};\n\nstruct reg_offset_data {\n\tu32 base_offset;\n\tunsigned int pipe_mult;\n\tunsigned int evnt_mult;\n\tunsigned int ee_mult;\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nstruct reg_val {\n\tu16 reg;\n\tu32 val;\n};\n\nstruct regcache_flat_data {\n\tlong unsigned int *valid;\n\tunsigned int data[0];\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tint (*populate)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regcache_rbtree_node;\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong unsigned int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\nstruct region_info_user {\n\t__u32 offset;\n\t__u32 erasesize;\n\t__u32 numblocks;\n\t__u32 regionindex;\n};\n\nstruct registered_event_data {\n\tu64 key;\n\tenum pm_api_cb_id cb_type;\n\tbool wake;\n\tstruct list_head cb_list_head;\n\tstruct hlist_node hentry;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\ts8 reg_shift;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct regmap_bus;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_spinlock;\n\t\t\tlong unsigned int raw_spinlock_flags;\n\t\t};\n\t};\n\tstruct lock_class_key *lock_key;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tunsigned int reg_base;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool async;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool max_register_is_set;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tbool defer_caching;\n\tbool force_write_field;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool can_sleep;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regmap_range;\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\nstruct regmap_async_spi {\n\tstruct regmap_async core;\n\tstruct spi_message m;\n\tstruct spi_transfer t[2];\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_noinc_write)(void *, unsigned int, const void *, size_t);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_noinc_read)(void *, unsigned int, void *, size_t);\n\ntypedef void (*regmap_hw_free_context)(void *);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)(void);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tbool free_on_exit;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_noinc_write reg_noinc_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_reg_noinc_read reg_noinc_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint reg_shift;\n\tunsigned int reg_base;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tbool can_sleep;\n\tbool fast_io;\n\tbool io_port;\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tunsigned int max_register;\n\tbool max_register_is_0;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool use_relaxed_mmio;\n\tbool can_multi_write;\n\tbool use_hwlock;\n\tbool use_raw_spinlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tstruct list_head link;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_irq_type {\n\tunsigned int type_reg_offset;\n\tunsigned int type_reg_mask;\n\tunsigned int type_rising_val;\n\tunsigned int type_falling_val;\n\tunsigned int type_level_low_val;\n\tunsigned int type_level_high_val;\n\tunsigned int types_supported;\n};\n\nstruct regmap_irq {\n\tunsigned int reg_offset;\n\tunsigned int mask;\n\tstruct regmap_irq_type type;\n};\n\nstruct regmap_irq_sub_irq_map;\n\nstruct regmap_irq_chip {\n\tconst char *name;\n\tconst char *domain_suffix;\n\tunsigned int main_status;\n\tunsigned int num_main_status_bits;\n\tconst struct regmap_irq_sub_irq_map *sub_reg_offsets;\n\tint num_main_regs;\n\tunsigned int status_base;\n\tunsigned int mask_base;\n\tunsigned int unmask_base;\n\tunsigned int ack_base;\n\tunsigned int wake_base;\n\tconst unsigned int *config_base;\n\tunsigned int irq_reg_stride;\n\tunsigned int init_ack_masked: 1;\n\tunsigned int mask_unmask_non_inverted: 1;\n\tunsigned int use_ack: 1;\n\tunsigned int ack_invert: 1;\n\tunsigned int clear_ack: 1;\n\tunsigned int status_invert: 1;\n\tunsigned int status_is_level: 1;\n\tunsigned int wake_invert: 1;\n\tunsigned int type_in_mask: 1;\n\tunsigned int clear_on_unmask: 1;\n\tunsigned int runtime_pm: 1;\n\tunsigned int no_status: 1;\n\tint num_regs;\n\tconst struct regmap_irq *irqs;\n\tint num_irqs;\n\tint num_config_bases;\n\tint num_config_regs;\n\tint (*handle_pre_irq)(void *);\n\tint (*handle_post_irq)(void *);\n\tint (*handle_mask_sync)(int, unsigned int, unsigned int, void *);\n\tint (*set_type_config)(unsigned int **, unsigned int, const struct regmap_irq *, int, void *);\n\tunsigned int (*get_irq_reg)(struct regmap_irq_chip_data *, unsigned int, int);\n\tvoid *irq_drv_data;\n};\n\nstruct regmap_irq_chip_data {\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tstruct irq_chip irq_chip;\n\tstruct regmap *map;\n\tconst struct regmap_irq_chip *chip;\n\tint irq_base;\n\tstruct irq_domain *domain;\n\tint irq;\n\tint wake_count;\n\tvoid *status_reg_buf;\n\tunsigned int *main_status_buf;\n\tunsigned int *status_buf;\n\tunsigned int *prev_status_buf;\n\tunsigned int *mask_buf;\n\tunsigned int *mask_buf_def;\n\tunsigned int *wake_buf;\n\tunsigned int *type_buf;\n\tunsigned int *type_buf_def;\n\tunsigned int **config_buf;\n\tunsigned int irq_reg_stride;\n\tunsigned int (*get_irq_reg)(struct regmap_irq_chip_data *, unsigned int, int);\n\tunsigned int clear_status: 1;\n};\n\nstruct regmap_irq_sub_irq_map {\n\tunsigned int num_regs;\n\tunsigned int *offset;\n};\n\nstruct regmap_mmio_context {\n\tvoid *regs;\n\tunsigned int val_bytes;\n\tbool big_endian;\n\tbool attached_clk;\n\tstruct clk *clk;\n\tvoid (*reg_write)(struct regmap_mmio_context *, unsigned int, unsigned int);\n\tunsigned int (*reg_read)(struct regmap_mmio_context *, unsigned int);\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regulator_voltage {\n\tint min_uV;\n\tint max_uV;\n};\n\nstruct regulator {\n\tstruct device *dev;\n\tstruct list_head list;\n\tunsigned int always_on: 1;\n\tunsigned int bypass: 1;\n\tunsigned int device_link: 1;\n\tint uA_load;\n\tunsigned int enable_count;\n\tunsigned int deferred_disables;\n\tstruct regulator_voltage voltage[5];\n\tconst char *supply_name;\n\tstruct device_attribute dev_attr;\n\tstruct regulator_dev *rdev;\n\tstruct dentry *debugfs;\n};\n\nstruct regulator_bulk_devres {\n\tstruct regulator_bulk_data *consumers;\n\tint num_consumers;\n};\n\nstruct regulator_config {\n\tstruct device *dev;\n\tconst struct regulator_init_data *init_data;\n\tvoid *driver_data;\n\tstruct device_node *of_node;\n\tstruct regmap *regmap;\n\tstruct gpio_desc *ena_gpiod;\n};\n\nstruct regulator_consumer_supply {\n\tconst char *dev_name;\n\tconst char *supply;\n};\n\nstruct regulator_enable_gpio;\n\nstruct regulator_dev {\n\tconst struct regulator_desc *desc;\n\tint exclusive;\n\tu32 use_count;\n\tu32 open_count;\n\tu32 bypass_count;\n\tstruct list_head list;\n\tstruct list_head consumer_list;\n\tstruct coupling_desc coupling_desc;\n\tstruct blocking_notifier_head notifier;\n\tstruct ww_mutex mutex;\n\tstruct task_struct *mutex_owner;\n\tint ref_cnt;\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct device bdev;\n\tstruct regulation_constraints *constraints;\n\tstruct regulator *supply;\n\tconst char *supply_name;\n\tstruct regmap *regmap;\n\tstruct delayed_work disable_work;\n\tvoid *reg_data;\n\tstruct dentry *debugfs;\n\tstruct regulator_enable_gpio *ena_pin;\n\tunsigned int ena_gpio_state: 1;\n\tunsigned int constraints_pending: 1;\n\tunsigned int is_switch: 1;\n\tktime_t last_off;\n\tint cached_err;\n\tbool use_cached_err;\n\tspinlock_t err_lock;\n\tint pw_requested_mW;\n\tstruct notifier_block supply_fwd_nb;\n};\n\nstruct regulator_enable_gpio {\n\tstruct list_head list;\n\tstruct gpio_desc *gpiod;\n\tu32 enable_count;\n\tu32 request_count;\n};\n\nstruct regulator_err_state {\n\tstruct regulator_dev *rdev;\n\tlong unsigned int notifs;\n\tlong unsigned int errors;\n\tint possible_errs;\n};\n\nstruct regulator_event_work {\n\tstruct work_struct work;\n\tstruct regulator_dev *rdev;\n\tlong unsigned int event;\n};\n\nstruct regulator_irq_data {\n\tstruct regulator_err_state *states;\n\tint num_states;\n\tvoid *data;\n\tlong int opaque;\n};\n\nstruct regulator_irq_desc {\n\tconst char *name;\n\tint fatal_cnt;\n\tint reread_ms;\n\tint irq_off_ms;\n\tbool skip_off;\n\tbool high_prio;\n\tvoid *data;\n\tint (*die)(struct regulator_irq_data *);\n\tint (*map_event)(int, struct regulator_irq_data *, long unsigned int *);\n\tint (*renable)(struct regulator_irq_data *);\n};\n\nstruct regulator_irq {\n\tstruct regulator_irq_data rdata;\n\tstruct regulator_irq_desc desc;\n\tint irq;\n\tint retry_cnt;\n\tstruct delayed_work isr_work;\n};\n\nstruct regulator_map {\n\tstruct list_head list;\n\tconst char *dev_name;\n\tconst char *supply;\n\tstruct regulator_dev *regulator;\n};\n\nstruct regulator_notifier_match {\n\tstruct regulator *regulator;\n\tstruct notifier_block *nb;\n};\n\nstruct regulator_supply_alias {\n\tstruct list_head list;\n\tstruct device *src_dev;\n\tconst char *src_supply;\n\tstruct device *alias_dev;\n\tconst char *alias_supply;\n};\n\nstruct regulator_supply_alias_match {\n\tstruct device *dev;\n\tconst char *id;\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\nstruct xen_remap_gfn_info;\n\nstruct remap_data {\n\txen_pfn_t *fgfn;\n\tint nr_fgfn;\n\tpgprot_t prot;\n\tdomid_t domid;\n\tstruct vm_area_struct *vma;\n\tint index;\n\tstruct page **pages;\n\tstruct xen_remap_gfn_info *info;\n\tint *err_ptr;\n\tint mapped;\n\tint h_errs[1];\n\txen_ulong_t h_idxs[1];\n\txen_pfn_t h_gpfns[1];\n\tint h_iter;\n};\n\nstruct remap_pfn {\n\tstruct mm_struct *mm;\n\tstruct page **pages;\n\tpgprot_t prot;\n\tlong unsigned int i;\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct renesas_family {\n\tconst char name[16];\n\tu32 reg;\n};\n\nstruct renesas_id {\n\tunsigned int offset;\n\tu32 mask;\n};\n\nstruct tmio_mmc_data {\n\tvoid *chan_priv_tx;\n\tvoid *chan_priv_rx;\n\tunsigned int hclk;\n\tlong unsigned int capabilities;\n\tlong unsigned int capabilities2;\n\tlong unsigned int flags;\n\tu32 ocr_mask;\n\tdma_addr_t dma_rx_offset;\n\tunsigned int max_blk_count;\n\tshort unsigned int max_segs;\n};\n\nstruct tmio_mmc_host;\n\nstruct renesas_sdhi_dma {\n\tlong unsigned int end_flags;\n\tenum dma_slave_buswidth dma_buswidth;\n\tdma_filter_fn filter;\n\tvoid (*enable)(struct tmio_mmc_host *, bool);\n\tstruct completion dma_dataend;\n\tstruct work_struct dma_complete;\n};\n\nstruct renesas_sdhi_quirks;\n\nstruct renesas_sdhi {\n\tstruct clk *clk;\n\tstruct clk *clkh;\n\tstruct clk *clk_cd;\n\tstruct tmio_mmc_data mmc_data;\n\tstruct renesas_sdhi_dma dma_priv;\n\tconst struct renesas_sdhi_quirks *quirks;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_uhs;\n\tvoid *scc_ctl;\n\tu32 scc_tappos;\n\tu32 scc_tappos_hs400;\n\tconst u8 *adjust_hs400_calib_table;\n\tbool needs_adjust_hs400;\n\tbool card_is_sdio;\n\tlong unsigned int taps[1];\n\tlong unsigned int smpcmp[1];\n\tunsigned int tap_num;\n\tunsigned int tap_set;\n\tstruct reset_control *rstc;\n\tstruct tmio_mmc_host *host;\n\tstruct regulator_dev *rdev;\n};\n\nstruct renesas_sdhi_scc;\n\nstruct renesas_sdhi_of_data {\n\tlong unsigned int tmio_flags;\n\tu32 tmio_ocr_mask;\n\tlong unsigned int capabilities;\n\tlong unsigned int capabilities2;\n\tenum dma_slave_buswidth dma_buswidth;\n\tdma_addr_t dma_rx_offset;\n\tunsigned int bus_shift;\n\tint scc_offset;\n\tstruct renesas_sdhi_scc *taps;\n\tint taps_num;\n\tunsigned int max_blk_count;\n\tshort unsigned int max_segs;\n\tlong unsigned int sdhi_flags;\n};\n\nstruct renesas_sdhi_of_data_with_quirks {\n\tconst struct renesas_sdhi_of_data *of_data;\n\tconst struct renesas_sdhi_quirks *quirks;\n};\n\nstruct renesas_sdhi_quirks {\n\tbool hs400_disabled;\n\tbool hs400_4taps;\n\tbool fixed_addr_mode;\n\tbool dma_one_rx_only;\n\tbool manual_tap_correction;\n\tbool old_info1_layout;\n\tu32 hs400_bad_taps;\n\tconst u8 (*hs400_calib_table)[32];\n};\n\nstruct renesas_sdhi_scc {\n\tlong unsigned int clk_rate;\n\tu32 tap;\n\tu32 tap_hs400_4tap;\n};\n\nstruct renesas_soc {\n\tconst struct renesas_family *family;\n\tu32 id;\n};\n\nstruct report_general_resp {\n\t__be16 change_count;\n\t__be16 route_indexes;\n\tu8 _r_a;\n\tu8 num_phys;\n\tu8 conf_route_table: 1;\n\tu8 configuring: 1;\n\tu8 config_others: 1;\n\tu8 orej_retry_supp: 1;\n\tu8 stp_cont_awt: 1;\n\tu8 self_config: 1;\n\tu8 zone_config: 1;\n\tu8 t2t_supp: 1;\n\tu8 _r_c;\n\tu8 enclosure_logical_id[8];\n\tu8 _r_d[12];\n};\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tstruct bio_crypt_ctx *crypt_ctx;\n\tstruct blk_crypto_keyslot *crypt_keyslot;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_desc_header {\n\tu8 cci;\n\tu8 ehs_length;\n\tu8 reserved2: 7;\n\tu8 enable_crypto: 1;\n\tu8 interrupt: 1;\n\tu8 data_direction: 2;\n\tu8 reserved1: 1;\n\tu8 command_type: 4;\n\t__le32 dunl;\n\tu8 ocs;\n\tu8 cds;\n\t__le16 ldbc;\n\t__le32 dunu;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct rq_qos;\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tstruct device *dev;\n\tenum rpm_status rpm_status;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct blk_crypto_profile *crypto_profile;\n\tstruct kobject *crypto_kobject;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tlong unsigned int blkcg_pols[1];\n\tstruct blkcg_gq *root_blkg;\n\tstruct list_head blkg_list;\n\tstruct mutex blkcg_mutex;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct res_proc_context {\n\tstruct list_head *list;\n\tint (*preproc)(struct acpi_resource *, void *);\n\tvoid *preproc_data;\n\tint count;\n\tint error;\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\nstruct reserved_mem_ops;\n\nstruct reserved_mem {\n\tconst char *name;\n\tlong unsigned int fdt_node;\n\tconst struct reserved_mem_ops *ops;\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tvoid *priv;\n};\n\nstruct reserved_mem_ops {\n\tint (*device_init)(struct reserved_mem *, struct device *);\n\tvoid (*device_release)(struct reserved_mem *, struct device *);\n};\n\nstruct reset_control {\n\tstruct reset_controller_dev *rcdev;\n\tstruct list_head list;\n\tunsigned int id;\n\tstruct kref refcnt;\n\tbool acquired;\n\tbool shared;\n\tbool array;\n\tatomic_t deassert_count;\n\tatomic_t triggered_count;\n};\n\nstruct reset_control_array {\n\tstruct reset_control base;\n\tunsigned int num_rstcs;\n\tstruct reset_control *rstc[0];\n};\n\nstruct reset_control_bulk_devres {\n\tint num_rstcs;\n\tstruct reset_control_bulk_data *rstcs;\n};\n\nstruct reset_dom_info {\n\tbool async_reset;\n\tbool reset_notify;\n\tu32 latency_us;\n\tchar name[64];\n};\n\nstruct reset_gpio_lookup {\n\tstruct of_phandle_args of_args;\n\tstruct fwnode_handle *swnode;\n\tstruct list_head list;\n};\n\nstruct reset_reg_mask {\n\tu32 rst_src_en_mask;\n\tu32 sw_mstr_rst_mask;\n};\n\nstruct reset_simple_devdata {\n\tu32 reg_offset;\n\tu32 nr_resets;\n\tbool active_low;\n\tbool status_active_low;\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct resource_name_formats {\n\tconst char *rsc_name_fmt;\n\tconst char *rsc_name_fmt1;\n};\n\nstruct resource_table {\n\tu32 ver;\n\tu32 num;\n\tu32 reserved[2];\n\tu32 offset[0];\n};\n\nstruct resource_win {\n\tstruct resource res;\n\tresource_size_t offset;\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct resume_swap_area {\n\t__kernel_loff_t offset;\n\t__u32 dev;\n} __attribute__((packed));\n\nstruct resv_map {\n\tstruct kref refs;\n\tspinlock_t lock;\n\tstruct list_head regions;\n\tlong int adds_in_progress;\n\tstruct list_head region_cache;\n\tlong int region_cache_count;\n\tstruct rw_semaphore rw_sema;\n\tstruct page_counter *reservation_counter;\n\tlong unsigned int pages_per_hpage;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct return_address_data {\n\tunsigned int level;\n\tvoid *addr;\n};\n\nstruct return_consumer {\n\t__u64 cookie;\n\t__u64 id;\n};\n\nstruct return_instance {\n\tstruct hprobe hprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tint cons_cnt;\n\tstruct return_instance *next;\n\tstruct callback_head rcu;\n\tstruct return_consumer consumer;\n\tstruct return_consumer *extra_consumers;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct stm32_rifsc_resources_names;\n\nstruct rifsc_dbg_private {\n\tconst struct stm32_rifsc_resources_names *res_names;\n\tvoid *mmio;\n\tunsigned int nb_risup;\n\tunsigned int nb_rimu;\n\tunsigned int nb_risal;\n};\n\nstruct rifsc_rimu_debug_data {\n\tchar m_name[11];\n\tu8 m_cid;\n\tbool cidsel;\n\tbool m_sec;\n\tbool m_priv;\n};\n\nstruct rifsc_risup_debug_data {\n\tchar dev_name[15];\n\tu8 dev_cid;\n\tu8 dev_sem_cids;\n\tu8 dev_id;\n\tbool dev_cid_filt_en;\n\tbool dev_sem_en;\n\tbool dev_priv;\n\tbool dev_sec;\n};\n\nstruct rifsc_subreg_debug_data {\n\tbool sr_sec;\n\tbool sr_priv;\n\tu8 sr_cid;\n\tbool sr_rlock;\n\tbool sr_enable;\n\tu16 sr_start;\n\tu16 sr_length;\n};\n\nstruct riic_of_data;\n\nstruct riic_dev {\n\tvoid *base;\n\tu8 *buf;\n\tstruct i2c_msg *msg;\n\tint bytes_left;\n\tint err;\n\tint is_last;\n\tconst struct riic_of_data *info;\n\tstruct completion msg_done;\n\tstruct i2c_adapter adapter;\n\tstruct clk *clk;\n\tstruct reset_control *rstc;\n\tstruct i2c_timings i2c_t;\n};\n\nstruct riic_irq_desc {\n\tint res_num;\n\tirq_handler_t isr;\n\tchar *name;\n};\n\nstruct riic_of_data {\n\tconst u8 *regs;\n\tconst struct riic_irq_desc *irqs;\n\tu8 num_irqs;\n\tbool fast_mode_plus;\n};\n\nstruct ring_buffer_cpu_meta {\n\tlong unsigned int first_buffer;\n\tlong unsigned int head_buffer;\n\tlong unsigned int commit_buffer;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tint buffers[0];\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tlong unsigned int cache_pages_removed;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tsize_t event_size;\n\tint missed_events;\n};\n\nstruct ring_buffer_meta {\n\tint magic;\n\tint struct_sizes;\n\tlong unsigned int total_size;\n\tlong unsigned int buffers_offset;\n};\n\nstruct trace_buffer_meta;\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tlong unsigned int cnt;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_lost;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\trb_time_t write_stamp;\n\trb_time_t before_stamp;\n\tu64 event_stamp[5];\n\tu64 read_stamp;\n\tlong unsigned int pages_removed;\n\tunsigned int mapped;\n\tunsigned int user_mapped;\n\tstruct mutex mapping_lock;\n\tlong unsigned int *subbuf_ids;\n\tstruct trace_buffer_meta *meta_page;\n\tstruct ring_buffer_cpu_meta *ring_meta;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct ringacc_match_data {\n\tstruct k3_ringacc_ops ops;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rk35xx_priv {\n\tstruct reset_control *reset;\n\tenum dwcmshc_rk_type devtype;\n\tu8 txclk_tapnum;\n};\n\nstruct rk3x_i2c_soc_data;\n\nstruct rk3x_i2c {\n\tstruct i2c_adapter adap;\n\tstruct device *dev;\n\tconst struct rk3x_i2c_soc_data *soc_data;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tstruct notifier_block clk_rate_nb;\n\tint irq;\n\tstruct i2c_timings t;\n\tspinlock_t lock;\n\twait_queue_head_t wait;\n\tbool busy;\n\tstruct i2c_msg *msg;\n\tu8 addr;\n\tunsigned int mode;\n\tbool is_last_msg;\n\tenum rk3x_i2c_state state;\n\tunsigned int processed;\n\tint error;\n};\n\nstruct rk3x_i2c_calced_timings {\n\tlong unsigned int div_low;\n\tlong unsigned int div_high;\n\tunsigned int tuning;\n};\n\nstruct rk3x_i2c_soc_data {\n\tint grf_offset;\n\tint (*calc_timings)(long unsigned int, struct i2c_timings *, struct rk3x_i2c_calced_timings *);\n};\n\nstruct rk808 {\n\tstruct device *dev;\n\tstruct regmap_irq_chip_data *irq_data;\n\tstruct regmap *regmap;\n\tlong int variant;\n\tconst struct regmap_config *regmap_cfg;\n\tconst struct regmap_irq_chip *regmap_irq_chip;\n};\n\nstruct rk808_clkout {\n\tstruct regmap *regmap;\n\tstruct clk_hw clkout1_hw;\n\tstruct clk_hw clkout2_hw;\n};\n\nstruct rk808_reg_data {\n\tint addr;\n\tint mask;\n\tint value;\n};\n\nstruct rk808_regulator_data {\n\tstruct gpio_desc *dvs_gpio[2];\n};\n\nstruct rk8xx_i2c_platform_data {\n\tconst struct regmap_config *regmap_cfg;\n\tint variant;\n};\n\nstruct rk8xx_register_bit {\n\tu8 reg;\n\tu8 bit;\n};\n\nstruct rk_timer {\n\tvoid *base;\n\tvoid *ctrl;\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tu32 freq;\n\tint irq;\n};\n\nstruct rk_clkevt {\n\tstruct clock_event_device ce;\n\tstruct rk_timer timer;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rk_iommu {\n\tstruct device *dev;\n\tvoid **bases;\n\tint num_mmu;\n\tint num_irq;\n\tstruct clk_bulk_data *clocks;\n\tint num_clocks;\n\tbool reset_disabled;\n\tstruct iommu_device iommu;\n\tstruct list_head node;\n\tstruct iommu_domain *domain;\n};\n\nstruct rk_iommu_domain {\n\tstruct list_head iommus;\n\tu32 *dt;\n\tdma_addr_t dt_dma;\n\tspinlock_t iommus_lock;\n\tspinlock_t dt_lock;\n\tstruct device *dma_dev;\n\tstruct iommu_domain domain;\n};\n\nstruct rk_iommu_ops {\n\tphys_addr_t (*pt_address)(u32);\n\tu32 (*mk_dtentries)(dma_addr_t);\n\tu32 (*mk_ptentries)(phys_addr_t, int);\n\tu64 dma_bit_mask;\n\tgfp_t gfp_flags;\n};\n\nstruct rk_iommudata {\n\tstruct device_link *link;\n\tstruct rk_iommu *iommu;\n};\n\nstruct rk_rng_soc_data;\n\nstruct rk_rng {\n\tstruct hwrng rng;\n\tvoid *base;\n\tint clk_num;\n\tstruct clk_bulk_data *clk_bulks;\n\tconst struct rk_rng_soc_data *soc_data;\n\tstruct device *dev;\n};\n\nstruct rk_rng_soc_data {\n\tint (*rk_rng_init)(struct hwrng *);\n\tint (*rk_rng_read)(struct hwrng *, void *, size_t, bool);\n\tvoid (*rk_rng_cleanup)(struct hwrng *);\n\tshort unsigned int quality;\n\tbool reset_optional;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rmem_assigned_device {\n\tstruct device *dev;\n\tstruct reserved_mem *rmem;\n\tstruct list_head list;\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_gpio_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_gpio_data gpio_data;\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tstruct crypto_alg base;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct rockchip_aux_grf {\n\tstruct regmap *grf;\n\tenum rockchip_grf_type type;\n\tstruct hlist_node node;\n};\n\nstruct usb2phy_reg {\n\tunsigned int offset;\n\tunsigned int bitend;\n\tunsigned int bitstart;\n\tunsigned int disable;\n\tunsigned int enable;\n};\n\nstruct rockchip_chg_det_reg {\n\tstruct usb2phy_reg cp_det;\n\tstruct usb2phy_reg dcp_det;\n\tstruct usb2phy_reg dp_det;\n\tstruct usb2phy_reg idm_sink_en;\n\tstruct usb2phy_reg idp_sink_en;\n\tstruct usb2phy_reg idp_src_en;\n\tstruct usb2phy_reg rdm_pdwn_en;\n\tstruct usb2phy_reg vdm_src_en;\n\tstruct usb2phy_reg vdp_src_en;\n\tstruct usb2phy_reg opmode;\n};\n\nstruct rockchip_clk_branch {\n\tunsigned int id;\n\tenum rockchip_clk_branch_type branch_type;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tint muxdiv_offset;\n\tu8 mux_shift;\n\tu8 mux_width;\n\tu8 mux_flags;\n\tu32 *mux_table;\n\tint div_offset;\n\tu8 div_shift;\n\tu8 div_width;\n\tu8 div_flags;\n\tstruct clk_div_table *div_table;\n\tint gate_offset;\n\tu8 gate_shift;\n\tu8 gate_flags;\n\tunsigned int linked_clk_id;\n\tenum rockchip_grf_type grf_type;\n\tstruct rockchip_clk_branch *child;\n};\n\nstruct rockchip_clk_frac {\n\tstruct notifier_block clk_nb;\n\tstruct clk_fractional_divider div;\n\tstruct clk_gate gate;\n\tstruct clk_mux mux;\n\tconst struct clk_ops *mux_ops;\n\tint mux_frac_idx;\n\tbool rate_change_remuxed;\n\tint rate_change_idx;\n};\n\nstruct rockchip_pll_rate_table;\n\nstruct rockchip_clk_provider;\n\nstruct rockchip_clk_pll {\n\tstruct clk_hw hw;\n\tstruct clk_mux pll_mux;\n\tconst struct clk_ops *pll_mux_ops;\n\tstruct notifier_block clk_nb;\n\tvoid *reg_base;\n\tint lock_offset;\n\tunsigned int lock_shift;\n\tenum rockchip_pll_type type;\n\tu8 flags;\n\tconst struct rockchip_pll_rate_table *rate_table;\n\tunsigned int rate_count;\n\tspinlock_t *lock;\n\tstruct rockchip_clk_provider *ctx;\n};\n\nstruct rockchip_clk_provider {\n\tvoid *reg_base;\n\tstruct clk_onecell_data clk_data;\n\tstruct device_node *cru_node;\n\tstruct regmap *grf;\n\tstruct hlist_head aux_grf_table[4];\n\tspinlock_t lock;\n};\n\nstruct rockchip_cpuclk_rate_table;\n\nstruct rockchip_cpuclk_reg_data;\n\nstruct rockchip_cpuclk {\n\tstruct clk_hw hw;\n\tstruct clk *alt_parent;\n\tvoid *reg_base;\n\tstruct notifier_block clk_nb;\n\tunsigned int rate_count;\n\tstruct rockchip_cpuclk_rate_table *rate_table;\n\tconst struct rockchip_cpuclk_reg_data *reg_data;\n\tspinlock_t *lock;\n};\n\nstruct rockchip_cpuclk_clksel {\n\tint reg;\n\tu32 val;\n};\n\nstruct rockchip_cpuclk_rate_table {\n\tlong unsigned int prate;\n\tstruct rockchip_cpuclk_clksel divs[6];\n\tstruct rockchip_cpuclk_clksel pre_muxs[6];\n\tstruct rockchip_cpuclk_clksel post_muxs[6];\n};\n\nstruct rockchip_cpuclk_reg_data {\n\tint core_reg[4];\n\tu8 div_core_shift[4];\n\tu32 div_core_mask[4];\n\tint num_cores;\n\tint mux_core_reg;\n\tu8 mux_core_alt;\n\tu8 mux_core_main;\n\tu8 mux_core_shift;\n\tu32 mux_core_mask;\n};\n\nstruct rockchip_data {\n\tint size;\n\tint read_offset;\n\tconst char * const *clks;\n\tint num_clks;\n\tnvmem_reg_read_t reg_read;\n};\n\nstruct rockchip_ddrclk {\n\tstruct clk_hw hw;\n\tvoid *reg_base;\n\tint mux_offset;\n\tint mux_shift;\n\tint mux_width;\n\tint div_shift;\n\tint div_width;\n\tint ddr_flag;\n\tspinlock_t *lock;\n};\n\nstruct rockchip_domain_info {\n\tconst char *name;\n\tint pwr_mask;\n\tint status_mask;\n\tint req_mask;\n\tint idle_mask;\n\tint ack_mask;\n\tbool active_wakeup;\n\tbool need_regulator;\n\tint pwr_w_mask;\n\tint req_w_mask;\n\tint clk_ungate_mask;\n\tint mem_status_mask;\n\tint repair_status_mask;\n\tu32 pwr_offset;\n\tu32 mem_offset;\n\tu32 req_offset;\n};\n\nstruct rockchip_drv {\n\tenum rockchip_pin_drv_type drv_type;\n\tint offset;\n};\n\nstruct rockchip_efuse_chip {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n};\n\nstruct rockchip_emmc_phy {\n\tunsigned int reg_offset;\n\tstruct regmap *reg_base;\n\tstruct clk *emmcclk;\n\tunsigned int drive_impedance;\n\tunsigned int enable_strobe_pulldown;\n\tunsigned int output_tapdelay_select;\n};\n\nstruct rockchip_gate_grf {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int reg;\n\tunsigned int shift;\n\tu8 flags;\n};\n\nstruct rockchip_gate_link_platdata {\n\tstruct rockchip_clk_provider *ctx;\n\tstruct rockchip_clk_branch *clkbr;\n};\n\nstruct rockchip_gpio_regs {\n\tu32 port_dr;\n\tu32 port_ddr;\n\tu32 int_en;\n\tu32 int_mask;\n\tu32 int_type;\n\tu32 int_polarity;\n\tu32 int_bothedge;\n\tu32 int_status;\n\tu32 int_rawstatus;\n\tu32 debounce;\n\tu32 dbclk_div_en;\n\tu32 dbclk_div_con;\n\tu32 port_eoi;\n\tu32 ext_port;\n\tu32 version_id;\n};\n\nstruct rockchip_grf_value;\n\nstruct rockchip_grf_info {\n\tconst struct rockchip_grf_value *values;\n\tint num_values;\n};\n\nstruct rockchip_grf_value {\n\tconst char *desc;\n\tu32 reg;\n\tu32 val;\n};\n\nstruct rockchip_inv_clock {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tint shift;\n\tint flags;\n\tspinlock_t *lock;\n};\n\nstruct rockchip_iodomain;\n\nstruct rockchip_iodomain_supply {\n\tstruct rockchip_iodomain *iod;\n\tstruct regulator *reg;\n\tstruct notifier_block nb;\n\tint idx;\n};\n\nstruct rockchip_iodomain_soc_data;\n\nstruct rockchip_iodomain {\n\tstruct device *dev;\n\tstruct regmap *grf;\n\tconst struct rockchip_iodomain_soc_data *soc_data;\n\tstruct rockchip_iodomain_supply supplies[16];\n\tint (*write)(struct rockchip_iodomain_supply *, int);\n};\n\nstruct rockchip_iodomain_soc_data {\n\tint grf_offset;\n\tconst char *supply_names[16];\n\tvoid (*init)(struct rockchip_iodomain *);\n\tint (*write)(struct rockchip_iodomain_supply *, int);\n};\n\nstruct rockchip_iomux {\n\tint type;\n\tint offset;\n};\n\nstruct rockchip_mmc_clock {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tstruct regmap *grf;\n\tint grf_reg;\n\tint shift;\n\tint cached_phase;\n\tstruct notifier_block clk_rate_change_nb;\n};\n\nstruct rockchip_mux_recalced_data {\n\tu8 num;\n\tu8 pin;\n\tu32 reg;\n\tu8 bit;\n\tu8 mask;\n};\n\nstruct rockchip_mux_route_data {\n\tu8 bank_num;\n\tu8 pin;\n\tu8 func;\n\tenum rockchip_mux_route_location route_location;\n\tu32 route_offset;\n\tu32 route_val;\n};\n\nstruct rockchip_muxgrf_clock {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 reg;\n\tu32 shift;\n\tu32 width;\n\tint flags;\n};\n\nstruct rockchip_otp {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk_bulk_data *clks;\n\tstruct reset_control *rst;\n\tconst struct rockchip_data *data;\n};\n\nstruct rockchip_p3phy_priv;\n\nstruct rockchip_p3phy_ops {\n\tint (*phy_init)(struct rockchip_p3phy_priv *);\n};\n\nstruct rockchip_p3phy_priv {\n\tconst struct rockchip_p3phy_ops *ops;\n\tvoid *mmio;\n\tint mode;\n\tint pcie30_phymode;\n\tstruct regmap *phy_grf;\n\tstruct regmap *pipe_grf;\n\tstruct reset_control *p30phy;\n\tstruct phy *phy;\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tint num_lanes;\n\tu32 lanes[4];\n\tu32 rx_cmn_refclk_mode[4];\n};\n\nstruct rockchip_pcie_of_data;\n\nstruct rockchip_pcie {\n\tstruct dw_pcie pci;\n\tvoid *apb_base;\n\tstruct phy *phy;\n\tstruct clk_bulk_data *clks;\n\tunsigned int clk_cnt;\n\tstruct reset_control *rst;\n\tstruct gpio_desc *rst_gpio;\n\tstruct irq_domain *irq_domain;\n\tconst struct rockchip_pcie_of_data *data;\n\tbool supports_clkreq;\n};\n\nstruct rockchip_pcie___2 {\n\tvoid *reg_base;\n\tvoid *apb_base;\n\tbool legacy_phy;\n\tstruct phy *phys[4];\n\tstruct reset_control_bulk_data pm_rsts[3];\n\tstruct reset_control_bulk_data core_rsts[4];\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n\tstruct regulator *vpcie12v;\n\tstruct regulator *vpcie3v3;\n\tstruct regulator *vpcie1v8;\n\tstruct regulator *vpcie0v9;\n\tstruct gpio_desc *perst_gpio;\n\tu32 lanes;\n\tu8 lanes_map;\n\tint link_gen;\n\tstruct device *dev;\n\tstruct irq_domain *irq_domain;\n\tint offset;\n\tvoid *msg_region;\n\tphys_addr_t msg_bus_addr;\n\tbool is_rc;\n\tstruct resource *mem_res;\n};\n\nstruct rockchip_pcie_of_data {\n\tenum dw_pcie_device_mode mode;\n\tconst struct pci_epc_features *epc_features;\n};\n\nstruct rockchip_pinctrl;\n\nstruct rockchip_pin_bank {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tstruct regmap *regmap_pull;\n\tstruct clk *clk;\n\tstruct clk *db_clk;\n\tint irq;\n\tu32 saved_masks;\n\tu32 pin_base;\n\tu8 nr_pins;\n\tchar *name;\n\tu8 bank_num;\n\tstruct rockchip_iomux iomux[4];\n\tstruct rockchip_drv drv[4];\n\tenum rockchip_pin_pull_type pull_type[4];\n\tbool valid;\n\tstruct device_node *of_node;\n\tstruct rockchip_pinctrl *drvdata;\n\tstruct irq_domain *domain;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range grange;\n\traw_spinlock_t slock;\n\tconst struct rockchip_gpio_regs *gpio_regs;\n\tu32 gpio_type;\n\tu32 toggle_edge_mode;\n\tu32 recalced_mask;\n\tu32 route_mask;\n\tstruct list_head deferred_pins;\n\tstruct mutex deferred_lock;\n};\n\nstruct rockchip_pin_config {\n\tunsigned int func;\n\tlong unsigned int *configs;\n\tunsigned int nconfigs;\n};\n\nstruct rockchip_pin_ctrl {\n\tstruct rockchip_pin_bank *pin_banks;\n\tu32 nr_banks;\n\tu32 nr_pins;\n\tchar *label;\n\tenum rockchip_pinctrl_type type;\n\tint grf_mux_offset;\n\tint pmu_mux_offset;\n\tint grf_drv_offset;\n\tint pmu_drv_offset;\n\tstruct rockchip_mux_recalced_data *iomux_recalced;\n\tu32 niomux_recalced;\n\tstruct rockchip_mux_route_data *iomux_routes;\n\tu32 niomux_routes;\n\tint (*pull_calc_reg)(struct rockchip_pin_bank *, int, struct regmap **, int *, u8 *);\n\tint (*drv_calc_reg)(struct rockchip_pin_bank *, int, struct regmap **, int *, u8 *);\n\tint (*schmitt_calc_reg)(struct rockchip_pin_bank *, int, struct regmap **, int *, u8 *);\n};\n\nstruct rockchip_pin_deferred {\n\tstruct list_head head;\n\tunsigned int pin;\n\tenum pin_config_param param;\n\tu32 arg;\n};\n\nstruct rockchip_pin_group {\n\tconst char *name;\n\tunsigned int npins;\n\tunsigned int *pins;\n\tstruct rockchip_pin_config *data;\n};\n\nstruct rockchip_pmx_func;\n\nstruct rockchip_pinctrl {\n\tstruct regmap *regmap_base;\n\tint reg_size;\n\tstruct regmap *regmap_pull;\n\tstruct regmap *regmap_pmu;\n\tstruct regmap *regmap_ioc1;\n\tstruct device *dev;\n\tstruct rockchip_pin_ctrl *ctrl;\n\tstruct pinctrl_desc pctl;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct rockchip_pin_group *groups;\n\tunsigned int ngroups;\n\tstruct rockchip_pmx_func *functions;\n\tunsigned int nfunctions;\n};\n\nstruct rockchip_pll_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tint con_offset;\n\tint mode_offset;\n\tint mode_shift;\n\tint lock_shift;\n\tenum rockchip_pll_type type;\n\tu8 pll_flags;\n\tstruct rockchip_pll_rate_table *rate_table;\n};\n\nstruct rockchip_pll_rate_table {\n\tlong unsigned int rate;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int nr;\n\t\t\tunsigned int nf;\n\t\t\tunsigned int no;\n\t\t\tunsigned int nb;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int fbdiv;\n\t\t\tunsigned int postdiv1;\n\t\t\tunsigned int refdiv;\n\t\t\tunsigned int postdiv2;\n\t\t\tunsigned int dsmpd;\n\t\t\tunsigned int frac;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int m;\n\t\t\tunsigned int p;\n\t\t\tunsigned int s;\n\t\t\tunsigned int k;\n\t\t};\n\t};\n};\n\nstruct rockchip_pmu;\n\nstruct rockchip_pm_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct rockchip_domain_info *info;\n\tstruct rockchip_pmu *pmu;\n\tint num_qos;\n\tstruct regmap **qos_regmap;\n\tu32 *qos_save_regs[5];\n\tint num_clks;\n\tstruct clk_bulk_data *clks;\n\tstruct device_node *node;\n\tstruct regulator *supply;\n};\n\nstruct rockchip_pmu_info;\n\nstruct rockchip_pmu {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tconst struct rockchip_pmu_info *info;\n\tstruct mutex mutex;\n\tstruct genpd_onecell_data genpd_data;\n\tstruct generic_pm_domain *domains[0];\n};\n\nstruct rockchip_pmu_info {\n\tu32 pwr_offset;\n\tu32 status_offset;\n\tu32 req_offset;\n\tu32 idle_offset;\n\tu32 ack_offset;\n\tu32 mem_pwr_offset;\n\tu32 chain_status_offset;\n\tu32 mem_status_offset;\n\tu32 repair_status_offset;\n\tu32 clk_ungate_offset;\n\tu32 core_pwrcnt_offset;\n\tu32 gpu_pwrcnt_offset;\n\tunsigned int core_power_transition_time;\n\tunsigned int gpu_power_transition_time;\n\tint num_domains;\n\tconst struct rockchip_domain_info *domain_info;\n};\n\nstruct rockchip_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tu8 ngroups;\n};\n\nstruct rockchip_pwm_data;\n\nstruct rockchip_pwm_chip {\n\tstruct clk *clk;\n\tstruct clk *pclk;\n\tconst struct rockchip_pwm_data *data;\n\tvoid *base;\n};\n\nstruct rockchip_pwm_regs {\n\tlong unsigned int duty;\n\tlong unsigned int period;\n\tlong unsigned int cntr;\n\tlong unsigned int ctrl;\n};\n\nstruct rockchip_pwm_data {\n\tstruct rockchip_pwm_regs regs;\n\tunsigned int prescaler;\n\tbool supports_polarity;\n\tbool supports_lock;\n\tu32 enable_conf;\n};\n\nstruct rockchip_softrst {\n\tstruct reset_controller_dev rcdev;\n\tconst int *lut;\n\tvoid *reg_base;\n\tint num_regs;\n\tint num_per_reg;\n\tu8 flags;\n\tspinlock_t lock;\n};\n\nstruct rockchip_spi {\n\tstruct device *dev;\n\tstruct clk *spiclk;\n\tstruct clk *apb_pclk;\n\tvoid *regs;\n\tdma_addr_t dma_addr_rx;\n\tdma_addr_t dma_addr_tx;\n\tconst void *tx;\n\tvoid *rx;\n\tunsigned int tx_left;\n\tunsigned int rx_left;\n\tatomic_t state;\n\tu32 fifo_len;\n\tu32 freq;\n\tu8 n_bytes;\n\tu8 rsd;\n\tbool target_abort;\n\tbool cs_inactive;\n\tbool cs_high_supported;\n\tstruct spi_transfer *xfer;\n};\n\nstruct rockchip_usb3phy_port_cfg;\n\nstruct rockchip_typec_phy {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct extcon_dev *extcon;\n\tstruct regmap *grf_regs;\n\tstruct clk *clk_core;\n\tstruct clk *clk_ref;\n\tstruct reset_control *uphy_rst;\n\tstruct reset_control *pipe_rst;\n\tstruct reset_control *tcphy_rst;\n\tconst struct rockchip_usb3phy_port_cfg *port_cfgs;\n\tstruct mutex lock;\n\tbool flip;\n\tu8 mode;\n};\n\nstruct rockchip_usb2phy_port_cfg;\n\nstruct rockchip_usb2phy_port {\n\tstruct phy *phy;\n\tunsigned int port_id;\n\tbool suspended;\n\tbool vbus_attached;\n\tbool host_disconnect;\n\tint bvalid_irq;\n\tint id_irq;\n\tint ls_irq;\n\tint otg_mux_irq;\n\tstruct mutex mutex;\n\tstruct delayed_work chg_work;\n\tstruct delayed_work otg_sm_work;\n\tstruct delayed_work sm_work;\n\tconst struct rockchip_usb2phy_port_cfg *port_cfg;\n\tstruct notifier_block event_nb;\n\tenum usb_otg_state state;\n\tenum usb_dr_mode mode;\n};\n\nstruct rockchip_usb2phy_cfg;\n\nstruct rockchip_usb2phy {\n\tstruct device *dev;\n\tstruct regmap *grf;\n\tstruct regmap *usbgrf;\n\tstruct clk_bulk_data *clks;\n\tstruct clk *clk480m;\n\tstruct clk_hw clk480m_hw;\n\tint num_clks;\n\tstruct reset_control *phy_reset;\n\tenum usb_chg_state chg_state;\n\tenum power_supply_type chg_type;\n\tu8 dcd_retries;\n\tstruct extcon_dev *edev;\n\tint irq;\n\tconst struct rockchip_usb2phy_cfg *phy_cfg;\n\tstruct rockchip_usb2phy_port ports[2];\n};\n\nstruct rockchip_usb2phy_port_cfg {\n\tstruct usb2phy_reg phy_sus;\n\tstruct usb2phy_reg bvalid_det_en;\n\tstruct usb2phy_reg bvalid_det_st;\n\tstruct usb2phy_reg bvalid_det_clr;\n\tstruct usb2phy_reg disfall_en;\n\tstruct usb2phy_reg disfall_st;\n\tstruct usb2phy_reg disfall_clr;\n\tstruct usb2phy_reg disrise_en;\n\tstruct usb2phy_reg disrise_st;\n\tstruct usb2phy_reg disrise_clr;\n\tstruct usb2phy_reg idfall_det_en;\n\tstruct usb2phy_reg idfall_det_st;\n\tstruct usb2phy_reg idfall_det_clr;\n\tstruct usb2phy_reg idrise_det_en;\n\tstruct usb2phy_reg idrise_det_st;\n\tstruct usb2phy_reg idrise_det_clr;\n\tstruct usb2phy_reg ls_det_en;\n\tstruct usb2phy_reg ls_det_st;\n\tstruct usb2phy_reg ls_det_clr;\n\tstruct usb2phy_reg utmi_avalid;\n\tstruct usb2phy_reg utmi_bvalid;\n\tstruct usb2phy_reg utmi_id;\n\tstruct usb2phy_reg utmi_ls;\n\tstruct usb2phy_reg utmi_hstdet;\n};\n\nstruct rockchip_usb2phy_cfg {\n\tunsigned int reg;\n\tunsigned int num_ports;\n\tint (*phy_tuning)(struct rockchip_usb2phy *);\n\tstruct usb2phy_reg clkout_ctl;\n\tconst struct rockchip_usb2phy_port_cfg port_cfgs[2];\n\tconst struct rockchip_chg_det_reg chg_det;\n};\n\nstruct usb3phy_reg {\n\tu32 offset;\n\tu32 enable_bit;\n\tu32 write_enable;\n};\n\nstruct rockchip_usb3phy_port_cfg {\n\tunsigned int reg;\n\tstruct usb3phy_reg typec_conn_dir;\n\tstruct usb3phy_reg usb3tousb2_en;\n\tstruct usb3phy_reg external_psm;\n\tstruct usb3phy_reg pipe_status;\n\tstruct usb3phy_reg usb3_host_disable;\n\tstruct usb3phy_reg usb3_host_port;\n\tstruct usb3phy_reg uphy_dp_sel;\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct rpc_add_xprt_test {\n\tvoid (*add_xprt_test)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tvoid *data;\n};\n\nstruct rpc_auth_create_args {\n\trpc_authflavor_t pseudoflavor;\n\tconst char *target_name;\n};\n\nstruct rpc_authops {\n\tstruct module *owner;\n\trpc_authflavor_t au_flavor;\n\tchar *au_name;\n\tstruct rpc_auth * (*create)(const struct rpc_auth_create_args *, struct rpc_clnt *);\n\tvoid (*destroy)(struct rpc_auth *);\n\tint (*hash_cred)(struct auth_cred *, unsigned int);\n\tstruct rpc_cred * (*lookup_cred)(struct rpc_auth *, struct auth_cred *, int);\n\tstruct rpc_cred * (*crcreate)(struct rpc_auth *, struct auth_cred *, int, gfp_t);\n\trpc_authflavor_t (*info2flavor)(struct rpcsec_gss_info *);\n\tint (*flavor2info)(rpc_authflavor_t, struct rpcsec_gss_info *);\n\tint (*key_timeout)(struct rpc_auth *, struct rpc_cred *);\n\tint (*ping)(struct rpc_clnt *);\n};\n\nstruct rpc_bind_conn_calldata {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct rpc_buffer {\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct rpc_call_ops {\n\tvoid (*rpc_call_prepare)(struct rpc_task *, void *);\n\tvoid (*rpc_call_done)(struct rpc_task *, void *);\n\tvoid (*rpc_count_stats)(struct rpc_task *, void *);\n\tvoid (*rpc_release)(void *);\n};\n\nstruct rpc_xprt_switch;\n\nstruct rpc_cb_add_xprt_calldata {\n\tstruct rpc_xprt_switch *xps;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_pipe_dir_head {\n\tstruct list_head pdh_entries;\n\tstruct dentry *pdh_dentry;\n};\n\nstruct rpc_rtt {\n\tlong unsigned int timeo;\n\tlong unsigned int srtt[5];\n\tlong unsigned int sdrtt[5];\n\tint ntimeouts[5];\n};\n\nstruct rpc_timeout {\n\tlong unsigned int to_initval;\n\tlong unsigned int to_maxval;\n\tlong unsigned int to_increment;\n\tunsigned int to_retries;\n\tunsigned char to_exponential;\n};\n\nstruct rpc_xprt_iter_ops;\n\nstruct rpc_xprt_iter {\n\tstruct rpc_xprt_switch *xpi_xpswitch;\n\tstruct rpc_xprt *xpi_cursor;\n\tconst struct rpc_xprt_iter_ops *xpi_ops;\n};\n\nstruct rpc_iostats;\n\nstruct rpc_sysfs_client;\n\nstruct rpc_clnt {\n\trefcount_t cl_count;\n\tunsigned int cl_clid;\n\tstruct list_head cl_clients;\n\tstruct list_head cl_tasks;\n\tatomic_t cl_pid;\n\tspinlock_t cl_lock;\n\tstruct rpc_xprt *cl_xprt;\n\tconst struct rpc_procinfo *cl_procinfo;\n\tu32 cl_prog;\n\tu32 cl_vers;\n\tu32 cl_maxproc;\n\tstruct rpc_auth *cl_auth;\n\tstruct rpc_stat *cl_stats;\n\tstruct rpc_iostats *cl_metrics;\n\tunsigned int cl_softrtry: 1;\n\tunsigned int cl_softerr: 1;\n\tunsigned int cl_discrtry: 1;\n\tunsigned int cl_noretranstimeo: 1;\n\tunsigned int cl_autobind: 1;\n\tunsigned int cl_chatty: 1;\n\tunsigned int cl_shutdown: 1;\n\tunsigned int cl_netunreach_fatal: 1;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct rpc_rtt *cl_rtt;\n\tconst struct rpc_timeout *cl_timeout;\n\tatomic_t cl_swapper;\n\tint cl_nodelen;\n\tchar cl_nodename[65];\n\tstruct rpc_pipe_dir_head cl_pipedir_objects;\n\tstruct rpc_clnt *cl_parent;\n\tstruct rpc_rtt cl_rtt_default;\n\tstruct rpc_timeout cl_timeout_default;\n\tconst struct rpc_program *cl_program;\n\tconst char *cl_principal;\n\tstruct rpc_sysfs_client *cl_sysfs;\n\tunion {\n\t\tstruct rpc_xprt_iter cl_xpi;\n\t\tstruct work_struct cl_work;\n\t};\n\tconst struct cred *cl_cred;\n\tunsigned int cl_max_connect;\n\tstruct super_block *pipefs_sb;\n\tatomic_t cl_task_count;\n};\n\nstruct rpc_clock {\n\tstruct clk_divider div;\n\tstruct clk_gate gate;\n\tstruct cpg_simple_notifier csn;\n};\n\nstruct svc_xprt;\n\nstruct rpc_create_args {\n\tstruct net *net;\n\tint protocol;\n\tstruct sockaddr *address;\n\tsize_t addrsize;\n\tstruct sockaddr *saddress;\n\tconst struct rpc_timeout *timeout;\n\tconst char *servername;\n\tconst char *nodename;\n\tconst struct rpc_program *program;\n\tstruct rpc_stat *stats;\n\tu32 prognumber;\n\tu32 version;\n\trpc_authflavor_t authflavor;\n\tu32 nconnect;\n\tlong unsigned int flags;\n\tchar *client_name;\n\tstruct svc_xprt *bc_xprt;\n\tconst struct cred *cred;\n\tunsigned int max_connect;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct rpc_cred_cache {\n\tstruct hlist_head *hashtable;\n\tunsigned int hashbits;\n\tspinlock_t lock;\n};\n\nstruct rpc_credops {\n\tconst char *cr_name;\n\tint (*cr_init)(struct rpc_auth *, struct rpc_cred *);\n\tvoid (*crdestroy)(struct rpc_cred *);\n\tint (*crmatch)(struct auth_cred *, struct rpc_cred *, int);\n\tint (*crmarshal)(struct rpc_task *, struct xdr_stream *);\n\tint (*crrefresh)(struct rpc_task *);\n\tint (*crvalidate)(struct rpc_task *, struct xdr_stream *);\n\tint (*crwrap_req)(struct rpc_task *, struct xdr_stream *);\n\tint (*crunwrap_resp)(struct rpc_task *, struct xdr_stream *);\n\tint (*crkey_timeout)(struct rpc_cred *);\n\tchar * (*crstringify_acceptor)(struct rpc_cred *);\n\tbool (*crneed_reencode)(struct rpc_task *);\n};\n\nstruct rpc_filelist {\n\tconst char *name;\n\tconst struct file_operations *i_fop;\n\tumode_t mode;\n};\n\nstruct rpc_inode {\n\tstruct inode vfs_inode;\n\tvoid *private;\n\tstruct rpc_pipe *pipe;\n\twait_queue_head_t waitq;\n};\n\nstruct rpc_iostats {\n\tspinlock_t om_lock;\n\tlong unsigned int om_ops;\n\tlong unsigned int om_ntrans;\n\tlong unsigned int om_timeouts;\n\tlong long unsigned int om_bytes_sent;\n\tlong long unsigned int om_bytes_recv;\n\tktime_t om_queue;\n\tktime_t om_rtt;\n\tktime_t om_execute;\n\tlong unsigned int om_error_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rpc_pipe {\n\tstruct list_head pipe;\n\tstruct list_head in_upcall;\n\tstruct list_head in_downcall;\n\tint pipelen;\n\tint nreaders;\n\tint nwriters;\n\tint flags;\n\tstruct delayed_work queue_timeout;\n\tconst struct rpc_pipe_ops *ops;\n\tspinlock_t lock;\n\tstruct dentry *dentry;\n};\n\nstruct rpc_pipe_dir_object_ops {\n\tint (*create)(struct dentry *, struct rpc_pipe_dir_object *);\n\tvoid (*destroy)(struct dentry *, struct rpc_pipe_dir_object *);\n};\n\nstruct rpc_pipe_ops {\n\tssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char *, size_t);\n\tssize_t (*downcall)(struct file *, const char *, size_t);\n\tvoid (*release_pipe)(struct inode *);\n\tint (*open_pipe)(struct inode *);\n\tvoid (*destroy_msg)(struct rpc_pipe_msg *);\n};\n\ntypedef void (*kxdreproc_t)(struct rpc_rqst *, struct xdr_stream *, const void *);\n\ntypedef int (*kxdrdproc_t)(struct rpc_rqst *, struct xdr_stream *, void *);\n\nstruct rpc_procinfo {\n\tu32 p_proc;\n\tkxdreproc_t p_encode;\n\tkxdrdproc_t p_decode;\n\tunsigned int p_arglen;\n\tunsigned int p_replen;\n\tunsigned int p_timer;\n\tu32 p_statidx;\n\tconst char *p_name;\n};\n\nstruct rpc_program {\n\tconst char *name;\n\tu32 number;\n\tunsigned int nrvers;\n\tconst struct rpc_version **version;\n\tstruct rpc_stat *stats;\n\tconst char *pipe_dir_name;\n};\n\nstruct xdr_buf {\n\tstruct kvec head[1];\n\tstruct kvec tail[1];\n\tstruct bio_vec *bvec;\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int flags;\n\tunsigned int buflen;\n\tunsigned int len;\n};\n\nstruct rpc_rqst {\n\tstruct rpc_xprt *rq_xprt;\n\tstruct xdr_buf rq_snd_buf;\n\tstruct xdr_buf rq_rcv_buf;\n\tstruct rpc_task *rq_task;\n\tstruct rpc_cred *rq_cred;\n\t__be32 rq_xid;\n\tint rq_cong;\n\tu32 rq_seqnos[3];\n\tunsigned int rq_seqno_count;\n\tint rq_enc_pages_num;\n\tstruct page **rq_enc_pages;\n\tvoid (*rq_release_snd_buf)(struct rpc_rqst *);\n\tunion {\n\t\tstruct list_head rq_list;\n\t\tstruct rb_node rq_recv;\n\t};\n\tstruct list_head rq_xmit;\n\tstruct list_head rq_xmit2;\n\tvoid *rq_buffer;\n\tsize_t rq_callsize;\n\tvoid *rq_rbuffer;\n\tsize_t rq_rcvsize;\n\tsize_t rq_xmit_bytes_sent;\n\tsize_t rq_reply_bytes_recvd;\n\tstruct xdr_buf rq_private_buf;\n\tlong unsigned int rq_majortimeo;\n\tlong unsigned int rq_minortimeo;\n\tlong unsigned int rq_timeout;\n\tktime_t rq_rtt;\n\tunsigned int rq_retries;\n\tunsigned int rq_connect_cookie;\n\tatomic_t rq_pin;\n\tu32 rq_bytes_sent;\n\tktime_t rq_xtime;\n\tint rq_ntrans;\n\tstruct lwq_node rq_bc_list;\n\tlong unsigned int rq_bc_pa_state;\n\tstruct list_head rq_bc_pa_list;\n};\n\nstruct rpc_sysfs_client {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_clnt *clnt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt {\n\tstruct kobject kobject;\n\tstruct rpc_xprt *xprt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt_switch {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_xprt_switch *xprt_switch;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_task_setup {\n\tstruct rpc_task *task;\n\tstruct rpc_clnt *rpc_client;\n\tstruct rpc_xprt *rpc_xprt;\n\tstruct rpc_cred *rpc_op_cred;\n\tconst struct rpc_message *rpc_message;\n\tconst struct rpc_call_ops *callback_ops;\n\tvoid *callback_data;\n\tstruct workqueue_struct *workqueue;\n\tshort unsigned int flags;\n\tsigned char priority;\n};\n\nstruct rpc_version {\n\tu32 number;\n\tunsigned int nrprocs;\n\tconst struct rpc_procinfo *procs;\n\tunsigned int *counts;\n};\n\nstruct rpc_xprt_ops;\n\nstruct xprt_class;\n\nstruct rpc_xprt {\n\tstruct kref kref;\n\tconst struct rpc_xprt_ops *ops;\n\tunsigned int id;\n\tconst struct rpc_timeout *timeout;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tint prot;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tsize_t max_payload;\n\tstruct rpc_wait_queue binding;\n\tstruct rpc_wait_queue sending;\n\tstruct rpc_wait_queue pending;\n\tstruct rpc_wait_queue backlog;\n\tstruct list_head free;\n\tunsigned int max_reqs;\n\tunsigned int min_reqs;\n\tunsigned int num_reqs;\n\tlong unsigned int state;\n\tunsigned char resvport: 1;\n\tunsigned char reuseport: 1;\n\tatomic_t swapper;\n\tunsigned int bind_index;\n\tstruct list_head xprt_switch;\n\tlong unsigned int bind_timeout;\n\tlong unsigned int reestablish_timeout;\n\tstruct xprtsec_parms xprtsec;\n\tunsigned int connect_cookie;\n\tstruct work_struct task_cleanup;\n\tstruct timer_list timer;\n\tlong unsigned int last_used;\n\tlong unsigned int idle_timeout;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int max_reconnect_timeout;\n\tatomic_long_t queuelen;\n\tspinlock_t transport_lock;\n\tspinlock_t reserve_lock;\n\tspinlock_t queue_lock;\n\tu32 xid;\n\tstruct rpc_task *snd_task;\n\tstruct list_head xmit_queue;\n\tatomic_long_t xmit_queuelen;\n\tstruct svc_xprt *bc_xprt;\n\tstruct svc_serv *bc_serv;\n\tunsigned int bc_alloc_max;\n\tunsigned int bc_alloc_count;\n\tatomic_t bc_slot_count;\n\tspinlock_t bc_pa_lock;\n\tstruct list_head bc_pa_list;\n\tstruct rb_root recv_queue;\n\tstruct {\n\t\tlong unsigned int bind_count;\n\t\tlong unsigned int connect_count;\n\t\tlong unsigned int connect_start;\n\t\tlong unsigned int connect_time;\n\t\tlong unsigned int sends;\n\t\tlong unsigned int recvs;\n\t\tlong unsigned int bad_xids;\n\t\tlong unsigned int max_slots;\n\t\tlong long unsigned int req_u;\n\t\tlong long unsigned int bklog_u;\n\t\tlong long unsigned int sending_u;\n\t\tlong long unsigned int pending_u;\n\t} stat;\n\tstruct net *xprt_net;\n\tnetns_tracker ns_tracker;\n\tconst char *servername;\n\tconst char *address_strings[6];\n\tstruct callback_head rcu;\n\tconst struct xprt_class *xprt_class;\n\tstruct rpc_sysfs_xprt *xprt_sysfs;\n\tbool main;\n};\n\nstruct rpc_xprt_iter_ops {\n\tvoid (*xpi_rewind)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_xprt)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_next)(struct rpc_xprt_iter *);\n};\n\nstruct rpc_xprt_ops {\n\tvoid (*set_buffer_size)(struct rpc_xprt *, size_t, size_t);\n\tint (*reserve_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*alloc_slot)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*free_slot)(struct rpc_xprt *, struct rpc_rqst *);\n\tvoid (*rpcbind)(struct rpc_task *);\n\tvoid (*set_port)(struct rpc_xprt *, short unsigned int);\n\tvoid (*connect)(struct rpc_xprt *, struct rpc_task *);\n\tint (*get_srcaddr)(struct rpc_xprt *, char *, size_t);\n\tshort unsigned int (*get_srcport)(struct rpc_xprt *);\n\tint (*buf_alloc)(struct rpc_task *);\n\tvoid (*buf_free)(struct rpc_task *);\n\tint (*prepare_request)(struct rpc_rqst *, struct xdr_buf *);\n\tint (*send_request)(struct rpc_rqst *);\n\tvoid (*abort_send_request)(struct rpc_rqst *);\n\tvoid (*wait_for_reply_request)(struct rpc_task *);\n\tvoid (*timer)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_request)(struct rpc_task *);\n\tvoid (*close)(struct rpc_xprt *);\n\tvoid (*destroy)(struct rpc_xprt *);\n\tvoid (*set_connect_timeout)(struct rpc_xprt *, long unsigned int, long unsigned int);\n\tvoid (*print_stats)(struct rpc_xprt *, struct seq_file *);\n\tint (*enable_swap)(struct rpc_xprt *);\n\tvoid (*disable_swap)(struct rpc_xprt *);\n\tvoid (*inject_disconnect)(struct rpc_xprt *);\n\tint (*bc_setup)(struct rpc_xprt *, unsigned int);\n\tsize_t (*bc_maxpayload)(struct rpc_xprt *);\n\tunsigned int (*bc_num_slots)(struct rpc_xprt *);\n\tvoid (*bc_free_rqst)(struct rpc_rqst *);\n\tvoid (*bc_destroy)(struct rpc_xprt *, unsigned int);\n};\n\nstruct rpc_xprt_switch {\n\tspinlock_t xps_lock;\n\tstruct kref xps_kref;\n\tunsigned int xps_id;\n\tunsigned int xps_nxprts;\n\tunsigned int xps_nactive;\n\tunsigned int xps_nunique_destaddr_xprts;\n\tatomic_long_t xps_queuelen;\n\tstruct list_head xps_xprt_list;\n\tstruct net *xps_net;\n\tconst struct rpc_xprt_iter_ops *xps_iter_ops;\n\tstruct rpc_sysfs_xprt_switch *xps_sysfs;\n\tstruct callback_head xps_rcu;\n};\n\nstruct rpcb_info {\n\tu32 rpc_vers;\n\tconst struct rpc_procinfo *rpc_proc;\n};\n\nstruct rpcbind_args {\n\tstruct rpc_xprt *r_xprt;\n\tu32 r_prog;\n\tu32 r_vers;\n\tu32 r_prot;\n\tshort unsigned int r_port;\n\tconst char *r_netid;\n\tconst char *r_addr;\n\tconst char *r_owner;\n\tint r_status;\n};\n\nstruct rpcd2_clock {\n\tstruct clk_fixed_factor fixed;\n\tstruct clk_gate gate;\n};\n\nstruct rpi_exp_gpio {\n\tstruct gpio_chip gc;\n\tstruct rpi_firmware *fw;\n};\n\nstruct rpi_firmware {\n\tstruct mbox_client cl;\n\tstruct mbox_chan *chan;\n\tstruct completion c;\n\tu32 enabled;\n\tstruct kref consumers;\n};\n\nstruct rpi_firmware_clk_rate_request {\n\t__le32 id;\n\t__le32 rate;\n};\n\nstruct rpi_firmware_get_clocks_response {\n\tu32 parent;\n\tu32 id;\n};\n\nstruct rpi_firmware_property_tag_header {\n\tu32 tag;\n\tu32 buf_size;\n\tu32 req_resp_size;\n};\n\nstruct rpi_power_domain {\n\tu32 domain;\n\tbool enabled;\n\tbool old_interface;\n\tstruct generic_pm_domain base;\n\tstruct rpi_firmware *fw;\n};\n\nstruct rpi_power_domain_packet {\n\tu32 domain;\n\tu32 state;\n};\n\nstruct rpi_power_domains {\n\tbool has_new_interface;\n\tstruct genpd_onecell_data xlate;\n\tstruct rpi_firmware *fw;\n\tstruct rpi_power_domain domains[23];\n};\n\nstruct rpi_reset {\n\tstruct reset_controller_dev rcdev;\n\tstruct rpi_firmware *fw;\n};\n\nstruct rpm_clk_resource {\n\tu32 resource_type;\n\tu32 clock_id;\n\tbool branch;\n};\n\nstruct rpm_regulator_data {\n\tconst char *name;\n\tu32 type;\n\tu32 id;\n\tconst struct regulator_desc *desc;\n\tconst char *supply;\n};\n\nstruct rpm_regulator_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct rpm_smd_clk_desc {\n\tstruct clk_smd_rpm **clks;\n\tsize_t num_clks;\n\tconst struct clk_smd_rpm ** const icc_clks;\n\tsize_t num_icc_clks;\n\tbool scaling_before_handover;\n};\n\nstruct rpm_toc_entry {\n\t__le32 id;\n\t__le32 offset;\n\t__le32 size;\n};\n\nstruct rpm_toc {\n\t__le32 magic;\n\t__le32 count;\n\tstruct rpm_toc_entry entries[0];\n};\n\nstruct rpmb_descr {\n\tenum rpmb_type type;\n\tint (*route_frames)(struct device *, u8 *, unsigned int, u8 *, unsigned int);\n\tu8 *dev_id;\n\tsize_t dev_id_len;\n\tu16 reliable_wr_count;\n\tu16 capacity;\n};\n\nstruct rpmb_dev {\n\tstruct device dev;\n\tint id;\n\tstruct list_head list_node;\n\tstruct rpmb_descr descr;\n};\n\nstruct rpmb_frame {\n\tu8 stuff[196];\n\tu8 key_mac[32];\n\tu8 data[256];\n\tu8 nonce[16];\n\t__be32 write_counter;\n\t__be16 addr;\n\t__be16 block_count;\n\t__be16 result;\n\t__be16 req_resp;\n};\n\nstruct rpmh_ctrlr {\n\tstruct list_head cache;\n\tspinlock_t cache_lock;\n\tbool dirty;\n\tstruct list_head batch_cache;\n};\n\nstruct rpmh_vreg_hw_data;\n\nstruct rpmh_vreg {\n\tstruct device *dev;\n\tu32 addr;\n\tstruct regulator_desc rdesc;\n\tconst struct rpmh_vreg_hw_data *hw_data;\n\tbool always_wait_for_ack;\n\tint enabled;\n\tbool bypassed;\n\tint voltage_selector;\n\tunsigned int mode;\n};\n\nstruct rpmh_vreg_hw_data {\n\tenum rpmh_regulator_type regulator_type;\n\tconst struct regulator_ops *ops;\n\tconst struct linear_range *voltage_ranges;\n\tint n_linear_ranges;\n\tint n_voltages;\n\tint hpm_min_load_uA;\n\tconst int *pmic_mode_map;\n\tunsigned int (*of_map_mode)(unsigned int);\n};\n\nstruct rpmh_vreg_init_data {\n\tconst char *name;\n\tenum regulator_hw_type vreg_hw_type;\n\tint index;\n\tconst char *supply_name;\n\tconst struct rpmh_vreg_hw_data *hw_data;\n};\n\nstruct rpmhpd {\n\tstruct device *dev;\n\tstruct generic_pm_domain pd;\n\tstruct generic_pm_domain *parent;\n\tstruct rpmhpd *peer;\n\tconst bool active_only;\n\tunsigned int corner;\n\tunsigned int active_corner;\n\tunsigned int enable_corner;\n\tu32 level[32];\n\tsize_t level_count;\n\tbool enabled;\n\tconst char *res_name;\n\tu32 addr;\n\tbool state_synced;\n\tbool skip_retention_level;\n};\n\nstruct rpmhpd_desc {\n\tstruct rpmhpd **rpmhpds;\n\tsize_t num_pds;\n};\n\nstruct rpmpd {\n\tstruct generic_pm_domain pd;\n\tstruct generic_pm_domain *parent;\n\tstruct rpmpd *peer;\n\tconst bool active_only;\n\tunsigned int corner;\n\tbool enabled;\n\tconst int res_type;\n\tconst int res_id;\n\tunsigned int max_state;\n\t__le32 key;\n\tbool state_synced;\n};\n\nstruct rpmpd_desc {\n\tstruct rpmpd **rpmpds;\n\tsize_t num_pds;\n\tunsigned int max_state;\n};\n\nstruct rpmpd_req {\n\t__le32 key;\n\t__le32 nbytes;\n\t__le32 value;\n};\n\nstruct rpmsg_channel_info {\n\tchar name[32];\n\tu32 src;\n\tu32 dst;\n};\n\nstruct rpmsg_device_ops {\n\tstruct rpmsg_device * (*create_channel)(struct rpmsg_device *, struct rpmsg_channel_info *);\n\tint (*release_channel)(struct rpmsg_device *, struct rpmsg_channel_info *);\n\tstruct rpmsg_endpoint * (*create_ept)(struct rpmsg_device *, rpmsg_rx_cb_t, void *, struct rpmsg_channel_info);\n\tint (*announce_create)(struct rpmsg_device *);\n\tint (*announce_destroy)(struct rpmsg_device *);\n};\n\nstruct rpmsg_driver {\n\tstruct device_driver drv;\n\tconst struct rpmsg_device_id *id_table;\n\tint (*probe)(struct rpmsg_device *);\n\tvoid (*remove)(struct rpmsg_device *);\n\tint (*callback)(struct rpmsg_device *, void *, int, void *, u32);\n\tint (*flowcontrol)(struct rpmsg_device *, void *, bool);\n};\n\nstruct rpmsg_endpoint_ops {\n\tvoid (*destroy_ept)(struct rpmsg_endpoint *);\n\tint (*send)(struct rpmsg_endpoint *, void *, int);\n\tint (*sendto)(struct rpmsg_endpoint *, void *, int, u32);\n\tint (*trysend)(struct rpmsg_endpoint *, void *, int);\n\tint (*trysendto)(struct rpmsg_endpoint *, void *, int, u32);\n\t__poll_t (*poll)(struct rpmsg_endpoint *, struct file *, poll_table *);\n\tint (*set_flow_control)(struct rpmsg_endpoint *, bool, u32);\n\tssize_t (*get_mtu)(struct rpmsg_endpoint *);\n};\n\nstruct rpmsg_hdr {\n\t__rpmsg32 src;\n\t__rpmsg32 dst;\n\t__rpmsg32 reserved;\n\t__rpmsg16 len;\n\t__rpmsg16 flags;\n\tu8 data[0];\n};\n\nstruct rpmsg_ns_msg {\n\tchar name[32];\n\t__rpmsg32 addr;\n\t__rpmsg32 flags;\n};\n\nstruct rproc_ops;\n\nstruct rproc {\n\tstruct list_head node;\n\tstruct iommu_domain *domain;\n\tconst char *name;\n\tconst char *firmware;\n\tvoid *priv;\n\tstruct rproc_ops *ops;\n\tstruct device dev;\n\tatomic_t power;\n\tunsigned int state;\n\tenum rproc_dump_mechanism dump_conf;\n\tstruct mutex lock;\n\tstruct dentry *dbg_dir;\n\tstruct list_head traces;\n\tint num_traces;\n\tstruct list_head carveouts;\n\tstruct list_head mappings;\n\tu64 bootaddr;\n\tstruct list_head rvdevs;\n\tstruct list_head subdevs;\n\tstruct idr notifyids;\n\tint index;\n\tstruct work_struct crash_handler;\n\tunsigned int crash_cnt;\n\tbool recovery_disabled;\n\tint max_notifyid;\n\tstruct resource_table *table_ptr;\n\tstruct resource_table *clean_table;\n\tstruct resource_table *cached_table;\n\tsize_t table_sz;\n\tbool has_iommu;\n\tbool auto_boot;\n\tbool sysfs_read_only;\n\tstruct list_head dump_segments;\n\tint nb_vdev;\n\tu8 elf_class;\n\tu16 elf_machine;\n\tstruct cdev cdev;\n\tbool cdev_put_on_release;\n\tlong unsigned int features[1];\n};\n\nstruct rproc_coredump_state {\n\tstruct rproc *rproc;\n\tvoid *header;\n\tstruct completion dump_done;\n};\n\nstruct rproc_mem_entry {\n\tvoid *va;\n\tbool is_iomem;\n\tdma_addr_t dma;\n\tsize_t len;\n\tu32 da;\n\tvoid *priv;\n\tchar name[32];\n\tstruct list_head node;\n\tu32 rsc_offset;\n\tu32 flags;\n\tu32 of_resm_idx;\n\tint (*alloc)(struct rproc *, struct rproc_mem_entry *);\n\tint (*release)(struct rproc *, struct rproc_mem_entry *);\n};\n\nstruct rproc_debug_trace {\n\tstruct rproc *rproc;\n\tstruct dentry *tfile;\n\tstruct list_head node;\n\tstruct rproc_mem_entry trace_mem;\n};\n\nstruct rproc_dump_segment {\n\tstruct list_head node;\n\tdma_addr_t da;\n\tsize_t size;\n\tvoid *priv;\n\tvoid (*dump)(struct rproc *, struct rproc_dump_segment *, void *, size_t, size_t);\n\tloff_t offset;\n};\n\nstruct rproc_ops {\n\tint (*prepare)(struct rproc *);\n\tint (*unprepare)(struct rproc *);\n\tint (*start)(struct rproc *);\n\tint (*stop)(struct rproc *);\n\tint (*attach)(struct rproc *);\n\tint (*detach)(struct rproc *);\n\tvoid (*kick)(struct rproc *, int);\n\tvoid * (*da_to_va)(struct rproc *, u64, size_t, bool *);\n\tint (*parse_fw)(struct rproc *, const struct firmware *);\n\tint (*handle_rsc)(struct rproc *, u32, void *, int, int);\n\tstruct resource_table * (*find_loaded_rsc_table)(struct rproc *, const struct firmware *);\n\tstruct resource_table * (*get_loaded_rsc_table)(struct rproc *, size_t *);\n\tint (*load)(struct rproc *, const struct firmware *);\n\tint (*sanity_check)(struct rproc *, const struct firmware *);\n\tu64 (*get_boot_addr)(struct rproc *, const struct firmware *);\n\tlong unsigned int (*panic)(struct rproc *);\n\tvoid (*coredump)(struct rproc *);\n};\n\nstruct rproc_subdev {\n\tstruct list_head node;\n\tint (*prepare)(struct rproc_subdev *);\n\tint (*start)(struct rproc_subdev *);\n\tvoid (*stop)(struct rproc_subdev *, bool);\n\tvoid (*unprepare)(struct rproc_subdev *);\n};\n\nstruct rproc_vdev;\n\nstruct rproc_vring {\n\tvoid *va;\n\tint num;\n\tu32 da;\n\tu32 align;\n\tint notifyid;\n\tstruct rproc_vdev *rvdev;\n\tstruct virtqueue *vq;\n};\n\nstruct rproc_vdev {\n\tstruct rproc_subdev subdev;\n\tstruct platform_device *pdev;\n\tunsigned int id;\n\tstruct list_head node;\n\tstruct rproc *rproc;\n\tstruct rproc_vring vring[2];\n\tu32 rsc_offset;\n\tu32 index;\n};\n\nstruct rproc_vdev_data {\n\tu32 rsc_offset;\n\tunsigned int id;\n\tu32 index;\n\tstruct fw_rsc_vdev *rsc;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[2];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tcall_single_data_t nohz_csd;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tunsigned int numa_migrate_on;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 64;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tstruct sched_avg avg_irq;\n\tstruct sched_avg avg_hw;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tu64 prev_irq_time;\n\tu64 psi_irq_time;\n\tu64 prev_steal_time;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tktime_t hrtick_time;\n\tstruct cpuidle_state *idle_state;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tcpumask_var_t scratch_mask;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t cfsb_csd;\n\tstruct list_head cfsb_csd_list;\n\tatomic_t nr_iowait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\nstruct rq_wait;\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n};\n\nstruct rs9_chip_info {\n\tunsigned int num_clks;\n\tu8 outshift;\n\tu8 did;\n};\n\nstruct rs9_driver_data {\n\tstruct i2c_client *client;\n\tstruct regmap *regmap;\n\tconst struct rs9_chip_info *chip_info;\n\tstruct clk_hw *clk_dif[8];\n\tu8 pll_amplitude;\n\tu8 pll_ssc;\n\tu8 clk_dif_sr;\n};\n\nstruct rsa_key {\n\tconst u8 *n;\n\tconst u8 *e;\n\tconst u8 *d;\n\tconst u8 *p;\n\tconst u8 *q;\n\tconst u8 *dp;\n\tconst u8 *dq;\n\tconst u8 *qinv;\n\tsize_t n_sz;\n\tsize_t e_sz;\n\tsize_t d_sz;\n\tsize_t p_sz;\n\tsize_t q_sz;\n\tsize_t dp_sz;\n\tsize_t dq_sz;\n\tsize_t qinv_sz;\n};\n\nstruct rsa_mpi_key {\n\tMPI n;\n\tMPI e;\n\tMPI d;\n\tMPI p;\n\tMPI q;\n\tMPI dp;\n\tMPI dq;\n\tMPI qinv;\n};\n\nstruct rsassa_pkcs1_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct rsassa_pkcs1_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n\tconst struct hash_prefix *hash_prefix;\n};\n\nstruct rsc {\n\tstruct cache_head h;\n\tstruct xdr_netobj handle;\n\tstruct svc_cred cred;\n\tstruct gss_svc_seq_data seqdata;\n\tstruct gss_ctx *mechctx;\n\tstruct callback_head callback_head;\n};\n\nstruct rsc_drv;\n\nstruct tcs_group {\n\tstruct rsc_drv *drv;\n\tint type;\n\tu32 mask;\n\tu32 offset;\n\tint num_tcs;\n\tint ncpt;\n\tconst struct tcs_request *req[3];\n\tlong unsigned int slots[1];\n};\n\nstruct rsc_ver {\n\tu32 major;\n\tu32 minor;\n};\n\nstruct rsc_drv {\n\tconst char *name;\n\tvoid *base;\n\tvoid *tcs_base;\n\tint id;\n\tint num_tcs;\n\tstruct notifier_block rsc_pm;\n\tstruct notifier_block genpd_nb;\n\tatomic_t cpus_in_pm;\n\tstruct tcs_group tcs[4];\n\tlong unsigned int tcs_in_use[1];\n\tspinlock_t lock;\n\twait_queue_head_t tcs_wait;\n\tstruct rpmh_ctrlr client;\n\tstruct device *dev;\n\tstruct rsc_ver ver;\n\tu32 *regs;\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rsi {\n\tstruct cache_head h;\n\tstruct xdr_netobj in_handle;\n\tstruct xdr_netobj in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tint major_status;\n\tint minor_status;\n\tstruct callback_head callback_head;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rsst_req_update {\n\tstruct ntmp_req_by_eid rbe;\n\tu8 groups[0];\n};\n\nstruct rst_config {\n\tunsigned int modemr;\n\tint (*configure)(void *);\n\tint (*set_rproc_boot_addr)(u64);\n};\n\nstruct rsvd_count {\n\tint ndelayed;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct rswitch_desc {\n\t__le16 info_ds;\n\tu8 die_dt;\n\t__u8 dptrh;\n\t__le32 dptrl;\n};\n\nstruct rswitch_private;\n\nstruct rswitch_gwca_queue;\n\nstruct rswitch_etha;\n\nstruct rswitch_device {\n\tstruct rswitch_private *priv;\n\tstruct net_device *ndev;\n\tstruct napi_struct napi;\n\tvoid *addr;\n\tstruct rswitch_gwca_queue *tx_queue;\n\tstruct rswitch_gwca_queue *rx_queue;\n\tstruct sk_buff *ts_skb[256];\n\tlong unsigned int ts_skb_used[4];\n\tbool disabled;\n\tstruct list_head list;\n\tint port;\n\tstruct rswitch_etha *etha;\n\tstruct device_node *np_port;\n\tstruct phy *serdes;\n\tstruct net_device *brdev;\n\tunsigned int learning_requested: 1;\n\tunsigned int learning_offloaded: 1;\n\tunsigned int forwarding_requested: 1;\n\tunsigned int forwarding_offloaded: 1;\n};\n\nstruct rswitch_etha {\n\tunsigned int index;\n\tvoid *addr;\n\tvoid *coma_addr;\n\tbool external_phy;\n\tstruct mii_bus *mii;\n\tphy_interface_t phy_interface;\n\tu32 psmcs;\n\tu8 mac_addr[32];\n\tint link;\n\tint speed;\n\tbool operated;\n};\n\nstruct rswitch_ext_desc {\n\tstruct rswitch_desc desc;\n\t__le64 info1;\n};\n\nstruct rswitch_ext_ts_desc {\n\tstruct rswitch_desc desc;\n\t__le64 info1;\n\t__le32 ts_nsec;\n\t__le32 ts_sec;\n};\n\nstruct rswitch_ts_desc;\n\nstruct rswitch_gwca_queue {\n\tunion {\n\t\tstruct rswitch_ext_desc *tx_ring;\n\t\tstruct rswitch_ext_ts_desc *rx_ring;\n\t\tstruct rswitch_ts_desc *ts_ring;\n\t};\n\tdma_addr_t ring_dma;\n\tunsigned int ring_size;\n\tunsigned int cur;\n\tunsigned int dirty;\n\tunsigned int index;\n\tbool dir_tx;\n\tstruct net_device *ndev;\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff **skbs;\n\t\t\tdma_addr_t *unmap_addrs;\n\t\t};\n\t\tstruct {\n\t\t\tvoid **rx_bufs;\n\t\t\tstruct sk_buff *skb_fstart;\n\t\t\tu16 pkt_len;\n\t\t};\n\t};\n};\n\nstruct rswitch_gwca {\n\tunsigned int index;\n\tstruct rswitch_desc *linkfix_table;\n\tdma_addr_t linkfix_table_dma;\n\tu32 linkfix_table_size;\n\tstruct rswitch_gwca_queue *queues;\n\tint num_queues;\n\tstruct rswitch_gwca_queue ts_queue;\n\tlong unsigned int used[2];\n\tu32 tx_irq_bits[4];\n\tu32 rx_irq_bits[4];\n};\n\nstruct rswitch_mac_table_entry;\n\nstruct rswitch_mfwd {\n\tstruct rswitch_mac_table_entry *mac_table_entries;\n\tint num_mac_table_entries;\n};\n\nstruct rswitch_private {\n\tstruct platform_device *pdev;\n\tvoid *addr;\n\tstruct rcar_gen4_ptp_private *ptp_priv;\n\tstruct rswitch_device *rdev[3];\n\tlong unsigned int opened_ports[1];\n\tstruct rswitch_gwca gwca;\n\tstruct rswitch_etha etha[3];\n\tstruct rswitch_mfwd mfwd;\n\tstruct list_head port_list;\n\tspinlock_t lock;\n\tstruct clk *clk;\n\tbool etha_no_runtime_change;\n\tbool gwca_halt;\n\tstruct net_device *offload_brdev;\n\tenum hwtstamp_tx_types tstamp_tx_ctrl;\n\tenum hwtstamp_rx_filters tstamp_rx_ctrl;\n};\n\nstruct rswitch_ts_desc {\n\tstruct rswitch_desc desc;\n\t__le32 ts_nsec;\n\t__le32 ts_sec;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\t__kernel_size_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct sigcontext {\n\t__u64 fault_address;\n\t__u64 regs[31];\n\t__u64 sp;\n\t__u64 pc;\n\t__u64 pstate;\n\tlong: 64;\n\t__u8 __reserved[4096];\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tsigset_t uc_sigmask;\n\t__u8 __unused[120];\n\tlong: 64;\n\tstruct sigcontext uc_mcontext;\n};\n\nstruct rt_sigframe {\n\tstruct siginfo info;\n\tstruct ucontext uc;\n};\n\nstruct rt_sigframe_user_layout {\n\tstruct rt_sigframe *sigframe;\n\tstruct frame_record *next_frame;\n\tlong unsigned int size;\n\tlong unsigned int limit;\n\tlong unsigned int fpsimd_offset;\n\tlong unsigned int esr_offset;\n\tlong unsigned int gcs_offset;\n\tlong unsigned int sve_offset;\n\tlong unsigned int tpidr2_offset;\n\tlong unsigned int za_offset;\n\tlong unsigned int zt_offset;\n\tlong unsigned int fpmr_offset;\n\tlong unsigned int poe_offset;\n\tlong unsigned int extra_offset;\n\tlong unsigned int end_offset;\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtd119x_rtc {\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct rtc_device *rtcdev;\n\tunsigned int base_year;\n};\n\nstruct rtd119x_watchdog_device {\n\tstruct watchdog_device wdt_dev;\n\tvoid *base;\n\tstruct clk *clk;\n};\n\nstruct rtd_gpio_info;\n\nstruct rtd_gpio {\n\tstruct gpio_chip gpio_chip;\n\tconst struct rtd_gpio_info *info;\n\tvoid *base;\n\tvoid *irq_base;\n\tunsigned int irqs[2];\n\traw_spinlock_t lock;\n};\n\nstruct rtd_gpio_info {\n\tconst char *name;\n\tunsigned int gpio_base;\n\tunsigned int num_gpios;\n\tu8 *dir_offset;\n\tu8 *dato_offset;\n\tu8 *dati_offset;\n\tu8 *ie_offset;\n\tu8 *dp_offset;\n\tu8 *gpa_offset;\n\tu8 *gpda_offset;\n\tu8 *deb_offset;\n\tu8 *deb_val;\n\tu8 (*get_deb_setval)(const struct rtd_gpio_info *, unsigned int, u8, u8 *, u8 *);\n};\n\nstruct rtd_pin_config_desc {\n\tconst char *name;\n\tunsigned int reg_offset;\n\tunsigned int base_bit;\n\tunsigned int pud_en_offset;\n\tunsigned int pud_sel_offset;\n\tunsigned int curr_offset;\n\tunsigned int smt_offset;\n\tunsigned int power_offset;\n\tunsigned int curr_type;\n};\n\nstruct rtd_pin_mux_desc;\n\nstruct rtd_pin_desc {\n\tconst char *name;\n\tunsigned int mux_offset;\n\tu32 mux_mask;\n\tconst struct rtd_pin_mux_desc *functions;\n};\n\nstruct rtd_pin_func_desc {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct rtd_pin_group_desc {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int num_pins;\n};\n\nstruct rtd_pin_mux_desc {\n\tconst char *name;\n\tu32 mux_value;\n};\n\nstruct rtd_pin_reg_list {\n\tunsigned int reg_offset;\n\tunsigned int val;\n};\n\nstruct rtd_pin_sconfig_desc {\n\tconst char *name;\n\tunsigned int reg_offset;\n\tunsigned int dcycle_offset;\n\tunsigned int dcycle_maskbits;\n\tunsigned int ndrive_offset;\n\tunsigned int ndrive_maskbits;\n\tunsigned int pdrive_offset;\n\tunsigned int pdrive_maskbits;\n};\n\nstruct rtd_pinctrl_desc;\n\nstruct rtd_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pcdev;\n\tvoid *base;\n\tstruct pinctrl_desc desc;\n\tconst struct rtd_pinctrl_desc *info;\n\tstruct regmap *regmap_pinctrl;\n};\n\nstruct rtd_pinctrl_desc {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int num_pins;\n\tconst struct rtd_pin_group_desc *groups;\n\tunsigned int num_groups;\n\tconst struct rtd_pin_func_desc *functions;\n\tunsigned int num_functions;\n\tconst struct rtd_pin_desc *muxes;\n\tunsigned int num_muxes;\n\tconst struct rtd_pin_config_desc *configs;\n\tunsigned int num_configs;\n\tconst struct rtd_pin_sconfig_desc *sconfigs;\n\tunsigned int num_sconfigs;\n\tstruct rtd_pin_reg_list *lists;\n\tunsigned int num_regs;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtl821x_priv {\n\tbool enable_aldps;\n\tbool disable_clk_out;\n\tstruct clk *clk;\n\tu16 iner;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtree_node {\n\tstruct list_head list;\n\tlong unsigned int *data;\n};\n\nstruct rtsn_desc {\n\t__le16 info_ds;\n\t__u8 info;\n\tu8 die_dt;\n\t__le32 dptr;\n};\n\nstruct rtsn_ext_desc {\n\t__le16 info_ds;\n\t__u8 info;\n\tu8 die_dt;\n\t__le32 dptr;\n\t__le64 info1;\n};\n\nstruct rtsn_ext_ts_desc {\n\t__le16 info_ds;\n\t__u8 info;\n\tu8 die_dt;\n\t__le32 dptr;\n\t__le64 info1;\n\t__le32 ts_nsec;\n\t__le32 ts_sec;\n};\n\nstruct rtsn_private {\n\tstruct net_device *ndev;\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tstruct rcar_gen4_ptp_private *ptp_priv;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tu32 num_tx_ring;\n\tu32 num_rx_ring;\n\tu32 tx_desc_bat_size;\n\tdma_addr_t tx_desc_bat_dma;\n\tstruct rtsn_desc *tx_desc_bat;\n\tu32 rx_desc_bat_size;\n\tdma_addr_t rx_desc_bat_dma;\n\tstruct rtsn_desc *rx_desc_bat;\n\tdma_addr_t tx_desc_dma;\n\tdma_addr_t rx_desc_dma;\n\tstruct rtsn_ext_desc *tx_ring;\n\tstruct rtsn_ext_ts_desc *rx_ring;\n\tstruct sk_buff **tx_skb;\n\tstruct sk_buff **rx_skb;\n\tspinlock_t lock;\n\tu32 cur_tx;\n\tu32 dirty_tx;\n\tu32 cur_rx;\n\tu32 dirty_rx;\n\tu8 ts_tag;\n\tstruct napi_struct napi;\n\tstruct rtnl_link_stats64 stats;\n\tstruct mii_bus *mii;\n\tphy_interface_t iface;\n\tint link;\n\tint speed;\n\tint tx_data_irq;\n\tint rx_data_irq;\n\tu32 tstamp_tx_ctrl;\n\tu32 tstamp_rx_ctrl;\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rwdt_priv {\n\tvoid *base;\n\tstruct watchdog_device wdev;\n\tlong unsigned int clk_rate;\n\tu8 cks;\n\tstruct clk *clk;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct rx_ring_info {\n\tstruct sk_buff *skb;\n\tdma_addr_t data_addr;\n\t__u32 data_size;\n\tdma_addr_t frag_addr[2];\n};\n\nstruct rz_dmac_icu {\n\tstruct platform_device *pdev;\n\tu8 dmac_index;\n};\n\nstruct rz_dmac_chan;\n\nstruct rz_dmac {\n\tstruct dma_device engine;\n\tstruct rz_dmac_icu icu;\n\tstruct device *dev;\n\tstruct reset_control *rstc;\n\tvoid *base;\n\tvoid *ext_base;\n\tunsigned int n_channels;\n\tstruct rz_dmac_chan *channels;\n\tbool has_icu;\n\tlong unsigned int modules[16];\n};\n\nstruct rz_dmac_desc;\n\nstruct rz_lmdesc;\n\nstruct rz_dmac_chan {\n\tstruct virt_dma_chan vc;\n\tvoid *ch_base;\n\tvoid *ch_cmn_base;\n\tunsigned int index;\n\tstruct rz_dmac_desc *desc;\n\tint descs_allocated;\n\tdma_addr_t src_per_address;\n\tdma_addr_t dst_per_address;\n\tu32 chcfg;\n\tu32 chctrl;\n\tint mid_rid;\n\tstruct list_head ld_free;\n\tstruct list_head ld_queue;\n\tstruct list_head ld_active;\n\tstruct {\n\t\tstruct rz_lmdesc *base;\n\t\tstruct rz_lmdesc *head;\n\t\tstruct rz_lmdesc *tail;\n\t\tdma_addr_t base_dma;\n\t} lmdesc;\n};\n\nstruct rz_dmac_desc {\n\tstruct virt_dma_desc vd;\n\tdma_addr_t src;\n\tdma_addr_t dest;\n\tsize_t len;\n\tstruct list_head node;\n\tenum dma_transfer_direction direction;\n\tenum rz_dmac_prep_type type;\n\tstruct scatterlist *sg;\n\tunsigned int sgcount;\n};\n\nstruct rz_lmdesc {\n\tu32 header;\n\tu32 sa;\n\tu32 da;\n\tu32 tb;\n\tu32 chcfg;\n\tu32 chitvl;\n\tu32 chext;\n\tu32 nxla;\n};\n\nstruct rz_mtu3_channel {\n\tstruct device *dev;\n\tunsigned int channel_number;\n\tstruct mutex lock;\n\tbool is_busy;\n};\n\nstruct rz_mtu3 {\n\tstruct clk *clk;\n\tstruct rz_mtu3_channel channels[9];\n\tvoid *priv_data;\n};\n\nstruct rz_mtu3_priv {\n\tvoid *mmio;\n\tstruct reset_control *rstc;\n\tspinlock_t lock;\n};\n\nstruct rz_sysc {\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct rz_sysc_soc_id_init_data;\n\nstruct rz_sysc_init_data {\n\tconst struct rz_sysc_soc_id_init_data *soc_id_init_data;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tu32 max_register;\n};\n\nstruct soc_device_attribute;\n\nstruct rz_sysc_soc_id_init_data {\n\tconst char * const family;\n\tu32 id;\n\tu32 devid_offset;\n\tu32 revision_mask;\n\tu32 specific_id_mask;\n\tvoid (*print_id)(struct device *, void *, struct soc_device_attribute *);\n};\n\nstruct rzg2l_mod_clk;\n\nstruct rzg2l_reset;\n\nstruct rzg2l_cpg_info {\n\tconst struct cpg_core_clk___3 *core_clks;\n\tunsigned int num_core_clks;\n\tunsigned int last_dt_core_clk;\n\tunsigned int num_total_core_clks;\n\tconst struct rzg2l_mod_clk *mod_clks;\n\tunsigned int num_mod_clks;\n\tunsigned int num_hw_mod_clks;\n\tconst unsigned int *no_pm_mod_clks;\n\tunsigned int num_no_pm_mod_clks;\n\tconst struct rzg2l_reset *resets;\n\tunsigned int num_resets;\n\tconst unsigned int *crit_mod_clks;\n\tunsigned int num_crit_mod_clks;\n\tbool has_clk_mon_regs;\n};\n\nstruct rzg2l_pll5_mux_dsi_div_param {\n\tu8 clksrc;\n\tu8 dsi_div_a;\n\tu8 dsi_div_b;\n};\n\nstruct rzg2l_cpg_priv {\n\tstruct reset_controller_dev rcdev;\n\tstruct device *dev;\n\tvoid *base;\n\tspinlock_t rmw_lock;\n\tstruct clk **clks;\n\tunsigned int num_core_clks;\n\tunsigned int num_mod_clks;\n\tunsigned int num_resets;\n\tunsigned int last_dt_core_clk;\n\tconst struct rzg2l_cpg_info *info;\n\tstruct generic_pm_domain genpd;\n\tstruct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;\n};\n\nstruct rzg2l_dedicated_configs {\n\tconst char *name;\n\tu64 config;\n};\n\nstruct rzg2l_register_offsets {\n\tu16 pwpr;\n\tu16 sd_ch;\n\tu16 eth_poc;\n\tu16 oen;\n};\n\nstruct rzg2l_hwcfg {\n\tconst struct rzg2l_register_offsets regs;\n\tu16 iolh_groupa_ua[12];\n\tu16 iolh_groupb_ua[12];\n\tu16 iolh_groupc_ua[12];\n\tu16 iolh_groupb_oi[4];\n\tu16 tint_start_index;\n\tbool drive_strength_ua;\n\tbool oen_pwpr_lock;\n\tu8 func_base;\n\tu8 oen_max_pin;\n\tu8 oen_max_port;\n};\n\nstruct rzg2l_irqc_reg_cache {\n\tu32 iitsr;\n\tu32 titsr[2];\n};\n\nstruct rzg2l_irqc_priv {\n\tvoid *base;\n\tconst struct irq_chip *irqchip;\n\tstruct irq_fwspec fwspec[41];\n\traw_spinlock_t lock;\n\tstruct rzg2l_irqc_reg_cache cache;\n};\n\nstruct rzg2l_mod_clk {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int parent;\n\tu32 mstop_conf;\n\tu16 off;\n\tu8 bit;\n\tbool is_coupled;\n};\n\nstruct rzg2l_pinctrl_data;\n\nstruct rzg2l_pinctrl_pin_settings;\n\nstruct rzg2l_pinctrl_reg_cache;\n\nstruct rzg2l_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc desc;\n\tstruct pinctrl_pin_desc *pins;\n\tconst struct rzg2l_pinctrl_data *data;\n\tvoid *base;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range gpio_range;\n\tlong unsigned int tint_slot[1];\n\tspinlock_t bitmap_lock;\n\tunsigned int hwirq[32];\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct rzg2l_pinctrl_pin_settings *settings;\n\tstruct rzg2l_pinctrl_reg_cache *cache;\n\tstruct rzg2l_pinctrl_reg_cache *dedicated_cache;\n\tatomic_t wakeup_path;\n};\n\nstruct rzg2l_pinctrl_data {\n\tconst char * const *port_pins;\n\tconst u64 *port_pin_configs;\n\tunsigned int n_ports;\n\tconst struct rzg2l_dedicated_configs *dedicated_pins;\n\tunsigned int n_port_pins;\n\tunsigned int n_dedicated_pins;\n\tconst struct rzg2l_hwcfg *hwcfg;\n\tconst u64 *variable_pin_cfg;\n\tunsigned int n_variable_pin_cfg;\n\tunsigned int num_custom_params;\n\tconst struct pinconf_generic_params *custom_params;\n\tconst struct pin_config_item *custom_conf_items;\n\tvoid (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *, bool);\n\tvoid (*pmc_writeb)(struct rzg2l_pinctrl *, u8, u16);\n\tint (*pin_to_oen_bit)(struct rzg2l_pinctrl *, unsigned int);\n\tint (*hw_to_bias_param)(unsigned int);\n\tint (*bias_param_to_hw)(enum pin_config_param);\n};\n\nstruct rzg2l_pinctrl_pin_settings {\n\tu16 power_source;\n\tu16 drive_strength_ua;\n};\n\nstruct rzg2l_pinctrl_reg_cache {\n\tu8 *p;\n\tu16 *pm;\n\tu8 *pmc;\n\tu32 *pfc;\n\tu32 *iolh[2];\n\tu32 *ien[2];\n\tu32 *pupd[2];\n\tu32 *smt;\n\tu8 sd_ch[2];\n\tu8 eth_poc[2];\n\tu8 oen;\n\tu8 qspi;\n};\n\nstruct rzg2l_pll5_param {\n\tu32 pl5_fracin;\n\tu16 pl5_intin;\n\tu8 pl5_refdiv;\n\tu8 pl5_postdiv1;\n\tu8 pl5_postdiv2;\n\tu8 pl5_spread;\n};\n\nstruct rzg2l_reset {\n\tu16 off;\n\tu8 bit;\n\ts8 monbit;\n};\n\nstruct rzg2l_thermal_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct thermal_zone_device *zone;\n\tstruct reset_control *rstc;\n\tu32 calib0;\n\tu32 calib1;\n};\n\nstruct rzg2l_usbphy_ctrl_priv {\n\tstruct reset_controller_dev rcdev;\n\tstruct reset_control *rstc;\n\tvoid *base;\n\tstruct platform_device *vdev;\n\tstruct regmap_field *pwrrdy;\n\tspinlock_t lock;\n};\n\nstruct rzg2l_wdt_priv {\n\tvoid *base;\n\tstruct watchdog_device wdev;\n\tstruct reset_control *rstc;\n\tlong unsigned int osc_clk_rate;\n\tlong unsigned int delay;\n\tstruct clk *pclk;\n\tstruct clk *osc_clk;\n\tenum rz_wdt_type devtype;\n};\n\nstruct rzg3e_thermal_priv;\n\nstruct rzg3e_thermal_info {\n\tint (*get_trim)(struct rzg3e_thermal_priv *);\n\tint temp_d_mc;\n\tint temp_e_mc;\n};\n\nstruct rzg3e_thermal_priv {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct thermal_zone_device *zone;\n\tstruct reset_control *rstc;\n\tconst struct rzg3e_thermal_info *info;\n\tu16 trmval0;\n\tu16 trmval1;\n\tstruct mutex lock;\n};\n\nstruct rzg3s_pcie_msi {\n\tstruct irq_domain *domain;\n\tlong unsigned int map[1];\n\tdma_addr_t dma_addr;\n\tdma_addr_t window_base;\n\tlong unsigned int pages;\n\tstruct mutex map_lock;\n\tint irq;\n};\n\nstruct rzg3s_pcie_port {\n\tstruct clk *refclk;\n\tu32 vendor_id;\n\tu32 device_id;\n};\n\nstruct rzg3s_pcie_soc_data;\n\nstruct rzg3s_pcie_host {\n\tvoid *axi;\n\tvoid *pcie;\n\tstruct device *dev;\n\tstruct reset_control_bulk_data *power_resets;\n\tstruct reset_control_bulk_data *cfg_resets;\n\tstruct regmap *sysc;\n\tstruct irq_domain *intx_domain;\n\tconst struct rzg3s_pcie_soc_data *data;\n\tstruct rzg3s_pcie_msi msi;\n\tstruct rzg3s_pcie_port port;\n\traw_spinlock_t hw_lock;\n\tint intx_irqs[4];\n\tint max_link_speed;\n};\n\nstruct rzg3s_pcie_soc_data {\n\tint (*init_phy)(struct rzg3s_pcie_host *);\n\tconst char * const *power_resets;\n\tconst char * const *cfg_resets;\n\tu8 num_power_resets;\n\tu8 num_cfg_resets;\n};\n\nstruct rzt2h_icu_priv {\n\tvoid *base_ns;\n\tvoid *base_s;\n\tstruct irq_fwspec fwspec[33];\n\traw_spinlock_t lock;\n};\n\nstruct rzt2h_pinctrl_data;\n\nstruct rzt2h_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc desc;\n\tstruct pinctrl_pin_desc *pins;\n\tconst struct rzt2h_pinctrl_data *data;\n\tvoid *base0;\n\tvoid *base1;\n\tstruct device *dev;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range gpio_range;\n\tlong unsigned int used_irqs[1];\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tbool safety_port_enabled;\n\tatomic_t wakeup_path;\n};\n\nstruct rzt2h_pinctrl_data {\n\tunsigned int n_port_pins;\n\tconst u8 *port_pin_configs;\n\tunsigned int n_ports;\n};\n\nstruct rzv2h_mod_clk;\n\nstruct rzv2h_reset;\n\nstruct rzv2h_cpg_info {\n\tconst struct cpg_core_clk *core_clks;\n\tunsigned int num_core_clks;\n\tunsigned int last_dt_core_clk;\n\tunsigned int num_total_core_clks;\n\tconst struct rzv2h_mod_clk *mod_clks;\n\tunsigned int num_mod_clks;\n\tunsigned int num_hw_mod_clks;\n\tconst struct rzv2h_reset *resets;\n\tunsigned int num_resets;\n\tunsigned int num_mstop_bits;\n};\n\nstruct rzv2h_cpg_pd {\n\tstruct rzv2h_cpg_priv *priv;\n\tstruct generic_pm_domain genpd;\n};\n\nstruct rzv2h_pll_pars {\n\tu16 m;\n\tu8 p;\n\tu8 s;\n\ts16 k;\n\tu64 freq_millihz;\n\ts64 error_millihz;\n};\n\nstruct rzv2h_pll_div_pars {\n\tstruct rzv2h_pll_pars pll;\n\tstruct {\n\t\tu8 divider_value;\n\t\tu64 freq_millihz;\n\t\ts64 error_millihz;\n\t} div;\n};\n\nstruct rzv2h_pll_dsi_info {\n\tconst struct rzv2h_pll_limits *pll_dsi_limits;\n\tstruct rzv2h_pll_div_pars pll_dsi_parameters;\n\tlong unsigned int req_pll_dsi_rate;\n};\n\nstruct rzv2h_cpg_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tspinlock_t rmw_lock;\n\tstruct clk **clks;\n\tunsigned int num_core_clks;\n\tunsigned int num_mod_clks;\n\tstruct rzv2h_reset *resets;\n\tunsigned int num_resets;\n\tunsigned int last_dt_core_clk;\n\tstruct clk_ops *ff_mod_status_ops;\n\tatomic_t *mstop_count;\n\tstruct reset_controller_dev rcdev;\n\tstruct rzv2h_pll_dsi_info pll_dsi_info[2];\n};\n\nstruct rzv2h_ff_mod_status_clk {\n\tstruct rzv2h_cpg_priv *priv;\n\tstruct fixed_mod_conf conf;\n\tstruct clk_fixed_factor fix;\n};\n\nstruct rzv2h_hw_info {\n\tconst u8 *tssel_lut;\n\tu16 t_offs;\n\tu8 max_tssel;\n\tu8 field_width;\n};\n\nstruct rzv2h_irqc_reg_cache {\n\tu32 nitsr;\n\tu32 iitsr;\n\tu32 titsr[2];\n};\n\nstruct rzv2h_icu_priv {\n\tvoid *base;\n\tstruct irq_fwspec fwspec[49];\n\traw_spinlock_t lock;\n\tconst struct rzv2h_hw_info *info;\n\tstruct rzv2h_irqc_reg_cache cache;\n};\n\nstruct rzv2h_mod_clk {\n\tconst char *name;\n\tu32 mstop_data;\n\tu16 parent;\n\tbool critical;\n\tbool no_pm;\n\tu8 on_index;\n\tu8 on_bit;\n\ts8 mon_index;\n\tu8 mon_bit;\n\ts8 ext_clk_mux_index;\n};\n\nstruct rzv2h_of_data {\n\tu8 cks_min;\n\tu8 cks_max;\n\tu16 cks_div;\n\tu8 tops;\n\tu16 timeout_cycles;\n\tenum rzv2h_wdt_count_source count_source;\n\tbool wdtdcr;\n};\n\nstruct rzv2h_pll_limits {\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} fout;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} fvco;\n\tstruct {\n\t\tu16 min;\n\t\tu16 max;\n\t} m;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} p;\n\tstruct {\n\t\tu8 min;\n\t\tu8 max;\n\t} s;\n\tstruct {\n\t\ts16 min;\n\t\ts16 max;\n\t} k;\n};\n\nstruct rzv2h_plldsi_div_clk {\n\tconst struct clk_div_table *dtable;\n\tstruct rzv2h_cpg_priv *priv;\n\tstruct clk_hw hw;\n\tstruct ddiv ddiv;\n};\n\nstruct rzv2h_reset {\n\tu8 reset_index;\n\tu8 reset_bit;\n\tu8 mon_index;\n\tu8 mon_bit;\n};\n\nstruct rzv2h_wdt_priv {\n\tvoid *base;\n\tvoid *wdtdcr;\n\tstruct clk *pclk;\n\tstruct clk *oscclk;\n\tstruct reset_control *rstc;\n\tstruct watchdog_device wdev;\n\tconst struct rzv2h_of_data *of_data;\n};\n\nstruct rzv2m_dedicated_configs {\n\tconst char *name;\n\tu32 config;\n};\n\nstruct rzv2m_pinctrl_data;\n\nstruct rzv2m_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc desc;\n\tstruct pinctrl_pin_desc *pins;\n\tconst struct rzv2m_pinctrl_data *data;\n\tvoid *base;\n\tstruct device *dev;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range gpio_range;\n\tspinlock_t lock;\n\tstruct mutex mutex;\n};\n\nstruct rzv2m_pinctrl_data {\n\tconst char * const *port_pins;\n\tconst u32 *port_pin_configs;\n\tconst struct rzv2m_dedicated_configs *dedicated_pins;\n\tunsigned int n_port_pins;\n\tunsigned int n_dedicated_pins;\n};\n\nstruct rzv2m_pwc_priv {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct gpio_chip gp;\n\tlong unsigned int ch_en_bits[1];\n};\n\nstruct rzv2m_usb3drd {\n\tvoid *reg;\n\tint drd_irq;\n\tstruct device *dev;\n\tstruct reset_control *drd_rstc;\n};\n\nstruct s1_walk_info;\n\nstruct s1_walk_context {\n\tstruct s1_walk_info *wi;\n\tu64 table_ipa;\n\tint level;\n};\n\nstruct s1_walk_filter {\n\tint (*fn)(struct s1_walk_context *, void *);\n\tvoid *priv;\n};\n\nstruct s1_walk_info {\n\tstruct s1_walk_filter *filter;\n\tu64 baddr;\n\tenum trans_regime regime;\n\tunsigned int max_oa_bits;\n\tunsigned int pgshift;\n\tunsigned int txsz;\n\tint sl;\n\tu8 sh;\n\tbool as_el0;\n\tbool hpd;\n\tbool e0poe;\n\tbool poe;\n\tbool pan;\n\tbool be;\n\tbool s2;\n\tbool pa52bit;\n\tbool ha;\n};\n\nstruct s1_walk_result {\n\tunion {\n\t\tstruct {\n\t\t\tu64 desc;\n\t\t\tu64 pa;\n\t\t\ts8 level;\n\t\t\tu8 APTable;\n\t\t\tbool nG;\n\t\t\tu16 asid;\n\t\t\tbool UXNTable;\n\t\t\tbool PXNTable;\n\t\t\tbool uwxn;\n\t\t\tbool uov;\n\t\t\tbool ur;\n\t\t\tbool uw;\n\t\t\tbool ux;\n\t\t\tbool pwxn;\n\t\t\tbool pov;\n\t\t\tbool pr;\n\t\t\tbool pw;\n\t\t\tbool px;\n\t\t};\n\t\tstruct {\n\t\t\tu8 fst;\n\t\t\tbool ptw;\n\t\t\tbool s2;\n\t\t};\n\t};\n\tbool failed;\n};\n\nstruct s1e2_tlbi_scope {\n\tenum {\n\t\tTLBI_ALL = 0,\n\t\tTLBI_VA = 1,\n\t\tTLBI_VAA = 2,\n\t\tTLBI_ASID = 3,\n\t} type;\n\tu16 asid;\n\tu64 va;\n\tu64 size;\n};\n\nstruct s2_walk_info {\n\tu64 baddr;\n\tunsigned int max_oa_bits;\n\tunsigned int pgshift;\n\tunsigned int sl;\n\tunsigned int t0sz;\n\tbool be;\n\tbool ha;\n};\n\nstruct s2mpg10_regulator_desc {\n\tstruct regulator_desc desc;\n\tunsigned int enable_ramp_rate;\n\tunsigned int pctrlsel_reg;\n\tunsigned int pctrlsel_mask;\n\tunsigned int pctrlsel_val;\n};\n\nstruct sec_pmic_dev;\n\nstruct s2mps11_clk {\n\tstruct sec_pmic_dev *iodev;\n\tstruct device_node *clk_np;\n\tstruct clk_hw hw;\n\tstruct clk *clk;\n\tstruct clk_lookup *lookup;\n\tu32 mask;\n\tunsigned int reg;\n};\n\nstruct s2mps11_info {\n\tint ramp_delay2;\n\tint ramp_delay34;\n\tint ramp_delay5;\n\tint ramp_delay16;\n\tint ramp_delay7810;\n\tint ramp_delay9;\n\tenum sec_device_type dev_type;\n\tlong unsigned int suspend_state[1];\n};\n\nstruct s3_save {\n\tu32 command;\n\tu32 dev_nt;\n\tu64 dcbaa_ptr;\n\tu32 config_reg;\n};\n\nstruct s3c2410_platform_i2c {\n\tint bus_num;\n\tunsigned int flags;\n\tunsigned int slave_addr;\n\tlong unsigned int frequency;\n\tunsigned int sda_delay;\n\tvoid (*cfg_gpio)(struct platform_device *);\n};\n\nstruct s3c2410_uartcfg {\n\tunsigned char hwport;\n\tunsigned char unused;\n\tshort unsigned int flags;\n\tupf_t uart_flags;\n\tunsigned int clk_sel;\n\tunsigned int has_fracval;\n\tlong unsigned int ucon;\n\tlong unsigned int ulcon;\n\tlong unsigned int ufcon;\n};\n\nstruct s3c2410_wdt_variant;\n\nstruct s3c2410_wdt {\n\tstruct device *dev;\n\tstruct clk *bus_clk;\n\tstruct clk *src_clk;\n\tvoid *reg_base;\n\tunsigned int count;\n\tspinlock_t lock;\n\tlong unsigned int wtcon_save;\n\tlong unsigned int wtdat_save;\n\tstruct watchdog_device wdt_device;\n\tstruct notifier_block freq_transition;\n\tconst struct s3c2410_wdt_variant *drv_data;\n\tstruct regmap *pmureg;\n\tu32 max_cnt;\n};\n\nstruct s3c2410_wdt_variant {\n\tint disable_reg;\n\tint mask_reset_reg;\n\tbool mask_reset_inv;\n\tint mask_bit;\n\tint rst_stat_reg;\n\tint rst_stat_bit;\n\tint cnt_en_reg;\n\tint cnt_en_bit;\n\tu32 quirks;\n};\n\nstruct s3c24xx_i2c {\n\twait_queue_head_t wait;\n\tkernel_ulong_t quirks;\n\tstruct i2c_msg *msg;\n\tunsigned int msg_num;\n\tunsigned int msg_idx;\n\tunsigned int msg_ptr;\n\tunsigned int tx_setup;\n\tunsigned int irq;\n\tenum s3c24xx_i2c_state state;\n\tlong unsigned int clkrate;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct device *dev;\n\tstruct i2c_adapter adap;\n\tstruct s3c2410_platform_i2c *pdata;\n\tstruct gpio_desc *gpios[2];\n\tstruct pinctrl *pctrl;\n\tstruct regmap *sysreg;\n\tunsigned int sys_i2c_cfg;\n};\n\nstruct s3c24xx_uart_info {\n\tconst char *name;\n\tenum s3c24xx_port_type type;\n\tunsigned int port_type;\n\tunsigned int fifosize;\n\tu32 rx_fifomask;\n\tu32 rx_fifoshift;\n\tu32 rx_fifofull;\n\tu32 tx_fifomask;\n\tu32 tx_fifoshift;\n\tu32 tx_fifofull;\n\tu32 clksel_mask;\n\tu32 clksel_shift;\n\tu32 ucon_mask;\n\tu8 def_clk_sel;\n\tu8 num_clks;\n\tu8 iotype;\n\tbool has_divslot;\n};\n\nstruct s3c24xx_serial_drv_data {\n\tconst struct s3c24xx_uart_info info;\n\tconst struct s3c2410_uartcfg def_cfg;\n\tconst unsigned int fifosize[18];\n};\n\nstruct s3c24xx_uart_dma {\n\tunsigned int rx_chan_id;\n\tunsigned int tx_chan_id;\n\tstruct dma_slave_config rx_conf;\n\tstruct dma_slave_config tx_conf;\n\tstruct dma_chan *rx_chan;\n\tstruct dma_chan *tx_chan;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tchar *rx_buf;\n\tdma_addr_t tx_transfer_addr;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tstruct dma_async_tx_descriptor *tx_desc;\n\tstruct dma_async_tx_descriptor *rx_desc;\n\tint tx_bytes_requested;\n\tint rx_bytes_requested;\n};\n\nstruct s3c24xx_uart_port {\n\tunsigned char rx_enabled;\n\tunsigned char tx_enabled;\n\tunsigned int pm_level;\n\tlong unsigned int baudclk_rate;\n\tunsigned int min_dma_size;\n\tunsigned int rx_irq;\n\tunsigned int tx_irq;\n\tunsigned int tx_in_progress;\n\tunsigned int tx_mode;\n\tunsigned int rx_mode;\n\tconst struct s3c24xx_uart_info *info;\n\tstruct clk *clk;\n\tstruct clk *baudclk;\n\tstruct uart_port port;\n\tconst struct s3c24xx_serial_drv_data *drv_data;\n\tconst struct s3c2410_uartcfg *cfg;\n\tstruct s3c24xx_uart_dma *dma;\n};\n\nstruct s3c64xx_spi_csinfo {\n\tu8 fb_delay;\n};\n\nstruct s3c64xx_spi_dma_data {\n\tstruct dma_chan *ch;\n\tdma_cookie_t cookie;\n\tenum dma_transfer_direction direction;\n};\n\nstruct s3c64xx_spi_info;\n\nstruct s3c64xx_spi_port_config;\n\nstruct s3c64xx_spi_driver_data {\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct clk *src_clk;\n\tstruct clk *ioclk;\n\tstruct platform_device *pdev;\n\tstruct spi_controller *host;\n\tstruct s3c64xx_spi_info *cntrlr_info;\n\tspinlock_t lock;\n\tlong unsigned int sfr_start;\n\tstruct completion xfer_completion;\n\tunsigned int state;\n\tunsigned int cur_mode;\n\tunsigned int cur_bpw;\n\tunsigned int cur_speed;\n\tstruct s3c64xx_spi_dma_data rx_dma;\n\tstruct s3c64xx_spi_dma_data tx_dma;\n\tconst struct s3c64xx_spi_port_config *port_conf;\n\tunsigned int port_id;\n\tunsigned int fifo_depth;\n\tu32 rx_fifomask;\n\tu32 tx_fifomask;\n};\n\nstruct s3c64xx_spi_info {\n\tint src_clk_nr;\n\tint num_cs;\n\tbool no_cs;\n\tbool polling;\n\tint (*cfg_gpio)(void);\n};\n\nstruct s3c64xx_spi_port_config {\n\tint fifo_lvl_mask[12];\n\tint rx_lvl_offset;\n\tunsigned int fifo_depth;\n\tu32 rx_fifomask;\n\tu32 tx_fifomask;\n\tint tx_st_done;\n\tint quirks;\n\tint clk_div;\n\tbool high_speed;\n\tbool clk_from_cmu;\n\tbool clk_ioclk;\n\tbool has_loopback;\n\tbool use_32bit_io;\n};\n\nstruct s3c_rtc_data;\n\nstruct s3c_rtc {\n\tstruct device *dev;\n\tstruct rtc_device *rtc;\n\tvoid *base;\n\tstruct clk *rtc_clk;\n\tstruct clk *rtc_src_clk;\n\tbool alarm_enabled;\n\tconst struct s3c_rtc_data *data;\n\tint irq_alarm;\n\tspinlock_t alarm_lock;\n\tbool wake_en;\n};\n\nstruct s3c_rtc_data {\n\tbool needs_src_clk;\n\tvoid (*irq_handler)(struct s3c_rtc *, int);\n\tvoid (*enable)(struct s3c_rtc *);\n\tvoid (*disable)(struct s3c_rtc *);\n};\n\nstruct s5_hw_clk {\n\tstruct clk_hw hw;\n\tvoid *reg;\n};\n\nstruct s5_clk_data {\n\tvoid *base;\n\tstruct s5_hw_clk s5_hw[9];\n};\n\nstruct s5_pll_conf {\n\tlong unsigned int freq;\n\tu8 div;\n\tbool rot_ena;\n\tu8 rot_sel;\n\tu8 rot_dir;\n\tu8 pre_div;\n};\n\nstruct s5m_rtc_reg_config;\n\nstruct s5m_rtc_info {\n\tstruct device *dev;\n\tstruct sec_pmic_dev *s5m87xx;\n\tstruct regmap *regmap;\n\tstruct rtc_device *rtc_dev;\n\tint irq;\n\tenum sec_device_type device_type;\n\tint rtc_24hr_mode;\n\tconst struct s5m_rtc_reg_config *regs;\n};\n\nstruct s5m_rtc_reg_config {\n\tunsigned int regs_count;\n\tunsigned int time;\n\tunsigned int ctrl;\n\tunsigned int alarm0;\n\tunsigned int alarm1;\n\tunsigned int udr_update;\n\tunsigned int autoclear_udr_mask;\n\tunsigned int read_time_udr_mask;\n\tunsigned int write_time_udr_mask;\n\tunsigned int write_alarm_udr_mask;\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct samsung_pll_rate_table;\n\nstruct samsung_clk_pll {\n\tstruct clk_hw hw;\n\tvoid *lock_reg;\n\tvoid *con_reg;\n\tshort unsigned int enable_offs;\n\tshort unsigned int lock_offs;\n\tenum samsung_pll_type type;\n\tunsigned int rate_count;\n\tconst struct samsung_pll_rate_table *rate_table;\n};\n\nstruct samsung_clk_provider {\n\tvoid *reg_base;\n\tstruct device *dev;\n\tstruct regmap *sysreg;\n\tspinlock_t lock;\n\tbool auto_clock_gate;\n\tu32 gate_dbg_offset;\n\tu32 option_offset;\n\tu32 drcg_offset;\n\tu32 memclk_offset;\n\tstruct clk_hw_onecell_data clk_data;\n};\n\nstruct samsung_clk_reg_dump {\n\tu32 offset;\n\tu32 value;\n};\n\nstruct samsung_clock_alias {\n\tunsigned int id;\n\tconst char *dev_name;\n\tconst char *alias;\n};\n\nstruct samsung_clock_reg_cache {\n\tstruct list_head node;\n\tvoid *reg_base;\n\tstruct regmap *sysreg;\n\tstruct samsung_clk_reg_dump *rdump;\n\tunsigned int rd_num;\n\tconst struct samsung_clk_reg_dump *rsuspend;\n\tunsigned int rsuspend_num;\n};\n\nstruct samsung_pll_clock;\n\nstruct samsung_mux_clock;\n\nstruct samsung_div_clock;\n\nstruct samsung_gate_clock;\n\nstruct samsung_fixed_rate_clock;\n\nstruct samsung_fixed_factor_clock;\n\nstruct samsung_cpu_clock;\n\nstruct samsung_cmu_info {\n\tconst struct samsung_pll_clock *pll_clks;\n\tunsigned int nr_pll_clks;\n\tconst struct samsung_mux_clock *mux_clks;\n\tunsigned int nr_mux_clks;\n\tconst struct samsung_div_clock *div_clks;\n\tunsigned int nr_div_clks;\n\tconst struct samsung_gate_clock *gate_clks;\n\tunsigned int nr_gate_clks;\n\tconst struct samsung_fixed_rate_clock *fixed_clks;\n\tunsigned int nr_fixed_clks;\n\tconst struct samsung_fixed_factor_clock *fixed_factor_clks;\n\tunsigned int nr_fixed_factor_clks;\n\tunsigned int nr_clk_ids;\n\tconst struct samsung_cpu_clock *cpu_clks;\n\tunsigned int nr_cpu_clks;\n\tconst long unsigned int *clk_regs;\n\tunsigned int nr_clk_regs;\n\tconst struct samsung_clk_reg_dump *suspend_regs;\n\tunsigned int nr_suspend_regs;\n\tconst char *clk_name;\n\tconst long unsigned int *sysreg_clk_regs;\n\tunsigned int nr_sysreg_clk_regs;\n\tbool manual_plls;\n\tbool auto_clock_gate;\n\tu32 gate_dbg_offset;\n\tu32 option_offset;\n\tu32 drcg_offset;\n\tu32 memclk_offset;\n};\n\nstruct samsung_cpu_clock {\n\tunsigned int id;\n\tconst char *name;\n\tunsigned int parent_id;\n\tunsigned int alt_parent_id;\n\tlong unsigned int flags;\n\tint offset;\n\tenum exynos_cpuclk_layout reg_layout;\n\tconst struct exynos_cpuclk_cfg_data *cfg;\n};\n\nstruct samsung_div_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 div_flags;\n\tstruct clk_div_table *table;\n};\n\nstruct samsung_early_console_data {\n\tu32 txfull_mask;\n\tu32 rxfifo_mask;\n};\n\nstruct samsung_fixed_factor_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int mult;\n\tlong unsigned int div;\n\tlong unsigned int flags;\n};\n\nstruct samsung_fixed_rate_clock {\n\tunsigned int id;\n\tchar *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int fixed_rate;\n};\n\nstruct samsung_gate_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 bit_idx;\n\tu8 gate_flags;\n};\n\nstruct samsung_mux_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char * const *parent_names;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 shift;\n\tu8 width;\n\tu8 mux_flags;\n};\n\nstruct samsung_pin_bank_type;\n\nstruct samsung_pin_bank {\n\tconst struct samsung_pin_bank_type *type;\n\tvoid *pctl_base;\n\tu32 pctl_offset;\n\tu8 nr_pins;\n\tvoid *eint_base;\n\tu8 eint_func;\n\tenum eint_type eint_type;\n\tu32 eint_mask;\n\tu32 eint_offset;\n\tu32 eint_num;\n\tu32 eint_con_offset;\n\tu32 eint_mask_offset;\n\tu32 eint_pend_offset;\n\tu32 eint_fltcon_offset;\n\tconst char *name;\n\tu32 id;\n\tu32 pin_base;\n\tvoid *soc_priv;\n\tstruct fwnode_handle *fwnode;\n\tstruct samsung_pinctrl_drv_data *drvdata;\n\tstruct irq_domain *irq_domain;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range grange;\n\tstruct exynos_irq_chip *irq_chip;\n\traw_spinlock_t slock;\n\tu32 pm_save[7];\n};\n\nstruct samsung_pin_bank_data {\n\tconst struct samsung_pin_bank_type *type;\n\tu32 pctl_offset;\n\tu8 pctl_res_idx;\n\tu8 nr_pins;\n\tu8 eint_func;\n\tenum eint_type eint_type;\n\tu32 eint_mask;\n\tu32 eint_offset;\n\tu32 eint_num;\n\tu32 eint_con_offset;\n\tu32 eint_mask_offset;\n\tu32 eint_pend_offset;\n\tu32 eint_fltcon_offset;\n\tconst char *name;\n};\n\nstruct samsung_pin_bank_type {\n\tu8 fld_width[6];\n\tu8 reg_offset[6];\n};\n\nstruct samsung_retention_data;\n\nstruct samsung_pin_ctrl {\n\tconst struct samsung_pin_bank_data *pin_banks;\n\tunsigned int nr_banks;\n\tunsigned int nr_ext_resources;\n\tconst struct samsung_retention_data *retention_data;\n\tint (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);\n\tint (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);\n\tvoid (*pud_value_init)(struct samsung_pinctrl_drv_data *);\n\tvoid (*suspend)(struct samsung_pin_bank *);\n\tvoid (*resume)(struct samsung_pin_bank *);\n};\n\nstruct samsung_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tu8 num_pins;\n\tu8 func;\n};\n\nstruct samsung_pmx_func;\n\nstruct samsung_retention_ctrl;\n\nstruct samsung_pinctrl_drv_data {\n\tstruct list_head node;\n\tvoid *virt_base;\n\tstruct device *dev;\n\tint irq;\n\tstruct clk *pclk;\n\tstruct pinctrl_desc pctl;\n\tstruct pinctrl_dev *pctl_dev;\n\tconst struct samsung_pin_group *pin_groups;\n\tunsigned int nr_groups;\n\tconst struct samsung_pmx_func *pmx_functions;\n\tunsigned int nr_functions;\n\tstruct samsung_pin_bank *pin_banks;\n\tunsigned int nr_banks;\n\tunsigned int nr_pins;\n\tunsigned int pud_val[3];\n\tstruct samsung_retention_ctrl *retention_ctrl;\n\tvoid (*suspend)(struct samsung_pin_bank *);\n\tvoid (*resume)(struct samsung_pin_bank *);\n};\n\nstruct samsung_pinctrl_of_match_data {\n\tconst struct samsung_pin_ctrl *ctrl;\n\tunsigned int num_ctrl;\n};\n\nstruct samsung_pll_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tlong unsigned int flags;\n\tint con_offset;\n\tint lock_offset;\n\tenum samsung_pll_type type;\n\tconst struct samsung_pll_rate_table *rate_table;\n};\n\nstruct samsung_pll_rate_table {\n\tunsigned int rate;\n\tunsigned int pdiv;\n\tunsigned int mdiv;\n\tunsigned int sdiv;\n\tunsigned int kdiv;\n\tunsigned int afc;\n\tunsigned int mfr;\n\tunsigned int mrr;\n\tunsigned int vsel;\n};\n\nstruct samsung_pmx_func {\n\tconst char *name;\n\tconst char **groups;\n\tu8 num_groups;\n\tu32 val;\n};\n\nstruct samsung_pwm_channel {\n\tu32 period_ns;\n\tu32 duty_ns;\n\tu32 tin_ns;\n};\n\nstruct samsung_pwm_variant {\n\tu8 bits;\n\tu8 div_base;\n\tu8 tclk_mask;\n\tu8 output_mask;\n\tbool has_tint_cstat;\n};\n\nstruct samsung_pwm_chip {\n\tstruct samsung_pwm_variant variant;\n\tu8 inverter_mask;\n\tu8 disabled_mask;\n\tvoid *base;\n\tstruct clk *base_clk;\n\tstruct clk *tclk0;\n\tstruct clk *tclk1;\n\tstruct samsung_pwm_channel channel[5];\n};\n\nstruct samsung_retention_ctrl {\n\tconst u32 *regs;\n\tint nr_regs;\n\tu32 value;\n\tatomic_t *refcnt;\n\tvoid *priv;\n\tvoid (*enable)(struct samsung_pinctrl_drv_data *);\n\tvoid (*disable)(struct samsung_pinctrl_drv_data *);\n};\n\nstruct samsung_retention_data {\n\tconst u32 *regs;\n\tint nr_regs;\n\tu32 value;\n\tatomic_t *refcnt;\n\tstruct samsung_retention_ctrl * (*init)(struct samsung_pinctrl_drv_data *, const struct samsung_retention_data *);\n};\n\nstruct samsung_ufs_phy_pmu_isol {\n\tu32 offset;\n\tu32 mask;\n\tu32 en;\n};\n\nstruct samsung_ufs_phy_drvdata;\n\nstruct samsung_ufs_phy_cfg;\n\nstruct samsung_ufs_phy {\n\tstruct device *dev;\n\tvoid *reg_pma;\n\tstruct regmap *reg_pmu;\n\tstruct clk_bulk_data *clks;\n\tconst struct samsung_ufs_phy_drvdata *drvdata;\n\tconst struct samsung_ufs_phy_cfg * const *cfgs;\n\tconst struct samsung_ufs_phy_cfg * const *cfgs_hibern8;\n\tstruct samsung_ufs_phy_pmu_isol isol;\n\tu8 lane_cnt;\n\tint ufs_phy_state;\n\tenum phy_mode mode;\n};\n\nstruct samsung_ufs_phy_cfg {\n\tu32 off_0;\n\tu32 off_1;\n\tu32 val;\n\tu8 desc;\n\tu8 id;\n};\n\nstruct samsung_ufs_phy_drvdata {\n\tconst struct samsung_ufs_phy_cfg **cfgs;\n\tconst struct samsung_ufs_phy_cfg **cfgs_hibern8;\n\tstruct samsung_ufs_phy_pmu_isol isol;\n\tconst char * const *clk_list;\n\tint num_clks;\n\tu32 cdr_lock_status_offset;\n\tint (*wait_for_cal)(struct phy *, u8);\n\tint (*wait_for_cdr)(struct phy *, u8);\n};\n\nstruct samsung_usb2_phy_instance;\n\nstruct samsung_usb2_common_phy {\n\tint (*power_on)(struct samsung_usb2_phy_instance *);\n\tint (*power_off)(struct samsung_usb2_phy_instance *);\n\tunsigned int id;\n\tchar *label;\n};\n\nstruct samsung_usb2_phy_config {\n\tconst struct samsung_usb2_common_phy *phys;\n\tint (*rate_to_clk)(long unsigned int, u32 *);\n\tunsigned int num_phys;\n\tbool has_mode_switch;\n\tbool has_refclk_sel;\n};\n\nstruct samsung_usb2_phy_driver;\n\nstruct samsung_usb2_phy_instance {\n\tconst struct samsung_usb2_common_phy *cfg;\n\tstruct phy *phy;\n\tstruct samsung_usb2_phy_driver *drv;\n\tint int_cnt;\n\tint ext_cnt;\n};\n\nstruct samsung_usb2_phy_driver {\n\tconst struct samsung_usb2_phy_config *cfg;\n\tstruct clk *clk;\n\tstruct clk *ref_clk;\n\tstruct regulator *vbus;\n\tlong unsigned int ref_rate;\n\tu32 ref_reg_val;\n\tstruct device *dev;\n\tvoid *reg_phy;\n\tstruct regmap *reg_pmu;\n\tstruct regmap *reg_sys;\n\tspinlock_t lock;\n\tstruct samsung_usb2_phy_instance instances[0];\n};\n\nstruct sas_ata_task {\n\tstruct host_to_dev_fis fis;\n\tu8 atapi_packet[16];\n\tu8 dma_xfer: 1;\n\tu8 use_ncq: 1;\n\tu8 return_fis_on_success: 1;\n\tu8 device_control_reg_update: 1;\n\tbool force_phy;\n\tint force_phy_id;\n};\n\nstruct sas_domain_function_template {\n\tvoid (*lldd_port_formed)(struct asd_sas_phy *);\n\tvoid (*lldd_port_deformed)(struct asd_sas_phy *);\n\tint (*lldd_dev_found)(struct domain_device *);\n\tvoid (*lldd_dev_gone)(struct domain_device *);\n\tint (*lldd_execute_task)(struct sas_task *, gfp_t);\n\tint (*lldd_abort_task)(struct sas_task *);\n\tint (*lldd_abort_task_set)(struct domain_device *, u8 *);\n\tint (*lldd_clear_task_set)(struct domain_device *, u8 *);\n\tint (*lldd_I_T_nexus_reset)(struct domain_device *);\n\tint (*lldd_ata_check_ready)(struct domain_device *);\n\tvoid (*lldd_ata_set_dmamode)(struct domain_device *);\n\tint (*lldd_lu_reset)(struct domain_device *, u8 *);\n\tint (*lldd_query_task)(struct sas_task *);\n\tvoid (*lldd_tmf_exec_complete)(struct domain_device *);\n\tvoid (*lldd_tmf_aborted)(struct sas_task *);\n\tbool (*lldd_abort_timeout)(struct sas_task *, void *);\n\tint (*lldd_clear_nexus_port)(struct asd_sas_port *);\n\tint (*lldd_clear_nexus_ha)(struct sas_ha_struct *);\n\tint (*lldd_control_phy)(struct asd_sas_phy *, enum phy_func, void *);\n\tint (*lldd_write_gpio)(struct sas_ha_struct *, u8, u8, u8, u8 *);\n};\n\nstruct sas_rphy {\n\tstruct device dev;\n\tstruct sas_identify identify;\n\tstruct list_head list;\n\tstruct request_queue *q;\n\tu32 scsi_target_id;\n};\n\nstruct sas_end_device {\n\tstruct sas_rphy rphy;\n\tunsigned int ready_led_meaning: 1;\n\tunsigned int tlr_supported: 1;\n\tunsigned int tlr_enabled: 1;\n\tu16 I_T_nexus_loss_timeout;\n\tu16 initiator_response_timeout;\n};\n\nstruct sas_expander_device {\n\tint level;\n\tint next_port_id;\n\tchar vendor_id[9];\n\tchar product_id[17];\n\tchar product_rev[5];\n\tchar component_vendor_id[9];\n\tu16 component_id;\n\tu8 component_revision_id;\n\tstruct sas_rphy rphy;\n};\n\nstruct sas_function_template {\n\tint (*get_linkerrors)(struct sas_phy *);\n\tint (*get_enclosure_identifier)(struct sas_rphy *, u64 *);\n\tint (*get_bay_identifier)(struct sas_rphy *);\n\tint (*phy_reset)(struct sas_phy *, int);\n\tint (*phy_enable)(struct sas_phy *, int);\n\tint (*phy_setup)(struct sas_phy *);\n\tvoid (*phy_release)(struct sas_phy *);\n\tint (*set_phy_speed)(struct sas_phy *, struct sas_phy_linkrates *);\n\tvoid (*smp_handler)(struct bsg_job *, struct Scsi_Host *, struct sas_rphy *);\n};\n\nstruct sas_host_attrs {\n\tstruct list_head rphy_list;\n\tstruct mutex lock;\n\tstruct request_queue *q;\n\tu32 next_target_id;\n\tu32 next_expander_id;\n\tint next_port_id;\n};\n\nstruct sas_identify_frame {\n\tu8 frame_type: 4;\n\tu8 dev_type: 3;\n\tu8 _un0: 1;\n\tu8 _un1;\n\tunion {\n\t\tstruct {\n\t\t\tu8 _un20: 1;\n\t\t\tu8 smp_iport: 1;\n\t\t\tu8 stp_iport: 1;\n\t\t\tu8 ssp_iport: 1;\n\t\t\tu8 _un247: 4;\n\t\t};\n\t\tu8 initiator_bits;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu8 _un30: 1;\n\t\t\tu8 smp_tport: 1;\n\t\t\tu8 stp_tport: 1;\n\t\t\tu8 ssp_tport: 1;\n\t\t\tu8 _un347: 4;\n\t\t};\n\t\tu8 target_bits;\n\t};\n\tu8 _un4_11[8];\n\tu8 sas_addr[8];\n\tu8 phy_id;\n\tu8 _un21_27[7];\n\t__be32 crc;\n};\n\nstruct sas_internal {\n\tstruct scsi_transport_template t;\n\tstruct sas_function_template *f;\n\tstruct sas_domain_function_template *dft;\n\tstruct device_attribute private_host_attrs[0];\n\tstruct device_attribute private_phy_attrs[17];\n\tstruct device_attribute private_port_attrs[1];\n\tstruct device_attribute private_rphy_attrs[8];\n\tstruct device_attribute private_end_dev_attrs[5];\n\tstruct device_attribute private_expander_attrs[7];\n\tstruct transport_container phy_attr_cont;\n\tstruct transport_container port_attr_cont;\n\tstruct transport_container rphy_attr_cont;\n\tstruct transport_container end_dev_attr_cont;\n\tstruct transport_container expander_attr_cont;\n\tstruct device_attribute *host_attrs[1];\n\tstruct device_attribute *phy_attrs[18];\n\tstruct device_attribute *port_attrs[2];\n\tstruct device_attribute *rphy_attrs[9];\n\tstruct device_attribute *end_dev_attrs[6];\n\tstruct device_attribute *expander_attrs[8];\n};\n\nstruct sas_internal_abort_task {\n\tenum sas_internal_abort type;\n\tunsigned int qid;\n\tu16 tag;\n};\n\nstruct sas_phy {\n\tstruct device dev;\n\tint number;\n\tint enabled;\n\tstruct sas_identify identify;\n\tenum sas_linkrate negotiated_linkrate;\n\tenum sas_linkrate minimum_linkrate_hw;\n\tenum sas_linkrate minimum_linkrate;\n\tenum sas_linkrate maximum_linkrate_hw;\n\tenum sas_linkrate maximum_linkrate;\n\tu32 invalid_dword_count;\n\tu32 running_disparity_error_count;\n\tu32 loss_of_dword_sync_count;\n\tu32 phy_reset_problem_count;\n\tstruct list_head port_siblings;\n\tvoid *hostdata;\n};\n\nstruct sas_phy_data {\n\tstruct sas_phy *phy;\n\tstruct mutex event_lock;\n\tint hard_reset;\n\tint reset_result;\n\tstruct sas_work reset_work;\n\tint enable;\n\tint enable_result;\n\tstruct sas_work enable_work;\n};\n\nstruct sas_phy_linkrates {\n\tenum sas_linkrate maximum_linkrate;\n\tenum sas_linkrate minimum_linkrate;\n};\n\nstruct sas_port {\n\tstruct device dev;\n\tint port_identifier;\n\tint num_phys;\n\tunsigned int is_backlink: 1;\n\tstruct sas_rphy *rphy;\n\tstruct mutex phy_list_mutex;\n\tstruct list_head phy_list;\n\tstruct list_head del_list;\n};\n\nstruct sas_smp_task {\n\tstruct scatterlist smp_req;\n\tstruct scatterlist smp_resp;\n};\n\nstruct sas_ssp_task {\n\tu8 LUN[8];\n\tenum task_attribute task_attr;\n\tstruct scsi_cmnd *cmd;\n};\n\nstruct task_status_struct {\n\tenum service_response resp;\n\tenum exec_status stat;\n\tint buf_valid_size;\n\tu8 buf[96];\n\tu32 residual;\n\tenum sas_open_rej_reason open_rej_reason;\n};\n\nstruct sas_task_slow;\n\nstruct sas_task {\n\tstruct domain_device *dev;\n\tspinlock_t task_state_lock;\n\tunsigned int task_state_flags;\n\tenum sas_protocol task_proto;\n\tunion {\n\t\tstruct sas_ata_task ata_task;\n\t\tstruct sas_smp_task smp_task;\n\t\tstruct sas_ssp_task ssp_task;\n\t\tstruct sas_internal_abort_task abort_task;\n\t};\n\tstruct scatterlist *scatter;\n\tint num_scatter;\n\tu32 total_xfer_len;\n\tu8 data_dir: 2;\n\tstruct task_status_struct task_status;\n\tvoid (*task_done)(struct sas_task *);\n\tvoid *lldd_task;\n\tvoid *uldd_task;\n\tstruct sas_task_slow *slow_task;\n\tstruct sas_tmf_task *tmf;\n};\n\nstruct sas_task_slow {\n\tstruct timer_list timer;\n\tstruct completion completion;\n\tstruct sas_task *task;\n};\n\nstruct sas_tmf_task {\n\tu8 tmf;\n\tu16 tag_of_task_to_be_managed;\n};\n\nstruct sata_rcar_priv {\n\tvoid *base;\n\tu32 sataint_mask;\n\tenum sata_rcar_type type;\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar saved_cmdlines[0];\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbsa_gwdt {\n\tstruct watchdog_device wdd;\n\tu32 clk;\n\tint version;\n\tbool need_ws0_race_workaround;\n\tvoid *refresh_base;\n\tvoid *control_base;\n};\n\nstruct scale_freq_data {\n\tenum scale_freq_source source;\n\tvoid (*set_freq_scale)(void);\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_info {\n\tlong unsigned int pcount;\n\tlong long unsigned int run_delay;\n\tlong long unsigned int max_run_delay;\n\tlong long unsigned int min_run_delay;\n\tlong long unsigned int last_arrival;\n\tlong long unsigned int last_queued;\n\tstruct timespec64 max_run_delay_ts;\n};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_poll {\n\t__guest_handle_evtchn_port_t ports;\n\tunsigned int nr_ports;\n\tuint64_t timeout;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct sched_shutdown {\n\tunsigned int reason;\n};\n\nstruct sched_statistics {};\n\nstruct sci_clk_provider;\n\nstruct sci_clk {\n\tstruct clk_hw hw;\n\tu16 dev_id;\n\tu32 clk_id;\n\tu32 num_parents;\n\tstruct sci_clk_provider *provider;\n\tu8 flags;\n\tstruct list_head node;\n\tlong unsigned int cached_req;\n\tlong unsigned int cached_res;\n};\n\nstruct ti_sci_clk_ops;\n\nstruct sci_clk_provider {\n\tconst struct ti_sci_handle *sci;\n\tconst struct ti_sci_clk_ops *ops;\n\tstruct device *dev;\n\tstruct sci_clk **clocks;\n\tint num_clocks;\n};\n\nstruct sci_common_regs {\n\tunsigned int status;\n\tunsigned int control;\n};\n\nstruct sci_irq_desc {\n\tconst char *desc;\n\tirq_handler_t handler;\n};\n\nstruct sci_port_params;\n\nstruct sci_port_ops;\n\nstruct sci_of_data {\n\tconst struct sci_port_params *params;\n\tconst struct uart_ops *uart_ops;\n\tconst struct sci_port_ops *ops;\n\tshort unsigned int regtype;\n\tshort unsigned int type;\n};\n\nstruct sci_suspend_regs;\n\nstruct sci_port {\n\tstruct uart_port port;\n\tconst struct sci_port_params *params;\n\tconst struct plat_sci_port *cfg;\n\tunsigned int sampling_rate_mask;\n\tresource_size_t reg_size;\n\tstruct mctrl_gpios *gpios;\n\tstruct clk *clks[7];\n\tlong unsigned int clk_rates[7];\n\tint irqs[6];\n\tchar *irqstr[6];\n\tstruct dma_chan *chan_tx;\n\tstruct dma_chan *chan_rx;\n\tstruct reset_control *rstc;\n\tstruct sci_suspend_regs *suspend_regs;\n\tstruct dma_chan *chan_tx_saved;\n\tstruct dma_chan *chan_rx_saved;\n\tdma_cookie_t cookie_tx;\n\tdma_cookie_t cookie_rx[2];\n\tdma_cookie_t active_rx;\n\tdma_addr_t tx_dma_addr;\n\tunsigned int tx_dma_len;\n\tstruct scatterlist sg_rx[2];\n\tvoid *rx_buf[2];\n\tsize_t buf_len_rx;\n\tstruct work_struct work_tx;\n\tstruct hrtimer rx_timer;\n\tunsigned int rx_timeout;\n\tunsigned int rx_frame;\n\tint rx_trigger;\n\tstruct timer_list rx_fifo_timer;\n\tint rx_fifo_timeout;\n\tu16 hscif_tot;\n\tu8 type;\n\tu8 regtype;\n\tconst struct sci_port_ops *ops;\n\tbool has_rtscts;\n\tbool autorts;\n\tbool tx_occurred;\n};\n\nstruct sci_port_ops {\n\tu32 (*read_reg)(struct uart_port *, int);\n\tvoid (*write_reg)(struct uart_port *, int, int);\n\tvoid (*clear_SCxSR)(struct uart_port *, unsigned int);\n\tvoid (*transmit_chars)(struct uart_port *);\n\tvoid (*receive_chars)(struct uart_port *);\n\tvoid (*poll_put_char)(struct uart_port *, unsigned char);\n\tint (*set_rtrg)(struct uart_port *, int);\n\tint (*rtrg_enabled)(struct uart_port *);\n\tvoid (*shutdown_complete)(struct uart_port *);\n\tvoid (*prepare_console_write)(struct uart_port *, u32);\n\tvoid (*finish_console_write)(struct uart_port *, u32);\n\tvoid (*console_save)(struct uart_port *);\n\tvoid (*console_restore)(struct uart_port *);\n\tsize_t (*suspend_regs_size)(void);\n};\n\nstruct sci_port_params_bits;\n\nstruct sci_port_params {\n\tconst struct plat_sci_reg regs[20];\n\tconst struct sci_common_regs *common_regs;\n\tconst struct sci_port_params_bits *param_bits;\n\tunsigned int fifosize;\n\tunsigned int overrun_reg;\n\tunsigned int overrun_mask;\n\tunsigned int sampling_rate_mask;\n\tunsigned int error_mask;\n\tunsigned int error_clear;\n};\n\nstruct sci_port_params_bits {\n\tunsigned int rxtx_enable;\n\tunsigned int te_clear;\n\tunsigned int poll_sent_bits;\n};\n\nstruct sci_suspend_regs {\n\tu16 scdl;\n\tu16 sccks;\n\tu16 scsmr;\n\tu16 scscr;\n\tu16 scfcr;\n\tu16 scsptr;\n\tu16 hssrr;\n\tu16 scpcr;\n\tu16 scpdr;\n\tu8 scbrr;\n\tu8 semr;\n};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_legacy_command {\n\t__le32 len;\n\t__le32 buf_offset;\n\t__le32 resp_hdr_offset;\n\t__le32 id;\n\t__le32 buf[0];\n};\n\nstruct scm_legacy_response {\n\t__le32 len;\n\t__le32 buf_offset;\n\t__le32 is_complete;\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scmi_sensor_info;\n\nstruct scmi_apriv {\n\tbool any_axes_support_extended_names;\n\tstruct scmi_sensor_info *s;\n};\n\nstruct scmi_msg_resp_attrs {\n\t__le32 min_range_low;\n\t__le32 min_range_high;\n\t__le32 max_range_low;\n\t__le32 max_range_high;\n};\n\nstruct scmi_axis_descriptor {\n\t__le32 id;\n\t__le32 attributes_low;\n\t__le32 attributes_high;\n\tu8 name[16];\n\t__le32 resolution;\n\tstruct scmi_msg_resp_attrs attrs;\n};\n\nstruct scmi_base_error_notify_payld {\n\t__le32 agent_id;\n\t__le32 error_status;\n\t__le64 msg_reports[1024];\n};\n\nstruct scmi_base_error_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tbool fatal;\n\tunsigned int cmd_count;\n\tlong long unsigned int reports[0];\n};\n\nstruct scmi_handle;\n\nstruct scmi_chan_info {\n\tint id;\n\tstruct device *dev;\n\tbool is_p2a;\n\tunsigned int rx_timeout_ms;\n\tunsigned int max_msg_size;\n\tstruct scmi_handle *handle;\n\tbool no_completion_irq;\n\tvoid *transport_info;\n};\n\nstruct scmi_clk {\n\tu32 id;\n\tstruct device *dev;\n\tstruct clk_hw hw;\n\tconst struct scmi_clock_info *info;\n\tconst struct scmi_protocol_handle *ph;\n\tstruct clk_parent_data *parent_data;\n};\n\nstruct scmi_clk_ipriv {\n\tstruct device *dev;\n\tu32 clk_id;\n\tstruct scmi_clock_info *clk;\n};\n\nstruct scmi_clk_proto_ops {\n\tint (*count_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_clock_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*rate_get)(const struct scmi_protocol_handle *, u32, u64 *);\n\tint (*rate_set)(const struct scmi_protocol_handle *, u32, u64);\n\tint (*enable)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*disable)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*state_get)(const struct scmi_protocol_handle *, u32, bool *, bool);\n\tint (*config_oem_get)(const struct scmi_protocol_handle *, u32, enum scmi_clock_oem_config, u32 *, u32 *, bool);\n\tint (*config_oem_set)(const struct scmi_protocol_handle *, u32, enum scmi_clock_oem_config, u32, bool);\n\tint (*parent_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*parent_set)(const struct scmi_protocol_handle *, u32, u32);\n};\n\nstruct scmi_clock_info {\n\tchar name[64];\n\tunsigned int enable_latency;\n\tbool rate_discrete;\n\tbool rate_changed_notifications;\n\tbool rate_change_requested_notifications;\n\tbool state_ctrl_forbidden;\n\tbool rate_ctrl_forbidden;\n\tbool parent_ctrl_forbidden;\n\tbool extended_config;\n\tunion {\n\t\tstruct {\n\t\t\tint num_rates;\n\t\t\tu64 rates[16];\n\t\t} list;\n\t\tstruct {\n\t\t\tu64 min_rate;\n\t\t\tu64 max_rate;\n\t\t\tu64 step_size;\n\t\t} range;\n\t};\n\tint num_parents;\n\tu32 *parents;\n};\n\nstruct scmi_clock_rate_notif_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int clock_id;\n\tlong long unsigned int rate;\n};\n\nstruct scmi_clock_rate_notify_payld {\n\t__le32 agent_id;\n\t__le32 clock_id;\n\t__le32 rate_low;\n\t__le32 rate_high;\n};\n\nstruct scmi_clock_set_rate {\n\t__le32 flags;\n\t__le32 id;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_data {\n\tint domain_id;\n\tint nr_opp;\n\tstruct device *cpu_dev;\n\tcpumask_var_t opp_shared_cpus;\n\tstruct notifier_block limit_notify_nb;\n\tstruct freq_qos_request limits_freq_req;\n};\n\nstruct scmi_debug_info {\n\tstruct dentry *top_dentry;\n\tconst char *name;\n\tconst char *type;\n\tbool is_atomic;\n\tatomic_t counters[15];\n};\n\nstruct scmi_transport_ops;\n\nstruct scmi_desc {\n\tconst struct scmi_transport_ops *ops;\n\tint max_rx_timeout_ms;\n\tint max_msg;\n\tint max_msg_size;\n\tunsigned int atomic_threshold;\n\tconst bool force_polling;\n\tconst bool sync_cmds_completed_on_ret;\n\tconst bool atomic_enabled;\n};\n\nstruct scmi_device {\n\tu32 id;\n\tu8 protocol_id;\n\tconst char *name;\n\tstruct device dev;\n\tstruct scmi_handle *handle;\n};\n\nstruct scmi_device_id {\n\tu8 protocol_id;\n\tconst char *name;\n};\n\nstruct scmi_driver {\n\tconst char *name;\n\tint (*probe)(struct scmi_device *);\n\tvoid (*remove)(struct scmi_device *);\n\tconst struct scmi_device_id *id_table;\n\tstruct device_driver driver;\n};\n\nstruct scmi_event {\n\tu8 id;\n\tsize_t max_payld_sz;\n\tsize_t max_report_sz;\n};\n\nstruct scmi_registered_event;\n\nstruct scmi_event_handler {\n\tu32 key;\n\trefcount_t users;\n\tstruct scmi_registered_event *r_evt;\n\tstruct blocking_notifier_head chain;\n\tstruct hlist_node hash;\n\tbool enabled;\n};\n\nstruct scmi_event_header {\n\tktime_t timestamp;\n\tsize_t payld_sz;\n\tunsigned char evt_id;\n\tunsigned char payld[0];\n};\n\nstruct scmi_event_ops {\n\tbool (*is_notify_supported)(const struct scmi_protocol_handle *, u8, u32);\n\tint (*get_num_sources)(const struct scmi_protocol_handle *);\n\tint (*set_notify_enabled)(const struct scmi_protocol_handle *, u8, u32, bool);\n\tvoid * (*fill_custom_report)(const struct scmi_protocol_handle *, u8, ktime_t, const void *, size_t, void *, u32 *);\n};\n\nstruct scmi_fc_db_info {\n\tint width;\n\tu64 set;\n\tu64 mask;\n\tvoid *addr;\n};\n\nstruct scmi_fc_info {\n\tvoid *set_addr;\n\tvoid *get_addr;\n\tstruct scmi_fc_db_info *set_db;\n\tu32 rate_limit;\n};\n\nstruct scmi_function_info {\n\tchar name[64];\n\tbool present;\n\tu32 *groups;\n\tu32 nr_groups;\n};\n\nstruct scmi_group_info {\n\tchar name[64];\n\tbool present;\n\tu32 *group_pins;\n\tu32 nr_pins;\n};\n\nstruct scmi_revision_info;\n\nstruct scmi_notify_ops;\n\nstruct scmi_handle {\n\tstruct device *dev;\n\tstruct scmi_revision_info *version;\n\tint (*devm_protocol_acquire)(struct scmi_device *, u8);\n\tconst void * (*devm_protocol_get)(struct scmi_device *, u8, struct scmi_protocol_handle **);\n\tvoid (*devm_protocol_put)(struct scmi_device *, u8);\n\tbool (*is_transport_atomic)(const struct scmi_handle *, unsigned int *);\n\tconst struct scmi_notify_ops *notify_ops;\n};\n\nstruct scmi_imx_bbm_proto_ops;\n\nstruct scmi_imx_bbm {\n\tstruct scmi_protocol_handle *ph;\n\tconst struct scmi_imx_bbm_proto_ops *ops;\n\tstruct notifier_block nb;\n\tint keycode;\n\tint keystate;\n\tbool suspended;\n\tstruct delayed_work check_work;\n\tstruct input_dev *input;\n};\n\nstruct scmi_imx_bbm___2 {\n\tconst struct scmi_imx_bbm_proto_ops *ops;\n\tstruct rtc_device *rtc_dev;\n\tstruct scmi_protocol_handle *ph;\n\tstruct notifier_block nb;\n};\n\nstruct scmi_imx_bbm_alarm_time {\n\t__le32 id;\n\t__le32 flags;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_imx_bbm_get_time {\n\t__le32 id;\n\t__le32 flags;\n};\n\nstruct scmi_imx_bbm_info {\n\tint nr_rtc;\n\tint nr_gpr;\n};\n\nstruct scmi_imx_bbm_notif_report {\n\tbool is_rtc;\n\tbool is_button;\n\tktime_t timestamp;\n\tunsigned int rtc_id;\n\tunsigned int rtc_evt;\n};\n\nstruct scmi_imx_bbm_notify_payld {\n\t__le32 flags;\n};\n\nstruct scmi_imx_bbm_proto_ops {\n\tint (*rtc_time_set)(const struct scmi_protocol_handle *, u32, uint64_t);\n\tint (*rtc_time_get)(const struct scmi_protocol_handle *, u32, u64 *);\n\tint (*rtc_alarm_set)(const struct scmi_protocol_handle *, u32, bool, u64);\n\tint (*button_get)(const struct scmi_protocol_handle *, u32 *);\n};\n\nstruct scmi_imx_bbm_set_time {\n\t__le32 id;\n\t__le32 flags;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_imx_cpu_info {\n\tu32 nr_cpu;\n};\n\nstruct scmi_imx_cpu_info_get_out {\n\t__le32 runmode;\n\t__le32 sleepmode;\n\t__le32 resetvectorlow;\n\t__le32 resetvectorhigh;\n};\n\nstruct scmi_imx_cpu_proto_ops {\n\tint (*cpu_reset_vector_set)(const struct scmi_protocol_handle *, u32, u64, bool, bool, bool);\n\tint (*cpu_start)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*cpu_started)(const struct scmi_protocol_handle *, u32, bool *);\n};\n\nstruct scmi_imx_cpu_reset_vector_set_in {\n\t__le32 cpuid;\n\t__le32 flags;\n\t__le32 resetvectorlow;\n\t__le32 resetvectorhigh;\n};\n\nstruct scmi_imx_lmm_info {\n\tu32 lmid;\n\tenum scmi_imx_lmm_state state;\n\tu32 errstatus;\n\tu8 name[16];\n};\n\nstruct scmi_imx_lmm_priv {\n\tu32 nr_lmm;\n};\n\nstruct scmi_imx_lmm_proto_ops {\n\tint (*lmm_power_boot)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*lmm_info)(const struct scmi_protocol_handle *, u32, struct scmi_imx_lmm_info *);\n\tint (*lmm_reset_vector_set)(const struct scmi_protocol_handle *, u32, u32, u32, u64);\n\tint (*lmm_shutdown)(const struct scmi_protocol_handle *, u32, u32);\n};\n\nstruct scmi_imx_lmm_reset_vector_set_in {\n\t__le32 lmid;\n\t__le32 cpuid;\n\t__le32 flags;\n\t__le32 resetvectorlow;\n\t__le32 resetvectorhigh;\n};\n\nstruct scmi_imx_lmm_shutdown_in {\n\t__le32 lmid;\n\t__le32 flags;\n};\n\nstruct scmi_imx_misc_board_info_out {\n\t__le32 attributes;\n\tu8 brdname[16];\n};\n\nstruct scmi_imx_misc_buildinfo_out {\n\t__le32 buildnum;\n\t__le32 buildcommit;\n\tu8 builddate[16];\n\tu8 buildtime[16];\n};\n\nstruct scmi_imx_misc_cfg_info_out {\n\t__le32 msel;\n\tu8 cfgname[16];\n};\n\nstruct scmi_imx_misc_ctrl_get_out {\n\t__le32 num;\n\t__le32 val[0];\n};\n\nstruct scmi_imx_misc_ctrl_notify_in {\n\t__le32 ctrl_id;\n\t__le32 flags;\n};\n\nstruct scmi_imx_misc_ctrl_notify_payld {\n\t__le32 ctrl_id;\n\t__le32 flags;\n};\n\nstruct scmi_imx_misc_ctrl_notify_report {\n\tktime_t timestamp;\n\tunsigned int ctrl_id;\n\tunsigned int flags;\n};\n\nstruct scmi_imx_misc_ctrl_set_in {\n\t__le32 id;\n\t__le32 num;\n\t__le32 value[0];\n};\n\nstruct scmi_imx_misc_info {\n\tu32 nr_dev_ctrl;\n\tu32 nr_brd_ctrl;\n\tu32 nr_reason;\n};\n\nstruct scmi_imx_misc_proto_ops {\n\tint (*misc_ctrl_set)(const struct scmi_protocol_handle *, u32, u32, u32 *);\n\tint (*misc_ctrl_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n\tint (*misc_ctrl_req_notify)(const struct scmi_protocol_handle *, u32, u32, u32);\n\tint (*misc_syslog)(const struct scmi_protocol_handle *, u16 *, void *);\n};\n\nstruct scmi_imx_misc_syslog_in {\n\t__le32 flags;\n\t__le32 index;\n};\n\nstruct scmi_imx_misc_syslog_ipriv {\n\tu32 *array;\n\tu16 *size;\n};\n\nstruct scmi_imx_misc_syslog_out {\n\t__le32 numlogflags;\n\t__le32 syslog[0];\n};\n\nstruct scmi_revision_info {\n\tu16 major_ver;\n\tu16 minor_ver;\n\tu8 num_protocols;\n\tu8 num_agents;\n\tu32 impl_ver;\n\tchar vendor_id[16];\n\tchar sub_vendor_id[16];\n};\n\nstruct scmi_xfers_info {\n\tlong unsigned int *xfer_alloc_table;\n\tspinlock_t xfer_lock;\n\tint max_msg;\n\tstruct hlist_head free_xfers;\n\tstruct hlist_head pending_xfers[512];\n};\n\nstruct scmi_info {\n\tint id;\n\tstruct device *dev;\n\tconst struct scmi_desc *desc;\n\tstruct scmi_revision_info version;\n\tstruct scmi_handle handle;\n\tstruct scmi_xfers_info tx_minfo;\n\tstruct scmi_xfers_info rx_minfo;\n\tstruct idr tx_idr;\n\tstruct idr rx_idr;\n\tstruct idr protocols;\n\tstruct mutex protocols_mtx;\n\tu8 *protocols_imp;\n\tstruct idr active_protocols;\n\tvoid *notify_priv;\n\tstruct list_head node;\n\tint users;\n\tstruct notifier_block bus_nb;\n\tstruct notifier_block dev_req_nb;\n\tstruct mutex devreq_mtx;\n\tstruct scmi_debug_info *dbg;\n\tvoid *raw;\n};\n\nstruct scmi_iterator_state {\n\tunsigned int desc_index;\n\tunsigned int num_returned;\n\tunsigned int num_remaining;\n\tunsigned int max_resources;\n\tunsigned int loop_idx;\n\tsize_t rx_len;\n\tvoid *priv;\n};\n\nstruct scmi_xfer;\n\nstruct scmi_iterator_ops;\n\nstruct scmi_iterator {\n\tvoid *msg;\n\tvoid *resp;\n\tstruct scmi_xfer *t;\n\tconst struct scmi_protocol_handle *ph;\n\tstruct scmi_iterator_ops *ops;\n\tstruct scmi_iterator_state state;\n\tvoid *priv;\n};\n\nstruct scmi_iterator_ops {\n\tvoid (*prepare_message)(void *, unsigned int, const void *);\n\tint (*update_state)(struct scmi_iterator_state *, const void *, void *);\n\tint (*process_response)(const struct scmi_protocol_handle *, const void *, struct scmi_iterator_state *, void *);\n};\n\nstruct scmi_shared_mem;\n\nstruct scmi_shmem_io_ops;\n\nstruct scmi_mailbox {\n\tstruct mbox_client cl;\n\tstruct mbox_chan *chan;\n\tstruct mbox_chan *chan_receiver;\n\tstruct mbox_chan *chan_platform_receiver;\n\tstruct scmi_chan_info *cinfo;\n\tstruct scmi_shared_mem *shmem;\n\tstruct mutex chan_lock;\n\tstruct scmi_shmem_io_ops *io_ops;\n};\n\nstruct scmi_msg_payld;\n\nstruct scmi_message_operations {\n\tsize_t (*response_size)(struct scmi_xfer *);\n\tsize_t (*command_size)(struct scmi_xfer *);\n\tvoid (*tx_prepare)(struct scmi_msg_payld *, struct scmi_xfer *);\n\tu32 (*read_header)(struct scmi_msg_payld *);\n\tvoid (*fetch_response)(struct scmi_msg_payld *, size_t, struct scmi_xfer *);\n\tvoid (*fetch_notification)(struct scmi_msg_payld *, size_t, size_t, struct scmi_xfer *);\n};\n\nstruct scmi_msg {\n\tvoid *buf;\n\tsize_t len;\n};\n\nstruct scmi_msg_base_error_notify {\n\t__le32 event_control;\n};\n\nstruct scmi_msg_clock_config_get {\n\t__le32 id;\n\t__le32 flags;\n};\n\nstruct scmi_msg_clock_config_set {\n\t__le32 id;\n\t__le32 attributes;\n};\n\nstruct scmi_msg_clock_config_set_v2 {\n\t__le32 id;\n\t__le32 attributes;\n\t__le32 oem_config_val;\n};\n\nstruct scmi_msg_clock_describe_rates {\n\t__le32 id;\n\t__le32 rate_index;\n};\n\nstruct scmi_msg_clock_possible_parents {\n\t__le32 id;\n\t__le32 skip_parents;\n};\n\nstruct scmi_msg_clock_rate_notify {\n\t__le32 clk_id;\n\t__le32 notify_enable;\n};\n\nstruct scmi_msg_clock_set_parent {\n\t__le32 id;\n\t__le32 parent_id;\n};\n\nstruct scmi_msg_cmd_config_set {\n\t__le32 domain_id;\n\t__le32 config;\n};\n\nstruct scmi_msg_cmd_describe_levels {\n\t__le32 domain_id;\n\t__le32 level_index;\n};\n\nstruct scmi_msg_cmd_level_set {\n\t__le32 domain_id;\n\t__le32 flags;\n\t__le32 voltage_level;\n};\n\nstruct scmi_msg_get_fc_info {\n\t__le32 domain;\n\t__le32 message_id;\n};\n\nstruct scmi_msg_hdr {\n\tu8 id;\n\tu8 protocol_id;\n\tu8 type;\n\tu16 seq;\n\tu32 status;\n\tbool poll_completion;\n};\n\nstruct scmi_msg_imx_bbm_button_notify {\n\t__le32 flags;\n};\n\nstruct scmi_msg_imx_bbm_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_imx_bbm_rtc_notify {\n\t__le32 rtc_id;\n\t__le32 flags;\n};\n\nstruct scmi_msg_imx_cpu_attributes_out {\n\t__le32 attributes;\n\tu8 name[16];\n};\n\nstruct scmi_msg_imx_cpu_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_imx_lmm_attributes_out {\n\t__le32 lmid;\n\t__le32 attributes;\n\t__le32 state;\n\t__le32 errstatus;\n\tu8 name[16];\n};\n\nstruct scmi_msg_imx_lmm_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_imx_misc_protocol_attributes {\n\t__le32 attributes;\n};\n\nstruct scmi_msg_payld {\n\t__le32 msg_header;\n\t__le32 msg_payload[0];\n};\n\nstruct scmi_msg_perf_describe_levels {\n\t__le32 domain;\n\t__le32 level_index;\n};\n\nstruct scmi_msg_pinctrl_attributes {\n\t__le32 identifier;\n\t__le32 flags;\n};\n\nstruct scmi_msg_pinctrl_list_assoc {\n\t__le32 identifier;\n\t__le32 flags;\n\t__le32 index;\n};\n\nstruct scmi_msg_pinctrl_protocol_attributes {\n\t__le32 attributes_low;\n\t__le32 attributes_high;\n};\n\nstruct scmi_msg_powercap_notify_cap {\n\t__le32 domain;\n\t__le32 notify_enable;\n};\n\nstruct scmi_msg_powercap_notify_thresh {\n\t__le32 domain;\n\t__le32 notify_enable;\n\t__le32 power_thresh_low;\n\t__le32 power_thresh_high;\n};\n\nstruct scmi_msg_powercap_set_cap_or_pai {\n\t__le32 domain;\n\t__le32 flags;\n\t__le32 value;\n};\n\nstruct scmi_msg_request {\n\t__le32 identifier;\n\t__le32 flags;\n};\n\nstruct scmi_msg_reset_domain_reset {\n\t__le32 domain_id;\n\t__le32 flags;\n\t__le32 reset_state;\n};\n\nstruct scmi_msg_reset_notify {\n\t__le32 id;\n\t__le32 event_control;\n};\n\nstruct scmi_msg_resp_base_attributes {\n\tu8 num_protocols;\n\tu8 num_agents;\n\t__le16 reserved;\n};\n\nstruct scmi_msg_resp_base_discover_agent {\n\t__le32 agent_id;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_clock_attributes {\n\t__le32 attributes;\n\tu8 name[16];\n\t__le32 clock_enable_latency;\n};\n\nstruct scmi_msg_resp_clock_config_get {\n\t__le32 attributes;\n\t__le32 config;\n\t__le32 oem_config_val;\n};\n\nstruct scmi_msg_resp_clock_describe_rates {\n\t__le32 num_rates_flags;\n\tstruct {\n\t\t__le32 value_low;\n\t\t__le32 value_high;\n\t} rate[0];\n};\n\nstruct scmi_msg_resp_clock_possible_parents {\n\t__le32 num_parent_flags;\n\t__le32 possible_parents[0];\n};\n\nstruct scmi_msg_resp_clock_protocol_attributes {\n\t__le16 num_clocks;\n\tu8 max_async_req;\n\tu8 reserved;\n};\n\nstruct scmi_msg_resp_desc_fc {\n\t__le32 attr;\n\t__le32 rate_limit;\n\t__le32 chan_addr_low;\n\t__le32 chan_addr_high;\n\t__le32 chan_size;\n\t__le32 db_addr_low;\n\t__le32 db_addr_high;\n\t__le32 db_set_lmask;\n\t__le32 db_set_hmask;\n\t__le32 db_preserve_lmask;\n\t__le32 db_preserve_hmask;\n};\n\nstruct scmi_msg_resp_describe_levels {\n\t__le32 flags;\n\t__le32 voltage[0];\n};\n\nstruct scmi_msg_resp_domain_attributes {\n\t__le32 attr;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_domain_name_get {\n\t__le32 flags;\n\tu8 name[64];\n};\n\nstruct scmi_msg_resp_perf_attributes {\n\t__le16 num_domains;\n\t__le16 flags;\n\t__le32 stats_addr_low;\n\t__le32 stats_addr_high;\n\t__le32 stats_size;\n};\n\nstruct scmi_msg_resp_perf_describe_levels {\n\t__le16 num_returned;\n\t__le16 num_remaining;\n\tstruct {\n\t\t__le32 perf_val;\n\t\t__le32 power;\n\t\t__le16 transition_latency_us;\n\t\t__le16 reserved;\n\t} opp[0];\n};\n\nstruct scmi_msg_resp_perf_describe_levels_v4 {\n\t__le16 num_returned;\n\t__le16 num_remaining;\n\tstruct {\n\t\t__le32 perf_val;\n\t\t__le32 power;\n\t\t__le16 transition_latency_us;\n\t\t__le16 reserved;\n\t\t__le32 indicative_freq;\n\t\t__le32 level_index;\n\t} opp[0];\n};\n\nstruct scmi_msg_resp_perf_domain_attributes {\n\t__le32 flags;\n\t__le32 rate_limit_us;\n\t__le32 sustained_freq_khz;\n\t__le32 sustained_perf_level;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_power_attributes {\n\t__le16 num_domains;\n\t__le16 reserved;\n\t__le32 stats_addr_low;\n\t__le32 stats_addr_high;\n\t__le32 stats_size;\n};\n\nstruct scmi_msg_resp_power_domain_attributes {\n\t__le32 flags;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_powercap_cap_set_complete {\n\t__le32 domain;\n\t__le32 power_cap;\n};\n\nstruct scmi_msg_resp_powercap_domain_attributes {\n\t__le32 attributes;\n\tu8 name[16];\n\t__le32 min_pai;\n\t__le32 max_pai;\n\t__le32 pai_step;\n\t__le32 min_power_cap;\n\t__le32 max_power_cap;\n\t__le32 power_cap_step;\n\t__le32 sustainable_power;\n\t__le32 accuracy;\n\t__le32 parent_id;\n};\n\nstruct scmi_msg_resp_powercap_meas_get {\n\t__le32 power;\n\t__le32 pai;\n};\n\nstruct scmi_msg_resp_reset_domain_attributes {\n\t__le32 attributes;\n\t__le32 latency;\n\tu8 name[16];\n};\n\nstruct scmi_msg_resp_sensor_attributes {\n\t__le16 num_sensors;\n\tu8 max_requests;\n\tu8 reserved;\n\t__le32 reg_addr_low;\n\t__le32 reg_addr_high;\n\t__le32 reg_size;\n};\n\nstruct scmi_msg_resp_sensor_axis_description {\n\t__le32 num_axis_flags;\n\tstruct scmi_axis_descriptor desc[0];\n};\n\nstruct scmi_sensor_axis_name_descriptor {\n\t__le32 axis_id;\n\tu8 name[64];\n};\n\nstruct scmi_msg_resp_sensor_axis_names_description {\n\t__le32 num_axis_flags;\n\tstruct scmi_sensor_axis_name_descriptor desc[0];\n};\n\nstruct scmi_sensor_descriptor {\n\t__le32 id;\n\t__le32 attributes_low;\n\t__le32 attributes_high;\n\tu8 name[16];\n\t__le32 power;\n\t__le32 resolution;\n\tstruct scmi_msg_resp_attrs scalar_attrs;\n};\n\nstruct scmi_msg_resp_sensor_description {\n\t__le16 num_returned;\n\t__le16 num_remaining;\n\tstruct scmi_sensor_descriptor desc[0];\n};\n\nstruct scmi_msg_resp_sensor_list_update_intervals {\n\t__le32 num_intervals_flags;\n\t__le32 intervals[0];\n};\n\nstruct scmi_msg_resp_set_rate_complete {\n\t__le32 id;\n\t__le32 rate_low;\n\t__le32 rate_high;\n};\n\nstruct scmi_msg_sensor_axis_description_get {\n\t__le32 id;\n\t__le32 axis_desc_index;\n};\n\nstruct scmi_msg_sensor_config_set {\n\t__le32 id;\n\t__le32 sensor_config;\n};\n\nstruct scmi_msg_sensor_description {\n\t__le32 desc_index;\n};\n\nstruct scmi_msg_sensor_list_update_intervals {\n\t__le32 id;\n\t__le32 index;\n};\n\nstruct scmi_msg_sensor_reading_get {\n\t__le32 id;\n\t__le32 flags;\n};\n\nstruct scmi_msg_sensor_request_notify {\n\t__le32 id;\n\t__le32 event_control;\n};\n\nstruct scmi_msg_set_sensor_trip_point {\n\t__le32 id;\n\t__le32 event_control;\n\t__le32 value_low;\n\t__le32 value_high;\n};\n\nstruct scmi_msg_settings_conf {\n\t__le32 identifier;\n\t__le32 function_id;\n\t__le32 attributes;\n\t__le32 configs[0];\n};\n\nstruct scmi_msg_settings_get {\n\t__le32 identifier;\n\t__le32 attributes;\n};\n\nstruct scmi_notifier_devres {\n\tconst struct scmi_handle *handle;\n\tu8 proto_id;\n\tu8 evt_id;\n\tu32 __src_id;\n\tu32 *src_id;\n\tstruct notifier_block *nb;\n};\n\nstruct scmi_registered_events_desc;\n\nstruct scmi_notify_instance {\n\tvoid *gid;\n\tstruct scmi_handle *handle;\n\tstruct work_struct init_work;\n\tstruct workqueue_struct *notify_wq;\n\tstruct mutex pending_mtx;\n\tstruct scmi_registered_events_desc **registered_protocols;\n\tstruct hlist_head pending_events_handlers[16];\n};\n\nstruct scmi_notify_ops {\n\tint (*devm_event_notifier_register)(struct scmi_device *, u8, u8, const u32 *, struct notifier_block *);\n\tint (*devm_event_notifier_unregister)(struct scmi_device *, struct notifier_block *);\n\tint (*event_notifier_register)(const struct scmi_handle *, u8, u8, const u32 *, struct notifier_block *);\n\tint (*event_notifier_unregister)(const struct scmi_handle *, u8, u8, const u32 *, struct notifier_block *);\n};\n\nstruct scmi_optee_agent {\n\tstruct device *dev;\n\tstruct tee_context *tee_ctx;\n\tu32 caps;\n\tstruct mutex mu;\n\tstruct list_head channel_list;\n};\n\nstruct scmi_optee_channel {\n\tu32 channel_id;\n\tu32 tee_session;\n\tu32 caps;\n\tu32 rx_len;\n\tstruct mutex mu;\n\tstruct scmi_chan_info *cinfo;\n\tunion {\n\t\tstruct scmi_shared_mem *shmem;\n\t\tstruct scmi_msg_payld *msg;\n\t} req;\n\tstruct scmi_shmem_io_ops *io_ops;\n\tstruct tee_shm *tee_shm;\n\tstruct list_head link;\n};\n\nstruct scmi_perf_proto_ops;\n\nstruct scmi_perf_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct scmi_perf_proto_ops *perf_ops;\n\tconst struct scmi_protocol_handle *ph;\n\tconst struct scmi_perf_domain_info *info;\n\tu32 domain_id;\n};\n\nstruct scmi_perf_get_limits {\n\t__le32 max_level;\n\t__le32 min_level;\n};\n\nstruct scmi_perf_info {\n\tu16 num_domains;\n\tenum scmi_power_scale power_scale;\n\tu64 stats_addr;\n\tu32 stats_size;\n\tbool notify_lvl_cmd;\n\tbool notify_lim_cmd;\n\tstruct perf_dom_info *dom_info;\n};\n\nstruct scmi_perf_level_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 performance_level;\n};\n\nstruct scmi_perf_level_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int performance_level;\n\tlong unsigned int performance_level_freq;\n};\n\nstruct scmi_perf_limits_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 range_max;\n\t__le32 range_min;\n};\n\nstruct scmi_perf_limits_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int range_max;\n\tunsigned int range_min;\n\tlong unsigned int range_max_freq;\n\tlong unsigned int range_min_freq;\n};\n\nstruct scmi_perf_notify_level_or_limits {\n\t__le32 domain;\n\t__le32 notify_enable;\n};\n\nstruct scmi_perf_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_perf_domain_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*limits_set)(const struct scmi_protocol_handle *, u32, u32, u32);\n\tint (*limits_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n\tint (*level_set)(const struct scmi_protocol_handle *, u32, u32, bool);\n\tint (*level_get)(const struct scmi_protocol_handle *, u32, u32 *, bool);\n\tint (*transition_latency_get)(const struct scmi_protocol_handle *, u32);\n\tint (*rate_limit_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*device_opps_add)(const struct scmi_protocol_handle *, struct device *, u32);\n\tint (*freq_set)(const struct scmi_protocol_handle *, u32, long unsigned int, bool);\n\tint (*freq_get)(const struct scmi_protocol_handle *, u32, long unsigned int *, bool);\n\tint (*est_power_get)(const struct scmi_protocol_handle *, u32, long unsigned int *, long unsigned int *);\n\tbool (*fast_switch_possible)(const struct scmi_protocol_handle *, u32);\n\tint (*fast_switch_rate_limit)(const struct scmi_protocol_handle *, u32, u32 *);\n\tenum scmi_power_scale (*power_scale_get)(const struct scmi_protocol_handle *);\n};\n\nstruct scmi_perf_set_level {\n\t__le32 domain;\n\t__le32 level;\n};\n\nstruct scmi_perf_set_limits {\n\t__le32 domain;\n\t__le32 max_level;\n\t__le32 min_level;\n};\n\nstruct scmi_pin_info {\n\tchar name[64];\n\tbool present;\n};\n\nstruct scmi_pinctrl_proto_ops;\n\nstruct scmi_pinctrl_imx {\n\tstruct device *dev;\n\tstruct scmi_protocol_handle *ph;\n\tstruct pinctrl_dev *pctldev;\n\tstruct pinctrl_desc pctl_desc;\n\tconst struct scmi_pinctrl_proto_ops *ops;\n};\n\nstruct scmi_pinctrl_info {\n\tint nr_groups;\n\tint nr_functions;\n\tint nr_pins;\n\tstruct scmi_group_info *groups;\n\tstruct scmi_function_info *functions;\n\tstruct scmi_pin_info *pins;\n};\n\nstruct scmi_pinctrl_ipriv {\n\tu32 selector;\n\tenum scmi_pinctrl_selector_type type;\n\tu32 *array;\n};\n\nstruct scmi_pinctrl_proto_ops {\n\tint (*count_get)(const struct scmi_protocol_handle *, enum scmi_pinctrl_selector_type);\n\tint (*name_get)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, const char **);\n\tint (*group_pins_get)(const struct scmi_protocol_handle *, u32, const unsigned int **, unsigned int *);\n\tint (*function_groups_get)(const struct scmi_protocol_handle *, u32, unsigned int *, const unsigned int **);\n\tint (*mux_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*settings_get_one)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, enum scmi_pinctrl_conf_type, u32 *);\n\tint (*settings_get_all)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, unsigned int *, enum scmi_pinctrl_conf_type *, u32 *);\n\tint (*settings_conf)(const struct scmi_protocol_handle *, u32, enum scmi_pinctrl_selector_type, unsigned int, enum scmi_pinctrl_conf_type *, u32 *);\n\tint (*pin_request)(const struct scmi_protocol_handle *, u32);\n\tint (*pin_free)(const struct scmi_protocol_handle *, u32);\n};\n\nstruct scmi_pm_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct scmi_protocol_handle *ph;\n\tconst char *name;\n\tu32 domain;\n};\n\nstruct scmi_power_info {\n\tbool notify_state_change_cmd;\n\tint num_domains;\n\tu64 stats_addr;\n\tu32 stats_size;\n\tstruct power_dom_info *dom_info;\n};\n\nstruct scmi_power_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst char * (*name_get)(const struct scmi_protocol_handle *, u32);\n\tint (*state_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*state_get)(const struct scmi_protocol_handle *, u32, u32 *);\n};\n\nstruct scmi_power_set_state {\n\t__le32 flags;\n\t__le32 domain;\n\t__le32 state;\n};\n\nstruct scmi_power_state_changed_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int power_state;\n};\n\nstruct scmi_power_state_notify {\n\t__le32 domain;\n\t__le32 notify_enable;\n};\n\nstruct scmi_power_state_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 power_state;\n};\n\nstruct scmi_powercap_cap_changed_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 power_cap;\n\t__le32 pai;\n};\n\nstruct scmi_powercap_cap_changed_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int power_cap;\n\tunsigned int pai;\n};\n\nstruct scmi_powercap_info {\n\tunsigned int id;\n\tbool notify_powercap_cap_change;\n\tbool notify_powercap_measurement_change;\n\tbool async_powercap_cap_set;\n\tbool powercap_cap_config;\n\tbool powercap_monitoring;\n\tbool powercap_pai_config;\n\tbool powercap_scale_mw;\n\tbool powercap_scale_uw;\n\tbool fastchannels;\n\tchar name[64];\n\tunsigned int min_pai;\n\tunsigned int max_pai;\n\tunsigned int pai_step;\n\tunsigned int min_power_cap;\n\tunsigned int max_power_cap;\n\tunsigned int power_cap_step;\n\tunsigned int sustainable_power;\n\tunsigned int accuracy;\n\tunsigned int parent_id;\n\tstruct scmi_fc_info *fc_info;\n};\n\nstruct scmi_powercap_meas_changed_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 power;\n};\n\nstruct scmi_powercap_meas_changed_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int power;\n};\n\nstruct scmi_powercap_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_powercap_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*cap_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*cap_set)(const struct scmi_protocol_handle *, u32, u32, bool);\n\tint (*cap_enable_set)(const struct scmi_protocol_handle *, u32, bool);\n\tint (*cap_enable_get)(const struct scmi_protocol_handle *, u32, bool *);\n\tint (*pai_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*pai_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*measurements_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n\tint (*measurements_threshold_set)(const struct scmi_protocol_handle *, u32, u32, u32);\n\tint (*measurements_threshold_get)(const struct scmi_protocol_handle *, u32, u32 *, u32 *);\n};\n\nstruct scmi_powercap_state {\n\tbool enabled;\n\tu32 last_pcap;\n\tbool meas_notif_enabled;\n\tu64 thresholds;\n};\n\nstruct scmi_proto_helpers_ops {\n\tint (*extended_name_get)(const struct scmi_protocol_handle *, u8, u32, u32 *, char *, size_t);\n\tvoid * (*iter_response_init)(const struct scmi_protocol_handle *, struct scmi_iterator_ops *, unsigned int, u8, size_t, void *);\n\tint (*iter_response_run)(void *);\n\tint (*protocol_msg_check)(const struct scmi_protocol_handle *, u32, u32 *);\n\tvoid (*fastchannel_init)(const struct scmi_protocol_handle *, u8, u32, u32, u32, void **, struct scmi_fc_db_info **, u32 *);\n\tvoid (*fastchannel_db_ring)(struct scmi_fc_db_info *);\n\tint (*get_max_msg_size)(const struct scmi_protocol_handle *);\n};\n\ntypedef int (*scmi_prot_init_ph_fn_t)(const struct scmi_protocol_handle *);\n\nstruct scmi_protocol_events;\n\nstruct scmi_protocol {\n\tconst u8 id;\n\tstruct module *owner;\n\tconst scmi_prot_init_ph_fn_t instance_init;\n\tconst scmi_prot_init_ph_fn_t instance_deinit;\n\tconst void *ops;\n\tconst struct scmi_protocol_events *events;\n\tunsigned int supported_version;\n\tchar *vendor_id;\n\tchar *sub_vendor_id;\n\tu32 impl_ver;\n};\n\nstruct scmi_protocol_devres {\n\tconst struct scmi_handle *handle;\n\tu8 protocol_id;\n};\n\nstruct scmi_protocol_events {\n\tsize_t queue_sz;\n\tconst struct scmi_event_ops *ops;\n\tconst struct scmi_event *evts;\n\tunsigned int num_events;\n\tunsigned int num_sources;\n};\n\nstruct scmi_xfer_ops;\n\nstruct scmi_protocol_handle {\n\tstruct device *dev;\n\tunsigned int version;\n\tconst struct scmi_xfer_ops *xops;\n\tconst struct scmi_proto_helpers_ops *hops;\n\tint (*set_priv)(const struct scmi_protocol_handle *, void *);\n\tvoid * (*get_priv)(const struct scmi_protocol_handle *);\n};\n\nstruct scmi_protocol_instance {\n\tconst struct scmi_handle *handle;\n\tconst struct scmi_protocol *proto;\n\tvoid *gid;\n\trefcount_t users;\n\tvoid *priv;\n\tunsigned int version;\n\tunsigned int negotiated_version;\n\tstruct scmi_protocol_handle ph;\n};\n\nstruct scmi_quirk {\n\tbool enabled;\n\tconst char *name;\n\tconst char *vendor;\n\tconst char *sub_vendor_id;\n\tconst char *impl_ver_range;\n\tu32 start_range;\n\tu32 end_range;\n\tstruct static_key_false *key;\n\tstruct hlist_node hash;\n\tunsigned int hkey;\n\tconst char * const compats[0];\n};\n\nstruct scmi_range_attrs {\n\tlong long int min_range;\n\tlong long int max_range;\n};\n\nstruct scmi_registered_event {\n\tstruct scmi_registered_events_desc *proto;\n\tconst struct scmi_event *evt;\n\tvoid *report;\n\tu32 num_sources;\n\tbool not_supported_by_platform;\n\trefcount_t *sources;\n\tstruct mutex sources_mtx;\n};\n\nstruct scmi_registered_events_desc {\n\tu8 id;\n\tconst struct scmi_event_ops *ops;\n\tstruct events_queue equeue;\n\tstruct scmi_notify_instance *ni;\n\tstruct scmi_event_header *eh;\n\tsize_t eh_sz;\n\tvoid *in_flight;\n\tint num_events;\n\tstruct scmi_registered_event **registered_events;\n\tstruct mutex registered_mtx;\n\tconst struct scmi_protocol_handle *ph;\n\tstruct hlist_head registered_events_handlers[64];\n};\n\nstruct scmi_regulator {\n\tu32 id;\n\tstruct scmi_device *sdev;\n\tstruct scmi_protocol_handle *ph;\n\tstruct regulator_dev *rdev;\n\tstruct device_node *of_node;\n\tstruct regulator_desc desc;\n\tstruct regulator_config conf;\n};\n\nstruct scmi_regulator_info {\n\tint num_doms;\n\tstruct scmi_regulator **sregv;\n};\n\nstruct scmi_requested_dev {\n\tconst struct scmi_device_id *id_table;\n\tstruct list_head node;\n};\n\nstruct scmi_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tconst struct scmi_protocol_handle *ph;\n};\n\nstruct scmi_reset_info {\n\tint num_domains;\n\tbool notify_reset_cmd;\n\tstruct reset_dom_info *dom_info;\n};\n\nstruct scmi_reset_issued_notify_payld {\n\t__le32 agent_id;\n\t__le32 domain_id;\n\t__le32 reset_state;\n};\n\nstruct scmi_reset_issued_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int domain_id;\n\tunsigned int reset_state;\n};\n\nstruct scmi_reset_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst char * (*name_get)(const struct scmi_protocol_handle *, u32);\n\tint (*latency_get)(const struct scmi_protocol_handle *, u32);\n\tint (*reset)(const struct scmi_protocol_handle *, u32);\n\tint (*assert)(const struct scmi_protocol_handle *, u32);\n\tint (*deassert)(const struct scmi_protocol_handle *, u32);\n};\n\nstruct scmi_resp_pinctrl_attributes {\n\t__le32 attributes;\n\tu8 name[16];\n};\n\nstruct scmi_resp_pinctrl_list_assoc {\n\t__le32 flags;\n\t__le16 array[0];\n};\n\nstruct scmi_resp_sensor_reading_complete {\n\t__le32 id;\n\t__le32 readings_low;\n\t__le32 readings_high;\n};\n\nstruct scmi_sensor_reading_resp {\n\t__le32 sensor_value_low;\n\t__le32 sensor_value_high;\n\t__le32 timestamp_low;\n\t__le32 timestamp_high;\n};\n\nstruct scmi_resp_sensor_reading_complete_v3 {\n\t__le32 id;\n\tstruct scmi_sensor_reading_resp readings[0];\n};\n\nstruct scmi_resp_settings_get {\n\t__le32 function_selected;\n\t__le32 num_configs;\n\t__le32 configs[0];\n};\n\nstruct scmi_resp_voltage_level_set_complete {\n\t__le32 domain_id;\n\t__le32 voltage_level;\n};\n\nstruct scmi_sens_ipriv {\n\tvoid *priv;\n\tstruct device *dev;\n};\n\nstruct scmi_sensor_axis_info {\n\tunsigned int id;\n\tunsigned int type;\n\tint scale;\n\tchar name[64];\n\tbool extended_attrs;\n\tunsigned int resolution;\n\tint exponent;\n\tstruct scmi_range_attrs attrs;\n};\n\nstruct scmi_sensor_intervals_info {\n\tbool segmented;\n\tunsigned int count;\n\tunsigned int *desc;\n\tunsigned int prealloc_pool[16];\n};\n\nstruct scmi_sensor_info {\n\tunsigned int id;\n\tunsigned int type;\n\tint scale;\n\tunsigned int num_trip_points;\n\tbool async;\n\tbool update;\n\tbool timestamped;\n\tint tstamp_scale;\n\tunsigned int num_axis;\n\tstruct scmi_sensor_axis_info *axis;\n\tstruct scmi_sensor_intervals_info intervals;\n\tunsigned int sensor_config;\n\tchar name[64];\n\tbool extended_scalar_attrs;\n\tunsigned int sensor_power;\n\tunsigned int resolution;\n\tint exponent;\n\tstruct scmi_range_attrs scalar_attrs;\n};\n\nstruct scmi_sensor_reading;\n\nstruct scmi_sensor_proto_ops {\n\tint (*count_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_sensor_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*trip_point_config)(const struct scmi_protocol_handle *, u32, u8, u64);\n\tint (*reading_get)(const struct scmi_protocol_handle *, u32, u64 *);\n\tint (*reading_get_timestamped)(const struct scmi_protocol_handle *, u32, u8, struct scmi_sensor_reading *);\n\tint (*config_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*config_set)(const struct scmi_protocol_handle *, u32, u32);\n};\n\nstruct scmi_sensor_reading {\n\tlong long int value;\n\tlong long unsigned int timestamp;\n};\n\nstruct scmi_sensor_trip_notify_payld {\n\t__le32 agent_id;\n\t__le32 sensor_id;\n\t__le32 trip_point_desc;\n};\n\nstruct scmi_sensor_trip_point_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int sensor_id;\n\tunsigned int trip_point_desc;\n};\n\nstruct scmi_sensor_update_notify_payld {\n\t__le32 agent_id;\n\t__le32 sensor_id;\n\tstruct scmi_sensor_reading_resp readings[0];\n};\n\nstruct scmi_sensor_update_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int sensor_id;\n\tunsigned int readings_count;\n\tstruct scmi_sensor_reading readings[0];\n};\n\nstruct scmi_sensors {\n\tconst struct scmi_protocol_handle *ph;\n\tconst struct scmi_sensor_info **info[11];\n};\n\nstruct scmi_settings_get_ipriv {\n\tu32 selector;\n\tenum scmi_pinctrl_selector_type type;\n\tbool get_all;\n\tunsigned int *nr_configs;\n\tenum scmi_pinctrl_conf_type *config_types;\n\tu32 *config_values;\n};\n\nstruct scmi_shared_mem {\n\t__le32 reserved;\n\t__le32 channel_status;\n\t__le32 reserved1[2];\n\t__le32 flags;\n\t__le32 length;\n\t__le32 msg_header;\n\tu8 msg_payload[0];\n};\n\ntypedef void (*shmem_copy_toio_t)(void *, const void *, size_t);\n\ntypedef void (*shmem_copy_fromio_t)(void *, const void *, size_t);\n\nstruct scmi_shared_mem_operations {\n\tvoid (*tx_prepare)(struct scmi_shared_mem *, struct scmi_xfer *, struct scmi_chan_info *, shmem_copy_toio_t);\n\tu32 (*read_header)(struct scmi_shared_mem *);\n\tvoid (*fetch_response)(struct scmi_shared_mem *, struct scmi_xfer *, shmem_copy_fromio_t);\n\tvoid (*fetch_notification)(struct scmi_shared_mem *, size_t, struct scmi_xfer *, shmem_copy_fromio_t);\n\tvoid (*clear_channel)(struct scmi_shared_mem *);\n\tbool (*poll_done)(struct scmi_shared_mem *, struct scmi_xfer *);\n\tbool (*channel_free)(struct scmi_shared_mem *);\n\tbool (*channel_intr_enabled)(struct scmi_shared_mem *);\n\tvoid * (*setup_iomap)(struct scmi_chan_info *, struct device *, bool, struct resource *, struct scmi_shmem_io_ops **);\n};\n\nstruct scmi_shmem_io_ops {\n\tshmem_copy_fromio_t fromio;\n\tshmem_copy_toio_t toio;\n};\n\nstruct scmi_smc {\n\tint irq;\n\tstruct scmi_chan_info *cinfo;\n\tstruct scmi_shared_mem *shmem;\n\tstruct scmi_shmem_io_ops *io_ops;\n\tstruct mutex shmem_lock;\n\tatomic_t inflight;\n\tlong unsigned int func_id;\n\tlong unsigned int param_page;\n\tlong unsigned int param_offset;\n\tlong unsigned int cap_id;\n};\n\nstruct scmi_system_info {\n\tbool graceful_timeout_supported;\n\tbool power_state_notify_cmd;\n};\n\nstruct scmi_system_power_state_notifier_payld {\n\t__le32 agent_id;\n\t__le32 flags;\n\t__le32 system_state;\n\t__le32 timeout;\n};\n\nstruct scmi_system_power_state_notifier_report {\n\tktime_t timestamp;\n\tunsigned int agent_id;\n\tunsigned int flags;\n\tunsigned int system_state;\n\tunsigned int timeout;\n};\n\nstruct scmi_system_power_state_notify {\n\t__le32 notify_enable;\n};\n\nstruct scmi_thermal_sensor {\n\tconst struct scmi_protocol_handle *ph;\n\tconst struct scmi_sensor_info *info;\n};\n\nstruct scmi_transport_core_operations;\n\nstruct scmi_transport {\n\tstruct device *supplier;\n\tstruct scmi_desc desc;\n\tstruct scmi_transport_core_operations **core_ops;\n};\n\nstruct scmi_transport_core_operations {\n\tvoid (*bad_message_trace)(struct scmi_chan_info *, u32, enum scmi_bad_msg);\n\tvoid (*rx_callback)(struct scmi_chan_info *, u32, void *);\n\tconst struct scmi_shared_mem_operations *shmem;\n\tconst struct scmi_message_operations *msg;\n};\n\nstruct scmi_transport_ops {\n\tbool (*chan_available)(struct device_node *, int);\n\tint (*chan_setup)(struct scmi_chan_info *, struct device *, bool);\n\tint (*chan_free)(int, void *, void *);\n\tunsigned int (*get_max_msg)(struct scmi_chan_info *);\n\tint (*send_message)(struct scmi_chan_info *, struct scmi_xfer *);\n\tvoid (*mark_txdone)(struct scmi_chan_info *, int, struct scmi_xfer *);\n\tvoid (*fetch_response)(struct scmi_chan_info *, struct scmi_xfer *);\n\tvoid (*fetch_notification)(struct scmi_chan_info *, size_t, struct scmi_xfer *);\n\tvoid (*clear_channel)(struct scmi_chan_info *);\n\tbool (*poll_done)(struct scmi_chan_info *, struct scmi_xfer *);\n};\n\nstruct scmi_voltage_info;\n\nstruct scmi_volt_ipriv {\n\tstruct device *dev;\n\tstruct scmi_voltage_info *v;\n};\n\nstruct scmi_voltage_info {\n\tunsigned int id;\n\tbool segmented;\n\tbool negative_volts_allowed;\n\tbool async_level_set;\n\tchar name[64];\n\tunsigned int num_levels;\n\tint *levels_uv;\n};\n\nstruct scmi_voltage_proto_ops {\n\tint (*num_domains_get)(const struct scmi_protocol_handle *);\n\tconst struct scmi_voltage_info * (*info_get)(const struct scmi_protocol_handle *, u32);\n\tint (*config_set)(const struct scmi_protocol_handle *, u32, u32);\n\tint (*config_get)(const struct scmi_protocol_handle *, u32, u32 *);\n\tint (*level_set)(const struct scmi_protocol_handle *, u32, enum scmi_voltage_level_mode, s32);\n\tint (*level_get)(const struct scmi_protocol_handle *, u32, s32 *);\n};\n\nstruct scmi_xfer {\n\tint transfer_id;\n\tstruct scmi_msg_hdr hdr;\n\tstruct scmi_msg tx;\n\tstruct scmi_msg rx;\n\tstruct completion done;\n\tstruct completion *async_done;\n\tbool pending;\n\tstruct hlist_node node;\n\trefcount_t users;\n\tatomic_t busy;\n\tint state;\n\tint flags;\n\tspinlock_t lock;\n\tvoid *priv;\n};\n\nstruct scmi_xfer_ops {\n\tint (*xfer_get_init)(const struct scmi_protocol_handle *, u8, size_t, size_t, struct scmi_xfer **);\n\tvoid (*reset_rx_to_maxsz)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n\tint (*do_xfer)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n\tint (*do_xfer_with_response)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n\tvoid (*xfer_put)(const struct scmi_protocol_handle *, struct scmi_xfer *);\n};\n\nstruct scomp_alg {\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_acomp_streams streams;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tunion {\n\t\tvoid *src;\n\t\tlong unsigned int saddr;\n\t};\n};\n\nstruct scp_ctrl_reg {\n\tint pwr_sta_offs;\n\tint pwr_sta2nd_offs;\n};\n\nstruct scp_domain;\n\nstruct scp {\n\tstruct scp_domain *domains;\n\tstruct genpd_onecell_data pd_data;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct regmap *infracfg;\n\tstruct scp_ctrl_reg ctrl_reg;\n\tbool bus_prot_reg_update;\n};\n\nstruct scp_capabilities {\n\t__le32 protocol_version;\n\t__le32 event_version;\n\t__le32 platform_version;\n\t__le32 commands[4];\n};\n\nstruct scp_domain_data;\n\nstruct scp_domain {\n\tstruct generic_pm_domain genpd;\n\tstruct scp *scp;\n\tstruct clk *clk[3];\n\tconst struct scp_domain_data *data;\n\tstruct regulator *supply;\n};\n\nstruct scp_domain_data {\n\tconst char *name;\n\tu32 sta_mask;\n\tint ctl_offs;\n\tu32 sram_pdn_bits;\n\tu32 sram_pdn_ack_bits;\n\tu32 bus_prot_mask;\n\tenum clk_id___2 clk_id[3];\n\tu8 caps;\n};\n\nstruct scp_subdomain;\n\nstruct scp_soc_data {\n\tconst struct scp_domain_data *domains;\n\tint num_domains;\n\tconst struct scp_subdomain *subdomains;\n\tint num_subdomains;\n\tconst struct scp_ctrl_reg regs;\n\tbool bus_prot_reg_update;\n};\n\nstruct scp_subdomain {\n\tint origin;\n\tint subdomain;\n};\n\nstruct scpi_xfer;\n\nstruct scpi_chan {\n\tstruct mbox_client cl;\n\tstruct mbox_chan *chan;\n\tvoid *tx_payload;\n\tvoid *rx_payload;\n\tstruct list_head rx_pending;\n\tstruct list_head xfers_list;\n\tstruct scpi_xfer *xfers;\n\tspinlock_t rx_lock;\n\tstruct mutex xfers_lock;\n\tu8 token;\n};\n\nstruct scpi_dvfs_info;\n\nstruct scpi_ops;\n\nstruct scpi_clk {\n\tu32 id;\n\tstruct clk_hw hw;\n\tstruct scpi_dvfs_info *info;\n\tstruct scpi_ops *scpi_ops;\n};\n\nstruct scpi_clk_data {\n\tstruct scpi_clk **clk;\n\tunsigned int clk_num;\n};\n\nstruct scpi_data {\n\tstruct clk *clk;\n\tstruct device *cpu_dev;\n};\n\nstruct scpi_drvinfo {\n\tu32 protocol_version;\n\tu32 firmware_version;\n\tbool is_legacy;\n\tint num_chans;\n\tint *commands;\n\tlong unsigned int cmd_priority[1];\n\tatomic_t next_chan;\n\tstruct scpi_ops *scpi_ops;\n\tstruct scpi_chan *channels;\n\tstruct scpi_dvfs_info *dvfs[8];\n};\n\nstruct scpi_opp;\n\nstruct scpi_dvfs_info {\n\tunsigned int count;\n\tunsigned int latency;\n\tstruct scpi_opp *opps;\n};\n\nstruct scpi_opp {\n\tu32 freq;\n\tu32 m_volt;\n};\n\nstruct scpi_sensor_info;\n\nstruct scpi_ops {\n\tu32 (*get_version)(void);\n\tint (*clk_get_range)(u16, long unsigned int *, long unsigned int *);\n\tlong unsigned int (*clk_get_val)(u16);\n\tint (*clk_set_val)(u16, long unsigned int);\n\tint (*dvfs_get_idx)(u8);\n\tint (*dvfs_set_idx)(u8, u8);\n\tstruct scpi_dvfs_info * (*dvfs_get_info)(u8);\n\tint (*device_domain_id)(struct device *);\n\tint (*get_transition_latency)(struct device *);\n\tint (*add_opps_to_device)(struct device *);\n\tint (*sensor_get_capability)(u16 *);\n\tint (*sensor_get_info)(u16, struct scpi_sensor_info *);\n\tint (*sensor_get_value)(u16, u64 *);\n\tint (*device_get_power_state)(u16);\n\tint (*device_set_power_state)(u16, u8);\n};\n\nstruct scpi_pm_domain {\n\tstruct generic_pm_domain genpd;\n\tstruct scpi_ops *ops;\n\tu32 domain;\n};\n\nstruct scpi_sensor_info {\n\tu16 sensor_id;\n\tu8 class;\n\tu8 trigger_type;\n\tchar name[20];\n};\n\nstruct sensor_data;\n\nstruct scpi_sensors {\n\tstruct scpi_ops *scpi_ops;\n\tstruct sensor_data *data;\n\tstruct list_head thermal_zones;\n\tstruct attribute **attrs;\n\tstruct attribute_group group;\n\tconst struct attribute_group *groups[2];\n};\n\nstruct scpi_shared_mem {\n\t__le32 command;\n\t__le32 status;\n\tu8 payload[0];\n};\n\nstruct scpi_thermal_zone {\n\tint sensor_id;\n\tstruct scpi_sensors *scpi_sensors;\n};\n\nstruct scpi_xfer {\n\tu32 slot;\n\tu32 cmd;\n\tu32 status;\n\tconst void *tx_buf;\n\tvoid *rx_buf;\n\tunsigned int tx_len;\n\tunsigned int rx_len;\n\tstruct list_head node;\n\tstruct completion done;\n};\n\nstruct scpsys_soc_data;\n\nstruct scpsys {\n\tstruct device *dev;\n\tstruct regmap *base;\n\tconst struct scpsys_soc_data *soc_data;\n\tu8 bus_prot_index[4];\n\tstruct regmap **bus_prot;\n\tstruct genpd_onecell_data pd_data;\n\tstruct generic_pm_domain *domains[0];\n};\n\nstruct scpsys_bus_prot_data {\n\tu8 bus_prot_block;\n\tu8 bus_prot_sta_block;\n\tu32 bus_prot_set_clr_mask;\n\tu32 bus_prot_set;\n\tu32 bus_prot_clr;\n\tu32 bus_prot_sta_mask;\n\tu32 bus_prot_sta;\n\tu8 flags;\n};\n\nstruct scpsys_domain_data;\n\nstruct scpsys_hwv_domain_data;\n\nstruct scpsys_domain {\n\tstruct generic_pm_domain genpd;\n\tconst struct scpsys_domain_data *data;\n\tconst struct scpsys_hwv_domain_data *hwv_data;\n\tstruct scpsys *scpsys;\n\tint num_clks;\n\tstruct clk_bulk_data *clks;\n\tint num_subsys_clks;\n\tstruct clk_bulk_data *subsys_clks;\n\tstruct regulator *supply;\n};\n\nstruct scpsys_domain_data {\n\tconst char *name;\n\tu32 sta_mask;\n\tu32 sta2nd_mask;\n\tint ctl_offs;\n\tu32 sram_pdn_bits;\n\tu32 sram_pdn_ack_bits;\n\tint ext_buck_iso_offs;\n\tu32 ext_buck_iso_mask;\n\tu16 caps;\n\tenum scpsys_rtff_type rtff_type;\n\tconst struct scpsys_bus_prot_data bp_cfg[7];\n\tint pwr_sta_offs;\n\tint pwr_sta2nd_offs;\n};\n\nstruct scpsys_hwv_domain_data {\n\tconst char *name;\n\tu16 set;\n\tu16 clr;\n\tu16 done;\n\tu16 en;\n\tu16 set_sta;\n\tu16 clr_sta;\n\tu8 setclr_bit;\n\tu8 sta_bit;\n\tu16 caps;\n};\n\nstruct scpsys_soc_data {\n\tconst struct scpsys_domain_data *domains_data;\n\tint num_domains;\n\tconst struct scpsys_hwv_domain_data *hwv_domains_data;\n\tint num_hwv_domains;\n\tenum scpsys_bus_prot_block *bus_prot_blocks;\n\tint num_bus_prot_blocks;\n\tenum scpsys_mtcmos_type type;\n};\n\nstruct scratch {\n\tu8 status[29];\n\tu8 data_token;\n\t__be16 crc_val;\n};\n\nstruct screen_info {\n\t__u8 orig_x;\n\t__u8 orig_y;\n\t__u16 ext_mem_k;\n\t__u16 orig_video_page;\n\t__u8 orig_video_mode;\n\t__u8 orig_video_cols;\n\t__u8 flags;\n\t__u8 unused2;\n\t__u16 orig_video_ega_bx;\n\t__u16 unused3;\n\t__u8 orig_video_lines;\n\t__u8 orig_video_isVGA;\n\t__u16 orig_video_points;\n\t__u16 lfb_width;\n\t__u16 lfb_height;\n\t__u16 lfb_depth;\n\t__u32 lfb_base;\n\t__u32 lfb_size;\n\t__u16 cl_magic;\n\t__u16 cl_offset;\n\t__u16 lfb_linelength;\n\t__u8 red_size;\n\t__u8 red_pos;\n\t__u8 green_size;\n\t__u8 green_pos;\n\t__u8 blue_size;\n\t__u8 blue_pos;\n\t__u8 rsvd_size;\n\t__u8 rsvd_pos;\n\t__u16 vesapm_seg;\n\t__u16 vesapm_off;\n\t__u16 pages;\n\t__u16 vesa_attributes;\n\t__u32 capabilities;\n\t__u32 ext_lfb_base;\n\t__u8 _reserved[2];\n} __attribute__((packed));\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_sense_hdr;\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n\tstruct bio_crypt_ctx *rq_crypt_ctx;\n\tstruct blk_crypto_keyslot *rq_crypt_keyslot;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*compat_ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 ic_enable: 1;\n\tu8 cs_enble: 1;\n\tu8 st_enble: 1;\n\tu8 reserved1: 3;\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved2[3];\n\tu8 lbm_descriptor_type: 4;\n\tu8 rlbsr: 2;\n\tu8 reserved3: 1;\n\tu8 acdlu: 1;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 reserved1: 7;\n\tu8 perm: 1;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 rel_lifetime: 6;\n\tu8 reserved3: 2;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct sctphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 vtag;\n\t__le32 checksum;\n};\n\nstruct scu_gpio_priv {\n\tstruct gpio_chip chip;\n\tstruct mutex lock;\n\tstruct device *dev;\n\tstruct imx_sc_ipc *handle;\n};\n\nstruct scu_wakeup {\n\tu32 mask;\n\tu32 wakeup_src;\n\tbool valid;\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tconst char *reason;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[1];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work error_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n};\n\nstruct sd_app_op_cond_busy_data {\n\tstruct mmc_host *host;\n\tu32 ocr;\n\tstruct mmc_command *cmd;\n};\n\nstruct sd_busy_data {\n\tstruct mmc_card *card;\n\tu8 *reg_buf;\n};\n\nstruct sd_emmc_desc {\n\tu32 cmd_cfg;\n\tu32 cmd_arg;\n\tu32 cmd_data;\n\tu32 cmd_resp;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct sd_mux_hw_data {\n\tstruct clk_hw_data hw_data;\n\tconst u32 *mtable;\n};\n\nstruct sd_uhs2_wait_active_state_data {\n\tstruct mmc_host *host;\n\tstruct mmc_command *cmd;\n};\n\nstruct sdei_event;\n\nstruct sdei_crosscall_args {\n\tstruct sdei_event *event;\n\tatomic_t errors;\n\tint first_error;\n};\n\nstruct sdei_registered_event;\n\nstruct sdei_event {\n\tstruct list_head list;\n\tbool reregister;\n\tbool reenable;\n\tu32 event_num;\n\tu8 type;\n\tu8 priority;\n\tunion {\n\t\tstruct sdei_registered_event *registered;\n\t\tstruct sdei_registered_event *private_registered;\n\t};\n};\n\ntypedef int sdei_event_callback(u32, struct pt_regs *, void *);\n\nstruct sdei_registered_event {\n\tstruct pt_regs interrupted_regs;\n\tsdei_event_callback *callback;\n\tvoid *callback_arg;\n\tu32 event_num;\n\tu8 priority;\n};\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tvoid *__ctx[0];\n};\n\nstruct sdesc {\n\tstruct shash_desc shash;\n};\n\nstruct sdhci_acpi_chip {\n\tconst struct sdhci_ops *ops;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tlong unsigned int caps;\n\tunsigned int caps2;\n\tmmc_pm_flag_t pm_caps;\n};\n\nstruct sdhci_acpi_slot;\n\nstruct sdhci_acpi_host {\n\tstruct sdhci_host *host;\n\tconst struct sdhci_acpi_slot *slot;\n\tstruct platform_device *pdev;\n\tbool use_runtime_pm;\n\tbool is_intel;\n\tbool reset_signal_volt_on_suspend;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct sdhci_acpi_slot {\n\tconst struct sdhci_acpi_chip *chip;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tlong unsigned int caps;\n\tunsigned int caps2;\n\tmmc_pm_flag_t pm_caps;\n\tunsigned int flags;\n\tsize_t priv_size;\n\tint (*probe_slot)(struct platform_device *, struct acpi_device *);\n\tint (*remove_slot)(struct platform_device *);\n\tint (*free_slot)(struct platform_device *);\n\tint (*setup_host)(struct platform_device *);\n};\n\nstruct sdhci_acpi_uid_slot {\n\tconst char *hid;\n\tconst char *uid;\n\tconst struct sdhci_acpi_slot *slot;\n};\n\nstruct sdhci_adma2_64_desc {\n\t__le16 cmd;\n\t__le16 len;\n\t__le32 addr_lo;\n\t__le32 addr_hi;\n};\n\nstruct sdhci_am654_data {\n\tstruct regmap *base;\n\tu32 otap_del_sel[11];\n\tu32 itap_del_sel[11];\n\tu32 itap_del_ena[11];\n\tint clkbuf_sel;\n\tint trm_icp;\n\tint drv_strength;\n\tint strb_sel;\n\tu32 flags;\n\tu32 quirks;\n\tbool dll_enable;\n\tu32 tuning_loop;\n};\n\nstruct sdhci_am654_driver_data {\n\tconst struct sdhci_pltfm_data *pdata;\n\tu32 flags;\n\tu32 quirks;\n};\n\nstruct sdhci_arasan_clk_data {\n\tstruct clk_hw sdcardclk_hw;\n\tstruct clk *sdcardclk;\n\tstruct clk_hw sampleclk_hw;\n\tstruct clk *sampleclk;\n\tint clk_phase_in[11];\n\tint clk_phase_out[11];\n\tvoid (*set_clk_delays)(struct sdhci_host *);\n\tvoid *clk_of_data;\n};\n\nstruct sdhci_arasan_clk_ops {\n\tconst struct clk_ops *sdcardclk_ops;\n\tconst struct clk_ops *sampleclk_ops;\n};\n\nstruct sdhci_arasan_soc_ctl_map;\n\nstruct sdhci_arasan_data {\n\tstruct sdhci_host *host;\n\tstruct clk *clk_ahb;\n\tstruct phy *phy;\n\tbool is_phy_on;\n\tbool internal_phy_reg;\n\tbool has_cqe;\n\tstruct sdhci_arasan_clk_data clk_data;\n\tconst struct sdhci_arasan_clk_ops *clk_ops;\n\tstruct regmap *soc_ctl_base;\n\tconst struct sdhci_arasan_soc_ctl_map *soc_ctl_map;\n\tunsigned int quirks;\n};\n\nstruct sdhci_arasan_of_data {\n\tconst struct sdhci_arasan_soc_ctl_map *soc_ctl_map;\n\tconst struct sdhci_pltfm_data *pdata;\n\tconst struct sdhci_arasan_clk_ops *clk_ops;\n\tu32 quirks;\n};\n\nstruct sdhci_arasan_soc_ctl_field {\n\tu32 reg;\n\tu16 width;\n\ts16 shift;\n};\n\nstruct sdhci_arasan_soc_ctl_map {\n\tstruct sdhci_arasan_soc_ctl_field baseclkfreq;\n\tstruct sdhci_arasan_soc_ctl_field clockmultiplier;\n\tstruct sdhci_arasan_soc_ctl_field support64b;\n\tbool hiword_update;\n};\n\nstruct sdhci_brcmstb_saved_regs {\n\tu32 sd_pin_sel;\n\tu32 phy_sw_mode0_rxctrl;\n\tu32 max_50mhz_mode;\n\tu32 boot_main_ctl;\n};\n\nstruct sdhci_brcmstb_priv {\n\tvoid *cfg_regs;\n\tvoid *boot_regs;\n\tstruct sdhci_brcmstb_saved_regs saved_regs;\n\tunsigned int flags;\n\tstruct clk *base_clk;\n\tu32 base_freq_hz;\n\tconst struct brcmstb_match_priv *match_priv;\n};\n\nstruct sdhci_cdns_drv_data {\n\tint (*init)(struct platform_device *);\n\tconst struct sdhci_pltfm_data pltfm_data;\n};\n\nstruct sdhci_cdns_phy_cfg {\n\tconst char *property;\n\tu8 addr;\n};\n\nstruct sdhci_cdns_phy_param {\n\tu8 addr;\n\tu8 data;\n};\n\nstruct sdhci_cdns_priv {\n\tvoid *hrs_addr;\n\tvoid *ctl_addr;\n\tspinlock_t wrlock;\n\tbool enhanced_strobe;\n\tvoid (*priv_writel)(struct sdhci_cdns_priv *, u32, void *);\n\tstruct reset_control *rst_hw;\n\tunsigned int nr_phy_params;\n\tstruct sdhci_cdns_phy_param phy_params[0];\n};\n\nstruct sdhci_esdhc {\n\tu8 vendor_ver;\n\tu8 spec_ver;\n\tbool quirk_incorrect_hostver;\n\tbool quirk_limited_clk_division;\n\tbool quirk_unreliable_pulse_detection;\n\tbool quirk_tuning_erratum_type1;\n\tbool quirk_tuning_erratum_type2;\n\tbool quirk_ignore_data_inhibit;\n\tbool quirk_delay_before_data_reset;\n\tbool quirk_trans_complete_erratum;\n\tbool in_sw_tuning;\n\tunsigned int peripheral_clock;\n\tconst struct esdhc_clk_fixup *clk_fixup;\n\tu32 div_ratio;\n};\n\nstruct sdhci_host {\n\tconst char *hw_name;\n\tunsigned int quirks;\n\tunsigned int quirks2;\n\tint irq;\n\tvoid *ioaddr;\n\tphys_addr_t mapbase;\n\tchar *bounce_buffer;\n\tdma_addr_t bounce_addr;\n\tunsigned int bounce_buffer_size;\n\tconst struct sdhci_ops *ops;\n\tstruct mmc_host *mmc;\n\tstruct mmc_host_ops mmc_host_ops;\n\tu64 dma_mask;\n\tstruct led_classdev led;\n\tchar led_name[32];\n\tspinlock_t lock;\n\tint flags;\n\tunsigned int version;\n\tunsigned int max_clk;\n\tunsigned int timeout_clk;\n\tu8 max_timeout_count;\n\tunsigned int clk_mul;\n\tunsigned int clock;\n\tu8 pwr;\n\tu8 drv_type;\n\tbool reinit_uhs;\n\tbool runtime_suspended;\n\tbool bus_on;\n\tbool preset_enabled;\n\tbool pending_reset;\n\tbool irq_wake_enabled;\n\tbool v4_mode;\n\tbool use_external_dma;\n\tbool always_defer_done;\n\tstruct mmc_request *mrqs_done[2];\n\tstruct mmc_command *cmd;\n\tstruct mmc_command *data_cmd;\n\tstruct mmc_command *deferred_cmd;\n\tstruct mmc_data *data;\n\tunsigned int data_early: 1;\n\tstruct sg_mapping_iter sg_miter;\n\tunsigned int blocks;\n\tint sg_count;\n\tint max_adma;\n\tvoid *adma_table;\n\tvoid *align_buffer;\n\tsize_t adma_table_sz;\n\tsize_t align_buffer_sz;\n\tdma_addr_t adma_addr;\n\tdma_addr_t align_addr;\n\tunsigned int desc_sz;\n\tunsigned int alloc_desc_sz;\n\tstruct workqueue_struct *complete_wq;\n\tstruct work_struct complete_work;\n\tstruct timer_list timer;\n\tstruct timer_list data_timer;\n\tvoid (*complete_work_fn)(struct work_struct *);\n\tirqreturn_t (*thread_irq_fn)(int, void *);\n\tu32 caps;\n\tu32 caps1;\n\tbool read_caps;\n\tbool sdhci_core_to_disable_vqmmc;\n\tunsigned int ocr_avail_sdio;\n\tunsigned int ocr_avail_sd;\n\tunsigned int ocr_avail_mmc;\n\tu32 ocr_mask;\n\tunsigned int timing;\n\tu32 thread_isr;\n\tu32 ier;\n\tbool cqe_on;\n\tu32 cqe_ier;\n\tu32 cqe_err_ier;\n\twait_queue_head_t buf_ready_int;\n\tunsigned int tuning_done;\n\tunsigned int tuning_count;\n\tunsigned int tuning_mode;\n\tunsigned int tuning_err;\n\tint tuning_delay;\n\tint tuning_loop_count;\n\tu32 sdma_boundary;\n\tu32 adma_table_cnt;\n\tu64 data_timeout;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct sdhci_iproc_data {\n\tconst struct sdhci_pltfm_data *pdata;\n\tu32 caps;\n\tu32 caps1;\n\tu32 mmc_caps;\n\tbool missing_caps;\n};\n\nstruct sdhci_iproc_host {\n\tconst struct sdhci_iproc_data *data;\n\tu32 shadow_cmd;\n\tu32 shadow_blk;\n\tbool is_cmd_shadowed;\n\tbool is_blk_shadowed;\n};\n\nstruct sdhci_msm_variant_ops;\n\nstruct sdhci_msm_offset;\n\nstruct sdhci_msm_host {\n\tstruct platform_device *pdev;\n\tvoid *core_mem;\n\tint pwr_irq;\n\tstruct clk *bus_clk;\n\tstruct clk *xo_clk;\n\tstruct clk_bulk_data bulk_clks[4];\n\tlong unsigned int clk_rate;\n\tstruct mmc_host *mmc;\n\tbool use_14lpp_dll_reset;\n\tbool tuning_done;\n\tbool calibration_done;\n\tu8 saved_tuning_phase;\n\tbool use_cdclp533;\n\tu32 curr_pwr_state;\n\tu32 curr_io_level;\n\twait_queue_head_t pwr_irq_wait;\n\tbool pwr_irq_flag;\n\tu32 caps_0;\n\tbool mci_removed;\n\tbool restore_dll_config;\n\tconst struct sdhci_msm_variant_ops *var_ops;\n\tconst struct sdhci_msm_offset *offset;\n\tbool use_cdr;\n\tu32 transfer_mode;\n\tbool updated_ddr_cfg;\n\tbool uses_tassadar_dll;\n\tu32 dll_config;\n\tu32 ddr_config;\n\tbool vqmmc_enabled;\n};\n\nstruct sdhci_msm_offset {\n\tu32 core_hc_mode;\n\tu32 core_mci_data_cnt;\n\tu32 core_mci_status;\n\tu32 core_mci_fifo_cnt;\n\tu32 core_mci_version;\n\tu32 core_generics;\n\tu32 core_testbus_config;\n\tu32 core_testbus_sel2_bit;\n\tu32 core_testbus_ena;\n\tu32 core_testbus_sel2;\n\tu32 core_pwrctl_status;\n\tu32 core_pwrctl_mask;\n\tu32 core_pwrctl_clear;\n\tu32 core_pwrctl_ctl;\n\tu32 core_sdcc_debug_reg;\n\tu32 core_dll_config;\n\tu32 core_dll_status;\n\tu32 core_vendor_spec;\n\tu32 core_vendor_spec_adma_err_addr0;\n\tu32 core_vendor_spec_adma_err_addr1;\n\tu32 core_vendor_spec_func2;\n\tu32 core_vendor_spec_capabilities0;\n\tu32 core_ddr_200_cfg;\n\tu32 core_vendor_spec3;\n\tu32 core_dll_config_2;\n\tu32 core_dll_config_3;\n\tu32 core_ddr_config_old;\n\tu32 core_ddr_config;\n\tu32 core_dll_usr_ctl;\n};\n\nstruct sdhci_msm_variant_info {\n\tbool mci_removed;\n\tbool restore_dll_config;\n\tconst struct sdhci_msm_variant_ops *var_ops;\n\tconst struct sdhci_msm_offset *offset;\n};\n\nstruct sdhci_msm_variant_ops {\n\tu32 (*msm_readl_relaxed)(struct sdhci_host *, u32);\n\tvoid (*msm_writel_relaxed)(u32, struct sdhci_host *, u32);\n};\n\nstruct sdhci_ops {\n\tu32 (*read_l)(struct sdhci_host *, int);\n\tu16 (*read_w)(struct sdhci_host *, int);\n\tu8 (*read_b)(struct sdhci_host *, int);\n\tvoid (*write_l)(struct sdhci_host *, u32, int);\n\tvoid (*write_w)(struct sdhci_host *, u16, int);\n\tvoid (*write_b)(struct sdhci_host *, u8, int);\n\tvoid (*set_clock)(struct sdhci_host *, unsigned int);\n\tvoid (*set_power)(struct sdhci_host *, unsigned char, short unsigned int);\n\tu32 (*irq)(struct sdhci_host *, u32);\n\tint (*set_dma_mask)(struct sdhci_host *);\n\tint (*enable_dma)(struct sdhci_host *);\n\tunsigned int (*get_max_clock)(struct sdhci_host *);\n\tunsigned int (*get_min_clock)(struct sdhci_host *);\n\tunsigned int (*get_timeout_clock)(struct sdhci_host *);\n\tunsigned int (*get_max_timeout_count)(struct sdhci_host *);\n\tvoid (*set_timeout)(struct sdhci_host *, struct mmc_command *);\n\tvoid (*set_bus_width)(struct sdhci_host *, int);\n\tvoid (*platform_send_init_74_clocks)(struct sdhci_host *, u8);\n\tunsigned int (*get_ro)(struct sdhci_host *);\n\tvoid (*reset)(struct sdhci_host *, u8);\n\tint (*platform_execute_tuning)(struct sdhci_host *, u32);\n\tvoid (*set_uhs_signaling)(struct sdhci_host *, unsigned int);\n\tvoid (*hw_reset)(struct sdhci_host *);\n\tvoid (*adma_workaround)(struct sdhci_host *, u32);\n\tvoid (*card_event)(struct sdhci_host *);\n\tvoid (*voltage_switch)(struct sdhci_host *);\n\tvoid (*adma_write_desc)(struct sdhci_host *, void **, dma_addr_t, int, unsigned int);\n\tvoid (*copy_to_bounce_buffer)(struct sdhci_host *, struct mmc_data *, unsigned int);\n\tvoid (*request_done)(struct sdhci_host *, struct mmc_request *);\n\tvoid (*dump_vendor_regs)(struct sdhci_host *);\n\tvoid (*dump_uhs2_regs)(struct sdhci_host *);\n\tvoid (*uhs2_pre_detect_init)(struct sdhci_host *);\n};\n\nstruct sdhci_pltfm_host {\n\tstruct clk *clk;\n\tunsigned int clock;\n\tu16 xfer_mode_shadow;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct sdhci_sparx5_data {\n\tstruct sdhci_host *host;\n\tstruct regmap *cpu_ctrl;\n\tint delay_clock;\n};\n\nstruct sdhci_tegra_autocal_offsets {\n\tu32 pull_up_3v3;\n\tu32 pull_down_3v3;\n\tu32 pull_up_3v3_timeout;\n\tu32 pull_down_3v3_timeout;\n\tu32 pull_up_1v8;\n\tu32 pull_down_1v8;\n\tu32 pull_up_1v8_timeout;\n\tu32 pull_down_1v8_timeout;\n\tu32 pull_up_sdr104;\n\tu32 pull_down_sdr104;\n\tu32 pull_up_hs400;\n\tu32 pull_down_hs400;\n};\n\nstruct sdhci_tegra_soc_data;\n\nstruct sdhci_tegra {\n\tconst struct sdhci_tegra_soc_data *soc_data;\n\tstruct gpio_desc *power_gpio;\n\tstruct clk *tmclk;\n\tbool ddr_signaling;\n\tbool pad_calib_required;\n\tbool pad_control_available;\n\tstruct reset_control *rst;\n\tstruct pinctrl *pinctrl_sdmmc;\n\tstruct pinctrl_state *pinctrl_state_3v3;\n\tstruct pinctrl_state *pinctrl_state_1v8;\n\tstruct pinctrl_state *pinctrl_state_3v3_drv;\n\tstruct pinctrl_state *pinctrl_state_1v8_drv;\n\tstruct sdhci_tegra_autocal_offsets autocal_offsets;\n\tktime_t last_calib;\n\tu32 default_tap;\n\tu32 default_trim;\n\tu32 dqs_trim;\n\tbool enable_hwcq;\n\tlong unsigned int curr_clk_rate;\n\tu8 tuned_tap_delay;\n\tu32 stream_id;\n};\n\nstruct sdhci_tegra_soc_data {\n\tconst struct sdhci_pltfm_data *pdata;\n\tu64 dma_mask;\n\tu32 nvquirks;\n\tu8 min_tap_delay;\n\tu8 max_tap_delay;\n};\n\nstruct sdio_device_id {\n\t__u8 class;\n\t__u16 vendor;\n\t__u16 device;\n\tkernel_ulong_t driver_data;\n};\n\nstruct sdio_driver {\n\tchar *name;\n\tconst struct sdio_device_id *id_table;\n\tint (*probe)(struct sdio_func *, const struct sdio_device_id *);\n\tvoid (*remove)(struct sdio_func *);\n\tvoid (*shutdown)(struct sdio_func *);\n\tstruct device_driver drv;\n};\n\ntypedef void sdio_irq_handler_t(struct sdio_func *);\n\nstruct sdio_func {\n\tstruct mmc_card *card;\n\tstruct device dev;\n\tsdio_irq_handler_t *irq_handler;\n\tunsigned int num;\n\tunsigned char class;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tunsigned int max_blksize;\n\tunsigned int cur_blksize;\n\tunsigned int enable_timeout;\n\tunsigned int state;\n\tu8 *tmpbuf;\n\tu8 major_rev;\n\tu8 minor_rev;\n\tunsigned int num_info;\n\tconst char **info;\n\tstruct sdio_func_tuple *tuples;\n};\n\nstruct sdio_func_tuple {\n\tstruct sdio_func_tuple *next;\n\tunsigned char code;\n\tunsigned char size;\n\tunsigned char data[0];\n};\n\nstruct sdmmc_tuning_ops;\n\nstruct sdmmc_dlyb {\n\tvoid *base;\n\tu32 unit;\n\tu32 max;\n\tstruct sdmmc_tuning_ops *ops;\n};\n\nstruct sdmmc_idma {\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tdma_addr_t bounce_dma_addr;\n\tvoid *bounce_buf;\n\tbool use_bounce_buffer;\n};\n\nstruct sdmmc_lli_desc {\n\tu32 idmalar;\n\tu32 idmabase;\n\tu32 idmasize;\n};\n\nstruct sdmmc_tuning_ops {\n\tint (*dlyb_enable)(struct sdmmc_dlyb *);\n\tvoid (*set_input_ck)(struct sdmmc_dlyb *);\n\tint (*tuning_prepare)(struct mmci_host *);\n\tint (*set_cfg)(struct sdmmc_dlyb *, int, int, bool);\n};\n\nstruct se_fw_hdr {\n\t__le32 magic;\n\t__le32 version;\n\t__le32 core_version;\n\t__le16 serial_protocol;\n\t__le16 fw_version;\n\t__le16 cfg_version;\n\t__le16 fw_size_in_items;\n\t__le16 fw_offset;\n\t__le16 cfg_size_in_items;\n\t__le16 cfg_idx_offset;\n\t__le16 cfg_val_offset;\n};\n\nstruct sec_opmode_data {\n\tint id;\n\tunsigned int mode;\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct xfrm_state;\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct sec_regulator_data;\n\nstruct sec_platform_data {\n\tstruct sec_regulator_data *regulators;\n\tstruct sec_opmode_data *opmode;\n\tint num_regulators;\n\tint buck_gpios[3];\n\tint buck_ds[3];\n\tunsigned int buck2_voltage[8];\n\tbool buck2_gpiodvs;\n\tunsigned int buck3_voltage[8];\n\tbool buck3_gpiodvs;\n\tunsigned int buck4_voltage[8];\n\tbool buck4_gpiodvs;\n\tint buck_default_idx;\n\tint buck_ramp_delay;\n\tbool buck2_ramp_enable;\n\tbool buck3_ramp_enable;\n\tbool buck4_ramp_enable;\n\tint buck2_init;\n\tint buck3_init;\n\tint buck4_init;\n\tbool manual_poweroff;\n\tbool disable_wrstbi;\n};\n\nstruct sec_pmic_dev {\n\tstruct device *dev;\n\tstruct sec_platform_data *pdata;\n\tstruct regmap *regmap_pmic;\n\tstruct i2c_client *i2c;\n\tint device_type;\n\tint irq;\n};\n\nstruct sec_pmic_i2c_platform_data {\n\tconst struct regmap_config *regmap_cfg;\n\tint device_type;\n};\n\nstruct sec_regulator_data {\n\tint id;\n\tstruct regulator_init_data *initdata;\n\tstruct device_node *reg_node;\n\tstruct gpio_desc *ext_control_gpiod;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct secondary_data {\n\tstruct task_struct *task;\n\tlong int status;\n};\n\nstruct timezone;\n\nstruct xattr;\n\nstruct sembuf;\n\nunion security_list_options {\n\tint (*binder_set_context_mgr)(const struct cred *);\n\tint (*binder_transaction)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_binder)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_file)(const struct cred *, const struct cred *, const struct file *);\n\tint (*ptrace_access_check)(struct task_struct *, unsigned int);\n\tint (*ptrace_traceme)(struct task_struct *);\n\tint (*capget)(const struct task_struct *, kernel_cap_t *, kernel_cap_t *, kernel_cap_t *);\n\tint (*capset)(struct cred *, const struct cred *, const kernel_cap_t *, const kernel_cap_t *, const kernel_cap_t *);\n\tint (*capable)(const struct cred *, struct user_namespace *, int, unsigned int);\n\tint (*quotactl)(int, int, int, const struct super_block *);\n\tint (*quota_on)(struct dentry *);\n\tint (*syslog)(int);\n\tint (*settime)(const struct timespec64 *, const struct timezone *);\n\tint (*vm_enough_memory)(struct mm_struct *, long int);\n\tint (*bprm_creds_for_exec)(struct linux_binprm *);\n\tint (*bprm_creds_from_file)(struct linux_binprm *, const struct file *);\n\tint (*bprm_check_security)(struct linux_binprm *);\n\tvoid (*bprm_committing_creds)(const struct linux_binprm *);\n\tvoid (*bprm_committed_creds)(const struct linux_binprm *);\n\tint (*fs_context_submount)(struct fs_context *, struct super_block *);\n\tint (*fs_context_dup)(struct fs_context *, struct fs_context *);\n\tint (*fs_context_parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*sb_alloc_security)(struct super_block *);\n\tvoid (*sb_delete)(struct super_block *);\n\tvoid (*sb_free_security)(struct super_block *);\n\tvoid (*sb_free_mnt_opts)(void *);\n\tint (*sb_eat_lsm_opts)(char *, void **);\n\tint (*sb_mnt_opts_compat)(struct super_block *, void *);\n\tint (*sb_remount)(struct super_block *, void *);\n\tint (*sb_kern_mount)(const struct super_block *);\n\tint (*sb_show_options)(struct seq_file *, struct super_block *);\n\tint (*sb_statfs)(struct dentry *);\n\tint (*sb_mount)(const char *, const struct path *, const char *, long unsigned int, void *);\n\tint (*sb_umount)(struct vfsmount *, int);\n\tint (*sb_pivotroot)(const struct path *, const struct path *);\n\tint (*sb_set_mnt_opts)(struct super_block *, void *, long unsigned int, long unsigned int *);\n\tint (*sb_clone_mnt_opts)(const struct super_block *, struct super_block *, long unsigned int, long unsigned int *);\n\tint (*move_mount)(const struct path *, const struct path *);\n\tint (*dentry_init_security)(struct dentry *, int, const struct qstr *, const char **, struct lsm_context *);\n\tint (*dentry_create_files_as)(struct dentry *, int, const struct qstr *, const struct cred *, struct cred *);\n\tint (*path_notify)(const struct path *, u64, unsigned int);\n\tint (*inode_alloc_security)(struct inode *);\n\tvoid (*inode_free_security)(struct inode *);\n\tvoid (*inode_free_security_rcu)(void *);\n\tint (*inode_init_security)(struct inode *, struct inode *, const struct qstr *, struct xattr *, int *);\n\tint (*inode_init_security_anon)(struct inode *, const struct qstr *, const struct inode *);\n\tint (*inode_create)(struct inode *, struct dentry *, umode_t);\n\tvoid (*inode_post_create_tmpfile)(struct mnt_idmap *, struct inode *);\n\tint (*inode_link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_unlink)(struct inode *, struct dentry *);\n\tint (*inode_symlink)(struct inode *, struct dentry *, const char *);\n\tint (*inode_mkdir)(struct inode *, struct dentry *, umode_t);\n\tint (*inode_rmdir)(struct inode *, struct dentry *);\n\tint (*inode_mknod)(struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*inode_rename)(struct inode *, struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_readlink)(struct dentry *);\n\tint (*inode_follow_link)(struct dentry *, struct inode *, bool);\n\tint (*inode_permission)(struct inode *, int);\n\tint (*inode_setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tvoid (*inode_post_setattr)(struct mnt_idmap *, struct dentry *, int);\n\tint (*inode_getattr)(const struct path *);\n\tint (*inode_xattr_skipcap)(const char *);\n\tint (*inode_setxattr)(struct mnt_idmap *, struct dentry *, const char *, const void *, size_t, int);\n\tvoid (*inode_post_setxattr)(struct dentry *, const char *, const void *, size_t, int);\n\tint (*inode_getxattr)(struct dentry *, const char *);\n\tint (*inode_listxattr)(struct dentry *);\n\tint (*inode_removexattr)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_removexattr)(struct dentry *, const char *);\n\tint (*inode_file_setattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_file_getattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_set_acl)(struct mnt_idmap *, struct dentry *, const char *, struct posix_acl *);\n\tvoid (*inode_post_set_acl)(struct dentry *, const char *, struct posix_acl *);\n\tint (*inode_get_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_need_killpriv)(struct dentry *);\n\tint (*inode_killpriv)(struct mnt_idmap *, struct dentry *);\n\tint (*inode_getsecurity)(struct mnt_idmap *, struct inode *, const char *, void **, bool);\n\tint (*inode_setsecurity)(struct inode *, const char *, const void *, size_t, int);\n\tint (*inode_listsecurity)(struct inode *, char *, size_t);\n\tvoid (*inode_getlsmprop)(struct inode *, struct lsm_prop *);\n\tint (*inode_copy_up)(struct dentry *, struct cred **);\n\tint (*inode_copy_up_xattr)(struct dentry *, const char *);\n\tint (*inode_setintegrity)(const struct inode *, enum lsm_integrity_type, const void *, size_t);\n\tint (*kernfs_init_security)(struct kernfs_node *, struct kernfs_node *);\n\tint (*file_permission)(struct file *, int);\n\tint (*file_alloc_security)(struct file *);\n\tvoid (*file_release)(struct file *);\n\tvoid (*file_free_security)(struct file *);\n\tint (*file_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*file_ioctl_compat)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap_addr)(long unsigned int);\n\tint (*mmap_file)(struct file *, long unsigned int, long unsigned int, long unsigned int);\n\tint (*file_mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int);\n\tint (*file_lock)(struct file *, unsigned int);\n\tint (*file_fcntl)(struct file *, unsigned int, long unsigned int);\n\tvoid (*file_set_fowner)(struct file *);\n\tint (*file_send_sigiotask)(struct task_struct *, struct fown_struct *, int);\n\tint (*file_receive)(struct file *);\n\tint (*file_open)(struct file *);\n\tint (*file_post_open)(struct file *, int);\n\tint (*file_truncate)(struct file *);\n\tint (*task_alloc)(struct task_struct *, u64);\n\tvoid (*task_free)(struct task_struct *);\n\tint (*cred_alloc_blank)(struct cred *, gfp_t);\n\tvoid (*cred_free)(struct cred *);\n\tint (*cred_prepare)(struct cred *, const struct cred *, gfp_t);\n\tvoid (*cred_transfer)(struct cred *, const struct cred *);\n\tvoid (*cred_getsecid)(const struct cred *, u32 *);\n\tvoid (*cred_getlsmprop)(const struct cred *, struct lsm_prop *);\n\tint (*kernel_act_as)(struct cred *, u32);\n\tint (*kernel_create_files_as)(struct cred *, struct inode *);\n\tint (*kernel_module_request)(char *);\n\tint (*kernel_load_data)(enum kernel_load_data_id, bool);\n\tint (*kernel_post_load_data)(char *, loff_t, enum kernel_load_data_id, char *);\n\tint (*kernel_read_file)(struct file *, enum kernel_read_file_id, bool);\n\tint (*kernel_post_read_file)(struct file *, char *, loff_t, enum kernel_read_file_id);\n\tint (*task_fix_setuid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgroups)(struct cred *, const struct cred *);\n\tint (*task_setpgid)(struct task_struct *, pid_t);\n\tint (*task_getpgid)(struct task_struct *);\n\tint (*task_getsid)(struct task_struct *);\n\tvoid (*current_getlsmprop_subj)(struct lsm_prop *);\n\tvoid (*task_getlsmprop_obj)(struct task_struct *, struct lsm_prop *);\n\tint (*task_setnice)(struct task_struct *, int);\n\tint (*task_setioprio)(struct task_struct *, int);\n\tint (*task_getioprio)(struct task_struct *);\n\tint (*task_prlimit)(const struct cred *, const struct cred *, unsigned int);\n\tint (*task_setrlimit)(struct task_struct *, unsigned int, struct rlimit *);\n\tint (*task_setscheduler)(struct task_struct *);\n\tint (*task_getscheduler)(struct task_struct *);\n\tint (*task_movememory)(struct task_struct *);\n\tint (*task_kill)(struct task_struct *, struct kernel_siginfo *, int, const struct cred *);\n\tint (*task_prctl)(int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tvoid (*task_to_inode)(struct task_struct *, struct inode *);\n\tint (*userns_create)(const struct cred *);\n\tint (*ipc_permission)(struct kern_ipc_perm *, short int);\n\tvoid (*ipc_getlsmprop)(struct kern_ipc_perm *, struct lsm_prop *);\n\tint (*msg_msg_alloc_security)(struct msg_msg *);\n\tvoid (*msg_msg_free_security)(struct msg_msg *);\n\tint (*msg_queue_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*msg_queue_free_security)(struct kern_ipc_perm *);\n\tint (*msg_queue_associate)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgctl)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgsnd)(struct kern_ipc_perm *, struct msg_msg *, int);\n\tint (*msg_queue_msgrcv)(struct kern_ipc_perm *, struct msg_msg *, struct task_struct *, long int, int);\n\tint (*shm_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*shm_free_security)(struct kern_ipc_perm *);\n\tint (*shm_associate)(struct kern_ipc_perm *, int);\n\tint (*shm_shmctl)(struct kern_ipc_perm *, int);\n\tint (*shm_shmat)(struct kern_ipc_perm *, char *, int);\n\tint (*sem_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*sem_free_security)(struct kern_ipc_perm *);\n\tint (*sem_associate)(struct kern_ipc_perm *, int);\n\tint (*sem_semctl)(struct kern_ipc_perm *, int);\n\tint (*sem_semop)(struct kern_ipc_perm *, struct sembuf *, unsigned int, int);\n\tint (*netlink_send)(struct sock *, struct sk_buff *);\n\tvoid (*d_instantiate)(struct dentry *, struct inode *);\n\tint (*getselfattr)(unsigned int, struct lsm_ctx *, u32 *, u32);\n\tint (*setselfattr)(unsigned int, struct lsm_ctx *, u32, u32);\n\tint (*getprocattr)(struct task_struct *, const char *, char **);\n\tint (*setprocattr)(const char *, void *, size_t);\n\tint (*ismaclabel)(const char *);\n\tint (*secid_to_secctx)(u32, struct lsm_context *);\n\tint (*lsmprop_to_secctx)(struct lsm_prop *, struct lsm_context *);\n\tint (*secctx_to_secid)(const char *, u32, u32 *);\n\tvoid (*release_secctx)(struct lsm_context *);\n\tvoid (*inode_invalidate_secctx)(struct inode *);\n\tint (*inode_notifysecctx)(struct inode *, void *, u32);\n\tint (*inode_setsecctx)(struct dentry *, void *, u32);\n\tint (*inode_getsecctx)(struct inode *, struct lsm_context *);\n\tint (*key_alloc)(struct key *, const struct cred *, long unsigned int);\n\tint (*key_permission)(key_ref_t, const struct cred *, enum key_need_perm);\n\tint (*key_getsecurity)(struct key *, char **);\n\tvoid (*key_post_create_or_update)(struct key *, struct key *, const void *, size_t, long unsigned int, bool);\n\tint (*audit_rule_init)(u32, u32, char *, void **, gfp_t);\n\tint (*audit_rule_known)(struct audit_krule *);\n\tint (*audit_rule_match)(struct lsm_prop *, u32, u32, void *);\n\tvoid (*audit_rule_free)(void *);\n\tint (*bpf)(int, union bpf_attr *, unsigned int, bool);\n\tint (*bpf_map)(struct bpf_map *, fmode_t);\n\tint (*bpf_prog)(struct bpf_prog *);\n\tint (*bpf_map_create)(struct bpf_map *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_map_free)(struct bpf_map *);\n\tint (*bpf_prog_load)(struct bpf_prog *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_prog_free)(struct bpf_prog *);\n\tint (*bpf_token_create)(struct bpf_token *, union bpf_attr *, const struct path *);\n\tvoid (*bpf_token_free)(struct bpf_token *);\n\tint (*bpf_token_cmd)(const struct bpf_token *, enum bpf_cmd);\n\tint (*bpf_token_capable)(const struct bpf_token *, int);\n\tint (*locked_down)(enum lockdown_reason);\n\tint (*perf_event_open)(int);\n\tint (*perf_event_alloc)(struct perf_event *);\n\tint (*perf_event_read)(struct perf_event *);\n\tint (*perf_event_write)(struct perf_event *);\n\tint (*uring_override_creds)(const struct cred *);\n\tint (*uring_sqpoll)(void);\n\tint (*uring_cmd)(struct io_uring_cmd *);\n\tint (*uring_allowed)(void);\n\tvoid (*initramfs_populated)(void);\n\tint (*bdev_alloc_security)(struct block_device *);\n\tvoid (*bdev_free_security)(struct block_device *);\n\tint (*bdev_setintegrity)(struct block_device *, enum lsm_integrity_type, const void *, size_t);\n\tvoid *lsm_func_addr;\n};\n\nstruct security_hook_list {\n\tstruct lsm_static_call *scalls;\n\tunion security_list_options hook;\n\tconst struct lsm_id *lsmid;\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\ttime64_t sem_otime;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\tlong int sem_otime;\n\tlong int sem_ctime;\n\tlong unsigned int sem_nsems;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct virtnet_sq_stats {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tu64_stats_t xdp_tx;\n\tu64_stats_t xdp_tx_drops;\n\tu64_stats_t kicks;\n\tu64_stats_t tx_timeouts;\n\tu64_stats_t stop;\n\tu64_stats_t wake;\n};\n\nstruct send_queue {\n\tstruct virtqueue *vq;\n\tstruct scatterlist sg[19];\n\tchar name[16];\n\tstruct virtnet_sq_stats stats;\n\tstruct virtnet_interrupt_coalesce intr_coal;\n\tstruct napi_struct napi;\n\tbool reset;\n\tstruct xsk_buff_pool *xsk_pool;\n\tdma_addr_t xsk_hdr_dma_addr;\n};\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n\tbool has_siginfo;\n\tstruct kernel_siginfo info;\n};\n\nstruct sensor_data {\n\tunsigned int scale;\n\tstruct scpi_sensor_info info;\n\tstruct device_attribute dev_attr_input;\n\tstruct device_attribute dev_attr_label;\n\tchar input[20];\n\tchar label[20];\n};\n\nstruct sensors_info {\n\tbool notify_trip_point_cmd;\n\tbool notify_continuos_update_cmd;\n\tint num_sensors;\n\tint max_requests;\n\tu64 reg_addr;\n\tu32 reg_size;\n\tstruct scmi_sensor_info *sensors;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct seqbuf {\n\tchar *buf;\n\tsize_t pos;\n\tsize_t size;\n};\n\nstruct seqcount_rwlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_rwlock seqcount_rwlock_t;\n\nstruct serdev_device;\n\nstruct serdev_controller_ops;\n\nstruct serdev_controller {\n\tstruct device dev;\n\tstruct device *host;\n\tunsigned int nr;\n\tstruct serdev_device *serdev;\n\tconst struct serdev_controller_ops *ops;\n};\n\nstruct serdev_controller_ops {\n\tssize_t (*write_buf)(struct serdev_controller *, const u8 *, size_t);\n\tvoid (*write_flush)(struct serdev_controller *);\n\tint (*open)(struct serdev_controller *);\n\tvoid (*close)(struct serdev_controller *);\n\tvoid (*set_flow_control)(struct serdev_controller *, bool);\n\tint (*set_parity)(struct serdev_controller *, enum serdev_parity);\n\tunsigned int (*set_baudrate)(struct serdev_controller *, unsigned int);\n\tvoid (*wait_until_sent)(struct serdev_controller *, long int);\n\tint (*get_tiocm)(struct serdev_controller *);\n\tint (*set_tiocm)(struct serdev_controller *, unsigned int, unsigned int);\n\tint (*break_ctl)(struct serdev_controller *, unsigned int);\n};\n\nstruct serdev_device_ops;\n\nstruct serdev_device {\n\tstruct device dev;\n\tint nr;\n\tstruct serdev_controller *ctrl;\n\tconst struct serdev_device_ops *ops;\n\tstruct completion write_comp;\n\tstruct mutex write_lock;\n};\n\nstruct serdev_device_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct serdev_device *);\n\tvoid (*remove)(struct serdev_device *);\n\tvoid (*shutdown)(struct serdev_device *);\n};\n\nstruct serdev_device_ops {\n\tsize_t (*receive_buf)(struct serdev_device *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct serdev_device *);\n};\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct serial8250_em_priv {\n\tint line;\n};\n\nstruct serial_ctrl_device {\n\tstruct device dev;\n\tstruct ida port_ida;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_port_device {\n\tstruct device dev;\n\tstruct uart_port *port;\n\tunsigned int tx_enabled: 1;\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\nstruct serial_struct32 {\n\tcompat_int_t type;\n\tcompat_int_t line;\n\tcompat_uint_t port;\n\tcompat_int_t irq;\n\tcompat_int_t flags;\n\tcompat_int_t xmit_fifo_size;\n\tcompat_int_t custom_divisor;\n\tcompat_int_t baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char;\n\tcompat_int_t hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tcompat_uint_t iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tcompat_int_t reserved;\n};\n\ntypedef struct serio *class_serio_pause_rx_t;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nstruct serport {\n\tstruct tty_port *port;\n\tstruct tty_struct *tty;\n\tstruct tty_driver *tty_drv;\n\tint tty_idx;\n\tlong unsigned int flags;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_config_request {\n\tstruct usb_device *udev;\n\tint config;\n\tstruct work_struct work;\n\tstruct list_head node;\n};\n\nstruct set_error_type_with_address {\n\tu32 type;\n\tu32 vendor_extension;\n\tu32 flags;\n\tu32 apicid;\n\tu64 memory_address;\n\tu64 memory_address_range;\n\tu32 pcie_sbdf;\n\tstruct einjv2_extension_struct einjv2_struct;\n};\n\nstruct set_event_iter {\n\tenum set_event_iter_type type;\n\tunion {\n\t\tstruct trace_event_file *file;\n\t\tstruct event_mod_load *event_mod;\n\t};\n};\n\nstruct set_perm_data {\n\tconst efi_memory_desc_t *md;\n\tbool has_bti;\n};\n\nstruct setup_rw_req {\n\tunsigned int grant_idx;\n\tstruct blkif_request_segment *segments;\n\tstruct blkfront_ring_info *rinfo;\n\tstruct blkif_request *ring_req;\n\tgrant_ref_t gref_head;\n\tunsigned int id;\n\tbool need_copy;\n\tunsigned int bvec_off;\n\tchar *bvec_data;\n\tbool require_extra_req;\n\tstruct blkif_request *extra_ring_req;\n};\n\nstruct sfdp {\n\tsize_t num_dwords;\n\tu32 *dwords;\n};\n\nstruct sfdp_4bait {\n\tu32 hwcaps;\n\tu32 supported_bit;\n};\n\nstruct sfdp_bfpt {\n\tu32 dwords[20];\n};\n\nstruct sfdp_bfpt_erase {\n\tu32 dword;\n\tu32 shift;\n};\n\nstruct sfdp_bfpt_read {\n\tu32 hwcaps;\n\tu32 supported_dword;\n\tu32 supported_bit;\n\tu32 settings_dword;\n\tu32 settings_shift;\n\tenum spi_nor_protocol proto;\n};\n\nstruct sfdp_parameter_header {\n\tu8 id_lsb;\n\tu8 minor;\n\tu8 major;\n\tu8 length;\n\tu8 parameter_table_pointer[3];\n\tu8 id_msb;\n};\n\nstruct sfdp_header {\n\tu32 signature;\n\tu8 minor;\n\tu8 major;\n\tu8 nph;\n\tu8 unused;\n\tstruct sfdp_parameter_header bfpt_header;\n};\n\nstruct sfi_counter_data {\n\tu32 matchl;\n\tu32 matchh;\n\tu32 msdu_dropl;\n\tu32 msdu_droph;\n\tu32 stream_gate_dropl;\n\tu32 stream_gate_droph;\n\tu32 flow_meter_dropl;\n\tu32 flow_meter_droph;\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_module_caps {\n\tlong unsigned int interfaces[1];\n\tlong unsigned int link_modes[2];\n\tbool may_have_phy;\n\tu8 port;\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *, struct phy_device *);\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_desc {\n\t__le32 total_len;\n\t__le32 resvd0;\n\t__le32 linear_addr;\n\t__le32 linear_len;\n\tstruct frags_info frags[18];\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_list {\n\tunsigned int n;\n\tunsigned int size;\n\tsize_t len;\n\tstruct scatterlist *sg;\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sg_splitter {\n\tstruct scatterlist *in_sg0;\n\tint nents;\n\toff_t skip_sg0;\n\tunsigned int length_last_sg;\n\tstruct scatterlist *out_sg;\n};\n\nstruct sgce {\n\tu32 interval;\n\tu8 msdu[3];\n\tu8 multi;\n};\n\nstruct sgcl_data {\n\tu32 btl;\n\tu32 bth;\n\tu32 ct;\n\tu32 cte;\n\tstruct sgce sgcl[0];\n};\n\nstruct sh_cmt_device;\n\nstruct sh_cmt_channel {\n\tstruct sh_cmt_device *cmt;\n\tunsigned int index;\n\tunsigned int hwidx;\n\tvoid *iostart;\n\tvoid *ioctrl;\n\tunsigned int timer_bit;\n\tlong unsigned int flags;\n\tu32 match_value;\n\tu32 next_match_value;\n\tu32 max_match_value;\n\traw_spinlock_t lock;\n\tstruct clock_event_device ced;\n\tstruct clocksource cs;\n\tu64 total_cycles;\n\tbool cs_enabled;\n\tlong: 64;\n};\n\nstruct sh_cmt_info;\n\nstruct sh_cmt_device {\n\tstruct platform_device *pdev;\n\tconst struct sh_cmt_info *info;\n\tvoid *mapbase;\n\tstruct clk *clk;\n\tlong unsigned int rate;\n\tunsigned int reg_delay;\n\traw_spinlock_t lock;\n\tstruct sh_cmt_channel *channels;\n\tunsigned int num_channels;\n\tunsigned int hw_channels;\n\tbool has_clockevent;\n\tbool has_clocksource;\n};\n\nstruct sh_cmt_info {\n\tenum sh_cmt_model model;\n\tunsigned int channels_mask;\n\tlong unsigned int width;\n\tu32 overflow_bit;\n\tu32 clear_bits;\n\tu32 (*read_control)(void *, long unsigned int);\n\tvoid (*write_control)(void *, long unsigned int, u32);\n\tu32 (*read_count)(void *, long unsigned int);\n\tvoid (*write_count)(void *, long unsigned int, u32);\n};\n\nstruct sh_eth_cpu_data {\n\tint (*soft_reset)(struct net_device *);\n\tvoid (*chip_reset)(struct net_device *);\n\tvoid (*set_duplex)(struct net_device *);\n\tvoid (*set_rate)(struct net_device *);\n\tint register_type;\n\tu32 edtrr_trns;\n\tu32 eesipr_value;\n\tu32 ecsr_value;\n\tu32 ecsipr_value;\n\tu32 fdr_value;\n\tu32 fcftr_value;\n\tu32 tx_check;\n\tu32 eesr_err_check;\n\tu32 trscer_err_mask;\n\tlong unsigned int irq_flags;\n\tunsigned int no_psr: 1;\n\tunsigned int apr: 1;\n\tunsigned int mpr: 1;\n\tunsigned int tpauser: 1;\n\tunsigned int gecmr: 1;\n\tunsigned int bculr: 1;\n\tunsigned int tsu: 1;\n\tunsigned int hw_swap: 1;\n\tunsigned int nbst: 1;\n\tunsigned int rpadir: 1;\n\tunsigned int no_trimd: 1;\n\tunsigned int no_ade: 1;\n\tunsigned int no_xdfar: 1;\n\tunsigned int xdfar_rw: 1;\n\tunsigned int csmr: 1;\n\tunsigned int rx_csum: 1;\n\tunsigned int select_mii: 1;\n\tunsigned int rmiimode: 1;\n\tunsigned int rtrate: 1;\n\tunsigned int magic: 1;\n\tunsigned int no_tx_cntrs: 1;\n\tunsigned int cexcr: 1;\n\tunsigned int dual_port: 1;\n};\n\nstruct sh_eth_plat_data {\n\tint phy;\n\tint phy_irq;\n\tphy_interface_t phy_interface;\n\tvoid (*set_mdio_gate)(void *);\n\tunsigned char mac_addr[6];\n\tunsigned int no_ether_link: 1;\n\tunsigned int ether_link_active_low: 1;\n};\n\nstruct sh_eth_rxdesc;\n\nstruct sh_eth_txdesc;\n\nstruct sh_eth_private {\n\tstruct platform_device *pdev;\n\tstruct sh_eth_cpu_data *cd;\n\tconst u16 *reg_offset;\n\tvoid *addr;\n\tvoid *tsu_addr;\n\tstruct clk *clk;\n\tu32 num_rx_ring;\n\tu32 num_tx_ring;\n\tdma_addr_t rx_desc_dma;\n\tdma_addr_t tx_desc_dma;\n\tstruct sh_eth_rxdesc *rx_ring;\n\tstruct sh_eth_txdesc *tx_ring;\n\tstruct sk_buff **rx_skbuff;\n\tstruct sk_buff **tx_skbuff;\n\tspinlock_t lock;\n\tu32 cur_rx;\n\tu32 dirty_rx;\n\tu32 cur_tx;\n\tu32 dirty_tx;\n\tu32 rx_buf_sz;\n\tstruct napi_struct napi;\n\tbool irq_enabled;\n\tu32 phy_id;\n\tstruct mii_bus *mii_bus;\n\tint link;\n\tphy_interface_t phy_interface;\n\tint msg_enable;\n\tint speed;\n\tint duplex;\n\tint port;\n\tint vlan_num_ids;\n\tunsigned int no_ether_link: 1;\n\tunsigned int ether_link_active_low: 1;\n\tunsigned int is_opened: 1;\n\tunsigned int wol_enabled: 1;\n};\n\nstruct sh_eth_rxdesc {\n\tu32 status;\n\tu32 len;\n\tu32 addr;\n\tu32 pad0;\n};\n\nstruct sh_eth_txdesc {\n\tu32 status;\n\tu32 len;\n\tu32 addr;\n\tu32 pad0;\n};\n\nstruct sh_mobile_i2c_data;\n\nstruct sh_mobile_dt_config {\n\tint clks_per_count;\n\tint (*setup)(struct sh_mobile_i2c_data *);\n};\n\nstruct sh_mobile_i2c_data {\n\tstruct device *dev;\n\tvoid *reg;\n\tstruct i2c_adapter adap;\n\tlong unsigned int bus_speed;\n\tunsigned int clks_per_count;\n\tstruct clk *clk;\n\tu_int8_t icic;\n\tu_int8_t flags;\n\tu_int16_t iccl;\n\tu_int16_t icch;\n\tspinlock_t lock;\n\twait_queue_head_t wait;\n\tstruct i2c_msg *msg;\n\tint pos;\n\tint sr;\n\tbool send_stop;\n\tbool stop_after_dma;\n\tbool atomic_xfer;\n\tstruct resource *res;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tstruct scatterlist sg;\n\tenum dma_data_direction dma_direction;\n\tu8 *dma_buf;\n};\n\nstruct sh_pfc_chip;\n\nstruct sh_pfc_soc_info;\n\nstruct sh_pfc_window;\n\nstruct sh_pfc_pin_range;\n\nstruct sh_pfc {\n\tstruct device *dev;\n\tconst struct sh_pfc_soc_info *info;\n\tspinlock_t lock;\n\tunsigned int num_windows;\n\tstruct sh_pfc_window *windows;\n\tunsigned int num_irqs;\n\tunsigned int *irqs;\n\tstruct sh_pfc_pin_range *ranges;\n\tunsigned int nr_ranges;\n\tunsigned int nr_gpio_pins;\n\tstruct sh_pfc_chip *gpio;\n\tu32 *saved_regs;\n};\n\nstruct sh_pfc_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int nr_groups;\n};\n\nstruct sh_pfc_pin {\n\tconst char *name;\n\tunsigned int configs;\n\tu16 pin;\n\tu16 enum_id;\n};\n\nstruct sh_pfc_pin_config {\n\tu16 gpio_enabled: 1;\n\tu16 mux_mark: 15;\n};\n\nstruct sh_pfc_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tconst unsigned int *mux;\n\tunsigned int nr_pins;\n};\n\nstruct sh_pfc_pin_range {\n\tu16 start;\n\tu16 end;\n};\n\nstruct sh_pfc_pinctrl {\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct sh_pfc *pfc;\n\tstruct pinctrl_pin_desc *pins;\n\tstruct sh_pfc_pin_config *configs;\n};\n\nstruct sh_pfc_soc_operations;\n\nstruct sh_pfc_soc_info {\n\tconst char *name;\n\tconst struct sh_pfc_soc_operations *ops;\n\tstruct pinmux_range function;\n\tconst struct sh_pfc_pin *pins;\n\tunsigned int nr_pins;\n\tconst struct sh_pfc_pin_group *groups;\n\tunsigned int nr_groups;\n\tconst struct sh_pfc_function *functions;\n\tunsigned int nr_functions;\n\tconst struct pinmux_cfg_reg *cfg_regs;\n\tconst struct pinmux_drive_reg *drive_regs;\n\tconst struct pinmux_bias_reg *bias_regs;\n\tconst struct pinmux_ioctrl_reg *ioctrl_regs;\n\tconst struct pinmux_data_reg *data_regs;\n\tconst u16 *pinmux_data;\n\tunsigned int pinmux_data_size;\n\tu32 unlock_reg;\n};\n\nstruct sh_pfc_soc_operations {\n\tint (*init)(struct sh_pfc *);\n\tunsigned int (*get_bias)(struct sh_pfc *, unsigned int);\n\tvoid (*set_bias)(struct sh_pfc *, unsigned int, unsigned int);\n\tint (*pin_to_pocctrl)(unsigned int, u32 *);\n\tint (*pin_to_portcr)(unsigned int);\n};\n\nstruct sh_pfc_window {\n\tphys_addr_t phys;\n\tvoid *virt;\n\tlong unsigned int size;\n};\n\nstruct sh_timer_config {\n\tunsigned int channels_mask;\n};\n\nstruct sh_tmu_device;\n\nstruct sh_tmu_channel {\n\tstruct sh_tmu_device *tmu;\n\tunsigned int index;\n\tvoid *base;\n\tint irq;\n\tlong unsigned int periodic;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct clock_event_device ced;\n\tstruct clocksource cs;\n\tbool cs_enabled;\n\tunsigned int enable_count;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sh_tmu_device {\n\tstruct platform_device *pdev;\n\tvoid *mapbase;\n\tstruct clk *clk;\n\tlong unsigned int rate;\n\tenum sh_tmu_model model;\n\traw_spinlock_t lock;\n\tstruct sh_tmu_channel *channels;\n\tunsigned int num_channels;\n\tbool has_clockevent;\n\tbool has_clocksource;\n};\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha384_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct sha3_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct sha512_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct shadow_if {\n\tstruct vgic_v3_cpu_if cpuif;\n\tlong unsigned int lr_map;\n};\n\nstruct shake_ctx {\n\tstruct __sha3_ctx ctx;\n};\n\nstruct vcpu_info {\n\tuint8_t evtchn_upcall_pending;\n\tuint8_t evtchn_upcall_mask;\n\txen_ulong_t evtchn_pending_sel;\n\tstruct arch_vcpu_info arch;\n\tstruct pvclock_vcpu_time_info time;\n};\n\nstruct shared_info {\n\tstruct vcpu_info vcpu_info[1];\n\txen_ulong_t evtchn_pending[64];\n\txen_ulong_t evtchn_mask[64];\n\tstruct pvclock_wall_clock wc;\n\tuint32_t wc_sec_hi;\n\tstruct arch_shared_info arch;\n};\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*export_core)(struct shash_desc *, void *);\n\tint (*import_core)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tint (*clone_tfm)(struct crypto_shash *, struct crypto_shash *);\n\tunsigned int descsize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int digestsize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct hash_alg_common halg;\n\t};\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[120];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\t__kernel_size_t shm_segsz;\n\tlong int shm_atime;\n\tlong int shm_dtime;\n\tlong int shm_ctime;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct shortname_info {\n\tunsigned char lower: 1;\n\tunsigned char upper: 1;\n\tunsigned char valid: 1;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tint id;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct shrinker_info_unit;\n\nstruct shrinker_info {\n\tstruct callback_head rcu;\n\tint map_nr_max;\n\tstruct shrinker_info_unit *unit[0];\n};\n\nstruct shrinker_info_unit {\n\tatomic_long_t nr_deferred[64];\n\tlong unsigned int map[1];\n};\n\nstruct shutdown_handler {\n\tconst char command[11];\n\tbool flag;\n\tvoid (*cb)(void);\n};\n\nstruct sifive_fu540_macb_mgmt {\n\tvoid *reg;\n\tlong unsigned int rate;\n\tstruct clk_hw hw;\n};\n\nstruct sig_alg {\n\tint (*sign)(struct crypto_sig *, const void *, unsigned int, void *, unsigned int);\n\tint (*verify)(struct crypto_sig *, const void *, unsigned int, const void *, unsigned int);\n\tint (*set_pub_key)(struct crypto_sig *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_sig *, const void *, unsigned int);\n\tunsigned int (*key_size)(struct crypto_sig *);\n\tunsigned int (*digest_size)(struct crypto_sig *);\n\tunsigned int (*max_size)(struct crypto_sig *);\n\tint (*init)(struct crypto_sig *);\n\tvoid (*exit)(struct crypto_sig *);\n\tstruct crypto_alg base;\n};\n\nstruct signal_attenuation_s;\n\nstruct sig_atten_lu_s {\n\tconst struct signal_attenuation_s *att;\n\tu32 sas_phy_ctrl;\n};\n\nstruct sig_instance {\n\tvoid (*free)(struct sig_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[72];\n\t\t\tstruct crypto_instance base;\n\t\t};\n\t\tstruct sig_alg alg;\n\t};\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct signal_attenuation_s {\n\tu32 de_emphasis;\n\tu32 preshoot;\n\tu32 boost;\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {\n\tu64 rchar;\n\tu64 wchar;\n\tu64 syscr;\n\tu64 syscw;\n\tu64 read_bytes;\n\tu64 write_bytes;\n\tu64 cancelled_write_bytes;\n};\n\nstruct taskstats;\n\nstruct tty_audit_buf;\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tstruct autogroup *autogroup;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct pacct_struct pacct;\n\tstruct taskstats *stats;\n\tunsigned int audit_tty;\n\tstruct tty_audit_buf *tty_audit_buf;\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct sil24_prb {\n\t__le16 ctrl;\n\t__le16 prot;\n\t__le32 rx_cnt;\n\tu8 fis[24];\n};\n\nstruct sil24_sge {\n\t__le64 addr;\n\t__le32 cnt;\n\t__le32 flags;\n};\n\nstruct sil24_ata_block {\n\tstruct sil24_prb prb;\n\tstruct sil24_sge sge[253];\n};\n\nstruct sil24_atapi_block {\n\tstruct sil24_prb prb;\n\tu8 cdb[16];\n\tstruct sil24_sge sge[253];\n};\n\nstruct sil24_cerr_info {\n\tunsigned int err_mask;\n\tunsigned int action;\n\tconst char *desc;\n};\n\nunion sil24_cmd_block {\n\tstruct sil24_ata_block ata;\n\tstruct sil24_atapi_block atapi;\n};\n\nstruct sil24_port_priv {\n\tunion sil24_cmd_block *cmd_block;\n\tdma_addr_t cmd_block_dma;\n\tint do_port_rst;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_mfd_data {\n\tconst struct regmap_config *regmap_config;\n\tconst struct mfd_cell *mfd_cell;\n\tsize_t mfd_cell_size;\n};\n\nstruct simple_pm_bus {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct simplefb_platform_data {\n\tu32 width;\n\tu32 height;\n\tu32 stride;\n\tconst char *format;\n};\n\nstruct sipll5 {\n\tstruct clk_hw hw;\n\tu32 conf;\n\tlong unsigned int foutpostdiv_rate;\n\tstruct rzg2l_cpg_priv *priv;\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct skb_ext {\n\trefcount_t refcnt;\n\tu8 offset[2];\n\tu8 chunks;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*export)(struct skcipher_request *, void *);\n\tint (*import)(struct skcipher_request *, const void *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int walksize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int min_keysize;\n\t\t\tunsigned int max_keysize;\n\t\t\tunsigned int ivsize;\n\t\t\tunsigned int chunksize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct skcipher_alg_common co;\n\t};\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[88];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tvoid *__ctx[0];\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int nbytes;\n\tunsigned int total;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct sky2_status_le;\n\nstruct sky2_hw {\n\tvoid *regs;\n\tstruct pci_dev *pdev;\n\tstruct napi_struct napi;\n\tstruct net_device *dev[2];\n\tlong unsigned int flags;\n\tu8 chip_id;\n\tu8 chip_rev;\n\tu8 pmd_type;\n\tu8 ports;\n\tstruct sky2_status_le *st_le;\n\tu32 st_size;\n\tu32 st_idx;\n\tdma_addr_t st_dma;\n\tstruct timer_list watchdog_timer;\n\tstruct work_struct restart_work;\n\twait_queue_head_t msi_wait;\n\tchar irq_name[0];\n};\n\nstruct sky2_stats {\n\tstruct u64_stats_sync syncp;\n\tu64 packets;\n\tu64 bytes;\n};\n\nstruct tx_ring_info;\n\nstruct sky2_tx_le;\n\nstruct sky2_rx_le;\n\nstruct sky2_port {\n\tstruct sky2_hw *hw;\n\tstruct net_device *netdev;\n\tunsigned int port;\n\tu32 msg_enable;\n\tspinlock_t phy_lock;\n\tstruct tx_ring_info *tx_ring;\n\tstruct sky2_tx_le *tx_le;\n\tstruct sky2_stats tx_stats;\n\tu16 tx_ring_size;\n\tu16 tx_cons;\n\tu16 tx_prod;\n\tu16 tx_next;\n\tu16 tx_pending;\n\tu16 tx_last_mss;\n\tu32 tx_last_upper;\n\tu32 tx_tcpsum;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rx_ring_info *rx_ring;\n\tstruct sky2_rx_le *rx_le;\n\tstruct sky2_stats rx_stats;\n\tu16 rx_next;\n\tu16 rx_put;\n\tu16 rx_pending;\n\tu16 rx_data_size;\n\tu16 rx_nfrags;\n\tlong unsigned int last_rx;\n\tstruct {\n\t\tlong unsigned int last;\n\t\tu32 mac_rp;\n\t\tu8 mac_lev;\n\t\tu8 fifo_rp;\n\t\tu8 fifo_lev;\n\t} check;\n\tdma_addr_t rx_le_map;\n\tdma_addr_t tx_le_map;\n\tu16 advertising;\n\tu16 speed;\n\tu8 wol;\n\tu8 duplex;\n\tu16 flags;\n\tenum flow_control flow_mode;\n\tenum flow_control flow_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sky2_rx_le {\n\t__le32 addr;\n\t__le16 length;\n\tu8 ctrl;\n\tu8 opcode;\n};\n\nstruct sky2_stat {\n\tchar name[32];\n\tu16 offset;\n};\n\nstruct sky2_status_le {\n\t__le32 status;\n\t__le16 length;\n\tu8 css;\n\tu8 opcode;\n};\n\nstruct sky2_tx_le {\n\t__le32 addr;\n\t__le16 length;\n\tu8 ctrl;\n\tu8 opcode;\n};\n\nstruct sl28cpld_intc {\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip chip;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int obj_exts;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct slabobj_ext {\n\tstruct obj_cgroup *objcg;\n};\n\nstruct sleep_stack_data {\n\tstruct cpu_suspend_ctx system_regs;\n\tlong unsigned int callee_saved_regs[12];\n};\n\nstruct slot {\n\tstruct hotplug_slot hotplug_slot;\n\tstruct acpiphp_slot *acpi_slot;\n\tunsigned int sun;\n};\n\nstruct slot_pwrctrl {\n\tstruct pci_pwrctrl pwrctrl;\n\tstruct regulator_bulk_data *supplies;\n\tint num_supplies;\n\tstruct clk *clk;\n\tstruct pwrseq_desc *pwrseq;\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc91x_platdata {\n\tlong unsigned int flags;\n\tunsigned char leda;\n\tunsigned char ledb;\n\tbool pxa_u16_align4;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct smc_local {\n\tstruct sk_buff *pending_tx_skb;\n\tstruct tasklet_struct tx_task;\n\tstruct gpio_desc *power_gpio;\n\tstruct gpio_desc *reset_gpio;\n\tint version;\n\tint tcr_cur_mode;\n\tint rcr_cur_mode;\n\tint rpc_cur_mode;\n\tint ctl_rfduplx;\n\tint ctl_rspeed;\n\tu32 msg_enable;\n\tu32 phy_type;\n\tstruct mii_if_info mii;\n\tstruct work_struct phy_configure;\n\tstruct net_device *dev;\n\tint work_pending;\n\tspinlock_t lock;\n\tstruct dma_chan *dma_chan;\n\tvoid *base;\n\tvoid *datacs;\n\tint io_shift;\n\tbool half_word_align4;\n\tstruct smc91x_platdata cfg;\n};\n\nstruct smd_channel_info {\n\t__le32 state;\n\tu8 fDSR;\n\tu8 fCTS;\n\tu8 fCD;\n\tu8 fRI;\n\tu8 fHEAD;\n\tu8 fTAIL;\n\tu8 fSTATE;\n\tu8 fBLOCKREADINTR;\n\t__le32 tail;\n\t__le32 head;\n};\n\nstruct smd_channel_info_pair {\n\tstruct smd_channel_info tx;\n\tstruct smd_channel_info rx;\n};\n\nstruct smd_channel_info_word {\n\t__le32 state;\n\t__le32 fDSR;\n\t__le32 fCTS;\n\t__le32 fCD;\n\t__le32 fRI;\n\t__le32 fHEAD;\n\t__le32 fTAIL;\n\t__le32 fSTATE;\n\t__le32 fBLOCKREADINTR;\n\t__le32 tail;\n\t__le32 head;\n};\n\nstruct smd_channel_info_word_pair {\n\tstruct smd_channel_info_word tx;\n\tstruct smd_channel_info_word rx;\n};\n\nstruct smem_global_entry {\n\t__le32 allocated;\n\t__le32 offset;\n\t__le32 size;\n\t__le32 aux_base;\n};\n\nstruct smem_proc_comm {\n\t__le32 command;\n\t__le32 status;\n\t__le32 params[2];\n};\n\nstruct smem_header {\n\tstruct smem_proc_comm proc_comm[4];\n\t__le32 version[32];\n\t__le32 initialized;\n\t__le32 free_offset;\n\t__le32 available;\n\t__le32 reserved;\n\tstruct smem_global_entry toc[512];\n};\n\nstruct smem_info {\n\tu8 magic[4];\n\t__le32 size;\n\t__le32 base_addr;\n\t__le32 reserved;\n\t__le16 num_items;\n};\n\nstruct smem_partition_header {\n\tu8 magic[4];\n\t__le16 host0;\n\t__le16 host1;\n\t__le32 size;\n\t__le32 offset_free_uncached;\n\t__le32 offset_free_cached;\n\t__le32 reserved[3];\n};\n\nstruct smem_private_entry {\n\tu16 canary;\n\t__le16 item;\n\t__le32 size;\n\t__le16 padding_data;\n\t__le16 padding_hdr;\n\t__le32 reserved;\n};\n\nstruct smem_ptable_entry {\n\t__le32 offset;\n\t__le32 size;\n\t__le32 flags;\n\t__le16 host0;\n\t__le16 host1;\n\t__le32 cacheline;\n\t__le32 reserved[7];\n};\n\nstruct smem_ptable {\n\tu8 magic[4];\n\t__le32 version;\n\t__le32 num_entries;\n\t__le32 reserved[5];\n\tstruct smem_ptable_entry entry[0];\n};\n\nstruct smp2p_entry {\n\tstruct list_head node;\n\tstruct qcom_smp2p *smp2p;\n\tconst char *name;\n\tu32 *value;\n\tu32 last_value;\n\tstruct irq_domain *domain;\n\tlong unsigned int irq_enabled[1];\n\tlong unsigned int irq_rising[1];\n\tlong unsigned int irq_falling[1];\n\tstruct qcom_smem_state *state;\n\tspinlock_t lock;\n};\n\nstruct smp2p_smem_item {\n\tu32 magic;\n\tu8 version;\n\tunsigned int features: 24;\n\tu16 local_pid;\n\tu16 remote_pid;\n\tu16 total_entries;\n\tu16 valid_entries;\n\tu32 flags;\n\tstruct {\n\t\tu8 name[16];\n\t\tu32 value;\n\t} entries[16];\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_disc_resp {\n\tu8 frame_type;\n\tu8 function;\n\tu8 result;\n\tu8 reserved;\n\tstruct discover_resp disc;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smp_rg_resp {\n\tu8 frame_type;\n\tu8 function;\n\tu8 result;\n\tu8 reserved;\n\tstruct report_general_resp rg;\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct smsc911x_platform_config {\n\tunsigned int irq_polarity;\n\tunsigned int irq_type;\n\tunsigned int flags;\n\tunsigned int shift;\n\tphy_interface_t phy_interface;\n\tunsigned char mac[6];\n};\n\nstruct smsc911x_ops;\n\nstruct smsc911x_data {\n\tvoid *ioaddr;\n\tunsigned int idrev;\n\tunsigned int generation;\n\tstruct smsc911x_platform_config config;\n\tspinlock_t mac_lock;\n\tspinlock_t dev_lock;\n\tstruct mii_bus *mii_bus;\n\tunsigned int using_extphy;\n\tint last_duplex;\n\tint last_carrier;\n\tu32 msg_enable;\n\tunsigned int gpio_setting;\n\tunsigned int gpio_orig_setting;\n\tstruct net_device *dev;\n\tstruct napi_struct napi;\n\tunsigned int software_irq_signal;\n\tchar loopback_tx_pkt[64];\n\tchar loopback_rx_pkt[64];\n\tunsigned int resetcount;\n\tunsigned int multicast_update_pending;\n\tunsigned int set_bits_mask;\n\tunsigned int clear_bits_mask;\n\tunsigned int hashhi;\n\tunsigned int hashlo;\n\tconst struct smsc911x_ops *ops;\n\tstruct regulator_bulk_data supplies[2];\n\tstruct gpio_desc *reset_gpiod;\n\tstruct clk *clk;\n};\n\nstruct smsc911x_ops {\n\tu32 (*reg_read)(struct smsc911x_data *, u32);\n\tvoid (*reg_write)(struct smsc911x_data *, u32, u32);\n\tvoid (*rx_readfifo)(struct smsc911x_data *, unsigned int *, unsigned int);\n\tvoid (*tx_writefifo)(struct smsc911x_data *, unsigned int *, unsigned int);\n};\n\nstruct smsm_entry {\n\tstruct qcom_smsm *smsm;\n\tstruct irq_domain *domain;\n\tlong unsigned int irq_enabled[1];\n\tlong unsigned int irq_rising[1];\n\tlong unsigned int irq_falling[1];\n\tlong unsigned int last_value;\n\tu32 *remote_state;\n\tu32 *subscription;\n};\n\nstruct smsm_host {\n\tstruct regmap *ipc_regmap;\n\tint ipc_offset;\n\tint ipc_bit;\n\tstruct mbox_chan *mbox_chan;\n};\n\nstruct snapshot_handle {\n\tunsigned int cur;\n\tvoid *buffer;\n\tint sync_read;\n};\n\nstruct snapshot_data {\n\tstruct snapshot_handle handle;\n\tint swap;\n\tint mode;\n\tbool frozen;\n\tbool ready;\n\tbool platform_support;\n\tbool free_bitmaps;\n\tdev_t dev;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct snvs_lpgpr_cfg {\n\tint offset;\n\tint offset_hplr;\n\tint offset_lplr;\n\tint size;\n};\n\nstruct device_d;\n\nstruct snvs_lpgpr_priv {\n\tstruct device_d *dev;\n\tstruct regmap *regmap;\n\tstruct nvmem_config cfg;\n\tconst struct snvs_lpgpr_cfg *dcfg;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct soc_device {\n\tstruct device dev;\n\tstruct soc_device_attribute *attr;\n\tint soc_dev_num;\n};\n\nstruct soc_device_attribute {\n\tconst char *machine;\n\tconst char *family;\n\tconst char *revision;\n\tconst char *serial_number;\n\tconst char *soc_id;\n\tconst void *data;\n\tconst struct attribute_group *custom_attr_group;\n};\n\nstruct soc_pad_ctrl {\n\tvoid *reg;\n\tenum soc_pad_ctrl_type pad_type;\n\tvoid (*set_soc_pad)(struct sdhci_host *, unsigned char);\n};\n\nstruct socfpga_gate_clk {\n\tstruct clk_gate hw;\n\tchar *parent_name;\n\tu32 fixed_div;\n\tvoid *div_reg;\n\tvoid *bypass_reg;\n\tstruct regmap *sys_mgr_base_addr;\n\tu32 width;\n\tu32 shift;\n\tu32 bypass_shift;\n};\n\nstruct socfpga_periph_clk {\n\tstruct clk_gate hw;\n\tchar *parent_name;\n\tu32 fixed_div;\n\tvoid *div_reg;\n\tvoid *bypass_reg;\n\tu32 width;\n\tu32 shift;\n\tu32 bypass_shift;\n};\n\nstruct socfpga_pll {\n\tstruct clk_gate hw;\n};\n\nstruct socinfo {\n\t__le32 fmt;\n\t__le32 id;\n\t__le32 ver;\n\tchar build_id[32];\n\t__le32 raw_id;\n\t__le32 raw_ver;\n\t__le32 hw_plat;\n\t__le32 plat_ver;\n\t__le32 accessory_chip;\n\t__le32 hw_plat_subtype;\n\t__le32 pmic_model;\n\t__le32 pmic_die_rev;\n\t__le32 pmic_model_1;\n\t__le32 pmic_die_rev_1;\n\t__le32 pmic_model_2;\n\t__le32 pmic_die_rev_2;\n\t__le32 foundry_id;\n\t__le32 serial_num;\n\t__le32 num_pmics;\n\t__le32 pmic_array_offset;\n\t__le32 chip_family;\n\t__le32 raw_device_family;\n\t__le32 raw_device_num;\n\t__le32 nproduct_id;\n\tchar chip_id[32];\n\t__le32 num_clusters;\n\t__le32 ncluster_array_offset;\n\t__le32 num_subset_parts;\n\t__le32 nsubset_parts_array_offset;\n\t__le32 nmodem_supported;\n\t__le32 feature_code;\n\t__le32 pcode;\n\t__le32 npartnamemap_offset;\n\t__le32 nnum_partname_mapping;\n\t__le32 oem_variant;\n\t__le32 num_kvps;\n\t__le32 kvps_offset;\n\t__le32 num_func_clusters;\n\t__le32 boot_cluster;\n\t__le32 boot_core;\n\t__le32 raw_package_type;\n\t__le32 reserve1[4];\n};\n\nstruct socinfo_data {\n\tchar *soc_name;\n\tchar *segment_name;\n\tchar *marketing_name;\n\tu32 cell_data[2];\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sock_xprt {\n\tstruct rpc_xprt xprt;\n\tstruct socket *sock;\n\tstruct sock *inet;\n\tstruct file *file;\n\tstruct {\n\t\tstruct {\n\t\t\t__be32 fraghdr;\n\t\t\t__be32 xid;\n\t\t\t__be32 calldir;\n\t\t};\n\t\tu32 offset;\n\t\tu32 len;\n\t\tlong unsigned int copied;\n\t} recv;\n\tstruct {\n\t\tu32 offset;\n\t} xmit;\n\tlong unsigned int sock_state;\n\tstruct delayed_work connect_worker;\n\tstruct work_struct error_worker;\n\tstruct work_struct recv_worker;\n\tstruct mutex recv_mutex;\n\tstruct completion handshake_done;\n\tstruct __kernel_sockaddr_storage srcaddr;\n\tshort unsigned int srcport;\n\tint xprt_err;\n\tstruct rpc_clnt *clnt;\n\tsize_t rcvsize;\n\tsize_t sndsize;\n\tstruct rpc_timeout tcp_timeout;\n\tvoid (*old_data_ready)(struct sock *);\n\tvoid (*old_state_change)(struct sock *);\n\tvoid (*old_write_space)(struct sock *);\n\tvoid (*old_error_report)(struct sock *);\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 64;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int input_queue_head;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t defer_csd;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct sophgo_pinctrl;\n\nstruct sophgo_pin_mux_config;\n\nstruct sophgo_cfg_ops {\n\tint (*pctrl_init)(struct platform_device *, struct sophgo_pinctrl *);\n\tint (*verify_pinmux_config)(const struct sophgo_pin_mux_config *);\n\tint (*verify_pin_group)(const struct sophgo_pin_mux_config *, unsigned int);\n\tint (*dt_node_to_map_post)(struct device_node *, struct sophgo_pinctrl *, struct sophgo_pin_mux_config *, unsigned int);\n\tint (*compute_pinconf_config)(struct sophgo_pinctrl *, const struct sophgo_pin *, long unsigned int *, unsigned int, u32 *, u32 *);\n\tint (*set_pinconf_config)(struct sophgo_pinctrl *, const struct sophgo_pin *, u32, u32);\n\tvoid (*set_pinmux_config)(struct sophgo_pinctrl *, const struct sophgo_pin *, u32);\n};\n\nstruct sophgo_pin_mux_config {\n\tconst struct sophgo_pin *pin;\n\tu32 config;\n};\n\nstruct sophgo_pinctrl_data;\n\nstruct sophgo_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctrl_dev;\n\tconst struct sophgo_pinctrl_data *data;\n\tstruct pinctrl_desc pdesc;\n\tstruct mutex mutex;\n\traw_spinlock_t lock;\n\tvoid *priv_ctrl;\n};\n\nstruct sophgo_vddio_cfg_ops;\n\nstruct sophgo_pinctrl_data {\n\tconst struct pinctrl_pin_desc *pins;\n\tconst void *pindata;\n\tconst char * const *pdnames;\n\tconst struct sophgo_vddio_cfg_ops *vddio_ops;\n\tconst struct sophgo_cfg_ops *cfg_ops;\n\tconst struct pinctrl_ops *pctl_ops;\n\tconst struct pinmux_ops *pmx_ops;\n\tconst struct pinconf_ops *pconf_ops;\n\tu16 npins;\n\tu16 npds;\n\tu16 pinsize;\n};\n\nstruct sophgo_vddio_cfg_ops {\n\tint (*get_pull_up)(const struct sophgo_pin *, const u32 *);\n\tint (*get_pull_down)(const struct sophgo_pin *, const u32 *);\n\tint (*get_oc_map)(const struct sophgo_pin *, const u32 *, const u32 **);\n\tint (*get_schmitt_map)(const struct sophgo_pin *, const u32 *, const u32 **);\n};\n\nstruct sp804_clkevt {\n\tvoid *base;\n\tvoid *load;\n\tvoid *load_h;\n\tvoid *value;\n\tvoid *value_h;\n\tvoid *ctrl;\n\tvoid *intclr;\n\tvoid *ris;\n\tvoid *mis;\n\tvoid *bgload;\n\tvoid *bgload_h;\n\tlong unsigned int reload;\n\tint width;\n};\n\nstruct sp804_timer {\n\tint load;\n\tint load_h;\n\tint value;\n\tint value_h;\n\tint ctrl;\n\tint intclr;\n\tint ris;\n\tint mis;\n\tint bgload;\n\tint bgload_h;\n\tint timer_base[2];\n\tint width;\n};\n\nstruct sp805_wdt {\n\tstruct watchdog_device wdd;\n\tspinlock_t lock;\n\tvoid *base;\n\tstruct clk *clk;\n\tu64 rate;\n\tstruct amba_device *adev;\n\tunsigned int load_val;\n};\n\nstruct sp_node {\n\tstruct rb_node nd;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct mempolicy *policy;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct spansion_nor_params {\n\tu8 clsr;\n};\n\nstruct spectre_v4_param {\n\tconst char *str;\n\tenum spectre_v4_policy policy;\n};\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n};\n\nstruct spi_controller_mem_ops;\n\nstruct spi_controller_mem_caps;\n\nstruct spi_offload_config;\n\nstruct spi_statistics;\n\nstruct spi_controller {\n\tstruct device dev;\n\tstruct list_head list;\n\ts16 bus_num;\n\tu16 num_chipselect;\n\tu16 num_data_lanes;\n\tu16 dma_alignment;\n\tu32 mode_bits;\n\tu32 buswidth_override_bits;\n\tu32 bits_per_word_mask;\n\tu32 min_speed_hz;\n\tu32 max_speed_hz;\n\tu16 flags;\n\tbool devm_allocated;\n\tunion {\n\t\tbool slave;\n\t\tbool target;\n\t};\n\tsize_t (*max_transfer_size)(struct spi_device *);\n\tsize_t (*max_message_size)(struct spi_device *);\n\tstruct mutex io_mutex;\n\tstruct mutex add_lock;\n\tspinlock_t bus_lock_spinlock;\n\tstruct mutex bus_lock_mutex;\n\tbool bus_lock_flag;\n\tint (*setup)(struct spi_device *);\n\tint (*set_cs_timing)(struct spi_device *);\n\tint (*transfer)(struct spi_device *, struct spi_message *);\n\tvoid (*cleanup)(struct spi_device *);\n\tbool (*can_dma)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tstruct device *dma_map_dev;\n\tstruct device *cur_rx_dma_dev;\n\tstruct device *cur_tx_dma_dev;\n\tbool queued;\n\tstruct kthread_worker *kworker;\n\tstruct kthread_work pump_messages;\n\tspinlock_t queue_lock;\n\tstruct list_head queue;\n\tstruct spi_message *cur_msg;\n\tstruct completion cur_msg_completion;\n\tbool cur_msg_incomplete;\n\tbool cur_msg_need_completion;\n\tbool busy;\n\tbool running;\n\tbool rt;\n\tbool auto_runtime_pm;\n\tbool fallback;\n\tbool last_cs_mode_high;\n\ts8 last_cs[4];\n\tu32 last_cs_index_mask: 4;\n\tstruct completion xfer_completion;\n\tsize_t max_dma_len;\n\tint (*optimize_message)(struct spi_message *);\n\tint (*unoptimize_message)(struct spi_message *);\n\tint (*prepare_transfer_hardware)(struct spi_controller *);\n\tint (*transfer_one_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_transfer_hardware)(struct spi_controller *);\n\tint (*prepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*unprepare_message)(struct spi_controller *, struct spi_message *);\n\tint (*target_abort)(struct spi_controller *);\n\tvoid (*set_cs)(struct spi_device *, bool);\n\tint (*transfer_one)(struct spi_controller *, struct spi_device *, struct spi_transfer *);\n\tvoid (*handle_err)(struct spi_controller *, struct spi_message *);\n\tconst struct spi_controller_mem_ops *mem_ops;\n\tconst struct spi_controller_mem_caps *mem_caps;\n\tbool dtr_caps;\n\tstruct spi_offload * (*get_offload)(struct spi_device *, const struct spi_offload_config *);\n\tvoid (*put_offload)(struct spi_offload *);\n\tstruct gpio_desc **cs_gpiods;\n\tbool use_gpio_descriptors;\n\ts8 unused_native_cs;\n\ts8 max_native_cs;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct dma_chan *dma_tx;\n\tstruct dma_chan *dma_rx;\n\tvoid *dummy_rx;\n\tvoid *dummy_tx;\n\tint (*fw_translate_cs)(struct spi_controller *, unsigned int);\n\tbool ptp_sts_supported;\n\tlong unsigned int irq_flags;\n\tbool queue_empty;\n\tbool must_async;\n\tbool defer_optimize_message;\n};\n\nstruct spi_controller_mem_caps {\n\tbool dtr;\n\tbool ecc;\n\tbool swap16;\n\tbool per_op_freq;\n};\n\nstruct spi_mem;\n\nstruct spi_mem_dirmap_desc;\n\nstruct spi_controller_mem_ops {\n\tint (*adjust_op_size)(struct spi_mem *, struct spi_mem_op *);\n\tbool (*supports_op)(struct spi_mem *, const struct spi_mem_op *);\n\tint (*exec_op)(struct spi_mem *, const struct spi_mem_op *);\n\tconst char * (*get_name)(struct spi_mem *);\n\tint (*dirmap_create)(struct spi_mem_dirmap_desc *);\n\tvoid (*dirmap_destroy)(struct spi_mem_dirmap_desc *);\n\tssize_t (*dirmap_read)(struct spi_mem_dirmap_desc *, u64, size_t, void *);\n\tssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *, u64, size_t, const void *);\n\tint (*poll_status)(struct spi_mem *, const struct spi_mem_op *, u16, u16, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct spi_device {\n\tstruct device dev;\n\tstruct spi_controller *controller;\n\tu32 max_speed_hz;\n\tu8 bits_per_word;\n\tbool rt;\n\tu32 mode;\n\tint irq;\n\tvoid *controller_state;\n\tvoid *controller_data;\n\tchar modalias[32];\n\tconst char *driver_override;\n\tstruct spi_statistics *pcpu_statistics;\n\tstruct spi_delay word_delay;\n\tstruct spi_delay cs_setup;\n\tstruct spi_delay cs_hold;\n\tstruct spi_delay cs_inactive;\n\tu8 chip_select[4];\n\tu8 num_chipselect;\n\tu32 cs_index_mask: 4;\n\tstruct gpio_desc *cs_gpiod[4];\n\tu8 tx_lane_map[8];\n\tu8 num_tx_lanes;\n\tu8 rx_lane_map[8];\n\tu8 num_rx_lanes;\n};\n\nstruct spi_device_id {\n\tchar name[32];\n\tkernel_ulong_t driver_data;\n};\n\nstruct spi_driver {\n\tconst struct spi_device_id *id_table;\n\tint (*probe)(struct spi_device *);\n\tvoid (*remove)(struct spi_device *);\n\tvoid (*shutdown)(struct spi_device *);\n\tstruct device_driver driver;\n};\n\nstruct spi_mem {\n\tstruct spi_device *spi;\n\tvoid *drvpriv;\n\tconst char *name;\n};\n\nstruct spi_mem_op {\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tu16 opcode;\n\t} cmd;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t\tu64 val;\n\t} addr;\n\tstruct {\n\t\tu8 nbytes;\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 __pad: 7;\n\t} dummy;\n\tstruct {\n\t\tu8 buswidth;\n\t\tu8 dtr: 1;\n\t\tu8 ecc: 1;\n\t\tu8 swap16: 1;\n\t\tu8 __pad: 5;\n\t\tenum spi_mem_data_dir dir;\n\t\tunsigned int nbytes;\n\t\tunion {\n\t\t\tvoid *in;\n\t\t\tconst void *out;\n\t\t} buf;\n\t} data;\n\tunsigned int max_freq;\n};\n\nstruct spi_mem_dirmap_info {\n\tstruct spi_mem_op op_tmpl;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct spi_mem_dirmap_desc {\n\tstruct spi_mem *mem;\n\tstruct spi_mem_dirmap_info info;\n\tunsigned int nodirmap;\n\tvoid *priv;\n};\n\nstruct spi_mem_driver {\n\tstruct spi_driver spidrv;\n\tint (*probe)(struct spi_mem *);\n\tint (*remove)(struct spi_mem *);\n\tvoid (*shutdown)(struct spi_mem *);\n};\n\nstruct spi_nor_rww {\n\twait_queue_head_t wait;\n\tbool ongoing_io;\n\tbool ongoing_rd;\n\tbool ongoing_pe;\n\tunsigned int used_banks;\n};\n\nstruct spi_nor_manufacturer;\n\nstruct spi_nor_controller_ops;\n\nstruct spi_nor_flash_parameter;\n\nstruct spi_nor {\n\tstruct mtd_info mtd;\n\tstruct mutex lock;\n\tstruct spi_nor_rww rww;\n\tstruct device *dev;\n\tstruct spi_mem *spimem;\n\tu8 *bouncebuf;\n\tsize_t bouncebuf_size;\n\tu8 *id;\n\tconst struct flash_info___3 *info;\n\tconst struct spi_nor_manufacturer *manufacturer;\n\tu8 addr_nbytes;\n\tu8 erase_opcode;\n\tu8 read_opcode;\n\tu8 read_dummy;\n\tu8 program_opcode;\n\tenum spi_nor_protocol read_proto;\n\tenum spi_nor_protocol write_proto;\n\tenum spi_nor_protocol reg_proto;\n\tbool sst_write_second;\n\tu32 flags;\n\tenum spi_nor_cmd_ext cmd_ext_type;\n\tstruct sfdp *sfdp;\n\tstruct dentry *debugfs_root;\n\tconst struct spi_nor_controller_ops *controller_ops;\n\tstruct spi_nor_flash_parameter *params;\n\tstruct {\n\t\tstruct spi_mem_dirmap_desc *rdesc;\n\t\tstruct spi_mem_dirmap_desc *wdesc;\n\t} dirmap;\n\tvoid *priv;\n};\n\nstruct spi_nor_controller_ops {\n\tint (*prepare)(struct spi_nor *);\n\tvoid (*unprepare)(struct spi_nor *);\n\tint (*read_reg)(struct spi_nor *, u8, u8 *, size_t);\n\tint (*write_reg)(struct spi_nor *, u8, const u8 *, size_t);\n\tssize_t (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tssize_t (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*erase)(struct spi_nor *, loff_t);\n};\n\nstruct spi_nor_erase_command {\n\tstruct list_head list;\n\tu32 count;\n\tu32 size;\n\tu8 opcode;\n};\n\nstruct spi_nor_erase_region {\n\tu64 offset;\n\tu64 size;\n\tu8 erase_mask;\n\tbool overlaid;\n};\n\nstruct spi_nor_erase_type {\n\tu32 size;\n\tu32 size_shift;\n\tu32 size_mask;\n\tu8 opcode;\n\tu8 idx;\n};\n\nstruct spi_nor_erase_map {\n\tstruct spi_nor_erase_region *regions;\n\tstruct spi_nor_erase_region uniform_region;\n\tstruct spi_nor_erase_type erase_type[4];\n\tunsigned int n_regions;\n};\n\nstruct spi_nor_fixups {\n\tvoid (*default_init)(struct spi_nor *);\n\tint (*post_bfpt)(struct spi_nor *, const struct sfdp_parameter_header *, const struct sfdp_bfpt *);\n\tvoid (*smpt_read_dummy)(const struct spi_nor *, u8 *);\n\tvoid (*smpt_map_id)(const struct spi_nor *, u8 *);\n\tint (*post_sfdp)(struct spi_nor *);\n\tint (*late_init)(struct spi_nor *);\n};\n\nstruct spi_nor_hwcaps {\n\tu32 mask;\n};\n\nstruct spi_nor_read_command {\n\tu8 num_mode_clocks;\n\tu8 num_wait_states;\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_pp_command {\n\tu8 opcode;\n\tenum spi_nor_protocol proto;\n};\n\nstruct spi_nor_otp_ops;\n\nstruct spi_nor_otp {\n\tconst struct spi_nor_otp_organization *org;\n\tconst struct spi_nor_otp_ops *ops;\n};\n\nstruct spi_nor_locking_ops;\n\nstruct spi_nor_flash_parameter {\n\tu64 bank_size;\n\tu64 size;\n\tu32 writesize;\n\tu32 page_size;\n\tu8 addr_nbytes;\n\tu8 addr_mode_nbytes;\n\tu8 rdsr_dummy;\n\tu8 rdsr_addr_nbytes;\n\tu8 n_banks;\n\tu8 n_dice;\n\tu8 die_erase_opcode;\n\tu32 *vreg_offset;\n\tstruct spi_nor_hwcaps hwcaps;\n\tstruct spi_nor_read_command reads[16];\n\tstruct spi_nor_pp_command page_programs[8];\n\tstruct spi_nor_erase_map erase_map;\n\tstruct spi_nor_otp otp;\n\tint (*set_octal_dtr)(struct spi_nor *, bool);\n\tint (*quad_enable)(struct spi_nor *);\n\tint (*set_4byte_addr_mode)(struct spi_nor *, bool);\n\tint (*ready)(struct spi_nor *);\n\tconst struct spi_nor_locking_ops *locking_ops;\n\tvoid *priv;\n};\n\nstruct spi_nor_id {\n\tconst u8 *bytes;\n\tu8 len;\n};\n\nstruct spi_nor_locking_ops {\n\tint (*lock)(struct spi_nor *, loff_t, u64);\n\tint (*unlock)(struct spi_nor *, loff_t, u64);\n\tint (*is_locked)(struct spi_nor *, loff_t, u64);\n};\n\nstruct spi_nor_manufacturer {\n\tconst char *name;\n\tconst struct flash_info___3 *parts;\n\tunsigned int nparts;\n\tconst struct spi_nor_fixups *fixups;\n};\n\nstruct spi_nor_otp_ops {\n\tint (*read)(struct spi_nor *, loff_t, size_t, u8 *);\n\tint (*write)(struct spi_nor *, loff_t, size_t, const u8 *);\n\tint (*lock)(struct spi_nor *, unsigned int);\n\tint (*erase)(struct spi_nor *, loff_t);\n\tint (*is_locked)(struct spi_nor *, unsigned int);\n};\n\nstruct spi_nor_otp_organization {\n\tsize_t len;\n\tloff_t base;\n\tloff_t offset;\n\tunsigned int n_regions;\n};\n\nstruct spi_offload_ops;\n\nstruct spi_offload {\n\tstruct device *provider_dev;\n\tvoid *priv;\n\tconst struct spi_offload_ops *ops;\n\tu32 xfer_flags;\n};\n\nstruct spi_offload_config {\n\tu32 capability_flags;\n};\n\nstruct spi_offload_ops {\n\tint (*trigger_enable)(struct spi_offload *);\n\tvoid (*trigger_disable)(struct spi_offload *);\n\tstruct dma_chan * (*tx_stream_request_dma_chan)(struct spi_offload *);\n\tstruct dma_chan * (*rx_stream_request_dma_chan)(struct spi_offload *);\n};\n\nstruct spi_qup {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct clk *cclk;\n\tstruct clk *iclk;\n\tstruct icc_path *icc_path;\n\tint irq;\n\tspinlock_t lock;\n\tint in_fifo_sz;\n\tint out_fifo_sz;\n\tint in_blk_sz;\n\tint out_blk_sz;\n\tstruct spi_transfer *xfer;\n\tstruct completion done;\n\tint error;\n\tint w_size;\n\tint n_words;\n\tint tx_bytes;\n\tint rx_bytes;\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tint qup_v1;\n\tint mode;\n\tstruct dma_slave_config rx_conf;\n\tstruct dma_slave_config tx_conf;\n\tu32 bw_speed_hz;\n};\n\nstruct spi_replaced_transfers;\n\ntypedef void (*spi_replaced_release_t)(struct spi_controller *, struct spi_message *, struct spi_replaced_transfers *);\n\nstruct spi_replaced_transfers {\n\tspi_replaced_release_t release;\n\tvoid *extradata;\n\tstruct list_head replaced_transfers;\n\tstruct list_head *replaced_after;\n\tsize_t inserted;\n\tstruct spi_transfer inserted_transfers[0];\n};\n\ntypedef void (*spi_res_release_t)(struct spi_controller *, struct spi_message *, void *);\n\nstruct spi_res {\n\tstruct list_head entry;\n\tspi_res_release_t release;\n\tlong long unsigned int data[0];\n};\n\nstruct spi_statistics {\n\tstruct u64_stats_sync syncp;\n\tu64_stats_t messages;\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t timedout;\n\tu64_stats_t spi_sync;\n\tu64_stats_t spi_sync_immediate;\n\tu64_stats_t spi_async;\n\tu64_stats_t bytes;\n\tu64_stats_t bytes_rx;\n\tu64_stats_t bytes_tx;\n\tu64_stats_t transfer_bytes_histo[17];\n\tu64_stats_t transfers_split_maxsize;\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct spmi_controller {\n\tstruct device dev;\n\tunsigned int nr;\n\tint (*cmd)(struct spmi_controller *, u8, u8);\n\tint (*read_cmd)(struct spmi_controller *, u8, u8, u16, u8 *, size_t);\n\tint (*write_cmd)(struct spmi_controller *, u8, u8, u16, const u8 *, size_t);\n};\n\nstruct spmi_device {\n\tstruct device dev;\n\tstruct spmi_controller *ctrl;\n\tu8 usid;\n};\n\nstruct spmi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct spmi_device *);\n\tvoid (*remove)(struct spmi_device *);\n\tvoid (*shutdown)(struct spmi_device *);\n};\n\nstruct spmi_pmic_arb {\n\tvoid *rd_base;\n\tvoid *wr_base;\n\tvoid *core;\n\tresource_size_t core_size;\n\tvoid *apid_map;\n\tu8 channel;\n\tu8 ee;\n\tconst struct pmic_arb_ver_ops *ver_ops;\n\tint max_periphs;\n\tstruct spmi_pmic_arb_bus *buses[4];\n\tint buses_available;\n};\n\nstruct spmi_pmic_arb_bus {\n\tstruct spmi_pmic_arb *pmic_arb;\n\tstruct irq_domain *domain;\n\tvoid *intr;\n\tvoid *cnfg;\n\tvoid *apid_owner;\n\tstruct spmi_controller *spmic;\n\traw_spinlock_t lock;\n\tu16 base_apid;\n\tint apid_count;\n\tu32 *mapping_table;\n\tlong unsigned int mapping_table_valid[8];\n\tu16 *ppid_to_apid;\n\tu16 last_apid;\n\tstruct apid_data *apid_data;\n\tu16 min_apid;\n\tu16 max_apid;\n\tint irq;\n\tu8 id;\n};\n\nstruct spmi_pmic_arb_qpnpint_type {\n\tu8 type;\n\tu8 polarity_high;\n\tu8 polarity_low;\n};\n\nstruct spmi_voltage_set_points;\n\nstruct spmi_regulator {\n\tstruct regulator_desc desc;\n\tstruct device *dev;\n\tstruct delayed_work ocp_work;\n\tstruct regmap *regmap;\n\tstruct spmi_voltage_set_points *set_points;\n\tenum spmi_regulator_logical_type logical_type;\n\tint ocp_irq;\n\tint ocp_count;\n\tint ocp_max_retries;\n\tint ocp_retry_delay_ms;\n\tint hpm_min_load;\n\tint slew_rate;\n\tktime_t vs_enable_time;\n\tu16 base;\n\tstruct list_head node;\n};\n\nstruct spmi_regulator_data {\n\tconst char *name;\n\tu16 base;\n\tconst char *supply;\n\tconst char *ocp;\n\tu16 force_type;\n};\n\nstruct spmi_regulator_init_data {\n\tunsigned int pin_ctrl_enable;\n\tunsigned int pin_ctrl_hpm;\n\tenum spmi_vs_soft_start_str vs_soft_start_strength;\n};\n\nstruct spmi_regulator_mapping {\n\tenum spmi_regulator_type type;\n\tenum spmi_regulator_subtype subtype;\n\tenum spmi_regulator_logical_type logical_type;\n\tu32 revision_min;\n\tu32 revision_max;\n\tconst struct regulator_ops *ops;\n\tstruct spmi_voltage_set_points *set_points;\n\tint hpm_min_load;\n};\n\nstruct spmi_voltage_range {\n\tint min_uV;\n\tint max_uV;\n\tint step_uV;\n\tint set_point_min_uV;\n\tint set_point_max_uV;\n\tunsigned int n_voltages;\n\tu8 range_sel;\n};\n\nstruct spmi_voltage_set_points {\n\tconst struct spmi_voltage_range *range;\n\tint count;\n\tunsigned int n_voltages;\n};\n\nstruct sprd_clk_common {\n\tstruct regmap *regmap;\n\tu32 reg;\n\tstruct clk_hw hw;\n};\n\nstruct sprd_clk_desc {\n\tstruct sprd_clk_common **clk_clks;\n\tlong unsigned int num_clk_clks;\n\tstruct clk_hw_onecell_data *hw_clks;\n};\n\nstruct sprd_mux_ssel {\n\tu8 shift;\n\tu8 width;\n\tconst u8 *table;\n};\n\nstruct sprd_div_internal {\n\ts32 offset;\n\tu8 shift;\n\tu8 width;\n};\n\nstruct sprd_comp {\n\tstruct sprd_mux_ssel mux;\n\tstruct sprd_div_internal div;\n\tstruct sprd_clk_common common;\n};\n\nstruct sprd_div {\n\tstruct sprd_div_internal div;\n\tstruct sprd_clk_common common;\n};\n\nstruct sprd_gate {\n\tu32 enable_mask;\n\tu16 flags;\n\tu16 sc_offset;\n\tu16 udelay;\n\tstruct sprd_clk_common common;\n};\n\nstruct sprd_mux {\n\tstruct sprd_mux_ssel mux;\n\tstruct sprd_clk_common common;\n};\n\nstruct sprd_pll {\n\tu32 regs_num;\n\tconst u64 *itable;\n\tconst struct clk_bit_field *factors;\n\tu16 udelay;\n\tu16 k1;\n\tu16 k2;\n\tu16 fflag;\n\tu64 fvco;\n\tstruct sprd_clk_common common;\n};\n\nstruct squashfs_base_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n};\n\nstruct squashfs_cache_entry;\n\nstruct squashfs_cache {\n\tchar *name;\n\tint entries;\n\tint curr_blk;\n\tint next_blk;\n\tint num_waiters;\n\tint unused;\n\tint block_size;\n\tint pages;\n\tspinlock_t lock;\n\twait_queue_head_t wait_queue;\n\tstruct squashfs_cache_entry *entry;\n};\n\nstruct squashfs_page_actor;\n\nstruct squashfs_cache_entry {\n\tu64 block;\n\tint length;\n\tint refcount;\n\tu64 next_index;\n\tint pending;\n\tint error;\n\tint num_waiters;\n\twait_queue_head_t wait_queue;\n\tstruct squashfs_cache *cache;\n\tvoid **data;\n\tstruct squashfs_page_actor *actor;\n};\n\nstruct squashfs_sb_info;\n\nstruct squashfs_decompressor {\n\tvoid * (*init)(struct squashfs_sb_info *, void *);\n\tvoid * (*comp_opts)(struct squashfs_sb_info *, void *, int);\n\tvoid (*free)(void *);\n\tint (*decompress)(struct squashfs_sb_info *, void *, struct bio *, int, int, struct squashfs_page_actor *);\n\tint id;\n\tchar *name;\n\tint alloc_buffer;\n\tint supported;\n};\n\nstruct squashfs_decompressor_thread_ops {\n\tvoid * (*create)(struct squashfs_sb_info *, void *);\n\tvoid (*destroy)(struct squashfs_sb_info *);\n\tint (*decompress)(struct squashfs_sb_info *, struct bio *, int, int, struct squashfs_page_actor *);\n\tint (*max_decompressors)(void);\n};\n\nstruct squashfs_dev_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 rdev;\n};\n\nstruct squashfs_dir_entry {\n\t__le16 offset;\n\t__le16 inode_number;\n\t__le16 type;\n\t__le16 size;\n\tchar name[0];\n};\n\nstruct squashfs_dir_header {\n\t__le32 count;\n\t__le32 start_block;\n\t__le32 inode_number;\n};\n\nstruct squashfs_dir_index {\n\t__le32 index;\n\t__le32 start_block;\n\t__le32 size;\n\tunsigned char name[0];\n};\n\nstruct squashfs_dir_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 start_block;\n\t__le32 nlink;\n\t__le16 file_size;\n\t__le16 offset;\n\t__le32 parent_inode;\n};\n\nstruct squashfs_fragment_entry {\n\t__le64 start_block;\n\t__le32 size;\n\tunsigned int unused;\n};\n\nstruct squashfs_ldev_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 rdev;\n\t__le32 xattr;\n};\n\nstruct squashfs_symlink_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 symlink_size;\n\tchar symlink[0];\n};\n\nstruct squashfs_reg_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 start_block;\n\t__le32 fragment;\n\t__le32 offset;\n\t__le32 file_size;\n\t__le16 block_list[0];\n};\n\nstruct squashfs_lreg_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le64 start_block;\n\t__le64 file_size;\n\t__le64 sparse;\n\t__le32 nlink;\n\t__le32 fragment;\n\t__le32 offset;\n\t__le32 xattr;\n\t__le16 block_list[0];\n};\n\nstruct squashfs_ldir_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 file_size;\n\t__le32 start_block;\n\t__le32 parent_inode;\n\t__le16 i_count;\n\t__le16 offset;\n\t__le32 xattr;\n\tstruct squashfs_dir_index index[0];\n};\n\nstruct squashfs_ipc_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n};\n\nstruct squashfs_lipc_inode {\n\t__le16 inode_type;\n\t__le16 mode;\n\t__le16 uid;\n\t__le16 guid;\n\t__le32 mtime;\n\t__le32 inode_number;\n\t__le32 nlink;\n\t__le32 xattr;\n};\n\nunion squashfs_inode {\n\tstruct squashfs_base_inode base;\n\tstruct squashfs_dev_inode dev;\n\tstruct squashfs_ldev_inode ldev;\n\tstruct squashfs_symlink_inode symlink;\n\tstruct squashfs_reg_inode reg;\n\tstruct squashfs_lreg_inode lreg;\n\tstruct squashfs_dir_inode dir;\n\tstruct squashfs_ldir_inode ldir;\n\tstruct squashfs_ipc_inode ipc;\n\tstruct squashfs_lipc_inode lipc;\n};\n\nstruct squashfs_inode_info {\n\tu64 start;\n\tint offset;\n\tu64 xattr;\n\tunsigned int xattr_size;\n\tint xattr_count;\n\tint parent;\n\tunion {\n\t\tstruct {\n\t\t\tu64 fragment_block;\n\t\t\tint fragment_size;\n\t\t\tint fragment_offset;\n\t\t\tu64 block_list_start;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dir_idx_start;\n\t\t\tint dir_idx_offset;\n\t\t\tint dir_idx_cnt;\n\t\t};\n\t};\n\tstruct inode vfs_inode;\n};\n\nstruct squashfs_mount_opts {\n\tenum Opt_errors errors;\n\tconst struct squashfs_decompressor_thread_ops *thread_ops;\n\tint thread_num;\n};\n\nstruct squashfs_page_actor {\n\tunion {\n\t\tvoid **buffer;\n\t\tstruct page **page;\n\t};\n\tvoid *pageaddr;\n\tvoid *tmp_buffer;\n\tvoid * (*squashfs_first_page)(struct squashfs_page_actor *);\n\tvoid * (*squashfs_next_page)(struct squashfs_page_actor *);\n\tvoid (*squashfs_finish_page)(struct squashfs_page_actor *);\n\tstruct page *last_page;\n\tint pages;\n\tint length;\n\tint next_page;\n\tint alloc_buffer;\n\tint returned_pages;\n\tlong unsigned int next_index;\n};\n\nstruct squashfs_sb_info {\n\tconst struct squashfs_decompressor *decompressor;\n\tint devblksize;\n\tint devblksize_log2;\n\tstruct squashfs_cache *block_cache;\n\tstruct squashfs_cache *fragment_cache;\n\tstruct squashfs_cache *read_page;\n\tstruct address_space *cache_mapping;\n\tint next_meta_index;\n\t__le64 *id_table;\n\t__le64 *fragment_index;\n\t__le64 *xattr_id_table;\n\tstruct mutex meta_index_mutex;\n\tstruct meta_index *meta_index;\n\tvoid *stream;\n\t__le64 *inode_lookup_table;\n\tu64 inode_table;\n\tu64 directory_table;\n\tu64 xattr_table;\n\tunsigned int block_size;\n\tshort unsigned int block_log;\n\tlong long int bytes_used;\n\tunsigned int inodes;\n\tunsigned int fragments;\n\tunsigned int xattr_ids;\n\tunsigned int ids;\n\tbool panic_on_errors;\n\tconst struct squashfs_decompressor_thread_ops *thread_ops;\n\tint max_thread_num;\n};\n\nstruct squashfs_stream {\n\tvoid *stream;\n\tstruct mutex mutex;\n};\n\nstruct squashfs_super_block {\n\t__le32 s_magic;\n\t__le32 inodes;\n\t__le32 mkfs_time;\n\t__le32 block_size;\n\t__le32 fragments;\n\t__le16 compression;\n\t__le16 block_log;\n\t__le16 flags;\n\t__le16 no_ids;\n\t__le16 s_major;\n\t__le16 s_minor;\n\t__le64 root_inode;\n\t__le64 bytes_used;\n\t__le64 id_table_start;\n\t__le64 xattr_id_table_start;\n\t__le64 inode_table_start;\n\t__le64 directory_table_start;\n\t__le64 fragment_table_start;\n\t__le64 lookup_table_start;\n};\n\nstruct squashfs_xattr_id_table {\n\t__le64 xattr_table_start;\n\t__le32 xattr_ids;\n\t__le32 unused;\n};\n\nstruct sr_loc {\n\tenum sr_loc_attr loc;\n\tenum vcpu_sysreg map_reg;\n\tu64 (*xlate)(u64);\n};\n\nstruct sr_pcie_phy_core;\n\nstruct sr_pcie_phy {\n\tstruct sr_pcie_phy_core *core;\n\tunsigned int index;\n\tstruct phy *phy;\n};\n\nstruct sr_pcie_phy_core {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct regmap *cdru;\n\tstruct regmap *mhb;\n\tu32 pipemux;\n\tstruct sr_pcie_phy phys[9];\n};\n\nstruct sr_thermal;\n\nstruct sr_tmon {\n\tunsigned int crit_temp;\n\tunsigned int tmon_id;\n\tstruct sr_thermal *priv;\n};\n\nstruct sr_thermal {\n\tvoid *regs;\n\tunsigned int max_crit_temp;\n\tstruct sr_tmon tmon[6];\n};\n\nstruct sram_config {\n\tint (*init)(void);\n\tbool map_only_reserved;\n};\n\nstruct sram_partition;\n\nstruct sram_dev {\n\tconst struct sram_config *config;\n\tstruct device *dev;\n\tvoid *virt_base;\n\tbool no_memory_wc;\n\tstruct gen_pool *pool;\n\tstruct sram_partition *partition;\n\tu32 partitions;\n};\n\nstruct sram_partition {\n\tvoid *base;\n\tstruct gen_pool *pool;\n\tstruct bin_attribute battr;\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct sram_reserve {\n\tstruct list_head list;\n\tu32 start;\n\tu32 size;\n\tstruct resource res;\n\tbool export;\n\tbool pool;\n\tbool protect_exec;\n\tconst char *label;\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct ssp_response_iu {\n\tu8 _r_a[10];\n\tu8 datapres: 2;\n\tu8 _r_b: 6;\n\tu8 status;\n\tu32 _r_c;\n\t__be32 sense_data_len;\n\t__be32 response_data_len;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_resp_data;\n\t\t\tu8 resp_data[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_sense_data;\n\t\t\tu8 sense_data[0];\n\t\t};\n\t};\n};\n\nstruct sst25l_flash {\n\tstruct spi_device *spi;\n\tstruct mutex lock;\n\tstruct mtd_info mtd;\n};\n\nstruct ssusb_mtk {\n\tstruct device *dev;\n\tstruct mtu3 *u3d;\n\tvoid *mac_base;\n\tvoid *ippc_base;\n\tstruct phy **phys;\n\tint num_phys;\n\tint wakeup_irq;\n\tstruct regulator *vusb33;\n\tstruct clk_bulk_data clks[6];\n\tstruct otg_switch_mtk otg_switch;\n\tenum usb_dr_mode dr_mode;\n\tbool is_host;\n\tint u2_ports;\n\tint u3_ports;\n\tint u2p_dis_msk;\n\tint u3p_dis_msk;\n\tstruct dentry *dbgfs_root;\n\tbool uwk_en;\n\tstruct regmap *uwk;\n\tu32 uwk_reg_base;\n\tu32 uwk_vers;\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[0];\n};\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tu64 data[0];\n};\n\nstruct stack_record {\n\tstruct list_head hash_list;\n\tu32 hash;\n\tu32 size;\n\tunion handle_parts handle;\n\trefcount_t count;\n\tunion {\n\t\tlong unsigned int entries[64];\n\t\tstruct {\n\t\t\tstruct list_head free_list;\n\t\t\tlong unsigned int rcu_state;\n\t\t};\n\t};\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\nstruct stage2_age_data {\n\tbool mkold;\n\tbool young;\n};\n\nstruct stage2_attr_data {\n\tkvm_pte_t attr_set;\n\tkvm_pte_t attr_clr;\n\tkvm_pte_t pte;\n\ts8 level;\n};\n\nstruct stage2_map_data {\n\tconst u64 phys;\n\tkvm_pte_t attr;\n\tu8 owner_id;\n\tkvm_pte_t *anchor;\n\tkvm_pte_t *childp;\n\tstruct kvm_s2_mmu *mmu;\n\tvoid *memcache;\n\tbool force_pte;\n\tbool annotation;\n};\n\nstruct start_info {\n\tchar magic[32];\n\tlong unsigned int nr_pages;\n\tlong unsigned int shared_info;\n\tuint32_t flags;\n\txen_pfn_t store_mfn;\n\tuint32_t store_evtchn;\n\tunion {\n\t\tstruct {\n\t\t\txen_pfn_t mfn;\n\t\t\tuint32_t evtchn;\n\t\t} domU;\n\t\tstruct {\n\t\t\tuint32_t info_off;\n\t\t\tuint32_t info_size;\n\t\t} dom0;\n\t} console;\n\tlong unsigned int pt_base;\n\tlong unsigned int nr_pt_frames;\n\tlong unsigned int mfn_list;\n\tlong unsigned int mod_start;\n\tlong unsigned int mod_len;\n\tint8_t cmd_line[1024];\n\tlong unsigned int first_p2m_pfn;\n\tlong unsigned int nr_p2m_frames;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\tlong unsigned int st_dev;\n\tlong unsigned int st_ino;\n\tunsigned int st_mode;\n\tunsigned int st_nlink;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tlong unsigned int st_rdev;\n\tlong unsigned int __pad1;\n\tlong int st_size;\n\tint st_blksize;\n\tint __pad2;\n\tlong int st_blocks;\n\tlong int st_atime;\n\tlong unsigned int st_atime_nsec;\n\tlong int st_mtime;\n\tlong unsigned int st_mtime_nsec;\n\tlong int st_ctime;\n\tlong unsigned int st_ctime_nsec;\n\tunsigned int __unused4;\n\tunsigned int __unused5;\n};\n\nstruct stat64 {\n\tcompat_u64 st_dev;\n\tunsigned char __pad0[4];\n\tcompat_ulong_t __st_ino;\n\tcompat_uint_t st_mode;\n\tcompat_uint_t st_nlink;\n\tcompat_ulong_t st_uid;\n\tcompat_ulong_t st_gid;\n\tcompat_u64 st_rdev;\n\tunsigned char __pad3[4];\n\tcompat_s64 st_size;\n\tcompat_ulong_t st_blksize;\n\tcompat_u64 st_blocks;\n\tcompat_ulong_t st_atime;\n\tcompat_ulong_t st_atime_nsec;\n\tcompat_ulong_t st_mtime;\n\tcompat_ulong_t st_mtime_nsec;\n\tcompat_ulong_t st_ctime;\n\tcompat_ulong_t st_ctime_nsec;\n\tcompat_u64 st_ino;\n};\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct tracer_stat;\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct statfs {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__kernel_long_t f_blocks;\n\t__kernel_long_t f_bfree;\n\t__kernel_long_t f_bavail;\n\t__kernel_long_t f_files;\n\t__kernel_long_t f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct statfs64 {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct static_call_key {\n\tvoid *func;\n};\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct static_tree_desc_s {\n\tconst ct_data *static_tree;\n\tconst int *extra_bits;\n\tint extra_base;\n\tint elems;\n\tint max_length;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct stm32_desc_function {\n\tconst char *name;\n\tconst unsigned char num;\n};\n\nstruct stm32_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tconst struct stm32_desc_function functions[19];\n\tconst unsigned int pkg;\n};\n\nstruct stm32_div_cfg {\n\tu16 offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tu8 ready;\n\tconst struct clk_div_table *table;\n};\n\nstruct stm32_firewall_controller;\n\nstruct stm32_firewall {\n\tstruct stm32_firewall_controller *firewall_ctrl;\n\tu32 extra_args[5];\n\tconst char *entry;\n\tsize_t extra_args_size;\n\tu32 firewall_id;\n};\n\nstruct stm32_firewall_controller {\n\tconst char *name;\n\tstruct device *dev;\n\tvoid *mmio;\n\tstruct list_head entry;\n\tunsigned int type;\n\tunsigned int max_entries;\n\tint (*grant_access)(struct stm32_firewall_controller *, u32);\n\tvoid (*release_access)(struct stm32_firewall_controller *, u32);\n\tint (*grant_memory_range_access)(struct stm32_firewall_controller *, phys_addr_t, size_t);\n};\n\nstruct stm32_gate_cfg {\n\tu16 offset;\n\tu8 bit_idx;\n\tu8 set_clr;\n};\n\nstruct stm32_pin_backup {\n\tunsigned int alt: 4;\n\tunsigned int mode: 2;\n\tunsigned int bias: 2;\n\tunsigned int speed: 2;\n\tunsigned int drive: 1;\n\tunsigned int value: 1;\n\tunsigned int advcfg: 4;\n\tunsigned int skew_delay: 4;\n};\n\nstruct stm32_gpio_bank {\n\tvoid *base;\n\tstruct reset_control *rstc;\n\tspinlock_t lock;\n\tstruct gpio_chip gpio_chip;\n\tstruct pinctrl_gpio_range range;\n\tstruct fwnode_handle *fwnode;\n\tstruct irq_domain *domain;\n\tu32 bank_nr;\n\tu32 bank_ioport_nr;\n\tstruct stm32_pin_backup pin_backup[16];\n\tu8 irq_type[16];\n\tbool secure_control;\n\tbool io_sync_control;\n\tbool rif_control;\n};\n\nstruct stm32_hdp {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct gpio_generic_chip gpio_chip;\n\tu32 mux_conf;\n\tu32 gposet_conf;\n\tconst char * const *func_name;\n};\n\nstruct stm32_iwdg_data;\n\nstruct stm32_iwdg {\n\tstruct watchdog_device wdd;\n\tconst struct stm32_iwdg_data *data;\n\tvoid *regs;\n\tstruct clk *clk_lsi;\n\tstruct clk *clk_pclk;\n\tunsigned int rate;\n};\n\nstruct stm32_iwdg_data {\n\tbool has_pclk;\n\tbool has_early_wakeup;\n\tu32 max_prescaler;\n};\n\nstruct stm32_lp_private {\n\tstruct regmap *reg;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct clock_event_device clkevt;\n\tlong unsigned int period;\n\tu32 psc;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tu32 version;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct stm32_lptimer {\n\tstruct clk *clk;\n\tstruct regmap *regmap;\n\tbool has_encoder;\n\tunsigned int num_cc_chans;\n\tu32 version;\n};\n\nstruct stm32_mux_cfg {\n\tu16 offset;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tu32 *table;\n\tu8 ready;\n};\n\nstruct stm32_pinctrl_group;\n\nstruct stm32_pinctrl_match_data;\n\nstruct stm32_pinctrl {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct pinctrl_desc pctl_desc;\n\tstruct stm32_pinctrl_group *groups;\n\tunsigned int ngroups;\n\tconst char **grp_names;\n\tstruct stm32_gpio_bank *banks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int nbanks;\n\tconst struct stm32_pinctrl_match_data *match_data;\n\tstruct irq_domain *domain;\n\tstruct regmap *regmap;\n\tstruct regmap_field *irqmux[16];\n\tstruct hwspinlock *hwlock;\n\tstruct stm32_desc_pin *pins;\n\tu32 npins;\n\tu32 pkg;\n\tu16 irqmux_map;\n\tspinlock_t irqmux_lock;\n};\n\nstruct stm32_pinctrl_group {\n\tconst char *name;\n\tlong unsigned int config;\n\tunsigned int pin;\n};\n\nstruct stm32_pinctrl_match_data {\n\tconst struct stm32_desc_pin *pins;\n\tconst unsigned int npins;\n\tbool secure_control;\n\tbool io_sync_control;\n\tbool rif_control;\n};\n\nstruct stm32_usart_info;\n\nstruct stm32_port {\n\tstruct uart_port port;\n\tstruct clk *clk;\n\tconst struct stm32_usart_info *info;\n\tstruct dma_chan *rx_ch;\n\tdma_addr_t rx_dma_buf;\n\tunsigned char *rx_buf;\n\tstruct dma_chan *tx_ch;\n\tdma_addr_t tx_dma_buf;\n\tunsigned char *tx_buf;\n\tu32 cr1_irq;\n\tu32 cr3_irq;\n\tint last_res;\n\tbool tx_dma_busy;\n\tbool rx_dma_busy;\n\tbool throttled;\n\tbool hw_flow_control;\n\tbool swap;\n\tbool fifoen;\n\tint rxftcfg;\n\tint txftcfg;\n\tbool wakeup_src;\n\tint rdr_mask;\n\tstruct mctrl_gpios *gpios;\n\tstruct dma_tx_state rx_dma_state;\n};\n\nstruct stm32_rcc_match_data {\n\tstruct clk_hw_onecell_data *hw_clks;\n\tunsigned int num_clocks;\n\tconst struct clock_config *tab_clocks;\n\tunsigned int maxbinding;\n\tstruct clk_stm32_clock_data *clock_data;\n\tstruct clk_stm32_reset_data *reset_data;\n\tint (*check_security)(struct device_node *, void *, const struct clock_config *);\n\tint (*multi_mux)(void *, const struct clock_config *);\n};\n\nstruct stm32_reset_cfg {\n\tu16 offset;\n\tu8 bit_idx;\n\tbool set_clr;\n};\n\nstruct stm32_reset_data {\n\tspinlock_t lock;\n\tstruct reset_controller_dev rcdev;\n\tvoid *membase;\n\tu32 clear_offset;\n\tconst struct stm32_reset_cfg **reset_lines;\n};\n\nstruct stm32_rifsc_resources_names {\n\tconst char **device_names;\n\tconst char **initiator_names;\n};\n\nstruct stm32_rng_config {\n\tu32 cr;\n\tu32 nscr;\n\tu32 htcr;\n};\n\nstruct stm32_rng_data {\n\tuint max_clock_rate;\n\tuint nb_clock;\n\tu32 cr;\n\tu32 nscr;\n\tu32 htcr;\n\tbool has_cond_reset;\n};\n\nstruct stm32_rng_private {\n\tstruct hwrng rng;\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk_bulk_data *clk_bulk;\n\tstruct reset_control *rst;\n\tstruct stm32_rng_config pm_conf;\n\tconst struct stm32_rng_data *data;\n\tbool ced;\n\tbool lock_conf;\n};\n\nstruct stm32_usart_config {\n\tu8 uart_enable_bit;\n\tbool has_7bits_data;\n\tbool has_swap;\n\tbool has_wakeup;\n\tbool has_fifo;\n};\n\nstruct stm32_usart_offsets {\n\tu16 cr1;\n\tu16 cr2;\n\tu16 cr3;\n\tu16 brr;\n\tu16 gtpr;\n\tu16 rtor;\n\tu16 rqr;\n\tu16 isr;\n\tu16 icr;\n\tu16 rdr;\n\tu16 tdr;\n\tu16 presc;\n\tu16 hwcfgr1;\n};\n\nstruct stm32_usart_info {\n\tstruct stm32_usart_offsets ofs;\n\tstruct stm32_usart_config cfg;\n};\n\nstruct stm32_usart_thresh_ratio {\n\tint mul;\n\tint div;\n};\n\nstruct stm32mp_exti_bank {\n\tu32 imr_ofst;\n\tu32 rtsr_ofst;\n\tu32 ftsr_ofst;\n\tu32 swier_ofst;\n\tu32 rpr_ofst;\n\tu32 fpr_ofst;\n\tu32 trg_ofst;\n\tu32 seccfgr_ofst;\n};\n\nstruct stm32mp_exti_host_data;\n\nstruct stm32mp_exti_chip_data {\n\tstruct stm32mp_exti_host_data *host_data;\n\tconst struct stm32mp_exti_bank *reg_bank;\n\tstruct raw_spinlock rlock;\n\tu32 wake_active;\n\tu32 mask_cache;\n\tu32 rtsr_cache;\n\tu32 ftsr_cache;\n\tu32 event_reserved;\n};\n\nstruct stm32mp_exti_drv_data {\n\tconst struct stm32mp_exti_bank **exti_banks;\n\tconst u8 *desc_irqs;\n\tu32 bank_nr;\n};\n\nstruct stm32mp_exti_host_data {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct stm32mp_exti_chip_data *chips_data;\n\tconst struct stm32mp_exti_drv_data *drv_data;\n\tstruct hwspinlock *hwlock;\n\tbool dt_has_irqs_desc;\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct stratix10_async_chan {\n\tlong unsigned int async_client_id;\n\tstruct ida job_id_pool;\n};\n\nstruct stratix10_async_ctrl {\n\tbool initialized;\n\tvoid (*invoke_fn)(struct stratix10_async_ctrl *, const struct arm_smccc_1_2_regs *, struct arm_smccc_1_2_regs *);\n\tstruct ida async_id_pool;\n\tatomic_t common_achan_refcount;\n\tstruct stratix10_async_chan *common_async_chan;\n\tspinlock_t trx_list_lock;\n\tstruct hlist_head trx_list[8];\n};\n\nstruct stratix10_clock_data {\n\tvoid *base;\n\tstruct clk_hw_onecell_data clk_data;\n};\n\nstruct stratix10_gate_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst struct clk_parent_data *parent_data;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int gate_reg;\n\tu8 gate_idx;\n\tlong unsigned int div_reg;\n\tu8 div_offset;\n\tu8 div_width;\n\tlong unsigned int bypass_reg;\n\tu8 bypass_shift;\n\tu8 fixed_div;\n};\n\nstruct stratix10_perip_c_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst struct clk_parent_data *parent_data;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n};\n\nstruct stratix10_perip_cnt_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent_name;\n\tconst struct clk_parent_data *parent_data;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n\tu8 fixed_divider;\n\tlong unsigned int bypass_reg;\n\tlong unsigned int bypass_shift;\n};\n\nstruct stratix10_pll_clock {\n\tunsigned int id;\n\tconst char *name;\n\tconst struct clk_parent_data *parent_data;\n\tu8 num_parents;\n\tlong unsigned int flags;\n\tlong unsigned int offset;\n};\n\nstruct stratix10_svc {\n\tstruct platform_device *stratix10_svc_rsu;\n\tstruct platform_device *intel_svc_fcs;\n};\n\ntypedef void (*async_callback_t)(void *);\n\nstruct stratix10_svc_client_msg;\n\nstruct stratix10_svc_async_handler {\n\tu8 transaction_id;\n\tstruct stratix10_async_chan *achan;\n\tvoid *cb_arg;\n\tasync_callback_t cb;\n\tstruct stratix10_svc_client_msg *msg;\n\tstruct hlist_node next;\n\tstruct arm_smccc_1_2_regs res;\n};\n\nstruct stratix10_svc_cb_data {\n\tu32 status;\n\tvoid *kaddr1;\n\tvoid *kaddr2;\n\tvoid *kaddr3;\n};\n\nstruct stratix10_svc_controller;\n\nstruct stratix10_svc_client;\n\nstruct stratix10_svc_chan {\n\tstruct stratix10_svc_controller *ctrl;\n\tstruct stratix10_svc_client *scl;\n\tchar *name;\n\tspinlock_t lock;\n\tstruct stratix10_async_chan *async_chan;\n};\n\nstruct stratix10_svc_client {\n\tstruct device *dev;\n\tvoid (*receive_cb)(struct stratix10_svc_client *, struct stratix10_svc_cb_data *);\n\tvoid *priv;\n};\n\nstruct stratix10_svc_client_msg {\n\tvoid *payload;\n\tsize_t payload_length;\n\tvoid *payload_output;\n\tsize_t payload_length_output;\n\tenum stratix10_svc_command_code command;\n\tu64 arg[3];\n};\n\nstruct stratix10_svc_command_config_type {\n\tu32 flags;\n};\n\ntypedef void svc_invoke_fn(long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, struct arm_smccc_res *);\n\nstruct stratix10_svc_controller {\n\tstruct device *dev;\n\tstruct stratix10_svc_chan *chans;\n\tint num_chans;\n\tint num_active_client;\n\tstruct list_head node;\n\tstruct gen_pool *genpool;\n\tstruct task_struct *task;\n\tstruct kfifo svc_fifo;\n\tstruct completion complete_status;\n\tspinlock_t svc_fifo_lock;\n\tsvc_invoke_fn *invoke_fn;\n\tstruct stratix10_svc *svc;\n\tstruct stratix10_async_ctrl actrl;\n};\n\nstruct stratix10_svc_data {\n\tstruct stratix10_svc_chan *chan;\n\tphys_addr_t paddr;\n\tsize_t size;\n\tphys_addr_t paddr_output;\n\tsize_t size_output;\n\tu32 command;\n\tu32 flag;\n\tu64 arg[3];\n};\n\nstruct stratix10_svc_data_mem {\n\tvoid *vaddr;\n\tphys_addr_t paddr;\n\tsize_t size;\n\tstruct list_head node;\n};\n\nstruct stratix10_svc_sh_memory {\n\tstruct completion sync_complete;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tsvc_invoke_fn *invoke_fn;\n};\n\nstruct streamid_data {\n\tunion {\n\t\tu8 dmac[6];\n\t\tu8 smac[6];\n\t};\n\tu16 vid_vidm_tg;\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\nstruct sugov_policy;\n\nstruct sugov_cpu {\n\tstruct update_util_data update_util;\n\tstruct sugov_policy *sg_policy;\n\tunsigned int cpu;\n\tbool iowait_boost_pending;\n\tunsigned int iowait_boost;\n\tu64 last_update;\n\tlong unsigned int util;\n\tlong unsigned int bw_min;\n\tlong unsigned int saved_idle_calls;\n};\n\nstruct sugov_tunables;\n\nstruct sugov_policy {\n\tstruct cpufreq_policy *policy;\n\tstruct sugov_tunables *tunables;\n\tstruct list_head tunables_hook;\n\traw_spinlock_t update_lock;\n\tu64 last_freq_update_time;\n\ts64 freq_update_delay_ns;\n\tunsigned int next_freq;\n\tunsigned int cached_raw_freq;\n\tstruct irq_work irq_work;\n\tstruct kthread_work work;\n\tstruct mutex work_lock;\n\tstruct kthread_worker worker;\n\tstruct task_struct *thread;\n\tbool work_in_progress;\n\tbool limits_changed;\n\tbool need_freq_update;\n};\n\nstruct sugov_tunables {\n\tstruct gov_attr_set attr_set;\n\tunsigned int rate_limit_us;\n};\n\nstruct summary_data {\n\tstruct seq_file *s;\n\tstruct regulator_dev *parent;\n\tint level;\n};\n\nstruct summary_lock_data {\n\tstruct ww_acquire_ctx *ww_ctx;\n\tstruct regulator_dev **new_contended_rdev;\n\tstruct regulator_dev **old_contended_rdev;\n};\n\nstruct sun20i_ppu_desc {\n\tconst char * const *names;\n\tunsigned int num_domains;\n};\n\nstruct sun20i_ppu_pd {\n\tstruct generic_pm_domain genpd;\n\tvoid *base;\n};\n\nstruct sun20i_regulator_data {\n\tconst struct regulator_desc *descs;\n\tunsigned int ndescs;\n};\n\nstruct sun4i_usb_phy {\n\tstruct phy *phy;\n\tvoid *pmu;\n\tstruct regulator *vbus;\n\tstruct reset_control *reset;\n\tstruct clk *clk;\n\tstruct clk *clk2;\n\tbool regulator_on;\n\tint index;\n};\n\nstruct sun4i_usb_phy_cfg {\n\tint hsic_index;\n\tu32 disc_thresh;\n\tu32 hci_phy_ctl_clear;\n\tu8 phyctl_offset;\n\tbool dedicated_clocks;\n\tbool phy0_dual_route;\n\tbool needs_phy2_siddq;\n\tbool siddq_in_base;\n\tbool poll_vbusen;\n\tint missing_phys;\n};\n\nstruct sun4i_usb_phy_data {\n\tvoid *base;\n\tconst struct sun4i_usb_phy_cfg *cfg;\n\tenum usb_dr_mode dr_mode;\n\tspinlock_t reg_lock;\n\tint num_phys;\n\tstruct sun4i_usb_phy phys[4];\n\tstruct extcon_dev *extcon;\n\tbool phy0_init;\n\tstruct gpio_desc *id_det_gpio;\n\tstruct gpio_desc *vbus_det_gpio;\n\tstruct power_supply *vbus_power_supply;\n\tstruct notifier_block vbus_power_nb;\n\tbool vbus_power_nb_registered;\n\tbool force_session_end;\n\tint id_det_irq;\n\tint vbus_det_irq;\n\tint id_det;\n\tint vbus_det;\n\tstruct delayed_work detect;\n};\n\nstruct sun6i_msgbox {\n\tstruct mbox_controller controller;\n\tstruct clk *clk;\n\tspinlock_t lock;\n\tvoid *regs;\n};\n\nstruct sun6i_r_intc_variant {\n\tu32 first_mux_irq;\n\tu32 nr_mux_irqs;\n\tu32 mux_valid[4];\n};\n\nstruct sun6i_rtc_clk_data {\n\tlong unsigned int rc_osc_rate;\n\tunsigned int fixed_prescaler: 16;\n\tunsigned int has_prescaler: 1;\n\tunsigned int has_out_clk: 1;\n\tunsigned int has_losc_en: 1;\n\tunsigned int has_auto_swt: 1;\n};\n\nstruct sun6i_rtc_dev {\n\tstruct rtc_device *rtc;\n\tconst struct sun6i_rtc_clk_data *data;\n\tvoid *base;\n\tint irq;\n\ttime64_t alarm;\n\tlong unsigned int flags;\n\tstruct clk_hw hw;\n\tstruct clk_hw *int_osc;\n\tstruct clk *losc;\n\tstruct clk *ext_losc;\n\tspinlock_t lock;\n};\n\nstruct sun6i_rtc_match_data {\n\tbool have_ext_osc32k: 1;\n\tbool have_iosc_calibration: 1;\n\tbool rtc_32k_single_parent: 1;\n\tconst struct clk_parent_data *osc32k_fanout_parents;\n\tu8 osc32k_fanout_nparents;\n};\n\nstruct sun6i_spi_cfg;\n\nstruct sun6i_spi {\n\tstruct spi_controller *host;\n\tvoid *base_addr;\n\tdma_addr_t dma_addr_rx;\n\tdma_addr_t dma_addr_tx;\n\tstruct clk *hclk;\n\tstruct clk *mclk;\n\tstruct reset_control *rstc;\n\tstruct completion done;\n\tstruct completion dma_rx_done;\n\tconst u8 *tx_buf;\n\tu8 *rx_buf;\n\tint len;\n\tconst struct sun6i_spi_cfg *cfg;\n};\n\nstruct sun6i_spi_cfg {\n\tlong unsigned int fifo_depth;\n\tbool has_clk_ctl;\n\tu32 mode_bits;\n};\n\nstruct sunrpc_net {\n\tstruct proc_dir_entry *proc_net_rpc;\n\tstruct cache_detail *ip_map_cache;\n\tstruct cache_detail *unix_gid_cache;\n\tstruct cache_detail *rsc_cache;\n\tstruct cache_detail *rsi_cache;\n\tstruct super_block *pipefs_sb;\n\tstruct rpc_pipe *gssd_dummy;\n\tstruct mutex pipefs_sb_lock;\n\tstruct list_head all_clients;\n\tspinlock_t rpc_client_lock;\n\tstruct rpc_clnt *rpcb_local_clnt;\n\tstruct rpc_clnt *rpcb_local_clnt4;\n\tspinlock_t rpcb_clnt_lock;\n\tunsigned int rpcb_users;\n\tunsigned int rpcb_is_af_local: 1;\n\tstruct mutex gssp_lock;\n\tstruct rpc_clnt *gssp_clnt;\n\tint use_gss_proxy;\n\tint pipe_version;\n\tatomic_t pipe_users;\n\tstruct proc_dir_entry *use_gssp_proc;\n\tstruct proc_dir_entry *gss_krb5_enctypes;\n};\n\nstruct sunxi_ccu_desc;\n\nstruct sunxi_ccu {\n\tconst struct sunxi_ccu_desc *desc;\n\tspinlock_t lock;\n\tstruct ccu_reset reset;\n};\n\nstruct sunxi_ccu_desc {\n\tstruct ccu_common **ccu_clks;\n\tlong unsigned int num_ccu_clks;\n\tstruct clk_hw_onecell_data *hw_clks;\n\tconst struct ccu_reset_map *resets;\n\tlong unsigned int num_resets;\n};\n\nstruct sunxi_desc_function {\n\tlong unsigned int variant;\n\tconst char *name;\n\tu8 muxval;\n\tu8 irqbank;\n\tu8 irqnum;\n};\n\nstruct sunxi_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tlong unsigned int variant;\n\tstruct sunxi_desc_function *functions;\n};\n\nstruct sunxi_glue {\n\tstruct device *dev;\n\tstruct musb *musb;\n\tstruct platform_device *musb_pdev;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tstruct phy *phy;\n\tstruct platform_device *usb_phy;\n\tstruct usb_phy *xceiv;\n\tenum phy_mode phy_mode;\n\tlong unsigned int flags;\n\tstruct work_struct work;\n\tstruct extcon_dev *extcon;\n\tstruct notifier_block host_nb;\n};\n\nstruct sunxi_idma_des {\n\t__le32 config;\n\t__le32 buf_size;\n\t__le32 buf_addr_ptr1;\n\t__le32 buf_addr_ptr2;\n};\n\nstruct sunxi_mmc_clk_delay;\n\nstruct sunxi_mmc_cfg {\n\tu32 idma_des_size_bits;\n\tu32 idma_des_shift;\n\tconst struct sunxi_mmc_clk_delay *clk_delays;\n\tbool can_calibrate;\n\tbool mask_data0;\n\tbool needs_new_timings;\n\tbool ccu_has_timings_switch;\n};\n\nstruct sunxi_mmc_clk_delay {\n\tu32 output;\n\tu32 sample;\n};\n\nstruct sunxi_mmc_host {\n\tstruct device *dev;\n\tstruct mmc_host *mmc;\n\tstruct reset_control *reset;\n\tconst struct sunxi_mmc_cfg *cfg;\n\tvoid *reg_base;\n\tstruct clk *clk_ahb;\n\tstruct clk *clk_mmc;\n\tstruct clk *clk_sample;\n\tstruct clk *clk_output;\n\tspinlock_t lock;\n\tint irq;\n\tu32 int_sum;\n\tu32 sdio_imask;\n\tdma_addr_t sg_dma;\n\tvoid *sg_cpu;\n\tbool wait_dma;\n\tstruct mmc_request *mrq;\n\tstruct mmc_request *manual_stop_mrq;\n\tint ferror;\n\tbool vqmmc_enabled;\n\tbool use_new_timings;\n};\n\nstruct sunxi_musb_cfg {\n\tconst struct musb_hdrc_config *hdrc_config;\n\tbool has_sram;\n\tbool has_reset;\n\tbool no_configdata;\n};\n\nstruct sunxi_pck600;\n\nstruct sunxi_pck600_pd {\n\tstruct generic_pm_domain genpd;\n\tstruct sunxi_pck600 *pck;\n\tvoid *base;\n};\n\nstruct sunxi_pck600 {\n\tstruct device *dev;\n\tstruct genpd_onecell_data genpd_data;\n\tstruct sunxi_pck600_pd pds[0];\n};\n\nstruct sunxi_pck600_desc {\n\tconst char * const *pd_names;\n\tunsigned int num_domains;\n\tu32 logic_power_switch0_delay_offset;\n\tu32 logic_power_switch1_delay_offset;\n\tu32 off2on_delay_offset;\n\tu32 device_ctrl0_delay;\n\tu32 device_ctrl1_delay;\n\tu32 logic_power_switch0_delay;\n\tu32 logic_power_switch1_delay;\n\tu32 off2on_delay;\n};\n\nstruct sunxi_pinctrl_regulator {\n\tstruct regulator *regulator;\n\trefcount_t refcount;\n};\n\nstruct sunxi_pinctrl_desc;\n\nstruct sunxi_pinctrl_function;\n\nstruct sunxi_pinctrl_group;\n\nstruct sunxi_pinctrl {\n\tvoid *membase;\n\tstruct gpio_chip *chip;\n\tconst struct sunxi_pinctrl_desc *desc;\n\tstruct device *dev;\n\tstruct sunxi_pinctrl_regulator regulators[11];\n\tstruct irq_domain *domain;\n\tstruct sunxi_pinctrl_function *functions;\n\tunsigned int nfunctions;\n\tstruct sunxi_pinctrl_group *groups;\n\tunsigned int ngroups;\n\tint *irq;\n\tunsigned int *irq_array;\n\traw_spinlock_t lock;\n\tstruct pinctrl_dev *pctl_dev;\n\tlong unsigned int variant;\n\tu32 bank_mem_size;\n\tu32 pull_regs_offset;\n\tu32 dlevel_field_width;\n\tu32 pow_mod_sel_offset;\n};\n\nstruct sunxi_pinctrl_desc {\n\tconst struct sunxi_desc_pin *pins;\n\tint npins;\n\tunsigned int pin_base;\n\tunsigned int irq_banks;\n\tconst unsigned int *irq_bank_map;\n\tbool irq_read_needs_mux;\n\tbool disable_strict_mode;\n\tenum sunxi_desc_bias_voltage io_bias_cfg_variant;\n};\n\nstruct sunxi_pinctrl_function {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct sunxi_pinctrl_group {\n\tconst char *name;\n\tunsigned int pin;\n};\n\nstruct sunxi_rsb {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct reset_control *rstc;\n\tstruct completion complete;\n\tstruct mutex lock;\n\tunsigned int status;\n\tu32 clk_freq;\n};\n\nstruct sunxi_rsb_addr_map {\n\tu16 hwaddr;\n\tu8 rtaddr;\n};\n\nstruct sunxi_rsb_device;\n\nstruct sunxi_rsb_ctx {\n\tstruct sunxi_rsb_device *rdev;\n\tint size;\n};\n\nstruct sunxi_rsb_device {\n\tstruct device dev;\n\tstruct sunxi_rsb *rsb;\n\tint irq;\n\tu8 rtaddr;\n\tu16 hwaddr;\n};\n\nstruct sunxi_rsb_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct sunxi_rsb_device *);\n\tvoid (*remove)(struct sunxi_rsb_device *);\n};\n\nstruct sunxi_sc_nmi_data {\n\tstruct {\n\t\tu32 ctrl;\n\t\tu32 pend;\n\t\tu32 enable;\n\t} reg_offs;\n\tu32 enable_val;\n};\n\nstruct sunxi_sid {\n\tvoid *base;\n\tu32 value_offset;\n};\n\nstruct sunxi_sid_cfg {\n\tu32 value_offset;\n\tu32 size;\n\tbool need_register_readout;\n};\n\nstruct sunxi_sram_func;\n\nstruct sunxi_sram_data {\n\tchar *name;\n\tu8 reg;\n\tu8 offset;\n\tu8 width;\n\tstruct sunxi_sram_func *func;\n};\n\nstruct sunxi_sram_desc {\n\tstruct sunxi_sram_data data;\n\tbool claimed;\n};\n\nstruct sunxi_sram_func {\n\tchar *func;\n\tu8 val;\n\tu32 reg_val;\n};\n\nstruct sunxi_sramc_variant {\n\tint num_emac_clocks;\n\tbool has_ldo_ctrl;\n\tbool has_ths_offset;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tvoid *s_security;\n\tconst struct xattr_handler * const *s_xattr;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t);\n\tssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t);\n\tstruct dquot ** (*get_dquots)(struct inode *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct supplier_bindings {\n\tstruct device_node * (*parse_prop)(struct device_node *, const char *, int);\n\tstruct device_node * (*get_con_dev)(struct device_node *);\n\tbool optional;\n\tu8 fwlink_flags;\n};\n\nstruct suspend_info {\n\tint cancelled;\n};\n\nstruct suspend_stats {\n\tunsigned int step_failures[8];\n\tunsigned int success;\n\tunsigned int fail;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tu64 last_hw_sleep;\n\tu64 total_hw_sleep;\n\tu64 max_hw_sleep;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nstruct svc_deferred_req {\n\tu32 prot;\n\tstruct svc_xprt *xprt;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tstruct __kernel_sockaddr_storage daddr;\n\tsize_t daddrlen;\n\tvoid *xprt_ctxt;\n\tstruct cache_deferred_req handle;\n\tint argslen;\n\t__be32 args[0];\n};\n\nstruct svc_info {\n\tstruct svc_serv *serv;\n\tstruct mutex *mutex;\n};\n\nstruct svc_pool {\n\tunsigned int sp_id;\n\tunsigned int sp_nrthreads;\n\tunsigned int sp_nrthrmin;\n\tunsigned int sp_nrthrmax;\n\tstruct lwq sp_xprts;\n\tstruct list_head sp_all_threads;\n\tstruct llist_head sp_idle_threads;\n\tstruct percpu_counter sp_messages_arrived;\n\tstruct percpu_counter sp_sockets_queued;\n\tstruct percpu_counter sp_threads_woken;\n\tlong unsigned int sp_flags;\n};\n\nstruct svc_pool_map {\n\tint count;\n\tint mode;\n\tunsigned int npools;\n\tunsigned int *pool_to;\n\tunsigned int *to_pool;\n};\n\nstruct svc_procedure {\n\t__be32 (*pc_func)(struct svc_rqst *);\n\tbool (*pc_decode)(struct svc_rqst *, struct xdr_stream *);\n\tbool (*pc_encode)(struct svc_rqst *, struct xdr_stream *);\n\tvoid (*pc_release)(struct svc_rqst *);\n\tunsigned int pc_argsize;\n\tunsigned int pc_argzero;\n\tunsigned int pc_ressize;\n\tunsigned int pc_cachetype;\n\tunsigned int pc_xdrressize;\n\tconst char *pc_name;\n};\n\nstruct svc_process_info {\n\tunion {\n\t\tint (*dispatch)(struct svc_rqst *);\n\t\tstruct {\n\t\t\tunsigned int lovers;\n\t\t\tunsigned int hivers;\n\t\t} mismatch;\n\t};\n};\n\nstruct svc_version;\n\nstruct svc_program {\n\tu32 pg_prog;\n\tunsigned int pg_lovers;\n\tunsigned int pg_hivers;\n\tunsigned int pg_nvers;\n\tconst struct svc_version **pg_vers;\n\tchar *pg_name;\n\tchar *pg_class;\n\tenum svc_auth_status (*pg_authenticate)(struct svc_rqst *);\n\t__be32 (*pg_init_request)(struct svc_rqst *, const struct svc_program *, struct svc_process_info *);\n\tint (*pg_rpcbind_set)(struct net *, const struct svc_program *, u32, int, short unsigned int, short unsigned int);\n};\n\nstruct xdr_stream {\n\t__be32 *p;\n\tstruct xdr_buf *buf;\n\t__be32 *end;\n\tstruct kvec *iov;\n\tstruct kvec scratch;\n\tstruct page **page_ptr;\n\tvoid *page_kaddr;\n\tunsigned int nwords;\n\tstruct rpc_rqst *rqst;\n};\n\nstruct svc_rqst {\n\tstruct list_head rq_all;\n\tstruct llist_node rq_idle;\n\tstruct callback_head rq_rcu_head;\n\tstruct svc_xprt *rq_xprt;\n\tstruct __kernel_sockaddr_storage rq_addr;\n\tsize_t rq_addrlen;\n\tstruct __kernel_sockaddr_storage rq_daddr;\n\tsize_t rq_daddrlen;\n\tstruct svc_serv *rq_server;\n\tstruct svc_pool *rq_pool;\n\tconst struct svc_procedure *rq_procinfo;\n\tstruct auth_ops *rq_authop;\n\tstruct svc_cred rq_cred;\n\tvoid *rq_xprt_ctxt;\n\tstruct svc_deferred_req *rq_deferred;\n\tstruct xdr_buf rq_arg;\n\tstruct xdr_stream rq_arg_stream;\n\tstruct xdr_stream rq_res_stream;\n\tstruct folio *rq_scratch_folio;\n\tstruct xdr_buf rq_res;\n\tlong unsigned int rq_maxpages;\n\tstruct page **rq_pages;\n\tstruct page **rq_respages;\n\tstruct page **rq_next_page;\n\tstruct page **rq_page_end;\n\tstruct folio_batch rq_fbatch;\n\tstruct bio_vec *rq_bvec;\n\t__be32 rq_xid;\n\tu32 rq_prog;\n\tu32 rq_vers;\n\tu32 rq_proc;\n\tu32 rq_prot;\n\tint rq_cachetype;\n\tlong unsigned int rq_flags;\n\tktime_t rq_qtime;\n\tvoid *rq_argp;\n\tvoid *rq_resp;\n\t__be32 *rq_accept_statp;\n\tvoid *rq_auth_data;\n\t__be32 rq_auth_stat;\n\tint rq_auth_slack;\n\tint rq_reserved;\n\tktime_t rq_stime;\n\tstruct cache_req rq_chandle;\n\tstruct auth_domain *rq_client;\n\tstruct auth_domain *rq_gssclient;\n\tstruct task_struct *rq_task;\n\tstruct net *rq_bc_net;\n\tint rq_err;\n\tlong unsigned int bc_to_initval;\n\tunsigned int bc_to_retries;\n\tunsigned int rq_status_counter;\n\tvoid **rq_lease_breaker;\n};\n\nstruct svc_stat;\n\nstruct svc_serv {\n\tstruct svc_program *sv_programs;\n\tstruct svc_stat *sv_stats;\n\tspinlock_t sv_lock;\n\tunsigned int sv_nprogs;\n\tunsigned int sv_nrthreads;\n\tunsigned int sv_max_payload;\n\tunsigned int sv_max_mesg;\n\tunsigned int sv_xdrsize;\n\tstruct list_head sv_permsocks;\n\tstruct list_head sv_tempsocks;\n\tint sv_tmpcnt;\n\tstruct timer_list sv_temptimer;\n\tchar *sv_name;\n\tunsigned int sv_nrpools;\n\tbool sv_is_pooled;\n\tstruct svc_pool *sv_pools;\n\tint (*sv_threadfn)(void *);\n\tstruct lwq sv_cb_list;\n\tbool sv_bc_enabled;\n};\n\nstruct svc_xprt_class;\n\nstruct svc_xprt_ops;\n\nstruct svc_xprt {\n\tstruct svc_xprt_class *xpt_class;\n\tconst struct svc_xprt_ops *xpt_ops;\n\tstruct kref xpt_ref;\n\tktime_t xpt_qtime;\n\tstruct list_head xpt_list;\n\tstruct lwq_node xpt_ready;\n\tlong unsigned int xpt_flags;\n\tstruct svc_serv *xpt_server;\n\tatomic_t xpt_reserved;\n\tatomic_t xpt_nr_rqsts;\n\tstruct mutex xpt_mutex;\n\tspinlock_t xpt_lock;\n\tvoid *xpt_auth_cache;\n\tstruct list_head xpt_deferred;\n\tstruct __kernel_sockaddr_storage xpt_local;\n\tsize_t xpt_locallen;\n\tstruct __kernel_sockaddr_storage xpt_remote;\n\tsize_t xpt_remotelen;\n\tchar xpt_remotebuf[58];\n\tstruct list_head xpt_users;\n\tstruct net *xpt_net;\n\tnetns_tracker ns_tracker;\n\tconst struct cred *xpt_cred;\n\tstruct rpc_xprt *xpt_bc_xprt;\n\tstruct rpc_xprt_switch *xpt_bc_xps;\n};\n\nstruct svc_sock {\n\tstruct svc_xprt sk_xprt;\n\tstruct socket *sk_sock;\n\tstruct sock *sk_sk;\n\tvoid (*sk_ostate)(struct sock *);\n\tvoid (*sk_odata)(struct sock *);\n\tvoid (*sk_owspace)(struct sock *);\n\tstruct bio_vec *sk_bvec;\n\t__be32 sk_marker;\n\tu32 sk_tcplen;\n\tu32 sk_datalen;\n\tstruct page_frag_cache sk_frag_cache;\n\tstruct completion sk_handshake_done;\n\tlong unsigned int sk_maxpages;\n\tstruct page *sk_pages[0];\n};\n\nstruct svc_stat {\n\tstruct svc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcbadfmt;\n\tunsigned int rpcbadauth;\n\tunsigned int rpcbadclnt;\n};\n\nstruct svc_version {\n\tu32 vs_vers;\n\tu32 vs_nproc;\n\tconst struct svc_procedure *vs_proc;\n\tlong unsigned int *vs_count;\n\tu32 vs_xdrsize;\n\tbool vs_hidden;\n\tbool vs_rpcb_optnl;\n\tbool vs_need_cong_ctrl;\n\tint (*vs_dispatch)(struct svc_rqst *);\n};\n\nstruct svc_xprt_class {\n\tconst char *xcl_name;\n\tstruct module *xcl_owner;\n\tconst struct svc_xprt_ops *xcl_ops;\n\tstruct list_head xcl_list;\n\tu32 xcl_max_payload;\n\tint xcl_ident;\n};\n\nstruct svc_xprt_ops {\n\tstruct svc_xprt * (*xpo_create)(struct svc_serv *, struct net *, struct sockaddr *, int, int);\n\tstruct svc_xprt * (*xpo_accept)(struct svc_xprt *);\n\tint (*xpo_has_wspace)(struct svc_xprt *);\n\tint (*xpo_recvfrom)(struct svc_rqst *);\n\tint (*xpo_sendto)(struct svc_rqst *);\n\tint (*xpo_result_payload)(struct svc_rqst *, unsigned int, unsigned int);\n\tvoid (*xpo_release_ctxt)(struct svc_xprt *, void *);\n\tvoid (*xpo_detach)(struct svc_xprt *);\n\tvoid (*xpo_free)(struct svc_xprt *);\n\tvoid (*xpo_kill_temp_xprt)(struct svc_xprt *);\n\tvoid (*xpo_handshake)(struct svc_xprt *);\n};\n\nstruct svc_xpt_user {\n\tstruct list_head list;\n\tvoid (*callback)(struct svc_xpt_user *);\n};\n\nstruct sve_context {\n\tstruct _aarch64_ctx head;\n\t__u16 vl;\n\t__u16 flags;\n\t__u16 __reserved[2];\n};\n\nstruct sve_state_reg_region {\n\tunsigned int koffset;\n\tunsigned int klen;\n\tunsigned int upad;\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cgroup {\n\tatomic_t ids;\n};\n\nstruct swap_cgroup_ctrl {\n\tstruct swap_cgroup *map;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[10];\n\tstruct list_head frag_clusters[10];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_map_page;\n\nstruct swap_map_page_list;\n\nstruct swap_map_handle {\n\tstruct swap_map_page *cur;\n\tstruct swap_map_page_list *maps;\n\tsector_t cur_swap;\n\tsector_t first_sector;\n\tunsigned int k;\n\tlong unsigned int reqd_free_pages;\n\tu32 crc32;\n};\n\nstruct swap_map_page {\n\tsector_t entries[511];\n\tsector_t next_swap;\n};\n\nstruct swap_map_page_list {\n\tstruct swap_map_page *map;\n\tstruct swap_map_page_list *next;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[10];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[512];\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n};\n\nstruct switchdev_mst_state {\n\tu16 msti;\n\tu8 state;\n};\n\nstruct switchdev_brport_flags {\n\tlong unsigned int val;\n\tlong unsigned int mask;\n};\n\nstruct switchdev_vlan_msti {\n\tu16 vid;\n\tu16 msti;\n};\n\nstruct switchdev_attr {\n\tstruct net_device *orig_dev;\n\tenum switchdev_attr_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n\tunion {\n\t\tu8 stp_state;\n\t\tstruct switchdev_mst_state mst_state;\n\t\tstruct switchdev_brport_flags brport_flags;\n\t\tbool mrouter;\n\t\tclock_t ageing_time;\n\t\tbool vlan_filtering;\n\t\tu16 vlan_protocol;\n\t\tbool mst;\n\t\tbool mc_disabled;\n\t\tu8 mrp_port_role;\n\t\tstruct switchdev_vlan_msti vlan_msti;\n\t} u;\n};\n\nstruct switchdev_brport {\n\tstruct net_device *dev;\n\tconst void *ctx;\n\tstruct notifier_block *atomic_nb;\n\tstruct notifier_block *blocking_nb;\n\tbool tx_fwd_offload;\n};\n\ntypedef void switchdev_deferred_func_t(struct net_device *, const void *);\n\nstruct switchdev_deferred_item {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tswitchdev_deferred_func_t *func;\n\tlong unsigned int data[0];\n};\n\nstruct switchdev_nested_priv {\n\tbool (*check_cb)(const struct net_device *);\n\tbool (*foreign_dev_check_cb)(const struct net_device *, const struct net_device *);\n\tconst struct net_device *dev;\n\tstruct net_device *lower_dev;\n};\n\nstruct switchdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n\tconst void *ctx;\n};\n\nstruct switchdev_notifier_brport_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_brport brport;\n};\n\nstruct switchdev_notifier_fdb_info {\n\tstruct switchdev_notifier_info info;\n\tconst unsigned char *addr;\n\tu16 vid;\n\tu8 added_by_user: 1;\n\tu8 is_local: 1;\n\tu8 locked: 1;\n\tu8 offloaded: 1;\n};\n\nstruct switchdev_notifier_port_attr_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_attr *attr;\n\tbool handled;\n};\n\nstruct switchdev_obj;\n\nstruct switchdev_notifier_port_obj_info {\n\tstruct switchdev_notifier_info info;\n\tconst struct switchdev_obj *obj;\n\tbool handled;\n};\n\nstruct switchdev_obj {\n\tstruct list_head list;\n\tstruct net_device *orig_dev;\n\tenum switchdev_obj_id id;\n\tu32 flags;\n\tvoid *complete_priv;\n\tvoid (*complete)(struct net_device *, int, void *);\n};\n\nstruct switchdev_obj_mrp {\n\tstruct switchdev_obj obj;\n\tstruct net_device *p_port;\n\tstruct net_device *s_port;\n\tu32 ring_id;\n\tu16 prio;\n};\n\nstruct switchdev_obj_port_mdb {\n\tstruct switchdev_obj obj;\n\tunsigned char addr[6];\n\tu16 vid;\n};\n\nstruct switchdev_obj_port_vlan {\n\tstruct switchdev_obj obj;\n\tu16 flags;\n\tu16 vid;\n\tbool changed;\n};\n\nstruct switchdev_obj_ring_role_mrp {\n\tstruct switchdev_obj obj;\n\tu8 ring_role;\n\tu32 ring_id;\n\tu8 sw_backup;\n};\n\nstruct swmii_regs {\n\tu16 bmsr;\n\tu16 lpa;\n\tu16 lpagb;\n\tu16 estat;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct swoc_info {\n\t__u8 rev;\n\t__u8 reserved[8];\n\t__u16 LinuxSKU;\n\t__u16 LinuxVer;\n\t__u8 reserved2[47];\n} __attribute__((packed));\n\nstruct swsusp_extent {\n\tstruct rb_node node;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct swsusp_header {\n\tchar reserved[4056];\n\tu32 hw_sig;\n\tu32 crc32;\n\tsector_t image;\n\tunsigned int flags;\n\tchar orig_sig[10];\n\tchar sig[10];\n};\n\nstruct swsusp_info {\n\tstruct new_utsname uts;\n\tu32 version_code;\n\tlong unsigned int num_physpages;\n\tint cpus;\n\tlong unsigned int image_pages;\n\tlong unsigned int pages;\n\tlong unsigned int size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tbool pt_port_open;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct sync_fence_info {\n\tchar obj_name[32];\n\tchar driver_name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u64 timestamp_ns;\n};\n\nstruct sync_file {\n\tstruct file *file;\n\tchar user_name[32];\n\tstruct list_head sync_file_list;\n\twait_queue_head_t wq;\n\tlong unsigned int flags;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct sync_file_info {\n\tchar name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u32 num_fences;\n\t__u32 pad;\n\t__u64 sync_fence_info;\n};\n\nstruct sync_merge_data {\n\tchar name[32];\n\t__s32 fd2;\n\t__s32 fence;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct sync_set_deadline {\n\t__u64 deadline_ns;\n\t__u64 pad;\n};\n\nstruct sys64_hook {\n\tlong unsigned int esr_mask;\n\tlong unsigned int esr_val;\n\tvoid (*handler)(long unsigned int, struct pt_regs *);\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct sys_reg_params;\n\nstruct sys_reg_desc {\n\tconst char *name;\n\tenum {\n\t\tAA32_DIRECT = 0,\n\t\tAA32_LO = 1,\n\t\tAA32_HI = 2,\n\t} aarch32_map;\n\tu8 Op0;\n\tu8 Op1;\n\tu8 CRn;\n\tu8 CRm;\n\tu8 Op2;\n\tbool (*access)(struct kvm_vcpu *, struct sys_reg_params *, const struct sys_reg_desc *);\n\tu64 (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);\n\tint reg;\n\tu64 val;\n\tint (*__get_user)(struct kvm_vcpu *, const struct sys_reg_desc *, u64 *);\n\tint (*set_user)(struct kvm_vcpu *, const struct sys_reg_desc *, u64);\n\tunsigned int (*visibility)(const struct kvm_vcpu *, const struct sys_reg_desc *);\n};\n\nstruct sys_reg_params {\n\tu8 Op0;\n\tu8 Op1;\n\tu8 CRn;\n\tu8 CRm;\n\tu8 Op2;\n\tu64 regval;\n\tbool is_write;\n};\n\nstruct sysc_config {\n\tu32 sysc_val;\n\tu32 syss_mask;\n\tu8 midlemodes;\n\tu8 sidlemodes;\n\tu8 srst_udelay;\n\tu32 quirks;\n};\n\nstruct ti_sysc_cookie {\n\tvoid *data;\n\tvoid *clkdm;\n};\n\nstruct ti_sysc_module_data;\n\nstruct sysc_capabilities;\n\nstruct sysc {\n\tstruct device *dev;\n\tu64 module_pa;\n\tu32 module_size;\n\tvoid *module_va;\n\tint offsets[3];\n\tstruct ti_sysc_module_data *mdata;\n\tstruct clk **clocks;\n\tconst char **clock_roles;\n\tint nr_clocks;\n\tstruct reset_control *rsts;\n\tconst char *legacy_mode;\n\tconst struct sysc_capabilities *cap;\n\tstruct sysc_config cfg;\n\tstruct ti_sysc_cookie cookie;\n\tconst char *name;\n\tu32 revision;\n\tu32 sysconfig;\n\tunsigned int reserved: 1;\n\tunsigned int enabled: 1;\n\tunsigned int needs_resume: 1;\n\tunsigned int child_needs_resume: 1;\n\tstruct delayed_work idle_work;\n\tvoid (*pre_reset_quirk)(struct sysc *);\n\tvoid (*post_reset_quirk)(struct sysc *);\n\tvoid (*reset_done_quirk)(struct sysc *);\n\tvoid (*module_enable_quirk)(struct sysc *);\n\tvoid (*module_disable_quirk)(struct sysc *);\n\tvoid (*module_unlock_quirk)(struct sysc *);\n\tvoid (*module_lock_quirk)(struct sysc *);\n};\n\nstruct sysc_address {\n\tlong unsigned int base;\n\tstruct list_head node;\n};\n\nstruct sysc_regbits;\n\nstruct sysc_capabilities {\n\tconst enum ti_sysc_module_type type;\n\tconst u32 sysc_mask;\n\tconst struct sysc_regbits *regbits;\n\tconst u32 mod_quirks;\n};\n\nstruct sysc_dts_quirk {\n\tconst char *name;\n\tu32 mask;\n};\n\nstruct sysc_module {\n\tstruct sysc *ddata;\n\tstruct list_head node;\n};\n\nstruct sysc_regbits {\n\ts8 midle_shift;\n\ts8 clkact_shift;\n\ts8 sidle_shift;\n\ts8 enwkup_shift;\n\ts8 srst_shift;\n\ts8 autoidle_shift;\n\ts8 dmadisable_shift;\n\ts8 emufree_shift;\n};\n\nstruct sysc_revision_quirk {\n\tconst char *name;\n\tu32 base;\n\tint rev_offset;\n\tint sysc_offset;\n\tint syss_offset;\n\tu32 revision;\n\tu32 revision_mask;\n\tu32 quirks;\n};\n\nstruct sysc_soc_info {\n\tlong unsigned int general_purpose: 1;\n\tenum sysc_soc soc;\n\tstruct mutex list_lock;\n\tstruct list_head disabled_modules;\n\tstruct list_head restored_modules;\n\tstruct notifier_block nb;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_user_dispatch {};\n\nstruct syscon {\n\tstruct device_node *np;\n\tstruct regmap *regmap;\n\tstruct reset_control *reset;\n\tstruct list_head list;\n};\n\nstruct syscon_gpio_data {\n\tunsigned int flags;\n\tunsigned int bit_count;\n\tunsigned int dat_bit_offset;\n\tunsigned int dir_bit_offset;\n\tint (*set)(struct gpio_chip *, unsigned int, int);\n};\n\nstruct syscon_gpio_priv {\n\tstruct gpio_chip chip;\n\tstruct regmap *syscon;\n\tconst struct syscon_gpio_data *data;\n\tu32 dreg_offset;\n\tu32 dir_reg_offset;\n};\n\nstruct syscon_led {\n\tstruct led_classdev cdev;\n\tstruct regmap *map;\n\tu32 offset;\n\tu32 mask;\n\tbool state;\n};\n\nstruct syscon_poweroff_data {\n\tstruct regmap *map;\n\tu32 offset;\n\tu32 value;\n\tu32 mask;\n};\n\nstruct syscon_reboot_context {\n\tstruct regmap *map;\n\tconst struct reboot_data *rd;\n\tstruct reboot_mode_bits catchall;\n\tstruct notifier_block restart_handler;\n};\n\nstruct syscon_reboot_mode {\n\tstruct regmap *map;\n\tstruct reboot_mode_driver reboot;\n\tu32 offset;\n\tu32 mask;\n};\n\nstruct syscore_ops;\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysctr_private {\n\tu32 cmpcr;\n\tu32 lo_off;\n\tu32 hi_off;\n};\n\nstruct sysfb_display_info {\n\tstruct screen_info screen;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysfs_wi_group {\n\tstruct kobject wi_kobj;\n\tstruct mutex kobj_lock;\n\tstruct iw_node_attr *nattrs[0];\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[0];\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[12];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tunsigned int shift;\n\tunsigned int shift_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[12];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct t10_pi_tuple {\n\t__be16 guard_tag;\n\t__be16 app_tag;\n\t__be32 ref_tag;\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\nstruct tap_filter {\n\tunsigned int count;\n\tu32 mask[2];\n\tunsigned char addr[48];\n};\n\nstruct target {\n\tstruct device_node *np;\n\tbool in_livetree;\n};\n\nstruct target_cache {\n\tstruct list_head node;\n\tstruct node_cache_attrs cache_attrs;\n};\n\nstruct target_impl_cpu {\n\tu64 midr;\n\tu64 revidr;\n\tu64 aidr;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t load_avg;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct autogroup *autogroup;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_numa_env {\n\tstruct task_struct *p;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tint imb_numa_nr;\n\tstruct numa_stats src_stats;\n\tstruct numa_stats dst_stats;\n\tint imbalance_pct;\n\tint dist;\n\tstruct task_struct *best_task;\n\tlong int best_imp;\n\tint best_cpu;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct thread_info {\n\tlong unsigned int flags;\n\tunion {\n\t\tu64 preempt_count;\n\t\tstruct {\n\t\t\tu32 count;\n\t\t\tu32 need_resched;\n\t\t} preempt;\n\t};\n\tu32 cpu;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {\n\tstruct arch_tlbflush_unmap_batch arch;\n\tbool flush_required;\n\tbool writable;\n};\n\nstruct thread_struct {\n\tstruct cpu_context cpu_context;\n\tlong: 64;\n\tstruct {\n\t\tlong unsigned int tp_value;\n\t\tlong unsigned int tp2_value;\n\t\tu64 fpmr;\n\t\tlong unsigned int pad;\n\t\tstruct user_fpsimd_state fpsimd_state;\n\t} uw;\n\tenum fp_type fp_type;\n\tunsigned int fpsimd_cpu;\n\tvoid *sve_state;\n\tvoid *sme_state;\n\tunsigned int vl[2];\n\tunsigned int vl_onexec[2];\n\tlong unsigned int fault_address;\n\tlong unsigned int fault_code;\n\tstruct debug_info debug;\n\tstruct user_fpsimd_state *kernel_fpsimd_state;\n\tunsigned int kernel_fpsimd_cpu;\n\tstruct ptrauth_keys_user keys_user;\n\tstruct ptrauth_keys_kernel keys_kernel;\n\tu64 mte_ctrl;\n\tu64 sctlr_user;\n\tu64 svcr;\n\tu64 tpidr2_el0;\n\tu64 por_el0;\n\tunsigned int gcs_el0_mode;\n\tunsigned int gcs_el0_locked;\n\tu64 gcspr_el0;\n\tu64 gcs_base;\n\tu64 gcs_size;\n};\n\nstruct uprobe_task;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct task_group *sched_task_group;\n\tstruct callback_head sched_throttle_work;\n\tstruct list_head throttle_node;\n\tbool throttled;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_statistics stats;\n\tstruct hlist_head preempt_notifiers;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tint rcu_read_lock_nesting;\n\tunion rcu_special rcu_read_unlock_special;\n\tstruct list_head rcu_node_entry;\n\tstruct rcu_node *rcu_blocked_node;\n\tlong unsigned int rcu_tasks_nvcsw;\n\tu8 rcu_tasks_holdout;\n\tu8 rcu_tasks_idx;\n\tint rcu_tasks_idle_cpu;\n\tstruct list_head rcu_tasks_holdout_list;\n\tint rcu_tasks_exit_cpu;\n\tstruct list_head rcu_tasks_exit_list;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int use_memdelay: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct posix_cputimers_work posix_cputimers_work;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct audit_context *audit_context;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tu64 acct_rss_mem1;\n\tu64 acct_vm_mem1;\n\tu64 acct_timexpd;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct compat_robust_list_head *compat_robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tu8 perf_recursion[4];\n\tstruct perf_event_context *perf_event_ctxp;\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct perf_ctx_data *perf_ctx_data;\n\tstruct mempolicy *mempolicy;\n\tshort int il_prev;\n\tu8 il_weight;\n\tshort int pref_node_fork;\n\tint numa_scan_seq;\n\tunsigned int numa_scan_period;\n\tunsigned int numa_scan_period_max;\n\tint numa_preferred_nid;\n\tlong unsigned int numa_migrate_retry;\n\tu64 node_stamp;\n\tu64 last_task_numa_placement;\n\tu64 last_sum_exec_runtime;\n\tstruct callback_head numa_work;\n\tstruct numa_group *numa_group;\n\tlong unsigned int *numa_faults;\n\tlong unsigned int total_numa_faults;\n\tlong unsigned int numa_faults_locality[3];\n\tlong unsigned int numa_pages_migrated;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tstruct lazy_mmu_state lazy_mmu_state;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tlong unsigned int trace_recursion;\n\tunsigned int memcg_nr_pages_over_high;\n\tstruct mem_cgroup *active_memcg;\n\tstruct obj_cgroup *objcg;\n\tstruct gendisk *throttle_disk;\n\tstruct uprobe_task *utask;\n\tstruct kmap_ctrl kmap_ctrl;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\tstruct vm_struct *stack_vm_area;\n\trefcount_t stack_refcount;\n\tvoid *security;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tstruct thread_struct thread;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct taskstats {\n\t__u16 version;\n\t__u32 ac_exitcode;\n\t__u8 ac_flag;\n\t__u8 ac_nice;\n\t__u64 cpu_count;\n\t__u64 cpu_delay_total;\n\t__u64 blkio_count;\n\t__u64 blkio_delay_total;\n\t__u64 swapin_count;\n\t__u64 swapin_delay_total;\n\t__u64 cpu_run_real_total;\n\t__u64 cpu_run_virtual_total;\n\tchar ac_comm[32];\n\t__u8 ac_sched;\n\t__u8 ac_pad[3];\n\tlong: 0;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u64 ac_etime;\n\t__u64 ac_utime;\n\t__u64 ac_stime;\n\t__u64 ac_minflt;\n\t__u64 ac_majflt;\n\t__u64 coremem;\n\t__u64 virtmem;\n\t__u64 hiwater_rss;\n\t__u64 hiwater_vm;\n\t__u64 read_char;\n\t__u64 write_char;\n\t__u64 read_syscalls;\n\t__u64 write_syscalls;\n\t__u64 read_bytes;\n\t__u64 write_bytes;\n\t__u64 cancelled_write_bytes;\n\t__u64 nvcsw;\n\t__u64 nivcsw;\n\t__u64 ac_utimescaled;\n\t__u64 ac_stimescaled;\n\t__u64 cpu_scaled_run_real_total;\n\t__u64 freepages_count;\n\t__u64 freepages_delay_total;\n\t__u64 thrashing_count;\n\t__u64 thrashing_delay_total;\n\t__u64 ac_btime64;\n\t__u64 compact_count;\n\t__u64 compact_delay_total;\n\t__u32 ac_tgid;\n\t__u64 ac_tgetime;\n\t__u64 ac_exe_dev;\n\t__u64 ac_exe_inode;\n\t__u64 wpcopy_count;\n\t__u64 wpcopy_delay_total;\n\t__u64 irq_count;\n\t__u64 irq_delay_total;\n\t__u64 cpu_delay_max;\n\t__u64 cpu_delay_min;\n\t__u64 blkio_delay_max;\n\t__u64 blkio_delay_min;\n\t__u64 swapin_delay_max;\n\t__u64 swapin_delay_min;\n\t__u64 freepages_delay_max;\n\t__u64 freepages_delay_min;\n\t__u64 thrashing_delay_max;\n\t__u64 thrashing_delay_min;\n\t__u64 compact_delay_max;\n\t__u64 compact_delay_min;\n\t__u64 wpcopy_delay_max;\n\t__u64 wpcopy_delay_min;\n\t__u64 irq_delay_max;\n\t__u64 irq_delay_min;\n\tstruct __kernel_timespec cpu_delay_max_ts;\n\tstruct __kernel_timespec blkio_delay_max_ts;\n\tstruct __kernel_timespec swapin_delay_max_ts;\n\tstruct __kernel_timespec freepages_delay_max_ts;\n\tstruct __kernel_timespec thrashing_delay_max_ts;\n\tstruct __kernel_timespec compact_delay_max_ts;\n\tstruct __kernel_timespec wpcopy_delay_max_ts;\n\tstruct __kernel_timespec irq_delay_max_ts;\n};\n\nstruct tbg_def {\n\tchar *name;\n\tu32 refdiv_offset;\n\tu32 fbdiv_offset;\n\tu32 vcodiv_reg;\n\tu32 vcodiv_offset;\n};\n\nstruct tc_act_pernet_id {\n\tstruct list_head list;\n\tunsigned int id;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tstruct tcf_t tcfa_tm;\n\tlong: 64;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n};\n\nstruct tc_action_net {\n\tstruct tcf_idrinfo *idrinfo;\n\tconst struct tc_action_ops *ops;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_bind_class_args {\n\tstruct qdisc_walker w;\n\tlong unsigned int new_cl;\n\tu32 portid;\n\tu32 clid;\n};\n\nstruct tc_cbs_qopt_offload {\n\tu8 enable;\n\ts32 queue;\n\ts32 hicredit;\n\ts32 locredit;\n\ts32 idleslope;\n\ts32 sendslope;\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_etf_qopt_offload {\n\tu8 enable;\n\ts32 queue;\n};\n\nstruct tc_fifo_qopt {\n\t__u32 limit;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_fifo_qopt_offload {\n\tenum tc_fifo_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t};\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_mqprio_caps {\n\tbool validate_queue_counts: 1;\n};\n\nstruct tc_pedit_key {\n\t__u32 mask;\n\t__u32 val;\n\t__u32 off;\n\t__u32 at;\n\t__u32 offmask;\n\t__u32 shift;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_root_qopt_offload {\n\tenum tc_root_command command;\n\tu32 handle;\n\tbool ingress;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tc_taprio_caps {\n\tbool supports_queue_max_sdu: 1;\n\tbool gate_mask_per_txq: 1;\n\tbool broken_mqprio: 1;\n};\n\nstruct tc_tbf_qopt_offload_replace_params {\n\tstruct psched_ratecfg rate;\n\tu32 max_size;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_tbf_qopt_offload {\n\tenum tc_tbf_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_tbf_qopt_offload_replace_params replace_params;\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tu32 child_handle;\n\t};\n};\n\nstruct tcamsg {\n\tunsigned char tca_family;\n\tunsigned char tca__pad1;\n\tshort unsigned int tca__pad2;\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcf_bind_args {\n\tstruct tcf_walker w;\n\tlong unsigned int base;\n\tlong unsigned int cl;\n\tu32 classid;\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\ntypedef void tcf_chain_head_change_t(struct tcf_proto *, void *);\n\nstruct tcf_block_ext_info {\n\tenum flow_block_binder_type binder_type;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n\tu32 block_index;\n};\n\nstruct tcf_block_owner_item {\n\tstruct list_head list;\n\tstruct Qdisc *q;\n\tenum flow_block_binder_type binder_type;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_chain_info {\n\tstruct tcf_proto **pprev;\n\tstruct tcf_proto *next;\n};\n\nstruct tcf_dump_args {\n\tstruct tcf_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct tcf_block *block;\n\tstruct Qdisc *q;\n\tu32 parent;\n\tbool terse_dump;\n};\n\nstruct tcf_exts_miss_cookie_node;\n\nstruct tcf_exts {\n\t__u32 type;\n\tint nr_actions;\n\tstruct tc_action **actions;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct tcf_exts_miss_cookie_node *miss_cookie_node;\n\tint action;\n\tint police;\n};\n\nunion tcf_exts_miss_cookie {\n\tstruct {\n\t\tu32 miss_cookie_base;\n\t\tu32 act_index;\n\t};\n\tu64 miss_cookie;\n};\n\nstruct tcf_exts_miss_cookie_node {\n\tconst struct tcf_chain *chain;\n\tconst struct tcf_proto *tp;\n\tconst struct tcf_exts *exts;\n\tu32 chain_index;\n\tu32 tp_prio;\n\tu32 handle;\n\tu32 miss_cookie_base;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_filter_chain_list_item {\n\tstruct list_head list;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_net {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n};\n\nstruct tcf_pedit_parms;\n\nstruct tcf_pedit {\n\tstruct tc_action common;\n\tstruct tcf_pedit_parms *parms;\n\tlong: 64;\n};\n\nstruct tcf_pedit_key_ex {\n\tenum pedit_header_type htype;\n\tenum pedit_cmd cmd;\n};\n\nstruct tcf_pedit_parms {\n\tstruct tc_pedit_key *tcfp_keys;\n\tstruct tcf_pedit_key_ex *tcfp_keys_ex;\n\tint action;\n\tu32 tcfp_off_max_hint;\n\tunsigned char tcfp_nkeys;\n\tunsigned char tcfp_flags;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_qevent {\n\tstruct tcf_block *block;\n\tstruct tcf_block_ext_info info;\n\tstruct tcf_proto *filter_chain;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\tlong: 64;\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t};\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 ae: 1;\n\t__u16 res1: 3;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpa_event {\n\tu32 pcr_index;\n\tu32 event_type;\n\tu8 pcr_value[20];\n\tu32 event_size;\n\tu8 event_data[0];\n};\n\nstruct tcpa_pc_event {\n\tu32 event_id;\n\tu32 event_size;\n\tu8 event_data[0];\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcs_type_config {\n\tu32 type;\n\tu32 n;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n};\n\nstruct td {\n\t__hc32 hwINFO;\n\t__hc32 hwCBP;\n\t__hc32 hwNextTD;\n\t__hc32 hwBE;\n\t__hc16 hwPSW[2];\n\t__u8 index;\n\tstruct ed *ed;\n\tstruct td *td_hash;\n\tstruct td *next_dl_td;\n\tstruct urb *urb;\n\tdma_addr_t td_dma;\n\tdma_addr_t data_dma;\n\tstruct list_head td_list;\n\tlong: 64;\n};\n\nstruct td_node {\n\tstruct list_head td;\n\tdma_addr_t dma;\n\tstruct ci_hw_td *ptr;\n\tint td_remaining_size;\n};\n\nstruct tee_bnxt_fw_private {\n\tstruct device *dev;\n\tstruct tee_context *ctx;\n\tu32 session_id;\n\tstruct tee_shm *fw_shm_pool;\n};\n\nstruct tee_client_device_id {\n\tuuid_t uuid;\n};\n\nstruct tee_client_device {\n\tstruct tee_client_device_id id;\n\tstruct device dev;\n};\n\nstruct tee_client_driver {\n\tint (*probe)(struct tee_client_device *);\n\tvoid (*remove)(struct tee_client_device *);\n\tvoid (*shutdown)(struct tee_client_device *);\n\tconst struct tee_client_device_id *id_table;\n\tstruct device_driver driver;\n};\n\nstruct tee_context {\n\tstruct tee_device *teedev;\n\tvoid *data;\n\tstruct kref refcount;\n\tbool releasing;\n\tbool supp_nowait;\n\tbool cap_memref_null;\n};\n\nstruct tee_driver_ops;\n\nstruct tee_desc {\n\tconst char *name;\n\tconst struct tee_driver_ops *ops;\n\tstruct module *owner;\n\tu32 flags;\n};\n\nstruct tee_device {\n\tchar name[32];\n\tconst struct tee_desc *desc;\n\tint id;\n\tunsigned int flags;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tsize_t num_users;\n\tstruct completion c_no_users;\n\tstruct mutex mutex;\n\tstruct idr idr;\n\tstruct tee_shm_pool *pool;\n};\n\nstruct tee_ioctl_open_session_arg;\n\nstruct tee_ioctl_invoke_arg;\n\nstruct tee_ioctl_object_invoke_arg;\n\nstruct tee_driver_ops {\n\tvoid (*get_version)(struct tee_device *, struct tee_ioctl_version_data *);\n\tint (*get_tee_revision)(struct tee_device *, char *, size_t);\n\tint (*open)(struct tee_context *);\n\tvoid (*close_context)(struct tee_context *);\n\tvoid (*release)(struct tee_context *);\n\tint (*open_session)(struct tee_context *, struct tee_ioctl_open_session_arg *, struct tee_param *);\n\tint (*close_session)(struct tee_context *, u32);\n\tint (*system_session)(struct tee_context *, u32);\n\tint (*invoke_func)(struct tee_context *, struct tee_ioctl_invoke_arg *, struct tee_param *);\n\tint (*object_invoke_func)(struct tee_context *, struct tee_ioctl_object_invoke_arg *, struct tee_param *);\n\tint (*cancel_req)(struct tee_context *, u32, u32);\n\tint (*supp_recv)(struct tee_context *, u32 *, u32 *, struct tee_param *);\n\tint (*supp_send)(struct tee_context *, u32, u32, struct tee_param *);\n\tint (*shm_register)(struct tee_context *, struct tee_shm *, struct page **, size_t, long unsigned int);\n\tint (*shm_unregister)(struct tee_context *, struct tee_shm *);\n};\n\nstruct tee_ioctl_param {\n\t__u64 attr;\n\t__u64 a;\n\t__u64 b;\n\t__u64 c;\n};\n\nstruct tee_iocl_supp_recv_arg {\n\t__u32 func;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_iocl_supp_send_arg {\n\t__u32 ret;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_buf_data {\n\t__u64 buf_ptr;\n\t__u64 buf_len;\n};\n\nstruct tee_ioctl_cancel_arg {\n\t__u32 cancel_id;\n\t__u32 session;\n};\n\nstruct tee_ioctl_close_session_arg {\n\t__u32 session;\n};\n\nstruct tee_ioctl_invoke_arg {\n\t__u32 func;\n\t__u32 session;\n\t__u32 cancel_id;\n\t__u32 ret;\n\t__u32 ret_origin;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_object_invoke_arg {\n\t__u64 id;\n\t__u32 op;\n\t__u32 ret;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_open_session_arg {\n\t__u8 uuid[16];\n\t__u8 clnt_uuid[16];\n\t__u32 clnt_login;\n\t__u32 cancel_id;\n\t__u32 session;\n\t__u32 ret;\n\t__u32 ret_origin;\n\t__u32 num_params;\n\tstruct tee_ioctl_param params[0];\n};\n\nstruct tee_ioctl_shm_alloc_data {\n\t__u64 size;\n\t__u32 flags;\n\t__s32 id;\n};\n\nstruct tee_ioctl_shm_register_data {\n\t__u64 addr;\n\t__u64 length;\n\t__u32 flags;\n\t__s32 id;\n};\n\nstruct tee_ioctl_shm_register_fd_data {\n\t__s64 fd;\n\t__u64 size;\n\t__u32 flags;\n\t__s32 id;\n};\n\nstruct tee_ioctl_version_data {\n\t__u32 impl_id;\n\t__u32 impl_caps;\n\t__u32 gen_caps;\n};\n\nstruct tee_param_memref {\n\tsize_t shm_offs;\n\tsize_t size;\n\tstruct tee_shm *shm;\n};\n\nstruct tee_param_objref {\n\tu64 id;\n\tu64 flags;\n};\n\nstruct tee_param_ubuf {\n\tvoid *uaddr;\n\tsize_t size;\n};\n\nstruct tee_param_value {\n\tu64 a;\n\tu64 b;\n\tu64 c;\n};\n\nstruct tee_param {\n\tu64 attr;\n\tunion {\n\t\tstruct tee_param_memref memref;\n\t\tstruct tee_param_objref objref;\n\t\tstruct tee_param_ubuf ubuf;\n\t\tstruct tee_param_value value;\n\t} u;\n};\n\nstruct tee_protmem_pool_ops {\n\tint (*alloc)(struct tee_protmem_pool *, struct sg_table *, size_t, size_t *);\n\tvoid (*free)(struct tee_protmem_pool *, struct sg_table *);\n\tint (*update_shm)(struct tee_protmem_pool *, struct sg_table *, size_t, struct tee_shm *, struct tee_shm **);\n\tvoid (*destroy_pool)(struct tee_protmem_pool *);\n};\n\nstruct tee_protmem_static_pool {\n\tstruct tee_protmem_pool pool;\n\tstruct gen_pool *gen_pool;\n\tphys_addr_t pa_base;\n};\n\nstruct tee_shm {\n\tstruct tee_context *ctx;\n\tphys_addr_t paddr;\n\tvoid *kaddr;\n\tsize_t size;\n\tunsigned int offset;\n\tstruct page **pages;\n\tsize_t num_pages;\n\trefcount_t refcount;\n\tu32 flags;\n\tint id;\n\tu64 sec_world_id;\n};\n\nstruct tee_shm_dmabuf_ref {\n\tstruct tee_shm shm;\n\tsize_t offset;\n\tstruct dma_buf *dmabuf;\n\tstruct tee_shm *parent_shm;\n};\n\nstruct tee_shm_pool_ops;\n\nstruct tee_shm_pool {\n\tconst struct tee_shm_pool_ops *ops;\n\tvoid *private_data;\n};\n\nstruct tee_shm_pool_ops {\n\tint (*alloc)(struct tee_shm_pool *, struct tee_shm *, size_t, size_t);\n\tvoid (*free)(struct tee_shm_pool *, struct tee_shm *);\n\tvoid (*destroy_pool)(struct tee_shm_pool *);\n};\n\nstruct tegra124_cpufreq_priv {\n\tstruct clk *cpu_clk;\n\tstruct clk *pllp_clk;\n\tstruct clk *pllx_clk;\n\tstruct clk *dfll_clk;\n\tstruct platform_device *cpufreq_dt_pdev;\n};\n\nstruct tegra124_xusb_fuse_calibration {\n\tu32 hs_curr_level[3];\n\tu32 hs_iref_cap;\n\tu32 hs_term_range_adj;\n\tu32 hs_squelch_level;\n};\n\nstruct tegra_xusb_padctl_soc;\n\nstruct tegra_xusb_pad;\n\nstruct tegra_xusb_padctl {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct mutex lock;\n\tstruct reset_control *rst;\n\tconst struct tegra_xusb_padctl_soc *soc;\n\tstruct tegra_xusb_pad *pcie;\n\tstruct tegra_xusb_pad *sata;\n\tstruct tegra_xusb_pad *ulpi;\n\tstruct tegra_xusb_pad *usb2;\n\tstruct tegra_xusb_pad *hsic;\n\tstruct list_head ports;\n\tstruct list_head lanes;\n\tstruct list_head pads;\n\tunsigned int enable;\n\tstruct clk *clk;\n\tstruct regulator_bulk_data *supplies;\n};\n\nstruct tegra124_xusb_padctl {\n\tstruct tegra_xusb_padctl base;\n\tstruct tegra124_xusb_fuse_calibration fuse;\n};\n\nstruct tegra_bpmp;\n\nstruct tegra186_bpmp {\n\tstruct tegra_bpmp *parent;\n\tstruct {\n\t\tstruct gen_pool *pool;\n\t\tunion {\n\t\t\tvoid *sram;\n\t\t\tvoid *dram;\n\t\t};\n\t\tdma_addr_t phys;\n\t} tx;\n\tstruct {\n\t\tstruct gen_pool *pool;\n\t\tunion {\n\t\t\tvoid *sram;\n\t\t\tvoid *dram;\n\t\t};\n\t\tdma_addr_t phys;\n\t} rx;\n\tstruct {\n\t\tstruct mbox_client client;\n\t\tstruct mbox_chan *channel;\n\t} mbox;\n};\n\nstruct tegra186_cpufreq_cluster {\n\tstruct cpufreq_frequency_table *bpmp_lut;\n\tu32 ref_clk_khz;\n\tu32 div;\n};\n\nstruct tegra186_cpufreq_cpu {\n\tunsigned int bpmp_cluster_id;\n\tunsigned int edvd_offset;\n};\n\nstruct tegra186_cpufreq_data {\n\tvoid *regs;\n\tconst struct tegra186_cpufreq_cpu *cpus;\n\tbool icc_dram_bw_scaling;\n\tstruct tegra186_cpufreq_cluster clusters[0];\n};\n\nstruct tegra186_emc_dvfs;\n\nstruct tegra186_emc {\n\tstruct tegra_bpmp *bpmp;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct tegra186_emc_dvfs *dvfs;\n\tunsigned int num_dvfs;\n\tstruct {\n\t\tstruct dentry *root;\n\t\tlong unsigned int min_rate;\n\t\tlong unsigned int max_rate;\n\t} debugfs;\n\tstruct icc_provider provider;\n};\n\nstruct tegra186_emc_dvfs {\n\tlong unsigned int latency;\n\tlong unsigned int rate;\n};\n\nstruct tegra186_pin_range {\n\tunsigned int offset;\n\tconst char *group;\n};\n\nstruct tegra186_timer_soc;\n\nstruct tegra186_wdt;\n\nstruct tegra186_timer {\n\tconst struct tegra186_timer_soc *soc;\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct tegra186_wdt *wdt;\n\tstruct clocksource usec;\n\tstruct clocksource tsc;\n\tstruct clocksource osc;\n};\n\nstruct tegra186_timer_soc {\n\tunsigned int num_timers;\n\tunsigned int num_wdts;\n};\n\nstruct tegra186_tmr {\n\tstruct tegra186_timer *parent;\n\tvoid *regs;\n\tunsigned int index;\n\tunsigned int hwirq;\n};\n\nstruct tegra186_wdt {\n\tstruct watchdog_device base;\n\tvoid *regs;\n\tunsigned int index;\n\tbool locked;\n\tstruct tegra186_tmr *tmr;\n};\n\nstruct tegra_xusb_fuse_calibration {\n\tu32 *hs_curr_level;\n\tu32 hs_squelch;\n\tu32 hs_term_range_adj;\n\tu32 rpd_ctrl;\n};\n\nstruct tegra186_xusb_padctl_context {\n\tu32 vbus_id;\n\tu32 usb2_pad_mux;\n\tu32 usb2_port_cap;\n\tu32 ss_port_cap;\n};\n\nstruct tegra186_xusb_padctl {\n\tstruct tegra_xusb_padctl base;\n\tvoid *ao_regs;\n\tstruct tegra_xusb_fuse_calibration calib;\n\tstruct clk *usb2_trk_clk;\n\tlong unsigned int utmi_pad_enabled[1];\n\tstruct tegra186_xusb_padctl_context context;\n};\n\nstruct tegra194_axi2apb_bridge {\n\tstruct resource res;\n\tvoid *base;\n};\n\nstruct tegra_cbb_ops;\n\nstruct tegra_cbb {\n\tstruct device *dev;\n\tconst struct tegra_cbb_ops *ops;\n\tstruct list_head node;\n};\n\nstruct tegra194_cbb_noc_data;\n\nstruct tegra194_cbb {\n\tstruct tegra_cbb base;\n\tconst struct tegra194_cbb_noc_data *noc;\n\tstruct resource *res;\n\tvoid *regs;\n\tunsigned int num_intr;\n\tunsigned int sec_irq;\n\tunsigned int nonsec_irq;\n\tu32 errlog0;\n\tu32 errlog1;\n\tu32 errlog2;\n\tu32 errlog3;\n\tu32 errlog4;\n\tu32 errlog5;\n\tstruct tegra194_axi2apb_bridge *bridges;\n\tunsigned int num_bridges;\n};\n\nstruct tegra194_cbb_aperture {\n\tu8 initflow;\n\tu8 targflow;\n\tu8 targ_subrange;\n\tu8 init_mapping;\n\tu32 init_localaddress;\n\tu8 targ_mapping;\n\tu32 targ_localaddress;\n\tu16 seqid;\n};\n\nstruct tegra194_cbb_userbits;\n\nstruct tegra194_cbb_noc_data {\n\tconst char *name;\n\tbool erd_mask_inband_err;\n\tconst char * const *initiator_id;\n\tunsigned int max_aperture;\n\tconst struct tegra194_cbb_aperture *noc_aperture;\n\tconst char * const *routeid_initflow;\n\tconst char * const *routeid_targflow;\n\tvoid (*parse_routeid)(struct tegra194_cbb_aperture *, u64);\n\tvoid (*parse_userbits)(struct tegra194_cbb_userbits *, u32);\n};\n\nstruct tegra194_cbb_packet_header {\n\tbool lock;\n\tu8 opc;\n\tu8 errcode;\n\tu16 len1;\n\tbool format;\n};\n\nstruct tegra194_cbb_userbits {\n\tu8 axcache;\n\tu8 non_mod;\n\tu8 axprot;\n\tu8 falconsec;\n\tu8 grpsec;\n\tu8 vqc;\n\tu8 mstr_id;\n\tu8 axi_id;\n};\n\nstruct tegra_cpufreq_soc;\n\nstruct tegra_cpu_data;\n\nstruct tegra194_cpufreq_data {\n\tvoid *regs;\n\tstruct cpufreq_frequency_table **bpmp_luts;\n\tconst struct tegra_cpufreq_soc *soc;\n\tbool icc_dram_bw_scaling;\n\tstruct tegra_cpu_data *cpu_data;\n};\n\nstruct tegra194_pcie_ecam {\n\tvoid *config_base;\n\tvoid *iatu_base;\n\tvoid *dbi_base;\n};\n\nstruct tegra210_bpmp {\n\tvoid *atomics;\n\tvoid *arb_sema;\n\tstruct irq_data *tx_irq_data;\n};\n\nstruct tegra210_clk_emc_provider;\n\nstruct tegra210_clk_emc {\n\tstruct clk_hw hw;\n\tvoid *regs;\n\tstruct tegra210_clk_emc_provider *provider;\n\tstruct clk *parents[8];\n};\n\nstruct tegra210_clk_emc_config {\n\tlong unsigned int rate;\n\tbool same_freq;\n\tu32 value;\n\tlong unsigned int parent_rate;\n\tu8 parent;\n};\n\nstruct tegra210_clk_emc_provider {\n\tstruct module *owner;\n\tstruct device *dev;\n\tstruct tegra210_clk_emc_config *configs;\n\tunsigned int num_configs;\n\tint (*set_rate)(struct device *, const struct tegra210_clk_emc_config *);\n};\n\nstruct tegra210_domain_mbist_war {\n\tvoid (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *);\n\tconst u32 lvl2_offset;\n\tconst u32 lvl2_mask;\n\tconst unsigned int num_clks;\n\tconst unsigned int *clk_init_data;\n\tstruct clk_bulk_data *clks;\n};\n\nstruct tegra210_xusb_fuse_calibration {\n\tu32 hs_curr_level[4];\n\tu32 hs_term_range_adj;\n\tu32 rpd_ctrl;\n};\n\nstruct tegra210_xusb_padctl_context {\n\tu32 usb2_pad_mux;\n\tu32 usb2_port_cap;\n\tu32 ss_port_map;\n\tu32 usb3_pad_mux;\n};\n\nstruct tegra210_xusb_padctl {\n\tstruct tegra_xusb_padctl base;\n\tstruct regmap *regmap;\n\tstruct tegra210_xusb_fuse_calibration fuse;\n\tstruct tegra210_xusb_padctl_context context;\n};\n\nstruct tegra234_cbb_fabric;\n\nstruct tegra234_cbb {\n\tstruct tegra_cbb base;\n\tconst struct tegra234_cbb_fabric *fabric;\n\tstruct resource *res;\n\tvoid *regs;\n\tint num_intr;\n\tint sec_irq;\n\tvoid *mon;\n\tunsigned int type;\n\tu32 mask;\n\tu64 access;\n\tu32 mn_attr0;\n\tu32 mn_attr1;\n\tu32 mn_attr2;\n\tu32 mn_user_bits;\n};\n\nstruct tegra234_cbb_acpi_uid {\n\tconst char *hid;\n\tconst char *uid;\n\tconst struct tegra234_cbb_fabric *fabric;\n};\n\nstruct tegra_cbb_error;\n\nstruct tegra234_fabric_lookup;\n\nstruct tegra234_cbb_fabric {\n\tint fab_id;\n\tphys_addr_t off_mask_erd;\n\tphys_addr_t firewall_base;\n\tunsigned int firewall_ctl;\n\tunsigned int firewall_wr_ctl;\n\tconst char * const *initiator_id;\n\tunsigned int notifier_offset;\n\tconst struct tegra_cbb_error *errors;\n\tconst int max_errors;\n\tconst struct tegra234_fabric_lookup *fab_list;\n\tconst u32 err_intr_enbl;\n\tconst u32 err_status_clr;\n};\n\nstruct tegra234_target_lookup;\n\nstruct tegra234_fabric_lookup {\n\tconst char *name;\n\tbool is_lookup;\n\tconst struct tegra234_target_lookup *target_map;\n\tconst int max_targets;\n};\n\nstruct tegra234_target_lookup {\n\tconst char *name;\n\tunsigned int offset;\n};\n\nstruct tegra_ahb {\n\tvoid *regs;\n\tstruct device *dev;\n\tu32 ctx[0];\n};\n\nstruct tegra_audio2x_clk_initdata {\n\tchar *parent;\n\tchar *gate_name;\n\tchar *name_2x;\n\tchar *div_name;\n\tint clk_id;\n\tint clk_num;\n\tu8 div_offset;\n};\n\nstruct tegra_clk_pll_params;\n\nstruct tegra_audio_clk_info {\n\tchar *name;\n\tstruct tegra_clk_pll_params *pll_params;\n\tint clk_id;\n\tchar *parent;\n};\n\nstruct tegra_audio_clk_initdata {\n\tchar *gate_name;\n\tchar *mux_name;\n\tu32 offset;\n\tint gate_clk_id;\n\tint mux_clk_id;\n};\n\nstruct tegra_baud_tolerance {\n\tu32 lower_range_baud;\n\tu32 upper_range_baud;\n\ts32 tolerance;\n};\n\nstruct tegra_bpmp_soc;\n\nstruct tegra_bpmp_channel;\n\nstruct tegra_bpmp_clk;\n\nstruct tegra_bpmp {\n\tconst struct tegra_bpmp_soc *soc;\n\tstruct device *dev;\n\tvoid *priv;\n\tstruct {\n\t\tstruct mbox_client client;\n\t\tstruct mbox_chan *channel;\n\t} mbox;\n\tspinlock_t atomic_tx_lock;\n\tstruct tegra_bpmp_channel *tx_channel;\n\tstruct tegra_bpmp_channel *rx_channel;\n\tstruct tegra_bpmp_channel *threaded_channels;\n\tstruct {\n\t\tlong unsigned int *allocated;\n\t\tlong unsigned int *busy;\n\t\tunsigned int count;\n\t\tstruct semaphore lock;\n\t} threaded;\n\tstruct list_head mrqs;\n\tspinlock_t lock;\n\tstruct tegra_bpmp_clk **clocks;\n\tunsigned int num_clocks;\n\tstruct reset_controller_dev rstc;\n\tstruct genpd_onecell_data genpd;\n\tstruct dentry *debugfs_mirror;\n\tbool suspended;\n};\n\nstruct tegra_ivc;\n\nstruct tegra_bpmp_channel {\n\tstruct tegra_bpmp *bpmp;\n\tstruct iosys_map ib;\n\tstruct iosys_map ob;\n\tstruct completion completion;\n\tstruct tegra_ivc *ivc;\n\tunsigned int index;\n};\n\nstruct tegra_bpmp_clk {\n\tstruct clk_hw hw;\n\tstruct tegra_bpmp *bpmp;\n\tunsigned int id;\n\tunsigned int num_parents;\n\tunsigned int *parents;\n};\n\nstruct tegra_bpmp_clk_info {\n\tunsigned int id;\n\tchar name[40];\n\tunsigned int parents[16];\n\tunsigned int num_parents;\n\tlong unsigned int flags;\n};\n\nstruct tegra_bpmp_clk_message {\n\tunsigned int cmd;\n\tunsigned int id;\n\tstruct {\n\t\tconst void *data;\n\t\tsize_t size;\n\t} tx;\n\tstruct {\n\t\tvoid *data;\n\t\tsize_t size;\n\t\tint ret;\n\t} rx;\n};\n\nstruct tegra_bpmp_i2c {\n\tstruct i2c_adapter adapter;\n\tstruct device *dev;\n\tstruct tegra_bpmp *bpmp;\n\tunsigned int bus;\n};\n\nstruct tegra_bpmp_mb_data {\n\tu32 code;\n\tu32 flags;\n\tu8 data[120];\n};\n\nstruct tegra_bpmp_message {\n\tunsigned int mrq;\n\tstruct {\n\t\tconst void *data;\n\t\tsize_t size;\n\t} tx;\n\tstruct {\n\t\tvoid *data;\n\t\tsize_t size;\n\t\tint ret;\n\t} rx;\n\tlong unsigned int flags;\n};\n\ntypedef void (*tegra_bpmp_mrq_handler_t)(unsigned int, struct tegra_bpmp_channel *, void *);\n\nstruct tegra_bpmp_mrq {\n\tstruct list_head list;\n\tunsigned int mrq;\n\ttegra_bpmp_mrq_handler_t handler;\n\tvoid *data;\n};\n\nstruct tegra_bpmp_ops {\n\tint (*init)(struct tegra_bpmp *);\n\tvoid (*deinit)(struct tegra_bpmp *);\n\tbool (*is_response_ready)(struct tegra_bpmp_channel *);\n\tbool (*is_request_ready)(struct tegra_bpmp_channel *);\n\tint (*ack_response)(struct tegra_bpmp_channel *);\n\tint (*ack_request)(struct tegra_bpmp_channel *);\n\tbool (*is_response_channel_free)(struct tegra_bpmp_channel *);\n\tbool (*is_request_channel_free)(struct tegra_bpmp_channel *);\n\tint (*post_response)(struct tegra_bpmp_channel *);\n\tint (*post_request)(struct tegra_bpmp_channel *);\n\tint (*ring_doorbell)(struct tegra_bpmp *);\n\tint (*resume)(struct tegra_bpmp *);\n};\n\nstruct tegra_bpmp_soc {\n\tstruct {\n\t\tstruct {\n\t\t\tunsigned int offset;\n\t\t\tunsigned int count;\n\t\t\tunsigned int timeout;\n\t\t} cpu_tx;\n\t\tstruct {\n\t\t\tunsigned int offset;\n\t\t\tunsigned int count;\n\t\t\tunsigned int timeout;\n\t\t} thread;\n\t\tstruct {\n\t\t\tunsigned int offset;\n\t\t\tunsigned int count;\n\t\t\tunsigned int timeout;\n\t\t} cpu_rx;\n\t} channels;\n\tconst struct tegra_bpmp_ops *ops;\n\tunsigned int num_resets;\n};\n\nstruct tegra_cbb_error {\n\tconst char *code;\n\tconst char *source;\n\tconst char *desc;\n};\n\nstruct tegra_cbb_ops {\n\tint (*debugfs_show)(struct tegra_cbb *, struct seq_file *, void *);\n\tint (*interrupt_enable)(struct tegra_cbb *);\n\tvoid (*error_enable)(struct tegra_cbb *);\n\tvoid (*fault_enable)(struct tegra_cbb *);\n\tvoid (*stall_enable)(struct tegra_cbb *);\n\tvoid (*error_clear)(struct tegra_cbb *);\n\tu32 (*get_status)(struct tegra_cbb *);\n};\n\nstruct tegra_clk {\n\tint dt_id;\n\tbool present;\n};\n\nstruct tegra_clk_device {\n\tstruct notifier_block clk_nb;\n\tstruct device *dev;\n\tstruct clk_hw *hw;\n\tstruct mutex lock;\n};\n\nstruct tegra_clk_duplicate {\n\tint clk_id;\n\tstruct clk_lookup lookup;\n};\n\nstruct tegra_clk_frac_div {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 flags;\n\tu8 shift;\n\tu8 width;\n\tu8 frac_width;\n\tspinlock_t *lock;\n};\n\nstruct tegra_clk_init_table {\n\tunsigned int clk_id;\n\tunsigned int parent_id;\n\tlong unsigned int rate;\n\tint state;\n};\n\nstruct tegra_clk_periph_regs;\n\nstruct tegra_clk_periph_gate {\n\tu32 magic;\n\tstruct clk_hw hw;\n\tvoid *clk_base;\n\tu8 flags;\n\tint clk_num;\n\tint *enable_refcnt;\n\tconst struct tegra_clk_periph_regs *regs;\n};\n\nstruct tegra_clk_periph {\n\tu32 magic;\n\tstruct clk_hw hw;\n\tstruct clk_mux mux;\n\tstruct tegra_clk_frac_div divider;\n\tstruct tegra_clk_periph_gate gate;\n\tconst struct clk_ops *mux_ops;\n\tconst struct clk_ops *div_ops;\n\tconst struct clk_ops *gate_ops;\n};\n\nstruct tegra_clk_periph_fixed {\n\tstruct clk_hw hw;\n\tvoid *base;\n\tconst struct tegra_clk_periph_regs *regs;\n\tunsigned int mul;\n\tunsigned int div;\n\tunsigned int num;\n};\n\nstruct tegra_clk_periph_regs {\n\tu32 enb_reg;\n\tu32 enb_set_reg;\n\tu32 enb_clr_reg;\n\tu32 rst_reg;\n\tu32 rst_set_reg;\n\tu32 rst_clr_reg;\n};\n\nstruct tegra_clk_pll {\n\tstruct clk_hw hw;\n\tvoid *clk_base;\n\tvoid *pmc;\n\tspinlock_t *lock;\n\tstruct tegra_clk_pll_params *params;\n};\n\nstruct tegra_clk_pll_freq_table {\n\tlong unsigned int input_rate;\n\tlong unsigned int output_rate;\n\tu32 n;\n\tu32 m;\n\tu8 p;\n\tu8 cpcon;\n\tu16 sdm_data;\n};\n\nstruct tegra_clk_pll_out {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 enb_bit_idx;\n\tu8 rst_bit_idx;\n\tspinlock_t *lock;\n\tu8 flags;\n};\n\nstruct tegra_clk_pll_params {\n\tlong unsigned int input_min;\n\tlong unsigned int input_max;\n\tlong unsigned int cf_min;\n\tlong unsigned int cf_max;\n\tlong unsigned int vco_min;\n\tlong unsigned int vco_max;\n\tu32 base_reg;\n\tu32 misc_reg;\n\tu32 lock_reg;\n\tu32 lock_mask;\n\tu32 lock_enable_bit_idx;\n\tu32 iddq_reg;\n\tu32 iddq_bit_idx;\n\tu32 reset_reg;\n\tu32 reset_bit_idx;\n\tu32 sdm_din_reg;\n\tu32 sdm_din_mask;\n\tu32 sdm_ctrl_reg;\n\tu32 sdm_ctrl_en_mask;\n\tu32 ssc_ctrl_reg;\n\tu32 ssc_ctrl_en_mask;\n\tu32 aux_reg;\n\tu32 dyn_ramp_reg;\n\tu32 ext_misc_reg[6];\n\tu32 pmc_divnm_reg;\n\tu32 pmc_divp_reg;\n\tu32 flags;\n\tint stepa_shift;\n\tint stepb_shift;\n\tint lock_delay;\n\tint max_p;\n\tbool defaults_set;\n\tconst struct pdiv_map *pdiv_tohw;\n\tstruct div_nmp *div_nmp;\n\tstruct tegra_clk_pll_freq_table *freq_table;\n\tlong unsigned int fixed_rate;\n\tu16 mdiv_default;\n\tu32 (*round_p_to_pdiv)(u32, u32 *);\n\tvoid (*set_gain)(struct tegra_clk_pll_freq_table *);\n\tint (*calc_rate)(struct clk_hw *, struct tegra_clk_pll_freq_table *, long unsigned int, long unsigned int);\n\tlong unsigned int (*adjust_vco)(struct tegra_clk_pll_params *, long unsigned int);\n\tvoid (*set_defaults)(struct tegra_clk_pll *);\n\tint (*dyn_ramp)(struct tegra_clk_pll *, struct tegra_clk_pll_freq_table *);\n\tint (*pre_rate_change)(void);\n\tvoid (*post_rate_change)(void);\n};\n\nstruct tegra_clk_super_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tstruct tegra_clk_frac_div frac_div;\n\tconst struct clk_ops *div_ops;\n\tu8 width;\n\tu8 flags;\n\tu8 div2_index;\n\tu8 pllx_index;\n\tspinlock_t *lock;\n};\n\nstruct tegra_clk_sync_source {\n\tstruct clk_hw hw;\n\tlong unsigned int rate;\n\tlong unsigned int max_rate;\n};\n\nstruct tegra_core_opp_params {\n\tbool init_state;\n};\n\nstruct tegra_cpu_car_ops {\n\tvoid (*wait_for_reset)(u32);\n\tvoid (*put_in_reset)(u32);\n\tvoid (*out_of_reset)(u32);\n\tvoid (*enable_clock)(u32);\n\tvoid (*disable_clock)(u32);\n\tbool (*rail_off_ready)(void);\n\tvoid (*suspend)(void);\n\tvoid (*resume)(void);\n};\n\nstruct tegra_cpu_data {\n\tu32 cpuid;\n\tu32 clusterid;\n\tvoid *freq_core_reg;\n};\n\nstruct tegra_cpufreq_ops {\n\tvoid (*read_counters)(struct tegra_cpu_ctr *);\n\tvoid (*set_cpu_ndiv)(struct cpufreq_policy *, u64);\n\tvoid (*get_cpu_cluster_id)(u32, u32 *, u32 *);\n\tint (*get_cpu_ndiv)(u32, u32, u32, u64 *);\n};\n\nstruct tegra_cpufreq_soc {\n\tstruct tegra_cpufreq_ops *ops;\n\tint maxcpus_per_cluster;\n\tunsigned int num_clusters;\n\tphys_addr_t actmon_cntr_base;\n\tu32 refclk_delta_min;\n};\n\nstruct tegra_devclk {\n\tint dt_id;\n\tchar *dev_id;\n\tchar *con_id;\n};\n\nstruct tegra_dfll_soc_data;\n\nstruct tegra_dfll {\n\tstruct device *dev;\n\tstruct tegra_dfll_soc_data *soc;\n\tvoid *base;\n\tvoid *i2c_base;\n\tvoid *i2c_controller_base;\n\tvoid *lut_base;\n\tstruct regulator *vdd_reg;\n\tstruct clk *soc_clk;\n\tstruct clk *ref_clk;\n\tstruct clk *i2c_clk;\n\tstruct clk *dfll_clk;\n\tstruct reset_control *dfll_rst;\n\tstruct reset_control *dvco_rst;\n\tlong unsigned int ref_rate;\n\tlong unsigned int i2c_clk_rate;\n\tlong unsigned int dvco_rate_min;\n\tenum dfll_ctrl_mode mode;\n\tenum dfll_tune_range tune_range;\n\tstruct dentry *debugfs_dir;\n\tstruct clk_hw dfll_clk_hw;\n\tconst char *output_clock_name;\n\tstruct dfll_rate_req last_req;\n\tlong unsigned int last_unrounded_rate;\n\tu32 droop_ctrl;\n\tu32 sample_rate;\n\tu32 force_mode;\n\tu32 cf;\n\tu32 ci;\n\tu32 cg;\n\tbool cg_scale;\n\tu32 i2c_fs_rate;\n\tu32 i2c_reg;\n\tu32 i2c_slave_addr;\n\tunsigned int lut[33];\n\tlong unsigned int lut_uv[33];\n\tint lut_size;\n\tu8 lut_bottom;\n\tu8 lut_min;\n\tu8 lut_max;\n\tu8 lut_safe;\n\tenum tegra_dfll_pmu_if pmu_if;\n\tlong unsigned int pwm_rate;\n\tstruct pinctrl *pwm_pin;\n\tstruct pinctrl_state *pwm_enable_state;\n\tstruct pinctrl_state *pwm_disable_state;\n\tu32 reg_init_uV;\n};\n\nstruct tegra_dfll_soc_data {\n\tstruct device *dev;\n\tlong unsigned int max_freq;\n\tconst struct cvb_table *cvb;\n\tstruct rail_alignment alignment;\n\tvoid (*init_clock_trimmers)(void);\n\tvoid (*set_clock_trimmers_high)(void);\n\tvoid (*set_clock_trimmers_low)(void);\n};\n\nstruct tegra_dma;\n\nstruct tegra_dma_desc;\n\nstruct tegra_dma_channel {\n\tbool config_init;\n\tchar name[30];\n\tenum dma_transfer_direction sid_dir;\n\tenum dma_status status;\n\tint id;\n\tint irq;\n\tint slave_id;\n\tstruct tegra_dma *tdma;\n\tstruct virt_dma_chan vc;\n\tstruct tegra_dma_desc *dma_desc;\n\tstruct dma_slave_config dma_sconfig;\n\tunsigned int stream_id;\n\tlong unsigned int chan_base_offset;\n};\n\nstruct tegra_dma_chip_data;\n\nstruct tegra_dma {\n\tconst struct tegra_dma_chip_data *chip_data;\n\tlong unsigned int sid_m2d_reserved;\n\tlong unsigned int sid_d2m_reserved;\n\tu32 chan_mask;\n\tvoid *base_addr;\n\tstruct device *dev;\n\tstruct dma_device dma_dev;\n\tstruct reset_control *rst;\n\tstruct tegra_dma_channel channels[0];\n};\n\nstruct tegra_dma_channel___2;\n\ntypedef void (*dma_isr_handler)(struct tegra_dma_channel___2 *, bool);\n\nstruct tegra_dma_channel_regs {\n\tu32 csr;\n\tu32 ahb_ptr;\n\tu32 apb_ptr;\n\tu32 ahb_seq;\n\tu32 apb_seq;\n\tu32 wcount;\n};\n\nstruct tegra_dma___2;\n\nstruct tegra_dma_channel___2 {\n\tstruct dma_chan dma_chan;\n\tchar name[12];\n\tbool config_init;\n\tunsigned int id;\n\tvoid *chan_addr;\n\tspinlock_t lock;\n\tbool busy;\n\tstruct tegra_dma___2 *tdma;\n\tbool cyclic;\n\tstruct list_head free_sg_req;\n\tstruct list_head pending_sg_req;\n\tstruct list_head free_dma_desc;\n\tstruct list_head cb_desc;\n\tdma_isr_handler isr_handler;\n\tstruct tasklet_struct tasklet;\n\tunsigned int slave_id;\n\tstruct dma_slave_config dma_sconfig;\n\tstruct tegra_dma_channel_regs channel_reg;\n\tstruct wait_queue_head wq;\n};\n\nstruct tegra_dma_chip_data___2;\n\nstruct tegra_dma___2 {\n\tstruct dma_device dma_dev;\n\tstruct device *dev;\n\tstruct clk *dma_clk;\n\tstruct reset_control *rst;\n\tspinlock_t global_lock;\n\tvoid *base_addr;\n\tconst struct tegra_dma_chip_data___2 *chip_data;\n\tu32 global_pause_count;\n\tstruct tegra_dma_channel___2 channels[0];\n};\n\nstruct tegra_dma_channel_regs___2 {\n\tu32 csr;\n\tu32 src_ptr;\n\tu32 dst_ptr;\n\tu32 high_addr_ptr;\n\tu32 mc_seq;\n\tu32 mmio_seq;\n\tu32 wcount;\n\tu32 fixed_pattern;\n};\n\nstruct tegra_dma_chip_data___2 {\n\tunsigned int nr_channels;\n\tunsigned int channel_reg_size;\n\tunsigned int max_dma_count;\n\tbool support_channel_pause;\n\tbool support_separate_wcount_reg;\n};\n\nstruct tegra_dma_chip_data {\n\tbool hw_support_pause;\n\tunsigned int nr_channels;\n\tunsigned int channel_reg_size;\n\tunsigned int max_dma_count;\n\tint (*terminate)(struct tegra_dma_channel *);\n};\n\nstruct tegra_dma_desc___2 {\n\tstruct dma_async_tx_descriptor txd;\n\tunsigned int bytes_requested;\n\tunsigned int bytes_transferred;\n\tenum dma_status dma_status;\n\tstruct list_head node;\n\tstruct list_head tx_list;\n\tstruct list_head cb_node;\n\tunsigned int cb_count;\n};\n\nstruct tegra_dma_sg_req {\n\tunsigned int len;\n\tstruct tegra_dma_channel_regs___2 ch_regs;\n};\n\nstruct tegra_dma_desc {\n\tbool cyclic;\n\tunsigned int bytes_req;\n\tunsigned int bytes_xfer;\n\tunsigned int sg_idx;\n\tunsigned int sg_count;\n\tstruct virt_dma_desc vd;\n\tstruct tegra_dma_channel *tdc;\n\tstruct tegra_dma_sg_req sg_req[0];\n};\n\nstruct tegra_dma_sg_req___2 {\n\tstruct tegra_dma_channel_regs ch_regs;\n\tunsigned int req_len;\n\tbool configured;\n\tbool last_sg;\n\tstruct list_head node;\n\tstruct tegra_dma_desc___2 *dma_desc;\n\tunsigned int words_xferred;\n};\n\nstruct tegra_function {\n\tconst char *name;\n\tconst char **groups;\n\tunsigned int ngroups;\n};\n\nstruct tegra_fuse_soc;\n\nstruct tegra_fuse {\n\tstruct device *dev;\n\tvoid *base;\n\tphys_addr_t phys;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tu32 (*read_early)(struct tegra_fuse *, unsigned int);\n\tu32 (*read)(struct tegra_fuse *, unsigned int);\n\tconst struct tegra_fuse_soc *soc;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct completion wait;\n\t\tstruct dma_chan *chan;\n\t\tstruct dma_slave_config config;\n\t\tdma_addr_t phys;\n\t\tu32 *virt;\n\t} apbdma;\n\tstruct nvmem_device *nvmem;\n\tstruct nvmem_cell_lookup *lookups;\n};\n\nstruct tegra_fuse_info {\n\tu32 (*read)(struct tegra_fuse *, unsigned int);\n\tunsigned int size;\n\tunsigned int spare;\n};\n\nstruct tegra_sku_info;\n\nstruct tegra_fuse_soc {\n\tvoid (*init)(struct tegra_fuse *);\n\tvoid (*speedo_init)(struct tegra_sku_info *);\n\tint (*probe)(struct tegra_fuse *);\n\tconst struct tegra_fuse_info *info;\n\tconst struct nvmem_cell_lookup *lookups;\n\tunsigned int num_lookups;\n\tconst struct nvmem_cell_info *cells;\n\tunsigned int num_cells;\n\tconst struct nvmem_keepout *keepouts;\n\tunsigned int num_keepouts;\n\tconst struct attribute_group *soc_attr_group;\n\tbool clk_suspend_on;\n};\n\nstruct tegra_gpio_soc;\n\nstruct tegra_gpio {\n\tstruct gpio_chip gpio;\n\tunsigned int num_irq;\n\tunsigned int *irq;\n\tconst struct tegra_gpio_soc *soc;\n\tunsigned int num_irqs_per_bank;\n\tunsigned int num_banks;\n\tvoid *secure;\n\tvoid *base;\n};\n\nstruct tegra_gpio_bank {\n\tunsigned int bank;\n\traw_spinlock_t lvl_lock[4];\n\tspinlock_t dbc_lock[4];\n\tu32 cnf[4];\n\tu32 out[4];\n\tu32 oe[4];\n\tu32 int_enb[4];\n\tu32 int_lvl[4];\n\tu32 wake_enb[4];\n\tu32 dbc_enb[4];\n\tu32 dbc_cnt[4];\n};\n\nstruct tegra_gpio_soc_config;\n\nstruct tegra_gpio_info {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct tegra_gpio_bank *bank_info;\n\tconst struct tegra_gpio_soc_config *soc;\n\tstruct gpio_chip gc;\n\tu32 bank_count;\n\tunsigned int *irqs;\n};\n\nstruct tegra_gpio_port {\n\tconst char *name;\n\tunsigned int bank;\n\tunsigned int port;\n\tunsigned int pins;\n};\n\nstruct tegra_gpio_soc {\n\tconst struct tegra_gpio_port *ports;\n\tunsigned int num_ports;\n\tconst char *name;\n\tconst char *prefix;\n\tunsigned int instance;\n\tunsigned int num_irqs_per_bank;\n\tconst struct tegra186_pin_range *pin_ranges;\n\tunsigned int num_pin_ranges;\n\tconst char *pinmux;\n\tbool has_gte;\n\tbool has_vm_support;\n};\n\nstruct tegra_gpio_soc_config {\n\tbool debounce_supported;\n\tu32 bank_stride;\n\tu32 upper_offset;\n};\n\nstruct tegra_hsp_soc;\n\nstruct tegra_hsp_mailbox;\n\nstruct tegra_hsp {\n\tstruct device *dev;\n\tconst struct tegra_hsp_soc *soc;\n\tstruct mbox_controller mbox_db;\n\tstruct mbox_controller mbox_sm;\n\tvoid *regs;\n\tunsigned int doorbell_irq;\n\tunsigned int *shared_irqs;\n\tunsigned int shared_irq;\n\tunsigned int num_sm;\n\tunsigned int num_as;\n\tunsigned int num_ss;\n\tunsigned int num_db;\n\tunsigned int num_si;\n\tspinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct list_head doorbells;\n\tstruct tegra_hsp_mailbox *mailboxes;\n\tlong unsigned int mask;\n};\n\nstruct tegra_hsp_channel {\n\tstruct tegra_hsp *hsp;\n\tstruct mbox_chan *chan;\n\tvoid *regs;\n};\n\nstruct tegra_hsp_db_map {\n\tconst char *name;\n\tunsigned int master;\n\tunsigned int index;\n};\n\nstruct tegra_hsp_doorbell {\n\tstruct tegra_hsp_channel channel;\n\tstruct list_head list;\n\tconst char *name;\n\tunsigned int master;\n\tunsigned int index;\n};\n\nstruct tegra_hsp_sm_ops;\n\nstruct tegra_hsp_mailbox {\n\tstruct tegra_hsp_channel channel;\n\tconst struct tegra_hsp_sm_ops *ops;\n\tunsigned int index;\n\tbool producer;\n};\n\nstruct tegra_hsp_sm_ops {\n\tvoid (*send)(struct tegra_hsp_channel *, void *);\n\tvoid (*recv)(struct tegra_hsp_channel *);\n};\n\nstruct tegra_hsp_soc {\n\tconst struct tegra_hsp_db_map *map;\n\tbool has_per_mb_ie;\n\tbool has_128_bit_mb;\n\tunsigned int reg_stride;\n\tunsigned int si_shift;\n\tunsigned int db_shift;\n\tunsigned int as_shift;\n\tunsigned int ss_shift;\n\tunsigned int sm_shift;\n\tunsigned int si_mask;\n\tunsigned int db_mask;\n\tunsigned int as_mask;\n\tunsigned int ss_mask;\n\tunsigned int sm_mask;\n};\n\nstruct tegra_hte_line_mapped;\n\nstruct tegra_hte_data {\n\tenum tegra_hte_type type;\n\tu32 slices;\n\tu32 map_sz;\n\tu32 sec_map_sz;\n\tconst struct tegra_hte_line_mapped *map;\n\tconst struct tegra_hte_line_mapped *sec_map;\n};\n\nstruct tegra_hte_line_data {\n\tlong unsigned int flags;\n\tvoid *data;\n};\n\nstruct tegra_hte_line_mapped {\n\tint slice;\n\tu32 bit_index;\n};\n\nstruct tegra_hte_soc {\n\tint hte_irq;\n\tu32 itr_thrshld;\n\tu32 conf_rval;\n\tstruct hte_slices *sl;\n\tconst struct tegra_hte_data *prov_data;\n\tstruct tegra_hte_line_data *line_data;\n\tstruct hte_chip *chip;\n\tstruct gpio_device *gdev;\n\tvoid *regs;\n};\n\nstruct tegra_i2c_hw_feature;\n\nstruct tegra_i2c_dev {\n\tstruct device *dev;\n\tstruct i2c_adapter adapter;\n\tconst struct tegra_i2c_hw_feature *hw;\n\tunsigned int cont_id;\n\tunsigned int irq;\n\tphys_addr_t base_phys;\n\tvoid *base;\n\tstruct clk_bulk_data clocks[2];\n\tunsigned int nclocks;\n\tstruct clk *div_clk;\n\tstruct i2c_timings timings;\n\tstruct completion msg_complete;\n\tsize_t msg_buf_remaining;\n\tunsigned int msg_len;\n\tint msg_err;\n\tu8 *msg_buf;\n\tstruct completion dma_complete;\n\tstruct dma_chan *dma_chan;\n\tunsigned int dma_buf_size;\n\tstruct device *dma_dev;\n\tdma_addr_t dma_phys;\n\tvoid *dma_buf;\n\tbool multimaster_mode;\n\tbool atomic_mode;\n\tbool dma_mode;\n\tbool msg_read;\n\tbool is_dvc;\n\tbool is_vi;\n};\n\nstruct tegra_i2c_hw_feature {\n\tbool has_continue_xfer_support;\n\tbool has_per_pkt_xfer_complete_irq;\n\tbool has_config_load_reg;\n\tu32 clk_divisor_hs_mode;\n\tu32 clk_divisor_std_mode;\n\tu32 clk_divisor_fast_mode;\n\tu32 clk_divisor_fast_plus_mode;\n\tbool has_multi_master_mode;\n\tbool has_slcg_override_reg;\n\tbool has_mst_fifo;\n\tbool has_mst_reset;\n\tconst struct i2c_adapter_quirks *quirks;\n\tbool supports_bus_clear;\n\tbool has_apb_dma;\n\tu32 tlow_std_mode;\n\tu32 thigh_std_mode;\n\tu32 tlow_fast_mode;\n\tu32 thigh_fast_mode;\n\tu32 tlow_fastplus_mode;\n\tu32 thigh_fastplus_mode;\n\tu32 tlow_hs_mode;\n\tu32 thigh_hs_mode;\n\tu32 setup_hold_time_std_mode;\n\tu32 setup_hold_time_fast_mode;\n\tu32 setup_hold_time_fastplus_mode;\n\tu32 setup_hold_time_hs_mode;\n\tbool has_interface_timing_reg;\n\tbool enable_hs_mode_support;\n\tbool has_mutex;\n};\n\nstruct tegra_ictlr_info {\n\tvoid *base[6];\n\tu32 cop_ier[6];\n\tu32 cop_iep[6];\n\tu32 cpu_ier[6];\n\tu32 cpu_iep[6];\n\tu32 ictlr_wake_mask[6];\n};\n\nstruct tegra_ictlr_soc {\n\tunsigned int num_ictlrs;\n};\n\nstruct tegra_io_pad_soc {\n\tenum tegra_io_pad id;\n\tunsigned int dpd;\n\tunsigned int request;\n\tunsigned int status;\n\tunsigned int voltage;\n\tconst char *name;\n};\n\nstruct tegra_ivc {\n\tstruct device *peer;\n\tstruct {\n\t\tstruct iosys_map map;\n\t\tunsigned int position;\n\t\tdma_addr_t phys;\n\t} rx;\n\tstruct {\n\t\tstruct iosys_map map;\n\t\tunsigned int position;\n\t\tdma_addr_t phys;\n\t} tx;\n\tvoid (*notify)(struct tegra_ivc *, void *);\n\tvoid *notify_data;\n\tunsigned int num_frames;\n\tsize_t frame_size;\n};\n\nstruct tegra_ivc_header {\n\tunion {\n\t\tstruct {\n\t\t\tu32 count;\n\t\t\tu32 state;\n\t\t};\n\t\tu8 pad[64];\n\t} tx;\n\tunion {\n\t\tu32 count;\n\t\tu8 pad[64];\n\t} rx;\n};\n\nstruct tegra_smmu;\n\nstruct tegra_mc_soc;\n\nstruct tegra_mc_timing;\n\nstruct tegra_mc {\n\tstruct tegra_bpmp *bpmp;\n\tstruct device *dev;\n\tstruct tegra_smmu *smmu;\n\tvoid *regs;\n\tvoid *bcast_ch_regs;\n\tvoid **ch_regs;\n\tstruct clk *clk;\n\tint irq;\n\tconst struct tegra_mc_soc *soc;\n\tlong unsigned int tick;\n\tstruct tegra_mc_timing *timings;\n\tunsigned int num_timings;\n\tunsigned int num_channels;\n\tbool bwmgr_mrq_supported;\n\tstruct reset_controller_dev reset;\n\tstruct icc_provider provider;\n\tspinlock_t lock;\n\tstruct {\n\t\tstruct dentry *root;\n\t} debugfs;\n};\n\nstruct tegra_mc_client {\n\tunsigned int id;\n\tunsigned int bpmp_id;\n\tenum tegra_icc_client_type type;\n\tconst char *name;\n\tunion {\n\t\tunsigned int swgroup;\n\t\tunsigned int sid;\n\t};\n\tunsigned int fifo_size;\n\tstruct {\n\t\tstruct {\n\t\t\tunsigned int reg;\n\t\t\tunsigned int bit;\n\t\t} smmu;\n\t\tstruct {\n\t\t\tunsigned int reg;\n\t\t\tunsigned int shift;\n\t\t\tunsigned int mask;\n\t\t\tunsigned int def;\n\t\t} la;\n\t\tstruct {\n\t\t\tunsigned int override;\n\t\t\tunsigned int security;\n\t\t} sid;\n\t} regs;\n};\n\nstruct tegra_mc_icc_ops {\n\tint (*set)(struct icc_node *, struct icc_node *);\n\tint (*aggregate)(struct icc_node *, u32, u32, u32, u32 *, u32 *);\n\tstruct icc_node * (*xlate)(const struct of_phandle_args *, void *);\n\tstruct icc_node_data * (*xlate_extended)(const struct of_phandle_args *, void *);\n\tint (*get_bw)(struct icc_node *, u32 *, u32 *);\n};\n\nstruct tegra_mc_ops {\n\tint (*probe)(struct tegra_mc *);\n\tvoid (*remove)(struct tegra_mc *);\n\tint (*resume)(struct tegra_mc *);\n\tirqreturn_t (*handle_irq)(int, void *);\n\tint (*probe_device)(struct tegra_mc *, struct device *);\n};\n\nstruct tegra_mc_reset {\n\tconst char *name;\n\tlong unsigned int id;\n\tunsigned int control;\n\tunsigned int status;\n\tunsigned int reset;\n\tunsigned int bit;\n};\n\nstruct tegra_mc_reset_ops {\n\tint (*hotreset_assert)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*hotreset_deassert)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*block_dma)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tbool (*dma_idling)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*unblock_dma)(struct tegra_mc *, const struct tegra_mc_reset *);\n\tint (*reset_status)(struct tegra_mc *, const struct tegra_mc_reset *);\n};\n\nstruct tegra_smmu_soc;\n\nstruct tegra_mc_soc {\n\tconst struct tegra_mc_client *clients;\n\tunsigned int num_clients;\n\tconst long unsigned int *emem_regs;\n\tunsigned int num_emem_regs;\n\tunsigned int num_address_bits;\n\tunsigned int atom_size;\n\tunsigned int num_carveouts;\n\tu16 client_id_mask;\n\tu8 num_channels;\n\tconst struct tegra_smmu_soc *smmu;\n\tu32 intmask;\n\tu32 ch_intmask;\n\tu32 global_intstatus_channel_shift;\n\tbool has_addr_hi_reg;\n\tconst struct tegra_mc_reset_ops *reset_ops;\n\tconst struct tegra_mc_reset *resets;\n\tunsigned int num_resets;\n\tconst struct tegra_mc_icc_ops *icc_ops;\n\tconst struct tegra_mc_ops *ops;\n};\n\nstruct tegra_mc_timing {\n\tlong unsigned int rate;\n\tu32 *emem_data;\n};\n\nstruct tegra_msi {\n\tlong unsigned int used[4];\n\tstruct irq_domain *domain;\n\tstruct mutex map_lock;\n\traw_spinlock_t mask_lock;\n\tvoid *virt;\n\tdma_addr_t phys;\n\tint irq;\n};\n\nstruct tegra_pcie_soc;\n\nstruct tegra_pcie {\n\tstruct device *dev;\n\tvoid *pads;\n\tvoid *afi;\n\tvoid *cfg;\n\tint irq;\n\tstruct resource cs;\n\tstruct clk *pex_clk;\n\tstruct clk *afi_clk;\n\tstruct clk *pll_e;\n\tstruct clk *cml_clk;\n\tstruct reset_control *pex_rst;\n\tstruct reset_control *afi_rst;\n\tstruct reset_control *pcie_xrst;\n\tbool legacy_phy;\n\tstruct phy *phy;\n\tstruct tegra_msi msi;\n\tstruct list_head ports;\n\tu32 xbar_config;\n\tstruct regulator_bulk_data *supplies;\n\tunsigned int num_supplies;\n\tconst struct tegra_pcie_soc *soc;\n\tstruct dentry *debugfs;\n};\n\nstruct tegra_pcie_port {\n\tstruct tegra_pcie *pcie;\n\tstruct device_node *np;\n\tstruct list_head list;\n\tstruct resource regs;\n\tvoid *base;\n\tunsigned int index;\n\tunsigned int lanes;\n\tstruct phy **phys;\n\tstruct gpio_desc *reset_gpio;\n};\n\nstruct tegra_pcie_port_soc {\n\tstruct {\n\t\tu8 turnoff_bit;\n\t\tu8 ack_bit;\n\t} pme;\n};\n\nstruct tegra_pcie_soc {\n\tunsigned int num_ports;\n\tconst struct tegra_pcie_port_soc *ports;\n\tunsigned int msi_base_shift;\n\tlong unsigned int afi_pex2_ctrl;\n\tu32 pads_pll_ctl;\n\tu32 tx_ref_sel;\n\tu32 pads_refclk_cfg0;\n\tu32 pads_refclk_cfg1;\n\tu32 update_fc_threshold;\n\tbool has_pex_clkreq_en;\n\tbool has_pex_bias_ctrl;\n\tbool has_intr_prsnt_sense;\n\tbool has_cml_clk;\n\tbool has_gen2;\n\tbool force_pca_enable;\n\tbool program_uphy;\n\tbool update_clamp_threshold;\n\tbool program_deskew_time;\n\tbool update_fc_timer;\n\tbool has_cache_bars;\n\tstruct {\n\t\tstruct {\n\t\t\tu32 rp_ectl_2_r1;\n\t\t\tu32 rp_ectl_4_r1;\n\t\t\tu32 rp_ectl_5_r1;\n\t\t\tu32 rp_ectl_6_r1;\n\t\t\tu32 rp_ectl_2_r2;\n\t\t\tu32 rp_ectl_4_r2;\n\t\t\tu32 rp_ectl_5_r2;\n\t\t\tu32 rp_ectl_6_r2;\n\t\t} regs;\n\t\tbool enable;\n\t} ectl;\n};\n\nstruct tegra_pd {\n\tu32 val[1024];\n};\n\nstruct tegra_periph_init_data {\n\tconst char *name;\n\tint clk_id;\n\tunion {\n\t\tconst char * const *parent_names;\n\t\tconst char *parent_name;\n\t} p;\n\tint num_parents;\n\tstruct tegra_clk_periph periph;\n\tu32 offset;\n\tconst char *con_id;\n\tconst char *dev_id;\n\tlong unsigned int flags;\n};\n\nstruct tegra_phy_soc_config {\n\tbool utmi_pll_config_in_car_module;\n\tbool has_hostpc;\n\tbool requires_usbmode_setup;\n\tbool requires_extra_tuning_parameters;\n\tbool requires_pmc_ao_power_up;\n\tu32 uhsic_registers_offset;\n\tu32 uhsic_tx_rtune;\n\tu32 uhsic_pts_value;\n\tu32 portsc1_offset;\n};\n\nstruct tegra_pingroup;\n\nstruct tegra_pinctrl_soc_data {\n\tunsigned int ngpios;\n\tconst char *gpio_compatible;\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst char * const *functions;\n\tunsigned int nfunctions;\n\tconst struct tegra_pingroup *groups;\n\tunsigned int ngroups;\n\tbool hsm_in_mux;\n\tbool schmitt_in_mux;\n\tbool drvtype_in_mux;\n\tbool sfsel_in_mux;\n};\n\nstruct tegra_pingroup {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tu8 npins;\n\tu8 funcs[4];\n\ts32 mux_reg;\n\ts32 pupd_reg;\n\ts32 tri_reg;\n\ts32 drv_reg;\n\tu32 mux_bank: 2;\n\tu32 pupd_bank: 2;\n\tu32 tri_bank: 2;\n\tu32 drv_bank: 2;\n\ts32 mux_bit: 6;\n\ts32 pupd_bit: 6;\n\ts32 tri_bit: 6;\n\ts32 einput_bit: 6;\n\ts32 odrain_bit: 6;\n\ts32 lock_bit: 6;\n\ts32 ioreset_bit: 6;\n\ts32 rcv_sel_bit: 6;\n\ts32 hsm_bit: 6;\n\tlong: 2;\n\ts32 sfsel_bit: 6;\n\ts32 schmitt_bit: 6;\n\ts32 lpmd_bit: 6;\n\ts32 drvdn_bit: 6;\n\ts32 drvup_bit: 6;\n\tint: 2;\n\ts32 slwr_bit: 6;\n\ts32 slwf_bit: 6;\n\ts32 lpdr_bit: 6;\n\ts32 drvtype_bit: 6;\n\ts32 drvdn_width: 6;\n\tlong: 2;\n\ts32 drvup_width: 6;\n\ts32 slwr_width: 6;\n\ts32 slwf_width: 6;\n\tu32 parked_bitmask;\n};\n\nstruct tegra_pingroup_config {\n\tbool is_sfsel;\n};\n\nstruct tegra_pmc_soc;\n\nstruct tegra_pmc {\n\tstruct device *dev;\n\tvoid *base;\n\tvoid *wake;\n\tvoid *aotag;\n\tvoid *scratch;\n\tstruct clk *clk;\n\tconst struct tegra_pmc_soc *soc;\n\tbool tz_only;\n\tlong unsigned int rate;\n\tenum tegra_suspend_mode suspend_mode;\n\tu32 cpu_good_time;\n\tu32 cpu_off_time;\n\tu32 core_osc_time;\n\tu32 core_pmu_time;\n\tu32 core_off_time;\n\tbool corereq_high;\n\tbool sysclkreq_high;\n\tbool combined_req;\n\tbool cpu_pwr_good_en;\n\tu32 lp0_vec_phys;\n\tu32 lp0_vec_size;\n\tlong unsigned int powergates_available[1];\n\tstruct mutex powergates_lock;\n\tstruct pinctrl_dev *pctl_dev;\n\tstruct irq_domain *domain;\n\tstruct irq_chip irq;\n\tstruct notifier_block clk_nb;\n\tbool core_domain_state_synced;\n\tlong unsigned int *wake_type_level_map;\n\tlong unsigned int *wake_type_dual_edge_map;\n\tlong unsigned int *wake_sw_status_map;\n\tlong unsigned int *wake_cntrl_level_map;\n\tstruct notifier_block reboot_notifier;\n\tstruct syscore syscore;\n\tstruct irq_work wake_work;\n\tu32 *wake_status;\n};\n\nstruct tegra_pmc_core_pd {\n\tstruct generic_pm_domain genpd;\n\tstruct tegra_pmc *pmc;\n};\n\nstruct tegra_pmc_regs {\n\tunsigned int scratch0;\n\tunsigned int rst_status;\n\tunsigned int rst_source_shift;\n\tunsigned int rst_source_mask;\n\tunsigned int rst_level_shift;\n\tunsigned int rst_level_mask;\n};\n\nstruct tegra_wake_event;\n\nstruct tegra_pmc_soc {\n\tunsigned int num_powergates;\n\tconst char * const *powergates;\n\tunsigned int num_cpu_powergates;\n\tconst u8 *cpu_powergates;\n\tbool has_tsense_reset;\n\tbool has_gpu_clamps;\n\tbool needs_mbist_war;\n\tbool has_impl_33v_pwr;\n\tbool maybe_tz_only;\n\tconst struct tegra_io_pad_soc *io_pads;\n\tunsigned int num_io_pads;\n\tconst struct pinctrl_pin_desc *pin_descs;\n\tunsigned int num_pin_descs;\n\tconst struct tegra_pmc_regs *regs;\n\tvoid (*init)(struct tegra_pmc *);\n\tvoid (*setup_irq_polarity)(struct tegra_pmc *, struct device_node *, bool);\n\tvoid (*set_wake_filters)(struct tegra_pmc *);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*powergate_set)(struct tegra_pmc *, unsigned int, bool);\n\tconst char * const *reset_sources;\n\tunsigned int num_reset_sources;\n\tconst char * const *reset_levels;\n\tunsigned int num_reset_levels;\n\tconst struct tegra_wake_event *wake_events;\n\tunsigned int num_wake_events;\n\tunsigned int max_wake_events;\n\tunsigned int max_wake_vectors;\n\tconst struct pmc_clk_init_data *pmc_clks_data;\n\tunsigned int num_pmc_clks;\n\tbool has_blink_output;\n\tbool has_usb_sleepwalk;\n\tbool supports_core_domain;\n\tbool has_single_mmio_aperture;\n};\n\nstruct tegra_pmx {\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tconst struct tegra_pinctrl_soc_data *soc;\n\tstruct tegra_function *functions;\n\tconst char **group_pins;\n\tstruct pinctrl_gpio_range gpio_range;\n\tstruct pinctrl_desc desc;\n\tint nbanks;\n\tvoid **regs;\n\tu32 *backup_regs;\n\tstruct tegra_pingroup_config *pingroup_configs;\n};\n\nstruct tegra_powergate {\n\tstruct generic_pm_domain genpd;\n\tstruct tegra_pmc *pmc;\n\tunsigned int id;\n\tstruct clk **clks;\n\tunsigned int num_clks;\n\tlong unsigned int *clk_rates;\n\tstruct reset_control *reset;\n};\n\nstruct tegra_powergate___2 {\n\tstruct generic_pm_domain genpd;\n\tstruct tegra_bpmp *bpmp;\n\tunsigned int id;\n};\n\nstruct tegra_powergate_info {\n\tunsigned int id;\n\tchar *name;\n};\n\nstruct tegra_pt {\n\tu32 val[1024];\n};\n\nstruct tegra_rtc_info {\n\tstruct platform_device *pdev;\n\tstruct rtc_device *rtc;\n\tvoid *base;\n\tstruct clk *clk;\n\tint irq;\n\tspinlock_t lock;\n};\n\nstruct tegra_sdmmc_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tspinlock_t *lock;\n\tconst struct clk_ops *gate_ops;\n\tstruct tegra_clk_periph_gate gate;\n\tu8 div_flags;\n};\n\nstruct tegra_sku_info {\n\tint sku_id;\n\tint cpu_process_id;\n\tint cpu_speedo_id;\n\tint cpu_speedo_value;\n\tint cpu_iddq_value;\n\tint soc_process_id;\n\tint soc_speedo_id;\n\tint soc_speedo_value;\n\tint gpu_process_id;\n\tint gpu_speedo_id;\n\tint gpu_speedo_value;\n\tenum tegra_revision revision;\n\tenum tegra_platform platform;\n};\n\nstruct tegra_smmu {\n\tvoid *regs;\n\tstruct device *dev;\n\tstruct tegra_mc *mc;\n\tconst struct tegra_smmu_soc *soc;\n\tstruct list_head groups;\n\tlong unsigned int pfn_mask;\n\tlong unsigned int tlb_mask;\n\tlong unsigned int *asids;\n\tstruct mutex lock;\n\tstruct list_head list;\n\tstruct dentry *debugfs;\n\tstruct iommu_device iommu;\n};\n\nstruct tegra_smmu_as {\n\tstruct iommu_domain domain;\n\tstruct tegra_smmu *smmu;\n\tunsigned int use_count;\n\tspinlock_t lock;\n\tu32 *count;\n\tstruct tegra_pt **pts;\n\tstruct tegra_pd *pd;\n\tdma_addr_t pd_dma;\n\tunsigned int id;\n\tu32 attr;\n};\n\nstruct tegra_smmu_group_soc;\n\nstruct tegra_smmu_group {\n\tstruct list_head list;\n\tstruct tegra_smmu *smmu;\n\tconst struct tegra_smmu_group_soc *soc;\n\tstruct iommu_group *group;\n\tunsigned int swgroup;\n};\n\nstruct tegra_smmu_group_soc {\n\tconst char *name;\n\tconst unsigned int *swgroups;\n\tunsigned int num_swgroups;\n};\n\nstruct tegra_smmu_swgroup;\n\nstruct tegra_smmu_soc {\n\tconst struct tegra_mc_client *clients;\n\tunsigned int num_clients;\n\tconst struct tegra_smmu_swgroup *swgroups;\n\tunsigned int num_swgroups;\n\tconst struct tegra_smmu_group_soc *groups;\n\tunsigned int num_groups;\n\tbool supports_round_robin_arbitration;\n\tbool supports_request_limit;\n\tunsigned int num_tlb_lines;\n\tunsigned int num_asids;\n};\n\nstruct tegra_smmu_swgroup {\n\tconst char *name;\n\tunsigned int swgroup;\n\tunsigned int reg;\n};\n\nstruct tegra_super_gen_info {\n\tenum tegra_super_gen gen;\n\tconst char **sclk_parents;\n\tconst char **cclk_g_parents;\n\tconst char **cclk_lp_parents;\n\tint num_sclk_parents;\n\tint num_cclk_g_parents;\n\tint num_cclk_lp_parents;\n};\n\nstruct tegra_sync_source_initdata {\n\tchar *name;\n\tlong unsigned int rate;\n\tlong unsigned int max_rate;\n\tint clk_id;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct tegra_tcu {\n\tstruct uart_driver driver;\n\tstruct console console;\n\tstruct uart_port port;\n\tstruct mbox_client tx_client;\n\tstruct mbox_client rx_client;\n\tstruct mbox_chan *tx;\n\tstruct mbox_chan *rx;\n};\n\nstruct tegra_uart {\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tint line;\n};\n\nstruct tegra_uart_chip_data {\n\tbool tx_fifo_full_status;\n\tbool allow_txfifo_reset_fifo_mode;\n\tbool support_clk_src_div;\n\tbool fifo_mode_enable_status;\n\tint uart_max_port;\n\tint max_dma_burst_bytes;\n\tint error_tolerance_low_range;\n\tint error_tolerance_high_range;\n};\n\nstruct tegra_uart_port {\n\tstruct uart_port uport;\n\tconst struct tegra_uart_chip_data *cdata;\n\tstruct clk *uart_clk;\n\tstruct reset_control *rst;\n\tunsigned int current_baud;\n\tlong unsigned int fcr_shadow;\n\tlong unsigned int mcr_shadow;\n\tlong unsigned int lcr_shadow;\n\tlong unsigned int ier_shadow;\n\tbool rts_active;\n\tint tx_in_progress;\n\tunsigned int tx_bytes;\n\tbool enable_modem_interrupt;\n\tbool rx_timeout;\n\tint rx_in_progress;\n\tint symb_bit;\n\tstruct dma_chan *rx_dma_chan;\n\tstruct dma_chan *tx_dma_chan;\n\tdma_addr_t rx_dma_buf_phys;\n\tdma_addr_t tx_dma_buf_phys;\n\tunsigned char *rx_dma_buf_virt;\n\tunsigned char *tx_dma_buf_virt;\n\tstruct dma_async_tx_descriptor *tx_dma_desc;\n\tstruct dma_async_tx_descriptor *rx_dma_desc;\n\tdma_cookie_t tx_cookie;\n\tdma_cookie_t rx_cookie;\n\tunsigned int tx_bytes_requested;\n\tunsigned int rx_bytes_requested;\n\tstruct tegra_baud_tolerance *baud_tolerance;\n\tint n_adjustable_baud_rates;\n\tint required_rate;\n\tint configured_rate;\n\tbool use_rx_pio;\n\tbool use_tx_pio;\n\tbool rx_dma_active;\n};\n\nstruct tegra_usb_soc_info;\n\nstruct tegra_usb {\n\tstruct ci_hdrc_platform_data data;\n\tstruct platform_device *dev;\n\tconst struct tegra_usb_soc_info *soc;\n\tstruct usb_phy *phy;\n\tstruct clk *clk;\n\tbool needs_double_reset;\n};\n\nstruct usb_charger_current {\n\tunsigned int sdp_min;\n\tunsigned int sdp_max;\n\tunsigned int dcp_min;\n\tunsigned int dcp_max;\n\tunsigned int cdp_min;\n\tunsigned int cdp_max;\n\tunsigned int aca_min;\n\tunsigned int aca_max;\n};\n\nstruct usb_phy_io_ops;\n\nstruct usb_phy {\n\tstruct device *dev;\n\tconst char *label;\n\tunsigned int flags;\n\tenum usb_phy_type type;\n\tenum usb_phy_events last_event;\n\tstruct usb_otg *otg;\n\tstruct device *io_dev;\n\tstruct usb_phy_io_ops *io_ops;\n\tvoid *io_priv;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *id_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct notifier_block type_nb;\n\tenum usb_charger_type chg_type;\n\tenum usb_charger_state chg_state;\n\tstruct usb_charger_current chg_cur;\n\tstruct work_struct chg_work;\n\tstruct atomic_notifier_head notifier;\n\tu16 port_status;\n\tu16 port_change;\n\tstruct list_head head;\n\tint (*init)(struct usb_phy *);\n\tvoid (*shutdown)(struct usb_phy *);\n\tint (*set_vbus)(struct usb_phy *, int);\n\tint (*set_power)(struct usb_phy *, unsigned int);\n\tint (*set_suspend)(struct usb_phy *, int);\n\tint (*set_wakeup)(struct usb_phy *, bool);\n\tint (*notify_connect)(struct usb_phy *, enum usb_device_speed);\n\tint (*notify_disconnect)(struct usb_phy *, enum usb_device_speed);\n\tenum usb_charger_type (*charger_detect)(struct usb_phy *);\n};\n\nstruct tegra_xtal_freq;\n\nstruct tegra_usb_phy {\n\tint irq;\n\tint instance;\n\tconst struct tegra_xtal_freq *freq;\n\tvoid *regs;\n\tvoid *pad_regs;\n\tstruct clk *clk;\n\tstruct clk *pll_u;\n\tstruct clk *pad_clk;\n\tstruct regulator *vbus;\n\tstruct regmap *pmc_regmap;\n\tenum usb_dr_mode mode;\n\tvoid *config;\n\tconst struct tegra_phy_soc_config *soc_config;\n\tstruct usb_phy *ulpi;\n\tstruct usb_phy u_phy;\n\tbool is_legacy_phy;\n\tenum usb_phy_interface phy_type;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *pad_rst;\n\tbool wakeup_enabled;\n\tbool pad_wakeup;\n\tbool powered_on;\n};\n\nstruct tegra_usb_soc_info {\n\tlong unsigned int flags;\n\tunsigned int txfifothresh;\n\tenum usb_dr_mode dr_mode;\n};\n\nstruct tegra_utmip_config {\n\tu8 hssync_start_delay;\n\tu8 elastic_limit;\n\tu8 idle_wait_delay;\n\tu8 term_range_adj;\n\tbool xcvr_setup_use_fuses;\n\tu8 xcvr_setup;\n\tu8 xcvr_lsfslew;\n\tu8 xcvr_lsrslew;\n\tu8 xcvr_hsslew;\n\tu8 hssquelch_level;\n\tu8 hsdiscon_level;\n};\n\nstruct tegra_wake_event {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int irq;\n\tstruct {\n\t\tunsigned int instance;\n\t\tunsigned int pin;\n\t} gpio;\n};\n\nstruct tegra_xtal_freq {\n\tunsigned int freq;\n\tu8 enable_delay;\n\tu8 stable_count;\n\tu8 active_delay;\n\tu8 utmi_xtal_freq_count;\n\tu16 hsic_xtal_freq_count;\n\tu16 debounce;\n};\n\nstruct tegra_xusb_padctl;\n\nstruct tegra_xusb_context {\n\tu32 *ipfs;\n\tu32 *fpci;\n};\n\nstruct tegra_xusb_soc;\n\nstruct tegra_xusb {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct usb_hcd *hcd;\n\tstruct mutex lock;\n\tint xhci_irq;\n\tint mbox_irq;\n\tint padctl_irq;\n\tint *wake_irqs;\n\tvoid *ipfs_base;\n\tvoid *fpci_base;\n\tvoid *bar2_base;\n\tstruct resource *bar2;\n\tconst struct tegra_xusb_soc *soc;\n\tstruct regulator_bulk_data *supplies;\n\tstruct tegra_xusb_padctl *padctl;\n\tstruct clk *host_clk;\n\tstruct clk *falcon_clk;\n\tstruct clk *ss_clk;\n\tstruct clk *ss_src_clk;\n\tstruct clk *hs_src_clk;\n\tstruct clk *fs_src_clk;\n\tstruct clk *pll_u_480m;\n\tstruct clk *clk_m;\n\tstruct clk *pll_e;\n\tstruct reset_control *host_rst;\n\tstruct reset_control *ss_rst;\n\tstruct device *genpd_dev_host;\n\tstruct device *genpd_dev_ss;\n\tbool use_genpd;\n\tstruct phy **phys;\n\tunsigned int num_phys;\n\tstruct usb_phy **usbphy;\n\tunsigned int num_usb_phys;\n\tint otg_usb2_port;\n\tint otg_usb3_port;\n\tbool host_mode;\n\tstruct notifier_block id_nb;\n\tstruct work_struct id_work;\n\tstruct {\n\t\tsize_t size;\n\t\tvoid *virt;\n\t\tdma_addr_t phys;\n\t} fw;\n\tbool suspended;\n\tstruct tegra_xusb_context context;\n\tu8 lp0_utmi_pad_mask;\n\tint num_wakes;\n};\n\nstruct tegra_xusb_context_soc {\n\tstruct {\n\t\tconst unsigned int *offsets;\n\t\tunsigned int num_offsets;\n\t} ipfs;\n\tstruct {\n\t\tconst unsigned int *offsets;\n\t\tunsigned int num_offsets;\n\t} fpci;\n};\n\nstruct tegra_xusb_fw_header {\n\t__le32 boot_loadaddr_in_imem;\n\t__le32 boot_codedfi_offset;\n\t__le32 boot_codetag;\n\t__le32 boot_codesize;\n\t__le32 phys_memaddr;\n\t__le16 reqphys_memsize;\n\t__le16 alloc_phys_memsize;\n\t__le32 rodata_img_offset;\n\t__le32 rodata_section_start;\n\t__le32 rodata_section_end;\n\t__le32 main_fnaddr;\n\t__le32 fwimg_cksum;\n\t__le32 fwimg_created_time;\n\t__le32 imem_resident_start;\n\t__le32 imem_resident_end;\n\t__le32 idirect_start;\n\t__le32 idirect_end;\n\t__le32 l2_imem_start;\n\t__le32 l2_imem_end;\n\t__le32 version_id;\n\tu8 init_ddirect;\n\tu8 reserved[3];\n\t__le32 phys_addr_log_buffer;\n\t__le32 total_log_entries;\n\t__le32 dequeue_ptr;\n\t__le32 dummy_var[2];\n\t__le32 fwimg_len;\n\tu8 magic[8];\n\t__le32 ss_low_power_entry_timeout;\n\tu8 num_hsic_port;\n\tu8 padding[139];\n};\n\nstruct tegra_xusb_lane_soc;\n\nstruct tegra_xusb_lane {\n\tconst struct tegra_xusb_lane_soc *soc;\n\tstruct tegra_xusb_pad *pad;\n\tstruct device_node *np;\n\tstruct list_head list;\n\tunsigned int function;\n\tunsigned int index;\n};\n\nstruct tegra_xusb_hsic_lane {\n\tstruct tegra_xusb_lane base;\n\tu32 strobe_trim;\n\tu32 rx_strobe_trim;\n\tu32 rx_data_trim;\n\tu32 tx_rtune_n;\n\tu32 tx_rtune_p;\n\tu32 tx_rslew_n;\n\tu32 tx_rslew_p;\n\tbool auto_term;\n};\n\nstruct tegra_xusb_pad_soc;\n\nstruct tegra_xusb_lane_ops;\n\nstruct tegra_xusb_pad {\n\tconst struct tegra_xusb_pad_soc *soc;\n\tstruct tegra_xusb_padctl *padctl;\n\tstruct phy_provider *provider;\n\tstruct phy **lanes;\n\tstruct device dev;\n\tconst struct tegra_xusb_lane_ops *ops;\n\tstruct list_head list;\n};\n\nstruct tegra_xusb_hsic_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct regulator *supply;\n\tstruct clk *clk;\n};\n\nstruct tegra_xusb_port_ops;\n\nstruct tegra_xusb_port {\n\tstruct tegra_xusb_padctl *padctl;\n\tstruct tegra_xusb_lane *lane;\n\tunsigned int index;\n\tstruct list_head list;\n\tstruct device dev;\n\tstruct usb_role_switch *usb_role_sw;\n\tstruct work_struct usb_phy_work;\n\tstruct usb_phy usb_phy;\n\tconst struct tegra_xusb_port_ops *ops;\n};\n\nstruct tegra_xusb_hsic_port {\n\tstruct tegra_xusb_port base;\n};\n\nstruct tegra_xusb_lane_map {\n\tunsigned int port;\n\tconst char *type;\n\tunsigned int index;\n\tconst char *func;\n};\n\nstruct tegra_xusb_lane_ops {\n\tstruct tegra_xusb_lane * (*probe)(struct tegra_xusb_pad *, struct device_node *, unsigned int);\n\tvoid (*remove)(struct tegra_xusb_lane *);\n\tvoid (*iddq_enable)(struct tegra_xusb_lane *);\n\tvoid (*iddq_disable)(struct tegra_xusb_lane *);\n\tint (*enable_phy_sleepwalk)(struct tegra_xusb_lane *, enum usb_device_speed);\n\tint (*disable_phy_sleepwalk)(struct tegra_xusb_lane *);\n\tint (*enable_phy_wake)(struct tegra_xusb_lane *);\n\tint (*disable_phy_wake)(struct tegra_xusb_lane *);\n\tbool (*remote_wake_detected)(struct tegra_xusb_lane *);\n};\n\nstruct tegra_xusb_lane_soc {\n\tconst char *name;\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int mask;\n\tconst char * const *funcs;\n\tunsigned int num_funcs;\n\tstruct {\n\t\tunsigned int misc_ctl2;\n\t} regs;\n};\n\nstruct tegra_xusb_mbox_msg {\n\tu32 cmd;\n\tu32 data;\n};\n\nstruct tegra_xusb_mbox_regs {\n\tu16 cmd;\n\tu16 data_in;\n\tu16 data_out;\n\tu16 owner;\n\tu16 smi_intr;\n};\n\nstruct tegra_xusb_pad_ops {\n\tstruct tegra_xusb_pad * (*probe)(struct tegra_xusb_padctl *, const struct tegra_xusb_pad_soc *, struct device_node *);\n\tvoid (*remove)(struct tegra_xusb_pad *);\n};\n\nstruct tegra_xusb_pad_soc {\n\tconst char *name;\n\tconst struct tegra_xusb_lane_soc *lanes;\n\tunsigned int num_lanes;\n\tconst struct tegra_xusb_pad_ops *ops;\n};\n\nstruct tegra_xusb_padctl_soc___2;\n\nstruct tegra_xusb_padctl___2 {\n\tstruct device *dev;\n\tvoid *regs;\n\tstruct mutex lock;\n\tstruct reset_control *rst;\n\tconst struct tegra_xusb_padctl_soc___2 *soc;\n\tstruct pinctrl_dev *pinctrl;\n\tstruct pinctrl_desc desc;\n\tstruct phy_provider *provider;\n\tstruct phy *phys[2];\n\tunsigned int enable;\n};\n\nstruct tegra_xusb_padctl_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct tegra_xusb_padctl_lane {\n\tconst char *name;\n\tunsigned int offset;\n\tunsigned int shift;\n\tunsigned int mask;\n\tunsigned int iddq;\n\tconst unsigned int *funcs;\n\tunsigned int num_funcs;\n};\n\nstruct tegra_xusb_padctl_ops {\n\tstruct tegra_xusb_padctl * (*probe)(struct device *, const struct tegra_xusb_padctl_soc *);\n\tvoid (*remove)(struct tegra_xusb_padctl *);\n\tint (*suspend_noirq)(struct tegra_xusb_padctl *);\n\tint (*resume_noirq)(struct tegra_xusb_padctl *);\n\tint (*usb3_save_context)(struct tegra_xusb_padctl *, unsigned int);\n\tint (*hsic_set_idle)(struct tegra_xusb_padctl *, unsigned int, bool);\n\tint (*usb3_set_lfps_detect)(struct tegra_xusb_padctl *, unsigned int, bool);\n\tint (*vbus_override)(struct tegra_xusb_padctl *, bool);\n\tint (*utmi_port_reset)(struct phy *);\n\tvoid (*utmi_pad_power_on)(struct phy *);\n\tvoid (*utmi_pad_power_down)(struct phy *);\n};\n\nstruct tegra_xusb_padctl_property {\n\tconst char *name;\n\tenum tegra_xusb_padctl_param param;\n};\n\nstruct tegra_xusb_padctl_soc {\n\tconst struct tegra_xusb_pad_soc * const *pads;\n\tunsigned int num_pads;\n\tstruct {\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} usb2;\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} ulpi;\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} hsic;\n\t\tstruct {\n\t\t\tconst struct tegra_xusb_port_ops *ops;\n\t\t\tunsigned int count;\n\t\t} usb3;\n\t} ports;\n\tconst struct tegra_xusb_padctl_ops *ops;\n\tconst char * const *supply_names;\n\tunsigned int num_supplies;\n\tbool supports_gen2;\n\tbool need_fake_usb3_port;\n\tbool poll_trk_completed;\n\tbool trk_hw_mode;\n\tbool trk_update_on_idle;\n\tbool supports_lp_cfg_en;\n};\n\nstruct tegra_xusb_padctl_soc___2 {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int num_pins;\n\tconst struct tegra_xusb_padctl_function *functions;\n\tunsigned int num_functions;\n\tconst struct tegra_xusb_padctl_lane *lanes;\n\tunsigned int num_lanes;\n};\n\nstruct tegra_xusb_pcie_lane {\n\tstruct tegra_xusb_lane base;\n};\n\nstruct tegra_xusb_pcie_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct reset_control *rst;\n\tstruct clk *pll;\n\tbool enable;\n};\n\nstruct tegra_xusb_phy_type {\n\tconst char *name;\n\tunsigned int num;\n};\n\nstruct tegra_xusb_port_ops {\n\tvoid (*release)(struct tegra_xusb_port *);\n\tvoid (*remove)(struct tegra_xusb_port *);\n\tint (*enable)(struct tegra_xusb_port *);\n\tvoid (*disable)(struct tegra_xusb_port *);\n\tstruct tegra_xusb_lane * (*map)(struct tegra_xusb_port *);\n};\n\nstruct tegra_xusb_sata_lane {\n\tstruct tegra_xusb_lane base;\n};\n\nstruct tegra_xusb_sata_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct reset_control *rst;\n\tstruct clk *pll;\n\tbool enable;\n};\n\nstruct tegra_xusb_soc_ops;\n\nstruct tegra_xusb_soc {\n\tconst char *firmware;\n\tconst char * const *supply_names;\n\tunsigned int num_supplies;\n\tconst struct tegra_xusb_phy_type *phy_types;\n\tunsigned int num_types;\n\tunsigned int max_num_wakes;\n\tconst struct tegra_xusb_context_soc *context;\n\tstruct {\n\t\tstruct {\n\t\t\tunsigned int offset;\n\t\t\tunsigned int count;\n\t\t} usb2;\n\t\tstruct {\n\t\t\tunsigned int offset;\n\t\t\tunsigned int count;\n\t\t} ulpi;\n\t\tstruct {\n\t\t\tunsigned int offset;\n\t\t\tunsigned int count;\n\t\t} hsic;\n\t\tstruct {\n\t\t\tunsigned int offset;\n\t\t\tunsigned int count;\n\t\t} usb3;\n\t} ports;\n\tstruct tegra_xusb_mbox_regs mbox;\n\tconst struct tegra_xusb_soc_ops *ops;\n\tbool scale_ss_clock;\n\tbool has_ipfs;\n\tbool lpm_support;\n\tbool otg_reset_sspi;\n\tbool has_bar2;\n};\n\nstruct tegra_xusb_soc_ops {\n\tu32 (*mbox_reg_readl)(struct tegra_xusb *, unsigned int);\n\tvoid (*mbox_reg_writel)(struct tegra_xusb *, u32, unsigned int);\n\tu32 (*csb_reg_readl)(struct tegra_xusb *, unsigned int);\n\tvoid (*csb_reg_writel)(struct tegra_xusb *, u32, unsigned int);\n};\n\nstruct tegra_xusb_ulpi_lane {\n\tstruct tegra_xusb_lane base;\n};\n\nstruct tegra_xusb_ulpi_pad {\n\tstruct tegra_xusb_pad base;\n};\n\nstruct tegra_xusb_ulpi_port {\n\tstruct tegra_xusb_port base;\n\tstruct regulator *supply;\n\tbool internal;\n};\n\nstruct tegra_xusb_usb2_lane {\n\tstruct tegra_xusb_lane base;\n\tu32 hs_curr_level_offset;\n};\n\nstruct tegra_xusb_usb2_pad {\n\tstruct tegra_xusb_pad base;\n\tstruct clk *clk;\n\tunsigned int enable;\n\tstruct mutex lock;\n};\n\nstruct tegra_xusb_usb2_port {\n\tstruct tegra_xusb_port base;\n\tstruct regulator *supply;\n\tenum usb_dr_mode mode;\n\tbool internal;\n\tint usb3_port_fake;\n};\n\nstruct tegra_xusb_usb3_lane {\n\tstruct tegra_xusb_lane base;\n};\n\nstruct tegra_xusb_usb3_pad {\n\tstruct tegra_xusb_pad base;\n\tunsigned int enable;\n\tstruct mutex lock;\n};\n\nstruct tegra_xusb_usb3_port {\n\tstruct tegra_xusb_port base;\n\tbool context_saved;\n\tunsigned int port;\n\tbool internal;\n\tbool disable_gen2;\n\tu32 tap1;\n\tu32 amp;\n\tu32 ctle_z;\n\tu32 ctle_g;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[8];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct tgec_cfg {\n\tbool pause_ignore;\n\tbool promiscuous_mode_enable;\n\tu16 max_frame_length;\n\tu16 pause_quant;\n\tu32 tx_ipg_length;\n};\n\nstruct tgec_mdio_controller {\n\t__be32 reserved[12];\n\t__be32 mdio_stat;\n\t__be32 mdio_ctl;\n\t__be32 mdio_data;\n\t__be32 mdio_addr;\n};\n\nstruct tgec_regs {\n\tu32 tgec_id;\n\tu32 reserved001[1];\n\tu32 command_config;\n\tu32 mac_addr_0;\n\tu32 mac_addr_1;\n\tu32 maxfrm;\n\tu32 pause_quant;\n\tu32 rx_fifo_sections;\n\tu32 tx_fifo_sections;\n\tu32 rx_fifo_almost_f_e;\n\tu32 tx_fifo_almost_f_e;\n\tu32 hashtable_ctrl;\n\tu32 mdio_cfg_status;\n\tu32 mdio_command;\n\tu32 mdio_data;\n\tu32 mdio_regaddr;\n\tu32 status;\n\tu32 tx_ipg_len;\n\tu32 mac_addr_2;\n\tu32 mac_addr_3;\n\tu32 rx_fifo_ptr_rd;\n\tu32 rx_fifo_ptr_wr;\n\tu32 tx_fifo_ptr_rd;\n\tu32 tx_fifo_ptr_wr;\n\tu32 imask;\n\tu32 ievent;\n\tu32 udp_port;\n\tu32 type_1588v2;\n\tu32 reserved070[4];\n\tu32 tfrm_u;\n\tu32 tfrm_l;\n\tu32 rfrm_u;\n\tu32 rfrm_l;\n\tu32 rfcs_u;\n\tu32 rfcs_l;\n\tu32 raln_u;\n\tu32 raln_l;\n\tu32 txpf_u;\n\tu32 txpf_l;\n\tu32 rxpf_u;\n\tu32 rxpf_l;\n\tu32 rlong_u;\n\tu32 rlong_l;\n\tu32 rflr_u;\n\tu32 rflr_l;\n\tu32 tvlan_u;\n\tu32 tvlan_l;\n\tu32 rvlan_u;\n\tu32 rvlan_l;\n\tu32 toct_u;\n\tu32 toct_l;\n\tu32 roct_u;\n\tu32 roct_l;\n\tu32 ruca_u;\n\tu32 ruca_l;\n\tu32 rmca_u;\n\tu32 rmca_l;\n\tu32 rbca_u;\n\tu32 rbca_l;\n\tu32 terr_u;\n\tu32 terr_l;\n\tu32 reserved100[2];\n\tu32 tuca_u;\n\tu32 tuca_l;\n\tu32 tmca_u;\n\tu32 tmca_l;\n\tu32 tbca_u;\n\tu32 tbca_l;\n\tu32 rdrp_u;\n\tu32 rdrp_l;\n\tu32 reoct_u;\n\tu32 reoct_l;\n\tu32 rpkt_u;\n\tu32 rpkt_l;\n\tu32 trund_u;\n\tu32 trund_l;\n\tu32 r64_u;\n\tu32 r64_l;\n\tu32 r127_u;\n\tu32 r127_l;\n\tu32 r255_u;\n\tu32 r255_l;\n\tu32 r511_u;\n\tu32 r511_l;\n\tu32 r1023_u;\n\tu32 r1023_l;\n\tu32 r1518_u;\n\tu32 r1518_l;\n\tu32 r1519x_u;\n\tu32 r1519x_l;\n\tu32 trovr_u;\n\tu32 trovr_l;\n\tu32 trjbr_u;\n\tu32 trjbr_l;\n\tu32 trfrg_u;\n\tu32 trfrg_l;\n\tu32 rerr_u;\n\tu32 rerr_l;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct tgs_gcl_data {\n\t__le32 btl;\n\t__le32 bth;\n\t__le32 ct;\n\t__le32 cte;\n\tstruct gce entry[0];\n};\n\nstruct thermal_attr {\n\tstruct device_attribute attr;\n\tchar name[20];\n};\n\ntypedef struct thermal_cooling_device *class_cooling_dev_t;\n\nstruct thermal_cooling_device {\n\tint id;\n\tconst char *type;\n\tlong unsigned int max_state;\n\tstruct device device;\n\tstruct device_node *np;\n\tvoid *devdata;\n\tvoid *stats;\n\tconst struct thermal_cooling_device_ops *ops;\n\tbool updated;\n\tstruct mutex lock;\n\tstruct list_head thermal_instances;\n\tstruct list_head node;\n};\n\nstruct thermal_governor {\n\tconst char *name;\n\tint (*bind_to_tz)(struct thermal_zone_device *);\n\tvoid (*unbind_from_tz)(struct thermal_zone_device *);\n\tvoid (*trip_crossed)(struct thermal_zone_device *, const struct thermal_trip *, bool);\n\tvoid (*manage)(struct thermal_zone_device *);\n\tvoid (*update_tz)(struct thermal_zone_device *, enum thermal_notify_event);\n\tstruct list_head governor_list;\n};\n\nstruct thermal_hwmon_attr {\n\tstruct device_attribute attr;\n\tchar name[16];\n};\n\nstruct thermal_hwmon_device {\n\tchar type[20];\n\tstruct device *device;\n\tint count;\n\tstruct list_head tz_list;\n\tstruct list_head node;\n};\n\nstruct thermal_hwmon_temp {\n\tstruct list_head hwmon_node;\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_hwmon_attr temp_input;\n\tstruct thermal_hwmon_attr temp_crit;\n};\n\nstruct thermal_instance {\n\tint id;\n\tchar name[20];\n\tstruct thermal_cooling_device *cdev;\n\tconst struct thermal_trip *trip;\n\tbool initialized;\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tlong unsigned int target;\n\tchar attr_name[20];\n\tstruct device_attribute attr;\n\tchar weight_attr_name[20];\n\tstruct device_attribute weight_attr;\n\tstruct list_head trip_node;\n\tstruct list_head cdev_node;\n\tunsigned int weight;\n\tbool upper_no_limit;\n};\n\nstruct thermal_trip {\n\tint temperature;\n\tint hysteresis;\n\tenum thermal_trip_type type;\n\tu8 flags;\n\tvoid *priv;\n};\n\nstruct thermal_trip_attrs {\n\tstruct thermal_attr type;\n\tstruct thermal_attr temp;\n\tstruct thermal_attr hyst;\n};\n\nstruct thermal_trip_desc {\n\tstruct thermal_trip trip;\n\tstruct thermal_trip_attrs trip_attrs;\n\tstruct list_head list_node;\n\tstruct list_head thermal_instances;\n\tint threshold;\n};\n\ntypedef struct thermal_zone_device *class_thermal_zone_reverse_t;\n\ntypedef struct thermal_zone_device *class_thermal_zone_t;\n\nstruct thermal_zone_params;\n\nstruct thermal_zone_device {\n\tint id;\n\tchar type[20];\n\tstruct device device;\n\tstruct completion removal;\n\tstruct completion resume;\n\tstruct attribute_group trips_attribute_group;\n\tstruct list_head trips_high;\n\tstruct list_head trips_reached;\n\tstruct list_head trips_invalid;\n\tenum thermal_device_mode mode;\n\tvoid *devdata;\n\tint num_trips;\n\tlong unsigned int passive_delay_jiffies;\n\tlong unsigned int polling_delay_jiffies;\n\tlong unsigned int recheck_delay_jiffies;\n\tint temperature;\n\tint last_temperature;\n\tint emul_temperature;\n\tint passive;\n\tint prev_low_trip;\n\tint prev_high_trip;\n\tstruct thermal_zone_device_ops ops;\n\tstruct thermal_zone_params *tzp;\n\tstruct thermal_governor *governor;\n\tvoid *governor_data;\n\tstruct ida ida;\n\tstruct mutex lock;\n\tstruct list_head node;\n\tstruct delayed_work poll_queue;\n\tenum thermal_notify_event notify_event;\n\tu8 state;\n\tstruct list_head user_thresholds;\n\tstruct thermal_trip_desc trips[0];\n};\n\nstruct thermal_zone_params {\n\tconst char *governor_name;\n\tbool no_hwmon;\n\tu32 sustainable_power;\n\ts32 k_po;\n\ts32 k_pu;\n\ts32 k_i;\n\ts32 k_d;\n\ts32 integral_cutoff;\n\tint slope;\n\tint offset;\n};\n\nstruct thpsize {\n\tstruct kobject kobj;\n\tstruct list_head node;\n\tint order;\n};\n\nstruct thread_deferred_req {\n\tstruct cache_deferred_req handle;\n\tstruct completion completion;\n};\n\nstruct ths_device;\n\nstruct tsensor {\n\tstruct ths_device *tmdev;\n\tstruct thermal_zone_device *tzd;\n\tint id;\n};\n\nstruct ths_thermal_chip;\n\nstruct ths_device {\n\tconst struct ths_thermal_chip *chip;\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct regmap_field *sram_regmap_field;\n\tstruct reset_control *reset;\n\tstruct clk *bus_clk;\n\tstruct clk *mod_clk;\n\tstruct tsensor sensor[4];\n};\n\nstruct ths_thermal_chip {\n\tbool has_mod_clk;\n\tbool has_bus_clk_reset;\n\tbool needs_sram;\n\tint sensor_num;\n\tint offset;\n\tint scale;\n\tint ft_deviation;\n\tint temp_data_base;\n\tint (*calibrate)(struct ths_device *, u16 *, int);\n\tint (*init)(struct ths_device *);\n\tlong unsigned int (*irq_ack)(struct ths_device *);\n\tint (*calc_temp)(struct ths_device *, int, int);\n};\n\nstruct thunder_mdiobus_nexus {\n\tvoid *bar0;\n\tstruct cavium_mdiobus *buses[4];\n};\n\nstruct thunder_pem_pci {\n\tu32 ea_entry[3];\n\tvoid *pem_reg_base;\n};\n\nstruct ti_cpufreq_soc_data;\n\nstruct ti_cpufreq_data {\n\tstruct device *cpu_dev;\n\tstruct device_node *opp_node;\n\tstruct regmap *syscon;\n\tconst struct ti_cpufreq_soc_data *soc_data;\n};\n\nstruct ti_cpufreq_soc_data {\n\tconst char * const *reg_names;\n\tlong unsigned int (*efuse_xlate)(struct ti_cpufreq_data *, long unsigned int);\n\tlong unsigned int efuse_fallback;\n\tlong unsigned int efuse_offset;\n\tlong unsigned int efuse_mask;\n\tlong unsigned int efuse_shift;\n\tlong unsigned int rev_offset;\n\tbool multi_regulator;\n\tu8 quirks;\n};\n\nstruct ti_msgmgr_valid_queue_desc;\n\nstruct ti_msgmgr_desc {\n\tu8 queue_count;\n\tu8 max_message_size;\n\tu8 max_messages;\n\tu8 data_first_reg;\n\tu8 data_last_reg;\n\tu32 status_cnt_mask;\n\tu32 status_err_mask;\n\tbool tx_polled;\n\tint tx_poll_timeout_ms;\n\tconst struct ti_msgmgr_valid_queue_desc *valid_queues;\n\tconst char *data_region_name;\n\tconst char *status_region_name;\n\tconst char *ctrl_region_name;\n\tint num_valid_queues;\n\tbool is_sproxy;\n};\n\nstruct ti_queue_inst;\n\nstruct ti_msgmgr_inst {\n\tstruct device *dev;\n\tconst struct ti_msgmgr_desc *desc;\n\tvoid *queue_proxy_region;\n\tvoid *queue_state_debug_region;\n\tvoid *queue_ctrl_region;\n\tu8 num_valid_queues;\n\tstruct ti_queue_inst *qinsts;\n\tstruct mbox_controller mbox;\n\tstruct mbox_chan *chans;\n};\n\nstruct ti_msgmgr_message {\n\tsize_t len;\n\tu8 *buf;\n\tstruct mbox_chan *chan_rx;\n\tint timeout_rx_ms;\n};\n\nstruct ti_msgmgr_valid_queue_desc {\n\tu8 queue_id;\n\tu8 proxy_id;\n\tbool is_tx;\n};\n\nstruct ti_opp_supply_optimum_voltage_table;\n\nstruct ti_opp_supply_data {\n\tstruct ti_opp_supply_optimum_voltage_table *vdd_table;\n\tu32 num_vdd_table;\n\tu32 vdd_absolute_max_voltage_uv;\n\tstruct dev_pm_opp_supply old_supplies[2];\n\tstruct dev_pm_opp_supply new_supplies[2];\n};\n\nstruct ti_opp_supply_of_data {\n\tconst u8 flags;\n\tconst u32 efuse_voltage_mask;\n\tconst bool efuse_voltage_uv;\n};\n\nstruct ti_opp_supply_optimum_voltage_table {\n\tunsigned int reference_uv;\n\tunsigned int optimized_uv;\n};\n\nstruct ti_queue_inst {\n\tchar name[30];\n\tu8 queue_id;\n\tu8 proxy_id;\n\tint irq;\n\tbool is_tx;\n\tvoid *queue_buff_start;\n\tvoid *queue_buff_end;\n\tvoid *queue_state;\n\tvoid *queue_ctrl;\n\tstruct mbox_chan *chan;\n\tu32 *rx_buff;\n\tbool polled_rx_mode;\n};\n\nstruct ti_sci_clk_ops {\n\tint (*get_clock)(const struct ti_sci_handle *, u32, u32, bool, bool, bool);\n\tint (*idle_clock)(const struct ti_sci_handle *, u32, u32);\n\tint (*put_clock)(const struct ti_sci_handle *, u32, u32);\n\tint (*is_auto)(const struct ti_sci_handle *, u32, u32, bool *);\n\tint (*is_on)(const struct ti_sci_handle *, u32, u32, bool *, bool *);\n\tint (*is_off)(const struct ti_sci_handle *, u32, u32, bool *, bool *);\n\tint (*set_parent)(const struct ti_sci_handle *, u32, u32, u32);\n\tint (*get_parent)(const struct ti_sci_handle *, u32, u32, u32 *);\n\tint (*get_num_parents)(const struct ti_sci_handle *, u32, u32, u32 *);\n\tint (*get_best_match_freq)(const struct ti_sci_handle *, u32, u32, u64, u64, u64, u64 *);\n\tint (*set_freq)(const struct ti_sci_handle *, u32, u32, u64, u64, u64);\n\tint (*get_freq)(const struct ti_sci_handle *, u32, u32, u64 *);\n};\n\nstruct ti_sci_core_ops {\n\tint (*reboot_device)(const struct ti_sci_handle *);\n};\n\nstruct ti_sci_desc {\n\tu8 default_host_id;\n\tint max_rx_timeout_ms;\n\tint max_msgs;\n\tint max_msg_size;\n};\n\nstruct ti_sci_dev_ops {\n\tint (*get_device)(const struct ti_sci_handle *, u32);\n\tint (*get_device_exclusive)(const struct ti_sci_handle *, u32);\n\tint (*idle_device)(const struct ti_sci_handle *, u32);\n\tint (*idle_device_exclusive)(const struct ti_sci_handle *, u32);\n\tint (*put_device)(const struct ti_sci_handle *, u32);\n\tint (*is_valid)(const struct ti_sci_handle *, u32);\n\tint (*get_context_loss_count)(const struct ti_sci_handle *, u32, u32 *);\n\tint (*is_idle)(const struct ti_sci_handle *, u32, bool *);\n\tint (*is_stop)(const struct ti_sci_handle *, u32, bool *, bool *);\n\tint (*is_on)(const struct ti_sci_handle *, u32, bool *, bool *);\n\tint (*is_transitioning)(const struct ti_sci_handle *, u32, bool *);\n\tint (*set_device_resets)(const struct ti_sci_handle *, u32, u32);\n\tint (*get_device_resets)(const struct ti_sci_handle *, u32, u32 *);\n};\n\nstruct ti_sci_genpd_provider {\n\tconst struct ti_sci_handle *ti_sci;\n\tstruct device *dev;\n\tstruct list_head pd_list;\n\tstruct genpd_onecell_data data;\n};\n\nstruct ti_sci_version_info {\n\tu8 abi_major;\n\tu8 abi_minor;\n\tu16 firmware_revision;\n\tchar firmware_description[32];\n};\n\nstruct ti_sci_pm_ops {\n\tint (*lpm_wake_reason)(const struct ti_sci_handle *, u32 *, u64 *, u8 *, u8 *);\n\tint (*set_device_constraint)(const struct ti_sci_handle *, u32, u8);\n\tint (*set_latency_constraint)(const struct ti_sci_handle *, u16, u8);\n};\n\nstruct ti_sci_resource_desc;\n\nstruct ti_sci_rm_core_ops {\n\tint (*get_range)(const struct ti_sci_handle *, u32, u8, struct ti_sci_resource_desc *);\n\tint (*get_range_from_shost)(const struct ti_sci_handle *, u32, u8, u8, struct ti_sci_resource_desc *);\n};\n\nstruct ti_sci_rm_irq_ops {\n\tint (*set_irq)(const struct ti_sci_handle *, u16, u16, u16, u16);\n\tint (*set_event_map)(const struct ti_sci_handle *, u16, u16, u16, u16, u16, u8);\n\tint (*free_irq)(const struct ti_sci_handle *, u16, u16, u16, u16);\n\tint (*free_event_map)(const struct ti_sci_handle *, u16, u16, u16, u16, u16, u8);\n};\n\nstruct ti_sci_msg_rm_ring_cfg;\n\nstruct ti_sci_rm_ringacc_ops {\n\tint (*set_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_ring_cfg *);\n};\n\nstruct ti_sci_rm_psil_ops {\n\tint (*pair)(const struct ti_sci_handle *, u32, u32, u32);\n\tint (*unpair)(const struct ti_sci_handle *, u32, u32, u32);\n};\n\nstruct ti_sci_msg_rm_udmap_tx_ch_cfg;\n\nstruct ti_sci_msg_rm_udmap_rx_ch_cfg;\n\nstruct ti_sci_msg_rm_udmap_flow_cfg;\n\nstruct ti_sci_rm_udmap_ops {\n\tint (*tx_ch_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_udmap_tx_ch_cfg *);\n\tint (*rx_ch_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_udmap_rx_ch_cfg *);\n\tint (*rx_flow_cfg)(const struct ti_sci_handle *, const struct ti_sci_msg_rm_udmap_flow_cfg *);\n};\n\nstruct ti_sci_proc_ops {\n\tint (*request)(const struct ti_sci_handle *, u8);\n\tint (*release)(const struct ti_sci_handle *, u8);\n\tint (*handover)(const struct ti_sci_handle *, u8, u8);\n\tint (*set_config)(const struct ti_sci_handle *, u8, u64, u32, u32);\n\tint (*set_control)(const struct ti_sci_handle *, u8, u32, u32);\n\tint (*get_status)(const struct ti_sci_handle *, u8, u64 *, u32 *, u32 *, u32 *);\n};\n\nstruct ti_sci_ops {\n\tstruct ti_sci_core_ops core_ops;\n\tstruct ti_sci_dev_ops dev_ops;\n\tstruct ti_sci_clk_ops clk_ops;\n\tstruct ti_sci_pm_ops pm_ops;\n\tstruct ti_sci_rm_core_ops rm_core_ops;\n\tstruct ti_sci_rm_irq_ops rm_irq_ops;\n\tstruct ti_sci_rm_ringacc_ops rm_ring_ops;\n\tstruct ti_sci_rm_psil_ops rm_psil_ops;\n\tstruct ti_sci_rm_udmap_ops rm_udmap_ops;\n\tstruct ti_sci_proc_ops proc_ops;\n};\n\nstruct ti_sci_handle {\n\tstruct ti_sci_version_info version;\n\tstruct ti_sci_ops ops;\n};\n\nstruct ti_sci_xfer;\n\nstruct ti_sci_xfers_info {\n\tstruct semaphore sem_xfer_count;\n\tstruct ti_sci_xfer *xfer_block;\n\tlong unsigned int *xfer_alloc_table;\n\tspinlock_t xfer_lock;\n};\n\nstruct ti_sci_info {\n\tstruct device *dev;\n\tconst struct ti_sci_desc *desc;\n\tstruct dentry *d;\n\tvoid *debug_region;\n\tchar *debug_buffer;\n\tsize_t debug_region_size;\n\tstruct ti_sci_handle handle;\n\tstruct mbox_client cl;\n\tstruct mbox_chan *chan_tx;\n\tstruct mbox_chan *chan_rx;\n\tstruct ti_sci_xfers_info minfo;\n\tstruct list_head node;\n\tu8 host_id;\n\tu64 fw_caps;\n\tint users;\n};\n\nstruct ti_sci_inta_event_desc {\n\tu16 global_event;\n\tu32 hwirq;\n\tu8 vint_bit;\n};\n\nstruct ti_sci_inta_irq_domain {\n\tconst struct ti_sci_handle *sci;\n\tstruct ti_sci_resource *vint;\n\tstruct ti_sci_resource *global_event;\n\tstruct list_head vint_list;\n\tstruct mutex vint_mutex;\n\tvoid *base;\n\tstruct platform_device *pdev;\n\tu32 ti_sci_id;\n\tint unmapped_cnt;\n\tu16 *unmapped_dev_ids;\n};\n\nstruct ti_sci_inta_vint_desc {\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tlong unsigned int event_map[1];\n\tstruct ti_sci_inta_event_desc events[64];\n\tunsigned int parent_virq;\n\tu16 vint_id;\n};\n\nstruct ti_sci_intr_irq_domain {\n\tconst struct ti_sci_handle *sci;\n\tstruct ti_sci_resource *out_irqs;\n\tstruct device *dev;\n\tu32 ti_sci_id;\n\tu32 type;\n};\n\nstruct ti_sci_msg_hdr {\n\tu16 type;\n\tu8 host;\n\tu8 seq;\n\tu32 flags;\n};\n\nstruct ti_sci_msg_psil_pair {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 nav_id;\n\tu32 src_thread;\n\tu32 dst_thread;\n};\n\nstruct ti_sci_msg_psil_unpair {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 nav_id;\n\tu32 src_thread;\n\tu32 dst_thread;\n};\n\nstruct ti_sci_msg_req_get_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_clock_num_parents {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_clock_parent {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_clock_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_get_device_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n};\n\nstruct ti_sci_msg_req_get_resource_range {\n\tstruct ti_sci_msg_hdr hdr;\n\tu16 type;\n\tu8 subtype;\n\tu8 secondary_host;\n};\n\nstruct ti_sci_msg_req_get_status {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_lpm_set_device_constraint {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n\tu8 state;\n\tu32 rsvd[2];\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_lpm_set_latency_constraint {\n\tstruct ti_sci_msg_hdr hdr;\n\tu16 latency;\n\tu8 state;\n\tu32 rsvd;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_manage_irq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 src_id;\n\tu16 src_index;\n\tu16 dst_id;\n\tu16 dst_host_irq;\n\tu16 ia_id;\n\tu16 vint;\n\tu16 global_event;\n\tu8 vint_status_bit;\n\tu8 secondary_host;\n};\n\nstruct ti_sci_msg_req_prepare_sleep {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 mode;\n\tu32 ctx_lo;\n\tu32 ctx_hi;\n\tu32 debug_flags;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_proc_handover {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu8 host_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_proc_release {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_proc_request {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_query_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu64 min_freq_hz;\n\tu64 target_freq_hz;\n\tu64 max_freq_hz;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_reboot {\n\tstruct ti_sci_msg_hdr hdr;\n};\n\nstruct ti_sci_msg_req_set_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu64 min_freq_hz;\n\tu64 target_freq_hz;\n\tu64 max_freq_hz;\n\tu8 clk_id;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_clock_parent {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu8 parent_id;\n\tu32 clk_id_32;\n\tu32 parent_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_clock_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 dev_id;\n\tu8 clk_id;\n\tu8 request_state;\n\tu32 clk_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_config {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu32 bootvector_low;\n\tu32 bootvector_high;\n\tu32 config_flags_set;\n\tu32 config_flags_clear;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_ctrl {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu32 control_flags_set;\n\tu32 control_flags_clear;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_device_resets {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n\tu32 resets;\n};\n\nstruct ti_sci_msg_req_set_device_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 id;\n\tu32 reserved;\n\tu8 state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_req_set_io_isolation {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu64 freq_hz;\n};\n\nstruct ti_sci_msg_resp_get_clock_num_parents {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 num_parents;\n\tu32 num_parents_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_clock_parent {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 parent_id;\n\tu32 parent_id_32;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_clock_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 programmed_state;\n\tu8 current_state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_device_state {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 context_loss_count;\n\tu32 resets;\n\tu8 programmed_state;\n\tu8 current_state;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_get_resource_range {\n\tstruct ti_sci_msg_hdr hdr;\n\tu16 range_start;\n\tu16 range_num;\n\tu16 range_start_sec;\n\tu16 range_num_sec;\n};\n\nstruct ti_sci_msg_resp_get_status {\n\tstruct ti_sci_msg_hdr hdr;\n\tu8 processor_id;\n\tu32 bootvector_low;\n\tu32 bootvector_high;\n\tu32 config_flags;\n\tu32 control_flags;\n\tu32 status_flags;\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_lpm_wake_reason {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 wake_source;\n\tu64 wake_timestamp;\n\tu8 wake_pin;\n\tu8 mode;\n\tu32 rsvd[2];\n} __attribute__((packed));\n\nstruct ti_sci_msg_resp_query_clock_freq {\n\tstruct ti_sci_msg_hdr hdr;\n\tu64 freq_hz;\n};\n\nstruct ti_sci_msg_resp_query_fw_caps {\n\tstruct ti_sci_msg_hdr hdr;\n\tu64 fw_caps;\n};\n\nstruct ti_sci_msg_resp_version {\n\tstruct ti_sci_msg_hdr hdr;\n\tchar firmware_description[32];\n\tu16 firmware_revision;\n\tu8 abi_major;\n\tu8 abi_minor;\n};\n\nstruct ti_sci_msg_rm_ring_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu32 addr_lo;\n\tu32 addr_hi;\n\tu32 count;\n\tu8 mode;\n\tu8 size;\n\tu8 order_id;\n\tu16 virtid;\n\tu8 asel;\n};\n\nstruct ti_sci_msg_rm_ring_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu32 addr_lo;\n\tu32 addr_hi;\n\tu32 count;\n\tu8 mode;\n\tu8 size;\n\tu8 order_id;\n\tu16 virtid;\n\tu8 asel;\n} __attribute__((packed));\n\nstruct ti_sci_msg_rm_udmap_flow_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 flow_index;\n\tu8 rx_einfo_present;\n\tu8 rx_psinfo_present;\n\tu8 rx_error_handling;\n\tu8 rx_desc_type;\n\tu16 rx_sop_offset;\n\tu16 rx_dest_qnum;\n\tu8 rx_src_tag_hi;\n\tu8 rx_src_tag_lo;\n\tu8 rx_dest_tag_hi;\n\tu8 rx_dest_tag_lo;\n\tu8 rx_src_tag_hi_sel;\n\tu8 rx_src_tag_lo_sel;\n\tu8 rx_dest_tag_hi_sel;\n\tu8 rx_dest_tag_lo_sel;\n\tu16 rx_fdq0_sz0_qnum;\n\tu16 rx_fdq1_qnum;\n\tu16 rx_fdq2_qnum;\n\tu16 rx_fdq3_qnum;\n\tu8 rx_ps_location;\n};\n\nstruct ti_sci_msg_rm_udmap_flow_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 flow_index;\n\tu8 rx_einfo_present;\n\tu8 rx_psinfo_present;\n\tu8 rx_error_handling;\n\tu8 rx_desc_type;\n\tu16 rx_sop_offset;\n\tu16 rx_dest_qnum;\n\tu8 rx_src_tag_hi;\n\tu8 rx_src_tag_lo;\n\tu8 rx_dest_tag_hi;\n\tu8 rx_dest_tag_lo;\n\tu8 rx_src_tag_hi_sel;\n\tu8 rx_src_tag_lo_sel;\n\tu8 rx_dest_tag_hi_sel;\n\tu8 rx_dest_tag_lo_sel;\n\tu16 rx_fdq0_sz0_qnum;\n\tu16 rx_fdq1_qnum;\n\tu16 rx_fdq2_qnum;\n\tu16 rx_fdq3_qnum;\n\tu8 rx_ps_location;\n} __attribute__((packed));\n\nstruct ti_sci_msg_rm_udmap_rx_ch_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu16 rx_fetch_size;\n\tu16 rxcq_qnum;\n\tu8 rx_priority;\n\tu8 rx_qos;\n\tu8 rx_orderid;\n\tu8 rx_sched_priority;\n\tu16 flowid_start;\n\tu16 flowid_cnt;\n\tu8 rx_pause_on_err;\n\tu8 rx_atype;\n\tu8 rx_chan_type;\n\tu8 rx_ignore_short;\n\tu8 rx_ignore_long;\n\tu8 rx_burst_size;\n};\n\nstruct ti_sci_msg_rm_udmap_rx_ch_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu16 rx_fetch_size;\n\tu16 rxcq_qnum;\n\tu8 rx_priority;\n\tu8 rx_qos;\n\tu8 rx_orderid;\n\tu8 rx_sched_priority;\n\tu16 flowid_start;\n\tu16 flowid_cnt;\n\tu8 rx_pause_on_err;\n\tu8 rx_atype;\n\tu8 rx_chan_type;\n\tu8 rx_ignore_short;\n\tu8 rx_ignore_long;\n\tu8 rx_burst_size;\n} __attribute__((packed));\n\nstruct ti_sci_msg_rm_udmap_tx_ch_cfg {\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu8 tx_pause_on_err;\n\tu8 tx_filt_einfo;\n\tu8 tx_filt_pswords;\n\tu8 tx_atype;\n\tu8 tx_chan_type;\n\tu8 tx_supr_tdpkt;\n\tu16 tx_fetch_size;\n\tu8 tx_credit_count;\n\tu16 txcq_qnum;\n\tu8 tx_priority;\n\tu8 tx_qos;\n\tu8 tx_orderid;\n\tu16 fdepth;\n\tu8 tx_sched_priority;\n\tu8 tx_burst_size;\n\tu8 tx_tdtype;\n\tu8 extended_ch_type;\n};\n\nstruct ti_sci_msg_rm_udmap_tx_ch_cfg_req {\n\tstruct ti_sci_msg_hdr hdr;\n\tu32 valid_params;\n\tu16 nav_id;\n\tu16 index;\n\tu8 tx_pause_on_err;\n\tu8 tx_filt_einfo;\n\tu8 tx_filt_pswords;\n\tu8 tx_atype;\n\tu8 tx_chan_type;\n\tu8 tx_supr_tdpkt;\n\tu16 tx_fetch_size;\n\tu8 tx_credit_count;\n\tu16 txcq_qnum;\n\tu8 tx_priority;\n\tu8 tx_qos;\n\tu8 tx_orderid;\n\tu16 fdepth;\n\tu8 tx_sched_priority;\n\tu8 tx_burst_size;\n\tu8 tx_tdtype;\n\tu8 extended_ch_type;\n} __attribute__((packed));\n\nstruct ti_sci_pm_domain {\n\tint idx;\n\tu8 exclusive;\n\tstruct generic_pm_domain pd;\n\tstruct list_head node;\n\tstruct ti_sci_genpd_provider *parent;\n};\n\nstruct ti_sci_reset_control {\n\tu32 dev_id;\n\tu32 reset_mask;\n\tstruct mutex lock;\n};\n\nstruct ti_sci_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tstruct device *dev;\n\tconst struct ti_sci_handle *sci;\n\tstruct idr idr;\n};\n\nstruct ti_sci_resource {\n\tu16 sets;\n\traw_spinlock_t lock;\n\tstruct ti_sci_resource_desc *desc;\n};\n\nstruct ti_sci_resource_desc {\n\tu16 start;\n\tu16 num;\n\tu16 start_sec;\n\tu16 num_sec;\n\tlong unsigned int *res_map;\n};\n\nstruct ti_sci_xfer {\n\tstruct ti_msgmgr_message tx_message;\n\tu8 rx_len;\n\tu8 *xfer_buf;\n\tstruct completion done;\n};\n\nstruct ti_sysc_module_data {\n\tconst char *name;\n\tu64 module_pa;\n\tu32 module_size;\n\tint *offsets;\n\tint nr_offsets;\n\tconst struct sysc_capabilities *cap;\n\tstruct sysc_config *cfg;\n};\n\nstruct ti_sysc_platform_data {\n\tstruct of_dev_auxdata *auxdata;\n\tbool (*soc_type_gp)(void);\n\tint (*init_clockdomain)(struct device *, struct clk *, struct clk *, struct ti_sysc_cookie *);\n\tvoid (*clkdm_deny_idle)(struct device *, const struct ti_sysc_cookie *);\n\tvoid (*clkdm_allow_idle)(struct device *, const struct ti_sysc_cookie *);\n\tint (*init_module)(struct device *, const struct ti_sysc_module_data *, struct ti_sysc_cookie *);\n\tint (*enable_module)(struct device *, const struct ti_sysc_cookie *);\n\tint (*idle_module)(struct device *, const struct ti_sysc_cookie *);\n\tint (*shutdown_module)(struct device *, const struct ti_sysc_cookie *);\n};\n\nstruct ti_syscon_gate_clk_data {\n\tchar *name;\n\tu32 offset;\n\tu32 bit_idx;\n};\n\nstruct ti_syscon_gate_clk_priv {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 reg;\n\tu32 idx;\n};\n\nstruct ti_syscon_reset_control {\n\tunsigned int assert_offset;\n\tunsigned int assert_bit;\n\tunsigned int deassert_offset;\n\tunsigned int deassert_bit;\n\tunsigned int status_offset;\n\tunsigned int status_bit;\n\tu32 flags;\n};\n\nstruct ti_syscon_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *regmap;\n\tstruct ti_syscon_reset_control *controls;\n\tunsigned int nr_controls;\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct tile_info {\n\tu32 offset;\n\tu32 size;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[9];\n\tstruct hlist_head vectors[576];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_map {\n\tstruct arch_timer_context *direct_vtimer;\n\tstruct arch_timer_context *direct_ptimer;\n\tstruct arch_timer_context *emul_vtimer;\n\tstruct arch_timer_context *emul_ptimer;\n};\n\nstruct timer_of {\n\tunsigned int flags;\n\tstruct device_node *np;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct clock_event_device clkevt;\n\tstruct of_timer_base of_base;\n\tstruct of_timer_irq of_irq;\n\tstruct of_timer_clk of_clk;\n\tvoid *private_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timerlat_entry {\n\tstruct trace_entry ent;\n\tunsigned int seqnum;\n\tint context;\n\tu64 timer_latency;\n};\n\nstruct timestamp_event_queue {\n\tstruct ptp_extts_event buf[128];\n\tint head;\n\tint tail;\n\tspinlock_t lock;\n\tstruct list_head qlist;\n\tlong unsigned int *mask;\n\tstruct dentry *debugfs_instance;\n\tstruct debugfs_u32_array dfs_bitmap;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct timing {\n\tu8 u1sel;\n\tu8 u1pel;\n\t__le16 u2sel;\n\t__le16 u2pel;\n};\n\nstruct timing_data {\n\tconst char *otap_binding;\n\tconst char *itap_binding;\n\tu32 capability;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tstruct tk_read_base base[2];\n};\n\nstruct tlb_inv_context {\n\tstruct kvm_s2_mmu *mmu;\n\tlong unsigned int flags;\n\tu64 tcr;\n\tu64 sctlr;\n};\n\nstruct tlb_inv_context___2 {\n\tstruct kvm_s2_mmu *mmu;\n\tu64 tcr;\n\tu64 sctlr;\n};\n\nunion tlbi_info {\n\tstruct {\n\t\tu64 start;\n\t\tu64 size;\n\t} range;\n\tstruct {\n\t\tu64 addr;\n\t} ipa;\n\tstruct {\n\t\tu64 addr;\n\t\tu32 encoding;\n\t} va;\n};\n\nstruct tlp_rp_regpair_t {\n\tu32 ctrl;\n\tu32 reg0;\n\tu32 reg1;\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\ntypedef void (*tls_done_func_t)(void *, int, key_serial_t);\n\nstruct tls_handshake_args {\n\tstruct socket *ta_sock;\n\ttls_done_func_t ta_done;\n\tvoid *ta_data;\n\tconst char *ta_peername;\n\tunsigned int ta_timeout_ms;\n\tkey_serial_t ta_keyring;\n\tkey_serial_t ta_my_cert;\n\tkey_serial_t ta_my_privkey;\n\tunsigned int ta_num_peerids;\n\tkey_serial_t ta_my_peerids[5];\n};\n\nstruct tls_handshake_req {\n\tvoid (*th_consumer_done)(void *, int, key_serial_t);\n\tvoid *th_consumer_data;\n\tint th_type;\n\tunsigned int th_timeout_ms;\n\tint th_auth_mode;\n\tconst char *th_peername;\n\tkey_serial_t th_keyring;\n\tkey_serial_t th_certificate;\n\tkey_serial_t th_privkey;\n\tunsigned int th_num_peerids;\n\tkey_serial_t th_peerid[5];\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tu64 now;\n\tbool check;\n};\n\nstruct tmio_mmc_dma_ops {\n\tvoid (*start)(struct tmio_mmc_host *, struct mmc_data *);\n\tvoid (*enable)(struct tmio_mmc_host *, bool);\n\tvoid (*request)(struct tmio_mmc_host *, struct tmio_mmc_data *);\n\tvoid (*release)(struct tmio_mmc_host *);\n\tvoid (*abort)(struct tmio_mmc_host *);\n\tvoid (*dataend)(struct tmio_mmc_host *);\n\tvoid (*end)(struct tmio_mmc_host *);\n\tbool (*dma_irq)(struct tmio_mmc_host *);\n};\n\nstruct tmio_mmc_host {\n\tvoid *ctl;\n\tstruct mmc_command *cmd;\n\tstruct mmc_request *mrq;\n\tstruct mmc_data *data;\n\tstruct mmc_host *mmc;\n\tstruct mmc_host_ops ops;\n\tstruct scatterlist *sg_ptr;\n\tstruct scatterlist *sg_orig;\n\tunsigned int sg_len;\n\tunsigned int sg_off;\n\tunsigned int bus_shift;\n\tstruct platform_device *pdev;\n\tstruct tmio_mmc_data *pdata;\n\tbool dma_on;\n\tstruct dma_chan *chan_rx;\n\tstruct dma_chan *chan_tx;\n\tstruct work_struct dma_issue;\n\tstruct scatterlist bounce_sg;\n\tu8 *bounce_buf;\n\tstruct delayed_work delayed_reset_work;\n\tstruct work_struct done;\n\tu32 sdcard_irq_mask;\n\tu32 sdio_irq_mask;\n\tunsigned int clk_cache;\n\tu32 sdcard_irq_setbit_mask;\n\tu32 sdcard_irq_mask_all;\n\tspinlock_t lock;\n\tlong unsigned int last_req_ts;\n\tstruct mutex ios_lock;\n\tbool native_hotplug;\n\tbool sdio_irq_enabled;\n\tint (*clk_enable)(struct tmio_mmc_host *);\n\tvoid (*set_clock)(struct tmio_mmc_host *, unsigned int);\n\tvoid (*clk_disable)(struct tmio_mmc_host *);\n\tint (*multi_io_quirk)(struct mmc_card *, unsigned int, int);\n\tint (*write16_hook)(struct tmio_mmc_host *, int);\n\tvoid (*reset)(struct tmio_mmc_host *, bool);\n\tbool (*check_retune)(struct tmio_mmc_host *, struct mmc_request *);\n\tvoid (*fixup_request)(struct tmio_mmc_host *, struct mmc_request *);\n\tunsigned int (*get_timeout_cycles)(struct tmio_mmc_host *);\n\tvoid (*sdio_irq)(struct tmio_mmc_host *);\n\tconst struct tmio_mmc_dma_ops *dma_ops;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct topology_resp {\n\tu32 topology[3];\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nstruct tp_transition_snapshot {\n\tlong unsigned int rcu;\n\tlong unsigned int srcu_gp;\n\tbool ongoing;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct tpidr2_context {\n\tstruct _aarch64_ctx head;\n\t__u64 tpidr2;\n};\n\nstruct tpm1_get_random_out {\n\t__be32 rng_data_len;\n\tu8 rng_data[128];\n};\n\nstruct tpm2_auth {\n\tu32 handle;\n\tu32 session;\n\tu8 our_nonce[32];\n\tu8 tpm_nonce[32];\n\tunion {\n\t\tu8 salt[32];\n\t\tu8 scratch[32];\n\t};\n\tu8 session_key[32];\n\tu8 passphrase[32];\n\tint passphrase_len;\n\tstruct aes_enckey aes_key;\n\tu8 attrs;\n\t__be32 ordinal;\n\tu32 name_h[3];\n\tu8 name[198];\n};\n\nstruct tpm2_cap_handles {\n\tu8 more_data;\n\t__be32 capability;\n\t__be32 count;\n\t__be32 handles[0];\n} __attribute__((packed));\n\nstruct tpm2_context {\n\t__be64 sequence;\n\t__be32 saved_handle;\n\t__be32 hierarchy;\n\t__be16 blob_size;\n} __attribute__((packed));\n\nstruct tpm2_get_cap_out {\n\tu8 more_data;\n\t__be32 subcap_id;\n\t__be32 property_cnt;\n\t__be32 property_id;\n\t__be32 value;\n} __attribute__((packed));\n\nstruct tpm2_get_random_out {\n\t__be16 size;\n\tu8 buffer[128];\n};\n\nstruct tpm2_hash {\n\tunsigned int crypto_id;\n\tunsigned int tpm_id;\n};\n\nstruct tpm2_pcr_read_out {\n\t__be32 update_cnt;\n\t__be32 pcr_selects_cnt;\n\t__be16 hash_alg;\n\tu8 pcr_select_size;\n\tu8 pcr_select[3];\n\t__be32 digests_cnt;\n\t__be16 digest_size;\n\tu8 digest[0];\n} __attribute__((packed));\n\nstruct tpm2_pcr_selection {\n\t__be16 hash_alg;\n\tu8 size_of_select;\n\tu8 pcr_select[3];\n};\n\nstruct tpm_bank_info {\n\tu16 alg_id;\n\tu16 digest_size;\n\tu16 crypto_id;\n};\n\nstruct tpm_bios_log {\n\tvoid *bios_event_log;\n\tvoid *bios_event_log_end;\n};\n\nstruct tpm_buf {\n\tu32 flags;\n\tu32 length;\n\tu8 *data;\n\tu8 handles;\n};\n\nstruct tpm_chip_seqops {\n\tstruct tpm_chip *chip;\n\tconst struct seq_operations *seqops;\n};\n\nstruct tpm_space {\n\tu32 context_tbl[3];\n\tu8 *context_buf;\n\tu32 session_tbl[3];\n\tu8 *session_buf;\n\tu32 buf_size;\n};\n\nstruct tpm_class_ops;\n\nstruct tpm_chip {\n\tstruct device dev;\n\tstruct device devs;\n\tstruct cdev cdev;\n\tstruct cdev cdevs;\n\tstruct rw_semaphore ops_sem;\n\tconst struct tpm_class_ops *ops;\n\tstruct tpm_bios_log log;\n\tstruct tpm_chip_seqops bin_log_seqops;\n\tstruct tpm_chip_seqops ascii_log_seqops;\n\tunsigned int flags;\n\tint dev_num;\n\tlong unsigned int is_open;\n\tchar hwrng_name[64];\n\tstruct hwrng hwrng;\n\tstruct mutex tpm_mutex;\n\tlong unsigned int timeout_a;\n\tlong unsigned int timeout_b;\n\tlong unsigned int timeout_c;\n\tlong unsigned int timeout_d;\n\tbool timeout_adjusted;\n\tlong unsigned int duration[4];\n\tbool duration_adjusted;\n\tstruct dentry *bios_dir;\n\tconst struct attribute_group *groups[8];\n\tunsigned int groups_cnt;\n\tu32 nr_allocated_banks;\n\tstruct tpm_bank_info allocated_banks[8];\n\tacpi_handle acpi_dev_handle;\n\tchar ppi_version[4];\n\tstruct tpm_space work_space;\n\tu32 last_cc;\n\tu32 nr_commands;\n\tu32 *cc_attrs_tbl;\n\tint locality;\n};\n\nstruct tpm_class_ops {\n\tunsigned int flags;\n\tconst u8 req_complete_mask;\n\tconst u8 req_complete_val;\n\tbool (*req_canceled)(struct tpm_chip *, u8);\n\tint (*recv)(struct tpm_chip *, u8 *, size_t);\n\tint (*send)(struct tpm_chip *, u8 *, size_t, size_t);\n\tvoid (*cancel)(struct tpm_chip *);\n\tu8 (*status)(struct tpm_chip *);\n\tvoid (*update_timeouts)(struct tpm_chip *, long unsigned int *);\n\tvoid (*update_durations)(struct tpm_chip *, long unsigned int *);\n\tint (*go_idle)(struct tpm_chip *);\n\tint (*cmd_ready)(struct tpm_chip *);\n\tint (*request_locality)(struct tpm_chip *, int);\n\tint (*relinquish_locality)(struct tpm_chip *, int);\n\tvoid (*clk_enable)(struct tpm_chip *, bool);\n};\n\nstruct tpm_header {\n\t__be16 tag;\n\t__be32 length;\n\tunion {\n\t\t__be32 ordinal;\n\t\t__be32 return_code;\n\t};\n} __attribute__((packed));\n\nstruct tpm_inf_dev {\n\tstruct i2c_client *client;\n\tint locality;\n\tu8 buf[1261];\n\tstruct tpm_chip *chip;\n\tenum i2c_chip_type chip_type;\n\tunsigned int adapterlimit;\n};\n\nstruct tpm_pcr_attr {\n\tint alg_id;\n\tint pcr;\n\tstruct device_attribute attr;\n};\n\nstruct tpm_readpubek_out {\n\tu8 algorithm[4];\n\tu8 encscheme[2];\n\tu8 sigscheme[2];\n\t__be32 paramsize;\n\tu8 parameters[12];\n\t__be32 keysize;\n\tu8 modulus[256];\n\tu8 checksum[20];\n};\n\nstruct tpmrm_priv {\n\tstruct file_priv priv;\n\tstruct tpm_space space;\n};\n\nstruct tps65219 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct regmap_irq_chip_data *irq_data;\n};\n\nstruct tps65219_regulator_irq_type;\n\nstruct tps65219_chip_data {\n\tsize_t rdesc_size;\n\tsize_t common_rdesc_size;\n\tsize_t dev_irq_size;\n\tsize_t common_irq_size;\n\tconst struct regulator_desc *rdesc;\n\tconst struct regulator_desc *common_rdesc;\n\tstruct tps65219_regulator_irq_type *irq_types;\n\tstruct tps65219_regulator_irq_type *common_irq_types;\n};\n\nstruct tps65219_chip_data___2 {\n\tconst struct regmap_irq_chip *irq_chip;\n\tconst struct mfd_cell *cells;\n\tint n_cells;\n};\n\nstruct tps65219_gpio {\n\tint (*change_dir)(struct gpio_chip *, unsigned int, unsigned int);\n\tstruct gpio_chip gpio_chip;\n\tstruct tps65219 *tps;\n};\n\nstruct tps65219_regulator_irq_data {\n\tstruct device *dev;\n\tstruct tps65219_regulator_irq_type *type;\n\tstruct regulator_dev *rdev;\n};\n\nstruct tps65219_regulator_irq_type {\n\tconst char *irq_name;\n\tconst char *regulator_name;\n\tconst char *event_name;\n\tlong unsigned int event;\n};\n\nstruct trace_module_delta;\n\nstruct trace_pid_list;\n\nstruct tracer_flags;\n\nstruct trace_options;\n\nstruct trace_func_repeats;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tstruct array_buffer array_buffer;\n\tunsigned int mapped;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_size;\n\tchar *range_name;\n\tlong int text_delta;\n\tstruct trace_module_delta *module_delta;\n\tvoid *scratch;\n\tint scratch_size;\n\tint buffer_disabled;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tstruct tracer_flags *current_trace_flags;\n\tu64 trace_flags;\n\tunsigned char trace_flags_index[64];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tconst char *system_names;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct eventfs_inode *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct list_head marker_list;\n\tstruct list_head tracers;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tcpumask_var_t pipe_cpumask;\n\tint ref;\n\tint trace_ref;\n\tstruct list_head mod_events;\n\tint no_filter_buffering_ref;\n\tunsigned int syscall_buf_sz;\n\tstruct list_head hist_vars;\n\tstruct trace_func_repeats *last_func_repeats;\n\tbool ring_buffer_expanded;\n};\n\nstruct trace_array_cpu {\n\tlocal_t disabled;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tbool ignore_pid;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\ntypedef struct trace_buffer *class_ring_buffer_nest_t;\n\nstruct trace_buffer {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tatomic_t resizing;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)(void);\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_end;\n\tstruct ring_buffer_meta *meta;\n\tunsigned int subbuf_size;\n\tunsigned int subbuf_order;\n\tunsigned int max_data_size;\n};\n\nstruct trace_buffer_meta {\n\t__u32 meta_page_size;\n\t__u32 meta_struct_len;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tstruct {\n\t\t__u64 lost_events;\n\t\t__u32 id;\n\t\t__u32 read;\n\t} reader;\n\t__u64 flags;\n\t__u64 entries;\n\t__u64 overrun;\n\t__u64 read;\n\t__u64 Reserved1;\n\t__u64 Reserved2;\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct trace_probe_event;\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_entry_arg *entry_arg;\n\tstruct probe_arg args[0];\n};\n\nstruct trace_eprobe {\n\tconst char *event_system;\n\tconst char *event_name;\n\tchar *filter_str;\n\tstruct trace_event_call *event;\n\tstruct dyn_event devent;\n\tstruct trace_probe tp;\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tunsigned int trace_ctx;\n\tstruct pt_regs *regs;\n};\n\nstruct trace_event_class;\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tconst char *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tunion {\n\t\tvoid *module;\n\t\tatomic_t refcnt;\n\t};\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct trace_event_fields;\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_event_data_offsets_9p_client_req {};\n\nstruct trace_event_data_offsets_9p_client_res {};\n\nstruct trace_event_data_offsets_9p_fid_ref {};\n\nstruct trace_event_data_offsets_9p_protocol_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_aer_event {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 bus_type;\n\tconst void *bus_type_ptr_;\n};\n\nstruct trace_event_data_offsets_alarm_class {};\n\nstruct trace_event_data_offsets_alarmtimer_suspend {};\n\nstruct trace_event_data_offsets_alloc_vmap_area {};\n\nstruct trace_event_data_offsets_aoss_send {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_aoss_send_done {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_arm_event {\n\tu32 pei_buf;\n\tconst void *pei_buf_ptr_;\n\tu32 ctx_buf;\n\tconst void *ctx_buf_ptr_;\n\tu32 oem_buf;\n\tconst void *oem_buf_ptr_;\n};\n\nstruct trace_event_data_offsets_ata_bmdma_status {};\n\nstruct trace_event_data_offsets_ata_eh_action_template {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy_qc {};\n\nstruct trace_event_data_offsets_ata_exec_command_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_begin_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_end_template {};\n\nstruct trace_event_data_offsets_ata_port_eh_begin_template {};\n\nstruct trace_event_data_offsets_ata_qc_complete_template {};\n\nstruct trace_event_data_offsets_ata_qc_issue_template {};\n\nstruct trace_event_data_offsets_ata_sff_hsm_template {};\n\nstruct trace_event_data_offsets_ata_sff_template {};\n\nstruct trace_event_data_offsets_ata_tf_load {};\n\nstruct trace_event_data_offsets_ata_transfer_data_template {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_bl_ext_tree_prepare_commit {};\n\nstruct trace_event_data_offsets_blkdev_zone_mgmt {};\n\nstruct trace_event_data_offsets_block_bio {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_completion {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_zwplug {};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\nstruct trace_event_data_offsets_bpf_trace_printk {\n\tu32 bpf_string;\n\tconst void *bpf_string_ptr_;\n};\n\nstruct trace_event_data_offsets_bpf_trigger_tp {};\n\nstruct trace_event_data_offsets_bpf_xdp_link_attach_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_add {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_external_learn_add {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_update {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_mdb_full {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cap_capable {};\n\nstruct trace_event_data_offsets_cdev_update {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tconst void *dst_path_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_rstat {};\n\nstruct trace_event_data_offsets_ci_log {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_ci_log_trb {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_duty_cycle {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_parent {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 pname;\n\tconst void *pname_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_phase {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate_range {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_clk_rate_request {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 pname;\n\tconst void *pname_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_busy_retry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_finish {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_start {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_release {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_compact_retry {};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_contention_begin {};\n\nstruct trace_event_data_offsets_contention_end {};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_cpu_idle_miss {};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_cros_ec_request_done {};\n\nstruct trace_event_data_offsets_cros_ec_request_start {};\n\nstruct trace_event_data_offsets_cros_ec_sensorhub_data {};\n\nstruct trace_event_data_offsets_cros_ec_sensorhub_filter {};\n\nstruct trace_event_data_offsets_cros_ec_sensorhub_timestamp {};\n\nstruct trace_event_data_offsets_csd_function {};\n\nstruct trace_event_data_offsets_csd_queue_cpu {};\n\nstruct trace_event_data_offsets_ctime {};\n\nstruct trace_event_data_offsets_ctime_ns_xchg {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_devfreq_frequency {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devfreq_monitor {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_end {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_start {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 parent;\n\tconst void *parent_ptr_;\n\tu32 pm_ops;\n\tconst void *pm_ops_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_recover_aborted {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_reporter_state_update {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwerr {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwmsg {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_trap_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 trap_name;\n\tconst void *trap_name_ptr_;\n\tu32 trap_group_name;\n\tconst void *trap_group_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devres {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_attach_dev {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_fd {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence_unsignaled {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg_err {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_single {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 addrs;\n\tconst void *addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dpaa2_eth_buf {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dpaa2_eth_fd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dpaa_eth_fd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dql_stall_detected {};\n\nstruct trace_event_data_offsets_dwc3_log_ctrl {};\n\nstruct trace_event_data_offsets_dwc3_log_ep {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dwc3_log_event {};\n\nstruct trace_event_data_offsets_dwc3_log_gadget_ep_cmd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dwc3_log_generic_cmd {};\n\nstruct trace_event_data_offsets_dwc3_log_io {};\n\nstruct trace_event_data_offsets_dwc3_log_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dwc3_log_set_prtcap {};\n\nstruct trace_event_data_offsets_dwc3_log_trb {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_e1000e_trace_mac_register {};\n\nstruct trace_event_data_offsets_edma_log_io {};\n\nstruct trace_event_data_offsets_edma_log_tcd {};\n\nstruct trace_event_data_offsets_error_report_template {};\n\nstruct trace_event_data_offsets_exit_mmap {};\n\nstruct trace_event_data_offsets_ext4__bitmap_load {};\n\nstruct trace_event_data_offsets_ext4__es_extent {};\n\nstruct trace_event_data_offsets_ext4__es_shrink_enter {};\n\nstruct trace_event_data_offsets_ext4__fallocate_mode {};\n\nstruct trace_event_data_offsets_ext4__folio_op {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_enter {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_exit {};\n\nstruct trace_event_data_offsets_ext4__mb_new_pa {};\n\nstruct trace_event_data_offsets_ext4__mballoc {};\n\nstruct trace_event_data_offsets_ext4__trim {};\n\nstruct trace_event_data_offsets_ext4__truncate {};\n\nstruct trace_event_data_offsets_ext4__write_begin {};\n\nstruct trace_event_data_offsets_ext4__write_end {};\n\nstruct trace_event_data_offsets_ext4_alloc_da_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_inode {};\n\nstruct trace_event_data_offsets_ext4_begin_ordered_truncate {};\n\nstruct trace_event_data_offsets_ext4_collapse_range {};\n\nstruct trace_event_data_offsets_ext4_da_release_space {};\n\nstruct trace_event_data_offsets_ext4_da_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_update_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_end {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_start {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages_extent {};\n\nstruct trace_event_data_offsets_ext4_discard_blocks {};\n\nstruct trace_event_data_offsets_ext4_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_drop_inode {};\n\nstruct trace_event_data_offsets_ext4_error {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_enter {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_exit {};\n\nstruct trace_event_data_offsets_ext4_es_insert_delayed_extent {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_es_remove_extent {};\n\nstruct trace_event_data_offsets_ext4_es_shrink {};\n\nstruct trace_event_data_offsets_ext4_es_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_ext4_evict_inode {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_enter {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_fastpath {};\n\nstruct trace_event_data_offsets_ext4_ext_handle_unwritten_extents {};\n\nstruct trace_event_data_offsets_ext4_ext_load_extent {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space_done {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_idx {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_leaf {};\n\nstruct trace_event_data_offsets_ext4_ext_show_extent {};\n\nstruct trace_event_data_offsets_ext4_fallocate_exit {};\n\nstruct trace_event_data_offsets_ext4_fc_cleanup {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_start {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_stop {};\n\nstruct trace_event_data_offsets_ext4_fc_replay {};\n\nstruct trace_event_data_offsets_ext4_fc_replay_scan {};\n\nstruct trace_event_data_offsets_ext4_fc_stats {};\n\nstruct trace_event_data_offsets_ext4_fc_track_dentry {};\n\nstruct trace_event_data_offsets_ext4_fc_track_inode {};\n\nstruct trace_event_data_offsets_ext4_fc_track_range {};\n\nstruct trace_event_data_offsets_ext4_forget {};\n\nstruct trace_event_data_offsets_ext4_free_blocks {};\n\nstruct trace_event_data_offsets_ext4_free_inode {};\n\nstruct trace_event_data_offsets_ext4_fsmap_class {};\n\nstruct trace_event_data_offsets_ext4_get_implied_cluster_alloc_exit {};\n\nstruct trace_event_data_offsets_ext4_getfsmap_class {};\n\nstruct trace_event_data_offsets_ext4_insert_range {};\n\nstruct trace_event_data_offsets_ext4_invalidate_folio_op {};\n\nstruct trace_event_data_offsets_ext4_journal_start_inode {};\n\nstruct trace_event_data_offsets_ext4_journal_start_reserved {};\n\nstruct trace_event_data_offsets_ext4_journal_start_sb {};\n\nstruct trace_event_data_offsets_ext4_lazy_itable_init {};\n\nstruct trace_event_data_offsets_ext4_load_inode {};\n\nstruct trace_event_data_offsets_ext4_mark_inode_dirty {};\n\nstruct trace_event_data_offsets_ext4_mb_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_mb_release_group_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_inode_pa {};\n\nstruct trace_event_data_offsets_ext4_mballoc_alloc {};\n\nstruct trace_event_data_offsets_ext4_mballoc_prealloc {};\n\nstruct trace_event_data_offsets_ext4_move_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_move_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_nfs_commit_metadata {};\n\nstruct trace_event_data_offsets_ext4_other_inode_update_time {};\n\nstruct trace_event_data_offsets_ext4_prefetch_bitmaps {};\n\nstruct trace_event_data_offsets_ext4_read_block_bitmap_load {};\n\nstruct trace_event_data_offsets_ext4_remove_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_inode {};\n\nstruct trace_event_data_offsets_ext4_shutdown {};\n\nstruct trace_event_data_offsets_ext4_sync_file_enter {};\n\nstruct trace_event_data_offsets_ext4_sync_file_exit {};\n\nstruct trace_event_data_offsets_ext4_sync_fs {};\n\nstruct trace_event_data_offsets_ext4_unlink_enter {};\n\nstruct trace_event_data_offsets_ext4_unlink_exit {};\n\nstruct trace_event_data_offsets_ext4_update_sb {};\n\nstruct trace_event_data_offsets_ext4_writepages {};\n\nstruct trace_event_data_offsets_ext4_writepages_result {};\n\nstruct trace_event_data_offsets_fdb_delete {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_ff_layout_commit_error {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_fib_table_lookup {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_fill_mg_cmtime {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_fl_getdevinfo {\n\tu32 mds_addr;\n\tconst void *mds_addr_ptr_;\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_flush_foreign {};\n\nstruct trace_event_data_offsets_free_vmap_area_noflush {};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_gpio_direction {};\n\nstruct trace_event_data_offsets_gpio_value {};\n\nstruct trace_event_data_offsets_gpu_mem_total {};\n\nstruct trace_event_data_offsets_guest_halt_poll_ns {};\n\nstruct trace_event_data_offsets_handshake_alert_class {};\n\nstruct trace_event_data_offsets_handshake_complete {};\n\nstruct trace_event_data_offsets_handshake_error_class {};\n\nstruct trace_event_data_offsets_handshake_event_class {};\n\nstruct trace_event_data_offsets_handshake_fd_class {};\n\nstruct trace_event_data_offsets_hclge_pf_cmd_template {\n\tu32 pciname;\n\tconst void *pciname_ptr_;\n};\n\nstruct trace_event_data_offsets_hclge_pf_mbx_get {\n\tu32 pciname;\n\tconst void *pciname_ptr_;\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_hclge_pf_mbx_send {\n\tu32 pciname;\n\tconst void *pciname_ptr_;\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_hclge_pf_special_cmd_template {\n\tu32 pciname;\n\tconst void *pciname_ptr_;\n};\n\nstruct trace_event_data_offsets_hns3_rx_desc {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_hns3_skb_template {};\n\nstruct trace_event_data_offsets_hns3_tx_desc {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_setup {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hugetlbfs__inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_alloc_inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_fallocate {};\n\nstruct trace_event_data_offsets_hugetlbfs_setattr {\n\tu32 d_name;\n\tconst void *d_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hw_pressure_update {};\n\nstruct trace_event_data_offsets_hwmon_attr_class {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_show_string {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_read {};\n\nstruct trace_event_data_offsets_i2c_reply {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_result {};\n\nstruct trace_event_data_offsets_i2c_slave {};\n\nstruct trace_event_data_offsets_i2c_write {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_icc_set_bw {\n\tu32 path_name;\n\tconst void *path_name_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 node_name;\n\tconst void *node_name_ptr_;\n};\n\nstruct trace_event_data_offsets_icc_set_bw_end {\n\tu32 path_name;\n\tconst void *path_name_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_icmp_send {};\n\nstruct trace_event_data_offsets_inet_sk_error_report {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n\tconst void *level_ptr_;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_inode_foreign_history {};\n\nstruct trace_event_data_offsets_inode_switch_wbs {};\n\nstruct trace_event_data_offsets_inode_switch_wbs_queue {};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_cqe_overflow {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_defer {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_fail_link {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_local_work_run {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_req_failed {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_short_write {};\n\nstruct trace_event_data_offsets_io_uring_submit_req {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_add {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_work_run {};\n\nstruct trace_event_data_offsets_iomap_add_to_ioend {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_dio_complete {};\n\nstruct trace_event_data_offsets_iomap_dio_rw_begin {};\n\nstruct trace_event_data_offsets_iomap_iter {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_handler {};\n\nstruct trace_event_data_offsets_ipi_raise {\n\tu32 target_cpus;\n\tconst void *target_cpus_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_send_cpu {};\n\nstruct trace_event_data_offsets_ipi_send_cpumask {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint_stats {};\n\nstruct trace_event_data_offsets_jbd2_commit {};\n\nstruct trace_event_data_offsets_jbd2_end_commit {};\n\nstruct trace_event_data_offsets_jbd2_handle_extend {};\n\nstruct trace_event_data_offsets_jbd2_handle_start_class {};\n\nstruct trace_event_data_offsets_jbd2_handle_stats {};\n\nstruct trace_event_data_offsets_jbd2_journal_shrink {};\n\nstruct trace_event_data_offsets_jbd2_lock_buffer_stall {};\n\nstruct trace_event_data_offsets_jbd2_run_stats {};\n\nstruct trace_event_data_offsets_jbd2_shrink_checkpoint_list {};\n\nstruct trace_event_data_offsets_jbd2_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_jbd2_submit_inode_data {};\n\nstruct trace_event_data_offsets_jbd2_update_log_tail {};\n\nstruct trace_event_data_offsets_jbd2_write_superblock {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\nstruct trace_event_data_offsets_kfree {};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_kmalloc {};\n\nstruct trace_event_data_offsets_kmem_cache_alloc {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kmem_cache_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_ksm_advisor {};\n\nstruct trace_event_data_offsets_ksm_enter_exit_template {};\n\nstruct trace_event_data_offsets_ksm_merge_one_page {};\n\nstruct trace_event_data_offsets_ksm_merge_with_ksm_page {};\n\nstruct trace_event_data_offsets_ksm_remove_ksm_page {};\n\nstruct trace_event_data_offsets_ksm_remove_rmap_item {};\n\nstruct trace_event_data_offsets_ksm_scan_template {};\n\nstruct trace_event_data_offsets_kvm_access_fault {};\n\nstruct trace_event_data_offsets_kvm_ack_irq {};\n\nstruct trace_event_data_offsets_kvm_age_hva {};\n\nstruct trace_event_data_offsets_kvm_arm_set_dreg32 {};\n\nstruct trace_event_data_offsets_kvm_dirty_ring_exit {};\n\nstruct trace_event_data_offsets_kvm_dirty_ring_push {};\n\nstruct trace_event_data_offsets_kvm_dirty_ring_reset {};\n\nstruct trace_event_data_offsets_kvm_entry {};\n\nstruct trace_event_data_offsets_kvm_exit {};\n\nstruct trace_event_data_offsets_kvm_forward_sysreg_trap {};\n\nstruct trace_event_data_offsets_kvm_fpu {};\n\nstruct trace_event_data_offsets_kvm_get_timer_map {};\n\nstruct trace_event_data_offsets_kvm_guest_fault {};\n\nstruct trace_event_data_offsets_kvm_halt_poll_ns {};\n\nstruct trace_event_data_offsets_kvm_handle_sys_reg {};\n\nstruct trace_event_data_offsets_kvm_hvc_arm64 {};\n\nstruct trace_event_data_offsets_kvm_inject_nested_exception {};\n\nstruct trace_event_data_offsets_kvm_irq_line {};\n\nstruct trace_event_data_offsets_kvm_mmio {};\n\nstruct trace_event_data_offsets_kvm_mmio_emulate {};\n\nstruct trace_event_data_offsets_kvm_mmio_nisv {};\n\nstruct trace_event_data_offsets_kvm_nested_eret {};\n\nstruct trace_event_data_offsets_kvm_set_guest_debug {};\n\nstruct trace_event_data_offsets_kvm_set_irq {};\n\nstruct trace_event_data_offsets_kvm_set_way_flush {};\n\nstruct trace_event_data_offsets_kvm_sys_access {};\n\nstruct trace_event_data_offsets_kvm_test_age_hva {};\n\nstruct trace_event_data_offsets_kvm_timer_emulate {};\n\nstruct trace_event_data_offsets_kvm_timer_hrtimer_expire {};\n\nstruct trace_event_data_offsets_kvm_timer_restore_state {};\n\nstruct trace_event_data_offsets_kvm_timer_save_state {};\n\nstruct trace_event_data_offsets_kvm_timer_update_irq {};\n\nstruct trace_event_data_offsets_kvm_toggle_cache {};\n\nstruct trace_event_data_offsets_kvm_unmap_hva_range {};\n\nstruct trace_event_data_offsets_kvm_userspace_exit {};\n\nstruct trace_event_data_offsets_kvm_vcpu_wakeup {};\n\nstruct trace_event_data_offsets_kvm_wfx_arm64 {};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_ma_op {};\n\nstruct trace_event_data_offsets_ma_read {};\n\nstruct trace_event_data_offsets_ma_write {};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_mark_victim {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_mc_event {\n\tu32 msg;\n\tconst void *msg_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n\tu32 driver_detail;\n\tconst void *driver_detail_ptr_;\n};\n\nstruct trace_event_data_offsets_mdio_access {};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_memcg_flush_stats {};\n\nstruct trace_event_data_offsets_memcg_rstat_events {};\n\nstruct trace_event_data_offsets_memcg_rstat_stats {};\n\nstruct trace_event_data_offsets_memory_failure_event {};\n\nstruct trace_event_data_offsets_migration_pmd {};\n\nstruct trace_event_data_offsets_migration_pte {};\n\nstruct trace_event_data_offsets_mm_calculate_totalreserve_pages {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page_isolate {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page_swapin {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_filemap_fault {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache_range {};\n\nstruct trace_event_data_offsets_mm_khugepaged_collapse_file {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_khugepaged_scan_file {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_khugepaged_scan_pmd {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\nstruct trace_event_data_offsets_mm_migrate_pages_start {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_lowmem_reserve {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 upper_name;\n\tconst void *upper_name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_wmarks {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_clear_hopeless {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_reclaim_fail {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\nstruct trace_event_data_offsets_mm_vmscan_reclaim_pages {};\n\nstruct trace_event_data_offsets_mm_vmscan_throttled {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_write_folio {};\n\nstruct trace_event_data_offsets_mmap_lock {};\n\nstruct trace_event_data_offsets_mmap_lock_acquire_returned {};\n\nstruct trace_event_data_offsets_mmc_request_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mmc_request_start {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mtu3_log {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_mtu3_log_ep {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mtu3_log_gpd {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mtu3_log_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mtu3_log_setup {};\n\nstruct trace_event_data_offsets_mtu3_qmu_isr {};\n\nstruct trace_event_data_offsets_mtu3_u2_common_isr {};\n\nstruct trace_event_data_offsets_mtu3_u3_ltssm_isr {};\n\nstruct trace_event_data_offsets_musb_isr {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_musb_log {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_musb_regb {};\n\nstruct trace_event_data_offsets_musb_regl {};\n\nstruct trace_event_data_offsets_musb_regw {};\n\nstruct trace_event_data_offsets_musb_req {};\n\nstruct trace_event_data_offsets_musb_state {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 desc;\n\tconst void *desc_ptr_;\n};\n\nstruct trace_event_data_offsets_musb_urb {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_netfs_collect {};\n\nstruct trace_event_data_offsets_netfs_collect_folio {};\n\nstruct trace_event_data_offsets_netfs_collect_gap {};\n\nstruct trace_event_data_offsets_netfs_collect_sreq {};\n\nstruct trace_event_data_offsets_netfs_collect_state {};\n\nstruct trace_event_data_offsets_netfs_collect_stream {};\n\nstruct trace_event_data_offsets_netfs_copy2cache {};\n\nstruct trace_event_data_offsets_netfs_failure {};\n\nstruct trace_event_data_offsets_netfs_folio {};\n\nstruct trace_event_data_offsets_netfs_folioq {};\n\nstruct trace_event_data_offsets_netfs_read {};\n\nstruct trace_event_data_offsets_netfs_rreq {};\n\nstruct trace_event_data_offsets_netfs_rreq_ref {};\n\nstruct trace_event_data_offsets_netfs_sreq {};\n\nstruct trace_event_data_offsets_netfs_sreq_ref {};\n\nstruct trace_event_data_offsets_netfs_write {};\n\nstruct trace_event_data_offsets_netfs_write_iter {};\n\nstruct trace_event_data_offsets_netlink_extack {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_cached_open {};\n\nstruct trace_event_data_offsets_nfs4_cb_error_class {};\n\nstruct trace_event_data_offsets_nfs4_cb_offload {};\n\nstruct trace_event_data_offsets_nfs4_cb_seqid_err {};\n\nstruct trace_event_data_offsets_nfs4_cb_sequence {};\n\nstruct trace_event_data_offsets_nfs4_clientid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_clone {};\n\nstruct trace_event_data_offsets_nfs4_close {};\n\nstruct trace_event_data_offsets_nfs4_commit_event {};\n\nstruct trace_event_data_offsets_nfs4_copy {};\n\nstruct trace_event_data_offsets_nfs4_copy_notify {};\n\nstruct trace_event_data_offsets_nfs4_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_delegreturn_exit {};\n\nstruct trace_event_data_offsets_nfs4_deviceid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_deviceid_status {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_flexfiles_io_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_getattr_event {};\n\nstruct trace_event_data_offsets_nfs4_idmap_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_event {};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_layoutget {};\n\nstruct trace_event_data_offsets_nfs4_llseek {};\n\nstruct trace_event_data_offsets_nfs4_lock_event {};\n\nstruct trace_event_data_offsets_nfs4_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_lookupp {};\n\nstruct trace_event_data_offsets_nfs4_match_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_offload_class {};\n\nstruct trace_event_data_offsets_nfs4_open_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_read_event {};\n\nstruct trace_event_data_offsets_nfs4_rename {\n\tu32 oldname;\n\tconst void *oldname_ptr_;\n\tu32 newname;\n\tconst void *newname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_sequence_done {};\n\nstruct trace_event_data_offsets_nfs4_set_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_set_lock {};\n\nstruct trace_event_data_offsets_nfs4_setup_sequence {};\n\nstruct trace_event_data_offsets_nfs4_sparse_event {};\n\nstruct trace_event_data_offsets_nfs4_state_lock_reclaim {};\n\nstruct trace_event_data_offsets_nfs4_state_mgr {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_state_mgr_failed {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n\tu32 section;\n\tconst void *section_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_test_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_trunked_exchange_id {\n\tu32 main_addr;\n\tconst void *main_addr_ptr_;\n\tu32 trunk_addr;\n\tconst void *trunk_addr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_write_event {};\n\nstruct trace_event_data_offsets_nfs4_xattr_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_xdr_bad_operation {};\n\nstruct trace_event_data_offsets_nfs4_xdr_event {};\n\nstruct trace_event_data_offsets_nfs_access_exit {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead_done {};\n\nstruct trace_event_data_offsets_nfs_atomic_open_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_atomic_open_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_commit_done {};\n\nstruct trace_event_data_offsets_nfs_create_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_create_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_direct_req_class {};\n\nstruct trace_event_data_offsets_nfs_directory_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_directory_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_fh_to_dentry {};\n\nstruct trace_event_data_offsets_nfs_folio_event {};\n\nstruct trace_event_data_offsets_nfs_folio_event_done {};\n\nstruct trace_event_data_offsets_nfs_initiate_commit {};\n\nstruct trace_event_data_offsets_nfs_initiate_read {};\n\nstruct trace_event_data_offsets_nfs_initiate_write {};\n\nstruct trace_event_data_offsets_nfs_inode_event {};\n\nstruct trace_event_data_offsets_nfs_inode_event_done {};\n\nstruct trace_event_data_offsets_nfs_inode_range_event {};\n\nstruct trace_event_data_offsets_nfs_kiocb_event {};\n\nstruct trace_event_data_offsets_nfs_link_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_link_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_local_open_fh {};\n\nstruct trace_event_data_offsets_nfs_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_lookup_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_assign {\n\tu32 option;\n\tconst void *option_ptr_;\n\tu32 value;\n\tconst void *value_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_option {\n\tu32 option;\n\tconst void *option_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_path {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_page_class {};\n\nstruct trace_event_data_offsets_nfs_page_error_class {};\n\nstruct trace_event_data_offsets_nfs_pgio_error {};\n\nstruct trace_event_data_offsets_nfs_readdir_event {};\n\nstruct trace_event_data_offsets_nfs_readpage_done {};\n\nstruct trace_event_data_offsets_nfs_readpage_short {};\n\nstruct trace_event_data_offsets_nfs_rename_event {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_rename_event_done {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_sillyrename_unlink {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_update_size_class {};\n\nstruct trace_event_data_offsets_nfs_writeback_done {};\n\nstruct trace_event_data_offsets_nfs_xdr_event {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_nlmclnt_lock_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_non_standard_event {\n\tu32 fru_text;\n\tconst void *fru_text_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_notifier_info {};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_optee_invoke_fn_begin {};\n\nstruct trace_event_data_offsets_optee_invoke_fn_end {};\n\nstruct trace_event_data_offsets_page_cache_ra_op {};\n\nstruct trace_event_data_offsets_page_cache_ra_order {};\n\nstruct trace_event_data_offsets_page_cache_ra_unbounded {};\n\nstruct trace_event_data_offsets_page_pool_release {};\n\nstruct trace_event_data_offsets_page_pool_state_hold {};\n\nstruct trace_event_data_offsets_page_pool_state_release {};\n\nstruct trace_event_data_offsets_page_pool_update_nid {};\n\nstruct trace_event_data_offsets_pci_hp_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n\tu32 slot;\n\tconst void *slot_ptr_;\n};\n\nstruct trace_event_data_offsets_pcie_link_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_pmap_register {};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_err_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_ds_connect {\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_layout_event {};\n\nstruct trace_event_data_offsets_pnfs_update_layout {};\n\nstruct trace_event_data_offsets_psci_domain_idle {};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_purge_vmap_area_lazy {};\n\nstruct trace_event_data_offsets_pwm {};\n\nstruct trace_event_data_offsets_pwm_read_waveform {};\n\nstruct trace_event_data_offsets_pwm_round_waveform_fromhw {};\n\nstruct trace_event_data_offsets_pwm_round_waveform_tohw {};\n\nstruct trace_event_data_offsets_pwm_write_waveform {};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_close {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_close_ack {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_intent {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_open {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_open_ack {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_read_notif {\n\tu32 remote;\n\tconst void *remote_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_rx_done {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_rx_intent_req {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_rx_intent_req_ack {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_signal {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_tx_data {\n\tu32 remote;\n\tconst void *remote_ptr_;\n\tu32 channel;\n\tconst void *channel_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_version {\n\tu32 remote;\n\tconst void *remote_ptr_;\n};\n\nstruct trace_event_data_offsets_qcom_glink_cmd_version_ack {\n\tu32 remote;\n\tconst void *remote_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_enqueue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kvfree_callback {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_segcb_stats {};\n\nstruct trace_event_data_offsets_rcu_sr_normal {};\n\nstruct trace_event_data_offsets_rcu_stall_warning {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_watching {};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_regcache_drop_region {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regcache_sync {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 status;\n\tconst void *status_ptr_;\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_register_class {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_async {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bool {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bulk {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_reg {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_basic {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_range {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regulator_value {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_buf_alloc {};\n\nstruct trace_event_data_offsets_rpc_call_rpcerror {};\n\nstruct trace_event_data_offsets_rpc_clnt_class {};\n\nstruct trace_event_data_offsets_rpc_clnt_clone_err {};\n\nstruct trace_event_data_offsets_rpc_clnt_new {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_clnt_new_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_failure {};\n\nstruct trace_event_data_offsets_rpc_reply_event {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_request {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_socket_nospace {};\n\nstruct trace_event_data_offsets_rpc_stats_latency {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_queued {\n\tu32 q_name;\n\tconst void *q_name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_running {};\n\nstruct trace_event_data_offsets_rpc_task_status {};\n\nstruct trace_event_data_offsets_rpc_tls_class {\n\tu32 servername;\n\tconst void *servername_ptr_;\n\tu32 progname;\n\tconst void *progname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_alignment {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_rpc_xdr_overflow {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_lifetime_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_getport {\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_register {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_setport {};\n\nstruct trace_event_data_offsets_rpcb_unregister {\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_bad_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_context {\n\tu32 acceptor;\n\tconst void *acceptor_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_createauth {};\n\nstruct trace_event_data_offsets_rpcgss_ctx_class {\n\tu32 principal;\n\tconst void *principal_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_gssapi_event {};\n\nstruct trace_event_data_offsets_rpcgss_import_ctx {};\n\nstruct trace_event_data_offsets_rpcgss_need_reencode {};\n\nstruct trace_event_data_offsets_rpcgss_oid_to_mech {\n\tu32 oid;\n\tconst void *oid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_svc_accept_upcall {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_authenticate {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_gssapi_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_bad {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_class {};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_low {};\n\nstruct trace_event_data_offsets_rpcgss_svc_unwrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_wrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_unwrap_failed {};\n\nstruct trace_event_data_offsets_rpcgss_upcall_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_upcall_result {};\n\nstruct trace_event_data_offsets_rpcgss_update_slack {};\n\nstruct trace_event_data_offsets_rpm_internal {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_return_int {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_status {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpmh_send_msg {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpmh_tx_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\nstruct trace_event_data_offsets_rtc_alarm_irq_enable {};\n\nstruct trace_event_data_offsets_rtc_irq_set_freq {};\n\nstruct trace_event_data_offsets_rtc_irq_set_state {};\n\nstruct trace_event_data_offsets_rtc_offset_class {};\n\nstruct trace_event_data_offsets_rtc_time_alarm_class {};\n\nstruct trace_event_data_offsets_rtc_timer_class {};\n\nstruct trace_event_data_offsets_sched_ext_bypass_lb {};\n\nstruct trace_event_data_offsets_sched_ext_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_ext_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_end {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_start {};\n\nstruct trace_event_data_offsets_sched_kthread_work_queue_work {};\n\nstruct trace_event_data_offsets_sched_migrate_task {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_move_numa {};\n\nstruct trace_event_data_offsets_sched_numa_pair_template {};\n\nstruct trace_event_data_offsets_sched_pi_setprio {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_prepare_exec {\n\tu32 interp;\n\tconst void *interp_ptr_;\n\tu32 filename;\n\tconst void *filename_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exit {};\n\nstruct trace_event_data_offsets_sched_process_fork {\n\tu32 parent_comm;\n\tconst void *parent_comm_ptr_;\n\tu32 child_comm;\n\tconst void *child_comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_wait {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_skip_cpuset_numa {};\n\nstruct trace_event_data_offsets_sched_skip_vma_numa {};\n\nstruct trace_event_data_offsets_sched_stat_runtime {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_scmi_fc_call {};\n\nstruct trace_event_data_offsets_scmi_msg_dump {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_scmi_rx_done {};\n\nstruct trace_event_data_offsets_scmi_xfer_begin {};\n\nstruct trace_event_data_offsets_scmi_xfer_end {};\n\nstruct trace_event_data_offsets_scmi_xfer_response_wait {};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_sk_data_ready {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_smbus_read {};\n\nstruct trace_event_data_offsets_smbus_reply {};\n\nstruct trace_event_data_offsets_smbus_result {};\n\nstruct trace_event_data_offsets_smbus_write {};\n\nstruct trace_event_data_offsets_smp2p_negotiate {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_smp2p_notify_in {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 client_name;\n\tconst void *client_name_ptr_;\n};\n\nstruct trace_event_data_offsets_smp2p_ssr_ack {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_smp2p_update_bits {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 client_name;\n\tconst void *client_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_sock_msg_length {};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_softirq {};\n\nstruct trace_event_data_offsets_spi_controller {};\n\nstruct trace_event_data_offsets_spi_mem_start_op {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 op;\n\tconst void *op_ptr_;\n\tu32 data;\n\tconst void *data_ptr_;\n};\n\nstruct trace_event_data_offsets_spi_mem_stop_op {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 data;\n\tconst void *data_ptr_;\n};\n\nstruct trace_event_data_offsets_spi_message {};\n\nstruct trace_event_data_offsets_spi_message_done {};\n\nstruct trace_event_data_offsets_spi_set_cs {};\n\nstruct trace_event_data_offsets_spi_setup {};\n\nstruct trace_event_data_offsets_spi_transfer {\n\tu32 rx_buf;\n\tconst void *rx_buf_ptr_;\n\tu32 tx_buf;\n\tconst void *tx_buf_ptr_;\n};\n\nstruct trace_event_data_offsets_spmi_cmd {};\n\nstruct trace_event_data_offsets_spmi_read_begin {};\n\nstruct trace_event_data_offsets_spmi_read_end {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_spmi_write_begin {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_spmi_write_end {};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_svc_alloc_arg_err {};\n\nstruct trace_event_data_offsets_svc_authenticate {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_deferred_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_pool_thread_event {};\n\nstruct trace_event_data_offsets_svc_process {\n\tu32 service;\n\tconst void *service_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_replace_page_err {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_status {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_stats_latency {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_unregister {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_svc_xdr_msg_class {};\n\nstruct trace_event_data_offsets_svc_xprt_accept {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_create_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_dequeue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_enqueue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_accept_class {\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_lifetime_class {};\n\nstruct trace_event_data_offsets_svcsock_marker {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_recv_short {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_state {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_swiotlb_bounced {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_prctl_unknown {};\n\nstruct trace_event_data_offsets_task_rename {};\n\nstruct trace_event_data_offsets_tasklet {};\n\nstruct trace_event_data_offsets_tcp_ao_event {};\n\nstruct trace_event_data_offsets_tcp_cong_state_set {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_event_skb {};\n\nstruct trace_event_data_offsets_tcp_hash_event {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\nstruct trace_event_data_offsets_tcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_tcp_retransmit_skb {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_send_reset {};\n\nstruct trace_event_data_offsets_tcp_sendmsg_locked {};\n\nstruct trace_event_data_offsets_tegra_dma_complete_cb {\n\tu32 chan;\n\tconst void *chan_ptr_;\n};\n\nstruct trace_event_data_offsets_tegra_dma_isr {\n\tu32 chan;\n\tconst void *chan_ptr_;\n};\n\nstruct trace_event_data_offsets_tegra_dma_tx_status {\n\tu32 chan;\n\tconst void *chan_ptr_;\n};\n\nstruct trace_event_data_offsets_test_pages_isolated {};\n\nstruct trace_event_data_offsets_thermal_power_actor {};\n\nstruct trace_event_data_offsets_thermal_power_allocator {};\n\nstruct trace_event_data_offsets_thermal_power_allocator_pid {};\n\nstruct trace_event_data_offsets_thermal_power_cpu_get_power_simple {};\n\nstruct trace_event_data_offsets_thermal_power_cpu_limit {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_power_devfreq_get_power {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_power_devfreq_limit {\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_temperature {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_thermal_zone_trip {\n\tu32 thermal_zone;\n\tconst void *thermal_zone_ptr_;\n};\n\nstruct trace_event_data_offsets_tick_stop {};\n\nstruct trace_event_data_offsets_timer_base_idle {};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_tls_contenttype {};\n\nstruct trace_event_data_offsets_tmigr_connect_child_parent {};\n\nstruct trace_event_data_offsets_tmigr_connect_cpu_parent {};\n\nstruct trace_event_data_offsets_tmigr_cpugroup {};\n\nstruct trace_event_data_offsets_tmigr_group_and_cpu {};\n\nstruct trace_event_data_offsets_tmigr_group_set {};\n\nstruct trace_event_data_offsets_tmigr_handle_remote {};\n\nstruct trace_event_data_offsets_tmigr_idle {};\n\nstruct trace_event_data_offsets_tmigr_update_events {};\n\nstruct trace_event_data_offsets_track_foreign_dirty {};\n\nstruct trace_event_data_offsets_udc_log_ep {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_udc_log_gadget {};\n\nstruct trace_event_data_offsets_udc_log_req {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\nstruct trace_event_data_offsets_ufs_mtk_clk_scale {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_ufs_mtk_event {};\n\nstruct trace_event_data_offsets_ufshcd_auto_bkops_state {\n\tu32 state;\n\tconst void *state_ptr_;\n};\n\nstruct trace_event_data_offsets_ufshcd_clk_gating {};\n\nstruct trace_event_data_offsets_ufshcd_clk_scaling {\n\tu32 state;\n\tconst void *state_ptr_;\n\tu32 clk;\n\tconst void *clk_ptr_;\n};\n\nstruct trace_event_data_offsets_ufshcd_command {};\n\nstruct trace_event_data_offsets_ufshcd_exception_event {};\n\nstruct trace_event_data_offsets_ufshcd_profiling_template {\n\tu32 profile_info;\n\tconst void *profile_info_ptr_;\n};\n\nstruct trace_event_data_offsets_ufshcd_template {};\n\nstruct trace_event_data_offsets_ufshcd_uic_command {};\n\nstruct trace_event_data_offsets_ufshcd_upiu {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_usb_core_log_usb_device {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_vgic_update_irq_pending {};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_watchdog_set_timeout {};\n\nstruct trace_event_data_offsets_watchdog_template {};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_queue_work {\n\tu32 workqueue;\n\tconst void *workqueue_ptr_;\n};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_folio_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_data_offsets_xhci_dbc_log_request {};\n\nstruct trace_event_data_offsets_xhci_log_ctrl_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_doorbell {};\n\nstruct trace_event_data_offsets_xhci_log_ep_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_free_virt_dev {};\n\nstruct trace_event_data_offsets_xhci_log_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_portsc {};\n\nstruct trace_event_data_offsets_xhci_log_ring {};\n\nstruct trace_event_data_offsets_xhci_log_slot_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_stream_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_trb {};\n\nstruct trace_event_data_offsets_xhci_log_urb {\n\tu32 devname;\n\tconst void *devname_ptr_;\n};\n\nstruct trace_event_data_offsets_xhci_log_virt_dev {};\n\nstruct trace_event_data_offsets_xprt_cong_event {};\n\nstruct trace_event_data_offsets_xprt_ping {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_reserve {};\n\nstruct trace_event_data_offsets_xprt_retransmit {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_transmit {};\n\nstruct trace_event_data_offsets_xprt_writelock_event {};\n\nstruct trace_event_data_offsets_xs_data_ready {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_socket_event {};\n\nstruct trace_event_data_offsets_xs_socket_event_done {};\n\nstruct trace_event_data_offsets_xs_stream_read_data {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_stream_read_request {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst unsigned int is_signed: 1;\n\t\t\tunsigned int needs_test: 1;\n\t\t\tconst int filter_type;\n\t\t\tconst int len;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct eventfs_inode *ei;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\trefcount_t ref;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nstruct trace_event_raw_9p_client_req {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_client_res {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u32 tag;\n\t__u32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_fid_ref {\n\tstruct trace_entry ent;\n\tint fid;\n\tint refcount;\n\t__u8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_9p_protocol_dump {\n\tstruct trace_entry ent;\n\tvoid *clnt;\n\t__u8 type;\n\t__u16 tag;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_aer_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 status;\n\tu8 severity;\n\tu8 tlp_header_valid;\n\tu32 tlp_header[14];\n\tu32 __data_loc_bus_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarmtimer_suspend {\n\tstruct trace_entry ent;\n\ts64 expires;\n\tunsigned char alarm_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alloc_vmap_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int vstart;\n\tlong unsigned int vend;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_aoss_send {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_aoss_send_done {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_arm_event {\n\tstruct trace_entry ent;\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n\tu8 affinity;\n\tu32 pei_len;\n\tu32 __data_loc_pei_buf;\n\tu32 ctx_len;\n\tu32 __data_loc_ctx_buf;\n\tu32 oem_len;\n\tu32 __data_loc_oem_buf;\n\tu8 sev;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_bmdma_status {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char host_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_action_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy_qc {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_exec_command_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char feature;\n\tunsigned char hob_nsect;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tlong unsigned int deadline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_end_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tint rc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_port_eh_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_complete_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char status;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char error;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_issue_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tunsigned char proto;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_hsm_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int protocol;\n\tunsigned int hsm_state;\n\tunsigned char dev_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char hsm_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_tf_load {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_transfer_data_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int flags;\n\tunsigned int offset;\n\tunsigned int bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int wb_setpoint;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bl_ext_tree_prepare_commit {\n\tstruct trace_entry ent;\n\tint ret;\n\tsize_t count;\n\tu64 lwb;\n\tbool not_all_ranges;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_blkdev_zone_mgmt {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t nr_sectors;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_completion {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_zwplug {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int zno;\n\tsector_t sector;\n\tunsigned int nr_sectors;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trace_printk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bpf_string;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trigger_tp {\n\tstruct trace_entry ent;\n\tint nonce;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_xdp_link_attach_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_add {\n\tstruct trace_entry ent;\n\tu8 ndm_flags;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tu16 nlh_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_external_learn_add {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_mdb_full {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tint af;\n\tu16 vid;\n\t__u8 src[16];\n\t__u8 grp[16];\n\t__u8 grpmac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_event {\n\tstruct trace_entry ent;\n\tconst struct cache_head *h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cap_capable {\n\tstruct trace_entry ent;\n\tconst struct cred *cred;\n\tstruct user_namespace *target_ns;\n\tconst struct user_namespace *capable_ns;\n\tint cap;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cdev_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int target;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_level;\n\tu64 dst_id;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu32 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_rstat {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tint cpu;\n\tbool contended;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ci_log {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ci_log_trb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tstruct td_node *td;\n\tstruct usb_request *req;\n\tdma_addr_t dma;\n\ts32 td_remaining_size;\n\tu32 next;\n\tu32 token;\n\tu32 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_duty_cycle {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int num;\n\tunsigned int den;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_parent {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_pname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_phase {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint phase;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int rate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate_range {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_pname;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int prate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_busy_retry {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_finish {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tint errorno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int request_count;\n\tlong unsigned int available_count;\n\tlong unsigned int total_count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_release {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_begin {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_end {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_idle_miss {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool below;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cros_ec_request_done {\n\tstruct trace_entry ent;\n\tuint32_t version;\n\tuint32_t offset;\n\tuint32_t command;\n\tuint32_t outsize;\n\tuint32_t insize;\n\tuint32_t result;\n\tint retval;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cros_ec_request_start {\n\tstruct trace_entry ent;\n\tuint32_t version;\n\tuint32_t offset;\n\tuint32_t command;\n\tuint32_t outsize;\n\tuint32_t insize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cros_ec_sensorhub_data {\n\tstruct trace_entry ent;\n\tu32 ec_sensor_num;\n\tu32 ec_fifo_timestamp;\n\ts64 fifo_timestamp;\n\ts64 current_timestamp;\n\ts64 current_time;\n\ts64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cros_ec_sensorhub_filter {\n\tstruct trace_entry ent;\n\ts64 dx;\n\ts64 dy;\n\ts64 median_m;\n\ts64 median_error;\n\ts64 history_len;\n\ts64 x;\n\ts64 y;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cros_ec_sensorhub_timestamp {\n\tstruct trace_entry ent;\n\tu32 ec_sample_timestamp;\n\tu32 ec_fifo_timestamp;\n\ts64 fifo_timestamp;\n\ts64 current_timestamp;\n\ts64 current_time;\n\ts64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_function {\n\tstruct trace_entry ent;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_queue_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\tu32 ctime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime_ns_xchg {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tu32 gen;\n\tu32 old;\n\tu32 new;\n\tu32 cur;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devfreq_frequency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tlong unsigned int freq;\n\tlong unsigned int prev_freq;\n\tlong unsigned int busy_time;\n\tlong unsigned int total_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devfreq_monitor {\n\tstruct trace_entry ent;\n\tlong unsigned int freq;\n\tlong unsigned int busy_time;\n\tlong unsigned int total_time;\n\tunsigned int polling_ms;\n\tu32 __data_loc_dev_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_parent;\n\tu32 __data_loc_pm_ops;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_recover_aborted {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tbool health_state;\n\tu64 time_since_last_recover;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_reporter_state_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu8 new_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwerr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tint err;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwmsg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tbool incoming;\n\tlong unsigned int type;\n\tu32 __data_loc_buf;\n\tsize_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_trap_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_trap_name;\n\tu32 __data_loc_trap_group_name;\n\tchar input_dev_name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devres {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tstruct device *dev;\n\tconst char *op;\n\tvoid *node;\n\tu32 __data_loc_name;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tgfp_t flags;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tgfp_t flags;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_attach_dev {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tstruct dma_buf_attachment *attach;\n\tbool is_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_fd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence_unsignaled {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 phys_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tint full_nents;\n\tint full_ents;\n\tbool truncated;\n\tu32 __data_loc_phys_addrs;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tint err;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_single {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_addrs;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dpaa2_eth_buf {\n\tstruct trace_entry ent;\n\tvoid *vaddr;\n\tsize_t size;\n\tdma_addr_t dma_addr;\n\tsize_t map_size;\n\tu16 bpid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dpaa2_eth_fd {\n\tstruct trace_entry ent;\n\tu64 fd_addr;\n\tu32 fd_len;\n\tu16 fd_offset;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dpaa_eth_fd {\n\tstruct trace_entry ent;\n\tu32 fqid;\n\tu64 fd_addr;\n\tu8 fd_format;\n\tu16 fd_offset;\n\tu32 fd_length;\n\tu32 fd_status;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dql_stall_detected {\n\tstruct trace_entry ent;\n\tshort unsigned int thrs;\n\tunsigned int len;\n\tlong unsigned int last_reap;\n\tlong unsigned int hist_head;\n\tlong unsigned int now;\n\tlong unsigned int hist[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_ctrl {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_ep {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tunsigned int maxpacket;\n\tunsigned int maxpacket_limit;\n\tunsigned int max_streams;\n\tunsigned int maxburst;\n\tunsigned int flags;\n\tunsigned int direction;\n\tu8 trb_enqueue;\n\tu8 trb_dequeue;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_event {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 event;\n\tu32 ep0state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_gadget_ep_cmd {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tunsigned int cmd;\n\tu32 param0;\n\tu32 param1;\n\tu32 param2;\n\tint cmd_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_generic_cmd {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tunsigned int cmd;\n\tu32 param;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_io {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tvoid *base;\n\tu32 offset;\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_request {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tstruct dwc3_request *req;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tint zero;\n\tint short_not_ok;\n\tint no_interrupt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_set_prtcap {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dwc3_log_trb {\n\tstruct trace_entry ent;\n\tphys_addr_t base_address;\n\tu32 __data_loc_name;\n\tstruct dwc3_trb *trb;\n\tu32 bpl;\n\tu32 bph;\n\tu32 size;\n\tu32 ctrl;\n\tu32 type;\n\tu32 enqueue;\n\tu32 dequeue;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_e1000e_trace_mac_register {\n\tstruct trace_entry ent;\n\tuint32_t reg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_edma_log_io {\n\tstruct trace_entry ent;\n\tstruct fsl_edma_engine *edma;\n\tvoid *addr;\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_edma_log_tcd {\n\tstruct trace_entry ent;\n\tu64 saddr;\n\tu16 soff;\n\tu16 attr;\n\tu32 nbytes;\n\tu64 slast;\n\tu64 daddr;\n\tu16 doff;\n\tu16 citer;\n\tu64 dlast_sga;\n\tu16 csr;\n\tu16 biter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_error_report_template {\n\tstruct trace_entry ent;\n\tenum error_detector error_detector;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exit_mmap {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tstruct maple_tree *mt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_shrink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_to_scan;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__fallocate_mode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tint mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int flags;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int mflags;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mb_new_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 pa_pstart;\n\t__u64 pa_lstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mballoc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__trim {\n\tstruct trace_entry ent;\n\tint dev_major;\n\tint dev_minor;\n\t__u32 group;\n\tint start;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int copied;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_alloc_da_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int data_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_begin_ordered_truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_collapse_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_release_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint freed_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint reserve_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_update_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint used_blocks;\n\tint reserved_data_blocks;\n\tint quota_claim;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 lblk;\n\t__u32 len;\n\t__u32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 blk;\n\t__u64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_drop_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint drop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tconst char *function;\n\tunsigned int line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_insert_delayed_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tbool lclu_allocated;\n\tbool end_allocated;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tint found;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_remove_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t lblk;\n\tloff_t len;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tlong long unsigned int scan_time;\n\tint nr_skipped;\n\tint retried;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_evict_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_fastpath {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\text4_lblk_t i_lblk;\n\tunsigned int i_len;\n\text4_fsblk_t i_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_handle_unwritten_extents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tunsigned int allocated;\n\text4_fsblk_t newblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_load_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tshort unsigned int eh_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_idx {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_leaf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t ee_lblk;\n\text4_fsblk_t ee_pblk;\n\tshort int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_show_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tshort unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fallocate_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int blocks;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_cleanup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint j_fc_off;\n\tint full;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_stop {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nblks;\n\tint reason;\n\tint num_fc;\n\tint num_fc_ineligible;\n\tint nblks_agg;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint tag;\n\tint ino;\n\tint priv1;\n\tint priv2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint error;\n\tint off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int fc_ineligible_rc[13];\n\tlong unsigned int fc_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_numblks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_dentry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tlong int start;\n\tlong int end;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_forget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tint is_metadata;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tlong unsigned int count;\n\tint flags;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u64 blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu32 agno;\n\tu64 bno;\n\tu64 len;\n\tu64 owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_implied_cluster_alloc_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu64 block;\n\tu64 len;\n\tu64 owner;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_insert_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_invalidate_folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tsize_t offset;\n\tsize_t length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_inode {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_reserved {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_lazy_itable_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_load_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mark_inode_dirty {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint needed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_group_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 pa_pstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_inode_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\t__u32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 goal_logical;\n\tint goal_start;\n\t__u32 goal_group;\n\tint goal_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\t__u16 found;\n\t__u16 groups;\n\t__u16 buddy;\n\t__u16 flags;\n\t__u16 tail;\n\t__u8 cr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_prealloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tunsigned int orig_flags;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int m_len;\n\tu64 move_len;\n\tint move_type;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_nfs_commit_metadata {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_other_inode_update_time {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t orig_ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_prefetch_bitmaps {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\t__u32 next;\n\t__u32 ios;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_read_block_bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tbool prefetch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_remove_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\text4_fsblk_t ee_pblk;\n\text4_lblk_t ee_lblk;\n\tshort unsigned int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tint datasync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_update_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\text4_fsblk_t fsblk;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages_result {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tint pages_written;\n\tlong int pages_skipped;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fdb_delete {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ff_layout_commit_error {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tchar name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lease *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tlong unsigned int break_time;\n\tlong unsigned int downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int pid;\n\tunsigned int flags;\n\tunsigned char type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fill_mg_cmtime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\ttime64_t mtime_s;\n\tu32 ctime_ns;\n\tu32 mtime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fl_getdevinfo {\n\tstruct trace_entry ent;\n\tu32 __data_loc_mds_addr;\n\tunsigned char deviceid[16];\n\tu32 __data_loc_ds_ips;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_flush_foreign {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tunsigned int frn_bdi_id;\n\tunsigned int frn_memcg_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_free_vmap_area_noflush {\n\tstruct trace_entry ent;\n\tlong unsigned int va_start;\n\tlong unsigned int nr_lazy;\n\tlong unsigned int nr_lazy_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpio_direction {\n\tstruct trace_entry ent;\n\tunsigned int gpio;\n\tint in;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpio_value {\n\tstruct trace_entry ent;\n\tunsigned int gpio;\n\tint get;\n\tint value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_gpu_mem_total {\n\tstruct trace_entry ent;\n\tuint32_t gpu_id;\n\tuint32_t pid;\n\tuint64_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_guest_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_alert_class {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int level;\n\tlong unsigned int description;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_complete {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint status;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_error_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint err;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_event_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_fd_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint fd;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hclge_pf_cmd_template {\n\tstruct trace_entry ent;\n\tu16 opcode;\n\tu16 flag;\n\tu16 retval;\n\tu16 rsv;\n\tint index;\n\tint num;\n\tu32 __data_loc_pciname;\n\tu32 data[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hclge_pf_mbx_get {\n\tstruct trace_entry ent;\n\tu8 vfid;\n\tu8 code;\n\tu8 subcode;\n\tu32 __data_loc_pciname;\n\tu32 __data_loc_devname;\n\tu32 mbx_data[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hclge_pf_mbx_send {\n\tstruct trace_entry ent;\n\tu8 vfid;\n\tu16 code;\n\tu32 __data_loc_pciname;\n\tu32 __data_loc_devname;\n\tu32 mbx_data[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hclge_pf_special_cmd_template {\n\tstruct trace_entry ent;\n\tint index;\n\tint num;\n\tu32 __data_loc_pciname;\n\tu32 data[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hns3_rx_desc {\n\tstruct trace_entry ent;\n\tint index;\n\tint ntu;\n\tint ntc;\n\tdma_addr_t desc_dma;\n\tdma_addr_t buf_dma;\n\tu32 desc[8];\n\tu32 __data_loc_devname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hns3_skb_template {\n\tstruct trace_entry ent;\n\tunsigned int headlen;\n\tunsigned int len;\n\t__u8 nr_frags;\n\t__u8 ip_summed;\n\tunsigned int hdr_len;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tunsigned int gso_type;\n\tbool fraglist;\n\t__u32 size[17];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hns3_tx_desc {\n\tstruct trace_entry ent;\n\tint index;\n\tint ntu;\n\tint ntc;\n\tdma_addr_t desc_dma;\n\tu32 desc[8];\n\tu32 __data_loc_devname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_setup {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs__inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u16 mode;\n\tloff_t size;\n\tunsigned int nlink;\n\tunsigned int seals;\n\tblkcnt_t blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_alloc_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_fallocate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint mode;\n\tloff_t offset;\n\tloff_t len;\n\tloff_t size;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_setattr {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int d_len;\n\tu32 __data_loc_d_name;\n\tunsigned int ia_valid;\n\tunsigned int ia_mode;\n\tloff_t old_size;\n\tloff_t ia_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hw_pressure_update {\n\tstruct trace_entry ent;\n\tlong unsigned int hw_pressure;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_class {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tlong long int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_show_string {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tu32 __data_loc_label;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 nr_msgs;\n\t__s16 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_slave {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\tint ret;\n\t__u16 addr;\n\t__u16 len;\n\tenum i2c_slave_event event;\n\t__u8 buf[1];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icc_set_bw {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path_name;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_node_name;\n\tu32 avg_bw;\n\tu32 peak_bw;\n\tu32 node_avg_bw;\n\tu32 node_peak_bw;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icc_set_bw_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path_name;\n\tu32 __data_loc_dev;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icmp_send {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint type;\n\tint code;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u16 sport;\n\t__u16 dport;\n\tshort unsigned int ulen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sk_error_report {\n\tstruct trace_entry ent;\n\tint error;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\ntypedef int (*initcall_t)(void);\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_foreign_history {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t cgroup_ino;\n\tunsigned int history;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs_queue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint res;\n\tunsigned int cflags;\n\tu64 extra1;\n\tu64 extra2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqe_overflow {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong long unsigned int user_data;\n\ts32 res;\n\tu32 cflags;\n\tvoid *ocqe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tu8 opcode;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tvoid *link;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_local_work_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint count;\n\tunsigned int loops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tint events;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tstruct io_wq_work *work;\n\tbool hashed;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_req_failed {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tu8 flags;\n\tu8 ioprio;\n\tu64 off;\n\tu64 addr;\n\tu32 len;\n\tu32 op_flags;\n\tu16 buf_index;\n\tu16 personality;\n\tu32 file_index;\n\tu64 pad1;\n\tu64 addr3;\n\tint error;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_short_write {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu64 fpos;\n\tu64 wanted;\n\tu64 got;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_req {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tbool sq_thread;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_work_run {\n\tstruct trace_entry ent;\n\tvoid *tctx;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_add_to_ioend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 pos;\n\tu64 dirty_len;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tint ki_flags;\n\tbool aio;\n\tint error;\n\tssize_t ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_rw_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tsize_t count;\n\tsize_t done_before;\n\tint ki_flags;\n\tunsigned int dio_flags;\n\tbool aio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_iter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t pos;\n\tu64 length;\n\tint status;\n\tunsigned int flags;\n\tconst void *ops;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t size;\n\tloff_t offset;\n\tu64 length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_handler {\n\tstruct trace_entry ent;\n\tconst char *reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_raise {\n\tstruct trace_entry ent;\n\tu32 __data_loc_target_cpus;\n\tconst char *reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpumask {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int chp_time;\n\t__u32 forced_to_close;\n\t__u32 written;\n\t__u32 dropped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_end_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\ttid_t head;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_extend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint buffer_credits;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_start_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint interval;\n\tint sync;\n\tint requested_blocks;\n\tint dirtied_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_journal_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_lock_buffer_stall {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int stall_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_run_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int wait;\n\tlong unsigned int request_delay;\n\tlong unsigned int running;\n\tlong unsigned int locked;\n\tlong unsigned int flushing;\n\tlong unsigned int logging;\n\t__u32 handle_count;\n\t__u32 blocks;\n\t__u32 blocks_logged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_checkpoint_list {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t first_tid;\n\ttid_t tid;\n\ttid_t last_tid;\n\tlong unsigned int nr_freed;\n\ttid_t next_tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_shrunk;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_submit_inode_data {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_update_log_tail {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tail_sequence;\n\ttid_t first_tid;\n\tlong unsigned int block_nr;\n\tlong unsigned int freed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_write_superblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tblk_opf_t write_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tvoid *rx_sk;\n\tshort unsigned int protocol;\n\tenum skb_drop_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmalloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tbool accounted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_advisor {\n\tstruct trace_entry ent;\n\ts64 scan_time;\n\tlong unsigned int pages_to_scan;\n\tunsigned int cpu_percent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_enter_exit_template {\n\tstruct trace_entry ent;\n\tvoid *mm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_merge_one_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_merge_with_ksm_page {\n\tstruct trace_entry ent;\n\tvoid *ksm_page;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_remove_ksm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_remove_rmap_item {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_scan_template {\n\tstruct trace_entry ent;\n\tint seq;\n\tu32 rmap_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_access_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int ipa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_ack_irq {\n\tstruct trace_entry ent;\n\tunsigned int irqchip;\n\tunsigned int pin;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_age_hva {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_arm_set_dreg32 {\n\tstruct trace_entry ent;\n\tconst char *name;\n\t__u64 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_dirty_ring_exit {\n\tstruct trace_entry ent;\n\tint vcpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_dirty_ring_push {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 dirty_index;\n\tu32 reset_index;\n\tu32 slot;\n\tu64 offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_dirty_ring_reset {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 dirty_index;\n\tu32 reset_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_exit {\n\tstruct trace_entry ent;\n\tint ret;\n\tunsigned int esr_ec;\n\tlong unsigned int vcpu_pc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_forward_sysreg_trap {\n\tstruct trace_entry ent;\n\tu64 pc;\n\tu32 sysreg;\n\tbool is_read;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_fpu {\n\tstruct trace_entry ent;\n\tu32 load;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_get_timer_map {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_id;\n\tint direct_vtimer;\n\tint direct_ptimer;\n\tint emul_vtimer;\n\tint emul_ptimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_guest_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tlong unsigned int hsr;\n\tlong unsigned int hxfar;\n\tlong long unsigned int ipa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int vcpu_id;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_handle_sys_reg {\n\tstruct trace_entry ent;\n\tlong unsigned int hsr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_hvc_arm64 {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tlong unsigned int r0;\n\tlong unsigned int imm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_inject_nested_exception {\n\tstruct trace_entry ent;\n\tstruct kvm_vcpu *vcpu;\n\tlong unsigned int esr_el2;\n\tint type;\n\tlong unsigned int spsr_el2;\n\tlong unsigned int pc;\n\tlong unsigned int source_mode;\n\tlong unsigned int hcr_el2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_irq_line {\n\tstruct trace_entry ent;\n\tunsigned int type;\n\tint vcpu_idx;\n\tint irq_num;\n\tint level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmio {\n\tstruct trace_entry ent;\n\tu32 type;\n\tu32 len;\n\tu64 gpa;\n\tu64 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmio_emulate {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tlong unsigned int instr;\n\tlong unsigned int cpsr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_mmio_nisv {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tlong unsigned int esr;\n\tlong unsigned int far;\n\tlong unsigned int ipa;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_nested_eret {\n\tstruct trace_entry ent;\n\tstruct kvm_vcpu *vcpu;\n\tlong unsigned int elr_el2;\n\tlong unsigned int spsr_el2;\n\tlong unsigned int target_mode;\n\tlong unsigned int hcr_el2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_set_guest_debug {\n\tstruct trace_entry ent;\n\tstruct kvm_vcpu *vcpu;\n\t__u32 guest_debug;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_set_irq {\n\tstruct trace_entry ent;\n\tunsigned int gsi;\n\tint level;\n\tint irq_source_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_set_way_flush {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tbool cache;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_sys_access {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tbool is_write;\n\tconst char *name;\n\tu8 Op0;\n\tu8 Op1;\n\tu8 CRn;\n\tu8 CRm;\n\tu8 Op2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_test_age_hva {\n\tstruct trace_entry ent;\n\tlong unsigned int hva;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_timer_emulate {\n\tstruct trace_entry ent;\n\tint timer_idx;\n\tbool should_fire;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_timer_hrtimer_expire {\n\tstruct trace_entry ent;\n\tint timer_idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_timer_restore_state {\n\tstruct trace_entry ent;\n\tlong unsigned int ctl;\n\tlong long unsigned int cval;\n\tint timer_idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_timer_save_state {\n\tstruct trace_entry ent;\n\tlong unsigned int ctl;\n\tlong long unsigned int cval;\n\tint timer_idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_timer_update_irq {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_id;\n\t__u32 irq;\n\tint level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_toggle_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tbool was;\n\tbool now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_unmap_hva_range {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_userspace_exit {\n\tstruct trace_entry ent;\n\t__u32 reason;\n\tint errno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_vcpu_wakeup {\n\tstruct trace_entry ent;\n\t__u64 ns;\n\tbool waited;\n\tbool valid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kvm_wfx_arm64 {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_pc;\n\tbool is_wfe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_op {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_read {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_write {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tlong unsigned int piv;\n\tvoid *val;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tu32 __data_loc_comm;\n\tlong unsigned int total_vm;\n\tlong unsigned int anon_rss;\n\tlong unsigned int file_rss;\n\tlong unsigned int shmem_rss;\n\tuid_t uid;\n\tlong unsigned int pgtables;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mc_event {\n\tstruct trace_entry ent;\n\tunsigned int error_type;\n\tu32 __data_loc_msg;\n\tu32 __data_loc_label;\n\tu16 error_count;\n\tu8 mc_index;\n\ts8 top_layer;\n\ts8 middle_layer;\n\ts8 lower_layer;\n\tlong int address;\n\tu8 grain_bits;\n\tlong int syndrome;\n\tu32 __data_loc_driver_detail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mdio_access {\n\tstruct trace_entry ent;\n\tchar busid[61];\n\tchar read;\n\tu8 addr;\n\tu16 val;\n\tunsigned int regnum;\n\tchar __data[0];\n};\n\nstruct xdp_mem_allocator;\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_flush_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\ts64 stats_updates;\n\tbool force;\n\tbool needs_flush;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_events {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tlong unsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memory_failure_event {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint type;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pmd {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pte {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_calculate_totalreserve_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int totalreserve_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tint isolated;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page_isolate {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint none_or_zero;\n\tint referenced;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page_swapin {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tint swapped_in;\n\tint referenced;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tunsigned char order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache_range {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int last_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_collapse_file {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int hpfn;\n\tlong unsigned int index;\n\tlong unsigned int addr;\n\tbool is_shmem;\n\tu32 __data_loc_filename;\n\tint nr;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_scan_file {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tu32 __data_loc_filename;\n\tint present;\n\tint swap;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_scan_pmd {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tint referenced;\n\tint none_or_zero;\n\tint status;\n\tint unmapped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tenum lru_list lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tlong unsigned int thp_succeeded;\n\tlong unsigned int thp_failed;\n\tlong unsigned int thp_split;\n\tlong unsigned int large_folio_split;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages_start {\n\tstruct trace_entry ent;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tint percpu_refill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tlong unsigned int gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_lowmem_reserve {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tu32 __data_loc_upper_name;\n\tlong int lowmem_reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_wmarks {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tlong unsigned int watermark_min;\n\tlong unsigned int watermark_low;\n\tlong unsigned int watermark_high;\n\tlong unsigned int watermark_promo;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tlong unsigned int gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_clear_hopeless {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_reclaim_fail {\n\tstruct trace_entry ent;\n\tint nid;\n\tint failures;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_reclaim_pages {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_throttled {\n\tstruct trace_entry ent;\n\tint nid;\n\tint usec_timeout;\n\tint usec_delayed;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_write_folio {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock_acquire_returned {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tbool success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmc_request_done {\n\tstruct trace_entry ent;\n\tu32 cmd_opcode;\n\tint cmd_err;\n\tu32 cmd_resp[4];\n\tunsigned int cmd_retries;\n\tu32 stop_opcode;\n\tint stop_err;\n\tu32 stop_resp[4];\n\tunsigned int stop_retries;\n\tu32 sbc_opcode;\n\tint sbc_err;\n\tu32 sbc_resp[4];\n\tunsigned int sbc_retries;\n\tunsigned int bytes_xfered;\n\tint data_err;\n\tint tag;\n\tunsigned int can_retune;\n\tunsigned int doing_retune;\n\tunsigned int retune_now;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct mmc_request *mrq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmc_request_start {\n\tstruct trace_entry ent;\n\tu32 cmd_opcode;\n\tu32 cmd_arg;\n\tunsigned int cmd_flags;\n\tunsigned int cmd_retries;\n\tu32 stop_opcode;\n\tu32 stop_arg;\n\tunsigned int stop_flags;\n\tunsigned int stop_retries;\n\tu32 sbc_opcode;\n\tu32 sbc_arg;\n\tunsigned int sbc_flags;\n\tunsigned int sbc_retries;\n\tunsigned int blocks;\n\tunsigned int blk_addr;\n\tunsigned int blksz;\n\tunsigned int data_flags;\n\tint tag;\n\tunsigned int can_retune;\n\tunsigned int doing_retune;\n\tunsigned int retune_now;\n\tint need_retune;\n\tint hold_retune;\n\tunsigned int retune_period;\n\tstruct mmc_request *mrq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_log {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_log_ep {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int type;\n\tunsigned int slot;\n\tunsigned int maxp;\n\tunsigned int mult;\n\tunsigned int maxburst;\n\tunsigned int flags;\n\tunsigned int direction;\n\tstruct mtu3_gpd_ring *gpd_ring;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_log_gpd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tstruct qmu_gpd *gpd;\n\tu32 dw0;\n\tu32 dw1;\n\tu32 dw2;\n\tu32 dw3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_log_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tstruct mtu3_request *mreq;\n\tstruct qmu_gpd *gpd;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tint zero;\n\tint no_interrupt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_log_setup {\n\tstruct trace_entry ent;\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_qmu_isr {\n\tstruct trace_entry ent;\n\tu32 done_intr;\n\tu32 exp_intr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_u2_common_isr {\n\tstruct trace_entry ent;\n\tu32 intr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mtu3_u3_ltssm_isr {\n\tstruct trace_entry ent;\n\tu32 intr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_isr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu8 int_usb;\n\tu16 int_tx;\n\tu16 int_rx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_log {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_regb {\n\tstruct trace_entry ent;\n\tvoid *caller;\n\tconst void *addr;\n\tunsigned int offset;\n\tu8 data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_regl {\n\tstruct trace_entry ent;\n\tvoid *caller;\n\tconst void *addr;\n\tunsigned int offset;\n\tu32 data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_regw {\n\tstruct trace_entry ent;\n\tvoid *caller;\n\tconst void *addr;\n\tunsigned int offset;\n\tu16 data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_req {\n\tstruct trace_entry ent;\n\tstruct usb_request *req;\n\tu8 is_tx;\n\tu8 epnum;\n\tint status;\n\tunsigned int buf_len;\n\tunsigned int actual_len;\n\tunsigned int zero;\n\tunsigned int short_not_ok;\n\tunsigned int no_interrupt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_state {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu8 devctl;\n\tu32 __data_loc_desc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_musb_urb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tstruct urb *urb;\n\tunsigned int pipe;\n\tint status;\n\tunsigned int flag;\n\tu32 buf_len;\n\tu32 actual_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int len;\n\tlong long unsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_folio {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tlong unsigned int index;\n\tlong long unsigned int fend;\n\tlong long unsigned int cleaned_to;\n\tlong long unsigned int collected_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_gap {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tunsigned char type;\n\tlong long unsigned int from;\n\tlong long unsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_sreq {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int subreq;\n\tunsigned int stream;\n\tunsigned int len;\n\tunsigned int transferred;\n\tlong long unsigned int start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_state {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int notes;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int cleaned_to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_collect_stream {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned char stream;\n\tlong long unsigned int collected_to;\n\tlong long unsigned int front;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_copy2cache {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int creq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_failure {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_failure what;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folio {\n\tstruct trace_entry ent;\n\tino_t ino;\n\tlong unsigned int index;\n\tunsigned int nr;\n\tenum netfs_folio_trace why;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_folioq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int id;\n\tenum netfs_folioq_trace trace;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_read {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int cookie;\n\tloff_t i_size;\n\tloff_t start;\n\tsize_t len;\n\tenum netfs_read_trace what;\n\tunsigned int netfs_inode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int flags;\n\tenum netfs_io_origin origin;\n\tenum netfs_rreq_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_rreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tint ref;\n\tenum netfs_rreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tshort unsigned int index;\n\tshort int error;\n\tshort unsigned int flags;\n\tenum netfs_io_source source;\n\tenum netfs_sreq_trace what;\n\tu8 slot;\n\tsize_t len;\n\tsize_t transferred;\n\tloff_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_sreq_ref {\n\tstruct trace_entry ent;\n\tunsigned int rreq;\n\tunsigned int subreq;\n\tint ref;\n\tenum netfs_sreq_ref_trace what;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write {\n\tstruct trace_entry ent;\n\tunsigned int wreq;\n\tunsigned int cookie;\n\tunsigned int ino;\n\tenum netfs_write_trace what;\n\tlong long unsigned int start;\n\tlong long unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netfs_write_iter {\n\tstruct trace_entry ent;\n\tlong long unsigned int start;\n\tsize_t len;\n\tunsigned int flags;\n\tunsigned int ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netlink_extack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cached_open {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_error_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 cbident;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_offload {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tloff_t cb_count;\n\tint cb_how;\n\tint cb_stateid_seq;\n\tu32 cb_stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_seqid_err {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clientid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clone {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 src_fhandle;\n\tu32 src_fileid;\n\tu32 dst_fhandle;\n\tu32 dst_fileid;\n\tdev_t src_dev;\n\tdev_t dst_dev;\n\tloff_t src_offset;\n\tloff_t dst_offset;\n\tint src_stateid_seq;\n\tu32 src_stateid_hash;\n\tint dst_stateid_seq;\n\tu32 dst_stateid_hash;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_close {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_commit_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tloff_t offset;\n\tu32 count;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_copy {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 src_fhandle;\n\tu32 src_fileid;\n\tu32 dst_fhandle;\n\tu32 dst_fileid;\n\tdev_t src_dev;\n\tdev_t dst_dev;\n\tint src_stateid_seq;\n\tu32 src_stateid_hash;\n\tint dst_stateid_seq;\n\tu32 dst_stateid_hash;\n\tloff_t src_offset;\n\tloff_t dst_offset;\n\tbool sync;\n\tloff_t len;\n\tint res_stateid_seq;\n\tu32 res_stateid_hash;\n\tloff_t res_count;\n\tbool res_sync;\n\tbool res_cons;\n\tbool intra;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_copy_notify {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tu32 fileid;\n\tdev_t dev;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint res_stateid_seq;\n\tu32 res_stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegation_event {\n\tstruct trace_entry ent;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegreturn_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_status {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint status;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_flexfiles_io_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_getattr_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int valid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_idmap_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 id;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_layoutget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 iomode;\n\tu64 offset;\n\tu64 count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_llseek {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tu32 fileid;\n\tdev_t dev;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tloff_t offset_s;\n\tu32 what;\n\tloff_t offset_r;\n\tu32 eof;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lock_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookup_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookupp {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_match_stateid_event {\n\tstruct trace_entry ent;\n\tint s1_seq;\n\tint s2_seq;\n\tu32 s1_hash;\n\tu32 s2_hash;\n\tint s1_type;\n\tint s2_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_offload_class {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_open_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint openstateid_seq;\n\tu32 openstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_read_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 olddir;\n\tu32 __data_loc_oldname;\n\tu64 newdir;\n\tu32 __data_loc_newname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_sequence_done {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int target_highest_slotid;\n\tlong unsigned int status_flags;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_delegation_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_lock {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint lockstateid_seq;\n\tu32 lockstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_setup_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_used_slotid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_sparse_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tloff_t offset;\n\tloff_t len;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_lock_reclaim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int state_flags;\n\tlong unsigned int lock_flags;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr_failed {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tu32 __data_loc_section;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_test_stateid_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_trunked_exchange_id {\n\tstruct trace_entry ent;\n\tu32 __data_loc_main_addr;\n\tu32 __data_loc_trunk_addr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_write_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xattr_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_bad_operation {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tu32 expected;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_access_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tunsigned int mask;\n\tunsigned int permitted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_commit_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_direct_req_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t offset;\n\tssize_t count;\n\tssize_t error;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_fh_to_dentry {\n\tstruct trace_entry ent;\n\tint error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_read {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_write {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tlong unsigned int stable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_range_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t range_start;\n\tloff_t range_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_kiocb_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_local_open_fh {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_assign {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tu32 __data_loc_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_option {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_path {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tconst struct nfs_page *req;\n\tloff_t offset;\n\tunsigned int count;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tunsigned int count;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_pgio_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tloff_t pos;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readdir_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tchar verifier[8];\n\tu64 cookie;\n\tlong unsigned int index;\n\tunsigned int dtsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_short {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 old_dir;\n\tu64 new_dir;\n\tu32 __data_loc_old_name;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 old_dir;\n\tu32 __data_loc_old_name;\n\tu64 new_dir;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_sillyrename_unlink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_update_size_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t cur_size;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_writeback_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tlong unsigned int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nlmclnt_lock_event {\n\tstruct trace_entry ent;\n\tu32 oh;\n\tu32 svid;\n\tu32 fh;\n\tlong unsigned int status;\n\tu64 start;\n\tu64 len;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_non_standard_event {\n\tstruct trace_entry ent;\n\tchar sec_type[16];\n\tchar fru_id[16];\n\tu32 __data_loc_fru_text;\n\tu8 sev;\n\tu32 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_notifier_info {\n\tstruct trace_entry ent;\n\tvoid *cb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_optee_invoke_fn_begin {\n\tstruct trace_entry ent;\n\tvoid *param;\n\tu32 args[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_optee_invoke_fn_end {\n\tstruct trace_entry ent;\n\tvoid *param;\n\tlong unsigned int rets[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_op {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n\tlong unsigned int req_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_order {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_unbounded {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int nr_to_read;\n\tlong unsigned int lookahead_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\ts32 inflight;\n\tu32 hold;\n\tu32 release;\n\tu64 cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_hold {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 hold;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 release;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_update_nid {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tint pool_nid;\n\tint new_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pci_hp_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tu32 __data_loc_slot;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pcie_link_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tunsigned int type;\n\tunsigned int reason;\n\tunsigned int cur_bus_speed;\n\tunsigned int max_bus_speed;\n\tunsigned int width;\n\tunsigned int flit_mode;\n\tunsigned int link_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pmap_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_err_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tlong unsigned int status;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_ds_connect {\n\tstruct trace_entry ent;\n\tu32 __data_loc_ds_ips;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_layout_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_update_layout {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tenum pnfs_update_layout_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_psci_domain_idle {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool s2idle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_purge_vmap_area_lazy {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int npurged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tu64 period;\n\tu64 duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_read_waveform {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tvoid *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_round_waveform_fromhw {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tconst void *wfhw;\n\tu64 wf_period_length_ns;\n\tu64 wf_duty_length_ns;\n\tu64 wf_duty_offset_ns;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_round_waveform_tohw {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tu64 wf_period_length_ns;\n\tu64 wf_duty_length_ns;\n\tu64 wf_duty_offset_ns;\n\tvoid *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pwm_write_waveform {\n\tstruct trace_entry ent;\n\tunsigned int chipid;\n\tunsigned int hwpwm;\n\tconst void *wfhw;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_close {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_close_ack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_intent {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tu32 count;\n\tu32 size;\n\tu32 liid;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_open {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_open_ack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_read_notif {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_rx_done {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tu32 iid;\n\tbool reuse;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_rx_intent_req {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tu32 size;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_rx_intent_req_ack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tbool granted;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_signal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tu32 signals;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_tx_data {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 __data_loc_channel;\n\tu16 lcid;\n\tu16 rcid;\n\tu32 iid;\n\tu32 chunk_size;\n\tu32 left_size;\n\tbool cont;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_version {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 version;\n\tu32 features;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qcom_glink_cmd_version_ack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_remote;\n\tu32 version;\n\tu32 features;\n\tbool tx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_enqueue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kvfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_segcb_stats {\n\tstruct trace_entry ent;\n\tconst char *ctx;\n\tlong unsigned int gp_seq[4];\n\tlong int seglen[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_sr_normal {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tconst char *srevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_stall_warning {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_watching {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint counter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_drop_region {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int from;\n\tunsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_sync {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_status;\n\tu32 __data_loc_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_register_class {\n\tstruct trace_entry ent;\n\tu32 version;\n\tlong unsigned int family;\n\tshort unsigned int protocol;\n\tshort unsigned int port;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_async {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_block {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bool {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bulk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tu32 __data_loc_buf;\n\tint val_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_reg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_basic {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_range {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint min;\n\tint max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regulator_value {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_buf_alloc {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tsize_t callsize;\n\tsize_t recvsize;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_call_rpcerror {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint tk_status;\n\tint rpc_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_class {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_clone_err {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tlong unsigned int xprtsec;\n\tlong unsigned int flags;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new_err {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_failure {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_reply_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 __data_loc_progname;\n\tu32 version;\n\tu32 __data_loc_procname;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_request {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tbool async;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_socket_nospace {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int total;\n\tunsigned int remaining;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_stats_latency {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tlong unsigned int backlog;\n\tlong unsigned int rtt;\n\tlong unsigned int execute;\n\tu32 xprt_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_queued {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tlong unsigned int timeout;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tu32 __data_loc_q_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_running {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *action;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_tls_class {\n\tstruct trace_entry ent;\n\tlong unsigned int requested_policy;\n\tu32 version;\n\tu32 __data_loc_servername;\n\tu32 __data_loc_progname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_alignment {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t offset;\n\tunsigned int copied;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_overflow {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t requested;\n\tconst void *end;\n\tconst void *p;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_lifetime_class {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_getport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int bind_version;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_setport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tshort unsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_unregister {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_bad_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 expected;\n\tu32 received;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_context {\n\tstruct trace_entry ent;\n\tlong unsigned int expiry;\n\tlong unsigned int now;\n\tunsigned int timeout;\n\tu32 window_size;\n\tint len;\n\tu32 __data_loc_acceptor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_createauth {\n\tstruct trace_entry ent;\n\tunsigned int flavor;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_ctx_class {\n\tstruct trace_entry ent;\n\tconst void *cred;\n\tlong unsigned int service;\n\tu32 __data_loc_principal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_gssapi_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 maj_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_import_ctx {\n\tstruct trace_entry ent;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_need_reencode {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seq_xmit;\n\tu32 seqno;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_oid_to_mech {\n\tstruct trace_entry ent;\n\tu32 __data_loc_oid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_accept_upcall {\n\tstruct trace_entry ent;\n\tu32 minor_status;\n\tlong unsigned int major_status;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 seqno;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_gssapi_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 maj_stat;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_bad {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_low {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_unwrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_wrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_unwrap_failed {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_result {\n\tstruct trace_entry ent;\n\tu32 uid;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_update_slack {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tconst void *auth;\n\tunsigned int rslack;\n\tunsigned int ralign;\n\tunsigned int verfsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_internal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flags;\n\tint usage_count;\n\tint disable_depth;\n\tint runtime_auto;\n\tint request_pending;\n\tint irq_safe;\n\tint child_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_return_int {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int ip;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpmh_send_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint m;\n\tu32 state;\n\tint n;\n\tu32 hdr;\n\tu32 addr;\n\tu32 data;\n\tbool wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpmh_tx_done {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint m;\n\tu32 addr;\n\tu32 data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\ts32 node_id;\n\ts32 mm_cid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_alarm_irq_enable {\n\tstruct trace_entry ent;\n\tunsigned int enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_freq {\n\tstruct trace_entry ent;\n\tint freq;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_state {\n\tstruct trace_entry ent;\n\tint enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_offset_class {\n\tstruct trace_entry ent;\n\tlong int offset;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_time_alarm_class {\n\tstruct trace_entry ent;\n\ttime64_t secs;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_timer_class {\n\tstruct trace_entry ent;\n\tstruct rtc_timer *timer;\n\tktime_t expires;\n\tktime_t period;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_bypass_lb {\n\tstruct trace_entry ent;\n\t__u32 node;\n\t__u32 nr_cpus;\n\t__u32 nr_tasks;\n\t__u32 nr_balanced;\n\t__u32 before_min;\n\t__u32 before_max;\n\t__u32 after_min;\n\t__u32 after_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_dump {\n\tstruct trace_entry ent;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\t__s64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *worker;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_move_numa {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_numa_pair_template {\n\tstruct trace_entry ent;\n\tpid_t src_pid;\n\tpid_t src_tgid;\n\tpid_t src_ngid;\n\tint src_cpu;\n\tint src_nid;\n\tpid_t dst_pid;\n\tpid_t dst_tgid;\n\tpid_t dst_ngid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_prepare_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_interp;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exit {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tbool group_dead;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tu32 __data_loc_parent_comm;\n\tpid_t parent_pid;\n\tu32 __data_loc_child_comm;\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_cpuset_numa {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tlong unsigned int mem_allowed[1];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_vma_numa {\n\tstruct trace_entry ent;\n\tlong unsigned int numa_scan_offset;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tenum numa_vmaskip_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 runtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_fc_call {\n\tstruct trace_entry ent;\n\tu8 protocol_id;\n\tu8 msg_id;\n\tu32 res_id;\n\tu32 val1;\n\tu32 val2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_msg_dump {\n\tstruct trace_entry ent;\n\tint id;\n\tu8 channel_id;\n\tu8 protocol_id;\n\tu8 msg_id;\n\tchar tag[6];\n\tu16 seq;\n\tint status;\n\tsize_t len;\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_rx_done {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tu8 msg_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_xfer_begin {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tbool poll;\n\tint inflight;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_xfer_end {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tint status;\n\tint inflight;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scmi_xfer_response_wait {\n\tstruct trace_entry ent;\n\tint transfer_id;\n\tu8 msg_id;\n\tu8 protocol_id;\n\tu16 seq;\n\tu32 timeout;\n\tbool poll;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sk_data_ready {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 family;\n\t__u16 protocol;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 flags;\n\t__u16 addr;\n\t__u8 command;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 read_write;\n\t__u8 command;\n\t__s16 res;\n\t__u32 protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_negotiate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 out_features;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_notify_in {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_client_name;\n\tlong unsigned int status;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_ssr_ack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smp2p_update_bits {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_client_name;\n\tu32 orig;\n\tu32 val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int sysctl_mem[3];\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_msg_length {\n\tstruct trace_entry ent;\n\tvoid *sk;\n\t__u16 family;\n\t__u16 protocol;\n\tint ret;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_controller {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_mem_start_op {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_op;\n\tu32 __data_loc_data;\n\tu32 data_len;\n\tu32 max_freq;\n\tu8 cmd_buswidth;\n\tbool cmd_dtr;\n\tu8 addr_buswidth;\n\tbool addr_dtr;\n\tu8 dummy_nbytes;\n\tu8 data_buswidth;\n\tbool data_dtr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_mem_stop_op {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_data;\n\tu32 data_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_message {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_message *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_message_done {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_message *msg;\n\tunsigned int frame;\n\tunsigned int actual;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_set_cs {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tlong unsigned int mode;\n\tbool enable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_setup {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tlong unsigned int mode;\n\tunsigned int bits_per_word;\n\tunsigned int max_speed_hz;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spi_transfer {\n\tstruct trace_entry ent;\n\tint bus_num;\n\tint chip_select;\n\tstruct spi_transfer *xfer;\n\tint len;\n\tu32 __data_loc_rx_buf;\n\tu32 __data_loc_tx_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_cmd {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_read_begin {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_read_end {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tint ret;\n\tu8 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_write_begin {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tu8 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_spmi_write_end {\n\tstruct trace_entry ent;\n\tu8 opcode;\n\tu8 sid;\n\tu16 addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_alloc_arg_err {\n\tstruct trace_entry ent;\n\tunsigned int requested;\n\tunsigned int allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int svc_status;\n\tlong unsigned int auth_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_deferred_event {\n\tstruct trace_entry ent;\n\tconst void *dr;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_pool_thread_event {\n\tstruct trace_entry ent;\n\tunsigned int pool_id;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_process {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 vers;\n\tu32 proc;\n\tu32 __data_loc_service;\n\tu32 __data_loc_procedure;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_replace_page_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tconst void *begin;\n\tconst void *respages;\n\tconst void *nextpage;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tint status;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_stats_latency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int execute;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_unregister {\n\tstruct trace_entry ent;\n\tu32 version;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_msg_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_accept {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_service;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_create_err {\n\tstruct trace_entry ent;\n\tlong int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_dequeue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tlong unsigned int wakeup;\n\tlong unsigned int qtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_enqueue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_accept_class {\n\tstruct trace_entry ent;\n\tlong int status;\n\tu32 __data_loc_service;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_class {\n\tstruct trace_entry ent;\n\tssize_t result;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_lifetime_class {\n\tstruct trace_entry ent;\n\tunsigned int netns_ino;\n\tconst void *svsk;\n\tconst void *sk;\n\tlong unsigned int type;\n\tlong unsigned int family;\n\tlong unsigned int state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_marker {\n\tstruct trace_entry ent;\n\tunsigned int length;\n\tbool last;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_recv_short {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_state {\n\tstruct trace_entry ent;\n\tlong unsigned int socket_state;\n\tlong unsigned int sock_state;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_swiotlb_bounced {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu64 dma_mask;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tbool force;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tu64 clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_prctl_unknown {\n\tstruct trace_entry ent;\n\tint option;\n\tlong unsigned int arg2;\n\tlong unsigned int arg3;\n\tlong unsigned int arg4;\n\tlong unsigned int arg5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tasklet {\n\tstruct trace_entry ent;\n\tvoid *tasklet;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_ao_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\t__u8 keyid;\n\t__u8 rnext;\n\t__u8 maclen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_cong_state_set {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u8 cong_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_hash_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\t__u64 sock_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_ssthresh;\n\t__u32 window_clamp;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_send_reset {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\tenum sk_rst_reason reason;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_sendmsg_locked {\n\tstruct trace_entry ent;\n\tconst void *skb_addr;\n\tint skb_len;\n\tint msg_left;\n\tint size_goal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tegra_dma_complete_cb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_chan;\n\tint count;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tegra_dma_isr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_chan;\n\tint irq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tegra_dma_tx_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_chan;\n\tdma_cookie_t cookie;\n\t__u32 residue;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_test_pages_isolated {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int fin_pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_actor {\n\tstruct trace_entry ent;\n\tint tz_id;\n\tint actor_id;\n\tu32 req_power;\n\tu32 granted_power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_allocator {\n\tstruct trace_entry ent;\n\tint tz_id;\n\tu32 total_req_power;\n\tu32 total_granted_power;\n\tsize_t num_actors;\n\tu32 power_range;\n\tu32 max_allocatable_power;\n\tint current_temp;\n\ts32 delta_temp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_allocator_pid {\n\tstruct trace_entry ent;\n\tint tz_id;\n\ts32 err;\n\ts32 err_integral;\n\ts64 p;\n\ts64 i;\n\ts64 d;\n\ts32 output;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_cpu_get_power_simple {\n\tstruct trace_entry ent;\n\tint cpu;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_cpu_limit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tunsigned int freq;\n\tlong unsigned int cdev_state;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_devfreq_get_power {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int freq;\n\tu32 busy_time;\n\tu32 total_time;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_power_devfreq_limit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tunsigned int freq;\n\tlong unsigned int cdev_state;\n\tu32 power;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_temperature {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint temp_prev;\n\tint temp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_zone_trip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint trip;\n\tenum thermal_trip_type trip_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_base_idle {\n\tstruct trace_entry ent;\n\tbool is_idle;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int bucket_expiry;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tls_contenttype {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_child_parent {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_cpu_parent {\n\tstruct trace_entry ent;\n\tvoid *parent;\n\tunsigned int cpu;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_cpugroup {\n\tstruct trace_entry ent;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_and_cpu {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tu32 childmask;\n\tu8 active;\n\tu8 migrator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_set {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_handle_remote {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_idle {\n\tstruct trace_entry ent;\n\tu64 nextevt;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_update_events {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *group;\n\tu64 nextevt;\n\tu64 group_next_expiry;\n\tu64 child_evt_expiry;\n\tunsigned int group_lvl;\n\tunsigned int child_evtcpu;\n\tu8 child_active;\n\tu8 group_active;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_track_foreign_dirty {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tu64 bdi_id;\n\tino_t ino;\n\tunsigned int memcg_id;\n\tino_t cgroup_ino;\n\tino_t page_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udc_log_ep {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int maxpacket;\n\tunsigned int maxpacket_limit;\n\tunsigned int max_streams;\n\tunsigned int mult;\n\tunsigned int maxburst;\n\tu8 address;\n\tbool claimed;\n\tbool enabled;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udc_log_gadget {\n\tstruct trace_entry ent;\n\tenum usb_device_speed speed;\n\tenum usb_device_speed max_speed;\n\tenum usb_device_state state;\n\tunsigned int mA;\n\tunsigned int sg_supported;\n\tunsigned int is_otg;\n\tunsigned int is_a_peripheral;\n\tunsigned int b_hnp_enable;\n\tunsigned int a_hnp_support;\n\tunsigned int hnp_polling_support;\n\tunsigned int host_request_flag;\n\tunsigned int quirk_ep_out_aligned_size;\n\tunsigned int quirk_altset_not_supp;\n\tunsigned int quirk_stall_not_supp;\n\tunsigned int quirk_zlp_not_supp;\n\tunsigned int is_selfpowered;\n\tunsigned int deactivated;\n\tunsigned int connected;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udc_log_req {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int length;\n\tunsigned int actual;\n\tunsigned int num_sgs;\n\tunsigned int num_mapped_sgs;\n\tunsigned int stream_id;\n\tunsigned int no_interrupt;\n\tunsigned int zero;\n\tunsigned int short_not_ok;\n\tint status;\n\tint ret;\n\tstruct usb_request *req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufs_mtk_clk_scale {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tbool scale_up;\n\tlong unsigned int clk_rate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufs_mtk_event {\n\tstruct trace_entry ent;\n\tunsigned int type;\n\tunsigned int data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_auto_bkops_state {\n\tstruct trace_entry ent;\n\tstruct ufs_hba *hba;\n\tu32 __data_loc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_clk_gating {\n\tstruct trace_entry ent;\n\tstruct ufs_hba *hba;\n\tint state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_clk_scaling {\n\tstruct trace_entry ent;\n\tstruct ufs_hba *hba;\n\tu32 __data_loc_state;\n\tu32 __data_loc_clk;\n\tu32 prev_state;\n\tu32 curr_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_command {\n\tstruct trace_entry ent;\n\tstruct scsi_device *sdev;\n\tstruct ufs_hba *hba;\n\tenum ufs_trace_str_t str_t;\n\tunsigned int tag;\n\tu32 doorbell;\n\tu32 hwq_id;\n\tu32 intr;\n\tu64 lba;\n\tint transfer_len;\n\tu8 opcode;\n\tu8 group_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_exception_event {\n\tstruct trace_entry ent;\n\tstruct ufs_hba *hba;\n\tu16 status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_profiling_template {\n\tstruct trace_entry ent;\n\tstruct ufs_hba *hba;\n\tu32 __data_loc_profile_info;\n\ts64 time_us;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_template {\n\tstruct trace_entry ent;\n\ts64 usecs;\n\tint err;\n\tstruct ufs_hba *hba;\n\tint dev_state;\n\tint link_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_uic_command {\n\tstruct trace_entry ent;\n\tstruct ufs_hba *hba;\n\tenum ufs_trace_str_t str_t;\n\tu32 cmd;\n\tu32 arg1;\n\tu32 arg2;\n\tu32 arg3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ufshcd_upiu {\n\tstruct trace_entry ent;\n\tstruct ufs_hba *hba;\n\tenum ufs_trace_str_t str_t;\n\tunsigned char hdr[12];\n\tunsigned char tsf[16];\n\tenum ufs_trace_tsf_t tsf_t;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_usb_core_log_usb_device {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum usb_device_speed speed;\n\tenum usb_device_state state;\n\tshort unsigned int bus_mA;\n\tunsigned int authorized;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vgic_update_irq_pending {\n\tstruct trace_entry ent;\n\tlong unsigned int vcpu_id;\n\t__u32 irq;\n\tbool level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_set_timeout {\n\tstruct trace_entry ent;\n\tint id;\n\tunsigned int timeout;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_watchdog_template {\n\tstruct trace_entry ent;\n\tint id;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tu32 __data_loc_workqueue;\n\tint req_cpu;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_folio_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tunsigned int xdp_pass;\n\tunsigned int xdp_drop;\n\tunsigned int xdp_redirect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_dbc_log_request {\n\tstruct trace_entry ent;\n\tstruct dbc_request *req;\n\tbool dir;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctrl_ctx {\n\tstruct trace_entry ent;\n\tu32 drop;\n\tu32 add;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctx {\n\tstruct trace_entry ent;\n\tint ctx_64;\n\tunsigned int ctx_type;\n\tdma_addr_t ctx_dma;\n\tu8 *ctx_va;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_doorbell {\n\tstruct trace_entry ent;\n\tu32 slot;\n\tu32 doorbell;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ep_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu64 deq;\n\tu32 tx_info;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_free_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint slot_id;\n\tu16 current_mel;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_portsc {\n\tstruct trace_entry ent;\n\tu32 busnum;\n\tu32 portnum;\n\tu32 portsc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ring {\n\tstruct trace_entry ent;\n\tu32 type;\n\tvoid *ring;\n\tdma_addr_t enq;\n\tdma_addr_t deq;\n\tunsigned int num_segs;\n\tunsigned int stream_id;\n\tunsigned int cycle_state;\n\tunsigned int bounce_buf_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_slot_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu32 tt_info;\n\tu32 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_stream_ctx {\n\tstruct trace_entry ent;\n\tunsigned int stream_id;\n\tu64 stream_ring;\n\tdma_addr_t ctx_array_dma;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_trb {\n\tstruct trace_entry ent;\n\tdma_addr_t dma;\n\tu32 type;\n\tu32 field0;\n\tu32 field1;\n\tu32 field2;\n\tu32 field3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_urb {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tvoid *urb;\n\tunsigned int pipe;\n\tunsigned int stream;\n\tint status;\n\tunsigned int flags;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tint length;\n\tint actual;\n\tint epnum;\n\tint dir_in;\n\tint type;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint devnum;\n\tint state;\n\tint speed;\n\tu8 portnum;\n\tu8 level;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_cong_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tbool wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_ping {\n\tstruct trace_entry ent;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_reserve {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_retransmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint ntrans;\n\tint version;\n\tlong unsigned int timeout;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_transmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_writelock_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_data_ready {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event {\n\tstruct trace_entry ent;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event_done {\n\tstruct trace_entry ent;\n\tint error;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_data {\n\tstruct trace_entry ent;\n\tssize_t err;\n\tsize_t total;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tu32 xid;\n\tlong unsigned int copied;\n\tunsigned int reclen;\n\tunsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n\tint flags;\n};\n\nstruct trace_func_repeats {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int count;\n\tu64 ts_last_call;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n};\n\nstruct trace_min_max_param {\n\tstruct mutex *lock;\n\tu64 *val;\n\tu64 *min;\n\tu64 *max;\n};\n\nstruct trace_mod_entry {\n\tlong unsigned int mod_addr;\n\tchar mod_name[56];\n};\n\nstruct trace_module_delta {\n\tstruct callback_head rcu;\n\tlong int delta[0];\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tbool fail;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nunion upper_chunk;\n\nstruct trace_pid_list {\n\tseqcount_raw_spinlock_t seqcount;\n\traw_spinlock_t lock;\n\tstruct irq_work refill_irqwork;\n\tunion upper_chunk *upper[256];\n\tunion upper_chunk *upper_list;\n\tunion lower_chunk *lower_list;\n\tint free_upper_chunks;\n\tint free_lower_chunks;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nstruct trace_scratch {\n\tunsigned int clock_id;\n\tlong unsigned int text_addr;\n\tlong unsigned int nr_entries;\n\tstruct trace_mod_entry entries[0];\n};\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct eventfs_inode *ei;\n\tint ref_count;\n\tint nr_events;\n};\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tchar *filename;\n\tstruct uprobe *uprobe;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int *nhits;\n\tstruct trace_probe tp;\n};\n\nstruct trace_user_buf {\n\tchar *buf;\n};\n\nstruct trace_user_buf_info {\n\tstruct trace_user_buf *tbuf;\n\tsize_t size;\n\tint ref;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct tracefs_inode {\n\tstruct inode vfs_inode;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tvoid *private;\n};\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct traceprobe_parse_context {\n\tstruct trace_event_call *event;\n\tconst char *funcname;\n\tconst struct btf_type *proto;\n\tconst struct btf_param *params;\n\ts32 nr_params;\n\tstruct btf *btf;\n\tconst struct btf_type *last_type;\n\tu32 last_bitoffs;\n\tu32 last_bitsize;\n\tstruct trace_probe *tp;\n\tunsigned int flags;\n\tint offset;\n};\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u64, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tstruct tracer_flags *default_flags;\n\tint enabled;\n\tbool print_max;\n\tbool allow_instances;\n\tbool noboot;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct tracers {\n\tstruct list_head list;\n\tstruct tracer *tracer;\n\tstruct tracer_flags *flags;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar *cmd;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tdepot_stack_handle_t handle;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct trans_pgd_info {\n\tvoid * (*trans_alloc_page)(void *);\n\tvoid *trans_alloc_arg;\n};\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n};\n\nstruct trap_bits {\n\tconst enum vcpu_sysreg index;\n\tconst enum trap_behaviour behaviour;\n\tconst u64 value;\n\tconst u64 mask;\n};\n\ntypedef struct tree_desc_s tree_desc;\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct uniphier_tm_dev;\n\nstruct trip_walk_data {\n\tstruct uniphier_tm_dev *tdev;\n\tint crit_temp;\n\tint index;\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsens_context {\n\tint threshold;\n\tint control;\n};\n\nstruct tsens_features {\n\tunsigned int ver_major;\n\tunsigned int crit_int: 1;\n\tunsigned int combo_int: 1;\n\tunsigned int adc: 1;\n\tunsigned int srot_split: 1;\n\tunsigned int has_watchdog: 1;\n\tunsigned int max_sensors;\n\tint trip_min_temp;\n\tint trip_max_temp;\n};\n\nstruct tsens_irq_data {\n\tu32 up_viol;\n\tint up_thresh;\n\tu32 up_irq_mask;\n\tu32 up_irq_clear;\n\tu32 low_viol;\n\tint low_thresh;\n\tu32 low_irq_mask;\n\tu32 low_irq_clear;\n\tu32 crit_viol;\n\tu32 crit_thresh;\n\tu32 crit_irq_mask;\n\tu32 crit_irq_clear;\n};\n\nstruct tsens_single_value {\n\tu8 idx;\n\tu8 shift;\n\tu8 blob;\n};\n\nstruct tsens_legacy_calibration_format {\n\tunsigned int base_len;\n\tunsigned int base_shift;\n\tunsigned int sp_len;\n\tstruct tsens_single_value mode;\n\tstruct tsens_single_value invalid;\n\tstruct tsens_single_value base[2];\n\tstruct tsens_single_value sp[0];\n};\n\nstruct tsens_priv;\n\nstruct tsens_sensor;\n\nstruct tsens_ops {\n\tint (*init)(struct tsens_priv *);\n\tint (*calibrate)(struct tsens_priv *);\n\tint (*get_temp)(const struct tsens_sensor *, int *);\n\tint (*enable)(struct tsens_priv *, int);\n\tvoid (*disable)(struct tsens_priv *);\n\tint (*suspend)(struct tsens_priv *);\n\tint (*resume)(struct tsens_priv *);\n};\n\nstruct tsens_plat_data {\n\tconst u32 num_sensors;\n\tconst struct tsens_ops *ops;\n\tunsigned int *hw_ids;\n\tstruct tsens_features *feat;\n\tconst struct reg_field *fields;\n};\n\nstruct tsens_sensor {\n\tstruct tsens_priv *priv;\n\tstruct thermal_zone_device *tzd;\n\tint offset;\n\tunsigned int hw_id;\n\tint slope;\n\tu32 status;\n\tint p1_calib_offset;\n\tint p2_calib_offset;\n};\n\nstruct tsens_priv {\n\tstruct device *dev;\n\tu32 num_sensors;\n\tstruct regmap *tm_map;\n\tstruct regmap *srot_map;\n\tu32 tm_offset;\n\tspinlock_t ul_lock;\n\tstruct regmap_field *rf[321];\n\tstruct tsens_context ctx;\n\tstruct tsens_features *feat;\n\tconst struct reg_field *fields;\n\tconst struct tsens_ops *ops;\n\tstruct dentry *debug_root;\n\tstruct dentry *debug;\n\tstruct tsens_sensor sensor[0];\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct tty_audit_buf {\n\tstruct mutex mutex;\n\tdev_t dev;\n\tbool icanon;\n\tsize_t valid;\n\tu8 *data;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct tun_struct;\n\nstruct tun_file {\n\tstruct sock sk;\n\tstruct socket socket;\n\tstruct tun_struct *tun;\n\tstruct fasync_struct *fasync;\n\tunsigned int flags;\n\tunion {\n\t\tu16 queue_index;\n\t\tunsigned int ifindex;\n\t};\n\tstruct napi_struct napi;\n\tbool napi_enabled;\n\tbool napi_frags_enabled;\n\tstruct mutex napi_mutex;\n\tstruct list_head next;\n\tstruct tun_struct *detached;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring tx_ring;\n\tstruct xdp_rxq_info xdp_rxq;\n};\n\nstruct tun_filter {\n\t__u16 flags;\n\t__u16 count;\n\t__u8 addr[0];\n};\n\nstruct tun_flow_entry {\n\tstruct hlist_node hash_link;\n\tstruct callback_head rcu;\n\tstruct tun_struct *tun;\n\tu32 rxhash;\n\tu32 rps_rxhash;\n\tint queue_index;\n\tlong: 64;\n\tlong unsigned int updated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tun_msg_ctl {\n\tshort unsigned int type;\n\tshort unsigned int num;\n\tvoid *ptr;\n};\n\nstruct tun_page {\n\tstruct page *page;\n\tint count;\n};\n\nstruct tun_pi {\n\t__u16 flags;\n\t__be16 proto;\n};\n\nstruct tun_prog {\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct tun_struct {\n\tstruct tun_file *tfiles[256];\n\tunsigned int numqueues;\n\tunsigned int flags;\n\tkuid_t owner;\n\tkgid_t group;\n\tstruct net_device *dev;\n\tnetdev_features_t set_features;\n\tint align;\n\tint vnet_hdr_sz;\n\tint sndbuf;\n\tstruct tap_filter txflt;\n\tstruct sock_fprog fprog;\n\tbool filter_attached;\n\tu32 msg_enable;\n\tspinlock_t lock;\n\tstruct hlist_head flows[1024];\n\tstruct timer_list flow_gc_timer;\n\tlong unsigned int ageing_time;\n\tunsigned int numdisabled;\n\tstruct list_head disabled;\n\tvoid *security;\n\tu32 flow_count;\n\tu32 rx_batched;\n\tatomic_long_t rx_frame_errors;\n\tstruct bpf_prog *xdp_prog;\n\tstruct tun_prog *steering_prog;\n\tstruct tun_prog *filter_prog;\n\tstruct ethtool_link_ksettings link_ksettings;\n\tstruct file *file;\n\tstruct ifreq *ifr;\n};\n\nstruct tx_ring_info {\n\tstruct sk_buff *skb;\n\tlong unsigned int flags;\n\tdma_addr_t mapaddr;\n\t__u32 maplen;\n};\n\nstruct typec_connector {\n\tvoid (*attach)(struct typec_connector *, struct device *);\n\tvoid (*deattach)(struct typec_connector *, struct device *);\n};\n\nstruct u32_fract {\n\t__u32 numerator;\n\t__u32 denominator;\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n};\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n\tvoid (*setup_timer)(struct uart_8250_port *);\n};\n\ntypedef struct uart_8250_port *class_serial8250_rpm_t;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tu16 bugs;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tu16 lsr_saved_flags;\n\tu16 lsr_save_mask;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *, bool);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *, bool);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct vendor_data___2;\n\nstruct uart_amba_port {\n\tstruct uart_port port;\n\tconst u16 *reg_offset;\n\tstruct clk *clk;\n\tconst struct vendor_data___2 *vendor;\n\tunsigned int im;\n\tunsigned int old_status;\n\tunsigned int fifosize;\n\tunsigned int fixed_baud;\n\tchar type[12];\n\tktime_t rs485_tx_drain_interval;\n\tenum pl011_rs485_tx_state rs485_tx_state;\n\tstruct hrtimer trigger_start_tx;\n\tstruct hrtimer trigger_stop_tx;\n\tbool console_line_ended;\n\tunsigned int dmacr;\n\tbool using_tx_dma;\n\tbool using_rx_dma;\n\tstruct pl011_dmarx_data dmarx;\n\tstruct pl011_dmatx_data dmatx;\n\tbool dma_probed;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*start_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\ntypedef struct uart_port *class_uart_port_lock_irq_t;\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct uc_string_id {\n\tu8 len;\n\tu8 type;\n\twchar_t uc[0];\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[12];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udc_ep_regs;\n\nstruct udc_stp_dma;\n\nstruct udc_data_dma;\n\nstruct udc_request;\n\nstruct udc;\n\nstruct udc_ep {\n\tstruct usb_ep ep;\n\tstruct udc_ep_regs *regs;\n\tu32 *txfifo;\n\tu32 *dma;\n\tdma_addr_t td_phys;\n\tdma_addr_t td_stp_dma;\n\tstruct udc_stp_dma *td_stp;\n\tstruct udc_data_dma *td;\n\tstruct udc_request *req;\n\tunsigned int req_used;\n\tunsigned int req_completed;\n\tstruct udc_request *bna_dummy_req;\n\tunsigned int bna_occurred;\n\tunsigned int naking;\n\tstruct udc *dev;\n\tstruct list_head queue;\n\tunsigned int halted;\n\tunsigned int cancel_transfer;\n\tunsigned int num: 5;\n\tunsigned int fifo_depth: 14;\n\tunsigned int in: 1;\n};\n\nstruct udc_csrs;\n\nstruct udc_regs;\n\nstruct udc {\n\tstruct usb_gadget gadget;\n\tspinlock_t lock;\n\tstruct udc_ep ep[32];\n\tstruct usb_gadget_driver *driver;\n\tunsigned int stall_ep0in: 1;\n\tunsigned int waiting_zlp_ack_ep0in: 1;\n\tunsigned int set_cfg_not_acked: 1;\n\tunsigned int data_ep_enabled: 1;\n\tunsigned int data_ep_queued: 1;\n\tunsigned int sys_suspended: 1;\n\tunsigned int connected;\n\tu16 chiprev;\n\tstruct pci_dev *pdev;\n\tstruct udc_csrs *csr;\n\tstruct udc_regs *regs;\n\tstruct udc_ep_regs *ep_regs;\n\tu32 *rxfifo;\n\tu32 *txfifo;\n\tstruct dma_pool *data_requests;\n\tstruct dma_pool *stp_requests;\n\tlong unsigned int phys_addr;\n\tvoid *virt_addr;\n\tunsigned int irq;\n\tu16 cur_config;\n\tu16 cur_intf;\n\tu16 cur_alt;\n\tstruct device *dev;\n\tstruct phy *udc_phy;\n\tstruct extcon_dev *edev;\n\tstruct extcon_specific_cable_nb extcon_nb;\n\tstruct notifier_block nb;\n\tstruct delayed_work drd_work;\n\tu32 conn_type;\n};\n\nstruct udc_csrs {\n\tu32 sca;\n\tu32 ne[9];\n};\n\nstruct udc_data_dma {\n\tu32 status;\n\tu32 _reserved;\n\tu32 bufptr;\n\tu32 next;\n};\n\nstruct udc_ep_regs {\n\tu32 ctl;\n\tu32 sts;\n\tu32 bufin_framenum;\n\tu32 bufout_maxpkt;\n\tu32 subptr;\n\tu32 desptr;\n\tu32 reserved;\n\tu32 confirm;\n};\n\nstruct udc_regs {\n\tu32 cfg;\n\tu32 ctl;\n\tu32 sts;\n\tu32 irqsts;\n\tu32 irqmsk;\n\tu32 ep_irqsts;\n\tu32 ep_irqmsk;\n};\n\nstruct udc_request {\n\tstruct usb_request req;\n\tunsigned int dma_going: 1;\n\tunsigned int dma_done: 1;\n\tdma_addr_t td_phys;\n\tstruct udc_data_dma *td_data;\n\tstruct udc_data_dma *td_data_last;\n\tstruct list_head queue;\n\tunsigned int chain_len;\n};\n\nunion udc_setup_data {\n\tu32 data[2];\n\tstruct usb_ctrlrequest request;\n};\n\nstruct udc_stp_dma {\n\tu32 status;\n\tu32 _reserved;\n\tu32 data12;\n\tu32 data34;\n};\n\nstruct udma_static_tr {\n\tu8 elsize;\n\tu16 elcnt;\n\tu16 bstcnt;\n};\n\nstruct udma_tx_drain {\n\tstruct delayed_work work;\n\tktime_t tstamp;\n\tu32 residue;\n};\n\nstruct udma_chan_config {\n\tbool pkt_mode;\n\tbool needs_epib;\n\tu32 psd_size;\n\tu32 metadata_size;\n\tu32 hdesc_size;\n\tbool notdpkt;\n\tint remote_thread_id;\n\tu32 atype;\n\tu32 asel;\n\tu32 src_thread;\n\tu32 dst_thread;\n\tenum psil_endpoint_type ep_type;\n\tbool enable_acc32;\n\tbool enable_burst;\n\tenum udma_tp_level channel_tpl;\n\tu32 tr_trigger_type;\n\tlong unsigned int tx_flags;\n\tint mapped_channel_id;\n\tint default_flow_id;\n\tenum dma_transfer_direction dir;\n};\n\nstruct udma_desc;\n\nstruct udma_chan {\n\tstruct virt_dma_chan vc;\n\tstruct dma_slave_config cfg;\n\tstruct udma_dev *ud;\n\tstruct device *dma_dev;\n\tstruct udma_desc *desc;\n\tstruct udma_desc *terminated_desc;\n\tstruct udma_static_tr static_tr;\n\tchar *name;\n\tstruct udma_tchan *bchan;\n\tstruct udma_tchan *tchan;\n\tstruct udma_rchan *rchan;\n\tstruct udma_rflow *rflow;\n\tbool psil_paired;\n\tint irq_num_ring;\n\tint irq_num_udma;\n\tbool cyclic;\n\tbool paused;\n\tenum udma_chan_state state;\n\tstruct completion teardown_completed;\n\tstruct udma_tx_drain tx_drain;\n\tstruct udma_chan_config config;\n\tstruct udma_chan_config backup_config;\n\tbool use_dma_pool;\n\tstruct dma_pool *hdesc_pool;\n\tu32 id;\n};\n\nstruct udma_hwdesc {\n\tsize_t cppi5_desc_size;\n\tvoid *cppi5_desc_vaddr;\n\tdma_addr_t cppi5_desc_paddr;\n\tvoid *tr_req_base;\n\tstruct cppi5_tr_resp_t *tr_resp_base;\n};\n\nstruct udma_desc {\n\tstruct virt_dma_desc vd;\n\tbool terminated;\n\tenum dma_transfer_direction dir;\n\tstruct udma_static_tr static_tr;\n\tu32 residue;\n\tunsigned int sglen;\n\tunsigned int desc_idx;\n\tunsigned int tr_idx;\n\tu32 metadata_size;\n\tvoid *metadata;\n\tunsigned int hwdesc_count;\n\tstruct udma_hwdesc hwdesc[0];\n};\n\nstruct udma_tpl {\n\tu8 levels;\n\tu32 start_idx[3];\n};\n\nstruct udma_tisci_rm {\n\tconst struct ti_sci_handle *tisci;\n\tconst struct ti_sci_rm_udmap_ops *tisci_udmap_ops;\n\tu32 tisci_dev_id;\n\tconst struct ti_sci_rm_psil_ops *tisci_psil_ops;\n\tu32 tisci_navss_dev_id;\n\tstruct ti_sci_resource *rm_ranges[5];\n};\n\nstruct udma_rx_flush {\n\tstruct udma_hwdesc hwdescs[2];\n\tsize_t buffer_size;\n\tvoid *buffer_vaddr;\n\tdma_addr_t buffer_paddr;\n};\n\nstruct udma_match_data;\n\nstruct udma_soc_data;\n\nstruct udma_dev {\n\tstruct dma_device ddev;\n\tstruct device *dev;\n\tvoid *mmrs[4];\n\tconst struct udma_match_data *match_data;\n\tconst struct udma_soc_data *soc_data;\n\tstruct udma_tpl bchan_tpl;\n\tstruct udma_tpl tchan_tpl;\n\tstruct udma_tpl rchan_tpl;\n\tsize_t desc_align;\n\tstruct udma_tisci_rm tisci_rm;\n\tstruct k3_ringacc *ringacc;\n\tstruct work_struct purge_work;\n\tstruct list_head desc_to_purge;\n\tspinlock_t lock;\n\tstruct udma_rx_flush rx_flush;\n\tint bchan_cnt;\n\tint tchan_cnt;\n\tint echan_cnt;\n\tint rchan_cnt;\n\tint rflow_cnt;\n\tint tflow_cnt;\n\tlong unsigned int *bchan_map;\n\tlong unsigned int *tchan_map;\n\tlong unsigned int *rchan_map;\n\tlong unsigned int *rflow_gp_map;\n\tlong unsigned int *rflow_gp_map_allocated;\n\tlong unsigned int *rflow_in_use;\n\tlong unsigned int *tflow_map;\n\tstruct udma_tchan *bchans;\n\tstruct udma_tchan *tchans;\n\tstruct udma_rchan *rchans;\n\tstruct udma_rflow *rflows;\n\tstruct udma_chan *channels;\n\tu32 psil_base;\n\tu32 atype;\n\tu32 asel;\n};\n\nstruct udma_filter_param {\n\tint remote_thread_id;\n\tu32 atype;\n\tu32 asel;\n\tu32 tr_trigger_type;\n};\n\nstruct udma_match_data {\n\tenum k3_dma_type type;\n\tu32 psil_base;\n\tbool enable_memcpy_support;\n\tu32 flags;\n\tu32 statictr_z_mask;\n\tu8 burst_size[3];\n\tstruct udma_soc_data *soc_data;\n};\n\nstruct udma_oes_offsets {\n\tu32 udma_rchan;\n\tu32 bcdma_bchan_data;\n\tu32 bcdma_bchan_ring;\n\tu32 bcdma_tchan_data;\n\tu32 bcdma_tchan_ring;\n\tu32 bcdma_rchan_data;\n\tu32 bcdma_rchan_ring;\n\tu32 pktdma_tchan_flow;\n\tu32 pktdma_rchan_flow;\n};\n\nstruct udma_rchan {\n\tvoid *reg_rt;\n\tint id;\n};\n\nstruct udma_rflow {\n\tint id;\n\tstruct k3_ring *fd_ring;\n\tstruct k3_ring *r_ring;\n};\n\nstruct udma_soc_data {\n\tstruct udma_oes_offsets oes;\n\tu32 bcdma_trigger_event_offset;\n};\n\nstruct udma_tchan {\n\tvoid *reg_rt;\n\tint id;\n\tstruct k3_ring *t_ring;\n\tstruct k3_ring *tc_ring;\n\tint tflow_id;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n\tu16 len;\n\tbool is_linear;\n\tbool csum_unnecessary;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 64;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct ufs_arpmb_meta {\n\t__be16 req_resp_type;\n\t__u8 nonce[16];\n\t__be32 write_counter;\n\t__be16 addr_lun;\n\t__be16 block_count;\n\t__be16 result;\n} __attribute__((packed));\n\nstruct utp_upiu_header {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 dword_0;\n\t\t\t__be32 dword_1;\n\t\t\t__be32 dword_2;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 transaction_code;\n\t\t\t__u8 flags;\n\t\t\t__u8 lun;\n\t\t\t__u8 task_tag;\n\t\t\t__u8 command_set_type: 4;\n\t\t\t__u8 iid: 4;\n\t\t\tunion {\n\t\t\t\t__u8 tm_function;\n\t\t\t\t__u8 query_function;\n\t\t\t};\n\t\t\t__u8 response;\n\t\t\t__u8 status;\n\t\t\t__u8 ehs_length;\n\t\t\t__u8 device_information;\n\t\t\t__be16 data_segment_length;\n\t\t};\n\t};\n};\n\nstruct utp_upiu_cmd {\n\t__be32 exp_data_transfer_len;\n\t__u8 cdb[16];\n};\n\nstruct utp_upiu_query {\n\t__u8 opcode;\n\t__u8 idn;\n\t__u8 index;\n\t__u8 selector;\n\t__be16 reserved_osf;\n\t__be16 length;\n\t__be32 value;\n\t__be32 reserved[2];\n};\n\nstruct utp_upiu_req {\n\tstruct utp_upiu_header header;\n\tunion {\n\t\tstruct utp_upiu_cmd sc;\n\t\tstruct utp_upiu_query qr;\n\t\tstruct utp_upiu_query uc;\n\t};\n};\n\nstruct ufs_bsg_reply {\n\tint result;\n\t__u32 reply_payload_rcv_len;\n\tstruct utp_upiu_req upiu_rsp;\n};\n\nstruct ufs_bsg_request {\n\t__u32 msgcode;\n\tstruct utp_upiu_req upiu_req;\n};\n\nstruct ufs_clk_gating {\n\tstruct delayed_work gate_work;\n\tstruct work_struct ungate_work;\n\tstruct workqueue_struct *clk_gating_workq;\n\tspinlock_t lock;\n\tenum clk_gating_state state;\n\tlong unsigned int delay_ms;\n\tbool is_suspended;\n\tstruct device_attribute delay_attr;\n\tstruct device_attribute enable_attr;\n\tbool is_enabled;\n\tbool is_initialized;\n\tint active_reqs;\n};\n\nstruct ufs_clk_info {\n\tstruct list_head list;\n\tstruct clk *clk;\n\tconst char *name;\n\tu32 max_freq;\n\tu32 min_freq;\n\tu32 curr_freq;\n\tbool keep_link_active;\n\tbool enabled;\n};\n\nstruct ufs_clk_scaling {\n\tstruct workqueue_struct *workq;\n\tstruct work_struct suspend_work;\n\tstruct work_struct resume_work;\n\tspinlock_t lock;\n\tint active_reqs;\n\tlong unsigned int tot_busy_t;\n\tktime_t window_start_t;\n\tktime_t busy_start_t;\n\tstruct device_attribute enable_attr;\n\tstruct ufs_pa_layer_attr saved_pwr_info;\n\tlong unsigned int target_freq;\n\tu32 min_gear;\n\tu32 wb_gear;\n\tbool is_enabled;\n\tbool is_allowed;\n\tbool is_initialized;\n\tbool is_busy_started;\n\tbool is_suspended;\n\tbool suspend_on_no_request;\n};\n\nstruct ufs_crypto_alg_entry {\n\tenum ufs_crypto_alg ufs_alg;\n\tenum ufs_crypto_key_size ufs_key_size;\n};\n\nunion ufs_crypto_cap_entry {\n\t__le32 reg_val;\n\tstruct {\n\t\tu8 algorithm_id;\n\t\tu8 sdus_mask;\n\t\tu8 key_size;\n\t\tu8 reserved;\n\t};\n};\n\nunion ufs_crypto_capabilities {\n\t__le32 reg_val;\n\tstruct {\n\t\tu8 num_crypto_cap;\n\t\tu8 config_count;\n\t\tu8 reserved;\n\t\tu8 config_array_ptr;\n\t};\n};\n\nunion ufs_crypto_cfg_entry {\n\t__le32 reg_val[32];\n\tstruct {\n\t\tu8 crypto_key[64];\n\t\tu8 data_unit_size;\n\t\tu8 crypto_cap_idx;\n\t\tu8 reserved_1;\n\t\tu8 config_enable;\n\t\tu8 reserved_multi_host;\n\t\tu8 reserved_2;\n\t\tu8 vsb[2];\n\t\tu8 reserved_3[56];\n\t};\n};\n\nstruct ufs_debugfs_attr {\n\tconst char *name;\n\tmode_t mode;\n\tconst struct file_operations *fops;\n};\n\nstruct ufs_query_req {\n\tu8 query_func;\n\tstruct utp_upiu_query upiu_req;\n};\n\nstruct ufs_query_res {\n\tstruct utp_upiu_query upiu_res;\n};\n\nstruct ufs_query {\n\tstruct ufs_query_req request;\n\tu8 *descriptor;\n\tstruct ufs_query_res response;\n};\n\nstruct ufs_dev_cmd {\n\tenum dev_cmd_type type;\n\tstruct mutex lock;\n\tstruct ufs_query query;\n};\n\nstruct ufs_dev_info {\n\tbool f_power_on_wp_en;\n\tbool is_lu_power_on_wp;\n\tu8 max_lu_supported;\n\tu16 wmanufacturerid;\n\tu8 *model;\n\tu16 wspecversion;\n\tu32 clk_gating_wait_us;\n\tu8 bqueuedepth;\n\tbool wb_enabled;\n\tbool wb_buf_flush_enabled;\n\tu8 wb_dedicated_lu;\n\tu8 wb_buffer_type;\n\tu16 ext_wb_sup;\n\tbool b_rpm_dev_flush_capable;\n\tu8 b_presrv_uspc_en;\n\tbool b_advanced_rpmb_en;\n\tenum ufs_rtc_time rtc_type;\n\ttime64_t rtc_time_baseline;\n\tu32 rtc_update_period;\n\tu8 rtt_cap;\n\tbool hid_sup;\n\tchar *device_id;\n\tu8 rpmb_io_size;\n\tu8 rpmb_region_size[4];\n};\n\nstruct ufs_dev_quirk {\n\tu16 wmanufacturerid;\n\tconst u8 *model;\n\tunsigned int quirk;\n};\n\nstruct ufs_ehs {\n\t__u8 length;\n\t__u8 ehs_type;\n\t__be16 ehssub_type;\n\tstruct ufs_arpmb_meta meta;\n\t__u8 mac_key[32];\n};\n\nstruct ufs_event_hist {\n\tint pos;\n\tu32 val[8];\n\tu64 tstamp[8];\n\tlong long unsigned int cnt;\n};\n\nstruct ufs_stats {\n\tu32 hibern8_exit_cnt;\n\tu64 last_hibern8_exit_tstamp;\n\tstruct ufs_event_hist event[15];\n};\n\nstruct ufs_vreg;\n\nstruct ufs_vreg_info {\n\tstruct ufs_vreg *vcc;\n\tstruct ufs_vreg *vccq;\n\tstruct ufs_vreg *vccq2;\n\tstruct ufs_vreg *vdd_hba;\n};\n\nstruct ufs_pwr_mode_info {\n\tbool is_valid;\n\tstruct ufs_pa_layer_attr info;\n};\n\nstruct ufs_hba_monitor {\n\tlong unsigned int chunk_size;\n\tlong unsigned int nr_sec_rw[2];\n\tktime_t total_busy[2];\n\tlong unsigned int nr_req[2];\n\tktime_t lat_sum[2];\n\tktime_t lat_max[2];\n\tktime_t lat_min[2];\n\tu32 nr_queued[2];\n\tktime_t busy_start_ts[2];\n\tktime_t enabled_ts;\n\tbool enabled;\n};\n\nstruct ufshcd_mcq_opr_info_t {\n\tlong unsigned int offset;\n\tlong unsigned int stride;\n\tvoid *base;\n};\n\nstruct utp_transfer_cmd_desc;\n\nstruct utp_transfer_req_desc;\n\nstruct utp_task_req_desc;\n\nstruct ufs_hba_variant_params;\n\nstruct uic_command;\n\nstruct ufs_hw_queue;\n\nstruct ufs_hba {\n\tvoid *mmio_base;\n\tstruct utp_transfer_cmd_desc *ucdl_base_addr;\n\tstruct utp_transfer_req_desc *utrdl_base_addr;\n\tstruct utp_task_req_desc *utmrdl_base_addr;\n\tdma_addr_t ucdl_dma_addr;\n\tdma_addr_t utrdl_dma_addr;\n\tdma_addr_t utmrdl_dma_addr;\n\tstruct Scsi_Host *host;\n\tstruct device *dev;\n\tstruct scsi_device *ufs_device_wlun;\n\tstruct scsi_device *ufs_rpmb_wlun;\n\tenum ufs_dev_pwr_mode curr_dev_pwr_mode;\n\tenum uic_link_state uic_link_state;\n\tenum ufs_pm_level rpm_lvl;\n\tenum ufs_pm_level spm_lvl;\n\tenum ufs_pm_level pm_lvl_min;\n\tint pm_op_in_progress;\n\tu32 ahit;\n\tlong unsigned int outstanding_tasks;\n\tspinlock_t outstanding_lock;\n\tlong unsigned int outstanding_reqs;\n\tu32 capabilities;\n\tint nutrs;\n\tint nortt;\n\tu32 mcq_capabilities;\n\tint nutmrs;\n\tu32 ufs_version;\n\tconst struct ufs_hba_variant_ops *vops;\n\tstruct ufs_hba_variant_params *vps;\n\tvoid *priv;\n\tsize_t sg_entry_size;\n\tunsigned int irq;\n\tbool is_irq_enabled;\n\tenum ufs_ref_clk_freq dev_ref_clk_freq;\n\tunsigned int quirks;\n\tunsigned int dev_quirks;\n\tstruct blk_mq_tag_set tmf_tag_set;\n\tstruct request_queue *tmf_queue;\n\tstruct request **tmf_rqs;\n\tstruct uic_command *active_uic_cmd;\n\tstruct mutex uic_cmd_mutex;\n\tstruct completion *uic_async_done;\n\tenum ufshcd_state ufshcd_state;\n\tu32 eh_flags;\n\tu32 intr_mask;\n\tu16 ee_ctrl_mask;\n\tu16 ee_drv_mask;\n\tu16 ee_usr_mask;\n\tstruct mutex ee_ctrl_mutex;\n\tbool is_powered;\n\tbool shutting_down;\n\tstruct semaphore host_sem;\n\tstruct workqueue_struct *eh_wq;\n\tstruct work_struct eh_work;\n\tstruct work_struct eeh_work;\n\tu32 errors;\n\tu32 uic_error;\n\tu32 saved_err;\n\tu32 saved_uic_err;\n\tstruct ufs_stats ufs_stats;\n\tbool force_reset;\n\tbool force_pmc;\n\tbool silence_err_logs;\n\tstruct ufs_dev_cmd dev_cmd;\n\tktime_t last_dme_cmd_tstamp;\n\tint nop_out_timeout;\n\tstruct ufs_dev_info dev_info;\n\tbool auto_bkops_enabled;\n\tstruct ufs_vreg_info vreg_info;\n\tstruct list_head clk_list_head;\n\tbool use_pm_opp;\n\tint req_abort_count;\n\tu32 lanes_per_direction;\n\tstruct ufs_pa_layer_attr pwr_info;\n\tstruct ufs_pwr_mode_info max_pwr_info;\n\tstruct ufs_clk_gating clk_gating;\n\tu32 caps;\n\tstruct devfreq *devfreq;\n\tstruct ufs_clk_scaling clk_scaling;\n\tbool system_suspending;\n\tbool is_sys_suspended;\n\tenum bkops_status urgent_bkops_lvl;\n\tbool is_urgent_bkops_lvl_checked;\n\tstruct mutex wb_mutex;\n\tstruct rw_semaphore clk_scaling_lock;\n\tstruct device bsg_dev;\n\tstruct request_queue *bsg_queue;\n\tstruct delayed_work rpm_dev_flush_recheck_work;\n\tstruct ufs_hba_monitor monitor;\n\tunion ufs_crypto_capabilities crypto_capabilities;\n\tunion ufs_crypto_cap_entry *crypto_cap_array;\n\tu32 crypto_cfg_register;\n\tstruct blk_crypto_profile crypto_profile;\n\tstruct dentry *debugfs_root;\n\tstruct delayed_work debugfs_ee_work;\n\tu32 debugfs_ee_rate_limit_ms;\n\tu32 luns_avail;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_queues[3];\n\tbool complete_put;\n\tbool scsi_host_added;\n\tbool mcq_sup;\n\tbool lsdb_sup;\n\tbool mcq_enabled;\n\tbool mcq_esi_enabled;\n\tvoid *mcq_base;\n\tstruct ufs_hw_queue *uhq;\n\tstruct ufshcd_mcq_opr_info_t mcq_opr[4];\n\tstruct delayed_work ufs_rtc_update_work;\n\tstruct pm_qos_request pm_qos_req;\n\tbool pm_qos_enabled;\n\tstruct mutex pm_qos_mutex;\n\tint critical_health_count;\n\tatomic_t dev_lvl_exception_count;\n\tu64 dev_lvl_exception_id;\n\tu32 vcc_off_delay_us;\n\tstruct list_head rpmbs;\n};\n\nstruct ufs_hba_variant_ops {\n\tconst char *name;\n\tint max_num_rtt;\n\tint (*init)(struct ufs_hba *);\n\tvoid (*exit)(struct ufs_hba *);\n\tu32 (*get_ufs_hci_version)(struct ufs_hba *);\n\tint (*set_dma_mask)(struct ufs_hba *);\n\tint (*clk_scale_notify)(struct ufs_hba *, bool, long unsigned int, enum ufs_notify_change_status);\n\tint (*setup_clocks)(struct ufs_hba *, bool, enum ufs_notify_change_status);\n\tint (*hce_enable_notify)(struct ufs_hba *, enum ufs_notify_change_status);\n\tint (*link_startup_notify)(struct ufs_hba *, enum ufs_notify_change_status);\n\tint (*pwr_change_notify)(struct ufs_hba *, enum ufs_notify_change_status, const struct ufs_pa_layer_attr *, struct ufs_pa_layer_attr *);\n\tvoid (*setup_xfer_req)(struct ufs_hba *, int, bool);\n\tvoid (*setup_task_mgmt)(struct ufs_hba *, int, u8);\n\tvoid (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, enum ufs_notify_change_status);\n\tint (*apply_dev_quirks)(struct ufs_hba *);\n\tvoid (*fixup_dev_quirks)(struct ufs_hba *);\n\tint (*suspend)(struct ufs_hba *, enum ufs_pm_op, enum ufs_notify_change_status);\n\tint (*resume)(struct ufs_hba *, enum ufs_pm_op);\n\tvoid (*dbg_register_dump)(struct ufs_hba *);\n\tint (*phy_initialization)(struct ufs_hba *);\n\tint (*device_reset)(struct ufs_hba *);\n\tvoid (*config_scaling_param)(struct ufs_hba *, struct devfreq_dev_profile *, struct devfreq_simple_ondemand_data *);\n\tint (*fill_crypto_prdt)(struct ufs_hba *, const struct bio_crypt_ctx *, void *, unsigned int);\n\tvoid (*event_notify)(struct ufs_hba *, enum ufs_event_type, void *);\n\tint (*mcq_config_resource)(struct ufs_hba *);\n\tint (*get_hba_mac)(struct ufs_hba *);\n\tint (*op_runtime_config)(struct ufs_hba *);\n\tint (*get_outstanding_cqs)(struct ufs_hba *, long unsigned int *);\n\tint (*config_esi)(struct ufs_hba *);\n\tvoid (*config_scsi_dev)(struct scsi_device *);\n\tu32 (*freq_to_gear_speed)(struct ufs_hba *, long unsigned int);\n};\n\nstruct ufs_hba_variant_params {\n\tstruct devfreq_dev_profile devfreq_profile;\n\tstruct devfreq_simple_ondemand_data ondemand_data;\n\tu16 hba_enable_delay_us;\n\tu32 wb_flush_threshold;\n};\n\nstruct ufs_hisi_host {\n\tstruct ufs_hba *hba;\n\tvoid *ufs_sys_ctrl;\n\tstruct reset_control *rst;\n\tuint64_t caps;\n\tbool in_suspend;\n};\n\nstruct ufs_host_params {\n\tu32 pwm_rx_gear;\n\tu32 pwm_tx_gear;\n\tu32 hs_rx_gear;\n\tu32 hs_tx_gear;\n\tu32 rx_lanes;\n\tu32 tx_lanes;\n\tu32 rx_pwr_pwm;\n\tu32 tx_pwr_pwm;\n\tu32 rx_pwr_hs;\n\tu32 tx_pwr_hs;\n\tu32 hs_rate;\n\tu32 desired_working_mode;\n};\n\nstruct ufs_hw_queue {\n\tvoid *mcq_sq_head;\n\tvoid *mcq_sq_tail;\n\tvoid *mcq_cq_head;\n\tvoid *mcq_cq_tail;\n\tstruct utp_transfer_req_desc *sqe_base_addr;\n\tdma_addr_t sqe_dma_addr;\n\tstruct cq_entry *cqe_base_addr;\n\tdma_addr_t cqe_dma_addr;\n\tu32 max_entries;\n\tu32 id;\n\tu32 sq_tail_slot;\n\tspinlock_t sq_lock;\n\tu32 cq_tail_slot;\n\tu32 cq_head_slot;\n\tspinlock_t cq_lock;\n\tstruct mutex sq_mutex;\n};\n\nstruct ufs_mtk_clk {\n\tstruct ufs_clk_info *ufs_sel_clki;\n\tstruct ufs_clk_info *ufs_sel_max_clki;\n\tstruct ufs_clk_info *ufs_sel_min_clki;\n\tstruct ufs_clk_info *ufs_fde_clki;\n\tstruct ufs_clk_info *ufs_fde_max_clki;\n\tstruct ufs_clk_info *ufs_fde_min_clki;\n\tstruct regulator *reg_vcore;\n\tint vcore_volt;\n};\n\nstruct ufs_mtk_crypt_cfg {\n\tstruct regulator *reg_vcore;\n\tstruct clk *clk_crypt_perf;\n\tstruct clk *clk_crypt_mux;\n\tstruct clk *clk_crypt_lp;\n\tint vcore_volt;\n};\n\nstruct ufs_mtk_hw_ver {\n\tu8 step;\n\tu8 minor;\n\tu8 major;\n};\n\nstruct ufs_mtk_mcq_intr_info {\n\tstruct ufs_hba *hba;\n\tu32 irq;\n\tu8 qid;\n};\n\nstruct ufs_mtk_host {\n\tstruct phy *mphy;\n\tstruct regulator *reg_va09;\n\tstruct reset_control *hci_reset;\n\tstruct reset_control *unipro_reset;\n\tstruct reset_control *crypto_reset;\n\tstruct reset_control *mphy_reset;\n\tstruct ufs_hba *hba;\n\tstruct ufs_mtk_crypt_cfg *crypt;\n\tstruct ufs_mtk_clk mclk;\n\tstruct ufs_mtk_hw_ver hw_ver;\n\tenum ufs_mtk_host_caps caps;\n\tbool mphy_powered_on;\n\tbool unipro_lpm;\n\tbool ref_clk_enabled;\n\tbool clk_scale_up;\n\tu16 ref_clk_ungating_wait_us;\n\tu16 ref_clk_gating_wait_us;\n\tu32 ip_ver;\n\tbool legacy_ip_ver;\n\tbool mcq_set_intr;\n\tbool is_mcq_intr_enabled;\n\tint mcq_nr_intr;\n\tstruct ufs_mtk_mcq_intr_info mcq_intr_info[8];\n\tstruct device *phy_dev;\n};\n\nstruct ufs_mtk_phy {\n\tstruct device *dev;\n\tvoid *mmio;\n\tstruct clk_bulk_data clks[2];\n};\n\nstruct ufs_mtk_smc_arg {\n\tlong unsigned int cmd;\n\tstruct arm_smccc_res *res;\n\tlong unsigned int v1;\n\tlong unsigned int v2;\n\tlong unsigned int v3;\n\tlong unsigned int v4;\n\tlong unsigned int v5;\n\tlong unsigned int v6;\n\tlong unsigned int v7;\n};\n\nstruct ufs_pm_lvl_states {\n\tenum ufs_dev_pwr_mode dev_state;\n\tenum uic_link_state link_state;\n};\n\nstruct ufs_ref_clk {\n\tlong unsigned int freq_hz;\n\tenum ufs_ref_clk_freq val;\n};\n\nstruct ufs_rockchip_host {\n\tstruct ufs_hba *hba;\n\tvoid *ufs_phy_ctrl;\n\tvoid *ufs_sys_ctrl;\n\tvoid *mphy_base;\n\tstruct gpio_desc *rst_gpio;\n\tstruct reset_control *rst;\n\tstruct clk *ref_out_clk;\n\tstruct clk_bulk_data *clks;\n\tuint64_t caps;\n};\n\nstruct ufs_rpmb_reply {\n\tstruct ufs_bsg_reply bsg_reply;\n\tstruct ufs_ehs ehs_rsp;\n};\n\nstruct ufs_rpmb_request {\n\tstruct ufs_bsg_request bsg_request;\n\tstruct ufs_ehs ehs_req;\n};\n\nstruct ufs_vreg {\n\tstruct regulator *reg;\n\tconst char *name;\n\tbool always_on;\n\tbool enabled;\n\tint max_uA;\n};\n\nstruct utp_upiu_rsp;\n\nstruct ufshcd_lrb {\n\tstruct utp_transfer_req_desc *utr_descriptor_ptr;\n\tstruct utp_upiu_req *ucd_req_ptr;\n\tstruct utp_upiu_rsp *ucd_rsp_ptr;\n\tstruct ufshcd_sg_entry *ucd_prdt_ptr;\n\tdma_addr_t utrd_dma_addr;\n\tdma_addr_t ucd_req_dma_addr;\n\tdma_addr_t ucd_rsp_dma_addr;\n\tdma_addr_t ucd_prdt_dma_addr;\n\tint scsi_status;\n\tint command_type;\n\tu8 lun;\n\tbool intr_cmd;\n\tbool req_abort_skip;\n\tktime_t issue_time_stamp;\n\tu64 issue_time_stamp_local_clock;\n\tktime_t compl_time_stamp;\n\tu64 compl_time_stamp_local_clock;\n\tint crypto_key_slot;\n\tu64 data_unit_num;\n};\n\nstruct uic_command {\n\tconst u32 command;\n\tconst u32 argument1;\n\tu32 argument2;\n\tu32 argument3;\n\tbool cmd_active;\n\tstruct completion done;\n};\n\nstruct ulpi_device_id {\n\t__u16 vendor;\n\t__u16 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct ulpi {\n\tstruct device dev;\n\tstruct ulpi_device_id id;\n\tconst struct ulpi_ops *ops;\n};\n\nstruct ulpi_driver {\n\tconst struct ulpi_device_id *id_table;\n\tint (*probe)(struct ulpi *);\n\tvoid (*remove)(struct ulpi *);\n\tstruct device_driver driver;\n};\n\nstruct ulpi_info {\n\tunsigned int id;\n\tchar *name;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct uncharge_gather {\n\tstruct mem_cgroup *memcg;\n\tlong unsigned int nr_memory;\n\tlong unsigned int pgpgout;\n\tlong unsigned int nr_kmem;\n\tint nid;\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct unimac_mdio_pdata {\n\tu32 phy_mask;\n\tint (*wait_func)(void *);\n\tvoid *wait_func_data;\n\tconst char *bus_name;\n\tstruct clk *clk;\n};\n\nstruct unimac_mdio_priv {\n\tstruct mii_bus *mii_bus;\n\tvoid *base;\n\tint (*wait_func)(void *);\n\tvoid *wait_func_data;\n\tstruct clk *clk;\n\tu32 clk_freq;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct uniphier8250_priv {\n\tint line;\n\tstruct clk *clk;\n\tspinlock_t atomic_write_lock;\n};\n\nstruct uniphier_ahciphy_soc_data;\n\nstruct uniphier_ahciphy_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_parent_gio;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_parent;\n\tstruct reset_control *rst_parent_gio;\n\tstruct reset_control *rst_pm;\n\tstruct reset_control *rst_tx;\n\tstruct reset_control *rst_rx;\n\tconst struct uniphier_ahciphy_soc_data *data;\n};\n\nstruct uniphier_ahciphy_soc_data {\n\tint (*init)(struct uniphier_ahciphy_priv *);\n\tint (*power_on)(struct uniphier_ahciphy_priv *);\n\tint (*power_off)(struct uniphier_ahciphy_priv *);\n\tbool is_legacy;\n\tbool is_ready_high;\n\tbool is_phy_clk;\n};\n\nstruct uniphier_aidet_priv {\n\tstruct irq_domain *domain;\n\tvoid *reg_base;\n\tspinlock_t lock;\n\tu32 saved_vals[8];\n};\n\nstruct uniphier_clk_cpugear {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int regbase;\n\tunsigned int mask;\n};\n\nstruct uniphier_clk_cpugear_data {\n\tconst char *parent_names[16];\n\tunsigned int num_parents;\n\tunsigned int regbase;\n\tunsigned int mask;\n};\n\nstruct uniphier_clk_fixed_factor_data {\n\tconst char *parent_name;\n\tunsigned int mult;\n\tunsigned int div;\n};\n\nstruct uniphier_clk_fixed_rate_data {\n\tlong unsigned int fixed_rate;\n};\n\nstruct uniphier_clk_gate_data {\n\tconst char *parent_name;\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct uniphier_clk_mux_data {\n\tconst char *parent_names[8];\n\tunsigned int num_parents;\n\tunsigned int reg;\n\tunsigned int masks[8];\n\tunsigned int vals[8];\n};\n\nstruct uniphier_clk_data {\n\tconst char *name;\n\tenum uniphier_clk_type type;\n\tint idx;\n\tunion {\n\t\tstruct uniphier_clk_cpugear_data cpugear;\n\t\tstruct uniphier_clk_fixed_factor_data factor;\n\t\tstruct uniphier_clk_fixed_rate_data rate;\n\t\tstruct uniphier_clk_gate_data gate;\n\t\tstruct uniphier_clk_mux_data mux;\n\t} data;\n};\n\nstruct uniphier_clk_gate {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int reg;\n\tunsigned int bit;\n};\n\nstruct uniphier_clk_mux {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tunsigned int reg;\n\tconst unsigned int *masks;\n\tconst unsigned int *vals;\n};\n\nstruct uniphier_efuse_priv {\n\tvoid *base;\n};\n\nstruct uniphier_fi2c_priv {\n\tstruct completion comp;\n\tstruct i2c_adapter adap;\n\tvoid *membase;\n\tstruct clk *clk;\n\tunsigned int len;\n\tu8 *buf;\n\tu32 enabled_irqs;\n\tint error;\n\tunsigned int flags;\n\tunsigned int busy_cnt;\n\tunsigned int clk_cycle;\n\tspinlock_t lock;\n};\n\nstruct uniphier_glue_reset_soc_data;\n\nstruct uniphier_glue_reset_priv {\n\tstruct clk_bulk_data clk[2];\n\tstruct reset_control_bulk_data rst[2];\n\tstruct reset_simple_data rdata;\n\tconst struct uniphier_glue_reset_soc_data *data;\n};\n\nstruct uniphier_glue_reset_soc_data {\n\tint nclks;\n\tconst char * const *clock_names;\n\tint nrsts;\n\tconst char * const *reset_names;\n};\n\nstruct uniphier_gpio_priv {\n\tstruct gpio_chip chip;\n\tstruct irq_chip irq_chip;\n\tstruct irq_domain *domain;\n\tvoid *regs;\n\tspinlock_t lock;\n\tu32 saved_vals[0];\n};\n\nstruct uniphier_pinctrl_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int num_pins;\n\tconst int *muxvals;\n};\n\nstruct uniphier_pinctrl_socdata;\n\nstruct uniphier_pinctrl_priv {\n\tstruct pinctrl_desc pctldesc;\n\tstruct pinctrl_dev *pctldev;\n\tstruct regmap *regmap;\n\tconst struct uniphier_pinctrl_socdata *socdata;\n\tstruct list_head reg_regions;\n};\n\nstruct uniphier_pinctrl_reg_region {\n\tstruct list_head node;\n\tunsigned int base;\n\tunsigned int nregs;\n\tu32 vals[0];\n};\n\nstruct uniphier_pinmux_function;\n\nstruct uniphier_pinctrl_socdata {\n\tconst struct pinctrl_pin_desc *pins;\n\tunsigned int npins;\n\tconst struct uniphier_pinctrl_group *groups;\n\tint groups_count;\n\tconst struct uniphier_pinmux_function *functions;\n\tint functions_count;\n\tint (*get_gpio_muxval)(unsigned int, unsigned int);\n\tunsigned int caps;\n};\n\nstruct uniphier_pinmux_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int num_groups;\n};\n\nstruct uniphier_regulator_soc_data;\n\nstruct uniphier_regulator_priv {\n\tstruct clk_bulk_data clk[2];\n\tstruct reset_control *rst[2];\n\tconst struct uniphier_regulator_soc_data *data;\n};\n\nstruct uniphier_regulator_soc_data {\n\tint nclks;\n\tconst char * const *clock_names;\n\tint nrsts;\n\tconst char * const *reset_names;\n\tconst struct regulator_desc *desc;\n\tconst struct regmap_config *regconf;\n};\n\nstruct uniphier_reset_data {\n\tunsigned int id;\n\tunsigned int reg;\n\tunsigned int bit;\n\tunsigned int flags;\n};\n\nstruct uniphier_reset_priv {\n\tstruct reset_controller_dev rcdev;\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tconst struct uniphier_reset_data *data;\n};\n\nstruct uniphier_sd_priv {\n\tstruct tmio_mmc_data tmio_data;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pinstate_uhs;\n\tstruct clk *clk;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_br;\n\tstruct reset_control *rst_hw;\n\tstruct dma_chan *chan;\n\tenum dma_data_direction dma_dir;\n\tstruct regmap *sdctrl_regmap;\n\tu32 sdctrl_ch;\n\tlong unsigned int clk_rate;\n\tlong unsigned int caps;\n};\n\nstruct uniphier_system_bus_bank {\n\tu32 base;\n\tu32 end;\n};\n\nstruct uniphier_system_bus_priv {\n\tstruct device *dev;\n\tvoid *membase;\n\tstruct uniphier_system_bus_bank bank[8];\n};\n\nstruct uniphier_tm_soc_data;\n\nstruct uniphier_tm_dev {\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tbool alert_en[3];\n\tstruct thermal_zone_device *tz_dev;\n\tconst struct uniphier_tm_soc_data *data;\n};\n\nstruct uniphier_tm_soc_data {\n\tu32 map_base;\n\tu32 block_base;\n\tu32 tmod_setup_addr;\n};\n\nstruct uniphier_u2phy_param {\n\tu32 offset;\n\tu32 value;\n};\n\nstruct uniphier_u2phy_soc_data;\n\nstruct uniphier_u2phy_priv {\n\tstruct regmap *regmap;\n\tstruct phy *phy;\n\tstruct regulator *vbus;\n\tconst struct uniphier_u2phy_soc_data *data;\n\tstruct uniphier_u2phy_priv *next;\n};\n\nstruct uniphier_u2phy_soc_data {\n\tstruct uniphier_u2phy_param config0;\n\tstruct uniphier_u2phy_param config1;\n};\n\nstruct uniphier_u3hsphy_param {\n\tstruct {\n\t\tint reg_no;\n\t\tint msb;\n\t\tint lsb;\n\t} field;\n\tu8 value;\n};\n\nstruct uniphier_u3hsphy_soc_data;\n\nstruct uniphier_u3hsphy_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_ext;\n\tstruct clk *clk_parent_gio;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_parent;\n\tstruct reset_control *rst_parent_gio;\n\tstruct regulator *vbus;\n\tconst struct uniphier_u3hsphy_soc_data *data;\n};\n\nstruct uniphier_u3hsphy_trim_param;\n\nstruct uniphier_u3hsphy_soc_data {\n\tbool is_legacy;\n\tint nparams;\n\tconst struct uniphier_u3hsphy_param param[4];\n\tu32 config0;\n\tu32 config1;\n\tvoid (*trim_func)(struct uniphier_u3hsphy_priv *, u32 *, struct uniphier_u3hsphy_trim_param *);\n};\n\nstruct uniphier_u3hsphy_trim_param {\n\tunsigned int rterm;\n\tunsigned int sel_t;\n\tunsigned int hs_i;\n};\n\nstruct uniphier_u3ssphy_param {\n\tstruct {\n\t\tint reg_no;\n\t\tint msb;\n\t\tint lsb;\n\t} field;\n\tu8 value;\n};\n\nstruct uniphier_u3ssphy_soc_data;\n\nstruct uniphier_u3ssphy_priv {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct clk *clk;\n\tstruct clk *clk_ext;\n\tstruct clk *clk_parent;\n\tstruct clk *clk_parent_gio;\n\tstruct reset_control *rst;\n\tstruct reset_control *rst_parent;\n\tstruct reset_control *rst_parent_gio;\n\tstruct regulator *vbus;\n\tconst struct uniphier_u3ssphy_soc_data *data;\n};\n\nstruct uniphier_u3ssphy_soc_data {\n\tbool is_legacy;\n\tint nparams;\n\tconst struct uniphier_u3ssphy_param param[7];\n};\n\nstruct uniphier_wdt_dev {\n\tstruct watchdog_device wdt_dev;\n\tstruct regmap *regmap;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_domain {\n\tstruct auth_domain h;\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_gid {\n\tstruct cache_head h;\n\tkuid_t uid;\n\tstruct group_info *gi;\n\tstruct callback_head rcu;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 64;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\nstruct unmap_refs_callback_data {\n\tstruct completion completion;\n\tint result;\n};\n\nstruct unmap_ring_hvm {\n\tunsigned int idx;\n\tlong unsigned int addrs[16];\n};\n\nstruct unwind_stacktrace {\n\tunsigned int nr;\n\tlong unsigned int *entries;\n};\n\nstruct unwind_work;\n\ntypedef void (*unwind_callback_t)(struct unwind_work *, struct unwind_stacktrace *, u64);\n\nstruct unwind_work {\n\tstruct list_head list;\n\tunwind_callback_t func;\n\tint bit;\n};\n\nstruct update_cgr_params {\n\tstruct qman_cgr *cgr;\n\tstruct qm_mcc_initcgr *opts;\n\tint ret;\n};\n\nunion upper_chunk {\n\tunion upper_chunk *next;\n\tunion lower_chunk *data[256];\n};\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct list_head consumers;\n\tstruct inode *inode;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n\tint dsize;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunsigned int depth;\n\tstruct return_instance *return_instances;\n\tstruct return_instance *ri_pool;\n\tstruct timer_list ri_timer;\n\tseqcount_t ri_seqcount;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tbool signal_denied;\n\tstruct arch_uprobe *auprobe;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\ntypedef void (*usb_complete_t)(struct urb *);\n\nstruct usb_iso_packet_descriptor {\n\tunsigned int offset;\n\tunsigned int length;\n\tunsigned int actual_length;\n\tint status;\n};\n\nstruct usb_anchor;\n\nstruct urb {\n\tstruct kref kref;\n\tint unlinked;\n\tvoid *hcpriv;\n\tatomic_t use_count;\n\tatomic_t reject;\n\tstruct list_head urb_list;\n\tstruct list_head anchor_list;\n\tstruct usb_anchor *anchor;\n\tstruct usb_device *dev;\n\tstruct usb_host_endpoint *ep;\n\tunsigned int pipe;\n\tunsigned int stream_id;\n\tint status;\n\tunsigned int transfer_flags;\n\tvoid *transfer_buffer;\n\tdma_addr_t transfer_dma;\n\tstruct scatterlist *sg;\n\tstruct sg_table *sgt;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tu32 transfer_buffer_length;\n\tu32 actual_length;\n\tunsigned char *setup_packet;\n\tdma_addr_t setup_dma;\n\tint start_frame;\n\tint number_of_packets;\n\tint interval;\n\tint error_count;\n\tvoid *context;\n\tusb_complete_t complete;\n\tstruct usb_iso_packet_descriptor iso_frame_desc[0];\n};\n\nstruct urb_listitem {\n\tstruct list_head urb_list;\n\tstruct urb *urb;\n};\n\nstruct urb_priv {\n\tstruct ed *ed;\n\tu16 length;\n\tu16 td_cnt;\n\tstruct list_head pending;\n\tstruct td *td[0];\n};\n\nstruct xhci_segment;\n\nstruct xhci_td {\n\tstruct list_head td_list;\n\tstruct list_head cancelled_td_list;\n\tint status;\n\tenum xhci_cancelled_td_status cancel_status;\n\tstruct urb *urb;\n\tstruct xhci_segment *start_seg;\n\tunion xhci_trb *start_trb;\n\tstruct xhci_segment *end_seg;\n\tunion xhci_trb *end_trb;\n\tstruct xhci_segment *bounce_seg;\n\tbool urb_length_set;\n\tbool error_mid_td;\n};\n\nstruct urb_priv___2 {\n\tint num_tds;\n\tint num_tds_done;\n\tstruct xhci_td td[0];\n};\n\ntypedef struct urb_priv urb_priv_t;\n\nstruct us_data;\n\ntypedef int (*trans_cmnd)(struct scsi_cmnd *, struct us_data *);\n\ntypedef int (*trans_reset)(struct us_data *);\n\ntypedef void (*proto_cmnd)(struct scsi_cmnd *, struct us_data *);\n\nstruct usb_sg_request {\n\tint status;\n\tsize_t bytes;\n\tspinlock_t lock;\n\tstruct usb_device *dev;\n\tint pipe;\n\tint entries;\n\tstruct urb **urbs;\n\tint count;\n\tstruct completion complete;\n};\n\ntypedef void (*extra_data_destructor)(void *);\n\ntypedef void (*pm_hook)(struct us_data *, int);\n\nstruct usb_interface;\n\nstruct us_unusual_dev;\n\nstruct us_data {\n\tstruct mutex dev_mutex;\n\tstruct usb_device *pusb_dev;\n\tstruct usb_interface *pusb_intf;\n\tconst struct us_unusual_dev *unusual_dev;\n\tu64 fflags;\n\tlong unsigned int dflags;\n\tunsigned int send_bulk_pipe;\n\tunsigned int recv_bulk_pipe;\n\tunsigned int send_ctrl_pipe;\n\tunsigned int recv_ctrl_pipe;\n\tunsigned int recv_intr_pipe;\n\tchar *transport_name;\n\tchar *protocol_name;\n\t__le32 bcs_signature;\n\tu8 subclass;\n\tu8 protocol;\n\tu8 max_lun;\n\tu8 ifnum;\n\tu8 ep_bInterval;\n\ttrans_cmnd transport;\n\ttrans_reset transport_reset;\n\tproto_cmnd proto_handler;\n\tstruct scsi_cmnd *srb;\n\tunsigned int tag;\n\tchar scsi_name[32];\n\tstruct urb *current_urb;\n\tstruct usb_ctrlrequest *cr;\n\tstruct usb_sg_request current_sg;\n\tunsigned char *iobuf;\n\tdma_addr_t iobuf_dma;\n\tstruct task_struct *ctl_thread;\n\tstruct completion cmnd_ready;\n\tstruct completion notify;\n\twait_queue_head_t delay_wait;\n\tstruct delayed_work scan_dwork;\n\tvoid *extra;\n\textra_data_destructor extra_destructor;\n\tpm_hook suspend_resume_hook;\n\tint use_last_sector_hacks;\n\tint last_sector_retries;\n};\n\nstruct us_unusual_dev {\n\tconst char *vendorName;\n\tconst char *productName;\n\t__u8 useProtocol;\n\t__u8 useTransport;\n\tint (*initFunction)(struct us_data *);\n};\n\nstruct usage_priority {\n\t__u32 usage;\n\tbool global;\n\tunsigned int slot_overwrite;\n};\n\nstruct usb2_clock_sel_priv {\n\tvoid *base;\n\tstruct clk_hw hw;\n\tstruct clk_bulk_data clks[2];\n\tstruct reset_control *rsts;\n\tbool extal;\n\tbool xtal;\n};\n\nstruct usb2_lpm_parameters {\n\tunsigned int besl;\n\tint timeout;\n};\n\nstruct usb3503 {\n\tenum usb3503_mode mode;\n\tstruct regmap *regmap;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tu8 port_off_mask;\n\tstruct gpio_desc *bypass;\n\tstruct gpio_desc *intn;\n\tstruct gpio_desc *reset;\n\tstruct gpio_desc *connect;\n\tbool secondary_ref_clk;\n};\n\nstruct usb3503_platform_data {\n\tenum usb3503_mode initial_mode;\n\tu8 port_off_mask;\n};\n\nstruct usb3_lpm_parameters {\n\tunsigned int mel;\n\tunsigned int pel;\n\tunsigned int sel;\n\tint timeout;\n};\n\nstruct usb_anchor {\n\tstruct list_head urb_list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tatomic_t suspend_wakeups;\n\tunsigned int poisoned: 1;\n};\n\nstruct usb_bos_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumDeviceCaps;\n} __attribute__((packed));\n\nstruct usb_bus {\n\tstruct device *controller;\n\tstruct device *sysdev;\n\tint busnum;\n\tconst char *bus_name;\n\tu8 uses_pio_for_control;\n\tu8 otg_port;\n\tunsigned int is_b_host: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int no_stop_on_short: 1;\n\tunsigned int no_sg_constraint: 1;\n\tunsigned int sg_tablesize;\n\tint devnum_next;\n\tstruct mutex devnum_next_mutex;\n\tlong unsigned int devmap[2];\n\tstruct usb_device *root_hub;\n\tstruct usb_bus *hs_companion;\n\tint bandwidth_allocated;\n\tint bandwidth_int_reqs;\n\tint bandwidth_isoc_reqs;\n\tunsigned int resuming_ports;\n};\n\nstruct usb_cdc_acm_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n};\n\nstruct usb_cdc_call_mgmt_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n\t__u8 bDataInterface;\n};\n\nstruct usb_cdc_country_functional_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iCountryCodeRelDate;\n\tunion {\n\t\t__le16 wCountryCode0;\n\t\tstruct {\n\t\t\tstruct {} __empty_wCountryCodes;\n\t\t\t__le16 wCountryCodes[0];\n\t\t};\n\t};\n};\n\nstruct usb_cdc_dmm_desc {\n\t__u8 bFunctionLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubtype;\n\t__u16 bcdVersion;\n\t__le16 wMaxCommand;\n} __attribute__((packed));\n\nstruct usb_cdc_ether_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iMACAddress;\n\t__le32 bmEthernetStatistics;\n\t__le16 wMaxSegmentSize;\n\t__le16 wNumberMCFilters;\n\t__u8 bNumberPowerFilters;\n} __attribute__((packed));\n\nstruct usb_cdc_header_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdCDC;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMVersion;\n\t__le16 wMaxControlMessage;\n\t__u8 bNumberFilters;\n\t__u8 bMaxFilterSize;\n\t__le16 wMaxSegmentSize;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_extended_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMExtendedVersion;\n\t__u8 bMaxOutstandingCommandMessages;\n\t__le16 wMTU;\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n\t__u8 bGUID[16];\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_detail_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bGuidDescriptorType;\n\t__u8 bDetailData[0];\n};\n\nstruct usb_cdc_ncm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdNcmVersion;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_network_terminal_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bEntityId;\n\t__u8 iName;\n\t__u8 bChannelIndex;\n\t__u8 bPhysicalInterface;\n};\n\nstruct usb_cdc_obex_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n} __attribute__((packed));\n\nstruct usb_cdc_union_desc;\n\nstruct usb_cdc_parsed_header {\n\tstruct usb_cdc_union_desc *usb_cdc_union_desc;\n\tstruct usb_cdc_header_desc *usb_cdc_header_desc;\n\tstruct usb_cdc_call_mgmt_descriptor *usb_cdc_call_mgmt_descriptor;\n\tstruct usb_cdc_acm_descriptor *usb_cdc_acm_descriptor;\n\tstruct usb_cdc_country_functional_desc *usb_cdc_country_functional_desc;\n\tstruct usb_cdc_network_terminal_desc *usb_cdc_network_terminal_desc;\n\tstruct usb_cdc_ether_desc *usb_cdc_ether_desc;\n\tstruct usb_cdc_dmm_desc *usb_cdc_dmm_desc;\n\tstruct usb_cdc_mdlm_desc *usb_cdc_mdlm_desc;\n\tstruct usb_cdc_mdlm_detail_desc *usb_cdc_mdlm_detail_desc;\n\tstruct usb_cdc_obex_desc *usb_cdc_obex_desc;\n\tstruct usb_cdc_ncm_desc *usb_cdc_ncm_desc;\n\tstruct usb_cdc_mbim_desc *usb_cdc_mbim_desc;\n\tstruct usb_cdc_mbim_extended_desc *usb_cdc_mbim_extended_desc;\n\tbool phonet_magic_present;\n};\n\nstruct usb_cdc_union_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bMasterInterface0;\n\tunion {\n\t\t__u8 bSlaveInterface0;\n\t\tstruct {\n\t\t\tstruct {} __empty_bSlaveInterfaces;\n\t\t\t__u8 bSlaveInterfaces[0];\n\t\t};\n\t};\n};\n\nstruct usb_class_driver {\n\tchar *name;\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tconst struct file_operations *fops;\n\tint minor_base;\n};\n\nstruct usb_config_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumInterfaces;\n\t__u8 bConfigurationValue;\n\t__u8 iConfiguration;\n\t__u8 bmAttributes;\n\t__u8 bMaxPower;\n} __attribute__((packed));\n\nstruct usb_conn_info {\n\tstruct device *dev;\n\tint conn_id;\n\tstruct usb_role_switch *role_sw;\n\tenum usb_role last_role;\n\tstruct regulator *vbus;\n\tstruct delayed_work dw_det;\n\tlong unsigned int debounce_jiffies;\n\tstruct gpio_desc *id_gpiod;\n\tstruct gpio_desc *vbus_gpiod;\n\tint id_irq;\n\tint vbus_irq;\n\tstruct power_supply_desc desc;\n\tstruct power_supply *charger;\n\tbool initial_detection;\n};\n\nstruct usb_dcd_config_params {\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n\t__u8 besl_baseline;\n\t__u8 besl_deep;\n};\n\nstruct usb_descriptor_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n};\n\nstruct usb_dev_cap_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_dev_state {\n\tstruct list_head list;\n\tstruct usb_device *dev;\n\tstruct file *file;\n\tspinlock_t lock;\n\tstruct list_head async_pending;\n\tstruct list_head async_completed;\n\tstruct list_head memory_list;\n\twait_queue_head_t wait;\n\twait_queue_head_t wait_for_resume;\n\tunsigned int discsignr;\n\tstruct pid *disc_pid;\n\tconst struct cred *cred;\n\tsigval_t disccontext;\n\tlong unsigned int ifclaimed;\n\tu32 disabled_bulk_eps;\n\tlong unsigned int interface_allowed_mask;\n\tint not_yet_resumed;\n\tbool suspend_allowed;\n\tbool privileges_dropped;\n};\n\nstruct usb_endpoint_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bEndpointAddress;\n\t__u8 bmAttributes;\n\t__le16 wMaxPacketSize;\n\t__u8 bInterval;\n\t__u8 bRefresh;\n\t__u8 bSynchAddress;\n} __attribute__((packed));\n\nstruct usb_ss_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bMaxBurst;\n\t__u8 bmAttributes;\n\t__le16 wBytesPerInterval;\n};\n\nstruct usb_ssp_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wReseved;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_eusb2_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wMaxPacketSize;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_host_endpoint {\n\tstruct usb_endpoint_descriptor desc;\n\tstruct usb_ss_ep_comp_descriptor ss_ep_comp;\n\tstruct usb_ssp_isoc_ep_comp_descriptor ssp_isoc_ep_comp;\n\tstruct usb_eusb2_isoc_ep_comp_descriptor eusb2_isoc_ep_comp;\n\tlong: 0;\n\tstruct list_head urb_list;\n\tvoid *hcpriv;\n\tstruct ep_device *ep_dev;\n\tunsigned char *extra;\n\tint extralen;\n\tint enabled;\n\tint streams;\n\tlong: 0;\n} __attribute__((packed));\n\nstruct usb_device_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__le16 idVendor;\n\t__le16 idProduct;\n\t__le16 bcdDevice;\n\t__u8 iManufacturer;\n\t__u8 iProduct;\n\t__u8 iSerialNumber;\n\t__u8 bNumConfigurations;\n};\n\nstruct usb_host_bos;\n\nstruct usb_host_config;\n\nstruct usb_device {\n\tint devnum;\n\tchar devpath[16];\n\tu32 route;\n\tenum usb_device_state state;\n\tenum usb_device_speed speed;\n\tunsigned int rx_lanes;\n\tunsigned int tx_lanes;\n\tenum usb_ssp_rate ssp_rate;\n\tstruct usb_tt *tt;\n\tint ttport;\n\tunsigned int toggle[2];\n\tstruct usb_device *parent;\n\tstruct usb_bus *bus;\n\tstruct usb_host_endpoint ep0;\n\tstruct device dev;\n\tstruct usb_device_descriptor descriptor;\n\tstruct usb_host_bos *bos;\n\tstruct usb_host_config *config;\n\tstruct usb_host_config *actconfig;\n\tstruct usb_host_endpoint *ep_in[16];\n\tstruct usb_host_endpoint *ep_out[16];\n\tchar **rawdescriptors;\n\tshort unsigned int bus_mA;\n\tu8 portnum;\n\tu8 level;\n\tu8 devaddr;\n\tunsigned int can_submit: 1;\n\tunsigned int persist_enabled: 1;\n\tunsigned int reset_in_progress: 1;\n\tunsigned int have_langid: 1;\n\tunsigned int authorized: 1;\n\tunsigned int authenticated: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int lpm_devinit_allow: 1;\n\tunsigned int usb2_hw_lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_besl_capable: 1;\n\tunsigned int usb2_hw_lpm_enabled: 1;\n\tunsigned int usb2_hw_lpm_allowed: 1;\n\tunsigned int usb3_lpm_u1_enabled: 1;\n\tunsigned int usb3_lpm_u2_enabled: 1;\n\tint string_langid;\n\tchar *product;\n\tchar *manufacturer;\n\tchar *serial;\n\tstruct list_head filelist;\n\tint maxchild;\n\tu32 quirks;\n\tatomic_t urbnum;\n\tlong unsigned int active_duration;\n\tlong unsigned int connect_time;\n\tunsigned int do_remote_wakeup: 1;\n\tunsigned int reset_resume: 1;\n\tunsigned int port_is_suspended: 1;\n\tunsigned int offload_at_suspend: 1;\n\tint offload_usage;\n\tenum usb_link_tunnel_mode tunnel_mode;\n\tstruct device_link *usb4_link;\n\tint slot_id;\n\tstruct usb2_lpm_parameters l1_params;\n\tstruct usb3_lpm_parameters u1_params;\n\tstruct usb3_lpm_parameters u2_params;\n\tunsigned int lpm_disable_count;\n\tu16 hub_delay;\n\tunsigned int use_generic_driver: 1;\n};\n\nstruct usb_device_id;\n\nstruct usb_device_driver {\n\tconst char *name;\n\tbool (*match)(struct usb_device *);\n\tint (*probe)(struct usb_device *);\n\tvoid (*disconnect)(struct usb_device *);\n\tint (*suspend)(struct usb_device *, pm_message_t);\n\tint (*resume)(struct usb_device *, pm_message_t);\n\tint (*choose_configuration)(struct usb_device *);\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tconst struct usb_device_id *id_table;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int generic_subclass: 1;\n};\n\nstruct usb_device_id {\n\t__u16 match_flags;\n\t__u16 idVendor;\n\t__u16 idProduct;\n\t__u16 bcdDevice_lo;\n\t__u16 bcdDevice_hi;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 bInterfaceNumber;\n\tkernel_ulong_t driver_info;\n};\n\nstruct usb_dynids {\n\tstruct list_head list;\n};\n\nstruct usb_driver {\n\tconst char *name;\n\tint (*probe)(struct usb_interface *, const struct usb_device_id *);\n\tvoid (*disconnect)(struct usb_interface *);\n\tint (*unlocked_ioctl)(struct usb_interface *, unsigned int, void *);\n\tint (*suspend)(struct usb_interface *, pm_message_t);\n\tint (*resume)(struct usb_interface *);\n\tint (*reset_resume)(struct usb_interface *);\n\tint (*pre_reset)(struct usb_interface *);\n\tint (*post_reset)(struct usb_interface *);\n\tvoid (*shutdown)(struct usb_interface *);\n\tconst struct usb_device_id *id_table;\n\tconst struct attribute_group **dev_groups;\n\tstruct usb_dynids dynids;\n\tstruct device_driver driver;\n\tunsigned int no_dynamic_id: 1;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int disable_hub_initiated_lpm: 1;\n\tunsigned int soft_unbind: 1;\n};\n\nstruct usb_dynid {\n\tstruct list_head node;\n\tstruct usb_device_id id;\n};\n\nstruct usb_ehci_pdata {\n\tint caps_offset;\n\tunsigned int has_tt: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int no_io_watchdog: 1;\n\tunsigned int reset_on_resume: 1;\n\tunsigned int dma_mask_64: 1;\n\tunsigned int spurious_oc: 1;\n\tint (*power_on)(struct platform_device *);\n\tvoid (*power_off)(struct platform_device *);\n\tvoid (*power_suspend)(struct platform_device *);\n\tint (*pre_setup)(struct usb_hcd *);\n};\n\nstruct usb_ep_ops {\n\tint (*enable)(struct usb_ep *, const struct usb_endpoint_descriptor *);\n\tint (*disable)(struct usb_ep *);\n\tvoid (*dispose)(struct usb_ep *);\n\tstruct usb_request * (*alloc_request)(struct usb_ep *, gfp_t);\n\tvoid (*free_request)(struct usb_ep *, struct usb_request *);\n\tint (*queue)(struct usb_ep *, struct usb_request *, gfp_t);\n\tint (*dequeue)(struct usb_ep *, struct usb_request *);\n\tint (*set_halt)(struct usb_ep *, int);\n\tint (*set_wedge)(struct usb_ep *);\n\tint (*fifo_status)(struct usb_ep *);\n\tvoid (*fifo_flush)(struct usb_ep *);\n};\n\nstruct usb_ext_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__le32 bmAttributes;\n} __attribute__((packed));\n\nstruct usb_extcon_info {\n\tstruct device *dev;\n\tstruct extcon_dev *edev;\n\tstruct gpio_desc *id_gpiod;\n\tstruct gpio_desc *vbus_gpiod;\n\tint id_irq;\n\tint vbus_irq;\n\tlong unsigned int debounce_jiffies;\n\tstruct delayed_work wq_detcable;\n};\n\nstruct usb_gadget_driver {\n\tchar *function;\n\tenum usb_device_speed max_speed;\n\tint (*bind)(struct usb_gadget *, struct usb_gadget_driver *);\n\tvoid (*unbind)(struct usb_gadget *);\n\tint (*setup)(struct usb_gadget *, const struct usb_ctrlrequest *);\n\tvoid (*disconnect)(struct usb_gadget *);\n\tvoid (*suspend)(struct usb_gadget *);\n\tvoid (*resume)(struct usb_gadget *);\n\tvoid (*reset)(struct usb_gadget *);\n\tstruct device_driver driver;\n\tchar *udc_name;\n\tunsigned int match_existing_only: 1;\n\tbool is_bound: 1;\n};\n\nstruct usb_gadget_ops {\n\tint (*get_frame)(struct usb_gadget *);\n\tint (*wakeup)(struct usb_gadget *);\n\tint (*func_wakeup)(struct usb_gadget *, int);\n\tint (*set_remote_wakeup)(struct usb_gadget *, int);\n\tint (*set_selfpowered)(struct usb_gadget *, int);\n\tint (*vbus_session)(struct usb_gadget *, int);\n\tint (*vbus_draw)(struct usb_gadget *, unsigned int);\n\tint (*pullup)(struct usb_gadget *, int);\n\tint (*ioctl)(struct usb_gadget *, unsigned int, long unsigned int);\n\tvoid (*get_config_params)(struct usb_gadget *, struct usb_dcd_config_params *);\n\tint (*udc_start)(struct usb_gadget *, struct usb_gadget_driver *);\n\tint (*udc_stop)(struct usb_gadget *);\n\tvoid (*udc_set_speed)(struct usb_gadget *, enum usb_device_speed);\n\tvoid (*udc_set_ssp_rate)(struct usb_gadget *, enum usb_ssp_rate);\n\tvoid (*udc_async_callbacks)(struct usb_gadget *, bool);\n\tstruct usb_ep * (*match_ep)(struct usb_gadget *, struct usb_endpoint_descriptor *, struct usb_ss_ep_comp_descriptor *);\n\tint (*check_config)(struct usb_gadget *);\n};\n\nstruct usb_phy_roothub;\n\nstruct usb_hcd {\n\tstruct usb_bus self;\n\tstruct kref kref;\n\tconst char *product_desc;\n\tint speed;\n\tchar irq_descr[24];\n\tstruct timer_list rh_timer;\n\tstruct urb *status_urb;\n\tstruct work_struct wakeup_work;\n\tstruct work_struct died_work;\n\tconst struct hc_driver *driver;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_phy_roothub *phy_roothub;\n\tlong unsigned int flags;\n\tenum usb_dev_authorize_policy dev_policy;\n\tunsigned int rh_registered: 1;\n\tunsigned int rh_pollable: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int msi_enabled: 1;\n\tunsigned int skip_phy_initialization: 1;\n\tunsigned int uses_new_polling: 1;\n\tunsigned int has_tt: 1;\n\tunsigned int amd_resume_bug: 1;\n\tunsigned int can_do_streams: 1;\n\tunsigned int tpl_support: 1;\n\tunsigned int cant_recv_wakeups: 1;\n\tunsigned int irq;\n\tvoid *regs;\n\tresource_size_t rsrc_start;\n\tresource_size_t rsrc_len;\n\tunsigned int power_budget;\n\tstruct giveback_urb_bh high_prio_bh;\n\tstruct giveback_urb_bh low_prio_bh;\n\tstruct mutex *address0_mutex;\n\tstruct mutex *bandwidth_mutex;\n\tstruct usb_hcd *shared_hcd;\n\tstruct usb_hcd *primary_hcd;\n\tstruct dma_pool *pool[4];\n\tint state;\n\tstruct gen_pool *localmem_pool;\n\tlong unsigned int hcd_priv[0];\n};\n\nstruct usb_ss_cap_descriptor;\n\nstruct usb_ssp_cap_descriptor;\n\nstruct usb_ss_container_id_descriptor;\n\nstruct usb_ptm_cap_descriptor;\n\nstruct usb_host_bos {\n\tstruct usb_bos_descriptor *desc;\n\tstruct usb_ext_cap_descriptor *ext_cap;\n\tstruct usb_ss_cap_descriptor *ss_cap;\n\tstruct usb_ssp_cap_descriptor *ssp_cap;\n\tstruct usb_ss_container_id_descriptor *ss_id;\n\tstruct usb_ptm_cap_descriptor *ptm_cap;\n};\n\nstruct usb_interface_assoc_descriptor;\n\nstruct usb_interface_cache;\n\nstruct usb_host_config {\n\tstruct usb_config_descriptor desc;\n\tchar *string;\n\tstruct usb_interface_assoc_descriptor *intf_assoc[16];\n\tstruct usb_interface *interface[32];\n\tstruct usb_interface_cache *intf_cache[32];\n\tunsigned char *extra;\n\tint extralen;\n};\n\nstruct usb_interface_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bInterfaceNumber;\n\t__u8 bAlternateSetting;\n\t__u8 bNumEndpoints;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 iInterface;\n};\n\nstruct usb_host_interface {\n\tstruct usb_interface_descriptor desc;\n\tint extralen;\n\tunsigned char *extra;\n\tstruct usb_host_endpoint *endpoint;\n\tchar *string;\n};\n\nstruct usb_hub_status {\n\t__le16 wHubStatus;\n\t__le16 wHubChange;\n};\n\nstruct usb_port_status {\n\t__le16 wPortStatus;\n\t__le16 wPortChange;\n\t__le32 dwExtPortStatus;\n};\n\nstruct usb_tt {\n\tstruct usb_device *hub;\n\tint multi;\n\tunsigned int think_time;\n\tvoid *hcpriv;\n\tspinlock_t lock;\n\tstruct list_head clear_list;\n\tstruct work_struct clear_work;\n};\n\nstruct usb_hub_descriptor;\n\nstruct usb_port;\n\nstruct usb_hub {\n\tstruct device *intfdev;\n\tstruct usb_device *hdev;\n\tstruct kref kref;\n\tstruct urb *urb;\n\tu8 (*buffer)[8];\n\tunion {\n\t\tstruct usb_hub_status hub;\n\t\tstruct usb_port_status port;\n\t} *status;\n\tstruct mutex status_mutex;\n\tint error;\n\tint nerrors;\n\tlong unsigned int event_bits[1];\n\tlong unsigned int change_bits[1];\n\tlong unsigned int removed_bits[1];\n\tlong unsigned int wakeup_bits[1];\n\tlong unsigned int power_bits[1];\n\tlong unsigned int child_usage_bits[1];\n\tlong unsigned int warm_reset_bits[1];\n\tstruct usb_hub_descriptor *descriptor;\n\tstruct usb_tt tt;\n\tunsigned int mA_per_port;\n\tunsigned int wakeup_enabled_descendants;\n\tunsigned int limited_power: 1;\n\tunsigned int quiescing: 1;\n\tunsigned int disconnected: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int quirk_disable_autosuspend: 1;\n\tunsigned int quirk_check_port_auto_suspend: 1;\n\tunsigned int has_indicators: 1;\n\tu8 indicator[31];\n\tstruct delayed_work leds;\n\tstruct delayed_work init_work;\n\tstruct delayed_work post_resume_work;\n\tstruct work_struct events;\n\tspinlock_t irq_urb_lock;\n\tstruct timer_list irq_urb_retry;\n\tstruct usb_port **ports;\n\tstruct list_head onboard_devs;\n};\n\nstruct usb_hub_descriptor {\n\t__u8 bDescLength;\n\t__u8 bDescriptorType;\n\t__u8 bNbrPorts;\n\t__le16 wHubCharacteristics;\n\t__u8 bPwrOn2PwrGood;\n\t__u8 bHubContrCurrent;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 DeviceRemovable[4];\n\t\t\t__u8 PortPwrCtrlMask[4];\n\t\t} hs;\n\t\tstruct {\n\t\t\t__u8 bHubHdrDecLat;\n\t\t\t__le16 wHubDelay;\n\t\t\t__le16 DeviceRemovable;\n\t\t} __attribute__((packed)) ss;\n\t} u;\n} __attribute__((packed));\n\nstruct usb_interface {\n\tstruct usb_host_interface *altsetting;\n\tstruct usb_host_interface *cur_altsetting;\n\tunsigned int num_altsetting;\n\tstruct usb_interface_assoc_descriptor *intf_assoc;\n\tint minor;\n\tenum usb_interface_condition condition;\n\tunsigned int sysfs_files_created: 1;\n\tunsigned int ep_devs_created: 1;\n\tunsigned int unregistering: 1;\n\tunsigned int needs_remote_wakeup: 1;\n\tunsigned int needs_altsetting0: 1;\n\tunsigned int needs_binding: 1;\n\tunsigned int resetting_device: 1;\n\tunsigned int authorized: 1;\n\tenum usb_wireless_status wireless_status;\n\tstruct work_struct wireless_status_work;\n\tstruct device dev;\n\tstruct device *usb_dev;\n\tstruct work_struct reset_ws;\n};\n\nstruct usb_interface_assoc_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bFirstInterface;\n\t__u8 bInterfaceCount;\n\t__u8 bFunctionClass;\n\t__u8 bFunctionSubClass;\n\t__u8 bFunctionProtocol;\n\t__u8 iFunction;\n};\n\nstruct usb_interface_cache {\n\tunsigned int num_altsetting;\n\tstruct kref ref;\n\tstruct usb_host_interface altsetting[0];\n};\n\nstruct usb_memory {\n\tstruct list_head memlist;\n\tint vma_use_count;\n\tint urb_use_count;\n\tu32 size;\n\tvoid *mem;\n\tdma_addr_t dma_handle;\n\tlong unsigned int vm_start;\n\tstruct usb_dev_state *ps;\n};\n\nstruct usb_ohci_pdata {\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int no_big_frame_no: 1;\n\tunsigned int num_ports;\n\tint (*power_on)(struct platform_device *);\n\tvoid (*power_off)(struct platform_device *);\n\tvoid (*power_suspend)(struct platform_device *);\n};\n\nstruct usb_otg_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bmAttributes;\n};\n\nstruct usb_phy_generic {\n\tstruct usb_phy phy;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tstruct regulator *vcc;\n\tstruct gpio_desc *gpiod_reset;\n\tstruct gpio_desc *gpiod_vbus;\n\tstruct regulator *vbus_draw;\n\tbool vbus_draw_enabled;\n\tlong unsigned int mA;\n\tunsigned int vbus;\n};\n\nstruct usb_phy_io_ops {\n\tint (*read)(struct usb_phy *, u32);\n\tint (*write)(struct usb_phy *, u32, u32);\n};\n\nstruct usb_phy_roothub {\n\tstruct phy *phy;\n\tstruct list_head list;\n};\n\nstruct usb_port {\n\tstruct usb_device *child;\n\tstruct device dev;\n\tstruct usb_dev_state *port_owner;\n\tstruct usb_port *peer;\n\tstruct typec_connector *connector;\n\tstruct dev_pm_qos_request *req;\n\tenum usb_port_connect_type connect_type;\n\tenum usb_device_state state;\n\tstruct kernfs_node *state_kn;\n\tusb_port_location_t location;\n\tstruct mutex status_lock;\n\tu32 over_current_count;\n\tu8 portnum;\n\tu32 quirks;\n\tunsigned int early_stop: 1;\n\tunsigned int ignore_event: 1;\n\tunsigned int is_superspeed: 1;\n\tunsigned int usb3_lpm_u1_permit: 1;\n\tunsigned int usb3_lpm_u2_permit: 1;\n};\n\nstruct usb_ptm_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_qualifier_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__u8 bNumConfigurations;\n\t__u8 bRESERVED;\n};\n\nstruct usb_role_switch {\n\tstruct device dev;\n\tstruct lock_class_key key;\n\tstruct mutex lock;\n\tstruct module *module;\n\tenum usb_role role;\n\tbool registered;\n\tstruct device *usb2_port;\n\tstruct device *usb3_port;\n\tstruct device *udc;\n\tusb_role_switch_set_t set;\n\tusb_role_switch_get_t get;\n\tbool allow_userspace_control;\n};\n\nstruct usb_set_sel_req {\n\t__u8 u1_sel;\n\t__u8 u1_pel;\n\t__le16 u2_sel;\n\t__le16 u2_pel;\n};\n\nstruct usb_ss_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bmAttributes;\n\t__le16 wSpeedSupported;\n\t__u8 bFunctionalitySupport;\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n};\n\nstruct usb_ss_container_id_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__u8 ContainerID[16];\n};\n\nstruct usb_ssp_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__le32 bmAttributes;\n\t__le16 wFunctionalitySupport;\n\t__le16 wReserved;\n\tunion {\n\t\t__le32 legacy_padding;\n\t\tstruct {\n\t\t\tstruct {} __empty_bmSublinkSpeedAttr;\n\t\t\t__le32 bmSublinkSpeedAttr[0];\n\t\t};\n\t};\n};\n\nstruct usb_tt_clear {\n\tstruct list_head clear_list;\n\tunsigned int tt;\n\tu16 devinfo;\n\tstruct usb_hcd *hcd;\n\tstruct usb_host_endpoint *ep;\n};\n\nstruct usb_udc {\n\tstruct usb_gadget_driver *driver;\n\tstruct usb_gadget *gadget;\n\tstruct device dev;\n\tstruct list_head list;\n\tbool vbus;\n\tbool started;\n\tbool allow_connect;\n\tstruct work_struct vbus_work;\n\tstruct mutex connect_lock;\n};\n\nstruct usbdevfs_bulktransfer {\n\tunsigned int ep;\n\tunsigned int len;\n\tunsigned int timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_bulktransfer32 {\n\tcompat_uint_t ep;\n\tcompat_uint_t len;\n\tcompat_uint_t timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_connectinfo {\n\tunsigned int devnum;\n\tunsigned char slow;\n};\n\nstruct usbdevfs_conninfo_ex {\n\t__u32 size;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 speed;\n\t__u8 num_ports;\n\t__u8 ports[7];\n};\n\nstruct usbdevfs_ctrltransfer {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\t__u32 timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_ctrltransfer32 {\n\tu8 bRequestType;\n\tu8 bRequest;\n\tu16 wValue;\n\tu16 wIndex;\n\tu16 wLength;\n\tu32 timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_disconnect_claim {\n\tunsigned int interface;\n\tunsigned int flags;\n\tchar driver[256];\n};\n\nstruct usbdevfs_disconnectsignal {\n\tunsigned int signr;\n\tvoid *context;\n};\n\nstruct usbdevfs_disconnectsignal32 {\n\tcompat_int_t signr;\n\tcompat_caddr_t context;\n};\n\nstruct usbdevfs_getdriver {\n\tunsigned int interface;\n\tchar driver[256];\n};\n\nstruct usbdevfs_hub_portinfo {\n\tchar nports;\n\tchar port[127];\n};\n\nstruct usbdevfs_ioctl {\n\tint ifno;\n\tint ioctl_code;\n\tvoid *data;\n};\n\nstruct usbdevfs_ioctl32 {\n\ts32 ifno;\n\ts32 ioctl_code;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_iso_packet_desc {\n\tunsigned int length;\n\tunsigned int actual_length;\n\tunsigned int status;\n};\n\nstruct usbdevfs_setinterface {\n\tunsigned int interface;\n\tunsigned int altsetting;\n};\n\nstruct usbdevfs_streams {\n\tunsigned int num_streams;\n\tunsigned int num_eps;\n\tunsigned char eps[0];\n};\n\nstruct usbdevfs_urb {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tint status;\n\tunsigned int flags;\n\tvoid *buffer;\n\tint buffer_length;\n\tint actual_length;\n\tint start_frame;\n\tunion {\n\t\tint number_of_packets;\n\t\tunsigned int stream_id;\n\t};\n\tint error_count;\n\tunsigned int signr;\n\tvoid *usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbdevfs_urb32 {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tcompat_int_t status;\n\tcompat_uint_t flags;\n\tcompat_caddr_t buffer;\n\tcompat_int_t buffer_length;\n\tcompat_int_t actual_length;\n\tcompat_int_t start_frame;\n\tcompat_int_t number_of_packets;\n\tcompat_int_t error_count;\n\tcompat_uint_t signr;\n\tcompat_caddr_t usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbhid_device {\n\tstruct hid_device *hid;\n\tstruct usb_interface *intf;\n\tint ifnum;\n\tunsigned int bufsize;\n\tstruct urb *urbin;\n\tchar *inbuf;\n\tdma_addr_t inbuf_dma;\n\tstruct urb *urbctrl;\n\tstruct usb_ctrlrequest *cr;\n\tstruct hid_control_fifo ctrl[256];\n\tunsigned char ctrlhead;\n\tunsigned char ctrltail;\n\tchar *ctrlbuf;\n\tdma_addr_t ctrlbuf_dma;\n\tlong unsigned int last_ctrl;\n\tstruct urb *urbout;\n\tstruct hid_output_fifo out[256];\n\tunsigned char outhead;\n\tunsigned char outtail;\n\tchar *outbuf;\n\tdma_addr_t outbuf_dma;\n\tlong unsigned int last_out;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tlong unsigned int iofl;\n\tstruct timer_list io_retry;\n\tlong unsigned int stop_retry;\n\tunsigned int retry_delay;\n\tstruct work_struct reset_work;\n\twait_queue_head_t wait;\n};\n\nstruct usbmisc_ops {\n\tint (*init)(struct imx_usbmisc_data *);\n\tint (*post)(struct imx_usbmisc_data *);\n\tint (*set_wakeup)(struct imx_usbmisc_data *, bool);\n\tint (*hsic_set_connect)(struct imx_usbmisc_data *);\n\tint (*hsic_set_clk)(struct imx_usbmisc_data *, bool);\n\tint (*charger_detection)(struct imx_usbmisc_data *);\n\tint (*power_lost_check)(struct imx_usbmisc_data *);\n\tvoid (*pullup)(struct imx_usbmisc_data *, bool);\n\tvoid (*vbus_comparator_on)(struct imx_usbmisc_data *, bool);\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct used_entry {\n\tu32 id;\n\tu32 len;\n};\n\nstruct user_access_state {\n\tu64 por_el0;\n};\n\nstruct user_arg_ptr {\n\tbool is_compat;\n\tunion {\n\t\tconst char * const *native;\n\t\tconst compat_uptr_t *compat;\n\t} ptr;\n};\n\nstruct za_context;\n\nstruct zt_context;\n\nstruct user_ctxs {\n\tstruct fpsimd_context *fpsimd;\n\tu32 fpsimd_size;\n\tstruct sve_context *sve;\n\tu32 sve_size;\n\tstruct tpidr2_context *tpidr2;\n\tu32 tpidr2_size;\n\tstruct za_context *za;\n\tu32 za_size;\n\tstruct zt_context *zt;\n\tu32 zt_size;\n\tstruct fpmr_context *fpmr;\n\tu32 fpmr_size;\n\tstruct poe_context *poe;\n\tu32 poe_size;\n\tstruct gcs_context *gcs;\n\tu32 gcs_size;\n};\n\nstruct user_evtchn {\n\tstruct rb_node node;\n\tstruct per_user_data *user;\n\tevtchn_port_t port;\n\tbool enabled;\n\tbool unbinding;\n};\n\nstruct user_gcs {\n\t__u64 features_enabled;\n\t__u64 features_locked;\n\t__u64 gcspr_el0;\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[12];\n\tlong int rlimit_max[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct user_pac_mask {\n\t__u64 data_mask;\n\t__u64 insn_mask;\n};\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n};\n\nstruct user_sve_header {\n\t__u32 size;\n\t__u32 max_size;\n\t__u16 vl;\n\t__u16 max_vl;\n\t__u16 flags;\n\t__u16 __reserved;\n};\n\nstruct user_threshold {\n\tstruct list_head list_node;\n\tint temperature;\n\tint direction;\n};\n\nstruct user_za_header {\n\t__u32 size;\n\t__u32 max_size;\n\t__u16 vl;\n\t__u16 max_vl;\n\t__u16 flags;\n\t__u16 __reserved;\n};\n\nstruct userspace_data {\n\tlong unsigned int user_frequency;\n\tbool valid;\n};\n\nstruct userspace_policy {\n\tunsigned int is_managed;\n\tunsigned int setspeed;\n\tstruct mutex mutex;\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tlong unsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct ustring_buffer {\n\tchar buffer[1024];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct utmi_clk_param {\n\tu32 osc_frequency;\n\tu8 enable_delay_count;\n\tu16 stable_count;\n\tu8 active_delay_count;\n\tu16 xtal_freq_count;\n};\n\nstruct utmi_clk_param___2 {\n\tu32 osc_frequency;\n\tu8 enable_delay_count;\n\tu8 stable_count;\n\tu8 active_delay_count;\n\tu8 xtal_freq_count;\n};\n\nstruct utp_cmd_rsp {\n\t__be32 residual_transfer_count;\n\t__be32 reserved[4];\n\t__be16 sense_data_len;\n\tu8 sense_data[18];\n};\n\nstruct utp_task_req_desc {\n\tstruct request_desc_header header;\n\tstruct {\n\t\tstruct utp_upiu_header req_header;\n\t\t__be32 input_param1;\n\t\t__be32 input_param2;\n\t\t__be32 input_param3;\n\t\t__be32 __reserved1[2];\n\t} upiu_req;\n\tstruct {\n\t\tstruct utp_upiu_header rsp_header;\n\t\t__be32 output_param1;\n\t\t__be32 output_param2;\n\t\t__be32 __reserved2[3];\n\t} upiu_rsp;\n};\n\nstruct utp_transfer_cmd_desc {\n\tu8 command_upiu[512];\n\tu8 response_upiu[512];\n\tu8 prd_table[0];\n};\n\nstruct utp_transfer_req_desc {\n\tstruct request_desc_header header;\n\t__le64 command_desc_base_addr;\n\t__le16 response_upiu_length;\n\t__le16 response_upiu_offset;\n\t__le16 prd_table_length;\n\t__le16 prd_table_offset;\n};\n\nstruct utp_upiu_query_v4_0 {\n\t__u8 opcode;\n\t__u8 idn;\n\t__u8 index;\n\t__u8 selector;\n\t__u8 osf3;\n\t__u8 osf4;\n\t__be16 osf5;\n\t__be32 osf6;\n\t__be32 osf7;\n\t__be32 reserved;\n};\n\nstruct utp_upiu_rsp {\n\tstruct utp_upiu_header header;\n\tunion {\n\t\tstruct utp_cmd_rsp sr;\n\t\tstruct utp_upiu_query qr;\n\t};\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct v2m_data {\n\tstruct list_head entry;\n\tstruct fwnode_handle *fwnode;\n\tstruct resource res;\n\tvoid *base;\n\tu32 spi_start;\n\tu32 nr_spis;\n\tu32 spi_offset;\n\tlong unsigned int *bm;\n\tu32 flags;\n};\n\nstruct v9fs_context {\n\tstruct p9_client_opts client_opts;\n\tstruct p9_fd_opts fd_opts;\n\tstruct p9_rdma_opts rdma_opts;\n\tstruct p9_session_opts session_opts;\n};\n\nstruct v9fs_inode {\n\tstruct netfs_inode netfs;\n\tstruct p9_qid qid;\n\tunsigned int cache_validity;\n\tstruct mutex v_mutex;\n};\n\nstruct v9fs_session_info {\n\tunsigned int flags;\n\tunsigned char nodev;\n\tshort unsigned int debug;\n\tunsigned int afid;\n\tunsigned int cache;\n\tchar *uname;\n\tchar *aname;\n\tunsigned int maxdata;\n\tkuid_t dfltuid;\n\tkgid_t dfltgid;\n\tkuid_t uid;\n\tstruct p9_client *clnt;\n\tstruct list_head slist;\n\tstruct rw_semaphore rename_sem;\n\tlong int session_lock_timeout;\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct value_to_freq {\n\tu32 value;\n\tu8 freq;\n};\n\nstruct value_to_name_map {\n\tint value;\n\tconst char *name;\n};\n\nstruct variable_validate {\n\tefi_guid_t vendor;\n\tchar *name;\n\tbool (*validate)(efi_char16_t *, int, u8 *, long unsigned int);\n};\n\nstruct variant_data {\n\tunsigned int clkreg;\n\tunsigned int clkreg_enable;\n\tunsigned int clkreg_8bit_bus_enable;\n\tunsigned int clkreg_neg_edge_enable;\n\tunsigned int cmdreg_cpsm_enable;\n\tunsigned int cmdreg_lrsp_crc;\n\tunsigned int cmdreg_srsp_crc;\n\tunsigned int cmdreg_srsp;\n\tunsigned int cmdreg_stop;\n\tunsigned int datalength_bits;\n\tunsigned int fifosize;\n\tunsigned int fifohalfsize;\n\tunsigned int data_cmd_enable;\n\tunsigned int datactrl_mask_ddrmode;\n\tunsigned int datactrl_mask_sdio;\n\tunsigned int datactrl_blocksz;\n\tu8 datactrl_any_blocksz: 1;\n\tu8 dma_power_of_2: 1;\n\tu8 datactrl_first: 1;\n\tu8 datacnt_useless: 1;\n\tu8 st_sdio: 1;\n\tu8 st_clkdiv: 1;\n\tu8 stm32_clkdiv: 1;\n\tu32 pwrreg_powerup;\n\tu32 f_max;\n\tu8 signal_direction: 1;\n\tu8 pwrreg_clkgate: 1;\n\tu8 busy_detect: 1;\n\tu8 busy_timeout: 1;\n\tu32 busy_dpsm_flag;\n\tu32 busy_detect_flag;\n\tu32 busy_detect_mask;\n\tu8 pwrreg_nopower: 1;\n\tu8 explicit_mclk_control: 1;\n\tu8 qcom_fifo: 1;\n\tu8 qcom_dml: 1;\n\tu8 reversed_irq_handling: 1;\n\tu8 mmcimask1: 1;\n\tunsigned int irq_pio_mask;\n\tu32 start_err;\n\tu32 opendrain;\n\tu8 dma_lli: 1;\n\tbool supports_sdio_irq;\n\tu32 stm32_idmabsize_mask;\n\tu32 stm32_idmabsize_align;\n\tbool dma_flow_controller;\n\tvoid (*init)(struct mmci_host *);\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc3_clk_data {\n\tu8 offs;\n\tu8 bitmsk;\n};\n\nstruct vc3_div_data {\n\tconst struct clk_div_table *table;\n\tu8 offs;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n};\n\nstruct vc3_vco {\n\tlong unsigned int min;\n\tlong unsigned int max;\n};\n\nstruct vc3_hw_cfg {\n\tstruct vc3_vco pll2_vco;\n\tu32 se2_clk_sel_msk;\n};\n\nstruct vc3_hw_data {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tvoid *data;\n\tu32 div_int;\n\tu32 div_frc;\n};\n\nstruct vc3_pfd_data {\n\tu8 num;\n\tu8 offs;\n\tu8 mdiv1_bitmsk;\n\tu8 mdiv2_bitmsk;\n};\n\nstruct vc3_pll_data {\n\tstruct vc3_vco vco;\n\tu8 num;\n\tu8 int_div_msb_offs;\n\tu8 int_div_lsb_offs;\n};\n\nstruct vc5_chip_info {\n\tconst enum vc5_model model;\n\tconst unsigned int clk_fod_cnt;\n\tconst unsigned int clk_out_cnt;\n\tconst u32 flags;\n\tconst long unsigned int vco_max;\n};\n\nstruct vc5_driver_data;\n\nstruct vc5_hw_data {\n\tstruct clk_hw hw;\n\tstruct vc5_driver_data *vc5;\n\tu32 div_int;\n\tu32 div_frc;\n\tunsigned int num;\n};\n\nstruct vc5_out_data {\n\tstruct clk_hw hw;\n\tstruct vc5_driver_data *vc5;\n\tunsigned int num;\n\tunsigned int clk_output_cfg0;\n\tunsigned int clk_output_cfg0_mask;\n};\n\nstruct vc5_driver_data {\n\tstruct i2c_client *client;\n\tstruct regmap *regmap;\n\tconst struct vc5_chip_info *chip_info;\n\tstruct clk *pin_xin;\n\tstruct clk *pin_clkin;\n\tunsigned char clk_mux_ins;\n\tstruct clk_hw clk_mux;\n\tstruct clk_hw clk_mul;\n\tstruct clk_hw clk_pfd;\n\tstruct vc5_hw_data clk_pll;\n\tstruct vc5_hw_data clk_fod[4];\n\tstruct vc5_out_data clk_out[5];\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[4];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcpu_register_runstate_memory_area {\n\tunion {\n\t\t__guest_handle_vcpu_runstate_info h;\n\t\tstruct vcpu_runstate_info *v;\n\t\tuint64_t p;\n\t} addr;\n};\n\nstruct vcpu_register_vcpu_info {\n\tuint64_t mfn;\n\tuint32_t offset;\n\tuint32_t rsvd;\n};\n\nstruct vcpu_runstate_info {\n\tint state;\n\tuint64_t state_entry_time;\n\tuint64_t time[4];\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vm_special_mapping;\n\nstruct vdso_abi_info {\n\tconst char *name;\n\tconst char *vdso_code_start;\n\tconst char *vdso_code_end;\n\tlong unsigned int vdso_pages;\n\tstruct vm_special_mapping *cm;\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_rng_data {\n\tu64 generation;\n\tu8 is_ready;\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vendor_data {\n\tint fifodepth;\n\tint max_bpw;\n\tbool unidir;\n\tbool extended_cr;\n\tbool pl023;\n\tbool loopback;\n\tbool internal_cs_ctrl;\n};\n\nstruct vendor_data___2 {\n\tconst u16 *reg_offset;\n\tunsigned int ifls;\n\tunsigned int fr_busy;\n\tunsigned int fr_dsr;\n\tunsigned int fr_cts;\n\tunsigned int fr_ri;\n\tunsigned int inv_fr;\n\tbool access_32b;\n\tbool oversampling;\n\tbool dma_threshold;\n\tbool cts_event_workaround;\n\tbool always_enabled;\n\tbool fixed_options;\n\tunsigned int (*get_fifosize)(struct amba_device *);\n};\n\nstruct vendor_error_type_extension {\n\tu32 length;\n\tu32 pcie_sbdf;\n\tu16 vendor_id;\n\tu16 device_id;\n\tu8 rev_id;\n\tu8 reserved[3];\n};\n\nstruct veth {\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n};\n\nstruct vexpress_config_bridge_ops;\n\nstruct vexpress_config_bridge {\n\tstruct vexpress_config_bridge_ops *ops;\n\tvoid *context;\n};\n\nstruct vexpress_config_bridge_ops {\n\tstruct regmap * (*regmap_init)(struct device *, void *);\n\tvoid (*regmap_exit)(struct regmap *, void *);\n};\n\nstruct vexpress_osc {\n\tstruct regmap *reg;\n\tstruct clk_hw hw;\n\tlong unsigned int rate_min;\n\tlong unsigned int rate_max;\n};\n\nstruct vexpress_syscfg {\n\tstruct device *dev;\n\tvoid *base;\n\tstruct list_head funcs;\n};\n\nstruct vexpress_syscfg_func {\n\tstruct list_head list;\n\tstruct vexpress_syscfg *syscfg;\n\tstruct regmap *regmap;\n\tint num_templates;\n\tu32 template[0];\n};\n\nstruct vf610_gpio_port {\n\tstruct gpio_generic_chip chip;\n\tvoid *base;\n\tvoid *gpio_base;\n\tconst struct fsl_gpio_soc_data *sdata;\n\tu8 irqc[32];\n\tstruct clk *clk_port;\n\tstruct clk *clk_gpio;\n\tint irq;\n};\n\nstruct vf_data_storage {\n\tunsigned char vf_mac_addresses[6];\n\tu16 vf_mc_hashes[30];\n\tu16 num_vf_mc_hashes;\n\tu32 flags;\n\tlong unsigned int last_nack;\n\tu16 pf_vlan;\n\tu16 pf_qos;\n\tu16 tx_rate;\n\tbool spoofchk_enabled;\n\tbool trusted;\n};\n\nstruct vfio {\n\tstruct list_head iommu_drivers_list;\n\tstruct mutex iommu_drivers_lock;\n};\n\nstruct vfio___2 {\n\tstruct class *device_class;\n\tstruct ida device_ida;\n\tstruct vfsmount *vfs_mount;\n\tint fs_count;\n};\n\nstruct vfio___3 {\n\tstruct class *class;\n\tstruct list_head group_list;\n\tstruct mutex group_lock;\n\tstruct ida group_ida;\n\tdev_t group_devt;\n};\n\nstruct vfio_batch {\n\tstruct page **pages;\n\tstruct page *fallback_page;\n\tunsigned int capacity;\n\tunsigned int size;\n\tunsigned int offset;\n};\n\nstruct vfio_bitmap {\n\t__u64 pgsize;\n\t__u64 size;\n\t__u64 *data;\n};\n\nstruct vfio_iommu_driver;\n\nstruct vfio_container {\n\tstruct kref kref;\n\tstruct list_head group_list;\n\tstruct rw_semaphore group_lock;\n\tstruct vfio_iommu_driver *iommu_driver;\n\tvoid *iommu_data;\n\tbool noiommu;\n};\n\nstruct vfio_device_ops;\n\nstruct vfio_migration_ops;\n\nstruct vfio_log_ops;\n\nstruct vfio_group;\n\nstruct vfio_device_set;\n\nstruct vfio_device {\n\tstruct device *dev;\n\tconst struct vfio_device_ops *ops;\n\tconst struct vfio_migration_ops *mig_ops;\n\tconst struct vfio_log_ops *log_ops;\n\tstruct vfio_group *group;\n\tstruct list_head group_next;\n\tstruct list_head iommu_entry;\n\tstruct vfio_device_set *dev_set;\n\tstruct list_head dev_set_list;\n\tunsigned int migration_flags;\n\tstruct kvm *kvm;\n\tunsigned int index;\n\tstruct device device;\n\trefcount_t refcount;\n\tunsigned int open_count;\n\tstruct completion comp;\n\tstruct iommufd_access *iommufd_access;\n\tvoid (*put_kvm)(struct kvm *);\n\tstruct inode *inode;\n\tu8 cdev_opened: 1;\n\tstruct dentry *debug_root;\n};\n\nstruct vfio_device_bind_iommufd {\n\t__u32 argsz;\n\t__u32 flags;\n\t__s32 iommufd;\n\t__u32 out_devid;\n\t__u64 token_uuid_ptr;\n};\n\nstruct vfio_device_feature {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u8 data[0];\n};\n\nstruct vfio_region_dma_range {\n\t__u64 offset;\n\t__u64 length;\n};\n\nstruct vfio_device_feature_dma_buf {\n\t__u32 region_index;\n\t__u32 open_flags;\n\t__u32 flags;\n\t__u32 nr_ranges;\n\tstruct vfio_region_dma_range dma_ranges[0];\n};\n\nstruct vfio_device_feature_dma_logging_control {\n\t__u64 page_size;\n\t__u32 num_ranges;\n\t__u32 __reserved;\n\t__u64 ranges;\n};\n\nstruct vfio_device_feature_dma_logging_range {\n\t__u64 iova;\n\t__u64 length;\n};\n\nstruct vfio_device_feature_dma_logging_report {\n\t__u64 iova;\n\t__u64 length;\n\t__u64 page_size;\n\t__u64 bitmap;\n};\n\nstruct vfio_device_feature_mig_data_size {\n\t__u64 stop_copy_length;\n};\n\nstruct vfio_device_feature_mig_state {\n\t__u32 device_state;\n\t__s32 data_fd;\n};\n\nstruct vfio_device_feature_migration {\n\t__u64 flags;\n};\n\nstruct vfio_device_file {\n\tstruct vfio_device *device;\n\tstruct vfio_group *group;\n\tu8 access_granted;\n\tu32 devid;\n\tspinlock_t kvm_ref_lock;\n\tstruct kvm *kvm;\n\tstruct iommufd_ctx *iommufd;\n};\n\nstruct vfio_device_info {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u32 num_regions;\n\t__u32 num_irqs;\n\t__u32 cap_offset;\n\t__u32 pad;\n};\n\nstruct vfio_info_cap_header {\n\t__u16 id;\n\t__u16 version;\n\t__u32 next;\n};\n\nstruct vfio_device_info_cap_pci_atomic_comp {\n\tstruct vfio_info_cap_header header;\n\t__u32 flags;\n\t__u32 reserved;\n};\n\nstruct vfio_device_ioeventfd {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u64 offset;\n\t__u64 data;\n\t__s32 fd;\n\t__u32 reserved;\n};\n\nstruct vfio_device_low_power_entry_with_wakeup {\n\t__s32 wakeup_eventfd;\n\t__u32 reserved;\n};\n\nstruct vfio_region_info;\n\nstruct vfio_info_cap;\n\nstruct vfio_device_ops {\n\tchar *name;\n\tint (*init)(struct vfio_device *);\n\tvoid (*release)(struct vfio_device *);\n\tint (*bind_iommufd)(struct vfio_device *, struct iommufd_ctx *, u32 *);\n\tvoid (*unbind_iommufd)(struct vfio_device *);\n\tint (*attach_ioas)(struct vfio_device *, u32 *);\n\tvoid (*detach_ioas)(struct vfio_device *);\n\tint (*pasid_attach_ioas)(struct vfio_device *, u32, u32 *);\n\tvoid (*pasid_detach_ioas)(struct vfio_device *, u32);\n\tint (*open_device)(struct vfio_device *);\n\tvoid (*close_device)(struct vfio_device *);\n\tssize_t (*read)(struct vfio_device *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct vfio_device *, const char *, size_t, loff_t *);\n\tlong int (*ioctl)(struct vfio_device *, unsigned int, long unsigned int);\n\tint (*get_region_info_caps)(struct vfio_device *, struct vfio_region_info *, struct vfio_info_cap *);\n\tint (*mmap)(struct vfio_device *, struct vm_area_struct *);\n\tvoid (*request)(struct vfio_device *, unsigned int);\n\tint (*match)(struct vfio_device *, char *);\n\tint (*match_token_uuid)(struct vfio_device *, const uuid_t *);\n\tvoid (*dma_unmap)(struct vfio_device *, u64, u64);\n\tint (*device_feature)(struct vfio_device *, u32, void *, size_t);\n};\n\nstruct vfio_device_set {\n\tvoid *set_id;\n\tstruct mutex lock;\n\tstruct list_head device_list;\n\tunsigned int device_count;\n};\n\nstruct vfio_dma {\n\tstruct rb_node node;\n\tdma_addr_t iova;\n\tlong unsigned int vaddr;\n\tsize_t size;\n\tint prot;\n\tbool iommu_mapped;\n\tbool lock_cap;\n\tbool vaddr_invalid;\n\tbool has_rsvd;\n\tstruct task_struct *task;\n\tstruct rb_root pfn_list;\n\tlong unsigned int *bitmap;\n\tstruct mm_struct *mm;\n\tsize_t locked_vm;\n};\n\nstruct vfio_domain {\n\tstruct iommu_domain *domain;\n\tstruct list_head next;\n\tstruct list_head group_list;\n\tbool enforce_cache_coherency: 1;\n};\n\nstruct vfio_group {\n\tstruct device dev;\n\tstruct cdev cdev;\n\trefcount_t drivers;\n\tunsigned int container_users;\n\tstruct iommu_group *iommu_group;\n\tstruct vfio_container *container;\n\tstruct list_head device_list;\n\tstruct mutex device_lock;\n\tstruct list_head vfio_next;\n\tstruct list_head container_next;\n\tenum vfio_group_type type;\n\tstruct mutex group_lock;\n\tstruct kvm *kvm;\n\tstruct file *opened_file;\n\tstruct blocking_notifier_head notifier;\n\tstruct iommufd_ctx *iommufd;\n\tspinlock_t kvm_ref_lock;\n\tunsigned int cdev_device_open_cnt;\n};\n\nstruct vfio_group_status {\n\t__u32 argsz;\n\t__u32 flags;\n};\n\nstruct vfio_info_cap {\n\tstruct vfio_info_cap_header *buf;\n\tsize_t size;\n};\n\nstruct vfio_iommu {\n\tstruct list_head domain_list;\n\tstruct list_head iova_list;\n\tstruct mutex lock;\n\tstruct rb_root dma_list;\n\tstruct list_head device_list;\n\tstruct mutex device_list_lock;\n\tunsigned int dma_avail;\n\tunsigned int vaddr_invalid_count;\n\tuint64_t pgsize_bitmap;\n\tuint64_t num_non_pinned_groups;\n\tbool v2;\n\tbool dirty_page_tracking;\n\tstruct list_head emulated_iommu_groups;\n};\n\nstruct vfio_iommu_driver_ops;\n\nstruct vfio_iommu_driver {\n\tconst struct vfio_iommu_driver_ops *ops;\n\tstruct list_head vfio_next;\n};\n\nstruct vfio_iommu_driver_ops {\n\tchar *name;\n\tstruct module *owner;\n\tvoid * (*open)(long unsigned int);\n\tvoid (*release)(void *);\n\tlong int (*ioctl)(void *, unsigned int, long unsigned int);\n\tint (*attach_group)(void *, struct iommu_group *, enum vfio_group_type);\n\tvoid (*detach_group)(void *, struct iommu_group *);\n\tint (*pin_pages)(void *, struct iommu_group *, dma_addr_t, int, int, struct page **);\n\tvoid (*unpin_pages)(void *, dma_addr_t, int);\n\tvoid (*register_device)(void *, struct vfio_device *);\n\tvoid (*unregister_device)(void *, struct vfio_device *);\n\tint (*dma_rw)(void *, dma_addr_t, void *, size_t, bool);\n\tstruct iommu_domain * (*group_iommu_domain)(void *, struct iommu_group *);\n};\n\nstruct vfio_iommu_group {\n\tstruct iommu_group *iommu_group;\n\tstruct list_head next;\n\tbool pinned_page_dirty_scope;\n};\n\nstruct vfio_iommu_type1_dirty_bitmap {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u8 data[0];\n};\n\nstruct vfio_iommu_type1_dirty_bitmap_get {\n\t__u64 iova;\n\t__u64 size;\n\tstruct vfio_bitmap bitmap;\n};\n\nstruct vfio_iommu_type1_dma_map {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u64 vaddr;\n\t__u64 iova;\n\t__u64 size;\n};\n\nstruct vfio_iommu_type1_dma_unmap {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u64 iova;\n\t__u64 size;\n\t__u8 data[0];\n};\n\nstruct vfio_iommu_type1_info {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u64 iova_pgsizes;\n\t__u32 cap_offset;\n\t__u32 pad;\n};\n\nstruct vfio_iova_range {\n\t__u64 start;\n\t__u64 end;\n};\n\nstruct vfio_iommu_type1_info_cap_iova_range {\n\tstruct vfio_info_cap_header header;\n\t__u32 nr_iovas;\n\t__u32 reserved;\n\tstruct vfio_iova_range iova_ranges[0];\n};\n\nstruct vfio_iommu_type1_info_cap_migration {\n\tstruct vfio_info_cap_header header;\n\t__u32 flags;\n\t__u64 pgsize_bitmap;\n\t__u64 max_dirty_bitmap_size;\n};\n\nstruct vfio_iommu_type1_info_dma_avail {\n\tstruct vfio_info_cap_header header;\n\t__u32 avail;\n};\n\nstruct vfio_iova {\n\tstruct list_head list;\n\tdma_addr_t start;\n\tdma_addr_t end;\n};\n\nstruct vfio_irq_info {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u32 index;\n\t__u32 count;\n};\n\nstruct vfio_irq_set {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u32 index;\n\t__u32 start;\n\t__u32 count;\n\t__u8 data[0];\n};\n\nstruct vfio_log_ops {\n\tint (*log_start)(struct vfio_device *, struct rb_root_cached *, u32, u64 *);\n\tint (*log_stop)(struct vfio_device *);\n\tint (*log_read_and_clear)(struct vfio_device *, long unsigned int, long unsigned int, struct iova_bitmap *);\n};\n\nstruct vfio_migration_ops {\n\tstruct file * (*migration_set_state)(struct vfio_device *, enum vfio_device_mig_state);\n\tint (*migration_get_state)(struct vfio_device *, enum vfio_device_mig_state *);\n\tint (*migration_get_data_size)(struct vfio_device *, long unsigned int *);\n};\n\nstruct vfio_pci_device_ops;\n\nstruct vfio_pci_region;\n\nstruct vfio_pci_eventfd;\n\nstruct vfio_pci_vf_token;\n\nstruct vfio_pci_core_device {\n\tstruct vfio_device vdev;\n\tstruct pci_dev *pdev;\n\tconst struct vfio_pci_device_ops *pci_ops;\n\tvoid *barmap[6];\n\tbool bar_mmap_supported[6];\n\tu8 *pci_config_map;\n\tu8 *vconfig;\n\tstruct perm_bits *msi_perm;\n\tspinlock_t irqlock;\n\tstruct mutex igate;\n\tstruct xarray ctx;\n\tint irq_type;\n\tint num_regions;\n\tstruct vfio_pci_region *region;\n\tu8 msi_qmax;\n\tu8 msix_bar;\n\tu16 msix_size;\n\tu32 msix_offset;\n\tu32 rbar[7];\n\tbool has_dyn_msix: 1;\n\tbool pci_2_3: 1;\n\tbool virq_disabled: 1;\n\tbool reset_works: 1;\n\tbool extended_caps: 1;\n\tbool bardirty: 1;\n\tbool has_vga: 1;\n\tbool needs_reset: 1;\n\tbool nointx: 1;\n\tbool needs_pm_restore: 1;\n\tbool pm_intx_masked: 1;\n\tbool pm_runtime_engaged: 1;\n\tstruct pci_saved_state *pci_saved_state;\n\tstruct pci_saved_state *pm_save;\n\tint ioeventfds_nr;\n\tstruct vfio_pci_eventfd *err_trigger;\n\tstruct vfio_pci_eventfd *req_trigger;\n\tstruct eventfd_ctx *pm_wake_eventfd_ctx;\n\tstruct list_head dummy_resources_list;\n\tstruct mutex ioeventfds_lock;\n\tstruct list_head ioeventfds_list;\n\tstruct vfio_pci_vf_token *vf_token;\n\tstruct list_head sriov_pfs_item;\n\tstruct vfio_pci_core_device *sriov_pf_core_dev;\n\tstruct notifier_block nb;\n\tstruct rw_semaphore memory_lock;\n\tstruct list_head dmabufs;\n};\n\nstruct vfio_pci_dependent_device {\n\tunion {\n\t\t__u32 group_id;\n\t\t__u32 devid;\n\t};\n\t__u16 segment;\n\t__u8 bus;\n\t__u8 devfn;\n};\n\nstruct vfio_pci_device_ops {\n\tint (*get_dmabuf_phys)(struct vfio_pci_core_device *, struct p2pdma_provider **, unsigned int, struct phys_vec *, struct vfio_region_dma_range *, size_t);\n};\n\nstruct vfio_pci_dummy_resource {\n\tstruct resource resource;\n\tint index;\n\tstruct list_head res_next;\n};\n\nstruct vfio_pci_eventfd {\n\tstruct eventfd_ctx *ctx;\n\tstruct callback_head rcu;\n};\n\nstruct vfio_pci_fill_info {\n\tstruct vfio_device *vdev;\n\tstruct vfio_pci_dependent_device *devices;\n\tint nr_devices;\n\tu32 count;\n\tu32 flags;\n};\n\nstruct vfio_pci_group_info {\n\tint count;\n\tstruct file **files;\n};\n\nstruct vfio_pci_hot_reset {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u32 count;\n\t__s32 group_fds[0];\n};\n\nstruct vfio_pci_hot_reset_info {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u32 count;\n\tstruct vfio_pci_dependent_device devices[0];\n};\n\nstruct virqfd;\n\nstruct vfio_pci_ioeventfd {\n\tstruct list_head next;\n\tstruct vfio_pci_core_device *vdev;\n\tstruct virqfd *virqfd;\n\tvoid *addr;\n\tuint64_t data;\n\tloff_t pos;\n\tint bar;\n\tint count;\n\tbool test_mem;\n};\n\nstruct vfio_pci_irq_ctx {\n\tstruct vfio_pci_core_device *vdev;\n\tstruct eventfd_ctx *trigger;\n\tstruct virqfd *unmask;\n\tstruct virqfd *mask;\n\tchar *name;\n\tbool masked;\n\tstruct irq_bypass_producer producer;\n};\n\nstruct vfio_pci_regops;\n\nstruct vfio_pci_region {\n\tu32 type;\n\tu32 subtype;\n\tconst struct vfio_pci_regops *ops;\n\tvoid *data;\n\tsize_t size;\n\tu32 flags;\n};\n\nstruct vfio_pci_regops {\n\tssize_t (*rw)(struct vfio_pci_core_device *, char *, size_t, loff_t *, bool);\n\tvoid (*release)(struct vfio_pci_core_device *, struct vfio_pci_region *);\n\tint (*mmap)(struct vfio_pci_core_device *, struct vfio_pci_region *, struct vm_area_struct *);\n\tint (*add_capability)(struct vfio_pci_core_device *, struct vfio_pci_region *, struct vfio_info_cap *);\n};\n\nstruct vfio_pci_vf_token {\n\tstruct mutex lock;\n\tuuid_t uuid;\n\tint users;\n};\n\nstruct vfio_pci_walk_info {\n\tint (*fn)(struct pci_dev *, void *);\n\tvoid *data;\n\tstruct pci_dev *pdev;\n\tbool slot;\n\tint ret;\n};\n\nstruct vfio_pfn {\n\tstruct rb_node node;\n\tdma_addr_t iova;\n\tlong unsigned int pfn;\n\tunsigned int ref_count;\n};\n\nstruct vfio_region_info {\n\t__u32 argsz;\n\t__u32 flags;\n\t__u32 index;\n\t__u32 cap_offset;\n\t__u64 size;\n\t__u64 offset;\n};\n\nstruct vfio_region_info_cap_type {\n\tstruct vfio_info_cap_header header;\n\t__u32 type;\n\t__u32 subtype;\n};\n\nstruct vfio_regions {\n\tstruct list_head list;\n\tdma_addr_t iova;\n\tphys_addr_t phys;\n\tsize_t len;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tbool is_firmware_default;\n\tunsigned int (*set_decode)(struct pci_dev *, bool);\n};\n\nstruct vgic_global {\n\tenum vgic_type type;\n\tphys_addr_t vcpu_base;\n\tvoid *vcpu_base_va;\n\tvoid *vcpu_hyp_va;\n\tvoid *vctrl_base;\n\tvoid *vctrl_hyp;\n\tvoid *gicc_base;\n\tint nr_lr;\n\tunsigned int maint_irq;\n\tint max_gic_vcpus;\n\tbool can_emulate_gicv2;\n\tbool has_gicv4;\n\tbool has_gicv4_1;\n\tbool no_hw_deactivation;\n\tstruct static_key_false gicv3_cpuif;\n\tbool has_gcie_v3_compat;\n\tu32 ich_vtr_el2;\n};\n\nstruct vgic_irq {\n\traw_spinlock_t irq_lock;\n\tu32 intid;\n\tstruct callback_head rcu;\n\tstruct list_head ap_list;\n\tstruct kvm_vcpu *vcpu;\n\tstruct kvm_vcpu *target_vcpu;\n\tbool pending_release: 1;\n\tbool pending_latch: 1;\n\tenum vgic_irq_config config: 1;\n\tbool line_level: 1;\n\tbool enabled: 1;\n\tbool active: 1;\n\tbool hw: 1;\n\tbool on_lr: 1;\n\trefcount_t refcount;\n\tu32 hwintid;\n\tunsigned int host_irq;\n\tunion {\n\t\tu8 targets;\n\t\tu32 mpidr;\n\t};\n\tu8 source;\n\tu8 active_source;\n\tu8 priority;\n\tu8 group;\n\tstruct irq_ops *ops;\n\tvoid *owner;\n};\n\nstruct vgic_its {\n\tgpa_t vgic_its_base;\n\tbool enabled;\n\tstruct vgic_io_device iodev;\n\tstruct kvm_device *dev;\n\tu64 baser_device_table;\n\tu64 baser_coll_table;\n\tstruct mutex cmd_lock;\n\tu64 cbaser;\n\tu32 creadr;\n\tu32 cwriter;\n\tu32 abi_rev;\n\tstruct mutex its_lock;\n\tstruct list_head device_list;\n\tstruct list_head collection_list;\n\tstruct xarray translation_cache;\n};\n\nstruct vgic_its_abi {\n\tint cte_esz;\n\tint dte_esz;\n\tint ite_esz;\n\tint (*save_tables)(struct vgic_its *);\n\tint (*restore_tables)(struct vgic_its *);\n\tint (*commit)(struct vgic_its *);\n};\n\nstruct vgic_its_iter {\n\tstruct its_device___2 *dev;\n\tstruct its_ite *ite;\n};\n\nstruct vgic_redist_region {\n\tu32 index;\n\tgpa_t base;\n\tu32 count;\n\tu32 free_index;\n\tstruct list_head list;\n};\n\nstruct vgic_reg_attr {\n\tstruct kvm_vcpu *vcpu;\n\tgpa_t addr;\n};\n\nstruct vgic_register_region {\n\tunsigned int reg_offset;\n\tunsigned int len;\n\tunsigned int bits_per_irq;\n\tunsigned int access_flags;\n\tunion {\n\t\tlong unsigned int (*read)(struct kvm_vcpu *, gpa_t, unsigned int);\n\t\tlong unsigned int (*its_read)(struct kvm *, struct vgic_its *, gpa_t, unsigned int);\n\t};\n\tunion {\n\t\tvoid (*write)(struct kvm_vcpu *, gpa_t, unsigned int, long unsigned int);\n\t\tvoid (*its_write)(struct kvm *, struct vgic_its *, gpa_t, unsigned int, long unsigned int);\n\t};\n\tlong unsigned int (*uaccess_read)(struct kvm_vcpu *, gpa_t, unsigned int);\n\tunion {\n\t\tint (*uaccess_write)(struct kvm_vcpu *, gpa_t, unsigned int, long unsigned int);\n\t\tint (*uaccess_its_write)(struct kvm *, struct vgic_its *, gpa_t, unsigned int, long unsigned int);\n\t};\n};\n\nstruct vgic_vmcr {\n\tu32 grpen0;\n\tu32 grpen1;\n\tu32 ackctl;\n\tu32 fiqen;\n\tu32 cbpr;\n\tu32 eoim;\n\tu32 abpr;\n\tu32 bpr;\n\tu32 pmr;\n};\n\nstruct vgic_sort_info {\n\tstruct kvm_vcpu *vcpu;\n\tstruct vgic_vmcr vmcr;\n};\n\nstruct vgic_state_iter {\n\tint nr_cpus;\n\tint nr_spis;\n\tint dist_id;\n\tint vcpu_id;\n\tlong unsigned int intid;\n};\n\nstruct vid_pll_div {\n\tunsigned int shift_val;\n\tunsigned int shift_sel;\n\tunsigned int divider;\n\tunsigned int multiplier;\n};\n\nstruct videomode {\n\tlong unsigned int pixelclock;\n\tu32 hactive;\n\tu32 hfront_porch;\n\tu32 hback_porch;\n\tu32 hsync_len;\n\tu32 vactive;\n\tu32 vfront_porch;\n\tu32 vback_porch;\n\tu32 vsync_len;\n\tenum display_flags flags;\n};\n\nstruct virqfd {\n\tvoid *opaque;\n\tstruct eventfd_ctx *eventfd;\n\tint (*handler)(void *, void *);\n\tvoid (*thread)(void *, void *);\n\tvoid *data;\n\tstruct work_struct inject;\n\twait_queue_entry_t wait;\n\tpoll_table pt;\n\tstruct work_struct shutdown;\n\tstruct work_struct flush_inject;\n\tstruct virqfd **pvirqfd;\n};\n\nstruct virtio_blk_outhdr {\n\t__virtio32 type;\n\t__virtio32 ioprio;\n\t__virtio64 sector;\n};\n\nstruct virtblk_req {\n\tstruct virtio_blk_outhdr out_hdr;\n\tunion {\n\t\tu8 status;\n\t\tstruct {\n\t\t\t__virtio64 sector;\n\t\t\tu8 status;\n\t\t} zone_append;\n\t} in_hdr;\n\tsize_t in_hdr_len;\n\tstruct sg_table sg_table;\n\tstruct scatterlist sg[0];\n};\n\nstruct virtio_9p_config {\n\t__virtio16 tag_len;\n\t__u8 tag[0];\n};\n\nstruct virtio_admin_cmd {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__le64 group_member_id;\n\tstruct scatterlist *data_sg;\n\tstruct scatterlist *result_sg;\n\tstruct completion completion;\n\tu32 result_sg_size;\n\tint ret;\n};\n\nstruct virtio_admin_cmd_cap_get_data {\n\t__le16 id;\n\t__u8 reserved[6];\n};\n\nstruct virtio_admin_cmd_cap_set_data {\n\t__le16 id;\n\t__u8 reserved[6];\n\t__u8 cap_specific_data[0];\n};\n\nstruct virtio_admin_cmd_dev_mode_set_data {\n\t__u8 flags;\n};\n\nstruct virtio_admin_cmd_resource_obj_cmd_hdr {\n\t__le16 type;\n\t__u8 reserved[2];\n\t__le32 id;\n};\n\nstruct virtio_dev_part_hdr {\n\t__le16 part_type;\n\t__u8 flags;\n\t__u8 reserved;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 offset;\n\t\t\t__le32 reserved;\n\t\t} pci_common_cfg;\n\t\tstruct {\n\t\t\t__le16 index;\n\t\t\t__u8 reserved[6];\n\t\t} vq_index;\n\t} selector;\n\t__le32 length;\n};\n\nstruct virtio_admin_cmd_dev_parts_get_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n\tstruct virtio_dev_part_hdr hdr_list[0];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtio_admin_cmd_dev_parts_metadata_result {\n\tunion {\n\t\tstruct {\n\t\t\t__le32 size;\n\t\t\t__le32 reserved;\n\t\t} parts_size;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t} hdr_list_count;\n\t\tstruct {\n\t\t\t__le32 count;\n\t\t\t__le32 reserved;\n\t\t\tstruct virtio_dev_part_hdr hdrs[0];\n\t\t} hdr_list;\n\t};\n};\n\nstruct virtio_admin_cmd_hdr {\n\t__le16 opcode;\n\t__le16 group_type;\n\t__u8 reserved1[12];\n\t__le64 group_member_id;\n};\n\nstruct virtio_admin_cmd_query_cap_id_result {\n\t__le64 supported_caps[1];\n};\n\nstruct virtio_admin_cmd_resource_obj_create_data {\n\tstruct virtio_admin_cmd_resource_obj_cmd_hdr hdr;\n\t__le64 flags;\n\t__u8 resource_obj_specific_data[0];\n};\n\nstruct virtio_admin_cmd_status {\n\t__le16 status;\n\t__le16 status_qualifier;\n\t__u8 reserved2[4];\n};\n\nstruct virtio_balloon_stat {\n\t__virtio16 tag;\n\t__virtio64 val;\n} __attribute__((packed));\n\nstruct virtio_balloon {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *inflate_vq;\n\tstruct virtqueue *deflate_vq;\n\tstruct virtqueue *stats_vq;\n\tstruct virtqueue *free_page_vq;\n\tstruct workqueue_struct *balloon_wq;\n\tstruct work_struct report_free_page_work;\n\tstruct work_struct update_balloon_stats_work;\n\tstruct work_struct update_balloon_size_work;\n\tspinlock_t stop_update_lock;\n\tbool stop_update;\n\tlong unsigned int config_read_bitmap;\n\tstruct list_head free_page_list;\n\tspinlock_t free_page_list_lock;\n\tlong unsigned int num_free_page_blocks;\n\tu32 cmd_id_received_cache;\n\t__virtio32 cmd_id_active;\n\t__virtio32 cmd_id_stop;\n\twait_queue_head_t acked;\n\tunsigned int num_pages;\n\tstruct balloon_dev_info vb_dev_info;\n\tstruct mutex balloon_lock;\n\tunsigned int num_pfns;\n\t__virtio32 pfns[256];\n\tstruct virtio_balloon_stat stats[16];\n\tstruct shrinker *shrinker;\n\tstruct notifier_block oom_nb;\n\tstruct virtqueue *reporting_vq;\n\tstruct page_reporting_dev_info pr_dev_info;\n\tspinlock_t wakeup_lock;\n\tbool processing_wakeup_event;\n\tu32 wakeup_signal_mask;\n};\n\nstruct virtio_balloon_config {\n\t__le32 num_pages;\n\t__le32 actual;\n\tunion {\n\t\t__le32 free_page_hint_cmd_id;\n\t\t__le32 free_page_report_cmd_id;\n\t};\n\t__le32 poison_val;\n};\n\nstruct virtio_blk_vq;\n\nstruct virtio_blk {\n\tstruct mutex vdev_mutex;\n\tstruct virtio_device *vdev;\n\tstruct gendisk *disk;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct work_struct config_work;\n\tint index;\n\tint num_vqs;\n\tint io_queues[3];\n\tstruct virtio_blk_vq *vqs;\n\tunsigned int zone_sectors;\n};\n\nstruct virtio_blk_geometry {\n\t__virtio16 cylinders;\n\t__u8 heads;\n\t__u8 sectors;\n};\n\nstruct virtio_blk_zoned_characteristics {\n\t__virtio32 zone_sectors;\n\t__virtio32 max_open_zones;\n\t__virtio32 max_active_zones;\n\t__virtio32 max_append_sectors;\n\t__virtio32 write_granularity;\n\t__u8 model;\n\t__u8 unused2[3];\n};\n\nstruct virtio_blk_config {\n\t__virtio64 capacity;\n\t__virtio32 size_max;\n\t__virtio32 seg_max;\n\tstruct virtio_blk_geometry geometry;\n\t__virtio32 blk_size;\n\t__u8 physical_block_exp;\n\t__u8 alignment_offset;\n\t__virtio16 min_io_size;\n\t__virtio32 opt_io_size;\n\t__u8 wce;\n\t__u8 unused;\n\t__virtio16 num_queues;\n\t__virtio32 max_discard_sectors;\n\t__virtio32 max_discard_seg;\n\t__virtio32 discard_sector_alignment;\n\t__virtio32 max_write_zeroes_sectors;\n\t__virtio32 max_write_zeroes_seg;\n\t__u8 write_zeroes_may_unmap;\n\t__u8 unused1[3];\n\t__virtio32 max_secure_erase_sectors;\n\t__virtio32 max_secure_erase_seg;\n\t__virtio32 secure_erase_sector_alignment;\n\tstruct virtio_blk_zoned_characteristics zoned;\n};\n\nstruct virtio_blk_discard_write_zeroes {\n\t__le64 sector;\n\t__le32 num_sectors;\n\t__le32 flags;\n};\n\nstruct virtio_blk_vq {\n\tstruct virtqueue *vq;\n\tspinlock_t lock;\n\tchar name[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct virtio_chan {\n\tbool inuse;\n\tspinlock_t lock;\n\tstruct p9_client *client;\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *vq;\n\tint ring_bufs_avail;\n\twait_queue_head_t *vc_wq;\n\tlong unsigned int p9_max_pages;\n\tstruct scatterlist sg[128];\n\tchar *tag;\n\tstruct list_head chan_list;\n};\n\nstruct virtqueue_info;\n\nstruct virtio_shm_region;\n\nstruct virtio_config_ops {\n\tvoid (*get)(struct virtio_device *, unsigned int, void *, unsigned int);\n\tvoid (*set)(struct virtio_device *, unsigned int, const void *, unsigned int);\n\tu32 (*generation)(struct virtio_device *);\n\tu8 (*get_status)(struct virtio_device *);\n\tvoid (*set_status)(struct virtio_device *, u8);\n\tvoid (*reset)(struct virtio_device *);\n\tint (*find_vqs)(struct virtio_device *, unsigned int, struct virtqueue **, struct virtqueue_info *, struct irq_affinity *);\n\tvoid (*del_vqs)(struct virtio_device *);\n\tvoid (*synchronize_cbs)(struct virtio_device *);\n\tu64 (*get_features)(struct virtio_device *);\n\tvoid (*get_extended_features)(struct virtio_device *, u64 *);\n\tint (*finalize_features)(struct virtio_device *);\n\tconst char * (*bus_name)(struct virtio_device *);\n\tint (*set_vq_affinity)(struct virtqueue *, const struct cpumask *);\n\tconst struct cpumask * (*get_vq_affinity)(struct virtio_device *, int);\n\tbool (*get_shm_region)(struct virtio_device *, struct virtio_shm_region *, u8);\n\tint (*disable_vq_and_reset)(struct virtqueue *);\n\tint (*enable_vq_after_reset)(struct virtqueue *);\n};\n\nstruct virtio_console_config {\n\t__virtio16 cols;\n\t__virtio16 rows;\n\t__virtio32 max_nr_ports;\n\t__virtio32 emerg_wr;\n};\n\nstruct virtio_dev_parts_cap {\n\t__u8 get_parts_resource_objects_limit;\n\t__u8 set_parts_resource_objects_limit;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct vringh_config_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_map_ops;\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_driver {\n\tstruct device_driver driver;\n\tconst struct virtio_device_id *id_table;\n\tconst unsigned int *feature_table;\n\tunsigned int feature_table_size;\n\tconst unsigned int *feature_table_legacy;\n\tunsigned int feature_table_size_legacy;\n\tint (*validate)(struct virtio_device *);\n\tint (*probe)(struct virtio_device *);\n\tvoid (*scan)(struct virtio_device *);\n\tvoid (*remove)(struct virtio_device *);\n\tvoid (*config_changed)(struct virtio_device *);\n\tint (*freeze)(struct virtio_device *);\n\tint (*restore)(struct virtio_device *);\n\tint (*reset_prepare)(struct virtio_device *);\n\tint (*reset_done)(struct virtio_device *);\n\tvoid (*shutdown)(struct virtio_device *);\n};\n\nstruct virtio_map_ops {\n\tdma_addr_t (*map_page)(union virtio_map, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(union virtio_map, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid * (*alloc)(union virtio_map, size_t, dma_addr_t *, gfp_t);\n\tvoid (*free)(union virtio_map, size_t, void *, dma_addr_t, long unsigned int);\n\tbool (*need_sync)(union virtio_map, dma_addr_t);\n\tint (*mapping_error)(union virtio_map, dma_addr_t);\n\tsize_t (*max_mapping_size)(union virtio_map);\n};\n\nstruct virtio_mmio_device {\n\tstruct virtio_device vdev;\n\tstruct platform_device *pdev;\n\tvoid *base;\n\tlong unsigned int version;\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1 {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\tunion {\n\t\tstruct {\n\t\t\t__virtio16 csum_start;\n\t\t\t__virtio16 csum_offset;\n\t\t};\n\t\tstruct {\n\t\t\t__virtio16 start;\n\t\t\t__virtio16 offset;\n\t\t} csum;\n\t\tstruct {\n\t\t\t__le16 segments;\n\t\t\t__le16 dup_acks;\n\t\t} rsc;\n\t};\n\t__virtio16 num_buffers;\n};\n\nstruct virtio_net_hdr_v1_hash {\n\tstruct virtio_net_hdr_v1 hdr;\n\t__le16 hash_value_lo;\n\t__le16 hash_value_hi;\n\t__le16 hash_report;\n\t__le16 padding;\n};\n\nstruct virtio_net_hdr_v1_hash_tunnel {\n\tstruct virtio_net_hdr_v1_hash hash_hdr;\n\t__le16 outer_th_offset;\n\t__le16 inner_nh_offset;\n};\n\nstruct virtio_net_common_hdr {\n\tunion {\n\t\tstruct virtio_net_hdr hdr;\n\t\tstruct virtio_net_hdr_mrg_rxbuf mrg_hdr;\n\t\tstruct virtio_net_hdr_v1_hash hash_v1_hdr;\n\t\tstruct virtio_net_hdr_v1_hash_tunnel tnl_hdr;\n\t};\n};\n\nstruct virtio_net_config {\n\t__u8 mac[6];\n\t__virtio16 status;\n\t__virtio16 max_virtqueue_pairs;\n\t__virtio16 mtu;\n\t__le32 speed;\n\t__u8 duplex;\n\t__u8 rss_max_key_size;\n\t__le16 rss_max_indirection_table_length;\n\t__le32 supported_hash_types;\n};\n\nstruct virtio_net_ctrl_coal {\n\t__le32 max_packets;\n\t__le32 max_usecs;\n};\n\nstruct virtio_net_ctrl_coal_rx {\n\t__le32 rx_max_packets;\n\t__le32 rx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_tx {\n\t__le32 tx_max_packets;\n\t__le32 tx_usecs;\n};\n\nstruct virtio_net_ctrl_coal_vq {\n\t__le16 vqn;\n\t__le16 reserved;\n\tstruct virtio_net_ctrl_coal coal;\n};\n\nstruct virtio_net_ctrl_mac {\n\t__virtio32 entries;\n\t__u8 macs[0];\n};\n\nstruct virtio_net_ctrl_mq {\n\t__virtio16 virtqueue_pairs;\n};\n\nstruct virtio_net_ctrl_queue_stats {\n\tstruct {\n\t\t__le16 vq_index;\n\t\t__le16 reserved[3];\n\t\t__le64 types_bitmap[1];\n\t} stats[1];\n};\n\nstruct virtio_net_rss_config_hdr {\n\t__le32 hash_types;\n\t__le16 indirection_table_mask;\n\t__le16 unclassified_queue;\n\t__le16 indirection_table[0];\n};\n\nstruct virtio_net_rss_config_trailer {\n\t__le16 max_tx_vq;\n\t__u8 hash_key_length;\n\t__u8 hash_key_data[0];\n};\n\nstruct virtio_net_stats_capabilities {\n\t__le64 supported_stats_types[1];\n};\n\nstruct virtio_net_stats_reply_hdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__le16 vq_index;\n\t__le16 reserved1;\n\t__le16 size;\n};\n\nstruct virtio_pci_vq_info;\n\nstruct virtio_pci_admin_vq {\n\tstruct virtio_pci_vq_info *info;\n\tspinlock_t lock;\n\tu64 supported_cmds;\n\tu64 supported_caps;\n\tu8 max_dev_parts_objects;\n\tstruct ida dev_parts_ida;\n\tchar name[10];\n\tu16 vq_index;\n};\n\nstruct virtio_pci_common_cfg {\n\t__le32 device_feature_select;\n\t__le32 device_feature;\n\t__le32 guest_feature_select;\n\t__le32 guest_feature;\n\t__le16 msix_config;\n\t__le16 num_queues;\n\t__u8 device_status;\n\t__u8 config_generation;\n\t__le16 queue_select;\n\t__le16 queue_size;\n\t__le16 queue_msix_vector;\n\t__le16 queue_enable;\n\t__le16 queue_notify_off;\n\t__le32 queue_desc_lo;\n\t__le32 queue_desc_hi;\n\t__le32 queue_avail_lo;\n\t__le32 queue_avail_hi;\n\t__le32 queue_used_lo;\n\t__le32 queue_used_hi;\n};\n\nstruct virtio_pci_legacy_device {\n\tstruct pci_dev *pci_dev;\n\tu8 *isr;\n\tvoid *ioaddr;\n\tstruct virtio_device_id id;\n};\n\nstruct virtio_pci_modern_device {\n\tstruct pci_dev *pci_dev;\n\tstruct virtio_pci_common_cfg *common;\n\tvoid *device;\n\tvoid *notify_base;\n\tresource_size_t notify_pa;\n\tu8 *isr;\n\tsize_t notify_len;\n\tsize_t device_len;\n\tsize_t common_len;\n\tint notify_map_cap;\n\tu32 notify_offset_multiplier;\n\tint modern_bars;\n\tstruct virtio_device_id id;\n\tint (*device_id_check)(struct pci_dev *);\n\tu64 dma_mask;\n};\n\nstruct virtio_pci_device {\n\tstruct virtio_device vdev;\n\tstruct pci_dev *pci_dev;\n\tunion {\n\t\tstruct virtio_pci_legacy_device ldev;\n\t\tstruct virtio_pci_modern_device mdev;\n\t};\n\tbool is_legacy;\n\tu8 *isr;\n\tspinlock_t lock;\n\tstruct list_head virtqueues;\n\tstruct list_head slow_virtqueues;\n\tstruct virtio_pci_vq_info **vqs;\n\tstruct virtio_pci_admin_vq admin_vq;\n\tint msix_enabled;\n\tint intx_enabled;\n\tcpumask_var_t *msix_affinity_masks;\n\tchar (*msix_names)[256];\n\tunsigned int msix_vectors;\n\tunsigned int msix_used_vectors;\n\tbool per_vq_vectors;\n\tstruct virtqueue * (*setup_vq)(struct virtio_pci_device *, struct virtio_pci_vq_info *, unsigned int, void (*)(struct virtqueue *), const char *, bool, u16);\n\tvoid (*del_vq)(struct virtio_pci_vq_info *);\n\tu16 (*config_vector)(struct virtio_pci_device *, u16);\n\tint (*avq_index)(struct virtio_device *, u16 *, u16 *);\n};\n\nstruct virtio_pci_modern_common_cfg {\n\tstruct virtio_pci_common_cfg cfg;\n\t__le16 queue_notify_data;\n\t__le16 queue_reset;\n\t__le16 admin_queue_index;\n\t__le16 admin_queue_num;\n};\n\nstruct virtio_pci_vq_info {\n\tstruct virtqueue *vq;\n\tstruct list_head node;\n\tunsigned int msix_vector;\n};\n\nstruct virtio_resource_obj_dev_parts {\n\t__u8 type;\n\t__u8 reserved[7];\n};\n\nstruct virtproc_info;\n\nstruct virtio_rpmsg_channel {\n\tstruct rpmsg_device rpdev;\n\tstruct virtproc_info *vrp;\n};\n\nstruct virtio_shm_region {\n\tu64 addr;\n\tu64 len;\n};\n\nstruct virtnet_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *cvq;\n\tstruct net_device *dev;\n\tstruct send_queue *sq;\n\tstruct receive_queue *rq;\n\tunsigned int status;\n\tu16 max_queue_pairs;\n\tu16 curr_queue_pairs;\n\tu16 xdp_queue_pairs;\n\tbool xdp_enabled;\n\tbool big_packets;\n\tunsigned int big_packets_num_skbfrags;\n\tbool mergeable_rx_bufs;\n\tbool has_rss;\n\tbool has_rss_hash_report;\n\tu8 rss_key_size;\n\tu16 rss_indir_table_size;\n\tu32 rss_hash_types_supported;\n\tu32 rss_hash_types_saved;\n\tbool has_cvq;\n\tstruct mutex cvq_lock;\n\tbool any_header_sg;\n\tu8 hdr_len;\n\tbool tx_tnl;\n\tbool rx_tnl;\n\tbool rx_tnl_csum;\n\tstruct work_struct config_work;\n\tstruct work_struct rx_mode_work;\n\tbool rx_mode_work_enabled;\n\tbool affinity_hint_set;\n\tstruct hlist_node node;\n\tstruct hlist_node node_dead;\n\tstruct control_buf *ctrl;\n\tu8 duplex;\n\tu32 speed;\n\tbool rx_dim_enabled;\n\tstruct virtnet_interrupt_coalesce intr_coal_tx;\n\tstruct virtnet_interrupt_coalesce intr_coal_rx;\n\tlong unsigned int guest_offloads;\n\tlong unsigned int guest_offloads_capable;\n\tstruct failover *failover;\n\tu64 device_stats_cap;\n\tstruct virtio_net_rss_config_hdr *rss_hdr;\n\tunion {\n\t\tstruct virtio_net_rss_config_trailer rss_trailer;\n\t\tstruct {\n\t\t\tunsigned char __offset_to_FAM[3];\n\t\t\tu8 rss_hash_key_data[40];\n\t\t};\n\t};\n};\n\nstruct virtnet_rq_dma {\n\tdma_addr_t addr;\n\tu32 ref;\n\tu16 len;\n\tu16 need_sync;\n};\n\nstruct virtnet_sq_free_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 napi_packets;\n\tu64 napi_bytes;\n\tu64 xsk;\n};\n\nstruct virtnet_stat_desc {\n\tchar desc[32];\n\tsize_t offset;\n\tsize_t qstat_offset;\n};\n\nstruct virtnet_stats_ctx {\n\tbool to_qstat;\n\tu32 desc_num[3];\n\tu64 bitmap[3];\n\tu32 size[3];\n\tu64 *data;\n};\n\nstruct virtproc_info {\n\tstruct virtio_device *vdev;\n\tstruct virtqueue *rvq;\n\tstruct virtqueue *svq;\n\tvoid *rbufs;\n\tvoid *sbufs;\n\tunsigned int num_bufs;\n\tunsigned int buf_size;\n\tint last_sbuf;\n\tdma_addr_t bufs_dma;\n\tstruct mutex tx_lock;\n\tstruct idr endpoints;\n\tstruct mutex endpoints_lock;\n\twait_queue_head_t sendq;\n};\n\nstruct virtqueue {\n\tstruct list_head list;\n\tvoid (*callback)(struct virtqueue *);\n\tconst char *name;\n\tstruct virtio_device *vdev;\n\tunsigned int index;\n\tunsigned int num_free;\n\tunsigned int num_max;\n\tbool reset;\n\tvoid *priv;\n};\n\ntypedef void vq_callback_t(struct virtqueue *);\n\nstruct virtqueue_info {\n\tconst char *name;\n\tvq_callback_t *callback;\n\tbool ctx;\n};\n\nstruct vring_virtqueue;\n\nstruct virtqueue_ops {\n\tint (*add)(struct vring_virtqueue *, struct scatterlist **, unsigned int, unsigned int, unsigned int, void *, void *, bool, gfp_t, long unsigned int);\n\tvoid * (*get)(struct vring_virtqueue *, unsigned int *, void **);\n\tbool (*kick_prepare)(struct vring_virtqueue *);\n\tvoid (*disable_cb)(struct vring_virtqueue *);\n\tbool (*enable_cb_delayed)(struct vring_virtqueue *);\n\tunsigned int (*enable_cb_prepare)(struct vring_virtqueue *);\n\tbool (*poll)(const struct vring_virtqueue *, unsigned int);\n\tvoid * (*detach_unused_buf)(struct vring_virtqueue *);\n\tbool (*more_used)(const struct vring_virtqueue *);\n\tint (*resize)(struct vring_virtqueue *, u32);\n\tvoid (*reset)(struct vring_virtqueue *);\n};\n\nstruct virtrng_info {\n\tstruct hwrng hwrng;\n\tstruct virtqueue *vq;\n\tchar name[25];\n\tint index;\n\tbool hwrng_register_done;\n\tbool hwrng_removed;\n\tstruct completion have_data;\n\tunsigned int data_avail;\n\tunsigned int data_idx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__[0];\n\tu8 data[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_end__[0];\n};\n\nstruct visconti_clk_gate {\n\tstruct clk_hw hw;\n\tstruct regmap *regmap;\n\tu32 ckon_offset;\n\tu32 ckoff_offset;\n\tu8 ck_idx;\n\tu8 flags;\n\tu32 rson_offset;\n\tu32 rsoff_offset;\n\tu8 rs_idx;\n\tspinlock_t *lock;\n};\n\nstruct visconti_clk_gate_table {\n\tunsigned int id;\n\tconst char *name;\n\tconst struct clk_parent_data *parent_data;\n\tu8 num_parents;\n\tu8 flags;\n\tu32 ckon_offset;\n\tu32 ckoff_offset;\n\tu8 ck_idx;\n\tunsigned int div;\n\tu8 rs_id;\n};\n\nstruct visconti_clk_provider {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct clk_hw_onecell_data clk_data;\n};\n\nstruct visconti_desc_pin {\n\tstruct pinctrl_pin_desc pin;\n\tunsigned int dsel_offset;\n\tunsigned int dsel_shift;\n\tunsigned int pude_offset;\n\tunsigned int pudsel_offset;\n\tunsigned int pud_shift;\n};\n\nstruct visconti_fixed_clk {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent;\n\tlong unsigned int flag;\n\tunsigned int mult;\n\tunsigned int div;\n};\n\nstruct visconti_gpio {\n\tvoid *base;\n\tspinlock_t lock;\n\tstruct gpio_generic_chip chip;\n\tstruct device *dev;\n};\n\nstruct visconti_mux {\n\tunsigned int offset;\n\tunsigned int mask;\n\tunsigned int val;\n};\n\nstruct visconti_pcie {\n\tstruct dw_pcie pci;\n\tvoid *ulreg_base;\n\tvoid *smu_base;\n\tvoid *mpu_base;\n\tstruct clk *refclk;\n\tstruct clk *coreclk;\n\tstruct clk *auxclk;\n};\n\nstruct visconti_pin_function {\n\tconst char *name;\n\tconst char * const *groups;\n\tunsigned int nr_groups;\n};\n\nstruct visconti_pin_group {\n\tconst char *name;\n\tconst unsigned int *pins;\n\tunsigned int nr_pins;\n\tstruct visconti_mux mux;\n};\n\nstruct visconti_pinctrl_devdata;\n\nstruct visconti_pinctrl {\n\tvoid *base;\n\tstruct device *dev;\n\tstruct pinctrl_dev *pctl;\n\tstruct pinctrl_desc pctl_desc;\n\tconst struct visconti_pinctrl_devdata *devdata;\n\tspinlock_t lock;\n};\n\nstruct visconti_pinctrl_devdata {\n\tconst struct visconti_desc_pin *pins;\n\tunsigned int nr_pins;\n\tconst struct visconti_pin_group *groups;\n\tunsigned int nr_groups;\n\tconst struct visconti_pin_function *functions;\n\tunsigned int nr_functions;\n\tconst struct visconti_mux *gpio_mux;\n\tvoid (*unlock)(void *);\n};\n\nstruct visconti_pll_rate_table;\n\nstruct visconti_pll_provider;\n\nstruct visconti_pll {\n\tstruct clk_hw hw;\n\tvoid *pll_base;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tconst struct visconti_pll_rate_table *rate_table;\n\tsize_t rate_count;\n\tstruct visconti_pll_provider *ctx;\n};\n\nstruct visconti_pll_info {\n\tunsigned int id;\n\tconst char *name;\n\tconst char *parent;\n\tlong unsigned int base_reg;\n\tconst struct visconti_pll_rate_table *rate_table;\n};\n\nstruct visconti_pll_provider {\n\tvoid *reg_base;\n\tstruct device_node *node;\n\tstruct clk_hw_onecell_data clk_data;\n};\n\nstruct visconti_pll_rate_table {\n\tlong unsigned int rate;\n\tunsigned int dacen;\n\tunsigned int dsmen;\n\tunsigned int refdiv;\n\tlong unsigned int intin;\n\tlong unsigned int fracin;\n\tunsigned int postdiv1;\n\tunsigned int postdiv2;\n};\n\nstruct visconti_reset_data;\n\nstruct visconti_reset {\n\tstruct reset_controller_dev rcdev;\n\tstruct regmap *regmap;\n\tconst struct visconti_reset_data *resets;\n\tspinlock_t *lock;\n};\n\nstruct visconti_reset_data {\n\tu32 rson_offset;\n\tu32 rsoff_offset;\n\tu8 rs_idx;\n};\n\nstruct vl_config {\n\tint __default_vl;\n};\n\nstruct vl_info {\n\tenum vec_type type;\n\tconst char *name;\n\tint min_vl;\n\tint max_vl;\n\tint max_virtualisable_vl;\n\tlong unsigned int vq_map[8];\n\tlong unsigned int vq_partial_map[8];\n};\n\nstruct vlan_priority_tci_mapping;\n\nstruct vlan_pcpu_stats;\n\nstruct vlan_dev_priv {\n\tunsigned int nr_ingress_mappings;\n\tu32 ingress_priority_map[8];\n\tunsigned int nr_egress_mappings;\n\tstruct vlan_priority_tci_mapping *egress_priority_map[16];\n\t__be16 vlan_proto;\n\tu16 vlan_id;\n\tu16 flags;\n\tstruct net_device *real_dev;\n\tnetdevice_tracker dev_tracker;\n\tunsigned char real_dev_addr[6];\n\tstruct proc_dir_entry *dent;\n\tstruct vlan_pcpu_stats *vlan_pcpu_stats;\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_group {\n\tunsigned int nr_vlan_devs;\n\tstruct hlist_node hlist;\n\tstruct net_device **vlan_devices_arrays[16];\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_info {\n\tstruct net_device *real_dev;\n\tstruct vlan_group grp;\n\tstruct list_head vid_list;\n\tunsigned int nr_vids;\n\tbool auto_vid0;\n\tstruct callback_head rcu;\n};\n\nstruct vlan_pcpu_stats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_multicast;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n\tu32 rx_errors;\n\tu32 tx_dropped;\n};\n\nstruct vlan_priority_tci_mapping {\n\tu32 priority;\n\tu16 vlan_qos;\n\tstruct vlan_priority_tci_mapping *next;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vlan_vid_info {\n\tstruct list_head list;\n\t__be16 proto;\n\tu16 vid;\n\tint refcount;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {};\n\nstruct vma_numab_state;\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tunsigned int vm_lock_seq;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct mempolicy *vm_policy;\n\tstruct vma_numab_state *numab_state;\n\trefcount_t vm_refcnt;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[110];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n\tint (*set_policy)(struct vm_area_struct *, struct mempolicy *);\n\tstruct mempolicy * (*get_policy)(struct vm_area_struct *, long unsigned int, long unsigned int *);\n\tstruct page * (*find_normal_page)(struct vm_area_struct *, long unsigned int);\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct vm_stack {\n\tstruct callback_head rcu;\n\tstruct vm_struct *stack_vm_area;\n};\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int page_order;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_exclude_readers_state {\n\tstruct vm_area_struct *vma;\n\tint state;\n\tbool detaching;\n\tbool detached;\n\tbool exclusive;\n};\n\nstruct vma_list {\n\tstruct vm_area_struct *vma;\n\tstruct list_head head;\n\trefcount_t mmap_count;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_numab_state {\n\tlong unsigned int next_scan;\n\tlong unsigned int pids_active_reset;\n\tlong unsigned int pids_active[2];\n\tint start_scan_seq;\n\tint prev_scan_seq;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[16];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmclock_abi {\n\t__le32 magic;\n\t__le32 size;\n\t__le16 version;\n\t__u8 counter_id;\n\t__u8 time_type;\n\t__le32 seq_count;\n\t__le64 disruption_marker;\n\t__le64 flags;\n\t__u8 pad[2];\n\t__u8 clock_status;\n\t__u8 leap_second_smearing_hint;\n\t__le16 tai_offset_sec;\n\t__u8 leap_indicator;\n\t__u8 counter_period_shift;\n\t__le64 counter_value;\n\t__le64 counter_period_frac_sec;\n\t__le64 counter_period_esterror_rate_frac_sec;\n\t__le64 counter_period_maxerror_rate_frac_sec;\n\t__le64 time_sec;\n\t__le64 time_frac_sec;\n\t__le64 time_esterror_nanosec;\n\t__le64 time_maxerror_nanosec;\n\t__le64 vm_generation_counter;\n};\n\nstruct vmclock_state;\n\nstruct vmclock_file_state {\n\tstruct vmclock_state *st;\n\tatomic_t seq;\n};\n\nstruct vmclock_state {\n\tstruct resource res;\n\tstruct vmclock_abi *clk;\n\tstruct miscdevice miscdev;\n\twait_queue_head_t disrupt_wait;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct ptp_clock *ptp_clock;\n\tenum clocksource_ids cs_id;\n\tenum clocksource_ids sys_cs_id;\n\tint index;\n\tchar *name;\n};\n\nstruct vmcore_cb {\n\tbool (*pfn_is_ram)(struct vmcore_cb *, long unsigned int);\n\tint (*get_device_ram)(struct vmcore_cb *, struct list_head *);\n\tstruct list_head next;\n};\n\nstruct vmcore_range {\n\tstruct list_head list;\n\tlong long unsigned int paddr;\n\tlong long unsigned int size;\n\tloff_t offset;\n};\n\nstruct vmpressure_event {\n\tstruct eventfd_ctx *efd;\n\tenum vmpressure_levels level;\n\tenum vmpressure_modes mode;\n\tstruct list_head node;\n};\n\nstruct vncr_tlb {\n\tu64 gva;\n\tstruct s1_walk_info wi;\n\tstruct s1_walk_result wr;\n\tu64 hpa;\n\tint cpu;\n\tbool valid;\n};\n\nstruct voltage_info {\n\tunsigned int num_domains;\n\tstruct scmi_voltage_info *domains;\n};\n\nstruct vring_desc;\n\ntypedef struct vring_desc vring_desc_t;\n\nstruct vring_avail;\n\ntypedef struct vring_avail vring_avail_t;\n\nstruct vring_used;\n\ntypedef struct vring_used vring_used_t;\n\nstruct vring {\n\tunsigned int num;\n\tvring_desc_t *desc;\n\tvring_avail_t *avail;\n\tvring_used_t *used;\n};\n\nstruct vring_avail {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\t__virtio16 ring[0];\n};\n\nstruct vring_desc {\n\t__virtio64 addr;\n\t__virtio32 len;\n\t__virtio16 flags;\n\t__virtio16 next;\n};\n\nstruct vring_desc_extra {\n\tdma_addr_t addr;\n\tu32 len;\n\tu16 flags;\n\tu16 next;\n};\n\nstruct vring_packed_desc;\n\nstruct vring_desc_state_packed {\n\tvoid *data;\n\tstruct vring_packed_desc *indir_desc;\n\tu16 num;\n\tu16 last;\n\tu32 total_in_len;\n};\n\nstruct vring_desc_state_split {\n\tvoid *data;\n\tstruct vring_desc *indir_desc;\n\tu32 total_in_len;\n};\n\nstruct vring_packed_desc {\n\t__le64 addr;\n\t__le32 len;\n\t__le16 id;\n\t__le16 flags;\n};\n\nstruct vring_packed_desc_event {\n\t__le16 off_wrap;\n\t__le16 flags;\n};\n\nstruct vring_used_elem {\n\t__virtio32 id;\n\t__virtio32 len;\n};\n\ntypedef struct vring_used_elem vring_used_elem_t;\n\nstruct vring_used {\n\t__virtio16 flags;\n\t__virtio16 idx;\n\tvring_used_elem_t ring[0];\n};\n\nstruct vring_virtqueue_split {\n\tstruct vring vring;\n\tu16 avail_flags_shadow;\n\tu16 avail_idx_shadow;\n\tstruct vring_desc_state_split *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t queue_dma_addr;\n\tsize_t queue_size_in_bytes;\n\tu32 vring_align;\n\tbool may_reduce_num;\n};\n\nstruct vring_virtqueue_packed {\n\tstruct {\n\t\tunsigned int num;\n\t\tstruct vring_packed_desc *desc;\n\t\tstruct vring_packed_desc_event *driver;\n\t\tstruct vring_packed_desc_event *device;\n\t} vring;\n\tbool avail_wrap_counter;\n\tu16 avail_used_flags;\n\tu16 next_avail_idx;\n\tu16 event_flags_shadow;\n\tstruct vring_desc_state_packed *desc_state;\n\tstruct vring_desc_extra *desc_extra;\n\tdma_addr_t ring_dma_addr;\n\tdma_addr_t driver_event_dma_addr;\n\tdma_addr_t device_event_dma_addr;\n\tsize_t ring_size_in_bytes;\n\tsize_t event_size_in_bytes;\n};\n\nstruct vring_virtqueue {\n\tstruct virtqueue vq;\n\tbool use_map_api;\n\tbool weak_barriers;\n\tbool broken;\n\tbool indirect;\n\tbool event;\n\tenum vq_layout layout;\n\tunsigned int free_head;\n\tstruct used_entry batch_last;\n\tunsigned int num_added;\n\tu16 last_used_idx;\n\tu16 last_used;\n\tbool event_triggered;\n\tunion {\n\t\tstruct vring_virtqueue_split split;\n\t\tstruct vring_virtqueue_packed packed;\n\t};\n\tbool (*notify)(struct virtqueue *);\n\tbool we_own_ring;\n\tunion virtio_map map;\n};\n\nstruct vsc8531_edge_rate_table {\n\tu32 vddmac;\n\tu32 slowdown[8];\n};\n\nstruct vsc85xx_ptp;\n\nstruct vsc85xx_hw_stat;\n\nstruct vsc8531_private {\n\tint rate_magic;\n\tu16 supp_led_modes;\n\tu32 leds_mode[4];\n\tu8 nleds;\n\tconst struct vsc85xx_hw_stat *hw_stats;\n\tu64 *stats;\n\tint nstats;\n\tu8 addr;\n\tunsigned int base_addr;\n\tstruct mii_timestamper mii_ts;\n\tbool input_clk_init;\n\tstruct vsc85xx_ptp *ptp;\n\tstruct gpio_desc *load_save;\n\tunsigned int ts_base_addr;\n\tu8 ts_base_phy;\n\tstruct mutex ts_lock;\n\tstruct mutex phc_lock;\n\tstruct sk_buff_head rx_skbs_list;\n};\n\nstruct vsc85xx_hw_stat {\n\tconst char *string;\n\tu8 reg;\n\tu16 page;\n\tu16 mask;\n};\n\nstruct vsc85xx_probe_config {\n\tconst struct vsc85xx_hw_stat *hw_stats;\n\tsize_t shared_size;\n\tsize_t nstats;\n\tu16 supp_led_modes;\n\tu8 nleds;\n\tbool check_rate_magic;\n\tbool use_package;\n\tbool has_ptp;\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n};\n\nstruct walk_rcec_data {\n\tstruct pci_dev *rcec;\n\tint (*user_callback)(struct pci_dev *, void *);\n\tvoid *user_data;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct xenbus_watch {\n\tstruct list_head list;\n\tconst char *node;\n\tunsigned int nr_pending;\n\tbool (*will_handle)(struct xenbus_watch *, const char *, const char *);\n\tvoid (*callback)(struct xenbus_watch *, const char *, const char *);\n};\n\nstruct xenbus_file_priv;\n\nstruct watch_adapter {\n\tstruct list_head list;\n\tstruct xenbus_watch watch;\n\tstruct xenbus_file_priv *dev_data;\n\tchar *token;\n};\n\nstruct watchdog_core_data {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tstruct watchdog_device *wdd;\n\tstruct mutex lock;\n\tktime_t last_keepalive;\n\tktime_t last_hw_keepalive;\n\tktime_t open_deadline;\n\tstruct hrtimer timer;\n\tstruct kthread_work work;\n\tlong unsigned int status;\n};\n\nstruct watchdog_governor {\n\tconst char name[20];\n\tvoid (*pretimeout)(struct watchdog_device *);\n};\n\nstruct watchdog_info {\n\t__u32 options;\n\t__u32 firmware_version;\n\t__u8 identity[32];\n};\n\nstruct watchdog_ops {\n\tstruct module *owner;\n\tint (*start)(struct watchdog_device *);\n\tint (*stop)(struct watchdog_device *);\n\tint (*ping)(struct watchdog_device *);\n\tunsigned int (*status)(struct watchdog_device *);\n\tint (*set_timeout)(struct watchdog_device *, unsigned int);\n\tint (*set_pretimeout)(struct watchdog_device *, unsigned int);\n\tunsigned int (*get_timeleft)(struct watchdog_device *);\n\tint (*restart)(struct watchdog_device *, long unsigned int, void *);\n\tlong int (*ioctl)(struct watchdog_device *, unsigned int, long unsigned int);\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct wchan_info {\n\tlong unsigned int pc;\n\tint count;\n};\n\nstruct weighted_interleave_state {\n\tbool mode_auto;\n\tu8 iw_table[0];\n};\n\nstruct window {\n\tu8 start;\n\tu8 end;\n\tu8 length;\n};\n\nstruct wktmr_time {\n\tu32 sec;\n\tu32 pre;\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int one_bits;\n\tconst long unsigned int high_bits;\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct wrapper_priv_data {\n\tstruct dwc2_hsotg *hsotg;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n\tstruct bdi_writeback *wb;\n\tstruct inode *inode;\n\tint wb_id;\n\tint wb_lcand_id;\n\tint wb_tcand_id;\n\tsize_t wb_bytes;\n\tsize_t wb_lcand_bytes;\n\tsize_t wb_tcand_bytes;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct x509_certificate {\n\tstruct x509_certificate *next;\n\tstruct x509_certificate *signer;\n\tstruct public_key *pub;\n\tstruct public_key_signature *sig;\n\tu8 sha256[32];\n\tchar *issuer;\n\tchar *subject;\n\tstruct asymmetric_key_id *id;\n\tstruct asymmetric_key_id *skid;\n\ttime64_t valid_from;\n\ttime64_t valid_to;\n\tconst void *tbs;\n\tunsigned int tbs_size;\n\tunsigned int raw_sig_size;\n\tconst void *raw_sig;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_subject;\n\tunsigned int raw_subject_size;\n\tunsigned int raw_skid_size;\n\tconst void *raw_skid;\n\tunsigned int index;\n\tbool seen;\n\tbool verified;\n\tbool self_signed;\n\tbool unsupported_sig;\n\tbool blacklisted;\n};\n\nstruct x509_parse_context {\n\tstruct x509_certificate *cert;\n\tlong unsigned int data;\n\tconst void *key;\n\tsize_t key_size;\n\tconst void *params;\n\tsize_t params_size;\n\tenum OID key_algo;\n\tenum OID last_oid;\n\tenum OID sig_algo;\n\tu8 o_size;\n\tu8 cn_size;\n\tu8 email_size;\n\tu16 o_offset;\n\tu16 cn_offset;\n\tu16 email_offset;\n\tunsigned int raw_akid_size;\n\tconst void *raw_akid;\n\tconst void *akid_raw_issuer;\n\tunsigned int akid_raw_issuer_size;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[3];\n\t\tlong unsigned int marks[3];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xb1s_ff_report {\n\t__u8 report_id;\n\t__u8 enable;\n\t__u8 magnitude[4];\n\t__u8 duration_10ms;\n\t__u8 start_delay_10ms;\n\t__u8 loop_count;\n};\n\nstruct xb_find_info {\n\tstruct xenbus_device *dev;\n\tconst char *nodename;\n};\n\nstruct xsd_sockmsg {\n\tuint32_t type;\n\tuint32_t req_id;\n\tuint32_t tx_id;\n\tuint32_t len;\n};\n\nstruct xb_req_data {\n\tstruct list_head list;\n\twait_queue_head_t wq;\n\tstruct kref kref;\n\tstruct xsd_sockmsg msg;\n\tuint32_t caller_req_id;\n\tenum xsd_sockmsg_type type;\n\tchar *body;\n\tconst struct kvec *vec;\n\tint num_vecs;\n\tint err;\n\tenum xb_req_state state;\n\tbool user_req;\n\tvoid (*cb)(struct xb_req_data *);\n\tvoid *par;\n};\n\nstruct xcv {\n\tvoid *reg_base;\n\tstruct pci_dev *pdev;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n\tlong: 64;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 64;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n};\n\nstruct xdr_array2_desc;\n\ntypedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *, void *);\n\nstruct xdr_array2_desc {\n\tunsigned int elem_size;\n\tunsigned int array_len;\n\tunsigned int array_maxlen;\n\txdr_xcode_elem_t xcode;\n};\n\nstruct xdr_skb_reader {\n\tstruct sk_buff *skb;\n\tunsigned int offset;\n\tbool need_checksum;\n\tsize_t count;\n\t__wsum csum;\n};\n\nstruct xen_add_to_physmap {\n\tdomid_t domid;\n\tuint16_t size;\n\tunsigned int space;\n\txen_ulong_t idx;\n\txen_pfn_t gpfn;\n};\n\nstruct xen_add_to_physmap_range {\n\tdomid_t domid;\n\tuint16_t space;\n\tuint16_t size;\n\tdomid_t foreign_domid;\n\t__guest_handle_xen_ulong_t idxs;\n\t__guest_handle_xen_pfn_t gpfns;\n\t__guest_handle_int errs;\n};\n\nstruct xen_build_id {\n\tuint32_t len;\n\tunsigned char buf[0];\n};\n\nstruct xen_bus_type {\n\tchar *root;\n\tunsigned int levels;\n\tint (*get_bus_id)(char *, const char *);\n\tint (*probe)(struct xen_bus_type *, const char *, const char *);\n\tbool (*otherend_will_handle)(struct xenbus_watch *, const char *, const char *);\n\tvoid (*otherend_changed)(struct xenbus_watch *, const char *, const char *);\n\tstruct bus_type bus;\n};\n\nstruct xen_compile_info {\n\tchar compiler[64];\n\tchar compile_by[16];\n\tchar compile_domain[32];\n\tchar compile_date[32];\n};\n\nstruct xen_device_domain_owner {\n\tdomid_t domain;\n\tstruct pci_dev *dev;\n\tstruct list_head list;\n};\n\nstruct xen_dm_op_buf {\n\t__guest_handle_void h;\n\txen_ulong_t size;\n};\n\nstruct xen_feature_info {\n\tunsigned int submap_idx;\n\tuint32_t submap;\n};\n\nstruct xen_hvm_param {\n\tdomid_t domid;\n\tuint32_t index;\n\tuint64_t value;\n};\n\nstruct xen_mem_acquire_resource {\n\tdomid_t domid;\n\tuint16_t type;\n\tuint32_t id;\n\tuint32_t nr_frames;\n\tuint32_t flags;\n\tuint64_t frame;\n\t__guest_handle_xen_pfn_t frame_list;\n};\n\nstruct xen_memory_region {\n\tlong unsigned int start_pfn;\n\tlong unsigned int n_pfns;\n};\n\nstruct xen_memory_reservation {\n\t__guest_handle_xen_pfn_t extent_start;\n\txen_ulong_t nr_extents;\n\tunsigned int extent_order;\n\tunsigned int address_bits;\n\tdomid_t domid;\n};\n\nstruct xen_netif_rx_request {\n\tuint16_t id;\n\tuint16_t pad;\n\tgrant_ref_t gref;\n};\n\nunion xen_netif_rx_sring_entry {\n\tstruct xen_netif_rx_request req;\n\tstruct xen_netif_rx_response rsp;\n};\n\nstruct xen_netif_rx_sring {\n\tRING_IDX req_prod;\n\tRING_IDX req_event;\n\tRING_IDX rsp_prod;\n\tRING_IDX rsp_event;\n\tuint8_t __pad[48];\n\tunion xen_netif_rx_sring_entry ring[0];\n};\n\nstruct xen_netif_tx_request {\n\tgrant_ref_t gref;\n\tuint16_t offset;\n\tuint16_t flags;\n\tuint16_t id;\n\tuint16_t size;\n};\n\nstruct xen_netif_tx_response {\n\tuint16_t id;\n\tint16_t status;\n};\n\nunion xen_netif_tx_sring_entry {\n\tstruct xen_netif_tx_request req;\n\tstruct xen_netif_tx_response rsp;\n};\n\nstruct xen_netif_tx_sring {\n\tRING_IDX req_prod;\n\tRING_IDX req_event;\n\tRING_IDX rsp_prod;\n\tRING_IDX rsp_event;\n\tuint8_t __pad[48];\n\tunion xen_netif_tx_sring_entry ring[0];\n};\n\nstruct xen_p2m_entry {\n\tlong unsigned int pfn;\n\tlong unsigned int mfn;\n\tlong unsigned int nr_pages;\n\tstruct rb_node rbnode_phys;\n};\n\nstruct xen_page_foreign {\n\tdomid_t domid;\n\tgrant_ref_t gref;\n};\n\nstruct xen_pct_register {\n\tuint8_t descriptor;\n\tuint16_t length;\n\tuint8_t space_id;\n\tuint8_t bit_width;\n\tuint8_t bit_offset;\n\tuint8_t reserved;\n\tuint64_t address;\n};\n\nstruct xenpf_settime32 {\n\tuint32_t secs;\n\tuint32_t nsecs;\n\tuint64_t system_time;\n};\n\nstruct xenpf_settime64 {\n\tuint64_t secs;\n\tuint32_t nsecs;\n\tuint32_t mbz;\n\tuint64_t system_time;\n};\n\nstruct xenpf_add_memtype {\n\txen_pfn_t mfn;\n\tuint64_t nr_mfns;\n\tuint32_t type;\n\tuint32_t handle;\n\tuint32_t reg;\n};\n\nstruct xenpf_del_memtype {\n\tuint32_t handle;\n\tuint32_t reg;\n};\n\nstruct xenpf_read_memtype {\n\tuint32_t reg;\n\txen_pfn_t mfn;\n\tuint64_t nr_mfns;\n\tuint32_t type;\n};\n\nstruct xenpf_microcode_update {\n\t__guest_handle_void data;\n\tuint32_t length;\n};\n\nstruct xenpf_platform_quirk {\n\tuint32_t quirk_id;\n};\n\nstruct xenpf_efi_time {\n\tuint16_t year;\n\tuint8_t month;\n\tuint8_t day;\n\tuint8_t hour;\n\tuint8_t min;\n\tuint8_t sec;\n\tuint32_t ns;\n\tint16_t tz;\n\tuint8_t daylight;\n};\n\nstruct xenpf_efi_guid {\n\tuint32_t data1;\n\tuint16_t data2;\n\tuint16_t data3;\n\tuint8_t data4[8];\n};\n\nstruct xenpf_efi_runtime_call {\n\tuint32_t function;\n\tuint32_t misc;\n\txen_ulong_t status;\n\tunion {\n\t\tstruct {\n\t\t\tstruct xenpf_efi_time time;\n\t\t\tuint32_t resolution;\n\t\t\tuint32_t accuracy;\n\t\t} get_time;\n\t\tstruct xenpf_efi_time set_time;\n\t\tstruct xenpf_efi_time get_wakeup_time;\n\t\tstruct xenpf_efi_time set_wakeup_time;\n\t\tstruct {\n\t\t\t__guest_handle_void name;\n\t\t\txen_ulong_t size;\n\t\t\t__guest_handle_void data;\n\t\t\tstruct xenpf_efi_guid vendor_guid;\n\t\t} get_variable;\n\t\tstruct {\n\t\t\t__guest_handle_void name;\n\t\t\txen_ulong_t size;\n\t\t\t__guest_handle_void data;\n\t\t\tstruct xenpf_efi_guid vendor_guid;\n\t\t} set_variable;\n\t\tstruct {\n\t\t\txen_ulong_t size;\n\t\t\t__guest_handle_void name;\n\t\t\tstruct xenpf_efi_guid vendor_guid;\n\t\t} get_next_variable_name;\n\t\tstruct {\n\t\t\tuint32_t attr;\n\t\t\tuint64_t max_store_size;\n\t\t\tuint64_t remain_store_size;\n\t\t\tuint64_t max_size;\n\t\t} query_variable_info;\n\t\tstruct {\n\t\t\t__guest_handle_void capsule_header_array;\n\t\t\txen_ulong_t capsule_count;\n\t\t\tuint64_t max_capsule_size;\n\t\t\tuint32_t reset_type;\n\t\t} query_capsule_capabilities;\n\t\tstruct {\n\t\t\t__guest_handle_void capsule_header_array;\n\t\t\txen_ulong_t capsule_count;\n\t\t\tuint64_t sg_list;\n\t\t} update_capsule;\n\t} u;\n};\n\nunion xenpf_efi_info {\n\tuint32_t version;\n\tstruct {\n\t\tuint64_t addr;\n\t\tuint32_t nent;\n\t} cfg;\n\tstruct {\n\t\tuint32_t revision;\n\t\tuint32_t bufsz;\n\t\t__guest_handle_void name;\n\t} vendor;\n\tstruct {\n\t\tuint64_t addr;\n\t\tuint64_t size;\n\t\tuint64_t attr;\n\t\tuint32_t type;\n\t} mem;\n};\n\nstruct xenpf_firmware_info {\n\tuint32_t type;\n\tuint32_t index;\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t device;\n\t\t\tuint8_t version;\n\t\t\tuint16_t interface_support;\n\t\t\tuint16_t legacy_max_cylinder;\n\t\t\tuint8_t legacy_max_head;\n\t\t\tuint8_t legacy_sectors_per_track;\n\t\t\t__guest_handle_void edd_params;\n\t\t} disk_info;\n\t\tstruct {\n\t\t\tuint8_t device;\n\t\t\tuint32_t mbr_signature;\n\t\t} disk_mbr_signature;\n\t\tstruct {\n\t\t\tuint8_t capabilities;\n\t\t\tuint8_t edid_transfer_time;\n\t\t\t__guest_handle_uchar edid;\n\t\t} vbeddc_info;\n\t\tunion xenpf_efi_info efi_info;\n\t\tuint8_t kbd_shift_flags;\n\t} u;\n};\n\nstruct xenpf_enter_acpi_sleep {\n\tuint16_t val_a;\n\tuint16_t val_b;\n\tuint32_t sleep_state;\n\tuint32_t flags;\n};\n\nstruct xenpf_change_freq {\n\tuint32_t flags;\n\tuint32_t cpu;\n\tuint64_t freq;\n};\n\nstruct xenpf_getidletime {\n\t__guest_handle_uchar cpumap_bitmap;\n\tuint32_t cpumap_nr_cpus;\n\t__guest_handle_uint64_t idletime;\n\tuint64_t now;\n};\n\nstruct xen_processor_flags {\n\tuint32_t bm_control: 1;\n\tuint32_t bm_check: 1;\n\tuint32_t has_cst: 1;\n\tuint32_t power_setup_done: 1;\n\tuint32_t bm_rld_set: 1;\n};\n\nstruct xen_processor_power {\n\tuint32_t count;\n\tstruct xen_processor_flags flags;\n\t__guest_handle_xen_processor_cx states;\n};\n\nstruct xen_psd_package {\n\tuint64_t num_entries;\n\tuint64_t revision;\n\tuint64_t domain;\n\tuint64_t coord_type;\n\tuint64_t num_processors;\n};\n\nstruct xen_processor_performance {\n\tuint32_t flags;\n\tuint32_t platform_limit;\n\tstruct xen_pct_register control_register;\n\tstruct xen_pct_register status_register;\n\tuint32_t state_count;\n\t__guest_handle_xen_processor_px states;\n\tstruct xen_psd_package domain_info;\n\tuint32_t shared_type;\n};\n\nstruct xenpf_set_processor_pminfo {\n\tuint32_t id;\n\tuint32_t type;\n\tunion {\n\t\tstruct xen_processor_power power;\n\t\tstruct xen_processor_performance perf;\n\t\t__guest_handle_uint32_t pdc;\n\t};\n};\n\nstruct xenpf_pcpuinfo {\n\tuint32_t xen_cpuid;\n\tuint32_t max_present;\n\tuint32_t flags;\n\tuint32_t apic_id;\n\tuint32_t acpi_id;\n};\n\nstruct xenpf_cpu_ol {\n\tuint32_t cpuid;\n};\n\nstruct xenpf_cpu_hotadd {\n\tuint32_t apic_id;\n\tuint32_t acpi_id;\n\tuint32_t pxm;\n};\n\nstruct xenpf_mem_hotadd {\n\tuint64_t spfn;\n\tuint64_t epfn;\n\tuint32_t pxm;\n\tuint32_t flags;\n};\n\nstruct xenpf_core_parking {\n\tuint32_t type;\n\tuint32_t idle_nums;\n};\n\nstruct xenpf_symdata {\n\tuint32_t namelen;\n\tuint32_t symnum;\n\t__guest_handle_char name;\n\tuint64_t address;\n\tchar type;\n};\n\nstruct xen_platform_op {\n\tuint32_t cmd;\n\tuint32_t interface_version;\n\tunion {\n\t\tstruct xenpf_settime32 settime32;\n\t\tstruct xenpf_settime64 settime64;\n\t\tstruct xenpf_add_memtype add_memtype;\n\t\tstruct xenpf_del_memtype del_memtype;\n\t\tstruct xenpf_read_memtype read_memtype;\n\t\tstruct xenpf_microcode_update microcode;\n\t\tstruct xenpf_platform_quirk platform_quirk;\n\t\tstruct xenpf_efi_runtime_call efi_runtime_call;\n\t\tstruct xenpf_firmware_info firmware_info;\n\t\tstruct xenpf_enter_acpi_sleep enter_acpi_sleep;\n\t\tstruct xenpf_change_freq change_freq;\n\t\tstruct xenpf_getidletime getidletime;\n\t\tstruct xenpf_set_processor_pminfo set_pminfo;\n\t\tstruct xenpf_pcpuinfo pcpu_info;\n\t\tstruct xenpf_cpu_ol cpu_ol;\n\t\tstruct xenpf_cpu_hotadd cpu_add;\n\t\tstruct xenpf_mem_hotadd mem_add;\n\t\tstruct xenpf_core_parking core_parking;\n\t\tstruct xenpf_symdata symdata;\n\t\tstruct dom0_vga_console_info dom0_console;\n\t\tuint8_t pad[128];\n\t} u;\n};\n\nstruct xen_platform_parameters {\n\txen_ulong_t virt_start;\n};\n\nstruct xen_power_register {\n\tuint32_t space_id;\n\tuint32_t bit_width;\n\tuint32_t bit_offset;\n\tuint32_t access_size;\n\tuint64_t address;\n};\n\nstruct xen_processor_csd {\n\tuint32_t domain;\n\tuint32_t coord_type;\n\tuint32_t num;\n};\n\nstruct xen_processor_cx {\n\tstruct xen_power_register reg;\n\tuint8_t type;\n\tuint32_t latency;\n\tuint32_t power;\n\tuint32_t dpcnt;\n\t__guest_handle_xen_processor_csd dp;\n};\n\nstruct xen_processor_px {\n\tuint64_t core_frequency;\n\tuint64_t power;\n\tuint64_t transition_latency;\n\tuint64_t bus_master_latency;\n\tuint64_t control;\n\tuint64_t status;\n};\n\nstruct xen_remove_from_physmap {\n\tdomid_t domid;\n\txen_pfn_t gpfn;\n};\n\nstruct xenbus_device {\n\tconst char *devicetype;\n\tconst char *nodename;\n\tconst char *otherend;\n\tint otherend_id;\n\tstruct xenbus_watch otherend_watch;\n\tstruct device dev;\n\tenum xenbus_state state;\n\tstruct completion down;\n\tstruct work_struct work;\n\tstruct semaphore reclaim_sem;\n\tatomic_t event_channels;\n\tatomic_t events;\n\tatomic_t spurious_events;\n\tatomic_t jiffies_eoi_delayed;\n\tunsigned int spurious_threshold;\n};\n\nstruct xenbus_device_id {\n\tchar devicetype[32];\n};\n\nstruct xenbus_driver {\n\tconst char *name;\n\tconst struct xenbus_device_id *ids;\n\tbool allow_rebind;\n\tbool not_essential;\n\tint (*probe)(struct xenbus_device *, const struct xenbus_device_id *);\n\tvoid (*otherend_changed)(struct xenbus_device *, enum xenbus_state);\n\tvoid (*remove)(struct xenbus_device *);\n\tint (*suspend)(struct xenbus_device *);\n\tint (*resume)(struct xenbus_device *);\n\tint (*uevent)(const struct xenbus_device *, struct kobj_uevent_env *);\n\tstruct device_driver driver;\n\tint (*read_otherend_details)(struct xenbus_device *);\n\tint (*is_ready)(struct xenbus_device *);\n\tvoid (*reclaim_memory)(struct xenbus_device *);\n};\n\nstruct xenbus_file_priv {\n\tstruct mutex msgbuffer_mutex;\n\tstruct list_head transactions;\n\tstruct list_head watches;\n\tunsigned int len;\n\tunion {\n\t\tstruct xsd_sockmsg msg;\n\t\tchar buffer[4096];\n\t} u;\n\tstruct mutex reply_mutex;\n\tstruct list_head read_buffers;\n\twait_queue_head_t read_waitq;\n\tstruct kref kref;\n\tstruct work_struct wq;\n};\n\nstruct xenbus_map_node {\n\tstruct list_head next;\n\tunion {\n\t\tstruct {\n\t\t\tstruct vm_struct *area;\n\t\t} pv;\n\t\tstruct {\n\t\t\tstruct page *pages[16];\n\t\t\tlong unsigned int addrs[16];\n\t\t\tvoid *addr;\n\t\t} hvm;\n\t};\n\tgrant_handle_t handles[16];\n\tunsigned int nr_handles;\n};\n\nstruct xenbus_ring_ops {\n\tint (*map)(struct xenbus_device *, struct map_ring_valloc *, grant_ref_t *, unsigned int, void **);\n\tint (*unmap)(struct xenbus_device *, void *);\n};\n\nstruct xenbus_transaction {\n\tu32 id;\n};\n\nstruct xenbus_transaction_holder {\n\tstruct list_head list;\n\tstruct xenbus_transaction handle;\n\tunsigned int generation_id;\n};\n\nstruct xencons_interface;\n\nstruct xencons_info {\n\tstruct list_head list;\n\tstruct xenbus_device *xbdev;\n\tstruct xencons_interface *intf;\n\tunsigned int evtchn;\n\tXENCONS_RING_IDX out_cons;\n\tunsigned int out_cons_same;\n\tstruct hvc_struct *hvc;\n\tint irq;\n\tint vtermno;\n\tgrant_ref_t gntref;\n\tspinlock_t ring_lock;\n};\n\nstruct xencons_interface {\n\tchar in[1024];\n\tchar out[2048];\n\tXENCONS_RING_IDX in_cons;\n\tXENCONS_RING_IDX in_prod;\n\tXENCONS_RING_IDX out_cons;\n\tXENCONS_RING_IDX out_prod;\n};\n\nstruct xenfb_resize {\n\tuint8_t type;\n\tint32_t width;\n\tint32_t height;\n\tint32_t stride;\n\tint32_t depth;\n\tint32_t offset;\n};\n\nstruct xenfb_page;\n\nstruct xenfb_info {\n\tunsigned char *fb;\n\tstruct fb_info *fb_info;\n\tint x1;\n\tint y1;\n\tint x2;\n\tint y2;\n\tspinlock_t dirty_lock;\n\tint nr_pages;\n\tint irq;\n\tstruct xenfb_page *page;\n\tlong unsigned int *gfns;\n\tint update_wanted;\n\tint feature_resize;\n\tstruct xenfb_resize resize;\n\tint resize_dpy;\n\tspinlock_t resize_lock;\n\tstruct xenbus_device *xbdev;\n};\n\nstruct xenfb_update {\n\tuint8_t type;\n\tint32_t x;\n\tint32_t y;\n\tint32_t width;\n\tint32_t height;\n};\n\nunion xenfb_out_event {\n\tuint8_t type;\n\tstruct xenfb_update update;\n\tstruct xenfb_resize resize;\n\tchar pad[40];\n};\n\nstruct xenfb_page {\n\tuint32_t in_cons;\n\tuint32_t in_prod;\n\tuint32_t out_cons;\n\tuint32_t out_prod;\n\tint32_t width;\n\tint32_t height;\n\tuint32_t line_length;\n\tuint32_t mem_length;\n\tuint8_t depth;\n\tlong unsigned int pd[256];\n};\n\nstruct xenkbd_motion {\n\tuint8_t type;\n\tint32_t rel_x;\n\tint32_t rel_y;\n\tint32_t rel_z;\n};\n\nstruct xenkbd_key {\n\tuint8_t type;\n\tuint8_t pressed;\n\tuint32_t keycode;\n};\n\nstruct xenkbd_position {\n\tuint8_t type;\n\tint32_t abs_x;\n\tint32_t abs_y;\n\tint32_t rel_z;\n};\n\nstruct xenkbd_mtouch {\n\tuint8_t type;\n\tuint8_t event_type;\n\tuint8_t contact_id;\n\tuint8_t reserved[5];\n\tunion {\n\t\tstruct {\n\t\t\tint32_t abs_x;\n\t\t\tint32_t abs_y;\n\t\t} pos;\n\t\tstruct {\n\t\t\tuint32_t major;\n\t\t\tuint32_t minor;\n\t\t} shape;\n\t\tint16_t orientation;\n\t} u;\n};\n\nunion xenkbd_in_event {\n\tuint8_t type;\n\tstruct xenkbd_motion motion;\n\tstruct xenkbd_key key;\n\tstruct xenkbd_position pos;\n\tstruct xenkbd_mtouch mtouch;\n\tchar pad[40];\n};\n\nstruct xenkbd_page;\n\nstruct xenkbd_info {\n\tstruct input_dev *kbd;\n\tstruct input_dev *ptr;\n\tstruct input_dev *mtouch;\n\tstruct xenkbd_page *page;\n\tint gref;\n\tint irq;\n\tstruct xenbus_device *xbdev;\n\tchar phys[32];\n\tint mtouch_cur_contact_id;\n};\n\nstruct xenkbd_page {\n\tuint32_t in_cons;\n\tuint32_t in_prod;\n\tuint32_t out_cons;\n\tuint32_t out_prod;\n};\n\nstruct xennet_gnttab_make_txreq {\n\tstruct netfront_queue *queue;\n\tstruct sk_buff *skb;\n\tstruct page *page;\n\tstruct xen_netif_tx_request *tx;\n\tstruct xen_netif_tx_request tx_local;\n\tunsigned int size;\n};\n\nstruct xennet_stat {\n\tchar name[32];\n\tu16 offset;\n};\n\nstruct xenon_emmc_phy_params {\n\tbool slow_mode;\n\tu8 znr;\n\tu8 zpr;\n\tu8 nr_tun_times;\n\tu8 tun_step_divider;\n\tstruct soc_pad_ctrl pad_ctrl;\n};\n\nstruct xenon_emmc_phy_regs {\n\tu16 timing_adj;\n\tu16 func_ctrl;\n\tu16 pad_ctrl;\n\tu16 pad_ctrl2;\n\tu16 dll_ctrl;\n\tu16 logic_timing_adj;\n\tu32 dll_update;\n\tu32 logic_timing_val;\n};\n\nstruct xenon_priv {\n\tunsigned char tuning_count;\n\tu8 sdhc_id;\n\tunsigned int init_card_type;\n\tunsigned char bus_width;\n\tunsigned char timing;\n\tunsigned int clock;\n\tstruct clk *axi_clk;\n\tint phy_type;\n\tvoid *phy_params;\n\tstruct xenon_emmc_phy_regs *emmc_phy_regs;\n\tbool restore_needed;\n\tenum xenon_variant hw_version;\n};\n\nstruct xenstore_domain_interface {\n\tchar req[1024];\n\tchar rsp[1024];\n\tXENSTORE_RING_IDX req_cons;\n\tXENSTORE_RING_IDX req_prod;\n\tXENSTORE_RING_IDX rsp_cons;\n\tXENSTORE_RING_IDX rsp_prod;\n\tuint32_t server_features;\n\tuint32_t connection;\n\tuint32_t error;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xgbe_page_alloc {\n\tstruct page *pages;\n\tunsigned int pages_len;\n\tunsigned int pages_offset;\n\tdma_addr_t pages_dma;\n};\n\nstruct xgbe_buffer_data {\n\tstruct xgbe_page_alloc pa;\n\tstruct xgbe_page_alloc pa_unmap;\n\tdma_addr_t dma_base;\n\tlong unsigned int dma_off;\n\tunsigned int dma_len;\n};\n\nstruct xgbe_prv_data;\n\nstruct xgbe_ring;\n\nstruct xgbe_channel {\n\tchar name[20];\n\tstruct xgbe_prv_data *pdata;\n\tunsigned int queue_index;\n\tvoid *dma_regs;\n\tint dma_irq;\n\tchar dma_irq_name[48];\n\tstruct napi_struct napi;\n\tunsigned int curr_ier;\n\tunsigned int saved_ier;\n\tunsigned int tx_timer_active;\n\tstruct timer_list tx_timer;\n\tstruct xgbe_ring *tx_ring;\n\tstruct xgbe_ring *rx_ring;\n\tint node;\n\tcpumask_t affinity_mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xgbe_ring_data;\n\nstruct xgbe_desc_if {\n\tint (*alloc_ring_resources)(struct xgbe_prv_data *);\n\tvoid (*free_ring_resources)(struct xgbe_prv_data *);\n\tint (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);\n\tint (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, struct xgbe_ring_data *);\n\tvoid (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);\n\tvoid (*wrapper_tx_desc_init)(struct xgbe_prv_data *);\n\tvoid (*wrapper_rx_desc_init)(struct xgbe_prv_data *);\n};\n\nstruct xgbe_ext_stats {\n\tu64 tx_tso_packets;\n\tu64 rx_split_header_packets;\n\tu64 rx_buffer_unavailable;\n\tu64 txq_packets[16];\n\tu64 txq_bytes[16];\n\tu64 rxq_packets[16];\n\tu64 rxq_bytes[16];\n\tu64 tx_vxlan_packets;\n\tu64 rx_vxlan_packets;\n\tu64 rx_csum_errors;\n\tu64 rx_vxlan_csum_errors;\n};\n\nstruct xgbe_hw_features {\n\tunsigned int version;\n\tunsigned int gmii;\n\tunsigned int vlhash;\n\tunsigned int sma;\n\tunsigned int rwk;\n\tunsigned int mgk;\n\tunsigned int mmc;\n\tunsigned int aoe;\n\tunsigned int ts;\n\tunsigned int eee;\n\tunsigned int tx_coe;\n\tunsigned int rx_coe;\n\tunsigned int addn_mac;\n\tunsigned int ts_src;\n\tunsigned int sa_vlan_ins;\n\tunsigned int vxn;\n\tunsigned int rx_fifo_size;\n\tunsigned int tx_fifo_size;\n\tunsigned int adv_ts_hi;\n\tunsigned int dma_width;\n\tunsigned int dcb;\n\tunsigned int sph;\n\tunsigned int tso;\n\tunsigned int dma_debug;\n\tunsigned int rss;\n\tunsigned int tc_cnt;\n\tunsigned int hash_table_size;\n\tunsigned int l3l4_filter_num;\n\tunsigned int rx_q_cnt;\n\tunsigned int tx_q_cnt;\n\tunsigned int rx_ch_cnt;\n\tunsigned int tx_ch_cnt;\n\tunsigned int pps_out_num;\n\tunsigned int aux_snap_num;\n};\n\nstruct xgbe_ring_desc;\n\nstruct xgbe_hw_if {\n\tint (*tx_complete)(struct xgbe_ring_desc *);\n\tint (*set_mac_address)(struct xgbe_prv_data *, const u8 *);\n\tint (*config_rx_mode)(struct xgbe_prv_data *);\n\tint (*enable_rx_csum)(struct xgbe_prv_data *);\n\tint (*disable_rx_csum)(struct xgbe_prv_data *);\n\tint (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);\n\tint (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);\n\tint (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);\n\tint (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);\n\tint (*update_vlan_hash_table)(struct xgbe_prv_data *);\n\tint (*read_mmd_regs)(struct xgbe_prv_data *, int, int);\n\tvoid (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);\n\tint (*set_speed)(struct xgbe_prv_data *, int);\n\tint (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, enum xgbe_mdio_mode);\n\tint (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int);\n\tint (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16);\n\tint (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int);\n\tint (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int, u16);\n\tint (*set_gpio)(struct xgbe_prv_data *, unsigned int);\n\tint (*clr_gpio)(struct xgbe_prv_data *, unsigned int);\n\tvoid (*enable_tx)(struct xgbe_prv_data *);\n\tvoid (*disable_tx)(struct xgbe_prv_data *);\n\tvoid (*enable_rx)(struct xgbe_prv_data *);\n\tvoid (*disable_rx)(struct xgbe_prv_data *);\n\tvoid (*powerup_tx)(struct xgbe_prv_data *);\n\tvoid (*powerdown_tx)(struct xgbe_prv_data *);\n\tvoid (*powerup_rx)(struct xgbe_prv_data *);\n\tvoid (*powerdown_rx)(struct xgbe_prv_data *);\n\tint (*init)(struct xgbe_prv_data *);\n\tint (*exit)(struct xgbe_prv_data *);\n\tint (*enable_int)(struct xgbe_channel *, enum xgbe_int);\n\tint (*disable_int)(struct xgbe_channel *, enum xgbe_int);\n\tvoid (*dev_xmit)(struct xgbe_channel *);\n\tint (*dev_read)(struct xgbe_channel *);\n\tvoid (*tx_desc_init)(struct xgbe_channel *);\n\tvoid (*rx_desc_init)(struct xgbe_channel *);\n\tvoid (*tx_desc_reset)(struct xgbe_ring_data *);\n\tvoid (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, unsigned int);\n\tint (*is_last_desc)(struct xgbe_ring_desc *);\n\tint (*is_context_desc)(struct xgbe_ring_desc *);\n\tvoid (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);\n\tint (*config_tx_flow_control)(struct xgbe_prv_data *);\n\tint (*config_rx_flow_control)(struct xgbe_prv_data *);\n\tint (*config_rx_coalesce)(struct xgbe_prv_data *);\n\tint (*config_tx_coalesce)(struct xgbe_prv_data *);\n\tunsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);\n\tunsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);\n\tint (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);\n\tint (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);\n\tint (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);\n\tint (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);\n\tint (*config_osp_mode)(struct xgbe_prv_data *);\n\tvoid (*rx_mmc_int)(struct xgbe_prv_data *);\n\tvoid (*tx_mmc_int)(struct xgbe_prv_data *);\n\tvoid (*read_mmc_stats)(struct xgbe_prv_data *);\n\tvoid (*config_tc)(struct xgbe_prv_data *);\n\tvoid (*config_dcb_tc)(struct xgbe_prv_data *);\n\tvoid (*config_dcb_pfc)(struct xgbe_prv_data *);\n\tint (*enable_rss)(struct xgbe_prv_data *);\n\tint (*disable_rss)(struct xgbe_prv_data *);\n\tint (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);\n\tint (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);\n\tvoid (*disable_ecc_ded)(struct xgbe_prv_data *);\n\tvoid (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);\n\tvoid (*enable_vxlan)(struct xgbe_prv_data *);\n\tvoid (*disable_vxlan)(struct xgbe_prv_data *);\n\tvoid (*set_vxlan_id)(struct xgbe_prv_data *);\n\tvoid (*enable_sph)(struct xgbe_prv_data *);\n\tvoid (*disable_sph)(struct xgbe_prv_data *);\n};\n\nstruct xgbe_i2c_op;\n\nstruct xgbe_i2c_op_state {\n\tstruct xgbe_i2c_op *op;\n\tunsigned int tx_len;\n\tunsigned char *tx_buf;\n\tunsigned int rx_len;\n\tunsigned char *rx_buf;\n\tunsigned int tx_abort_source;\n\tint ret;\n};\n\nstruct xgbe_i2c {\n\tunsigned int started;\n\tunsigned int max_speed_mode;\n\tunsigned int rx_fifo_size;\n\tunsigned int tx_fifo_size;\n\tstruct xgbe_i2c_op_state op_state;\n};\n\nstruct xgbe_i2c_if {\n\tint (*i2c_init)(struct xgbe_prv_data *);\n\tint (*i2c_start)(struct xgbe_prv_data *);\n\tvoid (*i2c_stop)(struct xgbe_prv_data *);\n\tint (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);\n\tirqreturn_t (*i2c_isr)(struct xgbe_prv_data *);\n};\n\nstruct xgbe_i2c_op {\n\tenum xgbe_i2c_cmd cmd;\n\tunsigned int target;\n\tvoid *buf;\n\tunsigned int len;\n};\n\nstruct xgbe_mmc_stats {\n\tu64 txoctetcount_gb;\n\tu64 txframecount_gb;\n\tu64 txbroadcastframes_g;\n\tu64 txmulticastframes_g;\n\tu64 tx64octets_gb;\n\tu64 tx65to127octets_gb;\n\tu64 tx128to255octets_gb;\n\tu64 tx256to511octets_gb;\n\tu64 tx512to1023octets_gb;\n\tu64 tx1024tomaxoctets_gb;\n\tu64 txunicastframes_gb;\n\tu64 txmulticastframes_gb;\n\tu64 txbroadcastframes_gb;\n\tu64 txunderflowerror;\n\tu64 txoctetcount_g;\n\tu64 txframecount_g;\n\tu64 txpauseframes;\n\tu64 txvlanframes_g;\n\tu64 rxframecount_gb;\n\tu64 rxoctetcount_gb;\n\tu64 rxoctetcount_g;\n\tu64 rxbroadcastframes_g;\n\tu64 rxmulticastframes_g;\n\tu64 rxcrcerror;\n\tu64 rxrunterror;\n\tu64 rxjabbererror;\n\tu64 rxundersize_g;\n\tu64 rxoversize_g;\n\tu64 rx64octets_gb;\n\tu64 rx65to127octets_gb;\n\tu64 rx128to255octets_gb;\n\tu64 rx256to511octets_gb;\n\tu64 rx512to1023octets_gb;\n\tu64 rx1024tomaxoctets_gb;\n\tu64 rxunicastframes_g;\n\tu64 rxlengtherror;\n\tu64 rxoutofrangetype;\n\tu64 rxpauseframes;\n\tu64 rxfifooverflow;\n\tu64 rxvlanframes_gb;\n\tu64 rxwatchdogerror;\n\tu64 rxalignmenterror;\n};\n\nstruct xgbe_packet_data {\n\tstruct sk_buff *skb;\n\tunsigned int attributes;\n\tunsigned int errors;\n\tunsigned int rdesc_count;\n\tunsigned int length;\n\tunsigned int header_len;\n\tunsigned int tcp_header_len;\n\tunsigned int tcp_payload_len;\n\tshort unsigned int mss;\n\tshort unsigned int vlan_ctag;\n\tu64 rx_tstamp;\n\tu32 rss_hash;\n\tenum pkt_hash_types rss_hash_type;\n\tunsigned int tx_packets;\n\tunsigned int tx_bytes;\n};\n\nstruct xgbe_phy {\n\tstruct ethtool_link_ksettings lks;\n\tint address;\n\tint autoneg;\n\tint speed;\n\tint duplex;\n\tint link;\n\tint pause_autoneg;\n\tint tx_pause;\n\tint rx_pause;\n};\n\nstruct xgbe_sfp_eeprom {\n\tu8 base[64];\n\tu8 extd[32];\n\tu8 vendor[32];\n};\n\nstruct xgbe_phy_data {\n\tenum xgbe_port_mode port_mode;\n\tunsigned int port_id;\n\tunsigned int port_speeds;\n\tenum xgbe_conn_type conn_type;\n\tenum xgbe_mode cur_mode;\n\tenum xgbe_mode start_mode;\n\tunsigned int rrc_count;\n\tunsigned int mdio_addr;\n\tenum xgbe_sfp_comm sfp_comm;\n\tunsigned int sfp_mux_address;\n\tunsigned int sfp_mux_channel;\n\tunsigned int sfp_gpio_address;\n\tunsigned int sfp_gpio_mask;\n\tunsigned int sfp_gpio_inputs;\n\tunsigned int sfp_gpio_rx_los;\n\tunsigned int sfp_gpio_tx_fault;\n\tunsigned int sfp_gpio_mod_absent;\n\tunsigned int sfp_gpio_rate_select;\n\tunsigned int sfp_rx_los;\n\tunsigned int sfp_tx_fault;\n\tunsigned int sfp_mod_absent;\n\tunsigned int sfp_changed;\n\tunsigned int sfp_phy_avail;\n\tunsigned int sfp_cable_len;\n\tenum xgbe_sfp_base sfp_base;\n\tenum xgbe_sfp_cable sfp_cable;\n\tenum xgbe_sfp_speed sfp_speed;\n\tstruct xgbe_sfp_eeprom sfp_eeprom;\n\tenum xgbe_mdio_mode phydev_mode;\n\tstruct mii_bus *mii;\n\tstruct phy_device *phydev;\n\tenum xgbe_mdio_reset mdio_reset;\n\tunsigned int mdio_reset_addr;\n\tunsigned int mdio_reset_gpio;\n\tunsigned int redrv;\n\tunsigned int redrv_if;\n\tunsigned int redrv_addr;\n\tunsigned int redrv_lane;\n\tunsigned int redrv_model;\n\tunsigned int phy_cdr_notrack;\n\tunsigned int phy_cdr_delay;\n};\n\nstruct xgbe_phy_data___2 {\n\tunsigned int speed_set;\n\tu32 blwc[3];\n\tu32 cdr_rate[3];\n\tu32 pq_skew[3];\n\tu32 tx_amp[3];\n\tu32 dfe_tap_cfg[3];\n\tu32 dfe_tap_ena[3];\n};\n\nstruct xgbe_phy_impl_if {\n\tint (*init)(struct xgbe_prv_data *);\n\tvoid (*exit)(struct xgbe_prv_data *);\n\tint (*reset)(struct xgbe_prv_data *);\n\tint (*start)(struct xgbe_prv_data *);\n\tvoid (*stop)(struct xgbe_prv_data *);\n\tint (*link_status)(struct xgbe_prv_data *, int *);\n\tbool (*valid_speed)(struct xgbe_prv_data *, int);\n\tbool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);\n\tvoid (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);\n\tenum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);\n\tenum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);\n\tenum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);\n\tenum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);\n\tint (*an_config)(struct xgbe_prv_data *);\n\tvoid (*an_advertising)(struct xgbe_prv_data *, struct ethtool_link_ksettings *);\n\tenum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);\n\tvoid (*an_pre)(struct xgbe_prv_data *);\n\tvoid (*an_post)(struct xgbe_prv_data *);\n\tvoid (*kr_training_pre)(struct xgbe_prv_data *);\n\tvoid (*kr_training_post)(struct xgbe_prv_data *);\n\tint (*module_info)(struct xgbe_prv_data *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct xgbe_prv_data *, struct ethtool_eeprom *, u8 *);\n};\n\nstruct xgbe_phy_if {\n\tint (*phy_init)(struct xgbe_prv_data *);\n\tvoid (*phy_exit)(struct xgbe_prv_data *);\n\tint (*phy_reset)(struct xgbe_prv_data *);\n\tint (*phy_start)(struct xgbe_prv_data *);\n\tvoid (*phy_stop)(struct xgbe_prv_data *);\n\tvoid (*phy_status)(struct xgbe_prv_data *);\n\tint (*phy_config_aneg)(struct xgbe_prv_data *);\n\tbool (*phy_valid_speed)(struct xgbe_prv_data *, int);\n\tirqreturn_t (*an_isr)(struct xgbe_prv_data *);\n\tint (*module_info)(struct xgbe_prv_data *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct xgbe_prv_data *, struct ethtool_eeprom *, u8 *);\n\tstruct xgbe_phy_impl_if phy_impl;\n};\n\nstruct xgbe_pps_config {\n\tstruct timespec64 start;\n\tstruct timespec64 period;\n};\n\nstruct xgbe_version_data;\n\nstruct xgbe_prv_data {\n\tstruct net_device *netdev;\n\tstruct pci_dev *pcidev;\n\tstruct platform_device *platdev;\n\tstruct acpi_device *adev;\n\tstruct device *dev;\n\tstruct platform_device *phy_platdev;\n\tstruct device *phy_dev;\n\tunsigned int smn_base;\n\tstruct xgbe_version_data *vdata;\n\tunsigned int use_acpi;\n\tvoid *xgmac_regs;\n\tvoid *xpcs_regs;\n\tvoid *rxtx_regs;\n\tvoid *sir0_regs;\n\tvoid *sir1_regs;\n\tvoid *xprop_regs;\n\tvoid *xi2c_regs;\n\tunsigned int pp0;\n\tunsigned int pp1;\n\tunsigned int pp2;\n\tunsigned int pp3;\n\tunsigned int pp4;\n\tspinlock_t xpcs_lock;\n\tunsigned int xpcs_window_def_reg;\n\tunsigned int xpcs_window_sel_reg;\n\tunsigned int xpcs_window;\n\tunsigned int xpcs_window_size;\n\tunsigned int xpcs_window_mask;\n\tstruct mutex rss_mutex;\n\tlong unsigned int dev_state;\n\tlong unsigned int tx_sec_period;\n\tlong unsigned int tx_ded_period;\n\tlong unsigned int rx_sec_period;\n\tlong unsigned int rx_ded_period;\n\tlong unsigned int desc_sec_period;\n\tlong unsigned int desc_ded_period;\n\tunsigned int tx_sec_count;\n\tunsigned int tx_ded_count;\n\tunsigned int rx_sec_count;\n\tunsigned int rx_ded_count;\n\tunsigned int desc_ded_count;\n\tunsigned int desc_sec_count;\n\tint dev_irq;\n\tint ecc_irq;\n\tint i2c_irq;\n\tint channel_irq[16];\n\tunsigned int per_channel_irq;\n\tunsigned int irq_count;\n\tunsigned int channel_irq_count;\n\tunsigned int channel_irq_mode;\n\tchar ecc_name[48];\n\tstruct xgbe_hw_if hw_if;\n\tstruct xgbe_phy_if phy_if;\n\tstruct xgbe_desc_if desc_if;\n\tstruct xgbe_i2c_if i2c_if;\n\tunsigned int coherent;\n\tunsigned int arcr;\n\tunsigned int awcr;\n\tunsigned int awarcr;\n\tstruct workqueue_struct *dev_workqueue;\n\tstruct work_struct service_work;\n\tstruct timer_list service_timer;\n\tstruct xgbe_channel *channel[16];\n\tunsigned int tx_max_channel_count;\n\tunsigned int rx_max_channel_count;\n\tunsigned int channel_count;\n\tunsigned int tx_ring_count;\n\tunsigned int tx_desc_count;\n\tunsigned int rx_ring_count;\n\tunsigned int rx_desc_count;\n\tunsigned int new_tx_ring_count;\n\tunsigned int new_rx_ring_count;\n\tunsigned int tx_max_q_count;\n\tunsigned int rx_max_q_count;\n\tunsigned int tx_q_count;\n\tunsigned int rx_q_count;\n\tunsigned int blen;\n\tunsigned int pbl;\n\tunsigned int aal;\n\tunsigned int rd_osr_limit;\n\tunsigned int wr_osr_limit;\n\tunsigned int tx_sf_mode;\n\tunsigned int tx_threshold;\n\tunsigned int tx_osp_mode;\n\tunsigned int tx_max_fifo_size;\n\tunsigned int rx_sf_mode;\n\tunsigned int rx_threshold;\n\tunsigned int rx_max_fifo_size;\n\tunsigned int tx_usecs;\n\tunsigned int tx_frames;\n\tunsigned int rx_riwt;\n\tunsigned int rx_usecs;\n\tunsigned int rx_frames;\n\tunsigned int rx_buf_size;\n\tunsigned int pause_autoneg;\n\tunsigned int tx_pause;\n\tunsigned int rx_pause;\n\tunsigned int rx_rfa[16];\n\tunsigned int rx_rfd[16];\n\tu8 rss_key[40];\n\tu32 rss_table[256];\n\tu32 rss_options;\n\tu16 vxlan_port;\n\tunsigned char mac_addr[6];\n\tnetdev_features_t netdev_features;\n\tstruct napi_struct napi;\n\tstruct xgbe_mmc_stats mmc_stats;\n\tstruct xgbe_ext_stats ext_stats;\n\tlong unsigned int active_vlans[64];\n\tstruct clk *sysclk;\n\tlong unsigned int sysclk_rate;\n\tstruct clk *ptpclk;\n\tlong unsigned int ptpclk_rate;\n\tspinlock_t tstamp_lock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct ptp_clock *ptp_clock;\n\tstruct kernel_hwtstamp_config tstamp_config;\n\tunsigned int tstamp_addend;\n\tstruct work_struct tx_tstamp_work;\n\tstruct sk_buff *tx_tstamp_skb;\n\tu64 tx_tstamp;\n\tstruct xgbe_pps_config pps[4];\n\tstruct ieee_ets *ets;\n\tstruct ieee_pfc *pfc;\n\tunsigned int q2tc_map[16];\n\tunsigned int prio2q_map[8];\n\tunsigned int pfcq[16];\n\tunsigned int pfc_rfa;\n\tu8 num_tcs;\n\tstruct xgbe_hw_features hw_feat;\n\tstruct work_struct restart_work;\n\tstruct work_struct stopdev_work;\n\tunsigned int power_down;\n\tu32 msg_enable;\n\tphy_interface_t phy_mode;\n\tint phy_link;\n\tint phy_speed;\n\tunsigned int phy_started;\n\tvoid *phy_data;\n\tstruct xgbe_phy phy;\n\tint mdio_mmd;\n\tlong unsigned int link_check;\n\tstruct completion mdio_complete;\n\tunsigned int kr_redrv;\n\tchar an_name[48];\n\tstruct workqueue_struct *an_workqueue;\n\tint an_irq;\n\tstruct work_struct an_irq_work;\n\tunsigned int an_int;\n\tunsigned int an_status;\n\tstruct mutex an_mutex;\n\tenum xgbe_an an_result;\n\tenum xgbe_an an_state;\n\tenum xgbe_rx kr_state;\n\tenum xgbe_rx kx_state;\n\tstruct work_struct an_work;\n\tunsigned int an_again;\n\tunsigned int an_supported;\n\tunsigned int parallel_detect;\n\tunsigned int fec_ability;\n\tlong unsigned int an_start;\n\tlong unsigned int kr_start_time;\n\tenum xgbe_an_mode an_mode;\n\tstruct xgbe_i2c i2c;\n\tstruct mutex i2c_mutex;\n\tstruct completion i2c_complete;\n\tchar i2c_name[48];\n\tunsigned int lpm_ctrl;\n\tunsigned int isr_as_bh_work;\n\tstruct work_struct dev_bh_work;\n\tstruct work_struct ecc_bh_work;\n\tstruct work_struct i2c_bh_work;\n\tstruct work_struct an_bh_work;\n\tstruct dentry *xgbe_debugfs;\n\tunsigned int debugfs_xgmac_reg;\n\tunsigned int debugfs_xpcs_mmd;\n\tunsigned int debugfs_xpcs_reg;\n\tunsigned int debugfs_xprop_reg;\n\tunsigned int debugfs_xi2c_reg;\n\tbool debugfs_an_cdr_workaround;\n\tbool debugfs_an_cdr_track_early;\n\tbool en_rx_adap;\n\tint rx_adapt_retries;\n\tbool rx_adapt_done;\n\tbool mode_set;\n\tbool sph;\n};\n\nstruct xgbe_ring {\n\tspinlock_t lock;\n\tstruct xgbe_packet_data packet_data;\n\tstruct xgbe_ring_desc *rdesc;\n\tdma_addr_t rdesc_dma;\n\tunsigned int rdesc_count;\n\tstruct xgbe_ring_data *rdata;\n\tstruct xgbe_page_alloc rx_hdr_pa;\n\tstruct xgbe_page_alloc rx_buf_pa;\n\tint node;\n\tunsigned int cur;\n\tunsigned int dirty;\n\tunsigned int coalesce_count;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int queue_stopped;\n\t\t\tunsigned int xmit_more;\n\t\t\tshort unsigned int cur_mss;\n\t\t\tshort unsigned int cur_vlan_ctag;\n\t\t} tx;\n\t};\n\tlong: 64;\n};\n\nstruct xgbe_tx_ring_data {\n\tunsigned int packets;\n\tunsigned int bytes;\n};\n\nstruct xgbe_rx_ring_data {\n\tstruct xgbe_buffer_data hdr;\n\tstruct xgbe_buffer_data buf;\n\tshort unsigned int hdr_len;\n\tshort unsigned int len;\n};\n\nstruct xgbe_ring_data {\n\tstruct xgbe_ring_desc *rdesc;\n\tdma_addr_t rdesc_dma;\n\tstruct sk_buff *skb;\n\tdma_addr_t skb_dma;\n\tunsigned int skb_dma_len;\n\tstruct xgbe_tx_ring_data tx;\n\tstruct xgbe_rx_ring_data rx;\n\tunsigned int mapped_as_page;\n\tunsigned int state_saved;\n\tstruct {\n\t\tstruct sk_buff *skb;\n\t\tunsigned int len;\n\t\tunsigned int error;\n\t} state;\n};\n\nstruct xgbe_ring_desc {\n\t__le32 desc0;\n\t__le32 desc1;\n\t__le32 desc2;\n\t__le32 desc3;\n};\n\nstruct xgbe_sfp_ascii {\n\tunion {\n\t\tchar vendor[17];\n\t\tchar partno[17];\n\t\tchar rev[5];\n\t\tchar serno[17];\n\t} u;\n};\n\nstruct xgbe_stats {\n\tchar stat_string[32];\n\tint stat_size;\n\tint stat_offset;\n};\n\nstruct xgbe_test {\n\tchar name[32];\n\tint lb;\n\tint (*fn)(struct xgbe_prv_data *);\n};\n\nstruct xgbe_version_data {\n\tvoid (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);\n\tenum xgbe_xpcs_access xpcs_access;\n\tunsigned int mmc_64bit;\n\tunsigned int tx_max_fifo_size;\n\tunsigned int rx_max_fifo_size;\n\tunsigned int tx_tstamp_workaround;\n\tunsigned int tstamp_ptp_clock_freq;\n\tunsigned int ecc_support;\n\tunsigned int i2c_support;\n\tunsigned int irq_reissue_support;\n\tunsigned int tx_desc_prefetch;\n\tunsigned int rx_desc_prefetch;\n\tunsigned int an_cdr_workaround;\n\tunsigned int enable_rrc;\n};\n\nstruct xgene_ahci_context {\n\tstruct ahci_host_priv *hpriv;\n\tstruct device *dev;\n\tu8 last_cmd[2];\n\tu32 class[2];\n\tvoid *csr_core;\n\tvoid *csr_diag;\n\tvoid *csr_axi;\n\tvoid *csr_mux;\n};\n\nstruct xgene_cle_dbptr {\n\tu8 split_boundary;\n\tu8 mirror_nxtfpsel;\n\tu8 mirror_fpsel;\n\tu16 mirror_dstqid;\n\tu8 drop;\n\tu8 mirror;\n\tu8 hdr_data_split;\n\tu64 hopinfomsbs;\n\tu8 DR;\n\tu8 HR;\n\tu64 hopinfomlsbs;\n\tu16 h0enq_num;\n\tu8 h0fpsel;\n\tu8 nxtfpsel;\n\tu8 fpsel;\n\tu16 dstqid;\n\tu8 cle_priority;\n\tu8 cle_flowgroup;\n\tu8 cle_perflow;\n\tu8 cle_insert_timestamp;\n\tu8 stash;\n\tu8 in;\n\tu8 perprioen;\n\tu8 perflowgroupen;\n\tu8 perflowen;\n\tu8 selhash;\n\tu8 selhdrext;\n\tu8 mirror_nxtfpsel_msb;\n\tu8 mirror_fpsel_msb;\n\tu8 hfpsel_msb;\n\tu8 nxtfpsel_msb;\n\tu8 fpsel_msb;\n};\n\nstruct xgene_enet_pdata;\n\nstruct xgene_cle_ops {\n\tint (*cle_init)(struct xgene_enet_pdata *);\n};\n\nstruct xgene_cle_ptree_kn;\n\nstruct xgene_cle_ptree {\n\tstruct xgene_cle_ptree_kn *kn;\n\tstruct xgene_cle_dbptr *dbptr;\n\tu32 num_kn;\n\tu32 num_dbptr;\n\tu32 start_node;\n\tu32 start_pkt;\n\tu32 start_dbptr;\n};\n\nstruct xgene_cle_ptree_branch {\n\tbool valid;\n\tu16 next_packet_pointer;\n\tbool jump_bw;\n\tbool jump_rel;\n\tu8 operation;\n\tu16 next_node;\n\tu8 next_branch;\n\tu16 data;\n\tu16 mask;\n};\n\nstruct xgene_cle_ptree_ewdn {\n\tu8 node_type;\n\tbool last_node;\n\tbool hdr_len_store;\n\tu8 hdr_extn;\n\tu8 byte_store;\n\tu8 search_byte_store;\n\tu16 result_pointer;\n\tu8 num_branches;\n\tstruct xgene_cle_ptree_branch branch[6];\n};\n\nstruct xgene_cle_ptree_key {\n\tu8 priority;\n\tu16 result_pointer;\n};\n\nstruct xgene_cle_ptree_kn {\n\tu8 node_type;\n\tu8 num_keys;\n\tstruct xgene_cle_ptree_key key[32];\n};\n\nstruct xgene_dev_parameters {\n\tvoid *csr_reg;\n\tu32 reg_clk_offset;\n\tu32 reg_clk_mask;\n\tu32 reg_csr_offset;\n\tu32 reg_csr_mask;\n\tvoid *divider_reg;\n\tu32 reg_divider_offset;\n\tu32 reg_divider_shift;\n\tu32 reg_divider_width;\n};\n\nstruct xgene_clk {\n\tstruct clk_hw hw;\n\tspinlock_t *lock;\n\tstruct xgene_dev_parameters param;\n};\n\nstruct xgene_clk_pll {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tspinlock_t *lock;\n\tu32 pll_offset;\n\tenum xgene_pll_type type;\n\tint version;\n};\n\nstruct xgene_clk_pmd {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu32 mask;\n\tu64 denom;\n\tu32 flags;\n\tspinlock_t *lock;\n};\n\nstruct xgene_enet_cle {\n\tvoid *base;\n\tstruct xgene_cle_ptree ptree;\n\tenum xgene_cle_parser active_parser;\n\tu32 parsers;\n\tu32 max_nodes;\n\tu32 max_dbptrs;\n\tu32 jump_bytes;\n};\n\nstruct xgene_enet_raw_desc;\n\nstruct xgene_enet_raw_desc16;\n\nstruct xgene_enet_desc_ring {\n\tstruct net_device *ndev;\n\tu16 id;\n\tu16 num;\n\tu16 head;\n\tu16 tail;\n\tu16 exp_buf_tail;\n\tu16 slots;\n\tu16 irq;\n\tchar irq_name[16];\n\tu32 size;\n\tu32 state[6];\n\tvoid *cmd_base;\n\tvoid *cmd;\n\tdma_addr_t dma;\n\tdma_addr_t irq_mbox_dma;\n\tvoid *irq_mbox_addr;\n\tu16 dst_ring_num;\n\tu16 nbufpool;\n\tint npagepool;\n\tu8 index;\n\tu32 flags;\n\tstruct sk_buff **rx_skb;\n\tstruct sk_buff **cp_skb;\n\tdma_addr_t *frag_dma_addr;\n\tstruct page **frag_page;\n\tenum xgene_enet_ring_cfgsize cfgsize;\n\tstruct xgene_enet_desc_ring *cp_ring;\n\tstruct xgene_enet_desc_ring *buf_pool;\n\tstruct xgene_enet_desc_ring *page_pool;\n\tstruct napi_struct napi;\n\tunion {\n\t\tvoid *desc_addr;\n\t\tstruct xgene_enet_raw_desc *raw_desc;\n\t\tstruct xgene_enet_raw_desc16 *raw_desc16;\n\t};\n\t__le64 *exp_bufs;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_dropped;\n\tu64 tx_errors;\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_dropped;\n\tu64 rx_errors;\n\tu64 rx_length_errors;\n\tu64 rx_crc_errors;\n\tu64 rx_frame_errors;\n\tu64 rx_fifo_errors;\n};\n\nstruct xgene_mac_ops;\n\nstruct xgene_port_ops;\n\nstruct xgene_ring_ops;\n\nstruct xgene_enet_pdata {\n\tstruct net_device *ndev;\n\tstruct mii_bus *mdio_bus;\n\tint phy_speed;\n\tstruct clk *clk;\n\tstruct platform_device *pdev;\n\tenum xgene_enet_id enet_id;\n\tstruct xgene_enet_desc_ring *tx_ring[8];\n\tstruct xgene_enet_desc_ring *rx_ring[8];\n\tu16 tx_level[8];\n\tu16 txc_level[8];\n\tchar *dev_name;\n\tu32 rx_buff_cnt;\n\tu32 tx_qcnt_hi;\n\tu32 irqs[16];\n\tu8 rxq_cnt;\n\tu8 txq_cnt;\n\tu8 cq_cnt;\n\tvoid *eth_csr_addr;\n\tvoid *eth_ring_if_addr;\n\tvoid *eth_diag_csr_addr;\n\tvoid *mcx_mac_addr;\n\tvoid *mcx_mac_csr_addr;\n\tvoid *mcx_stats_addr;\n\tvoid *base_addr;\n\tvoid *pcs_addr;\n\tvoid *ring_csr_addr;\n\tvoid *ring_cmd_addr;\n\tint phy_mode;\n\tenum xgene_enet_rm rm;\n\tstruct xgene_enet_cle cle;\n\tu64 *extd_stats;\n\tu64 false_rflr;\n\tu64 vlan_rjbr;\n\tspinlock_t stats_lock;\n\tconst struct xgene_mac_ops *mac_ops;\n\tspinlock_t mac_lock;\n\tconst struct xgene_port_ops *port_ops;\n\tstruct xgene_ring_ops *ring_ops;\n\tconst struct xgene_cle_ops *cle_ops;\n\tstruct delayed_work link_work;\n\tu32 port_id;\n\tu8 cpu_bufnum;\n\tu8 eth_bufnum;\n\tu8 bp_bufnum;\n\tu16 ring_num;\n\tu32 mss[4];\n\tu32 mss_refcnt[4];\n\tspinlock_t mss_lock;\n\tu8 tx_delay;\n\tu8 rx_delay;\n\tbool mdio_driver;\n\tstruct gpio_desc *sfp_rdy;\n\tbool sfp_gpio_en;\n\tu32 pause_autoneg;\n\tbool tx_pause;\n\tbool rx_pause;\n};\n\nstruct xgene_enet_raw_desc {\n\t__le64 m0;\n\t__le64 m1;\n\t__le64 m2;\n\t__le64 m3;\n};\n\nstruct xgene_enet_raw_desc16 {\n\t__le64 m0;\n\t__le64 m1;\n};\n\nstruct xgene_gpio {\n\tstruct gpio_chip chip;\n\tvoid *base;\n\tspinlock_t lock;\n\tu32 set_dr_val[3];\n};\n\nstruct xgene_gpio_sb {\n\tstruct gpio_generic_chip chip;\n\tvoid *regs;\n\tstruct irq_domain *irq_domain;\n\tu16 irq_start;\n\tu16 nirq;\n\tu16 parent_irq_base;\n};\n\nstruct xgene_gstrings_stats {\n\tchar name[32];\n\tint offset;\n\tu32 addr;\n\tu32 mask;\n};\n\nstruct xgene_mac_ops {\n\tvoid (*init)(struct xgene_enet_pdata *);\n\tvoid (*reset)(struct xgene_enet_pdata *);\n\tvoid (*tx_enable)(struct xgene_enet_pdata *);\n\tvoid (*rx_enable)(struct xgene_enet_pdata *);\n\tvoid (*tx_disable)(struct xgene_enet_pdata *);\n\tvoid (*rx_disable)(struct xgene_enet_pdata *);\n\tvoid (*get_drop_cnt)(struct xgene_enet_pdata *, u32 *, u32 *);\n\tvoid (*set_speed)(struct xgene_enet_pdata *);\n\tvoid (*set_mac_addr)(struct xgene_enet_pdata *);\n\tvoid (*set_framesize)(struct xgene_enet_pdata *, int);\n\tvoid (*set_mss)(struct xgene_enet_pdata *, u16, u8);\n\tvoid (*link_state)(struct work_struct *);\n\tvoid (*enable_tx_pause)(struct xgene_enet_pdata *, bool);\n\tvoid (*flowctl_rx)(struct xgene_enet_pdata *, bool);\n\tvoid (*flowctl_tx)(struct xgene_enet_pdata *, bool);\n};\n\nstruct xgene_mdio_pdata {\n\tstruct clk *clk;\n\tstruct device *dev;\n\tvoid *mac_csr_addr;\n\tvoid *diag_csr_addr;\n\tvoid *mdio_csr_addr;\n\tstruct mii_bus *mdio_bus;\n\tint mdio_id;\n\tspinlock_t mac_lock;\n};\n\nstruct xgene_msi {\n\tstruct irq_domain *inner_domain;\n\tu64 msi_addr;\n\tvoid *msi_regs;\n\tlong unsigned int *bitmap;\n\tstruct mutex bitmap_lock;\n\tunsigned int gic_irq[16];\n};\n\nstruct xgene_pcie {\n\tstruct device_node *node;\n\tstruct device *dev;\n\tstruct clk *clk;\n\tvoid *csr_base;\n\tvoid *cfg_base;\n\tlong unsigned int cfg_addr;\n\tbool link_up;\n\tu32 version;\n};\n\nstruct xgene_sata_override_param {\n\tu32 speed[2];\n\tu32 txspeed[3];\n\tu32 txboostgain[6];\n\tu32 txeyetuning[6];\n\tu32 txeyedirection[6];\n\tu32 txamplitude[6];\n\tu32 txprecursor_cn1[6];\n\tu32 txprecursor_cn2[6];\n\tu32 txpostcursor_cp1[6];\n};\n\nstruct xgene_phy_ctx {\n\tstruct device *dev;\n\tstruct phy *phy;\n\tenum xgene_phy_mode mode;\n\tenum clk_type_t clk_type;\n\tvoid *sds_base;\n\tstruct clk *clk;\n\tstruct xgene_sata_override_param sata_param;\n};\n\nstruct xgene_port_ops {\n\tint (*reset)(struct xgene_enet_pdata *);\n\tvoid (*clear)(struct xgene_enet_pdata *, struct xgene_enet_desc_ring *);\n\tvoid (*cle_bypass)(struct xgene_enet_pdata *, u32, u16, u16);\n\tvoid (*shutdown)(struct xgene_enet_pdata *);\n};\n\nstruct xgene_reboot_context {\n\tstruct device *dev;\n\tvoid *csr;\n\tu32 mask;\n};\n\nstruct xgene_ring_ops {\n\tu8 num_ring_config;\n\tu8 num_ring_id_shift;\n\tstruct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);\n\tvoid (*clear)(struct xgene_enet_desc_ring *);\n\tvoid (*wr_cmd)(struct xgene_enet_desc_ring *, int);\n\tu32 (*len)(struct xgene_enet_desc_ring *);\n\tvoid (*coalesce)(struct xgene_enet_desc_ring *);\n};\n\nstruct xgene_rng_dev {\n\tu32 irq;\n\tvoid *csr_base;\n\tu32 revision;\n\tu32 datum_size;\n\tu32 failure_cnt;\n\tlong unsigned int failure_ts;\n\tstruct timer_list failure_timer;\n\tstruct device *dev;\n};\n\nstruct xgene_rtc_dev {\n\tstruct rtc_device *rtc;\n\tvoid *csr_base;\n\tstruct clk *clk;\n\tunsigned int irq_wake;\n\tunsigned int irq_enabled;\n};\n\nstruct xhci_bus_state {\n\tlong unsigned int bus_suspended;\n\tlong unsigned int next_statechange;\n\tu32 port_c_suspend;\n\tu32 suspended_ports;\n\tu32 port_remote_wakeup;\n\tlong unsigned int resuming_ports;\n};\n\nstruct xhci_bw_info {\n\tunsigned int ep_interval;\n\tunsigned int mult;\n\tunsigned int num_packets;\n\tunsigned int max_packet_size;\n\tunsigned int max_esit_payload;\n\tunsigned int type;\n};\n\nstruct xhci_cap_regs {\n\t__le32 hc_capbase;\n\t__le32 hcs_params1;\n\t__le32 hcs_params2;\n\t__le32 hcs_params3;\n\t__le32 hcc_params;\n\t__le32 db_off;\n\t__le32 run_regs_off;\n\t__le32 hcc_params2;\n};\n\nstruct xhci_container_ctx;\n\nstruct xhci_command {\n\tstruct xhci_container_ctx *in_ctx;\n\tu32 status;\n\tu32 comp_param;\n\tint slot_id;\n\tstruct completion *completion;\n\tunion xhci_trb *command_trb;\n\tstruct list_head cmd_list;\n\tunsigned int timeout_ms;\n};\n\nstruct xhci_container_ctx {\n\tunsigned int type;\n\tint size;\n\tu8 *bytes;\n\tdma_addr_t dma;\n};\n\nstruct xhci_erst_entry;\n\nstruct xhci_erst {\n\tstruct xhci_erst_entry *entries;\n\tunsigned int num_entries;\n\tdma_addr_t erst_dma_addr;\n};\n\nstruct xhci_hcd;\n\nstruct xhci_dbc {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tstruct xhci_hcd *xhci;\n\tstruct dbc_regs *regs;\n\tstruct xhci_ring *ring_evt;\n\tstruct xhci_ring *ring_in;\n\tstruct xhci_ring *ring_out;\n\tstruct xhci_erst erst;\n\tstruct xhci_container_ctx *ctx;\n\tstruct dbc_str_descs *str_descs;\n\tdma_addr_t str_descs_dma;\n\tsize_t str_descs_size;\n\tstruct dbc_str str;\n\tu16 idVendor;\n\tu16 idProduct;\n\tu16 bcdDevice;\n\tu8 bInterfaceProtocol;\n\tenum dbc_state state;\n\tstruct delayed_work event_work;\n\tunsigned int poll_interval;\n\tlong unsigned int xfer_timestamp;\n\tunsigned int resume_required: 1;\n\tstruct dbc_ep eps[2];\n\tconst struct dbc_driver *driver;\n\tvoid *priv;\n};\n\nstruct xhci_device_context_array {\n\t__le64 dev_context_ptrs[256];\n\tdma_addr_t dma;\n};\n\nstruct xhci_doorbell_array {\n\t__le32 doorbell[256];\n};\n\nstruct xhci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n};\n\nstruct xhci_ep_ctx {\n\t__le32 ep_info;\n\t__le32 ep_info2;\n\t__le64 deq;\n\t__le32 tx_info;\n\t__le32 reserved[3];\n};\n\nstruct xhci_stream_info;\n\nstruct xhci_ep_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *show_ring;\n\tunsigned int stream_id;\n};\n\nstruct xhci_erst_entry {\n\t__le64 seg_addr;\n\t__le32 seg_size;\n\t__le32 rsvd;\n};\n\nstruct xhci_event_cmd {\n\t__le64 cmd_trb;\n\t__le32 status;\n\t__le32 flags;\n};\n\nstruct xhci_file_map {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct xhci_generic_trb {\n\t__le32 field[4];\n};\n\nstruct xhci_port;\n\nstruct xhci_hub {\n\tstruct xhci_port **ports;\n\tunsigned int num_ports;\n\tstruct usb_hcd *hcd;\n\tstruct xhci_bus_state bus_state;\n\tu8 maj_rev;\n\tu8 min_rev;\n};\n\nstruct xhci_op_regs;\n\nstruct xhci_run_regs;\n\nstruct xhci_interrupter;\n\nstruct xhci_scratchpad;\n\nstruct xhci_virt_device;\n\nstruct xhci_root_port_bw_info;\n\nstruct xhci_port_cap;\n\nstruct xhci_hcd {\n\tstruct usb_hcd *main_hcd;\n\tstruct usb_hcd *shared_hcd;\n\tstruct xhci_cap_regs *cap_regs;\n\tstruct xhci_op_regs *op_regs;\n\tstruct xhci_run_regs *run_regs;\n\tstruct xhci_doorbell_array *dba;\n\t__u32 hcs_params2;\n\t__u32 hcs_params3;\n\t__u32 hcc_params;\n\t__u32 hcc_params2;\n\tspinlock_t lock;\n\tu16 hci_version;\n\tu16 max_interrupters;\n\tu8 max_slots;\n\tu8 max_ports;\n\tu32 imod_interval;\n\tu32 page_size;\n\tint nvecs;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\tstruct reset_control *reset;\n\tstruct xhci_device_context_array *dcbaa;\n\tstruct xhci_interrupter **interrupters;\n\tstruct xhci_ring *cmd_ring;\n\tunsigned int cmd_ring_state;\n\tstruct list_head cmd_list;\n\tunsigned int cmd_ring_reserved_trbs;\n\tstruct delayed_work cmd_timer;\n\tstruct completion cmd_ring_stop_completion;\n\tstruct xhci_command *current_cmd;\n\tstruct xhci_scratchpad *scratchpad;\n\tstruct mutex mutex;\n\tstruct xhci_virt_device *devs[256];\n\tstruct xhci_root_port_bw_info *rh_bw;\n\tstruct dma_pool *device_pool;\n\tstruct dma_pool *segment_pool;\n\tstruct dma_pool *small_streams_pool;\n\tstruct dma_pool *port_bw_pool;\n\tstruct dma_pool *medium_streams_pool;\n\tunsigned int xhc_state;\n\tlong unsigned int run_graceperiod;\n\tstruct s3_save s3;\n\tlong long unsigned int quirks;\n\tunsigned int num_active_eps;\n\tunsigned int limit_active_eps;\n\tstruct xhci_port *hw_ports;\n\tstruct xhci_hub usb2_rhub;\n\tstruct xhci_hub usb3_rhub;\n\tunsigned int hw_lpm_support: 1;\n\tunsigned int broken_suspend: 1;\n\tunsigned int allow_single_roothub: 1;\n\tstruct xhci_port_cap *port_caps;\n\tunsigned int num_port_caps;\n\tstruct timer_list comp_mode_recovery_timer;\n\tu32 port_status_u0;\n\tu16 test_mode;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_slots;\n\tstruct list_head regset_list;\n\tvoid *dbc;\n\tlong unsigned int priv[0];\n};\n\nstruct xhci_hcd_mtk {\n\tstruct device *dev;\n\tstruct usb_hcd *hcd;\n\tstruct mu3h_sch_bw_info *sch_array;\n\tstruct list_head bw_ep_chk_list;\n\tstruct hlist_head sch_ep_hash[32];\n\tstruct mu3c_ippc_regs *ippc_regs;\n\tint num_u2_ports;\n\tint num_u3_ports;\n\tint u2p_dis_msk;\n\tint u3p_dis_msk;\n\tstruct clk_bulk_data clks[6];\n\tstruct regulator_bulk_data supplies[2];\n\tunsigned int has_ippc: 1;\n\tunsigned int lpm_support: 1;\n\tunsigned int u2_lpm_disable: 1;\n\tunsigned int uwk_en: 1;\n\tstruct regmap *uwk;\n\tu32 uwk_reg_base;\n\tu32 uwk_vers;\n\tu32 rxfifo_depth;\n};\n\nstruct xhci_input_control_ctx {\n\t__le32 drop_flags;\n\t__le32 add_flags;\n\t__le32 rsvd2[6];\n};\n\nstruct xhci_intr_reg;\n\nstruct xhci_interrupter {\n\tstruct xhci_ring *event_ring;\n\tstruct xhci_erst erst;\n\tstruct xhci_intr_reg *ir_set;\n\tunsigned int intr_num;\n\tbool ip_autoclear;\n\tu32 isoc_bei_interval;\n\tu32 s3_iman;\n\tu32 s3_imod;\n\tu32 s3_erst_size;\n\tu64 s3_erst_base;\n\tu64 s3_erst_dequeue;\n};\n\nstruct xhci_interval_bw {\n\tunsigned int num_packets;\n\tstruct list_head endpoints;\n\tunsigned int overhead[3];\n};\n\nstruct xhci_interval_bw_table {\n\tunsigned int interval0_esit_payload;\n\tstruct xhci_interval_bw interval_bw[16];\n\tunsigned int bw_used;\n\tunsigned int ss_bw_in;\n\tunsigned int ss_bw_out;\n};\n\nstruct xhci_intr_reg {\n\t__le32 iman;\n\t__le32 imod;\n\t__le32 erst_size;\n\t__le32 rsvd;\n\t__le64 erst_base;\n\t__le64 erst_dequeue;\n};\n\nstruct xhci_link_trb {\n\t__le64 segment_ptr;\n\t__le32 intr_target;\n\t__le32 control;\n};\n\nstruct xhci_port_regs {\n\t__le32 portsc;\n\t__le32 portpmsc;\n\t__le32 portli;\n\t__le32 porthlmpc;\n};\n\nstruct xhci_op_regs {\n\t__le32 command;\n\t__le32 status;\n\t__le32 page_size;\n\t__le32 reserved1;\n\t__le32 reserved2;\n\t__le32 dev_notification;\n\t__le64 cmd_ring;\n\t__le32 reserved3[4];\n\t__le64 dcbaa_ptr;\n\t__le32 config_reg;\n\t__le32 reserved4[241];\n\tstruct xhci_port_regs port_regs[0];\n};\n\nstruct xhci_plat_priv {\n\tconst char *firmware_name;\n\tlong long unsigned int quirks;\n\tbool power_lost;\n\tunsigned int sideband_at_suspend: 1;\n\tvoid (*plat_start)(struct usb_hcd *);\n\tint (*init_quirk)(struct usb_hcd *);\n\tint (*suspend_quirk)(struct usb_hcd *);\n\tint (*resume_quirk)(struct usb_hcd *);\n\tint (*post_resume_quirk)(struct usb_hcd *);\n};\n\nstruct xhci_port {\n\tstruct xhci_port_regs *port_reg;\n\tint hw_portnum;\n\tint hcd_portnum;\n\tstruct xhci_hub *rhub;\n\tstruct xhci_port_cap *port_cap;\n\tunsigned int lpm_incapable: 1;\n\tlong unsigned int resume_timestamp;\n\tbool rexit_active;\n\tint slot_id;\n\tstruct completion rexit_done;\n\tstruct completion u3exit_done;\n};\n\nstruct xhci_port_cap {\n\tu32 *psi;\n\tu8 psi_count;\n\tu8 psi_uid_count;\n\tu8 maj_rev;\n\tu8 min_rev;\n\tu32 protocol_caps;\n};\n\nstruct xhci_regset {\n\tchar name[32];\n\tstruct debugfs_regset32 regset;\n\tsize_t nregs;\n\tstruct list_head list;\n};\n\nstruct xhci_ring {\n\tstruct xhci_segment *first_seg;\n\tstruct xhci_segment *last_seg;\n\tunion xhci_trb *enqueue;\n\tstruct xhci_segment *enq_seg;\n\tunion xhci_trb *dequeue;\n\tstruct xhci_segment *deq_seg;\n\tstruct list_head td_list;\n\tu32 cycle_state;\n\tunsigned int stream_id;\n\tunsigned int num_segs;\n\tunsigned int num_trbs_free;\n\tunsigned int bounce_buf_len;\n\tenum xhci_ring_type type;\n\tu32 old_trb_comp_code;\n\tstruct xarray *trb_address_map;\n};\n\nstruct xhci_root_port_bw_info {\n\tstruct list_head tts;\n\tunsigned int num_active_tts;\n\tstruct xhci_interval_bw_table bw_table;\n};\n\nstruct xhci_run_regs {\n\t__le32 microframe_index;\n\t__le32 rsvd[7];\n\tstruct xhci_intr_reg ir_set[1024];\n};\n\nstruct xhci_scratchpad {\n\tu64 *sp_array;\n\tdma_addr_t sp_dma;\n\tvoid **sp_buffers;\n};\n\nstruct xhci_segment {\n\tunion xhci_trb *trbs;\n\tstruct xhci_segment *next;\n\tunsigned int num;\n\tdma_addr_t dma;\n\tdma_addr_t bounce_dma;\n\tvoid *bounce_buf;\n\tunsigned int bounce_offs;\n\tunsigned int bounce_len;\n};\n\nstruct xhci_virt_ep;\n\nstruct xhci_sideband_event;\n\nstruct xhci_sideband {\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_virt_device *vdev;\n\tstruct xhci_virt_ep *eps[31];\n\tstruct xhci_interrupter *ir;\n\tenum xhci_sideband_type type;\n\tstruct mutex mutex;\n\tstruct usb_interface *intf;\n\tint (*notify_client)(struct usb_interface *, struct xhci_sideband_event *);\n};\n\nstruct xhci_sideband_event {\n\tenum xhci_sideband_notify_type type;\n\tvoid *evt_data;\n};\n\nstruct xhci_slot_ctx {\n\t__le32 dev_info;\n\t__le32 dev_info2;\n\t__le32 tt_info;\n\t__le32 dev_state;\n\t__le32 reserved[4];\n};\n\nstruct xhci_slot_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_ep_priv *eps[31];\n\tstruct xhci_virt_device *dev;\n};\n\nstruct xhci_stream_ctx {\n\t__le64 stream_ring;\n\t__le32 reserved[2];\n};\n\nstruct xhci_stream_info {\n\tstruct xhci_ring **stream_rings;\n\tunsigned int num_streams;\n\tstruct xhci_stream_ctx *stream_ctx_array;\n\tunsigned int num_stream_ctxs;\n\tdma_addr_t ctx_array_dma;\n\tstruct xarray trb_address_map;\n\tstruct xhci_command *free_streams_command;\n};\n\nstruct xhci_transfer_event {\n\t__le64 buffer;\n\t__le32 transfer_len;\n\t__le32 flags;\n};\n\nunion xhci_trb {\n\tstruct xhci_link_trb link;\n\tstruct xhci_transfer_event trans_event;\n\tstruct xhci_event_cmd event_cmd;\n\tstruct xhci_generic_trb generic;\n};\n\nstruct xhci_tt_bw_info {\n\tstruct list_head tt_list;\n\tint slot_id;\n\tint ttport;\n\tstruct xhci_interval_bw_table bw_table;\n\tint active_eps;\n};\n\nstruct xhci_virt_ep {\n\tstruct xhci_virt_device *vdev;\n\tunsigned int ep_index;\n\tstruct xhci_ring *ring;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *new_ring;\n\tunsigned int err_count;\n\tunsigned int ep_state;\n\tstruct list_head cancelled_td_list;\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_segment *queued_deq_seg;\n\tunion xhci_trb *queued_deq_ptr;\n\tbool skip;\n\tstruct xhci_bw_info bw_info;\n\tstruct list_head bw_endpoint_list;\n\tlong unsigned int stop_time;\n\tint next_frame_id;\n\tbool use_extended_tbc;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xhci_virt_device {\n\tint slot_id;\n\tstruct usb_device *udev;\n\tstruct xhci_container_ctx *out_ctx;\n\tstruct xhci_container_ctx *in_ctx;\n\tstruct xhci_virt_ep eps[31];\n\tstruct xhci_port *rhub_port;\n\tstruct xhci_interval_bw_table *bw_table;\n\tstruct xhci_tt_bw_info *tt_info;\n\tlong unsigned int flags;\n\tu16 current_mel;\n\tvoid *debugfs_private;\n\tstruct xhci_sideband *sideband;\n};\n\nstruct xilinx_cpm_variant;\n\nstruct xilinx_cpm_pcie {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tvoid *cpm_base;\n\tstruct irq_domain *intx_domain;\n\tstruct irq_domain *cpm_domain;\n\tstruct pci_config_window *cfg;\n\tint intx_irq;\n\tint irq;\n\traw_spinlock_t lock;\n\tconst struct xilinx_cpm_variant *variant;\n};\n\nstruct xilinx_cpm_variant {\n\tenum xilinx_cpm_version version;\n\tu32 ir_status;\n\tu32 ir_enable;\n\tu32 ir_misc_value;\n};\n\nstruct xilinx_pcie {\n\tstruct device *dev;\n\tvoid *reg_base;\n\tlong unsigned int msi_map[2];\n\tstruct mutex map_lock;\n\tstruct irq_domain *msi_domain;\n\tstruct irq_domain *leg_domain;\n\tstruct list_head resources;\n};\n\nstruct xilinx_pl_dma_variant {\n\tenum xilinx_pl_dma_version version;\n};\n\nstruct xintc_irq_chip {\n\tvoid *base;\n\tstruct irq_domain *root_domain;\n\tu32 intr_mask;\n\tu32 nr_irq;\n};\n\nstruct xlnx_feature {\n\tu32 family;\n\tu32 feature_id;\n\tvoid *data;\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tlong unsigned int *bitmap;\n\tstruct page *page;\n\tlong unsigned int vaddr;\n};\n\nstruct xprt_addr {\n\tconst char *addr;\n\tstruct callback_head rcu;\n};\n\nstruct xprt_create;\n\nstruct xprt_class {\n\tstruct list_head list;\n\tint ident;\n\tstruct rpc_xprt * (*setup)(struct xprt_create *);\n\tstruct module *owner;\n\tchar name[32];\n\tconst char *netid[0];\n};\n\nstruct xprt_create {\n\tint ident;\n\tstruct net *net;\n\tstruct sockaddr *srcaddr;\n\tstruct sockaddr *dstaddr;\n\tsize_t addrlen;\n\tconst char *servername;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rpc_xprt_switch *bc_xps;\n\tunsigned int flags;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xs_watch_event {\n\tstruct list_head list;\n\tunsigned int len;\n\tstruct xenbus_watch *handle;\n\tconst char *path;\n\tconst char *token;\n\tchar body[0];\n};\n\nstruct xsd_errors {\n\tint errnum;\n\tconst char *errstring;\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\nstruct za_context {\n\tstruct _aarch64_ctx head;\n\t__u16 vl;\n\t__u16 __reserved[3];\n};\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\nstruct zt_context {\n\tstruct _aarch64_ctx head;\n\t__u16 nregs;\n\t__u16 __reserved[3];\n};\n\nstruct zynqmp_clk_divider {\n\tstruct clk_hw hw;\n\tu8 flags;\n\tbool is_frac;\n\tu32 clk_id;\n\tu32 div_type;\n\tu16 max_div;\n};\n\nstruct zynqmp_clk_gate {\n\tstruct clk_hw hw;\n\tu8 flags;\n\tu32 clk_id;\n};\n\nstruct zynqmp_clk_mux {\n\tstruct clk_hw hw;\n\tu8 flags;\n\tu32 clk_id;\n};\n\nstruct zynqmp_clock {\n\tchar clk_name[50];\n\tu32 valid;\n\tenum clk_type type;\n\tstruct clock_topology node[6];\n\tu32 num_nodes;\n\tstruct clock_parent parent[100];\n\tu32 num_parents;\n\tu32 clk_id;\n};\n\nstruct zynqmp_devinfo {\n\tstruct device *dev;\n\tu32 feature_conf_id;\n};\n\nstruct zynqmp_ipi_mchan {\n\tint is_opened;\n\tvoid *req_buf;\n\tvoid *resp_buf;\n\tvoid *rx_buf;\n\tsize_t req_buf_size;\n\tsize_t resp_buf_size;\n\tunsigned int chan_type;\n};\n\nstruct zynqmp_ipi_mbox;\n\ntypedef int (*setup_ipi_fn)(struct zynqmp_ipi_mbox *, struct device_node *);\n\nstruct zynqmp_ipi_pdata;\n\nstruct zynqmp_ipi_mbox {\n\tstruct zynqmp_ipi_pdata *pdata;\n\tstruct device dev;\n\tu32 remote_id;\n\tstruct mbox_controller mbox;\n\tstruct zynqmp_ipi_mchan mchans[2];\n\tsetup_ipi_fn setup_ipi_fn;\n};\n\nstruct zynqmp_ipi_message {\n\tsize_t len;\n\tu8 data[0];\n};\n\nstruct zynqmp_ipi_pdata {\n\tstruct device *dev;\n\tint irq;\n\tunsigned int irq_type;\n\tunsigned int method;\n\tu32 local_id;\n\tint virq_sgi;\n\tint num_mboxes;\n\tstruct zynqmp_ipi_mbox ipi_mboxes[0];\n};\n\nstruct zynqmp_pctrl_group {\n\tconst char *name;\n\tunsigned int pins[50];\n\tunsigned int npins;\n};\n\nstruct zynqmp_pmux_function;\n\nstruct zynqmp_pinctrl {\n\tstruct pinctrl_dev *pctrl;\n\tconst struct zynqmp_pctrl_group *groups;\n\tunsigned int ngroups;\n\tconst struct zynqmp_pmux_function *funcs;\n\tunsigned int nfuncs;\n};\n\nstruct zynqmp_pll {\n\tstruct clk_hw hw;\n\tu32 clk_id;\n\tbool set_pll_mode;\n};\n\nstruct zynqmp_pm_domain {\n\tstruct generic_pm_domain gpd;\n\tu32 node_id;\n\tbool requested;\n};\n\nstruct zynqmp_pm_event_info {\n\tevent_cb_func_t cb_fun;\n\tenum pm_api_cb_id cb_type;\n\tu32 node_id;\n\tu32 event;\n\tbool wake;\n};\n\nstruct zynqmp_pm_query_data {\n\tu32 qid;\n\tu32 arg1;\n\tu32 arg2;\n\tu32 arg3;\n};\n\nstruct zynqmp_pm_shutdown_scope {\n\tconst enum zynqmp_pm_shutdown_subtype subtype;\n\tconst char *name;\n};\n\nstruct zynqmp_pm_work_struct {\n\tstruct work_struct callback_work;\n\tu32 args[4];\n};\n\nstruct zynqmp_pmux_function {\n\tchar name[16];\n\tconst char * const *groups;\n\tunsigned int ngroups;\n};\n\nstruct zynqmp_reset_soc_data;\n\nstruct zynqmp_reset_data {\n\tstruct reset_controller_dev rcdev;\n\tconst struct zynqmp_reset_soc_data *data;\n};\n\nstruct zynqmp_reset_soc_data {\n\tu32 reset_id;\n\tu32 num_resets;\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef u32 (*acpi_event_handler)(void *);\n\ntypedef acpi_status (*acpi_exception_handler)(acpi_status, acpi_name, u16, u32, void *);\n\ntypedef acpi_status (*acpi_execute_op)(struct acpi_walk_state *);\n\ntypedef void (*acpi_gbl_event_handler)(u32, acpi_handle, u32, void *);\n\ntypedef struct fwnode_handle * (*acpi_gsi_domain_disp_fn)(u32);\n\ntypedef acpi_status (*acpi_init_handler)(acpi_handle, u32);\n\ntypedef u32 (*acpi_interface_handler)(acpi_string, u32);\n\ntypedef u32 (*acpi_osd_handler)(void *);\n\ntypedef acpi_status (*acpi_pkg_callback)(u8, union acpi_operand_object *, union acpi_generic_state *, void *);\n\ntypedef acpi_status (*acpi_table_handler)(u32, void *, void *);\n\ntypedef acpi_status (*acpi_walk_aml_callback)(u8 *, u32, u32, u8, void **);\n\ntypedef acpi_status (*acpi_walk_resource_callback)(struct acpi_resource *, void *);\n\ntypedef void (*alternative_cb_t)(struct alt_instr *, __le32 *, __le32 *, int);\n\ntypedef int (*apei_exec_entry_func_t)(struct apei_exec_context *, struct acpi_whea_header *, void *);\n\ntypedef int (*apei_hest_func_t)(struct acpi_hest_header *, void *);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\ntypedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, const void *);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u32 (*bpf_prog_run_fn)(const struct bpf_prog *, const void *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_d_path)(const struct path *, char *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_pe)(struct bpf_perf_event_data_kern *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_trace)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_branch_snapshot)(void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_task)(void);\n\ntypedef u64 (*btf_bpf_get_current_task_btf)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_func_ip_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_local_storage)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sockopt)(struct bpf_sockopt_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_retval)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_pe)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_sleepable)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_pe)(struct bpf_perf_event_data_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack_sleepable)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_probe_read_compat)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_printf_btf)(struct seq_file *, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_set_retval)(int);\n\ntypedef u64 (*btf_bpf_sk_ancestor_cgroup_id)(struct sock *, int);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_cgroup_id)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_ancestor_cgroup_id)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_cgroup_id)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_snprintf_btf)(char *, u32, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_sysctl_get_current_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_get_name)(struct bpf_sysctl_kern *, char *, size_t, u64);\n\ntypedef u64 (*btf_bpf_sysctl_get_new_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_set_new_value)(struct bpf_sysctl_kern *, const char *, size_t);\n\ntypedef u64 (*btf_bpf_task_pt_regs)(struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_vprintk)(char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_get_func_arg)(void *, u32, u64 *);\n\ntypedef u64 (*btf_get_func_arg_cnt)(void *);\n\ntypedef u64 (*btf_get_func_ret)(void *, u64 *);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*btf_trace_9p_client_req)(void *, struct p9_client *, int8_t, int);\n\ntypedef void (*btf_trace_9p_client_res)(void *, struct p9_client *, int8_t, int, int);\n\ntypedef void (*btf_trace_9p_fid_ref)(void *, struct p9_fid *, __u8);\n\ntypedef void (*btf_trace_9p_protocol_dump)(void *, struct p9_client *, struct p9_fcall *);\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_aer_event)(void *, const char *, const u32, const u8, const u8, struct pcie_tlp_log *, const char *);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_suspend)(void *, ktime_t, int);\n\ntypedef void (*btf_trace_alloc_vmap_area)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_aoss_send)(void *, const char *);\n\ntypedef void (*btf_trace_aoss_send_done)(void *, const char *, int);\n\ntypedef void (*btf_trace_arm_event)(void *, const struct cper_sec_proc_arm *, const u8 *, const u32, const u8 *, const u32, const u8 *, const u32, u8, int);\n\ntypedef void (*btf_trace_ata_bmdma_setup)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_start)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_status)(void *, struct ata_port *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_stop)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_about_to_do)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_done)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy)(void *, struct ata_device *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy_qc)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_exec_command)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_softreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_softreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_port_freeze)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_port_thaw)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_qc_complete_done)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_failed)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_internal)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_issue)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_prep)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_sff_flush_pio_task)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_sff_hsm_command_complete)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_hsm_state)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_sff_port_intr)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_slave_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_slave_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_slave_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_std_sched_eh)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_tf_load)(void *, struct ata_port *, const struct ata_taskfile *);\n\ntypedef void (*btf_trace_atapi_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_atapi_send_cdb)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, struct dirty_throttle_control *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_bl_ext_tree_prepare_commit)(void *, int, size_t, u64, bool);\n\ntypedef void (*btf_trace_bl_pr_key_reg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_reg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_bl_pr_key_unreg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_unreg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_blk_zone_append_update_request_bio)(void *, struct request *);\n\ntypedef void (*btf_trace_blk_zone_wplug_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_blkdev_zone_mgmt)(void *, struct bio *, sector_t);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_io_done)(void *, struct request *);\n\ntypedef void (*btf_trace_block_io_start)(void *, struct request *);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_error)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_merge)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_split)(void *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\ntypedef void (*btf_trace_bpf_trace_printk)(void *, const char *);\n\ntypedef void (*btf_trace_bpf_trigger_tp)(void *, int);\n\ntypedef void (*btf_trace_bpf_xdp_link_attach_failed)(void *, const char *);\n\ntypedef void (*btf_trace_br_fdb_add)(void *, struct ndmsg *, struct net_device *, const unsigned char *, u16, u16);\n\ntypedef void (*btf_trace_br_fdb_external_learn_add)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16);\n\ntypedef void (*btf_trace_br_fdb_update)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16, long unsigned int);\n\ntypedef void (*btf_trace_br_mdb_full)(void *, const struct net_device *, const struct br_ip *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_cache_entry_expired)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_make_negative)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_no_listener)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_upcall)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_update)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cap_capable)(void *, const struct cred *, struct user_namespace *, const struct user_namespace *, int, int);\n\ntypedef void (*btf_trace_cdev_update)(void *, struct thermal_cooling_device *, long unsigned int);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rstat_lock_contended)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_locked)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_unlock)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_ci_complete_td)(void *, struct ci_hw_ep *, struct ci_hw_req *, struct td_node *);\n\ntypedef void (*btf_trace_ci_log)(void *, struct ci_hdrc *, struct va_format *);\n\ntypedef void (*btf_trace_ci_prepare_td)(void *, struct ci_hw_ep *, struct ci_hw_req *, struct td_node *);\n\ntypedef void (*btf_trace_clk_disable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_disable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_enable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_enable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_rate_request_done)(void *, struct clk_rate_request *);\n\ntypedef void (*btf_trace_clk_rate_request_start)(void *, struct clk_rate_request *);\n\ntypedef void (*btf_trace_clk_set_duty_cycle)(void *, struct clk_core *, struct clk_duty *);\n\ntypedef void (*btf_trace_clk_set_duty_cycle_complete)(void *, struct clk_core *, struct clk_duty *);\n\ntypedef void (*btf_trace_clk_set_max_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_min_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_parent)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_parent_complete)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_phase)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_phase_complete)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_rate_complete)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_rate_range)(void *, struct clk_core *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_clk_unprepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_unprepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_cma_alloc_busy_retry)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_alloc_finish)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_cma_alloc_start)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_release)(void *, const char *, long unsigned int, const struct page *, long unsigned int);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_contention_begin)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_contention_end)(void *, void *, int);\n\ntypedef void (*btf_trace_count_memcg_events)(void *, struct mem_cgroup *, int, long unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_idle_miss)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_cros_ec_request_done)(void *, struct cros_ec_command *, int);\n\ntypedef void (*btf_trace_cros_ec_request_start)(void *, struct cros_ec_command *);\n\ntypedef void (*btf_trace_cros_ec_sensorhub_data)(void *, u32, u32, s64, s64, s64);\n\ntypedef void (*btf_trace_cros_ec_sensorhub_filter)(void *, struct cros_ec_sensors_ts_filter_state *, s64, s64);\n\ntypedef void (*btf_trace_cros_ec_sensorhub_timestamp)(void *, u32, u32, s64, s64, s64);\n\ntypedef void (*btf_trace_csd_function_entry)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_function_exit)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_queue_cpu)(void *, const unsigned int, long unsigned int, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_ctime_ns_xchg)(void *, struct inode *, u32, u32, u32);\n\ntypedef void (*btf_trace_ctime_xchg_skip)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_devfreq_frequency)(void *, struct devfreq *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_devfreq_monitor)(void *, struct devfreq *);\n\ntypedef void (*btf_trace_device_pm_callback_end)(void *, struct device *, int);\n\ntypedef void (*btf_trace_device_pm_callback_start)(void *, struct device *, const char *, int);\n\ntypedef void (*btf_trace_devlink_health_recover_aborted)(void *, const struct devlink *, const char *, bool, u64);\n\ntypedef void (*btf_trace_devlink_health_report)(void *, const struct devlink *, const char *, const char *);\n\ntypedef void (*btf_trace_devlink_health_reporter_state_update)(void *, const struct devlink *, const char *, bool);\n\ntypedef void (*btf_trace_devlink_hwerr)(void *, const struct devlink *, int, const char *);\n\ntypedef void (*btf_trace_devlink_hwmsg)(void *, const struct devlink *, bool, long unsigned int, const u8 *, size_t);\n\ntypedef void (*btf_trace_devlink_trap_report)(void *, const struct devlink *, struct sk_buff *, const struct devlink_trap_metadata *);\n\ntypedef void (*btf_trace_devres_log)(void *, struct device *, const char *, void *, const char *, size_t);\n\ntypedef void (*btf_trace_disk_zone_wplug_add_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_dma_alloc)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt_err)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_buf_detach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_dynamic_attach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_export)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_fd)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_get)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_mmap)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_mmap_internal)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_put)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_free)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_map_phys)(void *, struct device *, phys_addr_t, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg_err)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_sync_sg_for_cpu)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_sg_for_device)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_cpu)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_device)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_unmap_phys)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_unmap_sg)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dpaa2_eth_buf_seed)(void *, struct net_device *, void *, size_t, dma_addr_t, size_t, u16);\n\ntypedef void (*btf_trace_dpaa2_rx_fd)(void *, struct net_device *, const struct dpaa2_fd *);\n\ntypedef void (*btf_trace_dpaa2_rx_xsk_fd)(void *, struct net_device *, const struct dpaa2_fd *);\n\ntypedef void (*btf_trace_dpaa2_tx_conf_fd)(void *, struct net_device *, const struct dpaa2_fd *);\n\ntypedef void (*btf_trace_dpaa2_tx_fd)(void *, struct net_device *, const struct dpaa2_fd *);\n\ntypedef void (*btf_trace_dpaa2_tx_xsk_fd)(void *, struct net_device *, const struct dpaa2_fd *);\n\ntypedef void (*btf_trace_dpaa2_xsk_buf_seed)(void *, struct net_device *, void *, size_t, dma_addr_t, size_t, u16);\n\ntypedef void (*btf_trace_dpaa_rx_fd)(void *, struct net_device *, struct qman_fq *, const struct qm_fd *);\n\ntypedef void (*btf_trace_dpaa_tx_conf_fd)(void *, struct net_device *, struct qman_fq *, const struct qm_fd *);\n\ntypedef void (*btf_trace_dpaa_tx_fd)(void *, struct net_device *, struct qman_fq *, const struct qm_fd *);\n\ntypedef void (*btf_trace_dql_stall_detected)(void *, short unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_dwc3_alloc_request)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_complete_trb)(void *, struct dwc3_ep *, struct dwc3_trb *);\n\ntypedef void (*btf_trace_dwc3_ctrl_req)(void *, struct dwc3 *, struct usb_ctrlrequest *);\n\ntypedef void (*btf_trace_dwc3_ep_dequeue)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_ep_queue)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_event)(void *, u32, struct dwc3 *);\n\ntypedef void (*btf_trace_dwc3_free_request)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_gadget_ep_cmd)(void *, struct dwc3_ep *, unsigned int, struct dwc3_gadget_ep_cmd_params *, int);\n\ntypedef void (*btf_trace_dwc3_gadget_ep_disable)(void *, struct dwc3_ep *);\n\ntypedef void (*btf_trace_dwc3_gadget_ep_enable)(void *, struct dwc3_ep *);\n\ntypedef void (*btf_trace_dwc3_gadget_generic_cmd)(void *, struct dwc3 *, unsigned int, u32, int);\n\ntypedef void (*btf_trace_dwc3_gadget_giveback)(void *, struct dwc3_request *);\n\ntypedef void (*btf_trace_dwc3_prepare_trb)(void *, struct dwc3_ep *, struct dwc3_trb *);\n\ntypedef void (*btf_trace_dwc3_readl)(void *, struct dwc3 *, void *, u32, u32);\n\ntypedef void (*btf_trace_dwc3_set_prtcap)(void *, struct dwc3 *, u32);\n\ntypedef void (*btf_trace_dwc3_writel)(void *, struct dwc3 *, void *, u32, u32);\n\ntypedef void (*btf_trace_e1000e_trace_mac_register)(void *, uint32_t);\n\ntypedef void (*btf_trace_edma_fill_tcd)(void *, struct fsl_edma_chan *, void *);\n\ntypedef void (*btf_trace_edma_readb)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_readl)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_readw)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_writeb)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_writel)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_edma_writew)(void *, struct fsl_edma_engine *, void *, u32);\n\ntypedef void (*btf_trace_error_report_end)(void *, enum error_detector, long unsigned int);\n\ntypedef void (*btf_trace_exit_mmap)(void *, struct mm_struct *);\n\ntypedef void (*btf_trace_ext4_alloc_da_blocks)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_allocate_blocks)(void *, struct ext4_allocation_request *, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_allocate_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_begin_ordered_truncate)(void *, struct inode *, loff_t);\n\ntypedef void (*btf_trace_ext4_collapse_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_da_release_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_reserve_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_update_reserve_space)(void *, struct inode *, int, int);\n\ntypedef void (*btf_trace_ext4_da_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_end)(void *, struct inode *, loff_t, loff_t, struct writeback_control *, int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_start)(void *, struct inode *, loff_t, loff_t, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages_extent)(void *, struct inode *, struct ext4_map_blocks *);\n\ntypedef void (*btf_trace_ext4_discard_blocks)(void *, struct super_block *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_discard_preallocations)(void *, struct inode *, unsigned int);\n\ntypedef void (*btf_trace_ext4_drop_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_error)(void *, struct super_block *, const char *, unsigned int);\n\ntypedef void (*btf_trace_ext4_es_cache_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_exit)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_insert_delayed_extent)(void *, struct inode *, struct extent_status *, bool, bool);\n\ntypedef void (*btf_trace_ext4_es_insert_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_exit)(void *, struct inode *, struct extent_status *, int);\n\ntypedef void (*btf_trace_ext4_es_remove_extent)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_shrink)(void *, struct super_block *, int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_count)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_enter)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_exit)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_enter)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_fastpath)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_handle_unwritten_extents)(void *, struct inode *, struct ext4_map_blocks *, int, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_load_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space_done)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, struct partial_cluster *, __le16);\n\ntypedef void (*btf_trace_ext4_ext_rm_idx)(void *, struct inode *, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_rm_leaf)(void *, struct inode *, ext4_lblk_t, struct ext4_extent *, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_show_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t, short unsigned int);\n\ntypedef void (*btf_trace_ext4_fallocate_enter)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_fallocate_exit)(void *, struct inode *, loff_t, unsigned int, int);\n\ntypedef void (*btf_trace_ext4_fc_cleanup)(void *, journal_t *, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_start)(void *, struct super_block *, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_stop)(void *, struct super_block *, int, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_replay)(void *, struct super_block *, int, int, int, int);\n\ntypedef void (*btf_trace_ext4_fc_replay_scan)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_fc_stats)(void *, struct super_block *);\n\ntypedef void (*btf_trace_ext4_fc_track_create)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_inode)(void *, handle_t *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_link)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_range)(void *, handle_t *, struct inode *, long int, long int, int);\n\ntypedef void (*btf_trace_ext4_fc_track_unlink)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_forget)(void *, struct inode *, int, __u64);\n\ntypedef void (*btf_trace_ext4_free_blocks)(void *, struct inode *, __u64, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_fsmap_high_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_low_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_mapping)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_get_implied_cluster_alloc_exit)(void *, struct super_block *, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_getfsmap_high_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_low_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_mapping)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_insert_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journal_start_inode)(void *, struct inode *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_reserved)(void *, struct super_block *, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_sb)(void *, struct super_block *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journalled_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_lazy_itable_init)(void *, struct super_block *, ext4_group_t);\n\ntypedef void (*btf_trace_ext4_load_inode)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_load_inode_bitmap)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mark_inode_dirty)(void *, struct inode *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_buddy_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_discard_preallocations)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_mb_new_group_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_new_inode_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_group_pa)(void *, struct super_block *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_inode_pa)(void *, struct ext4_prealloc_space *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_mballoc_alloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_discard)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_free)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_prealloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_move_extent_enter)(void *, struct inode *, struct ext4_map_blocks *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_move_extent_exit)(void *, struct inode *, ext4_lblk_t, struct inode *, ext4_lblk_t, unsigned int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_nfs_commit_metadata)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_other_inode_update_time)(void *, struct inode *, ino_t);\n\ntypedef void (*btf_trace_ext4_prefetch_bitmaps)(void *, struct super_block *, ext4_group_t, ext4_group_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_punch_hole)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_read_block_bitmap_load)(void *, struct super_block *, long unsigned int, bool);\n\ntypedef void (*btf_trace_ext4_read_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_release_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_remove_blocks)(void *, struct inode *, struct ext4_extent *, ext4_lblk_t, ext4_fsblk_t, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_request_blocks)(void *, struct ext4_allocation_request *);\n\ntypedef void (*btf_trace_ext4_request_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_shutdown)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_sync_file_enter)(void *, struct file *, int);\n\ntypedef void (*btf_trace_ext4_sync_file_exit)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_sync_fs)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_trim_all_free)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_trim_extent)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_truncate_enter)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_truncate_exit)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_unlink_enter)(void *, struct inode *, struct dentry *);\n\ntypedef void (*btf_trace_ext4_unlink_exit)(void *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_update_sb)(void *, struct super_block *, ext4_fsblk_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_writepages)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_writepages_result)(void *, struct inode *, struct writeback_control *, int, int);\n\ntypedef void (*btf_trace_ext4_zero_range)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_fdb_delete)(void *, struct net_bridge *, struct net_bridge_fdb_entry *);\n\ntypedef void (*btf_trace_ff_layout_commit_error)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_ff_layout_read_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_ff_layout_write_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_fill_mg_cmtime)(void *, struct inode *, struct timespec64 *, struct timespec64 *);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_fl_getdevinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, char *);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_flush_foreign)(void *, struct bdi_writeback *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_folio_wait_writeback)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_free_vmap_area_noflush)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_gpio_direction)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_gpio_value)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_gpu_mem_total)(void *, uint32_t, uint32_t, uint64_t);\n\ntypedef void (*btf_trace_guest_halt_poll_ns)(void *, bool, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_handshake_cancel)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_busy)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_none)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cmd_accept)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_accept_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_complete)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_destruct)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_notify_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_submit)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_submit_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_hclge_pf_cmd_get)(void *, struct hclge_comm_hw *, struct hclge_desc *, int, int);\n\ntypedef void (*btf_trace_hclge_pf_cmd_send)(void *, struct hclge_comm_hw *, struct hclge_desc *, int, int);\n\ntypedef void (*btf_trace_hclge_pf_mbx_get)(void *, struct hclge_dev *, struct hclge_mbx_vf_to_pf_cmd *);\n\ntypedef void (*btf_trace_hclge_pf_mbx_send)(void *, struct hclge_dev *, struct hclge_mbx_pf_to_vf_cmd *);\n\ntypedef void (*btf_trace_hclge_pf_special_cmd_get)(void *, struct hclge_comm_hw *, __le32 *, int, int);\n\ntypedef void (*btf_trace_hclge_pf_special_cmd_send)(void *, struct hclge_comm_hw *, __le32 *, int, int);\n\ntypedef void (*btf_trace_hns3_gro)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_hns3_over_max_bd)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_hns3_rx_desc)(void *, struct hns3_enet_ring *);\n\ntypedef void (*btf_trace_hns3_tso)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_hns3_tx_desc)(void *, struct hns3_enet_ring *, int);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_setup)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hugetlbfs_alloc_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_hugetlbfs_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_fallocate)(void *, struct inode *, int, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_hugetlbfs_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_setattr)(void *, struct inode *, struct dentry *, struct iattr *);\n\ntypedef void (*btf_trace_hw_pressure_update)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_hwmon_attr_show)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_hwmon_attr_show_string)(void *, int, const char *, const char *);\n\ntypedef void (*btf_trace_hwmon_attr_store)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_i2c_read)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_reply)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_result)(void *, const struct i2c_adapter *, int, int);\n\ntypedef void (*btf_trace_i2c_slave)(void *, const struct i2c_client *, enum i2c_slave_event, __u8 *, int);\n\ntypedef void (*btf_trace_i2c_write)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_icc_set_bw)(void *, struct icc_path *, struct icc_node *, int, u32, u32);\n\ntypedef void (*btf_trace_icc_set_bw_end)(void *, struct icc_path *, int);\n\ntypedef void (*btf_trace_icmp_send)(void *, const struct sk_buff *, int, int);\n\ntypedef void (*btf_trace_inet_sk_error_report)(void *, const struct sock *);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_inode_foreign_history)(void *, struct inode *, struct writeback_control *, unsigned int);\n\ntypedef void (*btf_trace_inode_set_ctime_to_ts)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_inode_switch_wbs)(void *, struct inode *, struct bdi_writeback *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_inode_switch_wbs_queue)(void *, struct bdi_writeback *, struct bdi_writeback *, unsigned int);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, struct io_ring_ctx *, void *, struct io_uring_cqe *);\n\ntypedef void (*btf_trace_io_uring_cqe_overflow)(void *, void *, long long unsigned int, s32, u32, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_local_work_run)(void *, void *, int, unsigned int);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, struct io_kiocb *, int, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, struct io_kiocb *, bool);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, long int);\n\ntypedef void (*btf_trace_io_uring_req_failed)(void *, const struct io_uring_sqe *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_short_write)(void *, void *, u64, u64, u64);\n\ntypedef void (*btf_trace_io_uring_submit_req)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_task_work_run)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_iomap_add_to_ioend)(void *, struct inode *, u64, unsigned int, struct iomap *);\n\ntypedef void (*btf_trace_iomap_dio_complete)(void *, struct kiocb *, int, ssize_t);\n\ntypedef void (*btf_trace_iomap_dio_invalidate_fail)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_dio_rw_begin)(void *, struct kiocb *, struct iov_iter *, unsigned int, size_t);\n\ntypedef void (*btf_trace_iomap_dio_rw_queued)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_invalidate_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_iter)(void *, struct iomap_iter *, const void *, long unsigned int);\n\ntypedef void (*btf_trace_iomap_iter_dstmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_iter_srcmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_release_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_writeback_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_zero_iter)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_ipi_entry)(void *, const char *);\n\ntypedef void (*btf_trace_ipi_exit)(void *, const char *);\n\ntypedef void (*btf_trace_ipi_raise)(void *, const struct cpumask *, const char *);\n\ntypedef void (*btf_trace_ipi_send_cpu)(void *, const unsigned int, long unsigned int, void *);\n\ntypedef void (*btf_trace_ipi_send_cpumask)(void *, const struct cpumask *, long unsigned int, void *);\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_jbd2_checkpoint)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_checkpoint_stats)(void *, dev_t, tid_t, struct transaction_chp_stats_s *);\n\ntypedef void (*btf_trace_jbd2_commit_flushing)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_locking)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_logging)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_drop_transaction)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_end_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_handle_extend)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int);\n\ntypedef void (*btf_trace_jbd2_handle_restart)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_start)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_stats)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int, int, int);\n\ntypedef void (*btf_trace_jbd2_lock_buffer_stall)(void *, dev_t, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_run_stats)(void *, dev_t, tid_t, struct transaction_run_stats_s *);\n\ntypedef void (*btf_trace_jbd2_shrink_checkpoint_list)(void *, journal_t *, tid_t, tid_t, tid_t, long unsigned int, tid_t);\n\ntypedef void (*btf_trace_jbd2_shrink_count)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_enter)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_exit)(void *, journal_t *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_start_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_submit_inode_data)(void *, struct inode *);\n\ntypedef void (*btf_trace_jbd2_update_log_tail)(void *, journal_t *, tid_t, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_write_superblock)(void *, journal_t *, blk_opf_t);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *, enum skb_drop_reason, struct sock *);\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, struct kmem_cache *, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *, const struct kmem_cache *);\n\ntypedef void (*btf_trace_ksm_advisor)(void *, s64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ksm_enter)(void *, void *);\n\ntypedef void (*btf_trace_ksm_exit)(void *, void *);\n\ntypedef void (*btf_trace_ksm_merge_one_page)(void *, long unsigned int, void *, void *, int);\n\ntypedef void (*btf_trace_ksm_merge_with_ksm_page)(void *, void *, long unsigned int, void *, void *, int);\n\ntypedef void (*btf_trace_ksm_remove_ksm_page)(void *, long unsigned int);\n\ntypedef void (*btf_trace_ksm_remove_rmap_item)(void *, long unsigned int, void *, void *);\n\ntypedef void (*btf_trace_ksm_start_scan)(void *, int, u32);\n\ntypedef void (*btf_trace_ksm_stop_scan)(void *, int, u32);\n\ntypedef void (*btf_trace_kvm_access_fault)(void *, long unsigned int);\n\ntypedef void (*btf_trace_kvm_ack_irq)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_age_hva)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_arm_set_dreg32)(void *, const char *, __u64);\n\ntypedef void (*btf_trace_kvm_dirty_ring_exit)(void *, struct kvm_vcpu *);\n\ntypedef void (*btf_trace_kvm_dirty_ring_push)(void *, struct kvm_dirty_ring *, u32, u64);\n\ntypedef void (*btf_trace_kvm_dirty_ring_reset)(void *, struct kvm_dirty_ring *);\n\ntypedef void (*btf_trace_kvm_entry)(void *, long unsigned int);\n\ntypedef void (*btf_trace_kvm_exit)(void *, int, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_forward_sysreg_trap)(void *, struct kvm_vcpu *, u32, bool);\n\ntypedef void (*btf_trace_kvm_fpu)(void *, int);\n\ntypedef void (*btf_trace_kvm_get_timer_map)(void *, long unsigned int, struct timer_map *);\n\ntypedef void (*btf_trace_kvm_guest_fault)(void *, long unsigned int, long unsigned int, long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_kvm_halt_poll_ns)(void *, bool, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kvm_handle_sys_reg)(void *, long unsigned int);\n\ntypedef void (*btf_trace_kvm_hvc_arm64)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_inject_nested_exception)(void *, struct kvm_vcpu *, u64, int);\n\ntypedef void (*btf_trace_kvm_irq_line)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_kvm_mmio)(void *, int, int, u64, void *);\n\ntypedef void (*btf_trace_kvm_mmio_emulate)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_mmio_nisv)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_nested_eret)(void *, struct kvm_vcpu *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_set_guest_debug)(void *, struct kvm_vcpu *, __u32);\n\ntypedef void (*btf_trace_kvm_set_irq)(void *, unsigned int, int, int);\n\ntypedef void (*btf_trace_kvm_set_way_flush)(void *, long unsigned int, bool);\n\ntypedef void (*btf_trace_kvm_sys_access)(void *, long unsigned int, struct sys_reg_params *, const struct sys_reg_desc *);\n\ntypedef void (*btf_trace_kvm_test_age_hva)(void *, long unsigned int);\n\ntypedef void (*btf_trace_kvm_timer_emulate)(void *, struct arch_timer_context *, bool);\n\ntypedef void (*btf_trace_kvm_timer_hrtimer_expire)(void *, struct arch_timer_context *);\n\ntypedef void (*btf_trace_kvm_timer_restore_state)(void *, struct arch_timer_context *);\n\ntypedef void (*btf_trace_kvm_timer_save_state)(void *, struct arch_timer_context *);\n\ntypedef void (*btf_trace_kvm_timer_update_irq)(void *, long unsigned int, __u32, int);\n\ntypedef void (*btf_trace_kvm_toggle_cache)(void *, long unsigned int, bool, bool);\n\ntypedef void (*btf_trace_kvm_unmap_hva_range)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_kvm_userspace_exit)(void *, __u32, int);\n\ntypedef void (*btf_trace_kvm_vcpu_wakeup)(void *, __u64, bool, bool);\n\ntypedef void (*btf_trace_kvm_wfx_arm64)(void *, long unsigned int, bool);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, dev_t, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_latency)(void *, dev_t, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, dev_t, const char *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lease *, struct file_lease *);\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ma_op)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_read)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_write)(void *, const char *, struct ma_state *, long unsigned int, void *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_mark_victim)(void *, struct task_struct *, uid_t);\n\ntypedef void (*btf_trace_mc_event)(void *, const unsigned int, const char *, const char *, const int, const u8, const s8, const s8, const s8, long unsigned int, const u8, long unsigned int, const char *);\n\ntypedef void (*btf_trace_mdio_access)(void *, struct mii_bus *, char, u8, unsigned int, u16, int);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_memcg_flush_stats)(void *, struct mem_cgroup *, s64, bool, bool);\n\ntypedef void (*btf_trace_memory_failure_event)(void *, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_calculate_totalreserve_pages)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page)(void *, struct mm_struct *, int, int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page_isolate)(void *, struct folio *, int, int, int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page_swapin)(void *, struct mm_struct *, int, int, int);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, struct compact_control *, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, struct compact_control *, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_fast_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_fault)(void *, struct address_space *, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_get_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_map_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_khugepaged_collapse_file)(void *, struct mm_struct *, struct folio *, long unsigned int, long unsigned int, bool, struct file *, int, int);\n\ntypedef void (*btf_trace_mm_khugepaged_scan_file)(void *, struct mm_struct *, struct folio *, struct file *, int, int, int);\n\ntypedef void (*btf_trace_mm_khugepaged_scan_pmd)(void *, struct mm_struct *, struct folio *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_migrate_pages_start)(void *, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_lowmem_reserve)(void *, struct zone *, struct zone *, long int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_wmarks)(void *, struct zone *);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_clear_hopeless)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_reclaim_fail)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_reclaim_pages)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *);\n\ntypedef void (*btf_trace_mm_vmscan_throttled)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_write_folio)(void *, struct folio *);\n\ntypedef void (*btf_trace_mmap_lock_acquire_returned)(void *, struct mm_struct *, bool, bool);\n\ntypedef void (*btf_trace_mmap_lock_released)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmap_lock_start_locking)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmc_request_done)(void *, struct mmc_host *, struct mmc_request *);\n\ntypedef void (*btf_trace_mmc_request_start)(void *, struct mmc_host *, struct mmc_request *);\n\ntypedef void (*btf_trace_mod_memcg_lruvec_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_mod_memcg_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_mtu3_alloc_request)(void *, struct mtu3_request *);\n\ntypedef void (*btf_trace_mtu3_complete_gpd)(void *, struct mtu3_ep *, struct qmu_gpd *);\n\ntypedef void (*btf_trace_mtu3_free_request)(void *, struct mtu3_request *);\n\ntypedef void (*btf_trace_mtu3_gadget_dequeue)(void *, struct mtu3_request *);\n\ntypedef void (*btf_trace_mtu3_gadget_ep_disable)(void *, struct mtu3_ep *);\n\ntypedef void (*btf_trace_mtu3_gadget_ep_enable)(void *, struct mtu3_ep *);\n\ntypedef void (*btf_trace_mtu3_gadget_ep_set_halt)(void *, struct mtu3_ep *);\n\ntypedef void (*btf_trace_mtu3_gadget_queue)(void *, struct mtu3_request *);\n\ntypedef void (*btf_trace_mtu3_handle_setup)(void *, struct usb_ctrlrequest *);\n\ntypedef void (*btf_trace_mtu3_log)(void *, struct device *, struct va_format *);\n\ntypedef void (*btf_trace_mtu3_prepare_gpd)(void *, struct mtu3_ep *, struct qmu_gpd *);\n\ntypedef void (*btf_trace_mtu3_qmu_isr)(void *, u32, u32);\n\ntypedef void (*btf_trace_mtu3_req_complete)(void *, struct mtu3_request *);\n\ntypedef void (*btf_trace_mtu3_u2_common_isr)(void *, u32);\n\ntypedef void (*btf_trace_mtu3_u3_ltssm_isr)(void *, u32);\n\ntypedef void (*btf_trace_mtu3_zlp_exp_gpd)(void *, struct mtu3_ep *, struct qmu_gpd *);\n\ntypedef void (*btf_trace_musb_isr)(void *, struct musb *);\n\ntypedef void (*btf_trace_musb_log)(void *, struct musb *, struct va_format *);\n\ntypedef void (*btf_trace_musb_readb)(void *, void *, const void *, unsigned int, u8);\n\ntypedef void (*btf_trace_musb_readl)(void *, void *, const void *, unsigned int, u32);\n\ntypedef void (*btf_trace_musb_readw)(void *, void *, const void *, unsigned int, u16);\n\ntypedef void (*btf_trace_musb_req_alloc)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_req_deq)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_req_enq)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_req_free)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_req_gb)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_req_rx)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_req_start)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_req_tx)(void *, struct musb_request *);\n\ntypedef void (*btf_trace_musb_state)(void *, struct musb *, u8, const char *);\n\ntypedef void (*btf_trace_musb_urb_deq)(void *, struct musb *, struct urb *);\n\ntypedef void (*btf_trace_musb_urb_enq)(void *, struct musb *, struct urb *);\n\ntypedef void (*btf_trace_musb_urb_gb)(void *, struct musb *, struct urb *);\n\ntypedef void (*btf_trace_musb_urb_rx)(void *, struct musb *, struct urb *);\n\ntypedef void (*btf_trace_musb_urb_start)(void *, struct musb *, struct urb *);\n\ntypedef void (*btf_trace_musb_urb_tx)(void *, struct musb *, struct urb *);\n\ntypedef void (*btf_trace_musb_writeb)(void *, void *, const void *, unsigned int, u8);\n\ntypedef void (*btf_trace_musb_writel)(void *, void *, const void *, unsigned int, u32);\n\ntypedef void (*btf_trace_musb_writew)(void *, void *, const void *, unsigned int, u16);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_netfs_collect)(void *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_collect_folio)(void *, const struct netfs_io_request *, const struct folio *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_gap)(void *, const struct netfs_io_request *, const struct netfs_io_stream *, long long unsigned int, char);\n\ntypedef void (*btf_trace_netfs_collect_sreq)(void *, const struct netfs_io_request *, const struct netfs_io_subrequest *);\n\ntypedef void (*btf_trace_netfs_collect_state)(void *, const struct netfs_io_request *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_netfs_collect_stream)(void *, const struct netfs_io_request *, const struct netfs_io_stream *);\n\ntypedef void (*btf_trace_netfs_copy2cache)(void *, const struct netfs_io_request *, const struct netfs_io_request *);\n\ntypedef void (*btf_trace_netfs_failure)(void *, struct netfs_io_request *, struct netfs_io_subrequest *, int, enum netfs_failure);\n\ntypedef void (*btf_trace_netfs_folio)(void *, struct folio *, enum netfs_folio_trace);\n\ntypedef void (*btf_trace_netfs_folioq)(void *, const struct folio_queue *, enum netfs_folioq_trace);\n\ntypedef void (*btf_trace_netfs_read)(void *, struct netfs_io_request *, loff_t, size_t, enum netfs_read_trace);\n\ntypedef void (*btf_trace_netfs_rreq)(void *, struct netfs_io_request *, enum netfs_rreq_trace);\n\ntypedef void (*btf_trace_netfs_rreq_ref)(void *, unsigned int, int, enum netfs_rreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_sreq)(void *, struct netfs_io_subrequest *, enum netfs_sreq_trace);\n\ntypedef void (*btf_trace_netfs_sreq_ref)(void *, unsigned int, unsigned int, int, enum netfs_sreq_ref_trace);\n\ntypedef void (*btf_trace_netfs_write)(void *, const struct netfs_io_request *, enum netfs_write_trace);\n\ntypedef void (*btf_trace_netfs_write_iter)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netlink_extack)(void *, const char *);\n\ntypedef void (*btf_trace_nfs41_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_access)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_bind_conn_to_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_cached_open)(void *, const struct nfs4_state *);\n\ntypedef void (*btf_trace_nfs4_cb_getattr)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_cb_layoutrecall_file)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_offload)(void *, const struct nfs_fh *, const nfs4_stateid *, uint64_t, int, int);\n\ntypedef void (*btf_trace_nfs4_cb_recall)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_seqid_err)(void *, const struct cb_sequenceargs *, __be32);\n\ntypedef void (*btf_trace_nfs4_cb_sequence)(void *, const struct cb_sequenceargs *, const struct cb_sequenceres *, __be32);\n\ntypedef void (*btf_trace_nfs4_clone)(void *, const struct inode *, const struct inode *, const struct nfs42_clone_args *, int);\n\ntypedef void (*btf_trace_nfs4_close)(void *, const struct nfs4_state *, const struct nfs_closeargs *, const struct nfs_closeres *, int);\n\ntypedef void (*btf_trace_nfs4_close_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_commit)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_copy)(void *, const struct inode *, const struct inode *, const struct nfs42_copy_args *, const struct nfs42_copy_res *, const struct nl4_server *, int);\n\ntypedef void (*btf_trace_nfs4_copy_notify)(void *, const struct inode *, const struct nfs42_copy_notify_args *, const struct nfs42_copy_notify_res *, int);\n\ntypedef void (*btf_trace_nfs4_create_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_deallocate)(void *, const struct inode *, const struct nfs42_falloc_args *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn_exit)(void *, const struct nfs4_delegreturnargs *, const struct nfs4_delegreturnres *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_clientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_detach_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_deviceid_free)(void *, const struct nfs_client *, const struct nfs4_deviceid *);\n\ntypedef void (*btf_trace_nfs4_exchange_id)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_fallocate)(void *, const struct inode *, const struct nfs42_falloc_args *, int);\n\ntypedef void (*btf_trace_nfs4_find_deviceid)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_fsinfo)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_get_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_get_fs_locations)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_get_lock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_get_security_label)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_getattr)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_getdeviceinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_getxattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_layoutcommit)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layouterror)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutget)(void *, const struct nfs_open_context *, const struct pnfs_layout_range *, const struct pnfs_layout_range *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn_on_close)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutstats)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_listxattr)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_llseek)(void *, const struct inode *, const struct nfs42_seek_args *, const struct nfs42_seek_res *, int);\n\ntypedef void (*btf_trace_nfs4_lookup)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_lookup_root)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_lookupp)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_map_gid_to_group)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_group_to_gid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_name_to_uid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_uid_to_name)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_mkdir)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_mknod)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_offload_cancel)(void *, const struct nfs42_offload_status_args *, int);\n\ntypedef void (*btf_trace_nfs4_offload_status)(void *, const struct nfs42_offload_status_args *, int);\n\ntypedef void (*btf_trace_nfs4_open_expired)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_file)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_reclaim)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_skip)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_commit_ds)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_readdir)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_readlink)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_complete)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_remove)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_removexattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_rename)(void *, const struct inode *, const struct qstr *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_renew)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_renew_async)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_secinfo)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_sequence)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_sequence_done)(void *, const struct nfs4_session *, const struct nfs4_sequence_res *);\n\ntypedef void (*btf_trace_nfs4_set_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_set_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_set_lock)(void *, const struct file_lock *, const struct nfs4_state *, const nfs4_stateid *, int, int);\n\ntypedef void (*btf_trace_nfs4_set_security_label)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_setattr)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid_confirm)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setup_sequence)(void *, const struct nfs4_session *, const struct nfs4_sequence_args *);\n\ntypedef void (*btf_trace_nfs4_setxattr)(void *, const struct inode *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_state_lock_reclaim)(void *, const struct nfs4_state *, const struct nfs4_lock_state *);\n\ntypedef void (*btf_trace_nfs4_state_mgr)(void *, const struct nfs_client *);\n\ntypedef void (*btf_trace_nfs4_state_mgr_failed)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_symlink)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_test_delegation_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_lock_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_open_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_trunked_exchange_id)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_unlock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_filehandle)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_operation)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_status)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs_access_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_access_exit)(void *, const struct inode *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readahead)(void *, const struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_nfs_aop_readahead_done)(void *, const struct inode *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readpage)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_aop_readpage_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_async_rename_done)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_atomic_open_enter)(void *, const struct inode *, const struct nfs_open_context *, unsigned int);\n\ntypedef void (*btf_trace_nfs_atomic_open_exit)(void *, const struct inode *, const struct nfs_open_context *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_cb_badprinc)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_cb_no_clp)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_commit_done)(void *, const struct rpc_task *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_commit_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_comp_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_create_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_create_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_delegation_need_return)(void *, const struct nfs_delegation *);\n\ntypedef void (*btf_trace_nfs_direct_commit_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_resched_write)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_completion)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_reschedule_io)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_schedule_iovec)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_do_writepage)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_fh_to_dentry)(void *, const struct super_block *, const struct nfs_fh *, u64, int);\n\ntypedef void (*btf_trace_nfs_file_read)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_file_write)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_fsync_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_fsync_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_getattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_getattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_initiate_commit)(void *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_initiate_read)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_initiate_write)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_invalidate_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_launder_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_link_enter)(void *, const struct inode *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_link_exit)(void *, const struct inode *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_local_open_fh)(void *, const struct nfs_fh *, fmode_t, int);\n\ntypedef void (*btf_trace_nfs_lookup_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_mkdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mkdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mknod_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mknod_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mount_assign)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_nfs_mount_option)(void *, const struct fs_parameter *);\n\ntypedef void (*btf_trace_nfs_mount_path)(void *, const char *);\n\ntypedef void (*btf_trace_nfs_pgio_error)(void *, const struct nfs_pgio_header *, int, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readdir_force_readdirplus)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_readdir_invalidate_cache_range)(void *, const struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_lookup)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate_failed)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readpage_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_readpage_short)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_remove_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_remove_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_rename_enter)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rename_exit)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_rmdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rmdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_set_cache_invalid)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_set_inode_stale)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_sillyrename_unlink)(void *, const struct nfs_unlinkdata *, int);\n\ntypedef void (*btf_trace_nfs_size_grow)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate_folio)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_update)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_wcc)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_symlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_symlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_try_to_update_request)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_try_to_update_request_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_unlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_unlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_update_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_update_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_begin)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_begin_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_end)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_end_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_writeback_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_writeback_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_writeback_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_writepage_setup)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_writepages)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writepages_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_xdr_bad_filehandle)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nfs_xdr_status)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nlmclnt_grant)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_lock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_test)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_unlock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_non_standard_event)(void *, const guid_t *, const guid_t *, const char *, const u8, const u8 *, const u32);\n\ntypedef void (*btf_trace_notifier_register)(void *, void *);\n\ntypedef void (*btf_trace_notifier_run)(void *, void *);\n\ntypedef void (*btf_trace_notifier_unregister)(void *, void *);\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_optee_invoke_fn_begin)(void *, struct optee_rpc_param *);\n\ntypedef void (*btf_trace_optee_invoke_fn_end)(void *, struct optee_rpc_param *, struct arm_smccc_res *);\n\ntypedef void (*btf_trace_page_cache_async_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_ra_order)(void *, struct inode *, long unsigned int, struct file_ra_state *);\n\ntypedef void (*btf_trace_page_cache_ra_unbounded)(void *, struct inode *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_sync_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_pool_release)(void *, const struct page_pool *, s32, u32, u32);\n\ntypedef void (*btf_trace_page_pool_state_hold)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_state_release)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_update_nid)(void *, const struct page_pool *, int);\n\ntypedef void (*btf_trace_pci_hp_event)(void *, const char *, const char *, const int);\n\ntypedef void (*btf_trace_pcie_link_event)(void *, struct pci_bus *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pelt_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_pelt_dl_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_hw_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_irq_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_rt_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, long unsigned int, bool, bool, size_t, size_t, void *, int, void *, size_t, gfp_t);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pmap_register)(void *, u32, u32, int, short unsigned int);\n\ntypedef void (*btf_trace_pnfs_ds_connect)(void *, char *, int);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_get_mirror_count)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_read)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_write)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_update_layout)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *, enum pnfs_update_layout_reason);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_psci_domain_idle_enter)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_psci_domain_idle_exit)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_purge_vmap_area_lazy)(void *, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pwm_apply)(void *, struct pwm_device *, const struct pwm_state *, int);\n\ntypedef void (*btf_trace_pwm_get)(void *, struct pwm_device *, const struct pwm_state *, int);\n\ntypedef void (*btf_trace_pwm_read_waveform)(void *, struct pwm_device *, void *, int);\n\ntypedef void (*btf_trace_pwm_round_waveform_fromhw)(void *, struct pwm_device *, const void *, struct pwm_waveform *, int);\n\ntypedef void (*btf_trace_pwm_round_waveform_tohw)(void *, struct pwm_device *, const struct pwm_waveform *, void *, int);\n\ntypedef void (*btf_trace_pwm_write_waveform)(void *, struct pwm_device *, const void *, int);\n\ntypedef void (*btf_trace_qcom_glink_cmd_close)(void *, const char *, const char *, u16, u16, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_close_ack)(void *, const char *, const char *, u16, u16, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_intent)(void *, const char *, const char *, u16, u16, size_t, size_t, u32, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_open)(void *, const char *, const char *, u16, u16, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_open_ack)(void *, const char *, const char *, u16, u16, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_read_notif)(void *, const char *, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_rx_done)(void *, const char *, const char *, u16, u16, u32, bool, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_rx_intent_req)(void *, const char *, const char *, u16, u16, size_t, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_rx_intent_req_ack)(void *, const char *, const char *, u16, u16, bool, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_signal)(void *, const char *, const char *, u16, u16, unsigned int, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_tx_data)(void *, const char *, const char *, u16, u16, u32, u32, u32, bool, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_version)(void *, const char *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_qcom_glink_cmd_version_ack)(void *, const char *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_enqueue)(void *, struct Qdisc *, const struct netdev_queue *, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_invoke_kvfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_segcb_stats)(void *, struct rcu_segcblist *, const char *);\n\ntypedef void (*btf_trace_rcu_sr_normal)(void *, const char *, struct callback_head *, const char *);\n\ntypedef void (*btf_trace_rcu_stall_warning)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_watching)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_regcache_drop_region)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regcache_sync)(void *, struct regmap *, const char *, const char *);\n\ntypedef void (*btf_trace_regmap_async_complete_done)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_start)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_io_complete)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_bulk_read)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_bulk_write)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_cache_bypass)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_cache_only)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_hw_read_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_read_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_reg_read)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read_cache)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_write)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regulator_bypass_disable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_disable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_enable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_bypass_enable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_disable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_disable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable_complete)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_enable_delay)(void *, const char *);\n\ntypedef void (*btf_trace_regulator_set_voltage)(void *, const char *, int, int);\n\ntypedef void (*btf_trace_regulator_set_voltage_complete)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_migration_pmd)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_remove_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_rpc__auth_tooweak)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__bad_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__garbage_args)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__proc_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__stale_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__unparsable)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_callhdr)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_verifier)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_buf_alloc)(void *, const struct rpc_task *, int);\n\ntypedef void (*btf_trace_rpc_call_rpcerror)(void *, const struct rpc_task *, int, int);\n\ntypedef void (*btf_trace_rpc_call_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_clnt_clone_err)(void *, const struct rpc_clnt *, int);\n\ntypedef void (*btf_trace_rpc_clnt_free)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_killall)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_new)(void *, const struct rpc_clnt *, const struct rpc_xprt *, const struct rpc_create_args *);\n\ntypedef void (*btf_trace_rpc_clnt_new_err)(void *, const char *, const char *, int);\n\ntypedef void (*btf_trace_rpc_clnt_release)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt_err)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_shutdown)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_connect_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_request)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_retry_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_socket_close)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_connect)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_error)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_nospace)(void *, const struct rpc_rqst *, const struct sock_xprt *);\n\ntypedef void (*btf_trace_rpc_socket_reset_connection)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_shutdown)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_state_change)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_stats_latency)(void *, const struct rpc_task *, ktime_t, ktime_t, ktime_t);\n\ntypedef void (*btf_trace_rpc_task_begin)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_call_done)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_complete)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_end)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_run_action)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_signalled)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sleep)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_task_sync_sleep)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sync_wake)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_timeout)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_wakeup)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_timeout_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_tls_not_started)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_tls_unavailable)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_xdr_alignment)(void *, const struct xdr_stream *, size_t, unsigned int);\n\ntypedef void (*btf_trace_rpc_xdr_overflow)(void *, const struct xdr_stream *, size_t);\n\ntypedef void (*btf_trace_rpc_xdr_recvfrom)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_reply_pages)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_sendto)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpcb_bind_version_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_getport)(void *, const struct rpc_clnt *, const struct rpc_task *, unsigned int);\n\ntypedef void (*btf_trace_rpcb_prog_unavail_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_register)(void *, u32, u32, const char *, const char *);\n\ntypedef void (*btf_trace_rpcb_setport)(void *, const struct rpc_task *, int, short unsigned int);\n\ntypedef void (*btf_trace_rpcb_timeout_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unreachable_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unrecognized_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unregister)(void *, u32, u32, const char *);\n\ntypedef void (*btf_trace_rpcgss_bad_seqno)(void *, const struct rpc_task *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_context)(void *, u32, long unsigned int, long unsigned int, unsigned int, unsigned int, const u8 *);\n\ntypedef void (*btf_trace_rpcgss_createauth)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rpcgss_ctx_destroy)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_ctx_init)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_get_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_import_ctx)(void *, int);\n\ntypedef void (*btf_trace_rpcgss_need_reencode)(void *, const struct rpc_task *, u32, bool);\n\ntypedef void (*btf_trace_rpcgss_oid_to_mech)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_seqno)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_svc_accept_upcall)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_authenticate)(void *, const struct svc_rqst *, const struct rpc_gss_wire_cred *);\n\ntypedef void (*btf_trace_rpcgss_svc_get_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_bad)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_large)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_low)(void *, const struct svc_rqst *, u32, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_seen)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_unwrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_unwrap_failed)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_upcall_msg)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_upcall_result)(void *, u32, int);\n\ntypedef void (*btf_trace_rpcgss_update_slack)(void *, const struct rpc_task *, const struct rpc_auth *);\n\ntypedef void (*btf_trace_rpcgss_verify_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_wrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpm_idle)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_resume)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_return_int)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_rpm_status)(void *, struct device *, enum rpm_status);\n\ntypedef void (*btf_trace_rpm_suspend)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_usage)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpmh_send_msg)(void *, struct rsc_drv *, int, enum rpmh_state, int, u32, const struct tcs_cmd *);\n\ntypedef void (*btf_trace_rpmh_tx_done)(void *, struct rsc_drv *, int, const struct tcs_request *);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int);\n\ntypedef void (*btf_trace_rtc_alarm_irq_enable)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_freq)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_state)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_read_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_read_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_set_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_timer_dequeue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_enqueue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_fired)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sched_compute_energy_tp)(void *, struct task_struct *, int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_sched_cpu_capacity_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_sched_entry_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_exit_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_ext_bypass_lb)(void *, __u32, __u32, __u32, __u32, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_sched_ext_dump)(void *, const char *);\n\ntypedef void (*btf_trace_sched_ext_event)(void *, const char *, __s64);\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_end)(void *, struct kthread_work *, kthread_work_func_t);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_start)(void *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_kthread_work_queue_work)(void *, struct kthread_worker *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_move_numa)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_overutilized_tp)(void *, struct root_domain *, bool);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_prepare_exec)(void *, struct task_struct *, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_set_need_resched_tp)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_skip_cpuset_numa)(void *, struct task_struct *, nodemask_t *);\n\ntypedef void (*btf_trace_sched_skip_vma_numa)(void *, struct mm_struct *, struct vm_area_struct *, enum numa_vmaskip_reason);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stick_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_swap_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *, unsigned int);\n\ntypedef void (*btf_trace_sched_update_nr_running_tp)(void *, struct rq *, int);\n\ntypedef void (*btf_trace_sched_util_est_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_sched_util_est_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_scmi_fc_call)(void *, u8, u8, u32, u32, u32);\n\ntypedef void (*btf_trace_scmi_msg_dump)(void *, int, u8, u8, u8, unsigned char *, u16, int, void *, size_t);\n\ntypedef void (*btf_trace_scmi_rx_done)(void *, int, u8, u8, u16, u8);\n\ntypedef void (*btf_trace_scmi_xfer_begin)(void *, int, u8, u8, u16, bool, int);\n\ntypedef void (*btf_trace_scmi_xfer_end)(void *, int, u8, u8, u16, int, int);\n\ntypedef void (*btf_trace_scmi_xfer_response_wait)(void *, int, u8, u8, u16, u32, bool);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\ntypedef void (*btf_trace_set_migration_pmd)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_set_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sk_data_ready)(void *, const struct sock *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_smbus_read)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int);\n\ntypedef void (*btf_trace_smbus_reply)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *, int);\n\ntypedef void (*btf_trace_smbus_result)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, int);\n\ntypedef void (*btf_trace_smbus_write)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *);\n\ntypedef void (*btf_trace_smp2p_negotiate)(void *, const struct device *, unsigned int);\n\ntypedef void (*btf_trace_smp2p_notify_in)(void *, struct smp2p_entry *, long unsigned int, u32);\n\ntypedef void (*btf_trace_smp2p_ssr_ack)(void *, const struct device *);\n\ntypedef void (*btf_trace_smp2p_update_bits)(void *, struct smp2p_entry *, u32, u32);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_recv_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_sock_send_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\ntypedef void (*btf_trace_spi_controller_busy)(void *, struct spi_controller *);\n\ntypedef void (*btf_trace_spi_controller_idle)(void *, struct spi_controller *);\n\ntypedef void (*btf_trace_spi_mem_start_op)(void *, struct spi_mem *, const struct spi_mem_op *);\n\ntypedef void (*btf_trace_spi_mem_stop_op)(void *, struct spi_mem *, const struct spi_mem_op *);\n\ntypedef void (*btf_trace_spi_message_done)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_message_start)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_message_submit)(void *, struct spi_message *);\n\ntypedef void (*btf_trace_spi_set_cs)(void *, struct spi_device *, bool);\n\ntypedef void (*btf_trace_spi_setup)(void *, struct spi_device *, int);\n\ntypedef void (*btf_trace_spi_transfer_start)(void *, struct spi_message *, struct spi_transfer *);\n\ntypedef void (*btf_trace_spi_transfer_stop)(void *, struct spi_message *, struct spi_transfer *);\n\ntypedef void (*btf_trace_spmi_cmd)(void *, u8, u8, int);\n\ntypedef void (*btf_trace_spmi_read_begin)(void *, u8, u8, u16);\n\ntypedef void (*btf_trace_spmi_read_end)(void *, u8, u8, u16, int, u8, const u8 *);\n\ntypedef void (*btf_trace_spmi_write_begin)(void *, u8, u8, u16, u8, const u8 *);\n\ntypedef void (*btf_trace_spmi_write_end)(void *, u8, u8, u16, int);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_svc_alloc_arg_err)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_svc_authenticate)(void *, const struct svc_rqst *, enum svc_auth_status);\n\ntypedef void (*btf_trace_svc_defer)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_defer_drop)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_queue)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_recv)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_drop)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_noregister)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_pool_thread_noidle)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_running)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_wake)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_process)(void *, const struct svc_rqst *, const char *);\n\ntypedef void (*btf_trace_svc_register)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_replace_page_err)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_send)(void *, const struct svc_rqst *, int);\n\ntypedef void (*btf_trace_svc_stats_latency)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_tls_not_started)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_start)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_timed_out)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_unavailable)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_upcall)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_unregister)(void *, const char *, const u32, int);\n\ntypedef void (*btf_trace_svc_xdr_recvfrom)(void *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xdr_sendto)(void *, __be32, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xprt_accept)(void *, const struct svc_xprt *, const char *);\n\ntypedef void (*btf_trace_svc_xprt_close)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_create_err)(void *, const char *, const char *, struct sockaddr *, size_t, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_dequeue)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_xprt_detach)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_enqueue)(void *, const struct svc_xprt *, long unsigned int);\n\ntypedef void (*btf_trace_svc_xprt_free)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_no_write_space)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svcsock_accept_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_data_ready)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_free)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_getpeername_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_marker)(void *, const struct svc_xprt *, __be32);\n\ntypedef void (*btf_trace_svcsock_new)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_tcp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_eagain)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_short)(void *, const struct svc_xprt *, u32, u32);\n\ntypedef void (*btf_trace_svcsock_tcp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_state)(void *, const struct svc_xprt *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_udp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_write_space)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_swiotlb_bounced)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_task_prctl_unknown)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef void (*btf_trace_tasklet_entry)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tasklet_exit)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tcp_ao_handshake_failure)(void *, const struct sock *, const struct sk_buff *, const __u8, const __u8, const __u8);\n\ntypedef void (*btf_trace_tcp_bad_csum)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_cong_state_set)(void *, struct sock *, const u8);\n\ntypedef void (*btf_trace_tcp_cwnd_reduction_tp)(void *, const struct sock *, int, int, int);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_hash_ao_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_bad_header)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_mismatch)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_unexpected)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *, const enum sk_rst_reason);\n\ntypedef void (*btf_trace_tcp_sendmsg_locked)(void *, const struct sock *, const struct msghdr *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tegra_dma_complete_cb)(void *, struct dma_chan *, int, void *);\n\ntypedef void (*btf_trace_tegra_dma_isr)(void *, struct dma_chan *, int);\n\ntypedef void (*btf_trace_tegra_dma_tx_status)(void *, struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\ntypedef void (*btf_trace_test_pages_isolated)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_thermal_power_actor)(void *, struct thermal_zone_device *, int, u32, u32);\n\ntypedef void (*btf_trace_thermal_power_allocator)(void *, struct thermal_zone_device *, u32, u32, int, u32, u32, int, s32);\n\ntypedef void (*btf_trace_thermal_power_allocator_pid)(void *, struct thermal_zone_device *, s32, s32, s64, s64, s64, s32);\n\ntypedef void (*btf_trace_thermal_power_cpu_get_power_simple)(void *, int, u32);\n\ntypedef void (*btf_trace_thermal_power_cpu_limit)(void *, const struct cpumask *, unsigned int, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_power_devfreq_get_power)(void *, struct thermal_cooling_device *, struct devfreq_dev_status *, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_power_devfreq_limit)(void *, struct thermal_cooling_device *, long unsigned int, long unsigned int, u32);\n\ntypedef void (*btf_trace_thermal_temperature)(void *, struct thermal_zone_device *);\n\ntypedef void (*btf_trace_thermal_zone_trip)(void *, struct thermal_zone_device *, int, enum thermal_trip_type);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_timer_base_idle)(void *, bool, unsigned int);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_tls_alert_recv)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_alert_send)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_contenttype)(void *, const struct sock *, unsigned char);\n\ntypedef void (*btf_trace_tmigr_connect_child_parent)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_connect_cpu_parent)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_active)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_available)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_unavailable)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_group_set)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_active)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_inactive)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_handle_remote)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_handle_remote_cpu)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_update_events)(void *, struct tmigr_group *, struct tmigr_group *, union tmigr_state, union tmigr_state, u64);\n\ntypedef void (*btf_trace_track_foreign_dirty)(void *, struct folio *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_ufs_mtk_clk_scale)(void *, const char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_ufs_mtk_event)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ufshcd_auto_bkops_state)(void *, struct ufs_hba *, const char *);\n\ntypedef void (*btf_trace_ufshcd_clk_gating)(void *, struct ufs_hba *, int);\n\ntypedef void (*btf_trace_ufshcd_clk_scaling)(void *, struct ufs_hba *, const char *, const char *, u32, u32);\n\ntypedef void (*btf_trace_ufshcd_command)(void *, struct scsi_device *, struct ufs_hba *, enum ufs_trace_str_t, unsigned int, u32, u32, int, u32, u64, u8, u8);\n\ntypedef void (*btf_trace_ufshcd_exception_event)(void *, struct ufs_hba *, u16);\n\ntypedef void (*btf_trace_ufshcd_init)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_profile_clk_gating)(void *, struct ufs_hba *, const char *, s64, int);\n\ntypedef void (*btf_trace_ufshcd_profile_clk_scaling)(void *, struct ufs_hba *, const char *, s64, int);\n\ntypedef void (*btf_trace_ufshcd_profile_hibern8)(void *, struct ufs_hba *, const char *, s64, int);\n\ntypedef void (*btf_trace_ufshcd_runtime_resume)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_runtime_suspend)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_system_resume)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_system_suspend)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_uic_command)(void *, struct ufs_hba *, enum ufs_trace_str_t, u32, u32, u32, u32);\n\ntypedef void (*btf_trace_ufshcd_upiu)(void *, struct ufs_hba *, enum ufs_trace_str_t, void *, void *, enum ufs_trace_tsf_t);\n\ntypedef void (*btf_trace_ufshcd_wl_resume)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_wl_runtime_resume)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_wl_runtime_suspend)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_ufshcd_wl_suspend)(void *, struct ufs_hba *, int, s64, int, int);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_usb_alloc_dev)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_usb_ep_alloc_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_clear_halt)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_dequeue)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_disable)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_enable)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_fifo_flush)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_fifo_status)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_free_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_queue)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_ep_set_halt)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_set_maxpacket_limit)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_ep_set_wedge)(void *, struct usb_ep *, int);\n\ntypedef void (*btf_trace_usb_gadget_activate)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_clear_selfpowered)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_connect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_deactivate)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_disconnect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_frame_number)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_giveback_request)(void *, struct usb_ep *, struct usb_request *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_remote_wakeup)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_selfpowered)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_set_state)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_connect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_disconnect)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_vbus_draw)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_gadget_wakeup)(void *, struct usb_gadget *, int);\n\ntypedef void (*btf_trace_usb_set_device_state)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_vgic_update_irq_pending)(void *, long unsigned int, __u32, bool);\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_watchdog_ping)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_set_timeout)(void *, struct watchdog_device *, unsigned int, int);\n\ntypedef void (*btf_trace_watchdog_start)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_watchdog_stop)(void *, struct watchdog_device *, int);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_dirty_folio)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, long unsigned int, int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int, struct xdp_cpumap_stats *);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xhci_add_endpoint)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctx)(void *, struct xhci_hcd *, struct xhci_container_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_stream_info_ctx)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_alloc_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_dbc_alloc_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_free_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_gadget_ep_queue)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_giveback_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_dbc_queue_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbg_address)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_cancel_urb)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_context_change)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_init)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_quirks)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_reset_ep)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_ring_expansion)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_discover_or_reset_device)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_get_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_cmd_addr_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_config_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_disable_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_stream)(void *, struct xhci_stream_info *, unsigned int);\n\ntypedef void (*btf_trace_xhci_handle_cmd_stop_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_command)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_handle_port_status)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_hub_status_data)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_inc_deq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_inc_enq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_portsc_writel)(void *, struct xhci_port *, u32);\n\ntypedef void (*btf_trace_xhci_queue_trb)(void *, struct xhci_ring *, struct xhci_generic_trb *, dma_addr_t);\n\ntypedef void (*btf_trace_xhci_ring_alloc)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_ep_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_ring_expansion)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_free)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_host_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_setup_addressable_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_stop_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_urb_dequeue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_enqueue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_giveback)(void *, struct urb *);\n\ntypedef void (*btf_trace_xprt_connect)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_create)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_destroy)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_auto)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_done)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_force)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_get_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_lookup_rqst)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_ping)(void *, const struct rpc_xprt *, int);\n\ntypedef void (*btf_trace_xprt_put_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_reserve_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_retransmit)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_timer)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_transmit)(void *, const struct rpc_rqst *, int);\n\ntypedef void (*btf_trace_xs_data_ready)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xs_stream_read_data)(void *, struct rpc_xprt *, ssize_t, size_t);\n\ntypedef void (*btf_trace_xs_stream_read_request)(void *, struct sock_xprt *);\n\ntypedef struct mtd_info *cfi_cmdset_fn_t(struct map_info *, int);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef void (*companion_fn)(struct pci_dev *, struct usb_hcd *, struct pci_dev *, struct usb_hcd *);\n\ntypedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *);\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\ntypedef int (*copy_fn_t)(void *, const void *, u32, struct task_struct *);\n\ntypedef long unsigned int (*count_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int devlink_chunk_fill_t(void *, u8 *, u32, u64, struct netlink_ext_ack *);\n\ntypedef int devlink_nl_dump_one_func_t(struct sk_buff *, struct devlink *, struct netlink_callback *, int);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\ntypedef efi_status_t (*efi_exit_boot_map_processing)(struct efi_boot_memmap *, void *);\n\ntypedef int (*efi_memattr_perm_setter)(struct mm_struct *, efi_memory_desc_t *, bool);\n\ntypedef int (*entry_fn_t)(struct vgic_its *, u32, void *, void *);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef int (*exit_handle_fn)(struct kvm_vcpu *);\n\ntypedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\ntypedef void ext4_update_sb_callback(struct ext4_sb_info *, struct ext4_super_block *, const void *);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, struct mm_struct *);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef struct irq_chip * (*gpio_get_irq_chip_cb_t)(unsigned int);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef void (*hcall_t)(struct kvm_cpu_context *);\n\ntypedef int (*hclge_mbx_ops_fn)(struct hclge_mbx_ops_param *);\n\ntypedef bool (*hid_usage_cmp_t)(struct hid_usage *, unsigned int, unsigned int);\n\ntypedef int hwpoison_filter_func_t(struct page *);\n\ntypedef const struct iio_mount_matrix *iio_get_mount_matrix_t(const struct iio_dev *, const struct iio_chan_spec *);\n\ntypedef u32 inet6_ehashfn_t(const struct net *, const struct in6_addr *, const u16, const struct in6_addr *, const __be16);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef int (*ioctl_fn)(struct file *, struct autofs_sb_info *, struct autofs_dev_ioctl *);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef int (*ioremap_prot_hook_t)(phys_addr_t, size_t, pgprot_t *);\n\ntypedef acpi_status (*iort_find_node_callback)(struct acpi_iort_node *, void *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef int (*iova_bitmap_fn_t)(struct iova_bitmap *, long unsigned int, size_t, void *);\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *, const struct inet6_skb_parm *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef struct its_collection * (*its_cmd_builder_t)(struct its_node *, struct its_cmd_block *, struct its_cmd_desc *);\n\ntypedef struct its_vpe * (*its_cmd_vbuilder_t)(struct its_node *, struct its_cmd_block *, struct its_cmd_desc *);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef void kpti_remap_fn(int, int, phys_addr_t, long unsigned int);\n\ntypedef bool (*kunwind_consume_fn)(const struct kunwind_state *, void *);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef void (*mapped_f)(struct perf_event *, struct mm_struct *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*nlm_host_match_fn_t)(void *, struct nlm_host *);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef struct gpio_desc * (*of_find_gpio_quirk)(struct device_node *, const char *, unsigned int, enum of_gpio_flags *);\n\ntypedef void (*of_init_fn_1)(struct device_node *);\n\ntypedef int (*of_init_fn_1_ret)(struct device_node *);\n\ntypedef int (*of_init_fn_2)(struct device_node *, struct device_node *);\n\ntypedef void (*online_page_callback_t)(struct page *, unsigned int);\n\ntypedef int (*otp_op_t)(struct map_info *, struct flchip *, loff_t, size_t, u_char *, size_t);\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef void (*pci_parity_check_fn_t)(struct pci_dev *);\n\ntypedef int (*pcie_callback_t)(struct pcie_device *);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\ntypedef int perf_snapshot_branch_stack_t(struct perf_branch_entry *, unsigned int);\n\ntypedef int (*platform_irq_probe_t)(struct platform_device *, struct device_node *);\n\ntypedef int (*pm_callback_t)(struct device *);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef long unsigned int psci_fn(long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef int (*psci_initcall_t)(const struct device_node *);\n\ntypedef bool pstate_check_t(long unsigned int);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\ntypedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\ntypedef int (*reservedmem_of_init_fn)(struct reserved_mem *);\n\ntypedef bool (*ring_buffer_cond_fn)(void *);\n\ntypedef void (*rpc_action)(struct rpc_task *);\n\ntypedef int (*rproc_handle_resource_t)(struct rproc *, void *, int, int);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef long unsigned int (*scan_objects_cb)(struct shrinker *, struct shrink_control *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef void (*set_params_cb)(struct dwc2_hsotg *);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef long int (*syscall_fn_t)(const struct pt_regs *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef void (*tegra_clk_apply_init_table_func)(void);\n\ntypedef void text_poke_f(void *, void *, size_t, size_t);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef int (*trace_user_buf_copy)(char *, const char *, size_t, void *);\n\ntypedef void ttbr_replace_func(phys_addr_t);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*uprobe_write_verify_t)(struct page *, long unsigned int, uprobe_opcode_t *, int, void *);\n\ntypedef int (*varsize_frob_t)(struct map_info *, struct flchip *, long unsigned int, int, void *);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef void wait_split_fn(void);\n\ntypedef int (*walk_memory_groups_func_t)(struct memory_group *, void *);\n\ntypedef void (*xen_gfn_fn_t)(long unsigned int, void *);\n\ntypedef void (*xen_grant_fn_t)(long unsigned int, unsigned int, unsigned int, void *);\n\ntypedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);\n\ntypedef struct rpc_xprt * (*xprt_switch_find_xprt_t)(struct rpc_xprt_switch *, const struct rpc_xprt *);\n\nstruct ftrace_regs;\n\nstruct amd5536udc;\n\nstruct bpf_iter;\n\nstruct fscrypt_inode_info;\n\nstruct megasas_debug_buffer;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern void __attribute__((address_space(1))) *bpf_arena_alloc_pages(void *p__map, void __attribute__((address_space(1))) *addr__ign, u32 page_cnt, int node_id, u64 flags) __weak __ksym;\nextern void bpf_arena_free_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern int bpf_arena_reserve_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern struct cgroup *bpf_cgroup_from_id(u64 cgid) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_task_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_dynptr_adjust(const struct bpf_dynptr *p, u64 start, u64 end) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_copy(struct bpf_dynptr *dst_ptr, u64 dst_off, struct bpf_dynptr *src_ptr, u64 src_off, u64 size) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb(struct __sk_buff *s, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb_meta(struct __sk_buff *skb_, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_xdp(struct xdp_md *x, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_dynptr_memset(struct bpf_dynptr *p, u64 offset, u64 size, u8 val) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern void *bpf_dynptr_slice(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern void *bpf_dynptr_slice_rdwr(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern struct kmem_cache *bpf_get_kmem_cache(u64 addr) __weak __ksym;\nextern struct mem_cgroup *bpf_get_mem_cgroup(struct cgroup_subsys_state *css) __weak __ksym;\nextern struct mem_cgroup *bpf_get_root_mem_cgroup(void) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern int bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it, struct task_struct *task, u64 addr) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern struct bpf_key *bpf_lookup_system_key(u64 id) __weak __ksym;\nextern struct bpf_key *bpf_lookup_user_key(s32 serial, u64 flags) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern void bpf_mem_cgroup_flush_stats(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_memory_events(struct mem_cgroup *memcg, enum memcg_memory_event event) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_page_state(struct mem_cgroup *memcg, int idx) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_usage(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_vm_events(struct mem_cgroup *memcg, enum vm_event_item event) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_percpu_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern int bpf_probe_read_kernel_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_kernel_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern void bpf_put_mem_cgroup(struct mem_cgroup *memcg) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_send_signal_task(struct task_struct *task, int sig, enum pid_type type, u64 value) __weak __ksym;\nextern __u64 *bpf_session_cookie(void *ctx) __weak __ksym;\nextern bool bpf_session_is_return(void *ctx) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_sock_ops_enable_tx_tstamp(struct bpf_sock_ops_kern *skops, u64 flags) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern void bpf_throw(u64 cookie) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_verify_pkcs7_signature(struct bpf_dynptr *data_p, struct bpf_dynptr *sig_p, struct bpf_key *trusted_keyring) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void crash_kexec(struct pt_regs *regs) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __weak __ksym;\nextern void scx_bpf_destroy_dsq(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_insert___v2(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local(u64 dsq_id) __weak __ksym;\nextern bool scx_bpf_dsq_move_vtime(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __weak __ksym;\nextern struct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern void scx_bpf_exit_bstr(s64 exit_code, char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern void scx_bpf_kick_cpu(s32 cpu, u64 flags) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern s32 scx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags, const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __weak __ksym;\nextern bool scx_bpf_sub_dispatch(u64 cgroup_id) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime) __weak __ksym;\nextern bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n#pragma clang diagnostic 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diagnostic ignored \"-Wmissing-declarations\"\n#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\n#ifndef __ksym\n#define __ksym __attribute__((section(\".ksyms\")))\n#endif\n\n#ifndef __weak\n#define __weak __attribute__((weak))\n#endif\n\n#ifndef __bpf_fastcall\n#if __has_attribute(bpf_fastcall)\n#define __bpf_fastcall __attribute__((bpf_fastcall))\n#else\n#define __bpf_fastcall\n#endif\n#endif\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_DELAYED_REPREP = 2,\n\tACTION_RETRY = 3,\n\tACTION_DELAYED_RETRY = 4,\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DMPS = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_CPD = 1048576,\n\tPORT_CMD_MPSP = 524288,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_CMD_CAP = 8126464,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_SUSPEND_PHYS = 33554432,\n\tAHCI_HFLAG_NO_SXS = 67108864,\n\tAHCI_HFLAG_43BIT_ONLY = 134217728,\n\tAHCI_HFLAG_INTEL_PCS_QUIRK = 268435456,\n\tAHCI_HFLAG_ATAPI_DMA_QUIRK = 536870912,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 15,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum {\n\tASCII_NULL = 0,\n\tASCII_BELL = 7,\n\tASCII_BACKSPACE = 8,\n\tASCII_IGNORE_FIRST = 8,\n\tASCII_HTAB = 9,\n\tASCII_LINEFEED = 10,\n\tASCII_VTAB = 11,\n\tASCII_FORMFEED = 12,\n\tASCII_CAR_RET = 13,\n\tASCII_IGNORE_LAST = 13,\n\tASCII_SHIFTOUT = 14,\n\tASCII_SHIFTIN = 15,\n\tASCII_CANCEL = 24,\n\tASCII_SUBSTITUTE = 26,\n\tASCII_ESCAPE = 27,\n\tASCII_CSI_IGNORE_FIRST = 32,\n\tASCII_CSI_IGNORE_LAST = 63,\n\tASCII_DEL = 127,\n\tASCII_EXT_CSI = 155,\n};\n\nenum {\n\tASSUME_PERFECT = 255,\n\tASSUME_VALID_DTB = 1,\n\tASSUME_VALID_INPUT = 2,\n\tASSUME_LATEST = 4,\n\tASSUME_NO_ROLLBACK = 8,\n\tASSUME_LIBFDT_ORDER = 16,\n\tASSUME_LIBFDT_FLAWLESS = 32,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = -2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nenum {\n\tATA_GEN_CLASS_MATCH = 1,\n\tATA_GEN_FORCE_DMA = 2,\n\tATA_GEN_INTEL_IDER = 4,\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = -2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_CDL = 24,\n\tATA_LOG_CDL_SIZE = 512,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SENSE_NCQ = 15,\n\tATA_LOG_SENSE_NCQ_SIZE = 1024,\n\tATA_LOG_CONCURRENT_POSITIONING_RANGES = 71,\n\tATA_LOG_SUPPORTED_CAPABILITIES = 3,\n\tATA_LOG_CURRENT_SETTINGS = 4,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSETFEATURES_CDL = 13,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tSETFEATURE_SENSE_DATA_SUCC_NCQ = 196,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum {\n\tATA_QUIRK_DIAGNOSTIC = 1,\n\tATA_QUIRK_NODMA = 2,\n\tATA_QUIRK_NONCQ = 4,\n\tATA_QUIRK_BROKEN_HPA = 8,\n\tATA_QUIRK_DISABLE = 16,\n\tATA_QUIRK_HPA_SIZE = 32,\n\tATA_QUIRK_IVB = 64,\n\tATA_QUIRK_STUCK_ERR = 128,\n\tATA_QUIRK_BRIDGE_OK = 256,\n\tATA_QUIRK_ATAPI_MOD16_DMA = 512,\n\tATA_QUIRK_FIRMWARE_WARN = 1024,\n\tATA_QUIRK_1_5_GBPS = 2048,\n\tATA_QUIRK_NOSETXFER = 4096,\n\tATA_QUIRK_BROKEN_FPDMA_AA = 8192,\n\tATA_QUIRK_DUMP_ID = 16384,\n\tATA_QUIRK_MAX_SEC_LBA48 = 32768,\n\tATA_QUIRK_ATAPI_DMADIR = 65536,\n\tATA_QUIRK_NO_NCQ_TRIM = 131072,\n\tATA_QUIRK_NOLPM = 262144,\n\tATA_QUIRK_WD_BROKEN_LPM = 524288,\n\tATA_QUIRK_ZERO_AFTER_TRIM = 1048576,\n\tATA_QUIRK_NO_DMA_LOG = 2097152,\n\tATA_QUIRK_NOTRIM = 4194304,\n\tATA_QUIRK_MAX_SEC = 8388608,\n\tATA_QUIRK_MAX_TRIM_128M = 16777216,\n\tATA_QUIRK_NO_NCQ_ON_ATI = 33554432,\n\tATA_QUIRK_NO_LPM_ON_ATI = 67108864,\n\tATA_QUIRK_NO_ID_DEV_LOG = 134217728,\n\tATA_QUIRK_NO_LOG_DIR = 268435456,\n\tATA_QUIRK_NO_FUA = 536870912,\n};\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = -2147483648,\n};\n\nenum {\n\tAT_PKT_END = -1,\n\tBEYOND_PKT_END = -2,\n};\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_MAX_VALUES = 13,\n};\n\nenum {\n\tAudit_equal = 0,\n\tAudit_not_equal = 1,\n\tAudit_bitmask = 2,\n\tAudit_bittest = 3,\n\tAudit_lt = 4,\n\tAudit_gt = 5,\n\tAudit_le = 6,\n\tAudit_ge = 7,\n\tAudit_bad = 8,\n};\n\nenum {\n\tBCM54XX_COPPER = 0,\n\tBCM54XX_FIBER = 1,\n\tBCM54XX_GBIC = 2,\n\tBCM54XX_SGMII = 3,\n\tBCM54XX_UNKNOWN = 4,\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n\tBIOSET_PERCPU_CACHE = 4,\n};\n\nenum {\n\tBIO_PAGE_PINNED = 0,\n\tBIO_CLONED = 1,\n\tBIO_QUIET = 2,\n\tBIO_CHAIN = 3,\n\tBIO_REFFED = 4,\n\tBIO_BPS_THROTTLED = 5,\n\tBIO_TRACE_COMPLETION = 6,\n\tBIO_CGROUP_ACCT = 7,\n\tBIO_QOS_THROTTLED = 8,\n\tBIO_TG_BPS_THROTTLED = 8,\n\tBIO_QOS_MERGED = 9,\n\tBIO_REMAPPED = 10,\n\tBIO_ZONE_WRITE_PLUGGING = 11,\n\tBIO_EMULATES_ZONE_APPEND = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum {\n\tBLK_MQ_F_TAG_QUEUE_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_TAG_HCTX_SHARED = 8,\n\tBLK_MQ_F_BLOCKING = 16,\n\tBLK_MQ_F_TAG_RR = 32,\n\tBLK_MQ_F_NO_SCHED_BY_DEFAULT = 64,\n\tBLK_MQ_F_MAX = 128,\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_PM = 4,\n};\n\nenum {\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_S_MAX = 4,\n};\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n\tBPF_F_CPU = 8,\n\tBPF_F_ALL_CPUS = 16,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n\tBPF_FIB_LKUP_RET_NO_SRC_ADDR = 9,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n\tBPF_FIB_LOOKUP_SKIP_NEIGH = 4,\n\tBPF_FIB_LOOKUP_TBID = 8,\n\tBPF_FIB_LOOKUP_SRC = 16,\n\tBPF_FIB_LOOKUP_MARK = 32,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n\tBPF_F_ADJ_ROOM_ENCAP_L2_ETH = 64,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV4 = 128,\n\tBPF_F_ADJ_ROOM_DECAP_L3_IPV6 = 256,\n};\n\nenum {\n\tBPF_F_BPRM_SECUREEXEC = 1,\n};\n\nenum {\n\tBPF_F_CURRENT_NETNS = -1,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295ULL,\n\tBPF_F_CURRENT_CPU = 4294967295ULL,\n\tBPF_F_CTXLEN_MASK = 4503595332403200ULL,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n\tBPF_F_BROADCAST = 8,\n\tBPF_F_EXCLUDE_INGRESS = 16,\n};\n\nenum {\n\tBPF_F_KPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_NEIGH = 65536,\n\tBPF_F_PEER = 131072,\n\tBPF_F_NEXTHOP = 262144,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n\tBPF_F_PRESERVE_ELEMS = 2048,\n\tBPF_F_INNER_MAP = 4096,\n\tBPF_F_LINK = 8192,\n\tBPF_F_PATH_FD = 16384,\n\tBPF_F_VTYPE_BTF_OBJ_FD = 32768,\n\tBPF_F_TOKEN_FD = 65536,\n\tBPF_F_SEGV_ON_FAULT = 131072,\n\tBPF_F_NO_USER_CONV = 262144,\n\tBPF_F_RB_OVERWRITE = 524288,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n\tBPF_F_IPV6 = 128,\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\nenum {\n\tBPF_F_SYSCTL_BASE_NAME = 1,\n};\n\nenum {\n\tBPF_F_TIMER_ABS = 1,\n\tBPF_F_TIMER_CPU_PIN = 2,\n};\n\nenum {\n\tBPF_F_TUNINFO_FLAGS = 16,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_UPROBE_MULTI_RETURN = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n\tBPF_F_NO_TUNNEL_KEY = 16,\n};\n\nenum {\n\tBPF_LOAD_HDR_OPT_TCP_SYN = 1,\n};\n\nenum {\n\tBPF_LOCAL_STORAGE_GET_F_CREATE = 1,\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nenum {\n\tBPF_MAX_LOOPS = 8388608,\n\tBPF_MAX_TIMED_LOOPS = 65535,\n};\n\nenum {\n\tBPF_MAX_TRAMP_LINKS = 38,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n\tBPF_RB_OVERWRITE_POS = 4,\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nenum {\n\tBPF_SKB_TSTAMP_UNSPEC = 0,\n\tBPF_SKB_TSTAMP_DELIVERY_MONO = 1,\n\tBPF_SKB_CLOCK_REALTIME = 0,\n\tBPF_SKB_CLOCK_MONOTONIC = 1,\n\tBPF_SKB_CLOCK_TAI = 2,\n};\n\nenum {\n\tBPF_SK_LOOKUP_F_REPLACE = 1,\n\tBPF_SK_LOOKUP_F_NO_REUSEPORT = 2,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = 16,\n\tBPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = 32,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = 64,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 127,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n\tBPF_SOCK_OPS_PARSE_HDR_OPT_CB = 13,\n\tBPF_SOCK_OPS_HDR_OPT_LEN_CB = 14,\n\tBPF_SOCK_OPS_WRITE_HDR_OPT_CB = 15,\n\tBPF_SOCK_OPS_TSTAMP_SCHED_CB = 16,\n\tBPF_SOCK_OPS_TSTAMP_SND_SW_CB = 17,\n\tBPF_SOCK_OPS_TSTAMP_SND_HW_CB = 18,\n\tBPF_SOCK_OPS_TSTAMP_ACK_CB = 19,\n\tBPF_SOCK_OPS_TSTAMP_SENDMSG_CB = 20,\n};\n\nenum {\n\tBPF_STREAM_MAX_CAPACITY = 100000,\n};\n\nenum {\n\tBPF_TASK_ITER_ALL_PROCS = 0,\n\tBPF_TASK_ITER_ALL_THREADS = 1,\n\tBPF_TASK_ITER_PROC_THREADS = 2,\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_BOUND_INACTIVE = 13,\n\tBPF_TCP_MAX_STATES = 14,\n};\n\nenum {\n\tBPF_WRITE_HDR_TCP_CURRENT_MSS = 1,\n\tBPF_WRITE_HDR_TCP_SYNACK_COOKIE = 2,\n};\n\nenum {\n\tBPF_XFRM_STATE_OPTS_SZ = 36,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum {\n\tBTF_FIELDS_MAX = 11,\n};\n\nenum {\n\tBTF_FIELD_IGNORE = 0,\n\tBTF_FIELD_FOUND = 1,\n};\n\nenum {\n\tBTF_F_COMPACT = 1,\n\tBTF_F_NONAME = 2,\n\tBTF_F_PTR_RAW = 4,\n\tBTF_F_ZERO = 8,\n};\n\nenum {\n\tBTF_KFUNC_SET_MAX_CNT = 256,\n\tBTF_DTOR_KFUNC_MAX_CNT = 256,\n\tBTF_KFUNC_FILTER_MAX_CNT = 16,\n};\n\nenum {\n\tBTF_KIND_UNKN = 0,\n\tBTF_KIND_INT = 1,\n\tBTF_KIND_PTR = 2,\n\tBTF_KIND_ARRAY = 3,\n\tBTF_KIND_STRUCT = 4,\n\tBTF_KIND_UNION = 5,\n\tBTF_KIND_ENUM = 6,\n\tBTF_KIND_FWD = 7,\n\tBTF_KIND_TYPEDEF = 8,\n\tBTF_KIND_VOLATILE = 9,\n\tBTF_KIND_CONST = 10,\n\tBTF_KIND_RESTRICT = 11,\n\tBTF_KIND_FUNC = 12,\n\tBTF_KIND_FUNC_PROTO = 13,\n\tBTF_KIND_VAR = 14,\n\tBTF_KIND_DATASEC = 15,\n\tBTF_KIND_FLOAT = 16,\n\tBTF_KIND_DECL_TAG = 17,\n\tBTF_KIND_TYPE_TAG = 18,\n\tBTF_KIND_ENUM64 = 19,\n\tNR_BTF_KINDS = 20,\n\tBTF_KIND_MAX = 19,\n};\n\nenum {\n\tBTF_MODULE_F_LIVE = 1,\n};\n\nenum {\n\tBTF_SOCK_TYPE_INET = 0,\n\tBTF_SOCK_TYPE_INET_CONN = 1,\n\tBTF_SOCK_TYPE_INET_REQ = 2,\n\tBTF_SOCK_TYPE_INET_TW = 3,\n\tBTF_SOCK_TYPE_REQ = 4,\n\tBTF_SOCK_TYPE_SOCK = 5,\n\tBTF_SOCK_TYPE_SOCK_COMMON = 6,\n\tBTF_SOCK_TYPE_TCP = 7,\n\tBTF_SOCK_TYPE_TCP_REQ = 8,\n\tBTF_SOCK_TYPE_TCP_TW = 9,\n\tBTF_SOCK_TYPE_TCP6 = 10,\n\tBTF_SOCK_TYPE_UDP = 11,\n\tBTF_SOCK_TYPE_UDP6 = 12,\n\tBTF_SOCK_TYPE_UNIX = 13,\n\tBTF_SOCK_TYPE_MPTCP = 14,\n\tBTF_SOCK_TYPE_SOCKET = 15,\n\tMAX_BTF_SOCK_TYPE = 16,\n};\n\nenum {\n\tBTF_TRACING_TYPE_TASK = 0,\n\tBTF_TRACING_TYPE_FILE = 1,\n\tBTF_TRACING_TYPE_VMA = 2,\n\tMAX_BTF_TRACING_TYPE = 3,\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nenum {\n\tBlktrace_setup = 1,\n\tBlktrace_running = 2,\n\tBlktrace_stopped = 3,\n};\n\nenum {\n\tCACHE_RH_CNT = 14,\n};\n\nenum {\n\tCACHE_VALID = 0,\n\tCACHE_NEGATIVE = 1,\n\tCACHE_PENDING = 2,\n\tCACHE_CLEANED = 3,\n};\n\nenum {\n\tCACHE_WH_CNT = 15,\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n\t__CFTYPE_ADDED = 262144,\n};\n\nenum {\n\tCGROUPSTATS_CMD_ATTR_UNSPEC = 0,\n\tCGROUPSTATS_CMD_ATTR_FD = 1,\n\t__CGROUPSTATS_CMD_ATTR_MAX = 2,\n};\n\nenum {\n\tCGROUPSTATS_CMD_UNSPEC = 3,\n\tCGROUPSTATS_CMD_GET = 4,\n\tCGROUPSTATS_CMD_NEW = 5,\n\t__CGROUPSTATS_CMD_MAX = 6,\n};\n\nenum {\n\tCGROUPSTATS_TYPE_UNSPEC = 0,\n\tCGROUPSTATS_TYPE_CGROUP_STATS = 1,\n\t__CGROUPSTATS_TYPE_MAX = 2,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_FAVOR_DYNMODS = 16,\n\tCGRP_ROOT_CPUSET_V2_MODE = 65536,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 131072,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 262144,\n\tCGRP_ROOT_MEMORY_HUGETLB_ACCOUNTING = 524288,\n\tCGRP_ROOT_PIDS_LOCAL_EVENTS = 1048576,\n};\n\nenum {\n\tCMIS_MODULE_LOW_PWR = 1,\n\tCMIS_MODULE_READY = 3,\n};\n\nenum {\n\tCOREDUMP_ACK_SIZE_VER0 = 16,\n};\n\nenum {\n\tCOREDUMP_KERNEL = 1,\n\tCOREDUMP_USERSPACE = 2,\n\tCOREDUMP_REJECT = 4,\n\tCOREDUMP_WAIT = 8,\n};\n\nenum {\n\tCRI_RES_UTIL = 5,\n};\n\nenum {\n\tCRNG_EMPTY = 0,\n\tCRNG_EARLY = 1,\n\tCRNG_READY = 2,\n};\n\nenum {\n\tCRNG_RESEED_START_INTERVAL = 1000,\n\tCRNG_RESEED_INTERVAL = 60000,\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\t__CRYPTOA_MAX = 3,\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nenum {\n\tCSI_DEC_hl_CURSOR_KEYS = 1,\n\tCSI_DEC_hl_132_COLUMNS = 3,\n\tCSI_DEC_hl_REVERSE_VIDEO = 5,\n\tCSI_DEC_hl_ORIGIN_MODE = 6,\n\tCSI_DEC_hl_AUTOWRAP = 7,\n\tCSI_DEC_hl_AUTOREPEAT = 8,\n\tCSI_DEC_hl_MOUSE_X10 = 9,\n\tCSI_DEC_hl_SHOW_CURSOR = 25,\n\tCSI_DEC_hl_MOUSE_VT200 = 1000,\n\tCSI_DEC_hl_ALT_SCREEN = 1049,\n\tCSI_DEC_hl_BRACKETED_PASTE = 2004,\n};\n\nenum {\n\tCSI_K_CURSOR_TO_LINEEND = 0,\n\tCSI_K_LINESTART_TO_CURSOR = 1,\n\tCSI_K_LINE = 2,\n};\n\nenum {\n\tCSI_hl_DISPLAY_CTRL = 3,\n\tCSI_hl_INSERT = 4,\n\tCSI_hl_AUTO_NL = 20,\n};\n\nenum {\n\tCSI_m_DEFAULT = 0,\n\tCSI_m_BOLD = 1,\n\tCSI_m_HALF_BRIGHT = 2,\n\tCSI_m_ITALIC = 3,\n\tCSI_m_UNDERLINE = 4,\n\tCSI_m_BLINK = 5,\n\tCSI_m_REVERSE = 7,\n\tCSI_m_PRI_FONT = 10,\n\tCSI_m_ALT_FONT1 = 11,\n\tCSI_m_ALT_FONT2 = 12,\n\tCSI_m_DOUBLE_UNDERLINE = 21,\n\tCSI_m_NORMAL_INTENSITY = 22,\n\tCSI_m_NO_ITALIC = 23,\n\tCSI_m_NO_UNDERLINE = 24,\n\tCSI_m_NO_BLINK = 25,\n\tCSI_m_NO_REVERSE = 27,\n\tCSI_m_FG_COLOR_BEG = 30,\n\tCSI_m_FG_COLOR_END = 37,\n\tCSI_m_FG_COLOR = 38,\n\tCSI_m_DEFAULT_FG_COLOR = 39,\n\tCSI_m_BG_COLOR_BEG = 40,\n\tCSI_m_BG_COLOR_END = 47,\n\tCSI_m_BG_COLOR = 48,\n\tCSI_m_DEFAULT_BG_COLOR = 49,\n\tCSI_m_BRIGHT_FG_COLOR_BEG = 90,\n\tCSI_m_BRIGHT_FG_COLOR_END = 97,\n\tCSI_m_BRIGHT_FG_COLOR_OFF = 60,\n\tCSI_m_BRIGHT_BG_COLOR_BEG = 100,\n\tCSI_m_BRIGHT_BG_COLOR_END = 107,\n\tCSI_m_BRIGHT_BG_COLOR_OFF = 60,\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCTL_RES_CNT = 1,\n};\n\nenum {\n\tCTL_RES_TM = 2,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_POLICY_UNSPEC = 0,\n\tCTRL_ATTR_POLICY_DO = 1,\n\tCTRL_ATTR_POLICY_DUMP = 2,\n\t__CTRL_ATTR_POLICY_DUMP_MAX = 3,\n\tCTRL_ATTR_POLICY_DUMP_MAX = 2,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\tCTRL_ATTR_OP_POLICY = 9,\n\tCTRL_ATTR_OP = 10,\n\t__CTRL_ATTR_MAX = 11,\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tDAD_PROCESS = 0,\n\tDAD_BEGIN = 1,\n\tDAD_ABORT = 2,\n};\n\nenum {\n\tDDW_EXT_SIZE = 0,\n\tDDW_EXT_RESET_DMA_WIN = 1,\n\tDDW_EXT_QUERY_OUT_SIZE = 2,\n\tDDW_EXT_LIMITED_ADDR_MODE = 3,\n};\n\nenum {\n\tDDW_QUERY_PE_DMA_WIN = 0,\n\tDDW_CREATE_PE_DMA_WIN = 1,\n\tDDW_REMOVE_PE_DMA_WIN = 2,\n\tDDW_APPLICABLE_SIZE = 3,\n};\n\nenum {\n\tDD_DIR_COUNT = 2,\n};\n\nenum {\n\tDD_PRIO_COUNT = 3,\n};\n\nenum {\n\tDEVCONF_FORWARDING = 0,\n\tDEVCONF_HOPLIMIT = 1,\n\tDEVCONF_MTU6 = 2,\n\tDEVCONF_ACCEPT_RA = 3,\n\tDEVCONF_ACCEPT_REDIRECTS = 4,\n\tDEVCONF_AUTOCONF = 5,\n\tDEVCONF_DAD_TRANSMITS = 6,\n\tDEVCONF_RTR_SOLICITS = 7,\n\tDEVCONF_RTR_SOLICIT_INTERVAL = 8,\n\tDEVCONF_RTR_SOLICIT_DELAY = 9,\n\tDEVCONF_USE_TEMPADDR = 10,\n\tDEVCONF_TEMP_VALID_LFT = 11,\n\tDEVCONF_TEMP_PREFERED_LFT = 12,\n\tDEVCONF_REGEN_MAX_RETRY = 13,\n\tDEVCONF_MAX_DESYNC_FACTOR = 14,\n\tDEVCONF_MAX_ADDRESSES = 15,\n\tDEVCONF_FORCE_MLD_VERSION = 16,\n\tDEVCONF_ACCEPT_RA_DEFRTR = 17,\n\tDEVCONF_ACCEPT_RA_PINFO = 18,\n\tDEVCONF_ACCEPT_RA_RTR_PREF = 19,\n\tDEVCONF_RTR_PROBE_INTERVAL = 20,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN = 21,\n\tDEVCONF_PROXY_NDP = 22,\n\tDEVCONF_OPTIMISTIC_DAD = 23,\n\tDEVCONF_ACCEPT_SOURCE_ROUTE = 24,\n\tDEVCONF_MC_FORWARDING = 25,\n\tDEVCONF_DISABLE_IPV6 = 26,\n\tDEVCONF_ACCEPT_DAD = 27,\n\tDEVCONF_FORCE_TLLAO = 28,\n\tDEVCONF_NDISC_NOTIFY = 29,\n\tDEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL = 30,\n\tDEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL = 31,\n\tDEVCONF_SUPPRESS_FRAG_NDISC = 32,\n\tDEVCONF_ACCEPT_RA_FROM_LOCAL = 33,\n\tDEVCONF_USE_OPTIMISTIC = 34,\n\tDEVCONF_ACCEPT_RA_MTU = 35,\n\tDEVCONF_STABLE_SECRET = 36,\n\tDEVCONF_USE_OIF_ADDRS_ONLY = 37,\n\tDEVCONF_ACCEPT_RA_MIN_HOP_LIMIT = 38,\n\tDEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 39,\n\tDEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 40,\n\tDEVCONF_DROP_UNSOLICITED_NA = 41,\n\tDEVCONF_KEEP_ADDR_ON_DOWN = 42,\n\tDEVCONF_RTR_SOLICIT_MAX_INTERVAL = 43,\n\tDEVCONF_SEG6_ENABLED = 44,\n\tDEVCONF_SEG6_REQUIRE_HMAC = 45,\n\tDEVCONF_ENHANCED_DAD = 46,\n\tDEVCONF_ADDR_GEN_MODE = 47,\n\tDEVCONF_DISABLE_POLICY = 48,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN = 49,\n\tDEVCONF_NDISC_TCLASS = 50,\n\tDEVCONF_RPL_SEG_ENABLED = 51,\n\tDEVCONF_RA_DEFRTR_METRIC = 52,\n\tDEVCONF_IOAM6_ENABLED = 53,\n\tDEVCONF_IOAM6_ID = 54,\n\tDEVCONF_IOAM6_ID_WIDE = 55,\n\tDEVCONF_NDISC_EVICT_NOCARRIER = 56,\n\tDEVCONF_ACCEPT_UNTRACKED_NA = 57,\n\tDEVCONF_ACCEPT_RA_MIN_LFT = 58,\n\tDEVCONF_FORCE_FORWARDING = 59,\n\tDEVCONF_MAX = 60,\n};\n\nenum {\n\tDEVLINK_ATTR_STATS_RX_PACKETS = 0,\n\tDEVLINK_ATTR_STATS_RX_BYTES = 1,\n\tDEVLINK_ATTR_STATS_RX_DROPPED = 2,\n\t__DEVLINK_ATTR_STATS_MAX = 3,\n\tDEVLINK_ATTR_STATS_MAX = 2,\n};\n\nenum {\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_IN_PORT = 0,\n\tDEVLINK_ATTR_TRAP_METADATA_TYPE_FA_COOKIE = 1,\n};\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nenum {\n\tDIO_SHOULD_DIRTY = 1,\n\tDIO_IS_SYNC = 2,\n};\n\nenum {\n\tDIR_OFFSET_FIRST = 2,\n\tDIR_OFFSET_EOD = 2147483647,\n};\n\nenum {\n\tDIR_OFFSET_MIN = 3,\n\tDIR_OFFSET_MAX = 2147483646,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n\tDISK_EVENT_FLAG_BLOCK_ON_EXCL_WRITE = 4,\n};\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nenum {\n\tDM_IO_ACCOUNTED = 0,\n\tDM_IO_WAS_SPLIT = 1,\n\tDM_IO_BLK_STAT = 2,\n};\n\nenum {\n\tDM_TIO_INSIDE_DM_IO = 0,\n\tDM_TIO_IS_DUPLICATE_BIO = 1,\n};\n\nenum {\n\tDM_VERSION_CMD = 0,\n\tDM_REMOVE_ALL_CMD = 1,\n\tDM_LIST_DEVICES_CMD = 2,\n\tDM_DEV_CREATE_CMD = 3,\n\tDM_DEV_REMOVE_CMD = 4,\n\tDM_DEV_RENAME_CMD = 5,\n\tDM_DEV_SUSPEND_CMD = 6,\n\tDM_DEV_STATUS_CMD = 7,\n\tDM_DEV_WAIT_CMD = 8,\n\tDM_TABLE_LOAD_CMD = 9,\n\tDM_TABLE_CLEAR_CMD = 10,\n\tDM_TABLE_DEPS_CMD = 11,\n\tDM_TABLE_STATUS_CMD = 12,\n\tDM_LIST_VERSIONS_CMD = 13,\n\tDM_TARGET_MSG_CMD = 14,\n\tDM_DEV_SET_GEOMETRY_CMD = 15,\n\tDM_DEV_ARM_POLL_CMD = 16,\n\tDM_GET_TARGET_VERSION_CMD = 17,\n\tDM_MPATH_PROBE_PATHS_CMD = 18,\n};\n\nenum {\n\tDONE_EXPLORING = 0,\n\tKEEP_EXPLORING = 1,\n};\n\nenum {\n\tDTL_ALL = 7,\n};\n\nenum {\n\tDTL_CEDE = 1,\n};\n\nenum {\n\tDTL_FAULT = 4,\n};\n\nenum {\n\tDTL_PREEMPT = 2,\n};\n\nenum {\n\tDTRIG_UNKNOWN = 0,\n\tDTRIG_VECTOR_CI = 1,\n\tDTRIG_SUSPEND_ESCAPE = 2,\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nenum {\n\tEEH_NEXT_ERR_NONE = 0,\n\tEEH_NEXT_ERR_INF = 1,\n\tEEH_NEXT_ERR_FROZEN_PE = 2,\n\tEEH_NEXT_ERR_FENCED_PHB = 3,\n\tEEH_NEXT_ERR_DEAD_PHB = 4,\n\tEEH_NEXT_ERR_DEAD_IOC = 5,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_C33_PSE_PW_LIMIT_UNSPEC = 0,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MIN = 1,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_CNT = 3,\n\t__ETHTOOL_A_C33_PSE_PW_LIMIT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_SRC = 3,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 4,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_INF_SRC_UNSPEC = 0,\n\tETHTOOL_A_CABLE_INF_SRC_TDR = 1,\n\tETHTOOL_A_CABLE_INF_SRC_ALCD = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_CODE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_CODE_OK = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE_OPEN = 2,\n\tETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT = 3,\n\tETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT = 4,\n\tETHTOOL_A_CABLE_RESULT_CODE_IMPEDANCE_MISMATCH = 5,\n\tETHTOOL_A_CABLE_RESULT_CODE_NOISE = 6,\n\tETHTOOL_A_CABLE_RESULT_CODE_RESOLUTION_NOT_POSSIBLE = 7,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\tETHTOOL_A_CABLE_RESULT_SRC = 3,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 4,\n\tETHTOOL_A_CABLE_RESULT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_TX = 24,\n\tETHTOOL_A_COALESCE_USE_CQE_MODE_RX = 25,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES = 26,\n\tETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES = 27,\n\tETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS = 28,\n\tETHTOOL_A_COALESCE_RX_PROFILE = 29,\n\tETHTOOL_A_COALESCE_TX_PROFILE = 30,\n\t__ETHTOOL_A_COALESCE_CNT = 31,\n\tETHTOOL_A_COALESCE_MAX = 30,\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_HIST_PAD = 1,\n\tETHTOOL_A_FEC_HIST_BIN_LOW = 2,\n\tETHTOOL_A_FEC_HIST_BIN_HIGH = 3,\n\tETHTOOL_A_FEC_HIST_BIN_VAL = 4,\n\tETHTOOL_A_FEC_HIST_BIN_VAL_PER_LANE = 5,\n\t__ETHTOOL_A_FEC_HIST_CNT = 6,\n\tETHTOOL_A_FEC_HIST_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_STAT_UNSPEC = 0,\n\tETHTOOL_A_FEC_STAT_PAD = 1,\n\tETHTOOL_A_FEC_STAT_CORRECTED = 2,\n\tETHTOOL_A_FEC_STAT_UNCORR = 3,\n\tETHTOOL_A_FEC_STAT_CORR_BITS = 4,\n\tETHTOOL_A_FEC_STAT_HIST = 5,\n\t__ETHTOOL_A_FEC_STAT_CNT = 6,\n\tETHTOOL_A_FEC_STAT_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FEC_UNSPEC = 0,\n\tETHTOOL_A_FEC_HEADER = 1,\n\tETHTOOL_A_FEC_MODES = 2,\n\tETHTOOL_A_FEC_AUTO = 3,\n\tETHTOOL_A_FEC_ACTIVE = 4,\n\tETHTOOL_A_FEC_STATS = 5,\n\t__ETHTOOL_A_FEC_CNT = 6,\n\tETHTOOL_A_FEC_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_FLOW_ETHER = 1,\n\tETHTOOL_A_FLOW_IP4 = 2,\n\tETHTOOL_A_FLOW_IP6 = 3,\n\tETHTOOL_A_FLOW_TCP4 = 4,\n\tETHTOOL_A_FLOW_TCP6 = 5,\n\tETHTOOL_A_FLOW_UDP4 = 6,\n\tETHTOOL_A_FLOW_UDP6 = 7,\n\tETHTOOL_A_FLOW_SCTP4 = 8,\n\tETHTOOL_A_FLOW_SCTP6 = 9,\n\tETHTOOL_A_FLOW_AH4 = 10,\n\tETHTOOL_A_FLOW_AH6 = 11,\n\tETHTOOL_A_FLOW_ESP4 = 12,\n\tETHTOOL_A_FLOW_ESP6 = 13,\n\tETHTOOL_A_FLOW_AH_ESP4 = 14,\n\tETHTOOL_A_FLOW_AH_ESP6 = 15,\n\tETHTOOL_A_FLOW_GTPU4 = 16,\n\tETHTOOL_A_FLOW_GTPU6 = 17,\n\tETHTOOL_A_FLOW_GTPC4 = 18,\n\tETHTOOL_A_FLOW_GTPC6 = 19,\n\tETHTOOL_A_FLOW_GTPC_TEID4 = 20,\n\tETHTOOL_A_FLOW_GTPC_TEID6 = 21,\n\tETHTOOL_A_FLOW_GTPU_EH4 = 22,\n\tETHTOOL_A_FLOW_GTPU_EH6 = 23,\n\tETHTOOL_A_FLOW_GTPU_UL4 = 24,\n\tETHTOOL_A_FLOW_GTPU_UL6 = 25,\n\tETHTOOL_A_FLOW_GTPU_DL4 = 26,\n\tETHTOOL_A_FLOW_GTPU_DL6 = 27,\n\t__ETHTOOL_A_FLOW_CNT = 28,\n\tETHTOOL_A_FLOW_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\tETHTOOL_A_HEADER_PHY_INDEX = 4,\n\t__ETHTOOL_A_HEADER_CNT = 5,\n\tETHTOOL_A_HEADER_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_IRQ_MODERATION_UNSPEC = 0,\n\tETHTOOL_A_IRQ_MODERATION_USEC = 1,\n\tETHTOOL_A_IRQ_MODERATION_PKTS = 2,\n\tETHTOOL_A_IRQ_MODERATION_COMPS = 3,\n\t__ETHTOOL_A_IRQ_MODERATION_CNT = 4,\n\tETHTOOL_A_IRQ_MODERATION_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\tETHTOOL_A_LINKMODES_LANES = 9,\n\tETHTOOL_A_LINKMODES_RATE_MATCHING = 10,\n\t__ETHTOOL_A_LINKMODES_CNT = 11,\n\tETHTOOL_A_LINKMODES_MAX = 10,\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\tETHTOOL_A_LINKSTATE_EXT_STATE = 5,\n\tETHTOOL_A_LINKSTATE_EXT_SUBSTATE = 6,\n\tETHTOOL_A_LINKSTATE_EXT_DOWN_CNT = 7,\n\t__ETHTOOL_A_LINKSTATE_CNT = 8,\n\tETHTOOL_A_LINKSTATE_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_STAT_UNSPEC = 0,\n\tETHTOOL_A_MM_STAT_PAD = 1,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_ERRORS = 2,\n\tETHTOOL_A_MM_STAT_SMD_ERRORS = 3,\n\tETHTOOL_A_MM_STAT_REASSEMBLY_OK = 4,\n\tETHTOOL_A_MM_STAT_RX_FRAG_COUNT = 5,\n\tETHTOOL_A_MM_STAT_TX_FRAG_COUNT = 6,\n\tETHTOOL_A_MM_STAT_HOLD_COUNT = 7,\n\t__ETHTOOL_A_MM_STAT_CNT = 8,\n\tETHTOOL_A_MM_STAT_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MM_UNSPEC = 0,\n\tETHTOOL_A_MM_HEADER = 1,\n\tETHTOOL_A_MM_PMAC_ENABLED = 2,\n\tETHTOOL_A_MM_TX_ENABLED = 3,\n\tETHTOOL_A_MM_TX_ACTIVE = 4,\n\tETHTOOL_A_MM_TX_MIN_FRAG_SIZE = 5,\n\tETHTOOL_A_MM_RX_MIN_FRAG_SIZE = 6,\n\tETHTOOL_A_MM_VERIFY_ENABLED = 7,\n\tETHTOOL_A_MM_VERIFY_STATUS = 8,\n\tETHTOOL_A_MM_VERIFY_TIME = 9,\n\tETHTOOL_A_MM_MAX_VERIFY_TIME = 10,\n\tETHTOOL_A_MM_STATS = 11,\n\t__ETHTOOL_A_MM_CNT = 12,\n\tETHTOOL_A_MM_MAX = 11,\n};\n\nenum {\n\tETHTOOL_A_MODULE_EEPROM_UNSPEC = 0,\n\tETHTOOL_A_MODULE_EEPROM_HEADER = 1,\n\tETHTOOL_A_MODULE_EEPROM_OFFSET = 2,\n\tETHTOOL_A_MODULE_EEPROM_LENGTH = 3,\n\tETHTOOL_A_MODULE_EEPROM_PAGE = 4,\n\tETHTOOL_A_MODULE_EEPROM_BANK = 5,\n\tETHTOOL_A_MODULE_EEPROM_I2C_ADDRESS = 6,\n\tETHTOOL_A_MODULE_EEPROM_DATA = 7,\n\t__ETHTOOL_A_MODULE_EEPROM_CNT = 8,\n\tETHTOOL_A_MODULE_EEPROM_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_FW_FLASH_UNSPEC = 0,\n\tETHTOOL_A_MODULE_FW_FLASH_HEADER = 1,\n\tETHTOOL_A_MODULE_FW_FLASH_FILE_NAME = 2,\n\tETHTOOL_A_MODULE_FW_FLASH_PASSWORD = 3,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS = 4,\n\tETHTOOL_A_MODULE_FW_FLASH_STATUS_MSG = 5,\n\tETHTOOL_A_MODULE_FW_FLASH_DONE = 6,\n\tETHTOOL_A_MODULE_FW_FLASH_TOTAL = 7,\n\t__ETHTOOL_A_MODULE_FW_FLASH_CNT = 8,\n\tETHTOOL_A_MODULE_FW_FLASH_MAX = 7,\n};\n\nenum {\n\tETHTOOL_A_MODULE_UNSPEC = 0,\n\tETHTOOL_A_MODULE_HEADER = 1,\n\tETHTOOL_A_MODULE_POWER_MODE_POLICY = 2,\n\tETHTOOL_A_MODULE_POWER_MODE = 3,\n\t__ETHTOOL_A_MODULE_CNT = 4,\n\tETHTOOL_A_MODULE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_CAPABILITIES_REFRESH_RATE_PS = 3,\n\tETHTOOL_A_MSE_CAPABILITIES_NUM_SYMBOLS = 4,\n\t__ETHTOOL_A_MSE_CAPABILITIES_CNT = 5,\n\tETHTOOL_A_MSE_CAPABILITIES_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_MSE_HEADER = 1,\n\tETHTOOL_A_MSE_CAPABILITIES = 2,\n\tETHTOOL_A_MSE_CHANNEL_A = 3,\n\tETHTOOL_A_MSE_CHANNEL_B = 4,\n\tETHTOOL_A_MSE_CHANNEL_C = 5,\n\tETHTOOL_A_MSE_CHANNEL_D = 6,\n\tETHTOOL_A_MSE_WORST_CHANNEL = 7,\n\tETHTOOL_A_MSE_LINK = 8,\n\t__ETHTOOL_A_MSE_CNT = 9,\n\tETHTOOL_A_MSE_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_MSE_SNAPSHOT_AVERAGE_MSE = 1,\n\tETHTOOL_A_MSE_SNAPSHOT_PEAK_MSE = 2,\n\tETHTOOL_A_MSE_SNAPSHOT_WORST_PEAK_MSE = 3,\n\t__ETHTOOL_A_MSE_SNAPSHOT_CNT = 4,\n\tETHTOOL_A_MSE_SNAPSHOT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_STAT_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_STAT_PAD = 1,\n\tETHTOOL_A_PAUSE_STAT_TX_FRAMES = 2,\n\tETHTOOL_A_PAUSE_STAT_RX_FRAMES = 3,\n\t__ETHTOOL_A_PAUSE_STAT_CNT = 4,\n\tETHTOOL_A_PAUSE_STAT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\tETHTOOL_A_PAUSE_STATS = 5,\n\tETHTOOL_A_PAUSE_STATS_SRC = 6,\n\t__ETHTOOL_A_PAUSE_CNT = 7,\n\tETHTOOL_A_PAUSE_MAX = 6,\n};\n\nenum {\n\tETHTOOL_A_PHC_VCLOCKS_UNSPEC = 0,\n\tETHTOOL_A_PHC_VCLOCKS_HEADER = 1,\n\tETHTOOL_A_PHC_VCLOCKS_NUM = 2,\n\tETHTOOL_A_PHC_VCLOCKS_INDEX = 3,\n\t__ETHTOOL_A_PHC_VCLOCKS_CNT = 4,\n\tETHTOOL_A_PHC_VCLOCKS_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_PHY_UNSPEC = 0,\n\tETHTOOL_A_PHY_HEADER = 1,\n\tETHTOOL_A_PHY_INDEX = 2,\n\tETHTOOL_A_PHY_DRVNAME = 3,\n\tETHTOOL_A_PHY_NAME = 4,\n\tETHTOOL_A_PHY_UPSTREAM_TYPE = 5,\n\tETHTOOL_A_PHY_UPSTREAM_INDEX = 6,\n\tETHTOOL_A_PHY_UPSTREAM_SFP_NAME = 7,\n\tETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME = 8,\n\t__ETHTOOL_A_PHY_CNT = 9,\n\tETHTOOL_A_PHY_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_PLCA_UNSPEC = 0,\n\tETHTOOL_A_PLCA_HEADER = 1,\n\tETHTOOL_A_PLCA_VERSION = 2,\n\tETHTOOL_A_PLCA_ENABLED = 3,\n\tETHTOOL_A_PLCA_STATUS = 4,\n\tETHTOOL_A_PLCA_NODE_CNT = 5,\n\tETHTOOL_A_PLCA_NODE_ID = 6,\n\tETHTOOL_A_PLCA_TO_TMR = 7,\n\tETHTOOL_A_PLCA_BURST_CNT = 8,\n\tETHTOOL_A_PLCA_BURST_TMR = 9,\n\t__ETHTOOL_A_PLCA_CNT = 10,\n\tETHTOOL_A_PLCA_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PROFILE_UNSPEC = 0,\n\tETHTOOL_A_PROFILE_IRQ_MODERATION = 1,\n\t__ETHTOOL_A_PROFILE_CNT = 2,\n\tETHTOOL_A_PROFILE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_PSE_NTF_HEADER = 1,\n\tETHTOOL_A_PSE_NTF_EVENTS = 2,\n\t__ETHTOOL_A_PSE_NTF_CNT = 3,\n\tETHTOOL_A_PSE_NTF_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_PSE_UNSPEC = 0,\n\tETHTOOL_A_PSE_HEADER = 1,\n\tETHTOOL_A_PODL_PSE_ADMIN_STATE = 2,\n\tETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3,\n\tETHTOOL_A_PODL_PSE_PW_D_STATUS = 4,\n\tETHTOOL_A_C33_PSE_ADMIN_STATE = 5,\n\tETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6,\n\tETHTOOL_A_C33_PSE_PW_D_STATUS = 7,\n\tETHTOOL_A_C33_PSE_PW_CLASS = 8,\n\tETHTOOL_A_C33_PSE_ACTUAL_PW = 9,\n\tETHTOOL_A_C33_PSE_EXT_STATE = 10,\n\tETHTOOL_A_C33_PSE_EXT_SUBSTATE = 11,\n\tETHTOOL_A_C33_PSE_AVAIL_PW_LIMIT = 12,\n\tETHTOOL_A_C33_PSE_PW_LIMIT_RANGES = 13,\n\tETHTOOL_A_PSE_PW_D_ID = 14,\n\tETHTOOL_A_PSE_PRIO_MAX = 15,\n\tETHTOOL_A_PSE_PRIO = 16,\n\t__ETHTOOL_A_PSE_CNT = 17,\n\tETHTOOL_A_PSE_MAX = 16,\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\tETHTOOL_A_RINGS_RX_BUF_LEN = 10,\n\tETHTOOL_A_RINGS_TCP_DATA_SPLIT = 11,\n\tETHTOOL_A_RINGS_CQE_SIZE = 12,\n\tETHTOOL_A_RINGS_TX_PUSH = 13,\n\tETHTOOL_A_RINGS_RX_PUSH = 14,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN = 15,\n\tETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAX = 16,\n\tETHTOOL_A_RINGS_HDS_THRESH = 17,\n\tETHTOOL_A_RINGS_HDS_THRESH_MAX = 18,\n\t__ETHTOOL_A_RINGS_CNT = 19,\n\tETHTOOL_A_RINGS_MAX = 18,\n};\n\nenum {\n\tETHTOOL_A_RSS_UNSPEC = 0,\n\tETHTOOL_A_RSS_HEADER = 1,\n\tETHTOOL_A_RSS_CONTEXT = 2,\n\tETHTOOL_A_RSS_HFUNC = 3,\n\tETHTOOL_A_RSS_INDIR = 4,\n\tETHTOOL_A_RSS_HKEY = 5,\n\tETHTOOL_A_RSS_INPUT_XFRM = 6,\n\tETHTOOL_A_RSS_START_CONTEXT = 7,\n\tETHTOOL_A_RSS_FLOW_HASH = 8,\n\t__ETHTOOL_A_RSS_CNT = 9,\n\tETHTOOL_A_RSS_MAX = 8,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_CTRL_3_TX = 0,\n\tETHTOOL_A_STATS_ETH_CTRL_4_RX = 1,\n\tETHTOOL_A_STATS_ETH_CTRL_5_RX_UNSUP = 2,\n\t__ETHTOOL_A_STATS_ETH_CTRL_CNT = 3,\n\tETHTOOL_A_STATS_ETH_CTRL_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_MAC_2_TX_PKT = 0,\n\tETHTOOL_A_STATS_ETH_MAC_3_SINGLE_COL = 1,\n\tETHTOOL_A_STATS_ETH_MAC_4_MULTI_COL = 2,\n\tETHTOOL_A_STATS_ETH_MAC_5_RX_PKT = 3,\n\tETHTOOL_A_STATS_ETH_MAC_6_FCS_ERR = 4,\n\tETHTOOL_A_STATS_ETH_MAC_7_ALIGN_ERR = 5,\n\tETHTOOL_A_STATS_ETH_MAC_8_TX_BYTES = 6,\n\tETHTOOL_A_STATS_ETH_MAC_9_TX_DEFER = 7,\n\tETHTOOL_A_STATS_ETH_MAC_10_LATE_COL = 8,\n\tETHTOOL_A_STATS_ETH_MAC_11_XS_COL = 9,\n\tETHTOOL_A_STATS_ETH_MAC_12_TX_INT_ERR = 10,\n\tETHTOOL_A_STATS_ETH_MAC_13_CS_ERR = 11,\n\tETHTOOL_A_STATS_ETH_MAC_14_RX_BYTES = 12,\n\tETHTOOL_A_STATS_ETH_MAC_15_RX_INT_ERR = 13,\n\tETHTOOL_A_STATS_ETH_MAC_18_TX_MCAST = 14,\n\tETHTOOL_A_STATS_ETH_MAC_19_TX_BCAST = 15,\n\tETHTOOL_A_STATS_ETH_MAC_20_XS_DEFER = 16,\n\tETHTOOL_A_STATS_ETH_MAC_21_RX_MCAST = 17,\n\tETHTOOL_A_STATS_ETH_MAC_22_RX_BCAST = 18,\n\tETHTOOL_A_STATS_ETH_MAC_23_IR_LEN_ERR = 19,\n\tETHTOOL_A_STATS_ETH_MAC_24_OOR_LEN = 20,\n\tETHTOOL_A_STATS_ETH_MAC_25_TOO_LONG_ERR = 21,\n\t__ETHTOOL_A_STATS_ETH_MAC_CNT = 22,\n\tETHTOOL_A_STATS_ETH_MAC_MAX = 21,\n};\n\nenum {\n\tETHTOOL_A_STATS_ETH_PHY_5_SYM_ERR = 0,\n\t__ETHTOOL_A_STATS_ETH_PHY_CNT = 1,\n\tETHTOOL_A_STATS_ETH_PHY_MAX = 0,\n};\n\nenum {\n\tETHTOOL_A_STATS_GRP_UNSPEC = 0,\n\tETHTOOL_A_STATS_GRP_PAD = 1,\n\tETHTOOL_A_STATS_GRP_ID = 2,\n\tETHTOOL_A_STATS_GRP_SS_ID = 3,\n\tETHTOOL_A_STATS_GRP_STAT = 4,\n\tETHTOOL_A_STATS_GRP_HIST_RX = 5,\n\tETHTOOL_A_STATS_GRP_HIST_TX = 6,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_LOW = 7,\n\tETHTOOL_A_STATS_GRP_HIST_BKT_HI = 8,\n\tETHTOOL_A_STATS_GRP_HIST_VAL = 9,\n\t__ETHTOOL_A_STATS_GRP_CNT = 10,\n\tETHTOOL_A_STATS_GRP_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_STATS_PHY_RX_PKTS = 0,\n\tETHTOOL_A_STATS_PHY_RX_BYTES = 1,\n\tETHTOOL_A_STATS_PHY_RX_ERRORS = 2,\n\tETHTOOL_A_STATS_PHY_TX_PKTS = 3,\n\tETHTOOL_A_STATS_PHY_TX_BYTES = 4,\n\tETHTOOL_A_STATS_PHY_TX_ERRORS = 5,\n\t__ETHTOOL_A_STATS_PHY_CNT = 6,\n\tETHTOOL_A_STATS_PHY_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STATS_RMON_UNDERSIZE = 0,\n\tETHTOOL_A_STATS_RMON_OVERSIZE = 1,\n\tETHTOOL_A_STATS_RMON_FRAG = 2,\n\tETHTOOL_A_STATS_RMON_JABBER = 3,\n\t__ETHTOOL_A_STATS_RMON_CNT = 4,\n\tETHTOOL_A_STATS_RMON_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STATS_UNSPEC = 0,\n\tETHTOOL_A_STATS_PAD = 1,\n\tETHTOOL_A_STATS_HEADER = 2,\n\tETHTOOL_A_STATS_GROUPS = 3,\n\tETHTOOL_A_STATS_GRP = 4,\n\tETHTOOL_A_STATS_SRC = 5,\n\t__ETHTOOL_A_STATS_CNT = 6,\n\tETHTOOL_A_STATS_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TSCONFIG_UNSPEC = 0,\n\tETHTOOL_A_TSCONFIG_HEADER = 1,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDER = 2,\n\tETHTOOL_A_TSCONFIG_TX_TYPES = 3,\n\tETHTOOL_A_TSCONFIG_RX_FILTERS = 4,\n\tETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGS = 5,\n\t__ETHTOOL_A_TSCONFIG_CNT = 6,\n\tETHTOOL_A_TSCONFIG_MAX = 5,\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\tETHTOOL_A_TSINFO_STATS = 6,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PROVIDER = 7,\n\tETHTOOL_A_TSINFO_HWTSTAMP_SOURCE = 8,\n\tETHTOOL_A_TSINFO_HWTSTAMP_PHYINDEX = 9,\n\t__ETHTOOL_A_TSINFO_CNT = 10,\n\tETHTOOL_A_TSINFO_MAX = 9,\n};\n\nenum {\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPEC = 0,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEX = 1,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIER = 2,\n\t__ETHTOOL_A_TS_HWTSTAMP_PROVIDER_CNT = 3,\n\tETHTOOL_A_TS_HWTSTAMP_PROVIDER_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TS_STAT_UNSPEC = 0,\n\tETHTOOL_A_TS_STAT_TX_PKTS = 1,\n\tETHTOOL_A_TS_STAT_TX_LOST = 2,\n\tETHTOOL_A_TS_STAT_TX_ERR = 3,\n\tETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMED = 4,\n\t__ETHTOOL_A_TS_STAT_CNT = 5,\n\tETHTOOL_A_TS_STAT_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_INFO_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_INFO_HEADER = 1,\n\tETHTOOL_A_TUNNEL_INFO_UDP_PORTS = 2,\n\t__ETHTOOL_A_TUNNEL_INFO_CNT = 3,\n\tETHTOOL_A_TUNNEL_INFO_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_PORT = 1,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE = 2,\n\t__ETHTOOL_A_TUNNEL_UDP_ENTRY_CNT = 3,\n\tETHTOOL_A_TUNNEL_UDP_ENTRY_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_TABLE_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_SIZE = 1,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_TYPES = 2,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY = 3,\n\t__ETHTOOL_A_TUNNEL_UDP_TABLE_CNT = 4,\n\tETHTOOL_A_TUNNEL_UDP_TABLE_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_TUNNEL_UDP_UNSPEC = 0,\n\tETHTOOL_A_TUNNEL_UDP_TABLE = 1,\n\t__ETHTOOL_A_TUNNEL_UDP_CNT = 2,\n\tETHTOOL_A_TUNNEL_UDP_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\tETHTOOL_MSG_TUNNEL_INFO_GET_REPLY = 29,\n\tETHTOOL_MSG_FEC_GET_REPLY = 30,\n\tETHTOOL_MSG_FEC_NTF = 31,\n\tETHTOOL_MSG_MODULE_EEPROM_GET_REPLY = 32,\n\tETHTOOL_MSG_STATS_GET_REPLY = 33,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET_REPLY = 34,\n\tETHTOOL_MSG_MODULE_GET_REPLY = 35,\n\tETHTOOL_MSG_MODULE_NTF = 36,\n\tETHTOOL_MSG_PSE_GET_REPLY = 37,\n\tETHTOOL_MSG_RSS_GET_REPLY = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG_REPLY = 39,\n\tETHTOOL_MSG_PLCA_GET_STATUS_REPLY = 40,\n\tETHTOOL_MSG_PLCA_NTF = 41,\n\tETHTOOL_MSG_MM_GET_REPLY = 42,\n\tETHTOOL_MSG_MM_NTF = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_NTF = 44,\n\tETHTOOL_MSG_PHY_GET_REPLY = 45,\n\tETHTOOL_MSG_PHY_NTF = 46,\n\tETHTOOL_MSG_TSCONFIG_GET_REPLY = 47,\n\tETHTOOL_MSG_TSCONFIG_SET_REPLY = 48,\n\tETHTOOL_MSG_PSE_NTF = 49,\n\tETHTOOL_MSG_RSS_NTF = 50,\n\tETHTOOL_MSG_RSS_CREATE_ACT_REPLY = 51,\n\tETHTOOL_MSG_RSS_CREATE_NTF = 52,\n\tETHTOOL_MSG_RSS_DELETE_NTF = 53,\n\tETHTOOL_MSG_MSE_GET_REPLY = 54,\n\t__ETHTOOL_MSG_KERNEL_CNT = 55,\n\tETHTOOL_MSG_KERNEL_MAX = 54,\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\tETHTOOL_MSG_TUNNEL_INFO_GET = 28,\n\tETHTOOL_MSG_FEC_GET = 29,\n\tETHTOOL_MSG_FEC_SET = 30,\n\tETHTOOL_MSG_MODULE_EEPROM_GET = 31,\n\tETHTOOL_MSG_STATS_GET = 32,\n\tETHTOOL_MSG_PHC_VCLOCKS_GET = 33,\n\tETHTOOL_MSG_MODULE_GET = 34,\n\tETHTOOL_MSG_MODULE_SET = 35,\n\tETHTOOL_MSG_PSE_GET = 36,\n\tETHTOOL_MSG_PSE_SET = 37,\n\tETHTOOL_MSG_RSS_GET = 38,\n\tETHTOOL_MSG_PLCA_GET_CFG = 39,\n\tETHTOOL_MSG_PLCA_SET_CFG = 40,\n\tETHTOOL_MSG_PLCA_GET_STATUS = 41,\n\tETHTOOL_MSG_MM_GET = 42,\n\tETHTOOL_MSG_MM_SET = 43,\n\tETHTOOL_MSG_MODULE_FW_FLASH_ACT = 44,\n\tETHTOOL_MSG_PHY_GET = 45,\n\tETHTOOL_MSG_TSCONFIG_GET = 46,\n\tETHTOOL_MSG_TSCONFIG_SET = 47,\n\tETHTOOL_MSG_RSS_SET = 48,\n\tETHTOOL_MSG_RSS_CREATE_ACT = 49,\n\tETHTOOL_MSG_RSS_DELETE_ACT = 50,\n\tETHTOOL_MSG_MSE_GET = 51,\n\t__ETHTOOL_MSG_USER_CNT = 52,\n\tETHTOOL_MSG_USER_MAX = 51,\n};\n\nenum {\n\tETHTOOL_STATS_ETH_PHY = 0,\n\tETHTOOL_STATS_ETH_MAC = 1,\n\tETHTOOL_STATS_ETH_CTRL = 2,\n\tETHTOOL_STATS_RMON = 3,\n\tETHTOOL_STATS_PHY = 4,\n\t__ETHTOOL_STATS_CNT = 5,\n};\n\nenum {\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN = 0,\n\tETHTOOL_UDP_TUNNEL_TYPE_GENEVE = 1,\n\tETHTOOL_UDP_TUNNEL_TYPE_VXLAN_GPE = 2,\n\t__ETHTOOL_UDP_TUNNEL_TYPE_CNT = 3,\n\tETHTOOL_UDP_TUNNEL_TYPE_MAX = 2,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nenum {\n\tEVENTFS_SAVE_MODE = 65536,\n\tEVENTFS_SAVE_UID = 131072,\n\tEVENTFS_SAVE_GID = 262144,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_DISABLED = 32,\n\tEVENT_FILE_FL_TRIGGER_MODE = 64,\n\tEVENT_FILE_FL_TRIGGER_COND = 128,\n\tEVENT_FILE_FL_PID_FILTER = 256,\n\tEVENT_FILE_FL_WAS_ENABLED = 512,\n\tEVENT_FILE_FL_FREED = 1024,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 5,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 7,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 8,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 9,\n\tEVENT_FILE_FL_FREED_BIT = 10,\n};\n\nenum {\n\tEVENT_TRIGGER_FL_PROBE = 1,\n\tEVENT_TRIGGER_FL_COUNT = 2,\n};\n\nenum {\n\tEXT4_FC_REASON_XATTR = 0,\n\tEXT4_FC_REASON_CROSS_RENAME = 1,\n\tEXT4_FC_REASON_JOURNAL_FLAG_CHANGE = 2,\n\tEXT4_FC_REASON_NOMEM = 3,\n\tEXT4_FC_REASON_SWAP_BOOT = 4,\n\tEXT4_FC_REASON_RESIZE = 5,\n\tEXT4_FC_REASON_RENAME_DIR = 6,\n\tEXT4_FC_REASON_FALLOC_RANGE = 7,\n\tEXT4_FC_REASON_INODE_JOURNAL_DATA = 8,\n\tEXT4_FC_REASON_ENCRYPTED_FILENAME = 9,\n\tEXT4_FC_REASON_MIGRATE = 10,\n\tEXT4_FC_REASON_VERITY = 11,\n\tEXT4_FC_REASON_MOVE_EXT = 12,\n\tEXT4_FC_REASON_MAX = 13,\n};\n\nenum {\n\tEXT4_FC_STATUS_OK = 0,\n\tEXT4_FC_STATUS_INELIGIBLE = 1,\n\tEXT4_FC_STATUS_SKIPPED = 2,\n\tEXT4_FC_STATUS_FAILED = 3,\n};\n\nenum {\n\tEXT4_FLAGS_RESIZING = 0,\n\tEXT4_FLAGS_SHUTDOWN = 1,\n\tEXT4_FLAGS_BDEV_IS_DAX = 2,\n\tEXT4_FLAGS_EMERGENCY_RO = 3,\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nenum {\n\tEXT4_MF_MNTDIR_SAMPLED = 0,\n\tEXT4_MF_FC_INELIGIBLE = 1,\n\tEXT4_MF_JOURNAL_DESTROY = 2,\n};\n\nenum {\n\tEXT4_STATE_NEW = 0,\n\tEXT4_STATE_XATTR = 1,\n\tEXT4_STATE_NO_EXPAND = 2,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 3,\n\tEXT4_STATE_EXT_MIGRATE = 4,\n\tEXT4_STATE_NEWENTRY = 5,\n\tEXT4_STATE_MAY_INLINE_DATA = 6,\n\tEXT4_STATE_EXT_PRECACHED = 7,\n\tEXT4_STATE_LUSTRE_EA_INODE = 8,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 9,\n\tEXT4_STATE_FC_COMMITTING = 10,\n\tEXT4_STATE_FC_FLUSHING_DATA = 11,\n\tEXT4_STATE_ORPHAN_FILE = 12,\n};\n\nenum {\n\tFAST_W_CNT = 16,\n};\n\nenum {\n\tFATTR4_CLONE_BLKSIZE = 77,\n\tFATTR4_SPACE_FREED = 78,\n\tFATTR4_CHANGE_ATTR_TYPE = 79,\n\tFATTR4_SEC_LABEL = 80,\n};\n\nenum {\n\tFATTR4_DIR_NOTIF_DELAY = 56,\n\tFATTR4_DIRENT_NOTIF_DELAY = 57,\n\tFATTR4_DACL = 58,\n\tFATTR4_SACL = 59,\n\tFATTR4_CHANGE_POLICY = 60,\n\tFATTR4_FS_STATUS = 61,\n\tFATTR4_FS_LAYOUT_TYPES = 62,\n\tFATTR4_LAYOUT_HINT = 63,\n\tFATTR4_LAYOUT_TYPES = 64,\n\tFATTR4_LAYOUT_BLKSIZE = 65,\n\tFATTR4_LAYOUT_ALIGNMENT = 66,\n\tFATTR4_FS_LOCATIONS_INFO = 67,\n\tFATTR4_MDSTHRESHOLD = 68,\n\tFATTR4_RETENTION_GET = 69,\n\tFATTR4_RETENTION_SET = 70,\n\tFATTR4_RETENTEVT_GET = 71,\n\tFATTR4_RETENTEVT_SET = 72,\n\tFATTR4_RETENTION_HOLD = 73,\n\tFATTR4_MODE_SET_MASKED = 74,\n\tFATTR4_SUPPATTR_EXCLCREAT = 75,\n\tFATTR4_FS_CHARSET_CAP = 76,\n};\n\nenum {\n\tFATTR4_MODE_UMASK = 81,\n};\n\nenum {\n\tFATTR4_OPEN_ARGUMENTS = 86,\n};\n\nenum {\n\tFATTR4_SUPPORTED_ATTRS = 0,\n\tFATTR4_TYPE = 1,\n\tFATTR4_FH_EXPIRE_TYPE = 2,\n\tFATTR4_CHANGE = 3,\n\tFATTR4_SIZE = 4,\n\tFATTR4_LINK_SUPPORT = 5,\n\tFATTR4_SYMLINK_SUPPORT = 6,\n\tFATTR4_NAMED_ATTR = 7,\n\tFATTR4_FSID = 8,\n\tFATTR4_UNIQUE_HANDLES = 9,\n\tFATTR4_LEASE_TIME = 10,\n\tFATTR4_RDATTR_ERROR = 11,\n\tFATTR4_ACL = 12,\n\tFATTR4_ACLSUPPORT = 13,\n\tFATTR4_ARCHIVE = 14,\n\tFATTR4_CANSETTIME = 15,\n\tFATTR4_CASE_INSENSITIVE = 16,\n\tFATTR4_CASE_PRESERVING = 17,\n\tFATTR4_CHOWN_RESTRICTED = 18,\n\tFATTR4_FILEHANDLE = 19,\n\tFATTR4_FILEID = 20,\n\tFATTR4_FILES_AVAIL = 21,\n\tFATTR4_FILES_FREE = 22,\n\tFATTR4_FILES_TOTAL = 23,\n\tFATTR4_FS_LOCATIONS = 24,\n\tFATTR4_HIDDEN = 25,\n\tFATTR4_HOMOGENEOUS = 26,\n\tFATTR4_MAXFILESIZE = 27,\n\tFATTR4_MAXLINK = 28,\n\tFATTR4_MAXNAME = 29,\n\tFATTR4_MAXREAD = 30,\n\tFATTR4_MAXWRITE = 31,\n\tFATTR4_MIMETYPE = 32,\n\tFATTR4_MODE = 33,\n\tFATTR4_NO_TRUNC = 34,\n\tFATTR4_NUMLINKS = 35,\n\tFATTR4_OWNER = 36,\n\tFATTR4_OWNER_GROUP = 37,\n\tFATTR4_QUOTA_AVAIL_HARD = 38,\n\tFATTR4_QUOTA_AVAIL_SOFT = 39,\n\tFATTR4_QUOTA_USED = 40,\n\tFATTR4_RAWDEV = 41,\n\tFATTR4_SPACE_AVAIL = 42,\n\tFATTR4_SPACE_FREE = 43,\n\tFATTR4_SPACE_TOTAL = 44,\n\tFATTR4_SPACE_USED = 45,\n\tFATTR4_SYSTEM = 46,\n\tFATTR4_TIME_ACCESS = 47,\n\tFATTR4_TIME_ACCESS_SET = 48,\n\tFATTR4_TIME_BACKUP = 49,\n\tFATTR4_TIME_CREATE = 50,\n\tFATTR4_TIME_DELTA = 51,\n\tFATTR4_TIME_METADATA = 52,\n\tFATTR4_TIME_MODIFY = 53,\n\tFATTR4_TIME_MODIFY_SET = 54,\n\tFATTR4_MOUNTED_ON_FILEID = 55,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_ACCESS = 84,\n};\n\nenum {\n\tFATTR4_TIME_DELEG_MODIFY = 85,\n};\n\nenum {\n\tFATTR4_XATTR_SUPPORT = 82,\n};\n\nenum {\n\tFBCON_LOGO_CANSHOW = -1,\n\tFBCON_LOGO_DRAW = -2,\n\tFBCON_LOGO_DONTSHOW = -3,\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nenum {\n\tFD_NEED_TWADDLE_BIT = 0,\n\tFD_VERIFY_BIT = 1,\n\tFD_DISK_NEWCHANGE_BIT = 2,\n\tFD_UNUSED_BIT = 3,\n\tFD_DISK_CHANGED_BIT = 4,\n\tFD_DISK_WRITABLE_BIT = 5,\n\tFD_OPEN_SHOULD_FAIL_BIT = 6,\n};\n\nenum {\n\tFGRAPH_TYPE_RESERVED = 0,\n\tFGRAPH_TYPE_BITMAP = 1,\n\tFGRAPH_TYPE_DATA = 2,\n};\n\nenum {\n\tFIB6_NO_SERNUM_CHANGE = 0,\n};\n\nenum {\n\tFILEID_HIGH_OFF = 0,\n\tFILEID_LOW_OFF = 1,\n\tFILE_I_TYPE_OFF = 2,\n\tEMBED_FH_OFF = 3,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_RDYN_STRING = 3,\n\tFILTER_PTR_STRING = 4,\n\tFILTER_TRACE_FN = 5,\n\tFILTER_CPUMASK = 6,\n\tFILTER_COMM = 7,\n\tFILTER_CPU = 8,\n\tFILTER_STACKTRACE = 9,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_MISSING_BRACE_OPEN = 5,\n\tFILT_ERR_MISSING_BRACE_CLOSE = 6,\n\tFILT_ERR_OPERAND_TOO_LONG = 7,\n\tFILT_ERR_EXPECT_STRING = 8,\n\tFILT_ERR_EXPECT_DIGIT = 9,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 10,\n\tFILT_ERR_FIELD_NOT_FOUND = 11,\n\tFILT_ERR_ILLEGAL_INTVAL = 12,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 13,\n\tFILT_ERR_TOO_MANY_PREDS = 14,\n\tFILT_ERR_INVALID_FILTER = 15,\n\tFILT_ERR_INVALID_CPULIST = 16,\n\tFILT_ERR_IP_FIELD_ONLY = 17,\n\tFILT_ERR_INVALID_VALUE = 18,\n\tFILT_ERR_NO_FUNCTION = 19,\n\tFILT_ERR_ERRNO = 20,\n\tFILT_ERR_NO_FILTER = 21,\n};\n\nenum {\n\tFLAGS_FILL_FULL = 268435456,\n\tFLAGS_FILL_START = 536870912,\n\tFLAGS_FILL_END = 805306368,\n};\n\nenum {\n\tFOLL_TOUCH = 65536,\n\tFOLL_TRIED = 131072,\n\tFOLL_REMOTE = 262144,\n\tFOLL_PIN = 524288,\n\tFOLL_FAST_ONLY = 1048576,\n\tFOLL_UNLOCKABLE = 2097152,\n\tFOLL_MADV_POPULATE = 4194304,\n};\n\nenum {\n\tFOLL_WRITE = 1,\n\tFOLL_GET = 2,\n\tFOLL_DUMP = 4,\n\tFOLL_FORCE = 8,\n\tFOLL_NOWAIT = 16,\n\tFOLL_NOFAULT = 32,\n\tFOLL_HWPOISON = 64,\n\tFOLL_ANON = 128,\n\tFOLL_LONGTERM = 256,\n\tFOLL_SPLIT_PMD = 512,\n\tFOLL_PCI_P2PDMA = 1024,\n\tFOLL_INTERRUPTIBLE = 2048,\n\tFOLL_HONOR_NUMA_FAULT = 4096,\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\nenum {\n\tFR_PERCPU = 0,\n\tFR_ATOMIC = 1,\n};\n\nenum {\n\tFTRACE_FL_ENABLED = 2147483648,\n\tFTRACE_FL_REGS = 1073741824,\n\tFTRACE_FL_REGS_EN = 536870912,\n\tFTRACE_FL_TRAMP = 268435456,\n\tFTRACE_FL_TRAMP_EN = 134217728,\n\tFTRACE_FL_IPMODIFY = 67108864,\n\tFTRACE_FL_DISABLED = 33554432,\n\tFTRACE_FL_DIRECT = 16777216,\n\tFTRACE_FL_DIRECT_EN = 8388608,\n\tFTRACE_FL_CALL_OPS = 4194304,\n\tFTRACE_FL_CALL_OPS_EN = 2097152,\n\tFTRACE_FL_TOUCHED = 1048576,\n\tFTRACE_FL_MODIFIED = 524288,\n};\n\nenum {\n\tFTRACE_HASH_FL_MOD = 1,\n};\n\nenum {\n\tFTRACE_ITER_FILTER = 1,\n\tFTRACE_ITER_NOTRACE = 2,\n\tFTRACE_ITER_PRINTALL = 4,\n\tFTRACE_ITER_DO_PROBES = 8,\n\tFTRACE_ITER_PROBE = 16,\n\tFTRACE_ITER_MOD = 32,\n\tFTRACE_ITER_ENABLED = 64,\n\tFTRACE_ITER_TOUCHED = 128,\n\tFTRACE_ITER_ADDRS = 256,\n};\n\nenum {\n\tFTRACE_MODIFY_ENABLE_FL = 1,\n\tFTRACE_MODIFY_MAY_SLEEP_FL = 2,\n};\n\nenum {\n\tFTRACE_OPS_FL_ENABLED = 1,\n\tFTRACE_OPS_FL_DYNAMIC = 2,\n\tFTRACE_OPS_FL_SAVE_REGS = 4,\n\tFTRACE_OPS_FL_SAVE_REGS_IF_SUPPORTED = 8,\n\tFTRACE_OPS_FL_RECURSION = 16,\n\tFTRACE_OPS_FL_STUB = 32,\n\tFTRACE_OPS_FL_INITIALIZED = 64,\n\tFTRACE_OPS_FL_DELETED = 128,\n\tFTRACE_OPS_FL_ADDING = 256,\n\tFTRACE_OPS_FL_REMOVING = 512,\n\tFTRACE_OPS_FL_MODIFYING = 1024,\n\tFTRACE_OPS_FL_ALLOC_TRAMP = 2048,\n\tFTRACE_OPS_FL_IPMODIFY = 4096,\n\tFTRACE_OPS_FL_PID = 8192,\n\tFTRACE_OPS_FL_RCU = 16384,\n\tFTRACE_OPS_FL_TRACE_ARRAY = 32768,\n\tFTRACE_OPS_FL_PERMANENT = 65536,\n\tFTRACE_OPS_FL_DIRECT = 131072,\n\tFTRACE_OPS_FL_SUBOP = 262144,\n\tFTRACE_OPS_FL_GRAPH = 524288,\n};\n\nenum {\n\tFTRACE_UPDATE_CALLS = 1,\n\tFTRACE_DISABLE_CALLS = 2,\n\tFTRACE_UPDATE_TRACE_FUNC = 4,\n\tFTRACE_START_FUNC_RET = 8,\n\tFTRACE_STOP_FUNC_RET = 16,\n\tFTRACE_MAY_SLEEP = 32,\n};\n\nenum {\n\tFTRACE_UPDATE_IGNORE = 0,\n\tFTRACE_UPDATE_MAKE_CALL = 1,\n\tFTRACE_UPDATE_MODIFY_CALL = 2,\n\tFTRACE_UPDATE_MAKE_NOP = 3,\n};\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum {\n\tFW_FEATURE_PSERIES_POSSIBLE = 35183556296703ULL,\n\tFW_FEATURE_PSERIES_ALWAYS = 0ULL,\n\tFW_FEATURE_POWERNV_POSSIBLE = 275146342400ULL,\n\tFW_FEATURE_POWERNV_ALWAYS = 0ULL,\n\tFW_FEATURE_PS3_POSSIBLE = 12582912ULL,\n\tFW_FEATURE_PS3_ALWAYS = 12582912ULL,\n\tFW_FEATURE_NATIVE_POSSIBLE = 0ULL,\n\tFW_FEATURE_NATIVE_ALWAYS = 0ULL,\n\tFW_FEATURE_POSSIBLE = 35183824732159ULL,\n\tFW_FEATURE_ALWAYS = 0ULL,\n};\n\nenum {\n\tGENHD_FL_REMOVABLE = 1,\n\tGENHD_FL_HIDDEN = 2,\n\tGENHD_FL_NO_PART = 4,\n};\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\nenum {\n\tGSSX_NULL = 0,\n\tGSSX_INDICATE_MECHS = 1,\n\tGSSX_GET_CALL_CONTEXT = 2,\n\tGSSX_IMPORT_AND_CANON_NAME = 3,\n\tGSSX_EXPORT_CRED = 4,\n\tGSSX_IMPORT_CRED = 5,\n\tGSSX_ACQUIRE_CRED = 6,\n\tGSSX_STORE_CRED = 7,\n\tGSSX_INIT_SEC_CONTEXT = 8,\n\tGSSX_ACCEPT_SEC_CONTEXT = 9,\n\tGSSX_RELEASE_HANDLE = 10,\n\tGSSX_GET_MIC = 11,\n\tGSSX_VERIFY = 12,\n\tGSSX_WRAP = 13,\n\tGSSX_UNWRAP = 14,\n\tGSSX_WRAP_SIZE_LIMIT = 15,\n};\n\nenum {\n\tHANDSHAKE_A_ACCEPT_SOCKFD = 1,\n\tHANDSHAKE_A_ACCEPT_HANDLER_CLASS = 2,\n\tHANDSHAKE_A_ACCEPT_MESSAGE_TYPE = 3,\n\tHANDSHAKE_A_ACCEPT_TIMEOUT = 4,\n\tHANDSHAKE_A_ACCEPT_AUTH_MODE = 5,\n\tHANDSHAKE_A_ACCEPT_PEER_IDENTITY = 6,\n\tHANDSHAKE_A_ACCEPT_CERTIFICATE = 7,\n\tHANDSHAKE_A_ACCEPT_PEERNAME = 8,\n\tHANDSHAKE_A_ACCEPT_KEYRING = 9,\n\t__HANDSHAKE_A_ACCEPT_MAX = 10,\n\tHANDSHAKE_A_ACCEPT_MAX = 9,\n};\n\nenum {\n\tHANDSHAKE_A_DONE_STATUS = 1,\n\tHANDSHAKE_A_DONE_SOCKFD = 2,\n\tHANDSHAKE_A_DONE_REMOTE_AUTH = 3,\n\t__HANDSHAKE_A_DONE_MAX = 4,\n\tHANDSHAKE_A_DONE_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_A_X509_CERT = 1,\n\tHANDSHAKE_A_X509_PRIVKEY = 2,\n\t__HANDSHAKE_A_X509_MAX = 3,\n\tHANDSHAKE_A_X509_MAX = 2,\n};\n\nenum {\n\tHANDSHAKE_CMD_READY = 1,\n\tHANDSHAKE_CMD_ACCEPT = 2,\n\tHANDSHAKE_CMD_DONE = 3,\n\t__HANDSHAKE_CMD_MAX = 4,\n\tHANDSHAKE_CMD_MAX = 3,\n};\n\nenum {\n\tHANDSHAKE_NLGRP_NONE = 0,\n\tHANDSHAKE_NLGRP_TLSHD = 1,\n};\n\nenum {\n\tHASH_SIZE = 128,\n};\n\nenum {\n\tHAS_READ = 1,\n\tHAS_WRITE = 2,\n\tHAS_LSEEK = 4,\n\tHAS_POLL = 8,\n\tHAS_IOCTL = 16,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum {\n\tHMM_NEED_FAULT = 1,\n\tHMM_NEED_WRITE_FAULT = 2,\n\tHMM_NEED_ALL_BITS = 3,\n};\n\nenum {\n\tHMM_PFN_INOUT_FLAGS = 2017612633061982208ULL,\n};\n\nenum {\n\tHOST_L_CNT = 6,\n};\n\nenum {\n\tHOST_L_DUR = 9,\n};\n\nenum {\n\tHOST_S_CNT = 7,\n};\n\nenum {\n\tHOST_S_DUR = 8,\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nenum {\n\tHUF_flags_bmi2 = 1,\n\tHUF_flags_optimalDepth = 2,\n\tHUF_flags_preferRepeat = 4,\n\tHUF_flags_suspectUncompressible = 8,\n\tHUF_flags_disableAsm = 16,\n\tHUF_flags_disableFast = 32,\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nenum {\n\tHV_GPCI_CM_GA = 128,\n\tHV_GPCI_CM_EXPANDED = 64,\n\tHV_GPCI_CM_LAB = 32,\n};\n\nenum {\n\tHW_BREAKPOINT_EMPTY = 0,\n\tHW_BREAKPOINT_R = 1,\n\tHW_BREAKPOINT_W = 2,\n\tHW_BREAKPOINT_RW = 3,\n\tHW_BREAKPOINT_X = 4,\n\tHW_BREAKPOINT_INVALID = 7,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\tICMP6_MIB_RATELIMITHOST = 6,\n\t__ICMP6_MIB_MAX = 7,\n};\n\nenum {\n\tICMP_ERR_EXT_IIO_IIF = 0,\n\tICMP_ERR_EXT_COUNT = 1,\n};\n\nenum {\n\tICMP_EXT_CTYPE_IIO_ROLE_IIF = 0,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\tICMP_MIB_RATELIMITGLOBAL = 28,\n\tICMP_MIB_RATELIMITHOST = 29,\n\t__ICMP_MIB_MAX = 30,\n};\n\nenum {\n\tIDX_MODULE_ID = 0,\n\tIDX_ST_OPS_COMMON_VALUE_ID = 1,\n};\n\nenum {\n\tIFAL_ADDRESS = 1,\n\tIFAL_LABEL = 2,\n\t__IFAL_MAX = 3,\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\tIFA_PROTO = 11,\n\t__IFA_MAX = 12,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\tIFLA_BRIDGE_CFM = 5,\n\tIFLA_BRIDGE_MST = 6,\n\t__IFLA_BRIDGE_MAX = 7,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\tIFLA_BRPORT_MRP_IN_OPEN = 36,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT = 37,\n\tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT = 38,\n\tIFLA_BRPORT_LOCKED = 39,\n\tIFLA_BRPORT_MAB = 40,\n\tIFLA_BRPORT_MCAST_N_GROUPS = 41,\n\tIFLA_BRPORT_MCAST_MAX_GROUPS = 42,\n\tIFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43,\n\tIFLA_BRPORT_BACKUP_NHID = 44,\n\t__IFLA_BRPORT_MAX = 45,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_INET6_UNSPEC = 0,\n\tIFLA_INET6_FLAGS = 1,\n\tIFLA_INET6_CONF = 2,\n\tIFLA_INET6_STATS = 3,\n\tIFLA_INET6_MCAST = 4,\n\tIFLA_INET6_CACHEINFO = 5,\n\tIFLA_INET6_ICMP6STATS = 6,\n\tIFLA_INET6_TOKEN = 7,\n\tIFLA_INET6_ADDR_GEN_MODE = 8,\n\tIFLA_INET6_RA_MTU = 9,\n\t__IFLA_INET6_MAX = 10,\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_REQUEST = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO_USED = 2,\n\t__IFLA_OFFLOAD_XSTATS_HW_S_INFO_MAX = 3,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\tIFLA_OFFLOAD_XSTATS_HW_S_INFO = 2,\n\tIFLA_OFFLOAD_XSTATS_L3_STATS = 3,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 4,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nenum {\n\tIFLA_PROTO_DOWN_REASON_UNSPEC = 0,\n\tIFLA_PROTO_DOWN_REASON_MASK = 1,\n\tIFLA_PROTO_DOWN_REASON_VALUE = 2,\n\t__IFLA_PROTO_DOWN_REASON_CNT = 3,\n\tIFLA_PROTO_DOWN_REASON_MAX = 2,\n};\n\nenum {\n\tIFLA_STATS_GETSET_UNSPEC = 0,\n\tIFLA_STATS_GET_FILTERS = 1,\n\tIFLA_STATS_SET_OFFLOAD_XSTATS_L3_STATS = 2,\n\t__IFLA_STATS_GETSET_MAX = 3,\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\tIFLA_PROTO_DOWN_REASON = 55,\n\tIFLA_PARENT_DEV_NAME = 56,\n\tIFLA_PARENT_DEV_BUS_NAME = 57,\n\tIFLA_GRO_MAX_SIZE = 58,\n\tIFLA_TSO_MAX_SIZE = 59,\n\tIFLA_TSO_MAX_SEGS = 60,\n\tIFLA_ALLMULTI = 61,\n\tIFLA_DEVLINK_PORT = 62,\n\tIFLA_GSO_IPV4_MAX_SIZE = 63,\n\tIFLA_GRO_IPV4_MAX_SIZE = 64,\n\tIFLA_DPLL_PIN = 65,\n\tIFLA_MAX_PACING_OFFLOAD_HORIZON = 66,\n\tIFLA_NETNS_IMMUTABLE = 67,\n\tIFLA_HEADROOM = 68,\n\tIFLA_TAILROOM = 69,\n\t__IFLA_MAX = 70,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIF_ACT_NONE = -1,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nenum {\n\tIMAGE_INVALID = 0,\n\tIMAGE_LOADING = 1,\n\tIMAGE_READY = 2,\n};\n\nenum {\n\tIMC_TYPE_THREAD = 1,\n\tIMC_TYPE_TRACE = 2,\n\tIMC_TYPE_CORE = 4,\n\tIMC_TYPE_CHIP = 16,\n};\n\nenum {\n\tINET6_IFADDR_STATE_PREDAD = 0,\n\tINET6_IFADDR_STATE_DAD = 1,\n\tINET6_IFADDR_STATE_POSTDAD = 2,\n\tINET6_IFADDR_STATE_ERRDAD = 3,\n\tINET6_IFADDR_STATE_DEAD = 4,\n};\n\nenum {\n\tINET_DIAG_BC_NOP = 0,\n\tINET_DIAG_BC_JMP = 1,\n\tINET_DIAG_BC_S_GE = 2,\n\tINET_DIAG_BC_S_LE = 3,\n\tINET_DIAG_BC_D_GE = 4,\n\tINET_DIAG_BC_D_LE = 5,\n\tINET_DIAG_BC_AUTO = 6,\n\tINET_DIAG_BC_S_COND = 7,\n\tINET_DIAG_BC_D_COND = 8,\n\tINET_DIAG_BC_DEV_COND = 9,\n\tINET_DIAG_BC_MARK_COND = 10,\n\tINET_DIAG_BC_S_EQ = 11,\n\tINET_DIAG_BC_D_EQ = 12,\n\tINET_DIAG_BC_CGROUP_COND = 13,\n};\n\nenum {\n\tINET_DIAG_NONE = 0,\n\tINET_DIAG_MEMINFO = 1,\n\tINET_DIAG_INFO = 2,\n\tINET_DIAG_VEGASINFO = 3,\n\tINET_DIAG_CONG = 4,\n\tINET_DIAG_TOS = 5,\n\tINET_DIAG_TCLASS = 6,\n\tINET_DIAG_SKMEMINFO = 7,\n\tINET_DIAG_SHUTDOWN = 8,\n\tINET_DIAG_DCTCPINFO = 9,\n\tINET_DIAG_PROTOCOL = 10,\n\tINET_DIAG_SKV6ONLY = 11,\n\tINET_DIAG_LOCALS = 12,\n\tINET_DIAG_PEERS = 13,\n\tINET_DIAG_PAD = 14,\n\tINET_DIAG_MARK = 15,\n\tINET_DIAG_BBRINFO = 16,\n\tINET_DIAG_CLASS_ID = 17,\n\tINET_DIAG_MD5SIG = 18,\n\tINET_DIAG_ULP_INFO = 19,\n\tINET_DIAG_SK_BPF_STORAGES = 20,\n\tINET_DIAG_CGROUP_ID = 21,\n\tINET_DIAG_SOCKOPT = 22,\n\t__INET_DIAG_MAX = 23,\n};\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\tINET_DIAG_REQ_PROTOCOL = 3,\n\t__INET_DIAG_REQ_MAX = 4,\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nenum {\n\tINET_FLAGS_PKTINFO = 0,\n\tINET_FLAGS_TTL = 1,\n\tINET_FLAGS_TOS = 2,\n\tINET_FLAGS_RECVOPTS = 3,\n\tINET_FLAGS_RETOPTS = 4,\n\tINET_FLAGS_PASSSEC = 5,\n\tINET_FLAGS_ORIGDSTADDR = 6,\n\tINET_FLAGS_CHECKSUM = 7,\n\tINET_FLAGS_RECVFRAGSIZE = 8,\n\tINET_FLAGS_RECVERR = 9,\n\tINET_FLAGS_RECVERR_RFC4884 = 10,\n\tINET_FLAGS_FREEBIND = 11,\n\tINET_FLAGS_HDRINCL = 12,\n\tINET_FLAGS_MC_LOOP = 13,\n\tINET_FLAGS_MC_ALL = 14,\n\tINET_FLAGS_TRANSPARENT = 15,\n\tINET_FLAGS_IS_ICSK = 16,\n\tINET_FLAGS_NODEFRAG = 17,\n\tINET_FLAGS_BIND_ADDRESS_NO_PORT = 18,\n\tINET_FLAGS_DEFER_CONNECT = 19,\n\tINET_FLAGS_MC6_LOOP = 20,\n\tINET_FLAGS_RECVERR6_RFC4884 = 21,\n\tINET_FLAGS_MC6_ALL = 22,\n\tINET_FLAGS_AUTOFLOWLABEL_SET = 23,\n\tINET_FLAGS_AUTOFLOWLABEL = 24,\n\tINET_FLAGS_DONTFRAG = 25,\n\tINET_FLAGS_RECVERR6 = 26,\n\tINET_FLAGS_REPFLOW = 27,\n\tINET_FLAGS_RTALERT_ISOLATE = 28,\n\tINET_FLAGS_SNDFLOW = 29,\n\tINET_FLAGS_RTALERT = 30,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n\tINET_FRAG_DROP = 16,\n};\n\nenum {\n\tINET_ULP_INFO_UNSPEC = 0,\n\tINET_ULP_INFO_NAME = 1,\n\tINET_ULP_INFO_TLS = 2,\n\tINET_ULP_INFO_MPTCP = 3,\n\t__INET_ULP_INFO_MAX = 4,\n};\n\nenum {\n\tINSN_F_FRAMENO_MASK = 7,\n\tINSN_F_SPI_MASK = 63,\n\tINSN_F_SPI_SHIFT = 3,\n\tINSN_F_STACK_ACCESS = 512,\n\tINSN_F_DST_REG_STACK = 1024,\n\tINSN_F_SRC_REG_STACK = 2048,\n};\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tIOAM6_ATTR_UNSPEC = 0,\n\tIOAM6_ATTR_NS_ID = 1,\n\tIOAM6_ATTR_NS_DATA = 2,\n\tIOAM6_ATTR_NS_DATA_WIDE = 3,\n\tIOAM6_ATTR_SC_ID = 4,\n\tIOAM6_ATTR_SC_DATA = 5,\n\tIOAM6_ATTR_SC_NONE = 6,\n\tIOAM6_ATTR_PAD = 7,\n\t__IOAM6_ATTR_MAX = 8,\n};\n\nenum {\n\tIOAM6_CMD_UNSPEC = 0,\n\tIOAM6_CMD_ADD_NAMESPACE = 1,\n\tIOAM6_CMD_DEL_NAMESPACE = 2,\n\tIOAM6_CMD_DUMP_NAMESPACES = 3,\n\tIOAM6_CMD_ADD_SCHEMA = 4,\n\tIOAM6_CMD_DEL_SCHEMA = 5,\n\tIOAM6_CMD_DUMP_SCHEMAS = 6,\n\tIOAM6_CMD_NS_SET_SCHEMA = 7,\n\t__IOAM6_CMD_MAX = 8,\n};\n\nenum {\n\tIOBL_BUF_RING = 1,\n\tIOBL_INC = 2,\n};\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nenum {\n\tIOMMU_PASID_ARRAY_DOMAIN = 0,\n\tIOMMU_PASID_ARRAY_HANDLE = 1,\n};\n\nenum {\n\tIOMMU_SET_DOMAIN_MUST_SUCCEED = 1,\n};\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n\tIOPRIO_CLASS_INVALID = 7,\n};\n\nenum {\n\tIOPRIO_HINT_NONE = 0,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6,\n\tIOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7,\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n\tIORES_DESC_CXL = 9,\n};\n\nenum {\n\tIORING_MEM_REGION_REG_WAIT_ARG = 1,\n};\n\nenum {\n\tIORING_MEM_REGION_TYPE_USER = 1,\n};\n\nenum {\n\tIORING_REGISTER_SRC_REGISTERED = 1,\n\tIORING_REGISTER_DST_REPLACE = 2,\n};\n\nenum {\n\tIORING_REG_WAIT_TS = 1,\n};\n\nenum {\n\tIORING_RSRC_FILE = 0,\n\tIORING_RSRC_BUFFER = 1,\n};\n\nenum {\n\tIOU_COMPLETE = 0,\n\tIOU_ISSUE_SKIP_COMPLETE = -529,\n\tIOU_RETRY = -11,\n\tIOU_REQUEUE = -3072,\n};\n\nenum {\n\tIOU_F_TWQ_LAZY_WAKE = 1,\n};\n\nenum {\n\tIOU_POLL_DONE = 0,\n\tIOU_POLL_NO_ACTION = 1,\n\tIOU_POLL_REMOVE_POLL_USE_RES = 2,\n\tIOU_POLL_REISSUE = 3,\n\tIOU_POLL_REQUEUE = 4,\n};\n\nenum {\n\tIO_ACCT_STALLED_BIT = 0,\n};\n\nenum {\n\tIO_APOLL_OK = 0,\n\tIO_APOLL_ABORTED = 1,\n\tIO_APOLL_READY = 2,\n};\n\nenum {\n\tIO_CHECK_CQ_OVERFLOW_BIT = 0,\n\tIO_CHECK_CQ_DROPPED_BIT = 1,\n};\n\nenum {\n\tIO_EVENTFD_OP_SIGNAL_BIT = 0,\n};\n\nenum {\n\tIO_IMU_DEST = 1,\n\tIO_IMU_SOURCE = 2,\n};\n\nenum {\n\tIO_REGBUF_F_KBUF = 1,\n};\n\nenum {\n\tIO_REGION_F_VMAP = 1,\n\tIO_REGION_F_USER_PROVIDED = 2,\n\tIO_REGION_F_SINGLE_REF = 4,\n};\n\nenum {\n\tIO_SQ_THREAD_SHOULD_STOP = 0,\n\tIO_SQ_THREAD_SHOULD_PARK = 1,\n};\n\nenum {\n\tIO_URING_BPF_CMD_FILTER = 1,\n};\n\nenum {\n\tIO_URING_BPF_FILTER_DENY_REST = 1,\n\tIO_URING_BPF_FILTER_SZ_STRICT = 2,\n};\n\nenum {\n\tIO_URING_QUERY_OPCODES = 0,\n\tIO_URING_QUERY_ZCRX = 1,\n\tIO_URING_QUERY_SCQ = 2,\n\t__IO_URING_QUERY_MAX = 3,\n};\n\nenum {\n\tIO_WORKER_F_UP = 0,\n\tIO_WORKER_F_RUNNING = 1,\n\tIO_WORKER_F_FREE = 2,\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n\tIO_WQ_ACCT_NR = 2,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_EXIT_ON_IDLE = 1,\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 2,\n\tIO_WQ_WORK_UNBOUND = 4,\n\tIO_WQ_WORK_CONCURRENT = 16,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_L2TP = 115,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_AGGFRAG = 144,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_SMC = 256,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_NOECTPKTS = 4,\n\tIPSTATS_MIB_ECT1PKTS = 5,\n\tIPSTATS_MIB_ECT0PKTS = 6,\n\tIPSTATS_MIB_CEPKTS = 7,\n\tIPSTATS_MIB_OUTREQUESTS = 8,\n\tIPSTATS_MIB_OUTPKTS = 9,\n\tIPSTATS_MIB_OUTOCTETS = 10,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 11,\n\tIPSTATS_MIB_INHDRERRORS = 12,\n\tIPSTATS_MIB_INTOOBIGERRORS = 13,\n\tIPSTATS_MIB_INNOROUTES = 14,\n\tIPSTATS_MIB_INADDRERRORS = 15,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 16,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 17,\n\tIPSTATS_MIB_INDISCARDS = 18,\n\tIPSTATS_MIB_OUTDISCARDS = 19,\n\tIPSTATS_MIB_OUTNOROUTES = 20,\n\tIPSTATS_MIB_REASMTIMEOUT = 21,\n\tIPSTATS_MIB_REASMREQDS = 22,\n\tIPSTATS_MIB_REASMOKS = 23,\n\tIPSTATS_MIB_REASMFAILS = 24,\n\tIPSTATS_MIB_FRAGOKS = 25,\n\tIPSTATS_MIB_FRAGFAILS = 26,\n\tIPSTATS_MIB_FRAGCREATES = 27,\n\tIPSTATS_MIB_INMCASTPKTS = 28,\n\tIPSTATS_MIB_OUTMCASTPKTS = 29,\n\tIPSTATS_MIB_INBCASTPKTS = 30,\n\tIPSTATS_MIB_OUTBCASTPKTS = 31,\n\tIPSTATS_MIB_INMCASTOCTETS = 32,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 33,\n\tIPSTATS_MIB_INBCASTOCTETS = 34,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 35,\n\tIPSTATS_MIB_CSUMERRORS = 36,\n\tIPSTATS_MIB_REASM_OVERLAPS = 37,\n\t__IPSTATS_MIB_MAX = 38,\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\tIPV4_DEVCONF_ARP_EVICT_NOCARRIER = 33,\n\t__IPV4_DEVCONF_MAX = 34,\n};\n\nenum {\n\tIPV6_SADDR_RULE_INIT = 0,\n\tIPV6_SADDR_RULE_LOCAL = 1,\n\tIPV6_SADDR_RULE_SCOPE = 2,\n\tIPV6_SADDR_RULE_PREFERRED = 3,\n\tIPV6_SADDR_RULE_OIF = 4,\n\tIPV6_SADDR_RULE_LABEL = 5,\n\tIPV6_SADDR_RULE_PRIVACY = 6,\n\tIPV6_SADDR_RULE_ORCHID = 7,\n\tIPV6_SADDR_RULE_PREFIX = 8,\n\tIPV6_SADDR_RULE_MAX = 9,\n};\n\nenum {\n\tIP_TUNNEL_CSUM_BIT = 0,\n\tIP_TUNNEL_ROUTING_BIT = 1,\n\tIP_TUNNEL_KEY_BIT = 2,\n\tIP_TUNNEL_SEQ_BIT = 3,\n\tIP_TUNNEL_STRICT_BIT = 4,\n\tIP_TUNNEL_REC_BIT = 5,\n\tIP_TUNNEL_VERSION_BIT = 6,\n\tIP_TUNNEL_NO_KEY_BIT = 7,\n\tIP_TUNNEL_DONT_FRAGMENT_BIT = 8,\n\tIP_TUNNEL_OAM_BIT = 9,\n\tIP_TUNNEL_CRIT_OPT_BIT = 10,\n\tIP_TUNNEL_GENEVE_OPT_BIT = 11,\n\tIP_TUNNEL_VXLAN_OPT_BIT = 12,\n\tIP_TUNNEL_NOCACHE_BIT = 13,\n\tIP_TUNNEL_ERSPAN_OPT_BIT = 14,\n\tIP_TUNNEL_GTP_OPT_BIT = 15,\n\tIP_TUNNEL_VTI_BIT = 16,\n\tIP_TUNNEL_SIT_ISATAP_BIT = 16,\n\tIP_TUNNEL_PFCP_OPT_BIT = 17,\n\t__IP_TUNNEL_FLAG_NUM = 18,\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n\tIRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 512,\n\tIRQCHIP_AFFINITY_PRE_STARTUP = 1024,\n\tIRQCHIP_IMMUTABLE = 2048,\n\tIRQCHIP_MOVE_DEFERRED = 4096,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 134217728,\n\tIRQD_AFFINITY_ON_ACTIVATE = 268435456,\n\tIRQD_IRQ_ENABLED_ON_SUSPEND = 536870912,\n\tIRQD_RESEND_WHEN_IN_PROGRESS = 1073741824,\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n\tIRQS_SYSFS = 16384,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n\tIRQTF_READY = 4,\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_ISOLATED_MSI = 32,\n\tIRQ_DOMAIN_FLAG_NO_MAP = 64,\n\tIRQ_DOMAIN_FLAG_MSI_PARENT = 256,\n\tIRQ_DOMAIN_FLAG_MSI_DEVICE = 512,\n\tIRQ_DOMAIN_FLAG_DESTROY_GC = 1024,\n\tIRQ_DOMAIN_FLAG_MSI_IMMUTABLE = 2048,\n\tIRQ_DOMAIN_FLAG_FWNODE_PARENT = 4096,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\nenum {\n\tIRQ_POLL_F_SCHED = 0,\n\tIRQ_POLL_F_DISABLE = 1,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n\tIRQ_HIDDEN = 1048576,\n\tIRQ_NO_DEBUG = 2097152,\n};\n\nenum {\n\tK2_FLAG_SATA_8_PORTS = 16777216,\n\tK2_FLAG_NO_ATAPI_DMA = 33554432,\n\tK2_FLAG_BAR_POS_3 = 67108864,\n\tK2_SATA_TF_CMD_OFFSET = 0,\n\tK2_SATA_TF_DATA_OFFSET = 0,\n\tK2_SATA_TF_ERROR_OFFSET = 4,\n\tK2_SATA_TF_NSECT_OFFSET = 8,\n\tK2_SATA_TF_LBAL_OFFSET = 12,\n\tK2_SATA_TF_LBAM_OFFSET = 16,\n\tK2_SATA_TF_LBAH_OFFSET = 20,\n\tK2_SATA_TF_DEVICE_OFFSET = 24,\n\tK2_SATA_TF_CMDSTAT_OFFSET = 28,\n\tK2_SATA_TF_CTL_OFFSET = 32,\n\tK2_SATA_DMA_CMD_OFFSET = 48,\n\tK2_SATA_SCR_STATUS_OFFSET = 64,\n\tK2_SATA_SCR_ERROR_OFFSET = 68,\n\tK2_SATA_SCR_CONTROL_OFFSET = 72,\n\tK2_SATA_SICR1_OFFSET = 128,\n\tK2_SATA_SICR2_OFFSET = 132,\n\tK2_SATA_SIM_OFFSET = 136,\n\tK2_SATA_PORT_OFFSET = 256,\n\tchip_svw4 = 0,\n\tchip_svw8 = 1,\n\tchip_svw42 = 2,\n\tchip_svw43 = 3,\n};\n\nenum {\n\tKBUF_MODE_EXPAND = 1,\n\tKBUF_MODE_FREE = 2,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKF_ARG_DYNPTR_ID = 0,\n\tKF_ARG_LIST_HEAD_ID = 1,\n\tKF_ARG_LIST_NODE_ID = 2,\n\tKF_ARG_RB_ROOT_ID = 3,\n\tKF_ARG_RB_NODE_ID = 4,\n\tKF_ARG_WORKQUEUE_ID = 5,\n\tKF_ARG_RES_SPIN_LOCK_ID = 6,\n\tKF_ARG_TASK_WORK_ID = 7,\n\tKF_ARG_PROG_AUX_ID = 8,\n\tKF_ARG_TIMER_ID = 9,\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nenum {\n\tKVMPPC_GSE_BE32 = 0,\n\tKVMPPC_GSE_BE64 = 1,\n\tKVMPPC_GSE_VEC128 = 2,\n\tKVMPPC_GSE_PARTITION_TABLE = 3,\n\tKVMPPC_GSE_PROCESS_TABLE = 4,\n\tKVMPPC_GSE_BUFFER = 5,\n\t__KVMPPC_GSE_TYPE_MAX = 6,\n};\n\nenum {\n\tKVMPPC_GS_CLASS_GUESTWIDE = 1,\n\tKVMPPC_GS_CLASS_HOSTWIDE = 2,\n\tKVMPPC_GS_CLASS_META = 4,\n\tKVMPPC_GS_CLASS_DWORD_REG = 8,\n\tKVMPPC_GS_CLASS_WORD_REG = 16,\n\tKVMPPC_GS_CLASS_VECTOR = 24,\n\tKVMPPC_GS_CLASS_INTR = 32,\n};\n\nenum {\n\tKVMPPC_GS_FLAGS_WIDE = 1,\n\tKVMPPC_GS_FLAGS_HOST_WIDE = 2,\n};\n\nenum {\n\tKYBER_DEFAULT_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = -1,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_FUA = 512,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_NCQ_SEND_RECV = 2048,\n\tATA_DFLAG_NCQ_PRIO = 4096,\n\tATA_DFLAG_CDL = 8192,\n\tATA_DFLAG_CFG_MASK = 16383,\n\tATA_DFLAG_PIO = 16384,\n\tATA_DFLAG_NCQ_OFF = 32768,\n\tATA_DFLAG_SLEEPING = 65536,\n\tATA_DFLAG_DUBIOUS_XFER = 131072,\n\tATA_DFLAG_NO_UNLOAD = 262144,\n\tATA_DFLAG_UNLOCK_HPA = 524288,\n\tATA_DFLAG_INIT_MASK = 1048575,\n\tATA_DFLAG_NCQ_PRIO_ENABLED = 1048576,\n\tATA_DFLAG_CDL_ENABLED = 2097152,\n\tATA_DFLAG_RESUMING = 4194304,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_FEATURES_MASK = 201341696,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DEBOUNCE_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_RESUMING = 65536,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_RTF_FILLED = 4,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_HAS_CDL = 256,\n\tATA_QCFLAG_EH = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_QCFLAG_EH_SUCCESS_CMD = 524288,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_HOST_NO_PART = 16,\n\tATA_HOST_NO_SSC = 32,\n\tATA_HOST_NO_DEVSLP = 64,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 10000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_GET_SUCCESS_SENSE = 64,\n\tATA_EH_SET_ACTIVE = 128,\n\tATA_EH_PERDEV_MASK = 225,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_PRINT_QUIRKS = 2097152,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum {\n\tLINK_CAPA_10HD = 0,\n\tLINK_CAPA_10FD = 1,\n\tLINK_CAPA_100HD = 2,\n\tLINK_CAPA_100FD = 3,\n\tLINK_CAPA_1000HD = 4,\n\tLINK_CAPA_1000FD = 5,\n\tLINK_CAPA_2500FD = 6,\n\tLINK_CAPA_5000FD = 7,\n\tLINK_CAPA_10000FD = 8,\n\tLINK_CAPA_20000FD = 9,\n\tLINK_CAPA_25000FD = 10,\n\tLINK_CAPA_40000FD = 11,\n\tLINK_CAPA_50000FD = 12,\n\tLINK_CAPA_56000FD = 13,\n\tLINK_CAPA_80000FD = 14,\n\tLINK_CAPA_100000FD = 15,\n\tLINK_CAPA_200000FD = 16,\n\tLINK_CAPA_400000FD = 17,\n\tLINK_CAPA_800000FD = 18,\n\tLINK_CAPA_1600000FD = 19,\n\t__LINK_CAPA_MAX = 20,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_BEYOND_WINDOW = 16,\n\tLINUX_MIB_TSECRREJECTED = 17,\n\tLINUX_MIB_PAWS_OLD_ACK = 18,\n\tLINUX_MIB_PAWS_TW_REJECTED = 19,\n\tLINUX_MIB_DELAYEDACKS = 20,\n\tLINUX_MIB_DELAYEDACKLOCKED = 21,\n\tLINUX_MIB_DELAYEDACKLOST = 22,\n\tLINUX_MIB_LISTENOVERFLOWS = 23,\n\tLINUX_MIB_LISTENDROPS = 24,\n\tLINUX_MIB_TCPHPHITS = 25,\n\tLINUX_MIB_TCPPUREACKS = 26,\n\tLINUX_MIB_TCPHPACKS = 27,\n\tLINUX_MIB_TCPRENORECOVERY = 28,\n\tLINUX_MIB_TCPSACKRECOVERY = 29,\n\tLINUX_MIB_TCPSACKRENEGING = 30,\n\tLINUX_MIB_TCPSACKREORDER = 31,\n\tLINUX_MIB_TCPRENOREORDER = 32,\n\tLINUX_MIB_TCPTSREORDER = 33,\n\tLINUX_MIB_TCPFULLUNDO = 34,\n\tLINUX_MIB_TCPPARTIALUNDO = 35,\n\tLINUX_MIB_TCPDSACKUNDO = 36,\n\tLINUX_MIB_TCPLOSSUNDO = 37,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 38,\n\tLINUX_MIB_TCPRENOFAILURES = 39,\n\tLINUX_MIB_TCPSACKFAILURES = 40,\n\tLINUX_MIB_TCPLOSSFAILURES = 41,\n\tLINUX_MIB_TCPFASTRETRANS = 42,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 43,\n\tLINUX_MIB_TCPTIMEOUTS = 44,\n\tLINUX_MIB_TCPLOSSPROBES = 45,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 46,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 47,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 48,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 49,\n\tLINUX_MIB_TCPDSACKOLDSENT = 50,\n\tLINUX_MIB_TCPDSACKOFOSENT = 51,\n\tLINUX_MIB_TCPDSACKRECV = 52,\n\tLINUX_MIB_TCPDSACKOFORECV = 53,\n\tLINUX_MIB_TCPABORTONDATA = 54,\n\tLINUX_MIB_TCPABORTONCLOSE = 55,\n\tLINUX_MIB_TCPABORTONMEMORY = 56,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 57,\n\tLINUX_MIB_TCPABORTONLINGER = 58,\n\tLINUX_MIB_TCPABORTFAILED = 59,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 60,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 61,\n\tLINUX_MIB_TCPSACKDISCARD = 62,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 63,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 64,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 65,\n\tLINUX_MIB_TCPMD5NOTFOUND = 66,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 67,\n\tLINUX_MIB_TCPMD5FAILURE = 68,\n\tLINUX_MIB_SACKSHIFTED = 69,\n\tLINUX_MIB_SACKMERGED = 70,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 71,\n\tLINUX_MIB_TCPBACKLOGDROP = 72,\n\tLINUX_MIB_PFMEMALLOCDROP = 73,\n\tLINUX_MIB_TCPMINTTLDROP = 74,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 75,\n\tLINUX_MIB_IPRPFILTER = 76,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 77,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 78,\n\tLINUX_MIB_TCPREQQFULLDROP = 79,\n\tLINUX_MIB_TCPRETRANSFAIL = 80,\n\tLINUX_MIB_TCPRCVCOALESCE = 81,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 82,\n\tLINUX_MIB_TCPOFOQUEUE = 83,\n\tLINUX_MIB_TCPOFODROP = 84,\n\tLINUX_MIB_TCPOFOMERGE = 85,\n\tLINUX_MIB_TCPCHALLENGEACK = 86,\n\tLINUX_MIB_TCPSYNCHALLENGE = 87,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 88,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 89,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 90,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 91,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 92,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 93,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 94,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 95,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 96,\n\tLINUX_MIB_TCPAUTOCORKING = 97,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 98,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 99,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 100,\n\tLINUX_MIB_TCPSYNRETRANS = 101,\n\tLINUX_MIB_TCPORIGDATASENT = 102,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 103,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 104,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 105,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 106,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 107,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 108,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 109,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 110,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 111,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 112,\n\tLINUX_MIB_TCPWINPROBE = 113,\n\tLINUX_MIB_TCPKEEPALIVE = 114,\n\tLINUX_MIB_TCPMTUPFAIL = 115,\n\tLINUX_MIB_TCPMTUPSUCCESS = 116,\n\tLINUX_MIB_TCPDELIVERED = 117,\n\tLINUX_MIB_TCPDELIVEREDCE = 118,\n\tLINUX_MIB_TCPACKCOMPRESSED = 119,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 120,\n\tLINUX_MIB_TCPRCVQDROP = 121,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 122,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 123,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 124,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 125,\n\tLINUX_MIB_TCPDSACKRECVSEGS = 126,\n\tLINUX_MIB_TCPDSACKIGNOREDDUBIOUS = 127,\n\tLINUX_MIB_TCPMIGRATEREQSUCCESS = 128,\n\tLINUX_MIB_TCPMIGRATEREQFAILURE = 129,\n\tLINUX_MIB_TCPPLBREHASH = 130,\n\tLINUX_MIB_TCPAOREQUIRED = 131,\n\tLINUX_MIB_TCPAOBAD = 132,\n\tLINUX_MIB_TCPAOKEYNOTFOUND = 133,\n\tLINUX_MIB_TCPAOGOOD = 134,\n\tLINUX_MIB_TCPAODROPPEDICMPS = 135,\n\t__LINUX_MIB_MAX = 136,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\tLINUX_MIB_TLSDECRYPTRETRY = 11,\n\tLINUX_MIB_TLSRXNOPADVIOL = 12,\n\tLINUX_MIB_TLSRXREKEYOK = 13,\n\tLINUX_MIB_TLSRXREKEYERROR = 14,\n\tLINUX_MIB_TLSTXREKEYOK = 15,\n\tLINUX_MIB_TLSTXREKEYERROR = 16,\n\tLINUX_MIB_TLSRXREKEYRECEIVED = 17,\n\t__LINUX_MIB_TLSMAX = 18,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\tLINUX_MIB_XFRMOUTSTATEDIRERROR = 29,\n\tLINUX_MIB_XFRMINSTATEDIRERROR = 30,\n\tLINUX_MIB_XFRMINIPTFSERROR = 31,\n\tLINUX_MIB_XFRMOUTNOQSPACE = 32,\n\t__LINUX_MIB_XFRMMAX = 33,\n};\n\nenum {\n\tLK_STATE_IN_USE = 0,\n\tNFS_DELEGATED_STATE = 1,\n\tNFS_OPEN_STATE = 2,\n\tNFS_O_RDONLY_STATE = 3,\n\tNFS_O_WRONLY_STATE = 4,\n\tNFS_O_RDWR_STATE = 5,\n\tNFS_STATE_RECLAIM_REBOOT = 6,\n\tNFS_STATE_RECLAIM_NOGRACE = 7,\n\tNFS_STATE_POSIX_LOCKS = 8,\n\tNFS_STATE_RECOVERY_FAILED = 9,\n\tNFS_STATE_MAY_NOTIFY_LOCK = 10,\n\tNFS_STATE_CHANGE_WAIT = 11,\n\tNFS_CLNT_DST_SSC_COPY_STATE = 12,\n\tNFS_CLNT_SRC_SSC_COPY_STATE = 13,\n\tNFS_SRV_SSC_COPY_STATE = 14,\n};\n\nenum {\n\tLOCKD_A_SERVER_GRACETIME = 1,\n\tLOCKD_A_SERVER_TCP_PORT = 2,\n\tLOCKD_A_SERVER_UDP_PORT = 3,\n\t__LOCKD_A_SERVER_MAX = 4,\n\tLOCKD_A_SERVER_MAX = 3,\n};\n\nenum {\n\tLOCKD_CMD_SERVER_SET = 1,\n\tLOCKD_CMD_SERVER_GET = 2,\n\t__LOCKD_CMD_MAX = 3,\n\tLOCKD_CMD_MAX = 2,\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 256,\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n\tLo_deleting = 3,\n};\n\nenum {\n\tM88E3082_VCT_OFF = 0,\n\tM88E3082_VCT_PHASE1 = 1,\n\tM88E3082_VCT_PHASE2 = 2,\n};\n\nenum {\n\tMAGNITUDE_STRONG = 2,\n\tMAGNITUDE_WEAK = 3,\n\tMAGNITUDE_NUM = 4,\n};\n\nenum {\n\tMAX_IORES_LEVEL = 8,\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\nenum {\n\tMBE_REFERENCED_B = 0,\n\tMBE_REUSABLE_B = 1,\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nenum {\n\tMDBA_GET_ENTRY_UNSPEC = 0,\n\tMDBA_GET_ENTRY = 1,\n\tMDBA_GET_ENTRY_ATTRS = 2,\n\t__MDBA_GET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMDBA_SET_ENTRY_UNSPEC = 0,\n\tMDBA_SET_ENTRY = 1,\n\tMDBA_SET_ENTRY_ATTRS = 2,\n\t__MDBA_SET_ENTRY_MAX = 3,\n};\n\nenum {\n\tMD_RESYNC_NONE = 0,\n\tMD_RESYNC_YIELDED = 1,\n\tMD_RESYNC_DELAYED = 2,\n\tMD_RESYNC_ACTIVE = 3,\n};\n\nenum {\n\tMED_R_CNT = 10,\n};\n\nenum {\n\tMED_R_DUR = 12,\n};\n\nenum {\n\tMED_W_CNT = 11,\n};\n\nenum {\n\tMED_W_DUR = 13,\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n\tMEMBARRIER_FLAG_RSEQ = 2,\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY = 64,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ = 128,\n};\n\nenum {\n\tMEMMAP_ON_MEMORY_DISABLE = 0,\n\tMEMMAP_ON_MEMORY_ENABLE = 1,\n\tMEMMAP_ON_MEMORY_FORCE = 2,\n};\n\nenum {\n\tMEMORY_RECLAIM_SWAPPINESS = 0,\n\tMEMORY_RECLAIM_SWAPPINESS_MAX = 1,\n\tMEMORY_RECLAIM_NULL = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tMEM_LIFE = 4,\n};\n\nenum {\n\tMEM_LOADS = 228505944544ULL,\n};\n\nenum {\n\tMEM_STORES = 228640162272ULL,\n};\n\nenum {\n\tMIX_INFLIGHT = 2147483648,\n};\n\nenum {\n\tMMOP_OFFLINE = 0,\n\tMMOP_ONLINE = 1,\n\tMMOP_ONLINE_KERNEL = 2,\n\tMMOP_ONLINE_MOVABLE = 3,\n};\n\nenum {\n\tMMU_FTRS_POSSIBLE = 4261477953,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum {\n\tMOUNTPROC3_NULL = 0,\n\tMOUNTPROC3_MNT = 1,\n\tMOUNTPROC3_DUMP = 2,\n\tMOUNTPROC3_UMNT = 3,\n\tMOUNTPROC3_UMNTALL = 4,\n\tMOUNTPROC3_EXPORT = 5,\n};\n\nenum {\n\tMOUNTPROC_NULL = 0,\n\tMOUNTPROC_MNT = 1,\n\tMOUNTPROC_DUMP = 2,\n\tMOUNTPROC_UMNT = 3,\n\tMOUNTPROC_UMNTALL = 4,\n\tMOUNTPROC_EXPORT = 5,\n};\n\nenum {\n\tMOXA_SUPP_RS232 = 1,\n\tMOXA_SUPP_RS422 = 2,\n\tMOXA_SUPP_RS485 = 4,\n};\n\nenum {\n\tMPOL_DEFAULT = 0,\n\tMPOL_PREFERRED = 1,\n\tMPOL_BIND = 2,\n\tMPOL_INTERLEAVE = 3,\n\tMPOL_LOCAL = 4,\n\tMPOL_PREFERRED_MANY = 5,\n\tMPOL_WEIGHTED_INTERLEAVE = 6,\n\tMPOL_MAX = 7,\n};\n\nenum {\n\tMSI_CHIP_FLAG_SET_EOI = 1,\n\tMSI_CHIP_FLAG_SET_ACK = 2,\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_ACTIVATE_EARLY = 4,\n\tMSI_FLAG_MUST_REACTIVATE = 8,\n\tMSI_FLAG_DEV_SYSFS = 16,\n\tMSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32,\n\tMSI_FLAG_FREE_MSI_DESCS = 64,\n\tMSI_FLAG_USE_DEV_FWNODE = 128,\n\tMSI_FLAG_PARENT_PM_DEV = 256,\n\tMSI_FLAG_PCI_MSI_MASK_PARENT = 512,\n\tMSI_FLAG_PCI_MSI_STARTUP_PARENT = 1024,\n\tMSI_GENERIC_FLAGS_MASK = 65535,\n\tMSI_DOMAIN_FLAGS_MASK = 4294901760,\n\tMSI_FLAG_MULTI_PCI_MSI = 65536,\n\tMSI_FLAG_PCI_MSIX = 131072,\n\tMSI_FLAG_LEVEL_CAPABLE = 262144,\n\tMSI_FLAG_MSIX_CONTIGUOUS = 524288,\n\tMSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576,\n\tMSI_FLAG_NO_AFFINITY = 2097152,\n\tMSI_FLAG_NO_MASK = 4194304,\n};\n\nenum {\n\tMV_DMA_BOUNDARY = 65535,\n\tEDMA_REQ_Q_BASE_LO_MASK = 4294966272,\n\tEDMA_RSP_Q_BASE_LO_MASK = 4294967040,\n};\n\nenum {\n\tMV_PRIMARY_BAR = 0,\n\tMV_IO_BAR = 2,\n\tMV_MISC_BAR = 3,\n\tMV_MAJOR_REG_AREA_SZ = 65536,\n\tMV_MINOR_REG_AREA_SZ = 8192,\n\tCOAL_CLOCKS_PER_USEC = 150,\n\tMAX_COAL_TIME_THRESHOLD = 16777215,\n\tMAX_COAL_IO_COUNT = 255,\n\tMV_PCI_REG_BASE = 0,\n\tCOAL_REG_BASE = 98304,\n\tIRQ_COAL_CAUSE = 98312,\n\tALL_PORTS_COAL_IRQ = 16,\n\tIRQ_COAL_IO_THRESHOLD = 98508,\n\tIRQ_COAL_TIME_THRESHOLD = 98512,\n\tTRAN_COAL_CAUSE_LO = 98440,\n\tTRAN_COAL_CAUSE_HI = 98444,\n\tSATAHC0_REG_BASE = 131072,\n\tFLASH_CTL = 66668,\n\tGPIO_PORT_CTL = 66800,\n\tRESET_CFG = 98520,\n\tMV_PCI_REG_SZ = 65536,\n\tMV_SATAHC_REG_SZ = 65536,\n\tMV_SATAHC_ARBTR_REG_SZ = 8192,\n\tMV_PORT_REG_SZ = 8192,\n\tMV_MAX_Q_DEPTH = 32,\n\tMV_MAX_Q_DEPTH_MASK = 31,\n\tMV_CRQB_Q_SZ = 1024,\n\tMV_CRPB_Q_SZ = 256,\n\tMV_MAX_SG_CT = 256,\n\tMV_SG_TBL_SZ = 4096,\n\tMV_PORT_HC_SHIFT = 2,\n\tMV_PORTS_PER_HC = 4,\n\tMV_PORT_MASK = 3,\n\tMV_FLAG_DUAL_HC = 1073741824,\n\tMV_COMMON_FLAGS = 514,\n\tMV_GEN_I_FLAGS = 578,\n\tMV_GEN_II_FLAGS = 656898,\n\tMV_GEN_IIE_FLAGS = 919042,\n\tCRQB_FLAG_READ = 1,\n\tCRQB_TAG_SHIFT = 1,\n\tCRQB_IOID_SHIFT = 6,\n\tCRQB_PMP_SHIFT = 12,\n\tCRQB_HOSTQ_SHIFT = 17,\n\tCRQB_CMD_ADDR_SHIFT = 8,\n\tCRQB_CMD_CS = 4096,\n\tCRQB_CMD_LAST = 32768,\n\tCRPB_FLAG_STATUS_SHIFT = 8,\n\tCRPB_IOID_SHIFT_6 = 5,\n\tCRPB_IOID_SHIFT_7 = 7,\n\tEPRD_FLAG_END_OF_TBL = -2147483648,\n\tMV_PCI_COMMAND = 3072,\n\tMV_PCI_COMMAND_MWRCOM = 16,\n\tMV_PCI_COMMAND_MRDTRIG = 128,\n\tPCI_MAIN_CMD_STS = 3376,\n\tSTOP_PCI_MASTER = 4,\n\tPCI_MASTER_EMPTY = 8,\n\tGLOB_SFT_RST = 16,\n\tMV_PCI_MODE = 3328,\n\tMV_PCI_MODE_MASK = 48,\n\tMV_PCI_EXP_ROM_BAR_CTL = 3372,\n\tMV_PCI_DISC_TIMER = 3332,\n\tMV_PCI_MSI_TRIGGER = 3128,\n\tMV_PCI_SERR_MASK = 3112,\n\tMV_PCI_XBAR_TMOUT = 7428,\n\tMV_PCI_ERR_LOW_ADDRESS = 7488,\n\tMV_PCI_ERR_HIGH_ADDRESS = 7492,\n\tMV_PCI_ERR_ATTRIBUTE = 7496,\n\tMV_PCI_ERR_COMMAND = 7504,\n\tPCI_IRQ_CAUSE = 7512,\n\tPCI_IRQ_MASK = 7516,\n\tPCI_UNMASK_ALL_IRQS = 8388607,\n\tPCIE_IRQ_CAUSE = 6400,\n\tPCIE_IRQ_MASK = 6416,\n\tPCIE_UNMASK_ALL_IRQS = 1034,\n\tPCI_HC_MAIN_IRQ_CAUSE = 7520,\n\tPCI_HC_MAIN_IRQ_MASK = 7524,\n\tSOC_HC_MAIN_IRQ_CAUSE = 131104,\n\tSOC_HC_MAIN_IRQ_MASK = 131108,\n\tERR_IRQ = 1,\n\tDONE_IRQ = 2,\n\tHC0_IRQ_PEND = 511,\n\tHC_SHIFT = 9,\n\tDONE_IRQ_0_3 = 170,\n\tDONE_IRQ_4_7 = 87040,\n\tPCI_ERR = 262144,\n\tTRAN_COAL_LO_DONE = 524288,\n\tTRAN_COAL_HI_DONE = 1048576,\n\tPORTS_0_3_COAL_DONE = 256,\n\tPORTS_4_7_COAL_DONE = 131072,\n\tALL_PORTS_COAL_DONE = 2097152,\n\tGPIO_INT = 4194304,\n\tSELF_INT = 8388608,\n\tTWSI_INT = 16777216,\n\tHC_MAIN_RSVD = -33554432,\n\tHC_MAIN_RSVD_5 = -524288,\n\tHC_MAIN_RSVD_SOC = -320,\n\tHC_CFG = 0,\n\tHC_IRQ_CAUSE = 20,\n\tDMA_IRQ = 1,\n\tHC_COAL_IRQ = 16,\n\tDEV_IRQ = 256,\n\tHC_IRQ_COAL_IO_THRESHOLD = 12,\n\tHC_IRQ_COAL_TIME_THRESHOLD = 16,\n\tSOC_LED_CTRL = 44,\n\tSOC_LED_CTRL_BLINK = 1,\n\tSOC_LED_CTRL_ACT_PRESENCE = 4,\n\tSHD_BLK = 256,\n\tSHD_CTL_AST = 32,\n\tSATA_STATUS = 768,\n\tSATA_ACTIVE = 848,\n\tFIS_IRQ_CAUSE = 868,\n\tFIS_IRQ_CAUSE_AN = 512,\n\tLTMODE = 780,\n\tLTMODE_BIT8 = 256,\n\tPHY_MODE2 = 816,\n\tPHY_MODE3 = 784,\n\tPHY_MODE4 = 788,\n\tPHY_MODE4_CFG_MASK = 3,\n\tPHY_MODE4_CFG_VALUE = 1,\n\tPHY_MODE4_RSVD_ZEROS = 1575223290,\n\tPHY_MODE4_RSVD_ONES = 5,\n\tSATA_IFCTL = 836,\n\tSATA_TESTCTL = 840,\n\tSATA_IFSTAT = 844,\n\tVENDOR_UNIQUE_FIS = 860,\n\tFISCFG = 864,\n\tFISCFG_WAIT_DEV_ERR = 256,\n\tFISCFG_SINGLE_SYNC = 65536,\n\tPHY_MODE9_GEN2 = 920,\n\tPHY_MODE9_GEN1 = 924,\n\tPHYCFG_OFS = 928,\n\tMV5_PHY_MODE = 116,\n\tMV5_LTMODE = 48,\n\tMV5_PHY_CTL = 12,\n\tSATA_IFCFG = 80,\n\tLP_PHY_CTL = 88,\n\tLP_PHY_CTL_PIN_PU_PLL = 1,\n\tLP_PHY_CTL_PIN_PU_RX = 2,\n\tLP_PHY_CTL_PIN_PU_TX = 4,\n\tLP_PHY_CTL_GEN_TX_3G = 32,\n\tLP_PHY_CTL_GEN_RX_3G = 512,\n\tMV_M2_PREAMP_MASK = 2016,\n\tEDMA_CFG = 0,\n\tEDMA_CFG_Q_DEPTH = 31,\n\tEDMA_CFG_NCQ = 32,\n\tEDMA_CFG_NCQ_GO_ON_ERR = 16384,\n\tEDMA_CFG_RD_BRST_EXT = 2048,\n\tEDMA_CFG_WR_BUFF_LEN = 8192,\n\tEDMA_CFG_EDMA_FBS = 65536,\n\tEDMA_CFG_FBS = 67108864,\n\tEDMA_ERR_IRQ_CAUSE = 8,\n\tEDMA_ERR_IRQ_MASK = 12,\n\tEDMA_ERR_D_PAR = 1,\n\tEDMA_ERR_PRD_PAR = 2,\n\tEDMA_ERR_DEV = 4,\n\tEDMA_ERR_DEV_DCON = 8,\n\tEDMA_ERR_DEV_CON = 16,\n\tEDMA_ERR_SERR = 32,\n\tEDMA_ERR_SELF_DIS = 128,\n\tEDMA_ERR_SELF_DIS_5 = 256,\n\tEDMA_ERR_BIST_ASYNC = 256,\n\tEDMA_ERR_TRANS_IRQ_7 = 256,\n\tEDMA_ERR_CRQB_PAR = 512,\n\tEDMA_ERR_CRPB_PAR = 1024,\n\tEDMA_ERR_INTRL_PAR = 2048,\n\tEDMA_ERR_IORDY = 4096,\n\tEDMA_ERR_LNK_CTRL_RX = 122880,\n\tEDMA_ERR_LNK_CTRL_RX_0 = 8192,\n\tEDMA_ERR_LNK_CTRL_RX_1 = 16384,\n\tEDMA_ERR_LNK_CTRL_RX_2 = 32768,\n\tEDMA_ERR_LNK_CTRL_RX_3 = 65536,\n\tEDMA_ERR_LNK_DATA_RX = 1966080,\n\tEDMA_ERR_LNK_CTRL_TX = 65011712,\n\tEDMA_ERR_LNK_CTRL_TX_0 = 2097152,\n\tEDMA_ERR_LNK_CTRL_TX_1 = 4194304,\n\tEDMA_ERR_LNK_CTRL_TX_2 = 8388608,\n\tEDMA_ERR_LNK_CTRL_TX_3 = 16777216,\n\tEDMA_ERR_LNK_CTRL_TX_4 = 33554432,\n\tEDMA_ERR_LNK_DATA_TX = 2080374784,\n\tEDMA_ERR_TRANS_PROTO = -2147483648,\n\tEDMA_ERR_OVERRUN_5 = 32,\n\tEDMA_ERR_UNDERRUN_5 = 64,\n\tEDMA_ERR_IRQ_TRANSIENT = 65101824,\n\tEDMA_EH_FREEZE = -65102149,\n\tEDMA_EH_FREEZE_5 = 8059,\n\tEDMA_REQ_Q_BASE_HI = 16,\n\tEDMA_REQ_Q_IN_PTR = 20,\n\tEDMA_REQ_Q_OUT_PTR = 24,\n\tEDMA_REQ_Q_PTR_SHIFT = 5,\n\tEDMA_RSP_Q_BASE_HI = 28,\n\tEDMA_RSP_Q_IN_PTR = 32,\n\tEDMA_RSP_Q_OUT_PTR = 36,\n\tEDMA_RSP_Q_PTR_SHIFT = 3,\n\tEDMA_CMD = 40,\n\tEDMA_EN = 1,\n\tEDMA_DS = 2,\n\tEDMA_RESET = 4,\n\tEDMA_STATUS = 48,\n\tEDMA_STATUS_CACHE_EMPTY = 64,\n\tEDMA_STATUS_IDLE = 128,\n\tEDMA_IORDY_TMOUT = 52,\n\tEDMA_ARB_CFG = 56,\n\tEDMA_HALTCOND = 96,\n\tEDMA_UNKNOWN_RSVD = 108,\n\tBMDMA_CMD = 548,\n\tBMDMA_STATUS = 552,\n\tBMDMA_PRD_LOW = 556,\n\tBMDMA_PRD_HIGH = 560,\n\tMV_HP_FLAG_MSI = 1,\n\tMV_HP_ERRATA_50XXB0 = 2,\n\tMV_HP_ERRATA_50XXB2 = 4,\n\tMV_HP_ERRATA_60X1B2 = 8,\n\tMV_HP_ERRATA_60X1C0 = 16,\n\tMV_HP_GEN_I = 64,\n\tMV_HP_GEN_II = 128,\n\tMV_HP_GEN_IIE = 256,\n\tMV_HP_PCIE = 512,\n\tMV_HP_CUT_THROUGH = 1024,\n\tMV_HP_FLAG_SOC = 2048,\n\tMV_HP_QUIRK_LED_BLINK_EN = 4096,\n\tMV_HP_FIX_LP_PHY_CTL = 8192,\n\tMV_PP_FLAG_EDMA_EN = 1,\n\tMV_PP_FLAG_NCQ_EN = 2,\n\tMV_PP_FLAG_FBS_EN = 4,\n\tMV_PP_FLAG_DELAYED_EH = 8,\n\tMV_PP_FLAG_FAKE_ATA_BUSY = 16,\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_LISTED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n\tNAPIF_STATE_PREFER_BUSY_POLL = 128,\n\tNAPIF_STATE_THREADED = 256,\n\tNAPIF_STATE_SCHED_THREADED = 512,\n\tNAPIF_STATE_HAS_NOTIFIER = 1024,\n\tNAPIF_STATE_THREADED_BUSY_POLL = 2048,\n};\n\nenum {\n\tNAPI_F_PREFER_BUSY_POLL = 1,\n\tNAPI_F_END_ON_RESCHED = 2,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_LISTED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n\tNAPI_STATE_PREFER_BUSY_POLL = 7,\n\tNAPI_STATE_THREADED = 8,\n\tNAPI_STATE_SCHED_THREADED = 9,\n\tNAPI_STATE_HAS_NOTIFIER = 10,\n\tNAPI_STATE_THREADED_BUSY_POLL = 11,\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\tNDA_FDB_EXT_ATTRS = 14,\n\tNDA_FLAGS_EXT = 15,\n\tNDA_NDM_STATE_MASK = 16,\n\tNDA_NDM_FLAGS_MASK = 17,\n\t__NDA_MAX = 18,\n};\n\nenum {\n\tNDD_UNARMED = 1,\n\tNDD_LOCKED = 2,\n\tNDD_SECURITY_OVERWRITE = 3,\n\tNDD_WORK_PENDING = 4,\n\tNDD_LABELING = 6,\n\tNDD_INCOHERENT = 7,\n\tNDD_REGISTER_SYNC = 8,\n\tND_IOCTL_MAX_BUFLEN = 4194304,\n\tND_CMD_MAX_ELEM = 5,\n\tND_CMD_MAX_ENVELOPE = 256,\n\tND_MAX_MAPPINGS = 32,\n\tND_REGION_PAGEMAP = 0,\n\tND_REGION_PERSIST_CACHE = 1,\n\tND_REGION_PERSIST_MEMCTRL = 2,\n\tND_REGION_ASYNC = 3,\n\tND_REGION_CXL = 4,\n\tDPA_RESOURCE_ADJUSTED = 1,\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\tNDTPA_INTERVAL_PROBE_TIME_MS = 19,\n\t__NDTPA_MAX = 20,\n};\n\nenum {\n\tNDUSEROPT_UNSPEC = 0,\n\tNDUSEROPT_SRCADDR = 1,\n\t__NDUSEROPT_MAX = 2,\n};\n\nenum {\n\tND_CMD_IMPLEMENTED = 0,\n\tND_CMD_ARS_CAP = 1,\n\tND_CMD_ARS_START = 2,\n\tND_CMD_ARS_STATUS = 3,\n\tND_CMD_CLEAR_ERROR = 4,\n\tND_CMD_SMART = 1,\n\tND_CMD_SMART_THRESHOLD = 2,\n\tND_CMD_DIMM_FLAGS = 3,\n\tND_CMD_GET_CONFIG_SIZE = 4,\n\tND_CMD_GET_CONFIG_DATA = 5,\n\tND_CMD_SET_CONFIG_DATA = 6,\n\tND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,\n\tND_CMD_VENDOR_EFFECT_LOG = 8,\n\tND_CMD_VENDOR = 9,\n\tND_CMD_CALL = 10,\n};\n\nenum {\n\tND_MAX_LANES = 256,\n\tINT_LBASIZE_ALIGNMENT = 64,\n\tNVDIMM_IO_ATOMIC = 1,\n};\n\nenum {\n\tND_MIN_NAMESPACE_SIZE = 65536,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_NR_TABLES = 2,\n\tNEIGH_LINK_TABLE = 2,\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_INTERVAL_PROBE_TIME_MS = 7,\n\tNEIGH_VAR_GC_STALETIME = 8,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 9,\n\tNEIGH_VAR_PROXY_QLEN = 10,\n\tNEIGH_VAR_ANYCAST_DELAY = 11,\n\tNEIGH_VAR_PROXY_DELAY = 12,\n\tNEIGH_VAR_LOCKTIME = 13,\n\tNEIGH_VAR_QUEUE_LEN = 14,\n\tNEIGH_VAR_RETRANS_TIME_MS = 15,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 16,\n\tNEIGH_VAR_GC_INTERVAL = 17,\n\tNEIGH_VAR_GC_THRESH1 = 18,\n\tNEIGH_VAR_GC_THRESH2 = 19,\n\tNEIGH_VAR_GC_THRESH3 = 20,\n\tNEIGH_VAR_MAX = 21,\n};\n\nenum {\n\tNESTED_SYNC_IMM_BIT = 0,\n\tNESTED_SYNC_TODO_BIT = 1,\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\tNETCONFA_FORCE_FORWARDING = 9,\n\t__NETCONFA_MAX = 10,\n};\n\nenum {\n\tNETDEV_A_DEV_IFINDEX = 1,\n\tNETDEV_A_DEV_PAD = 2,\n\tNETDEV_A_DEV_XDP_FEATURES = 3,\n\tNETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4,\n\tNETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5,\n\tNETDEV_A_DEV_XSK_FEATURES = 6,\n\t__NETDEV_A_DEV_MAX = 7,\n\tNETDEV_A_DEV_MAX = 6,\n};\n\nenum {\n\tNETDEV_A_DMABUF_IFINDEX = 1,\n\tNETDEV_A_DMABUF_QUEUES = 2,\n\tNETDEV_A_DMABUF_FD = 3,\n\tNETDEV_A_DMABUF_ID = 4,\n\t__NETDEV_A_DMABUF_MAX = 5,\n\tNETDEV_A_DMABUF_MAX = 4,\n};\n\nenum {\n\tNETDEV_A_NAPI_IFINDEX = 1,\n\tNETDEV_A_NAPI_ID = 2,\n\tNETDEV_A_NAPI_IRQ = 3,\n\tNETDEV_A_NAPI_PID = 4,\n\tNETDEV_A_NAPI_DEFER_HARD_IRQS = 5,\n\tNETDEV_A_NAPI_GRO_FLUSH_TIMEOUT = 6,\n\tNETDEV_A_NAPI_IRQ_SUSPEND_TIMEOUT = 7,\n\tNETDEV_A_NAPI_THREADED = 8,\n\t__NETDEV_A_NAPI_MAX = 9,\n\tNETDEV_A_NAPI_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_ID = 1,\n\tNETDEV_A_PAGE_POOL_IFINDEX = 2,\n\tNETDEV_A_PAGE_POOL_NAPI_ID = 3,\n\tNETDEV_A_PAGE_POOL_INFLIGHT = 4,\n\tNETDEV_A_PAGE_POOL_INFLIGHT_MEM = 5,\n\tNETDEV_A_PAGE_POOL_DETACH_TIME = 6,\n\tNETDEV_A_PAGE_POOL_DMABUF = 7,\n\tNETDEV_A_PAGE_POOL_IO_URING = 8,\n\t__NETDEV_A_PAGE_POOL_MAX = 9,\n\tNETDEV_A_PAGE_POOL_MAX = 8,\n};\n\nenum {\n\tNETDEV_A_PAGE_POOL_STATS_INFO = 1,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_FAST = 8,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW = 9,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_SLOW_HIGH_ORDER = 10,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_EMPTY = 11,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_REFILL = 12,\n\tNETDEV_A_PAGE_POOL_STATS_ALLOC_WAIVE = 13,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHED = 14,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_CACHE_FULL = 15,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING = 16,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RING_FULL = 17,\n\tNETDEV_A_PAGE_POOL_STATS_RECYCLE_RELEASED_REFCNT = 18,\n\t__NETDEV_A_PAGE_POOL_STATS_MAX = 19,\n\tNETDEV_A_PAGE_POOL_STATS_MAX = 18,\n};\n\nenum {\n\tNETDEV_A_QSTATS_IFINDEX = 1,\n\tNETDEV_A_QSTATS_QUEUE_TYPE = 2,\n\tNETDEV_A_QSTATS_QUEUE_ID = 3,\n\tNETDEV_A_QSTATS_SCOPE = 4,\n\tNETDEV_A_QSTATS_RX_PACKETS = 8,\n\tNETDEV_A_QSTATS_RX_BYTES = 9,\n\tNETDEV_A_QSTATS_TX_PACKETS = 10,\n\tNETDEV_A_QSTATS_TX_BYTES = 11,\n\tNETDEV_A_QSTATS_RX_ALLOC_FAIL = 12,\n\tNETDEV_A_QSTATS_RX_HW_DROPS = 13,\n\tNETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14,\n\tNETDEV_A_QSTATS_RX_CSUM_COMPLETE = 15,\n\tNETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 16,\n\tNETDEV_A_QSTATS_RX_CSUM_NONE = 17,\n\tNETDEV_A_QSTATS_RX_CSUM_BAD = 18,\n\tNETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 19,\n\tNETDEV_A_QSTATS_RX_HW_GRO_BYTES = 20,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 21,\n\tNETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 22,\n\tNETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 23,\n\tNETDEV_A_QSTATS_TX_HW_DROPS = 24,\n\tNETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 25,\n\tNETDEV_A_QSTATS_TX_CSUM_NONE = 26,\n\tNETDEV_A_QSTATS_TX_NEEDS_CSUM = 27,\n\tNETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 28,\n\tNETDEV_A_QSTATS_TX_HW_GSO_BYTES = 29,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 30,\n\tNETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 31,\n\tNETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 32,\n\tNETDEV_A_QSTATS_TX_STOP = 33,\n\tNETDEV_A_QSTATS_TX_WAKE = 34,\n\t__NETDEV_A_QSTATS_MAX = 35,\n\tNETDEV_A_QSTATS_MAX = 34,\n};\n\nenum {\n\tNETDEV_A_QUEUE_ID = 1,\n\tNETDEV_A_QUEUE_IFINDEX = 2,\n\tNETDEV_A_QUEUE_TYPE = 3,\n\tNETDEV_A_QUEUE_NAPI_ID = 4,\n\tNETDEV_A_QUEUE_DMABUF = 5,\n\tNETDEV_A_QUEUE_IO_URING = 6,\n\tNETDEV_A_QUEUE_XSK = 7,\n\t__NETDEV_A_QUEUE_MAX = 8,\n\tNETDEV_A_QUEUE_MAX = 7,\n};\n\nenum {\n\tNETDEV_CMD_DEV_GET = 1,\n\tNETDEV_CMD_DEV_ADD_NTF = 2,\n\tNETDEV_CMD_DEV_DEL_NTF = 3,\n\tNETDEV_CMD_DEV_CHANGE_NTF = 4,\n\tNETDEV_CMD_PAGE_POOL_GET = 5,\n\tNETDEV_CMD_PAGE_POOL_ADD_NTF = 6,\n\tNETDEV_CMD_PAGE_POOL_DEL_NTF = 7,\n\tNETDEV_CMD_PAGE_POOL_CHANGE_NTF = 8,\n\tNETDEV_CMD_PAGE_POOL_STATS_GET = 9,\n\tNETDEV_CMD_QUEUE_GET = 10,\n\tNETDEV_CMD_NAPI_GET = 11,\n\tNETDEV_CMD_QSTATS_GET = 12,\n\tNETDEV_CMD_BIND_RX = 13,\n\tNETDEV_CMD_NAPI_SET = 14,\n\tNETDEV_CMD_BIND_TX = 15,\n\t__NETDEV_CMD_MAX = 16,\n\tNETDEV_CMD_MAX = 15,\n};\n\nenum {\n\tNETDEV_NLGRP_MGMT = 0,\n\tNETDEV_NLGRP_PAGE_POOL = 1,\n};\n\nenum {\n\tNETDEV_STATS = 0,\n\tE1000_STATS = 1,\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\t__UNUSED_NETIF_F_12 = 12,\n\t__UNUSED_NETIF_F_13 = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_ACCECN_BIT = 35,\n\tNETIF_F_GSO_LAST = 35,\n\tNETIF_F_FCOE_CRC_BIT = 36,\n\tNETIF_F_SCTP_CRC_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETIF_F_GRO_UDP_FWD_BIT = 59,\n\tNETIF_F_HW_HSR_TAG_INS_BIT = 60,\n\tNETIF_F_HW_HSR_TAG_RM_BIT = 61,\n\tNETIF_F_HW_HSR_FWD_BIT = 62,\n\tNETIF_F_HW_HSR_DUP_BIT = 63,\n\tNETDEV_FEATURE_COUNT = 64,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nenum {\n\tNETLINK_F_KERNEL_SOCKET = 0,\n\tNETLINK_F_RECV_PKTINFO = 1,\n\tNETLINK_F_BROADCAST_SEND_ERROR = 2,\n\tNETLINK_F_RECV_NO_ENOBUFS = 3,\n\tNETLINK_F_LISTEN_ALL_NSID = 4,\n\tNETLINK_F_CAP_ACK = 5,\n\tNETLINK_F_EXT_ACK = 6,\n\tNETLINK_F_STRICT_CHK = 7,\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\tNEXTHOP_GRP_TYPE_RES = 1,\n\t__NEXTHOP_GRP_TYPE_MAX = 2,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_NUMPROTO = 11,\n};\n\nenum {\n\tNFSPROC4_CLNT_NULL = 0,\n\tNFSPROC4_CLNT_READ = 1,\n\tNFSPROC4_CLNT_WRITE = 2,\n\tNFSPROC4_CLNT_COMMIT = 3,\n\tNFSPROC4_CLNT_OPEN = 4,\n\tNFSPROC4_CLNT_OPEN_CONFIRM = 5,\n\tNFSPROC4_CLNT_OPEN_NOATTR = 6,\n\tNFSPROC4_CLNT_OPEN_DOWNGRADE = 7,\n\tNFSPROC4_CLNT_CLOSE = 8,\n\tNFSPROC4_CLNT_SETATTR = 9,\n\tNFSPROC4_CLNT_FSINFO = 10,\n\tNFSPROC4_CLNT_RENEW = 11,\n\tNFSPROC4_CLNT_SETCLIENTID = 12,\n\tNFSPROC4_CLNT_SETCLIENTID_CONFIRM = 13,\n\tNFSPROC4_CLNT_LOCK = 14,\n\tNFSPROC4_CLNT_LOCKT = 15,\n\tNFSPROC4_CLNT_LOCKU = 16,\n\tNFSPROC4_CLNT_ACCESS = 17,\n\tNFSPROC4_CLNT_GETATTR = 18,\n\tNFSPROC4_CLNT_LOOKUP = 19,\n\tNFSPROC4_CLNT_LOOKUP_ROOT = 20,\n\tNFSPROC4_CLNT_REMOVE = 21,\n\tNFSPROC4_CLNT_RENAME = 22,\n\tNFSPROC4_CLNT_LINK = 23,\n\tNFSPROC4_CLNT_SYMLINK = 24,\n\tNFSPROC4_CLNT_CREATE = 25,\n\tNFSPROC4_CLNT_PATHCONF = 26,\n\tNFSPROC4_CLNT_STATFS = 27,\n\tNFSPROC4_CLNT_READLINK = 28,\n\tNFSPROC4_CLNT_READDIR = 29,\n\tNFSPROC4_CLNT_SERVER_CAPS = 30,\n\tNFSPROC4_CLNT_DELEGRETURN = 31,\n\tNFSPROC4_CLNT_GETACL = 32,\n\tNFSPROC4_CLNT_SETACL = 33,\n\tNFSPROC4_CLNT_FS_LOCATIONS = 34,\n\tNFSPROC4_CLNT_RELEASE_LOCKOWNER = 35,\n\tNFSPROC4_CLNT_SECINFO = 36,\n\tNFSPROC4_CLNT_FSID_PRESENT = 37,\n\tNFSPROC4_CLNT_EXCHANGE_ID = 38,\n\tNFSPROC4_CLNT_CREATE_SESSION = 39,\n\tNFSPROC4_CLNT_DESTROY_SESSION = 40,\n\tNFSPROC4_CLNT_SEQUENCE = 41,\n\tNFSPROC4_CLNT_GET_LEASE_TIME = 42,\n\tNFSPROC4_CLNT_RECLAIM_COMPLETE = 43,\n\tNFSPROC4_CLNT_LAYOUTGET = 44,\n\tNFSPROC4_CLNT_GETDEVICEINFO = 45,\n\tNFSPROC4_CLNT_LAYOUTCOMMIT = 46,\n\tNFSPROC4_CLNT_LAYOUTRETURN = 47,\n\tNFSPROC4_CLNT_SECINFO_NO_NAME = 48,\n\tNFSPROC4_CLNT_TEST_STATEID = 49,\n\tNFSPROC4_CLNT_FREE_STATEID = 50,\n\tNFSPROC4_CLNT_GETDEVICELIST = 51,\n\tNFSPROC4_CLNT_BIND_CONN_TO_SESSION = 52,\n\tNFSPROC4_CLNT_DESTROY_CLIENTID = 53,\n\tNFSPROC4_CLNT_SEEK = 54,\n\tNFSPROC4_CLNT_ALLOCATE = 55,\n\tNFSPROC4_CLNT_DEALLOCATE = 56,\n\tNFSPROC4_CLNT_ZERO_RANGE = 57,\n\tNFSPROC4_CLNT_LAYOUTSTATS = 58,\n\tNFSPROC4_CLNT_CLONE = 59,\n\tNFSPROC4_CLNT_COPY = 60,\n\tNFSPROC4_CLNT_OFFLOAD_CANCEL = 61,\n\tNFSPROC4_CLNT_LOOKUPP = 62,\n\tNFSPROC4_CLNT_LAYOUTERROR = 63,\n\tNFSPROC4_CLNT_COPY_NOTIFY = 64,\n\tNFSPROC4_CLNT_GETXATTR = 65,\n\tNFSPROC4_CLNT_SETXATTR = 66,\n\tNFSPROC4_CLNT_LISTXATTRS = 67,\n\tNFSPROC4_CLNT_REMOVEXATTR = 68,\n\tNFSPROC4_CLNT_READ_PLUS = 69,\n\tNFSPROC4_CLNT_OFFLOAD_STATUS = 70,\n};\n\nenum {\n\tNFS_DELEGATION_NEED_RECLAIM = 0,\n\tNFS_DELEGATION_RETURN_IF_CLOSED = 1,\n\tNFS_DELEGATION_REFERENCED = 2,\n\tNFS_DELEGATION_RETURNING = 3,\n\tNFS_DELEGATION_REVOKED = 4,\n\tNFS_DELEGATION_TEST_EXPIRED = 5,\n\tNFS_DELEGATION_DELEGTIME = 6,\n};\n\nenum {\n\tNFS_DEVICEID_INVALID = 0,\n\tNFS_DEVICEID_UNAVAILABLE = 1,\n\tNFS_DEVICEID_NOCACHE = 2,\n};\n\nenum {\n\tNFS_IOHDR_ERROR = 0,\n\tNFS_IOHDR_EOF = 1,\n\tNFS_IOHDR_REDO = 2,\n\tNFS_IOHDR_STAT = 3,\n\tNFS_IOHDR_RESEND_PNFS = 4,\n\tNFS_IOHDR_RESEND_MDS = 5,\n\tNFS_IOHDR_UNSTABLE_WRITES = 6,\n\tNFS_IOHDR_ODIRECT = 7,\n};\n\nenum {\n\tNFS_LAYOUT_RO_FAILED = 0,\n\tNFS_LAYOUT_RW_FAILED = 1,\n\tNFS_LAYOUT_BULK_RECALL = 2,\n\tNFS_LAYOUT_RETURN = 3,\n\tNFS_LAYOUT_RETURN_LOCK = 4,\n\tNFS_LAYOUT_RETURN_REQUESTED = 5,\n\tNFS_LAYOUT_INVALID_STID = 6,\n\tNFS_LAYOUT_FIRST_LAYOUTGET = 7,\n\tNFS_LAYOUT_INODE_FREEING = 8,\n\tNFS_LAYOUT_HASHED = 9,\n\tNFS_LAYOUT_DRAIN = 10,\n};\n\nenum {\n\tNFS_LSEG_VALID = 0,\n\tNFS_LSEG_ROC = 1,\n\tNFS_LSEG_LAYOUTCOMMIT = 2,\n\tNFS_LSEG_LAYOUTRETURN = 3,\n\tNFS_LSEG_UNAVAILABLE = 4,\n};\n\nenum {\n\tNFS_OWNER_RECLAIM_REBOOT = 0,\n\tNFS_OWNER_RECLAIM_NOGRACE = 1,\n};\n\nenum {\n\tNHA_GROUP_STATS_ENTRY_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY_ID = 1,\n\tNHA_GROUP_STATS_ENTRY_PACKETS = 2,\n\tNHA_GROUP_STATS_ENTRY_PACKETS_HW = 3,\n\t__NHA_GROUP_STATS_ENTRY_MAX = 4,\n};\n\nenum {\n\tNHA_GROUP_STATS_UNSPEC = 0,\n\tNHA_GROUP_STATS_ENTRY = 1,\n\t__NHA_GROUP_STATS_MAX = 2,\n};\n\nenum {\n\tNHA_RES_BUCKET_UNSPEC = 0,\n\tNHA_RES_BUCKET_PAD = 0,\n\tNHA_RES_BUCKET_INDEX = 1,\n\tNHA_RES_BUCKET_IDLE_TIME = 2,\n\tNHA_RES_BUCKET_NH_ID = 3,\n\t__NHA_RES_BUCKET_MAX = 4,\n};\n\nenum {\n\tNHA_RES_GROUP_UNSPEC = 0,\n\tNHA_RES_GROUP_PAD = 0,\n\tNHA_RES_GROUP_BUCKETS = 1,\n\tNHA_RES_GROUP_IDLE_TIMER = 2,\n\tNHA_RES_GROUP_UNBALANCED_TIMER = 3,\n\tNHA_RES_GROUP_UNBALANCED_TIME = 4,\n\t__NHA_RES_GROUP_MAX = 5,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\tNHA_RES_GROUP = 12,\n\tNHA_RES_BUCKET = 13,\n\tNHA_OP_FLAGS = 14,\n\tNHA_GROUP_STATS = 15,\n\tNHA_HW_STATS_ENABLE = 16,\n\tNHA_HW_STATS_USED = 17,\n\t__NHA_MAX = 18,\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_BE16 = 18,\n\tNLA_BE32 = 19,\n\tNLA_SINT = 20,\n\tNLA_UINT = 21,\n\t__NLA_TYPE_MAX = 22,\n};\n\nenum {\n\tNLM_LCK_GRANTED = 0,\n\tNLM_LCK_DENIED = 1,\n\tNLM_LCK_DENIED_NOLOCKS = 2,\n\tNLM_LCK_BLOCKED = 3,\n\tNLM_LCK_DENIED_GRACE_PERIOD = 4,\n\tNLM_DEADLCK = 5,\n\tNLM_ROFS = 6,\n\tNLM_STALE_FH = 7,\n\tNLM_FBIG = 8,\n\tNLM_FAILED = 9,\n};\n\nenum {\n\tNODE_SIZE = 256,\n\tKEYS_PER_NODE = 16,\n\tRECS_PER_LEAF = 15,\n};\n\nenum {\n\tNO_USER_KERNEL = 0,\n\tNO_USER_USER = 1,\n\tNO_GUEST_HOST = 2,\n\tNO_GUEST_GUEST = 3,\n\tNO_CROSS_THREAD = 4,\n\tNR_VECTOR_PARAMS = 5,\n};\n\nenum {\n\tNSINDEX_SIG_LEN = 16,\n\tNSINDEX_ALIGN = 256,\n\tNSINDEX_SEQ_MASK = 3,\n\tNSLABEL_UUID_LEN = 16,\n\tNSLABEL_NAME_LEN = 64,\n\tNSLABEL_FLAG_ROLABEL = 1,\n\tNSLABEL_FLAG_LOCAL = 2,\n\tNSLABEL_FLAG_BTT = 4,\n\tNSLABEL_FLAG_UPDATING = 8,\n\tBTT_ALIGN = 4096,\n\tBTTINFO_SIG_LEN = 16,\n\tBTTINFO_UUID_LEN = 16,\n\tBTTINFO_FLAG_ERROR = 1,\n\tBTTINFO_MAJOR_VERSION = 1,\n\tND_LABEL_MIN_SIZE = 1024,\n\tND_LABEL_ID_SIZE = 50,\n\tND_NSINDEX_INIT = 1,\n};\n\nenum {\n\tNSMPROC_NULL = 0,\n\tNSMPROC_STAT = 1,\n\tNSMPROC_MON = 2,\n\tNSMPROC_UNMON = 3,\n\tNSMPROC_UNMON_ALL = 4,\n\tNSMPROC_SIMU_CRASH = 5,\n\tNSMPROC_NOTIFY = 6,\n};\n\nenum {\n\tNUM_TRIAL_SAMPLES = 8192,\n\tMAX_SAMPLES_PER_BIT = 66,\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n\tNVMEM_LAYOUT_ADD = 5,\n\tNVMEM_LAYOUT_REMOVE = 6,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_CSS_MASK = 112,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_CSS_CSI = 96,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_MPS_MASK = 1920,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_AMS_MASK = 14336,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOSQES_MASK = 983040,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_IOCQES_MASK = 15728640,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CC_CRIME = 16777216,\n};\n\nenum {\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_CMBMSC = 80,\n\tNVME_REG_CRTO = 104,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tOD_NORMAL_SAMPLE = 0,\n\tOD_SUB_SAMPLE = 1,\n};\n\nenum {\n\tONLINE_POLICY_CONTIG_ZONES = 0,\n\tONLINE_POLICY_AUTO_MOVABLE = 1,\n};\n\nenum {\n\tOPAL_HMI_FLAGS_TB_RESYNC = 1ULL,\n\tOPAL_HMI_FLAGS_DEC_LOST = 2ULL,\n\tOPAL_HMI_FLAGS_HDEC_LOST = 4ULL,\n\tOPAL_HMI_FLAGS_TOD_TB_FAIL = 8ULL,\n\tOPAL_HMI_FLAGS_NEW_EVENT = 9223372036854775808ULL,\n};\n\nenum {\n\tOPAL_IMC_COUNTERS_NEST = 1,\n\tOPAL_IMC_COUNTERS_CORE = 2,\n\tOPAL_IMC_COUNTERS_TRACE = 3,\n};\n\nenum {\n\tOPAL_P7IOC_DIAG_TYPE_NONE = 0,\n\tOPAL_P7IOC_DIAG_TYPE_RGC = 1,\n\tOPAL_P7IOC_DIAG_TYPE_BI = 2,\n\tOPAL_P7IOC_DIAG_TYPE_CI = 3,\n\tOPAL_P7IOC_DIAG_TYPE_MISC = 4,\n\tOPAL_P7IOC_DIAG_TYPE_I2C = 5,\n\tOPAL_P7IOC_DIAG_TYPE_LAST = 6,\n};\n\nenum {\n\tOPAL_P7IOC_NUM_PEST_REGS = 128,\n\tOPAL_PHB3_NUM_PEST_REGS = 256,\n\tOPAL_PHB4_NUM_PEST_REGS = 512,\n};\n\nenum {\n\tOPAL_PCI_TCE_KILL_PAGES = 0,\n\tOPAL_PCI_TCE_KILL_PE = 1,\n\tOPAL_PCI_TCE_KILL_ALL = 2,\n};\n\nenum {\n\tOPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,\n\tOPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,\n\tOPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3,\n};\n\nenum {\n\tOPAL_REBOOT_NORMAL = 0,\n\tOPAL_REBOOT_PLATFORM_ERROR = 1,\n\tOPAL_REBOOT_FULL_IPL = 2,\n\tOPAL_REBOOT_MPIPL = 3,\n\tOPAL_REBOOT_FAST = 4,\n};\n\nenum {\n\tOPAL_REINIT_CPUS_HILE_BE = 1,\n\tOPAL_REINIT_CPUS_HILE_LE = 2,\n\tOPAL_REINIT_CPUS_MMU_HASH = 4,\n\tOPAL_REINIT_CPUS_MMU_RADIX = 8,\n\tOPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = 16,\n};\n\nenum {\n\tOPAL_XIVE_EQ_ENABLED = 1,\n\tOPAL_XIVE_EQ_ALWAYS_NOTIFY = 2,\n\tOPAL_XIVE_EQ_ESCALATE = 4,\n};\n\nenum {\n\tOPAL_XIVE_IRQ_TRIGGER_PAGE = 1,\n\tOPAL_XIVE_IRQ_STORE_EOI = 2,\n\tOPAL_XIVE_IRQ_LSI = 4,\n\tOPAL_XIVE_IRQ_SHIFT_BUG = 8,\n\tOPAL_XIVE_IRQ_MASK_VIA_FW = 16,\n\tOPAL_XIVE_IRQ_EOI_VIA_FW = 32,\n\tOPAL_XIVE_IRQ_STORE_EOI2 = 64,\n};\n\nenum {\n\tOPAL_XIVE_MODE_EMU = 0,\n\tOPAL_XIVE_MODE_EXPL = 1,\n};\n\nenum {\n\tOPAL_XIVE_VP_ENABLED = 1,\n\tOPAL_XIVE_VP_SINGLE_ESCALATION = 2,\n};\n\nenum {\n\tOPTIMIZER_ST_IDLE = 0,\n\tOPTIMIZER_ST_KICKED = 1,\n\tOPTIMIZER_ST_FLUSHING = 2,\n};\n\nenum {\n\tOPT_UID = 0,\n\tOPT_GID = 1,\n\tOPT_MODE = 2,\n\tOPT_DELEGATE_CMDS = 3,\n\tOPT_DELEGATE_MAPS = 4,\n\tOPT_DELEGATE_PROGS = 5,\n\tOPT_DELEGATE_ATTACHS = 6,\n};\n\nenum {\n\tOp_deprecated = 0,\n\tOpt_logbufs = 1,\n\tOpt_logbsize = 2,\n\tOpt_logdev = 3,\n\tOpt_rtdev = 4,\n\tOpt_wsync = 5,\n\tOpt_noalign = 6,\n\tOpt_swalloc = 7,\n\tOpt_sunit = 8,\n\tOpt_swidth = 9,\n\tOpt_nouuid = 10,\n\tOpt_grpid = 11,\n\tOpt_nogrpid = 12,\n\tOpt_bsdgroups = 13,\n\tOpt_sysvgroups = 14,\n\tOpt_allocsize = 15,\n\tOpt_norecovery = 16,\n\tOpt_inode64 = 17,\n\tOpt_inode32 = 18,\n\tOpt_largeio = 19,\n\tOpt_nolargeio = 20,\n\tOpt_filestreams = 21,\n\tOpt_quota = 22,\n\tOpt_noquota = 23,\n\tOpt_usrquota = 24,\n\tOpt_grpquota = 25,\n\tOpt_prjquota = 26,\n\tOpt_uquota = 27,\n\tOpt_gquota = 28,\n\tOpt_pquota = 29,\n\tOpt_uqnoenforce = 30,\n\tOpt_gqnoenforce = 31,\n\tOpt_pqnoenforce = 32,\n\tOpt_qnoenforce = 33,\n\tOpt_discard = 34,\n\tOpt_nodiscard = 35,\n\tOpt_dax = 36,\n\tOpt_dax_enum = 37,\n\tOpt_max_open_zones = 38,\n\tOpt_lifetime = 39,\n\tOpt_nolifetime = 40,\n\tOpt_max_atomic_write = 41,\n\tOpt_errortag = 42,\n};\n\nenum {\n\tOpt_block = 0,\n\tOpt_check = 1,\n\tOpt_cruft = 2,\n\tOpt_gid = 3,\n\tOpt_ignore = 4,\n\tOpt_iocharset = 5,\n\tOpt_map = 6,\n\tOpt_mode = 7,\n\tOpt_nojoliet = 8,\n\tOpt_norock = 9,\n\tOpt_sb = 10,\n\tOpt_session = 11,\n\tOpt_uid = 12,\n\tOpt_unhide = 13,\n\tOpt_utf8 = 14,\n\tOpt_err = 15,\n\tOpt_nocompress = 16,\n\tOpt_hide = 17,\n\tOpt_showassoc = 18,\n\tOpt_dmode = 19,\n\tOpt_overriderockperm = 20,\n};\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid___2 = 2,\n\tOpt_nogrpid___2 = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb___2 = 6,\n\tOpt_nouid32 = 7,\n\tOpt_debug = 8,\n\tOpt_removed = 9,\n\tOpt_user_xattr = 10,\n\tOpt_acl = 11,\n\tOpt_auto_da_alloc = 12,\n\tOpt_noauto_da_alloc = 13,\n\tOpt_noload = 14,\n\tOpt_commit = 15,\n\tOpt_min_batch_time = 16,\n\tOpt_max_batch_time = 17,\n\tOpt_journal_dev = 18,\n\tOpt_journal_path = 19,\n\tOpt_journal_checksum = 20,\n\tOpt_journal_async_commit = 21,\n\tOpt_abort = 22,\n\tOpt_data_journal = 23,\n\tOpt_data_ordered = 24,\n\tOpt_data_writeback = 25,\n\tOpt_data_err_abort = 26,\n\tOpt_data_err_ignore = 27,\n\tOpt_test_dummy_encryption = 28,\n\tOpt_inlinecrypt = 29,\n\tOpt_usrjquota = 30,\n\tOpt_grpjquota = 31,\n\tOpt_quota___2 = 32,\n\tOpt_noquota___2 = 33,\n\tOpt_barrier = 34,\n\tOpt_nobarrier = 35,\n\tOpt_err___2 = 36,\n\tOpt_usrquota___2 = 37,\n\tOpt_grpquota___2 = 38,\n\tOpt_prjquota___2 = 39,\n\tOpt_dax___2 = 40,\n\tOpt_dax_always = 41,\n\tOpt_dax_inode = 42,\n\tOpt_dax_never = 43,\n\tOpt_stripe = 44,\n\tOpt_delalloc = 45,\n\tOpt_nodelalloc = 46,\n\tOpt_warn_on_error = 47,\n\tOpt_nowarn_on_error = 48,\n\tOpt_mblk_io_submit = 49,\n\tOpt_debug_want_extra_isize = 50,\n\tOpt_nomblk_io_submit = 51,\n\tOpt_block_validity = 52,\n\tOpt_noblock_validity = 53,\n\tOpt_inode_readahead_blks = 54,\n\tOpt_journal_ioprio = 55,\n\tOpt_dioread_nolock = 56,\n\tOpt_dioread_lock = 57,\n\tOpt_discard___2 = 58,\n\tOpt_nodiscard___2 = 59,\n\tOpt_init_itable = 60,\n\tOpt_noinit_itable = 61,\n\tOpt_max_dir_size_kb = 62,\n\tOpt_nojournal_checksum = 63,\n\tOpt_nombcache = 64,\n\tOpt_no_prefetch_block_bitmaps = 65,\n\tOpt_mb_optimize_scan = 66,\n\tOpt_errors = 67,\n\tOpt_data = 68,\n\tOpt_data_err = 69,\n\tOpt_jqfmt = 70,\n\tOpt_dax_type = 71,\n};\n\nenum {\n\tOpt_check___2 = 0,\n\tOpt_uid___2 = 1,\n\tOpt_gid___2 = 2,\n\tOpt_umask = 3,\n\tOpt_dmask = 4,\n\tOpt_fmask = 5,\n\tOpt_allow_utime = 6,\n\tOpt_codepage = 7,\n\tOpt_usefree = 8,\n\tOpt_nocase = 9,\n\tOpt_quiet = 10,\n\tOpt_showexec = 11,\n\tOpt_debug___2 = 12,\n\tOpt_immutable = 13,\n\tOpt_dots = 14,\n\tOpt_dotsOK = 15,\n\tOpt_charset = 16,\n\tOpt_shortname = 17,\n\tOpt_utf8___2 = 18,\n\tOpt_utf8_bool = 19,\n\tOpt_uni_xl = 20,\n\tOpt_uni_xl_bool = 21,\n\tOpt_nonumtail = 22,\n\tOpt_nonumtail_bool = 23,\n\tOpt_obsolete = 24,\n\tOpt_flush = 25,\n\tOpt_tz = 26,\n\tOpt_rodir = 27,\n\tOpt_errors___2 = 28,\n\tOpt_discard___3 = 29,\n\tOpt_nfs = 30,\n\tOpt_nfs_enum = 31,\n\tOpt_time_offset = 32,\n\tOpt_dos1xfloppy = 33,\n};\n\nenum {\n\tOpt_err___3 = 0,\n\tOpt_enc = 1,\n\tOpt_hash = 2,\n};\n\nenum {\n\tOpt_error = -1,\n\tOpt_context = 0,\n\tOpt_defcontext = 1,\n\tOpt_fscontext = 2,\n\tOpt_rootcontext = 3,\n\tOpt_seclabel = 4,\n};\n\nenum {\n\tOpt_fatal_neterrors_default = 0,\n\tOpt_fatal_neterrors_enetunreach = 1,\n\tOpt_fatal_neterrors_none = 2,\n};\n\nenum {\n\tOpt_find_uid = 0,\n\tOpt_find_gid = 1,\n\tOpt_find_user = 2,\n\tOpt_find_group = 3,\n\tOpt_find_err = 4,\n};\n\nenum {\n\tOpt_kmsg_bytes = 0,\n};\n\nenum {\n\tOpt_local_lock_all = 0,\n\tOpt_local_lock_flock = 1,\n\tOpt_local_lock_none = 2,\n\tOpt_local_lock_posix = 3,\n};\n\nenum {\n\tOpt_lookupcache_all = 0,\n\tOpt_lookupcache_none = 1,\n\tOpt_lookupcache_positive = 2,\n};\n\nenum {\n\tOpt_sec_krb5 = 0,\n\tOpt_sec_krb5i = 1,\n\tOpt_sec_krb5p = 2,\n\tOpt_sec_lkey = 3,\n\tOpt_sec_lkeyi = 4,\n\tOpt_sec_lkeyp = 5,\n\tOpt_sec_none = 6,\n\tOpt_sec_spkm = 7,\n\tOpt_sec_spkmi = 8,\n\tOpt_sec_spkmp = 9,\n\tOpt_sec_sys = 10,\n\tnr__Opt_sec = 11,\n};\n\nenum {\n\tOpt_uid___3 = 0,\n\tOpt_gid___3 = 1,\n\tOpt_mode___2 = 2,\n};\n\nenum {\n\tOpt_uid___4 = 0,\n\tOpt_gid___4 = 1,\n\tOpt_mode___3 = 2,\n\tOpt_source = 3,\n};\n\nenum {\n\tOpt_uid___5 = 0,\n\tOpt_gid___5 = 1,\n\tOpt_mode___4 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err___4 = 6,\n};\n\nenum {\n\tOpt_vers_2 = 0,\n\tOpt_vers_3 = 1,\n\tOpt_vers_4 = 2,\n\tOpt_vers_4_0 = 3,\n\tOpt_vers_4_1 = 4,\n\tOpt_vers_4_2 = 5,\n};\n\nenum {\n\tOpt_write_lazy = 0,\n\tOpt_write_eager = 1,\n\tOpt_write_wait = 2,\n};\n\nenum {\n\tOpt_xprt_rdma = 0,\n\tOpt_xprt_rdma6 = 1,\n\tOpt_xprt_tcp = 2,\n\tOpt_xprt_tcp6 = 3,\n\tOpt_xprt_udp = 4,\n\tOpt_xprt_udp6 = 5,\n\tnr__Opt_xprt = 6,\n};\n\nenum {\n\tOpt_xprtsec_none = 0,\n\tOpt_xprtsec_tls = 1,\n\tOpt_xprtsec_mtls = 2,\n\tnr__Opt_xprtsec = 3,\n};\n\nenum {\n\tPAGE_REPORTING_IDLE = 0,\n\tPAGE_REPORTING_REQUESTED = 1,\n\tPAGE_REPORTING_ACTIVE = 2,\n};\n\nenum {\n\tPAGE_WAS_MAPPED = 1,\n\tPAGE_WAS_MLOCKED = 2,\n\tPAGE_OLD_STATES = 3,\n};\n\nenum {\n\tPAPR_MISCDEV_IOC_ID = 178,\n};\n\nenum {\n\tPAPR_SYSPARM_MAX_INPUT = 1024,\n\tPAPR_SYSPARM_MAX_OUTPUT = 4000,\n};\n\nenum {\n\tPARSE_INVALID = 1,\n\tPARSE_NOT_LONGNAME = 2,\n\tPARSE_EOF = 3,\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_BRIDGE_RESOURCES = 7,\n\tPCI_BRIDGE_RESOURCE_END = 10,\n\tPCI_NUM_RESOURCES = 11,\n\tDEVICE_COUNT_RESOURCE = 11,\n};\n\nenum {\n\tPCMCIA_IOPORT_0 = 0,\n\tPCMCIA_IOPORT_1 = 1,\n\tPCMCIA_IOMEM_0 = 2,\n\tPCMCIA_IOMEM_1 = 3,\n\tPCMCIA_IOMEM_2 = 4,\n\tPCMCIA_IOMEM_3 = 5,\n\tPCMCIA_NUM_RESOURCES = 6,\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nenum {\n\tPG_BUSY = 0,\n\tPG_MAPPED = 1,\n\tPG_FOLIO = 2,\n\tPG_CLEAN = 3,\n\tPG_COMMIT_TO_DS = 4,\n\tPG_INODE_REF = 5,\n\tPG_HEADLOCK = 6,\n\tPG_TEARDOWN = 7,\n\tPG_UNLOCKPAGE = 8,\n\tPG_UPTODATE = 9,\n\tPG_WB_END = 10,\n\tPG_REMOVE = 11,\n\tPG_CONTENDED1 = 12,\n\tPG_CONTENDED2 = 13,\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = -1,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nenum {\n\tPM_BR_CMPL = 315486,\n};\n\nenum {\n\tPM_BR_FIN = 192586,\n};\n\nenum {\n\tPM_BR_MPRED_CMPL = 262390,\n};\n\nenum {\n\tPM_CYC = 393460,\n};\n\nenum {\n\tPM_CYC___2 = 30,\n\tPM_GCT_NOSLOT_CYC = 65784,\n\tPM_CMPLU_STALL = 262154,\n\tPM_INST_CMPL = 2,\n\tPM_BRU_FIN = 65640,\n\tPM_BR_MPRED_CMPL___2 = 262390,\n\tPM_LD_REF_L1 = 65774,\n\tPM_LD_MISS_L1 = 254036,\n\tPM_ST_MISS_L1 = 196848,\n\tPM_L1_PREF = 55480,\n\tPM_INST_FROM_L1 = 16512,\n\tPM_L1_ICACHE_MISS = 131325,\n\tPM_L1_DEMAND_WRITE = 16524,\n\tPM_IC_PREF_WRITE = 16526,\n\tPM_DATA_FROM_L3 = 311362,\n\tPM_DATA_FROM_L3MISS = 196862,\n\tPM_L2_ST = 94336,\n\tPM_L2_ST_MISS = 94338,\n\tPM_L3_PREF_ALL = 319570,\n\tPM_DTLB_MISS = 196860,\n\tPM_ITLB_MISS = 262396,\n\tPM_RUN_INST_CMPL = 327930,\n\tPM_RUN_INST_CMPL_ALT = 262394,\n\tPM_RUN_CYC = 393460,\n\tPM_RUN_CYC_ALT = 131316,\n\tPM_MRK_ST_CMPL = 65844,\n\tPM_MRK_ST_CMPL_ALT = 197090,\n\tPM_BR_MRK_2PATH = 65848,\n\tPM_BR_MRK_2PATH_ALT = 262456,\n\tPM_L3_CO_MEPF = 98434,\n\tPM_L3_CO_MEPF_ALT = 254046,\n\tPM_MRK_DATA_FROM_L2MISS = 119118,\n\tPM_MRK_DATA_FROM_L2MISS_ALT = 262632,\n\tPM_CMPLU_STALL_ALT = 122964,\n\tPM_BR_2PATH = 131126,\n\tPM_BR_2PATH_ALT = 262198,\n\tPM_INST_DISP = 131314,\n\tPM_INST_DISP_ALT = 196850,\n\tPM_MRK_FILT_MATCH = 131388,\n\tPM_MRK_FILT_MATCH_ALT = 196910,\n\tPM_LD_MISS_L1_ALT = 262384,\n\tMEM_ACCESS = 17039840,\n};\n\nenum {\n\tPM_CYC___3 = 30ULL,\n\tPM_ICT_NOSLOT_CYC = 65784ULL,\n\tPM_CMPLU_STALL___2 = 122964ULL,\n\tPM_INST_CMPL___2 = 2ULL,\n\tPM_BR_CMPL___2 = 315486ULL,\n\tPM_BR_MPRED_CMPL___3 = 262390ULL,\n\tPM_LD_REF_L1___2 = 65788ULL,\n\tPM_LD_MISS_L1_FIN = 180302ULL,\n\tPM_LD_MISS_L1___2 = 254036ULL,\n\tPM_LD_MISS_L1_ALT___2 = 262384ULL,\n\tPM_ST_MISS_L1___2 = 196848ULL,\n\tPM_L1_PREF___2 = 131156ULL,\n\tPM_INST_FROM_L1___2 = 16512ULL,\n\tPM_L1_ICACHE_MISS___2 = 131325ULL,\n\tPM_L1_DEMAND_WRITE___2 = 16524ULL,\n\tPM_IC_PREF_WRITE___2 = 18572ULL,\n\tPM_DATA_FROM_L3___2 = 311362ULL,\n\tPM_DATA_FROM_L3MISS___2 = 196862ULL,\n\tPM_L2_ST___2 = 92288ULL,\n\tPM_L2_ST_MISS___2 = 157824ULL,\n\tPM_L3_PREF_ALL___2 = 319570ULL,\n\tPM_DTLB_MISS___2 = 196860ULL,\n\tPM_ITLB_MISS___2 = 262396ULL,\n\tPM_RUN_INST_CMPL___2 = 327930ULL,\n\tPM_RUN_INST_CMPL_ALT___2 = 262394ULL,\n\tPM_RUN_CYC___2 = 393460ULL,\n\tPM_RUN_CYC_ALT___2 = 131316ULL,\n\tPM_INST_DISP___2 = 131314ULL,\n\tPM_INST_DISP_ALT___2 = 196850ULL,\n\tPM_BR_2PATH___2 = 131126ULL,\n\tPM_BR_2PATH_ALT___2 = 262198ULL,\n\tPM_MRK_ST_DONE_L2 = 65844ULL,\n\tPM_RADIX_PWC_L1_HIT = 127062ULL,\n\tPM_FLOP_CMPL = 65780ULL,\n\tPM_MRK_NTF_FIN = 131346ULL,\n\tPM_RADIX_PWC_L2_HIT = 184356ULL,\n\tPM_IFETCH_THROTTLE = 213086ULL,\n\tPM_MRK_L2_TM_ST_ABORT_SISTER = 254300ULL,\n\tPM_RADIX_PWC_L3_HIT = 258134ULL,\n\tPM_RUN_CYC_SMT2_MODE = 196716ULL,\n\tPM_TM_TX_PASS_RUN_INST = 319508ULL,\n\tPM_DISP_HELD_SYNC_HOLD = 262204ULL,\n\tPM_DTLB_MISS_16G = 114776ULL,\n\tPM_DERAT_MISS_2M = 114778ULL,\n\tPM_DTLB_MISS_2M = 114780ULL,\n\tPM_MRK_DTLB_MISS_1G = 119132ULL,\n\tPM_DTLB_MISS_4K = 180310ULL,\n\tPM_DERAT_MISS_1G = 180314ULL,\n\tPM_MRK_DERAT_MISS_2M = 184658ULL,\n\tPM_MRK_DTLB_MISS_4K = 184662ULL,\n\tPM_MRK_DTLB_MISS_16G = 184670ULL,\n\tPM_DTLB_MISS_64K = 245846ULL,\n\tPM_MRK_DERAT_MISS_1G = 250194ULL,\n\tPM_MRK_DTLB_MISS_64K = 250198ULL,\n\tPM_DTLB_MISS_16M = 311382ULL,\n\tPM_DTLB_MISS_1G = 311386ULL,\n\tPM_MRK_DTLB_MISS_16M = 311646ULL,\n\tMEM_LOADS___2 = 224210977248ULL,\n\tMEM_STORES___2 = 224345194976ULL,\n};\n\nenum {\n\tPM_CYC_ALT = 30,\n};\n\nenum {\n\tPM_CYC_ALT___2 = 65776,\n\tPM_CYC_INST_CMPL = 65778,\n\tPM_FLOP_CMPL___2 = 65780,\n\tPM_L1_ITLB_MISS = 65782,\n\tPM_NO_INST_AVAIL = 65784,\n\tPM_LD_CMPL = 65788,\n\tPM_INST_CMPL_ALT = 65790,\n\tPM_ST_CMPL = 131312,\n\tPM_INST_DISP___3 = 131314,\n\tPM_RUN_CYC___3 = 131316,\n\tPM_L1_DTLB_RELOAD = 131318,\n\tPM_BR_TAKEN_CMPL = 131322,\n\tPM_L1_ICACHE_MISS___3 = 131324,\n\tPM_L1_RELOAD_FROM_MEM = 131326,\n\tPM_ST_MISS_L1___3 = 196848,\n\tPM_INST_DISP_ALT___3 = 196850,\n\tPM_BR_MISPREDICT = 196854,\n\tPM_DTLB_MISS___3 = 196860,\n\tPM_DATA_FROM_L3MISS___3 = 196862,\n\tPM_LD_MISS_L1___3 = 262384,\n\tPM_CYC_INST_DISP = 262386,\n\tPM_BR_MPRED_CMPL___4 = 262390,\n\tPM_RUN_INST_CMPL___3 = 262394,\n\tPM_ITLB_MISS___3 = 262396,\n\tPM_LD_NOT_CACHED = 262398,\n\tPM_INST_CMPL___3 = 327930,\n\tPM_CYC___4 = 393460,\n};\n\nenum {\n\tPM_DATA_FROM_L3___3 = 5418393301794880ULL,\n};\n\nenum {\n\tPM_DATA_FROM_L3MISS___4 = 196862,\n};\n\nenum {\n\tPM_DTLB_MISS___4 = 196860,\n};\n\nenum {\n\tPM_IC_DEMAND_L2_BR_ALL = 18584,\n\tPM_GCT_UTIL_7_TO_10_SLOTS = 8352,\n\tPM_PMC2_SAVED = 65570,\n\tPM_CMPLU_STALL_DFU = 131132,\n\tPM_VSU0_16FLOP = 41124,\n\tPM_MRK_LSU_DERAT_MISS = 249946,\n\tPM_MRK_ST_CMPL___2 = 65588,\n\tPM_NEST_PAIR3_ADD = 264321,\n\tPM_L2_ST_DISP = 287104,\n\tPM_L2_CASTOUT_MOD = 90496,\n\tPM_ISEG = 8356,\n\tPM_MRK_INST_TIMEO = 262196,\n\tPM_L2_RCST_DISP_FAIL_ADDR = 221826,\n\tPM_LSU1_DC_PREF_STREAM_CONFIRM = 53430,\n\tPM_IERAT_WR_64K = 16574,\n\tPM_MRK_DTLB_MISS_16M___2 = 315486,\n\tPM_IERAT_MISS = 65782,\n\tPM_MRK_PTEG_FROM_LMEM = 315474,\n\tPM_FLOP = 65780,\n\tPM_THRD_PRIO_4_5_CYC = 16564,\n\tPM_BR_PRED_TA = 16554,\n\tPM_CMPLU_STALL_FXU = 131092,\n\tPM_EXT_INT = 131320,\n\tPM_VSU_FSQRT_FDIV = 43144,\n\tPM_MRK_LD_MISS_EXPOSED_CYC = 65598,\n\tPM_LSU1_LDF = 49286,\n\tPM_IC_WRITE_ALL = 18572,\n\tPM_LSU0_SRQ_STFWD = 49312,\n\tPM_PTEG_FROM_RL2L3_MOD = 114770,\n\tPM_MRK_DATA_FROM_L31_SHR = 118862,\n\tPM_DATA_FROM_L21_MOD = 245830,\n\tPM_VSU1_SCAL_DOUBLE_ISSUED = 45194,\n\tPM_VSU0_8FLOP = 41120,\n\tPM_POWER_EVENT1 = 65646,\n\tPM_DISP_CLB_HELD_BAL = 8338,\n\tPM_VSU1_2FLOP = 41114,\n\tPM_LWSYNC_HELD = 8346,\n\tPM_PTEG_FROM_DL2L3_SHR = 245844,\n\tPM_INST_FROM_L21_MOD = 213062,\n\tPM_IERAT_XLATE_WR_16MPLUS = 16572,\n\tPM_IC_REQ_ALL = 18568,\n\tPM_DSLB_MISS = 53392,\n\tPM_L3_MISS = 127106,\n\tPM_LSU0_L1_PREF = 53432,\n\tPM_VSU_SCALAR_SINGLE_ISSUED = 47236,\n\tPM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE = 53438,\n\tPM_L2_INST = 221312,\n\tPM_VSU0_FRSP = 41140,\n\tPM_FLUSH_DISP = 8322,\n\tPM_PTEG_FROM_L2MISS = 311384,\n\tPM_VSU1_DQ_ISSUED = 45210,\n\tPM_CMPLU_STALL_LSU = 131090,\n\tPM_MRK_DATA_FROM_DMEM = 118858,\n\tPM_LSU_FLUSH_ULD = 51376,\n\tPM_PTEG_FROM_LMEM = 311378,\n\tPM_MRK_DERAT_MISS_16M = 249948,\n\tPM_THRD_ALL_RUN_CYC = 131084,\n\tPM_MEM0_PREFETCH_DISP = 131203,\n\tPM_MRK_STALL_CMPLU_CYC_COUNT = 196671,\n\tPM_DATA_FROM_DL2L3_MOD = 245836,\n\tPM_VSU_FRSP = 43188,\n\tPM_MRK_DATA_FROM_L21_MOD = 249926,\n\tPM_PMC1_OVERFLOW = 131088,\n\tPM_VSU0_SINGLE = 41128,\n\tPM_MRK_PTEG_FROM_L3MISS = 184408,\n\tPM_MRK_PTEG_FROM_L31_SHR = 184406,\n\tPM_VSU0_VECTOR_SP_ISSUED = 45200,\n\tPM_VSU1_FEST = 41146,\n\tPM_MRK_INST_DISP = 131120,\n\tPM_VSU0_COMPLEX_ISSUED = 45206,\n\tPM_LSU1_FLUSH_UST = 49334,\n\tPM_INST_CMPL___4 = 2,\n\tPM_FXU_IDLE = 65550,\n\tPM_LSU0_FLUSH_ULD = 49328,\n\tPM_MRK_DATA_FROM_DL2L3_MOD = 249932,\n\tPM_LSU_LMQ_SRQ_EMPTY_ALL_CYC = 196636,\n\tPM_LSU1_REJECT_LMQ_FULL = 49318,\n\tPM_INST_PTEG_FROM_L21_MOD = 254038,\n\tPM_INST_FROM_RL2L3_MOD = 81986,\n\tPM_SHL_CREATED = 20610,\n\tPM_L2_ST_HIT = 287106,\n\tPM_DATA_FROM_DMEM = 114762,\n\tPM_L3_LD_MISS = 192642,\n\tPM_FXU1_BUSY_FXU0_IDLE = 262158,\n\tPM_DISP_CLB_HELD_RES = 8340,\n\tPM_L2_SN_SX_I_DONE = 222082,\n\tPM_GRP_CMPL = 196612,\n\tPM_STCX_CMPL = 49304,\n\tPM_VSU0_2FLOP = 41112,\n\tPM_L3_PREF_MISS = 258178,\n\tPM_LSU_SRQ_SYNC_CYC = 53398,\n\tPM_LSU_REJECT_ERAT_MISS = 131172,\n\tPM_L1_ICACHE_MISS___4 = 131324,\n\tPM_LSU1_FLUSH_SRQ = 49342,\n\tPM_LD_REF_L1_LSU0 = 49280,\n\tPM_VSU0_FEST = 41144,\n\tPM_VSU_VECTOR_SINGLE_ISSUED = 47248,\n\tPM_FREQ_UP = 262156,\n\tPM_DATA_FROM_LMEM = 245834,\n\tPM_LSU1_LDX = 49290,\n\tPM_PMC3_OVERFLOW = 262160,\n\tPM_MRK_BR_MPRED = 196662,\n\tPM_SHL_MATCH = 20614,\n\tPM_MRK_BR_TAKEN = 65590,\n\tPM_CMPLU_STALL_BRU = 262222,\n\tPM_ISLB_MISS = 53394,\n\tPM_CYC___5 = 30,\n\tPM_DISP_HELD_THERMAL = 196614,\n\tPM_INST_PTEG_FROM_RL2L3_SHR = 188500,\n\tPM_LSU1_SRQ_STFWD = 49314,\n\tPM_GCT_NOSLOT_BR_MPRED = 262170,\n\tPM_1PLUS_PPC_CMPL = 65778,\n\tPM_PTEG_FROM_DMEM = 180306,\n\tPM_VSU_2FLOP = 43160,\n\tPM_GCT_FULL_CYC = 16518,\n\tPM_MRK_DATA_FROM_L3_CYC = 262176,\n\tPM_LSU_SRQ_S0_ALLOC = 53405,\n\tPM_MRK_DERAT_MISS_4K = 118876,\n\tPM_BR_MPRED_TA = 16558,\n\tPM_INST_PTEG_FROM_L2MISS = 319576,\n\tPM_DPU_HELD_POWER = 131078,\n\tPM_RUN_INST_CMPL___4 = 262394,\n\tPM_MRK_VSU_FIN = 196658,\n\tPM_LSU_SRQ_S0_VALID = 53404,\n\tPM_GCT_EMPTY_CYC = 131080,\n\tPM_IOPS_DISP = 196628,\n\tPM_RUN_SPURR = 65544,\n\tPM_PTEG_FROM_L21_MOD = 245846,\n\tPM_VSU0_1FLOP = 41088,\n\tPM_SNOOP_TLBIE = 53426,\n\tPM_DATA_FROM_L3MISS___5 = 180296,\n\tPM_VSU_SINGLE = 43176,\n\tPM_DTLB_MISS_16G___2 = 114782,\n\tPM_CMPLU_STALL_VECTOR = 131100,\n\tPM_FLUSH = 262392,\n\tPM_L2_LD_HIT = 221570,\n\tPM_NEST_PAIR2_AND = 198787,\n\tPM_VSU1_1FLOP = 41090,\n\tPM_IC_PREF_REQ = 16522,\n\tPM_L3_LD_HIT = 192640,\n\tPM_GCT_NOSLOT_IC_MISS = 131098,\n\tPM_DISP_HELD = 65542,\n\tPM_L2_LD = 90240,\n\tPM_LSU_FLUSH_SRQ = 51388,\n\tPM_BC_PLUS_8_CONV = 16568,\n\tPM_MRK_DATA_FROM_L31_MOD_CYC = 262182,\n\tPM_CMPLU_STALL_VECTOR_LONG = 262218,\n\tPM_L2_RCST_BUSY_RC_FULL = 156290,\n\tPM_TB_BIT_TRANS = 196856,\n\tPM_THERMAL_MAX = 262150,\n\tPM_LSU1_FLUSH_ULD = 49330,\n\tPM_LSU1_REJECT_LHS = 49326,\n\tPM_LSU_LRQ_S0_ALLOC = 53407,\n\tPM_L3_CO_L31 = 323712,\n\tPM_POWER_EVENT4 = 262254,\n\tPM_DATA_FROM_L31_SHR = 114766,\n\tPM_BR_UNCOND = 16542,\n\tPM_LSU1_DC_PREF_STREAM_ALLOC = 53418,\n\tPM_PMC4_REWIND = 65568,\n\tPM_L2_RCLD_DISP = 90752,\n\tPM_THRD_PRIO_2_3_CYC = 16562,\n\tPM_MRK_PTEG_FROM_L2MISS = 315480,\n\tPM_IC_DEMAND_L2_BHT_REDIRECT = 16536,\n\tPM_LSU_DERAT_MISS = 131318,\n\tPM_IC_PREF_CANCEL_L2 = 16532,\n\tPM_MRK_FIN_STALL_CYC_COUNT = 65597,\n\tPM_BR_PRED_CCACHE = 16544,\n\tPM_GCT_UTIL_1_TO_2_SLOTS = 8348,\n\tPM_MRK_ST_CMPL_INT = 196660,\n\tPM_LSU_TWO_TABLEWALK_CYC = 53414,\n\tPM_MRK_DATA_FROM_L3MISS = 184392,\n\tPM_GCT_NOSLOT_CYC___2 = 65784,\n\tPM_LSU_SET_MPRED = 49320,\n\tPM_FLUSH_DISP_TLBIE = 8330,\n\tPM_VSU1_FCONV = 41138,\n\tPM_DERAT_MISS_16G = 311388,\n\tPM_INST_FROM_LMEM = 213066,\n\tPM_IC_DEMAND_L2_BR_REDIRECT = 16538,\n\tPM_CMPLU_STALL_SCALAR_LONG = 131096,\n\tPM_INST_PTEG_FROM_L2 = 122960,\n\tPM_PTEG_FROM_L2 = 114768,\n\tPM_MRK_DATA_FROM_L21_SHR_CYC = 131108,\n\tPM_MRK_DTLB_MISS_4K___2 = 184410,\n\tPM_VSU0_FPSCR = 45212,\n\tPM_VSU1_VECT_DOUBLE_ISSUED = 45186,\n\tPM_MRK_PTEG_FROM_RL2L3_MOD = 118866,\n\tPM_MEM0_RQ_DISP = 65667,\n\tPM_L2_LD_MISS = 155776,\n\tPM_VMX_RESULT_SAT_1 = 45216,\n\tPM_L1_PREF___3 = 55480,\n\tPM_MRK_DATA_FROM_LMEM_CYC = 131116,\n\tPM_GRP_IC_MISS_NONSPEC = 65548,\n\tPM_PB_NODE_PUMP = 65665,\n\tPM_SHL_MERGED = 20612,\n\tPM_NEST_PAIR1_ADD = 133249,\n\tPM_DATA_FROM_L3___4 = 114760,\n\tPM_LSU_FLUSH = 8334,\n\tPM_LSU_SRQ_SYNC_COUNT = 53399,\n\tPM_PMC2_OVERFLOW = 196624,\n\tPM_LSU_LDF = 51332,\n\tPM_POWER_EVENT3 = 196718,\n\tPM_DISP_WT = 196616,\n\tPM_CMPLU_STALL_REJECT = 262166,\n\tPM_IC_BANK_CONFLICT = 16514,\n\tPM_BR_MPRED_CR_TA = 18606,\n\tPM_L2_INST_MISS = 221314,\n\tPM_CMPLU_STALL_ERAT_MISS = 262168,\n\tPM_NEST_PAIR2_ADD = 198785,\n\tPM_MRK_LSU_FLUSH = 53388,\n\tPM_L2_LDST = 92288,\n\tPM_INST_FROM_L31_SHR = 81998,\n\tPM_VSU0_FIN = 41148,\n\tPM_LARX_LSU = 51348,\n\tPM_INST_FROM_RMEM = 213058,\n\tPM_DISP_CLB_HELD_TLBIE = 8342,\n\tPM_MRK_DATA_FROM_DMEM_CYC = 131118,\n\tPM_BR_PRED_CR = 16552,\n\tPM_LSU_REJECT = 65636,\n\tPM_GCT_UTIL_3_TO_6_SLOTS = 8350,\n\tPM_CMPLU_STALL_END_GCT_NOSLOT = 65576,\n\tPM_LSU0_REJECT_LMQ_FULL = 49316,\n\tPM_VSU_FEST = 43192,\n\tPM_NEST_PAIR0_AND = 67715,\n\tPM_PTEG_FROM_L3 = 180304,\n\tPM_POWER_EVENT2 = 131182,\n\tPM_IC_PREF_CANCEL_PAGE = 16528,\n\tPM_VSU0_FSQRT_FDIV = 41096,\n\tPM_MRK_GRP_CMPL = 262192,\n\tPM_VSU0_SCAL_DOUBLE_ISSUED = 45192,\n\tPM_GRP_DISP = 196618,\n\tPM_LSU0_LDX = 49288,\n\tPM_DATA_FROM_L2 = 114752,\n\tPM_MRK_DATA_FROM_RL2L3_MOD = 118850,\n\tPM_LD_REF_L1___3 = 51328,\n\tPM_VSU0_VECT_DOUBLE_ISSUED = 45184,\n\tPM_VSU1_2FLOP_DOUBLE = 41102,\n\tPM_THRD_PRIO_6_7_CYC = 16566,\n\tPM_BC_PLUS_8_RSLV_TAKEN = 16570,\n\tPM_BR_MPRED_CR = 16556,\n\tPM_L3_CO_MEM = 323714,\n\tPM_LD_MISS_L1___4 = 262384,\n\tPM_DATA_FROM_RL2L3_MOD = 114754,\n\tPM_LSU_SRQ_FULL_CYC = 65562,\n\tPM_TABLEWALK_CYC = 65574,\n\tPM_MRK_PTEG_FROM_RMEM = 249938,\n\tPM_LSU_SRQ_STFWD = 51360,\n\tPM_INST_PTEG_FROM_RMEM = 254034,\n\tPM_FXU0_FIN = 65540,\n\tPM_LSU1_L1_SW_PREF = 49310,\n\tPM_PTEG_FROM_L31_MOD = 114772,\n\tPM_PMC5_OVERFLOW = 65572,\n\tPM_LD_REF_L1_LSU1 = 49282,\n\tPM_INST_PTEG_FROM_L21_SHR = 319574,\n\tPM_CMPLU_STALL_THRD = 65564,\n\tPM_DATA_FROM_RMEM = 245826,\n\tPM_VSU0_SCAL_SINGLE_ISSUED = 45188,\n\tPM_BR_MPRED_LSTACK = 16550,\n\tPM_MRK_DATA_FROM_RL2L3_MOD_CYC = 262184,\n\tPM_LSU0_FLUSH_UST = 49332,\n\tPM_LSU_NCST = 49296,\n\tPM_BR_TAKEN = 131076,\n\tPM_INST_PTEG_FROM_LMEM = 319570,\n\tPM_GCT_NOSLOT_BR_MPRED_IC_MISS = 262172,\n\tPM_DTLB_MISS_4K___2 = 180314,\n\tPM_PMC4_SAVED = 196642,\n\tPM_VSU1_PERMUTE_ISSUED = 45202,\n\tPM_SLB_MISS = 55440,\n\tPM_LSU1_FLUSH_LRQ = 49338,\n\tPM_DTLB_MISS___5 = 196860,\n\tPM_VSU1_FRSP = 41142,\n\tPM_VSU_VECTOR_DOUBLE_ISSUED = 47232,\n\tPM_L2_CASTOUT_SHR = 90498,\n\tPM_DATA_FROM_DL2L3_SHR = 245828,\n\tPM_VSU1_STF = 45198,\n\tPM_ST_FIN = 131312,\n\tPM_PTEG_FROM_L21_SHR = 311382,\n\tPM_L2_LOC_GUESS_WRONG = 156800,\n\tPM_MRK_STCX_FAIL = 53390,\n\tPM_LSU0_REJECT_LHS = 49324,\n\tPM_IC_PREF_CANCEL_HIT = 16530,\n\tPM_L3_PREF_BUSY = 323712,\n\tPM_MRK_BRU_FIN = 131130,\n\tPM_LSU1_NCLD = 49294,\n\tPM_INST_PTEG_FROM_L31_MOD = 122964,\n\tPM_LSU_NCLD = 51340,\n\tPM_LSU_LDX = 51336,\n\tPM_L2_LOC_GUESS_CORRECT = 91264,\n\tPM_THRESH_TIMEO = 65592,\n\tPM_L3_PREF_ST = 53422,\n\tPM_DISP_CLB_HELD_SYNC = 8344,\n\tPM_VSU_SIMPLE_ISSUED = 47252,\n\tPM_VSU1_SINGLE = 41130,\n\tPM_DATA_TABLEWALK_CYC = 196634,\n\tPM_L2_RC_ST_DONE = 222080,\n\tPM_MRK_PTEG_FROM_L21_MOD = 249942,\n\tPM_LARX_LSU1 = 49302,\n\tPM_MRK_DATA_FROM_RMEM = 249922,\n\tPM_DISP_CLB_HELD = 8336,\n\tPM_DERAT_MISS_4K = 114780,\n\tPM_L2_RCLD_DISP_FAIL_ADDR = 90754,\n\tPM_SEG_EXCEPTION = 10404,\n\tPM_FLUSH_DISP_SB = 8332,\n\tPM_L2_DC_INV = 156034,\n\tPM_PTEG_FROM_DL2L3_MOD = 311380,\n\tPM_DSEG = 8358,\n\tPM_BR_PRED_LSTACK = 16546,\n\tPM_VSU0_STF = 45196,\n\tPM_LSU_FX_FIN = 65638,\n\tPM_DERAT_MISS_16M = 245852,\n\tPM_MRK_PTEG_FROM_DL2L3_MOD = 315476,\n\tPM_GCT_UTIL_11_PLUS_SLOTS = 8354,\n\tPM_INST_FROM_L3 = 81992,\n\tPM_MRK_IFU_FIN = 196666,\n\tPM_ITLB_MISS___4 = 262396,\n\tPM_VSU_STF = 47244,\n\tPM_LSU_FLUSH_UST = 51380,\n\tPM_L2_LDST_MISS = 157824,\n\tPM_FXU1_FIN = 262148,\n\tPM_SHL_DEALLOCATED = 20608,\n\tPM_L2_SN_M_WR_DONE = 287618,\n\tPM_LSU_REJECT_SET_MPRED = 51368,\n\tPM_L3_PREF_LD = 53420,\n\tPM_L2_SN_M_RD_DONE = 287616,\n\tPM_MRK_DERAT_MISS_16G = 315484,\n\tPM_VSU_FCONV = 43184,\n\tPM_ANY_THRD_RUN_CYC = 65786,\n\tPM_LSU_LMQ_FULL_CYC = 53412,\n\tPM_MRK_LSU_REJECT_LHS = 53378,\n\tPM_MRK_LD_MISS_L1_CYC = 262206,\n\tPM_MRK_DATA_FROM_L2_CYC = 131104,\n\tPM_INST_IMC_MATCH_DISP = 196630,\n\tPM_MRK_DATA_FROM_RMEM_CYC = 262188,\n\tPM_VSU0_SIMPLE_ISSUED = 45204,\n\tPM_CMPLU_STALL_DIV = 262164,\n\tPM_MRK_PTEG_FROM_RL2L3_SHR = 184404,\n\tPM_VSU_FMA_DOUBLE = 43152,\n\tPM_VSU_4FLOP = 43164,\n\tPM_VSU1_FIN = 41150,\n\tPM_NEST_PAIR1_AND = 133251,\n\tPM_INST_PTEG_FROM_RL2L3_MOD = 122962,\n\tPM_RUN_CYC___4 = 131316,\n\tPM_PTEG_FROM_RMEM = 245842,\n\tPM_LSU_LRQ_S0_VALID = 53406,\n\tPM_LSU0_LDF = 49284,\n\tPM_FLUSH_COMPLETION = 196626,\n\tPM_ST_MISS_L1___4 = 196848,\n\tPM_L2_NODE_PUMP = 222336,\n\tPM_INST_FROM_DL2L3_SHR = 213060,\n\tPM_MRK_STALL_CMPLU_CYC = 196670,\n\tPM_VSU1_DENORM = 41134,\n\tPM_MRK_DATA_FROM_L31_SHR_CYC = 131110,\n\tPM_NEST_PAIR0_ADD = 67713,\n\tPM_INST_FROM_L3MISS = 147528,\n\tPM_EE_OFF_EXT_INT = 8320,\n\tPM_INST_PTEG_FROM_DMEM = 188498,\n\tPM_INST_FROM_DL2L3_MOD = 213068,\n\tPM_PMC6_OVERFLOW = 196644,\n\tPM_VSU_2FLOP_DOUBLE = 43148,\n\tPM_TLB_MISS = 131174,\n\tPM_FXU_BUSY = 131086,\n\tPM_L2_RCLD_DISP_FAIL_OTHER = 156288,\n\tPM_LSU_REJECT_LMQ_FULL = 51364,\n\tPM_IC_RELOAD_SHR = 16534,\n\tPM_GRP_MRK = 65585,\n\tPM_MRK_ST_NEST = 131124,\n\tPM_VSU1_FSQRT_FDIV = 41098,\n\tPM_LSU0_FLUSH_LRQ = 49336,\n\tPM_LARX_LSU0 = 49300,\n\tPM_IBUF_FULL_CYC = 16516,\n\tPM_MRK_DATA_FROM_DL2L3_SHR_CYC = 131114,\n\tPM_LSU_DC_PREF_STREAM_ALLOC = 55464,\n\tPM_GRP_MRK_CYC = 65584,\n\tPM_MRK_DATA_FROM_RL2L3_SHR_CYC = 131112,\n\tPM_L2_GLOB_GUESS_CORRECT = 91266,\n\tPM_LSU_REJECT_LHS = 51372,\n\tPM_MRK_DATA_FROM_LMEM = 249930,\n\tPM_INST_PTEG_FROM_L3 = 188496,\n\tPM_FREQ_DOWN = 196620,\n\tPM_PB_RETRY_NODE_PUMP = 196737,\n\tPM_INST_FROM_RL2L3_SHR = 81996,\n\tPM_MRK_INST_ISSUED = 65586,\n\tPM_PTEG_FROM_L3MISS = 180312,\n\tPM_RUN_PURR = 262388,\n\tPM_MRK_GRP_IC_MISS = 262200,\n\tPM_MRK_DATA_FROM_L3 = 118856,\n\tPM_CMPLU_STALL_DCACHE_MISS = 131094,\n\tPM_PTEG_FROM_RL2L3_SHR = 180308,\n\tPM_LSU_FLUSH_LRQ = 51384,\n\tPM_MRK_DERAT_MISS_64K = 184412,\n\tPM_INST_PTEG_FROM_DL2L3_MOD = 319572,\n\tPM_L2_ST_MISS___3 = 155778,\n\tPM_MRK_PTEG_FROM_L21_SHR = 315478,\n\tPM_LWSYNC = 53396,\n\tPM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE = 53436,\n\tPM_MRK_LSU_FLUSH_LRQ = 53384,\n\tPM_INST_IMC_MATCH_CMPL = 65776,\n\tPM_NEST_PAIR3_AND = 264323,\n\tPM_PB_RETRY_SYS_PUMP = 262273,\n\tPM_MRK_INST_FIN = 196656,\n\tPM_MRK_PTEG_FROM_DL2L3_SHR = 249940,\n\tPM_INST_FROM_L31_MOD = 81988,\n\tPM_MRK_DTLB_MISS_64K___2 = 249950,\n\tPM_LSU_FIN = 196710,\n\tPM_MRK_LSU_REJECT = 262244,\n\tPM_L2_CO_FAIL_BUSY = 91010,\n\tPM_MEM0_WQ_DISP = 262275,\n\tPM_DATA_FROM_L31_MOD = 114756,\n\tPM_THERMAL_WARN = 65558,\n\tPM_VSU0_4FLOP = 41116,\n\tPM_BR_MPRED_CCACHE = 16548,\n\tPM_CMPLU_STALL_IFU = 262220,\n\tPM_L1_DEMAND_WRITE___3 = 16524,\n\tPM_FLUSH_BR_MPRED = 8324,\n\tPM_MRK_DTLB_MISS_16G___2 = 118878,\n\tPM_MRK_PTEG_FROM_DMEM = 184402,\n\tPM_L2_RCST_DISP = 221824,\n\tPM_CMPLU_STALL___3 = 262154,\n\tPM_LSU_PARTIAL_CDF = 49322,\n\tPM_DISP_CLB_HELD_SB = 8360,\n\tPM_VSU0_FMA_DOUBLE = 41104,\n\tPM_FXU0_BUSY_FXU1_IDLE = 196622,\n\tPM_IC_DEMAND_CYC = 65560,\n\tPM_MRK_DATA_FROM_L21_SHR = 249934,\n\tPM_MRK_LSU_FLUSH_UST = 53382,\n\tPM_INST_PTEG_FROM_L3MISS = 188504,\n\tPM_VSU_DENORM = 43180,\n\tPM_MRK_LSU_PARTIAL_CDF = 53376,\n\tPM_INST_FROM_L21_SHR = 213070,\n\tPM_IC_PREF_WRITE___3 = 16526,\n\tPM_BR_PRED = 16540,\n\tPM_INST_FROM_DMEM = 81994,\n\tPM_IC_PREF_CANCEL_ALL = 18576,\n\tPM_LSU_DC_PREF_STREAM_CONFIRM = 55476,\n\tPM_MRK_LSU_FLUSH_SRQ = 53386,\n\tPM_MRK_FIN_STALL_CYC = 65596,\n\tPM_L2_RCST_DISP_FAIL_OTHER = 287360,\n\tPM_VSU1_DD_ISSUED = 45208,\n\tPM_PTEG_FROM_L31_SHR = 180310,\n\tPM_DATA_FROM_L21_SHR = 245838,\n\tPM_LSU0_NCLD = 49292,\n\tPM_VSU1_4FLOP = 41118,\n\tPM_VSU1_8FLOP = 41122,\n\tPM_VSU_8FLOP = 43168,\n\tPM_LSU_LMQ_SRQ_EMPTY_CYC = 131134,\n\tPM_DTLB_MISS_64K___2 = 245854,\n\tPM_THRD_CONC_RUN_INST = 196852,\n\tPM_MRK_PTEG_FROM_L2 = 118864,\n\tPM_PB_SYS_PUMP = 131201,\n\tPM_VSU_FIN = 43196,\n\tPM_MRK_DATA_FROM_L31_MOD = 118852,\n\tPM_THRD_PRIO_0_1_CYC = 16560,\n\tPM_DERAT_MISS_64K = 180316,\n\tPM_PMC2_REWIND = 196640,\n\tPM_INST_FROM_L2 = 81984,\n\tPM_GRP_BR_MPRED_NONSPEC = 65546,\n\tPM_INST_DISP___4 = 131314,\n\tPM_MEM0_RD_CANCEL_TOTAL = 196739,\n\tPM_LSU0_DC_PREF_STREAM_CONFIRM = 53428,\n\tPM_L1_DCACHE_RELOAD_VALID = 196854,\n\tPM_VSU_SCALAR_DOUBLE_ISSUED = 47240,\n\tPM_L3_PREF_HIT = 258176,\n\tPM_MRK_PTEG_FROM_L31_MOD = 118868,\n\tPM_CMPLU_STALL_STORE = 131146,\n\tPM_MRK_FXU_FIN = 131128,\n\tPM_PMC4_OVERFLOW = 65552,\n\tPM_MRK_PTEG_FROM_L3 = 184400,\n\tPM_LSU0_LMQ_LHR_MERGE = 53400,\n\tPM_BTAC_HIT = 20618,\n\tPM_L3_RD_BUSY = 323714,\n\tPM_LSU0_L1_SW_PREF = 49308,\n\tPM_INST_FROM_L2MISS = 278600,\n\tPM_LSU0_DC_PREF_STREAM_ALLOC = 53416,\n\tPM_L2_ST___3 = 90242,\n\tPM_VSU0_DENORM = 41132,\n\tPM_MRK_DATA_FROM_DL2L3_SHR = 249924,\n\tPM_BR_PRED_CR_TA = 18602,\n\tPM_VSU0_FCONV = 41136,\n\tPM_MRK_LSU_FLUSH_ULD = 53380,\n\tPM_BTAC_MISS = 20616,\n\tPM_MRK_LD_MISS_EXPOSED_CYC_COUNT = 65599,\n\tPM_MRK_DATA_FROM_L2 = 118848,\n\tPM_LSU_DCACHE_RELOAD_VALID = 53410,\n\tPM_VSU_FMA = 43140,\n\tPM_LSU0_FLUSH_SRQ = 49340,\n\tPM_LSU1_L1_PREF = 53434,\n\tPM_IOPS_CMPL = 65556,\n\tPM_L2_SYS_PUMP = 222338,\n\tPM_L2_RCLD_BUSY_RC_FULL = 287362,\n\tPM_LSU_LMQ_S0_ALLOC = 53409,\n\tPM_FLUSH_DISP_SYNC = 8328,\n\tPM_MRK_DATA_FROM_DL2L3_MOD_CYC = 262186,\n\tPM_L2_IC_INV = 156032,\n\tPM_MRK_DATA_FROM_L21_MOD_CYC = 262180,\n\tPM_L3_PREF_LDST = 55468,\n\tPM_LSU_SRQ_EMPTY_CYC = 262152,\n\tPM_LSU_LMQ_S0_VALID = 53408,\n\tPM_FLUSH_PARTIAL = 8326,\n\tPM_VSU1_FMA_DOUBLE = 41106,\n\tPM_1PLUS_PPC_DISP = 262386,\n\tPM_DATA_FROM_L2MISS = 131326,\n\tPM_SUSPENDED = 0,\n\tPM_VSU0_FMA = 41092,\n\tPM_CMPLU_STALL_SCALAR = 262162,\n\tPM_STCX_FAIL = 49306,\n\tPM_VSU0_FSQRT_FDIV_DOUBLE = 41108,\n\tPM_DC_PREF_DST = 53424,\n\tPM_VSU1_SCAL_SINGLE_ISSUED = 45190,\n\tPM_L3_HIT = 127104,\n\tPM_L2_GLOB_GUESS_WRONG = 156802,\n\tPM_MRK_DFU_FIN = 131122,\n\tPM_INST_FROM_L1___3 = 16512,\n\tPM_BRU_FIN___2 = 65640,\n\tPM_IC_DEMAND_REQ = 16520,\n\tPM_VSU1_FSQRT_FDIV_DOUBLE = 41110,\n\tPM_VSU1_FMA = 41094,\n\tPM_MRK_LD_MISS_L1 = 131126,\n\tPM_VSU0_2FLOP_DOUBLE = 41100,\n\tPM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM = 55484,\n\tPM_INST_PTEG_FROM_L31_SHR = 188502,\n\tPM_MRK_LSU_REJECT_ERAT_MISS = 196708,\n\tPM_MRK_DATA_FROM_L2MISS___2 = 315464,\n\tPM_DATA_FROM_RL2L3_SHR = 114764,\n\tPM_INST_FROM_PREF = 81990,\n\tPM_VSU1_SQ = 45214,\n\tPM_L2_LD_DISP = 221568,\n\tPM_L2_DISP_ALL = 286848,\n\tPM_THRD_GRP_CMPL_BOTH_CYC = 65554,\n\tPM_VSU_FSQRT_FDIV_DOUBLE = 43156,\n\tPM_BR_MPRED = 262390,\n\tPM_INST_PTEG_FROM_DL2L3_SHR = 254036,\n\tPM_VSU_1FLOP = 43136,\n\tPM_HV_CYC = 131082,\n\tPM_MRK_LSU_FIN = 262194,\n\tPM_MRK_DATA_FROM_RL2L3_SHR = 118860,\n\tPM_DTLB_MISS_16M___2 = 311390,\n\tPM_LSU1_LMQ_LHR_MERGE = 53402,\n\tPM_IFU_FIN = 262246,\n\tPM_1THRD_CON_RUN_INSTR = 196706,\n\tPM_CMPLU_STALL_COUNT = 262155,\n\tPM_MEM0_PB_RD_CL = 196739,\n\tPM_THRD_1_RUN_CYC = 65632,\n\tPM_THRD_2_CONC_RUN_INSTR = 262242,\n\tPM_THRD_2_RUN_CYC = 131168,\n\tPM_THRD_3_CONC_RUN_INST = 65634,\n\tPM_THRD_3_RUN_CYC = 196704,\n\tPM_THRD_4_CONC_RUN_INST = 131170,\n\tPM_THRD_4_RUN_CYC = 262240,\n};\n\nenum {\n\tPM_IC_PREF_REQ___2 = 16544,\n};\n\nenum {\n\tPM_INST_CMPL___5 = 327930,\n};\n\nenum {\n\tPM_INST_CMPL_ALT___2 = 2,\n};\n\nenum {\n\tPM_INST_FROM_L1___4 = 16512,\n};\n\nenum {\n\tPM_INST_FROM_L1MISS = 17732923532886080ULL,\n};\n\nenum {\n\tPM_ITLB_MISS___5 = 262396,\n};\n\nenum {\n\tPM_L1_ICACHE_MISS___5 = 131324,\n};\n\nenum {\n\tPM_L2_ST___4 = 1099511914624ULL,\n};\n\nenum {\n\tPM_L2_ST_MISS___4 = 157824,\n};\n\nenum {\n\tPM_L3_PF_MISS_L3 = 17592186134656ULL,\n};\n\nenum {\n\tPM_LD_DEMAND_MISS_L1_FIN = 262384,\n};\n\nenum {\n\tPM_LD_MISS_L1___5 = 254036,\n};\n\nenum {\n\tPM_LD_PREFETCH_CACHE_LINE_MISS = 65580,\n};\n\nenum {\n\tPM_LD_REF_L1___4 = 65788,\n};\n\nenum {\n\tPM_MPRED_BR_FIN = 254104,\n};\n\nenum {\n\tPM_ST_MISS_L1___5 = 196848,\n};\n\nenum {\n\tPNFS_BDEV_REGISTERED = 0,\n};\n\nenum {\n\tPOLICYDB_CAP_NETPEER = 0,\n\tPOLICYDB_CAP_OPENPERM = 1,\n\tPOLICYDB_CAP_EXTSOCKCLASS = 2,\n\tPOLICYDB_CAP_ALWAYSNETWORK = 3,\n\tPOLICYDB_CAP_CGROUPSECLABEL = 4,\n\tPOLICYDB_CAP_NNP_NOSUID_TRANSITION = 5,\n\tPOLICYDB_CAP_GENFS_SECLABEL_SYMLINKS = 6,\n\tPOLICYDB_CAP_IOCTL_SKIP_CLOEXEC = 7,\n\tPOLICYDB_CAP_USERSPACE_INITIAL_CONTEXT = 8,\n\tPOLICYDB_CAP_NETLINK_XPERM = 9,\n\tPOLICYDB_CAP_NETIF_WILDCARD = 10,\n\tPOLICYDB_CAP_GENFS_SECLABEL_WILDCARD = 11,\n\tPOLICYDB_CAP_FUNCTIONFS_SECLABEL = 12,\n\tPOLICYDB_CAP_MEMFD_CLASS = 13,\n\tPOLICYDB_CAP_BPF_TOKEN_PERMS = 14,\n\t__POLICYDB_CAP_MAX = 15,\n};\n\nenum {\n\tPOOL_BITS = 256,\n\tPOOL_READY_BITS = 256,\n\tPOOL_EARLY_BITS = 128,\n};\n\nenum {\n\tPOWERON_SECS = 3,\n};\n\nenum {\n\tPREFIX_UNSPEC = 0,\n\tPREFIX_ADDRESS = 1,\n\tPREFIX_CACHEINFO = 2,\n\t__PREFIX_MAX = 3,\n};\n\nenum {\n\tPROCESSOR_BUS_TOPOLOGY = 0,\n\tPROCESSOR_CONFIG = 1,\n\tAFFINITY_DOMAIN_VIA_VP = 2,\n\tAFFINITY_DOMAIN_VIA_DOM = 3,\n\tAFFINITY_DOMAIN_VIA_PAR = 4,\n};\n\nenum {\n\tPROCESS_BPF_EXIT = 1,\n};\n\nenum {\n\tPROCESS_SPIN_LOCK = 1,\n\tPROCESS_RES_LOCK = 2,\n\tPROCESS_LOCK_IRQ = 4,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n\tPROC_ENTRY_proc_read_iter = 2,\n\tPROC_ENTRY_proc_compat_ioctl = 4,\n\tPROC_ENTRY_proc_lseek = 8,\n\tPROC_ENTRY_FORCE_LOOKUP = 128,\n};\n\nenum {\n\tQCFG_RX_PAGE_SIZE = 1,\n};\n\nenum {\n\tQUEUE_FLAG_DYING = 0,\n\tQUEUE_FLAG_NOMERGES = 1,\n\tQUEUE_FLAG_SAME_COMP = 2,\n\tQUEUE_FLAG_FAIL_IO = 3,\n\tQUEUE_FLAG_NOXMERGES = 4,\n\tQUEUE_FLAG_SAME_FORCE = 5,\n\tQUEUE_FLAG_INIT_DONE = 6,\n\tQUEUE_FLAG_STATS = 7,\n\tQUEUE_FLAG_REGISTERED = 8,\n\tQUEUE_FLAG_QUIESCED = 9,\n\tQUEUE_FLAG_RQ_ALLOC_TIME = 10,\n\tQUEUE_FLAG_HCTX_ACTIVE = 11,\n\tQUEUE_FLAG_SQ_SCHED = 12,\n\tQUEUE_FLAG_DISABLE_WBT_DEF = 13,\n\tQUEUE_FLAG_NO_ELV_SWITCH = 14,\n\tQUEUE_FLAG_QOS_ENABLED = 15,\n\tQUEUE_FLAG_BIO_ISSUE_TIME = 16,\n\tQUEUE_FLAG_MAX = 17,\n};\n\nenum {\n\tQ_REQUEUE_PI_NONE = 0,\n\tQ_REQUEUE_PI_IGNORE = 1,\n\tQ_REQUEUE_PI_IN_PROGRESS = 2,\n\tQ_REQUEUE_PI_WAIT = 3,\n\tQ_REQUEUE_PI_DONE = 4,\n\tQ_REQUEUE_PI_LOCKED = 5,\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nenum {\n\tRB_ADD_STAMP_NONE = 0,\n\tRB_ADD_STAMP_EXTEND = 2,\n\tRB_ADD_STAMP_ABSOLUTE = 4,\n\tRB_ADD_STAMP_FORCE = 8,\n};\n\nenum {\n\tRB_CTX_TRANSITION = 0,\n\tRB_CTX_NMI = 1,\n\tRB_CTX_IRQ = 2,\n\tRB_CTX_SOFTIRQ = 3,\n\tRB_CTX_NORMAL = 4,\n\tRB_CTX_MAX = 5,\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nenum {\n\tREASON_BOUNDS = -1,\n\tREASON_TYPE = -2,\n\tREASON_PATHS = -3,\n\tREASON_LIMIT = -4,\n\tREASON_STACK = -5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nenum {\n\tRELAY_STATS_BUF_FULL = 1,\n\tRELAY_STATS_WRT_BIG = 2,\n\tRELAY_STATS_LAST = 2,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 5000,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1ULL,\n\tREQ_F_IO_DRAIN = 2ULL,\n\tREQ_F_LINK = 4ULL,\n\tREQ_F_HARDLINK = 8ULL,\n\tREQ_F_FORCE_ASYNC = 16ULL,\n\tREQ_F_BUFFER_SELECT = 32ULL,\n\tREQ_F_CQE_SKIP = 64ULL,\n\tREQ_F_FAIL = 256ULL,\n\tREQ_F_INFLIGHT = 512ULL,\n\tREQ_F_CUR_POS = 1024ULL,\n\tREQ_F_NOWAIT = 2048ULL,\n\tREQ_F_LINK_TIMEOUT = 4096ULL,\n\tREQ_F_NEED_CLEANUP = 8192ULL,\n\tREQ_F_POLLED = 16384ULL,\n\tREQ_F_IOPOLL_STATE = 32768ULL,\n\tREQ_F_BUFFER_SELECTED = 65536ULL,\n\tREQ_F_BUFFER_RING = 131072ULL,\n\tREQ_F_REISSUE = 262144ULL,\n\tREQ_F_SUPPORT_NOWAIT = 536870912ULL,\n\tREQ_F_ISREG = 1073741824ULL,\n\tREQ_F_CREDS = 524288ULL,\n\tREQ_F_REFCOUNT = 1048576ULL,\n\tREQ_F_ARM_LTIMEOUT = 2097152ULL,\n\tREQ_F_ASYNC_DATA = 4194304ULL,\n\tREQ_F_SKIP_LINK_CQES = 8388608ULL,\n\tREQ_F_SINGLE_POLL = 16777216ULL,\n\tREQ_F_DOUBLE_POLL = 33554432ULL,\n\tREQ_F_MULTISHOT = 67108864ULL,\n\tREQ_F_APOLL_MULTISHOT = 134217728ULL,\n\tREQ_F_CLEAR_POLLIN = 268435456ULL,\n\tREQ_F_POLL_NO_LAZY = 2147483648ULL,\n\tREQ_F_CAN_POLL = 4294967296ULL,\n\tREQ_F_BL_EMPTY = 8589934592ULL,\n\tREQ_F_BL_NO_RECYCLE = 17179869184ULL,\n\tREQ_F_BUFFERS_COMMIT = 34359738368ULL,\n\tREQ_F_BUF_NODE = 68719476736ULL,\n\tREQ_F_HAS_METADATA = 137438953472ULL,\n\tREQ_F_IMPORT_BUFFER = 274877906944ULL,\n\tREQ_F_SQE_COPIED = 549755813888ULL,\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_CQE_SKIP_BIT = 6,\n\tREQ_F_FAIL_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_NEED_CLEANUP_BIT = 13,\n\tREQ_F_POLLED_BIT = 14,\n\tREQ_F_HYBRID_IOPOLL_STATE_BIT = 15,\n\tREQ_F_BUFFER_SELECTED_BIT = 16,\n\tREQ_F_BUFFER_RING_BIT = 17,\n\tREQ_F_REISSUE_BIT = 18,\n\tREQ_F_CREDS_BIT = 19,\n\tREQ_F_REFCOUNT_BIT = 20,\n\tREQ_F_ARM_LTIMEOUT_BIT = 21,\n\tREQ_F_ASYNC_DATA_BIT = 22,\n\tREQ_F_SKIP_LINK_CQES_BIT = 23,\n\tREQ_F_SINGLE_POLL_BIT = 24,\n\tREQ_F_DOUBLE_POLL_BIT = 25,\n\tREQ_F_MULTISHOT_BIT = 26,\n\tREQ_F_APOLL_MULTISHOT_BIT = 27,\n\tREQ_F_CLEAR_POLLIN_BIT = 28,\n\tREQ_F_SUPPORT_NOWAIT_BIT = 29,\n\tREQ_F_ISREG_BIT = 30,\n\tREQ_F_POLL_NO_LAZY_BIT = 31,\n\tREQ_F_CAN_POLL_BIT = 32,\n\tREQ_F_BL_EMPTY_BIT = 33,\n\tREQ_F_BL_NO_RECYCLE_BIT = 34,\n\tREQ_F_BUFFERS_COMMIT_BIT = 35,\n\tREQ_F_BUF_NODE_BIT = 36,\n\tREQ_F_HAS_METADATA_BIT = 37,\n\tREQ_F_IMPORT_BUFFER_BIT = 38,\n\tREQ_F_SQE_COPIED_BIT = 39,\n\t__REQ_F_LAST_BIT = 40,\n};\n\nenum {\n\tRES_USAGE = 0,\n\tRES_RSVD_USAGE = 1,\n\tRES_LIMIT = 2,\n\tRES_RSVD_LIMIT = 3,\n\tRES_MAX_USAGE = 4,\n\tRES_RSVD_MAX_USAGE = 5,\n\tRES_FAILCNT = 6,\n\tRES_RSVD_FAILCNT = 7,\n};\n\nenum {\n\tRPCAUTH_lockd = 0,\n\tRPCAUTH_mount = 1,\n\tRPCAUTH_nfs = 2,\n\tRPCAUTH_portmap = 3,\n\tRPCAUTH_statd = 4,\n\tRPCAUTH_nfsd4_cb = 5,\n\tRPCAUTH_cache = 6,\n\tRPCAUTH_nfsd = 7,\n\tRPCAUTH_RootEOF = 8,\n};\n\nenum {\n\tRPCBPROC_NULL = 0,\n\tRPCBPROC_SET = 1,\n\tRPCBPROC_UNSET = 2,\n\tRPCBPROC_GETPORT = 3,\n\tRPCBPROC_GETADDR = 3,\n\tRPCBPROC_DUMP = 4,\n\tRPCBPROC_CALLIT = 5,\n\tRPCBPROC_BCAST = 5,\n\tRPCBPROC_GETTIME = 6,\n\tRPCBPROC_UADDR2TADDR = 7,\n\tRPCBPROC_TADDR2UADDR = 8,\n\tRPCBPROC_GETVERSADDR = 9,\n\tRPCBPROC_INDIRECT = 10,\n\tRPCBPROC_GETADDRLIST = 11,\n\tRPCBPROC_GETSTAT = 12,\n};\n\nenum {\n\tRPCSVC_MAXPAYLOAD = 4194304,\n\tRPCSVC_MAXPAYLOAD_TCP = 4194304,\n\tRPCSVC_MAXPAYLOAD_UDP = 32768,\n};\n\nenum {\n\tRPC_PIPEFS_MOUNT = 0,\n\tRPC_PIPEFS_UMOUNT = 1,\n};\n\nenum {\n\tRPC_TASK_RUNNING = 0,\n\tRPC_TASK_QUEUED = 1,\n\tRPC_TASK_ACTIVE = 2,\n\tRPC_TASK_NEED_XMIT = 3,\n\tRPC_TASK_NEED_RECV = 4,\n\tRPC_TASK_MSG_PIN_WAIT = 5,\n};\n\nenum {\n\tRQ_SECURE = 0,\n\tRQ_LOCAL = 1,\n\tRQ_USEDEFERRAL = 2,\n\tRQ_DROPME = 3,\n\tRQ_VICTIM = 4,\n\tRQ_DATA = 5,\n};\n\nenum {\n\tRTAS_WORK_AREA_ARENA_ALIGN = 65536,\n\tRTAS_WORK_AREA_ARENA_SZ = 262144,\n\tRTAS_WORK_AREA_MIN_ALLOC_SZ = 128,\n};\n\nenum {\n\tRTAS_WORK_AREA_MAX_ALLOC_SZ = 131072,\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_NEWMULTICAST = 56,\n\tRTM_DELMULTICAST = 57,\n\tRTM_GETMULTICAST = 58,\n\tRTM_NEWANYCAST = 60,\n\tRTM_DELANYCAST = 61,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_SETSTATS = 95,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\tRTM_NEWNEXTHOPBUCKET = 116,\n\tRTM_DELNEXTHOPBUCKET = 117,\n\tRTM_GETNEXTHOPBUCKET = 118,\n\tRTM_NEWTUNNEL = 120,\n\tRTM_DELTUNNEL = 121,\n\tRTM_GETTUNNEL = 122,\n\t__RTM_MAX = 123,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_Generic = 253,\n\tRoot_RAM0 = 1048576,\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n\tSCM_TSTAMP_COMPLETION = 3,\n};\n\nenum {\n\tSCSI_DH_OK = 0,\n\tSCSI_DH_DEV_FAILED = 1,\n\tSCSI_DH_DEV_TEMP_BUSY = 2,\n\tSCSI_DH_DEV_UNSUPP = 3,\n\tSCSI_DH_DEVICE_MAX = 4,\n\tSCSI_DH_NOTCONN = 5,\n\tSCSI_DH_CONN_FAILURE = 6,\n\tSCSI_DH_TRANSPORT_MAX = 7,\n\tSCSI_DH_IO = 8,\n\tSCSI_DH_INVALID_IO = 9,\n\tSCSI_DH_RETRY = 10,\n\tSCSI_DH_IMM_RETRY = 11,\n\tSCSI_DH_TIMED_OUT = 12,\n\tSCSI_DH_RES_TEMP_UNAVAIL = 13,\n\tSCSI_DH_DEV_OFFLINED = 14,\n\tSCSI_DH_NOMEM = 15,\n\tSCSI_DH_NOSYS = 16,\n\tSCSI_DH_DRIVER_MAX = 17,\n};\n\nenum {\n\tSCTP_AUTH_HMAC_ID_RESERVED_0 = 0,\n\tSCTP_AUTH_HMAC_ID_SHA1 = 1,\n\tSCTP_AUTH_HMAC_ID_RESERVED_2 = 2,\n\tSCTP_AUTH_HMAC_ID_SHA256 = 3,\n\t__SCTP_AUTH_HMAC_MAX = 4,\n};\n\nenum {\n\tSCTP_MAX_DUP_TSNS = 16,\n};\n\nenum {\n\tSCTP_MAX_STREAM = 65535,\n};\n\nenum {\n\tSD_BALANCE_NEWIDLE = 1,\n\tSD_BALANCE_EXEC = 2,\n\tSD_BALANCE_FORK = 4,\n\tSD_BALANCE_WAKE = 8,\n\tSD_WAKE_AFFINE = 16,\n\tSD_ASYM_CPUCAPACITY = 32,\n\tSD_ASYM_CPUCAPACITY_FULL = 64,\n\tSD_SHARE_CPUCAPACITY = 128,\n\tSD_CLUSTER = 256,\n\tSD_SHARE_LLC = 512,\n\tSD_SERIALIZE = 1024,\n\tSD_ASYM_PACKING = 2048,\n\tSD_PREFER_SIBLING = 4096,\n\tSD_NUMA = 8192,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nenum {\n\tSECTION_MARKED_PRESENT_BIT = 0,\n\tSECTION_HAS_MEM_MAP_BIT = 1,\n\tSECTION_IS_ONLINE_BIT = 2,\n\tSECTION_IS_EARLY_BIT = 3,\n\tSECTION_TAINT_ZONE_DEVICE_BIT = 4,\n\tSECTION_MAP_LAST_BIT = 5,\n};\n\nenum {\n\tSEG6_ATTR_UNSPEC = 0,\n\tSEG6_ATTR_DST = 1,\n\tSEG6_ATTR_DSTLEN = 2,\n\tSEG6_ATTR_HMACKEYID = 3,\n\tSEG6_ATTR_SECRET = 4,\n\tSEG6_ATTR_SECRETLEN = 5,\n\tSEG6_ATTR_ALGID = 6,\n\tSEG6_ATTR_HMACINFO = 7,\n\t__SEG6_ATTR_MAX = 8,\n};\n\nenum {\n\tSEG6_CMD_UNSPEC = 0,\n\tSEG6_CMD_SETHMAC = 1,\n\tSEG6_CMD_DUMPHMAC = 2,\n\tSEG6_CMD_SET_TUNSRC = 3,\n\tSEG6_CMD_GET_TUNSRC = 4,\n\t__SEG6_CMD_MAX = 5,\n};\n\nenum {\n\tSELNL_MSG_SETENFORCE = 16,\n\tSELNL_MSG_POLICYLOAD = 17,\n\tSELNL_MSG_MAX = 18,\n};\n\nenum {\n\tSFF8024_ID_UNK = 0,\n\tSFF8024_ID_SFF_8472 = 2,\n\tSFF8024_ID_SFP = 3,\n\tSFF8024_ID_DWDM_SFP = 11,\n\tSFF8024_ID_QSFP_8438 = 12,\n\tSFF8024_ID_QSFP_8436_8636 = 13,\n\tSFF8024_ID_QSFP28_8636 = 17,\n\tSFF8024_ID_QSFP_DD = 24,\n\tSFF8024_ID_OSFP = 25,\n\tSFF8024_ID_DSFP = 27,\n\tSFF8024_ID_QSFP_PLUS_CMIS = 30,\n\tSFF8024_ID_SFP_DD_CMIS = 31,\n\tSFF8024_ID_SFP_PLUS_CMIS = 32,\n\tSFF8024_ENCODING_UNSPEC = 0,\n\tSFF8024_ENCODING_8B10B = 1,\n\tSFF8024_ENCODING_4B5B = 2,\n\tSFF8024_ENCODING_NRZ = 3,\n\tSFF8024_ENCODING_8472_MANCHESTER = 4,\n\tSFF8024_ENCODING_8472_SONET = 5,\n\tSFF8024_ENCODING_8472_64B66B = 6,\n\tSFF8024_ENCODING_8436_MANCHESTER = 6,\n\tSFF8024_ENCODING_8436_SONET = 4,\n\tSFF8024_ENCODING_8436_64B66B = 5,\n\tSFF8024_ENCODING_256B257B = 7,\n\tSFF8024_ENCODING_PAM4 = 8,\n\tSFF8024_CONNECTOR_UNSPEC = 0,\n\tSFF8024_CONNECTOR_SC = 1,\n\tSFF8024_CONNECTOR_FIBERJACK = 6,\n\tSFF8024_CONNECTOR_LC = 7,\n\tSFF8024_CONNECTOR_MT_RJ = 8,\n\tSFF8024_CONNECTOR_MU = 9,\n\tSFF8024_CONNECTOR_SG = 10,\n\tSFF8024_CONNECTOR_OPTICAL_PIGTAIL = 11,\n\tSFF8024_CONNECTOR_MPO_1X12 = 12,\n\tSFF8024_CONNECTOR_MPO_2X16 = 13,\n\tSFF8024_CONNECTOR_HSSDC_II = 32,\n\tSFF8024_CONNECTOR_COPPER_PIGTAIL = 33,\n\tSFF8024_CONNECTOR_RJ45 = 34,\n\tSFF8024_CONNECTOR_NOSEPARATE = 35,\n\tSFF8024_CONNECTOR_MXC_2X16 = 36,\n\tSFF8024_ECC_UNSPEC = 0,\n\tSFF8024_ECC_100G_25GAUI_C2M_AOC = 1,\n\tSFF8024_ECC_100GBASE_SR4_25GBASE_SR = 2,\n\tSFF8024_ECC_100GBASE_LR4_25GBASE_LR = 3,\n\tSFF8024_ECC_100GBASE_ER4_25GBASE_ER = 4,\n\tSFF8024_ECC_100GBASE_SR10 = 5,\n\tSFF8024_ECC_100GBASE_CR4 = 11,\n\tSFF8024_ECC_25GBASE_CR_S = 12,\n\tSFF8024_ECC_25GBASE_CR_N = 13,\n\tSFF8024_ECC_10GBASE_T_SFI = 22,\n\tSFF8024_ECC_10GBASE_T_SR = 28,\n\tSFF8024_ECC_5GBASE_T = 29,\n\tSFF8024_ECC_2_5GBASE_T = 30,\n};\n\nenum {\n\tSFP_PHYS_ID = 0,\n\tSFP_PHYS_EXT_ID = 1,\n\tSFP_PHYS_EXT_ID_SFP = 4,\n\tSFP_CONNECTOR = 2,\n\tSFP_COMPLIANCE = 3,\n\tSFP_ENCODING = 11,\n\tSFP_BR_NOMINAL = 12,\n\tSFP_RATE_ID = 13,\n\tSFF_RID_8079 = 1,\n\tSFF_RID_8431_RX_ONLY = 2,\n\tSFF_RID_8431_TX_ONLY = 4,\n\tSFF_RID_8431 = 6,\n\tSFF_RID_10G8G = 14,\n\tSFP_LINK_LEN_SM_KM = 14,\n\tSFP_LINK_LEN_SM_100M = 15,\n\tSFP_LINK_LEN_50UM_OM2_10M = 16,\n\tSFP_LINK_LEN_62_5UM_OM1_10M = 17,\n\tSFP_LINK_LEN_COPPER_1M = 18,\n\tSFP_LINK_LEN_50UM_OM4_10M = 18,\n\tSFP_LINK_LEN_50UM_OM3_10M = 19,\n\tSFP_VENDOR_NAME = 20,\n\tSFP_VENDOR_OUI = 37,\n\tSFP_VENDOR_PN = 40,\n\tSFP_VENDOR_REV = 56,\n\tSFP_OPTICAL_WAVELENGTH_MSB = 60,\n\tSFP_OPTICAL_WAVELENGTH_LSB = 61,\n\tSFP_CABLE_SPEC = 60,\n\tSFP_CC_BASE = 63,\n\tSFP_OPTIONS = 64,\n\tSFP_OPTIONS_HIGH_POWER_LEVEL = 8192,\n\tSFP_OPTIONS_PAGING_A2 = 4096,\n\tSFP_OPTIONS_RETIMER = 2048,\n\tSFP_OPTIONS_COOLED_XCVR = 1024,\n\tSFP_OPTIONS_POWER_DECL = 512,\n\tSFP_OPTIONS_RX_LINEAR_OUT = 256,\n\tSFP_OPTIONS_RX_DECISION_THRESH = 128,\n\tSFP_OPTIONS_TUNABLE_TX = 64,\n\tSFP_OPTIONS_RATE_SELECT = 32,\n\tSFP_OPTIONS_TX_DISABLE = 16,\n\tSFP_OPTIONS_TX_FAULT = 8,\n\tSFP_OPTIONS_LOS_INVERTED = 4,\n\tSFP_OPTIONS_LOS_NORMAL = 2,\n\tSFP_BR_MAX = 66,\n\tSFP_BR_MIN = 67,\n\tSFP_VENDOR_SN = 68,\n\tSFP_DATECODE = 84,\n\tSFP_DIAGMON = 92,\n\tSFP_DIAGMON_DDM = 64,\n\tSFP_DIAGMON_INT_CAL = 32,\n\tSFP_DIAGMON_EXT_CAL = 16,\n\tSFP_DIAGMON_RXPWR_AVG = 8,\n\tSFP_DIAGMON_ADDRMODE = 4,\n\tSFP_ENHOPTS = 93,\n\tSFP_ENHOPTS_ALARMWARN = 128,\n\tSFP_ENHOPTS_SOFT_TX_DISABLE = 64,\n\tSFP_ENHOPTS_SOFT_TX_FAULT = 32,\n\tSFP_ENHOPTS_SOFT_RX_LOS = 16,\n\tSFP_ENHOPTS_SOFT_RATE_SELECT = 8,\n\tSFP_ENHOPTS_APP_SELECT_SFF8079 = 4,\n\tSFP_ENHOPTS_SOFT_RATE_SFF8431 = 2,\n\tSFP_SFF8472_COMPLIANCE = 94,\n\tSFP_SFF8472_COMPLIANCE_NONE = 0,\n\tSFP_SFF8472_COMPLIANCE_REV9_3 = 1,\n\tSFP_SFF8472_COMPLIANCE_REV9_5 = 2,\n\tSFP_SFF8472_COMPLIANCE_REV10_2 = 3,\n\tSFP_SFF8472_COMPLIANCE_REV10_4 = 4,\n\tSFP_SFF8472_COMPLIANCE_REV11_0 = 5,\n\tSFP_SFF8472_COMPLIANCE_REV11_3 = 6,\n\tSFP_SFF8472_COMPLIANCE_REV11_4 = 7,\n\tSFP_SFF8472_COMPLIANCE_REV12_0 = 8,\n\tSFP_CC_EXT = 95,\n};\n\nenum {\n\tSIL24_HOST_BAR = 0,\n\tSIL24_PORT_BAR = 2,\n\tSIL24_PRB_SZ = 64,\n\tSIL24_MAX_SGT = 1023,\n\tSIL24_MAX_SGE = 4093,\n\tHOST_SLOT_STAT = 0,\n\tHOST_CTRL = 64,\n\tHOST_IRQ_STAT___2 = 68,\n\tHOST_PHY_CFG = 72,\n\tHOST_BIST_CTRL = 80,\n\tHOST_BIST_PTRN = 84,\n\tHOST_BIST_STAT = 88,\n\tHOST_MEM_BIST_STAT = 92,\n\tHOST_FLASH_CMD = 112,\n\tHOST_FLASH_DATA = 116,\n\tHOST_TRANSITION_DETECT = 117,\n\tHOST_GPIO_CTRL = 118,\n\tHOST_I2C_ADDR = 120,\n\tHOST_I2C_DATA = 124,\n\tHOST_I2C_XFER_CNT = 126,\n\tHOST_I2C_CTRL = 127,\n\tHOST_SSTAT_ATTN = -2147483648,\n\tHOST_CTRL_M66EN = 65536,\n\tHOST_CTRL_TRDY = 131072,\n\tHOST_CTRL_STOP = 262144,\n\tHOST_CTRL_DEVSEL = 524288,\n\tHOST_CTRL_REQ64 = 1048576,\n\tHOST_CTRL_GLOBAL_RST = -2147483648,\n\tPORT_REGS_SIZE = 8192,\n\tPORT_LRAM = 0,\n\tPORT_LRAM_SLOT_SZ = 128,\n\tPORT_PMP = 3968,\n\tPORT_PMP_STATUS = 0,\n\tPORT_PMP_QACTIVE = 4,\n\tPORT_PMP_SIZE = 8,\n\tPORT_CTRL_STAT = 4096,\n\tPORT_CTRL_CLR = 4100,\n\tPORT_IRQ_STAT___2 = 4104,\n\tPORT_IRQ_ENABLE_SET = 4112,\n\tPORT_IRQ_ENABLE_CLR = 4116,\n\tPORT_ACTIVATE_UPPER_ADDR = 4124,\n\tPORT_EXEC_FIFO = 4128,\n\tPORT_CMD_ERR = 4132,\n\tPORT_FIS_CFG = 4136,\n\tPORT_FIFO_THRES = 4140,\n\tPORT_DECODE_ERR_CNT = 4160,\n\tPORT_DECODE_ERR_THRESH = 4162,\n\tPORT_CRC_ERR_CNT = 4164,\n\tPORT_CRC_ERR_THRESH = 4166,\n\tPORT_HSHK_ERR_CNT = 4168,\n\tPORT_HSHK_ERR_THRESH = 4170,\n\tPORT_PHY_CFG = 4176,\n\tPORT_SLOT_STAT = 6144,\n\tPORT_CMD_ACTIVATE = 7168,\n\tPORT_CONTEXT = 7684,\n\tPORT_EXEC_DIAG = 7680,\n\tPORT_PSD_DIAG = 7744,\n\tPORT_SCONTROL = 7936,\n\tPORT_SSTATUS = 7940,\n\tPORT_SERROR = 7944,\n\tPORT_SACTIVE = 7948,\n\tPORT_CS_PORT_RST = 1,\n\tPORT_CS_DEV_RST = 2,\n\tPORT_CS_INIT = 4,\n\tPORT_CS_IRQ_WOC = 8,\n\tPORT_CS_CDB16 = 32,\n\tPORT_CS_PMP_RESUME = 64,\n\tPORT_CS_32BIT_ACTV = 1024,\n\tPORT_CS_PMP_EN = 8192,\n\tPORT_CS_RDY = -2147483648,\n\tPORT_IRQ_COMPLETE = 1,\n\tPORT_IRQ_ERROR___2 = 2,\n\tPORT_IRQ_PORTRDY_CHG = 4,\n\tPORT_IRQ_PWR_CHG = 8,\n\tPORT_IRQ_PHYRDY_CHG = 16,\n\tPORT_IRQ_COMWAKE = 32,\n\tPORT_IRQ_UNK_FIS___2 = 64,\n\tPORT_IRQ_DEV_XCHG = 128,\n\tPORT_IRQ_8B10B = 256,\n\tPORT_IRQ_CRC = 512,\n\tPORT_IRQ_HANDSHAKE = 1024,\n\tPORT_IRQ_SDB_NOTIFY = 2048,\n\tDEF_PORT_IRQ___2 = 2259,\n\tPORT_IRQ_RAW_SHIFT = 16,\n\tPORT_IRQ_MASKED_MASK = 2047,\n\tPORT_IRQ_RAW_MASK = 134152192,\n\tPORT_IRQ_STEER_SHIFT = 30,\n\tPORT_IRQ_STEER_MASK = -1073741824,\n\tPORT_CERR_DEV = 1,\n\tPORT_CERR_SDB = 2,\n\tPORT_CERR_DATA = 3,\n\tPORT_CERR_SEND = 4,\n\tPORT_CERR_INCONSISTENT = 5,\n\tPORT_CERR_DIRECTION = 6,\n\tPORT_CERR_UNDERRUN = 7,\n\tPORT_CERR_OVERRUN = 8,\n\tPORT_CERR_PKT_PROT = 11,\n\tPORT_CERR_SGT_BOUNDARY = 16,\n\tPORT_CERR_SGT_TGTABRT = 17,\n\tPORT_CERR_SGT_MSTABRT = 18,\n\tPORT_CERR_SGT_PCIPERR = 19,\n\tPORT_CERR_CMD_BOUNDARY = 24,\n\tPORT_CERR_CMD_TGTABRT = 25,\n\tPORT_CERR_CMD_MSTABRT = 26,\n\tPORT_CERR_CMD_PCIPERR = 27,\n\tPORT_CERR_XFR_UNDEF = 32,\n\tPORT_CERR_XFR_TGTABRT = 33,\n\tPORT_CERR_XFR_MSTABRT = 34,\n\tPORT_CERR_XFR_PCIPERR = 35,\n\tPORT_CERR_SENDSERVICE = 36,\n\tPRB_CTRL_PROTOCOL = 1,\n\tPRB_CTRL_PACKET_READ = 16,\n\tPRB_CTRL_PACKET_WRITE = 32,\n\tPRB_CTRL_NIEN = 64,\n\tPRB_CTRL_SRST = 128,\n\tPRB_PROT_PACKET = 1,\n\tPRB_PROT_TCQ = 2,\n\tPRB_PROT_NCQ = 4,\n\tPRB_PROT_READ = 8,\n\tPRB_PROT_WRITE = 16,\n\tPRB_PROT_TRANSPARENT = 32,\n\tSGE_TRM = -2147483648,\n\tSGE_LNK = 1073741824,\n\tSGE_DRD = 536870912,\n\tSIL24_MAX_CMDS = 31,\n\tBID_SIL3124 = 0,\n\tBID_SIL3132 = 1,\n\tBID_SIL3131 = 2,\n\tSIL24_COMMON_FLAGS = 918658,\n\tSIL24_FLAG_PCIX_IRQ_WOC = 16777216,\n\tIRQ_STAT_4PORTS = 15,\n};\n\nenum {\n\tSKBFL_ZEROCOPY_ENABLE = 1,\n\tSKBFL_SHARED_FRAG = 2,\n\tSKBFL_PURE_ZEROCOPY = 4,\n\tSKBFL_DONT_ORPHAN = 8,\n\tSKBFL_MANAGED_FRAG_REFS = 16,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP_NOBPF = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_COMPLETION_TSTAMP = 8,\n\tSKBTX_HW_TSTAMP_NETDEV = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n\tSKBTX_BPF = 128,\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\t__SKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n\tSKB_GSO_TCP_ACCECN = 524288,\n\tSKB_GSO_TCP_FIXEDID = 1073741824,\n\tSKB_GSO_TCP_FIXEDID_INNER = -2147483648,\n};\n\nenum {\n\tSKCIPHER_WALK_SLOW = 1,\n\tSKCIPHER_WALK_COPY = 2,\n\tSKCIPHER_WALK_DIFF = 4,\n\tSKCIPHER_WALK_SLEEP = 8,\n};\n\nenum {\n\tSK_BPF_CB_TX_TIMESTAMPING = 1,\n\tSK_BPF_CB_MASK = 1,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_BIND_PHC = 32768,\n\tSOF_TIMESTAMPING_OPT_ID_TCP = 65536,\n\tSOF_TIMESTAMPING_OPT_RX_FILTER = 131072,\n\tSOF_TIMESTAMPING_TX_COMPLETION = 262144,\n\tSOF_TIMESTAMPING_LAST = 262144,\n\tSOF_TIMESTAMPING_MASK = 524287,\n};\n\nenum {\n\tSP_TASK_PENDING = 0,\n\tSP_NEED_VICTIM = 1,\n\tSP_VICTIM_REMAINS = 2,\n\tSP_TASK_STARTING = 3,\n};\n\nenum {\n\tSRP_BUF_FORMAT_DIRECT = 2,\n\tSRP_BUF_FORMAT_INDIRECT = 4,\n};\n\nenum {\n\tSRP_LOGIN_REQ = 0,\n\tSRP_TSK_MGMT = 1,\n\tSRP_CMD = 2,\n\tSRP_I_LOGOUT = 3,\n\tSRP_LOGIN_RSP = 192,\n\tSRP_RSP = 193,\n\tSRP_LOGIN_REJ = 194,\n\tSRP_T_LOGOUT = 128,\n\tSRP_CRED_REQ = 129,\n\tSRP_AER_REQ = 130,\n\tSRP_CRED_RSP = 65,\n\tSRP_AER_RSP = 66,\n};\n\nenum {\n\tSRP_NO_DATA_DESC = 0,\n\tSRP_DATA_DESC_DIRECT = 1,\n\tSRP_DATA_DESC_INDIRECT = 2,\n\tSRP_DATA_DESC_IMM = 3,\n};\n\nenum {\n\tSRP_RSP_FLAG_RSPVALID = 1,\n\tSRP_RSP_FLAG_SNSVALID = 2,\n\tSRP_RSP_FLAG_DOOVER = 4,\n\tSRP_RSP_FLAG_DOUNDER = 8,\n\tSRP_RSP_FLAG_DIOVER = 16,\n\tSRP_RSP_FLAG_DIUNDER = 32,\n};\n\nenum {\n\tSRP_TSK_ABORT_TASK = 1,\n\tSRP_TSK_ABORT_TASK_SET = 2,\n\tSRP_TSK_CLEAR_TASK_SET = 4,\n\tSRP_TSK_LUN_RESET = 8,\n\tSRP_TSK_CLEAR_ACA = 64,\n};\n\nenum {\n\tSUNRPC_MAX_UDP_SENDPAGES = 3,\n};\n\nenum {\n\tSUNRPC_PIPEFS_NFS_PRIO = 0,\n\tSUNRPC_PIPEFS_RPC_PRIO = 1,\n};\n\nenum {\n\tSVC_HANDSHAKE_TO = 5000,\n};\n\nenum {\n\tSVC_POOL_AUTO = -1,\n\tSVC_POOL_GLOBAL = 0,\n\tSVC_POOL_PERCPU = 1,\n\tSVC_POOL_PERNODE = 2,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nenum {\n\tSWMII_SPEED_10 = 0,\n\tSWMII_SPEED_100 = 1,\n\tSWMII_SPEED_1000 = 2,\n\tSWMII_DUPLEX_HALF = 0,\n\tSWMII_DUPLEX_FULL = 1,\n};\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS_OPS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = -1,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nenum {\n\tTASKSTATS_CMD_ATTR_UNSPEC = 0,\n\tTASKSTATS_CMD_ATTR_PID = 1,\n\tTASKSTATS_CMD_ATTR_TGID = 2,\n\tTASKSTATS_CMD_ATTR_REGISTER_CPUMASK = 3,\n\tTASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK = 4,\n\t__TASKSTATS_CMD_ATTR_MAX = 5,\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum {\n\tTASKSTATS_TYPE_UNSPEC = 0,\n\tTASKSTATS_TYPE_PID = 1,\n\tTASKSTATS_TYPE_TGID = 2,\n\tTASKSTATS_TYPE_STATS = 3,\n\tTASKSTATS_TYPE_AGGR_PID = 4,\n\tTASKSTATS_TYPE_AGGR_TGID = 5,\n\tTASKSTATS_TYPE_NULL = 6,\n\t__TASKSTATS_TYPE_MAX = 7,\n};\n\nenum {\n\tTASK_COMM_LEN = 16,\n};\n\nenum {\n\tTCA_ACT_UNSPEC = 0,\n\tTCA_ACT_KIND = 1,\n\tTCA_ACT_OPTIONS = 2,\n\tTCA_ACT_INDEX = 3,\n\tTCA_ACT_STATS = 4,\n\tTCA_ACT_PAD = 5,\n\tTCA_ACT_COOKIE = 6,\n\tTCA_ACT_FLAGS = 7,\n\tTCA_ACT_HW_STATS = 8,\n\tTCA_ACT_USED_HW_STATS = 9,\n\tTCA_ACT_IN_HW_COUNT = 10,\n\t__TCA_ACT_MAX = 11,\n};\n\nenum {\n\tTCA_FLOWER_KEY_CT_FLAGS_NEW = 1,\n\tTCA_FLOWER_KEY_CT_FLAGS_ESTABLISHED = 2,\n\tTCA_FLOWER_KEY_CT_FLAGS_RELATED = 4,\n\tTCA_FLOWER_KEY_CT_FLAGS_TRACKED = 8,\n\tTCA_FLOWER_KEY_CT_FLAGS_INVALID = 16,\n\tTCA_FLOWER_KEY_CT_FLAGS_REPLY = 32,\n\t__TCA_FLOWER_KEY_CT_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1,\n\tTCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CSUM = 4,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_DONT_FRAGMENT = 8,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_OAM = 16,\n\tTCA_FLOWER_KEY_FLAGS_TUNNEL_CRIT_OPT = 32,\n\t__TCA_FLOWER_KEY_FLAGS_MAX = 33,\n};\n\nenum {\n\tTCA_ROOT_UNSPEC = 0,\n\tTCA_ROOT_TAB = 1,\n\tTCA_ROOT_FLAGS = 2,\n\tTCA_ROOT_COUNT = 3,\n\tTCA_ROOT_TIME_DELTA = 4,\n\tTCA_ROOT_EXT_WARN_MSG = 5,\n\t__TCA_ROOT_MAX = 6,\n};\n\nenum {\n\tTCA_STAB_UNSPEC = 0,\n\tTCA_STAB_BASE = 1,\n\tTCA_STAB_DATA = 2,\n\t__TCA_STAB_MAX = 3,\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\tTCA_EXT_WARN_MSG = 16,\n\t__TCA_MAX = 17,\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n\tTCPF_BOUND_INACTIVE = 8192,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_RX = 2,\n\tTCP_BPF_TXRX = 3,\n\tTCP_BPF_NUM_CFGS = 4,\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n\tTCP_BPF_DELACK_MAX = 1003,\n\tTCP_BPF_RTO_MIN = 1004,\n\tTCP_BPF_SYN = 1005,\n\tTCP_BPF_SYN_IP = 1006,\n\tTCP_BPF_SYN_MAC = 1007,\n\tTCP_BPF_SOCK_OPS_CB_FLAGS = 1008,\n\tSK_BPF_CB_FLAGS = 1009,\n\tSK_BPF_BYPASS_PROT_MEM = 1010,\n};\n\nenum {\n\tTCP_CMSG_INQ = 1,\n\tTCP_CMSG_TS = 2,\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_BOUND_INACTIVE = 13,\n\tTCP_MAX_STATES = 14,\n};\n\nenum {\n\tTCP_FLAG_AE = 1,\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 14,\n\tTCP_DATA_OFFSET = 240,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n\tTCP_NLA_EDT = 25,\n\tTCP_NLA_TTL = 26,\n\tTCP_NLA_REHASH = 27,\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nenum {\n\tTCP_V4_FLOW = 1,\n\tUDP_V4_FLOW = 2,\n\tSCTP_V4_FLOW = 3,\n\tAH_ESP_V4_FLOW = 4,\n\tTCP_V6_FLOW = 5,\n\tUDP_V6_FLOW = 6,\n\tSCTP_V6_FLOW = 7,\n\tAH_ESP_V6_FLOW = 8,\n\tAH_V4_FLOW = 9,\n\tESP_V4_FLOW = 10,\n\tAH_V6_FLOW = 11,\n\tESP_V6_FLOW = 12,\n\tIPV4_USER_FLOW = 13,\n\tIP_USER_FLOW = 13,\n\tIPV6_USER_FLOW = 14,\n\tIPV4_FLOW = 16,\n\tIPV6_FLOW = 17,\n\tETHER_FLOW = 18,\n\tGTPU_V4_FLOW = 19,\n\tGTPU_V6_FLOW = 20,\n\tGTPC_V4_FLOW = 21,\n\tGTPC_V6_FLOW = 22,\n\tGTPC_TEID_V4_FLOW = 23,\n\tGTPC_TEID_V6_FLOW = 24,\n\tGTPU_EH_V4_FLOW = 25,\n\tGTPU_EH_V6_FLOW = 26,\n\tGTPU_UL_V4_FLOW = 27,\n\tGTPU_UL_V6_FLOW = 28,\n\tGTPU_DL_V4_FLOW = 29,\n\tGTPU_DL_V6_FLOW = 30,\n\t__FLOW_TYPE_COUNT = 31,\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nenum {\n\tTLB_INVAL_SCOPE_GLOBAL = 0,\n\tTLB_INVAL_SCOPE_LPID = 1,\n};\n\nenum {\n\tTLS_ALERT_DESC_CLOSE_NOTIFY = 0,\n\tTLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10,\n\tTLS_ALERT_DESC_BAD_RECORD_MAC = 20,\n\tTLS_ALERT_DESC_RECORD_OVERFLOW = 22,\n\tTLS_ALERT_DESC_HANDSHAKE_FAILURE = 40,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE = 42,\n\tTLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43,\n\tTLS_ALERT_DESC_CERTIFICATE_REVOKED = 44,\n\tTLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45,\n\tTLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46,\n\tTLS_ALERT_DESC_ILLEGAL_PARAMETER = 47,\n\tTLS_ALERT_DESC_UNKNOWN_CA = 48,\n\tTLS_ALERT_DESC_ACCESS_DENIED = 49,\n\tTLS_ALERT_DESC_DECODE_ERROR = 50,\n\tTLS_ALERT_DESC_DECRYPT_ERROR = 51,\n\tTLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52,\n\tTLS_ALERT_DESC_PROTOCOL_VERSION = 70,\n\tTLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71,\n\tTLS_ALERT_DESC_INTERNAL_ERROR = 80,\n\tTLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86,\n\tTLS_ALERT_DESC_USER_CANCELED = 90,\n\tTLS_ALERT_DESC_MISSING_EXTENSION = 109,\n\tTLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110,\n\tTLS_ALERT_DESC_UNRECOGNIZED_NAME = 112,\n\tTLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113,\n\tTLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115,\n\tTLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116,\n\tTLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120,\n};\n\nenum {\n\tTLS_ALERT_LEVEL_WARNING = 1,\n\tTLS_ALERT_LEVEL_FATAL = 2,\n};\n\nenum {\n\tTLS_NO_KEYRING = 0,\n\tTLS_NO_PEERID = 0,\n\tTLS_NO_CERT = 0,\n\tTLS_NO_PRIVKEY = 0,\n};\n\nenum {\n\tTLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20,\n\tTLS_RECORD_TYPE_ALERT = 21,\n\tTLS_RECORD_TYPE_HANDSHAKE = 22,\n\tTLS_RECORD_TYPE_DATA = 23,\n\tTLS_RECORD_TYPE_HEARTBEAT = 24,\n\tTLS_RECORD_TYPE_TLS12_CID = 25,\n\tTLS_RECORD_TYPE_ACK = 26,\n};\n\nenum {\n\tTOO_MANY_CLOSE = -1,\n\tTOO_MANY_OPEN = -2,\n\tMISSING_QUOTE = -3,\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_BAD_MAXACT_TYPE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_NON_UNIQ_SYMBOL = 10,\n\tTP_ERR_BAD_RETPROBE = 11,\n\tTP_ERR_NO_TRACEPOINT = 12,\n\tTP_ERR_BAD_TP_NAME = 13,\n\tTP_ERR_BAD_ADDR_SUFFIX = 14,\n\tTP_ERR_NO_GROUP_NAME = 15,\n\tTP_ERR_GROUP_TOO_LONG = 16,\n\tTP_ERR_BAD_GROUP_NAME = 17,\n\tTP_ERR_NO_EVENT_NAME = 18,\n\tTP_ERR_EVENT_TOO_LONG = 19,\n\tTP_ERR_BAD_EVENT_NAME = 20,\n\tTP_ERR_EVENT_EXIST = 21,\n\tTP_ERR_RETVAL_ON_PROBE = 22,\n\tTP_ERR_NO_RETVAL = 23,\n\tTP_ERR_BAD_STACK_NUM = 24,\n\tTP_ERR_BAD_ARG_NUM = 25,\n\tTP_ERR_BAD_VAR = 26,\n\tTP_ERR_BAD_REG_NAME = 27,\n\tTP_ERR_BAD_MEM_ADDR = 28,\n\tTP_ERR_BAD_IMM = 29,\n\tTP_ERR_IMMSTR_NO_CLOSE = 30,\n\tTP_ERR_FILE_ON_KPROBE = 31,\n\tTP_ERR_BAD_FILE_OFFS = 32,\n\tTP_ERR_SYM_ON_UPROBE = 33,\n\tTP_ERR_TOO_MANY_OPS = 34,\n\tTP_ERR_DEREF_NEED_BRACE = 35,\n\tTP_ERR_BAD_DEREF_OFFS = 36,\n\tTP_ERR_DEREF_OPEN_BRACE = 37,\n\tTP_ERR_COMM_CANT_DEREF = 38,\n\tTP_ERR_BAD_FETCH_ARG = 39,\n\tTP_ERR_ARRAY_NO_CLOSE = 40,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 41,\n\tTP_ERR_BAD_ARRAY_NUM = 42,\n\tTP_ERR_ARRAY_TOO_BIG = 43,\n\tTP_ERR_BAD_TYPE = 44,\n\tTP_ERR_BAD_STRING = 45,\n\tTP_ERR_BAD_SYMSTRING = 46,\n\tTP_ERR_BAD_BITFIELD = 47,\n\tTP_ERR_ARG_NAME_TOO_LONG = 48,\n\tTP_ERR_NO_ARG_NAME = 49,\n\tTP_ERR_BAD_ARG_NAME = 50,\n\tTP_ERR_USED_ARG_NAME = 51,\n\tTP_ERR_ARG_TOO_LONG = 52,\n\tTP_ERR_NO_ARG_BODY = 53,\n\tTP_ERR_BAD_INSN_BNDRY = 54,\n\tTP_ERR_FAIL_REG_PROBE = 55,\n\tTP_ERR_DIFF_PROBE_TYPE = 56,\n\tTP_ERR_DIFF_ARG_TYPE = 57,\n\tTP_ERR_SAME_PROBE = 58,\n\tTP_ERR_NO_EVENT_INFO = 59,\n\tTP_ERR_BAD_ATTACH_EVENT = 60,\n\tTP_ERR_BAD_ATTACH_ARG = 61,\n\tTP_ERR_NO_EP_FILTER = 62,\n\tTP_ERR_NOSUP_BTFARG = 63,\n\tTP_ERR_NO_BTFARG = 64,\n\tTP_ERR_NO_BTF_ENTRY = 65,\n\tTP_ERR_BAD_VAR_ARGS = 66,\n\tTP_ERR_NOFENTRY_ARGS = 67,\n\tTP_ERR_DOUBLE_ARGS = 68,\n\tTP_ERR_ARGS_2LONG = 69,\n\tTP_ERR_ARGIDX_2BIG = 70,\n\tTP_ERR_NO_PTR_STRCT = 71,\n\tTP_ERR_NOSUP_DAT_ARG = 72,\n\tTP_ERR_BAD_HYPHEN = 73,\n\tTP_ERR_NO_BTF_FIELD = 74,\n\tTP_ERR_BAD_BTF_TID = 75,\n\tTP_ERR_BAD_TYPE4STR = 76,\n\tTP_ERR_NEED_STRING_TYPE = 77,\n\tTP_ERR_TOO_MANY_ARGS = 78,\n\tTP_ERR_TOO_MANY_EARGS = 79,\n};\n\nenum {\n\tTRACEFS_EVENT_INODE = 2,\n\tTRACEFS_GID_PERM_SET = 4,\n\tTRACEFS_UID_PERM_SET = 8,\n\tTRACEFS_INSTANCE_INODE = 16,\n};\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n\tTRACE_ARRAY_FL_BOOT = 2,\n\tTRACE_ARRAY_FL_LAST_BOOT = 4,\n\tTRACE_ARRAY_FL_MOD_INIT = 8,\n\tTRACE_ARRAY_FL_MEMMAP = 16,\n\tTRACE_ARRAY_FL_VMALLOC = 32,\n};\n\nenum {\n\tTRACE_CTX_NMI = 0,\n\tTRACE_CTX_IRQ = 1,\n\tTRACE_CTX_SOFTIRQ = 2,\n\tTRACE_CTX_NORMAL = 3,\n\tTRACE_CTX_TRANSITION = 4,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 4,\n\tTRACE_EVENT_FL_TRACEPOINT = 8,\n\tTRACE_EVENT_FL_DYNAMIC = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n\tTRACE_EVENT_FL_EPROBE = 128,\n\tTRACE_EVENT_FL_FPROBE = 256,\n\tTRACE_EVENT_FL_CUSTOM = 512,\n\tTRACE_EVENT_FL_TEST_STR = 1024,\n};\n\nenum {\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 0,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 1,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 2,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 3,\n\tTRACE_EVENT_FL_DYNAMIC_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n\tTRACE_EVENT_FL_EPROBE_BIT = 7,\n\tTRACE_EVENT_FL_FPROBE_BIT = 8,\n\tTRACE_EVENT_FL_CUSTOM_BIT = 9,\n\tTRACE_EVENT_FL_TEST_STR_BIT = 10,\n};\n\nenum {\n\tTRACE_FTRACE_BIT = 0,\n\tTRACE_FTRACE_NMI_BIT = 1,\n\tTRACE_FTRACE_IRQ_BIT = 2,\n\tTRACE_FTRACE_SIRQ_BIT = 3,\n\tTRACE_FTRACE_TRANSITION_BIT = 4,\n\tTRACE_INTERNAL_BIT = 5,\n\tTRACE_INTERNAL_NMI_BIT = 6,\n\tTRACE_INTERNAL_IRQ_BIT = 7,\n\tTRACE_INTERNAL_SIRQ_BIT = 8,\n\tTRACE_INTERNAL_TRANSITION_BIT = 9,\n\tTRACE_INTERNAL_EVENT_BIT = 10,\n\tTRACE_INTERNAL_EVENT_NMI_BIT = 11,\n\tTRACE_INTERNAL_EVENT_IRQ_BIT = 12,\n\tTRACE_INTERNAL_EVENT_SIRQ_BIT = 13,\n\tTRACE_INTERNAL_EVENT_TRANSITION_BIT = 14,\n\tTRACE_BRANCH_BIT = 15,\n\tTRACE_IRQ_BIT = 16,\n\tTRACE_RECORD_RECURSION_BIT = 17,\n};\n\nenum {\n\tTRACE_FUNC_NO_OPTS = 0,\n\tTRACE_FUNC_OPT_STACK = 1,\n\tTRACE_FUNC_OPT_NO_REPEATS = 2,\n\tTRACE_FUNC_OPT_ARGS = 4,\n\tTRACE_FUNC_OPT_HIGHEST_BIT = 8,\n};\n\nenum {\n\tTRACE_GRAPH_FL = 1,\n\tTRACE_GRAPH_DEPTH_START_BIT = 2,\n\tTRACE_GRAPH_DEPTH_END_BIT = 3,\n\tTRACE_GRAPH_NOTRACE_BIT = 4,\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nenum {\n\tT_SHARED = 1,\n\tT_UNBINDABLE = 2,\n\tT_MARKED = 4,\n\tT_UMOUNT_CANDIDATE = 8,\n\tT_SHARED_MASK = 2,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tUDP_FLAGS_CORK = 0,\n\tUDP_FLAGS_NO_CHECK6_TX = 1,\n\tUDP_FLAGS_NO_CHECK6_RX = 2,\n\tUDP_FLAGS_GRO_ENABLED = 3,\n\tUDP_FLAGS_ACCEPT_FRAGLIST = 4,\n\tUDP_FLAGS_ACCEPT_L4 = 5,\n\tUDP_FLAGS_ENCAP_ENABLED = 6,\n\tUDP_FLAGS_UDPLITE_SEND_CC = 7,\n\tUDP_FLAGS_UDPLITE_RECV_CC = 8,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\tUDP_MIB_MEMERRORS = 9,\n\t__UDP_MIB_MAX = 10,\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum {\n\tUNIX_GRAPH_NOT_CYCLIC = 0,\n\tUNIX_GRAPH_MAYBE_CYCLIC = 1,\n\tUNIX_GRAPH_CYCLIC = 2,\n};\n\nenum {\n\tVMA_READ_BIT = 0,\n\tVMA_WRITE_BIT = 1,\n\tVMA_EXEC_BIT = 2,\n\tVMA_SHARED_BIT = 3,\n\tVMA_MAYREAD_BIT = 4,\n\tVMA_MAYWRITE_BIT = 5,\n\tVMA_MAYEXEC_BIT = 6,\n\tVMA_MAYSHARE_BIT = 7,\n\tVMA_GROWSDOWN_BIT = 8,\n\tVMA_UFFD_MISSING_BIT = 9,\n\tVMA_PFNMAP_BIT = 10,\n\tVMA_MAYBE_GUARD_BIT = 11,\n\tVMA_UFFD_WP_BIT = 12,\n\tVMA_LOCKED_BIT = 13,\n\tVMA_IO_BIT = 14,\n\tVMA_SEQ_READ_BIT = 15,\n\tVMA_RAND_READ_BIT = 16,\n\tVMA_DONTCOPY_BIT = 17,\n\tVMA_DONTEXPAND_BIT = 18,\n\tVMA_LOCKONFAULT_BIT = 19,\n\tVMA_ACCOUNT_BIT = 20,\n\tVMA_NORESERVE_BIT = 21,\n\tVMA_HUGETLB_BIT = 22,\n\tVMA_SYNC_BIT = 23,\n\tVMA_ARCH_1_BIT = 24,\n\tVMA_WIPEONFORK_BIT = 25,\n\tVMA_DONTDUMP_BIT = 26,\n\tVMA_SOFTDIRTY_BIT = 27,\n\tVMA_MIXEDMAP_BIT = 28,\n\tVMA_HUGEPAGE_BIT = 29,\n\tVMA_NOHUGEPAGE_BIT = 30,\n\tVMA_MERGEABLE_BIT = 31,\n\tVMA_HIGH_ARCH_0_BIT = 32,\n\tVMA_HIGH_ARCH_1_BIT = 33,\n\tVMA_HIGH_ARCH_2_BIT = 34,\n\tVMA_HIGH_ARCH_3_BIT = 35,\n\tVMA_HIGH_ARCH_4_BIT = 36,\n\tVMA_HIGH_ARCH_5_BIT = 37,\n\tVMA_HIGH_ARCH_6_BIT = 38,\n\tVMA_ALLOW_ANY_UNCACHED_BIT = 39,\n\tVMA_DROPPABLE_BIT = 40,\n\tVMA_UFFD_MINOR_BIT = 41,\n\tVMA_SEALED_BIT = 42,\n\tVMA_PKEY_BIT0_BIT = 32,\n\tVMA_PKEY_BIT1_BIT = 33,\n\tVMA_PKEY_BIT2_BIT = 34,\n\tVMA_PKEY_BIT3_BIT = 35,\n\tVMA_PKEY_BIT4_BIT = 36,\n\tVMA_SAO_BIT = 24,\n\tVMA_GROWSUP_BIT = 24,\n\tVMA_SPARC_ADI_BIT = 24,\n\tVMA_ARM64_BTI_BIT = 24,\n\tVMA_ARCH_CLEAR_BIT = 24,\n\tVMA_MAPPED_COPY_BIT = 24,\n\tVMA_MTE_BIT = 36,\n\tVMA_MTE_ALLOWED_BIT = 37,\n\tVMA_STACK_BIT = 8,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tXFRM_DEV_OFFLOAD_UNSPECIFIED = 0,\n\tXFRM_DEV_OFFLOAD_CRYPTO = 1,\n\tXFRM_DEV_OFFLOAD_PACKET = 2,\n};\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nenum {\n\tXFRM_MODE_FLAG_TUNNEL = 1,\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\tXFRM_MSG_SETDEFAULT = 39,\n\tXFRM_MSG_GETDEFAULT = 40,\n\t__XFRM_MSG_MAX = 41,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nenum {\n\tXFRM_STATE_VOID = 0,\n\tXFRM_STATE_ACQ = 1,\n\tXFRM_STATE_VALID = 2,\n\tXFRM_STATE_ERROR = 3,\n\tXFRM_STATE_EXPIRED = 4,\n\tXFRM_STATE_DEAD = 5,\n};\n\nenum {\n\tXFS_ERR_DEFAULT = 0,\n\tXFS_ERR_EIO = 1,\n\tXFS_ERR_ENOSPC = 2,\n\tXFS_ERR_ENODEV = 3,\n\tXFS_ERR_ERRNO_MAX = 4,\n};\n\nenum {\n\tXFS_ERR_METADATA = 0,\n\tXFS_ERR_CLASS_MAX = 1,\n};\n\nenum {\n\tXFS_LOWSP_1_PCNT = 0,\n\tXFS_LOWSP_2_PCNT = 1,\n\tXFS_LOWSP_3_PCNT = 2,\n\tXFS_LOWSP_4_PCNT = 3,\n\tXFS_LOWSP_5_PCNT = 4,\n\tXFS_LOWSP_MAX = 5,\n};\n\nenum {\n\tXFS_QLOWSP_1_PCNT = 0,\n\tXFS_QLOWSP_3_PCNT = 1,\n\tXFS_QLOWSP_5_PCNT = 2,\n\tXFS_QLOWSP_MAX = 3,\n};\n\nenum {\n\tXFS_QM_TRANS_USR = 0,\n\tXFS_QM_TRANS_GRP = 1,\n\tXFS_QM_TRANS_PRJ = 2,\n\tXFS_QM_TRANS_DQTYPES = 3,\n};\n\nenum {\n\tXIVE_DUMP_TM_HYP = 0,\n\tXIVE_DUMP_TM_POOL = 1,\n\tXIVE_DUMP_TM_OS = 2,\n\tXIVE_DUMP_TM_USER = 3,\n\tXIVE_DUMP_VP = 4,\n\tXIVE_DUMP_EMU_STATE = 5,\n};\n\nenum {\n\tXIVE_SYNC_EAS = 1,\n\tXIVE_SYNC_QUEUE = 2,\n};\n\nenum {\n\tXPT_BUSY = 0,\n\tXPT_CONN = 1,\n\tXPT_CLOSE = 2,\n\tXPT_DATA = 3,\n\tXPT_TEMP = 4,\n\tXPT_DEAD = 5,\n\tXPT_CHNGBUF = 6,\n\tXPT_DEFERRED = 7,\n\tXPT_OLD = 8,\n\tXPT_LISTENER = 9,\n\tXPT_CACHE_AUTH = 10,\n\tXPT_LOCAL = 11,\n\tXPT_KILL_TEMP = 12,\n\tXPT_CONG_CTRL = 13,\n\tXPT_HANDSHAKE = 14,\n\tXPT_TLS_SESSION = 15,\n\tXPT_PEER_AUTH = 16,\n\tXPT_PEER_VALID = 17,\n\tXPT_RPCB_UNREG = 18,\n};\n\nenum {\n\tXREP_AGF_BNOBT = 0,\n\tXREP_AGF_CNTBT = 1,\n\tXREP_AGF_RMAPBT = 2,\n\tXREP_AGF_REFCOUNTBT = 3,\n\tXREP_AGF_END = 4,\n\tXREP_AGF_MAX = 5,\n};\n\nenum {\n\tXREP_AGI_INOBT = 0,\n\tXREP_AGI_FINOBT = 1,\n\tXREP_AGI_END = 2,\n\tXREP_AGI_MAX = 3,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tZONELIST_NOFALLBACK = 1,\n\tMAX_ZONELISTS = 2,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 2048,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQ_HIDDEN = 1048576,\n\t_IRQ_NO_DEBUG = 2097152,\n\t_IRQF_MODIFY_MASK = 2080527,\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum {\n\t__SCHED_FEAT_PLACE_LAG = 0,\n\t__SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1,\n\t__SCHED_FEAT_PLACE_REL_DEADLINE = 2,\n\t__SCHED_FEAT_RUN_TO_PARITY = 3,\n\t__SCHED_FEAT_PREEMPT_SHORT = 4,\n\t__SCHED_FEAT_NEXT_BUDDY = 5,\n\t__SCHED_FEAT_PICK_BUDDY = 6,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 7,\n\t__SCHED_FEAT_DELAY_DEQUEUE = 8,\n\t__SCHED_FEAT_DELAY_ZERO = 9,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 10,\n\t__SCHED_FEAT_HRTICK = 11,\n\t__SCHED_FEAT_HRTICK_DL = 12,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 13,\n\t__SCHED_FEAT_TTWU_QUEUE = 14,\n\t__SCHED_FEAT_SIS_UTIL = 15,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 16,\n\t__SCHED_FEAT_RT_PUSH_IPI = 17,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 18,\n\t__SCHED_FEAT_LB_MIN = 19,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 20,\n\t__SCHED_FEAT_WA_IDLE = 21,\n\t__SCHED_FEAT_WA_WEIGHT = 22,\n\t__SCHED_FEAT_WA_BIAS = 23,\n\t__SCHED_FEAT_UTIL_EST = 24,\n\t__SCHED_FEAT_LATENCY_WARN = 25,\n\t__SCHED_FEAT_NI_RANDOM = 26,\n\t__SCHED_FEAT_NR = 27,\n};\n\nenum {\n\t__SD_BALANCE_NEWIDLE = 0,\n\t__SD_BALANCE_EXEC = 1,\n\t__SD_BALANCE_FORK = 2,\n\t__SD_BALANCE_WAKE = 3,\n\t__SD_WAKE_AFFINE = 4,\n\t__SD_ASYM_CPUCAPACITY = 5,\n\t__SD_ASYM_CPUCAPACITY_FULL = 6,\n\t__SD_SHARE_CPUCAPACITY = 7,\n\t__SD_CLUSTER = 8,\n\t__SD_SHARE_LLC = 9,\n\t__SD_SERIALIZE = 10,\n\t__SD_ASYM_PACKING = 11,\n\t__SD_PREFER_SIBLING = 12,\n\t__SD_NUMA = 13,\n\t__SD_FLAG_CNT = 14,\n};\n\nenum {\n\t__XBTS_lookup = 0,\n\t__XBTS_compare = 1,\n\t__XBTS_insrec = 2,\n\t__XBTS_delrec = 3,\n\t__XBTS_newroot = 4,\n\t__XBTS_killroot = 5,\n\t__XBTS_increment = 6,\n\t__XBTS_decrement = 7,\n\t__XBTS_lshift = 8,\n\t__XBTS_rshift = 9,\n\t__XBTS_split = 10,\n\t__XBTS_join = 11,\n\t__XBTS_alloc = 12,\n\t__XBTS_free = 13,\n\t__XBTS_moves = 14,\n\t__XBTS_MAX = 15,\n};\n\nenum {\n\t___GFP_DMA_BIT = 0,\n\t___GFP_HIGHMEM_BIT = 1,\n\t___GFP_DMA32_BIT = 2,\n\t___GFP_MOVABLE_BIT = 3,\n\t___GFP_RECLAIMABLE_BIT = 4,\n\t___GFP_HIGH_BIT = 5,\n\t___GFP_IO_BIT = 6,\n\t___GFP_FS_BIT = 7,\n\t___GFP_ZERO_BIT = 8,\n\t___GFP_UNUSED_BIT = 9,\n\t___GFP_DIRECT_RECLAIM_BIT = 10,\n\t___GFP_KSWAPD_RECLAIM_BIT = 11,\n\t___GFP_WRITE_BIT = 12,\n\t___GFP_NOWARN_BIT = 13,\n\t___GFP_RETRY_MAYFAIL_BIT = 14,\n\t___GFP_NOFAIL_BIT = 15,\n\t___GFP_NORETRY_BIT = 16,\n\t___GFP_MEMALLOC_BIT = 17,\n\t___GFP_COMP_BIT = 18,\n\t___GFP_NOMEMALLOC_BIT = 19,\n\t___GFP_HARDWALL_BIT = 20,\n\t___GFP_THISNODE_BIT = 21,\n\t___GFP_ACCOUNT_BIT = 22,\n\t___GFP_ZEROTAGS_BIT = 23,\n\t___GFP_NO_OBJ_EXT_BIT = 24,\n\t___GFP_LAST_BIT = 25,\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SKB = 4,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK = 5,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 7,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 8,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 9,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 10,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 11,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 12,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 13,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 14,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 15,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 16,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 17,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 18,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 19,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 20,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_DEVICE = 21,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SYSCTL = 22,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCKOPT = 23,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 24,\n\t__ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 25,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 26,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 27,\n\t__ctx_convertBPF_PROG_TYPE_LSM = 28,\n\t__ctx_convertBPF_PROG_TYPE_SYSCALL = 29,\n\t__ctx_convertBPF_PROG_TYPE_NETFILTER = 30,\n\t__ctx_convert_unused = 31,\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_sra_exceeded_retry_limit = 5,\n\tattr_inode_readahead = 6,\n\tattr_trigger_test_error = 7,\n\tattr_first_error_time = 8,\n\tattr_last_error_time = 9,\n\tattr_clusters_in_group = 10,\n\tattr_mb_order = 11,\n\tattr_feature = 12,\n\tattr_pointer_pi = 13,\n\tattr_pointer_ui = 14,\n\tattr_pointer_ul = 15,\n\tattr_pointer_u64 = 16,\n\tattr_pointer_u8 = 17,\n\tattr_pointer_string = 18,\n\tattr_pointer_atomic = 19,\n\tattr_journal_task = 20,\n\tattr_err_report_sec = 21,\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tcmap_unknown = 0,\n\tcmap_simple = 1,\n\tcmap_r128 = 2,\n\tcmap_M3A = 3,\n\tcmap_M3B = 4,\n\tcmap_radeon = 5,\n\tcmap_gxt2000 = 6,\n\tcmap_avivo = 7,\n\tcmap_qemu = 8,\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nenum {\n\te1000_10_half = 0,\n\te1000_10_full = 1,\n\te1000_100_half = 2,\n\te1000_100_full = 3,\n};\n\nenum {\n\te1000_igp_cable_length_10 = 10,\n\te1000_igp_cable_length_20 = 20,\n\te1000_igp_cable_length_30 = 30,\n\te1000_igp_cable_length_40 = 40,\n\te1000_igp_cable_length_50 = 50,\n\te1000_igp_cable_length_60 = 60,\n\te1000_igp_cable_length_70 = 70,\n\te1000_igp_cable_length_80 = 80,\n\te1000_igp_cable_length_90 = 90,\n\te1000_igp_cable_length_100 = 100,\n\te1000_igp_cable_length_110 = 110,\n\te1000_igp_cable_length_115 = 115,\n\te1000_igp_cable_length_120 = 120,\n\te1000_igp_cable_length_130 = 130,\n\te1000_igp_cable_length_140 = 140,\n\te1000_igp_cable_length_150 = 150,\n\te1000_igp_cable_length_160 = 160,\n\te1000_igp_cable_length_170 = 170,\n\te1000_igp_cable_length_180 = 180,\n};\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\nenum {\n\tmask_exec = 0,\n\tmask_write = 1,\n\tmask_read = 2,\n\tmask_append = 3,\n};\n\nenum {\n\tmechtype_caddy = 0,\n\tmechtype_tray = 1,\n\tmechtype_popup = 2,\n\tmechtype_individual_changer = 4,\n\tmechtype_cartridge_changer = 5,\n};\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nenum {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\ntypedef enum {\n\tBIT_DStream_unfinished = 0,\n\tBIT_DStream_endOfBuffer = 1,\n\tBIT_DStream_completed = 2,\n\tBIT_DStream_overflow = 3,\n} BIT_DStream_status;\n\ntypedef enum {\n\tZSTD_error_no_error = 0,\n\tZSTD_error_GENERIC = 1,\n\tZSTD_error_prefix_unknown = 10,\n\tZSTD_error_version_unsupported = 12,\n\tZSTD_error_frameParameter_unsupported = 14,\n\tZSTD_error_frameParameter_windowTooLarge = 16,\n\tZSTD_error_corruption_detected = 20,\n\tZSTD_error_checksum_wrong = 22,\n\tZSTD_error_literals_headerWrong = 24,\n\tZSTD_error_dictionary_corrupted = 30,\n\tZSTD_error_dictionary_wrong = 32,\n\tZSTD_error_dictionaryCreation_failed = 34,\n\tZSTD_error_parameter_unsupported = 40,\n\tZSTD_error_parameter_combination_unsupported = 41,\n\tZSTD_error_parameter_outOfBound = 42,\n\tZSTD_error_tableLog_tooLarge = 44,\n\tZSTD_error_maxSymbolValue_tooLarge = 46,\n\tZSTD_error_maxSymbolValue_tooSmall = 48,\n\tZSTD_error_cannotProduce_uncompressedBlock = 49,\n\tZSTD_error_stabilityCondition_notRespected = 50,\n\tZSTD_error_stage_wrong = 60,\n\tZSTD_error_init_missing = 62,\n\tZSTD_error_memory_allocation = 64,\n\tZSTD_error_workSpace_tooSmall = 66,\n\tZSTD_error_dstSize_tooSmall = 70,\n\tZSTD_error_srcSize_wrong = 72,\n\tZSTD_error_dstBuffer_null = 74,\n\tZSTD_error_noForwardProgress_destFull = 80,\n\tZSTD_error_noForwardProgress_inputEmpty = 82,\n\tZSTD_error_frameIndex_tooLarge = 100,\n\tZSTD_error_seekableIO = 102,\n\tZSTD_error_dstBuffer_wrong = 104,\n\tZSTD_error_srcBuffer_wrong = 105,\n\tZSTD_error_sequenceProducer_failed = 106,\n\tZSTD_error_externalSequences_invalid = 107,\n\tZSTD_error_maxCode = 120,\n} ZSTD_ErrorCode;\n\ntypedef ZSTD_ErrorCode ERR_enum;\n\ntypedef enum {\n\tset_basic = 0,\n\tset_rle = 1,\n\tset_compressed = 2,\n\tset_repeat = 3,\n} SymbolEncodingType_e;\n\ntypedef enum {\n\tZSTD_frame = 0,\n\tZSTD_skippableFrame = 1,\n} ZSTD_FrameType_e;\n\ntypedef enum {\n\tZSTD_reset_session_only = 1,\n\tZSTD_reset_parameters = 2,\n\tZSTD_reset_session_and_parameters = 3,\n} ZSTD_ResetDirective;\n\ntypedef enum {\n\tZSTD_bm_buffered = 0,\n\tZSTD_bm_stable = 1,\n} ZSTD_bufferMode_e;\n\ntypedef enum {\n\tZSTD_d_windowLogMax = 100,\n\tZSTD_d_experimentalParam1 = 1000,\n\tZSTD_d_experimentalParam2 = 1001,\n\tZSTD_d_experimentalParam3 = 1002,\n\tZSTD_d_experimentalParam4 = 1003,\n\tZSTD_d_experimentalParam5 = 1004,\n\tZSTD_d_experimentalParam6 = 1005,\n} ZSTD_dParameter;\n\ntypedef enum {\n\tZSTDds_getFrameHeaderSize = 0,\n\tZSTDds_decodeFrameHeader = 1,\n\tZSTDds_decodeBlockHeader = 2,\n\tZSTDds_decompressBlock = 3,\n\tZSTDds_decompressLastBlock = 4,\n\tZSTDds_checkChecksum = 5,\n\tZSTDds_decodeSkippableHeader = 6,\n\tZSTDds_skipFrame = 7,\n} ZSTD_dStage;\n\ntypedef enum {\n\tzdss_init = 0,\n\tzdss_loadHeader = 1,\n\tzdss_read = 2,\n\tzdss_load = 3,\n\tzdss_flush = 4,\n} ZSTD_dStreamStage;\n\ntypedef enum {\n\tZSTD_dct_auto = 0,\n\tZSTD_dct_rawContent = 1,\n\tZSTD_dct_fullDict = 2,\n} ZSTD_dictContentType_e;\n\ntypedef enum {\n\tZSTD_dlm_byCopy = 0,\n\tZSTD_dlm_byRef = 1,\n} ZSTD_dictLoadMethod_e;\n\ntypedef enum {\n\tZSTD_use_indefinitely = -1,\n\tZSTD_dont_use = 0,\n\tZSTD_use_once = 1,\n} ZSTD_dictUses_e;\n\ntypedef enum {\n\tZSTD_d_validateChecksum = 0,\n\tZSTD_d_ignoreChecksum = 1,\n} ZSTD_forceIgnoreChecksum_e;\n\ntypedef enum {\n\tZSTD_f_zstd1 = 0,\n\tZSTD_f_zstd1_magicless = 1,\n} ZSTD_format_e;\n\ntypedef enum {\n\tZSTD_not_in_dst = 0,\n\tZSTD_in_dst = 1,\n\tZSTD_split = 2,\n} ZSTD_litLocation_e;\n\ntypedef enum {\n\tZSTD_lo_isRegularOffset = 0,\n\tZSTD_lo_isLongOffset = 1,\n} ZSTD_longOffset_e;\n\ntypedef enum {\n\tZSTDnit_frameHeader = 0,\n\tZSTDnit_blockHeader = 1,\n\tZSTDnit_block = 2,\n\tZSTDnit_lastBlock = 3,\n\tZSTDnit_checksum = 4,\n\tZSTDnit_skippableFrame = 5,\n} ZSTD_nextInputType_e;\n\ntypedef enum {\n\tZSTD_no_overlap = 0,\n\tZSTD_overlap_src_before_dst = 1,\n} ZSTD_overlap_e;\n\ntypedef enum {\n\tZSTD_rmd_refSingleDDict = 0,\n\tZSTD_rmd_refMultipleDDicts = 1,\n} ZSTD_refMultipleDDicts_e;\n\ntypedef enum {\n\tbt_raw = 0,\n\tbt_rle = 1,\n\tbt_compressed = 2,\n\tbt_reserved = 3,\n} blockType_e;\n\ntypedef enum {\n\tneed_more = 0,\n\tblock_done = 1,\n\tfinish_started = 2,\n\tfinish_done = 3,\n} block_state;\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_EXCLUSIVE_CPULIST = 6,\n\tFILE_EFFECTIVE_XCPULIST = 7,\n\tFILE_ISOLATED_CPULIST = 8,\n\tFILE_CPU_EXCLUSIVE = 9,\n\tFILE_MEM_EXCLUSIVE = 10,\n\tFILE_MEM_HARDWALL = 11,\n\tFILE_SCHED_LOAD_BALANCE = 12,\n\tFILE_PARTITION_ROOT = 13,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 14,\n\tFILE_MEMORY_PRESSURE_ENABLED = 15,\n\tFILE_MEMORY_PRESSURE = 16,\n\tFILE_SPREAD_PAGE = 17,\n\tFILE_SPREAD_SLAB = 18,\n} cpuset_filetype_t;\n\ntypedef enum {\n\tCS_CPU_EXCLUSIVE = 0,\n\tCS_MEM_EXCLUSIVE = 1,\n\tCS_MEM_HARDWALL = 2,\n\tCS_MEMORY_MIGRATE = 3,\n\tCS_SCHED_LOAD_BALANCE = 4,\n\tCS_SPREAD_PAGE = 5,\n\tCS_SPREAD_SLAB = 6,\n} cpuset_flagbits_t;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\ntypedef enum {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok = 1,\n\te1000_1000t_rx_status_undefined = 255,\n} e1000_1000t_rx_status;\n\ntypedef enum {\n\te1000_10bt_ext_dist_enable_normal = 0,\n\te1000_10bt_ext_dist_enable_lower = 1,\n\te1000_10bt_ext_dist_enable_undefined = 255,\n} e1000_10bt_ext_dist_enable;\n\ntypedef enum {\n\te1000_auto_x_mode_manual_mdi = 0,\n\te1000_auto_x_mode_manual_mdix = 1,\n\te1000_auto_x_mode_auto1 = 2,\n\te1000_auto_x_mode_auto2 = 3,\n\te1000_auto_x_mode_undefined = 255,\n} e1000_auto_x_mode;\n\ntypedef enum {\n\te1000_bus_speed_unknown = 0,\n\te1000_bus_speed_33 = 1,\n\te1000_bus_speed_66 = 2,\n\te1000_bus_speed_100 = 3,\n\te1000_bus_speed_120 = 4,\n\te1000_bus_speed_133 = 5,\n\te1000_bus_speed_reserved = 6,\n} e1000_bus_speed;\n\ntypedef enum {\n\te1000_bus_type_unknown = 0,\n\te1000_bus_type_pci = 1,\n\te1000_bus_type_pcix = 2,\n\te1000_bus_type_reserved = 3,\n} e1000_bus_type;\n\ntypedef enum {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_32 = 1,\n\te1000_bus_width_64 = 2,\n\te1000_bus_width_reserved = 3,\n} e1000_bus_width;\n\ntypedef enum {\n\te1000_cable_length_50 = 0,\n\te1000_cable_length_50_80 = 1,\n\te1000_cable_length_80_110 = 2,\n\te1000_cable_length_110_140 = 3,\n\te1000_cable_length_140 = 4,\n\te1000_cable_length_undefined = 255,\n} e1000_cable_length;\n\ntypedef enum {\n\te1000_downshift_normal = 0,\n\te1000_downshift_activated = 1,\n\te1000_downshift_undefined = 255,\n} e1000_downshift;\n\ntypedef enum {\n\te1000_dsp_config_disabled = 0,\n\te1000_dsp_config_enabled = 1,\n\te1000_dsp_config_activated = 2,\n\te1000_dsp_config_undefined = 255,\n} e1000_dsp_config;\n\ntypedef enum {\n\te1000_eeprom_uninitialized = 0,\n\te1000_eeprom_spi = 1,\n\te1000_eeprom_microwire = 2,\n\te1000_eeprom_flash = 3,\n\te1000_eeprom_none = 4,\n\te1000_num_eeprom_types = 5,\n} e1000_eeprom_type;\n\ntypedef enum {\n\tE1000_FC_NONE = 0,\n\tE1000_FC_RX_PAUSE = 1,\n\tE1000_FC_TX_PAUSE = 2,\n\tE1000_FC_FULL = 3,\n\tE1000_FC_DEFAULT = 255,\n} e1000_fc_type;\n\ntypedef enum {\n\te1000_ffe_config_enabled = 0,\n\te1000_ffe_config_active = 1,\n\te1000_ffe_config_blocked = 2,\n} e1000_ffe_config;\n\ntypedef enum {\n\te1000_undefined = 0,\n\te1000_82542_rev2_0 = 1,\n\te1000_82542_rev2_1 = 2,\n\te1000_82543 = 3,\n\te1000_82544 = 4,\n\te1000_82540 = 5,\n\te1000_82545 = 6,\n\te1000_82545_rev_3 = 7,\n\te1000_82546 = 8,\n\te1000_ce4100 = 9,\n\te1000_82546_rev_3 = 10,\n\te1000_82541 = 11,\n\te1000_82541_rev_2 = 12,\n\te1000_82547 = 13,\n\te1000_82547_rev_2 = 14,\n\te1000_num_macs = 15,\n} e1000_mac_type;\n\ntypedef enum {\n\te1000_media_type_copper = 0,\n\te1000_media_type_fiber = 1,\n\te1000_media_type_internal_serdes = 2,\n\te1000_num_media_types = 3,\n} e1000_media_type;\n\ntypedef enum {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master = 1,\n\te1000_ms_force_slave = 2,\n\te1000_ms_auto = 3,\n} e1000_ms_type;\n\ntypedef enum {\n\te1000_phy_m88 = 0,\n\te1000_phy_igp = 1,\n\te1000_phy_8211 = 2,\n\te1000_phy_8201 = 3,\n\te1000_phy_undefined = 255,\n} e1000_phy_type;\n\ntypedef enum {\n\te1000_polarity_reversal_enabled = 0,\n\te1000_polarity_reversal_disabled = 1,\n\te1000_polarity_reversal_undefined = 255,\n} e1000_polarity_reversal;\n\ntypedef enum {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed = 1,\n\te1000_rev_polarity_undefined = 255,\n} e1000_rev_polarity;\n\ntypedef enum {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on = 1,\n\te1000_smart_speed_off = 2,\n} e1000_smart_speed;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n\tEXT4_IGET_BAD = 4,\n\tEXT4_IGET_EA_INODE = 8,\n} ext4_iget_flags;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\ntypedef enum {\n\tMAP_CHG_REUSE = 0,\n\tMAP_CHG_NEEDED = 1,\n\tMAP_CHG_ENFORCED = 2,\n} map_chg_state;\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_REVRMII = 8,\n\tPHY_INTERFACE_MODE_RGMII = 9,\n\tPHY_INTERFACE_MODE_RGMII_ID = 10,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 11,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 12,\n\tPHY_INTERFACE_MODE_RTBI = 13,\n\tPHY_INTERFACE_MODE_SMII = 14,\n\tPHY_INTERFACE_MODE_XGMII = 15,\n\tPHY_INTERFACE_MODE_XLGMII = 16,\n\tPHY_INTERFACE_MODE_MOCA = 17,\n\tPHY_INTERFACE_MODE_PSGMII = 18,\n\tPHY_INTERFACE_MODE_QSGMII = 19,\n\tPHY_INTERFACE_MODE_TRGMII = 20,\n\tPHY_INTERFACE_MODE_100BASEX = 21,\n\tPHY_INTERFACE_MODE_1000BASEX = 22,\n\tPHY_INTERFACE_MODE_2500BASEX = 23,\n\tPHY_INTERFACE_MODE_5GBASER = 24,\n\tPHY_INTERFACE_MODE_RXAUI = 25,\n\tPHY_INTERFACE_MODE_XAUI = 26,\n\tPHY_INTERFACE_MODE_10GBASER = 27,\n\tPHY_INTERFACE_MODE_25GBASER = 28,\n\tPHY_INTERFACE_MODE_USXGMII = 29,\n\tPHY_INTERFACE_MODE_10GKR = 30,\n\tPHY_INTERFACE_MODE_QUSGMII = 31,\n\tPHY_INTERFACE_MODE_1000BASEKX = 32,\n\tPHY_INTERFACE_MODE_10G_QXGMII = 33,\n\tPHY_INTERFACE_MODE_50GBASER = 34,\n\tPHY_INTERFACE_MODE_LAUI = 35,\n\tPHY_INTERFACE_MODE_100GBASEP = 36,\n\tPHY_INTERFACE_MODE_MIILITE = 37,\n\tPHY_INTERFACE_MODE_MAX = 38,\n} phy_interface_t;\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\ntypedef enum {\n\tSTATUSTYPE_INFO = 0,\n\tSTATUSTYPE_TABLE = 1,\n\tSTATUSTYPE_IMA = 2,\n} status_type_t;\n\ntypedef enum {\n\tnot_streaming = 0,\n\tis_streaming = 1,\n} streaming_operation;\n\ntypedef enum {\n\tXFS_EXT_NORM = 0,\n\tXFS_EXT_UNWRITTEN = 1,\n} xfs_exntst_t;\n\ntypedef enum {\n\tXFS_LOOKUP_EQi = 0,\n\tXFS_LOOKUP_LEi = 1,\n\tXFS_LOOKUP_GEi = 2,\n} xfs_lookup_t;\n\ntypedef ZSTD_ErrorCode zstd_error_code;\n\nenum CSI_J {\n\tCSI_J_CURSOR_TO_END = 0,\n\tCSI_J_START_TO_CURSOR = 1,\n\tCSI_J_VISIBLE = 2,\n\tCSI_J_FULL = 3,\n};\n\nenum CSI_right_square_bracket {\n\tCSI_RSB_COLOR_FOR_UNDERLINE = 1,\n\tCSI_RSB_COLOR_FOR_HALF_BRIGHT = 2,\n\tCSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8,\n\tCSI_RSB_BLANKING_INTERVAL = 9,\n\tCSI_RSB_BELL_FREQUENCY = 10,\n\tCSI_RSB_BELL_DURATION = 11,\n\tCSI_RSB_BRING_CONSOLE_TO_FRONT = 12,\n\tCSI_RSB_UNBLANK = 13,\n\tCSI_RSB_VESA_OFF_INTERVAL = 14,\n\tCSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15,\n\tCSI_RSB_CURSOR_BLINK_INTERVAL = 16,\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nenum MCE_Disposition {\n\tMCE_DISPOSITION_RECOVERED = 0,\n\tMCE_DISPOSITION_NOT_RECOVERED = 1,\n};\n\nenum MCE_EratErrorType {\n\tMCE_ERAT_ERROR_INDETERMINATE = 0,\n\tMCE_ERAT_ERROR_PARITY = 1,\n\tMCE_ERAT_ERROR_MULTIHIT = 2,\n};\n\nenum MCE_ErrorClass {\n\tMCE_ECLASS_UNKNOWN = 0,\n\tMCE_ECLASS_HARDWARE = 1,\n\tMCE_ECLASS_HARD_INDETERMINATE = 2,\n\tMCE_ECLASS_SOFTWARE = 3,\n\tMCE_ECLASS_SOFT_INDETERMINATE = 4,\n};\n\nenum MCE_ErrorType {\n\tMCE_ERROR_TYPE_UNKNOWN = 0,\n\tMCE_ERROR_TYPE_UE = 1,\n\tMCE_ERROR_TYPE_SLB = 2,\n\tMCE_ERROR_TYPE_ERAT = 3,\n\tMCE_ERROR_TYPE_TLB = 4,\n\tMCE_ERROR_TYPE_USER = 5,\n\tMCE_ERROR_TYPE_RA = 6,\n\tMCE_ERROR_TYPE_LINK = 7,\n\tMCE_ERROR_TYPE_DCACHE = 8,\n\tMCE_ERROR_TYPE_ICACHE = 9,\n};\n\nenum MCE_Initiator {\n\tMCE_INITIATOR_UNKNOWN = 0,\n\tMCE_INITIATOR_CPU = 1,\n\tMCE_INITIATOR_PCI = 2,\n\tMCE_INITIATOR_ISA = 3,\n\tMCE_INITIATOR_MEMORY = 4,\n\tMCE_INITIATOR_POWERMGM = 5,\n};\n\nenum MCE_LinkErrorType {\n\tMCE_LINK_ERROR_INDETERMINATE = 0,\n\tMCE_LINK_ERROR_IFETCH_TIMEOUT = 1,\n\tMCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT = 2,\n\tMCE_LINK_ERROR_LOAD_TIMEOUT = 3,\n\tMCE_LINK_ERROR_STORE_TIMEOUT = 4,\n\tMCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT = 5,\n};\n\nenum MCE_RaErrorType {\n\tMCE_RA_ERROR_INDETERMINATE = 0,\n\tMCE_RA_ERROR_IFETCH = 1,\n\tMCE_RA_ERROR_IFETCH_FOREIGN = 2,\n\tMCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH = 3,\n\tMCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN = 4,\n\tMCE_RA_ERROR_LOAD = 5,\n\tMCE_RA_ERROR_STORE = 6,\n\tMCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 7,\n\tMCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN = 8,\n\tMCE_RA_ERROR_LOAD_STORE_FOREIGN = 9,\n};\n\nenum MCE_Severity {\n\tMCE_SEV_NO_ERROR = 0,\n\tMCE_SEV_WARNING = 1,\n\tMCE_SEV_SEVERE = 2,\n\tMCE_SEV_FATAL = 3,\n};\n\nenum MCE_SlbErrorType {\n\tMCE_SLB_ERROR_INDETERMINATE = 0,\n\tMCE_SLB_ERROR_PARITY = 1,\n\tMCE_SLB_ERROR_MULTIHIT = 2,\n};\n\nenum MCE_TlbErrorType {\n\tMCE_TLB_ERROR_INDETERMINATE = 0,\n\tMCE_TLB_ERROR_PARITY = 1,\n\tMCE_TLB_ERROR_MULTIHIT = 2,\n};\n\nenum MCE_UeErrorType {\n\tMCE_UE_ERROR_INDETERMINATE = 0,\n\tMCE_UE_ERROR_IFETCH = 1,\n\tMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,\n\tMCE_UE_ERROR_LOAD_STORE = 3,\n\tMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,\n};\n\nenum MCE_UserErrorType {\n\tMCE_USER_ERROR_INDETERMINATE = 0,\n\tMCE_USER_ERROR_TLBIE = 1,\n\tMCE_USER_ERROR_SCV = 2,\n};\n\nenum MCE_Version {\n\tMCE_V1 = 1,\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecPublicKey = 2,\n\tOID_id_prime192v1 = 3,\n\tOID_id_prime256v1 = 4,\n\tOID_id_ecdsa_with_sha1 = 5,\n\tOID_id_ecdsa_with_sha224 = 6,\n\tOID_id_ecdsa_with_sha256 = 7,\n\tOID_id_ecdsa_with_sha384 = 8,\n\tOID_id_ecdsa_with_sha512 = 9,\n\tOID_rsaEncryption = 10,\n\tOID_sha1WithRSAEncryption = 11,\n\tOID_sha256WithRSAEncryption = 12,\n\tOID_sha384WithRSAEncryption = 13,\n\tOID_sha512WithRSAEncryption = 14,\n\tOID_sha224WithRSAEncryption = 15,\n\tOID_data = 16,\n\tOID_signed_data = 17,\n\tOID_email_address = 18,\n\tOID_contentType = 19,\n\tOID_messageDigest = 20,\n\tOID_signingTime = 21,\n\tOID_smimeCapabilites = 22,\n\tOID_smimeAuthenticatedAttrs = 23,\n\tOID_mskrb5 = 24,\n\tOID_krb5 = 25,\n\tOID_krb5u2u = 26,\n\tOID_msIndirectData = 27,\n\tOID_msStatementType = 28,\n\tOID_msSpOpusInfo = 29,\n\tOID_msPeImageDataObjId = 30,\n\tOID_msIndividualSPKeyPurpose = 31,\n\tOID_msOutlookExpress = 32,\n\tOID_ntlmssp = 33,\n\tOID_negoex = 34,\n\tOID_spnego = 35,\n\tOID_IAKerb = 36,\n\tOID_PKU2U = 37,\n\tOID_Scram = 38,\n\tOID_certAuthInfoAccess = 39,\n\tOID_sha1 = 40,\n\tOID_id_ansip384r1 = 41,\n\tOID_id_ansip521r1 = 42,\n\tOID_sha256 = 43,\n\tOID_sha384 = 44,\n\tOID_sha512 = 45,\n\tOID_sha224 = 46,\n\tOID_commonName = 47,\n\tOID_surname = 48,\n\tOID_countryName = 49,\n\tOID_locality = 50,\n\tOID_stateOrProvinceName = 51,\n\tOID_organizationName = 52,\n\tOID_organizationUnitName = 53,\n\tOID_title = 54,\n\tOID_description = 55,\n\tOID_name = 56,\n\tOID_givenName = 57,\n\tOID_initials = 58,\n\tOID_generationalQualifier = 59,\n\tOID_subjectKeyIdentifier = 60,\n\tOID_keyUsage = 61,\n\tOID_subjectAltName = 62,\n\tOID_issuerAltName = 63,\n\tOID_basicConstraints = 64,\n\tOID_crlDistributionPoints = 65,\n\tOID_certPolicies = 66,\n\tOID_authorityKeyIdentifier = 67,\n\tOID_extKeyUsage = 68,\n\tOID_NetlogonMechanism = 69,\n\tOID_appleLocalKdcSupported = 70,\n\tOID_gostCPSignA = 71,\n\tOID_gostCPSignB = 72,\n\tOID_gostCPSignC = 73,\n\tOID_gost2012PKey256 = 74,\n\tOID_gost2012PKey512 = 75,\n\tOID_gost2012Digest256 = 76,\n\tOID_gost2012Digest512 = 77,\n\tOID_gost2012Signature256 = 78,\n\tOID_gost2012Signature512 = 79,\n\tOID_gostTC26Sign256A = 80,\n\tOID_gostTC26Sign256B = 81,\n\tOID_gostTC26Sign256C = 82,\n\tOID_gostTC26Sign256D = 83,\n\tOID_gostTC26Sign512A = 84,\n\tOID_gostTC26Sign512B = 85,\n\tOID_gostTC26Sign512C = 86,\n\tOID_sm2 = 87,\n\tOID_sm3 = 88,\n\tOID_SM2_with_SM3 = 89,\n\tOID_sm3WithRSAEncryption = 90,\n\tOID_TPMLoadableKey = 91,\n\tOID_TPMImportableKey = 92,\n\tOID_TPMSealedData = 93,\n\tOID_sha3_256 = 94,\n\tOID_sha3_384 = 95,\n\tOID_sha3_512 = 96,\n\tOID_id_ecdsa_with_sha3_256 = 97,\n\tOID_id_ecdsa_with_sha3_384 = 98,\n\tOID_id_ecdsa_with_sha3_512 = 99,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101,\n\tOID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102,\n\tOID_id_ml_dsa_44 = 103,\n\tOID_id_ml_dsa_65 = 104,\n\tOID_id_ml_dsa_87 = 105,\n\tOID__NR = 106,\n};\n\nenum OpalDeviceCompare {\n\tOPAL_IGNORE_RID_DEVICE_NUMBER = 0,\n\tOPAL_COMPARE_RID_DEVICE_NUMBER = 1,\n};\n\nenum OpalEehFreezeActionToken {\n\tOPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,\n\tOPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,\n\tOPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,\n\tOPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,\n\tOPAL_EEH_ACTION_SET_FREEZE_DMA = 2,\n\tOPAL_EEH_ACTION_SET_FREEZE_ALL = 3,\n};\n\nenum OpalErrinjectFunc {\n\tOPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,\n\tOPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,\n\tOPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,\n\tOPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,\n\tOPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,\n\tOPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,\n\tOPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,\n\tOPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,\n\tOPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,\n\tOPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,\n\tOPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,\n\tOPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,\n\tOPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,\n};\n\nenum OpalErrinjectType {\n\tOPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,\n\tOPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,\n};\n\nenum OpalFreezeState {\n\tOPAL_EEH_STOPPED_NOT_FROZEN = 0,\n\tOPAL_EEH_STOPPED_MMIO_FREEZE = 1,\n\tOPAL_EEH_STOPPED_DMA_FREEZE = 2,\n\tOPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,\n\tOPAL_EEH_STOPPED_RESET = 4,\n\tOPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,\n\tOPAL_EEH_STOPPED_PERM_UNAVAIL = 6,\n};\n\nenum OpalFuncCompare {\n\tOPAL_IGNORE_RID_FUNCTION_NUMBER = 0,\n\tOPAL_COMPARE_RID_FUNCTION_NUMBER = 1,\n};\n\nenum OpalHMI_CoreXstopReason {\n\tCORE_CHECKSTOP_IFU_REGFILE = 1,\n\tCORE_CHECKSTOP_IFU_LOGIC = 2,\n\tCORE_CHECKSTOP_PC_DURING_RECOV = 4,\n\tCORE_CHECKSTOP_ISU_REGFILE = 8,\n\tCORE_CHECKSTOP_ISU_LOGIC = 16,\n\tCORE_CHECKSTOP_FXU_LOGIC = 32,\n\tCORE_CHECKSTOP_VSU_LOGIC = 64,\n\tCORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 128,\n\tCORE_CHECKSTOP_LSU_REGFILE = 256,\n\tCORE_CHECKSTOP_PC_FWD_PROGRESS = 512,\n\tCORE_CHECKSTOP_LSU_LOGIC = 1024,\n\tCORE_CHECKSTOP_PC_LOGIC = 2048,\n\tCORE_CHECKSTOP_PC_HYP_RESOURCE = 4096,\n\tCORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 8192,\n\tCORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 16384,\n\tCORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 32768,\n\tCORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 65536,\n};\n\nenum OpalHMI_Disposition {\n\tOpalHMI_DISPOSITION_RECOVERED = 0,\n\tOpalHMI_DISPOSITION_NOT_RECOVERED = 1,\n};\n\nenum OpalHMI_ErrType {\n\tOpalHMI_ERROR_MALFUNC_ALERT = 0,\n\tOpalHMI_ERROR_PROC_RECOV_DONE = 1,\n\tOpalHMI_ERROR_PROC_RECOV_DONE_AGAIN = 2,\n\tOpalHMI_ERROR_PROC_RECOV_MASKED = 3,\n\tOpalHMI_ERROR_TFAC = 4,\n\tOpalHMI_ERROR_TFMR_PARITY = 5,\n\tOpalHMI_ERROR_HA_OVERFLOW_WARN = 6,\n\tOpalHMI_ERROR_XSCOM_FAIL = 7,\n\tOpalHMI_ERROR_XSCOM_DONE = 8,\n\tOpalHMI_ERROR_SCOM_FIR = 9,\n\tOpalHMI_ERROR_DEBUG_TRIG_FIR = 10,\n\tOpalHMI_ERROR_HYP_RESOURCE = 11,\n\tOpalHMI_ERROR_CAPP_RECOVERY = 12,\n};\n\nenum OpalHMI_NestAccelXstopReason {\n\tNX_CHECKSTOP_SHM_INVAL_STATE_ERR = 1,\n\tNX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 2,\n\tNX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 4,\n\tNX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 8,\n\tNX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 16,\n\tNX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 32,\n\tNX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 64,\n\tNX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 128,\n\tNX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 256,\n\tNX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 512,\n\tNX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 1024,\n\tNX_CHECKSTOP_DMA_CRB_UE = 2048,\n\tNX_CHECKSTOP_DMA_CRB_SUE = 4096,\n\tNX_CHECKSTOP_PBI_ISN_UE = 8192,\n};\n\nenum OpalHMI_Severity {\n\tOpalHMI_SEV_NO_ERROR = 0,\n\tOpalHMI_SEV_WARNING = 1,\n\tOpalHMI_SEV_ERROR_SYNC = 2,\n\tOpalHMI_SEV_FATAL = 3,\n};\n\nenum OpalHMI_Version {\n\tOpalHMIEvt_V1 = 1,\n\tOpalHMIEvt_V2 = 2,\n};\n\nenum OpalHMI_XstopType {\n\tCHECKSTOP_TYPE_UNKNOWN = 0,\n\tCHECKSTOP_TYPE_CORE = 1,\n\tCHECKSTOP_TYPE_NX = 2,\n\tCHECKSTOP_TYPE_NPU = 3,\n};\n\nenum OpalLPCAddressType {\n\tOPAL_LPC_MEM = 0,\n\tOPAL_LPC_IO = 1,\n\tOPAL_LPC_FW = 2,\n};\n\nenum OpalM64Action {\n\tOPAL_DISABLE_M64 = 0,\n\tOPAL_ENABLE_M64_SPLIT = 1,\n\tOPAL_ENABLE_M64_NON_SPLIT = 2,\n};\n\nenum OpalMmioWindowType {\n\tOPAL_M32_WINDOW_TYPE = 1,\n\tOPAL_M64_WINDOW_TYPE = 2,\n\tOPAL_IO_WINDOW_TYPE = 3,\n};\n\nenum OpalPciBusCompare {\n\tOpalPciBusAny = 0,\n\tOpalPciBus3Bits = 2,\n\tOpalPciBus4Bits = 3,\n\tOpalPciBus5Bits = 4,\n\tOpalPciBus6Bits = 5,\n\tOpalPciBus7Bits = 6,\n\tOpalPciBusAll = 7,\n};\n\nenum OpalPciErrorSeverity {\n\tOPAL_EEH_SEV_NO_ERROR = 0,\n\tOPAL_EEH_SEV_IOC_DEAD = 1,\n\tOPAL_EEH_SEV_PHB_DEAD = 2,\n\tOPAL_EEH_SEV_PHB_FENCED = 3,\n\tOPAL_EEH_SEV_PE_ER = 4,\n\tOPAL_EEH_SEV_INF = 5,\n};\n\nenum OpalPciReinitScope {\n\tOPAL_REINIT_PCI_DEV = 1000,\n};\n\nenum OpalPciResetScope {\n\tOPAL_RESET_PHB_COMPLETE = 1,\n\tOPAL_RESET_PCI_LINK = 2,\n\tOPAL_RESET_PHB_ERROR = 3,\n\tOPAL_RESET_PCI_HOT = 4,\n\tOPAL_RESET_PCI_FUNDAMENTAL = 5,\n\tOPAL_RESET_PCI_IODA_TABLE = 6,\n};\n\nenum OpalPciResetState {\n\tOPAL_DEASSERT_RESET = 0,\n\tOPAL_ASSERT_RESET = 1,\n};\n\nenum OpalPciStatusToken {\n\tOPAL_EEH_NO_ERROR = 0,\n\tOPAL_EEH_IOC_ERROR = 1,\n\tOPAL_EEH_PHB_ERROR = 2,\n\tOPAL_EEH_PE_ERROR = 3,\n\tOPAL_EEH_PE_MMIO_ERROR = 4,\n\tOPAL_EEH_PE_DMA_ERROR = 5,\n};\n\nenum OpalPeAction {\n\tOPAL_UNMAP_PE = 0,\n\tOPAL_MAP_PE = 1,\n};\n\nenum OpalPeltvAction {\n\tOPAL_REMOVE_PE_FROM_DOMAIN = 0,\n\tOPAL_ADD_PE_TO_DOMAIN = 1,\n};\n\nenum OpalPendingState {\n\tOPAL_EVENT_OPAL_INTERNAL = 1,\n\tOPAL_EVENT_NVRAM = 2,\n\tOPAL_EVENT_RTC = 4,\n\tOPAL_EVENT_CONSOLE_OUTPUT = 8,\n\tOPAL_EVENT_CONSOLE_INPUT = 16,\n\tOPAL_EVENT_ERROR_LOG_AVAIL = 32,\n\tOPAL_EVENT_ERROR_LOG = 64,\n\tOPAL_EVENT_EPOW = 128,\n\tOPAL_EVENT_LED_STATUS = 256,\n\tOPAL_EVENT_PCI_ERROR = 512,\n\tOPAL_EVENT_DUMP_AVAIL = 1024,\n\tOPAL_EVENT_MSG_PENDING = 2048,\n};\n\nenum OpalSysEpow {\n\tOPAL_SYSEPOW_POWER = 0,\n\tOPAL_SYSEPOW_TEMP = 1,\n\tOPAL_SYSEPOW_COOLING = 2,\n\tOPAL_SYSEPOW_MAX = 3,\n};\n\nenum OpalSysPower {\n\tOPAL_SYSPOWER_UPS = 1,\n\tOPAL_SYSPOWER_CHNG = 2,\n\tOPAL_SYSPOWER_FAIL = 4,\n\tOPAL_SYSPOWER_INCL = 8,\n};\n\nenum OpalSysparamPerm {\n\tOPAL_SYSPARAM_READ = 1,\n\tOPAL_SYSPARAM_WRITE = 2,\n\tOPAL_SYSPARAM_RW = 3,\n};\n\nenum OpalThreadStatus {\n\tOPAL_THREAD_INACTIVE = 0,\n\tOPAL_THREAD_STARTED = 1,\n\tOPAL_THREAD_UNAVAILABLE = 2,\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum TG3_FLAGS {\n\tTG3_FLAG_TAGGED_STATUS = 0,\n\tTG3_FLAG_TXD_MBOX_HWBUG = 1,\n\tTG3_FLAG_USE_LINKCHG_REG = 2,\n\tTG3_FLAG_ERROR_PROCESSED = 3,\n\tTG3_FLAG_ENABLE_ASF = 4,\n\tTG3_FLAG_ASPM_WORKAROUND = 5,\n\tTG3_FLAG_POLL_SERDES = 6,\n\tTG3_FLAG_POLL_CPMU_LINK = 7,\n\tTG3_FLAG_MBOX_WRITE_REORDER = 8,\n\tTG3_FLAG_PCIX_TARGET_HWBUG = 9,\n\tTG3_FLAG_WOL_SPEED_100MB = 10,\n\tTG3_FLAG_WOL_ENABLE = 11,\n\tTG3_FLAG_EEPROM_WRITE_PROT = 12,\n\tTG3_FLAG_NVRAM = 13,\n\tTG3_FLAG_NVRAM_BUFFERED = 14,\n\tTG3_FLAG_SUPPORT_MSI = 15,\n\tTG3_FLAG_SUPPORT_MSIX = 16,\n\tTG3_FLAG_USING_MSI = 17,\n\tTG3_FLAG_USING_MSIX = 18,\n\tTG3_FLAG_PCIX_MODE = 19,\n\tTG3_FLAG_PCI_HIGH_SPEED = 20,\n\tTG3_FLAG_PCI_32BIT = 21,\n\tTG3_FLAG_SRAM_USE_CONFIG = 22,\n\tTG3_FLAG_TX_RECOVERY_PENDING = 23,\n\tTG3_FLAG_WOL_CAP = 24,\n\tTG3_FLAG_JUMBO_RING_ENABLE = 25,\n\tTG3_FLAG_PAUSE_AUTONEG = 26,\n\tTG3_FLAG_CPMU_PRESENT = 27,\n\tTG3_FLAG_40BIT_DMA_BUG = 28,\n\tTG3_FLAG_BROKEN_CHECKSUMS = 29,\n\tTG3_FLAG_JUMBO_CAPABLE = 30,\n\tTG3_FLAG_CHIP_RESETTING = 31,\n\tTG3_FLAG_INIT_COMPLETE = 32,\n\tTG3_FLAG_MAX_RXPEND_64 = 33,\n\tTG3_FLAG_PCI_EXPRESS = 34,\n\tTG3_FLAG_ASF_NEW_HANDSHAKE = 35,\n\tTG3_FLAG_HW_AUTONEG = 36,\n\tTG3_FLAG_IS_NIC = 37,\n\tTG3_FLAG_FLASH = 38,\n\tTG3_FLAG_FW_TSO = 39,\n\tTG3_FLAG_HW_TSO_1 = 40,\n\tTG3_FLAG_HW_TSO_2 = 41,\n\tTG3_FLAG_HW_TSO_3 = 42,\n\tTG3_FLAG_TSO_CAPABLE = 43,\n\tTG3_FLAG_TSO_BUG = 44,\n\tTG3_FLAG_ICH_WORKAROUND = 45,\n\tTG3_FLAG_1SHOT_MSI = 46,\n\tTG3_FLAG_NO_FWARE_REPORTED = 47,\n\tTG3_FLAG_NO_NVRAM_ADDR_TRANS = 48,\n\tTG3_FLAG_ENABLE_APE = 49,\n\tTG3_FLAG_PROTECTED_NVRAM = 50,\n\tTG3_FLAG_5701_DMA_BUG = 51,\n\tTG3_FLAG_USE_PHYLIB = 52,\n\tTG3_FLAG_MDIOBUS_INITED = 53,\n\tTG3_FLAG_LRG_PROD_RING_CAP = 54,\n\tTG3_FLAG_RGMII_INBAND_DISABLE = 55,\n\tTG3_FLAG_RGMII_EXT_IBND_RX_EN = 56,\n\tTG3_FLAG_RGMII_EXT_IBND_TX_EN = 57,\n\tTG3_FLAG_CLKREQ_BUG = 58,\n\tTG3_FLAG_NO_NVRAM = 59,\n\tTG3_FLAG_ENABLE_RSS = 60,\n\tTG3_FLAG_ENABLE_TSS = 61,\n\tTG3_FLAG_SHORT_DMA_BUG = 62,\n\tTG3_FLAG_USE_JUMBO_BDFLAG = 63,\n\tTG3_FLAG_L1PLLPD_EN = 64,\n\tTG3_FLAG_APE_HAS_NCSI = 65,\n\tTG3_FLAG_TX_TSTAMP_EN = 66,\n\tTG3_FLAG_4K_FIFO_LIMIT = 67,\n\tTG3_FLAG_5719_5720_RDMA_BUG = 68,\n\tTG3_FLAG_RESET_TASK_PENDING = 69,\n\tTG3_FLAG_PTP_CAPABLE = 70,\n\tTG3_FLAG_5705_PLUS = 71,\n\tTG3_FLAG_IS_5788 = 72,\n\tTG3_FLAG_5750_PLUS = 73,\n\tTG3_FLAG_5780_CLASS = 74,\n\tTG3_FLAG_5755_PLUS = 75,\n\tTG3_FLAG_57765_PLUS = 76,\n\tTG3_FLAG_57765_CLASS = 77,\n\tTG3_FLAG_5717_PLUS = 78,\n\tTG3_FLAG_IS_SSB_CORE = 79,\n\tTG3_FLAG_FLUSH_POSTED_WRITES = 80,\n\tTG3_FLAG_ROBOSWITCH = 81,\n\tTG3_FLAG_ONE_DMA_AT_ONCE = 82,\n\tTG3_FLAG_RGMII_MODE = 83,\n\tTG3_FLAG_NUMBER_OF_FLAGS = 84,\n};\n\nenum TPM_OPS_FLAGS {\n\tTPM_OPS_AUTO_STARTUP = 1,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nenum _record_type {\n\t_START_RECORD = 0,\n\t_COMMIT_RECORD = 1,\n};\n\nenum _slab_flag_bits {\n\t_SLAB_CONSISTENCY_CHECKS = 0,\n\t_SLAB_RED_ZONE = 1,\n\t_SLAB_POISON = 2,\n\t_SLAB_KMALLOC = 3,\n\t_SLAB_HWCACHE_ALIGN = 4,\n\t_SLAB_CACHE_DMA = 5,\n\t_SLAB_CACHE_DMA32 = 6,\n\t_SLAB_STORE_USER = 7,\n\t_SLAB_PANIC = 8,\n\t_SLAB_TYPESAFE_BY_RCU = 9,\n\t_SLAB_TRACE = 10,\n\t_SLAB_NOLEAKTRACE = 11,\n\t_SLAB_NO_MERGE = 12,\n\t_SLAB_ACCOUNT = 13,\n\t_SLAB_NO_USER_FLAGS = 14,\n\t_SLAB_RECLAIM_ACCOUNT = 15,\n\t_SLAB_OBJECT_POISON = 16,\n\t_SLAB_CMPXCHG_DOUBLE = 17,\n\t_SLAB_NO_OBJ_EXT = 18,\n\t_SLAB_OBJ_EXT_IN_OBJ = 19,\n\t_SLAB_FLAGS_LAST_BIT = 20,\n};\n\nenum access_coordinate_class {\n\tACCESS_COORDINATE_LOCAL = 0,\n\tACCESS_COORDINATE_CPU = 1,\n\tACCESS_COORDINATE_MAX = 2,\n};\n\nenum actions {\n\tREGISTER = 0,\n\tDEREGISTER = 1,\n\tCPU_DONT_CARE = 2,\n};\n\nenum add_mode {\n\tADD_TO_HEAD = 0,\n\tADD_TO_TAIL = 1,\n};\n\nenum addr_type_t {\n\tUNICAST_ADDR = 0,\n\tMULTICAST_ADDR = 1,\n\tANYCAST_ADDR = 2,\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum alloc_loc {\n\tALLOC_ERR = 0,\n\tALLOC_BEFORE = 1,\n\tALLOC_MID = 2,\n\tALLOC_AFTER = 3,\n};\n\nenum array_state {\n\tclear = 0,\n\tinactive = 1,\n\tsuspended = 2,\n\treadonly = 3,\n\tread_auto = 4,\n\tclean = 5,\n\tactive = 6,\n\twrite_pending = 7,\n\tactive_idle = 8,\n\tbroken = 9,\n\tbad_word = 10,\n};\n\nenum asn1_class {\n\tASN1_UNIV = 0,\n\tASN1_APPL = 1,\n\tASN1_CONT = 2,\n\tASN1_PRIV = 3,\n};\n\nenum asn1_method {\n\tASN1_PRIM = 0,\n\tASN1_CONS = 1,\n};\n\nenum asn1_opcode {\n\tASN1_OP_MATCH = 0,\n\tASN1_OP_MATCH_OR_SKIP = 1,\n\tASN1_OP_MATCH_ACT = 2,\n\tASN1_OP_MATCH_ACT_OR_SKIP = 3,\n\tASN1_OP_MATCH_JUMP = 4,\n\tASN1_OP_MATCH_JUMP_OR_SKIP = 5,\n\tASN1_OP_MATCH_ANY = 8,\n\tASN1_OP_MATCH_ANY_OR_SKIP = 9,\n\tASN1_OP_MATCH_ANY_ACT = 10,\n\tASN1_OP_MATCH_ANY_ACT_OR_SKIP = 11,\n\tASN1_OP_COND_MATCH_OR_SKIP = 17,\n\tASN1_OP_COND_MATCH_ACT_OR_SKIP = 19,\n\tASN1_OP_COND_MATCH_JUMP_OR_SKIP = 21,\n\tASN1_OP_COND_MATCH_ANY = 24,\n\tASN1_OP_COND_MATCH_ANY_OR_SKIP = 25,\n\tASN1_OP_COND_MATCH_ANY_ACT = 26,\n\tASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 27,\n\tASN1_OP_COND_FAIL = 28,\n\tASN1_OP_COMPLETE = 29,\n\tASN1_OP_ACT = 30,\n\tASN1_OP_MAYBE_ACT = 31,\n\tASN1_OP_END_SEQ = 32,\n\tASN1_OP_END_SET = 33,\n\tASN1_OP_END_SEQ_OF = 34,\n\tASN1_OP_END_SET_OF = 35,\n\tASN1_OP_END_SEQ_ACT = 36,\n\tASN1_OP_END_SET_ACT = 37,\n\tASN1_OP_END_SEQ_OF_ACT = 38,\n\tASN1_OP_END_SET_OF_ACT = 39,\n\tASN1_OP_RETURN = 40,\n\tASN1_OP__NR = 41,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nenum asymmetric_payload_bits {\n\tasym_crypto = 0,\n\tasym_subtype = 1,\n\tasym_key_ids = 2,\n\tasym_auth = 3,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nenum ata_quirks {\n\t__ATA_QUIRK_DIAGNOSTIC = 0,\n\t__ATA_QUIRK_NODMA = 1,\n\t__ATA_QUIRK_NONCQ = 2,\n\t__ATA_QUIRK_BROKEN_HPA = 3,\n\t__ATA_QUIRK_DISABLE = 4,\n\t__ATA_QUIRK_HPA_SIZE = 5,\n\t__ATA_QUIRK_IVB = 6,\n\t__ATA_QUIRK_STUCK_ERR = 7,\n\t__ATA_QUIRK_BRIDGE_OK = 8,\n\t__ATA_QUIRK_ATAPI_MOD16_DMA = 9,\n\t__ATA_QUIRK_FIRMWARE_WARN = 10,\n\t__ATA_QUIRK_1_5_GBPS = 11,\n\t__ATA_QUIRK_NOSETXFER = 12,\n\t__ATA_QUIRK_BROKEN_FPDMA_AA = 13,\n\t__ATA_QUIRK_DUMP_ID = 14,\n\t__ATA_QUIRK_MAX_SEC_LBA48 = 15,\n\t__ATA_QUIRK_ATAPI_DMADIR = 16,\n\t__ATA_QUIRK_NO_NCQ_TRIM = 17,\n\t__ATA_QUIRK_NOLPM = 18,\n\t__ATA_QUIRK_WD_BROKEN_LPM = 19,\n\t__ATA_QUIRK_ZERO_AFTER_TRIM = 20,\n\t__ATA_QUIRK_NO_DMA_LOG = 21,\n\t__ATA_QUIRK_NOTRIM = 22,\n\t__ATA_QUIRK_MAX_SEC = 23,\n\t__ATA_QUIRK_MAX_TRIM_128M = 24,\n\t__ATA_QUIRK_NO_NCQ_ON_ATI = 25,\n\t__ATA_QUIRK_NO_LPM_ON_ATI = 26,\n\t__ATA_QUIRK_NO_ID_DEV_LOG = 27,\n\t__ATA_QUIRK_NO_LOG_DIR = 28,\n\t__ATA_QUIRK_NO_FUA = 29,\n\t__ATA_QUIRK_MAX = 30,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum audit_nfcfgop {\n\tAUDIT_XT_OP_REGISTER = 0,\n\tAUDIT_XT_OP_REPLACE = 1,\n\tAUDIT_XT_OP_UNREGISTER = 2,\n\tAUDIT_NFT_OP_TABLE_REGISTER = 3,\n\tAUDIT_NFT_OP_TABLE_UNREGISTER = 4,\n\tAUDIT_NFT_OP_CHAIN_REGISTER = 5,\n\tAUDIT_NFT_OP_CHAIN_UNREGISTER = 6,\n\tAUDIT_NFT_OP_RULE_REGISTER = 7,\n\tAUDIT_NFT_OP_RULE_UNREGISTER = 8,\n\tAUDIT_NFT_OP_SET_REGISTER = 9,\n\tAUDIT_NFT_OP_SET_UNREGISTER = 10,\n\tAUDIT_NFT_OP_SETELEM_REGISTER = 11,\n\tAUDIT_NFT_OP_SETELEM_UNREGISTER = 12,\n\tAUDIT_NFT_OP_GEN_REGISTER = 13,\n\tAUDIT_NFT_OP_OBJ_REGISTER = 14,\n\tAUDIT_NFT_OP_OBJ_UNREGISTER = 15,\n\tAUDIT_NFT_OP_OBJ_RESET = 16,\n\tAUDIT_NFT_OP_FLOWTABLE_REGISTER = 17,\n\tAUDIT_NFT_OP_FLOWTABLE_UNREGISTER = 18,\n\tAUDIT_NFT_OP_SETELEM_RESET = 19,\n\tAUDIT_NFT_OP_RULE_RESET = 20,\n\tAUDIT_NFT_OP_INVALID = 21,\n};\n\nenum audit_nlgrps {\n\tAUDIT_NLGRP_NONE = 0,\n\tAUDIT_NLGRP_READLOG = 1,\n\t__AUDIT_NLGRP_MAX = 2,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\nenum audit_state {\n\tAUDIT_STATE_DISABLED = 0,\n\tAUDIT_STATE_BUILD = 1,\n\tAUDIT_STATE_RECORD = 2,\n};\n\nenum auditsc_class_t {\n\tAUDITSC_NATIVE = 0,\n\tAUDITSC_COMPAT = 1,\n\tAUDITSC_OPEN = 2,\n\tAUDITSC_OPENAT = 3,\n\tAUDITSC_SOCKETCALL = 4,\n\tAUDITSC_EXECVE = 5,\n\tAUDITSC_OPENAT2 = 6,\n\tAUDITSC_NVALS = 7,\n};\n\nenum base64_variant {\n\tBASE64_STD = 0,\n\tBASE64_URLSAFE = 1,\n\tBASE64_IMAP = 2,\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_MCAST = 5,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_Migrate = 16,\n\tBH_PrivateStart = 17,\n};\n\nenum bio_merge_status {\n\tBIO_MERGE_OK = 0,\n\tBIO_MERGE_NONE = 1,\n\tBIO_MERGE_FAILED = 2,\n};\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_DISK_NOCHECK = 4,\n\tBIP_IP_CHECKSUM = 8,\n\tBIP_COPY_USER = 16,\n\tBIP_CHECK_GUARD = 32,\n\tBIP_CHECK_REFTAG = 64,\n\tBIP_CHECK_APPTAG = 128,\n\tBIP_MEMPOOL = 32768,\n};\n\nenum bitmap_page_attr {\n\tBITMAP_PAGE_DIRTY = 0,\n\tBITMAP_PAGE_PENDING = 1,\n\tBITMAP_PAGE_NEEDWRITE = 2,\n};\n\nenum bitmap_state {\n\tBITMAP_STALE = 1,\n\tBITMAP_WRITE_ERROR = 2,\n\tBITMAP_FIRST_USE = 3,\n\tBITMAP_CLEAN = 4,\n\tBITMAP_DAEMON_BUSY = 5,\n\tBITMAP_HOSTENDIAN = 15,\n};\n\nenum blacklist_hash_type {\n\tBLACKLIST_HASH_X509_TBS = 1,\n\tBLACKLIST_HASH_BINARY = 2,\n};\n\nenum blake2s_iv {\n\tBLAKE2S_IV0 = 1779033703,\n\tBLAKE2S_IV1 = 3144134277,\n\tBLAKE2S_IV2 = 1013904242,\n\tBLAKE2S_IV3 = 2773480762,\n\tBLAKE2S_IV4 = 1359893119,\n\tBLAKE2S_IV5 = 2600822924,\n\tBLAKE2S_IV6 = 528734635,\n\tBLAKE2S_IV7 = 1541459225,\n};\n\nenum blake2s_lengths {\n\tBLAKE2S_BLOCK_SIZE = 64,\n\tBLAKE2S_HASH_SIZE = 32,\n\tBLAKE2S_KEY_SIZE = 32,\n\tBLAKE2S_128_HASH_SIZE = 16,\n\tBLAKE2S_160_HASH_SIZE = 20,\n\tBLAKE2S_224_HASH_SIZE = 28,\n\tBLAKE2S_256_HASH_SIZE = 32,\n};\n\nenum blk_crypto_key_type {\n\tBLK_CRYPTO_KEY_TYPE_RAW = 1,\n\tBLK_CRYPTO_KEY_TYPE_HW_WRAPPED = 2,\n};\n\nenum blk_crypto_mode_num {\n\tBLK_ENCRYPTION_MODE_INVALID = 0,\n\tBLK_ENCRYPTION_MODE_AES_256_XTS = 1,\n\tBLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV = 2,\n\tBLK_ENCRYPTION_MODE_ADIANTUM = 3,\n\tBLK_ENCRYPTION_MODE_SM4_XTS = 4,\n\tBLK_ENCRYPTION_MODE_MAX = 5,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\nenum blk_integrity_checksum {\n\tBLK_INTEGRITY_CSUM_NONE = 0,\n\tBLK_INTEGRITY_CSUM_IP = 1,\n\tBLK_INTEGRITY_CSUM_CRC = 2,\n\tBLK_INTEGRITY_CSUM_CRC64 = 3,\n} __attribute__((mode(byte)));\n\nenum blk_integrity_flags {\n\tBLK_INTEGRITY_NOVERIFY = 1,\n\tBLK_INTEGRITY_NOGENERATE = 2,\n\tBLK_INTEGRITY_DEVICE_CAPABLE = 4,\n\tBLK_INTEGRITY_REF_TAG = 8,\n\tBLK_INTEGRITY_STACKED = 16,\n};\n\nenum blk_unique_id {\n\tBLK_UID_T10 = 1,\n\tBLK_UID_EUI64 = 2,\n\tBLK_UID_NAA = 3,\n};\n\nenum blkg_iostat_type {\n\tBLKG_IOSTAT_READ = 0,\n\tBLKG_IOSTAT_WRITE = 1,\n\tBLKG_IOSTAT_DISCARD = 2,\n\tBLKG_IOSTAT_NR = 3,\n};\n\nenum blkg_rwstat_type {\n\tBLKG_RWSTAT_READ = 0,\n\tBLKG_RWSTAT_WRITE = 1,\n\tBLKG_RWSTAT_SYNC = 2,\n\tBLKG_RWSTAT_ASYNC = 3,\n\tBLKG_RWSTAT_DISCARD = 4,\n\tBLKG_RWSTAT_NR = 5,\n\tBLKG_RWSTAT_TOTAL = 5,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_ZONE_PLUG = 18,\n\t__BLK_TA_ZONE_UNPLUG = 19,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum blktrace_cat {\n\tBLK_TC_READ = 1,\n\tBLK_TC_WRITE = 2,\n\tBLK_TC_FLUSH = 4,\n\tBLK_TC_SYNC = 8,\n\tBLK_TC_SYNCIO = 8,\n\tBLK_TC_QUEUE = 16,\n\tBLK_TC_REQUEUE = 32,\n\tBLK_TC_ISSUE = 64,\n\tBLK_TC_COMPLETE = 128,\n\tBLK_TC_FS = 256,\n\tBLK_TC_PC = 512,\n\tBLK_TC_NOTIFY = 1024,\n\tBLK_TC_AHEAD = 2048,\n\tBLK_TC_META = 4096,\n\tBLK_TC_DISCARD = 8192,\n\tBLK_TC_DRV_DATA = 16384,\n\tBLK_TC_FUA = 32768,\n\tBLK_TC_END_V1 = 32768,\n\tBLK_TC_ZONE_APPEND = 65536,\n\tBLK_TC_ZONE_RESET = 131072,\n\tBLK_TC_ZONE_RESET_ALL = 262144,\n\tBLK_TC_ZONE_FINISH = 524288,\n\tBLK_TC_ZONE_OPEN = 1048576,\n\tBLK_TC_ZONE_CLOSE = 2097152,\n\tBLK_TC_WRITE_ZEROES = 4194304,\n\tBLK_TC_END_V2 = 4194304,\n};\n\nenum blktrace_notify {\n\t__BLK_TN_PROCESS = 0,\n\t__BLK_TN_TIMESTAMP = 1,\n\t__BLK_TN_MESSAGE = 2,\n\t__BLK_TN_CGROUP = 256,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_43bit_dma = 1,\n\tboard_ahci_ign_iferr = 2,\n\tboard_ahci_no_debounce_delay = 3,\n\tboard_ahci_no_msi = 4,\n\tboard_ahci_pcs_quirk = 5,\n\tboard_ahci_pcs_quirk_no_devslp = 6,\n\tboard_ahci_pcs_quirk_no_sntf = 7,\n\tboard_ahci_yes_fbs = 8,\n\tboard_ahci_yes_fbs_atapi_dma = 9,\n\tboard_ahci_al = 10,\n\tboard_ahci_avn = 11,\n\tboard_ahci_mcp65 = 12,\n\tboard_ahci_mcp77 = 13,\n\tboard_ahci_mcp89 = 14,\n\tboard_ahci_mv = 15,\n\tboard_ahci_sb600 = 16,\n\tboard_ahci_sb700 = 17,\n\tboard_ahci_vt8251 = 18,\n\tboard_ahci_mcp_linux = 12,\n\tboard_ahci_mcp67 = 12,\n\tboard_ahci_mcp73 = 12,\n\tboard_ahci_mcp79 = 13,\n};\n\nenum bootmem_type {\n\tMEMORY_HOTPLUG_MIN_BOOTMEM_TYPE = 1,\n\tSECTION_INFO = 1,\n\tMIX_SECTION_INFO = 2,\n\tNODE_INFO = 3,\n\tMEMORY_HOTPLUG_MAX_BOOTMEM_TYPE = 3,\n};\n\nenum bp_type_idx {\n\tTYPE_INST = 0,\n\tTYPE_DATA = 1,\n\tTYPE_MAX = 2,\n};\n\nenum bpf_access_src {\n\tACCESS_DIRECT = 1,\n\tACCESS_HELPER = 2,\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_addr_space_cast {\n\tBPF_ADDR_SPACE_CAST = 1,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_MEM = 4,\n\tARG_PTR_TO_ARENA = 5,\n\tARG_CONST_SIZE = 6,\n\tARG_CONST_SIZE_OR_ZERO = 7,\n\tARG_PTR_TO_CTX = 8,\n\tARG_ANYTHING = 9,\n\tARG_PTR_TO_SPIN_LOCK = 10,\n\tARG_PTR_TO_SOCK_COMMON = 11,\n\tARG_PTR_TO_SOCKET = 12,\n\tARG_PTR_TO_BTF_ID = 13,\n\tARG_PTR_TO_RINGBUF_MEM = 14,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 15,\n\tARG_PTR_TO_BTF_ID_SOCK_COMMON = 16,\n\tARG_PTR_TO_PERCPU_BTF_ID = 17,\n\tARG_PTR_TO_FUNC = 18,\n\tARG_PTR_TO_STACK = 19,\n\tARG_PTR_TO_CONST_STR = 20,\n\tARG_PTR_TO_TIMER = 21,\n\tARG_KPTR_XCHG_DEST = 22,\n\tARG_PTR_TO_DYNPTR = 23,\n\t__BPF_ARG_TYPE_MAX = 24,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 259,\n\tARG_PTR_TO_MEM_OR_NULL = 260,\n\tARG_PTR_TO_CTX_OR_NULL = 264,\n\tARG_PTR_TO_SOCKET_OR_NULL = 268,\n\tARG_PTR_TO_STACK_OR_NULL = 275,\n\tARG_PTR_TO_BTF_ID_OR_NULL = 269,\n\tARG_PTR_TO_UNINIT_MEM = 67141636,\n\tARG_PTR_TO_FIXED_SIZE_MEM = 262148,\n\t__BPF_ARG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_async_op {\n\tBPF_ASYNC_START = 0,\n\tBPF_ASYNC_CANCEL = 1,\n};\n\nenum bpf_async_type {\n\tBPF_ASYNC_TYPE_TIMER = 0,\n\tBPF_ASYNC_TYPE_WQ = 1,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\tBPF_CGROUP_INET_SOCK_RELEASE = 34,\n\tBPF_XDP_CPUMAP = 35,\n\tBPF_SK_LOOKUP = 36,\n\tBPF_XDP = 37,\n\tBPF_SK_SKB_VERDICT = 38,\n\tBPF_SK_REUSEPORT_SELECT = 39,\n\tBPF_SK_REUSEPORT_SELECT_OR_MIGRATE = 40,\n\tBPF_PERF_EVENT = 41,\n\tBPF_TRACE_KPROBE_MULTI = 42,\n\tBPF_LSM_CGROUP = 43,\n\tBPF_STRUCT_OPS = 44,\n\tBPF_NETFILTER = 45,\n\tBPF_TCX_INGRESS = 46,\n\tBPF_TCX_EGRESS = 47,\n\tBPF_TRACE_UPROBE_MULTI = 48,\n\tBPF_CGROUP_UNIX_CONNECT = 49,\n\tBPF_CGROUP_UNIX_SENDMSG = 50,\n\tBPF_CGROUP_UNIX_RECVMSG = 51,\n\tBPF_CGROUP_UNIX_GETPEERNAME = 52,\n\tBPF_CGROUP_UNIX_GETSOCKNAME = 53,\n\tBPF_NETKIT_PRIMARY = 54,\n\tBPF_NETKIT_PEER = 55,\n\tBPF_TRACE_KPROBE_SESSION = 56,\n\tBPF_TRACE_UPROBE_SESSION = 57,\n\tBPF_TRACE_FSESSION = 58,\n\t__MAX_BPF_ATTACH_TYPE = 59,\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nenum bpf_cgroup_iter_order {\n\tBPF_CGROUP_ITER_ORDER_UNSPEC = 0,\n\tBPF_CGROUP_ITER_SELF_ONLY = 1,\n\tBPF_CGROUP_ITER_DESCENDANTS_PRE = 2,\n\tBPF_CGROUP_ITER_DESCENDANTS_POST = 3,\n\tBPF_CGROUP_ITER_ANCESTORS_UP = 4,\n\tBPF_CGROUP_ITER_CHILDREN = 5,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum bpf_check_mtu_flags {\n\tBPF_MTU_CHK_SEGS = 1,\n};\n\nenum bpf_check_mtu_ret {\n\tBPF_MTU_CHK_RET_SUCCESS = 0,\n\tBPF_MTU_CHK_RET_FRAG_NEEDED = 1,\n\tBPF_MTU_CHK_RET_SEGS_TOOBIG = 2,\n};\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n\tBPF_LINK_DETACH = 34,\n\tBPF_PROG_BIND_MAP = 35,\n\tBPF_TOKEN_CREATE = 36,\n\tBPF_PROG_STREAM_READ_BY_FD = 37,\n\tBPF_PROG_ASSOC_STRUCT_OPS = 38,\n\t__MAX_BPF_CMD = 39,\n};\n\nenum bpf_cond_pseudo_jmp {\n\tBPF_MAY_GOTO = 0,\n};\n\nenum bpf_core_relo_kind {\n\tBPF_CORE_FIELD_BYTE_OFFSET = 0,\n\tBPF_CORE_FIELD_BYTE_SIZE = 1,\n\tBPF_CORE_FIELD_EXISTS = 2,\n\tBPF_CORE_FIELD_SIGNED = 3,\n\tBPF_CORE_FIELD_LSHIFT_U64 = 4,\n\tBPF_CORE_FIELD_RSHIFT_U64 = 5,\n\tBPF_CORE_TYPE_ID_LOCAL = 6,\n\tBPF_CORE_TYPE_ID_TARGET = 7,\n\tBPF_CORE_TYPE_EXISTS = 8,\n\tBPF_CORE_TYPE_SIZE = 9,\n\tBPF_CORE_ENUMVAL_EXISTS = 10,\n\tBPF_CORE_ENUMVAL_VALUE = 11,\n\tBPF_CORE_TYPE_MATCHES = 12,\n};\n\nenum bpf_dynptr_type {\n\tBPF_DYNPTR_TYPE_INVALID = 0,\n\tBPF_DYNPTR_TYPE_LOCAL = 1,\n\tBPF_DYNPTR_TYPE_RINGBUF = 2,\n\tBPF_DYNPTR_TYPE_SKB = 3,\n\tBPF_DYNPTR_TYPE_XDP = 4,\n\tBPF_DYNPTR_TYPE_SKB_META = 5,\n\tBPF_DYNPTR_TYPE_FILE = 6,\n};\n\nenum bpf_features {\n\tBPF_FEAT_RDONLY_CAST_TO_VOID = 0,\n\tBPF_FEAT_STREAMS = 1,\n\t__MAX_BPF_FEAT = 2,\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\tBPF_FUNC_skc_to_tcp6_sock = 136,\n\tBPF_FUNC_skc_to_tcp_sock = 137,\n\tBPF_FUNC_skc_to_tcp_timewait_sock = 138,\n\tBPF_FUNC_skc_to_tcp_request_sock = 139,\n\tBPF_FUNC_skc_to_udp6_sock = 140,\n\tBPF_FUNC_get_task_stack = 141,\n\tBPF_FUNC_load_hdr_opt = 142,\n\tBPF_FUNC_store_hdr_opt = 143,\n\tBPF_FUNC_reserve_hdr_opt = 144,\n\tBPF_FUNC_inode_storage_get = 145,\n\tBPF_FUNC_inode_storage_delete = 146,\n\tBPF_FUNC_d_path = 147,\n\tBPF_FUNC_copy_from_user = 148,\n\tBPF_FUNC_snprintf_btf = 149,\n\tBPF_FUNC_seq_printf_btf = 150,\n\tBPF_FUNC_skb_cgroup_classid = 151,\n\tBPF_FUNC_redirect_neigh = 152,\n\tBPF_FUNC_per_cpu_ptr = 153,\n\tBPF_FUNC_this_cpu_ptr = 154,\n\tBPF_FUNC_redirect_peer = 155,\n\tBPF_FUNC_task_storage_get = 156,\n\tBPF_FUNC_task_storage_delete = 157,\n\tBPF_FUNC_get_current_task_btf = 158,\n\tBPF_FUNC_bprm_opts_set = 159,\n\tBPF_FUNC_ktime_get_coarse_ns = 160,\n\tBPF_FUNC_ima_inode_hash = 161,\n\tBPF_FUNC_sock_from_file = 162,\n\tBPF_FUNC_check_mtu = 163,\n\tBPF_FUNC_for_each_map_elem = 164,\n\tBPF_FUNC_snprintf = 165,\n\tBPF_FUNC_sys_bpf = 166,\n\tBPF_FUNC_btf_find_by_name_kind = 167,\n\tBPF_FUNC_sys_close = 168,\n\tBPF_FUNC_timer_init = 169,\n\tBPF_FUNC_timer_set_callback = 170,\n\tBPF_FUNC_timer_start = 171,\n\tBPF_FUNC_timer_cancel = 172,\n\tBPF_FUNC_get_func_ip = 173,\n\tBPF_FUNC_get_attach_cookie = 174,\n\tBPF_FUNC_task_pt_regs = 175,\n\tBPF_FUNC_get_branch_snapshot = 176,\n\tBPF_FUNC_trace_vprintk = 177,\n\tBPF_FUNC_skc_to_unix_sock = 178,\n\tBPF_FUNC_kallsyms_lookup_name = 179,\n\tBPF_FUNC_find_vma = 180,\n\tBPF_FUNC_loop = 181,\n\tBPF_FUNC_strncmp = 182,\n\tBPF_FUNC_get_func_arg = 183,\n\tBPF_FUNC_get_func_ret = 184,\n\tBPF_FUNC_get_func_arg_cnt = 185,\n\tBPF_FUNC_get_retval = 186,\n\tBPF_FUNC_set_retval = 187,\n\tBPF_FUNC_xdp_get_buff_len = 188,\n\tBPF_FUNC_xdp_load_bytes = 189,\n\tBPF_FUNC_xdp_store_bytes = 190,\n\tBPF_FUNC_copy_from_user_task = 191,\n\tBPF_FUNC_skb_set_tstamp = 192,\n\tBPF_FUNC_ima_file_hash = 193,\n\tBPF_FUNC_kptr_xchg = 194,\n\tBPF_FUNC_map_lookup_percpu_elem = 195,\n\tBPF_FUNC_skc_to_mptcp_sock = 196,\n\tBPF_FUNC_dynptr_from_mem = 197,\n\tBPF_FUNC_ringbuf_reserve_dynptr = 198,\n\tBPF_FUNC_ringbuf_submit_dynptr = 199,\n\tBPF_FUNC_ringbuf_discard_dynptr = 200,\n\tBPF_FUNC_dynptr_read = 201,\n\tBPF_FUNC_dynptr_write = 202,\n\tBPF_FUNC_dynptr_data = 203,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv4 = 204,\n\tBPF_FUNC_tcp_raw_gen_syncookie_ipv6 = 205,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv4 = 206,\n\tBPF_FUNC_tcp_raw_check_syncookie_ipv6 = 207,\n\tBPF_FUNC_ktime_get_tai_ns = 208,\n\tBPF_FUNC_user_ringbuf_drain = 209,\n\tBPF_FUNC_cgrp_storage_get = 210,\n\tBPF_FUNC_cgrp_storage_delete = 211,\n\t__BPF_FUNC_MAX_ID = 212,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_iter_feature {\n\tBPF_ITER_RESCHED = 1,\n};\n\nenum bpf_iter_state {\n\tBPF_ITER_STATE_INVALID = 0,\n\tBPF_ITER_STATE_ACTIVE = 1,\n\tBPF_ITER_STATE_DRAINED = 2,\n};\n\nenum bpf_iter_task_type {\n\tBPF_TASK_ITER_ALL = 0,\n\tBPF_TASK_ITER_TID = 1,\n\tBPF_TASK_ITER_TGID = 2,\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nenum bpf_kfunc_flags {\n\tBPF_F_PAD_ZEROS = 1,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tBPF_LINK_TYPE_XDP = 6,\n\tBPF_LINK_TYPE_PERF_EVENT = 7,\n\tBPF_LINK_TYPE_KPROBE_MULTI = 8,\n\tBPF_LINK_TYPE_STRUCT_OPS = 9,\n\tBPF_LINK_TYPE_NETFILTER = 10,\n\tBPF_LINK_TYPE_TCX = 11,\n\tBPF_LINK_TYPE_UPROBE_MULTI = 12,\n\tBPF_LINK_TYPE_NETKIT = 13,\n\tBPF_LINK_TYPE_SOCKMAP = 14,\n\t__MAX_BPF_LINK_TYPE = 15,\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE_DEPRECATED = 19,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE_DEPRECATED = 21,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n\tBPF_MAP_TYPE_INODE_STORAGE = 28,\n\tBPF_MAP_TYPE_TASK_STORAGE = 29,\n\tBPF_MAP_TYPE_BLOOM_FILTER = 30,\n\tBPF_MAP_TYPE_USER_RINGBUF = 31,\n\tBPF_MAP_TYPE_CGRP_STORAGE = 32,\n\tBPF_MAP_TYPE_ARENA = 33,\n\tBPF_MAP_TYPE_INSN_ARRAY = 34,\n\t__MAX_BPF_MAP_TYPE = 35,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tBPF_OFFLOAD_MAP_ALLOC = 2,\n\tBPF_OFFLOAD_MAP_FREE = 3,\n\tXDP_SETUP_XSK_POOL = 4,\n};\n\nenum bpf_perf_event_type {\n\tBPF_PERF_EVENT_UNSPEC = 0,\n\tBPF_PERF_EVENT_UPROBE = 1,\n\tBPF_PERF_EVENT_URETPROBE = 2,\n\tBPF_PERF_EVENT_KPROBE = 3,\n\tBPF_PERF_EVENT_KRETPROBE = 4,\n\tBPF_PERF_EVENT_TRACEPOINT = 5,\n\tBPF_PERF_EVENT_EVENT = 6,\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n\tBPF_PROG_TYPE_SK_LOOKUP = 30,\n\tBPF_PROG_TYPE_SYSCALL = 31,\n\tBPF_PROG_TYPE_NETFILTER = 32,\n\t__MAX_BPF_PROG_TYPE = 33,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_KEY = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCK_COMMON = 12,\n\tPTR_TO_TCP_SOCK = 13,\n\tPTR_TO_TP_BUFFER = 14,\n\tPTR_TO_XDP_SOCK = 15,\n\tPTR_TO_BTF_ID = 16,\n\tPTR_TO_MEM = 17,\n\tPTR_TO_ARENA = 18,\n\tPTR_TO_BUF = 19,\n\tPTR_TO_FUNC = 20,\n\tPTR_TO_INSN = 21,\n\tCONST_PTR_TO_DYNPTR = 22,\n\t__BPF_REG_TYPE_MAX = 23,\n\tPTR_TO_MAP_VALUE_OR_NULL = 260,\n\tPTR_TO_SOCKET_OR_NULL = 267,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 268,\n\tPTR_TO_TCP_SOCK_OR_NULL = 269,\n\tPTR_TO_BTF_ID_OR_NULL = 272,\n\t__BPF_REG_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n\tBPF_FLOW_DISSECTOR_CONTINUE = 129,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_SOCKET = 3,\n\tRET_PTR_TO_TCP_SOCK = 4,\n\tRET_PTR_TO_SOCK_COMMON = 5,\n\tRET_PTR_TO_MEM = 6,\n\tRET_PTR_TO_MEM_OR_BTF_ID = 7,\n\tRET_PTR_TO_BTF_ID = 8,\n\t__BPF_RET_TYPE_MAX = 9,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 258,\n\tRET_PTR_TO_SOCKET_OR_NULL = 259,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 260,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 261,\n\tRET_PTR_TO_RINGBUF_MEM_OR_NULL = 1286,\n\tRET_PTR_TO_DYNPTR_MEM_OR_NULL = 262,\n\tRET_PTR_TO_BTF_ID_OR_NULL = 264,\n\tRET_PTR_TO_BTF_ID_TRUSTED = 1048584,\n\t__BPF_RET_TYPE_LIMIT = 536870911,\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n\tSTACK_DYNPTR = 4,\n\tSTACK_ITER = 5,\n\tSTACK_IRQ_FLAG = 6,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nenum bpf_stream_id {\n\tBPF_STDOUT = 1,\n\tBPF_STDERR = 2,\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n\tBPF_STRUCT_OPS_STATE_READY = 3,\n};\n\nenum bpf_struct_walk_result {\n\tWALK_SCALAR = 0,\n\tWALK_PTR = 1,\n\tWALK_PTR_UNTRUSTED = 2,\n\tWALK_STRUCT = 3,\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nenum bpf_task_vma_iter_find_op {\n\ttask_vma_iter_first_vma = 0,\n\ttask_vma_iter_next_vma = 1,\n\ttask_vma_iter_find_vma = 2,\n};\n\nenum bpf_task_work_state {\n\tBPF_TW_STANDBY = 0,\n\tBPF_TW_PENDING = 1,\n\tBPF_TW_SCHEDULING = 2,\n\tBPF_TW_SCHEDULED = 3,\n\tBPF_TW_RUNNING = 4,\n\tBPF_TW_FREED = 5,\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_NOP = 0,\n\tBPF_MOD_CALL = 1,\n\tBPF_MOD_JUMP = 2,\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n\tBPF_TRAMP_FSESSION = 5,\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nenum bpf_type_flag {\n\tPTR_MAYBE_NULL = 256,\n\tMEM_RDONLY = 512,\n\tMEM_RINGBUF = 1024,\n\tMEM_USER = 2048,\n\tMEM_PERCPU = 4096,\n\tOBJ_RELEASE = 8192,\n\tPTR_UNTRUSTED = 16384,\n\tMEM_UNINIT = 32768,\n\tDYNPTR_TYPE_LOCAL = 65536,\n\tDYNPTR_TYPE_RINGBUF = 131072,\n\tMEM_FIXED_SIZE = 262144,\n\tMEM_ALLOC = 524288,\n\tPTR_TRUSTED = 1048576,\n\tMEM_RCU = 2097152,\n\tNON_OWN_REF = 4194304,\n\tDYNPTR_TYPE_SKB = 8388608,\n\tDYNPTR_TYPE_XDP = 16777216,\n\tMEM_ALIGNED = 33554432,\n\tMEM_WRITE = 67108864,\n\tDYNPTR_TYPE_SKB_META = 134217728,\n\tDYNPTR_TYPE_FILE = 268435456,\n\t__BPF_TYPE_FLAG_MAX = 268435457,\n\t__BPF_TYPE_LAST_FLAG = 268435456,\n};\n\nenum bpf_xdp_mode {\n\tXDP_MODE_SKB = 0,\n\tXDP_MODE_DRV = 1,\n\tXDP_MODE_HW = 2,\n\t__MAX_XDP_MODE = 3,\n};\n\nenum branch_cache_flush_type {\n\tBRANCH_CACHE_FLUSH_NONE = 1,\n\tBRANCH_CACHE_FLUSH_SW = 2,\n\tBRANCH_CACHE_FLUSH_HW = 4,\n};\n\nenum btf_arg_tag {\n\tARG_TAG_CTX = 1,\n\tARG_TAG_NONNULL = 2,\n\tARG_TAG_TRUSTED = 4,\n\tARG_TAG_UNTRUSTED = 8,\n\tARG_TAG_NULLABLE = 16,\n\tARG_TAG_ARENA = 32,\n};\n\nenum btf_field_iter_kind {\n\tBTF_FIELD_ITER_IDS = 0,\n\tBTF_FIELD_ITER_STRS = 1,\n};\n\nenum btf_field_type {\n\tBPF_SPIN_LOCK = 1,\n\tBPF_TIMER = 2,\n\tBPF_KPTR_UNREF = 4,\n\tBPF_KPTR_REF = 8,\n\tBPF_KPTR_PERCPU = 16,\n\tBPF_KPTR = 28,\n\tBPF_LIST_HEAD = 32,\n\tBPF_LIST_NODE = 64,\n\tBPF_RB_ROOT = 128,\n\tBPF_RB_NODE = 256,\n\tBPF_GRAPH_NODE = 320,\n\tBPF_GRAPH_ROOT = 160,\n\tBPF_REFCOUNT = 512,\n\tBPF_WORKQUEUE = 1024,\n\tBPF_UPTR = 2048,\n\tBPF_RES_SPIN_LOCK = 4096,\n\tBPF_TASK_WORK = 8192,\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nenum btf_kfunc_hook {\n\tBTF_KFUNC_HOOK_COMMON = 0,\n\tBTF_KFUNC_HOOK_XDP = 1,\n\tBTF_KFUNC_HOOK_TC = 2,\n\tBTF_KFUNC_HOOK_STRUCT_OPS = 3,\n\tBTF_KFUNC_HOOK_TRACING = 4,\n\tBTF_KFUNC_HOOK_SYSCALL = 5,\n\tBTF_KFUNC_HOOK_FMODRET = 6,\n\tBTF_KFUNC_HOOK_CGROUP = 7,\n\tBTF_KFUNC_HOOK_SCHED_ACT = 8,\n\tBTF_KFUNC_HOOK_SK_SKB = 9,\n\tBTF_KFUNC_HOOK_SOCKET_FILTER = 10,\n\tBTF_KFUNC_HOOK_LWT = 11,\n\tBTF_KFUNC_HOOK_NETFILTER = 12,\n\tBTF_KFUNC_HOOK_KPROBE = 13,\n\tBTF_KFUNC_HOOK_MAX = 14,\n};\n\nenum btt_init_state {\n\tINIT_UNCHECKED = 0,\n\tINIT_NOTFOUND = 1,\n\tINIT_READY = 2,\n};\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum bus_notifier_event {\n\tBUS_NOTIFY_ADD_DEVICE = 0,\n\tBUS_NOTIFY_DEL_DEVICE = 1,\n\tBUS_NOTIFY_REMOVED_DEVICE = 2,\n\tBUS_NOTIFY_BIND_DRIVER = 3,\n\tBUS_NOTIFY_BOUND_DRIVER = 4,\n\tBUS_NOTIFY_UNBIND_DRIVER = 5,\n\tBUS_NOTIFY_UNBOUND_DRIVER = 6,\n\tBUS_NOTIFY_DRIVER_NOT_BOUND = 7,\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nenum cb_command {\n\tcb_nop = 0,\n\tcb_iaaddr = 1,\n\tcb_config = 2,\n\tcb_multi = 3,\n\tcb_tx = 4,\n\tcb_ucode = 5,\n\tcb_dump = 6,\n\tcb_tx_sf = 8,\n\tcb_tx_nc = 16,\n\tcb_cid = 7936,\n\tcb_i = 8192,\n\tcb_s = 16384,\n\tcb_el = 32768,\n};\n\nenum cb_status {\n\tcb_complete = 32768,\n\tcb_ok = 8192,\n};\n\nenum cc_attr {\n\tCC_ATTR_MEM_ENCRYPT = 0,\n\tCC_ATTR_HOST_MEM_ENCRYPT = 1,\n\tCC_ATTR_GUEST_MEM_ENCRYPT = 2,\n\tCC_ATTR_GUEST_STATE_ENCRYPT = 3,\n\tCC_ATTR_GUEST_UNROLL_STRING_IO = 4,\n\tCC_ATTR_GUEST_SEV_SNP = 5,\n\tCC_ATTR_GUEST_SNP_SECURE_TSC = 6,\n\tCC_ATTR_HOST_SEV_SNP = 7,\n\tCC_ATTR_SNP_SECURE_AVIC = 8,\n};\n\nenum cdrom_print_option {\n\tCTL_NAME = 0,\n\tCTL_SPEED = 1,\n\tCTL_SLOTS = 2,\n\tCTL_CAPABILITY = 3,\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n\tOpt_favordynmods = 8,\n\tOpt_nofavordynmods = 9,\n};\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_favordynmods___2 = 1,\n\tOpt_memory_localevents = 2,\n\tOpt_memory_recursiveprot = 3,\n\tOpt_memory_hugetlb_accounting = 4,\n\tOpt_pids_localevents = 5,\n\tnr__cgroup2_params = 6,\n};\n\nenum cgroup_attach_lock_mode {\n\tCGRP_ATTACH_LOCK_GLOBAL = 0,\n\tCGRP_ATTACH_LOCK_NONE = 1,\n\tCGRP_ATTACH_LOCK_PER_THREADGROUP = 2,\n};\n\nenum cgroup_bpf_attach_type {\n\tCGROUP_BPF_ATTACH_TYPE_INVALID = -1,\n\tCGROUP_INET_INGRESS = 0,\n\tCGROUP_INET_EGRESS = 1,\n\tCGROUP_INET_SOCK_CREATE = 2,\n\tCGROUP_SOCK_OPS = 3,\n\tCGROUP_DEVICE = 4,\n\tCGROUP_INET4_BIND = 5,\n\tCGROUP_INET6_BIND = 6,\n\tCGROUP_INET4_CONNECT = 7,\n\tCGROUP_INET6_CONNECT = 8,\n\tCGROUP_UNIX_CONNECT = 9,\n\tCGROUP_INET4_POST_BIND = 10,\n\tCGROUP_INET6_POST_BIND = 11,\n\tCGROUP_UDP4_SENDMSG = 12,\n\tCGROUP_UDP6_SENDMSG = 13,\n\tCGROUP_UNIX_SENDMSG = 14,\n\tCGROUP_SYSCTL = 15,\n\tCGROUP_UDP4_RECVMSG = 16,\n\tCGROUP_UDP6_RECVMSG = 17,\n\tCGROUP_UNIX_RECVMSG = 18,\n\tCGROUP_GETSOCKOPT = 19,\n\tCGROUP_SETSOCKOPT = 20,\n\tCGROUP_INET4_GETPEERNAME = 21,\n\tCGROUP_INET6_GETPEERNAME = 22,\n\tCGROUP_UNIX_GETPEERNAME = 23,\n\tCGROUP_INET4_GETSOCKNAME = 24,\n\tCGROUP_INET6_GETSOCKNAME = 25,\n\tCGROUP_UNIX_GETSOCKNAME = 26,\n\tCGROUP_INET_SOCK_RELEASE = 27,\n\tCGROUP_LSM_START = 28,\n\tCGROUP_LSM_END = 37,\n\tMAX_CGROUP_BPF_ATTACH_TYPE = 38,\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nenum cgroup_lifetime_events {\n\tCGROUP_LIFETIME_ONLINE = 0,\n\tCGROUP_LIFETIME_OFFLINE = 1,\n};\n\nenum cgroup_opt_features {\n\tOPT_FEATURE_PRESSURE = 0,\n\tOPT_FEATURE_COUNT = 1,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tio_cgrp_id = 3,\n\tmemory_cgrp_id = 4,\n\tdevices_cgrp_id = 5,\n\tfreezer_cgrp_id = 6,\n\tperf_event_cgrp_id = 7,\n\thugetlb_cgrp_id = 8,\n\tpids_cgrp_id = 9,\n\tmisc_cgrp_id = 10,\n\tCGROUP_SUBSYS_COUNT = 11,\n};\n\nenum chacha_constants {\n\tCHACHA_CONSTANT_EXPA = 1634760805,\n\tCHACHA_CONSTANT_ND_3 = 857760878,\n\tCHACHA_CONSTANT_2_BY = 2036477234,\n\tCHACHA_CONSTANT_TE_K = 1797285236,\n};\n\nenum chip_type {\n\tchip_504x = 0,\n\tchip_508x = 1,\n\tchip_5080 = 2,\n\tchip_604x = 3,\n\tchip_608x = 4,\n\tchip_6042 = 5,\n\tchip_7042 = 6,\n\tchip_soc = 7,\n};\n\nenum class_stat_type {\n\tZS_OBJS_ALLOCATED = 12,\n\tZS_OBJS_INUSE = 13,\n\tNR_CLASS_STAT_TYPES = 14,\n};\n\nenum cleanup_prefix_rt_t {\n\tCLEANUP_PREFIX_RT_NOP = 0,\n\tCLEANUP_PREFIX_RT_DEL = 1,\n\tCLEANUP_PREFIX_RT_EXPIRE = 2,\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nenum clocksource_ids {\n\tCSID_GENERIC = 0,\n\tCSID_ARM_ARCH_COUNTER = 1,\n\tCSID_S390_TOD = 2,\n\tCSID_X86_TSC_EARLY = 3,\n\tCSID_X86_TSC = 4,\n\tCSID_X86_KVM_CLK = 5,\n\tCSID_X86_ART = 6,\n\tCSID_MAX = 7,\n};\n\nenum cma_flags {\n\tCMA_RESERVE_PAGES_ON_ERROR = 0,\n\tCMA_ZONES_VALID = 1,\n\tCMA_ZONES_INVALID = 2,\n\tCMA_ACTIVATED = 3,\n};\n\nenum cmis_cdb_fw_write_mechanism {\n\tCMIS_CDB_FW_WRITE_MECHANISM_NONE = 0,\n\tCMIS_CDB_FW_WRITE_MECHANISM_LPL = 1,\n\tCMIS_CDB_FW_WRITE_MECHANISM_EPL = 16,\n\tCMIS_CDB_FW_WRITE_MECHANISM_BOTH = 17,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nenum cons_flags {\n\tCON_PRINTBUFFER = 1,\n\tCON_CONSDEV = 2,\n\tCON_ENABLED = 4,\n\tCON_BOOT = 8,\n\tCON_ANYTIME = 16,\n\tCON_BRL = 32,\n\tCON_EXTENDED = 64,\n\tCON_SUSPENDED = 128,\n\tCON_NBCON = 256,\n\tCON_NBCON_ATOMIC_UNSAFE = 512,\n};\n\nenum console_type {\n\tCONS_BASIC = 1,\n\tCONS_EXTENDED = 2,\n};\n\nenum coredump_mark {\n\tCOREDUMP_MARK_REQACK = 0,\n\tCOREDUMP_MARK_MINSIZE = 1,\n\tCOREDUMP_MARK_MAXSIZE = 2,\n\tCOREDUMP_MARK_UNSUPPORTED = 3,\n\tCOREDUMP_MARK_CONFLICTING = 4,\n\t__COREDUMP_MARK_MAX = 2147483648,\n};\n\nenum coredump_type_t {\n\tCOREDUMP_FILE = 1,\n\tCOREDUMP_PIPE = 2,\n\tCOREDUMP_SOCK = 3,\n\tCOREDUMP_SOCK_REQ = 4,\n};\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nenum cpu_attack_vectors {\n\tCPU_MITIGATE_USER_KERNEL = 0,\n\tCPU_MITIGATE_USER_USER = 1,\n\tCPU_MITIGATE_GUEST_HOST = 2,\n\tCPU_MITIGATE_GUEST_GUEST = 3,\n\tNR_CPU_ATTACK_VECTORS = 4,\n};\n\nenum cpu_idle_type {\n\t__CPU_NOT_IDLE = 0,\n\tCPU_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tNR_STATS = 10,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = -1,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_X86_PREPARE = 2,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 3,\n\tCPUHP_PERF_POWER = 4,\n\tCPUHP_PERF_SUPERH = 5,\n\tCPUHP_X86_HPET_DEAD = 6,\n\tCPUHP_X86_MCE_DEAD = 7,\n\tCPUHP_VIRT_NET_DEAD = 8,\n\tCPUHP_IBMVNIC_DEAD = 9,\n\tCPUHP_SLUB_DEAD = 10,\n\tCPUHP_DEBUG_OBJ_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_BIO_DEAD = 21,\n\tCPUHP_ACPI_CPUDRV_DEAD = 22,\n\tCPUHP_S390_PFAULT_DEAD = 23,\n\tCPUHP_BLK_MQ_DEAD = 24,\n\tCPUHP_FS_BUFF_DEAD = 25,\n\tCPUHP_PRINTK_DEAD = 26,\n\tCPUHP_MM_MEMCQ_DEAD = 27,\n\tCPUHP_PERCPU_CNT_DEAD = 28,\n\tCPUHP_RADIX_DEAD = 29,\n\tCPUHP_PAGE_ALLOC = 30,\n\tCPUHP_NET_DEV_DEAD = 31,\n\tCPUHP_IOMMU_IOVA_DEAD = 32,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 33,\n\tCPUHP_PADATA_DEAD = 34,\n\tCPUHP_AP_DTPM_CPU_DEAD = 35,\n\tCPUHP_RANDOM_PREPARE = 36,\n\tCPUHP_WORKQUEUE_PREP = 37,\n\tCPUHP_POWER_NUMA_PREPARE = 38,\n\tCPUHP_HRTIMERS_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_MD_RAID5_PREPARE = 43,\n\tCPUHP_RCUTREE_PREP = 44,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 45,\n\tCPUHP_POWERPC_PMAC_PREPARE = 46,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 47,\n\tCPUHP_XEN_PREPARE = 48,\n\tCPUHP_XEN_EVTCHN_PREPARE = 49,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 50,\n\tCPUHP_SH_SH3X_PREPARE = 51,\n\tCPUHP_TOPOLOGY_PREPARE = 52,\n\tCPUHP_NET_IUCV_PREPARE = 53,\n\tCPUHP_ARM_BL_PREPARE = 54,\n\tCPUHP_TRACE_RB_PREPARE = 55,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 56,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 57,\n\tCPUHP_ZCOMP_PREPARE = 58,\n\tCPUHP_TIMERS_PREPARE = 59,\n\tCPUHP_TMIGR_PREPARE = 60,\n\tCPUHP_MIPS_SOC_PREPARE = 61,\n\tCPUHP_BP_PREPARE_DYN = 62,\n\tCPUHP_BP_PREPARE_DYN_END = 82,\n\tCPUHP_BP_KICK_AP = 83,\n\tCPUHP_BRINGUP_CPU = 84,\n\tCPUHP_AP_IDLE_DEAD = 85,\n\tCPUHP_AP_OFFLINE = 86,\n\tCPUHP_AP_CACHECTRL_STARTING = 87,\n\tCPUHP_AP_SCHED_STARTING = 88,\n\tCPUHP_AP_RCUTREE_DYING = 89,\n\tCPUHP_AP_CPU_PM_STARTING = 90,\n\tCPUHP_AP_IRQ_GIC_STARTING = 91,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 92,\n\tCPUHP_AP_IRQ_APPLE_AIC_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_EIOINTC_STARTING = 97,\n\tCPUHP_AP_IRQ_AVECINTC_STARTING = 98,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 99,\n\tCPUHP_AP_IRQ_ACLINT_SSWI_STARTING = 100,\n\tCPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 101,\n\tCPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING = 102,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 103,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104,\n\tCPUHP_AP_PERF_X86_STARTING = 105,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 107,\n\tCPUHP_AP_ARM_VFP_STARTING = 108,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 109,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_STARTING = 112,\n\tCPUHP_AP_PERF_RISCV_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 117,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 118,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 119,\n\tCPUHP_AP_ARM_TWD_STARTING = 120,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 121,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 122,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 123,\n\tCPUHP_AP_LOONGARCH_ARCH_TIMER_STARTING = 124,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 125,\n\tCPUHP_AP_ARC_TIMER_STARTING = 126,\n\tCPUHP_AP_REALTEK_TIMER_STARTING = 127,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 128,\n\tCPUHP_AP_CLINT_TIMER_STARTING = 129,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 130,\n\tCPUHP_AP_TI_GP_TIMER_STARTING = 131,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_HRTIMERS_DYING = 140,\n\tCPUHP_AP_TICK_DYING = 141,\n\tCPUHP_AP_X86_TBOOT_DYING = 142,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 143,\n\tCPUHP_AP_ONLINE = 144,\n\tCPUHP_TEARDOWN_CPU = 145,\n\tCPUHP_AP_ONLINE_IDLE = 146,\n\tCPUHP_AP_HYPERV_ONLINE = 147,\n\tCPUHP_AP_KVM_ONLINE = 148,\n\tCPUHP_AP_SCHED_WAIT_EMPTY = 149,\n\tCPUHP_AP_SMPBOOT_THREADS = 150,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 151,\n\tCPUHP_AP_BLK_MQ_ONLINE = 152,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 153,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 154,\n\tCPUHP_AP_PERF_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 158,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 160,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 170,\n\tCPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 171,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 172,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 173,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 174,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 175,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 176,\n\tCPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 177,\n\tCPUHP_AP_PERF_ARM_MRVL_PEM_ONLINE = 178,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182,\n\tCPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183,\n\tCPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184,\n\tCPUHP_AP_PERF_CSKY_ONLINE = 185,\n\tCPUHP_AP_TMIGR_ONLINE = 186,\n\tCPUHP_AP_WATCHDOG_ONLINE = 187,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 188,\n\tCPUHP_AP_RANDOM_ONLINE = 189,\n\tCPUHP_AP_RCUTREE_ONLINE = 190,\n\tCPUHP_AP_KTHREADS_ONLINE = 191,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 192,\n\tCPUHP_AP_ONLINE_DYN = 193,\n\tCPUHP_AP_ONLINE_DYN_END = 233,\n\tCPUHP_AP_X86_HPET_ONLINE = 234,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 235,\n\tCPUHP_AP_ACTIVE = 236,\n\tCPUHP_ONLINE = 237,\n};\n\nenum cpuhp_sync_state {\n\tSYNC_STATE_DEAD = 0,\n\tSYNC_STATE_KICKED = 1,\n\tSYNC_STATE_SHOULD_DIE = 2,\n\tSYNC_STATE_ALIVE = 3,\n\tSYNC_STATE_SHOULD_ONLINE = 4,\n\tSYNC_STATE_ONLINE = 5,\n};\n\nenum createmode4 {\n\tNFS4_CREATE_UNCHECKED = 0,\n\tNFS4_CREATE_GUARDED = 1,\n\tNFS4_CREATE_EXCLUSIVE = 2,\n\tNFS4_CREATE_EXCLUSIVE4_1 = 3,\n};\n\nenum criteria {\n\tCR_POWER2_ALIGNED = 0,\n\tCR_GOAL_LEN_FAST = 1,\n\tCR_BEST_AVAIL_LEN = 2,\n\tCR_GOAL_LEN_SLOW = 3,\n\tCR_ANY_FREE = 4,\n\tEXT4_MB_NUM_CRS = 5,\n};\n\nenum css_task_iter_flags {\n\tCSS_TASK_ITER_PROCS = 1,\n\tCSS_TASK_ITER_THREADED = 2,\n\tCSS_TASK_ITER_SKIPPED = 65536,\n};\n\nenum cti_port_type {\n\tCTI_PORT_TYPE_NONE = 0,\n\tCTI_PORT_TYPE_RS232 = 1,\n\tCTI_PORT_TYPE_RS422_485 = 2,\n\tCTI_PORT_TYPE_RS232_422_485_HW = 3,\n\tCTI_PORT_TYPE_RS232_422_485_SW = 4,\n\tCTI_PORT_TYPE_RS232_422_485_4B = 5,\n\tCTI_PORT_TYPE_RS232_422_485_2B = 6,\n\tCTI_PORT_TYPE_MAX = 7,\n};\n\nenum ctx_state {\n\tCT_STATE_DISABLED = -1,\n\tCT_STATE_KERNEL = 0,\n\tCT_STATE_IDLE = 1,\n\tCT_STATE_USER = 2,\n\tCT_STATE_GUEST = 3,\n\tCT_STATE_MAX = 4,\n};\n\nenum cuc_dump {\n\tcuc_dump_complete = 40965,\n\tcuc_dump_reset_complete = 40967,\n};\n\nenum d_real_type {\n\tD_REAL_DATA = 0,\n\tD_REAL_METADATA = 1,\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nenum data_formats {\n\tDATA_FMT_DIGEST = 0,\n\tDATA_FMT_DIGEST_WITH_ALGO = 1,\n\tDATA_FMT_DIGEST_WITH_TYPE_AND_ALGO = 2,\n\tDATA_FMT_STRING = 3,\n\tDATA_FMT_HEX = 4,\n\tDATA_FMT_UINT = 5,\n};\n\nenum dax_access_mode {\n\tDAX_ACCESS = 0,\n\tDAX_RECOVERY_WRITE = 1,\n};\n\nenum dax_device_flags {\n\tDAXDEV_ALIVE = 0,\n\tDAXDEV_WRITE_CACHE = 1,\n\tDAXDEV_SYNC = 2,\n\tDAXDEV_NOCACHE = 3,\n\tDAXDEV_NOMC = 4,\n};\n\nenum dax_driver_type {\n\tDAXDRV_KMEM_TYPE = 0,\n\tDAXDRV_DEVICE_TYPE = 1,\n};\n\nenum dax_wake_mode {\n\tWAKE_ALL = 0,\n\tWAKE_NEXT = 1,\n};\n\nenum dbgfs_get_mode {\n\tDBGFS_GET_ALREADY = 0,\n\tDBGFS_GET_REGULAR = 1,\n\tDBGFS_GET_SHORT = 2,\n};\n\nenum dd_data_dir {\n\tDD_READ = 0,\n\tDD_WRITE = 1,\n};\n\nenum dd_prio {\n\tDD_RT_PRIO = 0,\n\tDD_BE_PRIO = 1,\n\tDD_IDLE_PRIO = 2,\n\tDD_PRIO_MAX = 2,\n};\n\nenum ddc_type {\n\tddc_none = 0,\n\tddc_monid = 1,\n\tddc_dvi = 2,\n\tddc_vga = 3,\n\tddc_crt2 = 4,\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nenum dentry_flags {\n\tDCACHE_OP_HASH = 1,\n\tDCACHE_OP_COMPARE = 2,\n\tDCACHE_OP_REVALIDATE = 4,\n\tDCACHE_OP_DELETE = 8,\n\tDCACHE_OP_PRUNE = 16,\n\tDCACHE_DISCONNECTED = 32,\n\tDCACHE_REFERENCED = 64,\n\tDCACHE_DONTCACHE = 128,\n\tDCACHE_CANT_MOUNT = 256,\n\tDCACHE_SHRINK_LIST = 1024,\n\tDCACHE_OP_WEAK_REVALIDATE = 2048,\n\tDCACHE_NFSFS_RENAMED = 4096,\n\tDCACHE_FSNOTIFY_PARENT_WATCHED = 8192,\n\tDCACHE_DENTRY_KILLED = 16384,\n\tDCACHE_MOUNTED = 32768,\n\tDCACHE_NEED_AUTOMOUNT = 65536,\n\tDCACHE_MANAGE_TRANSIT = 131072,\n\tDCACHE_LRU_LIST = 262144,\n\tDCACHE_ENTRY_TYPE = 3670016,\n\tDCACHE_MISS_TYPE = 0,\n\tDCACHE_WHITEOUT_TYPE = 524288,\n\tDCACHE_DIRECTORY_TYPE = 1048576,\n\tDCACHE_AUTODIR_TYPE = 1572864,\n\tDCACHE_REGULAR_TYPE = 2097152,\n\tDCACHE_SPECIAL_TYPE = 2621440,\n\tDCACHE_SYMLINK_TYPE = 3145728,\n\tDCACHE_NOKEY_NAME = 4194304,\n\tDCACHE_OP_REAL = 8388608,\n\tDCACHE_PAR_LOOKUP = 16777216,\n\tDCACHE_DENTRY_CURSOR = 33554432,\n\tDCACHE_NORCU = 67108864,\n\tDCACHE_PERSISTENT = 134217728,\n};\n\nenum depot_counter_id {\n\tDEPOT_COUNTER_REFD_ALLOCS = 0,\n\tDEPOT_COUNTER_REFD_FREES = 1,\n\tDEPOT_COUNTER_REFD_INUSE = 2,\n\tDEPOT_COUNTER_FREELIST_SIZE = 3,\n\tDEPOT_COUNTER_PERSIST_COUNT = 4,\n\tDEPOT_COUNTER_PERSIST_BYTES = 5,\n\tDEPOT_COUNTER_COUNT = 6,\n};\n\nenum desc_state {\n\tdesc_miss = -1,\n\tdesc_reserved = 0,\n\tdesc_committed = 1,\n\tdesc_finalized = 2,\n\tdesc_reusable = 3,\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nenum dev_type {\n\tDEV_UNKNOWN = 0,\n\tDEV_X1 = 1,\n\tDEV_X2 = 2,\n\tDEV_X4 = 3,\n\tDEV_X8 = 4,\n\tDEV_X16 = 5,\n\tDEV_X32 = 6,\n\tDEV_X64 = 7,\n};\n\nenum devcg_behavior {\n\tDEVCG_DEFAULT_NONE = 0,\n\tDEVCG_DEFAULT_ALLOW = 1,\n\tDEVCG_DEFAULT_DENY = 2,\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = -1,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nenum device_physical_location_horizontal_position {\n\tDEVICE_HORI_POS_LEFT = 0,\n\tDEVICE_HORI_POS_CENTER = 1,\n\tDEVICE_HORI_POS_RIGHT = 2,\n};\n\nenum device_physical_location_panel {\n\tDEVICE_PANEL_TOP = 0,\n\tDEVICE_PANEL_BOTTOM = 1,\n\tDEVICE_PANEL_LEFT = 2,\n\tDEVICE_PANEL_RIGHT = 3,\n\tDEVICE_PANEL_FRONT = 4,\n\tDEVICE_PANEL_BACK = 5,\n\tDEVICE_PANEL_UNKNOWN = 6,\n};\n\nenum device_physical_location_vertical_position {\n\tDEVICE_VERT_POS_UPPER = 0,\n\tDEVICE_VERT_POS_CENTER = 1,\n\tDEVICE_VERT_POS_LOWER = 2,\n};\n\nenum device_removable {\n\tDEVICE_REMOVABLE_NOT_SUPPORTED = 0,\n\tDEVICE_REMOVABLE_UNKNOWN = 1,\n\tDEVICE_FIXED = 2,\n\tDEVICE_REMOVABLE = 3,\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum devlink_attr {\n\tDEVLINK_ATTR_UNSPEC = 0,\n\tDEVLINK_ATTR_BUS_NAME = 1,\n\tDEVLINK_ATTR_DEV_NAME = 2,\n\tDEVLINK_ATTR_PORT_INDEX = 3,\n\tDEVLINK_ATTR_PORT_TYPE = 4,\n\tDEVLINK_ATTR_PORT_DESIRED_TYPE = 5,\n\tDEVLINK_ATTR_PORT_NETDEV_IFINDEX = 6,\n\tDEVLINK_ATTR_PORT_NETDEV_NAME = 7,\n\tDEVLINK_ATTR_PORT_IBDEV_NAME = 8,\n\tDEVLINK_ATTR_PORT_SPLIT_COUNT = 9,\n\tDEVLINK_ATTR_PORT_SPLIT_GROUP = 10,\n\tDEVLINK_ATTR_SB_INDEX = 11,\n\tDEVLINK_ATTR_SB_SIZE = 12,\n\tDEVLINK_ATTR_SB_INGRESS_POOL_COUNT = 13,\n\tDEVLINK_ATTR_SB_EGRESS_POOL_COUNT = 14,\n\tDEVLINK_ATTR_SB_INGRESS_TC_COUNT = 15,\n\tDEVLINK_ATTR_SB_EGRESS_TC_COUNT = 16,\n\tDEVLINK_ATTR_SB_POOL_INDEX = 17,\n\tDEVLINK_ATTR_SB_POOL_TYPE = 18,\n\tDEVLINK_ATTR_SB_POOL_SIZE = 19,\n\tDEVLINK_ATTR_SB_POOL_THRESHOLD_TYPE = 20,\n\tDEVLINK_ATTR_SB_THRESHOLD = 21,\n\tDEVLINK_ATTR_SB_TC_INDEX = 22,\n\tDEVLINK_ATTR_SB_OCC_CUR = 23,\n\tDEVLINK_ATTR_SB_OCC_MAX = 24,\n\tDEVLINK_ATTR_ESWITCH_MODE = 25,\n\tDEVLINK_ATTR_ESWITCH_INLINE_MODE = 26,\n\tDEVLINK_ATTR_DPIPE_TABLES = 27,\n\tDEVLINK_ATTR_DPIPE_TABLE = 28,\n\tDEVLINK_ATTR_DPIPE_TABLE_NAME = 29,\n\tDEVLINK_ATTR_DPIPE_TABLE_SIZE = 30,\n\tDEVLINK_ATTR_DPIPE_TABLE_MATCHES = 31,\n\tDEVLINK_ATTR_DPIPE_TABLE_ACTIONS = 32,\n\tDEVLINK_ATTR_DPIPE_TABLE_COUNTERS_ENABLED = 33,\n\tDEVLINK_ATTR_DPIPE_ENTRIES = 34,\n\tDEVLINK_ATTR_DPIPE_ENTRY = 35,\n\tDEVLINK_ATTR_DPIPE_ENTRY_INDEX = 36,\n\tDEVLINK_ATTR_DPIPE_ENTRY_MATCH_VALUES = 37,\n\tDEVLINK_ATTR_DPIPE_ENTRY_ACTION_VALUES = 38,\n\tDEVLINK_ATTR_DPIPE_ENTRY_COUNTER = 39,\n\tDEVLINK_ATTR_DPIPE_MATCH = 40,\n\tDEVLINK_ATTR_DPIPE_MATCH_VALUE = 41,\n\tDEVLINK_ATTR_DPIPE_MATCH_TYPE = 42,\n\tDEVLINK_ATTR_DPIPE_ACTION = 43,\n\tDEVLINK_ATTR_DPIPE_ACTION_VALUE = 44,\n\tDEVLINK_ATTR_DPIPE_ACTION_TYPE = 45,\n\tDEVLINK_ATTR_DPIPE_VALUE = 46,\n\tDEVLINK_ATTR_DPIPE_VALUE_MASK = 47,\n\tDEVLINK_ATTR_DPIPE_VALUE_MAPPING = 48,\n\tDEVLINK_ATTR_DPIPE_HEADERS = 49,\n\tDEVLINK_ATTR_DPIPE_HEADER = 50,\n\tDEVLINK_ATTR_DPIPE_HEADER_NAME = 51,\n\tDEVLINK_ATTR_DPIPE_HEADER_ID = 52,\n\tDEVLINK_ATTR_DPIPE_HEADER_FIELDS = 53,\n\tDEVLINK_ATTR_DPIPE_HEADER_GLOBAL = 54,\n\tDEVLINK_ATTR_DPIPE_HEADER_INDEX = 55,\n\tDEVLINK_ATTR_DPIPE_FIELD = 56,\n\tDEVLINK_ATTR_DPIPE_FIELD_NAME = 57,\n\tDEVLINK_ATTR_DPIPE_FIELD_ID = 58,\n\tDEVLINK_ATTR_DPIPE_FIELD_BITWIDTH = 59,\n\tDEVLINK_ATTR_DPIPE_FIELD_MAPPING_TYPE = 60,\n\tDEVLINK_ATTR_PAD = 61,\n\tDEVLINK_ATTR_ESWITCH_ENCAP_MODE = 62,\n\tDEVLINK_ATTR_RESOURCE_LIST = 63,\n\tDEVLINK_ATTR_RESOURCE = 64,\n\tDEVLINK_ATTR_RESOURCE_NAME = 65,\n\tDEVLINK_ATTR_RESOURCE_ID = 66,\n\tDEVLINK_ATTR_RESOURCE_SIZE = 67,\n\tDEVLINK_ATTR_RESOURCE_SIZE_NEW = 68,\n\tDEVLINK_ATTR_RESOURCE_SIZE_VALID = 69,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MIN = 70,\n\tDEVLINK_ATTR_RESOURCE_SIZE_MAX = 71,\n\tDEVLINK_ATTR_RESOURCE_SIZE_GRAN = 72,\n\tDEVLINK_ATTR_RESOURCE_UNIT = 73,\n\tDEVLINK_ATTR_RESOURCE_OCC = 74,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID = 75,\n\tDEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS = 76,\n\tDEVLINK_ATTR_PORT_FLAVOUR = 77,\n\tDEVLINK_ATTR_PORT_NUMBER = 78,\n\tDEVLINK_ATTR_PORT_SPLIT_SUBPORT_NUMBER = 79,\n\tDEVLINK_ATTR_PARAM = 80,\n\tDEVLINK_ATTR_PARAM_NAME = 81,\n\tDEVLINK_ATTR_PARAM_GENERIC = 82,\n\tDEVLINK_ATTR_PARAM_TYPE = 83,\n\tDEVLINK_ATTR_PARAM_VALUES_LIST = 84,\n\tDEVLINK_ATTR_PARAM_VALUE = 85,\n\tDEVLINK_ATTR_PARAM_VALUE_DATA = 86,\n\tDEVLINK_ATTR_PARAM_VALUE_CMODE = 87,\n\tDEVLINK_ATTR_REGION_NAME = 88,\n\tDEVLINK_ATTR_REGION_SIZE = 89,\n\tDEVLINK_ATTR_REGION_SNAPSHOTS = 90,\n\tDEVLINK_ATTR_REGION_SNAPSHOT = 91,\n\tDEVLINK_ATTR_REGION_SNAPSHOT_ID = 92,\n\tDEVLINK_ATTR_REGION_CHUNKS = 93,\n\tDEVLINK_ATTR_REGION_CHUNK = 94,\n\tDEVLINK_ATTR_REGION_CHUNK_DATA = 95,\n\tDEVLINK_ATTR_REGION_CHUNK_ADDR = 96,\n\tDEVLINK_ATTR_REGION_CHUNK_LEN = 97,\n\tDEVLINK_ATTR_INFO_DRIVER_NAME = 98,\n\tDEVLINK_ATTR_INFO_SERIAL_NUMBER = 99,\n\tDEVLINK_ATTR_INFO_VERSION_FIXED = 100,\n\tDEVLINK_ATTR_INFO_VERSION_RUNNING = 101,\n\tDEVLINK_ATTR_INFO_VERSION_STORED = 102,\n\tDEVLINK_ATTR_INFO_VERSION_NAME = 103,\n\tDEVLINK_ATTR_INFO_VERSION_VALUE = 104,\n\tDEVLINK_ATTR_SB_POOL_CELL_SIZE = 105,\n\tDEVLINK_ATTR_FMSG = 106,\n\tDEVLINK_ATTR_FMSG_OBJ_NEST_START = 107,\n\tDEVLINK_ATTR_FMSG_PAIR_NEST_START = 108,\n\tDEVLINK_ATTR_FMSG_ARR_NEST_START = 109,\n\tDEVLINK_ATTR_FMSG_NEST_END = 110,\n\tDEVLINK_ATTR_FMSG_OBJ_NAME = 111,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_TYPE = 112,\n\tDEVLINK_ATTR_FMSG_OBJ_VALUE_DATA = 113,\n\tDEVLINK_ATTR_HEALTH_REPORTER = 114,\n\tDEVLINK_ATTR_HEALTH_REPORTER_NAME = 115,\n\tDEVLINK_ATTR_HEALTH_REPORTER_STATE = 116,\n\tDEVLINK_ATTR_HEALTH_REPORTER_ERR_COUNT = 117,\n\tDEVLINK_ATTR_HEALTH_REPORTER_RECOVER_COUNT = 118,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS = 119,\n\tDEVLINK_ATTR_HEALTH_REPORTER_GRACEFUL_PERIOD = 120,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_RECOVER = 121,\n\tDEVLINK_ATTR_FLASH_UPDATE_FILE_NAME = 122,\n\tDEVLINK_ATTR_FLASH_UPDATE_COMPONENT = 123,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_MSG = 124,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_DONE = 125,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TOTAL = 126,\n\tDEVLINK_ATTR_PORT_PCI_PF_NUMBER = 127,\n\tDEVLINK_ATTR_PORT_PCI_VF_NUMBER = 128,\n\tDEVLINK_ATTR_STATS = 129,\n\tDEVLINK_ATTR_TRAP_NAME = 130,\n\tDEVLINK_ATTR_TRAP_ACTION = 131,\n\tDEVLINK_ATTR_TRAP_TYPE = 132,\n\tDEVLINK_ATTR_TRAP_GENERIC = 133,\n\tDEVLINK_ATTR_TRAP_METADATA = 134,\n\tDEVLINK_ATTR_TRAP_GROUP_NAME = 135,\n\tDEVLINK_ATTR_RELOAD_FAILED = 136,\n\tDEVLINK_ATTR_HEALTH_REPORTER_DUMP_TS_NS = 137,\n\tDEVLINK_ATTR_NETNS_FD = 138,\n\tDEVLINK_ATTR_NETNS_PID = 139,\n\tDEVLINK_ATTR_NETNS_ID = 140,\n\tDEVLINK_ATTR_HEALTH_REPORTER_AUTO_DUMP = 141,\n\tDEVLINK_ATTR_TRAP_POLICER_ID = 142,\n\tDEVLINK_ATTR_TRAP_POLICER_RATE = 143,\n\tDEVLINK_ATTR_TRAP_POLICER_BURST = 144,\n\tDEVLINK_ATTR_PORT_FUNCTION = 145,\n\tDEVLINK_ATTR_INFO_BOARD_SERIAL_NUMBER = 146,\n\tDEVLINK_ATTR_PORT_LANES = 147,\n\tDEVLINK_ATTR_PORT_SPLITTABLE = 148,\n\tDEVLINK_ATTR_PORT_EXTERNAL = 149,\n\tDEVLINK_ATTR_PORT_CONTROLLER_NUMBER = 150,\n\tDEVLINK_ATTR_FLASH_UPDATE_STATUS_TIMEOUT = 151,\n\tDEVLINK_ATTR_FLASH_UPDATE_OVERWRITE_MASK = 152,\n\tDEVLINK_ATTR_RELOAD_ACTION = 153,\n\tDEVLINK_ATTR_RELOAD_ACTIONS_PERFORMED = 154,\n\tDEVLINK_ATTR_RELOAD_LIMITS = 155,\n\tDEVLINK_ATTR_DEV_STATS = 156,\n\tDEVLINK_ATTR_RELOAD_STATS = 157,\n\tDEVLINK_ATTR_RELOAD_STATS_ENTRY = 158,\n\tDEVLINK_ATTR_RELOAD_STATS_LIMIT = 159,\n\tDEVLINK_ATTR_RELOAD_STATS_VALUE = 160,\n\tDEVLINK_ATTR_REMOTE_RELOAD_STATS = 161,\n\tDEVLINK_ATTR_RELOAD_ACTION_INFO = 162,\n\tDEVLINK_ATTR_RELOAD_ACTION_STATS = 163,\n\tDEVLINK_ATTR_PORT_PCI_SF_NUMBER = 164,\n\tDEVLINK_ATTR_RATE_TYPE = 165,\n\tDEVLINK_ATTR_RATE_TX_SHARE = 166,\n\tDEVLINK_ATTR_RATE_TX_MAX = 167,\n\tDEVLINK_ATTR_RATE_NODE_NAME = 168,\n\tDEVLINK_ATTR_RATE_PARENT_NODE_NAME = 169,\n\tDEVLINK_ATTR_REGION_MAX_SNAPSHOTS = 170,\n\tDEVLINK_ATTR_LINECARD_INDEX = 171,\n\tDEVLINK_ATTR_LINECARD_STATE = 172,\n\tDEVLINK_ATTR_LINECARD_TYPE = 173,\n\tDEVLINK_ATTR_LINECARD_SUPPORTED_TYPES = 174,\n\tDEVLINK_ATTR_NESTED_DEVLINK = 175,\n\tDEVLINK_ATTR_SELFTESTS = 176,\n\tDEVLINK_ATTR_RATE_TX_PRIORITY = 177,\n\tDEVLINK_ATTR_RATE_TX_WEIGHT = 178,\n\tDEVLINK_ATTR_REGION_DIRECT = 179,\n\tDEVLINK_ATTR_RATE_TC_BWS = 180,\n\tDEVLINK_ATTR_HEALTH_REPORTER_BURST_PERIOD = 181,\n\tDEVLINK_ATTR_PARAM_VALUE_DEFAULT = 182,\n\tDEVLINK_ATTR_PARAM_RESET_DEFAULT = 183,\n\t__DEVLINK_ATTR_MAX = 184,\n\tDEVLINK_ATTR_MAX = 183,\n};\n\nenum devlink_attr_selftest_id {\n\tDEVLINK_ATTR_SELFTEST_ID_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_ID_FLASH = 1,\n\t__DEVLINK_ATTR_SELFTEST_ID_MAX = 2,\n\tDEVLINK_ATTR_SELFTEST_ID_MAX = 1,\n};\n\nenum devlink_attr_selftest_result {\n\tDEVLINK_ATTR_SELFTEST_RESULT_UNSPEC = 0,\n\tDEVLINK_ATTR_SELFTEST_RESULT = 1,\n\tDEVLINK_ATTR_SELFTEST_RESULT_ID = 2,\n\tDEVLINK_ATTR_SELFTEST_RESULT_STATUS = 3,\n\t__DEVLINK_ATTR_SELFTEST_RESULT_MAX = 4,\n\tDEVLINK_ATTR_SELFTEST_RESULT_MAX = 3,\n};\n\nenum devlink_command {\n\tDEVLINK_CMD_UNSPEC = 0,\n\tDEVLINK_CMD_GET = 1,\n\tDEVLINK_CMD_SET = 2,\n\tDEVLINK_CMD_NEW = 3,\n\tDEVLINK_CMD_DEL = 4,\n\tDEVLINK_CMD_PORT_GET = 5,\n\tDEVLINK_CMD_PORT_SET = 6,\n\tDEVLINK_CMD_PORT_NEW = 7,\n\tDEVLINK_CMD_PORT_DEL = 8,\n\tDEVLINK_CMD_PORT_SPLIT = 9,\n\tDEVLINK_CMD_PORT_UNSPLIT = 10,\n\tDEVLINK_CMD_SB_GET = 11,\n\tDEVLINK_CMD_SB_SET = 12,\n\tDEVLINK_CMD_SB_NEW = 13,\n\tDEVLINK_CMD_SB_DEL = 14,\n\tDEVLINK_CMD_SB_POOL_GET = 15,\n\tDEVLINK_CMD_SB_POOL_SET = 16,\n\tDEVLINK_CMD_SB_POOL_NEW = 17,\n\tDEVLINK_CMD_SB_POOL_DEL = 18,\n\tDEVLINK_CMD_SB_PORT_POOL_GET = 19,\n\tDEVLINK_CMD_SB_PORT_POOL_SET = 20,\n\tDEVLINK_CMD_SB_PORT_POOL_NEW = 21,\n\tDEVLINK_CMD_SB_PORT_POOL_DEL = 22,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_GET = 23,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_SET = 24,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_NEW = 25,\n\tDEVLINK_CMD_SB_TC_POOL_BIND_DEL = 26,\n\tDEVLINK_CMD_SB_OCC_SNAPSHOT = 27,\n\tDEVLINK_CMD_SB_OCC_MAX_CLEAR = 28,\n\tDEVLINK_CMD_ESWITCH_GET = 29,\n\tDEVLINK_CMD_ESWITCH_SET = 30,\n\tDEVLINK_CMD_DPIPE_TABLE_GET = 31,\n\tDEVLINK_CMD_DPIPE_ENTRIES_GET = 32,\n\tDEVLINK_CMD_DPIPE_HEADERS_GET = 33,\n\tDEVLINK_CMD_DPIPE_TABLE_COUNTERS_SET = 34,\n\tDEVLINK_CMD_RESOURCE_SET = 35,\n\tDEVLINK_CMD_RESOURCE_DUMP = 36,\n\tDEVLINK_CMD_RELOAD = 37,\n\tDEVLINK_CMD_PARAM_GET = 38,\n\tDEVLINK_CMD_PARAM_SET = 39,\n\tDEVLINK_CMD_PARAM_NEW = 40,\n\tDEVLINK_CMD_PARAM_DEL = 41,\n\tDEVLINK_CMD_REGION_GET = 42,\n\tDEVLINK_CMD_REGION_SET = 43,\n\tDEVLINK_CMD_REGION_NEW = 44,\n\tDEVLINK_CMD_REGION_DEL = 45,\n\tDEVLINK_CMD_REGION_READ = 46,\n\tDEVLINK_CMD_PORT_PARAM_GET = 47,\n\tDEVLINK_CMD_PORT_PARAM_SET = 48,\n\tDEVLINK_CMD_PORT_PARAM_NEW = 49,\n\tDEVLINK_CMD_PORT_PARAM_DEL = 50,\n\tDEVLINK_CMD_INFO_GET = 51,\n\tDEVLINK_CMD_HEALTH_REPORTER_GET = 52,\n\tDEVLINK_CMD_HEALTH_REPORTER_SET = 53,\n\tDEVLINK_CMD_HEALTH_REPORTER_RECOVER = 54,\n\tDEVLINK_CMD_HEALTH_REPORTER_DIAGNOSE = 55,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_GET = 56,\n\tDEVLINK_CMD_HEALTH_REPORTER_DUMP_CLEAR = 57,\n\tDEVLINK_CMD_FLASH_UPDATE = 58,\n\tDEVLINK_CMD_FLASH_UPDATE_END = 59,\n\tDEVLINK_CMD_FLASH_UPDATE_STATUS = 60,\n\tDEVLINK_CMD_TRAP_GET = 61,\n\tDEVLINK_CMD_TRAP_SET = 62,\n\tDEVLINK_CMD_TRAP_NEW = 63,\n\tDEVLINK_CMD_TRAP_DEL = 64,\n\tDEVLINK_CMD_TRAP_GROUP_GET = 65,\n\tDEVLINK_CMD_TRAP_GROUP_SET = 66,\n\tDEVLINK_CMD_TRAP_GROUP_NEW = 67,\n\tDEVLINK_CMD_TRAP_GROUP_DEL = 68,\n\tDEVLINK_CMD_TRAP_POLICER_GET = 69,\n\tDEVLINK_CMD_TRAP_POLICER_SET = 70,\n\tDEVLINK_CMD_TRAP_POLICER_NEW = 71,\n\tDEVLINK_CMD_TRAP_POLICER_DEL = 72,\n\tDEVLINK_CMD_HEALTH_REPORTER_TEST = 73,\n\tDEVLINK_CMD_RATE_GET = 74,\n\tDEVLINK_CMD_RATE_SET = 75,\n\tDEVLINK_CMD_RATE_NEW = 76,\n\tDEVLINK_CMD_RATE_DEL = 77,\n\tDEVLINK_CMD_LINECARD_GET = 78,\n\tDEVLINK_CMD_LINECARD_SET = 79,\n\tDEVLINK_CMD_LINECARD_NEW = 80,\n\tDEVLINK_CMD_LINECARD_DEL = 81,\n\tDEVLINK_CMD_SELFTESTS_GET = 82,\n\tDEVLINK_CMD_SELFTESTS_RUN = 83,\n\tDEVLINK_CMD_NOTIFY_FILTER_SET = 84,\n\t__DEVLINK_CMD_MAX = 85,\n\tDEVLINK_CMD_MAX = 84,\n};\n\nenum devlink_dpipe_action_type {\n\tDEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY = 0,\n};\n\nenum devlink_dpipe_field_ethernet_id {\n\tDEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC = 0,\n};\n\nenum devlink_dpipe_field_ipv4_id {\n\tDEVLINK_DPIPE_FIELD_IPV4_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_ipv6_id {\n\tDEVLINK_DPIPE_FIELD_IPV6_DST_IP = 0,\n};\n\nenum devlink_dpipe_field_mapping_type {\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0,\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1,\n};\n\nenum devlink_dpipe_header_id {\n\tDEVLINK_DPIPE_HEADER_ETHERNET = 0,\n\tDEVLINK_DPIPE_HEADER_IPV4 = 1,\n\tDEVLINK_DPIPE_HEADER_IPV6 = 2,\n};\n\nenum devlink_dpipe_match_type {\n\tDEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT = 0,\n};\n\nenum devlink_eswitch_encap_mode {\n\tDEVLINK_ESWITCH_ENCAP_MODE_NONE = 0,\n\tDEVLINK_ESWITCH_ENCAP_MODE_BASIC = 1,\n};\n\nenum devlink_health_reporter_state {\n\tDEVLINK_HEALTH_REPORTER_STATE_HEALTHY = 0,\n\tDEVLINK_HEALTH_REPORTER_STATE_ERROR = 1,\n};\n\nenum devlink_info_version_type {\n\tDEVLINK_INFO_VERSION_TYPE_NONE = 0,\n\tDEVLINK_INFO_VERSION_TYPE_COMPONENT = 1,\n};\n\nenum devlink_linecard_state {\n\tDEVLINK_LINECARD_STATE_UNSPEC = 0,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONED = 1,\n\tDEVLINK_LINECARD_STATE_UNPROVISIONING = 2,\n\tDEVLINK_LINECARD_STATE_PROVISIONING = 3,\n\tDEVLINK_LINECARD_STATE_PROVISIONING_FAILED = 4,\n\tDEVLINK_LINECARD_STATE_PROVISIONED = 5,\n\tDEVLINK_LINECARD_STATE_ACTIVE = 6,\n\t__DEVLINK_LINECARD_STATE_MAX = 7,\n\tDEVLINK_LINECARD_STATE_MAX = 6,\n};\n\nenum devlink_multicast_groups {\n\tDEVLINK_MCGRP_CONFIG = 0,\n};\n\nenum devlink_param_cmode {\n\tDEVLINK_PARAM_CMODE_RUNTIME = 0,\n\tDEVLINK_PARAM_CMODE_DRIVERINIT = 1,\n\tDEVLINK_PARAM_CMODE_PERMANENT = 2,\n\t__DEVLINK_PARAM_CMODE_MAX = 3,\n\tDEVLINK_PARAM_CMODE_MAX = 2,\n};\n\nenum devlink_param_generic_id {\n\tDEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET = 0,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MACS = 1,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_SRIOV = 2,\n\tDEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT = 3,\n\tDEVLINK_PARAM_GENERIC_ID_IGNORE_ARI = 4,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX = 5,\n\tDEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN = 6,\n\tDEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY = 7,\n\tDEVLINK_PARAM_GENERIC_ID_RESET_DEV_ON_DRV_PROBE = 8,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE = 9,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_REMOTE_DEV_RESET = 10,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_ETH = 11,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA = 12,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_VNET = 13,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_IWARP = 14,\n\tDEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE = 15,\n\tDEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE = 16,\n\tDEVLINK_PARAM_GENERIC_ID_ENABLE_PHC = 17,\n\tDEVLINK_PARAM_GENERIC_ID_CLOCK_ID = 18,\n\tDEVLINK_PARAM_GENERIC_ID_TOTAL_VFS = 19,\n\tDEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS = 20,\n\tDEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF = 21,\n\t__DEVLINK_PARAM_GENERIC_ID_MAX = 22,\n\tDEVLINK_PARAM_GENERIC_ID_MAX = 21,\n};\n\nenum devlink_param_type {\n\tDEVLINK_PARAM_TYPE_U8 = 1,\n\tDEVLINK_PARAM_TYPE_U16 = 2,\n\tDEVLINK_PARAM_TYPE_U32 = 3,\n\tDEVLINK_PARAM_TYPE_U64 = 4,\n\tDEVLINK_PARAM_TYPE_STRING = 5,\n\tDEVLINK_PARAM_TYPE_BOOL = 6,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n\tDEVLINK_PORT_FLAVOUR_UNUSED = 6,\n\tDEVLINK_PORT_FLAVOUR_PCI_SF = 7,\n};\n\nenum devlink_port_fn_attr_cap {\n\tDEVLINK_PORT_FN_ATTR_CAP_ROCE_BIT = 0,\n\tDEVLINK_PORT_FN_ATTR_CAP_MIGRATABLE_BIT = 1,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_CRYPTO_BIT = 2,\n\tDEVLINK_PORT_FN_ATTR_CAP_IPSEC_PACKET_BIT = 3,\n\t__DEVLINK_PORT_FN_ATTR_CAPS_MAX = 4,\n};\n\nenum devlink_port_fn_opstate {\n\tDEVLINK_PORT_FN_OPSTATE_DETACHED = 0,\n\tDEVLINK_PORT_FN_OPSTATE_ATTACHED = 1,\n};\n\nenum devlink_port_fn_state {\n\tDEVLINK_PORT_FN_STATE_INACTIVE = 0,\n\tDEVLINK_PORT_FN_STATE_ACTIVE = 1,\n};\n\nenum devlink_port_function_attr {\n\tDEVLINK_PORT_FUNCTION_ATTR_UNSPEC = 0,\n\tDEVLINK_PORT_FUNCTION_ATTR_HW_ADDR = 1,\n\tDEVLINK_PORT_FN_ATTR_STATE = 2,\n\tDEVLINK_PORT_FN_ATTR_OPSTATE = 3,\n\tDEVLINK_PORT_FN_ATTR_CAPS = 4,\n\tDEVLINK_PORT_FN_ATTR_DEVLINK = 5,\n\tDEVLINK_PORT_FN_ATTR_MAX_IO_EQS = 6,\n\t__DEVLINK_PORT_FUNCTION_ATTR_MAX = 7,\n\tDEVLINK_PORT_FUNCTION_ATTR_MAX = 6,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_rate_tc_attr {\n\tDEVLINK_RATE_TC_ATTR_UNSPEC = 0,\n\tDEVLINK_RATE_TC_ATTR_INDEX = 1,\n\tDEVLINK_RATE_TC_ATTR_BW = 2,\n\t__DEVLINK_RATE_TC_ATTR_MAX = 3,\n\tDEVLINK_RATE_TC_ATTR_MAX = 2,\n};\n\nenum devlink_rate_type {\n\tDEVLINK_RATE_TYPE_LEAF = 0,\n\tDEVLINK_RATE_TYPE_NODE = 1,\n};\n\nenum devlink_reload_action {\n\tDEVLINK_RELOAD_ACTION_UNSPEC = 0,\n\tDEVLINK_RELOAD_ACTION_DRIVER_REINIT = 1,\n\tDEVLINK_RELOAD_ACTION_FW_ACTIVATE = 2,\n\t__DEVLINK_RELOAD_ACTION_MAX = 3,\n\tDEVLINK_RELOAD_ACTION_MAX = 2,\n};\n\nenum devlink_reload_limit {\n\tDEVLINK_RELOAD_LIMIT_UNSPEC = 0,\n\tDEVLINK_RELOAD_LIMIT_NO_RESET = 1,\n\t__DEVLINK_RELOAD_LIMIT_MAX = 2,\n\tDEVLINK_RELOAD_LIMIT_MAX = 1,\n};\n\nenum devlink_resource_unit {\n\tDEVLINK_RESOURCE_UNIT_ENTRY = 0,\n};\n\nenum devlink_sb_pool_type {\n\tDEVLINK_SB_POOL_TYPE_INGRESS = 0,\n\tDEVLINK_SB_POOL_TYPE_EGRESS = 1,\n};\n\nenum devlink_sb_threshold_type {\n\tDEVLINK_SB_THRESHOLD_TYPE_STATIC = 0,\n\tDEVLINK_SB_THRESHOLD_TYPE_DYNAMIC = 1,\n};\n\nenum devlink_selftest_status {\n\tDEVLINK_SELFTEST_STATUS_SKIP = 0,\n\tDEVLINK_SELFTEST_STATUS_PASS = 1,\n\tDEVLINK_SELFTEST_STATUS_FAIL = 2,\n};\n\nenum devlink_trap_action {\n\tDEVLINK_TRAP_ACTION_DROP = 0,\n\tDEVLINK_TRAP_ACTION_TRAP = 1,\n\tDEVLINK_TRAP_ACTION_MIRROR = 2,\n};\n\nenum devlink_trap_generic_id {\n\tDEVLINK_TRAP_GENERIC_ID_SMAC_MC = 0,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_TAG_MISMATCH = 1,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_VLAN_FILTER = 2,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_STP_FILTER = 3,\n\tDEVLINK_TRAP_GENERIC_ID_EMPTY_TX_LIST = 4,\n\tDEVLINK_TRAP_GENERIC_ID_PORT_LOOPBACK_FILTER = 5,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_ROUTE = 6,\n\tDEVLINK_TRAP_GENERIC_ID_TTL_ERROR = 7,\n\tDEVLINK_TRAP_GENERIC_ID_TAIL_DROP = 8,\n\tDEVLINK_TRAP_GENERIC_ID_NON_IP_PACKET = 9,\n\tDEVLINK_TRAP_GENERIC_ID_UC_DIP_MC_DMAC = 10,\n\tDEVLINK_TRAP_GENERIC_ID_DIP_LB = 11,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_MC = 12,\n\tDEVLINK_TRAP_GENERIC_ID_SIP_LB = 13,\n\tDEVLINK_TRAP_GENERIC_ID_CORRUPTED_IP_HDR = 14,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_SIP_BC = 15,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_RESERVED_SCOPE = 16,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_MC_DIP_INTERFACE_LOCAL_SCOPE = 17,\n\tDEVLINK_TRAP_GENERIC_ID_MTU_ERROR = 18,\n\tDEVLINK_TRAP_GENERIC_ID_UNRESOLVED_NEIGH = 19,\n\tDEVLINK_TRAP_GENERIC_ID_RPF = 20,\n\tDEVLINK_TRAP_GENERIC_ID_REJECT_ROUTE = 21,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_LPM_UNICAST_MISS = 22,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_LPM_UNICAST_MISS = 23,\n\tDEVLINK_TRAP_GENERIC_ID_NON_ROUTABLE = 24,\n\tDEVLINK_TRAP_GENERIC_ID_DECAP_ERROR = 25,\n\tDEVLINK_TRAP_GENERIC_ID_OVERLAY_SMAC_MC = 26,\n\tDEVLINK_TRAP_GENERIC_ID_INGRESS_FLOW_ACTION_DROP = 27,\n\tDEVLINK_TRAP_GENERIC_ID_EGRESS_FLOW_ACTION_DROP = 28,\n\tDEVLINK_TRAP_GENERIC_ID_STP = 29,\n\tDEVLINK_TRAP_GENERIC_ID_LACP = 30,\n\tDEVLINK_TRAP_GENERIC_ID_LLDP = 31,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_QUERY = 32,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V1_REPORT = 33,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_REPORT = 34,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V3_REPORT = 35,\n\tDEVLINK_TRAP_GENERIC_ID_IGMP_V2_LEAVE = 36,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_QUERY = 37,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_REPORT = 38,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V2_REPORT = 39,\n\tDEVLINK_TRAP_GENERIC_ID_MLD_V1_DONE = 40,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_DHCP = 41,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DHCP = 42,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_REQUEST = 43,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_RESPONSE = 44,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_OVERLAY = 45,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_SOLICIT = 46,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_NEIGH_ADVERT = 47,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BFD = 48,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BFD = 49,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_OSPF = 50,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_OSPF = 51,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_BGP = 52,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_BGP = 53,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_VRRP = 54,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_VRRP = 55,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_PIM = 56,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_PIM = 57,\n\tDEVLINK_TRAP_GENERIC_ID_UC_LB = 58,\n\tDEVLINK_TRAP_GENERIC_ID_LOCAL_ROUTE = 59,\n\tDEVLINK_TRAP_GENERIC_ID_EXTERNAL_ROUTE = 60,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_UC_DIP_LINK_LOCAL_SCOPE = 61,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_NODES = 62,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_DIP_ALL_ROUTERS = 63,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_SOLICIT = 64,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ADVERT = 65,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_REDIRECT = 66,\n\tDEVLINK_TRAP_GENERIC_ID_IPV4_ROUTER_ALERT = 67,\n\tDEVLINK_TRAP_GENERIC_ID_IPV6_ROUTER_ALERT = 68,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_EVENT = 69,\n\tDEVLINK_TRAP_GENERIC_ID_PTP_GENERAL = 70,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_SAMPLE = 71,\n\tDEVLINK_TRAP_GENERIC_ID_FLOW_ACTION_TRAP = 72,\n\tDEVLINK_TRAP_GENERIC_ID_EARLY_DROP = 73,\n\tDEVLINK_TRAP_GENERIC_ID_VXLAN_PARSING = 74,\n\tDEVLINK_TRAP_GENERIC_ID_LLC_SNAP_PARSING = 75,\n\tDEVLINK_TRAP_GENERIC_ID_VLAN_PARSING = 76,\n\tDEVLINK_TRAP_GENERIC_ID_PPPOE_PPP_PARSING = 77,\n\tDEVLINK_TRAP_GENERIC_ID_MPLS_PARSING = 78,\n\tDEVLINK_TRAP_GENERIC_ID_ARP_PARSING = 79,\n\tDEVLINK_TRAP_GENERIC_ID_IP_1_PARSING = 80,\n\tDEVLINK_TRAP_GENERIC_ID_IP_N_PARSING = 81,\n\tDEVLINK_TRAP_GENERIC_ID_GRE_PARSING = 82,\n\tDEVLINK_TRAP_GENERIC_ID_UDP_PARSING = 83,\n\tDEVLINK_TRAP_GENERIC_ID_TCP_PARSING = 84,\n\tDEVLINK_TRAP_GENERIC_ID_IPSEC_PARSING = 85,\n\tDEVLINK_TRAP_GENERIC_ID_SCTP_PARSING = 86,\n\tDEVLINK_TRAP_GENERIC_ID_DCCP_PARSING = 87,\n\tDEVLINK_TRAP_GENERIC_ID_GTP_PARSING = 88,\n\tDEVLINK_TRAP_GENERIC_ID_ESP_PARSING = 89,\n\tDEVLINK_TRAP_GENERIC_ID_BLACKHOLE_NEXTHOP = 90,\n\tDEVLINK_TRAP_GENERIC_ID_DMAC_FILTER = 91,\n\tDEVLINK_TRAP_GENERIC_ID_EAPOL = 92,\n\tDEVLINK_TRAP_GENERIC_ID_LOCKED_PORT = 93,\n\t__DEVLINK_TRAP_GENERIC_ID_MAX = 94,\n\tDEVLINK_TRAP_GENERIC_ID_MAX = 93,\n};\n\nenum devlink_trap_group_generic_id {\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L2_DROPS = 0,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_DROPS = 1,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_L3_EXCEPTIONS = 2,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BUFFER_DROPS = 3,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_TUNNEL_DROPS = 4,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_DROPS = 5,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_STP = 6,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LACP = 7,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LLDP = 8,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MC_SNOOPING = 9,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_DHCP = 10,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_NEIGH_DISCOVERY = 11,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BFD = 12,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_OSPF = 13,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_BGP = 14,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_VRRP = 15,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PIM = 16,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_UC_LB = 17,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_LOCAL_DELIVERY = 18,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EXTERNAL_DELIVERY = 19,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_IPV6 = 20,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_EVENT = 21,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PTP_GENERAL = 22,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_SAMPLE = 23,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_ACL_TRAP = 24,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_PARSER_ERROR_DROPS = 25,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_EAPOL = 26,\n\t__DEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 27,\n\tDEVLINK_TRAP_GROUP_GENERIC_ID_MAX = 26,\n};\n\nenum devlink_trap_type {\n\tDEVLINK_TRAP_TYPE_DROP = 0,\n\tDEVLINK_TRAP_TYPE_EXCEPTION = 1,\n\tDEVLINK_TRAP_TYPE_CONTROL = 2,\n};\n\nenum devlink_var_attr_type {\n\tDEVLINK_VAR_ATTR_TYPE_U8 = 1,\n\tDEVLINK_VAR_ATTR_TYPE_U16 = 2,\n\tDEVLINK_VAR_ATTR_TYPE_U32 = 3,\n\tDEVLINK_VAR_ATTR_TYPE_U64 = 4,\n\tDEVLINK_VAR_ATTR_TYPE_STRING = 5,\n\tDEVLINK_VAR_ATTR_TYPE_FLAG = 6,\n\tDEVLINK_VAR_ATTR_TYPE_NUL_STRING = 10,\n\tDEVLINK_VAR_ATTR_TYPE_BINARY = 11,\n\t__DEVLINK_VAR_ATTR_TYPE_CUSTOM_BASE = 128,\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n\tDEVM_IOREMAP_NP = 3,\n};\n\nenum die_val {\n\tDIE_OOPS = 1,\n\tDIE_IABR_MATCH = 2,\n\tDIE_DABR_MATCH = 3,\n\tDIE_BPT = 4,\n\tDIE_SSTEP = 5,\n};\n\nenum digest_type {\n\tDIGEST_TYPE_IMA = 0,\n\tDIGEST_TYPE_VERITY = 1,\n\tDIGEST_TYPE__LAST = 2,\n};\n\nenum dim_cq_period_mode {\n\tDIM_CQ_PERIOD_MODE_START_FROM_EQE = 0,\n\tDIM_CQ_PERIOD_MODE_START_FROM_CQE = 1,\n\tDIM_CQ_PERIOD_NUM_MODES = 2,\n};\n\nenum dim_state {\n\tDIM_START_MEASURE = 0,\n\tDIM_MEASURE_IN_PROGRESS = 1,\n\tDIM_APPLY_NEW_PROFILE = 2,\n};\n\nenum dim_stats_state {\n\tDIM_STATS_WORSE = 0,\n\tDIM_STATS_SAME = 1,\n\tDIM_STATS_BETTER = 2,\n};\n\nenum dim_step_result {\n\tDIM_STEPPED = 0,\n\tDIM_TOO_TIRED = 1,\n\tDIM_ON_EDGE = 2,\n};\n\nenum dim_tune_state {\n\tDIM_PARKING_ON_TOP = 0,\n\tDIM_PARKING_TIRED = 1,\n\tDIM_GOING_RIGHT = 2,\n\tDIM_GOING_LEFT = 3,\n};\n\nenum dl_bw_request {\n\tdl_bw_req_deactivate = 0,\n\tdl_bw_req_alloc = 1,\n\tdl_bw_req_free = 2,\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nenum dl_param {\n\tDL_RUNTIME = 0,\n\tDL_PERIOD = 1,\n};\n\nenum dm_io_mem_type {\n\tDM_IO_PAGE_LIST = 0,\n\tDM_IO_BIO = 1,\n\tDM_IO_VMA = 2,\n\tDM_IO_KMEM = 3,\n};\n\nenum dm_queue_mode {\n\tDM_TYPE_NONE = 0,\n\tDM_TYPE_BIO_BASED = 1,\n\tDM_TYPE_REQUEST_BASED = 2,\n\tDM_TYPE_DAX_BIO_BASED = 3,\n};\n\nenum dm_uevent_type {\n\tDM_UEVENT_PATH_FAILED = 0,\n\tDM_UEVENT_PATH_REINSTATED = 1,\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n\tDMA_PREP_REPEAT = 256,\n\tDMA_PREP_LOAD_EOT = 512,\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SEQNO64_BIT = 0,\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 1,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 2,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 3,\n\tDMA_FENCE_FLAG_USER_BITS = 4,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nenum dma_resv_usage {\n\tDMA_RESV_USAGE_KERNEL = 0,\n\tDMA_RESV_USAGE_WRITE = 1,\n\tDMA_RESV_USAGE_READ = 2,\n\tDMA_RESV_USAGE_BOOKKEEP = 3,\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n\tDMA_SLAVE_BUSWIDTH_128_BYTES = 128,\n};\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n\tDMA_OUT_OF_ORDER = 4,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_COMPLETION_NO_ORDER = 13,\n\tDMA_REPEAT = 14,\n\tDMA_LOAD_EOT = 15,\n\tDMA_TX_TYPE_END = 16,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n\tDMAENGINE_ALIGN_128_BYTES = 7,\n\tDMAENGINE_ALIGN_256_BYTES = 8,\n};\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum dns_lookup_status {\n\tDNS_LOOKUP_NOT_DONE = 0,\n\tDNS_LOOKUP_GOOD = 1,\n\tDNS_LOOKUP_GOOD_WITH_BAD = 2,\n\tDNS_LOOKUP_BAD = 3,\n\tDNS_LOOKUP_GOT_NOT_FOUND = 4,\n\tDNS_LOOKUP_GOT_LOCAL_FAILURE = 5,\n\tDNS_LOOKUP_GOT_TEMP_FAILURE = 6,\n\tDNS_LOOKUP_GOT_NS_FAILURE = 7,\n\tNR__dns_lookup_status = 8,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nenum ds_type {\n\tunknown_ds_type = 0,\n\tds_1307 = 1,\n\tds_1308 = 2,\n\tds_1337 = 3,\n\tds_1338 = 4,\n\tds_1339 = 5,\n\tds_1340 = 6,\n\tds_1341 = 7,\n\tds_1388 = 8,\n\tds_3231 = 9,\n\tm41t0 = 10,\n\tm41t00 = 11,\n\tm41t11 = 12,\n\tmcp794xx = 13,\n\trx_8025 = 14,\n\trx_8130 = 15,\n\tlast_ds_type = 16,\n};\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok___2 = 0,\n\te1000_1000t_rx_status_ok___2 = 1,\n\te1000_1000t_rx_status_undefined___2 = 255,\n};\n\nenum e1000_boards {\n\tboard_82571 = 0,\n\tboard_82572 = 1,\n\tboard_82573 = 2,\n\tboard_82574 = 3,\n\tboard_82583 = 4,\n\tboard_80003es2lan = 5,\n\tboard_ich8lan = 6,\n\tboard_ich9lan = 7,\n\tboard_ich10lan = 8,\n\tboard_pchlan = 9,\n\tboard_pch2lan = 10,\n\tboard_pch_lpt = 11,\n\tboard_pch_spt = 12,\n\tboard_pch_cnp = 13,\n\tboard_pch_tgp = 14,\n\tboard_pch_adp = 15,\n\tboard_pch_mtp = 16,\n\tboard_pch_ptp = 17,\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown___2 = 0,\n\te1000_bus_width_pcie_x1 = 1,\n\te1000_bus_width_pcie_x2 = 2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32___2 = 9,\n\te1000_bus_width_64___2 = 10,\n\te1000_bus_width_reserved___2 = 11,\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause = 1,\n\te1000_fc_tx_pause = 2,\n\te1000_fc_full = 3,\n\te1000_fc_default = 255,\n};\n\nenum e1000_mac_type {\n\te1000_82571 = 0,\n\te1000_82572 = 1,\n\te1000_82573 = 2,\n\te1000_82574 = 3,\n\te1000_82583 = 4,\n\te1000_80003es2lan = 5,\n\te1000_ich8lan = 6,\n\te1000_ich9lan = 7,\n\te1000_ich10lan = 8,\n\te1000_pchlan = 9,\n\te1000_pch2lan = 10,\n\te1000_pch_lpt = 11,\n\te1000_pch_spt = 12,\n\te1000_pch_cnp = 13,\n\te1000_pch_tgp = 14,\n\te1000_pch_adp = 15,\n\te1000_pch_mtp = 16,\n\te1000_pch_lnp = 17,\n\te1000_pch_ptp = 18,\n\te1000_pch_nvp = 19,\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper___2 = 1,\n\te1000_media_type_fiber___2 = 2,\n\te1000_media_type_internal_serdes___2 = 3,\n\te1000_num_media_types___2 = 4,\n};\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf = 1,\n\te1000_mng_mode_pt = 2,\n\te1000_mng_mode_ipmi = 3,\n\te1000_mng_mode_host_if_only = 4,\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default___2 = 0,\n\te1000_ms_force_master___2 = 1,\n\te1000_ms_force_slave___2 = 2,\n\te1000_ms_auto___2 = 3,\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small = 1,\n\te1000_nvm_override_spi_large = 2,\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none = 1,\n\te1000_nvm_eeprom_spi = 2,\n\te1000_nvm_flash_hw = 3,\n\te1000_nvm_flash_sw = 4,\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none = 1,\n\te1000_phy_m88___2 = 2,\n\te1000_phy_igp___2 = 3,\n\te1000_phy_igp_2 = 4,\n\te1000_phy_gg82563 = 5,\n\te1000_phy_igp_3 = 6,\n\te1000_phy_ife = 7,\n\te1000_phy_bm = 8,\n\te1000_phy_82578 = 9,\n\te1000_phy_82577 = 10,\n\te1000_phy_82579 = 11,\n\te1000_phy_i217 = 12,\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal___2 = 0,\n\te1000_rev_polarity_reversed___2 = 1,\n\te1000_rev_polarity_undefined___2 = 255,\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress = 1,\n\te1000_serdes_link_autoneg_complete = 2,\n\te1000_serdes_link_forced_up = 3,\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default___2 = 0,\n\te1000_smart_speed_on___2 = 1,\n\te1000_smart_speed_off___2 = 2,\n};\n\nenum e1000_state_t {\n\t__E1000_TESTING = 0,\n\t__E1000_RESETTING = 1,\n\t__E1000_ACCESS_SHARED_RESOURCE = 2,\n\t__E1000_DOWN = 3,\n};\n\nenum e1000_state_t___2 {\n\t__E1000_TESTING___2 = 0,\n\t__E1000_RESETTING___2 = 1,\n\t__E1000_DOWN___2 = 2,\n\t__E1000_DISABLED = 3,\n};\n\nenum e1000_ulp_state {\n\te1000_ulp_state_unknown = 0,\n\te1000_ulp_state_off = 1,\n\te1000_ulp_state_on = 2,\n};\n\nenum edac_dev_feat {\n\tRAS_FEAT_SCRUB = 0,\n\tRAS_FEAT_ECS = 1,\n\tRAS_FEAT_MEM_REPAIR = 2,\n\tRAS_FEAT_MAX = 3,\n};\n\nenum edac_mc_layer_type {\n\tEDAC_MC_LAYER_BRANCH = 0,\n\tEDAC_MC_LAYER_CHANNEL = 1,\n\tEDAC_MC_LAYER_SLOT = 2,\n\tEDAC_MC_LAYER_CHIP_SELECT = 3,\n\tEDAC_MC_LAYER_ALL_MEM = 4,\n};\n\nenum edac_type {\n\tEDAC_UNKNOWN = 0,\n\tEDAC_NONE = 1,\n\tEDAC_RESERVED = 2,\n\tEDAC_PARITY = 3,\n\tEDAC_EC = 4,\n\tEDAC_SECDED = 5,\n\tEDAC_S2ECD2ED = 6,\n\tEDAC_S4ECD4ED = 7,\n\tEDAC_S8ECD8ED = 8,\n\tEDAC_S16ECD16ED = 9,\n};\n\nenum eeprom_cnfg_mdix {\n\teeprom_mdix_enabled = 128,\n};\n\nenum eeprom_config_asf {\n\teeprom_asf = 32768,\n\teeprom_gcl = 16384,\n};\n\nenum eeprom_ctrl_lo {\n\teesk = 1,\n\teecs = 2,\n\teedi = 4,\n\teedo = 8,\n};\n\nenum eeprom_id {\n\teeprom_id_wol = 32,\n};\n\nenum eeprom_offsets {\n\teeprom_cnfg_mdix = 3,\n\teeprom_phy_iface = 6,\n\teeprom_id = 10,\n\teeprom_config_asf = 13,\n\teeprom_smbus_addr = 144,\n};\n\nenum eeprom_op {\n\top_write = 5,\n\top_read = 6,\n\top_ewds = 16,\n\top_ewen = 19,\n};\n\nenum eeprom_phy_iface {\n\tNoSuchPhy = 0,\n\tI82553AB = 1,\n\tI82553C = 2,\n\tI82503 = 3,\n\tDP83840 = 4,\n\tS80C240 = 5,\n\tS80C24 = 6,\n\tI82555 = 7,\n\tDP83840A = 10,\n};\n\nenum ehci_hrtimer_event {\n\tEHCI_HRTIMER_POLL_ASS = 0,\n\tEHCI_HRTIMER_POLL_PSS = 1,\n\tEHCI_HRTIMER_POLL_DEAD = 2,\n\tEHCI_HRTIMER_UNLINK_INTR = 3,\n\tEHCI_HRTIMER_FREE_ITDS = 4,\n\tEHCI_HRTIMER_ACTIVE_UNLINK = 5,\n\tEHCI_HRTIMER_START_UNLINK_INTR = 6,\n\tEHCI_HRTIMER_ASYNC_UNLINKS = 7,\n\tEHCI_HRTIMER_IAA_WATCHDOG = 8,\n\tEHCI_HRTIMER_DISABLE_PERIODIC = 9,\n\tEHCI_HRTIMER_DISABLE_ASYNC = 10,\n\tEHCI_HRTIMER_IO_WATCHDOG = 11,\n\tEHCI_HRTIMER_NUM_EVENTS = 12,\n};\n\nenum ehci_rh_state {\n\tEHCI_RH_HALTED = 0,\n\tEHCI_RH_SUSPENDED = 1,\n\tEHCI_RH_RUNNING = 2,\n\tEHCI_RH_STOPPING = 3,\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nenum enable_type {\n\tundefined = -1,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nenum equalization_preset_type {\n\tEQ_PRESET_TYPE_8GTS = 0,\n\tEQ_PRESET_TYPE_16GTS = 1,\n\tEQ_PRESET_TYPE_32GTS = 2,\n\tEQ_PRESET_TYPE_64GTS = 3,\n\tEQ_PRESET_TYPE_MAX = 4,\n};\n\nenum error_detector {\n\tERROR_DETECTOR_KFENCE = 0,\n\tERROR_DETECTOR_KASAN = 1,\n\tERROR_DETECTOR_WARN = 2,\n};\n\nenum ethnl_sock_type {\n\tETHTOOL_SOCK_TYPE_MODULE_FW_FLASH = 0,\n};\n\nenum ethtool_c33_pse_admin_state {\n\tETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_c33_pse_ext_state {\n\tETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID = 2,\n\tETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE = 3,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED = 4,\n\tETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM = 5,\n\tETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED = 6,\n\tETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE = 7,\n\tETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE = 8,\n\tETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_error_condition {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON = 4,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS = 5,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF = 6,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN = 7,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE = 8,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP = 9,\n};\n\nenum ethtool_c33_pse_ext_substate_mr_pse_enable {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_option_detect_ted {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR = 2,\n};\n\nenum ethtool_c33_pse_ext_substate_option_vport_lim {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION = 3,\n};\n\nenum ethtool_c33_pse_ext_substate_ovld_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,\n};\n\nenum ethtool_c33_pse_ext_substate_power_not_available {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET = 2,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT = 3,\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT = 4,\n};\n\nenum ethtool_c33_pse_ext_substate_short_detected {\n\tETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,\n};\n\nenum ethtool_c33_pse_pw_d_status {\n\tETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5,\n\tETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6,\n\tETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7,\n};\n\nenum ethtool_cmis_cdb_cmd_id {\n\tETHTOOL_CMIS_CDB_CMD_QUERY_STATUS = 0,\n\tETHTOOL_CMIS_CDB_CMD_MODULE_FEATURES = 64,\n\tETHTOOL_CMIS_CDB_CMD_FW_MANAGMENT_FEATURES = 65,\n\tETHTOOL_CMIS_CDB_CMD_START_FW_DOWNLOAD = 257,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_LPL = 259,\n\tETHTOOL_CMIS_CDB_CMD_WRITE_FW_BLOCK_EPL = 260,\n\tETHTOOL_CMIS_CDB_CMD_COMPLETE_FW_DOWNLOAD = 263,\n\tETHTOOL_CMIS_CDB_CMD_RUN_FW_IMAGE = 265,\n\tETHTOOL_CMIS_CDB_CMD_COMMIT_FW_IMAGE = 266,\n};\n\nenum ethtool_fec_config_bits {\n\tETHTOOL_FEC_NONE_BIT = 0,\n\tETHTOOL_FEC_AUTO_BIT = 1,\n\tETHTOOL_FEC_OFF_BIT = 2,\n\tETHTOOL_FEC_RS_BIT = 3,\n\tETHTOOL_FEC_BASER_BIT = 4,\n\tETHTOOL_FEC_LLRS_BIT = 5,\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nenum ethtool_header_flags {\n\tETHTOOL_FLAG_COMPACT_BITSETS = 1,\n\tETHTOOL_FLAG_OMIT_REPLY = 2,\n\tETHTOOL_FLAG_STATS = 4,\n};\n\nenum ethtool_link_ext_state {\n\tETHTOOL_LINK_EXT_STATE_AUTONEG = 0,\n\tETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE = 1,\n\tETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH = 2,\n\tETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY = 3,\n\tETHTOOL_LINK_EXT_STATE_NO_CABLE = 4,\n\tETHTOOL_LINK_EXT_STATE_CABLE_ISSUE = 5,\n\tETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE = 6,\n\tETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE = 7,\n\tETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED = 8,\n\tETHTOOL_LINK_EXT_STATE_OVERHEAT = 9,\n\tETHTOOL_LINK_EXT_STATE_MODULE = 10,\n\tETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION = 11,\n\tETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN = 12,\n};\n\nenum ethtool_link_ext_substate_autoneg {\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE = 5,\n\tETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD = 6,\n};\n\nenum ethtool_link_ext_substate_bad_signal_integrity {\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS = 4,\n};\n\nenum ethtool_link_ext_substate_cable_issue {\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE = 2,\n};\n\nenum ethtool_link_ext_substate_link_logical_mismatch {\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED = 4,\n\tETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED = 5,\n};\n\nenum ethtool_link_ext_substate_link_training {\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT = 2,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY = 3,\n\tETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT = 4,\n};\n\nenum ethtool_link_ext_substate_module {\n\tETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1,\n};\n\nenum ethtool_link_medium {\n\tETHTOOL_LINK_MEDIUM_BASET = 0,\n\tETHTOOL_LINK_MEDIUM_BASEK = 1,\n\tETHTOOL_LINK_MEDIUM_BASES = 2,\n\tETHTOOL_LINK_MEDIUM_BASEC = 3,\n\tETHTOOL_LINK_MEDIUM_BASEL = 4,\n\tETHTOOL_LINK_MEDIUM_BASED = 5,\n\tETHTOOL_LINK_MEDIUM_BASEE = 6,\n\tETHTOOL_LINK_MEDIUM_BASEF = 7,\n\tETHTOOL_LINK_MEDIUM_BASEV = 8,\n\tETHTOOL_LINK_MEDIUM_BASEMLD = 9,\n\tETHTOOL_LINK_MEDIUM_NONE = 10,\n\t__ETHTOOL_LINK_MEDIUM_LAST = 11,\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\tETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,\n\tETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,\n\tETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,\n\tETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,\n\tETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,\n\tETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,\n\tETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,\n\tETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,\n\tETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,\n\tETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,\n\tETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,\n\tETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,\n\tETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,\n\tETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,\n\tETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,\n\tETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,\n\tETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,\n\tETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,\n\tETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,\n\tETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,\n\tETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,\n\tETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,\n\tETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,\n\tETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,\n\tETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,\n\tETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,\n\tETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,\n\tETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,\n\tETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,\n\tETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,\n\tETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,\n\tETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,\n\tETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,\n\tETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,\n\tETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,\n\tETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,\n\tETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,\n\tETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,\n\tETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,\n\tETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,\n\tETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,\n\tETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,\n\tETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,\n\tETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,\n\tETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,\n\tETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,\n\tETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,\n\tETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,\n\tETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,\n\tETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 125,\n};\n\nenum ethtool_mac_stats_src {\n\tETHTOOL_MAC_STATS_SRC_AGGREGATE = 0,\n\tETHTOOL_MAC_STATS_SRC_EMAC = 1,\n\tETHTOOL_MAC_STATS_SRC_PMAC = 2,\n};\n\nenum ethtool_mm_verify_status {\n\tETHTOOL_MM_VERIFY_STATUS_UNKNOWN = 0,\n\tETHTOOL_MM_VERIFY_STATUS_INITIAL = 1,\n\tETHTOOL_MM_VERIFY_STATUS_VERIFYING = 2,\n\tETHTOOL_MM_VERIFY_STATUS_SUCCEEDED = 3,\n\tETHTOOL_MM_VERIFY_STATUS_FAILED = 4,\n\tETHTOOL_MM_VERIFY_STATUS_DISABLED = 5,\n};\n\nenum ethtool_mmsv_event {\n\tETHTOOL_MMSV_LP_SENT_VERIFY_MPACKET = 0,\n\tETHTOOL_MMSV_LD_SENT_VERIFY_MPACKET = 1,\n\tETHTOOL_MMSV_LP_SENT_RESPONSE_MPACKET = 2,\n};\n\nenum ethtool_module_fw_flash_status {\n\tETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS = 2,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED = 3,\n\tETHTOOL_MODULE_FW_FLASH_STATUS_ERROR = 4,\n};\n\nenum ethtool_module_power_mode {\n\tETHTOOL_MODULE_POWER_MODE_LOW = 1,\n\tETHTOOL_MODULE_POWER_MODE_HIGH = 2,\n};\n\nenum ethtool_module_power_mode_policy {\n\tETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1,\n\tETHTOOL_MODULE_POWER_MODE_POLICY_AUTO = 2,\n};\n\nenum ethtool_mpacket {\n\tETHTOOL_MPACKET_VERIFY = 0,\n\tETHTOOL_MPACKET_RESPONSE = 1,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nenum ethtool_podl_pse_admin_state {\n\tETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED = 2,\n\tETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED = 3,\n};\n\nenum ethtool_podl_pse_pw_d_status {\n\tETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED = 2,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING = 3,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING = 4,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP = 5,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_IDLE = 6,\n\tETHTOOL_PODL_PSE_PW_D_STATUS_ERROR = 7,\n};\n\nenum ethtool_reset_flags {\n\tETH_RESET_MGMT = 1,\n\tETH_RESET_IRQ = 2,\n\tETH_RESET_DMA = 4,\n\tETH_RESET_FILTER = 8,\n\tETH_RESET_OFFLOAD = 16,\n\tETH_RESET_MAC = 32,\n\tETH_RESET_PHY = 64,\n\tETH_RESET_RAM = 128,\n\tETH_RESET_AP = 256,\n\tETH_RESET_DEDICATED = 65535,\n\tETH_RESET_ALL = 4294967295,\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_UDP_TUNNEL_TYPES = 15,\n\tETH_SS_STATS_STD = 16,\n\tETH_SS_STATS_ETH_PHY = 17,\n\tETH_SS_STATS_ETH_MAC = 18,\n\tETH_SS_STATS_ETH_CTRL = 19,\n\tETH_SS_STATS_RMON = 20,\n\tETH_SS_STATS_PHY = 21,\n\tETH_SS_TS_FLAGS = 22,\n\tETH_SS_COUNT = 23,\n};\n\nenum ethtool_supported_ring_param {\n\tETHTOOL_RING_USE_RX_BUF_LEN = 1,\n\tETHTOOL_RING_USE_CQE_SIZE = 2,\n\tETHTOOL_RING_USE_TX_PUSH = 4,\n\tETHTOOL_RING_USE_RX_PUSH = 8,\n\tETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16,\n\tETHTOOL_RING_USE_TCP_DATA_SPLIT = 32,\n\tETHTOOL_RING_USE_HDS_THRS = 64,\n};\n\nenum ethtool_tcp_data_split {\n\tETHTOOL_TCP_DATA_SPLIT_UNKNOWN = 0,\n\tETHTOOL_TCP_DATA_SPLIT_DISABLED = 1,\n\tETHTOOL_TCP_DATA_SPLIT_ENABLED = 2,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n\tETT_EVENT_EPROBE = 64,\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_FROZEN = 8,\n\tEVENT_CPU = 16,\n\tEVENT_CGROUP = 32,\n\tEVENT_GUEST = 64,\n\tEVENT_FLAGS = 96,\n\tEVENT_ALL = 3,\n\tEVENT_TIME_FROZEN = 12,\n};\n\nenum evm_ima_xattr_type {\n\tIMA_XATTR_DIGEST = 1,\n\tEVM_XATTR_HMAC = 2,\n\tEVM_IMA_XATTR_DIGSIG = 3,\n\tIMA_XATTR_DIGEST_NG = 4,\n\tEVM_XATTR_PORTABLE_DIGSIG = 5,\n\tIMA_VERITY_DIGSIG = 6,\n\tIMA_XATTR_LAST = 7,\n};\n\nenum exact_level {\n\tNOT_EXACT = 0,\n\tEXACT = 1,\n\tRANGE_WITHIN = 2,\n};\n\nenum execmem_range_flags {\n\tEXECMEM_KASAN_SHADOW = 1,\n\tEXECMEM_ROX_CACHE = 2,\n};\n\nenum execmem_type {\n\tEXECMEM_DEFAULT = 0,\n\tEXECMEM_MODULE_TEXT = 0,\n\tEXECMEM_KPROBES = 1,\n\tEXECMEM_FTRACE = 2,\n\tEXECMEM_BPF = 3,\n\tEXECMEM_MODULE_DATA = 4,\n\tEXECMEM_TYPE_MAX = 5,\n};\n\nenum ext4_journal_trigger_type {\n\tEXT4_JTR_ORPHAN_FILE = 0,\n\tEXT4_JTR_NONE = 1,\n};\n\nenum ext4_li_mode {\n\tEXT4_LI_MODE_PREFETCH_BBITMAP = 0,\n\tEXT4_LI_MODE_ITABLE = 1,\n};\n\nenum fail_dup_mod_reason {\n\tFAIL_DUP_MOD_BECOMING = 0,\n\tFAIL_DUP_MOD_LOAD = 1,\n};\n\nenum fault_flag {\n\tFAULT_FLAG_WRITE = 1,\n\tFAULT_FLAG_MKWRITE = 2,\n\tFAULT_FLAG_ALLOW_RETRY = 4,\n\tFAULT_FLAG_RETRY_NOWAIT = 8,\n\tFAULT_FLAG_KILLABLE = 16,\n\tFAULT_FLAG_TRIED = 32,\n\tFAULT_FLAG_USER = 64,\n\tFAULT_FLAG_REMOTE = 128,\n\tFAULT_FLAG_INSTRUCTION = 256,\n\tFAULT_FLAG_INTERRUPTIBLE = 512,\n\tFAULT_FLAG_UNSHARE = 1024,\n\tFAULT_FLAG_ORIG_PTE_VALID = 2048,\n\tFAULT_FLAG_VMA_LOCK = 4096,\n};\n\nenum fault_flags {\n\tFAULT_NOWARN = 1,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum fc_fpin_congn_event_types {\n\tFPIN_CONGN_CLEAR = 0,\n\tFPIN_CONGN_LOST_CREDIT = 1,\n\tFPIN_CONGN_CREDIT_STALL = 2,\n\tFPIN_CONGN_OVERSUBSCRIPTION = 3,\n\tFPIN_CONGN_DEVICE_SPEC = 15,\n};\n\nenum fc_fpin_deli_event_types {\n\tFPIN_DELI_UNKNOWN = 0,\n\tFPIN_DELI_TIMEOUT = 1,\n\tFPIN_DELI_UNABLE_TO_ROUTE = 2,\n\tFPIN_DELI_DEVICE_SPEC = 15,\n};\n\nenum fc_fpin_li_event_types {\n\tFPIN_LI_UNKNOWN = 0,\n\tFPIN_LI_LINK_FAILURE = 1,\n\tFPIN_LI_LOSS_OF_SYNC = 2,\n\tFPIN_LI_LOSS_OF_SIG = 3,\n\tFPIN_LI_PRIM_SEQ_ERR = 4,\n\tFPIN_LI_INVALID_TX_WD = 5,\n\tFPIN_LI_INVALID_CRC = 6,\n\tFPIN_LI_DEVICE_SPEC = 15,\n};\n\nenum fc_host_event_code {\n\tFCH_EVT_LIP = 1,\n\tFCH_EVT_LINKUP = 2,\n\tFCH_EVT_LINKDOWN = 3,\n\tFCH_EVT_LIPRESET = 4,\n\tFCH_EVT_RSCN = 5,\n\tFCH_EVT_ADAPTER_CHANGE = 259,\n\tFCH_EVT_PORT_UNKNOWN = 512,\n\tFCH_EVT_PORT_OFFLINE = 513,\n\tFCH_EVT_PORT_ONLINE = 514,\n\tFCH_EVT_PORT_FABRIC = 516,\n\tFCH_EVT_LINK_UNKNOWN = 1280,\n\tFCH_EVT_LINK_FPIN = 1281,\n\tFCH_EVT_LINK_FPIN_ACK = 1282,\n\tFCH_EVT_VENDOR_UNIQUE = 65535,\n};\n\nenum fc_ls_tlv_dtag {\n\tELS_DTAG_LS_REQ_INFO = 1,\n\tELS_DTAG_LNK_FAULT_CAP = 65549,\n\tELS_DTAG_CG_SIGNAL_CAP = 65551,\n\tELS_DTAG_LNK_INTEGRITY = 131073,\n\tELS_DTAG_DELIVERY = 131074,\n\tELS_DTAG_PEER_CONGEST = 131075,\n\tELS_DTAG_CONGESTION = 131076,\n\tELS_DTAG_FPIN_REGISTER = 196609,\n};\n\nenum fc_port_state {\n\tFC_PORTSTATE_UNKNOWN = 0,\n\tFC_PORTSTATE_NOTPRESENT = 1,\n\tFC_PORTSTATE_ONLINE = 2,\n\tFC_PORTSTATE_OFFLINE = 3,\n\tFC_PORTSTATE_BLOCKED = 4,\n\tFC_PORTSTATE_BYPASSED = 5,\n\tFC_PORTSTATE_DIAGNOSTICS = 6,\n\tFC_PORTSTATE_LINKDOWN = 7,\n\tFC_PORTSTATE_ERROR = 8,\n\tFC_PORTSTATE_LOOPBACK = 9,\n\tFC_PORTSTATE_DELETED = 10,\n\tFC_PORTSTATE_MARGINAL = 11,\n};\n\nenum fc_port_type {\n\tFC_PORTTYPE_UNKNOWN = 0,\n\tFC_PORTTYPE_OTHER = 1,\n\tFC_PORTTYPE_NOTPRESENT = 2,\n\tFC_PORTTYPE_NPORT = 3,\n\tFC_PORTTYPE_NLPORT = 4,\n\tFC_PORTTYPE_LPORT = 5,\n\tFC_PORTTYPE_PTP = 6,\n\tFC_PORTTYPE_NPIV = 7,\n};\n\nenum fc_tgtid_binding_type {\n\tFC_TGTID_BIND_NONE = 0,\n\tFC_TGTID_BIND_BY_WWPN = 1,\n\tFC_TGTID_BIND_BY_WWNN = 2,\n\tFC_TGTID_BIND_BY_ID = 3,\n};\n\nenum fc_vport_state {\n\tFC_VPORT_UNKNOWN = 0,\n\tFC_VPORT_ACTIVE = 1,\n\tFC_VPORT_DISABLED = 2,\n\tFC_VPORT_LINKDOWN = 3,\n\tFC_VPORT_INITIALIZING = 4,\n\tFC_VPORT_NO_FABRIC_SUPP = 5,\n\tFC_VPORT_NO_FABRIC_RSCS = 6,\n\tFC_VPORT_FABRIC_LOGOUT = 7,\n\tFC_VPORT_FABRIC_REJ_WWN = 8,\n\tFC_VPORT_FAILED = 9,\n};\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_EDATA = 10,\n\tFETCH_OP_DEREF = 11,\n\tFETCH_OP_UDEREF = 12,\n\tFETCH_OP_ST_RAW = 13,\n\tFETCH_OP_ST_MEM = 14,\n\tFETCH_OP_ST_UMEM = 15,\n\tFETCH_OP_ST_STRING = 16,\n\tFETCH_OP_ST_USTRING = 17,\n\tFETCH_OP_ST_SYMSTR = 18,\n\tFETCH_OP_ST_EDATA = 19,\n\tFETCH_OP_MOD_BF = 20,\n\tFETCH_OP_LP_ARRAY = 21,\n\tFETCH_OP_TP_ARG = 22,\n\tFETCH_OP_END = 23,\n\tFETCH_NOP_SYMBOL = 24,\n};\n\nenum fib6_walk_state {\n\tFWS_L = 0,\n\tFWS_R = 1,\n\tFWS_C = 2,\n\tFWS_U = 3,\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_INO64_GEN = 129,\n\tFILEID_INO64_GEN_PARENT = 130,\n\tFILEID_LUSTRE = 151,\n\tFILEID_BCACHEFS_WITHOUT_PARENT = 177,\n\tFILEID_BCACHEFS_WITH_PARENT = 178,\n\tFILEID_NSFS = 241,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum filter_pred_fn {\n\tFILTER_PRED_FN_NOP = 0,\n\tFILTER_PRED_FN_64 = 1,\n\tFILTER_PRED_FN_64_CPUMASK = 2,\n\tFILTER_PRED_FN_S64 = 3,\n\tFILTER_PRED_FN_U64 = 4,\n\tFILTER_PRED_FN_32 = 5,\n\tFILTER_PRED_FN_32_CPUMASK = 6,\n\tFILTER_PRED_FN_S32 = 7,\n\tFILTER_PRED_FN_U32 = 8,\n\tFILTER_PRED_FN_16 = 9,\n\tFILTER_PRED_FN_16_CPUMASK = 10,\n\tFILTER_PRED_FN_S16 = 11,\n\tFILTER_PRED_FN_U16 = 12,\n\tFILTER_PRED_FN_8 = 13,\n\tFILTER_PRED_FN_8_CPUMASK = 14,\n\tFILTER_PRED_FN_S8 = 15,\n\tFILTER_PRED_FN_U8 = 16,\n\tFILTER_PRED_FN_COMM = 17,\n\tFILTER_PRED_FN_STRING = 18,\n\tFILTER_PRED_FN_STRLOC = 19,\n\tFILTER_PRED_FN_STRRELLOC = 20,\n\tFILTER_PRED_FN_PCHAR_USER = 21,\n\tFILTER_PRED_FN_PCHAR = 22,\n\tFILTER_PRED_FN_CPU = 23,\n\tFILTER_PRED_FN_CPU_CPUMASK = 24,\n\tFILTER_PRED_FN_CPUMASK = 25,\n\tFILTER_PRED_FN_CPUMASK_CPU = 26,\n\tFILTER_PRED_FN_FUNCTION = 27,\n\tFILTER_PRED_FN_ = 28,\n\tFILTER_PRED_TEST_VISITED = 29,\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nenum fixed_addresses {\n\tFIX_HOLE = 0,\n\t__end_of_permanent_fixed_addresses = 1,\n\tFIX_BTMAP_END = 1,\n\tFIX_BTMAP_BEGIN = 64,\n\t__end_of_fixed_addresses = 65,\n};\n\nenum flag_bits {\n\tFaulty = 0,\n\tIn_sync = 1,\n\tBitmap_sync = 2,\n\tWriteMostly = 3,\n\tAutoDetected = 4,\n\tBlocked = 5,\n\tWriteErrorSeen = 6,\n\tFaultRecorded = 7,\n\tBlockedBadBlocks = 8,\n\tWantReplacement = 9,\n\tReplacement = 10,\n\tCandidate = 11,\n\tJournal = 12,\n\tClusterRemove = 13,\n\tExternalBbl = 14,\n\tFailFast = 15,\n\tLastDev = 16,\n\tCollisionCheck = 17,\n\tNonrot = 18,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_RX_QUEUE_MAPPING = 19,\n\tFLOW_ACTION_WAKE = 20,\n\tFLOW_ACTION_QUEUE = 21,\n\tFLOW_ACTION_SAMPLE = 22,\n\tFLOW_ACTION_POLICE = 23,\n\tFLOW_ACTION_CT = 24,\n\tFLOW_ACTION_CT_METADATA = 25,\n\tFLOW_ACTION_MPLS_PUSH = 26,\n\tFLOW_ACTION_MPLS_POP = 27,\n\tFLOW_ACTION_MPLS_MANGLE = 28,\n\tFLOW_ACTION_GATE = 29,\n\tFLOW_ACTION_PPPOE_PUSH = 30,\n\tFLOW_ACTION_JUMP = 31,\n\tFLOW_ACTION_PIPE = 32,\n\tFLOW_ACTION_VLAN_PUSH_ETH = 33,\n\tFLOW_ACTION_VLAN_POP_ETH = 34,\n\tFLOW_ACTION_CONTINUE = 35,\n\tNUM_FLOW_ACTIONS = 36,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n\tFLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP = 3,\n\tFLOW_BLOCK_BINDER_TYPE_RED_MARK = 4,\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nenum flow_dissector_ctrl_flags {\n\tFLOW_DIS_IS_FRAGMENT = 1,\n\tFLOW_DIS_FIRST_FRAG = 2,\n\tFLOW_DIS_F_TUNNEL_CSUM = 4,\n\tFLOW_DIS_F_TUNNEL_DONT_FRAGMENT = 8,\n\tFLOW_DIS_F_TUNNEL_OAM = 16,\n\tFLOW_DIS_F_TUNNEL_CRIT_OPT = 32,\n\tFLOW_DIS_ENCAPSULATION = 64,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_HASH = 27,\n\tFLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28,\n\tFLOW_DISSECTOR_KEY_PPPOE = 29,\n\tFLOW_DISSECTOR_KEY_L2TPV3 = 30,\n\tFLOW_DISSECTOR_KEY_CFM = 31,\n\tFLOW_DISSECTOR_KEY_IPSEC = 32,\n\tFLOW_DISSECTOR_KEY_MAX = 33,\n};\n\nenum flowlabel_reflect {\n\tFLOWLABEL_REFLECT_ESTABLISHED = 1,\n\tFLOWLABEL_REFLECT_TCP_RESET = 2,\n\tFLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4,\n};\n\nenum folio_references {\n\tFOLIOREF_RECLAIM = 0,\n\tFOLIOREF_RECLAIM_CLEAN = 1,\n\tFOLIOREF_KEEP = 2,\n\tFOLIOREF_ACTIVATE = 3,\n};\n\nenum folio_walk_level {\n\tFW_LEVEL_PTE = 0,\n\tFW_LEVEL_PMD = 1,\n\tFW_LEVEL_PUD = 2,\n};\n\nenum format_state {\n\tFORMAT_STATE_NONE = 0,\n\tFORMAT_STATE_NUM = 1,\n\tFORMAT_STATE_WIDTH = 2,\n\tFORMAT_STATE_PRECISION = 3,\n\tFORMAT_STATE_CHAR = 4,\n\tFORMAT_STATE_STR = 5,\n\tFORMAT_STATE_PTR = 6,\n\tFORMAT_STATE_PERCENT_CHAR = 7,\n\tFORMAT_STATE_INVALID = 8,\n};\n\nenum freeze_holder {\n\tFREEZE_HOLDER_KERNEL = 1,\n\tFREEZE_HOLDER_USERSPACE = 2,\n\tFREEZE_MAY_NEST = 4,\n\tFREEZE_EXCL = 8,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_update_time {\n\tFS_UPD_ATIME = 0,\n\tFS_UPD_CMTIME = 1,\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n\tFSCONFIG_CMD_CREATE_EXCL = 8,\n};\n\nenum fserror_type {\n\tFSERR_BUFFERED_READ = 0,\n\tFSERR_BUFFERED_WRITE = 1,\n\tFSERR_DIRECTIO_READ = 2,\n\tFSERR_DIRECTIO_WRITE = 3,\n\tFSERR_DATA_LOST = 4,\n\tFSERR_METADATA = 5,\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_FILE_RANGE = 1,\n\tFSNOTIFY_EVENT_PATH = 2,\n\tFSNOTIFY_EVENT_INODE = 3,\n\tFSNOTIFY_EVENT_DENTRY = 4,\n\tFSNOTIFY_EVENT_MNT = 5,\n\tFSNOTIFY_EVENT_ERROR = 6,\n};\n\nenum fsnotify_group_prio {\n\tFSNOTIFY_PRIO_NORMAL = 0,\n\tFSNOTIFY_PRIO_CONTENT = 1,\n\tFSNOTIFY_PRIO_PRE_CONTENT = 2,\n\t__FSNOTIFY_PRIO_NUM = 3,\n};\n\nenum fsnotify_iter_type {\n\tFSNOTIFY_ITER_TYPE_INODE = 0,\n\tFSNOTIFY_ITER_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_ITER_TYPE_SB = 2,\n\tFSNOTIFY_ITER_TYPE_PARENT = 3,\n\tFSNOTIFY_ITER_TYPE_INODE2 = 4,\n\tFSNOTIFY_ITER_TYPE_MNTNS = 5,\n\tFSNOTIFY_ITER_TYPE_COUNT = 6,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_ANY = -1,\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_MNTNS = 3,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 4,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 4,\n};\n\nenum ftrace_bug_type {\n\tFTRACE_BUG_UNKNOWN = 0,\n\tFTRACE_BUG_INIT = 1,\n\tFTRACE_BUG_NOP = 2,\n\tFTRACE_BUG_CALL = 3,\n\tFTRACE_BUG_UPDATE = 4,\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n\tDUMP_PARAM = 3,\n};\n\nenum ftrace_ops_cmd {\n\tFTRACE_OPS_CMD_ENABLE_SHARE_IPMODIFY_SELF = 0,\n\tFTRACE_OPS_CMD_ENABLE_SHARE_IPMODIFY_PEER = 1,\n\tFTRACE_OPS_CMD_DISABLE_SHARE_IPMODIFY_PEER = 2,\n};\n\nenum fullness_group {\n\tZS_INUSE_RATIO_0 = 0,\n\tZS_INUSE_RATIO_10 = 1,\n\tZS_INUSE_RATIO_99 = 10,\n\tZS_INUSE_RATIO_100 = 11,\n\tNR_FULLNESS_GROUPS = 12,\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n\tFW_OPT_PARTIAL = 128,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nenum gddrnf4_status {\n\tGDD4_OK = 0,\n\tGDD4_UNAVAIL = 1,\n};\n\nenum gem_phy_type {\n\tphy_mii_mdio0 = 0,\n\tphy_mii_mdio1 = 1,\n\tphy_serialink = 2,\n\tphy_serdes = 3,\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nenum graph_filter_type {\n\tGRAPH_FILTER_NOTRACE = 0,\n\tGRAPH_FILTER_FUNCTION = 1,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_CONSUMED = 4,\n};\n\ntypedef enum gro_result gro_result_t;\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_smt_balance = 3,\n\tgroup_asym_packing = 4,\n\tgroup_imbalanced = 5,\n\tgroup_overloaded = 6,\n};\n\nenum gxt_cards {\n\tGXT4500P = 0,\n\tGXT6500P = 1,\n\tGXT4000P = 2,\n\tGXT6000P = 3,\n};\n\nenum handle_to_path_flags {\n\tHANDLE_CHECK_PERMS = 1,\n\tHANDLE_CHECK_SUBTREE = 2,\n};\n\nenum handshake_auth {\n\tHANDSHAKE_AUTH_UNSPEC = 0,\n\tHANDSHAKE_AUTH_UNAUTH = 1,\n\tHANDSHAKE_AUTH_PSK = 2,\n\tHANDSHAKE_AUTH_X509 = 3,\n};\n\nenum handshake_handler_class {\n\tHANDSHAKE_HANDLER_CLASS_NONE = 0,\n\tHANDSHAKE_HANDLER_CLASS_TLSHD = 1,\n\tHANDSHAKE_HANDLER_CLASS_MAX = 2,\n};\n\nenum handshake_msg_type {\n\tHANDSHAKE_MSG_TYPE_UNSPEC = 0,\n\tHANDSHAKE_MSG_TYPE_CLIENTHELLO = 1,\n\tHANDSHAKE_MSG_TYPE_SERVERHELLO = 2,\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO_SHA3_256 = 20,\n\tHASH_ALGO_SHA3_384 = 21,\n\tHASH_ALGO_SHA3_512 = 22,\n\tHASH_ALGO__LAST = 23,\n};\n\nenum hash_pointers_policy {\n\tHASH_PTR_AUTO = 0,\n\tHASH_PTR_ALWAYS = 1,\n\tHASH_PTR_NEVER = 2,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nenum header_fields {\n\tHDR_PCR = 0,\n\tHDR_DIGEST = 1,\n\tHDR_TEMPLATE_NAME = 2,\n\tHDR_TEMPLATE_DATA = 3,\n\tHDR__LAST = 4,\n};\n\nenum hid_class_request {\n\tHID_REQ_GET_REPORT = 1,\n\tHID_REQ_GET_IDLE = 2,\n\tHID_REQ_GET_PROTOCOL = 3,\n\tHID_REQ_SET_REPORT = 9,\n\tHID_REQ_SET_IDLE = 10,\n\tHID_REQ_SET_PROTOCOL = 11,\n};\n\nenum hid_report_type {\n\tHID_INPUT_REPORT = 0,\n\tHID_OUTPUT_REPORT = 1,\n\tHID_FEATURE_REPORT = 2,\n\tHID_REPORT_TYPES = 3,\n};\n\nenum hid_type {\n\tHID_TYPE_OTHER = 0,\n\tHID_TYPE_USBMOUSE = 1,\n\tHID_TYPE_USBNONE = 2,\n};\n\nenum hk_flags {\n\tHK_FLAG_DOMAIN_BOOT = 1,\n\tHK_FLAG_DOMAIN = 2,\n\tHK_FLAG_MANAGED_IRQ = 4,\n\tHK_FLAG_KERNEL_NOISE = 8,\n};\n\nenum hk_type {\n\tHK_TYPE_DOMAIN_BOOT = 0,\n\tHK_TYPE_DOMAIN = 1,\n\tHK_TYPE_MANAGED_IRQ = 2,\n\tHK_TYPE_KERNEL_NOISE = 3,\n\tHK_TYPE_MAX = 4,\n\tHK_TYPE_TICK = 3,\n\tHK_TYPE_TIMER = 3,\n\tHK_TYPE_RCU = 3,\n\tHK_TYPE_MISC = 3,\n\tHK_TYPE_WQ = 3,\n\tHK_TYPE_KTHREAD = 3,\n};\n\nenum hmm_pfn_flags {\n\tHMM_PFN_VALID = 9223372036854775808ULL,\n\tHMM_PFN_WRITE = 4611686018427387904ULL,\n\tHMM_PFN_ERROR = 2305843009213693952ULL,\n\tHMM_PFN_DMA_MAPPED = 1152921504606846976ULL,\n\tHMM_PFN_P2PDMA = 576460752303423488ULL,\n\tHMM_PFN_P2PDMA_BUS = 288230376151711744ULL,\n\tHMM_PFN_ORDER_SHIFT = 53ULL,\n\tHMM_PFN_REQ_FAULT = 9223372036854775808ULL,\n\tHMM_PFN_REQ_WRITE = 4611686018427387904ULL,\n\tHMM_PFN_FLAGS = 18437736874454810624ULL,\n};\n\nenum hn_flags_bits {\n\tHANDSHAKE_F_NET_DRAINING = 0,\n};\n\nenum hp_flags_bits {\n\tHANDSHAKE_F_PROTO_NOTIFY = 0,\n};\n\nenum hprobe_state {\n\tHPROBE_LEASED = 0,\n\tHPROBE_STABLE = 1,\n\tHPROBE_GONE = 2,\n\tHPROBE_CONSUMED = 3,\n};\n\nenum hr_flags_bits {\n\tHANDSHAKE_F_REQ_COMPLETED = 0,\n\tHANDSHAKE_F_REQ_SESSION = 1,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nenum hub_activation_type {\n\tHUB_INIT = 0,\n\tHUB_INIT2 = 1,\n\tHUB_INIT3 = 2,\n\tHUB_POST_RESET = 3,\n\tHUB_RESUME = 4,\n\tHUB_RESET_RESUME = 5,\n};\n\nenum hub_led_mode {\n\tINDICATOR_AUTO = 0,\n\tINDICATOR_CYCLE = 1,\n\tINDICATOR_GREEN_BLINK = 2,\n\tINDICATOR_GREEN_BLINK_OFF = 3,\n\tINDICATOR_AMBER_BLINK = 4,\n\tINDICATOR_AMBER_BLINK_OFF = 5,\n\tINDICATOR_ALT_BLINK = 6,\n\tINDICATOR_ALT_BLINK_OFF = 7,\n} __attribute__((mode(byte)));\n\nenum hub_quiescing_type {\n\tHUB_DISCONNECT = 0,\n\tHUB_PRE_RESET = 1,\n\tHUB_SUSPEND = 2,\n};\n\nenum hugetlb_memory_event {\n\tHUGETLB_MAX = 0,\n\tHUGETLB_NR_MEMORY_EVENTS = 1,\n};\n\nenum hugetlb_page_flags {\n\tHPG_restore_reserve = 0,\n\tHPG_migratable = 1,\n\tHPG_temporary = 2,\n\tHPG_freed = 3,\n\tHPG_vmemmap_optimized = 4,\n\tHPG_raw_hwp_unreliable = 5,\n\tHPG_cma = 6,\n\t__NR_HPAGEFLAGS = 7,\n};\n\nenum hugetlb_param {\n\tOpt_gid___6 = 0,\n\tOpt_min_size = 1,\n\tOpt_mode___5 = 2,\n\tOpt_nr_inodes = 3,\n\tOpt_pagesize = 4,\n\tOpt_size = 5,\n\tOpt_uid___6 = 6,\n};\n\nenum hugetlbfs_size_type {\n\tNO_SIZE = 0,\n\tSIZE_STD = 1,\n\tSIZE_PERCENT = 2,\n};\n\nenum hv_gpci_requests {\n\tHV_GPCI_dispatch_timebase_by_processor = 16,\n\tHV_GPCI_entitled_capped_uncapped_donated_idle_timebase_by_partition = 32,\n\tHV_GPCI_run_instructions_run_cycles_by_partition = 48,\n\tHV_GPCI_system_performance_capabilities = 64,\n\tHV_GPCI_processor_bus_utilization_abc_links = 80,\n\tHV_GPCI_processor_bus_utilization_wxyz_links = 96,\n\tHV_GPCI_processor_bus_utilization_gx_links = 112,\n\tHV_GPCI_processor_bus_utilization_mc_links = 128,\n\tHV_GPCI_processor_core_utilization = 148,\n\tHV_GPCI_partition_hypervisor_queuing_times = 224,\n\tHV_GPCI_system_hypervisor_times = 240,\n\tHV_GPCI_system_tlbie_count_and_time = 244,\n\tHV_GPCI_partition_instruction_count_and_time = 256,\n};\n\nenum hv_perf_domains {\n\tHV_PERF_DOMAIN_PHYS_CHIP = 1,\n\tHV_PERF_DOMAIN_PHYS_CORE = 2,\n\tHV_PERF_DOMAIN_VCPU_HOME_CORE = 3,\n\tHV_PERF_DOMAIN_VCPU_HOME_CHIP = 4,\n\tHV_PERF_DOMAIN_VCPU_HOME_NODE = 5,\n\tHV_PERF_DOMAIN_VCPU_REMOTE_NODE = 6,\n\tHV_PERF_DOMAIN_MAX = 7,\n};\n\nenum hv_protocol {\n\tHV_PROTOCOL_RAW = 0,\n\tHV_PROTOCOL_HVSI = 1,\n};\n\ntypedef enum hv_protocol hv_protocol_t;\n\nenum hvpipe_migrate_action {\n\tHVPIPE_SUSPEND = 0,\n\tHVPIPE_RESUME = 1,\n};\n\nenum hw_event_mc_err_type {\n\tHW_EVENT_ERR_CORRECTED = 0,\n\tHW_EVENT_ERR_UNCORRECTED = 1,\n\tHW_EVENT_ERR_DEFERRED = 2,\n\tHW_EVENT_ERR_FATAL = 3,\n\tHW_EVENT_ERR_INFO = 4,\n};\n\nenum hw_protection_action {\n\tHWPROT_ACT_DEFAULT = 0,\n\tHWPROT_ACT_SHUTDOWN = 1,\n\tHWPROT_ACT_REBOOT = 2,\n};\n\nenum hwerr_error_type {\n\tHWERR_RECOV_CPU = 0,\n\tHWERR_RECOV_MEMORY = 1,\n\tHWERR_RECOV_PCI = 2,\n\tHWERR_RECOV_CXL = 3,\n\tHWERR_RECOV_OTHERS = 4,\n\tHWERR_RECOV_MAX = 5,\n};\n\nenum hwmon_chip_attributes {\n\thwmon_chip_temp_reset_history = 0,\n\thwmon_chip_in_reset_history = 1,\n\thwmon_chip_curr_reset_history = 2,\n\thwmon_chip_power_reset_history = 3,\n\thwmon_chip_register_tz = 4,\n\thwmon_chip_update_interval = 5,\n\thwmon_chip_alarms = 6,\n\thwmon_chip_samples = 7,\n\thwmon_chip_curr_samples = 8,\n\thwmon_chip_in_samples = 9,\n\thwmon_chip_power_samples = 10,\n\thwmon_chip_temp_samples = 11,\n\thwmon_chip_beep_enable = 12,\n\thwmon_chip_pec = 13,\n};\n\nenum hwmon_curr_attributes {\n\thwmon_curr_enable = 0,\n\thwmon_curr_input = 1,\n\thwmon_curr_min = 2,\n\thwmon_curr_max = 3,\n\thwmon_curr_lcrit = 4,\n\thwmon_curr_crit = 5,\n\thwmon_curr_average = 6,\n\thwmon_curr_lowest = 7,\n\thwmon_curr_highest = 8,\n\thwmon_curr_reset_history = 9,\n\thwmon_curr_label = 10,\n\thwmon_curr_alarm = 11,\n\thwmon_curr_min_alarm = 12,\n\thwmon_curr_max_alarm = 13,\n\thwmon_curr_lcrit_alarm = 14,\n\thwmon_curr_crit_alarm = 15,\n\thwmon_curr_rated_min = 16,\n\thwmon_curr_rated_max = 17,\n\thwmon_curr_beep = 18,\n};\n\nenum hwmon_energy_attributes {\n\thwmon_energy_enable = 0,\n\thwmon_energy_input = 1,\n\thwmon_energy_label = 2,\n};\n\nenum hwmon_fan_attributes {\n\thwmon_fan_enable = 0,\n\thwmon_fan_input = 1,\n\thwmon_fan_label = 2,\n\thwmon_fan_min = 3,\n\thwmon_fan_max = 4,\n\thwmon_fan_div = 5,\n\thwmon_fan_pulses = 6,\n\thwmon_fan_target = 7,\n\thwmon_fan_alarm = 8,\n\thwmon_fan_min_alarm = 9,\n\thwmon_fan_max_alarm = 10,\n\thwmon_fan_fault = 11,\n\thwmon_fan_beep = 12,\n};\n\nenum hwmon_humidity_attributes {\n\thwmon_humidity_enable = 0,\n\thwmon_humidity_input = 1,\n\thwmon_humidity_label = 2,\n\thwmon_humidity_min = 3,\n\thwmon_humidity_min_hyst = 4,\n\thwmon_humidity_max = 5,\n\thwmon_humidity_max_hyst = 6,\n\thwmon_humidity_alarm = 7,\n\thwmon_humidity_fault = 8,\n\thwmon_humidity_rated_min = 9,\n\thwmon_humidity_rated_max = 10,\n\thwmon_humidity_min_alarm = 11,\n\thwmon_humidity_max_alarm = 12,\n};\n\nenum hwmon_in_attributes {\n\thwmon_in_enable = 0,\n\thwmon_in_input = 1,\n\thwmon_in_min = 2,\n\thwmon_in_max = 3,\n\thwmon_in_lcrit = 4,\n\thwmon_in_crit = 5,\n\thwmon_in_average = 6,\n\thwmon_in_lowest = 7,\n\thwmon_in_highest = 8,\n\thwmon_in_reset_history = 9,\n\thwmon_in_label = 10,\n\thwmon_in_alarm = 11,\n\thwmon_in_min_alarm = 12,\n\thwmon_in_max_alarm = 13,\n\thwmon_in_lcrit_alarm = 14,\n\thwmon_in_crit_alarm = 15,\n\thwmon_in_rated_min = 16,\n\thwmon_in_rated_max = 17,\n\thwmon_in_beep = 18,\n\thwmon_in_fault = 19,\n};\n\nenum hwmon_intrusion_attributes {\n\thwmon_intrusion_alarm = 0,\n\thwmon_intrusion_beep = 1,\n};\n\nenum hwmon_power_attributes {\n\thwmon_power_enable = 0,\n\thwmon_power_average = 1,\n\thwmon_power_average_interval = 2,\n\thwmon_power_average_interval_max = 3,\n\thwmon_power_average_interval_min = 4,\n\thwmon_power_average_highest = 5,\n\thwmon_power_average_lowest = 6,\n\thwmon_power_average_max = 7,\n\thwmon_power_average_min = 8,\n\thwmon_power_input = 9,\n\thwmon_power_input_highest = 10,\n\thwmon_power_input_lowest = 11,\n\thwmon_power_reset_history = 12,\n\thwmon_power_accuracy = 13,\n\thwmon_power_cap = 14,\n\thwmon_power_cap_hyst = 15,\n\thwmon_power_cap_max = 16,\n\thwmon_power_cap_min = 17,\n\thwmon_power_min = 18,\n\thwmon_power_max = 19,\n\thwmon_power_crit = 20,\n\thwmon_power_lcrit = 21,\n\thwmon_power_label = 22,\n\thwmon_power_alarm = 23,\n\thwmon_power_cap_alarm = 24,\n\thwmon_power_min_alarm = 25,\n\thwmon_power_max_alarm = 26,\n\thwmon_power_lcrit_alarm = 27,\n\thwmon_power_crit_alarm = 28,\n\thwmon_power_rated_min = 29,\n\thwmon_power_rated_max = 30,\n};\n\nenum hwmon_pwm_attributes {\n\thwmon_pwm_input = 0,\n\thwmon_pwm_enable = 1,\n\thwmon_pwm_mode = 2,\n\thwmon_pwm_freq = 3,\n\thwmon_pwm_auto_channels_temp = 4,\n};\n\nenum hwmon_sensor_types {\n\thwmon_chip = 0,\n\thwmon_temp = 1,\n\thwmon_in = 2,\n\thwmon_curr = 3,\n\thwmon_power = 4,\n\thwmon_energy = 5,\n\thwmon_energy64 = 6,\n\thwmon_humidity = 7,\n\thwmon_fan = 8,\n\thwmon_pwm = 9,\n\thwmon_intrusion = 10,\n\thwmon_max = 11,\n};\n\nenum hwmon_temp_attributes {\n\thwmon_temp_enable = 0,\n\thwmon_temp_input = 1,\n\thwmon_temp_type = 2,\n\thwmon_temp_lcrit = 3,\n\thwmon_temp_lcrit_hyst = 4,\n\thwmon_temp_min = 5,\n\thwmon_temp_min_hyst = 6,\n\thwmon_temp_max = 7,\n\thwmon_temp_max_hyst = 8,\n\thwmon_temp_crit = 9,\n\thwmon_temp_crit_hyst = 10,\n\thwmon_temp_emergency = 11,\n\thwmon_temp_emergency_hyst = 12,\n\thwmon_temp_alarm = 13,\n\thwmon_temp_lcrit_alarm = 14,\n\thwmon_temp_min_alarm = 15,\n\thwmon_temp_max_alarm = 16,\n\thwmon_temp_crit_alarm = 17,\n\thwmon_temp_emergency_alarm = 18,\n\thwmon_temp_fault = 19,\n\thwmon_temp_offset = 20,\n\thwmon_temp_label = 21,\n\thwmon_temp_lowest = 22,\n\thwmon_temp_highest = 23,\n\thwmon_temp_reset_history = 24,\n\thwmon_temp_rated_min = 25,\n\thwmon_temp_rated_max = 26,\n\thwmon_temp_beep = 27,\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nenum hwtstamp_flags {\n\tHWTSTAMP_FLAG_BONDED_PHC_INDEX = 1,\n\tHWTSTAMP_FLAG_LAST = 1,\n\tHWTSTAMP_FLAG_MASK = 1,\n};\n\nenum hwtstamp_provider_qualifier {\n\tHWTSTAMP_PROVIDER_QUALIFIER_PRECISE = 0,\n\tHWTSTAMP_PROVIDER_QUALIFIER_APPROX = 1,\n\tHWTSTAMP_PROVIDER_QUALIFIER_CNT = 2,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nenum hwtstamp_source {\n\tHWTSTAMP_SOURCE_NETDEV = 1,\n\tHWTSTAMP_SOURCE_PHYLIB = 2,\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nenum i8042_controller_reset_mode {\n\tI8042_RESET_NEVER = 0,\n\tI8042_RESET_ALWAYS = 1,\n\tI8042_RESET_ON_S2RAM = 2,\n};\n\nenum ib_atomic_cap {\n\tIB_ATOMIC_NONE = 0,\n\tIB_ATOMIC_HCA = 1,\n\tIB_ATOMIC_GLOB = 2,\n};\n\nenum ib_cq_notify_flags {\n\tIB_CQ_SOLICITED = 1,\n\tIB_CQ_NEXT_COMP = 2,\n\tIB_CQ_SOLICITED_MASK = 3,\n\tIB_CQ_REPORT_MISSED_EVENTS = 4,\n};\n\nenum ib_event_type {\n\tIB_EVENT_CQ_ERR = 0,\n\tIB_EVENT_QP_FATAL = 1,\n\tIB_EVENT_QP_REQ_ERR = 2,\n\tIB_EVENT_QP_ACCESS_ERR = 3,\n\tIB_EVENT_COMM_EST = 4,\n\tIB_EVENT_SQ_DRAINED = 5,\n\tIB_EVENT_PATH_MIG = 6,\n\tIB_EVENT_PATH_MIG_ERR = 7,\n\tIB_EVENT_DEVICE_FATAL = 8,\n\tIB_EVENT_PORT_ACTIVE = 9,\n\tIB_EVENT_PORT_ERR = 10,\n\tIB_EVENT_LID_CHANGE = 11,\n\tIB_EVENT_PKEY_CHANGE = 12,\n\tIB_EVENT_SM_CHANGE = 13,\n\tIB_EVENT_SRQ_ERR = 14,\n\tIB_EVENT_SRQ_LIMIT_REACHED = 15,\n\tIB_EVENT_QP_LAST_WQE_REACHED = 16,\n\tIB_EVENT_CLIENT_REREGISTER = 17,\n\tIB_EVENT_GID_CHANGE = 18,\n\tIB_EVENT_WQ_FATAL = 19,\n\tIB_EVENT_DEVICE_SPEED_CHANGE = 20,\n};\n\nenum ib_flow_action_type {\n\tIB_FLOW_ACTION_UNSPECIFIED = 0,\n\tIB_FLOW_ACTION_ESP = 1,\n};\n\nenum ib_flow_attr_type {\n\tIB_FLOW_ATTR_NORMAL = 0,\n\tIB_FLOW_ATTR_ALL_DEFAULT = 1,\n\tIB_FLOW_ATTR_MC_DEFAULT = 2,\n\tIB_FLOW_ATTR_SNIFFER = 3,\n};\n\nenum ib_flow_spec_type {\n\tIB_FLOW_SPEC_ETH = 32,\n\tIB_FLOW_SPEC_IB = 34,\n\tIB_FLOW_SPEC_IPV4 = 48,\n\tIB_FLOW_SPEC_IPV6 = 49,\n\tIB_FLOW_SPEC_ESP = 52,\n\tIB_FLOW_SPEC_TCP = 64,\n\tIB_FLOW_SPEC_UDP = 65,\n\tIB_FLOW_SPEC_VXLAN_TUNNEL = 80,\n\tIB_FLOW_SPEC_GRE = 81,\n\tIB_FLOW_SPEC_MPLS = 96,\n\tIB_FLOW_SPEC_INNER = 256,\n\tIB_FLOW_SPEC_ACTION_TAG = 4096,\n\tIB_FLOW_SPEC_ACTION_DROP = 4097,\n\tIB_FLOW_SPEC_ACTION_HANDLE = 4098,\n\tIB_FLOW_SPEC_ACTION_COUNT = 4099,\n};\n\nenum ib_gid_type {\n\tIB_GID_TYPE_IB = 0,\n\tIB_GID_TYPE_ROCE = 1,\n\tIB_GID_TYPE_ROCE_UDP_ENCAP = 2,\n\tIB_GID_TYPE_SIZE = 3,\n};\n\nenum ib_mig_state {\n\tIB_MIG_MIGRATED = 0,\n\tIB_MIG_REARM = 1,\n\tIB_MIG_ARMED = 2,\n};\n\nenum ib_mr_type {\n\tIB_MR_TYPE_MEM_REG = 0,\n\tIB_MR_TYPE_SG_GAPS = 1,\n\tIB_MR_TYPE_DM = 2,\n\tIB_MR_TYPE_USER = 3,\n\tIB_MR_TYPE_DMA = 4,\n\tIB_MR_TYPE_INTEGRITY = 5,\n};\n\nenum ib_mtu {\n\tIB_MTU_256 = 1,\n\tIB_MTU_512 = 2,\n\tIB_MTU_1024 = 3,\n\tIB_MTU_2048 = 4,\n\tIB_MTU_4096 = 5,\n};\n\nenum ib_mw_type {\n\tIB_MW_TYPE_1 = 1,\n\tIB_MW_TYPE_2 = 2,\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nenum ib_port_state {\n\tIB_PORT_NOP = 0,\n\tIB_PORT_DOWN = 1,\n\tIB_PORT_INIT = 2,\n\tIB_PORT_ARMED = 3,\n\tIB_PORT_ACTIVE = 4,\n\tIB_PORT_ACTIVE_DEFER = 5,\n};\n\nenum ib_qp_state {\n\tIB_QPS_RESET = 0,\n\tIB_QPS_INIT = 1,\n\tIB_QPS_RTR = 2,\n\tIB_QPS_RTS = 3,\n\tIB_QPS_SQD = 4,\n\tIB_QPS_SQE = 5,\n\tIB_QPS_ERR = 6,\n};\n\nenum ib_qp_type {\n\tIB_QPT_SMI = 0,\n\tIB_QPT_GSI = 1,\n\tIB_QPT_RC = 2,\n\tIB_QPT_UC = 3,\n\tIB_QPT_UD = 4,\n\tIB_QPT_RAW_IPV6 = 5,\n\tIB_QPT_RAW_ETHERTYPE = 6,\n\tIB_QPT_RAW_PACKET = 8,\n\tIB_QPT_XRC_INI = 9,\n\tIB_QPT_XRC_TGT = 10,\n\tIB_QPT_MAX = 11,\n\tIB_QPT_DRIVER = 255,\n\tIB_QPT_RESERVED1 = 4096,\n\tIB_QPT_RESERVED2 = 4097,\n\tIB_QPT_RESERVED3 = 4098,\n\tIB_QPT_RESERVED4 = 4099,\n\tIB_QPT_RESERVED5 = 4100,\n\tIB_QPT_RESERVED6 = 4101,\n\tIB_QPT_RESERVED7 = 4102,\n\tIB_QPT_RESERVED8 = 4103,\n\tIB_QPT_RESERVED9 = 4104,\n\tIB_QPT_RESERVED10 = 4105,\n};\n\nenum ib_sig_err_type {\n\tIB_SIG_BAD_GUARD = 0,\n\tIB_SIG_BAD_REFTAG = 1,\n\tIB_SIG_BAD_APPTAG = 2,\n};\n\nenum ib_sig_type {\n\tIB_SIGNAL_ALL_WR = 0,\n\tIB_SIGNAL_REQ_WR = 1,\n};\n\nenum ib_signature_type {\n\tIB_SIG_TYPE_NONE = 0,\n\tIB_SIG_TYPE_T10_DIF = 1,\n};\n\nenum ib_srq_attr_mask {\n\tIB_SRQ_MAX_WR = 1,\n\tIB_SRQ_LIMIT = 2,\n};\n\nenum ib_srq_type {\n\tIB_SRQT_BASIC = 0,\n\tIB_SRQT_XRC = 1,\n\tIB_SRQT_TM = 2,\n};\n\nenum ib_t10_dif_bg_type {\n\tIB_T10DIF_CRC = 0,\n\tIB_T10DIF_CSUM = 1,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_FLUSH_GLOBAL = 256,\n\tIB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_advise_mr_advice {\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1,\n\tIB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2,\n};\n\nenum ib_uverbs_device_cap_flags {\n\tIB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL,\n\tIB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL,\n\tIB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL,\n\tIB_UVERBS_DEVICE_RAW_MULTI = 8ULL,\n\tIB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL,\n\tIB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL,\n\tIB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL,\n\tIB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL,\n\tIB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL,\n\tIB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL,\n\tIB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL,\n\tIB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL,\n\tIB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL,\n\tIB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL,\n\tIB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL,\n\tIB_UVERBS_DEVICE_XRC = 1048576ULL,\n\tIB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL,\n\tIB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL,\n\tIB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL,\n\tIB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL,\n\tIB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL,\n\tIB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL,\n\tIB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL,\n\tIB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL,\n\tIB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL,\n\tIB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL,\n};\n\nenum ib_uverbs_gid_type {\n\tIB_UVERBS_GID_TYPE_IB = 0,\n\tIB_UVERBS_GID_TYPE_ROCE_V1 = 1,\n\tIB_UVERBS_GID_TYPE_ROCE_V2 = 2,\n};\n\nenum ib_uverbs_odp_general_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT = 1,\n\tIB_UVERBS_ODP_SUPPORT_IMPLICIT = 2,\n};\n\nenum ib_uverbs_odp_transport_cap_bits {\n\tIB_UVERBS_ODP_SUPPORT_SEND = 1,\n\tIB_UVERBS_ODP_SUPPORT_RECV = 2,\n\tIB_UVERBS_ODP_SUPPORT_WRITE = 4,\n\tIB_UVERBS_ODP_SUPPORT_READ = 8,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC = 16,\n\tIB_UVERBS_ODP_SUPPORT_SRQ_RECV = 32,\n\tIB_UVERBS_ODP_SUPPORT_FLUSH = 64,\n\tIB_UVERBS_ODP_SUPPORT_ATOMIC_WRITE = 128,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_raw_packet_caps {\n\tIB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2,\n\tIB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4,\n\tIB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wc_opcode {\n\tIB_UVERBS_WC_SEND = 0,\n\tIB_UVERBS_WC_RDMA_WRITE = 1,\n\tIB_UVERBS_WC_RDMA_READ = 2,\n\tIB_UVERBS_WC_COMP_SWAP = 3,\n\tIB_UVERBS_WC_FETCH_ADD = 4,\n\tIB_UVERBS_WC_BIND_MW = 5,\n\tIB_UVERBS_WC_LOCAL_INV = 6,\n\tIB_UVERBS_WC_TSO = 7,\n\tIB_UVERBS_WC_FLUSH = 8,\n\tIB_UVERBS_WC_ATOMIC_WRITE = 9,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_UVERBS_WR_FLUSH = 14,\n\tIB_UVERBS_WR_ATOMIC_WRITE = 15,\n};\n\nenum ib_wc_opcode {\n\tIB_WC_SEND = 0,\n\tIB_WC_RDMA_WRITE = 1,\n\tIB_WC_RDMA_READ = 2,\n\tIB_WC_COMP_SWAP = 3,\n\tIB_WC_FETCH_ADD = 4,\n\tIB_WC_BIND_MW = 5,\n\tIB_WC_LOCAL_INV = 6,\n\tIB_WC_LSO = 7,\n\tIB_WC_ATOMIC_WRITE = 9,\n\tIB_WC_REG_MR = 10,\n\tIB_WC_MASKED_COMP_SWAP = 11,\n\tIB_WC_MASKED_FETCH_ADD = 12,\n\tIB_WC_FLUSH = 8,\n\tIB_WC_RECV = 128,\n\tIB_WC_RECV_RDMA_WITH_IMM = 129,\n};\n\nenum ib_wc_status {\n\tIB_WC_SUCCESS = 0,\n\tIB_WC_LOC_LEN_ERR = 1,\n\tIB_WC_LOC_QP_OP_ERR = 2,\n\tIB_WC_LOC_EEC_OP_ERR = 3,\n\tIB_WC_LOC_PROT_ERR = 4,\n\tIB_WC_WR_FLUSH_ERR = 5,\n\tIB_WC_MW_BIND_ERR = 6,\n\tIB_WC_BAD_RESP_ERR = 7,\n\tIB_WC_LOC_ACCESS_ERR = 8,\n\tIB_WC_REM_INV_REQ_ERR = 9,\n\tIB_WC_REM_ACCESS_ERR = 10,\n\tIB_WC_REM_OP_ERR = 11,\n\tIB_WC_RETRY_EXC_ERR = 12,\n\tIB_WC_RNR_RETRY_EXC_ERR = 13,\n\tIB_WC_LOC_RDD_VIOL_ERR = 14,\n\tIB_WC_REM_INV_RD_REQ_ERR = 15,\n\tIB_WC_REM_ABORT_ERR = 16,\n\tIB_WC_INV_EECN_ERR = 17,\n\tIB_WC_INV_EEC_STATE_ERR = 18,\n\tIB_WC_FATAL_ERR = 19,\n\tIB_WC_RESP_TIMEOUT_ERR = 20,\n\tIB_WC_GENERAL_ERR = 21,\n};\n\nenum ib_wq_state {\n\tIB_WQS_RESET = 0,\n\tIB_WQS_RDY = 1,\n\tIB_WQS_ERR = 2,\n};\n\nenum ib_wq_type {\n\tIB_WQT_RQ = 0,\n};\n\nenum ib_wr_opcode {\n\tIB_WR_RDMA_WRITE = 0,\n\tIB_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_WR_SEND = 2,\n\tIB_WR_SEND_WITH_IMM = 3,\n\tIB_WR_RDMA_READ = 4,\n\tIB_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_WR_BIND_MW = 8,\n\tIB_WR_LSO = 10,\n\tIB_WR_SEND_WITH_INV = 9,\n\tIB_WR_RDMA_READ_WITH_INV = 11,\n\tIB_WR_LOCAL_INV = 7,\n\tIB_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n\tIB_WR_FLUSH = 14,\n\tIB_WR_ATOMIC_WRITE = 15,\n\tIB_WR_REG_MR = 32,\n\tIB_WR_REG_MR_INTEGRITY = 33,\n\tIB_WR_RESERVED1 = 240,\n\tIB_WR_RESERVED2 = 241,\n\tIB_WR_RESERVED3 = 242,\n\tIB_WR_RESERVED4 = 243,\n\tIB_WR_RESERVED5 = 244,\n\tIB_WR_RESERVED6 = 245,\n\tIB_WR_RESERVED7 = 246,\n\tIB_WR_RESERVED8 = 247,\n\tIB_WR_RESERVED9 = 248,\n\tIB_WR_RESERVED10 = 249,\n};\n\nenum ibmvscsi_host_action {\n\tIBMVSCSI_HOST_ACTION_NONE = 0,\n\tIBMVSCSI_HOST_ACTION_RESET = 1,\n\tIBMVSCSI_HOST_ACTION_REENABLE = 2,\n\tIBMVSCSI_HOST_ACTION_UNBLOCK = 3,\n};\n\nenum id_action {\n\tID_REMOVE = 0,\n\tID_ADD = 1,\n};\n\nenum idle_boot_override {\n\tIDLE_NO_OVERRIDE = 0,\n\tIDLE_POWERSAVE_OFF = 1,\n};\n\nenum ima_fs_flags {\n\tIMA_FS_BUSY = 0,\n};\n\nenum ima_hooks {\n\tNONE = 0,\n\tFILE_CHECK = 1,\n\tMMAP_CHECK = 2,\n\tMMAP_CHECK_REQPROT = 3,\n\tBPRM_CHECK = 4,\n\tCREDS_CHECK = 5,\n\tPOST_SETATTR = 6,\n\tMODULE_CHECK = 7,\n\tFIRMWARE_CHECK = 8,\n\tKEXEC_KERNEL_CHECK = 9,\n\tKEXEC_INITRAMFS_CHECK = 10,\n\tPOLICY_CHECK = 11,\n\tKEXEC_CMDLINE = 12,\n\tKEY_CHECK = 13,\n\tCRITICAL_DATA = 14,\n\tSETXATTR_CHECK = 15,\n\tMAX_CHECK = 16,\n};\n\nenum ima_show_type {\n\tIMA_SHOW_BINARY = 0,\n\tIMA_SHOW_BINARY_NO_FIELD_LEN = 1,\n\tIMA_SHOW_BINARY_OLD_STRING_FMT = 2,\n\tIMA_SHOW_ASCII = 3,\n};\n\nenum in6_addr_gen_mode {\n\tIN6_ADDR_GEN_MODE_EUI64 = 0,\n\tIN6_ADDR_GEN_MODE_NONE = 1,\n\tIN6_ADDR_GEN_MODE_STABLE_PRIVACY = 2,\n\tIN6_ADDR_GEN_MODE_RANDOM = 3,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n\tICSK_ACK_NOMEM = 32,\n};\n\nenum init_ns_id {\n\tIPC_NS_INIT_ID = 1,\n\tUTS_NS_INIT_ID = 2,\n\tUSER_NS_INIT_ID = 3,\n\tPID_NS_INIT_ID = 4,\n\tCGROUP_NS_INIT_ID = 5,\n\tTIME_NS_INIT_ID = 6,\n\tNET_NS_INIT_ID = 7,\n\tMNT_NS_INIT_ID = 8,\n\tNS_LAST_INIT_ID = 8,\n};\n\nenum init_ns_ino {\n\tIPC_NS_INIT_INO = 4026531839,\n\tUTS_NS_INIT_INO = 4026531838,\n\tUSER_NS_INIT_INO = 4026531837,\n\tPID_NS_INIT_INO = 4026531836,\n\tCGROUP_NS_INIT_INO = 4026531835,\n\tTIME_NS_INIT_INO = 4026531834,\n\tNET_NS_INIT_INO = 4026531833,\n\tMNT_NS_INIT_INO = 4026531832,\n\tMNT_NS_ANON_INO = 4026531831,\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nenum inode_state_bits {\n\t__I_NEW = 0,\n\t__I_SYNC = 1,\n\t__I_LRU_ISOLATING = 2,\n};\n\nenum inode_state_flags_enum {\n\tI_NEW = 1,\n\tI_SYNC = 2,\n\tI_LRU_ISOLATING = 4,\n\tI_DIRTY_SYNC = 16,\n\tI_DIRTY_DATASYNC = 32,\n\tI_DIRTY_PAGES = 64,\n\tI_WILL_FREE = 128,\n\tI_FREEING = 256,\n\tI_CLEAR = 512,\n\tI_REFERENCED = 1024,\n\tI_LINKABLE = 2048,\n\tI_DIRTY_TIME = 4096,\n\tI_WB_SWITCH = 8192,\n\tI_OVL_INUSE = 16384,\n\tI_CREATING = 32768,\n\tI_DONTCACHE = 65536,\n\tI_SYNC_QUEUED = 131072,\n\tI_PINNING_NETFS_WB = 262144,\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nenum instruction_type {\n\tCOMPUTE = 0,\n\tLOAD = 1,\n\tLOAD_MULTI = 2,\n\tLOAD_FP = 3,\n\tLOAD_VMX = 4,\n\tLOAD_VSX = 5,\n\tSTORE = 6,\n\tSTORE_MULTI = 7,\n\tSTORE_FP = 8,\n\tSTORE_VMX = 9,\n\tSTORE_VSX = 10,\n\tLARX = 11,\n\tSTCX = 12,\n\tBRANCH___2 = 13,\n\tMFSPR = 14,\n\tMTSPR = 15,\n\tCACHEOP = 16,\n\tBARRIER = 17,\n\tSYSCALL = 18,\n\tSYSCALL_VECTORED_0 = 19,\n\tMFMSR = 20,\n\tMTMSR = 21,\n\tRFI = 22,\n\tINTERRUPT = 23,\n\tUNKNOWN = 24,\n};\n\nenum integrity_status {\n\tINTEGRITY_PASS = 0,\n\tINTEGRITY_PASS_IMMUTABLE = 1,\n\tINTEGRITY_FAIL = 2,\n\tINTEGRITY_FAIL_IMMUTABLE = 3,\n\tINTEGRITY_NOLABEL = 4,\n\tINTEGRITY_NOXATTRS = 5,\n\tINTEGRITY_UNKNOWN = 6,\n};\n\nenum io_uring_cmd_flags {\n\tIO_URING_F_COMPLETE_DEFER = 1,\n\tIO_URING_F_UNLOCKED = 2,\n\tIO_URING_F_MULTISHOT = 4,\n\tIO_URING_F_IOWQ = 8,\n\tIO_URING_F_INLINE = 16,\n\tIO_URING_F_NONBLOCK = -2147483648,\n\tIO_URING_F_SQE128 = 256,\n\tIO_URING_F_CQE32 = 512,\n\tIO_URING_F_IOPOLL = 1024,\n\tIO_URING_F_CANCEL = 2048,\n\tIO_URING_F_COMPAT = 4096,\n};\n\nenum io_uring_msg_ring_flags {\n\tIORING_MSG_DATA = 0,\n\tIORING_MSG_SEND_FD = 1,\n};\n\nenum io_uring_napi_op {\n\tIO_URING_NAPI_REGISTER_OP = 0,\n\tIO_URING_NAPI_STATIC_ADD_ID = 1,\n\tIO_URING_NAPI_STATIC_DEL_ID = 2,\n};\n\nenum io_uring_napi_tracking_strategy {\n\tIO_URING_NAPI_TRACKING_DYNAMIC = 0,\n\tIO_URING_NAPI_TRACKING_STATIC = 1,\n\tIO_URING_NAPI_TRACKING_INACTIVE = 255,\n};\n\nenum io_uring_op {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_SHUTDOWN = 34,\n\tIORING_OP_RENAMEAT = 35,\n\tIORING_OP_UNLINKAT = 36,\n\tIORING_OP_MKDIRAT = 37,\n\tIORING_OP_SYMLINKAT = 38,\n\tIORING_OP_LINKAT = 39,\n\tIORING_OP_MSG_RING = 40,\n\tIORING_OP_FSETXATTR = 41,\n\tIORING_OP_SETXATTR = 42,\n\tIORING_OP_FGETXATTR = 43,\n\tIORING_OP_GETXATTR = 44,\n\tIORING_OP_SOCKET = 45,\n\tIORING_OP_URING_CMD = 46,\n\tIORING_OP_SEND_ZC = 47,\n\tIORING_OP_SENDMSG_ZC = 48,\n\tIORING_OP_READ_MULTISHOT = 49,\n\tIORING_OP_WAITID = 50,\n\tIORING_OP_FUTEX_WAIT = 51,\n\tIORING_OP_FUTEX_WAKE = 52,\n\tIORING_OP_FUTEX_WAITV = 53,\n\tIORING_OP_FIXED_FD_INSTALL = 54,\n\tIORING_OP_FTRUNCATE = 55,\n\tIORING_OP_BIND = 56,\n\tIORING_OP_LISTEN = 57,\n\tIORING_OP_RECV_ZC = 58,\n\tIORING_OP_EPOLL_WAIT = 59,\n\tIORING_OP_READV_FIXED = 60,\n\tIORING_OP_WRITEV_FIXED = 61,\n\tIORING_OP_PIPE = 62,\n\tIORING_OP_NOP128 = 63,\n\tIORING_OP_URING_CMD128 = 64,\n\tIORING_OP_LAST = 65,\n};\n\nenum io_uring_register_op {\n\tIORING_REGISTER_BUFFERS = 0,\n\tIORING_UNREGISTER_BUFFERS = 1,\n\tIORING_REGISTER_FILES = 2,\n\tIORING_UNREGISTER_FILES = 3,\n\tIORING_REGISTER_EVENTFD = 4,\n\tIORING_UNREGISTER_EVENTFD = 5,\n\tIORING_REGISTER_FILES_UPDATE = 6,\n\tIORING_REGISTER_EVENTFD_ASYNC = 7,\n\tIORING_REGISTER_PROBE = 8,\n\tIORING_REGISTER_PERSONALITY = 9,\n\tIORING_UNREGISTER_PERSONALITY = 10,\n\tIORING_REGISTER_RESTRICTIONS = 11,\n\tIORING_REGISTER_ENABLE_RINGS = 12,\n\tIORING_REGISTER_FILES2 = 13,\n\tIORING_REGISTER_FILES_UPDATE2 = 14,\n\tIORING_REGISTER_BUFFERS2 = 15,\n\tIORING_REGISTER_BUFFERS_UPDATE = 16,\n\tIORING_REGISTER_IOWQ_AFF = 17,\n\tIORING_UNREGISTER_IOWQ_AFF = 18,\n\tIORING_REGISTER_IOWQ_MAX_WORKERS = 19,\n\tIORING_REGISTER_RING_FDS = 20,\n\tIORING_UNREGISTER_RING_FDS = 21,\n\tIORING_REGISTER_PBUF_RING = 22,\n\tIORING_UNREGISTER_PBUF_RING = 23,\n\tIORING_REGISTER_SYNC_CANCEL = 24,\n\tIORING_REGISTER_FILE_ALLOC_RANGE = 25,\n\tIORING_REGISTER_PBUF_STATUS = 26,\n\tIORING_REGISTER_NAPI = 27,\n\tIORING_UNREGISTER_NAPI = 28,\n\tIORING_REGISTER_CLOCK = 29,\n\tIORING_REGISTER_CLONE_BUFFERS = 30,\n\tIORING_REGISTER_SEND_MSG_RING = 31,\n\tIORING_REGISTER_ZCRX_IFQ = 32,\n\tIORING_REGISTER_RESIZE_RINGS = 33,\n\tIORING_REGISTER_MEM_REGION = 34,\n\tIORING_REGISTER_QUERY = 35,\n\tIORING_REGISTER_ZCRX_CTRL = 36,\n\tIORING_REGISTER_BPF_FILTER = 37,\n\tIORING_REGISTER_LAST = 38,\n\tIORING_REGISTER_USE_REGISTERED_RING = 2147483648,\n};\n\nenum io_uring_register_pbuf_ring_flags {\n\tIOU_PBUF_RING_MMAP = 1,\n\tIOU_PBUF_RING_INC = 2,\n};\n\nenum io_uring_register_restriction_op {\n\tIORING_RESTRICTION_REGISTER_OP = 0,\n\tIORING_RESTRICTION_SQE_OP = 1,\n\tIORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2,\n\tIORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3,\n\tIORING_RESTRICTION_LAST = 4,\n};\n\nenum io_uring_socket_op {\n\tSOCKET_URING_OP_SIOCINQ = 0,\n\tSOCKET_URING_OP_SIOCOUTQ = 1,\n\tSOCKET_URING_OP_GETSOCKOPT = 2,\n\tSOCKET_URING_OP_SETSOCKOPT = 3,\n\tSOCKET_URING_OP_TX_TIMESTAMP = 4,\n\tSOCKET_URING_OP_GETSOCKNAME = 5,\n};\n\nenum io_uring_sqe_flags_bit {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n\tIOSQE_CQE_SKIP_SUCCESS_BIT = 6,\n};\n\nenum io_uring_zcrx_area_flags {\n\tIORING_ZCRX_AREA_DMABUF = 1,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\nenum io_wq_type {\n\tIO_WQ_BOUND = 0,\n\tIO_WQ_UNBOUND = 1,\n};\n\nenum ioam6_event_attr {\n\tIOAM6_EVENT_ATTR_UNSPEC = 0,\n\tIOAM6_EVENT_ATTR_TRACE_NAMESPACE = 1,\n\tIOAM6_EVENT_ATTR_TRACE_NODELEN = 2,\n\tIOAM6_EVENT_ATTR_TRACE_TYPE = 3,\n\tIOAM6_EVENT_ATTR_TRACE_DATA = 4,\n\t__IOAM6_EVENT_ATTR_MAX = 5,\n};\n\nenum ioam6_event_type {\n\tIOAM6_EVENT_UNSPEC = 0,\n\tIOAM6_EVENT_TRACE = 1,\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_NOEXEC = 1,\n\tIOMMU_CAP_PRE_BOOT_PROTECTION = 2,\n\tIOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3,\n\tIOMMU_CAP_DEFERRED_FLUSH = 4,\n\tIOMMU_CAP_DIRTY_TRACKING = 5,\n};\n\nenum iommu_domain_cookie_type {\n\tIOMMU_COOKIE_NONE = 0,\n\tIOMMU_COOKIE_DMA_IOVA = 1,\n\tIOMMU_COOKIE_DMA_MSI = 2,\n\tIOMMU_COOKIE_FAULT_HANDLER = 3,\n\tIOMMU_COOKIE_SVA = 4,\n\tIOMMU_COOKIE_IOMMUFD = 5,\n};\n\nenum iommu_hw_info_type {\n\tIOMMU_HW_INFO_TYPE_NONE = 0,\n\tIOMMU_HW_INFO_TYPE_DEFAULT = 0,\n\tIOMMU_HW_INFO_TYPE_INTEL_VTD = 1,\n\tIOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,\n\tIOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,\n\tIOMMU_HW_INFO_TYPE_AMD = 4,\n};\n\nenum iommu_hw_queue_type {\n\tIOMMU_HW_QUEUE_TYPE_DEFAULT = 0,\n\tIOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,\n};\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nenum iommu_viommu_type {\n\tIOMMU_VIOMMU_TYPE_DEFAULT = 0,\n\tIOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,\n\tIOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,\n};\n\nenum iommufd_hwpt_alloc_flags {\n\tIOMMU_HWPT_ALLOC_NEST_PARENT = 1,\n\tIOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2,\n\tIOMMU_HWPT_FAULT_ID_VALID = 4,\n\tIOMMU_HWPT_ALLOC_PASID = 8,\n};\n\nenum iommufd_object_type {\n\tIOMMUFD_OBJ_NONE = 0,\n\tIOMMUFD_OBJ_ANY = 0,\n\tIOMMUFD_OBJ_DEVICE = 1,\n\tIOMMUFD_OBJ_HWPT_PAGING = 2,\n\tIOMMUFD_OBJ_HWPT_NESTED = 3,\n\tIOMMUFD_OBJ_IOAS = 4,\n\tIOMMUFD_OBJ_ACCESS = 5,\n\tIOMMUFD_OBJ_FAULT = 6,\n\tIOMMUFD_OBJ_VIOMMU = 7,\n\tIOMMUFD_OBJ_VDEVICE = 8,\n\tIOMMUFD_OBJ_VEVENTQ = 9,\n\tIOMMUFD_OBJ_HW_QUEUE = 10,\n\tIOMMUFD_OBJ_MAX = 11,\n};\n\nenum ip6_defrag_users {\n\tIP6_DEFRAG_LOCAL_DELIVER = 0,\n\tIP6_DEFRAG_CONNTRACK_IN = 1,\n\t__IP6_DEFRAG_CONNTRACK_IN = 65536,\n\tIP6_DEFRAG_CONNTRACK_OUT = 65537,\n\t__IP6_DEFRAG_CONNTRACK_OUT = 131072,\n\tIP6_DEFRAG_CONNTRACK_BRIDGE_IN = 131073,\n\t__IP6_DEFRAG_CONNTRACK_BRIDGE_IN = 196608,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum ip_conntrack_info {\n\tIP_CT_ESTABLISHED = 0,\n\tIP_CT_RELATED = 1,\n\tIP_CT_NEW = 2,\n\tIP_CT_IS_REPLY = 3,\n\tIP_CT_ESTABLISHED_REPLY = 3,\n\tIP_CT_RELATED_REPLY = 4,\n\tIP_CT_NUMBER = 5,\n\tIP_CT_UNTRACKED = 7,\n};\n\nenum ip_conntrack_status {\n\tIPS_EXPECTED_BIT = 0,\n\tIPS_EXPECTED = 1,\n\tIPS_SEEN_REPLY_BIT = 1,\n\tIPS_SEEN_REPLY = 2,\n\tIPS_ASSURED_BIT = 2,\n\tIPS_ASSURED = 4,\n\tIPS_CONFIRMED_BIT = 3,\n\tIPS_CONFIRMED = 8,\n\tIPS_SRC_NAT_BIT = 4,\n\tIPS_SRC_NAT = 16,\n\tIPS_DST_NAT_BIT = 5,\n\tIPS_DST_NAT = 32,\n\tIPS_NAT_MASK = 48,\n\tIPS_SEQ_ADJUST_BIT = 6,\n\tIPS_SEQ_ADJUST = 64,\n\tIPS_SRC_NAT_DONE_BIT = 7,\n\tIPS_SRC_NAT_DONE = 128,\n\tIPS_DST_NAT_DONE_BIT = 8,\n\tIPS_DST_NAT_DONE = 256,\n\tIPS_NAT_DONE_MASK = 384,\n\tIPS_DYING_BIT = 9,\n\tIPS_DYING = 512,\n\tIPS_FIXED_TIMEOUT_BIT = 10,\n\tIPS_FIXED_TIMEOUT = 1024,\n\tIPS_TEMPLATE_BIT = 11,\n\tIPS_TEMPLATE = 2048,\n\tIPS_UNTRACKED_BIT = 12,\n\tIPS_UNTRACKED = 4096,\n\tIPS_NAT_CLASH_BIT = 12,\n\tIPS_NAT_CLASH = 4096,\n\tIPS_HELPER_BIT = 13,\n\tIPS_HELPER = 8192,\n\tIPS_OFFLOAD_BIT = 14,\n\tIPS_OFFLOAD = 16384,\n\tIPS_HW_OFFLOAD_BIT = 15,\n\tIPS_HW_OFFLOAD = 32768,\n\tIPS_UNCHANGEABLE_MASK = 56313,\n\t__IPS_MAX_BIT = 16,\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum ipr_sdt_state {\n\tINACTIVE = 0,\n\tWAIT_FOR_DUMP = 1,\n\tGET_DUMP = 2,\n\tREAD_DUMP = 3,\n\tABORT_DUMP = 4,\n\tDUMP_OBTAINED = 5,\n};\n\nenum ipr_shutdown_type {\n\tIPR_SHUTDOWN_NORMAL = 0,\n\tIPR_SHUTDOWN_PREPARE_FOR_NORMAL = 64,\n\tIPR_SHUTDOWN_ABBREV = 128,\n\tIPR_SHUTDOWN_NONE = 256,\n\tIPR_SHUTDOWN_QUIESCE = 257,\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n\tDOMAIN_BUS_VMD_MSI = 10,\n\tDOMAIN_BUS_PCI_DEVICE_MSI = 11,\n\tDOMAIN_BUS_PCI_DEVICE_MSIX = 12,\n\tDOMAIN_BUS_DMAR = 13,\n\tDOMAIN_BUS_AMDVI = 14,\n\tDOMAIN_BUS_DEVICE_MSI = 15,\n\tDOMAIN_BUS_WIRED_TO_MSI = 16,\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\nenum isofs_file_format {\n\tisofs_file_normal = 0,\n\tisofs_file_sparse = 1,\n\tisofs_file_compressed = 2,\n};\n\nenum iter_type {\n\tITER_UBUF = 0,\n\tITER_IOVEC = 1,\n\tITER_BVEC = 2,\n\tITER_KVEC = 3,\n\tITER_FOLIOQ = 4,\n\tITER_XARRAY = 5,\n\tITER_DISCARD = 6,\n};\n\nenum jbd2_shrink_type {\n\tJBD2_SHRINK_DESTROY = 0,\n\tJBD2_SHRINK_BUSY_STOP = 1,\n\tJBD2_SHRINK_BUSY_SKIP = 2,\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 17,\n\tBH_JWrite = 18,\n\tBH_Freed = 19,\n\tBH_Revoked = 20,\n\tBH_RevokeValid = 21,\n\tBH_JBDDirty = 22,\n\tBH_JournalHead = 23,\n\tBH_Shadow = 24,\n\tBH_Verified = 25,\n\tBH_JBDPrivateStart = 26,\n};\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nenum kcmp_type {\n\tKCMP_FILE = 0,\n\tKCMP_VM = 1,\n\tKCMP_FILES = 2,\n\tKCMP_FS = 3,\n\tKCMP_SIGHAND = 4,\n\tKCMP_IO = 5,\n\tKCMP_SYSVSEM = 6,\n\tKCMP_EPOLL_TFD = 7,\n\tKCMP_TYPES = 8,\n};\n\nenum kcore_type {\n\tKCORE_TEXT = 0,\n\tKCORE_VMALLOC = 1,\n\tKCORE_RAM = 2,\n\tKCORE_VMEMMAP = 3,\n\tKCORE_USER = 4,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_MODULE = 2,\n\tLOADING_KEXEC_IMAGE = 3,\n\tLOADING_KEXEC_INITRAMFS = 4,\n\tLOADING_POLICY = 5,\n\tLOADING_X509_CERTIFICATE = 6,\n\tLOADING_MODULE_COMPRESSED = 7,\n\tLOADING_MAX_ID = 8,\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_MODULE = 2,\n\tREADING_KEXEC_IMAGE = 3,\n\tREADING_KEXEC_INITRAMFS = 4,\n\tREADING_POLICY = 5,\n\tREADING_X509_CERTIFICATE = 6,\n\tREADING_MODULE_COMPRESSED = 7,\n\tREADING_MAX_ID = 8,\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_HIDDEN = 512,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n\tKERNFS_REMOVING = 16384,\n};\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n\tKERNFS_ROOT_INVARIANT_PARENT = 16,\n};\n\nenum key_being_used_for {\n\tVERIFYING_MODULE_SIGNATURE = 0,\n\tVERIFYING_FIRMWARE_SIGNATURE = 1,\n\tVERIFYING_KEXEC_PE_SIGNATURE = 2,\n\tVERIFYING_KEY_SIGNATURE = 3,\n\tVERIFYING_KEY_SELF_SIGNATURE = 4,\n\tVERIFYING_UNSPECIFIED_SIGNATURE = 5,\n\tVERIFYING_BPF_SIGNATURE = 6,\n\tNR__KEY_BEING_USED_FOR = 7,\n};\n\nenum key_lookup_flag {\n\tKEY_LOOKUP_CREATE = 1,\n\tKEY_LOOKUP_PARTIAL = 2,\n\tKEY_LOOKUP_ALL = 3,\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nenum kfunc_ptr_arg_type {\n\tKF_ARG_PTR_TO_CTX = 0,\n\tKF_ARG_PTR_TO_ALLOC_BTF_ID = 1,\n\tKF_ARG_PTR_TO_REFCOUNTED_KPTR = 2,\n\tKF_ARG_PTR_TO_DYNPTR = 3,\n\tKF_ARG_PTR_TO_ITER = 4,\n\tKF_ARG_PTR_TO_LIST_HEAD = 5,\n\tKF_ARG_PTR_TO_LIST_NODE = 6,\n\tKF_ARG_PTR_TO_BTF_ID = 7,\n\tKF_ARG_PTR_TO_MEM = 8,\n\tKF_ARG_PTR_TO_MEM_SIZE = 9,\n\tKF_ARG_PTR_TO_CALLBACK = 10,\n\tKF_ARG_PTR_TO_RB_ROOT = 11,\n\tKF_ARG_PTR_TO_RB_NODE = 12,\n\tKF_ARG_PTR_TO_NULL = 13,\n\tKF_ARG_PTR_TO_CONST_STR = 14,\n\tKF_ARG_PTR_TO_MAP = 15,\n\tKF_ARG_PTR_TO_TIMER = 16,\n\tKF_ARG_PTR_TO_WORKQUEUE = 17,\n\tKF_ARG_PTR_TO_IRQ_FLAG = 18,\n\tKF_ARG_PTR_TO_RES_SPIN_LOCK = 19,\n\tKF_ARG_PTR_TO_TASK_WORK = 20,\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_DMA = 0,\n\tKMALLOC_RANDOM_START = 0,\n\tKMALLOC_RANDOM_END = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_CGROUP = 2,\n\tNR_KMALLOC_TYPES = 3,\n};\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n};\n\nenum kpage_operation {\n\tKPAGE_FLAGS = 0,\n\tKPAGE_COUNT = 1,\n\tKPAGE_CGROUP = 2,\n};\n\nenum kprobe_slot_state {\n\tSLOT_CLEAN = 0,\n\tSLOT_DIRTY = 1,\n\tSLOT_USED = 2,\n};\n\nenum ksm_advisor_type {\n\tKSM_ADVISOR_NONE = 0,\n\tKSM_ADVISOR_SCAN_TIME = 1,\n};\n\nenum ksm_get_folio_flags {\n\tKSM_GET_FOLIO_NOLOCK = 0,\n\tKSM_GET_FOLIO_LOCK = 1,\n\tKSM_GET_FOLIO_TRYLOCK = 2,\n};\n\nenum kswapd_clear_hopeless_reason {\n\tKSWAPD_CLEAR_HOPELESS_OTHER = 0,\n\tKSWAPD_CLEAR_HOPELESS_KSWAPD = 1,\n\tKSWAPD_CLEAR_HOPELESS_DIRECT = 2,\n\tKSWAPD_CLEAR_HOPELESS_PCP = 3,\n};\n\nenum kunit_speed {\n\tKUNIT_SPEED_UNSET = 0,\n\tKUNIT_SPEED_VERY_SLOW = 1,\n\tKUNIT_SPEED_SLOW = 2,\n\tKUNIT_SPEED_NORMAL = 3,\n\tKUNIT_SPEED_MAX = 3,\n};\n\nenum kunit_status {\n\tKUNIT_SUCCESS = 0,\n\tKUNIT_FAILURE = 1,\n\tKUNIT_SKIPPED = 2,\n};\n\nenum kvm_bus {\n\tKVM_MMIO_BUS = 0,\n\tKVM_PIO_BUS = 1,\n\tKVM_VIRTIO_CCW_NOTIFY_BUS = 2,\n\tKVM_FAST_MMIO_BUS = 3,\n\tKVM_IOCSR_BUS = 4,\n\tKVM_NR_BUSES = 5,\n};\n\nenum kvm_gfn_range_filter {\n\tKVM_FILTER_SHARED = 1,\n\tKVM_FILTER_PRIVATE = 2,\n};\n\nenum kvm_mr_change {\n\tKVM_MR_CREATE = 0,\n\tKVM_MR_DELETE = 1,\n\tKVM_MR_MOVE = 2,\n\tKVM_MR_FLAGS_ONLY = 3,\n};\n\nenum kvm_stat_kind {\n\tKVM_STAT_VM = 0,\n\tKVM_STAT_VCPU = 1,\n};\n\nenum l1d_flush_type {\n\tL1D_FLUSH_NONE = 1,\n\tL1D_FLUSH_FALLBACK = 2,\n\tL1D_FLUSH_ORI = 4,\n\tL1D_FLUSH_MTTRIG = 8,\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nenum label_initialized {\n\tLABEL_INVALID = 0,\n\tLABEL_INITIALIZED = 1,\n\tLABEL_PENDING = 2,\n};\n\nenum landlock_key_type {\n\tLANDLOCK_KEY_INODE = 1,\n\tLANDLOCK_KEY_NET_PORT = 2,\n};\n\nenum landlock_log_status {\n\tLANDLOCK_LOG_PENDING = 0,\n\tLANDLOCK_LOG_RECORDED = 1,\n\tLANDLOCK_LOG_DISABLED = 2,\n};\n\nenum landlock_request_type {\n\tLANDLOCK_REQUEST_PTRACE = 1,\n\tLANDLOCK_REQUEST_FS_CHANGE_TOPOLOGY = 2,\n\tLANDLOCK_REQUEST_FS_ACCESS = 3,\n\tLANDLOCK_REQUEST_NET_ACCESS = 4,\n\tLANDLOCK_REQUEST_SCOPE_ABSTRACT_UNIX_SOCKET = 5,\n\tLANDLOCK_REQUEST_SCOPE_SIGNAL = 6,\n};\n\nenum landlock_rule_type {\n\tLANDLOCK_RULE_PATH_BENEATH = 1,\n\tLANDLOCK_RULE_NET_PORT = 2,\n};\n\nenum latency_range {\n\tlowest_latency = 0,\n\tlow_latency = 1,\n\tbulk_latency = 2,\n\tlatency_invalid = 255,\n};\n\nenum layout_break_reason {\n\tBREAK_WRITE = 0,\n\tBREAK_UNMAP = 1,\n};\n\nenum layoutdriver_policy_flags {\n\tPNFS_LAYOUTRET_ON_SETATTR = 1,\n\tPNFS_LAYOUTRET_ON_ERROR = 2,\n\tPNFS_READ_WHOLE_PAGE = 4,\n\tPNFS_LAYOUTGET_ON_OPEN = 8,\n};\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nenum led_default_state {\n\tLEDS_DEFSTATE_OFF = 0,\n\tLEDS_DEFSTATE_ON = 1,\n\tLEDS_DEFSTATE_KEEP = 2,\n};\n\nenum led_state {\n\tled_on = 1,\n\tled_off = 4,\n\tled_on_559 = 5,\n\tled_on_557 = 7,\n};\n\nenum led_trigger_netdev_modes {\n\tTRIGGER_NETDEV_LINK = 0,\n\tTRIGGER_NETDEV_LINK_10 = 1,\n\tTRIGGER_NETDEV_LINK_100 = 2,\n\tTRIGGER_NETDEV_LINK_1000 = 3,\n\tTRIGGER_NETDEV_LINK_2500 = 4,\n\tTRIGGER_NETDEV_LINK_5000 = 5,\n\tTRIGGER_NETDEV_LINK_10000 = 6,\n\tTRIGGER_NETDEV_HALF_DUPLEX = 7,\n\tTRIGGER_NETDEV_FULL_DUPLEX = 8,\n\tTRIGGER_NETDEV_TX = 9,\n\tTRIGGER_NETDEV_RX = 10,\n\tTRIGGER_NETDEV_TX_ERR = 11,\n\tTRIGGER_NETDEV_RX_ERR = 12,\n\t__TRIGGER_NETDEV_MAX = 13,\n};\n\nenum limit_by4 {\n\tNFS4_LIMIT_SIZE = 1,\n\tNFS4_LIMIT_BLOCKS = 2,\n};\n\nenum link_inband_signalling {\n\tLINK_INBAND_DISABLE = 1,\n\tLINK_INBAND_ENABLE = 2,\n\tLINK_INBAND_BYPASS = 4,\n};\n\nenum link_state {\n\tlink_down = 0,\n\tlink_aneg = 1,\n\tlink_force_try = 2,\n\tlink_force_ret = 3,\n\tlink_force_ok = 4,\n\tlink_up = 5,\n};\n\nenum lock_type4 {\n\tNFS4_UNLOCK_LT = 0,\n\tNFS4_READ_LT = 1,\n\tNFS4_WRITE_LT = 2,\n\tNFS4_READW_LT = 3,\n\tNFS4_WRITEW_LT = 4,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_DEVICE_TREE = 10,\n\tLOCKDOWN_PCMCIA_CIS = 11,\n\tLOCKDOWN_TIOCSSERIAL = 12,\n\tLOCKDOWN_MODULE_PARAMETERS = 13,\n\tLOCKDOWN_MMIOTRACE = 14,\n\tLOCKDOWN_DEBUGFS = 15,\n\tLOCKDOWN_XMON_WR = 16,\n\tLOCKDOWN_BPF_WRITE_USER = 17,\n\tLOCKDOWN_DBG_WRITE_KERNEL = 18,\n\tLOCKDOWN_RTAS_ERROR_INJECTION = 19,\n\tLOCKDOWN_INTEGRITY_MAX = 20,\n\tLOCKDOWN_KCORE = 21,\n\tLOCKDOWN_KPROBES = 22,\n\tLOCKDOWN_BPF_READ_KERNEL = 23,\n\tLOCKDOWN_DBG_READ_KERNEL = 24,\n\tLOCKDOWN_PERF = 25,\n\tLOCKDOWN_TRACEFS = 26,\n\tLOCKDOWN_XMON_RW = 27,\n\tLOCKDOWN_XFRM_SECRET = 28,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 29,\n};\n\nenum log_ent_request {\n\tLOG_NEW_ENT = 0,\n\tLOG_OLD_ENT = 1,\n};\n\nenum loopback {\n\tlb_none = 0,\n\tlb_mac = 1,\n\tlb_phy = 3,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n\tLRU_STOP = 5,\n};\n\nenum lruvec_flags {\n\tLRUVEC_CGROUP_CONGESTED = 0,\n\tLRUVEC_NODE_CONGESTED = 1,\n};\n\nenum lsm_event {\n\tLSM_POLICY_CHANGE = 0,\n\tLSM_STARTED_ALL = 1,\n};\n\nenum lsm_integrity_type {\n\tLSM_INT_DMVERITY_SIG_VALID = 0,\n\tLSM_INT_DMVERITY_ROOTHASH = 1,\n\tLSM_INT_FSVERITY_BUILTINSIG_VALID = 2,\n};\n\nenum lsm_order {\n\tLSM_ORDER_FIRST = -1,\n\tLSM_ORDER_MUTABLE = 0,\n\tLSM_ORDER_LAST = 1,\n};\n\nenum lsm_rule_types {\n\tLSM_OBJ_USER = 0,\n\tLSM_OBJ_ROLE = 1,\n\tLSM_OBJ_TYPE = 2,\n\tLSM_SUBJ_USER = 3,\n\tLSM_SUBJ_ROLE = 4,\n\tLSM_SUBJ_TYPE = 5,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\tLWTUNNEL_ENCAP_IOAM6 = 9,\n\tLWTUNNEL_ENCAP_XFRM = 10,\n\t__LWTUNNEL_ENCAP_MAX = 11,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nenum mac {\n\tmac_82557_D100_A = 0,\n\tmac_82557_D100_B = 1,\n\tmac_82557_D100_C = 2,\n\tmac_82558_D101_A4 = 4,\n\tmac_82558_D101_B0 = 5,\n\tmac_82559_D101M = 8,\n\tmac_82559_D101S = 9,\n\tmac_82550_D102 = 12,\n\tmac_82550_D102_C = 13,\n\tmac_82551_E = 14,\n\tmac_82551_F = 15,\n\tmac_82551_10 = 16,\n\tmac_unknown = 255,\n};\n\nenum madvise_lock_mode {\n\tMADVISE_NO_LOCK = 0,\n\tMADVISE_MMAP_READ_LOCK = 1,\n\tMADVISE_MMAP_WRITE_LOCK = 2,\n\tMADVISE_VMA_READ_LOCK = 3,\n};\n\nenum maple_status {\n\tma_active = 0,\n\tma_start = 1,\n\tma_root = 2,\n\tma_none = 3,\n\tma_pause = 4,\n\tma_overflow = 5,\n\tma_underflow = 6,\n\tma_error = 7,\n};\n\nenum maple_type {\n\tmaple_dense = 0,\n\tmaple_leaf_64 = 1,\n\tmaple_range_64 = 2,\n\tmaple_arange_64 = 3,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n\tAS_RELEASE_ALWAYS = 6,\n\tAS_STABLE_WRITES = 7,\n\tAS_INACCESSIBLE = 8,\n\tAS_WRITEBACK_MAY_DEADLOCK_ON_RECLAIM = 9,\n\tAS_KERNEL_FILE = 10,\n\tAS_NO_DATA_INTEGRITY = 11,\n\tAS_FOLIO_ORDER_BITS = 5,\n\tAS_FOLIO_ORDER_MIN = 16,\n\tAS_FOLIO_ORDER_MAX = 21,\n};\n\nenum md_ro_state {\n\tMD_RDWR = 0,\n\tMD_RDONLY = 1,\n\tMD_AUTO_READ = 2,\n\tMD_MAX_STATE = 3,\n};\n\nenum md_submodule_id {\n\tID_LINEAR = -1,\n\tID_RAID0 = 0,\n\tID_RAID1 = 1,\n\tID_RAID4 = 4,\n\tID_RAID5 = 5,\n\tID_RAID6 = 6,\n\tID_RAID10 = 10,\n\tID_CLUSTER = 11,\n\tID_BITMAP = 12,\n\tID_LLBITMAP = 13,\n\tID_BITMAP_NONE = 14,\n};\n\nenum md_submodule_type {\n\tMD_PERSONALITY = 0,\n\tMD_CLUSTER = 1,\n\tMD_BITMAP = 2,\n};\n\nenum mddev_flags {\n\tMD_ARRAY_FIRST_USE = 0,\n\tMD_CLOSING = 1,\n\tMD_JOURNAL_CLEAN = 2,\n\tMD_HAS_JOURNAL = 3,\n\tMD_CLUSTER_RESYNC_LOCKED = 4,\n\tMD_FAILFAST_SUPPORTED = 5,\n\tMD_HAS_PPL = 6,\n\tMD_HAS_MULTIPLE_PPLS = 7,\n\tMD_NOT_READY = 8,\n\tMD_BROKEN = 9,\n\tMD_DO_DELETE = 10,\n\tMD_DELETED = 11,\n\tMD_HAS_SUPERBLOCK = 12,\n\tMD_FAILLAST_DEV = 13,\n\tMD_SERIALIZE_POLICY = 14,\n};\n\nenum mddev_sb_flags {\n\tMD_SB_CHANGE_DEVS = 0,\n\tMD_SB_CHANGE_CLEAN = 1,\n\tMD_SB_CHANGE_PENDING = 2,\n\tMD_SB_NEED_REWRITE = 3,\n};\n\nenum mdi_ctrl {\n\tmdi_write = 67108864,\n\tmdi_read = 134217728,\n\tmdi_ready = 268435456,\n};\n\nenum mem_type {\n\tMEM_EMPTY = 0,\n\tMEM_RESERVED = 1,\n\tMEM_UNKNOWN = 2,\n\tMEM_FPM = 3,\n\tMEM_EDO = 4,\n\tMEM_BEDO = 5,\n\tMEM_SDR = 6,\n\tMEM_RDR = 7,\n\tMEM_DDR = 8,\n\tMEM_RDDR = 9,\n\tMEM_RMBS = 10,\n\tMEM_DDR2 = 11,\n\tMEM_FB_DDR2 = 12,\n\tMEM_RDDR2 = 13,\n\tMEM_XDR = 14,\n\tMEM_DDR3 = 15,\n\tMEM_RDDR3 = 16,\n\tMEM_LRDDR3 = 17,\n\tMEM_LPDDR3 = 18,\n\tMEM_DDR4 = 19,\n\tMEM_RDDR4 = 20,\n\tMEM_LRDDR4 = 21,\n\tMEM_LPDDR4 = 22,\n\tMEM_DDR5 = 23,\n\tMEM_RDDR5 = 24,\n\tMEM_LRDDR5 = 25,\n\tMEM_NVDIMM = 26,\n\tMEM_WIO2 = 27,\n\tMEM_HBM2 = 28,\n\tMEM_HBM3 = 29,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ = 128,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ = 256,\n\tMEMBARRIER_CMD_GET_REGISTRATIONS = 512,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nenum membarrier_cmd_flag {\n\tMEMBARRIER_CMD_FLAG_CPU = 1,\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n\tMEMBLOCK_DRIVER_MANAGED = 8,\n\tMEMBLOCK_RSRV_NOINIT = 16,\n\tMEMBLOCK_RSRV_KERN = 32,\n\tMEMBLOCK_KHO_SCRATCH = 64,\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_OOM_GROUP_KILL = 5,\n\tMEMCG_SWAP_HIGH = 6,\n\tMEMCG_SWAP_MAX = 7,\n\tMEMCG_SWAP_FAIL = 8,\n\tMEMCG_SOCK_THROTTLED = 9,\n\tMEMCG_NR_MEMORY_EVENTS = 10,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 51,\n\tMEMCG_SOCK = 52,\n\tMEMCG_PERCPU_B = 53,\n\tMEMCG_VMALLOC = 54,\n\tMEMCG_KMEM = 55,\n\tMEMCG_ZSWAP_B = 56,\n\tMEMCG_ZSWAPPED = 57,\n\tMEMCG_NR_STAT = 58,\n};\n\nenum meminit_context {\n\tMEMINIT_EARLY = 0,\n\tMEMINIT_HOTPLUG = 1,\n};\n\nenum memory_block_state {\n\tMEM_ONLINE = 0,\n\tMEM_GOING_OFFLINE = 1,\n\tMEM_OFFLINE = 2,\n\tMEM_GOING_ONLINE = 3,\n\tMEM_CANCEL_ONLINE = 4,\n\tMEM_CANCEL_OFFLINE = 5,\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_COHERENT = 2,\n\tMEMORY_DEVICE_FS_DAX = 3,\n\tMEMORY_DEVICE_GENERIC = 4,\n\tMEMORY_DEVICE_PCI_P2PDMA = 5,\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n\tMETADATA_MACSEC = 2,\n\tMETADATA_XFRM = 3,\n};\n\nenum mext_move_type {\n\tMEXT_SKIP_EXTENT = 0,\n\tMEXT_MOVE_EXTENT = 1,\n\tMEXT_COPY_DATA = 2,\n};\n\nenum mf_flags {\n\tMF_COUNT_INCREASED = 1,\n\tMF_ACTION_REQUIRED = 2,\n\tMF_MUST_KILL = 4,\n\tMF_SOFT_OFFLINE = 8,\n\tMF_UNPOISON = 16,\n\tMF_SW_SIMULATED = 32,\n\tMF_NO_RETRY = 64,\n\tMF_MEM_PRE_REMOVE = 128,\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_LONGTERM_PIN = 7,\n\tMR_DEMOTION = 8,\n\tMR_DAMON = 9,\n\tMR_TYPES = 10,\n};\n\nenum migrate_vma_direction {\n\tMIGRATE_VMA_SELECT_SYSTEM = 1,\n\tMIGRATE_VMA_SELECT_DEVICE_PRIVATE = 2,\n\tMIGRATE_VMA_SELECT_DEVICE_COHERENT = 4,\n\tMIGRATE_VMA_SELECT_COMPOUND = 8,\n};\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\tMIGRATE_CMA = 4,\n\t__MIGRATE_TYPE_END = 4,\n\tMIGRATE_ISOLATE = 5,\n\tMIGRATE_TYPES = 6,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nenum misc_res_type {\n\tMISC_CG_RES_TYPES = 0,\n};\n\nenum mmap_action_type {\n\tMMAP_NOTHING = 0,\n\tMMAP_REMAP_PFN = 1,\n\tMMAP_IO_REMAP_PFN = 2,\n};\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nenum mmu_notifier_event {\n\tMMU_NOTIFY_UNMAP = 0,\n\tMMU_NOTIFY_CLEAR = 1,\n\tMMU_NOTIFY_PROTECTION_VMA = 2,\n\tMMU_NOTIFY_PROTECTION_PAGE = 3,\n\tMMU_NOTIFY_SOFT_DIRTY = 4,\n\tMMU_NOTIFY_RELEASE = 5,\n\tMMU_NOTIFY_MIGRATE = 6,\n\tMMU_NOTIFY_EXCLUSIVE = 7,\n};\n\nenum mnt_tree_flags_t {\n\tMNT_TREE_BENEATH = 1,\n\tMNT_TREE_PROPAGATION = 2,\n};\n\nenum mod_license {\n\tNOT_GPL_ONLY = 0,\n\tGPL_ONLY = 1,\n};\n\nenum mod_mem_type {\n\tMOD_TEXT = 0,\n\tMOD_DATA = 1,\n\tMOD_RODATA = 2,\n\tMOD_RO_AFTER_INIT = 3,\n\tMOD_INIT_TEXT = 4,\n\tMOD_INIT_DATA = 5,\n\tMOD_INIT_RODATA = 6,\n\tMOD_MEM_NUM_TYPES = 7,\n\tMOD_INVALID = -1,\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nenum mount_flags {\n\tMNT_NOSUID = 1,\n\tMNT_NODEV = 2,\n\tMNT_NOEXEC = 4,\n\tMNT_NOATIME = 8,\n\tMNT_NODIRATIME = 16,\n\tMNT_RELATIME = 32,\n\tMNT_READONLY = 64,\n\tMNT_NOSYMFOLLOW = 128,\n\tMNT_SHRINKABLE = 256,\n\tMNT_INTERNAL = 16384,\n\tMNT_LOCK_ATIME = 262144,\n\tMNT_LOCK_NOEXEC = 524288,\n\tMNT_LOCK_NOSUID = 1048576,\n\tMNT_LOCK_NODEV = 2097152,\n\tMNT_LOCK_READONLY = 4194304,\n\tMNT_LOCKED = 8388608,\n\tMNT_DOOMED = 16777216,\n\tMNT_SYNC_UMOUNT = 33554432,\n\tMNT_UMOUNT = 134217728,\n\tMNT_USER_SETTABLE_MASK = 255,\n\tMNT_ATIME_MASK = 56,\n\tMNT_INTERNAL_FLAGS = 58736640,\n};\n\nenum mount_kattr_flags_t {\n\tMOUNT_KATTR_RECURSE = 1,\n\tMOUNT_KATTR_IDMAP_REPLACE = 2,\n};\n\nenum mountstat {\n\tMNT_OK = 0,\n\tMNT_EPERM = 1,\n\tMNT_ENOENT = 2,\n\tMNT_EACCES = 13,\n\tMNT_EINVAL = 22,\n};\n\nenum mountstat3 {\n\tMNT3_OK = 0,\n\tMNT3ERR_PERM = 1,\n\tMNT3ERR_NOENT = 2,\n\tMNT3ERR_IO = 5,\n\tMNT3ERR_ACCES = 13,\n\tMNT3ERR_NOTDIR = 20,\n\tMNT3ERR_INVAL = 22,\n\tMNT3ERR_NAMETOOLONG = 63,\n\tMNT3ERR_NOTSUPP = 10004,\n\tMNT3ERR_SERVERFAULT = 10006,\n};\n\nenum mpic_reg_type {\n\tmpic_access_mmio_le = 0,\n\tmpic_access_mmio_be = 1,\n};\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nenum mremap_type {\n\tMREMAP_INVALID = 0,\n\tMREMAP_NO_RESIZE = 1,\n\tMREMAP_SHRINK = 2,\n\tMREMAP_EXPAND = 3,\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nenum msi_desc_filter {\n\tMSI_DESC_ALL = 0,\n\tMSI_DESC_NOTASSOCIATED = 1,\n\tMSI_DESC_ASSOCIATED = 2,\n};\n\nenum msi_domain_ids {\n\tMSI_DEFAULT_DOMAIN = 0,\n\tMSI_MAX_DEVICE_IRQDOMAINS = 1,\n};\n\nenum mthp_stat_item {\n\tMTHP_STAT_ANON_FAULT_ALLOC = 0,\n\tMTHP_STAT_ANON_FAULT_FALLBACK = 1,\n\tMTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2,\n\tMTHP_STAT_ZSWPOUT = 3,\n\tMTHP_STAT_SWPIN = 4,\n\tMTHP_STAT_SWPIN_FALLBACK = 5,\n\tMTHP_STAT_SWPIN_FALLBACK_CHARGE = 6,\n\tMTHP_STAT_SWPOUT = 7,\n\tMTHP_STAT_SWPOUT_FALLBACK = 8,\n\tMTHP_STAT_SHMEM_ALLOC = 9,\n\tMTHP_STAT_SHMEM_FALLBACK = 10,\n\tMTHP_STAT_SHMEM_FALLBACK_CHARGE = 11,\n\tMTHP_STAT_SPLIT = 12,\n\tMTHP_STAT_SPLIT_FAILED = 13,\n\tMTHP_STAT_SPLIT_DEFERRED = 14,\n\tMTHP_STAT_NR_ANON = 15,\n\tMTHP_STAT_NR_ANON_PARTIALLY_MAPPED = 16,\n\t__MTHP_STAT_COUNT = 17,\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nenum nbcon_prio {\n\tNBCON_PRIO_NONE = 0,\n\tNBCON_PRIO_NORMAL = 1,\n\tNBCON_PRIO_EMERGENCY = 2,\n\tNBCON_PRIO_PANIC = 3,\n\tNBCON_PRIO_MAX = 4,\n};\n\nenum nd_async_mode {\n\tND_SYNC = 0,\n\tND_ASYNC = 1,\n};\n\nenum nd_driver_flags {\n\tND_DRIVER_DIMM = 2,\n\tND_DRIVER_REGION_PMEM = 4,\n\tND_DRIVER_REGION_BLK = 8,\n\tND_DRIVER_NAMESPACE_IO = 16,\n\tND_DRIVER_NAMESPACE_PMEM = 32,\n\tND_DRIVER_DAX_PMEM = 128,\n};\n\nenum nd_ioctl_mode {\n\tBUS_IOCTL = 0,\n\tDIMM_IOCTL = 1,\n};\n\nenum nd_label_flags {\n\tND_LABEL_REAP = 0,\n};\n\nenum nd_pfn_mode {\n\tPFN_MODE_NONE = 0,\n\tPFN_MODE_RAM = 1,\n\tPFN_MODE_PMEM = 2,\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nenum net_device_path_type {\n\tDEV_PATH_ETHERNET = 0,\n\tDEV_PATH_VLAN = 1,\n\tDEV_PATH_BRIDGE = 2,\n\tDEV_PATH_PPPOE = 3,\n\tDEV_PATH_DSA = 4,\n\tDEV_PATH_MTK_WDMA = 5,\n\tDEV_PATH_TUN = 6,\n};\n\nenum net_iov_type {\n\tNET_IOV_DMABUF = 0,\n\tNET_IOV_IOURING = 1,\n};\n\nenum net_xmit_qdisc_t {\n\t__NET_XMIT_STOLEN = 65536,\n\t__NET_XMIT_BYPASS = 131072,\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_PRE_UNINIT = 18,\n\tNETDEV_RELEASE = 19,\n\tNETDEV_NOTIFY_PEERS = 20,\n\tNETDEV_JOIN = 21,\n\tNETDEV_CHANGEUPPER = 22,\n\tNETDEV_RESEND_IGMP = 23,\n\tNETDEV_PRECHANGEMTU = 24,\n\tNETDEV_CHANGEINFODATA = 25,\n\tNETDEV_BONDING_INFO = 26,\n\tNETDEV_PRECHANGEUPPER = 27,\n\tNETDEV_CHANGELOWERSTATE = 28,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 29,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 30,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 31,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 32,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 33,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 34,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 35,\n\tNETDEV_OFFLOAD_XSTATS_ENABLE = 36,\n\tNETDEV_OFFLOAD_XSTATS_DISABLE = 37,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_USED = 38,\n\tNETDEV_OFFLOAD_XSTATS_REPORT_DELTA = 39,\n\tNETDEV_XDP_FEAT_CHANGE = 40,\n};\n\nenum netdev_ml_priv_type {\n\tML_PRIV_NONE = 0,\n\tML_PRIV_CAN = 1,\n};\n\nenum netdev_napi_threaded {\n\tNETDEV_NAPI_THREADED_DISABLED = 0,\n\tNETDEV_NAPI_THREADED_ENABLED = 1,\n\tNETDEV_NAPI_THREADED_BUSY_POLL = 2,\n};\n\nenum netdev_offload_xstats_type {\n\tNETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_NO_ADDRCONF = 1073741824,\n\tIFF_TX_SKB_NO_LINEAR = 2147483648,\n};\n\nenum netdev_qstats_scope {\n\tNETDEV_QSTATS_SCOPE_QUEUE = 1,\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum netdev_queue_type {\n\tNETDEV_QUEUE_TYPE_RX = 0,\n\tNETDEV_QUEUE_TYPE_TX = 1,\n};\n\nenum netdev_reg_state {\n\tNETREG_UNINITIALIZED = 0,\n\tNETREG_REGISTERED = 1,\n\tNETREG_UNREGISTERING = 2,\n\tNETREG_UNREGISTERED = 3,\n\tNETREG_RELEASED = 4,\n\tNETREG_DUMMY = 5,\n};\n\nenum netdev_stat_type {\n\tNETDEV_PCPU_STAT_NONE = 0,\n\tNETDEV_PCPU_STAT_LSTATS = 1,\n\tNETDEV_PCPU_STAT_TSTATS = 2,\n\tNETDEV_PCPU_STAT_DSTATS = 3,\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = -2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nenum netdev_xdp_act {\n\tNETDEV_XDP_ACT_BASIC = 1,\n\tNETDEV_XDP_ACT_REDIRECT = 2,\n\tNETDEV_XDP_ACT_NDO_XMIT = 4,\n\tNETDEV_XDP_ACT_XSK_ZEROCOPY = 8,\n\tNETDEV_XDP_ACT_HW_OFFLOAD = 16,\n\tNETDEV_XDP_ACT_RX_SG = 32,\n\tNETDEV_XDP_ACT_NDO_XMIT_SG = 64,\n\tNETDEV_XDP_ACT_MASK = 127,\n};\n\nenum netdev_xdp_rx_metadata {\n\tNETDEV_XDP_RX_METADATA_TIMESTAMP = 1,\n\tNETDEV_XDP_RX_METADATA_HASH = 2,\n\tNETDEV_XDP_RX_METADATA_VLAN_TAG = 4,\n};\n\nenum netdev_xsk_flags {\n\tNETDEV_XSK_FLAGS_TX_TIMESTAMP = 1,\n\tNETDEV_XSK_FLAGS_TX_CHECKSUM = 2,\n\tNETDEV_XSK_FLAGS_TX_LAUNCH_TIME_FIFO = 4,\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n\tNL_ATTR_TYPE_SINT = 16,\n\tNL_ATTR_TYPE_UINT = 17,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\tNL_POLICY_TYPE_ATTR_MASK = 12,\n\t__NL_POLICY_TYPE_ATTR_MAX = 13,\n\tNL_POLICY_TYPE_ATTR_MAX = 12,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = -1,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tNETNS_BPF_SK_LOOKUP = 1,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 2,\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_DEL = 0,\n\tNEXTHOP_EVENT_REPLACE = 1,\n\tNEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2,\n\tNEXTHOP_EVENT_BUCKET_REPLACE = 3,\n\tNEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4,\n};\n\nenum nf_ct_ext_id {\n\tNF_CT_EXT_HELPER = 0,\n\tNF_CT_EXT_NAT = 1,\n\tNF_CT_EXT_SEQADJ = 2,\n\tNF_CT_EXT_ACCT = 3,\n\tNF_CT_EXT_NUM = 4,\n};\n\nenum nf_dev_hooks {\n\tNF_NETDEV_INGRESS = 0,\n\tNF_NETDEV_EGRESS = 1,\n\tNF_NETDEV_NUMHOOKS = 2,\n};\n\nenum nf_hook_ops_type {\n\tNF_HOOK_OP_UNDEFINED = 0,\n\tNF_HOOK_OP_NF_TABLES = 1,\n\tNF_HOOK_OP_BPF = 2,\n\tNF_HOOK_OP_NFT_FT = 3,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n\tNF_INET_INGRESS = 5,\n};\n\nenum nf_ip6_hook_priorities {\n\tNF_IP6_PRI_FIRST = -2147483648,\n\tNF_IP6_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP6_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP6_PRI_RAW = -300,\n\tNF_IP6_PRI_SELINUX_FIRST = -225,\n\tNF_IP6_PRI_CONNTRACK = -200,\n\tNF_IP6_PRI_MANGLE = -150,\n\tNF_IP6_PRI_NAT_DST = -100,\n\tNF_IP6_PRI_FILTER = 0,\n\tNF_IP6_PRI_SECURITY = 50,\n\tNF_IP6_PRI_NAT_SRC = 100,\n\tNF_IP6_PRI_SELINUX_LAST = 225,\n\tNF_IP6_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP6_PRI_LAST = 2147483647,\n};\n\nenum nf_ip_hook_priorities {\n\tNF_IP_PRI_FIRST = -2147483648,\n\tNF_IP_PRI_RAW_BEFORE_DEFRAG = -450,\n\tNF_IP_PRI_CONNTRACK_DEFRAG = -400,\n\tNF_IP_PRI_RAW = -300,\n\tNF_IP_PRI_SELINUX_FIRST = -225,\n\tNF_IP_PRI_CONNTRACK = -200,\n\tNF_IP_PRI_MANGLE = -150,\n\tNF_IP_PRI_NAT_DST = -100,\n\tNF_IP_PRI_FILTER = 0,\n\tNF_IP_PRI_SECURITY = 50,\n\tNF_IP_PRI_NAT_SRC = 100,\n\tNF_IP_PRI_SELINUX_LAST = 225,\n\tNF_IP_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP_PRI_CONNTRACK_CONFIRM = 2147483647,\n\tNF_IP_PRI_LAST = 2147483647,\n};\n\nenum nf_log_type {\n\tNF_LOG_TYPE_LOG = 0,\n\tNF_LOG_TYPE_ULOG = 1,\n\tNF_LOG_TYPE_MAX = 2,\n};\n\nenum nf_nat_manip_type;\n\nenum nfs3_createmode {\n\tNFS3_CREATE_UNCHECKED = 0,\n\tNFS3_CREATE_GUARDED = 1,\n\tNFS3_CREATE_EXCLUSIVE = 2,\n};\n\nenum nfs3_ftype {\n\tNF3NON = 0,\n\tNF3REG = 1,\n\tNF3DIR = 2,\n\tNF3BLK = 3,\n\tNF3CHR = 4,\n\tNF3LNK = 5,\n\tNF3SOCK = 6,\n\tNF3FIFO = 7,\n\tNF3BAD = 8,\n};\n\nenum nfs3_stable_how {\n\tNFS_UNSTABLE = 0,\n\tNFS_DATA_SYNC = 1,\n\tNFS_FILE_SYNC = 2,\n\tNFS_INVALID_STABLE_HOW = -1,\n};\n\nenum nfs4_acl_type {\n\tNFS4ACL_NONE = 0,\n\tNFS4ACL_ACL = 1,\n\tNFS4ACL_DACL = 2,\n\tNFS4ACL_SACL = 3,\n};\n\nenum nfs4_callback_procnum {\n\tCB_NULL = 0,\n\tCB_COMPOUND = 1,\n};\n\nenum nfs4_change_attr_type {\n\tNFS4_CHANGE_TYPE_IS_MONOTONIC_INCR = 0,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER = 1,\n\tNFS4_CHANGE_TYPE_IS_VERSION_COUNTER_NOPNFS = 2,\n\tNFS4_CHANGE_TYPE_IS_TIME_METADATA = 3,\n\tNFS4_CHANGE_TYPE_IS_UNDEFINED = 4,\n};\n\nenum nfs4_client_state {\n\tNFS4CLNT_MANAGER_RUNNING = 0,\n\tNFS4CLNT_CHECK_LEASE = 1,\n\tNFS4CLNT_LEASE_EXPIRED = 2,\n\tNFS4CLNT_RECLAIM_REBOOT = 3,\n\tNFS4CLNT_RECLAIM_NOGRACE = 4,\n\tNFS4CLNT_DELEGRETURN = 5,\n\tNFS4CLNT_SESSION_RESET = 6,\n\tNFS4CLNT_LEASE_CONFIRM = 7,\n\tNFS4CLNT_SERVER_SCOPE_MISMATCH = 8,\n\tNFS4CLNT_PURGE_STATE = 9,\n\tNFS4CLNT_BIND_CONN_TO_SESSION = 10,\n\tNFS4CLNT_MOVED = 11,\n\tNFS4CLNT_LEASE_MOVED = 12,\n\tNFS4CLNT_DELEGATION_EXPIRED = 13,\n\tNFS4CLNT_RUN_MANAGER = 14,\n\tNFS4CLNT_MANAGER_AVAILABLE = 15,\n\tNFS4CLNT_RECALL_RUNNING = 16,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_READ = 17,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_RW = 18,\n\tNFS4CLNT_DELEGRETURN_DELAYED = 19,\n};\n\nenum nfs4_ff_op_type {\n\tNFS4_FF_OP_LAYOUTSTATS = 0,\n\tNFS4_FF_OP_LAYOUTRETURN = 1,\n};\n\nenum nfs4_open_delegation_type4 {\n\tNFS4_OPEN_DELEGATE_NONE = 0,\n\tNFS4_OPEN_DELEGATE_READ = 1,\n\tNFS4_OPEN_DELEGATE_WRITE = 2,\n\tNFS4_OPEN_DELEGATE_NONE_EXT = 3,\n\tNFS4_OPEN_DELEGATE_READ_ATTRS_DELEG = 4,\n\tNFS4_OPEN_DELEGATE_WRITE_ATTRS_DELEG = 5,\n};\n\nenum nfs4_session_state {\n\tNFS4_SESSION_INITING = 0,\n\tNFS4_SESSION_ESTABLISHED = 1,\n};\n\nenum nfs4_slot_tbl_state {\n\tNFS4_SLOT_TBL_DRAINING = 0,\n};\n\nenum nfs_cb_opnum4 {\n\tOP_CB_GETATTR = 3,\n\tOP_CB_RECALL = 4,\n\tOP_CB_LAYOUTRECALL = 5,\n\tOP_CB_NOTIFY = 6,\n\tOP_CB_PUSH_DELEG = 7,\n\tOP_CB_RECALL_ANY = 8,\n\tOP_CB_RECALLABLE_OBJ_AVAIL = 9,\n\tOP_CB_RECALL_SLOT = 10,\n\tOP_CB_SEQUENCE = 11,\n\tOP_CB_WANTS_CANCELLED = 12,\n\tOP_CB_NOTIFY_LOCK = 13,\n\tOP_CB_NOTIFY_DEVICEID = 14,\n\tOP_CB_OFFLOAD = 15,\n\tOP_CB_ILLEGAL = 10044,\n};\n\nenum nfs_ftype4 {\n\tNF4BAD = 0,\n\tNF4REG = 1,\n\tNF4DIR = 2,\n\tNF4BLK = 3,\n\tNF4CHR = 4,\n\tNF4LNK = 5,\n\tNF4SOCK = 6,\n\tNF4FIFO = 7,\n\tNF4ATTRDIR = 8,\n\tNF4NAMEDATTR = 9,\n};\n\nenum nfs_lock_status {\n\tNFS_LOCK_NOT_SET = 0,\n\tNFS_LOCK_LOCK = 1,\n\tNFS_LOCK_NOLOCK = 2,\n};\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_GETXATTR = 72,\n\tOP_SETXATTR = 73,\n\tOP_LISTXATTRS = 74,\n\tOP_REMOVEXATTR = 75,\n\tOP_ILLEGAL = 10044,\n};\n\nenum nfs_param {\n\tOpt_ac = 0,\n\tOpt_acdirmax = 1,\n\tOpt_acdirmin = 2,\n\tOpt_acl___2 = 3,\n\tOpt_acregmax = 4,\n\tOpt_acregmin = 5,\n\tOpt_actimeo = 6,\n\tOpt_addr = 7,\n\tOpt_bg = 8,\n\tOpt_bsize = 9,\n\tOpt_clientaddr = 10,\n\tOpt_cto = 11,\n\tOpt_alignwrite = 12,\n\tOpt_fatal_neterrors = 13,\n\tOpt_fg = 14,\n\tOpt_fscache = 15,\n\tOpt_fscache_flag = 16,\n\tOpt_hard = 17,\n\tOpt_intr = 18,\n\tOpt_local_lock = 19,\n\tOpt_lock = 20,\n\tOpt_lookupcache = 21,\n\tOpt_migration = 22,\n\tOpt_minorversion = 23,\n\tOpt_mountaddr = 24,\n\tOpt_mounthost = 25,\n\tOpt_mountport = 26,\n\tOpt_mountproto = 27,\n\tOpt_mountvers = 28,\n\tOpt_namelen = 29,\n\tOpt_nconnect = 30,\n\tOpt_max_connect = 31,\n\tOpt_port = 32,\n\tOpt_posix = 33,\n\tOpt_proto = 34,\n\tOpt_rdirplus = 35,\n\tOpt_rdirplus_none = 36,\n\tOpt_rdirplus_force = 37,\n\tOpt_rdma = 38,\n\tOpt_resvport = 39,\n\tOpt_retrans = 40,\n\tOpt_retry = 41,\n\tOpt_rsize = 42,\n\tOpt_sec = 43,\n\tOpt_sharecache = 44,\n\tOpt_sloppy = 45,\n\tOpt_soft = 46,\n\tOpt_softerr = 47,\n\tOpt_softreval = 48,\n\tOpt_source___2 = 49,\n\tOpt_tcp = 50,\n\tOpt_timeo = 51,\n\tOpt_trunkdiscovery = 52,\n\tOpt_udp = 53,\n\tOpt_v = 54,\n\tOpt_vers = 55,\n\tOpt_wsize = 56,\n\tOpt_write = 57,\n\tOpt_xprtsec = 58,\n\tOpt_cert_serial = 59,\n\tOpt_privkey_serial = 60,\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nenum nfs_stat_bytecounters {\n\tNFSIOS_NORMALREADBYTES = 0,\n\tNFSIOS_NORMALWRITTENBYTES = 1,\n\tNFSIOS_DIRECTREADBYTES = 2,\n\tNFSIOS_DIRECTWRITTENBYTES = 3,\n\tNFSIOS_SERVERREADBYTES = 4,\n\tNFSIOS_SERVERWRITTENBYTES = 5,\n\tNFSIOS_READPAGES = 6,\n\tNFSIOS_WRITEPAGES = 7,\n\t__NFSIOS_BYTESMAX = 8,\n};\n\nenum nfs_stat_eventcounters {\n\tNFSIOS_INODEREVALIDATE = 0,\n\tNFSIOS_DENTRYREVALIDATE = 1,\n\tNFSIOS_DATAINVALIDATE = 2,\n\tNFSIOS_ATTRINVALIDATE = 3,\n\tNFSIOS_VFSOPEN = 4,\n\tNFSIOS_VFSLOOKUP = 5,\n\tNFSIOS_VFSACCESS = 6,\n\tNFSIOS_VFSUPDATEPAGE = 7,\n\tNFSIOS_VFSREADPAGE = 8,\n\tNFSIOS_VFSREADPAGES = 9,\n\tNFSIOS_VFSWRITEPAGE = 10,\n\tNFSIOS_VFSWRITEPAGES = 11,\n\tNFSIOS_VFSGETDENTS = 12,\n\tNFSIOS_VFSSETATTR = 13,\n\tNFSIOS_VFSFLUSH = 14,\n\tNFSIOS_VFSFSYNC = 15,\n\tNFSIOS_VFSLOCK = 16,\n\tNFSIOS_VFSRELEASE = 17,\n\tNFSIOS_CONGESTIONWAIT = 18,\n\tNFSIOS_SETATTRTRUNC = 19,\n\tNFSIOS_EXTENDWRITE = 20,\n\tNFSIOS_SILLYRENAME = 21,\n\tNFSIOS_SHORTREAD = 22,\n\tNFSIOS_SHORTWRITE = 23,\n\tNFSIOS_DELAY = 24,\n\tNFSIOS_PNFS_READ = 25,\n\tNFSIOS_PNFS_WRITE = 26,\n\t__NFSIOS_COUNTSMAX = 27,\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n\tNFS4ERR_NOXATTR = 10095,\n\tNFS4ERR_XATTR2BIG = 10096,\n\tNFS4ERR_FIRST_FREE = 10097,\n};\n\nenum nh_notifier_info_type {\n\tNH_NOTIFIER_INFO_TYPE_SINGLE = 0,\n\tNH_NOTIFIER_INFO_TYPE_GRP = 1,\n\tNH_NOTIFIER_INFO_TYPE_RES_TABLE = 2,\n\tNH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3,\n\tNH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4,\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_RANGE_WARN_TOO_LONG = 2,\n\tNLA_VALIDATE_MIN = 3,\n\tNLA_VALIDATE_MAX = 4,\n\tNLA_VALIDATE_MASK = 5,\n\tNLA_VALIDATE_RANGE_PTR = 6,\n\tNLA_VALIDATE_FUNCTION = 7,\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\tNLMSGERR_ATTR_POLICY = 4,\n\tNLMSGERR_ATTR_MISS_TYPE = 5,\n\tNLMSGERR_ATTR_MISS_NEST = 6,\n\t__NLMSGERR_ATTR_MAX = 7,\n\tNLMSGERR_ATTR_MAX = 6,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE_B = 5,\n\tNR_SLAB_UNRECLAIMABLE_B = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT_BASE = 10,\n\tWORKINGSET_REFAULT_ANON = 10,\n\tWORKINGSET_REFAULT_FILE = 11,\n\tWORKINGSET_ACTIVATE_BASE = 12,\n\tWORKINGSET_ACTIVATE_ANON = 12,\n\tWORKINGSET_ACTIVATE_FILE = 13,\n\tWORKINGSET_RESTORE_BASE = 14,\n\tWORKINGSET_RESTORE_ANON = 14,\n\tWORKINGSET_RESTORE_FILE = 15,\n\tWORKINGSET_NODERECLAIM = 16,\n\tNR_ANON_MAPPED = 17,\n\tNR_FILE_MAPPED = 18,\n\tNR_FILE_PAGES = 19,\n\tNR_FILE_DIRTY = 20,\n\tNR_WRITEBACK = 21,\n\tNR_SHMEM = 22,\n\tNR_SHMEM_THPS = 23,\n\tNR_SHMEM_PMDMAPPED = 24,\n\tNR_FILE_THPS = 25,\n\tNR_FILE_PMDMAPPED = 26,\n\tNR_ANON_THPS = 27,\n\tNR_VMSCAN_WRITE = 28,\n\tNR_VMSCAN_IMMEDIATE = 29,\n\tNR_DIRTIED = 30,\n\tNR_WRITTEN = 31,\n\tNR_THROTTLED_WRITTEN = 32,\n\tNR_KERNEL_MISC_RECLAIMABLE = 33,\n\tNR_FOLL_PIN_ACQUIRED = 34,\n\tNR_FOLL_PIN_RELEASED = 35,\n\tNR_KERNEL_STACK_KB = 36,\n\tNR_PAGETABLE = 37,\n\tNR_SECONDARY_PAGETABLE = 38,\n\tNR_IOMMU_PAGES = 39,\n\tNR_SWAPCACHE = 40,\n\tPGPROMOTE_SUCCESS = 41,\n\tPGPROMOTE_CANDIDATE = 42,\n\tPGPROMOTE_CANDIDATE_NRL = 43,\n\tPGDEMOTE_KSWAPD = 44,\n\tPGDEMOTE_DIRECT = 45,\n\tPGDEMOTE_KHUGEPAGED = 46,\n\tPGDEMOTE_PROACTIVE = 47,\n\tNR_HUGETLB = 48,\n\tNR_BALLOON_PAGES = 49,\n\tNR_KERNEL_FILE_PAGES = 50,\n\tNR_VM_NODE_STAT_ITEMS = 51,\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 2,\n\tN_MEMORY = 3,\n\tN_CPU = 4,\n\tN_GENERIC_INITIATOR = 5,\n\tNR_NODE_STATES = 6,\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nenum ns_type {\n\tTIME_NS = 128,\n\tMNT_NS = 131072,\n\tCGROUP_NS = 33554432,\n\tUTS_NS = 67108864,\n\tIPC_NS = 134217728,\n\tUSER_NS = 268435456,\n\tPID_NS = 536870912,\n\tNET_NS = 1073741824,\n};\n\nenum numa_faults_stats {\n\tNUMA_MEM = 0,\n\tNUMA_CPU = 1,\n\tNUMA_MEMBUF = 2,\n\tNUMA_CPUBUF = 3,\n};\n\nenum numa_stat_item {\n\tNUMA_HIT = 0,\n\tNUMA_MISS = 1,\n\tNUMA_FOREIGN = 2,\n\tNUMA_INTERLEAVE_HIT = 3,\n\tNUMA_LOCAL = 4,\n\tNUMA_OTHER = 5,\n\tNR_VM_NUMA_EVENT_ITEMS = 6,\n};\n\nenum numa_topology_type {\n\tNUMA_DIRECT = 0,\n\tNUMA_GLUELESS_MESH = 1,\n\tNUMA_BACKPLANE = 2,\n};\n\nenum numa_type {\n\tnode_has_spare = 0,\n\tnode_fully_busy = 1,\n\tnode_overloaded = 2,\n};\n\nenum numa_vmaskip_reason {\n\tNUMAB_SKIP_UNSUITABLE = 0,\n\tNUMAB_SKIP_SHARED_RO = 1,\n\tNUMAB_SKIP_INACCESSIBLE = 2,\n\tNUMAB_SKIP_SCAN_DELAY = 3,\n\tNUMAB_SKIP_PID_INACTIVE = 4,\n\tNUMAB_SKIP_IGNORE_PID = 5,\n\tNUMAB_SKIP_SEQ_COMPLETED = 6,\n};\n\nenum nvdimm_claim_class {\n\tNVDIMM_CCLASS_NONE = 0,\n\tNVDIMM_CCLASS_BTT = 1,\n\tNVDIMM_CCLASS_BTT2 = 2,\n\tNVDIMM_CCLASS_PFN = 3,\n\tNVDIMM_CCLASS_DAX = 4,\n\tNVDIMM_CCLASS_UNKNOWN = 5,\n};\n\nenum nvdimm_event {\n\tNVDIMM_REVALIDATE_POISON = 0,\n\tNVDIMM_REVALIDATE_REGION = 1,\n};\n\nenum nvdimm_fwa_capability {\n\tNVDIMM_FWA_CAP_INVALID = 0,\n\tNVDIMM_FWA_CAP_NONE = 1,\n\tNVDIMM_FWA_CAP_QUIESCE = 2,\n\tNVDIMM_FWA_CAP_LIVE = 3,\n};\n\nenum nvdimm_fwa_result {\n\tNVDIMM_FWA_RESULT_INVALID = 0,\n\tNVDIMM_FWA_RESULT_NONE = 1,\n\tNVDIMM_FWA_RESULT_SUCCESS = 2,\n\tNVDIMM_FWA_RESULT_NOTSTAGED = 3,\n\tNVDIMM_FWA_RESULT_NEEDRESET = 4,\n\tNVDIMM_FWA_RESULT_FAIL = 5,\n};\n\nenum nvdimm_fwa_state {\n\tNVDIMM_FWA_INVALID = 0,\n\tNVDIMM_FWA_IDLE = 1,\n\tNVDIMM_FWA_ARMED = 2,\n\tNVDIMM_FWA_BUSY = 3,\n\tNVDIMM_FWA_ARM_OVERFLOW = 4,\n};\n\nenum nvdimm_fwa_trigger {\n\tNVDIMM_FWA_ARM = 0,\n\tNVDIMM_FWA_DISARM = 1,\n};\n\nenum nvdimm_passphrase_type {\n\tNVDIMM_USER = 0,\n\tNVDIMM_MASTER = 1,\n};\n\nenum nvdimm_security_bits {\n\tNVDIMM_SECURITY_DISABLED = 0,\n\tNVDIMM_SECURITY_UNLOCKED = 1,\n\tNVDIMM_SECURITY_LOCKED = 2,\n\tNVDIMM_SECURITY_FROZEN = 3,\n\tNVDIMM_SECURITY_OVERWRITE = 4,\n};\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n\tNVMEM_TYPE_FRAM = 4,\n};\n\nenum oatc14_hdd_status {\n\tOATC14_HDD_STATUS_CABLE_OK = 0,\n\tOATC14_HDD_STATUS_OPEN = 1,\n\tOATC14_HDD_STATUS_SHORT = 2,\n\tOATC14_HDD_STATUS_NOT_DETECTABLE = 3,\n};\n\nenum objext_flags {\n\tOBJEXTS_ALLOC_FAIL = 1,\n\t__OBJEXTS_FLAG_UNUSED = 4,\n\t__NR_OBJEXTS_FLAGS = 8,\n};\n\nenum of_reconfig_change {\n\tOF_RECONFIG_NO_CHANGE = 0,\n\tOF_RECONFIG_CHANGE_ADD = 1,\n\tOF_RECONFIG_CHANGE_REMOVE = 2,\n};\n\nenum offload_act_command {\n\tFLOW_ACT_REPLACE = 0,\n\tFLOW_ACT_DESTROY = 1,\n\tFLOW_ACT_STATS = 2,\n};\n\nenum ohci_rh_state {\n\tOHCI_RH_HALTED = 0,\n\tOHCI_RH_SUSPENDED = 1,\n\tOHCI_RH_RUNNING = 2,\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nenum opal_async_token_state {\n\tASYNC_TOKEN_UNALLOCATED = 0,\n\tASYNC_TOKEN_ALLOCATED = 1,\n\tASYNC_TOKEN_DISPATCHED = 2,\n\tASYNC_TOKEN_ABANDONED = 3,\n\tASYNC_TOKEN_COMPLETED = 4,\n};\n\nenum opal_mpipl_ops {\n\tOPAL_MPIPL_ADD_RANGE = 0,\n\tOPAL_MPIPL_REMOVE_RANGE = 1,\n\tOPAL_MPIPL_REMOVE_ALL = 2,\n\tOPAL_MPIPL_FREE_PRESERVED_MEMORY = 3,\n};\n\nenum opal_mpipl_tags {\n\tOPAL_MPIPL_TAG_CPU = 0,\n\tOPAL_MPIPL_TAG_OPAL = 1,\n\tOPAL_MPIPL_TAG_KERNEL = 2,\n\tOPAL_MPIPL_TAG_BOOT_MEM = 3,\n};\n\nenum opal_msg_type {\n\tOPAL_MSG_ASYNC_COMP = 0,\n\tOPAL_MSG_MEM_ERR = 1,\n\tOPAL_MSG_EPOW = 2,\n\tOPAL_MSG_SHUTDOWN = 3,\n\tOPAL_MSG_HMI_EVT = 4,\n\tOPAL_MSG_DPO = 5,\n\tOPAL_MSG_PRD = 6,\n\tOPAL_MSG_OCC = 7,\n\tOPAL_MSG_PRD2 = 8,\n\tOPAL_MSG_TYPE_MAX = 9,\n};\n\nenum open_claim_type4 {\n\tNFS4_OPEN_CLAIM_NULL = 0,\n\tNFS4_OPEN_CLAIM_PREVIOUS = 1,\n\tNFS4_OPEN_CLAIM_DELEGATE_CUR = 2,\n\tNFS4_OPEN_CLAIM_DELEGATE_PREV = 3,\n\tNFS4_OPEN_CLAIM_FH = 4,\n\tNFS4_OPEN_CLAIM_DELEG_CUR_FH = 5,\n\tNFS4_OPEN_CLAIM_DELEG_PREV_FH = 6,\n};\n\nenum opentype4 {\n\tNFS4_OPEN_NOCREATE = 0,\n\tNFS4_OPEN_CREATE = 1,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nenum packet_sock_flags {\n\tPACKET_SOCK_ORIGDEV = 0,\n\tPACKET_SOCK_AUXDATA = 1,\n\tPACKET_SOCK_TX_HAS_OFF = 2,\n\tPACKET_SOCK_TP_LOSS = 3,\n\tPACKET_SOCK_RUNNING = 4,\n\tPACKET_SOCK_PRESSURE = 5,\n\tPACKET_SOCK_QDISC_BYPASS = 6,\n};\n\nenum page_ext_flags {\n\tPAGE_EXT_OWNER = 0,\n\tPAGE_EXT_OWNER_ALLOCATED = 1,\n};\n\nenum page_memcg_data_flags {\n\tMEMCG_DATA_OBJEXTS = 1,\n\tMEMCG_DATA_KMEM = 2,\n\t__NR_MEMCG_DATA_FLAGS = 4,\n};\n\nenum page_size_enum {\n\t__PAGE_SIZE = 65536,\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nenum page_walk_lock {\n\tPGWALK_RDLOCK = 0,\n\tPGWALK_WRLOCK = 1,\n\tPGWALK_WRLOCK_VERIFY = 2,\n\tPGWALK_VMA_RDLOCK_VERIFY = 3,\n};\n\nenum pageblock_bits {\n\tPB_migrate_0 = 0,\n\tPB_migrate_1 = 1,\n\tPB_migrate_2 = 2,\n\tPB_compact_skip = 3,\n\tPB_migrate_isolate = 4,\n\t__NR_PAGEBLOCK_BITS = 5,\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_writeback = 1,\n\tPG_referenced = 2,\n\tPG_uptodate = 3,\n\tPG_dirty = 4,\n\tPG_lru = 5,\n\tPG_head = 6,\n\tPG_waiters = 7,\n\tPG_active = 8,\n\tPG_workingset = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_owner_2 = 11,\n\tPG_arch_1 = 12,\n\tPG_reserved = 13,\n\tPG_private = 14,\n\tPG_private_2 = 15,\n\tPG_reclaim = 16,\n\tPG_swapbacked = 17,\n\tPG_unevictable = 18,\n\tPG_dropbehind = 19,\n\tPG_mlocked = 20,\n\t__NR_PAGEFLAGS = 21,\n\tPG_readahead = 16,\n\tPG_swapcache = 10,\n\tPG_checked = 10,\n\tPG_anon_exclusive = 11,\n\tPG_mappedtodisk = 11,\n\tPG_fscache = 15,\n\tPG_pinned = 10,\n\tPG_savepinned = 4,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_movable_ops_isolated = 16,\n\tPG_movable_ops = 3,\n\tPG_reported = 3,\n\tPG_vmemmap_self_hosted = 10,\n\tPG_has_hwpoisoned = 8,\n\tPG_large_rmappable = 9,\n\tPG_partially_mapped = 16,\n};\n\nenum pagetype {\n\tPGTY_buddy = 240,\n\tPGTY_offline = 241,\n\tPGTY_table = 242,\n\tPGTY_guard = 243,\n\tPGTY_hugetlb = 244,\n\tPGTY_slab = 245,\n\tPGTY_zsmalloc = 246,\n\tPGTY_unaccepted = 247,\n\tPGTY_large_kmalloc = 248,\n\tPGTY_mapcount_underflow = 255,\n};\n\nenum partition_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_enablei = 1,\n\tpartcmd_disable = 2,\n\tpartcmd_update = 3,\n\tpartcmd_invalidate = 4,\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nenum pb_isolate_mode {\n\tPB_ISOLATE_MODE_MEM_OFFLINE = 0,\n\tPB_ISOLATE_MODE_CMA_ALLOC = 1,\n\tPB_ISOLATE_MODE_OTHER = 2,\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_15625000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_oxsemi = 71,\n\tpbn_oxsemi_1_15625000 = 72,\n\tpbn_oxsemi_2_15625000 = 73,\n\tpbn_oxsemi_4_15625000 = 74,\n\tpbn_oxsemi_8_15625000 = 75,\n\tpbn_intel_i960 = 76,\n\tpbn_sgi_ioc3 = 77,\n\tpbn_computone_4 = 78,\n\tpbn_computone_6 = 79,\n\tpbn_computone_8 = 80,\n\tpbn_sbsxrsio = 81,\n\tpbn_pasemi_1682M = 82,\n\tpbn_ni8430_2 = 83,\n\tpbn_ni8430_4 = 84,\n\tpbn_ni8430_8 = 85,\n\tpbn_ni8430_16 = 86,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 87,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 90,\n\tpbn_ce4100_1_115200 = 91,\n\tpbn_omegapci = 92,\n\tpbn_NETMOS9900_2s_115200 = 93,\n\tpbn_brcm_trumanage = 94,\n\tpbn_fintek_4 = 95,\n\tpbn_fintek_8 = 96,\n\tpbn_fintek_12 = 97,\n\tpbn_fintek_F81504A = 98,\n\tpbn_fintek_F81508A = 99,\n\tpbn_fintek_F81512A = 100,\n\tpbn_wch382_2 = 101,\n\tpbn_wch384_4 = 102,\n\tpbn_wch384_8 = 103,\n\tpbn_sunix_pci_1s = 104,\n\tpbn_sunix_pci_2s = 105,\n\tpbn_sunix_pci_4s = 106,\n\tpbn_sunix_pci_8s = 107,\n\tpbn_sunix_pci_16s = 108,\n\tpbn_titan_1_4000000 = 109,\n\tpbn_titan_2_4000000 = 110,\n\tpbn_titan_4_4000000 = 111,\n\tpbn_titan_8_4000000 = 112,\n\tpbn_moxa_2 = 113,\n\tpbn_moxa_4 = 114,\n\tpbn_moxa_8 = 115,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCIE_SPEED_64_0GT = 25,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n\tPCI_DEV_FLAGS_HAS_MSI_MASKING = 4096,\n\tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = 8192,\n\tPCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = 16384,\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nenum pci_hotplug_event {\n\tPCI_HOTPLUG_LINK_UP = 0,\n\tPCI_HOTPLUG_LINK_DOWN = 1,\n\tPCI_HOTPLUG_CARD_PRESENT = 2,\n\tPCI_HOTPLUG_CARD_NOT_PRESENT = 3,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_p2pdma_map_type {\n\tPCI_P2PDMA_MAP_UNKNOWN = 0,\n\tPCI_P2PDMA_MAP_NONE = 1,\n\tPCI_P2PDMA_MAP_NOT_SUPPORTED = 2,\n\tPCI_P2PDMA_MAP_BUS_ADDR = 3,\n\tPCI_P2PDMA_MAP_THRU_HOST_BRIDGE = 4,\n};\n\nenum pci_search_direction {\n\tPCI_SEARCH_FORWARD = 0,\n\tPCI_SEARCH_REVERSE = 1,\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nenum pcie_link_change_reason {\n\tPCIE_LINK_RETRAIN = 0,\n\tPCIE_ADD_BUS = 1,\n\tPCIE_BWCTRL_ENABLE = 2,\n\tPCIE_BWCTRL_IRQ = 3,\n\tPCIE_HOTPLUG = 4,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcim_addr_devres_type {\n\tPCIM_ADDR_DEVRES_TYPE_INVALID = 0,\n\tPCIM_ADDR_DEVRES_TYPE_REGION = 1,\n\tPCIM_ADDR_DEVRES_TYPE_REGION_MAPPING = 2,\n\tPCIM_ADDR_DEVRES_TYPE_MAPPING = 3,\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nenum pedit_cmd {\n\tTCA_PEDIT_KEY_EX_CMD_SET = 0,\n\tTCA_PEDIT_KEY_EX_CMD_ADD = 1,\n\t__PEDIT_CMD_MAX = 2,\n};\n\nenum pedit_header_type {\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK = 0,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_ETH = 1,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP4 = 2,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP6 = 3,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_TCP = 4,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_UDP = 5,\n\t__PEDIT_HDR_TYPE_MAX = 6,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE = 262144,\n\tPERF_SAMPLE_BRANCH_COUNTERS = 524288,\n\tPERF_SAMPLE_BRANCH_MAX = 1048576,\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,\n\tPERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 20,\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 18446744073709551584ULL,\n\tPERF_CONTEXT_KERNEL = 18446744073709551488ULL,\n\tPERF_CONTEXT_USER = 18446744073709551104ULL,\n\tPERF_CONTEXT_USER_DEFERRED = 18446744073709550976ULL,\n\tPERF_CONTEXT_GUEST = 18446744073709549568ULL,\n\tPERF_CONTEXT_GUEST_KERNEL = 18446744073709549440ULL,\n\tPERF_CONTEXT_GUEST_USER = 18446744073709549056ULL,\n\tPERF_CONTEXT_MAX = 18446744073709547521ULL,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nenum perf_event_powerpc_regs {\n\tPERF_REG_POWERPC_R0 = 0,\n\tPERF_REG_POWERPC_R1 = 1,\n\tPERF_REG_POWERPC_R2 = 2,\n\tPERF_REG_POWERPC_R3 = 3,\n\tPERF_REG_POWERPC_R4 = 4,\n\tPERF_REG_POWERPC_R5 = 5,\n\tPERF_REG_POWERPC_R6 = 6,\n\tPERF_REG_POWERPC_R7 = 7,\n\tPERF_REG_POWERPC_R8 = 8,\n\tPERF_REG_POWERPC_R9 = 9,\n\tPERF_REG_POWERPC_R10 = 10,\n\tPERF_REG_POWERPC_R11 = 11,\n\tPERF_REG_POWERPC_R12 = 12,\n\tPERF_REG_POWERPC_R13 = 13,\n\tPERF_REG_POWERPC_R14 = 14,\n\tPERF_REG_POWERPC_R15 = 15,\n\tPERF_REG_POWERPC_R16 = 16,\n\tPERF_REG_POWERPC_R17 = 17,\n\tPERF_REG_POWERPC_R18 = 18,\n\tPERF_REG_POWERPC_R19 = 19,\n\tPERF_REG_POWERPC_R20 = 20,\n\tPERF_REG_POWERPC_R21 = 21,\n\tPERF_REG_POWERPC_R22 = 22,\n\tPERF_REG_POWERPC_R23 = 23,\n\tPERF_REG_POWERPC_R24 = 24,\n\tPERF_REG_POWERPC_R25 = 25,\n\tPERF_REG_POWERPC_R26 = 26,\n\tPERF_REG_POWERPC_R27 = 27,\n\tPERF_REG_POWERPC_R28 = 28,\n\tPERF_REG_POWERPC_R29 = 29,\n\tPERF_REG_POWERPC_R30 = 30,\n\tPERF_REG_POWERPC_R31 = 31,\n\tPERF_REG_POWERPC_NIP = 32,\n\tPERF_REG_POWERPC_MSR = 33,\n\tPERF_REG_POWERPC_ORIG_R3 = 34,\n\tPERF_REG_POWERPC_CTR = 35,\n\tPERF_REG_POWERPC_LINK = 36,\n\tPERF_REG_POWERPC_XER = 37,\n\tPERF_REG_POWERPC_CCR = 38,\n\tPERF_REG_POWERPC_SOFTE = 39,\n\tPERF_REG_POWERPC_TRAP = 40,\n\tPERF_REG_POWERPC_DAR = 41,\n\tPERF_REG_POWERPC_DSISR = 42,\n\tPERF_REG_POWERPC_SIER = 43,\n\tPERF_REG_POWERPC_MMCRA = 44,\n\tPERF_REG_POWERPC_MMCR0 = 45,\n\tPERF_REG_POWERPC_MMCR1 = 46,\n\tPERF_REG_POWERPC_MMCR2 = 47,\n\tPERF_REG_POWERPC_MMCR3 = 48,\n\tPERF_REG_POWERPC_SIER2 = 49,\n\tPERF_REG_POWERPC_SIER3 = 50,\n\tPERF_REG_POWERPC_PMC1 = 51,\n\tPERF_REG_POWERPC_PMC2 = 52,\n\tPERF_REG_POWERPC_PMC3 = 53,\n\tPERF_REG_POWERPC_PMC4 = 54,\n\tPERF_REG_POWERPC_PMC5 = 55,\n\tPERF_REG_POWERPC_PMC6 = 56,\n\tPERF_REG_POWERPC_SDAR = 57,\n\tPERF_REG_POWERPC_SIAR = 58,\n\tPERF_REG_POWERPC_MAX = 45,\n\tPERF_REG_EXTENDED_MAX = 59,\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_LOST = 16,\n\tPERF_FORMAT_MAX = 32,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_DATA_PAGE_SIZE = 4194304,\n\tPERF_SAMPLE_CODE_PAGE_SIZE = 8388608,\n\tPERF_SAMPLE_WEIGHT_STRUCT = 16777216,\n\tPERF_SAMPLE_MAX = 33554432,\n};\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = -5,\n\tPERF_EVENT_STATE_REVOKED = -4,\n\tPERF_EVENT_STATE_EXIT = -3,\n\tPERF_EVENT_STATE_ERROR = -2,\n\tPERF_EVENT_STATE_OFF = -1,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = -1,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_TEXT_POKE = 20,\n\tPERF_RECORD_AUX_OUTPUT_HW_ID = 21,\n\tPERF_RECORD_CALLCHAIN_DEFERRED = 22,\n\tPERF_RECORD_MAX = 23,\n};\n\nenum perf_hw_cache_id {\n\tPERF_COUNT_HW_CACHE_L1D = 0,\n\tPERF_COUNT_HW_CACHE_L1I = 1,\n\tPERF_COUNT_HW_CACHE_LL = 2,\n\tPERF_COUNT_HW_CACHE_DTLB = 3,\n\tPERF_COUNT_HW_CACHE_ITLB = 4,\n\tPERF_COUNT_HW_CACHE_BPU = 5,\n\tPERF_COUNT_HW_CACHE_NODE = 6,\n\tPERF_COUNT_HW_CACHE_MAX = 7,\n};\n\nenum perf_hw_cache_op_id {\n\tPERF_COUNT_HW_CACHE_OP_READ = 0,\n\tPERF_COUNT_HW_CACHE_OP_WRITE = 1,\n\tPERF_COUNT_HW_CACHE_OP_PREFETCH = 2,\n\tPERF_COUNT_HW_CACHE_OP_MAX = 3,\n};\n\nenum perf_hw_cache_op_result_id {\n\tPERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,\n\tPERF_COUNT_HW_CACHE_RESULT_MISS = 1,\n\tPERF_COUNT_HW_CACHE_RESULT_MAX = 2,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_pmu_scope {\n\tPERF_PMU_SCOPE_NONE = 0,\n\tPERF_PMU_SCOPE_CORE = 1,\n\tPERF_PMU_SCOPE_DIE = 2,\n\tPERF_PMU_SCOPE_CLUSTER = 3,\n\tPERF_PMU_SCOPE_PKG = 4,\n\tPERF_PMU_SCOPE_SYS_WIDE = 5,\n\tPERF_PMU_MAX_SCOPE = 6,\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_OOL = 2,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 3,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_CGROUP_SWITCHES = 11,\n\tPERF_COUNT_SW_MAX = 12,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum pgdat_flags {\n\tPGDAT_WRITEBACK = 0,\n\tPGDAT_RECLAIM_LOCKED = 1,\n};\n\nenum pgt_entry {\n\tNORMAL_PMD = 0,\n\tHPAGE_PMD = 1,\n\tNORMAL_PUD = 2,\n\tHPAGE_PUD = 3,\n};\n\nenum pgtable_index {\n\tPTE_INDEX = 0,\n\tPMD_INDEX = 1,\n\tPUD_INDEX = 2,\n\tPGD_INDEX = 3,\n\tHTLB_16M_INDEX = 4,\n\tHTLB_16G_INDEX = 5,\n};\n\nenum pgtable_level {\n\tPGTABLE_LEVEL_PTE = 0,\n\tPGTABLE_LEVEL_PMD = 1,\n\tPGTABLE_LEVEL_PUD = 2,\n\tPGTABLE_LEVEL_P4D = 3,\n\tPGTABLE_LEVEL_PGD = 4,\n};\n\nenum phy {\n\tphy_100a = 992,\n\tphy_100c = 55575208,\n\tphy_82555_tx = 22020776,\n\tphy_nsc_tx = 1543512064,\n\tphy_82562_et = 53478056,\n\tphy_82562_em = 52429480,\n\tphy_82562_ek = 51380904,\n\tphy_82562_eh = 24117928,\n\tphy_82552_v = 3496017997,\n\tphy_unknown = 4294967295,\n};\n\nenum phy_media {\n\tPHY_MEDIA_DEFAULT = 0,\n\tPHY_MEDIA_SR = 1,\n\tPHY_MEDIA_DAC = 2,\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n\tPHY_MODE_HDMI = 20,\n};\n\nenum phy_mse_channel {\n\tPHY_MSE_CHANNEL_A = 0,\n\tPHY_MSE_CHANNEL_B = 1,\n\tPHY_MSE_CHANNEL_C = 2,\n\tPHY_MSE_CHANNEL_D = 3,\n\tPHY_MSE_CHANNEL_WORST = 4,\n\tPHY_MSE_CHANNEL_LINK = 5,\n};\n\nenum phy_port_parent {\n\tPHY_PORT_PHY = 0,\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_ERROR = 3,\n\tPHY_UP = 4,\n\tPHY_RUNNING = 5,\n\tPHY_NOLINK = 6,\n\tPHY_CABLETEST = 7,\n};\n\nenum phy_state_work {\n\tPHY_STATE_WORK_NONE = 0,\n\tPHY_STATE_WORK_ANEG = 1,\n\tPHY_STATE_WORK_SUSPEND = 2,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nenum phy_ufs_state {\n\tPHY_UFS_HIBERN8_ENTER = 0,\n\tPHY_UFS_HIBERN8_EXIT = 1,\n};\n\nenum phy_upstream {\n\tPHY_UPSTREAM_MAC = 0,\n\tPHY_UPSTREAM_PHY = 1,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nenum pidcg_event {\n\tPIDCG_MAX = 0,\n\tPIDCG_FORKFAIL = 1,\n\tNR_PIDCG_EVENTS = 2,\n};\n\nenum pidfs_attr_mask_bits {\n\tPIDFS_ATTR_BIT_EXIT = 0,\n\tPIDFS_ATTR_BIT_COREDUMP = 1,\n};\n\nenum pkcs7_actions {\n\tACT_pkcs7_check_content_type = 0,\n\tACT_pkcs7_extract_cert = 1,\n\tACT_pkcs7_note_OID = 2,\n\tACT_pkcs7_note_certificate_list = 3,\n\tACT_pkcs7_note_content = 4,\n\tACT_pkcs7_note_data = 5,\n\tACT_pkcs7_note_signed_info = 6,\n\tACT_pkcs7_note_signeddata_version = 7,\n\tACT_pkcs7_note_signerinfo_version = 8,\n\tACT_pkcs7_sig_note_authenticated_attr = 9,\n\tACT_pkcs7_sig_note_digest_algo = 10,\n\tACT_pkcs7_sig_note_issuer = 11,\n\tACT_pkcs7_sig_note_pkey_algo = 12,\n\tACT_pkcs7_sig_note_serial = 13,\n\tACT_pkcs7_sig_note_set_of_authattrs = 14,\n\tACT_pkcs7_sig_note_signature = 15,\n\tACT_pkcs7_sig_note_skid = 16,\n\tNR__pkcs7_actions = 17,\n};\n\nenum pkey_id_type {\n\tPKEY_ID_PGP = 0,\n\tPKEY_ID_X509 = 1,\n\tPKEY_ID_PKCS7 = 2,\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nenum pldmfw_update_mode {\n\tPLDMFW_UPDATE_MODE_FULL = 0,\n\tPLDMFW_UPDATE_MODE_SINGLE_COMPONENT = 1,\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = -1,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nenum pnfs_block_extent_state {\n\tPNFS_BLOCK_READWRITE_DATA = 0,\n\tPNFS_BLOCK_READ_DATA = 1,\n\tPNFS_BLOCK_INVALID_DATA = 2,\n\tPNFS_BLOCK_NONE_DATA = 3,\n};\n\nenum pnfs_block_volume_type {\n\tPNFS_BLOCK_VOLUME_SIMPLE = 0,\n\tPNFS_BLOCK_VOLUME_SLICE = 1,\n\tPNFS_BLOCK_VOLUME_CONCAT = 2,\n\tPNFS_BLOCK_VOLUME_STRIPE = 3,\n\tPNFS_BLOCK_VOLUME_SCSI = 4,\n};\n\nenum pnfs_iomode {\n\tIOMODE_READ = 1,\n\tIOMODE_RW = 2,\n\tIOMODE_ANY = 3,\n};\n\nenum pnfs_layout_destroy_mode {\n\tPNFS_LAYOUT_INVALIDATE = 0,\n\tPNFS_LAYOUT_BULK_RETURN = 1,\n\tPNFS_LAYOUT_FILE_BULK_RETURN = 2,\n};\n\nenum pnfs_layoutreturn_type {\n\tRETURN_FILE = 1,\n\tRETURN_FSID = 2,\n\tRETURN_ALL = 3,\n};\n\nenum pnfs_layouttype {\n\tLAYOUT_NFSV4_1_FILES = 1,\n\tLAYOUT_OSD2_OBJECTS = 2,\n\tLAYOUT_BLOCK_VOLUME = 3,\n\tLAYOUT_FLEX_FILES = 4,\n\tLAYOUT_SCSI = 5,\n\tLAYOUT_TYPE_MAX = 6,\n};\n\nenum pnfs_notify_deviceid_type4 {\n\tNOTIFY_DEVICEID4_CHANGE = 2,\n\tNOTIFY_DEVICEID4_DELETE = 4,\n};\n\nenum pnfs_try_status {\n\tPNFS_ATTEMPTED = 0,\n\tPNFS_NOT_ATTEMPTED = 1,\n\tPNFS_TRY_AGAIN = 2,\n};\n\nenum pnfs_update_layout_reason {\n\tPNFS_UPDATE_LAYOUT_UNKNOWN = 0,\n\tPNFS_UPDATE_LAYOUT_NO_PNFS = 1,\n\tPNFS_UPDATE_LAYOUT_RD_ZEROLEN = 2,\n\tPNFS_UPDATE_LAYOUT_MDSTHRESH = 3,\n\tPNFS_UPDATE_LAYOUT_NOMEM = 4,\n\tPNFS_UPDATE_LAYOUT_BULK_RECALL = 5,\n\tPNFS_UPDATE_LAYOUT_IO_TEST_FAIL = 6,\n\tPNFS_UPDATE_LAYOUT_FOUND_CACHED = 7,\n\tPNFS_UPDATE_LAYOUT_RETURN = 8,\n\tPNFS_UPDATE_LAYOUT_RETRY = 9,\n\tPNFS_UPDATE_LAYOUT_BLOCKED = 10,\n\tPNFS_UPDATE_LAYOUT_INVALID_OPEN = 11,\n\tPNFS_UPDATE_LAYOUT_SEND_LAYOUTGET = 12,\n\tPNFS_UPDATE_LAYOUT_EXIT = 13,\n};\n\nenum pnv_phb_model {\n\tPNV_PHB_MODEL_UNKNOWN = 0,\n\tPNV_PHB_MODEL_P7IOC = 1,\n\tPNV_PHB_MODEL_PHB3 = 2,\n};\n\nenum pnv_phb_type {\n\tPNV_PHB_IODA2 = 0,\n\tPNV_PHB_NPU_OCAPI = 1,\n};\n\nenum policy_opt {\n\tOpt_measure = 0,\n\tOpt_dont_measure = 1,\n\tOpt_appraise = 2,\n\tOpt_dont_appraise = 3,\n\tOpt_audit = 4,\n\tOpt_dont_audit = 5,\n\tOpt_hash___2 = 6,\n\tOpt_dont_hash = 7,\n\tOpt_obj_user = 8,\n\tOpt_obj_role = 9,\n\tOpt_obj_type = 10,\n\tOpt_subj_user = 11,\n\tOpt_subj_role = 12,\n\tOpt_subj_type = 13,\n\tOpt_func = 14,\n\tOpt_mask = 15,\n\tOpt_fsmagic = 16,\n\tOpt_fsname = 17,\n\tOpt_fs_subtype = 18,\n\tOpt_fsuuid = 19,\n\tOpt_uid_eq = 20,\n\tOpt_euid_eq = 21,\n\tOpt_gid_eq = 22,\n\tOpt_egid_eq = 23,\n\tOpt_fowner_eq = 24,\n\tOpt_fgroup_eq = 25,\n\tOpt_uid_gt = 26,\n\tOpt_euid_gt = 27,\n\tOpt_gid_gt = 28,\n\tOpt_egid_gt = 29,\n\tOpt_fowner_gt = 30,\n\tOpt_fgroup_gt = 31,\n\tOpt_uid_lt = 32,\n\tOpt_euid_lt = 33,\n\tOpt_gid_lt = 34,\n\tOpt_egid_lt = 35,\n\tOpt_fowner_lt = 36,\n\tOpt_fgroup_lt = 37,\n\tOpt_digest_type = 38,\n\tOpt_appraise_type = 39,\n\tOpt_appraise_flag = 40,\n\tOpt_appraise_algos = 41,\n\tOpt_permit_directio = 42,\n\tOpt_pcr = 43,\n\tOpt_template = 44,\n\tOpt_keyrings = 45,\n\tOpt_label = 46,\n\tOpt_err___5 = 47,\n};\n\nenum policy_rule_list {\n\tIMA_DEFAULT_POLICY = 1,\n\tIMA_CUSTOM_POLICY = 2,\n};\n\nenum policy_types {\n\tORIGINAL_TCB = 1,\n\tDEFAULT_TCB = 2,\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\nenum pool_workqueue_stats {\n\tPWQ_STAT_STARTED = 0,\n\tPWQ_STAT_COMPLETED = 1,\n\tPWQ_STAT_CPU_TIME = 2,\n\tPWQ_STAT_CPU_INTENSIVE = 3,\n\tPWQ_STAT_CM_WAKEUP = 4,\n\tPWQ_STAT_REPATRIATED = 5,\n\tPWQ_STAT_MAYDAY = 6,\n\tPWQ_STAT_RESCUED = 7,\n\tPWQ_NR_STATS = 8,\n};\n\nenum port {\n\tsoftware_reset = 0,\n\tselftest = 1,\n\tselective_reset = 2,\n};\n\nenum port_pkey_state {\n\tIB_PORT_PKEY_NOT_VALID = 0,\n\tIB_PORT_PKEY_VALID = 1,\n\tIB_PORT_PKEY_LISTED = 2,\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum posix_timer_state {\n\tPOSIX_TIMER_DISARMED = 0,\n\tPOSIX_TIMER_ARMED = 1,\n\tPOSIX_TIMER_REQUEUE_PENDING = 2,\n};\n\nenum powerpc_pmc_type {\n\tPPC_PMC_DEFAULT = 0,\n\tPPC_PMC_IBM = 1,\n\tPPC_PMC_PA6T = 2,\n\tPPC_PMC_G4 = 3,\n};\n\nenum powerpc_regset {\n\tREGSET_GPR = 0,\n\tREGSET_FPR = 1,\n\tREGSET_VMX = 2,\n\tREGSET_VSX = 3,\n\tREGSET_TM_CGPR = 4,\n\tREGSET_TM_CFPR = 5,\n\tREGSET_TM_CVMX = 6,\n\tREGSET_TM_CVSX = 7,\n\tREGSET_TM_SPR = 8,\n\tREGSET_TM_CTAR = 9,\n\tREGSET_TM_CPPR = 10,\n\tREGSET_TM_CDSCR = 11,\n\tREGSET_PPR = 12,\n\tREGSET_DSCR = 13,\n\tREGSET_TAR = 14,\n\tREGSET_EBB = 15,\n\tREGSET_PMR = 16,\n\tREGSET_DEXCR = 17,\n\tREGSET_HASHKEYR = 18,\n\tREGSET_PKEY = 19,\n};\n\nenum ppc_dbell {\n\tPPC_DBELL = 0,\n\tPPC_DBELL_CRIT = 1,\n\tPPC_G_DBELL = 2,\n\tPPC_G_DBELL_CRIT = 3,\n\tPPC_G_DBELL_MC = 4,\n\tPPC_DBELL_SERVER = 5,\n};\n\nenum pr_direction {\n\tPR_IN = 0,\n\tPR_OUT = 1,\n};\n\nenum pr_status {\n\tPR_STS_SUCCESS = 0,\n\tPR_STS_IOERR = 2,\n\tPR_STS_RESERVATION_CONFLICT = 24,\n\tPR_STS_RETRY_PATH_FAILURE = 917504,\n\tPR_STS_PATH_FAST_FAILED = 983040,\n\tPR_STS_PATH_FAILED = 65536,\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nenum preempt_wakeup_action {\n\tPREEMPT_WAKEUP_NONE = 0,\n\tPREEMPT_WAKEUP_SHORT = 1,\n\tPREEMPT_WAKEUP_PICK = 2,\n\tPREEMPT_WAKEUP_RESCHED = 3,\n};\n\nenum prep_dispatch {\n\tPREP_DISPATCH_OK = 0,\n\tPREP_DISPATCH_NO_TAG = 1,\n\tPREP_DISPATCH_NO_BUDGET = 2,\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\nenum printk_info_flags {\n\tLOG_FORCE_CON = 1,\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nenum priv_stack_mode {\n\tPRIV_STACK_UNKNOWN = 0,\n\tNO_PRIV_STACK = 1,\n\tPRIV_STACK_ADAPTIVE = 2,\n};\n\nenum probe_print_type {\n\tPROBE_PRINT_NORMAL = 0,\n\tPROBE_PRINT_RETURN = 1,\n\tPROBE_PRINT_EVENT = 2,\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nenum proc_cn_event {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_NONZERO_EXIT = 536870912,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_mem_force {\n\tPROC_MEM_FORCE_ALWAYS = 0,\n\tPROC_MEM_FORCE_PTRACE = 1,\n\tPROC_MEM_FORCE_NEVER = 2,\n};\n\nenum proc_param {\n\tOpt_gid___7 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n\tOpt_pidns = 3,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nenum procfs_ino {\n\tPROCFS_ROOT_INO = 1,\n};\n\nenum procmap_query_flags {\n\tPROCMAP_QUERY_VMA_READABLE = 1,\n\tPROCMAP_QUERY_VMA_WRITABLE = 2,\n\tPROCMAP_QUERY_VMA_EXECUTABLE = 4,\n\tPROCMAP_QUERY_VMA_SHARED = 8,\n\tPROCMAP_QUERY_COVERING_OR_NEXT_VMA = 16,\n\tPROCMAP_QUERY_FILE_BACKED_VMA = 32,\n};\n\nenum prs_errcode {\n\tPERR_NONE = 0,\n\tPERR_INVCPUS = 1,\n\tPERR_INVPARENT = 2,\n\tPERR_NOTPART = 3,\n\tPERR_NOTEXCL = 4,\n\tPERR_NOCPUS = 5,\n\tPERR_HOTPLUG = 6,\n\tPERR_CPUSEMPTY = 7,\n\tPERR_HKEEPING = 8,\n\tPERR_ACCESS = 9,\n\tPERR_REMOTE = 10,\n};\n\nenum ps2_disposition {\n\tPS2_PROCESS = 0,\n\tPS2_IGNORE = 1,\n\tPS2_ERROR = 2,\n};\n\nenum psi_aggregators {\n\tPSI_AVGS = 0,\n\tPSI_POLL = 1,\n\tNR_PSI_AGGREGATORS = 2,\n};\n\nenum psi_res {\n\tPSI_IO = 0,\n\tPSI_MEM = 1,\n\tPSI_CPU = 2,\n\tNR_PSI_RESOURCES = 3,\n};\n\nenum psi_states {\n\tPSI_IO_SOME = 0,\n\tPSI_IO_FULL = 1,\n\tPSI_MEM_SOME = 2,\n\tPSI_MEM_FULL = 3,\n\tPSI_CPU_SOME = 4,\n\tPSI_CPU_FULL = 5,\n\tPSI_NONIDLE = 6,\n\tNR_PSI_STATES = 7,\n};\n\nenum psi_task_count {\n\tNR_IOWAIT = 0,\n\tNR_MEMSTALL = 1,\n\tNR_RUNNING = 2,\n\tNR_MEMSTALL_RUNNING = 3,\n\tNR_PSI_TASK_COUNTS = 4,\n};\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nenum pstore_type_id {\n\tPSTORE_TYPE_DMESG = 0,\n\tPSTORE_TYPE_MCE = 1,\n\tPSTORE_TYPE_CONSOLE = 2,\n\tPSTORE_TYPE_FTRACE = 3,\n\tPSTORE_TYPE_PPC_RTAS = 4,\n\tPSTORE_TYPE_PPC_OF = 5,\n\tPSTORE_TYPE_PPC_COMMON = 6,\n\tPSTORE_TYPE_PMSG = 7,\n\tPSTORE_TYPE_PPC_OPAL = 8,\n\tPSTORE_TYPE_MAX = 9,\n};\n\nenum pt_flags {\n\tPT_kernel = 2,\n\tPT_reserved = 13,\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_EXTOFF = 2,\n\tPTP_CLOCK_PPS = 3,\n\tPTP_CLOCK_PPSUSR = 4,\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nenum pubkey_algo {\n\tPUBKEY_ALGO_RSA = 0,\n\tPUBKEY_ALGO_MAX = 1,\n};\n\nenum qdisc_class_ops_flags {\n\tQDISC_CLASS_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n\t__QDISC_STATE_MISSED = 2,\n\t__QDISC_STATE_DRAINING = 3,\n};\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nenum r0layout {\n\tRAID0_ORIG_LAYOUT = 1,\n\tRAID0_ALT_MULTIZONE_LAYOUT = 2,\n};\n\nenum r1bio_state {\n\tR1BIO_Uptodate = 0,\n\tR1BIO_IsSync = 1,\n\tR1BIO_BehindIO = 2,\n\tR1BIO_ReadError = 3,\n\tR1BIO_Returned = 4,\n\tR1BIO_MadeGood = 5,\n\tR1BIO_WriteError = 6,\n\tR1BIO_FailFast = 7,\n};\n\nenum radeon_chip_flags {\n\tCHIP_FAMILY_MASK = 65535,\n\tCHIP_FLAGS_MASK = 4294901760,\n\tCHIP_IS_MOBILITY = 65536,\n\tCHIP_IS_IGP = 131072,\n\tCHIP_HAS_CRTC2 = 262144,\n};\n\nenum radeon_errata {\n\tCHIP_ERRATA_R300_CG = 1,\n\tCHIP_ERRATA_PLL_DUMMYREADS = 2,\n\tCHIP_ERRATA_PLL_DELAY = 4,\n};\n\nenum radeon_family {\n\tCHIP_FAMILY_UNKNOW = 0,\n\tCHIP_FAMILY_LEGACY = 1,\n\tCHIP_FAMILY_RADEON = 2,\n\tCHIP_FAMILY_RV100 = 3,\n\tCHIP_FAMILY_RS100 = 4,\n\tCHIP_FAMILY_RV200 = 5,\n\tCHIP_FAMILY_RS200 = 6,\n\tCHIP_FAMILY_R200 = 7,\n\tCHIP_FAMILY_RV250 = 8,\n\tCHIP_FAMILY_RS300 = 9,\n\tCHIP_FAMILY_RV280 = 10,\n\tCHIP_FAMILY_R300 = 11,\n\tCHIP_FAMILY_R350 = 12,\n\tCHIP_FAMILY_RV350 = 13,\n\tCHIP_FAMILY_RV380 = 14,\n\tCHIP_FAMILY_R420 = 15,\n\tCHIP_FAMILY_RC410 = 16,\n\tCHIP_FAMILY_RS400 = 17,\n\tCHIP_FAMILY_RS480 = 18,\n\tCHIP_FAMILY_LAST = 19,\n};\n\nenum radeon_montype {\n\tMT_NONE = 0,\n\tMT_CRT = 1,\n\tMT_LCD = 2,\n\tMT_DFP = 3,\n\tMT_CTV = 4,\n\tMT_STV = 5,\n};\n\nenum radeon_pm_mode {\n\tradeon_pm_none = 0,\n\tradeon_pm_d2 = 1,\n\tradeon_pm_off = 2,\n};\n\nenum ramfs_param {\n\tOpt_mode___6 = 0,\n};\n\nenum rdma_ah_attr_type {\n\tRDMA_AH_ATTR_TYPE_UNDEFINED = 0,\n\tRDMA_AH_ATTR_TYPE_IB = 1,\n\tRDMA_AH_ATTR_TYPE_ROCE = 2,\n\tRDMA_AH_ATTR_TYPE_OPA = 3,\n};\n\nenum rdma_driver_id {\n\tRDMA_DRIVER_UNKNOWN = 0,\n\tRDMA_DRIVER_MLX5 = 1,\n\tRDMA_DRIVER_MLX4 = 2,\n\tRDMA_DRIVER_CXGB3 = 3,\n\tRDMA_DRIVER_CXGB4 = 4,\n\tRDMA_DRIVER_MTHCA = 5,\n\tRDMA_DRIVER_BNXT_RE = 6,\n\tRDMA_DRIVER_OCRDMA = 7,\n\tRDMA_DRIVER_NES = 8,\n\tRDMA_DRIVER_I40IW = 9,\n\tRDMA_DRIVER_IRDMA = 9,\n\tRDMA_DRIVER_VMW_PVRDMA = 10,\n\tRDMA_DRIVER_QEDR = 11,\n\tRDMA_DRIVER_HNS = 12,\n\tRDMA_DRIVER_USNIC = 13,\n\tRDMA_DRIVER_RXE = 14,\n\tRDMA_DRIVER_HFI1 = 15,\n\tRDMA_DRIVER_QIB = 16,\n\tRDMA_DRIVER_EFA = 17,\n\tRDMA_DRIVER_SIW = 18,\n\tRDMA_DRIVER_ERDMA = 19,\n\tRDMA_DRIVER_MANA = 20,\n\tRDMA_DRIVER_IONIC = 21,\n};\n\nenum rdma_link_layer {\n\tIB_LINK_LAYER_UNSPECIFIED = 0,\n\tIB_LINK_LAYER_INFINIBAND = 1,\n\tIB_LINK_LAYER_ETHERNET = 2,\n};\n\nenum rdma_netdev_t {\n\tRDMA_NETDEV_OPA_VNIC = 0,\n\tRDMA_NETDEV_IPOIB = 1,\n};\n\nenum rdma_nl_counter_mask {\n\tRDMA_COUNTER_MASK_QP_TYPE = 1,\n\tRDMA_COUNTER_MASK_PID = 2,\n};\n\nenum rdma_nl_counter_mode {\n\tRDMA_COUNTER_MODE_NONE = 0,\n\tRDMA_COUNTER_MODE_AUTO = 1,\n\tRDMA_COUNTER_MODE_MANUAL = 2,\n\tRDMA_COUNTER_MODE_MAX = 3,\n};\n\nenum rdma_nl_dev_type {\n\tRDMA_DEVICE_TYPE_SMI = 1,\n};\n\nenum rdma_nl_name_assign_type {\n\tRDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0,\n\tRDMA_NAME_ASSIGN_TYPE_USER = 1,\n};\n\nenum rdma_restrack_type {\n\tRDMA_RESTRACK_PD = 0,\n\tRDMA_RESTRACK_CQ = 1,\n\tRDMA_RESTRACK_QP = 2,\n\tRDMA_RESTRACK_CM_ID = 3,\n\tRDMA_RESTRACK_MR = 4,\n\tRDMA_RESTRACK_CTX = 5,\n\tRDMA_RESTRACK_COUNTER = 6,\n\tRDMA_RESTRACK_SRQ = 7,\n\tRDMA_RESTRACK_DMAH = 8,\n\tRDMA_RESTRACK_MAX = 9,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = -1,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\nenum recovery_flags {\n\tMD_RECOVERY_NEEDED = 0,\n\tMD_RECOVERY_RUNNING = 1,\n\tMD_RECOVERY_INTR = 2,\n\tMD_RECOVERY_DONE = 3,\n\tMD_RECOVERY_FROZEN = 4,\n\tMD_RECOVERY_WAIT = 5,\n\tMD_RECOVERY_SYNC = 6,\n\tMD_RECOVERY_REQUESTED = 7,\n\tMD_RECOVERY_CHECK = 8,\n\tMD_RECOVERY_RECOVER = 9,\n\tMD_RECOVERY_RESHAPE = 10,\n\tMD_RESYNCING_REMOTE = 11,\n\tMD_RECOVERY_LAZY_RECOVER = 12,\n};\n\nenum ref_state_type {\n\tREF_TYPE_PTR = 2,\n\tREF_TYPE_IRQ = 4,\n\tREF_TYPE_LOCK = 8,\n\tREF_TYPE_RES_LOCK = 16,\n\tREF_TYPE_RES_LOCK_IRQ = 32,\n\tREF_TYPE_LOCK_MASK = 56,\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum reflink_scan_state {\n\tRLS_IRRELEVANT = -1,\n\tRLS_UNKNOWN = 0,\n\tRLS_SET_IFLAG = 1,\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_FLAT = 2,\n\tREGCACHE_MAPLE = 3,\n\tREGCACHE_FLAT_S = 4,\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_POLLED = 22,\n\t__REQ_ALLOC_CACHE = 23,\n\t__REQ_SWAP = 24,\n\t__REQ_DRV = 25,\n\t__REQ_FS_PRIVATE = 26,\n\t__REQ_ATOMIC = 27,\n\t__REQ_NOUNMAP = 28,\n\t__REQ_NR_BITS = 29,\n};\n\nenum req_op {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_APPEND = 7,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 11,\n\tREQ_OP_ZONE_CLOSE = 13,\n\tREQ_OP_ZONE_FINISH = 15,\n\tREQ_OP_ZONE_RESET = 17,\n\tREQ_OP_ZONE_RESET_ALL = 19,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum resctrl_conf_type {\n\tCDP_NONE = 0,\n\tCDP_CODE = 1,\n\tCDP_DATA = 2,\n};\n\nenum resctrl_event_id {\n\tQOS_FIRST_EVENT = 1,\n\tQOS_L3_OCCUP_EVENT_ID = 1,\n\tQOS_L3_MBM_TOTAL_EVENT_ID = 2,\n\tQOS_L3_MBM_LOCAL_EVENT_ID = 3,\n\tPMT_EVENT_ENERGY = 4,\n\tPMT_EVENT_ACTIVITY = 5,\n\tPMT_EVENT_STALLS_LLC_HIT = 6,\n\tPMT_EVENT_C1_RES = 7,\n\tPMT_EVENT_UNHALTED_CORE_CYCLES = 8,\n\tPMT_EVENT_STALLS_LLC_MISS = 9,\n\tPMT_EVENT_AUTO_C6_RES = 10,\n\tPMT_EVENT_UNHALTED_REF_CYCLES = 11,\n\tPMT_EVENT_UOPS_RETIRED = 12,\n\tQOS_NUM_EVENTS = 13,\n};\n\nenum reset_control_flags {\n\tRESET_CONTROL_EXCLUSIVE = 4,\n\tRESET_CONTROL_EXCLUSIVE_DEASSERTED = 12,\n\tRESET_CONTROL_EXCLUSIVE_RELEASED = 0,\n\tRESET_CONTROL_SHARED = 1,\n\tRESET_CONTROL_SHARED_DEASSERTED = 9,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE = 6,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_DEASSERTED = 14,\n\tRESET_CONTROL_OPTIONAL_EXCLUSIVE_RELEASED = 2,\n\tRESET_CONTROL_OPTIONAL_SHARED = 3,\n\tRESET_CONTROL_OPTIONAL_SHARED_DEASSERTED = 11,\n};\n\nenum reset_mode {\n\tFD_RESET_IF_NEEDED = 0,\n\tFD_RESET_IF_RAWCMD = 1,\n\tFD_RESET_ALWAYS = 2,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nenum rht_lookup_freq {\n\tRHT_LOOKUP_NORMAL = 0,\n\tRHT_LOOKUP_LIKELY = 1,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum rlimit_type {\n\tUCOUNT_RLIMIT_NPROC = 0,\n\tUCOUNT_RLIMIT_MSGQUEUE = 1,\n\tUCOUNT_RLIMIT_SIGPENDING = 2,\n\tUCOUNT_RLIMIT_MEMLOCK = 3,\n\tUCOUNT_RLIMIT_COUNTS = 4,\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nenum rmqueue_mode {\n\tRMQUEUE_NORMAL = 0,\n\tRMQUEUE_CMA = 1,\n\tRMQUEUE_CLAIM = 2,\n\tRMQUEUE_STEAL = 3,\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nenum rpc_accept_stat {\n\tRPC_SUCCESS = 0,\n\tRPC_PROG_UNAVAIL = 1,\n\tRPC_PROG_MISMATCH = 2,\n\tRPC_PROC_UNAVAIL = 3,\n\tRPC_GARBAGE_ARGS = 4,\n\tRPC_SYSTEM_ERR = 5,\n\tRPC_DROP_REPLY = 60000,\n};\n\nenum rpc_auth_flavors {\n\tRPC_AUTH_NULL = 0,\n\tRPC_AUTH_UNIX = 1,\n\tRPC_AUTH_SHORT = 2,\n\tRPC_AUTH_DES = 3,\n\tRPC_AUTH_KRB = 4,\n\tRPC_AUTH_GSS = 6,\n\tRPC_AUTH_TLS = 7,\n\tRPC_AUTH_MAXFLAVOR = 8,\n\tRPC_AUTH_GSS_KRB5 = 390003,\n\tRPC_AUTH_GSS_KRB5I = 390004,\n\tRPC_AUTH_GSS_KRB5P = 390005,\n\tRPC_AUTH_GSS_LKEY = 390006,\n\tRPC_AUTH_GSS_LKEYI = 390007,\n\tRPC_AUTH_GSS_LKEYP = 390008,\n\tRPC_AUTH_GSS_SPKM = 390009,\n\tRPC_AUTH_GSS_SPKMI = 390010,\n\tRPC_AUTH_GSS_SPKMP = 390011,\n};\n\nenum rpc_auth_stat {\n\tRPC_AUTH_OK = 0,\n\tRPC_AUTH_BADCRED = 1,\n\tRPC_AUTH_REJECTEDCRED = 2,\n\tRPC_AUTH_BADVERF = 3,\n\tRPC_AUTH_REJECTEDVERF = 4,\n\tRPC_AUTH_TOOWEAK = 5,\n\tRPC_AUTH_INVALIDRESP = 6,\n\tRPC_AUTH_FAILED = 7,\n\tRPCSEC_GSS_CREDPROBLEM = 13,\n\tRPCSEC_GSS_CTXPROBLEM = 14,\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum rpc_gss_proc {\n\tRPC_GSS_PROC_DATA = 0,\n\tRPC_GSS_PROC_INIT = 1,\n\tRPC_GSS_PROC_CONTINUE_INIT = 2,\n\tRPC_GSS_PROC_DESTROY = 3,\n};\n\nenum rpc_gss_svc {\n\tRPC_GSS_SVC_NONE = 1,\n\tRPC_GSS_SVC_INTEGRITY = 2,\n\tRPC_GSS_SVC_PRIVACY = 3,\n};\n\nenum rpc_msg_type {\n\tRPC_CALL = 0,\n\tRPC_REPLY = 1,\n};\n\nenum rpc_reject_stat {\n\tRPC_MISMATCH = 0,\n\tRPC_AUTH_ERROR = 1,\n};\n\nenum rpc_reply_stat {\n\tRPC_MSG_ACCEPTED = 0,\n\tRPC_MSG_DENIED = 1,\n};\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_INVALID = -1,\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n\tRPM_BLOCKED = 4,\n};\n\nenum rq_end_io_ret {\n\tRQ_END_IO_NONE = 0,\n\tRQ_END_IO_FREE = 1,\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nenum rqf_flags {\n\t__RQF_STARTED = 0,\n\t__RQF_FLUSH_SEQ = 1,\n\t__RQF_MIXED_MERGE = 2,\n\t__RQF_DONTPREP = 3,\n\t__RQF_SCHED_TAGS = 4,\n\t__RQF_USE_SCHED = 5,\n\t__RQF_FAILED = 6,\n\t__RQF_QUIET = 7,\n\t__RQF_IO_STAT = 8,\n\t__RQF_PM = 9,\n\t__RQF_HASHED = 10,\n\t__RQF_STATS = 11,\n\t__RQF_SPECIAL_PAYLOAD = 12,\n\t__RQF_ZONE_WRITE_PLUGGING = 13,\n\t__RQF_TIMED_OUT = 14,\n\t__RQF_RESV = 15,\n\t__RQF_BITS = 16,\n};\n\nenum rsaprivkey_actions {\n\tACT_rsa_get_d = 0,\n\tACT_rsa_get_dp = 1,\n\tACT_rsa_get_dq = 2,\n\tACT_rsa_get_e = 3,\n\tACT_rsa_get_n = 4,\n\tACT_rsa_get_p = 5,\n\tACT_rsa_get_q = 6,\n\tACT_rsa_get_qinv = 7,\n\tNR__rsaprivkey_actions = 8,\n};\n\nenum rsapubkey_actions {\n\tACT_rsa_get_e___2 = 0,\n\tACT_rsa_get_n___2 = 1,\n\tNR__rsapubkey_actions = 2,\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = -1,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = -2,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE = 16,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED = 32,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n\tRSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,\n\tRSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n\tRSEQ_FLAG_SLICE_EXT_DEFAULT_ON = 2,\n};\n\nenum rt6_nud_state {\n\tRT6_NUD_FAIL_HARD = -3,\n\tRT6_NUD_FAIL_PROBE = -2,\n\tRT6_NUD_FAIL_DO_RR = -1,\n\tRT6_NUD_SUCCEED = 1,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rtas_function_index {\n\tRTAS_FNIDX__CHECK_EXCEPTION = 0,\n\tRTAS_FNIDX__DISPLAY_CHARACTER = 1,\n\tRTAS_FNIDX__EVENT_SCAN = 2,\n\tRTAS_FNIDX__FREEZE_TIME_BASE = 3,\n\tRTAS_FNIDX__GET_POWER_LEVEL = 4,\n\tRTAS_FNIDX__GET_SENSOR_STATE = 5,\n\tRTAS_FNIDX__GET_TERM_CHAR = 6,\n\tRTAS_FNIDX__GET_TIME_OF_DAY = 7,\n\tRTAS_FNIDX__IBM_ACTIVATE_FIRMWARE = 8,\n\tRTAS_FNIDX__IBM_CBE_START_PTCAL = 9,\n\tRTAS_FNIDX__IBM_CBE_STOP_PTCAL = 10,\n\tRTAS_FNIDX__IBM_CHANGE_MSI = 11,\n\tRTAS_FNIDX__IBM_CLOSE_ERRINJCT = 12,\n\tRTAS_FNIDX__IBM_CONFIGURE_BRIDGE = 13,\n\tRTAS_FNIDX__IBM_CONFIGURE_CONNECTOR = 14,\n\tRTAS_FNIDX__IBM_CONFIGURE_KERNEL_DUMP = 15,\n\tRTAS_FNIDX__IBM_CONFIGURE_PE = 16,\n\tRTAS_FNIDX__IBM_CREATE_PE_DMA_WINDOW = 17,\n\tRTAS_FNIDX__IBM_DISPLAY_MESSAGE = 18,\n\tRTAS_FNIDX__IBM_ERRINJCT = 19,\n\tRTAS_FNIDX__IBM_EXTI2C = 20,\n\tRTAS_FNIDX__IBM_GET_CONFIG_ADDR_INFO = 21,\n\tRTAS_FNIDX__IBM_GET_CONFIG_ADDR_INFO2 = 22,\n\tRTAS_FNIDX__IBM_GET_DYNAMIC_SENSOR_STATE = 23,\n\tRTAS_FNIDX__IBM_GET_INDICES = 24,\n\tRTAS_FNIDX__IBM_GET_RIO_TOPOLOGY = 25,\n\tRTAS_FNIDX__IBM_GET_SYSTEM_PARAMETER = 26,\n\tRTAS_FNIDX__IBM_GET_VPD = 27,\n\tRTAS_FNIDX__IBM_GET_XIVE = 28,\n\tRTAS_FNIDX__IBM_INT_OFF = 29,\n\tRTAS_FNIDX__IBM_INT_ON = 30,\n\tRTAS_FNIDX__IBM_IO_QUIESCE_ACK = 31,\n\tRTAS_FNIDX__IBM_LPAR_PERFTOOLS = 32,\n\tRTAS_FNIDX__IBM_MANAGE_FLASH_IMAGE = 33,\n\tRTAS_FNIDX__IBM_MANAGE_STORAGE_PRESERVATION = 34,\n\tRTAS_FNIDX__IBM_NMI_INTERLOCK = 35,\n\tRTAS_FNIDX__IBM_NMI_REGISTER = 36,\n\tRTAS_FNIDX__IBM_OPEN_ERRINJCT = 37,\n\tRTAS_FNIDX__IBM_OPEN_SRIOV_ALLOW_UNFREEZE = 38,\n\tRTAS_FNIDX__IBM_OPEN_SRIOV_MAP_PE_NUMBER = 39,\n\tRTAS_FNIDX__IBM_OS_TERM = 40,\n\tRTAS_FNIDX__IBM_PARTNER_CONTROL = 41,\n\tRTAS_FNIDX__IBM_PHYSICAL_ATTESTATION = 42,\n\tRTAS_FNIDX__IBM_PLATFORM_DUMP = 43,\n\tRTAS_FNIDX__IBM_POWER_OFF_UPS = 44,\n\tRTAS_FNIDX__IBM_QUERY_INTERRUPT_SOURCE_NUMBER = 45,\n\tRTAS_FNIDX__IBM_QUERY_PE_DMA_WINDOW = 46,\n\tRTAS_FNIDX__IBM_READ_PCI_CONFIG = 47,\n\tRTAS_FNIDX__IBM_READ_SLOT_RESET_STATE = 48,\n\tRTAS_FNIDX__IBM_READ_SLOT_RESET_STATE2 = 49,\n\tRTAS_FNIDX__IBM_RECEIVE_HVPIPE_MSG = 50,\n\tRTAS_FNIDX__IBM_REMOVE_PE_DMA_WINDOW = 51,\n\tRTAS_FNIDX__IBM_RESET_PE_DMA_WINDOW = 52,\n\tRTAS_FNIDX__IBM_SCAN_LOG_DUMP = 53,\n\tRTAS_FNIDX__IBM_SEND_HVPIPE_MSG = 54,\n\tRTAS_FNIDX__IBM_SET_DYNAMIC_INDICATOR = 55,\n\tRTAS_FNIDX__IBM_SET_EEH_OPTION = 56,\n\tRTAS_FNIDX__IBM_SET_SLOT_RESET = 57,\n\tRTAS_FNIDX__IBM_SET_SYSTEM_PARAMETER = 58,\n\tRTAS_FNIDX__IBM_SET_XIVE = 59,\n\tRTAS_FNIDX__IBM_SLOT_ERROR_DETAIL = 60,\n\tRTAS_FNIDX__IBM_SUSPEND_ME = 61,\n\tRTAS_FNIDX__IBM_TUNE_DMA_PARMS = 62,\n\tRTAS_FNIDX__IBM_UPDATE_FLASH_64_AND_REBOOT = 63,\n\tRTAS_FNIDX__IBM_UPDATE_NODES = 64,\n\tRTAS_FNIDX__IBM_UPDATE_PROPERTIES = 65,\n\tRTAS_FNIDX__IBM_VALIDATE_FLASH_IMAGE = 66,\n\tRTAS_FNIDX__IBM_WRITE_PCI_CONFIG = 67,\n\tRTAS_FNIDX__NVRAM_FETCH = 68,\n\tRTAS_FNIDX__NVRAM_STORE = 69,\n\tRTAS_FNIDX__POWER_OFF = 70,\n\tRTAS_FNIDX__PUT_TERM_CHAR = 71,\n\tRTAS_FNIDX__QUERY_CPU_STOPPED_STATE = 72,\n\tRTAS_FNIDX__READ_PCI_CONFIG = 73,\n\tRTAS_FNIDX__RTAS_LAST_ERROR = 74,\n\tRTAS_FNIDX__SET_INDICATOR = 75,\n\tRTAS_FNIDX__SET_POWER_LEVEL = 76,\n\tRTAS_FNIDX__SET_TIME_FOR_POWER_ON = 77,\n\tRTAS_FNIDX__SET_TIME_OF_DAY = 78,\n\tRTAS_FNIDX__START_CPU = 79,\n\tRTAS_FNIDX__STOP_SELF = 80,\n\tRTAS_FNIDX__SYSTEM_REBOOT = 81,\n\tRTAS_FNIDX__THAW_TIME_BASE = 82,\n\tRTAS_FNIDX__WRITE_PCI_CONFIG = 83,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\tRTA_FLOWLABEL = 31,\n\t__RTA_MAX = 32,\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\tRTNLGRP_MCTP_IFADDR = 34,\n\tRTNLGRP_TUNNEL = 35,\n\tRTNLGRP_STATS = 36,\n\tRTNLGRP_IPV4_MCADDR = 37,\n\tRTNLGRP_IPV6_MCADDR = 38,\n\tRTNLGRP_IPV6_ACADDR = 39,\n\t__RTNLGRP_MAX = 40,\n};\n\nenum rtnl_kinds {\n\tRTNL_KIND_NEW = 0,\n\tRTNL_KIND_DEL = 1,\n\tRTNL_KIND_GET = 2,\n\tRTNL_KIND_SET = 3,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n\tRTNL_FLAG_BULK_DEL_SUPPORTED = 2,\n\tRTNL_FLAG_DUMP_UNLOCKED = 4,\n\tRTNL_FLAG_DUMP_SPLIT_NLM_DONE = 8,\n};\n\nenum ru_state {\n\tRU_SUSPENDED = 0,\n\tRU_RUNNING = 1,\n\tRU_UNINITIALIZED = -1,\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n\tWRITE_LIFE_HINT_NR = 6,\n} __attribute__((mode(byte)));\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum sam_status {\n\tSAM_STAT_GOOD = 0,\n\tSAM_STAT_CHECK_CONDITION = 2,\n\tSAM_STAT_CONDITION_MET = 4,\n\tSAM_STAT_BUSY = 8,\n\tSAM_STAT_INTERMEDIATE = 16,\n\tSAM_STAT_INTERMEDIATE_CONDITION_MET = 20,\n\tSAM_STAT_RESERVATION_CONFLICT = 24,\n\tSAM_STAT_COMMAND_TERMINATED = 34,\n\tSAM_STAT_TASK_SET_FULL = 40,\n\tSAM_STAT_ACA_ACTIVE = 48,\n\tSAM_STAT_TASK_ABORTED = 64,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nenum scan_result {\n\tSCAN_FAIL = 0,\n\tSCAN_SUCCEED = 1,\n\tSCAN_NO_PTE_TABLE = 2,\n\tSCAN_PMD_MAPPED = 3,\n\tSCAN_EXCEED_NONE_PTE = 4,\n\tSCAN_EXCEED_SWAP_PTE = 5,\n\tSCAN_EXCEED_SHARED_PTE = 6,\n\tSCAN_PTE_NON_PRESENT = 7,\n\tSCAN_PTE_UFFD_WP = 8,\n\tSCAN_PTE_MAPPED_HUGEPAGE = 9,\n\tSCAN_LACK_REFERENCED_PAGE = 10,\n\tSCAN_PAGE_NULL = 11,\n\tSCAN_SCAN_ABORT = 12,\n\tSCAN_PAGE_COUNT = 13,\n\tSCAN_PAGE_LRU = 14,\n\tSCAN_PAGE_LOCK = 15,\n\tSCAN_PAGE_ANON = 16,\n\tSCAN_PAGE_COMPOUND = 17,\n\tSCAN_ANY_PROCESS = 18,\n\tSCAN_VMA_NULL = 19,\n\tSCAN_VMA_CHECK = 20,\n\tSCAN_ADDRESS_RANGE = 21,\n\tSCAN_DEL_PAGE_LRU = 22,\n\tSCAN_ALLOC_HUGE_PAGE_FAIL = 23,\n\tSCAN_CGROUP_CHARGE_FAIL = 24,\n\tSCAN_TRUNCATED = 25,\n\tSCAN_PAGE_HAS_PRIVATE = 26,\n\tSCAN_STORE_FAILED = 27,\n\tSCAN_COPY_MC = 28,\n\tSCAN_PAGE_FILLED = 29,\n\tSCAN_PAGE_DIRTY_OR_WRITEBACK = 30,\n};\n\nenum scb_cmd_hi {\n\tirq_mask_none = 0,\n\tirq_mask_all = 1,\n\tirq_sw_gen = 2,\n};\n\nenum scb_cmd_lo {\n\tcuc_nop = 0,\n\truc_start = 1,\n\truc_load_base = 6,\n\tcuc_start = 16,\n\tcuc_resume = 32,\n\tcuc_dump_addr = 64,\n\tcuc_dump_stats = 80,\n\tcuc_load_base = 96,\n\tcuc_dump_reset = 112,\n};\n\nenum scb_stat_ack {\n\tstat_ack_not_ours = 0,\n\tstat_ack_sw_gen = 4,\n\tstat_ack_rnr = 16,\n\tstat_ack_cu_idle = 32,\n\tstat_ack_frame_rx = 64,\n\tstat_ack_cu_cmd_done = 128,\n\tstat_ack_not_present = 255,\n\tstat_ack_rx = 84,\n\tstat_ack_tx = 160,\n};\n\nenum scb_status {\n\trus_no_res = 8,\n\trus_ready = 16,\n\trus_mask = 60,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum scrub_type {\n\tSCRUB_UNKNOWN = 0,\n\tSCRUB_NONE = 1,\n\tSCRUB_SW_PROG = 2,\n\tSCRUB_SW_SRC = 3,\n\tSCRUB_SW_PROG_SRC = 4,\n\tSCRUB_SW_TUNABLE = 5,\n\tSCRUB_HW_PROG = 6,\n\tSCRUB_HW_SRC = 7,\n\tSCRUB_HW_PROG_SRC = 8,\n\tSCRUB_HW_TUNABLE = 9,\n};\n\nenum scsi_cmnd_submitter {\n\tSUBMITTED_BY_BLOCK_LAYER = 0,\n\tSUBMITTED_BY_SCSI_ERROR_HANDLER = 1,\n\tSUBMITTED_BY_SCSI_RESET_IOCTL = 2,\n} __attribute__((mode(byte)));\n\nenum scsi_code_set {\n\tPS_CODE_SET_BINARY = 1,\n\tPS_CODE_SET_ASCII = 2,\n\tPS_CODE_SET_UTF8 = 3,\n};\n\nenum scsi_designator_type {\n\tPS_DESIGNATOR_T10 = 1,\n\tPS_DESIGNATOR_EUI64 = 2,\n\tPS_DESIGNATOR_NAA = 3,\n\tPS_DESIGNATOR_NAME = 8,\n};\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nenum scsi_disposition {\n\tNEEDS_RETRY = 8193,\n\tSUCCESS = 8194,\n\tFAILED = 8195,\n\tQUEUED = 8196,\n\tSOFT_ERROR = 8197,\n\tADD_TO_MLQUEUE = 8198,\n\tTIMEOUT_ERROR = 8199,\n\tSCSI_RETURN_NOT_HANDLED = 8200,\n\tFAST_IO_FAIL = 8201,\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nenum scsi_host_status {\n\tDID_OK = 0,\n\tDID_NO_CONNECT = 1,\n\tDID_BUS_BUSY = 2,\n\tDID_TIME_OUT = 3,\n\tDID_BAD_TARGET = 4,\n\tDID_ABORT = 5,\n\tDID_PARITY = 6,\n\tDID_ERROR = 7,\n\tDID_RESET = 8,\n\tDID_BAD_INTR = 9,\n\tDID_PASSTHROUGH = 10,\n\tDID_SOFT_ERROR = 11,\n\tDID_IMM_RETRY = 12,\n\tDID_REQUEUE = 13,\n\tDID_TRANSPORT_DISRUPTED = 14,\n\tDID_TRANSPORT_FAILFAST = 15,\n\tDID_TRANSPORT_MARGINAL = 20,\n};\n\nenum scsi_ml_status {\n\tSCSIML_STAT_OK = 0,\n\tSCSIML_STAT_RESV_CONFLICT = 1,\n\tSCSIML_STAT_NOSPC = 2,\n\tSCSIML_STAT_MED_ERROR = 3,\n\tSCSIML_STAT_TGT_FAILURE = 4,\n\tSCSIML_STAT_DL_TIMEOUT = 5,\n};\n\nenum scsi_msg_byte {\n\tCOMMAND_COMPLETE = 0,\n\tEXTENDED_MESSAGE = 1,\n\tSAVE_POINTERS = 2,\n\tRESTORE_POINTERS = 3,\n\tDISCONNECT = 4,\n\tINITIATOR_ERROR = 5,\n\tABORT_TASK_SET = 6,\n\tMESSAGE_REJECT = 7,\n\tNOP = 8,\n\tMSG_PARITY_ERROR = 9,\n\tLINKED_CMD_COMPLETE = 10,\n\tLINKED_FLG_CMD_COMPLETE = 11,\n\tTARGET_RESET = 12,\n\tABORT_TASK = 13,\n\tCLEAR_TASK_SET = 14,\n\tINITIATE_RECOVERY = 15,\n\tRELEASE_RECOVERY = 16,\n\tTERMINATE_IO_PROC = 17,\n\tCLEAR_ACA = 22,\n\tLOGICAL_UNIT_RESET = 23,\n\tSIMPLE_QUEUE_TAG = 32,\n\tHEAD_OF_QUEUE_TAG = 33,\n\tORDERED_QUEUE_TAG = 34,\n\tIGNORE_WIDE_RESIDUE = 35,\n\tACA = 36,\n\tQAS_REQUEST = 85,\n\tBUS_DEVICE_RESET = 12,\n\tABORT = 6,\n};\n\nenum scsi_pr_type {\n\tSCSI_PR_WRITE_EXCLUSIVE = 1,\n\tSCSI_PR_EXCLUSIVE_ACCESS = 3,\n\tSCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5,\n\tSCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6,\n\tSCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7,\n\tSCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nenum scsi_qc_status {\n\tSCSI_MLQUEUE_HOST_BUSY = 4181,\n\tSCSI_MLQUEUE_DEVICE_BUSY = 4182,\n\tSCSI_MLQUEUE_EH_RETRY = 4183,\n\tSCSI_MLQUEUE_TARGET_BUSY = 4184,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nenum scsi_timeout_action {\n\tSCSI_EH_DONE = 0,\n\tSCSI_EH_RESET_TIMER = 1,\n\tSCSI_EH_NOT_HANDLED = 2,\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 10000,\n};\n\nenum scsi_vpd_parameters {\n\tSCSI_VPD_HEADER_SIZE = 4,\n\tSCSI_VPD_LIST_SIZE = 36,\n};\n\nenum sctp_cid {\n\tSCTP_CID_DATA = 0,\n\tSCTP_CID_INIT = 1,\n\tSCTP_CID_INIT_ACK = 2,\n\tSCTP_CID_SACK = 3,\n\tSCTP_CID_HEARTBEAT = 4,\n\tSCTP_CID_HEARTBEAT_ACK = 5,\n\tSCTP_CID_ABORT = 6,\n\tSCTP_CID_SHUTDOWN = 7,\n\tSCTP_CID_SHUTDOWN_ACK = 8,\n\tSCTP_CID_ERROR = 9,\n\tSCTP_CID_COOKIE_ECHO = 10,\n\tSCTP_CID_COOKIE_ACK = 11,\n\tSCTP_CID_ECN_ECNE = 12,\n\tSCTP_CID_ECN_CWR = 13,\n\tSCTP_CID_SHUTDOWN_COMPLETE = 14,\n\tSCTP_CID_AUTH = 15,\n\tSCTP_CID_I_DATA = 64,\n\tSCTP_CID_FWD_TSN = 192,\n\tSCTP_CID_ASCONF = 193,\n\tSCTP_CID_I_FWD_TSN = 194,\n\tSCTP_CID_ASCONF_ACK = 128,\n\tSCTP_CID_RECONF = 130,\n\tSCTP_CID_PAD = 132,\n};\n\nenum sctp_conntrack {\n\tSCTP_CONNTRACK_NONE = 0,\n\tSCTP_CONNTRACK_CLOSED = 1,\n\tSCTP_CONNTRACK_COOKIE_WAIT = 2,\n\tSCTP_CONNTRACK_COOKIE_ECHOED = 3,\n\tSCTP_CONNTRACK_ESTABLISHED = 4,\n\tSCTP_CONNTRACK_SHUTDOWN_SENT = 5,\n\tSCTP_CONNTRACK_SHUTDOWN_RECD = 6,\n\tSCTP_CONNTRACK_SHUTDOWN_ACK_SENT = 7,\n\tSCTP_CONNTRACK_HEARTBEAT_SENT = 8,\n\tSCTP_CONNTRACK_HEARTBEAT_ACKED = 9,\n\tSCTP_CONNTRACK_MAX = 10,\n};\n\nenum sctp_endpoint_type {\n\tSCTP_EP_TYPE_SOCKET = 0,\n\tSCTP_EP_TYPE_ASSOCIATION = 1,\n};\n\nenum sctp_event_timeout {\n\tSCTP_EVENT_TIMEOUT_NONE = 0,\n\tSCTP_EVENT_TIMEOUT_T1_COOKIE = 1,\n\tSCTP_EVENT_TIMEOUT_T1_INIT = 2,\n\tSCTP_EVENT_TIMEOUT_T2_SHUTDOWN = 3,\n\tSCTP_EVENT_TIMEOUT_T3_RTX = 4,\n\tSCTP_EVENT_TIMEOUT_T4_RTO = 5,\n\tSCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD = 6,\n\tSCTP_EVENT_TIMEOUT_HEARTBEAT = 7,\n\tSCTP_EVENT_TIMEOUT_RECONF = 8,\n\tSCTP_EVENT_TIMEOUT_PROBE = 9,\n\tSCTP_EVENT_TIMEOUT_SACK = 10,\n\tSCTP_EVENT_TIMEOUT_AUTOCLOSE = 11,\n};\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nenum sctp_param {\n\tSCTP_PARAM_HEARTBEAT_INFO = 256,\n\tSCTP_PARAM_IPV4_ADDRESS = 1280,\n\tSCTP_PARAM_IPV6_ADDRESS = 1536,\n\tSCTP_PARAM_STATE_COOKIE = 1792,\n\tSCTP_PARAM_UNRECOGNIZED_PARAMETERS = 2048,\n\tSCTP_PARAM_COOKIE_PRESERVATIVE = 2304,\n\tSCTP_PARAM_HOST_NAME_ADDRESS = 2816,\n\tSCTP_PARAM_SUPPORTED_ADDRESS_TYPES = 3072,\n\tSCTP_PARAM_ECN_CAPABLE = 128,\n\tSCTP_PARAM_RANDOM = 640,\n\tSCTP_PARAM_CHUNKS = 896,\n\tSCTP_PARAM_HMAC_ALGO = 1152,\n\tSCTP_PARAM_SUPPORTED_EXT = 2176,\n\tSCTP_PARAM_FWD_TSN_SUPPORT = 192,\n\tSCTP_PARAM_ADD_IP = 448,\n\tSCTP_PARAM_DEL_IP = 704,\n\tSCTP_PARAM_ERR_CAUSE = 960,\n\tSCTP_PARAM_SET_PRIMARY = 1216,\n\tSCTP_PARAM_SUCCESS_REPORT = 1472,\n\tSCTP_PARAM_ADAPTATION_LAYER_IND = 1728,\n\tSCTP_PARAM_RESET_OUT_REQUEST = 3328,\n\tSCTP_PARAM_RESET_IN_REQUEST = 3584,\n\tSCTP_PARAM_RESET_TSN_REQUEST = 3840,\n\tSCTP_PARAM_RESET_RESPONSE = 4096,\n\tSCTP_PARAM_RESET_ADD_OUT_STREAMS = 4352,\n\tSCTP_PARAM_RESET_ADD_IN_STREAMS = 4608,\n};\n\nenum sctp_scope {\n\tSCTP_SCOPE_GLOBAL = 0,\n\tSCTP_SCOPE_PRIVATE = 1,\n\tSCTP_SCOPE_LINK = 2,\n\tSCTP_SCOPE_LOOPBACK = 3,\n\tSCTP_SCOPE_UNUSABLE = 4,\n};\n\nenum sctp_socket_type {\n\tSCTP_SOCKET_UDP = 0,\n\tSCTP_SOCKET_UDP_HIGH_BANDWIDTH = 1,\n\tSCTP_SOCKET_TCP = 2,\n};\n\nenum sctp_state {\n\tSCTP_STATE_CLOSED = 0,\n\tSCTP_STATE_COOKIE_WAIT = 1,\n\tSCTP_STATE_COOKIE_ECHOED = 2,\n\tSCTP_STATE_ESTABLISHED = 3,\n\tSCTP_STATE_SHUTDOWN_PENDING = 4,\n\tSCTP_STATE_SHUTDOWN_SENT = 5,\n\tSCTP_STATE_SHUTDOWN_RECEIVED = 6,\n\tSCTP_STATE_SHUTDOWN_ACK_SENT = 7,\n};\n\nenum scx_consts {\n\tSCX_DSP_DFL_MAX_BATCH = 32,\n\tSCX_DSP_MAX_LOOPS = 32,\n\tSCX_WATCHDOG_MAX_TIMEOUT = 30000,\n\tSCX_EXIT_BT_LEN = 64,\n\tSCX_EXIT_MSG_LEN = 1024,\n\tSCX_EXIT_DUMP_DFL_LEN = 32768,\n\tSCX_CPUPERF_ONE = 1024,\n\tSCX_TASK_ITER_BATCH = 32,\n\tSCX_BYPASS_HOST_NTH = 2,\n\tSCX_BYPASS_LB_DFL_INTV_US = 500000,\n\tSCX_BYPASS_LB_DONOR_PCT = 125,\n\tSCX_BYPASS_LB_MIN_DELTA_DIV = 4,\n\tSCX_BYPASS_LB_BATCH = 256,\n\tSCX_SUB_MAX_DEPTH = 4,\n};\n\nenum scx_cpu_preempt_reason {\n\tSCX_CPU_PREEMPT_RT = 0,\n\tSCX_CPU_PREEMPT_DL = 1,\n\tSCX_CPU_PREEMPT_STOP = 2,\n\tSCX_CPU_PREEMPT_UNKNOWN = 3,\n};\n\nenum scx_deq_flags {\n\tSCX_DEQ_SLEEP = 1ULL,\n\tSCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL,\n\tSCX_DEQ_SCHED_CHANGE = 8589934592ULL,\n};\n\nenum scx_dsq_id_flags {\n\tSCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL,\n\tSCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL,\n\tSCX_DSQ_INVALID = 9223372036854775808ULL,\n\tSCX_DSQ_GLOBAL = 9223372036854775809ULL,\n\tSCX_DSQ_LOCAL = 9223372036854775810ULL,\n\tSCX_DSQ_BYPASS = 9223372036854775811ULL,\n\tSCX_DSQ_LOCAL_ON = 13835058055282163712ULL,\n\tSCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL,\n};\n\nenum scx_dsq_iter_flags {\n\tSCX_DSQ_ITER_REV = 65536,\n\t__SCX_DSQ_ITER_HAS_SLICE = 1073741824,\n\t__SCX_DSQ_ITER_HAS_VTIME = 2147483648,\n\t__SCX_DSQ_ITER_USER_FLAGS = 65536,\n\t__SCX_DSQ_ITER_ALL_FLAGS = 3221291008,\n};\n\nenum scx_dsq_lnode_flags {\n\tSCX_DSQ_LNODE_ITER_CURSOR = 1,\n\t__SCX_DSQ_LNODE_PRIV_SHIFT = 16,\n};\n\nenum scx_enable_state {\n\tSCX_ENABLING = 0,\n\tSCX_ENABLED = 1,\n\tSCX_DISABLING = 2,\n\tSCX_DISABLED = 3,\n};\n\nenum scx_enq_flags {\n\tSCX_ENQ_WAKEUP = 1ULL,\n\tSCX_ENQ_HEAD = 65536ULL,\n\tSCX_ENQ_CPU_SELECTED = 1048576ULL,\n\tSCX_ENQ_PREEMPT = 4294967296ULL,\n\tSCX_ENQ_REENQ = 1099511627776ULL,\n\tSCX_ENQ_LAST = 2199023255552ULL,\n\t__SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_ENQ_CLEAR_OPSS = 72057594037927936ULL,\n\tSCX_ENQ_DSQ_PRIQ = 144115188075855872ULL,\n\tSCX_ENQ_NESTED = 288230376151711744ULL,\n};\n\nenum scx_ent_dsq_flags {\n\tSCX_TASK_DSQ_ON_PRIQ = 1,\n};\n\nenum scx_ent_flags {\n\tSCX_TASK_QUEUED = 1,\n\tSCX_TASK_IN_CUSTODY = 2,\n\tSCX_TASK_RESET_RUNNABLE_AT = 4,\n\tSCX_TASK_DEQD_FOR_SLEEP = 8,\n\tSCX_TASK_SUB_INIT = 16,\n\tSCX_TASK_STATE_SHIFT = 8,\n\tSCX_TASK_STATE_BITS = 2,\n\tSCX_TASK_STATE_MASK = 768,\n\tSCX_TASK_NONE = 0,\n\tSCX_TASK_INIT = 256,\n\tSCX_TASK_READY = 512,\n\tSCX_TASK_ENABLED = 768,\n\tSCX_TASK_REENQ_REASON_SHIFT = 12,\n\tSCX_TASK_REENQ_REASON_BITS = 2,\n\tSCX_TASK_REENQ_REASON_MASK = 12288,\n\tSCX_TASK_REENQ_NONE = 0,\n\tSCX_TASK_REENQ_KFUNC = 4096,\n\tSCX_TASK_CURSOR = -2147483648,\n};\n\nenum scx_exit_code {\n\tSCX_ECODE_RSN_HOTPLUG = 4294967296ULL,\n\tSCX_ECODE_RSN_CGROUP_OFFLINE = 8589934592ULL,\n\tSCX_ECODE_ACT_RESTART = 281474976710656ULL,\n};\n\nenum scx_exit_flags {\n\tSCX_EFLAG_INITIALIZED = 1,\n};\n\nenum scx_exit_kind {\n\tSCX_EXIT_NONE = 0,\n\tSCX_EXIT_DONE = 1,\n\tSCX_EXIT_UNREG = 64,\n\tSCX_EXIT_UNREG_BPF = 65,\n\tSCX_EXIT_UNREG_KERN = 66,\n\tSCX_EXIT_SYSRQ = 67,\n\tSCX_EXIT_PARENT = 68,\n\tSCX_EXIT_ERROR = 1024,\n\tSCX_EXIT_ERROR_BPF = 1025,\n\tSCX_EXIT_ERROR_STALL = 1026,\n};\n\nenum scx_kf_mask {\n\tSCX_KF_UNLOCKED = 0,\n\tSCX_KF_CPU_RELEASE = 1,\n\tSCX_KF_DISPATCH = 2,\n\tSCX_KF_ENQUEUE = 4,\n\tSCX_KF_SELECT_CPU = 8,\n\tSCX_KF_REST = 16,\n\t__SCX_KF_RQ_LOCKED = 31,\n\t__SCX_KF_TERMINAL = 28,\n};\n\nenum scx_kick_flags {\n\tSCX_KICK_IDLE = 1,\n\tSCX_KICK_PREEMPT = 2,\n\tSCX_KICK_WAIT = 4,\n};\n\nenum scx_opi {\n\tSCX_OPI_BEGIN = 0,\n\tSCX_OPI_NORMAL_BEGIN = 0,\n\tSCX_OPI_NORMAL_END = 33,\n\tSCX_OPI_CPU_HOTPLUG_BEGIN = 33,\n\tSCX_OPI_CPU_HOTPLUG_END = 35,\n\tSCX_OPI_END = 35,\n};\n\nenum scx_ops_flags {\n\tSCX_OPS_KEEP_BUILTIN_IDLE = 1ULL,\n\tSCX_OPS_ENQ_LAST = 2ULL,\n\tSCX_OPS_ENQ_EXITING = 4ULL,\n\tSCX_OPS_SWITCH_PARTIAL = 8ULL,\n\tSCX_OPS_ENQ_MIGRATION_DISABLED = 16ULL,\n\tSCX_OPS_ALLOW_QUEUED_WAKEUP = 32ULL,\n\tSCX_OPS_BUILTIN_IDLE_PER_NODE = 64ULL,\n\tSCX_OPS_HAS_CGROUP_WEIGHT = 65536ULL,\n\tSCX_OPS_ALL_FLAGS = 65663ULL,\n\t__SCX_OPS_INTERNAL_MASK = 18374686479671623680ULL,\n\tSCX_OPS_HAS_CPU_PREEMPT = 72057594037927936ULL,\n};\n\nenum scx_ops_state {\n\tSCX_OPSS_NONE = 0,\n\tSCX_OPSS_QUEUEING = 1,\n\tSCX_OPSS_QUEUED = 2,\n\tSCX_OPSS_DISPATCHING = 3,\n\tSCX_OPSS_QSEQ_SHIFT = 2,\n};\n\nenum scx_pick_idle_cpu_flags {\n\tSCX_PICK_IDLE_CORE = 1,\n\tSCX_PICK_IDLE_IN_NODE = 2,\n};\n\nenum scx_public_consts {\n\tSCX_OPS_NAME_LEN = 128ULL,\n\tSCX_SLICE_DFL = 20000000ULL,\n\tSCX_SLICE_BYPASS = 5000000ULL,\n\tSCX_SLICE_INF = 18446744073709551615ULL,\n};\n\nenum scx_reenq_flags {\n\tSCX_REENQ_ANY = 1,\n\t__SCX_REENQ_FILTER_MASK = 65535,\n\t__SCX_REENQ_USER_MASK = 1,\n};\n\nenum scx_rq_flags {\n\tSCX_RQ_ONLINE = 1,\n\tSCX_RQ_CAN_STOP_TICK = 2,\n\tSCX_RQ_BAL_KEEP = 8,\n\tSCX_RQ_CLK_VALID = 32,\n\tSCX_RQ_BAL_CB_PENDING = 64,\n\tSCX_RQ_IN_WAKEUP = 65536,\n\tSCX_RQ_IN_BALANCE = 131072,\n};\n\nenum scx_sched_pcpu_flags {\n\tSCX_SCHED_PCPU_BYPASSING = 1,\n};\n\nenum scx_tg_flags {\n\tSCX_TG_ONLINE = 1,\n\tSCX_TG_INITED = 2,\n};\n\nenum scx_wake_flags {\n\tSCX_WAKE_FORK = 4,\n\tSCX_WAKE_TTWU = 8,\n\tSCX_WAKE_SYNC = 16,\n};\n\nenum sel_inos {\n\tSEL_ROOT_INO = 2,\n\tSEL_LOAD = 3,\n\tSEL_ENFORCE = 4,\n\tSEL_CONTEXT = 5,\n\tSEL_ACCESS = 6,\n\tSEL_CREATE = 7,\n\tSEL_RELABEL = 8,\n\tSEL_USER = 9,\n\tSEL_POLICYVERS = 10,\n\tSEL_COMMIT_BOOLS = 11,\n\tSEL_MLS = 12,\n\tSEL_DISABLE = 13,\n\tSEL_MEMBER = 14,\n\tSEL_CHECKREQPROT = 15,\n\tSEL_COMPAT_NET = 16,\n\tSEL_REJECT_UNKNOWN = 17,\n\tSEL_DENY_UNKNOWN = 18,\n\tSEL_STATUS = 19,\n\tSEL_POLICY = 20,\n\tSEL_VALIDATE_TRANS = 21,\n\tSEL_INO_NEXT = 22,\n};\n\nenum selinux_nlgroups {\n\tSELNLGRP_NONE = 0,\n\tSELNLGRP_AVC = 1,\n\t__SELNLGRP_MAX = 2,\n};\n\nenum sensors {\n\tFAN = 0,\n\tTEMP = 1,\n\tPOWER_SUPPLY = 2,\n\tPOWER_INPUT = 3,\n\tCURRENT = 4,\n\tENERGY = 5,\n\tMAX_SENSOR_TYPE = 6,\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nenum set_event_iter_type {\n\tSET_EVENT_FILE = 0,\n\tSET_EVENT_MOD = 1,\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_NOALLOC = 1,\n\tSGP_CACHE = 2,\n\tSGP_WRITE = 3,\n\tSGP_FALLOC = 4,\n};\n\nenum shmem_param {\n\tOpt_gid___8 = 0,\n\tOpt_huge = 1,\n\tOpt_mode___7 = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes___2 = 5,\n\tOpt_size___2 = 6,\n\tOpt_uid___7 = 7,\n\tOpt_inode32___2 = 8,\n\tOpt_inode64___2 = 9,\n\tOpt_noswap = 10,\n\tOpt_quota___3 = 11,\n\tOpt_usrquota___3 = 12,\n\tOpt_grpquota___3 = 13,\n\tOpt_usrquota_block_hardlimit = 14,\n\tOpt_usrquota_inode_hardlimit = 15,\n\tOpt_grpquota_block_hardlimit = 16,\n\tOpt_grpquota_inode_hardlimit = 17,\n\tOpt_casefold_version = 18,\n\tOpt_casefold = 19,\n\tOpt_strict_encoding = 20,\n};\n\nenum sig_handler {\n\tHANDLER_CURRENT = 0,\n\tHANDLER_SIG_DFL = 1,\n\tHANDLER_EXIT = 2,\n};\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_TRAPNO = 4,\n\tSIL_FAULT_MCEERR = 5,\n\tSIL_FAULT_BNDERR = 6,\n\tSIL_FAULT_PKUERR = 7,\n\tSIL_FAULT_PERF_EVENT = 8,\n\tSIL_CHLD = 9,\n\tSIL_RT = 10,\n\tSIL_SYS = 11,\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n\tSK_PSOCK_RX_STRP_ENABLED = 1,\n};\n\nenum sk_rst_reason {\n\tSK_RST_REASON_NOT_SPECIFIED = 0,\n\tSK_RST_REASON_NO_SOCKET = 1,\n\tSK_RST_REASON_TCP_INVALID_ACK_SEQUENCE = 2,\n\tSK_RST_REASON_TCP_RFC7323_PAWS = 3,\n\tSK_RST_REASON_TCP_TOO_OLD_ACK = 4,\n\tSK_RST_REASON_TCP_ACK_UNSENT_DATA = 5,\n\tSK_RST_REASON_TCP_FLAGS = 6,\n\tSK_RST_REASON_TCP_OLD_ACK = 7,\n\tSK_RST_REASON_TCP_ABORT_ON_DATA = 8,\n\tSK_RST_REASON_TCP_TIMEWAIT_SOCKET = 9,\n\tSK_RST_REASON_INVALID_SYN = 10,\n\tSK_RST_REASON_TCP_ABORT_ON_CLOSE = 11,\n\tSK_RST_REASON_TCP_ABORT_ON_LINGER = 12,\n\tSK_RST_REASON_TCP_ABORT_ON_MEMORY = 13,\n\tSK_RST_REASON_TCP_STATE = 14,\n\tSK_RST_REASON_TCP_KEEPALIVE_TIMEOUT = 15,\n\tSK_RST_REASON_TCP_DISCONNECT_WITH_DATA = 16,\n\tSK_RST_REASON_MPTCP_RST_EUNSPEC = 17,\n\tSK_RST_REASON_MPTCP_RST_EMPTCP = 18,\n\tSK_RST_REASON_MPTCP_RST_ERESOURCE = 19,\n\tSK_RST_REASON_MPTCP_RST_EPROHIBIT = 20,\n\tSK_RST_REASON_MPTCP_RST_EWQ2BIG = 21,\n\tSK_RST_REASON_MPTCP_RST_EBADPERF = 22,\n\tSK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 23,\n\tSK_RST_REASON_ERROR = 24,\n\tSK_RST_REASON_MAX = 25,\n};\n\nenum skb_drop_reason {\n\tSKB_NOT_DROPPED_YET = 0,\n\tSKB_CONSUMED = 1,\n\tSKB_DROP_REASON_NOT_SPECIFIED = 2,\n\tSKB_DROP_REASON_NO_SOCKET = 3,\n\tSKB_DROP_REASON_SOCKET_CLOSE = 4,\n\tSKB_DROP_REASON_SOCKET_FILTER = 5,\n\tSKB_DROP_REASON_SOCKET_RCVBUFF = 6,\n\tSKB_DROP_REASON_UNIX_DISCONNECT = 7,\n\tSKB_DROP_REASON_UNIX_SKIP_OOB = 8,\n\tSKB_DROP_REASON_PKT_TOO_SMALL = 9,\n\tSKB_DROP_REASON_TCP_CSUM = 10,\n\tSKB_DROP_REASON_UDP_CSUM = 11,\n\tSKB_DROP_REASON_NETFILTER_DROP = 12,\n\tSKB_DROP_REASON_OTHERHOST = 13,\n\tSKB_DROP_REASON_IP_CSUM = 14,\n\tSKB_DROP_REASON_IP_INHDR = 15,\n\tSKB_DROP_REASON_IP_RPFILTER = 16,\n\tSKB_DROP_REASON_UNICAST_IN_L2_MULTICAST = 17,\n\tSKB_DROP_REASON_XFRM_POLICY = 18,\n\tSKB_DROP_REASON_IP_NOPROTO = 19,\n\tSKB_DROP_REASON_PROTO_MEM = 20,\n\tSKB_DROP_REASON_TCP_AUTH_HDR = 21,\n\tSKB_DROP_REASON_TCP_MD5NOTFOUND = 22,\n\tSKB_DROP_REASON_TCP_MD5UNEXPECTED = 23,\n\tSKB_DROP_REASON_TCP_MD5FAILURE = 24,\n\tSKB_DROP_REASON_TCP_AONOTFOUND = 25,\n\tSKB_DROP_REASON_TCP_AOUNEXPECTED = 26,\n\tSKB_DROP_REASON_TCP_AOKEYNOTFOUND = 27,\n\tSKB_DROP_REASON_TCP_AOFAILURE = 28,\n\tSKB_DROP_REASON_SOCKET_BACKLOG = 29,\n\tSKB_DROP_REASON_TCP_FLAGS = 30,\n\tSKB_DROP_REASON_TCP_ABORT_ON_DATA = 31,\n\tSKB_DROP_REASON_TCP_ZEROWINDOW = 32,\n\tSKB_DROP_REASON_TCP_OLD_DATA = 33,\n\tSKB_DROP_REASON_TCP_OVERWINDOW = 34,\n\tSKB_DROP_REASON_TCP_OFOMERGE = 35,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS = 36,\n\tSKB_DROP_REASON_TCP_RFC7323_PAWS_ACK = 37,\n\tSKB_DROP_REASON_TCP_RFC7323_TW_PAWS = 38,\n\tSKB_DROP_REASON_TCP_RFC7323_TSECR = 39,\n\tSKB_DROP_REASON_TCP_LISTEN_OVERFLOW = 40,\n\tSKB_DROP_REASON_TCP_OLD_SEQUENCE = 41,\n\tSKB_DROP_REASON_TCP_INVALID_SEQUENCE = 42,\n\tSKB_DROP_REASON_TCP_INVALID_END_SEQUENCE = 43,\n\tSKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 44,\n\tSKB_DROP_REASON_TCP_RESET = 45,\n\tSKB_DROP_REASON_TCP_INVALID_SYN = 46,\n\tSKB_DROP_REASON_TCP_CLOSE = 47,\n\tSKB_DROP_REASON_TCP_FASTOPEN = 48,\n\tSKB_DROP_REASON_TCP_OLD_ACK = 49,\n\tSKB_DROP_REASON_TCP_TOO_OLD_ACK = 50,\n\tSKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 51,\n\tSKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 52,\n\tSKB_DROP_REASON_TCP_OFO_DROP = 53,\n\tSKB_DROP_REASON_IP_OUTNOROUTES = 54,\n\tSKB_DROP_REASON_BPF_CGROUP_EGRESS = 55,\n\tSKB_DROP_REASON_IPV6DISABLED = 56,\n\tSKB_DROP_REASON_NEIGH_CREATEFAIL = 57,\n\tSKB_DROP_REASON_NEIGH_FAILED = 58,\n\tSKB_DROP_REASON_NEIGH_QUEUEFULL = 59,\n\tSKB_DROP_REASON_NEIGH_DEAD = 60,\n\tSKB_DROP_REASON_NEIGH_HH_FILLFAIL = 61,\n\tSKB_DROP_REASON_TC_EGRESS = 62,\n\tSKB_DROP_REASON_SECURITY_HOOK = 63,\n\tSKB_DROP_REASON_QDISC_DROP = 64,\n\tSKB_DROP_REASON_QDISC_BURST_DROP = 65,\n\tSKB_DROP_REASON_QDISC_OVERLIMIT = 66,\n\tSKB_DROP_REASON_QDISC_CONGESTED = 67,\n\tSKB_DROP_REASON_CAKE_FLOOD = 68,\n\tSKB_DROP_REASON_FQ_BAND_LIMIT = 69,\n\tSKB_DROP_REASON_FQ_HORIZON_LIMIT = 70,\n\tSKB_DROP_REASON_FQ_FLOW_LIMIT = 71,\n\tSKB_DROP_REASON_CPU_BACKLOG = 72,\n\tSKB_DROP_REASON_XDP = 73,\n\tSKB_DROP_REASON_TC_INGRESS = 74,\n\tSKB_DROP_REASON_UNHANDLED_PROTO = 75,\n\tSKB_DROP_REASON_SKB_CSUM = 76,\n\tSKB_DROP_REASON_SKB_GSO_SEG = 77,\n\tSKB_DROP_REASON_SKB_UCOPY_FAULT = 78,\n\tSKB_DROP_REASON_DEV_HDR = 79,\n\tSKB_DROP_REASON_DEV_READY = 80,\n\tSKB_DROP_REASON_FULL_RING = 81,\n\tSKB_DROP_REASON_NOMEM = 82,\n\tSKB_DROP_REASON_HDR_TRUNC = 83,\n\tSKB_DROP_REASON_TAP_FILTER = 84,\n\tSKB_DROP_REASON_TAP_TXFILTER = 85,\n\tSKB_DROP_REASON_ICMP_CSUM = 86,\n\tSKB_DROP_REASON_INVALID_PROTO = 87,\n\tSKB_DROP_REASON_IP_INADDRERRORS = 88,\n\tSKB_DROP_REASON_IP_INNOROUTES = 89,\n\tSKB_DROP_REASON_IP_LOCAL_SOURCE = 90,\n\tSKB_DROP_REASON_IP_INVALID_SOURCE = 91,\n\tSKB_DROP_REASON_IP_LOCALNET = 92,\n\tSKB_DROP_REASON_IP_INVALID_DEST = 93,\n\tSKB_DROP_REASON_PKT_TOO_BIG = 94,\n\tSKB_DROP_REASON_DUP_FRAG = 95,\n\tSKB_DROP_REASON_FRAG_REASM_TIMEOUT = 96,\n\tSKB_DROP_REASON_FRAG_TOO_FAR = 97,\n\tSKB_DROP_REASON_TCP_MINTTL = 98,\n\tSKB_DROP_REASON_IPV6_BAD_EXTHDR = 99,\n\tSKB_DROP_REASON_IPV6_NDISC_FRAG = 100,\n\tSKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 101,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 102,\n\tSKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 103,\n\tSKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 104,\n\tSKB_DROP_REASON_QUEUE_PURGE = 105,\n\tSKB_DROP_REASON_TC_COOKIE_ERROR = 106,\n\tSKB_DROP_REASON_PACKET_SOCK_ERROR = 107,\n\tSKB_DROP_REASON_TC_CHAIN_NOTFOUND = 108,\n\tSKB_DROP_REASON_TC_RECLASSIFY_LOOP = 109,\n\tSKB_DROP_REASON_VXLAN_INVALID_HDR = 110,\n\tSKB_DROP_REASON_VXLAN_VNI_NOT_FOUND = 111,\n\tSKB_DROP_REASON_MAC_INVALID_SOURCE = 112,\n\tSKB_DROP_REASON_VXLAN_ENTRY_EXISTS = 113,\n\tSKB_DROP_REASON_NO_TX_TARGET = 114,\n\tSKB_DROP_REASON_IP_TUNNEL_ECN = 115,\n\tSKB_DROP_REASON_TUNNEL_TXINFO = 116,\n\tSKB_DROP_REASON_LOCAL_MAC = 117,\n\tSKB_DROP_REASON_ARP_PVLAN_DISABLE = 118,\n\tSKB_DROP_REASON_MAC_IEEE_MAC_CONTROL = 119,\n\tSKB_DROP_REASON_BRIDGE_INGRESS_STP_STATE = 120,\n\tSKB_DROP_REASON_CAN_RX_INVALID_FRAME = 121,\n\tSKB_DROP_REASON_CANFD_RX_INVALID_FRAME = 122,\n\tSKB_DROP_REASON_CANXL_RX_INVALID_FRAME = 123,\n\tSKB_DROP_REASON_PFMEMALLOC = 124,\n\tSKB_DROP_REASON_DUALPI2_STEP_DROP = 125,\n\tSKB_DROP_REASON_PSP_INPUT = 126,\n\tSKB_DROP_REASON_PSP_OUTPUT = 127,\n\tSKB_DROP_REASON_MAX = 128,\n\tSKB_DROP_REASON_SUBSYS_MASK = 4294901760,\n};\n\nenum skb_drop_reason_subsys {\n\tSKB_DROP_REASON_SUBSYS_CORE = 0,\n\tSKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1,\n\tSKB_DROP_REASON_SUBSYS_OPENVSWITCH = 2,\n\tSKB_DROP_REASON_SUBSYS_NUM = 3,\n};\n\nenum skb_ext_id {\n\tSKB_EXT_SEC_PATH = 0,\n\tSKB_EXT_NUM = 1,\n};\n\nenum skb_tstamp_type {\n\tSKB_CLOCK_REALTIME = 0,\n\tSKB_CLOCK_MONOTONIC = 1,\n\tSKB_CLOCK_TAI = 2,\n\t__SKB_CLOCK_MAX = 2,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nenum slab_flags {\n\tSL_locked = 0,\n\tSL_partial = 9,\n\tSL_pfmemalloc = 8,\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nenum slab_state {\n\tDOWN = 0,\n\tPARTIAL = 1,\n\tUP = 2,\n\tFULL = 3,\n};\n\nenum slb_index {\n\tLINEAR_INDEX = 0,\n\tKSTACK_INDEX = 1,\n};\n\nenum smt_mitigations {\n\tSMT_MITIGATIONS_OFF = 0,\n\tSMT_MITIGATIONS_AUTO = 1,\n\tSMT_MITIGATIONS_ON = 2,\n};\n\nenum snoop_when {\n\tSUBMIT = 0,\n\tCOMPLETE = 1,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_MEMALLOC = 14,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 15,\n\tSOCK_FASYNC = 16,\n\tSOCK_RXQ_OVFL = 17,\n\tSOCK_ZEROCOPY = 18,\n\tSOCK_WIFI_STATUS = 19,\n\tSOCK_NOFCS = 20,\n\tSOCK_FILTER_LOCKED = 21,\n\tSOCK_SELECT_ERR_QUEUE = 22,\n\tSOCK_RCU_FREE = 23,\n\tSOCK_TXTIME = 24,\n\tSOCK_XDP = 25,\n\tSOCK_TSTAMP_NEW = 26,\n\tSOCK_RCVMARK = 27,\n\tSOCK_RCVPRIORITY = 28,\n\tSOCK_TIMESTAMPING_ANY = 29,\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum socket_flags {\n\tSOCKWQ_ASYNC_NOSPACE = 0,\n\tSOCKWQ_ASYNC_WAITDATA = 1,\n\tSOCK_NOSPACE = 2,\n\tSOCK_SUPPORT_ZC = 3,\n\tSOCK_CUSTOM_SOCKOPT = 4,\n};\n\nenum softleaf_type {\n\tSOFTLEAF_NONE = 0,\n\tSOFTLEAF_SWAP = 1,\n\tSOFTLEAF_MIGRATION_READ = 2,\n\tSOFTLEAF_MIGRATION_READ_EXCLUSIVE = 3,\n\tSOFTLEAF_MIGRATION_WRITE = 4,\n\tSOFTLEAF_DEVICE_PRIVATE_READ = 5,\n\tSOFTLEAF_DEVICE_PRIVATE_WRITE = 6,\n\tSOFTLEAF_DEVICE_EXCLUSIVE = 7,\n\tSOFTLEAF_HWPOISON = 8,\n\tSOFTLEAF_MARKER = 9,\n};\n\nenum special_kfunc_type {\n\tKF_bpf_obj_new_impl = 0,\n\tKF_bpf_obj_drop_impl = 1,\n\tKF_bpf_refcount_acquire_impl = 2,\n\tKF_bpf_list_push_front_impl = 3,\n\tKF_bpf_list_push_back_impl = 4,\n\tKF_bpf_list_pop_front = 5,\n\tKF_bpf_list_pop_back = 6,\n\tKF_bpf_list_front = 7,\n\tKF_bpf_list_back = 8,\n\tKF_bpf_cast_to_kern_ctx = 9,\n\tKF_bpf_rdonly_cast = 10,\n\tKF_bpf_rcu_read_lock = 11,\n\tKF_bpf_rcu_read_unlock = 12,\n\tKF_bpf_rbtree_remove = 13,\n\tKF_bpf_rbtree_add_impl = 14,\n\tKF_bpf_rbtree_first = 15,\n\tKF_bpf_rbtree_root = 16,\n\tKF_bpf_rbtree_left = 17,\n\tKF_bpf_rbtree_right = 18,\n\tKF_bpf_dynptr_from_skb = 19,\n\tKF_bpf_dynptr_from_xdp = 20,\n\tKF_bpf_dynptr_from_skb_meta = 21,\n\tKF_bpf_xdp_pull_data = 22,\n\tKF_bpf_dynptr_slice = 23,\n\tKF_bpf_dynptr_slice_rdwr = 24,\n\tKF_bpf_dynptr_clone = 25,\n\tKF_bpf_percpu_obj_new_impl = 26,\n\tKF_bpf_percpu_obj_drop_impl = 27,\n\tKF_bpf_throw = 28,\n\tKF_bpf_wq_set_callback = 29,\n\tKF_bpf_preempt_disable = 30,\n\tKF_bpf_preempt_enable = 31,\n\tKF_bpf_iter_css_task_new = 32,\n\tKF_bpf_session_cookie = 33,\n\tKF_bpf_get_kmem_cache = 34,\n\tKF_bpf_local_irq_save = 35,\n\tKF_bpf_local_irq_restore = 36,\n\tKF_bpf_iter_num_new = 37,\n\tKF_bpf_iter_num_next = 38,\n\tKF_bpf_iter_num_destroy = 39,\n\tKF_bpf_set_dentry_xattr = 40,\n\tKF_bpf_remove_dentry_xattr = 41,\n\tKF_bpf_res_spin_lock = 42,\n\tKF_bpf_res_spin_unlock = 43,\n\tKF_bpf_res_spin_lock_irqsave = 44,\n\tKF_bpf_res_spin_unlock_irqrestore = 45,\n\tKF_bpf_dynptr_from_file = 46,\n\tKF_bpf_dynptr_file_discard = 47,\n\tKF___bpf_trap = 48,\n\tKF_bpf_task_work_schedule_signal = 49,\n\tKF_bpf_task_work_schedule_resume = 50,\n\tKF_bpf_arena_alloc_pages = 51,\n\tKF_bpf_arena_free_pages = 52,\n\tKF_bpf_arena_reserve_pages = 53,\n\tKF_bpf_session_is_return = 54,\n\tKF_bpf_stream_vprintk = 55,\n\tKF_bpf_stream_print_stack = 56,\n};\n\nenum split_type {\n\tSPLIT_TYPE_UNIFORM = 0,\n\tSPLIT_TYPE_NON_UNIFORM = 1,\n};\n\nenum spu_utilization_state {\n\tSPU_UTIL_USER = 0,\n\tSPU_UTIL_SYSTEM = 1,\n\tSPU_UTIL_IOWAIT = 2,\n\tSPU_UTIL_IDLE_LOADED = 3,\n\tSPU_UTIL_MAX = 4,\n};\n\nenum sr_retry_flags {\n\tIORING_RECV_RETRY = 32768,\n\tIORING_RECV_PARTIAL_MAP = 16384,\n\tIORING_RECV_MSHOT_CAP = 8192,\n\tIORING_RECV_MSHOT_LIM = 4096,\n\tIORING_RECV_MSHOT_DONE = 2048,\n\tIORING_RECV_RETRY_CLEAR = 49152,\n\tIORING_RECV_NO_RETRY = 59392,\n};\n\nenum srp_rport_state {\n\tSRP_RPORT_RUNNING = 0,\n\tSRP_RPORT_BLOCKED = 1,\n\tSRP_RPORT_FAIL_FAST = 2,\n\tSRP_RPORT_LOST = 3,\n};\n\nenum ss_state {\n\tss_done = 0,\n\tss_lock = 1,\n\tss_lock_irqsave = 2,\n\tss_lockless = 3,\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_RCU_SHEAF = 2,\n\tFREE_RCU_SHEAF_FAIL = 3,\n\tFREE_FASTPATH = 4,\n\tFREE_SLOWPATH = 5,\n\tFREE_ADD_PARTIAL = 6,\n\tFREE_REMOVE_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_NODE_MISMATCH = 9,\n\tFREE_SLAB = 10,\n\tORDER_FALLBACK = 11,\n\tCMPXCHG_DOUBLE_FAIL = 12,\n\tSHEAF_FLUSH = 13,\n\tSHEAF_REFILL = 14,\n\tSHEAF_ALLOC = 15,\n\tSHEAF_FREE = 16,\n\tBARN_GET = 17,\n\tBARN_GET_FAIL = 18,\n\tBARN_PUT = 19,\n\tBARN_PUT_FAIL = 20,\n\tSHEAF_PREFILL_FAST = 21,\n\tSHEAF_PREFILL_SLOW = 22,\n\tSHEAF_PREFILL_OVERSIZE = 23,\n\tSHEAF_RETURN_FAST = 24,\n\tSHEAF_RETURN_SLOW = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\nenum state_protect_how4 {\n\tSP4_NONE = 0,\n\tSP4_MACH_CRED = 1,\n\tSP4_SSV = 2,\n};\n\nenum stf_barrier_type {\n\tSTF_BARRIER_NONE = 1,\n\tSTF_BARRIER_FALLBACK = 2,\n\tSTF_BARRIER_EIEIO = 4,\n\tSTF_BARRIER_SYNC_ORI = 8,\n};\n\nenum store_type {\n\twr_invalid = 0,\n\twr_new_root = 1,\n\twr_store_root = 2,\n\twr_exact_fit = 3,\n\twr_spanning_store = 4,\n\twr_split_store = 5,\n\twr_rebalance = 6,\n\twr_append = 7,\n\twr_node_store = 8,\n\twr_slot_store = 9,\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n\tSTRING_UNITS_MASK = 1,\n\tSTRING_UNITS_NO_SPACE = 1073741824,\n\tSTRING_UNITS_NO_BYTES = 2147483648,\n};\n\nenum stripetype4 {\n\tSTRIPE_SPARSE = 1,\n\tSTRIPE_DENSE = 2,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\nenum super_iter_flags_t {\n\tSUPER_ITER_EXCL = 1,\n\tSUPER_ITER_UNLOCKED = 2,\n\tSUPER_ITER_REVERSE = 4,\n};\n\nenum support_mode {\n\tALLOW_LEGACY = 0,\n\tDENY_LEGACY = 1,\n};\n\nenum suspend_mode {\n\tPRESUSPEND = 0,\n\tPRESUSPEND_UNDO = 1,\n\tPOSTSUSPEND = 2,\n};\n\nenum suspend_stat_step {\n\tSUSPEND_WORKING = 0,\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nenum svc_auth_status {\n\tSVC_GARBAGE = 1,\n\tSVC_VALID = 2,\n\tSVC_NEGATIVE = 3,\n\tSVC_OK = 4,\n\tSVC_DROP = 5,\n\tSVC_CLOSE = 6,\n\tSVC_DENIED = 7,\n\tSVC_PENDING = 8,\n\tSVC_COMPLETE = 9,\n};\n\nenum sw_activity {\n\tOFF = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nenum swap_cluster_flags {\n\tCLUSTER_FLAG_NONE = 0,\n\tCLUSTER_FLAG_FREE = 1,\n\tCLUSTER_FLAG_NONFULL = 2,\n\tCLUSTER_FLAG_FRAG = 3,\n\tCLUSTER_FLAG_USABLE = 3,\n\tCLUSTER_FLAG_FULL = 4,\n\tCLUSTER_FLAG_DISCARD = 5,\n\tCLUSTER_FLAG_MAX = 6,\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nenum sync_action {\n\tACTION_RESYNC = 0,\n\tACTION_RECOVER = 1,\n\tACTION_CHECK = 2,\n\tACTION_REPAIR = 3,\n\tACTION_RESHAPE = 4,\n\tACTION_FROZEN = 5,\n\tACTION_IDLE = 6,\n\tNR_SYNC_ACTIONS = 7,\n};\n\nenum sys_off_mode {\n\tSYS_OFF_MODE_POWER_OFF_PREPARE = 0,\n\tSYS_OFF_MODE_POWER_OFF = 1,\n\tSYS_OFF_MODE_RESTART_PREPARE = 2,\n\tSYS_OFF_MODE_RESTART = 3,\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = -1,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_FREEING_INITMEM = 2,\n\tSYSTEM_RUNNING = 3,\n\tSYSTEM_HALT = 4,\n\tSYSTEM_POWER_OFF = 5,\n\tSYSTEM_RESTART = 6,\n\tSYSTEM_SUSPEND = 7,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum target_state {\n\tSTATE_DISABLED = 0,\n\tSTATE_ENABLED = 1,\n\tSTATE_DEACTIVATED = 2,\n};\n\nenum task_work_notify_mode {\n\tTWA_NONE = 0,\n\tTWA_RESUME = 1,\n\tTWA_SIGNAL = 2,\n\tTWA_SIGNAL_NO_IPI = 3,\n\tTWA_NMI_CURRENT = 4,\n};\n\nenum tc_fifo_command {\n\tTC_FIFO_REPLACE = 0,\n\tTC_FIFO_DESTROY = 1,\n\tTC_FIFO_STATS = 2,\n};\n\nenum tc_link_layer {\n\tTC_LINKLAYER_UNAWARE = 0,\n\tTC_LINKLAYER_ETHERNET = 1,\n\tTC_LINKLAYER_ATM = 2,\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nenum tc_root_command {\n\tTC_ROOT_GRAFT = 0,\n};\n\nenum tc_setup_type {\n\tTC_QUERY_CAPS = 0,\n\tTC_SETUP_QDISC_MQPRIO = 1,\n\tTC_SETUP_CLSU32 = 2,\n\tTC_SETUP_CLSFLOWER = 3,\n\tTC_SETUP_CLSMATCHALL = 4,\n\tTC_SETUP_CLSBPF = 5,\n\tTC_SETUP_BLOCK = 6,\n\tTC_SETUP_QDISC_CBS = 7,\n\tTC_SETUP_QDISC_RED = 8,\n\tTC_SETUP_QDISC_PRIO = 9,\n\tTC_SETUP_QDISC_MQ = 10,\n\tTC_SETUP_QDISC_ETF = 11,\n\tTC_SETUP_ROOT_QDISC = 12,\n\tTC_SETUP_QDISC_GRED = 13,\n\tTC_SETUP_QDISC_TAPRIO = 14,\n\tTC_SETUP_FT = 15,\n\tTC_SETUP_QDISC_ETS = 16,\n\tTC_SETUP_QDISC_TBF = 17,\n\tTC_SETUP_QDISC_FIFO = 18,\n\tTC_SETUP_QDISC_HTB = 19,\n\tTC_SETUP_ACT = 20,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nenum tcf_proto_ops_flags {\n\tTCF_PROTO_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum tcp_accecn_option {\n\tTCP_ACCECN_OPTION_DISABLED = 0,\n\tTCP_ACCECN_OPTION_MINIMUM = 1,\n\tTCP_ACCECN_OPTION_FULL = 2,\n\tTCP_ACCECN_OPTION_PERSIST = 3,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nenum tcp_conntrack {\n\tTCP_CONNTRACK_NONE = 0,\n\tTCP_CONNTRACK_SYN_SENT = 1,\n\tTCP_CONNTRACK_SYN_RECV = 2,\n\tTCP_CONNTRACK_ESTABLISHED = 3,\n\tTCP_CONNTRACK_FIN_WAIT = 4,\n\tTCP_CONNTRACK_CLOSE_WAIT = 5,\n\tTCP_CONNTRACK_LAST_ACK = 6,\n\tTCP_CONNTRACK_TIME_WAIT = 7,\n\tTCP_CONNTRACK_CLOSE = 8,\n\tTCP_CONNTRACK_LISTEN = 9,\n\tTCP_CONNTRACK_MAX = 10,\n\tTCP_CONNTRACK_IGNORE = 11,\n\tTCP_CONNTRACK_RETRANS = 12,\n\tTCP_CONNTRACK_UNACK = 13,\n\tTCP_CONNTRACK_TIMEOUT_MAX = 14,\n};\n\nenum tcp_ecn_mode {\n\tTCP_ECN_IN_NOECN_OUT_NOECN = 0,\n\tTCP_ECN_IN_ECN_OUT_ECN = 1,\n\tTCP_ECN_IN_ECN_OUT_NOECN = 2,\n\tTCP_ECN_IN_ACCECN_OUT_ACCECN = 3,\n\tTCP_ECN_IN_ACCECN_OUT_ECN = 4,\n\tTCP_ECN_IN_ACCECN_OUT_NOECN = 5,\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nenum tcp_skb_cb_sacked_flags {\n\tTCPCB_SACKED_ACKED = 1,\n\tTCPCB_SACKED_RETRANS = 2,\n\tTCPCB_LOST = 4,\n\tTCPCB_TAGBITS = 7,\n\tTCPCB_REPAIRED = 16,\n\tTCPCB_EVER_RETRANS = 128,\n\tTCPCB_RETRANS = 146,\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n\tTCP_SYNACK_RETRANS = 3,\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n\tTCP_TW_ACK_OOW = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nenum tcpa_pc_event_ids {\n\tSMBIOS = 1,\n\tBIS_CERT = 2,\n\tPOST_BIOS_ROM = 3,\n\tESCD = 4,\n\tCMOS = 5,\n\tNVRAM = 6,\n\tOPTION_ROM_EXEC = 7,\n\tOPTION_ROM_CONFIG = 8,\n\tOPTION_ROM_MICROCODE = 10,\n\tS_CRTM_VERSION = 11,\n\tS_CRTM_CONTENTS = 12,\n\tPOST_CONTENTS = 13,\n\tHOST_TABLE_OF_DEVICES = 14,\n};\n\nenum tcx_action_base {\n\tTCX_NEXT = -1,\n\tTCX_PASS = 0,\n\tTCX_DROP = 2,\n\tTCX_REDIRECT = 7,\n};\n\nenum thermal_device_mode {\n\tTHERMAL_DEVICE_DISABLED = 0,\n\tTHERMAL_DEVICE_ENABLED = 1,\n};\n\nenum thermal_notify_event {\n\tTHERMAL_EVENT_UNSPECIFIED = 0,\n\tTHERMAL_EVENT_TEMP_SAMPLE = 1,\n\tTHERMAL_TRIP_VIOLATED = 2,\n\tTHERMAL_TRIP_CHANGED = 3,\n\tTHERMAL_DEVICE_DOWN = 4,\n\tTHERMAL_DEVICE_UP = 5,\n\tTHERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6,\n\tTHERMAL_TABLE_CHANGED = 7,\n\tTHERMAL_EVENT_KEEP_ALIVE = 8,\n\tTHERMAL_TZ_BIND_CDEV = 9,\n\tTHERMAL_TZ_UNBIND_CDEV = 10,\n\tTHERMAL_INSTANCE_WEIGHT_CHANGED = 11,\n\tTHERMAL_TZ_RESUME = 12,\n\tTHERMAL_TZ_ADD_THRESHOLD = 13,\n\tTHERMAL_TZ_DEL_THRESHOLD = 14,\n\tTHERMAL_TZ_FLUSH_THRESHOLDS = 15,\n};\n\nenum thermal_trend {\n\tTHERMAL_TREND_STABLE = 0,\n\tTHERMAL_TREND_RAISING = 1,\n\tTHERMAL_TREND_DROPPING = 2,\n};\n\nenum thermal_trip_type {\n\tTHERMAL_TRIP_ACTIVE = 0,\n\tTHERMAL_TRIP_PASSIVE = 1,\n\tTHERMAL_TRIP_HOT = 2,\n\tTHERMAL_TRIP_CRITICAL = 3,\n};\n\nenum throttle_reason_type {\n\tNO_THROTTLE = 0,\n\tPOWERCAP = 1,\n\tCPU_OVERTEMP = 2,\n\tPOWER_SUPPLY_FAILURE = 3,\n\tOVERCURRENT = 4,\n\tOCC_RESET_THROTTLE = 5,\n\tOCC_MAX_REASON = 6,\n};\n\nenum tick_broadcast_mode {\n\tTICK_BROADCAST_OFF = 0,\n\tTICK_BROADCAST_ON = 1,\n\tTICK_BROADCAST_FORCE = 2,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nenum timekeeper_ids {\n\tTIMEKEEPER_CORE = 0,\n\tTIMEKEEPERS_MAX = 1,\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nenum tlb_flush_type {\n\tFLUSH_TYPE_NONE = 0,\n\tFLUSH_TYPE_LOCAL = 1,\n\tFLUSH_TYPE_GLOBAL = 2,\n};\n\nenum tp_func_state {\n\tTP_FUNC_0 = 0,\n\tTP_FUNC_1 = 1,\n\tTP_FUNC_2 = 2,\n\tTP_FUNC_N = 3,\n};\n\nenum tp_transition_sync {\n\tTP_TRANSITION_SYNC_1_0_1 = 0,\n\tTP_TRANSITION_SYNC_N_2_1 = 1,\n\t_NR_TP_TRANSITION_SYNC = 2,\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nenum tph_mem_type {\n\tTPH_MEM_TYPE_VM = 0,\n\tTPH_MEM_TYPE_PM = 1,\n};\n\nenum tpm2_capabilities {\n\tTPM2_CAP_HANDLES = 1,\n\tTPM2_CAP_COMMANDS = 2,\n\tTPM2_CAP_PCRS = 5,\n\tTPM2_CAP_TPM_PROPERTIES = 6,\n};\n\nenum tpm2_cc_attrs {\n\tTPM2_CC_ATTR_CHANDLES = 25,\n\tTPM2_CC_ATTR_RHANDLE = 28,\n\tTPM2_CC_ATTR_VENDOR = 29,\n};\n\nenum tpm2_command_codes {\n\tTPM2_CC_FIRST = 287,\n\tTPM2_CC_HIERARCHY_CONTROL = 289,\n\tTPM2_CC_HIERARCHY_CHANGE_AUTH = 297,\n\tTPM2_CC_CREATE_PRIMARY = 305,\n\tTPM2_CC_SEQUENCE_COMPLETE = 318,\n\tTPM2_CC_SELF_TEST = 323,\n\tTPM2_CC_STARTUP = 324,\n\tTPM2_CC_SHUTDOWN = 325,\n\tTPM2_CC_NV_READ = 334,\n\tTPM2_CC_CREATE = 339,\n\tTPM2_CC_LOAD = 343,\n\tTPM2_CC_SEQUENCE_UPDATE = 348,\n\tTPM2_CC_UNSEAL = 350,\n\tTPM2_CC_CONTEXT_LOAD = 353,\n\tTPM2_CC_CONTEXT_SAVE = 354,\n\tTPM2_CC_FLUSH_CONTEXT = 357,\n\tTPM2_CC_READ_PUBLIC = 371,\n\tTPM2_CC_START_AUTH_SESS = 374,\n\tTPM2_CC_VERIFY_SIGNATURE = 375,\n\tTPM2_CC_GET_CAPABILITY = 378,\n\tTPM2_CC_GET_RANDOM = 379,\n\tTPM2_CC_PCR_READ = 382,\n\tTPM2_CC_PCR_EXTEND = 386,\n\tTPM2_CC_EVENT_SEQUENCE_COMPLETE = 389,\n\tTPM2_CC_HASH_SEQUENCE_START = 390,\n\tTPM2_CC_CREATE_LOADED = 401,\n\tTPM2_CC_LAST = 403,\n};\n\nenum tpm2_const {\n\tTPM2_PLATFORM_PCR = 24,\n\tTPM2_PCR_SELECT_MIN = 3,\n};\n\nenum tpm2_durations {\n\tTPM2_DURATION_SHORT = 20,\n\tTPM2_DURATION_LONG = 2000,\n\tTPM2_DURATION_DEFAULT = 120000,\n};\n\nenum tpm2_handle_types {\n\tTPM2_HT_HMAC_SESSION = 33554432,\n\tTPM2_HT_POLICY_SESSION = 50331648,\n\tTPM2_HT_TRANSIENT = 2147483648,\n};\n\nenum tpm2_permanent_handles {\n\tTPM2_RH_NULL = 1073741831,\n\tTPM2_RS_PW = 1073741833,\n};\n\nenum tpm2_properties {\n\tTPM_PT_TOTAL_COMMANDS = 297,\n};\n\nenum tpm2_return_codes {\n\tTPM2_RC_SUCCESS = 0,\n\tTPM2_RC_HASH = 131,\n\tTPM2_RC_HANDLE = 139,\n\tTPM2_RC_INTEGRITY = 159,\n\tTPM2_RC_INITIALIZE = 256,\n\tTPM2_RC_FAILURE = 257,\n\tTPM2_RC_DISABLED = 288,\n\tTPM2_RC_UPGRADE = 301,\n\tTPM2_RC_COMMAND_CODE = 323,\n\tTPM2_RC_TESTING = 2314,\n\tTPM2_RC_REFERENCE_H0 = 2320,\n\tTPM2_RC_RETRY = 2338,\n\tTPM2_RC_SESSION_MEMORY = 2307,\n};\n\nenum tpm2_session_attributes {\n\tTPM2_SA_CONTINUE_SESSION = 1,\n\tTPM2_SA_AUDIT_EXCLUSIVE = 2,\n\tTPM2_SA_AUDIT_RESET = 8,\n\tTPM2_SA_DECRYPT = 32,\n\tTPM2_SA_ENCRYPT = 64,\n\tTPM2_SA_AUDIT = 128,\n};\n\nenum tpm2_startup_types {\n\tTPM2_SU_CLEAR = 0,\n\tTPM2_SU_STATE = 1,\n};\n\nenum tpm2_structures {\n\tTPM2_ST_NO_SESSIONS = 32769,\n\tTPM2_ST_SESSIONS = 32770,\n\tTPM2_ST_CREATION = 32801,\n};\n\nenum tpm2_timeouts {\n\tTPM2_TIMEOUT_A = 750,\n\tTPM2_TIMEOUT_B = 4000,\n\tTPM2_TIMEOUT_C = 200,\n\tTPM2_TIMEOUT_D = 30,\n};\n\nenum tpm_algorithms {\n\tTPM_ALG_ERROR = 0,\n\tTPM_ALG_SHA1 = 4,\n\tTPM_ALG_AES = 6,\n\tTPM_ALG_KEYEDHASH = 8,\n\tTPM_ALG_SHA256 = 11,\n\tTPM_ALG_SHA384 = 12,\n\tTPM_ALG_SHA512 = 13,\n\tTPM_ALG_NULL = 16,\n\tTPM_ALG_SM3_256 = 18,\n\tTPM_ALG_ECC = 35,\n\tTPM_ALG_CFB = 67,\n};\n\nenum tpm_buf_flags {\n\tTPM_BUF_OVERFLOW = 1,\n\tTPM_BUF_TPM2B = 2,\n\tTPM_BUF_BOUNDARY_ERROR = 4,\n};\n\nenum tpm_capabilities {\n\tTPM_CAP_FLAG = 4,\n\tTPM_CAP_PROP = 5,\n\tTPM_CAP_VERSION_1_1 = 6,\n\tTPM_CAP_VERSION_1_2 = 26,\n};\n\nenum tpm_chip_flags {\n\tTPM_CHIP_FLAG_BOOTSTRAPPED = 1,\n\tTPM_CHIP_FLAG_TPM2 = 2,\n\tTPM_CHIP_FLAG_IRQ = 4,\n\tTPM_CHIP_FLAG_VIRTUAL = 8,\n\tTPM_CHIP_FLAG_HAVE_TIMEOUTS = 16,\n\tTPM_CHIP_FLAG_ALWAYS_POWERED = 32,\n\tTPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED = 64,\n\tTPM_CHIP_FLAG_FIRMWARE_UPGRADE = 128,\n\tTPM_CHIP_FLAG_SUSPENDED = 256,\n\tTPM_CHIP_FLAG_HWRNG_DISABLED = 512,\n\tTPM_CHIP_FLAG_DISABLE = 1024,\n\tTPM_CHIP_FLAG_SYNC = 2048,\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum tpm_pcrs {\n\tTPM_PCR0 = 0,\n\tTPM_PCR8 = 8,\n\tTPM_PCR10 = 10,\n};\n\nenum tpm_sub_capabilities {\n\tTPM_CAP_PROP_PCR = 257,\n\tTPM_CAP_PROP_MANUFACTURER = 259,\n\tTPM_CAP_FLAG_PERM = 264,\n\tTPM_CAP_FLAG_VOL = 265,\n\tTPM_CAP_PROP_OWNER = 273,\n\tTPM_CAP_PROP_TIS_TIMEOUT = 277,\n\tTPM_CAP_PROP_TIS_DURATION = 288,\n};\n\nenum tpm_timeout {\n\tTPM_TIMEOUT = 5,\n\tTPM_TIMEOUT_RETRY = 100,\n\tTPM_TIMEOUT_RANGE_US = 300,\n\tTPM_TIMEOUT_POLL = 1,\n\tTPM_TIMEOUT_USECS_MIN = 100,\n\tTPM_TIMEOUT_USECS_MAX = 500,\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_NEED_RESCHED_LAZY = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n\tTRACE_FLAG_BH_OFF = 128,\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n\tTRACE_FILE_PAUSE = 8,\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_FIELDS_BIT = 8,\n\tTRACE_ITER_PRINTK_BIT = 9,\n\tTRACE_ITER_ANNOTATE_BIT = 10,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 11,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 12,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 13,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 14,\n\tTRACE_ITER_LATENCY_FMT_BIT = 15,\n\tTRACE_ITER_RECORD_CMD_BIT = 16,\n\tTRACE_ITER_RECORD_TGID_BIT = 17,\n\tTRACE_ITER_OVERWRITE_BIT = 18,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 19,\n\tTRACE_ITER_IRQ_INFO_BIT = 20,\n\tTRACE_ITER_MARKERS_BIT = 21,\n\tTRACE_ITER_EVENT_FORK_BIT = 22,\n\tTRACE_ITER_TRACE_PRINTK_BIT = 23,\n\tTRACE_ITER_COPY_MARKER_BIT = 24,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 25,\n\tTRACE_ITER_HASH_PTR_BIT = 26,\n\tTRACE_ITER_BITMASK_LIST_BIT = 27,\n\tTRACE_ITER_FUNCTION_BIT = 28,\n\tTRACE_ITER_FUNC_FORK_BIT = 29,\n\tTRACE_ITER_DISPLAY_GRAPH_BIT = 30,\n\tTRACE_ITER_STACKTRACE_BIT = 31,\n\tTRACE_ITER_LAST_BIT = 32,\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_GRAPH_RETADDR_ENT = 12,\n\tTRACE_USER_STACK = 13,\n\tTRACE_BLK = 14,\n\tTRACE_BPUTS = 15,\n\tTRACE_HWLAT = 16,\n\tTRACE_OSNOISE = 17,\n\tTRACE_TIMERLAT = 18,\n\tTRACE_RAW_DATA = 19,\n\tTRACE_FUNC_REPEATS = 20,\n\t__TRACE_LAST_TYPE = 21,\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nenum translation_map {\n\tLAT1_MAP = 0,\n\tGRAF_MAP = 1,\n\tIBMPC_MAP = 2,\n\tUSER_MAP = 3,\n\tFIRST_MAP = 0,\n\tLAST_MAP = 3,\n};\n\nenum transparent_hugepage_flag {\n\tTRANSPARENT_HUGEPAGE_UNSUPPORTED = 0,\n\tTRANSPARENT_HUGEPAGE_FLAG = 1,\n\tTRANSPARENT_HUGEPAGE_REQ_MADV_FLAG = 2,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_DIRECT_FLAG = 3,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_FLAG = 4,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_OR_MADV_FLAG = 5,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_REQ_MADV_FLAG = 6,\n\tTRANSPARENT_HUGEPAGE_DEFRAG_KHUGEPAGED_FLAG = 7,\n\tTRANSPARENT_HUGEPAGE_USE_ZERO_PAGE_FLAG = 8,\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n\tTCP_ACK_DEFERRED = 6,\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n\tTCPF_ACK_DEFERRED = 64,\n};\n\nenum ttu_flags {\n\tTTU_USE_SHARED_ZEROPAGE = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_SYNC = 16,\n\tTTU_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n};\n\nenum tty_driver_flag {\n\tTTY_DRIVER_INSTALLED = 1,\n\tTTY_DRIVER_RESET_TERMIOS = 2,\n\tTTY_DRIVER_REAL_RAW = 4,\n\tTTY_DRIVER_DYNAMIC_DEV = 8,\n\tTTY_DRIVER_DEVPTS_MEM = 16,\n\tTTY_DRIVER_HARDWARE_BREAK = 32,\n\tTTY_DRIVER_DYNAMIC_ALLOC = 64,\n\tTTY_DRIVER_UNNUMBERED_NODE = 128,\n};\n\nenum tty_driver_subtype {\n\tSYSTEM_TYPE_TTY = 1,\n\tSYSTEM_TYPE_CONSOLE = 2,\n\tSYSTEM_TYPE_SYSCONS = 3,\n\tSYSTEM_TYPE_SYSPTMX = 4,\n\tPTY_TYPE_MASTER = 1,\n\tPTY_TYPE_SLAVE = 2,\n\tSERIAL_TYPE_NORMAL = 1,\n};\n\nenum tty_driver_type {\n\tTTY_DRIVER_TYPE_SYSTEM = 0,\n\tTTY_DRIVER_TYPE_CONSOLE = 1,\n\tTTY_DRIVER_TYPE_SERIAL = 2,\n\tTTY_DRIVER_TYPE_PTY = 3,\n\tTTY_DRIVER_TYPE_SCC = 4,\n\tTTY_DRIVER_TYPE_SYSCONS = 5,\n};\n\nenum tty_flow_change {\n\tTTY_FLOW_NO_CHANGE = 0,\n\tTTY_THROTTLE_SAFE = 1,\n\tTTY_UNTHROTTLE_SAFE = 2,\n};\n\nenum tty_struct_flags {\n\tTTY_THROTTLED = 0,\n\tTTY_IO_ERROR = 1,\n\tTTY_OTHER_CLOSED = 2,\n\tTTY_EXCLUSIVE = 3,\n\tTTY_DO_WRITE_WAKEUP = 4,\n\tTTY_LDISC_OPEN = 5,\n\tTTY_PTY_LOCK = 6,\n\tTTY_NO_WRITE_SPLIT = 7,\n\tTTY_HUPPED = 8,\n\tTTY_HUPPING = 9,\n\tTTY_LDISC_CHANGING = 10,\n\tTTY_LDISC_HALTED = 11,\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\tETHTOOL_TX_COPYBREAK_BUF_SIZE = 4,\n\t__ETHTOOL_TUNABLE_COUNT = 5,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum tunnel_encap_types {\n\tTUNNEL_ENCAP_NONE = 0,\n\tTUNNEL_ENCAP_FOU = 1,\n\tTUNNEL_ENCAP_GUE = 2,\n\tTUNNEL_ENCAP_MPLS = 3,\n};\n\nenum tva_type {\n\tTVA_SMAPS = 0,\n\tTVA_PAGEFAULT = 1,\n\tTVA_KHUGEPAGED = 2,\n\tTVA_FORCED_COLLAPSE = 3,\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nenum uart_iotype {\n\tUPIO_UNKNOWN = -1,\n\tUPIO_PORT = 0,\n\tUPIO_HUB6 = 1,\n\tUPIO_MEM = 2,\n\tUPIO_MEM32 = 3,\n\tUPIO_AU = 4,\n\tUPIO_TSI = 5,\n\tUPIO_MEM32BE = 6,\n\tUPIO_MEM16 = 7,\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nenum uclamp_id {\n\tUCLAMP_MIN = 0,\n\tUCLAMP_MAX = 1,\n\tUCLAMP_CNT = 2,\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_COUNTS = 10,\n};\n\nenum udp_conntrack {\n\tUDP_CT_UNREPLIED = 0,\n\tUDP_CT_REPLIED = 1,\n\tUDP_CT_MAX = 2,\n};\n\nenum udp_parsable_tunnel_type {\n\tUDP_TUNNEL_TYPE_VXLAN = 1,\n\tUDP_TUNNEL_TYPE_GENEVE = 2,\n\tUDP_TUNNEL_TYPE_VXLAN_GPE = 4,\n};\n\nenum udp_tunnel_nic_info_flags {\n\tUDP_TUNNEL_NIC_INFO_OPEN_ONLY = 1,\n\tUDP_TUNNEL_NIC_INFO_IPV4_ONLY = 2,\n\tUDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN = 4,\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nenum unix_vertex_index {\n\tUNIX_VERTEX_INDEX_MARK1 = 0,\n\tUNIX_VERTEX_INDEX_MARK2 = 1,\n\tUNIX_VERTEX_INDEX_START = 2,\n};\n\nenum unwind_user_type_bits {\n\tUNWIND_USER_TYPE_FP_BIT = 0,\n\tNR_UNWIND_USER_TYPE_BITS = 1,\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nenum usb3_link_state {\n\tUSB3_LPM_U0 = 0,\n\tUSB3_LPM_U1 = 1,\n\tUSB3_LPM_U2 = 2,\n\tUSB3_LPM_U3 = 3,\n};\n\nenum usb_charger_state {\n\tUSB_CHARGER_DEFAULT = 0,\n\tUSB_CHARGER_PRESENT = 1,\n\tUSB_CHARGER_ABSENT = 2,\n};\n\nenum usb_charger_type {\n\tUNKNOWN_TYPE = 0,\n\tSDP_TYPE = 1,\n\tDCP_TYPE = 2,\n\tCDP_TYPE = 3,\n\tACA_TYPE = 4,\n};\n\nenum usb_dev_authorize_policy {\n\tUSB_DEVICE_AUTHORIZE_NONE = 0,\n\tUSB_DEVICE_AUTHORIZE_ALL = 1,\n\tUSB_DEVICE_AUTHORIZE_INTERNAL = 2,\n};\n\nenum usb_device_speed {\n\tUSB_SPEED_UNKNOWN = 0,\n\tUSB_SPEED_LOW = 1,\n\tUSB_SPEED_FULL = 2,\n\tUSB_SPEED_HIGH = 3,\n\tUSB_SPEED_WIRELESS = 4,\n\tUSB_SPEED_SUPER = 5,\n\tUSB_SPEED_SUPER_PLUS = 6,\n};\n\nenum usb_device_state {\n\tUSB_STATE_NOTATTACHED = 0,\n\tUSB_STATE_ATTACHED = 1,\n\tUSB_STATE_POWERED = 2,\n\tUSB_STATE_RECONNECTING = 3,\n\tUSB_STATE_UNAUTHENTICATED = 4,\n\tUSB_STATE_DEFAULT = 5,\n\tUSB_STATE_ADDRESS = 6,\n\tUSB_STATE_CONFIGURED = 7,\n\tUSB_STATE_SUSPENDED = 8,\n};\n\nenum usb_dr_mode {\n\tUSB_DR_MODE_UNKNOWN = 0,\n\tUSB_DR_MODE_HOST = 1,\n\tUSB_DR_MODE_PERIPHERAL = 2,\n\tUSB_DR_MODE_OTG = 3,\n};\n\nenum usb_interface_condition {\n\tUSB_INTERFACE_UNBOUND = 0,\n\tUSB_INTERFACE_BINDING = 1,\n\tUSB_INTERFACE_BOUND = 2,\n\tUSB_INTERFACE_UNBINDING = 3,\n};\n\nenum usb_led_event {\n\tUSB_LED_EVENT_HOST = 0,\n\tUSB_LED_EVENT_GADGET = 1,\n};\n\nenum usb_link_tunnel_mode {\n\tUSB_LINK_UNKNOWN = 0,\n\tUSB_LINK_NATIVE = 1,\n\tUSB_LINK_TUNNELED = 2,\n};\n\nenum usb_otg_state {\n\tOTG_STATE_UNDEFINED = 0,\n\tOTG_STATE_B_IDLE = 1,\n\tOTG_STATE_B_SRP_INIT = 2,\n\tOTG_STATE_B_PERIPHERAL = 3,\n\tOTG_STATE_B_WAIT_ACON = 4,\n\tOTG_STATE_B_HOST = 5,\n\tOTG_STATE_A_IDLE = 6,\n\tOTG_STATE_A_WAIT_VRISE = 7,\n\tOTG_STATE_A_WAIT_BCON = 8,\n\tOTG_STATE_A_HOST = 9,\n\tOTG_STATE_A_SUSPEND = 10,\n\tOTG_STATE_A_PERIPHERAL = 11,\n\tOTG_STATE_A_WAIT_VFALL = 12,\n\tOTG_STATE_A_VBUS_ERR = 13,\n};\n\nenum usb_phy_events {\n\tUSB_EVENT_NONE = 0,\n\tUSB_EVENT_VBUS = 1,\n\tUSB_EVENT_ID = 2,\n\tUSB_EVENT_CHARGER = 3,\n\tUSB_EVENT_ENUMERATED = 4,\n};\n\nenum usb_phy_interface {\n\tUSBPHY_INTERFACE_MODE_UNKNOWN = 0,\n\tUSBPHY_INTERFACE_MODE_UTMI = 1,\n\tUSBPHY_INTERFACE_MODE_UTMIW = 2,\n\tUSBPHY_INTERFACE_MODE_ULPI = 3,\n\tUSBPHY_INTERFACE_MODE_SERIAL = 4,\n\tUSBPHY_INTERFACE_MODE_HSIC = 5,\n};\n\nenum usb_phy_type {\n\tUSB_PHY_TYPE_UNDEFINED = 0,\n\tUSB_PHY_TYPE_USB2 = 1,\n\tUSB_PHY_TYPE_USB3 = 2,\n};\n\nenum usb_port_connect_type {\n\tUSB_PORT_CONNECT_TYPE_UNKNOWN = 0,\n\tUSB_PORT_CONNECT_TYPE_HOT_PLUG = 1,\n\tUSB_PORT_CONNECT_TYPE_HARD_WIRED = 2,\n\tUSB_PORT_NOT_USED = 3,\n};\n\nenum usb_ssp_rate {\n\tUSB_SSP_GEN_UNKNOWN = 0,\n\tUSB_SSP_GEN_2x1 = 1,\n\tUSB_SSP_GEN_1x2 = 2,\n\tUSB_SSP_GEN_2x2 = 3,\n};\n\nenum usb_wireless_status {\n\tUSB_WIRELESS_STATUS_NA = 0,\n\tUSB_WIRELESS_STATUS_DISCONNECTED = 1,\n\tUSB_WIRELESS_STATUS_CONNECTED = 2,\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nenum uts_proc {\n\tUTS_PROC_ARCH = 0,\n\tUTS_PROC_OSTYPE = 1,\n\tUTS_PROC_OSRELEASE = 2,\n\tUTS_PROC_VERSION = 3,\n\tUTS_PROC_HOSTNAME = 4,\n\tUTS_PROC_DOMAINNAME = 5,\n};\n\nenum vas_cop_feat_type {\n\tVAS_GZIP_QOS_FEAT_TYPE = 0,\n\tVAS_GZIP_DEF_FEAT_TYPE = 1,\n\tVAS_MAX_FEAT_TYPE = 2,\n};\n\nenum vas_cop_type {\n\tVAS_COP_TYPE_FAULT = 0,\n\tVAS_COP_TYPE_842 = 1,\n\tVAS_COP_TYPE_842_HIPRI = 2,\n\tVAS_COP_TYPE_GZIP = 3,\n\tVAS_COP_TYPE_GZIP_HIPRI = 4,\n\tVAS_COP_TYPE_FTW = 5,\n\tVAS_COP_TYPE_MAX = 6,\n};\n\nenum vas_dma_type {\n\tVAS_DMA_TYPE_INJECT = 0,\n\tVAS_DMA_TYPE_WRITE = 1,\n};\n\nenum vas_migrate_action {\n\tVAS_SUSPEND = 0,\n\tVAS_RESUME = 1,\n};\n\nenum vas_notify_after_count {\n\tVAS_NOTIFY_AFTER_256 = 0,\n\tVAS_NOTIFY_NONE = 1,\n\tVAS_NOTIFY_AFTER_2 = 2,\n};\n\nenum vas_notify_scope {\n\tVAS_SCOPE_LOCAL = 0,\n\tVAS_SCOPE_GROUP = 1,\n\tVAS_SCOPE_VECTORED_GROUP = 2,\n\tVAS_SCOPE_UNUSED = 3,\n};\n\nenum vasi_aborting_entity {\n\tORCHESTRATOR = 1,\n\tVSP_SOURCE = 2,\n\tPARTITION_FIRMWARE = 3,\n\tPLATFORM_FIRMWARE = 4,\n\tVSP_TARGET = 5,\n\tMIGRATING_PARTITION = 6,\n};\n\nenum vc_ctl_state {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n\tESANSI_first = 12,\n\tESapc = 13,\n\tESpm = 14,\n\tESdcs = 15,\n\tESANSI_last = 15,\n};\n\nenum vc_intensity {\n\tVCI_HALF_BRIGHT = 0,\n\tVCI_NORMAL = 1,\n\tVCI_BOLD = 2,\n\tVCI_MASK = 3,\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_ARCHTIMER = 1,\n\tVDSO_CLOCKMODE_MAX = 2,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nenum vdso_pages {\n\tVDSO_TIME_PAGE_OFFSET = 0,\n\tVDSO_TIMENS_PAGE_OFFSET = 1,\n\tVDSO_RNG_PAGE_OFFSET = 2,\n\tVDSO_ARCH_PAGES_START = 3,\n\tVDSO_ARCH_PAGES_END = 3,\n\tVDSO_NR_PAGES = 4,\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nenum vesa_blank_mode {\n\tVESA_NO_BLANKING = 0,\n\tVESA_VSYNC_SUSPEND = 1,\n\tVESA_HSYNC_SUSPEND = 2,\n\tVESA_POWERDOWN = 3,\n\tVESA_BLANK_MAX = 3,\n};\n\nenum vhost_task_flags {\n\tVHOST_TASK_FLAGS_STOP = 0,\n\tVHOST_TASK_FLAGS_KILLED = 1,\n};\n\nenum vio_dev_family {\n\tVDEVICE = 0,\n\tPFO = 1,\n};\n\nenum viosrp_capability_flag {\n\tCLIENT_MIGRATED = 1,\n\tCLIENT_RECONNECT = 2,\n\tCAP_LIST_SUPPORTED = 4,\n\tCAP_LIST_DATA = 8,\n};\n\nenum viosrp_capability_support {\n\tSERVER_DOES_NOT_SUPPORTS_CAP = 0,\n\tSERVER_SUPPORTS_CAP = 1,\n\tSERVER_CAP_DATA = 2,\n};\n\nenum viosrp_capability_type {\n\tMIGRATION_CAPABILITIES = 1,\n\tRESERVATION_CAPABILITIES = 2,\n};\n\nenum viosrp_crq_formats {\n\tVIOSRP_SRP_FORMAT = 1,\n\tVIOSRP_MAD_FORMAT = 2,\n\tVIOSRP_OS400_FORMAT = 3,\n\tVIOSRP_AIX_FORMAT = 4,\n\tVIOSRP_LINUX_FORMAT = 5,\n\tVIOSRP_INLINE_FORMAT = 6,\n};\n\nenum viosrp_crq_headers {\n\tVIOSRP_CRQ_FREE = 0,\n\tVIOSRP_CRQ_CMD_RSP = 128,\n\tVIOSRP_CRQ_INIT_RSP = 192,\n\tVIOSRP_CRQ_XPORT_EVENT = 255,\n};\n\nenum viosrp_crq_init_formats {\n\tVIOSRP_CRQ_INIT = 1,\n\tVIOSRP_CRQ_INIT_COMPLETE = 2,\n};\n\nenum viosrp_crq_status {\n\tVIOSRP_OK = 0,\n\tVIOSRP_NONRECOVERABLE_ERR = 1,\n\tVIOSRP_VIOLATES_MAX_XFER = 2,\n\tVIOSRP_PARTNER_PANIC = 3,\n\tVIOSRP_DEVICE_BUSY = 8,\n\tVIOSRP_ADAPTER_FAIL = 16,\n\tVIOSRP_OK2 = 153,\n};\n\nenum viosrp_mad_status {\n\tVIOSRP_MAD_SUCCESS = 0,\n\tVIOSRP_MAD_NOT_SUPPORTED = 241,\n\tVIOSRP_MAD_FAILED = 247,\n};\n\nenum viosrp_mad_types {\n\tVIOSRP_EMPTY_IU_TYPE = 1,\n\tVIOSRP_ERROR_LOG_TYPE = 2,\n\tVIOSRP_ADAPTER_INFO_TYPE = 3,\n\tVIOSRP_CAPABILITIES_TYPE = 5,\n\tVIOSRP_ENABLE_FAST_FAIL = 8,\n};\n\nenum viosrp_reserve_type {\n\tCLIENT_RESERVE_SCSI_2 = 1,\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum vlan_flags {\n\tVLAN_FLAG_REORDER_HDR = 1,\n\tVLAN_FLAG_GVRP = 2,\n\tVLAN_FLAG_LOOSE_BINDING = 4,\n\tVLAN_FLAG_MVRP = 8,\n\tVLAN_FLAG_BRIDGE_BINDING = 16,\n};\n\nenum vlan_protos {\n\tVLAN_PROTO_8021Q = 0,\n\tVLAN_PROTO_8021AD = 1,\n\tVLAN_PROTO_NUM = 2,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_NORMAL = 4,\n\tPGALLOC_MOVABLE = 5,\n\tPGALLOC_DEVICE = 6,\n\tALLOCSTALL_NORMAL = 7,\n\tALLOCSTALL_MOVABLE = 8,\n\tALLOCSTALL_DEVICE = 9,\n\tPGSCAN_SKIP_NORMAL = 10,\n\tPGSCAN_SKIP_MOVABLE = 11,\n\tPGSCAN_SKIP_DEVICE = 12,\n\tPGFREE = 13,\n\tPGACTIVATE = 14,\n\tPGDEACTIVATE = 15,\n\tPGLAZYFREE = 16,\n\tPGFAULT = 17,\n\tPGMAJFAULT = 18,\n\tPGLAZYFREED = 19,\n\tPGREFILL = 20,\n\tPGREUSE = 21,\n\tPGSTEAL_KSWAPD = 22,\n\tPGSTEAL_DIRECT = 23,\n\tPGSTEAL_KHUGEPAGED = 24,\n\tPGSTEAL_PROACTIVE = 25,\n\tPGSCAN_KSWAPD = 26,\n\tPGSCAN_DIRECT = 27,\n\tPGSCAN_KHUGEPAGED = 28,\n\tPGSCAN_PROACTIVE = 29,\n\tPGSCAN_DIRECT_THROTTLE = 30,\n\tPGSCAN_ANON = 31,\n\tPGSCAN_FILE = 32,\n\tPGSTEAL_ANON = 33,\n\tPGSTEAL_FILE = 34,\n\tPGSCAN_ZONE_RECLAIM_SUCCESS = 35,\n\tPGSCAN_ZONE_RECLAIM_FAILED = 36,\n\tPGINODESTEAL = 37,\n\tSLABS_SCANNED = 38,\n\tKSWAPD_INODESTEAL = 39,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 40,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 41,\n\tPAGEOUTRUN = 42,\n\tPGROTATED = 43,\n\tDROP_PAGECACHE = 44,\n\tDROP_SLAB = 45,\n\tOOM_KILL = 46,\n\tNUMA_PTE_UPDATES = 47,\n\tNUMA_HUGE_PTE_UPDATES = 48,\n\tNUMA_HINT_FAULTS = 49,\n\tNUMA_HINT_FAULTS_LOCAL = 50,\n\tNUMA_PAGE_MIGRATE = 51,\n\tPGMIGRATE_SUCCESS = 52,\n\tPGMIGRATE_FAIL = 53,\n\tTHP_MIGRATION_SUCCESS = 54,\n\tTHP_MIGRATION_FAIL = 55,\n\tTHP_MIGRATION_SPLIT = 56,\n\tCOMPACTMIGRATE_SCANNED = 57,\n\tCOMPACTFREE_SCANNED = 58,\n\tCOMPACTISOLATED = 59,\n\tCOMPACTSTALL = 60,\n\tCOMPACTFAIL = 61,\n\tCOMPACTSUCCESS = 62,\n\tKCOMPACTD_WAKE = 63,\n\tKCOMPACTD_MIGRATE_SCANNED = 64,\n\tKCOMPACTD_FREE_SCANNED = 65,\n\tHTLB_BUDDY_PGALLOC = 66,\n\tHTLB_BUDDY_PGALLOC_FAIL = 67,\n\tCMA_ALLOC_SUCCESS = 68,\n\tCMA_ALLOC_FAIL = 69,\n\tUNEVICTABLE_PGCULLED = 70,\n\tUNEVICTABLE_PGSCANNED = 71,\n\tUNEVICTABLE_PGRESCUED = 72,\n\tUNEVICTABLE_PGMLOCKED = 73,\n\tUNEVICTABLE_PGMUNLOCKED = 74,\n\tUNEVICTABLE_PGCLEARED = 75,\n\tUNEVICTABLE_PGSTRANDED = 76,\n\tTHP_FAULT_ALLOC = 77,\n\tTHP_FAULT_FALLBACK = 78,\n\tTHP_FAULT_FALLBACK_CHARGE = 79,\n\tTHP_COLLAPSE_ALLOC = 80,\n\tTHP_COLLAPSE_ALLOC_FAILED = 81,\n\tTHP_FILE_ALLOC = 82,\n\tTHP_FILE_FALLBACK = 83,\n\tTHP_FILE_FALLBACK_CHARGE = 84,\n\tTHP_FILE_MAPPED = 85,\n\tTHP_SPLIT_PAGE = 86,\n\tTHP_SPLIT_PAGE_FAILED = 87,\n\tTHP_DEFERRED_SPLIT_PAGE = 88,\n\tTHP_UNDERUSED_SPLIT_PAGE = 89,\n\tTHP_SPLIT_PMD = 90,\n\tTHP_SCAN_EXCEED_NONE_PTE = 91,\n\tTHP_SCAN_EXCEED_SWAP_PTE = 92,\n\tTHP_SCAN_EXCEED_SHARED_PTE = 93,\n\tTHP_SPLIT_PUD = 94,\n\tTHP_ZERO_PAGE_ALLOC = 95,\n\tTHP_ZERO_PAGE_ALLOC_FAILED = 96,\n\tTHP_SWPOUT = 97,\n\tTHP_SWPOUT_FALLBACK = 98,\n\tBALLOON_INFLATE = 99,\n\tBALLOON_DEFLATE = 100,\n\tBALLOON_MIGRATE = 101,\n\tSWAP_RA = 102,\n\tSWAP_RA_HIT = 103,\n\tSWPIN_ZERO = 104,\n\tSWPOUT_ZERO = 105,\n\tKSM_SWPIN_COPY = 106,\n\tCOW_KSM = 107,\n\tZSWPIN = 108,\n\tZSWPOUT = 109,\n\tZSWPWB = 110,\n\tKSTACK_1K = 111,\n\tKSTACK_2K = 112,\n\tKSTACK_4K = 113,\n\tKSTACK_8K = 114,\n\tKSTACK_16K = 115,\n\tKSTACK_32K = 116,\n\tNR_VM_EVENT_ITEMS = 117,\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_COMPLETED = 16384,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nenum vm_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_MEMMAP_PAGES = 2,\n\tNR_MEMMAP_BOOT_PAGES = 3,\n\tNR_VM_STAT_ITEMS = 4,\n};\n\nenum vma_merge_state {\n\tVMA_MERGE_START = 0,\n\tVMA_MERGE_ERROR_NOMEM = 1,\n\tVMA_MERGE_NOMERGE = 2,\n\tVMA_MERGE_SUCCESS = 3,\n};\n\nenum vma_operation {\n\tVMA_OP_SPLIT = 0,\n\tVMA_OP_MERGE_UNFAULTED = 1,\n\tVMA_OP_REMAP = 2,\n\tVMA_OP_FORK = 3,\n};\n\nenum vma_resv_mode {\n\tVMA_NEEDS_RESV = 0,\n\tVMA_COMMIT_RESV = 1,\n\tVMA_END_RESV = 2,\n\tVMA_ADD_RESV = 3,\n\tVMA_DEL_RESV = 4,\n};\n\nenum vmpressure_levels {\n\tVMPRESSURE_LOW = 0,\n\tVMPRESSURE_MEDIUM = 1,\n\tVMPRESSURE_CRITICAL = 2,\n\tVMPRESSURE_NUM_LEVELS = 3,\n};\n\nenum vmpressure_modes {\n\tVMPRESSURE_NO_PASSTHROUGH = 0,\n\tVMPRESSURE_HIERARCHY = 1,\n\tVMPRESSURE_LOCAL = 2,\n\tVMPRESSURE_NUM_MODES = 3,\n};\n\nenum vmscan_throttle_state {\n\tVMSCAN_THROTTLE_WRITEBACK = 0,\n\tVMSCAN_THROTTLE_ISOLATED = 1,\n\tVMSCAN_THROTTLE_NOPROGRESS = 2,\n\tVMSCAN_THROTTLE_CONGESTED = 3,\n\tNR_VMSCAN_THROTTLE = 4,\n};\n\nenum vtime_state {\n\tVTIME_INACTIVE = 0,\n\tVTIME_IDLE = 1,\n\tVTIME_SYS = 2,\n\tVTIME_USER = 3,\n\tVTIME_GUEST = 4,\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_FS_FREE_SPACE = 4,\n\tWB_REASON_FORKER_THREAD = 5,\n\tWB_REASON_FOREIGN_FLUSH = 6,\n\tWB_REASON_MAX = 7,\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum why_no_delegation4 {\n\tWND4_NOT_WANTED = 0,\n\tWND4_CONTENTION = 1,\n\tWND4_RESOURCE = 2,\n\tWND4_NOT_SUPP_FTYPE = 3,\n\tWND4_WRITE_DELEG_NOT_SUPP_FTYPE = 4,\n\tWND4_NOT_SUPP_UPGRADE = 5,\n\tWND4_NOT_SUPP_DOWNGRADE = 6,\n\tWND4_CANCELLED = 7,\n\tWND4_IS_DIR = 8,\n};\n\nenum work_bits {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_INACTIVE_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_FLAG_BITS = 4,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PWQ_SHIFT = 8,\n\tWORK_OFFQ_FLAG_SHIFT = 4,\n\tWORK_OFFQ_BH_BIT = 4,\n\tWORK_OFFQ_FLAG_END = 5,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_DISABLE_SHIFT = 5,\n\tWORK_OFFQ_DISABLE_BITS = 16,\n\tWORK_OFFQ_POOL_SHIFT = 21,\n\tWORK_OFFQ_LEFT = 43,\n\tWORK_OFFQ_POOL_BITS = 31,\n};\n\nenum work_cancel_flags {\n\tWORK_CANCEL_DELAYED = 1,\n\tWORK_CANCEL_DISABLE = 2,\n};\n\nenum work_flags {\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_INACTIVE = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n};\n\nenum worker_flags {\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n};\n\nenum worker_pool_flags {\n\tPOOL_BH = 1,\n\tPOOL_MANAGER_ACTIVE = 2,\n\tPOOL_DISASSOCIATED = 4,\n\tPOOL_BH_DRAINING = 8,\n};\n\nenum wq_affn_scope {\n\tWQ_AFFN_DFL = 0,\n\tWQ_AFFN_CPU = 1,\n\tWQ_AFFN_SMT = 2,\n\tWQ_AFFN_CACHE = 3,\n\tWQ_AFFN_NUMA = 4,\n\tWQ_AFFN_SYSTEM = 5,\n\tWQ_AFFN_NR_TYPES = 6,\n};\n\nenum wq_consts {\n\tWQ_MAX_ACTIVE = 2048,\n\tWQ_UNBOUND_MAX_ACTIVE = 2048,\n\tWQ_DFL_ACTIVE = 1024,\n\tWQ_DFL_MIN_ACTIVE = 8,\n};\n\nenum wq_flags {\n\tWQ_BH = 1,\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\tWQ_PERCPU = 256,\n\t__WQ_DESTROYING = 32768,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_BH_ALLOWS = 273,\n};\n\nenum wq_internal_consts {\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 300000,\n\tMAYDAY_INITIAL_TIMEOUT = 10,\n\tMAYDAY_INTERVAL = 100,\n\tCREATE_COOLDOWN = 1000,\n\tRESCUER_BATCH = 16,\n\tRESCUER_NICE_LEVEL = -20,\n\tHIGHPRI_NICE_LEVEL = -20,\n\tWQ_NAME_LEN = 32,\n\tWORKER_ID_LEN = 42,\n};\n\nenum wq_misc_consts {\n\tWORK_NR_COLORS = 16,\n\tWORK_CPU_UNBOUND = 2048,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 32,\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nenum x509_actions {\n\tACT_x509_extract_key_data = 0,\n\tACT_x509_extract_name_segment = 1,\n\tACT_x509_note_OID = 2,\n\tACT_x509_note_issuer = 3,\n\tACT_x509_note_not_after = 4,\n\tACT_x509_note_not_before = 5,\n\tACT_x509_note_params = 6,\n\tACT_x509_note_serial = 7,\n\tACT_x509_note_sig_algo = 8,\n\tACT_x509_note_signature = 9,\n\tACT_x509_note_subject = 10,\n\tACT_x509_note_tbs_certificate = 11,\n\tACT_x509_process_extension = 12,\n\tNR__x509_actions = 13,\n};\n\nenum x509_akid_actions {\n\tACT_x509_akid_note_kid = 0,\n\tACT_x509_akid_note_name = 1,\n\tACT_x509_akid_note_serial = 2,\n\tACT_x509_extract_name_segment___2 = 3,\n\tACT_x509_note_OID___2 = 4,\n\tNR__x509_akid_actions = 5,\n};\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nenum xbtree_key_contig {\n\tXBTREE_KEY_GAP = 0,\n\tXBTREE_KEY_CONTIGUOUS = 1,\n\tXBTREE_KEY_OVERLAP = 2,\n};\n\nenum xbtree_recpacking {\n\tXBTREE_RECPACKING_EMPTY = 0,\n\tXBTREE_RECPACKING_SPARSE = 1,\n\tXBTREE_RECPACKING_FULL = 2,\n};\n\nenum xchk_dirpath_outcome {\n\tXCHK_DIRPATH_SCANNING = 0,\n\tXCHK_DIRPATH_DELETE = 1,\n\tXCHK_DIRPATH_CORRUPT = 2,\n\tXCHK_DIRPATH_LOOP = 3,\n\tXCHK_DIRPATH_STALE = 4,\n\tXCHK_DIRPATH_OK = 5,\n\tXREP_DIRPATH_DELETING = 6,\n\tXREP_DIRPATH_DELETED = 7,\n\tXREP_DIRPATH_ADOPTING = 8,\n\tXREP_DIRPATH_ADOPTED = 9,\n};\n\nenum xchk_health_group {\n\tXHG_NONE = 1,\n\tXHG_FS = 2,\n\tXHG_AG = 3,\n\tXHG_INO = 4,\n\tXHG_RTGROUP = 5,\n};\n\nenum xchk_type {\n\tST_NONE = 1,\n\tST_PERAG = 2,\n\tST_FS = 3,\n\tST_INODE = 4,\n\tST_GENERIC = 5,\n\tST_RTGROUP = 6,\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_buff_flags {\n\tXDP_FLAGS_HAS_FRAGS = 1,\n\tXDP_FLAGS_FRAGS_PF_MEMALLOC = 2,\n\tXDP_FLAGS_FRAGS_UNREADABLE = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\nenum xdp_rss_hash_type {\n\tXDP_RSS_L3_IPV4 = 1,\n\tXDP_RSS_L3_IPV6 = 2,\n\tXDP_RSS_L3_DYNHDR = 4,\n\tXDP_RSS_L4 = 8,\n\tXDP_RSS_L4_TCP = 16,\n\tXDP_RSS_L4_UDP = 32,\n\tXDP_RSS_L4_SCTP = 64,\n\tXDP_RSS_L4_IPSEC = 128,\n\tXDP_RSS_L4_ICMP = 256,\n\tXDP_RSS_TYPE_NONE = 0,\n\tXDP_RSS_TYPE_L2 = 0,\n\tXDP_RSS_TYPE_L3_IPV4 = 1,\n\tXDP_RSS_TYPE_L3_IPV6 = 2,\n\tXDP_RSS_TYPE_L3_IPV4_OPT = 5,\n\tXDP_RSS_TYPE_L3_IPV6_EX = 6,\n\tXDP_RSS_TYPE_L4_ANY = 8,\n\tXDP_RSS_TYPE_L4_IPV4_TCP = 25,\n\tXDP_RSS_TYPE_L4_IPV4_UDP = 41,\n\tXDP_RSS_TYPE_L4_IPV4_SCTP = 73,\n\tXDP_RSS_TYPE_L4_IPV4_IPSEC = 137,\n\tXDP_RSS_TYPE_L4_IPV4_ICMP = 265,\n\tXDP_RSS_TYPE_L4_IPV6_TCP = 26,\n\tXDP_RSS_TYPE_L4_IPV6_UDP = 42,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP = 74,\n\tXDP_RSS_TYPE_L4_IPV6_IPSEC = 138,\n\tXDP_RSS_TYPE_L4_IPV6_ICMP = 266,\n\tXDP_RSS_TYPE_L4_IPV6_TCP_EX = 30,\n\tXDP_RSS_TYPE_L4_IPV6_UDP_EX = 46,\n\tXDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78,\n};\n\nenum xdp_rx_metadata {\n\tXDP_METADATA_KFUNC_RX_TIMESTAMP = 0,\n\tXDP_METADATA_KFUNC_RX_HASH = 1,\n\tXDP_METADATA_KFUNC_RX_VLAN_TAG = 2,\n\tMAX_XDP_METADATA_KFUNC = 3,\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nenum xfrm_ae_ftype_t {\n\tXFRM_AE_UNSPEC = 0,\n\tXFRM_AE_RTHR = 1,\n\tXFRM_AE_RVAL = 2,\n\tXFRM_AE_LVAL = 4,\n\tXFRM_AE_ETHR = 8,\n\tXFRM_AE_CR = 16,\n\tXFRM_AE_CE = 32,\n\tXFRM_AE_CU = 64,\n\t__XFRM_AE_MAX = 65,\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\tXFRMA_MTIMER_THRESH = 32,\n\tXFRMA_SA_DIR = 33,\n\tXFRMA_NAT_KEEPALIVE_INTERVAL = 34,\n\tXFRMA_SA_PCPU = 35,\n\tXFRMA_IPTFS_DROP_TIME = 36,\n\tXFRMA_IPTFS_REORDER_WINDOW = 37,\n\tXFRMA_IPTFS_DONT_FRAG = 38,\n\tXFRMA_IPTFS_INIT_DELAY = 39,\n\tXFRMA_IPTFS_MAX_QSIZE = 40,\n\tXFRMA_IPTFS_PKT_SIZE = 41,\n\t__XFRMA_MAX = 42,\n};\n\nenum xfrm_nlgroups {\n\tXFRMNLGRP_NONE = 0,\n\tXFRMNLGRP_ACQUIRE = 1,\n\tXFRMNLGRP_EXPIRE = 2,\n\tXFRMNLGRP_SA = 3,\n\tXFRMNLGRP_POLICY = 4,\n\tXFRMNLGRP_AEVENTS = 5,\n\tXFRMNLGRP_REPORT = 6,\n\tXFRMNLGRP_MIGRATE = 7,\n\tXFRMNLGRP_MAPPING = 8,\n\t__XFRMNLGRP_MAX = 9,\n};\n\nenum xfrm_pol_inexact_candidate_type {\n\tXFRM_POL_CAND_BOTH = 0,\n\tXFRM_POL_CAND_SADDR = 1,\n\tXFRM_POL_CAND_DADDR = 2,\n\tXFRM_POL_CAND_ANY = 3,\n\tXFRM_POL_CAND_MAX = 4,\n};\n\nenum xfrm_replay_mode {\n\tXFRM_REPLAY_MODE_LEGACY = 0,\n\tXFRM_REPLAY_MODE_BMP = 1,\n\tXFRM_REPLAY_MODE_ESN = 2,\n};\n\nenum xfrm_sa_dir {\n\tXFRM_SA_DIR_IN = 1,\n\tXFRM_SA_DIR_OUT = 2,\n};\n\nenum xfs_ag_resv_type {\n\tXFS_AG_RESV_NONE = 0,\n\tXFS_AG_RESV_AGFL = 1,\n\tXFS_AG_RESV_METADATA = 2,\n\tXFS_AG_RESV_RMAPBT = 3,\n\tXFS_AG_RESV_IGNORE = 4,\n\tXFS_AG_RESV_METAFILE = 5,\n};\n\nenum xfs_attr_defer_op {\n\tXFS_ATTR_DEFER_SET = 0,\n\tXFS_ATTR_DEFER_REMOVE = 1,\n\tXFS_ATTR_DEFER_REPLACE = 2,\n};\n\nenum xfs_attr_update {\n\tXFS_ATTRUPDATE_REMOVE = 0,\n\tXFS_ATTRUPDATE_UPSERT = 1,\n\tXFS_ATTRUPDATE_CREATE = 2,\n\tXFS_ATTRUPDATE_REPLACE = 3,\n};\n\nenum xfs_blft {\n\tXFS_BLFT_UNKNOWN_BUF = 0,\n\tXFS_BLFT_UDQUOT_BUF = 1,\n\tXFS_BLFT_PDQUOT_BUF = 2,\n\tXFS_BLFT_GDQUOT_BUF = 3,\n\tXFS_BLFT_BTREE_BUF = 4,\n\tXFS_BLFT_AGF_BUF = 5,\n\tXFS_BLFT_AGFL_BUF = 6,\n\tXFS_BLFT_AGI_BUF = 7,\n\tXFS_BLFT_DINO_BUF = 8,\n\tXFS_BLFT_SYMLINK_BUF = 9,\n\tXFS_BLFT_DIR_BLOCK_BUF = 10,\n\tXFS_BLFT_DIR_DATA_BUF = 11,\n\tXFS_BLFT_DIR_FREE_BUF = 12,\n\tXFS_BLFT_DIR_LEAF1_BUF = 13,\n\tXFS_BLFT_DIR_LEAFN_BUF = 14,\n\tXFS_BLFT_DA_NODE_BUF = 15,\n\tXFS_BLFT_ATTR_LEAF_BUF = 16,\n\tXFS_BLFT_ATTR_RMT_BUF = 17,\n\tXFS_BLFT_SB_BUF = 18,\n\tXFS_BLFT_RTBITMAP_BUF = 19,\n\tXFS_BLFT_RTSUMMARY_BUF = 20,\n\tXFS_BLFT_MAX_BUF = 32,\n};\n\nenum xfs_bmap_intent_type {\n\tXFS_BMAP_MAP = 1,\n\tXFS_BMAP_UNMAP = 2,\n};\n\nenum xfs_btree_type {\n\tXFS_BTREE_TYPE_AG = 0,\n\tXFS_BTREE_TYPE_INODE = 1,\n\tXFS_BTREE_TYPE_MEM = 2,\n};\n\nenum xfs_dacmp {\n\tXFS_CMP_DIFFERENT = 0,\n\tXFS_CMP_EXACT = 1,\n\tXFS_CMP_CASE = 2,\n};\n\nenum xfs_dax_mode {\n\tXFS_DAX_INODE = 0,\n\tXFS_DAX_ALWAYS = 1,\n\tXFS_DAX_NEVER = 2,\n};\n\nenum xfs_delattr_state {\n\tXFS_DAS_UNINIT = 0,\n\tXFS_DAS_SF_ADD = 1,\n\tXFS_DAS_SF_REMOVE = 2,\n\tXFS_DAS_LEAF_ADD = 3,\n\tXFS_DAS_LEAF_REMOVE = 4,\n\tXFS_DAS_NODE_ADD = 5,\n\tXFS_DAS_NODE_REMOVE = 6,\n\tXFS_DAS_LEAF_SET_RMT = 7,\n\tXFS_DAS_LEAF_ALLOC_RMT = 8,\n\tXFS_DAS_LEAF_REPLACE = 9,\n\tXFS_DAS_LEAF_REMOVE_OLD = 10,\n\tXFS_DAS_LEAF_REMOVE_RMT = 11,\n\tXFS_DAS_LEAF_REMOVE_ATTR = 12,\n\tXFS_DAS_NODE_SET_RMT = 13,\n\tXFS_DAS_NODE_ALLOC_RMT = 14,\n\tXFS_DAS_NODE_REPLACE = 15,\n\tXFS_DAS_NODE_REMOVE_OLD = 16,\n\tXFS_DAS_NODE_REMOVE_RMT = 17,\n\tXFS_DAS_NODE_REMOVE_ATTR = 18,\n\tXFS_DAS_DONE = 19,\n};\n\nenum xfs_device {\n\tXFS_DEV_DATA = 1,\n\tXFS_DEV_LOG = 2,\n\tXFS_DEV_RT = 3,\n};\n\nenum xfs_dinode_fmt {\n\tXFS_DINODE_FMT_DEV = 0,\n\tXFS_DINODE_FMT_LOCAL = 1,\n\tXFS_DINODE_FMT_EXTENTS = 2,\n\tXFS_DINODE_FMT_BTREE = 3,\n\tXFS_DINODE_FMT_UUID = 4,\n\tXFS_DINODE_FMT_META_BTREE = 5,\n};\n\nenum xfs_dir2_fmt {\n\tXFS_DIR2_FMT_SF = 0,\n\tXFS_DIR2_FMT_BLOCK = 1,\n\tXFS_DIR2_FMT_LEAF = 2,\n\tXFS_DIR2_FMT_NODE = 3,\n\tXFS_DIR2_FMT_ERROR = 4,\n};\n\nenum xfs_experimental_feat {\n\tXFS_EXPERIMENTAL_SHRINK = 0,\n\tXFS_EXPERIMENTAL_LARP = 1,\n\tXFS_EXPERIMENTAL_ZONED = 2,\n\tXFS_EXPERIMENTAL_MAX = 3,\n};\n\nenum xfs_free_counter {\n\tXC_FREE_BLOCKS = 0,\n\tXC_FREE_RTEXTENTS = 1,\n\tXC_FREE_RTAVAILABLE = 2,\n\tXC_FREE_NR = 3,\n};\n\nenum xfs_fstrm_alloc {\n\tXFS_PICK_USERDATA = 1,\n\tXFS_PICK_LOWSPACE = 2,\n};\n\nenum xfs_group_type {\n\tXG_TYPE_AG = 0,\n\tXG_TYPE_RTG = 1,\n\tXG_TYPE_MAX = 2,\n} __attribute__((mode(byte)));\n\nenum xfs_healthmon_domain {\n\tXFS_HEALTHMON_MOUNT = 0,\n\tXFS_HEALTHMON_FS = 1,\n\tXFS_HEALTHMON_AG = 2,\n\tXFS_HEALTHMON_INODE = 3,\n\tXFS_HEALTHMON_RTGROUP = 4,\n\tXFS_HEALTHMON_DATADEV = 5,\n\tXFS_HEALTHMON_RTDEV = 6,\n\tXFS_HEALTHMON_LOGDEV = 7,\n\tXFS_HEALTHMON_FILERANGE = 8,\n};\n\nenum xfs_healthmon_type {\n\tXFS_HEALTHMON_RUNNING = 0,\n\tXFS_HEALTHMON_LOST = 1,\n\tXFS_HEALTHMON_UNMOUNT = 2,\n\tXFS_HEALTHMON_SHUTDOWN = 3,\n\tXFS_HEALTHMON_SICK = 4,\n\tXFS_HEALTHMON_CORRUPT = 5,\n\tXFS_HEALTHMON_HEALTHY = 6,\n\tXFS_HEALTHMON_MEDIA_ERROR = 7,\n\tXFS_HEALTHMON_BUFREAD = 8,\n\tXFS_HEALTHMON_BUFWRITE = 9,\n\tXFS_HEALTHMON_DIOREAD = 10,\n\tXFS_HEALTHMON_DIOWRITE = 11,\n\tXFS_HEALTHMON_DATALOST = 12,\n};\n\nenum xfs_icwalk_goal {\n\tXFS_ICWALK_BLOCKGC = 1,\n\tXFS_ICWALK_RECLAIM = 0,\n};\n\nenum xfs_metafile_type {\n\tXFS_METAFILE_UNKNOWN = 0,\n\tXFS_METAFILE_DIR = 1,\n\tXFS_METAFILE_USRQUOTA = 2,\n\tXFS_METAFILE_GRPQUOTA = 3,\n\tXFS_METAFILE_PRJQUOTA = 4,\n\tXFS_METAFILE_RTBITMAP = 5,\n\tXFS_METAFILE_RTSUMMARY = 6,\n\tXFS_METAFILE_RTRMAP = 7,\n\tXFS_METAFILE_RTREFCOUNT = 8,\n\tXFS_METAFILE_MAX = 9,\n} __attribute__((mode(byte)));\n\nenum xfs_refc_adjust_op {\n\tXFS_REFCOUNT_ADJUST_INCREASE = 1,\n\tXFS_REFCOUNT_ADJUST_DECREASE = -1,\n\tXFS_REFCOUNT_ADJUST_COW_ALLOC = 0,\n\tXFS_REFCOUNT_ADJUST_COW_FREE = -1,\n};\n\nenum xfs_refc_domain {\n\tXFS_REFC_DOMAIN_SHARED = 0,\n\tXFS_REFC_DOMAIN_COW = 1,\n};\n\nenum xfs_refcount_intent_type {\n\tXFS_REFCOUNT_INCREASE = 1,\n\tXFS_REFCOUNT_DECREASE = 2,\n\tXFS_REFCOUNT_ALLOC_COW = 3,\n\tXFS_REFCOUNT_FREE_COW = 4,\n};\n\nenum xfs_rmap_intent_type {\n\tXFS_RMAP_MAP = 0,\n\tXFS_RMAP_MAP_SHARED = 1,\n\tXFS_RMAP_UNMAP = 2,\n\tXFS_RMAP_UNMAP_SHARED = 3,\n\tXFS_RMAP_CONVERT = 4,\n\tXFS_RMAP_CONVERT_SHARED = 5,\n\tXFS_RMAP_ALLOC = 6,\n\tXFS_RMAP_FREE = 7,\n};\n\nenum xfs_rtg_inodes {\n\tXFS_RTGI_BITMAP = 0,\n\tXFS_RTGI_SUMMARY = 1,\n\tXFS_RTGI_RMAP = 2,\n\tXFS_RTGI_REFCOUNT = 3,\n\tXFS_RTGI_MAX = 4,\n};\n\nenum xlog_iclog_state {\n\tXLOG_STATE_ACTIVE = 0,\n\tXLOG_STATE_WANT_SYNC = 1,\n\tXLOG_STATE_SYNCING = 2,\n\tXLOG_STATE_DONE_SYNC = 3,\n\tXLOG_STATE_CALLBACK = 4,\n\tXLOG_STATE_DIRTY = 5,\n};\n\nenum xlog_recover_reorder {\n\tXLOG_REORDER_BUFFER_LIST = 0,\n\tXLOG_REORDER_ITEM_LIST = 1,\n\tXLOG_REORDER_INODE_BUFFER_LIST = 2,\n\tXLOG_REORDER_CANCEL_LIST = 3,\n};\n\nenum xprt_transports {\n\tXPRT_TRANSPORT_UDP = 17,\n\tXPRT_TRANSPORT_TCP = 6,\n\tXPRT_TRANSPORT_BC_TCP = -2147483642,\n\tXPRT_TRANSPORT_RDMA = 256,\n\tXPRT_TRANSPORT_BC_RDMA = -2147483392,\n\tXPRT_TRANSPORT_LOCAL = 257,\n\tXPRT_TRANSPORT_TCP_TLS = 258,\n};\n\nenum xprt_xid_rb_cmp {\n\tXID_RB_EQUAL = 0,\n\tXID_RB_LEFT = 1,\n\tXID_RB_RIGHT = 2,\n};\n\nenum xprtsec_policies {\n\tRPC_XPRTSEC_NONE = 0,\n\tRPC_XPRTSEC_TLS_ANON = 1,\n\tRPC_XPRTSEC_TLS_X509 = 2,\n};\n\nenum xps_map_type {\n\tXPS_CPUS = 0,\n\tXPS_RXQS = 1,\n\tXPS_MAPS_MAX = 2,\n};\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nenum zcrx_ctrl_op {\n\tZCRX_CTRL_FLUSH_RQ = 0,\n\tZCRX_CTRL_EXPORT = 1,\n\t__ZCRX_CTRL_LAST = 2,\n};\n\nenum zcrx_features {\n\tZCRX_FEATURE_RX_PAGE_SIZE = 1,\n};\n\nenum zcrx_reg_flags {\n\tZCRX_REG_IMPORT = 1,\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n\tZONE_RECLAIM_ACTIVE = 1,\n\tZONE_BELOW_HIGH = 2,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_FREE_PAGES_BLOCKS = 1,\n\tNR_ZONE_LRU_BASE = 2,\n\tNR_ZONE_INACTIVE_ANON = 2,\n\tNR_ZONE_ACTIVE_ANON = 3,\n\tNR_ZONE_INACTIVE_FILE = 4,\n\tNR_ZONE_ACTIVE_FILE = 5,\n\tNR_ZONE_UNEVICTABLE = 6,\n\tNR_ZONE_WRITE_PENDING = 7,\n\tNR_MLOCK = 8,\n\tNR_ZSPAGES = 9,\n\tNR_FREE_CMA_PAGES = 10,\n\tNR_VM_ZONE_STAT_ITEMS = 11,\n};\n\nenum zone_type {\n\tZONE_NORMAL = 0,\n\tZONE_MOVABLE = 1,\n\tZONE_DEVICE = 2,\n\t__MAX_NR_ZONES = 3,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tWMARK_PROMO = 3,\n\tNR_WMARK = 4,\n};\n\nenum zswap_init_type {\n\tZSWAP_UNINIT = 0,\n\tZSWAP_INIT_SUCCEED = 1,\n\tZSWAP_INIT_FAILED = 2,\n};\n\ntypedef _Bool bool;\n\ntypedef __int128 unsigned __u128;\n\ntypedef __u128 u128;\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\ntypedef char *va_list;\n\ntypedef double elf_fpreg_t;\n\ntypedef elf_fpreg_t elf_fpregset_t[33];\n\ntypedef int __kernel_clockid_t;\n\ntypedef int __kernel_daddr_t;\n\ntypedef int __kernel_ipc_pid_t;\n\ntypedef int __kernel_key_t;\n\ntypedef int __kernel_mqd_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef int __kernel_rwf_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __s32;\n\ntypedef int class_get_unused_fd_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef __s32 s32;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_int_t;\n\ntypedef s32 compat_long_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_ssize_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef int cydp_t;\n\ntypedef s32 dma_cookie_t;\n\ntypedef int ext4_grpblk_t;\n\ntypedef int folio_walk_flags_t;\n\ntypedef int fpb_t;\n\ntypedef int fpi_t;\n\ntypedef s32 int32_t;\n\ntypedef int32_t key_serial_t;\n\ntypedef __kernel_key_t key_t;\n\ntypedef int mhp_t;\n\ntypedef int mm_id_mapcount_t;\n\ntypedef int mpi_size_t;\n\ntypedef __kernel_mqd_t mqd_t;\n\ntypedef s32 old_time32_t;\n\ntypedef int pci_power_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef int rmap_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef __s32 sctp_assoc_t;\n\ntypedef int suspend_state_t;\n\ntypedef __kernel_timer_t timer_t;\n\ntypedef int vma_flag_t;\n\ntypedef long int __kernel_long_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_long_t __kernel_ptrdiff_t;\n\ntypedef __kernel_long_t __kernel_ssize_t;\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_clock_t clock_t;\n\ntypedef long int intptr_t;\n\ntypedef long int mpi_limb_signed_t;\n\ntypedef __kernel_off_t off_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef long long int __s64;\n\ntypedef __s64 Elf64_Sxword;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef __s64 s64;\n\ntypedef s64 int64_t;\n\ntypedef s64 ktime_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef long long int qsize_t;\n\ntypedef __s64 time64_t;\n\ntypedef loff_t xfblob_cookie;\n\ntypedef int64_t xfs_csn_t;\n\ntypedef __s64 xfs_daddr_t;\n\ntypedef __s64 xfs_off_t;\n\ntypedef xfs_off_t xfs_dir2_off_t;\n\ntypedef int64_t xfs_fsize_t;\n\ntypedef int64_t xfs_lsn_t;\n\ntypedef long long unsigned int __u64;\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u64 Elf64_Off;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __u64 u64;\n\ntypedef u64 uint64_t;\n\ntypedef uint64_t U64;\n\ntypedef __u64 __addrpair;\n\ntypedef __u64 __be64;\n\ntypedef long long unsigned int __kernel_uoff_t;\n\ntypedef __u64 __le64;\n\ntypedef u64 async_cookie_t;\n\ntypedef __u64 blist_flags_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 clientid4;\n\ntypedef u64 dma_addr_t;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef __be64 fdt64_t;\n\ntypedef u64 gfn_t;\n\ntypedef u64 gpa_t;\n\ntypedef u64 io_req_flags_t;\n\ntypedef long long unsigned int llu;\n\ntypedef u64 netdev_features_t;\n\ntypedef u64 pci_bus_addr_t;\n\ntypedef u64 phys_addr_t;\n\ntypedef uint64_t ppc_cpu_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef u64 sci_t;\n\ntypedef u64 sector_t;\n\ntypedef __u64 timeu64_t;\n\ntypedef __kernel_uoff_t uoff_t;\n\ntypedef u64 upf_t;\n\ntypedef uint64_t vli_type;\n\ntypedef uint64_t xfarray_idx_t;\n\ntypedef uint64_t xfbno_t;\n\ntypedef __be64 xfs_bmbt_ptr_t;\n\ntypedef uint64_t xfs_bmbt_rec_base_t;\n\ntypedef uint64_t xfs_extnum_t;\n\ntypedef uint64_t xfs_filblks_t;\n\ntypedef uint64_t xfs_fileoff_t;\n\ntypedef uint64_t xfs_fsblock_t;\n\ntypedef long long unsigned int xfs_ino_t;\n\ntypedef uint64_t xfs_inofree_t;\n\ntypedef uint64_t xfs_log_timestamp_t;\n\ntypedef uint64_t xfs_qcnt_t;\n\ntypedef uint64_t xfs_rfsblock_t;\n\ntypedef uint64_t xfs_rtblock_t;\n\ntypedef uint64_t xfs_rtbxlen_t;\n\ntypedef __be64 xfs_rtrefcount_ptr_t;\n\ntypedef __be64 xfs_rtrmap_ptr_t;\n\ntypedef uint64_t xfs_rtxnum_t;\n\ntypedef __be64 xfs_timestamp_t;\n\ntypedef uint64_t xfs_ufsize_t;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef __kernel_ulong_t __kernel_size_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef size_t BitContainerType;\n\ntypedef long unsigned int mpi_limb_t;\n\ntypedef mpi_limb_t UWtype;\n\ntypedef __kernel_ulong_t __kernel_ino_t;\n\ntypedef long unsigned int __kernel_old_dev_t;\n\ntypedef __kernel_ulong_t aio_context_t;\n\ntypedef long unsigned int cycles_t;\n\ntypedef long unsigned int dax_entry_t;\n\ntypedef long unsigned int elf_greg_t64;\n\ntypedef elf_greg_t64 elf_gregset_t64[48];\n\ntypedef elf_gregset_t64 elf_gregset_t;\n\ntypedef long unsigned int gva_t;\n\ntypedef __kernel_ulong_t ino_t;\n\ntypedef long unsigned int irq_hw_number_t;\n\ntypedef long unsigned int kernel_ulong_t;\n\ntypedef long unsigned int kimage_entry_t;\n\ntypedef long unsigned int mm_context_id_t;\n\ntypedef mpi_limb_t *mpi_ptr_t;\n\ntypedef long unsigned int netmem_ref;\n\ntypedef long unsigned int old_sigset_t;\n\ntypedef long unsigned int perf_trace_t[1024];\n\ntypedef long unsigned int pte_basic_t;\n\ntypedef long unsigned int pte_marker;\n\ntypedef long unsigned int uLong;\n\ntypedef long unsigned int u_long;\n\ntypedef long unsigned int uintptr_t;\n\ntypedef long unsigned int ulg;\n\ntypedef long unsigned int ulong;\n\ntypedef uintptr_t uptrval;\n\ntypedef long unsigned int vm_flags_t;\n\ntypedef short int __s16;\n\ntypedef __s16 s16;\n\ntypedef s16 int16_t;\n\ntypedef int16_t S16;\n\ntypedef short unsigned int __u16;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u16 Elf64_Half;\n\ntypedef short unsigned int ush;\n\ntypedef ush Pos;\n\ntypedef __u16 u16;\n\ntypedef u16 uint16_t;\n\ntypedef uint16_t U16;\n\ntypedef __u16 __be16;\n\ntypedef __u16 __hc16;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef short unsigned int __kernel_sa_family_t;\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef __u16 __le16;\n\ntypedef __u16 __sum16;\n\ntypedef __u16 __virtio16;\n\ntypedef u16 access_mask_t;\n\ntypedef __u16 bitmap_counter_t;\n\ntypedef u16 blk_short_t;\n\ntypedef __u16 comp_t;\n\ntypedef __kernel_gid16_t gid16_t;\n\ntypedef short unsigned int pci_bus_flags_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\ntypedef __u16 port_id;\n\ntypedef __kernel_sa_family_t sa_family_t;\n\ntypedef u16 u_int16_t;\n\ntypedef short unsigned int u_short;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __u16 uio_meta_flags_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef short unsigned int ushort;\n\ntypedef u16 wchar_t;\n\ntypedef uint16_t xfs_dir2_data_off_t;\n\ntypedef signed char __s8;\n\ntypedef __s8 s8;\n\ntypedef s8 int8_t;\n\ntypedef signed char unative_t[16];\n\ntypedef unsigned char __u8;\n\ntypedef __u8 u8;\n\ntypedef u8 uint8_t;\n\ntypedef uint8_t BYTE;\n\ntypedef unsigned char Byte;\n\ntypedef uint8_t U8;\n\ntypedef u8 blk_status_t;\n\ntypedef unsigned char cc_t;\n\ntypedef unsigned char cisdata_t;\n\ntypedef u8 deny_masks_t;\n\ntypedef u8 dscp_t;\n\ntypedef __u8 dvd_challenge[10];\n\ntypedef __u8 dvd_key[5];\n\ntypedef u8 rmap_age_t;\n\ntypedef unsigned char u_char;\n\ntypedef u8 u_int8_t;\n\ntypedef unsigned char uch;\n\ntypedef uint8_t xfs_dqtype_t;\n\ntypedef unsigned int __u32;\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u32 Elf32_Off;\n\ntypedef __u32 Elf32_Word;\n\ntypedef __u32 Elf64_Word;\n\ntypedef unsigned int FSE_DTable;\n\ntypedef __u32 u32;\n\ntypedef u32 uint32_t;\n\ntypedef uint32_t U32;\n\ntypedef U32 HUF_DTable;\n\ntypedef unsigned int IPos;\n\ntypedef unsigned int OM_uint32;\n\ntypedef unsigned int UHWtype;\n\ntypedef __u32 __be32;\n\ntypedef u32 __compat_uid32_t;\n\ntypedef __u32 __hc32;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef unsigned int __kernel_gid_t;\n\ntypedef unsigned int __kernel_mode_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef __u32 __le32;\n\ntypedef unsigned int __poll_t;\n\ntypedef __u32 __portpair;\n\ntypedef __u32 __wsum;\n\ntypedef unsigned int acr_flags_t;\n\ntypedef unsigned int blk_features_t;\n\ntypedef unsigned int blk_flags_t;\n\ntypedef unsigned int blk_insert_t;\n\ntypedef unsigned int blk_mode_t;\n\ntypedef __u32 blk_mq_req_flags_t;\n\ntypedef __u32 blk_opf_t;\n\ntypedef unsigned int blk_qc_t;\n\ntypedef __be32 cell_t;\n\ntypedef u32 compat_caddr_t;\n\ntypedef u32 compat_size_t;\n\ntypedef u32 compat_uint_t;\n\ntypedef u32 compat_ulong_t;\n\ntypedef u32 compat_uptr_t;\n\ntypedef u32 depot_flags_t;\n\ntypedef u32 depot_stack_handle_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef u32 errseq_t;\n\ntypedef unsigned int ext4_group_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef __be32 fdt32_t;\n\ntypedef unsigned int fgf_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef unsigned int fop_flags_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef u32 ihandle;\n\ntypedef unsigned int ioasid_t;\n\ntypedef unsigned int iov_iter_extraction_t;\n\ntypedef unsigned int isolate_mode_t;\n\ntypedef unsigned int kasan_vmalloc_flags_t;\n\ntypedef uint32_t key_perm_t;\n\ntypedef u32 kprobe_opcode_t;\n\ntypedef unsigned int mm_id_t;\n\ntypedef __kernel_mode_t mode_t;\n\ntypedef u32 nlink_t;\n\ntypedef u32 note_buf_t[134];\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef unsigned int pci_ers_result_t;\n\ntypedef unsigned int pgtbl_mod_mask;\n\ntypedef u32 phandle;\n\ntypedef unsigned int pipe_index_t;\n\ntypedef uint32_t prid_t;\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef u32 prom_arg_t;\n\ntypedef U32 rankValCol_t[13];\n\ntypedef __u32 req_flags_t;\n\ntypedef u32 rpc_authflavor_t;\n\ntypedef __be32 rpc_fraghdr;\n\ntypedef __be32 rtas_arg_t;\n\ntypedef unsigned int sk_buff_data_t;\n\ntypedef unsigned int slab_flags_t;\n\ntypedef unsigned int speed_t;\n\ntypedef unsigned int t_key;\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned int tid_t;\n\ntypedef unsigned int uInt;\n\ntypedef unsigned int u_int;\n\ntypedef u32 u_int32_t;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef unsigned int uint;\n\ntypedef u32 unicode_t;\n\ntypedef u32 uprobe_opcode_t;\n\ntypedef unsigned int upstat_t;\n\ntypedef u32 usb_port_location_t;\n\ntypedef unsigned int vm_fault_t;\n\ntypedef unsigned int xa_mark_t;\n\ntypedef u32 xdp_features_t;\n\ntypedef uint32_t xfs_aextnum_t;\n\ntypedef uint32_t xfs_agblock_t;\n\ntypedef uint32_t xfs_agino_t;\n\ntypedef uint32_t xfs_agnumber_t;\n\ntypedef unsigned int xfs_buf_flags_t;\n\ntypedef uint32_t xfs_dablk_t;\n\ntypedef uint32_t xfs_dahash_t;\n\ntypedef __u32 xfs_dev_t;\n\ntypedef uint xfs_dir2_data_aoff_t;\n\ntypedef uint32_t xfs_dir2_dataptr_t;\n\ntypedef uint32_t xfs_dir2_db_t;\n\ntypedef uint32_t xfs_dqid_t;\n\ntypedef uint32_t xfs_extlen_t;\n\ntypedef __u32 xfs_nlink_t;\n\ntypedef uint32_t xfs_rgblock_t;\n\ntypedef uint32_t xfs_rgnumber_t;\n\ntypedef uint32_t xfs_rtxlen_t;\n\ntypedef uint32_t xlog_tid_t;\n\ntypedef unsigned int zap_flags_t;\n\ntypedef struct {\n\tBitContainerType bitContainer;\n\tunsigned int bitsConsumed;\n\tconst char *ptr;\n\tconst char *start;\n\tconst char *limitPtr;\n} BIT_DStream_t;\n\ntypedef struct {\n\tBYTE maxTableLog;\n\tBYTE tableType;\n\tBYTE tableLog;\n\tBYTE reserved;\n} DTableDesc;\n\ntypedef struct {\n\tsize_t state;\n\tconst void *table;\n} FSE_DState_t;\n\ntypedef struct {\n\tU16 tableLog;\n\tU16 fastMode;\n} FSE_DTableHeader;\n\ntypedef struct {\n\tshort int ncount[256];\n} FSE_DecompressWksp;\n\ntypedef struct {\n\tshort unsigned int newState;\n\tunsigned char symbol;\n\tunsigned char nbBits;\n} FSE_decode_t;\n\ntypedef struct {\n\tBYTE nbBits;\n\tBYTE byte;\n} HUF_DEltX1;\n\ntypedef struct {\n\tU16 sequence;\n\tBYTE nbBits;\n\tBYTE length;\n} HUF_DEltX2;\n\ntypedef struct {\n\tconst BYTE *ip[4];\n\tBYTE *op[4];\n\tU64 bits[4];\n\tconst void *dt;\n\tconst BYTE *ilowest;\n\tBYTE *oend;\n\tconst BYTE *iend[4];\n} HUF_DecompressFastArgs;\n\ntypedef struct {\n\tU32 rankVal[13];\n\tU32 rankStart[13];\n\tU32 statsWksp[219];\n\tBYTE symbols[256];\n\tBYTE huffWeight[256];\n} HUF_ReadDTableX1_Workspace;\n\ntypedef struct {\n\tBYTE symbol;\n} sortedSymbol_t;\n\ntypedef struct {\n\tU32 rankVal[156];\n\tU32 rankStats[13];\n\tU32 rankStart0[15];\n\tsortedSymbol_t sortedSymbol[256];\n\tBYTE weightList[256];\n\tU32 calleeWksp[219];\n} HUF_ReadDTableX2_Workspace;\n\nstruct buffer_head;\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\nstruct folio;\n\ntypedef struct {\n\tstruct folio *v;\n} Sector;\n\nstruct ZSTD_DDict_s;\n\ntypedef struct ZSTD_DDict_s ZSTD_DDict;\n\ntypedef struct {\n\tconst ZSTD_DDict **ddictPtrTable;\n\tsize_t ddictPtrTableSize;\n\tsize_t ddictPtrCount;\n} ZSTD_DDictHashSet;\n\ntypedef struct {\n\tlong long unsigned int frameContentSize;\n\tlong long unsigned int windowSize;\n\tunsigned int blockSizeMax;\n\tZSTD_FrameType_e frameType;\n\tunsigned int headerSize;\n\tunsigned int dictID;\n\tunsigned int checksumFlag;\n\tunsigned int _reserved1;\n\tunsigned int _reserved2;\n} ZSTD_FrameHeader;\n\ntypedef struct {\n\tunsigned int longOffsetShare;\n\tunsigned int maxNbAdditionalBits;\n} ZSTD_OffsetInfo;\n\ntypedef struct {\n\tsize_t error;\n\tint lowerBound;\n\tint upperBound;\n} ZSTD_bounds;\n\ntypedef void * (*ZSTD_allocFunction)(void *, size_t);\n\ntypedef void (*ZSTD_freeFunction)(void *, void *);\n\ntypedef struct {\n\tZSTD_allocFunction customAlloc;\n\tZSTD_freeFunction customFree;\n\tvoid *opaque;\n} ZSTD_customMem;\n\ntypedef struct {\n\tU16 nextState;\n\tBYTE nbAdditionalBits;\n\tBYTE nbBits;\n\tU32 baseValue;\n} ZSTD_seqSymbol;\n\ntypedef struct {\n\tZSTD_seqSymbol LLTable[513];\n\tZSTD_seqSymbol OFTable[257];\n\tZSTD_seqSymbol MLTable[513];\n\tHUF_DTable hufTable[4097];\n\tU32 rep[3];\n\tU32 workspace[157];\n} ZSTD_entropyDTables_t;\n\ntypedef struct {\n\tsize_t nbBlocks;\n\tsize_t compressedSize;\n\tlong long unsigned int decompressedBound;\n} ZSTD_frameSizeInfo;\n\ntypedef struct {\n\tsize_t state;\n\tconst ZSTD_seqSymbol *table;\n} ZSTD_fseState;\n\ntypedef struct {\n\tU32 fastMode;\n\tU32 tableLog;\n} ZSTD_seqSymbol_header;\n\ntypedef struct {\n\tlong unsigned int fds_bits[16];\n} __kernel_fd_set;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef struct {\n\t__u32 u[4];\n} __vector128;\n\ntypedef struct {\n\tU32 tableTime;\n\tU32 decode256Time;\n} algo_time_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\ntypedef atomic64_t atomic_long_t;\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\ntypedef struct {\n\tblockType_e blockType;\n\tU32 lastBlock;\n\tU32 origSize;\n} blockProperties_t;\n\ntypedef struct {\n\tunion {\n\t\tvoid *kernel;\n\t\tvoid *user;\n\t};\n\tbool is_kernel: 1;\n} sockptr_t;\n\ntypedef sockptr_t bpfptr_t;\n\nstruct permanent_flags_t {\n\t__be16 tag;\n\tu8 disable;\n\tu8 ownership;\n\tu8 deactivated;\n\tu8 readPubek;\n\tu8 disableOwnerClear;\n\tu8 allowMaintenance;\n\tu8 physicalPresenceLifetimeLock;\n\tu8 physicalPresenceHWEnable;\n\tu8 physicalPresenceCMDEnable;\n\tu8 CEKPUsed;\n\tu8 TPMpost;\n\tu8 TPMpostLock;\n\tu8 FIPS;\n\tu8 operator;\n\tu8 enableRevokeEK;\n\tu8 nvLocked;\n\tu8 readSRKPub;\n\tu8 tpmEstablished;\n\tu8 maintenanceDone;\n\tu8 disableFullDALogicInfo;\n};\n\nstruct stclear_flags_t {\n\t__be16 tag;\n\tu8 deactivated;\n\tu8 disableForceClear;\n\tu8 physicalPresence;\n\tu8 physicalPresenceLock;\n\tu8 bGlobalLock;\n} __attribute__((packed));\n\nstruct tpm1_version {\n\tu8 major;\n\tu8 minor;\n\tu8 rev_major;\n\tu8 rev_minor;\n};\n\nstruct tpm1_version2 {\n\t__be16 tag;\n\tstruct tpm1_version version;\n};\n\nstruct timeout_t {\n\t__be32 a;\n\t__be32 b;\n\t__be32 c;\n\t__be32 d;\n};\n\nstruct duration_t {\n\t__be32 tpm_short;\n\t__be32 tpm_medium;\n\t__be32 tpm_long;\n};\n\ntypedef union {\n\tstruct permanent_flags_t perm_flags;\n\tstruct stclear_flags_t stclear_flags;\n\t__u8 owned;\n\t__be32 num_pcrs;\n\tstruct tpm1_version version1;\n\tstruct tpm1_version2 version2;\n\t__be32 manufacturer_id;\n\tstruct timeout_t timeout;\n\tstruct duration_t duration;\n} cap_t;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\nstruct pin_cookie {};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n\tunsigned int clock_update_flags;\n};\n\nstruct task_struct;\n\nstruct rq;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class___task_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_console_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_cpus_read_lock_t;\n\nstruct raw_spinlock;\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\traw_spinlock_t *lock2;\n} class_double_raw_spinlock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq *lock2;\n} class_double_rq_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_irq_t;\n\nstruct irq_desc;\n\ntypedef struct {\n\tstruct irq_desc *lock;\n\tlong unsigned int flags;\n\tbool bus;\n} class_irqdesc_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n\tlong unsigned int flags;\n} class_irqsave_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_jump_label_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_mount_writer_t;\n\nstruct device;\n\ntypedef struct {\n\tstruct device *lock;\n} class_msi_descs_lock_t;\n\nstruct mutex;\n\ntypedef struct {\n\tstruct mutex *lock;\n} class_mutex_t;\n\ntypedef class_mutex_t class_mutex_intr_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_excl_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_namespace_shared_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_locked_reader_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_ns_tree_writer_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_pagefault_t;\n\nstruct perf_cpu_context;\n\nstruct perf_event_context;\n\ntypedef struct {\n\tstruct perf_cpu_context *cpuctx;\n\tstruct perf_event_context *ctx;\n} class_perf_ctx_lock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_notrace_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_preempt_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_irq_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n\tlong unsigned int flags;\n} class_raw_spinlock_irqsave_t;\n\ntypedef struct {\n\traw_spinlock_t *lock;\n} class_raw_spinlock_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_t;\n\ntypedef struct {\n\tvoid *lock;\n} class_rcu_tasks_trace_t;\n\nstruct rwlock;\n\ntypedef struct rwlock rwlock_t;\n\ntypedef struct {\n\trwlock_t *lock;\n\tlong unsigned int flags;\n} class_read_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_read_lock_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irq_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_irqsave_t;\n\ntypedef struct {\n\tstruct rq *lock;\n\tstruct rq_flags rf;\n} class_rq_lock_t;\n\nstruct rw_semaphore;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_read_t;\n\ntypedef struct {\n\tstruct rw_semaphore *lock;\n} class_rwsem_write_t;\n\nstruct spinlock;\n\ntypedef struct spinlock spinlock_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_bh_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_irq_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n} class_spinlock_irqsave_t;\n\ntypedef struct {\n\tspinlock_t *lock;\n} class_spinlock_t;\n\nstruct srcu_struct;\n\nstruct srcu_ctr;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tstruct srcu_ctr *scp;\n} class_srcu_fast_notrace_t;\n\ntypedef struct {\n\tstruct srcu_struct *lock;\n\tint idx;\n} class_srcu_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n} class_task_lock_t;\n\ntypedef struct {\n\tstruct task_struct *lock;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n} class_task_rq_lock_t;\n\nstruct tty_struct;\n\ntypedef struct {\n\tstruct tty_struct *lock;\n} class_tty_port_tty_t;\n\nstruct uart_port;\n\ntypedef struct {\n\tstruct uart_port *lock;\n\tlong unsigned int flags;\n} class_uart_port_lock_irqsave_t;\n\ntypedef struct {\n\trwlock_t *lock;\n} class_write_lock_irq_t;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef struct {\n\t__be16 disc_information_length;\n\t__u8 disc_status: 2;\n\t__u8 border_status: 2;\n\t__u8 erasable: 1;\n\t__u8 reserved1: 3;\n\t__u8 n_first_track;\n\t__u8 n_sessions_lsb;\n\t__u8 first_track_lsb;\n\t__u8 last_track_lsb;\n\t__u8 mrw_status: 2;\n\t__u8 dbit: 1;\n\t__u8 reserved2: 2;\n\t__u8 uru: 1;\n\t__u8 dbc_v: 1;\n\t__u8 did_v: 1;\n\t__u8 disc_type;\n\t__u8 n_sessions_msb;\n\t__u8 first_track_msb;\n\t__u8 last_track_msb;\n\t__u32 disc_id;\n\t__u32 lead_in;\n\t__u32 lead_out;\n\t__u8 disc_bar_code[8];\n\t__u8 reserved3;\n\t__u8 n_opc;\n} disc_information;\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\nstruct dvd_lu_send_agid {\n\t__u8 type;\n\tunsigned int agid: 2;\n};\n\nstruct dvd_host_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_send_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key key;\n};\n\nstruct dvd_lu_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_lu_send_title_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key title_key;\n\tint lba;\n\tunsigned int cpm: 1;\n\tunsigned int cp_sec: 1;\n\tunsigned int cgms: 2;\n};\n\nstruct dvd_lu_send_asf {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tunsigned int asf: 1;\n};\n\nstruct dvd_host_send_rpcstate {\n\t__u8 type;\n\t__u8 pdrc;\n};\n\nstruct dvd_lu_send_rpcstate {\n\t__u8 type: 2;\n\t__u8 vra: 3;\n\t__u8 ucca: 3;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_lu_send_agid lsa;\n\tstruct dvd_host_send_challenge hsc;\n\tstruct dvd_send_key lsk;\n\tstruct dvd_lu_send_challenge lsc;\n\tstruct dvd_send_key hsk;\n\tstruct dvd_lu_send_title_key lstk;\n\tstruct dvd_lu_send_asf lsasf;\n\tstruct dvd_host_send_rpcstate hrpcs;\n\tstruct dvd_lu_send_rpcstate lrpcs;\n} dvd_authinfo;\n\nstruct dvd_layer {\n\t__u8 book_version: 4;\n\t__u8 book_type: 4;\n\t__u8 min_rate: 4;\n\t__u8 disc_size: 4;\n\t__u8 layer_type: 4;\n\t__u8 track_path: 1;\n\t__u8 nlayers: 2;\n\tchar: 1;\n\t__u8 track_density: 4;\n\t__u8 linear_density: 4;\n\t__u8 bca: 1;\n\t__u32 start_sector;\n\t__u32 end_sector;\n\t__u32 end_sector_l0;\n};\n\nstruct dvd_physical {\n\t__u8 type;\n\t__u8 layer_num;\n\tstruct dvd_layer layer[4];\n};\n\nstruct dvd_copyright {\n\t__u8 type;\n\t__u8 layer_num;\n\t__u8 cpst;\n\t__u8 rmi;\n};\n\nstruct dvd_disckey {\n\t__u8 type;\n\tunsigned int agid: 2;\n\t__u8 value[2048];\n};\n\nstruct dvd_bca {\n\t__u8 type;\n\tint len;\n\t__u8 value[188];\n};\n\nstruct dvd_manufact {\n\t__u8 type;\n\t__u8 layer_num;\n\tint len;\n\t__u8 value[2048];\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_physical physical;\n\tstruct dvd_copyright copyright;\n\tstruct dvd_disckey disckey;\n\tstruct dvd_bca bca;\n\tstruct dvd_manufact manufact;\n} dvd_struct;\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\tefi_guid_t signature_owner;\n\tu8 signature_data[0];\n} efi_signature_data_t;\n\ntypedef struct {\n\tefi_guid_t signature_type;\n\tu32 signature_list_size;\n\tu32 signature_header_size;\n\tu32 signature_size;\n\tu8 signature_header[0];\n} efi_signature_list_t;\n\ntypedef __vector128 elf_vrreg_t;\n\ntypedef struct {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n} ext4_acl_entry;\n\ntypedef struct {\n\t__le32 a_version;\n} ext4_acl_header;\n\ntypedef __kernel_fd_set fd_set;\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\ntypedef struct {\n\tatomic64_t refcnt;\n} file_ref_t;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tlong unsigned int v;\n} freeptr_t;\n\ntypedef struct {\n\tlong unsigned int addr;\n} func_desc_t;\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\ntypedef struct {\n\tunsigned int __softirq_pending;\n\tunsigned int timer_irqs_event;\n\tunsigned int broadcast_irqs_event;\n\tunsigned int timer_irqs_others;\n\tunsigned int pmu_irqs;\n\tunsigned int mce_exceptions;\n\tunsigned int spurious_irqs;\n\tunsigned int sreset_irqs;\n\tunsigned int soft_nmi_irqs;\n\tunsigned int doorbell_irqs;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n} irq_cpustat_t;\n\ntypedef struct {\n\tu64 val;\n} kernel_cap_t;\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\ntypedef struct {\n\tlong int v;\n} local_t;\n\ntypedef struct {\n\tlocal_t a;\n} local64_t;\n\ntypedef struct {\n\tlong unsigned int f;\n} memdesc_flags_t;\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\nstruct hash_mm_context;\n\ntypedef struct {\n\tunion {\n\t\tmm_context_id_t id;\n\t\tmm_context_id_t extended_id[8];\n\t};\n\tatomic_t active_cpus;\n\tatomic_t copros;\n\tatomic_t vas_windows;\n\tstruct hash_mm_context *hash_context;\n\tvoid *vdso;\n\tvoid *pte_frag;\n\tvoid *pmd_frag;\n\tstruct list_head iommu_group_mem_list;\n\tu32 pkey_allocation_map;\n\ts16 execute_only_pkey;\n} mm_context_t;\n\ntypedef struct {\n\tlong unsigned int __mm_flags[1];\n} mm_flags_t;\n\ntypedef struct {} netdevice_tracker;\n\ntypedef struct {} netns_tracker;\n\ntypedef struct {\n\tchar data[8];\n} nfs4_verifier;\n\ntypedef struct {\n\tlong unsigned int bits[4];\n} nodemask_t;\n\ntypedef struct {\n\t__be64 pgd;\n} pgd_t;\n\ntypedef struct {\n\tpgd_t pgd;\n} p4d_t;\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\ntypedef struct {\n\tu32 token;\n} papr_sysparm_t;\n\ntypedef struct {\n\tlong unsigned int pgprot;\n} pgprot_t;\n\ntypedef struct {\n\t__be64 pte;\n} pte_t;\n\ntypedef pte_t *pgtable_t;\n\ntypedef struct {\n\t__be64 pmd;\n} pmd_t;\n\nstruct net;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\ntypedef struct {\n\tu32 val;\n\tu32 suffix;\n} ppc_inst_t;\n\ntypedef struct {\n\t__be64 pud;\n} pud_t;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tatomic_t refcnt;\n} rcuref_t;\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\ntypedef struct {\n\tpte_t pte;\n\tlong unsigned int hidx;\n} real_pte_t;\n\ntypedef struct {\n\tu16 reg;\n\tu32 val;\n} reg_val;\n\ntypedef union {\n} release_pages_arg;\n\ntypedef struct {\n\t__u16 report_key_length;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 ucca: 3;\n\t__u8 vra: 3;\n\t__u8 type_code: 2;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n\t__u8 reserved3;\n} rpc_state_t;\n\ntypedef struct {\n\tconst enum rtas_function_index index;\n} rtas_fn_handle_t;\n\ntypedef struct {\n\tBIT_DStream_t DStream;\n\tZSTD_fseState stateLL;\n\tZSTD_fseState stateOffb;\n\tZSTD_fseState stateML;\n\tsize_t prevOffset[3];\n} seqState_t;\n\ntypedef struct {\n\tsize_t litLength;\n\tsize_t matchLength;\n\tsize_t offset;\n} seq_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef struct {\n\tseqcount_t seqcount;\n} seqcount_latch_t;\n\ntypedef struct {\n\tlong unsigned int sig[1];\n} sigset_t;\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\nstruct qspinlock {\n\tunion {\n\t\tu32 val;\n\t\tstruct {\n\t\t\tu16 locked;\n\t\t\tu8 reserved[2];\n\t\t};\n\t};\n};\n\ntypedef struct qspinlock arch_spinlock_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\ntypedef swp_entry_t softleaf_t;\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\tu32 high;\n\tu32 low;\n} tg3_stat64_t;\n\ntypedef struct {\n\t__be16 track_information_length;\n\t__u8 track_lsb;\n\t__u8 session_lsb;\n\t__u8 reserved1;\n\t__u8 track_mode: 4;\n\t__u8 copy: 1;\n\t__u8 damage: 1;\n\t__u8 reserved2: 2;\n\t__u8 data_mode: 4;\n\t__u8 fp: 1;\n\t__u8 packet: 1;\n\t__u8 blank: 1;\n\t__u8 rt: 1;\n\t__u8 nwa_v: 1;\n\t__u8 lra_v: 1;\n\t__u8 reserved3: 6;\n\t__be32 track_start;\n\t__be32 next_writable;\n\t__be32 free_blocks;\n\t__be32 fixed_packet_size;\n\t__be32 track_size;\n\t__be32 last_rec_address;\n} track_information;\n\ntypedef struct {\n\tint data;\n\tint audio;\n\tint cdi;\n\tint xa;\n\tlong int error;\n} tracktype;\n\ntypedef struct {\n\tlocal64_t v;\n} u64_stats_t;\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\ntypedef __vector128 vector128;\n\ntypedef struct {\n\tgid_t val;\n} vfsgid_t;\n\ntypedef struct {\n\tuid_t val;\n} vfsuid_t;\n\ntypedef struct {\n\tlong unsigned int __vma_flags[1];\n} vma_flags_t;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\ntypedef ZSTD_customMem zstd_custom_mem;\n\ntypedef ZSTD_FrameHeader zstd_frame_header;\n\nstruct OpalHMIEvent {\n\tuint8_t version;\n\tuint8_t severity;\n\tuint8_t type;\n\tuint8_t disposition;\n\tuint8_t reserved_1[4];\n\t__be64 hmer;\n\t__be64 tfmr;\n\tunion {\n\t\tstruct {\n\t\t\tuint8_t xstop_type;\n\t\t\tuint8_t reserved_1[3];\n\t\t\t__be32 xstop_reason;\n\t\t\tunion {\n\t\t\t\t__be32 pir;\n\t\t\t\t__be32 chip_id;\n\t\t\t} u;\n\t\t} xstop_error;\n\t} u;\n};\n\nstruct OpalHmiEvtNode {\n\tstruct list_head list;\n\tstruct OpalHMIEvent hmi_evt;\n};\n\nstruct OpalIoP7IOCBiErrorData {\n\t__be64 biLdcp0;\n\t__be64 biLdcp1;\n\t__be64 biLdcp2;\n\t__be64 biFenceStatus;\n\tuint8_t biDownbound;\n};\n\nstruct OpalIoP7IOCCiErrorData {\n\t__be64 ciPortStatus;\n\t__be64 ciPortLdcp;\n\tuint8_t ciPort;\n};\n\nstruct OpalIoP7IOCRgcErrorData {\n\t__be64 rgcStatus;\n\t__be64 rgcLdcp;\n};\n\nstruct OpalIoP7IOCErrorData {\n\t__be16 type;\n\t__be64 gemXfir;\n\t__be64 gemRfir;\n\t__be64 gemRirqfir;\n\t__be64 gemMask;\n\t__be64 gemRwof;\n\t__be64 lemFir;\n\t__be64 lemErrMask;\n\t__be64 lemAction0;\n\t__be64 lemAction1;\n\t__be64 lemWof;\n\tunion {\n\t\tstruct OpalIoP7IOCRgcErrorData rgc;\n\t\tstruct OpalIoP7IOCBiErrorData bi;\n\t\tstruct OpalIoP7IOCCiErrorData ci;\n\t};\n};\n\nstruct OpalIoPhbErrorCommon {\n\t__be32 version;\n\t__be32 ioType;\n\t__be32 len;\n};\n\nstruct OpalIoP7IOCPhbErrorData {\n\tstruct OpalIoPhbErrorCommon common;\n\t__be32 brdgCtl;\n\t__be32 portStatusReg;\n\t__be32 rootCmplxStatus;\n\t__be32 busAgentStatus;\n\t__be32 deviceStatus;\n\t__be32 slotStatus;\n\t__be32 linkStatus;\n\t__be32 devCmdStatus;\n\t__be32 devSecStatus;\n\t__be32 rootErrorStatus;\n\t__be32 uncorrErrorStatus;\n\t__be32 corrErrorStatus;\n\t__be32 tlpHdr1;\n\t__be32 tlpHdr2;\n\t__be32 tlpHdr3;\n\t__be32 tlpHdr4;\n\t__be32 sourceId;\n\t__be32 rsv3;\n\t__be64 errorClass;\n\t__be64 correlator;\n\t__be64 p7iocPlssr;\n\t__be64 p7iocCsr;\n\t__be64 lemFir;\n\t__be64 lemErrorMask;\n\t__be64 lemWOF;\n\t__be64 phbErrorStatus;\n\t__be64 phbFirstErrorStatus;\n\t__be64 phbErrorLog0;\n\t__be64 phbErrorLog1;\n\t__be64 mmioErrorStatus;\n\t__be64 mmioFirstErrorStatus;\n\t__be64 mmioErrorLog0;\n\t__be64 mmioErrorLog1;\n\t__be64 dma0ErrorStatus;\n\t__be64 dma0FirstErrorStatus;\n\t__be64 dma0ErrorLog0;\n\t__be64 dma0ErrorLog1;\n\t__be64 dma1ErrorStatus;\n\t__be64 dma1FirstErrorStatus;\n\t__be64 dma1ErrorLog0;\n\t__be64 dma1ErrorLog1;\n\t__be64 pestA[128];\n\t__be64 pestB[128];\n};\n\nstruct OpalIoPhb3ErrorData {\n\tstruct OpalIoPhbErrorCommon common;\n\t__be32 brdgCtl;\n\t__be32 portStatusReg;\n\t__be32 rootCmplxStatus;\n\t__be32 busAgentStatus;\n\t__be32 deviceStatus;\n\t__be32 slotStatus;\n\t__be32 linkStatus;\n\t__be32 devCmdStatus;\n\t__be32 devSecStatus;\n\t__be32 rootErrorStatus;\n\t__be32 uncorrErrorStatus;\n\t__be32 corrErrorStatus;\n\t__be32 tlpHdr1;\n\t__be32 tlpHdr2;\n\t__be32 tlpHdr3;\n\t__be32 tlpHdr4;\n\t__be32 sourceId;\n\t__be32 rsv3;\n\t__be64 errorClass;\n\t__be64 correlator;\n\t__be64 nFir;\n\t__be64 nFirMask;\n\t__be64 nFirWOF;\n\t__be64 phbPlssr;\n\t__be64 phbCsr;\n\t__be64 lemFir;\n\t__be64 lemErrorMask;\n\t__be64 lemWOF;\n\t__be64 phbErrorStatus;\n\t__be64 phbFirstErrorStatus;\n\t__be64 phbErrorLog0;\n\t__be64 phbErrorLog1;\n\t__be64 mmioErrorStatus;\n\t__be64 mmioFirstErrorStatus;\n\t__be64 mmioErrorLog0;\n\t__be64 mmioErrorLog1;\n\t__be64 dma0ErrorStatus;\n\t__be64 dma0FirstErrorStatus;\n\t__be64 dma0ErrorLog0;\n\t__be64 dma0ErrorLog1;\n\t__be64 dma1ErrorStatus;\n\t__be64 dma1FirstErrorStatus;\n\t__be64 dma1ErrorLog0;\n\t__be64 dma1ErrorLog1;\n\t__be64 pestA[256];\n\t__be64 pestB[256];\n};\n\nstruct OpalIoPhb4ErrorData {\n\tstruct OpalIoPhbErrorCommon common;\n\t__be32 brdgCtl;\n\t__be32 deviceStatus;\n\t__be32 slotStatus;\n\t__be32 linkStatus;\n\t__be32 devCmdStatus;\n\t__be32 devSecStatus;\n\t__be32 rootErrorStatus;\n\t__be32 uncorrErrorStatus;\n\t__be32 corrErrorStatus;\n\t__be32 tlpHdr1;\n\t__be32 tlpHdr2;\n\t__be32 tlpHdr3;\n\t__be32 tlpHdr4;\n\t__be32 sourceId;\n\t__be64 nFir;\n\t__be64 nFirMask;\n\t__be64 nFirWOF;\n\t__be64 phbPlssr;\n\t__be64 phbCsr;\n\t__be64 lemFir;\n\t__be64 lemErrorMask;\n\t__be64 lemWOF;\n\t__be64 phbErrorStatus;\n\t__be64 phbFirstErrorStatus;\n\t__be64 phbErrorLog0;\n\t__be64 phbErrorLog1;\n\t__be64 phbTxeErrorStatus;\n\t__be64 phbTxeFirstErrorStatus;\n\t__be64 phbTxeErrorLog0;\n\t__be64 phbTxeErrorLog1;\n\t__be64 phbRxeArbErrorStatus;\n\t__be64 phbRxeArbFirstErrorStatus;\n\t__be64 phbRxeArbErrorLog0;\n\t__be64 phbRxeArbErrorLog1;\n\t__be64 phbRxeMrgErrorStatus;\n\t__be64 phbRxeMrgFirstErrorStatus;\n\t__be64 phbRxeMrgErrorLog0;\n\t__be64 phbRxeMrgErrorLog1;\n\t__be64 phbRxeTceErrorStatus;\n\t__be64 phbRxeTceFirstErrorStatus;\n\t__be64 phbRxeTceErrorLog0;\n\t__be64 phbRxeTceErrorLog1;\n\t__be64 phbPblErrorStatus;\n\t__be64 phbPblFirstErrorStatus;\n\t__be64 phbPblErrorLog0;\n\t__be64 phbPblErrorLog1;\n\t__be64 phbPcieDlpErrorLog1;\n\t__be64 phbPcieDlpErrorLog2;\n\t__be64 phbPcieDlpErrorStatus;\n\t__be64 phbRegbErrorStatus;\n\t__be64 phbRegbFirstErrorStatus;\n\t__be64 phbRegbErrorLog0;\n\t__be64 phbRegbErrorLog1;\n\t__be64 pestA[512];\n\t__be64 pestB[512];\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct sk_buff;\n\nstruct sk_buff_list {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n};\n\nstruct sk_buff_head {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t};\n\t\tstruct sk_buff_list list;\n\t};\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct u64_stats_sync {};\n\nstruct gnet_stats_basic_sync {\n\tu64_stats_t bytes;\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct llist_node;\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\nstruct lock_class_key {};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct netdev_queue;\n\nstruct net_rate_estimator;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint pad;\n\trefcount_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_read_mostly[0];\n\tstruct sk_buff_head gso_skb;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\t__u8 __cacheline_group_end__Qdisc_read_mostly[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__Qdisc_write[0];\n\tstruct qdisc_skb_head q;\n\tlong unsigned int state;\n\tstruct gnet_stats_basic_sync bstats;\n\tbool running;\n\tstruct gnet_stats_queue qstats;\n\tstruct sk_buff *to_free;\n\t__u8 __cacheline_group_end__Qdisc_write[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t defer_count;\n\tstruct llist_head defer_list;\n\tspinlock_t seqlock;\n\tstruct callback_head rcu;\n\tnetdevice_tracker dev_tracker;\n\tstruct lock_class_key root_lock_key;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong int privdata[0];\n};\n\nstruct Qdisc_class_common {\n\tu32 classid;\n\tunsigned int filter_cnt;\n\tstruct hlist_node hnode;\n};\n\nstruct hlist_head;\n\nstruct Qdisc_class_hash {\n\tstruct hlist_head *hash;\n\tunsigned int hashsize;\n\tunsigned int hashmask;\n\tunsigned int hashelems;\n};\n\nstruct tcmsg;\n\nstruct netlink_ext_ack;\n\nstruct nlattr;\n\nstruct qdisc_walker;\n\nstruct tcf_block;\n\nstruct gnet_dump;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct module;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tvoid (*change_real_num_tx)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct RR_CL_s {\n\t__u8 location[8];\n};\n\nstruct RR_NM_s {\n\t__u8 flags;\n\tchar name[0];\n};\n\nstruct RR_PL_s {\n\t__u8 location[8];\n};\n\nstruct RR_PN_s {\n\t__u8 dev_high[8];\n\t__u8 dev_low[8];\n};\n\nstruct RR_PX_s {\n\t__u8 mode[8];\n\t__u8 n_links[8];\n\t__u8 uid[8];\n\t__u8 gid[8];\n};\n\nstruct RR_RR_s {\n\t__u8 flags[1];\n};\n\nstruct SL_component {\n\t__u8 flags;\n\t__u8 len;\n\t__u8 text[0];\n};\n\nstruct RR_SL_s {\n\t__u8 flags;\n\tstruct SL_component link;\n};\n\nstruct RR_TF_s {\n\t__u8 flags;\n\t__u8 data[0];\n};\n\nstruct RR_ZF_s {\n\t__u8 algorithm[2];\n\t__u8 parms[2];\n\t__u8 real_size[8];\n};\n\nstruct SU_CE_s {\n\t__u8 extent[8];\n\t__u8 offset[8];\n\t__u8 size[8];\n};\n\nstruct SU_ER_s {\n\t__u8 len_id;\n\t__u8 len_des;\n\t__u8 len_src;\n\t__u8 ext_ver;\n\t__u8 data[0];\n};\n\nstruct SU_SP_s {\n\t__u8 magic[2];\n\t__u8 skip;\n};\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\traw_spinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n\tvoid *magic;\n};\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct lockdep_map {};\n\nstruct srcu_data;\n\nstruct srcu_usage;\n\nstruct srcu_struct {\n\tstruct srcu_ctr *srcu_ctrp;\n\tstruct srcu_data *sda;\n\tu8 srcu_reader_flavor;\n\tstruct lockdep_map dep_map;\n\tstruct srcu_usage *srcu_sup;\n};\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct blk_mq_ops;\n\nstruct blk_mq_tags;\n\nstruct blk_mq_tag_set {\n\tconst struct blk_mq_ops *ops;\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct blk_mq_tags *shared_tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n\tstruct srcu_struct *srcu;\n\tstruct srcu_struct tags_srcu;\n\tstruct rw_semaphore update_nr_hwq_lock;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tconst struct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head defer_sync;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tktime_t expires;\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tbool can_wakeup: 1;\n\tbool async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool work_in_progress;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tbool smart_suspend: 1;\n\tbool must_resume: 1;\n\tbool may_skip_resume: 1;\n\tbool out_band_wakeup: 1;\n\tbool strict_midlayer: 1;\n\tstruct hrtimer suspend_timer;\n\tu64 timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tbool idle_notification: 1;\n\tbool request_pending: 1;\n\tbool deferred_resume: 1;\n\tbool needs_force_resume: 1;\n\tbool runtime_auto: 1;\n\tbool ignore_children: 1;\n\tbool no_callbacks: 1;\n\tbool irq_safe: 1;\n\tbool use_autosuspend: 1;\n\tbool timer_autosuspends: 1;\n\tbool memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tenum rpm_status last_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n\tbool detach_power_off: 1;\n};\n\nstruct irq_domain;\n\nstruct msi_device_data;\n\nstruct dev_msi_info {\n\tstruct irq_domain *domain;\n\tstruct msi_device_data *data;\n};\n\nstruct iommu_table;\n\nstruct pci_dn;\n\nstruct eeh_dev;\n\nstruct dev_archdata {\n\tdma_addr_t dma_offset;\n\tstruct iommu_table *iommu_table_base;\n\tstruct pci_dn *pci_data;\n\tstruct eeh_dev *edev;\n};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct dma_map_ops;\n\nstruct bus_dma_region;\n\nstruct device_dma_parameters;\n\nstruct dma_coherent_mem;\n\nstruct io_tlb_mem;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device_physical_location;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tconst struct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct dev_msi_info msi;\n\tconst struct dma_map_ops *dma_ops;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tconst struct bus_dma_region *dma_range_map;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct dma_coherent_mem *dma_mem;\n\tstruct io_tlb_mem *dma_io_tlb_mem;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tint numa_node;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tconst struct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tstruct device_physical_location *physical_location;\n\tenum device_removable removable;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n\tbool can_match: 1;\n\tbool dma_ops_bypass: 1;\n\tbool dma_skip_sync: 1;\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct workqueue_struct;\n\nstruct scsi_device;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_abort_list;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tconst struct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct kref tagset_refcnt;\n\tstruct completion tagset_freed;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tunsigned int nr_reserved_cmds;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int opt_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_maps;\n\tunsigned int active_mode: 2;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tstruct scsi_device *pseudo_sdev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tint rpm_autosuspend_delay;\n\tlong unsigned int hostdata[0];\n};\n\nstruct xxh64_state {\n\tuint64_t total_len;\n\tuint64_t v1;\n\tuint64_t v2;\n\tuint64_t v3;\n\tuint64_t v4;\n\tuint64_t mem64[4];\n\tuint32_t memsize;\n};\n\nstruct ZSTD_outBuffer_s {\n\tvoid *dst;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_outBuffer_s ZSTD_outBuffer;\n\nstruct ZSTD_DCtx_s {\n\tconst ZSTD_seqSymbol *LLTptr;\n\tconst ZSTD_seqSymbol *MLTptr;\n\tconst ZSTD_seqSymbol *OFTptr;\n\tconst HUF_DTable *HUFptr;\n\tZSTD_entropyDTables_t entropy;\n\tU32 workspace[640];\n\tconst void *previousDstEnd;\n\tconst void *prefixStart;\n\tconst void *virtualStart;\n\tconst void *dictEnd;\n\tsize_t expected;\n\tZSTD_FrameHeader fParams;\n\tU64 processedCSize;\n\tU64 decodedSize;\n\tblockType_e bType;\n\tZSTD_dStage stage;\n\tU32 litEntropy;\n\tU32 fseEntropy;\n\tstruct xxh64_state xxhState;\n\tsize_t headerSize;\n\tZSTD_format_e format;\n\tZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;\n\tU32 validateChecksum;\n\tconst BYTE *litPtr;\n\tZSTD_customMem customMem;\n\tsize_t litSize;\n\tsize_t rleSize;\n\tsize_t staticSize;\n\tint isFrameDecompression;\n\tZSTD_DDict *ddictLocal;\n\tconst ZSTD_DDict *ddict;\n\tU32 dictID;\n\tint ddictIsCold;\n\tZSTD_dictUses_e dictUses;\n\tZSTD_DDictHashSet *ddictSet;\n\tZSTD_refMultipleDDicts_e refMultipleDDicts;\n\tint disableHufAsm;\n\tint maxBlockSizeParam;\n\tZSTD_dStreamStage streamStage;\n\tchar *inBuff;\n\tsize_t inBuffSize;\n\tsize_t inPos;\n\tsize_t maxWindowSize;\n\tchar *outBuff;\n\tsize_t outBuffSize;\n\tsize_t outStart;\n\tsize_t outEnd;\n\tsize_t lhSize;\n\tU32 hostageByte;\n\tint noForwardProgress;\n\tZSTD_bufferMode_e outBufferMode;\n\tZSTD_outBuffer expectedOutBuffer;\n\tBYTE *litBuffer;\n\tconst BYTE *litBufferEnd;\n\tZSTD_litLocation_e litBufferLocation;\n\tBYTE litExtraBuffer[65568];\n\tBYTE headerBuffer[18];\n\tsize_t oversizedDuration;\n};\n\ntypedef struct ZSTD_DCtx_s ZSTD_DCtx;\n\ntypedef ZSTD_DCtx ZSTD_DStream;\n\ntypedef ZSTD_DCtx zstd_dctx;\n\ntypedef ZSTD_DStream zstd_dstream;\n\nstruct ZSTD_DDict_s {\n\tvoid *dictBuffer;\n\tconst void *dictContent;\n\tsize_t dictSize;\n\tZSTD_entropyDTables_t entropy;\n\tU32 dictID;\n\tU32 entropyPresent;\n\tZSTD_customMem cMem;\n};\n\ntypedef ZSTD_DDict zstd_ddict;\n\nstruct ZSTD_inBuffer_s {\n\tconst void *src;\n\tsize_t size;\n\tsize_t pos;\n};\n\ntypedef struct ZSTD_inBuffer_s ZSTD_inBuffer;\n\ntypedef ZSTD_inBuffer zstd_in_buffer;\n\ntypedef ZSTD_outBuffer zstd_out_buffer;\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct user_pt_regs {\n\tlong unsigned int gpr[32];\n\tlong unsigned int nip;\n\tlong unsigned int msr;\n\tlong unsigned int orig_gpr3;\n\tlong unsigned int ctr;\n\tlong unsigned int link;\n\tlong unsigned int xer;\n\tlong unsigned int ccr;\n\tlong unsigned int softe;\n\tlong unsigned int trap;\n\tlong unsigned int dar;\n\tlong unsigned int dsisr;\n\tlong unsigned int result;\n};\n\nstruct pt_regs {\n\tunion {\n\t\tstruct user_pt_regs user_regs;\n\t\tstruct {\n\t\t\tlong unsigned int gpr[32];\n\t\t\tlong unsigned int nip;\n\t\t\tlong unsigned int msr;\n\t\t\tlong unsigned int orig_gpr3;\n\t\t\tlong unsigned int ctr;\n\t\t\tlong unsigned int link;\n\t\t\tlong unsigned int xer;\n\t\t\tlong unsigned int ccr;\n\t\t\tlong unsigned int softe;\n\t\t\tlong unsigned int trap;\n\t\t\tunion {\n\t\t\t\tlong unsigned int dar;\n\t\t\t\tlong unsigned int dear;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tlong unsigned int dsisr;\n\t\t\t\tlong unsigned int esr;\n\t\t\t};\n\t\t\tlong unsigned int result;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int ppr;\n\t\t\tlong unsigned int exit_result;\n\t\t\tunion {\n\t\t\t\tlong unsigned int kuap;\n\t\t\t\tlong unsigned int amr;\n\t\t\t};\n\t\t\tlong unsigned int iamr;\n\t\t};\n\t\tlong unsigned int __pad[4];\n\t};\n};\n\nstruct __arch_ftrace_regs {\n\tstruct pt_regs regs;\n};\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n\tu16 src;\n\tu16 dst;\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tstruct __call_single_node node;\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct idr;\n\nstruct __class_idr {\n\tstruct idr *idr;\n\tint id;\n};\n\ntypedef struct __class_idr class_idr_alloc_t;\n\nstruct cpumask;\n\nstruct __cmp_key {\n\tconst struct cpumask *cpus;\n\tstruct cpumask ***masks;\n\tint node;\n\tint cpu;\n\tint w;\n};\n\nstruct __fat_dirent {\n\tlong int d_ino;\n\t__kernel_off_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[256];\n};\n\nstruct __fb_timings {\n\tu32 dclk;\n\tu32 hfreq;\n\tu32 vfreq;\n\tu32 hactive;\n\tu32 vactive;\n\tu32 hblank;\n\tu32 vblank;\n\tu32 htotal;\n\tu32 vtotal;\n};\n\nstruct audit_names;\n\nstruct __filename_head {\n\tconst char *name;\n\tint refcnt;\n\tstruct audit_names *aname;\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct pmu;\n\nstruct cgroup;\n\nstruct __group_key {\n\tint cpu;\n\tstruct pmu *pmu;\n\tstruct cgroup *cgroup;\n};\n\nstruct sha256_block_state {\n\tu32 h[8];\n};\n\nstruct __sha256_ctx {\n\tstruct sha256_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct __hmac_sha256_ctx {\n\tstruct __sha256_ctx sha_ctx;\n\tstruct sha256_block_state ostate;\n};\n\nstruct __hmac_sha256_key {\n\tstruct sha256_block_state istate;\n\tstruct sha256_block_state ostate;\n};\n\nstruct sha512_block_state {\n\tu64 h[8];\n};\n\nstruct __sha512_ctx {\n\tstruct sha512_block_state state;\n\tu64 bytecount_lo;\n\tu64 bytecount_hi;\n\tu8 buf[128];\n};\n\nstruct __hmac_sha512_ctx {\n\tstruct __sha512_ctx sha_ctx;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __hmac_sha512_key {\n\tstruct sha512_block_state istate;\n\tstruct sha512_block_state ostate;\n};\n\nstruct __ip6_tnl_parm {\n\tchar name[16];\n\tint link;\n\t__u8 proto;\n\t__u8 encap_limit;\n\t__u8 hop_limit;\n\tbool collect_md;\n\t__be32 flowinfo;\n\t__u32 flags;\n\tstruct in6_addr laddr;\n\tstruct in6_addr raddr;\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\t__u32 fwmark;\n\t__u32 index;\n\t__u8 erspan_ver;\n\t__u8 dir;\n\t__u16 hwid;\n};\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct __pldm_timestamp {\n\tu8 b[13];\n};\n\nstruct __pldm_header {\n\tuuid_t id;\n\tu8 revision;\n\t__le16 size;\n\tstruct __pldm_timestamp release_date;\n\t__le16 component_bitmap_len;\n\tu8 version_type;\n\tu8 version_len;\n\tu8 version_string[0];\n} __attribute__((packed));\n\nstruct __pldmfw_component_area {\n\t__le16 component_image_count;\n\tu8 components[0];\n};\n\nstruct __pldmfw_component_info {\n\t__le16 classification;\n\t__le16 identifier;\n\t__le32 comparison_stamp;\n\t__le16 options;\n\t__le16 activation_method;\n\t__le32 location_offset;\n\t__le32 size;\n\tu8 version_type;\n\tu8 version_len;\n\tu8 version_string[0];\n} __attribute__((packed));\n\nstruct __pldmfw_desc_tlv {\n\t__le16 type;\n\t__le16 size;\n\tu8 data[0];\n};\n\nstruct __pldmfw_record_area {\n\tu8 record_count;\n\tu8 records[0];\n};\n\nstruct __pldmfw_record_info {\n\t__le16 record_len;\n\tu8 descriptor_count;\n\t__le32 device_update_flags;\n\tu8 version_type;\n\tu8 version_len;\n\t__le16 package_data_len;\n\tu8 variable_record_data[0];\n} __attribute__((packed));\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tint _trapno;\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[8];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[8];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t\tstruct {\n\t\t\t\tlong unsigned int _data;\n\t\t\t\t__u32 _type;\n\t\t\t\t__u32 _flags;\n\t\t\t} _perf;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct bpf_flow_keys;\n\nstruct bpf_sock;\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n\t__u8 tstamp_type;\n\t__u64 hwtstamp;\n};\n\nstruct dentry;\n\nstruct __track_dentry_update_args {\n\tstruct dentry *dentry;\n\tint op;\n};\n\nstruct __track_range_args {\n\text4_lblk_t start;\n\text4_lblk_t end;\n};\n\nstruct inode;\n\nstruct __uprobe_key {\n\tstruct inode *inode;\n\tloff_t offset;\n};\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct __xfsstats {\n\tuint32_t xs_allocx;\n\tuint32_t xs_allocb;\n\tuint32_t xs_freex;\n\tuint32_t xs_freeb;\n\tuint32_t xs_abt_lookup;\n\tuint32_t xs_abt_compare;\n\tuint32_t xs_abt_insrec;\n\tuint32_t xs_abt_delrec;\n\tuint32_t xs_blk_mapr;\n\tuint32_t xs_blk_mapw;\n\tuint32_t xs_blk_unmap;\n\tuint32_t xs_add_exlist;\n\tuint32_t xs_del_exlist;\n\tuint32_t xs_look_exlist;\n\tuint32_t xs_cmp_exlist;\n\tuint32_t xs_bmbt_lookup;\n\tuint32_t xs_bmbt_compare;\n\tuint32_t xs_bmbt_insrec;\n\tuint32_t xs_bmbt_delrec;\n\tuint32_t xs_dir_lookup;\n\tuint32_t xs_dir_create;\n\tuint32_t xs_dir_remove;\n\tuint32_t xs_dir_getdents;\n\tuint32_t xs_trans_sync;\n\tuint32_t xs_trans_async;\n\tuint32_t xs_trans_empty;\n\tuint32_t xs_ig_attempts;\n\tuint32_t xs_ig_found;\n\tuint32_t xs_ig_frecycle;\n\tuint32_t xs_ig_missed;\n\tuint32_t xs_ig_dup;\n\tuint32_t xs_ig_reclaims;\n\tuint32_t xs_ig_attrchg;\n\tuint32_t xs_log_writes;\n\tuint32_t xs_log_blocks;\n\tuint32_t xs_log_noiclogs;\n\tuint32_t xs_log_force;\n\tuint32_t xs_log_force_sleep;\n\tuint32_t xs_try_logspace;\n\tuint32_t xs_sleep_logspace;\n\tuint32_t xs_push_ail;\n\tuint32_t xs_push_ail_success;\n\tuint32_t xs_push_ail_pushbuf;\n\tuint32_t xs_push_ail_pinned;\n\tuint32_t xs_push_ail_locked;\n\tuint32_t xs_push_ail_flushing;\n\tuint32_t xs_push_ail_restarts;\n\tuint32_t xs_push_ail_flush;\n\tuint32_t xs_xstrat_quick;\n\tuint32_t xs_xstrat_split;\n\tuint32_t xs_write_calls;\n\tuint32_t xs_read_calls;\n\tuint32_t xs_attr_get;\n\tuint32_t xs_attr_set;\n\tuint32_t xs_attr_remove;\n\tuint32_t xs_attr_list;\n\tuint32_t xs_iflush_count;\n\tuint32_t xs_icluster_flushcnt;\n\tuint32_t xs_icluster_flushinode;\n\tuint32_t xs_inodes_active;\n\tuint32_t __unused_vn_alloc;\n\tuint32_t __unused_vn_get;\n\tuint32_t __unused_vn_hold;\n\tuint32_t xs_inode_destroy;\n\tuint32_t xs_inode_destroy2;\n\tuint32_t xs_inode_mark_reclaimable;\n\tuint32_t __unused_vn_free;\n\tuint32_t xb_get;\n\tuint32_t xb_create;\n\tuint32_t xb_get_locked;\n\tuint32_t xb_get_locked_waited;\n\tuint32_t xb_busy_locked;\n\tuint32_t xb_miss_locked;\n\tuint32_t xb_page_retries;\n\tuint32_t xb_page_found;\n\tuint32_t xb_get_read;\n\tuint32_t xs_abtb_2[15];\n\tuint32_t xs_abtc_2[15];\n\tuint32_t xs_bmbt_2[15];\n\tuint32_t xs_ibt_2[15];\n\tuint32_t xs_fibt_2[15];\n\tuint32_t xs_rmap_2[15];\n\tuint32_t xs_refcbt_2[15];\n\tuint32_t xs_rmap_mem_2[15];\n\tuint32_t xs_rcbag_2[15];\n\tuint32_t xs_rtrmap_2[15];\n\tuint32_t xs_rtrmap_mem_2[15];\n\tuint32_t xs_rtrefcbt_2[15];\n\tuint32_t xs_qm_dqreclaims;\n\tuint32_t xs_qm_dqreclaim_misses;\n\tuint32_t xs_qm_dquot_dups;\n\tuint32_t xs_qm_dqcachemisses;\n\tuint32_t xs_qm_dqcachehits;\n\tuint32_t xs_qm_dqwants;\n\tuint32_t xs_qm_dquot;\n\tuint32_t xs_qm_dquot_unused;\n\tuint32_t xs_gc_read_calls;\n\tuint32_t xs_gc_write_calls;\n\tuint32_t xs_gc_zone_reset_calls;\n\tuint32_t xs_inodes_meta;\n\tuint64_t xs_xstrat_bytes;\n\tuint64_t xs_write_bytes;\n\tuint64_t xs_read_bytes;\n\tuint64_t xs_defer_relog;\n\tuint64_t xs_gc_bytes;\n};\n\nstruct net_device;\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n} __attribute__((packed));\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct kvm_stats_desc {\n\t__u32 flags;\n\t__s16 exponent;\n\t__u16 size;\n\t__u32 offset;\n\t__u32 bucket_size;\n\tchar name[0];\n};\n\nstruct _kvm_stats_desc {\n\tstruct kvm_stats_desc desc;\n\tchar name[48];\n};\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nstruct a4tech_sc {\n\tlong unsigned int quirks;\n\tunsigned int hw_wheel;\n\t__s32 delayed_value;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n};\n\nstruct ac6_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct access_coordinate {\n\tunsigned int read_bandwidth;\n\tunsigned int write_bandwidth;\n\tunsigned int read_latency;\n\tunsigned int write_latency;\n};\n\nstruct access_masks {\n\taccess_mask_t fs: 16;\n\taccess_mask_t net: 2;\n\taccess_mask_t scope: 2;\n};\n\nunion access_masks_all {\n\tstruct access_masks masks;\n\tu32 all;\n};\n\nstruct access_report_info {\n\tstruct callback_head work;\n\tconst char *access;\n\tstruct task_struct *target;\n\tstruct task_struct *agent;\n};\n\nstruct acct_v3 {\n\tchar ac_flag;\n\tchar ac_version;\n\t__u16 ac_tty;\n\t__u32 ac_exitcode;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u32 ac_etime;\n\tcomp_t ac_utime;\n\tcomp_t ac_stime;\n\tcomp_t ac_mem;\n\tcomp_t ac_io;\n\tcomp_t ac_rw;\n\tcomp_t ac_minflt;\n\tcomp_t ac_majflt;\n\tcomp_t ac_swaps;\n\tchar ac_comm[16];\n};\n\ntypedef struct acct_v3 acct_t;\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct crypto_tfm;\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tunsigned int cra_reqsize;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n};\n\nstruct comp_alg_common {\n\tstruct crypto_alg base;\n};\n\nstruct acomp_req;\n\nstruct crypto_acomp;\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\ntypedef void (*crypto_completion_t)(void *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n\tunsigned int dma_length;\n};\n\nstruct acomp_req_chain {\n\tcrypto_completion_t compl;\n\tvoid *data;\n\tstruct scatterlist ssg;\n\tstruct scatterlist dsg;\n\tunion {\n\t\tconst u8 *src;\n\t\tstruct folio *sfolio;\n\t};\n\tunion {\n\t\tu8 *dst;\n\t\tstruct folio *dfolio;\n\t};\n\tu32 flags;\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tunion {\n\t\tstruct scatterlist *dst;\n\t\tu8 *dvirt;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct acomp_req_chain chain;\n\tvoid *__ctx[0];\n};\n\nunion crypto_no_such_thing;\n\nstruct scatter_walk {\n\tunion {\n\t\tvoid * const addr;\n\t\tunion crypto_no_such_thing *__addr;\n\t};\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct acomp_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int slen;\n\tunsigned int dlen;\n\tint flags;\n};\n\nstruct acpi_device_id {\n\t__u8 id[16];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct action_cache {\n\tlong unsigned int allow_native[8];\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct action_gate_entry {\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n};\n\nstruct addr_marker {\n\tlong unsigned int start_address;\n\tconst char *name;\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tstruct rw_semaphore invalidate_lock;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tlong unsigned int nrpages;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t i_private_lock;\n\tstruct list_head i_private_list;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tvoid *i_private_data;\n};\n\nstruct file;\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*read_folio)(struct file *, struct folio *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tbool (*dirty_folio)(struct address_space *, struct folio *);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(const struct kiocb *, struct address_space *, loff_t, unsigned int, struct folio **, void **);\n\tint (*write_end)(const struct kiocb *, struct address_space *, loff_t, unsigned int, unsigned int, struct folio *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidate_folio)(struct folio *, size_t, size_t);\n\tbool (*release_folio)(struct folio *, gfp_t);\n\tvoid (*free_folio)(struct folio *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migrate_folio)(struct address_space *, struct folio *, struct folio *, enum migrate_mode);\n\tint (*launder_folio)(struct folio *);\n\tbool (*is_partially_uptodate)(struct folio *, size_t, size_t);\n\tvoid (*is_dirty_writeback)(struct folio *, bool *, bool *);\n\tint (*error_remove_folio)(struct address_space *, struct folio *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n\tint (*swap_rw)(struct kiocb *, struct iov_iter *);\n};\n\nstruct audit_ntp_val {\n\tlong long int oldval;\n\tlong long int newval;\n};\n\nstruct audit_ntp_data {\n\tstruct audit_ntp_val vals[6];\n};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct adjtimex_result {\n\tstruct audit_ntp_data ad;\n\tstruct timespec64 delta;\n\tbool clock_set;\n};\n\nstruct advisor_ctx {\n\tktime_t start_scan;\n\tlong unsigned int scan_time;\n\tlong unsigned int change;\n\tlong long unsigned int cpu_time;\n};\n\nstruct crypto_aead;\n\nstruct aead_request;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tstruct crypto_alg base;\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tvoid *__ctx[0];\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tvoid *__ctx[0];\n};\n\nstruct p8_aes_key {\n\tu32 rndkeys[60];\n\tint nrounds;\n};\n\nunion aes_enckey_arch {\n\tu32 rndkeys[60];\n\tstruct p8_aes_key p8;\n};\n\nstruct aes_enckey {\n\tu32 len;\n\tu32 nrounds;\n\tu32 padding[2];\n\tunion aes_enckey_arch k;\n};\n\nstruct affinity_context {\n\tconst struct cpumask *new_mask;\n\tstruct cpumask *user_mask;\n\tunsigned int flags;\n};\n\nstruct aggregate_control {\n\tlong int *aggregate;\n\tlong int *local;\n\tlong int *pending;\n\tlong int *ppending;\n\tlong int *cstat;\n\tlong int *cstat_prev;\n\tint size;\n};\n\nstruct component_master_ops;\n\nstruct component_match;\n\nstruct aggregate_device {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *parent;\n\tstruct component_match *match;\n};\n\nstruct xfs_btree_ops;\n\nstruct aghdr_init_data {\n\txfs_agblock_t agno;\n\txfs_extlen_t agsize;\n\tstruct list_head buffer_list;\n\txfs_rfsblock_t nfree;\n\txfs_daddr_t daddr;\n\tsize_t numblks;\n\tconst struct xfs_btree_ops *bc_ops;\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request;\n\nstruct crypto_ahash;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*export_core)(struct ahash_request *, void *);\n\tint (*import_core)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_ahash *);\n\tvoid (*exit_tfm)(struct crypto_ahash *);\n\tint (*clone_tfm)(struct crypto_ahash *, struct crypto_ahash *);\n\tstruct hash_alg_common halg;\n};\n\nstruct ahash_hmac_ctx {\n\tstruct crypto_ahash *hash;\n\tu8 pads[0];\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[112];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tunion {\n\t\tstruct scatterlist *src;\n\t\tconst u8 *svirt;\n\t};\n\tu8 *result;\n\tstruct scatterlist sg_head[2];\n\tcrypto_completion_t saved_complete;\n\tvoid *saved_data;\n\tvoid *__ctx[0];\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\nstruct ata_link;\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct reset_control;\n\nstruct regulator;\n\nstruct clk_bulk_data;\n\nstruct phy___2;\n\nstruct ata_port;\n\nstruct ata_host;\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 mask_port_map;\n\tu32 mask_port_ext;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 saved_port_cap[32];\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tunsigned int n_clks;\n\tstruct clk_bulk_data *clks;\n\tunsigned int f_rsts;\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy___2 **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[15];\n\tchar *irq_desc;\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nstruct wait_page_queue;\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_ioprio;\n\tu8 ki_write_stream;\n\tstruct wait_page_queue *ki_waitq;\n};\n\nstruct cred;\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool cancelled;\n\tbool work_scheduled;\n\tbool work_need_resched;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct kioctx;\n\nstruct eventfd_ctx;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx *ki_eventfd;\n};\n\nstruct poll_table_struct;\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tbool queued;\n\tint error;\n};\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct aio_waiter {\n\tstruct wait_queue_entry w;\n\tsize_t min_nr;\n};\n\nstruct akcipher_request;\n\nstruct crypto_akcipher;\n\nstruct akcipher_alg {\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[56];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tvoid (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)(void);\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct alias_prop {\n\tstruct list_head link;\n\tconst char *alias;\n\tstruct device_node *np;\n\tint id;\n\tchar stem[0];\n};\n\nstruct aligned_lock {\n\tunion {\n\t\tspinlock_t lock;\n\t\tu8 cacheline_padding[128];\n\t};\n};\n\nstruct zonelist;\n\nstruct zoneref;\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct codetag {\n\tunsigned int flags;\n\tunsigned int lineno;\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n};\n\nstruct alloc_tag_counters;\n\nstruct alloc_tag {\n\tstruct codetag ct;\n\tstruct alloc_tag_counters *counters;\n};\n\nstruct alloc_tag_counters {\n\tu64 bytes;\n\tu64 calls;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct psmouse;\n\nstruct input_dev;\n\nstruct alps_nibble_commands;\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct amba_cs_uci_id {\n\tunsigned int devarch;\n\tunsigned int devarch_mask;\n\tunsigned int devtype;\n\tvoid *data;\n};\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct clk;\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tunsigned int min_align_mask;\n\tlong unsigned int segment_boundary_mask;\n};\n\nstruct amba_device {\n\tstruct device dev;\n\tstruct resource res;\n\tstruct clk *pclk;\n\tstruct device_dma_parameters dma_parms;\n\tunsigned int periphid;\n\tstruct mutex periphid_lock;\n\tunsigned int cid;\n\tstruct amba_cs_uci_id uci;\n\tunsigned int irq[9];\n\tconst char *driver_override;\n};\n\nstruct rt_mutex_base {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nstruct rt_mutex {\n\tstruct rt_mutex_base rtmutex;\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n\tstruct regulator *bus_regulator;\n\tstruct dentry *debugfs;\n\tlong unsigned int addrs_in_instantiation[2];\n};\n\nstruct pci_dev;\n\nstruct amd_smbus {\n\tstruct pci_dev *dev;\n\tstruct i2c_adapter adapter;\n\tint base;\n\tint size;\n};\n\nstruct kobj_uevent_env;\n\nstruct kobj_ns_type_operations;\n\nstruct dev_pm_ops;\n\nstruct class {\n\tconst char *name;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tint (*dev_uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tvoid (*class_release)(const struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(const struct device *);\n\tvoid (*get_ownership)(const struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct device_attribute;\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tlong unsigned int num_children;\n\tlong unsigned int num_active_vmas;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct vm_area_struct;\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nstruct anon_vma_name {\n\tstruct kref kref;\n\tchar name[0];\n};\n\nstruct aperture_range {\n\tstruct device *dev;\n\tresource_size_t base;\n\tresource_size_t size;\n\tstruct list_head lh;\n\tvoid (*detach)(struct device *);\n};\n\nstruct api_context {\n\tstruct completion done;\n\tint status;\n};\n\nstruct page;\n\nstruct apply_range_data {\n\tstruct page **pages;\n\tint i;\n};\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct arch_elf_state {};\n\nstruct arch_hw_breakpoint {\n\tlong unsigned int address;\n\tu16 type;\n\tu16 len;\n\tu16 hw_len;\n\tu8 flags;\n\tbool perf_single_step;\n};\n\nstruct arch_io_reserve_memtype_wc_devres {\n\tresource_size_t start;\n\tresource_size_t size;\n};\n\nstruct arch_msi_msg_addr_hi {\n\tu32 address_hi;\n};\n\ntypedef struct arch_msi_msg_addr_hi arch_msi_msg_addr_hi_t;\n\nstruct arch_msi_msg_addr_lo {\n\tu32 address_lo;\n};\n\ntypedef struct arch_msi_msg_addr_lo arch_msi_msg_addr_lo_t;\n\nstruct arch_msi_msg_data {\n\tu32 data;\n};\n\ntypedef struct arch_msi_msg_data arch_msi_msg_data_t;\n\nstruct arch_optimized_insn {\n\tkprobe_opcode_t copied_insn[1];\n\tkprobe_opcode_t *insn;\n};\n\nstruct arch_specific_insn {\n\tkprobe_opcode_t *insn;\n\tint boostable;\n};\n\nstruct arch_uprobe {\n\tunion {\n\t\tu32 insn[2];\n\t\tu32 ixol[2];\n\t};\n};\n\nstruct arch_uprobe_task {\n\tlong unsigned int saved_trap_nr;\n};\n\nstruct arch_vdso_time_data {};\n\nstruct arena_free_span {\n\tstruct llist_node node;\n\tlong unsigned int uaddr;\n\tu32 page_cnt;\n};\n\nstruct free_entry;\n\nstruct nd_btt;\n\nstruct arena_info {\n\tu64 size;\n\tu64 external_lba_start;\n\tu32 internal_nlba;\n\tu32 internal_lbasize;\n\tu32 external_nlba;\n\tu32 external_lbasize;\n\tu32 nfree;\n\tu16 version_major;\n\tu16 version_minor;\n\tu32 sector_size;\n\tu64 nextoff;\n\tu64 infooff;\n\tu64 dataoff;\n\tu64 mapoff;\n\tu64 logoff;\n\tu64 info2off;\n\tstruct free_entry *freelist;\n\tu32 *rtt;\n\tstruct aligned_lock *map_locks;\n\tstruct nd_btt *nd_btt;\n\tstruct list_head list;\n\tstruct dentry *debugfs_dir;\n\tu32 flags;\n\tstruct mutex err_lock;\n\tint log_index[2];\n};\n\nstruct arg_dev_net_ip {\n\tstruct net *net;\n\tstruct in6_addr *addr;\n};\n\nstruct arg_netdev_event {\n\tconst struct net_device *dev;\n\tunion {\n\t\tunsigned char nh_flags;\n\t\tlong unsigned int event;\n\t};\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\nstruct trace_array;\n\nstruct trace_buffer;\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tu64 time_start;\n\tint cpu;\n};\n\ntypedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t);\n\nstruct asn1_decoder {\n\tconst unsigned char *machine;\n\tsize_t machlen;\n\tconst asn1_action_t *actions;\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct assoc_array_node;\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct assoc_array_ops;\n\nstruct assoc_array_edit {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct assoc_arrays {\n\tu32 n_arrays;\n\tu32 array_sz;\n\tconst __be32 *arrays;\n};\n\nstruct asym_cap_data {\n\tstruct list_head link;\n\tstruct callback_head rcu;\n\tlong unsigned int capacity;\n\tlong unsigned int cpus[0];\n};\n\nstruct asymmetric_key_id {\n\tshort unsigned int len;\n\tunsigned char data[0];\n};\n\nstruct asymmetric_key_ids {\n\tvoid *id[3];\n};\n\nstruct key_preparsed_payload;\n\nstruct asymmetric_key_parser {\n\tstruct list_head link;\n\tstruct module *owner;\n\tconst char *name;\n\tint (*parse)(struct key_preparsed_payload *);\n};\n\nstruct key;\n\nstruct seq_file;\n\nstruct kernel_pkey_params;\n\nstruct kernel_pkey_query;\n\nstruct public_key_signature;\n\nstruct asymmetric_key_subtype {\n\tstruct module *owner;\n\tconst char *name;\n\tshort unsigned int name_len;\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tvoid (*destroy)(void *, void *);\n\tint (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*verify_signature)(const struct key *, const struct public_key_signature *);\n};\n\nstruct usb_dev_state;\n\nstruct pid;\n\nstruct urb;\n\nstruct usb_memory;\n\nstruct async {\n\tstruct list_head asynclist;\n\tstruct usb_dev_state *ps;\n\tstruct pid *pid;\n\tconst struct cred *cred;\n\tunsigned int signr;\n\tunsigned int ifnum;\n\tvoid *userbuffer;\n\tvoid *userurb;\n\tsigval_t userurb_sigval;\n\tstruct urb *urb;\n\tstruct usb_memory *usbm;\n\tunsigned int mem_usage;\n\tint status;\n\tu8 bulk_addr;\n\tu8 bulk_status;\n};\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n};\n\nstruct io_poll {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tint retries;\n\tstruct wait_queue_entry wait;\n};\n\nstruct async_poll {\n\tstruct io_poll poll;\n\tstruct io_poll *double_poll;\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nstruct ata_acpi_drive {\n\tu32 pio;\n\tu32 dma;\n};\n\nstruct ata_acpi_gtm {\n\tstruct ata_acpi_drive drive[2];\n\tu32 flags;\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nstruct ata_cdl {\n\tu8 desc_log_buf[512];\n\tu8 ncq_sense_log_buf[1024];\n};\n\nstruct ata_cpr {\n\tu8 num;\n\tu8 num_storage_elements;\n\tu64 start_lba;\n\tu64 num_lbas;\n};\n\nstruct ata_cpr_log {\n\tu8 nr_cpr;\n\tstruct ata_cpr cpr[0];\n};\n\nstruct ata_dev_quirk_value {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 val;\n};\n\nstruct ata_dev_quirks_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tu64 quirks;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tu64 quirks;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 gp_log_dir[512];\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tstruct ata_cpr_log *cpr_log;\n\tstruct ata_cdl *cdl;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 sector_buf[512];\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst unsigned int *timeouts;\n};\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[16];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tu64 value;\n\tu8 cbl;\n\tu8 spd_limit;\n\tunsigned int xfer_mask;\n\tu64 quirk_on;\n\tu64 quirk_off;\n\tunsigned int pflags_on;\n\tu16 lflags_on;\n\tu16 lflags_off;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n\tconst struct attribute_group *encryption;\n};\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tunion {\n\t\tu8 error;\n\t\tu8 feature;\n\t};\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tunion {\n\t\tu8 status;\n\t\tu8 command;\n\t};\n\tu32 auxiliary;\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct scsi_cmnd;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tu64 qc_active;\n\tint nr_active_links;\n\tstruct work_struct deferred_qc_work;\n\tstruct ata_queued_cmd *deferred_qc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct delayed_work scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tunsigned int fastdrain_cnt;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nstruct ata_reset_operations {\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tvoid (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tvoid (*qc_ncq_fill_rtf)(struct ata_port *, u64);\n\tint (*cable_detect)(struct ata_port *);\n\tunsigned int (*mode_filter)(struct ata_device *, unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, __le16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tstruct ata_reset_operations reset;\n\tstruct ata_reset_operations pmp_reset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nstruct ata_timing {\n\tshort unsigned int mode;\n\tshort unsigned int setup;\n\tshort unsigned int act8b;\n\tshort unsigned int rec8b;\n\tshort unsigned int cyc8b;\n\tshort unsigned int active;\n\tshort unsigned int recover;\n\tshort unsigned int dmack_hold;\n\tshort unsigned int cycle;\n\tshort unsigned int udma;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ps2dev;\n\ntypedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int);\n\ntypedef void (*ps2_receive_handler_t)(struct ps2dev *, u8);\n\nstruct serio;\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n\tps2_pre_receive_handler_t pre_receive_handler;\n\tps2_receive_handler_t receive_handler;\n};\n\nstruct vivaldi_data {\n\tu32 function_row_physmap[24];\n\tunsigned int num_function_row_keys;\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[8];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tstruct vivaldi_data vdata;\n};\n\nstruct notifier_block;\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nstruct bin_attribute;\n\nstruct attribute_group {\n\tconst char *name;\n\tunion {\n\t\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\t\tumode_t (*is_visible_const)(struct kobject *, const struct attribute *, int);\n\t};\n\tumode_t (*is_bin_visible)(struct kobject *, const struct bin_attribute *, int);\n\tsize_t (*bin_size)(struct kobject *, const struct bin_attribute *, int);\n\tunion {\n\t\tstruct attribute **attrs;\n\t\tconst struct attribute * const *attrs_const;\n\t};\n\tconst struct bin_attribute * const *bin_attrs;\n};\n\nstruct audit_aux_data {\n\tstruct audit_aux_data *next;\n\tint type;\n};\n\nstruct audit_cap_data {\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n\tunion {\n\t\tunsigned int fE;\n\t\tkernel_cap_t effective;\n\t};\n\tkernel_cap_t ambient;\n\tkuid_t rootid;\n};\n\nstruct audit_aux_data_bprm_fcaps {\n\tstruct audit_aux_data d;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tstruct audit_cap_data old_pcap;\n\tstruct audit_cap_data new_pcap;\n};\n\nstruct lsm_prop_selinux {\n\tu32 secid;\n};\n\nstruct lsm_prop_smack {};\n\nstruct lsm_prop_apparmor {};\n\nstruct lsm_prop_bpf {\n\tu32 secid;\n};\n\nstruct lsm_prop {\n\tstruct lsm_prop_selinux selinux;\n\tstruct lsm_prop_smack smack;\n\tstruct lsm_prop_apparmor apparmor;\n\tstruct lsm_prop_bpf bpf;\n};\n\nstruct audit_aux_data_pids {\n\tstruct audit_aux_data d;\n\tpid_t target_pid[16];\n\tkuid_t target_auid[16];\n\tkuid_t target_uid[16];\n\tunsigned int target_sessionid[16];\n\tstruct lsm_prop target_ref[16];\n\tchar target_comm[256];\n\tint pid_count;\n};\n\nstruct audit_stamp {\n\tstruct timespec64 ctime;\n\tunsigned int serial;\n};\n\nstruct audit_context;\n\nstruct audit_buffer {\n\tstruct sk_buff *skb;\n\tstruct sk_buff_head skb_list;\n\tstruct audit_context *ctx;\n\tstruct audit_stamp stamp;\n\tgfp_t gfp_mask;\n};\n\nstruct audit_tree;\n\nstruct audit_node {\n\tstruct list_head list;\n\tstruct audit_tree *owner;\n\tunsigned int index;\n};\n\nstruct fsnotify_mark;\n\nstruct audit_chunk {\n\tstruct list_head hash;\n\tlong unsigned int key;\n\tstruct fsnotify_mark *mark;\n\tstruct list_head trees;\n\tint count;\n\tatomic_long_t refs;\n\tstruct callback_head head;\n\tstruct audit_node owners[0];\n};\n\nstruct filename;\n\nstruct audit_names {\n\tstruct list_head list;\n\tstruct filename *name;\n\tint name_len;\n\tbool hidden;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tstruct lsm_prop oprop;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tunsigned char type;\n\tbool should_free;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nstruct mq_attr {\n\t__kernel_long_t mq_flags;\n\t__kernel_long_t mq_maxmsg;\n\t__kernel_long_t mq_msgsize;\n\t__kernel_long_t mq_curmsgs;\n\t__kernel_long_t __reserved[4];\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\nstruct audit_proctitle {\n\tint len;\n\tchar *value;\n};\n\nstruct audit_tree_refs;\n\nstruct audit_context {\n\tint dummy;\n\tenum {\n\t\tAUDIT_CTX_UNUSED = 0,\n\t\tAUDIT_CTX_SYSCALL = 1,\n\t\tAUDIT_CTX_URING = 2,\n\t} context;\n\tenum audit_state state;\n\tenum audit_state current_state;\n\tstruct audit_stamp stamp;\n\tint major;\n\tint uring_op;\n\tlong unsigned int argv[4];\n\tlong int return_code;\n\tu64 prio;\n\tint return_valid;\n\tstruct audit_names preallocated_names[5];\n\tint name_count;\n\tstruct list_head names_list;\n\tchar *filterkey;\n\tstruct path pwd;\n\tstruct audit_aux_data *aux;\n\tstruct audit_aux_data *aux_pids;\n\tstruct __kernel_sockaddr_storage *sockaddr;\n\tsize_t sockaddr_len;\n\tpid_t ppid;\n\tkuid_t uid;\n\tkuid_t euid;\n\tkuid_t suid;\n\tkuid_t fsuid;\n\tkgid_t gid;\n\tkgid_t egid;\n\tkgid_t sgid;\n\tkgid_t fsgid;\n\tlong unsigned int personality;\n\tint arch;\n\tpid_t target_pid;\n\tkuid_t target_auid;\n\tkuid_t target_uid;\n\tunsigned int target_sessionid;\n\tstruct lsm_prop target_ref;\n\tchar target_comm[16];\n\tstruct audit_tree_refs *trees;\n\tstruct audit_tree_refs *first_trees;\n\tstruct list_head killed_trees;\n\tint tree_count;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tint nargs;\n\t\t\tlong int args[6];\n\t\t} socketcall;\n\t\tstruct {\n\t\t\tkuid_t uid;\n\t\t\tkgid_t gid;\n\t\t\tumode_t mode;\n\t\t\tstruct lsm_prop oprop;\n\t\t\tint has_perm;\n\t\t\tuid_t perm_uid;\n\t\t\tgid_t perm_gid;\n\t\t\tumode_t perm_mode;\n\t\t\tlong unsigned int qbytes;\n\t\t} ipc;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tstruct mq_attr mqstat;\n\t\t} mq_getsetattr;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tint sigev_signo;\n\t\t} mq_notify;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tsize_t msg_len;\n\t\t\tunsigned int msg_prio;\n\t\t\tstruct timespec64 abs_timeout;\n\t\t} mq_sendrecv;\n\t\tstruct {\n\t\t\tint oflag;\n\t\t\tumode_t mode;\n\t\t\tstruct mq_attr attr;\n\t\t} mq_open;\n\t\tstruct {\n\t\t\tpid_t pid;\n\t\t\tstruct audit_cap_data cap;\n\t\t} capset;\n\t\tstruct {\n\t\t\tint fd;\n\t\t\tint flags;\n\t\t} mmap;\n\t\tstruct open_how openat2;\n\t\tstruct {\n\t\t\tint argc;\n\t\t} execve;\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t} module;\n\t\tstruct {\n\t\t\tstruct audit_ntp_data ntp_data;\n\t\t\tstruct timespec64 tk_injoffset;\n\t\t} time;\n\t};\n\tint fds[2];\n\tstruct audit_proctitle proctitle;\n};\n\nstruct audit_ctl_mutex {\n\tstruct mutex lock;\n\tvoid *owner;\n};\n\nstruct audit_field;\n\nstruct audit_watch;\n\nstruct audit_fsnotify_mark;\n\nstruct audit_krule {\n\tu32 pflags;\n\tu32 flags;\n\tu32 listnr;\n\tu32 action;\n\tu32 mask[64];\n\tu32 buflen;\n\tu32 field_count;\n\tchar *filterkey;\n\tstruct audit_field *fields;\n\tstruct audit_field *arch_f;\n\tstruct audit_field *inode_f;\n\tstruct audit_watch *watch;\n\tstruct audit_tree *tree;\n\tstruct audit_fsnotify_mark *exe;\n\tstruct list_head rlist;\n\tstruct list_head list;\n\tu64 prio;\n};\n\nstruct audit_entry {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tstruct audit_krule rule;\n};\n\nstruct audit_features {\n\t__u32 vers;\n\t__u32 mask;\n\t__u32 features;\n\t__u32 lock;\n};\n\nstruct audit_field {\n\tu32 type;\n\tunion {\n\t\tu32 val;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tstruct {\n\t\t\tchar *lsm_str;\n\t\t\tvoid *lsm_rule;\n\t\t};\n\t};\n\tu32 op;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_mark_connector;\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignore_mask;\n\tunsigned int flags;\n};\n\nstruct audit_fsnotify_mark {\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar *path;\n\tstruct fsnotify_mark mark;\n\tstruct audit_krule *rule;\n};\n\nstruct sock;\n\nstruct audit_net {\n\tstruct sock *sk;\n};\n\nstruct audit_netlink_list {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff_head q;\n};\n\nstruct audit_nfcfgop_tab {\n\tenum audit_nfcfgop op;\n\tconst char *s;\n};\n\nstruct audit_parent {\n\tstruct list_head watches;\n\tstruct fsnotify_mark mark;\n};\n\nstruct audit_reply {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff *skb;\n};\n\nstruct audit_rule_data {\n\t__u32 flags;\n\t__u32 action;\n\t__u32 field_count;\n\t__u32 mask[64];\n\t__u32 fields[64];\n\t__u32 values[64];\n\t__u32 fieldflags[64];\n\t__u32 buflen;\n\tchar buf[0];\n};\n\nstruct audit_sig_info {\n\tuid_t uid;\n\tpid_t pid;\n\tchar ctx[0];\n};\n\nstruct audit_status {\n\t__u32 mask;\n\t__u32 enabled;\n\t__u32 failure;\n\t__u32 pid;\n\t__u32 rate_limit;\n\t__u32 backlog_limit;\n\t__u32 lost;\n\t__u32 backlog;\n\tunion {\n\t\t__u32 version;\n\t\t__u32 feature_bitmap;\n\t};\n\t__u32 backlog_wait_time;\n\t__u32 backlog_wait_time_actual;\n};\n\nstruct audit_tree {\n\trefcount_t count;\n\tint goner;\n\tstruct audit_chunk *root;\n\tstruct list_head chunks;\n\tstruct list_head rules;\n\tstruct list_head list;\n\tstruct list_head same_root;\n\tstruct callback_head head;\n\tchar pathname[0];\n};\n\nstruct audit_tree_mark {\n\tstruct fsnotify_mark mark;\n\tstruct audit_chunk *chunk;\n};\n\nstruct audit_tree_refs {\n\tstruct audit_tree_refs *next;\n\tstruct audit_chunk *c[31];\n};\n\nstruct audit_tty_status {\n\t__u32 enabled;\n\t__u32 log_passwd;\n};\n\nstruct audit_watch {\n\trefcount_t count;\n\tdev_t dev;\n\tchar *path;\n\tlong unsigned int ino;\n\tstruct audit_parent *parent;\n\tstruct list_head wlist;\n\tstruct list_head rules;\n};\n\nstruct auditd_connection {\n\tstruct pid *pid;\n\tu32 portid;\n\tstruct net *net;\n\tstruct callback_head rcu;\n};\n\nstruct auth_cred {\n\tconst struct cred *cred;\n\tconst char *principal;\n};\n\nstruct auth_ops;\n\nstruct auth_domain {\n\tstruct kref ref;\n\tstruct hlist_node hash;\n\tchar *name;\n\tstruct auth_ops *flavour;\n\tstruct callback_head callback_head;\n};\n\nstruct svc_rqst;\n\nstruct auth_ops {\n\tchar *name;\n\tstruct module *owner;\n\tint flavour;\n\tenum svc_auth_status (*accept)(struct svc_rqst *);\n\tint (*release)(struct svc_rqst *);\n\tvoid (*domain_release)(struct auth_domain *);\n\tenum svc_auth_status (*set_client)(struct svc_rqst *);\n\trpc_authflavor_t (*pseudoflavor)(struct svc_rqst *);\n};\n\nstruct auto_mode_param {\n\tint qp_type;\n};\n\nstruct auto_movable_group_stats {\n\tlong unsigned int movable_pages;\n\tlong unsigned int req_kernel_early_pages;\n};\n\nstruct auto_movable_stats {\n\tlong unsigned int kernel_early_pages;\n\tlong unsigned int movable_pages;\n};\n\nstruct task_group;\n\nstruct autogroup {\n\tstruct kref kref;\n\tstruct task_group *tg;\n\tstruct rw_semaphore lock;\n\tlong unsigned int id;\n\tint nice;\n};\n\nstruct auxiliary_device {\n\tstruct device dev;\n\tconst char *name;\n\tu32 id;\n\tstruct {\n\t\tstruct xarray irqs;\n\t\tstruct mutex lock;\n\t\tbool irq_dir_exists;\n\t} sysfs;\n};\n\nstruct auxiliary_device_id {\n\tchar name[40];\n\tkernel_ulong_t driver_data;\n};\n\nstruct of_device_id;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tconst struct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n\tstruct {\n\t\tvoid (*post_unbind_rust)(struct device *);\n\t} p_cb;\n};\n\nstruct auxiliary_driver {\n\tint (*probe)(struct auxiliary_device *, const struct auxiliary_device_id *);\n\tvoid (*remove)(struct auxiliary_device *);\n\tvoid (*shutdown)(struct auxiliary_device *);\n\tint (*suspend)(struct auxiliary_device *, pm_message_t);\n\tint (*resume)(struct auxiliary_device *);\n\tconst char *name;\n\tstruct device_driver driver;\n\tconst struct auxiliary_device_id *id_table;\n};\n\nstruct auxiliary_irq_info {\n\tstruct device_attribute sysfs_attr;\n\tchar name[11];\n};\n\nstruct av_decision {\n\tu32 allowed;\n\tu32 auditallow;\n\tu32 auditdeny;\n\tu32 seqno;\n\tu32 flags;\n};\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct avc_cache {\n\tstruct hlist_head slots[512];\n\tspinlock_t slots_lock[512];\n\tatomic_t lru_hint;\n\tatomic_t active_nodes;\n\tu32 latest_notif;\n};\n\nstruct avc_cache_stats {\n\tunsigned int lookups;\n\tunsigned int misses;\n\tunsigned int allocations;\n\tunsigned int reclaims;\n\tunsigned int frees;\n};\n\nstruct avc_callback_node {\n\tint (*callback)(u32);\n\tu32 events;\n\tstruct avc_callback_node *next;\n};\n\nstruct avc_xperms_node;\n\nstruct avc_entry {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tstruct av_decision avd;\n\tstruct avc_xperms_node *xp_node;\n};\n\nstruct avc_node {\n\tstruct avc_entry ae;\n\tstruct hlist_node list;\n\tstruct callback_head rhead;\n};\n\nstruct extended_perms_data;\n\nstruct extended_perms_decision {\n\tu8 used;\n\tu8 driver;\n\tu8 base_perm;\n\tstruct extended_perms_data *allowed;\n\tstruct extended_perms_data *auditallow;\n\tstruct extended_perms_data *dontaudit;\n};\n\nstruct avc_xperms_decision_node {\n\tstruct extended_perms_decision xpd;\n\tstruct list_head xpd_list;\n};\n\nstruct extended_perms_data {\n\tu32 p[8];\n};\n\nstruct extended_perms {\n\tu16 len;\n\tu8 base_perms;\n\tstruct extended_perms_data drivers;\n};\n\nstruct avc_xperms_node {\n\tstruct extended_perms xp;\n\tstruct list_head xpd_head;\n};\n\nstruct avdc_entry {\n\tu32 isid;\n\tu32 allowed;\n\tu32 audited;\n\tbool permissive;\n};\n\nstruct avtab_node;\n\nstruct avtab {\n\tstruct avtab_node **htable;\n\tu32 nel;\n\tu32 nslot;\n\tu32 mask;\n};\n\nstruct avtab_extended_perms;\n\nstruct avtab_datum {\n\tunion {\n\t\tu32 data;\n\t\tstruct avtab_extended_perms *xperms;\n\t} u;\n};\n\nstruct avtab_extended_perms {\n\tu8 specified;\n\tu8 driver;\n\tstruct extended_perms_data perms;\n};\n\nstruct avtab_key {\n\tu16 source_type;\n\tu16 target_type;\n\tu16 target_class;\n\tu16 specified;\n};\n\nstruct avtab_node {\n\tstruct avtab_key key;\n\tstruct avtab_datum datum;\n\tstruct avtab_node *next;\n};\n\nstruct backing_aio {\n\tstruct kiocb iocb;\n\trefcount_t ref;\n\tstruct kiocb *orig_iocb;\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n\tstruct work_struct work;\n\tlong int res;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n};\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct percpu_ref_data;\n\nstruct percpu_ref {\n\tlong unsigned int percpu_count_ptr;\n\tstruct percpu_ref_data *data;\n};\n\nstruct backing_dev_info;\n\nstruct cgroup_subsys_state;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tatomic_t writeback_inodes;\n\tstruct percpu_counter stat[4];\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tstruct delayed_work bw_dwork;\n\tstruct list_head bdi_node;\n\tstruct percpu_ref refcnt;\n\tstruct fprop_local_percpu memcg_completions;\n\tstruct cgroup_subsys_state *memcg_css;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct list_head memcg_node;\n\tstruct list_head blkcg_node;\n\tstruct list_head b_attached;\n\tstruct list_head offline_node;\n\tstruct work_struct switch_work;\n\tstruct llist_head switch_wbs_ctxs;\n\tunion {\n\t\tstruct work_struct release_work;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tlong unsigned int last_bdp_sleep;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\tstruct xarray cgwb_tree;\n\tstruct mutex cgwb_release_mutex;\n\tstruct rw_semaphore wb_switch_rwsem;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct dentry *debug_dir;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tshort unsigned int order;\n\tshort unsigned int mmap_miss;\n\tloff_t prev_pos;\n};\n\nstruct file_operations;\n\nstruct fown_struct;\n\nstruct file {\n\tspinlock_t f_lock;\n\tfmode_t f_mode;\n\tconst struct file_operations *f_op;\n\tstruct address_space *f_mapping;\n\tvoid *private_data;\n\tstruct inode *f_inode;\n\tunsigned int f_flags;\n\tunsigned int f_iocb_flags;\n\tconst struct cred *f_cred;\n\tstruct fown_struct *f_owner;\n\tunion {\n\t\tconst struct path f_path;\n\t\tstruct path __f_path;\n\t};\n\tunion {\n\t\tstruct mutex f_pos_lock;\n\t\tu64 f_pipe;\n\t};\n\tloff_t f_pos;\n\tvoid *f_security;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n\tstruct hlist_head *f_ep;\n\tunion {\n\t\tstruct callback_head f_task_work;\n\t\tstruct llist_node f_llist;\n\t\tstruct file_ra_state f_ra;\n\t\tfreeptr_t f_freeptr;\n\t};\n\tfile_ref_t f_ref;\n};\n\nstruct backing_file {\n\tstruct file file;\n\tunion {\n\t\tstruct path user_path;\n\t\tfreeptr_t bf_freeptr;\n\t};\n};\n\nstruct backing_file_ctx {\n\tconst struct cred *cred;\n\tvoid (*accessed)(struct file *);\n\tvoid (*end_write)(struct kiocb *, ssize_t);\n};\n\nstruct bpf_verifier_env;\n\nstruct backtrack_state {\n\tstruct bpf_verifier_env *env;\n\tu32 frame;\n\tu32 reg_masks[8];\n\tu64 stack_masks[8];\n};\n\nstruct seqcount_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_spinlock seqcount_spinlock_t;\n\nstruct seqlock {\n\tseqcount_spinlock_t seqcount;\n\tspinlock_t lock;\n};\n\ntypedef struct seqlock seqlock_t;\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct badblocks_context {\n\tsector_t start;\n\tsector_t len;\n\tint ack;\n};\n\nstruct badrange {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct badrange_entry {\n\tu64 start;\n\tu64 length;\n\tstruct list_head list;\n};\n\nstruct balance_callback {\n\tstruct balance_callback *next;\n\tvoid (*func)(struct rq *);\n};\n\nstruct balloon_dev_info {\n\tlong unsigned int isolated_pages;\n\tstruct list_head pages;\n\tint (*migratepage)(struct balloon_dev_info *, struct page *, struct page *, enum migrate_mode);\n\tbool adjust_managed_page_count;\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct local_lock {};\n\ntypedef struct local_lock local_lock_t;\n\nstruct batch_u16 {\n\tu16 entropy[48];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u32 {\n\tu32 entropy[24];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u64 {\n\tu64 entropy[12];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct batch_u8 {\n\tu8 entropy[96];\n\tlocal_lock_t lock;\n\tlong unsigned int generation;\n\tunsigned int position;\n};\n\nstruct bd_holder_disk {\n\tstruct list_head list;\n\tstruct kobject *holder_dir;\n\tint refcnt;\n};\n\nstruct gendisk;\n\nstruct request_queue;\n\nstruct disk_stats;\n\nstruct blk_holder_ops;\n\nstruct partition_meta_info;\n\nstruct block_device {\n\tsector_t bd_start_sect;\n\tsector_t bd_nr_sectors;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct disk_stats *bd_stats;\n\tlong unsigned int bd_stamp;\n\tatomic_t __bd_flags;\n\tdev_t bd_dev;\n\tstruct address_space *bd_mapping;\n\tatomic_t bd_openers;\n\tspinlock_t bd_size_lock;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tconst struct blk_holder_ops *bd_holder_ops;\n\tstruct mutex bd_holder_lock;\n\tint bd_holders;\n\tstruct kobject *bd_holder_dir;\n\tatomic_t bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n\tstruct partition_meta_info *bd_meta_info;\n\tint bd_writers;\n\tvoid *bd_security;\n\tstruct device bd_device;\n};\n\nstruct inode_state_flags {\n\tenum inode_state_flags_enum __state;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct super_block;\n\nstruct file_lock_context;\n\nstruct pipe_inode_info;\n\nstruct cdev;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tvoid *i_security;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\ttime64_t i_atime_sec;\n\ttime64_t i_mtime_sec;\n\ttime64_t i_ctime_sec;\n\tu32 i_atime_nsec;\n\tu32 i_mtime_nsec;\n\tu32 i_ctime_nsec;\n\tu32 i_generation;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tenum rw_hint i_write_hint;\n\tblkcnt_t i_blocks;\n\tstruct inode_state_flags i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct bdi_writeback *i_wb;\n\tint i_wb_frn_winner;\n\tu16 i_wb_frn_avg_time;\n\tu16 i_wb_frn_history;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tunion {\n\t\tstruct list_head i_devices;\n\t\tint i_linklen;\n\t};\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tstruct address_space * (*f_mapping)(void);\n\tssize_t (*read)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, const struct bin_attribute *, char *, loff_t, size_t);\n\tloff_t (*llseek)(struct file *, struct kobject *, const struct bin_attribute *, loff_t, int);\n\tint (*mmap)(struct file *, struct kobject *, const struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct qrwlock {\n\tunion {\n\t\tatomic_t cnts;\n\t\tstruct {\n\t\t\tu8 wlocked;\n\t\t\tu8 __lstate[3];\n\t\t};\n\t};\n\tarch_spinlock_t wait_lock;\n};\n\ntypedef struct qrwlock arch_rwlock_t;\n\nstruct rwlock {\n\tarch_rwlock_t raw_lock;\n};\n\nstruct binfmt_misc {\n\tstruct list_head entries;\n\trwlock_t entries_lock;\n\tbool enabled;\n};\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n} __attribute__((packed));\n\nstruct bio;\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec;\n\nstruct blkcg_gq;\n\nstruct bio_set;\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct block_device *bi_bdev;\n\tblk_opf_t bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tenum rw_hint bi_write_hint;\n\tu8 bi_write_stream;\n\tblk_status_t bi_status;\n\tu8 bi_bvec_gap_bit;\n\tatomic_t __bi_remaining;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bvec_iter bi_iter;\n\tunion {\n\t\tblk_qc_t bi_cookie;\n\t\tunsigned int __bi_nr_segments;\n\t};\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tstruct blkcg_gq *bi_blkg;\n\tu64 issue_time_ns;\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_set *bi_pool;\n};\n\nstruct bio_alloc_cache {\n\tstruct bio *free_list;\n\tstruct bio *free_list_irq;\n\tunsigned int nr;\n\tunsigned int nr_irq;\n};\n\nstruct blk_crypto_key;\n\nstruct bio_crypt_ctx {\n\tconst struct blk_crypto_key *bc_key;\n\tu64 bc_dun[4];\n};\n\nstruct bio_integrity_payload {\n\tstruct bvec_iter bip_iter;\n\tshort unsigned int bip_vcnt;\n\tshort unsigned int bip_max_vcnt;\n\tshort unsigned int bip_flags;\n\tu16 app_tag;\n\tstruct bio_vec *bip_vec;\n};\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec;\n\nstruct folio_queue;\n\nstruct iov_iter {\n\tu8 iter_type;\n\tbool nofault;\n\tbool data_source;\n\tsize_t iov_offset;\n\tunion {\n\t\tstruct iovec __ubuf_iovec;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tconst struct iovec *__iov;\n\t\t\t\tconst struct kvec *kvec;\n\t\t\t\tconst struct bio_vec *bvec;\n\t\t\t\tconst struct folio_queue *folioq;\n\t\t\t\tstruct xarray *xarray;\n\t\t\t\tvoid *ubuf;\n\t\t\t};\n\t\t\tsize_t count;\n\t\t};\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tu8 folioq_slot;\n\t\tloff_t xarray_start;\n\t};\n};\n\nstruct bio_map_data {\n\tbool is_our_pages: 1;\n\tbool is_null_mapped: 1;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct fsverity_info;\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct fsverity_info *vi;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool mempool_t;\n\nstruct kmem_cache;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tstruct bio_alloc_cache *cache;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tunsigned int back_pad;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n\tstruct hlist_node cpuhp_dead;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[12];\n};\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nstruct bitmap_page;\n\nstruct bitmap_counts {\n\tspinlock_t lock;\n\tstruct bitmap_page *bp;\n\tlong unsigned int pages;\n\tlong unsigned int missing_pages;\n\tlong unsigned int chunkshift;\n\tlong unsigned int chunks;\n};\n\nstruct bitmap_storage {\n\tstruct file *file;\n\tstruct page *sb_page;\n\tlong unsigned int sb_index;\n\tstruct page **filemap;\n\tlong unsigned int *filemap_attr;\n\tlong unsigned int file_pages;\n\tlong unsigned int bytes;\n};\n\nstruct mddev;\n\nstruct bitmap {\n\tstruct bitmap_counts counts;\n\tstruct mddev *mddev;\n\t__u64 events_cleared;\n\tint need_sync;\n\tstruct bitmap_storage storage;\n\tlong unsigned int flags;\n\tint allclean;\n\tatomic_t behind_writes;\n\tlong unsigned int behind_writes_used;\n\tlong unsigned int daemon_lastrun;\n\tlong unsigned int last_end_sync;\n\tatomic_t pending_writes;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t overflow_wait;\n\twait_queue_head_t behind_wait;\n\tstruct kernfs_node *sysfs_can_clear;\n\tint cluster_slot;\n};\n\nstruct md_submodule_head {\n\tenum md_submodule_type type;\n\tenum md_submodule_id id;\n\tconst char *name;\n\tstruct module *owner;\n};\n\ntypedef void md_bitmap_fn(struct mddev *, sector_t, long unsigned int);\n\nstruct md_bitmap_stats;\n\nstruct bitmap_operations {\n\tstruct md_submodule_head head;\n\tbool (*enabled)(void *, bool);\n\tint (*create)(struct mddev *);\n\tint (*resize)(struct mddev *, sector_t, int);\n\tint (*load)(struct mddev *);\n\tvoid (*destroy)(struct mddev *);\n\tvoid (*flush)(struct mddev *);\n\tvoid (*write_all)(struct mddev *);\n\tvoid (*dirty_bits)(struct mddev *, long unsigned int, long unsigned int);\n\tvoid (*unplug)(struct mddev *, bool);\n\tvoid (*daemon_work)(struct mddev *);\n\tvoid (*start_behind_write)(struct mddev *);\n\tvoid (*end_behind_write)(struct mddev *);\n\tvoid (*wait_behind_writes)(struct mddev *);\n\tmd_bitmap_fn *start_write;\n\tmd_bitmap_fn *end_write;\n\tmd_bitmap_fn *start_discard;\n\tmd_bitmap_fn *end_discard;\n\tsector_t (*skip_sync_blocks)(struct mddev *, sector_t);\n\tbool (*blocks_synced)(struct mddev *, sector_t);\n\tbool (*start_sync)(struct mddev *, sector_t, sector_t *, bool);\n\tvoid (*end_sync)(struct mddev *, sector_t, sector_t *);\n\tvoid (*cond_end_sync)(struct mddev *, sector_t, bool);\n\tvoid (*close_sync)(struct mddev *);\n\tvoid (*update_sb)(void *);\n\tint (*get_stats)(void *, struct md_bitmap_stats *);\n\tvoid (*sync_with_cluster)(struct mddev *, sector_t, sector_t, sector_t, sector_t);\n\tvoid * (*get_from_slot)(struct mddev *, int);\n\tint (*copy_from_slot)(struct mddev *, int, sector_t *, sector_t *, bool);\n\tvoid (*set_pages)(void *, long unsigned int);\n\tvoid (*free)(void *);\n\tstruct attribute_group *group;\n};\n\nstruct bitmap_page {\n\tchar *map;\n\tunsigned int hijacked: 1;\n\tunsigned int pending: 1;\n\tunsigned int count: 30;\n};\n\nstruct bitmap_super_s {\n\t__le32 magic;\n\t__le32 version;\n\t__u8 uuid[16];\n\t__le64 events;\n\t__le64 events_cleared;\n\t__le64 sync_size;\n\t__le32 state;\n\t__le32 chunksize;\n\t__le32 daemon_sleep;\n\t__le32 write_behind;\n\t__le32 sectors_reserved;\n\t__le32 nodes;\n\t__u8 cluster_name[64];\n\t__u8 pad[120];\n};\n\ntypedef struct bitmap_super_s bitmap_super_t;\n\nstruct bitmap_unplug_work {\n\tstruct work_struct work;\n\tstruct bitmap *bitmap;\n\tstruct completion *done;\n};\n\nstruct bl_dev_msg {\n\tint32_t status;\n\tuint32_t major;\n\tuint32_t minor;\n};\n\nstruct bl_msg_hdr {\n\tu8 type;\n\tu16 totallen;\n};\n\nstruct rpc_pipe_msg {\n\tstruct list_head list;\n\tvoid *data;\n\tsize_t len;\n\tsize_t copied;\n\tint errno;\n};\n\nstruct bl_pipe_msg {\n\tstruct rpc_pipe_msg msg;\n\twait_queue_head_t *bl_wq;\n};\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\nstruct blake2s_ctx {\n\tu32 h[8];\n\tu32 t[2];\n\tu32 f[2];\n\tu8 buf[64];\n\tunsigned int buflen;\n\tunsigned int outlen;\n};\n\nstruct blk_crypto_config {\n\tenum blk_crypto_mode_num crypto_mode;\n\tunsigned int data_unit_size;\n\tunsigned int dun_bytes;\n\tenum blk_crypto_key_type key_type;\n};\n\nstruct blk_crypto_key {\n\tstruct blk_crypto_config crypto_cfg;\n\tunsigned int data_unit_size_bits;\n\tunsigned int size;\n\tu8 bytes[128];\n};\n\nstruct blk_crypto_profile;\n\nstruct blk_crypto_ll_ops {\n\tint (*keyslot_program)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*keyslot_evict)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int);\n\tint (*derive_sw_secret)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*import_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n\tint (*generate_key)(struct blk_crypto_profile *, u8 *);\n\tint (*prepare_key)(struct blk_crypto_profile *, const u8 *, size_t, u8 *);\n};\n\nstruct blk_crypto_keyslot;\n\nstruct blk_crypto_profile {\n\tstruct blk_crypto_ll_ops ll_ops;\n\tunsigned int max_dun_bytes_supported;\n\tunsigned int key_types_supported;\n\tunsigned int modes_supported[5];\n\tstruct device *dev;\n\tunsigned int num_slots;\n\tstruct rw_semaphore lock;\n\tstruct lock_class_key lockdep_key;\n\twait_queue_head_t idle_slots_wait_queue;\n\tstruct list_head idle_slots;\n\tspinlock_t idle_slots_lock;\n\tstruct hlist_head *slot_hashtable;\n\tunsigned int log_slot_ht_size;\n\tstruct blk_crypto_keyslot *slots;\n};\n\nstruct p2pdma_provider;\n\nstruct pci_p2pdma_map_state {\n\tstruct p2pdma_provider *mem;\n\tenum pci_p2pdma_map_type map;\n};\n\nstruct blk_map_iter {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n\tstruct bio_vec *bvecs;\n\tbool is_integrity;\n};\n\nstruct blk_dma_iter {\n\tdma_addr_t addr;\n\tu32 len;\n\tstruct pci_p2pdma_map_state p2pdma;\n\tblk_status_t status;\n\tstruct blk_map_iter iter;\n};\n\nstruct blk_expired_data {\n\tbool has_timedout_rq;\n\tlong unsigned int next;\n\tlong unsigned int timeout_start;\n};\n\nstruct request;\n\nstruct blk_flush_queue {\n\tspinlock_t mq_flush_lock;\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tlong unsigned int flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct callback_head callback_head;\n};\n\nstruct blk_holder_ops {\n\tvoid (*mark_dead)(struct block_device *, bool);\n\tvoid (*sync)(struct block_device *);\n\tint (*freeze)(struct block_device *);\n\tint (*thaw)(struct block_device *);\n};\n\nstruct blk_independent_access_range;\n\nstruct blk_ia_range_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_independent_access_range *, char *);\n};\n\nstruct blk_independent_access_range {\n\tstruct kobject kobj;\n\tsector_t sector;\n\tsector_t nr_sectors;\n};\n\nstruct blk_independent_access_ranges {\n\tstruct kobject kobj;\n\tbool sysfs_registered;\n\tunsigned int nr_ia_ranges;\n\tstruct blk_independent_access_range ia_range[0];\n};\n\nstruct blk_integrity {\n\tunsigned char flags;\n\tenum blk_integrity_checksum csum_type;\n\tunsigned char metadata_size;\n\tunsigned char pi_offset;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n\tunsigned char pi_tuple_size;\n};\n\nstruct blk_io_trace {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 action;\n\t__u32 pid;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n};\n\nstruct blk_io_trace2 {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 pid;\n\t__u64 action;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n\t__u8 pad[12];\n};\n\nstruct blk_io_trace_remap {\n\t__be32 device_from;\n\t__be32 device_to;\n\t__be64 sector_from;\n};\n\nstruct blk_iou_cmd {\n\tint res;\n\tbool nowait;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n\tvoid (*probe)(dev_t);\n};\n\nstruct rq_list;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tunsigned int nr_tags;\n\tstruct rq_list *cached_rqs;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 64;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\nstruct seq_operations;\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct cpumask {\n\tlong unsigned int bits[128];\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tbool round_robin;\n\tstruct sbitmap_word *map;\n\tunsigned int *alloc_hint;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n};\n\nstruct blk_mq_queue_data;\n\nstruct io_comp_batch;\n\nstruct blk_mq_ops {\n\tblk_status_t (*queue_rq)(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\tvoid (*commit_rqs)(struct blk_mq_hw_ctx *);\n\tvoid (*queue_rqs)(struct rq_list *);\n\tint (*get_budget)(struct request_queue *);\n\tvoid (*put_budget)(struct request_queue *, int);\n\tvoid (*set_rq_budget_token)(struct request *, int);\n\tint (*get_rq_budget_token)(struct request *);\n\tenum blk_eh_timer_return (*timeout)(struct request *);\n\tint (*poll)(struct blk_mq_hw_ctx *, struct io_comp_batch *);\n\tvoid (*complete)(struct request *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, void *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tint (*init_request)(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\tvoid (*exit_request)(struct blk_mq_tag_set *, struct request *, unsigned int);\n\tvoid (*cleanup_rq)(struct request *);\n\tbool (*busy)(struct request_queue *);\n\tvoid (*map_queues)(struct blk_mq_tag_set *);\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct sbq_wait_state;\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tunsigned int min_shallow_depth;\n\tatomic_t completion_cnt;\n\tatomic_t wakeup_cnt;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tunsigned int active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct callback_head callback_head;\n};\n\nstruct rq_list {\n\tstruct request *head;\n\tstruct request *tail;\n};\n\nstruct blk_plug {\n\tstruct rq_list mq_list;\n\tstruct rq_list cached_rqs;\n\tu64 cur_ktime;\n\tshort unsigned int nr_ios;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n\tbool has_elevator;\n\tstruct list_head cb_list;\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tint accounting;\n};\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tu64 batch;\n};\n\nstruct blk_rq_wait {\n\tstruct completion done;\n\tblk_status_t ret;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct rchan;\n\nstruct blk_trace {\n\tint version;\n\tint trace_state;\n\tstruct rchan *rchan;\n\tlong unsigned int *sequence;\n\tunsigned char *msg_data;\n\tu64 act_mask;\n\tu64 start_lba;\n\tu64 end_lba;\n\tu32 pid;\n\tu32 dev;\n\tstruct dentry *dir;\n\tstruct list_head running_list;\n\tatomic_t dropped;\n};\n\nstruct blk_user_trace_setup {\n\tchar name[32];\n\t__u16 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n};\n\nstruct blk_user_trace_setup2 {\n\tchar name[64];\n\t__u64 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n\t__u32 flags;\n\t__u64 reserved[11];\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct cgroup_subsys;\n\nstruct css_rstat_cpu;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct css_rstat_cpu *rstat_cpu;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tint id;\n\tunsigned int flags;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n\tint nr_descendants;\n\tstruct cgroup_subsys_state *rstat_flush_next;\n};\n\nstruct blkcg_policy_data;\n\nstruct blkcg {\n\tstruct cgroup_subsys_state css;\n\tspinlock_t lock;\n\trefcount_t online_pin;\n\tatomic_t congestion_count;\n\tstruct xarray blkg_tree;\n\tstruct blkcg_gq *blkg_hint;\n\tstruct hlist_head blkg_list;\n\tstruct blkcg_policy_data *cpd[6];\n\tstruct list_head all_blkcgs_node;\n\tstruct llist_head *lhead;\n\tstruct list_head cgwb_list;\n};\n\nstruct blkg_iostat {\n\tu64 bytes[3];\n\tu64 ios[3];\n};\n\nstruct blkg_iostat_set {\n\tstruct u64_stats_sync sync;\n\tstruct blkcg_gq *blkg;\n\tstruct llist_node lnode;\n\tint lqueued;\n\tstruct blkg_iostat cur;\n\tstruct blkg_iostat last;\n};\n\nstruct blkg_policy_data;\n\nstruct blkcg_gq {\n\tstruct request_queue *q;\n\tstruct list_head q_node;\n\tstruct hlist_node blkcg_node;\n\tstruct blkcg *blkcg;\n\tstruct blkcg_gq *parent;\n\tstruct percpu_ref refcnt;\n\tbool online;\n\tstruct blkg_iostat_set *iostat_cpu;\n\tstruct blkg_iostat_set iostat;\n\tstruct blkg_policy_data *pd[6];\n\tspinlock_t async_bio_lock;\n\tstruct bio_list async_bios;\n\tunion {\n\t\tstruct work_struct async_bio_work;\n\t\tstruct work_struct free_work;\n\t};\n\tatomic_t use_delay;\n\tatomic64_t delay_nsec;\n\tatomic64_t delay_start;\n\tu64 last_delay;\n\tint last_use;\n\tstruct callback_head callback_head;\n};\n\ntypedef struct blkcg_policy_data *blkcg_pol_alloc_cpd_fn(gfp_t);\n\ntypedef void blkcg_pol_free_cpd_fn(struct blkcg_policy_data *);\n\ntypedef struct blkg_policy_data *blkcg_pol_alloc_pd_fn(struct gendisk *, struct blkcg *, gfp_t);\n\ntypedef void blkcg_pol_init_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_online_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_offline_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_free_pd_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_reset_pd_stats_fn(struct blkg_policy_data *);\n\ntypedef void blkcg_pol_stat_pd_fn(struct blkg_policy_data *, struct seq_file *);\n\nstruct cftype;\n\nstruct blkcg_policy {\n\tint plid;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tblkcg_pol_alloc_cpd_fn *cpd_alloc_fn;\n\tblkcg_pol_free_cpd_fn *cpd_free_fn;\n\tblkcg_pol_alloc_pd_fn *pd_alloc_fn;\n\tblkcg_pol_init_pd_fn *pd_init_fn;\n\tblkcg_pol_online_pd_fn *pd_online_fn;\n\tblkcg_pol_offline_pd_fn *pd_offline_fn;\n\tblkcg_pol_free_pd_fn *pd_free_fn;\n\tblkcg_pol_reset_pd_stats_fn *pd_reset_stats_fn;\n\tblkcg_pol_stat_pd_fn *pd_stat_fn;\n};\n\nstruct blkcg_policy_data {\n\tstruct blkcg *blkcg;\n\tint plid;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bio bio;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blkg_conf_ctx {\n\tchar *input;\n\tchar *body;\n\tstruct block_device *bdev;\n\tstruct blkcg_gq *blkg;\n};\n\nstruct blkg_policy_data {\n\tstruct blkcg_gq *blkg;\n\tint plid;\n\tbool online;\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n};\n\nstruct blk_report_zones_args;\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tvoid (*submit_bio)(struct bio *);\n\tint (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int);\n\tint (*open)(struct gendisk *, blk_mode_t);\n\tvoid (*release)(struct gendisk *);\n\tint (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*getgeo)(struct gendisk *, struct hd_geometry *);\n\tint (*set_read_only)(struct block_device *, bool);\n\tvoid (*free_disk)(struct gendisk *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, struct blk_report_zones_args *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tint (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n\tint (*alternative_gpt_sector)(struct gendisk *, sector_t *);\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[128];\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct boot_param_header {\n\t__be32 magic;\n\t__be32 totalsize;\n\t__be32 off_dt_struct;\n\t__be32 off_dt_strings;\n\t__be32 off_mem_rsvmap;\n\t__be32 version;\n\t__be32 last_comp_version;\n\t__be32 boot_cpuid_phys;\n\t__be32 dt_strings_size;\n\t__be32 dt_struct_size;\n};\n\nstruct boot_triggers {\n\tconst char *event;\n\tchar *trigger;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t};\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct boottb_freq {\n\tu64 boot_tb;\n\tu64 tb_freq;\n\tu64 timebase;\n\tu64 padded[3];\n};\n\nstruct bp_slots_histogram {\n\tatomic_t *count;\n};\n\nstruct bp_cpuinfo {\n\tunsigned int cpu_pinned;\n\tstruct bp_slots_histogram tsk_pinned;\n};\n\nstruct bpf_map_ops;\n\nstruct btf_record;\n\nstruct btf;\n\nstruct obj_cgroup;\n\nstruct bpf_map_owner;\n\nstruct bpf_map {\n\tu8 sha[32];\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tvoid *security;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu64 map_extra;\n\tu32 map_flags;\n\tu32 id;\n\tstruct btf_record *record;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tu32 btf_vmlinux_value_type_id;\n\tstruct btf *btf;\n\tstruct obj_cgroup *objcg;\n\tchar name[16];\n\tstruct mutex freeze_mutex;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tatomic64_t writecnt;\n\tspinlock_t owner_lock;\n\tstruct bpf_map_owner *owner;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tbool free_after_mult_rcu_gp;\n\tbool free_after_rcu_gp;\n\tatomic64_t sleepable_refcnt;\n\ts64 *elem_count;\n\tu64 cookie;\n\tchar *excl_prog_sha;\n};\n\nstruct range_tree {\n\tstruct rb_root_cached it_root;\n\tstruct rb_root_cached range_size_root;\n};\n\nstruct rqspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tu32 locked;\n\t};\n};\n\ntypedef struct rqspinlock rqspinlock_t;\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct irq_work {\n\tstruct __call_single_node node;\n\tvoid (*func)(struct irq_work *);\n\tstruct rcuwait irqwait;\n};\n\nstruct vm_struct;\n\nstruct bpf_arena {\n\tstruct bpf_map map;\n\tu64 user_vm_start;\n\tu64 user_vm_end;\n\tstruct vm_struct *kern_vm;\n\tstruct range_tree rt;\n\trqspinlock_t spinlock;\n\tstruct list_head vma_list;\n\tstruct mutex lock;\n\tstruct irq_work free_irq;\n\tstruct work_struct free_work;\n\tstruct llist_head free_spans;\n};\n\nstruct bpf_array_aux;\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_value;\n\t\t\tchar value[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_ptrs;\n\t\t\tvoid *ptrs[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_pptrs;\n\t\t\tvoid *pptrs[0];\n\t\t};\n\t};\n};\n\nstruct bpf_array_aux {\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct bpf_prog;\n\nstruct bpf_async_cb {\n\tstruct bpf_map *map;\n\tstruct bpf_prog *prog;\n\tvoid *callback_fn;\n\tvoid *value;\n\tstruct callback_head rcu;\n\tu64 flags;\n\tstruct irq_work worker;\n\trefcount_t refcnt;\n\tenum bpf_async_type type;\n\tstruct llist_head async_cmds;\n};\n\nstruct bpf_async_cmd {\n\tstruct llist_node node;\n\tu64 nsec;\n\tu32 mode;\n\tenum bpf_async_op op;\n};\n\nstruct bpf_hrtimer;\n\nstruct bpf_work;\n\nstruct bpf_async_kern {\n\tunion {\n\t\tstruct bpf_async_cb *cb;\n\t\tstruct bpf_hrtimer *timer;\n\t\tstruct bpf_work *work;\n\t};\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 ret_flags;\n\tu8 nr_args;\n\tu8 arg_size[12];\n\tu8 arg_flags[12];\n};\n\nstruct btf_type;\n\nstruct bpf_attach_target_info {\n\tstruct btf_func_model fmodel;\n\tlong int tgt_addr;\n\tstruct module *tgt_mod;\n\tconst char *tgt_name;\n\tconst struct btf_type *tgt_type;\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t\t__u64 map_extra;\n\t\t__s32 value_type_btf_obj_fd;\n\t\t__s32 map_token_fd;\n\t\t__u64 excl_prog_hash;\n\t\t__u32 excl_prog_hash_size;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\tunion {\n\t\t\t__u32 attach_prog_fd;\n\t\t\t__u32 attach_btf_obj_fd;\n\t\t};\n\t\t__u32 core_relo_cnt;\n\t\t__u64 fd_array;\n\t\t__u64 core_relos;\n\t\t__u32 core_relo_rec_size;\n\t\t__u32 log_true_size;\n\t\t__s32 prog_token_fd;\n\t\t__u32 fd_array_cnt;\n\t\t__u64 signature;\n\t\t__u32 signature_size;\n\t\t__s32 keyring_id;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t\t__s32 path_fd;\n\t};\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t\tunion {\n\t\t\t__u32 relative_fd;\n\t\t\t__u32 relative_id;\n\t\t};\n\t\t__u64 expected_revision;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t\t__u32 flags;\n\t\t__u32 cpu;\n\t\t__u32 batch_size;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t\t__s32 fd_by_id_token_fd;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\tunion {\n\t\t\t__u32 prog_cnt;\n\t\t\t__u32 count;\n\t\t};\n\t\t__u64 prog_attach_flags;\n\t\t__u64 link_ids;\n\t\t__u64 link_attach_flags;\n\t\t__u64 revision;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t\t__u64 cookie;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t\t__u32 btf_log_true_size;\n\t\t__u32 btf_flags;\n\t\t__s32 btf_token_fd;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 prog_fd;\n\t\t\t__u32 map_fd;\n\t\t};\n\t\tunion {\n\t\t\t__u32 target_fd;\n\t\t\t__u32 target_ifindex;\n\t\t};\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 target_btf_id;\n\t\t\tstruct {\n\t\t\t\t__u64 iter_info;\n\t\t\t\t__u32 iter_info_len;\n\t\t\t};\n\t\t\tstruct {\n\t\t\t\t__u64 bpf_cookie;\n\t\t\t} perf_event;\n\t\t\tstruct {\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u64 syms;\n\t\t\t\t__u64 addrs;\n\t\t\t\t__u64 cookies;\n\t\t\t} kprobe_multi;\n\t\t\tstruct {\n\t\t\t\t__u32 target_btf_id;\n\t\t\t\t__u64 cookie;\n\t\t\t} tracing;\n\t\t\tstruct {\n\t\t\t\t__u32 pf;\n\t\t\t\t__u32 hooknum;\n\t\t\t\t__s32 priority;\n\t\t\t\t__u32 flags;\n\t\t\t} netfilter;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} tcx;\n\t\t\tstruct {\n\t\t\t\t__u64 path;\n\t\t\t\t__u64 offsets;\n\t\t\t\t__u64 ref_ctr_offsets;\n\t\t\t\t__u64 cookies;\n\t\t\t\t__u32 cnt;\n\t\t\t\t__u32 flags;\n\t\t\t\t__u32 pid;\n\t\t\t} uprobe_multi;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} netkit;\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__u32 relative_fd;\n\t\t\t\t\t__u32 relative_id;\n\t\t\t\t};\n\t\t\t\t__u64 expected_revision;\n\t\t\t} cgroup;\n\t\t};\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\tunion {\n\t\t\t__u32 new_prog_fd;\n\t\t\t__u32 new_map_fd;\n\t\t};\n\t\t__u32 flags;\n\t\tunion {\n\t\t\t__u32 old_prog_fd;\n\t\t\t__u32 old_map_fd;\n\t\t};\n\t} link_update;\n\tstruct {\n\t\t__u32 link_fd;\n\t} link_detach;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 map_fd;\n\t\t__u32 flags;\n\t} prog_bind_map;\n\tstruct {\n\t\t__u32 flags;\n\t\t__u32 bpffs_fd;\n\t} token_create;\n\tstruct {\n\t\t__u64 stream_buf;\n\t\t__u32 stream_buf_len;\n\t\t__u32 stream_id;\n\t\t__u32 prog_fd;\n\t} prog_stream_read;\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u32 prog_fd;\n\t\t__u32 flags;\n\t} prog_assoc_struct_ops;\n};\n\nstruct bpf_binary_header {\n\tu32 size;\n\tlong: 0;\n\tu8 image[0];\n};\n\nstruct bpf_bloom_filter {\n\tstruct bpf_map map;\n\tu32 bitset_mask;\n\tu32 hash_seed;\n\tu32 nr_hash_funcs;\n\tlong unsigned int bitset[0];\n};\n\nstruct bpf_bprintf_buffers {\n\tchar bin_args[512];\n\tchar buf[1024];\n};\n\nstruct bpf_bprintf_data {\n\tu32 *bin_args;\n\tchar *buf;\n\tbool get_bin_args;\n\tbool get_buf;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n\t__u64 name;\n\t__u32 name_len;\n\t__u32 kernel_btf;\n};\n\nstruct bpf_map_desc {\n\tstruct bpf_map *ptr;\n\tint uid;\n};\n\nstruct btf_field;\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map_desc map;\n\tbool raw_mode;\n\tbool pkt_access;\n\tu8 release_regno;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint dynptr_id;\n\tint func_id;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tstruct btf *ret_btf;\n\tu32 ret_btf_id;\n\tu32 subprogno;\n\tstruct btf_field *kptr_field;\n\ts64 const_map_key;\n};\n\nstruct bpf_cand_cache {\n\tconst char *name;\n\tu32 name_len;\n\tu16 kind;\n\tu16 cnt;\n\tstruct {\n\t\tconst struct btf *btf;\n\t\tu32 id;\n\t} cands[0];\n};\n\nstruct bpf_run_ctx {};\n\nstruct bpf_prog_array_item;\n\nstruct bpf_cg_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tconst struct bpf_prog_array_item *prog_item;\n\tint retval;\n};\n\nstruct bpf_cgroup_dev_ctx {\n\t__u32 access_type;\n\t__u32 major;\n\t__u32 minor;\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tu32 flags;\n\tenum bpf_attach_type attach_type;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tbool sleepable;\n};\n\nstruct bpf_cgroup_link {\n\tstruct bpf_link link;\n\tstruct cgroup *cgroup;\n};\n\nstruct bpf_cgroup_storage_key {\n\t__u64 cgroup_inode_id;\n\t__u32 attach_type;\n};\n\nstruct bpf_storage_buffer;\n\nstruct bpf_cgroup_storage_map;\n\nstruct bpf_cgroup_storage {\n\tunion {\n\t\tstruct bpf_storage_buffer *buf;\n\t\tvoid *percpu_buf;\n\t};\n\tstruct bpf_cgroup_storage_map *map;\n\tstruct bpf_cgroup_storage_key key;\n\tstruct list_head list_map;\n\tstruct list_head list_cg;\n\tstruct rb_node node;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_cgroup_storage_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tstruct rb_root root;\n\tstruct list_head list;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_lru_locallist;\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_core_accessor {\n\t__u32 type_id;\n\t__u32 idx;\n\tconst char *name;\n};\n\nstruct bpf_core_cand {\n\tconst struct btf *btf;\n\t__u32 id;\n};\n\nstruct bpf_core_cand_list {\n\tstruct bpf_core_cand *cands;\n\tint len;\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_core_ctx {\n\tstruct bpf_verifier_log *log;\n\tconst struct btf *btf;\n};\n\nstruct bpf_core_relo {\n\t__u32 insn_off;\n\t__u32 type_id;\n\t__u32 access_str_off;\n\tenum bpf_core_relo_kind kind;\n};\n\nstruct bpf_core_relo_res {\n\t__u64 orig_val;\n\t__u64 new_val;\n\tbool poison;\n\tbool validate;\n\tbool fail_memsz_adjust;\n\t__u32 orig_sz;\n\t__u32 orig_type_id;\n\t__u32 new_sz;\n\t__u32 new_type_id;\n};\n\nstruct bpf_core_spec {\n\tconst struct btf *btf;\n\tstruct bpf_core_accessor spec[64];\n\t__u32 root_type_id;\n\tenum bpf_core_relo_kind relo_kind;\n\tint len;\n\tint raw_spec[64];\n\tint raw_len;\n\t__u32 bit_offset;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n};\n\nstruct bpf_cpumap_val {\n\t__u32 qsize;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct gro_node {\n\tlong unsigned int bitmask;\n\tstruct gro_list hash[8];\n\tstruct list_head rx_list;\n\tu32 rx_count;\n\tu32 cached_napi_id;\n};\n\nstruct xdp_bulk_queue;\n\nstruct ptr_ring;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct bpf_cpumap_val value;\n\tstruct bpf_prog *prog;\n\tstruct gro_node gro;\n\tstruct completion kthread_running;\n\tstruct rcu_work free_work;\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct bpf_cpumask {\n\tcpumask_t cpumask;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_type;\n\nstruct bpf_crypto_ctx {\n\tconst struct bpf_crypto_type *type;\n\tvoid *tfm;\n\tu32 siv_len;\n\tstruct callback_head rcu;\n\trefcount_t usage;\n};\n\nstruct bpf_crypto_params {\n\tchar type[14];\n\tu8 reserved[2];\n\tchar algo[128];\n\tu8 key[256];\n\tu32 key_len;\n\tu32 authsize;\n};\n\nstruct bpf_crypto_type {\n\tvoid * (*alloc_tfm)(const char *);\n\tvoid (*free_tfm)(void *);\n\tint (*has_algo)(const char *);\n\tint (*setkey)(void *, const u8 *, unsigned int);\n\tint (*setauthsize)(void *, unsigned int);\n\tint (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tint (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *);\n\tunsigned int (*ivsize)(void *);\n\tunsigned int (*statesize)(void *);\n\tu32 (*get_flags)(void *);\n\tstruct module *owner;\n\tchar name[14];\n};\n\nstruct bpf_crypto_type_list {\n\tconst struct bpf_crypto_type *type;\n\tstruct list_head list;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n\tstruct btf *btf;\n\tu32 btf_id;\n\tu32 ref_obj_id;\n\tbool refcounted;\n};\n\nstruct skb_ext;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t\tstruct llist_node ll_node;\n\t};\n\tstruct sock *sk;\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t\tlong unsigned int _sk_redir;\n\t};\n\tlong unsigned int _nfct;\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 pp_recycle: 1;\n\t__u8 active_extensions;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 __pkt_type_offset[0];\n\t\t\t__u8 pkt_type: 3;\n\t\t\t__u8 ignore_df: 1;\n\t\t\t__u8 dst_pending_confirm: 1;\n\t\t\t__u8 ip_summed: 2;\n\t\t\t__u8 ooo_okay: 1;\n\t\t\t__u8 __mono_tc_offset[0];\n\t\t\t__u8 tstamp_type: 2;\n\t\t\t__u8 tc_at_ingress: 1;\n\t\t\t__u8 tc_skip_classify: 1;\n\t\t\t__u8 remcsum_offload: 1;\n\t\t\t__u8 csum_complete_sw: 1;\n\t\t\t__u8 csum_level: 2;\n\t\t\t__u8 inner_protocol_type: 1;\n\t\t\t__u8 l4_hash: 1;\n\t\t\t__u8 sw_hash: 1;\n\t\t\t__u8 wifi_acked_valid: 1;\n\t\t\t__u8 wifi_acked: 1;\n\t\t\t__u8 no_fcs: 1;\n\t\t\t__u8 encapsulation: 1;\n\t\t\t__u8 encap_hdr_csum: 1;\n\t\t\t__u8 csum_valid: 1;\n\t\t\t__u8 ndisc_nodetype: 2;\n\t\t\t__u8 redirected: 1;\n\t\t\t__u8 nf_skip_egress: 1;\n\t\t\t__u8 slow_gro: 1;\n\t\t\t__u8 unreadable: 1;\n\t\t\t__u16 tc_index;\n\t\t\tu16 alloc_cpu;\n\t\t\tunion {\n\t\t\t\t__wsum csum;\n\t\t\t\tstruct {\n\t\t\t\t\t__u16 csum_start;\n\t\t\t\t\t__u16 csum_offset;\n\t\t\t\t};\n\t\t\t};\n\t\t\t__u32 priority;\n\t\t\tint skb_iif;\n\t\t\t__u32 hash;\n\t\t\tunion {\n\t\t\t\tu32 vlan_all;\n\t\t\t\tstruct {\n\t\t\t\t\t__be16 vlan_proto;\n\t\t\t\t\t__u16 vlan_tci;\n\t\t\t\t};\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tunsigned int napi_id;\n\t\t\t\tunsigned int sender_cpu;\n\t\t\t};\n\t\t\t__u32 secmark;\n\t\t\tunion {\n\t\t\t\t__u32 mark;\n\t\t\t\t__u32 reserved_tailroom;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\t__be16 inner_protocol;\n\t\t\t\t__u8 inner_ipproto;\n\t\t\t};\n\t\t\t__u16 inner_transport_header;\n\t\t\t__u16 inner_network_header;\n\t\t\t__u16 inner_mac_header;\n\t\t\t__be16 protocol;\n\t\t\t__u16 transport_header;\n\t\t\t__u16 network_header;\n\t\t\t__u16 mac_header;\n\t\t} headers;\n\t};\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tstruct skb_ext *extensions;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct xdp_rxq_info;\n\nstruct xdp_txq_info;\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tunion {\n\t\tstruct {\n\t\t\tu32 frame_sz;\n\t\t\tu32 flags;\n\t\t};\n\t\tu64 frame_sz_flags_init;\n\t};\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__be16 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tunsigned char skc_bypass_prot_mem: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct sock_cgroup_data {\n\tstruct cgroup *cgroup;\n};\n\nstruct dst_entry;\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct socket;\n\nstruct mem_cgroup;\n\nstruct xfrm_policy;\n\nstruct sock_reuseport;\n\nstruct bpf_local_storage;\n\nstruct numa_drop_counters;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\t__u8 __cacheline_group_begin__sock_write_rx[0];\n\tatomic_t sk_drops;\n\t__s32 sk_peek_off;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\t__u8 __cacheline_group_end__sock_write_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rx[0];\n\tstruct dst_entry *sk_rx_dst;\n\tint sk_rx_dst_ifindex;\n\tu32 sk_rx_dst_cookie;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tu16 sk_busy_poll_budget;\n\tu8 sk_prefer_busy_poll;\n\tu8 sk_userlocks;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tvoid (*sk_data_ready)(struct sock *);\n\tlong int sk_rcvtimeo;\n\tint sk_rcvlowat;\n\t__u8 __cacheline_group_end__sock_read_rx[0];\n\t__u8 __cacheline_group_begin__sock_read_rxtx[0];\n\tint sk_err;\n\tstruct socket *sk_socket;\n\tstruct mem_cgroup *sk_memcg;\n\tstruct xfrm_policy *sk_policy[2];\n\t__u8 __cacheline_group_end__sock_read_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_rxtx[0];\n\tsocket_lock_t sk_lock;\n\tu32 sk_reserved_mem;\n\tint sk_forward_alloc;\n\tu32 sk_tsflags;\n\t__u8 __cacheline_group_end__sock_write_rxtx[0];\n\t__u8 __cacheline_group_begin__sock_write_tx[0];\n\tint sk_write_pending;\n\tatomic_t sk_omem_alloc;\n\tint sk_err_soft;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff_head sk_write_queue;\n\tstruct page_frag sk_frag;\n\tunion {\n\t\tstruct timer_list sk_timer;\n\t\tstruct timer_list tcp_retransmit_timer;\n\t\tstruct timer_list mptcp_retransmit_timer;\n\t};\n\tlong unsigned int sk_pacing_rate;\n\tatomic_t sk_zckey;\n\tatomic_t sk_tskey;\n\tlong unsigned int sk_tx_queue_mapping_jiffies;\n\t__u8 __cacheline_group_end__sock_write_tx[0];\n\t__u8 __cacheline_group_begin__sock_read_tx[0];\n\tu32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong unsigned int sk_max_pacing_rate;\n\tlong int sk_sndtimeo;\n\tu32 sk_priority;\n\tu32 sk_mark;\n\tkuid_t sk_uid;\n\tu16 sk_protocol;\n\tu16 sk_type;\n\tstruct dst_entry *sk_dst_cache;\n\tnetdev_features_t sk_route_caps;\n\tu16 sk_gso_type;\n\tu16 sk_gso_max_segs;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\tu32 sk_txhash;\n\tint sk_sndbuf;\n\tu8 sk_pacing_shift;\n\tbool sk_use_task_frag;\n\t__u8 __cacheline_group_end__sock_read_tx[0];\n\tu8 sk_gso_disabled: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_shutdown;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tlong unsigned int sk_ino;\n\tspinlock_t sk_peer_lock;\n\tint sk_bind_phc;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tktime_t sk_stamp;\n\tint sk_disconnects;\n\tunion {\n\t\tu8 sk_txrehash;\n\t\tu8 sk_scm_recv_flags;\n\t\tstruct {\n\t\t\tu8 sk_scm_credentials: 1;\n\t\t\tu8 sk_scm_security: 1;\n\t\t\tu8 sk_scm_pidfd: 1;\n\t\t\tu8 sk_scm_rights: 1;\n\t\t\tu8 sk_scm_unused: 4;\n\t\t};\n\t};\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tu8 sk_bpf_cb_flags;\n\tvoid *sk_user_data;\n\tvoid *sk_security;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_local_storage *sk_bpf_storage;\n\tstruct numa_drop_counters *sk_drop_counters;\n\tunion {\n\t\tstruct callback_head sk_rcu;\n\t\tfreeptr_t sk_freeptr;\n\t};\n\tnetns_tracker ns_tracker;\n\tstruct xarray sk_user_frags;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sockaddr_unsized;\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr_unsized *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n\tu32 uaddrlen;\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *skb_data;\n\t};\n\tunion {\n\t\tvoid *skb_data_end;\n\t};\n\t__u32 skb_len;\n\t__u32 skb_tcp_flags;\n\t__u64 skb_hwtstamp;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tstruct sk_buff *syn_skb;\n\tstruct sk_buff *skb;\n\tvoid *skb_data_end;\n\tu8 op;\n\tu8 is_fullsock;\n\tu8 is_locked_tcp_sock;\n\tu8 remaining_opt_len;\n\tu64 temp;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy[1];\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tconst void *data;\n\tconst void *data_end;\n};\n\ntypedef struct user_pt_regs bpf_user_pt_regs_t;\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_sample_data;\n\nstruct perf_event;\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nstruct bpf_sysctl {\n\t__u32 write;\n\t__u32 file_pos;\n};\n\nstruct ctl_table_header;\n\nstruct ctl_table;\n\nstruct bpf_sysctl_kern {\n\tstruct ctl_table_header *head;\n\tconst struct ctl_table *table;\n\tvoid *cur_val;\n\tsize_t cur_len;\n\tvoid *new_val;\n\tsize_t new_len;\n\tint new_updated;\n\tint write;\n\tloff_t *ppos;\n\tu64 tmp_reg;\n};\n\nstruct bpf_sockopt {\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *optval;\n\t};\n\tunion {\n\t\tvoid *optval_end;\n\t};\n\t__s32 level;\n\t__s32 optname;\n\t__s32 optlen;\n\t__s32 retval;\n};\n\nstruct bpf_sockopt_kern {\n\tstruct sock *sk;\n\tu8 *optval;\n\tu8 *optval_end;\n\ts32 level;\n\ts32 optname;\n\ts32 optlen;\n\tstruct task_struct *current_task;\n\tu64 tmp_reg;\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tstruct bpf_sock *migrating_sk;\n\t};\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tstruct sock *migrating_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_sk_lookup {\n\tunion {\n\t\tunion {\n\t\t\tstruct bpf_sock *sk;\n\t\t};\n\t\t__u64 cookie;\n\t};\n\t__u32 family;\n\t__u32 protocol;\n\t__u32 remote_ip4;\n\t__u32 remote_ip6[4];\n\t__be16 remote_port;\n\t__u32 local_ip4;\n\t__u32 local_ip6[4];\n\t__u32 local_port;\n\t__u32 ingress_ifindex;\n};\n\nstruct bpf_sk_lookup_kern {\n\tu16 family;\n\tu16 protocol;\n\t__be16 sport;\n\tu16 dport;\n\tstruct {\n\t\t__be32 saddr;\n\t\t__be32 daddr;\n\t} v4;\n\tstruct {\n\t\tconst struct in6_addr *saddr;\n\t\tconst struct in6_addr *daddr;\n\t} v6;\n\tstruct sock *selected_sk;\n\tu32 ingress_ifindex;\n\tbool no_reuseport;\n};\n\nstruct nf_hook_state;\n\nstruct bpf_nf_ctx {\n\tconst struct nf_hook_state *state;\n\tstruct sk_buff *skb;\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_CGROUP_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_CGROUP_SKB_kern;\n\tstruct bpf_sock BPF_PROG_TYPE_CGROUP_SOCK_prog;\n\tstruct sock BPF_PROG_TYPE_CGROUP_SOCK_kern;\n\tstruct bpf_sock_addr BPF_PROG_TYPE_CGROUP_SOCK_ADDR_prog;\n\tstruct bpf_sock_addr_kern BPF_PROG_TYPE_CGROUP_SOCK_ADDR_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_prog;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_kern;\n\tstruct bpf_sysctl BPF_PROG_TYPE_CGROUP_SYSCTL_prog;\n\tstruct bpf_sysctl_kern BPF_PROG_TYPE_CGROUP_SYSCTL_kern;\n\tstruct bpf_sockopt BPF_PROG_TYPE_CGROUP_SOCKOPT_prog;\n\tstruct bpf_sockopt_kern BPF_PROG_TYPE_CGROUP_SOCKOPT_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tstruct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog;\n\tstruct bpf_sk_lookup_kern BPF_PROG_TYPE_SK_LOOKUP_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n\tvoid *BPF_PROG_TYPE_LSM_prog;\n\tvoid *BPF_PROG_TYPE_LSM_kern;\n\tvoid *BPF_PROG_TYPE_SYSCALL_prog;\n\tvoid *BPF_PROG_TYPE_SYSCALL_kern;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_prog;\n\tstruct bpf_nf_ctx BPF_PROG_TYPE_NETFILTER_kern;\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[512];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n\tu32 fp_start;\n\tu32 fp_end;\n};\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tvoid *rw_image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n};\n\nstruct bpf_dtab_netdev;\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n};\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dummy_ops_state;\n\nstruct bpf_dummy_ops {\n\tint (*test_1)(struct bpf_dummy_ops_state *);\n\tint (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int);\n\tint (*test_sleepable)(struct bpf_dummy_ops_state *);\n};\n\nstruct bpf_dummy_ops_state {\n\tint val;\n};\n\nstruct bpf_dummy_ops_test_args {\n\tu64 args[12];\n\tstruct bpf_dummy_ops_state state;\n};\n\nstruct bpf_dynptr {\n\t__u64 __opaque[2];\n};\n\nstruct freader {\n\tvoid *buf;\n\tu32 buf_sz;\n\tint err;\n\tunion {\n\t\tstruct {\n\t\t\tstruct file *file;\n\t\t\tstruct folio *folio;\n\t\t\tvoid *addr;\n\t\t\tloff_t folio_off;\n\t\t\tbool may_fault;\n\t\t};\n\t\tstruct {\n\t\t\tconst char *data;\n\t\t\tu64 data_sz;\n\t\t};\n\t};\n};\n\nstruct bpf_dynptr_file_impl {\n\tstruct freader freader;\n\tu64 offset;\n\tu64 size;\n};\n\nstruct bpf_dynptr_kern {\n\tvoid *data;\n\tu32 size;\n\tu32 offset;\n};\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tunion {\n\t\tstruct bpf_cgroup_storage *cgroup_storage[2];\n\t\tu64 bpf_cookie;\n\t};\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_empty_prog_array {\n\tstruct bpf_prog_array hdr;\n\tstruct bpf_prog *null_prog;\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\t__u16 tot_len;\n\t\t__u16 mtu_result;\n\t};\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__be16 h_vlan_proto;\n\t\t\t__be16 h_vlan_TCI;\n\t\t};\n\t\t__u32 tbid;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u32 mark;\n\t\t};\n\t\tstruct {\n\t\t\t__u8 smac[6];\n\t\t\t__u8 dmac[6];\n\t\t};\n\t};\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_tramp_link {\n\tstruct bpf_link link;\n\tstruct hlist_node tramp_hlist;\n\tu64 cookie;\n};\n\nstruct bpf_trampoline;\n\nstruct bpf_tracing_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n\tstruct bpf_prog *tgt_prog;\n};\n\nstruct bpf_fsession_link {\n\tstruct bpf_tracing_link link;\n\tstruct bpf_tramp_link fexit;\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n\tbool called: 1;\n\tbool verified: 1;\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tbool might_sleep;\n\tbool allow_fastcall;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 *arg1_btf_id;\n\t\t\tu32 *arg2_btf_id;\n\t\t\tu32 *arg3_btf_id;\n\t\t\tu32 *arg4_btf_id;\n\t\t\tu32 *arg5_btf_id;\n\t\t};\n\t\tu32 *arg_btf_id[5];\n\t\tstruct {\n\t\t\tsize_t arg1_size;\n\t\t\tsize_t arg2_size;\n\t\t\tsize_t arg3_size;\n\t\t\tsize_t arg4_size;\n\t\t\tsize_t arg5_size;\n\t\t};\n\t\tsize_t arg_size[5];\n\t};\n\tint *ret_btf_id;\n\tbool (*allowed)(const struct bpf_prog *);\n};\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\ts32 off;\n\tunion {\n\t\tint range;\n\t\tstruct {\n\t\t\tstruct bpf_map *map_ptr;\n\t\t\tu32 map_uid;\n\t\t};\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t};\n\t\tstruct {\n\t\t\tu32 mem_size;\n\t\t\tu32 dynptr_id;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_dynptr_type type;\n\t\t\tbool first_slot;\n\t\t} dynptr;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tenum bpf_iter_state state: 2;\n\t\t\tint depth: 30;\n\t\t} iter;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tIRQ_NATIVE_KFUNC = 0,\n\t\t\t\tIRQ_LOCK_KFUNC = 1,\n\t\t\t} kfunc_class;\n\t\t} irq;\n\t\tstruct {\n\t\t\tlong unsigned int raw1;\n\t\t\tlong unsigned int raw2;\n\t\t} raw;\n\t\tu32 subprogno;\n\t};\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tu32 id;\n\tu32 ref_obj_id;\n\tu32 frameno;\n\ts32 subreg_def;\n\tbool precise;\n};\n\nstruct bpf_retval_range {\n\ts32 minval;\n\ts32 maxval;\n};\n\nstruct bpf_stack_state;\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tu32 async_entry_cnt;\n\tstruct bpf_retval_range callback_ret_range;\n\tbool in_callback_fn;\n\tbool in_async_callback_fn;\n\tbool in_exception_callback_fn;\n\tu32 callback_depth;\n\tstruct bpf_stack_state *stack;\n\tint allocated_stack;\n};\n\nstruct bpf_hrtimer {\n\tstruct bpf_async_cb cb;\n\tstruct hrtimer timer;\n\tatomic_t cancelling;\n};\n\nstruct bpf_mem_caches;\n\nstruct bpf_mem_cache;\n\nstruct bpf_mem_alloc {\n\tstruct bpf_mem_caches *caches;\n\tstruct bpf_mem_cache *cache;\n\tstruct obj_cgroup *objcg;\n\tbool percpu;\n\tstruct work_struct work;\n\tvoid (*dtor_ctx_free)(void *);\n\tvoid *dtor_ctx;\n};\n\nstruct pcpu_freelist_head;\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node;\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int target_free;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bucket;\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bpf_mem_alloc ma;\n\tstruct bpf_mem_alloc pcpu_ma;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tstruct percpu_counter pcount;\n\tatomic_t count;\n\tbool use_percpu_counter;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_iarray {\n\tint cnt;\n\tu32 items[0];\n};\n\nstruct bpf_id_pair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct bpf_idmap {\n\tu32 tmp_id_gen;\n\tu32 cnt;\n\tstruct bpf_id_pair map[600];\n};\n\nstruct bpf_idset {\n\tu32 num_ids;\n\tstruct {\n\t\tu32 id;\n\t\tu32 cnt;\n\t} entries[600];\n};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tbool is_ldsx;\n\tunion {\n\t\tint ctx_field_size;\n\t\tstruct {\n\t\t\tstruct btf *btf;\n\t\t\tu32 btf_id;\n\t\t\tu32 ref_obj_id;\n\t\t};\n\t};\n\tstruct bpf_verifier_log *log;\n\tbool is_retval;\n};\n\nstruct bpf_insn_array_value {\n\t__u32 orig_off;\n\t__u32 xlated_off;\n\t__u32 jitted_off;\n\tlong: 0;\n};\n\nstruct bpf_insn_array {\n\tstruct bpf_map map;\n\tatomic_t used;\n\tlong int *ips;\n\tstruct {\n\t\tstruct {} __empty_values;\n\t\tstruct bpf_insn_array_value values[0];\n\t};\n};\n\nstruct bpf_map_ptr_state {\n\tstruct bpf_map *map_ptr;\n\tbool poison;\n\tbool unpriv;\n};\n\nstruct bpf_loop_inline_state {\n\tunsigned int initialized: 1;\n\tunsigned int fit_for_inline: 1;\n\tu32 callback_subprogno;\n};\n\nstruct btf_struct_meta;\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tstruct bpf_map_ptr_state map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t\tstruct {\n\t\t\tenum bpf_reg_type reg_type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct btf *btf;\n\t\t\t\t\tu32 btf_id;\n\t\t\t\t};\n\t\t\t\tu32 mem_size;\n\t\t\t};\n\t\t} btf_var;\n\t\tstruct bpf_loop_inline_state loop_inline_state;\n\t};\n\tunion {\n\t\tu64 obj_new_size;\n\t\tu64 insert_off;\n\t};\n\tstruct bpf_iarray *jt;\n\tstruct btf_struct_meta *kptr_struct_meta;\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tu32 seen;\n\tbool nospec;\n\tbool nospec_result;\n\tbool zext_dst;\n\tbool needs_zext;\n\tbool non_sleepable;\n\tbool is_iter_next;\n\tbool call_with_percpu_alloc_ptr;\n\tu8 alu_state;\n\tu8 fastcall_pattern: 1;\n\tu8 fastcall_spills_num: 3;\n\tu8 arg_prog: 4;\n\tunsigned int orig_idx;\n\tbool jmp_point;\n\tbool prune_point;\n\tbool force_checkpoint;\n\tbool calls_callback;\n\tu32 scc;\n\tu16 live_regs_before;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_iter_meta;\n\nstruct bpf_iter__bpf_link {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_link *link;\n\t};\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter__bpf_map_elem {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__bpf_prog {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_prog *prog;\n\t};\n};\n\nstruct bpf_iter__bpf_sk_storage_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n\tunion {\n\t\tvoid *value;\n\t};\n};\n\nstruct bpf_iter__cgroup {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct cgroup *cgroup;\n\t};\n};\n\nstruct dma_buf;\n\nstruct bpf_iter__dmabuf {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct dma_buf *dmabuf;\n\t};\n};\n\nstruct fib6_info;\n\nstruct bpf_iter__ipv6_route {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct fib6_info *rt;\n\t};\n};\n\nstruct bpf_iter__kmem_cache {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kmem_cache *s;\n\t};\n};\n\nstruct kallsym_iter;\n\nstruct bpf_iter__ksym {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct kallsym_iter *ksym;\n\t};\n};\n\nstruct netlink_sock;\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nstruct bpf_iter__sockmap {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n\tunion {\n\t\tvoid *key;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t};\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter__task__safe_trusted {\n\tstruct bpf_iter_meta *meta;\n\tstruct task_struct *task;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct bpf_iter__task_vma {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tunion {\n\t\tstruct vm_area_struct *vma;\n\t};\n};\n\nstruct bpf_iter__tcp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct sock_common *sk_common;\n\t};\n\tuid_t uid;\n};\n\nstruct udp_sock;\n\nstruct bpf_iter__udp {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct udp_sock *udp_sk;\n\t};\n\tuid_t uid;\n\tlong: 0;\n\tint bucket;\n};\n\nstruct unix_sock;\n\nstruct bpf_iter__unix {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct unix_sock *unix_sk;\n\t};\n\tuid_t uid;\n};\n\nstruct bpf_iter_aux_info {\n\tstruct bpf_map *map;\n\tstruct {\n\t\tstruct cgroup *start;\n\t\tenum bpf_cgroup_iter_order order;\n\t} cgroup;\n\tstruct {\n\t\tenum bpf_iter_task_type type;\n\t\tu32 pid;\n\t} task;\n};\n\nstruct bpf_iter_bits {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_iter_bits_kern {\n\tunion {\n\t\t__u64 *bits;\n\t\t__u64 bits_copy;\n\t};\n\tint nr_bits;\n\tint bit;\n};\n\nstruct bpf_iter_css {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_css_kern {\n\tstruct cgroup_subsys_state *start;\n\tstruct cgroup_subsys_state *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_css_task {\n\t__u64 __opaque[1];\n};\n\nstruct css_task_iter;\n\nstruct bpf_iter_css_task_kern {\n\tstruct css_task_iter *css_it;\n};\n\nstruct bpf_iter_dmabuf {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_dmabuf_kern {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct bpf_iter_kmem_cache {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_kmem_cache_kern {\n\tstruct kmem_cache *pos;\n};\n\nstruct bpf_iter_target_info;\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_aux_info aux;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nunion bpf_iter_link_info {\n\tstruct {\n\t\t__u32 map_fd;\n\t} map;\n\tstruct {\n\t\tenum bpf_cgroup_iter_order order;\n\t\t__u32 cgroup_fd;\n\t\t__u64 cgroup_id;\n\t} cgroup;\n\tstruct {\n\t\t__u32 tid;\n\t\t__u32 pid;\n\t\t__u32 pid_fd;\n\t} task;\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_meta__safe_trusted {\n\tstruct seq_file *seq;\n};\n\nstruct bpf_iter_num {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_num_kern {\n\tint cur;\n\tint end;\n};\n\nstruct bpf_iter_seq_info;\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tconst struct bpf_iter_seq_info *seq_info;\n\tstruct bpf_prog *prog;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 0;\n\tu8 target_private[0];\n};\n\ntypedef int (*bpf_iter_attach_target_t)(struct bpf_prog *, union bpf_iter_link_info *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_show_fdinfo_t)(const struct bpf_iter_aux_info *, struct seq_file *);\n\nstruct bpf_link_info;\n\ntypedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *, struct bpf_link_info *);\n\ntypedef const struct bpf_func_proto * (*bpf_iter_get_func_proto_t)(enum bpf_func_id, const struct bpf_prog *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tbpf_iter_attach_target_t attach_target;\n\tbpf_iter_detach_target_t detach_target;\n\tbpf_iter_show_fdinfo_t show_fdinfo;\n\tbpf_iter_fill_link_info_t fill_link_info;\n\tbpf_iter_get_func_proto_t get_func_proto;\n\tu32 ctx_arg_info_size;\n\tu32 feature;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n\tconst struct bpf_iter_seq_info *seq_info;\n};\n\nstruct bpf_iter_scx_dsq {\n\tu64 __opaque[6];\n};\n\nstruct scx_dsq_list_node {\n\tstruct list_head node;\n\tu32 flags;\n\tu32 priv;\n};\n\nstruct scx_dispatch_q;\n\nstruct bpf_iter_scx_dsq_kern {\n\tstruct scx_dsq_list_node cursor;\n\tstruct scx_dispatch_q *dsq;\n\tu64 slice;\n\tu64 vtime;\n};\n\nstruct bpf_iter_seq_array_map_info {\n\tstruct bpf_map *map;\n\tvoid *percpu_value_buf;\n\tu32 index;\n};\n\nstruct bpf_iter_seq_hash_map_info {\n\tstruct bpf_map *map;\n\tstruct bpf_htab *htab;\n\tvoid *percpu_value_buf;\n\tu32 bucket_id;\n\tu32 skip_elems;\n};\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *, struct bpf_iter_aux_info *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_seq_info {\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n};\n\nstruct bpf_iter_seq_link_info {\n\tu32 link_id;\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 map_id;\n};\n\nstruct bpf_iter_seq_prog_info {\n\tu32 prog_id;\n};\n\nstruct bpf_iter_seq_sk_storage_map_info {\n\tstruct bpf_map *map;\n\tunsigned int bucket_id;\n\tunsigned int skip_elems;\n};\n\nstruct pid_namespace;\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n\tenum bpf_iter_task_type type;\n\tu32 pid;\n\tu32 pid_visiting;\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct mm_struct;\n\nstruct bpf_iter_seq_task_vma_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *vma;\n\tu32 tid;\n\tlong unsigned int prev_vm_start;\n\tlong unsigned int prev_vm_end;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_task {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_iter_task_kern {\n\tstruct task_struct *task;\n\tstruct task_struct *pos;\n\tunsigned int flags;\n};\n\nstruct bpf_iter_task_vma {\n\t__u64 __opaque[1];\n};\n\nstruct bpf_iter_task_vma_kern_data;\n\nstruct bpf_iter_task_vma_kern {\n\tstruct bpf_iter_task_vma_kern_data *data;\n};\n\nstruct maple_enode;\n\nstruct maple_tree;\n\nstruct slab_sheaf;\n\nstruct maple_node;\n\nstruct ma_state {\n\tstruct maple_tree *tree;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tstruct maple_enode *node;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tstruct slab_sheaf *sheaf;\n\tstruct maple_node *alloc;\n\tlong unsigned int node_request;\n\tenum maple_status status;\n\tunsigned char depth;\n\tunsigned char offset;\n\tunsigned char mas_flags;\n\tunsigned char end;\n\tenum store_type store_type;\n};\n\nstruct vma_iterator {\n\tstruct ma_state mas;\n};\n\nstruct mmap_unlock_irq_work;\n\nstruct bpf_iter_task_vma_kern_data {\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct mmap_unlock_irq_work *work;\n\tstruct vma_iterator vmi;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *tailcall_target;\n\tvoid *tailcall_bypass;\n\tvoid *bypass_addr;\n\tvoid *aux;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool tailcall_target_stable;\n\tu8 adj_off;\n\tu16 reason;\n\tu32 insn_idx;\n};\n\nstruct bpf_jmp_history_entry {\n\tu32 idx;\n\tu32 prev_idx: 20;\n\tu32 flags: 12;\n\tu64 linked_regs;\n};\n\nstruct bpf_key {\n\tstruct key *key;\n\tbool has_ref;\n};\n\nstruct bpf_kfunc_btf {\n\tstruct btf *btf;\n\tstruct module *module;\n\tu16 offset;\n};\n\nstruct bpf_kfunc_btf_tab {\n\tstruct bpf_kfunc_btf descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_call_arg_meta {\n\tstruct btf *btf;\n\tu32 func_id;\n\tu32 kfunc_flags;\n\tconst struct btf_type *func_proto;\n\tconst char *func_name;\n\tu32 ref_obj_id;\n\tu8 release_regno;\n\tbool r0_rdonly;\n\tu32 ret_btf_id;\n\tu64 r0_size;\n\tu32 subprogno;\n\tstruct {\n\t\tu64 value;\n\t\tbool found;\n\t} arg_constant;\n\tstruct btf *arg_btf;\n\tu32 arg_btf_id;\n\tbool arg_owning_ref;\n\tbool arg_prog;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_list_head;\n\tstruct {\n\t\tstruct btf_field *field;\n\t} arg_rbtree_root;\n\tstruct {\n\t\tenum bpf_dynptr_type type;\n\t\tu32 id;\n\t\tu32 ref_obj_id;\n\t} initialized_dynptr;\n\tstruct {\n\t\tu8 spi;\n\t\tu8 frameno;\n\t} iter;\n\tstruct bpf_map_desc map;\n\tu64 mem_size;\n};\n\nstruct bpf_kfunc_desc {\n\tstruct btf_func_model func_model;\n\tu32 func_id;\n\ts32 imm;\n\tu16 offset;\n\tlong unsigned int addr;\n};\n\nstruct bpf_kfunc_desc_tab {\n\tstruct bpf_kfunc_desc descs[256];\n\tu32 nr_descs;\n};\n\nstruct bpf_kfunc_meta {\n\tstruct btf *btf;\n\tconst struct btf_type *proto;\n\tconst char *name;\n\tconst u32 *flags;\n\ts32 id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t\t__u64 cookie;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t\t__u32 target_obj_id;\n\t\t\t__u32 target_btf_id;\n\t\t\t__u64 cookie;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u64 target_name;\n\t\t\t__u32 target_name_len;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 map_id;\n\t\t\t\t} map;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 cgroup_id;\n\t\t\t\t\t__u32 order;\n\t\t\t\t} cgroup;\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 tid;\n\t\t\t\t\t__u32 pid;\n\t\t\t\t} task;\n\t\t\t};\n\t\t} iter;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t} xdp;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t} struct_ops;\n\t\tstruct {\n\t\t\t__u32 pf;\n\t\t\t__u32 hooknum;\n\t\t\t__s32 priority;\n\t\t\t__u32 flags;\n\t\t} netfilter;\n\t\tstruct {\n\t\t\t__u64 addrs;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u64 missed;\n\t\t\t__u64 cookies;\n\t\t} kprobe_multi;\n\t\tstruct {\n\t\t\t__u64 path;\n\t\t\t__u64 offsets;\n\t\t\t__u64 ref_ctr_offsets;\n\t\t\t__u64 cookies;\n\t\t\t__u32 path_size;\n\t\t\t__u32 count;\n\t\t\t__u32 flags;\n\t\t\t__u32 pid;\n\t\t} uprobe_multi;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 file_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t\t__u64 ref_ctr_offset;\n\t\t\t\t} uprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 func_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u32 offset;\n\t\t\t\t\t__u64 addr;\n\t\t\t\t\t__u64 missed;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} kprobe;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 tp_name;\n\t\t\t\t\t__u32 name_len;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} tracepoint;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 config;\n\t\t\t\t\t__u32 type;\n\t\t\t\t\t__u64 cookie;\n\t\t\t\t} event;\n\t\t\t};\n\t\t} perf_event;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} tcx;\n\t\tstruct {\n\t\t\t__u32 ifindex;\n\t\t\t__u32 attach_type;\n\t\t} netkit;\n\t\tstruct {\n\t\t\t__u32 map_id;\n\t\t\t__u32 attach_type;\n\t\t} sockmap;\n\t};\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tvoid (*dealloc_deferred)(struct bpf_link *);\n\tint (*detach)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n\tint (*update_map)(struct bpf_link *, struct bpf_map *, struct bpf_map *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nstruct bpf_list_head {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_list_node {\n\t__u64 __opaque[3];\n};\n\nstruct bpf_list_node_kern {\n\tstruct list_head list_head;\n\tvoid *owner;\n};\n\nstruct func_instance;\n\nstruct live_stack_query {\n\tstruct func_instance *instances[8];\n\tu32 curframe;\n\tu32 insn_idx;\n};\n\nstruct bpf_liveness {\n\tstruct hlist_head func_instances[256];\n\tstruct live_stack_query live_stack_query;\n\tstruct func_instance *cur_instance;\n\tu64 write_masks_acc[8];\n\tu32 write_insn_idx;\n};\n\nstruct bpf_local_storage_data;\n\nstruct bpf_local_storage {\n\tstruct bpf_local_storage_data *cache[16];\n\tstruct hlist_head list;\n\tvoid *owner;\n\tstruct callback_head rcu;\n\trqspinlock_t lock;\n\tu64 mem_charge;\n\trefcount_t owner_refcnt;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_cache {\n\tspinlock_t idx_lock;\n\tu64 idx_usage_counts[16];\n};\n\nstruct bpf_local_storage_map;\n\nstruct bpf_local_storage_data {\n\tstruct bpf_local_storage_map *smap;\n\tu8 data[0];\n};\n\nstruct bpf_local_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_local_storage *local_storage;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct hlist_node free_node;\n\t};\n\tatomic_t state;\n\tbool use_kmalloc_nolock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_local_storage_data sdata;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_local_storage_map_bucket;\n\nstruct bpf_local_storage_map {\n\tstruct bpf_map map;\n\tstruct bpf_local_storage_map_bucket *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tbool use_kmalloc_nolock;\n};\n\nstruct bpf_local_storage_map_bucket {\n\tstruct hlist_head list;\n\trqspinlock_t lock;\n};\n\nstruct bpf_lpm_trie_key_hdr {\n\t__u32 prefixlen;\n};\n\nstruct bpf_lpm_trie_key_u8 {\n\tunion {\n\t\tstruct bpf_lpm_trie_key_hdr hdr;\n\t\t__u32 prefixlen;\n\t};\n\t__u8 data[0];\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n\t__u32 btf_vmlinux_id;\n\t__u64 map_extra;\n\t__u64 hash;\n\t__u32 hash_size;\n};\n\ntypedef u64 (*bpf_callback_t)(u64, u64, u64, u64, u64);\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tlong int (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tlong int (*map_delete_elem)(struct bpf_map *, void *);\n\tlong int (*map_push_elem)(struct bpf_map *, void *, u64);\n\tlong int (*map_pop_elem)(struct bpf_map *, void *);\n\tlong int (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\tint (*map_get_hash)(struct bpf_map *, u32, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(struct bpf_map *, void *, bool);\n\tint (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n\tlong unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32);\n\tvoid (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32);\n\tstruct bpf_local_storage ** (*map_owner_storage_ptr)(void *);\n\tlong int (*map_redirect)(struct bpf_map *, u64, u64);\n\tbool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *);\n\tint (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *);\n\tlong int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64);\n\tu64 (*map_mem_usage)(const struct bpf_map *);\n\tint *map_btf_id;\n\tconst struct bpf_iter_seq_info *iter_seq_info;\n};\n\nstruct bpf_map_owner {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tbool xdp_has_frags;\n\tbool sleepable;\n\tu64 storage_cookie[2];\n\tconst struct btf_type *attach_func_proto;\n\tenum bpf_attach_type expected_attach_type;\n};\n\nstruct bpf_mem_cache {\n\tstruct llist_head free_llist;\n\tlocal_t active;\n\tstruct llist_head free_llist_extra;\n\tstruct irq_work refill_work;\n\tstruct obj_cgroup *objcg;\n\tint unit_size;\n\tint free_cnt;\n\tint low_watermark;\n\tint high_watermark;\n\tint batch;\n\tint percpu_size;\n\tbool draining;\n\tstruct bpf_mem_cache *tgt;\n\tvoid (*dtor)(void *, void *);\n\tvoid *dtor_ctx;\n\tstruct llist_head free_by_rcu;\n\tstruct llist_node *free_by_rcu_tail;\n\tstruct llist_head waiting_for_gp;\n\tstruct llist_node *waiting_for_gp_tail;\n\tstruct callback_head rcu;\n\tatomic_t call_rcu_in_progress;\n\tstruct llist_head free_llist_extra_rcu;\n\tstruct llist_head free_by_rcu_ttrace;\n\tstruct llist_head waiting_for_gp_ttrace;\n\tstruct callback_head rcu_ttrace;\n\tatomic_t call_rcu_ttrace_in_progress;\n};\n\nstruct bpf_mem_caches {\n\tstruct bpf_mem_cache cache[11];\n};\n\nstruct bpf_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tu64 delegate_cmds;\n\tu64 delegate_maps;\n\tu64 delegate_progs;\n\tu64 delegate_attachs;\n};\n\nstruct bpf_mprog_fp {\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_mprog_bundle;\n\nstruct bpf_mprog_entry {\n\tstruct bpf_mprog_fp fp_items[64];\n\tstruct bpf_mprog_bundle *parent;\n};\n\nstruct bpf_mprog_cp {\n\tstruct bpf_link *link;\n};\n\nstruct bpf_mprog_bundle {\n\tstruct bpf_mprog_entry a;\n\tstruct bpf_mprog_entry b;\n\tstruct bpf_mprog_cp cp_items[64];\n\tstruct bpf_prog *ref;\n\tatomic64_t revision;\n\tu32 count;\n};\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_nh_params {\n\tu32 nh_family;\n\tunion {\n\t\tu32 ipv4_nh;\n\t\tstruct in6_addr ipv6_nh;\n\t};\n};\n\nstruct bpf_redirect_info {\n\tu64 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 flags;\n\tu32 map_id;\n\tenum bpf_map_type map_type;\n\tstruct bpf_nh_params nh;\n\tu32 kern_flags;\n};\n\nstruct bpf_net_context {\n\tstruct bpf_redirect_info ri;\n\tstruct list_head cpu_map_flush_list;\n\tstruct list_head dev_map_flush_list;\n\tstruct list_head xskmap_map_flush_list;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tstruct net *net;\n\tstruct list_head node;\n\tenum netns_bpf_attach_type netns_type;\n};\n\ntypedef unsigned int nf_hookfn(void *, struct sk_buff *, const struct nf_hook_state *);\n\nstruct nf_hook_ops {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tnf_hookfn *hook;\n\tstruct net_device *dev;\n\tvoid *priv;\n\tu8 pf;\n\tenum nf_hook_ops_type hook_ops_type: 8;\n\tunsigned int hooknum;\n\tint priority;\n};\n\nstruct nf_defrag_hook;\n\nstruct bpf_nf_link {\n\tstruct bpf_link link;\n\tstruct nf_hook_ops hook_ops;\n\tnetns_tracker ns_tracker;\n\tstruct net *net;\n\tu32 dead;\n\tconst struct nf_defrag_hook *defrag_hook;\n};\n\nstruct bpf_prog_offload_ops;\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_perf_link {\n\tstruct bpf_link link;\n\tstruct file *perf_file;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\nstruct bpf_preload_info {\n\tchar link_name[16];\n\tstruct bpf_link *link;\n};\n\nstruct bpf_preload_ops {\n\tint (*preload)(struct bpf_preload_info *);\n\tstruct module *owner;\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct bpf_prog_stats;\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinding_requested: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tu16 call_get_stack: 1;\n\tu16 call_get_func_ip: 1;\n\tu16 call_session_cookie: 1;\n\tu16 tstamp_type_access: 1;\n\tu16 sleepable: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tunion {\n\t\tu8 digest[32];\n\t\tu8 tag[8];\n\t};\n\tstruct bpf_prog_stats *stats;\n\tu8 *active;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_insns;\n\t\t\tstruct sock_filter insns[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_insnsi;\n\t\t\tstruct bpf_insn insnsi[0];\n\t\t};\n\t};\n};\n\nstruct bpf_stream {\n\tatomic_t capacity;\n\tstruct llist_head log;\n\tstruct mutex lock;\n\tstruct llist_node *backlog_head;\n\tstruct llist_node *backlog_tail;\n};\n\nstruct bpf_prog_ops;\n\nstruct bpf_struct_ops;\n\nstruct btf_mod_pair;\n\nstruct user_struct;\n\nstruct bpf_token;\n\nstruct bpf_prog_offload;\n\nstruct exception_table_entry;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 real_func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 attach_st_ops_member_off;\n\tu32 ctx_arg_info_size;\n\tu32 max_rdonly_access;\n\tu32 max_rdwr_access;\n\tu32 subprog_start;\n\tstruct btf *attach_btf;\n\tstruct bpf_ctx_arg_aux *ctx_arg_info;\n\tvoid *priv_stack_ptr;\n\tstruct mutex dst_mutex;\n\tstruct bpf_prog *dst_prog;\n\tstruct bpf_trampoline *dst_trampoline;\n\tenum bpf_prog_type saved_dst_prog_type;\n\tenum bpf_attach_type saved_dst_attach_type;\n\tbool verifier_zext;\n\tbool dev_bound;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool attach_tracing_prog;\n\tbool func_proto_unreliable;\n\tbool tail_call_reachable;\n\tbool xdp_has_frags;\n\tbool exception_cb;\n\tbool exception_boundary;\n\tbool is_extended;\n\tbool jits_use_priv_stack;\n\tbool priv_stack_requested;\n\tbool changes_pkt_data;\n\tbool might_sleep;\n\tbool kprobe_write_ctx;\n\tu64 prog_array_member_cnt;\n\tstruct mutex ext_mutex;\n\tstruct bpf_arena *arena;\n\tvoid (*recursion_detected)(struct bpf_prog *);\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tstruct bpf_prog_aux *main_prog_aux;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tstruct bpf_kfunc_desc_tab *kfunc_tab;\n\tstruct bpf_kfunc_btf_tab *kfunc_btf_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct bpf_map **used_maps;\n\tstruct mutex used_maps_mutex;\n\tstruct btf_mod_pair *used_btfs;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tu32 verified_insns;\n\tint cgroup_atype;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tu64 (*bpf_exception_cb)(u64, u64, u64, u64, u64);\n\tvoid *security;\n\tstruct bpf_token *token;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tstruct module *mod;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct bpf_stream stream[2];\n\tstruct mutex st_ops_assoc_mutex;\n\tstruct bpf_map *st_ops_assoc;\n};\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n\t__u64 recursion_misses;\n\t__u32 verified_insns;\n\t__u32 attach_btf_obj_id;\n\t__u32 attach_btf_id;\n};\n\nstruct bpf_prog_kstats {\n\tu64 nsecs;\n\tu64 cnt;\n\tu64 misses;\n};\n\nstruct bpf_prog_list {\n\tstruct hlist_node node;\n\tstruct bpf_prog *prog;\n\tstruct bpf_cgroup_link *link;\n\tstruct bpf_cgroup_storage *storage[2];\n\tu32 flags;\n};\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_prog_pack {\n\tstruct list_head list;\n\tvoid *ptr;\n\tlong unsigned int bitmap[0];\n};\n\nstruct bpf_prog_stats {\n\tu64_stats_t cnt;\n\tu64_stats_t nsecs;\n\tu64_stats_t misses;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\trqspinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n};\n\nstruct tracepoint;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 64;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n\tu64 cookie;\n};\n\nstruct bpf_raw_tp_null_args {\n\tconst char *func;\n\tu64 mask;\n};\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\nstruct bpf_raw_tp_test_run_info {\n\tstruct bpf_prog *prog;\n\tvoid *ctx;\n\tu32 retval;\n};\n\nstruct bpf_rb_node {\n\t__u64 __opaque[4];\n};\n\nstruct bpf_rb_node_kern {\n\tstruct rb_node rb_node;\n\tvoid *owner;\n};\n\nstruct bpf_rb_root {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_redir_neigh {\n\t__u32 nh_family;\n\tunion {\n\t\t__be32 ipv4_nh;\n\t\t__u32 ipv6_nh[4];\n\t};\n};\n\nstruct bpf_refcount {\n\t__u32 __opaque[1];\n};\n\nstruct bpf_reference_state {\n\tenum ref_state_type type;\n\tint id;\n\tint insn_idx;\n\tvoid *ptr;\n};\n\nstruct bpf_reg_types {\n\tconst enum bpf_reg_type types[10];\n\tu32 *btf_id;\n};\n\nstruct bpf_res_spin_lock {\n\tu32 val;\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tbool overwrite_mode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\trqspinlock_t spinlock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t busy;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 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64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int consumer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 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64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 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64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int producer_pos;\n\tlong unsigned int pending_pos;\n\tlong unsigned int overwrite_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 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64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_ringbuf *rb;\n};\n\nstruct bpf_sanitize_info {\n\tstruct bpf_insn_aux_data aux;\n\tbool mask_to_left;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tstruct bpf_reference_state *refs;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 acquired_refs;\n\tu32 active_locks;\n\tu32 active_preempt_locks;\n\tu32 active_irq_id;\n\tu32 active_lock_id;\n\tvoid *active_lock_ptr;\n\tu32 active_rcu_locks;\n\tbool speculative;\n\tbool in_sleepable;\n\tbool cleaned;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_verifier_state *equal_state;\n\tstruct bpf_jmp_history_entry *jmp_history;\n\tu32 jmp_history_cnt;\n\tu32 dfs_depth;\n\tu32 callback_unroll_depth;\n\tu32 may_goto_depth;\n};\n\nstruct bpf_scc_backedge {\n\tstruct bpf_scc_backedge *next;\n\tstruct bpf_verifier_state state;\n};\n\nstruct bpf_scc_callchain {\n\tu32 callsites[7];\n\tu32 scc;\n};\n\nstruct bpf_scc_visit {\n\tstruct bpf_scc_callchain callchain;\n\tstruct bpf_verifier_state *entry_state;\n\tstruct bpf_scc_backedge *backedges;\n\tu32 num_backedges;\n};\n\nstruct bpf_scc_info {\n\tu32 num_visits;\n\tstruct bpf_scc_visit visits[0];\n};\n\nstruct bpf_security_struct {\n\tu32 sid;\n\tu32 perms;\n\tu32 grantor_sid;\n};\n\nstruct bpf_session_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tbool is_return;\n\tvoid *data;\n};\n\nstruct bpf_shim_tramp_link {\n\tstruct bpf_tramp_link link;\n\tstruct bpf_trampoline *trampoline;\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *stream_parser;\n\tstruct bpf_prog *stream_verdict;\n\tstruct bpf_prog *skb_verdict;\n\tstruct bpf_link *msg_parser_link;\n\tstruct bpf_link *stream_parser_link;\n\tstruct bpf_link *stream_verdict_link;\n\tstruct bpf_link *skb_verdict_link;\n};\n\nstruct bpf_shtab_bucket;\n\nstruct bpf_shtab {\n\tstruct bpf_map map;\n\tstruct bpf_shtab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n};\n\nstruct bpf_shtab_bucket {\n\tstruct hlist_head head;\n\tspinlock_t lock;\n};\n\nstruct bpf_shtab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct qdisc_skb_cb {\n\tunsigned int pkt_len;\n\tu16 pkt_segs;\n\tu16 tc_classid;\n\tunsigned char data[20];\n\tu16 slave_dev_queue_mapping;\n\tu8 post_ct: 1;\n\tu8 post_ct_snat: 1;\n\tu8 post_ct_dnat: 1;\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_sockopt_buf {\n\tu8 data[32];\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\tspinlock_t lock;\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nstruct stack_map_bucket;\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_storage_blob {\n\tstruct bpf_local_storage *storage;\n};\n\nstruct bpf_storage_buffer {\n\tstruct callback_head rcu;\n\tchar data[0];\n};\n\nstruct bpf_stream_elem {\n\tstruct llist_node node;\n\tint total_len;\n\tint consumed_len;\n\tchar str[0];\n};\n\nstruct bpf_stream_stage {\n\tstruct llist_head log;\n\tint len;\n};\n\nstruct bpf_verifier_ops;\n\nstruct btf_member;\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *, const struct bpf_prog *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *, struct bpf_link *);\n\tvoid (*unreg)(void *, struct bpf_link *);\n\tint (*update)(void *, void *, struct bpf_link *);\n\tint (*validate)(void *);\n\tvoid *cfi_stubs;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n};\n\nstruct bpf_struct_ops_arg_info {\n\tstruct bpf_ctx_arg_aux *info;\n\tu32 cnt;\n};\n\nstruct bpf_struct_ops_common_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n};\n\nstruct bpf_struct_ops_bpf_dummy_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_dummy_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_desc {\n\tstruct bpf_struct_ops *st_ops;\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tu32 type_id;\n\tu32 value_id;\n\tstruct bpf_struct_ops_arg_info *arg_info;\n};\n\nstruct bpf_struct_ops_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n\twait_queue_head_t wait_hup;\n};\n\nstruct bpf_struct_ops_value {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops_desc *st_ops_desc;\n\tstruct mutex lock;\n\tstruct bpf_link **links;\n\tstruct bpf_ksym **ksyms;\n\tu32 funcs_cnt;\n\tu32 image_pages_cnt;\n\tvoid *image_pages[8];\n\tstruct btf *btf;\n\tstruct bpf_struct_ops_value *uvalue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct scx_cpu_acquire_args;\n\nstruct scx_cpu_release_args;\n\nstruct scx_init_task_args;\n\nstruct scx_exit_task_args;\n\nstruct scx_dump_ctx;\n\nstruct scx_cgroup_init_args;\n\nstruct scx_sub_attach_args;\n\nstruct scx_sub_detach_args;\n\nstruct scx_exit_info;\n\nstruct sched_ext_ops {\n\ts32 (*select_cpu)(struct task_struct *, s32, u64);\n\tvoid (*enqueue)(struct task_struct *, u64);\n\tvoid (*dequeue)(struct task_struct *, u64);\n\tvoid (*dispatch)(s32, struct task_struct *);\n\tvoid (*tick)(struct task_struct *);\n\tvoid (*runnable)(struct task_struct *, u64);\n\tvoid (*running)(struct task_struct *);\n\tvoid (*stopping)(struct task_struct *, bool);\n\tvoid (*quiescent)(struct task_struct *, u64);\n\tbool (*yield)(struct task_struct *, struct task_struct *);\n\tbool (*core_sched_before)(struct task_struct *, struct task_struct *);\n\tvoid (*set_weight)(struct task_struct *, u32);\n\tvoid (*set_cpumask)(struct task_struct *, const struct cpumask *);\n\tvoid (*update_idle)(s32, bool);\n\tvoid (*cpu_acquire)(s32, struct scx_cpu_acquire_args *);\n\tvoid (*cpu_release)(s32, struct scx_cpu_release_args *);\n\ts32 (*init_task)(struct task_struct *, struct scx_init_task_args *);\n\tvoid (*exit_task)(struct task_struct *, struct scx_exit_task_args *);\n\tvoid (*enable)(struct task_struct *);\n\tvoid (*disable)(struct task_struct *);\n\tvoid (*dump)(struct scx_dump_ctx *);\n\tvoid (*dump_cpu)(struct scx_dump_ctx *, s32, bool);\n\tvoid (*dump_task)(struct scx_dump_ctx *, struct task_struct *);\n\ts32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *);\n\tvoid (*cgroup_exit)(struct cgroup *);\n\ts32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *);\n\tvoid (*cgroup_set_weight)(struct cgroup *, u32);\n\tvoid (*cgroup_set_bandwidth)(struct cgroup *, u64, u64, u64);\n\tvoid (*cgroup_set_idle)(struct cgroup *, bool);\n\ts32 (*sub_attach)(struct scx_sub_attach_args *);\n\tvoid (*sub_detach)(struct scx_sub_detach_args *);\n\tvoid (*cpu_online)(s32);\n\tvoid (*cpu_offline)(s32);\n\ts32 (*init)(void);\n\tvoid (*exit)(struct scx_exit_info *);\n\tu32 dispatch_max_batch;\n\tu64 flags;\n\tu32 timeout_ms;\n\tu32 exit_dump_len;\n\tu64 hotplug_seq;\n\tu64 sub_cgroup_id;\n\tchar name[128];\n\tvoid *priv;\n};\n\nstruct bpf_struct_ops_sched_ext_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_ext_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*cong_control)(struct sock *, u32, int, const struct rate_sample *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*undo_cwnd)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\tstruct bpf_struct_ops_common_value common;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tcp_congestion_ops data;\n};\n\nstruct bpf_subprog_arg_info {\n\tenum bpf_arg_type arg_type;\n\tunion {\n\t\tu32 mem_size;\n\t\tu32 btf_id;\n\t};\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu32 postorder_start;\n\tu32 exit_idx;\n\tu16 stack_depth;\n\tu16 stack_extra;\n\ts16 fastcall_stack_off;\n\tbool has_tail_call: 1;\n\tbool tail_call_reachable: 1;\n\tbool has_ld_abs: 1;\n\tbool is_cb: 1;\n\tbool is_async_cb: 1;\n\tbool is_exception_cb: 1;\n\tbool args_cached: 1;\n\tbool keep_fastcall_stack: 1;\n\tbool changes_pkt_data: 1;\n\tbool might_sleep: 1;\n\tu8 arg_cnt: 3;\n\tenum priv_stack_mode priv_stack_mode;\n\tstruct bpf_subprog_arg_info args[5];\n};\n\nstruct bpf_task_work {\n\t__u64 __opaque;\n};\n\ntypedef int (*bpf_task_work_callback_t)(struct bpf_map *, void *, void *);\n\nstruct bpf_task_work_ctx {\n\tenum bpf_task_work_state state;\n\trefcount_t refcnt;\n\tstruct callback_head work;\n\tstruct irq_work irq_work;\n\tstruct bpf_prog *prog;\n\tstruct task_struct *task;\n\tstruct bpf_map *map;\n\tvoid *map_val;\n\tenum task_work_notify_mode mode;\n\tbpf_task_work_callback_t callback_fn;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_task_work_kern {\n\tstruct bpf_task_work_ctx *ctx;\n};\n\nunion bpf_tcp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tloff_t last_pos;\n};\n\nstruct bpf_tcp_iter_state {\n\tstruct tcp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_tcp_iter_batch_item *batch;\n};\n\nstruct bpf_tcp_req_attrs {\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 mss;\n\tu8 rcv_wscale;\n\tu8 snd_wscale;\n\tu8 ecn_ok;\n\tu8 wscale_ok;\n\tu8 sack_ok;\n\tu8 tstamp_ok;\n\tu8 usec_ts_ok;\n\tu8 reserved[3];\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_test_timer {\n\tu32 i;\n\tu64 time_start;\n\tu64 time_spent;\n};\n\nstruct bpf_throw_ctx {\n\tstruct bpf_prog_aux *aux;\n\tu64 sp;\n\tu64 bp;\n\tint cnt;\n};\n\nstruct bpf_timed_may_goto {\n\tu64 count;\n\tu64 timestamp;\n};\n\nstruct bpf_timer {\n\t__u64 __opaque[2];\n};\n\nstruct user_namespace;\n\nstruct bpf_token {\n\tstruct work_struct work;\n\tatomic64_t refcnt;\n\tstruct user_namespace *userns;\n\tu64 allowed_cmds;\n\tu64 allowed_maps;\n\tu64 allowed_progs;\n\tu64 allowed_attachs;\n\tvoid *security;\n};\n\nstruct bpf_token_info {\n\t__u64 allowed_cmds;\n\t__u64 allowed_maps;\n\t__u64 allowed_progs;\n\t__u64 allowed_attachs;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct bpf_trace_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tbool is_uprobe;\n};\n\nunion perf_sample_weight {\n\t__u64 full;\n\tstruct {\n\t\t__u32 var1_dw;\n\t\t__u16 var2_w;\n\t\t__u16 var3_w;\n\t};\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_op: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_blk: 3;\n\t\t__u64 mem_hops: 3;\n\t\t__u64 mem_region: 5;\n\t\t__u64 mem_rsvd: 13;\n\t};\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n};\n\nstruct perf_callchain_entry;\n\nstruct perf_raw_record;\n\nstruct perf_branch_stack;\n\nstruct perf_sample_data {\n\tu64 sample_flags;\n\tu64 period;\n\tu64 dyn_size;\n\tu64 type;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tu64 ip;\n\tstruct perf_callchain_entry *callchain;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 *br_stack_cntr;\n\tunion perf_sample_weight weight;\n\tunion perf_mem_data_src data_src;\n\tu64 txn;\n\tstruct perf_regs regs_user;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 stream_id;\n\tu64 cgroup;\n\tu64 addr;\n\tu64 phys_addr;\n\tu64 data_page_size;\n\tu64 code_page_size;\n\tu64 aux_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\nstruct bpf_tramp_image {\n\tvoid *image;\n\tint size;\n\tstruct bpf_ksym ksym;\n\tstruct percpu_ref pcref;\n\tvoid *ip_after_call;\n\tvoid *ip_epilogue;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n};\n\nstruct bpf_tramp_links {\n\tstruct bpf_tramp_link *links[38];\n\tint nr_links;\n};\n\nstruct bpf_tramp_run_ctx {\n\tstruct bpf_run_ctx run_ctx;\n\tu64 bpf_cookie;\n\tstruct bpf_run_ctx *saved_run_ctx;\n};\n\nstruct ftrace_ops;\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist_key;\n\tstruct hlist_node hlist_ip;\n\tstruct ftrace_ops *fops;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu32 flags;\n\tu64 key;\n\tlong unsigned int ip;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tstruct bpf_tramp_image *cur_image;\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\tunion {\n\t\t__u16 tunnel_ext;\n\t\t__be16 tunnel_flags;\n\t};\n\t__u32 tunnel_label;\n\tunion {\n\t\t__u32 local_ipv4;\n\t\t__u32 local_ipv6[4];\n\t};\n};\n\nstruct bpf_tuple {\n\tstruct bpf_prog *prog;\n\tstruct bpf_link *link;\n};\n\nunion bpf_udp_iter_batch_item {\n\tstruct sock *sk;\n\t__u64 cookie;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct bpf_udp_iter_state {\n\tstruct udp_iter_state state;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tunion bpf_udp_iter_batch_item *batch;\n};\n\nstruct bpf_unix_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int cur_sk;\n\tunsigned int end_sk;\n\tunsigned int max_sk;\n\tstruct sock **batch;\n\tbool st_bucket_done;\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *, __u64 *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *, __u64 *);\n\tbool (*filter)(struct uprobe_consumer *, struct mm_struct *);\n\tstruct list_head cons_node;\n\t__u64 id;\n};\n\nstruct bpf_uprobe_multi_link;\n\nstruct uprobe;\n\nstruct bpf_uprobe {\n\tstruct bpf_uprobe_multi_link *link;\n\tloff_t offset;\n\tlong unsigned int ref_ctr_offset;\n\tu64 cookie;\n\tstruct uprobe *uprobe;\n\tstruct uprobe_consumer consumer;\n\tbool session;\n};\n\nstruct bpf_uprobe_multi_link {\n\tstruct path path;\n\tstruct bpf_link link;\n\tu32 cnt;\n\tstruct bpf_uprobe *uprobes;\n\tstruct task_struct *task;\n};\n\nstruct bpf_uprobe_multi_run_ctx {\n\tstruct bpf_session_run_ctx session_ctx;\n\tlong unsigned int entry_ip;\n\tstruct bpf_uprobe *uprobe;\n};\n\nstruct btf_mod_pair {\n\tstruct btf *btf;\n\tstruct module *module;\n};\n\nstruct bpf_verifier_log {\n\tu64 start_pos;\n\tu64 end_pos;\n\tchar *ubuf;\n\tu32 level;\n\tu32 len_total;\n\tu32 len_max;\n\tchar kbuf[1024];\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct module *attach_btf_mod;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tbool test_reg_invariants;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct list_head *explored_states;\n\tstruct list_head free_list;\n\tstruct bpf_map *used_maps[64];\n\tstruct btf_mod_pair used_btfs[64];\n\tstruct bpf_map *insn_array_maps[64];\n\tu32 used_map_cnt;\n\tu32 used_btf_cnt;\n\tu32 insn_array_map_cnt;\n\tu32 id_gen;\n\tu32 hidden_subprog_cnt;\n\tint exception_callback_subprog;\n\tbool explore_alu_limits;\n\tbool allow_ptr_leaks;\n\tbool allow_uninit_stack;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tbool seen_exception;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[258];\n\tunion {\n\t\tstruct bpf_idmap idmap_scratch;\n\t\tstruct bpf_idset idset_scratch;\n\t};\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint *insn_postorder;\n\t\tint cur_stack;\n\t\tint cur_postorder;\n\t} cfg;\n\tstruct backtrack_state bt;\n\tstruct bpf_jmp_history_entry *cur_hist_ent;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n\tu32 free_list_size;\n\tu32 explored_states_size;\n\tu32 num_backedges;\n\tbpfptr_t fd_array;\n\tu32 scratched_regs;\n\tu64 scratched_stack_slots;\n\tu64 prev_log_pos;\n\tu64 prev_insn_print_pos;\n\tstruct bpf_reg_state fake_reg[2];\n\tchar tmp_str_buf[320];\n\tstruct bpf_insn insn_buf[32];\n\tstruct bpf_insn epilogue_buf[32];\n\tstruct bpf_scc_callchain callchain_buf;\n\tstruct bpf_liveness *liveness;\n\tstruct bpf_scc_info **scc_info;\n\tu32 scc_cnt;\n\tstruct bpf_iarray *succ;\n\tstruct bpf_iarray *gotox_tmp_buf;\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_epilogue)(struct bpf_insn *, const struct bpf_prog *, s16);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct bpf_reg_state *, int, int);\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct list_head node;\n\tu32 miss_cnt;\n\tu32 hit_cnt: 31;\n\tu32 in_free_list: 1;\n};\n\nstruct bpf_work {\n\tstruct bpf_async_cb cb;\n\tstruct work_struct work;\n};\n\nstruct bpf_wq {\n\t__u64 __opaque[2];\n};\n\nstruct bpf_xdp_link;\n\nstruct bpf_xdp_entity {\n\tstruct bpf_prog *prog;\n\tstruct bpf_xdp_link *link;\n};\n\nstruct bpf_xdp_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n\tint flags;\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nstruct bpf_xfrm_state {\n\t__u32 reqid;\n\t__u32 spi;\n\t__u16 family;\n\t__u16 ext;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n};\n\nstruct bpf_xfrm_state_opts {\n\ts32 error;\n\ts32 netns_id;\n\tu32 mark;\n\txfrm_address_t daddr;\n\t__be32 spi;\n\tu8 proto;\n\tu16 family;\n};\n\nstruct bpffs_btf_enums {\n\tconst struct btf *btf;\n\tconst struct btf_type *cmd_t;\n\tconst struct btf_type *map_t;\n\tconst struct btf_type *prog_t;\n\tconst struct btf_type *attach_t;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct bpt {\n\tlong unsigned int address;\n\tu32 *instr;\n\tatomic_t ref_count;\n\tint enabled;\n\tlong unsigned int pad;\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nstruct br_input_skb_cb {\n\tstruct net_device *brdev;\n\tu16 frag_max_size;\n\tu8 igmp;\n\tu8 mrouters_only: 1;\n\tu8 proxyarp_replied: 1;\n\tu8 src_port_isolated: 1;\n\tu8 promisc: 1;\n\tu32 backup_nhid;\n};\n\nstruct br_ip {\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t} src;\n\tunion {\n\t\t__be32 ip4;\n\t\tstruct in6_addr ip6;\n\t\tunsigned char mac_addr[6];\n\t} dst;\n\t__be16 proto;\n\t__u16 vid;\n};\n\nstruct br_mcast_stats {\n\t__u64 igmp_v1queries[2];\n\t__u64 igmp_v2queries[2];\n\t__u64 igmp_v3queries[2];\n\t__u64 igmp_leaves[2];\n\t__u64 igmp_v1reports[2];\n\t__u64 igmp_v2reports[2];\n\t__u64 igmp_v3reports[2];\n\t__u64 igmp_parse_errors;\n\t__u64 mld_v1queries[2];\n\t__u64 mld_v2queries[2];\n\t__u64 mld_leaves[2];\n\t__u64 mld_v1reports[2];\n\t__u64 mld_v2reports[2];\n\t__u64 mld_parse_errors;\n\t__u64 mcast_bytes[2];\n\t__u64 mcast_packets[2];\n};\n\nstruct br_mdb_entry {\n\t__u32 ifindex;\n\t__u8 state;\n\t__u8 flags;\n\t__u16 vid;\n\tstruct {\n\t\tunion {\n\t\t\t__be32 ip4;\n\t\t\tstruct in6_addr ip6;\n\t\t\tunsigned char mac_addr[6];\n\t\t} u;\n\t\t__be16 proto;\n\t} addr;\n};\n\nstruct br_port_msg {\n\t__u8 family;\n\t__u32 ifindex;\n};\n\nstruct metadata_dst;\n\nstruct br_tunnel_info {\n\t__be64 tunnel_id;\n\tstruct metadata_dst *tunnel_dst;\n};\n\nstruct brd_device {\n\tint brd_number;\n\tstruct gendisk *brd_disk;\n\tstruct list_head brd_list;\n\tstruct xarray brd_pages;\n\tu64 brd_nr_pages;\n};\n\nstruct bridge_id {\n\tunsigned char prio[2];\n\tunsigned char addr[6];\n};\n\ntypedef struct bridge_id bridge_id;\n\nstruct bridge_mcast_other_query {\n\tstruct timer_list timer;\n\tstruct timer_list delay_timer;\n};\n\nstruct bridge_mcast_own_query {\n\tstruct timer_list timer;\n\tu32 startup_sent;\n};\n\nstruct bridge_mcast_querier {\n\tstruct br_ip addr;\n\tint port_ifidx;\n\tseqcount_spinlock_t seq;\n};\n\nstruct bridge_mcast_stats {\n\tstruct br_mcast_stats mstats;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct bridge_stp_xstats {\n\t__u64 transition_blk;\n\t__u64 transition_fwd;\n\t__u64 rx_bpdu;\n\t__u64 tx_bpdu;\n\t__u64 rx_tcn;\n\t__u64 tx_tcn;\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\nstruct broken_edid {\n\tu8 manufacturer[4];\n\tu32 model;\n\tu32 fix;\n};\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct bsd_acct_struct {\n\tstruct fs_pin pin;\n\tatomic_long_t count;\n\tstruct callback_head rcu;\n\tstruct mutex lock;\n\tbool active;\n\tbool check_space;\n\tlong unsigned int needcheck;\n\tstruct file *file;\n\tstruct pid_namespace *ns;\n\tstruct work_struct work;\n\tstruct completion done;\n\tacct_t ac;\n};\n\nstruct bsg_buffer {\n\tunsigned int payload_len;\n\tint sg_cnt;\n\tstruct scatterlist *sg_list;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct sg_io_v4;\n\ntypedef int bsg_sg_io_fn(struct request_queue *, struct sg_io_v4 *, bool, unsigned int);\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tstruct device device;\n\tstruct cdev cdev;\n\tint max_queue;\n\tunsigned int timeout;\n\tunsigned int reserved_size;\n\tbsg_sg_io_fn *sg_io_fn;\n};\n\nstruct bsg_job {\n\tstruct device *dev;\n\tstruct kref kref;\n\tunsigned int timeout;\n\tvoid *request;\n\tvoid *reply;\n\tunsigned int request_len;\n\tunsigned int reply_len;\n\tstruct bsg_buffer request_payload;\n\tstruct bsg_buffer reply_payload;\n\tint result;\n\tunsigned int reply_payload_rcv_len;\n\tstruct request *bidi_rq;\n\tstruct bio *bidi_bio;\n\tvoid *dd_data;\n};\n\ntypedef int bsg_job_fn(struct bsg_job *);\n\ntypedef enum blk_eh_timer_return bsg_timeout_fn(struct request *);\n\nstruct bsg_set {\n\tstruct blk_mq_tag_set tag_set;\n\tstruct bsg_device *bd;\n\tbsg_job_fn *job_fn;\n\tbsg_timeout_fn *timeout_fn;\n};\n\ntypedef bool busy_tag_iter_fn(struct request *, void *);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request_queue *q;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf_kfunc_set_tab;\n\nstruct btf_id_dtor_kfunc_tab;\n\nstruct btf_struct_metas;\n\nstruct btf_struct_ops_tab;\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 named_start_id;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n\tstruct btf_kfunc_set_tab *kfunc_set_tab;\n\tstruct btf_id_dtor_kfunc_tab *dtor_kfunc_tab;\n\tstruct btf_struct_metas *struct_meta_tab;\n\tstruct btf_struct_ops_tab *struct_ops_tab;\n\tstruct btf *base_btf;\n\tu32 start_id;\n\tu32 start_str_off;\n\tchar name[56];\n\tbool kernel_btf;\n\t__u32 *base_id_map;\n};\n\nstruct btf_anon_stack {\n\tu32 tid;\n\tu32 offset;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_decl_tag {\n\t__s32 component_idx;\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_enum64 {\n\t__u32 name_off;\n\t__u32 val_lo32;\n\t__u32 val_hi32;\n};\n\ntypedef void (*btf_dtor_kfunc_t)(void *);\n\nstruct btf_field_kptr {\n\tstruct btf *btf;\n\tstruct module *module;\n\tbtf_dtor_kfunc_t dtor;\n\tu32 btf_id;\n};\n\nstruct btf_field_graph_root {\n\tstruct btf *btf;\n\tu32 value_btf_id;\n\tu32 node_offset;\n\tstruct btf_record *value_rec;\n};\n\nstruct btf_field {\n\tu32 offset;\n\tu32 size;\n\tenum btf_field_type type;\n\tunion {\n\t\tstruct btf_field_kptr kptr;\n\t\tstruct btf_field_graph_root graph_root;\n\t};\n};\n\nstruct btf_field_desc {\n\tint t_off_cnt;\n\tint t_offs[2];\n\tint m_sz;\n\tint m_off_cnt;\n\tint m_offs[1];\n};\n\nstruct btf_field_info {\n\tenum btf_field_type type;\n\tu32 off;\n\tunion {\n\t\tstruct {\n\t\t\tu32 type_id;\n\t\t} kptr;\n\t\tstruct {\n\t\t\tconst char *node_name;\n\t\t\tu32 value_btf_id;\n\t\t} graph_root;\n\t};\n};\n\nstruct btf_field_iter {\n\tstruct btf_field_desc desc;\n\tvoid *p;\n\tint m_idx;\n\tint off_idx;\n\tint vlen;\n};\n\nstruct btf_id_dtor_kfunc {\n\tu32 btf_id;\n\tu32 kfunc_btf_id;\n};\n\nstruct btf_id_dtor_kfunc_tab {\n\tu32 cnt;\n\tstruct btf_id_dtor_kfunc dtors[0];\n};\n\nstruct btf_id_set {\n\tu32 cnt;\n\tu32 ids[0];\n};\n\nstruct btf_id_set8 {\n\tu32 cnt;\n\tu32 flags;\n\tstruct {\n\t\tu32 id;\n\t\tu32 flags;\n\t} pairs[0];\n};\n\ntypedef int (*btf_kfunc_filter_t)(const struct bpf_prog *, u32);\n\nstruct btf_kfunc_hook_filter {\n\tbtf_kfunc_filter_t filters[16];\n\tu32 nr_filters;\n};\n\nstruct btf_kfunc_id_set {\n\tstruct module *owner;\n\tstruct btf_id_set8 *set;\n\tbtf_kfunc_filter_t filter;\n};\n\nstruct btf_kfunc_set_tab {\n\tstruct btf_id_set8 *sets[14];\n\tstruct btf_kfunc_hook_filter hook_filters[14];\n};\n\nstruct btf_verifier_env;\n\nstruct resolve_vertex;\n\nstruct btf_show;\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct btf_show *);\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nstruct btf_module {\n\tstruct list_head list;\n\tstruct module *module;\n\tstruct btf *btf;\n\tstruct bin_attribute *sysfs_attr;\n\tint flags;\n};\n\nstruct btf_name_info {\n\tconst char *name;\n\tbool needs_size: 1;\n\tunsigned int size: 31;\n\t__u32 id;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nstruct btf_ptr {\n\tvoid *ptr;\n\t__u32 type_id;\n\t__u32 flags;\n};\n\nstruct btf_record {\n\tu32 cnt;\n\tu32 field_mask;\n\tint spin_lock_off;\n\tint res_spin_lock_off;\n\tint timer_off;\n\tint wq_off;\n\tint refcount_off;\n\tint task_work_off;\n\tstruct btf_field fields[0];\n};\n\nstruct btf_relocate {\n\tstruct btf *btf;\n\tconst struct btf *base_btf;\n\tconst struct btf *dist_base_btf;\n\tunsigned int nr_base_types;\n\tunsigned int nr_split_types;\n\tunsigned int nr_dist_base_types;\n\tint dist_str_len;\n\tint base_str_len;\n\t__u32 *id_map;\n\t__u32 *str_map;\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\nstruct btf_show {\n\tu64 flags;\n\tvoid *target;\n\tvoid (*showfn)(struct btf_show *, const char *, va_list);\n\tconst struct btf *btf;\n\tstruct {\n\t\tu8 depth;\n\t\tu8 depth_to_show;\n\t\tu8 depth_check;\n\t\tu8 array_member: 1;\n\t\tu8 array_terminated: 1;\n\t\tu16 array_encoding;\n\t\tu32 type_id;\n\t\tint status;\n\t\tconst struct btf_type *type;\n\t\tconst struct btf_member *member;\n\t\tchar name[80];\n\t} state;\n\tstruct {\n\t\tu32 size;\n\t\tvoid *head;\n\t\tvoid *data;\n\t\tu8 safe[32];\n\t} obj;\n};\n\nstruct btf_show_snprintf {\n\tstruct btf_show show;\n\tint len_left;\n\tint len;\n};\n\nstruct btf_struct_meta {\n\tu32 btf_id;\n\tstruct btf_record *record;\n};\n\nstruct btf_struct_metas {\n\tu32 cnt;\n\tstruct btf_struct_meta types[0];\n};\n\nstruct btf_struct_ops_tab {\n\tu32 cnt;\n\tu32 capacity;\n\tstruct bpf_struct_ops_desc ops[0];\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct btree_geo {\n\tint keylen;\n\tint no_pairs;\n\tint no_longs;\n};\n\nstruct btree_head {\n\tlong unsigned int *node;\n\tmempool_t *mempool;\n\tint height;\n};\n\nstruct nd_region;\n\nstruct btt {\n\tstruct gendisk *btt_disk;\n\tstruct list_head arena_list;\n\tstruct dentry *debugfs_dir;\n\tstruct nd_btt *nd_btt;\n\tu64 nlba;\n\tlong long unsigned int rawsize;\n\tu32 lbasize;\n\tu32 sector_size;\n\tstruct nd_region *nd_region;\n\tstruct mutex init_lock;\n\tint init_state;\n\tint num_arenas;\n\tstruct badblocks *phys_bb;\n};\n\nstruct btt_sb {\n\tu8 signature[16];\n\tu8 uuid[16];\n\tu8 parent_uuid[16];\n\t__le32 flags;\n\t__le16 version_major;\n\t__le16 version_minor;\n\t__le32 external_lbasize;\n\t__le32 external_nlba;\n\t__le32 internal_lbasize;\n\t__le32 internal_nlba;\n\t__le32 nfree;\n\t__le32 infosize;\n\t__le64 nextoff;\n\t__le64 dataoff;\n\t__le64 mapoff;\n\t__le64 logoff;\n\t__le64 info2off;\n\tu8 padding[3968];\n\t__le64 checksum;\n};\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\trqspinlock_t raw_lock;\n};\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nstruct buf_sel_arg {\n\tstruct iovec *iovs;\n\tsize_t out_len;\n\tsize_t max_len;\n\tshort unsigned int nr_iovs;\n\tshort unsigned int mode;\n\tshort unsigned int buf_group;\n\tshort unsigned int partial_map;\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n};\n\nstruct buffer_data_read_page {\n\tunsigned int order;\n\tstruct buffer_data_page *data;\n};\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tunion {\n\t\tstruct page *b_page;\n\t\tstruct folio *b_folio;\n\t};\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tunsigned int order;\n\tu32 id: 30;\n\tu32 range: 1;\n\tstruct buffer_data_page *page;\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct bug_entry {\n\tint bug_addr_disp;\n\tint file_disp;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct bus_type *, char *);\n\tssize_t (*store)(const struct bus_type *, const char *, size_t);\n};\n\nstruct bus_dma_region {\n\tphys_addr_t cpu_start;\n\tdma_addr_t dma_start;\n\tu64 size;\n};\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, const struct device_driver *);\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tconst struct cpumask * (*irq_get_affinity)(struct device *, unsigned int);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tvoid (*dma_cleanup)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tbool need_parent_lock;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct cache {\n\tstruct device_node *ofnode;\n\tstruct cpumask shared_cpu_map;\n\tint type;\n\tint level;\n\tint group_id;\n\tstruct list_head list;\n\tstruct cache *next_local;\n};\n\nstruct cache_head;\n\nstruct cache_deferred_req {\n\tstruct hlist_node hash;\n\tstruct list_head recent;\n\tstruct cache_head *item;\n\tvoid *owner;\n\tvoid (*revisit)(struct cache_deferred_req *, int);\n};\n\nstruct proc_dir_entry;\n\nstruct cache_detail {\n\tstruct module *owner;\n\tint hash_size;\n\tstruct hlist_head *hash_table;\n\tspinlock_t hash_lock;\n\tchar *name;\n\tvoid (*cache_put)(struct kref *);\n\tint (*cache_upcall)(struct cache_detail *, struct cache_head *);\n\tvoid (*cache_request)(struct cache_detail *, struct cache_head *, char **, int *);\n\tint (*cache_parse)(struct cache_detail *, char *, int);\n\tint (*cache_show)(struct seq_file *, struct cache_detail *, struct cache_head *);\n\tvoid (*warn_no_listener)(struct cache_detail *, int);\n\tstruct cache_head * (*alloc)(void);\n\tvoid (*flush)(void);\n\tint (*match)(struct cache_head *, struct cache_head *);\n\tvoid (*init)(struct cache_head *, struct cache_head *);\n\tvoid (*update)(struct cache_head *, struct cache_head *);\n\ttime64_t flush_time;\n\tstruct list_head others;\n\ttime64_t nextcheck;\n\tint entries;\n\tstruct list_head queue;\n\tatomic_t writers;\n\ttime64_t last_close;\n\ttime64_t last_warn;\n\tunion {\n\t\tstruct proc_dir_entry *procfs;\n\t\tstruct dentry *pipefs;\n\t};\n\tstruct net *net;\n};\n\nstruct cache_index_dir;\n\nstruct cache_dir {\n\tstruct kobject *kobj;\n\tstruct cache_index_dir *index;\n};\n\nstruct cache_head {\n\tstruct hlist_node cache_list;\n\ttime64_t expiry_time;\n\ttime64_t last_refresh;\n\tstruct kref ref;\n\tlong unsigned int flags;\n};\n\nstruct cache_index_dir {\n\tstruct kobject kobj;\n\tstruct cache_index_dir *next;\n\tstruct cache *cache;\n};\n\nstruct cache_queue {\n\tstruct list_head list;\n\tint reader;\n};\n\nstruct cache_reader {\n\tstruct cache_queue q;\n\tint offset;\n};\n\nstruct cache_req {\n\tstruct cache_deferred_req * (*defer)(struct cache_req *);\n\tlong unsigned int thread_wait;\n};\n\nstruct cache_request {\n\tstruct cache_queue q;\n\tstruct cache_head *item;\n\tchar *buf;\n\tint len;\n\tint readers;\n};\n\nstruct cache_type_info {\n\tconst char *name;\n\tconst char *size_prop;\n\tconst char *line_size_props[2];\n\tconst char *nr_sets_prop;\n};\n\nstruct cache_type_info___2 {\n\tconst char *size_prop;\n\tconst char *line_size_props[2];\n\tconst char *nr_sets_prop;\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cacheline_padding {\n\tchar x[0];\n};\n\nstruct cachestat {\n\t__u64 nr_cache;\n\t__u64 nr_dirty;\n\t__u64 nr_writeback;\n\t__u64 nr_evicted;\n\t__u64 nr_recently_evicted;\n};\n\nstruct cachestat_range {\n\t__u64 off;\n\t__u64 len;\n};\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct call_summary {\n\tu8 num_params;\n\tbool is_void;\n\tbool fastcall;\n};\n\nstruct cb_process_state;\n\nstruct xdr_stream;\n\nstruct callback_op {\n\t__be32 (*process_op)(void *, void *, struct cb_process_state *);\n\t__be32 (*decode_args)(struct svc_rqst *, struct xdr_stream *, void *);\n\t__be32 (*encode_res)(struct svc_rqst *, struct xdr_stream *, const void *);\n\tlong int res_maxsize;\n};\n\nstruct callchain {\n\tu32 callsites[8];\n\tu32 sp_starts[8];\n\tu32 curframe;\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nstruct mad_capability_common {\n\t__be32 cap_type;\n\t__be16 length;\n\t__be16 server_support;\n};\n\nstruct mad_migration_cap {\n\tstruct mad_capability_common common;\n\t__be32 ecl;\n};\n\nstruct mad_reserve_cap {\n\tstruct mad_capability_common common;\n\t__be32 type;\n};\n\nstruct capabilities {\n\t__be32 flags;\n\tchar name[32];\n\tchar loc[32];\n\tstruct mad_migration_cap migration;\n\tstruct mad_reserve_cap reserve;\n};\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct cardinfo {\n\tint refclk_ps;\n\tconst char *cardname;\n};\n\nstruct cat_datum {\n\tu32 value;\n\tunsigned char isalias;\n};\n\nstruct config {\n\tu8 byte_count: 6;\n\tu8 pad0: 2;\n\tu8 rx_fifo_limit: 4;\n\tu8 tx_fifo_limit: 3;\n\tu8 pad1: 1;\n\tu8 adaptive_ifs;\n\tu8 mwi_enable: 1;\n\tu8 type_enable: 1;\n\tu8 read_align_enable: 1;\n\tu8 term_write_cache_line: 1;\n\tu8 pad3: 4;\n\tu8 rx_dma_max_count: 7;\n\tu8 pad4: 1;\n\tu8 tx_dma_max_count: 7;\n\tu8 dma_max_count_enable: 1;\n\tu8 late_scb_update: 1;\n\tu8 direct_rx_dma: 1;\n\tu8 tno_intr: 1;\n\tu8 cna_intr: 1;\n\tu8 standard_tcb: 1;\n\tu8 standard_stat_counter: 1;\n\tu8 rx_save_overruns: 1;\n\tu8 rx_save_bad_frames: 1;\n\tu8 rx_discard_short_frames: 1;\n\tu8 tx_underrun_retry: 2;\n\tu8 pad7: 2;\n\tu8 rx_extended_rfd: 1;\n\tu8 tx_two_frames_in_fifo: 1;\n\tu8 tx_dynamic_tbd: 1;\n\tu8 mii_mode: 1;\n\tu8 pad8: 6;\n\tu8 csma_disabled: 1;\n\tu8 rx_tcpudp_checksum: 1;\n\tu8 pad9: 3;\n\tu8 vlan_arp_tco: 1;\n\tu8 link_status_wake: 1;\n\tu8 arp_wake: 1;\n\tu8 mcmatch_wake: 1;\n\tu8 pad10: 3;\n\tu8 no_source_addr_insertion: 1;\n\tu8 preamble_length: 2;\n\tu8 loopback: 2;\n\tu8 linear_priority: 3;\n\tu8 pad11: 5;\n\tu8 linear_priority_mode: 1;\n\tu8 pad12: 3;\n\tu8 ifs: 4;\n\tu8 ip_addr_lo;\n\tu8 ip_addr_hi;\n\tu8 promiscuous_mode: 1;\n\tu8 broadcast_disabled: 1;\n\tu8 wait_after_win: 1;\n\tu8 pad15_1: 1;\n\tu8 ignore_ul_bit: 1;\n\tu8 crc_16_bit: 1;\n\tu8 pad15_2: 1;\n\tu8 crs_or_cdt: 1;\n\tu8 fc_delay_lo;\n\tu8 fc_delay_hi;\n\tu8 rx_stripping: 1;\n\tu8 tx_padding: 1;\n\tu8 rx_crc_transfer: 1;\n\tu8 rx_long_ok: 1;\n\tu8 fc_priority_threshold: 3;\n\tu8 pad18: 1;\n\tu8 addr_wake: 1;\n\tu8 magic_packet_disable: 1;\n\tu8 fc_disable: 1;\n\tu8 fc_restop: 1;\n\tu8 fc_restart: 1;\n\tu8 fc_reject: 1;\n\tu8 full_duplex_force: 1;\n\tu8 full_duplex_pin: 1;\n\tu8 pad20_1: 5;\n\tu8 fc_priority_location: 1;\n\tu8 multi_ia: 1;\n\tu8 pad20_2: 1;\n\tu8 pad21_1: 3;\n\tu8 multicast_all: 1;\n\tu8 pad21_2: 4;\n\tu8 rx_d102_mode: 1;\n\tu8 rx_vlan_drop: 1;\n\tu8 pad22: 6;\n\tu8 pad_d102[9];\n};\n\nstruct multi {\n\t__le16 count;\n\tu8 addr[386];\n};\n\nstruct cb {\n\t__le16 status;\n\t__le16 command;\n\t__le32 link;\n\tunion {\n\t\tu8 iaaddr[6];\n\t\t__le32 ucode[134];\n\t\tstruct config config;\n\t\tstruct multi multi;\n\t\tstruct {\n\t\t\tu32 tbd_array;\n\t\t\tu16 tcb_byte_count;\n\t\t\tu8 threshold;\n\t\t\tu8 tbd_count;\n\t\t\tstruct {\n\t\t\t\t__le32 buf_addr;\n\t\t\t\t__le16 size;\n\t\t\t\tu16 eol;\n\t\t\t} tbd;\n\t\t} tcb;\n\t\t__le32 dump_buffer_addr;\n\t} u;\n\tstruct cb *next;\n\tstruct cb *prev;\n\tdma_addr_t dma_addr;\n\tstruct sk_buff *skb;\n};\n\nstruct cb_compound_hdr_arg {\n\tunsigned int taglen;\n\tconst char *tag;\n\tunsigned int minorversion;\n\tunsigned int cb_ident;\n\tunsigned int nops;\n};\n\nstruct cb_compound_hdr_res {\n\t__be32 *status;\n\tunsigned int taglen;\n\tconst char *tag;\n\t__be32 *nops;\n};\n\nstruct cb_devicenotifyitem;\n\nstruct cb_devicenotifyargs {\n\tuint32_t ndevs;\n\tstruct cb_devicenotifyitem *devs;\n};\n\nstruct nfs4_deviceid {\n\tchar data[16];\n};\n\nstruct cb_devicenotifyitem {\n\tuint32_t cbd_notify_type;\n\tuint32_t cbd_layout_type;\n\tstruct nfs4_deviceid cbd_dev_id;\n\tuint32_t cbd_immediate;\n};\n\nstruct nfs_fh {\n\tshort unsigned int size;\n\tunsigned char data[128];\n};\n\nstruct cb_getattrargs {\n\tstruct nfs_fh fh;\n\tuint32_t bitmap[3];\n};\n\nstruct cb_getattrres {\n\t__be32 status;\n\tuint32_t bitmap[3];\n\tuint64_t size;\n\tuint64_t change_attr;\n\tstruct timespec64 atime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 mtime;\n};\n\nstruct pnfs_layout_range {\n\tu32 iomode;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct nfs4_stateid_struct {\n\tunion {\n\t\tchar data[16];\n\t\tstruct {\n\t\t\t__be32 seqid;\n\t\t\tchar other[12];\n\t\t};\n\t};\n\tenum {\n\t\tNFS4_INVALID_STATEID_TYPE = 0,\n\t\tNFS4_SPECIAL_STATEID_TYPE = 1,\n\t\tNFS4_OPEN_STATEID_TYPE = 2,\n\t\tNFS4_LOCK_STATEID_TYPE = 3,\n\t\tNFS4_DELEGATION_STATEID_TYPE = 4,\n\t\tNFS4_LAYOUT_STATEID_TYPE = 5,\n\t\tNFS4_PNFS_DS_STATEID_TYPE = 6,\n\t\tNFS4_REVOKED_STATEID_TYPE = 7,\n\t\tNFS4_FREED_STATEID_TYPE = 8,\n\t} type;\n};\n\ntypedef struct nfs4_stateid_struct nfs4_stateid;\n\nstruct nfs_fsid {\n\tuint64_t major;\n\tuint64_t minor;\n};\n\nstruct cb_layoutrecallargs {\n\tuint32_t cbl_recall_type;\n\tuint32_t cbl_layout_type;\n\tuint32_t cbl_layoutchanged;\n\tunion {\n\t\tstruct {\n\t\t\tstruct nfs_fh cbl_fh;\n\t\t\tstruct pnfs_layout_range cbl_range;\n\t\t\tnfs4_stateid cbl_stateid;\n\t\t};\n\t\tstruct nfs_fsid cbl_fsid;\n\t};\n};\n\nstruct nfs_lowner {\n\t__u64 clientid;\n\t__u64 id;\n\tdev_t s_dev;\n};\n\nstruct cb_notify_lock_args {\n\tstruct nfs_fh cbnl_fh;\n\tstruct nfs_lowner cbnl_owner;\n\tbool cbnl_valid;\n};\n\nstruct nfs_client;\n\nstruct nfs4_slot;\n\nstruct cb_process_state {\n\tstruct nfs_client *clp;\n\tstruct nfs4_slot *slot;\n\tstruct net *net;\n\tu32 minorversion;\n\t__be32 drc_status;\n\tunsigned int referring_calls;\n};\n\nstruct cb_recallanyargs {\n\tuint32_t craa_objs_to_keep;\n\tuint32_t craa_type_mask;\n};\n\nstruct cb_recallargs {\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tuint32_t truncate;\n};\n\nstruct cb_recallslotargs {\n\tuint32_t crsa_target_highest_slotid;\n};\n\nstruct nfs4_sessionid {\n\tunsigned char data[16];\n};\n\nstruct referring_call_list;\n\nstruct cb_sequenceargs {\n\tstruct sockaddr *csa_addr;\n\tstruct nfs4_sessionid csa_sessionid;\n\tuint32_t csa_sequenceid;\n\tuint32_t csa_slotid;\n\tuint32_t csa_highestslotid;\n\tuint32_t csa_cachethis;\n\tuint32_t csa_nrclists;\n\tstruct referring_call_list *csa_rclists;\n};\n\nstruct cb_sequenceres {\n\t__be32 csr_status;\n\tstruct nfs4_sessionid csr_sessionid;\n\tuint32_t csr_sequenceid;\n\tuint32_t csr_slotid;\n\tuint32_t csr_highestslotid;\n\tuint32_t csr_target_highestslotid;\n};\n\nstruct cc_workarea {\n\t__be32 drc_index;\n\t__be32 zero;\n\t__be32 name_offset;\n\t__be32 prop_length;\n\t__be32 prop_offset;\n};\n\nstruct ccs_modesel_head {\n\t__u8 _r1;\n\t__u8 medium;\n\t__u8 _r2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_blocks_hi;\n\t__u8 number_blocks_med;\n\t__u8 number_blocks_lo;\n\t__u8 _r3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct cdrom_msf0 {\n\t__u8 minute;\n\t__u8 second;\n\t__u8 frame;\n};\n\nunion cdrom_addr {\n\tstruct cdrom_msf0 msf;\n\tint lba;\n};\n\nstruct cdrom_blk {\n\tunsigned int from;\n\tshort unsigned int len;\n};\n\nstruct cdrom_mechstat_header {\n\t__u8 curslot: 5;\n\t__u8 changer_state: 2;\n\t__u8 fault: 1;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 mech_state: 3;\n\t__u8 curlba[3];\n\t__u8 nslots;\n\t__u16 slot_tablelen;\n};\n\nstruct cdrom_slot {\n\t__u8 change: 1;\n\t__u8 reserved1: 6;\n\t__u8 disc_present: 1;\n\t__u8 reserved2[3];\n};\n\nstruct cdrom_changer_info {\n\tstruct cdrom_mechstat_header hdr;\n\tstruct cdrom_slot slots[256];\n};\n\nstruct cdrom_device_ops;\n\nstruct cdrom_device_info {\n\tconst struct cdrom_device_ops *ops;\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tvoid *handle;\n\tint mask;\n\tint speed;\n\tint capacity;\n\tunsigned int options: 30;\n\tunsigned int mc_flags: 2;\n\tunsigned int vfs_events;\n\tunsigned int ioctl_events;\n\tint use_count;\n\tchar name[20];\n\t__u8 sanyo_slot: 2;\n\t__u8 keeplocked: 1;\n\t__u8 reserved: 5;\n\tint cdda_method;\n\t__u8 last_sense;\n\t__u8 media_written;\n\tshort unsigned int mmc3_profile;\n\tint mrw_mode_page;\n\tbool opened_for_data;\n\t__s64 last_media_change_ms;\n};\n\nstruct cdrom_multisession;\n\nstruct cdrom_mcn;\n\nstruct packet_command;\n\nstruct cdrom_device_ops {\n\tint (*open)(struct cdrom_device_info *, int);\n\tvoid (*release)(struct cdrom_device_info *);\n\tint (*drive_status)(struct cdrom_device_info *, int);\n\tunsigned int (*check_events)(struct cdrom_device_info *, unsigned int, int);\n\tint (*tray_move)(struct cdrom_device_info *, int);\n\tint (*lock_door)(struct cdrom_device_info *, int);\n\tint (*select_speed)(struct cdrom_device_info *, long unsigned int);\n\tint (*get_last_session)(struct cdrom_device_info *, struct cdrom_multisession *);\n\tint (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);\n\tint (*reset)(struct cdrom_device_info *);\n\tint (*audio_ioctl)(struct cdrom_device_info *, unsigned int, void *);\n\tint (*generic_packet)(struct cdrom_device_info *, struct packet_command *);\n\tint (*read_cdda_bpc)(struct cdrom_device_info *, void *, u32, u32, u8 *);\n\tconst int capability;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tunion {\n\t\tvoid *reserved[1];\n\t\tvoid *unused;\n\t};\n};\n\nstruct cdrom_mcn {\n\t__u8 medium_catalog_number[14];\n};\n\nstruct cdrom_msf {\n\t__u8 cdmsf_min0;\n\t__u8 cdmsf_sec0;\n\t__u8 cdmsf_frame0;\n\t__u8 cdmsf_min1;\n\t__u8 cdmsf_sec1;\n\t__u8 cdmsf_frame1;\n};\n\nstruct cdrom_multisession {\n\tunion cdrom_addr addr;\n\t__u8 xa_flag;\n\t__u8 addr_format;\n};\n\nstruct cdrom_read_audio {\n\tunion cdrom_addr addr;\n\t__u8 addr_format;\n\tint nframes;\n\t__u8 *buf;\n};\n\nstruct cdrom_subchnl {\n\t__u8 cdsc_format;\n\t__u8 cdsc_audiostatus;\n\t__u8 cdsc_adr: 4;\n\t__u8 cdsc_ctrl: 4;\n\t__u8 cdsc_trk;\n\t__u8 cdsc_ind;\n\tunion cdrom_addr cdsc_absaddr;\n\tunion cdrom_addr cdsc_reladdr;\n};\n\nstruct cdrom_sysctl_settings {\n\tchar info[1000];\n\tint autoclose;\n\tint autoeject;\n\tint debug;\n\tint lock;\n\tint check;\n};\n\nstruct cdrom_ti {\n\t__u8 cdti_trk0;\n\t__u8 cdti_ind0;\n\t__u8 cdti_trk1;\n\t__u8 cdti_ind1;\n};\n\nstruct cdrom_timed_media_change_info {\n\t__s64 last_media_change;\n\t__u64 media_flags;\n};\n\nstruct cdrom_tocentry {\n\t__u8 cdte_track;\n\t__u8 cdte_adr: 4;\n\t__u8 cdte_ctrl: 4;\n\t__u8 cdte_format;\n\tunion cdrom_addr cdte_addr;\n\t__u8 cdte_datamode;\n};\n\nstruct cdrom_tochdr {\n\t__u8 cdth_trk0;\n\t__u8 cdth_trk1;\n};\n\nstruct cdrom_volctrl {\n\t__u8 channel0;\n\t__u8 channel1;\n\t__u8 channel2;\n\t__u8 channel3;\n};\n\nstruct clock_event_device;\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\nstruct cfs_bandwidth {\n\traw_spinlock_t lock;\n\tktime_t period;\n\tu64 quota;\n\tu64 runtime;\n\tu64 burst;\n\tu64 runtime_snap;\n\ts64 hierarchical_quota;\n\tu8 idle;\n\tu8 period_active;\n\tu8 slack_started;\n\tstruct hrtimer period_timer;\n\tstruct hrtimer slack_timer;\n\tstruct list_head throttled_cfs_rq;\n\tint nr_periods;\n\tint nr_throttled;\n\tint nr_burst;\n\tu64 throttled_time;\n\tu64 burst_time;\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tunsigned int util_est;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sched_entity;\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_queued;\n\tunsigned int h_nr_queued;\n\tunsigned int h_nr_runnable;\n\tunsigned int h_nr_idle;\n\ts64 sum_w_vruntime;\n\tu64 sum_weight;\n\tu64 zero_vruntime;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t} removed;\n\tu64 last_update_tg_load_avg;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tint idle;\n\tint runtime_enabled;\n\ts64 runtime_remaining;\n\tu64 throttled_pelt_idle;\n\tu64 throttled_clock;\n\tu64 throttled_clock_pelt;\n\tu64 throttled_clock_pelt_time;\n\tu64 throttled_clock_self;\n\tu64 throttled_clock_self_time;\n\tbool throttled: 1;\n\tbool pelt_clock_throttled: 1;\n\tint throttle_count;\n\tstruct list_head throttled_list;\n\tstruct list_head throttled_csd_list;\n\tstruct list_head throttled_limbo_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cfs_schedulable_data {\n\tstruct task_group *tg;\n\tu64 period;\n\tu64 quota;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_file;\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tstruct lock_class_key lockdep_key;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n\tu64 ntime;\n};\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n};\n\nstruct cgroup_bpf {\n\tstruct bpf_prog_array *effective[38];\n\tstruct hlist_head progs[38];\n\tu8 flags[38];\n\tu64 revisions[38];\n\tstruct list_head storages;\n\tstruct bpf_prog_array *inactive;\n\tstruct percpu_ref refcnt;\n\tstruct work_struct release_work;\n};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tbool e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n\tseqcount_spinlock_t freeze_seq;\n\tu64 freeze_start_nsec;\n\tu64 frozen_nsec;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_base_cpu;\n\nstruct psi_group;\n\nstruct scx_sched;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tunsigned int kill_seq;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file psi_files[3];\n\tu32 subtree_control;\n\tu32 subtree_ss_mask;\n\tu32 old_subtree_control;\n\tu32 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[11];\n\tint nr_dying_subsys[11];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[11];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_base_cpu *rstat_base_cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad_;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group *psi;\n\tstruct cgroup_bpf bpf;\n\tstruct cgroup_freezer_state freezer;\n\tstruct bpf_local_storage *bpf_cgrp_storage;\n\tstruct scx_sched *scx_sched;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_ancestors;\n\t\t\tstruct cgroup *ancestors[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct cgroup *_root_ancestor;\n\t\t\tstruct {\n\t\t\t\tstruct {} __empty__low_ancestors;\n\t\t\t\tstruct cgroup *_low_ancestors[0];\n\t\t\t};\n\t\t};\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup__safe_rcu {\n\tstruct kernfs_node *kn;\n};\n\nstruct css_set;\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_of_peak {\n\tlong unsigned int value;\n\tstruct list_head list;\n};\n\nstruct cgroup_namespace;\n\nstruct cgroup_pidlist;\n\nstruct cgroup_file_ctx {\n\tstruct cgroup_namespace *ns;\n\tstruct {\n\t\tvoid *trigger;\n\t} psi;\n\tstruct {\n\t\tbool started;\n\t\tstruct css_task_iter iter;\n\t} procs;\n\tstruct {\n\t\tstruct cgroup_pidlist *pidlist;\n\t} procs1;\n\tstruct cgroup_of_peak peak;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu32 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgroup_iter_priv {\n\tstruct cgroup_subsys_state *start_css;\n\tbool visited_all;\n\tbool terminate;\n\tint order;\n};\n\nstruct cgroup_lsm_atype {\n\tu32 attach_btf_id;\n\tint refcnt;\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu32 ss_mask;\n};\n\nstruct ns_tree_node {\n\tstruct rb_node ns_node;\n\tstruct list_head ns_list_entry;\n};\n\nstruct ns_tree_root {\n\tstruct rb_root ns_rb;\n\tstruct list_head ns_list_head;\n};\n\nstruct ns_tree {\n\tu64 ns_id;\n\tatomic_t __ns_ref_active;\n\tstruct ns_tree_node ns_unified_node;\n\tstruct ns_tree_node ns_tree_node;\n\tstruct ns_tree_node ns_owner_node;\n\tstruct ns_tree_root ns_owner_root;\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tstruct {\n\t\trefcount_t __ns_ref;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tu32 ns_type;\n\tstruct dentry *stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n\tunion {\n\t\tstruct ns_tree;\n\t\tstruct callback_head ns_rcu;\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ucounts;\n\nstruct cgroup_namespace {\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct list_head root_list;\n\tstruct callback_head rcu;\n\tatomic_t nr_cgrps;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n\tlong: 64;\n\tstruct cgroup cgrp;\n};\n\nstruct cgroup_rstat_base_cpu {\n\tstruct u64_stats_sync bsync;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat subtree_bstat;\n\tstruct cgroup_base_stat last_subtree_bstat;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_killed)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*css_local_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n\tspinlock_t rstat_ss_lock;\n\tstruct llist_head *lhead;\n};\n\nstruct cgroup_subsys_state__safe_rcu {\n\tstruct cgroup *cgroup;\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct chacha_state {\n\tu32 x[16];\n};\n\nstruct change_memory_parms {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int newpp;\n\tunsigned int step;\n\tunsigned int nr_cpus;\n\tatomic_t master_cpu;\n\tatomic_t cpu_counter;\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\nstruct check_loop_arg {\n\tstruct qdisc_walker w;\n\tstruct Qdisc *p;\n\tint depth;\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct check_owner {\n\tstruct list_head list;\n\txfs_daddr_t daddr;\n\tint level;\n};\n\nstruct chip {\n\tunsigned int id;\n\tbool throttled;\n\tbool restore;\n\tu8 throttle_reason;\n\tcpumask_t mask;\n\tstruct work_struct throttle;\n\tint throttle_turbo;\n\tint throttle_sub_turbo;\n\tint reason[6];\n};\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct rtc_class_ops;\n\nstruct ds1307;\n\nstruct chip_desc {\n\tunsigned int alarm: 1;\n\tu16 nvram_offset;\n\tu16 nvram_size;\n\tu8 offset;\n\tu8 century_reg;\n\tu8 century_enable_bit;\n\tu8 century_bit;\n\tu8 bbsqi_bit;\n\tirq_handler_t irq_handler;\n\tconst struct rtc_class_ops *rtc_ops;\n\tu16 trickle_charger_reg;\n\tu8 (*do_trickle_setup)(struct ds1307 *, u32, bool);\n\tbool requires_trickle_resistor;\n\tbool charge_default;\n};\n\nstruct cipher_context {\n\tchar iv[20];\n\tchar rec_seq[8];\n};\n\nstruct cis_cache_entry {\n\tstruct list_head node;\n\tunsigned int addr;\n\tunsigned int len;\n\tunsigned int attr;\n\tunsigned char cache[0];\n};\n\nstruct cistpl_device_t {\n\tu_char ndev;\n\tstruct {\n\t\tu_char type;\n\t\tu_char wp;\n\t\tu_int speed;\n\t\tu_int size;\n\t} dev[4];\n};\n\ntypedef struct cistpl_device_t cistpl_device_t;\n\nstruct cistpl_checksum_t {\n\tu_short addr;\n\tu_short len;\n\tu_char sum;\n};\n\ntypedef struct cistpl_checksum_t cistpl_checksum_t;\n\nstruct cistpl_longlink_t {\n\tu_int addr;\n};\n\ntypedef struct cistpl_longlink_t cistpl_longlink_t;\n\nstruct cistpl_longlink_mfc_t {\n\tu_char nfn;\n\tstruct {\n\t\tu_char space;\n\t\tu_int addr;\n\t} fn[8];\n};\n\ntypedef struct cistpl_longlink_mfc_t cistpl_longlink_mfc_t;\n\nstruct cistpl_vers_1_t {\n\tu_char major;\n\tu_char minor;\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_vers_1_t cistpl_vers_1_t;\n\nstruct cistpl_altstr_t {\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_altstr_t cistpl_altstr_t;\n\nstruct cistpl_jedec_t {\n\tu_char nid;\n\tstruct {\n\t\tu_char mfr;\n\t\tu_char info;\n\t} id[4];\n};\n\ntypedef struct cistpl_jedec_t cistpl_jedec_t;\n\nstruct cistpl_manfid_t {\n\tu_short manf;\n\tu_short card;\n};\n\ntypedef struct cistpl_manfid_t cistpl_manfid_t;\n\nstruct cistpl_funcid_t {\n\tu_char func;\n\tu_char sysinit;\n};\n\ntypedef struct cistpl_funcid_t cistpl_funcid_t;\n\nstruct cistpl_funce_t {\n\tu_char type;\n\tu_char data[0];\n};\n\ntypedef struct cistpl_funce_t cistpl_funce_t;\n\nstruct cistpl_bar_t {\n\tu_char attr;\n\tu_int size;\n};\n\ntypedef struct cistpl_bar_t cistpl_bar_t;\n\nstruct cistpl_config_t {\n\tu_char last_idx;\n\tu_int base;\n\tu_int rmask[4];\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_config_t cistpl_config_t;\n\nstruct cistpl_power_t {\n\tu_char present;\n\tu_char flags;\n\tu_int param[7];\n};\n\ntypedef struct cistpl_power_t cistpl_power_t;\n\nstruct cistpl_timing_t {\n\tu_int wait;\n\tu_int waitscale;\n\tu_int ready;\n\tu_int rdyscale;\n\tu_int reserved;\n\tu_int rsvscale;\n};\n\ntypedef struct cistpl_timing_t cistpl_timing_t;\n\nstruct cistpl_io_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int base;\n\t\tu_int len;\n\t} win[16];\n};\n\ntypedef struct cistpl_io_t cistpl_io_t;\n\nstruct cistpl_irq_t {\n\tu_int IRQInfo1;\n\tu_int IRQInfo2;\n};\n\ntypedef struct cistpl_irq_t cistpl_irq_t;\n\nstruct cistpl_mem_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int len;\n\t\tu_int card_addr;\n\t\tu_int host_addr;\n\t} win[8];\n};\n\ntypedef struct cistpl_mem_t cistpl_mem_t;\n\nstruct cistpl_cftable_entry_t {\n\tu_char index;\n\tu_short flags;\n\tu_char interface;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tcistpl_timing_t timing;\n\tcistpl_io_t io;\n\tcistpl_irq_t irq;\n\tcistpl_mem_t mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_t cistpl_cftable_entry_t;\n\nstruct cistpl_cftable_entry_cb_t {\n\tu_char index;\n\tu_int flags;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tu_char io;\n\tcistpl_irq_t irq;\n\tu_char mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_cb_t cistpl_cftable_entry_cb_t;\n\nstruct cistpl_device_geo_t {\n\tu_char ngeo;\n\tstruct {\n\t\tu_char buswidth;\n\t\tu_int erase_block;\n\t\tu_int read_block;\n\t\tu_int write_block;\n\t\tu_int partition;\n\t\tu_int interleave;\n\t} geo[4];\n};\n\ntypedef struct cistpl_device_geo_t cistpl_device_geo_t;\n\nstruct cistpl_vers_2_t {\n\tu_char vers;\n\tu_char comply;\n\tu_short dindex;\n\tu_char vspec8;\n\tu_char vspec9;\n\tu_char nhdr;\n\tu_char vendor;\n\tu_char info;\n\tchar str[244];\n};\n\ntypedef struct cistpl_vers_2_t cistpl_vers_2_t;\n\nstruct cistpl_org_t {\n\tu_char data_org;\n\tchar desc[30];\n};\n\ntypedef struct cistpl_org_t cistpl_org_t;\n\nstruct cistpl_format_t {\n\tu_char type;\n\tu_char edc;\n\tu_int offset;\n\tu_int length;\n};\n\ntypedef struct cistpl_format_t cistpl_format_t;\n\nunion cisparse_t {\n\tcistpl_device_t device;\n\tcistpl_checksum_t checksum;\n\tcistpl_longlink_t longlink;\n\tcistpl_longlink_mfc_t longlink_mfc;\n\tcistpl_vers_1_t version_1;\n\tcistpl_altstr_t altstr;\n\tcistpl_jedec_t jedec;\n\tcistpl_manfid_t manfid;\n\tcistpl_funcid_t funcid;\n\tcistpl_funce_t funce;\n\tcistpl_bar_t bar;\n\tcistpl_config_t config;\n\tcistpl_cftable_entry_t cftable_entry;\n\tcistpl_cftable_entry_cb_t cftable_entry_cb;\n\tcistpl_device_geo_t device_geo;\n\tcistpl_vers_2_t vers_2;\n\tcistpl_org_t org;\n\tcistpl_format_t format;\n};\n\ntypedef union cisparse_t cisparse_t;\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct class *, const struct class_attribute *, char *);\n\tssize_t (*store)(const struct class *, const struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct hashtab_node;\n\nstruct hashtab {\n\tstruct hashtab_node **htable;\n\tu32 size;\n\tu32 nel;\n};\n\nstruct symtab {\n\tstruct hashtab table;\n\tu32 nprim;\n};\n\nstruct common_datum;\n\nstruct constraint_node;\n\nstruct class_datum {\n\tu32 value;\n\tchar *comkey;\n\tstruct common_datum *comdatum;\n\tstruct symtab permissions;\n\tstruct constraint_node *constraints;\n\tstruct constraint_node *validatetrans;\n\tchar default_user;\n\tchar default_role;\n\tchar default_type;\n\tchar default_range;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct subsys_private;\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n\tstruct subsys_private *sp;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tconst struct class *class;\n};\n\nstruct class_info {\n\tint class;\n\tchar *class_name;\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tconst struct class *class;\n\tint (*add_dev)(struct device *);\n\tvoid (*remove_dev)(struct device *);\n};\n\nstruct clear_badblocks_context {\n\tresource_size_t phys;\n\tresource_size_t cleared;\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct clock_identity {\n\tu8 id[8];\n};\n\nstruct clocksource_base;\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu32 uncertainty_margin;\n\tu64 max_cycles;\n\tu64 max_raw_delta;\n\tconst char *name;\n\tstruct list_head list;\n\tu32 freq_khz;\n\tint rating;\n\tenum clocksource_ids id;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tstruct clocksource_base *base;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct module *owner;\n};\n\nstruct clocksource_base {\n\tenum clocksource_ids id;\n\tu32 freq_khz;\n\tu64 offset;\n\tu32 numerator;\n\tu32 denominator;\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct dm_table;\n\nstruct dm_io;\n\nstruct clone_info {\n\tstruct dm_table *map;\n\tstruct bio *bio;\n\tstruct dm_io *io;\n\tsector_t sector;\n\tunsigned int sector_count;\n\tbool is_abnormal_io: 1;\n\tbool submit_as_polled: 1;\n};\n\nstruct cma_memrange {\n\tlong unsigned int base_pfn;\n\tlong unsigned int count;\n\tunion {\n\t\tlong unsigned int early_pfn;\n\t\tlong unsigned int *bitmap;\n\t};\n};\n\nstruct cma {\n\tlong unsigned int count;\n\tlong unsigned int available_count;\n\tunsigned int order_per_bit;\n\tspinlock_t lock;\n\tstruct mutex alloc_mutex;\n\tchar name[64];\n\tint nranges;\n\tstruct cma_memrange ranges[8];\n\tlong unsigned int flags;\n\tint nid;\n};\n\nstruct cma_init_memrange {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tstruct list_head list;\n};\n\nstruct cmis_cdb_advert_rpl {\n\tu8 inst_supported;\n\tu8 read_write_len_ext;\n\tu8 resv1;\n\tu8 resv2;\n};\n\nstruct cmis_cdb_fw_mng_features_rpl {\n\tu8 resv1;\n\tu8 resv2;\n\tu8 start_cmd_payload_size;\n\tu8 resv3;\n\tu8 read_write_len_ext;\n\tu8 write_mechanism;\n\tu8 resv4;\n\tu8 resv5;\n\t__be16 max_duration_start;\n\t__be16 resv6;\n\t__be16 max_duration_write;\n\t__be16 max_duration_complete;\n\t__be16 resv7;\n};\n\nstruct cmis_cdb_module_features_rpl {\n\tu8 resv1[34];\n\t__be16 max_completion_time;\n};\n\nstruct cmis_cdb_query_status_pl {\n\tu16 response_delay;\n};\n\nstruct cmis_cdb_query_status_rpl {\n\tu8 length;\n\tu8 status;\n};\n\nstruct cmis_cdb_run_fw_image_pl {\n\tu8 resv1;\n\tu8 image_to_run;\n\tu16 delay_to_reset;\n};\n\nstruct cmis_cdb_start_fw_download_pl_h {\n\t__be32 image_size;\n\t__be32 resv1;\n};\n\nstruct cmis_cdb_start_fw_download_pl {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 image_size;\n\t\t\t__be32 resv1;\n\t\t};\n\t\tstruct cmis_cdb_start_fw_download_pl_h head;\n\t};\n\tu8 vendor_data[112];\n};\n\nstruct cmis_cdb_write_fw_block_epl_pl {\n\tu8 fw_block[2048];\n};\n\nstruct cmis_cdb_write_fw_block_lpl_pl {\n\t__be32 block_address;\n\tu8 fw_block[116];\n};\n\nstruct cmis_fw_update_fw_mng_features {\n\tu8 start_cmd_payload_size;\n\tu8 write_mechanism;\n\tu16 max_duration_start;\n\tu16 max_duration_write;\n\tu16 max_duration_complete;\n};\n\nstruct cmis_password_entry_pl {\n\t__be32 password;\n};\n\nstruct cmis_rev_rpl {\n\tu8 rev;\n};\n\nstruct cmis_wait_for_cond_rpl {\n\tu8 state;\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct kernel_ethtool_coalesce {\n\tu8 use_cqe_mode_tx;\n\tu8 use_cqe_mode_rx;\n\tu32 tx_aggr_max_bytes;\n\tu32 tx_aggr_max_frames;\n\tu32 tx_aggr_time_usecs;\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tstruct kernel_ethtool_coalesce kernel_coalesce;\n\tu32 supported_params;\n};\n\nstruct codegen_context {\n\tunsigned int seen;\n\tunsigned int idx;\n\tunsigned int stack_size;\n\tint b2p[15];\n\tunsigned int exentry_idx;\n\tunsigned int alt_exit_addr;\n\tu64 arena_vm_start;\n\tu64 user_vm_start;\n\tbool is_subprog;\n\tbool exception_boundary;\n\tbool exception_cb;\n};\n\nstruct collapse_control {\n\tbool is_khugepaged;\n\tu32 node_load[256];\n\tnodemask_t alloc_nmask;\n};\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n};\n\nstruct lsm_network_audit;\n\nstruct lsm_ioctlop_audit;\n\nstruct lsm_ibpkey_audit;\n\nstruct lsm_ibendport_audit;\n\nstruct selinux_audit_data;\n\nstruct common_audit_data {\n\tchar type;\n\tunion {\n\t\tstruct path path;\n\t\tstruct dentry *dentry;\n\t\tstruct inode *inode;\n\t\tstruct lsm_network_audit *net;\n\t\tint cap;\n\t\tint ipc_id;\n\t\tstruct task_struct *tsk;\n\t\tstruct {\n\t\t\tkey_serial_t key;\n\t\t\tchar *key_desc;\n\t\t} key_struct;\n\t\tchar *kmod_name;\n\t\tstruct lsm_ioctlop_audit *op;\n\t\tstruct file *file;\n\t\tstruct lsm_ibpkey_audit *ibpkey;\n\t\tstruct lsm_ibendport_audit *ibendport;\n\t\tint reason;\n\t\tconst char *anonclass;\n\t\tu16 nlmsg_type;\n\t} u;\n\tunion {\n\t\tstruct selinux_audit_data *selinux_audit_data;\n\t};\n};\n\nstruct common_datum {\n\tu32 value;\n\tstruct symtab permissions;\n};\n\nstruct zone;\n\nstruct compact_control {\n\tstruct list_head freepages[9];\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool proactive_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool finish_pageblock;\n\tbool alloc_contig;\n};\n\nstruct compare_key {\n\tu16 base;\n\tu16 mark;\n};\n\nstruct compat_group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t} __attribute__((packed));\n\t};\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n} __attribute__((packed));\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n} __attribute__((packed));\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct compat_nfs_string {\n\tcompat_uint_t len;\n\tcompat_uptr_t data;\n};\n\nstruct compat_nfs4_mount_data_v1 {\n\tcompat_int_t version;\n\tcompat_int_t flags;\n\tcompat_int_t rsize;\n\tcompat_int_t wsize;\n\tcompat_int_t timeo;\n\tcompat_int_t retrans;\n\tcompat_int_t acregmin;\n\tcompat_int_t acregmax;\n\tcompat_int_t acdirmin;\n\tcompat_int_t acdirmax;\n\tstruct compat_nfs_string client_addr;\n\tstruct compat_nfs_string mnt_path;\n\tstruct compat_nfs_string hostname;\n\tcompat_uint_t host_addrlen;\n\tcompat_uptr_t host_addr;\n\tcompat_int_t proto;\n\tcompat_int_t auth_flavourlen;\n\tcompat_uptr_t auth_flavours;\n};\n\nstruct compat_sg_io_hdr {\n\tcompat_int_t interface_id;\n\tcompat_int_t dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tcompat_uint_t dxfer_len;\n\tcompat_uint_t dxferp;\n\tcompat_uptr_t cmdp;\n\tcompat_uptr_t sbp;\n\tcompat_uint_t timeout;\n\tcompat_uint_t flags;\n\tcompat_int_t pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tcompat_int_t resid;\n\tcompat_uint_t duration;\n\tcompat_uint_t info;\n};\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tint _trapno;\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t\tstruct {\n\t\t\t\t\tcompat_ulong_t _data;\n\t\t\t\t\tu32 _type;\n\t\t\t\t\tu32 _flags;\n\t\t\t\t} _perf;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nstruct component_ops;\n\nstruct component {\n\tstruct list_head node;\n\tstruct aggregate_device *adev;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component_match_array;\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\nstruct compound_hdr {\n\tint32_t status;\n\tuint32_t nops;\n\t__be32 *nops_p;\n\tuint32_t taglen;\n\tchar *tag;\n\tuint32_t replen;\n\tu32 minorversion;\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct consw;\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nstruct cond_av_list {\n\tstruct avtab_node **nodes;\n\tu32 len;\n};\n\nstruct cond_bool_datum {\n\tu32 value;\n\tint state;\n};\n\nstruct cond_expr_node;\n\nstruct cond_expr {\n\tstruct cond_expr_node *nodes;\n\tu32 len;\n};\n\nstruct cond_expr_node {\n\tu32 expr_type;\n\tu32 boolean;\n};\n\nstruct policydb;\n\nstruct cond_insertf_data {\n\tstruct policydb *p;\n\tstruct avtab_node **dst;\n\tstruct cond_av_list *other;\n};\n\nstruct cond_node {\n\tint cur_state;\n\tstruct cond_expr expr;\n\tstruct cond_av_list true_list;\n\tstruct cond_av_list false_list;\n};\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\nstruct cond_snapshot {\n\tvoid *cond_data;\n\tcond_update_fn_t update;\n};\n\nstruct config___2 {\n\tu8 version;\n\tu8 flags;\n\t__be16 rsvd0;\n\t__be16 objoverhead;\n\t__be16 maxpwsize;\n\t__be16 maxobjlabelsize;\n\t__be16 maxobjsize;\n\t__be32 totalsize;\n\t__be32 usedspace;\n\t__be32 supportedpolicies;\n\t__be32 maxlargeobjectsize;\n\t__be64 signedupdatealgorithms;\n\t__be64 wrappingfeatures;\n\tu8 rsvd1[476];\n} __attribute__((packed));\n\nstruct deflate_state;\n\ntypedef struct deflate_state deflate_state;\n\ntypedef block_state (*compress_func)(deflate_state *, int);\n\nstruct config_s {\n\tush good_length;\n\tush max_lazy;\n\tush nice_length;\n\tush max_chain;\n\tcompress_func func;\n};\n\ntypedef struct config_s config;\n\nstruct config_t {\n\tstruct kref ref;\n\tunsigned int state;\n\tstruct resource io[2];\n\tstruct resource mem[4];\n};\n\ntypedef struct config_t config_t;\n\nstruct connect_timeout_data {\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct console;\n\nstruct printk_buffers;\n\nstruct nbcon_context {\n\tstruct console *console;\n\tunsigned int spinwait_max_us;\n\tenum nbcon_prio prio;\n\tunsigned int allow_unsafe_takeover: 1;\n\tunsigned int backlog: 1;\n\tstruct printk_buffers *pbufs;\n\tu64 seq;\n};\n\nstruct tty_driver;\n\nstruct nbcon_write_context;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)(void);\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tuint ispeed;\n\tuint ospeed;\n\tu64 seq;\n\tlong unsigned int dropped;\n\tvoid *data;\n\tstruct hlist_node node;\n\tvoid (*write_atomic)(struct console *, struct nbcon_write_context *);\n\tvoid (*write_thread)(struct console *, struct nbcon_write_context *);\n\tvoid (*device_lock)(struct console *, long unsigned int *);\n\tvoid (*device_unlock)(struct console *, long unsigned int);\n\tatomic_t nbcon_state;\n\tatomic_long_t nbcon_seq;\n\tstruct nbcon_context nbcon_device_ctxt;\n\tatomic_long_t nbcon_prev_seq;\n\tstruct printk_buffers *pbufs;\n\tstruct task_struct *kthread;\n\tstruct rcuwait rcuwait;\n\tstruct irq_work irq_work;\n};\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tchar devname[32];\n\tbool user_specified;\n\tchar *options;\n};\n\nstruct console_flush_type {\n\tbool nbcon_atomic;\n\tbool nbcon_offload;\n\tbool legacy_direct;\n\tbool legacy_offload;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nstruct ebitmap_node;\n\nstruct ebitmap {\n\tstruct ebitmap_node *node;\n\tu32 highbit;\n};\n\nstruct type_set;\n\nstruct constraint_expr {\n\tu32 expr_type;\n\tu32 attr;\n\tu32 op;\n\tstruct ebitmap names;\n\tstruct type_set *type_names;\n\tstruct constraint_expr *next;\n};\n\nstruct constraint_node {\n\tu32 permissions;\n\tstruct constraint_expr *expr;\n\tstruct constraint_node *next;\n};\n\nstruct vc_data;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)(void);\n\tvoid (*con_init)(struct vc_data *, bool);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_putc)(struct vc_data *, u16, unsigned int, unsigned int);\n\tvoid (*con_putcs)(struct vc_data *, const u16 *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_cursor)(struct vc_data *, bool);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tbool (*con_switch)(struct vc_data *);\n\tbool (*con_blank)(struct vc_data *, enum vesa_blank_mode, bool);\n\tint (*con_font_set)(struct vc_data *, const struct console_font *, unsigned int, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, const char *);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, bool);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tbool (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, enum vc_intensity, bool, bool, bool, bool);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n};\n\nstruct cont_t {\n\tvoid (*interrupt)(void);\n\tvoid (*redo)(void);\n\tvoid (*error)(void);\n\tvoid (*done)(int);\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n};\n\nstruct mls_level {\n\tu32 sens;\n\tstruct ebitmap cat;\n};\n\nstruct mls_range {\n\tstruct mls_level level[2];\n};\n\nstruct context {\n\tu32 user;\n\tu32 role;\n\tu32 type;\n\tu32 len;\n\tstruct mls_range range;\n\tchar *str;\n};\n\nstruct context_tracking {\n\tbool active;\n\tint recursion;\n\tatomic_t state;\n\tlong int nesting;\n\tlong int nmi_nesting;\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\nstruct convert_context_args {\n\tstruct policydb *oldp;\n\tstruct policydb *newp;\n};\n\nstruct cooling_spec {\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tunsigned int weight;\n};\n\nstruct cop_symcpb_header {\n\tu8 mode;\n\tu8 fdm;\n\tu8 ks_ds;\n\tu8 pad_byte;\n\tu8 __rsvd[12];\n};\n\nstruct cop_symcpb_aes_ecb {\n\tu8 key[32];\n\tu8 __rsvd[80];\n};\n\nstruct cop_symcpb_aes_cbc {\n\tu8 iv[16];\n\tu8 key[32];\n\tu8 cv[16];\n\tu32 spbc;\n\tu8 __rsvd[44];\n};\n\nstruct cop_symcpb_aes_gca {\n\tu8 in_pat[16];\n\tu8 key[32];\n\tu8 out_pat[16];\n\tu32 spbc;\n\tu8 __rsvd[44];\n};\n\nstruct cop_symcpb_aes_gcm {\n\tu8 in_pat_or_aad[16];\n\tu8 iv_or_cnt[16];\n\tu64 bit_length_aad;\n\tu64 bit_length_data;\n\tu8 in_s0[16];\n\tu8 key[32];\n\tu8 __rsvd1[16];\n\tu8 out_pat_or_mac[16];\n\tu8 out_s0[16];\n\tu8 out_cnt[16];\n\tu32 spbc;\n\tu8 __rsvd2[12];\n};\n\nstruct cop_symcpb_aes_cca {\n\tu8 b0[16];\n\tu8 b1[16];\n\tu8 key[16];\n\tu8 out_pat_or_b0[16];\n\tu32 spbc;\n\tu8 __rsvd[44];\n};\n\nstruct cop_symcpb_aes_ccm {\n\tu8 in_pat_or_b0[16];\n\tu8 iv_or_ctr[16];\n\tu8 in_s0[16];\n\tu8 key[16];\n\tu8 __rsvd1[48];\n\tu8 out_pat_or_mac[16];\n\tu8 out_s0[16];\n\tu8 out_ctr[16];\n\tu32 spbc;\n\tu8 __rsvd2[12];\n};\n\nstruct cop_symcpb_aes_ctr {\n\tu8 iv[16];\n\tu8 key[32];\n\tu8 cv[16];\n\tu32 spbc;\n\tu8 __rsvd2[44];\n};\n\nstruct cop_symcpb_aes_xcbc {\n\tu8 cv[16];\n\tu8 key[16];\n\tu8 __rsvd1[16];\n\tu8 out_cv_mac[16];\n\tu32 spbc;\n\tu8 __rsvd2[44];\n};\n\nstruct cop_symcpb_sha256 {\n\tu64 message_bit_length;\n\tu64 __rsvd1;\n\tu8 input_partial_digest[32];\n\tu8 message_digest[32];\n\tu32 spbc;\n\tu8 __rsvd2[44];\n};\n\nstruct cop_symcpb_sha512 {\n\tu64 message_bit_length_hi;\n\tu64 message_bit_length_lo;\n\tu8 input_partial_digest[64];\n\tu8 __rsvd1[32];\n\tu8 message_digest[64];\n\tu32 spbc;\n\tu8 __rsvd2[76];\n};\n\nstruct cop_parameter_block {\n\tstruct cop_symcpb_header hdr;\n\tunion {\n\t\tstruct cop_symcpb_aes_ecb aes_ecb;\n\t\tstruct cop_symcpb_aes_cbc aes_cbc;\n\t\tstruct cop_symcpb_aes_gca aes_gca;\n\t\tstruct cop_symcpb_aes_gcm aes_gcm;\n\t\tstruct cop_symcpb_aes_cca aes_cca;\n\t\tstruct cop_symcpb_aes_ccm aes_ccm;\n\t\tstruct cop_symcpb_aes_ctr aes_ctr;\n\t\tstruct cop_symcpb_aes_xcbc aes_xcbc;\n\t\tstruct cop_symcpb_sha256 sha256;\n\t\tstruct cop_symcpb_sha512 sha512;\n\t};\n};\n\nstruct cop_status_block {\n\tu8 valid;\n\tu8 crb_seq_number;\n\tu8 completion_code;\n\tu8 completion_extension;\n\t__be32 processed_byte_count;\n\t__be64 address;\n};\n\nstruct vas_user_win_ops;\n\nstruct coproc_dev {\n\tstruct cdev cdev;\n\tstruct device *device;\n\tchar *name;\n\tdev_t devt;\n\tstruct class *class;\n\tenum vas_cop_type cop_type;\n\tconst struct vas_user_win_ops *vops;\n};\n\nstruct vas_window;\n\nstruct coproc_instance {\n\tstruct coproc_dev *coproc;\n\tstruct vas_window *txwin;\n};\n\nstruct coprocessor_completion_block {\n\t__be64 value;\n\t__be64 address;\n};\n\nstruct data_descriptor_entry {\n\t__be16 flags;\n\tu8 count;\n\tu8 index;\n\t__be32 length;\n\t__be64 address;\n};\n\nstruct nx_fault_stamp {\n\t__be64 fault_storage_addr;\n\t__be16 reserved;\n\t__u8 flags;\n\t__u8 fault_status;\n\t__be32 pswid;\n};\n\nstruct coprocessor_status_block {\n\tu8 flags;\n\tu8 cs;\n\tu8 cc;\n\tu8 ce;\n\t__be32 count;\n\t__be64 address;\n};\n\nstruct coprocessor_request_block {\n\t__be32 ccw;\n\t__be32 flags;\n\t__be64 csb_addr;\n\tstruct data_descriptor_entry source;\n\tstruct data_descriptor_entry target;\n\tstruct coprocessor_completion_block ccb;\n\tunion {\n\t\tstruct nx_fault_stamp nx;\n\t\tu8 reserved[16];\n\t} stamp;\n\tu8 reserved[32];\n\tstruct coprocessor_status_block csb;\n};\n\nstruct copy_subpage_arg {\n\tstruct folio *dst;\n\tstruct folio *src;\n\tstruct vm_area_struct *vma;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n\tunsigned int core_pipe_limit;\n\tbool core_dumped;\n\tenum coredump_type_t core_type;\n\tu64 mask;\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct core_vma_metadata {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvm_flags_t flags;\n\tlong unsigned int dump_size;\n\tlong unsigned int pgoff;\n\tstruct file *file;\n};\n\nstruct coredump_ack {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 mask;\n};\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tint cpu;\n\tloff_t written;\n\tloff_t pos;\n\tloff_t to_skip;\n\tint vma_count;\n\tsize_t vma_data_size;\n\tstruct core_vma_metadata *vma_meta;\n\tstruct pid *pid;\n};\n\nstruct coredump_req {\n\t__u32 size;\n\t__u32 size_ack;\n\t__u64 mask;\n};\n\nstruct cper_arm_ctx_info {\n\tu16 version;\n\tu16 type;\n\tu32 size;\n};\n\nstruct cper_arm_err_info {\n\tu8 version;\n\tu8 length;\n\tu16 validation_bits;\n\tu8 type;\n\tu16 multiple_error;\n\tu8 flags;\n\tu64 error_info;\n\tu64 virt_fault_addr;\n\tu64 physical_fault_addr;\n} __attribute__((packed));\n\nstruct cper_sec_proc_arm {\n\tu32 validation_bits;\n\tu16 err_info_num;\n\tu16 context_info_num;\n\tu32 section_length;\n\tu8 affinity_level;\n\tu8 reserved[3];\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct cpu_accounting_data {\n\tlong unsigned int utime;\n\tlong unsigned int stime;\n\tlong unsigned int gtime;\n\tlong unsigned int hardirq_time;\n\tlong unsigned int softirq_time;\n\tlong unsigned int steal_time;\n\tlong unsigned int idle_time;\n\tlong unsigned int starttime;\n\tlong unsigned int starttime_user;\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int per_cpu_data_slice_size;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n\tbool early_ci_levels;\n};\n\nstruct update_util_data {\n\tvoid (*func)(struct update_util_data *, u64, unsigned int);\n};\n\nstruct policy_dbs_info;\n\nstruct cpu_dbs_info {\n\tu64 prev_cpu_idle;\n\tu64 prev_update_time;\n\tu64 prev_cpu_nice;\n\tunsigned int prev_load;\n\tstruct update_util_data update_util;\n\tstruct policy_dbs_info *policy_dbs;\n};\n\nstruct folio_batch {\n\tunsigned char nr;\n\tunsigned char i;\n\tbool percpu_pvec_drained;\n\tstruct folio *folios[31];\n};\n\nstruct cpu_fbatches {\n\tlocal_lock_t lock;\n\tstruct folio_batch lru_add;\n\tstruct folio_batch lru_deactivate_file;\n\tstruct folio_batch lru_deactivate;\n\tstruct folio_batch lru_lazyfree;\n\tstruct folio_batch lru_activate;\n\tlocal_lock_t lock_irq;\n\tstruct folio_batch lru_move_tail;\n};\n\nstruct mmcr_regs {\n\tlong unsigned int mmcr0;\n\tlong unsigned int mmcr1;\n\tlong unsigned int mmcr2;\n\tlong unsigned int mmcra;\n\tlong unsigned int mmcr3;\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 spec: 2;\n\t__u64 new_type: 4;\n\t__u64 priv: 3;\n\t__u64 reserved: 31;\n};\n\nstruct perf_branch_stack {\n\tu64 nr;\n\tu64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct cpu_hw_events {\n\tint n_events;\n\tint n_percpu;\n\tint disabled;\n\tint n_added;\n\tint n_limited;\n\tu8 pmcs_enabled;\n\tstruct perf_event *event[8];\n\tu64 events[8];\n\tunsigned int flags[8];\n\tstruct mmcr_regs mmcr;\n\tstruct perf_event *limited_counter[2];\n\tu8 limited_hwidx[2];\n\tu64 alternatives[64];\n\tlong unsigned int amasks[64];\n\tlong unsigned int avalues[64];\n\tunsigned int txn_flags;\n\tint n_txn_start;\n\tu64 bhrb_filter;\n\tunsigned int bhrb_users;\n\tvoid *bhrb_context;\n\tstruct perf_branch_stack bhrb_stack;\n\tstruct perf_branch_entry bhrb_entries[32];\n\tu64 ic_init;\n\tlong unsigned int pmcs[8];\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct cpu_map_ret {\n\tu32 xdp_n;\n\tu32 skb_n;\n};\n\nstruct cpu_messages {\n\tlong int messages;\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct cpu_spec;\n\ntypedef void (*cpu_setup_t)(long unsigned int, struct cpu_spec *);\n\ntypedef void (*cpu_restore_t)(void);\n\nstruct cpu_spec {\n\tunsigned int pvr_mask;\n\tunsigned int pvr_value;\n\tchar *cpu_name;\n\tlong unsigned int cpu_features;\n\tunsigned int cpu_user_features;\n\tunsigned int cpu_user_features2;\n\tunsigned int mmu_features;\n\tunsigned int icache_bsize;\n\tunsigned int dcache_bsize;\n\tvoid (*cpu_down_flush)(void);\n\tunsigned int num_pmcs;\n\tenum powerpc_pmc_type pmc_type;\n\tcpu_setup_t cpu_setup;\n\tcpu_restore_t cpu_restore;\n\tchar *platform;\n\tint (*machine_check)(struct pt_regs *);\n\tlong int (*machine_check_early)(struct pt_regs *);\n};\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tlong unsigned int caller;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n\tlong unsigned int caller;\n\tcpu_stop_fn_t fn;\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tbool firing;\n\tbool nanosleep;\n\tstruct task_struct *handling;\n};\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkuid_t rootid;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n};\n\nstruct kernel_cpustat;\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tu64 *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_policy;\n\nstruct cpufreq_policy_data;\n\nstruct freq_attr;\n\nstruct cpufreq_driver {\n\tchar name[16];\n\tu16 flags;\n\tvoid *driver_data;\n\tint (*init)(struct cpufreq_policy *);\n\tint (*verify)(struct cpufreq_policy_data *);\n\tint (*setpolicy)(struct cpufreq_policy *);\n\tint (*target)(struct cpufreq_policy *, unsigned int, unsigned int);\n\tint (*target_index)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*fast_switch)(struct cpufreq_policy *, unsigned int);\n\tvoid (*adjust_perf)(unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get)(unsigned int);\n\tvoid (*update_limits)(struct cpufreq_policy *);\n\tint (*bios_limit)(int, unsigned int *);\n\tint (*online)(struct cpufreq_policy *);\n\tint (*offline)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n\tvoid (*ready)(struct cpufreq_policy *);\n\tstruct freq_attr **attr;\n\tbool boost_enabled;\n\tint (*set_boost)(struct cpufreq_policy *, int);\n\tvoid (*register_em)(struct cpufreq_policy *);\n};\n\nstruct cpufreq_freqs {\n\tstruct cpufreq_policy *policy;\n\tunsigned int old;\n\tunsigned int new;\n\tu8 flags;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tstruct list_head governor_list;\n\tstruct module *owner;\n\tu8 flags;\n};\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_read_t;\n\ntypedef struct cpufreq_policy *class_cpufreq_policy_write_t;\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct cpufreq_stats;\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct freq_qos_request;\n\nstruct thermal_cooling_device;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tbool strict_target;\n\tbool efficiencies_available;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tbool boost_enabled;\n\tbool boost_supported;\n\tunsigned int cached_target_freq;\n\tunsigned int cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpufreq_policy_data {\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tstruct cpufreq_frequency_table *freq_table;\n\tunsigned int cpu;\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tatomic_t ap_sync_state;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nstruct cpuidle_device;\n\nstruct cpuidle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_device *, char *);\n\tssize_t (*store)(struct cpuidle_device *, const char *, size_t);\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int rejected;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct cpuidle_device_kobj {\n\tstruct cpuidle_device *dev;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_driver;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\ts64 exit_latency_ns;\n\ts64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);\n\tvoid (*enter_dead)(struct cpuidle_device *, int);\n\tint (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver *, int);\n};\n\nstruct cpuidle_driver {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct cpuidle_governor {\n\tchar name[16];\n\tstruct list_head governor_list;\n\tunsigned int rating;\n\tint (*enable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tvoid (*disable)(struct cpuidle_driver *, struct cpuidle_device *);\n\tint (*select)(struct cpuidle_driver *, struct cpuidle_device *, bool *);\n\tvoid (*reflect)(struct cpuidle_device *, int);\n};\n\nstruct cpuidle_state_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_state *, struct cpuidle_state_usage *, char *);\n\tssize_t (*store)(struct cpuidle_state *, struct cpuidle_state_usage *, const char *, size_t);\n};\n\nstruct cpuidle_state_kobj {\n\tstruct cpuidle_state *state;\n\tstruct cpuidle_state_usage *state_usage;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n\tstruct cpuidle_device *device;\n};\n\nunion cpumask_rcuhead {\n\tcpumask_t cpumask;\n\tstruct callback_head rcu;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[101];\n\tint *cpu_to_pri;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t effective_xcpus;\n\tcpumask_var_t exclusive_cpus;\n\tnodemask_t old_mems_allowed;\n\tint attach_in_progress;\n\tint partition_root_state;\n\tbool remote_partition;\n\tint nr_deadline_tasks;\n\tint nr_migrate_dl_tasks;\n\tu64 sum_migrate_dl_bw;\n\tenum prs_errcode prs_err;\n\tstruct cgroup_file partition_file;\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\nstruct cramfs_info {\n\t__u32 crc;\n\t__u32 edition;\n\t__u32 blocks;\n\t__u32 files;\n};\n\nstruct cramfs_inode {\n\t__u32 mode: 16;\n\t__u32 uid: 16;\n\t__u32 size: 24;\n\t__u32 gid: 8;\n\t__u32 namelen: 6;\n\t__u32 offset: 26;\n};\n\nstruct cramfs_super {\n\t__u32 magic;\n\t__u32 size;\n\t__u32 flags;\n\t__u32 future;\n\t__u8 signature[16];\n\tstruct cramfs_info fsid;\n\t__u8 name[16];\n\tstruct cramfs_inode root;\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct crash_mem {\n\tunsigned int max_nr_ranges;\n\tunsigned int nr_ranges;\n\tstruct range ranges[0];\n};\n\ntypedef const struct cred *class_override_creds_t;\n\ntypedef struct cred *class_prepare_creds_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_long_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tvoid *security;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct cred_security_struct {\n\tu32 osid;\n\tu32 sid;\n\tu32 exec_sid;\n\tu32 create_sid;\n\tu32 keycreate_sid;\n\tu32 sockcreate_sid;\n};\n\nstruct crng {\n\tu8 key[32];\n\tlong unsigned int generation;\n\tlocal_lock_t lock;\n};\n\nstruct viosrp_crq;\n\nstruct crq_queue {\n\tstruct viosrp_crq *msgs;\n\tint size;\n\tint cur;\n\tdma_addr_t msg_token;\n\tspinlock_t lock;\n};\n\nstruct crypto_tfm {\n\trefcount_t refcnt;\n\tu32 crt_flags;\n\tint node;\n\tstruct crypto_tfm *fb;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tvoid *__crt_ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_acomp_ctx {\n\tstruct crypto_acomp *acomp;\n\tstruct acomp_req *req;\n\tstruct crypto_wait wait;\n\tu8 *buffer;\n\tstruct mutex mutex;\n};\n\nstruct crypto_acomp_stream {\n\tspinlock_t lock;\n\tvoid *ctx;\n};\n\nstruct crypto_acomp_streams {\n\tvoid * (*alloc_ctx)(void);\n\tvoid (*free_ctx)(void *);\n\tstruct crypto_acomp_stream *streams;\n\tstruct work_struct stream_work;\n\tcpumask_t stream_want;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_ahash {\n\tbool using_shash;\n\tunsigned int statesize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_akcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_akcipher_sync_data {\n\tstruct crypto_akcipher *tfm;\n\tconst void *src;\n\tvoid *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tstruct akcipher_request *req;\n\tstruct crypto_wait cwait;\n\tstruct scatterlist sg;\n\tu8 *buf;\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_hash_walk {\n\tconst char *data;\n\tunsigned int offset;\n\tunsigned int flags;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n};\n\nstruct crypto_kpp {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_kpp_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n\tbool test_started;\n};\n\nstruct crypto_lskcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_lskcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sig {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sig_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_sync_aead {\n\tstruct crypto_aead base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct hlist_head dead;\n\tstruct module *module;\n\tstruct work_struct free_work;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tvoid (*destroy)(struct crypto_alg *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n\tunsigned int algsize;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_alg data;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct cs_dbs_tuners {\n\tunsigned int down_threshold;\n\tunsigned int freq_step;\n};\n\nstruct dbs_data;\n\nstruct policy_dbs_info {\n\tstruct cpufreq_policy *policy;\n\tstruct mutex update_mutex;\n\tu64 last_sample_time;\n\ts64 sample_delay_ns;\n\tatomic_t work_count;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\tstruct dbs_data *dbs_data;\n\tstruct list_head list;\n\tunsigned int rate_mult;\n\tunsigned int idle_periods;\n\tbool is_shared;\n\tbool work_in_progress;\n};\n\nstruct cs_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int down_skip;\n\tunsigned int requested_freq;\n};\n\nstruct csr {\n\tstruct {\n\t\tu8 status;\n\t\tu8 stat_ack;\n\t\tu8 cmd_lo;\n\t\tu8 cmd_hi;\n\t\tu32 gen_ptr;\n\t} scb;\n\tu32 port;\n\tu16 flash_ctrl;\n\tu8 eeprom_ctrl_lo;\n\tu8 eeprom_ctrl_hi;\n\tu32 mdi_ctrl;\n\tu32 rx_dma_count;\n};\n\nstruct mem_ctl_info;\n\nstruct rank_info;\n\nstruct csrow_info {\n\tstruct device dev;\n\tlong unsigned int first_page;\n\tlong unsigned int last_page;\n\tlong unsigned int page_mask;\n\tint csrow_idx;\n\tu32 ue_count;\n\tu32 ce_count;\n\tstruct mem_ctl_info *mci;\n\tu32 nr_channels;\n\tstruct rank_info **channels;\n};\n\nstruct css_rstat_cpu {\n\tstruct cgroup_subsys_state *updated_children;\n\tstruct cgroup_subsys_state *updated_next;\n\tstruct llist_node lnode;\n\tstruct cgroup_subsys_state *owner;\n};\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[11];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[11];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_src_preload_node;\n\tstruct list_head mg_dst_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct css_set__safe_rcu {\n\tstruct cgroup *dfl_cgrp;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct csum_state {\n\t__wsum csum;\n\tsize_t off;\n};\n\nstruct ct_data_s {\n\tunion {\n\t\tush freq;\n\t\tush code;\n\t} fc;\n\tunion {\n\t\tush dad;\n\t\tush len;\n\t} dl;\n};\n\ntypedef struct ct_data_s ct_data;\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tconst struct ctl_table *ctl_table;\n\t\t\tint ctl_table_size;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tconst struct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n\tenum {\n\t\tSYSCTL_TABLE_TYPE_DEFAULT = 0,\n\t\tSYSCTL_TABLE_TYPE_PERMANENTLY_EMPTY = 1,\n\t} type;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct edac_device_ctl_info;\n\nstruct ctl_info_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\ntypedef int proc_handler(const struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, const struct ctl_table *);\n};\n\nstruct netlink_policy_dump_state;\n\nstruct genl_family;\n\nstruct genl_op_iter;\n\nstruct ctrl_dump_policy_ctx {\n\tstruct netlink_policy_dump_state *state;\n\tconst struct genl_family *rt;\n\tstruct genl_op_iter *op_iter;\n\tu32 op;\n\tu16 fam_id;\n\tu8 dump_map: 1;\n\tu8 single_op: 1;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct cyclecounter {\n\tu64 (*read)(struct cyclecounter *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct dahash_test {\n\tuint16_t start;\n\tuint16_t length;\n\txfs_dahash_t dahash;\n\txfs_dahash_t ascii_ci_dahash;\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct dax_operations;\n\nstruct dax_holder_operations;\n\nstruct dax_device {\n\tstruct inode inode;\n\tstruct cdev cdev;\n\tvoid *private;\n\tlong unsigned int flags;\n\tconst struct dax_operations *ops;\n\tvoid *holder_data;\n\tconst struct dax_holder_operations *holder_ops;\n};\n\nstruct dev_dax;\n\nstruct dax_device_driver {\n\tstruct device_driver drv;\n\tstruct list_head ids;\n\tenum dax_driver_type type;\n\tint (*probe)(struct dev_dax *);\n\tvoid (*remove)(struct dev_dax *);\n};\n\nstruct dax_holder_operations {\n\tint (*notify_failure)(struct dax_device *, u64, u64, int);\n};\n\nstruct dax_id {\n\tstruct list_head list;\n\tchar dev_name[30];\n};\n\nstruct dax_mapping {\n\tstruct device dev;\n\tint range_id;\n\tint id;\n};\n\nstruct dax_operations {\n\tlong int (*direct_access)(struct dax_device *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\tint (*zero_page_range)(struct dax_device *, long unsigned int, size_t);\n\tsize_t (*recovery_write)(struct dax_device *, long unsigned int, void *, size_t, struct iov_iter *);\n};\n\nstruct ida {\n\tstruct xarray xa;\n};\n\nstruct dax_region {\n\tint id;\n\tint target_node;\n\tstruct kref kref;\n\tstruct device *dev;\n\tunsigned int align;\n\tstruct ida ida;\n\tstruct resource res;\n\tstruct device *seed;\n\tstruct device *youngest;\n};\n\nstruct gov_attr_set {\n\tstruct kobject kobj;\n\tstruct list_head policy_list;\n\tstruct mutex update_lock;\n\tint usage_count;\n};\n\nstruct dbs_governor;\n\nstruct dbs_data {\n\tstruct gov_attr_set attr_set;\n\tstruct dbs_governor *gov;\n\tvoid *tuners;\n\tunsigned int ignore_nice_load;\n\tunsigned int sampling_rate;\n\tunsigned int sampling_down_factor;\n\tunsigned int up_threshold;\n\tunsigned int io_is_busy;\n};\n\nstruct sysfs_ops;\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(const struct kobject *);\n\tconst void * (*namespace)(const struct kobject *);\n\tvoid (*get_ownership)(const struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct dbs_governor {\n\tstruct cpufreq_governor gov;\n\tstruct kobj_type kobj_type;\n\tstruct dbs_data *gdbs_data;\n\tunsigned int (*gov_dbs_update)(struct cpufreq_policy *);\n\tstruct policy_dbs_info * (*alloc)(void);\n\tvoid (*free)(struct policy_dbs_info *);\n\tint (*init)(struct dbs_data *);\n\tvoid (*exit)(struct dbs_data *);\n\tvoid (*start)(struct cpufreq_policy *);\n};\n\nstruct io_stats_per_prio {\n\tuint32_t inserted;\n\tuint32_t merged;\n\tuint32_t dispatched;\n\tatomic_t completed;\n};\n\nstruct dd_per_prio {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tsector_t latest_pos[2];\n\tstruct io_stats_per_prio stats;\n};\n\nstruct ddw_create_response {\n\tu32 liobn;\n\tu32 addr_hi;\n\tu32 addr_lo;\n};\n\nstruct ddw_query_response {\n\tu32 windows_available;\n\tu64 largest_available_block;\n\tu32 page_size;\n\tu32 migration_capable;\n};\n\nstruct deadline_data {\n\tstruct list_head dispatch;\n\tstruct dd_per_prio per_prio[3];\n\tenum dd_data_dir last_dir;\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tint prio_aging_expire;\n\tspinlock_t lock;\n};\n\nstruct ohci_hcd;\n\nstruct debug_buffer {\n\tssize_t (*fill_func)(struct debug_buffer *);\n\tstruct ohci_hcd *ohci;\n\tstruct mutex mutex;\n\tsize_t count;\n\tchar *page;\n};\n\nstruct debug_reg {};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct debugfs_cancellation {\n\tstruct list_head list;\n\tvoid (*cancel)(struct dentry *, void *);\n\tvoid *cancel_data;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct debugfs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct debugfs_short_fops;\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\tconst struct debugfs_short_fops *short_fops;\n\tstruct {\n\t\trefcount_t active_users;\n\t\tstruct completion active_users_drained;\n\t\tstruct mutex cancellations_mtx;\n\t\tstruct list_head cancellations;\n\t\tunsigned int methods;\n\t};\n};\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_inode_info {\n\tstruct inode vfs_inode;\n\tunion {\n\t\tconst void *raw;\n\t\tconst struct file_operations *real_fops;\n\t\tconst struct debugfs_short_fops *short_fops;\n\t\tdebugfs_automount_t automount;\n\t};\n\tvoid *aux;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct debugfs_short_fops {\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*llseek)(struct file *, loff_t, int);\n};\n\nstruct debugfs_u32_array {\n\tu32 *array;\n\tu32 n_elements;\n};\n\nstruct skcipher_request;\n\nstruct decryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tstruct scatterlist frags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct dma_fence;\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct defer_free {\n\tstruct llist_head objects;\n\tstruct irq_work work;\n};\n\nstruct deferred_split {\n\tspinlock_t split_queue_lock;\n\tstruct list_head split_queue;\n\tlong unsigned int split_queue_len;\n};\n\nstruct z_stream_s;\n\ntypedef struct z_stream_s z_stream;\n\ntypedef z_stream *z_streamp;\n\nstruct static_tree_desc_s;\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\nstruct tree_desc_s {\n\tct_data *dyn_tree;\n\tint max_code;\n\tstatic_tree_desc *stat_desc;\n};\n\nstruct deflate_state {\n\tz_streamp strm;\n\tint status;\n\tByte *pending_buf;\n\tulg pending_buf_size;\n\tByte *pending_out;\n\tint pending;\n\tint noheader;\n\tByte data_type;\n\tByte method;\n\tint last_flush;\n\tuInt w_size;\n\tuInt w_bits;\n\tuInt w_mask;\n\tByte *window;\n\tulg window_size;\n\tPos *prev;\n\tPos *head;\n\tuInt ins_h;\n\tuInt hash_size;\n\tuInt hash_bits;\n\tuInt hash_mask;\n\tuInt hash_shift;\n\tlong int block_start;\n\tuInt match_length;\n\tIPos prev_match;\n\tint match_available;\n\tuInt strstart;\n\tuInt match_start;\n\tuInt lookahead;\n\tuInt prev_length;\n\tuInt max_chain_length;\n\tuInt max_lazy_match;\n\tint level;\n\tint strategy;\n\tuInt good_match;\n\tint nice_match;\n\tstruct ct_data_s dyn_ltree[573];\n\tstruct ct_data_s dyn_dtree[61];\n\tstruct ct_data_s bl_tree[39];\n\tstruct tree_desc_s l_desc;\n\tstruct tree_desc_s d_desc;\n\tstruct tree_desc_s bl_desc;\n\tush bl_count[16];\n\tint heap[573];\n\tint heap_len;\n\tint heap_max;\n\tuch depth[573];\n\tuch *l_buf;\n\tuInt lit_bufsize;\n\tuInt last_lit;\n\tush *d_buf;\n\tulg opt_len;\n\tulg static_len;\n\tulg compressed_len;\n\tuInt matches;\n\tint last_eob_len;\n\tush bi_buf;\n\tint bi_valid;\n};\n\nstruct deflate_workspace {\n\tdeflate_state deflate_memory;\n\tByte *window_memory;\n\tPos *prev_memory;\n\tPos *head_memory;\n\tchar *overlay_memory;\n};\n\ntypedef struct deflate_workspace deflate_workspace;\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\nstruct delayed_filename {\n\tstruct filename *__incomplete_filename;\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct delegated_inode {\n\tstruct inode *di_inode;\n};\n\nstruct delegation {\n\t__u32 d_flags;\n\t__u16 d_type;\n\t__u16 __pad;\n};\n\nstruct demotion_nodes {\n\tnodemask_t preferred;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n};\n\nunion shortname_store {\n\tunsigned char string[40];\n\tlong unsigned int words[5];\n};\n\nstruct lockref {\n\tunion {\n\t\t__u64 lock_count;\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_spinlock_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tunion {\n\t\tstruct qstr __d_name;\n\t\tconst struct qstr d_name;\n\t};\n\tstruct inode *d_inode;\n\tunion shortname_store d_shortname;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tstruct lockref d_lockref;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct hlist_node d_sib;\n\tstruct hlist_head d_children;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n};\n\nstruct dentry__safe_trusted_or_null {\n\tstruct inode *d_inode;\n};\n\nstruct dentry_info_args {\n\tint parent_ino;\n\tint dname_len;\n\tint ino;\n\tint inode_len;\n\tchar *dname;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct inode *, const struct qstr *, struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, enum d_real_type);\n\tbool (*d_unalias_trylock)(const struct dentry *);\n\tvoid (*d_unalias_unlock)(const struct dentry *);\n\tlong: 64;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct slab;\n\nstruct detached_freelist {\n\tstruct slab *slab;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct detected_devices_node {\n\tstruct list_head list;\n\tdev_t dev;\n};\n\nstruct dev_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct list_head exceptions;\n\tenum devcg_behavior behavior;\n};\n\nstruct dev_pagemap;\n\nstruct dev_dax_range;\n\nstruct dev_dax {\n\tstruct dax_region *region;\n\tstruct dax_device *dax_dev;\n\tunsigned int align;\n\tint target_node;\n\tbool dyn_id;\n\tint id;\n\tstruct ida ida;\n\tstruct device dev;\n\tstruct dev_pagemap *pgmap;\n\tbool memmap_on_memory;\n\tint nr_range;\n\tstruct dev_dax_range *ranges;\n};\n\nstruct dev_dax_data {\n\tstruct dax_region *dax_region;\n\tstruct dev_pagemap *pgmap;\n\tresource_size_t size;\n\tint id;\n\tbool memmap_on_memory;\n};\n\nstruct dev_dax_range {\n\tlong unsigned int pgoff;\n\tstruct range range;\n\tstruct dax_mapping *mapping;\n};\n\nstruct dev_exception_item {\n\tu32 major;\n\tu32 minor;\n\tshort int type;\n\tshort int access;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct md_rdev;\n\nstruct dev_info {\n\tstruct md_rdev *rdev;\n\tsector_t end_sector;\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct iommu_device;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n\tu32 max_pasids;\n\tu32 attach_deferred: 1;\n\tu32 pci_32bit_workaround: 1;\n\tu32 require_direct: 1;\n\tu32 shadow_on_flush: 1;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_drop_reason reason;\n};\n\nstruct vmem_altmap {\n\tlong unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct percpu_ref ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tlong unsigned int vmemmap_shift;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n\tint nr_range;\n\tunion {\n\t\tstruct range range;\n\t\tstruct {\n\t\t\tstruct {} __empty_ranges;\n\t\t\tstruct range ranges[0];\n\t\t};\n\t};\n};\n\nstruct vm_fault;\n\nstruct dev_pagemap_ops {\n\tvoid (*folio_free)(struct folio *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n\tint (*memory_failure)(struct dev_pagemap *, long unsigned int, long unsigned int, int);\n\tvoid (*folio_split)(struct folio *, struct folio *);\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n\tint (*set_performance_state)(struct device *, unsigned int);\n};\n\nstruct dev_pm_domain_attach_data {\n\tconst char * const *pd_names;\n\tconst u32 num_pd_names;\n\tconst u32 pd_flags;\n};\n\nstruct device_link;\n\nstruct dev_pm_domain_list {\n\tstruct device **pd_devs;\n\tstruct device_link **pd_links;\n\tu32 *opp_tokens;\n\tu32 num_pds;\n};\n\nstruct opp_table;\n\nstruct dev_pm_opp;\n\ntypedef int (*config_clks_t)(struct device *, struct opp_table *, struct dev_pm_opp *, void *, bool);\n\ntypedef int (*config_regulators_t)(struct device *, struct dev_pm_opp *, struct dev_pm_opp *, struct regulator **, unsigned int);\n\nstruct dev_pm_opp_config {\n\tconst char * const *clk_names;\n\tconfig_clks_t config_clks;\n\tconst char *prop_name;\n\tconfig_regulators_t config_regulators;\n\tconst unsigned int *supported_hw;\n\tunsigned int supported_hw_count;\n\tconst char * const *regulator_names;\n\tstruct device *required_dev;\n\tunsigned int required_dev_index;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nstruct dev_printk_info {\n\tchar subsystem[16];\n\tchar device[48];\n};\n\ntypedef struct device *class_device_t;\n\ntypedef struct device *class_nvdimm_bus_t;\n\ntypedef struct device *class_pm_runtime_active_t;\n\ntypedef class_pm_runtime_active_t class_pm_runtime_active_try_t;\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tstruct device link_dev;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct work_struct rm_work;\n\tbool supplier_preactivated;\n};\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tu8 flags;\n};\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tstruct kobject kobj;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nstruct device_physical_location {\n\tenum device_physical_location_panel panel;\n\tenum device_physical_location_vertical_position vertical_position;\n\tenum device_physical_location_horizontal_position horizontal_position;\n\tbool dock;\n\tbool lid;\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tconst struct device_driver *async_driver;\n\tchar *deferred_probe_reason;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(const struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(const struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tatomic_t rs_n_left;\n\tatomic_t missed;\n\tunsigned int flags;\n\tlong unsigned int begin;\n};\n\nstruct printk_buffers {\n\tchar outbuf[2048];\n\tchar scratchbuf[1024];\n};\n\nstruct devkmsg_user {\n\tatomic64_t seq;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tstruct printk_buffers pbufs;\n};\n\nstruct devlink_dev_stats {\n\tu32 reload_stats[6];\n\tu32 remote_reload_stats[6];\n};\n\nstruct devlink_dpipe_headers;\n\nstruct devlink_ops;\n\nstruct devlink_rel;\n\nstruct devlink {\n\tu32 index;\n\tstruct xarray ports;\n\tstruct list_head rate_list;\n\tstruct list_head sb_list;\n\tstruct list_head dpipe_table_list;\n\tstruct list_head resource_list;\n\tstruct xarray params;\n\tstruct list_head region_list;\n\tstruct list_head reporter_list;\n\tstruct devlink_dpipe_headers *dpipe_headers;\n\tstruct list_head trap_list;\n\tstruct list_head trap_group_list;\n\tstruct list_head trap_policer_list;\n\tstruct list_head linecard_list;\n\tconst struct devlink_ops *ops;\n\tstruct xarray snapshot_ids;\n\tstruct devlink_dev_stats stats;\n\tstruct device *dev;\n\tpossible_net_t _net;\n\tstruct mutex lock;\n\tstruct lock_class_key lock_key;\n\tu8 reload_failed: 1;\n\trefcount_t refcount;\n\tstruct rcu_work rwork;\n\tstruct devlink_rel *rel;\n\tstruct xarray nested_rels;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar priv[0];\n};\n\nstruct devlink_dpipe_header;\n\nstruct devlink_dpipe_action {\n\tenum devlink_dpipe_action_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct genl_info;\n\nstruct devlink_dpipe_dump_ctx {\n\tstruct genl_info *info;\n\tenum devlink_command cmd;\n\tstruct sk_buff *skb;\n\tstruct nlattr *nest;\n\tvoid *hdr;\n};\n\nstruct devlink_dpipe_value;\n\nstruct devlink_dpipe_entry {\n\tu64 index;\n\tstruct devlink_dpipe_value *match_values;\n\tunsigned int match_values_count;\n\tstruct devlink_dpipe_value *action_values;\n\tunsigned int action_values_count;\n\tu64 counter;\n\tbool counter_valid;\n};\n\nstruct devlink_dpipe_field {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int bitwidth;\n\tenum devlink_dpipe_field_mapping_type mapping_type;\n};\n\nstruct devlink_dpipe_header {\n\tconst char *name;\n\tunsigned int id;\n\tstruct devlink_dpipe_field *fields;\n\tunsigned int fields_count;\n\tbool global;\n};\n\nstruct devlink_dpipe_headers {\n\tstruct devlink_dpipe_header **headers;\n\tunsigned int headers_count;\n};\n\nstruct devlink_dpipe_match {\n\tenum devlink_dpipe_match_type type;\n\tunsigned int header_index;\n\tstruct devlink_dpipe_header *header;\n\tunsigned int field_id;\n};\n\nstruct devlink_dpipe_table_ops;\n\nstruct devlink_dpipe_table {\n\tvoid *priv;\n\tstruct list_head list;\n\tconst char *name;\n\tbool counters_enabled;\n\tbool counter_control_extern;\n\tbool resource_valid;\n\tu64 resource_id;\n\tu64 resource_units;\n\tconst struct devlink_dpipe_table_ops *table_ops;\n\tstruct callback_head rcu;\n};\n\nstruct devlink_dpipe_table_ops {\n\tint (*actions_dump)(void *, struct sk_buff *);\n\tint (*matches_dump)(void *, struct sk_buff *);\n\tint (*entries_dump)(void *, bool, struct devlink_dpipe_dump_ctx *);\n\tint (*counters_set_update)(void *, bool);\n\tu64 (*size_get)(void *);\n};\n\nstruct devlink_dpipe_value {\n\tunion {\n\t\tstruct devlink_dpipe_action *action;\n\t\tstruct devlink_dpipe_match *match;\n\t};\n\tunsigned int mapping_value;\n\tbool mapping_valid;\n\tunsigned int value_size;\n\tvoid *value;\n\tvoid *mask;\n};\n\nstruct devlink_flash_component_lookup_ctx {\n\tconst char *lookup_name;\n\tbool lookup_name_found;\n};\n\nstruct devlink_flash_notify {\n\tconst char *status_msg;\n\tconst char *component;\n\tlong unsigned int done;\n\tlong unsigned int total;\n\tlong unsigned int timeout;\n};\n\nstruct firmware;\n\nstruct devlink_flash_update_params {\n\tconst struct firmware *fw;\n\tconst char *component;\n\tu32 overwrite_mask;\n};\n\nstruct devlink_fmsg {\n\tstruct list_head item_list;\n\tint err;\n\tbool putting_binary;\n};\n\nstruct devlink_fmsg_item {\n\tstruct list_head list;\n\tint attrtype;\n\tu8 nla_type;\n\tu16 len;\n\tint value[0];\n};\n\nstruct devlink_health_reporter_ops;\n\nstruct devlink_port;\n\nstruct devlink_health_reporter {\n\tstruct list_head list;\n\tvoid *priv;\n\tconst struct devlink_health_reporter_ops *ops;\n\tstruct devlink *devlink;\n\tstruct devlink_port *devlink_port;\n\tstruct devlink_fmsg *dump_fmsg;\n\tu64 graceful_period;\n\tu64 burst_period;\n\tbool auto_recover;\n\tbool auto_dump;\n\tu8 health_state;\n\tu64 dump_ts;\n\tu64 dump_real_ts;\n\tu64 error_count;\n\tu64 recovery_count;\n\tu64 last_recovery_ts;\n};\n\nstruct devlink_health_reporter_ops {\n\tchar *name;\n\tint (*recover)(struct devlink_health_reporter *, void *, struct netlink_ext_ack *);\n\tint (*dump)(struct devlink_health_reporter *, struct devlink_fmsg *, void *, struct netlink_ext_ack *);\n\tint (*diagnose)(struct devlink_health_reporter *, struct devlink_fmsg *, struct netlink_ext_ack *);\n\tint (*test)(struct devlink_health_reporter *, struct netlink_ext_ack *);\n\tu64 default_graceful_period;\n\tu64 default_burst_period;\n};\n\nstruct devlink_info_req {\n\tstruct sk_buff *msg;\n\tvoid (*version_cb)(const char *, enum devlink_info_version_type, void *);\n\tvoid *version_cb_priv;\n};\n\nstruct devlink_linecard_ops;\n\nstruct devlink_linecard_type;\n\nstruct devlink_linecard {\n\tstruct list_head list;\n\tstruct devlink *devlink;\n\tunsigned int index;\n\tconst struct devlink_linecard_ops *ops;\n\tvoid *priv;\n\tenum devlink_linecard_state state;\n\tstruct mutex state_lock;\n\tconst char *type;\n\tstruct devlink_linecard_type *types;\n\tunsigned int types_count;\n\tu32 rel_index;\n};\n\nstruct devlink_linecard_ops {\n\tint (*provision)(struct devlink_linecard *, void *, const char *, const void *, struct netlink_ext_ack *);\n\tint (*unprovision)(struct devlink_linecard *, void *, struct netlink_ext_ack *);\n\tbool (*same_provision)(struct devlink_linecard *, void *, const char *, const void *);\n\tunsigned int (*types_count)(struct devlink_linecard *, void *);\n\tvoid (*types_get)(struct devlink_linecard *, void *, unsigned int, const char **, const void **);\n};\n\nstruct devlink_linecard_type {\n\tconst char *type;\n\tconst void *priv;\n};\n\nstruct devlink_nl_dump_state {\n\tlong unsigned int instance;\n\tint idx;\n\tunion {\n\t\tstruct {\n\t\t\tu64 start_offset;\n\t\t};\n\t\tstruct {\n\t\t\tu64 dump_ts;\n\t\t};\n\t};\n};\n\nstruct devlink_obj_desc;\n\nstruct devlink_nl_sock_priv {\n\tstruct devlink_obj_desc *flt;\n\tspinlock_t flt_lock;\n};\n\nstruct devlink_obj_desc {\n\tstruct callback_head rcu;\n\tconst char *bus_name;\n\tconst char *dev_name;\n\tunsigned int port_index;\n\tbool port_index_valid;\n\tlong int data[0];\n};\n\nstruct devlink_sb_pool_info;\n\nstruct devlink_trap;\n\nstruct devlink_trap_group;\n\nstruct devlink_trap_policer;\n\nstruct devlink_port_new_attrs;\n\nstruct devlink_rate;\n\nstruct devlink_ops {\n\tu32 supported_flash_update_params;\n\tlong unsigned int reload_actions;\n\tlong unsigned int reload_limits;\n\tint (*reload_down)(struct devlink *, bool, enum devlink_reload_action, enum devlink_reload_limit, struct netlink_ext_ack *);\n\tint (*reload_up)(struct devlink *, enum devlink_reload_action, enum devlink_reload_limit, u32 *, struct netlink_ext_ack *);\n\tint (*sb_pool_get)(struct devlink *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*sb_pool_set)(struct devlink *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*sb_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *);\n\tint (*sb_port_pool_set)(struct devlink_port *, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_tc_pool_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*sb_tc_pool_bind_set)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_occ_snapshot)(struct devlink *, unsigned int);\n\tint (*sb_occ_max_clear)(struct devlink *, unsigned int);\n\tint (*sb_occ_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *, u32 *);\n\tint (*sb_occ_tc_port_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*eswitch_mode_get)(struct devlink *, u16 *);\n\tint (*eswitch_mode_set)(struct devlink *, u16, struct netlink_ext_ack *);\n\tint (*eswitch_inline_mode_get)(struct devlink *, u8 *);\n\tint (*eswitch_inline_mode_set)(struct devlink *, u8, struct netlink_ext_ack *);\n\tint (*eswitch_encap_mode_get)(struct devlink *, enum devlink_eswitch_encap_mode *);\n\tint (*eswitch_encap_mode_set)(struct devlink *, enum devlink_eswitch_encap_mode, struct netlink_ext_ack *);\n\tint (*info_get)(struct devlink *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*flash_update)(struct devlink *, struct devlink_flash_update_params *, struct netlink_ext_ack *);\n\tint (*trap_init)(struct devlink *, const struct devlink_trap *, void *);\n\tvoid (*trap_fini)(struct devlink *, const struct devlink_trap *, void *);\n\tint (*trap_action_set)(struct devlink *, const struct devlink_trap *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_group_init)(struct devlink *, const struct devlink_trap_group *);\n\tint (*trap_group_set)(struct devlink *, const struct devlink_trap_group *, const struct devlink_trap_policer *, struct netlink_ext_ack *);\n\tint (*trap_group_action_set)(struct devlink *, const struct devlink_trap_group *, enum devlink_trap_action, struct netlink_ext_ack *);\n\tint (*trap_drop_counter_get)(struct devlink *, const struct devlink_trap *, u64 *);\n\tint (*trap_policer_init)(struct devlink *, const struct devlink_trap_policer *);\n\tvoid (*trap_policer_fini)(struct devlink *, const struct devlink_trap_policer *);\n\tint (*trap_policer_set)(struct devlink *, const struct devlink_trap_policer *, u64, u64, struct netlink_ext_ack *);\n\tint (*trap_policer_counter_get)(struct devlink *, const struct devlink_trap_policer *, u64 *);\n\tint (*port_new)(struct devlink *, const struct devlink_port_new_attrs *, struct netlink_ext_ack *, struct devlink_port **);\n\tint (*rate_leaf_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_leaf_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_tx_share_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_max_set)(struct devlink_rate *, void *, u64, struct netlink_ext_ack *);\n\tint (*rate_node_tx_priority_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tx_weight_set)(struct devlink_rate *, void *, u32, struct netlink_ext_ack *);\n\tint (*rate_node_tc_bw_set)(struct devlink_rate *, void *, u32 *, struct netlink_ext_ack *);\n\tint (*rate_node_new)(struct devlink_rate *, void **, struct netlink_ext_ack *);\n\tint (*rate_node_del)(struct devlink_rate *, void *, struct netlink_ext_ack *);\n\tint (*rate_leaf_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tint (*rate_node_parent_set)(struct devlink_rate *, struct devlink_rate *, void *, void *, struct netlink_ext_ack *);\n\tbool (*selftest_check)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n\tenum devlink_selftest_status (*selftest_run)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n};\n\nstruct devlink_param_gset_ctx;\n\nunion devlink_param_value;\n\nstruct devlink_param {\n\tu32 id;\n\tconst char *name;\n\tbool generic;\n\tenum devlink_param_type type;\n\tlong unsigned int supported_cmodes;\n\tint (*get)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*set)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*validate)(struct devlink *, u32, union devlink_param_value, struct netlink_ext_ack *);\n\tint (*get_default)(struct devlink *, u32, struct devlink_param_gset_ctx *, struct netlink_ext_ack *);\n\tint (*reset_default)(struct devlink *, u32, enum devlink_param_cmode, struct netlink_ext_ack *);\n};\n\nunion devlink_param_value {\n\tu8 vu8;\n\tu16 vu16;\n\tu32 vu32;\n\tu64 vu64;\n\tchar vstr[32];\n\tbool vbool;\n};\n\nstruct devlink_param_gset_ctx {\n\tunion devlink_param_value val;\n\tenum devlink_param_cmode cmode;\n};\n\nstruct devlink_param_item {\n\tstruct list_head list;\n\tconst struct devlink_param *param;\n\tunion devlink_param_value driverinit_value;\n\tbool driverinit_value_valid;\n\tunion devlink_param_value driverinit_value_new;\n\tbool driverinit_value_new_valid;\n\tunion devlink_param_value driverinit_default;\n};\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu32 controller;\n\tu16 pf;\n\tu16 vf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_pci_sf_attrs {\n\tu32 controller;\n\tu32 sf;\n\tu16 pf;\n\tu8 external: 1;\n};\n\nstruct devlink_port_attrs {\n\tu8 split: 1;\n\tu8 splittable: 1;\n\tu8 no_phys_port_name: 1;\n\tu32 lanes;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t\tstruct devlink_port_pci_sf_attrs pci_sf;\n\t};\n};\n\nstruct devlink_port_ops;\n\nstruct ib_device;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head region_list;\n\tstruct devlink *devlink;\n\tconst struct devlink_port_ops *ops;\n\tunsigned int index;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tint ifindex;\n\t\t\tchar ifname[16];\n\t\t} type_eth;\n\t\tstruct {\n\t\t\tstruct ib_device *ibdev;\n\t\t} type_ib;\n\t};\n\tstruct devlink_port_attrs attrs;\n\tu8 attrs_set: 1;\n\tu8 switch_port: 1;\n\tu8 registered: 1;\n\tu8 initialized: 1;\n\tstruct delayed_work type_warn_dw;\n\tstruct list_head reporter_list;\n\tstruct devlink_rate *devlink_rate;\n\tstruct devlink_linecard *linecard;\n\tu32 rel_index;\n};\n\nstruct devlink_port_new_attrs {\n\tenum devlink_port_flavour flavour;\n\tunsigned int port_index;\n\tu32 controller;\n\tu32 sfnum;\n\tu16 pfnum;\n\tu8 port_index_valid: 1;\n\tu8 controller_valid: 1;\n\tu8 sfnum_valid: 1;\n};\n\nstruct devlink_port_ops {\n\tint (*port_split)(struct devlink *, struct devlink_port *, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_del)(struct devlink *, struct devlink_port *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_get)(struct devlink_port *, u8 *, int *, struct netlink_ext_ack *);\n\tint (*port_fn_hw_addr_set)(struct devlink_port *, const u8 *, int, struct netlink_ext_ack *);\n\tint (*port_fn_roce_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_roce_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_migratable_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_state_get)(struct devlink_port *, enum devlink_port_fn_state *, enum devlink_port_fn_opstate *, struct netlink_ext_ack *);\n\tint (*port_fn_state_set)(struct devlink_port *, enum devlink_port_fn_state, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_crypto_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_get)(struct devlink_port *, bool *, struct netlink_ext_ack *);\n\tint (*port_fn_ipsec_packet_set)(struct devlink_port *, bool, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_get)(struct devlink_port *, u32 *, struct netlink_ext_ack *);\n\tint (*port_fn_max_io_eqs_set)(struct devlink_port *, u32, struct netlink_ext_ack *);\n};\n\nstruct devlink_port_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink_port *, const struct devlink_port_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\nstruct devlink_rate {\n\tstruct list_head list;\n\tenum devlink_rate_type type;\n\tstruct devlink *devlink;\n\tvoid *priv;\n\tu64 tx_share;\n\tu64 tx_max;\n\tstruct devlink_rate *parent;\n\tunion {\n\t\tstruct devlink_port *devlink_port;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t\trefcount_t refcnt;\n\t\t};\n\t};\n\tu32 tx_priority;\n\tu32 tx_weight;\n\tu32 tc_bw[8];\n};\n\nstruct devlink_region_ops;\n\nstruct devlink_region {\n\tstruct devlink *devlink;\n\tstruct devlink_port *port;\n\tstruct list_head list;\n\tunion {\n\t\tconst struct devlink_region_ops *ops;\n\t\tconst struct devlink_port_region_ops *port_ops;\n\t};\n\tstruct mutex snapshot_lock;\n\tstruct list_head snapshot_list;\n\tu32 max_snapshots;\n\tu32 cur_snapshots;\n\tu64 size;\n};\n\nstruct devlink_region_ops {\n\tconst char *name;\n\tvoid (*destructor)(const void *);\n\tint (*snapshot)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u8 **);\n\tint (*read)(struct devlink *, const struct devlink_region_ops *, struct netlink_ext_ack *, u64, u32, u8 *);\n\tvoid *priv;\n};\n\ntypedef void devlink_rel_notify_cb_t(struct devlink *, u32);\n\ntypedef void devlink_rel_cleanup_cb_t(struct devlink *, u32, u32);\n\nstruct devlink_rel {\n\tu32 index;\n\trefcount_t refcount;\n\tu32 devlink_index;\n\tstruct {\n\t\tu32 devlink_index;\n\t\tu32 obj_index;\n\t\tdevlink_rel_notify_cb_t *notify_cb;\n\t\tdevlink_rel_cleanup_cb_t *cleanup_cb;\n\t\tstruct delayed_work notify_work;\n\t} nested_in;\n};\n\nstruct devlink_reload_combination {\n\tenum devlink_reload_action action;\n\tenum devlink_reload_limit limit;\n};\n\nstruct devlink_resource_size_params {\n\tu64 size_min;\n\tu64 size_max;\n\tu64 size_granularity;\n\tenum devlink_resource_unit unit;\n};\n\ntypedef u64 devlink_resource_occ_get_t(void *);\n\nstruct devlink_resource {\n\tconst char *name;\n\tu64 id;\n\tu64 size;\n\tu64 size_new;\n\tbool size_valid;\n\tstruct devlink_resource *parent;\n\tstruct devlink_resource_size_params size_params;\n\tstruct list_head list;\n\tstruct list_head resource_list;\n\tdevlink_resource_occ_get_t *occ_get;\n\tvoid *occ_get_priv;\n};\n\nstruct devlink_sb {\n\tstruct list_head list;\n\tunsigned int index;\n\tu32 size;\n\tu16 ingress_pools_count;\n\tu16 egress_pools_count;\n\tu16 ingress_tc_count;\n\tu16 egress_tc_count;\n};\n\nstruct devlink_sb_pool_info {\n\tenum devlink_sb_pool_type pool_type;\n\tu32 size;\n\tenum devlink_sb_threshold_type threshold_type;\n\tu32 cell_size;\n};\n\nstruct devlink_snapshot {\n\tstruct list_head list;\n\tstruct devlink_region *region;\n\tu8 *data;\n\tu32 id;\n};\n\nstruct devlink_stats {\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct devlink_trap {\n\tenum devlink_trap_type type;\n\tenum devlink_trap_action init_action;\n\tbool generic;\n\tu16 id;\n\tconst char *name;\n\tu16 init_group_id;\n\tu32 metadata_cap;\n};\n\nstruct devlink_trap_group {\n\tconst char *name;\n\tu16 id;\n\tbool generic;\n\tu32 init_policer_id;\n};\n\nstruct devlink_trap_policer_item;\n\nstruct devlink_trap_group_item {\n\tconst struct devlink_trap_group *group;\n\tstruct devlink_trap_policer_item *policer_item;\n\tstruct list_head list;\n\tstruct devlink_stats *stats;\n};\n\nstruct devlink_trap_item {\n\tconst struct devlink_trap *trap;\n\tstruct devlink_trap_group_item *group_item;\n\tstruct list_head list;\n\tenum devlink_trap_action action;\n\tstruct devlink_stats *stats;\n\tvoid *priv;\n};\n\nstruct flow_action_cookie;\n\nstruct devlink_trap_metadata {\n\tconst char *trap_name;\n\tconst char *trap_group_name;\n\tstruct net_device *input_dev;\n\tnetdevice_tracker dev_tracker;\n\tconst struct flow_action_cookie *fa_cookie;\n\tenum devlink_trap_type trap_type;\n};\n\nstruct devlink_trap_policer {\n\tu32 id;\n\tu64 init_rate;\n\tu64 init_burst;\n\tu64 max_rate;\n\tu64 min_rate;\n\tu64 max_burst;\n\tu64 min_burst;\n};\n\nstruct devlink_trap_policer_item {\n\tconst struct devlink_trap_policer *policer;\n\tu64 rate;\n\tu64 burst;\n\tstruct list_head list;\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct dim_stats {\n\tint ppms;\n\tint bpms;\n\tint epms;\n\tint cpms;\n\tint cpe_ratio;\n};\n\nstruct dim_sample {\n\tktime_t time;\n\tu32 pkt_ctr;\n\tu32 byte_ctr;\n\tu16 event_ctr;\n\tu32 comp_ctr;\n};\n\nstruct dim {\n\tu8 state;\n\tstruct dim_stats prev_stats;\n\tstruct dim_sample start_sample;\n\tstruct dim_sample measuring_sample;\n\tstruct work_struct work;\n\tvoid *priv;\n\tu8 profile_ix;\n\tu8 mode;\n\tu8 tune_state;\n\tu8 steps_right;\n\tu8 steps_left;\n\tu8 tired;\n};\n\nstruct dim_cq_moder {\n\tu16 usec;\n\tu16 pkts;\n\tu16 comps;\n\tu8 cq_period_mode;\n\tstruct callback_head rcu;\n};\n\nstruct dim_irq_moder {\n\tu8 profile_flags;\n\tu8 coal_flags;\n\tu8 dim_rx_mode;\n\tu8 dim_tx_mode;\n\tstruct dim_cq_moder *rx_profile;\n\tstruct dim_cq_moder *tx_profile;\n\tvoid (*rx_dim_work)(struct work_struct *);\n\tvoid (*tx_dim_work)(struct work_struct *);\n};\n\nstruct dimm_info {\n\tstruct device dev;\n\tchar label[32];\n\tunsigned int location[3];\n\tstruct mem_ctl_info *mci;\n\tunsigned int idx;\n\tu32 grain;\n\tenum dev_type dtype;\n\tenum mem_type mtype;\n\tenum edac_type edac_mode;\n\tu32 nr_pages;\n\tunsigned int csrow;\n\tunsigned int cschannel;\n\tu16 smbios_handle;\n\tu32 ce_count;\n\tu32 ue_count;\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\nstruct dio {\n\tint flags;\n\tblk_opf_t opf;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tbool is_pinned;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 64;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n};\n\nstruct dioattr {\n\t__u32 d_mem;\n\t__u32 d_miniosz;\n\t__u32 d_maxiosz;\n};\n\nstruct dir_context;\n\ntypedef bool (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tloff_t pos;\n\tint count;\n\tunsigned int dt_flags_mask;\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\ttime64_t mtime;\n\tchar name[0];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n\tu64 cookie;\n\tbool initialized;\n};\n\nstruct wb_domain;\n\nstruct dirty_throttle_control {\n\tstruct wb_domain *dom;\n\tstruct dirty_throttle_control *gdtc;\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int limit;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n\tbool freerun;\n\tbool dirty_exceeded;\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct div_result {\n\tu64 result_high;\n\tu64 result_low;\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tunsigned int dl_nr_running;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tbool overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 max_bw;\n\tu64 bw_ratio;\n};\n\nstruct dm_arg {\n\tunsigned int min;\n\tunsigned int max;\n\tchar *error;\n};\n\nstruct dm_arg_set {\n\tunsigned int argc;\n\tchar **argv;\n};\n\nstruct dm_blkdev_id {\n\tu8 *id;\n\tenum blk_unique_id type;\n};\n\nstruct dm_dev {\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct dax_device *dax_dev;\n\tblk_mode_t mode;\n\tchar name[16];\n};\n\nstruct dm_dev_internal {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev *dm_dev;\n};\n\nstruct dm_ioctl {\n\t__u32 version[3];\n\t__u32 data_size;\n\t__u32 data_start;\n\t__u32 target_count;\n\t__s32 open_count;\n\t__u32 flags;\n\t__u32 event_nr;\n\t__u32 padding;\n\t__u64 dev;\n\tchar name[128];\n\tchar uuid[129];\n\tchar data[7];\n};\n\nstruct dm_target_spec;\n\nstruct dm_device {\n\tstruct dm_ioctl dmi;\n\tstruct dm_target_spec *table[256];\n\tchar *target_args_array[256];\n\tstruct list_head list;\n};\n\nstruct dm_file {\n\tvolatile unsigned int global_event_nr;\n};\n\nstruct dm_ima_device_table_metadata {\n\tchar *device_metadata;\n\tunsigned int device_metadata_len;\n\tunsigned int num_targets;\n\tchar *hash;\n\tunsigned int hash_len;\n};\n\nstruct dm_ima_measurements {\n\tstruct dm_ima_device_table_metadata active_table;\n\tstruct dm_ima_device_table_metadata inactive_table;\n\tunsigned int dm_version_str_len;\n};\n\nstruct dm_stats_aux {\n\tbool merged;\n\tlong long unsigned int duration_ns;\n};\n\nstruct dm_target;\n\nstruct dm_target_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tunsigned int target_bio_nr;\n\tstruct dm_io *io;\n\tstruct dm_target *ti;\n\tunsigned int *len_ptr;\n\tsector_t old_sector;\n\tstruct bio clone;\n};\n\nstruct mapped_device;\n\nstruct dm_io {\n\tshort unsigned int magic;\n\tblk_short_t flags;\n\tspinlock_t lock;\n\tlong unsigned int start_time;\n\tvoid *data;\n\tstruct dm_io *next;\n\tstruct dm_stats_aux stats_aux;\n\tblk_status_t status;\n\tbool requeue_flush_with_data;\n\tatomic_t io_count;\n\tstruct mapped_device *md;\n\tstruct bio *orig_bio;\n\tunsigned int sector_offset;\n\tunsigned int sectors;\n\tstruct dm_target_io tio;\n};\n\nstruct dm_io_client {\n\tmempool_t pool;\n\tstruct bio_set bios;\n};\n\nstruct page_list;\n\nstruct dm_io_memory {\n\tenum dm_io_mem_type type;\n\tunsigned int offset;\n\tunion {\n\t\tstruct page_list *pl;\n\t\tstruct bio *bio;\n\t\tvoid *vma;\n\t\tvoid *addr;\n\t} ptr;\n};\n\ntypedef void (*io_notify_fn)(long unsigned int, void *);\n\nstruct dm_io_notify {\n\tio_notify_fn fn;\n\tvoid *context;\n};\n\nstruct dm_io_region {\n\tstruct block_device *bdev;\n\tsector_t sector;\n\tsector_t count;\n};\n\nstruct dm_io_request {\n\tblk_opf_t bi_opf;\n\tstruct dm_io_memory mem;\n\tstruct dm_io_notify notify;\n\tstruct dm_io_client *client;\n};\n\nstruct dm_kcopyd_throttle;\n\nstruct dm_kcopyd_client {\n\tstruct page_list *pages;\n\tunsigned int nr_reserved_pages;\n\tunsigned int nr_free_pages;\n\tunsigned int sub_job_size;\n\tstruct dm_io_client *io_client;\n\twait_queue_head_t destroyq;\n\tmempool_t job_pool;\n\tstruct workqueue_struct *kcopyd_wq;\n\tstruct work_struct kcopyd_work;\n\tstruct dm_kcopyd_throttle *throttle;\n\tatomic_t nr_jobs;\n\tspinlock_t job_lock;\n\tstruct list_head callback_jobs;\n\tstruct list_head complete_jobs;\n\tstruct list_head io_jobs;\n\tstruct list_head pages_jobs;\n};\n\nstruct dm_kcopyd_throttle {\n\tunsigned int throttle;\n\tunsigned int num_io_jobs;\n\tunsigned int io_period;\n\tunsigned int total_period;\n\tunsigned int last_jiffies;\n};\n\nstruct dm_kobject_holder {\n\tstruct kobject kobj;\n\tstruct completion completion;\n};\n\nstruct dm_md_mempools {\n\tstruct bio_set bs;\n\tstruct bio_set io_bs;\n};\n\nstruct dm_name_list {\n\t__u64 dev;\n\t__u32 next;\n\tchar name[0];\n};\n\nstruct pr_keys;\n\nstruct pr_held_reservation;\n\nstruct dm_pr {\n\tu64 old_key;\n\tu64 new_key;\n\tu32 flags;\n\tbool abort;\n\tbool fail_early;\n\tint ret;\n\tenum pr_type type;\n\tstruct pr_keys *read_keys;\n\tstruct pr_held_reservation *rsv;\n};\n\nstruct dm_rq_target_io;\n\nstruct dm_rq_clone_bio_info {\n\tstruct bio *orig;\n\tstruct dm_rq_target_io *tio;\n\tstruct bio clone;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_worker;\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nunion map_info {\n\tvoid *ptr;\n};\n\nstruct dm_rq_target_io {\n\tstruct mapped_device *md;\n\tstruct dm_target *ti;\n\tstruct request *orig;\n\tstruct request *clone;\n\tstruct kthread_work work;\n\tblk_status_t error;\n\tunion map_info info;\n\tstruct dm_stats_aux stats_aux;\n\tlong unsigned int duration_jiffies;\n\tunsigned int n_sectors;\n\tunsigned int completed;\n};\n\nstruct dm_stat_percpu {\n\tlong long unsigned int sectors[2];\n\tlong long unsigned int ios[2];\n\tlong long unsigned int merges[2];\n\tlong long unsigned int ticks[2];\n\tlong long unsigned int io_ticks[2];\n\tlong long unsigned int io_ticks_total;\n\tlong long unsigned int time_in_queue;\n\tlong long unsigned int *histogram;\n};\n\nstruct dm_stat_shared {\n\tatomic_t in_flight[2];\n\tlong long unsigned int stamp;\n\tstruct dm_stat_percpu tmp;\n};\n\nstruct dm_stat {\n\tstruct list_head list_entry;\n\tint id;\n\tunsigned int stat_flags;\n\tsize_t n_entries;\n\tsector_t start;\n\tsector_t end;\n\tsector_t step;\n\tunsigned int n_histogram_entries;\n\tlong long unsigned int *histogram_boundaries;\n\tconst char *program_id;\n\tconst char *aux_data;\n\tstruct callback_head callback_head;\n\tsize_t shared_alloc_size;\n\tsize_t percpu_alloc_size;\n\tsize_t histogram_alloc_size;\n\tstruct dm_stat_percpu *stat_percpu[2048];\n\tstruct dm_stat_shared stat_shared[0];\n};\n\nstruct dm_stats_last_position;\n\nstruct dm_stats {\n\tstruct mutex mutex;\n\tstruct list_head list;\n\tstruct dm_stats_last_position *last;\n\tbool precise_timestamps;\n};\n\nstruct dm_stats_last_position {\n\tsector_t last_sector;\n\tunsigned int last_rw;\n};\n\nstruct dm_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mapped_device *, char *);\n\tssize_t (*store)(struct mapped_device *, const char *, size_t);\n};\n\nstruct target_type;\n\nstruct dm_table {\n\tstruct mapped_device *md;\n\tenum dm_queue_mode type;\n\tunsigned int depth;\n\tunsigned int counts[16];\n\tsector_t *index[16];\n\tunsigned int num_targets;\n\tunsigned int num_allocated;\n\tsector_t *highs;\n\tstruct dm_target *targets;\n\tstruct target_type *immutable_target_type;\n\tbool integrity_supported: 1;\n\tbool singleton: 1;\n\tbool flush_bypasses_map: 1;\n\tblk_mode_t mode;\n\tstruct list_head devices;\n\tvoid (*event_fn)(void *);\n\tvoid *event_context;\n\tstruct dm_md_mempools *mempools;\n};\n\nstruct dm_target {\n\tstruct dm_table *table;\n\tstruct target_type *type;\n\tsector_t begin;\n\tsector_t len;\n\tuint32_t max_io_len;\n\tunsigned int num_flush_bios;\n\tunsigned int num_discard_bios;\n\tunsigned int num_secure_erase_bios;\n\tunsigned int num_write_zeroes_bios;\n\tunsigned int per_io_data_size;\n\tvoid *private;\n\tchar *error;\n\tbool flush_supported: 1;\n\tbool discards_supported: 1;\n\tbool zone_reset_all_supported: 1;\n\tbool max_discard_granularity: 1;\n\tbool limit_swap_bios: 1;\n\tbool emulate_zone_append: 1;\n\tbool accounts_remapped_io: 1;\n\tbool needs_bio_set_dev: 1;\n\tbool flush_bypasses_map: 1;\n\tbool mempool_needs_integrity: 1;\n};\n\nstruct dm_target_deps {\n\t__u32 count;\n\t__u32 padding;\n\t__u64 dev[0];\n};\n\nstruct dm_target_msg {\n\t__u64 sector;\n\tchar message[0];\n};\n\nstruct dm_target_spec {\n\t__u64 sector_start;\n\t__u64 length;\n\t__s32 status;\n\t__u32 next;\n\tchar target_type[16];\n};\n\nstruct dm_target_versions {\n\t__u32 next;\n\t__u32 version[3];\n\tchar name[0];\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct dm_uevent {\n\tstruct mapped_device *md;\n\tenum kobject_action action;\n\tstruct kobj_uevent_env ku_env;\n\tstruct list_head elist;\n\tchar name[128];\n\tchar uuid[129];\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nstruct dmaengine_result;\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dma_chan;\n\nstruct dmaengine_unmap_data;\n\nstruct dma_descriptor_metadata_ops;\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n};\n\nstruct dma_block {\n\tstruct dma_block *next_block;\n\tdma_addr_t dma;\n};\n\nstruct iosys_map {\n\tunion {\n\t\tvoid *vaddr_iomem;\n\t\tvoid *vaddr;\n\t};\n\tbool is_iomem;\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf_ops;\n\nstruct dma_resv;\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tunsigned int vmapping_counter;\n\tstruct iosys_map vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_in;\n\tstruct dma_buf_poll_cb_t cb_out;\n};\n\nstruct dma_buf_attachment;\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\nstruct dma_iova_state;\n\nstruct dma_buf_dma {\n\tstruct sg_table sgt;\n\tstruct dma_iova_state *state;\n\tsize_t size;\n};\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tint (*vmap)(struct dma_buf *, struct iosys_map *);\n\tvoid (*vunmap)(struct dma_buf *, struct iosys_map *);\n};\n\nstruct dma_buf_sg_table_wrapper {\n\tstruct sg_table *original;\n\tstruct sg_table wrapper;\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_chan___2 {\n\tint lock;\n\tconst char *device_id;\n};\n\nstruct dma_device;\n\nstruct dma_chan_dev;\n\nstruct dma_chan_percpu;\n\nstruct dma_router;\n\nstruct dma_chan {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan *chan;\n\tstruct device device;\n\tint dev_id;\n\tbool chan_dma_dev;\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_coherent_mem {\n\tvoid *virt_base;\n\tdma_addr_t device_base;\n\tlong unsigned int pfn_base;\n\tint size;\n\tlong unsigned int *bitmap;\n\tspinlock_t spinlock;\n\tbool use_dev_dma_pfn_offset;\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan *, void *);\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nstruct dma_vec;\n\nstruct dma_interleaved_template;\n\nstruct dma_slave_caps;\n\nstruct dma_slave_config;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan *);\n\tint (*device_router_config)(struct dma_chan *);\n\tvoid (*device_free_chan_resources)(struct dma_chan *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_peripheral_dma_vec)(struct dma_chan *, const struct dma_vec *, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan *, struct dma_interleaved_template *, long unsigned int);\n\tvoid (*device_caps)(struct dma_chan *, struct dma_slave_caps *);\n\tint (*device_config)(struct dma_chan *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan *);\n\tint (*device_resume)(struct dma_chan *);\n\tint (*device_terminate_all)(struct dma_chan *);\n\tvoid (*device_synchronize)(struct dma_chan *);\n\tenum dma_status (*device_tx_status)(struct dma_chan *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n};\n\nstruct dma_fence_array;\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n\tstruct dma_fence_array_cb callbacks[0];\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tstruct dma_fence *prev;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tunion {\n\t\tstruct dma_fence_cb cb;\n\t\tstruct irq_work work;\n\t};\n\tspinlock_t lock;\n};\n\nstruct dma_fence_ops {\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*set_deadline)(struct dma_fence *, ktime_t);\n};\n\nstruct dma_fence_unwrap {\n\tstruct dma_fence *chain;\n\tstruct dma_fence *array;\n\tunsigned int index;\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nstruct dma_iova_state {\n\tdma_addr_t addr;\n\tu64 __size;\n};\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tstruct page * (*alloc_pages_op)(struct device *, size_t, dma_addr_t *, enum dma_data_direction, gfp_t);\n\tvoid (*free_pages)(struct device *, size_t, struct page *, dma_addr_t, enum dma_data_direction);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_phys)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_phys)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tsize_t (*opt_mapping_size)(void);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tstruct dma_block *next_block;\n\tsize_t nr_blocks;\n\tsize_t nr_active;\n\tsize_t nr_pages;\n\tstruct device *dev;\n\tunsigned int size;\n\tunsigned int allocation;\n\tunsigned int boundary;\n\tint node;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct ww_acquire_ctx;\n\nstruct ww_class;\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n\tstruct ww_class *ww_class;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tstruct dma_resv_list *fences;\n};\n\nstruct dma_resv_iter {\n\tstruct dma_resv *obj;\n\tenum dma_resv_usage usage;\n\tstruct dma_fence *fence;\n\tenum dma_resv_usage fence_usage;\n\tunsigned int index;\n\tstruct dma_resv_list *fences;\n\tunsigned int num_fences;\n\tbool is_restarted;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 num_fences;\n\tu32 max_fences;\n\tstruct dma_fence *table[0];\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 min_burst;\n\tu32 max_burst;\n\tu32 max_sg_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tvoid *peripheral_config;\n\tsize_t peripheral_size;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_vec {\n\tdma_addr_t addr;\n\tsize_t len;\n};\n\nstruct dynamic_dma_window_prop;\n\nstruct dma_win {\n\tstruct device_node *device;\n\tconst struct dynamic_dma_window_prop *prop;\n\tbool direct;\n\tstruct list_head list;\n};\n\nstruct dmabuf_cmsg {\n\t__u64 frag_offset;\n\t__u32 frag_size;\n\t__u32 frag_token;\n\t__u32 dmabuf_id;\n\t__u32 flags;\n};\n\nstruct net_iov;\n\nstruct net_iov_area {\n\tstruct net_iov *niovs;\n\tsize_t num_niovs;\n\tlong unsigned int base_virtual;\n};\n\nstruct net_devmem_dmabuf_binding;\n\nstruct dmabuf_genpool_chunk_owner {\n\tstruct net_iov_area area;\n\tstruct net_devmem_dmabuf_binding *binding;\n\tdma_addr_t base_dma_addr;\n};\n\nstruct dmabuf_iter_priv {\n\tstruct dma_buf *dmabuf;\n};\n\nstruct dmabuf_token {\n\t__u32 token_start;\n\t__u32 token_count;\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\nstruct dmaengine_unmap_data {\n\tu8 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct fb_videomode;\n\nstruct dmt_videomode {\n\tu32 dmt_id;\n\tu32 std_2byte_code;\n\tu32 cvt_3byte_code;\n\tconst struct fb_videomode *mode;\n};\n\nstruct dnotify_struct;\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\ntypedef void *fl_owner_t;\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nstruct dns_server_list_v1_header {\n\tstruct dns_payload_header hdr;\n\t__u8 source;\n\t__u8 status;\n\t__u8 nr_servers;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct dpages {\n\tvoid (*get_page)(struct dpages *, struct page **, long unsigned int *, unsigned int *);\n\tvoid (*next_page)(struct dpages *);\n\tunion {\n\t\tunsigned int context_u;\n\t\tstruct bvec_iter context_bi;\n\t};\n\tvoid *context_ptr;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tshort unsigned int stall_thrs;\n\tlong unsigned int history_head;\n\tlong unsigned int history[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tshort unsigned int stall_max;\n\tlong unsigned int last_reap;\n\tlong unsigned int stall_cnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nstruct module_kobject;\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct drmem_lmb {\n\tu64 base_addr;\n\tu32 drc_index;\n\tu32 aa_index;\n\tu32 flags;\n};\n\nstruct drmem_lmb_info {\n\tstruct drmem_lmb *lmbs;\n\tint n_lmbs;\n\tu64 lmb_size;\n};\n\nstruct drop_reason_list {\n\tconst char * const *reasons;\n\tsize_t n_reasons;\n};\n\nstruct pci_driver;\n\nstruct pci_device_id;\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nstruct regmap;\n\nstruct rtc_device;\n\nstruct ds1307 {\n\tenum ds_type type;\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tconst char *name;\n\tstruct rtc_device *rtc;\n};\n\nstruct ds1307_platform_data {\n\tu8 trickle_charger_setup;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tlocal_lock_t bh_lock;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct dst_ops;\n\nstruct xfrm_state;\n\nstruct uncached_list;\n\nstruct lwtunnel_state;\n\nstruct dst_entry {\n\tunion {\n\t\tstruct net_device *dev;\n\t\tstruct net_device *dev_rcu;\n\t};\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tstruct xfrm_state *xfrm;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\trcuref_t __rcuref;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n\tstruct lwtunnel_state *lwtstate;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tvoid (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *);\n\tvoid (*negative_advice)(struct sock *, struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct dt_cpu_feature {\n\tconst char *name;\n\tuint32_t isa;\n\tuint32_t usable_privilege;\n\tuint32_t hv_support;\n\tuint32_t os_support;\n\tuint32_t hfscr_bit_nr;\n\tuint32_t fscr_bit_nr;\n\tuint32_t hwcap_bit_nr;\n\tlong unsigned int node;\n\tint enabled;\n\tint disabled;\n};\n\nstruct dt_cpu_feature_match {\n\tconst char *name;\n\tint (*enable)(struct dt_cpu_feature *);\n\tu64 cpu_ftr_bit_mask;\n};\n\nstruct dtl_entry;\n\nstruct dtl {\n\tstruct dtl_entry *buf;\n\tint cpu;\n\tint buf_entries;\n\tu64 last_idx;\n\tspinlock_t lock;\n};\n\nstruct dtl_entry {\n\tu8 dispatch_reason;\n\tu8 preempt_reason;\n\t__be16 processor_id;\n\t__be32 enqueue_to_dispatch_time;\n\t__be32 ready_to_enqueue_time;\n\t__be32 waiting_to_ready_time;\n\t__be64 timebase;\n\t__be64 fault_addr;\n\t__be64 srr0;\n\t__be64 srr1;\n};\n\nstruct dtl_worker {\n\tstruct delayed_work work;\n\tint cpu;\n};\n\nstruct dump_obj;\n\nstruct dump_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct dump_obj *, struct dump_attribute *, char *);\n\tssize_t (*store)(struct dump_obj *, struct dump_attribute *, const char *, size_t);\n};\n\nstruct dump_obj {\n\tstruct kobject kobj;\n\tstruct bin_attribute dump_attr;\n\tuint32_t id;\n\tuint32_t type;\n\tuint32_t size;\n\tchar *buffer;\n};\n\nstruct dump_stack_ctx {\n\tstruct bpf_stream_stage *ss;\n\tint err;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct dyn_arch_ftrace {\n\tlong unsigned int ool_stub;\n};\n\nstruct dyn_event_operations;\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(const char *);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dyn_ftrace {\n\tlong unsigned int ip;\n\tlong unsigned int flags;\n\tstruct dyn_arch_ftrace arch;\n};\n\nstruct dynamic_dma_window_prop {\n\t__be32 liobn;\n\t__be64 dma_base;\n\t__be32 tce_shift;\n\t__be32 window_shift;\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nstruct napi_config;\n\nstruct napi_struct {\n\tlong unsigned int state;\n\tstruct list_head poll_list;\n\tint weight;\n\tu32 defer_hard_irqs_count;\n\tint (*poll)(struct napi_struct *, int);\n\tint poll_owner;\n\tint list_owner;\n\tstruct net_device *dev;\n\tstruct sk_buff *skb;\n\tstruct gro_node gro;\n\tstruct hrtimer timer;\n\tstruct task_struct *thread;\n\tlong unsigned int gro_flush_timeout;\n\tlong unsigned int irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tu32 napi_id;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tint irq;\n\tstruct irq_affinity_notify notify;\n\tint napi_rmap_idx;\n\tint index;\n\tstruct napi_config *config;\n};\n\nstruct e1000_eeprom_info {\n\te1000_eeprom_type type;\n\tu16 word_size;\n\tu16 opcode_bits;\n\tu16 address_bits;\n\tu16 delay_usec;\n\tu16 page_size;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\nstruct e1000_shadow_ram;\n\nstruct e1000_hw {\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tvoid *ce4100_gbe_mdio_base_virt;\n\te1000_mac_type mac_type;\n\te1000_phy_type phy_type;\n\tu32 phy_init_script;\n\te1000_media_type media_type;\n\tvoid *back;\n\tstruct e1000_shadow_ram *eeprom_shadow_ram;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\te1000_fc_type fc;\n\te1000_bus_speed bus_speed;\n\te1000_bus_width bus_width;\n\te1000_bus_type bus_type;\n\tstruct e1000_eeprom_info eeprom;\n\te1000_ms_type master_slave;\n\te1000_ms_type original_master_slave;\n\te1000_ffe_config ffe_config_state;\n\tu32 asf_firmware_present;\n\tu32 eeprom_semaphore_present;\n\tlong unsigned int io_base;\n\tu32 phy_id;\n\tu32 phy_revision;\n\tu32 phy_addr;\n\tu32 original_fc;\n\tu32 txcw;\n\tu32 autoneg_failed;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tu32 mc_filter_type;\n\tu32 num_mc_addrs;\n\tu32 collision_delta;\n\tu32 tx_packet_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tbool tx_pkt_filtering;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tu16 phy_spd_default;\n\tu16 autoneg_advertised;\n\tu16 pci_cmd_word;\n\tu16 fc_high_water;\n\tu16 fc_low_water;\n\tu16 fc_pause_time;\n\tu16 current_ifs_val;\n\tu16 ifs_min_val;\n\tu16 ifs_max_val;\n\tu16 ifs_step_size;\n\tu16 ifs_ratio;\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n\tu8 autoneg;\n\tu8 mdix;\n\tu8 forced_speed_duplex;\n\tu8 wait_autoneg_complete;\n\tu8 dma_fairness;\n\tu8 mac_addr[6];\n\tu8 perm_mac_addr[6];\n\tbool disable_polarity_correction;\n\tbool speed_downgraded;\n\te1000_smart_speed smart_speed;\n\te1000_dsp_config dsp_config_state;\n\tbool get_link_status;\n\tbool serdes_has_link;\n\tbool tbi_compatibility_en;\n\tbool tbi_compatibility_on;\n\tbool laa_is_present;\n\tbool phy_reset_disable;\n\tbool initialize_hw_bits_disable;\n\tbool fc_send_xon;\n\tbool fc_strict_ieee;\n\tbool report_tx_early;\n\tbool adaptive_ifs;\n\tbool ifs_params_forced;\n\tbool in_ifs_mode;\n\tbool mng_reg_access_disabled;\n\tbool leave_av_bit_off;\n\tbool bad_tx_carr_stats_fd;\n\tbool has_smbus;\n};\n\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 txerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorcl;\n\tu64 gorch;\n\tu64 gotcl;\n\tu64 gotch;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rlerrc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 torl;\n\tu64 torh;\n\tu64 totl;\n\tu64 toth;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_info {\n\te1000_cable_length cable_length;\n\te1000_10bt_ext_dist_enable extended_10bt_distance;\n\te1000_rev_polarity cable_polarity;\n\te1000_downshift downshift;\n\te1000_polarity_reversal polarity_correction;\n\te1000_auto_x_mode mdix_mode;\n\te1000_1000t_rx_status local_rx;\n\te1000_1000t_rx_status remote_rx;\n};\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_tx_buffer;\n\nstruct e1000_tx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_tx_buffer *buffer_info;\n\tu16 tdh;\n\tu16 tdt;\n\tbool last_tx_tso;\n};\n\nstruct e1000_rx_buffer;\n\nstruct e1000_rx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_rx_buffer *buffer_info;\n\tstruct sk_buff *rx_skb_top;\n\tint cpu;\n\tu16 rdh;\n\tu16 rdt;\n};\n\nstruct e1000_adapter {\n\tlong unsigned int active_vlans[64];\n\tu16 mng_vlan_id;\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu32 wol;\n\tu32 smartspeed;\n\tu32 en_mng_pt;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tspinlock_t stats_lock;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tu8 fc_autoneg;\n\tstruct e1000_tx_ring *tx_ring;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tu32 gotcl;\n\tu64 gotcl_old;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu8 tx_timeout_factor;\n\tatomic_t tx_fifo_stall;\n\tbool pcix_82544;\n\tbool detect_tx_hung;\n\tbool dump_buffers;\n\tbool (*clean_rx)(struct e1000_adapter *, struct e1000_rx_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_adapter *, struct e1000_rx_ring *, int);\n\tstruct e1000_rx_ring *rx_ring;\n\tstruct napi_struct napi;\n\tint num_tx_queues;\n\tint num_rx_queues;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tbool rx_csum;\n\tu32 gorcl;\n\tu64 gorcl_old;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw hw;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_phy_info phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tu32 test_icr;\n\tstruct e1000_tx_ring test_tx_ring;\n\tstruct e1000_rx_ring test_rx_ring;\n\tint msg_enable;\n\tbool tso_force;\n\tbool smart_power_down;\n\tbool quad_port_a;\n\tlong unsigned int flags;\n\tu32 eeprom_wol;\n\tint bars;\n\tint need_ioport;\n\tbool discarding;\n\tstruct work_struct reset_task;\n\tstruct delayed_work watchdog_task;\n\tstruct delayed_work fifo_stall_task;\n\tstruct delayed_work phy_info_task;\n};\n\nstruct e1000_hw___2;\n\nstruct e1000_mac_operations {\n\ts32 (*id_led_init)(struct e1000_hw___2 *);\n\ts32 (*blink_led)(struct e1000_hw___2 *);\n\tbool (*check_mng_mode)(struct e1000_hw___2 *);\n\ts32 (*check_for_link)(struct e1000_hw___2 *);\n\ts32 (*cleanup_led)(struct e1000_hw___2 *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw___2 *);\n\tvoid (*clear_vfta)(struct e1000_hw___2 *);\n\ts32 (*get_bus_info)(struct e1000_hw___2 *);\n\tvoid (*set_lan_id)(struct e1000_hw___2 *);\n\ts32 (*get_link_up_info)(struct e1000_hw___2 *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw___2 *);\n\ts32 (*led_off)(struct e1000_hw___2 *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw___2 *);\n\ts32 (*init_hw)(struct e1000_hw___2 *);\n\ts32 (*setup_link)(struct e1000_hw___2 *);\n\ts32 (*setup_physical_interface)(struct e1000_hw___2 *);\n\ts32 (*setup_led)(struct e1000_hw___2 *);\n\tvoid (*write_vfta)(struct e1000_hw___2 *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw___2 *);\n\tint (*rar_set)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw___2 *);\n\tu32 (*rar_get_count)(struct e1000_hw___2 *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type type;\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tenum e1000_serdes_link_state serdes_link_state;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tu16 refresh_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_phy_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*cfg_on_link_up)(struct e1000_hw___2 *);\n\ts32 (*check_polarity)(struct e1000_hw___2 *);\n\ts32 (*check_reset_block)(struct e1000_hw___2 *);\n\ts32 (*commit)(struct e1000_hw___2 *);\n\ts32 (*force_speed_duplex)(struct e1000_hw___2 *);\n\ts32 (*get_cfg_done)(struct e1000_hw___2 *);\n\ts32 (*get_cable_length)(struct e1000_hw___2 *);\n\ts32 (*get_info)(struct e1000_hw___2 *);\n\ts32 (*set_page)(struct e1000_hw___2 *, u16);\n\ts32 (*read_reg)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw___2 *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\ts32 (*reset)(struct e1000_hw___2 *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*write_reg)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw___2 *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw___2 *);\n\tvoid (*power_down)(struct e1000_hw___2 *);\n};\n\nstruct e1000_phy_info___2 {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tu32 retry_count;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n\tbool retry_enabled;\n};\n\nstruct e1000_nvm_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*read)(struct e1000_hw___2 *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\tvoid (*reload)(struct e1000_hw___2 *);\n\ts32 (*update)(struct e1000_hw___2 *);\n\ts32 (*valid_led_default)(struct e1000_hw___2 *, u16 *);\n\ts32 (*validate)(struct e1000_hw___2 *);\n\ts32 (*write)(struct e1000_hw___2 *, u16, u16, u16 *);\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_width width;\n\tu16 func;\n};\n\nstruct e1000_dev_spec_82571 {\n\tbool laa_is_present;\n\tu32 smb_counter;\n};\n\nstruct e1000_dev_spec_80003es2lan {\n\tbool mdic_wa_enable;\n};\n\nstruct e1000_shadow_ram___2 {\n\tu16 value;\n\tbool modified;\n};\n\nstruct e1000_dev_spec_ich8lan {\n\tbool kmrn_lock_loss_workaround_enabled;\n\tstruct e1000_shadow_ram___2 shadow_ram[2048];\n\tbool nvm_k1_enabled;\n\tbool eee_disable;\n\tu16 eee_lp_ability;\n\tenum e1000_ulp_state ulp_state;\n};\n\nstruct e1000_adapter___2;\n\nstruct e1000_hw___2 {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *hw_addr;\n\tvoid *flash_address;\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info___2 phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82571 e82571;\n\t\tstruct e1000_dev_spec_80003es2lan e80003es2lan;\n\t\tstruct e1000_dev_spec_ich8lan ich8lan;\n\t} dev_spec;\n};\n\nstruct e1000_hw_stats___2 {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_phy_regs {\n\tu16 bmcr;\n\tu16 bmsr;\n\tu16 advertise;\n\tu16 lpa;\n\tu16 expansion;\n\tu16 ctrl1000;\n\tu16 stat1000;\n\tu16 estatus;\n};\n\nstruct e1000_buffer;\n\nstruct e1000_ring {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\tvoid *head;\n\tvoid *tail;\n\tstruct e1000_buffer *buffer_info;\n\tchar name[21];\n\tu32 ims_val;\n\tu32 itr_val;\n\tvoid *itr_register;\n\tint set_itr;\n\tstruct sk_buff *rx_skb_top;\n};\n\nstruct ifreq;\n\nstruct kernel_hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n\tstruct ifreq *ifr;\n\tbool copied_to_user;\n\tenum hwtstamp_source source;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct timecounter {\n\tstruct cyclecounter *cc;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\nstruct ptp_pin_desc;\n\nstruct ptp_system_timestamp;\n\nstruct system_device_crosststamp;\n\nstruct ptp_clock_request;\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[32];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint n_per_lp;\n\tint pps;\n\tunsigned int supported_perout_flags;\n\tunsigned int supported_extts_flags;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\ts32 (*getmaxphase)(struct ptp_clock_info *);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*getcycles64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n\tint (*perout_loopback)(struct ptp_clock_info *, unsigned int, int);\n};\n\nstruct pm_qos_request {\n\tstruct plist_node node;\n\tstruct pm_qos_constraints *qos;\n};\n\nstruct e1000_info;\n\nstruct msix_entry;\n\nstruct ptp_clock;\n\nstruct e1000_adapter___2 {\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tstruct timer_list blink_timer;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tconst struct e1000_info *ei;\n\tlong unsigned int active_vlans[64];\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu16 mng_vlan_id;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu16 eeprom_vers;\n\tlong unsigned int state;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct e1000_ring *tx_ring;\n\tu32 tx_fifo_limit;\n\tstruct napi_struct napi;\n\tunsigned int uncorr_errors;\n\tunsigned int corr_errors;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tbool detect_tx_hung;\n\tbool tx_hang_recheck;\n\tu8 tx_timeout_factor;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 gotc;\n\tu64 gotc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu32 tx_dma_failed;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tlong: 64;\n\tlong: 64;\n\tbool (*clean_rx)(struct e1000_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_ring *, int, gfp_t);\n\tstruct e1000_ring *rx_ring;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu64 rx_hdr_split;\n\tu32 gorc;\n\tu64 gorc_old;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_dma_failed;\n\tu32 rx_hwtstamp_cleared;\n\tunsigned int rx_ps_pages;\n\tu16 rx_ps_bsize0;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw___2 hw;\n\tspinlock_t stats64_lock;\n\tstruct e1000_hw_stats___2 stats;\n\tstruct e1000_phy_info___2 phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tstruct e1000_phy_regs phy_regs;\n\tstruct e1000_ring test_tx_ring;\n\tstruct e1000_ring test_rx_ring;\n\tu32 test_icr;\n\tu32 msg_enable;\n\tunsigned int num_vectors;\n\tstruct msix_entry *msix_entries;\n\tint int_mode;\n\tu32 eiac_mask;\n\tu32 eeprom_wol;\n\tu32 wol;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\tbool fc_autoneg;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tstruct work_struct downshift_task;\n\tstruct work_struct update_phy_task;\n\tstruct work_struct print_hang_task;\n\tint phy_hang_count;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tstruct kernel_hwtstamp_config hwtstamp_config;\n\tstruct delayed_work systim_overflow_work;\n\tstruct sk_buff *tx_hwtstamp_skb;\n\tlong unsigned int tx_hwtstamp_start;\n\tstruct work_struct tx_hwtstamp_work;\n\tspinlock_t systim_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct pm_qos_request pm_qos_req;\n\tlong int ptp_delta;\n\tu16 eee_advert;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct e1000_ps_page;\n\nstruct e1000_buffer {\n\tdma_addr_t dma;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int time_stamp;\n\t\t\tu16 length;\n\t\t\tu16 next_to_watch;\n\t\t\tunsigned int segs;\n\t\t\tunsigned int bytecount;\n\t\t\tu16 mapped_as_page;\n\t\t};\n\t\tstruct {\n\t\t\tstruct e1000_ps_page *ps_pages;\n\t\t\tstruct page *page;\n\t\t};\n\t};\n};\n\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss;\n\t\t\tu8 ipcso;\n\t\t\t__le16 ipcse;\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss;\n\t\t\tu8 tucso;\n\t\t\t__le16 tucse;\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 hdr_len;\n\t\t\t__le16 mss;\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\nstruct e1000_info {\n\tenum e1000_mac_type mac;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\ts32 (*get_variants)(struct e1000_adapter___2 *);\n\tconst struct e1000_mac_operations *mac_ops;\n\tconst struct e1000_phy_operations *phy_ops;\n\tconst struct e1000_nvm_operations *nvm_ops;\n};\n\nstruct e1000_opt_list {\n\tint i;\n\tchar *str;\n};\n\nstruct e1000_option {\n\tenum {\n\t\tenable_option = 0,\n\t\trange_option = 1,\n\t\tlist_option = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tconst struct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_option___2 {\n\tenum {\n\t\tenable_option___2 = 0,\n\t\trange_option___2 = 1,\n\t\tlist_option___2 = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tstruct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstruct e1000_ps_page {\n\tstruct page *page;\n\tu64 dma;\n};\n\nstruct e1000_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nstruct e1000_rx_buffer {\n\tunion {\n\t\tstruct page *page;\n\t\tu8 *data;\n\t} rxbuf;\n\tdma_addr_t dma;\n};\n\nstruct e1000_rx_desc {\n\t__le64 buffer_addr;\n\t__le16 length;\n\t__le16 csum;\n\tu8 status;\n\tu8 errors;\n\t__le16 special;\n};\n\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t__le64 buffer_addr[4];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length0;\n\t\t\t__le16 vlan;\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t__le16 length[3];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb;\n};\n\nstruct e1000_shadow_ram {\n\tu16 eeprom_word;\n\tbool modified;\n};\n\nstruct e1000_stats {\n\tchar stat_string[32];\n\tint type;\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct e1000_tx_buffer {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n\tlong unsigned int time_stamp;\n\tu16 length;\n\tu16 next_to_watch;\n\tbool mapped_as_page;\n\tshort unsigned int segs;\n\tunsigned int bytecount;\n};\n\nstruct e1000_tx_desc {\n\t__le64 buffer_addr;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length;\n\t\t\tu8 cso;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 css;\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\nstruct usb_device;\n\nstruct each_dev_arg {\n\tvoid *data;\n\tint (*fn)(struct usb_device *, void *);\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\tunion {\n\t\t__u32 padding[5];\n\t\tstruct {\n\t\t\t__u8 addr_recv;\n\t\t\t__u8 addr_dest;\n\t\t\t__u8 padding0[2];\n\t\t\t__u32 padding1[4];\n\t\t};\n\t};\n};\n\nstruct gpio_desc;\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct ktermios;\n\nstruct uart_state;\n\nstruct uart_ops;\n\nstruct serial_port_device;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int ctrl_id;\n\tunsigned int port_id;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char quirks;\n\tenum uart_iotype iotype;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tupf_t flags;\n\tupstat_t status;\n\tbool hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int frame_time;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tstruct serial_port_device *port_dev;\n\tlong unsigned int sysrq;\n\tu8 sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tunsigned char console_reinit;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct serial_rs485 rs485_supported;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct gpio_desc *rs485_rx_during_tx_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tstruct uart_port port;\n\tchar options[32];\n\tunsigned int baud;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nstruct ebitmap_node {\n\tstruct ebitmap_node *next;\n\tlong unsigned int maps[6];\n\tu32 startbit;\n};\n\nstruct td;\n\nstruct ed {\n\t__hc32 hwINFO;\n\t__hc32 hwTailP;\n\t__hc32 hwHeadP;\n\t__hc32 hwNextED;\n\tdma_addr_t dma;\n\tstruct td *dummy;\n\tstruct ed *ed_next;\n\tstruct ed *ed_prev;\n\tstruct list_head td_list;\n\tstruct list_head in_use_list;\n\tu8 state;\n\tu8 type;\n\tu8 branch;\n\tu16 interval;\n\tu16 load;\n\tu16 last_iso;\n\tu16 tick;\n\tunsigned int takeback_wdh_cnt;\n\tstruct td *pending_td;\n\tlong: 64;\n};\n\nstruct edac_scrub_ops;\n\nstruct edac_ecs_ops;\n\nstruct edac_mem_repair_ops;\n\nstruct edac_dev_data {\n\tunion {\n\t\tconst struct edac_scrub_ops *scrub_ops;\n\t\tconst struct edac_ecs_ops *ecs_ops;\n\t\tconst struct edac_mem_repair_ops *mem_repair_ops;\n\t};\n\tu8 instance;\n\tvoid *private;\n};\n\nstruct edac_dev_feat_ctx {\n\tstruct device dev;\n\tvoid *private;\n\tstruct edac_dev_data *scrub;\n\tstruct edac_dev_data ecs;\n\tstruct edac_dev_data *mem_repair;\n};\n\nstruct edac_ecs_ex_info {\n\tu16 num_media_frus;\n};\n\nstruct edac_dev_feature {\n\tenum edac_dev_feat ft_type;\n\tu8 instance;\n\tunion {\n\t\tconst struct edac_scrub_ops *scrub_ops;\n\t\tconst struct edac_ecs_ops *ecs_ops;\n\t\tconst struct edac_mem_repair_ops *mem_repair_ops;\n\t};\n\tvoid *ctx;\n\tstruct edac_ecs_ex_info ecs_info;\n};\n\nstruct edac_dev_sysfs_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct edac_dev_sysfs_block_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n};\n\nstruct edac_device_counter {\n\tu32 ue_count;\n\tu32 ce_count;\n};\n\nstruct edac_device_instance;\n\nstruct edac_device_block {\n\tstruct edac_device_instance *instance;\n\tchar name[32];\n\tstruct edac_device_counter counters;\n\tint nr_attribs;\n\tstruct edac_dev_sysfs_block_attribute *block_attributes;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_ctl_info {\n\tstruct list_head link;\n\tstruct module *owner;\n\tint dev_idx;\n\tint log_ue;\n\tint log_ce;\n\tint panic_on_ue;\n\tunsigned int poll_msec;\n\tlong unsigned int delay;\n\tstruct edac_dev_sysfs_attribute *sysfs_attributes;\n\tconst struct bus_type *edac_subsys;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_device_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tchar name[32];\n\tu32 nr_instances;\n\tstruct edac_device_instance *instances;\n\tstruct edac_device_block *blocks;\n\tstruct edac_device_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_instance {\n\tstruct edac_device_ctl_info *ctl;\n\tchar name[35];\n\tstruct edac_device_counter counters;\n\tu32 nr_blocks;\n\tstruct edac_device_block *blocks;\n\tstruct kobject kobj;\n};\n\nstruct edac_ecs_ops {\n\tint (*get_log_entry_type)(struct device *, void *, int, u32 *);\n\tint (*set_log_entry_type)(struct device *, void *, int, u32);\n\tint (*get_mode)(struct device *, void *, int, u32 *);\n\tint (*set_mode)(struct device *, void *, int, u32);\n\tint (*reset)(struct device *, void *, int, u32);\n\tint (*get_threshold)(struct device *, void *, int, u32 *);\n\tint (*set_threshold)(struct device *, void *, int, u32);\n};\n\nstruct edac_mc_layer {\n\tenum edac_mc_layer_type type;\n\tunsigned int size;\n\tbool is_virt_csrow;\n};\n\nstruct edac_mem_repair_ops {\n\tint (*get_repair_type)(struct device *, void *, const char **);\n\tint (*get_persist_mode)(struct device *, void *, bool *);\n\tint (*set_persist_mode)(struct device *, void *, bool);\n\tint (*get_repair_safe_when_in_use)(struct device *, void *, bool *);\n\tint (*get_hpa)(struct device *, void *, u64 *);\n\tint (*set_hpa)(struct device *, void *, u64);\n\tint (*get_min_hpa)(struct device *, void *, u64 *);\n\tint (*get_max_hpa)(struct device *, void *, u64 *);\n\tint (*get_dpa)(struct device *, void *, u64 *);\n\tint (*set_dpa)(struct device *, void *, u64);\n\tint (*get_min_dpa)(struct device *, void *, u64 *);\n\tint (*get_max_dpa)(struct device *, void *, u64 *);\n\tint (*get_nibble_mask)(struct device *, void *, u32 *);\n\tint (*set_nibble_mask)(struct device *, void *, u32);\n\tint (*get_bank_group)(struct device *, void *, u32 *);\n\tint (*set_bank_group)(struct device *, void *, u32);\n\tint (*get_bank)(struct device *, void *, u32 *);\n\tint (*set_bank)(struct device *, void *, u32);\n\tint (*get_rank)(struct device *, void *, u32 *);\n\tint (*set_rank)(struct device *, void *, u32);\n\tint (*get_row)(struct device *, void *, u32 *);\n\tint (*set_row)(struct device *, void *, u32);\n\tint (*get_column)(struct device *, void *, u32 *);\n\tint (*set_column)(struct device *, void *, u32);\n\tint (*get_channel)(struct device *, void *, u32 *);\n\tint (*set_channel)(struct device *, void *, u32);\n\tint (*get_sub_channel)(struct device *, void *, u32 *);\n\tint (*set_sub_channel)(struct device *, void *, u32);\n\tint (*do_repair)(struct device *, void *, u32);\n};\n\nstruct edac_pci_counter {\n\tatomic_t pe_count;\n\tatomic_t npe_count;\n};\n\nstruct edac_pci_ctl_info {\n\tstruct list_head link;\n\tint pci_idx;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_pci_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tchar name[32];\n\tstruct edac_pci_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_pci_dev_attribute {\n\tstruct attribute attr;\n\tvoid *value;\n\tssize_t (*show)(void *, char *);\n\tssize_t (*store)(void *, const char *, size_t);\n};\n\nstruct edac_pci_gen_data {\n\tint edac_idx;\n};\n\nstruct edac_raw_error_desc {\n\tchar location[256];\n\tchar label[296];\n\tlong int grain;\n\tu16 error_count;\n\tenum hw_event_mc_err_type type;\n\tint top_layer;\n\tint mid_layer;\n\tint low_layer;\n\tlong unsigned int page_frame_number;\n\tlong unsigned int offset_in_page;\n\tlong unsigned int syndrome;\n\tconst char *msg;\n\tconst char *other_detail;\n};\n\nstruct edac_scrub_ops {\n\tint (*read_addr)(struct device *, void *, u64 *);\n\tint (*read_size)(struct device *, void *, u64 *);\n\tint (*write_addr)(struct device *, void *, u64);\n\tint (*write_size)(struct device *, void *, u64);\n\tint (*get_enabled_bg)(struct device *, void *, bool *);\n\tint (*set_enabled_bg)(struct device *, void *, bool);\n\tint (*get_min_cycle)(struct device *, void *, u32 *);\n\tint (*get_max_cycle)(struct device *, void *, u32 *);\n\tint (*get_cycle_duration)(struct device *, void *, u32 *);\n\tint (*set_cycle_duration)(struct device *, void *, u32);\n};\n\nstruct eee_config {\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_enabled;\n};\n\nstruct ethtool_keee {\n\tlong unsigned int supported[2];\n\tlong unsigned int advertised[2];\n\tlong unsigned int lp_advertised[2];\n\tu32 tx_lpi_timer;\n\tbool tx_lpi_enabled;\n\tbool eee_active;\n\tbool eee_enabled;\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_keee eee;\n};\n\nstruct pci_controller;\n\nstruct eeh_pe;\n\nstruct eeh_dev {\n\tint mode;\n\tint bdfn;\n\tstruct pci_controller *controller;\n\tint pe_config_addr;\n\tu32 config_space[16];\n\tint pcix_cap;\n\tint pcie_cap;\n\tint aer_cap;\n\tint af_cap;\n\tstruct eeh_pe *pe;\n\tstruct list_head entry;\n\tstruct list_head rmv_entry;\n\tstruct pci_dn *pdn;\n\tstruct pci_dev *pdev;\n\tbool in_error;\n\tstruct pci_dev *physfn;\n\tint vf_index;\n};\n\nstruct eeh_event {\n\tstruct list_head list;\n\tstruct eeh_pe *pe;\n};\n\nstruct eeh_ops {\n\tchar *name;\n\tstruct eeh_dev * (*probe)(struct pci_dev *);\n\tint (*set_option)(struct eeh_pe *, int);\n\tint (*get_state)(struct eeh_pe *, int *);\n\tint (*reset)(struct eeh_pe *, int);\n\tint (*get_log)(struct eeh_pe *, int, char *, long unsigned int);\n\tint (*configure_bridge)(struct eeh_pe *);\n\tint (*err_inject)(struct eeh_pe *, int, int, long unsigned int, long unsigned int);\n\tint (*read_config)(struct eeh_dev *, int, int, u32 *);\n\tint (*write_config)(struct eeh_dev *, int, int, u32);\n\tint (*next_error)(struct eeh_pe **);\n\tint (*restore_config)(struct eeh_dev *);\n\tint (*notify_resume)(struct eeh_dev *);\n};\n\nstruct pci_bus;\n\nstruct eeh_pe {\n\tint type;\n\tint state;\n\tint addr;\n\tstruct pci_controller *phb;\n\tstruct pci_bus *bus;\n\tint check_count;\n\tint freeze_count;\n\ttime64_t tstamp;\n\tint false_positives;\n\tatomic_t pass_dev_cnt;\n\tstruct eeh_pe *parent;\n\tvoid *data;\n\tstruct list_head child_list;\n\tstruct list_head child;\n\tstruct list_head edevs;\n\tlong unsigned int stack_trace[64];\n\tint trace_entries;\n};\n\nstruct eeh_rmv_data {\n\tstruct list_head removed_vf_list;\n\tint removed_dev_count;\n};\n\nstruct eeh_stats {\n\tu64 no_device;\n\tu64 no_dn;\n\tu64 no_cfg_addr;\n\tu64 ignored_check;\n\tu64 total_mmio_ffs;\n\tu64 false_positives;\n\tu64 slot_resets;\n};\n\nstruct eeprom_93cx6 {\n\tvoid *data;\n\tvoid (*register_read)(struct eeprom_93cx6 *);\n\tvoid (*register_write)(struct eeprom_93cx6 *);\n\tint width;\n\tunsigned int quirks;\n\tchar drive_data;\n\tchar reg_data_in;\n\tchar reg_data_out;\n\tchar reg_data_clock;\n\tchar reg_chip_select;\n};\n\nstruct eeprom_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 length;\n\tu8 *data;\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu32 flags;\n\tu32 phy_index;\n};\n\nstruct eeprom_req_info {\n\tstruct ethnl_req_info base;\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct usb_hcd;\n\nstruct ehci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\nstruct ehci_qh;\n\nstruct ehci_itd;\n\nstruct ehci_sitd;\n\nstruct ehci_fstn;\n\nunion ehci_shadow {\n\tstruct ehci_qh *qh;\n\tstruct ehci_itd *itd;\n\tstruct ehci_sitd *sitd;\n\tstruct ehci_fstn *fstn;\n\t__le32 *hw_next;\n\tvoid *ptr;\n};\n\nstruct ehci_fstn {\n\t__le32 hw_next;\n\t__le32 hw_prev;\n\tdma_addr_t fstn_dma;\n\tunion ehci_shadow fstn_next;\n\tlong: 64;\n};\n\nstruct ehci_regs;\n\nstruct ehci_hcd {\n\tenum ehci_hrtimer_event next_hrtimer_event;\n\tunsigned int enabled_hrtimer_events;\n\tktime_t hr_timeouts[12];\n\tstruct hrtimer hrtimer;\n\tint PSS_poll_count;\n\tint ASS_poll_count;\n\tint died_poll_count;\n\tstruct ehci_caps *caps;\n\tstruct ehci_regs *regs;\n\tstruct ehci_dbg_port *debug;\n\t__u32 hcs_params;\n\tspinlock_t lock;\n\tenum ehci_rh_state rh_state;\n\tbool scanning: 1;\n\tbool need_rescan: 1;\n\tbool intr_unlinking: 1;\n\tbool iaa_in_progress: 1;\n\tbool async_unlinking: 1;\n\tbool shutdown: 1;\n\tstruct ehci_qh *qh_scan_next;\n\tstruct ehci_qh *async;\n\tstruct ehci_qh *dummy;\n\tstruct list_head async_unlink;\n\tstruct list_head async_idle;\n\tunsigned int async_unlink_cycle;\n\tunsigned int async_count;\n\t__le32 old_current;\n\t__le32 old_token;\n\tunsigned int periodic_size;\n\t__le32 *periodic;\n\tdma_addr_t periodic_dma;\n\tstruct list_head intr_qh_list;\n\tunsigned int i_thresh;\n\tunion ehci_shadow *pshadow;\n\tstruct list_head intr_unlink_wait;\n\tstruct list_head intr_unlink;\n\tunsigned int intr_unlink_wait_cycle;\n\tunsigned int intr_unlink_cycle;\n\tunsigned int now_frame;\n\tunsigned int last_iso_frame;\n\tunsigned int intr_count;\n\tunsigned int isoc_count;\n\tunsigned int periodic_count;\n\tunsigned int uframe_periodic_max;\n\tstruct list_head cached_itd_list;\n\tstruct ehci_itd *last_itd_to_free;\n\tstruct list_head cached_sitd_list;\n\tstruct ehci_sitd *last_sitd_to_free;\n\tlong unsigned int reset_done[15];\n\tlong unsigned int bus_suspended;\n\tlong unsigned int companion_ports;\n\tlong unsigned int owned_ports;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int suspended_ports;\n\tlong unsigned int resuming_ports;\n\tstruct dma_pool *qh_pool;\n\tstruct dma_pool *qtd_pool;\n\tstruct dma_pool *itd_pool;\n\tstruct dma_pool *sitd_pool;\n\tunsigned int random_frame;\n\tlong unsigned int next_statechange;\n\tktime_t last_periodic_enable;\n\tu32 command;\n\tunsigned int no_selective_suspend: 1;\n\tunsigned int has_fsl_port_bug: 1;\n\tunsigned int has_fsl_hs_errata: 1;\n\tunsigned int has_fsl_susp_errata: 1;\n\tunsigned int has_ci_pec_bug: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_capbase: 1;\n\tunsigned int has_amcc_usb23: 1;\n\tunsigned int need_io_watchdog: 1;\n\tunsigned int amd_pll_fix: 1;\n\tunsigned int use_dummy_qh: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int frame_index_bug: 1;\n\tunsigned int need_oc_pp_cycle: 1;\n\tunsigned int imx28_write_fix: 1;\n\tunsigned int spurious_oc: 1;\n\tunsigned int is_aspeed: 1;\n\tunsigned int zx_wakeup_clear_needed: 1;\n\t__le32 *ohci_hcctrl_reg;\n\tunsigned int has_hostpc: 1;\n\tunsigned int has_tdi_phy_lpm: 1;\n\tunsigned int has_ppcd: 1;\n\tu8 sbrn;\n\tu8 bandwidth[64];\n\tu8 tt_budget[64];\n\tstruct list_head tt_list;\n\tlong unsigned int priv[0];\n};\n\nstruct ehci_iso_packet {\n\tu64 bufp;\n\t__le32 transaction;\n\tu8 cross;\n\tu32 buf1;\n};\n\nstruct ehci_iso_sched {\n\tstruct list_head td_list;\n\tunsigned int span;\n\tunsigned int first_packet;\n\tstruct ehci_iso_packet packet[0];\n};\n\nstruct usb_host_endpoint;\n\nstruct ehci_per_sched {\n\tstruct usb_device *udev;\n\tstruct usb_host_endpoint *ep;\n\tstruct list_head ps_list;\n\tu16 tt_usecs;\n\tu16 cs_mask;\n\tu16 period;\n\tu16 phase;\n\tu8 bw_phase;\n\tu8 phase_uf;\n\tu8 usecs;\n\tu8 c_usecs;\n\tu8 bw_uperiod;\n\tu8 bw_period;\n};\n\nstruct ehci_qh_hw;\n\nstruct ehci_iso_stream {\n\tstruct ehci_qh_hw *hw;\n\tu8 bEndpointAddress;\n\tu8 highspeed;\n\tstruct list_head td_list;\n\tstruct list_head free_list;\n\tstruct ehci_per_sched ps;\n\tunsigned int next_uframe;\n\t__le32 splits;\n\tu16 uperiod;\n\tu16 maxp;\n\tunsigned int bandwidth;\n\t__le32 buf0;\n\t__le32 buf1;\n\t__le32 buf2;\n\t__le32 address;\n};\n\nstruct ehci_itd {\n\t__le32 hw_next;\n\t__le32 hw_transaction[8];\n\t__le32 hw_bufp[7];\n\t__le32 hw_bufp_hi[7];\n\tdma_addr_t itd_dma;\n\tunion ehci_shadow itd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head itd_list;\n\tunsigned int frame;\n\tunsigned int pg;\n\tunsigned int index[8];\n\tlong: 64;\n};\n\nstruct ehci_qtd;\n\nstruct ehci_qh {\n\tstruct ehci_qh_hw *hw;\n\tdma_addr_t qh_dma;\n\tunion ehci_shadow qh_next;\n\tstruct list_head qtd_list;\n\tstruct list_head intr_node;\n\tstruct ehci_qtd *dummy;\n\tstruct list_head unlink_node;\n\tstruct ehci_per_sched ps;\n\tunsigned int unlink_cycle;\n\tu8 qh_state;\n\tu8 xacterrs;\n\tu8 unlink_reason;\n\tu8 gap_uf;\n\tunsigned int is_out: 1;\n\tunsigned int clearing_tt: 1;\n\tunsigned int dequeue_during_giveback: 1;\n\tunsigned int should_be_inactive: 1;\n};\n\nstruct ehci_qh_hw {\n\t__le32 hw_next;\n\t__le32 hw_info1;\n\t__le32 hw_info2;\n\t__le32 hw_current;\n\t__le32 hw_qtd_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ehci_qtd {\n\t__le32 hw_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tdma_addr_t qtd_dma;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tunion {\n\t\tu32 port_status[15];\n\t\tstruct {\n\t\t\tu32 reserved3[9];\n\t\t\tu32 usbmode;\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tu32 reserved4;\n\t\t\tu32 hostpc[15];\n\t\t};\n\t\tu32 brcm_insnreg[4];\n\t};\n\tu32 reserved5[2];\n\tu32 usbmode_ex;\n};\n\nstruct ehci_sitd {\n\t__le32 hw_next;\n\t__le32 hw_fullspeed_ep;\n\t__le32 hw_uframe;\n\t__le32 hw_results;\n\t__le32 hw_buf[2];\n\t__le32 hw_backpointer;\n\t__le32 hw_buf_hi[2];\n\tdma_addr_t sitd_dma;\n\tunion ehci_shadow sitd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head sitd_list;\n\tunsigned int frame;\n\tunsigned int index;\n};\n\nstruct usb_tt;\n\nstruct ehci_tt {\n\tu16 bandwidth[8];\n\tstruct list_head tt_list;\n\tstruct list_head ps_list;\n\tstruct usb_tt *usb_tt;\n\tint tt_port;\n};\n\nstruct elevator_queue;\n\nstruct io_cq;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_queue *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct request_queue *);\n\tvoid * (*alloc_sched_data)(struct request_queue *);\n\tvoid (*free_sched_data)(void *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct request_queue *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(blk_opf_t, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, blk_insert_t);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elevator_type;\n\nstruct elevator_tags;\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tstruct elevator_tags *et;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tlong unsigned int flags;\n\tstruct hlist_head hash[64];\n};\n\nstruct elevator_resources {\n\tvoid *data;\n\tstruct elevator_tags *et;\n};\n\nstruct elevator_tags {\n\tunsigned int nr_hw_queues;\n\tunsigned int nr_requests;\n\tstruct blk_mq_tags *tags[0];\n};\n\nstruct elv_fs_entry;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tconst struct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_note {\n\tElf64_Word n_namesz;\n\tElf64_Word n_descsz;\n\tElf64_Word n_type;\n};\n\ntypedef struct elf64_note Elf64_Nhdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\nstruct elf64_rela {\n\tElf64_Addr r_offset;\n\tElf64_Xword r_info;\n\tElf64_Sxword r_addend;\n};\n\ntypedef struct elf64_rela Elf64_Rela;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\ntypedef struct elf64_shdr Elf64_Shdr;\n\nstruct elf64_sym {\n\tElf64_Word st_name;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf64_Half st_shndx;\n\tElf64_Addr st_value;\n\tElf64_Xword st_size;\n};\n\ntypedef struct elf64_sym Elf64_Sym;\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\ntypedef struct siginfo siginfo_t;\n\nstruct elf_thread_core_info;\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus_common {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n};\n\nstruct elf_prstatus {\n\tstruct elf_prstatus_common common;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elog_obj;\n\nstruct elog_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elog_obj *, struct elog_attribute *, char *);\n\tssize_t (*store)(struct elog_obj *, struct elog_attribute *, const char *, size_t);\n};\n\nstruct elog_obj {\n\tstruct kobject kobj;\n\tstruct bin_attribute raw_attr;\n\tuint64_t id;\n\tuint64_t type;\n\tsize_t size;\n\tchar *buffer;\n};\n\nstruct elv_change_ctx {\n\tconst char *name;\n\tbool no_uevent;\n\tstruct elevator_queue *old;\n\tstruct elevator_queue *new;\n\tstruct elevator_type *type;\n\tstruct elevator_resources res;\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct em_perf_table;\n\nstruct em_perf_domain {\n\tstruct em_perf_table *em_table;\n\tstruct list_head node;\n\tint id;\n\tint nr_perf_states;\n\tint min_perf_state;\n\tint max_perf_state;\n\tlong unsigned int flags;\n\tlong unsigned int cpus[0];\n};\n\nstruct em_perf_state {\n\tlong unsigned int performance;\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n\tlong unsigned int flags;\n};\n\nstruct em_perf_table {\n\tstruct callback_head rcu;\n\tstruct kref kref;\n\tstruct em_perf_state state[0];\n};\n\nstruct trace_event_file;\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nstruct xdr_buf;\n\nstruct encryptor_desc {\n\tu8 iv[16];\n\tstruct skcipher_request *req;\n\tint pos;\n\tstruct xdr_buf *outbuf;\n\tstruct page **pages;\n\tstruct scatterlist infrags[4];\n\tstruct scatterlist outfrags[4];\n\tint fragno;\n\tint fraglen;\n};\n\nstruct energy_env {\n\tlong unsigned int task_busy_time;\n\tlong unsigned int pd_busy_time;\n\tlong unsigned int cpu_cap;\n\tlong unsigned int pd_cap;\n};\n\nstruct energy_scale_attribute {\n\t__be64 id;\n\t__be64 val;\n\tu8 desc[64];\n\tu8 value_desc[64];\n};\n\nstruct entropy_timer_state {\n\tlong unsigned int entropy;\n\tstruct timer_list timer;\n\tatomic_t samples;\n\tunsigned int samples_per_bit;\n};\n\nstruct usb_endpoint_descriptor;\n\nstruct ep_device {\n\tstruct usb_endpoint_descriptor *desc;\n\tstruct usb_device *udev;\n\tstruct device dev;\n};\n\ntypedef struct poll_table_struct poll_table;\n\nstruct epitem;\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n} __attribute__((packed));\n\nstruct epoll_event {\n\t__poll_t events;\n\t__u64 data;\n};\n\nstruct eppoll_entry;\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tbool dying;\n\tstruct eppoll_entry *pwqlist;\n\tstruct eventpoll *ep;\n\tstruct hlist_node fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct epitems_head {\n\tstruct hlist_head epitems;\n\tstruct epitems_head *next;\n};\n\nstruct epoll_params {\n\t__u32 busy_poll_usecs;\n\t__u16 busy_poll_budget;\n\t__u8 prefer_busy_poll;\n\t__u8 __pad;\n};\n\nstruct epow_errorlog {\n\tunsigned char sensor_value;\n\tunsigned char event_modifier;\n\tunsigned char extended_modifier;\n\tunsigned char reserved;\n\tunsigned char platform_reason;\n};\n\nstruct eppoll_entry {\n\tstruct eppoll_entry *next;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct trace_eprobe;\n\nstruct eprobe_data {\n\tstruct trace_event_file *file;\n\tstruct trace_eprobe *ep;\n};\n\nstruct eprobe_trace_entry_head {\n\tstruct trace_entry ent;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu16 pos;\n\tu64 ts;\n};\n\nstruct err_log_info {\n\t__be32 error_type;\n\t__be32 seq_num;\n};\n\nstruct error_info {\n\tshort unsigned int code12;\n\tshort unsigned int size;\n};\n\nstruct error_info2 {\n\tunsigned char code1;\n\tunsigned char code2_min;\n\tunsigned char code2_max;\n\tconst char *str;\n\tconst char *fmt;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nstruct ethnl_request_ops;\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n};\n\nstruct ethnl_module_fw_flash_ntf_params {\n\tu32 portid;\n\tu32 seq;\n\tbool closed_sock;\n};\n\nstruct ethnl_perphy_dump_ctx {\n\tstruct ethnl_dump_ctx ethnl_ctx;\n\tunsigned int ifindex;\n\tlong unsigned int pos_phyindex;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tbool allow_nodev_do;\n\tu8 set_ntf_cmd;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, const struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n\tint (*set_validate)(struct ethnl_req_info *, struct genl_info *);\n\tint (*set)(struct ethnl_req_info *, struct genl_info *);\n};\n\nstruct ethnl_sock_priv {\n\tstruct net_device *dev;\n\tu32 portid;\n\tenum ethnl_sock_type type;\n};\n\nstruct tsinfo_req_info;\n\nstruct tsinfo_reply_data;\n\nstruct ethnl_tsinfo_dump_ctx {\n\tstruct tsinfo_req_info *req_info;\n\tstruct tsinfo_reply_data *reply_data;\n\tlong unsigned int pos_ifindex;\n\tbool netdev_dump_done;\n\tlong unsigned int pos_phyindex;\n\tenum hwtstamp_provider_qualifier pos_phcqualifier;\n};\n\nstruct ethnl_tunnel_info_dump_ctx {\n\tstruct ethnl_req_info req_info;\n\tlong unsigned int ifindex;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_c33_pse_ext_state_info {\n\tenum ethtool_c33_pse_ext_state c33_pse_ext_state;\n\tunion {\n\t\tenum ethtool_c33_pse_ext_substate_error_condition error_condition;\n\t\tenum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;\n\t\tenum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;\n\t\tenum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;\n\t\tenum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;\n\t\tenum ethtool_c33_pse_ext_substate_power_not_available power_not_available;\n\t\tenum ethtool_c33_pse_ext_substate_short_detected short_detected;\n\t\tu32 __c33_pse_ext_substate;\n\t};\n};\n\nstruct ethtool_c33_pse_pw_limit_range {\n\tu32 min;\n\tu32 max;\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_cmis_cdb {\n\tu8 cmis_rev;\n\tu8 read_write_len_ext;\n\tu16 max_completion_time;\n};\n\nstruct ethtool_cmis_cdb_request {\n\t__be16 id;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t};\n\t\tstruct {\n\t\t\t__be16 epl_len;\n\t\t\tu8 lpl_len;\n\t\t\tu8 chk_code;\n\t\t\tu8 resv1;\n\t\t\tu8 resv2;\n\t\t\tu8 payload[120];\n\t\t} body;\n\t};\n\tu8 *epl;\n};\n\nstruct ethtool_cmis_cdb_cmd_args {\n\tstruct ethtool_cmis_cdb_request req;\n\tu16 max_duration;\n\tu8 read_write_len_ext;\n\tu8 msleep_pre_rpl;\n\tu8 rpl_exp_len;\n\tu8 flags;\n\tchar *err_msg;\n};\n\nstruct ethtool_cmis_cdb_rpl_hdr {\n\tu8 rpl_len;\n\tu8 rpl_chk_code;\n};\n\nstruct ethtool_cmis_cdb_rpl {\n\tstruct ethtool_cmis_cdb_rpl_hdr hdr;\n\tu8 payload[120];\n};\n\nstruct ethtool_module_fw_flash_params {\n\t__be32 password;\n\tu8 password_valid: 1;\n};\n\nstruct ethtool_cmis_fw_update_params {\n\tstruct net_device *dev;\n\tstruct ethtool_module_fw_flash_params params;\n\tstruct ethnl_module_fw_flash_ntf_params ntf_params;\n\tconst struct firmware *fw;\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_devlink_compat {\n\tstruct devlink *devlink;\n\tunion {\n\t\tstruct ethtool_flash efl;\n\t\tstruct ethtool_drvinfo info;\n\t};\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eth_ctrl_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t};\n\t\tstruct {\n\t\t\tu64 MACControlFramesTransmitted;\n\t\t\tu64 MACControlFramesReceived;\n\t\t\tu64 UnsupportedOpcodesReceived;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_mac_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t};\n\t\tstruct {\n\t\t\tu64 FramesTransmittedOK;\n\t\t\tu64 SingleCollisionFrames;\n\t\t\tu64 MultipleCollisionFrames;\n\t\t\tu64 FramesReceivedOK;\n\t\t\tu64 FrameCheckSequenceErrors;\n\t\t\tu64 AlignmentErrors;\n\t\t\tu64 OctetsTransmittedOK;\n\t\t\tu64 FramesWithDeferredXmissions;\n\t\t\tu64 LateCollisions;\n\t\t\tu64 FramesAbortedDueToXSColls;\n\t\t\tu64 FramesLostDueToIntMACXmitError;\n\t\t\tu64 CarrierSenseErrors;\n\t\t\tu64 OctetsReceivedOK;\n\t\t\tu64 FramesLostDueToIntMACRcvError;\n\t\t\tu64 MulticastFramesXmittedOK;\n\t\t\tu64 BroadcastFramesXmittedOK;\n\t\t\tu64 FramesWithExcessiveDeferral;\n\t\t\tu64 MulticastFramesReceivedOK;\n\t\t\tu64 BroadcastFramesReceivedOK;\n\t\t\tu64 InRangeLengthErrors;\n\t\t\tu64 OutOfRangeLengthField;\n\t\t\tu64 FrameTooLongErrors;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_eth_phy_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t};\n\t\tstruct {\n\t\t\tu64 SymbolErrorDuringCarrier;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_fec_hist_value {\n\tu64 sum;\n\tu64 per_lane[8];\n};\n\nstruct ethtool_fec_hist_range;\n\nstruct ethtool_fec_hist {\n\tstruct ethtool_fec_hist_value values[17];\n\tconst struct ethtool_fec_hist_range *ranges;\n};\n\nstruct ethtool_fec_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_fec_stat {\n\tu64 total;\n\tu64 lanes[8];\n};\n\nstruct ethtool_fec_stats {\n\tstruct ethtool_fec_stat corrected_blocks;\n\tstruct ethtool_fec_stat uncorrectable_blocks;\n\tstruct ethtool_fec_stat corrected_bits;\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_forced_speed_map {\n\tu32 speed;\n\tlong unsigned int caps[2];\n\tconst u32 *cap_arr;\n\tu32 arr_size;\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_link_ext_state_info {\n\tenum ethtool_link_ext_state link_ext_state;\n\tunion {\n\t\tenum ethtool_link_ext_substate_autoneg autoneg;\n\t\tenum ethtool_link_ext_substate_link_training link_training;\n\t\tenum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;\n\t\tenum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;\n\t\tenum ethtool_link_ext_substate_cable_issue cable_issue;\n\t\tenum ethtool_link_ext_substate_module module;\n\t\tu32 __link_ext_substate;\n\t};\n};\n\nstruct ethtool_link_ext_stats {\n\tu64 link_down_events;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 rate_matching;\n\t__u32 reserved[7];\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[2];\n\t\tlong unsigned int advertising[2];\n\t\tlong unsigned int lp_advertising[2];\n\t} link_modes;\n\tu32 lanes;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[4];\n\t\t__u32 advertising[4];\n\t\t__u32 lp_advertising[4];\n\t} link_modes;\n};\n\nstruct ethtool_mm_cfg {\n\tu32 verify_time;\n\tbool verify_enabled;\n\tbool tx_enabled;\n\tbool pmac_enabled;\n\tu32 tx_min_frag_size;\n};\n\nstruct ethtool_mm_state {\n\tu32 verify_time;\n\tu32 max_verify_time;\n\tenum ethtool_mm_verify_status verify_status;\n\tbool tx_enabled;\n\tbool tx_active;\n\tbool pmac_enabled;\n\tbool verify_enabled;\n\tu32 tx_min_frag_size;\n\tu32 rx_min_frag_size;\n};\n\nstruct ethtool_mm_stats {\n\tu64 MACMergeFrameAssErrorCount;\n\tu64 MACMergeFrameSmdErrorCount;\n\tu64 MACMergeFrameAssOkCount;\n\tu64 MACMergeFragCountRx;\n\tu64 MACMergeFragCountTx;\n\tu64 MACMergeHoldCount;\n};\n\nstruct ethtool_mmsv_ops;\n\nstruct ethtool_mmsv {\n\tconst struct ethtool_mmsv_ops *ops;\n\tstruct net_device *dev;\n\tspinlock_t lock;\n\tenum ethtool_mm_verify_status status;\n\tstruct timer_list verify_timer;\n\tbool verify_enabled;\n\tint verify_retries;\n\tbool pmac_enabled;\n\tu32 verify_time;\n\tbool tx_enabled;\n};\n\nstruct ethtool_mmsv_ops {\n\tvoid (*configure_tx)(struct ethtool_mmsv *, bool);\n\tvoid (*configure_pmac)(struct ethtool_mmsv *, bool);\n\tvoid (*send_mpacket)(struct ethtool_mmsv *, enum ethtool_mpacket);\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_module_eeprom {\n\tu32 offset;\n\tu32 length;\n\tu8 page;\n\tu8 bank;\n\tu8 i2c_address;\n\tu8 *data;\n};\n\nstruct ethtool_module_fw_flash {\n\tstruct list_head list;\n\tnetdevice_tracker dev_tracker;\n\tstruct work_struct work;\n\tstruct ethtool_cmis_fw_update_params fw_update;\n};\n\nstruct ethtool_module_power_mode_params {\n\tenum ethtool_module_power_mode_policy policy;\n\tenum ethtool_module_power_mode mode;\n};\n\nstruct ethtool_netdev_state {\n\tstruct xarray rss_ctx;\n\tstruct mutex rss_lock;\n\tunsigned int wol_enabled: 1;\n\tunsigned int module_fw_flash_in_progress: 1;\n};\n\nstruct ethtool_regs;\n\nstruct ethtool_wolinfo;\n\nstruct ethtool_ringparam;\n\nstruct kernel_ethtool_ringparam;\n\nstruct ethtool_pause_stats;\n\nstruct ethtool_pauseparam;\n\nstruct ethtool_test;\n\nstruct ethtool_stats;\n\nstruct ethtool_rxnfc;\n\nstruct ethtool_rxfh_param;\n\nstruct ethtool_rxfh_fields;\n\nstruct ethtool_rxfh_context;\n\nstruct kernel_ethtool_ts_info;\n\nstruct ethtool_ts_stats;\n\nstruct ethtool_tunable;\n\nstruct ethtool_rmon_stats;\n\nstruct ethtool_rmon_hist_range;\n\nstruct ethtool_ops {\n\tu32 supported_input_xfrm: 8;\n\tu32 cap_link_lanes_supported: 1;\n\tu32 rxfh_per_ctx_fields: 1;\n\tu32 rxfh_per_ctx_key: 1;\n\tu32 cap_rss_rxnfc_adds: 1;\n\tu32 rxfh_indir_space;\n\tu16 rxfh_key_space;\n\tu16 rxfh_priv_size;\n\tu32 rxfh_max_num_contexts;\n\tu32 supported_coalesce_params;\n\tu32 supported_ring_params;\n\tu32 supported_hwtstamp_qualifiers;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_link_ext_state)(struct net_device *, struct ethtool_link_ext_state_info *);\n\tvoid (*get_link_ext_stats)(struct net_device *, struct ethtool_link_ext_stats *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *, struct kernel_ethtool_coalesce *, struct netlink_ext_ack *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *, struct kernel_ethtool_ringparam *, struct netlink_ext_ack *);\n\tvoid (*get_pause_stats)(struct net_device *, struct ethtool_pause_stats *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rx_ring_count)(struct net_device *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, struct ethtool_rxfh_param *);\n\tint (*set_rxfh)(struct net_device *, struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*get_rxfh_fields)(struct net_device *, struct ethtool_rxfh_fields *);\n\tint (*set_rxfh_fields)(struct net_device *, const struct ethtool_rxfh_fields *, struct netlink_ext_ack *);\n\tint (*create_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*modify_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, const struct ethtool_rxfh_param *, struct netlink_ext_ack *);\n\tint (*remove_rxfh_context)(struct net_device *, struct ethtool_rxfh_context *, u32, struct netlink_ext_ack *);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct kernel_ethtool_ts_info *);\n\tvoid (*get_ts_stats)(struct net_device *, struct ethtool_ts_stats *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_keee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tvoid (*get_fec_stats)(struct net_device *, struct ethtool_fec_stats *, struct ethtool_fec_hist *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*get_phy_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_phy_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tint (*set_module_eeprom_by_page)(struct net_device *, const struct ethtool_module_eeprom *, struct netlink_ext_ack *);\n\tvoid (*get_eth_phy_stats)(struct net_device *, struct ethtool_eth_phy_stats *);\n\tvoid (*get_eth_mac_stats)(struct net_device *, struct ethtool_eth_mac_stats *);\n\tvoid (*get_eth_ctrl_stats)(struct net_device *, struct ethtool_eth_ctrl_stats *);\n\tvoid (*get_rmon_stats)(struct net_device *, struct ethtool_rmon_stats *, const struct ethtool_rmon_hist_range **);\n\tint (*get_module_power_mode)(struct net_device *, struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*set_module_power_mode)(struct net_device *, const struct ethtool_module_power_mode_params *, struct netlink_ext_ack *);\n\tint (*get_mm)(struct net_device *, struct ethtool_mm_state *);\n\tint (*set_mm)(struct net_device *, struct ethtool_mm_cfg *, struct netlink_ext_ack *);\n\tvoid (*get_mm_stats)(struct net_device *, struct ethtool_mm_stats *);\n};\n\nstruct ethtool_pause_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t};\n\t\tstruct {\n\t\t\tu64 tx_pause_frames;\n\t\t\tu64 rx_pause_frames;\n\t\t} stats;\n\t};\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nstruct phy_device;\n\nstruct phy_plca_cfg;\n\nstruct phy_plca_status;\n\nstruct phy_tdr_config;\n\nstruct ethtool_phy_ops {\n\tint (*get_sset_count)(struct phy_device *);\n\tint (*get_strings)(struct phy_device *, u8 *);\n\tint (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *, struct netlink_ext_ack *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*start_cable_test)(struct phy_device *, struct netlink_ext_ack *);\n\tint (*start_cable_test_tdr)(struct phy_device *, struct netlink_ext_ack *, const struct phy_tdr_config *);\n};\n\nstruct ethtool_phy_stats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 rx_errors;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tu64 tx_errors;\n};\n\nstruct ethtool_pse_control_status {\n\tu32 pw_d_id;\n\tenum ethtool_podl_pse_admin_state podl_admin_state;\n\tenum ethtool_podl_pse_pw_d_status podl_pw_status;\n\tenum ethtool_c33_pse_admin_state c33_admin_state;\n\tenum ethtool_c33_pse_pw_d_status c33_pw_status;\n\tu32 c33_pw_class;\n\tu32 c33_actual_pw;\n\tstruct ethtool_c33_pse_ext_state_info c33_ext_state_info;\n\tu32 c33_avail_pw_limit;\n\tstruct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;\n\tu32 c33_pw_limit_nb_ranges;\n\tu32 prio_max;\n\tu32 prio;\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_rmon_hist_range {\n\tu16 low;\n\tu16 high;\n};\n\nstruct ethtool_rmon_stats {\n\tenum ethtool_mac_stats_src src;\n\tunion {\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t};\n\t\tstruct {\n\t\t\tu64 undersize_pkts;\n\t\t\tu64 oversize_pkts;\n\t\t\tu64 fragments;\n\t\t\tu64 jabbers;\n\t\t\tu64 hist[11];\n\t\t\tu64 hist_tx[11];\n\t\t} stats;\n\t};\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n\t__be16 vlan_eth_type;\n\tu16 padding;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n};\n\nstruct flow_dissector {\n\tlong long unsigned int used_keys;\n\tshort unsigned int offset[33];\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nstruct flow_rule;\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\t__u64 ring_cookie;\n\t__u32 location;\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 input_xfrm;\n\t__u8 rsvd8[2];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_rxfh_context {\n\tu32 indir_size;\n\tu32 key_size;\n\tu16 priv_size;\n\tu8 hfunc;\n\tu8 input_xfrm;\n\tu8 indir_configured: 1;\n\tu8 key_configured: 1;\n\tu32 key_off;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct ethtool_rxfh_fields {\n\tu32 data;\n\tu32 flow_type;\n\tu32 rss_context;\n};\n\nstruct ethtool_rxfh_param {\n\tu8 hfunc;\n\tu32 indir_size;\n\tu32 *indir;\n\tu32 key_size;\n\tu8 *key;\n\tu32 rss_context;\n\tu8 rss_delete;\n\tu8 input_xfrm;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_ts_stats {\n\tunion {\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pkts;\n\t\t\tu64 onestep_pkts_unconfirmed;\n\t\t\tu64 lost;\n\t\t\tu64 err;\n\t\t} tx_stats;\n\t};\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct event_trigger_data;\n\nstruct ring_buffer_event;\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*parse)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*trigger)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tbool (*count_func)(struct event_trigger_data *, struct trace_buffer *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_data *);\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nstruct event_header {\n\t__be16 data_len;\n\t__u8 notification_class: 3;\n\t__u8 reserved1: 4;\n\t__u8 nea: 1;\n\t__u8 supp_event_class;\n};\n\nstruct event_mod_load {\n\tstruct list_head list;\n\tchar *module;\n\tchar *match;\n\tchar *system;\n\tchar *event;\n};\n\nstruct srp_event_struct;\n\nunion viosrp_iu;\n\nstruct event_pool {\n\tstruct srp_event_struct *events;\n\tu32 size;\n\tint next;\n\tunion viosrp_iu *iu_storage;\n\tdma_addr_t iu_token;\n};\n\nstruct event_probe_data {\n\tstruct trace_event_file *file;\n\tlong unsigned int count;\n\tint ref;\n\tbool enable;\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tint flags;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n\tstruct llist_node llist;\n};\n\nstruct event_uniq {\n\tstruct rb_node node;\n\tconst char *name;\n\tint nl;\n\tunsigned int ct;\n\tunsigned int domain;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct eventfs_attr {\n\tint mode;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\ntypedef int (*eventfs_callback)(const char *, umode_t *, void **, const struct file_operations **);\n\ntypedef void (*eventfs_release)(const char *, void *);\n\nstruct eventfs_entry {\n\tconst char *name;\n\teventfs_callback callback;\n\teventfs_release release;\n};\n\nstruct eventfs_inode {\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head children;\n\tconst struct eventfs_entry *entries;\n\tconst char *name;\n\tstruct eventfs_attr *entry_attrs;\n\tvoid *data;\n\tstruct eventfs_attr attr;\n\tstruct kref kref;\n\tunsigned int is_freed: 1;\n\tunsigned int is_events: 1;\n\tunsigned int nr_entries: 30;\n\tunsigned int ino;\n};\n\nstruct eventfs_root_inode {\n\tstruct eventfs_inode ei;\n\tstruct dentry *events_dir;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\tspinlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tu64 gen;\n\tstruct hlist_head refs;\n\tu8 loop_check_depth;\n\trefcount_t refcount;\n\tunsigned int napi_id;\n\tu32 busy_poll_usecs;\n\tu16 busy_poll_budget;\n\tbool prefer_busy_poll;\n};\n\nstruct evm_ima_xattr_data_hdr {\n\tu8 type;\n};\n\nstruct evm_ima_xattr_data {\n\tunion {\n\t\tstruct {\n\t\t\tu8 type;\n\t\t};\n\t\tstruct evm_ima_xattr_data_hdr hdr;\n\t};\n\tu8 data[0];\n};\n\nstruct exar8250_board;\n\nstruct exar8250 {\n\tunsigned int nr;\n\tunsigned int osc_freq;\n\tstruct exar8250_board *board;\n\tstruct eeprom_93cx6 eeprom;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct uart_8250_port;\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct ktermios *, struct serial_rs485 *);\n\tconst struct serial_rs485 *rs485_supported;\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n\tvoid (*unregister_gpio)(struct uart_8250_port *);\n};\n\nstruct exception_table_entry {\n\tint insn;\n\tint fixup;\n};\n\nstruct exceptional_entry_key {\n\tstruct xarray *xa;\n\tlong unsigned int entry_start;\n};\n\nstruct execmem_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fallback_start;\n\tlong unsigned int fallback_end;\n\tpgprot_t pgprot;\n\tunsigned int alignment;\n\tenum execmem_range_flags flags;\n};\n\nstruct execmem_info {\n\tstruct execmem_range ranges[5];\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nstruct fid;\n\nstruct iomap;\n\nstruct iattr;\n\nstruct handle_to_path_ctx;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n\tint (*permission)(struct handle_to_path_ctx *, unsigned int);\n\tstruct file * (*open)(const struct path *, unsigned int);\n\tlong unsigned int flags;\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_buddy;\n\nstruct ext4_prealloc_space;\n\nstruct ext4_locality_group;\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\text4_grpblk_t ac_orig_goal_len;\n\text4_group_t ac_prefetch_grp;\n\tunsigned int ac_prefetch_ios;\n\tunsigned int ac_prefetch_nr;\n\tint ac_first_err;\n\t__u32 ac_flags;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_cX_found[5];\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct ext4_buddy *ac_e4b;\n\tstruct folio *ac_bitmap_folio;\n\tstruct folio *ac_buddy_folio;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_group_info;\n\nstruct ext4_buddy {\n\tstruct folio *bd_buddy_folio;\n\tvoid *bd_buddy;\n\tstruct folio *bd_bitmap_folio;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_hash {\n\t__le32 hash;\n\t__le32 minor_hash;\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\nstruct ext4_err_translation {\n\tint code;\n\tint errno;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct extent_status;\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_extent;\n\nstruct ext4_extent_idx;\n\nstruct ext4_extent_header;\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_fc_add_range {\n\t__le32 fc_ino;\n\t__u8 fc_ex[12];\n};\n\nstruct ext4_fc_alloc_region {\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tint ino;\n\tint len;\n};\n\nstruct ext4_fc_del_range {\n\t__le32 fc_ino;\n\t__le32 fc_lblk;\n\t__le32 fc_len;\n};\n\nstruct ext4_fc_dentry_info {\n\t__le32 fc_parent_ino;\n\t__le32 fc_ino;\n\t__u8 fc_dname[0];\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunion shortname_store inline_name;\n};\n\nstruct ext4_fc_dentry_update {\n\tint fcd_op;\n\tint fcd_parent;\n\tint fcd_ino;\n\tstruct name_snapshot fcd_name;\n\tstruct list_head fcd_list;\n\tstruct list_head fcd_dilist;\n};\n\nstruct ext4_fc_head {\n\t__le32 fc_features;\n\t__le32 fc_tid;\n};\n\nstruct ext4_fc_inode {\n\t__le32 fc_ino;\n\t__u8 fc_raw_inode[0];\n};\n\nstruct ext4_fc_replay_state {\n\tint fc_replay_num_tags;\n\tint fc_replay_expected_off;\n\tint fc_current_pass;\n\tint fc_cur_tag;\n\tint fc_crc;\n\tstruct ext4_fc_alloc_region *fc_regions;\n\tint fc_regions_size;\n\tint fc_regions_used;\n\tint fc_regions_valid;\n\tint *fc_modified_inodes;\n\tint fc_modified_inodes_used;\n\tint fc_modified_inodes_size;\n};\n\nstruct ext4_fc_stats {\n\tunsigned int fc_ineligible_reason_count[13];\n\tlong unsigned int fc_num_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_failed_commits;\n\tlong unsigned int fc_skipped_commits;\n\tlong unsigned int fc_numblks;\n\tu64 s_fc_avg_commit_time;\n};\n\nstruct ext4_fc_tail {\n\t__le32 fc_tid;\n\t__le32 fc_crc;\n};\n\nstruct ext4_fc_tl {\n\t__le16 fc_tag;\n\t__le16 fc_len;\n};\n\nstruct ext4_fc_tl_mem {\n\tu16 fc_tag;\n\tu16 fc_len;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nstruct fscrypt_dummy_policy {};\n\nstruct ext4_fs_context {\n\tchar *s_qf_names[3];\n\tstruct fscrypt_dummy_policy dummy_enc_policy;\n\tint s_jquota_fmt;\n\tshort unsigned int qname_spec;\n\tlong unsigned int vals_s_flags;\n\tlong unsigned int mask_s_flags;\n\tlong unsigned int journal_devnum;\n\tlong unsigned int s_commit_interval;\n\tlong unsigned int s_stripe;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_want_extra_isize;\n\tunsigned int s_li_wait_mult;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int journal_ioprio;\n\tunsigned int vals_s_mount_opt;\n\tunsigned int mask_s_mount_opt;\n\tunsigned int vals_s_mount_opt2;\n\tunsigned int mask_s_mount_opt2;\n\tunsigned int opt_flags;\n\tunsigned int spec;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\text4_fsblk_t s_sb_block;\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\nstruct ext4_getfsmap_info;\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\tint bb_avg_fragment_size_order;\n\text4_grpblk_t bb_largest_free_order;\n\text4_group_t bb_group;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct jbd2_inode;\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tunion {\n\t\tstruct list_head i_orphan;\n\t\tunsigned int i_orphan_idx;\n\t};\n\tstruct list_head i_fc_dilist;\n\tstruct list_head i_fc_list;\n\text4_lblk_t i_fc_lblk_start;\n\text4_lblk_t i_fc_lblk_len;\n\tspinlock_t i_raw_lock;\n\twait_queue_head_t i_fc_wait;\n\tspinlock_t i_fc_lock;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tstruct timespec64 i_crtime;\n\tatomic_t i_prealloc_active;\n\tunsigned int i_reserved_data_blocks;\n\tstruct rb_root i_prealloc_node;\n\trwlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\tu64 i_es_seq;\n\text4_group_t i_last_alloc_group;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tspinlock_t i_block_reservation_lock;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\trefcount_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n};\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tsector_t io_next_block;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct ext4_journal_trigger {\n\tstruct jbd2_buffer_trigger_type tr_triggers;\n\tstruct super_block *sb;\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tenum ext4_li_mode lr_mode;\n\text4_group_t lr_first_not_zeroed;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n\tu64 m_seq;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n};\n\nstruct ext4_new_group_data;\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t resize_bg;\n\text4_group_t count;\n};\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct ext4_orphan_block {\n\tatomic_t ob_free_entries;\n\tstruct buffer_head *ob_bh;\n};\n\nstruct ext4_orphan_block_tail {\n\t__le32 ob_magic;\n\t__le32 ob_checksum;\n};\n\nstruct ext4_orphan_info {\n\tint of_blocks;\n\t__u32 of_csum_seed;\n\tstruct ext4_orphan_block *of_binfo;\n};\n\nstruct ext4_prealloc_space {\n\tunion {\n\t\tstruct rb_node inode_node;\n\t\tstruct list_head lg_list;\n\t} pa_node;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tunion {\n\t\trwlock_t *inode_lock;\n\t\tspinlock_t *lg_lock;\n\t} pa_node_lock;\n\tstruct inode *pa_inode;\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct ext4_super_block;\n\nstruct journal_s;\n\nstruct ext4_system_blocks;\n\nstruct flex_groups;\n\nstruct shrinker;\n\nstruct mb_cache;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tlong unsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\tunsigned int s_def_mount_opt2;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct percpu_counter s_sra_exceeded_retry_limit;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct buffer_head *s_mmp_bh;\n\tstruct journal_s *s_journal;\n\tlong unsigned int s_ext4_flags;\n\tstruct mutex s_orphan_lock;\n\tstruct list_head s_orphan;\n\tstruct ext4_orphan_info s_orphan_info;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct file *s_journal_bdev_file;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *s_system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tatomic_t s_mb_free_pending;\n\tstruct list_head s_freed_data_list[2];\n\tstruct list_head s_discard_list;\n\tstruct work_struct s_discard_work;\n\tatomic_t s_retry_alloc_pending;\n\tstruct xarray *s_mb_avg_fragment_size;\n\tstruct xarray *s_mb_largest_free_orders;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_max_linear_groups;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tunsigned int s_mb_prefetch;\n\tunsigned int s_mb_prefetch_limit;\n\tunsigned int s_mb_best_avail_max_trim_order;\n\tunsigned int s_sb_update_sec;\n\tunsigned int s_sb_update_kb;\n\text4_group_t *s_mb_last_groups;\n\tunsigned int s_mb_nr_global_goals;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_cX_ex_scanned[5];\n\tatomic_t s_bal_groups_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_stream_goals;\n\tatomic_t s_bal_len_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tatomic64_t s_bal_cX_groups_considered[5];\n\tatomic64_t s_bal_cX_hits[5];\n\tatomic64_t s_bal_cX_failed[5];\n\tatomic_t s_mb_buddies_generated;\n\tatomic64_t s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tlong unsigned int s_err_report_sec;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tlong unsigned int s_last_trim_minblks;\n\tu16 s_min_folio_order;\n\tu16 s_max_folio_order;\n\t__u32 s_csum_seed;\n\tstruct shrinker *s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache *s_ea_block_cache;\n\tstruct mb_cache *s_ea_inode_cache;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_es_lock;\n\tstruct ext4_journal_trigger s_journal_triggers[1];\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tatomic_t s_warning_count;\n\tatomic_t s_msg_count;\n\tstruct fscrypt_dummy_policy s_dummy_enc_policy;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tu64 s_dax_part_off;\n\terrseq_t s_bdev_wb_err;\n\tspinlock_t s_bdev_wb_lock;\n\tspinlock_t s_error_lock;\n\tint s_add_error_count;\n\tint s_first_error_code;\n\t__u32 s_first_error_line;\n\t__u32 s_first_error_ino;\n\t__u64 s_first_error_block;\n\tconst char *s_first_error_func;\n\ttime64_t s_first_error_time;\n\tint s_last_error_code;\n\t__u32 s_last_error_line;\n\t__u32 s_last_error_ino;\n\t__u64 s_last_error_block;\n\tconst char *s_last_error_func;\n\ttime64_t s_last_error_time;\n\tstruct work_struct s_sb_upd_work;\n\tunsigned int s_awu_min;\n\tunsigned int s_awu_max;\n\tatomic_t s_fc_subtid;\n\tstruct list_head s_fc_q[2];\n\tstruct list_head s_fc_dentry_q[2];\n\tunsigned int s_fc_bytes;\n\tstruct mutex s_fc_lock;\n\tstruct buffer_head *s_fc_bh;\n\tstruct ext4_fc_stats s_fc_stats;\n\ttid_t s_fc_ineligible_tid;\n\tstruct ext4_fc_replay_state s_fc_replay_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_orphan_file_inum;\n\t__le16 s_def_resuid_hi;\n\t__le16 s_def_resgid_hi;\n\t__le32 s_reserved[93];\n\t__le32 s_checksum;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n\tu32 ino;\n};\n\nstruct ext4_tune_sb_params {\n\t__u32 set_flags;\n\t__u32 checkinterval;\n\t__u16 errors_behavior;\n\t__u16 mnt_count;\n\t__u16 max_mnt_count;\n\t__u16 raid_stride;\n\t__u64 last_check_time;\n\t__u64 reserved_blocks;\n\t__u64 blocks_count;\n\t__u32 default_mnt_opts;\n\t__u32 reserved_uid;\n\t__u32 reserved_gid;\n\t__u32 raid_stripe_width;\n\t__u16 encoding;\n\t__u16 encoding_flags;\n\t__u8 def_hash_alg;\n\t__u8 pad_1;\n\t__u16 pad_2;\n\t__u32 feature_compat;\n\t__u32 feature_incompat;\n\t__u32 feature_ro_compat;\n\t__u32 set_feature_compat_mask;\n\t__u32 set_feature_incompat_mask;\n\t__u32 set_feature_ro_compat_mask;\n\t__u32 clear_feature_compat_mask;\n\t__u32 clear_feature_incompat_mask;\n\t__u32 clear_feature_ro_compat_mask;\n\t__u8 mount_opts[64];\n\t__u8 pad[68];\n};\n\nstruct ext4_xattr_entry;\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct ext_arg {\n\tsize_t argsz;\n\tstruct timespec64 ts;\n\tconst sigset_t *sig;\n\tktime_t min_time;\n\tbool ts_set;\n\tbool iowait;\n};\n\nstruct msg_msg;\n\nstruct ext_wait_queue {\n\tstruct task_struct *task;\n\tstruct list_head list;\n\tstruct msg_msg *msg;\n\tint state;\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\text4_fsblk_t es_pblk;\n};\n\nstruct external_name {\n\tatomic_t count;\n\tstruct callback_head head;\n\tunsigned char name[0];\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct fadump_crash_info_header {\n\tu64 magic_number;\n\tu32 version;\n\tu32 crashing_cpu;\n\tu64 vmcoreinfo_raddr;\n\tu64 vmcoreinfo_size;\n\tu32 pt_regs_sz;\n\tu32 cpu_mask_sz;\n\tstruct pt_regs regs;\n\tstruct cpumask cpu_mask;\n};\n\nstruct fadump_memory_range {\n\tu64 base;\n\tu64 size;\n};\n\nstruct fadump_mrange_info {\n\tchar name[16];\n\tstruct fadump_memory_range *mem_ranges;\n\tu32 mem_ranges_sz;\n\tu32 mem_range_cnt;\n\tu32 max_mem_ranges;\n\tbool is_static;\n};\n\nstruct fw_dump;\n\nstruct fadump_ops {\n\tu64 (*fadump_init_mem_struct)(struct fw_dump *);\n\tu64 (*fadump_get_metadata_size)(void);\n\tint (*fadump_setup_metadata)(struct fw_dump *);\n\tu64 (*fadump_get_bootmem_min)(void);\n\tint (*fadump_register)(struct fw_dump *);\n\tint (*fadump_unregister)(struct fw_dump *);\n\tint (*fadump_invalidate)(struct fw_dump *);\n\tvoid (*fadump_cleanup)(struct fw_dump *);\n\tint (*fadump_process)(struct fw_dump *);\n\tvoid (*fadump_region_show)(struct fw_dump *, struct seq_file *);\n\tvoid (*fadump_trigger)(struct fadump_crash_info_header *, const char *);\n\tint (*fadump_max_boot_mem_rgns)(void);\n};\n\nstruct failed_ddw_pdn {\n\tstruct device_node *pdn;\n\tstruct list_head list;\n};\n\nstruct fanotify_response_info_header {\n\t__u8 type;\n\t__u8 pad;\n\t__u16 len;\n};\n\nstruct fanotify_response_info_audit_rule {\n\tstruct fanotify_response_info_header hdr;\n\t__u32 rule_number;\n\t__u32 subj_trust;\n\t__u32 obj_trust;\n};\n\nstruct fanout_args {\n\t__u16 id;\n\t__u16 type_flags;\n\t__u32 max_num_members;\n};\n\nstruct fast_pool {\n\tlong unsigned int pool[4];\n\tlong unsigned int last;\n\tunsigned int count;\n\tstruct timer_list mix;\n};\n\nstruct request_sock;\n\nstruct tcp_fastopen_context;\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct fat_bios_param_block {\n\tu16 fat_sector_size;\n\tu8 fat_sec_per_clus;\n\tu16 fat_reserved;\n\tu8 fat_fats;\n\tu16 fat_dir_entries;\n\tu16 fat_sectors;\n\tu16 fat_fat_length;\n\tu32 fat_total_sect;\n\tu8 fat16_state;\n\tu32 fat16_vol_id;\n\tu32 fat32_length;\n\tu32 fat32_root_cluster;\n\tu16 fat32_info_sector;\n\tu8 fat32_state;\n\tu32 fat32_vol_id;\n};\n\nstruct fat_boot_fsinfo {\n\t__le32 signature1;\n\t__le32 reserved1[120];\n\t__le32 signature2;\n\t__le32 free_clusters;\n\t__le32 next_cluster;\n\t__le32 reserved2[4];\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fat_cache {\n\tstruct list_head cache_list;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_cache_id {\n\tunsigned int id;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_entry {\n\tint entry;\n\tunion {\n\t\tu8 *ent12_p[2];\n\t\t__le16 *ent16_p;\n\t\t__le32 *ent32_p;\n\t} u;\n\tint nr_bhs;\n\tstruct buffer_head *bhs[2];\n\tstruct inode *fat_inode;\n};\n\nstruct fat_fid {\n\tu32 i_gen;\n\tu32 i_pos_low;\n\tu16 i_pos_hi;\n\tu16 parent_i_pos_hi;\n\tu32 parent_i_pos_low;\n\tu32 parent_i_gen;\n};\n\nstruct fat_floppy_defaults {\n\tunsigned int nr_sectors;\n\tunsigned int sec_per_clus;\n\tunsigned int dir_entries;\n\tunsigned int media;\n\tunsigned int fat_length;\n};\n\nstruct fat_ioctl_filldir_callback {\n\tstruct dir_context ctx;\n\tvoid *dirent;\n\tint result;\n\tconst char *longname;\n\tint long_len;\n\tconst char *shortname;\n\tint short_len;\n};\n\nstruct fat_mount_options {\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tshort unsigned int fs_fmask;\n\tshort unsigned int fs_dmask;\n\tshort unsigned int codepage;\n\tint time_offset;\n\tchar *iocharset;\n\tshort unsigned int shortname;\n\tunsigned char name_check;\n\tunsigned char errors;\n\tunsigned char nfs;\n\tshort unsigned int allow_utime;\n\tunsigned int quiet: 1;\n\tunsigned int showexec: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int dotsOK: 1;\n\tunsigned int isvfat: 1;\n\tunsigned int utf8: 1;\n\tunsigned int unicode_xlate: 1;\n\tunsigned int numtail: 1;\n\tunsigned int flush: 1;\n\tunsigned int nocase: 1;\n\tunsigned int usefree: 1;\n\tunsigned int tz_set: 1;\n\tunsigned int rodir: 1;\n\tunsigned int discard: 1;\n\tunsigned int dos1xfloppy: 1;\n\tunsigned int debug: 1;\n};\n\nstruct msdos_dir_entry;\n\nstruct fat_slot_info {\n\tloff_t i_pos;\n\tloff_t slot_off;\n\tint nr_slots;\n\tstruct msdos_dir_entry *de;\n\tstruct buffer_head *bh;\n};\n\nstruct fatent_operations {\n\tvoid (*ent_blocknr)(struct super_block *, int, int *, sector_t *);\n\tvoid (*ent_set_ptr)(struct fat_entry *, int);\n\tint (*ent_bread)(struct super_block *, struct fat_entry *, int, sector_t);\n\tint (*ent_get)(struct fat_entry *);\n\tvoid (*ent_put)(struct fat_entry *, int);\n\tint (*ent_next)(struct fat_entry *);\n};\n\nstruct fatent_ra {\n\tsector_t cur;\n\tsector_t limit;\n\tunsigned int ra_blocks;\n\tsector_t ra_advance;\n\tsector_t ra_next;\n\tsector_t ra_limit;\n};\n\nstruct fault_attr {};\n\nstruct faux_device {\n\tstruct device dev;\n};\n\nstruct faux_device_ops {\n\tint (*probe)(struct faux_device *);\n\tvoid (*remove)(struct faux_device *);\n};\n\nstruct faux_object {\n\tstruct faux_device faux_dev;\n\tconst struct faux_device_ops *faux_ops;\n\tconst struct attribute_group **groups;\n};\n\nstruct fb_address {\n\tvoid *address;\n\tint bits;\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_bitmap4x_iter {\n\tconst u8 *data;\n\tu32 fgxcolor;\n\tu32 bgcolor;\n\tint width;\n\tint i;\n\tconst u32 *expand;\n\tint bpp;\n\tbool top;\n};\n\nstruct fb_bitmap_iter {\n\tconst u8 *data;\n\tlong unsigned int colors[2];\n\tint width;\n\tint i;\n};\n\nstruct fb_blit_caps {\n\tlong unsigned int x[1];\n\tlong unsigned int y[2];\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_reverse {\n\tbool byte;\n\tbool pixel;\n};\n\nstruct fb_color_iter {\n\tconst u8 *data;\n\tconst u32 *palette;\n\tstruct fb_reverse reverse;\n\tint shift;\n\tint width;\n\tint i;\n};\n\nstruct fb_con2fbmap {\n\t__u32 console;\n\t__u32 framebuffer;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_info;\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tlong unsigned int blit_x[1];\n\tlong unsigned int blit_y[2];\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct lcd_device;\n\nstruct fb_ops;\n\nstruct fbcon_par;\n\nstruct fb_info {\n\trefcount_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tint blank;\n\tstruct lcd_device *lcd_dev;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tstruct device *dev;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tstruct fbcon_par *fbcon_par;\n\tvoid *par;\n\tbool skip_vt_switch;\n\tbool skip_panic;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n};\n\nstruct fb_pattern {\n\tlong unsigned int pixels;\n\tint left;\n\tint right;\n\tstruct fb_reverse reverse;\n};\n\nstruct fbcon_bitops {\n\tvoid (*bmove)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*clear)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*putcs)(struct vc_data *, struct fb_info *, const short unsigned int *, int, int, int, int, int);\n\tvoid (*clear_margins)(struct vc_data *, struct fb_info *, int, int);\n\tvoid (*cursor)(struct vc_data *, struct fb_info *, bool, int, int);\n\tint (*update_start)(struct fb_info *);\n\tint (*rotate_font)(struct fb_info *, struct vc_data *);\n};\n\nstruct fbcon_display {\n\tconst u_char *fontdata;\n\tint userfont;\n\tshort int yscroll;\n\tint vrows;\n\tint cursor_shape;\n\tint con_rotate;\n\tu32 xres_virtual;\n\tu32 yres_virtual;\n\tu32 height;\n\tu32 width;\n\tu32 bits_per_pixel;\n\tu32 grayscale;\n\tu32 nonstd;\n\tu32 accel_flags;\n\tu32 rotate;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tconst struct fb_videomode *mode;\n};\n\nstruct fbcon_par {\n\tstruct fb_var_screeninfo var;\n\tstruct delayed_work cursor_work;\n\tstruct fb_cursor cursor_state;\n\tstruct fbcon_display *p;\n\tstruct fb_info *info;\n\tint currcon;\n\tint cur_blink_jiffies;\n\tint cursor_flash;\n\tint cursor_reset;\n\tint blank_state;\n\tint graphics;\n\tbool initialized;\n\tint rotate;\n\tint cur_rotate;\n\tchar *cursor_data;\n\tu8 *fontbuffer;\n\tu8 *fontdata;\n\tu8 *cursor_src;\n\tu32 cursor_size;\n\tu32 fd_size;\n\tconst struct fbcon_bitops *bitops;\n};\n\nstruct fc_bsg_ctels_reply {\n\t__u32 status;\n\tstruct {\n\t\t__u8 action;\n\t\t__u8 reason_code;\n\t\t__u8 reason_explanation;\n\t\t__u8 vendor_unique;\n\t} rjt_data;\n};\n\nstruct fc_bsg_host_add_rport {\n\t__u8 reserved;\n\t__u8 port_id[3];\n};\n\nstruct fc_bsg_host_ct {\n\t__u8 reserved;\n\t__u8 port_id[3];\n\t__u32 preamble_word0;\n\t__u32 preamble_word1;\n\t__u32 preamble_word2;\n};\n\nstruct fc_bsg_host_del_rport {\n\t__u8 reserved;\n\t__u8 port_id[3];\n};\n\nstruct fc_bsg_host_els {\n\t__u8 command_code;\n\t__u8 port_id[3];\n};\n\nstruct fc_bsg_host_vendor {\n\t__u64 vendor_id;\n\t__u32 vendor_cmd[0];\n};\n\nstruct fc_bsg_host_vendor_reply {\n\tstruct {\n\t\tstruct {} __empty_vendor_rsp;\n\t\t__u32 vendor_rsp[0];\n\t};\n};\n\nstruct fc_bsg_reply {\n\t__u32 result;\n\t__u32 reply_payload_rcv_len;\n\tunion {\n\t\tstruct fc_bsg_host_vendor_reply vendor_reply;\n\t\tstruct fc_bsg_ctels_reply ctels_reply;\n\t} reply_data;\n};\n\nstruct fc_bsg_rport_els {\n\t__u8 els_code;\n};\n\nstruct fc_bsg_rport_ct {\n\t__u32 preamble_word0;\n\t__u32 preamble_word1;\n\t__u32 preamble_word2;\n};\n\nstruct fc_bsg_request {\n\t__u32 msgcode;\n\tunion {\n\t\tstruct fc_bsg_host_add_rport h_addrport;\n\t\tstruct fc_bsg_host_del_rport h_delrport;\n\t\tstruct fc_bsg_host_els h_els;\n\t\tstruct fc_bsg_host_ct h_ct;\n\t\tstruct fc_bsg_host_vendor h_vendor;\n\t\tstruct fc_bsg_rport_els r_els;\n\t\tstruct fc_bsg_rport_ct r_ct;\n\t} rqst_data;\n} __attribute__((packed));\n\nstruct fc_tlv_desc {\n\t__be32 desc_tag;\n\t__be32 desc_len;\n\t__u8 desc_value[0];\n};\n\nstruct fc_els_fpin {\n\t__u8 fpin_cmd;\n\t__u8 fpin_zero[3];\n\t__be32 desc_len;\n\tstruct fc_tlv_desc fpin_desc[0];\n};\n\nstruct fc_encryption_info {\n\tu8 status;\n};\n\nstruct fc_fn_congn_desc {\n\t__be32 desc_tag;\n\t__be32 desc_len;\n\t__be16 event_type;\n\t__be16 event_modifier;\n\t__be32 event_period;\n\t__u8 severity;\n\t__u8 resv[3];\n};\n\nstruct fc_fn_deli_desc {\n\t__be32 desc_tag;\n\t__be32 desc_len;\n\t__be64 detecting_wwpn;\n\t__be64 attached_wwpn;\n\t__be32 deli_reason_code;\n};\n\nstruct fc_fn_li_desc {\n\t__be32 desc_tag;\n\t__be32 desc_len;\n\t__be64 detecting_wwpn;\n\t__be64 attached_wwpn;\n\t__be16 event_type;\n\t__be16 event_modifier;\n\t__be32 event_threshold;\n\t__be32 event_count;\n\t__be32 pname_count;\n\t__be64 pname_list[0];\n};\n\nstruct fc_fn_peer_congn_desc {\n\t__be32 desc_tag;\n\t__be32 desc_len;\n\t__be64 detecting_wwpn;\n\t__be64 attached_wwpn;\n\t__be16 event_type;\n\t__be16 event_modifier;\n\t__be32 event_period;\n\t__be32 pname_count;\n\t__be64 pname_list[0];\n};\n\nstruct fc_fpin_stats {\n\tu64 dn;\n\tu64 dn_unknown;\n\tu64 dn_timeout;\n\tu64 dn_unable_to_route;\n\tu64 dn_device_specific;\n\tu64 li;\n\tu64 li_failure_unknown;\n\tu64 li_link_failure_count;\n\tu64 li_loss_of_sync_count;\n\tu64 li_loss_of_signals_count;\n\tu64 li_prim_seq_err_count;\n\tu64 li_invalid_tx_word_count;\n\tu64 li_invalid_crc_count;\n\tu64 li_device_specific;\n\tu64 cn;\n\tu64 cn_clear;\n\tu64 cn_lost_credit;\n\tu64 cn_credit_stall;\n\tu64 cn_oversubscription;\n\tu64 cn_device_specific;\n};\n\nstruct fc_rport;\n\nstruct scsi_target;\n\nstruct fc_host_statistics;\n\nstruct fc_vport;\n\nstruct fc_function_template {\n\tvoid (*get_rport_dev_loss_tmo)(struct fc_rport *);\n\tvoid (*set_rport_dev_loss_tmo)(struct fc_rport *, u32);\n\tvoid (*get_starget_node_name)(struct scsi_target *);\n\tvoid (*get_starget_port_name)(struct scsi_target *);\n\tvoid (*get_starget_port_id)(struct scsi_target *);\n\tvoid (*get_host_port_id)(struct Scsi_Host *);\n\tvoid (*get_host_port_type)(struct Scsi_Host *);\n\tvoid (*get_host_port_state)(struct Scsi_Host *);\n\tvoid (*get_host_active_fc4s)(struct Scsi_Host *);\n\tvoid (*get_host_speed)(struct Scsi_Host *);\n\tvoid (*get_host_fabric_name)(struct Scsi_Host *);\n\tvoid (*get_host_symbolic_name)(struct Scsi_Host *);\n\tvoid (*set_host_system_hostname)(struct Scsi_Host *);\n\tstruct fc_host_statistics * (*get_fc_host_stats)(struct Scsi_Host *);\n\tvoid (*reset_fc_host_stats)(struct Scsi_Host *);\n\tstruct fc_encryption_info * (*get_fc_rport_enc_info)(struct fc_rport *);\n\tint (*issue_fc_host_lip)(struct Scsi_Host *);\n\tvoid (*dev_loss_tmo_callbk)(struct fc_rport *);\n\tvoid (*terminate_rport_io)(struct fc_rport *);\n\tvoid (*set_vport_symbolic_name)(struct fc_vport *);\n\tint (*vport_create)(struct fc_vport *, bool);\n\tint (*vport_disable)(struct fc_vport *, bool);\n\tint (*vport_delete)(struct fc_vport *);\n\tu32 max_bsg_segments;\n\tint (*bsg_request)(struct bsg_job *);\n\tint (*bsg_timeout)(struct bsg_job *);\n\tu32 dd_fcrport_size;\n\tu32 dd_fcvport_size;\n\tu32 dd_bsg_size;\n\tlong unsigned int show_rport_maxframe_size: 1;\n\tlong unsigned int show_rport_supported_classes: 1;\n\tlong unsigned int show_rport_dev_loss_tmo: 1;\n\tlong unsigned int show_starget_node_name: 1;\n\tlong unsigned int show_starget_port_name: 1;\n\tlong unsigned int show_starget_port_id: 1;\n\tlong unsigned int show_host_node_name: 1;\n\tlong unsigned int show_host_port_name: 1;\n\tlong unsigned int show_host_permanent_port_name: 1;\n\tlong unsigned int show_host_supported_classes: 1;\n\tlong unsigned int show_host_supported_fc4s: 1;\n\tlong unsigned int show_host_supported_speeds: 1;\n\tlong unsigned int show_host_maxframe_size: 1;\n\tlong unsigned int show_host_serial_number: 1;\n\tlong unsigned int show_host_manufacturer: 1;\n\tlong unsigned int show_host_model: 1;\n\tlong unsigned int show_host_model_description: 1;\n\tlong unsigned int show_host_hardware_version: 1;\n\tlong unsigned int show_host_driver_version: 1;\n\tlong unsigned int show_host_firmware_version: 1;\n\tlong unsigned int show_host_optionrom_version: 1;\n\tlong unsigned int show_host_port_id: 1;\n\tlong unsigned int show_host_port_type: 1;\n\tlong unsigned int show_host_port_state: 1;\n\tlong unsigned int show_host_active_fc4s: 1;\n\tlong unsigned int show_host_speed: 1;\n\tlong unsigned int show_host_fabric_name: 1;\n\tlong unsigned int show_host_symbolic_name: 1;\n\tlong unsigned int show_host_system_hostname: 1;\n\tlong unsigned int disable_target_scan: 1;\n};\n\nstruct fc_host_attrs {\n\tu64 node_name;\n\tu64 port_name;\n\tu64 permanent_port_name;\n\tu32 supported_classes;\n\tu8 supported_fc4s[32];\n\tu32 supported_speeds;\n\tu32 maxframe_size;\n\tu16 max_npiv_vports;\n\tu32 max_ct_payload;\n\tu32 num_ports;\n\tu32 num_discovered_ports;\n\tu32 bootbios_state;\n\tchar serial_number[64];\n\tchar manufacturer[64];\n\tchar model[256];\n\tchar model_description[256];\n\tchar hardware_version[64];\n\tchar driver_version[64];\n\tchar firmware_version[64];\n\tchar optionrom_version[64];\n\tchar vendor_identifier[8];\n\tchar bootbios_version[256];\n\tu32 port_id;\n\tenum fc_port_type port_type;\n\tenum fc_port_state port_state;\n\tu8 active_fc4s[32];\n\tu32 speed;\n\tu64 fabric_name;\n\tchar symbolic_name[256];\n\tchar system_hostname[256];\n\tu32 dev_loss_tmo;\n\tstruct fc_fpin_stats fpin_stats;\n\tenum fc_tgtid_binding_type tgtid_bind_type;\n\tstruct list_head rports;\n\tstruct list_head rport_bindings;\n\tstruct list_head vports;\n\tu32 next_rport_number;\n\tu32 next_target_id;\n\tu32 next_vport_number;\n\tu16 npiv_vports_inuse;\n\tstruct workqueue_struct *work_q;\n\tstruct request_queue *rqst_q;\n\tu8 fdmi_version;\n};\n\nstruct fc_host_statistics {\n\tu64 seconds_since_last_reset;\n\tu64 tx_frames;\n\tu64 tx_words;\n\tu64 rx_frames;\n\tu64 rx_words;\n\tu64 lip_count;\n\tu64 nos_count;\n\tu64 error_frames;\n\tu64 dumped_frames;\n\tu64 link_failure_count;\n\tu64 loss_of_sync_count;\n\tu64 loss_of_signal_count;\n\tu64 prim_seq_protocol_err_count;\n\tu64 invalid_tx_word_count;\n\tu64 invalid_crc_count;\n\tu64 fcp_input_requests;\n\tu64 fcp_output_requests;\n\tu64 fcp_control_requests;\n\tu64 fcp_input_megabytes;\n\tu64 fcp_output_megabytes;\n\tu64 fcp_packet_alloc_failures;\n\tu64 fcp_packet_aborts;\n\tu64 fcp_frame_alloc_failures;\n\tu64 fc_no_free_exch;\n\tu64 fc_no_free_exch_xid;\n\tu64 fc_xid_not_found;\n\tu64 fc_xid_busy;\n\tu64 fc_seq_not_found;\n\tu64 fc_non_bls_resp;\n\tu64 cn_sig_warn;\n\tu64 cn_sig_alarm;\n};\n\nstruct fc_internal {\n\tstruct scsi_transport_template t;\n\tstruct fc_function_template *f;\n\tstruct device_attribute private_starget_attrs[3];\n\tstruct device_attribute *starget_attrs[4];\n\tstruct device_attribute private_host_attrs[29];\n\tstruct device_attribute *host_attrs[30];\n\tstruct transport_container rport_attr_cont;\n\tstruct device_attribute private_rport_attrs[10];\n\tstruct device_attribute *rport_attrs[11];\n\tstruct transport_container vport_attr_cont;\n\tstruct device_attribute private_vport_attrs[9];\n\tstruct device_attribute *vport_attrs[10];\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct scsi_nl_hdr {\n\t__u8 version;\n\t__u8 transport;\n\t__u16 magic;\n\t__u16 msgtype;\n\t__u16 msglen;\n};\n\nstruct fc_nl_event {\n\tstruct scsi_nl_hdr snlh;\n\t__u64 seconds;\n\t__u64 vendor_id;\n\t__u16 host_no;\n\t__u16 event_datalen;\n\t__u32 event_num;\n\t__u32 event_code;\n\tunion {\n\t\t__u32 event_data;\n\t\tstruct {\n\t\t\tstruct {} __empty_event_data_flex;\n\t\t\t__u8 event_data_flex[0];\n\t\t};\n\t};\n};\n\nstruct fc_rport {\n\tu32 maxframe_size;\n\tu32 supported_classes;\n\tu32 dev_loss_tmo;\n\tstruct fc_fpin_stats fpin_stats;\n\tu64 node_name;\n\tu64 port_name;\n\tu32 port_id;\n\tu32 roles;\n\tstruct fc_encryption_info enc_info;\n\tenum fc_port_state port_state;\n\tu32 scsi_target_id;\n\tu32 fast_io_fail_tmo;\n\tvoid *dd_data;\n\tunsigned int channel;\n\tu32 number;\n\tu8 flags;\n\tstruct list_head peers;\n\tstruct device dev;\n\tstruct delayed_work dev_loss_work;\n\tstruct work_struct scan_work;\n\tstruct delayed_work fail_io_work;\n\tstruct work_struct stgt_delete_work;\n\tstruct work_struct rport_delete_work;\n\tstruct request_queue *rqst_q;\n\tstruct workqueue_struct *devloss_work_q;\n};\n\nstruct fc_rport_identifiers {\n\tu64 node_name;\n\tu64 port_name;\n\tu32 port_id;\n\tu32 roles;\n};\n\nstruct fc_starget_attrs {\n\tu64 node_name;\n\tu64 port_name;\n\tu32 port_id;\n};\n\nstruct fc_vport {\n\tenum fc_vport_state vport_state;\n\tenum fc_vport_state vport_last_state;\n\tu64 node_name;\n\tu64 port_name;\n\tu32 roles;\n\tu32 vport_id;\n\tenum fc_port_type vport_type;\n\tchar symbolic_name[64];\n\tvoid *dd_data;\n\tstruct Scsi_Host *shost;\n\tunsigned int channel;\n\tu32 number;\n\tu8 flags;\n\tstruct list_head peers;\n\tstruct device dev;\n\tstruct work_struct vport_delete_work;\n};\n\nstruct fc_vport_identifiers {\n\tu64 node_name;\n\tu64 port_name;\n\tu32 roles;\n\tbool disable;\n\tenum fc_port_type vport_type;\n\tchar symbolic_name[64];\n};\n\nstruct fd {\n\tlong unsigned int word;\n};\n\ntypedef struct fd class_fd_pos_t;\n\ntypedef struct fd class_fd_raw_t;\n\ntypedef struct fd class_fd_t;\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct fd_dma_ops {\n\tvoid (*_disable_dma)(unsigned int);\n\tvoid (*_free_dma)(unsigned int);\n\tint (*_get_dma_residue)(unsigned int);\n\tint (*_dma_setup)(char *, long unsigned int, int, int);\n};\n\nstruct fd_prepare {\n\ts32 err;\n\ts32 __fd;\n\tstruct file *__file;\n};\n\ntypedef struct fd_prepare class_fd_prepare_t;\n\nstruct fd_range {\n\tunsigned int from;\n\tunsigned int to;\n};\n\nstruct fdt_errtabent {\n\tconst char *str;\n};\n\nstruct fdt_header {\n\tfdt32_t magic;\n\tfdt32_t totalsize;\n\tfdt32_t off_dt_struct;\n\tfdt32_t off_dt_strings;\n\tfdt32_t off_mem_rsvmap;\n\tfdt32_t version;\n\tfdt32_t last_comp_version;\n\tfdt32_t boot_cpuid_phys;\n\tfdt32_t size_dt_strings;\n\tfdt32_t size_dt_struct;\n};\n\nstruct fdt_node_header {\n\tfdt32_t tag;\n\tchar name[0];\n};\n\nstruct fdt_property {\n\tfdt32_t tag;\n\tfdt32_t len;\n\tfdt32_t nameoff;\n\tchar data[0];\n};\n\nstruct fdt_reserve_entry {\n\tfdt64_t address;\n\tfdt64_t size;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct feature_property {\n\tconst char *name;\n\tu32 min_value;\n\tlong unsigned int cpu_feature;\n\tlong unsigned int cpu_user_ftr;\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nstruct fec_stat_grp {\n\tu64 stats[9];\n\tu8 cnt;\n};\n\nstruct fec_reply_data {\n\tstruct ethnl_reply_data base;\n\tlong unsigned int fec_link_modes[2];\n\tu32 active_fec;\n\tu8 fec_auto;\n\tstruct fec_stat_grp corr;\n\tstruct fec_stat_grp uncorr;\n\tstruct fec_stat_grp corr_bits;\n\tstruct ethtool_fec_hist fec_stat_hist;\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct trace_seq;\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tbool is_signed;\n\tbool is_string;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_effect;\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[2];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_haptic_effect {\n\t__u16 hid_usage;\n\t__u16 vendor_id;\n\t__u8 vendor_waveform_page;\n\t__u16 intensity;\n\t__u16 repeat_count;\n\t__u16 retrigger_period;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t\tstruct ff_haptic_effect haptic;\n\t} u;\n};\n\nstruct fgraph_cpu_data {\n\tpid_t last_pid;\n\tint depth;\n\tint depth_irq;\n\tint ignore;\n\tlong unsigned int enter_funcs[50];\n};\n\nstruct ftrace_graph_ent {\n\tlong unsigned int func;\n\tlong int depth;\n};\n\nstruct ftrace_graph_ent_entry {\n\tstruct trace_entry ent;\n\tstruct ftrace_graph_ent graph_ent;\n\tlong unsigned int args[0];\n};\n\nstruct fgraph_ent_args {\n\tstruct ftrace_graph_ent_entry ent;\n\tlong unsigned int args[6];\n};\n\nstruct fgraph_retaddr_ent_args {\n\tstruct ftrace_graph_ent_entry ent;\n\tlong unsigned int args[6];\n};\n\nstruct ftrace_graph_ret {\n\tlong unsigned int func;\n\tint depth;\n\tunsigned int overrun;\n};\n\nstruct ftrace_graph_ret_entry {\n\tstruct trace_entry ent;\n\tstruct ftrace_graph_ret ret;\n\tlong long unsigned int calltime;\n\tlong long unsigned int rettime;\n};\n\nstruct fgraph_data {\n\tstruct fgraph_cpu_data *cpu_data;\n\tunion {\n\t\tstruct fgraph_ent_args ent;\n\t\tstruct fgraph_retaddr_ent_args rent;\n\t};\n\tstruct ftrace_graph_ret_entry ret;\n\tint failed;\n\tint cpu;\n};\n\nstruct fgraph_ops;\n\nstruct ftrace_regs;\n\ntypedef int (*trace_func_graph_ent_t)(struct ftrace_graph_ent *, struct fgraph_ops *, struct ftrace_regs *);\n\ntypedef void (*trace_func_graph_ret_t)(struct ftrace_graph_ret *, struct fgraph_ops *, struct ftrace_regs *);\n\ntypedef void (*ftrace_func_t)(long unsigned int, long unsigned int, struct ftrace_ops *, struct ftrace_regs *);\n\nstruct ftrace_hash;\n\nstruct ftrace_ops_hash {\n\tstruct ftrace_hash *notrace_hash;\n\tstruct ftrace_hash *filter_hash;\n\tstruct mutex regex_lock;\n};\n\ntypedef int (*ftrace_ops_func_t)(struct ftrace_ops *, long unsigned int, enum ftrace_ops_cmd);\n\nstruct ftrace_ops {\n\tftrace_func_t func;\n\tstruct ftrace_ops *next;\n\tlong unsigned int flags;\n\tvoid *private;\n\tftrace_func_t saved_func;\n\tstruct ftrace_ops_hash local_hash;\n\tstruct ftrace_ops_hash *func_hash;\n\tstruct ftrace_ops_hash old_hash;\n\tlong unsigned int trampoline;\n\tlong unsigned int trampoline_size;\n\tstruct list_head list;\n\tstruct list_head subop_list;\n\tftrace_ops_func_t ops_func;\n\tstruct ftrace_ops *managed;\n\tlong unsigned int direct_call;\n};\n\nstruct fgraph_ops {\n\ttrace_func_graph_ent_t entryfunc;\n\ttrace_func_graph_ret_t retfunc;\n\tstruct ftrace_ops ops;\n\tvoid *private;\n\ttrace_func_graph_ent_t saved_func;\n\tint idx;\n};\n\nstruct fgraph_times {\n\tlong long unsigned int calltime;\n\tlong long unsigned int sleeptime;\n};\n\nstruct fib6_node;\n\nstruct fib6_walker {\n\tstruct list_head lh;\n\tstruct fib6_node *root;\n\tstruct fib6_node *node;\n\tstruct fib6_info *leaf;\n\tenum fib6_walk_state state;\n\tunsigned int skip;\n\tunsigned int count;\n\tunsigned int skip_in_node;\n\tint (*func)(struct fib6_walker *);\n\tvoid *args;\n};\n\nstruct fib6_cleaner {\n\tstruct fib6_walker w;\n\tstruct net *net;\n\tint (*func)(struct fib6_info *, void *);\n\tint sernum;\n\tvoid *arg;\n\tbool skip_notify;\n};\n\nstruct nlmsghdr;\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct fib6_dump_arg {\n\tstruct net *net;\n\tstruct notifier_block *nb;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib6_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib6_info *rt;\n\tunsigned int nsiblings;\n};\n\nstruct fib6_gc_args {\n\tint timeout;\n\tint more;\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tnetdevice_tracker nhc_dev_tracker;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_info;\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_table;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct hlist_node gc_link;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 unused: 4;\n\tstruct list_head purge_link;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct fib6_nh_age_excptn_arg {\n\tstruct fib6_gc_args *gc_args;\n\tlong unsigned int now;\n};\n\nstruct fib6_nh_del_cached_rt_arg {\n\tstruct fib6_config *cfg;\n\tstruct fib6_info *f6i;\n};\n\nstruct fib6_nh_dm_arg {\n\tstruct net *net;\n\tconst struct in6_addr *saddr;\n\tint oif;\n\tint flags;\n\tstruct fib6_nh *nh;\n};\n\nstruct rt6_rtnl_dump_arg;\n\nstruct fib6_nh_exception_dump_walker {\n\tstruct rt6_rtnl_dump_arg *dump;\n\tstruct fib6_info *rt;\n\tunsigned int flags;\n\tunsigned int skip;\n\tunsigned int count;\n};\n\nstruct fib6_nh_excptn_arg {\n\tstruct rt6_info *rt;\n\tint plen;\n};\n\nstruct fib6_nh_frl_arg {\n\tu32 flags;\n\tint oif;\n\tint strict;\n\tint *mpri;\n\tbool *do_rr;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_match_arg {\n\tconst struct net_device *dev;\n\tconst struct in6_addr *gw;\n\tstruct fib6_nh *match;\n};\n\nstruct fib6_result;\n\nstruct flowi6;\n\nstruct fib6_nh_rd_arg {\n\tstruct fib6_result *res;\n\tstruct flowi6 *fl6;\n\tconst struct in6_addr *gw;\n\tstruct rt6_info **ret;\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n\tstruct hlist_head tb6_gc_hlist;\n};\n\nstruct fib_info;\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tdscp_t fa_dscp;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload;\n\tu8 trap;\n\tu8 offload_failed;\n\tstruct callback_head rcu;\n};\n\nstruct rtnexthop;\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tdscp_t fc_dscp;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tbool rtnl_held;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tdscp_t dscp;\n\tu8 type;\n\tu32 tb_id;\n};\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\trefcount_t fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tbool pfsrc_removed;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(const struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct fib_table;\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tdscp_t dscp;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct key_vector;\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tloff_t pos;\n\tt_key key;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tdscp_t dscp;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 offload_failed: 1;\n\tu8 unused: 5;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu64 ino;\n\t\t\tu32 gen;\n\t\t} __attribute__((packed)) i64;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\tstruct {\n\t\t\tstruct {} __empty_raw;\n\t\t\t__u32 raw[0];\n\t\t};\n\t};\n};\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\nstruct file__safe_trusted {\n\tstruct inode *f_inode;\n};\n\nstruct file_attr {\n\t__u64 fa_xflags;\n\t__u32 fa_extsize;\n\t__u32 fa_nextents;\n\t__u32 fa_projid;\n\t__u32 fa_cowextsize;\n};\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct file_kattr {\n\tu32 flags;\n\tu32 fsx_xflags;\n\tu32 fsx_extsize;\n\tu32 fsx_nextents;\n\tu32 fsx_projid;\n\tu32 fsx_cowextsize;\n\tbool flags_valid: 1;\n\tbool fsx_valid: 1;\n};\n\nstruct file_lock_core {\n\tstruct file_lock_core *flc_blocker;\n\tstruct list_head flc_list;\n\tstruct hlist_node flc_link;\n\tstruct list_head flc_blocked_requests;\n\tstruct list_head flc_blocked_member;\n\tfl_owner_t flc_owner;\n\tunsigned int flc_flags;\n\tunsigned char flc_type;\n\tpid_t flc_pid;\n\tint flc_link_cpu;\n\twait_queue_head_t flc_wait;\n\tstruct file *flc_file;\n};\n\nstruct lease_manager_operations;\n\nstruct file_lease {\n\tstruct file_lock_core c;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct lease_manager_operations *fl_lmops;\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct file_lock_operations;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock_core c;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t\tstruct {\n\t\t\tstruct inode *inode;\n\t\t} ceph;\n\t} fl_u;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct io_uring_cmd;\n\nstruct vm_area_desc;\n\nstruct file_operations {\n\tstruct module *owner;\n\tfop_flags_t fop_flags;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, struct io_comp_batch *, unsigned int);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct file *);\n\tint (*setlease)(struct file *, int, struct file_lease **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n\tint (*uring_cmd)(struct io_uring_cmd *, unsigned int);\n\tint (*uring_cmd_iopoll)(struct io_uring_cmd *, struct io_comp_batch *, unsigned int);\n\tint (*mmap_prepare)(struct vm_area_desc *);\n};\n\nstruct tpm_chip;\n\nstruct tpm_space;\n\nstruct file_priv {\n\tstruct tpm_chip *chip;\n\tstruct tpm_space *space;\n\tstruct mutex buffer_mutex;\n\tstruct timer_list user_read_timer;\n\tstruct work_struct timeout_work;\n\tstruct work_struct async_work;\n\twait_queue_head_t async_wait;\n\tssize_t response_length;\n\tbool response_read;\n\tbool command_enqueued;\n\tu8 data_buffer[4096];\n};\n\nstruct file_range {\n\tconst struct path *path;\n\tloff_t pos;\n\tsize_t count;\n};\n\nstruct page_counter;\n\nstruct file_region {\n\tstruct list_head link;\n\tlong int from;\n\tlong int to;\n\tstruct page_counter *reservation_counter;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct file_security_struct {\n\tu32 sid;\n\tu32 fown_sid;\n\tu32 isid;\n\tu32 pseqno;\n};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key invalidate_lock_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef struct filename *class_filename_t;\n\ntypedef class_filename_t class_filename_complete_delayed_t;\n\ntypedef class_filename_t class_filename_flags_t;\n\ntypedef class_filename_t class_filename_kernel_t;\n\ntypedef class_filename_t class_filename_maybe_null_t;\n\ntypedef class_filename_t class_filename_uflags_t;\n\nstruct filename {\n\tstruct __filename_head;\n\tconst char iname[168];\n};\n\nstruct filename_trans_datum {\n\tstruct ebitmap stypes;\n\tu32 otype;\n\tstruct filename_trans_datum *next;\n};\n\nstruct filename_trans_key {\n\tu32 ttype;\n\tu16 tclass;\n\tconst char *name;\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct filter_head {\n\tstruct list_head list;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct rcu_work rwork;\n\t};\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\nstruct regex;\n\nstruct ftrace_event_field;\n\nstruct filter_pred {\n\tstruct regex *regex;\n\tstruct cpumask *mask;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tu64 val;\n\tu64 val2;\n\tenum filter_pred_fn fn_num;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nstruct find_interface_arg {\n\tint minor;\n\tstruct device_driver *drv;\n};\n\nstruct kernel_symbol;\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst u32 *crc;\n\tconst struct kernel_symbol *sym;\n\tenum mod_license license;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\nstruct fixed_phy_status {\n\tint speed;\n\tint duplex;\n\tbool link: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n};\n\nstruct fixed_phy {\n\tstruct phy_device *phydev;\n\tstruct fixed_phy_status status;\n\tint (*link_update)(struct net_device *, struct fixed_phy_status *);\n};\n\nstruct fixup_entry {\n\tlong unsigned int mask;\n\tlong unsigned int value;\n\tlong int start_off;\n\tlong int end_off;\n\tlong int alt_start_off;\n\tlong int alt_end_off;\n};\n\nstruct flag_info {\n\tu64 mask;\n\tu64 val;\n\tconst char *set;\n\tconst char *clear;\n\tbool is_val;\n\tint shift;\n};\n\nstruct flags_map {\n\tunsigned int in_mask;\n\tunsigned int out_mask;\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct floppy_max_errors {\n\tunsigned int abort;\n\tunsigned int read_track;\n\tunsigned int reset;\n\tunsigned int recal;\n\tunsigned int reporting;\n};\n\nstruct floppy_drive_params {\n\tsigned char cmos;\n\tlong unsigned int max_dtr;\n\tlong unsigned int hlt;\n\tlong unsigned int hut;\n\tlong unsigned int srt;\n\tlong unsigned int spinup;\n\tlong unsigned int spindown;\n\tunsigned char spindown_offset;\n\tunsigned char select_delay;\n\tunsigned char rps;\n\tunsigned char tracks;\n\tlong unsigned int timeout;\n\tunsigned char interleave_sect;\n\tstruct floppy_max_errors max_errors;\n\tchar flags;\n\tchar read_track;\n\tshort int autodetect[8];\n\tint checkfreq;\n\tint native_format;\n};\n\nstruct floppy_drive_struct {\n\tlong unsigned int flags;\n\tlong unsigned int spinup_date;\n\tlong unsigned int select_date;\n\tlong unsigned int first_read_date;\n\tshort int probed_format;\n\tshort int track;\n\tshort int maxblock;\n\tshort int maxtrack;\n\tint generation;\n\tint keep_data;\n\tint fd_ref;\n\tint fd_device;\n\tlong unsigned int last_checked;\n\tchar *dmabuf;\n\tint bufblocks;\n};\n\nstruct floppy_fdc_state {\n\tint spec1;\n\tint spec2;\n\tint dtr;\n\tunsigned char version;\n\tunsigned char dor;\n\tlong unsigned int address;\n\tunsigned int rawcmd: 2;\n\tunsigned int reset: 1;\n\tunsigned int need_configure: 1;\n\tunsigned int perp_mode: 2;\n\tunsigned int has_fifo: 1;\n\tunsigned int driver_version;\n\tunsigned char track[4];\n};\n\nstruct floppy_raw_cmd {\n\tunsigned int flags;\n\tvoid *data;\n\tchar *kernel_data;\n\tstruct floppy_raw_cmd *next;\n\tlong int length;\n\tlong int phys_length;\n\tint buffer_length;\n\tunsigned char rate;\n\tunsigned char cmd_count;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char cmd[16];\n\t\t\tunsigned char reply_count;\n\t\t\tunsigned char reply[16];\n\t\t};\n\t\tunsigned char fullcmd[33];\n\t};\n\tint track;\n\tint resultcode;\n\tint reserved1;\n\tint reserved2;\n};\n\nstruct floppy_struct {\n\tunsigned int size;\n\tunsigned int sect;\n\tunsigned int head;\n\tunsigned int track;\n\tunsigned int stretch;\n\tunsigned char gap;\n\tunsigned char rate;\n\tunsigned char spec1;\n\tunsigned char fmt_gap;\n\tconst char *name;\n};\n\nstruct floppy_write_errors {\n\tunsigned int write_errors;\n\tlong unsigned int first_error_sector;\n\tint first_error_generation;\n\tlong unsigned int last_error_sector;\n\tint last_error_generation;\n\tunsigned int badness;\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct flow_action_police {\n\tu32 burst;\n\tu64 rate_bytes_ps;\n\tu64 peakrate_bytes_ps;\n\tu32 avrate;\n\tu16 overhead;\n\tu64 burst_pkt;\n\tu64 rate_pkt_ps;\n\tu32 mtu;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} exceed;\n\tstruct {\n\t\tenum flow_action_id act_id;\n\t\tu32 extval;\n\t} notexceed;\n};\n\nstruct nf_flowtable;\n\nstruct ip_tunnel_info;\n\nstruct psample_group;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tu32 hw_index;\n\tlong unsigned int cookie;\n\tu64 miss_cookie;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tunsigned char dst[6];\n\t\t\tunsigned char src[6];\n\t\t} vlan_push_eth;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu16 rx_queue;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct flow_action_police police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t\tbool orig_dir;\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\ts32 prio;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t\tstruct {\n\t\t\tu16 sid;\n\t\t} pppoe;\n\t};\n\tstruct flow_action_cookie *user_cookie;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n\tstruct Qdisc *sch;\n\tstruct list_head *cb_list_head;\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_cfm {\n\tu8 mdl_ver;\n\tu8 opcode;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\tu32 dst_opt_type;\n};\n\nstruct flow_dissector_key_hash {\n\tu32 hash;\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_ipsec {\n\t__be32 spi;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_l2tpv3 {\n\t__be32 session_id;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n\tu8 l2_miss;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_num_of_vlans {\n\tu8 num_of_vlans;\n};\n\nstruct flow_dissector_key_ports_range {\n\tunion {\n\t\tstruct flow_dissector_key_ports tp;\n\t\tstruct {\n\t\t\tstruct flow_dissector_key_ports tp_min;\n\t\t\tstruct flow_dissector_key_ports tp_max;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_pppoe {\n\t__be16 session_id;\n\t__be16 ppp_proto;\n\t__be16 type;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_indir_dev_info {\n\tvoid *data;\n\tstruct net_device *dev;\n\tstruct Qdisc *sch;\n\tenum tc_setup_type type;\n\tvoid (*cleanup)(struct flow_block_cb *);\n\tstruct list_head list;\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tstruct list_head *cb_list;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, struct Qdisc *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tlong: 0;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_arp {\n\tstruct flow_dissector_key_arp *key;\n\tstruct flow_dissector_key_arp *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ipsec {\n\tstruct flow_dissector_key_ipsec *key;\n\tstruct flow_dissector_key_ipsec *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_l2tpv3 {\n\tstruct flow_dissector_key_l2tpv3 *key;\n\tstruct flow_dissector_key_l2tpv3 *mask;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_ports_range {\n\tstruct flow_dissector_key_ports_range *key;\n\tstruct flow_dissector_key_ports_range *mask;\n};\n\nstruct flow_match_pppoe {\n\tstruct flow_dissector_key_pppoe *key;\n\tstruct flow_dissector_key_pppoe *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_stats {\n\tu64 pkts;\n\tu64 bytes;\n\tu64 drops;\n\tu64 lastused;\n\tenum flow_action_hw_stats used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\nstruct flow_offload_action {\n\tstruct netlink_ext_ack *extack;\n\tenum offload_act_command command;\n\tenum flow_action_id id;\n\tu32 index;\n\tlong unsigned int cookie;\n\tstruct flow_stats stats;\n\tstruct flow_action action;\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tstruct flow_action action;\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\tint flowic_l3mdev;\n\t__u32 flowic_mark;\n\tdscp_t flowic_dscp;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\t__u32 flowic_multipath_hash;\n\tstruct flowi_tunnel flowic_tun_key;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t} u;\n};\n\nstruct flush_backlogs {\n\tcpumask_t flush_cpus;\n\tstruct work_struct w[0];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct kyber_hctx_data;\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct fmt {\n\tconst char *str;\n\tunsigned char state;\n\tunsigned char size;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nstruct page_pool;\n\nstruct page {\n\tmemdesc_flags_t flags;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct list_head buddy_list;\n\t\t\t\tstruct list_head pcp_list;\n\t\t\t\tstruct llist_node pcp_llist;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int __folio_index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t};\n\t\tstruct {\n\t\t\tvoid *_unused_pgmap_compound_head;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tunsigned int page_type;\n\t\tatomic_t _mapcount;\n\t};\n\tatomic_t _refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct folio {\n\tunion {\n\t\tstruct {\n\t\t\tmemdesc_flags_t flags;\n\t\t\tunion {\n\t\t\t\tstruct list_head lru;\n\t\t\t\tstruct {\n\t\t\t\t\tvoid *__filler;\n\t\t\t\t\tunsigned int mlock_count;\n\t\t\t\t};\n\t\t\t\tstruct dev_pagemap *pgmap;\n\t\t\t};\n\t\t\tstruct address_space *mapping;\n\t\t\tunion {\n\t\t\t\tlong unsigned int index;\n\t\t\t\tlong unsigned int share;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tvoid *private;\n\t\t\t\tswp_entry_t swap;\n\t\t\t};\n\t\t\tatomic_t _mapcount;\n\t\t\tatomic_t _refcount;\n\t\t\tlong unsigned int memcg_data;\n\t\t};\n\t\tstruct page page;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_1;\n\t\t\tlong unsigned int _head_1;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tatomic_t _large_mapcount;\n\t\t\t\t\tatomic_t _nr_pages_mapped;\n\t\t\t\t\tatomic_t _entire_mapcount;\n\t\t\t\t\tatomic_t _pincount;\n\t\t\t\t\tmm_id_mapcount_t _mm_id_mapcount[2];\n\t\t\t\t\tunion {\n\t\t\t\t\t\tmm_id_t _mm_id[2];\n\t\t\t\t\t\tlong unsigned int _mm_ids;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tlong unsigned int _usable_1[4];\n\t\t\t};\n\t\t\tatomic_t _mapcount_1;\n\t\t\tatomic_t _refcount_1;\n\t\t\tunsigned int _nr_pages;\n\t\t};\n\t\tstruct page __page_1;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_2;\n\t\t\tlong unsigned int _head_2;\n\t\t\tstruct list_head _deferred_list;\n\t\t};\n\t\tstruct page __page_2;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _flags_3;\n\t\t\tlong unsigned int _head_3;\n\t\t\tvoid *_hugetlb_subpool;\n\t\t\tvoid *_hugetlb_cgroup;\n\t\t\tvoid *_hugetlb_cgroup_rsvd;\n\t\t\tvoid *_hugetlb_hwpoison;\n\t\t};\n\t\tstruct page __page_3;\n\t};\n};\n\nstruct folio_iter {\n\tstruct folio *folio;\n\tsize_t offset;\n\tsize_t length;\n\tstruct folio *_next;\n\tsize_t _seg_count;\n\tint _i;\n};\n\nstruct folio_or_pfn {\n\tunion {\n\t\tstruct folio *folio;\n\t\tlong unsigned int pfn;\n\t};\n\tbool is_folio;\n};\n\nstruct folio_queue {\n\tstruct folio_batch vec;\n\tu8 orders[31];\n\tstruct folio_queue *next;\n\tstruct folio_queue *prev;\n\tlong unsigned int marks;\n\tlong unsigned int marks2;\n\tunsigned int rreq_id;\n\tunsigned int debug_id;\n};\n\nstruct folio_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tvm_flags_t vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct folio_walk {\n\tstruct page *page;\n\tenum folio_walk_level level;\n\tunion {\n\t\tpte_t *ptep;\n\t\tpud_t *pudp;\n\t\tpmd_t *pmdp;\n\t};\n\tunion {\n\t\tpte_t pte;\n\t\tpud_t pud;\n\t\tpmd_t pmd;\n\t};\n\tstruct vm_area_struct *vma;\n\tspinlock_t *ptl;\n};\n\nstruct follow_pfnmap_args {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tspinlock_t *lock;\n\tpte_t *ptep;\n\tlong unsigned int pfn;\n\tlong unsigned int addr_mask;\n\tpgprot_t pgprot;\n\tbool writable;\n\tbool special;\n};\n\nstruct font_data {\n\tunsigned int extra[4];\n\tconst unsigned char data[0];\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tconst void *data;\n\tint pref;\n};\n\nstruct memory_block;\n\ntypedef int (*walk_memory_blocks_func_t)(struct memory_block *, void *);\n\nstruct for_each_memory_block_cb_data {\n\twalk_memory_blocks_func_t func;\n\tvoid *arg;\n};\n\nstruct format_descr {\n\tunsigned int device;\n\tunsigned int head;\n\tunsigned int track;\n};\n\nstruct format_state___2 {\n\tunsigned char state;\n\tunsigned char size;\n\tunsigned char flags_or_double_size;\n\tunsigned char base;\n};\n\nstruct fown_struct {\n\tstruct file *file;\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct fparm {\n\tunsigned char track;\n\tunsigned char head;\n\tunsigned char sect;\n\tunsigned char size;\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\nstruct rhashtable_compare_arg;\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhashtable rhashtable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tstruct llist_node free_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\tu8 tstamp_type;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct frag_queue {\n\tstruct inet_frag_queue q;\n\tint iif;\n\t__u16 nhoffset;\n\tu8 ecn;\n};\n\nstruct free_area {\n\tstruct list_head free_list[6];\n\tlong unsigned int nr_free;\n};\n\nstruct free_entry {\n\tu32 block;\n\tu8 sub;\n\tu8 seq;\n\tu8 has_err;\n};\n\nstruct freelist_counters {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t\tshort unsigned int stride;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n};\n\nstruct freq_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpufreq_policy *, char *);\n\tssize_t (*store)(struct cpufreq_policy *, const char *, size_t);\n};\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n\tbool exclusive: 1;\n};\n\nstruct fs_parameter;\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_error_report {\n\tint error;\n\tstruct inode *inode;\n\tstruct super_block *sb;\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t};\n};\n\nstruct fs_struct {\n\tint users;\n\tseqlock_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\nstruct fs_sysfs_path {\n\t__u8 len;\n\t__u8 name[128];\n};\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_nokey_name;\n};\n\nstruct fserror_event {\n\tstruct work_struct work;\n\tstruct super_block *sb;\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tenum fserror_type type;\n\tint error;\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_io;\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu32 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n\tconst char *driver_override;\n};\n\nstruct fsl_mc_resource_pool;\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tunsigned int virq;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\traw_spinlock_t spinlock;\n\t};\n};\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n};\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_ops;\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tenum fsnotify_group_prio priority;\n\tbool shutdown;\n\tint flags;\n\tunsigned int owner_flags;\n\tstruct mutex mark_mutex;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tstruct user_namespace *user_ns;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t};\n};\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tunsigned char type;\n\tunsigned char prio;\n\tshort unsigned int flags;\n\tunion {\n\t\tvoid *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nstruct fsnotify_inode_mark_connector {\n\tstruct fsnotify_mark_connector common;\n\tstruct list_head conns_list;\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[6];\n\tstruct fsnotify_group *current_group;\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct mnt_namespace;\n\nstruct fsnotify_mnt {\n\tconst struct mnt_namespace *ns;\n\tu64 mnt_id;\n};\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, u32, const void *, int, struct inode *, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tint (*handle_inode_event)(struct fsnotify_mark *, u32, struct inode *, struct inode *, const struct qstr *, u32);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_group *, struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct fsnotify_sb_info {\n\tstruct fsnotify_mark_connector *sb_marks;\n\tstruct list_head inode_conn_list;\n\tspinlock_t list_lock;\n\tatomic_long_t watched_objects[3];\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct fsuuid {\n\t__u32 fsu_len;\n\t__u32 fsu_flags;\n\t__u8 fsu_uuid[0];\n};\n\nstruct fsuuid2 {\n\t__u8 len;\n\t__u8 uuid[16];\n};\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nstruct trace_seq {\n\tstruct seq_buf seq;\n\tsize_t readpos;\n\tint full;\n\tchar buffer[8156];\n};\n\nstruct tracer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tchar *fmt;\n\tunsigned int fmt_size;\n\tatomic_t wait_index;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool closed;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int spare_size;\n\tunsigned int read;\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int args[0];\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tunsigned int is_signed: 1;\n\tunsigned int needs_test: 1;\n\tint len;\n};\n\nstruct ftrace_func_command {\n\tstruct list_head list;\n\tchar *name;\n\tint (*func)(struct trace_array *, struct ftrace_hash *, char *, char *, char *, int);\n};\n\nstruct ftrace_func_entry {\n\tstruct hlist_node hlist;\n\tlong unsigned int ip;\n\tlong unsigned int direct;\n};\n\nstruct ftrace_func_map {\n\tstruct ftrace_func_entry entry;\n\tvoid *data;\n};\n\nstruct ftrace_hash {\n\tlong unsigned int size_bits;\n\tstruct hlist_head *buckets;\n\tlong unsigned int count;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct ftrace_func_mapper {\n\tstruct ftrace_hash hash;\n};\n\nstruct ftrace_probe_ops;\n\nstruct ftrace_func_probe {\n\tstruct ftrace_probe_ops *probe_ops;\n\tstruct ftrace_ops ops;\n\tstruct trace_array *tr;\n\tstruct list_head list;\n\tvoid *data;\n\tint ref;\n};\n\nstruct ftrace_glob {\n\tchar *search;\n\tunsigned int len;\n\tint type;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tbool fail;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nstruct ftrace_graph_data {\n\tstruct ftrace_hash *hash;\n\tstruct ftrace_func_entry *entry;\n\tint idx;\n\tenum graph_filter_type type;\n\tstruct ftrace_hash *new_hash;\n\tconst struct seq_operations *seq_ops;\n\tstruct trace_parser parser;\n};\n\nstruct ftrace_init_func {\n\tstruct list_head list;\n\tlong unsigned int ip;\n};\n\nstruct ftrace_page;\n\nstruct ftrace_iterator {\n\tloff_t pos;\n\tloff_t func_pos;\n\tloff_t mod_pos;\n\tstruct ftrace_page *pg;\n\tstruct dyn_ftrace *func;\n\tstruct ftrace_func_probe *probe;\n\tstruct ftrace_func_entry *probe_entry;\n\tstruct trace_parser parser;\n\tstruct ftrace_hash *hash;\n\tstruct ftrace_ops *ops;\n\tstruct trace_array *tr;\n\tstruct list_head *mod_list;\n\tint pidx;\n\tint idx;\n\tunsigned int flags;\n};\n\nstruct ftrace_mod_func {\n\tstruct list_head list;\n\tchar *name;\n\tlong unsigned int ip;\n\tunsigned int size;\n};\n\nstruct ftrace_mod_load {\n\tstruct list_head list;\n\tchar *func;\n\tchar *module;\n\tint enable;\n};\n\nstruct ftrace_mod_map {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct module *mod;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tstruct list_head funcs;\n\tunsigned int num_funcs;\n};\n\nstruct ftrace_ool_stub {\n\tstruct ftrace_ops *ftrace_op;\n\tu32 insn[4];\n};\n\nstruct ftrace_page {\n\tstruct ftrace_page *next;\n\tstruct dyn_ftrace *records;\n\tint index;\n\tint order;\n};\n\nstruct ftrace_probe_ops {\n\tvoid (*func)(long unsigned int, long unsigned int, struct trace_array *, struct ftrace_probe_ops *, void *);\n\tint (*init)(struct ftrace_probe_ops *, struct trace_array *, long unsigned int, void *, void **);\n\tvoid (*free)(struct ftrace_probe_ops *, struct trace_array *, long unsigned int, void *);\n\tint (*print)(struct seq_file *, long unsigned int, struct ftrace_probe_ops *, void *);\n};\n\nstruct ftrace_rec_iter {\n\tstruct ftrace_page *pg;\n\tint index;\n};\n\nstruct ftrace_regs {};\n\nstruct ftrace_ret_stack {\n\tlong unsigned int ret;\n\tlong unsigned int func;\n\tlong unsigned int *retp;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct func_desc {\n\tlong unsigned int addr;\n\tlong unsigned int toc;\n\tlong unsigned int env;\n};\n\nstruct per_frame_masks;\n\nstruct func_instance {\n\tstruct hlist_node hl_node;\n\tstruct callchain callchain;\n\tu32 insn_cnt;\n\tbool updated;\n\tbool must_write_dropped;\n\tstruct per_frame_masks *frames[8];\n\tbool *must_write_set;\n};\n\nstruct func_repeats_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu16 count;\n\tu16 top_delta_ts;\n\tu32 bottom_delta_ts;\n};\n\nstruct function_filter_data {\n\tstruct ftrace_ops *ops;\n\tint first_filter;\n\tint first_notrace;\n};\n\nstruct futex_hash_bucket;\n\ntypedef struct futex_hash_bucket *class_hb_t;\n\nstruct futex_private_hash;\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tstruct futex_private_hash *priv;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t\tunsigned int node;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex_base pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\ntypedef struct futex_private_hash *class_private_hash_t;\n\nstruct futex_private_hash {\n\tint state;\n\tunsigned int hash_mask;\n\tstruct callback_head rcu;\n\tvoid *mm;\n\tbool custom;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct futex_hash_bucket queues[0];\n};\n\nstruct wake_q_head;\n\nstruct futex_q;\n\ntypedef void futex_wake_fn(struct wake_q_head *, struct futex_q *);\n\nstruct rt_mutex_waiter;\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tfutex_wake_fn *wake;\n\tvoid *wake_data;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n\tatomic_t requeue_state;\n\tbool drop_hb_ref;\n};\n\nstruct futex_waitv {\n\t__u64 val;\n\t__u64 uaddr;\n\t__u32 flags;\n\t__u32 __reserved;\n};\n\nstruct futex_vector {\n\tstruct futex_waitv w;\n\tstruct futex_q q;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_dump {\n\tlong unsigned int reserve_dump_area_start;\n\tlong unsigned int reserve_dump_area_size;\n\tlong unsigned int reserve_bootvar;\n\tlong unsigned int cpu_state_data_size;\n\tu64 cpu_state_dest_vaddr;\n\tu32 cpu_state_data_version;\n\tu32 cpu_state_entry_size;\n\tlong unsigned int hpte_region_size;\n\tlong unsigned int boot_memory_size;\n\tu64 boot_mem_dest_addr;\n\tu64 boot_mem_addr[128];\n\tu64 boot_mem_sz[128];\n\tu64 boot_mem_top;\n\tu64 boot_mem_regs_cnt;\n\tlong unsigned int fadumphdr_addr;\n\tu64 elfcorehdr_addr;\n\tu64 elfcorehdr_size;\n\tlong unsigned int cpu_notes_buf_vaddr;\n\tlong unsigned int cpu_notes_buf_size;\n\tlong unsigned int param_area;\n\tu64 max_copy_size;\n\tu64 kernel_metadata;\n\tint ibm_configure_kernel_dump;\n\tlong unsigned int fadump_enabled: 1;\n\tlong unsigned int fadump_supported: 1;\n\tlong unsigned int dump_active: 1;\n\tlong unsigned int dump_registered: 1;\n\tlong unsigned int nocma: 1;\n\tlong unsigned int param_area_supported: 1;\n\tstruct fadump_ops *ops;\n};\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tsize_t offset;\n\tu32 opt_flags;\n\tconst char *fw_name;\n};\n\nunion fwnet_hwaddr {\n\tu8 u[16];\n\tstruct {\n\t\t__be64 uniq_id;\n\t\tu8 max_rec;\n\t\tu8 sspd;\n\t\tu8 fifo[6];\n\t} uc;\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_link {\n\tstruct fwnode_handle *supplier;\n\tstruct list_head s_hook;\n\tstruct fwnode_handle *consumer;\n\tstruct list_head c_hook;\n\tu8 flags;\n};\n\nstruct fwnode_reference_args;\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*device_dma_supported)(const struct fwnode_handle *);\n\tenum dev_dma_attr (*device_get_dma_attr)(const struct fwnode_handle *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tbool (*property_read_bool)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tvoid * (*iomap)(struct fwnode_handle *, int);\n\tint (*irq_get)(const struct fwnode_handle *, unsigned int);\n\tint (*add_links)(struct fwnode_handle *);\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct gcry_mpi;\n\ntypedef struct gcry_mpi *MPI;\n\nstruct gcry_mpi {\n\tint alloced;\n\tint nlimbs;\n\tint nbits;\n\tint sign;\n\tunsigned int flags;\n\tmpi_limb_t *d;\n};\n\nstruct mii_phy_def;\n\nstruct mii_phy {\n\tconst struct mii_phy_def *def;\n\tu32 advertising;\n\tint mii_id;\n\tint autoneg;\n\tint speed;\n\tint duplex;\n\tint pause;\n\tstruct net_device *dev;\n\tint (*mdio_read)(struct net_device *, int, int);\n\tvoid (*mdio_write)(struct net_device *, int, int, int);\n\tvoid *platform_data;\n};\n\nstruct gem_init_block;\n\nstruct gem {\n\tvoid *regs;\n\tint rx_new;\n\tint rx_old;\n\tint tx_new;\n\tint tx_old;\n\tunsigned int has_wol: 1;\n\tunsigned int asleep_wol: 1;\n\tint cell_enabled;\n\tu32 msg_enable;\n\tu32 status;\n\tstruct napi_struct napi;\n\tint tx_fifo_sz;\n\tint rx_fifo_sz;\n\tint rx_pause_off;\n\tint rx_pause_on;\n\tint rx_buf_sz;\n\tu64 pause_entered;\n\tu16 pause_last_time_recvd;\n\tu32 mac_rx_cfg;\n\tu32 swrst_base;\n\tint want_autoneg;\n\tint last_forced_speed;\n\tenum link_state lstate;\n\tstruct timer_list link_timer;\n\tint timer_ticks;\n\tint wake_on_lan;\n\tstruct work_struct reset_task;\n\tvolatile int reset_task_pending;\n\tenum gem_phy_type phy_type;\n\tstruct mii_phy phy_mii;\n\tint mii_phy_addr;\n\tstruct gem_init_block *init_block;\n\tstruct sk_buff *rx_skbs[128];\n\tstruct sk_buff *tx_skbs[128];\n\tdma_addr_t gblock_dvma;\n\tstruct pci_dev *pdev;\n\tstruct net_device *dev;\n};\n\nstruct gem_txd {\n\t__le64 control_word;\n\t__le64 buffer;\n};\n\nstruct gem_rxd {\n\t__le64 status_word;\n\t__le64 buffer;\n};\n\nstruct gem_init_block {\n\tstruct gem_txd txd[128];\n\tstruct gem_rxd rxd[128];\n};\n\nstruct pcpu_gen_cookie;\n\nstruct gen_cookie {\n\tstruct pcpu_gen_cookie *local;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t forward_last;\n\tatomic64_t reverse_last;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct gen_pool;\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct timer_rand_state;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct xarray part_tbl;\n\tstruct block_device *part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tstruct bio_set bio_split;\n\tint flags;\n\tlong unsigned int state;\n\tstruct mutex open_mutex;\n\tunsigned int open_partitions;\n\tstruct backing_dev_info *bdi;\n\tstruct kobject queue_kobj;\n\tstruct kobject *slave_dir;\n\tstruct list_head slave_bdevs;\n\tstruct timer_rand_state *random;\n\tstruct disk_events *ev;\n\tstruct cdrom_device_info *cdi;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n\tu64 diskseq;\n\tblk_mode_t open_mode;\n\tstruct blk_independent_access_ranges *ia_ranges;\n\tstruct mutex rqos_state_mutex;\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct ocontext;\n\nstruct genfs {\n\tchar *fstype;\n\tstruct ocontext *head;\n\tstruct genfs *next;\n};\n\nstruct netlink_callback;\n\nstruct nla_policy;\n\nstruct genl_split_ops {\n\tunion {\n\t\tstruct {\n\t\t\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t\tint (*doit)(struct sk_buff *, struct genl_info *);\n\t\t\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\t\t};\n\t\tstruct {\n\t\t\tint (*start)(struct netlink_callback *);\n\t\t\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\t\t\tint (*done)(struct netlink_callback *);\n\t\t};\n\t};\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genlmsghdr;\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tconst struct genl_family *family;\n\tconst struct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tunion {\n\t\tu8 ctx[48];\n\t\tvoid *user_ptr[2];\n\t};\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct genl_dumpit_info {\n\tstruct genl_split_ops op;\n\tstruct genl_info info;\n};\n\nstruct genl_ops;\n\nstruct genl_small_ops;\n\nstruct genl_multicast_group;\n\nstruct genl_family {\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tu8 netnsok: 1;\n\tu8 parallel_ops: 1;\n\tu8 n_ops;\n\tu8 n_small_ops;\n\tu8 n_split_ops;\n\tu8 n_mcgrps;\n\tu8 resv_start_op;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_split_ops *, struct sk_buff *, struct genl_info *);\n\tint (*bind)(int);\n\tvoid (*unbind)(int);\n\tconst struct genl_ops *ops;\n\tconst struct genl_small_ops *small_ops;\n\tconst struct genl_split_ops *split_ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tstruct module *module;\n\tsize_t sock_priv_size;\n\tvoid (*sock_priv_init)(void *);\n\tvoid (*sock_priv_destroy)(void *);\n\tint id;\n\tunsigned int mcgrp_offset;\n\tstruct xarray *sock_privs;\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n\tu8 flags;\n};\n\nstruct genl_op_iter {\n\tconst struct genl_family *family;\n\tstruct genl_split_ops doit;\n\tstruct genl_split_ops dumpit;\n\tint cmd_idx;\n\tint entry_idx;\n\tu32 cmd;\n\tu8 flags;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_small_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_split_ops *ops;\n\tint hdrlen;\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[64];\n\t\tu8 data[512];\n\t};\n};\n\nstruct getbmapx {\n\t__s64 bmv_offset;\n\t__s64 bmv_block;\n\t__s64 bmv_length;\n\t__s32 bmv_count;\n\t__s32 bmv_entries;\n\t__s32 bmv_iflags;\n\t__s32 bmv_oflags;\n\t__s32 bmv_unused1;\n\t__s32 bmv_unused2;\n};\n\nstruct linux_dirent;\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct linux_dirent64;\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint error;\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct giveback_urb_bh {\n\tbool running;\n\tbool high_prio;\n\tspinlock_t lock;\n\tstruct list_head head;\n\tstruct work_struct bh;\n\tstruct usb_host_endpoint *completing_ep;\n};\n\nstruct global_pstate_info {\n\tint highest_lpstate_idx;\n\tunsigned int elapsed_time;\n\tunsigned int last_sampled_time;\n\tint last_lpstate_idx;\n\tint last_gpstate_idx;\n\tspinlock_t gpstate_lock;\n\tstruct timer_list timer;\n\tstruct cpufreq_policy *policy;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct governor_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gov_attr_set *, char *);\n\tssize_t (*store)(struct gov_attr_set *, const char *, size_t);\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n\tlocal_lock_t bh_lock;\n};\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct group_filter {\n\tunion {\n\t\tstruct {\n\t\t\t__u32 gf_interface_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_group_aux;\n\t\t\t__u32 gf_fmode_aux;\n\t\t\t__u32 gf_numsrc_aux;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u32 gf_interface;\n\t\t\tstruct __kernel_sockaddr_storage gf_group;\n\t\t\t__u32 gf_fmode;\n\t\t\t__u32 gf_numsrc;\n\t\t\tstruct __kernel_sockaddr_storage gf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct group_info {\n\trefcount_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct rpc_clnt;\n\nstruct rpc_pipe_ops;\n\nstruct gss_alloc_pdo {\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tconst struct rpc_pipe_ops *upcall_ops;\n};\n\nstruct rpcsec_gss_oid {\n\tunsigned int len;\n\tu8 data[32];\n};\n\nstruct gss_api_ops;\n\nstruct pf_desc;\n\nstruct gss_api_mech {\n\tstruct list_head gm_list;\n\tstruct module *gm_owner;\n\tstruct rpcsec_gss_oid gm_oid;\n\tchar *gm_name;\n\tconst struct gss_api_ops *gm_ops;\n\tint gm_pf_num;\n\tstruct pf_desc *gm_pfs;\n\tconst char *gm_upcall_enctypes;\n};\n\nstruct gss_ctx;\n\nstruct xdr_netobj;\n\nstruct gss_api_ops {\n\tint (*gss_import_sec_context)(const void *, size_t, struct gss_ctx *, time64_t *, gfp_t);\n\tu32 (*gss_get_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_verify_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_wrap)(struct gss_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*gss_unwrap)(struct gss_ctx *, int, int, struct xdr_buf *);\n\tvoid (*gss_delete_sec_context)(void *);\n};\n\nstruct rpc_authops;\n\nstruct rpc_cred_cache;\n\nstruct rpc_auth {\n\tunsigned int au_cslack;\n\tunsigned int au_rslack;\n\tunsigned int au_verfsize;\n\tunsigned int au_ralign;\n\tlong unsigned int au_flags;\n\tconst struct rpc_authops *au_ops;\n\trpc_authflavor_t au_flavor;\n\trefcount_t au_count;\n\tstruct rpc_cred_cache *au_credcache;\n};\n\nstruct gss_pipe;\n\nstruct gss_auth {\n\tstruct kref kref;\n\tstruct hlist_node hash;\n\tstruct rpc_auth rpc_auth;\n\tstruct gss_api_mech *mech;\n\tenum rpc_gss_svc service;\n\tstruct rpc_clnt *client;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct gss_pipe *gss_pipe[2];\n\tconst char *target_name;\n};\n\nstruct xdr_netobj {\n\tunsigned int len;\n\tu8 *data;\n};\n\nstruct gss_cl_ctx {\n\trefcount_t count;\n\tenum rpc_gss_proc gc_proc;\n\tu32 gc_seq;\n\tu32 gc_seq_xmit;\n\tspinlock_t gc_seq_lock;\n\tstruct gss_ctx *gc_gss_ctx;\n\tstruct xdr_netobj gc_wire_ctx;\n\tstruct xdr_netobj gc_acceptor;\n\tu32 gc_win;\n\tlong unsigned int gc_expiry;\n\tstruct callback_head gc_rcu;\n};\n\nstruct rpc_credops;\n\nstruct rpc_cred {\n\tstruct hlist_node cr_hash;\n\tstruct list_head cr_lru;\n\tstruct callback_head cr_rcu;\n\tstruct rpc_auth *cr_auth;\n\tconst struct rpc_credops *cr_ops;\n\tlong unsigned int cr_expire;\n\tlong unsigned int cr_flags;\n\trefcount_t cr_count;\n\tconst struct cred *cr_cred;\n};\n\nstruct gss_upcall_msg;\n\nstruct gss_cred {\n\tstruct rpc_cred gc_base;\n\tenum rpc_gss_svc gc_service;\n\tstruct gss_cl_ctx *gc_ctx;\n\tstruct gss_upcall_msg *gc_upcall;\n\tconst char *gc_principal;\n\tlong unsigned int gc_upcall_timestamp;\n};\n\nstruct gss_ctx {\n\tstruct gss_api_mech *mech_type;\n\tvoid *internal_ctx_id;\n\tunsigned int slack;\n\tunsigned int align;\n};\n\nstruct gss_domain {\n\tstruct auth_domain h;\n\tu32 pseudoflavor;\n};\n\nstruct krb5_ctx;\n\nstruct gss_krb5_enctype {\n\tconst u32 etype;\n\tconst u32 ctype;\n\tconst char *name;\n\tconst char *encrypt_name;\n\tconst char *aux_cipher;\n\tconst char *cksum_name;\n\tconst u16 signalg;\n\tconst u16 sealalg;\n\tconst u32 cksumlength;\n\tconst u32 keyed_cksum;\n\tconst u32 keybytes;\n\tconst u32 keylength;\n\tconst u32 Kc_length;\n\tconst u32 Ke_length;\n\tconst u32 Ki_length;\n\tint (*derive_key)(const struct gss_krb5_enctype *, const struct xdr_netobj *, struct xdr_netobj *, const struct xdr_netobj *, gfp_t);\n\tu32 (*encrypt)(struct krb5_ctx *, u32, struct xdr_buf *, struct page **);\n\tu32 (*decrypt)(struct krb5_ctx *, u32, u32, struct xdr_buf *, u32 *, u32 *);\n\tu32 (*get_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*verify_mic)(struct krb5_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*wrap)(struct krb5_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*unwrap)(struct krb5_ctx *, int, int, struct xdr_buf *, unsigned int *, unsigned int *);\n};\n\nstruct rpc_pipe_dir_object_ops;\n\nstruct rpc_pipe_dir_object {\n\tstruct list_head pdo_head;\n\tconst struct rpc_pipe_dir_object_ops *pdo_ops;\n\tvoid *pdo_data;\n};\n\nstruct rpc_pipe;\n\nstruct gss_pipe {\n\tstruct rpc_pipe_dir_object pdo;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tstruct kref kref;\n};\n\nstruct rpc_gss_wire_cred {\n\tu32 gc_v;\n\tu32 gc_proc;\n\tu32 gc_seq;\n\tu32 gc_svc;\n\tstruct xdr_netobj gc_ctx;\n};\n\nstruct rsc;\n\nstruct gss_svc_data {\n\tstruct rpc_gss_wire_cred clcred;\n\tu32 gsd_databody_offset;\n\tstruct rsc *rsci;\n\t__be32 gsd_seq_num;\n\tu8 gsd_scratch[40];\n};\n\nstruct gss_svc_seq_data {\n\tu32 sd_max;\n\tlong unsigned int sd_win[2];\n\tspinlock_t sd_lock;\n};\n\nstruct rpc_timer {\n\tstruct list_head list;\n\tlong unsigned int expires;\n\tstruct delayed_work dwork;\n};\n\nstruct rpc_wait_queue {\n\tspinlock_t lock;\n\tstruct list_head tasks[4];\n\tunsigned char maxpriority;\n\tunsigned char priority;\n\tunsigned char nr;\n\tunsigned int qlen;\n\tstruct rpc_timer timer_list;\n\tconst char *name;\n};\n\nstruct gss_upcall_msg {\n\trefcount_t count;\n\tkuid_t uid;\n\tconst char *service_name;\n\tstruct rpc_pipe_msg msg;\n\tstruct list_head list;\n\tstruct gss_auth *auth;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_wait_queue rpc_waitqueue;\n\twait_queue_head_t waitqueue;\n\tstruct gss_cl_ctx *ctx;\n\tchar databuf[256];\n};\n\nstruct gssp_in_token {\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n};\n\nstruct svc_cred {\n\tkuid_t cr_uid;\n\tkgid_t cr_gid;\n\tstruct group_info *cr_group_info;\n\tu32 cr_flavor;\n\tchar *cr_raw_principal;\n\tchar *cr_principal;\n\tchar *cr_targ_princ;\n\tstruct gss_api_mech *cr_gss_mech;\n};\n\nstruct gssp_upcall_data {\n\tstruct xdr_netobj in_handle;\n\tstruct gssp_in_token in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tstruct rpcsec_gss_oid mech_oid;\n\tstruct svc_cred creds;\n\tint found_creds;\n\tint major_status;\n\tint minor_status;\n};\n\ntypedef struct xdr_netobj utf8string;\n\ntypedef struct xdr_netobj gssx_buffer;\n\nstruct gssx_option;\n\nstruct gssx_option_array {\n\tu32 count;\n\tstruct gssx_option *data;\n};\n\nstruct gssx_call_ctx {\n\tutf8string locale;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx;\n\nstruct gssx_cred;\n\nstruct gssx_cb;\n\nstruct gssx_arg_accept_sec_context {\n\tstruct gssx_call_ctx call_ctx;\n\tstruct gssx_ctx *context_handle;\n\tstruct gssx_cred *cred_handle;\n\tstruct gssp_in_token input_token;\n\tstruct gssx_cb *input_cb;\n\tu32 ret_deleg_cred;\n\tstruct gssx_option_array options;\n\tstruct page **pages;\n\tunsigned int npages;\n};\n\nstruct gssx_cb {\n\tu64 initiator_addrtype;\n\tgssx_buffer initiator_address;\n\tu64 acceptor_addrtype;\n\tgssx_buffer acceptor_address;\n\tgssx_buffer application_data;\n};\n\nstruct gssx_name {\n\tgssx_buffer display_name;\n};\n\ntypedef struct gssx_name gssx_name;\n\nstruct gssx_cred_element;\n\nstruct gssx_cred_element_array {\n\tu32 count;\n\tstruct gssx_cred_element *data;\n};\n\nstruct gssx_cred {\n\tgssx_name desired_name;\n\tstruct gssx_cred_element_array elements;\n\tgssx_buffer cred_handle_reference;\n\tu32 needs_release;\n};\n\ntypedef struct xdr_netobj gssx_OID;\n\nstruct gssx_cred_element {\n\tgssx_name MN;\n\tgssx_OID mech;\n\tu32 cred_usage;\n\tu64 initiator_time_rec;\n\tu64 acceptor_time_rec;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_ctx {\n\tgssx_buffer exported_context_token;\n\tgssx_buffer state;\n\tu32 need_release;\n\tgssx_OID mech;\n\tgssx_name src_name;\n\tgssx_name targ_name;\n\tu64 lifetime;\n\tu64 ctx_flags;\n\tu32 locally_initiated;\n\tu32 open;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_name_attr {\n\tgssx_buffer attr;\n\tgssx_buffer value;\n\tstruct gssx_option_array extensions;\n};\n\nstruct gssx_name_attr_array {\n\tu32 count;\n\tstruct gssx_name_attr *data;\n};\n\nstruct gssx_option {\n\tgssx_buffer option;\n\tgssx_buffer value;\n};\n\nstruct gssx_status {\n\tu64 major_status;\n\tgssx_OID mech;\n\tu64 minor_status;\n\tutf8string major_status_string;\n\tutf8string minor_status_string;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_res_accept_sec_context {\n\tstruct gssx_status status;\n\tstruct gssx_ctx *context_handle;\n\tgssx_buffer *output_token;\n\tstruct gssx_option_array options;\n};\n\nstruct gxt4500_par {\n\tvoid *regs;\n\tint wc_cookie;\n\tint pixfmt;\n\tint refclk_ps;\n\tint pll_m;\n\tint pll_n;\n\tint pll_pd1;\n\tint pll_pd2;\n\tu32 pseudo_palette[16];\n};\n\nstruct h_cpu_char_result {\n\tu64 character;\n\tu64 behaviour;\n};\n\nstruct h_energy_scale_info_hdr {\n\t__be64 num_attrs;\n\t__be64 array_offset;\n\tu8 data_header_version;\n} __attribute__((packed));\n\nunion handle_parts {\n\tdepot_stack_handle_t handle;\n\tstruct {\n\t\tu32 pool_index_plus_1: 13;\n\t\tu32 offset: 14;\n\t\tu32 extra: 5;\n\t};\n};\n\nstruct handle_to_path_ctx {\n\tstruct path root;\n\tenum handle_to_path_flags flags;\n\tunsigned int fh_flags;\n};\n\nstruct handshake_net {\n\tspinlock_t hn_lock;\n\tint hn_pending;\n\tint hn_pending_max;\n\tstruct list_head hn_requests;\n\tlong unsigned int hn_flags;\n};\n\nstruct handshake_req;\n\nstruct handshake_proto {\n\tint hp_handler_class;\n\tsize_t hp_privsize;\n\tlong unsigned int hp_flags;\n\tint (*hp_accept)(struct handshake_req *, struct genl_info *, int);\n\tvoid (*hp_done)(struct handshake_req *, unsigned int, struct genl_info *);\n\tvoid (*hp_destroy)(struct handshake_req *);\n};\n\nstruct handshake_req {\n\tstruct list_head hr_list;\n\tstruct rhash_head hr_rhash;\n\tlong unsigned int hr_flags;\n\tconst struct handshake_proto *hr_proto;\n\tstruct sock *hr_sk;\n\tvoid (*hr_odestruct)(struct sock *);\n\tchar hr_priv[0];\n};\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct hash_cell {\n\tstruct rb_node name_node;\n\tstruct rb_node uuid_node;\n\tbool name_set;\n\tbool uuid_set;\n\tchar *name;\n\tchar *uuid;\n\tstruct mapped_device *md;\n\tstruct dm_table *new_map;\n};\n\nstruct slice_mask {\n\tu64 low_slices;\n\tlong unsigned int high_slices[64];\n};\n\nstruct hash_mm_context {\n\tu16 user_psize;\n\tunsigned char low_slices_psize[8];\n\tunsigned char high_slices_psize[2048];\n\tlong unsigned int slb_addr_limit;\n\tstruct slice_mask mask_64k;\n\tstruct slice_mask mask_4k;\n\tstruct slice_mask mask_16m;\n\tstruct slice_mask mask_16g;\n};\n\nstruct hash_prefix {\n\tconst char *name;\n\tconst u8 *data;\n\tsize_t size;\n};\n\nstruct hash_pte {\n\t__be64 v;\n\t__be64 r;\n};\n\nstruct hashtab_key_params {\n\tu32 (*hash)(const void *);\n\tint (*cmp)(const void *, const void *);\n};\n\nstruct hashtab_node {\n\tvoid *key;\n\tvoid *datum;\n\tstruct hashtab_node *next;\n};\n\nstruct hc_driver {\n\tconst char *description;\n\tconst char *product_desc;\n\tsize_t hcd_priv_size;\n\tirqreturn_t (*irq)(struct usb_hcd *);\n\tint flags;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*pci_suspend)(struct usb_hcd *, bool);\n\tint (*pci_resume)(struct usb_hcd *, pm_message_t);\n\tint (*pci_poweroff_late)(struct usb_hcd *, bool);\n\tvoid (*stop)(struct usb_hcd *);\n\tvoid (*shutdown)(struct usb_hcd *);\n\tint (*get_frame_number)(struct usb_hcd *);\n\tint (*urb_enqueue)(struct usb_hcd *, struct urb *, gfp_t);\n\tint (*urb_dequeue)(struct usb_hcd *, struct urb *, int);\n\tint (*map_urb_for_dma)(struct usb_hcd *, struct urb *, gfp_t);\n\tvoid (*unmap_urb_for_dma)(struct usb_hcd *, struct urb *);\n\tvoid (*endpoint_disable)(struct usb_hcd *, struct usb_host_endpoint *);\n\tvoid (*endpoint_reset)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*hub_status_data)(struct usb_hcd *, char *);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n\tint (*bus_suspend)(struct usb_hcd *);\n\tint (*bus_resume)(struct usb_hcd *);\n\tint (*start_port_reset)(struct usb_hcd *, unsigned int);\n\tlong unsigned int (*get_resuming_ports)(struct usb_hcd *);\n\tvoid (*relinquish_port)(struct usb_hcd *, int);\n\tint (*port_handed_over)(struct usb_hcd *, int);\n\tvoid (*clear_tt_buffer_complete)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*alloc_dev)(struct usb_hcd *, struct usb_device *);\n\tvoid (*free_dev)(struct usb_hcd *, struct usb_device *);\n\tint (*alloc_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, unsigned int, gfp_t);\n\tint (*free_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, gfp_t);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*address_device)(struct usb_hcd *, struct usb_device *, unsigned int);\n\tint (*enable_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*reset_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_device)(struct usb_hcd *, struct usb_device *);\n\tint (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);\n\tint (*enable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*disable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*find_raw_port_number)(struct usb_hcd *, int);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n\tint (*submit_single_step_set_feature)(struct usb_hcd *, struct urb *, int);\n};\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct hdat_fadump_reg_entry {\n\t__be32 reg_type;\n\t__be32 reg_num;\n\t__be64 reg_val;\n};\n\nstruct hdat_fadump_thread_hdr {\n\t__be32 pir;\n\tu8 core_state;\n\tu8 reserved[3];\n\t__be32 offset;\n\t__be32 ecnt;\n\t__be32 esize;\n\t__be32 eactsz;\n};\n\nstruct hh_cache;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[12];\n};\n\nstruct hid_class_descriptor {\n\t__u8 bDescriptorType;\n\t__le16 wDescriptorLength;\n} __attribute__((packed));\n\nstruct hid_collection {\n\tint parent_idx;\n\tunsigned int type;\n\tunsigned int usage;\n\tunsigned int level;\n};\n\nstruct hid_report;\n\nstruct hid_control_fifo {\n\tunsigned char dir;\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_device;\n\nstruct hid_debug_list {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tchar *type;\n\t\t\tconst char *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tchar *ptr;\n\t\t\tconst char *ptr_const;\n\t\t};\n\t\tchar buf[0];\n\t} hid_debug_fifo;\n\tstruct fasync_struct *fasync;\n\tstruct hid_device *hdev;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct hid_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdHID;\n\t__u8 bCountryCode;\n\t__u8 bNumDescriptors;\n\tstruct hid_class_descriptor rpt_desc;\n\tstruct hid_class_descriptor opt_descs[0];\n} __attribute__((packed));\n\nstruct hid_report_enum {\n\tunsigned int numbered;\n\tstruct list_head report_list;\n\tstruct hid_report *report_id_hash[256];\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n\tlong unsigned int last_holder;\n};\n\nstruct hid_driver;\n\nstruct hid_ll_driver;\n\nstruct hid_field;\n\nstruct hid_usage;\n\nstruct hid_device {\n\tconst __u8 *dev_rdesc;\n\tconst __u8 *bpf_rdesc;\n\tconst __u8 *rdesc;\n\tunsigned int dev_rsize;\n\tunsigned int bpf_rsize;\n\tunsigned int rsize;\n\tunsigned int collection_size;\n\tstruct hid_collection *collection;\n\tunsigned int maxcollection;\n\tunsigned int maxapplication;\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\t__u32 version;\n\tenum hid_type type;\n\tunsigned int country;\n\tstruct hid_report_enum report_enum[3];\n\tstruct work_struct led_work;\n\tstruct semaphore driver_input_lock;\n\tstruct device dev;\n\tstruct hid_driver *driver;\n\tvoid *devres_group_id;\n\tconst struct hid_ll_driver *ll_driver;\n\tstruct mutex ll_open_lock;\n\tunsigned int ll_open_count;\n\tlong unsigned int status;\n\tunsigned int claimed;\n\tunsigned int quirks;\n\tunsigned int initial_quirks;\n\tbool io_started;\n\tstruct list_head inputs;\n\tvoid *hiddev;\n\tvoid *hidraw;\n\tchar name[128];\n\tchar phys[64];\n\tchar uniq[64];\n\tvoid *driver_data;\n\tint (*ff_init)(struct hid_device *);\n\tint (*hiddev_connect)(struct hid_device *, unsigned int);\n\tvoid (*hiddev_disconnect)(struct hid_device *);\n\tvoid (*hiddev_hid_event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*hiddev_report_event)(struct hid_device *, struct hid_report *);\n\tshort unsigned int debug;\n\tstruct dentry *debug_dir;\n\tstruct dentry *debug_rdesc;\n\tstruct dentry *debug_events;\n\tstruct list_head debug_list;\n\tspinlock_t debug_list_lock;\n\twait_queue_head_t debug_wait;\n\tstruct kref ref;\n\tunsigned int id;\n};\n\nstruct hid_device_id {\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hid_report_id;\n\nstruct hid_usage_id;\n\nstruct hid_input;\n\nstruct hid_driver {\n\tconst char *name;\n\tconst struct hid_device_id *id_table;\n\tstruct list_head dyn_list;\n\tspinlock_t dyn_lock;\n\tbool (*match)(struct hid_device *, bool);\n\tint (*probe)(struct hid_device *, const struct hid_device_id *);\n\tvoid (*remove)(struct hid_device *);\n\tconst struct hid_report_id *report_table;\n\tint (*raw_event)(struct hid_device *, struct hid_report *, u8 *, int);\n\tconst struct hid_usage_id *usage_table;\n\tint (*event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*report)(struct hid_device *, struct hid_report *);\n\tconst __u8 * (*report_fixup)(struct hid_device *, __u8 *, unsigned int *);\n\tint (*input_mapping)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_mapped)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_configured)(struct hid_device *, struct hid_input *);\n\tvoid (*feature_mapping)(struct hid_device *, struct hid_field *, struct hid_usage *);\n\tint (*suspend)(struct hid_device *, pm_message_t);\n\tint (*resume)(struct hid_device *);\n\tint (*reset_resume)(struct hid_device *);\n\tvoid (*on_hid_hw_open)(struct hid_device *);\n\tvoid (*on_hid_hw_close)(struct hid_device *);\n\tstruct device_driver driver;\n};\n\nstruct hid_dynid {\n\tstruct list_head list;\n\tstruct hid_device_id id;\n};\n\nstruct hid_field {\n\tunsigned int physical;\n\tunsigned int logical;\n\tunsigned int application;\n\tstruct hid_usage *usage;\n\tunsigned int maxusage;\n\tunsigned int flags;\n\tunsigned int report_offset;\n\tunsigned int report_size;\n\tunsigned int report_count;\n\tunsigned int report_type;\n\t__s32 *value;\n\t__s32 *new_value;\n\t__s32 *usages_priorities;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tbool ignored;\n\tstruct hid_report *report;\n\tunsigned int index;\n\tstruct hid_input *hidinput;\n\t__u16 dpad;\n\tunsigned int slot_idx;\n};\n\nstruct hid_field_entry {\n\tstruct list_head list;\n\tstruct hid_field *field;\n\tunsigned int index;\n\t__s32 priority;\n};\n\nstruct hid_global {\n\tunsigned int usage_page;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tunsigned int report_id;\n\tunsigned int report_size;\n\tunsigned int report_count;\n};\n\nstruct hid_input {\n\tstruct list_head list;\n\tstruct hid_report *report;\n\tstruct input_dev *input;\n\tconst char *name;\n\tstruct list_head reports;\n\tunsigned int application;\n\tbool registered;\n};\n\nstruct hid_item {\n\tunsigned int format;\n\t__u8 size;\n\t__u8 type;\n\t__u8 tag;\n\tunion {\n\t\t__u8 u8;\n\t\t__s8 s8;\n\t\t__u16 u16;\n\t\t__s16 s16;\n\t\t__u32 u32;\n\t\t__s32 s32;\n\t\tconst __u8 *longdata;\n\t} data;\n};\n\nstruct hid_ll_driver {\n\tint (*start)(struct hid_device *);\n\tvoid (*stop)(struct hid_device *);\n\tint (*open)(struct hid_device *);\n\tvoid (*close)(struct hid_device *);\n\tint (*power)(struct hid_device *, int);\n\tint (*parse)(struct hid_device *);\n\tvoid (*request)(struct hid_device *, struct hid_report *, int);\n\tint (*wait)(struct hid_device *);\n\tint (*raw_request)(struct hid_device *, unsigned char, __u8 *, size_t, unsigned char, int);\n\tint (*output_report)(struct hid_device *, __u8 *, size_t);\n\tint (*idle)(struct hid_device *, int, int, int);\n\tbool (*may_wakeup)(struct hid_device *);\n\tunsigned int max_buffer_size;\n};\n\nstruct hid_local {\n\tunsigned int usage[12288];\n\tu8 usage_size[12288];\n\tunsigned int collection_index[12288];\n\tunsigned int usage_index;\n\tunsigned int usage_minimum;\n\tunsigned int delimiter_depth;\n\tunsigned int delimiter_branch;\n};\n\nstruct hid_output_fifo {\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_parser {\n\tstruct hid_global global;\n\tstruct hid_global global_stack[4];\n\tunsigned int global_stack_ptr;\n\tstruct hid_local local;\n\tunsigned int *collection_stack;\n\tunsigned int collection_stack_ptr;\n\tunsigned int collection_stack_size;\n\tstruct hid_device *device;\n\tunsigned int scan_flags;\n};\n\nstruct hid_report {\n\tstruct list_head list;\n\tstruct list_head hidinput_list;\n\tstruct list_head field_entry_list;\n\tunsigned int id;\n\tenum hid_report_type type;\n\tunsigned int application;\n\tstruct hid_field *field[256];\n\tstruct hid_field_entry *field_entries;\n\tunsigned int maxfield;\n\tunsigned int size;\n\tstruct hid_device *device;\n\tbool tool_active;\n\tunsigned int tool;\n};\n\nstruct hid_report_id {\n\t__u32 report_type;\n};\n\nstruct hid_usage {\n\tunsigned int hid;\n\tunsigned int collection_index;\n\tunsigned int usage_index;\n\t__s8 resolution_multiplier;\n\t__s8 wheel_factor;\n\t__u16 code;\n\t__u8 type;\n\t__s16 hat_min;\n\t__s16 hat_max;\n\t__s16 hat_dir;\n\t__s16 wheel_accumulated;\n};\n\nstruct hid_usage_entry {\n\tunsigned int page;\n\tunsigned int usage;\n\tconst char *description;\n};\n\nstruct hid_usage_id {\n\t__u32 usage_hid;\n\t__u32 usage_type;\n\t__u32 usage_code;\n};\n\nstruct hiddev {\n\tint minor;\n\tint exist;\n\tint open;\n\tstruct mutex existancelock;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tbool initialized;\n};\n\nstruct hiddev_collection_info {\n\t__u32 index;\n\t__u32 type;\n\t__u32 usage;\n\t__u32 level;\n};\n\nstruct hiddev_devinfo {\n\t__u32 bustype;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 ifnum;\n\t__s16 vendor;\n\t__s16 product;\n\t__s16 version;\n\t__u32 num_applications;\n};\n\nstruct hiddev_event {\n\tunsigned int hid;\n\tint value;\n};\n\nstruct hiddev_field_info {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 field_index;\n\t__u32 maxusage;\n\t__u32 flags;\n\t__u32 physical;\n\t__u32 logical;\n\t__u32 application;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__u32 unit_exponent;\n\t__u32 unit;\n};\n\nstruct hiddev_usage_ref {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 field_index;\n\t__u32 usage_index;\n\t__u32 usage_code;\n\t__s32 value;\n};\n\nstruct hiddev_list {\n\tstruct hiddev_usage_ref buffer[2048];\n\tint head;\n\tint tail;\n\tunsigned int flags;\n\tstruct fasync_struct *fasync;\n\tstruct hiddev *hiddev;\n\tstruct list_head node;\n\tstruct mutex thread_lock;\n};\n\nstruct hiddev_report_info {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 num_fields;\n};\n\nstruct hiddev_usage_ref_multi {\n\tstruct hiddev_usage_ref uref;\n\t__u32 num_values;\n\t__s32 values[1024];\n};\n\nstruct hidraw {\n\tunsigned int minor;\n\tint exist;\n\tint open;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct device *dev;\n\tspinlock_t list_lock;\n\tstruct list_head list;\n};\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct hmac_ctx {\n\tstruct crypto_shash *hash;\n\tu8 pads[0];\n};\n\nstruct sha1_block_state {\n\tu32 h[5];\n};\n\nstruct sha1_ctx {\n\tstruct sha1_block_state state;\n\tu64 bytecount;\n\tu8 buf[64];\n};\n\nstruct hmac_sha1_ctx {\n\tstruct sha1_ctx sha_ctx;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha1_key {\n\tstruct sha1_block_state istate;\n\tstruct sha1_block_state ostate;\n};\n\nstruct hmac_sha224_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha224_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha256_ctx {\n\tstruct __hmac_sha256_ctx ctx;\n};\n\nstruct hmac_sha256_key {\n\tstruct __hmac_sha256_key key;\n};\n\nstruct hmac_sha384_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha384_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hmac_sha512_ctx {\n\tstruct __hmac_sha512_ctx ctx;\n};\n\nstruct hmac_sha512_key {\n\tstruct __hmac_sha512_key key;\n};\n\nstruct hmm_dma_map {\n\tstruct dma_iova_state state;\n\tlong unsigned int *pfn_list;\n\tdma_addr_t *dma_list;\n\tsize_t dma_entry_size;\n};\n\nstruct mmu_interval_notifier;\n\nstruct hmm_range {\n\tstruct mmu_interval_notifier *notifier;\n\tlong unsigned int notifier_seq;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int *hmm_pfns;\n\tlong unsigned int default_flags;\n\tlong unsigned int pfn_flags_mask;\n\tvoid *dev_private_owner;\n};\n\nstruct hmm_vma_walk {\n\tstruct hmm_range *range;\n\tlong unsigned int last;\n};\n\nstruct hotplug_slot_ops;\n\nstruct pci_slot;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, bool);\n};\n\nstruct housekeeping {\n\tstruct cpumask *cpumasks[4];\n\tlong unsigned int flags;\n};\n\nstruct hprobe {\n\tenum hprobe_state state;\n\tint srcu_idx;\n\tstruct uprobe *uprobe;\n};\n\nstruct hpt_resize_state {\n\tlong unsigned int shift;\n\tint commit_rc;\n};\n\nstruct seqcount_raw_spinlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_raw_spinlock seqcount_raw_spinlock_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_raw_spinlock_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tktime_t offset;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int online: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hrtimer_clock_base clock_base[8];\n\tcall_single_data_t csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n};\n\nstruct hs_primary_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\t__u8 id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 unused4[28];\n\t__u8 root_directory_record[34];\n};\n\nstruct hs_volume_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2033];\n};\n\nstruct hsr_tag {\n\t__be16 path_and_LSDU_size;\n\t__be16 sequence_nr;\n\t__be16 encap_proto;\n};\n\nstruct hstate {\n\tstruct mutex resize_lock;\n\tstruct lock_class_key resize_key;\n\tint next_nid_to_alloc;\n\tint next_nid_to_free;\n\tunsigned int order;\n\tunsigned int demote_order;\n\tlong unsigned int mask;\n\tlong unsigned int max_huge_pages;\n\tlong unsigned int nr_huge_pages;\n\tlong unsigned int free_huge_pages;\n\tlong unsigned int resv_huge_pages;\n\tlong unsigned int surplus_huge_pages;\n\tlong unsigned int nr_overcommit_huge_pages;\n\tstruct list_head hugepage_activelist;\n\tstruct list_head hugepage_freelists[256];\n\tunsigned int max_huge_pages_node[256];\n\tunsigned int nr_huge_pages_node[256];\n\tunsigned int free_huge_pages_node[256];\n\tunsigned int surplus_huge_pages_node[256];\n\tchar name[32];\n};\n\nstruct htab_btf_record {\n\tstruct btf_record *record;\n\tu32 key_size;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tvoid *ptr_to_pptr;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tlong: 0;\n\tchar key[0];\n};\n\nstruct huge_bootmem_page {\n\tstruct list_head list;\n\tstruct hstate *hstate;\n\tlong unsigned int flags;\n\tstruct cma *cma;\n};\n\nstruct hugepage_subpool {\n\tspinlock_t lock;\n\tlong int count;\n\tlong int max_hpages;\n\tlong int used_hpages;\n\tstruct hstate *hstate;\n\tlong int min_hpages;\n\tlong int rsv_hpages;\n};\n\nstruct page_counter {\n\tatomic_long_t usage;\n\tlong unsigned int failcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int emin;\n\tatomic_long_t min_usage;\n\tatomic_long_t children_min_usage;\n\tlong unsigned int elow;\n\tatomic_long_t low_usage;\n\tatomic_long_t children_low_usage;\n\tlong unsigned int watermark;\n\tlong unsigned int local_watermark;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tbool protection_support;\n\tbool track_failcnt;\n\tlong unsigned int min;\n\tlong unsigned int low;\n\tlong unsigned int high;\n\tlong unsigned int max;\n\tstruct page_counter *parent;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hugetlb_cgroup_per_node;\n\nstruct hugetlb_cgroup {\n\tstruct cgroup_subsys_state css;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter hugepage[15];\n\tstruct page_counter rsvd_hugepage[15];\n\tatomic_long_t events[15];\n\tatomic_long_t events_local[15];\n\tstruct cgroup_file events_file[15];\n\tstruct cgroup_file events_local_file[15];\n\tstruct hugetlb_cgroup_per_node *nodeinfo[0];\n};\n\nstruct hugetlb_cgroup_per_node {\n\tlong unsigned int usage[15];\n};\n\nstruct hugetlb_cmdline {\n\tchar *val;\n\tint (*setup)(char *);\n};\n\nstruct hugetlb_vma_lock {\n\tstruct kref refs;\n\tstruct rw_semaphore rw_sema;\n\tstruct vm_area_struct *vma;\n};\n\nstruct hugetlbfs_fs_context {\n\tstruct hstate *hstate;\n\tlong long unsigned int max_size_opt;\n\tlong long unsigned int min_size_opt;\n\tlong int max_hpages;\n\tlong int nr_inodes;\n\tlong int min_hpages;\n\tenum hugetlbfs_size_type max_val_type;\n\tenum hugetlbfs_size_type min_val_type;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hugetlbfs_inode_info {\n\tstruct inode vfs_inode;\n\tunsigned int seals;\n};\n\nstruct hugetlbfs_sb_info {\n\tlong int max_inodes;\n\tlong int free_inodes;\n\tspinlock_t stat_lock;\n\tstruct hstate *hstate;\n\tstruct hugepage_subpool *spool;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct hv_24x7_catalog_page_0 {\n\t__be32 magic;\n\t__be32 length;\n\t__be64 version;\n\t__u8 build_time_stamp[16];\n\t__u8 reserved2[32];\n\t__be16 schema_data_offs;\n\t__be16 schema_data_len;\n\t__be16 schema_entry_count;\n\t__u8 reserved3[2];\n\t__be16 event_data_offs;\n\t__be16 event_data_len;\n\t__be16 event_entry_count;\n\t__u8 reserved4[2];\n\t__be16 group_data_offs;\n\t__be16 group_data_len;\n\t__be16 group_entry_count;\n\t__u8 reserved5[2];\n\t__be16 formula_data_offs;\n\t__be16 formula_data_len;\n\t__be16 formula_entry_count;\n\t__u8 reserved6[2];\n};\n\nstruct hv_24x7_result {\n\t__u8 result_ix;\n\t__u8 results_complete;\n\t__be16 num_elements_returned;\n\t__be16 result_element_data_size;\n\t__u8 reserved[2];\n\tchar elements[0];\n};\n\nstruct hv_24x7_data_result_buffer {\n\t__u8 interface_version;\n\t__u8 num_results;\n\t__u8 reserved[1];\n\t__u8 failing_request_ix;\n\t__be32 detailed_rc;\n\t__be64 cec_cfg_instance_id;\n\t__be64 catalog_version_num;\n\t__u8 reserved2[8];\n\tstruct hv_24x7_result results[0];\n};\n\nstruct hv_24x7_event_data {\n\t__be16 length;\n\t__u8 reserved1[2];\n\t__u8 domain;\n\t__u8 reserved2[1];\n\t__be16 event_group_record_offs;\n\t__be16 event_group_record_len;\n\t__be16 event_counter_offs;\n\t__be32 flags;\n\t__be16 primary_group_ix;\n\t__be16 group_count;\n\t__be16 event_name_len;\n\t__u8 remainder[0];\n} __attribute__((packed));\n\nstruct hv_24x7_hw {\n\tstruct perf_event *events[255];\n};\n\nstruct hv_24x7_request {\n\t__u8 performance_domain;\n\t__u8 reserved[1];\n\t__be16 data_size;\n\t__be32 data_offset;\n\t__be16 starting_lpar_ix;\n\t__be16 max_num_lpars;\n\t__be16 starting_ix;\n\t__be16 max_ix;\n\t__u8 starting_thread_group_ix;\n\t__u8 max_num_thread_groups;\n\t__u8 reserved2[14];\n};\n\nstruct hv_24x7_request_buffer {\n\t__u8 interface_version;\n\t__u8 num_requests;\n\t__u8 reserved[14];\n\tstruct hv_24x7_request requests[0];\n};\n\nstruct hv_get_perf_counter_info_params {\n\t__be32 counter_request;\n\t__be32 starting_index;\n\t__be16 secondary_index;\n\t__be16 returned_values;\n\t__be32 detail_rc;\n\t__be16 cv_element_size;\n\t__u8 counter_info_version_in;\n\t__u8 counter_info_version_out;\n\t__u8 reserved[12];\n\t__u8 counter_value[0];\n};\n\nstruct hv_gpci_request_buffer {\n\tstruct hv_get_perf_counter_info_params params;\n\tuint8_t bytes[4064];\n};\n\nstruct hv_gpci_system_performance_capabilities {\n\t__u8 perf_collect_privileged;\n\t__u8 capability_mask;\n\t__u8 reserved[14];\n};\n\nstruct hv_nx_cop_caps {\n\t__be64 descriptor;\n\t__be64 req_max_processed_len;\n\t__be64 min_compress_len;\n\t__be64 min_decompress_len;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hvc_struct;\n\nstruct hv_ops {\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tint (*flush)(uint32_t, bool);\n\tint (*notifier_add)(struct hvc_struct *, int);\n\tvoid (*notifier_del)(struct hvc_struct *, int);\n\tvoid (*notifier_hangup)(struct hvc_struct *, int);\n\tint (*tiocmget)(struct hvc_struct *);\n\tint (*tiocmset)(struct hvc_struct *, unsigned int, unsigned int);\n\tvoid (*dtr_rts)(struct hvc_struct *, bool);\n};\n\nstruct hv_perf_caps {\n\tu16 version;\n\tu16 collect_privileged: 1;\n\tu16 ga: 1;\n\tu16 expanded: 1;\n\tu16 lab: 1;\n\tu16 unused: 12;\n};\n\nstruct hv_vas_all_caps {\n\t__be64 descriptor;\n\t__be64 feat_type;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hv_vas_cop_feat_caps {\n\t__be64 descriptor;\n\tu8 win_type;\n\tu8 user_mode;\n\t__be16 max_lpar_creds;\n\t__be16 max_win_creds;\n\tunion {\n\t\t__be16 reserved;\n\t\t__be16 def_lpar_creds;\n\t};\n\t__be16 target_lpar_creds;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hvsi_priv {\n\tunsigned int inbuf_len;\n\tunsigned char inbuf[255];\n\tunsigned int inbuf_cur;\n\tsize_t inbuf_pktlen;\n\tatomic_t seqno;\n\tunsigned int opened: 1;\n\tunsigned int established: 1;\n\tunsigned int is_console: 1;\n\tunsigned int mctrl_update: 1;\n\tshort unsigned int mctrl;\n\tstruct tty_struct *tty;\n\tssize_t (*get_chars)(uint32_t, u8 *, size_t);\n\tssize_t (*put_chars)(uint32_t, const u8 *, size_t);\n\tuint32_t termno;\n};\n\nstruct hvc_opal_priv {\n\thv_protocol_t proto;\n\tstruct hvsi_priv hvsi;\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tunsigned int used;\n\tunsigned int size;\n\tunsigned int commit;\n\tunsigned int lookahead;\n\tunsigned int read;\n\tbool flags;\n\tlong: 0;\n\tu8 data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tu8 *xmit_buf;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tu8 *type;\n\t\t\tconst u8 *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tu8 *ptr;\n\t\t\tconst u8 *ptr_const;\n\t\t};\n\t\tu8 buf[0];\n\t} xmit_fifo;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct hvc_struct {\n\tstruct tty_port port;\n\tspinlock_t lock;\n\tint index;\n\tint do_wakeup;\n\tint outbuf_size;\n\tint n_outbuf;\n\tuint32_t vtermno;\n\tconst struct hv_ops *ops;\n\tint irq_requested;\n\tint data;\n\tstruct winsize ws;\n\tstruct work_struct tty_resize;\n\tstruct list_head next;\n\tlong unsigned int flags;\n\tu8 outbuf[0];\n};\n\nstruct hvcall_mpp_data {\n\tlong unsigned int entitled_mem;\n\tlong unsigned int mapped_mem;\n\tshort unsigned int group_num;\n\tshort unsigned int pool_num;\n\tunsigned char mem_weight;\n\tunsigned char unallocated_mem_weight;\n\tlong unsigned int unallocated_entitlement;\n\tlong unsigned int pool_size;\n\tlong int loan_request;\n\tlong unsigned int backing_mem;\n};\n\nstruct hvcall_mpp_x_data {\n\tlong unsigned int coalesced_bytes;\n\tlong unsigned int pool_coalesced_bytes;\n\tlong unsigned int pool_purr_cycles;\n\tlong unsigned int pool_spurr_cycles;\n\tlong unsigned int reserved[3];\n};\n\nstruct hvcall_ppp_data {\n\tu64 entitlement;\n\tu64 unallocated_entitlement;\n\tu16 group_num;\n\tu16 pool_num;\n\tu8 capped;\n\tu8 weight;\n\tu8 unallocated_weight;\n\tu8 resource_group_index;\n\tu16 active_procs_in_resource_group;\n\tu16 active_procs_in_pool;\n\tu16 active_system_procs;\n\tu16 phys_platform_procs;\n\tu32 max_proc_cap_avail;\n\tu32 entitled_proc_cap_avail;\n};\n\nstruct hvpipe_event_buf {\n\t__be32 srcID;\n\tu8 event_type;\n};\n\nstruct hvpipe_source_info {\n\tstruct list_head list;\n\tu32 srcID;\n\tu32 hvpipe_status;\n\twait_queue_head_t recv_wqh;\n\tstruct task_struct *tsk;\n};\n\nstruct hvsi_header {\n\tuint8_t type;\n\tuint8_t len;\n\t__be16 seqno;\n};\n\nstruct hvsi_control {\n\tstruct hvsi_header hdr;\n\t__be16 verb;\n\t__be32 word;\n\t__be32 mask;\n} __attribute__((packed));\n\nstruct hvsi_data {\n\tstruct hvsi_header hdr;\n\tuint8_t data[12];\n};\n\nstruct hvsi_query {\n\tstruct hvsi_header hdr;\n\t__be16 verb;\n};\n\nstruct hvsi_query_response {\n\tstruct hvsi_header hdr;\n\t__be16 verb;\n\t__be16 query_seqno;\n\tunion {\n\t\tuint8_t version;\n\t\t__be32 mctrl_word;\n\t} u;\n};\n\nstruct hvterm_priv {\n\tu32 termno;\n\thv_protocol_t proto;\n\tstruct hvsi_priv hvsi;\n\tspinlock_t buf_lock;\n\tu8 buf[16];\n\tsize_t left;\n\tsize_t offset;\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 config1;\n\t\t\tu64 last_tag;\n\t\t\tu64 dyn_constraint;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tu64 aux_config;\n\t\t\tunsigned int aux_paused;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tstruct arch_hw_breakpoint info;\n\t\t\tstruct rhlist_head bp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tunion {\n\t\tstruct {\n\t\t\tu64 last_period;\n\t\t\tlocal64_t period_left;\n\t\t};\n\t\tstruct {\n\t\t\tu64 saved_metric;\n\t\t\tu64 saved_slots;\n\t\t};\n\t};\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct hwerr_info {\n\tatomic_t count;\n\ttime64_t timestamp;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n};\n\nstruct hwmon_channel_info {\n\tenum hwmon_sensor_types type;\n\tconst u32 *config;\n};\n\nstruct hwmon_ops;\n\nstruct hwmon_chip_info {\n\tconst struct hwmon_ops *ops;\n\tconst struct hwmon_channel_info * const *info;\n};\n\nstruct hwmon_device {\n\tconst char *name;\n\tconst char *label;\n\tstruct device dev;\n\tconst struct hwmon_chip_info *chip;\n\tstruct mutex lock;\n\tstruct list_head tzdata;\n\tstruct attribute_group group;\n\tconst struct attribute_group **groups;\n};\n\nstruct hwmon_device_attribute {\n\tstruct device_attribute dev_attr;\n\tconst struct hwmon_ops *ops;\n\tenum hwmon_sensor_types type;\n\tu32 attr;\n\tint index;\n\tchar name[32];\n};\n\nstruct hwmon_ops {\n\tumode_t visible;\n\tumode_t (*is_visible)(const void *, enum hwmon_sensor_types, u32, int);\n\tint (*read)(struct device *, enum hwmon_sensor_types, u32, int, long int *);\n\tint (*read_string)(struct device *, enum hwmon_sensor_types, u32, int, const char **);\n\tint (*write)(struct device *, enum hwmon_sensor_types, u32, int, long int);\n};\n\nstruct thermal_zone_device;\n\nstruct hwmon_thermal_data {\n\tstruct list_head node;\n\tstruct device *dev;\n\tint index;\n\tstruct thermal_zone_device *tzd;\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct work_struct cleanup_work;\n\tstruct completion cleanup_done;\n\tstruct completion dying;\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nstruct hwtstamp_provider_desc {\n\tint index;\n\tenum hwtstamp_provider_qualifier qualifier;\n};\n\nstruct hwtstamp_provider {\n\tstruct callback_head callback_head;\n\tenum hwtstamp_source source;\n\tstruct phy_device *phydev;\n\tstruct hwtstamp_provider_desc desc;\n};\n\nstruct hypertas_fw_feature {\n\tlong unsigned int val;\n\tchar *name;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n};\n\nstruct i2c_algo_bit_data {\n\tvoid *data;\n\tvoid (*setsda)(void *, int);\n\tvoid (*setscl)(void *, int);\n\tint (*getsda)(void *);\n\tint (*getscl)(void *);\n\tint (*pre_xfer)(struct i2c_adapter *);\n\tvoid (*post_xfer)(struct i2c_adapter *);\n\tint udelay;\n\tint timeout;\n\tbool can_do_atomic;\n};\n\nstruct i2c_msg;\n\nunion i2c_smbus_data;\n\nstruct i2c_algorithm {\n\tunion {\n\t\tint (*xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tunion {\n\t\tint (*xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\t};\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n};\n\nstruct software_node;\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct fwnode_handle *fwnode;\n\tconst struct software_node *swnode;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *pins_default;\n\tstruct pinctrl_state *pins_gpio;\n};\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n\tvoid *devres_group_id;\n\tstruct dentry *debugfs;\n};\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct i2c_dev {\n\tstruct list_head list;\n\tstruct i2c_adapter *adap;\n\tstruct device dev;\n\tstruct cdev cdev;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *);\n\tvoid (*remove)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tu32 flags;\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nstruct i2c_of_probe_ops;\n\nstruct i2c_of_probe_cfg {\n\tconst struct i2c_of_probe_ops *ops;\n\tconst char *type;\n};\n\nstruct i2c_of_probe_ops {\n\tint (*enable)(struct device *, struct device_node *, void *);\n\tvoid (*cleanup_early)(struct device *, void *);\n\tvoid (*cleanup)(struct device *, void *);\n};\n\nstruct i2c_of_probe_simple_opts;\n\nstruct i2c_of_probe_simple_ctx {\n\tconst struct i2c_of_probe_simple_opts *opts;\n\tstruct regulator *supply;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct i2c_of_probe_simple_opts {\n\tconst char *res_node_compatible;\n\tconst char *supply_name;\n\tconst char *gpio_name;\n\tunsigned int post_power_on_delay_ms;\n\tunsigned int post_gpio_config_delay_ms;\n\tbool gpio_assert_to_enable;\n};\n\nstruct i2c_rdwr_ioctl_data {\n\tstruct i2c_msg *msgs;\n\t__u32 nmsgs;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct i2c_smbus_ioctl_data {\n\t__u8 read_write;\n\t__u8 command;\n\t__u32 size;\n\tunion i2c_smbus_data *data;\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct i8042_port {\n\tstruct serio *serio;\n\tint irq;\n\tbool exists;\n\tbool driver_bound;\n\tsigned char mux;\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tunion {\n\t\tkuid_t ia_uid;\n\t\tvfsuid_t ia_vfsuid;\n\t};\n\tunion {\n\t\tkgid_t ia_gid;\n\t\tvfsgid_t ia_vfsgid;\n\t};\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n};\n\nstruct ib_pd;\n\nstruct ib_uobject;\n\nstruct ib_gid_attr;\n\nstruct ib_ah {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tconst struct ib_gid_attr *sgid_attr;\n\tenum rdma_ah_attr_type type;\n};\n\nstruct ib_ah_attr {\n\tu16 dlid;\n\tu8 src_path_bits;\n};\n\nstruct ib_core_device {\n\tstruct device dev;\n\tpossible_net_t rdma_net;\n\tstruct kobject *ports_kobj;\n\tstruct list_head port_list;\n\tstruct ib_device *owner;\n};\n\nstruct ib_counters {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_counters_read_attr {\n\tu64 *counters_buff;\n\tu32 ncounters;\n\tu32 flags;\n};\n\nstruct ib_ucq_object;\n\nstruct ib_cq;\n\ntypedef void (*ib_comp_handler)(struct ib_cq *, void *);\n\nstruct irq_poll;\n\ntypedef int irq_poll_fn(struct irq_poll *, int);\n\nstruct irq_poll {\n\tstruct list_head list;\n\tlong unsigned int state;\n\tint weight;\n\tirq_poll_fn *poll;\n};\n\nstruct rdma_restrack_entry {\n\tbool valid;\n\tu8 no_track: 1;\n\tstruct kref kref;\n\tstruct completion comp;\n\tstruct task_struct *task;\n\tconst char *kern_name;\n\tenum rdma_restrack_type type;\n\tbool user;\n\tu32 id;\n};\n\nstruct ib_event;\n\nstruct ib_wc;\n\nstruct ib_cq {\n\tstruct ib_device *device;\n\tstruct ib_ucq_object *uobject;\n\tib_comp_handler comp_handler;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *cq_context;\n\tint cqe;\n\tunsigned int cqe_used;\n\tatomic_t usecnt;\n\tenum ib_poll_context poll_ctx;\n\tstruct ib_wc *wc;\n\tstruct list_head pool_entry;\n\tunion {\n\t\tstruct irq_poll iop;\n\t\tstruct work_struct work;\n\t};\n\tstruct workqueue_struct *comp_wq;\n\tstruct dim *dim;\n\tktime_t timestamp;\n\tu8 interrupt: 1;\n\tu8 shared: 1;\n\tunsigned int comp_vector;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_cq_caps {\n\tu16 max_cq_moderation_count;\n\tu16 max_cq_moderation_period;\n};\n\nstruct ib_cq_init_attr {\n\tunsigned int cqe;\n\tu32 comp_vector;\n\tu32 flags;\n};\n\nstruct ib_cqe {\n\tvoid (*done)(struct ib_cq *, struct ib_wc *);\n};\n\nstruct ib_mad;\n\nstruct uverbs_attr_bundle;\n\nstruct ib_umem;\n\nstruct rdma_cm_id;\n\nstruct iw_cm_id;\n\nstruct iw_cm_conn_param;\n\nstruct ib_uverbs_file;\n\nstruct ib_qp;\n\nstruct ib_send_wr;\n\nstruct ib_recv_wr;\n\nstruct ib_srq;\n\nstruct ib_grh;\n\nstruct ib_device_attr;\n\nstruct ib_udata;\n\nstruct ib_device_modify;\n\nstruct ib_port_attr;\n\nstruct ib_port_modify;\n\nstruct ib_port_immutable;\n\nstruct rdma_netdev_alloc_params;\n\nunion ib_gid;\n\nstruct ib_ucontext;\n\nstruct rdma_user_mmap_entry;\n\nstruct phys_vec;\n\nstruct rdma_ah_init_attr;\n\nstruct rdma_ah_attr;\n\nstruct ib_srq_init_attr;\n\nstruct ib_srq_attr;\n\nstruct ib_qp_init_attr;\n\nstruct ib_qp_attr;\n\nstruct ib_mr;\n\nstruct ib_dmah;\n\nstruct ib_sge;\n\nstruct ib_mr_status;\n\nstruct ib_mw;\n\nstruct ib_xrcd;\n\nstruct ib_flow;\n\nstruct ib_flow_attr;\n\nstruct ib_flow_action;\n\nstruct ifla_vf_info;\n\nstruct ifla_vf_stats;\n\nstruct ifla_vf_guid;\n\nstruct ib_wq;\n\nstruct ib_wq_init_attr;\n\nstruct ib_wq_attr;\n\nstruct ib_rwq_ind_table;\n\nstruct ib_rwq_ind_table_init_attr;\n\nstruct ib_dm;\n\nstruct ib_dm_alloc_attr;\n\nstruct ib_dm_mr_attr;\n\nstruct rdma_hw_stats;\n\nstruct rdma_counter;\n\nstruct ib_device_ops {\n\tstruct module *owner;\n\tenum rdma_driver_id driver_id;\n\tu32 uverbs_abi_ver;\n\tunsigned int uverbs_no_driver_id_binding: 1;\n\tconst struct attribute_group *device_group;\n\tconst struct attribute_group **port_groups;\n\tint (*post_send)(struct ib_qp *, const struct ib_send_wr *, const struct ib_send_wr **);\n\tint (*post_recv)(struct ib_qp *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tvoid (*drain_rq)(struct ib_qp *);\n\tvoid (*drain_sq)(struct ib_qp *);\n\tint (*poll_cq)(struct ib_cq *, int, struct ib_wc *);\n\tint (*peek_cq)(struct ib_cq *, int);\n\tint (*req_notify_cq)(struct ib_cq *, enum ib_cq_notify_flags);\n\tint (*post_srq_recv)(struct ib_srq *, const struct ib_recv_wr *, const struct ib_recv_wr **);\n\tint (*process_mad)(struct ib_device *, int, u32, const struct ib_wc *, const struct ib_grh *, const struct ib_mad *, struct ib_mad *, size_t *, u16 *);\n\tint (*query_device)(struct ib_device *, struct ib_device_attr *, struct ib_udata *);\n\tint (*modify_device)(struct ib_device *, int, struct ib_device_modify *);\n\tvoid (*get_dev_fw_str)(struct ib_device *, char *);\n\tconst struct cpumask * (*get_vector_affinity)(struct ib_device *, int);\n\tint (*query_port)(struct ib_device *, u32, struct ib_port_attr *);\n\tint (*query_port_speed)(struct ib_device *, u32, u64 *);\n\tint (*modify_port)(struct ib_device *, u32, int, struct ib_port_modify *);\n\tint (*get_port_immutable)(struct ib_device *, u32, struct ib_port_immutable *);\n\tenum rdma_link_layer (*get_link_layer)(struct ib_device *, u32);\n\tstruct net_device * (*get_netdev)(struct ib_device *, u32);\n\tstruct net_device * (*alloc_rdma_netdev)(struct ib_device *, u32, enum rdma_netdev_t, const char *, unsigned char, void (*)(struct net_device *));\n\tint (*rdma_netdev_get_params)(struct ib_device *, u32, enum rdma_netdev_t, struct rdma_netdev_alloc_params *);\n\tint (*query_gid)(struct ib_device *, u32, int, union ib_gid *);\n\tint (*add_gid)(const struct ib_gid_attr *, void **);\n\tint (*del_gid)(const struct ib_gid_attr *, void **);\n\tint (*query_pkey)(struct ib_device *, u32, u16, u16 *);\n\tint (*alloc_ucontext)(struct ib_ucontext *, struct ib_udata *);\n\tvoid (*dealloc_ucontext)(struct ib_ucontext *);\n\tint (*mmap)(struct ib_ucontext *, struct vm_area_struct *);\n\tvoid (*mmap_free)(struct rdma_user_mmap_entry *);\n\tint (*mmap_get_pfns)(struct rdma_user_mmap_entry *, struct phys_vec *, struct p2pdma_provider **);\n\tstruct rdma_user_mmap_entry * (*pgoff_to_mmap_entry)(struct ib_ucontext *, off_t);\n\tvoid (*disassociate_ucontext)(struct ib_ucontext *);\n\tint (*alloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*dealloc_pd)(struct ib_pd *, struct ib_udata *);\n\tint (*create_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*create_user_ah)(struct ib_ah *, struct rdma_ah_init_attr *, struct ib_udata *);\n\tint (*modify_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*query_ah)(struct ib_ah *, struct rdma_ah_attr *);\n\tint (*destroy_ah)(struct ib_ah *, u32);\n\tint (*create_srq)(struct ib_srq *, struct ib_srq_init_attr *, struct ib_udata *);\n\tint (*modify_srq)(struct ib_srq *, struct ib_srq_attr *, enum ib_srq_attr_mask, struct ib_udata *);\n\tint (*query_srq)(struct ib_srq *, struct ib_srq_attr *);\n\tint (*destroy_srq)(struct ib_srq *, struct ib_udata *);\n\tint (*create_qp)(struct ib_qp *, struct ib_qp_init_attr *, struct ib_udata *);\n\tint (*modify_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);\n\tint (*query_qp)(struct ib_qp *, struct ib_qp_attr *, int, struct ib_qp_init_attr *);\n\tint (*destroy_qp)(struct ib_qp *, struct ib_udata *);\n\tint (*create_cq)(struct ib_cq *, const struct ib_cq_init_attr *, struct uverbs_attr_bundle *);\n\tint (*create_cq_umem)(struct ib_cq *, const struct ib_cq_init_attr *, struct ib_umem *, struct uverbs_attr_bundle *);\n\tint (*modify_cq)(struct ib_cq *, u16, u16);\n\tint (*destroy_cq)(struct ib_cq *, struct ib_udata *);\n\tint (*resize_cq)(struct ib_cq *, int, struct ib_udata *);\n\tint (*pre_destroy_cq)(struct ib_cq *);\n\tvoid (*post_destroy_cq)(struct ib_cq *);\n\tstruct ib_mr * (*get_dma_mr)(struct ib_pd *, int);\n\tstruct ib_mr * (*reg_user_mr)(struct ib_pd *, u64, u64, u64, int, struct ib_dmah *, struct ib_udata *);\n\tstruct ib_mr * (*reg_user_mr_dmabuf)(struct ib_pd *, u64, u64, u64, int, int, struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*rereg_user_mr)(struct ib_mr *, int, u64, u64, u64, int, struct ib_pd *, struct ib_udata *);\n\tint (*dereg_mr)(struct ib_mr *, struct ib_udata *);\n\tstruct ib_mr * (*alloc_mr)(struct ib_pd *, enum ib_mr_type, u32);\n\tstruct ib_mr * (*alloc_mr_integrity)(struct ib_pd *, u32, u32);\n\tint (*advise_mr)(struct ib_pd *, enum ib_uverbs_advise_mr_advice, u32, struct ib_sge *, u32, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg)(struct ib_mr *, struct scatterlist *, int, unsigned int *);\n\tint (*check_mr_status)(struct ib_mr *, u32, struct ib_mr_status *);\n\tint (*alloc_mw)(struct ib_mw *, struct ib_udata *);\n\tint (*dealloc_mw)(struct ib_mw *);\n\tint (*attach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*detach_mcast)(struct ib_qp *, union ib_gid *, u16);\n\tint (*alloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tint (*dealloc_xrcd)(struct ib_xrcd *, struct ib_udata *);\n\tstruct ib_flow * (*create_flow)(struct ib_qp *, struct ib_flow_attr *, struct ib_udata *);\n\tint (*destroy_flow)(struct ib_flow *);\n\tint (*destroy_flow_action)(struct ib_flow_action *);\n\tint (*set_vf_link_state)(struct ib_device *, int, u32, int);\n\tint (*get_vf_config)(struct ib_device *, int, u32, struct ifla_vf_info *);\n\tint (*get_vf_stats)(struct ib_device *, int, u32, struct ifla_vf_stats *);\n\tint (*get_vf_guid)(struct ib_device *, int, u32, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*set_vf_guid)(struct ib_device *, int, u32, u64, int);\n\tstruct ib_wq * (*create_wq)(struct ib_pd *, struct ib_wq_init_attr *, struct ib_udata *);\n\tint (*destroy_wq)(struct ib_wq *, struct ib_udata *);\n\tint (*modify_wq)(struct ib_wq *, struct ib_wq_attr *, u32, struct ib_udata *);\n\tint (*create_rwq_ind_table)(struct ib_rwq_ind_table *, struct ib_rwq_ind_table_init_attr *, struct ib_udata *);\n\tint (*destroy_rwq_ind_table)(struct ib_rwq_ind_table *);\n\tstruct ib_dm * (*alloc_dm)(struct ib_device *, struct ib_ucontext *, struct ib_dm_alloc_attr *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dm)(struct ib_dm *, struct uverbs_attr_bundle *);\n\tint (*alloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tint (*dealloc_dmah)(struct ib_dmah *, struct uverbs_attr_bundle *);\n\tstruct ib_mr * (*reg_dm_mr)(struct ib_pd *, struct ib_dm *, struct ib_dm_mr_attr *, struct uverbs_attr_bundle *);\n\tint (*create_counters)(struct ib_counters *, struct uverbs_attr_bundle *);\n\tint (*destroy_counters)(struct ib_counters *);\n\tint (*read_counters)(struct ib_counters *, struct ib_counters_read_attr *, struct uverbs_attr_bundle *);\n\tint (*map_mr_sg_pi)(struct ib_mr *, struct scatterlist *, int, unsigned int *, struct scatterlist *, int, unsigned int *);\n\tstruct rdma_hw_stats * (*alloc_hw_device_stats)(struct ib_device *);\n\tstruct rdma_hw_stats * (*alloc_hw_port_stats)(struct ib_device *, u32);\n\tint (*get_hw_stats)(struct ib_device *, struct rdma_hw_stats *, u32, int);\n\tint (*modify_hw_stat)(struct ib_device *, u32, unsigned int, bool);\n\tint (*fill_res_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_mr_entry_raw)(struct sk_buff *, struct ib_mr *);\n\tint (*fill_res_cq_entry)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_cq_entry_raw)(struct sk_buff *, struct ib_cq *);\n\tint (*fill_res_qp_entry)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_qp_entry_raw)(struct sk_buff *, struct ib_qp *);\n\tint (*fill_res_cm_id_entry)(struct sk_buff *, struct rdma_cm_id *);\n\tint (*fill_res_srq_entry)(struct sk_buff *, struct ib_srq *);\n\tint (*fill_res_srq_entry_raw)(struct sk_buff *, struct ib_srq *);\n\tint (*enable_driver)(struct ib_device *);\n\tvoid (*dealloc_driver)(struct ib_device *);\n\tvoid (*iw_add_ref)(struct ib_qp *);\n\tvoid (*iw_rem_ref)(struct ib_qp *);\n\tstruct ib_qp * (*iw_get_qp)(struct ib_device *, int);\n\tint (*iw_connect)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_accept)(struct iw_cm_id *, struct iw_cm_conn_param *);\n\tint (*iw_reject)(struct iw_cm_id *, const void *, u8);\n\tint (*iw_create_listen)(struct iw_cm_id *, int);\n\tint (*iw_destroy_listen)(struct iw_cm_id *);\n\tint (*counter_bind_qp)(struct rdma_counter *, struct ib_qp *, u32);\n\tint (*counter_unbind_qp)(struct ib_qp *, u32);\n\tint (*counter_dealloc)(struct rdma_counter *);\n\tstruct rdma_hw_stats * (*counter_alloc_stats)(struct rdma_counter *);\n\tint (*counter_update_stats)(struct rdma_counter *);\n\tvoid (*counter_init)(struct rdma_counter *);\n\tint (*fill_stat_mr_entry)(struct sk_buff *, struct ib_mr *);\n\tint (*query_ucontext)(struct ib_ucontext *, struct uverbs_attr_bundle *);\n\tint (*get_numa_node)(struct ib_device *);\n\tstruct ib_device * (*add_sub_dev)(struct ib_device *, enum rdma_nl_dev_type, const char *);\n\tvoid (*del_sub_dev)(struct ib_device *);\n\tvoid (*ufile_hw_cleanup)(struct ib_uverbs_file *);\n\tvoid (*report_port_event)(struct ib_device *, struct net_device *, long unsigned int);\n\tsize_t size_ib_ah;\n\tsize_t size_ib_counters;\n\tsize_t size_ib_cq;\n\tsize_t size_ib_dmah;\n\tsize_t size_ib_mw;\n\tsize_t size_ib_pd;\n\tsize_t size_ib_qp;\n\tsize_t size_ib_rwq_ind_table;\n\tsize_t size_ib_srq;\n\tsize_t size_ib_ucontext;\n\tsize_t size_ib_xrcd;\n\tsize_t size_rdma_counter;\n};\n\nstruct ib_odp_caps {\n\tuint64_t general_caps;\n\tstruct {\n\t\tuint32_t rc_odp_caps;\n\t\tuint32_t uc_odp_caps;\n\t\tuint32_t ud_odp_caps;\n\t\tuint32_t xrc_odp_caps;\n\t} per_transport_caps;\n};\n\nstruct ib_rss_caps {\n\tu32 supported_qpts;\n\tu32 max_rwq_indirection_tables;\n\tu32 max_rwq_indirection_table_size;\n};\n\nstruct ib_tm_caps {\n\tu32 max_rndv_hdr_size;\n\tu32 max_num_tags;\n\tu32 flags;\n\tu32 max_ops;\n\tu32 max_sge;\n};\n\nstruct ib_device_attr {\n\tu64 fw_ver;\n\t__be64 sys_image_guid;\n\tu64 max_mr_size;\n\tu64 page_size_cap;\n\tu32 vendor_id;\n\tu32 vendor_part_id;\n\tu32 hw_ver;\n\tint max_qp;\n\tint max_qp_wr;\n\tu64 device_cap_flags;\n\tu64 kernel_cap_flags;\n\tint max_send_sge;\n\tint max_recv_sge;\n\tint max_sge_rd;\n\tint max_cq;\n\tint max_cqe;\n\tint max_mr;\n\tint max_pd;\n\tint max_qp_rd_atom;\n\tint max_ee_rd_atom;\n\tint max_res_rd_atom;\n\tint max_qp_init_rd_atom;\n\tint max_ee_init_rd_atom;\n\tenum ib_atomic_cap atomic_cap;\n\tenum ib_atomic_cap masked_atomic_cap;\n\tint max_ee;\n\tint max_rdd;\n\tint max_mw;\n\tint max_raw_ipv6_qp;\n\tint max_raw_ethy_qp;\n\tint max_mcast_grp;\n\tint max_mcast_qp_attach;\n\tint max_total_mcast_qp_attach;\n\tint max_ah;\n\tint max_srq;\n\tint max_srq_wr;\n\tint max_srq_sge;\n\tunsigned int max_fast_reg_page_list_len;\n\tunsigned int max_pi_fast_reg_page_list_len;\n\tu16 max_pkeys;\n\tu8 local_ca_ack_delay;\n\tint sig_prot_cap;\n\tint sig_guard_cap;\n\tstruct ib_odp_caps odp_caps;\n\tuint64_t timestamp_mask;\n\tuint64_t hca_core_clock;\n\tstruct ib_rss_caps rss_caps;\n\tu32 max_wq_type_rq;\n\tu32 raw_packet_caps;\n\tstruct ib_tm_caps tm_caps;\n\tstruct ib_cq_caps cq_caps;\n\tu64 max_dm_size;\n\tu32 max_sgl_rd;\n};\n\nstruct hw_stats_device_data;\n\nstruct rdma_restrack_root;\n\nstruct uapi_definition;\n\nstruct ib_port_data;\n\nstruct rdma_link_ops;\n\nstruct ib_device {\n\tstruct device *dma_device;\n\tstruct ib_device_ops ops;\n\tchar name[64];\n\tstruct callback_head callback_head;\n\tstruct list_head event_handler_list;\n\tstruct rw_semaphore event_handler_rwsem;\n\tspinlock_t qp_open_list_lock;\n\tstruct rw_semaphore client_data_rwsem;\n\tstruct xarray client_data;\n\tstruct mutex unregistration_lock;\n\trwlock_t cache_lock;\n\tstruct ib_port_data *port_data;\n\tint num_comp_vectors;\n\tunion {\n\t\tstruct device dev;\n\t\tstruct ib_core_device coredev;\n\t};\n\tconst struct attribute_group *groups[4];\n\tu8 hw_stats_attr_index;\n\tu64 uverbs_cmd_mask;\n\tchar node_desc[64];\n\t__be64 node_guid;\n\tu32 local_dma_lkey;\n\tu16 is_switch: 1;\n\tu16 kverbs_provider: 1;\n\tu16 use_cq_dim: 1;\n\tu8 node_type;\n\tu32 phys_port_cnt;\n\tstruct ib_device_attr attrs;\n\tstruct hw_stats_device_data *hw_stats_data;\n\tu32 index;\n\tspinlock_t cq_pools_lock;\n\tstruct list_head cq_pools[3];\n\tstruct rdma_restrack_root *res;\n\tconst struct uapi_definition *driver_def;\n\trefcount_t refcount;\n\tstruct completion unreg_completion;\n\tstruct work_struct unregistration_work;\n\tconst struct rdma_link_ops *link_ops;\n\tstruct mutex compat_devs_mutex;\n\tstruct xarray compat_devs;\n\tchar iw_ifname[16];\n\tu32 iw_driver_flags;\n\tu32 lag_flags;\n\tstruct mutex subdev_lock;\n\tstruct list_head subdev_list_head;\n\tenum rdma_nl_dev_type type;\n\tstruct ib_device *parent;\n\tstruct list_head subdev_list;\n\tenum rdma_nl_name_assign_type name_assign_type;\n};\n\nstruct ib_device_modify {\n\tu64 sys_image_guid;\n\tchar node_desc[64];\n};\n\nstruct ib_dm {\n\tstruct ib_device *device;\n\tu32 length;\n\tu32 flags;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n};\n\nstruct ib_dm_alloc_attr {\n\tu64 length;\n\tu32 alignment;\n\tu32 flags;\n};\n\nstruct ib_dm_mr_attr {\n\tu64 length;\n\tu64 offset;\n\tu32 access_flags;\n};\n\nstruct ib_dmah {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tstruct rdma_restrack_entry res;\n\tu32 cpu_id;\n\tenum tph_mem_type mem_type;\n\tatomic_t usecnt;\n\tu8 ph;\n\tu8 valid_fields;\n};\n\nstruct ib_event {\n\tstruct ib_device *device;\n\tunion {\n\t\tstruct ib_cq *cq;\n\t\tstruct ib_qp *qp;\n\t\tstruct ib_srq *srq;\n\t\tstruct ib_wq *wq;\n\t\tu32 port_num;\n\t} element;\n\tenum ib_event_type event;\n};\n\nstruct ib_flow {\n\tstruct ib_qp *qp;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n};\n\nstruct ib_flow_action {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tenum ib_flow_action_type type;\n\tatomic_t usecnt;\n};\n\nstruct ib_flow_eth_filter {\n\tu8 dst_mac[6];\n\tu8 src_mac[6];\n\t__be16 ether_type;\n\t__be16 vlan_tag;\n};\n\nstruct ib_flow_spec_eth {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_eth_filter val;\n\tstruct ib_flow_eth_filter mask;\n};\n\nstruct ib_flow_ib_filter {\n\t__be16 dlid;\n\t__u8 sl;\n};\n\nstruct ib_flow_spec_ib {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ib_filter val;\n\tstruct ib_flow_ib_filter mask;\n};\n\nstruct ib_flow_ipv4_filter {\n\t__be32 src_ip;\n\t__be32 dst_ip;\n\tu8 proto;\n\tu8 tos;\n\tu8 ttl;\n\tu8 flags;\n};\n\nstruct ib_flow_spec_ipv4 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv4_filter val;\n\tstruct ib_flow_ipv4_filter mask;\n};\n\nstruct ib_flow_tcp_udp_filter {\n\t__be16 dst_port;\n\t__be16 src_port;\n};\n\nstruct ib_flow_spec_tcp_udp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tcp_udp_filter val;\n\tstruct ib_flow_tcp_udp_filter mask;\n};\n\nstruct ib_flow_ipv6_filter {\n\tu8 src_ip[16];\n\tu8 dst_ip[16];\n\t__be32 flow_label;\n\tu8 next_hdr;\n\tu8 traffic_class;\n\tu8 hop_limit;\n} __attribute__((packed));\n\nstruct ib_flow_spec_ipv6 {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_ipv6_filter val;\n\tstruct ib_flow_ipv6_filter mask;\n};\n\nstruct ib_flow_tunnel_filter {\n\t__be32 tunnel_id;\n};\n\nstruct ib_flow_spec_tunnel {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_tunnel_filter val;\n\tstruct ib_flow_tunnel_filter mask;\n};\n\nstruct ib_flow_esp_filter {\n\t__be32 spi;\n\t__be32 seq;\n};\n\nstruct ib_flow_spec_esp {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_esp_filter val;\n\tstruct ib_flow_esp_filter mask;\n};\n\nstruct ib_flow_gre_filter {\n\t__be16 c_ks_res0_ver;\n\t__be16 protocol;\n\t__be32 key;\n};\n\nstruct ib_flow_spec_gre {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_gre_filter val;\n\tstruct ib_flow_gre_filter mask;\n};\n\nstruct ib_flow_mpls_filter {\n\t__be32 tag;\n};\n\nstruct ib_flow_spec_mpls {\n\tu32 type;\n\tu16 size;\n\tstruct ib_flow_mpls_filter val;\n\tstruct ib_flow_mpls_filter mask;\n};\n\nstruct ib_flow_spec_action_tag {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tu32 tag_id;\n};\n\nstruct ib_flow_spec_action_drop {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n};\n\nstruct ib_flow_spec_action_handle {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_flow_action *act;\n};\n\nstruct ib_flow_spec_action_count {\n\tenum ib_flow_spec_type type;\n\tu16 size;\n\tstruct ib_counters *counters;\n};\n\nunion ib_flow_spec {\n\tstruct {\n\t\tu32 type;\n\t\tu16 size;\n\t};\n\tstruct ib_flow_spec_eth eth;\n\tstruct ib_flow_spec_ib ib;\n\tstruct ib_flow_spec_ipv4 ipv4;\n\tstruct ib_flow_spec_tcp_udp tcp_udp;\n\tstruct ib_flow_spec_ipv6 ipv6;\n\tstruct ib_flow_spec_tunnel tunnel;\n\tstruct ib_flow_spec_esp esp;\n\tstruct ib_flow_spec_gre gre;\n\tstruct ib_flow_spec_mpls mpls;\n\tstruct ib_flow_spec_action_tag flow_tag;\n\tstruct ib_flow_spec_action_drop drop;\n\tstruct ib_flow_spec_action_handle action;\n\tstruct ib_flow_spec_action_count flow_count;\n};\n\nstruct ib_flow_attr {\n\tenum ib_flow_attr_type type;\n\tu16 size;\n\tu16 priority;\n\tu32 flags;\n\tu8 num_of_specs;\n\tu32 port;\n\tunion ib_flow_spec flows[0];\n};\n\nunion ib_gid {\n\tu8 raw[16];\n\tstruct {\n\t\t__be64 subnet_prefix;\n\t\t__be64 interface_id;\n\t} global;\n};\n\nstruct ib_gid_attr {\n\tstruct net_device *ndev;\n\tstruct ib_device *device;\n\tunion ib_gid gid;\n\tenum ib_gid_type gid_type;\n\tu16 index;\n\tu32 port_num;\n};\n\nstruct ib_global_route {\n\tconst struct ib_gid_attr *sgid_attr;\n\tunion ib_gid dgid;\n\tu32 flow_label;\n\tu8 sgid_index;\n\tu8 hop_limit;\n\tu8 traffic_class;\n};\n\nstruct ib_grh {\n\t__be32 version_tclass_flow;\n\t__be16 paylen;\n\tu8 next_hdr;\n\tu8 hop_limit;\n\tunion ib_gid sgid;\n\tunion ib_gid dgid;\n};\n\nstruct ib_sig_attrs;\n\nstruct ib_mr {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tu32 lkey;\n\tu32 rkey;\n\tu64 iova;\n\tu64 length;\n\tunsigned int page_size;\n\tenum ib_mr_type type;\n\tbool need_inval;\n\tunion {\n\t\tstruct ib_uobject *uobject;\n\t\tstruct list_head qp_entry;\n\t};\n\tstruct ib_dm *dm;\n\tstruct ib_sig_attrs *sig_attrs;\n\tstruct ib_dmah *dmah;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_sig_err {\n\tenum ib_sig_err_type err_type;\n\tu32 expected;\n\tu32 actual;\n\tu64 sig_err_offset;\n\tu32 key;\n};\n\nstruct ib_mr_status {\n\tu32 fail_status;\n\tstruct ib_sig_err sig_err;\n};\n\nstruct ib_mw {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_uobject *uobject;\n\tu32 rkey;\n\tenum ib_mw_type type;\n};\n\nstruct ib_pd {\n\tu32 local_dma_lkey;\n\tu32 flags;\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 unsafe_global_rkey;\n\tstruct ib_mr *__internal_mr;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_port_attr {\n\tu64 subnet_prefix;\n\tenum ib_port_state state;\n\tenum ib_mtu max_mtu;\n\tenum ib_mtu active_mtu;\n\tu32 phys_mtu;\n\tint gid_tbl_len;\n\tunsigned int ip_gids: 1;\n\tu32 port_cap_flags;\n\tu32 max_msg_sz;\n\tu32 bad_pkey_cntr;\n\tu32 qkey_viol_cntr;\n\tu16 pkey_tbl_len;\n\tu32 sm_lid;\n\tu32 lid;\n\tu8 lmc;\n\tu8 max_vl_num;\n\tu8 sm_sl;\n\tu8 subnet_timeout;\n\tu8 init_type_reply;\n\tu8 active_width;\n\tu16 active_speed;\n\tu8 phys_state;\n\tu16 port_cap_flags2;\n};\n\nstruct ib_pkey_cache;\n\nstruct ib_gid_table;\n\nstruct ib_port_cache {\n\tu64 subnet_prefix;\n\tstruct ib_pkey_cache *pkey;\n\tstruct ib_gid_table *gid;\n\tu8 lmc;\n\tenum ib_port_state port_state;\n\tenum ib_port_state last_port_state;\n};\n\nstruct ib_port_immutable {\n\tint pkey_tbl_len;\n\tint gid_tbl_len;\n\tu32 core_cap_flags;\n\tu32 max_mad_size;\n};\n\nstruct rdma_counter_mode {\n\tenum rdma_nl_counter_mode mode;\n\tenum rdma_nl_counter_mask mask;\n\tstruct auto_mode_param param;\n\tbool bind_opcnt;\n};\n\nstruct rdma_port_counter {\n\tstruct rdma_counter_mode mode;\n\tstruct rdma_hw_stats *hstats;\n\tunsigned int num_counters;\n\tstruct mutex lock;\n};\n\nstruct ib_port;\n\nstruct ib_port_data {\n\tstruct ib_device *ib_dev;\n\tstruct ib_port_immutable immutable;\n\tspinlock_t pkey_list_lock;\n\tspinlock_t netdev_lock;\n\tstruct list_head pkey_list;\n\tstruct ib_port_cache cache;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\tstruct hlist_node ndev_hash_link;\n\tstruct rdma_port_counter port_counter;\n\tstruct ib_port *sysfs;\n};\n\nstruct ib_port_modify {\n\tu32 set_port_cap_mask;\n\tu32 clr_port_cap_mask;\n\tu8 init_type;\n};\n\nstruct ib_qp_security;\n\nstruct ib_port_pkey {\n\tenum port_pkey_state state;\n\tu16 pkey_index;\n\tu32 port_num;\n\tstruct list_head qp_list;\n\tstruct list_head to_error_list;\n\tstruct ib_qp_security *sec;\n};\n\nstruct ib_ports_pkeys {\n\tstruct ib_port_pkey main;\n\tstruct ib_port_pkey alt;\n};\n\nstruct ib_uqp_object;\n\nstruct ib_qp {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tspinlock_t mr_lock;\n\tint mrs_used;\n\tstruct list_head rdma_mrs;\n\tstruct list_head sig_mrs;\n\tstruct ib_srq *srq;\n\tstruct completion srq_completion;\n\tstruct ib_xrcd *xrcd;\n\tstruct list_head xrcd_list;\n\tatomic_t usecnt;\n\tstruct list_head open_list;\n\tstruct ib_qp *real_qp;\n\tstruct ib_uqp_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid (*registered_event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tconst struct ib_gid_attr *av_sgid_attr;\n\tconst struct ib_gid_attr *alt_path_sgid_attr;\n\tu32 qp_num;\n\tu32 max_write_sge;\n\tu32 max_read_sge;\n\tenum ib_qp_type qp_type;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tstruct ib_qp_security *qp_sec;\n\tu32 port;\n\tbool integrity_en;\n\tstruct rdma_restrack_entry res;\n\tstruct rdma_counter *counter;\n};\n\nstruct ib_qp_cap {\n\tu32 max_send_wr;\n\tu32 max_recv_wr;\n\tu32 max_send_sge;\n\tu32 max_recv_sge;\n\tu32 max_inline_data;\n\tu32 max_rdma_ctxs;\n};\n\nstruct roce_ah_attr {\n\tu8 dmac[6];\n};\n\nstruct opa_ah_attr {\n\tu32 dlid;\n\tu8 src_path_bits;\n\tbool make_grd;\n};\n\nstruct rdma_ah_attr {\n\tstruct ib_global_route grh;\n\tu8 sl;\n\tu8 static_rate;\n\tu32 port_num;\n\tu8 ah_flags;\n\tenum rdma_ah_attr_type type;\n\tunion {\n\t\tstruct ib_ah_attr ib;\n\t\tstruct roce_ah_attr roce;\n\t\tstruct opa_ah_attr opa;\n\t};\n};\n\nstruct ib_qp_attr {\n\tenum ib_qp_state qp_state;\n\tenum ib_qp_state cur_qp_state;\n\tenum ib_mtu path_mtu;\n\tenum ib_mig_state path_mig_state;\n\tu32 qkey;\n\tu32 rq_psn;\n\tu32 sq_psn;\n\tu32 dest_qp_num;\n\tint qp_access_flags;\n\tstruct ib_qp_cap cap;\n\tstruct rdma_ah_attr ah_attr;\n\tstruct rdma_ah_attr alt_ah_attr;\n\tu16 pkey_index;\n\tu16 alt_pkey_index;\n\tu8 en_sqd_async_notify;\n\tu8 sq_draining;\n\tu8 max_rd_atomic;\n\tu8 max_dest_rd_atomic;\n\tu8 min_rnr_timer;\n\tu32 port_num;\n\tu8 timeout;\n\tu8 retry_cnt;\n\tu8 rnr_retry;\n\tu32 alt_port_num;\n\tu8 alt_timeout;\n\tu32 rate_limit;\n\tstruct net_device *xmit_slave;\n};\n\nstruct ib_qp_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *qp_context;\n\tstruct ib_cq *send_cq;\n\tstruct ib_cq *recv_cq;\n\tstruct ib_srq *srq;\n\tstruct ib_xrcd *xrcd;\n\tstruct ib_qp_cap cap;\n\tenum ib_sig_type sq_sig_type;\n\tenum ib_qp_type qp_type;\n\tu32 create_flags;\n\tu32 port_num;\n\tstruct ib_rwq_ind_table *rwq_ind_tbl;\n\tu32 source_qpn;\n};\n\nstruct ib_qp_security {\n\tstruct ib_qp *qp;\n\tstruct ib_device *dev;\n\tstruct mutex mutex;\n\tstruct ib_ports_pkeys *ports_pkeys;\n\tstruct list_head shared_qp_list;\n\tvoid *security;\n\tbool destroying;\n\tatomic_t error_list_count;\n\tstruct completion error_complete;\n\tint error_comps_pending;\n};\n\nstruct ib_rdmacg_object {};\n\nstruct ib_recv_wr {\n\tstruct ib_recv_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n};\n\nstruct ib_rwq_ind_table {\n\tstruct ib_device *device;\n\tstruct ib_uobject *uobject;\n\tatomic_t usecnt;\n\tu32 ind_tbl_num;\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_rwq_ind_table_init_attr {\n\tu32 log_ind_tbl_size;\n\tstruct ib_wq **ind_tbl;\n};\n\nstruct ib_send_wr {\n\tstruct ib_send_wr *next;\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tstruct ib_sge *sg_list;\n\tint num_sge;\n\tenum ib_wr_opcode opcode;\n\tint send_flags;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n};\n\nstruct ib_sge {\n\tu64 addr;\n\tu32 length;\n\tu32 lkey;\n};\n\nstruct ib_t10_dif_domain {\n\tenum ib_t10_dif_bg_type bg_type;\n\tu16 pi_interval;\n\tu16 bg;\n\tu16 app_tag;\n\tu32 ref_tag;\n\tbool ref_remap;\n\tbool app_escape;\n\tbool ref_escape;\n\tu16 apptag_check_mask;\n};\n\nstruct ib_sig_domain {\n\tenum ib_signature_type sig_type;\n\tunion {\n\t\tstruct ib_t10_dif_domain dif;\n\t} sig;\n};\n\nstruct ib_sig_attrs {\n\tu8 check_mask;\n\tstruct ib_sig_domain mem;\n\tstruct ib_sig_domain wire;\n\tint meta_length;\n};\n\nstruct ib_usrq_object;\n\nstruct ib_srq {\n\tstruct ib_device *device;\n\tstruct ib_pd *pd;\n\tstruct ib_usrq_object *uobject;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tenum ib_srq_type srq_type;\n\tatomic_t usecnt;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t\tu32 srq_num;\n\t\t\t} xrc;\n\t\t};\n\t} ext;\n\tstruct rdma_restrack_entry res;\n};\n\nstruct ib_srq_attr {\n\tu32 max_wr;\n\tu32 max_sge;\n\tu32 srq_limit;\n};\n\nstruct ib_srq_init_attr {\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tvoid *srq_context;\n\tstruct ib_srq_attr attr;\n\tenum ib_srq_type srq_type;\n\tstruct {\n\t\tstruct ib_cq *cq;\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tstruct ib_xrcd *xrcd;\n\t\t\t} xrc;\n\t\t\tstruct {\n\t\t\t\tu32 max_num_tags;\n\t\t\t} tag_matching;\n\t\t};\n\t} ext;\n};\n\nstruct ib_ucontext {\n\tstruct ib_device *device;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_rdmacg_object cg_obj;\n\tu64 enabled_caps;\n\tstruct rdma_restrack_entry res;\n\tstruct xarray mmap_xa;\n};\n\nstruct ib_udata {\n\tconst void *inbuf;\n\tvoid *outbuf;\n\tsize_t inlen;\n\tsize_t outlen;\n};\n\nstruct uverbs_api_object;\n\nstruct ib_uobject {\n\tu64 user_handle;\n\tstruct ib_uverbs_file *ufile;\n\tstruct ib_ucontext *context;\n\tvoid *object;\n\tstruct list_head list;\n\tstruct ib_rdmacg_object cg_obj;\n\tint id;\n\tstruct kref ref;\n\tatomic_t usecnt;\n\tstruct callback_head rcu;\n\tconst struct uverbs_api_object *uapi_object;\n};\n\nstruct ib_wc {\n\tunion {\n\t\tu64 wr_id;\n\t\tstruct ib_cqe *wr_cqe;\n\t};\n\tenum ib_wc_status status;\n\tenum ib_wc_opcode opcode;\n\tu32 vendor_err;\n\tu32 byte_len;\n\tstruct ib_qp *qp;\n\tunion {\n\t\t__be32 imm_data;\n\t\tu32 invalidate_rkey;\n\t} ex;\n\tu32 src_qp;\n\tu32 slid;\n\tint wc_flags;\n\tu16 pkey_index;\n\tu8 sl;\n\tu8 dlid_path_bits;\n\tu32 port_num;\n\tu8 smac[6];\n\tu16 vlan_id;\n\tu8 network_hdr_type;\n};\n\nstruct ib_uwq_object;\n\nstruct ib_wq {\n\tstruct ib_device *device;\n\tstruct ib_uwq_object *uobject;\n\tvoid *wq_context;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tstruct ib_pd *pd;\n\tstruct ib_cq *cq;\n\tu32 wq_num;\n\tenum ib_wq_state state;\n\tenum ib_wq_type wq_type;\n\tatomic_t usecnt;\n};\n\nstruct ib_wq_attr {\n\tenum ib_wq_state wq_state;\n\tenum ib_wq_state curr_wq_state;\n\tu32 flags;\n\tu32 flags_mask;\n};\n\nstruct ib_wq_init_attr {\n\tvoid *wq_context;\n\tenum ib_wq_type wq_type;\n\tu32 max_wr;\n\tu32 max_sge;\n\tstruct ib_cq *cq;\n\tvoid (*event_handler)(struct ib_event *, void *);\n\tu32 create_flags;\n};\n\nstruct ib_xrcd {\n\tstruct ib_device *device;\n\tatomic_t usecnt;\n\tstruct inode *inode;\n\tstruct rw_semaphore tgt_qps_rwsem;\n\tstruct xarray tgt_qps;\n};\n\nstruct option_vector1 {\n\tu8 byte1;\n\tu8 arch_versions;\n\tu8 arch_versions3;\n};\n\nstruct option_vector2 {\n\tu8 byte1;\n\t__be16 reserved;\n\t__be32 real_base;\n\t__be32 real_size;\n\t__be32 virt_base;\n\t__be32 virt_size;\n\t__be32 load_base;\n\t__be32 min_rma;\n\t__be32 min_load;\n\tu8 min_rma_percent;\n\tu8 max_pft_size;\n} __attribute__((packed));\n\nstruct option_vector3 {\n\tu8 byte1;\n\tu8 byte2;\n};\n\nstruct option_vector4 {\n\tu8 byte1;\n\tu8 min_vp_cap;\n};\n\nstruct option_vector5 {\n\tu8 byte1;\n\tu8 byte2;\n\tu8 byte3;\n\tu8 cmo;\n\tu8 associativity;\n\tu8 bin_opts;\n\tu8 micro_checkpoint;\n\tu8 reserved0;\n\t__be32 max_cpus;\n\t__be16 papr_level;\n\t__be16 reserved1;\n\tu8 platform_facilities;\n\tu8 reserved2;\n\t__be16 reserved3;\n\tu8 subprocessors;\n\tu8 byte22;\n\tu8 intarch;\n\tu8 mmu;\n\tu8 hash_ext;\n\tu8 radix_ext;\n} __attribute__((packed));\n\nstruct option_vector6 {\n\tu8 reserved;\n\tu8 secondary_pteg;\n\tu8 os_name;\n};\n\nstruct option_vector7 {\n\tu8 os_id[256];\n};\n\nstruct ibm_arch_vec {\n\tstruct {\n\t\t__be32 mask;\n\t\t__be32 val;\n\t} pvrs[16];\n\tu8 num_vectors;\n\tu8 vec1_len;\n\tstruct option_vector1 vec1;\n\tu8 vec2_len;\n\tstruct option_vector2 vec2;\n\tu8 vec3_len;\n\tstruct option_vector3 vec3;\n\tu8 vec4_len;\n\tstruct option_vector4 vec4;\n\tu8 vec5_len;\n\tstruct option_vector5 vec5;\n\tu8 vec6_len;\n\tstruct option_vector6 vec6;\n\tu8 vec7_len;\n\tstruct option_vector7 vec7;\n} __attribute__((packed));\n\nstruct ibm_feature {\n\tlong unsigned int cpu_features;\n\tlong unsigned int mmu_features;\n\tunsigned int cpu_user_ftrs;\n\tunsigned int cpu_user_ftrs2;\n\tunsigned char pabyte;\n\tunsigned char pabit;\n\tunsigned char clear;\n};\n\nstruct ibm_nx842_counters {\n\tatomic64_t comp_complete;\n\tatomic64_t comp_failed;\n\tatomic64_t decomp_complete;\n\tatomic64_t decomp_failed;\n\tatomic64_t swdecomp;\n\tatomic64_t comp_times[32];\n\tatomic64_t decomp_times[32];\n};\n\nstruct rtas_work_area;\n\nstruct ibm_platform_dump_params {\n\tstruct rtas_work_area *work_area;\n\tu32 buf_length;\n\tu32 dump_tag_hi;\n\tu32 dump_tag_lo;\n\tu32 sequence_hi;\n\tu32 sequence_lo;\n\tu32 bytes_ret_hi;\n\tu32 bytes_ret_lo;\n\ts32 status;\n\tstruct list_head list;\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tbool use_callback;\n\tunion {\n\t\tvoid (*func)(long unsigned int);\n\t\tvoid (*callback)(struct tasklet_struct *);\n\t};\n\tlong unsigned int data;\n};\n\nstruct mad_adapter_info_data {\n\tchar srp_version[8];\n\tchar partition_name[96];\n\t__be32 partition_number;\n\t__be32 mad_version;\n\t__be32 os_type;\n\t__be32 port_max_txu[8];\n};\n\nstruct ibmvscsi_host_data {\n\tstruct list_head host_list;\n\tatomic_t request_limit;\n\tint client_migrated;\n\tenum ibmvscsi_host_action action;\n\tstruct device *dev;\n\tstruct event_pool pool;\n\tstruct crq_queue queue;\n\tstruct tasklet_struct srp_task;\n\tstruct list_head sent;\n\tstruct Scsi_Host *host;\n\tstruct task_struct *work_thread;\n\twait_queue_head_t work_wait_q;\n\tstruct mad_adapter_info_data madapter_info;\n\tstruct capabilities caps;\n\tdma_addr_t caps_addr;\n\tdma_addr_t adapter_info_addr;\n};\n\nstruct ibmvtpm_crq {\n\tu8 valid;\n\tu8 msg;\n\t__be16 len;\n\t__be32 data;\n\t__be64 reserved;\n};\n\nstruct ibmvtpm_crq_queue {\n\tstruct ibmvtpm_crq *crq_addr;\n\tu32 index;\n\tu32 num_entry;\n\twait_queue_head_t wq;\n};\n\nstruct vio_dev;\n\nstruct ibmvtpm_dev {\n\tstruct device *dev;\n\tstruct vio_dev *vdev;\n\tstruct ibmvtpm_crq_queue crq_queue;\n\tdma_addr_t crq_dma_handle;\n\tu32 rtce_size;\n\tvoid *rtce_buf;\n\tdma_addr_t rtce_dma_handle;\n\tspinlock_t rtce_lock;\n\twait_queue_head_t wq;\n\tu16 res_len;\n\tu32 vtpm_version;\n\tu8 tpm_processing_cmd;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct ich8_pr {\n\tu32 base: 13;\n\tu32 reserved1: 2;\n\tu32 rpe: 1;\n\tu32 limit: 13;\n\tu32 reserved2: 2;\n\tu32 wpe: 1;\n};\n\nunion ich8_flash_protected_range {\n\tstruct ich8_pr range;\n\tu32 regval;\n};\n\nstruct ich8_hsflctl {\n\tu16 flcgo: 1;\n\tu16 flcycle: 2;\n\tu16 reserved: 5;\n\tu16 fldbcount: 2;\n\tu16 flockdn: 6;\n};\n\nstruct ich8_hsfsts {\n\tu16 flcdone: 1;\n\tu16 flcerr: 1;\n\tu16 dael: 1;\n\tu16 berasesz: 2;\n\tu16 flcinprog: 1;\n\tu16 reserved1: 2;\n\tu16 reserved2: 6;\n\tu16 fldesvalid: 1;\n\tu16 flockdn: 1;\n};\n\nunion ich8_hws_flash_ctrl {\n\tstruct ich8_hsflctl hsf_ctrl;\n\tu16 regval;\n};\n\nunion ich8_hws_flash_status {\n\tstruct ich8_hsfsts hsf_status;\n\tu16 regval;\n};\n\nstruct icmp6_err {\n\tint err;\n\tint fatal;\n};\n\nstruct icmp6_ext_iio_addr6_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\tstruct in6_addr addr6;\n};\n\nstruct icmp6_filter {\n\t__u32 data[8];\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_rcu replyopts;\n};\n\nstruct icmp_control {\n\tenum skb_drop_reason (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct icmp_ext_echo_ctype3_hdr {\n\t__be16 afi;\n\t__u8 addrlen;\n\t__u8 reserved;\n};\n\nstruct icmp_extobj_hdr {\n\t__be16 length;\n\t__u8 class_num;\n\t__u8 class_type;\n};\n\nstruct icmp_ext_echo_iio {\n\tstruct icmp_extobj_hdr extobj_hdr;\n\tunion {\n\t\tchar name[16];\n\t\t__be32 ifindex;\n\t\tstruct {\n\t\t\tstruct icmp_ext_echo_ctype3_hdr ctype3_hdr;\n\t\t\tunion {\n\t\t\t\t__be32 ipv4_addr;\n\t\t\t\tstruct in6_addr ipv6_addr;\n\t\t\t} ip_addr;\n\t\t} addr;\n\t} ident;\n};\n\nstruct icmp_ext_hdr {\n\t__u8 reserved1: 4;\n\t__u8 version: 4;\n\t__u8 reserved2;\n\t__sum16 checksum;\n};\n\nstruct icmp_ext_iio_addr4_subobj {\n\t__be16 afi;\n\t__be16 reserved;\n\t__be32 addr4;\n};\n\nstruct icmp_ext_iio_name_subobj {\n\tu8 len;\n\tchar name[16];\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[30];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[7];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[7];\n};\n\nstruct icmpv6_msg {\n\tstruct sk_buff *skb;\n\tint offset;\n\tuint8_t type;\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct icp_ipl {\n\tunion {\n\t\tu32 word;\n\t\tu8 bytes[4];\n\t} xirr_poll;\n\tunion {\n\t\tu32 word;\n\t\tu8 bytes[4];\n\t} xirr;\n\tu32 dummy;\n\tunion {\n\t\tu32 word;\n\t\tu8 bytes[4];\n\t} qirr;\n\tu32 link_a;\n\tu32 link_b;\n\tu32 link_c;\n};\n\nstruct irq_data;\n\nstruct icp_ops {\n\tunsigned int (*get_irq)(void);\n\tvoid (*eoi)(struct irq_data *);\n\tvoid (*set_priority)(unsigned char);\n\tvoid (*teardown_cpu)(void);\n\tvoid (*flush_ipi)(void);\n\tvoid (*cause_ipi)(int);\n\tirq_handler_t ipi_action;\n};\n\nstruct irq_chip;\n\nstruct ics {\n\tstruct list_head link;\n\tint (*check)(struct ics *, unsigned int);\n\tvoid (*mask_unknown)(struct ics *, long unsigned int);\n\tlong int (*get_server)(struct ics *, long unsigned int);\n\tint (*host_match)(struct ics *, struct device_node *);\n\tstruct irq_chip *chip;\n\tchar data[0];\n};\n\nstruct ics_irq_state {\n\tu32 number;\n\tu32 server;\n\tu32 pq_state;\n\tu8 priority;\n\tu8 saved_priority;\n\tu8 resend;\n\tu8 masked_pending;\n\tu8 lsi;\n\tu8 exists;\n\tint intr_cpu;\n\tu32 host_irq;\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[16];\n};\n\nstruct idempotent {\n\tconst void *cookie;\n\tstruct hlist_node entry;\n\tstruct completion complete;\n\tint ret;\n};\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n};\n\nstruct idmap_legacy_upcalldata;\n\nstruct idmap {\n\tstruct rpc_pipe_dir_object idmap_pdo;\n\tstruct rpc_pipe *idmap_pipe;\n\tstruct idmap_legacy_upcalldata *idmap_upcall_data;\n\tstruct mutex idmap_mutex;\n\tstruct user_namespace *user_ns;\n};\n\nstruct idmap_key {\n\tbool map_up;\n\tu32 id;\n\tu32 count;\n};\n\nstruct idmap_msg {\n\t__u8 im_type;\n\t__u8 im_conv;\n\tchar im_name[128];\n\t__u32 im_id;\n\t__u8 im_status;\n};\n\nstruct idmap_legacy_upcalldata {\n\tstruct rpc_pipe_msg pipe_msg;\n\tstruct idmap_msg idmap_msg;\n\tstruct key *authkey;\n\tstruct idmap *idmap;\n};\n\nstruct if6_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tint offset;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nstruct ifa6_config {\n\tconst struct in6_addr *pfx;\n\tunsigned int plen;\n\tu8 ifa_proto;\n\tconst struct in6_addr *peer_pfx;\n\tu32 rt_priority;\n\tu32 ifa_flags;\n\tu32 preferred_lft;\n\tu32 valid_lft;\n\tu16 scope;\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifaddrlblmsg {\n\t__u8 ifal_family;\n\t__u8 __ifal_reserved;\n\t__u8 ifal_prefixlen;\n\t__u8 ifal_flags;\n\t__u32 ifal_index;\n\t__u32 ifal_seq;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\nstruct ifla_cacheinfo {\n\t__u32 max_reasm_len;\n\t__u32 tstamp;\n\t__u32 reachable_time;\n\t__u32 retrans_time;\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\t__u64 guid;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct inet6_dev;\n\nstruct ip6_sf_list;\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct delayed_work mca_work;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct igmp6_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct igmp6_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *im;\n};\n\nstruct in_device;\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct ip_mc_list;\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 qrv: 3;\n\t__u8 suppress: 1;\n\t__u8 resv: 4;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct ima_algo_desc {\n\tstruct crypto_shash *tfm;\n\tenum hash_algo algo;\n};\n\nstruct ima_digest_data_hdr {\n\tu8 algo;\n\tu8 length;\n\tunion {\n\t\tstruct {\n\t\t\tu8 unused;\n\t\t\tu8 type;\n\t\t} sha1;\n\t\tstruct {\n\t\t\tu8 type;\n\t\t\tu8 algo;\n\t\t} ng;\n\t\tu8 data[2];\n\t} xattr;\n};\n\nstruct ima_digest_data {\n\tunion {\n\t\tstruct {\n\t\t\tu8 algo;\n\t\t\tu8 length;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tu8 unused;\n\t\t\t\t\tu8 type;\n\t\t\t\t} sha1;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 type;\n\t\t\t\t\tu8 algo;\n\t\t\t\t} ng;\n\t\t\t\tu8 data[2];\n\t\t\t} xattr;\n\t\t};\n\t\tstruct ima_digest_data_hdr hdr;\n\t};\n\tu8 digest[0];\n};\n\nstruct ima_iint_cache;\n\nstruct modsig;\n\nstruct ima_event_data {\n\tstruct ima_iint_cache *iint;\n\tstruct file *file;\n\tconst unsigned char *filename;\n\tstruct evm_ima_xattr_data *xattr_value;\n\tint xattr_len;\n\tconst struct modsig *modsig;\n\tconst char *violation;\n\tconst void *buf;\n\tint buf_len;\n};\n\nstruct ima_field_data {\n\tu8 *data;\n\tu32 len;\n};\n\nstruct ima_file_id {\n\t__u8 hash_type;\n\t__u8 hash_algorithm;\n\t__u8 hash[64];\n};\n\nstruct ima_h_table {\n\tatomic_long_t len;\n\tatomic_long_t violations;\n\tstruct hlist_head queue[1024];\n};\n\nstruct integrity_inode_attributes {\n\tu64 version;\n\tlong unsigned int ino;\n\tdev_t dev;\n};\n\nstruct ima_iint_cache {\n\tstruct mutex mutex;\n\tstruct integrity_inode_attributes real_inode;\n\tlong unsigned int flags;\n\tlong unsigned int measured_pcrs;\n\tlong unsigned int atomic_flags;\n\tenum integrity_status ima_file_status: 4;\n\tenum integrity_status ima_mmap_status: 4;\n\tenum integrity_status ima_bprm_status: 4;\n\tenum integrity_status ima_read_status: 4;\n\tenum integrity_status ima_creds_status: 4;\n\tstruct ima_digest_data *ima_hash;\n};\n\nstruct ima_kexec_hdr {\n\tu16 version;\n\tu16 _reserved0;\n\tu32 _reserved1;\n\tu64 buffer_size;\n\tu64 count;\n};\n\nstruct ima_key_entry {\n\tstruct list_head list;\n\tvoid *payload;\n\tsize_t payload_len;\n\tchar *keyring_name;\n};\n\nstruct ima_max_digest_data {\n\tstruct ima_digest_data_hdr hdr;\n\tu8 digest[64];\n};\n\nstruct ima_template_entry;\n\nstruct ima_queue_entry {\n\tstruct hlist_node hnext;\n\tstruct list_head later;\n\tstruct ima_template_entry *entry;\n};\n\nstruct ima_rule_opt_list;\n\nstruct ima_template_desc;\n\nstruct ima_rule_entry {\n\tstruct list_head list;\n\tint action;\n\tunsigned int flags;\n\tenum ima_hooks func;\n\tint mask;\n\tlong unsigned int fsmagic;\n\tuuid_t fsuuid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t fowner;\n\tkgid_t fgroup;\n\tbool (*uid_op)(kuid_t, kuid_t);\n\tbool (*gid_op)(kgid_t, kgid_t);\n\tbool (*fowner_op)(vfsuid_t, kuid_t);\n\tbool (*fgroup_op)(vfsgid_t, kgid_t);\n\tint pcr;\n\tunsigned int allowed_algos;\n\tstruct {\n\t\tvoid *rule;\n\t\tchar *args_p;\n\t\tint type;\n\t} lsm[6];\n\tchar *fsname;\n\tchar *fs_subtype;\n\tstruct ima_rule_opt_list *keyrings;\n\tstruct ima_rule_opt_list *label;\n\tstruct ima_template_desc *template;\n};\n\nstruct ima_rule_opt_list {\n\tsize_t count;\n\tchar *items[0];\n};\n\nstruct ima_template_field;\n\nstruct ima_template_desc {\n\tstruct list_head list;\n\tchar *name;\n\tchar *fmt;\n\tint num_fields;\n\tconst struct ima_template_field **fields;\n};\n\nstruct tpm_digest;\n\nstruct ima_template_entry {\n\tint pcr;\n\tstruct tpm_digest *digests;\n\tstruct ima_template_desc *template_desc;\n\tu32 template_data_len;\n\tstruct ima_field_data template_data[0];\n};\n\nstruct ima_template_field {\n\tconst char field_id[16];\n\tint (*field_init)(struct ima_event_data *, struct ima_field_data *);\n\tvoid (*field_show)(struct seq_file *, enum ima_show_type, struct ima_field_data *);\n};\n\nstruct image_data_t {\n\tint status;\n\tvoid *data;\n\tuint32_t size;\n};\n\nstruct image_header_t {\n\tuint16_t magic;\n\tuint16_t version;\n\tuint32_t size;\n};\n\nstruct imc_events {\n\tu32 value;\n\tchar *name;\n\tchar *unit;\n\tchar *scale;\n};\n\nstruct imc_mem_info {\n\tu64 *vbase;\n\tu32 id;\n};\n\nstruct perf_cpu_pmu_context;\n\nstruct perf_event_pmu_context;\n\nstruct perf_output_handle;\n\nstruct pmu {\n\tstruct list_head entry;\n\tspinlock_t events_lock;\n\tstruct list_head events;\n\tstruct module *module;\n\tstruct device *dev;\n\tstruct device *parent;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tunsigned int scope;\n\tstruct perf_cpu_pmu_context **cpu_pmu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_pmu_context *, struct task_struct *, bool);\n\tstruct kmem_cache *task_ctx_cache;\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tbool (*filter)(struct pmu *, int);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\nstruct imc_pmu {\n\tstruct pmu pmu;\n\tstruct imc_mem_info *mem_info;\n\tstruct imc_events *events;\n\tconst struct attribute_group *attr_groups[4];\n\tu32 counter_mem_size;\n\tint domain;\n\tbool imc_counter_mmaped;\n};\n\nstruct imc_pmu_ref {\n\tspinlock_t lock;\n\tunsigned int id;\n\tint refc;\n};\n\nstruct in6_flowlabel_req {\n\tstruct in6_addr flr_dst;\n\t__be32 flr_label;\n\t__u8 flr_action;\n\t__u8 flr_share;\n\t__u16 flr_flags;\n\t__u16 flr_expires;\n\t__u16 flr_linger;\n\t__u32 __flr_pad;\n};\n\nstruct in6_ifreq {\n\tstruct in6_addr ifr6_addr;\n\t__u32 ifr6_prefixlen;\n\tint ifr6_ifindex;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\t__u32 rtmsg_type;\n\t__u16 rtmsg_dst_len;\n\t__u16 rtmsg_src_len;\n\t__u32 rtmsg_metric;\n\tlong unsigned int rtmsg_info;\n\t__u32 rtmsg_flags;\n\tint rtmsg_ifindex;\n};\n\nstruct in6_validator_info {\n\tstruct in6_addr i6vi_addr;\n\tstruct inet6_dev *i6vi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[33];\n\tlong unsigned int state[1];\n};\n\nstruct in_ifaddr;\n\nstruct neigh_parms;\n\nstruct in_device {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tu32 mr_maxdelay;\n\tu32 mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node addr_lst;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\tunsigned char ifa_proto;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct indicator_elem {\n\t__be32 token;\n\t__be32 maxindex;\n};\n\nstruct individual_sensor {\n\tunsigned int token;\n\tunsigned int quant;\n};\n\nstruct ipv6_txoptions;\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n\tu8 dontfrag: 1;\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__u8 __cacheline_group_begin__ipv6_devconf_read_txrx[0];\n\t__s32 disable_ipv6;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 forwarding;\n\t__s32 force_forwarding;\n\t__s32 disable_policy;\n\t__s32 proxy_ndp;\n\t__u8 __cacheline_group_end__ipv6_devconf_read_txrx[0];\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_min_advance;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__u32 ra_defrtr_metric;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_min_lft;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\t__s32 accept_untracked_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\t__u32 ioam6_id;\n\t__u32 ioam6_id_wide;\n\t__u8 ioam6_enabled;\n\t__u8 ndisc_evict_nocarrier;\n\t__u8 ra_honor_pio_life;\n\t__u8 ra_honor_pio_pflag;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct ipstats_mib;\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct delayed_work mc_gq_work;\n\tstruct delayed_work mc_ifc_work;\n\tstruct delayed_work mc_dad_work;\n\tstruct delayed_work mc_query_work;\n\tstruct delayed_work mc_report_work;\n\tstruct sk_buff_head mc_query_queue;\n\tstruct sk_buff_head mc_report_queue;\n\tspinlock_t mc_query_lock;\n\tspinlock_t mc_report_lock;\n\tstruct mutex mc_lock;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n\tunsigned int ra_mtu;\n};\n\nstruct inet6_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n\tenum addr_type_t type;\n\tbool force_rt_scope_universe;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head if_list_aux;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tu8 ifa_proto;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\nstruct inet6_skb_parm;\n\nstruct inet6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 frag_max_size;\n\t__u16 srhoff;\n};\n\nunion inet_addr {\n\t__be32 ip;\n\tstruct in6_addr in6;\n};\n\nstruct inet_bind2_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tshort unsigned int addr_type;\n\tstruct in6_addr v6_rcv_saddr;\n\tstruct hlist_node node;\n\tstruct hlist_node bhash_node;\n\tstruct hlist_head owners;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head bhash2;\n\tstruct callback_head rcu;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tu32 priority;\n\t__u16 gso_size;\n\tu32 ts_opt_id;\n\tu64 transmit_time;\n\tu32 mark;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n\tstruct inet6_cork base6;\n};\n\nstruct ipv6_pinfo;\n\nstruct ipv6_fl_socklist;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tlong unsigned int inet_flags;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__be16 inet_sport;\n\tstruct ip_options_rcu *inet_opt;\n\tatomic_t inet_id;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tu32 local_port_range;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu8 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tstruct inet_bind2_bucket *icsk_bind2_hash;\n\tstruct timer_list icsk_delack_timer;\n\tunion {\n\t\tstruct timer_list icsk_keepalive_timer;\n\t\tstruct timer_list mptcp_tout_timer;\n\t};\n\t__u32 icsk_rto;\n\t__u32 icsk_rto_min;\n\tu32 icsk_rto_max;\n\t__u32 icsk_delack_max;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 5;\n\t__u8 icsk_ca_initialized: 1;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 retry;\n\t\t__u32 ato: 8;\n\t\t__u32 lrcv_flowlabel: 20;\n\t\t__u32 dst_quick_ack: 1;\n\t\t__u32 unused: 3;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint search_high;\n\t\tint search_low;\n\t\tu32 probe_size: 31;\n\t\tu32 enabled: 1;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_probes_tstamp;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *, void (*)(struct sock *, const struct sock *));\n\tu16 net_header_len;\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_diag_bc_op {\n\tunsigned char code;\n\tunsigned char yes;\n\tshort unsigned int no;\n};\n\nstruct inet_diag_dump_data {\n\tstruct nlattr *req_nlas[4];\n\tstruct bpf_sk_storage_diag *bpf_stg_diag;\n\tbool mark_needed;\n\tbool cgroup_needed;\n\tbool userlocks_needed;\n};\n\nstruct inet_diag_entry {\n\tconst __be32 *saddr;\n\tconst __be32 *daddr;\n\tu16 sport;\n\tu16 dport;\n\tu16 family;\n\tu16 userlocks;\n\tu32 ifindex;\n\tu32 mark;\n\tu64 cgroup_id;\n};\n\nstruct inet_diag_req_v2;\n\nstruct inet_diag_msg;\n\nstruct inet_diag_handler {\n\tstruct module *owner;\n\tvoid (*dump)(struct sk_buff *, struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tint (*dump_one)(struct netlink_callback *, const struct inet_diag_req_v2 *);\n\tvoid (*idiag_get_info)(struct sock *, struct inet_diag_msg *, void *);\n\tint (*idiag_get_aux)(struct sock *, bool, struct sk_buff *);\n\tint (*destroy)(struct sk_buff *, const struct inet_diag_req_v2 *);\n\t__u16 idiag_type;\n\t__u16 idiag_info_size;\n};\n\nstruct inet_diag_hostcond {\n\t__u8 family;\n\t__u8 prefix_len;\n\tint port;\n\t__be32 addr[0];\n};\n\nstruct inet_diag_markcond {\n\t__u32 mark;\n\t__u32 mask;\n};\n\nstruct inet_diag_meminfo {\n\t__u32 idiag_rmem;\n\t__u32 idiag_wmem;\n\t__u32 idiag_fmem;\n\t__u32 idiag_tmem;\n};\n\nstruct inet_diag_sockid {\n\t__be16 idiag_sport;\n\t__be16 idiag_dport;\n\t__be32 idiag_src[4];\n\t__be32 idiag_dst[4];\n\t__u32 idiag_if;\n\t__u32 idiag_cookie[2];\n};\n\nstruct inet_diag_msg {\n\t__u8 idiag_family;\n\t__u8 idiag_state;\n\t__u8 idiag_timer;\n\t__u8 idiag_retrans;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_expires;\n\t__u32 idiag_rqueue;\n\t__u32 idiag_wqueue;\n\t__u32 idiag_uid;\n\t__u32 idiag_inode;\n};\n\nstruct inet_diag_req {\n\t__u8 idiag_family;\n\t__u8 idiag_src_len;\n\t__u8 idiag_dst_len;\n\t__u8 idiag_ext;\n\tstruct inet_diag_sockid id;\n\t__u32 idiag_states;\n\t__u32 idiag_dbs;\n};\n\nstruct inet_diag_req_v2 {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u8 idiag_ext;\n\t__u8 pad;\n\t__u32 idiag_states;\n\tstruct inet_diag_sockid id;\n};\n\nstruct inet_diag_sockopt {\n\t__u8 recverr: 1;\n\t__u8 is_icsk: 1;\n\t__u8 freebind: 1;\n\t__u8 hdrincl: 1;\n\t__u8 mc_loop: 1;\n\t__u8 transparent: 1;\n\t__u8 mc_all: 1;\n\t__u8 nodefrag: 1;\n\t__u8 bind_address_no_port: 1;\n\t__u8 recverr_rfc4884: 1;\n\t__u8 defer_connect: 1;\n\t__u8 unused: 5;\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct inet_listen_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tstruct kmem_cache *bind2_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash2;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tbool pernet;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head nulls_head;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct proto_ops;\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\nstruct request_sock_ops;\n\nstruct saved_syn;\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 syncookie: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tstruct saved_syn *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n\tu32 timeout;\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct inet_timewait_death_row {\n\trefcount_t tw_refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tunsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_usec_ts: 1;\n\tunsigned int tw_connect_bind: 1;\n\tunsigned int tw_pad: 1;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tu32 tw_entry_stamp;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n\tstruct inet_bind2_bucket *tw_tb2;\n};\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\nstruct mnt_idmap;\n\nstruct kstat;\n\nstruct offset_ctx;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct mnt_idmap *, struct inode *, int);\n\tstruct posix_acl * (*get_inode_acl)(struct inode *, int, bool);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct mnt_idmap *, struct inode *, struct dentry *, const char *);\n\tstruct dentry * (*mkdir)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct mnt_idmap *, struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tint (*getattr)(struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, enum fs_update_time, unsigned int);\n\tvoid (*sync_lazytime)(struct inode *);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct mnt_idmap *, struct inode *, struct file *, umode_t);\n\tstruct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int);\n\tint (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int);\n\tint (*fileattr_set)(struct mnt_idmap *, struct dentry *, struct file_kattr *);\n\tint (*fileattr_get)(struct dentry *, struct file_kattr *);\n\tstruct offset_ctx * (*get_offset_ctx)(struct inode *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inode_security_struct {\n\tstruct inode *inode;\n\tstruct list_head list;\n\tu32 task_sid;\n\tu32 sid;\n\tu16 sclass;\n\tunsigned char initialized;\n\tspinlock_t lock;\n};\n\nstruct inode_switch_wbs_context {\n\tstruct llist_node list;\n\tstruct inode *inodes[0];\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nunion inparam {\n\tstruct floppy_struct g;\n\tstruct format_descr f;\n\tstruct floppy_max_errors max_errors;\n\tstruct floppy_drive_params dp;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_handle;\n\nstruct input_value;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[12];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[1];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[2];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[12];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n\tbool inhibited;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[12];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[1];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[2];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct input_handler;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tunsigned int (*handle_events)(struct input_handle *, struct input_value *, unsigned int);\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tunsigned int (*events)(struct input_handle *, struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool passive_observer;\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nstruct input_seq_state {\n\tshort unsigned int pos;\n\tbool mutex_acquired;\n\tint input_devices_state;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct insn_live_regs {\n\tu16 use;\n\tu16 def;\n\tu16 in;\n\tu16 out;\n};\n\nstruct instance_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_instance *, char *);\n\tssize_t (*store)(struct edac_device_instance *, const char *, size_t);\n};\n\nstruct instance_attribute___2 {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_pci_ctl_info *, char *);\n\tssize_t (*store)(struct edac_pci_ctl_info *, const char *, size_t);\n};\n\nstruct instruction_op {\n\tint type;\n\tint reg;\n\tlong unsigned int val;\n\tlong unsigned int ea;\n\tint update_reg;\n\tint spr;\n\tu32 ccval;\n\tu32 xerval;\n\tu8 element_size;\n\tu8 vsx_flags;\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tstruct device classdev;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\nstruct interrupt_nmi_state {\n\tu8 irq_soft_mask;\n\tu8 irq_happened;\n\tu8 ftrace_enabled;\n\tu64 softe;\n};\n\nstruct interval_tree_node {\n\tstruct rb_node rb;\n\tlong unsigned int start;\n\tlong unsigned int last;\n\tlong unsigned int __subtree_last;\n};\n\nstruct io {\n\tlong unsigned int error_bits;\n\tatomic_t count;\n\tstruct dm_io_client *client;\n\tio_notify_fn callback;\n\tvoid *context;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n\tlong: 64;\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tint iou_flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_alloc_cache {\n\tvoid **entries;\n\tunsigned int nr_cached;\n\tunsigned int max_cached;\n\tunsigned int elem_size;\n\tunsigned int init_clear;\n};\n\nstruct iou_vec {\n\tunion {\n\t\tstruct iovec *iovec;\n\t\tstruct bio_vec *bvec;\n\t};\n\tunsigned int nr;\n};\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t\tstruct {\n\t\t\t__u32 cmd_op;\n\t\t\t__u32 __pad1;\n\t\t};\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t\tstruct {\n\t\t\t__u32 level;\n\t\t\t__u32 optname;\n\t\t};\n\t};\n\t__u32 len;\n\tunion {\n\t\t__u32 rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 poll32_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t\t__u32 rename_flags;\n\t\t__u32 unlink_flags;\n\t\t__u32 hardlink_flags;\n\t\t__u32 xattr_flags;\n\t\t__u32 msg_ring_flags;\n\t\t__u32 uring_cmd_flags;\n\t\t__u32 waitid_flags;\n\t\t__u32 futex_flags;\n\t\t__u32 install_fd_flags;\n\t\t__u32 nop_flags;\n\t\t__u32 pipe_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\t__u16 buf_index;\n\t\t__u16 buf_group;\n\t};\n\t__u16 personality;\n\tunion {\n\t\t__s32 splice_fd_in;\n\t\t__u32 file_index;\n\t\t__u32 zcrx_ifq_idx;\n\t\t__u32 optlen;\n\t\tstruct {\n\t\t\t__u16 addr_len;\n\t\t\t__u16 __pad3[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u8 write_stream;\n\t\t\t__u8 __pad4[3];\n\t\t};\n\t};\n\tunion {\n\t\tstruct {\n\t\t\t__u64 addr3;\n\t\t\t__u64 __pad2[1];\n\t\t};\n\t\tstruct {\n\t\t\t__u64 attr_ptr;\n\t\t\t__u64 attr_type_mask;\n\t\t};\n\t\t__u64 optval;\n\t\t__u8 cmd[0];\n\t};\n};\n\nstruct io_async_cmd {\n\tstruct iou_vec vec;\n\tstruct io_uring_sqe sqes[2];\n};\n\nstruct ubuf_info;\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tint msg_inq;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\tbool msg_get_inq: 1;\n\tunsigned int msg_flags;\n\t__kernel_size_t msg_controllen;\n\tstruct kiocb *msg_iocb;\n\tstruct ubuf_info *msg_ubuf;\n\tint (*sg_from_iter)(struct sk_buff *, struct iov_iter *, size_t);\n};\n\nstruct io_async_msghdr {\n\tstruct iou_vec vec;\n\tunion {\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t};\n\t\tstruct {\n\t\t\tint namelen;\n\t\t\tstruct iovec fast_iov;\n\t\t\t__kernel_size_t controllen;\n\t\t\t__kernel_size_t payloadlen;\n\t\t\tstruct sockaddr *uaddr;\n\t\t\tstruct msghdr msg;\n\t\t\tstruct __kernel_sockaddr_storage addr;\n\t\t} clear;\n\t};\n};\n\nstruct iov_iter_state {\n\tsize_t iov_offset;\n\tsize_t count;\n\tlong unsigned int nr_segs;\n};\n\nstruct wait_page_queue {\n\tstruct folio *folio;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nstruct uio_meta {\n\tuio_meta_flags_t flags;\n\tu16 app_tag;\n\tu64 seed;\n\tstruct iov_iter iter;\n};\n\nstruct io_meta_state {\n\tu32 seed;\n\tstruct iov_iter_state iter_meta;\n};\n\nstruct io_async_rw {\n\tstruct iou_vec vec;\n\tsize_t bytes_done;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tstruct iov_iter iter;\n\t\t\tstruct iov_iter_state iter_state;\n\t\t\tstruct iovec fast_iov;\n\t\t\tunsigned int buf_group;\n\t\t\tunion {\n\t\t\t\tstruct wait_page_queue wpq;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct uio_meta meta;\n\t\t\t\t\tstruct io_meta_state meta_state;\n\t\t\t\t};\n\t\t\t};\n\t\t} clear;\n\t};\n};\n\nstruct io_big_cqe {\n\tu64 extra1;\n\tu64 extra2;\n};\n\nstruct io_bind {\n\tstruct file *file;\n\tint addr_len;\n};\n\nstruct io_bpf_filter {\n\trefcount_t refs;\n\tstruct bpf_prog *prog;\n\tstruct io_bpf_filter *next;\n};\n\nstruct io_bpf_filters {\n\trefcount_t refs;\n\tspinlock_t lock;\n\tstruct io_bpf_filter **filters;\n\tstruct callback_head callback_head;\n};\n\nstruct io_buffer_list;\n\nstruct io_br_sel {\n\tstruct io_buffer_list *buf_list;\n\tunion {\n\t\tvoid *addr;\n\t\tssize_t val;\n\t};\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 bgid;\n};\n\nstruct io_mapped_region {\n\tstruct page **pages;\n\tvoid *ptr;\n\tunsigned int nr_pages;\n\tunsigned int flags;\n};\n\nstruct io_uring_buf_ring;\n\nstruct io_buffer_list {\n\tunion {\n\t\tstruct list_head buf_list;\n\t\tstruct io_uring_buf_ring *buf_ring;\n\t};\n\tint nbufs;\n\t__u16 bgid;\n\t__u16 nr_entries;\n\t__u16 head;\n\t__u16 mask;\n\t__u16 flags;\n\tstruct io_mapped_region region;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tu64 addr;\n\tu32 flags;\n\ts32 fd;\n\tu8 opcode;\n};\n\nstruct io_ring_ctx;\n\nstruct io_cancel_data {\n\tstruct io_ring_ctx *ctx;\n\tu64 data;\n\tstruct file *file;\n\tu8 opcode;\n\tu32 flags;\n\tint seq;\n};\n\nstruct io_wq_work;\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tint fd;\n\tu32 file_slot;\n};\n\nstruct io_cmd_data {\n\tstruct file *file;\n\t__u8 data[56];\n};\n\nstruct io_kiocb;\n\nstruct io_cold_def {\n\tconst char *name;\n\tvoid (*sqe_copy)(struct io_kiocb *);\n\tvoid (*cleanup)(struct io_kiocb *);\n\tvoid (*fail)(struct io_kiocb *);\n};\n\nstruct io_comp_batch {\n\tstruct rq_list req_list;\n\tbool need_ts;\n\tvoid (*complete)(struct io_comp_batch *);\n\tvoid *poll_ctx;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n\tbool in_progress;\n\tbool seen_econnaborted;\n};\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tshort unsigned int ioprio;\n};\n\nstruct io_copy_cache {\n\tstruct page *page;\n\tlong unsigned int offset;\n\tsize_t size;\n};\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct io_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\tunion {\n\t\t__u32 flags;\n\t\tint fd;\n\t};\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 user_addr;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_rings_layout {\n\tsize_t rings_size;\n\tsize_t sq_size;\n\tsize_t sq_array_offset;\n};\n\nstruct io_ctx_config {\n\tstruct io_uring_params p;\n\tstruct io_rings_layout layout;\n\tstruct io_uring_params *uptr;\n};\n\nstruct io_defer_entry {\n\tstruct list_head list;\n\tstruct io_kiocb *req;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n};\n\nstruct io_epoll_wait {\n\tstruct file *file;\n\tint maxevents;\n\tstruct epoll_event *events;\n};\n\nstruct io_err_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct io_ev_fd {\n\tstruct eventfd_ctx *cq_ev_fd;\n\tunsigned int eventfd_async;\n\tunsigned int last_cq_tail;\n\trefcount_t refs;\n\tatomic_t ops;\n\tstruct callback_head rcu;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tu64 offset;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_rsrc_node;\n\nstruct io_rsrc_data {\n\tunsigned int nr;\n\tstruct io_rsrc_node **nodes;\n};\n\nstruct io_file_table {\n\tstruct io_rsrc_data data;\n\tlong unsigned int *bitmap;\n\tunsigned int alloc_hint;\n};\n\nstruct io_fixed_install {\n\tstruct file *file;\n\tunsigned int o_flags;\n};\n\nstruct io_ftrunc {\n\tstruct file *file;\n\tloff_t len;\n};\n\nstruct io_futex {\n\tstruct file *file;\n\tvoid *uaddr;\n\tlong unsigned int futex_val;\n\tlong unsigned int futex_mask;\n\tu32 futex_flags;\n\tunsigned int futex_nr;\n\tbool futexv_unqueued;\n};\n\nstruct io_futex_data {\n\tstruct futex_q q;\n\tstruct io_kiocb *req;\n};\n\nstruct io_futexv_data {\n\tlong unsigned int owned;\n\tstruct futex_vector futexv[0];\n};\n\nstruct io_hash_bucket {\n\tstruct hlist_head list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_hash_table {\n\tstruct io_hash_bucket *hbs;\n\tunsigned int hash_bits;\n};\n\nstruct io_imu_folio_data {\n\tunsigned int nr_pages_head;\n\tunsigned int nr_pages_mid;\n\tunsigned int folio_shift;\n\tunsigned int nr_folios;\n\tlong unsigned int first_folio_page_idx;\n};\n\nstruct io_uring_bpf_ctx;\n\nstruct io_issue_def {\n\tunsigned int needs_file: 1;\n\tunsigned int plug: 1;\n\tunsigned int ioprio: 1;\n\tunsigned int iopoll: 1;\n\tunsigned int buffer_select: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int poll_exclusive: 1;\n\tunsigned int audit_skip: 1;\n\tunsigned int iopoll_queue: 1;\n\tunsigned int vectored: 1;\n\tunsigned int is_128: 1;\n\tshort unsigned int async_size;\n\tshort unsigned int filter_pdu_size;\n\tint (*issue)(struct io_kiocb *, unsigned int);\n\tint (*prep)(struct io_kiocb *, const struct io_uring_sqe *);\n\tvoid (*filter_populate)(struct io_uring_bpf_ctx *, struct io_kiocb *);\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_tw_req;\n\nstruct io_tw_state;\n\ntypedef struct io_tw_state io_tw_token_t;\n\ntypedef void (*io_req_tw_func_t)(struct io_tw_req, io_tw_token_t);\n\nstruct io_task_work {\n\tstruct llist_node node;\n\tio_req_tw_func_t func;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tatomic_t flags;\n\tint cancel_seq;\n};\n\nstruct io_uring_task;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_cmd_data cmd;\n\t};\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tunsigned int nr_tw;\n\tio_req_flags_t flags;\n\tstruct io_cqe cqe;\n\tstruct io_ring_ctx *ctx;\n\tstruct io_uring_task *tctx;\n\tunion {\n\t\tstruct io_buffer *kbuf;\n\t\tstruct io_rsrc_node *buf_node;\n\t};\n\tunion {\n\t\tstruct io_wq_work_node comp_list;\n\t\t__poll_t apoll_events;\n\t};\n\tstruct io_rsrc_node *file_node;\n\tatomic_t refs;\n\tbool cancel_seq_set;\n\tunion {\n\t\tstruct io_task_work io_task_work;\n\t\tu64 iopoll_start;\n\t};\n\tunion {\n\t\tstruct hlist_node hash_node;\n\t\tstruct list_head iopoll_node;\n\t\tstruct callback_head callback_head;\n\t};\n\tstruct async_poll *apoll;\n\tvoid *async_data;\n\tatomic_t poll_refs;\n\tstruct io_kiocb *link;\n\tconst struct cred *creds;\n\tstruct io_wq_work work;\n\tstruct io_big_cqe big_cqe;\n};\n\nstruct io_link {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_listen {\n\tstruct file *file;\n\tint backlog;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tu64 addr;\n\tu64 len;\n\tu32 advice;\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tunsigned int len;\n\tunsigned int nr_bvecs;\n\tunsigned int folio_shift;\n\trefcount_t refs;\n\tlong unsigned int acct_pages;\n\tvoid (*release)(void *);\n\tvoid *priv;\n\tu8 flags;\n\tu8 dir;\n\tstruct bio_vec bvec[0];\n};\n\nstruct io_mkdir {\n\tstruct file *file;\n\tint dfd;\n\tumode_t mode;\n\tstruct delayed_filename filename;\n};\n\nstruct io_msg {\n\tstruct file *file;\n\tstruct file *src_file;\n\tstruct callback_head tw;\n\tu64 user_data;\n\tu32 len;\n\tu32 cmd;\n\tu32 src_fd;\n\tunion {\n\t\tu32 dst_fd;\n\t\tu32 cqe_flags;\n\t};\n\tu32 flags;\n};\n\nstruct io_napi_entry {\n\tunsigned int napi_id;\n\tstruct list_head list;\n\tlong unsigned int timeout;\n\tstruct hlist_node node;\n\tstruct callback_head rcu;\n};\n\nstruct io_nop {\n\tstruct file *file;\n\tint result;\n\tint fd;\n\tunsigned int flags;\n\t__u64 extra1;\n\t__u64 extra2;\n};\n\nstruct ubuf_info_ops;\n\nstruct ubuf_info {\n\tconst struct ubuf_info_ops *ops;\n\trefcount_t refcnt;\n\tu8 flags;\n};\n\nstruct io_notif_data {\n\tstruct file *file;\n\tstruct ubuf_info uarg;\n\tstruct io_notif_data *next;\n\tstruct io_notif_data *head;\n\tunsigned int account_pages;\n\tbool zc_report;\n\tbool zc_used;\n\tbool zc_copied;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tu32 file_slot;\n\tstruct delayed_filename filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n\t__u64 big_cqe[0];\n};\n\nstruct io_overflow_cqe {\n\tstruct list_head list;\n\tstruct io_uring_cqe cqe;\n};\n\nstruct io_pipe {\n\tstruct file *file;\n\tint *fds;\n\tint flags;\n\tint file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint nr_entries;\n\tint error;\n\tbool owning;\n\t__poll_t result_mask;\n};\n\nstruct io_poll_update {\n\tstruct file *file;\n\tu64 old_user_data;\n\tu64 new_user_data;\n\t__poll_t events;\n\tbool update_events;\n\tbool update_user_data;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\t__u64 addr;\n\t__u32 len;\n\t__u32 bgid;\n\t__u32 nbufs;\n\t__u16 bid;\n};\n\nstruct io_uring_query_opcode {\n\t__u32 nr_request_opcodes;\n\t__u32 nr_register_opcodes;\n\t__u64 feature_flags;\n\t__u64 ring_setup_flags;\n\t__u64 enter_flags;\n\t__u64 sqe_flags;\n\t__u32 nr_query_opcodes;\n\t__u32 __pad;\n};\n\nstruct io_uring_query_zcrx {\n\t__u64 register_flags;\n\t__u64 area_flags;\n\t__u32 nr_ctrl_opcodes;\n\t__u32 features;\n\t__u32 rq_hdr_size;\n\t__u32 rq_hdr_alignment;\n\t__u64 __resv2;\n};\n\nstruct io_uring_query_scq {\n\t__u64 hdr_size;\n\t__u64 hdr_alignment;\n};\n\nunion io_query_data {\n\tstruct io_uring_query_opcode opcodes;\n\tstruct io_uring_query_zcrx zcrx;\n\tstruct io_uring_query_scq scq;\n};\n\nstruct io_uring_recvmsg_out {\n\t__u32 namelen;\n\t__u32 controllen;\n\t__u32 payloadlen;\n\t__u32 flags;\n};\n\nstruct io_recvmsg_multishot_hdr {\n\tstruct io_uring_recvmsg_out msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_zcrx_ifq;\n\nstruct io_recvzc {\n\tstruct file *file;\n\tu16 flags;\n\tu32 len;\n\tstruct io_zcrx_ifq *ifq;\n};\n\nstruct io_region {\n\tint offset;\n\tint size;\n};\n\nstruct io_rename {\n\tstruct file *file;\n\tint old_dfd;\n\tint new_dfd;\n\tstruct delayed_filename oldpath;\n\tstruct delayed_filename newpath;\n\tint flags;\n};\n\nstruct io_restriction {\n\tlong unsigned int register_op[1];\n\tlong unsigned int sqe_op[2];\n\tstruct io_bpf_filters *bpf_filters;\n\tbool bpf_filters_cow;\n\tu8 sqe_flags_allowed;\n\tu8 sqe_flags_required;\n\tbool op_registered;\n\tbool reg_registered;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\nstruct io_submit_link {\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *last;\n};\n\nstruct io_submit_state {\n\tstruct io_wq_work_node free_list;\n\tstruct io_wq_work_list compl_reqs;\n\tstruct io_submit_link link;\n\tbool plug_started;\n\tbool need_plug;\n\tbool cq_flush;\n\tshort unsigned int submit_nr;\n\tstruct blk_plug plug;\n};\n\nstruct io_rings;\n\nstruct io_sq_data;\n\nstruct io_wq_hash;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int op_restricted: 1;\n\t\tunsigned int reg_restricted: 1;\n\t\tunsigned int off_timeout_used: 1;\n\t\tunsigned int drain_active: 1;\n\t\tunsigned int has_evfd: 1;\n\t\tunsigned int task_complete: 1;\n\t\tunsigned int lockless_cq: 1;\n\t\tunsigned int syscall_iopoll: 1;\n\t\tunsigned int poll_activated: 1;\n\t\tunsigned int drain_disabled: 1;\n\t\tunsigned int compat: 1;\n\t\tunsigned int iowq_limits_set: 1;\n\t\tstruct task_struct *submitter_task;\n\t\tstruct io_rings *rings;\n\t\tstruct io_bpf_filter **bpf_filters;\n\t\tstruct percpu_ref refs;\n\t\tclockid_t clockid;\n\t\tenum tk_offsets clock_offset;\n\t\tenum task_work_notify_mode notify_method;\n\t\tunsigned int sq_thread_idle;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\tu32 *sq_array;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tatomic_t cancel_seq;\n\t\tbool poll_multi_queue;\n\t\tstruct list_head iopoll_list;\n\t\tstruct io_file_table file_table;\n\t\tstruct io_rsrc_data buf_table;\n\t\tstruct io_alloc_cache node_cache;\n\t\tstruct io_alloc_cache imu_cache;\n\t\tstruct io_submit_state submit_state;\n\t\tstruct xarray io_bl_xa;\n\t\tstruct io_hash_table cancel_table;\n\t\tstruct io_alloc_cache apoll_cache;\n\t\tstruct io_alloc_cache netmsg_cache;\n\t\tstruct io_alloc_cache rw_cache;\n\t\tstruct io_alloc_cache cmd_cache;\n\t\tstruct hlist_head cancelable_uring_cmd;\n\t\tu64 hybrid_poll_time;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct io_uring_cqe *cqe_cached;\n\t\tstruct io_uring_cqe *cqe_sentinel;\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tstruct io_ev_fd *io_ev_fd;\n\t\tvoid *cq_wait_arg;\n\t\tsize_t cq_wait_size;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct llist_head work_llist;\n\t\tstruct llist_head retry_llist;\n\t\tlong unsigned int check_cq;\n\t\tatomic_t cq_wait_nr;\n\t\tatomic_t cq_timeouts;\n\t\tstruct wait_queue_head cq_wait;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\traw_spinlock_t timeout_lock;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head ltimeout_list;\n\t\tunsigned int cq_last_tm_flush;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tspinlock_t completion_lock;\n\tstruct list_head cq_overflow_list;\n\tstruct hlist_head waitid_list;\n\tstruct hlist_head futex_list;\n\tstruct io_alloc_cache futex_cache;\n\tconst struct cred *sq_creds;\n\tstruct io_sq_data *sq_data;\n\tstruct wait_queue_head sqo_sq_wait;\n\tstruct list_head sqd_list;\n\tunsigned int file_alloc_start;\n\tunsigned int file_alloc_end;\n\tstruct wait_queue_head poll_wq;\n\tstruct io_restriction restrictions;\n\tstruct xarray zcrx_ctxs;\n\tu32 pers_next;\n\tstruct xarray personalities;\n\tstruct io_wq_hash *hash_map;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tstruct list_head tctx_list;\n\tstruct mutex tctx_lock;\n\tstruct llist_head fallback_llist;\n\tstruct delayed_work fallback_work;\n\tstruct work_struct exit_work;\n\tstruct completion ref_comp;\n\tu32 iowq_limits[2];\n\tstruct callback_head poll_wq_task_work;\n\tstruct list_head defer_list;\n\tunsigned int nr_drained;\n\tunsigned int nr_req_allocated;\n\tstruct list_head napi_list;\n\tspinlock_t napi_lock;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n\tu8 napi_track_mode;\n\tstruct hlist_head napi_ht[16];\n\tstruct mutex mmap_lock;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n\tstruct io_mapped_region param_region;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_ring_ctx_rings {\n\tstruct io_rings *rings;\n\tstruct io_uring_sqe *sq_sqes;\n\tstruct io_mapped_region sq_region;\n\tstruct io_mapped_region ring_region;\n};\n\nstruct io_uring {\n\tu32 head;\n\tu32 tail;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tatomic_t sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_rsrc_node {\n\tunsigned char type;\n\tint refs;\n\tu64 tag;\n\tunion {\n\t\tlong unsigned int file_ptr;\n\t\tstruct io_mapped_ubuf *buf;\n\t};\n};\n\nstruct io_rsrc_update {\n\tstruct file *file;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu32 len;\n\trwf_t flags;\n};\n\nstruct io_shutdown {\n\tstruct file *file;\n\tint how;\n};\n\nstruct io_socket {\n\tstruct file *file;\n\tint domain;\n\tint type;\n\tint protocol;\n\tint flags;\n\tu32 file_slot;\n\tlong unsigned int nofile;\n};\n\nstruct io_splice {\n\tstruct file *file_out;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tint splice_fd_in;\n\tunsigned int flags;\n\tstruct io_rsrc_node *rsrc_node;\n};\n\nstruct io_sq_data {\n\trefcount_t refs;\n\tatomic_t park_pending;\n\tstruct mutex lock;\n\tstruct list_head ctx_list;\n\tstruct task_struct *thread;\n\tstruct wait_queue_head wait;\n\tunsigned int sq_thread_idle;\n\tint sq_cpu;\n\tpid_t task_pid;\n\tpid_t task_tgid;\n\tu64 work_time;\n\tlong unsigned int state;\n\tstruct completion exited;\n};\n\nstruct io_sq_time {\n\tbool started;\n\tu64 usec;\n};\n\nstruct user_msghdr;\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct compat_msghdr *umsg_compat;\n\t\tstruct user_msghdr *umsg;\n\t\tvoid *buf;\n\t};\n\tint len;\n\tunsigned int done_io;\n\tunsigned int msg_flags;\n\tunsigned int nr_multishot_loops;\n\tu16 flags;\n\tu16 buf_group;\n\tunsigned int mshot_len;\n\tunsigned int mshot_total_len;\n\tvoid *msg_control;\n\tstruct io_kiocb *notif;\n};\n\nstruct statx;\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tstruct delayed_filename filename;\n\tstruct statx *buffer;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_task_cancel {\n\tstruct io_uring_task *tctx;\n\tbool all;\n};\n\nstruct io_tctx_exit {\n\tstruct callback_head task_work;\n\tstruct completion completion;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_tctx_node {\n\tstruct list_head ctx_node;\n\tstruct task_struct *task;\n\tstruct io_ring_ctx *ctx;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu32 off;\n\tu32 target_seq;\n\tu32 repeats;\n\tstruct list_head list;\n\tstruct io_kiocb *head;\n\tstruct io_kiocb *prev;\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n\tu32 flags;\n};\n\nstruct io_timeout_rem {\n\tstruct file *file;\n\tu64 addr;\n\tstruct timespec64 ts;\n\tu32 flags;\n\tbool ltimeout;\n};\n\nstruct io_timespec {\n\t__u64 tv_sec;\n\t__u64 tv_nsec;\n};\n\nstruct io_tlb_area {\n\tlong unsigned int used;\n\tunsigned int index;\n\tspinlock_t lock;\n};\n\nstruct io_tlb_slot;\n\nstruct io_tlb_pool {\n\tphys_addr_t start;\n\tphys_addr_t end;\n\tvoid *vaddr;\n\tlong unsigned int nslabs;\n\tbool late_alloc;\n\tunsigned int nareas;\n\tunsigned int area_nslabs;\n\tstruct io_tlb_area *areas;\n\tstruct io_tlb_slot *slots;\n};\n\nstruct io_tlb_mem {\n\tstruct io_tlb_pool defpool;\n\tlong unsigned int nslabs;\n\tstruct dentry *debugfs;\n\tbool force_bounce;\n\tbool for_alloc;\n\tatomic_long_t total_used;\n\tatomic_long_t used_hiwater;\n\tatomic_long_t transient_nslabs;\n};\n\nstruct io_tlb_slot {\n\tphys_addr_t orig_addr;\n\tsize_t alloc_size;\n\tshort unsigned int list;\n\tshort unsigned int pad_slots;\n};\n\nstruct io_tw_req {\n\tstruct io_kiocb *req;\n};\n\nstruct io_tw_state {\n\tbool cancel;\n};\n\nstruct io_unlink {\n\tstruct file *file;\n\tint dfd;\n\tint flags;\n\tstruct delayed_filename filename;\n};\n\nstruct io_uring_attr_pi {\n\t__u16 flags;\n\t__u16 app_tag;\n\t__u32 len;\n\t__u64 addr;\n\t__u64 seed;\n\t__u64 rsvd;\n};\n\nstruct io_uring_bpf_filter {\n\t__u32 opcode;\n\t__u32 flags;\n\t__u32 filter_len;\n\t__u8 pdu_size;\n\t__u8 resv[3];\n\t__u64 filter_ptr;\n\t__u64 resv2[5];\n};\n\nstruct io_uring_bpf {\n\t__u16 cmd_type;\n\t__u16 cmd_flags;\n\t__u32 resv;\n\tunion {\n\t\tstruct io_uring_bpf_filter filter;\n\t};\n};\n\nstruct io_uring_bpf_ctx {\n\t__u64 user_data;\n\t__u8 opcode;\n\t__u8 sqe_flags;\n\t__u8 pdu_size;\n\t__u8 pad[5];\n\tunion {\n\t\tstruct {\n\t\t\t__u32 family;\n\t\t\t__u32 type;\n\t\t\t__u32 protocol;\n\t\t} socket;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 mode;\n\t\t\t__u64 resolve;\n\t\t} open;\n\t};\n};\n\nstruct io_uring_buf {\n\t__u64 addr;\n\t__u32 len;\n\t__u16 bid;\n\t__u16 resv;\n};\n\nstruct io_uring_buf_reg {\n\t__u64 ring_addr;\n\t__u32 ring_entries;\n\t__u16 bgid;\n\t__u16 flags;\n\t__u64 resv[3];\n};\n\nstruct io_uring_buf_ring {\n\tunion {\n\t\tstruct {\n\t\t\t__u64 resv1;\n\t\t\t__u32 resv2;\n\t\t\t__u16 resv3;\n\t\t\t__u16 tail;\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_bufs;\n\t\t\tstruct io_uring_buf bufs[0];\n\t\t};\n\t};\n};\n\nstruct io_uring_buf_status {\n\t__u32 buf_group;\n\t__u32 head;\n\t__u32 resv[8];\n};\n\nstruct io_uring_clock_register {\n\t__u32 clockid;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_clone_buffers {\n\t__u32 src_fd;\n\t__u32 flags;\n\t__u32 src_off;\n\t__u32 dst_off;\n\t__u32 nr;\n\t__u32 pad[3];\n};\n\nstruct io_uring_cmd {\n\tstruct file *file;\n\tconst struct io_uring_sqe *sqe;\n\tu32 cmd_op;\n\tu32 flags;\n\tu8 pdu[32];\n\tu8 unused[8];\n};\n\nstruct io_uring_file_index_range {\n\t__u32 off;\n\t__u32 len;\n\t__u64 resv;\n};\n\nstruct io_uring_getevents_arg {\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 min_wait_usec;\n\t__u64 ts;\n};\n\nstruct io_uring_mem_region_reg {\n\t__u64 region_uptr;\n\t__u64 flags;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_napi {\n\t__u32 busy_poll_to;\n\t__u8 prefer_busy_poll;\n\t__u8 opcode;\n\t__u8 pad[2];\n\t__u32 op_param;\n\t__u32 resv;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nstruct io_uring_query_hdr {\n\t__u64 next_entry;\n\t__u64 query_data;\n\t__u32 query_op;\n\t__u32 size;\n\t__s32 result;\n\t__u32 __resv[3];\n};\n\nstruct io_uring_reg_wait {\n\tstruct __kernel_timespec ts;\n\t__u32 min_wait_usec;\n\t__u32 flags;\n\t__u64 sigmask;\n\t__u32 sigmask_sz;\n\t__u32 pad[3];\n\t__u64 pad2[2];\n};\n\nstruct io_uring_region_desc {\n\t__u64 user_addr;\n\t__u64 size;\n\t__u32 flags;\n\t__u32 id;\n\t__u64 mmap_offset;\n\t__u64 __resv[4];\n};\n\nstruct io_uring_restriction {\n\t__u16 opcode;\n\tunion {\n\t\t__u8 register_op;\n\t\t__u8 sqe_op;\n\t\t__u8 sqe_flags;\n\t};\n\t__u8 resv;\n\t__u32 resv2[3];\n};\n\nstruct io_uring_rsrc_register {\n\t__u32 nr;\n\t__u32 flags;\n\t__u64 resv2;\n\t__u64 data;\n\t__u64 tags;\n};\n\nstruct io_uring_rsrc_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n};\n\nstruct io_uring_rsrc_update2 {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 data;\n\t__u64 tags;\n\t__u32 nr;\n\t__u32 resv2;\n};\n\nstruct io_uring_sync_cancel_reg {\n\t__u64 addr;\n\t__s32 fd;\n\t__u32 flags;\n\tstruct __kernel_timespec timeout;\n\t__u8 opcode;\n\t__u8 pad[7];\n\t__u64 pad2[3];\n};\n\nstruct io_wq;\n\nstruct io_uring_task {\n\tint cached_refs;\n\tconst struct io_ring_ctx *last;\n\tstruct task_struct *task;\n\tstruct io_wq *io_wq;\n\tstruct file *registered_rings[16];\n\tstruct xarray xa;\n\tstruct wait_queue_head wait;\n\tatomic_t in_cancel;\n\tatomic_t inflight_tracked;\n\tstruct percpu_counter inflight;\n\tlong: 64;\n\tstruct {\n\t\tstruct llist_head task_list;\n\t\tstruct callback_head task_work;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n};\n\nstruct io_uring_task_restriction {\n\t__u16 flags;\n\t__u16 nr_res;\n\t__u32 resv[3];\n\tstruct {\n\t\tstruct {} __empty_restrictions;\n\t\tstruct io_uring_restriction restrictions[0];\n\t};\n};\n\nstruct io_uring_zcrx_area_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u64 rq_area_token;\n\t__u32 flags;\n\t__u32 dmabuf_fd;\n\t__u64 __resv2[2];\n};\n\nstruct io_uring_zcrx_cqe {\n\t__u64 off;\n\t__u64 __pad;\n};\n\nstruct io_uring_zcrx_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 rqes;\n\t__u32 __resv2;\n\t__u64 __resv[2];\n};\n\nstruct io_uring_zcrx_ifq_reg {\n\t__u32 if_idx;\n\t__u32 if_rxq;\n\t__u32 rq_entries;\n\t__u32 flags;\n\t__u64 area_ptr;\n\t__u64 region_ptr;\n\tstruct io_uring_zcrx_offsets offsets;\n\t__u32 zcrx_id;\n\t__u32 rx_buf_len;\n\t__u64 __resv[3];\n};\n\nstruct io_uring_zcrx_rqe {\n\t__u64 off;\n\t__u32 len;\n\t__u32 __pad;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int cq_tail;\n\tunsigned int cq_min_tail;\n\tunsigned int nr_timeouts;\n\tint hit_timeout;\n\tktime_t min_timeout;\n\tktime_t timeout;\n\tstruct hrtimer t;\n\tktime_t napi_busy_poll_dt;\n\tbool napi_prefer_busy_poll;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct io_waitid {\n\tstruct file *file;\n\tint which;\n\tpid_t upid;\n\tint options;\n\tatomic_t refs;\n\tstruct wait_queue_head *head;\n\tstruct siginfo *infop;\n\tstruct waitid_info info;\n};\n\nstruct rusage;\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct io_waitid_async {\n\tstruct io_kiocb *req;\n\tstruct wait_opts wo;\n};\n\nstruct io_window_t {\n\tu_int InUse;\n\tu_int Config;\n\tstruct resource *res;\n};\n\ntypedef struct io_window_t io_window_t;\n\nstruct io_wq_acct;\n\nstruct io_worker {\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wq *wq;\n\tstruct io_wq_acct *acct;\n\tstruct io_wq_work *cur_work;\n\traw_spinlock_t lock;\n\tstruct completion ref_done;\n\tlong unsigned int create_state;\n\tstruct callback_head create_work;\n\tint init_retries;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct delayed_work work;\n\t};\n};\n\nstruct io_wq_acct {\n\traw_spinlock_t workers_lock;\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\traw_spinlock_t lock;\n\tstruct io_wq_work_list work_list;\n\tlong unsigned int flags;\n};\n\nstruct io_wq {\n\tlong unsigned int state;\n\tstruct io_wq_hash *hash;\n\tatomic_t worker_refs;\n\tstruct completion worker_done;\n\tstruct hlist_node cpuhp_node;\n\tstruct task_struct *task;\n\tstruct io_wq_acct acct[2];\n\tstruct wait_queue_entry wait;\n\tstruct io_wq_work *hash_tail[64];\n\tcpumask_var_t cpu_mask;\n};\n\nstruct io_wq_data {\n\tstruct io_wq_hash *hash;\n\tstruct task_struct *task;\n};\n\nstruct io_wq_hash {\n\trefcount_t refs;\n\tlong unsigned int map;\n\tstruct wait_queue_head wait;\n};\n\nstruct xattr_name;\n\nstruct kernel_xattr_ctx {\n\tunion {\n\t\tconst void *cvalue;\n\t\tvoid *value;\n\t};\n\tvoid *kvalue;\n\tsize_t size;\n\tstruct xattr_name *kname;\n\tunsigned int flags;\n};\n\nstruct io_xattr {\n\tstruct file *file;\n\tstruct kernel_xattr_ctx ctx;\n\tstruct delayed_filename filename;\n};\n\nstruct io_zcrx_mem {\n\tlong unsigned int size;\n\tbool is_dmabuf;\n\tstruct page **pages;\n\tlong unsigned int nr_folios;\n\tstruct sg_table page_sg_table;\n\tlong unsigned int account_pages;\n\tstruct sg_table *sgt;\n\tstruct dma_buf_attachment *attach;\n\tstruct dma_buf *dmabuf;\n};\n\nstruct io_zcrx_area {\n\tstruct net_iov_area nia;\n\tstruct io_zcrx_ifq *ifq;\n\tatomic_t *user_refs;\n\tbool is_mapped;\n\tu16 area_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t freelist_lock;\n\tu32 free_count;\n\tu32 *freelist;\n\tstruct io_zcrx_mem mem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_zcrx_args {\n\tstruct io_kiocb *req;\n\tstruct io_zcrx_ifq *ifq;\n\tstruct socket *sock;\n\tunsigned int nr_skbs;\n};\n\nstruct io_zcrx_ifq {\n\tstruct io_zcrx_area *area;\n\tunsigned int niov_shift;\n\tstruct user_struct *user;\n\tstruct mm_struct *mm_account;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t rq_lock;\n\tstruct io_uring *rq_ring;\n\tstruct io_uring_zcrx_rqe *rqes;\n\tu32 cached_rq_head;\n\tu32 rq_entries;\n\tu32 if_rxq;\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tnetdevice_tracker netdev_tracker;\n\trefcount_t refs;\n\trefcount_t user_refs;\n\tstruct mutex pp_lock;\n\tstruct io_mapped_region region;\n};\n\nstruct ioam6_hdr {\n\t__u8 opt_type;\n\t__u8 opt_len;\n\tchar: 8;\n\t__u8 type;\n};\n\nstruct ioam6_schema;\n\nstruct ioam6_namespace {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_schema *schema;\n\t__be16 id;\n\t__be32 data;\n\t__be64 data_wide;\n};\n\nstruct ioam6_pernet_data {\n\tstruct mutex lock;\n\tstruct rhashtable namespaces;\n\tstruct rhashtable schemas;\n};\n\nstruct ioam6_schema {\n\tstruct rhash_head head;\n\tstruct callback_head rcu;\n\tstruct ioam6_namespace *ns;\n\tu32 id;\n\tint len;\n\t__be32 hdr;\n\tu8 data[0];\n};\n\nstruct ioam6_trace_hdr {\n\t__be16 namespace_id;\n\tchar: 2;\n\t__u8 overflow: 1;\n\t__u8 nodelen: 5;\n\t__u8 remlen: 7;\n\tunion {\n\t\t__be32 type_be32;\n\t\tstruct {\n\t\t\t__u32 bit7: 1;\n\t\t\t__u32 bit6: 1;\n\t\t\t__u32 bit5: 1;\n\t\t\t__u32 bit4: 1;\n\t\t\t__u32 bit3: 1;\n\t\t\t__u32 bit2: 1;\n\t\t\t__u32 bit1: 1;\n\t\t\t__u32 bit0: 1;\n\t\t\t__u32 bit15: 1;\n\t\t\t__u32 bit14: 1;\n\t\t\t__u32 bit13: 1;\n\t\t\t__u32 bit12: 1;\n\t\t\t__u32 bit11: 1;\n\t\t\t__u32 bit10: 1;\n\t\t\t__u32 bit9: 1;\n\t\t\t__u32 bit8: 1;\n\t\t\t__u32 bit23: 1;\n\t\t\t__u32 bit22: 1;\n\t\t\t__u32 bit21: 1;\n\t\t\t__u32 bit20: 1;\n\t\t\t__u32 bit19: 1;\n\t\t\t__u32 bit18: 1;\n\t\t\t__u32 bit17: 1;\n\t\t\t__u32 bit16: 1;\n\t\t} type;\n\t};\n\t__u8 data[0];\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\nstruct ioctl_sick_map {\n\tunsigned int sick_mask;\n\tunsigned int ioctl_mask;\n};\n\nstruct iomap {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tu64 validity_cookie;\n};\n\nstruct iomap_dio_ops;\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tsize_t done_before;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n};\n\nstruct iomap_iter;\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tvoid (*submit_io)(const struct iomap_iter *, struct bio *, loff_t);\n\tstruct bio_set *bio_set;\n};\n\nstruct iomap_folio_state {\n\tspinlock_t state_lock;\n\tunsigned int read_bytes_pending;\n\tatomic_t write_bytes_pending;\n\tlong unsigned int state[0];\n};\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tatomic_t io_remaining;\n\tint io_error;\n\tstruct iomap_ioend *io_parent;\n\tloff_t io_offset;\n\tsector_t io_sector;\n\tvoid *io_private;\n\tstruct bio io_bio;\n};\n\nstruct iomap_iter {\n\tstruct inode *inode;\n\tloff_t pos;\n\tu64 len;\n\tloff_t iter_start_pos;\n\tint status;\n\tunsigned int flags;\n\tstruct iomap iomap;\n\tstruct iomap srcmap;\n\tstruct folio_batch *fbatch;\n\tvoid *private;\n};\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap *, struct iomap *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap *);\n};\n\nstruct iomap_read_ops;\n\nstruct iomap_read_folio_ctx {\n\tconst struct iomap_read_ops *ops;\n\tstruct folio *cur_folio;\n\tstruct readahead_control *rac;\n\tvoid *read_ctx;\n};\n\nstruct iomap_read_ops {\n\tint (*read_folio_range)(const struct iomap_iter *, struct iomap_read_folio_ctx *, size_t);\n\tvoid (*submit_read)(struct iomap_read_folio_ctx *);\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap iomap;\n\tstruct swap_info_struct *sis;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n\tstruct file *file;\n};\n\nstruct iomap_write_ops {\n\tstruct folio * (*get_folio)(struct iomap_iter *, loff_t, unsigned int);\n\tvoid (*put_folio)(struct inode *, loff_t, unsigned int, struct folio *);\n\tbool (*iomap_valid)(struct inode *, const struct iomap *);\n\tint (*read_folio_range)(const struct iomap_iter *, struct folio *, loff_t, size_t);\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tssize_t (*writeback_range)(struct iomap_writepage_ctx *, struct folio *, u64, unsigned int, u64);\n\tint (*writeback_submit)(struct iomap_writepage_ctx *, int);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap iomap;\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tconst struct iomap_writeback_ops *ops;\n\tu32 nr_folios;\n\tvoid *wb_ctx;\n};\n\nstruct iommu_domain;\n\nstruct iommu_attach_handle {\n\tstruct iommu_domain *domain;\n};\n\nstruct iommu_ops;\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n\tstruct iommu_group *singleton_group;\n\tu32 max_pasids;\n\tbool ready;\n};\n\nstruct iova_bitmap;\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_dirty_bitmap {\n\tstruct iova_bitmap *bitmap;\n\tstruct iommu_iotlb_gather *gather;\n};\n\nstruct iommu_dirty_ops {\n\tint (*set_dirty_tracking)(struct iommu_domain *, bool);\n\tint (*read_and_clear_dirty)(struct iommu_domain *, long unsigned int, size_t, long unsigned int, struct iommu_dirty_bitmap *);\n};\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommu_dma_cookie;\n\nstruct iommu_dma_msi_cookie;\n\nstruct iommufd_hw_pagetable;\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_ops;\n\nstruct iopf_group;\n\nstruct iommu_domain {\n\tunsigned int type;\n\tenum iommu_domain_cookie_type cookie_type;\n\tconst struct iommu_domain_ops *ops;\n\tconst struct iommu_dirty_ops *dirty_ops;\n\tconst struct iommu_ops *owner;\n\tlong unsigned int pgsize_bitmap;\n\tstruct iommu_domain_geometry geometry;\n\tint (*iopf_handler)(struct iopf_group *);\n\tunion {\n\t\tstruct iommu_dma_cookie *iova_cookie;\n\t\tstruct iommu_dma_msi_cookie *msi_cookie;\n\t\tstruct iommufd_hw_pagetable *iommufd_hwpt;\n\t\tstruct {\n\t\t\tiommu_fault_handler_t handler;\n\t\t\tvoid *handler_token;\n\t\t};\n\t\tstruct {\n\t\t\tstruct mm_struct *mm;\n\t\t\tint users;\n\t\t\tstruct list_head next;\n\t\t};\n\t};\n};\n\nstruct iommu_user_data_array;\n\nstruct iommu_domain_ops {\n\tint (*attach_dev)(struct iommu_domain *, struct device *, struct iommu_domain *);\n\tint (*set_dev_pasid)(struct iommu_domain *, struct device *, ioasid_t, struct iommu_domain *);\n\tint (*map_pages)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, size_t, int, gfp_t, size_t *);\n\tsize_t (*unmap_pages)(struct iommu_domain *, long unsigned int, size_t, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tint (*iotlb_sync_map)(struct iommu_domain *, long unsigned int, size_t);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tint (*cache_invalidate_user)(struct iommu_domain *, struct iommu_user_data_array *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tbool (*enforce_cache_coherency)(struct iommu_domain *);\n\tint (*set_pgtable_quirks)(struct iommu_domain *, long unsigned int);\n\tvoid (*free)(struct iommu_domain *);\n};\n\nstruct iommu_fault_page_request {\n\tu32 flags;\n\tu32 pasid;\n\tu32 grpid;\n\tu32 perm;\n\tu64 addr;\n\tu64 private_data[2];\n};\n\nstruct iommu_fault {\n\tu32 type;\n\tstruct iommu_fault_page_request prm;\n};\n\nstruct iopf_queue;\n\nstruct iommu_fault_param {\n\tstruct mutex lock;\n\trefcount_t users;\n\tstruct callback_head rcu;\n\tstruct device *dev;\n\tstruct iopf_queue *queue;\n\tstruct list_head queue_list;\n\tstruct list_head partial;\n\tstruct list_head faults;\n};\n\nstruct iommu_fwspec {\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct xarray pasid_array;\n\tstruct mutex mutex;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *blocking_domain;\n\tstruct iommu_domain *resetting_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n\tunsigned int owner_cnt;\n\tvoid *owner;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct iommu_pages_list {\n\tstruct list_head pages;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n\tstruct iommu_pages_list freelist;\n\tbool queued;\n};\n\nstruct iommu_user_data;\n\nstruct of_phandle_args;\n\nstruct iopf_fault;\n\nstruct iommu_page_response;\n\nstruct iommufd_viommu;\n\nstruct iommu_ops {\n\tbool (*capable)(struct device *, enum iommu_cap);\n\tvoid * (*hw_info)(struct device *, u32 *, enum iommu_hw_info_type *);\n\tstruct iommu_domain * (*domain_alloc_identity)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_paging_flags)(struct device *, u32, const struct iommu_user_data *);\n\tstruct iommu_domain * (*domain_alloc_paging)(struct device *);\n\tstruct iommu_domain * (*domain_alloc_sva)(struct device *, struct mm_struct *);\n\tstruct iommu_domain * (*domain_alloc_nested)(struct device *, struct iommu_domain *, u32, const struct iommu_user_data *);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tint (*of_xlate)(struct device *, const struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct device *);\n\tvoid (*page_response)(struct device *, struct iopf_fault *, struct iommu_page_response *);\n\tint (*def_domain_type)(struct device *);\n\tsize_t (*get_viommu_size)(struct device *, enum iommu_viommu_type);\n\tint (*viommu_init)(struct iommufd_viommu *, struct iommu_domain *, const struct iommu_user_data *);\n\tconst struct iommu_domain_ops *default_domain_ops;\n\tstruct module *owner;\n\tstruct iommu_domain *identity_domain;\n\tstruct iommu_domain *blocked_domain;\n\tstruct iommu_domain *release_domain;\n\tstruct iommu_domain *default_domain;\n\tu8 user_pasid_table: 1;\n};\n\nstruct iommu_page_response {\n\tu32 pasid;\n\tu32 grpid;\n\tu32 code;\n};\n\nstruct iommu_pool {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int hint;\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n\tvoid (*free)(struct device *, struct iommu_resv_region *);\n};\n\nstruct iommu_table_ops;\n\nstruct iommu_table {\n\tlong unsigned int it_busno;\n\tlong unsigned int it_size;\n\tlong unsigned int it_indirect_levels;\n\tlong unsigned int it_level_size;\n\tlong unsigned int it_allocated_size;\n\tlong unsigned int it_offset;\n\tlong unsigned int it_base;\n\tlong unsigned int it_index;\n\tlong unsigned int it_type;\n\tlong unsigned int it_blocksize;\n\tlong unsigned int poolsize;\n\tlong unsigned int nr_pools;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct iommu_pool large_pool;\n\tstruct iommu_pool pools[4];\n\tlong unsigned int *it_map;\n\tlong unsigned int it_page_shift;\n\tstruct list_head it_group_list;\n\t__be64 *it_userspace;\n\tstruct iommu_table_ops *it_ops;\n\tstruct kref it_kref;\n\tint it_nid;\n\tlong unsigned int it_reserved_start;\n\tlong unsigned int it_reserved_end;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct iommu_table_group_ops;\n\nstruct iommu_table_group {\n\t__u32 tce32_start;\n\t__u32 tce32_size;\n\t__u64 pgsizes;\n\t__u32 max_dynamic_windows_supported;\n\t__u32 max_levels;\n\tstruct iommu_group *group;\n\tstruct iommu_table *tables[2];\n\tstruct iommu_table_group_ops *ops;\n};\n\nstruct iommu_table_group_link {\n\tstruct list_head next;\n\tstruct callback_head rcu;\n\tstruct iommu_table_group *table_group;\n};\n\nstruct iommu_table_group_ops {\n\tlong unsigned int (*get_table_size)(__u32, __u64, __u32);\n\tlong int (*create_table)(struct iommu_table_group *, int, __u32, __u64, __u32, struct iommu_table **);\n\tlong int (*set_window)(struct iommu_table_group *, int, struct iommu_table *);\n\tlong int (*unset_window)(struct iommu_table_group *, int);\n\tlong int (*take_ownership)(struct iommu_table_group *, struct device *);\n\tvoid (*release_ownership)(struct iommu_table_group *, struct device *);\n};\n\nstruct iommu_table_ops {\n\tint (*set)(struct iommu_table *, long int, long int, long unsigned int, enum dma_data_direction, long unsigned int);\n\tint (*xchg_no_kill)(struct iommu_table *, long int, long unsigned int *, enum dma_data_direction *);\n\tvoid (*tce_kill)(struct iommu_table *, long unsigned int, long unsigned int);\n\t__be64 * (*useraddrptr)(struct iommu_table *, long int, bool);\n\tvoid (*clear)(struct iommu_table *, long int, long int);\n\tlong unsigned int (*get)(struct iommu_table *, long int);\n\tvoid (*flush)(struct iommu_table *);\n\tvoid (*free)(struct iommu_table *);\n};\n\nstruct iommu_user_data {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t len;\n};\n\nstruct iommu_user_data_array {\n\tunsigned int type;\n\tvoid *uptr;\n\tsize_t entry_len;\n\tu32 entry_num;\n};\n\nstruct iommufd_object {\n\trefcount_t wait_cnt;\n\trefcount_t users;\n\tenum iommufd_object_type type;\n\tunsigned int id;\n};\n\nstruct iommufd_access;\n\nstruct iommufd_hw_queue {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_access *access;\n\tu64 base_addr;\n\tsize_t length;\n\tenum iommu_hw_queue_type type;\n\tvoid (*destroy)(struct iommufd_hw_queue *);\n};\n\nstruct iommufd_device;\n\nstruct iommufd_vdevice {\n\tstruct iommufd_object obj;\n\tstruct iommufd_viommu *viommu;\n\tstruct iommufd_device *idev;\n\tu64 virt_id;\n\tvoid (*destroy)(struct iommufd_vdevice *);\n};\n\nstruct iommufd_ctx;\n\nstruct iommufd_hwpt_paging;\n\nstruct iommufd_viommu_ops;\n\nstruct iommufd_viommu {\n\tstruct iommufd_object obj;\n\tstruct iommufd_ctx *ictx;\n\tstruct iommu_device *iommu_dev;\n\tstruct iommufd_hwpt_paging *hwpt;\n\tconst struct iommufd_viommu_ops *ops;\n\tstruct xarray vdevs;\n\tstruct list_head veventqs;\n\tstruct rw_semaphore veventqs_rwsem;\n\tenum iommu_viommu_type type;\n};\n\nstruct iommufd_viommu_ops {\n\tvoid (*destroy)(struct iommufd_viommu *);\n\tstruct iommu_domain * (*alloc_domain_nested)(struct iommufd_viommu *, u32, const struct iommu_user_data *);\n\tint (*cache_invalidate)(struct iommufd_viommu *, struct iommu_user_data_array *);\n\tconst size_t vdevice_size;\n\tint (*vdevice_init)(struct iommufd_vdevice *);\n\tsize_t (*get_hw_queue_size)(struct iommufd_viommu *, enum iommu_hw_queue_type);\n\tint (*hw_queue_init_phys)(struct iommufd_hw_queue *, u32, phys_addr_t);\n};\n\nstruct iopf_fault {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iopf_group {\n\tstruct iopf_fault last_fault;\n\tstruct list_head faults;\n\tsize_t fault_count;\n\tstruct list_head pending_node;\n\tstruct work_struct work;\n\tstruct iommu_attach_handle *attach_handle;\n\tstruct iommu_fault_param *fault_param;\n\tstruct list_head node;\n\tu32 cookie;\n};\n\nstruct iopf_queue {\n\tstruct workqueue_struct *wq;\n\tstruct list_head devices;\n\tstruct mutex lock;\n};\n\nstruct ioptdesc {\n\tlong unsigned int __page_flags;\n\tstruct list_head iopt_freelist_elm;\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tu8 incoherent;\n\t\tlong unsigned int __index;\n\t};\n\tvoid *_private;\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int memcg_data;\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct ip6_frag_state {\n\tu8 *prevhdr;\n\tunsigned int hlen;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\tint hroom;\n\tint troom;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ipv6hdr;\n\nstruct ip6_fraglist_iter {\n\tstruct ipv6hdr *tmp_hdr;\n\tstruct sk_buff *frag;\n\tint offset;\n\tunsigned int hlen;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nstruct ip6_mtuinfo {\n\tstruct sockaddr_in6 ip6m_addr;\n\t__u32 ip6m_mtu;\n};\n\nstruct ip6_ra_chain {\n\tstruct ip6_ra_chain *next;\n\tstruct sock *sk;\n\tint sel;\n\tvoid (*destructor)(struct sock *);\n};\n\nstruct ip6_rt_info {\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\tu_int32_t mark;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip6_tnl {\n\tstruct ip6_tnl *next;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tstruct __ip6_tnl_parm parms;\n\tstruct flowi fl;\n\tstruct dst_cache dst_cache;\n\tstruct gro_cells gro_cells;\n\tint err_count;\n\tlong unsigned int err_time;\n\t__u32 i_seqno;\n\tatomic_t o_seqno;\n\tint hlen;\n\tint tun_hlen;\n\tint encap_hlen;\n\tstruct ip_tunnel_encap encap;\n\tint mlink;\n};\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct ip6addrlbl_entry {\n\tstruct in6_addr prefix;\n\tint prefixlen;\n\tint ifindex;\n\tint addrtype;\n\tu32 label;\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n};\n\nstruct ip6addrlbl_init_table {\n\tconst struct in6_addr *prefix;\n\tint prefixlen;\n\tu32 label;\n};\n\nstruct ip6fl_iter_state {\n\tstruct seq_net_private p;\n\tstruct pid_namespace *pid_ns;\n\tint bucket;\n};\n\nstruct ip6rd_flowi {\n\tstruct flowi6 fl6;\n\tstruct in6_addr gateway;\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct ip_beet_phdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 padlen;\n\t__u8 reserved;\n};\n\nstruct ip_conntrack_stat {\n\tunsigned int found;\n\tunsigned int invalid;\n\tunsigned int insert;\n\tunsigned int insert_failed;\n\tunsigned int clash_resolve;\n\tunsigned int drop;\n\tunsigned int early_drop;\n\tunsigned int error;\n\tunsigned int expect_new;\n\tunsigned int expect_create;\n\tunsigned int expect_delete;\n\tunsigned int search_restart;\n\tunsigned int chaintoolong;\n};\n\nstruct ip_ct_sctp {\n\tenum sctp_conntrack state;\n\t__be32 vtag[2];\n\tu8 init[2];\n\tu8 last_dir;\n\tu8 flags;\n};\n\nstruct ip_ct_tcp_state {\n\tu_int32_t td_end;\n\tu_int32_t td_maxend;\n\tu_int32_t td_maxwin;\n\tu_int32_t td_maxack;\n\tu_int8_t td_scale;\n\tu_int8_t flags;\n};\n\nstruct ip_ct_tcp {\n\tstruct ip_ct_tcp_state seen[2];\n\tu_int8_t state;\n\tu_int8_t last_dir;\n\tu_int8_t retrans;\n\tu_int8_t last_index;\n\tu_int32_t last_seq;\n\tu_int32_t last_ack;\n\tu_int32_t last_end;\n\tu_int16_t last_win;\n\tu_int8_t last_wscale;\n\tu_int8_t last_flags;\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct unix_domain;\n\nstruct ip_map {\n\tstruct cache_head h;\n\tchar m_class[8];\n\tstruct in6_addr m_addr;\n\tstruct unix_domain *m_client;\n\tstruct callback_head m_rcu;\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct ip_sf_socklist;\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\tunion {\n\t\t__be32 imsf_slist[1];\n\t\tstruct {\n\t\t\tstruct {} __empty_imsf_slist_flex;\n\t\t\t__be32 imsf_slist_flex[0];\n\t\t};\n\t};\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_rt_info {\n\t__be32 daddr;\n\t__be32 saddr;\n\tu_int8_t tos;\n\tu_int32_t mark;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_tunnel_parm_kern {\n\tchar name[16];\n\tlong unsigned int i_flags[1];\n\tlong unsigned int o_flags[1];\n\t__be32 i_key;\n\t__be32 o_key;\n\tint link;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl_entry;\n\nstruct ip_tunnel {\n\tstruct ip_tunnel *next;\n\tstruct hlist_node hash_node;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net *net;\n\tlong unsigned int err_time;\n\tint err_count;\n\tu32 i_seqno;\n\tatomic_t o_seqno;\n\tint tun_hlen;\n\tu32 index;\n\tu8 erspan_ver;\n\tu8 dir;\n\tu16 hwid;\n\tstruct dst_cache dst_cache;\n\tstruct ip_tunnel_parm_kern parms;\n\tint mlink;\n\tint encap_hlen;\n\tint hlen;\n\tstruct ip_tunnel_encap encap;\n\tstruct ip_tunnel_prl_entry *prl;\n\tunsigned int prl_count;\n\tunsigned int ip_tnl_net_id;\n\tstruct gro_cells gro_cells;\n\t__u32 fwmark;\n\tbool collect_md;\n\tbool ignore_df;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\tlong unsigned int tun_flags[1];\n\t__be32 label;\n\tu32 nhid;\n\tu8 tos;\n\tu8 ttl;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n\t__u8 flow_flags;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct ip_tunnel_encap encap;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n\tlong: 0;\n\tu8 options[0];\n};\n\nstruct rtnl_link_ops;\n\nstruct ip_tunnel_net {\n\tstruct net_device *fb_tunnel_dev;\n\tstruct rtnl_link_ops *rtnl_link_ops;\n\tstruct hlist_head tunnels[128];\n\tstruct ip_tunnel *collect_md_tun;\n\tint type;\n};\n\nstruct ip_tunnel_parm {\n\tchar name[16];\n\tint link;\n\t__be16 i_flags;\n\t__be16 o_flags;\n\t__be32 i_key;\n\t__be32 o_key;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_prl {\n\t__be32 addr;\n\t__u16 flags;\n\t__u16 __reserved;\n\t__u32 datalen;\n\t__u32 __reserved2;\n};\n\nstruct ip_tunnel_prl_entry {\n\tstruct ip_tunnel_prl_entry *next;\n\t__be32 addr;\n\tu16 flags;\n\tstruct callback_head callback_head;\n};\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned int seq;\n\tunsigned int __pad1;\n\tlong long unsigned int __unused1;\n\tlong long unsigned int __unused2;\n};\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tint next_id;\n\tstruct rhashtable key_ht;\n};\n\nstruct msgbuf;\n\nstruct ipc_kludge {\n\tstruct msgbuf *msgp;\n\tlong int msgtyp;\n};\n\nstruct ipc_namespace {\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tstruct percpu_counter percpu_msg_bytes;\n\tstruct percpu_counter percpu_msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct ctl_table_set mq_set;\n\tstruct ctl_table_header *mq_sysctls;\n\tstruct ctl_table_set ipc_set;\n\tstruct ctl_table_header *ipc_sysctls;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nstruct ipc_params;\n\nstruct kern_ipc_perm;\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct ipc_security_struct {\n\tu16 sclass;\n\tu32 sid;\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu32 tsflags;\n\tu32 ts_opt_id;\n\tu32 priority;\n\tu32 dmabuf_id;\n};\n\nstruct ipcm6_cookie {\n\tstruct sockcm_cookie sockc;\n\t__s16 hlimit;\n\t__s16 tclass;\n\t__u16 gso_size;\n\t__s8 dontfrag;\n\tstruct ipv6_txoptions *opt;\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 protocol;\n\t__u8 ttl;\n\t__s16 tos;\n\t__u16 gso_size;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n\tint ip_defrag_offset;\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ipr_auto_sense {\n\t__be16 auto_sense_len;\n\t__be16 ioa_data_len;\n\t__be32 data[24];\n};\n\nstruct ipr_bus_attributes {\n\tu8 bus;\n\tu8 qas_enabled;\n\tu8 bus_width;\n\tu8 reserved;\n\tu32 max_xfer_rate;\n};\n\nstruct ipr_interrupt_offsets {\n\tlong unsigned int set_interrupt_mask_reg;\n\tlong unsigned int clr_interrupt_mask_reg;\n\tlong unsigned int clr_interrupt_mask_reg32;\n\tlong unsigned int sense_interrupt_mask_reg;\n\tlong unsigned int sense_interrupt_mask_reg32;\n\tlong unsigned int clr_interrupt_reg;\n\tlong unsigned int clr_interrupt_reg32;\n\tlong unsigned int sense_interrupt_reg;\n\tlong unsigned int sense_interrupt_reg32;\n\tlong unsigned int ioarrin_reg;\n\tlong unsigned int sense_uproc_interrupt_reg;\n\tlong unsigned int sense_uproc_interrupt_reg32;\n\tlong unsigned int set_uproc_interrupt_reg;\n\tlong unsigned int set_uproc_interrupt_reg32;\n\tlong unsigned int clr_uproc_interrupt_reg;\n\tlong unsigned int clr_uproc_interrupt_reg32;\n\tlong unsigned int init_feedback_reg;\n\tlong unsigned int dump_addr_reg;\n\tlong unsigned int dump_data_reg;\n\tlong unsigned int endian_swap_reg;\n};\n\nstruct ipr_chip_cfg_t {\n\tu32 mailbox;\n\tu16 max_cmds;\n\tu8 cache_line_size;\n\tu8 clear_isr;\n\tu32 iopoll_weight;\n\tstruct ipr_interrupt_offsets regs;\n};\n\nstruct ipr_chip_t {\n\tu16 vendor;\n\tu16 device;\n\tbool has_msi;\n\tu16 sis_type;\n\tu16 bist_method;\n\tconst struct ipr_chip_cfg_t *cfg;\n};\n\nstruct ipr_cmd_pkt {\n\tu8 reserved;\n\tu8 hrrq_id;\n\tu8 request_type;\n\tu8 reserved2;\n\tu8 flags_hi;\n\tu8 flags_lo;\n\tu8 cdb[16];\n\t__be16 timeout;\n};\n\nstruct ipr_ioadl_desc {\n\t__be32 flags_and_data_len;\n\t__be32 address;\n};\n\nstruct ipr_ioarcb_add_data {\n\tunion {\n\t\tstruct ipr_ioadl_desc ioadl[5];\n\t\t__be32 add_cmd_parms[10];\n\t} u;\n};\n\nstruct ipr_ioarcb_sis64_add_addr_ecb {\n\t__be64 ioasa_host_pci_addr;\n\t__be64 data_ioadl_addr;\n\t__be64 reserved;\n\t__be32 ext_control_buf[4];\n};\n\nstruct ipr_ioarcb {\n\tunion {\n\t\t__be32 ioarcb_host_pci_addr;\n\t\t__be64 ioarcb_host_pci_addr64;\n\t} a;\n\t__be32 res_handle;\n\t__be32 host_response_handle;\n\t__be32 reserved1;\n\t__be32 reserved2;\n\t__be32 reserved3;\n\t__be32 data_transfer_length;\n\t__be32 read_data_transfer_length;\n\t__be32 write_ioadl_addr;\n\t__be32 ioadl_len;\n\t__be32 read_ioadl_addr;\n\t__be32 read_ioadl_len;\n\t__be32 ioasa_host_pci_addr;\n\t__be16 ioasa_len;\n\t__be16 reserved4;\n\tstruct ipr_cmd_pkt cmd_pkt;\n\t__be16 add_cmd_parms_offset;\n\t__be16 add_cmd_parms_len;\n\tunion {\n\t\tstruct ipr_ioarcb_add_data add_data;\n\t\tstruct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;\n\t} u;\n};\n\nstruct ipr_ioadl64_desc {\n\t__be32 flags;\n\t__be32 data_len;\n\t__be64 address;\n};\n\nstruct ipr_ioasa_hdr {\n\t__be32 ioasc;\n\t__be16 ret_stat_len;\n\t__be16 avail_stat_len;\n\t__be32 residual_data_len;\n\t__be32 ilid;\n\t__be32 fd_ioasc;\n\t__be32 fd_phys_locator;\n\t__be32 fd_res_handle;\n\t__be32 ioasc_specific;\n};\n\nstruct ipr_ioasa_vset {\n\t__be32 failing_lba_hi;\n\t__be32 failing_lba_lo;\n\t__be32 reserved;\n};\n\nstruct ipr_ioasa_af_dasd {\n\t__be32 failing_lba;\n\t__be32 reserved[2];\n};\n\nstruct ipr_ioasa_gpdd {\n\tu8 end_state;\n\tu8 bus_phase;\n\t__be16 reserved;\n\t__be32 ioa_data[2];\n};\n\nstruct ipr_ioasa {\n\tstruct ipr_ioasa_hdr hdr;\n\tunion {\n\t\tstruct ipr_ioasa_vset vset;\n\t\tstruct ipr_ioasa_af_dasd dasd;\n\t\tstruct ipr_ioasa_gpdd gpdd;\n\t} u;\n\tstruct ipr_auto_sense auto_sense;\n};\n\nstruct ipr_ioasa64 {\n\tstruct ipr_ioasa_hdr hdr;\n\tu8 fd_res_path[8];\n\tunion {\n\t\tstruct ipr_ioasa_vset vset;\n\t\tstruct ipr_ioasa_af_dasd dasd;\n\t\tstruct ipr_ioasa_gpdd gpdd;\n\t} u;\n\tstruct ipr_auto_sense auto_sense;\n};\n\nstruct ipr_hostrcb;\n\nstruct ipr_resource_entry;\n\nstruct ipr_hrr_queue;\n\nstruct ipr_ioa_cfg;\n\nstruct ipr_cmnd {\n\tstruct ipr_ioarcb ioarcb;\n\tunion {\n\t\tstruct ipr_ioadl_desc ioadl[64];\n\t\tstruct ipr_ioadl64_desc ioadl64[64];\n\t} i;\n\tunion {\n\t\tstruct ipr_ioasa ioasa;\n\t\tstruct ipr_ioasa64 ioasa64;\n\t} s;\n\tstruct list_head queue;\n\tstruct scsi_cmnd *scsi_cmd;\n\tstruct completion completion;\n\tstruct timer_list timer;\n\tstruct work_struct work;\n\tvoid (*fast_done)(struct ipr_cmnd *);\n\tvoid (*done)(struct ipr_cmnd *);\n\tint (*job_step)(struct ipr_cmnd *);\n\tint (*job_step_failed)(struct ipr_cmnd *);\n\tu16 cmd_index;\n\tu8 sense_buffer[96];\n\tdma_addr_t sense_buffer_dma;\n\tshort unsigned int dma_use_sg;\n\tdma_addr_t dma_addr;\n\tstruct ipr_cmnd *sibling;\n\tunion {\n\t\tenum ipr_shutdown_type shutdown_type;\n\t\tstruct ipr_hostrcb *hostrcb;\n\t\tlong unsigned int time_left;\n\t\tlong unsigned int scratch;\n\t\tstruct ipr_resource_entry *res;\n\t\tstruct scsi_device *sdev;\n\t} u;\n\tstruct completion *eh_comp;\n\tstruct ipr_hrr_queue *hrrq;\n\tstruct ipr_ioa_cfg *ioa_cfg;\n};\n\nstruct ipr_config_table_hdr {\n\tu8 num_entries;\n\tu8 flags;\n\t__be16 reserved;\n};\n\nstruct ipr_res_addr {\n\tu8 reserved;\n\tu8 bus;\n\tu8 target;\n\tu8 lun;\n};\n\nstruct ipr_std_inq_vpids {\n\tu8 vendor_id[8];\n\tu8 product_id[16];\n};\n\nstruct ipr_std_inq_data {\n\tu8 peri_qual_dev_type;\n\tu8 removeable_medium_rsvd;\n\tu8 version;\n\tu8 aen_naca_fmt;\n\tu8 additional_len;\n\tu8 sccs_rsvd;\n\tu8 bq_enc_multi;\n\tu8 sync_cmdq_flags;\n\tstruct ipr_std_inq_vpids vpids;\n\tu8 ros_rsvd_ram_rsvd[4];\n\tu8 serial_num[8];\n};\n\nstruct ipr_config_table_entry {\n\tu8 proto;\n\tu8 array_id;\n\tu8 flags;\n\tu8 rsvd_subtype;\n\tstruct ipr_res_addr res_addr;\n\t__be32 res_handle;\n\t__be32 lun_wwn[2];\n\tstruct ipr_std_inq_data std_inq_data;\n};\n\nstruct ipr_config_table {\n\tstruct ipr_config_table_hdr hdr;\n\tstruct ipr_config_table_entry dev[0];\n};\n\nstruct ipr_config_table_hdr64 {\n\t__be16 num_entries;\n\t__be16 reserved;\n\tu8 flags;\n\tu8 reserved2[11];\n};\n\nstruct ipr_config_table_entry64 {\n\tu8 res_type;\n\tu8 proto;\n\tu8 vset_num;\n\tu8 array_id;\n\t__be16 flags;\n\t__be16 res_flags;\n\t__be32 res_handle;\n\tu8 dev_id_type;\n\tu8 reserved[3];\n\t__be64 dev_id;\n\t__be64 lun;\n\t__be64 lun_wwn[2];\n\t__be64 res_path;\n\tstruct ipr_std_inq_data std_inq_data;\n\tu8 reserved2[4];\n\t__be64 reserved3[2];\n\tu8 reserved4[8];\n};\n\nstruct ipr_config_table64 {\n\tstruct ipr_config_table_hdr64 hdr64;\n\tstruct ipr_config_table_entry64 dev[0];\n};\n\nstruct ipr_config_table_entry_wrapper {\n\tunion {\n\t\tstruct ipr_config_table_entry *cfgte;\n\t\tstruct ipr_config_table_entry64 *cfgte64;\n\t} u;\n};\n\nstruct ipr_dev_bus_entry {\n\tstruct ipr_res_addr res_addr;\n\tu8 flags;\n\tu8 scsi_id;\n\tu8 bus_width;\n\tu8 extended_reset_delay;\n\t__be32 max_xfer_rate;\n\tu8 spinup_delay;\n\tu8 reserved3;\n\t__be16 reserved4;\n};\n\nstruct ipr_dump_header {\n\tu32 eye_catcher;\n\tu32 len;\n\tu32 num_entries;\n\tu32 first_entry_offset;\n\tu32 status;\n\tu32 os;\n\tu32 driver_name;\n};\n\nstruct ipr_dump_entry_header {\n\tu32 eye_catcher;\n\tu32 len;\n\tu32 num_elems;\n\tu32 offset;\n\tu32 data_type;\n\tu32 id;\n\tu32 status;\n};\n\nstruct ipr_dump_version_entry {\n\tstruct ipr_dump_entry_header hdr;\n\tu8 version[6];\n};\n\nstruct ipr_dump_location_entry {\n\tstruct ipr_dump_entry_header hdr;\n\tu8 location[20];\n};\n\nstruct ipr_dump_ioa_type_entry {\n\tstruct ipr_dump_entry_header hdr;\n\tu32 type;\n\tu32 fw_version;\n};\n\nstruct ipr_dump_trace_entry {\n\tstruct ipr_dump_entry_header hdr;\n\tu32 trace[1024];\n};\n\nstruct ipr_driver_dump {\n\tstruct ipr_dump_header hdr;\n\tstruct ipr_dump_version_entry version_entry;\n\tstruct ipr_dump_location_entry location_entry;\n\tstruct ipr_dump_ioa_type_entry ioa_type_entry;\n\tstruct ipr_dump_trace_entry trace_entry;\n};\n\nstruct ipr_sdt_header {\n\t__be32 state;\n\t__be32 num_entries;\n\t__be32 num_entries_used;\n\t__be32 dump_size;\n};\n\nstruct ipr_sdt_entry {\n\t__be32 start_token;\n\t__be32 end_token;\n\tu8 reserved[4];\n\tu8 flags;\n\tu8 resv;\n\t__be16 priority;\n};\n\nstruct ipr_sdt {\n\tstruct ipr_sdt_header hdr;\n\tstruct ipr_sdt_entry entry[4095];\n};\n\nstruct ipr_ioa_dump {\n\tstruct ipr_dump_entry_header hdr;\n\tstruct ipr_sdt sdt;\n\t__be32 **ioa_data;\n\tu32 reserved;\n\tu32 next_page_index;\n\tu32 page_offset;\n\tu32 format;\n} __attribute__((packed));\n\nstruct ipr_dump {\n\tstruct kref kref;\n\tstruct ipr_ioa_cfg *ioa_cfg;\n\tstruct ipr_driver_dump driver_dump;\n\tstruct ipr_ioa_dump ioa_dump;\n};\n\nstruct ipr_error_table_t {\n\tu32 ioasc;\n\tint log_ioasa;\n\tint log_hcam;\n\tchar *error;\n};\n\nstruct ipr_vpd {\n\tstruct ipr_std_inq_vpids vpids;\n\tu8 sn[8];\n};\n\nstruct ipr_ext_vpd {\n\tstruct ipr_vpd vpd;\n\t__be32 wwid[2];\n};\n\nstruct ipr_ext_vpd64 {\n\tstruct ipr_vpd vpd;\n\t__be32 wwid[4];\n};\n\nstruct ipr_hostrcb_type_ff_error {\n\t__be32 ioa_data[758];\n};\n\nstruct ipr_hostrcb_type_01_error {\n\t__be32 seek_counter;\n\t__be32 read_counter;\n\tu8 sense_data[32];\n\t__be32 ioa_data[236];\n};\n\nstruct ipr_hostrcb_type_02_error {\n\tstruct ipr_vpd ioa_vpd;\n\tstruct ipr_vpd cfc_vpd;\n\tstruct ipr_vpd ioa_last_attached_to_cfc_vpd;\n\tstruct ipr_vpd cfc_last_attached_to_ioa_vpd;\n\t__be32 ioa_data[3];\n};\n\nstruct ipr_hostrcb_device_data_entry {\n\tstruct ipr_vpd vpd;\n\tstruct ipr_res_addr dev_res_addr;\n\tstruct ipr_vpd new_vpd;\n\tstruct ipr_vpd ioa_last_with_dev_vpd;\n\tstruct ipr_vpd cfc_last_with_dev_vpd;\n\t__be32 ioa_data[5];\n};\n\nstruct ipr_hostrcb_type_03_error {\n\tstruct ipr_vpd ioa_vpd;\n\tstruct ipr_vpd cfc_vpd;\n\t__be32 errors_detected;\n\t__be32 errors_logged;\n\tu8 ioa_data[12];\n\tstruct ipr_hostrcb_device_data_entry dev[3];\n};\n\nstruct ipr_hostrcb_array_data_entry {\n\tstruct ipr_vpd vpd;\n\tstruct ipr_res_addr expected_dev_res_addr;\n\tstruct ipr_res_addr dev_res_addr;\n};\n\nstruct ipr_hostrcb_type_04_error {\n\tstruct ipr_vpd ioa_vpd;\n\tstruct ipr_vpd cfc_vpd;\n\tu8 ioa_data[12];\n\tstruct ipr_hostrcb_array_data_entry array_member[10];\n\t__be32 exposed_mode_adn;\n\t__be32 array_id;\n\tstruct ipr_vpd incomp_dev_vpd;\n\t__be32 ioa_data2;\n\tstruct ipr_hostrcb_array_data_entry array_member2[8];\n\tstruct ipr_res_addr last_func_vset_res_addr;\n\tu8 vset_serial_num[8];\n\tu8 protection_level[8];\n};\n\nstruct ipr_hostrcb_type_07_error {\n\tu8 failure_reason[64];\n\tstruct ipr_vpd vpd;\n\t__be32 data[222];\n};\n\nstruct ipr_hostrcb_type_12_error {\n\tstruct ipr_ext_vpd ioa_vpd;\n\tstruct ipr_ext_vpd cfc_vpd;\n\tstruct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;\n\tstruct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;\n\t__be32 ioa_data[3];\n};\n\nstruct ipr_hostrcb_device_data_entry_enhanced {\n\tstruct ipr_ext_vpd vpd;\n\tu8 ccin[4];\n\tstruct ipr_res_addr dev_res_addr;\n\tstruct ipr_ext_vpd new_vpd;\n\tu8 new_ccin[4];\n\tstruct ipr_ext_vpd ioa_last_with_dev_vpd;\n\tstruct ipr_ext_vpd cfc_last_with_dev_vpd;\n};\n\nstruct ipr_hostrcb_type_13_error {\n\tstruct ipr_ext_vpd ioa_vpd;\n\tstruct ipr_ext_vpd cfc_vpd;\n\t__be32 errors_detected;\n\t__be32 errors_logged;\n\tstruct ipr_hostrcb_device_data_entry_enhanced dev[3];\n};\n\nstruct ipr_hostrcb_array_data_entry_enhanced {\n\tstruct ipr_ext_vpd vpd;\n\tu8 ccin[4];\n\tstruct ipr_res_addr expected_dev_res_addr;\n\tstruct ipr_res_addr dev_res_addr;\n};\n\nstruct ipr_hostrcb_type_14_error {\n\tstruct ipr_ext_vpd ioa_vpd;\n\tstruct ipr_ext_vpd cfc_vpd;\n\t__be32 exposed_mode_adn;\n\t__be32 array_id;\n\tstruct ipr_res_addr last_func_vset_res_addr;\n\tu8 vset_serial_num[8];\n\tu8 protection_level[8];\n\t__be32 num_entries;\n\tstruct ipr_hostrcb_array_data_entry_enhanced array_member[18];\n};\n\nstruct ipr_hostrcb_type_17_error {\n\tu8 failure_reason[64];\n\tstruct ipr_ext_vpd vpd;\n\t__be32 data[476];\n};\n\nstruct ipr_hostrcb_config_element {\n\tu8 type_status;\n\tu8 cascaded_expander;\n\tu8 phy;\n\tu8 link_rate;\n\t__be32 wwid[2];\n};\n\nstruct ipr_hostrcb_fabric_desc {\n\t__be16 length;\n\tu8 ioa_port;\n\tu8 cascaded_expander;\n\tu8 phy;\n\tu8 path_state;\n\t__be16 num_entries;\n\tstruct ipr_hostrcb_config_element elem[0];\n};\n\nstruct ipr_hostrcb_type_20_error {\n\tu8 failure_reason[64];\n\tu8 reserved[3];\n\tu8 num_entries;\n\tstruct ipr_hostrcb_fabric_desc desc[1];\n};\n\nstruct ipr_hostrcb_error {\n\t__be32 fd_ioasc;\n\tstruct ipr_res_addr fd_res_addr;\n\t__be32 fd_res_handle;\n\t__be32 prc;\n\tunion {\n\t\tstruct ipr_hostrcb_type_ff_error type_ff_error;\n\t\tstruct ipr_hostrcb_type_01_error type_01_error;\n\t\tstruct ipr_hostrcb_type_02_error type_02_error;\n\t\tstruct ipr_hostrcb_type_03_error type_03_error;\n\t\tstruct ipr_hostrcb_type_04_error type_04_error;\n\t\tstruct ipr_hostrcb_type_07_error type_07_error;\n\t\tstruct ipr_hostrcb_type_12_error type_12_error;\n\t\tstruct ipr_hostrcb_type_13_error type_13_error;\n\t\tstruct ipr_hostrcb_type_14_error type_14_error;\n\t\tstruct ipr_hostrcb_type_17_error type_17_error;\n\t\tstruct ipr_hostrcb_type_20_error type_20_error;\n\t} u;\n};\n\nstruct ipr_hostrcb_type_21_error {\n\t__be32 wwn[4];\n\tu8 res_path[8];\n\tu8 primary_problem_desc[32];\n\tu8 second_problem_desc[32];\n\t__be32 sense_data[8];\n\t__be32 cdb[4];\n\t__be32 residual_trans_length;\n\t__be32 length_of_error;\n\t__be32 ioa_data[236];\n};\n\nstruct ipr_hostrcb64_device_data_entry_enhanced {\n\tstruct ipr_ext_vpd vpd;\n\tu8 ccin[4];\n\tu8 res_path[8];\n\tstruct ipr_ext_vpd new_vpd;\n\tu8 new_ccin[4];\n\tstruct ipr_ext_vpd ioa_last_with_dev_vpd;\n\tstruct ipr_ext_vpd cfc_last_with_dev_vpd;\n};\n\nstruct ipr_hostrcb_type_23_error {\n\tstruct ipr_ext_vpd ioa_vpd;\n\tstruct ipr_ext_vpd cfc_vpd;\n\t__be32 errors_detected;\n\t__be32 errors_logged;\n\tstruct ipr_hostrcb64_device_data_entry_enhanced dev[3];\n};\n\nstruct ipr_hostrcb64_array_data_entry {\n\tstruct ipr_ext_vpd vpd;\n\tu8 ccin[4];\n\tu8 expected_res_path[8];\n\tu8 res_path[8];\n};\n\nstruct ipr_hostrcb_type_24_error {\n\tstruct ipr_ext_vpd ioa_vpd;\n\tstruct ipr_ext_vpd cfc_vpd;\n\tu8 reserved[2];\n\tu8 exposed_mode_adn;\n\tu8 array_id;\n\tu8 last_res_path[8];\n\tu8 protection_level[8];\n\tstruct ipr_ext_vpd64 array_vpd;\n\tu8 description[16];\n\tu8 reserved2[3];\n\tu8 num_entries;\n\tstruct ipr_hostrcb64_array_data_entry array_member[32];\n};\n\nstruct ipr_hostrcb64_config_element {\n\t__be16 length;\n\tu8 descriptor_id;\n\tu8 reserved;\n\tu8 type_status;\n\tu8 reserved2[2];\n\tu8 link_rate;\n\tu8 res_path[8];\n\t__be32 wwid[2];\n};\n\nstruct ipr_hostrcb64_fabric_desc {\n\t__be16 length;\n\tu8 descriptor_id;\n\tu8 reserved[2];\n\tu8 path_state;\n\tu8 reserved2[2];\n\tu8 res_path[8];\n\tu8 reserved3[6];\n\t__be16 num_entries;\n\tstruct ipr_hostrcb64_config_element elem[0];\n};\n\nstruct ipr_hostrcb_type_30_error {\n\tu8 failure_reason[64];\n\tu8 reserved[3];\n\tu8 num_entries;\n\tstruct ipr_hostrcb64_fabric_desc desc[1];\n};\n\nstruct ipr_hostrcb_type_41_error {\n\tu8 failure_reason[64];\n\t__be32 data[200];\n};\n\nstruct ipr_hostrcb64_error {\n\t__be32 fd_ioasc;\n\t__be32 ioa_fw_level;\n\t__be32 fd_res_handle;\n\t__be32 prc;\n\t__be64 fd_dev_id;\n\t__be64 fd_lun;\n\tu8 fd_res_path[8];\n\t__be64 time_stamp;\n\tu8 reserved[16];\n\tunion {\n\t\tstruct ipr_hostrcb_type_ff_error type_ff_error;\n\t\tstruct ipr_hostrcb_type_12_error type_12_error;\n\t\tstruct ipr_hostrcb_type_17_error type_17_error;\n\t\tstruct ipr_hostrcb_type_21_error type_21_error;\n\t\tstruct ipr_hostrcb_type_23_error type_23_error;\n\t\tstruct ipr_hostrcb_type_24_error type_24_error;\n\t\tstruct ipr_hostrcb_type_30_error type_30_error;\n\t\tstruct ipr_hostrcb_type_41_error type_41_error;\n\t} u;\n};\n\nstruct ipr_hostrcb_cfg_ch_not {\n\tunion {\n\t\tstruct ipr_config_table_entry cfgte;\n\t\tstruct ipr_config_table_entry64 cfgte64;\n\t} u;\n\tu8 reserved[936];\n};\n\nstruct ipr_hostrcb_raw {\n\t__be32 data[762];\n};\n\nstruct ipr_hcam {\n\tu8 op_code;\n\tu8 notify_type;\n\tu8 notifications_lost;\n\tu8 flags;\n\tu8 overlay_id;\n\tu8 reserved1[3];\n\t__be32 ilid;\n\t__be32 time_since_last_ioa_reset;\n\t__be32 reserved2;\n\t__be32 length;\n\tunion {\n\t\tstruct ipr_hostrcb_error error;\n\t\tstruct ipr_hostrcb64_error error64;\n\t\tstruct ipr_hostrcb_cfg_ch_not ccn;\n\t\tstruct ipr_hostrcb_raw raw;\n\t} u;\n};\n\nstruct ipr_hostrcb {\n\tstruct ipr_hcam hcam;\n\tdma_addr_t hostrcb_dma;\n\tstruct list_head queue;\n\tstruct ipr_ioa_cfg *ioa_cfg;\n\tchar rp_buffer[48];\n};\n\nstruct ipr_hrr_queue {\n\tstruct ipr_ioa_cfg *ioa_cfg;\n\t__be32 *host_rrq;\n\tdma_addr_t host_rrq_dma;\n\tvolatile __be32 *hrrq_start;\n\tvolatile __be32 *hrrq_end;\n\tvolatile __be32 *hrrq_curr;\n\tstruct list_head hrrq_free_q;\n\tstruct list_head hrrq_pending_q;\n\tspinlock_t _lock;\n\tspinlock_t *lock;\n\tvolatile u32 toggle_bit;\n\tu32 size;\n\tu32 min_cmd_id;\n\tu32 max_cmd_id;\n\tu8 allow_interrupts: 1;\n\tu8 ioa_is_dead: 1;\n\tu8 allow_cmds: 1;\n\tu8 removing_ioa: 1;\n\tstruct irq_poll iopoll;\n};\n\nstruct ipr_inquiry_cap {\n\tu8 peri_qual_dev_type;\n\tu8 page_code;\n\tu8 reserved1;\n\tu8 page_length;\n\tu8 ascii_len;\n\tu8 reserved2;\n\tu8 sis_version[2];\n\tu8 cap;\n\tu8 reserved3[15];\n};\n\nstruct ipr_inquiry_page0 {\n\tu8 peri_qual_dev_type;\n\tu8 page_code;\n\tu8 reserved1;\n\tu8 len;\n\tu8 page[20];\n};\n\nstruct ipr_inquiry_page3 {\n\tu8 peri_qual_dev_type;\n\tu8 page_code;\n\tu8 reserved1;\n\tu8 page_length;\n\tu8 ascii_len;\n\tu8 reserved2[3];\n\tu8 load_id[4];\n\tu8 major_release;\n\tu8 card_type;\n\tu8 minor_release[2];\n\tu8 ptf_number[4];\n\tu8 patch_number[4];\n};\n\nstruct ipr_inquiry_pageC4 {\n\tu8 peri_qual_dev_type;\n\tu8 page_code;\n\tu8 reserved1;\n\tu8 len;\n\tu8 cache_cap[4];\n\tu8 reserved2[20];\n};\n\nstruct ipr_interrupts {\n\tvoid *set_interrupt_mask_reg;\n\tvoid *clr_interrupt_mask_reg;\n\tvoid *clr_interrupt_mask_reg32;\n\tvoid *sense_interrupt_mask_reg;\n\tvoid *sense_interrupt_mask_reg32;\n\tvoid *clr_interrupt_reg;\n\tvoid *clr_interrupt_reg32;\n\tvoid *sense_interrupt_reg;\n\tvoid *sense_interrupt_reg32;\n\tvoid *ioarrin_reg;\n\tvoid *sense_uproc_interrupt_reg;\n\tvoid *sense_uproc_interrupt_reg32;\n\tvoid *set_uproc_interrupt_reg;\n\tvoid *set_uproc_interrupt_reg32;\n\tvoid *clr_uproc_interrupt_reg;\n\tvoid *clr_uproc_interrupt_reg32;\n\tvoid *init_feedback_reg;\n\tvoid *dump_addr_reg;\n\tvoid *dump_data_reg;\n\tvoid *endian_swap_reg;\n};\n\nstruct ipr_trace_entry;\n\nstruct ipr_sglist;\n\nstruct ipr_misc_cbs;\n\nstruct ipr_ioa_cfg {\n\tchar eye_catcher[8];\n\tstruct list_head queue;\n\tu8 in_reset_reload: 1;\n\tu8 in_ioa_bringdown: 1;\n\tu8 ioa_unit_checked: 1;\n\tu8 dump_taken: 1;\n\tu8 scan_enabled: 1;\n\tu8 scan_done: 1;\n\tu8 needs_hard_reset: 1;\n\tu8 dual_raid: 1;\n\tu8 needs_warm_reset: 1;\n\tu8 msi_received: 1;\n\tu8 sis64: 1;\n\tu8 dump_timeout: 1;\n\tu8 cfg_locked: 1;\n\tu8 clear_isr: 1;\n\tu8 probe_done: 1;\n\tu8 scsi_unblock: 1;\n\tu8 scsi_blocked: 1;\n\tu8 revid;\n\tlong unsigned int target_ids[64];\n\tlong unsigned int array_ids[64];\n\tlong unsigned int vset_ids[64];\n\tu16 type;\n\tu8 log_level;\n\tchar trace_start[8];\n\tstruct ipr_trace_entry *trace;\n\tatomic_t trace_index;\n\tchar cfg_table_start[8];\n\tunion {\n\t\tstruct ipr_config_table *cfg_table;\n\t\tstruct ipr_config_table64 *cfg_table64;\n\t} u;\n\tdma_addr_t cfg_table_dma;\n\tu32 cfg_table_size;\n\tu32 max_devs_supported;\n\tchar resource_table_label[8];\n\tstruct ipr_resource_entry *res_entries;\n\tstruct list_head free_res_q;\n\tstruct list_head used_res_q;\n\tchar ipr_hcam_label[8];\n\tstruct ipr_hostrcb *hostrcb[16];\n\tdma_addr_t hostrcb_dma[16];\n\tstruct list_head hostrcb_free_q;\n\tstruct list_head hostrcb_pending_q;\n\tstruct list_head hostrcb_report_q;\n\tstruct ipr_hrr_queue hrrq[16];\n\tu32 hrrq_num;\n\tatomic_t hrrq_index;\n\tu16 identify_hrrq_index;\n\tstruct ipr_bus_attributes bus_attr[16];\n\tunsigned int transop_timeout;\n\tconst struct ipr_chip_cfg_t *chip_cfg;\n\tconst struct ipr_chip_t *ipr_chip;\n\tvoid *hdw_dma_regs;\n\tlong unsigned int hdw_dma_regs_pci;\n\tvoid *ioa_mailbox;\n\tstruct ipr_interrupts regs;\n\tu16 saved_pcix_cmd_reg;\n\tu16 reset_retries;\n\tu32 errors_logged;\n\tu32 doorbell;\n\tstruct Scsi_Host *host;\n\tstruct pci_dev *pdev;\n\tstruct ipr_sglist *ucode_sglist;\n\tu8 saved_mode_page_len;\n\tstruct work_struct work_q;\n\tstruct work_struct scsi_add_work_q;\n\tstruct workqueue_struct *reset_work_q;\n\twait_queue_head_t reset_wait_q;\n\twait_queue_head_t msi_wait_q;\n\twait_queue_head_t eeh_wait_q;\n\tstruct ipr_dump *dump;\n\tenum ipr_sdt_state sdt_state;\n\tstruct ipr_misc_cbs *vpd_cbs;\n\tdma_addr_t vpd_cbs_dma;\n\tstruct dma_pool *ipr_cmd_pool;\n\tstruct ipr_cmnd *reset_cmd;\n\tint (*reset)(struct ipr_cmnd *);\n\tchar ipr_cmd_label[8];\n\tu32 max_cmds;\n\tstruct ipr_cmnd **ipr_cmnd_list;\n\tdma_addr_t *ipr_cmnd_list_dma;\n\tunsigned int nvectors;\n\tstruct {\n\t\tchar desc[22];\n\t} vectors_info[16];\n\tu32 iopoll_weight;\n};\n\nstruct ipr_ioa_vpd {\n\tstruct ipr_std_inq_data std_inq_data;\n\tu8 ascii_part_num[12];\n\tu8 reserved[40];\n\tu8 ascii_plant_code[4];\n};\n\nstruct ipr_mode_parm_hdr {\n\tu8 length;\n\tu8 medium_type;\n\tu8 device_spec_parms;\n\tu8 block_desc_len;\n};\n\nstruct ipr_mode_pages {\n\tstruct ipr_mode_parm_hdr hdr;\n\tu8 data[251];\n};\n\nstruct ipr_supported_device {\n\t__be16 data_length;\n\tu8 reserved;\n\tu8 num_records;\n\tstruct ipr_std_inq_vpids vpids;\n\tu8 reserved2[16];\n};\n\nstruct ipr_misc_cbs {\n\tstruct ipr_ioa_vpd ioa_vpd;\n\tstruct ipr_inquiry_page0 page0_data;\n\tstruct ipr_inquiry_page3 page3_data;\n\tstruct ipr_inquiry_cap cap;\n\tstruct ipr_inquiry_pageC4 pageC4_data;\n\tstruct ipr_mode_pages mode_pages;\n\tstruct ipr_supported_device supp_dev;\n};\n\nstruct ipr_mode_page_hdr {\n\tu8 ps_page_code;\n\tu8 page_length;\n};\n\nstruct ipr_mode_page24 {\n\tstruct ipr_mode_page_hdr hdr;\n\tu8 flags;\n};\n\nstruct ipr_mode_page28 {\n\tstruct ipr_mode_page_hdr hdr;\n\tu8 num_entries;\n\tu8 entry_length;\n\tstruct ipr_dev_bus_entry bus[0];\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nstruct ipr_resource_entry {\n\tu8 needs_sync_complete: 1;\n\tu8 in_erp: 1;\n\tu8 add_to_ml: 1;\n\tu8 del_from_ml: 1;\n\tu8 resetting_device: 1;\n\tu8 reset_occurred: 1;\n\tu8 raw_mode: 1;\n\tu32 bus;\n\tu32 target;\n\tu32 lun;\n\tu8 ata_class;\n\tu8 type;\n\tu16 flags;\n\tu16 res_flags;\n\tu8 qmodel;\n\tstruct ipr_std_inq_data std_inq_data;\n\t__be32 res_handle;\n\t__be64 dev_id;\n\tu64 lun_wwn;\n\tstruct scsi_lun dev_lun;\n\tu8 res_path[8];\n\tstruct ipr_ioa_cfg *ioa_cfg;\n\tstruct scsi_device *sdev;\n\tstruct list_head queue;\n};\n\nstruct ipr_ses_table_entry {\n\tchar product_id[17];\n\tchar compare_product_id_byte[17];\n\tu32 max_bus_speed_limit;\n};\n\nstruct ipr_sglist {\n\tu32 order;\n\tu32 num_sg;\n\tu32 num_dma_sg;\n\tu32 buffer_len;\n\tstruct scatterlist *scatterlist;\n};\n\nstruct ipr_software_inq_lid_info {\n\t__be32 load_id;\n\t__be32 timestamp[3];\n};\n\nstruct ipr_trace_entry {\n\tu32 time;\n\tu8 op_code;\n\tu8 ata_op_code;\n\tu8 type;\n\tu8 cmd_index;\n\t__be32 res_handle;\n\tunion {\n\t\tu32 ioasc;\n\t\tu32 add_data;\n\t\tu32 res_addr;\n\t} u;\n};\n\nstruct ipr_uc_sdt {\n\tstruct ipr_sdt_header hdr;\n\tstruct ipr_sdt_entry entry[1];\n};\n\nstruct ipr_ucode_image_header {\n\t__be32 header_length;\n\t__be32 lid_table_offset;\n\tu8 major_release;\n\tu8 card_type;\n\tu8 minor_release[2];\n\tu8 reserved[20];\n\tchar eyecatcher[16];\n\t__be32 num_lids;\n\tstruct ipr_software_inq_lid_info lid[1];\n};\n\nstruct ipstats_mib {\n\tu64 mibs[38];\n\tstruct u64_stats_sync syncp;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct udp_table;\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr_unsized *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(const struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n\tint (*ipv6_setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*ipv6_getsockopt)(struct sock *, int, int, sockptr_t, sockptr_t);\n\tint (*ipv6_dev_get_saddr)(struct net *, const struct net_device *, const struct in6_addr *, unsigned int, struct in6_addr *);\n};\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_mreq {\n\tstruct in6_addr ipv6mr_multiaddr;\n\tint ipv6mr_ifindex;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6_params {\n\t__s32 disable_ipv6;\n\t__s32 autoconf;\n};\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tunion {\n\t\tstruct in6_addr daddr;\n\t\tstruct in6_addr final;\n\t};\n\t__be32 flow_label;\n\tu32 dst_cookie;\n\tstruct ipv6_txoptions *opt;\n\ts16 hop_limit;\n\tu8 pmtudisc;\n\tu8 tclass;\n\tbool daddr_cache;\n\tu8 mcast_hops;\n\tu32 frag_size;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\tu16 srcrt: 1;\n\t\t\tu16 osrcrt: 1;\n\t\t\tu16 rxinfo: 1;\n\t\t\tu16 rxoinfo: 1;\n\t\t\tu16 rxhlim: 1;\n\t\t\tu16 rxohlim: 1;\n\t\t\tu16 hopopts: 1;\n\t\t\tu16 ohopopts: 1;\n\t\t\tu16 dstopts: 1;\n\t\t\tu16 odstopts: 1;\n\t\t\tu16 rxflow: 1;\n\t\t\tu16 rxtclass: 1;\n\t\t\tu16 rxpmtu: 1;\n\t\t\tu16 rxorigdstaddr: 1;\n\t\t\tu16 recvfragsize: 1;\n\t\t} bits;\n\t\tu16 all;\n\t} rxopt;\n\tu8 srcprefs;\n\tu8 min_hopcount;\n\t__be32 rcv_flowinfo;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n};\n\nstruct ipv6_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib6_walker w;\n\tloff_t skip;\n\tstruct fib6_table *tbl;\n\tint sernum;\n};\n\nstruct ipv6_rpl_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u32 cmpre: 4;\n\t__u32 cmpri: 4;\n\t__u32 reserved: 4;\n\t__u32 pad: 4;\n\t__u32 reserved1: 16;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_addr;\n\t\t\tstruct in6_addr addr[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\t__u8 data[0];\n\t\t};\n\t} segments;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct ipv6_saddr_dst {\n\tconst struct in6_addr *addr;\n\tint ifindex;\n\tint scope;\n\tint label;\n\tunsigned int prefs;\n};\n\nstruct ipv6_saddr_score {\n\tint rule;\n\tint addr_type;\n\tstruct inet6_ifaddr *ifa;\n\tlong unsigned int scorebits[1];\n\tint scopedist;\n\tint matchlen;\n};\n\nstruct ipv6_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u8 first_segment;\n\t__u8 flags;\n\t__u16 tag;\n\tstruct in6_addr segments[0];\n};\n\nstruct neigh_table;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_nh_release_dsts)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)(void);\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tvoid (*xfrm6_local_rxpmtu)(struct sk_buff *, u32);\n\tint (*xfrm6_udp_encap_rcv)(struct sock *, struct sk_buff *);\n\tstruct sk_buff * (*xfrm6_gro_udp_encap_rcv)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*xfrm6_rcv_encap)(struct sk_buff *, int, __be32, int);\n\tstruct neigh_table *nd_tbl;\n\tint (*ipv6_fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tstruct net_device * (*ipv6_dev_find)(struct net *, const struct in6_addr *, struct net_device *);\n\tint (*ip6_xmit)(const struct sock *, struct sk_buff *, struct flowi6 *, __u32, struct ipv6_txoptions *, int, u32);\n};\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tunion {\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct in6_addr saddr;\n\t\t\tstruct in6_addr daddr;\n\t\t} addrs;\n\t};\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct irq_affinity_devres {\n\tunsigned int count;\n\tunsigned int irq[0];\n};\n\nstruct irq_bypass_producer;\n\nstruct irq_bypass_consumer {\n\tstruct eventfd_ctx *eventfd;\n\tstruct irq_bypass_producer *producer;\n\tint (*add_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tvoid (*del_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tvoid (*stop)(struct irq_bypass_consumer *);\n\tvoid (*start)(struct irq_bypass_consumer *);\n};\n\nstruct irq_bypass_producer {\n\tstruct eventfd_ctx *eventfd;\n\tstruct irq_bypass_consumer *consumer;\n\tint irq;\n\tint (*add_consumer)(struct irq_bypass_producer *, struct irq_bypass_consumer *);\n\tvoid (*del_consumer)(struct irq_bypass_producer *, struct irq_bypass_consumer *);\n\tvoid (*stop)(struct irq_bypass_producer *);\n\tvoid (*start)(struct irq_bypass_producer *);\n};\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tvoid (*irq_pre_redirect)(struct irq_data *);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tvoid (*irq_force_complete_move)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n};\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc *);\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nstruct msi_desc;\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tunsigned int node;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n};\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tirq_hw_number_t hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_redirect {\n\tstruct irq_work work;\n\tunsigned int target_cpu;\n};\n\nstruct irqstat;\n\nstruct irqaction;\n\nstruct irq_desc {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tstruct irqstat *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tstruct irq_redirect redirect;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tstruct hlist_node resend_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_domain_ops;\n\nstruct irq_domain_chip_generic;\n\nstruct msi_parent_ops;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct mutex mutex;\n\tstruct irq_domain *root;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct device *dev;\n\tstruct device *pm_dev;\n\tstruct irq_domain *parent;\n\tconst struct msi_parent_ops *msi_parent_ops;\n\tvoid (*exit)(struct irq_domain *);\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct irq_data *revmap[0];\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tvoid (*exit)(struct irq_chip_generic *);\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct irq_domain_chip_generic_info {\n\tconst char *name;\n\tirq_flow_handler_t handler;\n\tunsigned int irqs_per_chip;\n\tunsigned int num_ct;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tint (*init)(struct irq_chip_generic *);\n\tvoid (*exit)(struct irq_chip_generic *);\n};\n\nstruct irq_domain_info {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int domain_flags;\n\tunsigned int size;\n\tirq_hw_number_t hwirq_max;\n\tint direct_max;\n\tunsigned int hwirq_base;\n\tunsigned int virq_base;\n\tenum irq_domain_bus_token bus_token;\n\tconst char *name_suffix;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tstruct device *dev;\n\tstruct irq_domain *parent;\n\tstruct irq_domain_chip_generic_info *dgc_info;\n\tint (*init)(struct irq_domain *);\n\tvoid (*exit)(struct irq_domain *);\n};\n\nstruct irq_fwspec;\n\nstruct irq_fwspec_info;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n\tint (*get_fwspec_info)(struct irq_fwspec *, struct irq_fwspec_info *);\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct irq_fwspec_info {\n\tlong unsigned int flags;\n\tconst struct cpumask *affinity;\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\nstruct irq_info {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tunion {\n\t\tvoid *dev_id;\n\t\tvoid *percpu_dev_id;\n\t};\n\tconst struct cpumask *affinity;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nstruct irqstat {\n\tunsigned int cnt;\n};\n\nstruct iso_directory_record {\n\t__u8 length[1];\n\t__u8 ext_attr_length[1];\n\t__u8 extent[8];\n\t__u8 size[8];\n\t__u8 date[7];\n\t__u8 flags[1];\n\t__u8 file_unit_size[1];\n\t__u8 interleave[1];\n\t__u8 volume_sequence_number[4];\n\t__u8 name_len[1];\n\tchar name[0];\n};\n\nstruct iso_inode_info {\n\tlong unsigned int i_iget5_block;\n\tlong unsigned int i_iget5_offset;\n\tunsigned int i_first_extent;\n\tunsigned char i_file_format;\n\tunsigned char i_format_parm[3];\n\tlong unsigned int i_next_section_block;\n\tlong unsigned int i_next_section_offset;\n\toff_t i_section_size;\n\tstruct inode vfs_inode;\n};\n\nstruct iso_primary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_supplementary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 flags[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 escape[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_volume_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2041];\n};\n\nstruct isofs_fid {\n\tu32 block;\n\tu16 offset;\n\tu16 parent_offset;\n\tu32 generation;\n\tu32 parent_block;\n\tu32 parent_generation;\n};\n\nstruct isofs_iget5_callback_data {\n\tlong unsigned int block;\n\tlong unsigned int offset;\n};\n\nstruct isofs_options {\n\tunsigned int rock: 1;\n\tunsigned int joliet: 1;\n\tunsigned int cruft: 1;\n\tunsigned int hide: 1;\n\tunsigned int showassoc: 1;\n\tunsigned int nocompress: 1;\n\tunsigned int overriderockperm: 1;\n\tunsigned int uid_set: 1;\n\tunsigned int gid_set: 1;\n\tunsigned char map;\n\tunsigned char check;\n\tunsigned int blocksize;\n\tumode_t fmode;\n\tumode_t dmode;\n\tkgid_t gid;\n\tkuid_t uid;\n\tchar *iocharset;\n\ts32 session;\n\ts32 sbsector;\n};\n\nstruct nls_table;\n\nstruct isofs_sb_info {\n\tlong unsigned int s_ninodes;\n\tlong unsigned int s_nzones;\n\tlong unsigned int s_firstdatazone;\n\tlong unsigned int s_log_zone_size;\n\tlong unsigned int s_max_size;\n\tint s_rock_offset;\n\ts32 s_sbsector;\n\tunsigned char s_joliet_level;\n\tunsigned char s_mapping;\n\tunsigned char s_check;\n\tunsigned char s_session;\n\tunsigned int s_high_sierra: 1;\n\tunsigned int s_rock: 2;\n\tunsigned int s_cruft: 1;\n\tunsigned int s_nocompress: 1;\n\tunsigned int s_hide: 1;\n\tunsigned int s_showassoc: 1;\n\tunsigned int s_overriderockperm: 1;\n\tunsigned int s_uid_set: 1;\n\tunsigned int s_gid_set: 1;\n\tumode_t s_fmode;\n\tumode_t s_dmode;\n\tkgid_t s_gid;\n\tkuid_t s_uid;\n\tstruct nls_table *s_nls_iocharset;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct iw_node_attr {\n\tstruct kobj_attribute kobj_attr;\n\tint nid;\n};\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_s journal_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong long unsigned int blocknr;\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct transaction_stats_s;\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\twait_queue_head_t j_fc_wait;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tstruct shrinker *j_shrinker;\n\tstruct percpu_counter j_checkpoint_jh_count;\n\ttransaction_t *j_shrink_transaction;\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tlong unsigned int j_fc_first;\n\tlong unsigned int j_fc_off;\n\tlong unsigned int j_fc_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\terrseq_t j_fs_dev_wb_err;\n\tunsigned int j_total_len;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tint j_transaction_overhead_buffers;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tstruct buffer_head **j_fc_wbuf;\n\tint j_wbufsize;\n\tint j_fc_wbufsize;\n\tpid_t j_last_sync_writer;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tint (*j_submit_inode_data_buffers)(struct jbd2_inode *);\n\tint (*j_finish_inode_data_buffers)(struct jbd2_inode *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\t__u32 j_csum_seed;\n\tstruct lock_class_key jbd2_trans_commit_key;\n\tvoid (*j_fc_cleanup_callback)(struct journal_s *, int, tid_t);\n\tint (*j_fc_replay_callback)(struct journal_s *, struct buffer_head *, enum passtype, int, tid_t);\n\tint (*j_bmap)(struct journal_s *, sector_t *);\n};\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__be32 s_num_fc_blks;\n\t__be32 s_head;\n\t__u32 s_padding[40];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nstruct jump_entry {\n\ts32 code;\n\ts32 target;\n\tlong int key;\n};\n\nstruct k_itimer;\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\ntypedef struct k_itimer *class_lock_timer_t;\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct ucounts *ucounts;\n};\n\nstruct signal_struct;\n\nstruct k_itimer {\n\tstruct hlist_node t_hash;\n\tstruct hlist_node list;\n\ttimer_t it_id;\n\tclockid_t it_clock;\n\tint it_sigev_notify;\n\tenum pid_type it_pid_type;\n\tstruct signal_struct *it_signal;\n\tconst struct k_clock *kclock;\n\tspinlock_t it_lock;\n\tint it_status;\n\tbool it_sig_periodic;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tunsigned int it_signal_seq;\n\tunsigned int it_sigqueue_seq;\n\tktime_t it_interval;\n\tstruct hlist_node ignored_list;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue sigq;\n\trcuref_t rcuref;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\ntypedef void __restorefn_t(void);\n\ntypedef __restorefn_t *__sigrestore_t;\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tloff_t pos_bpf_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[512];\n\tchar module_name[56];\n\tint exported;\n\tint show_value;\n};\n\nstruct kallsyms_data {\n\tlong unsigned int *addrs;\n\tconst char **syms;\n\tsize_t cnt;\n\tsize_t found;\n};\n\nstruct karatsuba_ctx {\n\tstruct karatsuba_ctx *next;\n\tmpi_ptr_t tspace;\n\tmpi_size_t tspace_size;\n\tmpi_ptr_t tp;\n\tmpi_size_t tp_size;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tint: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kcmp_epoll_slot {\n\t__u32 efd;\n\t__u32 tfd;\n\t__u32 toff;\n};\n\ntypedef void (*dm_kcopyd_notify_fn)(int, long unsigned int, void *);\n\nstruct kcopyd_job {\n\tstruct dm_kcopyd_client *kc;\n\tstruct list_head list;\n\tunsigned int flags;\n\tint read_err;\n\tlong unsigned int write_err;\n\tenum req_op op;\n\tstruct dm_io_region source;\n\tunsigned int num_dests;\n\tstruct dm_io_region dests[8];\n\tstruct page_list *pages;\n\tdm_kcopyd_notify_fn fn;\n\tvoid *context;\n\tstruct mutex lock;\n\tatomic_t sub_jobs;\n\tsector_t progress;\n\tsector_t write_offset;\n\tstruct kcopyd_job *master_job;\n};\n\nstruct kcore_list {\n\tstruct list_head list;\n\tlong unsigned int addr;\n\tsize_t size;\n\tint type;\n};\n\nstruct kcsan_scoped_access {};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tconst char *name;\n\tint exit_signal;\n\tu32 kthread: 1;\n\tu32 io_thread: 1;\n\tu32 user_worker: 1;\n\tu32 no_files: 1;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tint idle;\n\tint (*fn)(void *);\n\tvoid *fn_arg;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tunsigned int kill_seq;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[10];\n};\n\nstruct kernel_ethtool_ringparam {\n\tu32 rx_buf_len;\n\tu8 tcp_data_split;\n\tu8 tx_push;\n\tu8 rx_push;\n\tu32 cqe_size;\n\tu32 tx_push_buf_len;\n\tu32 tx_push_buf_max_len;\n\tu32 hds_thresh;\n\tu32 hds_thresh_max;\n};\n\nstruct kernel_ethtool_ts_info {\n\tu32 cmd;\n\tu32 so_timestamping;\n\tint phc_index;\n\tenum hwtstamp_provider_qualifier phc_qualifier;\n\tenum hwtstamp_source phc_source;\n\tint phc_phyindex;\n\tu32 tx_types;\n\tu32 rx_filters;\n};\n\nstruct kernel_param_ops;\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct kernel_symbol {\n\tlong unsigned int value;\n\tconst char *name;\n\tconst char *namespace;\n};\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n};\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n\tlong unsigned int rev;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_global_locks {\n\tstruct mutex open_file_mutex[1024];\n};\n\nstruct simple_xattrs {\n\tstruct rb_root rb_root;\n\trwlock_t lock;\n};\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *__parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tu64 id;\n\tvoid *priv;\n\tstruct kernfs_iattrs *iattr;\n\tstruct callback_head rcu;\n};\n\nstruct vm_operations_struct;\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct kernfs_open_node {\n\tstruct callback_head callback_head;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n\tunsigned int nr_mmapped;\n\tunsigned int nr_to_release;\n};\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n\tloff_t (*llseek)(struct kernfs_open_file *, loff_t, int);\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tspinlock_t kernfs_idr_lock;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n\tstruct rw_semaphore kernfs_rwsem;\n\tstruct rw_semaphore kernfs_iattr_rwsem;\n\tstruct rw_semaphore kernfs_supers_rwsem;\n\trwlock_t kernfs_rename_lock;\n\tstruct callback_head rcu;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct kimage;\n\nstruct kexec_buf {\n\tstruct kimage *image;\n\tvoid *buffer;\n\tlong unsigned int bufsz;\n\tlong unsigned int mem;\n\tlong unsigned int memsz;\n\tlong unsigned int buf_align;\n\tlong unsigned int buf_min;\n\tlong unsigned int buf_max;\n\tstruct page *cma;\n\tbool top_down;\n\tbool random;\n};\n\nstruct kexec_elf_info {\n\tconst char *buffer;\n\tconst struct elf64_hdr *ehdr;\n\tconst struct elf64_phdr *proghdrs;\n};\n\ntypedef int kexec_probe_t(const char *, long unsigned int);\n\ntypedef void *kexec_load_t(struct kimage *, char *, long unsigned int, char *, long unsigned int, char *, long unsigned int);\n\ntypedef int kexec_cleanup_t(void *);\n\nstruct kexec_file_ops {\n\tkexec_probe_t *probe;\n\tkexec_load_t *load;\n\tkexec_cleanup_t *cleanup;\n};\n\nstruct kexec_link_entry {\n\tconst char *target;\n\tconst char *name;\n};\n\nstruct kexec_load_limit {\n\tstruct mutex mutex;\n\tint limit;\n};\n\nstruct kexec_segment {\n\tunion {\n\t\tvoid *buf;\n\t\tvoid *kbuf;\n\t};\n\tsize_t bufsz;\n\tlong unsigned int mem;\n\tsize_t memsz;\n};\n\nstruct kexec_sha_region {\n\tlong unsigned int start;\n\tlong unsigned int len;\n};\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[6];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nstruct key_preparsed_payload {\n\tconst char *orig_description;\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\ttime64_t expiry;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct key_security_struct {\n\tu32 sid;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct {\n\t\t\tstruct {} __empty_tnode;\n\t\t\tstruct key_vector *tnode[0];\n\t\t};\n\t};\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\ttime64_t now;\n};\n\nstruct rcu_gp_oldstate {\n\tlong unsigned int rgos_norm;\n\tlong unsigned int rgos_exp;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct rcu_gp_oldstate head_free_gp_snap;\n\tstruct list_head bulk_head_free[2];\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tlong unsigned int head_gp_snap;\n\tatomic_t head_count;\n\tstruct list_head bulk_head[2];\n\tatomic_t bulk_count[2];\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\traw_spinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool initialized;\n\tstruct delayed_work page_cache_work;\n\tatomic_t backoff_page_cache_fill;\n\tatomic_t work_in_progress;\n\tstruct hrtimer hrtimer;\n\tstruct llist_head bkvcache;\n\tint nr_bkv_objs;\n};\n\nstruct kgetbmap {\n\t__s64 bmv_offset;\n\t__s64 bmv_block;\n\t__s64 bmv_length;\n\t__s32 bmv_oflags;\n};\n\nstruct mm_slot;\n\nstruct khugepaged_scan {\n\tstruct list_head mm_head;\n\tstruct mm_slot *mm_slot;\n\tlong unsigned int address;\n};\n\nstruct kimage_arch {\n\tstruct crash_mem *exclude_ranges;\n\tlong unsigned int backup_start;\n\tvoid *backup_buf;\n\tvoid *fdt;\n};\n\nstruct purgatory_info {\n\tconst Elf64_Ehdr *ehdr;\n\tElf64_Shdr *sechdrs;\n\tvoid *purgatory_buf;\n};\n\nstruct kimage {\n\tkimage_entry_t head;\n\tkimage_entry_t *entry;\n\tkimage_entry_t *last_entry;\n\tlong unsigned int start;\n\tstruct page *control_code_page;\n\tstruct page *swap_page;\n\tvoid *vmcoreinfo_data_copy;\n\tlong unsigned int nr_segments;\n\tstruct kexec_segment segment[16];\n\tstruct page *segment_cma[16];\n\tstruct list_head control_pages;\n\tstruct list_head dest_pages;\n\tstruct list_head unusable_pages;\n\tlong unsigned int control_page;\n\tunsigned int type: 1;\n\tunsigned int preserve_context: 1;\n\tunsigned int file_mode: 1;\n\tunsigned int hotplug_support: 1;\n\tunsigned int no_cma: 1;\n\tstruct kimage_arch arch;\n\tvoid *kernel_buf;\n\tlong unsigned int kernel_buf_len;\n\tvoid *initrd_buf;\n\tlong unsigned int initrd_buf_len;\n\tchar *cmdline_buf;\n\tlong unsigned int cmdline_buf_len;\n\tconst struct kexec_file_ops *fops;\n\tvoid *image_loader_data;\n\tstruct purgatory_info purgatory_info;\n\tbool force_dtb;\n\tint hp_action;\n\tint elfcorehdr_index;\n\tbool elfcorehdr_updated;\n\tvoid *ima_buffer;\n\tphys_addr_t ima_buffer_addr;\n\tsize_t ima_buffer_size;\n\tlong unsigned int ima_segment_index;\n\tbool is_ima_segment_index_set;\n\tstruct {\n\t\tstruct kexec_segment *scratch;\n\t\tphys_addr_t fdt;\n\t} kho;\n\tvoid *elf_headers;\n\tlong unsigned int elf_headers_sz;\n\tlong unsigned int elf_load_addr;\n\tlong unsigned int dm_crypt_keys_addr;\n\tlong unsigned int dm_crypt_keys_sz;\n};\n\nstruct kioctx_cpu;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct folio **ring_folios;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct folio *internal_folios[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct klistmount {\n\tu64 last_mnt_id;\n\tu64 mnt_parent_id;\n\tu64 *kmnt_ids;\n\tu32 nr_mnt_ids;\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n};\n\nstruct klistns {\n\tu64 *uns_ids;\n\tu32 nr_ns_ids;\n\tu64 last_ns_id;\n\tu64 user_ns_id;\n\tu32 ns_type;\n\tstruct user_namespace *user_ns;\n\tbool userns_capable;\n\tstruct ns_common *first_ns;\n};\n\nstruct km_event {\n\tunion {\n\t\tu32 hard;\n\t\tu32 proto;\n\t\tu32 byid;\n\t\tu32 aevent;\n\t\tu32 type;\n\t} data;\n\tu32 seq;\n\tu32 portid;\n\tu32 event;\n\tstruct net *net;\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[3];\n\tunsigned int size;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct kmap_ctrl {};\n\ntypedef struct kmem_cache *kmem_buckets[18];\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct slub_percpu_sheaves;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct slub_percpu_sheaves *cpu_sheaves;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tstruct reciprocal_value reciprocal_size;\n\tunsigned int offset;\n\tunsigned int sheaf_capacity;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tlong unsigned int random;\n\tunsigned int remote_node_defrag_ratio;\n\tunsigned int *random_seq;\n\tstruct kmem_cache_node *node[256];\n};\n\nstruct kmem_cache_args {\n\tunsigned int align;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tunsigned int freeptr_offset;\n\tbool use_freeptr_offset;\n\tvoid (*ctor)(void *);\n\tunsigned int sheaf_capacity;\n};\n\nunion kmem_cache_iter_priv {\n\tstruct bpf_iter_kmem_cache it;\n\tstruct bpf_iter_kmem_cache_kern kit;\n};\n\nstruct node_barn;\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n\tstruct node_barn *barn;\n};\n\nstruct kmem_obj_info {\n\tvoid *kp_ptr;\n\tstruct slab *kp_slab;\n\tvoid *kp_objp;\n\tlong unsigned int kp_data_offset;\n\tstruct kmem_cache *kp_slab_cache;\n\tvoid *kp_ret;\n\tvoid *kp_stack[16];\n\tvoid *kp_free_stack[16];\n};\n\nstruct kmsg_dump_detail {\n\tenum kmsg_dump_reason reason;\n\tconst char *description;\n};\n\nstruct kmsg_dump_iter {\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, struct kmsg_dump_detail *);\n\tenum kmsg_dump_reason max_reason;\n\tbool registered;\n};\n\nstruct probe;\n\nstruct kobj_map {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)(void);\n\tvoid * (*grab_current_ns)(void);\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)(void);\n\tvoid (*drop_ns)(void *);\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kpp_request;\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tstruct crypto_alg base;\n};\n\nstruct kpp_instance {\n\tvoid (*free)(struct kpp_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[48];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct kpp_alg alg;\n\t};\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct kprobe;\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct kprobe_blacklist_entry {\n\tstruct list_head list;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n};\n\nstruct prev_kprobe {\n\tstruct kprobe *kp;\n\tlong unsigned int status;\n\tlong unsigned int saved_msr;\n};\n\nstruct kprobe_ctlblk {\n\tlong unsigned int kprobe_status;\n\tlong unsigned int kprobe_saved_msr;\n\tstruct prev_kprobe prev_kprobe;\n};\n\nstruct kprobe_insn_cache {\n\tstruct mutex mutex;\n\tvoid * (*alloc)(void);\n\tvoid (*free)(void *);\n\tconst char *sym;\n\tstruct list_head pages;\n\tsize_t insn_size;\n\tint nr_garbage;\n};\n\nstruct kprobe_insn_page {\n\tstruct list_head list;\n\tkprobe_opcode_t *insns;\n\tstruct kprobe_insn_cache *cache;\n\tint nused;\n\tint ngarbage;\n\tchar slot_used[0];\n};\n\nstruct kprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n};\n\nstruct krb5_ctx {\n\tint initiate;\n\tu32 enctype;\n\tu32 flags;\n\tconst struct gss_krb5_enctype *gk5e;\n\tstruct crypto_sync_skcipher *enc;\n\tstruct crypto_sync_skcipher *seq;\n\tstruct crypto_sync_skcipher *acceptor_enc;\n\tstruct crypto_sync_skcipher *initiator_enc;\n\tstruct crypto_sync_skcipher *acceptor_enc_aux;\n\tstruct crypto_sync_skcipher *initiator_enc_aux;\n\tstruct crypto_ahash *acceptor_sign;\n\tstruct crypto_ahash *initiator_sign;\n\tstruct crypto_ahash *initiator_integ;\n\tstruct crypto_ahash *acceptor_integ;\n\tu8 Ksess[32];\n\tu8 cksum[32];\n\tatomic_t seq_send;\n\tatomic64_t seq_send64;\n\ttime64_t endtime;\n\tstruct xdr_netobj mech_used;\n};\n\nstruct kretprobe_instance;\n\ntypedef int (*kretprobe_handler_t)(struct kretprobe_instance *, struct pt_regs *);\n\nstruct rethook;\n\nstruct kretprobe {\n\tstruct kprobe kp;\n\tkretprobe_handler_t handler;\n\tkretprobe_handler_t entry_handler;\n\tint maxactive;\n\tint nmissed;\n\tsize_t data_size;\n\tstruct rethook *rh;\n};\n\nstruct kretprobe_blackpoint {\n\tconst char *name;\n\tvoid *addr;\n};\n\nstruct rethook_node {\n\tstruct callback_head rcu;\n\tstruct llist_node llist;\n\tstruct rethook *rethook;\n\tlong unsigned int ret_addr;\n\tlong unsigned int frame;\n};\n\nstruct kretprobe_instance {\n\tstruct rethook_node node;\n\tchar data[0];\n};\n\nstruct kretprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int func;\n\tlong unsigned int ret_ip;\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(const struct kobject *);\n\tconst char * (* const name)(const struct kobject *);\n\tint (* const uevent)(const struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct mm_slot {\n\tstruct hlist_node hash;\n\tstruct list_head mm_node;\n\tstruct mm_struct *mm;\n};\n\nstruct ksm_rmap_item;\n\nstruct ksm_mm_slot {\n\tstruct mm_slot slot;\n\tstruct ksm_rmap_item *rmap_list;\n};\n\nstruct ksm_next_page_arg {\n\tstruct folio *folio;\n\tstruct page *page;\n\tlong unsigned int addr;\n};\n\nstruct ksm_stable_node;\n\nstruct ksm_rmap_item {\n\tstruct ksm_rmap_item *rmap_list;\n\tunion {\n\t\tstruct anon_vma *anon_vma;\n\t\tint nid;\n\t};\n\tstruct mm_struct *mm;\n\tlong unsigned int address;\n\tunsigned int oldchecksum;\n\trmap_age_t age;\n\trmap_age_t remaining_skips;\n\tunion {\n\t\tstruct rb_node node;\n\t\tstruct {\n\t\t\tstruct ksm_stable_node *head;\n\t\t\tstruct hlist_node hlist;\n\t\t};\n\t};\n};\n\nstruct ksm_scan {\n\tstruct ksm_mm_slot *mm_slot;\n\tlong unsigned int address;\n\tstruct ksm_rmap_item **rmap_list;\n\tlong unsigned int seqnr;\n};\n\nstruct ksm_stable_node {\n\tunion {\n\t\tstruct rb_node node;\n\t\tstruct {\n\t\t\tstruct list_head *head;\n\t\t\tstruct {\n\t\t\t\tstruct hlist_node hlist_dup;\n\t\t\t\tstruct list_head list;\n\t\t\t};\n\t\t};\n\t};\n\tstruct hlist_head hlist;\n\tunion {\n\t\tlong unsigned int kpfn;\n\t\tlong unsigned int chain_prune_time;\n\t};\n\tint rmap_hlist_len;\n\tint nid;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n\tu64 change_cookie;\n\tu64 subvol;\n\tu32 dio_mem_align;\n\tu32 dio_offset_align;\n\tu32 dio_read_offset_align;\n\tu32 atomic_write_unit_min;\n\tu32 atomic_write_unit_max;\n\tu32 atomic_write_unit_max_opt;\n\tu32 atomic_write_segments_max;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n};\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\nstruct statmount {\n\t__u32 size;\n\t__u32 mnt_opts;\n\t__u64 mask;\n\t__u32 sb_dev_major;\n\t__u32 sb_dev_minor;\n\t__u64 sb_magic;\n\t__u32 sb_flags;\n\t__u32 fs_type;\n\t__u64 mnt_id;\n\t__u64 mnt_parent_id;\n\t__u32 mnt_id_old;\n\t__u32 mnt_parent_id_old;\n\t__u64 mnt_attr;\n\t__u64 mnt_propagation;\n\t__u64 mnt_peer_group;\n\t__u64 mnt_master;\n\t__u64 propagate_from;\n\t__u32 mnt_root;\n\t__u32 mnt_point;\n\t__u64 mnt_ns_id;\n\t__u32 fs_subtype;\n\t__u32 sb_source;\n\t__u32 opt_num;\n\t__u32 opt_array;\n\t__u32 opt_sec_num;\n\t__u32 opt_sec_array;\n\t__u64 supported_mask;\n\t__u32 mnt_uidmap_num;\n\t__u32 mnt_uidmap;\n\t__u32 mnt_gidmap_num;\n\t__u32 mnt_gidmap;\n\t__u64 __spare2[43];\n\tchar str[0];\n};\n\nstruct kstatmount {\n\tstruct statmount *buf;\n\tsize_t bufsize;\n\tstruct vfsmount *mnt;\n\tstruct mnt_idmap *idmap;\n\tu64 mask;\n\tstruct path root;\n\tstruct seq_file seq;\n\tstruct statmount sm;\n};\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_cc[19];\n\tcc_t c_line;\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tunsigned int node;\n\tint started;\n\tint result;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tstruct completion parked;\n\tstruct completion exited;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tchar *full_name;\n\tstruct task_struct *task;\n\tstruct list_head affinity_node;\n\tstruct cpumask *preferred_affinity;\n};\n\nstruct kthread_create_info {\n\tchar *full_name;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kunit;\n\nstruct kunit_params {\n\tconst void *params;\n\tvoid (*get_description)(struct kunit *, const void *, char *);\n\tsize_t num_params;\n\tsize_t elem_size;\n};\n\nstruct string_stream;\n\ntypedef void (*kunit_try_catch_func_t)(void *);\n\nstruct kunit_try_catch {\n\tstruct kunit *test;\n\tint try_result;\n\tkunit_try_catch_func_t try;\n\tkunit_try_catch_func_t catch;\n\tlong unsigned int timeout;\n\tvoid *context;\n};\n\nstruct kunit_loc {\n\tint line;\n\tconst char *file;\n};\n\nstruct kunit {\n\tvoid *priv;\n\tstruct kunit *parent;\n\tstruct kunit_params params_array;\n\tconst char *name;\n\tstruct string_stream *log;\n\tstruct kunit_try_catch try_catch;\n\tconst void *param_value;\n\tint param_index;\n\tspinlock_t lock;\n\tenum kunit_status status;\n\tstruct list_head resources;\n\tchar status_comment[256];\n\tstruct kunit_loc last_seen;\n};\n\nstruct kunit_attributes {\n\tenum kunit_speed speed;\n};\n\nstruct kunit_case {\n\tvoid (*run_case)(struct kunit *);\n\tconst char *name;\n\tconst void * (*generate_params)(struct kunit *, const void *, char *);\n\tstruct kunit_attributes attr;\n\tint (*param_init)(struct kunit *);\n\tvoid (*param_exit)(struct kunit *);\n\tenum kunit_status status;\n\tchar *module_name;\n\tstruct string_stream *log;\n};\n\nstruct kunit_hooks_table {\n\tvoid (*fail_current_test)(const char *, int, const char *, ...);\n\tvoid * (*get_static_stub_address)(struct kunit *, void *);\n};\n\nstruct kunit_resource;\n\ntypedef void (*kunit_resource_free_t)(struct kunit_resource *);\n\nstruct kunit_resource {\n\tvoid *data;\n\tconst char *name;\n\tkunit_resource_free_t free;\n\tstruct kref refcount;\n\tstruct list_head node;\n\tbool should_kfree;\n};\n\nstruct kunit_suite {\n\tconst char name[256];\n\tint (*suite_init)(struct kunit_suite *);\n\tvoid (*suite_exit)(struct kunit_suite *);\n\tint (*init)(struct kunit *);\n\tvoid (*exit)(struct kunit *);\n\tstruct kunit_case *test_cases;\n\tstruct kunit_attributes attr;\n\tchar status_comment[256];\n\tstruct dentry *debugfs;\n\tstruct string_stream *log;\n\tint suite_init_err;\n\tbool is_init;\n};\n\nstruct kvfree_rcu_bulk_data {\n\tstruct list_head list;\n\tstruct rcu_gp_oldstate gp_snap;\n\tlong unsigned int nr_records;\n\tvoid *records[0];\n};\n\nstruct kvm_memslots {\n\tu64 generation;\n\tatomic_long_t last_used_slot;\n\tstruct rb_root_cached hva_tree;\n\tstruct rb_root gfn_tree;\n\tstruct hlist_head id_hash[128];\n\tint node_idx;\n};\n\nstruct kvm_vm_stat_generic {\n\tu64 remote_tlb_flush;\n\tu64 remote_tlb_flush_requests;\n};\n\nstruct kvm_vm_stat {\n\tstruct kvm_vm_stat_generic generic;\n\tu64 num_2M_pages;\n\tu64 num_1G_pages;\n};\n\nstruct revmap_entry;\n\nstruct kvm_hpt_info {\n\tlong unsigned int virt;\n\tstruct revmap_entry *rev;\n\tu32 order;\n\tint cma;\n};\n\nstruct kvm_resize_hpt;\n\nstruct kvmppc_xics;\n\nstruct kvmppc_xive;\n\nstruct kvmppc_passthru_irqmap;\n\nstruct kvmppc_ops;\n\nstruct kvmppc_vcore;\n\nstruct kvm_arch {\n\tu64 lpid;\n\tunsigned int smt_mode;\n\tunsigned int emul_smt_mode;\n\tunsigned int tlb_sets;\n\tstruct kvm_hpt_info hpt;\n\tatomic64_t mmio_update;\n\tunsigned int host_lpid;\n\tlong unsigned int host_lpcr;\n\tlong unsigned int sdr1;\n\tlong unsigned int host_sdr1;\n\tlong unsigned int lpcr;\n\tlong unsigned int vrma_slb_v;\n\tint mmu_ready;\n\tatomic_t vcpus_running;\n\tu32 online_vcores;\n\tatomic_t hpte_mod_interest;\n\tcpumask_t need_tlb_flush;\n\tu8 radix;\n\tu8 fwnmi_enabled;\n\tu8 secure_guest;\n\tu8 svm_enabled;\n\tbool nested_enable;\n\tbool dawr1_enabled;\n\tpgd_t *pgtable;\n\tu64 process_table;\n\tstruct kvm_resize_hpt *resize_hpt;\n\tstruct list_head spapr_tce_tables;\n\tstruct list_head rtas_tokens;\n\tstruct mutex rtas_token_lock;\n\tlong unsigned int enabled_hcalls[5];\n\tstruct kvmppc_xics *xics;\n\tstruct kvmppc_xics *xics_device;\n\tstruct kvmppc_xive *xive;\n\tstruct {\n\t\tstruct kvmppc_xive *native;\n\t\tstruct kvmppc_xive *xics_on_xive;\n\t} xive_devices;\n\tstruct kvmppc_passthru_irqmap *pimap;\n\tstruct kvmppc_ops *kvm_ops;\n\tstruct mutex uvmem_lock;\n\tstruct list_head uvmem_pfns;\n\tstruct mutex mmu_setup_lock;\n\tu64 l1_ptcr;\n\tstruct idr kvm_nested_guest_idr;\n\tstruct kvmppc_vcore *vcores[2048];\n};\n\nstruct kvm_irq_routing_table;\n\nstruct mmu_notifier_ops;\n\nstruct mmu_notifier {\n\tstruct hlist_node hlist;\n\tconst struct mmu_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct callback_head rcu;\n\tunsigned int users;\n};\n\nstruct kvm_io_bus;\n\nstruct kvm_stat_data;\n\nstruct kvm {\n\tspinlock_t mmu_lock;\n\tstruct mutex slots_lock;\n\tstruct mutex slots_arch_lock;\n\tstruct mm_struct *mm;\n\tlong unsigned int nr_memslot_pages;\n\tstruct kvm_memslots __memslots[2];\n\tstruct kvm_memslots *memslots[1];\n\tstruct xarray vcpu_array;\n\tatomic_t nr_memslots_dirty_logging;\n\tspinlock_t mn_invalidate_lock;\n\tlong unsigned int mn_active_invalidate_count;\n\tstruct rcuwait mn_memslots_update_rcuwait;\n\tspinlock_t gpc_lock;\n\tstruct list_head gpc_list;\n\tatomic_t online_vcpus;\n\tint max_vcpus;\n\tint created_vcpus;\n\tint last_boosted_vcpu;\n\tstruct list_head vm_list;\n\tstruct mutex lock;\n\tstruct kvm_io_bus *buses[5];\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head items;\n\t\tstruct list_head resampler_list;\n\t\tstruct mutex resampler_lock;\n\t} irqfds;\n\tstruct list_head ioeventfds;\n\tstruct kvm_vm_stat stat;\n\tstruct kvm_arch arch;\n\trefcount_t users_count;\n\tstruct mutex irq_lock;\n\tstruct kvm_irq_routing_table *irq_routing;\n\tstruct hlist_head irq_ack_notifier_list;\n\tstruct mmu_notifier mmu_notifier;\n\tlong unsigned int mmu_invalidate_seq;\n\tlong int mmu_invalidate_in_progress;\n\tgfn_t mmu_invalidate_range_start;\n\tgfn_t mmu_invalidate_range_end;\n\tstruct list_head devices;\n\tu64 manual_dirty_log_protect;\n\tstruct dentry *debugfs_dentry;\n\tstruct kvm_stat_data **debugfs_stat_data;\n\tstruct srcu_struct srcu;\n\tstruct srcu_struct irq_srcu;\n\tpid_t userspace_pid;\n\tbool override_halt_poll_ns;\n\tunsigned int max_halt_poll_ns;\n\tu32 dirty_ring_size;\n\tbool dirty_ring_with_bitmap;\n\tbool vm_bugged;\n\tbool vm_dead;\n\tchar stats_id[48];\n};\n\nstruct kvm_arch_memory_slot {\n\tlong unsigned int *rmap;\n};\n\nstruct kvm_debug_exit_arch {\n\t__u64 address;\n\t__u32 status;\n\t__u32 reserved;\n};\n\nstruct kvm_device_ops;\n\nstruct kvm_device {\n\tconst struct kvm_device_ops *ops;\n\tstruct kvm *kvm;\n\tvoid *private;\n\tstruct list_head vm_node;\n};\n\nstruct kvm_device_attr {\n\t__u32 flags;\n\t__u32 group;\n\t__u64 attr;\n\t__u64 addr;\n};\n\nstruct kvm_device_ops {\n\tconst char *name;\n\tint (*create)(struct kvm_device *, u32);\n\tvoid (*init)(struct kvm_device *);\n\tvoid (*destroy)(struct kvm_device *);\n\tvoid (*release)(struct kvm_device *);\n\tint (*set_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*get_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tint (*has_attr)(struct kvm_device *, struct kvm_device_attr *);\n\tlong int (*ioctl)(struct kvm_device *, unsigned int, long unsigned int);\n\tint (*mmap)(struct kvm_device *, struct vm_area_struct *);\n};\n\nstruct kvm_dirty_gfn {\n\t__u32 flags;\n\t__u32 slot;\n\t__u64 offset;\n};\n\nstruct kvm_dirty_log {\n\t__u32 slot;\n\t__u32 padding1;\n\tunion {\n\t\tvoid *dirty_bitmap;\n\t\t__u64 padding2;\n\t};\n};\n\nstruct kvm_dirty_ring {\n\tu32 dirty_index;\n\tu32 reset_index;\n\tu32 size;\n\tu32 soft_limit;\n\tstruct kvm_dirty_gfn *dirty_gfns;\n\tint index;\n};\n\nstruct kvm_exit_snp_req_certs {\n\t__u64 gpa;\n\t__u64 npages;\n\t__u64 ret;\n};\n\nunion kvm_mmu_notifier_arg {\n\tlong unsigned int attributes;\n};\n\nstruct kvm_memory_slot;\n\nstruct kvm_gfn_range {\n\tstruct kvm_memory_slot *slot;\n\tgfn_t start;\n\tgfn_t end;\n\tunion kvm_mmu_notifier_arg arg;\n\tenum kvm_gfn_range_filter attr_filter;\n\tbool may_block;\n\tbool lockless;\n};\n\nstruct kvm_hyperv_exit {\n\t__u32 type;\n\t__u32 pad1;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 evt_page;\n\t\t\t__u64 msg_page;\n\t\t} synic;\n\t\tstruct {\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[2];\n\t\t} hcall;\n\t\tstruct {\n\t\t\t__u32 msr;\n\t\t\t__u32 pad2;\n\t\t\t__u64 control;\n\t\t\t__u64 status;\n\t\t\t__u64 send_page;\n\t\t\t__u64 recv_page;\n\t\t\t__u64 pending_page;\n\t\t} syndbg;\n\t} u;\n};\n\nstruct kvm_io_device;\n\nstruct kvm_io_range {\n\tgpa_t addr;\n\tint len;\n\tstruct kvm_io_device *dev;\n};\n\nstruct kvm_io_bus {\n\tint dev_count;\n\tint ioeventfd_count;\n\tstruct callback_head rcu;\n\tstruct kvm_io_range range[0];\n};\n\nstruct kvm_memory_slot {\n\tstruct hlist_node id_node[2];\n\tstruct interval_tree_node hva_node[2];\n\tstruct rb_node gfn_node[2];\n\tgfn_t base_gfn;\n\tlong unsigned int npages;\n\tlong unsigned int *dirty_bitmap;\n\tstruct kvm_arch_memory_slot arch;\n\tlong unsigned int userspace_addr;\n\tu32 flags;\n\tshort int id;\n\tu16 as_id;\n};\n\nstruct kvm_mmio_fragment {\n\tgpa_t gpa;\n\tvoid *data;\n\tunsigned int len;\n};\n\nstruct kvm_nested_guest {\n\tstruct kvm *l1_host;\n\tint l1_lpid;\n\tint shadow_lpid;\n\tpgd_t *shadow_pgtable;\n\tu64 l1_gr_to_hr;\n\tu64 process_table;\n\tlong int refcnt;\n\tstruct mutex tlb_lock;\n\tstruct kvm_nested_guest *next;\n\tcpumask_t need_tlb_flush;\n\tshort int prev_cpu[2048];\n\tu8 radix;\n};\n\nstruct kvm_ppc_mmuv3_cfg {\n\t__u64 flags;\n\t__u64 process_table;\n};\n\nstruct kvm_ppc_one_page_size {\n\t__u32 page_shift;\n\t__u32 pte_enc;\n};\n\nstruct kvm_ppc_one_seg_page_size {\n\t__u32 page_shift;\n\t__u32 slb_enc;\n\tstruct kvm_ppc_one_page_size enc[8];\n};\n\nstruct kvm_ppc_radix_geom {\n\t__u8 page_shift;\n\t__u8 level_bits[4];\n\t__u8 pad[3];\n};\n\nstruct kvm_ppc_rmmu_info {\n\tstruct kvm_ppc_radix_geom geometries[8];\n\t__u32 ap_encodings[8];\n};\n\nstruct kvm_ppc_smmu_info {\n\t__u64 flags;\n\t__u32 slb_size;\n\t__u16 data_keys;\n\t__u16 instr_keys;\n\tstruct kvm_ppc_one_seg_page_size sps[8];\n};\n\nstruct kvm_xen_exit {\n\t__u32 type;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 longmode;\n\t\t\t__u32 cpl;\n\t\t\t__u64 input;\n\t\t\t__u64 result;\n\t\t\t__u64 params[6];\n\t\t} hcall;\n\t} u;\n};\n\nstruct kvm_sync_regs {};\n\nstruct kvm_run {\n\t__u8 request_interrupt_window;\n\t__u8 immediate_exit__unsafe;\n\t__u8 padding1[6];\n\t__u32 exit_reason;\n\t__u8 ready_for_interrupt_injection;\n\t__u8 if_flag;\n\t__u16 flags;\n\t__u64 cr8;\n\t__u64 apic_base;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 hardware_exit_reason;\n\t\t} hw;\n\t\tstruct {\n\t\t\t__u64 hardware_entry_failure_reason;\n\t\t\t__u32 cpu;\n\t\t} fail_entry;\n\t\tstruct {\n\t\t\t__u32 exception;\n\t\t\t__u32 error_code;\n\t\t} ex;\n\t\tstruct {\n\t\t\t__u8 direction;\n\t\t\t__u8 size;\n\t\t\t__u16 port;\n\t\t\t__u32 count;\n\t\t\t__u64 data_offset;\n\t\t} io;\n\t\tstruct {\n\t\t\tstruct kvm_debug_exit_arch arch;\n\t\t} debug;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} mmio;\n\t\tstruct {\n\t\t\t__u64 phys_addr;\n\t\t\t__u8 data[8];\n\t\t\t__u32 len;\n\t\t\t__u8 is_write;\n\t\t} iocsr_io;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u64 ret;\n\t\t\tunion {\n\t\t\t\t__u64 flags;\n\t\t\t};\n\t\t} hypercall;\n\t\tstruct {\n\t\t\t__u64 rip;\n\t\t\t__u32 is_write;\n\t\t\t__u32 pad;\n\t\t} tpr_access;\n\t\tstruct {\n\t\t\t__u8 icptcode;\n\t\t\t__u16 ipa;\n\t\t\t__u32 ipb;\n\t\t} s390_sieic;\n\t\t__u64 s390_reset_flags;\n\t\tstruct {\n\t\t\t__u64 trans_exc_code;\n\t\t\t__u32 pgm_code;\n\t\t} s390_ucontrol;\n\t\tstruct {\n\t\t\t__u32 dcrn;\n\t\t\t__u32 data;\n\t\t\t__u8 is_write;\n\t\t} dcr;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 data[16];\n\t\t} internal;\n\t\tstruct {\n\t\t\t__u32 suberror;\n\t\t\t__u32 ndata;\n\t\t\t__u64 flags;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u8 insn_size;\n\t\t\t\t\t__u8 insn_bytes[15];\n\t\t\t\t};\n\t\t\t};\n\t\t} emulation_failure;\n\t\tstruct {\n\t\t\t__u64 gprs[32];\n\t\t} osi;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 ret;\n\t\t\t__u64 args[9];\n\t\t} papr_hcall;\n\t\tstruct {\n\t\t\t__u16 subchannel_id;\n\t\t\t__u16 subchannel_nr;\n\t\t\t__u32 io_int_parm;\n\t\t\t__u32 io_int_word;\n\t\t\t__u32 ipb;\n\t\t\t__u8 dequeued;\n\t\t} s390_tsch;\n\t\tstruct {\n\t\t\t__u32 epr;\n\t\t} epr;\n\t\tstruct {\n\t\t\t__u32 type;\n\t\t\t__u32 ndata;\n\t\t\tunion {\n\t\t\t\t__u64 data[16];\n\t\t\t};\n\t\t} system_event;\n\t\tstruct {\n\t\t\t__u64 addr;\n\t\t\t__u8 ar;\n\t\t\t__u8 reserved;\n\t\t\t__u8 fc;\n\t\t\t__u8 sel1;\n\t\t\t__u16 sel2;\n\t\t} s390_stsi;\n\t\tstruct {\n\t\t\t__u8 vector;\n\t\t} eoi;\n\t\tstruct kvm_hyperv_exit hyperv;\n\t\tstruct {\n\t\t\t__u64 esr_iss;\n\t\t\t__u64 fault_ipa;\n\t\t} arm_nisv;\n\t\tstruct {\n\t\t\t__u8 error;\n\t\t\t__u8 pad[7];\n\t\t\t__u32 reason;\n\t\t\t__u32 index;\n\t\t\t__u64 data;\n\t\t} msr;\n\t\tstruct kvm_xen_exit xen;\n\t\tstruct {\n\t\t\tlong unsigned int extension_id;\n\t\t\tlong unsigned int function_id;\n\t\t\tlong unsigned int args[6];\n\t\t\tlong unsigned int ret[2];\n\t\t} riscv_sbi;\n\t\tstruct {\n\t\t\tlong unsigned int csr_num;\n\t\t\tlong unsigned int new_value;\n\t\t\tlong unsigned int write_mask;\n\t\t\tlong unsigned int ret_value;\n\t\t} riscv_csr;\n\t\tstruct {\n\t\t\t__u32 flags;\n\t\t} notify;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 gpa;\n\t\t\t__u64 size;\n\t\t} memory_fault;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 nr;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 data[5];\n\t\t\t\t} unknown;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 gpa;\n\t\t\t\t\t__u64 size;\n\t\t\t\t} get_quote;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 leaf;\n\t\t\t\t\t__u64 r11;\n\t\t\t\t\t__u64 r12;\n\t\t\t\t\t__u64 r13;\n\t\t\t\t\t__u64 r14;\n\t\t\t\t} get_tdvmcall_info;\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 ret;\n\t\t\t\t\t__u64 vector;\n\t\t\t\t} setup_event_notify;\n\t\t\t};\n\t\t} tdx;\n\t\tstruct {\n\t\t\t__u64 flags;\n\t\t\t__u64 esr;\n\t\t\t__u64 gva;\n\t\t\t__u64 gpa;\n\t\t} arm_sea;\n\t\tstruct kvm_exit_snp_req_certs snp_req_certs;\n\t\tchar padding[256];\n\t};\n\t__u64 kvm_valid_regs;\n\t__u64 kvm_dirty_regs;\n\tunion {\n\t\tstruct kvm_sync_regs regs;\n\t\tchar padding[2048];\n\t} s;\n};\n\nstruct kvm_split_mode {\n\tlong unsigned int rpr;\n\tlong unsigned int pmmar;\n\tlong unsigned int ldbar;\n\tu8 subcore_size;\n\tu8 do_nap;\n\tu8 napped[8];\n\tstruct kvmppc_vcore *vc[4];\n};\n\nstruct kvm_sregs {\n\t__u32 pvr;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 sdr1;\n\t\t\tstruct {\n\t\t\t\tstruct {\n\t\t\t\t\t__u64 slbe;\n\t\t\t\t\t__u64 slbv;\n\t\t\t\t} slb[64];\n\t\t\t} ppc64;\n\t\t\tstruct {\n\t\t\t\t__u32 sr[16];\n\t\t\t\t__u64 ibat[8];\n\t\t\t\t__u64 dbat[8];\n\t\t\t} ppc32;\n\t\t} s;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\t__u32 features;\n\t\t\t\t\t__u32 svr;\n\t\t\t\t\t__u64 mcar;\n\t\t\t\t\t__u32 hid0;\n\t\t\t\t\t__u32 pid1;\n\t\t\t\t\t__u32 pid2;\n\t\t\t\t} fsl;\n\t\t\t\t__u8 pad[256];\n\t\t\t} impl;\n\t\t\t__u32 features;\n\t\t\t__u32 impl_id;\n\t\t\t__u32 update_special;\n\t\t\t__u32 pir;\n\t\t\t__u64 sprg8;\n\t\t\t__u64 sprg9;\n\t\t\t__u64 csrr0;\n\t\t\t__u64 dsrr0;\n\t\t\t__u64 mcsrr0;\n\t\t\t__u32 csrr1;\n\t\t\t__u32 dsrr1;\n\t\t\t__u32 mcsrr1;\n\t\t\t__u32 esr;\n\t\t\t__u64 dear;\n\t\t\t__u64 ivpr;\n\t\t\t__u64 mcivpr;\n\t\t\t__u64 mcsr;\n\t\t\t__u32 tsr;\n\t\t\t__u32 tcr;\n\t\t\t__u32 decar;\n\t\t\t__u32 dec;\n\t\t\t__u64 tb;\n\t\t\t__u32 dbsr;\n\t\t\t__u32 dbcr[3];\n\t\t\t__u32 iac[4];\n\t\t\t__u32 dac[2];\n\t\t\t__u32 dvc[2];\n\t\t\t__u8 num_iac;\n\t\t\t__u8 num_dac;\n\t\t\t__u8 num_dvc;\n\t\t\t__u8 pad;\n\t\t\t__u32 epr;\n\t\t\t__u32 vrsave;\n\t\t\t__u32 epcr;\n\t\t\t__u32 mas0;\n\t\t\t__u32 mas1;\n\t\t\t__u64 mas2;\n\t\t\t__u64 mas7_3;\n\t\t\t__u32 mas4;\n\t\t\t__u32 mas6;\n\t\t\t__u32 ivor_low[16];\n\t\t\t__u32 ivor_high[18];\n\t\t\t__u32 mmucfg;\n\t\t\t__u32 eptcfg;\n\t\t\t__u32 tlbcfg[4];\n\t\t\t__u32 tlbps[4];\n\t\t\t__u32 eplc;\n\t\t\t__u32 epsc;\n\t\t} e;\n\t\t__u8 pad[1020];\n\t} u;\n};\n\nstruct kvm_stat_data {\n\tstruct kvm *kvm;\n\tconst struct _kvm_stats_desc *desc;\n\tenum kvm_stat_kind kind;\n};\n\nstruct preempt_ops;\n\nstruct preempt_notifier {\n\tstruct hlist_node link;\n\tstruct preempt_ops *ops;\n};\n\nstruct kvmppc_slb {\n\tu64 esid;\n\tu64 vsid;\n\tu64 orige;\n\tu64 origv;\n\tbool valid: 1;\n\tbool Ks: 1;\n\tbool Kp: 1;\n\tbool nx: 1;\n\tbool large: 1;\n\tbool tb: 1;\n\tbool class: 1;\n\tu8 base_page_size;\n};\n\nstruct kvm_vcpu;\n\nstruct kvmppc_pte;\n\nstruct kvmppc_mmu {\n\tvoid (*slbmte)(struct kvm_vcpu *, u64, u64);\n\tu64 (*slbmfee)(struct kvm_vcpu *, u64);\n\tu64 (*slbmfev)(struct kvm_vcpu *, u64);\n\tint (*slbfee)(struct kvm_vcpu *, gva_t, ulong *);\n\tvoid (*slbie)(struct kvm_vcpu *, u64);\n\tvoid (*slbia)(struct kvm_vcpu *);\n\tvoid (*mtsrin)(struct kvm_vcpu *, u32, ulong);\n\tu32 (*mfsrin)(struct kvm_vcpu *, u32);\n\tint (*xlate)(struct kvm_vcpu *, gva_t, struct kvmppc_pte *, bool, bool);\n\tvoid (*tlbie)(struct kvm_vcpu *, ulong, bool);\n\tint (*esid_to_vsid)(struct kvm_vcpu *, ulong, u64 *);\n\tu64 (*ea_to_vp)(struct kvm_vcpu *, gva_t, bool);\n\tbool (*is_dcbz32)(struct kvm_vcpu *);\n};\n\nstruct thread_fp_state {\n\tu64 fpr[64];\n\tu64 fpscr;\n\tlong: 64;\n};\n\nstruct thread_vr_state {\n\tvector128 vr[32];\n\tvector128 vscr;\n};\n\nstruct machine_check_event {\n\tenum MCE_Version version: 8;\n\tu8 in_use;\n\tenum MCE_Severity severity: 8;\n\tenum MCE_Initiator initiator: 8;\n\tenum MCE_ErrorType error_type: 8;\n\tenum MCE_ErrorClass error_class: 8;\n\tenum MCE_Disposition disposition: 8;\n\tbool sync_error;\n\tu16 cpu;\n\tu64 gpr3;\n\tu64 srr0;\n\tu64 srr1;\n\tunion {\n\t\tstruct {\n\t\t\tenum MCE_UeErrorType ue_error_type: 8;\n\t\t\tu8 effective_address_provided;\n\t\t\tu8 physical_address_provided;\n\t\t\tu8 ignore_event;\n\t\t\tu8 reserved_1[4];\n\t\t\tu64 effective_address;\n\t\t\tu64 physical_address;\n\t\t\tu8 reserved_2[8];\n\t\t} ue_error;\n\t\tstruct {\n\t\t\tenum MCE_SlbErrorType slb_error_type: 8;\n\t\t\tu8 effective_address_provided;\n\t\t\tu8 reserved_1[6];\n\t\t\tu64 effective_address;\n\t\t\tu8 reserved_2[16];\n\t\t} slb_error;\n\t\tstruct {\n\t\t\tenum MCE_EratErrorType erat_error_type: 8;\n\t\t\tu8 effective_address_provided;\n\t\t\tu8 reserved_1[6];\n\t\t\tu64 effective_address;\n\t\t\tu8 reserved_2[16];\n\t\t} erat_error;\n\t\tstruct {\n\t\t\tenum MCE_TlbErrorType tlb_error_type: 8;\n\t\t\tu8 effective_address_provided;\n\t\t\tu8 reserved_1[6];\n\t\t\tu64 effective_address;\n\t\t\tu8 reserved_2[16];\n\t\t} tlb_error;\n\t\tstruct {\n\t\t\tenum MCE_UserErrorType user_error_type: 8;\n\t\t\tu8 effective_address_provided;\n\t\t\tu8 reserved_1[6];\n\t\t\tu64 effective_address;\n\t\t\tu8 reserved_2[16];\n\t\t} user_error;\n\t\tstruct {\n\t\t\tenum MCE_RaErrorType ra_error_type: 8;\n\t\t\tu8 effective_address_provided;\n\t\t\tu8 reserved_1[6];\n\t\t\tu64 effective_address;\n\t\t\tu8 reserved_2[16];\n\t\t} ra_error;\n\t\tstruct {\n\t\t\tenum MCE_LinkErrorType link_error_type: 8;\n\t\t\tu8 effective_address_provided;\n\t\t\tu8 reserved_1[6];\n\t\t\tu64 effective_address;\n\t\t\tu8 reserved_2[16];\n\t\t} link_error;\n\t} u;\n};\n\nstruct openpic;\n\nunion xive_tma_w01 {\n\tstruct {\n\t\tu8 nsr;\n\t\tu8 cppr;\n\t\tu8 ipb;\n\t\tu8 lsmfb;\n\t\tu8 ack;\n\t\tu8 inc;\n\t\tu8 age;\n\t\tu8 pipr;\n\t};\n\t__be64 w01;\n};\n\nstruct kvm_vcpu_arch_shared {\n\t__u64 scratch1;\n\t__u64 scratch2;\n\t__u64 scratch3;\n\t__u64 critical;\n\t__u64 sprg0;\n\t__u64 sprg1;\n\t__u64 sprg2;\n\t__u64 sprg3;\n\t__u64 srr0;\n\t__u64 srr1;\n\t__u64 dar;\n\t__u64 msr;\n\t__u32 dsisr;\n\t__u32 int_pending;\n\t__u32 sr[16];\n\t__u32 mas0;\n\t__u32 mas1;\n\t__u64 mas7_3;\n\t__u64 mas2;\n\t__u32 mas4;\n\t__u32 mas6;\n\t__u32 esr;\n\t__u32 pir;\n\t__u64 sprg4;\n\t__u64 sprg5;\n\t__u64 sprg6;\n\t__u64 sprg7;\n};\n\nstruct mmio_hpte_cache_entry {\n\tlong unsigned int hpte_v;\n\tlong unsigned int hpte_r;\n\tlong unsigned int rpte;\n\tlong unsigned int pte_index;\n\tlong unsigned int eaddr;\n\tlong unsigned int slb_v;\n\tlong int mmio_update;\n\tunsigned int slb_base_pshift;\n};\n\nstruct mmio_hpte_cache {\n\tstruct mmio_hpte_cache_entry entry[4];\n\tunsigned int index;\n};\n\nstruct kvmppc_vpa {\n\tlong unsigned int gpa;\n\tvoid *pinned_addr;\n\tvoid *pinned_end;\n\tlong unsigned int next_gpa;\n\tlong unsigned int len;\n\tu8 update_pending;\n\tbool dirty;\n};\n\nstruct kvmppc_gs_buff_info {\n\tu64 address;\n\tu64 size;\n};\n\nstruct kvmhv_nestedv2_config {\n\tstruct kvmppc_gs_buff_info vcpu_run_output_cfg;\n\tstruct kvmppc_gs_buff_info vcpu_run_input_cfg;\n\tu64 vcpu_run_output_size;\n};\n\nstruct kvmppc_gs_bitmap {\n\tlong unsigned int bitmap[3];\n};\n\nstruct kvmppc_gs_buff;\n\nstruct kvmppc_gs_msg;\n\nstruct kvmhv_nestedv2_io {\n\tstruct kvmhv_nestedv2_config cfg;\n\tstruct kvmppc_gs_buff *vcpu_run_output;\n\tstruct kvmppc_gs_buff *vcpu_run_input;\n\tstruct kvmppc_gs_msg *vcpu_message;\n\tstruct kvmppc_gs_msg *vcore_message;\n\tstruct kvmppc_gs_bitmap valids;\n};\n\nstruct kvmppc_vcpu_book3s;\n\nstruct kvmppc_icp;\n\nstruct kvmppc_xive_vcpu;\n\nstruct kvm_vcpu_arch {\n\tulong host_stack;\n\tu32 host_pid;\n\tstruct kvmppc_slb slb[64];\n\tint slb_max;\n\tint slb_nr;\n\tstruct kvmppc_mmu mmu;\n\tstruct kvmppc_vcpu_book3s *book3s;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pt_regs regs;\n\tstruct thread_fp_state fp;\n\tstruct thread_vr_state vr;\n\tu32 qpr[32];\n\tulong tar;\n\tulong hflags;\n\tulong guest_owned_ext;\n\tulong purr;\n\tulong spurr;\n\tulong ic;\n\tulong dscr;\n\tulong amr;\n\tulong uamor;\n\tulong iamr;\n\tu32 ctrl;\n\tu32 dabrx;\n\tulong dabr;\n\tulong dawr0;\n\tulong dawrx0;\n\tulong dawr1;\n\tulong dawrx1;\n\tulong dexcr;\n\tulong hashkeyr;\n\tulong hashpkeyr;\n\tulong ciabr;\n\tulong cfar;\n\tulong ppr;\n\tu32 pspb;\n\tu8 load_ebb;\n\tu8 load_tm;\n\tulong fscr;\n\tulong shadow_fscr;\n\tulong ebbhr;\n\tulong ebbrr;\n\tulong bescr;\n\tulong csigr;\n\tulong tacr;\n\tulong tcscr;\n\tulong acop;\n\tulong wort;\n\tulong tid;\n\tulong psscr;\n\tulong hfscr;\n\tulong shadow_srr1;\n\tu32 vrsave;\n\tu32 mmucr;\n\tulong shadow_msr;\n\tulong csrr0;\n\tulong csrr1;\n\tulong dsrr0;\n\tulong dsrr1;\n\tulong mcsrr0;\n\tulong mcsrr1;\n\tulong mcsr;\n\tulong dec;\n\tu64 entry_tb;\n\tu64 entry_vtb;\n\tu64 entry_ic;\n\tu32 tcr;\n\tulong tsr;\n\tu32 ivor[64];\n\tulong ivpr;\n\tu32 pvr;\n\tu32 shadow_pid;\n\tu32 shadow_pid1;\n\tu32 pid;\n\tu32 swap_pid;\n\tu32 ccr0;\n\tu32 ccr1;\n\tu32 dbsr;\n\tu64 mmcr[4];\n\tu64 mmcra;\n\tu64 mmcrs;\n\tu32 pmc[8];\n\tu32 spmc[2];\n\tu64 siar;\n\tu64 sdar;\n\tu64 sier[3];\n\tu64 tfhar;\n\tu64 texasr;\n\tu64 tfiar;\n\tu64 orig_texasr;\n\tu32 cr_tm;\n\tu64 xer_tm;\n\tu64 lr_tm;\n\tu64 ctr_tm;\n\tu64 amr_tm;\n\tu64 ppr_tm;\n\tu64 dscr_tm;\n\tu64 tar_tm;\n\tulong gpr_tm[32];\n\tlong: 64;\n\tstruct thread_fp_state fp_tm;\n\tstruct thread_vr_state vr_tm;\n\tu32 vrsave_tm;\n\tulong fault_dar;\n\tu32 fault_dsisr;\n\tlong unsigned int intr_msr;\n\tulong fault_gpa;\n\tgpa_t paddr_accessed;\n\tgva_t vaddr_accessed;\n\tpgd_t *pgdir;\n\tu16 io_gpr;\n\tu8 mmio_host_swabbed;\n\tu8 mmio_sign_extend;\n\tu8 mmio_sp64_extend;\n\tu8 mmio_vsx_copy_nums;\n\tu8 mmio_vsx_offset;\n\tu8 mmio_vmx_copy_nums;\n\tu8 mmio_vmx_offset;\n\tu8 mmio_copy_type;\n\tu8 osi_needed;\n\tu8 osi_enabled;\n\tu8 papr_enabled;\n\tu8 watchdog_enabled;\n\tu8 sane;\n\tu8 cpu_type;\n\tu8 hcall_needed;\n\tu8 epr_flags;\n\tu8 epr_needed;\n\tu8 external_oneshot;\n\tu32 cpr0_cfgaddr;\n\tstruct hrtimer dec_timer;\n\tu64 dec_jiffies;\n\tu64 dec_expires;\n\tlong unsigned int pending_exceptions;\n\tu8 ceded;\n\tu8 prodded;\n\tu8 doorbell_request;\n\tu8 irq_pending;\n\tlong unsigned int last_inst;\n\tstruct rcuwait wait;\n\tstruct rcuwait *waitp;\n\tstruct kvmppc_vcore *vcore;\n\tint ret;\n\tint trap;\n\tint state;\n\tint ptid;\n\tint thread_cpu;\n\tint prev_cpu;\n\tbool timer_running;\n\twait_queue_head_t cpu_run;\n\tstruct machine_check_event mce_evt;\n\tstruct kvm_vcpu_arch_shared *shared;\n\tlong unsigned int magic_page_pa;\n\tlong unsigned int magic_page_ea;\n\tbool disable_kernel_nx;\n\tint irq_type;\n\tint irq_cpu_id;\n\tstruct openpic *mpic;\n\tstruct kvmppc_icp *icp;\n\tstruct kvmppc_xive_vcpu *xive_vcpu;\n\t__be32 xive_cam_word;\n\tu8 xive_pushed;\n\tu8 xive_esc_on;\n\tunion xive_tma_w01 xive_saved_state;\n\tu64 xive_esc_raddr;\n\tu64 xive_esc_vaddr;\n\tstruct kvm_vcpu_arch_shared shregs;\n\tstruct mmio_hpte_cache mmio_cache;\n\tlong unsigned int pgfault_addr;\n\tlong int pgfault_index;\n\tlong unsigned int pgfault_hpte[2];\n\tstruct mmio_hpte_cache_entry *pgfault_cache;\n\tstruct task_struct *run_task;\n\tspinlock_t vpa_update_lock;\n\tstruct kvmppc_vpa vpa;\n\tstruct kvmppc_vpa dtl;\n\tstruct dtl_entry *dtl_ptr;\n\tlong unsigned int dtl_index;\n\tu64 stolen_logged;\n\tstruct kvmppc_vpa slb_shadow;\n\tspinlock_t tbacct_lock;\n\tu64 busy_stolen;\n\tu64 busy_preempt;\n\tu64 emul_inst;\n\tu32 online;\n\tu64 hfscr_permitted;\n\tstruct kvm_nested_guest *nested;\n\tu64 nested_hfscr;\n\tu32 nested_vcpu_id;\n\tgpa_t nested_io_gpr;\n\tstruct kvmhv_nestedv2_io nestedv2_io;\n\tu64 l1_to_l2_cs;\n\tu64 l2_to_l1_cs;\n\tu64 l2_runtime_agg;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kvm_vcpu_stat_generic {\n\tu64 halt_successful_poll;\n\tu64 halt_attempted_poll;\n\tu64 halt_poll_invalid;\n\tu64 halt_wakeup;\n\tu64 halt_poll_success_ns;\n\tu64 halt_poll_fail_ns;\n\tu64 halt_wait_ns;\n\tu64 halt_poll_success_hist[32];\n\tu64 halt_poll_fail_hist[32];\n\tu64 halt_wait_hist[32];\n\tu64 blocking;\n};\n\nstruct kvm_vcpu_stat {\n\tstruct kvm_vcpu_stat_generic generic;\n\tu64 sum_exits;\n\tu64 mmio_exits;\n\tu64 signal_exits;\n\tu64 light_exits;\n\tu64 itlb_real_miss_exits;\n\tu64 itlb_virt_miss_exits;\n\tu64 dtlb_real_miss_exits;\n\tu64 dtlb_virt_miss_exits;\n\tu64 syscall_exits;\n\tu64 isi_exits;\n\tu64 dsi_exits;\n\tu64 emulated_inst_exits;\n\tu64 dec_exits;\n\tu64 ext_intr_exits;\n\tu64 halt_successful_wait;\n\tu64 dbell_exits;\n\tu64 gdbell_exits;\n\tu64 ld;\n\tu64 st;\n\tu64 pf_storage;\n\tu64 pf_instruc;\n\tu64 sp_storage;\n\tu64 sp_instruc;\n\tu64 queue_intr;\n\tu64 ld_slow;\n\tu64 st_slow;\n\tu64 pthru_all;\n\tu64 pthru_host;\n\tu64 pthru_bad_aff;\n};\n\nstruct kvm_vcpu {\n\tstruct kvm *kvm;\n\tstruct preempt_notifier preempt_notifier;\n\tint cpu;\n\tint vcpu_id;\n\tint vcpu_idx;\n\tint ____srcu_idx;\n\tint mode;\n\tu64 requests;\n\tlong unsigned int guest_debug;\n\tstruct mutex mutex;\n\tstruct kvm_run *run;\n\tstruct pid *pid;\n\trwlock_t pid_lock;\n\tint sigset_active;\n\tsigset_t sigset;\n\tunsigned int halt_poll_ns;\n\tbool valid_wakeup;\n\tint mmio_needed;\n\tint mmio_read_completed;\n\tint mmio_is_write;\n\tint mmio_cur_fragment;\n\tint mmio_nr_fragments;\n\tstruct kvm_mmio_fragment mmio_fragments[2];\n\tbool wants_to_run;\n\tbool preempted;\n\tbool ready;\n\tbool scheduled_out;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct kvm_vcpu_arch arch;\n\tstruct kvm_vcpu_stat stat;\n\tchar stats_id[48];\n\tstruct kvm_dirty_ring dirty_ring;\n\tstruct kvm_memory_slot *last_used_slot;\n\tu64 last_used_slot_gen;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kvmppc_bat {\n\tu64 raw;\n\tu32 bepi;\n\tu32 bepi_mask;\n\tu32 brpn;\n\tu8 wimg;\n\tu8 pp;\n\tbool vs: 1;\n\tbool vp: 1;\n};\n\nstruct kvmppc_gs_header;\n\nstruct kvmppc_gs_buff {\n\tsize_t capacity;\n\tsize_t len;\n\tlong unsigned int guest_id;\n\tlong unsigned int vcpu_id;\n\tstruct kvmppc_gs_header *hdr;\n};\n\nstruct kvmppc_gs_elem {\n\t__be16 iden;\n\t__be16 len;\n\tchar data[0];\n};\n\nstruct kvmppc_gs_header {\n\t__be32 nelems;\n\tchar data[0];\n};\n\nstruct kvmppc_gs_msg_ops;\n\nstruct kvmppc_gs_msg {\n\tstruct kvmppc_gs_bitmap bitmap;\n\tstruct kvmppc_gs_msg_ops *ops;\n\tlong unsigned int flags;\n\tvoid *data;\n};\n\nstruct kvmppc_gs_msg_ops {\n\tsize_t (*get_size)(struct kvmppc_gs_msg *);\n\tint (*fill_info)(struct kvmppc_gs_buff *, struct kvmppc_gs_msg *);\n\tint (*refresh_info)(struct kvmppc_gs_msg *, struct kvmppc_gs_buff *);\n};\n\nstruct kvmppc_gs_parser {\n\tstruct kvmppc_gs_bitmap iterator;\n\tstruct kvmppc_gs_elem *gses[182];\n};\n\nstruct kvmppc_gs_part_table {\n\tu64 address;\n\tu64 ea_bits;\n\tu64 gpd_size;\n};\n\nstruct kvmppc_gs_proc_table {\n\tu64 address;\n\tu64 gpd_size;\n};\n\nunion kvmppc_rm_state {\n\tlong unsigned int raw;\n\tstruct {\n\t\tu32 in_host;\n\t\tu32 rm_action;\n\t};\n};\n\nstruct kvmppc_host_rm_core {\n\tunion kvmppc_rm_state rm_state;\n\tvoid *rm_data;\n\tchar pad[112];\n};\n\nstruct kvmppc_host_rm_ops {\n\tstruct kvmppc_host_rm_core *rm_core;\n\tvoid (*vcpu_kick)(struct kvm_vcpu *);\n};\n\nstruct kvmppc_host_state {\n\tulong host_r1;\n\tulong host_r2;\n\tulong host_msr;\n\tulong vmhandler;\n\tulong scratch0;\n\tulong scratch1;\n\tulong scratch2;\n\tu8 in_guest;\n\tu8 restore_hid5;\n\tu8 napping;\n\tu8 hwthread_req;\n\tu8 hwthread_state;\n\tu8 host_ipi;\n\tu8 ptid;\n\tu8 fake_suspend;\n\tstruct kvm_vcpu *kvm_vcpu;\n\tstruct kvmppc_vcore *kvm_vcore;\n\tvoid *xics_phys;\n\tvoid *xive_tima_phys;\n\tvoid *xive_tima_virt;\n\tu32 saved_xirr;\n\tu64 dabr;\n\tu64 host_mmcr[7];\n\tu32 host_pmc[8];\n\tu64 host_purr;\n\tu64 host_spurr;\n\tu64 host_dscr;\n\tu64 dec_expires;\n\tstruct kvm_split_mode *kvm_split_mode;\n\tu64 cfar;\n\tu64 ppr;\n\tu64 host_fscr;\n};\n\nunion kvmppc_icp_state {\n\tlong unsigned int raw;\n\tstruct {\n\t\tu8 out_ee: 1;\n\t\tu8 need_resend: 1;\n\t\tu8 cppr;\n\t\tu8 mfrr;\n\t\tu8 pending_pri;\n\t\tu32 xisr;\n\t};\n};\n\nstruct kvmppc_icp {\n\tstruct kvm_vcpu *vcpu;\n\tlong unsigned int server_num;\n\tunion kvmppc_icp_state state;\n\tlong unsigned int resend_map[16];\n\tu32 rm_action;\n\tstruct kvm_vcpu *rm_kick_target;\n\tstruct kvmppc_icp *rm_resend_icp;\n\tu32 rm_reject;\n\tu32 rm_eoied_irq;\n\tlong unsigned int n_rm_kick_vcpu;\n\tlong unsigned int n_rm_check_resend;\n\tlong unsigned int n_rm_notify_eoi;\n\tlong unsigned int n_check_resend;\n\tlong unsigned int n_reject;\n\tunion kvmppc_icp_state rm_dbgstate;\n\tstruct kvm_vcpu *rm_dbgtgt;\n};\n\nstruct kvmppc_ics {\n\tarch_spinlock_t lock;\n\tu16 icsid;\n\tstruct ics_irq_state irq_state[1024];\n};\n\nstruct kvmppc_irq_map {\n\tu32 r_hwirq;\n\tu32 v_hwirq;\n\tstruct irq_desc *desc;\n};\n\nunion kvmppc_one_reg {\n\tu32 wval;\n\tu64 dval;\n\tvector128 vval;\n\tu64 vsxval[2];\n\tu32 vsx32val[4];\n\tu16 vsx16val[8];\n\tu8 vsx8val[16];\n\tstruct {\n\t\tu64 addr;\n\t\tu64 length;\n\t} vpaval;\n\tu64 xive_timaval[2];\n};\n\nstruct kvmppc_ops {\n\tstruct module *owner;\n\tint (*get_sregs)(struct kvm_vcpu *, struct kvm_sregs *);\n\tint (*set_sregs)(struct kvm_vcpu *, struct kvm_sregs *);\n\tint (*get_one_reg)(struct kvm_vcpu *, u64, union kvmppc_one_reg *);\n\tint (*set_one_reg)(struct kvm_vcpu *, u64, union kvmppc_one_reg *);\n\tvoid (*vcpu_load)(struct kvm_vcpu *, int);\n\tvoid (*vcpu_put)(struct kvm_vcpu *);\n\tvoid (*inject_interrupt)(struct kvm_vcpu *, int, u64);\n\tvoid (*set_msr)(struct kvm_vcpu *, u64);\n\tint (*vcpu_run)(struct kvm_vcpu *);\n\tint (*vcpu_create)(struct kvm_vcpu *);\n\tvoid (*vcpu_free)(struct kvm_vcpu *);\n\tint (*check_requests)(struct kvm_vcpu *);\n\tint (*get_dirty_log)(struct kvm *, struct kvm_dirty_log *);\n\tvoid (*flush_memslot)(struct kvm *, struct kvm_memory_slot *);\n\tint (*prepare_memory_region)(struct kvm *, const struct kvm_memory_slot *, struct kvm_memory_slot *, enum kvm_mr_change);\n\tvoid (*commit_memory_region)(struct kvm *, struct kvm_memory_slot *, const struct kvm_memory_slot *, enum kvm_mr_change);\n\tbool (*unmap_gfn_range)(struct kvm *, struct kvm_gfn_range *);\n\tbool (*age_gfn)(struct kvm *, struct kvm_gfn_range *);\n\tbool (*test_age_gfn)(struct kvm *, struct kvm_gfn_range *);\n\tvoid (*free_memslot)(struct kvm_memory_slot *);\n\tint (*init_vm)(struct kvm *);\n\tvoid (*destroy_vm)(struct kvm *);\n\tint (*get_smmu_info)(struct kvm *, struct kvm_ppc_smmu_info *);\n\tint (*emulate_op)(struct kvm_vcpu *, unsigned int, int *);\n\tint (*emulate_mtspr)(struct kvm_vcpu *, int, ulong);\n\tint (*emulate_mfspr)(struct kvm_vcpu *, int, ulong *);\n\tvoid (*fast_vcpu_kick)(struct kvm_vcpu *);\n\tint (*arch_vm_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*hcall_implemented)(long unsigned int);\n\tint (*irq_bypass_add_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tvoid (*irq_bypass_del_producer)(struct irq_bypass_consumer *, struct irq_bypass_producer *);\n\tint (*configure_mmu)(struct kvm *, struct kvm_ppc_mmuv3_cfg *);\n\tint (*get_rmmu_info)(struct kvm *, struct kvm_ppc_rmmu_info *);\n\tint (*set_smt_mode)(struct kvm *, long unsigned int, long unsigned int);\n\tvoid (*giveup_ext)(struct kvm_vcpu *, ulong);\n\tint (*enable_nested)(struct kvm *);\n\tint (*load_from_eaddr)(struct kvm_vcpu *, ulong *, void *, int);\n\tint (*store_to_eaddr)(struct kvm_vcpu *, ulong *, void *, int);\n\tint (*enable_svm)(struct kvm *);\n\tint (*svm_off)(struct kvm *);\n\tint (*enable_dawr1)(struct kvm *);\n\tbool (*hash_v3_possible)(void);\n\tint (*create_vm_debugfs)(struct kvm *);\n\tint (*create_vcpu_debugfs)(struct kvm_vcpu *, struct dentry *);\n};\n\nstruct kvmppc_passthru_irqmap {\n\tint n_mapped;\n\tstruct kvmppc_irq_map mapped[1024];\n};\n\nstruct kvmppc_pte {\n\tulong eaddr;\n\tu64 vpage;\n\tulong raddr;\n\tbool may_read: 1;\n\tbool may_write: 1;\n\tbool may_execute: 1;\n\tlong unsigned int wimg;\n\tlong unsigned int rc;\n\tu8 page_size;\n\tu8 page_shift;\n};\n\nstruct kvmppc_sid_map {\n\tu64 guest_vsid;\n\tu64 guest_esid;\n\tu64 host_vsid;\n\tbool valid: 1;\n};\n\nstruct kvmppc_vcore {\n\tint n_runnable;\n\tint num_threads;\n\tint entry_exit_map;\n\tint napping_threads;\n\tint first_vcpuid;\n\tu16 pcpu;\n\tu16 last_cpu;\n\tu8 vcore_state;\n\tu8 in_guest;\n\tstruct kvm_vcpu *runnable_threads[8];\n\tstruct list_head preempt_list;\n\tspinlock_t lock;\n\tstruct rcuwait wait;\n\tspinlock_t stoltb_lock;\n\tu64 stolen_tb;\n\tu64 preempt_tb;\n\tstruct kvm_vcpu *runner;\n\tstruct kvm *kvm;\n\tu64 tb_offset;\n\tu64 tb_offset_applied;\n\tulong lpcr;\n\tu32 arch_compat;\n\tulong pcr;\n\tulong dpdes;\n\tulong vtb;\n\tulong conferring_threads;\n\tunsigned int halt_poll_ns;\n\tatomic_t online_count;\n};\n\nstruct kvmppc_vcpu_book3s {\n\tstruct kvmppc_sid_map sid_map[512];\n\tstruct {\n\t\tu64 esid;\n\t\tu64 vsid;\n\t} slb_shadow[64];\n\tu8 slb_shadow_max;\n\tstruct kvmppc_bat ibat[8];\n\tstruct kvmppc_bat dbat[8];\n\tu64 hid[6];\n\tu64 gqr[8];\n\tu64 sdr1;\n\tu64 hior;\n\tu64 msr_mask;\n\tu64 vtb;\n\tu64 proto_vsid_first;\n\tu64 proto_vsid_max;\n\tu64 proto_vsid_next;\n\tint context_id[1];\n\tbool hior_explicit;\n\tstruct hlist_head hpte_hash_pte[8192];\n\tstruct hlist_head hpte_hash_pte_long[4096];\n\tstruct hlist_head hpte_hash_vpte[8192];\n\tstruct hlist_head hpte_hash_vpte_long[32];\n\tstruct hlist_head hpte_hash_vpte_64k[2048];\n\tint hpte_cache_count;\n\tspinlock_t mmu_lock;\n};\n\nstruct kvmppc_xics {\n\tstruct kvm *kvm;\n\tstruct kvm_device *dev;\n\tstruct dentry *dentry;\n\tu32 max_icsid;\n\tbool real_mode;\n\tbool real_mode_dbg;\n\tu32 err_noics;\n\tu32 err_noicp;\n\tstruct kvmppc_ics *ics[1024];\n};\n\nstruct kvmppc_xive_src_block;\n\nstruct kvmppc_xive_ops;\n\nstruct kvmppc_xive {\n\tstruct kvm *kvm;\n\tstruct kvm_device *dev;\n\tstruct dentry *dentry;\n\tu32 vp_base;\n\tstruct kvmppc_xive_src_block *src_blocks[1024];\n\tu32 max_sbid;\n\tu32 src_count;\n\tu32 saved_src_count;\n\tu32 delayed_irqs;\n\tu8 qmap;\n\tu32 q_order;\n\tu32 q_page_order;\n\tu8 flags;\n\tu32 nr_servers;\n\tstruct kvmppc_xive_ops *ops;\n\tstruct address_space *mapping;\n\tstruct mutex mapping_lock;\n\tstruct mutex lock;\n};\n\nstruct xive_irq_data {\n\tu64 flags;\n\tu64 eoi_page;\n\tvoid *eoi_mmio;\n\tu64 trig_page;\n\tvoid *trig_mmio;\n\tu32 esb_shift;\n\tint src_chip;\n\tu32 hw_irq;\n\tint target;\n\tbool saved_p;\n\tbool stale_p;\n};\n\nstruct kvmppc_xive_irq_state {\n\tbool valid;\n\tu32 number;\n\tu32 ipi_number;\n\tstruct xive_irq_data ipi_data;\n\tu32 pt_number;\n\tstruct xive_irq_data *pt_data;\n\tu8 guest_priority;\n\tu8 saved_priority;\n\tu32 act_server;\n\tu8 act_priority;\n\tbool in_eoi;\n\tbool old_p;\n\tbool old_q;\n\tbool lsi;\n\tbool asserted;\n\tbool in_queue;\n\tbool saved_p;\n\tbool saved_q;\n\tu8 saved_scan_prio;\n\tu32 eisn;\n};\n\nstruct kvmppc_xive_ops {\n\tint (*reset_mapped)(struct kvm *, long unsigned int);\n};\n\nstruct kvmppc_xive_src_block {\n\tarch_spinlock_t lock;\n\tu16 id;\n\tstruct kvmppc_xive_irq_state irq_state[1024];\n};\n\nstruct xive_q {\n\t__be32 *qpage;\n\tu32 msk;\n\tu32 idx;\n\tu32 toggle;\n\tu64 eoi_phys;\n\tu32 esc_irq;\n\tatomic_t count;\n\tatomic_t pending_count;\n\tu64 guest_qaddr;\n\tu32 guest_qshift;\n};\n\nstruct kvmppc_xive_vcpu {\n\tstruct kvmppc_xive *xive;\n\tstruct kvm_vcpu *vcpu;\n\tbool valid;\n\tu32 server_num;\n\tu32 vp_id;\n\tu32 vp_chip_id;\n\tu32 vp_cam;\n\tu32 vp_ipi;\n\tstruct xive_irq_data vp_ipi_data;\n\tuint8_t cppr;\n\tuint8_t hw_cppr;\n\tuint8_t mfrr;\n\tuint8_t pending;\n\tstruct xive_q queues[8];\n\tu32 esc_virq[8];\n\tchar *esc_virq_names[8];\n\tu32 delayed_irq;\n\tu64 stat_rm_h_xirr;\n\tu64 stat_rm_h_ipoll;\n\tu64 stat_rm_h_cppr;\n\tu64 stat_rm_h_eoi;\n\tu64 stat_rm_h_ipi;\n\tu64 stat_vm_h_xirr;\n\tu64 stat_vm_h_ipoll;\n\tu64 stat_vm_h_cppr;\n\tu64 stat_vm_h_eoi;\n\tu64 stat_vm_h_ipi;\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tdev_t dev;\n\tstruct sbitmap_queue domain_tokens[4];\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nstruct label_attr {\n\tu8 prefix[8];\n\tu8 version;\n\tu8 os;\n\tu8 length;\n\tu8 reserved[5];\n};\n\nstruct label {\n\tstruct label_attr attr;\n\tu8 name[239];\n\tsize_t size;\n};\n\nstruct landlock_ruleset;\n\nstruct landlock_cred_security {\n\tstruct landlock_ruleset *domain;\n\tu16 domain_exec;\n\tu8 log_subdomains_off: 1;\n} __attribute__((packed));\n\nstruct landlock_details {\n\tstruct pid *pid;\n\tuid_t uid;\n\tchar comm[16];\n\tchar exe_path[0];\n};\n\nstruct landlock_erratum {\n\tconst int abi;\n\tconst u8 number;\n};\n\nstruct landlock_file_security {\n\taccess_mask_t allowed_access;\n\tdeny_masks_t deny_masks;\n\tu8 fown_layer;\n\tstruct landlock_cred_security fown_subject;\n};\n\nstruct landlock_hierarchy {\n\tstruct landlock_hierarchy *parent;\n\trefcount_t usage;\n\tenum landlock_log_status log_status;\n\tatomic64_t num_denials;\n\tu64 id;\n\tconst struct landlock_details *details;\n\tu32 log_same_exec: 1;\n\tu32 log_new_exec: 1;\n};\n\nstruct landlock_object;\n\nunion landlock_key {\n\tstruct landlock_object *object;\n\tuintptr_t data;\n};\n\nstruct landlock_id {\n\tunion landlock_key key;\n\tconst enum landlock_key_type type;\n};\n\nstruct landlock_inode_security {\n\tstruct landlock_object *object;\n};\n\nstruct landlock_layer {\n\tu16 level;\n\taccess_mask_t access;\n};\n\nstruct landlock_net_port_attr {\n\t__u64 allowed_access;\n\t__u64 port;\n};\n\nstruct landlock_object_underops;\n\nstruct landlock_object {\n\trefcount_t usage;\n\tspinlock_t lock;\n\tvoid *underobj;\n\tunion {\n\t\tstruct callback_head rcu_free;\n\t\tconst struct landlock_object_underops *underops;\n\t};\n};\n\nstruct landlock_object_underops {\n\tvoid (*release)(struct landlock_object * const);\n};\n\nstruct landlock_path_beneath_attr {\n\t__u64 allowed_access;\n\t__s32 parent_fd;\n} __attribute__((packed));\n\nstruct layer_access_masks;\n\nstruct landlock_request {\n\tenum landlock_request_type type;\n\tstruct common_audit_data audit;\n\tsize_t layer_plus_one;\n\taccess_mask_t access;\n\tconst struct layer_access_masks *layer_masks;\n\tconst access_mask_t all_existing_optional_access;\n\tdeny_masks_t deny_masks;\n};\n\nstruct landlock_rule {\n\tstruct rb_node node;\n\tunion landlock_key key;\n\tu32 num_layers;\n\tstruct landlock_layer layers[0];\n};\n\nstruct landlock_ruleset {\n\tstruct rb_root root_inode;\n\tstruct rb_root root_net_port;\n\tstruct landlock_hierarchy *hierarchy;\n\tunion {\n\t\tstruct work_struct work_free;\n\t\tstruct {\n\t\t\tstruct mutex lock;\n\t\t\trefcount_t usage;\n\t\t\tu32 num_rules;\n\t\t\tu32 num_layers;\n\t\t\tstruct access_masks access_masks[0];\n\t\t};\n\t};\n};\n\nstruct landlock_ruleset_attr {\n\t__u64 handled_access_fs;\n\t__u64 handled_access_net;\n\t__u64 scoped;\n};\n\nstruct landlock_superblock_security {\n\tatomic_long_t inode_refs;\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct latch_tree_root {\n\tseqcount_latch_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latched_seq {\n\tseqcount_latch_t latch;\n\tu64 val[2];\n};\n\nstruct layer_access_masks {\n\taccess_mask_t access[16];\n};\n\nstruct layout_verification {\n\tu32 mode;\n\tu64 start;\n\tu64 inval;\n\tu64 cowread;\n};\n\nstruct lazy_mmu_state {\n\tu8 enable_count;\n\tu8 pause_count;\n};\n\nstruct sched_domain;\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct lcd_properties {\n\tint max_contrast;\n};\n\nstruct lcd_ops;\n\nstruct lcd_device {\n\tstruct lcd_properties props;\n\tstruct mutex ops_lock;\n\tconst struct lcd_ops *ops;\n\tstruct mutex update_lock;\n\tstruct list_head entry;\n\tstruct device dev;\n};\n\nstruct lcd_ops {\n\tint (*get_power)(struct lcd_device *);\n\tint (*set_power)(struct lcd_device *, int);\n\tint (*get_contrast)(struct lcd_device *);\n\tint (*set_contrast)(struct lcd_device *, int);\n\tint (*set_mode)(struct lcd_device *, u32, u32);\n\tbool (*controls_device)(struct lcd_device *, struct device *);\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct lease_manager_operations {\n\tbool (*lm_break)(struct file_lease *);\n\tint (*lm_change)(struct file_lease *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lease *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lease *);\n\tint (*lm_open_conflict)(struct file *, int);\n};\n\nstruct led_pattern;\n\nstruct led_classdev {\n\tconst char *name;\n\tunsigned int brightness;\n\tunsigned int max_brightness;\n\tunsigned int color;\n\tint flags;\n\tlong unsigned int work_flags;\n\tvoid (*brightness_set)(struct led_classdev *, enum led_brightness);\n\tint (*brightness_set_blocking)(struct led_classdev *, enum led_brightness);\n\tenum led_brightness (*brightness_get)(struct led_classdev *);\n\tint (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *);\n\tint (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int);\n\tint (*pattern_clear)(struct led_classdev *);\n\tstruct device *dev;\n\tconst struct attribute_group **groups;\n\tstruct list_head node;\n\tconst char *default_trigger;\n\tlong unsigned int blink_delay_on;\n\tlong unsigned int blink_delay_off;\n\tstruct timer_list blink_timer;\n\tint blink_brightness;\n\tint new_blink_brightness;\n\tvoid (*flash_resume)(struct led_classdev *);\n\tstruct workqueue_struct *wq;\n\tstruct work_struct set_brightness_work;\n\tint delayed_set_value;\n\tlong unsigned int delayed_delay_on;\n\tlong unsigned int delayed_delay_off;\n\tstruct mutex led_access;\n};\n\nstruct mc_subled;\n\nstruct led_classdev_mc {\n\tstruct led_classdev led_cdev;\n\tunsigned int num_colors;\n\tstruct mc_subled *subled_info;\n};\n\nstruct led_init_data {\n\tstruct fwnode_handle *fwnode;\n\tconst char *default_label;\n\tconst char *devicename;\n\tbool devname_mandatory;\n};\n\nstruct led_pattern {\n\tu32 delta_t;\n\tint brightness;\n};\n\nstruct led_properties {\n\tu32 color;\n\tbool color_present;\n\tconst char *function;\n\tu32 func_enum;\n\tbool func_enum_present;\n\tconst char *label;\n};\n\nstruct legacy_serial_info {\n\tstruct device_node *np;\n\tunsigned int speed;\n\tunsigned int clock;\n\tint irq_check_parent;\n\tphys_addr_t taddr;\n\tvoid *early_addr;\n};\n\nstruct level_datum {\n\tstruct mls_level level;\n\tunsigned char isalias;\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct linear_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct linear_conf {\n\tstruct callback_head rcu;\n\tsector_t array_sectors;\n\tint raid_disks;\n\tstruct dev_info disks[0];\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct link_capabilities {\n\tint speed;\n\tunsigned int duplex;\n\tlong unsigned int linkmodes[2];\n};\n\nstruct link_free {\n\tunion {\n\t\tlong unsigned int next;\n\t\tlong unsigned int handle;\n\t};\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 lanes;\n\tu8 min_pairs;\n\tu8 pairs;\n\tu8 duplex;\n\tu16 mediums;\n};\n\nstruct linked_reg {\n\tu8 frameno;\n\tunion {\n\t\tu8 spi;\n\t\tu8 regno;\n\t};\n\tbool is_reg;\n};\n\nstruct linked_regs {\n\tint cnt;\n\tstruct linked_reg entries[6];\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n\tstruct ethtool_link_ext_stats link_stats;\n\tbool link_ext_state_provided;\n\tstruct ethtool_link_ext_state_info ethtool_link_ext_state_info;\n};\n\nstruct linux_binprm;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef struct linux_binprm *class_bprm_t;\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tlong unsigned int argmin;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tunsigned int comm_from_dentry: 1;\n\tunsigned int is_check: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tconst char *fdpath;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct linux_binprm__safe_trusted {\n\tstruct file *file;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n};\n\nstruct linux_logo {\n\tint type;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int clutsize;\n\tconst unsigned char *clut;\n\tconst unsigned char *data;\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[136];\n};\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n\tstruct list_head list;\n\tint shrinker_id;\n\tbool memcg_aware;\n\tstruct xarray xa;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n\tspinlock_t lock;\n};\n\nstruct list_lru_memcg {\n\tstruct callback_head rcu;\n\tstruct list_lru_one node[0];\n};\n\nstruct list_lru_node {\n\tstruct list_lru_one lru;\n\tatomic_long_t nr_items;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct listener {\n\tstruct list_head list;\n\tpid_t pid;\n\tchar valid;\n};\n\nstruct listener_list {\n\tstruct rw_semaphore sem;\n\tstruct list_head list;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf64_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t\tunsigned int vers_ext_crc;\n\t\tunsigned int vers_ext_name;\n\t} index;\n};\n\nstruct location;\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n\tloff_t idx;\n};\n\nstruct local_ports {\n\tu32 range;\n\tbool warned;\n};\n\nstruct local_trylock {\n\tu8 acquired;\n};\n\ntypedef struct local_trylock local_trylock_t;\n\nstruct location {\n\tdepot_stack_handle_t handle;\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong unsigned int waste;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[32];\n\tnodemask_t nodes;\n};\n\nstruct lock_manager {\n\tstruct list_head list;\n\tbool block_opens;\n};\n\nstruct lock_manager_operations {\n\tvoid *lm_mod_owner;\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_lock_expirable)(struct file_lock *);\n\tvoid (*lm_expire_lock)(void);\n};\n\nstruct lockd_net {\n\tunsigned int nlmsvc_users;\n\tlong unsigned int next_gc;\n\tlong unsigned int nrhosts;\n\tu32 gracetime;\n\tu16 tcp_port;\n\tu16 udp_port;\n\tstruct delayed_work grace_period_end;\n\tstruct lock_manager lockd_manager;\n\tstruct list_head nsm_handles;\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tloff_t li_pos;\n};\n\nstruct log_entry {\n\t__le32 lba;\n\t__le32 old_map;\n\t__le32 new_map;\n\t__le32 seq;\n};\n\nstruct log_group {\n\tstruct log_entry ent[4];\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tconst struct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logical_block_metadata_cap {\n\t__u32 lbmd_flags;\n\t__u16 lbmd_interval;\n\t__u8 lbmd_size;\n\t__u8 lbmd_opaque_size;\n\t__u8 lbmd_opaque_offset;\n\t__u8 lbmd_pi_size;\n\t__u8 lbmd_pi_offset;\n\t__u8 lbmd_guard_tag_type;\n\t__u8 lbmd_app_tag_size;\n\t__u8 lbmd_ref_tag_size;\n\t__u8 lbmd_storage_tag_size;\n\t__u8 pad;\n};\n\nstruct logo_data {\n\tint depth;\n\tint needs_directpalette;\n\tint needs_truepalette;\n\tint needs_cmapreset;\n\tconst struct linux_logo *logo;\n};\n\nstruct lookup_args {\n\tint offset;\n\tconst struct in6_addr *addr;\n};\n\nstruct loop_cmd {\n\tstruct list_head list_entry;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tstruct cgroup_subsys_state *memcg_css;\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nstruct loop_device {\n\tint lo_number;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tchar lo_file_name[64];\n\tstruct file *lo_backing_file;\n\tunsigned int lo_min_dio_size;\n\tstruct block_device *lo_device;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tspinlock_t lo_work_lock;\n\tstruct workqueue_struct *workqueue;\n\tstruct work_struct rootcg_work;\n\tstruct list_head rootcg_cmd_list;\n\tstruct list_head idle_worker_list;\n\tstruct rb_root worker_tree;\n\tstruct timer_list timer;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n\tstruct mutex lo_mutex;\n\tbool idr_visible;\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_worker {\n\tstruct rb_node rb_node;\n\tstruct work_struct work;\n\tstruct list_head cmd_list;\n\tstruct list_head idle_list;\n\tstruct loop_device *lo;\n\tstruct cgroup_subsys_state *blkcg_css;\n\tlong unsigned int last_ran_at;\n};\n\nunion lower_chunk {\n\tunion lower_chunk *next;\n\tlong unsigned int data[256];\n};\n\nstruct lpc_debugfs_entry {\n\tenum OpalLPCAddressType lpc_type;\n};\n\nstruct lpm_trie_node;\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tstruct bpf_mem_alloc ma;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\trqspinlock_t lock;\n};\n\nstruct lpm_trie_node {\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct lppaca {\n\t__be32 desc;\n\t__be16 size;\n\tu8 reserved1[3];\n\tu8 __old_status;\n\tu8 reserved3[14];\n\tvolatile __be32 dyn_hw_node_id;\n\tvolatile __be32 dyn_hw_proc_id;\n\tu8 reserved4[56];\n\tvolatile u8 vphn_assoc_counts[8];\n\tu8 reserved5[32];\n\tu8 reserved6[48];\n\tu8 cede_latency_hint;\n\tu8 ebb_regs_in_use;\n\tu8 reserved7[6];\n\tu8 dtl_enable_mask;\n\tu8 donate_dedicated_cpu;\n\tu8 fpregs_in_use;\n\tu8 pmcregs_in_use;\n\tu8 l2_counters_enable;\n\tu8 reserved8[27];\n\t__be64 wait_state_cycles;\n\tu8 reserved9[28];\n\t__be16 slb_count;\n\tu8 idle;\n\tu8 vmxregs_in_use;\n\tvolatile __be32 yield_count;\n\tvolatile __be32 dispersion_count;\n\tvolatile __be64 cmo_faults;\n\tvolatile __be64 cmo_fault_time;\n\tu8 reserved10[64];\n\tvolatile __be64 enqueue_dispatch_tb;\n\tvolatile __be64 ready_enqueue_tb;\n\tvolatile __be64 wait_ready_tb;\n\tu8 reserved11[16];\n\t__be32 page_ins;\n\tu8 reserved12[28];\n\tvolatile __be64 l1_to_l2_cs_tb;\n\tvolatile __be64 l2_to_l1_cs_tb;\n\tvolatile __be64 l2_runtime_tb;\n\tu8 reserved13[96];\n\tvolatile __be64 dtl_idx;\n\tu8 reserved14[96];\n};\n\nstruct zswap_lruvec_state {\n\tatomic_long_t nr_disk_swapins;\n};\n\nstruct pglist_data;\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tspinlock_t lru_lock;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults[2];\n\tlong unsigned int flags;\n\tstruct pglist_data *pgdat;\n\tstruct zswap_lruvec_state zswap_lruvec_state;\n};\n\nstruct lruvec_stats {\n\tlong int state[33];\n\tlong int state_local[33];\n\tlong int state_pending[33];\n};\n\nstruct lruvec_stats_percpu {\n\tlong int state[33];\n\tlong int state_prev[33];\n};\n\nstruct skcipher_alg_common {\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct lskcipher_alg {\n\tint (*setkey)(struct crypto_lskcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*decrypt)(struct crypto_lskcipher *, const u8 *, u8 *, unsigned int, u8 *, u32);\n\tint (*init)(struct crypto_lskcipher *);\n\tvoid (*exit)(struct crypto_lskcipher *);\n\tstruct skcipher_alg_common co;\n};\n\nstruct lskcipher_instance {\n\tvoid (*free)(struct lskcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct lskcipher_alg alg;\n\t};\n};\n\nstruct lsm_blob_sizes {\n\tunsigned int lbs_cred;\n\tunsigned int lbs_file;\n\tunsigned int lbs_ib;\n\tunsigned int lbs_inode;\n\tunsigned int lbs_sock;\n\tunsigned int lbs_superblock;\n\tunsigned int lbs_ipc;\n\tunsigned int lbs_key;\n\tunsigned int lbs_msg_msg;\n\tunsigned int lbs_perf_event;\n\tunsigned int lbs_task;\n\tunsigned int lbs_xattr_count;\n\tunsigned int lbs_tun_dev;\n\tunsigned int lbs_bdev;\n\tunsigned int lbs_bpf_map;\n\tunsigned int lbs_bpf_prog;\n\tunsigned int lbs_bpf_token;\n};\n\nstruct lsm_context {\n\tchar *context;\n\tu32 len;\n\tint id;\n};\n\nstruct lsm_ctx {\n\t__u64 id;\n\t__u64 flags;\n\t__u64 len;\n\t__u64 ctx_len;\n\t__u8 ctx[0];\n};\n\nstruct lsm_ibendport_audit {\n\tconst char *dev_name;\n\tu8 port;\n};\n\nstruct lsm_ibpkey_audit {\n\tu64 subnet_prefix;\n\tu16 pkey;\n};\n\nstruct lsm_id {\n\tconst char *name;\n\tu64 id;\n};\n\nstruct lsm_info {\n\tconst struct lsm_id *id;\n\tenum lsm_order order;\n\tlong unsigned int flags;\n\tstruct lsm_blob_sizes *blobs;\n\tint *enabled;\n\tint (*init)(void);\n\tint (*initcall_pure)(void);\n\tint (*initcall_early)(void);\n\tint (*initcall_core)(void);\n\tint (*initcall_subsys)(void);\n\tint (*initcall_fs)(void);\n\tint (*initcall_device)(void);\n\tint (*initcall_late)(void);\n};\n\nstruct lsm_ioctlop_audit {\n\tstruct path path;\n\tu16 cmd;\n};\n\nstruct lsm_network_audit {\n\tint netif;\n\tconst struct sock *sk;\n\tu16 family;\n\t__be16 dport;\n\t__be16 sport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 daddr;\n\t\t\t__be32 saddr;\n\t\t} v4;\n\t\tstruct {\n\t\t\tstruct in6_addr daddr;\n\t\t\tstruct in6_addr saddr;\n\t\t} v6;\n\t} fam;\n};\n\nstruct static_call_key;\n\nstruct security_hook_list;\n\nstruct static_key_false;\n\nstruct lsm_static_call {\n\tstruct static_call_key *key;\n\tvoid *trampoline;\n\tstruct security_hook_list *hl;\n\tstruct static_key_false *active;\n};\n\nstruct lsm_static_calls_table {\n\tstruct lsm_static_call binder_set_context_mgr[7];\n\tstruct lsm_static_call binder_transaction[7];\n\tstruct lsm_static_call binder_transfer_binder[7];\n\tstruct lsm_static_call binder_transfer_file[7];\n\tstruct lsm_static_call ptrace_access_check[7];\n\tstruct lsm_static_call ptrace_traceme[7];\n\tstruct lsm_static_call capget[7];\n\tstruct lsm_static_call capset[7];\n\tstruct lsm_static_call capable[7];\n\tstruct lsm_static_call quotactl[7];\n\tstruct lsm_static_call quota_on[7];\n\tstruct lsm_static_call syslog[7];\n\tstruct lsm_static_call settime[7];\n\tstruct lsm_static_call vm_enough_memory[7];\n\tstruct lsm_static_call bprm_creds_for_exec[7];\n\tstruct lsm_static_call bprm_creds_from_file[7];\n\tstruct lsm_static_call bprm_check_security[7];\n\tstruct lsm_static_call bprm_committing_creds[7];\n\tstruct lsm_static_call bprm_committed_creds[7];\n\tstruct lsm_static_call fs_context_submount[7];\n\tstruct lsm_static_call fs_context_dup[7];\n\tstruct lsm_static_call fs_context_parse_param[7];\n\tstruct lsm_static_call sb_alloc_security[7];\n\tstruct lsm_static_call sb_delete[7];\n\tstruct lsm_static_call sb_free_security[7];\n\tstruct lsm_static_call sb_free_mnt_opts[7];\n\tstruct lsm_static_call sb_eat_lsm_opts[7];\n\tstruct lsm_static_call sb_mnt_opts_compat[7];\n\tstruct lsm_static_call sb_remount[7];\n\tstruct lsm_static_call sb_kern_mount[7];\n\tstruct lsm_static_call sb_show_options[7];\n\tstruct lsm_static_call sb_statfs[7];\n\tstruct lsm_static_call sb_mount[7];\n\tstruct lsm_static_call sb_umount[7];\n\tstruct lsm_static_call sb_pivotroot[7];\n\tstruct lsm_static_call sb_set_mnt_opts[7];\n\tstruct lsm_static_call sb_clone_mnt_opts[7];\n\tstruct lsm_static_call move_mount[7];\n\tstruct lsm_static_call dentry_init_security[7];\n\tstruct lsm_static_call dentry_create_files_as[7];\n\tstruct lsm_static_call path_unlink[7];\n\tstruct lsm_static_call path_mkdir[7];\n\tstruct lsm_static_call path_rmdir[7];\n\tstruct lsm_static_call path_mknod[7];\n\tstruct lsm_static_call path_post_mknod[7];\n\tstruct lsm_static_call path_truncate[7];\n\tstruct lsm_static_call path_symlink[7];\n\tstruct lsm_static_call path_link[7];\n\tstruct lsm_static_call path_rename[7];\n\tstruct lsm_static_call path_chmod[7];\n\tstruct lsm_static_call path_chown[7];\n\tstruct lsm_static_call path_chroot[7];\n\tstruct lsm_static_call path_notify[7];\n\tstruct lsm_static_call inode_alloc_security[7];\n\tstruct lsm_static_call inode_free_security[7];\n\tstruct lsm_static_call inode_free_security_rcu[7];\n\tstruct lsm_static_call inode_init_security[7];\n\tstruct lsm_static_call inode_init_security_anon[7];\n\tstruct lsm_static_call inode_create[7];\n\tstruct lsm_static_call inode_post_create_tmpfile[7];\n\tstruct lsm_static_call inode_link[7];\n\tstruct lsm_static_call inode_unlink[7];\n\tstruct lsm_static_call inode_symlink[7];\n\tstruct lsm_static_call inode_mkdir[7];\n\tstruct lsm_static_call inode_rmdir[7];\n\tstruct lsm_static_call inode_mknod[7];\n\tstruct lsm_static_call inode_rename[7];\n\tstruct lsm_static_call inode_readlink[7];\n\tstruct lsm_static_call inode_follow_link[7];\n\tstruct lsm_static_call inode_permission[7];\n\tstruct lsm_static_call inode_setattr[7];\n\tstruct lsm_static_call inode_post_setattr[7];\n\tstruct lsm_static_call inode_getattr[7];\n\tstruct lsm_static_call inode_xattr_skipcap[7];\n\tstruct lsm_static_call inode_setxattr[7];\n\tstruct lsm_static_call inode_post_setxattr[7];\n\tstruct lsm_static_call inode_getxattr[7];\n\tstruct lsm_static_call inode_listxattr[7];\n\tstruct lsm_static_call inode_removexattr[7];\n\tstruct lsm_static_call inode_post_removexattr[7];\n\tstruct lsm_static_call inode_file_setattr[7];\n\tstruct lsm_static_call inode_file_getattr[7];\n\tstruct lsm_static_call inode_set_acl[7];\n\tstruct lsm_static_call inode_post_set_acl[7];\n\tstruct lsm_static_call inode_get_acl[7];\n\tstruct lsm_static_call inode_remove_acl[7];\n\tstruct lsm_static_call inode_post_remove_acl[7];\n\tstruct lsm_static_call inode_need_killpriv[7];\n\tstruct lsm_static_call inode_killpriv[7];\n\tstruct lsm_static_call inode_getsecurity[7];\n\tstruct lsm_static_call inode_setsecurity[7];\n\tstruct lsm_static_call inode_listsecurity[7];\n\tstruct lsm_static_call inode_getlsmprop[7];\n\tstruct lsm_static_call inode_copy_up[7];\n\tstruct lsm_static_call inode_copy_up_xattr[7];\n\tstruct lsm_static_call inode_setintegrity[7];\n\tstruct lsm_static_call kernfs_init_security[7];\n\tstruct lsm_static_call file_permission[7];\n\tstruct lsm_static_call file_alloc_security[7];\n\tstruct lsm_static_call file_release[7];\n\tstruct lsm_static_call file_free_security[7];\n\tstruct lsm_static_call file_ioctl[7];\n\tstruct lsm_static_call file_ioctl_compat[7];\n\tstruct lsm_static_call mmap_addr[7];\n\tstruct lsm_static_call mmap_file[7];\n\tstruct lsm_static_call file_mprotect[7];\n\tstruct lsm_static_call file_lock[7];\n\tstruct lsm_static_call file_fcntl[7];\n\tstruct lsm_static_call file_set_fowner[7];\n\tstruct lsm_static_call file_send_sigiotask[7];\n\tstruct lsm_static_call file_receive[7];\n\tstruct lsm_static_call file_open[7];\n\tstruct lsm_static_call file_post_open[7];\n\tstruct lsm_static_call file_truncate[7];\n\tstruct lsm_static_call task_alloc[7];\n\tstruct lsm_static_call task_free[7];\n\tstruct lsm_static_call cred_alloc_blank[7];\n\tstruct lsm_static_call cred_free[7];\n\tstruct lsm_static_call cred_prepare[7];\n\tstruct lsm_static_call cred_transfer[7];\n\tstruct lsm_static_call cred_getsecid[7];\n\tstruct lsm_static_call cred_getlsmprop[7];\n\tstruct lsm_static_call kernel_act_as[7];\n\tstruct lsm_static_call kernel_create_files_as[7];\n\tstruct lsm_static_call kernel_module_request[7];\n\tstruct lsm_static_call kernel_load_data[7];\n\tstruct lsm_static_call kernel_post_load_data[7];\n\tstruct lsm_static_call kernel_read_file[7];\n\tstruct lsm_static_call kernel_post_read_file[7];\n\tstruct lsm_static_call task_fix_setuid[7];\n\tstruct lsm_static_call task_fix_setgid[7];\n\tstruct lsm_static_call task_fix_setgroups[7];\n\tstruct lsm_static_call task_setpgid[7];\n\tstruct lsm_static_call task_getpgid[7];\n\tstruct lsm_static_call task_getsid[7];\n\tstruct lsm_static_call current_getlsmprop_subj[7];\n\tstruct lsm_static_call task_getlsmprop_obj[7];\n\tstruct lsm_static_call task_setnice[7];\n\tstruct lsm_static_call task_setioprio[7];\n\tstruct lsm_static_call task_getioprio[7];\n\tstruct lsm_static_call task_prlimit[7];\n\tstruct lsm_static_call task_setrlimit[7];\n\tstruct lsm_static_call task_setscheduler[7];\n\tstruct lsm_static_call task_getscheduler[7];\n\tstruct lsm_static_call task_movememory[7];\n\tstruct lsm_static_call task_kill[7];\n\tstruct lsm_static_call task_prctl[7];\n\tstruct lsm_static_call task_to_inode[7];\n\tstruct lsm_static_call userns_create[7];\n\tstruct lsm_static_call ipc_permission[7];\n\tstruct lsm_static_call ipc_getlsmprop[7];\n\tstruct lsm_static_call msg_msg_alloc_security[7];\n\tstruct lsm_static_call msg_msg_free_security[7];\n\tstruct lsm_static_call msg_queue_alloc_security[7];\n\tstruct lsm_static_call msg_queue_free_security[7];\n\tstruct lsm_static_call msg_queue_associate[7];\n\tstruct lsm_static_call msg_queue_msgctl[7];\n\tstruct lsm_static_call msg_queue_msgsnd[7];\n\tstruct lsm_static_call msg_queue_msgrcv[7];\n\tstruct lsm_static_call shm_alloc_security[7];\n\tstruct lsm_static_call shm_free_security[7];\n\tstruct lsm_static_call shm_associate[7];\n\tstruct lsm_static_call shm_shmctl[7];\n\tstruct lsm_static_call shm_shmat[7];\n\tstruct lsm_static_call sem_alloc_security[7];\n\tstruct lsm_static_call sem_free_security[7];\n\tstruct lsm_static_call sem_associate[7];\n\tstruct lsm_static_call sem_semctl[7];\n\tstruct lsm_static_call sem_semop[7];\n\tstruct lsm_static_call netlink_send[7];\n\tstruct lsm_static_call d_instantiate[7];\n\tstruct lsm_static_call getselfattr[7];\n\tstruct lsm_static_call setselfattr[7];\n\tstruct lsm_static_call getprocattr[7];\n\tstruct lsm_static_call setprocattr[7];\n\tstruct lsm_static_call ismaclabel[7];\n\tstruct lsm_static_call secid_to_secctx[7];\n\tstruct lsm_static_call lsmprop_to_secctx[7];\n\tstruct lsm_static_call secctx_to_secid[7];\n\tstruct lsm_static_call release_secctx[7];\n\tstruct lsm_static_call inode_invalidate_secctx[7];\n\tstruct lsm_static_call inode_notifysecctx[7];\n\tstruct lsm_static_call inode_setsecctx[7];\n\tstruct lsm_static_call inode_getsecctx[7];\n\tstruct lsm_static_call unix_stream_connect[7];\n\tstruct lsm_static_call unix_may_send[7];\n\tstruct lsm_static_call socket_create[7];\n\tstruct lsm_static_call socket_post_create[7];\n\tstruct lsm_static_call socket_socketpair[7];\n\tstruct lsm_static_call socket_bind[7];\n\tstruct lsm_static_call socket_connect[7];\n\tstruct lsm_static_call socket_listen[7];\n\tstruct lsm_static_call socket_accept[7];\n\tstruct lsm_static_call socket_sendmsg[7];\n\tstruct lsm_static_call socket_recvmsg[7];\n\tstruct lsm_static_call socket_getsockname[7];\n\tstruct lsm_static_call socket_getpeername[7];\n\tstruct lsm_static_call socket_getsockopt[7];\n\tstruct lsm_static_call socket_setsockopt[7];\n\tstruct lsm_static_call socket_shutdown[7];\n\tstruct lsm_static_call socket_sock_rcv_skb[7];\n\tstruct lsm_static_call socket_getpeersec_stream[7];\n\tstruct lsm_static_call socket_getpeersec_dgram[7];\n\tstruct lsm_static_call sk_alloc_security[7];\n\tstruct lsm_static_call sk_free_security[7];\n\tstruct lsm_static_call sk_clone_security[7];\n\tstruct lsm_static_call sk_getsecid[7];\n\tstruct lsm_static_call sock_graft[7];\n\tstruct lsm_static_call inet_conn_request[7];\n\tstruct lsm_static_call inet_csk_clone[7];\n\tstruct lsm_static_call inet_conn_established[7];\n\tstruct lsm_static_call secmark_relabel_packet[7];\n\tstruct lsm_static_call secmark_refcount_inc[7];\n\tstruct lsm_static_call secmark_refcount_dec[7];\n\tstruct lsm_static_call req_classify_flow[7];\n\tstruct lsm_static_call tun_dev_alloc_security[7];\n\tstruct lsm_static_call tun_dev_create[7];\n\tstruct lsm_static_call tun_dev_attach_queue[7];\n\tstruct lsm_static_call tun_dev_attach[7];\n\tstruct lsm_static_call tun_dev_open[7];\n\tstruct lsm_static_call sctp_assoc_request[7];\n\tstruct lsm_static_call sctp_bind_connect[7];\n\tstruct lsm_static_call sctp_sk_clone[7];\n\tstruct lsm_static_call sctp_assoc_established[7];\n\tstruct lsm_static_call mptcp_add_subflow[7];\n\tstruct lsm_static_call key_alloc[7];\n\tstruct lsm_static_call key_permission[7];\n\tstruct lsm_static_call key_getsecurity[7];\n\tstruct lsm_static_call key_post_create_or_update[7];\n\tstruct lsm_static_call audit_rule_init[7];\n\tstruct lsm_static_call audit_rule_known[7];\n\tstruct lsm_static_call audit_rule_match[7];\n\tstruct lsm_static_call audit_rule_free[7];\n\tstruct lsm_static_call bpf[7];\n\tstruct lsm_static_call bpf_map[7];\n\tstruct lsm_static_call bpf_prog[7];\n\tstruct lsm_static_call bpf_map_create[7];\n\tstruct lsm_static_call bpf_map_free[7];\n\tstruct lsm_static_call bpf_prog_load[7];\n\tstruct lsm_static_call bpf_prog_free[7];\n\tstruct lsm_static_call bpf_token_create[7];\n\tstruct lsm_static_call bpf_token_free[7];\n\tstruct lsm_static_call bpf_token_cmd[7];\n\tstruct lsm_static_call bpf_token_capable[7];\n\tstruct lsm_static_call locked_down[7];\n\tstruct lsm_static_call perf_event_open[7];\n\tstruct lsm_static_call perf_event_alloc[7];\n\tstruct lsm_static_call perf_event_read[7];\n\tstruct lsm_static_call perf_event_write[7];\n\tstruct lsm_static_call uring_override_creds[7];\n\tstruct lsm_static_call uring_sqpoll[7];\n\tstruct lsm_static_call uring_cmd[7];\n\tstruct lsm_static_call uring_allowed[7];\n\tstruct lsm_static_call initramfs_populated[7];\n\tstruct lsm_static_call bdev_alloc_security[7];\n\tstruct lsm_static_call bdev_free_security[7];\n\tstruct lsm_static_call bdev_setintegrity[7];\n};\n\nstruct ltchars {\n\tchar t_suspc;\n\tchar t_dsuspc;\n\tchar t_rprntc;\n\tchar t_flushc;\n\tchar t_werasc;\n\tchar t_lnextc;\n};\n\nstruct lwq {\n\tspinlock_t lock;\n\tstruct llist_node *ready;\n\tstruct llist_head new;\n};\n\nstruct lwq_node {\n\tstruct llist_node node;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct ma_topiary {\n\tstruct maple_enode *head;\n\tstruct maple_enode *tail;\n\tstruct maple_tree *mtree;\n};\n\nstruct ma_wr_state {\n\tstruct ma_state *mas;\n\tstruct maple_node *node;\n\tlong unsigned int r_min;\n\tlong unsigned int r_max;\n\tenum maple_type type;\n\tunsigned char offset_end;\n\tlong unsigned int *pivots;\n\tlong unsigned int end_piv;\n\tvoid **slots;\n\tvoid *entry;\n\tvoid *content;\n\tunsigned char vacant_height;\n\tunsigned char sufficient_height;\n};\n\nstruct mac_addr {\n\tunsigned char addr[6];\n};\n\ntypedef struct mac_addr mac_addr;\n\nstruct pci_host_bridge;\n\nstruct rtc_time;\n\nstruct machdep_calls {\n\tconst char *name;\n\tconst char *compatible;\n\tconst char * const *compatibles;\n\tvoid (*iommu_restore)(void);\n\tlong unsigned int (*memory_block_size)(void);\n\tvoid (*dma_set_mask)(struct device *, u64);\n\tint (*probe)(void);\n\tvoid (*setup_arch)(void);\n\tvoid (*show_cpuinfo)(struct seq_file *);\n\tlong unsigned int (*get_proc_freq)(unsigned int);\n\tvoid (*init_IRQ)(void);\n\tunsigned int (*get_irq)(void);\n\tvoid (*pcibios_fixup)(void);\n\tvoid (*pci_irq_fixup)(struct pci_dev *);\n\tint (*pcibios_root_bridge_prepare)(struct pci_host_bridge *);\n\tvoid (*discover_phbs)(void);\n\tint (*pci_setup_phb)(struct pci_controller *);\n\tvoid (*restart)(char *);\n\tvoid (*halt)(void);\n\tvoid (*panic)(char *);\n\tlong int (*time_init)(void);\n\tint (*set_rtc_time)(struct rtc_time *);\n\tvoid (*get_rtc_time)(struct rtc_time *);\n\ttime64_t (*get_boot_time)(void);\n\tvoid (*calibrate_decr)(void);\n\tvoid (*progress)(char *, short unsigned int);\n\tvoid (*log_error)(char *, unsigned int, int);\n\tunsigned char (*nvram_read_val)(int);\n\tvoid (*nvram_write_val)(int, unsigned char);\n\tssize_t (*nvram_write)(char *, size_t, loff_t *);\n\tssize_t (*nvram_read)(char *, size_t, loff_t *);\n\tssize_t (*nvram_size)(void);\n\tvoid (*nvram_sync)(void);\n\tint (*system_reset_exception)(struct pt_regs *);\n\tint (*machine_check_exception)(struct pt_regs *);\n\tint (*handle_hmi_exception)(struct pt_regs *);\n\tint (*hmi_exception_early)(struct pt_regs *);\n\tlong int (*machine_check_early)(struct pt_regs *);\n\tbool (*mce_check_early_recovery)(struct pt_regs *);\n\tvoid (*machine_check_log_err)(void);\n\tlong int (*feature_call)(unsigned int, ...);\n\tint (*pci_get_legacy_ide_irq)(struct pci_dev *, int);\n\tpgprot_t (*phys_mem_access_prot)(long unsigned int, long unsigned int, pgprot_t);\n\tvoid (*power_save)(void);\n\tvoid (*enable_pmcs)(void);\n\tint (*set_dabr)(long unsigned int, long unsigned int);\n\tint (*set_dawr)(int, long unsigned int, long unsigned int);\n\tint (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);\n\tvoid (*pcibios_fixup_resources)(struct pci_dev *);\n\tvoid (*pcibios_fixup_bus)(struct pci_bus *);\n\tvoid (*pcibios_fixup_phb)(struct pci_controller *);\n\tvoid (*pcibios_bus_add_device)(struct pci_dev *);\n\tresource_size_t (*pcibios_default_alignment)(void);\n\tvoid (*machine_shutdown)(void);\n\tvoid (*kexec_cpu_down)(int, int);\n\tvoid (*machine_kexec)(struct kimage *);\n\tvoid (*suspend_disable_irqs)(void);\n\tvoid (*suspend_enable_irqs)(void);\n\tssize_t (*cpu_probe)(const char *, size_t);\n\tssize_t (*cpu_release)(const char *, size_t);\n\tint (*get_random_seed)(long unsigned int *);\n};\n\nstruct macsec_info {\n\tsci_t sci;\n};\n\nstruct mad_common {\n\t__be32 type;\n\t__be16 status;\n\t__be16 length;\n\t__be64 tag;\n};\n\nstruct viosrp_empty_iu {\n\tstruct mad_common common;\n\t__be64 buffer;\n\t__be32 port;\n};\n\nstruct viosrp_error_log {\n\tstruct mad_common common;\n\t__be64 buffer;\n};\n\nstruct viosrp_adapter_info {\n\tstruct mad_common common;\n\t__be64 buffer;\n};\n\nstruct viosrp_fast_fail {\n\tstruct mad_common common;\n};\n\nstruct viosrp_capabilities {\n\tstruct mad_common common;\n\t__be64 buffer;\n};\n\nunion mad_iu {\n\tstruct viosrp_empty_iu empty_iu;\n\tstruct viosrp_error_log error_log;\n\tstruct viosrp_adapter_info adapter_info;\n\tstruct viosrp_fast_fail fast_fail;\n\tstruct viosrp_capabilities capabilities;\n};\n\nstruct madvise_behavior_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct mmu_gather;\n\nstruct madvise_behavior {\n\tstruct mm_struct *mm;\n\tint behavior;\n\tstruct mmu_gather *tlb;\n\tenum madvise_lock_mode lock_mode;\n\tstruct anon_vma_name *anon_name;\n\tstruct madvise_behavior_range range;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *vma;\n\tbool lock_dropped;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct manage_flash_t {\n\tint status;\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct map_info___2 {\n\tstruct map_info___2 *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nstruct maple_pnode;\n\nstruct maple_metadata {\n\tunsigned char end;\n\tunsigned char gap;\n};\n\nstruct maple_arange_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[9];\n\tvoid *slot[10];\n\tlong unsigned int gap[10];\n\tstruct maple_metadata meta;\n};\n\nstruct maple_big_node {\n\tlong unsigned int pivot[33];\n\tunion {\n\t\tstruct maple_enode *slot[34];\n\t\tstruct {\n\t\t\tlong unsigned int padding[21];\n\t\t\tlong unsigned int gap[21];\n\t\t};\n\t};\n\tunsigned char b_end;\n\tenum maple_type type;\n};\n\nstruct maple_range_64 {\n\tstruct maple_pnode *parent;\n\tlong unsigned int pivot[15];\n\tunion {\n\t\tvoid *slot[16];\n\t\tstruct {\n\t\t\tvoid *pad[15];\n\t\t\tstruct maple_metadata meta;\n\t\t};\n\t};\n};\n\nstruct maple_node {\n\tunion {\n\t\tstruct {\n\t\t\tstruct maple_pnode *parent;\n\t\t\tvoid *slot[31];\n\t\t};\n\t\tstruct {\n\t\t\tvoid *pad;\n\t\t\tstruct callback_head rcu;\n\t\t\tstruct maple_enode *piv_parent;\n\t\t\tunsigned char parent_slot;\n\t\t\tenum maple_type type;\n\t\t\tunsigned char slot_len;\n\t\t\tunsigned int ma_flags;\n\t\t};\n\t\tstruct maple_range_64 mr64;\n\t\tstruct maple_arange_64 ma64;\n\t};\n};\n\nstruct maple_subtree_state {\n\tstruct ma_state *orig_l;\n\tstruct ma_state *orig_r;\n\tstruct ma_state *l;\n\tstruct ma_state *m;\n\tstruct ma_state *r;\n\tstruct ma_topiary *free;\n\tstruct ma_topiary *destroy;\n\tstruct maple_big_node *bn;\n};\n\nstruct maple_topiary {\n\tstruct maple_pnode *parent;\n\tstruct maple_enode *next;\n};\n\nstruct maple_tree {\n\tunion {\n\t\tspinlock_t ma_lock;\n\t};\n\tunsigned int ma_flags;\n\tvoid *ma_root;\n};\n\nstruct mapped_device {\n\tstruct mutex suspend_lock;\n\tstruct mutex table_devices_lock;\n\tstruct list_head table_devices;\n\tvoid *map;\n\tlong unsigned int flags;\n\tstruct mutex type_lock;\n\tenum dm_queue_mode type;\n\tint numa_node_id;\n\tstruct request_queue *queue;\n\tatomic_t holders;\n\tatomic_t open_count;\n\tstruct dm_target *immutable_target;\n\tstruct target_type *immutable_target_type;\n\tchar name[16];\n\tstruct gendisk *disk;\n\tstruct dax_device *dax_dev;\n\twait_queue_head_t wait;\n\tlong unsigned int *pending_io;\n\tstruct hd_geometry geometry;\n\tstruct workqueue_struct *wq;\n\tstruct work_struct work;\n\tspinlock_t deferred_lock;\n\tstruct bio_list deferred;\n\tstruct work_struct requeue_work;\n\tstruct dm_io *requeue_list;\n\tvoid *interface_ptr;\n\twait_queue_head_t eventq;\n\tatomic_t event_nr;\n\tatomic_t uevent_seq;\n\tstruct list_head uevent_list;\n\tspinlock_t uevent_lock;\n\tbool init_tio_pdu: 1;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct dm_stats stats;\n\tunsigned int internal_suspend_count;\n\tint swap_bios;\n\tstruct semaphore swap_bios_semaphore;\n\tstruct mutex swap_bios_lock;\n\tstruct dm_md_mempools *mempools;\n\tstruct dm_kobject_holder kobj_holder;\n\tstruct srcu_struct io_barrier;\n\tstruct dm_ima_measurements ima;\n};\n\nstruct marvell_hw_stat {\n\tconst char *string;\n\tu8 page;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct marvell_hw_stat_simple {\n\tconst char *string;\n\tu8 reg;\n\tu8 bits;\n};\n\nstruct marvell_hwmon_ops {\n\tint (*config)(struct phy_device *);\n\tint (*get_temp)(struct phy_device *, long int *);\n\tint (*get_temp_critical)(struct phy_device *, long int *);\n\tint (*set_temp_critical)(struct phy_device *, long int);\n\tint (*get_temp_alarm)(struct phy_device *, long int *);\n};\n\nstruct marvell_led_rules {\n\tint mode;\n\tlong unsigned int rules;\n};\n\nstruct marvell_priv {\n\tu64 stats[3];\n\tchar *hwmon_name;\n\tstruct device *hwmon_dev;\n\tbool cable_test_tdr;\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n\tu8 vct_phase;\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nstruct maxsynccop_t {\n\t__be32 comp_elements;\n\t__be32 comp_data_limit;\n\t__be32 comp_sg_limit;\n\t__be32 decomp_elements;\n\t__be32 decomp_data_limit;\n\t__be32 decomp_sg_limit;\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker *c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tlong unsigned int e_flags;\n\tu64 e_value;\n};\n\nstruct mbus_dram_window {\n\tu8 cs_index;\n\tu8 mbus_attr;\n\tu64 base;\n\tu64 size;\n};\n\nstruct mbus_dram_target_info {\n\tu8 mbus_dram_target_id;\n\tint num_cs;\n\tstruct mbus_dram_window cs[4];\n};\n\nstruct mc_subled {\n\tunsigned int color_index;\n\tunsigned int brightness;\n\tunsigned int intensity;\n\tunsigned int channel;\n};\n\nstruct mce_derror_table {\n\tlong unsigned int dsisr_value;\n\tbool dar_valid;\n\tunsigned int error_type;\n\tunsigned int error_subtype;\n\tunsigned int error_class;\n\tunsigned int initiator;\n\tunsigned int severity;\n\tbool sync_error;\n};\n\nstruct mce_error_info {\n\tenum MCE_ErrorType error_type: 8;\n\tunion {\n\t\tenum MCE_UeErrorType ue_error_type: 8;\n\t\tenum MCE_SlbErrorType slb_error_type: 8;\n\t\tenum MCE_EratErrorType erat_error_type: 8;\n\t\tenum MCE_TlbErrorType tlb_error_type: 8;\n\t\tenum MCE_UserErrorType user_error_type: 8;\n\t\tenum MCE_RaErrorType ra_error_type: 8;\n\t\tenum MCE_LinkErrorType link_error_type: 8;\n\t} u;\n\tenum MCE_Severity severity: 8;\n\tenum MCE_Initiator initiator: 8;\n\tenum MCE_ErrorClass error_class: 8;\n\tbool sync_error;\n\tbool ignore_event;\n};\n\nstruct mce_ierror_table {\n\tlong unsigned int srr1_mask;\n\tlong unsigned int srr1_value;\n\tbool nip_valid;\n\tunsigned int error_type;\n\tunsigned int error_subtype;\n\tunsigned int error_class;\n\tunsigned int initiator;\n\tunsigned int severity;\n\tbool sync_error;\n};\n\nstruct mce_info {\n\tint mce_nest_count;\n\tstruct machine_check_event mce_event[10];\n\tint mce_queue_count;\n\tstruct machine_check_event mce_event_queue[10];\n\tint mce_ue_count;\n\tstruct machine_check_event mce_ue_event_queue[10];\n};\n\nstruct mcheck_recoverable_range {\n\tu64 start_addr;\n\tu64 end_addr;\n\tu64 recover_addr;\n};\n\nstruct md_bitmap_stats {\n\tu64 events_cleared;\n\tint behind_writes;\n\tbool behind_wait;\n\tlong unsigned int missing_pages;\n\tlong unsigned int file_pages;\n\tlong unsigned int sync_size;\n\tlong unsigned int pages;\n\tstruct file *file;\n};\n\nstruct md_cluster_operations {\n\tstruct md_submodule_head head;\n\tint (*join)(struct mddev *, int);\n\tint (*leave)(struct mddev *);\n\tint (*slot_number)(struct mddev *);\n\tint (*resync_info_update)(struct mddev *, sector_t, sector_t);\n\tint (*resync_start_notify)(struct mddev *);\n\tint (*resync_status_get)(struct mddev *);\n\tvoid (*resync_info_get)(struct mddev *, sector_t *, sector_t *);\n\tint (*metadata_update_start)(struct mddev *);\n\tint (*metadata_update_finish)(struct mddev *);\n\tvoid (*metadata_update_cancel)(struct mddev *);\n\tint (*resync_start)(struct mddev *);\n\tint (*resync_finish)(struct mddev *);\n\tint (*area_resyncing)(struct mddev *, int, sector_t, sector_t);\n\tint (*add_new_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*add_new_disk_cancel)(struct mddev *);\n\tint (*new_disk_ack)(struct mddev *, bool);\n\tint (*remove_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*load_bitmaps)(struct mddev *, int);\n\tint (*gather_bitmaps)(struct md_rdev *);\n\tint (*resize_bitmaps)(struct mddev *, sector_t, sector_t);\n\tint (*lock_all_bitmaps)(struct mddev *);\n\tvoid (*unlock_all_bitmaps)(struct mddev *);\n\tvoid (*update_size)(struct mddev *, sector_t);\n};\n\nstruct md_io_clone {\n\tstruct mddev *mddev;\n\tstruct bio *orig_bio;\n\tlong unsigned int start_time;\n\tsector_t offset;\n\tlong unsigned int sectors;\n\tenum stat_group rw;\n\tstruct bio bio_clone;\n};\n\nstruct md_personality {\n\tstruct md_submodule_head head;\n\tbool (*make_request)(struct mddev *, struct bio *);\n\tint (*run)(struct mddev *);\n\tint (*start)(struct mddev *);\n\tvoid (*free)(struct mddev *, void *);\n\tvoid (*status)(struct seq_file *, struct mddev *);\n\tvoid (*error_handler)(struct mddev *, struct md_rdev *);\n\tint (*hot_add_disk)(struct mddev *, struct md_rdev *);\n\tint (*hot_remove_disk)(struct mddev *, struct md_rdev *);\n\tint (*spare_active)(struct mddev *);\n\tsector_t (*sync_request)(struct mddev *, sector_t, sector_t, int *);\n\tint (*resize)(struct mddev *, sector_t);\n\tsector_t (*size)(struct mddev *, sector_t, int);\n\tint (*check_reshape)(struct mddev *);\n\tint (*start_reshape)(struct mddev *);\n\tvoid (*finish_reshape)(struct mddev *);\n\tvoid (*update_reshape_pos)(struct mddev *);\n\tvoid (*prepare_suspend)(struct mddev *);\n\tvoid (*quiesce)(struct mddev *, int);\n\tvoid * (*takeover)(struct mddev *);\n\tint (*change_consistency_policy)(struct mddev *, const char *);\n\tvoid (*bitmap_sector)(struct mddev *, sector_t *, long unsigned int *);\n};\n\nstruct serial_in_rdev;\n\nstruct md_rdev {\n\tstruct list_head same_set;\n\tsector_t sectors;\n\tstruct mddev *mddev;\n\tlong unsigned int last_events;\n\tstruct block_device *meta_bdev;\n\tstruct block_device *bdev;\n\tstruct file *bdev_file;\n\tstruct page *sb_page;\n\tstruct page *bb_page;\n\tint sb_loaded;\n\t__u64 sb_events;\n\tsector_t data_offset;\n\tsector_t new_data_offset;\n\tsector_t sb_start;\n\tint sb_size;\n\tint preferred_minor;\n\tstruct kobject kobj;\n\tlong unsigned int flags;\n\twait_queue_head_t blocked_wait;\n\tint desc_nr;\n\tint raid_disk;\n\tint new_raid_disk;\n\tint saved_raid_disk;\n\tunion {\n\t\tsector_t recovery_offset;\n\t\tsector_t journal_tail;\n\t};\n\tatomic_t nr_pending;\n\tatomic_t read_errors;\n\ttime64_t last_read_error;\n\tatomic_t corrected_errors;\n\tstruct serial_in_rdev *serial;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_unack_badblocks;\n\tstruct kernfs_node *sysfs_badblocks;\n\tstruct badblocks badblocks;\n\tstruct {\n\t\tshort int offset;\n\t\tunsigned int size;\n\t\tsector_t sector;\n\t} ppl;\n};\n\nstruct md_setup_args {\n\tint minor;\n\tint partitioned;\n\tint level;\n\tint chunk;\n\tchar *device_names;\n};\n\nstruct md_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mddev *, char *);\n\tssize_t (*store)(struct mddev *, const char *, size_t);\n};\n\nstruct md_thread {\n\tvoid (*run)(struct md_thread *);\n\tstruct mddev *mddev;\n\twait_queue_head_t wqueue;\n\tlong unsigned int flags;\n\tstruct task_struct *tsk;\n\tlong unsigned int timeout;\n\tvoid *private;\n};\n\nstruct md_cluster_info;\n\nstruct mddev {\n\tvoid *private;\n\tstruct md_personality *pers;\n\tdev_t unit;\n\tint md_minor;\n\tstruct list_head disks;\n\tlong unsigned int flags;\n\tlong unsigned int sb_flags;\n\tint suspended;\n\tstruct mutex suspend_mutex;\n\tstruct percpu_ref active_io;\n\tint ro;\n\tint sysfs_active;\n\tstruct gendisk *gendisk;\n\tstruct gendisk *dm_gendisk;\n\tstruct kobject kobj;\n\tint hold_active;\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tint persistent;\n\tint external;\n\tchar metadata_type[17];\n\tint chunk_sectors;\n\ttime64_t ctime;\n\ttime64_t utime;\n\tint level;\n\tint layout;\n\tchar clevel[16];\n\tint raid_disks;\n\tint max_disks;\n\tsector_t dev_sectors;\n\tsector_t array_sectors;\n\tint external_size;\n\tunsigned int logical_block_size;\n\t__u64 events;\n\tint can_decrease_events;\n\tchar uuid[16];\n\tsector_t reshape_position;\n\tint delta_disks;\n\tint new_level;\n\tint new_layout;\n\tint new_chunk_sectors;\n\tint reshape_backwards;\n\tstruct md_thread *thread;\n\tstruct md_thread *sync_thread;\n\tenum sync_action last_sync_action;\n\tsector_t curr_resync;\n\tsector_t curr_resync_completed;\n\tlong unsigned int resync_mark;\n\tsector_t resync_mark_cnt;\n\tsector_t curr_mark_cnt;\n\tsector_t resync_max_sectors;\n\tatomic64_t resync_mismatches;\n\tsector_t suspend_lo;\n\tsector_t suspend_hi;\n\tint sync_speed_min;\n\tint sync_speed_max;\n\tint sync_io_depth;\n\tint parallel_resync;\n\tint ok_start_degraded;\n\tlong unsigned int recovery;\n\tint in_sync;\n\tstruct mutex open_mutex;\n\tstruct mutex reconfig_mutex;\n\tatomic_t active;\n\tatomic_t openers;\n\tint changed;\n\tint degraded;\n\tlong unsigned int normal_io_events;\n\tatomic_t recovery_active;\n\twait_queue_head_t recovery_wait;\n\tsector_t resync_offset;\n\tsector_t resync_min;\n\tsector_t resync_max;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_action;\n\tstruct kernfs_node *sysfs_completed;\n\tstruct kernfs_node *sysfs_degraded;\n\tstruct kernfs_node *sysfs_level;\n\tstruct work_struct del_work;\n\tstruct work_struct sync_work;\n\tspinlock_t lock;\n\twait_queue_head_t sb_wait;\n\tatomic_t pending_writes;\n\tunsigned int safemode;\n\tunsigned int safemode_delay;\n\tstruct timer_list safemode_timer;\n\tstruct percpu_ref writes_pending;\n\tint sync_checkers;\n\tenum md_submodule_id bitmap_id;\n\tvoid *bitmap;\n\tstruct bitmap_operations *bitmap_ops;\n\tstruct {\n\t\tstruct file *file;\n\t\tloff_t offset;\n\t\tlong unsigned int space;\n\t\tloff_t default_offset;\n\t\tlong unsigned int default_space;\n\t\tstruct mutex mutex;\n\t\tlong unsigned int chunksize;\n\t\tlong unsigned int daemon_sleep;\n\t\tlong unsigned int max_write_behind;\n\t\tint external;\n\t\tint nodes;\n\t\tchar cluster_name[64];\n\t} bitmap_info;\n\tatomic_t max_corr_read_errors;\n\tstruct list_head all_mddevs;\n\tconst struct attribute_group *to_remove;\n\tstruct bio_set bio_set;\n\tstruct bio_set sync_set;\n\tstruct bio_set io_clone_set;\n\tstruct work_struct event_work;\n\tmempool_t *serial_info_pool;\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tstruct md_cluster_info *cluster_info;\n\tstruct md_cluster_operations *cluster_ops;\n\tunsigned int good_device_nr;\n\tunsigned int noio_flag;\n\tstruct list_head deleting;\n\tatomic_t sync_seq;\n};\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct mii_bus;\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tint (*bus_match)(struct device *, const struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tint reset_state;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n\tvoid (*shutdown)(struct mdio_device *);\n};\n\nstruct mdiobus_devres {\n\tstruct mii_bus *mii;\n};\n\nstruct mdp_device_descriptor_s {\n\t__u32 number;\n\t__u32 major;\n\t__u32 minor;\n\t__u32 raid_disk;\n\t__u32 state;\n\t__u32 reserved[27];\n};\n\ntypedef struct mdp_device_descriptor_s mdp_disk_t;\n\nstruct mdp_superblock_1 {\n\t__le32 magic;\n\t__le32 major_version;\n\t__le32 feature_map;\n\t__le32 pad0;\n\t__u8 set_uuid[16];\n\tchar set_name[32];\n\t__le64 ctime;\n\t__le32 level;\n\t__le32 layout;\n\t__le64 size;\n\t__le32 chunksize;\n\t__le32 raid_disks;\n\tunion {\n\t\t__le32 bitmap_offset;\n\t\tstruct {\n\t\t\t__le16 offset;\n\t\t\t__le16 size;\n\t\t} ppl;\n\t};\n\t__le32 new_level;\n\t__le64 reshape_position;\n\t__le32 delta_disks;\n\t__le32 new_layout;\n\t__le32 new_chunk;\n\t__le32 new_offset;\n\t__le64 data_offset;\n\t__le64 data_size;\n\t__le64 super_offset;\n\tunion {\n\t\t__le64 recovery_offset;\n\t\t__le64 journal_tail;\n\t};\n\t__le32 dev_number;\n\t__le32 cnt_corrected_read;\n\t__u8 device_uuid[16];\n\t__u8 devflags;\n\t__u8 bblog_shift;\n\t__le16 bblog_size;\n\t__le32 bblog_offset;\n\t__le64 utime;\n\t__le64 events;\n\t__le64 resync_offset;\n\t__le32 sb_csum;\n\t__le32 max_dev;\n\t__le32 logical_block_size;\n\t__u8 pad3[28];\n\t__le16 dev_roles[0];\n};\n\nstruct mdp_superblock_s {\n\t__u32 md_magic;\n\t__u32 major_version;\n\t__u32 minor_version;\n\t__u32 patch_version;\n\t__u32 gvalid_words;\n\t__u32 set_uuid0;\n\t__u32 ctime;\n\t__u32 level;\n\t__u32 size;\n\t__u32 nr_disks;\n\t__u32 raid_disks;\n\t__u32 md_minor;\n\t__u32 not_persistent;\n\t__u32 set_uuid1;\n\t__u32 set_uuid2;\n\t__u32 set_uuid3;\n\t__u32 gstate_creserved[16];\n\t__u32 utime;\n\t__u32 state;\n\t__u32 active_disks;\n\t__u32 working_disks;\n\t__u32 failed_disks;\n\t__u32 spare_disks;\n\t__u32 sb_csum;\n\t__u32 events_lo;\n\t__u32 events_hi;\n\t__u32 cp_events_lo;\n\t__u32 cp_events_hi;\n\t__u32 recovery_cp;\n\t__u64 reshape_position;\n\t__u32 new_level;\n\t__u32 delta_disks;\n\t__u32 new_layout;\n\t__u32 new_chunk;\n\t__u32 gstate_sreserved[14];\n\t__u32 layout;\n\t__u32 chunk_size;\n\t__u32 root_pv;\n\t__u32 root_block;\n\t__u32 pstate_reserved[60];\n\tmdp_disk_t disks[27];\n\t__u32 reserved[0];\n\tmdp_disk_t this_disk;\n};\n\ntypedef struct mdp_superblock_s mdp_super_t;\n\nstruct mdu_array_info_s {\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tunsigned int ctime;\n\tint level;\n\tint size;\n\tint nr_disks;\n\tint raid_disks;\n\tint md_minor;\n\tint not_persistent;\n\tunsigned int utime;\n\tint state;\n\tint active_disks;\n\tint working_disks;\n\tint failed_disks;\n\tint spare_disks;\n\tint layout;\n\tint chunk_size;\n};\n\ntypedef struct mdu_array_info_s mdu_array_info_t;\n\nstruct mdu_bitmap_file_s {\n\tchar pathname[4096];\n};\n\ntypedef struct mdu_bitmap_file_s mdu_bitmap_file_t;\n\nstruct mdu_disk_info_s {\n\tint number;\n\tint major;\n\tint minor;\n\tint raid_disk;\n\tint state;\n};\n\ntypedef struct mdu_disk_info_s mdu_disk_info_t;\n\nstruct mdu_version_s {\n\tint major;\n\tint minor;\n\tint patchlevel;\n};\n\ntypedef struct mdu_version_s mdu_version_t;\n\nstruct media_event_desc {\n\t__u8 media_event_code: 4;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 media_present: 1;\n\t__u8 reserved2: 6;\n\t__u8 start_slot;\n\t__u8 end_slot;\n};\n\nstruct stats {\n\t__le32 tx_good_frames;\n\t__le32 tx_max_collisions;\n\t__le32 tx_late_collisions;\n\t__le32 tx_underruns;\n\t__le32 tx_lost_crs;\n\t__le32 tx_deferred;\n\t__le32 tx_single_collisions;\n\t__le32 tx_multiple_collisions;\n\t__le32 tx_total_collisions;\n\t__le32 rx_good_frames;\n\t__le32 rx_crc_errors;\n\t__le32 rx_alignment_errors;\n\t__le32 rx_resource_errors;\n\t__le32 rx_overrun_errors;\n\t__le32 rx_cdt_errors;\n\t__le32 rx_short_frame_errors;\n\t__le32 fc_xmt_pause;\n\t__le32 fc_rcv_pause;\n\t__le32 fc_rcv_unsupported;\n\t__le16 xmt_tco_frames;\n\t__le16 rcv_tco_frames;\n\t__le32 complete;\n};\n\nstruct mem {\n\tstruct {\n\t\tu32 signature;\n\t\tu32 result;\n\t} selftest;\n\tstruct stats stats;\n\tu8 dump_buf[596];\n};\n\nstruct mem_cgroup_private_id {\n\tint id;\n\trefcount_t ref;\n};\n\nstruct vmpressure {\n\tlong unsigned int scanned;\n\tlong unsigned int reclaimed;\n\tlong unsigned int tree_scanned;\n\tlong unsigned int tree_reclaimed;\n\tspinlock_t sr_lock;\n\tstruct list_head events;\n\tstruct mutex events_lock;\n\tstruct work_struct work;\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n\tlong unsigned int progress_stamp;\n\tlong unsigned int wait_start;\n};\n\nstruct memcg_cgwb_frn {\n\tu64 bdi_id;\n\tint memcg_id;\n\tu64 at;\n\tstruct wb_completion done;\n};\n\nstruct memcg_vmstats;\n\nstruct memcg_vmstats_percpu;\n\nstruct mem_cgroup_per_node;\n\nstruct mem_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct mem_cgroup_private_id id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct page_counter memory;\n\tunion {\n\t\tstruct page_counter swap;\n\t\tstruct page_counter memsw;\n\t};\n\tstruct list_head memory_peaks;\n\tstruct list_head swap_peaks;\n\tspinlock_t peaks_lock;\n\tstruct work_struct high_work;\n\tlong unsigned int zswap_max;\n\tbool zswap_writeback;\n\tstruct vmpressure vmpressure;\n\tbool oom_group;\n\tint swappiness;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct cgroup_file swap_events_file;\n\tstruct memcg_vmstats *vmstats;\n\tatomic_long_t memory_events[10];\n\tatomic_long_t memory_events_local[10];\n\tatomic_t kmem_stat;\n\tu64 socket_pressure;\n\tint kmemcg_id;\n\tstruct obj_cgroup *objcg;\n\tstruct obj_cgroup *orig_objcg;\n\tstruct list_head objcg_list;\n\tstruct memcg_vmstats_percpu *vmstats_percpu;\n\tstruct list_head cgwb_list;\n\tstruct wb_domain cgwb_domain;\n\tstruct memcg_cgwb_frn cgwb_frn[4];\n\tstruct deferred_split deferred_split_queue;\n\tstruct mem_cgroup_per_node *nodeinfo[0];\n\tlong: 64;\n};\n\nstruct mem_cgroup_reclaim_iter {\n\tstruct mem_cgroup *position;\n\tatomic_t generation;\n};\n\nstruct shrinker_info;\n\nstruct mem_cgroup_per_node {\n\tstruct mem_cgroup *memcg;\n\tstruct lruvec_stats_percpu *lruvec_stats_percpu;\n\tstruct lruvec_stats *lruvec_stats;\n\tstruct shrinker_info *shrinker_info;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct lruvec lruvec;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int lru_zone_size[15];\n\tstruct mem_cgroup_reclaim_iter iter;\n\tatomic_t slab_reclaimable;\n\tatomic_t slab_unreclaimable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct pglist_data pg_data_t;\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tint generation;\n};\n\nstruct mcidev_sysfs_attribute;\n\nstruct mem_ctl_info {\n\tstruct device dev;\n\tconst struct bus_type *bus;\n\tstruct list_head link;\n\tstruct module *owner;\n\tlong unsigned int mtype_cap;\n\tlong unsigned int edac_ctl_cap;\n\tlong unsigned int edac_cap;\n\tlong unsigned int scrub_cap;\n\tenum scrub_type scrub_mode;\n\tint (*set_sdram_scrub_rate)(struct mem_ctl_info *, u32);\n\tint (*get_sdram_scrub_rate)(struct mem_ctl_info *);\n\tvoid (*edac_check)(struct mem_ctl_info *);\n\tlong unsigned int (*ctl_page_to_phys)(struct mem_ctl_info *, long unsigned int);\n\tint mc_idx;\n\tstruct csrow_info **csrows;\n\tunsigned int nr_csrows;\n\tunsigned int num_cschannel;\n\tunsigned int n_layers;\n\tstruct edac_mc_layer *layers;\n\tbool csbased;\n\tunsigned int tot_dimms;\n\tstruct dimm_info **dimms;\n\tstruct device *pdev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tu32 ce_noinfo_count;\n\tu32 ue_noinfo_count;\n\tu32 ue_mc;\n\tu32 ce_mc;\n\tstruct completion complete;\n\tconst struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;\n\tstruct delayed_work work;\n\tstruct edac_raw_error_desc error_desc;\n\tint op_state;\n\tstruct dentry *debugfs;\n\tu8 fake_inject_layer[3];\n\tbool fake_inject_ue;\n\tu16 fake_inject_count;\n};\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n};\n\nstruct mem_entry {\n\tu32 offset;\n\tu32 len;\n};\n\nstruct mem_map_entry {\n\t__be64 base;\n\t__be64 size;\n};\n\nstruct mem_section_usage;\n\nstruct page_ext;\n\nstruct mem_section {\n\tlong unsigned int section_mem_map;\n\tstruct mem_section_usage *usage;\n\tstruct page_ext *page_ext;\n\tlong unsigned int pad;\n};\n\nstruct mem_section_usage {\n\tstruct callback_head rcu;\n\tlong unsigned int subsection_map[1];\n\tlong unsigned int pageblock_flags[0];\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tlong unsigned int ksm;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_dirty;\n\tu64 pss_locked;\n\tu64 swap_pss;\n};\n\nstruct memblock_region;\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n\tint nid;\n};\n\nstruct membuf {\n\tvoid *p;\n\tsize_t left;\n};\n\nstruct memcg_stock_pcp {\n\tlocal_trylock_t lock;\n\tuint8_t nr_pages[7];\n\tstruct mem_cgroup *cached[7];\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct memcg_vmstats {\n\tlong int state[40];\n\tlong unsigned int events[29];\n\tlong int state_local[40];\n\tlong unsigned int events_local[29];\n\tlong int state_pending[40];\n\tlong unsigned int events_pending[29];\n\tatomic_t stats_updates;\n};\n\nstruct memcg_vmstats_percpu {\n\tunsigned int stats_updates;\n\tstruct memcg_vmstats_percpu *parent_pcpu;\n\tstruct memcg_vmstats *vmstats;\n\tlong int state[40];\n\tlong unsigned int events[29];\n\tlong int state_prev[40];\n\tlong unsigned int events_prev[29];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct memcons {\n\t__be64 magic;\n\t__be64 obuf_phys;\n\t__be64 ibuf_phys;\n\t__be32 obuf_size;\n\t__be32 ibuf_size;\n\t__be32 out_pos;\n\t__be32 in_prod;\n\t__be32 in_cons;\n};\n\nstruct memdev {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n\tumode_t mode;\n};\n\nstruct memory_group;\n\nstruct memory_block {\n\tlong unsigned int start_section_nr;\n\tenum memory_block_state state;\n\tint online_type;\n\tint nid;\n\tstruct zone *zone;\n\tstruct device dev;\n\tstruct vmem_altmap *altmap;\n\tstruct memory_group *group;\n\tstruct list_head group_next;\n};\n\nstruct memory_dev_type {\n\tstruct list_head tier_sibling;\n\tstruct list_head list;\n\tint adistance;\n\tnodemask_t nodes;\n\tstruct kref kref;\n};\n\nstruct memory_group {\n\tint nid;\n\tstruct list_head memory_blocks;\n\tlong unsigned int present_kernel_pages;\n\tlong unsigned int present_movable_pages;\n\tbool is_dynamic;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int max_pages;\n\t\t} s;\n\t\tstruct {\n\t\t\tlong unsigned int unit_pages;\n\t\t} d;\n\t};\n};\n\nstruct memory_notify {\n\tlong unsigned int start_pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct netdev_rx_queue;\n\nstruct memory_provider_ops {\n\tnetmem_ref (*alloc_netmems)(struct page_pool *, gfp_t);\n\tbool (*release_netmem)(struct page_pool *, netmem_ref);\n\tint (*init)(struct page_pool *);\n\tvoid (*destroy)(struct page_pool *);\n\tint (*nl_fill)(void *, struct sk_buff *, struct netdev_rx_queue *);\n\tvoid (*uninstall)(void *, struct netdev_rx_queue *);\n};\n\nstruct memory_stat {\n\tconst char *name;\n\tunsigned int idx;\n};\n\nstruct memory_tier {\n\tstruct list_head list;\n\tstruct list_head memory_types;\n\tint adistance_start;\n\tstruct device dev;\n\tnodemask_t lower_tier_mask;\n};\n\nstruct mempolicy {\n\tatomic_t refcnt;\n\tshort unsigned int mode;\n\tshort unsigned int flags;\n\tnodemask_t nodes;\n\tint home_node;\n\tunion {\n\t\tnodemask_t cpuset_mems_allowed;\n\t\tnodemask_t user_nodemask;\n\t} w;\n};\n\nstruct mempolicy_operations {\n\tint (*create)(struct mempolicy *, const nodemask_t *);\n\tvoid (*rebind)(struct mempolicy *, const nodemask_t *);\n};\n\nstruct menu_device {\n\tint needs_update;\n\tint tick_wakeup;\n\tu64 next_timer_ns;\n\tunsigned int bucket;\n\tunsigned int correction_factor[6];\n\tunsigned int intervals[8];\n\tint interval_ptr;\n};\n\nstruct merge_sched_data {\n\tint can_add_hw;\n\tenum event_type_t event_type;\n};\n\nstruct xfrm_md_info {\n\tu32 if_id;\n\tint link;\n\tstruct dst_entry *dst_orig;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t\tstruct macsec_info macsec_info;\n\t\tstruct xfrm_md_info xfrm_info;\n\t} u;\n};\n\nstruct mext_data {\n\tstruct inode *orig_inode;\n\tstruct inode *donor_inode;\n\tstruct ext4_map_blocks orig_map;\n\text4_lblk_t donor_lblk;\n};\n\nstruct mhp_params {\n\tstruct vmem_altmap *altmap;\n\tpgprot_t pgprot;\n\tstruct dev_pagemap *pgmap;\n};\n\nstruct migrate_pages_stats {\n\tint nr_succeeded;\n\tint nr_failed_pages;\n\tint nr_thp_succeeded;\n\tint nr_thp_failed;\n\tint nr_thp_split;\n\tint nr_split;\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct migrate_vma {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int *dst;\n\tlong unsigned int *src;\n\tlong unsigned int cpages;\n\tlong unsigned int npages;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tvoid *pgmap_owner;\n\tlong unsigned int flags;\n\tstruct page *fault_page;\n};\n\nstruct set_affinity_pending;\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n\tstruct set_affinity_pending *pending;\n};\n\nstruct migration_mpol {\n\tstruct mempolicy *pol;\n\tlong unsigned int ilx;\n};\n\nstruct migration_swap_arg {\n\tstruct task_struct *src_task;\n\tstruct task_struct *dst_task;\n\tint src_cpu;\n\tint dst_cpu;\n};\n\nstruct migration_target_control {\n\tint nid;\n\tnodemask_t *nmask;\n\tgfp_t gfp_mask;\n\tenum migrate_reason reason;\n};\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*read_c45)(struct mii_bus *, int, int, int);\n\tint (*write_c45)(struct mii_bus *, int, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tint reset_post_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n};\n\nstruct mii_if_info {\n\tint phy_id;\n\tint advertising;\n\tint phy_id_mask;\n\tint reg_num_mask;\n\tunsigned int full_duplex: 1;\n\tunsigned int force_media: 1;\n\tunsigned int supports_gmii: 1;\n\tstruct net_device *dev;\n\tint (*mdio_read)(struct net_device *, int, int);\n\tvoid (*mdio_write)(struct net_device *, int, int, int);\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct mii_phy_ops;\n\nstruct mii_phy_def {\n\tu32 phy_id;\n\tu32 phy_id_mask;\n\tu32 features;\n\tint magic_aneg;\n\tconst char *name;\n\tconst struct mii_phy_ops *ops;\n};\n\nstruct mii_phy_ops {\n\tint (*init)(struct mii_phy *);\n\tint (*suspend)(struct mii_phy *);\n\tint (*setup_aneg)(struct mii_phy *, u32);\n\tint (*setup_forced)(struct mii_phy *, int, int);\n\tint (*poll_link)(struct mii_phy *);\n\tint (*read_link)(struct mii_phy *);\n\tint (*enable_fiber)(struct mii_phy *, int);\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp_set)(struct mii_timestamper *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tint (*hwtstamp_get)(struct mii_timestamper *, struct kernel_hwtstamp_config *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct kernel_ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct min_heap_callbacks {\n\tbool (*less)(const void *, const void *, void *);\n\tvoid (*swp)(void *, void *, void *);\n};\n\nstruct min_heap_char {\n\tsize_t nr;\n\tsize_t size;\n\tchar *data;\n\tchar preallocated[0];\n};\n\ntypedef struct min_heap_char min_heap_char;\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nstruct tcf_proto;\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tlong unsigned int rcu_state;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct minix_super_block {\n\t__u16 s_ninodes;\n\t__u16 s_nzones;\n\t__u16 s_imap_blocks;\n\t__u16 s_zmap_blocks;\n\t__u16 s_firstdatazone;\n\t__u16 s_log_zone_size;\n\t__u32 s_max_size;\n\t__u16 s_magic;\n\t__u16 s_state;\n\t__u32 s_zones;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct misc_res {\n\tu64 max;\n\tatomic64_t watermark;\n\tatomic64_t usage;\n\tatomic64_t events;\n\tatomic64_t events_local;\n};\n\nstruct misc_cg {\n\tstruct cgroup_subsys_state css;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tstruct misc_res res[0];\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nstruct ml_effect_state {\n\tstruct ff_effect *effect;\n\tlong unsigned int flags;\n\tint count;\n\tlong unsigned int play_at;\n\tlong unsigned int stop_at;\n\tlong unsigned int adj_at;\n};\n\nstruct ml_device {\n\tvoid *private;\n\tstruct ml_effect_state states[16];\n\tint gain;\n\tstruct timer_list timer;\n\tstruct input_dev *dev;\n\tint (*play_effect)(struct input_dev *, void *, struct ff_effect *);\n};\n\nstruct mld2_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\tstruct in6_addr grec_mca;\n\tstruct in6_addr grec_src[0];\n};\n\nstruct mld2_query {\n\tstruct icmp6hdr mld2q_hdr;\n\tstruct in6_addr mld2q_mca;\n\t__u8 mld2q_qrv: 3;\n\t__u8 mld2q_suppress: 1;\n\t__u8 mld2q_resv2: 4;\n\t__u8 mld2q_qqic;\n\t__be16 mld2q_nsrcs;\n\tstruct in6_addr mld2q_srcs[0];\n};\n\nstruct mld2_report {\n\tstruct icmp6hdr mld2r_hdr;\n\tstruct mld2_grec mld2r_grec[0];\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mlock_fbatch {\n\tlocal_lock_t lock;\n\tstruct folio_batch fbatch;\n};\n\nstruct mm_cid_pcpu {\n\tunsigned int cid;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_iommu_table_group_mem_t {\n\tstruct list_head next;\n\tstruct callback_head rcu;\n\tlong unsigned int used;\n\tatomic64_t mapped;\n\tunsigned int pageshift;\n\tu64 ua;\n\tu64 entries;\n\tunion {\n\t\tstruct page **hpages;\n\t\tphys_addr_t *hpas;\n\t};\n\tu64 dev_hpa;\n};\n\nstruct mm_mm_cid {\n\tstruct mm_cid_pcpu *pcpu;\n\tunsigned int mode;\n\tunsigned int max_cids;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tunsigned int nr_cpus_allowed;\n\tunsigned int users;\n\tunsigned int pcpu_thrs;\n\tunsigned int update_deferred;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mm_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_mm_state state;\n\tstruct ethtool_mm_stats stats;\n};\n\ntypedef struct mm_struct *class_mmap_read_lock_t;\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n};\n\nstruct mmu_notifier_subscriptions;\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct {\n\t\t\tatomic_t mm_count;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t\tlong: 64;\n\t\t};\n\t\tstruct maple_tree mm_mt;\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tstruct mm_mm_cid mm_cid;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tstruct rcuwait vma_writer_wait;\n\t\tseqcount_t mm_lock_seq;\n\t\tstruct mutex futex_hash_lock;\n\t\tstruct futex_private_hash *futex_phash;\n\t\tstruct futex_private_hash *futex_phash_new;\n\t\tlong unsigned int futex_batches;\n\t\tstruct callback_head futex_rcu;\n\t\tatomic_long_t futex_atomic;\n\t\tunsigned int *futex_ref;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tvm_flags_t def_flags;\n\t\tseqcount_t write_protect_seq;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[76];\n\t\tstruct percpu_counter rss_stat[4];\n\t\tstruct linux_binfmt *binfmt;\n\t\tmm_context_t context;\n\t\tmm_flags_t flags;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct task_struct *owner;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tstruct mmu_notifier_subscriptions *notifier_subscriptions;\n\t\tlong unsigned int numa_next_scan;\n\t\tlong unsigned int numa_scan_offset;\n\t\tint numa_scan_seq;\n\t\tatomic_t tlb_flush_pending;\n\t\tstruct uprobes_state uprobes_state;\n\t\tatomic_long_t hugetlb_usage;\n\t\tstruct work_struct async_put_work;\n\t\tlong unsigned int ksm_merging_pages;\n\t\tlong unsigned int ksm_rmap_items;\n\t\tatomic_long_t ksm_zero_pages;\n\t\tmm_id_t mm_id;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tchar flexible_array[0];\n};\n\nstruct mm_struct__safe_rcu_or_null {\n\tstruct file *exe_file;\n\tstruct task_struct *owner;\n};\n\nstruct mm_walk_ops;\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n\tint (*install_pte)(long unsigned int, long unsigned int, pte_t *, struct mm_walk *);\n\tenum page_walk_lock walk_lock;\n};\n\nstruct mmap_action {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int start;\n\t\t\tlong unsigned int start_pfn;\n\t\t\tlong unsigned int size;\n\t\t\tpgprot_t pgprot;\n\t\t} remap;\n\t};\n\tenum mmap_action_type type;\n\tint (*success_hook)(const struct vm_area_struct *);\n\tint (*error_hook)(int);\n\tbool hide_from_rmap_until_complete: 1;\n};\n\nstruct vma_munmap_struct {\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct list_head *uf;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int unmap_start;\n\tlong unsigned int unmap_end;\n\tint vma_count;\n\tbool unlock;\n\tbool clear_ptes;\n\tlong unsigned int nr_pages;\n\tlong unsigned int locked_vm;\n\tlong unsigned int nr_accounted;\n\tlong unsigned int exec_vm;\n\tlong unsigned int stack_vm;\n\tlong unsigned int data_vm;\n};\n\nstruct mmap_state {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tlong unsigned int addr;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tunion {\n\t\tvm_flags_t vm_flags;\n\t\tvma_flags_t vma_flags;\n\t};\n\tstruct file *file;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *vm_private_data;\n\tlong unsigned int charged;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *next;\n\tstruct vma_munmap_struct vms;\n\tstruct ma_state mas_detach;\n\tstruct maple_tree mt_detach;\n\tbool check_ksm_early: 1;\n\tbool hold_file_rmap_lock: 1;\n\tbool file_doesnt_need_get: 1;\n};\n\nstruct mmap_unlock_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\nstruct mminit_pfnnid_cache {\n\tlong unsigned int last_start;\n\tlong unsigned int last_end;\n\tint last_nid;\n};\n\nstruct mmiowb_state {\n\tu16 nesting_count;\n\tu16 mmiowb_pending;\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct encoded_page;\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct encoded_page *encoded_pages[0];\n};\n\nstruct mmu_table_batch;\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tstruct mmu_table_batch *batch;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int delayed_rmap: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int vma_pfn: 1;\n\tunsigned int unshared_tables: 1;\n\tunsigned int fully_unshared_tables: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n\tunsigned int page_size;\n};\n\nstruct mmu_hash_ops {\n\tvoid (*hpte_invalidate)(long unsigned int, long unsigned int, int, int, int, int);\n\tlong int (*hpte_updatepp)(long unsigned int, long unsigned int, long unsigned int, int, int, int, long unsigned int);\n\tvoid (*hpte_updateboltedpp)(long unsigned int, long unsigned int, int, int);\n\tlong int (*hpte_insert)(long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int, int);\n\tlong int (*hpte_remove)(long unsigned int);\n\tint (*hpte_removebolted)(long unsigned int, int, int);\n\tvoid (*flush_hash_range)(long unsigned int, int);\n\tvoid (*hugepage_invalidate)(long unsigned int, long unsigned int, unsigned char *, int, int, int);\n\tint (*resize_hpt)(long unsigned int);\n\tvoid (*hpte_clear_all)(void);\n};\n\nstruct mmu_interval_notifier_ops;\n\nstruct mmu_interval_notifier {\n\tstruct interval_tree_node interval_tree;\n\tconst struct mmu_interval_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct hlist_node deferred_item;\n\tlong unsigned int invalidate_seq;\n};\n\nstruct mmu_notifier_range;\n\nstruct mmu_interval_notifier_ops {\n\tbool (*invalidate)(struct mmu_interval_notifier *, const struct mmu_notifier_range *, long unsigned int);\n};\n\nstruct mmu_notifier_ops {\n\tvoid (*release)(struct mmu_notifier *, struct mm_struct *);\n\tint (*clear_flush_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*clear_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*test_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int);\n\tint (*invalidate_range_start)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range_end)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*arch_invalidate_secondary_tlbs)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tstruct mmu_notifier * (*alloc_notifier)(struct mm_struct *);\n\tvoid (*free_notifier)(struct mmu_notifier *);\n};\n\nstruct mmu_notifier_range {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int flags;\n\tenum mmu_notifier_event event;\n\tvoid *owner;\n};\n\nstruct mmu_notifier_subscriptions {\n\tstruct hlist_head list;\n\tbool has_itree;\n\tspinlock_t lock;\n\tlong unsigned int invalidate_seq;\n\tlong unsigned int active_invalidate_ranges;\n\tstruct rb_root_cached itree;\n\twait_queue_head_t wq;\n\tstruct hlist_head deferred_list;\n};\n\nstruct mmu_psize_def {\n\tunsigned int shift;\n\tint penc[16];\n\tunsigned int tlbiel;\n\tlong unsigned int avpnm;\n\tlong unsigned int h_rpt_pgsize;\n\tunion {\n\t\tlong unsigned int sllp;\n\t\tlong unsigned int ap;\n\t};\n};\n\nstruct mmu_table_batch {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tvoid *tables[0];\n};\n\nstruct mnt_id_req {\n\t__u32 size;\n\tunion {\n\t\t__u32 mnt_ns_fd;\n\t\t__u32 mnt_fd;\n\t};\n\t__u64 mnt_id;\n\t__u64 param;\n\t__u64 mnt_ns_id;\n};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tunion {\n\t\tstruct {\n\t\t\tstruct uid_gid_extent extent[5];\n\t\t\tu32 nr_extents;\n\t\t};\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct mnt_idmap {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\trefcount_t count;\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct {\n\t\tstruct rb_root mounts;\n\t\tstruct rb_node *mnt_last_node;\n\t\tstruct rb_node *mnt_first_node;\n\t};\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\twait_queue_head_t poll;\n\tu64 seq_origin;\n\tu64 event;\n\t__u32 n_fsnotify_mask;\n\tstruct fsnotify_mark_connector *n_fsnotify_marks;\n\tunsigned int nr_mounts;\n\tunsigned int pending_mounts;\n\trefcount_t passive;\n\tbool is_anon;\n\tlong: 64;\n};\n\nstruct mnt_ns_info {\n\t__u32 size;\n\t__u32 nr_mounts;\n\t__u64 mnt_ns_id;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct mod_arch_specific {\n\tunsigned int stubs_section;\n\tunsigned int stub_count;\n\tunsigned int toc_section;\n\tbool toc_fixed;\n\tlong unsigned int tramp;\n\tlong unsigned int tramp_regs;\n\tstruct ftrace_ool_stub *ool_stubs;\n\tunsigned int ool_stub_count;\n\tunsigned int ool_stub_index;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *init_text;\n\tvoid *init_data;\n\tvoid *init_rodata;\n};\n\nstruct mod_kallsyms {\n\tElf64_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct mode_map {\n\tint vmode;\n\tconst struct fb_videomode *mode;\n};\n\nstruct mode_page_header {\n\t__be16 mode_data_length;\n\t__u8 medium_type;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 reserved3;\n\t__be16 desc_length;\n};\n\nstruct modesel_head {\n\t__u8 reserved1;\n\t__u8 medium;\n\t__u8 reserved2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_of_blocks_hi;\n\t__u8 number_of_blocks_med;\n\t__u8 number_of_blocks_lo;\n\t__u8 reserved3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\nstruct pkcs7_message;\n\nstruct modsig {\n\tstruct pkcs7_message *pkcs7_msg;\n\tenum hash_algo hash_algo;\n\tconst u8 *digest;\n\tu32 digest_size;\n\tint raw_pkcs7_len;\n\tu8 raw_pkcs7[0];\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct module_memory {\n\tvoid *base;\n\tbool is_rox;\n\tunsigned int size;\n\tstruct mod_tree_node mtn;\n};\n\ntypedef struct tracepoint * const tracepoint_ptr_t;\n\nstruct module_attribute;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_event_call;\n\nstruct trace_eval_map;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[56];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst u32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst u32 *gpl_crcs;\n\tbool using_gplonly_symbols;\n\tbool sig_ok;\n\tbool async_probe_requested;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)(void);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct module_memory mem[7];\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tunsigned int btf_data_size;\n\tunsigned int btf_base_data_size;\n\tvoid *btf_data;\n\tvoid *btf_base_data;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tunsigned int num_ftrace_callsites;\n\tlong unsigned int *ftrace_callsites;\n\tvoid *kprobes_text_start;\n\tunsigned int kprobes_text_size;\n\tlong unsigned int *kprobe_blacklist;\n\tunsigned int num_kprobe_blacklist;\n\tint num_kunit_init_suites;\n\tstruct kunit_suite **kunit_init_suites;\n\tint num_kunit_suites;\n\tstruct kunit_suite **kunit_suites;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)(void);\n\tatomic_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(const struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(const struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct module_notes_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_module_power_mode_params power;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct module_signature {\n\tu8 algo;\n\tu8 hash;\n\tu8 id_type;\n\tu8 signer_len;\n\tu8 key_id_len;\n\tu8 __pad[3];\n\t__be32 sig_len;\n};\n\nstruct module_string {\n\tstruct list_head next;\n\tstruct module *module;\n\tchar *str;\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct modversion_info {\n\tlong unsigned int crc;\n\tchar name[56];\n};\n\nstruct modversion_info_ext {\n\tsize_t remaining;\n\tconst u32 *crc;\n\tconst char *name;\n};\n\nstruct monitor_map {\n\tint sense;\n\tint vmode;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct rb_node mnt_node;\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct mount *mnt_next_for_sb;\n\tstruct mount **mnt_pprev_for_sb;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct hlist_head mnt_slave_list;\n\tstruct hlist_node mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tstruct list_head to_notify;\n\tstruct mnt_namespace *prev_ns;\n\tint mnt_t_flags;\n\tint mnt_id;\n\tu64 mnt_id_unique;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n\tstruct mount *overmount;\n};\n\nstruct mount_attr {\n\t__u64 attr_set;\n\t__u64 attr_clr;\n\t__u64 propagation;\n\t__u64 userns_fd;\n};\n\nstruct mount_kattr {\n\tunsigned int attr_set;\n\tunsigned int attr_clr;\n\tunsigned int propagation;\n\tunsigned int lookup_flags;\n\tenum mount_kattr_flags_t kflags;\n\tstruct user_namespace *mnt_userns;\n\tstruct mnt_idmap *mnt_idmap;\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n};\n\nstruct mountres {\n\tint errno;\n\tstruct nfs_fh *fh;\n\tunsigned int *auth_count;\n\trpc_authflavor_t *auth_flavors;\n};\n\nstruct movable_operations {\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tint (*migrate_page)(struct page *, struct page *, enum migrate_mode);\n\tvoid (*putback_page)(struct page *);\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tunsigned int can_map: 1;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tloff_t end_pos;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n\tunsigned int journalled_more_data: 1;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct folio *folio;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpic_reg_bank {\n\tu32 *base;\n};\n\nstruct msi_bitmap {\n\tstruct device_node *of_node;\n\tlong unsigned int *bitmap;\n\tspinlock_t lock;\n\tunsigned int irq_count;\n\tbool bitmap_from_slab;\n};\n\nstruct mpic_irq_save;\n\nstruct mpic {\n\tstruct device_node *node;\n\tstruct irq_domain *irqhost;\n\tstruct irq_chip hc_irq;\n\tstruct irq_chip hc_ipi;\n\tstruct irq_chip hc_tm;\n\tstruct irq_chip hc_err;\n\tconst char *name;\n\tunsigned int flags;\n\tunsigned int isu_size;\n\tunsigned int isu_shift;\n\tunsigned int isu_mask;\n\tunsigned int num_sources;\n\tunsigned int ipi_vecs[4];\n\tunsigned int timer_vecs[8];\n\tunsigned int err_int_vecs[32];\n\tunsigned int spurious_vec;\n\tenum mpic_reg_type reg_type;\n\tphys_addr_t paddr;\n\tstruct mpic_reg_bank thiscpuregs;\n\tstruct mpic_reg_bank gregs;\n\tstruct mpic_reg_bank tmregs;\n\tstruct mpic_reg_bank cpuregs[32];\n\tstruct mpic_reg_bank isus[32];\n\tu32 *err_regs;\n\tlong unsigned int *protected;\n\tstruct msi_bitmap msi_bitmap;\n\tstruct mpic *next;\n\tstruct mpic_irq_save *save_data;\n};\n\nstruct mpic_irq_save {\n\tu32 vecprio;\n\tu32 dest;\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct mptcp_out_options {};\n\nstruct mptcp_sock {};\n\nstruct mq_inflight {\n\tstruct block_device *part;\n\tunsigned int inflight[2];\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nstruct mqueue_fs_context {\n\tstruct ipc_namespace *ipc_ns;\n\tbool newns;\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[12];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\nstruct posix_msg_tree_node;\n\nstruct mqueue_inode_info {\n\tspinlock_t lock;\n\tstruct inode vfs_inode;\n\twait_queue_head_t wait_q;\n\tstruct rb_root msg_tree;\n\tstruct rb_node *msg_tree_rightmost;\n\tstruct posix_msg_tree_node *node_cache;\n\tstruct mq_attr attr;\n\tstruct sigevent notify;\n\tstruct pid *notify_owner;\n\tu32 notify_self_exec_id;\n\tstruct user_namespace *notify_user_ns;\n\tstruct ucounts *ucounts;\n\tstruct sock *notify_sock;\n\tstruct sk_buff *notify_cookie;\n\tstruct ext_wait_queue e_wait_q[2];\n\tlong unsigned int qsize;\n};\n\nstruct mrw_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u8 write: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n\t__u8 reserved4;\n\t__u8 reserved5;\n};\n\nstruct ms_data {\n\tlong unsigned int quirks;\n\tstruct hid_device *hdev;\n\tstruct work_struct ff_worker;\n\t__u8 strong;\n\t__u8 weak;\n\tvoid *output_report_dmabuf;\n};\n\nstruct msdos_dir_entry {\n\t__u8 name[11];\n\t__u8 attr;\n\t__u8 lcase;\n\t__u8 ctime_cs;\n\t__le16 ctime;\n\t__le16 cdate;\n\t__le16 adate;\n\t__le16 starthi;\n\t__le16 time;\n\t__le16 date;\n\t__le16 start;\n\t__le32 size;\n};\n\nstruct msdos_dir_slot {\n\t__u8 id;\n\t__u8 name0_4[10];\n\t__u8 attr;\n\t__u8 reserved;\n\t__u8 alias_checksum;\n\t__u8 name5_10[12];\n\t__le16 start;\n\t__u8 name11_12[4];\n};\n\nstruct msdos_inode_info {\n\tspinlock_t cache_lru_lock;\n\tstruct list_head cache_lru;\n\tint nr_caches;\n\tunsigned int cache_valid_id;\n\tloff_t mmu_private;\n\tint i_start;\n\tint i_logstart;\n\tint i_attrs;\n\tloff_t i_pos;\n\tstruct hlist_node i_fat_hash;\n\tstruct hlist_node i_dir_hash;\n\tstruct rw_semaphore truncate_lock;\n\tstruct timespec64 i_crtime;\n\tstruct inode vfs_inode;\n};\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nstruct msdos_sb_info {\n\tshort unsigned int sec_per_clus;\n\tshort unsigned int cluster_bits;\n\tunsigned int cluster_size;\n\tunsigned char fats;\n\tunsigned char fat_bits;\n\tshort unsigned int fat_start;\n\tlong unsigned int fat_length;\n\tlong unsigned int dir_start;\n\tshort unsigned int dir_entries;\n\tlong unsigned int data_start;\n\tlong unsigned int max_cluster;\n\tlong unsigned int root_cluster;\n\tlong unsigned int fsinfo_sector;\n\tstruct mutex fat_lock;\n\tstruct mutex nfs_build_inode_lock;\n\tstruct mutex s_lock;\n\tunsigned int prev_free;\n\tunsigned int free_clusters;\n\tunsigned int free_clus_valid;\n\tstruct fat_mount_options options;\n\tstruct nls_table *nls_disk;\n\tstruct nls_table *nls_io;\n\tconst void *dir_ops;\n\tint dir_per_block;\n\tint dir_per_block_bits;\n\tunsigned int vol_id;\n\tint fatent_shift;\n\tconst struct fatent_operations *fatent_ops;\n\tstruct inode *fat_inode;\n\tstruct inode *fsinfo_inode;\n\tstruct ratelimit_state ratelimit;\n\tspinlock_t inode_hash_lock;\n\tstruct hlist_head inode_hashtable[256];\n\tspinlock_t dir_hash_lock;\n\tstruct hlist_head dir_hashtable[256];\n\tunsigned int dirty;\n\tstruct callback_head rcu;\n};\n\nstruct phy_mse_capability {\n\tu64 max_average_mse;\n\tu64 max_peak_mse;\n\tu64 refresh_rate_ps;\n\tu64 num_symbols;\n\tu32 supported_caps;\n};\n\nstruct mse_snapshot_entry;\n\nstruct mse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_mse_capability capability;\n\tstruct mse_snapshot_entry *snapshots;\n\tunsigned int num_snapshots;\n};\n\nstruct phy_mse_snapshot {\n\tu64 average_mse;\n\tu64 peak_mse;\n\tu64 worst_peak_mse;\n};\n\nstruct mse_snapshot_entry {\n\tstruct phy_mse_snapshot snapshot;\n\tint channel;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_security_struct {\n\tu32 sid;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\nstruct msi_alloc_info {\n\tstruct msi_desc *desc;\n\tirq_hw_number_t hwirq;\n\tlong unsigned int flags;\n\tunion {\n\t\tlong unsigned int ul;\n\t\tvoid *ptr;\n\t} scratchpad[2];\n};\n\ntypedef struct msi_alloc_info msi_alloc_info_t;\n\nstruct msi_counts {\n\tstruct device_node *requestor;\n\tint num_devices;\n\tint request;\n\tint quota;\n\tint spare;\n\tint over_quota;\n};\n\nstruct msi_ctrl {\n\tunsigned int domid;\n\tunsigned int first;\n\tunsigned int last;\n\tunsigned int nirqs;\n};\n\nstruct msi_msg {\n\tunion {\n\t\tu32 address_lo;\n\t\tarch_msi_msg_addr_lo_t arch_addr_lo;\n\t};\n\tunion {\n\t\tu32 address_hi;\n\t\tarch_msi_msg_addr_hi_t arch_addr_hi;\n\t};\n\tunion {\n\t\tu32 data;\n\t\tarch_msi_msg_data_t arch_data;\n\t};\n};\n\nstruct pci_msi_desc {\n\tunion {\n\t\tu32 msi_mask;\n\t\tu32 msix_ctrl;\n\t};\n\tstruct {\n\t\tu8 is_msix: 1;\n\t\tu8 multiple: 3;\n\t\tu8 multi_cap: 3;\n\t\tu8 can_mask: 1;\n\t\tu8 is_64: 1;\n\t\tu8 is_virtual: 1;\n\t\tunsigned int default_irq;\n\t} msi_attrib;\n\tunion {\n\t\tu8 mask_pos;\n\t\tvoid *mask_base;\n\t};\n};\n\nunion msi_domain_cookie {\n\tu64 value;\n\tvoid *ptr;\n\tvoid *iobase;\n};\n\nunion msi_instance_cookie {\n\tu64 value;\n\tvoid *ptr;\n};\n\nstruct msi_desc_data {\n\tunion msi_domain_cookie dcookie;\n\tunion msi_instance_cookie icookie;\n};\n\nstruct msi_desc {\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tstruct device_attribute *sysfs_attrs;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tu16 msi_index;\n\tunion {\n\t\tstruct pci_msi_desc pci;\n\t\tstruct msi_desc_data data;\n\t};\n};\n\nstruct msi_dev_domain {\n\tstruct xarray store;\n\tstruct irq_domain *domain;\n};\n\nstruct msi_device_data {\n\tlong unsigned int properties;\n\tstruct mutex mutex;\n\tstruct msi_dev_domain __domains[1];\n\tlong unsigned int __iter_idx;\n};\n\nstruct msi_domain_ops;\n\nstruct msi_domain_info {\n\tu32 flags;\n\tenum irq_domain_bus_token bus_token;\n\tunsigned int hwsize;\n\tstruct msi_domain_ops *ops;\n\tstruct device *dev;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tmsi_alloc_info_t *alloc_data;\n\tvoid *data;\n};\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_teardown)(struct irq_domain *, msi_alloc_info_t *);\n\tvoid (*prepare_desc)(struct irq_domain *, msi_alloc_info_t *, struct msi_desc *);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*domain_alloc_irqs)(struct irq_domain *, struct device *, int);\n\tvoid (*domain_free_irqs)(struct irq_domain *, struct device *);\n\tint (*msi_translate)(struct irq_domain *, struct irq_fwspec *, irq_hw_number_t *, unsigned int *);\n};\n\nstruct msi_domain_template {\n\tchar name[48];\n\tstruct irq_chip chip;\n\tstruct msi_domain_ops ops;\n\tstruct msi_domain_info info;\n\tmsi_alloc_info_t alloc_info;\n};\n\nstruct msi_map {\n\tint index;\n\tint virq;\n};\n\nstruct msi_parent_ops {\n\tu32 supported_flags;\n\tu32 required_flags;\n\tu32 chip_flags;\n\tu32 bus_select_token;\n\tu32 bus_select_mask;\n\tconst char *prefix;\n\tbool (*init_dev_msi_info)(struct device *, struct irq_domain *, struct irq_domain *, struct msi_domain_info *);\n};\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong int msg_stime;\n\tlong int msg_rtime;\n\tlong int msg_ctime;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct mthp_stat {\n\tlong unsigned int stats[153];\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n\tvoid *magic;\n};\n\nstruct mv_cached_regs {\n\tu32 fiscfg;\n\tu32 ltmode;\n\tu32 haltcond;\n\tu32 unknown_rsvd;\n};\n\nstruct mv_crpb {\n\t__le16 id;\n\t__le16 flags;\n\t__le32 tmstmp;\n};\n\nstruct mv_crqb {\n\t__le32 sg_addr;\n\t__le32 sg_addr_hi;\n\t__le16 ctrl_flags;\n\t__le16 ata_cmd[11];\n};\n\nstruct mv_crqb_iie {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 flags;\n\t__le32 len;\n\t__le32 ata_cmd[4];\n};\n\nstruct mv_port_signal {\n\tu32 amps;\n\tu32 pre;\n};\n\nstruct mv_hw_ops;\n\nstruct mv_host_priv {\n\tu32 hp_flags;\n\tunsigned int board_idx;\n\tu32 main_irq_mask;\n\tstruct mv_port_signal signal[8];\n\tconst struct mv_hw_ops *ops;\n\tint n_ports;\n\tvoid *base;\n\tvoid *main_irq_cause_addr;\n\tvoid *main_irq_mask_addr;\n\tu32 irq_cause_offset;\n\tu32 irq_mask_offset;\n\tu32 unmask_all_irqs;\n\tstruct clk *clk;\n\tstruct clk **port_clks;\n\tstruct phy___2 **port_phys;\n\tstruct dma_pool *crqb_pool;\n\tstruct dma_pool *crpb_pool;\n\tstruct dma_pool *sg_tbl_pool;\n};\n\nstruct mv_hw_ops {\n\tvoid (*phy_errata)(struct mv_host_priv *, void *, unsigned int);\n\tvoid (*enable_leds)(struct mv_host_priv *, void *);\n\tvoid (*read_preamp)(struct mv_host_priv *, int, void *);\n\tint (*reset_hc)(struct ata_host *, void *, unsigned int);\n\tvoid (*reset_flash)(struct mv_host_priv *, void *);\n\tvoid (*reset_bus)(struct ata_host *, void *);\n};\n\nstruct mv_sg;\n\nstruct mv_port_priv {\n\tstruct mv_crqb *crqb;\n\tdma_addr_t crqb_dma;\n\tstruct mv_crpb *crpb;\n\tdma_addr_t crpb_dma;\n\tstruct mv_sg *sg_tbl[32];\n\tdma_addr_t sg_tbl_dma[32];\n\tunsigned int req_idx;\n\tunsigned int resp_idx;\n\tu32 pp_flags;\n\tstruct mv_cached_regs cached;\n\tunsigned int delayed_eh_pmp_map;\n};\n\nstruct mv_sata_platform_data {\n\tint n_ports;\n};\n\nstruct mv_sg {\n\t__le32 addr;\n\t__le32 flags_size;\n\t__le32 addr_hi;\n\t__le32 reserved;\n};\n\nstruct my_u {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u0 {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u1 {\n\t__le64 a;\n\t__le64 b;\n\t__le64 c;\n\t__le64 d;\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[4];\n\tlong unsigned int overrun_time;\n\tunsigned int num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tu8 read_buf[4096];\n\tlong unsigned int read_flags[64];\n\tu8 echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tsize_t lookahead_count;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int state;\n\tunsigned int seq;\n\tunsigned int next_seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tconst char *pathname;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tvfsuid_t dir_vfsuid;\n\tumode_t dir_mode;\n};\n\nstruct page_frag_cache {\n\tlong unsigned int encoded_page;\n\t__u32 offset;\n\t__u32 pagecnt_bias;\n};\n\nstruct napi_alloc_cache {\n\tlocal_lock_t bh_lock;\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[128];\n};\n\nstruct napi_config {\n\tu64 gro_flush_timeout;\n\tu64 irq_suspend_timeout;\n\tu32 defer_hard_irqs;\n\tcpumask_t affinity_mask;\n\tu8 threaded;\n\tunsigned int napi_id;\n};\n\nstruct napi_gro_cb {\n\tunion {\n\t\tstruct {\n\t\t\tvoid *frag0;\n\t\t\tunsigned int frag0_len;\n\t\t};\n\t\tstruct {\n\t\t\tstruct sk_buff *last;\n\t\t\tlong unsigned int age;\n\t\t};\n\t};\n\tint data_offset;\n\tu16 flush;\n\tu16 count;\n\tu16 proto;\n\tu16 pad;\n\tunion {\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t};\n\t\tstruct {\n\t\t\tu16 gro_remcsum_start;\n\t\t\tu8 same_flow: 1;\n\t\t\tu8 encap_mark: 1;\n\t\t\tu8 csum_valid: 1;\n\t\t\tu8 csum_cnt: 3;\n\t\t\tu8 free: 2;\n\t\t\tu8 is_fou: 1;\n\t\t\tu8 ip_fixedid: 2;\n\t\t\tu8 recursion_counter: 4;\n\t\t\tu8 is_flist: 1;\n\t\t} zeroed;\n\t};\n\t__wsum csum;\n\tunion {\n\t\tstruct {\n\t\t\tu16 network_offset;\n\t\t\tu16 inner_network_offset;\n\t\t};\n\t\tu16 network_offsets[2];\n\t};\n};\n\nstruct nat_keepalive {\n\tstruct net *net;\n\tu16 family;\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\t__u32 smark;\n};\n\nstruct nat_keepalive_work_ctx {\n\ttime64_t next_run;\n\ttime64_t now;\n};\n\nstruct nbcon_state {\n\tunion {\n\t\tunsigned int atom;\n\t\tstruct {\n\t\t\tunsigned int prio: 2;\n\t\t\tunsigned int req_prio: 2;\n\t\t\tunsigned int unsafe: 1;\n\t\t\tunsigned int unsafe_takeover: 1;\n\t\t\tunsigned int cpu: 24;\n\t\t};\n\t};\n};\n\nstruct nbcon_write_context {\n\tstruct nbcon_context ctxt;\n\tchar *outbuf;\n\tunsigned int len;\n\tbool unsafe_takeover;\n};\n\nstruct nd_namespace_common;\n\nstruct nd_btt {\n\tstruct device dev;\n\tstruct nd_namespace_common *ndns;\n\tstruct btt *btt;\n\tlong unsigned int lbasize;\n\tu64 size;\n\tuuid_t *uuid;\n\tint id;\n\tint initial_offset;\n\tu16 version_major;\n\tu16 version_minor;\n};\n\nstruct nd_cmd_ars_cap {\n\t__u64 address;\n\t__u64 length;\n\t__u32 status;\n\t__u32 max_ars_out;\n\t__u32 clear_err_unit;\n\t__u16 flags;\n\t__u16 reserved;\n};\n\nstruct nd_cmd_clear_error {\n\t__u64 address;\n\t__u64 length;\n\t__u32 status;\n\t__u8 reserved[4];\n\t__u64 cleared;\n};\n\nstruct nd_cmd_desc {\n\tint in_num;\n\tint out_num;\n\tu32 in_sizes[5];\n\tint out_sizes[5];\n};\n\nstruct nd_cmd_get_config_data_hdr {\n\t__u32 in_offset;\n\t__u32 in_length;\n\t__u32 status;\n\t__u8 out_buf[0];\n};\n\nstruct nd_cmd_get_config_size {\n\t__u32 status;\n\t__u32 config_size;\n\t__u32 max_xfer;\n};\n\nstruct nd_cmd_pkg {\n\t__u64 nd_family;\n\t__u64 nd_command;\n\t__u32 nd_size_in;\n\t__u32 nd_size_out;\n\t__u32 nd_reserved2[9];\n\t__u32 nd_fw_size;\n\tunsigned char nd_payload[0];\n};\n\nstruct nd_cmd_set_config_hdr {\n\t__u32 in_offset;\n\t__u32 in_length;\n\t__u8 in_buf[0];\n};\n\nstruct nd_cmd_vendor_hdr {\n\t__u32 opcode;\n\t__u32 in_length;\n\t__u8 in_buf[0];\n};\n\nstruct nd_pfn_sb;\n\nstruct nd_pfn {\n\tint id;\n\tuuid_t *uuid;\n\tstruct device dev;\n\tlong unsigned int align;\n\tlong unsigned int npfns;\n\tenum nd_pfn_mode mode;\n\tstruct nd_pfn_sb *pfn_sb;\n\tstruct nd_namespace_common *ndns;\n};\n\nstruct nd_dax {\n\tstruct nd_pfn nd_pfn;\n};\n\nstruct nd_device_driver {\n\tstruct device_driver drv;\n\tlong unsigned int type;\n\tint (*probe)(struct device *);\n\tvoid (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tvoid (*notify)(struct device *, enum nvdimm_event);\n};\n\nstruct nd_gen_sb {\n\tchar reserved[4088];\n\t__le64 checksum;\n};\n\nstruct nd_interleave_set {\n\tu64 cookie1;\n\tu64 cookie2;\n\tu64 altcookie;\n\tguid_t type_guid;\n};\n\nstruct nd_namespace_label;\n\nstruct nd_label_ent {\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tstruct nd_namespace_label *label;\n};\n\nstruct nd_label_id {\n\tchar id[50];\n};\n\nstruct nvdimm;\n\nstruct nvdimm_drvdata;\n\nstruct nd_mapping {\n\tstruct nvdimm *nvdimm;\n\tu64 start;\n\tu64 size;\n\tint position;\n\tstruct list_head labels;\n\tstruct mutex lock;\n\tstruct nvdimm_drvdata *ndd;\n};\n\nstruct nd_mapping_desc {\n\tstruct nvdimm *nvdimm;\n\tu64 start;\n\tu64 size;\n\tint position;\n};\n\nstruct nd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\t__u8 opt[0];\n};\n\nstruct nd_namespace_common {\n\tint force_raw;\n\tstruct device dev;\n\tstruct device *claim;\n\tenum nvdimm_claim_class claim_class;\n\tint (*rw_bytes)(struct nd_namespace_common *, resource_size_t, void *, size_t, int, long unsigned int);\n};\n\nstruct nd_namespace_index {\n\tu8 sig[16];\n\tu8 flags[3];\n\tu8 labelsize;\n\t__le32 seq;\n\t__le64 myoff;\n\t__le64 mysize;\n\t__le64 otheroff;\n\t__le64 labeloff;\n\t__le32 nslot;\n\t__le16 major;\n\t__le16 minor;\n\t__le64 checksum;\n\tu8 free[0];\n};\n\nstruct nd_namespace_io {\n\tstruct nd_namespace_common common;\n\tstruct resource res;\n\tresource_size_t size;\n\tvoid *addr;\n\tstruct badblocks bb;\n};\n\nstruct nvdimm_cxl_label {\n\tu8 type[16];\n\tu8 uuid[16];\n\tu8 name[64];\n\t__le32 flags;\n\t__le16 nrange;\n\t__le16 position;\n\t__le64 dpa;\n\t__le64 rawsize;\n\t__le32 slot;\n\t__le32 align;\n\tu8 region_uuid[16];\n\tu8 abstraction_uuid[16];\n\t__le16 lbasize;\n\tu8 reserved[86];\n\t__le64 checksum;\n};\n\nstruct nvdimm_efi_label {\n\tu8 uuid[16];\n\tu8 name[64];\n\t__le32 flags;\n\t__le16 nlabel;\n\t__le16 position;\n\t__le64 isetcookie;\n\t__le64 lbasize;\n\t__le64 dpa;\n\t__le64 rawsize;\n\t__le32 slot;\n\tu8 align;\n\tu8 reserved[3];\n\tguid_t type_guid;\n\tguid_t abstraction_guid;\n\tu8 reserved2[88];\n\t__le64 checksum;\n};\n\nstruct nd_namespace_label {\n\tunion {\n\t\tstruct nvdimm_cxl_label cxl;\n\t\tstruct nvdimm_efi_label efi;\n\t};\n};\n\nstruct nd_namespace_pmem {\n\tstruct nd_namespace_io nsio;\n\tlong unsigned int lbasize;\n\tchar *alt_name;\n\tuuid_t *uuid;\n\tint id;\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct nd_percpu_lane {\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct nd_pfn_sb {\n\tu8 signature[16];\n\tu8 uuid[16];\n\tu8 parent_uuid[16];\n\t__le32 flags;\n\t__le16 version_major;\n\t__le16 version_minor;\n\t__le64 dataoff;\n\t__le64 npfns;\n\t__le32 mode;\n\t__le32 start_pad;\n\t__le32 end_trunc;\n\t__le32 align;\n\t__le32 page_size;\n\t__le16 page_struct_size;\n\tu8 padding[3994];\n\t__le64 checksum;\n};\n\nstruct nd_region {\n\tstruct device dev;\n\tstruct ida ns_ida;\n\tstruct ida btt_ida;\n\tstruct ida pfn_ida;\n\tstruct ida dax_ida;\n\tlong unsigned int flags;\n\tstruct device *ns_seed;\n\tstruct device *btt_seed;\n\tstruct device *pfn_seed;\n\tstruct device *dax_seed;\n\tlong unsigned int align;\n\tu16 ndr_mappings;\n\tu64 ndr_size;\n\tu64 ndr_start;\n\tint id;\n\tint num_lanes;\n\tint ro;\n\tint numa_node;\n\tint target_node;\n\tvoid *provider_data;\n\tstruct kernfs_node *bb_state;\n\tstruct badblocks bb;\n\tstruct nd_interleave_set *nd_set;\n\tstruct nd_percpu_lane *lane;\n\tint (*flush)(struct nd_region *, struct bio *);\n\tstruct nd_mapping mapping[0];\n};\n\nstruct nd_region_data {\n\tint ns_count;\n\tint ns_active;\n\tunsigned int hints_shift;\n\tvoid *flush_wpq[0];\n};\n\nstruct nd_region_desc {\n\tstruct resource *res;\n\tstruct nd_mapping_desc *mapping;\n\tu16 num_mappings;\n\tconst struct attribute_group **attr_groups;\n\tstruct nd_interleave_set *nd_set;\n\tvoid *provider_data;\n\tint num_lanes;\n\tint numa_node;\n\tint target_node;\n\tlong unsigned int flags;\n\tint memregion;\n\tstruct device_node *of_node;\n\tint (*flush)(struct nd_region *, struct bio *);\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct ndo_fdb_dump_context {\n\tlong unsigned int ifindex;\n\tlong unsigned int fdb_idx;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct nduseroptmsg {\n\tunsigned char nduseropt_family;\n\tunsigned char nduseropt_pad1;\n\tshort unsigned int nduseropt_opts_len;\n\tint nduseropt_ifindex;\n\t__u8 nduseropt_icmp_type;\n\t__u8 nduseropt_icmp_code;\n\tshort unsigned int nduseropt_pad2;\n\tunsigned int nduseropt_pad3;\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_hash_table {\n\tstruct hlist_head *hash_heads;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tu32 qlen;\n\tint data[14];\n\tlong unsigned int data_state[1];\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct pneigh_entry;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tint (*is_multicast)(const void *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct delayed_work managed_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tspinlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct mutex phash_lock;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neighbour {\n\tstruct hlist_node hash;\n\tstruct hlist_node dev_list;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tu8 protocol;\n\tu32 flags;\n\tseqlock_t ha_lock;\n\tlong: 0;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct list_head managed_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tu8 primary_key[0];\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct ref_tracker_dir {\n\tspinlock_t lock;\n\tunsigned int quarantine_avail;\n\trefcount_t untracked;\n\trefcount_t no_tracker;\n\tbool dead;\n\tstruct list_head list;\n\tstruct list_head quarantine;\n\tconst char *class;\n};\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint sysctl_txq_reselection;\n\tint sysctl_optmem_max;\n\tu8 sysctl_txrehash;\n\tu8 sysctl_tstamp_allow_data;\n\tu8 sysctl_bypass_prot_mem;\n\tstruct prot_inuse *prot_inuse;\n\tstruct cpumask *rps_default_mask;\n};\n\nstruct tcp_mib;\n\nstruct udp_mib;\n\nstruct netns_mib {\n\tstruct ipstats_mib *ip_statistics;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct tcp_mib *tcp_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct udp_mib *udplite_statistics;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct unix_table {\n\tspinlock_t *locks;\n\tstruct hlist_head *buckets;\n};\n\nstruct netns_unix {\n\tstruct unix_table table;\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct blocking_notifier_head notifier_chain;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\nstruct netns_ipv4 {\n\t__u8 __cacheline_group_begin__netns_ipv4_read_tx[0];\n\tu8 sysctl_tcp_early_retrans;\n\tu8 sysctl_tcp_tso_win_divisor;\n\tu8 sysctl_tcp_tso_rtt_log;\n\tu8 sysctl_tcp_autocorking;\n\tint sysctl_tcp_min_snd_mss;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_wmem[3];\n\tu8 sysctl_ip_fwd_use_pmtu;\n\t__u8 __cacheline_group_end__netns_ipv4_read_tx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_end__netns_ipv4_read_txrx[0];\n\t__u8 __cacheline_group_begin__netns_ipv4_read_rx[0];\n\tu8 sysctl_tcp_moderate_rcvbuf;\n\tu8 sysctl_ip_early_demux;\n\tu8 sysctl_tcp_early_demux;\n\tu8 sysctl_tcp_l3mdev_accept;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_rcvbuf_low_rtt;\n\t__u8 __cacheline_group_end__netns_ipv4_read_rx[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__icmp[0];\n\tatomic_t icmp_global_credit;\n\tu32 icmp_global_stamp;\n\t__u8 __cacheline_group_end__icmp[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__icmp;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tstruct udp_table *udp_table;\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tbool fib_has_custom_local_routes;\n\tbool fib_offload_disabled;\n\tu8 sysctl_tcp_shrink_window;\n\tstruct hlist_head *fib_table_hash;\n\tstruct sock *fibnl;\n\tstruct hlist_head *fib_info_hash;\n\tunsigned int fib_info_hash_bits;\n\tunsigned int fib_info_cnt;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tu8 sysctl_icmp_echo_ignore_all;\n\tu8 sysctl_icmp_echo_enable_probe;\n\tu8 sysctl_icmp_echo_ignore_broadcasts;\n\tu8 sysctl_icmp_ignore_bogus_error_responses;\n\tu8 sysctl_icmp_errors_use_inbound_ifaddr;\n\tu8 sysctl_icmp_errors_extension_mask;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_msgs_per_sec;\n\tint sysctl_icmp_msgs_burst;\n\tu32 ip_rt_min_pmtu;\n\tint ip_rt_mtu_expires;\n\tint ip_rt_min_advmss;\n\tstruct local_ports ip_local_ports;\n\tu8 sysctl_tcp_ecn;\n\tu8 sysctl_tcp_ecn_option;\n\tu8 sysctl_tcp_ecn_option_beacon;\n\tu8 sysctl_tcp_ecn_fallback;\n\tu8 sysctl_ip_default_ttl;\n\tu8 sysctl_ip_no_pmtu_disc;\n\tu8 sysctl_ip_fwd_update_priority;\n\tu8 sysctl_ip_nonlocal_bind;\n\tu8 sysctl_ip_autobind_reuse;\n\tu8 sysctl_ip_dynaddr;\n\tu8 sysctl_udp_early_demux;\n\tu8 sysctl_nexthop_compat_mode;\n\tu8 sysctl_fwmark_reflect;\n\tu8 sysctl_tcp_fwmark_accept;\n\tu8 sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_intvl;\n\tu8 sysctl_tcp_keepalive_probes;\n\tu8 sysctl_tcp_syn_retries;\n\tu8 sysctl_tcp_synack_retries;\n\tu8 sysctl_tcp_syncookies;\n\tu8 sysctl_tcp_migrate_req;\n\tu8 sysctl_tcp_comp_sack_nr;\n\tu8 sysctl_tcp_backlog_ack_defer;\n\tu8 sysctl_tcp_pingpong_thresh;\n\tu8 sysctl_tcp_retries1;\n\tu8 sysctl_tcp_retries2;\n\tu8 sysctl_tcp_orphan_retries;\n\tu8 sysctl_tcp_tw_reuse;\n\tunsigned int sysctl_tcp_tw_reuse_delay;\n\tint sysctl_tcp_fin_timeout;\n\tu8 sysctl_tcp_sack;\n\tu8 sysctl_tcp_window_scaling;\n\tu8 sysctl_tcp_timestamps;\n\tint sysctl_tcp_rto_min_us;\n\tint sysctl_tcp_rto_max_ms;\n\tu8 sysctl_tcp_recovery;\n\tu8 sysctl_tcp_thin_linear_timeouts;\n\tu8 sysctl_tcp_slow_start_after_idle;\n\tu8 sysctl_tcp_retrans_collapse;\n\tu8 sysctl_tcp_stdurg;\n\tu8 sysctl_tcp_rfc1337;\n\tu8 sysctl_tcp_abort_on_overflow;\n\tu8 sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_adv_win_scale;\n\tu8 sysctl_tcp_dsack;\n\tu8 sysctl_tcp_app_win;\n\tu8 sysctl_tcp_frto;\n\tu8 sysctl_tcp_nometrics_save;\n\tu8 sysctl_tcp_no_ssthresh_metrics_save;\n\tu8 sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_challenge_ack_limit;\n\tu8 sysctl_tcp_min_tso_segs;\n\tu8 sysctl_tcp_reflect_tos;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tunsigned int sysctl_tcp_child_ehash_entries;\n\tint sysctl_tcp_comp_sack_rtt_percent;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tu32 tcp_challenge_timestamp;\n\tu32 tcp_challenge_count;\n\tu8 sysctl_tcp_plb_enabled;\n\tu8 sysctl_tcp_plb_idle_rehash_rounds;\n\tu8 sysctl_tcp_plb_rehash_rounds;\n\tu8 sysctl_tcp_plb_suspend_rto_sec;\n\tint sysctl_tcp_plb_cong_thresh;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tu8 sysctl_fib_notify_on_flag_change;\n\tu8 sysctl_tcp_syn_linear_timeouts;\n\tu8 sysctl_igmp_llm_reports;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tu16 ping_port_rover;\n\tatomic_t dev_addr_genid;\n\tunsigned int sysctl_udp_child_hash_entries;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tstruct hlist_head *inet_addr_lst;\n\tstruct delayed_work addr_chk_work;\n\tlong: 64;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tu32 multipath_hash_fields;\n\tu8 multipath_hash_policy;\n\t__u8 __cacheline_group_begin__sysctl_ipv6_flowlabel[0];\n\tu8 flowlabel_consistency;\n\tu8 auto_flowlabels;\n\tu8 flowlabel_state_ranges;\n\t__u8 __cacheline_group_end__sysctl_ipv6_flowlabel[0];\n\tu8 icmpv6_echo_ignore_all;\n\tu8 icmpv6_echo_ignore_multicast;\n\tu8 icmpv6_echo_ignore_anycast;\n\tint icmpv6_time;\n\tlong unsigned int icmpv6_ratemask[4];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tu8 anycast_src_echo_reply;\n\tu8 bindv6only;\n\tu8 ip_nonlocal_bind;\n\tu8 fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tu32 ioam6_id;\n\tu64 ioam6_id_wide;\n\tu8 skip_notify_on_dev_down;\n\tu8 fib_notify_on_flag_change;\n\tu8 icmpv6_error_anycast_as_unicast;\n\tu8 icmpv6_errors_extension_mask;\n};\n\nstruct rt6_statistics;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct dst_ops ip6_dst_ops;\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tspinlock_t fib_table_hash_lock;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tatomic_t ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned char flowlabel_has_excl;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct hlist_head *inet6_addr_lst;\n\tspinlock_t addrconf_hash_lock;\n\tstruct delayed_work addr_chk_work;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tstruct ioam6_pernet_data *ioam6_data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nf_logger;\n\nstruct nf_hook_entries;\n\nstruct netns_nf {\n\tstruct proc_dir_entry *proc_netfilter;\n\tconst struct nf_logger *nf_loggers[11];\n\tstruct ctl_table_header *nf_log_dir_header;\n\tstruct nf_hook_entries *hooks_ipv4[5];\n\tstruct nf_hook_entries *hooks_ipv6[5];\n\tunsigned int defrag_ipv4_users;\n\tunsigned int defrag_ipv6_users;\n};\n\nstruct nf_ct_event_notifier;\n\nstruct nf_generic_net {\n\tunsigned int timeout;\n};\n\nstruct nf_tcp_net {\n\tunsigned int timeouts[14];\n\tu8 tcp_loose;\n\tu8 tcp_be_liberal;\n\tu8 tcp_max_retrans;\n\tu8 tcp_ignore_invalid_rst;\n};\n\nstruct nf_udp_net {\n\tunsigned int timeouts[2];\n};\n\nstruct nf_icmp_net {\n\tunsigned int timeout;\n};\n\nstruct nf_ip_net {\n\tstruct nf_generic_net generic;\n\tstruct nf_tcp_net tcp;\n\tstruct nf_udp_net udp;\n\tstruct nf_icmp_net icmp;\n\tstruct nf_icmp_net icmpv6;\n};\n\nstruct netns_ct {\n\tu8 sysctl_log_invalid;\n\tu8 sysctl_events;\n\tu8 sysctl_acct;\n\tu8 sysctl_tstamp;\n\tu8 sysctl_checksum;\n\tstruct ip_conntrack_stat *stat;\n\tstruct nf_ct_event_notifier *nf_conntrack_event_cb;\n\tstruct nf_ip_net nf_ct_proto;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[2];\n\tstruct bpf_prog *progs[2];\n\tstruct list_head links[2];\n};\n\nstruct xfrm_policy_hash {\n\tstruct hlist_head *table;\n\tunsigned int hmask;\n\tu8 dbits4;\n\tu8 sbits4;\n\tu8 dbits6;\n\tu8 sbits6;\n};\n\nstruct xfrm_policy_hthresh {\n\tstruct work_struct work;\n\tseqlock_t lock;\n\tu8 lbits4;\n\tu8 rbits4;\n\tu8 lbits6;\n\tu8 rbits6;\n};\n\nstruct netns_xfrm {\n\tstruct list_head state_all;\n\tstruct hlist_head *state_bydst;\n\tstruct hlist_head *state_bysrc;\n\tstruct hlist_head *state_byspi;\n\tstruct hlist_head *state_byseq;\n\tstruct hlist_head *state_cache_input;\n\tunsigned int state_hmask;\n\tunsigned int state_num;\n\tstruct work_struct state_hash_work;\n\tstruct list_head policy_all;\n\tstruct hlist_head *policy_byidx;\n\tunsigned int policy_idx_hmask;\n\tunsigned int idx_generator;\n\tstruct xfrm_policy_hash policy_bydst[3];\n\tunsigned int policy_count[6];\n\tstruct work_struct policy_hash_work;\n\tstruct xfrm_policy_hthresh policy_hthresh;\n\tstruct list_head inexact_bins;\n\tstruct sock *nlsk;\n\tstruct sock *nlsk_stash;\n\tu32 sysctl_aevent_etime;\n\tu32 sysctl_aevent_rseqth;\n\tint sysctl_larval_drop;\n\tu32 sysctl_acq_expires;\n\tu8 policy_default[3];\n\tstruct ctl_table_header *sysctl_hdr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct dst_ops xfrm4_dst_ops;\n\tstruct dst_ops xfrm6_dst_ops;\n\tspinlock_t xfrm_state_lock;\n\tseqcount_spinlock_t xfrm_state_hash_generation;\n\tseqcount_spinlock_t xfrm_policy_hash_generation;\n\tspinlock_t xfrm_policy_lock;\n\tstruct mutex xfrm_cfg_mutex;\n\tstruct delayed_work nat_keepalive_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_base_seq;\n\tu32 ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node defer_free_list;\n\tstruct llist_node cleanup_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct ref_tracker_dir notrefcnt_tracker;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct xarray dev_by_index;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tbool is_dying;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct netns_nf nf;\n\tstruct netns_ct ct;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_xfrm xfrm;\n\tu64 net_cookie;\n\tstruct sock *diag_nlsk;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_aligned_data {\n\tatomic64_t net_cookie;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t tcp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t udp_memory_allocated;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_bridge;\n\nstruct net_bridge_vlan;\n\nstruct net_bridge_mcast {\n\tstruct net_bridge *br;\n\tstruct net_bridge_vlan *vlan;\n\tu32 multicast_last_member_count;\n\tu32 multicast_startup_query_count;\n\tu8 multicast_querier;\n\tu8 multicast_igmp_version;\n\tu8 multicast_router;\n\tu8 multicast_mld_version;\n\tlong unsigned int multicast_last_member_interval;\n\tlong unsigned int multicast_membership_interval;\n\tlong unsigned int multicast_querier_interval;\n\tlong unsigned int multicast_query_interval;\n\tlong unsigned int multicast_query_response_interval;\n\tlong unsigned int multicast_startup_query_interval;\n\tstruct hlist_head ip4_mc_router_list;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct bridge_mcast_other_query ip4_other_query;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct bridge_mcast_querier ip4_querier;\n\tstruct hlist_head ip6_mc_router_list;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct bridge_mcast_other_query ip6_other_query;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct bridge_mcast_querier ip6_querier;\n};\n\nstruct net_bridge {\n\tspinlock_t lock;\n\tspinlock_t hash_lock;\n\tstruct hlist_head frame_type_list;\n\tstruct net_device *dev;\n\tlong unsigned int options;\n\tstruct rhashtable fdb_hash_tbl;\n\tstruct list_head port_list;\n\tu16 group_fwd_mask;\n\tu16 group_fwd_mask_required;\n\tbridge_id designated_root;\n\tbridge_id bridge_id;\n\tunsigned char topology_change;\n\tunsigned char topology_change_detected;\n\tu16 root_port;\n\tlong unsigned int max_age;\n\tlong unsigned int hello_time;\n\tlong unsigned int forward_delay;\n\tlong unsigned int ageing_time;\n\tlong unsigned int bridge_max_age;\n\tlong unsigned int bridge_hello_time;\n\tlong unsigned int bridge_forward_delay;\n\tlong unsigned int bridge_ageing_time;\n\tu32 root_path_cost;\n\tu8 group_addr[6];\n\tenum {\n\t\tBR_NO_STP = 0,\n\t\tBR_KERNEL_STP = 1,\n\t\tBR_USER_STP = 2,\n\t} stp_enabled;\n\tstruct net_bridge_mcast multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 hash_max;\n\tspinlock_t multicast_lock;\n\tstruct rhashtable mdb_hash_tbl;\n\tstruct rhashtable sg_port_tbl;\n\tstruct hlist_head mcast_gc_list;\n\tstruct hlist_head mdb_list;\n\tstruct work_struct mcast_gc_work;\n\tstruct timer_list hello_timer;\n\tstruct timer_list tcn_timer;\n\tstruct timer_list topology_change_timer;\n\tstruct delayed_work gc_work;\n\tstruct kobject *ifobj;\n\tu32 auto_cnt;\n\tatomic_t fdb_n_learned;\n\tu32 fdb_max_learned;\n\tstruct hlist_head fdb_list;\n};\n\nstruct net_bridge_fdb_key {\n\tmac_addr addr;\n\tu16 vlan_id;\n};\n\nstruct net_bridge_port;\n\nstruct net_bridge_fdb_entry {\n\tstruct rhash_head rhnode;\n\tstruct net_bridge_port *dst;\n\tstruct net_bridge_fdb_key key;\n\tstruct hlist_node fdb_node;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_bridge_mcast_port {\n\tstruct net_bridge_port *port;\n\tstruct net_bridge_vlan *vlan;\n\tstruct bridge_mcast_own_query ip4_own_query;\n\tstruct timer_list ip4_mc_router_timer;\n\tstruct hlist_node ip4_rlist;\n\tstruct bridge_mcast_own_query ip6_own_query;\n\tstruct timer_list ip6_mc_router_timer;\n\tstruct hlist_node ip6_rlist;\n\tunsigned char multicast_router;\n\tu32 mdb_n_entries;\n\tu32 mdb_max_entries;\n};\n\nstruct netpoll;\n\nstruct net_bridge_port {\n\tstruct net_bridge *br;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tstruct net_bridge_port *backup_port;\n\tu32 backup_nhid;\n\tu8 priority;\n\tu8 state;\n\tu16 port_no;\n\tunsigned char topology_change_ack;\n\tunsigned char config_pending;\n\tport_id port_id;\n\tport_id designated_port;\n\tbridge_id designated_root;\n\tbridge_id designated_bridge;\n\tu32 path_cost;\n\tu32 designated_cost;\n\tlong unsigned int designated_age;\n\tstruct timer_list forward_delay_timer;\n\tstruct timer_list hold_timer;\n\tstruct timer_list message_age_timer;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n\tstruct net_bridge_mcast_port multicast_ctx;\n\tstruct bridge_mcast_stats *mcast_stats;\n\tu32 multicast_eht_hosts_limit;\n\tu32 multicast_eht_hosts_cnt;\n\tstruct hlist_head mglist;\n\tchar sysfs_name[16];\n\tstruct netpoll *np;\n\tu16 group_fwd_mask;\n\tu16 backup_redirected_cnt;\n\tstruct bridge_stp_xstats stp_xstats;\n};\n\nstruct pcpu_sw_netstats;\n\nstruct net_bridge_vlan {\n\tstruct rhash_head vnode;\n\tstruct rhash_head tnode;\n\tu16 vid;\n\tu16 flags;\n\tu16 priv_flags;\n\tu8 state;\n\tstruct pcpu_sw_netstats *stats;\n\tunion {\n\t\tstruct net_bridge *br;\n\t\tstruct net_bridge_port *port;\n\t};\n\tunion {\n\t\trefcount_t refcnt;\n\t\tstruct net_bridge_vlan *brvlan;\n\t};\n\tstruct br_tunnel_info tinfo;\n\tunion {\n\t\tstruct net_bridge_mcast br_mcast_ctx;\n\t\tstruct net_bridge_mcast_port port_mcast_ctx;\n\t};\n\tu16 msti;\n\tstruct list_head vlist;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct net_device_stats {\n\tunion {\n\t\tlong unsigned int rx_packets;\n\t\tatomic_long_t __rx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int tx_packets;\n\t\tatomic_long_t __tx_packets;\n\t};\n\tunion {\n\t\tlong unsigned int rx_bytes;\n\t\tatomic_long_t __rx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int tx_bytes;\n\t\tatomic_long_t __tx_bytes;\n\t};\n\tunion {\n\t\tlong unsigned int rx_errors;\n\t\tatomic_long_t __rx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_errors;\n\t\tatomic_long_t __tx_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_dropped;\n\t\tatomic_long_t __rx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int tx_dropped;\n\t\tatomic_long_t __tx_dropped;\n\t};\n\tunion {\n\t\tlong unsigned int multicast;\n\t\tatomic_long_t __multicast;\n\t};\n\tunion {\n\t\tlong unsigned int collisions;\n\t\tatomic_long_t __collisions;\n\t};\n\tunion {\n\t\tlong unsigned int rx_length_errors;\n\t\tatomic_long_t __rx_length_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_over_errors;\n\t\tatomic_long_t __rx_over_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_crc_errors;\n\t\tatomic_long_t __rx_crc_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_frame_errors;\n\t\tatomic_long_t __rx_frame_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_fifo_errors;\n\t\tatomic_long_t __rx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_missed_errors;\n\t\tatomic_long_t __rx_missed_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_aborted_errors;\n\t\tatomic_long_t __tx_aborted_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_carrier_errors;\n\t\tatomic_long_t __tx_carrier_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_fifo_errors;\n\t\tatomic_long_t __tx_fifo_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_heartbeat_errors;\n\t\tatomic_long_t __tx_heartbeat_errors;\n\t};\n\tunion {\n\t\tlong unsigned int tx_window_errors;\n\t\tatomic_long_t __tx_window_errors;\n\t};\n\tunion {\n\t\tlong unsigned int rx_compressed;\n\t\tatomic_long_t __rx_compressed;\n\t};\n\tunion {\n\t\tlong unsigned int tx_compressed;\n\t\tatomic_long_t __tx_compressed;\n\t};\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n\tstruct rb_root tree;\n};\n\nstruct sfp_bus;\n\nstruct udp_tunnel_nic;\n\nstruct net_device_ops;\n\nstruct xps_dev_maps;\n\nstruct pcpu_lstats;\n\nstruct pcpu_dstats;\n\nstruct netpoll_info;\n\nstruct netdev_name_node;\n\nstruct xdp_metadata_ops;\n\nstruct xsk_tx_metadata_ops;\n\nstruct net_device_core_stats;\n\nstruct vlan_info;\n\nstruct xdp_dev_bulk_queue;\n\nstruct netdev_stat_ops;\n\nstruct netdev_queue_mgmt_ops;\n\nstruct phy_link_topology;\n\nstruct udp_tunnel_nic_info;\n\nstruct netdev_config;\n\nstruct rtnl_hw_stats64;\n\nstruct net_device {\n\t__u8 __cacheline_group_begin__net_device_read_tx[0];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int priv_flags: 32;\n\t\t\tlong unsigned int lltx: 1;\n\t\t\tlong unsigned int netmem_tx: 1;\n\t\t} priv_flags_fast;\n\t};\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct header_ops *header_ops;\n\tstruct netdev_queue *_tx;\n\tnetdev_features_t gso_partial_features;\n\tunsigned int real_num_tx_queues;\n\tunsigned int gso_max_size;\n\tunsigned int gso_ipv4_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tunsigned int mtu;\n\tshort unsigned int needed_headroom;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tstruct xps_dev_maps *xps_maps[2];\n\tstruct nf_hook_entries *nf_hooks_egress;\n\tstruct bpf_mprog_entry *tcx_egress;\n\t__u8 __cacheline_group_end__net_device_read_tx[0];\n\t__u8 __cacheline_group_begin__net_device_read_txrx[0];\n\tunion {\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tlong unsigned int state;\n\tunsigned int flags;\n\tshort unsigned int hard_header_len;\n\tnetdev_features_t features;\n\tstruct inet6_dev *ip6_ptr;\n\t__u8 __cacheline_group_end__net_device_read_txrx[0];\n\t__u8 __cacheline_group_begin__net_device_read_rx[0];\n\tstruct bpf_prog *xdp_prog;\n\tstruct list_head ptype_specific;\n\tint ifindex;\n\tunsigned int real_num_rx_queues;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int gro_max_size;\n\tunsigned int gro_ipv4_max_size;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tpossible_net_t nd_net;\n\tstruct netpoll_info *npinfo;\n\tstruct bpf_mprog_entry *tcx_ingress;\n\t__u8 __cacheline_group_end__net_device_read_rx[0];\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\txdp_features_t xdp_features;\n\tconst struct xdp_metadata_ops *xdp_metadata_ops;\n\tconst struct xsk_tx_metadata_ops *xsk_tx_metadata_ops;\n\tshort unsigned int gflags;\n\tshort unsigned int needed_tailroom;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t mangleid_features;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tunsigned char min_header_len;\n\tunsigned char name_assign_type;\n\tint group;\n\tstruct net_device_stats stats;\n\tstruct net_device_core_stats *core_stats;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tunsigned int operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tu8 threaded;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tint irq;\n\tu32 priv_len;\n\tspinlock_t addr_list_lock;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tbool uc_promisc;\n\tstruct in_device *ip_ptr;\n\tstruct hlist_head fib_nh_head;\n\tstruct vlan_info *vlan_info;\n\tconst unsigned char *dev_addr;\n\tunsigned int num_rx_queues;\n\tunsigned int xdp_zc_max_segs;\n\tstruct netdev_queue *ingress_queue;\n\tstruct nf_hook_entries *nf_hooks_ingress;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tunsigned int num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct hlist_head qdisc_hash[16];\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tu32 proto_down_reason;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct ref_tracker_dir refcnt_tracker;\n\tstruct list_head link_watch_list;\n\tu8 reg_state;\n\tbool dismantle;\n\tbool moving_ns;\n\tbool rtnl_link_initializing;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tvoid *ml_priv;\n\tenum netdev_ml_priv_type ml_priv_type;\n\tenum netdev_stat_type pcpu_stat_type: 8;\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tconst struct netdev_stat_ops *stat_ops;\n\tconst struct netdev_queue_mgmt_ops *queue_mgmt_ops;\n\tunsigned int tso_max_size;\n\tu16 tso_max_segs;\n\tu8 prio_tc_map[16];\n\tstruct phy_link_topology *link_topo;\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tbool proto_down;\n\tbool irq_affinity_auto;\n\tbool rx_cpu_rmap_auto;\n\tlong unsigned int see_all_hwtstamp_requests: 1;\n\tlong unsigned int change_proto_down: 1;\n\tlong unsigned int netns_immutable: 1;\n\tlong unsigned int fcoe_mtu: 1;\n\tstruct list_head net_notifier_list;\n\tconst struct udp_tunnel_nic_info *udp_tunnel_nic_info;\n\tstruct udp_tunnel_nic *udp_tunnel_nic;\n\tstruct netdev_config *cfg;\n\tstruct netdev_config *cfg_pending;\n\tstruct ethtool_netdev_state *ethtool;\n\tstruct bpf_xdp_entity xdp_state[3];\n\tu8 dev_addr_shadow[32];\n\tnetdevice_tracker linkwatch_dev_tracker;\n\tnetdevice_tracker watchdog_dev_tracker;\n\tnetdevice_tracker dev_registered_tracker;\n\tstruct rtnl_hw_stats64 *offload_xstats_l3;\n\tstruct devlink_port *devlink_port;\n\tstruct hlist_head page_pools;\n\tstruct dim_irq_moder *irq_moder;\n\tu64 max_pacing_offload_horizon;\n\tstruct napi_config *napi_config;\n\tu32 num_napi_configs;\n\tu32 napi_defer_hard_irqs;\n\tlong unsigned int gro_flush_timeout;\n\tbool up;\n\tbool request_ops_lock;\n\tstruct mutex lock;\n\tstruct hlist_head neighbours[2];\n\tstruct hwtstamp_provider *hwprov;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 priv[0];\n};\n\nstruct net_device_core_stats {\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int rx_nohandler;\n\tlong unsigned int rx_otherhost_dropped;\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct rtnl_link_stats64;\n\nstruct netdev_bpf;\n\nstruct xdp_frame;\n\nstruct net_device_path_ctx;\n\nstruct net_device_path;\n\nstruct skb_shared_hwtstamps;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_eth_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocbond)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_siocwandev)(struct net_device *, struct if_settings *);\n\tint (*ndo_siocdevprivate)(struct net_device *, struct ifreq *, void *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tvoid (*ndo_poll_controller)(struct net_device *);\n\tint (*ndo_netpoll_setup)(struct net_device *);\n\tvoid (*ndo_netpoll_cleanup)(struct net_device *);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tstruct net_device * (*ndo_sk_get_lower_dev)(struct net_device *, struct sock *);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, bool *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del_bulk)(struct nlmsghdr *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_mdb_add)(struct net_device *, struct nlattr **, u16, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_del_bulk)(struct net_device *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*ndo_mdb_dump)(struct net_device *, struct sk_buff *, struct netlink_callback *);\n\tint (*ndo_mdb_get)(struct net_device *, struct nlattr **, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tstruct net_device * (*ndo_xdp_get_xmit_slave)(struct net_device *, struct xdp_buff *);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm_kern *, int);\n\tstruct net_device * (*ndo_get_peer_dev)(struct net_device *);\n\tint (*ndo_fill_forward_path)(struct net_device_path_ctx *, struct net_device_path *);\n\tktime_t (*ndo_get_tstamp)(struct net_device *, const struct skb_shared_hwtstamps *, bool);\n\tint (*ndo_hwtstamp_get)(struct net_device *, struct kernel_hwtstamp_config *);\n\tint (*ndo_hwtstamp_set)(struct net_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n};\n\nstruct net_device_path {\n\tenum net_device_path_type type;\n\tconst struct net_device *dev;\n\tunion {\n\t\tstruct {\n\t\t\tu16 id;\n\t\t\t__be16 proto;\n\t\t\tu8 h_dest[6];\n\t\t} encap;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct in_addr src_v4;\n\t\t\t\tstruct in6_addr src_v6;\n\t\t\t};\n\t\t\tunion {\n\t\t\t\tstruct in_addr dst_v4;\n\t\t\t\tstruct in6_addr dst_v6;\n\t\t\t};\n\t\t\tu8 l3_proto;\n\t\t} tun;\n\t\tstruct {\n\t\t\tenum {\n\t\t\t\tDEV_PATH_BR_VLAN_KEEP = 0,\n\t\t\t\tDEV_PATH_BR_VLAN_TAG = 1,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG = 2,\n\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW = 3,\n\t\t\t} vlan_mode;\n\t\t\tu16 vlan_id;\n\t\t\t__be16 vlan_proto;\n\t\t} bridge;\n\t\tstruct {\n\t\t\tint port;\n\t\t\tu16 proto;\n\t\t} dsa;\n\t\tstruct {\n\t\t\tu8 wdma_idx;\n\t\t\tu8 queue;\n\t\t\tu16 wcid;\n\t\t\tu8 bss;\n\t\t\tu8 amsdu;\n\t\t} mtk_wdma;\n\t};\n};\n\nstruct net_device_path_ctx {\n\tconst struct net_device *dev;\n\tu8 daddr[6];\n\tint num_vlans;\n\tstruct {\n\t\tu16 id;\n\t\t__be16 proto;\n\t} vlan[2];\n};\n\nstruct net_device_path_stack {\n\tint num_paths;\n\tstruct net_device_path path[5];\n};\n\nstruct net_devmem_dmabuf_binding {\n\tstruct dma_buf *dmabuf;\n\tstruct dma_buf_attachment *attachment;\n\tstruct sg_table *sgt;\n\tstruct net_device *dev;\n\tstruct gen_pool *chunk_pool;\n\tstruct mutex lock;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct xarray bound_rxqs;\n\tu32 id;\n\tenum dma_data_direction direction;\n\tstruct net_iov **tx_vec;\n\tstruct work_struct unbind_w;\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tstruct {\n\t\t\tstruct {} __empty_ptr;\n\t\t\tvoid *ptr[0];\n\t\t};\n\t};\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n\tu32 secret;\n};\n\nstruct net_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n\tu32 secret;\n};\n\nstruct rps_sock_flow_table;\n\nstruct skb_defer_node;\n\nstruct net_hotdata {\n\tstruct packet_offload ip_packet_offload;\n\tstruct net_offload tcpv4_offload;\n\tstruct net_protocol tcp_protocol;\n\tstruct net_offload udpv4_offload;\n\tstruct net_protocol udp_protocol;\n\tstruct packet_offload ipv6_packet_offload;\n\tstruct net_offload tcpv6_offload;\n\tstruct inet6_protocol tcpv6_protocol;\n\tstruct inet6_protocol udpv6_protocol;\n\tstruct net_offload udpv6_offload;\n\tstruct list_head offload_base;\n\tstruct kmem_cache *skbuff_cache;\n\tstruct kmem_cache *skbuff_fclone_cache;\n\tstruct kmem_cache *skb_small_head_cache;\n\tstruct rps_sock_flow_table *rps_sock_flow_table;\n\tu32 rps_cpu_mask;\n\tstruct skb_defer_node *skb_defer_nodes;\n\tint gro_normal_batch;\n\tint netdev_budget;\n\tint netdev_budget_usecs;\n\tint tstamp_prequeue;\n\tint max_backlog;\n\tint qdisc_max_burst;\n\tint dev_tx_weight;\n\tint dev_rx_weight;\n\tint sysctl_max_skb_frags;\n\tint sysctl_skb_defer_max;\n\tint sysctl_mem_pcpu_rsv;\n};\n\nstruct netmem_desc {\n\tlong unsigned int _flags;\n\tlong unsigned int pp_magic;\n\tstruct page_pool *pp;\n\tlong unsigned int _pp_mapping_pad;\n\tlong unsigned int dma_addr;\n\tatomic_long_t pp_ref_count;\n};\n\nstruct net_iov {\n\tunion {\n\t\tstruct netmem_desc desc;\n\t\tstruct {\n\t\t\tlong unsigned int _flags;\n\t\t\tlong unsigned int pp_magic;\n\t\t\tstruct page_pool *pp;\n\t\t\tlong unsigned int _pp_mapping_pad;\n\t\t\tlong unsigned int dma_addr;\n\t\t\tatomic_long_t pp_ref_count;\n\t\t};\n\t};\n\tstruct net_iov_area *owner;\n\tenum net_iov_type type;\n};\n\nstruct net_packet_attrs {\n\tconst unsigned char *src;\n\tconst unsigned char *dst;\n\tu32 ip_src;\n\tu32 ip_dst;\n\tbool tcp;\n\tu16 sport;\n\tu16 dport;\n\tint timeout;\n\tint size;\n\tint max_size;\n\tu8 id;\n\tu16 queue_mapping;\n\tbool bad_csum;\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_sync *bstats;\n\tspinlock_t *stats_lock;\n\tbool running;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct net_test {\n\tchar name[32];\n\tint (*fn)(struct net_device *);\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tstruct net *af_packet_net;\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct net_test_priv {\n\tstruct net_packet_attrs *packet;\n\tstruct packet_type pt;\n\tstruct completion comp;\n\tint double_vlan;\n\tint vlan_id;\n\tint ok;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nstruct netconsole_target_stats {\n\tu64_stats_t xmit_drop_count;\n\tu64_stats_t enomem_count;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct netpoll {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tchar dev_name[16];\n\tu8 dev_mac[6];\n\tconst char *name;\n\tunion inet_addr local_ip;\n\tunion inet_addr remote_ip;\n\tbool ipv6;\n\tu16 local_port;\n\tu16 remote_port;\n\tu8 remote_mac[6];\n\tstruct sk_buff_head skb_pool;\n\tstruct work_struct refill_wq;\n};\n\nstruct netconsole_target {\n\tstruct list_head list;\n\tstruct netconsole_target_stats stats;\n\tenum target_state state;\n\tbool extended;\n\tbool release;\n\tstruct netpoll np;\n\tchar buf[1000];\n\tstruct work_struct resume_wq;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct xsk_buff_pool;\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xsk_buff_pool *pool;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct netdev_config {\n\tu32 hds_thresh;\n\tu8 hds_config;\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tstruct rb_node node;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n\tstruct callback_head rcu;\n};\n\nstruct netdev_nested_priv {\n\tunsigned char flags;\n\tvoid *data;\n};\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct netdev_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tunsigned int rxq_idx;\n\tunsigned int txq_idx;\n\tunsigned int napi_id;\n};\n\nstruct netdev_nl_sock {\n\tstruct mutex lock;\n\tstruct list_head bindings;\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_offload_xstats_rd;\n\nstruct netdev_notifier_offload_xstats_ru;\n\nstruct netdev_notifier_offload_xstats_info {\n\tstruct netdev_notifier_info info;\n\tenum netdev_offload_xstats_type type;\n\tunion {\n\t\tstruct netdev_notifier_offload_xstats_rd *report_delta;\n\t\tstruct netdev_notifier_offload_xstats_ru *report_used;\n\t};\n};\n\nstruct rtnl_hw_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n};\n\nstruct netdev_notifier_offload_xstats_rd {\n\tstruct rtnl_hw_stats64 stats;\n\tbool used;\n};\n\nstruct netdev_notifier_offload_xstats_ru {\n\tbool used;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tlong unsigned int tx_maxrate;\n\tatomic_long_t trans_timeout;\n\tstruct net_device *sb_dev;\n\tlong: 64;\n\tstruct dql dql;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tstruct napi_struct *napi;\n\tint numa_node;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, struct netdev_queue *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, struct netdev_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_config {\n\tu32 rx_page_size;\n};\n\nstruct netdev_queue_mgmt_ops {\n\tsize_t ndo_queue_mem_size;\n\tint (*ndo_queue_mem_alloc)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tvoid (*ndo_queue_mem_free)(struct net_device *, void *);\n\tint (*ndo_queue_start)(struct net_device *, struct netdev_queue_config *, void *, int);\n\tint (*ndo_queue_stop)(struct net_device *, void *, int);\n\tvoid (*ndo_default_qcfg)(struct net_device *, struct netdev_queue_config *);\n\tint (*ndo_validate_qcfg)(struct net_device *, struct netdev_queue_config *, struct netlink_ext_ack *);\n\tstruct device * (*ndo_queue_get_dma_dev)(struct net_device *, int);\n\tunsigned int supported_params;\n};\n\nstruct netdev_queue_stats_rx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 alloc_fail;\n\tu64 hw_drops;\n\tu64 hw_drop_overruns;\n\tu64 csum_complete;\n\tu64 csum_unnecessary;\n\tu64 csum_none;\n\tu64 csum_bad;\n\tu64 hw_gro_packets;\n\tu64 hw_gro_bytes;\n\tu64 hw_gro_wire_packets;\n\tu64 hw_gro_wire_bytes;\n\tu64 hw_drop_ratelimits;\n};\n\nstruct netdev_queue_stats_tx {\n\tu64 bytes;\n\tu64 packets;\n\tu64 hw_drops;\n\tu64 hw_drop_errors;\n\tu64 csum_none;\n\tu64 needs_csum;\n\tu64 hw_gso_packets;\n\tu64 hw_gso_bytes;\n\tu64 hw_gso_wire_packets;\n\tu64 hw_gso_wire_bytes;\n\tu64 hw_drop_ratelimits;\n\tu64 stop;\n\tu64 wake;\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tu32 frag_size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pp_memory_provider_params {\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tu32 rx_page_size;\n};\n\nstruct rps_map;\n\nstruct rps_dev_flow_table;\n\nstruct netdev_rx_queue {\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tconst struct attribute_group **groups;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct napi_struct *napi;\n\tstruct netdev_queue_config qcfg;\n\tstruct pp_memory_provider_params mp_params;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netdev_stat_ops {\n\tvoid (*get_queue_stats_rx)(struct net_device *, int, struct netdev_queue_stats_rx *);\n\tvoid (*get_queue_stats_tx)(struct net_device *, int, struct netdev_queue_stats_tx *);\n\tvoid (*get_base_stats)(struct net_device *, struct netdev_queue_stats_rx *, struct netdev_queue_stats_tx *);\n};\n\nstruct netdev_xmit {\n\tu16 recursion;\n\tu8 more;\n\tu8 skip_txqueue;\n};\n\nstruct netevent_redirect {\n\tstruct dst_entry *old;\n\tstruct dst_entry *new;\n\tstruct neighbour *neigh;\n\tconst void *daddr;\n};\n\nstruct netif_security_struct {\n\tconst struct net *ns;\n\tint ifindex;\n\tu32 sid;\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tint flags;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tstruct netlink_ext_ack *extack;\n\tvoid *data;\n\tstruct module *module;\n\tu32 min_dump_alloc;\n\tint flags;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tconst struct nla_policy *policy;\n\tconst struct nlattr *miss_nest;\n\tu16 miss_type;\n\tu8 cookie[8];\n\tu8 cookie_len;\n\tchar _msg_buf[80];\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_policy_dump_state {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tlong unsigned int flags;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex nl_cb_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tvoid (*netlink_release)(struct sock *, long unsigned int *);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tvoid (*release)(struct sock *, long unsigned int *);\n\tint registered;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netnode_security_struct {\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} addr;\n\tu32 sid;\n\tu16 family;\n};\n\nstruct netpoll_info {\n\trefcount_t refcnt;\n\tstruct semaphore dev_lock;\n\tstruct sk_buff_head txq;\n\tstruct delayed_work tx_work;\n\tstruct callback_head rcu;\n};\n\nstruct netport_security_struct {\n\tu32 sid;\n\tu16 port;\n\tu8 protocol;\n};\n\nstruct netsfhdr {\n\t__be32 version;\n\t__be64 magic;\n\tu8 id;\n} __attribute__((packed));\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\tbool dead;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 weight_high;\n\t__u16 resvd2;\n};\n\nstruct nf_conntrack {\n\trefcount_t use;\n};\n\nunion nf_inet_addr {\n\t__u32 all[4];\n\t__be32 ip;\n\t__be32 ip6[4];\n\tstruct in_addr in;\n\tstruct in6_addr in6;\n};\n\nunion nf_conntrack_man_proto {\n\t__be16 all;\n\tstruct {\n\t\t__be16 port;\n\t} tcp;\n\tstruct {\n\t\t__be16 port;\n\t} udp;\n\tstruct {\n\t\t__be16 id;\n\t} icmp;\n\tstruct {\n\t\t__be16 port;\n\t} dccp;\n\tstruct {\n\t\t__be16 port;\n\t} sctp;\n\tstruct {\n\t\t__be16 key;\n\t} gre;\n};\n\nstruct nf_conntrack_man {\n\tunion nf_inet_addr u3;\n\tunion nf_conntrack_man_proto u;\n\tu_int16_t l3num;\n};\n\nstruct nf_conntrack_tuple {\n\tstruct nf_conntrack_man src;\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion {\n\t\t\t__be16 all;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} tcp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} udp;\n\t\t\tstruct {\n\t\t\t\tu_int8_t type;\n\t\t\t\tu_int8_t code;\n\t\t\t} icmp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} dccp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} sctp;\n\t\t\tstruct {\n\t\t\t\t__be16 key;\n\t\t\t} gre;\n\t\t} u;\n\t\tu_int8_t protonum;\n\t\tstruct {} __nfct_hash_offsetend;\n\t\tu_int8_t dir;\n\t} dst;\n};\n\nstruct nf_conntrack_tuple_hash {\n\tstruct hlist_nulls_node hnnode;\n\tstruct nf_conntrack_tuple tuple;\n};\n\nstruct nf_ct_udp {\n\tlong unsigned int stream_ts;\n};\n\nstruct nf_ct_gre {\n\tunsigned int stream_timeout;\n\tunsigned int timeout;\n};\n\nunion nf_conntrack_proto {\n\tstruct ip_ct_sctp sctp;\n\tstruct ip_ct_tcp tcp;\n\tstruct nf_ct_udp udp;\n\tstruct nf_ct_gre gre;\n\tunsigned int tmpl_padto;\n};\n\nstruct nf_ct_ext;\n\nstruct nf_conn {\n\tstruct nf_conntrack ct_general;\n\tspinlock_t lock;\n\tu32 timeout;\n\tstruct nf_conntrack_tuple_hash tuplehash[2];\n\tlong unsigned int status;\n\tpossible_net_t ct_net;\n\tstruct hlist_node nat_bysource;\n\tstruct {} __nfct_init_offset;\n\tstruct nf_conn *master;\n\tu_int32_t secmark;\n\tstruct nf_ct_ext *ext;\n\tunion nf_conntrack_proto proto;\n};\n\nstruct nf_conn___init {\n\tstruct nf_conn ct;\n};\n\nstruct nf_conn_labels {\n\tlong unsigned int bits[2];\n};\n\nstruct nf_conntrack_zone {\n\tu16 id;\n\tu8 flags;\n\tu8 dir;\n};\n\nstruct nf_ct_ext {\n\tu8 offset[4];\n\tu8 len;\n\tunsigned int gen_id;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct nf_ct_hook {\n\tint (*update)(struct net *, struct sk_buff *);\n\tvoid (*destroy)(struct nf_conntrack *);\n\tbool (*get_tuple_skb)(struct nf_conntrack_tuple *, const struct sk_buff *);\n\tvoid (*attach)(struct sk_buff *, const struct sk_buff *);\n\tvoid (*set_closing)(struct nf_conntrack *);\n\tint (*confirm)(struct sk_buff *);\n\tu32 (*get_id)(const struct nf_conntrack *);\n};\n\nstruct nf_defrag_hook {\n\tstruct module *owner;\n\tint (*enable)(struct net *);\n\tvoid (*disable)(struct net *);\n};\n\nstruct nf_hook_entry {\n\tnf_hookfn *hook;\n\tvoid *priv;\n};\n\nstruct nf_hook_entries {\n\tu16 num_hook_entries;\n\tstruct nf_hook_entry hooks[0];\n};\n\nstruct nf_hook_entries_rcu_head {\n\tstruct callback_head head;\n\tvoid *allocation;\n};\n\nstruct nf_hook_state {\n\tu8 hook;\n\tu8 pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nf_queue_entry;\n\nstruct nf_ipv6_ops {\n\tvoid (*route_input)(struct sk_buff *);\n\tint (*fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tint (*reroute)(struct sk_buff *, const struct nf_queue_entry *);\n};\n\nstruct nf_log_buf {\n\tunsigned int count;\n\tchar buf[1020];\n};\n\nstruct nf_loginfo;\n\ntypedef void nf_logfn(struct net *, u_int8_t, unsigned int, const struct sk_buff *, const struct net_device *, const struct net_device *, const struct nf_loginfo *, const char *);\n\nstruct nf_logger {\n\tchar *name;\n\tenum nf_log_type type;\n\tnf_logfn *logfn;\n\tstruct module *me;\n};\n\nstruct nf_loginfo {\n\tu_int8_t type;\n\tunion {\n\t\tstruct {\n\t\t\tu_int32_t copy_len;\n\t\t\tu_int16_t group;\n\t\t\tu_int16_t qthreshold;\n\t\t\tu_int16_t flags;\n\t\t} ulog;\n\t\tstruct {\n\t\t\tu_int8_t level;\n\t\t\tu_int8_t logflags;\n\t\t} log;\n\t} u;\n};\n\nstruct nf_nat_hook {\n\tint (*parse_nat_setup)(struct nf_conn *, enum nf_nat_manip_type, const struct nlattr *);\n\tvoid (*decode_session)(struct sk_buff *, struct flowi *);\n\tvoid (*remove_nat_bysrc)(struct nf_conn *);\n};\n\nstruct nf_queue_entry {\n\tstruct list_head list;\n\tstruct rhash_head hash_node;\n\tstruct sk_buff *skb;\n\tunsigned int id;\n\tunsigned int hook_index;\n\tstruct nf_hook_state state;\n\tbool nf_ct_is_unconfirmed;\n\tu16 size;\n\tu16 queue_num;\n};\n\nstruct nf_queue_handler {\n\tint (*outfn)(struct nf_queue_entry *, unsigned int);\n\tvoid (*nf_hook_drop)(struct net *);\n};\n\nstruct nf_sockopt_ops {\n\tstruct list_head list;\n\tu_int8_t pf;\n\tint set_optmin;\n\tint set_optmax;\n\tint (*set)(struct sock *, int, sockptr_t, unsigned int);\n\tint get_optmin;\n\tint get_optmax;\n\tint (*get)(struct sock *, int, void *, int *);\n\tstruct module *owner;\n};\n\nstruct nfnl_ct_hook {\n\tsize_t (*build_size)(const struct nf_conn *);\n\tint (*build)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, u_int16_t, u_int16_t);\n\tint (*parse)(const struct nlattr *, struct nf_conn *);\n\tint (*attach_expect)(const struct nlattr *, struct nf_conn *, u32, u32);\n\tvoid (*seq_adjust)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, s32);\n};\n\nstruct nfs2_fh {\n\tchar data[32];\n};\n\nstruct nfs3_accessargs {\n\tstruct nfs_fh *fh;\n\t__u32 access;\n};\n\nstruct nfs_fattr;\n\nstruct nfs3_accessres {\n\tstruct nfs_fattr *fattr;\n\t__u32 access;\n};\n\nstruct nfs3_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n\tenum nfs3_createmode createmode;\n\t__be32 verifier[2];\n};\n\nstruct rpc_procinfo;\n\nstruct rpc_message {\n\tconst struct rpc_procinfo *rpc_proc;\n\tvoid *rpc_argp;\n\tvoid *rpc_resp;\n\tconst struct cred *rpc_cred;\n};\n\nstruct nfs3_mkdirargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_mknodargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tenum nfs3_ftype type;\n\tstruct iattr *sattr;\n\tdev_t rdev;\n};\n\nstruct nfs3_diropres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs4_string;\n\nstruct nfs4_threshold;\n\nstruct nfs4_label;\n\nstruct nfs_fattr {\n\t__u64 valid;\n\tumode_t mode;\n\t__u32 nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\t__u64 size;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 blocksize;\n\t\t\t__u32 blocks;\n\t\t} nfs2;\n\t\tstruct {\n\t\t\t__u64 used;\n\t\t} nfs3;\n\t} du;\n\tstruct nfs_fsid fsid;\n\t__u64 fileid;\n\t__u64 mounted_on_fileid;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\t__u64 change_attr;\n\t__u64 pre_change_attr;\n\t__u64 pre_size;\n\tstruct timespec64 pre_mtime;\n\tstruct timespec64 pre_ctime;\n\tlong unsigned int time_start;\n\tlong unsigned int gencount;\n\tstruct nfs4_string *owner_name;\n\tstruct nfs4_string *group_name;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs3_createdata {\n\tstruct rpc_message msg;\n\tunion {\n\t\tstruct nfs3_createargs create;\n\t\tstruct nfs3_mkdirargs mkdir;\n\t\tstruct nfs3_symlinkargs symlink;\n\t\tstruct nfs3_mknodargs mknod;\n\t} arg;\n\tstruct nfs3_diropres res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_fattr dir_attr;\n};\n\nstruct nfs3_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs3_fh {\n\tshort unsigned int size;\n\tunsigned char data[64];\n};\n\nstruct nfs3_getaclargs {\n\tstruct nfs_fh *fh;\n\tint mask;\n\tstruct page **pages;\n};\n\nstruct nfs3_getaclres {\n\tstruct nfs_fattr *fattr;\n\tint mask;\n\tunsigned int acl_access_count;\n\tunsigned int acl_default_count;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n};\n\nstruct nfs3_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs3_linkres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_readdirargs {\n\tstruct nfs_fh *fh;\n\t__u64 cookie;\n\t__be32 verf[2];\n\tbool plus;\n\tunsigned int count;\n\tstruct page **pages;\n};\n\nstruct nfs3_readdirres {\n\tstruct nfs_fattr *dir_attr;\n\t__be32 *verf;\n\tbool plus;\n};\n\nstruct nfs3_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs3_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n\tunsigned int guard;\n\tstruct timespec64 guardtime;\n};\n\nstruct nfs3_setaclargs {\n\tstruct inode *inode;\n\tint mask;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n\tsize_t len;\n\tunsigned int npages;\n\tstruct page **pages;\n};\n\nstruct nfs41_bind_conn_to_session_args {\n\tstruct nfs_client *client;\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n\tint retries;\n};\n\nstruct nfs41_bind_conn_to_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tu32 dir;\n\tbool use_conn_in_rdma_mode;\n};\n\nstruct nfs4_channel_attrs {\n\tu32 max_rqst_sz;\n\tu32 max_resp_sz;\n\tu32 max_resp_sz_cached;\n\tu32 max_ops;\n\tu32 max_reqs;\n};\n\nstruct nfs41_create_session_args {\n\tstruct nfs_client *client;\n\tu64 clientid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tuint32_t cb_program;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs41_create_session_res {\n\tstruct nfs4_sessionid sessionid;\n\tuint32_t seqid;\n\tuint32_t flags;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_channel_attrs bc_attrs;\n};\n\nstruct nfs4_op_map {\n\tunion {\n\t\tlong unsigned int longs[2];\n\t\tu32 words[4];\n\t} u;\n};\n\nstruct nfs41_state_protection {\n\tu32 how;\n\tstruct nfs4_op_map enforce;\n\tstruct nfs4_op_map allow;\n};\n\nstruct nfs41_exchange_id_args {\n\tstruct nfs_client *client;\n\tnfs4_verifier verifier;\n\tu32 flags;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_server_owner;\n\nstruct nfs41_server_scope;\n\nstruct nfs41_impl_id;\n\nstruct nfs41_exchange_id_res {\n\tu64 clientid;\n\tu32 seqid;\n\tu32 flags;\n\tstruct nfs41_server_owner *server_owner;\n\tstruct nfs41_server_scope *server_scope;\n\tstruct nfs41_impl_id *impl_id;\n\tstruct nfs41_state_protection state_protect;\n};\n\nstruct nfs41_exchange_id_data {\n\tstruct nfs41_exchange_id_res res;\n\tstruct nfs41_exchange_id_args args;\n};\n\nstruct nfs4_sequence_args {\n\tstruct nfs4_slot *sa_slot;\n\tu8 sa_cache_this: 1;\n\tu8 sa_privileged: 1;\n};\n\nstruct nfs41_free_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_sequence_slot_ops;\n\nstruct nfs4_sequence_res {\n\tconst struct nfs4_sequence_slot_ops *sr_slot_ops;\n\tstruct nfs4_slot *sr_slot;\n\tlong unsigned int sr_timestamp;\n\tint sr_status;\n\tu32 sr_status_flags;\n\tu32 sr_highest_slotid;\n\tu32 sr_target_highest_slotid;\n};\n\nstruct nfs41_free_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfstime4 {\n\tint64_t seconds;\n\tuint32_t nseconds;\n};\n\nstruct nfs41_impl_id {\n\tchar domain[1025];\n\tchar name[1025];\n\tstruct nfstime4 date;\n};\n\nstruct nfs41_reclaim_complete_args {\n\tstruct nfs4_sequence_args seq_args;\n\tunsigned char one_fs: 1;\n};\n\nstruct nfs41_reclaim_complete_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs41_secinfo_no_name_args {\n\tstruct nfs4_sequence_args seq_args;\n\tint style;\n};\n\nstruct nfs41_server_owner {\n\tuint64_t minor_id;\n\tuint32_t major_id_sz;\n\tchar major_id[1024];\n};\n\nstruct nfs41_server_scope {\n\tuint32_t server_scope_sz;\n\tchar server_scope[1024];\n};\n\nstruct nfs41_test_stateid_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs41_test_stateid_res {\n\tstruct nfs4_sequence_res seq_res;\n\tunsigned int status;\n};\n\nstruct nfs42_layoutstat_devinfo;\n\nstruct nfs42_layoutstat_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tint num_dev;\n\tstruct nfs42_layoutstat_devinfo *devinfo;\n};\n\nstruct nfs4_xdr_opaque_ops;\n\nstruct nfs4_xdr_opaque_data {\n\tconst struct nfs4_xdr_opaque_ops *ops;\n\tvoid *data;\n};\n\nstruct nfs42_layoutstat_devinfo {\n\tstruct nfs4_deviceid dev_id;\n\t__u64 offset;\n\t__u64 length;\n\t__u64 read_count;\n\t__u64 read_bytes;\n\t__u64 write_count;\n\t__u64 write_bytes;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs4_accessargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tu32 access;\n};\n\nstruct nfs_server;\n\nstruct nfs4_accessres {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tu32 supported;\n\tu32 access;\n};\n\nstruct nfs4_add_xprt_data {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct nfs4_cached_acl {\n\tenum nfs4_acl_type type;\n\tint cached;\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct nfs4_call_sync_data {\n\tconst struct nfs_server *seq_server;\n\tstruct nfs4_sequence_args *seq_args;\n\tstruct nfs4_sequence_res *seq_res;\n};\n\nstruct nfs4_change_info {\n\tu32 atomic;\n\tu64 before;\n\tu64 after;\n};\n\nstruct nfs_seqid;\n\nstruct nfs4_layoutreturn_args;\n\nstruct nfs_closeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n\tfmode_t fmode;\n\tu32 share_access;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs4_layoutreturn_res;\n\nstruct nfs_closeres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct pnfs_layout_hdr;\n\nstruct nfs4_layoutreturn_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_layout_hdr *layout;\n\tstruct inode *inode;\n\tstruct pnfs_layout_range range;\n\tnfs4_stateid stateid;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data *ld_private;\n};\n\nstruct nfs4_layoutreturn_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 lrs_present;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs4_state;\n\nstruct nfs4_closedata {\n\tstruct inode *inode;\n\tstruct nfs4_state *state;\n\tstruct nfs_closeargs arg;\n\tstruct nfs_closeres res;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs_write_verifier {\n\tchar data[8];\n};\n\nstruct nfs_writeverf {\n\tstruct nfs_write_verifier verifier;\n\tenum nfs3_stable_how committed;\n};\n\nstruct nfs4_copy_state {\n\tstruct list_head copies;\n\tstruct list_head src_copies;\n\tnfs4_stateid stateid;\n\tstruct completion completion;\n\tuint64_t count;\n\tstruct nfs_writeverf verf;\n\tint error;\n\tint flags;\n\tstruct nfs4_state *parent_src_state;\n\tstruct nfs4_state *parent_dst_state;\n};\n\nstruct nfs4_create_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tu32 ftype;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page **pages;\n\t\t\tunsigned int len;\n\t\t} symlink;\n\t\tstruct {\n\t\t\tu32 specdata1;\n\t\t\tu32 specdata2;\n\t\t} device;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst struct iattr *attrs;\n\tconst struct nfs_fh *dir_fh;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n};\n\nstruct nfs4_create_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info dir_cinfo;\n};\n\nstruct nfs4_createdata {\n\tstruct rpc_message msg;\n\tstruct nfs4_create_arg arg;\n\tstruct nfs4_create_res res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n};\n\nstruct nfs4_delegattr {\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tbool atime_set;\n\tbool mtime_set;\n};\n\nstruct nfs4_delegreturnargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fhandle;\n\tconst nfs4_stateid *stateid;\n\tconst u32 *bitmask;\n\tu32 bitmask_store[3];\n\tstruct nfs4_layoutreturn_args *lr_args;\n\tstruct nfs4_delegattr *sattr_args;\n};\n\nstruct nfs4_delegreturnres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n\tbool sattr_res;\n\tint sattr_ret;\n};\n\nstruct nfs4_delegreturndata {\n\tstruct nfs4_delegreturnargs args;\n\tstruct nfs4_delegreturnres res;\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs4_delegattr sattr;\n\tstruct nfs_fattr fattr;\n\tint rpc_status;\n\tstruct inode *inode;\n};\n\nstruct pnfs_layoutdriver_type;\n\nstruct nfs4_deviceid_node {\n\tstruct hlist_node node;\n\tstruct hlist_node tmpnode;\n\tconst struct pnfs_layoutdriver_type *ld;\n\tconst struct nfs_client *nfs_client;\n\tlong unsigned int flags;\n\tlong unsigned int timestamp_unavailable;\n\tstruct nfs4_deviceid deviceid;\n\tstruct callback_head rcu;\n\tatomic_t ref;\n};\n\nstruct nfs4_ds_server {\n\tstruct list_head list;\n\tstruct rpc_clnt *rpc_clnt;\n};\n\nstruct nfs4_exception {\n\tstruct nfs4_state *state;\n\tstruct inode *inode;\n\tnfs4_stateid *stateid;\n\tlong int timeout;\n\tshort unsigned int retrans;\n\tunsigned char task_is_privileged: 1;\n\tunsigned char delay: 1;\n\tunsigned char recovering: 1;\n\tunsigned char retry: 1;\n\tbool interruptible;\n};\n\nstruct nfs4_ff_busy_timer {\n\tktime_t start_time;\n\tatomic_t n_ops;\n};\n\nstruct nfs4_ff_ds_version {\n\tu32 version;\n\tu32 minor_version;\n\tu32 rsize;\n\tu32 wsize;\n\tbool tightly_coupled;\n};\n\nstruct nfs4_ff_io_stat {\n\t__u64 ops_requested;\n\t__u64 bytes_requested;\n\t__u64 ops_completed;\n\t__u64 bytes_completed;\n\t__u64 bytes_not_delivered;\n\tktime_t total_busy_time;\n\tktime_t aggregate_completion_time;\n};\n\nstruct nfs4_pnfs_ds;\n\nstruct nfs4_ff_layout_ds {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 ds_versions_cnt;\n\tstruct nfs4_ff_ds_version *ds_versions;\n\tstruct nfs4_pnfs_ds *ds;\n};\n\nstruct nfs4_ff_layout_ds_err {\n\tstruct list_head list;\n\tu64 offset;\n\tu64 length;\n\tint status;\n\tenum nfs_opnum4 opnum;\n\tnfs4_stateid stateid;\n\tstruct nfs4_deviceid deviceid;\n};\n\nstruct nfsd_file;\n\nstruct nfs_file_localio {\n\tstruct nfsd_file *ro_file;\n\tstruct nfsd_file *rw_file;\n\tstruct list_head list;\n\tvoid *nfs_uuid;\n};\n\nstruct nfs4_ff_layoutstat {\n\tstruct nfs4_ff_io_stat io_stat;\n\tstruct nfs4_ff_busy_timer busy_timer;\n};\n\nstruct nfs4_ff_layout_mirror;\n\nstruct nfs4_ff_layout_ds_stripe {\n\tstruct nfs4_ff_layout_mirror *mirror;\n\tstruct nfs4_deviceid devid;\n\tu32 efficiency;\n\tstruct nfs4_ff_layout_ds *mirror_ds;\n\tu32 fh_versions_cnt;\n\tstruct nfs_fh *fh_versions;\n\tnfs4_stateid stateid;\n\tconst struct cred *ro_cred;\n\tconst struct cred *rw_cred;\n\tstruct nfs_file_localio nfl;\n\tstruct nfs4_ff_layoutstat read_stat;\n\tstruct nfs4_ff_layoutstat write_stat;\n\tktime_t start_time;\n};\n\nstruct nfs4_ff_layout_mirror {\n\tstruct pnfs_layout_hdr *layout;\n\tstruct list_head mirrors;\n\tu32 dss_count;\n\tstruct nfs4_ff_layout_ds_stripe *dss;\n\trefcount_t ref;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tu32 report_interval;\n};\n\nstruct pnfs_layout_segment {\n\tstruct list_head pls_list;\n\tstruct list_head pls_lc_list;\n\tstruct list_head pls_commits;\n\tstruct pnfs_layout_range pls_range;\n\trefcount_t pls_refcount;\n\tu32 pls_seq;\n\tlong unsigned int pls_flags;\n\tstruct pnfs_layout_hdr *pls_layout;\n};\n\nstruct nfs4_ff_layout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu64 stripe_unit;\n\tu32 flags;\n\tu32 mirror_array_cnt;\n\tstruct nfs4_ff_layout_mirror *mirror_array[0];\n};\n\nstruct nfs4_file_layout_dsaddr {\n\tstruct nfs4_deviceid_node id_node;\n\tu32 stripe_count;\n\tu8 *stripe_indices;\n\tu32 ds_num;\n\tstruct nfs4_pnfs_ds *ds_list[0];\n};\n\nstruct pnfs_layout_hdr {\n\trefcount_t plh_refcount;\n\tatomic_t plh_outstanding;\n\tstruct list_head plh_layouts;\n\tstruct list_head plh_bulk_destroy;\n\tstruct list_head plh_segs;\n\tstruct list_head plh_return_segs;\n\tlong unsigned int plh_block_lgets;\n\tlong unsigned int plh_retry_timestamp;\n\tlong unsigned int plh_flags;\n\tnfs4_stateid plh_stateid;\n\tu32 plh_barrier;\n\tu32 plh_return_seq;\n\tenum pnfs_iomode plh_return_iomode;\n\tloff_t plh_lwb;\n\tconst struct cred *plh_lc_cred;\n\tstruct inode *plh_inode;\n\tstruct callback_head plh_rcu;\n};\n\nstruct pnfs_commit_ops;\n\nstruct pnfs_ds_commit_info {\n\tstruct list_head commits;\n\tunsigned int nwritten;\n\tunsigned int ncommitting;\n\tconst struct pnfs_commit_ops *ops;\n};\n\nstruct nfs4_filelayout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n};\n\nstruct nfs4_filelayout_segment {\n\tstruct pnfs_layout_segment generic_hdr;\n\tu32 stripe_type;\n\tu32 commit_through_mds;\n\tu32 stripe_unit;\n\tu32 first_stripe_index;\n\tu64 pattern_offset;\n\tstruct nfs4_deviceid deviceid;\n\tstruct nfs4_file_layout_dsaddr *dsaddr;\n\tunsigned int num_fh;\n\tstruct nfs_fh **fh_array;\n};\n\nstruct nfs4_flexfile_layout {\n\tstruct pnfs_layout_hdr generic_hdr;\n\tstruct pnfs_ds_commit_info commit_info;\n\tstruct list_head mirrors;\n\tstruct list_head error_list;\n\tktime_t last_report_time;\n};\n\nstruct nfs4_flexfile_layoutreturn_args {\n\tstruct list_head errors;\n\tstruct nfs42_layoutstat_devinfo devinfo[4];\n\tunsigned int num_errors;\n\tunsigned int num_dev;\n\tstruct page *pages[1];\n};\n\nstruct nfs4_string {\n\tunsigned int len;\n\tchar *data;\n};\n\nstruct nfs4_pathname {\n\tunsigned int ncomponents;\n\tstruct nfs4_string components[512];\n};\n\nstruct nfs4_fs_location {\n\tunsigned int nservers;\n\tstruct nfs4_string servers[10];\n\tstruct nfs4_pathname rootpath;\n};\n\nstruct nfs4_fs_locations {\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tstruct nfs4_pathname fs_path;\n\tint nlocations;\n\tstruct nfs4_fs_location locations[10];\n};\n\nstruct nfs4_fs_locations_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct nfs_fh *fh;\n\tconst struct qstr *name;\n\tstruct page *page;\n\tconst u32 *bitmask;\n\tclientid4 clientid;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fs_locations_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_fs_locations *fs_locations;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tclientid4 clientid;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fh *fh;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsinfo;\n\nstruct nfs4_fsinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsinfo *fsinfo;\n};\n\nstruct nfs4_gdd_res {\n\tu32 status;\n\tnfs4_stateid deleg;\n};\n\nstruct nfs4_get_lease_time_args {\n\tstruct nfs4_sequence_args la_seq_args;\n};\n\nstruct nfs4_get_lease_time_res;\n\nstruct nfs4_get_lease_time_data {\n\tstruct nfs4_get_lease_time_args *args;\n\tstruct nfs4_get_lease_time_res *res;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_get_lease_time_res {\n\tstruct nfs4_sequence_res lr_seq_res;\n\tstruct nfs_fsinfo *lr_fsinfo;\n};\n\nstruct nfs4_getattr_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tbool get_dir_deleg;\n};\n\nstruct nfs4_getattr_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_gdd_res *gdd_res;\n};\n\nstruct pnfs_device;\n\nstruct nfs4_getdeviceinfo_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_device *pdev;\n\t__u32 notify_types;\n};\n\nstruct nfs4_getdeviceinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct pnfs_device *pdev;\n\t__u32 notification;\n};\n\nstruct nfs4_label {\n\tuint32_t lfs;\n\tuint32_t pi;\n\tu32 lsmid;\n\tu32 len;\n\tchar *label;\n};\n\nstruct nfs4_layoutcommit_args {\n\tstruct nfs4_sequence_args seq_args;\n\tnfs4_stateid stateid;\n\t__u64 lastbytewritten;\n\tstruct inode *inode;\n\tconst u32 *bitmask;\n\tsize_t layoutupdate_len;\n\tstruct page *layoutupdate_page;\n\tstruct page **layoutupdate_pages;\n\t__be32 *start_p;\n};\n\nstruct rpc_wait {\n\tstruct list_head list;\n\tstruct list_head links;\n\tstruct list_head timer_list;\n};\n\nstruct rpc_call_ops;\n\nstruct rpc_xprt;\n\nstruct rpc_rqst;\n\nstruct rpc_task {\n\tatomic_t tk_count;\n\tint tk_status;\n\tstruct list_head tk_task;\n\tvoid (*tk_callback)(struct rpc_task *);\n\tvoid (*tk_action)(struct rpc_task *);\n\tlong unsigned int tk_timeout;\n\tlong unsigned int tk_runstate;\n\tstruct rpc_wait_queue *tk_waitqueue;\n\tunion {\n\t\tstruct work_struct tk_work;\n\t\tstruct rpc_wait tk_wait;\n\t} u;\n\tstruct rpc_message tk_msg;\n\tvoid *tk_calldata;\n\tconst struct rpc_call_ops *tk_ops;\n\tstruct rpc_clnt *tk_client;\n\tstruct rpc_xprt *tk_xprt;\n\tstruct rpc_cred *tk_op_cred;\n\tstruct rpc_rqst *tk_rqstp;\n\tstruct workqueue_struct *tk_workqueue;\n\tktime_t tk_start;\n\tpid_t tk_owner;\n\tint tk_rpc_status;\n\tshort unsigned int tk_flags;\n\tshort unsigned int tk_timeouts;\n\tshort unsigned int tk_pid;\n\tunsigned char tk_priority: 2;\n\tunsigned char tk_garb_retry: 2;\n\tunsigned char tk_cred_retry: 2;\n};\n\nstruct nfs4_layoutcommit_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n\tint status;\n};\n\nstruct nfs4_layoutcommit_data {\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct list_head lseg_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tstruct nfs4_layoutcommit_args args;\n\tstruct nfs4_layoutcommit_res res;\n};\n\nstruct nfs4_layoutdriver_data {\n\tstruct page **pages;\n\t__u32 pglen;\n\t__u32 len;\n};\n\nstruct nfs_open_context;\n\nstruct nfs4_layoutget_args {\n\tstruct nfs4_sequence_args seq_args;\n\t__u32 type;\n\tstruct pnfs_layout_range range;\n\t__u64 minlength;\n\t__u32 maxcount;\n\tstruct inode *inode;\n\tstruct nfs_open_context *ctx;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data layout;\n};\n\nstruct nfs4_layoutget_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint status;\n\t__u32 return_on_close;\n\tstruct pnfs_layout_range range;\n\t__u32 type;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data *layoutp;\n};\n\nstruct nfs4_layoutget {\n\tstruct nfs4_layoutget_args args;\n\tstruct nfs4_layoutget_res res;\n\tconst struct cred *cred;\n\tstruct pnfs_layout_hdr *lo;\n\tgfp_t gfp_flags;\n};\n\nstruct nfs4_layoutreturn {\n\tstruct nfs4_layoutreturn_args args;\n\tstruct nfs4_layoutreturn_res res;\n\tconst struct cred *cred;\n\tstruct nfs_client *clp;\n\tstruct inode *inode;\n\tint rpc_status;\n\tstruct nfs4_xdr_opaque_data ld_private;\n};\n\nstruct nfs4_link_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_link_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *dir_attr;\n};\n\nstruct nfs_seqid_counter {\n\tktime_t create_time;\n\tu64 owner_id;\n\tint flags;\n\tu32 counter;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct rpc_wait_queue wait;\n};\n\nstruct nfs4_lock_state {\n\tstruct list_head ls_locks;\n\tstruct nfs4_state *ls_state;\n\tlong unsigned int ls_flags;\n\tstruct nfs_seqid_counter ls_seqid;\n\tnfs4_stateid ls_stateid;\n\trefcount_t ls_count;\n\tfl_owner_t ls_owner;\n};\n\nstruct nfs4_lock_waiter {\n\tstruct inode *inode;\n\tstruct nfs_lowner owner;\n\twait_queue_entry_t wait;\n};\n\nstruct nfs_lock_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *lock_seqid;\n\tnfs4_stateid lock_stateid;\n\tstruct nfs_seqid *open_seqid;\n\tnfs4_stateid open_stateid;\n\tstruct nfs_lowner lock_owner;\n\tunsigned char block: 1;\n\tunsigned char reclaim: 1;\n\tunsigned char new_lock: 1;\n\tunsigned char new_lock_owner: 1;\n};\n\nstruct nfs_lock_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *lock_seqid;\n\tstruct nfs_seqid *open_seqid;\n};\n\nstruct nfs4_lockdata {\n\tstruct nfs_lock_args arg;\n\tstruct nfs_lock_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct file_lock fl;\n\tlong unsigned int timestamp;\n\tint rpc_status;\n\tint cancelled;\n\tstruct nfs_server *server;\n};\n\nstruct nfs4_lookup_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookup_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_lookup_root_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n};\n\nstruct nfs4_mig_recovery_ops {\n\tint (*get_locations)(struct nfs_server *, struct nfs_fh *, struct nfs4_fs_locations *, struct page *, const struct cred *);\n\tint (*fsid_present)(struct inode *, const struct cred *);\n};\n\nstruct nfs4_state_recovery_ops;\n\nstruct nfs4_state_maintenance_ops;\n\nstruct nfs4_minor_version_ops {\n\tu32 minor_version;\n\tunsigned int init_caps;\n\tint (*init_client)(struct nfs_client *);\n\tvoid (*shutdown_client)(struct nfs_client *);\n\tbool (*match_stateid)(const nfs4_stateid *, const nfs4_stateid *);\n\tint (*find_root_sec)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *);\n\tvoid (*free_lock_state)(struct nfs_server *, struct nfs4_lock_state *);\n\tint (*test_and_free_expired)(struct nfs_server *, nfs4_stateid *, const struct cred *);\n\tstruct nfs_seqid * (*alloc_seqid)(struct nfs_seqid_counter *, gfp_t);\n\tvoid (*session_trunk)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tconst struct rpc_call_ops *call_sync_ops;\n\tconst struct nfs4_sequence_slot_ops *sequence_slot_ops;\n\tconst struct nfs4_state_recovery_ops *reboot_recovery_ops;\n\tconst struct nfs4_state_recovery_ops *nograce_recovery_ops;\n\tconst struct nfs4_state_maintenance_ops *state_renewal_ops;\n\tconst struct nfs4_mig_recovery_ops *mig_recovery_ops;\n};\n\nstruct nfs_string {\n\tunsigned int len;\n\tconst char *data;\n};\n\nstruct nfs4_mount_data {\n\tint version;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct nfs_string client_addr;\n\tstruct nfs_string mnt_path;\n\tstruct nfs_string hostname;\n\tunsigned int host_addrlen;\n\tstruct sockaddr *host_addr;\n\tint proto;\n\tint auth_flavourlen;\n\tint *auth_flavours;\n};\n\nstruct nfs4_open_caps {\n\tu32 oa_share_access[1];\n\tu32 oa_share_deny[1];\n\tu32 oa_share_access_want[1];\n\tu32 oa_open_claim[1];\n\tu32 oa_createmode[1];\n};\n\nstruct nfs4_open_createattrs {\n\tstruct nfs4_label *label;\n\tstruct iattr *sattr;\n\tconst __u32 verf[2];\n};\n\nstruct nfs4_open_delegation {\n\t__u32 open_delegation_type;\n\tunion {\n\t\tstruct {\n\t\t\tfmode_t type;\n\t\t\t__u32 do_recall;\n\t\t\tnfs4_stateid stateid;\n\t\t\tlong unsigned int pagemod_limit;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 why_no_delegation;\n\t\t\t__u32 will_notify;\n\t\t};\n\t};\n};\n\nstruct stateowner_id {\n\t__u64 create_time;\n\t__u64 uniquifier;\n};\n\nstruct nfs_openargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct nfs_seqid *seqid;\n\tint open_flags;\n\tfmode_t fmode;\n\tu32 share_access;\n\tu32 access;\n\t__u64 clientid;\n\tstruct stateowner_id id;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iattr *attrs;\n\t\t\tnfs4_verifier verifier;\n\t\t};\n\t\tnfs4_stateid delegation;\n\t\t__u32 delegation_type;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst u32 *open_bitmap;\n\tenum open_claim_type4 claim;\n\tenum createmode4 createmode;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n\tstruct nfs4_layoutget_args *lg_args;\n};\n\nstruct nfs_openres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fh fh;\n\tstruct nfs4_change_info cinfo;\n\t__u32 rflags;\n\tstruct nfs_fattr *f_attr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\t__u32 attrset[3];\n\tstruct nfs4_string *owner;\n\tstruct nfs4_string *group_owner;\n\tstruct nfs4_open_delegation delegation;\n\t__u32 access_request;\n\t__u32 access_supported;\n\t__u32 access_result;\n\tstruct nfs4_layoutget_res *lg_res;\n};\n\nstruct nfs_open_confirmargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tnfs4_stateid *stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_open_confirmres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs4_state_owner;\n\nstruct nfs4_opendata {\n\tstruct kref kref;\n\tstruct nfs_openargs o_arg;\n\tstruct nfs_openres o_res;\n\tstruct nfs_open_confirmargs c_arg;\n\tstruct nfs_open_confirmres c_res;\n\tstruct nfs4_string owner_name;\n\tstruct nfs4_string group_name;\n\tstruct nfs4_label *a_label;\n\tstruct nfs_fattr f_attr;\n\tstruct dentry *dir;\n\tstruct dentry *dentry;\n\tstruct nfs4_state_owner *owner;\n\tstruct nfs4_state *state;\n\tstruct iattr attrs;\n\tstruct nfs4_layoutget *lgp;\n\tlong unsigned int timestamp;\n\tbool rpc_done;\n\tbool file_created;\n\tbool is_recover;\n\tbool cancelled;\n\tint rpc_status;\n};\n\nstruct nfs4_pathconf_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_pathconf;\n\nstruct nfs4_pathconf_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_pathconf *pathconf;\n};\n\nstruct nfs4_pnfs_ds {\n\tstruct list_head ds_node;\n\tchar *ds_remotestr;\n\tstruct list_head ds_addrs;\n\tconst struct net *ds_net;\n\tstruct nfs_client *ds_clp;\n\trefcount_t ds_count;\n\tlong unsigned int ds_state;\n};\n\nstruct nfs4_pnfs_ds_addr {\n\tstruct __kernel_sockaddr_storage da_addr;\n\tsize_t da_addrlen;\n\tstruct list_head da_node;\n\tchar *da_remotestr;\n\tconst char *da_netid;\n\tint da_transport;\n};\n\nstruct nfs4_readdir_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tu64 cookie;\n\tnfs4_verifier verifier;\n\tu32 count;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tconst u32 *bitmask;\n\tbool plus;\n};\n\nstruct nfs4_readdir_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_verifier verifier;\n\tunsigned int pgbase;\n};\n\nstruct nfs4_readlink {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs4_readlink_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_reclaim_complete_data {\n\tstruct nfs_client *clp;\n\tstruct nfs41_reclaim_complete_args arg;\n\tstruct nfs41_reclaim_complete_res res;\n};\n\nstruct rpcsec_gss_info {\n\tstruct rpcsec_gss_oid oid;\n\tu32 qop;\n\tu32 service;\n};\n\nstruct nfs4_secinfo4 {\n\tu32 flavor;\n\tstruct rpcsec_gss_info flavor_info;\n};\n\nstruct nfs4_secinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n};\n\nstruct nfs4_secinfo_flavors {\n\tunsigned int num_flavors;\n\tstruct nfs4_secinfo4 flavors[0];\n};\n\nstruct nfs4_secinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_secinfo_flavors *flavors;\n};\n\nstruct nfs4_sequence_data {\n\tstruct nfs_client *clp;\n\tstruct nfs4_sequence_args args;\n\tstruct nfs4_sequence_res res;\n};\n\nstruct nfs4_sequence_slot_ops {\n\tint (*process)(struct rpc_task *, struct nfs4_sequence_res *);\n\tint (*done)(struct rpc_task *, struct nfs4_sequence_res *);\n\tvoid (*free_slot)(struct nfs4_sequence_res *);\n};\n\nstruct nfs4_server_caps_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fhandle;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_server_caps_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 attr_bitmask[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 has_links;\n\tu32 has_symlinks;\n\tu32 fh_expire_type;\n\tu32 case_insensitive;\n\tu32 case_preserving;\n\tstruct nfs4_open_caps open_caps;\n};\n\nstruct nfs4_session;\n\nstruct nfs4_slot_table {\n\tstruct nfs4_session *session;\n\tstruct nfs4_slot *slots;\n\tlong unsigned int used_slots[16];\n\tspinlock_t slot_tbl_lock;\n\tstruct rpc_wait_queue slot_tbl_waitq;\n\twait_queue_head_t slot_waitq;\n\tu32 max_slots;\n\tu32 max_slotid;\n\tu32 highest_used_slotid;\n\tu32 target_highest_slotid;\n\tu32 server_highest_slotid;\n\ts32 d_target_highest_slotid;\n\ts32 d2_target_highest_slotid;\n\tlong unsigned int generation;\n\tstruct completion complete;\n\tlong unsigned int slot_tbl_state;\n};\n\nstruct nfs4_session {\n\tstruct nfs4_sessionid sess_id;\n\tu32 flags;\n\tlong unsigned int session_state;\n\tu32 hash_alg;\n\tu32 ssv_len;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_slot_table fc_slot_table;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tstruct nfs4_slot_table bc_slot_table;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs4_setclientid {\n\tconst nfs4_verifier *sc_verifier;\n\tu32 sc_prog;\n\tunsigned int sc_netid_len;\n\tchar sc_netid[6];\n\tunsigned int sc_uaddr_len;\n\tchar sc_uaddr[58];\n\tstruct nfs_client *sc_clnt;\n\tstruct rpc_cred *sc_cred;\n};\n\nstruct nfs4_setclientid_res {\n\tu64 clientid;\n\tnfs4_verifier confirm;\n};\n\nstruct nfs4_slot {\n\tstruct nfs4_slot_table *table;\n\tstruct nfs4_slot *next;\n\tlong unsigned int generation;\n\tu32 slot_nr;\n\tu32 seq_nr;\n\tu32 seq_nr_last_acked;\n\tu32 seq_nr_highest_sent;\n\tunsigned int privileged: 1;\n\tunsigned int seq_done: 1;\n};\n\nstruct nfs4_state {\n\tstruct list_head open_states;\n\tstruct list_head inode_states;\n\tstruct list_head lock_states;\n\tstruct nfs4_state_owner *owner;\n\tstruct inode *inode;\n\tlong unsigned int flags;\n\tspinlock_t state_lock;\n\tseqlock_t seqlock;\n\tnfs4_stateid stateid;\n\tnfs4_stateid open_stateid;\n\tunsigned int n_rdonly;\n\tunsigned int n_wronly;\n\tunsigned int n_rdwr;\n\tfmode_t state;\n\trefcount_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs4_state_maintenance_ops {\n\tint (*sched_state_renewal)(struct nfs_client *, const struct cred *, unsigned int);\n\tconst struct cred * (*get_state_renewal_cred)(struct nfs_client *);\n\tint (*renew_lease)(struct nfs_client *, const struct cred *);\n};\n\nstruct nfs4_state_owner {\n\tstruct nfs_server *so_server;\n\tstruct list_head so_lru;\n\tlong unsigned int so_expires;\n\tstruct rb_node so_server_node;\n\tconst struct cred *so_cred;\n\tspinlock_t so_lock;\n\tatomic_t so_count;\n\tlong unsigned int so_flags;\n\tstruct list_head so_states;\n\tstruct nfs_seqid_counter so_seqid;\n\tstruct mutex so_delegreturn_mutex;\n};\n\nstruct nfs4_state_recovery_ops {\n\tint owner_flag_bit;\n\tint state_flag_bit;\n\tint (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);\n\tint (*recover_lock)(struct nfs4_state *, struct file_lock *);\n\tint (*establish_clid)(struct nfs_client *, const struct cred *);\n\tint (*reclaim_complete)(struct nfs_client *, const struct cred *);\n\tint (*detect_trunking)(struct nfs_client *, struct nfs_client **, const struct cred *);\n};\n\nstruct nfs4_statfs_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_fsstat;\n\nstruct nfs4_statfs_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsstat *fsstat;\n};\n\nstruct nfs4_threshold {\n\t__u32 bm;\n\t__u32 l_type;\n\t__u64 rd_sz;\n\t__u64 wr_sz;\n\t__u64 rd_io_sz;\n\t__u64 wr_io_sz;\n};\n\nstruct nfs_locku_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *seqid;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs_locku_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_lock_context;\n\nstruct nfs4_unlockdata {\n\tstruct nfs_locku_args arg;\n\tstruct nfs_locku_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct file_lock fl;\n\tstruct nfs_server *server;\n\tlong unsigned int timestamp;\n\tshort unsigned int retrans;\n};\n\nstruct nfs4_xdr_opaque_ops {\n\tvoid (*encode)(struct xdr_stream *, const void *, const struct nfs4_xdr_opaque_data *);\n\tvoid (*free)(struct nfs4_xdr_opaque_data *);\n};\n\nstruct nfs_access_entry {\n\tstruct rb_node rb_node;\n\tstruct list_head lru;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tstruct group_info *group_info;\n\tu64 timestamp;\n\t__u32 mask;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_auth_info {\n\tunsigned int flavor_len;\n\trpc_authflavor_t flavors[12];\n};\n\nstruct nfs_cache_array_entry {\n\tu64 cookie;\n\tu64 ino;\n\tconst char *name;\n\tunsigned int name_len;\n\tunsigned char d_type;\n};\n\nstruct nfs_cache_array {\n\tu64 change_attr;\n\tu64 last_cookie;\n\tunsigned int size;\n\tunsigned char folio_full: 1;\n\tunsigned char folio_is_eof: 1;\n\tunsigned char cookies_are_ordered: 1;\n\tstruct nfs_cache_array_entry array[0];\n};\n\nstruct svc_serv;\n\nstruct nfs_callback_data {\n\tunsigned int users;\n\tstruct svc_serv *serv;\n};\n\nstruct xprtsec_parms {\n\tenum xprtsec_policies policy;\n\tkey_serial_t cert_serial;\n\tkey_serial_t privkey_serial;\n};\n\nstruct nfs_rpc_ops;\n\nstruct nfs_subversion;\n\nstruct nfs_client {\n\trefcount_t cl_count;\n\tatomic_t cl_mds_count;\n\tint cl_cons_state;\n\tlong unsigned int cl_res_state;\n\tlong unsigned int cl_flags;\n\tstruct __kernel_sockaddr_storage cl_addr;\n\tsize_t cl_addrlen;\n\tchar *cl_hostname;\n\tchar *cl_acceptor;\n\tstruct list_head cl_share_link;\n\tstruct list_head cl_superblocks;\n\tstruct rpc_clnt *cl_rpcclient;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tint cl_proto;\n\tstruct nfs_subversion *cl_nfs_mod;\n\tu32 cl_minorversion;\n\tunsigned int cl_nconnect;\n\tunsigned int cl_max_connect;\n\tconst char *cl_principal;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct list_head cl_ds_clients;\n\tu64 cl_clientid;\n\tnfs4_verifier cl_confirm;\n\tlong unsigned int cl_state;\n\tspinlock_t cl_lock;\n\tlong unsigned int cl_lease_time;\n\tlong unsigned int cl_last_renewal;\n\tstruct delayed_work cl_renewd;\n\tstruct rpc_wait_queue cl_rpcwaitq;\n\tstruct idmap *cl_idmap;\n\tconst char *cl_owner_id;\n\tu32 cl_cb_ident;\n\tconst struct nfs4_minor_version_ops *cl_mvops;\n\tlong unsigned int cl_mig_gen;\n\tstruct nfs4_slot_table *cl_slot_tbl;\n\tu32 cl_seqid;\n\tu32 cl_exchange_flags;\n\tstruct nfs4_session *cl_session;\n\tbool cl_preserve_clid;\n\tstruct nfs41_server_owner *cl_serverowner;\n\tstruct nfs41_server_scope *cl_serverscope;\n\tstruct nfs41_impl_id *cl_implid;\n\tlong unsigned int cl_sp4_flags;\n\twait_queue_head_t cl_lock_waitq;\n\tchar cl_ipaddr[48];\n\tstruct net *cl_net;\n\tnetns_tracker cl_ns_tracker;\n\tstruct list_head pending_cb_stateids;\n\tstruct callback_head rcu;\n};\n\nstruct rpc_timeout;\n\nstruct nfs_client_initdata {\n\tlong unsigned int init_flags;\n\tconst char *hostname;\n\tconst struct __kernel_sockaddr_storage *addr;\n\tconst char *nodename;\n\tconst char *ip_addr;\n\tsize_t addrlen;\n\tstruct nfs_subversion *nfs_mod;\n\tint proto;\n\tu32 minorversion;\n\tunsigned int nconnect;\n\tunsigned int max_connect;\n\tstruct net *net;\n\tconst struct rpc_timeout *timeparms;\n\tconst struct cred *cred;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct nfs_clone_mount {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_commit_data;\n\nstruct nfs_commit_info;\n\nstruct nfs_page;\n\nstruct nfs_commit_completion_ops {\n\tvoid (*completion)(struct nfs_commit_data *);\n\tvoid (*resched_write)(struct nfs_commit_info *, struct nfs_page *);\n};\n\nstruct nfs_commitargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\t__u64 offset;\n\t__u32 count;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_commitres {\n\tstruct nfs4_sequence_res seq_res;\n\t__u32 op_status;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_writeverf *verf;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs_direct_req;\n\nstruct nfs_commit_data {\n\tstruct rpc_task task;\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_writeverf verf;\n\tstruct list_head pages;\n\tstruct list_head list;\n\tstruct nfs_direct_req *dreq;\n\tstruct nfs_commitargs args;\n\tstruct nfs_commitres res;\n\tstruct nfs_open_context *context;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_index;\n\tloff_t lwb;\n\tconst struct rpc_call_ops *mds_ops;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n\tint (*commit_done_cb)(struct rpc_task *, struct nfs_commit_data *);\n\tlong unsigned int flags;\n};\n\nstruct nfs_mds_commit_info;\n\nstruct nfs_commit_info {\n\tstruct inode *inode;\n\tstruct nfs_mds_commit_info *mds;\n\tstruct pnfs_ds_commit_info *ds;\n\tstruct nfs_direct_req *dreq;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n};\n\nstruct nfs_delegation {\n\tstruct hlist_node hash;\n\tstruct list_head super_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tfmode_t type;\n\tlong unsigned int pagemod_limit;\n\t__u64 change_attr;\n\tlong unsigned int test_gen;\n\tlong unsigned int flags;\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_mds_commit_info {\n\tatomic_t rpcs_out;\n\tatomic_long_t ncommit;\n\tstruct list_head list;\n};\n\nstruct nfs_direct_req {\n\tstruct kref kref;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct kiocb *iocb;\n\tstruct inode *inode;\n\tatomic_t io_count;\n\tspinlock_t lock;\n\tloff_t io_start;\n\tssize_t count;\n\tssize_t max_count;\n\tssize_t error;\n\tstruct completion completion;\n\tstruct nfs_mds_commit_info mds_cinfo;\n\tstruct pnfs_ds_commit_info ds_cinfo;\n\tstruct work_struct work;\n\tint flags;\n};\n\nstruct nfs_entry {\n\t__u64 ino;\n\t__u64 cookie;\n\tconst char *name;\n\tunsigned int len;\n\tint eof;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tunsigned char d_type;\n\tstruct nfs_server *server;\n};\n\nstruct nfs_find_desc {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_free_stateid_data {\n\tstruct nfs_server *server;\n\tstruct nfs41_free_stateid_args args;\n\tstruct nfs41_free_stateid_res res;\n};\n\nstruct nfs_fs_context {\n\tbool internal;\n\tbool skip_reconfig_option_check;\n\tbool need_mount;\n\tbool sloppy;\n\tunsigned int flags;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tunsigned int timeo;\n\tunsigned int retrans;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namlen;\n\tunsigned int options;\n\tunsigned int bsize;\n\tstruct nfs_auth_info auth_info;\n\trpc_authflavor_t selected_flavor;\n\tstruct xprtsec_parms xprtsec;\n\tchar *client_address;\n\tunsigned int version;\n\tunsigned int minorversion;\n\tchar *fscache_uniq;\n\tshort unsigned int protofamily;\n\tshort unsigned int mountfamily;\n\tbool has_sec_mnt_opts;\n\tint lock_status;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tu32 version;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t} mount_server;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tchar *export_path;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t\tshort unsigned int nconnect;\n\t\tshort unsigned int max_connect;\n\t\tshort unsigned int export_path_len;\n\t} nfs_server;\n\tstruct nfs_fh *mntfh;\n\tstruct nfs_server *server;\n\tstruct nfs_subversion *nfs_mod;\n\tstruct nfs_clone_mount clone_data;\n};\n\nstruct nfs_fsinfo {\n\tstruct nfs_fattr *fattr;\n\t__u32 rtmax;\n\t__u32 rtpref;\n\t__u32 rtmult;\n\t__u32 wtmax;\n\t__u32 wtpref;\n\t__u32 wtmult;\n\t__u32 dtpref;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\t__u32 lease_time;\n\t__u32 nlayouttypes;\n\t__u32 layouttype[8];\n\t__u32 blksize;\n\t__u32 clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\t__u32 xattr_support;\n};\n\nstruct nfs_fsstat {\n\tstruct nfs_fattr *fattr;\n\t__u64 tbytes;\n\t__u64 fbytes;\n\t__u64 abytes;\n\t__u64 tfiles;\n\t__u64 ffiles;\n\t__u64 afiles;\n};\n\nstruct nfs_getaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_getaclres {\n\tstruct nfs4_sequence_res seq_res;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tsize_t acl_data_offset;\n\tint acl_flags;\n\tstruct folio *acl_scratch;\n};\n\nstruct nfs_inode {\n\t__u64 fileid;\n\tstruct nfs_fh fh;\n\tlong unsigned int flags;\n\tlong unsigned int cache_validity;\n\tstruct timespec64 btime;\n\tlong unsigned int read_cache_jiffies;\n\tlong unsigned int attrtimeo;\n\tlong unsigned int attrtimeo_timestamp;\n\tlong unsigned int attr_gencount;\n\tstruct rb_root access_cache;\n\tstruct list_head access_cache_entry_lru;\n\tstruct list_head access_cache_inode_lru;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int cache_change_attribute;\n\t\t\t__be32 cookieverf[2];\n\t\t\tstruct rw_semaphore rmdir_sem;\n\t\t};\n\t\tstruct {\n\t\t\tatomic_long_t nrequests;\n\t\t\tatomic_long_t redirtied_pages;\n\t\t\tstruct nfs_mds_commit_info commit_info;\n\t\t\tstruct mutex commit_mutex;\n\t\t};\n\t};\n\tstruct list_head open_files;\n\tstruct {\n\t\tint cnt;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 end;\n\t\t} gap[16];\n\t} *ooo;\n\tstruct nfs4_cached_acl *nfs4_acl;\n\tstruct list_head open_states;\n\tstruct nfs_delegation *delegation;\n\tstruct rw_semaphore rwsem;\n\tstruct pnfs_layout_hdr *layout;\n\t__u64 write_io;\n\t__u64 read_io;\n\tunion {\n\t\tstruct inode vfs_inode;\n\t};\n};\n\nstruct nfs_io_completion {\n\tvoid (*complete)(void *);\n\tvoid *data;\n\tstruct kref refcount;\n};\n\nstruct nfs_iostats {\n\tlong long unsigned int bytes[8];\n\tlong unsigned int events[27];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nfs_lock_context {\n\trefcount_t count;\n\tstruct list_head list;\n\tstruct nfs_open_context *open_context;\n\tfl_owner_t lockowner;\n\tatomic_t io_count;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_lockt_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_lockt_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct file_lock *denied;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct nfs_mount_data {\n\tint version;\n\tint fd;\n\tstruct nfs2_fh old_root;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct sockaddr_in addr;\n\tchar hostname[256];\n\tint namlen;\n\tunsigned int bsize;\n\tstruct nfs3_fh root;\n\tint pseudoflavor;\n\tchar context[257];\n};\n\nstruct nfs_mount_request {\n\tstruct __kernel_sockaddr_storage *sap;\n\tsize_t salen;\n\tchar *hostname;\n\tchar *dirpath;\n\tu32 version;\n\tshort unsigned int protocol;\n\tstruct nfs_fh *fh;\n\tint noresvport;\n\tunsigned int *auth_flav_len;\n\trpc_authflavor_t *auth_flavs;\n\tstruct net *net;\n};\n\nstruct rpc_program;\n\nstruct rpc_stat {\n\tconst struct rpc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int netreconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcretrans;\n\tunsigned int rpcauthrefresh;\n\tunsigned int rpcgarbage;\n};\n\nstruct nfs_netns_client;\n\nstruct nfs_net {\n\tstruct cache_detail *nfs_dns_resolve;\n\tstruct rpc_pipe *bl_device_pipe;\n\tstruct bl_dev_msg bl_mount_reply;\n\twait_queue_head_t bl_wq;\n\tstruct mutex bl_mutex;\n\tstruct list_head nfs_client_list;\n\tstruct list_head nfs_volume_list;\n\tstruct idr cb_ident_idr;\n\tshort unsigned int nfs_callback_tcpport;\n\tshort unsigned int nfs_callback_tcpport6;\n\tint cb_users[2];\n\tstruct list_head nfs4_data_server_cache;\n\tspinlock_t nfs4_data_server_lock;\n\tstruct nfs_netns_client *nfs_client;\n\tspinlock_t nfs_client_lock;\n\tktime_t boot_time;\n\tstruct rpc_stat rpcstats;\n\tstruct proc_dir_entry *proc_nfsfs;\n};\n\nstruct nfs_netns_client {\n\tstruct kobject kobject;\n\tstruct kobject nfs_net_kobj;\n\tstruct net *net;\n\tconst char *identifier;\n};\n\nstruct nfs_open_context {\n\tstruct nfs_lock_context lock_context;\n\tfl_owner_t flock_owner;\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\tstruct rpc_cred *ll_cred;\n\tstruct nfs4_state *state;\n\tfmode_t mode;\n\tint error;\n\tlong unsigned int flags;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tstruct nfs_file_localio nfl;\n};\n\nstruct nfs_open_dir_context {\n\tstruct list_head list;\n\tatomic_t cache_hits;\n\tatomic_t cache_misses;\n\tlong unsigned int attr_gencount;\n\t__be32 verf[2];\n\t__u64 dir_cookie;\n\t__u64 last_cookie;\n\tlong unsigned int page_index;\n\tunsigned int dtsize;\n\tbool force_clear;\n\tbool eof;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_page {\n\tstruct list_head wb_list;\n\tunion {\n\t\tstruct page *wb_page;\n\t\tstruct folio *wb_folio;\n\t};\n\tstruct nfs_lock_context *wb_lock_context;\n\tlong unsigned int wb_index;\n\tunsigned int wb_offset;\n\tunsigned int wb_pgbase;\n\tunsigned int wb_bytes;\n\tstruct kref wb_kref;\n\tlong unsigned int wb_flags;\n\tstruct nfs_write_verifier wb_verf;\n\tstruct nfs_page *wb_this_page;\n\tstruct nfs_page *wb_head;\n\tshort unsigned int wb_nio;\n};\n\nstruct nfs_page_array {\n\tstruct page **pagevec;\n\tunsigned int npages;\n\tstruct page *page_array[8];\n};\n\nstruct nfs_page_iter_page {\n\tconst struct nfs_page *req;\n\tsize_t count;\n};\n\nstruct nfs_pgio_mirror {\n\tstruct list_head pg_list;\n\tlong unsigned int pg_bytes_written;\n\tsize_t pg_count;\n\tsize_t pg_bsize;\n\tunsigned int pg_base;\n\tunsigned char pg_recoalesce: 1;\n};\n\nstruct nfs_pageio_ops;\n\nstruct nfs_rw_ops;\n\nstruct nfs_pgio_completion_ops;\n\nstruct nfs_pageio_descriptor {\n\tstruct inode *pg_inode;\n\tconst struct nfs_pageio_ops *pg_ops;\n\tconst struct nfs_rw_ops *pg_rw_ops;\n\tint pg_ioflags;\n\tint pg_error;\n\tconst struct rpc_call_ops *pg_rpc_callops;\n\tconst struct nfs_pgio_completion_ops *pg_completion_ops;\n\tstruct pnfs_layout_segment *pg_lseg;\n\tstruct nfs_io_completion *pg_io_completion;\n\tstruct nfs_direct_req *pg_dreq;\n\tunsigned int pg_bsize;\n\tu32 pg_mirror_count;\n\tstruct nfs_pgio_mirror *pg_mirrors;\n\tstruct nfs_pgio_mirror pg_mirrors_static[1];\n\tstruct nfs_pgio_mirror *pg_mirrors_dynamic;\n\tu32 pg_mirror_idx;\n\tshort unsigned int pg_maxretrans;\n\tunsigned char pg_moreio: 1;\n};\n\nstruct nfs_pageio_ops {\n\tvoid (*pg_init)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tsize_t (*pg_test)(struct nfs_pageio_descriptor *, struct nfs_page *, struct nfs_page *);\n\tint (*pg_doio)(struct nfs_pageio_descriptor *);\n\tunsigned int (*pg_get_mirror_count)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tvoid (*pg_cleanup)(struct nfs_pageio_descriptor *);\n\tstruct nfs_pgio_mirror * (*pg_get_mirror)(struct nfs_pageio_descriptor *, u32);\n\tu32 (*pg_set_mirror)(struct nfs_pageio_descriptor *, u32);\n};\n\nstruct nfs_pathconf {\n\tstruct nfs_fattr *fattr;\n\t__u32 max_link;\n\t__u32 max_namelen;\n};\n\nstruct nfs_pgio_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct nfs_open_context *context;\n\tstruct nfs_lock_context *lock_context;\n\tnfs4_stateid stateid;\n\t__u64 offset;\n\t__u32 count;\n\tunsigned int pgbase;\n\tstruct page **pages;\n\tunion {\n\t\tunsigned int replen;\n\t\tstruct {\n\t\t\tconst u32 *bitmask;\n\t\t\tu32 bitmask_store[3];\n\t\t\tenum nfs3_stable_how stable;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header;\n\nstruct nfs_pgio_completion_ops {\n\tvoid (*error_cleanup)(struct list_head *, int);\n\tvoid (*init_hdr)(struct nfs_pgio_header *);\n\tvoid (*completion)(struct nfs_pgio_header *);\n\tvoid (*reschedule_io)(struct nfs_pgio_header *);\n};\n\nstruct nfs_pgio_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\t__u64 count;\n\t__u32 op_status;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int replen;\n\t\t\tint eof;\n\t\t\tvoid *scratch;\n\t\t};\n\t\tstruct {\n\t\t\tstruct nfs_writeverf *verf;\n\t\t\tconst struct nfs_server *server;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_header {\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct list_head pages;\n\tstruct nfs_page *req;\n\tstruct nfs_writeverf verf;\n\tfmode_t rw_mode;\n\tstruct pnfs_layout_segment *lseg;\n\tloff_t io_start;\n\tconst struct rpc_call_ops *mds_ops;\n\tvoid (*release)(struct nfs_pgio_header *);\n\tconst struct nfs_pgio_completion_ops *completion_ops;\n\tconst struct nfs_rw_ops *rw_ops;\n\tstruct nfs_io_completion *io_completion;\n\tstruct nfs_direct_req *dreq;\n\tshort unsigned int retrans;\n\tint pnfs_error;\n\tint error;\n\tunsigned int good_bytes;\n\tlong unsigned int flags;\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_pgio_args args;\n\tstruct nfs_pgio_res res;\n\tlong unsigned int timestamp;\n\tint (*pgio_done_cb)(struct rpc_task *, struct nfs_pgio_header *);\n\t__u64 mds_offset;\n\tstruct nfs_page_array page_array;\n\tstruct nfs_client *ds_clp;\n\tu32 ds_commit_idx;\n\tu32 pgio_mirror_idx;\n};\n\nstruct nfs_readdir_arg {\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\t__be32 *verf;\n\tu64 cookie;\n\tstruct page **pages;\n\tunsigned int page_len;\n\tbool plus;\n};\n\nstruct nfs_readdir_descriptor {\n\tstruct file *file;\n\tstruct folio *folio;\n\tstruct dir_context *ctx;\n\tlong unsigned int folio_index;\n\tlong unsigned int folio_index_max;\n\tu64 dir_cookie;\n\tu64 last_cookie;\n\tloff_t current_index;\n\t__be32 verf[2];\n\tlong unsigned int dir_verifier;\n\tlong unsigned int timestamp;\n\tlong unsigned int gencount;\n\tlong unsigned int attr_gencount;\n\tunsigned int cache_entry_index;\n\tunsigned int buffer_fills;\n\tunsigned int dtsize;\n\tbool clear_cache;\n\tbool plus;\n\tbool eob;\n\tbool eof;\n};\n\nstruct nfs_readdir_res {\n\t__be32 *verf;\n};\n\nstruct nfs_referral_count {\n\tstruct list_head list;\n\tconst struct task_struct *task;\n\tunsigned int referral_count;\n};\n\nstruct nfs_removeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct qstr name;\n};\n\nstruct nfs_removeres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs_renameargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *old_dir;\n\tconst struct nfs_fh *new_dir;\n\tconst struct qstr *old_name;\n\tconst struct qstr *new_name;\n};\n\nstruct nfs_renameres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs4_change_info old_cinfo;\n\tstruct nfs_fattr *old_fattr;\n\tstruct nfs4_change_info new_cinfo;\n\tstruct nfs_fattr *new_fattr;\n};\n\nstruct nfs_renamedata {\n\tstruct nfs_renameargs args;\n\tstruct nfs_renameres res;\n\tstruct rpc_task task;\n\tconst struct cred *cred;\n\tstruct inode *old_dir;\n\tstruct dentry *old_dentry;\n\tstruct nfs_fattr old_fattr;\n\tstruct inode *new_dir;\n\tstruct dentry *new_dentry;\n\tstruct nfs_fattr new_fattr;\n\tvoid (*complete)(struct rpc_task *, struct nfs_renamedata *);\n\tlong int timeout;\n\tbool cancelled;\n};\n\nstruct nlmclnt_operations;\n\nstruct nfs_unlinkdata;\n\nstruct nfs_rpc_ops {\n\tu32 version;\n\tconst struct dentry_operations *dentry_ops;\n\tconst struct inode_operations *dir_inode_ops;\n\tconst struct inode_operations *file_inode_ops;\n\tconst struct file_operations *file_ops;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tint (*getroot)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*submount)(struct fs_context *, struct nfs_server *);\n\tint (*try_get_tree)(struct fs_context *);\n\tint (*getattr)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, struct inode *);\n\tint (*setattr)(struct dentry *, struct nfs_fattr *, struct iattr *);\n\tint (*lookup)(struct inode *, struct dentry *, const struct qstr *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*lookupp)(struct inode *, struct nfs_fh *, struct nfs_fattr *);\n\tint (*access)(struct inode *, struct nfs_access_entry *, const struct cred *);\n\tint (*readlink)(struct inode *, struct page *, unsigned int, unsigned int);\n\tint (*create)(struct inode *, struct dentry *, struct iattr *, int);\n\tint (*remove)(struct inode *, struct dentry *);\n\tvoid (*unlink_setup)(struct rpc_message *, struct dentry *, struct inode *);\n\tvoid (*unlink_rpc_prepare)(struct rpc_task *, struct nfs_unlinkdata *);\n\tint (*unlink_done)(struct rpc_task *, struct inode *);\n\tvoid (*rename_setup)(struct rpc_message *, struct dentry *, struct dentry *, struct inode *);\n\tvoid (*rename_rpc_prepare)(struct rpc_task *, struct nfs_renamedata *);\n\tint (*rename_done)(struct rpc_task *, struct inode *, struct inode *);\n\tint (*link)(struct inode *, struct inode *, const struct qstr *);\n\tint (*symlink)(struct inode *, struct dentry *, struct folio *, unsigned int, struct iattr *);\n\tstruct dentry * (*mkdir)(struct inode *, struct dentry *, struct iattr *);\n\tint (*rmdir)(struct inode *, const struct qstr *);\n\tint (*readdir)(struct nfs_readdir_arg *, struct nfs_readdir_res *);\n\tint (*mknod)(struct inode *, struct dentry *, struct iattr *, dev_t);\n\tint (*statfs)(struct nfs_server *, struct nfs_fh *, struct nfs_fsstat *);\n\tint (*fsinfo)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*pathconf)(struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *);\n\tint (*set_capabilities)(struct nfs_server *, struct nfs_fh *);\n\tint (*decode_dirent)(struct xdr_stream *, struct nfs_entry *, bool);\n\tint (*pgio_rpc_prepare)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*read_setup)(struct nfs_pgio_header *, struct rpc_message *);\n\tint (*read_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*write_setup)(struct nfs_pgio_header *, struct rpc_message *, struct rpc_clnt **);\n\tint (*write_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*commit_setup)(struct nfs_commit_data *, struct rpc_message *, struct rpc_clnt **);\n\tvoid (*commit_rpc_prepare)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*commit_done)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tint (*lock_check_bounds)(const struct file_lock *);\n\tvoid (*clear_acl_cache)(struct inode *);\n\tvoid (*close_context)(struct nfs_open_context *, int);\n\tstruct inode * (*open_context)(struct inode *, struct nfs_open_context *, int, struct iattr *, int *);\n\tint (*have_delegation)(struct inode *, fmode_t, int);\n\tvoid (*return_delegation)(struct inode *);\n\tstruct nfs_client * (*alloc_client)(const struct nfs_client_initdata *);\n\tstruct nfs_client * (*init_client)(struct nfs_client *, const struct nfs_client_initdata *);\n\tvoid (*free_client)(struct nfs_client *);\n\tstruct nfs_server * (*create_server)(struct fs_context *);\n\tstruct nfs_server * (*clone_server)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, rpc_authflavor_t);\n\tint (*discover_trunking)(struct nfs_server *, struct nfs_fh *);\n\tvoid (*enable_swap)(struct inode *);\n\tvoid (*disable_swap)(struct inode *);\n};\n\nstruct rpc_task_setup;\n\nstruct nfs_rw_ops {\n\tstruct nfs_pgio_header * (*rw_alloc_header)(void);\n\tvoid (*rw_free_header)(struct nfs_pgio_header *);\n\tint (*rw_done)(struct rpc_task *, struct nfs_pgio_header *, struct inode *);\n\tvoid (*rw_result)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*rw_initiate)(struct nfs_pgio_header *, struct rpc_message *, const struct nfs_rpc_ops *, struct rpc_task_setup *, int);\n};\n\nstruct nfs_seqid {\n\tstruct nfs_seqid_counter *sequence;\n\tstruct list_head list;\n\tstruct rpc_task *task;\n};\n\nstruct nlm_host;\n\nstruct nfs_server {\n\tstruct nfs_client *nfs_client;\n\tstruct list_head client_link;\n\tstruct list_head master_link;\n\tstruct rpc_clnt *client;\n\tstruct rpc_clnt *client_acl;\n\tstruct nlm_host *nlm_host;\n\tstruct nfs_iostats *io_stats;\n\twait_queue_head_t write_congestion_wait;\n\tatomic_long_t writeback;\n\tunsigned int write_congested;\n\tunsigned int flags;\n\tunsigned int automount_inherit;\n\tunsigned int caps;\n\t__u64 fattr_valid;\n\tunsigned int rsize;\n\tunsigned int rpages;\n\tunsigned int wsize;\n\tunsigned int wtmult;\n\tunsigned int dtsize;\n\tshort unsigned int port;\n\tunsigned int bsize;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namelen;\n\tunsigned int options;\n\tunsigned int clone_blksize;\n\tenum nfs4_change_attr_type change_attr_type;\n\tstruct nfs_fsid fsid;\n\tint s_sysfs_id;\n\t__u64 maxfilesize;\n\tlong unsigned int mount_time;\n\tstruct super_block *super;\n\tdev_t s_dev;\n\tstruct nfs_auth_info auth_info;\n\tu32 fh_expire_type;\n\tu32 pnfs_blksize;\n\tu32 attr_bitmask[3];\n\tu32 attr_bitmask_nl[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 cache_consistency_bitmask[3];\n\tu32 acl_bitmask;\n\tstruct pnfs_layoutdriver_type *pnfs_curr_ld;\n\tstruct rpc_wait_queue roc_rpcwaitq;\n\tstruct rb_root state_owners;\n\tatomic64_t owner_ctr;\n\tstruct list_head state_owners_lru;\n\tstruct list_head layouts;\n\tstruct list_head delegations;\n\tspinlock_t delegations_lock;\n\tstruct list_head delegations_return;\n\tstruct list_head delegations_lru;\n\tstruct list_head delegations_delayed;\n\tatomic_long_t nr_active_delegations;\n\tunsigned int delegation_hash_mask;\n\tstruct hlist_head *delegation_hash_table;\n\tstruct list_head ss_copies;\n\tstruct list_head ss_src_copies;\n\tlong unsigned int delegation_flags;\n\tlong unsigned int delegation_gen;\n\tlong unsigned int mig_gen;\n\tlong unsigned int mig_status;\n\tvoid (*destroy)(struct nfs_server *);\n\tatomic_t active;\n\tstruct __kernel_sockaddr_storage mountd_address;\n\tsize_t mountd_addrlen;\n\tu32 mountd_version;\n\tshort unsigned int mountd_port;\n\tshort unsigned int mountd_protocol;\n\tstruct rpc_wait_queue uoc_rpcwaitq;\n\tunsigned int read_hdrsize;\n\tconst struct cred *cred;\n\tbool has_sec_mnt_opts;\n\tstruct kobject kobj;\n\tstruct callback_head rcu;\n};\n\nstruct nfs_setaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tenum nfs4_acl_type acl_type;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_setaclres {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs_setattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct iattr *iap;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n};\n\nstruct nfs_setattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tconst struct nfs_server *server;\n};\n\nstruct rpc_version;\n\nstruct super_operations;\n\nstruct xattr_handler;\n\nstruct nfs_subversion {\n\tstruct module *owner;\n\tstruct file_system_type *nfs_fs;\n\tconst struct rpc_version *rpc_vers;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tconst struct super_operations *sops;\n\tconst struct xattr_handler * const *xattr;\n};\n\nstruct nfs_unlinkdata {\n\tstruct nfs_removeargs args;\n\tstruct nfs_removeres res;\n\tstruct dentry *dentry;\n\twait_queue_head_t wq;\n\tconst struct cred *cred;\n\tstruct nfs_fattr dir_attr;\n\tlong int timeout;\n};\n\nstruct xdr_array2_desc;\n\ntypedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *, void *);\n\nstruct xdr_array2_desc {\n\tunsigned int elem_size;\n\tunsigned int array_len;\n\tunsigned int array_maxlen;\n\txdr_xcode_elem_t xcode;\n};\n\nstruct nfsacl_decode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n};\n\nstruct nfsacl_encode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n\tint typeflag;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct posix_acl_hdr {\n\trefcount_t a_refcount;\n\tunsigned int a_count;\n\tstruct callback_head a_rcu;\n};\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct nfsacl_simple_acl {\n\tstruct posix_acl_hdr acl;\n\tstruct posix_acl_entry ace[4];\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tu16 nh_grp_res_num_buckets;\n\tlong unsigned int nh_grp_res_idle_timer;\n\tlong unsigned int nh_grp_res_unbalanced_timer;\n\tbool nh_grp_res_has_num_buckets;\n\tbool nh_grp_res_has_idle_timer;\n\tbool nh_grp_res_has_unbalanced_timer;\n\tbool nh_hw_stats;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nstruct nh_dump_filter {\n\tu32 nh_id;\n\tint dev_idx;\n\tint master_idx;\n\tbool group_filter;\n\tbool fdb_filter;\n\tu32 res_bucket_nh_id;\n\tu32 op_flags;\n};\n\nstruct nh_grp_entry_stats;\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tstruct nh_grp_entry_stats *stats;\n\tu16 weight;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t upper_bound;\n\t\t} hthr;\n\t\tstruct {\n\t\t\tstruct list_head uw_nh_entry;\n\t\t\tu16 count_buckets;\n\t\t\tu16 wants_buckets;\n\t\t} res;\n\t};\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n\tu64 packets_hw;\n};\n\nstruct nh_res_table;\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool is_multipath;\n\tbool hash_threshold;\n\tbool resilient;\n\tbool fdb_nh;\n\tbool has_v4;\n\tbool hw_stats;\n\tstruct nh_res_table *res_table;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct nh_grp_entry_stats {\n\tu64_stats_t packets;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_notifier_single_info {\n\tstruct net_device *dev;\n\tu8 gw_family;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t};\n\tu32 id;\n\tu8 is_reject: 1;\n\tu8 is_fdb: 1;\n\tu8 has_encap: 1;\n};\n\nstruct nh_notifier_grp_entry_info {\n\tu16 weight;\n\tstruct nh_notifier_single_info nh;\n};\n\nstruct nh_notifier_grp_hw_stats_entry_info {\n\tu32 id;\n\tu64 packets;\n};\n\nstruct nh_notifier_grp_hw_stats_info {\n\tu16 num_nh;\n\tbool hw_stats_used;\n\tstruct nh_notifier_grp_hw_stats_entry_info stats[0];\n};\n\nstruct nh_notifier_grp_info {\n\tu16 num_nh;\n\tbool is_fdb;\n\tbool hw_stats;\n\tstruct nh_notifier_grp_entry_info nh_entries[0];\n};\n\nstruct nh_notifier_res_table_info;\n\nstruct nh_notifier_res_bucket_info;\n\nstruct nh_notifier_info {\n\tstruct net *net;\n\tstruct netlink_ext_ack *extack;\n\tu32 id;\n\tenum nh_notifier_info_type type;\n\tunion {\n\t\tstruct nh_notifier_single_info *nh;\n\t\tstruct nh_notifier_grp_info *nh_grp;\n\t\tstruct nh_notifier_res_table_info *nh_res_table;\n\t\tstruct nh_notifier_res_bucket_info *nh_res_bucket;\n\t\tstruct nh_notifier_grp_hw_stats_info *nh_grp_hw_stats;\n\t};\n};\n\nstruct nh_notifier_res_bucket_info {\n\tu16 bucket_index;\n\tunsigned int idle_timer_ms;\n\tbool force;\n\tstruct nh_notifier_single_info old_nh;\n\tstruct nh_notifier_single_info new_nh;\n};\n\nstruct nh_notifier_res_table_info {\n\tu16 num_nh_buckets;\n\tbool hw_stats;\n\tstruct nh_notifier_single_info nhs[0];\n};\n\nstruct nh_res_bucket {\n\tstruct nh_grp_entry *nh_entry;\n\tatomic_long_t used_time;\n\tlong unsigned int migrated_time;\n\tbool occupied;\n\tu8 nh_flags;\n};\n\nstruct nh_res_table {\n\tstruct net *net;\n\tu32 nhg_id;\n\tstruct delayed_work upkeep_dw;\n\tstruct list_head uw_nh_entries;\n\tlong unsigned int unbalanced_since;\n\tu32 idle_timer;\n\tu32 unbalanced_timer;\n\tu16 num_nh_buckets;\n\tstruct nh_res_bucket nh_buckets[0];\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct rfd {\n\t__le16 status;\n\t__le16 command;\n\t__le32 link;\n\t__le32 rbd;\n\t__le16 actual_size;\n\t__le16 size;\n};\n\nstruct param_range {\n\tu32 min;\n\tu32 max;\n\tu32 count;\n};\n\nstruct params {\n\tstruct param_range rfds;\n\tstruct param_range cbs;\n};\n\nstruct rx;\n\nstruct nic {\n\tu32 msg_enable;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tu16 (*mdio_ctrl)(struct nic *, u32, u32, u32, u16);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rx *rxs;\n\tstruct rx *rx_to_use;\n\tstruct rx *rx_to_clean;\n\tstruct rfd blank_rfd;\n\tenum ru_state ru_running;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t cb_lock;\n\tspinlock_t cmd_lock;\n\tstruct csr *csr;\n\tenum scb_cmd_lo cuc_cmd;\n\tunsigned int cbs_avail;\n\tstruct napi_struct napi;\n\tstruct cb *cbs;\n\tstruct cb *cb_to_use;\n\tstruct cb *cb_to_send;\n\tstruct cb *cb_to_clean;\n\t__le16 tx_command;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tenum {\n\t\tich = 1,\n\t\tpromiscuous = 2,\n\t\tmulticast_all = 4,\n\t\twol_magic = 8,\n\t\tich_10h_workaround = 16,\n\t} flags;\n\tenum mac mac;\n\tenum phy phy;\n\tstruct params params;\n\tstruct timer_list watchdog;\n\tstruct mii_if_info mii;\n\tstruct work_struct tx_timeout_task;\n\tenum loopback loopback;\n\tstruct mem *mem;\n\tdma_addr_t dma_addr;\n\tstruct dma_pool *cbs_pool;\n\tdma_addr_t cbs_dma_addr;\n\tu8 adaptive_ifs;\n\tu8 tx_threshold;\n\tu32 tx_frames;\n\tu32 tx_collisions;\n\tu32 tx_deferred;\n\tu32 tx_single_collisions;\n\tu32 tx_multiple_collisions;\n\tu32 tx_fc_pause;\n\tu32 tx_tco_frames;\n\tu32 rx_fc_pause;\n\tu32 rx_fc_unsupported;\n\tu32 rx_tco_frames;\n\tu32 rx_short_frame_errors;\n\tu32 rx_over_length_errors;\n\tu16 eeprom_wc;\n\t__le16 eeprom[256];\n\tspinlock_t mdio_lock;\n\tconst struct firmware *fw;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tu16 strict_start_type;\n\t\tconst u32 bitfield32_valid;\n\t\tconst u32 mask;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tconst struct netlink_range_validation *range;\n\t\tconst struct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t};\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct nlm_cookie {\n\tunsigned char data[32];\n\tunsigned int len;\n};\n\nstruct nlm_lock {\n\tchar *caller;\n\tunsigned int len;\n\tstruct nfs_fh fh;\n\tstruct xdr_netobj oh;\n\tu32 svid;\n\tu64 lock_start;\n\tu64 lock_len;\n\tstruct file_lock fl;\n};\n\nstruct nlm_args {\n\tstruct nlm_cookie cookie;\n\tstruct nlm_lock lock;\n\tu32 block;\n\tu32 reclaim;\n\tu32 state;\n\tu32 monitor;\n\tu32 fsm_access;\n\tu32 fsm_mode;\n};\n\nstruct nlm_rqst;\n\nstruct nlm_file;\n\nstruct nlm_block {\n\tstruct kref b_count;\n\tstruct list_head b_list;\n\tstruct list_head b_flist;\n\tstruct nlm_rqst *b_call;\n\tstruct svc_serv *b_daemon;\n\tstruct nlm_host *b_host;\n\tlong unsigned int b_when;\n\tunsigned int b_id;\n\tunsigned char b_granted;\n\tstruct nlm_file *b_file;\n\tstruct cache_req *b_cache_req;\n\tstruct cache_deferred_req *b_deferred_req;\n\tunsigned int b_flags;\n};\n\nstruct nlm_share;\n\nstruct nlm_file {\n\tstruct hlist_node f_list;\n\tstruct nfs_fh f_handle;\n\tstruct file *f_file[2];\n\tstruct nlm_share *f_shares;\n\tstruct list_head f_blocks;\n\tunsigned int f_locks;\n\tunsigned int f_count;\n\tstruct mutex f_mutex;\n};\n\nstruct nsm_handle;\n\nstruct nlm_host {\n\tstruct hlist_node h_hash;\n\tstruct __kernel_sockaddr_storage h_addr;\n\tsize_t h_addrlen;\n\tstruct __kernel_sockaddr_storage h_srcaddr;\n\tsize_t h_srcaddrlen;\n\tstruct rpc_clnt *h_rpcclnt;\n\tchar *h_name;\n\tu32 h_version;\n\tshort unsigned int h_proto;\n\tshort unsigned int h_reclaiming: 1;\n\tshort unsigned int h_server: 1;\n\tshort unsigned int h_noresvport: 1;\n\tshort unsigned int h_inuse: 1;\n\twait_queue_head_t h_gracewait;\n\tstruct rw_semaphore h_rwsem;\n\tu32 h_state;\n\tu32 h_nsmstate;\n\tu32 h_pidcount;\n\trefcount_t h_count;\n\tstruct mutex h_mutex;\n\tlong unsigned int h_nextrebind;\n\tlong unsigned int h_expires;\n\tstruct list_head h_lockowners;\n\tspinlock_t h_lock;\n\tstruct list_head h_granted;\n\tstruct list_head h_reclaim;\n\tstruct nsm_handle *h_nsmhandle;\n\tchar *h_addrbuf;\n\tstruct net *net;\n\tconst struct cred *h_cred;\n\tchar nodename[65];\n\tconst struct nlmclnt_operations *h_nlmclnt_ops;\n};\n\nstruct nlm_lockowner {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct nlm_host *host;\n\tfl_owner_t owner;\n\tuint32_t pid;\n};\n\nstruct nlm_lookup_host_info {\n\tconst int server;\n\tconst struct sockaddr *sap;\n\tconst size_t salen;\n\tconst short unsigned int protocol;\n\tconst u32 version;\n\tconst char *hostname;\n\tconst size_t hostname_len;\n\tconst int noresvport;\n\tstruct net *net;\n\tconst struct cred *cred;\n};\n\nstruct nsm_private {\n\tunsigned char data[16];\n};\n\nstruct nlm_reboot {\n\tchar *mon;\n\tunsigned int len;\n\tu32 state;\n\tstruct nsm_private priv;\n};\n\nstruct nlm_res {\n\tstruct nlm_cookie cookie;\n\t__be32 status;\n\tstruct nlm_lock lock;\n};\n\nstruct nlm_rqst {\n\trefcount_t a_count;\n\tunsigned int a_flags;\n\tstruct nlm_host *a_host;\n\tstruct nlm_args a_args;\n\tstruct nlm_res a_res;\n\tstruct nlm_block *a_block;\n\tunsigned int a_retries;\n\tu8 a_owner[74];\n\tvoid *a_callback_data;\n};\n\nstruct nlm_share {\n\tstruct nlm_share *s_next;\n\tstruct nlm_host *s_host;\n\tstruct nlm_file *s_file;\n\tstruct xdr_netobj s_owner;\n\tu32 s_access;\n\tu32 s_mode;\n};\n\nstruct nlm_wait {\n\tstruct list_head b_list;\n\twait_queue_head_t b_wait;\n\tstruct nlm_host *b_host;\n\tstruct file_lock *b_lock;\n\t__be32 b_status;\n};\n\nstruct nlmclnt_initdata {\n\tconst char *hostname;\n\tconst struct sockaddr *address;\n\tsize_t addrlen;\n\tshort unsigned int protocol;\n\tu32 nfs_version;\n\tint noresvport;\n\tstruct net *net;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tconst struct cred *cred;\n};\n\nstruct nlmclnt_operations {\n\tvoid (*nlmclnt_alloc_call)(void *);\n\tbool (*nlmclnt_unlock_prepare)(struct rpc_task *, void *);\n\tvoid (*nlmclnt_release_call)(void *);\n};\n\nstruct nlmsg_perm {\n\tu16 nlmsg_type;\n\tu32 perm;\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nstruct nlmsvc_binding {\n\t__be32 (*fopen)(struct svc_rqst *, struct nfs_fh *, struct file **, int);\n\tvoid (*fclose)(struct file *);\n};\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\nstruct node {\n\tstruct device dev;\n\tstruct list_head access_list;\n};\n\nstruct node_access_nodes {\n\tstruct device dev;\n\tstruct list_head list_node;\n\tunsigned int access;\n};\n\nstruct node_attr {\n\tstruct device_attribute attr;\n\tenum node_states state;\n};\n\nstruct node_barn {\n\tspinlock_t lock;\n\tstruct list_head sheaves_full;\n\tstruct list_head sheaves_empty;\n\tunsigned int nr_full;\n\tunsigned int nr_empty;\n};\n\nstruct node_groups {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int ngroups;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct node_hstate {\n\tstruct kobject *hugepages_kobj;\n\tstruct kobject *hstate_kobjs[15];\n};\n\nstruct node_memory_type_map {\n\tstruct memory_dev_type *memtype;\n\tint map_count;\n};\n\nstruct node_notify {\n\tint nid;\n};\n\nstruct nodemask_scratch {\n\tnodemask_t mask1;\n\tnodemask_t mask2;\n};\n\nstruct notification {\n\tatomic_t requests;\n\tu32 flags;\n\tu64 next_id;\n\tstruct list_head notifications;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nstruct ns_id_req {\n\t__u32 size;\n\t__u32 spare;\n\t__u64 ns_id;\n\tstruct {\n\t\t__u32 ns_type;\n\t\t__u32 spare2;\n\t\t__u64 user_ns_id;\n\t};\n};\n\nstruct nsfs_file_handle {\n\t__u64 ns_id;\n\t__u32 ns_type;\n\t__u32 ns_inum;\n};\n\nstruct nsm_args {\n\tstruct nsm_private *priv;\n\tu32 prog;\n\tu32 vers;\n\tu32 proc;\n\tchar *mon_name;\n\tconst char *nodename;\n};\n\nstruct nsm_handle {\n\tstruct list_head sm_link;\n\trefcount_t sm_count;\n\tchar *sm_mon_name;\n\tchar *sm_name;\n\tstruct __kernel_sockaddr_storage sm_addr;\n\tsize_t sm_addrlen;\n\tunsigned int sm_monitored: 1;\n\tunsigned int sm_sticky: 1;\n\tstruct nsm_private sm_priv;\n\tchar sm_addrbuf[51];\n};\n\nstruct nsm_res {\n\tu32 status;\n\tu32 state;\n};\n\nstruct uts_namespace;\n\nstruct time_namespace;\n\nstruct nsproxy {\n\trefcount_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n} __attribute__((packed));\n\nstruct ntp_data {\n\tlong unsigned int tick_usec;\n\tu64 tick_length;\n\tu64 tick_length_base;\n\tint time_state;\n\tint time_status;\n\ts64 time_offset;\n\tlong int time_constant;\n\tlong int time_maxerror;\n\tlong int time_esterror;\n\ts64 time_freq;\n\ttime64_t time_reftime;\n\tlong int time_adjust;\n\ts64 ntp_tick_adj;\n\ttime64_t ntp_next_leap_sec;\n};\n\nstruct numa_drop_counters {\n\tatomic_t drops0;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t drops1;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct numa_group {\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tint nr_tasks;\n\tpid_t gid;\n\tint active_nodes;\n\tstruct callback_head rcu;\n\tlong unsigned int total_faults;\n\tlong unsigned int max_faults_cpu;\n\tlong unsigned int faults[0];\n};\n\nstruct numa_maps {\n\tlong unsigned int pages;\n\tlong unsigned int anon;\n\tlong unsigned int active;\n\tlong unsigned int writeback;\n\tlong unsigned int mapcount_max;\n\tlong unsigned int dirty;\n\tlong unsigned int swapcache;\n\tlong unsigned int node[256];\n};\n\nstruct proc_maps_locking_ctx {\n\tstruct mm_struct *mm;\n\tbool mmap_locked;\n\tstruct vm_area_struct *locked_vma;\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct vma_iterator iter;\n\tloff_t last_pos;\n\tstruct proc_maps_locking_ctx lock_ctx;\n\tstruct mempolicy *task_mempolicy;\n};\n\nstruct numa_maps_private {\n\tstruct proc_maps_private proc_maps;\n\tstruct numa_maps md;\n};\n\nstruct numa_stats {\n\tlong unsigned int load;\n\tlong unsigned int runnable;\n\tlong unsigned int util;\n\tlong unsigned int compute_capacity;\n\tunsigned int nr_running;\n\tunsigned int weight;\n\tenum numa_type node_type;\n\tint idle_cpu;\n};\n\nstruct nvdimm_security_ops;\n\nstruct nvdimm_fw_ops;\n\nstruct nvdimm {\n\tlong unsigned int flags;\n\tvoid *provider_data;\n\tlong unsigned int cmd_mask;\n\tstruct device dev;\n\tatomic_t busy;\n\tint id;\n\tint num_flush;\n\tstruct resource *flush_wpq;\n\tconst char *dimm_id;\n\tstruct {\n\t\tconst struct nvdimm_security_ops *ops;\n\t\tlong unsigned int flags;\n\t\tlong unsigned int ext_flags;\n\t\tunsigned int overwrite_tmo;\n\t\tstruct kernfs_node *overwrite_state;\n\t} sec;\n\tstruct delayed_work dwork;\n\tconst struct nvdimm_fw_ops *fw_ops;\n};\n\nstruct nvdimm_bus_descriptor;\n\nstruct nvdimm_bus {\n\tstruct nvdimm_bus_descriptor *nd_desc;\n\twait_queue_head_t wait;\n\tstruct list_head list;\n\tstruct device dev;\n\tint id;\n\tint probe_active;\n\tatomic_t ioctl_active;\n\tstruct list_head mapping_list;\n\tstruct mutex reconfig_mutex;\n\tstruct badrange badrange;\n};\n\ntypedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *, struct nvdimm *, unsigned int, void *, unsigned int, int *);\n\nstruct nvdimm_bus_fw_ops;\n\nstruct nvdimm_bus_descriptor {\n\tconst struct attribute_group **attr_groups;\n\tlong unsigned int cmd_mask;\n\tlong unsigned int dimm_family_mask;\n\tlong unsigned int bus_family_mask;\n\tstruct module *module;\n\tchar *provider_name;\n\tstruct device_node *of_node;\n\tndctl_fn ndctl;\n\tint (*flush_probe)(struct nvdimm_bus_descriptor *);\n\tint (*clear_to_send)(struct nvdimm_bus_descriptor *, struct nvdimm *, unsigned int, void *);\n\tconst struct nvdimm_bus_fw_ops *fw_ops;\n};\n\nstruct nvdimm_bus_fw_ops {\n\tenum nvdimm_fwa_state (*activate_state)(struct nvdimm_bus_descriptor *);\n\tenum nvdimm_fwa_capability (*capability)(struct nvdimm_bus_descriptor *);\n\tint (*activate)(struct nvdimm_bus_descriptor *);\n};\n\nstruct nvdimm_drvdata {\n\tstruct device *dev;\n\tint nslabel_size;\n\tstruct nd_cmd_get_config_size nsarea;\n\tvoid *data;\n\tbool cxl;\n\tint ns_current;\n\tint ns_next;\n\tstruct resource dpa;\n\tstruct kref kref;\n};\n\nstruct nvdimm_fw_ops {\n\tenum nvdimm_fwa_state (*activate_state)(struct nvdimm *);\n\tenum nvdimm_fwa_result (*activate_result)(struct nvdimm *);\n\tint (*arm)(struct nvdimm *, enum nvdimm_fwa_trigger);\n};\n\nstruct nvdimm_key_data {\n\tu8 data[32];\n};\n\nstruct nvdimm_map {\n\tstruct nvdimm_bus *nvdimm_bus;\n\tstruct list_head list;\n\tresource_size_t offset;\n\tlong unsigned int flags;\n\tsize_t size;\n\tunion {\n\t\tvoid *mem;\n\t\tvoid *iomem;\n\t};\n\tstruct kref kref;\n};\n\nstruct nvdimm_pmu {\n\tstruct pmu pmu;\n\tstruct device *dev;\n\tint cpu;\n\tstruct hlist_node node;\n\tenum cpuhp_state cpuhp_state;\n\tstruct cpumask arch_cpumask;\n};\n\nstruct nvdimm_security_ops {\n\tlong unsigned int (*get_flags)(struct nvdimm *, enum nvdimm_passphrase_type);\n\tint (*freeze)(struct nvdimm *);\n\tint (*change_key)(struct nvdimm *, const struct nvdimm_key_data *, const struct nvdimm_key_data *, enum nvdimm_passphrase_type);\n\tint (*unlock)(struct nvdimm *, const struct nvdimm_key_data *);\n\tint (*disable)(struct nvdimm *, const struct nvdimm_key_data *);\n\tint (*erase)(struct nvdimm *, const struct nvdimm_key_data *, enum nvdimm_passphrase_type);\n\tint (*overwrite)(struct nvdimm *, const struct nvdimm_key_data *);\n\tint (*query_overwrite)(struct nvdimm *);\n\tint (*disable_master)(struct nvdimm *, const struct nvdimm_key_data *);\n};\n\nstruct nvmem_cell_entry;\n\nstruct nvmem_cell {\n\tstruct nvmem_cell_entry *entry;\n\tconst char *id;\n\tint index;\n};\n\ntypedef int (*nvmem_cell_post_process_t)(void *, const char *, int, unsigned int, void *, size_t);\n\nstruct nvmem_device;\n\nstruct nvmem_cell_entry {\n\tconst char *name;\n\tint offset;\n\tsize_t raw_len;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n\tstruct device_node *np;\n\tstruct nvmem_device *nvmem;\n\tstruct list_head node;\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tsize_t raw_len;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n\tstruct device_node *np;\n\tnvmem_cell_post_process_t read_post_process;\n\tvoid *priv;\n};\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nstruct nvmem_keepout;\n\nstruct nvmem_layout;\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tbool add_legacy_fixed_of_cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool ignore_wp;\n\tstruct nvmem_layout *layout;\n\tstruct device_node *of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device {\n\tstruct module *owner;\n\tstruct device dev;\n\tstruct list_head node;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tvoid (*fixup_dt_cell_info)(struct nvmem_device *, struct nvmem_cell_info *);\n\tconst struct nvmem_keepout *keepout;\n\tunsigned int nkeepout;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tstruct nvmem_layout *layout;\n\tvoid *priv;\n\tbool sysfs_cells_populated;\n};\n\nstruct nvmem_keepout {\n\tunsigned int start;\n\tunsigned int end;\n\tunsigned char value;\n};\n\nstruct nvmem_layout {\n\tstruct device dev;\n\tstruct nvmem_device *nvmem;\n\tint (*add_cells)(struct nvmem_layout *);\n};\n\nstruct nvmem_layout_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct nvmem_layout *);\n\tvoid (*remove)(struct nvmem_layout *);\n};\n\nstruct nvram_header {\n\tunsigned char signature;\n\tunsigned char checksum;\n\tshort unsigned int length;\n\tchar name[12];\n};\n\nstruct nvram_os_partition {\n\tconst char *name;\n\tint req_size;\n\tint min_size;\n\tlong int size;\n\tlong int index;\n\tbool os_partition;\n};\n\nstruct nvram_partition {\n\tstruct list_head partition;\n\tstruct nvram_header header;\n\tunsigned int index;\n};\n\nstruct nx842_constraints {\n\tint alignment;\n\tint multiple;\n\tint minimum;\n\tint maximum;\n};\n\nstruct nx842_crypto_header_hdr {\n\t__be16 magic;\n\t__be16 ignore;\n\tu8 groups;\n};\n\nstruct nx842_crypto_header_group {\n\t__be16 padding;\n\t__be32 compressed_length;\n\t__be32 uncompressed_length;\n} __attribute__((packed));\n\nstruct nx842_driver;\n\nstruct nx842_crypto_ctx {\n\tspinlock_t lock;\n\tu8 *wmem;\n\tu8 *sbounce;\n\tu8 *dbounce;\n\tstruct nx842_crypto_header_hdr header;\n\tstruct nx842_crypto_header_group group[32];\n\tstruct nx842_driver *driver;\n};\n\nstruct nx842_crypto_header {\n\tunion {\n\t\tstruct {\n\t\t\t__be16 magic;\n\t\t\t__be16 ignore;\n\t\t\tu8 groups;\n\t\t};\n\t\tstruct nx842_crypto_header_hdr hdr;\n\t};\n\tstruct nx842_crypto_header_group group[0];\n};\n\nstruct nx842_crypto_param {\n\tu8 *in;\n\tunsigned int iremain;\n\tu8 *out;\n\tunsigned int oremain;\n\tunsigned int ototal;\n};\n\nstruct nx842_devdata {\n\tstruct vio_dev *vdev;\n\tstruct device *dev;\n\tstruct ibm_nx842_counters *counters;\n\tunsigned int max_sg_len;\n\tunsigned int max_sync_size;\n\tunsigned int max_sync_sg;\n};\n\nstruct nx842_driver {\n\tchar *name;\n\tstruct module *owner;\n\tsize_t workmem_size;\n\tstruct nx842_constraints *constraints;\n\tint (*compress)(const unsigned char *, unsigned int, unsigned char *, unsigned int *, void *);\n\tint (*decompress)(const unsigned char *, unsigned int, unsigned char *, unsigned int *, void *);\n};\n\nstruct nx842_slentry;\n\nstruct nx842_scatterlist {\n\tint entry_nr;\n\tstruct nx842_slentry *entries;\n};\n\nstruct nx842_slentry {\n\t__be64 ptr;\n\t__be64 len;\n};\n\nstruct nx842_workmem {\n\tstruct coprocessor_request_block crb;\n\tstruct data_descriptor_entry ddl_in[17];\n\tstruct data_descriptor_entry ddl_out[17];\n\tktime_t start;\n\tchar padding[256];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nx_csbcpb {\n\tunsigned char __rsvd[112];\n\tstruct cop_status_block csb;\n\tstruct cop_parameter_block cpb;\n};\n\nstruct nx842_workmem___2 {\n\tchar slin[4096];\n\tchar slout[4096];\n\tstruct nx_csbcpb csbcpb;\n\tchar padding[256];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nx_cop_caps {\n\tu64 descriptor;\n\tu64 req_max_processed_len;\n\tu64 min_compress_len;\n\tu64 min_decompress_len;\n};\n\nstruct nx_coproc {\n\tunsigned int chip_id;\n\tunsigned int ct;\n\tunsigned int ci;\n\tstruct {\n\t\tstruct vas_window *rxwin;\n\t\tint id;\n\t} vas;\n\tstruct list_head list;\n};\n\nstruct obj_cgroup {\n\tstruct percpu_ref refcnt;\n\tstruct mem_cgroup *memcg;\n\tatomic_t nr_charged_bytes;\n\tunion {\n\t\tstruct list_head list;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nstruct obj_stock_pcp {\n\tlocal_trylock_t lock;\n\tunsigned int nr_bytes;\n\tstruct obj_cgroup *cached_objcg;\n\tstruct pglist_data *cached_pgdat;\n\tint nr_slab_reclaimable_b;\n\tint nr_slab_unreclaimable_b;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n};\n\nstruct objpool_head;\n\ntypedef int (*objpool_fini_cb)(struct objpool_head *, void *);\n\nstruct objpool_slot;\n\nstruct objpool_head {\n\tint obj_size;\n\tint nr_objs;\n\tint nr_possible_cpus;\n\tint capacity;\n\tgfp_t gfp;\n\trefcount_t ref;\n\tlong unsigned int flags;\n\tstruct objpool_slot **cpu_slots;\n\tobjpool_fini_cb release;\n\tvoid *context;\n};\n\nstruct objpool_slot {\n\tuint32_t head;\n\tuint32_t tail;\n\tuint32_t last;\n\tuint32_t mask;\n\tvoid *entries[0];\n};\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nstruct ocontext {\n\tunion {\n\t\tchar *name;\n\t\tstruct {\n\t\t\tu8 protocol;\n\t\t\tu16 low_port;\n\t\t\tu16 high_port;\n\t\t} port;\n\t\tstruct {\n\t\t\tu32 addr;\n\t\t\tu32 mask;\n\t\t} node;\n\t\tstruct {\n\t\t\tu32 addr[4];\n\t\t\tu32 mask[4];\n\t\t} node6;\n\t\tstruct {\n\t\t\tu64 subnet_prefix;\n\t\t\tu16 low_pkey;\n\t\t\tu16 high_pkey;\n\t\t} ibpkey;\n\t\tstruct {\n\t\t\tchar *dev_name;\n\t\t\tu8 port;\n\t\t} ibendport;\n\t} u;\n\tunion {\n\t\tu32 sclass;\n\t\tu32 behavior;\n\t} v;\n\tstruct context context[2];\n\tu32 sid[2];\n\tstruct ocontext *next;\n};\n\nstruct od_dbs_tuners {\n\tunsigned int powersave_bias;\n};\n\nstruct od_ops {\n\tunsigned int (*powersave_bias_target)(struct cpufreq_policy *, unsigned int, unsigned int);\n};\n\nstruct od_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int freq_lo;\n\tunsigned int freq_lo_delay_us;\n\tunsigned int freq_hi_delay_us;\n\tunsigned int sample_type: 1;\n};\n\nstruct of_bus {\n\tvoid (*count_cells)(const void *, int, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n};\n\nstruct of_bus___2 {\n\tconst char *name;\n\tconst char *addresses;\n\tint (*match)(struct device_node *);\n\tvoid (*count_cells)(struct device_node *, int *, int *);\n\tu64 (*map)(__be32 *, const __be32 *, int, int, int, int);\n\tint (*translate)(__be32 *, u64, int);\n\tint flag_cells;\n\tunsigned int (*get_flags)(const __be32 *);\n};\n\nstruct of_changeset {\n\tstruct list_head entries;\n};\n\nstruct of_changeset_entry {\n\tstruct list_head node;\n\tlong unsigned int action;\n\tstruct device_node *np;\n\tstruct property *prop;\n\tstruct property *old_prop;\n};\n\nstruct of_dev_auxdata {\n\tchar *compatible;\n\tresource_size_t phys_addr;\n\tchar *name;\n\tvoid *platform_data;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\nstruct of_drc_info {\n\tchar *drc_type;\n\tchar *drc_name_prefix;\n\tu32 drc_index_start;\n\tu32 drc_name_suffix_start;\n\tu32 num_sequential_elems;\n\tu32 sequential_inc;\n\tu32 drc_power_domain;\n\tu32 last_drc_index;\n};\n\nstruct of_drconf_cell_v1 {\n\t__be64 base_addr;\n\t__be32 drc_index;\n\t__be32 reserved;\n\t__be32 aa_index;\n\t__be32 flags;\n};\n\nstruct of_drconf_cell_v2 {\n\tu32 seq_lmbs;\n\tu64 base_addr;\n\tu32 drc_index;\n\tu32 aa_index;\n\tu32 flags;\n} __attribute__((packed));\n\nstruct of_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct device_node *local_node;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct of_imap_item {\n\tstruct of_phandle_args parent_args;\n\tu32 child_imap_count;\n\tu32 child_imap[16];\n};\n\nstruct of_imap_parser {\n\tstruct device_node *node;\n\tconst __be32 *imap;\n\tconst __be32 *imap_end;\n\tu32 parent_offset;\n};\n\ntypedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *);\n\nstruct of_intc_desc {\n\tstruct list_head list;\n\tof_irq_init_cb_t irq_init_cb;\n\tstruct device_node *dev;\n\tstruct device_node *interrupt_parent;\n};\n\nstruct of_pci_iommu_alias_info {\n\tstruct device *dev;\n\tstruct device_node *np;\n};\n\nstruct of_pci_range {\n\tunion {\n\t\tu64 pci_addr;\n\t\tu64 bus_addr;\n\t};\n\tu64 cpu_addr;\n\tu64 parent_bus_addr;\n\tu64 size;\n\tu32 flags;\n};\n\nstruct of_pci_range_parser {\n\tstruct device_node *node;\n\tconst struct of_bus___2 *bus;\n\tconst __be32 *range;\n\tconst __be32 *end;\n\tint na;\n\tint ns;\n\tint pna;\n\tbool dma;\n};\n\nstruct of_phandle_iterator {\n\tconst char *cells_name;\n\tint cell_count;\n\tconst struct device_node *parent;\n\tconst __be32 *list_end;\n\tconst __be32 *phandle_end;\n\tconst __be32 *cur;\n\tuint32_t cur_count;\n\tphandle phandle;\n\tstruct device_node *node;\n};\n\nstruct of_pmem_private {\n\tstruct nvdimm_bus_descriptor bus_desc;\n\tstruct nvdimm_bus *bus;\n};\n\nstruct of_reconfig_data {\n\tstruct device_node *dn;\n\tstruct property *prop;\n\tstruct property *old_prop;\n};\n\nstruct offb_par {\n\tvolatile void *cmap_adr;\n\tvolatile void *cmap_data;\n\tint cmap_type;\n\tint blanked;\n\tu32 pseudo_palette[16];\n\tresource_size_t base;\n\tresource_size_t size;\n};\n\nstruct offset_ctx {\n\tstruct maple_tree mt;\n\tlong unsigned int next_offset;\n};\n\nstruct ohci_driver_overrides {\n\tconst char *product_desc;\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n};\n\nstruct ohci_hcca {\n\t__hc32 int_table[32];\n\t__hc32 frame_no;\n\t__hc32 done_head;\n\tu8 reserved_for_hc[116];\n\tu8 what[4];\n};\n\nstruct ohci_regs;\n\nstruct ohci_hcd {\n\tspinlock_t lock;\n\tstruct ohci_regs *regs;\n\tstruct ohci_hcca *hcca;\n\tdma_addr_t hcca_dma;\n\tstruct ed *ed_rm_list;\n\tstruct ed *ed_bulktail;\n\tstruct ed *ed_controltail;\n\tstruct ed *periodic[32];\n\tvoid (*start_hnp)(struct ohci_hcd *);\n\tstruct dma_pool *td_cache;\n\tstruct dma_pool *ed_cache;\n\tstruct td *td_hash[64];\n\tstruct td *dl_start;\n\tstruct td *dl_end;\n\tstruct list_head pending;\n\tstruct list_head eds_in_use;\n\tenum ohci_rh_state rh_state;\n\tint num_ports;\n\tint load[32];\n\tu32 hc_control;\n\tlong unsigned int next_statechange;\n\tu32 fminterval;\n\tunsigned int autostop: 1;\n\tunsigned int working: 1;\n\tunsigned int restart_work: 1;\n\tlong unsigned int flags;\n\tunsigned int prev_frame_no;\n\tunsigned int wdh_cnt;\n\tunsigned int prev_wdh_cnt;\n\tu32 prev_donehead;\n\tstruct timer_list io_watchdog;\n\tstruct work_struct nec_work;\n\tstruct dentry *debug_dir;\n\tlong unsigned int priv[0];\n};\n\nstruct ohci_roothub_regs {\n\t__hc32 a;\n\t__hc32 b;\n\t__hc32 status;\n\t__hc32 portstatus[15];\n};\n\nstruct ohci_regs {\n\t__hc32 revision;\n\t__hc32 control;\n\t__hc32 cmdstatus;\n\t__hc32 intrstatus;\n\t__hc32 intrenable;\n\t__hc32 intrdisable;\n\t__hc32 hcca;\n\t__hc32 ed_periodcurrent;\n\t__hc32 ed_controlhead;\n\t__hc32 ed_controlcurrent;\n\t__hc32 ed_bulkhead;\n\t__hc32 ed_bulkcurrent;\n\t__hc32 donehead;\n\t__hc32 fminterval;\n\t__hc32 fmremaining;\n\t__hc32 fmnumber;\n\t__hc32 periodicstart;\n\t__hc32 lsthresh;\n\tstruct ohci_roothub_regs roothub;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[0];\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n};\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct old_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n};\n\nstruct oldold_utsname {\n\tchar sysname[9];\n\tchar nodename[9];\n\tchar release[9];\n\tchar version[9];\n\tchar machine[9];\n};\n\nstruct static_key_true;\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n\tstruct module *module;\n};\n\nstruct online_data {\n\tunsigned int cpu;\n\tbool online;\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nstruct oops_log_info {\n\t__be16 version;\n\t__be16 report_length;\n\t__be64 timestamp;\n} __attribute__((packed));\n\nstruct opal {\n\tu64 base;\n\tu64 entry;\n\tu64 size;\n};\n\nstruct opal_msg {\n\t__be32 msg_type;\n\t__be32 reserved;\n\t__be64 params[8];\n};\n\nstruct opal_async_token {\n\tenum opal_async_token_state state;\n\tstruct opal_msg response;\n};\n\nstruct opal_event_irqchip {\n\tstruct irq_chip irqchip;\n\tstruct irq_domain *domain;\n\tlong unsigned int mask;\n};\n\nstruct opal_mpipl_region {\n\t__be64 src;\n\t__be64 dest;\n\t__be64 size;\n};\n\nstruct opal_fadump_mem_struct {\n\tu8 version;\n\tu8 reserved[3];\n\t__be16 region_cnt;\n\t__be16 registered_regions;\n\t__be64 fadumphdr_addr;\n\tstruct opal_mpipl_region rgn[128];\n};\n\nstruct opal_i2c_request {\n\tuint8_t type;\n\tuint8_t flags;\n\tuint8_t subaddr_sz;\n\tuint8_t reserved;\n\t__be16 addr;\n\t__be16 reserved2;\n\t__be32 subaddr;\n\t__be32 size;\n\t__be64 buffer_ra;\n};\n\nstruct opal_ipmi_msg {\n\tuint8_t version;\n\tuint8_t netfn;\n\tuint8_t cmd;\n\tuint8_t data[0];\n};\n\nstruct opal_mpipl_fadump {\n\tu8 version;\n\tu8 reserved[7];\n\t__be32 crashing_pir;\n\t__be32 cpu_data_version;\n\t__be32 cpu_data_size;\n\t__be32 region_cnt;\n\tstruct opal_mpipl_region region[0];\n};\n\nstruct opal_msg_node {\n\tstruct list_head list;\n\tstruct opal_msg msg;\n};\n\nstruct opal_occ_msg {\n\t__be64 type;\n\t__be64 chip;\n\t__be64 throttle_status;\n};\n\nstruct opal_sg_entry {\n\t__be64 data;\n\t__be64 length;\n};\n\nstruct opal_sg_list {\n\t__be64 length;\n\t__be64 next;\n\tstruct opal_sg_entry entry[0];\n};\n\nstruct opcode_info {\n\tbool can_jump;\n\tbool can_fallthrough;\n};\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\nstruct oppanel_line {\n\t__be64 line;\n\t__be64 line_len;\n};\n\ntypedef struct oppanel_line oppanel_line_t;\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct optimized_kprobe {\n\tstruct kprobe kp;\n\tstruct list_head list;\n\tstruct arch_optimized_insn optinsn;\n};\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\nstruct osnoise_entry {\n\tstruct trace_entry ent;\n\tu64 noise;\n\tu64 runtime;\n\tu64 max_sample;\n\tunsigned int hw_count;\n\tunsigned int nmi_count;\n\tunsigned int irq_count;\n\tunsigned int softirq_count;\n\tunsigned int thread_count;\n};\n\nstruct ostream {\n\tvoid (*func)(struct ostream *, char *, ...);\n\tchar *prefix;\n\tchar *buf;\n\tstruct seq_file *seq;\n\tint size;\n\tint used;\n};\n\nstruct output_log {\n\tunsigned char data;\n\tunsigned char status;\n\tlong unsigned int jiffies;\n};\n\nstruct p {\n\tstruct hv_get_perf_counter_info_params params;\n\tstruct hv_gpci_system_performance_capabilities caps;\n};\n\nstruct p2pdma_provider {\n\tstruct device *owner;\n\tu64 bus_offset;\n};\n\nstruct p7_sprs {\n\tu64 tscr;\n\tu64 worc;\n\tu64 sdr1;\n\tu64 rpr;\n\tu64 lpcr;\n\tu64 hfscr;\n\tu64 fscr;\n\tu64 purr;\n\tu64 spurr;\n\tu64 dscr;\n\tu64 wort;\n\tu64 amr;\n\tu64 iamr;\n\tu64 uamor;\n};\n\nstruct p9_host_os_sprs {\n\tlong unsigned int iamr;\n\tlong unsigned int amr;\n\tunsigned int pmc1;\n\tunsigned int pmc2;\n\tunsigned int pmc3;\n\tunsigned int pmc4;\n\tunsigned int pmc5;\n\tunsigned int pmc6;\n\tlong unsigned int mmcr0;\n\tlong unsigned int mmcr1;\n\tlong unsigned int mmcr2;\n\tlong unsigned int mmcr3;\n\tlong unsigned int mmcra;\n\tlong unsigned int siar;\n\tlong unsigned int sier1;\n\tlong unsigned int sier2;\n\tlong unsigned int sier3;\n\tlong unsigned int sdar;\n};\n\nstruct p9_sprs {\n\tu64 ptcr;\n\tu64 rpr;\n\tu64 tscr;\n\tu64 ldbar;\n\tu64 lpcr;\n\tu64 hfscr;\n\tu64 fscr;\n\tu64 pid;\n\tu64 purr;\n\tu64 spurr;\n\tu64 dscr;\n\tu64 ciabr;\n\tu64 mmcra;\n\tu32 mmcr0;\n\tu32 mmcr1;\n\tu64 mmcr2;\n\tu64 amr;\n\tu64 iamr;\n\tu64 amor;\n\tu64 uamor;\n};\n\nstruct slb_shadow;\n\nstruct sibling_subcore_state;\n\nstruct slb_entry;\n\nstruct paca_struct {\n\tstruct lppaca *lppaca_ptr;\n\tu16 paca_index;\n\tu16 lock_token;\n\tu64 kernel_toc;\n\tu64 kernelbase;\n\tu64 kernel_msr;\n\tvoid *emergency_sp;\n\tu64 data_offset;\n\ts16 hw_cpu_id;\n\tu8 cpu_start;\n\tu8 kexec_state;\n\tstruct slb_shadow *slb_shadow_ptr;\n\tstruct dtl_entry *dispatch_log;\n\tstruct dtl_entry *dispatch_log_end;\n\tu64 dscr_default;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 exgen[10];\n\tu16 vmalloc_sllp;\n\tu8 slb_cache_ptr;\n\tu8 stab_rr;\n\tu8 in_kernel_slb_handler;\n\tu32 slb_used_bitmap;\n\tu32 slb_kern_bitmap;\n\tu32 slb_cache[8];\n\tunsigned char mm_ctx_low_slices_psize[8];\n\tunsigned char mm_ctx_high_slices_psize[2048];\n\tstruct task_struct *__current;\n\tu64 kstack;\n\tu64 saved_r1;\n\tu64 saved_msr;\n\tu64 exit_save_r1;\n\tu8 hsrr_valid;\n\tu8 srr_valid;\n\tu8 irq_soft_mask;\n\tu8 irq_happened;\n\tu8 irq_work_pending;\n\tu8 pmcregs_in_use;\n\tu64 sprg_vdso;\n\tu64 tm_scratch;\n\tlong unsigned int idle_lock;\n\tlong unsigned int idle_state;\n\tunion {\n\t\tstruct {\n\t\t\tu8 thread_idle_state;\n\t\t\tu8 subcore_sibling_mask;\n\t\t};\n\t\tstruct {\n\t\t\tu64 requested_psscr;\n\t\t\tatomic_t dont_stop;\n\t\t};\n\t};\n\tu64 exnmi[10];\n\tu64 exmc[10];\n\tvoid *nmi_emergency_sp;\n\tvoid *mc_emergency_sp;\n\tu16 in_nmi;\n\tu16 in_mce;\n\tu8 hmi_event_available;\n\tu8 hmi_p9_special_emu;\n\tu32 hmi_irqs;\n\tu8 ftrace_enabled;\n\tstruct cpu_accounting_data accounting;\n\tu64 dtl_ridx;\n\tstruct dtl_entry *dtl_curr;\n\tstruct kvmppc_host_state kvm_hstate;\n\tstruct sibling_subcore_state *sibling_subcore_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 exrfi[10];\n\tvoid *rfi_flush_fallback_area;\n\tu64 l1d_flush_size;\n\tu8 *mce_data_buf;\n\tstruct slb_entry *mce_faulty_slbs;\n\tu16 slb_save_cache_ptr;\n\tlong unsigned int canary;\n\tstruct mmiowb_state mmiowb_state;\n\tstruct mce_info *mce_info;\n\tu8 mce_pending_irq_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pacct_struct {\n\tint ac_flag;\n\tlong int ac_exitcode;\n\tlong unsigned int ac_mem;\n\tu64 ac_utime;\n\tu64 ac_stime;\n\tlong unsigned int ac_minflt;\n\tlong unsigned int ac_majflt;\n};\n\nstruct scsi_sense_hdr;\n\nstruct packet_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct scsi_sense_hdr *sshdr;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu32 max_num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tstruct sock *arr[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n\tstruct list_head remove_list;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int version;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\trwlock_t blk_fill_in_prog_lock;\n\tktime_t interval_ktime;\n\tstruct hrtimer retire_blk_timer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 history[32];\n};\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tlong unsigned int flags;\n\tint ifindex;\n\tu8 vnet_hdr_sz;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_long_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t tp_drops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct padata_cpumask {\n\tcpumask_var_t pcpu;\n\tcpumask_var_t cbcpu;\n};\n\nstruct padata_instance {\n\tstruct hlist_node cpu_online_node;\n\tstruct hlist_node cpu_dead_node;\n\tstruct workqueue_struct *parallel_wq;\n\tstruct workqueue_struct *serial_wq;\n\tstruct list_head pslist;\n\tstruct padata_cpumask cpumask;\n\tstruct kobject kobj;\n\tstruct mutex lock;\n\tu8 flags;\n};\n\nstruct padata_list {\n\tstruct list_head list;\n\tspinlock_t lock;\n};\n\nstruct padata_mt_job {\n\tvoid (*thread_fn)(long unsigned int, long unsigned int, void *);\n\tvoid *fn_arg;\n\tlong unsigned int start;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int min_chunk;\n\tint max_threads;\n\tbool numa_aware;\n};\n\nstruct padata_mt_job_state {\n\tspinlock_t lock;\n\tstruct completion completion;\n\tstruct padata_mt_job *job;\n\tint nworks;\n\tint nworks_fini;\n\tlong unsigned int chunk_size;\n};\n\nstruct parallel_data;\n\nstruct padata_priv {\n\tstruct list_head list;\n\tstruct parallel_data *pd;\n\tint cb_cpu;\n\tunsigned int seq_nr;\n\tint info;\n\tvoid (*parallel)(struct padata_priv *);\n\tvoid (*serial)(struct padata_priv *);\n};\n\nstruct padata_serial_queue {\n\tstruct padata_list serial;\n\tstruct work_struct work;\n\tstruct parallel_data *pd;\n};\n\nstruct padata_shell {\n\tstruct padata_instance *pinst;\n\tstruct parallel_data *pd;\n\tstruct parallel_data *opd;\n\tstruct list_head list;\n};\n\nstruct padata_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct padata_instance *, const struct attribute *, char *);\n\tssize_t (*store)(struct padata_instance *, const struct attribute *, const char *, size_t);\n};\n\nstruct padata_work {\n\tstruct work_struct pw_work;\n\tstruct list_head pw_list;\n\tvoid *pw_data;\n};\n\nstruct page_ext {\n\tlong unsigned int flags;\n};\n\nstruct page_ext_iter {\n\tlong unsigned int index;\n\tlong unsigned int start_pfn;\n\tstruct page_ext *page_ext;\n};\n\nstruct page_ext_operations {\n\tsize_t offset;\n\tsize_t size;\n\tbool (*need)(void);\n\tvoid (*init)(void);\n\tbool need_shared_flags;\n};\n\nstruct printf_spec;\n\nstruct page_flags_fields {\n\tint width;\n\tint shift;\n\tint mask;\n\tconst struct printf_spec *spec;\n\tconst char *name;\n};\n\nstruct page_list {\n\tstruct page_list *next;\n\tstruct page *page;\n};\n\nstruct page_owner {\n\tshort unsigned int order;\n\tshort int last_migrate_reason;\n\tgfp_t gfp_mask;\n\tdepot_stack_handle_t handle;\n\tdepot_stack_handle_t free_handle;\n\tu64 ts_nsec;\n\tu64 free_ts_nsec;\n\tchar comm[16];\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t free_pid;\n\tpid_t free_tgid;\n};\n\nstruct page_pool_params_fast {\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tstruct napi_struct *napi;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tnetmem_ref cache[128];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_params_slow {\n\tstruct net_device *netdev;\n\tunsigned int queue_idx;\n\tunsigned int flags;\n\tvoid (*init_callback)(netmem_ref, void *);\n\tvoid *init_arg;\n};\n\nstruct page_pool {\n\tstruct page_pool_params_fast p;\n\tint cpuid;\n\tu32 pages_state_hold_cnt;\n\tbool has_init_callback: 1;\n\tbool dma_map: 1;\n\tbool dma_sync: 1;\n\tbool dma_sync_for_cpu: 1;\n\tlong: 0;\n\t__u8 __cacheline_group_begin__frag[0];\n\tlong int frag_users;\n\tnetmem_ref frag_page;\n\tunsigned int frag_offset;\n\tlong: 0;\n\t__u8 __cacheline_group_end__frag[0];\n\tlong: 64;\n\tstruct {} __cacheline_group_pad__frag;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tu32 xdp_mem_id;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pp_alloc_cache alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring ring;\n\tvoid *mp_priv;\n\tconst struct memory_provider_ops *mp_ops;\n\tstruct xarray dma_mapped;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tstruct page_pool_params_slow slow;\n\tstruct {\n\t\tstruct hlist_node list;\n\t\tu64 detach_time;\n\t\tu32 id;\n\t} user;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct page_pool_bh {\n\tstruct page_pool *pool;\n\tlocal_lock_t bh_lock;\n};\n\nstruct page_pool_dump_cb {\n\tlong unsigned int ifindex;\n\tu32 pp_id;\n};\n\nstruct page_pool_params {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int order;\n\t\t\tunsigned int pool_size;\n\t\t\tint nid;\n\t\t\tstruct device *dev;\n\t\t\tstruct napi_struct *napi;\n\t\t\tenum dma_data_direction dma_dir;\n\t\t\tunsigned int max_len;\n\t\t\tunsigned int offset;\n\t\t};\n\t\tstruct page_pool_params_fast fast;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct net_device *netdev;\n\t\t\tunsigned int queue_idx;\n\t\t\tunsigned int flags;\n\t\t\tvoid (*init_callback)(netmem_ref, void *);\n\t\t\tvoid *init_arg;\n\t\t};\n\t\tstruct page_pool_params_slow slow;\n\t};\n};\n\nstruct page_region {\n\t__u64 start;\n\t__u64 end;\n\t__u64 categories;\n};\n\nstruct page_reporting_dev_info {\n\tint (*report)(struct page_reporting_dev_info *, struct scatterlist *, unsigned int);\n\tstruct delayed_work work;\n\tatomic_t state;\n\tunsigned int order;\n};\n\nstruct page_snapshot {\n\tstruct folio folio_snapshot;\n\tstruct page page_snapshot;\n\tlong unsigned int pfn;\n\tlong unsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct page_vma_mapped_walk {\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n\tlong unsigned int pgoff;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nstruct pm_scan_arg {\n\t__u64 size;\n\t__u64 flags;\n\t__u64 start;\n\t__u64 end;\n\t__u64 walk_end;\n\t__u64 vec;\n\t__u64 vec_len;\n\t__u64 max_pages;\n\t__u64 category_inverted;\n\t__u64 category_mask;\n\t__u64 category_anyof_mask;\n\t__u64 return_mask;\n};\n\nstruct pagemap_scan_private {\n\tstruct pm_scan_arg arg;\n\tlong unsigned int masks_of_interest;\n\tlong unsigned int cur_vma_category;\n\tstruct page_region *vec_buf;\n\tlong unsigned int vec_buf_len;\n\tlong unsigned int vec_buf_index;\n\tlong unsigned int found_pages;\n\tstruct page_region *vec_out;\n};\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct pages_or_folios {\n\tunion {\n\t\tstruct page **pages;\n\t\tstruct folio **folios;\n\t\tvoid **entries;\n\t};\n\tbool has_folios;\n\tlong int nr_entries;\n};\n\nstruct pagetable_move_control {\n\tstruct vm_area_struct *old;\n\tstruct vm_area_struct *new;\n\tlong unsigned int old_addr;\n\tlong unsigned int old_end;\n\tlong unsigned int new_addr;\n\tlong unsigned int len_in;\n\tbool need_rmap_locks;\n\tbool for_stack;\n};\n\nstruct panel_info {\n\tint xres;\n\tint yres;\n\tint valid;\n\tint clock;\n\tint hOver_plus;\n\tint hSync_width;\n\tint hblank;\n\tint vOver_plus;\n\tint vSync_width;\n\tint vblank;\n\tint hAct_high;\n\tint vAct_high;\n\tint interlaced;\n\tint pwr_delay;\n\tint use_bios_dividers;\n\tint ref_divider;\n\tint post_divider;\n\tint fbk_divider;\n};\n\nstruct papr_attr {\n\tu64 id;\n\tstruct kobj_attribute kobj_attr;\n};\n\nstruct papr_group {\n\tstruct attribute_group pg;\n\tstruct papr_attr pgattrs[3];\n};\n\nstruct papr_hvpipe_hdr {\n\t__u8 version;\n\t__u8 reserved[3];\n\t__u32 flags;\n\t__u8 reserved2[40];\n};\n\nstruct papr_indices_io_block {\n\tunion {\n\t\tstruct {\n\t\t\t__u8 is_sensor;\n\t\t\t__u32 indice_type;\n\t\t} indices;\n\t\tstruct {\n\t\t\t__u32 token;\n\t\t\t__u32 state;\n\t\t\tchar location_code_str[80];\n\t\t} dynamic_param;\n\t};\n};\n\nstruct papr_location_code {\n\tchar str[80];\n};\n\nstruct papr_ops_info {\n\tconst char *attr_name;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n};\n\nstruct papr_phy_attest_io_block {\n\t__u8 version;\n\t__u8 command;\n\t__u8 TCG_major_ver;\n\t__u8 TCG_minor_ver;\n\t__be32 length;\n\t__be32 correlator;\n\t__u8 payload[4084];\n};\n\nstruct papr_rtas_blob {\n\tconst char *data;\n\tsize_t len;\n};\n\nstruct papr_rtas_sequence {\n\tint error;\n\tvoid *params;\n\tvoid (*begin)(struct papr_rtas_sequence *);\n\tvoid (*end)(struct papr_rtas_sequence *);\n\tconst char * (*work)(struct papr_rtas_sequence *, size_t *);\n};\n\nstruct papr_sysparm_buf {\n\t__be16 len;\n\tu8 val[4000];\n};\n\nstruct papr_sysparm_io_block {\n\t__u32 parameter;\n\t__u16 length;\n\t__u8 data[4000];\n};\n\nstruct parallel_data {\n\tstruct padata_shell *ps;\n\tstruct padata_list *reorder_list;\n\tstruct padata_serial_queue *squeue;\n\trefcount_t refcnt;\n\tunsigned int seq_nr;\n\tunsigned int processed;\n\tint cpu;\n\tstruct padata_cpumask cpumask;\n};\n\nstruct parallel_io {\n\tstruct kref refcnt;\n\tvoid (*pnfs_callback)(void *);\n\tvoid *data;\n};\n\nstruct param_attr {\n\tstruct list_head list;\n\tu32 param_id;\n\tu32 param_size;\n\tstruct kobj_attribute kobj_attr;\n};\n\nstruct param_table {\n\tconst char *name;\n\tvoid (*fn)(int *, int, int);\n\tint *var;\n\tint def_param;\n\tint param2;\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct parsed_partitions {\n\tstruct gendisk *disk;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\nstruct partial_bulk_context {\n\tgfp_t flags;\n\tunsigned int min_objects;\n\tunsigned int max_objects;\n\tstruct list_head slabs;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct partial_context {\n\tgfp_t flags;\n\tunsigned int orig_size;\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct patb_entry {\n\t__be64 patb0;\n\t__be64 patb1;\n};\n\nstruct patch_context {\n\tunion {\n\t\tstruct vm_struct *area;\n\t\tstruct mm_struct *mm;\n\t};\n\tlong unsigned int addr;\n\tpte_t *pte;\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n\tstruct ethtool_pause_stats pausestat;\n};\n\nstruct pause_req_info {\n\tstruct ethnl_req_info base;\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct powercap_attr;\n\nstruct pcap {\n\tstruct attribute_group pg;\n\tstruct powercap_attr *pattrs;\n};\n\nstruct pccard_io_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t start;\n\tphys_addr_t stop;\n};\n\ntypedef struct pccard_io_map pccard_io_map;\n\nstruct pccard_mem_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t static_start;\n\tu_int card_start;\n\tstruct resource *res;\n};\n\ntypedef struct pccard_mem_map pccard_mem_map;\n\nstruct pcmcia_socket;\n\nstruct socket_state_t;\n\ntypedef struct socket_state_t socket_state_t;\n\nstruct pccard_operations {\n\tint (*init)(struct pcmcia_socket *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*get_status)(struct pcmcia_socket *, u_int *);\n\tint (*set_socket)(struct pcmcia_socket *, socket_state_t *);\n\tint (*set_io_map)(struct pcmcia_socket *, struct pccard_io_map *);\n\tint (*set_mem_map)(struct pcmcia_socket *, struct pccard_mem_map *);\n};\n\nstruct pccard_resource_ops {\n\tint (*validate_mem)(struct pcmcia_socket *);\n\tint (*find_io)(struct pcmcia_socket *, unsigned int, unsigned int *, unsigned int, unsigned int, struct resource **);\n\tstruct resource * (*find_mem)(long unsigned int, long unsigned int, long unsigned int, int, struct pcmcia_socket *);\n\tint (*init)(struct pcmcia_socket *);\n\tvoid (*exit)(struct pcmcia_socket *);\n};\n\nstruct pci_acs {\n\tu16 ctrl;\n\tu16 fw_ctrl;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nstruct pci_ops;\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n\tunsigned int unsafe_warn: 1;\n\tunsigned int flit_mode: 1;\n};\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\nstruct pci_controller_ops {\n\tvoid (*dma_dev_setup)(struct pci_dev *);\n\tvoid (*dma_bus_setup)(struct pci_bus *);\n\tbool (*iommu_bypass_supported)(struct pci_dev *, u64);\n\tint (*probe_mode)(struct pci_bus *);\n\tbool (*enable_device_hook)(struct pci_dev *);\n\tvoid (*disable_device)(struct pci_dev *);\n\tvoid (*release_device)(struct pci_dev *);\n\tresource_size_t (*window_alignment)(struct pci_bus *, long unsigned int);\n\tvoid (*setup_bridge)(struct pci_bus *, long unsigned int);\n\tvoid (*reset_secondary_bus)(struct pci_dev *);\n\tint (*setup_msi_irqs)(struct pci_dev *, int, int);\n\tvoid (*teardown_msi_irqs)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_controller *);\n\tstruct iommu_group * (*device_group)(struct pci_controller *, struct pci_dev *);\n};\n\nstruct pci_controller {\n\tstruct pci_bus *bus;\n\tchar is_dynamic;\n\tint node;\n\tstruct device_node *dn;\n\tstruct list_head list_node;\n\tstruct device *parent;\n\tint first_busno;\n\tint last_busno;\n\tint self_busno;\n\tstruct resource busn;\n\tvoid *io_base_virt;\n\tvoid *io_base_alloc;\n\tresource_size_t io_base_phys;\n\tresource_size_t pci_io_size;\n\tresource_size_t isa_mem_phys;\n\tresource_size_t isa_mem_size;\n\tstruct pci_controller_ops controller_ops;\n\tstruct pci_ops *ops;\n\tunsigned int *cfg_addr;\n\tvoid *cfg_data;\n\tu32 indirect_type;\n\tstruct resource io_resource;\n\tstruct resource mem_resources[3];\n\tresource_size_t mem_offset[3];\n\tint global_number;\n\tresource_size_t dma_window_base_cur;\n\tresource_size_t dma_window_size;\n\tlong unsigned int buid;\n\tstruct pci_dn *pci_data;\n\tvoid *private_data;\n\tstruct irq_domain *dev_domain;\n\tstruct iommu_device iommu;\n};\n\nstruct pci_vpd {\n\tstruct mutex lock;\n\tunsigned int len;\n\tu8 cap;\n};\n\nstruct pcie_bwctrl_data;\n\nstruct pcie_link_state;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tu32 devcap;\n\tu16 rebar_cap;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tu64 msi_addr_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int pinned: 1;\n\tunsigned int config_rrs_sv: 1;\n\tunsigned int imm_ready: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int no_bw_notif: 1;\n\tunsigned int d3hot_delay;\n\tunsigned int d3cold_delay;\n\tu16 l1ss;\n\tstruct pcie_link_state *link_state;\n\tunsigned int aspm_l0s_support: 1;\n\tunsigned int aspm_l1_support: 1;\n\tunsigned int ltr_path: 1;\n\tunsigned int pasid_no_tlp: 1;\n\tunsigned int eetlp_prefix_max: 3;\n\tpci_channel_state_t error_state;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[11];\n\tstruct resource driver_exclusive_resource;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int tph_enabled: 1;\n\tunsigned int fm_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int is_msi_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int is_pciehp: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int is_cxl: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int external_facing: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tunsigned int no_command_memory: 1;\n\tunsigned int rom_bar_overlap: 1;\n\tunsigned int rom_attr_enabled: 1;\n\tunsigned int non_mappable_bars: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tspinlock_t pcie_cap_lock;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *res_attr[11];\n\tstruct bin_attribute *res_attr_wc[11];\n\tvoid *msix_base;\n\traw_spinlock_t msi_lock;\n\tstruct pci_vpd vpd;\n\tstruct pcie_bwctrl_data *link_bwctrl;\n\tu16 acs_cap;\n\tu16 acs_capabilities;\n\tu8 supported_speeds;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tconst char *driver_override;\n\tlong unsigned int priv_flags;\n\tu8 reset_methods[8];\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, bool);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n\t__u32 override_only;\n};\n\nstruct pci_dn {\n\tint flags;\n\tint busno;\n\tint devfn;\n\tint vendor_id;\n\tint device_id;\n\tint class_code;\n\tstruct pci_dn *parent;\n\tstruct pci_controller *phb;\n\tstruct iommu_table_group *table_group;\n\tint pci_ext_config_space;\n\tstruct eeh_dev *edev;\n\tunsigned int pe_number;\n\tint mps;\n\tstruct list_head child_list;\n\tstruct list_head list;\n\tstruct resource holes[6];\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tint (*sriov_set_msix_vec_count)(struct pci_dev *, int);\n\tu32 (*sriov_get_vf_total_msix)(struct pci_dev *);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n\tbool driver_managed_dma;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct pci_eq_presets {\n\tu16 eq_presets_8gts[16];\n\tu8 eq_presets_Ngts[48];\n};\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, pci_channel_state_t);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n\tvoid (*cor_error_detected)(struct pci_dev *);\n};\n\nstruct pci_filp_private {\n\tenum pci_mmap_state mmap_state;\n\tint write_combine;\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tvoid (*hook)(struct pci_dev *);\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tstruct pci_ops *child_ops;\n\tvoid *sysdata;\n\tint busnr;\n\tint domain_nr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tint (*enable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid (*disable_device)(struct pci_host_bridge *, struct pci_dev *);\n\tvoid *release_data;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int no_inc_mrrs: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int native_cxl_error: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tunsigned int msi_domain: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nstruct pci_intx_virq {\n\tint virq;\n\tstruct kref kref;\n\tstruct list_head list_node;\n};\n\nstruct pci_io_addr_cache {\n\tstruct rb_root rb_root;\n\tspinlock_t piar_lock;\n};\n\nstruct pci_io_addr_range {\n\tstruct rb_node rb_node;\n\tresource_size_t addr_lo;\n\tresource_size_t addr_hi;\n\tstruct eeh_dev *edev;\n\tstruct pci_dev *pcidev;\n\tlong unsigned int flags;\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_probe_arg {\n\tstruct drv_dev_and_id *ddi;\n\tstruct work_struct work;\n\tint ret;\n};\n\nstruct pci_reset_fn_method {\n\tint (*reset_fn)(struct pci_dev *, bool);\n\tchar *name;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct serial_private;\n\nstruct pciserial_board;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tint: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n};\n\nstruct pcim_addr_devres {\n\tenum pcim_addr_devres_type type;\n\tvoid *baseaddr;\n\tlong unsigned int offset;\n\tlong unsigned int len;\n\tint bar;\n};\n\nstruct pcim_intx_devres {\n\tint orig_intx;\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[11];\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct pcmcia_callback {\n\tstruct module *owner;\n\tint (*add)(struct pcmcia_socket *);\n\tint (*remove)(struct pcmcia_socket *);\n\tvoid (*requery)(struct pcmcia_socket *);\n\tint (*validate)(struct pcmcia_socket *, unsigned int *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*early_resume)(struct pcmcia_socket *);\n\tint (*resume)(struct pcmcia_socket *);\n};\n\nstruct pcmcia_device;\n\nstruct pcmcia_cfg_mem {\n\tstruct pcmcia_device *p_dev;\n\tint (*conf_check)(struct pcmcia_device *, void *);\n\tvoid *priv_data;\n\tcisparse_t parse;\n\tcistpl_cftable_entry_t dflt;\n};\n\nstruct pcmcia_device {\n\tstruct pcmcia_socket *socket;\n\tchar *devname;\n\tu8 device_no;\n\tu8 func;\n\tstruct config_t *function_config;\n\tstruct list_head socket_device_list;\n\tunsigned int irq;\n\tstruct resource *resource[6];\n\tresource_size_t card_addr;\n\tunsigned int vpp;\n\tunsigned int config_flags;\n\tunsigned int config_base;\n\tunsigned int config_index;\n\tunsigned int config_regs;\n\tunsigned int io_lines;\n\tu16 suspended: 1;\n\tu16 _irq: 1;\n\tu16 _io: 1;\n\tu16 _win: 4;\n\tu16 _locked: 1;\n\tu16 allow_func_id_match: 1;\n\tu16 has_manf_id: 1;\n\tu16 has_card_id: 1;\n\tu16 has_func_id: 1;\n\tu16 reserved: 4;\n\tu8 func_id;\n\tu16 manf_id;\n\tu16 card_id;\n\tchar *prod_id[4];\n\tu64 dma_mask;\n\tstruct device dev;\n\tvoid *priv;\n\tunsigned int open;\n};\n\nstruct pcmcia_device_id {\n\t__u16 match_flags;\n\t__u16 manf_id;\n\t__u16 card_id;\n\t__u8 func_id;\n\t__u8 function;\n\t__u8 device_no;\n\t__u32 prod_id_hash[4];\n\tconst char *prod_id[4];\n\tkernel_ulong_t driver_info;\n\tchar *cisfile;\n};\n\nstruct pcmcia_dynids {\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct pcmcia_driver {\n\tconst char *name;\n\tint (*probe)(struct pcmcia_device *);\n\tvoid (*remove)(struct pcmcia_device *);\n\tint (*suspend)(struct pcmcia_device *);\n\tint (*resume)(struct pcmcia_device *);\n\tstruct module *owner;\n\tconst struct pcmcia_device_id *id_table;\n\tstruct device_driver drv;\n\tstruct pcmcia_dynids dynids;\n};\n\nstruct pcmcia_dynid {\n\tstruct list_head node;\n\tstruct pcmcia_device_id id;\n};\n\nstruct pcmcia_loop_get {\n\tsize_t len;\n\tcisdata_t **buf;\n};\n\nstruct tuple_t;\n\ntypedef struct tuple_t tuple_t;\n\nstruct pcmcia_loop_mem {\n\tstruct pcmcia_device *p_dev;\n\tvoid *priv_data;\n\tint (*loop_tuple)(struct pcmcia_device *, tuple_t *, void *);\n};\n\nstruct socket_state_t {\n\tu_int flags;\n\tu_int csc_mask;\n\tu_char Vcc;\n\tu_char Vpp;\n\tu_char io_irq;\n};\n\nstruct pcmcia_socket {\n\tstruct module *owner;\n\tsocket_state_t socket;\n\tu_int state;\n\tu_int suspended_state;\n\tu_short functions;\n\tu_short lock_count;\n\tpccard_mem_map cis_mem;\n\tvoid *cis_virt;\n\tio_window_t io[2];\n\tpccard_mem_map win[4];\n\tstruct list_head cis_cache;\n\tsize_t fake_cis_len;\n\tu8 *fake_cis;\n\tstruct list_head socket_list;\n\tstruct completion socket_released;\n\tunsigned int sock;\n\tu_int features;\n\tu_int irq_mask;\n\tu_int map_size;\n\tu_int io_offset;\n\tu_int pci_irq;\n\tstruct pci_dev *cb_dev;\n\tu8 resource_setup_done;\n\tstruct pccard_operations *ops;\n\tstruct pccard_resource_ops *resource_ops;\n\tvoid *resource_data;\n\tvoid (*zoom_video)(struct pcmcia_socket *, int);\n\tint (*power_hook)(struct pcmcia_socket *, int);\n\tvoid (*tune_bridge)(struct pcmcia_socket *, struct pci_bus *);\n\tstruct task_struct *thread;\n\tstruct completion thread_done;\n\tunsigned int thread_events;\n\tunsigned int sysfs_events;\n\tstruct mutex skt_mutex;\n\tstruct mutex ops_mutex;\n\tspinlock_t thread_lock;\n\tstruct pcmcia_callback *callback;\n\tstruct list_head devices_list;\n\tu8 device_count;\n\tu8 pcmcia_pfc;\n\tatomic_t present;\n\tunsigned int pcmcia_irq;\n\tstruct device dev;\n\tvoid *driver_data;\n\tint resume_status;\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpuobj_ext;\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tlong unsigned int *bound_map;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tbool isolated;\n\tint start_offset;\n\tint end_offset;\n\tstruct pcpuobj_ext *obj_exts;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_dstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tu64_stats_t rx_drops;\n\tu64_stats_t tx_drops;\n\tstruct u64_stats_sync syncp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\trqspinlock_t lock;\n};\n\nstruct pcpu_gen_cookie {\n\tlocal_t nesting;\n\tu64 last;\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpu_sw_netstats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpuobj_ext {\n\tstruct obj_cgroup *cgroup;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nstruct pdev_archdata {\n\tu64 dma_mask;\n\tvoid *priv;\n};\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[51];\n};\n\nstruct per_cpu_pages {\n\tspinlock_t lock;\n\tint count;\n\tint high;\n\tint high_min;\n\tint high_max;\n\tint batch;\n\tu8 flags;\n\tu8 alloc_factor;\n\tu8 expire;\n\tshort int free_count;\n\tstruct list_head lists[14];\n};\n\nstruct per_cpu_zonestat {\n\ts8 vm_stat_diff[11];\n\ts8 stat_threshold;\n\tlong unsigned int vm_numa_event[6];\n};\n\nstruct per_frame_masks {\n\tu64 may_read;\n\tu64 must_write;\n\tu64 must_write_acc;\n\tu64 live_before;\n};\n\nstruct percpu_free_defer {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref_data {\n\tatomic_long_t count;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n\tstruct percpu_ref *ref;\n};\n\ntypedef struct percpu_rw_semaphore *class_percpu_read_t;\n\ntypedef struct percpu_rw_semaphore *class_percpu_write_t;\n\nstruct percpu_swap_cluster {\n\tstruct swap_info_struct *si[1];\n\tlong unsigned int offset[1];\n\tlocal_lock_t lock;\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu64 hw_id;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___3 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct perf_event_mmap_page;\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\trefcount_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tstruct mutex aux_mutex;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\trefcount_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tint aux_in_pause_resume;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct unwind_stacktrace;\n\nstruct perf_callchain_deferred_event {\n\tstruct unwind_stacktrace *trace;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 cookie;\n\t\tu64 nr;\n\t\tu64 ips[0];\n\t} event;\n};\n\nstruct perf_callchain_entry {\n\tu64 nr;\n\tu64 ip[0];\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nstruct perf_cgroup_info;\n\nstruct perf_cgroup {\n\tstruct cgroup_subsys_state css;\n\tstruct perf_cgroup_info *info;\n};\n\nstruct perf_cgroup_event {\n\tchar *path;\n\tint path_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 id;\n\t\tchar path[0];\n\t} event_id;\n};\n\nstruct perf_time_ctx {\n\tu64 time;\n\tu64 stamp;\n\tu64 offset;\n};\n\nstruct perf_cgroup_info {\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tint active;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tu64 index;\n};\n\nstruct perf_event_context {\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head pmu_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tint nr_events;\n\tint nr_user;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tstruct perf_time_ctx time;\n\tstruct perf_time_ctx timeguest;\n\tstruct perf_event_context *parent_ctx;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tint nr_cgroups;\n\tstruct callback_head callback_head;\n\tlocal_t nr_no_switch_fast;\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint online;\n\tstruct perf_cgroup *cgrp;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_event_pmu_context {\n\tstruct pmu *pmu;\n\tstruct perf_event_context *ctx;\n\tstruct list_head pmu_ctx_entry;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tunsigned int embedded: 1;\n\tunsigned int nr_events;\n\tunsigned int nr_cgroups;\n\tunsigned int nr_freq;\n\tatomic_t refcount;\n\tstruct callback_head callback_head;\n\tint rotate_necessary;\n};\n\nstruct perf_cpu_pmu_context {\n\tstruct perf_event_pmu_context epc;\n\tstruct perf_event_pmu_context *task_epc;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint active_oncpu;\n\tint exclusive;\n\tint pmu_disable_count;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n};\n\nstruct perf_ctx_data {\n\tstruct callback_head callback_head;\n\trefcount_t refcount;\n\tint global;\n\tstruct kmem_cache *ctx_cache;\n\tvoid *data;\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 text_poke: 1;\n\t__u64 build_id: 1;\n\t__u64 inherit_thread: 1;\n\t__u64 remove_on_exec: 1;\n\t__u64 sigtrap: 1;\n\t__u64 defer_callchain: 1;\n\t__u64 defer_output: 1;\n\t__u64 __reserved_1: 24;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\tunion {\n\t\t__u32 aux_action;\n\t\tstruct {\n\t\t\t__u32 aux_start_paused: 1;\n\t\t\t__u32 aux_pause: 1;\n\t\t\t__u32 aux_resume: 1;\n\t\t\t__u32 __reserved_3: 29;\n\t\t};\n\t};\n\t__u64 sig_data;\n\t__u64 config3;\n\t__u64 config4;\n};\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tunsigned int group_generation;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tstruct perf_event_pmu_context *pmu_ctx;\n\tatomic_long_t refcount;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\trefcount_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tunsigned int pending_wakeup;\n\tunsigned int pending_kill;\n\tunsigned int pending_disable;\n\tlong unsigned int pending_addr;\n\tstruct irq_work pending_irq;\n\tstruct irq_work pending_disable_irq;\n\tstruct callback_head pending_task;\n\tunsigned int pending_work;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tu64 id;\n\tatomic64_t lost_samples;\n\tu64 (*clock)(void);\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tstruct bpf_prog *prog;\n\tu64 bpf_cookie;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tstruct ftrace_ops ftrace_ops;\n\tstruct perf_cgroup *cgrp;\n\tvoid *security;\n\tstruct list_head sb_list;\n\tstruct list_head pmu_list;\n\tu32 orig_type;\n};\n\nstruct perf_event_min_heap {\n\tsize_t nr;\n\tsize_t size;\n\tstruct perf_event **data;\n\tstruct perf_event *preallocated[0];\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_user_time_short: 1;\n\t\t\t__u64 cap_____res: 58;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u32 __reserved_1;\n\t__u64 time_cycles;\n\t__u64 time_mask;\n\t__u8 __reserved[928];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct perf_event_security_struct {\n\tu32 sid;\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tu8 build_id[20];\n\tu32 build_id_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tunion {\n\t\tu64 flags;\n\t\tu64 aux_flags;\n\t\tstruct {\n\t\t\tu64 skip_read: 1;\n\t\t};\n\t};\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n} __attribute__((packed));\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_text_poke_event {\n\tconst void *old_bytes;\n\tconst void *new_bytes;\n\tsize_t pad;\n\tu16 old_len;\n\tu16 new_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t} event_id;\n};\n\nstruct pericom8250 {\n\tvoid *virt;\n\tunsigned int nr;\n\tint line[0];\n};\n\nstruct perm_datum {\n\tu32 value;\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tvoid (*exit_rtnl)(struct net *, struct list_head *);\n\tunsigned int * const id;\n\tconst size_t size;\n};\n\nstruct pf_desc {\n\tu32 pseudoflavor;\n\tu32 qop;\n\tu32 service;\n\tchar *name;\n\tchar *auth_domain_name;\n\tstruct auth_domain *domain;\n\tbool datatouch;\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct ptdump_range;\n\nstruct ptdump_state {\n\tvoid (*note_page_pte)(struct ptdump_state *, long unsigned int, pte_t);\n\tvoid (*note_page_pmd)(struct ptdump_state *, long unsigned int, pmd_t);\n\tvoid (*note_page_pud)(struct ptdump_state *, long unsigned int, pud_t);\n\tvoid (*note_page_p4d)(struct ptdump_state *, long unsigned int, p4d_t);\n\tvoid (*note_page_pgd)(struct ptdump_state *, long unsigned int, pgd_t);\n\tvoid (*note_page_flush)(struct ptdump_state *);\n\tvoid (*effective_prot_pte)(struct ptdump_state *, pte_t);\n\tvoid (*effective_prot_pmd)(struct ptdump_state *, pmd_t);\n\tvoid (*effective_prot_pud)(struct ptdump_state *, pud_t);\n\tvoid (*effective_prot_p4d)(struct ptdump_state *, p4d_t);\n\tvoid (*effective_prot_pgd)(struct ptdump_state *, pgd_t);\n\tconst struct ptdump_range *range;\n};\n\nstruct pg_state {\n\tstruct ptdump_state ptdump;\n\tstruct seq_file *seq;\n\tconst struct addr_marker *marker;\n\tlong unsigned int start_address;\n\tlong unsigned int start_pa;\n\tint level;\n\tu64 current_flags;\n\tbool check_wx;\n\tlong unsigned int wx_pages;\n};\n\nstruct zone {\n\tlong unsigned int _watermark[4];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong unsigned int nr_free_highatomic;\n\tlong int lowmem_reserve[3];\n\tint node;\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pages *per_cpu_pageset;\n\tstruct per_cpu_zonestat *per_cpu_zonestats;\n\tint pageset_high_min;\n\tint pageset_high_max;\n\tint pageset_batch;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tlong unsigned int present_early_pages;\n\tlong unsigned int cma_pages;\n\tconst char *name;\n\tlong unsigned int nr_isolate_pageblock;\n\tseqlock_t span_seqlock;\n\tint initialized;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tstruct free_area free_area[9];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tstruct llist_head trylock_free_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad3_;\n\tatomic_long_t vm_stat[11];\n\tatomic_long_t vm_numa_event[6];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[769];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[3];\n\tstruct zonelist node_zonelists[2];\n\tint nr_zones;\n\tspinlock_t node_size_lock;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\twait_queue_head_t reclaim_wait[4];\n\tatomic_t nr_writeback_throttled;\n\tlong unsigned int nr_reclaim_start;\n\tstruct mutex kswapd_lock;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tatomic_t kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tbool proactive_compact_trigger;\n\tlong unsigned int totalreserve_pages;\n\tlong unsigned int min_unmapped_pages;\n\tlong unsigned int min_slab_pages;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad1_;\n\tlong unsigned int first_deferred_pfn;\n\tstruct deferred_split deferred_split_queue;\n\tunsigned int nbp_rl_start;\n\tlong unsigned int nbp_rl_nr_cand;\n\tunsigned int nbp_threshold;\n\tunsigned int nbp_th_start;\n\tlong unsigned int nbp_th_nr_cand;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cacheline_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[51];\n\tstruct memory_tier *memtier;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct phc_vclocks_reply_data {\n\tstruct ethnl_reply_data base;\n\tint num;\n\tint *index;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tu32 max_link_rate;\n\tenum phy_mode mode;\n};\n\nstruct phy_ops;\n\nstruct phy___2 {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tstruct lock_class_key lockdep_key;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n\tstruct dentry *debugfs;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 mmds_present;\n\tu32 device_ids[32];\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_lvds {\n\tunsigned int bits_per_lane_and_dclk_cycle;\n\tlong unsigned int differential_clk_rate;\n\tunsigned int lanes;\n\tbool is_slave;\n};\n\nstruct phy_configure_opts_hdmi {\n\tunsigned int bpc;\n\tunion {\n\t\tlong long unsigned int tmds_char_rate;\n\t\tstruct {\n\t\t\tu8 rate_per_lane;\n\t\t\tu8 lanes;\n\t\t} frl;\n\t};\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n\tstruct phy_configure_opts_lvds lvds;\n\tstruct phy_configure_opts_hdmi hdmi;\n};\n\nstruct phylink;\n\nstruct pse_control;\n\nstruct phy_oatc14_sqi_capability {\n\tbool updated;\n\tint sqi_max;\n\tu8 sqiplus_bits;\n};\n\nstruct phy_driver;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tconst struct phy_driver *drv;\n\tstruct device_link *devlink;\n\tu32 phyindex;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int is_on_sfp_module: 1;\n\tunsigned int mac_managed_pm: 1;\n\tunsigned int wol_enabled: 1;\n\tunsigned int is_genphy_driven: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tbool pause: 1;\n\tbool asym_pause: 1;\n\tunsigned int interrupts: 1;\n\tunsigned int irq_suspended: 1;\n\tunsigned int irq_rerun: 1;\n\tunsigned int default_timestamp: 1;\n\tint rate_matching;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tlong unsigned int possible_interfaces[1];\n\tint speed;\n\tint duplex;\n\tint port;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tlong unsigned int adv_old[2];\n\tlong unsigned int supported_eee[2];\n\tlong unsigned int advertising_eee[2];\n\tlong unsigned int eee_disabled_modes[2];\n\tbool enable_tx_lpi;\n\tbool eee_active;\n\tstruct eee_config eee_cfg;\n\tlong unsigned int host_interfaces[1];\n\tstruct list_head leds;\n\tint irq;\n\tvoid *priv;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tstruct pse_control *psec;\n\tstruct list_head ports;\n\tint n_ports;\n\tint max_n_ports;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tint pma_extable;\n\tunsigned int link_down_events;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n\tstruct phy_oatc14_sqi_capability oatc14_sqi_capability;\n};\n\nstruct phy_device_node {\n\tenum phy_upstream upstream_type;\n\tunion {\n\t\tstruct net_device *netdev;\n\t\tstruct phy_device *phydev;\n\t} upstream;\n\tstruct sfp_bus *parent_sfp_bus;\n\tstruct phy_device *phy;\n};\n\nstruct phy_port;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tunsigned int (*inband_caps)(struct phy_device *, phy_interface_t);\n\tint (*config_inband)(struct phy_device *, unsigned int);\n\tint (*get_rate_matching)(struct phy_device *, phy_interface_t);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *, const struct phy_driver *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n\tint (*update_stats)(struct phy_device *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool, int);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n\tint (*get_mse_capability)(struct phy_device *, struct phy_mse_capability *);\n\tint (*get_mse_snapshot)(struct phy_device *, enum phy_mse_channel, struct phy_mse_snapshot *);\n\tint (*get_plca_cfg)(struct phy_device *, struct phy_plca_cfg *);\n\tint (*set_plca_cfg)(struct phy_device *, const struct phy_plca_cfg *);\n\tint (*get_plca_status)(struct phy_device *, struct phy_plca_status *);\n\tint (*led_brightness_set)(struct phy_device *, u8, enum led_brightness);\n\tint (*led_blink_set)(struct phy_device *, u8, long unsigned int *, long unsigned int *);\n\tint (*led_hw_is_supported)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_set)(struct phy_device *, u8, long unsigned int);\n\tint (*led_hw_control_get)(struct phy_device *, u8, long unsigned int *);\n\tint (*led_polarity_set)(struct phy_device *, int, long unsigned int);\n\tunsigned int (*get_next_update_time)(struct phy_device *);\n\tint (*attach_mii_port)(struct phy_device *, struct phy_port *);\n\tint (*attach_mdi_port)(struct phy_device *, struct phy_port *);\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct phy_link_topology {\n\tstruct xarray phys;\n\tu32 next_phy_index;\n};\n\nstruct phy_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct phy___2 *phy;\n};\n\nunion phy_notify {\n\tenum phy_ufs_state ufs_state;\n};\n\nstruct phy_ops {\n\tint (*init)(struct phy___2 *);\n\tint (*exit)(struct phy___2 *);\n\tint (*power_on)(struct phy___2 *);\n\tint (*power_off)(struct phy___2 *);\n\tint (*set_mode)(struct phy___2 *, enum phy_mode, int);\n\tint (*set_media)(struct phy___2 *, enum phy_media);\n\tint (*set_speed)(struct phy___2 *, int);\n\tint (*configure)(struct phy___2 *, union phy_configure_opts *);\n\tint (*validate)(struct phy___2 *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy___2 *);\n\tint (*calibrate)(struct phy___2 *);\n\tint (*connect)(struct phy___2 *, int);\n\tint (*disconnect)(struct phy___2 *, int);\n\tint (*notify_phystate)(struct phy___2 *, union phy_notify);\n\tvoid (*release)(struct phy___2 *);\n\tstruct module *owner;\n};\n\nstruct phy_plca_cfg {\n\tint version;\n\tint enabled;\n\tint node_id;\n\tint node_cnt;\n\tint to_tmr;\n\tint burst_cnt;\n\tint burst_tmr;\n};\n\nstruct phy_plca_status {\n\tbool pst;\n};\n\nstruct phy_port_ops;\n\nstruct phy_port {\n\tstruct list_head head;\n\tenum phy_port_parent parent_type;\n\tunion {\n\t\tstruct phy_device *phy;\n\t};\n\tconst struct phy_port_ops *ops;\n\tint pairs;\n\tlong unsigned int mediums;\n\tlong unsigned int supported[2];\n\tlong unsigned int interfaces[1];\n\tunsigned int not_described: 1;\n\tunsigned int active: 1;\n\tunsigned int is_mii: 1;\n\tunsigned int is_sfp: 1;\n};\n\nstruct phy_port_ops {\n\tvoid (*link_up)(struct phy_port *);\n\tvoid (*link_down)(struct phy_port *);\n\tint (*configure_mii)(struct phy_port *, bool, phy_interface_t);\n};\n\nstruct phy_provider {\n\tstruct device *dev;\n\tstruct device_node *children;\n\tstruct module *owner;\n\tstruct list_head list;\n\tstruct phy___2 * (*of_xlate)(struct device *, const struct of_phandle_args *);\n};\n\nstruct phy_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 phyindex;\n\tchar *drvname;\n\tchar *name;\n\tunsigned int upstream_type;\n\tchar *upstream_sfp_name;\n\tunsigned int upstream_index;\n\tchar *downstream_sfp_name;\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct phylib_stubs {\n\tint (*hwtstamp_get)(struct phy_device *, struct kernel_hwtstamp_config *);\n\tint (*hwtstamp_set)(struct phy_device *, struct kernel_hwtstamp_config *, struct netlink_ext_ack *);\n\tvoid (*get_phy_stats)(struct phy_device *, struct ethtool_eth_phy_stats *, struct ethtool_phy_stats *);\n\tvoid (*get_link_ext_stats)(struct phy_device *, struct ethtool_link_ext_stats *);\n};\n\nstruct phys_vec {\n\tphys_addr_t paddr;\n\tsize_t len;\n};\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pidfs_attr;\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tstruct {\n\t\tu64 ino;\n\t\tstruct rhash_head pidfs_hash;\n\t\tstruct dentry *stashed;\n\t\tstruct pidfs_attr *attr;\n\t};\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tint lsmid;\n};\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct pid_namespace {\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tint memfd_noexec_scope;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tint pid_max;\n\tstruct pid_namespace *parent;\n\tstruct fs_pin *bacct;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct work_struct work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct pidfd_info {\n\t__u64 mask;\n\t__u64 cgroupid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 ppid;\n\t__u32 ruid;\n\t__u32 rgid;\n\t__u32 euid;\n\t__u32 egid;\n\t__u32 suid;\n\t__u32 sgid;\n\t__u32 fsuid;\n\t__u32 fsgid;\n\t__s32 exit_code;\n\tstruct {\n\t\t__u32 coredump_mask;\n\t\t__u32 coredump_signal;\n\t};\n\t__u64 supported_mask;\n};\n\nstruct pidfs_attr {\n\tlong unsigned int attr_mask;\n\tstruct simple_xattrs *xattrs;\n\tstruct {\n\t\t__u64 cgroupid;\n\t\t__s32 exit_code;\n\t};\n\t__u32 coredump_mask;\n\t__u32 coredump_signal;\n};\n\nstruct pids_cgroup {\n\tstruct cgroup_subsys_state css;\n\tatomic64_t counter;\n\tatomic64_t limit;\n\tint64_t watermark;\n\tstruct cgroup_file events_file;\n\tstruct cgroup_file events_local_file;\n\tatomic64_t events[2];\n\tatomic64_t events_local[2];\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct ping_table {\n\tstruct hlist_head hash[64];\n\tspinlock_t lock;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct pinned_mountpoint {\n\tstruct hlist_node node;\n\tstruct mountpoint *mp;\n\tstruct mount *parent;\n};\n\nstruct pipe_buffer;\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nunion pipe_index {\n\tlong unsigned int head_tail;\n\tstruct {\n\t\tpipe_index_t head;\n\t\tpipe_index_t tail;\n\t};\n};\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunion pipe_index;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tbool poll_usage;\n\tstruct page *tmp_page[2];\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct pipe_wait {\n\tstruct trace_iterator *iter;\n\tint wait_index;\n};\n\nstruct pkcs1pad_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct pkcs1pad_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n};\n\nstruct pkcs1pad_request {\n\tstruct scatterlist in_sg[2];\n\tstruct scatterlist out_sg[1];\n\tuint8_t *in_buf;\n\tuint8_t *out_buf;\n\tstruct akcipher_request child_req;\n};\n\nstruct x509_certificate;\n\nstruct pkcs7_signed_info;\n\nstruct pkcs7_message {\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate *crl;\n\tstruct pkcs7_signed_info *signed_infos;\n\tu8 version;\n\tbool have_authattrs;\n\tenum OID data_type;\n\tsize_t data_len;\n\tsize_t data_hdrlen;\n\tconst void *data;\n};\n\nstruct pkcs7_parse_context {\n\tstruct pkcs7_message *msg;\n\tstruct pkcs7_signed_info *sinfo;\n\tstruct pkcs7_signed_info **ppsinfo;\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate **ppcerts;\n\tlong unsigned int data;\n\tenum OID last_oid;\n\tunsigned int x509_index;\n\tunsigned int sinfo_index;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_skid;\n\tunsigned int raw_skid_size;\n\tbool expect_skid;\n};\n\nstruct pkcs7_signed_info {\n\tstruct pkcs7_signed_info *next;\n\tstruct x509_certificate *signer;\n\tunsigned int index;\n\tbool unsupported_crypto;\n\tbool blacklisted;\n\tconst void *msgdigest;\n\tunsigned int msgdigest_len;\n\tunsigned int authattrs_len;\n\tconst void *authattrs;\n\tlong unsigned int aa_set;\n\ttime64_t signing_time;\n\tstruct public_key_signature *sig;\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tunsigned int uartclk;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tunsigned int type;\n\tupf_t flags;\n\tu16 bugs;\n\tu32 (*serial_in)(struct uart_port *, unsigned int);\n\tvoid (*serial_out)(struct uart_port *, unsigned int, u32);\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n};\n\nstruct sensor_group_data;\n\nstruct platform_data {\n\tconst struct attribute_group *attr_groups[7];\n\tstruct sensor_group_data *sgrp_data;\n\tu32 sensors_count;\n\tu32 nr_sensor_groups;\n};\n\nstruct mfd_cell;\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tconst char *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct platform_device_id {\n\tchar name[24];\n\tkernel_ulong_t driver_data;\n};\n\nstruct property_entry;\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tvoid (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n\tbool driver_managed_dma;\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)(void);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tvoid (*check)(void);\n\tbool (*wake)(void);\n\tvoid (*restore_early)(void);\n\tvoid (*restore)(void);\n\tvoid (*end)(void);\n};\n\nstruct platform_support {\n\tbool hash_mmu;\n\tbool radix_mmu;\n\tbool radix_gtse;\n\tbool xive;\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)(void);\n\tint (*prepare_late)(void);\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)(void);\n\tvoid (*finish)(void);\n\tbool (*suspend_again)(void);\n\tvoid (*end)(void);\n\tvoid (*recover)(void);\n};\n\nstruct plca_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct phy_plca_cfg plca_cfg;\n\tstruct phy_plca_status plca_st;\n};\n\nstruct pldm_pci_record_id {\n\tint vendor;\n\tint device;\n\tint subsystem_vendor;\n\tint subsystem_device;\n};\n\nstruct pldmfw_ops;\n\nstruct pldmfw {\n\tconst struct pldmfw_ops *ops;\n\tstruct device *dev;\n\tu16 component_identifier;\n\tenum pldmfw_update_mode mode;\n};\n\nstruct pldmfw_component {\n\tstruct list_head entry;\n\tu16 classification;\n\tu16 identifier;\n\tu16 options;\n\tu16 activation_method;\n\tu32 comparison_stamp;\n\tu32 component_size;\n\tconst u8 *component_data;\n\tconst u8 *version_string;\n\tu8 version_type;\n\tu8 version_len;\n\tu8 index;\n};\n\nstruct pldmfw_desc_tlv {\n\tstruct list_head entry;\n\tconst u8 *data;\n\tu16 type;\n\tu16 size;\n};\n\nstruct pldmfw_record;\n\nstruct pldmfw_ops {\n\tbool (*match_record)(struct pldmfw *, struct pldmfw_record *);\n\tint (*send_package_data)(struct pldmfw *, const u8 *, u16);\n\tint (*send_component_table)(struct pldmfw *, struct pldmfw_component *, u8);\n\tint (*flash_component)(struct pldmfw *, struct pldmfw_component *);\n\tint (*finalize_update)(struct pldmfw *);\n};\n\nstruct pldmfw_priv {\n\tstruct pldmfw *context;\n\tconst struct firmware *fw;\n\tsize_t offset;\n\tstruct list_head records;\n\tstruct list_head components;\n\tconst struct __pldm_header *header;\n\tu16 total_header_size;\n\tu16 component_bitmap_len;\n\tu16 bitmap_size;\n\tu16 component_count;\n\tconst u8 *component_start;\n\tconst u8 *record_start;\n\tu8 record_count;\n\tu32 header_crc;\n\tstruct pldmfw_record *matching_record;\n};\n\nstruct pldmfw_record {\n\tstruct list_head entry;\n\tstruct list_head descs;\n\tconst u8 *version_string;\n\tu8 version_type;\n\tu8 version_len;\n\tu16 package_data_len;\n\tu32 device_update_flags;\n\tconst u8 *package_data;\n\tlong unsigned int *component_bitmap;\n\tu16 component_bitmap_len;\n};\n\nstruct pll_info {\n\tint ppll_max;\n\tint ppll_min;\n\tint sclk;\n\tint mclk;\n\tint ref_div;\n\tint ref_clk;\n};\n\nstruct plpks_auth {\n\tu8 version;\n\tu8 consumer;\n\t__be64 rsvd0;\n\t__be32 rsvd1;\n\t__be16 passwordlength;\n\tu8 password[0];\n} __attribute__((packed));\n\nstruct plpks_var {\n\tchar *component;\n\tu8 *name;\n\tu8 *data;\n\tu32 policy;\n\tu16 namelen;\n\tu16 datalen;\n\tu8 os;\n};\n\nstruct plpks_var_name {\n\tu8 *name;\n\tu16 namelen;\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct pmem_device {\n\tphys_addr_t phys_addr;\n\tphys_addr_t data_offset;\n\tvoid *virt_addr;\n\tsize_t size;\n\tu32 pfn_pad;\n\tstruct kernfs_node *bb_state;\n\tstruct badblocks bb;\n\tstruct dax_device *dax_dev;\n\tstruct gendisk *disk;\n\tstruct dev_pagemap pgmap;\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tunion {\n\t\tstruct list_head free_node;\n\t\tstruct callback_head rcu;\n\t};\n\tu32 flags;\n\tu8 protocol;\n\tbool permanent;\n\tu32 key[0];\n};\n\nstruct pnfs_block_dev_map;\n\nstruct pnfs_block_dev {\n\tstruct nfs4_deviceid_node node;\n\tu64 start;\n\tu64 len;\n\tenum pnfs_block_volume_type type;\n\tu32 nr_children;\n\tstruct pnfs_block_dev *children;\n\tu64 chunk_size;\n\tstruct file *bdev_file;\n\tu64 disk_offset;\n\tlong unsigned int flags;\n\tu64 pr_key;\n\tbool (*map)(struct pnfs_block_dev *, u64, struct pnfs_block_dev_map *);\n};\n\nstruct pnfs_block_dev_map {\n\tu64 start;\n\tu64 len;\n\tu64 disk_offset;\n\tstruct block_device *bdev;\n};\n\nstruct pnfs_block_extent {\n\tunion {\n\t\tstruct rb_node be_node;\n\t\tstruct list_head be_list;\n\t};\n\tstruct nfs4_deviceid_node *be_device;\n\tsector_t be_f_offset;\n\tsector_t be_length;\n\tsector_t be_v_offset;\n\tenum pnfs_block_extent_state be_state;\n\tunsigned int be_tag;\n};\n\nstruct pnfs_block_layout {\n\tstruct pnfs_layout_hdr bl_layout;\n\tstruct rb_root bl_ext_rw;\n\tstruct rb_root bl_ext_ro;\n\tspinlock_t bl_ext_lock;\n\tbool bl_scsi_layout;\n\tu64 bl_lwb;\n};\n\nstruct pnfs_block_volume {\n\tenum pnfs_block_volume_type type;\n\tunion {\n\t\tstruct {\n\t\t\tint len;\n\t\t\tint nr_sigs;\n\t\t\tstruct {\n\t\t\t\tu64 offset;\n\t\t\t\tu32 sig_len;\n\t\t\t\tu8 sig[128];\n\t\t\t} sigs[4];\n\t\t} simple;\n\t\tstruct {\n\t\t\tu64 start;\n\t\t\tu64 len;\n\t\t\tu32 volume;\n\t\t} slice;\n\t\tstruct {\n\t\t\tu32 volumes_count;\n\t\t\tu32 volumes[64];\n\t\t} concat;\n\t\tstruct {\n\t\t\tu64 chunk_size;\n\t\t\tu32 volumes_count;\n\t\t\tu32 volumes[64];\n\t\t} stripe;\n\t\tstruct {\n\t\t\tenum scsi_code_set code_set;\n\t\t\tenum scsi_designator_type designator_type;\n\t\t\tint designator_len;\n\t\t\tu8 designator[256];\n\t\t\tu64 pr_key;\n\t\t} scsi;\n\t};\n};\n\nstruct pnfs_commit_bucket {\n\tstruct list_head written;\n\tstruct list_head committing;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_writeverf direct_verf;\n};\n\nstruct pnfs_commit_array {\n\tstruct list_head cinfo_list;\n\tstruct list_head lseg_list;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tunsigned int nbuckets;\n\tstruct pnfs_commit_bucket buckets[0];\n};\n\nstruct pnfs_commit_ops {\n\tvoid (*setup_ds_info)(struct pnfs_ds_commit_info *, struct pnfs_layout_segment *);\n\tvoid (*release_ds_info)(struct pnfs_ds_commit_info *, struct inode *);\n\tint (*commit_pagelist)(struct inode *, struct list_head *, int, struct nfs_commit_info *);\n\tvoid (*mark_request_commit)(struct nfs_page *, struct pnfs_layout_segment *, struct nfs_commit_info *, u32);\n\tvoid (*clear_request_commit)(struct nfs_page *, struct nfs_commit_info *);\n\tint (*scan_commit_lists)(struct nfs_commit_info *, int);\n\tvoid (*recover_commit_reqs)(struct list_head *, struct nfs_commit_info *);\n};\n\nstruct pnfs_device {\n\tstruct nfs4_deviceid dev_id;\n\tunsigned int layout_type;\n\tunsigned int mincount;\n\tunsigned int maxcount;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tunsigned char nocache: 1;\n};\n\nstruct pnfs_layoutdriver_type {\n\tstruct list_head pnfs_tblid;\n\tconst u32 id;\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int flags;\n\tunsigned int max_layoutget_response;\n\tint (*set_layoutdriver)(struct nfs_server *, const struct nfs_fh *);\n\tint (*clear_layoutdriver)(struct nfs_server *);\n\tstruct pnfs_layout_hdr * (*alloc_layout_hdr)(struct inode *, gfp_t);\n\tvoid (*free_layout_hdr)(struct pnfs_layout_hdr *);\n\tstruct pnfs_layout_segment * (*alloc_lseg)(struct pnfs_layout_hdr *, struct nfs4_layoutget_res *, gfp_t);\n\tvoid (*free_lseg)(struct pnfs_layout_segment *);\n\tvoid (*add_lseg)(struct pnfs_layout_hdr *, struct pnfs_layout_segment *, struct list_head *);\n\tvoid (*return_range)(struct pnfs_layout_hdr *, struct pnfs_layout_range *);\n\tconst struct nfs_pageio_ops *pg_read_ops;\n\tconst struct nfs_pageio_ops *pg_write_ops;\n\tstruct pnfs_ds_commit_info * (*get_ds_info)(struct inode *);\n\tint (*sync)(struct inode *, bool);\n\tenum pnfs_try_status (*read_pagelist)(struct nfs_pgio_header *);\n\tenum pnfs_try_status (*write_pagelist)(struct nfs_pgio_header *, int);\n\tvoid (*free_deviceid_node)(struct nfs4_deviceid_node *);\n\tstruct nfs4_deviceid_node * (*alloc_deviceid_node)(struct nfs_server *, struct pnfs_device *, gfp_t);\n\tint (*prepare_layoutreturn)(struct nfs4_layoutreturn_args *);\n\tvoid (*cleanup_layoutcommit)(struct nfs4_layoutcommit_data *);\n\tint (*prepare_layoutcommit)(struct nfs4_layoutcommit_args *);\n\tint (*prepare_layoutstats)(struct nfs42_layoutstat_args *);\n\tvoid (*cancel_io)(struct pnfs_layout_segment *);\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_device_id;\n\nstruct pnp_dev;\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_link;\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pnv_idle_states_t {\n\tchar name[16];\n\tu32 latency_ns;\n\tu32 residency_ns;\n\tu64 psscr_val;\n\tu64 psscr_mask;\n\tu32 flags;\n\tbool valid;\n};\n\nstruct pnv_phb;\n\nstruct pnv_ioda_pe {\n\tlong unsigned int flags;\n\tstruct pnv_phb *phb;\n\tint device_count;\n\tstruct pci_dev *pdev;\n\tstruct pci_bus *pbus;\n\tunsigned int rid;\n\tunsigned int pe_number;\n\tstruct iommu_table_group table_group;\n\tbool tce_bypass_enabled;\n\tuint64_t tce_bypass_base;\n\tbool dma_setup_done;\n\tint mve_number;\n\tstruct pnv_ioda_pe *master;\n\tstruct list_head slaves;\n\tstruct list_head list;\n};\n\nstruct pnv_phb {\n\tstruct pci_controller *hose;\n\tenum pnv_phb_type type;\n\tenum pnv_phb_model model;\n\tu64 hub_id;\n\tu64 opal_id;\n\tint flags;\n\tvoid *regs;\n\tu64 regs_phys;\n\tspinlock_t lock;\n\tint has_dbgfs;\n\tstruct dentry *dbgfs;\n\tunsigned int msi_base;\n\tstruct msi_bitmap msi_bmp;\n\tint (*init_m64)(struct pnv_phb *);\n\tint (*get_pe_state)(struct pnv_phb *, int);\n\tvoid (*freeze_pe)(struct pnv_phb *, int);\n\tint (*unfreeze_pe)(struct pnv_phb *, int, int);\n\tstruct {\n\t\tunsigned int total_pe_num;\n\t\tunsigned int reserved_pe_idx;\n\t\tunsigned int root_pe_idx;\n\t\tunsigned int m32_size;\n\t\tunsigned int m32_segsize;\n\t\tunsigned int m32_pci_base;\n\t\tunsigned int m64_bar_idx;\n\t\tlong unsigned int m64_size;\n\t\tlong unsigned int m64_segsize;\n\t\tlong unsigned int m64_base;\n\t\tlong unsigned int m64_bar_alloc;\n\t\tunsigned int io_size;\n\t\tunsigned int io_segsize;\n\t\tunsigned int io_pci_base;\n\t\tstruct mutex pe_alloc_mutex;\n\t\tlong unsigned int *pe_alloc;\n\t\tstruct pnv_ioda_pe *pe_array;\n\t\tunsigned int *m64_segmap;\n\t\tunsigned int *m32_segmap;\n\t\tunsigned int *io_segmap;\n\t\tstruct irq_chip irq_chip;\n\t\tstruct list_head pe_list;\n\t\tstruct mutex pe_list_mutex;\n\t\tunsigned int pe_rmap[65536];\n\t} ioda;\n\tunsigned int diag_data_size;\n\tu8 *diag_data;\n};\n\nstruct pnv_rng {\n\tvoid *regs;\n\tvoid *regs_real;\n\tlong unsigned int mask;\n};\n\nstruct vas_user_win_ref {\n\tstruct pid *pid;\n\tstruct pid *tgid;\n\tstruct mm_struct *mm;\n\tstruct mutex mmap_mutex;\n\tstruct vm_area_struct *vma;\n};\n\nstruct vas_window {\n\tu32 winid;\n\tu32 wcreds_max;\n\tu32 status;\n\tenum vas_cop_type cop;\n\tstruct vas_user_win_ref task_ref;\n\tchar *dbgname;\n\tstruct dentry *dbgdir;\n};\n\nstruct vas_instance;\n\nstruct pnv_vas_window {\n\tstruct vas_window vas_win;\n\tstruct vas_instance *vinst;\n\tbool tx_win;\n\tbool nx_win;\n\tbool user_win;\n\tvoid *hvwc_map;\n\tvoid *uwc_map;\n\tvoid *paste_kaddr;\n\tchar *paste_addr_name;\n\tstruct pnv_vas_window *rxwin;\n\tatomic_t num_txwins;\n};\n\nstruct policy_file;\n\nstruct policy_data {\n\tstruct policydb *p;\n\tstruct policy_file *fp;\n};\n\nstruct policy_file {\n\tchar *data;\n\tsize_t len;\n};\n\nstruct policy_load_memory {\n\tsize_t len;\n\tvoid *data;\n};\n\nstruct role_datum;\n\nstruct user_datum;\n\nstruct type_datum;\n\nstruct role_allow;\n\nstruct policydb {\n\tint mls_enabled;\n\tstruct symtab symtab[8];\n\tchar **sym_val_to_name[8];\n\tstruct class_datum **class_val_to_struct;\n\tstruct role_datum **role_val_to_struct;\n\tstruct user_datum **user_val_to_struct;\n\tstruct type_datum **type_val_to_struct;\n\tstruct avtab te_avtab;\n\tstruct hashtab role_tr;\n\tstruct ebitmap filename_trans_ttypes;\n\tstruct hashtab filename_trans;\n\tu32 compat_filename_trans_count;\n\tstruct cond_bool_datum **bool_val_to_struct;\n\tstruct avtab te_cond_avtab;\n\tstruct cond_node *cond_list;\n\tu32 cond_list_len;\n\tstruct role_allow *role_allow;\n\tstruct ocontext *ocontexts[9];\n\tstruct genfs *genfs;\n\tstruct hashtab range_tr;\n\tstruct ebitmap *type_attr_map_array;\n\tstruct ebitmap policycaps;\n\tstruct ebitmap permissive_map;\n\tstruct ebitmap neveraudit_map;\n\tsize_t len;\n\tunsigned int policyvers;\n\tunsigned int reject_unknown: 1;\n\tunsigned int allow_unknown: 1;\n\tu16 process_class;\n\tu32 process_trans_perms;\n};\n\nstruct policydb_compat_info {\n\tunsigned int version;\n\tunsigned int sym_num;\n\tunsigned int ocon_num;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tunsigned int len;\n\tstruct pollfd entries[0];\n};\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[9];\n};\n\nstruct worker_pool;\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[16];\n\tbool plugged;\n\tint nr_active;\n\tstruct list_head inactive_works;\n\tstruct list_head pending_node;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct mayday_cursor;\n\tu64 stats[8];\n\tstruct kthread_work release_work;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct port_identity {\n\tstruct clock_identity clock_identity;\n\t__be16 port_number;\n};\n\nstruct posix_acl {\n\tunion {\n\t\tstruct {\n\t\t\trefcount_t a_refcount;\n\t\t\tunsigned int a_count;\n\t\t\tstruct callback_head a_rcu;\n\t\t};\n\t\tstruct posix_acl_hdr hdr;\n\t};\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct posix_clock;\n\nstruct posix_clock_context;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock_context *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock_context *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock_context *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock_context *);\n\tssize_t (*read)(struct posix_clock_context *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_context {\n\tstruct posix_clock *clk;\n\tstruct file *fp;\n\tvoid *private_clkdata;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct posix_msg_tree_node {\n\tstruct rb_node rb_node;\n\tstruct list_head msg_list;\n\tint priority;\n};\n\nstruct postprocess_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n\tstruct fsverity_info *vi;\n};\n\nstruct power_pmu {\n\tconst char *name;\n\tint n_counter;\n\tint max_alternatives;\n\tlong unsigned int add_fields;\n\tlong unsigned int test_adder;\n\tint (*compute_mmcr)(u64 *, int, unsigned int *, struct mmcr_regs *, struct perf_event **, u32);\n\tint (*get_constraint)(u64, long unsigned int *, long unsigned int *, u64);\n\tint (*get_alternatives)(u64, unsigned int, u64 *);\n\tvoid (*get_mem_data_src)(union perf_mem_data_src *, u32, struct pt_regs *);\n\tvoid (*get_mem_weight)(u64 *, u64);\n\tlong unsigned int group_constraint_mask;\n\tlong unsigned int group_constraint_val;\n\tu64 (*bhrb_filter_map)(u64);\n\tvoid (*config_bhrb)(u64);\n\tvoid (*disable_pmc)(unsigned int, struct mmcr_regs *);\n\tint (*limited_pmc_event)(u64);\n\tu32 flags;\n\tconst struct attribute_group **attr_groups;\n\tint n_generic;\n\tint *generic_events;\n\tu64 (*cache_events)[42];\n\tint n_blacklist_ev;\n\tint *blacklist_ev;\n\tint bhrb_nr;\n\tint capabilities;\n\tint (*check_attr_config)(struct perf_event *);\n};\n\nstruct powercap_attr {\n\tu32 handle;\n\tstruct kobj_attribute attr;\n};\n\nstruct powernv_pstate_info {\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int nominal;\n\tunsigned int nr_pstates;\n\tbool wof_enabled;\n};\n\nstruct powernv_smp_call_data {\n\tunsigned int freq;\n\tu8 pstate_id;\n\tu8 gpstate_id;\n};\n\nstruct powerpc_jit_data {\n\tstruct bpf_binary_header *hdr;\n\tstruct bpf_binary_header *fhdr;\n\tu32 *addrs;\n\tu8 *fimage;\n\tu32 proglen;\n\tstruct codegen_context ctx;\n};\n\nstruct powerpc_macro {\n\tconst char *name;\n\tunsigned int operands;\n\tppc_cpu_t flags;\n\tconst char *format;\n};\n\nstruct powerpc_opcode {\n\tconst char *name;\n\tlong unsigned int opcode;\n\tlong unsigned int mask;\n\tppc_cpu_t flags;\n\tppc_cpu_t deprecated;\n\tunsigned char operands[8];\n};\n\nstruct powerpc_operand {\n\tunsigned int bitm;\n\tint shift;\n\tlong unsigned int (*insert)(long unsigned int, long int, ppc_cpu_t, const char **);\n\tlong int (*extract)(long unsigned int, ppc_cpu_t, int *);\n\tlong unsigned int flags;\n};\n\nstruct ppc_cache_info {\n\tu32 size;\n\tu32 line_size;\n\tu32 block_size;\n\tu32 log_block_size;\n\tu32 blocks_per_page;\n\tu32 sets;\n\tu32 assoc;\n};\n\nstruct ppc64_caches {\n\tstruct ppc_cache_info l1d;\n\tstruct ppc_cache_info l1i;\n\tstruct ppc_cache_info l2;\n\tstruct ppc_cache_info l3;\n};\n\nstruct ppc64_stub_entry {\n\tu32 jump[7];\n\tu32 magic;\n\tfunc_desc_t funcdata;\n};\n\nstruct ppc64_tlb_batch {\n\tlong unsigned int index;\n\tstruct mm_struct *mm;\n\treal_pte_t pte[192];\n\tlong unsigned int vpn[192];\n\tunsigned int psize;\n\tint ssize;\n};\n\nstruct ppc_debug_info {\n\t__u32 version;\n\t__u32 num_instruction_bps;\n\t__u32 num_data_bps;\n\t__u32 num_condition_regs;\n\t__u32 data_bp_alignment;\n\t__u32 sizeof_condition;\n\t__u64 features;\n};\n\nstruct ppc_emulated_entry {\n\tconst char *name;\n\tatomic_t val;\n};\n\nstruct ppc_emulated {\n\tstruct ppc_emulated_entry altivec;\n\tstruct ppc_emulated_entry dcba;\n\tstruct ppc_emulated_entry dcbz;\n\tstruct ppc_emulated_entry fp_pair;\n\tstruct ppc_emulated_entry isel;\n\tstruct ppc_emulated_entry mcrxr;\n\tstruct ppc_emulated_entry mfpvr;\n\tstruct ppc_emulated_entry multiple;\n\tstruct ppc_emulated_entry popcntb;\n\tstruct ppc_emulated_entry spe;\n\tstruct ppc_emulated_entry string;\n\tstruct ppc_emulated_entry sync;\n\tstruct ppc_emulated_entry unaligned;\n\tstruct ppc_emulated_entry vsx;\n\tstruct ppc_emulated_entry mfdscr;\n\tstruct ppc_emulated_entry mtdscr;\n\tstruct ppc_emulated_entry lq_stq;\n\tstruct ppc_emulated_entry lxvw4x;\n\tstruct ppc_emulated_entry lxvh8x;\n\tstruct ppc_emulated_entry lxvd2x;\n\tstruct ppc_emulated_entry lxvb16x;\n};\n\nstruct ppc_hw_breakpoint {\n\t__u32 version;\n\t__u32 trigger_type;\n\t__u32 addr_mode;\n\t__u32 condition_mode;\n\t__u64 addr;\n\t__u64 addr2;\n\t__u64 condition_value;\n};\n\nstruct ppc_pci_io {\n\tu8 (*inb)(long unsigned int);\n\tu16 (*inw)(long unsigned int);\n\tu32 (*inl)(long unsigned int);\n\tvoid (*outb)(u8, long unsigned int);\n\tvoid (*outw)(u16, long unsigned int);\n\tvoid (*outl)(u32, long unsigned int);\n\tvoid (*insb)(long unsigned int, void *, long unsigned int);\n\tvoid (*insw)(long unsigned int, void *, long unsigned int);\n\tvoid (*insl)(long unsigned int, void *, long unsigned int);\n\tvoid (*outsb)(long unsigned int, const void *, long unsigned int);\n\tvoid (*outsw)(long unsigned int, const void *, long unsigned int);\n\tvoid (*outsl)(long unsigned int, const void *, long unsigned int);\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct pps_bind_args {\n\tint tsformat;\n\tint edge;\n\tint consumer;\n};\n\nstruct pps_device;\n\nstruct pps_source_info {\n\tchar name[32];\n\tchar path[32];\n\tint mode;\n\tvoid (*echo)(struct pps_device *, int, void *);\n\tstruct module *owner;\n\tstruct device *dev;\n};\n\nstruct pps_ktime {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kparams {\n\tint api_version;\n\tint mode;\n\tstruct pps_ktime assert_off_tu;\n\tstruct pps_ktime clear_off_tu;\n};\n\nstruct pps_device {\n\tstruct pps_source_info info;\n\tstruct pps_kparams params;\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tunsigned int last_ev;\n\tunsigned int last_fetched_ev;\n\twait_queue_head_t queue;\n\tunsigned int id;\n\tconst void *lookup_cookie;\n\tstruct device dev;\n\tstruct fasync_struct *async_queue;\n\tspinlock_t lock;\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct pps_kinfo {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n};\n\nstruct pps_fdata {\n\tstruct pps_kinfo info;\n\tstruct pps_ktime timeout;\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_cont_work_struct {\n\tbool comma;\n\twork_func_t func;\n\tlong int ctr;\n};\n\nstruct pr_held_reservation {\n\tu64 key;\n\tu32 generation;\n\tenum pr_type type;\n};\n\nstruct pr_keys {\n\tu32 generation;\n\tu32 num_keys;\n\tu64 keys[0];\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n\tint (*pr_read_keys)(struct block_device *, struct pr_keys *);\n\tint (*pr_read_reservation)(struct block_device *, struct pr_held_reservation *);\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_read_keys {\n\t__u32 generation;\n\t__u32 num_keys;\n\t__u64 keys_ptr;\n};\n\nstruct pr_read_reservation {\n\t__u64 key;\n\t__u32 generation;\n\t__u32 type;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct prb_data_blk_lpos {\n\tlong unsigned int begin;\n\tlong unsigned int next;\n};\n\nstruct prb_data_block {\n\tlong unsigned int id;\n\tchar data[0];\n};\n\nstruct prb_data_ring {\n\tunsigned int size_bits;\n\tchar *data;\n\tatomic_long_t head_lpos;\n\tatomic_long_t tail_lpos;\n};\n\nstruct prb_desc {\n\tatomic_long_t state_var;\n\tstruct prb_data_blk_lpos text_blk_lpos;\n};\n\nstruct printk_info;\n\nstruct prb_desc_ring {\n\tunsigned int count_bits;\n\tstruct prb_desc *descs;\n\tstruct printk_info *infos;\n\tatomic_long_t head_id;\n\tatomic_long_t tail_id;\n\tatomic_long_t last_finalized_seq;\n};\n\nstruct printk_ringbuffer;\n\nstruct prb_reserved_entry {\n\tstruct printk_ringbuffer *rb;\n\tlong unsigned int irqflags;\n\tlong unsigned int id;\n\tunsigned int text_space;\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n};\n\nstruct preempt_ops {\n\tvoid (*sched_in)(struct preempt_notifier *, int);\n\tvoid (*sched_out)(struct preempt_notifier *, struct task_struct *);\n};\n\nstruct prefix_cacheinfo {\n\t__u32 preferred_time;\n\t__u32 valid_time;\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\tunion {\n\t\t__u8 flags;\n\t\tstruct {\n\t\t\t__u8 reserved: 4;\n\t\t\t__u8 preferpd: 1;\n\t\t\t__u8 routeraddr: 1;\n\t\t\t__u8 autoconf: 1;\n\t\t\t__u8 onlink: 1;\n\t\t};\n\t};\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct prefixmsg {\n\tunsigned char prefix_family;\n\tunsigned char prefix_pad1;\n\tshort unsigned int prefix_pad2;\n\tint prefix_ifindex;\n\tunsigned char prefix_type;\n\tunsigned char prefix_len;\n\tunsigned char prefix_flags;\n\tunsigned char prefix_pad3;\n};\n\nstruct prepend_buffer {\n\tchar *buf;\n\tint len;\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct printf_spec {\n\tunsigned char flags;\n\tunsigned char base;\n\tshort int precision;\n\tint field_width;\n};\n\nstruct printk_info {\n\tu64 seq;\n\tu64 ts_nsec;\n\tu16 text_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n\tu32 caller_id;\n\tstruct dev_printk_info dev_info;\n};\n\nstruct printk_message {\n\tstruct printk_buffers *pbufs;\n\tunsigned int outbuf_len;\n\tu64 seq;\n\tlong unsigned int dropped;\n};\n\nstruct printk_record {\n\tstruct printk_info *info;\n\tchar *text_buf;\n\tunsigned int text_buf_size;\n};\n\nstruct printk_ringbuffer {\n\tstruct prb_desc_ring desc_ring;\n\tstruct prb_data_ring text_data_ring;\n\tatomic_long_t fail;\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct probe_entry_arg {\n\tstruct fetch_insn *code;\n\tunsigned int size;\n};\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_ops;\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n\tstruct callback_head rcu;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tconst struct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n};\n\nstruct proc_nfs_info {\n\tint flag;\n\tconst char *str;\n\tconst char *nostr;\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct proc_timens_offset {\n\tint clockid;\n\tstruct timespec64 val;\n};\n\nstruct proc_xfs_info {\n\tuint64_t flag;\n\tchar *str;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\nstruct procmap_query {\n\t__u64 size;\n\t__u64 query_flags;\n\t__u64 query_addr;\n\t__u64 vma_start;\n\t__u64 vma_end;\n\t__u64 vma_flags;\n\t__u64 vma_page_size;\n\t__u64 vma_offset;\n\t__u64 inode;\n\t__u32 dev_major;\n\t__u32 dev_minor;\n\t__u32 vma_name_size;\n\t__u32 build_id_size;\n\t__u64 vma_name_addr;\n\t__u64 build_id_addr;\n};\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nstruct prog_test_member1 {\n\tint a;\n};\n\nstruct prog_test_member {\n\tstruct prog_test_member1 m;\n\tint c;\n};\n\nstruct prog_test_ref_kfunc {\n\tint a;\n\tint b;\n\tstruct prog_test_member memb;\n\tstruct prog_test_ref_kfunc *next;\n\trefcount_t cnt;\n};\n\nstruct prom_args {\n\t__be32 service;\n\t__be32 nargs;\n\t__be32 nret;\n\t__be32 args[10];\n};\n\nstruct prom_t {\n\tihandle root;\n\tphandle chosen;\n\tint cpu;\n\tihandle stdout;\n\tihandle mmumap;\n\tihandle memory;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n\tlong unsigned int _flags;\n\tstruct bin_attribute attr;\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[1];\n\t\t} value;\n\t};\n};\n\nstruct prot_inuse {\n\tint all;\n\tint val[64];\n};\n\nstruct proto_accept_arg;\n\nstruct sk_psock;\n\nstruct timewait_sock_ops;\n\nstruct raw_hashinfo;\n\nstruct smc_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, struct proto_accept_arg *);\n\tint (*ioctl)(struct sock *, int, int *);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int *);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*bind)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr_unsized *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tbool (*bpf_bypass_getsockopt)(int, int);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tvoid (*put_port)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*sock_is_readable)(struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tint *per_cpu_fw_alloc;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tunsigned int freeptr_offset;\n\tunsigned int ipv6_pinfo_offset;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct proto_accept_arg {\n\tint flags;\n\tint err;\n\tint is_empty;\n\tbool kern;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\ntypedef int (*skb_read_actor_t)(struct sock *, struct sk_buff *);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr_unsized *, int);\n\tint (*connect)(struct socket *, struct sockaddr_unsized *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, struct proto_accept_arg *);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*splice_eof)(struct socket *);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*read_skb)(struct sock *, skb_read_actor_t);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nstruct prtb_entry {\n\t__be64 prtb0;\n\t__be64 prtb1;\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct psample_group {\n\tstruct list_head list;\n\tstruct net *net;\n\tu32 group_num;\n\tu32 refcount;\n\tu32 seq;\n\tstruct callback_head rcu;\n};\n\nstruct psched_pktrate {\n\tu64 rate_pkts_ps;\n\tu32 mult;\n\tu8 shift;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu16 mpu;\n\tu8 linklayer;\n\tu8 shift;\n};\n\nstruct pse_control_config {\n\tenum ethtool_podl_pse_admin_state podl_admin_control;\n\tenum ethtool_c33_pse_admin_state c33_admin_control;\n};\n\nstruct pse_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pse_control_status status;\n};\n\nstruct pseries_errorlog {\n\t__be16 id;\n\t__be16 length;\n\tu8 version;\n\tu8 subtype;\n\t__be16 creator_component;\n\tu8 data[0];\n};\n\nstruct pseries_hp_errorlog {\n\tu8 resource;\n\tu8 action;\n\tu8 id_type;\n\tu8 reserved;\n\tunion {\n\t\t__be32 drc_index;\n\t\t__be32 drc_count;\n\t\tstruct {\n\t\t\t__be32 count;\n\t\t\t__be32 index;\n\t\t} ic;\n\t\tchar drc_name[1];\n\t} _drc_u;\n};\n\nstruct pseries_hp_work {\n\tstruct work_struct work;\n\tstruct pseries_hp_errorlog *errlog;\n};\n\nstruct pseries_io_event {\n\tuint8_t event_type;\n\tuint8_t rpc_data_len;\n\tuint8_t scope;\n\tuint8_t event_subtype;\n\tuint32_t drc_index;\n\tuint8_t rpc_data[216];\n};\n\nstruct pseries_mc_errorlog {\n\t__be32 fru_id;\n\t__be32 proc_id;\n\tu8 error_type;\n\tu8 sub_err_type;\n\tu8 reserved_1[6];\n\t__be64 effective_address;\n\t__be64 logical_address;\n};\n\nstruct pseries_msi_device {\n\tunsigned int msi_quota;\n\tunsigned int msi_used;\n};\n\nstruct pseries_suspend_info {\n\tatomic_t counter;\n\tbool done;\n};\n\nstruct pseries_vas_window {\n\tstruct vas_window vas_win;\n\tu64 win_addr;\n\tu8 win_type;\n\tu32 complete_irq;\n\tu32 fault_irq;\n\tu64 domain[6];\n\tu64 util;\n\tu32 pid;\n\tstruct list_head win_list;\n\tu64 flags;\n\tchar *name;\n\tint fault_virq;\n\tatomic_t pending_faults;\n};\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct export_operations *eops;\n\tconst struct xattr_handler * const *xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n\tunsigned int s_d_flags;\n};\n\nstruct psi_group_cpu;\n\nstruct psi_group {\n\tstruct psi_group *parent;\n\tbool enabled;\n\tstruct mutex avgs_lock;\n\tstruct psi_group_cpu *pcpu;\n\tu64 avg_total[6];\n\tu64 avg_last_update;\n\tu64 avg_next_update;\n\tstruct delayed_work avgs_work;\n\tstruct list_head avg_triggers;\n\tu32 avg_nr_triggers[6];\n\tu64 total[12];\n\tlong unsigned int avg[18];\n\tstruct task_struct *rtpoll_task;\n\tstruct timer_list rtpoll_timer;\n\twait_queue_head_t rtpoll_wait;\n\tatomic_t rtpoll_wakeup;\n\tatomic_t rtpoll_scheduled;\n\tstruct mutex rtpoll_trigger_lock;\n\tstruct list_head rtpoll_triggers;\n\tu32 rtpoll_nr_triggers[6];\n\tu32 rtpoll_states;\n\tu64 rtpoll_min_period;\n\tu64 rtpoll_total[6];\n\tu64 rtpoll_next_update;\n\tu64 rtpoll_until;\n};\n\nstruct psi_group_cpu {\n\tunsigned int tasks[4];\n\tu32 state_mask;\n\tu32 times[7];\n\tu64 state_start;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 times_prev[14];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct psi_window {\n\tu64 size;\n\tu64 start_time;\n\tu64 start_value;\n\tu64 prev_growth;\n};\n\nstruct psi_trigger {\n\tenum psi_states state;\n\tu64 threshold;\n\tstruct list_head node;\n\tstruct psi_group *group;\n\twait_queue_head_t event_wait;\n\tstruct kernfs_open_file *of;\n\tint event;\n\tstruct psi_window win;\n\tu64 last_event_time;\n\tbool pending_event;\n\tenum psi_aggregators aggregator;\n};\n\nstruct psmouse_protocol;\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct psr_attr {\n\tu32 handle;\n\tstruct kobj_attribute attr;\n};\n\nstruct pstate_idx_revmap_data {\n\tu8 pstate_id;\n\tunsigned int cpufreq_table_idx;\n\tstruct hlist_node hentry;\n};\n\nstruct pstore_context {\n\tunsigned int kmsg_bytes;\n};\n\nstruct pstore_ftrace_record {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tu64 ts;\n};\n\nstruct pstore_ftrace_seq_data {\n\tconst void *ptr;\n\tsize_t off;\n\tsize_t size;\n};\n\nstruct pstore_record;\n\nstruct pstore_info {\n\tstruct module *owner;\n\tconst char *name;\n\traw_spinlock_t buf_lock;\n\tchar *buf;\n\tsize_t bufsize;\n\tstruct mutex read_mutex;\n\tint flags;\n\tint max_reason;\n\tvoid *data;\n\tint (*open)(struct pstore_info *);\n\tint (*close)(struct pstore_info *);\n\tssize_t (*read)(struct pstore_record *);\n\tint (*write)(struct pstore_record *);\n\tint (*write_user)(struct pstore_record *, const char *);\n\tint (*erase)(struct pstore_record *);\n};\n\nstruct pstore_private {\n\tstruct list_head list;\n\tstruct dentry *dentry;\n\tstruct pstore_record *record;\n\tsize_t total_size;\n};\n\nstruct pstore_record {\n\tstruct pstore_info *psi;\n\tenum pstore_type_id type;\n\tu64 id;\n\tstruct timespec64 time;\n\tchar *buf;\n\tssize_t size;\n\tssize_t ecc_notice_size;\n\tvoid *priv;\n\tint count;\n\tenum kmsg_dump_reason reason;\n\tunsigned int part;\n\tbool compressed;\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\nstruct ptdesc {\n\tmemdesc_flags_t pt_flags;\n\tunion {\n\t\tstruct callback_head pt_rcu_head;\n\t\tstruct list_head pt_list;\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t};\n\t};\n\tlong unsigned int __page_mapping;\n\tunion {\n\t\tlong unsigned int pt_index;\n\t\tstruct mm_struct *pt_mm;\n\t\tatomic_t pt_frag_refcount;\n\t};\n\tunion {\n\t\tlong unsigned int _pt_pad_2;\n\t\tspinlock_t ptl;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int pt_memcg_data;\n};\n\nstruct ptdump_pg_level {\n\tconst struct flag_info *flag;\n\tchar name[4];\n\tsize_t num;\n\tu64 mask;\n};\n\nstruct ptdump_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct ptp_clock {\n\tstruct posix_clock clock;\n\tstruct device dev;\n\tstruct ptp_clock_info *info;\n\tdev_t devid;\n\tint index;\n\tstruct pps_device *pps_source;\n\tlong int dialed_frequency;\n\tstruct list_head tsevqs;\n\tspinlock_t tsevqs_lock;\n\tstruct mutex pincfg_mux;\n\twait_queue_head_t tsev_wq;\n\tint defunct;\n\tstruct device_attribute *pin_dev_attr;\n\tstruct attribute **pin_attr;\n\tstruct attribute_group pin_attr_group;\n\tconst struct attribute_group *pin_attr_groups[2];\n\tstruct kthread_worker *kworker;\n\tstruct kthread_delayed_work aux_work;\n\tunsigned int max_vclocks;\n\tunsigned int n_vclocks;\n\tint *vclock_index;\n\tstruct mutex n_vclocks_mux;\n\tbool is_virtual_clock;\n\tbool has_cycles;\n\tstruct dentry *debugfs_root;\n};\n\nstruct ptp_clock_caps {\n\tint max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint pps;\n\tint n_pins;\n\tint cross_timestamping;\n\tint adjust_phase;\n\tint max_phase_adj;\n\tint rsv[11];\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\ts64 offset;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_perout_request {\n\tunion {\n\t\tstruct ptp_clock_time start;\n\t\tstruct ptp_clock_time phase;\n\t};\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunion {\n\t\tstruct ptp_clock_time on;\n\t\tunsigned int rsv[4];\n\t};\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_extts_event {\n\tstruct ptp_clock_time t;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_header {\n\tu8 tsmt;\n\tu8 ver;\n\t__be16 message_length;\n\tu8 domain_number;\n\tu8 reserved1;\n\tu8 flag_field[2];\n\t__be64 correction;\n\t__be32 reserved2;\n\tstruct port_identity source_port_identity;\n\t__be16 sequence_id;\n\tu8 control;\n\tu8 log_message_interval;\n} __attribute__((packed));\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct ptp_sys_offset {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[51];\n};\n\nstruct ptp_sys_offset_extended {\n\tunsigned int n_samples;\n\t__kernel_clockid_t clockid;\n\tunsigned int rsv[2];\n\tstruct ptp_clock_time ts[75];\n};\n\nstruct ptp_sys_offset_precise {\n\tstruct ptp_clock_time device;\n\tstruct ptp_clock_time sys_realtime;\n\tstruct ptp_clock_time sys_monoraw;\n\tunsigned int rsv[4];\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n\tclockid_t clockid;\n};\n\nstruct ptp_vclock {\n\tstruct ptp_clock *pclock;\n\tstruct ptp_clock_info info;\n\tstruct ptp_clock *clock;\n\tstruct hlist_node vclock_hash_node;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct mutex lock;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_relation {\n\tstruct task_struct *tracer;\n\tstruct task_struct *tracee;\n\tbool invalid;\n\tstruct list_head node;\n\tstruct callback_head rcu;\n};\n\nstruct ptrace_rseq_configuration {\n\t__u64 rseq_abi_pointer;\n\t__u32 rseq_abi_size;\n\t__u32 signature;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u8 reserved;\n\t__u16 flags;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t\t__u32 reserved2;\n\t\t} seccomp;\n\t};\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct inode *ptmx_inode;\n};\n\nstruct ptype_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n};\n\nstruct pubkey_hdr {\n\tuint8_t version;\n\tuint32_t timestamp;\n\tuint8_t algo;\n\tuint8_t nmpi;\n\tchar mpi[0];\n} __attribute__((packed));\n\nstruct public_key {\n\tvoid *key;\n\tu32 keylen;\n\tenum OID algo;\n\tvoid *params;\n\tu32 paramlen;\n\tbool key_is_private;\n\tconst char *id_type;\n\tconst char *pkey_algo;\n\tlong unsigned int key_eflags;\n};\n\nstruct public_key_signature {\n\tstruct asymmetric_key_id *auth_ids[3];\n\tu8 *s;\n\tu8 *m;\n\tu32 s_size;\n\tu32 m_size;\n\tbool m_free;\n\tbool algo_takes_data;\n\tconst char *pkey_algo;\n\tconst char *hash_algo;\n\tconst char *encoding;\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qdisc_dump_args {\n\tstruct qdisc_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct qdisc_rate_table {\n\tstruct tc_ratespec rate;\n\tu32 data[256];\n\tstruct qdisc_rate_table *next;\n\tint refcnt;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct qdisc_watchdog {\n\tstruct hrtimer timer;\n\tstruct Qdisc *qdisc;\n};\n\nstruct qnode {\n\tstruct qnode *next;\n\tstruct qspinlock *lock;\n\tint cpu;\n\tu8 sleepy;\n\tu8 locked;\n};\n\nstruct qnodes {\n\tint count;\n\tstruct qnode nodes[4];\n};\n\nstruct queue_limits {\n\tblk_features_t features;\n\tblk_flags_t flags;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_user_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int max_fast_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_user_discard_sectors;\n\tunsigned int max_secure_erase_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_wzeroes_unmap_sectors;\n\tunsigned int max_hw_wzeroes_unmap_sectors;\n\tunsigned int max_user_wzeroes_unmap_sectors;\n\tunsigned int max_hw_zone_append_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tunsigned int zone_write_granularity;\n\tunsigned int atomic_write_hw_max;\n\tunsigned int atomic_write_max_sectors;\n\tunsigned int atomic_write_hw_boundary;\n\tunsigned int atomic_write_boundary_sectors;\n\tunsigned int atomic_write_hw_unit_min;\n\tunsigned int atomic_write_unit_min;\n\tunsigned int atomic_write_hw_unit_max;\n\tunsigned int atomic_write_unit_max;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tshort unsigned int max_write_streams;\n\tunsigned int write_stream_granularity;\n\tunsigned int max_open_zones;\n\tunsigned int max_active_zones;\n\tunsigned int dma_alignment;\n\tunsigned int dma_pad_mask;\n\tstruct blk_integrity integrity;\n};\n\nstruct queue_pages {\n\tstruct list_head *pagelist;\n\tlong unsigned int flags;\n\tnodemask_t *nmask;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct vm_area_struct *first;\n\tstruct folio *large;\n\tlong int nr_failed;\n};\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gendisk *, char *);\n\tssize_t (*show_limit)(struct gendisk *, char *);\n\tssize_t (*store)(struct gendisk *, const char *, size_t);\n\tint (*store_limit)(struct gendisk *, const char *, size_t, struct queue_limits *);\n};\n\nstruct quirk_entry {\n\tu16 vid;\n\tu16 pid;\n\tu32 flags;\n};\n\nstruct quirks_list_struct {\n\tstruct hid_device_id hid_bl_item;\n\tstruct list_head node;\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct strip_zone;\n\nstruct r0conf {\n\tstruct strip_zone *strip_zone;\n\tstruct md_rdev **devlist;\n\tint nr_strip_zones;\n\tenum r0layout layout;\n};\n\nstruct r1bio {\n\tatomic_t remaining;\n\tatomic_t behind_remaining;\n\tsector_t sector;\n\tint sectors;\n\tlong unsigned int state;\n\tstruct mddev *mddev;\n\tstruct bio *master_bio;\n\tint read_disk;\n\tstruct list_head retry_list;\n\tstruct bio *behind_master_bio;\n\tstruct bio *bios[0];\n};\n\nstruct raid1_info;\n\nstruct r1conf {\n\tstruct mddev *mddev;\n\tstruct raid1_info *mirrors;\n\tint raid_disks;\n\tint nonrot_disks;\n\tspinlock_t device_lock;\n\tstruct list_head retry_list;\n\tstruct list_head bio_end_io_list;\n\tstruct bio_list pending_bio_list;\n\twait_queue_head_t wait_barrier;\n\tspinlock_t resync_lock;\n\tatomic_t nr_sync_pending;\n\tatomic_t *nr_pending;\n\tatomic_t *nr_waiting;\n\tatomic_t *nr_queued;\n\tatomic_t *barrier;\n\tint array_frozen;\n\tint fullsync;\n\tmempool_t *r1bio_pool;\n\tmempool_t r1buf_pool;\n\tstruct bio_set bio_split;\n\tstruct page *tmppage;\n\tstruct md_thread *thread;\n\tsector_t cluster_sync_low;\n\tsector_t cluster_sync_high;\n};\n\nstruct ra_msg {\n\tstruct icmp6hdr icmph;\n\t__be32 reachable_time;\n\t__be32 retrans_timer;\n};\n\nstruct radeonfb_info;\n\nstruct radeon_i2c_chan {\n\tstruct radeonfb_info *rinfo;\n\tu32 ddc_reg;\n\tstruct i2c_adapter adapter;\n\tstruct i2c_algo_bit_data algo;\n};\n\nstruct radeon_regs {\n\tu32 ovr_clr;\n\tu32 ovr_wid_left_right;\n\tu32 ovr_wid_top_bottom;\n\tu32 ov0_scale_cntl;\n\tu32 mpp_tb_config;\n\tu32 mpp_gp_config;\n\tu32 subpic_cntl;\n\tu32 viph_control;\n\tu32 i2c_cntl_1;\n\tu32 gen_int_cntl;\n\tu32 cap0_trig_cntl;\n\tu32 cap1_trig_cntl;\n\tu32 bus_cntl;\n\tu32 surface_cntl;\n\tu32 bios_5_scratch;\n\tu32 dp_datatype;\n\tu32 rbbm_soft_reset;\n\tu32 clock_cntl_index;\n\tu32 amcgpio_en_reg;\n\tu32 amcgpio_mask;\n\tu32 surf_lower_bound[8];\n\tu32 surf_upper_bound[8];\n\tu32 surf_info[8];\n\tu32 crtc_gen_cntl;\n\tu32 crtc_ext_cntl;\n\tu32 dac_cntl;\n\tu32 crtc_h_total_disp;\n\tu32 crtc_h_sync_strt_wid;\n\tu32 crtc_v_total_disp;\n\tu32 crtc_v_sync_strt_wid;\n\tu32 crtc_offset;\n\tu32 crtc_offset_cntl;\n\tu32 crtc_pitch;\n\tu32 disp_merge_cntl;\n\tu32 grph_buffer_cntl;\n\tu32 crtc_more_cntl;\n\tu32 crtc2_gen_cntl;\n\tu32 dac2_cntl;\n\tu32 disp_output_cntl;\n\tu32 disp_hw_debug;\n\tu32 disp2_merge_cntl;\n\tu32 grph2_buffer_cntl;\n\tu32 crtc2_h_total_disp;\n\tu32 crtc2_h_sync_strt_wid;\n\tu32 crtc2_v_total_disp;\n\tu32 crtc2_v_sync_strt_wid;\n\tu32 crtc2_offset;\n\tu32 crtc2_offset_cntl;\n\tu32 crtc2_pitch;\n\tu32 fp_crtc_h_total_disp;\n\tu32 fp_crtc_v_total_disp;\n\tu32 fp_gen_cntl;\n\tu32 fp2_gen_cntl;\n\tu32 fp_h_sync_strt_wid;\n\tu32 fp2_h_sync_strt_wid;\n\tu32 fp_horz_stretch;\n\tu32 fp_panel_cntl;\n\tu32 fp_v_sync_strt_wid;\n\tu32 fp2_v_sync_strt_wid;\n\tu32 fp_vert_stretch;\n\tu32 lvds_gen_cntl;\n\tu32 lvds_pll_cntl;\n\tu32 tmds_crc;\n\tu32 tmds_transmitter_cntl;\n\tu32 dot_clock_freq;\n\tint feedback_div;\n\tint post_div;\n\tu32 ppll_div_3;\n\tu32 ppll_ref_div;\n\tu32 vclk_ecp_cntl;\n\tu32 clk_cntl_index;\n\tu32 dot_clock_freq_2;\n\tint feedback_div_2;\n\tint post_div_2;\n\tu32 p2pll_ref_div;\n\tu32 p2pll_div_0;\n\tu32 htotal_cntl2;\n\tint palette_valid;\n};\n\ntypedef void (*reinit_function_ptr)(struct radeonfb_info *);\n\nstruct radeonfb_info {\n\tstruct fb_info *info;\n\tstruct radeon_regs state;\n\tstruct radeon_regs init_state;\n\tchar name[50];\n\tlong unsigned int mmio_base_phys;\n\tlong unsigned int fb_base_phys;\n\tvoid *mmio_base;\n\tvoid *fb_base;\n\tlong unsigned int fb_local_base;\n\tstruct pci_dev *pdev;\n\tstruct device_node *of_node;\n\tvoid *bios_seg;\n\tint fp_bios_start;\n\tu32 pseudo_palette[16];\n\tstruct {\n\t\tu8 red;\n\t\tu8 green;\n\t\tu8 blue;\n\t\tu8 pad;\n\t} palette[256];\n\tint chipset;\n\tu8 family;\n\tu8 rev;\n\tunsigned int errata;\n\tlong unsigned int video_ram;\n\tlong unsigned int mapped_vram;\n\tint vram_width;\n\tint vram_ddr;\n\tint pitch;\n\tint bpp;\n\tint depth;\n\tint has_CRTC2;\n\tint is_mobility;\n\tint is_IGP;\n\tint reversed_DAC;\n\tint reversed_TMDS;\n\tstruct panel_info panel_info;\n\tint mon1_type;\n\tu8 *mon1_EDID;\n\tstruct fb_videomode *mon1_modedb;\n\tint mon1_dbsize;\n\tint mon2_type;\n\tu8 *mon2_EDID;\n\tu32 dp_gui_master_cntl;\n\tstruct pll_info pll;\n\tint wc_cookie;\n\tu32 save_regs[100];\n\tint asleep;\n\tint lock_blank;\n\tint dynclk;\n\tint no_schedule;\n\tenum radeon_pm_mode pm_mode;\n\treinit_function_ptr reinit_func;\n\tspinlock_t reg_lock;\n\tstruct timer_list lvds_timer;\n\tu32 pending_lvds_gen_cntl;\n\tstruct radeon_i2c_chan i2c[4];\n};\n\nstruct xa_node;\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nstruct raid1_info {\n\tstruct md_rdev *rdev;\n\tsector_t head_position;\n\tsector_t next_seq_sect;\n\tsector_t seq_start;\n};\n\nstruct raid1_plug_cb {\n\tstruct blk_plug_cb cb;\n\tstruct bio_list pending;\n\tunsigned int count;\n};\n\nstruct ramdax_dimm {\n\tstruct nvdimm *nvdimm;\n\tvoid *label_area;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nstruct range_node {\n\tstruct rb_node rn_rbnode;\n\tstruct rb_node rb_range_size;\n\tu32 rn_start;\n\tu32 rn_last;\n\tu32 __rn_subtree_last;\n};\n\nstruct range_trans {\n\tu32 source_type;\n\tu32 target_type;\n\tu32 target_class;\n};\n\nstruct rank_info {\n\tint chan_idx;\n\tstruct csrow_info *csrow;\n\tstruct dimm_info *dimm;\n\tu32 ce_count;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\tu32 prior_delivered_ce;\n\ts32 delivered;\n\ts32 delivered_ce;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tu32 last_end_seq;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n};\n\nstruct raw6_frag_vec {\n\tstruct msghdr *msg;\n\tint hlen;\n\tchar c[4];\n};\n\nstruct raw6_sock {\n\tstruct inet_sock inet;\n\t__u32 checksum;\n\t__u32 offset;\n\tstruct icmp6_filter filter;\n\t__u32 ip6mr_table;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct raw_hashinfo {\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct hlist_head ht[256];\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct rb0_cbdata {\n\tint drive;\n\tstruct completion complete;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tu64 before;\n\tu64 after;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tatomic_t seq;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct rb_list {\n\tstruct rb_root root;\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct rb_time_struct {\n\tlocal64_t time;\n};\n\ntypedef struct rb_time_struct rb_time_t;\n\nstruct rb_wait_data {\n\tstruct rb_irq_work *irq_work;\n\tint seq;\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nunion xfs_btree_ptr {\n\t__be32 s;\n\t__be64 l;\n};\n\nstruct xfs_buftarg;\n\nstruct xfbtree {\n\tstruct xfs_buftarg *target;\n\txfbno_t highest_bno;\n\tlong long unsigned int owner;\n\tunion xfs_btree_ptr root;\n\tunsigned int nlevels;\n\tunsigned int maxrecs[2];\n\tunsigned int minrecs[2];\n};\n\nstruct xfs_mount;\n\nstruct rcbag {\n\tstruct xfs_mount *mp;\n\tstruct xfbtree xfbtree;\n\tuint64_t nr_items;\n};\n\nstruct rcbag_key {\n\tuint32_t rbg_startblock;\n\tuint32_t rbg_blockcount;\n};\n\nstruct rcbag_rec {\n\tuint32_t rbg_startblock;\n\tuint32_t rbg_blockcount;\n\tuint64_t rbg_refcount;\n};\n\nstruct rchan_callbacks;\n\nstruct rchan_buf;\n\nstruct rchan {\n\tu32 version;\n\tsize_t subbuf_size;\n\tsize_t n_subbufs;\n\tsize_t alloc_size;\n\tconst struct rchan_callbacks *cb;\n\tstruct kref kref;\n\tvoid *private_data;\n\tstruct rchan_buf **buf;\n\tint is_global;\n\tstruct list_head list;\n\tstruct dentry *parent;\n\tint has_base_filename;\n\tchar base_filename[255];\n};\n\nstruct rchan_buf_stats {\n\tunsigned int full_count;\n\tunsigned int big_count;\n};\n\nstruct rchan_buf {\n\tvoid *start;\n\tvoid *data;\n\tsize_t offset;\n\tsize_t subbufs_produced;\n\tsize_t subbufs_consumed;\n\tstruct rchan *chan;\n\twait_queue_head_t read_wait;\n\tstruct irq_work wakeup_work;\n\tstruct dentry *dentry;\n\tstruct kref kref;\n\tstruct rchan_buf_stats stats;\n\tstruct page **page_array;\n\tunsigned int page_count;\n\tunsigned int finalized;\n\tsize_t *padding;\n\tsize_t bytes_consumed;\n\tsize_t early_bytes;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rchan_callbacks {\n\tint (*subbuf_start)(struct rchan_buf *, void *, void *);\n\tstruct dentry * (*create_buf_file)(const char *, struct dentry *, umode_t, struct rchan_buf *, int *);\n\tint (*remove_buf_file)(struct dentry *);\n};\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tatomic_long_t len;\n\tlong int seglen[4];\n\tu8 flags;\n};\n\nstruct rcu_snap_record {\n\tlong unsigned int gp_seq;\n\tu64 cputime_irq;\n\tu64 cputime_softirq;\n\tu64 cputime_system;\n\tu64 nr_hardirqs;\n\tunsigned int nr_softirqs;\n\tlong long unsigned int nr_csw;\n\tlong unsigned int jiffies;\n};\n\nstruct rcu_node;\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tunsigned int gpwrap_count;\n\tbool cpu_started;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tint defer_qs_pending;\n\tstruct work_struct strict_work;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_cbs_invoked;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint watching_snap;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tlong unsigned int barrier_seq_snap;\n\tstruct callback_head barrier_head;\n\tint exp_watching_snap;\n\tstruct swait_queue_head nocb_cb_wq;\n\tstruct swait_queue_head nocb_state_wq;\n\tstruct task_struct *nocb_gp_kthread;\n\traw_spinlock_t nocb_lock;\n\tint nocb_defer_wakeup;\n\tstruct timer_list nocb_timer;\n\tlong unsigned int nocb_gp_adv_time;\n\tstruct mutex nocb_gp_kthread_mutex;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t nocb_bypass_lock;\n\tstruct rcu_cblist nocb_bypass;\n\tlong unsigned int nocb_bypass_first;\n\tlong unsigned int nocb_nobypass_last;\n\tint nocb_nobypass_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t nocb_gp_lock;\n\tu8 nocb_gp_sleep;\n\tu8 nocb_gp_bypass;\n\tu8 nocb_gp_gp;\n\tlong unsigned int nocb_gp_seq;\n\tlong unsigned int nocb_gp_loops;\n\tstruct swait_queue_head nocb_gp_wq;\n\tbool nocb_cb_sleep;\n\tstruct task_struct *nocb_cb_kthread;\n\tstruct list_head nocb_head_rdp;\n\tstruct list_head nocb_entry_rdp;\n\tstruct rcu_data *nocb_toggling_rdp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rcu_data *nocb_gp_rdp;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tlong unsigned int rcuc_activity;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_state;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_state;\n\tlong unsigned int last_fqs_resched;\n\tlong unsigned int last_sched_clock;\n\tstruct rcu_snap_record snap_record;\n\tlong int lazy_len;\n\tint cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct kthread_work rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tstruct kthread_worker *exp_kworker;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct mutex kthread_mutex;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong unsigned int n_boosts;\n\tstruct swait_queue_head nocb_gp_wq[2];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t fqslock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\traw_spinlock_t exp_poll_lock;\n\tlong unsigned int exp_seq_poll_rq;\n\tstruct work_struct exp_poll_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sr_wait_node {\n\tatomic_t inuse;\n\tstruct llist_node node;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[131];\n\tstruct rcu_node *level[4];\n\tint ncpus;\n\tint n_online_cpus;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_max;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tlong unsigned int gp_seq_polled;\n\tlong unsigned int gp_seq_polled_snap;\n\tlong unsigned int gp_seq_polled_exp_snap;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\traw_spinlock_t barrier_lock;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tint nr_fqs_jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tconst char *name;\n\tchar abbr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tarch_spinlock_t ofl_lock;\n\tstruct llist_head srs_next;\n\tstruct llist_node *srs_wait_tail;\n\tstruct llist_node *srs_done_tail;\n\tstruct sr_wait_node srs_wait_nodes[5];\n\tstruct work_struct srs_cleanup_work;\n\tatomic_t srs_cleanups_pending;\n\tstruct mutex nocb_mutex;\n\tint nocb_is_setup;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n\tstruct rcu_gp_oldstate oldstate;\n};\n\nstruct rcu_tasks;\n\ntypedef void (*rcu_tasks_gp_func_t)(struct rcu_tasks *);\n\ntypedef void (*pregp_func_t)(struct list_head *);\n\ntypedef void (*pertask_func_t)(struct task_struct *, struct list_head *);\n\ntypedef void (*postscan_func_t)(struct list_head *);\n\ntypedef void (*holdouts_func_t)(struct list_head *, bool, bool *);\n\ntypedef void (*postgp_func_t)(struct rcu_tasks *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\nstruct rcu_tasks_percpu;\n\nstruct rcu_tasks {\n\tstruct rcuwait cbs_wait;\n\traw_spinlock_t cbs_gbl_lock;\n\tstruct mutex tasks_gp_mutex;\n\tint gp_state;\n\tint gp_sleep;\n\tint init_fract;\n\tlong unsigned int gp_jiffies;\n\tlong unsigned int gp_start;\n\tlong unsigned int tasks_gp_seq;\n\tlong unsigned int n_ipis;\n\tlong unsigned int n_ipis_fails;\n\tstruct task_struct *kthread_ptr;\n\tlong unsigned int lazy_jiffies;\n\trcu_tasks_gp_func_t gp_func;\n\tpregp_func_t pregp_func;\n\tpertask_func_t pertask_func;\n\tpostscan_func_t postscan_func;\n\tholdouts_func_t holdouts_func;\n\tpostgp_func_t postgp_func;\n\tcall_rcu_func_t call_func;\n\tunsigned int wait_state;\n\tstruct rcu_tasks_percpu *rtpcpu;\n\tstruct rcu_tasks_percpu **rtpcp_array;\n\tint percpu_enqueue_shift;\n\tint percpu_enqueue_lim;\n\tint percpu_dequeue_lim;\n\tlong unsigned int percpu_dequeue_gpseq;\n\tstruct mutex barrier_q_mutex;\n\tatomic_t barrier_q_count;\n\tstruct completion barrier_q_completion;\n\tlong unsigned int barrier_q_seq;\n\tlong unsigned int barrier_q_start;\n\tchar *name;\n\tchar *kname;\n};\n\nstruct rcu_tasks_percpu {\n\tstruct rcu_segcblist cblist;\n\traw_spinlock_t lock;\n\tlong unsigned int rtp_jiffies;\n\tlong unsigned int rtp_n_lock_retries;\n\tstruct timer_list lazy_timer;\n\tunsigned int urgent_gp;\n\tstruct work_struct rtp_work;\n\tstruct irq_work rtp_irq_work;\n\tstruct callback_head barrier_q_head;\n\tstruct list_head rtp_blkd_tasks;\n\tstruct list_head rtp_exit_list;\n\tint cpu;\n\tint index;\n\tstruct rcu_tasks *rtpp;\n};\n\nstruct rd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\tstruct in6_addr dest;\n\t__u8 opt[0];\n};\n\nstruct rdev_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct md_rdev *, char *);\n\tssize_t (*store)(struct md_rdev *, const char *, size_t);\n};\n\nstruct rdma_ah_init_attr {\n\tstruct rdma_ah_attr *ah_attr;\n\tu32 flags;\n\tstruct net_device *xmit_slave;\n};\n\nstruct rdma_counter {\n\tstruct rdma_restrack_entry res;\n\tstruct ib_device *device;\n\tuint32_t id;\n\tstruct kref kref;\n\tstruct rdma_counter_mode mode;\n\tstruct mutex lock;\n\tstruct rdma_hw_stats *stats;\n\tu32 port;\n};\n\nstruct rdma_stat_desc;\n\nstruct rdma_hw_stats {\n\tstruct mutex lock;\n\tlong unsigned int timestamp;\n\tlong unsigned int lifespan;\n\tconst struct rdma_stat_desc *descs;\n\tlong unsigned int *is_disabled;\n\tint num_counters;\n\tu64 value[0];\n};\n\nstruct rdma_link_ops {\n\tstruct list_head list;\n\tconst char *type;\n\tint (*newlink)(const char *, struct net_device *);\n};\n\nstruct rdma_netdev_alloc_params {\n\tsize_t sizeof_priv;\n\tunsigned int txqs;\n\tunsigned int rxqs;\n\tvoid *param;\n\tint (*initialize_rdma_netdev)(struct ib_device *, u32, struct net_device *, void *);\n};\n\nstruct rdma_stat_desc {\n\tconst char *name;\n\tunsigned int flags;\n\tconst void *priv;\n};\n\nstruct rdma_user_mmap_entry {\n\tstruct kref ref;\n\tstruct ib_ucontext *ucontext;\n\tlong unsigned int start_pgoff;\n\tsize_t npages;\n\tbool driver_removed;\n\tstruct mutex dmabufs_lock;\n\tstruct list_head dmabufs;\n};\n\nstruct read_balance_ctl {\n\tsector_t closest_dist;\n\tint closest_dist_disk;\n\tint min_pending;\n\tint min_pending_disk;\n\tint sequential_disk;\n\tint readable_disks;\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct file_ra_state *ra;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n\tbool dropbehind;\n\tbool _workingset;\n\tlong unsigned int _pflags;\n};\n\nstruct readdir_callback {\n\tstruct dir_context ctx;\n\tstruct old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n\tunsigned int nr_demoted;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed;\n};\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tlong unsigned int head_block;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\nstruct ref_tracker {\n\tstruct list_head head;\n\tbool dead;\n\tdepot_stack_handle_t alloc_stack_handle;\n\tdepot_stack_handle_t free_stack_handle;\n};\n\nstruct ref_tracker_dir_stats {\n\tint total;\n\tint count;\n\tstruct {\n\t\tdepot_stack_handle_t stack_handle;\n\t\tunsigned int count;\n\t} stacks[0];\n};\n\nstruct referring_call {\n\tuint32_t rc_sequenceid;\n\tuint32_t rc_slotid;\n};\n\nstruct referring_call_list {\n\tstruct nfs4_sessionid rcl_sessionid;\n\tuint32_t rcl_nrefcalls;\n\tstruct referring_call *rcl_refcalls;\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nstruct regbit {\n\tlong unsigned int bit;\n\tconst char *name;\n};\n\nstruct regcache_flat_data {\n\tlong unsigned int *valid;\n\tunsigned int data[0];\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tint (*populate)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regcache_rbtree_node;\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong unsigned int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n\tunsigned int nbits;\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\ts8 reg_shift;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct hwspinlock;\n\nstruct regmap_bus;\n\nstruct regmap_access_table;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t\tstruct {\n\t\t\traw_spinlock_t raw_spinlock;\n\t\t\tlong unsigned int raw_spinlock_flags;\n\t\t};\n\t};\n\tstruct lock_class_key *lock_key;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tunsigned int reg_base;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool async;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool max_register_is_set;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tbool defer_caching;\n\tbool force_write_field;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool can_sleep;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regmap_range;\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_noinc_write)(void *, unsigned int, const void *, size_t);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_noinc_read)(void *, unsigned int, void *, size_t);\n\ntypedef void (*regmap_hw_free_context)(void *);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)(void);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tbool free_on_exit;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_noinc_write reg_noinc_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_reg_noinc_read reg_noinc_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint reg_shift;\n\tunsigned int reg_base;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tint (*read)(void *, const void *, size_t, void *, size_t);\n\tint (*write)(void *, const void *, size_t);\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tbool can_sleep;\n\tbool fast_io;\n\tbool io_port;\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tunsigned int max_register;\n\tbool max_register_is_0;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tint (*reg_default_cb)(struct device *, unsigned int, unsigned int *);\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool use_relaxed_mmio;\n\tbool can_multi_write;\n\tbool use_hwlock;\n\tbool use_raw_spinlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tstruct list_head link;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct release_task_post {\n\tstruct pid *pids[4];\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct renamedata {\n\tstruct mnt_idmap *mnt_idmap;\n\tstruct dentry *old_parent;\n\tstruct dentry *old_dentry;\n\tstruct dentry *new_parent;\n\tstruct dentry *new_dentry;\n\tstruct delegated_inode *delegated_inode;\n\tunsigned int flags;\n};\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef enum rq_end_io_ret rq_end_io_fn(struct request *, blk_status_t, const struct io_comp_batch *);\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tblk_opf_t cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int timeout;\n\tunsigned int __data_len;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tunion {\n\t\tstruct list_head queuelist;\n\t\tstruct request *rq_next;\n\t};\n\tstruct block_device *part;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int nr_integrity_segments;\n\tunsigned char phys_gap_bit;\n\tenum mq_rq_state state;\n\tatomic_t ref;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct llist_node ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t};\n\tstruct {\n\t\tstruct io_cq *icq;\n\t\tvoid *priv[2];\n\t} elv;\n\tstruct {\n\t\tunsigned int seq;\n\t\trq_end_io_fn *saved_end_io;\n\t} flush;\n\tu64 fifo_time;\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct rq_qos;\n\nstruct request_queue {\n\tvoid *queuedata;\n\tstruct elevator_queue *elevator;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tlong unsigned int queue_flags;\n\tunsigned int rq_timeout;\n\tunsigned int queue_depth;\n\trefcount_t refs;\n\tunsigned int nr_hw_queues;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tstruct percpu_ref q_usage_counter;\n\tstruct lock_class_key io_lock_cls_key;\n\tstruct lockdep_map io_lockdep_map;\n\tstruct lock_class_key q_lock_cls_key;\n\tstruct lockdep_map q_lockdep_map;\n\tstruct request *last_merge;\n\tspinlock_t queue_lock;\n\tint quiesce_depth;\n\tstruct gendisk *disk;\n\tstruct kobject *mq_kobj;\n\tstruct queue_limits limits;\n\tstruct device *dev;\n\tenum rpm_status rpm_status;\n\tatomic_t pm_only;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tstruct mutex rq_qos_mutex;\n\tint id;\n\tunsigned int nr_requests;\n\tunsigned int async_depth;\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tatomic_t nr_active_requests_shared_tags;\n\tstruct blk_mq_tags *sched_shared_tags;\n\tstruct list_head icq_list;\n\tlong unsigned int blkcg_pols[1];\n\tstruct blkcg_gq *root_blkg;\n\tstruct list_head blkg_list;\n\tstruct mutex blkcg_mutex;\n\tint node;\n\tspinlock_t requeue_lock;\n\tstruct list_head requeue_list;\n\tstruct delayed_work requeue_work;\n\tstruct blk_trace *blk_trace;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head flush_list;\n\tstruct mutex elevator_lock;\n\tstruct mutex sysfs_lock;\n\tstruct mutex limits_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tstruct mutex debugfs_mutex;\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct request_sock__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *, enum sk_rst_reason);\n\tvoid (*destructor)(struct request_sock *);\n};\n\nstruct reserve_mem_table {\n\tchar name[16];\n\tphys_addr_t start;\n\tphys_addr_t size;\n};\n\nstruct reserved_mem_ops;\n\nstruct reserved_mem {\n\tconst char *name;\n\tlong unsigned int fdt_node;\n\tconst struct reserved_mem_ops *ops;\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tvoid *priv;\n};\n\nstruct reserved_mem_ops {\n\tint (*device_init)(struct reserved_mem *, struct device *);\n\tvoid (*device_release)(struct reserved_mem *, struct device *);\n};\n\ntypedef resource_size_t (*resource_alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_alignf alignf;\n\tvoid *alignf_data;\n};\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct restart_block {\n\tlong unsigned int arch_data;\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tktime_t time;\n\t\t\tu32 *uaddr2;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tktime_t expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tstruct timespec64 end_time;\n\t\t} poll;\n\t};\n};\n\nstruct restart_table_entry {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int fixup;\n};\n\nstruct resv_map {\n\tstruct kref refs;\n\tspinlock_t lock;\n\tstruct list_head regions;\n\tlong int adds_in_progress;\n\tstruct list_head region_cache;\n\tlong int region_cache_count;\n\tstruct rw_semaphore rw_sema;\n\tstruct page_counter *reservation_counter;\n\tlong unsigned int pages_per_hpage;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct resync_pages {\n\tvoid *raid_bio;\n\tstruct page *pages[1];\n};\n\nstruct rethook {\n\tvoid *data;\n\tvoid (*handler)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\tstruct objpool_head pool;\n\tstruct callback_head rcu;\n};\n\nstruct return_consumer {\n\t__u64 cookie;\n\t__u64 id;\n};\n\nstruct return_instance {\n\tstruct hprobe hprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tint cons_cnt;\n\tstruct return_instance *next;\n\tstruct callback_head rcu;\n\tstruct return_consumer consumer;\n\tstruct return_consumer *extra_consumers;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nstruct revmap_entry {\n\tlong unsigned int guest_rpte;\n\tunsigned int forw;\n\tunsigned int back;\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nstruct rhash_lock_head {};\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nstruct ring_buffer_cpu_meta {\n\tlong unsigned int first_buffer;\n\tlong unsigned int head_buffer;\n\tlong unsigned int commit_buffer;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tint buffers[0];\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tlong unsigned int cache_pages_removed;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tsize_t event_size;\n\tint missed_events;\n};\n\nstruct ring_buffer_meta {\n\tint magic;\n\tint struct_sizes;\n\tlong unsigned int total_size;\n\tlong unsigned int buffers_offset;\n};\n\nstruct trace_buffer_meta;\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tlong unsigned int cnt;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_lost;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\trb_time_t write_stamp;\n\trb_time_t before_stamp;\n\tu64 event_stamp[5];\n\tu64 read_stamp;\n\tlong unsigned int pages_removed;\n\tunsigned int mapped;\n\tunsigned int user_mapped;\n\tstruct mutex mapping_lock;\n\tlong unsigned int *subbuf_ids;\n\tstruct trace_buffer_meta *meta_page;\n\tstruct ring_buffer_cpu_meta *ring_meta;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct ring_info {\n\tu8 *data;\n\tdma_addr_t mapping;\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n\tstruct kernel_ethtool_ringparam kernel_ringparam;\n\tu32 supported_ring_params;\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct rmap_walk_arg {\n\tstruct folio *folio;\n\tbool map_unused_to_zeropage;\n};\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool try_lock;\n\tbool contended;\n\tbool (*rmap_one)(struct folio *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct folio *);\n\tstruct anon_vma * (*anon_lock)(const struct folio *, struct rmap_walk_control *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct rmem_assigned_device {\n\tstruct device *dev;\n\tstruct reserved_mem *rmem;\n\tstruct list_head list;\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_gpio_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_gpio_data gpio_data;\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tstruct crypto_alg base;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct rock_ridge {\n\t__u8 signature[2];\n\t__u8 len;\n\t__u8 version;\n\tunion {\n\t\tstruct SU_SP_s SP;\n\t\tstruct SU_CE_s CE;\n\t\tstruct SU_ER_s ER;\n\t\tstruct RR_RR_s RR;\n\t\tstruct RR_PX_s PX;\n\t\tstruct RR_PN_s PN;\n\t\tstruct RR_SL_s SL;\n\t\tstruct RR_NM_s NM;\n\t\tstruct RR_CL_s CL;\n\t\tstruct RR_PL_s PL;\n\t\tstruct RR_TF_s TF;\n\t\tstruct RR_ZF_s ZF;\n\t} u;\n};\n\nstruct rock_state {\n\tvoid *buffer;\n\tunsigned char *chr;\n\tint len;\n\tint cont_size;\n\tint cont_extent;\n\tint cont_offset;\n\tint cont_loops;\n\tstruct inode *inode;\n};\n\nstruct role_allow {\n\tu32 role;\n\tu32 new_role;\n\tstruct role_allow *next;\n};\n\nstruct role_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap dominates;\n\tstruct ebitmap types;\n};\n\nstruct role_trans_datum {\n\tu32 new_role;\n};\n\nstruct role_trans_key {\n\tu32 role;\n\tu32 type;\n\tu32 tclass;\n};\n\nstruct romfs_super_block {\n\t__be32 word0;\n\t__be32 word1;\n\t__be32 size;\n\t__be32 checksum;\n\tchar name[0];\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n};\n\nstruct root_domain {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tbool overloaded;\n\tbool overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tu64 visit_cookie;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tstruct perf_domain *pd;\n};\n\nstruct rpc_add_xprt_test {\n\tvoid (*add_xprt_test)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tvoid *data;\n};\n\nstruct rpc_auth_create_args {\n\trpc_authflavor_t pseudoflavor;\n\tconst char *target_name;\n};\n\nstruct rpc_authops {\n\tstruct module *owner;\n\trpc_authflavor_t au_flavor;\n\tchar *au_name;\n\tstruct rpc_auth * (*create)(const struct rpc_auth_create_args *, struct rpc_clnt *);\n\tvoid (*destroy)(struct rpc_auth *);\n\tint (*hash_cred)(struct auth_cred *, unsigned int);\n\tstruct rpc_cred * (*lookup_cred)(struct rpc_auth *, struct auth_cred *, int);\n\tstruct rpc_cred * (*crcreate)(struct rpc_auth *, struct auth_cred *, int, gfp_t);\n\trpc_authflavor_t (*info2flavor)(struct rpcsec_gss_info *);\n\tint (*flavor2info)(rpc_authflavor_t, struct rpcsec_gss_info *);\n\tint (*key_timeout)(struct rpc_auth *, struct rpc_cred *);\n\tint (*ping)(struct rpc_clnt *);\n};\n\nstruct rpc_bind_conn_calldata {\n\tstruct nfs_client *clp;\n\tconst struct cred *cred;\n};\n\nstruct rpc_buffer {\n\tsize_t len;\n\tchar data[0];\n};\n\nstruct rpc_call_ops {\n\tvoid (*rpc_call_prepare)(struct rpc_task *, void *);\n\tvoid (*rpc_call_done)(struct rpc_task *, void *);\n\tvoid (*rpc_count_stats)(struct rpc_task *, void *);\n\tvoid (*rpc_release)(void *);\n};\n\nstruct rpc_xprt_switch;\n\nstruct rpc_cb_add_xprt_calldata {\n\tstruct rpc_xprt_switch *xps;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_pipe_dir_head {\n\tstruct list_head pdh_entries;\n\tstruct dentry *pdh_dentry;\n};\n\nstruct rpc_rtt {\n\tlong unsigned int timeo;\n\tlong unsigned int srtt[5];\n\tlong unsigned int sdrtt[5];\n\tint ntimeouts[5];\n};\n\nstruct rpc_timeout {\n\tlong unsigned int to_initval;\n\tlong unsigned int to_maxval;\n\tlong unsigned int to_increment;\n\tunsigned int to_retries;\n\tunsigned char to_exponential;\n};\n\nstruct rpc_xprt_iter_ops;\n\nstruct rpc_xprt_iter {\n\tstruct rpc_xprt_switch *xpi_xpswitch;\n\tstruct rpc_xprt *xpi_cursor;\n\tconst struct rpc_xprt_iter_ops *xpi_ops;\n};\n\nstruct rpc_iostats;\n\nstruct rpc_sysfs_client;\n\nstruct rpc_clnt {\n\trefcount_t cl_count;\n\tunsigned int cl_clid;\n\tstruct list_head cl_clients;\n\tstruct list_head cl_tasks;\n\tatomic_t cl_pid;\n\tspinlock_t cl_lock;\n\tstruct rpc_xprt *cl_xprt;\n\tconst struct rpc_procinfo *cl_procinfo;\n\tu32 cl_prog;\n\tu32 cl_vers;\n\tu32 cl_maxproc;\n\tstruct rpc_auth *cl_auth;\n\tstruct rpc_stat *cl_stats;\n\tstruct rpc_iostats *cl_metrics;\n\tunsigned int cl_softrtry: 1;\n\tunsigned int cl_softerr: 1;\n\tunsigned int cl_discrtry: 1;\n\tunsigned int cl_noretranstimeo: 1;\n\tunsigned int cl_autobind: 1;\n\tunsigned int cl_chatty: 1;\n\tunsigned int cl_shutdown: 1;\n\tunsigned int cl_netunreach_fatal: 1;\n\tstruct xprtsec_parms cl_xprtsec;\n\tstruct rpc_rtt *cl_rtt;\n\tconst struct rpc_timeout *cl_timeout;\n\tatomic_t cl_swapper;\n\tint cl_nodelen;\n\tchar cl_nodename[65];\n\tstruct rpc_pipe_dir_head cl_pipedir_objects;\n\tstruct rpc_clnt *cl_parent;\n\tstruct rpc_rtt cl_rtt_default;\n\tstruct rpc_timeout cl_timeout_default;\n\tconst struct rpc_program *cl_program;\n\tconst char *cl_principal;\n\tstruct rpc_sysfs_client *cl_sysfs;\n\tunion {\n\t\tstruct rpc_xprt_iter cl_xpi;\n\t\tstruct work_struct cl_work;\n\t};\n\tconst struct cred *cl_cred;\n\tunsigned int cl_max_connect;\n\tstruct super_block *pipefs_sb;\n\tatomic_t cl_task_count;\n};\n\nstruct svc_xprt;\n\nstruct rpc_create_args {\n\tstruct net *net;\n\tint protocol;\n\tstruct sockaddr *address;\n\tsize_t addrsize;\n\tstruct sockaddr *saddress;\n\tconst struct rpc_timeout *timeout;\n\tconst char *servername;\n\tconst char *nodename;\n\tconst struct rpc_program *program;\n\tstruct rpc_stat *stats;\n\tu32 prognumber;\n\tu32 version;\n\trpc_authflavor_t authflavor;\n\tu32 nconnect;\n\tlong unsigned int flags;\n\tchar *client_name;\n\tstruct svc_xprt *bc_xprt;\n\tconst struct cred *cred;\n\tunsigned int max_connect;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct rpc_cred_cache {\n\tstruct hlist_head *hashtable;\n\tunsigned int hashbits;\n\tspinlock_t lock;\n};\n\nstruct rpc_credops {\n\tconst char *cr_name;\n\tint (*cr_init)(struct rpc_auth *, struct rpc_cred *);\n\tvoid (*crdestroy)(struct rpc_cred *);\n\tint (*crmatch)(struct auth_cred *, struct rpc_cred *, int);\n\tint (*crmarshal)(struct rpc_task *, struct xdr_stream *);\n\tint (*crrefresh)(struct rpc_task *);\n\tint (*crvalidate)(struct rpc_task *, struct xdr_stream *);\n\tint (*crwrap_req)(struct rpc_task *, struct xdr_stream *);\n\tint (*crunwrap_resp)(struct rpc_task *, struct xdr_stream *);\n\tint (*crkey_timeout)(struct rpc_cred *);\n\tchar * (*crstringify_acceptor)(struct rpc_cred *);\n\tbool (*crneed_reencode)(struct rpc_task *);\n};\n\nstruct rpc_filelist {\n\tconst char *name;\n\tconst struct file_operations *i_fop;\n\tumode_t mode;\n};\n\nstruct rpc_inode {\n\tstruct inode vfs_inode;\n\tvoid *private;\n\tstruct rpc_pipe *pipe;\n\twait_queue_head_t waitq;\n};\n\nstruct rpc_iostats {\n\tspinlock_t om_lock;\n\tlong unsigned int om_ops;\n\tlong unsigned int om_ntrans;\n\tlong unsigned int om_timeouts;\n\tlong long unsigned int om_bytes_sent;\n\tlong long unsigned int om_bytes_recv;\n\tktime_t om_queue;\n\tktime_t om_rtt;\n\tktime_t om_execute;\n\tlong unsigned int om_error_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rpc_pipe {\n\tstruct list_head pipe;\n\tstruct list_head in_upcall;\n\tstruct list_head in_downcall;\n\tint pipelen;\n\tint nreaders;\n\tint nwriters;\n\tint flags;\n\tstruct delayed_work queue_timeout;\n\tconst struct rpc_pipe_ops *ops;\n\tspinlock_t lock;\n\tstruct dentry *dentry;\n};\n\nstruct rpc_pipe_dir_object_ops {\n\tint (*create)(struct dentry *, struct rpc_pipe_dir_object *);\n\tvoid (*destroy)(struct dentry *, struct rpc_pipe_dir_object *);\n};\n\nstruct rpc_pipe_ops {\n\tssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char *, size_t);\n\tssize_t (*downcall)(struct file *, const char *, size_t);\n\tvoid (*release_pipe)(struct inode *);\n\tint (*open_pipe)(struct inode *);\n\tvoid (*destroy_msg)(struct rpc_pipe_msg *);\n};\n\ntypedef void (*kxdreproc_t)(struct rpc_rqst *, struct xdr_stream *, const void *);\n\ntypedef int (*kxdrdproc_t)(struct rpc_rqst *, struct xdr_stream *, void *);\n\nstruct rpc_procinfo {\n\tu32 p_proc;\n\tkxdreproc_t p_encode;\n\tkxdrdproc_t p_decode;\n\tunsigned int p_arglen;\n\tunsigned int p_replen;\n\tunsigned int p_timer;\n\tu32 p_statidx;\n\tconst char *p_name;\n};\n\nstruct rpc_program {\n\tconst char *name;\n\tu32 number;\n\tunsigned int nrvers;\n\tconst struct rpc_version **version;\n\tstruct rpc_stat *stats;\n\tconst char *pipe_dir_name;\n};\n\nstruct xdr_buf {\n\tstruct kvec head[1];\n\tstruct kvec tail[1];\n\tstruct bio_vec *bvec;\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int flags;\n\tunsigned int buflen;\n\tunsigned int len;\n};\n\nstruct rpc_rqst {\n\tstruct rpc_xprt *rq_xprt;\n\tstruct xdr_buf rq_snd_buf;\n\tstruct xdr_buf rq_rcv_buf;\n\tstruct rpc_task *rq_task;\n\tstruct rpc_cred *rq_cred;\n\t__be32 rq_xid;\n\tint rq_cong;\n\tu32 rq_seqnos[3];\n\tunsigned int rq_seqno_count;\n\tint rq_enc_pages_num;\n\tstruct page **rq_enc_pages;\n\tvoid (*rq_release_snd_buf)(struct rpc_rqst *);\n\tunion {\n\t\tstruct list_head rq_list;\n\t\tstruct rb_node rq_recv;\n\t};\n\tstruct list_head rq_xmit;\n\tstruct list_head rq_xmit2;\n\tvoid *rq_buffer;\n\tsize_t rq_callsize;\n\tvoid *rq_rbuffer;\n\tsize_t rq_rcvsize;\n\tsize_t rq_xmit_bytes_sent;\n\tsize_t rq_reply_bytes_recvd;\n\tstruct xdr_buf rq_private_buf;\n\tlong unsigned int rq_majortimeo;\n\tlong unsigned int rq_minortimeo;\n\tlong unsigned int rq_timeout;\n\tktime_t rq_rtt;\n\tunsigned int rq_retries;\n\tunsigned int rq_connect_cookie;\n\tatomic_t rq_pin;\n\tu32 rq_bytes_sent;\n\tktime_t rq_xtime;\n\tint rq_ntrans;\n\tstruct lwq_node rq_bc_list;\n\tlong unsigned int rq_bc_pa_state;\n\tstruct list_head rq_bc_pa_list;\n};\n\nstruct rpc_sysfs_client {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_clnt *clnt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt {\n\tstruct kobject kobject;\n\tstruct rpc_xprt *xprt;\n\tstruct rpc_xprt_switch *xprt_switch;\n};\n\nstruct rpc_sysfs_xprt_switch {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tstruct rpc_xprt_switch *xprt_switch;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct rpc_task_setup {\n\tstruct rpc_task *task;\n\tstruct rpc_clnt *rpc_client;\n\tstruct rpc_xprt *rpc_xprt;\n\tstruct rpc_cred *rpc_op_cred;\n\tconst struct rpc_message *rpc_message;\n\tconst struct rpc_call_ops *callback_ops;\n\tvoid *callback_data;\n\tstruct workqueue_struct *workqueue;\n\tshort unsigned int flags;\n\tsigned char priority;\n};\n\nstruct rpc_version {\n\tu32 number;\n\tunsigned int nrprocs;\n\tconst struct rpc_procinfo *procs;\n\tunsigned int *counts;\n};\n\nstruct rpc_xprt_ops;\n\nstruct xprt_class;\n\nstruct rpc_xprt {\n\tstruct kref kref;\n\tconst struct rpc_xprt_ops *ops;\n\tunsigned int id;\n\tconst struct rpc_timeout *timeout;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tint prot;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tsize_t max_payload;\n\tstruct rpc_wait_queue binding;\n\tstruct rpc_wait_queue sending;\n\tstruct rpc_wait_queue pending;\n\tstruct rpc_wait_queue backlog;\n\tstruct list_head free;\n\tunsigned int max_reqs;\n\tunsigned int min_reqs;\n\tunsigned int num_reqs;\n\tlong unsigned int state;\n\tunsigned char resvport: 1;\n\tunsigned char reuseport: 1;\n\tatomic_t swapper;\n\tunsigned int bind_index;\n\tstruct list_head xprt_switch;\n\tlong unsigned int bind_timeout;\n\tlong unsigned int reestablish_timeout;\n\tstruct xprtsec_parms xprtsec;\n\tunsigned int connect_cookie;\n\tstruct work_struct task_cleanup;\n\tstruct timer_list timer;\n\tlong unsigned int last_used;\n\tlong unsigned int idle_timeout;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int max_reconnect_timeout;\n\tatomic_long_t queuelen;\n\tspinlock_t transport_lock;\n\tspinlock_t reserve_lock;\n\tspinlock_t queue_lock;\n\tu32 xid;\n\tstruct rpc_task *snd_task;\n\tstruct list_head xmit_queue;\n\tatomic_long_t xmit_queuelen;\n\tstruct svc_xprt *bc_xprt;\n\tstruct svc_serv *bc_serv;\n\tunsigned int bc_alloc_max;\n\tunsigned int bc_alloc_count;\n\tatomic_t bc_slot_count;\n\tspinlock_t bc_pa_lock;\n\tstruct list_head bc_pa_list;\n\tstruct rb_root recv_queue;\n\tstruct {\n\t\tlong unsigned int bind_count;\n\t\tlong unsigned int connect_count;\n\t\tlong unsigned int connect_start;\n\t\tlong unsigned int connect_time;\n\t\tlong unsigned int sends;\n\t\tlong unsigned int recvs;\n\t\tlong unsigned int bad_xids;\n\t\tlong unsigned int max_slots;\n\t\tlong long unsigned int req_u;\n\t\tlong long unsigned int bklog_u;\n\t\tlong long unsigned int sending_u;\n\t\tlong long unsigned int pending_u;\n\t} stat;\n\tstruct net *xprt_net;\n\tnetns_tracker ns_tracker;\n\tconst char *servername;\n\tconst char *address_strings[6];\n\tstruct callback_head rcu;\n\tconst struct xprt_class *xprt_class;\n\tstruct rpc_sysfs_xprt *xprt_sysfs;\n\tbool main;\n};\n\nstruct rpc_xprt_iter_ops {\n\tvoid (*xpi_rewind)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_xprt)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_next)(struct rpc_xprt_iter *);\n};\n\nstruct rpc_xprt_ops {\n\tvoid (*set_buffer_size)(struct rpc_xprt *, size_t, size_t);\n\tint (*reserve_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*alloc_slot)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*free_slot)(struct rpc_xprt *, struct rpc_rqst *);\n\tvoid (*rpcbind)(struct rpc_task *);\n\tvoid (*set_port)(struct rpc_xprt *, short unsigned int);\n\tvoid (*connect)(struct rpc_xprt *, struct rpc_task *);\n\tint (*get_srcaddr)(struct rpc_xprt *, char *, size_t);\n\tshort unsigned int (*get_srcport)(struct rpc_xprt *);\n\tint (*buf_alloc)(struct rpc_task *);\n\tvoid (*buf_free)(struct rpc_task *);\n\tint (*prepare_request)(struct rpc_rqst *, struct xdr_buf *);\n\tint (*send_request)(struct rpc_rqst *);\n\tvoid (*abort_send_request)(struct rpc_rqst *);\n\tvoid (*wait_for_reply_request)(struct rpc_task *);\n\tvoid (*timer)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_request)(struct rpc_task *);\n\tvoid (*close)(struct rpc_xprt *);\n\tvoid (*destroy)(struct rpc_xprt *);\n\tvoid (*set_connect_timeout)(struct rpc_xprt *, long unsigned int, long unsigned int);\n\tvoid (*print_stats)(struct rpc_xprt *, struct seq_file *);\n\tint (*enable_swap)(struct rpc_xprt *);\n\tvoid (*disable_swap)(struct rpc_xprt *);\n\tvoid (*inject_disconnect)(struct rpc_xprt *);\n\tint (*bc_setup)(struct rpc_xprt *, unsigned int);\n\tsize_t (*bc_maxpayload)(struct rpc_xprt *);\n\tunsigned int (*bc_num_slots)(struct rpc_xprt *);\n\tvoid (*bc_free_rqst)(struct rpc_rqst *);\n\tvoid (*bc_destroy)(struct rpc_xprt *, unsigned int);\n};\n\nstruct rpc_xprt_switch {\n\tspinlock_t xps_lock;\n\tstruct kref xps_kref;\n\tunsigned int xps_id;\n\tunsigned int xps_nxprts;\n\tunsigned int xps_nactive;\n\tunsigned int xps_nunique_destaddr_xprts;\n\tatomic_long_t xps_queuelen;\n\tstruct list_head xps_xprt_list;\n\tstruct net *xps_net;\n\tconst struct rpc_xprt_iter_ops *xps_iter_ops;\n\tstruct rpc_sysfs_xprt_switch *xps_sysfs;\n\tstruct callback_head xps_rcu;\n};\n\nstruct rpcb_info {\n\tu32 rpc_vers;\n\tconst struct rpc_procinfo *rpc_proc;\n};\n\nstruct rpcbind_args {\n\tstruct rpc_xprt *r_xprt;\n\tu32 r_prog;\n\tu32 r_vers;\n\tu32 r_prot;\n\tshort unsigned int r_port;\n\tconst char *r_netid;\n\tconst char *r_addr;\n\tconst char *r_owner;\n\tint r_status;\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n\tu32 hash;\n};\n\nstruct rps_dev_flow_table {\n\tu8 log;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_sock_flow_table {\n\tstruct callback_head rcu;\n\tu32 mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 ents[0];\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[2];\n\tstruct list_head queue[100];\n};\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tbool overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tstruct task_group *tg;\n};\n\nstruct scx_dsq_pcpu;\n\nstruct scx_dispatch_q {\n\traw_spinlock_t lock;\n\tstruct task_struct *first_task;\n\tstruct list_head list;\n\tstruct rb_root priq;\n\tu32 nr;\n\tu32 seq;\n\tu64 id;\n\tstruct rhash_head hash_node;\n\tstruct llist_node free_node;\n\tstruct scx_sched *sched;\n\tstruct scx_dsq_pcpu *pcpu;\n\tstruct callback_head rcu;\n};\n\nstruct scx_rq {\n\tstruct scx_dispatch_q local_dsq;\n\tstruct list_head runnable_list;\n\tstruct list_head ddsp_deferred_locals;\n\tlong unsigned int ops_qseq;\n\tu64 extra_enq_flags;\n\tu32 nr_running;\n\tu32 cpuperf_target;\n\tbool cpu_released;\n\tu32 flags;\n\tu64 clock;\n\tcpumask_var_t cpus_to_kick;\n\tcpumask_var_t cpus_to_kick_if_idle;\n\tcpumask_var_t cpus_to_preempt;\n\tcpumask_var_t cpus_to_wait;\n\tlong unsigned int kick_sync;\n\tstruct task_struct *sub_dispatch_prev;\n\traw_spinlock_t deferred_reenq_lock;\n\tstruct list_head deferred_reenq_locals;\n\tstruct list_head deferred_reenq_users;\n\tstruct balance_callback deferred_bal_cb;\n\tstruct irq_work deferred_irq_work;\n\tstruct irq_work kick_cpus_irq_work;\n};\n\nstruct sched_dl_entity;\n\ntypedef struct task_struct * (*dl_server_pick_f)(struct sched_dl_entity *, struct rq_flags *);\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tunsigned int dl_server: 1;\n\tunsigned int dl_server_active: 1;\n\tunsigned int dl_defer: 1;\n\tunsigned int dl_defer_armed: 1;\n\tunsigned int dl_defer_running: 1;\n\tunsigned int dl_defer_idle: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n\tstruct rq *rq;\n\tdl_server_pick_f server_pick_task;\n\tstruct sched_dl_entity *pi_se;\n};\n\nstruct sched_info {\n\tlong unsigned int pcount;\n\tlong long unsigned int run_delay;\n\tlong long unsigned int max_run_delay;\n\tlong long unsigned int min_run_delay;\n\tlong long unsigned int last_arrival;\n\tlong long unsigned int last_queued;\n\tstruct timespec64 max_run_delay_ts;\n};\n\nstruct sched_class;\n\nstruct rq {\n\tunsigned int nr_running;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n\tunsigned int ttwu_pending;\n\tlong unsigned int cpu_capacity;\n\tunion {\n\t\tstruct task_struct *donor;\n\t\tstruct task_struct *curr;\n\t};\n\tstruct task_struct *idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 nr_switches;\n\traw_spinlock_t __lock;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int has_blocked_load;\n\tlong unsigned int last_blocked_load_update_tick;\n\tcall_single_data_t nohz_csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tstruct dl_rq dl;\n\tstruct scx_rq scx;\n\tstruct sched_dl_entity ext_server;\n\tstruct sched_dl_entity fair_server;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tunsigned int numa_migrate_on;\n\tlong unsigned int nr_uninterruptible;\n\tstruct sched_dl_entity *dl_server;\n\tstruct task_struct *stop;\n\tconst struct sched_class *next_class;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tu64 clock;\n\tlong unsigned int lost_idle_time;\n\tunsigned int clock_update_flags;\n\tu64 clock_pelt_idle;\n\tu64 clock_idle;\n\tu64 last_seen_need_resched_ns;\n\tint ticks_without_resched;\n\tint membarrier_state;\n\tstruct root_domain *rd;\n\tstruct sched_domain *sd;\n\tstruct balance_callback *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tstruct sched_avg avg_irq;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tstruct rcuwait hotplug_wait;\n\tu64 prev_steal_time;\n\tu64 prev_steal_time_rq;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tktime_t hrtick_time;\n\tstruct sched_info rq_sched_info;\n\tlong long unsigned int rq_cpu_time;\n\tunsigned int yld_count;\n\tunsigned int sched_count;\n\tunsigned int sched_goidle;\n\tunsigned int ttwu_count;\n\tunsigned int ttwu_local;\n\tstruct cpuidle_state *idle_state;\n\tunsigned int nr_pinned;\n\tunsigned int push_busy;\n\tstruct cpu_stop_work push_work;\n\tcpumask_var_t scratch_mask;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t cfsb_csd;\n\tstruct list_head cfsb_csd_list;\n\tatomic_t nr_iowait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tlong unsigned int offset;\n\tshort unsigned int page_order;\n\tshort unsigned int nr_entries;\n\tbool null_mapped;\n\tbool from_user;\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tconst struct rq_qos_ops *ops;\n\tstruct gendisk *disk;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\nstruct rq_wait;\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct rqspinlock_held {\n\tint cnt;\n\tvoid *locks[31];\n};\n\nstruct rqspinlock_timeout {\n\tu64 timeout_end;\n\tu64 duration;\n\tu64 cur;\n\tu16 spin;\n};\n\nstruct rs_msg {\n\tstruct icmp6hdr icmph;\n\t__u8 opt[0];\n};\n\nstruct rsa_key {\n\tconst u8 *n;\n\tconst u8 *e;\n\tconst u8 *d;\n\tconst u8 *p;\n\tconst u8 *q;\n\tconst u8 *dp;\n\tconst u8 *dq;\n\tconst u8 *qinv;\n\tsize_t n_sz;\n\tsize_t e_sz;\n\tsize_t d_sz;\n\tsize_t p_sz;\n\tsize_t q_sz;\n\tsize_t dp_sz;\n\tsize_t dq_sz;\n\tsize_t qinv_sz;\n};\n\nstruct rsa_mpi_key {\n\tMPI n;\n\tMPI e;\n\tMPI d;\n\tMPI p;\n\tMPI q;\n\tMPI dp;\n\tMPI dq;\n\tMPI qinv;\n};\n\nstruct rsassa_pkcs1_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct rsassa_pkcs1_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n\tconst struct hash_prefix *hash_prefix;\n};\n\nstruct rsc {\n\tstruct cache_head h;\n\tstruct xdr_netobj handle;\n\tstruct svc_cred cred;\n\tstruct gss_svc_seq_data seqdata;\n\tstruct gss_ctx *mechctx;\n\tstruct callback_head callback_head;\n};\n\nstruct rseq_slice_ctrl {\n\tunion {\n\t\t__u32 all;\n\t\tstruct {\n\t\t\t__u8 request;\n\t\t\t__u8 granted;\n\t\t\t__u16 __reserved;\n\t\t};\n\t};\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\t__u64 rseq_cs;\n\t__u32 flags;\n\t__u32 node_id;\n\t__u32 mm_cid;\n\tstruct rseq_slice_ctrl slice_ctrl;\n\t__u8 __reserved;\n\tchar end[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct rseq_event {\n\tunion {\n\t\tu64 all;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 events;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 sched_switch;\n\t\t\t\t\tu8 ids_changed;\n\t\t\t\t\tu8 user_irq;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu8 has_rseq;\n\t\t\tu8 __pad;\n\t\t\tunion {\n\t\t\t\tu16 error;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 fatal;\n\t\t\t\t\tu8 slowpath;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\nstruct rseq_ids {\n\tunion {\n\t\tu64 cpu_cid;\n\t\tstruct {\n\t\t\tu32 cpu_id;\n\t\t\tu32 mm_cid;\n\t\t};\n\t};\n};\n\nstruct rseq_data {\n\tstruct rseq *usrptr;\n\tu32 len;\n\tu32 sig;\n\tstruct rseq_event event;\n\tstruct rseq_ids ids;\n};\n\nstruct rsi {\n\tstruct cache_head h;\n\tstruct xdr_netobj in_handle;\n\tstruct xdr_netobj in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tint major_status;\n\tint minor_status;\n\tstruct callback_head callback_head;\n};\n\nstruct rss_nl_dump_ctx {\n\tlong unsigned int ifindex;\n\tlong unsigned int ctx_idx;\n\tunsigned int match_ifindex;\n\tunsigned int start_ctx;\n};\n\nstruct rss_reply_data {\n\tstruct ethnl_reply_data base;\n\tbool has_flow_hash;\n\tbool no_key_fields;\n\tu32 indir_size;\n\tu32 hkey_size;\n\tu32 hfunc;\n\tu32 input_xfrm;\n\tu32 *indir_table;\n\tu8 *hkey;\n\tint flow_hash[28];\n};\n\nstruct rss_req_info {\n\tstruct ethnl_req_info base;\n\tu32 rss_context;\n};\n\nstruct rsvd_count {\n\tint ndelayed;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct rt0_hdr {\n\tstruct ipv6_rt_hdr rt_hdr;\n\t__u32 reserved;\n\tstruct in6_addr addr[0];\n};\n\nstruct rt6_exception {\n\tstruct hlist_node hlist;\n\tstruct rt6_info *rt6i;\n\tlong unsigned int stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct rt6_mtu_change_arg {\n\tstruct net_device *dev;\n\tunsigned int mtu;\n\tstruct fib6_info *f6i;\n};\n\nstruct rt6_nh {\n\tstruct fib6_info *fib6_info;\n\tstruct fib6_config r_cfg;\n\tstruct list_head list;\n};\n\nstruct rt6_rtnl_dump_arg {\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct net *net;\n\tstruct fib_dump_filter filter;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct rt_waiter_node {\n\tstruct rb_node entry;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex_waiter {\n\tstruct rt_waiter_node tree;\n\tstruct rt_waiter_node pi_tree;\n\tstruct task_struct *task;\n\tstruct rt_mutex_base *lock;\n\tunsigned int wake_state;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\t__kernel_size_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct sigcontext {\n\tlong unsigned int _unused[4];\n\tint signal;\n\tint _pad0;\n\tlong unsigned int handler;\n\tlong unsigned int oldmask;\n\tstruct user_pt_regs *regs;\n\telf_gregset_t gp_regs;\n\telf_fpregset_t fp_regs;\n\telf_vrreg_t *v_regs;\n\tlong int vmx_reserve[101];\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tsigset_t uc_sigmask;\n\tsigset_t __unused[15];\n\tstruct sigcontext uc_mcontext;\n};\n\nstruct rt_sigframe {\n\tstruct ucontext uc;\n\tstruct ucontext uc_transact;\n\tlong unsigned int _unused[2];\n\tunsigned int tramp[7];\n\tstruct siginfo *pinfo;\n\tvoid *puc;\n\tstruct siginfo info;\n\tchar abigap[512];\n};\n\nstruct wake_q_node;\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct rt_wake_q_head {\n\tstruct wake_q_head head;\n\tstruct task_struct *rtlock_task;\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n};\n\nstruct rtas_args {\n\t__be32 token;\n\t__be32 nargs;\n\t__be32 nret;\n\trtas_arg_t args[16];\n\trtas_arg_t *rets;\n};\n\nstruct rtas_error_log {\n\tu8 byte0;\n\tu8 byte1;\n\tu8 byte2;\n\tu8 byte3;\n\t__be32 extended_log_length;\n\tunsigned char buffer[1];\n};\n\nstruct rtas_ext_event_log_v6 {\n\tu8 byte0;\n\tu8 byte1;\n\tu8 byte2;\n\tu8 byte3;\n\tu8 reserved[8];\n\t__be32 company_id;\n\tu8 vendor_log[1];\n};\n\nstruct rtas_fadump_section_header {\n\t__be32 dump_format_version;\n\t__be16 dump_num_sections;\n\t__be16 dump_status_flag;\n\t__be32 offset_first_dump_section;\n\t__be32 dd_block_size;\n\t__be64 dd_block_offset;\n\t__be64 dd_num_blocks;\n\t__be32 dd_offset_disk_path;\n\t__be32 max_time_auto;\n};\n\nstruct rtas_fadump_section {\n\t__be32 request_flag;\n\t__be16 source_data_type;\n\t__be16 error_flags;\n\t__be64 source_address;\n\t__be64 source_len;\n\t__be64 bytes_dumped;\n\t__be64 destination_address;\n};\n\nstruct rtas_fadump_mem_struct {\n\tstruct rtas_fadump_section_header header;\n\tstruct rtas_fadump_section rgn[10];\n};\n\nstruct rtas_fadump_reg_entry {\n\t__be64 reg_id;\n\t__be64 reg_value;\n};\n\nstruct rtas_fadump_reg_save_area_header {\n\t__be64 magic_number;\n\t__be32 version;\n\t__be32 num_cpu_offset;\n};\n\nstruct rtas_filter {\n\tconst int buf_idx1;\n\tconst int size_idx1;\n\tconst int buf_idx2;\n\tconst int size_idx2;\n\tconst int fixed_size;\n};\n\nstruct rtas_function {\n\ts32 token;\n\tconst bool banned_for_syscall_on_le: 1;\n\tconst char * const name;\n\tconst struct rtas_filter *filter;\n\tstruct mutex *lock;\n};\n\nstruct rtas_get_indices_params {\n\tu8 is_sensor;\n\tu32 indice_type;\n\tstruct rtas_work_area *work_area;\n\tu32 next;\n\ts32 status;\n};\n\nstruct rtas_ibm_get_vpd_params {\n\tconst struct papr_location_code *loc_code;\n\tstruct rtas_work_area *work_area;\n\tu32 sequence;\n\tu32 written;\n\ts32 status;\n};\n\nstruct rtas_phy_attest_params {\n\tstruct papr_phy_attest_io_block cmd;\n\tstruct rtas_work_area *work_area;\n\tu32 cmd_len;\n\tu32 sequence;\n\tu32 written;\n\ts32 status;\n};\n\nstruct rtas_sensors {\n\tstruct individual_sensor sensor[17];\n\tunsigned int quant;\n};\n\nstruct rtas_t {\n\tlong unsigned int entry;\n\tlong unsigned int base;\n\tlong unsigned int size;\n\tstruct device_node *dev;\n};\n\nstruct rtas_work_area {\n\tchar *buf;\n\tsize_t size;\n};\n\nstruct rtc_wkalrm;\n\nstruct rtc_param;\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n\tint (*param_get)(struct device *, struct rtc_param *);\n\tint (*param_set)(struct device *, struct rtc_param *);\n};\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tlong unsigned int set_offset_nsec;\n\tlong unsigned int features[1];\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttimeu64_t alarm_offset_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n};\n\nstruct rtc_param {\n\t__u64 param;\n\tunion {\n\t\t__u64 uvalue;\n\t\t__s64 svalue;\n\t\t__u64 ptr;\n\t};\n\t__u32 index;\n\t__u32 __pad;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nstruct rtm_dump_res_bucket_ctx;\n\nstruct rtm_dump_nexthop_bucket_data {\n\tstruct rtm_dump_res_bucket_ctx *ctx;\n\tstruct nh_dump_filter filter;\n};\n\nstruct rtm_dump_nh_ctx {\n\tu32 idx;\n};\n\nstruct rtm_dump_res_bucket_ctx {\n\tstruct rtm_dump_nh_ctx nh;\n\tu16 bucket_index;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *, struct netlink_ext_ack *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n};\n\nstruct rtnl_newlink_params;\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tstruct srcu_struct srcu;\n\tconst char *kind;\n\tsize_t priv_size;\n\tstruct net_device * (*alloc)(struct nlattr **, const char *, unsigned char, unsigned int, unsigned int);\n\tvoid (*setup)(struct net_device *);\n\tbool netns_refund;\n\tconst u16 peer_type;\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net_device *, struct rtnl_newlink_params *, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)(void);\n\tunsigned int (*get_num_rx_queues)(void);\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n\t__u64 rx_otherhost_dropped;\n};\n\nstruct rtnl_mdb_dump_ctx {\n\tlong int idx;\n};\n\nstruct rtnl_msg_handler {\n\tstruct module *owner;\n\tint protocol;\n\tint msgtype;\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tint flags;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct rtnl_nets {\n\tstruct net *net[3];\n\tunsigned char len;\n};\n\nstruct rtnl_newlink_params {\n\tstruct net *src_net;\n\tstruct net *link_net;\n\tstruct net *peer_net;\n\tstruct nlattr **tb;\n\tstruct nlattr **data;\n};\n\nstruct rtnl_newlink_tbs {\n\tstruct nlattr *tb[70];\n\tstruct nlattr *linkinfo[6];\n\tstruct nlattr *attr[51];\n\tstruct nlattr *slave_attr[45];\n};\n\nstruct rtnl_offload_xstats_request_used {\n\tbool request;\n\tbool used;\n};\n\nstruct rtnl_stats_dump_filters {\n\tu32 mask[6];\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct rwrt_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u32 last_lba;\n\t__u32 block_size;\n\t__u16 blocking;\n\t__u8 page_present: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tbool handoff_set;\n};\n\nstruct rx {\n\tstruct rx *next;\n\tstruct rx *prev;\n\tstruct sk_buff *skb;\n\tdma_addr_t dma_addr;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain *rd;\n};\n\nstruct value_name_pair;\n\nstruct sa_name_list {\n\tint opcode;\n\tconst struct value_name_pair *arr;\n\tint arr_sz;\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar saved_cmdlines[0];\n};\n\nstruct saved_syn {\n\tu32 mac_hdrlen;\n\tu32 network_hdrlen;\n\tu32 tcp_hdrlen;\n\tu8 data[0];\n};\n\nstruct sb_writers {\n\tshort unsigned int frozen;\n\tint freeze_kcount;\n\tint freeze_ucount;\n\tconst void *freeze_owner;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\nstruct sbitmap_word {\n\tlong unsigned int word;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int cleared;\n\traw_spinlock_t swap_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait_state {\n\twait_queue_head_t wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tint *proactive_swappiness;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int no_cache_trim_mode: 1;\n\tunsigned int cache_trim_mode_failed: 1;\n\tunsigned int proactive: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int memcg_full_walk: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\tunsigned int no_demotion: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\nstruct sch_frag_data {\n\tlong unsigned int dst;\n\tstruct qdisc_skb_cb cb;\n\t__be16 inner_protocol;\n\tu16 vlan_tci;\n\t__be16 vlan_proto;\n\tunsigned int l2_len;\n\tu8 l2_data[18];\n\tint (*xmit)(struct sk_buff *);\n\tlocal_lock_t bh_lock;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct sched_change_ctx;\n\ntypedef struct sched_change_ctx *class_sched_change_t;\n\nstruct sched_change_ctx {\n\tu64 prio;\n\tstruct task_struct *p;\n\tconst struct sched_class *class;\n\tint flags;\n\tbool queued;\n\tbool running;\n};\n\nstruct sched_class {\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tbool (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *);\n\tvoid (*wakeup_preempt)(struct rq *, struct task_struct *, int);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tstruct task_struct * (*pick_task)(struct rq *, struct rq_flags *);\n\tstruct task_struct * (*pick_next_task)(struct rq *, struct task_struct *, struct rq_flags *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*select_task_rq)(struct task_struct *, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, struct affinity_context *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tstruct rq * (*find_lock_rq)(struct task_struct *, struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switching_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switching_to)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tu64 (*get_prio)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, u64);\n\tvoid (*reweight_task)(struct rq *, struct task_struct *, const struct load_weight *);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *);\n};\n\nstruct sched_group;\n\nstruct sched_domain_shared;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tunsigned int imb_numa_nr;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tunsigned int newidle_call;\n\tunsigned int newidle_success;\n\tunsigned int newidle_ratio;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int last_decay_max_lb_cost;\n\tunsigned int lb_count[3];\n\tunsigned int lb_failed[3];\n\tunsigned int lb_balanced[3];\n\tunsigned int lb_imbalance_load[3];\n\tunsigned int lb_imbalance_util[3];\n\tunsigned int lb_imbalance_task[3];\n\tunsigned int lb_imbalance_misfit[3];\n\tunsigned int lb_gained[3];\n\tunsigned int lb_hot_gained[3];\n\tunsigned int lb_nobusyg[3];\n\tunsigned int lb_nobusyq[3];\n\tunsigned int alb_count;\n\tunsigned int alb_failed;\n\tunsigned int alb_pushed;\n\tunsigned int sbe_count;\n\tunsigned int sbe_balanced;\n\tunsigned int sbe_pushed;\n\tunsigned int sbf_count;\n\tunsigned int sbf_balanced;\n\tunsigned int sbf_pushed;\n\tunsigned int ttwu_wake_remote;\n\tunsigned int ttwu_move_affine;\n\tunsigned int ttwu_move_balance;\n\tchar *name;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n\tint nr_idle_scan;\n};\n\nstruct sched_domain_topology_level;\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(struct sched_domain_topology_level *, int);\n\ntypedef int (*sched_domain_flags_f)(void);\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint numa_level;\n\tstruct sd_data data;\n\tchar *name;\n};\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tu64 deadline;\n\tu64 min_vruntime;\n\tu64 min_slice;\n\tu64 max_slice;\n\tstruct list_head group_node;\n\tunsigned char on_rq;\n\tunsigned char sched_delayed;\n\tunsigned char rel_deadline;\n\tunsigned char custom_slice;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 prev_sum_exec_runtime;\n\tu64 vruntime;\n\ts64 vlag;\n\tu64 vprot;\n\tu64 slice;\n\tu64 nr_migrations;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n};\n\nstruct sched_statistics {\n\tu64 wait_start;\n\tu64 wait_max;\n\tu64 wait_count;\n\tu64 wait_sum;\n\tu64 iowait_count;\n\tu64 iowait_sum;\n\tu64 sleep_start;\n\tu64 sleep_max;\n\ts64 sum_sleep_runtime;\n\tu64 block_start;\n\tu64 block_max;\n\ts64 sum_block_runtime;\n\ts64 exec_max;\n\tu64 slice_max;\n\tu64 nr_migrations_cold;\n\tu64 nr_failed_migrations_affine;\n\tu64 nr_failed_migrations_running;\n\tu64 nr_failed_migrations_hot;\n\tu64 nr_forced_migrations;\n\tu64 nr_wakeups;\n\tu64 nr_wakeups_sync;\n\tu64 nr_wakeups_migrate;\n\tu64 nr_wakeups_local;\n\tu64 nr_wakeups_remote;\n\tu64 nr_wakeups_affine;\n\tu64 nr_wakeups_affine_attempts;\n\tu64 nr_wakeups_passive;\n\tu64 nr_wakeups_idle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sched_entity_stats {\n\tstruct sched_entity se;\n\tstruct sched_statistics stats;\n};\n\nstruct sched_ext_entity {\n\tstruct scx_sched *sched;\n\tstruct scx_dispatch_q *dsq;\n\tatomic_long_t ops_state;\n\tu64 ddsp_dsq_id;\n\tu64 ddsp_enq_flags;\n\tstruct scx_dsq_list_node dsq_list;\n\tstruct rb_node dsq_priq;\n\tu32 dsq_seq;\n\tu32 dsq_flags;\n\tu32 flags;\n\tu32 weight;\n\ts32 sticky_cpu;\n\ts32 holding_cpu;\n\ts32 selected_cpu;\n\tu32 kf_mask;\n\tstruct task_struct *kf_tasks[2];\n\tstruct list_head runnable_node;\n\tlong unsigned int runnable_at;\n\tu64 slice;\n\tu64 dsq_vtime;\n\tbool disallow;\n\tstruct cgroup *cgrp_moving_from;\n\tstruct list_head tasks_node;\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tunsigned int cores;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tint flags;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tint id;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_mm_cid {\n\tunsigned int active;\n\tunsigned int cid;\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\nstruct scm_fp_list;\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n\tu32 secid;\n};\n\nstruct unix_edge;\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int count_unix;\n\tshort int max;\n\tbool inflight;\n\tbool dead;\n\tstruct list_head vertices;\n\tstruct unix_edge *edges;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n\tlong unsigned int nr_unix_fds;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct scomp_alg {\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_acomp_streams streams;\n\tunion {\n\t\tstruct {\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct comp_alg_common calg;\n\t};\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tunion {\n\t\tvoid *src;\n\t\tlong unsigned int saddr;\n\t};\n};\n\nstruct scsi_cd {\n\tunsigned int capacity;\n\tstruct scsi_device *device;\n\tunsigned int vendor;\n\tlong unsigned int ms_offset;\n\tunsigned int writeable: 1;\n\tunsigned int use: 1;\n\tunsigned int xa_flag: 1;\n\tunsigned int readcd_known: 1;\n\tunsigned int readcd_cdda: 1;\n\tunsigned int media_present: 1;\n\tint tur_mismatch;\n\tbool tur_changed: 1;\n\tbool get_event_changed: 1;\n\tbool ignore_get_event: 1;\n\tstruct cdrom_device_info cdi;\n\tstruct mutex lock;\n\tstruct gendisk *disk;\n};\n\ntypedef struct scsi_cd Scsi_CD;\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tint budget_token;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tenum scsi_cmnd_submitter submitter;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tunsigned int resid_len;\n\tunsigned int sense_len;\n\tunsigned char *sense_buffer;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned int extra_len;\n\tunsigned char *host_scribble;\n\tint result;\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct scsi_vpd;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tstruct sbitmap budget_map;\n\tatomic_t device_blocked;\n\tatomic_t restarts;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tstruct scsi_vpd *vpd_pgb0;\n\tstruct scsi_vpd *vpd_pgb1;\n\tstruct scsi_vpd *vpd_pgb2;\n\tstruct scsi_vpd *vpd_pgb7;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int manage_system_start_stop: 1;\n\tunsigned int manage_runtime_start_stop: 1;\n\tunsigned int manage_shutdown: 1;\n\tunsigned int manage_restart: 1;\n\tunsigned int force_runtime_start_on_system_start: 1;\n\tunsigned int is_ata: 1;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int read_before_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int use_16_for_sync: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tunsigned int ignore_media_change: 1;\n\tunsigned int silence_suspend: 1;\n\tunsigned int no_vpd_size: 1;\n\tunsigned int cdl_supported: 1;\n\tunsigned int cdl_enable: 1;\n\tunsigned int queue_stopped;\n\tbool offline_already;\n\tatomic_t ua_new_media_ctr;\n\tatomic_t ua_por_ctr;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tatomic_t iotmo_cnt;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tstruct bsg_device *bsg_dev;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tenum scsi_disposition (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct scsi_dh_blist {\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *driver;\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_device *device;\n\tstruct device disk_dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tsector_t capacity;\n\tint max_retries;\n\tu32 min_xfer_blocks;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 max_atomic;\n\tu32 atomic_alignment;\n\tu32 atomic_granularity;\n\tu32 max_atomic_with_boundary;\n\tu32 max_atomic_boundary;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu16 permanent_stream_count;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tu8 nr_actuators;\n\tbool suspended;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n\tunsigned int rscs: 1;\n\tunsigned int use_atomic_write_boundary: 1;\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tint (*probe)(struct scsi_device *);\n\tvoid (*remove)(struct scsi_device *);\n\tvoid (*shutdown)(struct scsi_device *);\n\tint (*resume)(struct device *);\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char cmnd[32];\n\tstruct scsi_data_buffer sdb;\n\tstruct scatterlist sense_sgl;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nstruct scsi_failures;\n\nstruct scsi_exec_args {\n\tunsigned char *sense;\n\tunsigned int sense_len;\n\tstruct scsi_sense_hdr *sshdr;\n\tblk_mq_req_flags_t req_flags;\n\tint scmd_flags;\n\tint *resid;\n\tstruct scsi_failures *failures;\n};\n\nstruct scsi_failure {\n\tint result;\n\tu8 sense;\n\tu8 asc;\n\tu8 ascq;\n\ts8 allowed;\n\ts8 retries;\n};\n\nstruct scsi_failures {\n\tint total_allowed;\n\tint total_retries;\n\tstruct scsi_failure *failure_definitions;\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *);\n\tvoid *priv;\n};\n\nstruct scsi_host_template {\n\tunsigned int cmd_size;\n\tenum scsi_qc_status (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tenum scsi_qc_status (*queue_reserved_command)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*sdev_init)(struct scsi_device *);\n\tint (*sdev_configure)(struct scsi_device *, struct queue_limits *);\n\tvoid (*sdev_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tvoid (*map_queues)(struct Scsi_Host *);\n\tint (*mq_poll)(struct Scsi_Host *, unsigned int);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct gendisk *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum scsi_timeout_action (*eh_timed_out)(struct scsi_cmnd *);\n\tbool (*eh_should_retry_cmd)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tint can_queue;\n\tint nr_reserved_cmds;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int dma_alignment;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tbool tag_alloc_policy_rr: 1;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int host_tagset: 1;\n\tunsigned int queuecommand_may_block: 1;\n\tunsigned int max_host_blocked;\n\tconst struct attribute_group **shost_groups;\n\tconst struct attribute_group **sdev_groups;\n\tu64 vendor_id;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\nstruct scsi_io_group_descriptor {\n\tu8 ic_enable: 1;\n\tu8 cs_enble: 1;\n\tu8 st_enble: 1;\n\tu8 reserved1: 3;\n\tu8 io_advice_hints_mode: 2;\n\tu8 reserved2[3];\n\tu8 lbm_descriptor_type: 4;\n\tu8 rlbsr: 2;\n\tu8 reserved3: 1;\n\tu8 acdlu: 1;\n\tu8 params[2];\n\tu8 reserved4;\n\tu8 reserved5[8];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_proc_entry {\n\tstruct list_head entry;\n\tconst struct scsi_host_template *sht;\n\tstruct proc_dir_entry *proc_dir;\n\tunsigned int present;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct scsi_stream_status {\n\tu8 reserved1: 7;\n\tu8 perm: 1;\n\tu8 reserved2;\n\t__be16 stream_identifier;\n\tu8 rel_lifetime: 6;\n\tu8 reserved3: 2;\n\tu8 reserved4[3];\n};\n\nstruct scsi_stream_status_header {\n\t__be32 len;\n\tu16 reserved;\n\t__be16 number_of_open_streams;\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct sctp_paramhdr {\n\t__be16 type;\n\t__be16 length;\n};\n\nstruct sctp_adaptation_ind_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 adaptation_ind;\n};\n\nstruct sctp_addip_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 crr_id;\n};\n\nstruct sctp_addiphdr {\n\t__be32 serial;\n};\n\nstruct sockaddr_inet {\n\tshort unsigned int sa_family;\n\tchar sa_data[26];\n};\n\nunion sctp_addr {\n\tstruct sockaddr_inet sa;\n\tstruct sockaddr_in v4;\n\tstruct sockaddr_in6 v6;\n};\n\nstruct sctp_ipv4addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in_addr addr;\n};\n\nstruct sctp_ipv6addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in6_addr addr;\n};\n\nunion sctp_addr_param {\n\tstruct sctp_paramhdr p;\n\tstruct sctp_ipv4addr_param v4;\n\tstruct sctp_ipv6addr_param v6;\n};\n\nstruct sctp_transport;\n\nstruct sctp_sock;\n\nstruct sctp_af {\n\tint (*sctp_xmit)(struct sk_buff *, struct sctp_transport *);\n\tint (*setsockopt)(struct sock *, int, int, sockptr_t, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*get_dst)(struct sctp_transport *, union sctp_addr *, struct flowi *, struct sock *);\n\tvoid (*get_saddr)(struct sctp_sock *, struct sctp_transport *, struct flowi *);\n\tvoid (*copy_addrlist)(struct list_head *, struct net_device *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *);\n\tvoid (*addr_copy)(union sctp_addr *, union sctp_addr *);\n\tvoid (*from_skb)(union sctp_addr *, struct sk_buff *, int);\n\tvoid (*from_sk)(union sctp_addr *, struct sock *);\n\tbool (*from_addr_param)(union sctp_addr *, union sctp_addr_param *, __be16, int);\n\tint (*to_addr_param)(const union sctp_addr *, union sctp_addr_param *);\n\tint (*addr_valid)(union sctp_addr *, struct sctp_sock *, const struct sk_buff *);\n\tenum sctp_scope (*scope)(union sctp_addr *);\n\tvoid (*inaddr_any)(union sctp_addr *, __be16);\n\tint (*is_any)(const union sctp_addr *);\n\tint (*available)(union sctp_addr *, struct sctp_sock *);\n\tint (*skb_iif)(const struct sk_buff *);\n\tint (*skb_sdif)(const struct sk_buff *);\n\tint (*is_ce)(const struct sk_buff *);\n\tvoid (*seq_dump_addr)(struct seq_file *, union sctp_addr *);\n\tvoid (*ecn_capable)(struct sock *);\n\t__u16 net_header_len;\n\tint sockaddr_len;\n\tint (*ip_options_len)(struct sock *);\n\tsa_family_t sa_family;\n\tstruct list_head list;\n};\n\nstruct sctp_chunk;\n\nstruct sctp_inq {\n\tstruct list_head in_chunk_list;\n\tstruct sctp_chunk *in_progress;\n\tstruct work_struct immediate;\n};\n\nstruct sctp_bind_addr {\n\t__u16 port;\n\tstruct list_head address_list;\n};\n\nstruct sctp_ep_common {\n\tenum sctp_endpoint_type type;\n\trefcount_t refcnt;\n\tbool dead;\n\tstruct sock *sk;\n\tstruct net *net;\n\tstruct sctp_inq inqueue;\n\tstruct sctp_bind_addr bind_addr;\n};\n\nstruct sctp_cookie {\n\t__u32 my_vtag;\n\t__u32 peer_vtag;\n\t__u32 my_ttag;\n\t__u32 peer_ttag;\n\tktime_t expiration;\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u32 initial_tsn;\n\tunion sctp_addr peer_addr;\n\t__u16 my_port;\n\t__u8 prsctp_capable;\n\t__u8 padding;\n\t__u32 adaptation_ind;\n\t__u8 auth_random[36];\n\t__u8 auth_hmacs[10];\n\t__u8 auth_chunks[20];\n\t__u32 raw_addr_list_len;\n};\n\nstruct sctp_tsnmap {\n\tlong unsigned int *tsn_map;\n\t__u32 base_tsn;\n\t__u32 cumulative_tsn_ack_point;\n\t__u32 max_tsn_seen;\n\t__u16 len;\n\t__u16 pending_data;\n\t__u16 num_dup_tsns;\n\t__be32 dup_tsns[16];\n};\n\nstruct sctp_inithdr_host {\n\t__u32 init_tag;\n\t__u32 a_rwnd;\n\t__u16 num_outbound_streams;\n\t__u16 num_inbound_streams;\n\t__u32 initial_tsn;\n};\n\nstruct sctp_stream_out_ext;\n\nstruct sctp_stream_out {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\tstruct sctp_stream_out_ext *ext;\n\t__u8 state;\n};\n\nstruct sctp_stream_in {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\t__u32 fsn;\n\t__u32 fsn_uo;\n\tchar pd_mode;\n\tchar pd_mode_uo;\n};\n\nstruct sctp_stream_interleave;\n\nstruct sctp_stream {\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_out type[0];\n\t} out;\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_in type[0];\n\t} in;\n\t__u16 outcnt;\n\t__u16 incnt;\n\tstruct sctp_stream_out *out_curr;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t\tstruct sctp_stream_out_ext *rr_next;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t};\n\t};\n\tstruct sctp_stream_interleave *si;\n};\n\nstruct sctp_sched_ops;\n\nstruct sctp_association;\n\nstruct sctp_outq {\n\tstruct sctp_association *asoc;\n\tstruct list_head out_chunk_list;\n\tconst struct sctp_sched_ops *sched;\n\tunsigned int out_qlen;\n\tunsigned int error;\n\tstruct list_head control_chunk_list;\n\tstruct list_head sacked;\n\tstruct list_head retransmit;\n\tstruct list_head abandoned;\n\t__u32 outstanding_bytes;\n\tchar fast_rtx;\n\tchar cork;\n};\n\nstruct sctp_ulpq {\n\tchar pd_mode;\n\tstruct sctp_association *asoc;\n\tstruct sk_buff_head reasm;\n\tstruct sk_buff_head reasm_uo;\n\tstruct sk_buff_head lobby;\n};\n\nstruct sctp_priv_assoc_stats {\n\tstruct __kernel_sockaddr_storage obs_rto_ipaddr;\n\t__u64 max_obs_rto;\n\t__u64 isacks;\n\t__u64 osacks;\n\t__u64 opackets;\n\t__u64 ipackets;\n\t__u64 rtxchunks;\n\t__u64 outofseqtsns;\n\t__u64 idupchunks;\n\t__u64 gapcnt;\n\t__u64 ouodchunks;\n\t__u64 iuodchunks;\n\t__u64 oodchunks;\n\t__u64 iodchunks;\n\t__u64 octrlchunks;\n\t__u64 ictrlchunks;\n};\n\nstruct sctp_endpoint;\n\nstruct sctp_random_param;\n\nstruct sctp_chunks_param;\n\nstruct sctp_hmac_algo_param;\n\nstruct sctp_auth_bytes;\n\nstruct sctp_shared_key;\n\nstruct sctp_association {\n\tstruct sctp_ep_common base;\n\tstruct list_head asocs;\n\tsctp_assoc_t assoc_id;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_cookie c;\n\tstruct {\n\t\tstruct list_head transport_addr_list;\n\t\t__u32 rwnd;\n\t\t__u16 transport_count;\n\t\t__u16 port;\n\t\tstruct sctp_transport *primary_path;\n\t\tunion sctp_addr primary_addr;\n\t\tstruct sctp_transport *active_path;\n\t\tstruct sctp_transport *retran_path;\n\t\tstruct sctp_transport *last_sent_to;\n\t\tstruct sctp_transport *last_data_from;\n\t\tstruct sctp_tsnmap tsn_map;\n\t\t__be16 addip_disabled_mask;\n\t\t__u16 ecn_capable: 1;\n\t\t__u16 ipv4_address: 1;\n\t\t__u16 ipv6_address: 1;\n\t\t__u16 asconf_capable: 1;\n\t\t__u16 prsctp_capable: 1;\n\t\t__u16 reconf_capable: 1;\n\t\t__u16 intl_capable: 1;\n\t\t__u16 auth_capable: 1;\n\t\t__u16 sack_needed: 1;\n\t\t__u16 sack_generation: 1;\n\t\t__u16 zero_window_announced: 1;\n\t\t__u32 sack_cnt;\n\t\t__u32 adaptation_ind;\n\t\tstruct sctp_inithdr_host i;\n\t\tvoid *cookie;\n\t\tint cookie_len;\n\t\t__u32 addip_serial;\n\t\tstruct sctp_random_param *peer_random;\n\t\tstruct sctp_chunks_param *peer_chunks;\n\t\tstruct sctp_hmac_algo_param *peer_hmacs;\n\t} peer;\n\tenum sctp_state state;\n\tint overall_error_count;\n\tktime_t cookie_life;\n\tlong unsigned int rto_initial;\n\tlong unsigned int rto_max;\n\tlong unsigned int rto_min;\n\tint max_burst;\n\tint max_retrans;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u16 max_init_attempts;\n\t__u16 init_retries;\n\tlong unsigned int max_init_timeo;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u8 pmtu_pending;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\t__u32 sackfreq;\n\tlong unsigned int sackdelay;\n\tlong unsigned int timeouts[12];\n\tstruct timer_list timers[12];\n\tstruct sctp_transport *shutdown_last_sent_to;\n\tstruct sctp_transport *init_last_sent_to;\n\tint shutdown_retries;\n\t__u32 next_tsn;\n\t__u32 ctsn_ack_point;\n\t__u32 adv_peer_ack_point;\n\t__u32 highest_sacked;\n\t__u32 fast_recovery_exit;\n\t__u8 fast_recovery;\n\t__u16 unack_data;\n\t__u32 rtx_data_chunks;\n\t__u32 rwnd;\n\t__u32 a_rwnd;\n\t__u32 rwnd_over;\n\t__u32 rwnd_press;\n\tint sndbuf_used;\n\tatomic_t rmem_alloc;\n\twait_queue_head_t wait;\n\t__u32 frag_point;\n\t__u32 user_frag;\n\tint init_err_counter;\n\tint init_cycle;\n\t__u16 default_stream;\n\t__u16 default_flags;\n\t__u32 default_ppid;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tstruct sctp_stream stream;\n\tstruct sctp_outq outqueue;\n\tstruct sctp_ulpq ulpq;\n\t__u32 last_ecne_tsn;\n\t__u32 last_cwr_tsn;\n\tint numduptsns;\n\tstruct sctp_chunk *addip_last_asconf;\n\tstruct list_head asconf_ack_list;\n\tstruct list_head addip_chunk_list;\n\t__u32 addip_serial;\n\tint src_out_of_asoc_ok;\n\tunion sctp_addr *asconf_addr_del_pending;\n\tstruct sctp_transport *new_transport;\n\tstruct list_head endpoint_shared_keys;\n\tstruct sctp_auth_bytes *asoc_shared_key;\n\tstruct sctp_shared_key *shkey;\n\t__u16 default_hmac_id;\n\t__u16 active_key_id;\n\t__u8 need_ecne: 1;\n\t__u8 temp: 1;\n\t__u8 pf_expose: 2;\n\t__u8 force_delay: 1;\n\t__u8 strreset_enable;\n\t__u8 strreset_outstanding;\n\t__u32 strreset_outseq;\n\t__u32 strreset_inseq;\n\t__u32 strreset_result[2];\n\tstruct sctp_chunk *strreset_chunk;\n\tstruct sctp_priv_assoc_stats stats;\n\tint sent_cnt_removable;\n\t__u16 subscribe;\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tu32 secid;\n\tu32 peer_secid;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_assocparams {\n\tsctp_assoc_t sasoc_assoc_id;\n\t__u16 sasoc_asocmaxrxt;\n\t__u16 sasoc_number_peer_destinations;\n\t__u32 sasoc_peer_rwnd;\n\t__u32 sasoc_local_rwnd;\n\t__u32 sasoc_cookie_life;\n};\n\nstruct sctp_auth_bytes {\n\trefcount_t refcnt;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct sctp_authhdr {\n\t__be16 shkey_id;\n\t__be16 hmac_id;\n};\n\nstruct sctp_bind_bucket {\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct hlist_node node;\n\tstruct hlist_head owner;\n\tstruct net *net;\n};\n\nstruct sctp_cookie_preserve_param;\n\nstruct sctp_hostname_param;\n\nstruct sctp_cookie_param;\n\nstruct sctp_supported_addrs_param;\n\nstruct sctp_supported_ext_param;\n\nunion sctp_params {\n\tvoid *v;\n\tstruct sctp_paramhdr *p;\n\tstruct sctp_cookie_preserve_param *life;\n\tstruct sctp_hostname_param *dns;\n\tstruct sctp_cookie_param *cookie;\n\tstruct sctp_supported_addrs_param *sat;\n\tstruct sctp_ipv4addr_param *v4;\n\tstruct sctp_ipv6addr_param *v6;\n\tunion sctp_addr_param *addr;\n\tstruct sctp_adaptation_ind_param *aind;\n\tstruct sctp_supported_ext_param *ext;\n\tstruct sctp_random_param *random;\n\tstruct sctp_chunks_param *chunks;\n\tstruct sctp_hmac_algo_param *hmac_algo;\n\tstruct sctp_addip_param *addip;\n};\n\nstruct sctp_sndrcvinfo {\n\t__u16 sinfo_stream;\n\t__u16 sinfo_ssn;\n\t__u16 sinfo_flags;\n\t__u32 sinfo_ppid;\n\t__u32 sinfo_context;\n\t__u32 sinfo_timetolive;\n\t__u32 sinfo_tsn;\n\t__u32 sinfo_cumtsn;\n\tsctp_assoc_t sinfo_assoc_id;\n};\n\nstruct sctp_datahdr;\n\nstruct sctp_inithdr;\n\nstruct sctp_sackhdr;\n\nstruct sctp_heartbeathdr;\n\nstruct sctp_sender_hb_info;\n\nstruct sctp_shutdownhdr;\n\nstruct sctp_signed_cookie;\n\nstruct sctp_ecnehdr;\n\nstruct sctp_cwrhdr;\n\nstruct sctp_errhdr;\n\nstruct sctp_fwdtsn_hdr;\n\nstruct sctp_idatahdr;\n\nstruct sctp_ifwdtsn_hdr;\n\nstruct sctp_chunkhdr;\n\nstruct sctphdr;\n\nstruct sctp_datamsg;\n\nstruct sctp_chunk {\n\tstruct list_head list;\n\trefcount_t refcnt;\n\tint sent_count;\n\tunion {\n\t\tstruct list_head transmitted_list;\n\t\tstruct list_head stream_list;\n\t};\n\tstruct list_head frag_list;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct sk_buff *head_skb;\n\t\tstruct sctp_shared_key *shkey;\n\t};\n\tunion sctp_params param_hdr;\n\tunion {\n\t\t__u8 *v;\n\t\tstruct sctp_datahdr *data_hdr;\n\t\tstruct sctp_inithdr *init_hdr;\n\t\tstruct sctp_sackhdr *sack_hdr;\n\t\tstruct sctp_heartbeathdr *hb_hdr;\n\t\tstruct sctp_sender_hb_info *hbs_hdr;\n\t\tstruct sctp_shutdownhdr *shutdown_hdr;\n\t\tstruct sctp_signed_cookie *cookie_hdr;\n\t\tstruct sctp_ecnehdr *ecne_hdr;\n\t\tstruct sctp_cwrhdr *ecn_cwr_hdr;\n\t\tstruct sctp_errhdr *err_hdr;\n\t\tstruct sctp_addiphdr *addip_hdr;\n\t\tstruct sctp_fwdtsn_hdr *fwdtsn_hdr;\n\t\tstruct sctp_authhdr *auth_hdr;\n\t\tstruct sctp_idatahdr *idata_hdr;\n\t\tstruct sctp_ifwdtsn_hdr *ifwdtsn_hdr;\n\t} subh;\n\t__u8 *chunk_end;\n\tstruct sctp_chunkhdr *chunk_hdr;\n\tstruct sctphdr *sctp_hdr;\n\tstruct sctp_sndrcvinfo sinfo;\n\tstruct sctp_association *asoc;\n\tstruct sctp_ep_common *rcvr;\n\tlong unsigned int sent_at;\n\tunion sctp_addr source;\n\tunion sctp_addr dest;\n\tstruct sctp_datamsg *msg;\n\tstruct sctp_transport *transport;\n\tstruct sk_buff *auth_chunk;\n\t__u16 rtt_in_progress: 1;\n\t__u16 has_tsn: 1;\n\t__u16 has_ssn: 1;\n\t__u16 singleton: 1;\n\t__u16 end_of_packet: 1;\n\t__u16 ecn_ce_done: 1;\n\t__u16 pdiscard: 1;\n\t__u16 tsn_gap_acked: 1;\n\t__u16 data_accepted: 1;\n\t__u16 auth: 1;\n\t__u16 has_asconf: 1;\n\t__u16 pmtu_probe: 1;\n\t__u16 tsn_missing_report: 2;\n\t__u16 fast_retransmit: 2;\n};\n\nstruct sctp_chunkhdr {\n\t__u8 type;\n\t__u8 flags;\n\t__be16 length;\n};\n\nstruct sctp_chunks_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_cookie_param {\n\tstruct sctp_paramhdr p;\n\t__u8 body[0];\n};\n\nstruct sctp_cookie_preserve_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 lifespan_increment;\n};\n\nstruct sctp_cwrhdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_datahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 ssn;\n\t__u32 ppid;\n};\n\nstruct sctp_datamsg {\n\tstruct list_head chunks;\n\trefcount_t refcnt;\n\tlong unsigned int expires_at;\n\tint send_error;\n\tu8 send_failed: 1;\n\tu8 can_delay: 1;\n\tu8 abandoned: 1;\n};\n\nstruct sctp_ecnehdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_endpoint {\n\tstruct sctp_ep_common base;\n\tstruct hlist_node node;\n\tint hashent;\n\tstruct list_head asocs;\n\tstruct hmac_sha256_key cookie_auth_key;\n\t__u32 sndbuf_policy;\n\t__u32 rcvbuf_policy;\n\tstruct sctp_hmac_algo_param *auth_hmacs_list;\n\tstruct sctp_chunks_param *auth_chunk_list;\n\tstruct list_head endpoint_shared_keys;\n\t__u16 active_key_id;\n\t__u8 ecn_enable: 1;\n\t__u8 auth_enable: 1;\n\t__u8 intl_enable: 1;\n\t__u8 prsctp_enable: 1;\n\t__u8 asconf_enable: 1;\n\t__u8 reconf_enable: 1;\n\t__u8 strreset_enable;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_errhdr {\n\t__be16 cause;\n\t__be16 length;\n};\n\nstruct sctp_fwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_heartbeathdr {\n\tstruct sctp_paramhdr info;\n};\n\nstruct sctp_hmac_algo_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 hmac_ids[0];\n};\n\nstruct sctp_hostname_param {\n\tstruct sctp_paramhdr param_hdr;\n\tuint8_t hostname[0];\n};\n\nstruct sctp_idatahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 reserved;\n\t__be32 mid;\n\tunion {\n\t\t__u32 ppid;\n\t\t__be32 fsn;\n\t};\n};\n\nstruct sctp_ifwdtsn_hdr {\n\t__be32 new_cum_tsn;\n};\n\nstruct sctp_inithdr {\n\t__be32 init_tag;\n\t__be32 a_rwnd;\n\t__be16 num_outbound_streams;\n\t__be16 num_inbound_streams;\n\t__be32 initial_tsn;\n};\n\nstruct sctp_initmsg {\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u16 sinit_max_attempts;\n\t__u16 sinit_max_init_timeo;\n};\n\nstruct sctp_packet {\n\t__u16 source_port;\n\t__u16 destination_port;\n\t__u32 vtag;\n\tstruct list_head chunk_list;\n\tsize_t overhead;\n\tsize_t size;\n\tsize_t max_size;\n\tstruct sctp_transport *transport;\n\tstruct sctp_chunk *auth;\n\tu8 has_cookie_echo: 1;\n\tu8 has_sack: 1;\n\tu8 has_auth: 1;\n\tu8 has_data: 1;\n\tu8 ipfragok: 1;\n};\n\nstruct sctp_paddrparams {\n\tsctp_assoc_t spp_assoc_id;\n\tstruct __kernel_sockaddr_storage spp_address;\n\t__u32 spp_hbinterval;\n\t__u16 spp_pathmaxrxt;\n\t__u32 spp_pathmtu;\n\t__u32 spp_sackdelay;\n\t__u32 spp_flags;\n\t__u32 spp_ipv6_flowlabel;\n\t__u8 spp_dscp;\n\tint: 0;\n} __attribute__((packed));\n\nstruct sctp_ulpevent;\n\nstruct sctp_pf {\n\tvoid (*event_msgname)(struct sctp_ulpevent *, char *, int *);\n\tvoid (*skb_msgname)(struct sk_buff *, char *, int *);\n\tint (*af_supported)(sa_family_t, struct sctp_sock *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *, struct sctp_sock *);\n\tint (*bind_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*send_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*supported_addrs)(const struct sctp_sock *, __be16 *);\n\tint (*addr_to_user)(struct sctp_sock *, union sctp_addr *);\n\tvoid (*to_sk_saddr)(union sctp_addr *, struct sock *);\n\tvoid (*to_sk_daddr)(union sctp_addr *, struct sock *);\n\tvoid (*copy_ip_options)(struct sock *, struct sock *);\n\tstruct sctp_af *af;\n};\n\nstruct sctp_random_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 random_val[0];\n};\n\nstruct sctp_rtoinfo {\n\tsctp_assoc_t srto_assoc_id;\n\t__u32 srto_initial;\n\t__u32 srto_max;\n\t__u32 srto_min;\n};\n\nstruct sctp_sackhdr {\n\t__be32 cum_tsn_ack;\n\t__be32 a_rwnd;\n\t__be16 num_gap_ack_blocks;\n\t__be16 num_dup_tsns;\n};\n\nstruct sctp_sender_hb_info {\n\tstruct sctp_paramhdr param_hdr;\n\tunion sctp_addr daddr;\n\tlong unsigned int sent_at;\n\t__u64 hb_nonce;\n\t__u32 probe_size;\n};\n\nstruct sctp_shared_key {\n\tstruct list_head key_list;\n\tstruct sctp_auth_bytes *key;\n\trefcount_t refcnt;\n\t__u16 key_id;\n\t__u8 deactivated;\n};\n\nstruct sctp_shutdownhdr {\n\t__be32 cum_tsn_ack;\n};\n\nstruct sctp_signed_cookie {\n\t__u8 mac[32];\n\t__u32 __pad;\n\tstruct sctp_cookie c;\n} __attribute__((packed));\n\nstruct sctp_sock {\n\tstruct inet_sock inet;\n\tenum sctp_socket_type type;\n\tstruct sctp_pf *pf;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_bind_bucket *bind_hash;\n\t__u16 default_stream;\n\t__u32 default_ppid;\n\t__u16 default_flags;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tint max_burst;\n\t__u32 hbinterval;\n\t__u32 probe_interval;\n\t__be16 udp_port;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 sackdelay;\n\t__u32 sackfreq;\n\t__u32 param_flags;\n\t__u32 default_ss;\n\tstruct sctp_rtoinfo rtoinfo;\n\tstruct sctp_paddrparams paddrparam;\n\tstruct sctp_assocparams assocparams;\n\t__u16 subscribe;\n\tstruct sctp_initmsg initmsg;\n\tint user_frag;\n\t__u32 autoclose;\n\t__u32 adaptation_ind;\n\t__u32 pd_point;\n\t__u16 nodelay: 1;\n\t__u16 pf_expose: 2;\n\t__u16 reuse: 1;\n\t__u16 disable_fragments: 1;\n\t__u16 v4mapped: 1;\n\t__u16 frag_interleave: 1;\n\t__u16 recvrcvinfo: 1;\n\t__u16 recvnxtinfo: 1;\n\t__u16 data_ready_signalled: 1;\n\t__u16 cookie_auth_enable: 1;\n\tatomic_t pd_mode;\n\tstruct sk_buff_head pd_lobby;\n\tstruct list_head auto_asconf_list;\n\tint do_auto_asconf;\n};\n\nstruct sctp_stream_interleave {\n\t__u16 data_chunk_len;\n\t__u16 ftsn_chunk_len;\n\tstruct sctp_chunk * (*make_datafrag)(const struct sctp_association *, const struct sctp_sndrcvinfo *, int, __u8, gfp_t);\n\tvoid (*assign_number)(struct sctp_chunk *);\n\tbool (*validate_data)(struct sctp_chunk *);\n\tint (*ulpevent_data)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tint (*enqueue_event)(struct sctp_ulpq *, struct sctp_ulpevent *);\n\tvoid (*renege_events)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tvoid (*start_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*abort_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*generate_ftsn)(struct sctp_outq *, __u32);\n\tbool (*validate_ftsn)(struct sctp_chunk *);\n\tvoid (*report_ftsn)(struct sctp_ulpq *, __u32);\n\tvoid (*handle_ftsn)(struct sctp_ulpq *, struct sctp_chunk *);\n};\n\nstruct sctp_stream_priorities;\n\nstruct sctp_stream_out_ext {\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tstruct list_head outq;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t\tstruct sctp_stream_priorities *prio_head;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head fc_list;\n\t\t\t__u32 fc_length;\n\t\t\t__u16 fc_weight;\n\t\t};\n\t};\n};\n\nstruct sctp_stream_priorities {\n\tstruct list_head prio_sched;\n\tstruct list_head active;\n\tstruct sctp_stream_out_ext *next;\n\t__u16 prio;\n\t__u16 users;\n};\n\nstruct sctp_supported_addrs_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 types[0];\n};\n\nstruct sctp_supported_ext_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_transport {\n\tstruct list_head transports;\n\tstruct rhlist_head node;\n\trefcount_t refcnt;\n\t__u32 dead: 1;\n\t__u32 rto_pending: 1;\n\t__u32 hb_sent: 1;\n\t__u32 pmtu_pending: 1;\n\t__u32 dst_pending_confirm: 1;\n\t__u32 sack_generation: 1;\n\tu32 dst_cookie;\n\tstruct flowi fl;\n\tunion sctp_addr ipaddr;\n\tstruct sctp_af *af_specific;\n\tstruct sctp_association *asoc;\n\tlong unsigned int rto;\n\t__u32 rtt;\n\t__u32 rttvar;\n\t__u32 srtt;\n\t__u32 cwnd;\n\t__u32 ssthresh;\n\t__u32 partial_bytes_acked;\n\t__u32 flight_size;\n\t__u32 burst_limited;\n\tstruct dst_entry *dst;\n\tunion sctp_addr saddr;\n\tlong unsigned int hbinterval;\n\tlong unsigned int probe_interval;\n\tlong unsigned int sackdelay;\n\t__u32 sackfreq;\n\tatomic_t mtu_info;\n\tktime_t last_time_heard;\n\tlong unsigned int last_time_sent;\n\tlong unsigned int last_time_ecne_reduced;\n\t__be16 encap_port;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\tint init_sent_count;\n\tint state;\n\tshort unsigned int error_count;\n\tstruct timer_list T3_rtx_timer;\n\tstruct timer_list hb_timer;\n\tstruct timer_list proto_unreach_timer;\n\tstruct timer_list reconf_timer;\n\tstruct timer_list probe_timer;\n\tstruct list_head transmitted;\n\tstruct sctp_packet packet;\n\tstruct list_head send_ready;\n\tstruct {\n\t\t__u32 next_tsn_at_change;\n\t\tchar changeover_active;\n\t\tchar cycling_changeover;\n\t\tchar cacc_saw_newack;\n\t} cacc;\n\tstruct {\n\t\t__u16 pmtu;\n\t\t__u16 probe_size;\n\t\t__u16 probe_high;\n\t\t__u8 probe_count;\n\t\t__u8 state;\n\t} pl;\n\t__u64 hb_nonce;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_ulpevent {\n\tstruct sctp_association *asoc;\n\tstruct sctp_chunk *chunk;\n\tunsigned int rmem_len;\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\tunion {\n\t\t__u32 ppid;\n\t\t__u32 fsn;\n\t};\n\t__u32 tsn;\n\t__u32 cumtsn;\n\t__u16 stream;\n\t__u16 flags;\n\t__u16 msg_flags;\n} __attribute__((packed));\n\nstruct sctphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 vtag;\n\t__le32 checksum;\n};\n\nstruct scx_bpf_dsq_insert_vtime_args {\n\tu64 dsq_id;\n\tu64 slice;\n\tu64 vtime;\n\tu64 enq_flags;\n};\n\nstruct scx_bpf_select_cpu_and_args {\n\ts32 prev_cpu;\n\tu64 wake_flags;\n\tu64 flags;\n};\n\nstruct scx_bstr_buf {\n\tu64 data[12];\n\tchar line[1024];\n};\n\nstruct scx_cgroup_init_args {\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n};\n\nstruct scx_cpu_acquire_args {};\n\nstruct scx_cpu_release_args {\n\tenum scx_cpu_preempt_reason reason;\n\tstruct task_struct *task;\n};\n\nstruct scx_deferred_reenq_local {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_deferred_reenq_user {\n\tstruct list_head node;\n\tu64 flags;\n};\n\nstruct scx_dsp_buf_ent {\n\tstruct task_struct *task;\n\tlong unsigned int qseq;\n\tu64 dsq_id;\n\tu64 enq_flags;\n};\n\nstruct scx_dsp_ctx {\n\tstruct rq *rq;\n\tu32 cursor;\n\tu32 nr_tasks;\n\tstruct scx_dsp_buf_ent buf[0];\n};\n\nstruct scx_dsq_pcpu {\n\tstruct scx_dispatch_q *dsq;\n\tstruct scx_deferred_reenq_user deferred_reenq_user;\n};\n\nstruct scx_dump_ctx {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tconst char *reason;\n\tu64 at_ns;\n\tu64 at_jiffies;\n};\n\nstruct scx_dump_data {\n\ts32 cpu;\n\tbool first;\n\ts32 cursor;\n\tstruct seq_buf *s;\n\tconst char *prefix;\n\tstruct scx_bstr_buf buf;\n};\n\nstruct scx_enable_cmd {\n\tstruct kthread_work work;\n\tstruct sched_ext_ops *ops;\n\tint ret;\n};\n\nstruct scx_event_stats {\n\ts64 SCX_EV_SELECT_CPU_FALLBACK;\n\ts64 SCX_EV_DISPATCH_LOCAL_DSQ_OFFLINE;\n\ts64 SCX_EV_DISPATCH_KEEP_LAST;\n\ts64 SCX_EV_ENQ_SKIP_EXITING;\n\ts64 SCX_EV_ENQ_SKIP_MIGRATION_DISABLED;\n\ts64 SCX_EV_REFILL_SLICE_DFL;\n\ts64 SCX_EV_BYPASS_DURATION;\n\ts64 SCX_EV_BYPASS_DISPATCH;\n\ts64 SCX_EV_BYPASS_ACTIVATE;\n\ts64 SCX_EV_INSERT_NOT_OWNED;\n\ts64 SCX_EV_SUB_BYPASS_DISPATCH;\n};\n\nstruct scx_exit_info {\n\tenum scx_exit_kind kind;\n\ts64 exit_code;\n\tu64 flags;\n\tconst char *reason;\n\tlong unsigned int *bt;\n\tu32 bt_len;\n\tchar *msg;\n\tchar *dump;\n};\n\nstruct scx_exit_task_args {\n\tbool cancelled;\n};\n\nstruct scx_idle_cpus {\n\tcpumask_var_t cpu;\n\tcpumask_var_t smt;\n};\n\nstruct scx_init_task_args {\n\tbool fork;\n\tstruct cgroup *cgroup;\n};\n\nstruct scx_kick_syncs {\n\tstruct callback_head rcu;\n\tlong unsigned int syncs[0];\n};\n\nstruct scx_sched_pnode;\n\nstruct scx_sched_pcpu;\n\nstruct scx_sched {\n\tstruct sched_ext_ops ops;\n\tlong unsigned int has_op[1];\n\tstruct rhashtable dsq_hash;\n\tstruct scx_sched_pnode **pnode;\n\tstruct scx_sched_pcpu *pcpu;\n\tu64 slice_dfl;\n\tu64 bypass_timestamp;\n\ts32 bypass_depth;\n\tlong unsigned int bypass_dsp_claim;\n\tatomic_t bypass_dsp_enable_depth;\n\tbool aborting;\n\tu32 dsp_max_batch;\n\ts32 level;\n\tbool warned_zero_slice: 1;\n\tbool warned_deprecated_rq: 1;\n\tbool warned_unassoc_progs: 1;\n\tstruct list_head all;\n\tstruct rhash_head hash_node;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct cgroup *cgrp;\n\tchar *cgrp_path;\n\tstruct kset *sub_kset;\n\tbool sub_attached;\n\tlong unsigned int watchdog_timeout;\n\tatomic_t exit_kind;\n\tstruct scx_exit_info *exit_info;\n\tstruct kobject kobj;\n\tstruct kthread_worker *helper;\n\tstruct irq_work error_irq_work;\n\tstruct kthread_work disable_work;\n\tstruct timer_list bypass_lb_timer;\n\tstruct rcu_work rcu_work;\n\tstruct scx_sched *ancestors[0];\n};\n\nstruct scx_sched_pcpu {\n\tstruct scx_sched *sch;\n\tu64 flags;\n\tstruct scx_event_stats event_stats;\n\tstruct scx_deferred_reenq_local deferred_reenq_local;\n\tstruct scx_dispatch_q bypass_dsq;\n\tu32 bypass_host_seq;\n\tstruct scx_dsp_ctx dsp_ctx;\n};\n\nstruct scx_sched_pnode {\n\tstruct scx_dispatch_q global_dsq;\n};\n\nstruct scx_sub_attach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_sub_detach_args {\n\tstruct sched_ext_ops *ops;\n\tchar *cgroup_path;\n};\n\nstruct scx_task_group {\n\tu32 flags;\n\tu32 weight;\n\tu64 bw_period_us;\n\tu64 bw_quota_us;\n\tu64 bw_burst_us;\n\tbool idle;\n};\n\nstruct scx_task_iter {\n\tstruct sched_ext_entity cursor;\n\tstruct task_struct *locked_task;\n\tstruct rq *rq;\n\tstruct rq_flags rf;\n\tu32 cnt;\n\tbool list_locked;\n\tstruct cgroup *cgrp;\n\tstruct cgroup_subsys_state *css_pos;\n\tstruct css_task_iter css_iter;\n};\n\nstruct sd_flag_debug {\n\tunsigned int meta_flags;\n\tchar *name;\n};\n\nstruct sd_flow_limit {\n\tstruct callback_head rcu;\n\tunsigned int count;\n\tu8 log_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tunsigned int group_smt_balance;\n\tlong unsigned int group_misfit_task_load;\n\tunsigned int nr_numa_running;\n\tunsigned int nr_preferred_running;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u16 orig_mac_len;\n\t__u8 proto;\n\t__u8 inner_ipproto;\n};\n\nstruct sec_path {\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n\tu8 len;\n\tu8 olen;\n\tu8 verified_cnt;\n};\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tatomic_t filter_count;\n\tstruct seccomp_filter *filter;\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct seccomp_filter {\n\trefcount_t refs;\n\trefcount_t users;\n\tbool log;\n\tbool wait_killable_recv;\n\tstruct action_cache cache;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_kaddfd {\n\tstruct file *file;\n\tint fd;\n\tunsigned int flags;\n\t__u32 ioctl_flags;\n\tunion {\n\t\tbool setfd;\n\t\tint ret;\n\t};\n\tstruct completion completion;\n\tstruct list_head list;\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n\tstruct list_head addfd;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct seccomp_metadata {\n\t__u64 filter_off;\n\t__u64 flags;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_addfd {\n\t__u64 id;\n\t__u32 flags;\n\t__u32 srcfd;\n\t__u32 newfd;\n\t__u32 newfd_flags;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct security_class_mapping {\n\tconst char *name;\n\tconst char *perms[33];\n};\n\nstruct timezone;\n\nstruct xattr;\n\nstruct sembuf;\n\nunion security_list_options {\n\tint (*binder_set_context_mgr)(const struct cred *);\n\tint (*binder_transaction)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_binder)(const struct cred *, const struct cred *);\n\tint (*binder_transfer_file)(const struct cred *, const struct cred *, const struct file *);\n\tint (*ptrace_access_check)(struct task_struct *, unsigned int);\n\tint (*ptrace_traceme)(struct task_struct *);\n\tint (*capget)(const struct task_struct *, kernel_cap_t *, kernel_cap_t *, kernel_cap_t *);\n\tint (*capset)(struct cred *, const struct cred *, const kernel_cap_t *, const kernel_cap_t *, const kernel_cap_t *);\n\tint (*capable)(const struct cred *, struct user_namespace *, int, unsigned int);\n\tint (*quotactl)(int, int, int, const struct super_block *);\n\tint (*quota_on)(struct dentry *);\n\tint (*syslog)(int);\n\tint (*settime)(const struct timespec64 *, const struct timezone *);\n\tint (*vm_enough_memory)(struct mm_struct *, long int);\n\tint (*bprm_creds_for_exec)(struct linux_binprm *);\n\tint (*bprm_creds_from_file)(struct linux_binprm *, const struct file *);\n\tint (*bprm_check_security)(struct linux_binprm *);\n\tvoid (*bprm_committing_creds)(const struct linux_binprm *);\n\tvoid (*bprm_committed_creds)(const struct linux_binprm *);\n\tint (*fs_context_submount)(struct fs_context *, struct super_block *);\n\tint (*fs_context_dup)(struct fs_context *, struct fs_context *);\n\tint (*fs_context_parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*sb_alloc_security)(struct super_block *);\n\tvoid (*sb_delete)(struct super_block *);\n\tvoid (*sb_free_security)(struct super_block *);\n\tvoid (*sb_free_mnt_opts)(void *);\n\tint (*sb_eat_lsm_opts)(char *, void **);\n\tint (*sb_mnt_opts_compat)(struct super_block *, void *);\n\tint (*sb_remount)(struct super_block *, void *);\n\tint (*sb_kern_mount)(const struct super_block *);\n\tint (*sb_show_options)(struct seq_file *, struct super_block *);\n\tint (*sb_statfs)(struct dentry *);\n\tint (*sb_mount)(const char *, const struct path *, const char *, long unsigned int, void *);\n\tint (*sb_umount)(struct vfsmount *, int);\n\tint (*sb_pivotroot)(const struct path *, const struct path *);\n\tint (*sb_set_mnt_opts)(struct super_block *, void *, long unsigned int, long unsigned int *);\n\tint (*sb_clone_mnt_opts)(const struct super_block *, struct super_block *, long unsigned int, long unsigned int *);\n\tint (*move_mount)(const struct path *, const struct path *);\n\tint (*dentry_init_security)(struct dentry *, int, const struct qstr *, const char **, struct lsm_context *);\n\tint (*dentry_create_files_as)(struct dentry *, int, const struct qstr *, const struct cred *, struct cred *);\n\tint (*path_unlink)(const struct path *, struct dentry *);\n\tint (*path_mkdir)(const struct path *, struct dentry *, umode_t);\n\tint (*path_rmdir)(const struct path *, struct dentry *);\n\tint (*path_mknod)(const struct path *, struct dentry *, umode_t, unsigned int);\n\tvoid (*path_post_mknod)(struct mnt_idmap *, struct dentry *);\n\tint (*path_truncate)(const struct path *);\n\tint (*path_symlink)(const struct path *, struct dentry *, const char *);\n\tint (*path_link)(struct dentry *, const struct path *, struct dentry *);\n\tint (*path_rename)(const struct path *, struct dentry *, const struct path *, struct dentry *, unsigned int);\n\tint (*path_chmod)(const struct path *, umode_t);\n\tint (*path_chown)(const struct path *, kuid_t, kgid_t);\n\tint (*path_chroot)(const struct path *);\n\tint (*path_notify)(const struct path *, u64, unsigned int);\n\tint (*inode_alloc_security)(struct inode *);\n\tvoid (*inode_free_security)(struct inode *);\n\tvoid (*inode_free_security_rcu)(void *);\n\tint (*inode_init_security)(struct inode *, struct inode *, const struct qstr *, struct xattr *, int *);\n\tint (*inode_init_security_anon)(struct inode *, const struct qstr *, const struct inode *);\n\tint (*inode_create)(struct inode *, struct dentry *, umode_t);\n\tvoid (*inode_post_create_tmpfile)(struct mnt_idmap *, struct inode *);\n\tint (*inode_link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_unlink)(struct inode *, struct dentry *);\n\tint (*inode_symlink)(struct inode *, struct dentry *, const char *);\n\tint (*inode_mkdir)(struct inode *, struct dentry *, umode_t);\n\tint (*inode_rmdir)(struct inode *, struct dentry *);\n\tint (*inode_mknod)(struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*inode_rename)(struct inode *, struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_readlink)(struct dentry *);\n\tint (*inode_follow_link)(struct dentry *, struct inode *, bool);\n\tint (*inode_permission)(struct inode *, int);\n\tint (*inode_setattr)(struct mnt_idmap *, struct dentry *, struct iattr *);\n\tvoid (*inode_post_setattr)(struct mnt_idmap *, struct dentry *, int);\n\tint (*inode_getattr)(const struct path *);\n\tint (*inode_xattr_skipcap)(const char *);\n\tint (*inode_setxattr)(struct mnt_idmap *, struct dentry *, const char *, const void *, size_t, int);\n\tvoid (*inode_post_setxattr)(struct dentry *, const char *, const void *, size_t, int);\n\tint (*inode_getxattr)(struct dentry *, const char *);\n\tint (*inode_listxattr)(struct dentry *);\n\tint (*inode_removexattr)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_removexattr)(struct dentry *, const char *);\n\tint (*inode_file_setattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_file_getattr)(struct dentry *, struct file_kattr *);\n\tint (*inode_set_acl)(struct mnt_idmap *, struct dentry *, const char *, struct posix_acl *);\n\tvoid (*inode_post_set_acl)(struct dentry *, const char *, struct posix_acl *);\n\tint (*inode_get_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tvoid (*inode_post_remove_acl)(struct mnt_idmap *, struct dentry *, const char *);\n\tint (*inode_need_killpriv)(struct dentry *);\n\tint (*inode_killpriv)(struct mnt_idmap *, struct dentry *);\n\tint (*inode_getsecurity)(struct mnt_idmap *, struct inode *, const char *, void **, bool);\n\tint (*inode_setsecurity)(struct inode *, const char *, const void *, size_t, int);\n\tint (*inode_listsecurity)(struct inode *, char *, size_t);\n\tvoid (*inode_getlsmprop)(struct inode *, struct lsm_prop *);\n\tint (*inode_copy_up)(struct dentry *, struct cred **);\n\tint (*inode_copy_up_xattr)(struct dentry *, const char *);\n\tint (*inode_setintegrity)(const struct inode *, enum lsm_integrity_type, const void *, size_t);\n\tint (*kernfs_init_security)(struct kernfs_node *, struct kernfs_node *);\n\tint (*file_permission)(struct file *, int);\n\tint (*file_alloc_security)(struct file *);\n\tvoid (*file_release)(struct file *);\n\tvoid (*file_free_security)(struct file *);\n\tint (*file_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*file_ioctl_compat)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap_addr)(long unsigned int);\n\tint (*mmap_file)(struct file *, long unsigned int, long unsigned int, long unsigned int);\n\tint (*file_mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int);\n\tint (*file_lock)(struct file *, unsigned int);\n\tint (*file_fcntl)(struct file *, unsigned int, long unsigned int);\n\tvoid (*file_set_fowner)(struct file *);\n\tint (*file_send_sigiotask)(struct task_struct *, struct fown_struct *, int);\n\tint (*file_receive)(struct file *);\n\tint (*file_open)(struct file *);\n\tint (*file_post_open)(struct file *, int);\n\tint (*file_truncate)(struct file *);\n\tint (*task_alloc)(struct task_struct *, u64);\n\tvoid (*task_free)(struct task_struct *);\n\tint (*cred_alloc_blank)(struct cred *, gfp_t);\n\tvoid (*cred_free)(struct cred *);\n\tint (*cred_prepare)(struct cred *, const struct cred *, gfp_t);\n\tvoid (*cred_transfer)(struct cred *, const struct cred *);\n\tvoid (*cred_getsecid)(const struct cred *, u32 *);\n\tvoid (*cred_getlsmprop)(const struct cred *, struct lsm_prop *);\n\tint (*kernel_act_as)(struct cred *, u32);\n\tint (*kernel_create_files_as)(struct cred *, struct inode *);\n\tint (*kernel_module_request)(char *);\n\tint (*kernel_load_data)(enum kernel_load_data_id, bool);\n\tint (*kernel_post_load_data)(char *, loff_t, enum kernel_load_data_id, char *);\n\tint (*kernel_read_file)(struct file *, enum kernel_read_file_id, bool);\n\tint (*kernel_post_read_file)(struct file *, char *, loff_t, enum kernel_read_file_id);\n\tint (*task_fix_setuid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgroups)(struct cred *, const struct cred *);\n\tint (*task_setpgid)(struct task_struct *, pid_t);\n\tint (*task_getpgid)(struct task_struct *);\n\tint (*task_getsid)(struct task_struct *);\n\tvoid (*current_getlsmprop_subj)(struct lsm_prop *);\n\tvoid (*task_getlsmprop_obj)(struct task_struct *, struct lsm_prop *);\n\tint (*task_setnice)(struct task_struct *, int);\n\tint (*task_setioprio)(struct task_struct *, int);\n\tint (*task_getioprio)(struct task_struct *);\n\tint (*task_prlimit)(const struct cred *, const struct cred *, unsigned int);\n\tint (*task_setrlimit)(struct task_struct *, unsigned int, struct rlimit *);\n\tint (*task_setscheduler)(struct task_struct *);\n\tint (*task_getscheduler)(struct task_struct *);\n\tint (*task_movememory)(struct task_struct *);\n\tint (*task_kill)(struct task_struct *, struct kernel_siginfo *, int, const struct cred *);\n\tint (*task_prctl)(int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tvoid (*task_to_inode)(struct task_struct *, struct inode *);\n\tint (*userns_create)(const struct cred *);\n\tint (*ipc_permission)(struct kern_ipc_perm *, short int);\n\tvoid (*ipc_getlsmprop)(struct kern_ipc_perm *, struct lsm_prop *);\n\tint (*msg_msg_alloc_security)(struct msg_msg *);\n\tvoid (*msg_msg_free_security)(struct msg_msg *);\n\tint (*msg_queue_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*msg_queue_free_security)(struct kern_ipc_perm *);\n\tint (*msg_queue_associate)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgctl)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgsnd)(struct kern_ipc_perm *, struct msg_msg *, int);\n\tint (*msg_queue_msgrcv)(struct kern_ipc_perm *, struct msg_msg *, struct task_struct *, long int, int);\n\tint (*shm_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*shm_free_security)(struct kern_ipc_perm *);\n\tint (*shm_associate)(struct kern_ipc_perm *, int);\n\tint (*shm_shmctl)(struct kern_ipc_perm *, int);\n\tint (*shm_shmat)(struct kern_ipc_perm *, char *, int);\n\tint (*sem_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*sem_free_security)(struct kern_ipc_perm *);\n\tint (*sem_associate)(struct kern_ipc_perm *, int);\n\tint (*sem_semctl)(struct kern_ipc_perm *, int);\n\tint (*sem_semop)(struct kern_ipc_perm *, struct sembuf *, unsigned int, int);\n\tint (*netlink_send)(struct sock *, struct sk_buff *);\n\tvoid (*d_instantiate)(struct dentry *, struct inode *);\n\tint (*getselfattr)(unsigned int, struct lsm_ctx *, u32 *, u32);\n\tint (*setselfattr)(unsigned int, struct lsm_ctx *, u32, u32);\n\tint (*getprocattr)(struct task_struct *, const char *, char **);\n\tint (*setprocattr)(const char *, void *, size_t);\n\tint (*ismaclabel)(const char *);\n\tint (*secid_to_secctx)(u32, struct lsm_context *);\n\tint (*lsmprop_to_secctx)(struct lsm_prop *, struct lsm_context *);\n\tint (*secctx_to_secid)(const char *, u32, u32 *);\n\tvoid (*release_secctx)(struct lsm_context *);\n\tvoid (*inode_invalidate_secctx)(struct inode *);\n\tint (*inode_notifysecctx)(struct inode *, void *, u32);\n\tint (*inode_setsecctx)(struct dentry *, void *, u32);\n\tint (*inode_getsecctx)(struct inode *, struct lsm_context *);\n\tint (*unix_stream_connect)(struct sock *, struct sock *, struct sock *);\n\tint (*unix_may_send)(struct socket *, struct socket *);\n\tint (*socket_create)(int, int, int, int);\n\tint (*socket_post_create)(struct socket *, int, int, int, int);\n\tint (*socket_socketpair)(struct socket *, struct socket *);\n\tint (*socket_bind)(struct socket *, struct sockaddr *, int);\n\tint (*socket_connect)(struct socket *, struct sockaddr *, int);\n\tint (*socket_listen)(struct socket *, int);\n\tint (*socket_accept)(struct socket *, struct socket *);\n\tint (*socket_sendmsg)(struct socket *, struct msghdr *, int);\n\tint (*socket_recvmsg)(struct socket *, struct msghdr *, int, int);\n\tint (*socket_getsockname)(struct socket *);\n\tint (*socket_getpeername)(struct socket *);\n\tint (*socket_getsockopt)(struct socket *, int, int);\n\tint (*socket_setsockopt)(struct socket *, int, int);\n\tint (*socket_shutdown)(struct socket *, int);\n\tint (*socket_sock_rcv_skb)(struct sock *, struct sk_buff *);\n\tint (*socket_getpeersec_stream)(struct socket *, sockptr_t, sockptr_t, unsigned int);\n\tint (*socket_getpeersec_dgram)(struct socket *, struct sk_buff *, u32 *);\n\tint (*sk_alloc_security)(struct sock *, int, gfp_t);\n\tvoid (*sk_free_security)(struct sock *);\n\tvoid (*sk_clone_security)(const struct sock *, struct sock *);\n\tvoid (*sk_getsecid)(const struct sock *, u32 *);\n\tvoid (*sock_graft)(struct sock *, struct socket *);\n\tint (*inet_conn_request)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*inet_csk_clone)(struct sock *, const struct request_sock *);\n\tvoid (*inet_conn_established)(struct sock *, struct sk_buff *);\n\tint (*secmark_relabel_packet)(u32);\n\tvoid (*secmark_refcount_inc)(void);\n\tvoid (*secmark_refcount_dec)(void);\n\tvoid (*req_classify_flow)(const struct request_sock *, struct flowi_common *);\n\tint (*tun_dev_alloc_security)(void *);\n\tint (*tun_dev_create)(void);\n\tint (*tun_dev_attach_queue)(void *);\n\tint (*tun_dev_attach)(struct sock *, void *);\n\tint (*tun_dev_open)(void *);\n\tint (*sctp_assoc_request)(struct sctp_association *, struct sk_buff *);\n\tint (*sctp_bind_connect)(struct sock *, int, struct sockaddr *, int);\n\tvoid (*sctp_sk_clone)(struct sctp_association *, struct sock *, struct sock *);\n\tint (*sctp_assoc_established)(struct sctp_association *, struct sk_buff *);\n\tint (*mptcp_add_subflow)(struct sock *, struct sock *);\n\tint (*key_alloc)(struct key *, const struct cred *, long unsigned int);\n\tint (*key_permission)(key_ref_t, const struct cred *, enum key_need_perm);\n\tint (*key_getsecurity)(struct key *, char **);\n\tvoid (*key_post_create_or_update)(struct key *, struct key *, const void *, size_t, long unsigned int, bool);\n\tint (*audit_rule_init)(u32, u32, char *, void **, gfp_t);\n\tint (*audit_rule_known)(struct audit_krule *);\n\tint (*audit_rule_match)(struct lsm_prop *, u32, u32, void *);\n\tvoid (*audit_rule_free)(void *);\n\tint (*bpf)(int, union bpf_attr *, unsigned int, bool);\n\tint (*bpf_map)(struct bpf_map *, fmode_t);\n\tint (*bpf_prog)(struct bpf_prog *);\n\tint (*bpf_map_create)(struct bpf_map *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_map_free)(struct bpf_map *);\n\tint (*bpf_prog_load)(struct bpf_prog *, union bpf_attr *, struct bpf_token *, bool);\n\tvoid (*bpf_prog_free)(struct bpf_prog *);\n\tint (*bpf_token_create)(struct bpf_token *, union bpf_attr *, const struct path *);\n\tvoid (*bpf_token_free)(struct bpf_token *);\n\tint (*bpf_token_cmd)(const struct bpf_token *, enum bpf_cmd);\n\tint (*bpf_token_capable)(const struct bpf_token *, int);\n\tint (*locked_down)(enum lockdown_reason);\n\tint (*perf_event_open)(int);\n\tint (*perf_event_alloc)(struct perf_event *);\n\tint (*perf_event_read)(struct perf_event *);\n\tint (*perf_event_write)(struct perf_event *);\n\tint (*uring_override_creds)(const struct cred *);\n\tint (*uring_sqpoll)(void);\n\tint (*uring_cmd)(struct io_uring_cmd *);\n\tint (*uring_allowed)(void);\n\tvoid (*initramfs_populated)(void);\n\tint (*bdev_alloc_security)(struct block_device *);\n\tvoid (*bdev_free_security)(struct block_device *);\n\tint (*bdev_setintegrity)(struct block_device *, enum lsm_integrity_type, const void *, size_t);\n\tvoid *lsm_func_addr;\n};\n\nstruct security_hook_list {\n\tstruct lsm_static_call *scalls;\n\tunion security_list_options hook;\n\tconst struct lsm_id *lsmid;\n};\n\nstruct secvar_operations {\n\tint (*get)(const char *, u64, u8 *, u64 *);\n\tint (*get_next)(const char *, u64 *, u64);\n\tint (*set)(const char *, u64, u8 *, u64);\n\tssize_t (*format)(char *, size_t);\n\tint (*max_size)(u64 *);\n\tconst char * const *var_names;\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nstruct sel_netif {\n\tstruct list_head list;\n\tstruct netif_security_struct nsec;\n\tstruct callback_head callback_head;\n};\n\nstruct sel_netnode {\n\tstruct netnode_security_struct nsec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netnode_bkt {\n\tunsigned int size;\n\tstruct list_head list;\n};\n\nstruct sel_netport {\n\tstruct netport_security_struct psec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct sel_netport_bkt {\n\tint size;\n\tstruct list_head list;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\nstruct selinux_audit_data {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tu32 requested;\n\tu32 audited;\n\tu32 denied;\n\tint result;\n};\n\nstruct selinux_audit_rule {\n\tu32 au_seqno;\n\tstruct context au_ctxt;\n};\n\nstruct selinux_avc {\n\tunsigned int avc_cache_threshold;\n\tstruct avc_cache avc_cache;\n};\n\nstruct selinux_fs_info {\n\tstruct dentry *bool_dir;\n\tunsigned int bool_num;\n\tchar **bool_pending_names;\n\tint *bool_pending_values;\n\tstruct dentry *class_dir;\n\tlong unsigned int last_class_ino;\n\tbool policy_opened;\n\tlong unsigned int last_ino;\n\tstruct super_block *sb;\n};\n\nstruct selinux_kernel_status {\n\tu32 version;\n\tu32 sequence;\n\tu32 enforcing;\n\tu32 policyload;\n\tu32 deny_unknown;\n};\n\nstruct selinux_policy;\n\nstruct selinux_policy_convert_data;\n\nstruct selinux_load_state {\n\tstruct selinux_policy *policy;\n\tstruct selinux_policy_convert_data *convert_data;\n};\n\nstruct selinux_mapping;\n\nstruct selinux_map {\n\tstruct selinux_mapping *mapping;\n\tu16 size;\n};\n\nstruct selinux_mapping {\n\tu16 value;\n\tu16 num_perms;\n\tu32 perms[32];\n};\n\nstruct selinux_mnt_opts {\n\tu32 fscontext_sid;\n\tu32 context_sid;\n\tu32 rootcontext_sid;\n\tu32 defcontext_sid;\n};\n\nstruct sidtab;\n\nstruct selinux_policy {\n\tstruct sidtab *sidtab;\n\tstruct policydb policydb;\n\tstruct selinux_map map;\n\tu32 latest_granting;\n};\n\nstruct sidtab_convert_params {\n\tstruct convert_context_args *args;\n\tstruct sidtab *target;\n};\n\nstruct selinux_policy_convert_data {\n\tstruct convert_context_args args;\n\tstruct sidtab_convert_params sidtab_params;\n};\n\nstruct selinux_state {\n\tbool enforcing;\n\tbool initialized;\n\tbool policycap[15];\n\tstruct page *status_page;\n\tstruct mutex status_lock;\n\tstruct selinux_policy *policy;\n\tstruct mutex policy_mutex;\n};\n\nstruct selnl_msg_policyload {\n\t__u32 seqno;\n};\n\nstruct selnl_msg_setenforce {\n\t__s32 val;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\ttime64_t sem_otime;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sem sems[0];\n};\n\nstruct sem_undo;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo_list;\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int semadj[0];\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\tlong int sem_otime;\n\tlong int sem_ctime;\n\tlong unsigned int sem_nsems;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n\tbool has_siginfo;\n\tstruct kernel_siginfo info;\n};\n\nstruct sensor_data {\n\tu32 id;\n\tu32 hwmon_index;\n\tu32 opal_index;\n\tenum sensors type;\n\tchar label[64];\n\tchar name[32];\n\tstruct device_attribute dev_attr;\n\tstruct sensor_group_data *sgrp_data;\n};\n\nstruct sensor_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint index;\n};\n\nstruct sensor_group {\n\tconst char *name;\n\tstruct attribute_group group;\n\tu32 attr_count;\n\tu32 hwmon_index;\n};\n\nstruct sg_attr;\n\nstruct sensor_group___2 {\n\tchar name[20];\n\tstruct attribute_group sg;\n\tstruct sg_attr *sgattrs;\n};\n\nstruct sensor_group_data {\n\tstruct mutex mutex;\n\tu32 gid;\n\tbool enable;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct seqcount_rwlock {\n\tseqcount_t seqcount;\n};\n\ntypedef struct seqcount_rwlock seqcount_rwlock_t;\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct serial_ctrl_device {\n\tstruct device dev;\n\tstruct ida port_ida;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_in_rdev {\n\tstruct rb_root_cached serial_rb;\n\tspinlock_t serial_lock;\n\twait_queue_head_t serial_io_wait;\n};\n\nstruct serial_info {\n\tstruct rb_node node;\n\tsector_t start;\n\tsector_t last;\n\tsector_t _subtree_last;\n};\n\nstruct serial_port_device {\n\tstruct device dev;\n\tstruct uart_port *port;\n\tunsigned int tx_enabled: 1;\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\ntypedef struct serio *class_serio_pause_rx_t;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nstruct set_affinity_pending {\n\trefcount_t refs;\n\tunsigned int stop_pending;\n\tstruct completion done;\n\tstruct cpu_stop_work stop_work;\n\tstruct migration_arg arg;\n};\n\nstruct set_config_request {\n\tstruct usb_device *udev;\n\tint config;\n\tstruct work_struct work;\n\tstruct list_head node;\n};\n\nstruct set_event_iter {\n\tenum set_event_iter_type type;\n\tunion {\n\t\tstruct trace_event_file *file;\n\t\tstruct event_mod_load *event_mod;\n\t};\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_module_caps {\n\tlong unsigned int interfaces[1];\n\tlong unsigned int link_modes[2];\n\tbool may_have_phy;\n\tu8 port;\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *, struct phy_device *);\n};\n\nstruct sg_append_table {\n\tstruct sg_table sgt;\n\tstruct scatterlist *prv;\n\tunsigned int total_nents;\n};\n\nstruct sg_attr {\n\tu32 handle;\n\tstruct kobj_attribute attr;\n};\n\nstruct sg_device {\n\tstruct scsi_device *device;\n\twait_queue_head_t open_wait;\n\tstruct mutex open_rel_lock;\n\tint sg_tablesize;\n\tu32 index;\n\tstruct list_head sfds;\n\trwlock_t sfd_lock;\n\tatomic_t detaching;\n\tbool exclude;\n\tint open_cnt;\n\tchar sgdebug;\n\tchar name[32];\n\tstruct cdev *cdev;\n\tstruct kref d_ref;\n};\n\ntypedef struct sg_device Sg_device;\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_scatter_hold {\n\tshort unsigned int k_use_sg;\n\tunsigned int sglist_len;\n\tunsigned int bufflen;\n\tstruct page **pages;\n\tint page_order;\n\tchar dio_in_use;\n\tunsigned char cmd_opcode;\n};\n\ntypedef struct sg_scatter_hold Sg_scatter_hold;\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\ntypedef struct sg_io_hdr sg_io_hdr_t;\n\nstruct sg_fd;\n\nstruct sg_request {\n\tstruct list_head entry;\n\tstruct sg_fd *parentfp;\n\tSg_scatter_hold data;\n\tsg_io_hdr_t header;\n\tunsigned char sense_b[96];\n\tchar res_used;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar done;\n\tstruct request *rq;\n\tstruct bio *bio;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_request Sg_request;\n\nstruct sg_fd {\n\tstruct list_head sfd_siblings;\n\tstruct sg_device *parentdp;\n\twait_queue_head_t read_wait;\n\trwlock_t rq_list_lock;\n\tstruct mutex f_mutex;\n\tint timeout;\n\tint timeout_user;\n\tSg_scatter_hold reserve;\n\tstruct list_head rq_list;\n\tstruct fasync_struct *async_qp;\n\tSg_request req_arr[16];\n\tchar force_packid;\n\tchar cmd_q;\n\tunsigned char next_cmd_len;\n\tchar keep_orphan;\n\tchar mmap_called;\n\tchar res_in_use;\n\tstruct kref f_ref;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_fd Sg_fd;\n\nstruct sg_header {\n\tint pack_len;\n\tint reply_len;\n\tint pack_id;\n\tint result;\n\tunsigned int twelve_byte: 1;\n\tunsigned int target_status: 5;\n\tunsigned int host_status: 8;\n\tunsigned int driver_status: 8;\n\tunsigned int other_flags: 10;\n\tunsigned char sense_buffer[16];\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\nstruct sg_ops_info {\n\tint opal_no;\n\tconst char *attr_name;\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct sg_proc_deviter {\n\tloff_t index;\n\tsize_t max;\n};\n\nstruct sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\ntypedef struct sg_req_info sg_req_info_t;\n\nstruct sg_scsi_id {\n\tint host_no;\n\tint channel;\n\tint scsi_id;\n\tint lun;\n\tint scsi_type;\n\tshort int h_cmd_per_lun;\n\tshort int d_queue_depth;\n\tint unused[2];\n};\n\ntypedef struct sg_scsi_id sg_scsi_id_t;\n\nstruct sgttyb {\n\tchar sg_ispeed;\n\tchar sg_ospeed;\n\tchar sg_erase;\n\tchar sg_kill;\n\tshort int sg_flags;\n};\n\nstruct sha224_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha256_ctx {\n\tstruct __sha256_ctx ctx;\n};\n\nstruct sha384_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct sha512_ctx {\n\tstruct __sha512_ctx ctx;\n};\n\nstruct shared_policy {\n\tstruct rb_root root;\n\trwlock_t lock;\n};\n\nstruct shash_desc;\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*export_core)(struct shash_desc *, void *);\n\tint (*import_core)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tint (*clone_tfm)(struct crypto_shash *, struct crypto_shash *);\n\tunsigned int descsize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int digestsize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct hash_alg_common halg;\n\t};\n};\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tvoid *__ctx[0];\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[120];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tunion {\n\t\tstruct offset_ctx dir_offsets;\n\t\tstruct {\n\t\t\tstruct list_head shrinklist;\n\t\t\tstruct list_head swaplist;\n\t\t};\n\t};\n\tstruct timespec64 i_crtime;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tlong unsigned int fallocend;\n\tunsigned int fsflags;\n\tatomic_t stop_eviction;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_quota_limits {\n\tqsize_t usrquota_bhardlimit;\n\tqsize_t usrquota_ihardlimit;\n\tqsize_t grpquota_bhardlimit;\n\tqsize_t grpquota_ihardlimit;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tbool full_inums;\n\tint huge;\n\tint seen;\n\tbool noswap;\n\tshort unsigned int quota_types;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_ispace;\n\traw_spinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tbool full_inums;\n\tbool noswap;\n\tino_t next_ino;\n\tino_t *ino_batch;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n\tstruct shmem_quota_limits qlimits;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\tlong int shm_atime;\n\tlong int shm_dtime;\n\tlong int shm_ctime;\n\t__kernel_size_t shm_segsz;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused5;\n\tlong unsigned int __unused6;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct ucounts *mlock_ucounts;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tstruct ipc_namespace *ns;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\trefcount_t refcount;\n\tstruct completion done;\n\tstruct callback_head rcu;\n\tvoid *private_data;\n\tstruct list_head list;\n\tint id;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct shrinker_info_unit;\n\nstruct shrinker_info {\n\tstruct callback_head rcu;\n\tint map_nr_max;\n\tstruct shrinker_info_unit *unit[0];\n};\n\nstruct shrinker_info_unit {\n\tatomic_long_t nr_deferred[64];\n\tlong unsigned int map[1];\n};\n\nstruct sibling_subcore_state {\n\tlong unsigned int flags;\n\tu8 in_guest[4];\n};\n\nstruct sidtab_node_inner;\n\nstruct sidtab_node_leaf;\n\nunion sidtab_entry_inner {\n\tstruct sidtab_node_inner *ptr_inner;\n\tstruct sidtab_node_leaf *ptr_leaf;\n};\n\nstruct sidtab_str_cache;\n\nstruct sidtab_entry {\n\tu32 sid;\n\tu32 hash;\n\tstruct context context;\n\tstruct sidtab_str_cache *cache;\n\tstruct hlist_node list;\n};\n\nstruct sidtab_isid_entry {\n\tint set;\n\tstruct sidtab_entry entry;\n};\n\nstruct sidtab {\n\tunion sidtab_entry_inner roots[3];\n\tu32 count;\n\tstruct sidtab_convert_params *convert;\n\tbool frozen;\n\tspinlock_t lock;\n\tu32 cache_free_slots;\n\tstruct list_head cache_lru_list;\n\tspinlock_t cache_lock;\n\tstruct sidtab_isid_entry isids[27];\n\tstruct hlist_head context_to_sid[512];\n};\n\nstruct sidtab_node_inner {\n\tunion sidtab_entry_inner entries[8192];\n};\n\nstruct sidtab_node_leaf {\n\tstruct sidtab_entry entries[630];\n};\n\nstruct sidtab_str_cache {\n\tstruct callback_head rcu_member;\n\tstruct list_head lru_member;\n\tstruct sidtab_entry *parent;\n\tu32 len;\n\tchar str[0];\n};\n\nstruct sig_alg {\n\tint (*sign)(struct crypto_sig *, const void *, unsigned int, void *, unsigned int);\n\tint (*verify)(struct crypto_sig *, const void *, unsigned int, const void *, unsigned int);\n\tint (*set_pub_key)(struct crypto_sig *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_sig *, const void *, unsigned int);\n\tunsigned int (*key_size)(struct crypto_sig *);\n\tunsigned int (*digest_size)(struct crypto_sig *);\n\tunsigned int (*max_size)(struct crypto_sig *);\n\tint (*init)(struct crypto_sig *);\n\tvoid (*exit)(struct crypto_sig *);\n\tstruct crypto_alg base;\n};\n\nstruct sig_instance {\n\tvoid (*free)(struct sig_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[72];\n\t\t\tstruct crypto_instance base;\n\t\t};\n\t\tstruct sig_alg alg;\n\t};\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct signal_frame_64 {\n\tchar dummy[128];\n\tstruct ucontext uc;\n\tlong unsigned int unused[2];\n\tunsigned int tramp[6];\n\tstruct siginfo *pinfo;\n\tvoid *puc;\n\tstruct siginfo info;\n\tchar abigap[288];\n};\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct task_io_accounting {\n\tu64 rchar;\n\tu64 wchar;\n\tu64 syscr;\n\tu64 syscw;\n\tu64 read_bytes;\n\tu64 write_bytes;\n\tu64 cancelled_write_bytes;\n};\n\nstruct taskstats;\n\nstruct tty_audit_buf;\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tint quick_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exec_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tstruct core_state *core_state;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tunsigned int timer_create_restore_ids: 1;\n\tatomic_t next_posix_timer_id;\n\tstruct hlist_head posix_timers;\n\tstruct hlist_head ignored_posix_timers;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tatomic_t tick_dep_mask;\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tstruct autogroup *autogroup;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct pacct_struct pacct;\n\tstruct taskstats *stats;\n\tunsigned int audit_tty;\n\tstruct tty_audit_buf *tty_audit_buf;\n\tstruct rw_semaphore cgroup_threadgroup_rwsem;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct rw_semaphore exec_update_lock;\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct signature_hdr {\n\tuint8_t version;\n\tuint32_t timestamp;\n\tuint8_t algo;\n\tuint8_t hash;\n\tuint8_t keyid[8];\n\tuint8_t nmpi;\n\tchar mpi[0];\n} __attribute__((packed));\n\nstruct signature_v2_hdr {\n\tuint8_t type;\n\tuint8_t version;\n\tuint8_t hash_algo;\n\t__be32 keyid;\n\t__be16 sig_size;\n\tuint8_t sig[0];\n} __attribute__((packed));\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct sil24_prb {\n\t__le16 ctrl;\n\t__le16 prot;\n\t__le32 rx_cnt;\n\tu8 fis[24];\n};\n\nstruct sil24_sge {\n\t__le64 addr;\n\t__le32 cnt;\n\t__le32 flags;\n};\n\nstruct sil24_ata_block {\n\tstruct sil24_prb prb;\n\tstruct sil24_sge sge[4093];\n};\n\nstruct sil24_atapi_block {\n\tstruct sil24_prb prb;\n\tu8 cdb[16];\n\tstruct sil24_sge sge[4093];\n};\n\nstruct sil24_cerr_info {\n\tunsigned int err_mask;\n\tunsigned int action;\n\tconst char *desc;\n};\n\nunion sil24_cmd_block {\n\tstruct sil24_ata_block ata;\n\tstruct sil24_atapi_block atapi;\n};\n\nstruct sil24_port_priv {\n\tunion sil24_cmd_block *cmd_block;\n\tdma_addr_t cmd_block_dma;\n\tint do_port_rst;\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct simple_pm_bus {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_xattr {\n\tstruct rb_node rb_node;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nstruct sit_net {\n\tstruct ip_tunnel *tunnels_r_l[16];\n\tstruct ip_tunnel *tunnels_r[16];\n\tstruct ip_tunnel *tunnels_l[16];\n\tstruct ip_tunnel *tunnels_wc[1];\n\tstruct ip_tunnel **tunnels[4];\n\tstruct net_device *fb_tunnel_dev;\n};\n\nstruct zs_size_stat {\n\tlong unsigned int objs[14];\n};\n\nstruct size_class {\n\tspinlock_t lock;\n\tstruct list_head fullness_list[12];\n\tint size;\n\tint objs_per_zspage;\n\tint pages_per_zspage;\n\tunsigned int index;\n\tstruct zs_size_stat stats;\n};\n\nstruct sk_buff__safe_rcu_or_null {\n\tstruct sock *sk;\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct sk_psock_work_state {\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tbool redir_ingress;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tspinlock_t ingress_lock;\n\tu32 msg_tot_len;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_destroy)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tvoid (*saved_data_ready)(struct sock *);\n\tint (*psock_update_sk_prot)(struct sock *, struct sk_psock *, bool);\n\tstruct proto *sk_proto;\n\tstruct mutex work_mutex;\n\tstruct sk_psock_work_state work_state;\n\tstruct delayed_work work;\n\tstruct sock *sk_pair;\n\tstruct rcu_work rwork;\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct sk_security_struct {\n\tu32 sid;\n\tu32 peer_sid;\n\tu16 sclass;\n\tenum {\n\t\tSCTP_ASSOC_UNSET = 0,\n\t\tSCTP_ASSOC_SET = 1,\n\t} sctp_assoc_state;\n};\n\nstruct tls_msg {\n\tu8 control;\n};\n\nstruct sk_skb_cb {\n\tunsigned char data[20];\n\tunsigned char pad[4];\n\tstruct _strp_msg strp;\n\tstruct tls_msg tls;\n\tu64 temp_reg;\n};\n\nstruct skb_defer_node {\n\tstruct llist_head defer_list;\n\tatomic_long_t defer_count;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct skb_ext {\n\trefcount_t refcnt;\n\tu8 offset[1];\n\tu8 chunks;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct skb_frag {\n\tnetmem_ref netmem;\n\tunsigned int len;\n\tunsigned int offset;\n};\n\ntypedef struct skb_frag skb_frag_t;\n\nstruct skb_free_array {\n\tunsigned int skb_count;\n\tvoid *skb_array[16];\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n\t__u32 frag_off;\n};\n\nstruct skb_shared_hwtstamps {\n\tunion {\n\t\tktime_t hwtstamp;\n\t\tvoid *netdev_data;\n\t};\n};\n\nstruct xsk_tx_metadata_compl {\n\t__u64 *tx_timestamp;\n};\n\nstruct skb_shared_info {\n\t__u8 flags;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tunion {\n\t\tstruct skb_shared_hwtstamps hwtstamps;\n\t\tstruct xsk_tx_metadata_compl xsk_meta;\n\t};\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tunion {\n\t\tstruct {\n\t\t\tu32 xdp_frags_size;\n\t\t\tu32 xdp_frags_truesize;\n\t\t};\n\t\tvoid *destructor_arg;\n\t};\n\tskb_frag_t frags[17];\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*export)(struct skcipher_request *, void *);\n\tint (*import)(struct skcipher_request *, const void *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int walksize;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int min_keysize;\n\t\t\tunsigned int max_keysize;\n\t\t\tunsigned int ivsize;\n\t\t\tunsigned int chunksize;\n\t\t\tunsigned int statesize;\n\t\t\tstruct crypto_alg base;\n\t\t};\n\t\tstruct skcipher_alg_common co;\n\t};\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[88];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tvoid *__ctx[0];\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tconst void * const addr;\n\t\t\t} virt;\n\t\t} src;\n\t\tstruct scatter_walk in;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tvoid * const addr;\n\t\t\t} virt;\n\t\t} dst;\n\t\tstruct scatter_walk out;\n\t};\n\tunsigned int nbytes;\n\tunsigned int total;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct slab {\n\tmemdesc_flags_t flags;\n\tstruct kmem_cache *slab_cache;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head slab_list;\n\t\t\tstruct freelist_counters;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunsigned int __page_type;\n\tatomic_t __page_refcount;\n\tlong unsigned int obj_exts;\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct slab_sheaf {\n\tunion {\n\t\tstruct callback_head callback_head;\n\t\tstruct list_head barn_list;\n\t\tstruct {\n\t\t\tunsigned int capacity;\n\t\t\tbool pfmemalloc;\n\t\t};\n\t};\n\tstruct kmem_cache *cache;\n\tunsigned int size;\n\tint node;\n\tvoid *objects[0];\n};\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct slabobj_ext {\n\tstruct obj_cgroup *objcg;\n};\n\nstruct slb_entry {\n\tu64 esid;\n\tu64 vsid;\n};\n\nstruct slb_shadow {\n\t__be32 persistent;\n\t__be32 buffer_length;\n\t__be64 reserved;\n\tstruct {\n\t\t__be64 esid;\n\t\t__be64 vsid;\n\t} save_area[2];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct slub_flush_work {\n\tstruct work_struct work;\n\tstruct kmem_cache *s;\n\tbool skip;\n};\n\nstruct slub_percpu_sheaves {\n\tlocal_trylock_t lock;\n\tstruct slab_sheaf *main;\n\tstruct slab_sheaf *spare;\n\tstruct slab_sheaf *rcu_free;\n};\n\nstruct smc_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht;\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct smp_ops_t {\n\tvoid (*message_pass)(int, int);\n\tvoid (*cause_ipi)(int);\n\tint (*cause_nmi_ipi)(int);\n\tvoid (*probe)(void);\n\tint (*kick_cpu)(int);\n\tint (*prepare_cpu)(int);\n\tvoid (*setup_cpu)(int);\n\tvoid (*bringup_done)(void);\n\tvoid (*take_timebase)(void);\n\tvoid (*give_timebase)(void);\n\tint (*cpu_disable)(void);\n\tvoid (*cpu_die)(unsigned int);\n\tint (*cpu_bootable)(unsigned int);\n\tvoid (*cpu_offline_self)(void);\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct so_timestamping {\n\tint flags;\n\tint bind_phc;\n};\n\nstruct sock_bh_locked {\n\tstruct sock *sock;\n\tlocal_lock_t bh_lock;\n};\n\nstruct sock_diag_handler {\n\tstruct module *owner;\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_inet_compat {\n\tstruct module *owner;\n\tint (*fn)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_ee_data_rfc4884 {\n\t__u16 len;\n\t__u8 flags;\n\t__u8 reserved;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\tunion {\n\t\t__u32 ee_data;\n\t\tstruct sock_ee_data_rfc4884 ee_rfc4884;\n\t};\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sock_hash_seq_info {\n\tstruct bpf_map *map;\n\tstruct bpf_shtab *htab;\n\tu32 bucket_id;\n};\n\nstruct sock_map_seq_info {\n\tstruct bpf_map *map;\n\tstruct sock *sk;\n\tu32 index;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tu16 num_closed_socks;\n\tu16 incoming_cpu;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct sock_xprt {\n\tstruct rpc_xprt xprt;\n\tstruct socket *sock;\n\tstruct sock *inet;\n\tstruct file *file;\n\tstruct {\n\t\tstruct {\n\t\t\t__be32 fraghdr;\n\t\t\t__be32 xid;\n\t\t\t__be32 calldir;\n\t\t};\n\t\tu32 offset;\n\t\tu32 len;\n\t\tlong unsigned int copied;\n\t} recv;\n\tstruct {\n\t\tu32 offset;\n\t} xmit;\n\tlong unsigned int sock_state;\n\tstruct delayed_work connect_worker;\n\tstruct work_struct error_worker;\n\tstruct work_struct recv_worker;\n\tstruct mutex recv_mutex;\n\tstruct completion handshake_done;\n\tstruct __kernel_sockaddr_storage srcaddr;\n\tshort unsigned int srcport;\n\tint xprt_err;\n\tstruct rpc_clnt *clnt;\n\tsize_t rcvsize;\n\tsize_t sndsize;\n\tstruct rpc_timeout tcp_timeout;\n\tvoid (*old_data_ready)(struct sock *);\n\tvoid (*old_state_change)(struct sock *);\n\tvoid (*old_write_space)(struct sock *);\n\tvoid (*old_error_report)(struct sock *);\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct sockaddr_unsized {\n\t__kernel_sa_family_t sa_family;\n\tchar sa_data[0];\n};\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq wq;\n};\n\nstruct socket__safe_trusted_or_null {\n\tstruct sock *sk;\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sockmap_link {\n\tstruct bpf_link link;\n\tstruct bpf_map *map;\n};\n\nstruct soft_mask_table_entry {\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct softirq_action {\n\tvoid (*action)(void);\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tlocal_lock_t process_queue_bh_lock;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tstruct softnet_data *rps_ipi_list;\n\tunsigned int received_rps;\n\tbool in_net_rx_action;\n\tbool in_napi_threaded_poll;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct netdev_xmit xmit;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int input_queue_head;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong int pad[3];\n\tunsigned int input_queue_tail;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n\tint defer_ipi_scheduled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t defer_csd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct software_node_ref_args {\n\tconst struct software_node *swnode;\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[16];\n};\n\nstruct sp_node {\n\tstruct rb_node nd;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct mempolicy *policy;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n};\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tvoid (*splice_eof)(struct splice_desc *);\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct split_state {\n\tu8 step;\n\tu8 master;\n};\n\nstruct squashfs_super_block {\n\t__le32 s_magic;\n\t__le32 inodes;\n\t__le32 mkfs_time;\n\t__le32 block_size;\n\t__le32 fragments;\n\t__le16 compression;\n\t__le16 block_log;\n\t__le16 flags;\n\t__le16 no_ids;\n\t__le16 s_major;\n\t__le16 s_minor;\n\t__le64 root_inode;\n\t__le64 bytes_used;\n\t__le64 id_table_start;\n\t__le64 xattr_id_table_start;\n\t__le64 inode_table_start;\n\t__le64 directory_table_start;\n\t__le64 fragment_table_start;\n\t__le64 lookup_table_start;\n};\n\nstruct sr6_tlv {\n\t__u8 type;\n\t__u8 len;\n\t__u8 data[0];\n};\n\nstruct srcu_ctr {\n\tatomic_long_t srcu_locks;\n\tatomic_long_t srcu_unlocks;\n};\n\nstruct srcu_node;\n\nstruct srcu_data {\n\tstruct srcu_ctr srcu_ctrs[2];\n\tint srcu_reader_flavor;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct callback_head srcu_ec_head;\n\tint srcu_ec_state;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct srcu_usage {\n\tstruct srcu_node *node;\n\tstruct srcu_node *level[4];\n\tint srcu_size_state;\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_gp_start;\n\tlong unsigned int srcu_last_gp_end;\n\tlong unsigned int srcu_size_jiffies;\n\tlong unsigned int srcu_n_lock_retries;\n\tlong unsigned int srcu_n_exp_nodelay;\n\tbool sda_is_static;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tlong unsigned int reschedule_jiffies;\n\tlong unsigned int reschedule_count;\n\tstruct delayed_work work;\n\tstruct srcu_struct *srcu_ssp;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_usage srcuu;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nstruct srp_cmd {\n\tu8 opcode;\n\tu8 sol_not;\n\tu8 reserved1[3];\n\tu8 buf_fmt;\n\tu8 data_out_desc_cnt;\n\tu8 data_in_desc_cnt;\n\tu64 tag;\n\tu8 reserved2[4];\n\tstruct scsi_lun lun;\n\tu8 reserved3;\n\tu8 task_attr;\n\tu8 reserved4;\n\tu8 add_cdb_len;\n\tu8 cdb[16];\n\tu8 add_data[0];\n};\n\nstruct srp_direct_buf {\n\t__be64 va;\n\t__be32 key;\n\t__be32 len;\n};\n\nstruct viosrp_crq {\n\tunion {\n\t\t__be64 high;\n\t\tstruct {\n\t\t\tu8 valid;\n\t\t\tu8 format;\n\t\t\tu8 reserved;\n\t\t\tu8 status;\n\t\t\t__be16 timeout;\n\t\t\t__be16 IU_length;\n\t\t};\n\t};\n\t__be64 IU_data_ptr;\n};\n\nstruct srp_login_req {\n\tu8 opcode;\n\tu8 reserved1[7];\n\tu64 tag;\n\t__be32 req_it_iu_len;\n\tu8 reserved2[4];\n\t__be16 req_buf_fmt;\n\tu8 req_flags;\n\tu8 reserved3[1];\n\t__be16 imm_data_offset;\n\tu8 reserved4[2];\n\tu8 initiator_port_id[16];\n\tu8 target_port_id[16];\n};\n\nstruct srp_login_rsp {\n\tu8 opcode;\n\tu8 reserved1[3];\n\t__be32 req_lim_delta;\n\tu64 tag;\n\t__be32 max_it_iu_len;\n\t__be32 max_ti_iu_len;\n\t__be16 buf_fmt;\n\tu8 rsp_flags;\n\tu8 reserved2[25];\n} __attribute__((packed));\n\nstruct srp_login_rej {\n\tu8 opcode;\n\tu8 reserved1[3];\n\t__be32 reason;\n\tu64 tag;\n\tu8 reserved2[8];\n\t__be16 buf_fmt;\n\tu8 reserved3[6];\n};\n\nstruct srp_i_logout {\n\tu8 opcode;\n\tu8 reserved[7];\n\tu64 tag;\n};\n\nstruct srp_t_logout {\n\tu8 opcode;\n\tu8 sol_not;\n\tu8 reserved[2];\n\t__be32 reason;\n\tu64 tag;\n};\n\nstruct srp_tsk_mgmt {\n\tu8 opcode;\n\tu8 sol_not;\n\tu8 reserved1[6];\n\tu64 tag;\n\tu8 reserved2[4];\n\tstruct scsi_lun lun;\n\tu8 reserved3[2];\n\tu8 tsk_mgmt_func;\n\tu8 reserved4;\n\tu64 task_tag;\n\tu8 reserved5[8];\n};\n\nstruct srp_rsp {\n\tu8 opcode;\n\tu8 sol_not;\n\tu8 reserved1[2];\n\t__be32 req_lim_delta;\n\tu64 tag;\n\tu8 reserved2[2];\n\tu8 flags;\n\tu8 status;\n\t__be32 data_out_res_cnt;\n\t__be32 data_in_res_cnt;\n\t__be32 sense_data_len;\n\t__be32 resp_data_len;\n\tu8 data[0];\n} __attribute__((packed));\n\nunion srp_iu {\n\tstruct srp_login_req login_req;\n\tstruct srp_login_rsp login_rsp;\n\tstruct srp_login_rej login_rej;\n\tstruct srp_i_logout i_logout;\n\tstruct srp_t_logout t_logout;\n\tstruct srp_tsk_mgmt tsk_mgmt;\n\tstruct srp_cmd cmd;\n\tstruct srp_rsp rsp;\n\tu8 reserved[256];\n};\n\nunion viosrp_iu {\n\tunion srp_iu srp;\n\tunion mad_iu mad;\n};\n\nstruct srp_event_struct {\n\tunion viosrp_iu *xfer_iu;\n\tstruct scsi_cmnd *cmnd;\n\tstruct list_head list;\n\tvoid (*done)(struct srp_event_struct *);\n\tstruct viosrp_crq crq;\n\tstruct ibmvscsi_host_data *hostdata;\n\tatomic_t free;\n\tunion viosrp_iu iu;\n\tvoid (*cmnd_done)(struct scsi_cmnd *);\n\tstruct completion comp;\n\tstruct timer_list timer;\n\tunion viosrp_iu *sync_srp;\n\tstruct srp_direct_buf *ext_list;\n\tdma_addr_t ext_list_token;\n};\n\nstruct srp_rport;\n\nstruct srp_function_template {\n\tbool has_rport_state;\n\tbool reset_timer_if_blocked;\n\tint *reconnect_delay;\n\tint *fast_io_fail_tmo;\n\tint *dev_loss_tmo;\n\tint (*reconnect)(struct srp_rport *);\n\tvoid (*terminate_rport_io)(struct srp_rport *);\n\tvoid (*rport_delete)(struct srp_rport *);\n};\n\nstruct srp_host_attrs {\n\tatomic_t next_port_id;\n};\n\nstruct srp_indirect_buf {\n\tstruct srp_direct_buf table_desc;\n\t__be32 len;\n\tstruct srp_direct_buf desc_list[0];\n} __attribute__((packed));\n\nstruct srp_internal {\n\tstruct scsi_transport_template t;\n\tstruct srp_function_template *f;\n\tstruct device_attribute *host_attrs[1];\n\tstruct device_attribute *rport_attrs[9];\n\tstruct transport_container rport_attr_cont;\n};\n\nstruct srp_rport {\n\tstruct device dev;\n\tu8 port_id[16];\n\tu8 roles;\n\tvoid *lld_data;\n\tstruct mutex mutex;\n\tenum srp_rport_state state;\n\tint reconnect_delay;\n\tint failed_reconnects;\n\tstruct delayed_work reconnect_work;\n\tint fast_io_fail_tmo;\n\tint dev_loss_tmo;\n\tstruct delayed_work fast_io_fail_work;\n\tstruct delayed_work dev_loss_work;\n};\n\nstruct srp_rport_identifiers {\n\tu8 port_id[16];\n\tu8 roles;\n};\n\nstruct ss_tmp {\n\tenum ss_state state;\n\tlong unsigned int data;\n\tspinlock_t *lock;\n\tspinlock_t *lock_irqsave;\n};\n\nstruct stack_record;\n\nstruct stack {\n\tstruct stack_record *stack_record;\n\tstruct stack *next;\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[0];\n};\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tu64 data[0];\n};\n\nstruct stack_print_ctx {\n\tstruct stack *stack;\n\tu8 flags;\n};\n\nstruct stack_record {\n\tstruct list_head hash_list;\n\tu32 hash;\n\tu32 size;\n\tunion handle_parts handle;\n\trefcount_t count;\n\tunion {\n\t\tlong unsigned int entries[64];\n\t\tstruct {\n\t\t\tstruct list_head free_list;\n\t\t\tlong unsigned int rcu_state;\n\t\t};\n\t};\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\nstruct stashed_operations {\n\tstruct dentry * (*stash_dentry)(struct dentry **, struct dentry *);\n\tvoid (*put_data)(void *);\n\tint (*init_inode)(struct inode *, void *);\n};\n\nstruct stat {\n\tlong unsigned int st_dev;\n\t__kernel_ino_t st_ino;\n\tlong unsigned int st_nlink;\n\t__kernel_mode_t st_mode;\n\t__kernel_uid32_t st_uid;\n\t__kernel_gid32_t st_gid;\n\tlong unsigned int st_rdev;\n\tlong int st_size;\n\tlong unsigned int st_blksize;\n\tlong unsigned int st_blocks;\n\tlong unsigned int st_atime;\n\tlong unsigned int st_atime_nsec;\n\tlong unsigned int st_mtime;\n\tlong unsigned int st_mtime_nsec;\n\tlong unsigned int st_ctime;\n\tlong unsigned int st_ctime_nsec;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n\tlong unsigned int __unused6;\n};\n\nstruct stat64 {\n\tlong long unsigned int st_dev;\n\tlong long unsigned int st_ino;\n\tunsigned int st_mode;\n\tunsigned int st_nlink;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tlong long unsigned int st_rdev;\n\tshort unsigned int __pad2;\n\tlong long int st_size;\n\tint st_blksize;\n\tlong long int st_blocks;\n\tint st_atime;\n\tunsigned int st_atime_nsec;\n\tint st_mtime;\n\tunsigned int st_mtime_nsec;\n\tint st_ctime;\n\tunsigned int st_ctime_nsec;\n\tunsigned int __unused4;\n\tunsigned int __unused5;\n};\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct tracer_stat;\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct statfs {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__kernel_long_t f_blocks;\n\t__kernel_long_t f_bfree;\n\t__kernel_long_t f_bavail;\n\t__kernel_long_t f_files;\n\t__kernel_long_t f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct statfs64 {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct static_call_key {\n\tvoid *func;\n};\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct static_tree_desc_s {\n\tconst ct_data *static_tree;\n\tconst int *extra_bits;\n\tint extra_base;\n\tint elems;\n\tint max_length;\n};\n\nstruct stats_reply_data {\n\tstruct ethnl_reply_data base;\n\tunion {\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t};\n\t\tstruct {\n\t\t\tstruct ethtool_eth_phy_stats phy_stats;\n\t\t\tstruct ethtool_eth_mac_stats mac_stats;\n\t\t\tstruct ethtool_eth_ctrl_stats ctrl_stats;\n\t\t\tstruct ethtool_rmon_stats rmon_stats;\n\t\t\tstruct ethtool_phy_stats phydev_stats;\n\t\t} stats;\n\t};\n\tconst struct ethtool_rmon_hist_range *rmon_ranges;\n};\n\nstruct stats_req_info {\n\tstruct ethnl_req_info base;\n\tlong unsigned int stat_mask[1];\n\tenum ethtool_mac_stats_src src;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u32 stx_dio_mem_align;\n\t__u32 stx_dio_offset_align;\n\t__u64 stx_subvol;\n\t__u32 stx_atomic_write_unit_min;\n\t__u32 stx_atomic_write_unit_max;\n\t__u32 stx_atomic_write_segments_max;\n\t__u32 stx_dio_read_offset_align;\n\t__u32 stx_atomic_write_unit_max_opt;\n\t__u32 __spare2[1];\n\t__u64 __spare3[8];\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct stop_psscr_table {\n\tu64 val;\n\tu64 mask;\n};\n\nstruct strarray {\n\tchar **array;\n\tsize_t n;\n};\n\nstruct stress_hpt_struct {\n\tlong unsigned int last_group[16];\n};\n\nstruct strip_zone {\n\tsector_t zone_end;\n\tsector_t dev_start;\n\tint nb_dev;\n\tint disk_shift;\n};\n\nstruct stripe {\n\tstruct dm_dev *dev;\n\tsector_t physical_start;\n\tatomic_t error_count;\n};\n\nstruct stripe_c {\n\tuint32_t stripes;\n\tint stripes_shift;\n\tsector_t stripe_width;\n\tuint32_t chunk_size;\n\tint chunk_size_shift;\n\tstruct dm_target *ti;\n\tstruct work_struct trigger_event;\n\tstruct stripe stripe[0];\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[23];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tint wait;\n\tint retval;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tconst struct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tconst struct bus_type *bus;\n\tstruct device *dev_root;\n\tstruct kset glue_dirs;\n\tconst struct class *class;\n\tstruct lock_class_key lock_key;\n};\n\nstruct subsys_tbl_ent {\n\tu16 subsys_vendor;\n\tu16 subsys_devid;\n\tu32 phy_id;\n};\n\nstruct sunrpc_net {\n\tstruct proc_dir_entry *proc_net_rpc;\n\tstruct cache_detail *ip_map_cache;\n\tstruct cache_detail *unix_gid_cache;\n\tstruct cache_detail *rsc_cache;\n\tstruct cache_detail *rsi_cache;\n\tstruct super_block *pipefs_sb;\n\tstruct rpc_pipe *gssd_dummy;\n\tstruct mutex pipefs_sb_lock;\n\tstruct list_head all_clients;\n\tspinlock_t rpc_client_lock;\n\tstruct rpc_clnt *rpcb_local_clnt;\n\tstruct rpc_clnt *rpcb_local_clnt4;\n\tspinlock_t rpcb_clnt_lock;\n\tunsigned int rpcb_users;\n\tunsigned int rpcb_is_af_local: 1;\n\tstruct mutex gssp_lock;\n\tstruct rpc_clnt *gssp_clnt;\n\tint use_gss_proxy;\n\tint pipe_version;\n\tatomic_t pipe_users;\n\tstruct proc_dir_entry *use_gssp_proc;\n\tstruct proc_dir_entry *gss_krb5_enctypes;\n};\n\ntypedef struct super_block *class_super_write_t;\n\nstruct mtd_info;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tvoid *s_security;\n\tconst struct xattr_handler * const *s_xattr;\n\tstruct hlist_bl_head s_roots;\n\tstruct mount *s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct file *s_bdev_file;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\tu32 s_fsnotify_mask;\n\tstruct fsnotify_sb_info *s_fsnotify_info;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tu8 s_uuid_len;\n\tchar s_sysfs_name[37];\n\tunsigned int s_max_links;\n\tunsigned int s_d_flags;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *__s_d_op;\n\tstruct shrinker *s_shrink;\n\tatomic_long_t s_remove_count;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong int s_min_writeback_pages;\n\trefcount_t s_pending_errors;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *, enum freeze_holder, const void *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n\tint (*remove_bdev)(struct super_block *, struct block_device *);\n\tvoid (*shutdown)(struct super_block *);\n\tvoid (*report_error)(const struct fserror_event *);\n};\n\nstruct super_type {\n\tchar *name;\n\tstruct module *owner;\n\tint (*load_super)(struct md_rdev *, struct md_rdev *, int);\n\tint (*validate_super)(struct mddev *, struct md_rdev *, struct md_rdev *);\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tlong long unsigned int (*rdev_size_change)(struct md_rdev *, sector_t);\n\tint (*allow_new_offset)(struct md_rdev *, long long unsigned int);\n};\n\nstruct superblock_security_struct {\n\tu32 sid;\n\tu32 def_sid;\n\tu32 mntpoint_sid;\n\tu32 creator_sid;\n\tshort unsigned int behavior;\n\tshort unsigned int flags;\n\tstruct mutex lock;\n\tstruct list_head isec_head;\n\tspinlock_t isec_lock;\n};\n\nstruct supplier_bindings {\n\tstruct device_node * (*parse_prop)(struct device_node *, const char *, int);\n\tstruct device_node * (*get_con_dev)(struct device_node *);\n\tbool optional;\n\tu8 fwlink_flags;\n};\n\nstruct suspend_stats {\n\tunsigned int step_failures[8];\n\tunsigned int success;\n\tunsigned int fail;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tu64 last_hw_sleep;\n\tu64 total_hw_sleep;\n\tu64 max_hw_sleep;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nstruct svc_deferred_req {\n\tu32 prot;\n\tstruct svc_xprt *xprt;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tstruct __kernel_sockaddr_storage daddr;\n\tsize_t daddrlen;\n\tvoid *xprt_ctxt;\n\tstruct cache_deferred_req handle;\n\tint argslen;\n\t__be32 args[0];\n};\n\nstruct svc_info {\n\tstruct svc_serv *serv;\n\tstruct mutex *mutex;\n};\n\nstruct svc_pool {\n\tunsigned int sp_id;\n\tunsigned int sp_nrthreads;\n\tunsigned int sp_nrthrmin;\n\tunsigned int sp_nrthrmax;\n\tstruct lwq sp_xprts;\n\tstruct list_head sp_all_threads;\n\tstruct llist_head sp_idle_threads;\n\tstruct percpu_counter sp_messages_arrived;\n\tstruct percpu_counter sp_sockets_queued;\n\tstruct percpu_counter sp_threads_woken;\n\tlong unsigned int sp_flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct svc_pool_map {\n\tint count;\n\tint mode;\n\tunsigned int npools;\n\tunsigned int *pool_to;\n\tunsigned int *to_pool;\n};\n\nstruct svc_procedure {\n\t__be32 (*pc_func)(struct svc_rqst *);\n\tbool (*pc_decode)(struct svc_rqst *, struct xdr_stream *);\n\tbool (*pc_encode)(struct svc_rqst *, struct xdr_stream *);\n\tvoid (*pc_release)(struct svc_rqst *);\n\tunsigned int pc_argsize;\n\tunsigned int pc_argzero;\n\tunsigned int pc_ressize;\n\tunsigned int pc_cachetype;\n\tunsigned int pc_xdrressize;\n\tconst char *pc_name;\n};\n\nstruct svc_process_info {\n\tunion {\n\t\tint (*dispatch)(struct svc_rqst *);\n\t\tstruct {\n\t\t\tunsigned int lovers;\n\t\t\tunsigned int hivers;\n\t\t} mismatch;\n\t};\n};\n\nstruct svc_version;\n\nstruct svc_program {\n\tu32 pg_prog;\n\tunsigned int pg_lovers;\n\tunsigned int pg_hivers;\n\tunsigned int pg_nvers;\n\tconst struct svc_version **pg_vers;\n\tchar *pg_name;\n\tchar *pg_class;\n\tenum svc_auth_status (*pg_authenticate)(struct svc_rqst *);\n\t__be32 (*pg_init_request)(struct svc_rqst *, const struct svc_program *, struct svc_process_info *);\n\tint (*pg_rpcbind_set)(struct net *, const struct svc_program *, u32, int, short unsigned int, short unsigned int);\n};\n\nstruct xdr_stream {\n\t__be32 *p;\n\tstruct xdr_buf *buf;\n\t__be32 *end;\n\tstruct kvec *iov;\n\tstruct kvec scratch;\n\tstruct page **page_ptr;\n\tvoid *page_kaddr;\n\tunsigned int nwords;\n\tstruct rpc_rqst *rqst;\n};\n\nstruct svc_rqst {\n\tstruct list_head rq_all;\n\tstruct llist_node rq_idle;\n\tstruct callback_head rq_rcu_head;\n\tstruct svc_xprt *rq_xprt;\n\tstruct __kernel_sockaddr_storage rq_addr;\n\tsize_t rq_addrlen;\n\tstruct __kernel_sockaddr_storage rq_daddr;\n\tsize_t rq_daddrlen;\n\tstruct svc_serv *rq_server;\n\tstruct svc_pool *rq_pool;\n\tconst struct svc_procedure *rq_procinfo;\n\tstruct auth_ops *rq_authop;\n\tstruct svc_cred rq_cred;\n\tvoid *rq_xprt_ctxt;\n\tstruct svc_deferred_req *rq_deferred;\n\tstruct xdr_buf rq_arg;\n\tstruct xdr_stream rq_arg_stream;\n\tstruct xdr_stream rq_res_stream;\n\tstruct folio *rq_scratch_folio;\n\tstruct xdr_buf rq_res;\n\tlong unsigned int rq_maxpages;\n\tstruct page **rq_pages;\n\tstruct page **rq_respages;\n\tstruct page **rq_next_page;\n\tstruct page **rq_page_end;\n\tstruct folio_batch rq_fbatch;\n\tstruct bio_vec *rq_bvec;\n\t__be32 rq_xid;\n\tu32 rq_prog;\n\tu32 rq_vers;\n\tu32 rq_proc;\n\tu32 rq_prot;\n\tint rq_cachetype;\n\tlong unsigned int rq_flags;\n\tktime_t rq_qtime;\n\tvoid *rq_argp;\n\tvoid *rq_resp;\n\t__be32 *rq_accept_statp;\n\tvoid *rq_auth_data;\n\t__be32 rq_auth_stat;\n\tint rq_auth_slack;\n\tint rq_reserved;\n\tktime_t rq_stime;\n\tstruct cache_req rq_chandle;\n\tstruct auth_domain *rq_client;\n\tstruct auth_domain *rq_gssclient;\n\tstruct task_struct *rq_task;\n\tstruct net *rq_bc_net;\n\tint rq_err;\n\tlong unsigned int bc_to_initval;\n\tunsigned int bc_to_retries;\n\tunsigned int rq_status_counter;\n\tvoid **rq_lease_breaker;\n};\n\nstruct svc_stat;\n\nstruct svc_serv {\n\tstruct svc_program *sv_programs;\n\tstruct svc_stat *sv_stats;\n\tspinlock_t sv_lock;\n\tunsigned int sv_nprogs;\n\tunsigned int sv_nrthreads;\n\tunsigned int sv_max_payload;\n\tunsigned int sv_max_mesg;\n\tunsigned int sv_xdrsize;\n\tstruct list_head sv_permsocks;\n\tstruct list_head sv_tempsocks;\n\tint sv_tmpcnt;\n\tstruct timer_list sv_temptimer;\n\tchar *sv_name;\n\tunsigned int sv_nrpools;\n\tbool sv_is_pooled;\n\tstruct svc_pool *sv_pools;\n\tint (*sv_threadfn)(void *);\n\tstruct lwq sv_cb_list;\n\tbool sv_bc_enabled;\n};\n\nstruct svc_xprt_class;\n\nstruct svc_xprt_ops;\n\nstruct svc_xprt {\n\tstruct svc_xprt_class *xpt_class;\n\tconst struct svc_xprt_ops *xpt_ops;\n\tstruct kref xpt_ref;\n\tktime_t xpt_qtime;\n\tstruct list_head xpt_list;\n\tstruct lwq_node xpt_ready;\n\tlong unsigned int xpt_flags;\n\tstruct svc_serv *xpt_server;\n\tatomic_t xpt_reserved;\n\tatomic_t xpt_nr_rqsts;\n\tstruct mutex xpt_mutex;\n\tspinlock_t xpt_lock;\n\tvoid *xpt_auth_cache;\n\tstruct list_head xpt_deferred;\n\tstruct __kernel_sockaddr_storage xpt_local;\n\tsize_t xpt_locallen;\n\tstruct __kernel_sockaddr_storage xpt_remote;\n\tsize_t xpt_remotelen;\n\tchar xpt_remotebuf[58];\n\tstruct list_head xpt_users;\n\tstruct net *xpt_net;\n\tnetns_tracker ns_tracker;\n\tconst struct cred *xpt_cred;\n\tstruct rpc_xprt *xpt_bc_xprt;\n\tstruct rpc_xprt_switch *xpt_bc_xps;\n};\n\nstruct svc_sock {\n\tstruct svc_xprt sk_xprt;\n\tstruct socket *sk_sock;\n\tstruct sock *sk_sk;\n\tvoid (*sk_ostate)(struct sock *);\n\tvoid (*sk_odata)(struct sock *);\n\tvoid (*sk_owspace)(struct sock *);\n\tstruct bio_vec *sk_bvec;\n\t__be32 sk_marker;\n\tu32 sk_tcplen;\n\tu32 sk_datalen;\n\tstruct page_frag_cache sk_frag_cache;\n\tstruct completion sk_handshake_done;\n\tlong unsigned int sk_maxpages;\n\tstruct page *sk_pages[0];\n};\n\nstruct svc_stat {\n\tstruct svc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcbadfmt;\n\tunsigned int rpcbadauth;\n\tunsigned int rpcbadclnt;\n};\n\nstruct svc_version {\n\tu32 vs_vers;\n\tu32 vs_nproc;\n\tconst struct svc_procedure *vs_proc;\n\tlong unsigned int *vs_count;\n\tu32 vs_xdrsize;\n\tbool vs_hidden;\n\tbool vs_rpcb_optnl;\n\tbool vs_need_cong_ctrl;\n\tint (*vs_dispatch)(struct svc_rqst *);\n};\n\nstruct svc_xprt_class {\n\tconst char *xcl_name;\n\tstruct module *xcl_owner;\n\tconst struct svc_xprt_ops *xcl_ops;\n\tstruct list_head xcl_list;\n\tu32 xcl_max_payload;\n\tint xcl_ident;\n};\n\nstruct svc_xprt_ops {\n\tstruct svc_xprt * (*xpo_create)(struct svc_serv *, struct net *, struct sockaddr *, int, int);\n\tstruct svc_xprt * (*xpo_accept)(struct svc_xprt *);\n\tint (*xpo_has_wspace)(struct svc_xprt *);\n\tint (*xpo_recvfrom)(struct svc_rqst *);\n\tint (*xpo_sendto)(struct svc_rqst *);\n\tint (*xpo_result_payload)(struct svc_rqst *, unsigned int, unsigned int);\n\tvoid (*xpo_release_ctxt)(struct svc_xprt *, void *);\n\tvoid (*xpo_detach)(struct svc_xprt *);\n\tvoid (*xpo_free)(struct svc_xprt *);\n\tvoid (*xpo_kill_temp_xprt)(struct svc_xprt *);\n\tvoid (*xpo_handshake)(struct svc_xprt *);\n};\n\nstruct svc_xpt_user {\n\tstruct list_head list;\n\tvoid (*callback)(struct svc_xpt_user *);\n};\n\nstruct sw842_param {\n\tu8 *in;\n\tu8 bit;\n\tu64 ilen;\n\tu8 *out;\n\tu8 *ostart;\n\tu64 olen;\n};\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct swap_cgroup {\n\tatomic_t ids;\n};\n\nstruct swap_cgroup_ctrl {\n\tstruct swap_cgroup *map;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tu16 count;\n\tu8 flags;\n\tu8 order;\n\tatomic_long_t *table;\n\tstruct list_head list;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tsector_t start_block;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[65526];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_sequential_cluster;\n\nstruct swap_info_struct {\n\tstruct percpu_ref users;\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tlong unsigned int *zeromap;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct list_head free_clusters;\n\tstruct list_head full_clusters;\n\tstruct list_head nonfull_clusters[1];\n\tstruct list_head frag_clusters[1];\n\tunsigned int pages;\n\tatomic_long_t inuse_pages;\n\tstruct swap_sequential_cluster *global_cluster;\n\tspinlock_t global_cluster_lock;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tstruct completion comp;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct work_struct reclaim_work;\n\tstruct list_head discard_clusters;\n\tstruct plist_node avail_list;\n};\n\nstruct swap_iocb {\n\tstruct kiocb iocb;\n\tstruct bio_vec bvec[32];\n\tint pages;\n\tint len;\n};\n\nstruct swap_sequential_cluster {\n\tunsigned int next[1];\n};\n\nstruct swap_table {\n\tatomic_long_t entries[256];\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n};\n\nstruct swmii_regs {\n\tu16 bmsr;\n\tu16 lpa;\n\tu16 lpagb;\n\tu16 estat;\n};\n\nstruct swnode {\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tint id;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n\tunsigned int managed: 1;\n};\n\nstruct sym_count_ctx {\n\tunsigned int count;\n\tconst char *name;\n};\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst u32 *crcs;\n\tenum mod_license license;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tbool pt_port_open;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct sync_io {\n\tlong unsigned int error_bits;\n\tstruct completion wait;\n};\n\nstruct sys_off_data {\n\tint mode;\n\tvoid *cb_data;\n\tconst char *cmd;\n\tstruct device *dev;\n};\n\nstruct sys_off_handler {\n\tstruct notifier_block nb;\n\tint (*sys_off_cb)(struct sys_off_data *);\n\tvoid *cb_data;\n\tenum sys_off_mode mode;\n\tbool blocking;\n\tvoid *list;\n\tstruct device *dev;\n};\n\nstruct syscall_args {\n\tchar *ptr_array[3];\n\tint read[3];\n\tint uargs;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\nstruct syscall_metadata {\n\tconst char *name;\n\tint syscall_nr;\n\tu8 nb_args: 7;\n\tu8 user_arg_is_str: 1;\n\ts8 user_arg_size;\n\tshort int user_mask;\n\tconst char **types;\n\tconst char **args;\n\tstruct list_head enter_fields;\n\tstruct trace_event_call *enter_event;\n\tstruct trace_event_call *exit_event;\n};\n\nstruct syscall_tp_t {\n\tstruct trace_entry ent;\n\tint syscall_nr;\n\tlong unsigned int ret;\n};\n\nstruct syscall_tp_t___2 {\n\tstruct trace_entry ent;\n\tint syscall_nr;\n\tlong unsigned int args[6];\n};\n\nstruct syscall_trace_enter {\n\tstruct trace_entry ent;\n\tint nr;\n\tlong unsigned int args[0];\n};\n\nstruct syscall_trace_exit {\n\tstruct trace_entry ent;\n\tint nr;\n\tlong int ret;\n};\n\nstruct trace_user_buf;\n\nstruct trace_user_buf_info {\n\tstruct trace_user_buf *tbuf;\n\tsize_t size;\n\tint ref;\n};\n\nstruct syscall_user_buffer {\n\tstruct trace_user_buf_info buf;\n\tstruct callback_head rcu;\n};\n\nstruct syscall_user_dispatch {};\n\nstruct syscore_ops;\n\nstruct syscore {\n\tstruct list_head node;\n\tconst struct syscore_ops *ops;\n\tvoid *data;\n};\n\nstruct syscore_ops {\n\tint (*suspend)(void *);\n\tvoid (*resume)(void *);\n\tvoid (*shutdown)(void *);\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct sysfs_wi_group {\n\tstruct kobject wi_kobj;\n\tstruct mutex kobj_lock;\n\tstruct iw_node_attr *nattrs[0];\n};\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[0];\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(u8);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[12];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tunsigned int shift;\n\tunsigned int shift_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[12];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tenum clocksource_ids cs_id;\n\tbool use_nsecs;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t boot;\n\tktime_t raw;\n\tenum clocksource_ids cs_id;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n};\n\nstruct systemcfg {\n\t__u8 eye_catcher[16];\n\tstruct {\n\t\t__u32 major;\n\t\t__u32 minor;\n\t} version;\n\t__u32 platform;\n\t__u32 processor;\n\t__u64 processorCount;\n\t__u64 physicalMemorySize;\n\t__u64 tb_orig_stamp;\n\t__u64 tb_ticks_per_sec;\n\t__u64 tb_to_xs;\n\t__u64 stamp_xsec;\n\t__u64 tb_update_count;\n\t__u32 tz_minuteswest;\n\t__u32 tz_dsttime;\n\t__u32 dcache_size;\n\t__u32 dcache_line_size;\n\t__u32 icache_size;\n\t__u32 icache_line_size;\n};\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\nstruct table_device {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev dm_dev;\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tconst char *desc;\n};\n\ntypedef int (*dm_ctr_fn)(struct dm_target *, unsigned int, char **);\n\ntypedef void (*dm_dtr_fn)(struct dm_target *);\n\ntypedef int (*dm_map_fn)(struct dm_target *, struct bio *);\n\ntypedef int (*dm_clone_and_map_request_fn)(struct dm_target *, struct request *, union map_info *, struct request **);\n\ntypedef void (*dm_release_clone_request_fn)(struct request *, union map_info *);\n\ntypedef int (*dm_endio_fn)(struct dm_target *, struct bio *, blk_status_t *);\n\ntypedef int (*dm_request_endio_fn)(struct dm_target *, struct request *, blk_status_t, union map_info *);\n\ntypedef void (*dm_presuspend_fn)(struct dm_target *);\n\ntypedef void (*dm_presuspend_undo_fn)(struct dm_target *);\n\ntypedef void (*dm_postsuspend_fn)(struct dm_target *);\n\ntypedef int (*dm_preresume_fn)(struct dm_target *);\n\ntypedef void (*dm_resume_fn)(struct dm_target *);\n\ntypedef void (*dm_status_fn)(struct dm_target *, status_type_t, unsigned int, char *, unsigned int);\n\ntypedef int (*dm_message_fn)(struct dm_target *, unsigned int, char **, char *, unsigned int);\n\ntypedef int (*dm_prepare_ioctl_fn)(struct dm_target *, struct block_device **, unsigned int, long unsigned int, bool *);\n\ntypedef int (*dm_report_zones_fn)(struct dm_target *);\n\ntypedef int (*dm_busy_fn)(struct dm_target *);\n\ntypedef int (*iterate_devices_callout_fn)(struct dm_target *, struct dm_dev *, sector_t, sector_t, void *);\n\ntypedef int (*dm_iterate_devices_fn)(struct dm_target *, iterate_devices_callout_fn, void *);\n\ntypedef void (*dm_io_hints_fn)(struct dm_target *, struct queue_limits *);\n\ntypedef long int (*dm_dax_direct_access_fn)(struct dm_target *, long unsigned int, long int, enum dax_access_mode, void **, long unsigned int *);\n\ntypedef int (*dm_dax_zero_page_range_fn)(struct dm_target *, long unsigned int, size_t);\n\ntypedef size_t (*dm_dax_recovery_write_fn)(struct dm_target *, long unsigned int, void *, size_t, struct iov_iter *);\n\nstruct target_type {\n\tuint64_t features;\n\tconst char *name;\n\tstruct module *module;\n\tunsigned int version[3];\n\tdm_ctr_fn ctr;\n\tdm_dtr_fn dtr;\n\tdm_map_fn map;\n\tdm_clone_and_map_request_fn clone_and_map_rq;\n\tdm_release_clone_request_fn release_clone_rq;\n\tdm_endio_fn end_io;\n\tdm_request_endio_fn rq_end_io;\n\tdm_presuspend_fn presuspend;\n\tdm_presuspend_undo_fn presuspend_undo;\n\tdm_postsuspend_fn postsuspend;\n\tdm_preresume_fn preresume;\n\tdm_resume_fn resume;\n\tdm_status_fn status;\n\tdm_message_fn message;\n\tdm_prepare_ioctl_fn prepare_ioctl;\n\tdm_report_zones_fn report_zones;\n\tdm_busy_fn busy;\n\tdm_iterate_devices_fn iterate_devices;\n\tdm_io_hints_fn io_hints;\n\tdm_dax_direct_access_fn direct_access;\n\tdm_dax_zero_page_range_fn dax_zero_page_range;\n\tdm_dax_recovery_write_fn dax_recovery_write;\n\tstruct list_head list;\n};\n\nstruct task_delay_info {\n\traw_spinlock_t lock;\n\tu64 blkio_start;\n\tu64 blkio_delay_max;\n\tu64 blkio_delay_min;\n\tu64 blkio_delay;\n\tu64 swapin_start;\n\tu64 swapin_delay_max;\n\tu64 swapin_delay_min;\n\tu64 swapin_delay;\n\tu32 blkio_count;\n\tu32 swapin_count;\n\tu64 freepages_start;\n\tu64 freepages_delay_max;\n\tu64 freepages_delay_min;\n\tu64 freepages_delay;\n\tu64 thrashing_start;\n\tu64 thrashing_delay_max;\n\tu64 thrashing_delay_min;\n\tu64 thrashing_delay;\n\tu64 compact_start;\n\tu64 compact_delay_max;\n\tu64 compact_delay_min;\n\tu64 compact_delay;\n\tu64 wpcopy_start;\n\tu64 wpcopy_delay_max;\n\tu64 wpcopy_delay_min;\n\tu64 wpcopy_delay;\n\tu64 irq_delay_max;\n\tu64 irq_delay_min;\n\tu64 irq_delay;\n\tu32 freepages_count;\n\tu32 thrashing_count;\n\tu32 compact_count;\n\tu32 wpcopy_count;\n\tu32 irq_count;\n\tstruct timespec64 blkio_delay_max_ts;\n\tstruct timespec64 swapin_delay_max_ts;\n\tstruct timespec64 freepages_delay_max_ts;\n\tstruct timespec64 thrashing_delay_max_ts;\n\tstruct timespec64 compact_delay_max_ts;\n\tstruct timespec64 wpcopy_delay_max_ts;\n\tstruct timespec64 irq_delay_max_ts;\n};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tint idle;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t load_avg;\n\tstruct scx_task_group scx;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct autogroup *autogroup;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_numa_env {\n\tstruct task_struct *p;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tint imb_numa_nr;\n\tstruct numa_stats src_stats;\n\tstruct numa_stats dst_stats;\n\tint imbalance_pct;\n\tint dist;\n\tstruct task_struct *best_task;\n\tlong int best_imp;\n\tint best_cpu;\n};\n\nstruct task_security_struct {\n\tstruct {\n\t\tu32 sid;\n\t\tu32 seqno;\n\t\tunsigned int dir_spot;\n\t\tstruct avdc_entry dir[4];\n\t\tbool permissive_neveraudit;\n\t} avdcache;\n};\n\ntypedef struct task_struct *class_find_get_task_t;\n\nstruct thread_info {\n\tint preempt_count;\n\tunsigned int cpu;\n\tlong unsigned int local_flags;\n\tunsigned char slb_preload_nr;\n\tunsigned char slb_preload_tail;\n\tu32 slb_preload_esid[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vtime {\n\tseqcount_t seqcount;\n\tlong long unsigned int starttime;\n\tenum vtime_state state;\n\tunsigned int cpu;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct tlbflush_unmap_batch {};\n\nstruct thread_struct {\n\tlong unsigned int ksp;\n\tlong unsigned int ksp_vsid;\n\tstruct pt_regs *regs;\n\tstruct debug_reg debug;\n\tlong: 64;\n\tstruct thread_fp_state fp_state;\n\tstruct thread_fp_state *fp_save_area;\n\tint fpexc_mode;\n\tunsigned int align_ctl;\n\tstruct perf_event *ptrace_bps[2];\n\tstruct arch_hw_breakpoint hw_brk[2];\n\tlong unsigned int trap_nr;\n\tu8 load_slb;\n\tu8 load_fp;\n\tu8 load_vec;\n\tlong: 0;\n\tstruct thread_vr_state vr_state;\n\tstruct thread_vr_state *vr_save_area;\n\tlong unsigned int vrsave;\n\tint used_vr;\n\tint used_vsr;\n\tu8 load_tm;\n\tu64 tm_tfhar;\n\tu64 tm_texasr;\n\tu64 tm_tfiar;\n\tstruct pt_regs ckpt_regs;\n\tlong unsigned int tm_tar;\n\tlong unsigned int tm_ppr;\n\tlong unsigned int tm_dscr;\n\tlong unsigned int tm_amr;\n\tlong: 64;\n\tstruct thread_fp_state ckfp_state;\n\tstruct thread_vr_state ckvr_state;\n\tlong unsigned int ckvrsave;\n\tlong unsigned int dscr;\n\tlong unsigned int fscr;\n\tint dscr_inherit;\n\tlong unsigned int tidr;\n\tlong unsigned int tar;\n\tlong unsigned int ebbrr;\n\tlong unsigned int ebbhr;\n\tlong unsigned int bescr;\n\tlong unsigned int siar;\n\tlong unsigned int sdar;\n\tlong unsigned int sier;\n\tlong unsigned int mmcr2;\n\tunsigned int mmcr0;\n\tunsigned int used_ebb;\n\tlong unsigned int mmcr3;\n\tlong unsigned int sier2;\n\tlong unsigned int sier3;\n\tlong unsigned int hashkeyr;\n\tlong unsigned int dexcr;\n\tlong unsigned int dexcr_onexec;\n};\n\nstruct uprobe_task;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tunsigned int __state;\n\tunsigned int saved_state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tstruct sched_dl_entity dl;\n\tstruct sched_dl_entity *dl_server;\n\tstruct sched_ext_entity scx;\n\tconst struct sched_class *sched_class;\n\tstruct task_group *sched_task_group;\n\tstruct callback_head sched_throttle_work;\n\tstruct list_head throttle_node;\n\tbool throttled;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_statistics stats;\n\tstruct hlist_head preempt_notifiers;\n\tunsigned int btrace_seq;\n\tunsigned int policy;\n\tlong unsigned int max_allowed_capacity;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t *user_cpus_ptr;\n\tcpumask_t cpus_mask;\n\tvoid *migration_pending;\n\tshort unsigned int migration_disabled;\n\tshort unsigned int migration_flags;\n\tlong unsigned int rcu_tasks_nvcsw;\n\tu8 rcu_tasks_holdout;\n\tu8 rcu_tasks_idx;\n\tint rcu_tasks_idle_cpu;\n\tstruct list_head rcu_tasks_holdout_list;\n\tint rcu_tasks_exit_cpu;\n\tstruct list_head rcu_tasks_exit_list;\n\tint trc_reader_nesting;\n\tstruct srcu_ctr *trc_reader_scp;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_task_hot: 1;\n\tlong: 28;\n\tunsigned int sched_remote_wakeup: 1;\n\tunsigned int sched_rt_mutex: 1;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int restore_sigmask: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tunsigned int use_memdelay: 1;\n\tunsigned int in_memstall: 1;\n\tunsigned int in_page_owner: 1;\n\tunsigned int in_eventfd: 1;\n\tunsigned int in_thrashing: 1;\n\tunsigned int in_nf_duplicate: 1;\n\tlong unsigned int atomic_flags;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tvoid *worker_private;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tstruct vtime vtime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tlong unsigned int last_switch_count;\n\tlong unsigned int last_switch_time;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct io_uring_task *io_uring;\n\tstruct io_restriction *io_uring_restrict;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct audit_context *audit_context;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n\tstruct seccomp seccomp;\n\tstruct syscall_user_dispatch syscall_dispatch;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tstruct mutex *blocked_on;\n\tlong unsigned int blocker;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tunsigned int psi_flags;\n\tu64 acct_rss_mem1;\n\tu64 acct_vm_mem1;\n\tu64 acct_timexpd;\n\tnodemask_t mems_allowed;\n\tseqcount_spinlock_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tu8 perf_recursion[4];\n\tstruct perf_event_context *perf_event_ctxp;\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct perf_ctx_data *perf_ctx_data;\n\tstruct mempolicy *mempolicy;\n\tshort int il_prev;\n\tu8 il_weight;\n\tshort int pref_node_fork;\n\tint numa_scan_seq;\n\tunsigned int numa_scan_period;\n\tunsigned int numa_scan_period_max;\n\tint numa_preferred_nid;\n\tlong unsigned int numa_migrate_retry;\n\tu64 node_stamp;\n\tu64 last_task_numa_placement;\n\tu64 last_sum_exec_runtime;\n\tstruct callback_head numa_work;\n\tstruct numa_group *numa_group;\n\tlong unsigned int *numa_faults;\n\tlong unsigned int total_numa_faults;\n\tlong unsigned int numa_faults_locality[3];\n\tlong unsigned int numa_pages_migrated;\n\tstruct rseq_data rseq;\n\tstruct sched_mm_cid mm_cid;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tstruct lazy_mmu_state lazy_mmu_state;\n\tstruct task_delay_info *delays;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tstruct kunit *kunit_test;\n\tint curr_ret_stack;\n\tint curr_ret_depth;\n\tlong unsigned int *ret_stack;\n\tlong long unsigned int ftrace_timestamp;\n\tlong long unsigned int ftrace_sleeptime;\n\tatomic_t trace_overrun;\n\tatomic_t tracing_graph_pause;\n\tlong unsigned int trace_recursion;\n\tunsigned int memcg_nr_pages_over_high;\n\tstruct mem_cgroup *active_memcg;\n\tstruct obj_cgroup *objcg;\n\tstruct gendisk *throttle_disk;\n\tstruct uprobe_task *utask;\n\tstruct kmap_ctrl kmap_ctrl;\n\tstruct callback_head rcu;\n\trefcount_t rcu_users;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct timer_list oom_reaper_timer;\n\trefcount_t stack_refcount;\n\tvoid *security;\n\tstruct bpf_local_storage *bpf_storage;\n\tstruct bpf_run_ctx *bpf_ctx;\n\tstruct bpf_net_context *bpf_net_context;\n\tstruct llist_head kretprobe_instances;\n\tstruct llist_head rethooks;\n\tlong: 64;\n\tstruct thread_struct thread;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct task_struct__safe_rcu {\n\tconst cpumask_t *cpus_ptr;\n\tstruct css_set *cgroups;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *group_leader;\n};\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\nstruct taskstats {\n\t__u16 version;\n\t__u32 ac_exitcode;\n\t__u8 ac_flag;\n\t__u8 ac_nice;\n\t__u64 cpu_count;\n\t__u64 cpu_delay_total;\n\t__u64 blkio_count;\n\t__u64 blkio_delay_total;\n\t__u64 swapin_count;\n\t__u64 swapin_delay_total;\n\t__u64 cpu_run_real_total;\n\t__u64 cpu_run_virtual_total;\n\tchar ac_comm[32];\n\t__u8 ac_sched;\n\t__u8 ac_pad[3];\n\tlong: 0;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u64 ac_etime;\n\t__u64 ac_utime;\n\t__u64 ac_stime;\n\t__u64 ac_minflt;\n\t__u64 ac_majflt;\n\t__u64 coremem;\n\t__u64 virtmem;\n\t__u64 hiwater_rss;\n\t__u64 hiwater_vm;\n\t__u64 read_char;\n\t__u64 write_char;\n\t__u64 read_syscalls;\n\t__u64 write_syscalls;\n\t__u64 read_bytes;\n\t__u64 write_bytes;\n\t__u64 cancelled_write_bytes;\n\t__u64 nvcsw;\n\t__u64 nivcsw;\n\t__u64 ac_utimescaled;\n\t__u64 ac_stimescaled;\n\t__u64 cpu_scaled_run_real_total;\n\t__u64 freepages_count;\n\t__u64 freepages_delay_total;\n\t__u64 thrashing_count;\n\t__u64 thrashing_delay_total;\n\t__u64 ac_btime64;\n\t__u64 compact_count;\n\t__u64 compact_delay_total;\n\t__u32 ac_tgid;\n\t__u64 ac_tgetime;\n\t__u64 ac_exe_dev;\n\t__u64 ac_exe_inode;\n\t__u64 wpcopy_count;\n\t__u64 wpcopy_delay_total;\n\t__u64 irq_count;\n\t__u64 irq_delay_total;\n\t__u64 cpu_delay_max;\n\t__u64 cpu_delay_min;\n\t__u64 blkio_delay_max;\n\t__u64 blkio_delay_min;\n\t__u64 swapin_delay_max;\n\t__u64 swapin_delay_min;\n\t__u64 freepages_delay_max;\n\t__u64 freepages_delay_min;\n\t__u64 thrashing_delay_max;\n\t__u64 thrashing_delay_min;\n\t__u64 compact_delay_max;\n\t__u64 compact_delay_min;\n\t__u64 wpcopy_delay_max;\n\t__u64 wpcopy_delay_min;\n\t__u64 irq_delay_max;\n\t__u64 irq_delay_min;\n\tstruct __kernel_timespec cpu_delay_max_ts;\n\tstruct __kernel_timespec blkio_delay_max_ts;\n\tstruct __kernel_timespec swapin_delay_max_ts;\n\tstruct __kernel_timespec freepages_delay_max_ts;\n\tstruct __kernel_timespec thrashing_delay_max_ts;\n\tstruct __kernel_timespec compact_delay_max_ts;\n\tstruct __kernel_timespec wpcopy_delay_max_ts;\n\tstruct __kernel_timespec irq_delay_max_ts;\n};\n\nstruct tc_act_pernet_id {\n\tstruct list_head list;\n\tunsigned int id;\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct tc_action_ops;\n\nstruct tcf_idrinfo;\n\nstruct tc_cookie;\n\nstruct tcf_chain;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tstruct tcf_t tcfa_tm;\n\tlong: 64;\n\tstruct gnet_stats_basic_sync tcfa_bstats;\n\tstruct gnet_stats_basic_sync tcfa_bstats_hw;\n\tatomic_t tcfa_drops;\n\tatomic_t tcfa_overlimits;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_sync *cpu_bstats;\n\tstruct gnet_stats_basic_sync *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *user_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n\tu32 in_hw_count;\n};\n\nstruct tc_action_net {\n\tstruct tcf_idrinfo *idrinfo;\n\tconst struct tc_action_ops *ops;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tcf_result;\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tunsigned int net_id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u64, u64, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n\tint (*offload_act_setup)(struct tc_action *, void *, u32 *, bool, struct netlink_ext_ack *);\n};\n\nstruct tc_bind_class_args {\n\tstruct qdisc_walker w;\n\tlong unsigned int new_cl;\n\tu32 portid;\n\tu32 clid;\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tc_fifo_qopt {\n\t__u32 limit;\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_sync *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nstruct tc_fifo_qopt_offload {\n\tenum tc_fifo_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t};\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct tc_pedit_key {\n\t__u32 mask;\n\t__u32 val;\n\t__u32 off;\n\t__u32 at;\n\t__u32 offmask;\n\t__u32 shift;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nstruct tc_query_caps_base {\n\tenum tc_setup_type type;\n\tvoid *caps;\n};\n\nstruct tc_root_qopt_offload {\n\tenum tc_root_command command;\n\tu32 handle;\n\tbool ingress;\n};\n\nstruct tc_skb_cb {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tu32 drop_reason;\n\tu16 zone;\n\tu16 mru;\n};\n\nstruct tcamsg {\n\tunsigned char tca_family;\n\tunsigned char tca__pad1;\n\tshort unsigned int tca__pad2;\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct tcf_bind_args {\n\tstruct tcf_walker w;\n\tlong unsigned int base;\n\tlong unsigned int cl;\n\tu32 classid;\n};\n\nstruct tcf_block {\n\tstruct xarray ports;\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t useswcnt;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\ntypedef void tcf_chain_head_change_t(struct tcf_proto *, void *);\n\nstruct tcf_block_ext_info {\n\tenum flow_block_binder_type binder_type;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n\tu32 block_index;\n};\n\nstruct tcf_block_owner_item {\n\tstruct list_head list;\n\tstruct Qdisc *q;\n\tenum flow_block_binder_type binder_type;\n};\n\nstruct tcf_proto_ops;\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_chain_info {\n\tstruct tcf_proto **pprev;\n\tstruct tcf_proto *next;\n};\n\nstruct tcf_dump_args {\n\tstruct tcf_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct tcf_block *block;\n\tstruct Qdisc *q;\n\tu32 parent;\n\tbool terse_dump;\n};\n\nstruct tcf_exts_miss_cookie_node;\n\nstruct tcf_exts {\n\t__u32 type;\n\tint nr_actions;\n\tstruct tc_action **actions;\n\tstruct net *net;\n\tnetns_tracker ns_tracker;\n\tstruct tcf_exts_miss_cookie_node *miss_cookie_node;\n\tint action;\n\tint police;\n};\n\nunion tcf_exts_miss_cookie {\n\tstruct {\n\t\tu32 miss_cookie_base;\n\t\tu32 act_index;\n\t};\n\tu64 miss_cookie;\n};\n\nstruct tcf_exts_miss_cookie_node {\n\tconst struct tcf_chain *chain;\n\tconst struct tcf_proto *tp;\n\tconst struct tcf_exts *exts;\n\tu32 chain_index;\n\tu32 tp_prio;\n\tu32 handle;\n\tu32 miss_cookie_base;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_filter_chain_list_item {\n\tstruct list_head list;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n};\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tcf_net {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n};\n\nstruct tcf_pedit_parms;\n\nstruct tcf_pedit {\n\tstruct tc_action common;\n\tstruct tcf_pedit_parms *parms;\n\tlong: 64;\n};\n\nstruct tcf_pedit_key_ex {\n\tenum pedit_header_type htype;\n\tenum pedit_cmd cmd;\n};\n\nstruct tcf_pedit_parms {\n\tstruct tc_pedit_key *tcfp_keys;\n\tstruct tcf_pedit_key_ex *tcfp_keys_ex;\n\tint action;\n\tu32 tcfp_off_max_hint;\n\tunsigned char tcfp_nkeys;\n\tunsigned char tcfp_flags;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\tbool counted;\n\tbool usesw;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, u32, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tvoid (*tmplt_reoffload)(struct tcf_chain *, bool, flow_setup_cb_t *, void *);\n\tstruct tcf_exts * (*get_exts)(const struct tcf_proto *, u32);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_qevent {\n\tstruct tcf_block *block;\n\tstruct tcf_block_ext_info info;\n\tstruct tcf_proto *filter_chain;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t};\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\nstruct tchars {\n\tchar t_intrc;\n\tchar t_quitc;\n\tchar t_startc;\n\tchar t_stopc;\n\tchar t_eofc;\n\tchar t_brkc;\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 accecn: 6;\n\tu8 saw_unknown: 1;\n\tu8 unused: 1;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\t__u8 __cacheline_group_begin__tcp_sock_read_tx[0];\n\tu32 max_window;\n\tu32 rcv_ssthresh;\n\tu32 reordering;\n\tu32 notsent_lowat;\n\tu16 gso_segs;\n\tstruct sk_buff *retransmit_skb_hint;\n\t__u8 __cacheline_group_end__tcp_sock_read_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_txrx[0];\n\tu32 tsoffset;\n\tu32 snd_wnd;\n\tu32 mss_cache;\n\tu32 snd_cwnd;\n\tu32 prr_out;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tu16 tcp_header_len;\n\tu8 scaling_ratio;\n\tu8 chrono_type: 2;\n\tu8 repair: 1;\n\tu8 tcp_usec_ts: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 recvmsg_inq: 1;\n\t__u8 __cacheline_group_end__tcp_sock_read_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_read_rx[0];\n\tu32 copied_seq;\n\tu32 snd_wl1;\n\tu32 tlp_high_seq;\n\tu32 rttvar_us;\n\tu32 retrans_out;\n\tu16 advmss;\n\tu16 urg_data;\n\tu32 lost;\n\tu32 snd_ssthresh;\n\tstruct minmax rtt_min;\n\tstruct rb_root out_of_order_queue;\n\t__u8 __cacheline_group_end__tcp_sock_read_rx[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\t__u8 __cacheline_group_begin__tcp_sock_write_tx[0];\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu32 snd_sml;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu32 write_seq;\n\tu32 pushed_seq;\n\tu32 lsndtime;\n\tu32 mdev_us;\n\tu32 rtt_seq;\n\tu64 tcp_wstamp_ns;\n\tu64 accecn_opt_tstamp;\n\tstruct list_head tsorted_sent_queue;\n\tstruct sk_buff *highest_sack;\n\tu8 ecn_flags;\n\t__u8 __cacheline_group_end__tcp_sock_write_tx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_txrx[0];\n\tu8 nonagle: 4;\n\tu8 rate_app_limited: 1;\n\tshort: 3;\n\tu8 received_ce_pending: 4;\n\tu8 accecn_opt_sent_w_dsack: 1;\n\tu8 unused2: 3;\n\tu8 accecn_minlen: 2;\n\tu8 est_ecnfield: 2;\n\tu8 accecn_opt_demand: 2;\n\tu8 prev_ecnfield: 2;\n\t__be32 pred_flags;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 rcv_nxt;\n\tu32 snd_nxt;\n\tu32 snd_una;\n\tu32 window_clamp;\n\tu32 srtt_us;\n\tu32 packets_out;\n\tu32 snd_up;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 received_ce;\n\tu32 received_ecn_bytes[3];\n\tu32 app_limited;\n\tu32 rcv_wnd;\n\tu32 rcv_tstamp;\n\tstruct tcp_options_received rx_opt;\n\t__u8 __cacheline_group_end__tcp_sock_write_txrx[0];\n\t__u8 __cacheline_group_begin__tcp_sock_write_rx[0];\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_wup;\n\tu32 max_packets_out;\n\tu32 cwnd_usage_seq;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_rtt_last_tsecr;\n\tu32 delivered_ecn_bytes[3];\n\tu16 pkts_acked_ewma;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu64 bytes_acked;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tint space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\t__u8 __cacheline_group_end__tcp_sock_write_rx[0];\n\tu32 dsack_dups;\n\tu32 compressed_ack_rcv_nxt;\n\tstruct list_head tsq_node;\n\tstruct tcp_rack rack;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 thin_lto: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 save_syn: 2;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 syn_fastopen_child: 1;\n\tu8 keepalive_probes;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n\tu32 tcp_tx_delay;\n\tu32 mdev_max_us;\n\tu32 reord_seen;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 last_oow_ack_time;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu32 mtu_info;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 rto_stamp;\n\tu16 total_rto;\n\tu16 total_rto_recoveries;\n\tu32 total_rto_time;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu8 bpf_chg_cc_inprogress: 1;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 plb_rehash;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tstruct saved_syn *saved_syn;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tcp6_sock {\n\tstruct tcp_sock tcp;\n\tstruct ipv6_pinfo inet6;\n};\n\nunion tcp_ao_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_ao_hdr {\n\tu8 kind;\n\tu8 length;\n\tu8 keyid;\n\tu8 rnext_keyid;\n};\n\nstruct tcp_ao_key {\n\tstruct hlist_node node;\n\tunion tcp_ao_addr addr;\n\tu8 key[80];\n\tunsigned int tcp_sigpool_id;\n\tunsigned int digest_size;\n\tint l3index;\n\tu8 prefixlen;\n\tu8 family;\n\tu8 keylen;\n\tu8 keyflags;\n\tu8 sndid;\n\tu8 rcvid;\n\tu8 maclen;\n\tstruct callback_head rcu;\n\tatomic64_t pkt_good;\n\tatomic64_t pkt_bad;\n\tu8 traffic_keys[0];\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n\t__u32 tcpi_rcv_wnd;\n\t__u32 tcpi_rehash;\n\t__u16 tcpi_total_rto;\n\t__u16 tcpi_total_rto_recoveries;\n\t__u32 tcpi_total_rto_time;\n\t__u32 tcpi_received_ce;\n\t__u32 tcpi_delivered_e1_bytes;\n\t__u32 tcpi_delivered_e0_bytes;\n\t__u32 tcpi_delivered_ce_bytes;\n\t__u32 tcpi_received_e1_bytes;\n\t__u32 tcpi_received_e0_bytes;\n\t__u32 tcpi_received_ce_bytes;\n\t__u32 tcpi_ecn_mode: 2;\n\t__u32 tcpi_accecn_opt_seen: 2;\n\t__u32 tcpi_accecn_fail_mode: 4;\n\t__u32 tcpi_options2: 24;\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_key {\n\tunion {\n\t\tstruct {\n\t\t\tstruct tcp_ao_key *ao_key;\n\t\t\tchar *traffic_key;\n\t\t\tu32 sne;\n\t\t\tu8 rcv_next;\n\t\t};\n\t\tstruct tcp_md5sig_key *md5_key;\n\t};\n\tenum {\n\t\tTCP_KEY_NONE = 0,\n\t\tTCP_KEY_MD5 = 1,\n\t\tTCP_KEY_AO = 2,\n\t} type;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tu8 flags;\n\tunion tcp_ao_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tstruct net *tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 num_accecn_fields: 7;\n\tu8 use_synack_ecn_bytes: 1;\n\tu8 hash_size;\n\tu8 bpf_opt_len;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tcp_plb_state {\n\tu8 consec_cong_rounds: 5;\n\tu8 unused: 3;\n\tu32 pause_until;\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nstruct tcp_request_sock_ops;\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tbool req_usec_ts;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 snt_tsval_first;\n\tu32 snt_tsval_last;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n\tu8 syn_tos;\n\tbool accecn_ok;\n\tu8 syn_ect_snt: 2;\n\tu8 syn_ect_rcv: 2;\n\tu8 accecn_fail_mode: 4;\n\tu8 saw_accecn_opt: 2;\n};\n\nunion tcp_seq_and_ts_off;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\t__u32 (*cookie_init_seq)(const struct sk_buff *, __u16 *);\n\tstruct dst_entry * (*route_req)(const struct sock *, struct sk_buff *, struct flowi *, struct request_sock *, u32);\n\tunion tcp_seq_and_ts_off (*init_seq_and_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type, struct sk_buff *);\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct tcp_sacktag_state {\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tu32 reord;\n\tu32 sack_delivered;\n\tu32 delivered_bytes;\n\tint flag;\n\tunsigned int mss_now;\n\tstruct rate_sample *rate;\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nunion tcp_seq_and_ts_off {\n\tstruct {\n\t\tu32 seq;\n\t\tu32 ts_off;\n\t};\n\tu64 hash64;\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u16 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 2;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 4;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 delivered_ce: 20;\n\t\t\t__u32 unused: 11;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t};\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(struct sock *, struct sk_buff *, bool);\n\tsize_t (*get_info_size)(const struct sock *, bool);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 ae: 1;\n\t__u16 res1: 3;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nstruct tcp_xa_pool {\n\tu8 max;\n\tu8 idx;\n\t__u32 tokens[17];\n\tnetmem_ref netmems[17];\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n\t__u64 copybuf_address;\n\t__s32 copybuf_len;\n\t__u32 flags;\n\t__u64 msg_control;\n\t__u64 msg_controllen;\n\t__u32 msg_flags;\n\t__u32 reserved;\n};\n\nstruct tcpa_event {\n\tu32 pcr_index;\n\tu32 event_type;\n\tu8 pcr_value[20];\n\tu32 event_size;\n\tu8 event_data[0];\n};\n\nstruct tcpa_pc_event {\n\tu32 event_id;\n\tu32 event_size;\n\tu8 event_data[0];\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct tcx_entry {\n\tstruct mini_Qdisc *miniq;\n\tstruct bpf_mprog_bundle bundle;\n\tu32 miniq_active;\n\tstruct callback_head rcu;\n};\n\nstruct tcx_link {\n\tstruct bpf_link link;\n\tstruct net_device *dev;\n};\n\nstruct td {\n\t__hc32 hwINFO;\n\t__hc32 hwCBP;\n\t__hc32 hwNextTD;\n\t__hc32 hwBE;\n\t__hc16 hwPSW[2];\n\t__u8 index;\n\tstruct ed *ed;\n\tstruct td *td_hash;\n\tstruct td *next_dl_td;\n\tstruct urb *urb;\n\tdma_addr_t td_dma;\n\tdma_addr_t data_dma;\n\tstruct list_head td_list;\n\tlong: 64;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[10];\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_cc[19];\n\tcc_t c_line;\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct tg3_rx_buffer_desc;\n\nstruct tg3_ext_rx_buffer_desc;\n\nstruct tg3_rx_prodring_set {\n\tu32 rx_std_prod_idx;\n\tu32 rx_std_cons_idx;\n\tu32 rx_jmb_prod_idx;\n\tu32 rx_jmb_cons_idx;\n\tstruct tg3_rx_buffer_desc *rx_std;\n\tstruct tg3_ext_rx_buffer_desc *rx_jmb;\n\tstruct ring_info *rx_std_buffers;\n\tstruct ring_info *rx_jmb_buffers;\n\tdma_addr_t rx_std_mapping;\n\tdma_addr_t rx_jmb_mapping;\n};\n\nstruct tg3;\n\nstruct tg3_hw_status;\n\nstruct tg3_tx_buffer_desc;\n\nstruct tg3_tx_ring_info;\n\nstruct tg3_napi {\n\tstruct napi_struct napi;\n\tstruct tg3 *tp;\n\tstruct tg3_hw_status *hw_status;\n\tu32 chk_msi_cnt;\n\tu32 last_tag;\n\tu32 last_irq_tag;\n\tu32 int_mbox;\n\tu32 coal_now;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 consmbox;\n\tu32 rx_rcb_ptr;\n\tu32 last_rx_cons;\n\tu16 *rx_rcb_prod_idx;\n\tstruct tg3_rx_prodring_set prodring;\n\tstruct tg3_rx_buffer_desc *rx_rcb;\n\tlong unsigned int rx_dropped;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 tx_prod;\n\tu32 tx_cons;\n\tu32 tx_pending;\n\tu32 last_tx_cons;\n\tu32 prodmbox;\n\tstruct tg3_tx_buffer_desc *tx_ring;\n\tstruct tg3_tx_ring_info *tx_buffers;\n\tlong unsigned int tx_dropped;\n\tdma_addr_t status_mapping;\n\tdma_addr_t rx_rcb_mapping;\n\tdma_addr_t tx_desc_mapping;\n\tchar irq_lbl[32];\n\tunsigned int irq_vec;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tg3_ethtool_stats {\n\tu64 rx_octets;\n\tu64 rx_fragments;\n\tu64 rx_ucast_packets;\n\tu64 rx_mcast_packets;\n\tu64 rx_bcast_packets;\n\tu64 rx_fcs_errors;\n\tu64 rx_align_errors;\n\tu64 rx_xon_pause_rcvd;\n\tu64 rx_xoff_pause_rcvd;\n\tu64 rx_mac_ctrl_rcvd;\n\tu64 rx_xoff_entered;\n\tu64 rx_frame_too_long_errors;\n\tu64 rx_jabbers;\n\tu64 rx_undersize_packets;\n\tu64 rx_in_length_errors;\n\tu64 rx_out_length_errors;\n\tu64 rx_64_or_less_octet_packets;\n\tu64 rx_65_to_127_octet_packets;\n\tu64 rx_128_to_255_octet_packets;\n\tu64 rx_256_to_511_octet_packets;\n\tu64 rx_512_to_1023_octet_packets;\n\tu64 rx_1024_to_1522_octet_packets;\n\tu64 rx_1523_to_2047_octet_packets;\n\tu64 rx_2048_to_4095_octet_packets;\n\tu64 rx_4096_to_8191_octet_packets;\n\tu64 rx_8192_to_9022_octet_packets;\n\tu64 tx_octets;\n\tu64 tx_collisions;\n\tu64 tx_xon_sent;\n\tu64 tx_xoff_sent;\n\tu64 tx_flow_control;\n\tu64 tx_mac_errors;\n\tu64 tx_single_collisions;\n\tu64 tx_mult_collisions;\n\tu64 tx_deferred;\n\tu64 tx_excessive_collisions;\n\tu64 tx_late_collisions;\n\tu64 tx_collide_2times;\n\tu64 tx_collide_3times;\n\tu64 tx_collide_4times;\n\tu64 tx_collide_5times;\n\tu64 tx_collide_6times;\n\tu64 tx_collide_7times;\n\tu64 tx_collide_8times;\n\tu64 tx_collide_9times;\n\tu64 tx_collide_10times;\n\tu64 tx_collide_11times;\n\tu64 tx_collide_12times;\n\tu64 tx_collide_13times;\n\tu64 tx_collide_14times;\n\tu64 tx_collide_15times;\n\tu64 tx_ucast_packets;\n\tu64 tx_mcast_packets;\n\tu64 tx_bcast_packets;\n\tu64 tx_carrier_sense_errors;\n\tu64 tx_discards;\n\tu64 tx_errors;\n\tu64 dma_writeq_full;\n\tu64 dma_write_prioq_full;\n\tu64 rxbds_empty;\n\tu64 rx_discards;\n\tu64 rx_errors;\n\tu64 rx_threshold_hit;\n\tu64 dma_readq_full;\n\tu64 dma_read_prioq_full;\n\tu64 tx_comp_queue_full;\n\tu64 ring_set_send_prod_index;\n\tu64 ring_status_update;\n\tu64 nic_irqs;\n\tu64 nic_avoided_irqs;\n\tu64 nic_tx_threshold_hit;\n\tu64 mbuf_lwm_thresh_hit;\n};\n\nstruct tg3_link_config {\n\tu32 advertising;\n\tu32 speed;\n\tu8 duplex;\n\tu8 autoneg;\n\tu8 flowctrl;\n\tu8 active_flowctrl;\n\tu8 active_duplex;\n\tu32 active_speed;\n\tu32 rmt_adv;\n};\n\nstruct tg3_bufmgr_config {\n\tu32 mbuf_read_dma_low_water;\n\tu32 mbuf_mac_rx_low_water;\n\tu32 mbuf_high_water;\n\tu32 mbuf_read_dma_low_water_jumbo;\n\tu32 mbuf_mac_rx_low_water_jumbo;\n\tu32 mbuf_high_water_jumbo;\n\tu32 dma_low_water;\n\tu32 dma_high_water;\n};\n\nstruct tg3_hw_stats;\n\nstruct tg3 {\n\tunsigned int irq_sync;\n\tspinlock_t lock;\n\tspinlock_t indirect_lock;\n\tu32 (*read32)(struct tg3 *, u32);\n\tvoid (*write32)(struct tg3 *, u32, u32);\n\tu32 (*read32_mbox)(struct tg3 *, u32);\n\tvoid (*write32_mbox)(struct tg3 *, u32, u32);\n\tvoid *regs;\n\tvoid *aperegs;\n\tstruct net_device *dev;\n\tstruct pci_dev *pdev;\n\tu32 coal_now;\n\tu32 msg_enable;\n\tstruct ptp_clock_info ptp_info;\n\tstruct ptp_clock *ptp_clock;\n\ts64 ptp_adjust;\n\tu8 ptp_txts_retrycnt;\n\tvoid (*write32_tx_mbox)(struct tg3 *, u32, u32);\n\tu32 dma_limit;\n\tu32 txq_req;\n\tu32 txq_cnt;\n\tu32 txq_max;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tg3_napi napi[5];\n\tvoid (*write32_rx_mbox)(struct tg3 *, u32, u32);\n\tu32 rx_copy_thresh;\n\tu32 rx_std_ring_mask;\n\tu32 rx_jmb_ring_mask;\n\tu32 rx_ret_ring_mask;\n\tu32 rx_pending;\n\tu32 rx_jumbo_pending;\n\tu32 rx_std_max_post;\n\tu32 rx_offset;\n\tu32 rx_pkt_map_sz;\n\tu32 rxq_req;\n\tu32 rxq_cnt;\n\tu32 rxq_max;\n\tbool rx_refill;\n\tstruct rtnl_link_stats64 net_stats_prev;\n\tstruct tg3_ethtool_stats estats_prev;\n\tlong unsigned int tg3_flags[2];\n\tunion {\n\t\tlong unsigned int phy_crc_errors;\n\t\tlong unsigned int last_event_jiffies;\n\t};\n\tstruct timer_list timer;\n\tu16 timer_counter;\n\tu16 timer_multiplier;\n\tu32 timer_offset;\n\tu16 asf_counter;\n\tu16 asf_multiplier;\n\tu32 serdes_counter;\n\tstruct tg3_link_config link_config;\n\tstruct tg3_bufmgr_config bufmgr_config;\n\tu32 rx_mode;\n\tu32 tx_mode;\n\tu32 mac_mode;\n\tu32 mi_mode;\n\tu32 misc_host_ctrl;\n\tu32 grc_mode;\n\tu32 grc_local_ctrl;\n\tu32 dma_rwctrl;\n\tu32 coalesce_mode;\n\tu32 pwrmgmt_thresh;\n\tu32 rxptpctl;\n\tu32 pci_chip_rev_id;\n\tu16 pci_cmd;\n\tu8 pci_cacheline_sz;\n\tu8 pci_lat_timer;\n\tint pci_fn;\n\tint msi_cap;\n\tint pcix_cap;\n\tint pcie_readrq;\n\tstruct mii_bus *mdio_bus;\n\tint old_link;\n\tu8 phy_addr;\n\tu8 phy_ape_lock;\n\tu32 phy_id;\n\tu32 phy_flags;\n\tu32 led_ctrl;\n\tu32 phy_otp;\n\tu32 setlpicnt;\n\tu8 rss_ind_tbl[128];\n\tchar board_part_number[24];\n\tchar fw_ver[32];\n\tu32 nic_sram_data_cfg;\n\tu32 pci_clock_ctrl;\n\tstruct pci_dev *pdev_peer;\n\tstruct tg3_hw_stats *hw_stats;\n\tdma_addr_t stats_mapping;\n\tstruct work_struct reset_task;\n\tstruct sk_buff *tx_tstamp_skb;\n\tu64 pre_tx_ts;\n\tint nvram_lock_cnt;\n\tu32 nvram_size;\n\tu32 nvram_pagesize;\n\tu32 nvram_jedecnum;\n\tunsigned int irq_max;\n\tunsigned int irq_cnt;\n\tstruct ethtool_coalesce coal;\n\tstruct ethtool_keee eee;\n\tconst char *fw_needed;\n\tconst struct firmware *fw;\n\tu32 fw_len;\n\tstruct device *hwmon_dev;\n\tbool link_up;\n\tbool pcierr_recovery;\n\tu32 ape_hb;\n\tlong unsigned int ape_hb_interval;\n\tlong unsigned int ape_hb_jiffies;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tg3_dev_id {\n\tu32 vendor;\n\tu32 device;\n\tu32 rev;\n};\n\nstruct tg3_dev_id___2 {\n\tu32 vendor;\n\tu32 device;\n};\n\nstruct tg3_rx_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 idx_len;\n\tu32 type_flags;\n\tu32 ip_tcp_csum;\n\tu32 err_vlan;\n\tu32 reserved;\n\tu32 opaque;\n};\n\nstruct tg3_ext_rx_buffer_desc {\n\tstruct {\n\t\tu32 addr_hi;\n\t\tu32 addr_lo;\n\t} addrlist[3];\n\tu32 len2_len1;\n\tu32 resv_len3;\n\tstruct tg3_rx_buffer_desc std;\n};\n\nstruct tg3_fiber_aneginfo {\n\tint state;\n\tu32 flags;\n\tlong unsigned int link_time;\n\tlong unsigned int cur_time;\n\tu32 ability_match_cfg;\n\tint ability_match_count;\n\tchar ability_match;\n\tchar idle_match;\n\tchar ack_match;\n\tu32 txconfig;\n\tu32 rxconfig;\n};\n\nstruct tg3_firmware_hdr {\n\t__be32 version;\n\t__be32 base_addr;\n\t__be32 len;\n};\n\nstruct tg3_hw_stats {\n\tu8 __reserved0[256];\n\ttg3_stat64_t rx_octets;\n\tu64 __reserved1;\n\ttg3_stat64_t rx_fragments;\n\ttg3_stat64_t rx_ucast_packets;\n\ttg3_stat64_t rx_mcast_packets;\n\ttg3_stat64_t rx_bcast_packets;\n\ttg3_stat64_t rx_fcs_errors;\n\ttg3_stat64_t rx_align_errors;\n\ttg3_stat64_t rx_xon_pause_rcvd;\n\ttg3_stat64_t rx_xoff_pause_rcvd;\n\ttg3_stat64_t rx_mac_ctrl_rcvd;\n\ttg3_stat64_t rx_xoff_entered;\n\ttg3_stat64_t rx_frame_too_long_errors;\n\ttg3_stat64_t rx_jabbers;\n\ttg3_stat64_t rx_undersize_packets;\n\ttg3_stat64_t rx_in_length_errors;\n\ttg3_stat64_t rx_out_length_errors;\n\ttg3_stat64_t rx_64_or_less_octet_packets;\n\ttg3_stat64_t rx_65_to_127_octet_packets;\n\ttg3_stat64_t rx_128_to_255_octet_packets;\n\ttg3_stat64_t rx_256_to_511_octet_packets;\n\ttg3_stat64_t rx_512_to_1023_octet_packets;\n\ttg3_stat64_t rx_1024_to_1522_octet_packets;\n\ttg3_stat64_t rx_1523_to_2047_octet_packets;\n\ttg3_stat64_t rx_2048_to_4095_octet_packets;\n\ttg3_stat64_t rx_4096_to_8191_octet_packets;\n\ttg3_stat64_t rx_8192_to_9022_octet_packets;\n\tu64 __unused0[37];\n\ttg3_stat64_t tx_octets;\n\tu64 __reserved2;\n\ttg3_stat64_t tx_collisions;\n\ttg3_stat64_t tx_xon_sent;\n\ttg3_stat64_t tx_xoff_sent;\n\ttg3_stat64_t tx_flow_control;\n\ttg3_stat64_t tx_mac_errors;\n\ttg3_stat64_t tx_single_collisions;\n\ttg3_stat64_t tx_mult_collisions;\n\ttg3_stat64_t tx_deferred;\n\tu64 __reserved3;\n\ttg3_stat64_t tx_excessive_collisions;\n\ttg3_stat64_t tx_late_collisions;\n\ttg3_stat64_t tx_collide_2times;\n\ttg3_stat64_t tx_collide_3times;\n\ttg3_stat64_t tx_collide_4times;\n\ttg3_stat64_t tx_collide_5times;\n\ttg3_stat64_t tx_collide_6times;\n\ttg3_stat64_t tx_collide_7times;\n\ttg3_stat64_t tx_collide_8times;\n\ttg3_stat64_t tx_collide_9times;\n\ttg3_stat64_t tx_collide_10times;\n\ttg3_stat64_t tx_collide_11times;\n\ttg3_stat64_t tx_collide_12times;\n\ttg3_stat64_t tx_collide_13times;\n\ttg3_stat64_t tx_collide_14times;\n\ttg3_stat64_t tx_collide_15times;\n\ttg3_stat64_t tx_ucast_packets;\n\ttg3_stat64_t tx_mcast_packets;\n\ttg3_stat64_t tx_bcast_packets;\n\ttg3_stat64_t tx_carrier_sense_errors;\n\ttg3_stat64_t tx_discards;\n\ttg3_stat64_t tx_errors;\n\tu64 __unused1[31];\n\ttg3_stat64_t COS_rx_packets[16];\n\ttg3_stat64_t COS_rx_filter_dropped;\n\ttg3_stat64_t dma_writeq_full;\n\ttg3_stat64_t dma_write_prioq_full;\n\ttg3_stat64_t rxbds_empty;\n\ttg3_stat64_t rx_discards;\n\ttg3_stat64_t rx_errors;\n\ttg3_stat64_t rx_threshold_hit;\n\tu64 __unused2[9];\n\ttg3_stat64_t COS_out_packets[16];\n\ttg3_stat64_t dma_readq_full;\n\ttg3_stat64_t dma_read_prioq_full;\n\ttg3_stat64_t tx_comp_queue_full;\n\ttg3_stat64_t ring_set_send_prod_index;\n\ttg3_stat64_t ring_status_update;\n\ttg3_stat64_t nic_irqs;\n\ttg3_stat64_t nic_avoided_irqs;\n\ttg3_stat64_t nic_tx_threshold_hit;\n\ttg3_stat64_t mbuf_lwm_thresh_hit;\n\tu8 __reserved4[312];\n};\n\nstruct tg3_hw_status {\n\tu32 status;\n\tu32 status_tag;\n\tu16 rx_jumbo_consumer;\n\tu16 rx_consumer;\n\tu16 rx_mini_consumer;\n\tu16 reserved;\n\tstruct {\n\t\tu16 rx_producer;\n\t\tu16 tx_consumer;\n\t} idx[16];\n};\n\nstruct tg3_internal_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 nic_mbuf;\n\tu16 len;\n\tu16 cqid_sqid;\n\tu32 flags;\n\tu32 __cookie1;\n\tu32 __cookie2;\n\tu32 __cookie3;\n};\n\nstruct tg3_ocir {\n\tu32 signature;\n\tu16 version_flags;\n\tu16 refresh_int;\n\tu32 refresh_tmr;\n\tu32 update_tmr;\n\tu32 dst_base_addr;\n\tu16 src_hdr_offset;\n\tu16 src_hdr_length;\n\tu16 src_data_offset;\n\tu16 src_data_length;\n\tu16 dst_hdr_offset;\n\tu16 dst_data_offset;\n\tu16 dst_reg_upd_offset;\n\tu16 dst_sem_offset;\n\tu32 reserved1[2];\n\tu32 port0_flags;\n\tu32 port1_flags;\n\tu32 port2_flags;\n\tu32 port3_flags;\n\tu32 reserved2;\n};\n\nstruct tg3_tx_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 len_flags;\n\tu32 vlan_tag;\n};\n\nstruct tg3_tx_ring_info {\n\tstruct sk_buff *skb;\n\tdma_addr_t mapping;\n\tbool fragmented;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct thermal_cooling_device_ops;\n\nstruct thermal_cooling_device {\n\tint id;\n\tconst char *type;\n\tlong unsigned int max_state;\n\tstruct device device;\n\tstruct device_node *np;\n\tvoid *devdata;\n\tvoid *stats;\n\tconst struct thermal_cooling_device_ops *ops;\n\tbool updated;\n\tstruct mutex lock;\n\tstruct list_head thermal_instances;\n\tstruct list_head node;\n};\n\nstruct thermal_cooling_device_ops {\n\tint (*get_max_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*get_cur_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*set_cur_state)(struct thermal_cooling_device *, long unsigned int);\n\tint (*get_requested_power)(struct thermal_cooling_device *, u32 *);\n\tint (*state2power)(struct thermal_cooling_device *, long unsigned int, u32 *);\n\tint (*power2state)(struct thermal_cooling_device *, u32, long unsigned int *);\n};\n\nstruct thermal_trip {\n\tint temperature;\n\tint hysteresis;\n\tenum thermal_trip_type type;\n\tu8 flags;\n\tvoid *priv;\n};\n\nstruct thermal_zone_device_ops {\n\tbool (*should_bind)(struct thermal_zone_device *, const struct thermal_trip *, struct thermal_cooling_device *, struct cooling_spec *);\n\tint (*get_temp)(struct thermal_zone_device *, int *);\n\tint (*set_trips)(struct thermal_zone_device *, int, int);\n\tint (*change_mode)(struct thermal_zone_device *, enum thermal_device_mode);\n\tint (*set_trip_temp)(struct thermal_zone_device *, const struct thermal_trip *, int);\n\tint (*get_crit_temp)(struct thermal_zone_device *, int *);\n\tint (*set_emul_temp)(struct thermal_zone_device *, int);\n\tint (*get_trend)(struct thermal_zone_device *, const struct thermal_trip *, enum thermal_trend *);\n\tvoid (*hot)(struct thermal_zone_device *);\n\tvoid (*critical)(struct thermal_zone_device *);\n};\n\nstruct thpsize {\n\tstruct kobject kobj;\n\tstruct list_head node;\n\tint order;\n};\n\nstruct thread_deferred_req {\n\tstruct cache_deferred_req handle;\n\tstruct completion completion;\n};\n\nstruct thread_groups {\n\tunsigned int property;\n\tunsigned int nr_groups;\n\tunsigned int threads_per_group;\n\tunsigned int thread_list[8];\n};\n\nstruct thread_groups_list {\n\tunsigned int nr_properties;\n\tstruct thread_groups property_tgs[2];\n};\n\nunion thread_union {\n\tstruct task_struct task;\n\tlong unsigned int stack[4096];\n};\n\nstruct tick_device {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct tick_sched {\n\tlong unsigned int flags;\n\tunsigned int stalled_jiffies;\n\tlong unsigned int last_tick_jiffies;\n\tstruct hrtimer sched_timer;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tktime_t idle_waketime;\n\tunsigned int got_idle_tick;\n\tseqcount_t idle_sleeptime_seq;\n\tktime_t idle_entrytime;\n\tlong unsigned int last_jiffies;\n\tu64 timer_expires_base;\n\tu64 timer_expires;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tatomic_t tick_dep_mask;\n\tlong unsigned int check_clocks;\n};\n\nstruct tick_work {\n\tint cpu;\n\tatomic_t state;\n\tstruct delayed_work work;\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tunion {\n\t\tktime_t offs_tai;\n\t\tktime_t offs_aux;\n\t};\n\tu32 coarse_nsec;\n\tenum timekeeper_ids id;\n\tstruct tk_read_base tkr_raw;\n\tu64 raw_sec;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tu8 clock_valid;\n\tunion {\n\t\tstruct timespec64 monotonic_to_boot;\n\t\tstruct timespec64 monotonic_to_aux;\n\t};\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tktime_t next_leap_ktime;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n\ts32 tai_offset;\n};\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool next_expiry_recalc;\n\tbool is_idle;\n\tbool timers_pending;\n\tlong unsigned int pending_map[9];\n\tstruct hlist_head vectors[576];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct timer_events {\n\tu64 local;\n\tu64 global;\n};\n\nstruct timer_hash_bucket {\n\tspinlock_t lock;\n\tstruct hlist_head head;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct timer_rand_state {\n\tlong unsigned int last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct timerlat_entry {\n\tstruct trace_entry ent;\n\tunsigned int seqnum;\n\tint context;\n\tu64 timer_latency;\n};\n\nstruct timers_private {\n\tstruct pid *pid;\n\tstruct task_struct *task;\n\tstruct pid_namespace *ns;\n};\n\nstruct timestamp_event_queue {\n\tstruct ptp_extts_event buf[128];\n\tint head;\n\tint tail;\n\tspinlock_t lock;\n\tstruct list_head qlist;\n\tlong unsigned int *mask;\n\tstruct dentry *debugfs_instance;\n\tstruct debugfs_u32_array dfs_bitmap;\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct tk_data {\n\tseqcount_raw_spinlock_t seq;\n\tstruct timekeeper timekeeper;\n\tstruct timekeeper shadow_timekeeper;\n\traw_spinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tk_fast {\n\tseqcount_latch_t seq;\n\tstruct tk_read_base base[2];\n};\n\nstruct tlbiel_pid {\n\tlong unsigned int pid;\n\tlong unsigned int ric;\n};\n\nstruct tlbiel_va {\n\tlong unsigned int pid;\n\tlong unsigned int va;\n\tlong unsigned int psize;\n\tlong unsigned int ric;\n};\n\nstruct tlbiel_va_range {\n\tlong unsigned int pid;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int page_size;\n\tlong unsigned int psize;\n\tbool also_pwc;\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_chacha20_poly1305 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[12];\n\tunsigned char key[32];\n\tunsigned char salt[0];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_ccm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_sm4_gcm {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t\tstruct tls12_crypto_info_chacha20_poly1305 chacha20_poly1305;\n\t\tstruct tls12_crypto_info_sm4_gcm sm4_gcm;\n\t\tstruct tls12_crypto_info_sm4_ccm sm4_ccm;\n\t};\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tu8 zerocopy_sendfile: 1;\n\tu8 rx_no_pad: 1;\n\tu16 tx_max_payload_len;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool splicing_pages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tstruct sock *sk;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\ntypedef void (*tls_done_func_t)(void *, int, key_serial_t);\n\nstruct tls_handshake_args {\n\tstruct socket *ta_sock;\n\ttls_done_func_t ta_done;\n\tvoid *ta_data;\n\tconst char *ta_peername;\n\tunsigned int ta_timeout_ms;\n\tkey_serial_t ta_keyring;\n\tkey_serial_t ta_my_cert;\n\tkey_serial_t ta_my_privkey;\n\tunsigned int ta_num_peerids;\n\tkey_serial_t ta_my_peerids[5];\n};\n\nstruct tls_handshake_req {\n\tvoid (*th_consumer_done)(void *, int, key_serial_t);\n\tvoid *th_consumer_data;\n\tint th_type;\n\tunsigned int th_timeout_ms;\n\tint th_auth_mode;\n\tconst char *th_peername;\n\tkey_serial_t th_keyring;\n\tkey_serial_t th_certificate;\n\tkey_serial_t th_privkey;\n\tunsigned int th_num_peerids;\n\tkey_serial_t th_peerid[5];\n};\n\nstruct tls_strparser {\n\tstruct sock *sk;\n\tu32 mark: 8;\n\tu32 stopped: 1;\n\tu32 copy_mode: 1;\n\tu32 mixed_decrypted: 1;\n\tbool msg_ready;\n\tstruct strp_msg stm;\n\tstruct sk_buff *anchor;\n\tstruct work_struct work;\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tu8 reader_present;\n\tu8 async_capable: 1;\n\tu8 zc_capable: 1;\n\tu8 reader_contended: 1;\n\tbool key_update_pending;\n\tstruct tls_strparser strp;\n\tatomic_t decrypt_pending;\n\tstruct sk_buff_head async_hold;\n\tstruct wait_queue_head wq;\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_rec;\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct tmigr_event {\n\tstruct timerqueue_node nextevt;\n\tunsigned int cpu;\n\tbool ignore;\n};\n\nstruct tmigr_group;\n\nstruct tmigr_cpu {\n\traw_spinlock_t lock;\n\tbool available;\n\tbool idle;\n\tbool remote;\n\tstruct tmigr_group *tmgroup;\n\tu8 groupmask;\n\tu64 wakeup;\n\tstruct tmigr_event cpuevt;\n};\n\nstruct tmigr_group {\n\traw_spinlock_t lock;\n\tstruct tmigr_group *parent;\n\tstruct tmigr_event groupevt;\n\tu64 next_expiry;\n\tstruct timerqueue_head events;\n\tatomic_t migr_state;\n\tunsigned int level;\n\tint numa_node;\n\tunsigned int num_children;\n\tu8 groupmask;\n\tstruct list_head list;\n};\n\nunion tmigr_state {\n\tu32 state;\n\tstruct {\n\t\tu8 active;\n\t\tu8 migrator;\n\t\tu16 seq;\n\t};\n};\n\nstruct tmigr_walk {\n\tu64 nextexp;\n\tu64 firstexp;\n\tstruct tmigr_event *evt;\n\tu8 childmask;\n\tbool remote;\n\tlong unsigned int basej;\n\tu64 now;\n\tbool check;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct tnl_ptk_info {\n\tlong unsigned int flags[1];\n\t__be16 proto;\n\t__be32 key;\n\t__be32 seq;\n\tint hdr_len;\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct touch_overlay_segment {\n\tstruct list_head list;\n\tu32 x_origin;\n\tu32 y_origin;\n\tu32 x_size;\n\tu32 y_size;\n\tu32 key;\n\tbool pressed;\n\tint slot;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nstruct tp_transition_snapshot {\n\tlong unsigned int rcu;\n\tlong unsigned int srcu_gp;\n\tbool ongoing;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct tpm1_get_random_out {\n\t__be32 rng_data_len;\n\tu8 rng_data[128];\n};\n\nstruct tpm2_auth {\n\tu32 handle;\n\tu32 session;\n\tu8 our_nonce[32];\n\tu8 tpm_nonce[32];\n\tunion {\n\t\tu8 salt[32];\n\t\tu8 scratch[32];\n\t};\n\tu8 session_key[32];\n\tu8 passphrase[32];\n\tint passphrase_len;\n\tstruct aes_enckey aes_key;\n\tu8 attrs;\n\t__be32 ordinal;\n\tu32 name_h[3];\n\tu8 name[198];\n};\n\nstruct tpm2_cap_handles {\n\tu8 more_data;\n\t__be32 capability;\n\t__be32 count;\n\t__be32 handles[0];\n} __attribute__((packed));\n\nstruct tpm2_context {\n\t__be64 sequence;\n\t__be32 saved_handle;\n\t__be32 hierarchy;\n\t__be16 blob_size;\n} __attribute__((packed));\n\nstruct tpm2_get_cap_out {\n\tu8 more_data;\n\t__be32 subcap_id;\n\t__be32 property_cnt;\n\t__be32 property_id;\n\t__be32 value;\n} __attribute__((packed));\n\nstruct tpm2_get_random_out {\n\t__be16 size;\n\tu8 buffer[128];\n};\n\nstruct tpm2_hash {\n\tunsigned int crypto_id;\n\tunsigned int tpm_id;\n};\n\nstruct tpm2_pcr_read_out {\n\t__be32 update_cnt;\n\t__be32 pcr_selects_cnt;\n\t__be16 hash_alg;\n\tu8 pcr_select_size;\n\tu8 pcr_select[3];\n\t__be32 digests_cnt;\n\t__be16 digest_size;\n\tu8 digest[0];\n} __attribute__((packed));\n\nstruct tpm2_pcr_selection {\n\t__be16 hash_alg;\n\tu8 size_of_select;\n\tu8 pcr_select[3];\n};\n\nstruct tpm_bank_info {\n\tu16 alg_id;\n\tu16 digest_size;\n\tu16 crypto_id;\n};\n\nstruct tpm_bios_log {\n\tvoid *bios_event_log;\n\tvoid *bios_event_log_end;\n};\n\nstruct tpm_buf {\n\tu32 flags;\n\tu32 length;\n\tu8 *data;\n\tu8 handles;\n};\n\nstruct tpm_chip_seqops {\n\tstruct tpm_chip *chip;\n\tconst struct seq_operations *seqops;\n};\n\nstruct tpm_space {\n\tu32 context_tbl[3];\n\tu8 *context_buf;\n\tu32 session_tbl[3];\n\tu8 *session_buf;\n\tu32 buf_size;\n};\n\nstruct tpm_class_ops;\n\nstruct tpm_chip {\n\tstruct device dev;\n\tstruct device devs;\n\tstruct cdev cdev;\n\tstruct cdev cdevs;\n\tstruct rw_semaphore ops_sem;\n\tconst struct tpm_class_ops *ops;\n\tstruct tpm_bios_log log;\n\tstruct tpm_chip_seqops bin_log_seqops;\n\tstruct tpm_chip_seqops ascii_log_seqops;\n\tunsigned int flags;\n\tint dev_num;\n\tlong unsigned int is_open;\n\tchar hwrng_name[64];\n\tstruct hwrng hwrng;\n\tstruct mutex tpm_mutex;\n\tlong unsigned int timeout_a;\n\tlong unsigned int timeout_b;\n\tlong unsigned int timeout_c;\n\tlong unsigned int timeout_d;\n\tbool timeout_adjusted;\n\tlong unsigned int duration[4];\n\tbool duration_adjusted;\n\tstruct dentry *bios_dir;\n\tconst struct attribute_group *groups[8];\n\tunsigned int groups_cnt;\n\tu32 nr_allocated_banks;\n\tstruct tpm_bank_info allocated_banks[8];\n\tstruct tpm_space work_space;\n\tu32 last_cc;\n\tu32 nr_commands;\n\tu32 *cc_attrs_tbl;\n\tint locality;\n};\n\nstruct tpm_class_ops {\n\tunsigned int flags;\n\tconst u8 req_complete_mask;\n\tconst u8 req_complete_val;\n\tbool (*req_canceled)(struct tpm_chip *, u8);\n\tint (*recv)(struct tpm_chip *, u8 *, size_t);\n\tint (*send)(struct tpm_chip *, u8 *, size_t, size_t);\n\tvoid (*cancel)(struct tpm_chip *);\n\tu8 (*status)(struct tpm_chip *);\n\tvoid (*update_timeouts)(struct tpm_chip *, long unsigned int *);\n\tvoid (*update_durations)(struct tpm_chip *, long unsigned int *);\n\tint (*go_idle)(struct tpm_chip *);\n\tint (*cmd_ready)(struct tpm_chip *);\n\tint (*request_locality)(struct tpm_chip *, int);\n\tint (*relinquish_locality)(struct tpm_chip *, int);\n\tvoid (*clk_enable)(struct tpm_chip *, bool);\n};\n\nstruct tpm_header {\n\t__be16 tag;\n\t__be32 length;\n\tunion {\n\t\t__be32 ordinal;\n\t\t__be32 return_code;\n\t};\n} __attribute__((packed));\n\nstruct tpm_pcr_attr {\n\tint alg_id;\n\tint pcr;\n\tstruct device_attribute attr;\n};\n\nstruct tpm_readpubek_out {\n\tu8 algorithm[4];\n\tu8 encscheme[2];\n\tu8 sigscheme[2];\n\t__be32 paramsize;\n\tu8 parameters[12];\n\t__be32 keysize;\n\tu8 modulus[256];\n\tu8 checksum[20];\n};\n\nstruct tpmrm_priv {\n\tstruct file_priv priv;\n\tstruct tpm_space space;\n};\n\nstruct trace_module_delta;\n\nstruct trace_pid_list;\n\nstruct tracer_flags;\n\nstruct trace_options;\n\nstruct trace_func_repeats;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tstruct array_buffer array_buffer;\n\tstruct array_buffer snapshot_buffer;\n\tbool allocated_snapshot;\n\tspinlock_t snapshot_trigger_lock;\n\tunsigned int snapshot;\n\tlong unsigned int max_latency;\n\tstruct dentry *d_max_latency;\n\tstruct work_struct fsnotify_work;\n\tstruct irq_work fsnotify_irqwork;\n\tunsigned int mapped;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_size;\n\tchar *range_name;\n\tlong int text_delta;\n\tstruct trace_module_delta *module_delta;\n\tvoid *scratch;\n\tint scratch_size;\n\tint buffer_disabled;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint sys_refcount_enter;\n\tint sys_refcount_exit;\n\tstruct trace_event_file *enter_syscall_files[472];\n\tstruct trace_event_file *exit_syscall_files[472];\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tstruct tracer_flags *current_trace_flags;\n\tu64 trace_flags;\n\tunsigned char trace_flags_index[64];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tconst char *system_names;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct eventfs_inode *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct list_head marker_list;\n\tstruct list_head tracers;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tcpumask_var_t pipe_cpumask;\n\tint ref;\n\tint trace_ref;\n\tstruct list_head mod_events;\n\tstruct ftrace_ops *ops;\n\tstruct trace_pid_list *function_pids;\n\tstruct trace_pid_list *function_no_pids;\n\tstruct fgraph_ops *gops;\n\tstruct list_head func_probes;\n\tstruct list_head mod_trace;\n\tstruct list_head mod_notrace;\n\tint function_enabled;\n\tint no_filter_buffering_ref;\n\tunsigned int syscall_buf_sz;\n\tstruct list_head hist_vars;\n\tstruct cond_snapshot *cond_snapshot;\n\tstruct trace_func_repeats *last_func_repeats;\n\tbool ring_buffer_expanded;\n};\n\nstruct trace_array_cpu {\n\tlocal_t disabled;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tint ftrace_ignore_pid;\n\tbool ignore_pid;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\ntypedef struct trace_buffer *class_ring_buffer_nest_t;\n\nstruct trace_buffer {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tatomic_t resizing;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)(void);\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n\tlong unsigned int range_addr_start;\n\tlong unsigned int range_addr_end;\n\tstruct ring_buffer_meta *meta;\n\tunsigned int subbuf_size;\n\tunsigned int subbuf_order;\n\tunsigned int max_data_size;\n};\n\nstruct trace_buffer_meta {\n\t__u32 meta_page_size;\n\t__u32 meta_struct_len;\n\t__u32 subbuf_size;\n\t__u32 nr_subbufs;\n\tstruct {\n\t\t__u64 lost_events;\n\t\t__u32 id;\n\t\t__u32 read;\n\t} reader;\n\t__u64 flags;\n\t__u64 entries;\n\t__u64 overrun;\n\t__u64 read;\n\t__u64 Reserved1;\n\t__u64 Reserved2;\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct trace_probe_event;\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_entry_arg *entry_arg;\n\tstruct probe_arg args[0];\n};\n\nstruct trace_eprobe {\n\tconst char *event_system;\n\tconst char *event_name;\n\tchar *filter_str;\n\tstruct trace_event_call *event;\n\tstruct dyn_event devent;\n\tstruct trace_probe tp;\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tunsigned int trace_ctx;\n\tstruct pt_regs *regs;\n};\n\nstruct trace_event_class;\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tconst char *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tunion {\n\t\tvoid *module;\n\t\tatomic_t refcnt;\n\t};\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct trace_event_fields;\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_event_data_offsets_alarm_class {};\n\nstruct trace_event_data_offsets_alarmtimer_suspend {};\n\nstruct trace_event_data_offsets_alloc_vmap_area {};\n\nstruct trace_event_data_offsets_arm_event {\n\tu32 pei_buf;\n\tconst void *pei_buf_ptr_;\n\tu32 ctx_buf;\n\tconst void *ctx_buf_ptr_;\n\tu32 oem_buf;\n\tconst void *oem_buf_ptr_;\n};\n\nstruct trace_event_data_offsets_ata_bmdma_status {};\n\nstruct trace_event_data_offsets_ata_eh_action_template {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy_qc {};\n\nstruct trace_event_data_offsets_ata_exec_command_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_begin_template {};\n\nstruct trace_event_data_offsets_ata_link_reset_end_template {};\n\nstruct trace_event_data_offsets_ata_port_eh_begin_template {};\n\nstruct trace_event_data_offsets_ata_qc_complete_template {};\n\nstruct trace_event_data_offsets_ata_qc_issue_template {};\n\nstruct trace_event_data_offsets_ata_sff_hsm_template {};\n\nstruct trace_event_data_offsets_ata_sff_template {};\n\nstruct trace_event_data_offsets_ata_tf_load {};\n\nstruct trace_event_data_offsets_ata_transfer_data_template {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_bl_ext_tree_prepare_commit {};\n\nstruct trace_event_data_offsets_blkdev_zone_mgmt {};\n\nstruct trace_event_data_offsets_block_bio {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_completion {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n\tconst void *cmd_ptr_;\n};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_zwplug {};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\nstruct trace_event_data_offsets_bpf_trace_printk {\n\tu32 bpf_string;\n\tconst void *bpf_string_ptr_;\n};\n\nstruct trace_event_data_offsets_bpf_trigger_tp {};\n\nstruct trace_event_data_offsets_bpf_xdp_link_attach_failed {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_add {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_external_learn_add {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_fdb_update {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_br_mdb_full {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_cache_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cap_capable {};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tconst void *dst_path_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cgroup_rstat {};\n\nstruct trace_event_data_offsets_cma_alloc_busy_retry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_finish {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_alloc_start {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_cma_release {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_compact_retry {};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_contention_begin {};\n\nstruct trace_event_data_offsets_contention_end {};\n\nstruct trace_event_data_offsets_context_tracking_user {};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_cpu_idle_miss {};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_csd_function {};\n\nstruct trace_event_data_offsets_csd_queue_cpu {};\n\nstruct trace_event_data_offsets_ctime {};\n\nstruct trace_event_data_offsets_ctime_ns_xchg {};\n\nstruct trace_event_data_offsets_dax_pmd_fault_class {};\n\nstruct trace_event_data_offsets_dax_pmd_load_hole_class {};\n\nstruct trace_event_data_offsets_dax_pte_fault_class {};\n\nstruct trace_event_data_offsets_dax_writeback_one {};\n\nstruct trace_event_data_offsets_dax_writeback_range_class {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_end {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_start {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 parent;\n\tconst void *parent_ptr_;\n\tu32 pm_ops;\n\tconst void *pm_ops_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_recover_aborted {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_health_reporter_state_update {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 reporter_name;\n\tconst void *reporter_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwerr {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_hwmsg {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_devlink_trap_report {\n\tu32 bus_name;\n\tconst void *bus_name_ptr_;\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 driver_name;\n\tconst void *driver_name_ptr_;\n\tu32 trap_name;\n\tconst void *trap_name_ptr_;\n\tu32 trap_group_name;\n\tconst void *trap_group_name_ptr_;\n};\n\nstruct trace_event_data_offsets_devres {\n\tu32 devname;\n\tconst void *devname_ptr_;\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_alloc_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_attach_dev {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_buf_fd {\n\tu32 exp_name;\n\tconst void *exp_name_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_fence_unsignaled {\n\tu32 driver;\n\tconst void *driver_ptr_;\n\tu32 timeline;\n\tconst void *timeline_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_free_sgt {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_map_sg_err {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 phys_addrs;\n\tconst void *phys_addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 dma_addrs;\n\tconst void *dma_addrs_ptr_;\n\tu32 lengths;\n\tconst void *lengths_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_sync_single {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_dma_unmap_sg {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 addrs;\n\tconst void *addrs_ptr_;\n};\n\nstruct trace_event_data_offsets_dql_stall_detected {};\n\nstruct trace_event_data_offsets_e1000e_trace_mac_register {};\n\nstruct trace_event_data_offsets_error_report_template {};\n\nstruct trace_event_data_offsets_exit_mmap {};\n\nstruct trace_event_data_offsets_ext4__bitmap_load {};\n\nstruct trace_event_data_offsets_ext4__es_extent {};\n\nstruct trace_event_data_offsets_ext4__es_shrink_enter {};\n\nstruct trace_event_data_offsets_ext4__fallocate_mode {};\n\nstruct trace_event_data_offsets_ext4__folio_op {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_enter {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_exit {};\n\nstruct trace_event_data_offsets_ext4__mb_new_pa {};\n\nstruct trace_event_data_offsets_ext4__mballoc {};\n\nstruct trace_event_data_offsets_ext4__trim {};\n\nstruct trace_event_data_offsets_ext4__truncate {};\n\nstruct trace_event_data_offsets_ext4__write_begin {};\n\nstruct trace_event_data_offsets_ext4__write_end {};\n\nstruct trace_event_data_offsets_ext4_alloc_da_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_inode {};\n\nstruct trace_event_data_offsets_ext4_begin_ordered_truncate {};\n\nstruct trace_event_data_offsets_ext4_collapse_range {};\n\nstruct trace_event_data_offsets_ext4_da_release_space {};\n\nstruct trace_event_data_offsets_ext4_da_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_update_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_end {};\n\nstruct trace_event_data_offsets_ext4_da_write_folios_start {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages_extent {};\n\nstruct trace_event_data_offsets_ext4_discard_blocks {};\n\nstruct trace_event_data_offsets_ext4_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_drop_inode {};\n\nstruct trace_event_data_offsets_ext4_error {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_enter {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_exit {};\n\nstruct trace_event_data_offsets_ext4_es_insert_delayed_extent {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_es_remove_extent {};\n\nstruct trace_event_data_offsets_ext4_es_shrink {};\n\nstruct trace_event_data_offsets_ext4_es_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_ext4_evict_inode {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_enter {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_fastpath {};\n\nstruct trace_event_data_offsets_ext4_ext_handle_unwritten_extents {};\n\nstruct trace_event_data_offsets_ext4_ext_load_extent {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space_done {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_idx {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_leaf {};\n\nstruct trace_event_data_offsets_ext4_ext_show_extent {};\n\nstruct trace_event_data_offsets_ext4_fallocate_exit {};\n\nstruct trace_event_data_offsets_ext4_fc_cleanup {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_start {};\n\nstruct trace_event_data_offsets_ext4_fc_commit_stop {};\n\nstruct trace_event_data_offsets_ext4_fc_replay {};\n\nstruct trace_event_data_offsets_ext4_fc_replay_scan {};\n\nstruct trace_event_data_offsets_ext4_fc_stats {};\n\nstruct trace_event_data_offsets_ext4_fc_track_dentry {};\n\nstruct trace_event_data_offsets_ext4_fc_track_inode {};\n\nstruct trace_event_data_offsets_ext4_fc_track_range {};\n\nstruct trace_event_data_offsets_ext4_forget {};\n\nstruct trace_event_data_offsets_ext4_free_blocks {};\n\nstruct trace_event_data_offsets_ext4_free_inode {};\n\nstruct trace_event_data_offsets_ext4_fsmap_class {};\n\nstruct trace_event_data_offsets_ext4_get_implied_cluster_alloc_exit {};\n\nstruct trace_event_data_offsets_ext4_getfsmap_class {};\n\nstruct trace_event_data_offsets_ext4_insert_range {};\n\nstruct trace_event_data_offsets_ext4_invalidate_folio_op {};\n\nstruct trace_event_data_offsets_ext4_journal_start_inode {};\n\nstruct trace_event_data_offsets_ext4_journal_start_reserved {};\n\nstruct trace_event_data_offsets_ext4_journal_start_sb {};\n\nstruct trace_event_data_offsets_ext4_lazy_itable_init {};\n\nstruct trace_event_data_offsets_ext4_load_inode {};\n\nstruct trace_event_data_offsets_ext4_mark_inode_dirty {};\n\nstruct trace_event_data_offsets_ext4_mb_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_mb_release_group_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_inode_pa {};\n\nstruct trace_event_data_offsets_ext4_mballoc_alloc {};\n\nstruct trace_event_data_offsets_ext4_mballoc_prealloc {};\n\nstruct trace_event_data_offsets_ext4_move_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_move_extent_exit {};\n\nstruct trace_event_data_offsets_ext4_nfs_commit_metadata {};\n\nstruct trace_event_data_offsets_ext4_other_inode_update_time {};\n\nstruct trace_event_data_offsets_ext4_prefetch_bitmaps {};\n\nstruct trace_event_data_offsets_ext4_read_block_bitmap_load {};\n\nstruct trace_event_data_offsets_ext4_remove_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_blocks {};\n\nstruct trace_event_data_offsets_ext4_request_inode {};\n\nstruct trace_event_data_offsets_ext4_shutdown {};\n\nstruct trace_event_data_offsets_ext4_sync_file_enter {};\n\nstruct trace_event_data_offsets_ext4_sync_file_exit {};\n\nstruct trace_event_data_offsets_ext4_sync_fs {};\n\nstruct trace_event_data_offsets_ext4_unlink_enter {};\n\nstruct trace_event_data_offsets_ext4_unlink_exit {};\n\nstruct trace_event_data_offsets_ext4_update_sb {};\n\nstruct trace_event_data_offsets_ext4_writepages {};\n\nstruct trace_event_data_offsets_ext4_writepages_result {};\n\nstruct trace_event_data_offsets_fdb_delete {\n\tu32 br_dev;\n\tconst void *br_dev_ptr_;\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_ff_layout_commit_error {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_fib6_table_lookup {};\n\nstruct trace_event_data_offsets_fib_table_lookup {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_fill_mg_cmtime {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_fl_getdevinfo {\n\tu32 mds_addr;\n\tconst void *mds_addr_ptr_;\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_flush_foreign {};\n\nstruct trace_event_data_offsets_free_vmap_area_noflush {};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_guest_halt_poll_ns {};\n\nstruct trace_event_data_offsets_handshake_alert_class {};\n\nstruct trace_event_data_offsets_handshake_complete {};\n\nstruct trace_event_data_offsets_handshake_error_class {};\n\nstruct trace_event_data_offsets_handshake_event_class {};\n\nstruct trace_event_data_offsets_handshake_fd_class {};\n\nstruct trace_event_data_offsets_hash_fault {};\n\nstruct trace_event_data_offsets_hcall_entry {};\n\nstruct trace_event_data_offsets_hcall_exit {};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_setup {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hugepage_set {};\n\nstruct trace_event_data_offsets_hugepage_update {};\n\nstruct trace_event_data_offsets_hugetlbfs__inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_alloc_inode {};\n\nstruct trace_event_data_offsets_hugetlbfs_fallocate {};\n\nstruct trace_event_data_offsets_hugetlbfs_setattr {\n\tu32 d_name;\n\tconst void *d_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_class {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_show_string {\n\tu32 attr_name;\n\tconst void *attr_name_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_read {};\n\nstruct trace_event_data_offsets_i2c_reply {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_i2c_result {};\n\nstruct trace_event_data_offsets_i2c_write {\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_icmp_send {};\n\nstruct trace_event_data_offsets_inet_sk_error_report {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n\tconst void *level_ptr_;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_inode_foreign_history {};\n\nstruct trace_event_data_offsets_inode_switch_wbs {};\n\nstruct trace_event_data_offsets_inode_switch_wbs_queue {};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_cqe_overflow {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_defer {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_fail_link {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_local_work_run {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_req_failed {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_short_write {};\n\nstruct trace_event_data_offsets_io_uring_submit_req {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_add {\n\tu32 op_str;\n\tconst void *op_str_ptr_;\n};\n\nstruct trace_event_data_offsets_io_uring_task_work_run {};\n\nstruct trace_event_data_offsets_iomap_add_to_ioend {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_dio_complete {};\n\nstruct trace_event_data_offsets_iomap_dio_rw_begin {};\n\nstruct trace_event_data_offsets_iomap_iter {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tconst void *device_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_ipi_send_cpu {};\n\nstruct trace_event_data_offsets_ipi_send_cpumask {\n\tu32 cpumask;\n\tconst void *cpumask_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint_stats {};\n\nstruct trace_event_data_offsets_jbd2_commit {};\n\nstruct trace_event_data_offsets_jbd2_end_commit {};\n\nstruct trace_event_data_offsets_jbd2_handle_extend {};\n\nstruct trace_event_data_offsets_jbd2_handle_start_class {};\n\nstruct trace_event_data_offsets_jbd2_handle_stats {};\n\nstruct trace_event_data_offsets_jbd2_journal_shrink {};\n\nstruct trace_event_data_offsets_jbd2_lock_buffer_stall {};\n\nstruct trace_event_data_offsets_jbd2_run_stats {};\n\nstruct trace_event_data_offsets_jbd2_shrink_checkpoint_list {};\n\nstruct trace_event_data_offsets_jbd2_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_jbd2_submit_inode_data {};\n\nstruct trace_event_data_offsets_jbd2_update_log_tail {};\n\nstruct trace_event_data_offsets_jbd2_write_superblock {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\nstruct trace_event_data_offsets_kfree {};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_kmalloc {};\n\nstruct trace_event_data_offsets_kmem_cache_alloc {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_kmem_cache_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_ksm_advisor {};\n\nstruct trace_event_data_offsets_ksm_enter_exit_template {};\n\nstruct trace_event_data_offsets_ksm_merge_one_page {};\n\nstruct trace_event_data_offsets_ksm_merge_with_ksm_page {};\n\nstruct trace_event_data_offsets_ksm_remove_ksm_page {};\n\nstruct trace_event_data_offsets_ksm_remove_rmap_item {};\n\nstruct trace_event_data_offsets_ksm_scan_template {};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_ma_op {};\n\nstruct trace_event_data_offsets_ma_read {};\n\nstruct trace_event_data_offsets_ma_write {};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_mark_victim {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_mc_event {\n\tu32 msg;\n\tconst void *msg_ptr_;\n\tu32 label;\n\tconst void *label_ptr_;\n\tu32 driver_detail;\n\tconst void *driver_detail_ptr_;\n};\n\nstruct trace_event_data_offsets_mdio_access {};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_memcg_flush_stats {};\n\nstruct trace_event_data_offsets_memcg_rstat_events {};\n\nstruct trace_event_data_offsets_memcg_rstat_stats {};\n\nstruct trace_event_data_offsets_migration_pmd {};\n\nstruct trace_event_data_offsets_migration_pte {};\n\nstruct trace_event_data_offsets_mm_calculate_totalreserve_pages {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page_isolate {};\n\nstruct trace_event_data_offsets_mm_collapse_huge_page_swapin {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_filemap_fault {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache_range {};\n\nstruct trace_event_data_offsets_mm_khugepaged_collapse_file {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_khugepaged_scan_file {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_khugepaged_scan_pmd {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\nstruct trace_event_data_offsets_mm_migrate_pages_start {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_lowmem_reserve {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 upper_name;\n\tconst void *upper_name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_setup_per_zone_wmarks {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_clear_hopeless {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_reclaim_fail {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\nstruct trace_event_data_offsets_mm_vmscan_reclaim_pages {};\n\nstruct trace_event_data_offsets_mm_vmscan_throttled {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_write_folio {};\n\nstruct trace_event_data_offsets_mmap_lock {};\n\nstruct trace_event_data_offsets_mmap_lock_acquire_returned {};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n\tconst void *dev_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 driver;\n\tconst void *driver_ptr_;\n};\n\nstruct trace_event_data_offsets_netlink_extack {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_cached_open {};\n\nstruct trace_event_data_offsets_nfs4_cb_error_class {};\n\nstruct trace_event_data_offsets_nfs4_cb_offload {};\n\nstruct trace_event_data_offsets_nfs4_cb_seqid_err {};\n\nstruct trace_event_data_offsets_nfs4_cb_sequence {};\n\nstruct trace_event_data_offsets_nfs4_clientid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_close {};\n\nstruct trace_event_data_offsets_nfs4_commit_event {};\n\nstruct trace_event_data_offsets_nfs4_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_delegreturn_exit {};\n\nstruct trace_event_data_offsets_nfs4_deviceid_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_deviceid_status {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_flexfiles_io_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_getattr_event {};\n\nstruct trace_event_data_offsets_nfs4_idmap_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_event {};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_callback_event {\n\tu32 dstaddr;\n\tconst void *dstaddr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_layoutget {};\n\nstruct trace_event_data_offsets_nfs4_lock_event {};\n\nstruct trace_event_data_offsets_nfs4_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_lookupp {};\n\nstruct trace_event_data_offsets_nfs4_match_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_open_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_read_event {};\n\nstruct trace_event_data_offsets_nfs4_rename {\n\tu32 oldname;\n\tconst void *oldname_ptr_;\n\tu32 newname;\n\tconst void *newname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_sequence_done {};\n\nstruct trace_event_data_offsets_nfs4_set_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_set_lock {};\n\nstruct trace_event_data_offsets_nfs4_setup_sequence {};\n\nstruct trace_event_data_offsets_nfs4_state_lock_reclaim {};\n\nstruct trace_event_data_offsets_nfs4_state_mgr {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_state_mgr_failed {\n\tu32 hostname;\n\tconst void *hostname_ptr_;\n\tu32 section;\n\tconst void *section_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_test_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_trunked_exchange_id {\n\tu32 main_addr;\n\tconst void *main_addr_ptr_;\n\tu32 trunk_addr;\n\tconst void *trunk_addr_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs4_write_event {};\n\nstruct trace_event_data_offsets_nfs4_xdr_bad_operation {};\n\nstruct trace_event_data_offsets_nfs4_xdr_event {};\n\nstruct trace_event_data_offsets_nfs_access_exit {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead {};\n\nstruct trace_event_data_offsets_nfs_aop_readahead_done {};\n\nstruct trace_event_data_offsets_nfs_atomic_open_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_atomic_open_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_commit_done {};\n\nstruct trace_event_data_offsets_nfs_create_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_create_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_direct_req_class {};\n\nstruct trace_event_data_offsets_nfs_directory_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_directory_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_fh_to_dentry {};\n\nstruct trace_event_data_offsets_nfs_folio_event {};\n\nstruct trace_event_data_offsets_nfs_folio_event_done {};\n\nstruct trace_event_data_offsets_nfs_initiate_commit {};\n\nstruct trace_event_data_offsets_nfs_initiate_read {};\n\nstruct trace_event_data_offsets_nfs_initiate_write {};\n\nstruct trace_event_data_offsets_nfs_inode_event {};\n\nstruct trace_event_data_offsets_nfs_inode_event_done {};\n\nstruct trace_event_data_offsets_nfs_inode_range_event {};\n\nstruct trace_event_data_offsets_nfs_kiocb_event {};\n\nstruct trace_event_data_offsets_nfs_link_enter {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_link_exit {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_local_open_fh {};\n\nstruct trace_event_data_offsets_nfs_lookup_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_lookup_event_done {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_assign {\n\tu32 option;\n\tconst void *option_ptr_;\n\tu32 value;\n\tconst void *value_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_option {\n\tu32 option;\n\tconst void *option_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_mount_path {\n\tu32 path;\n\tconst void *path_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_page_class {};\n\nstruct trace_event_data_offsets_nfs_page_error_class {};\n\nstruct trace_event_data_offsets_nfs_pgio_error {};\n\nstruct trace_event_data_offsets_nfs_readdir_event {};\n\nstruct trace_event_data_offsets_nfs_readpage_done {};\n\nstruct trace_event_data_offsets_nfs_readpage_short {};\n\nstruct trace_event_data_offsets_nfs_rename_event {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_rename_event_done {\n\tu32 old_name;\n\tconst void *old_name_ptr_;\n\tu32 new_name;\n\tconst void *new_name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_sillyrename_unlink {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_nfs_update_size_class {};\n\nstruct trace_event_data_offsets_nfs_writeback_done {};\n\nstruct trace_event_data_offsets_nfs_xdr_event {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_nlmclnt_lock_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_non_standard_event {\n\tu32 fru_text;\n\tconst void *fru_text_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_notifier_info {};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_opal_entry {};\n\nstruct trace_event_data_offsets_opal_exit {};\n\nstruct trace_event_data_offsets_page_cache_ra_op {};\n\nstruct trace_event_data_offsets_page_cache_ra_order {};\n\nstruct trace_event_data_offsets_page_cache_ra_unbounded {};\n\nstruct trace_event_data_offsets_page_pool_release {};\n\nstruct trace_event_data_offsets_page_pool_state_hold {};\n\nstruct trace_event_data_offsets_page_pool_state_release {};\n\nstruct trace_event_data_offsets_page_pool_update_nid {};\n\nstruct trace_event_data_offsets_pci_hp_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n\tu32 slot;\n\tconst void *slot_ptr_;\n};\n\nstruct trace_event_data_offsets_pcie_link_event {\n\tu32 port_name;\n\tconst void *port_name_ptr_;\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_pmap_register {};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_bl_pr_key_err_class {\n\tu32 device;\n\tconst void *device_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_ds_connect {\n\tu32 ds_ips;\n\tconst void *ds_ips_ptr_;\n};\n\nstruct trace_event_data_offsets_pnfs_layout_event {};\n\nstruct trace_event_data_offsets_pnfs_update_layout {};\n\nstruct trace_event_data_offsets_powernv_throttle {\n\tu32 reason;\n\tconst void *reason_ptr_;\n};\n\nstruct trace_event_data_offsets_ppc64_interrupt_class {};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_purge_vmap_area_lazy {};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_qdisc_enqueue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tconst void *dev_ptr_;\n\tu32 kind;\n\tconst void *kind_ptr_;\n};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kvfree_callback {};\n\nstruct trace_event_data_offsets_rcu_nocb_wake {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_segcb_stats {};\n\nstruct trace_event_data_offsets_rcu_sr_normal {};\n\nstruct trace_event_data_offsets_rcu_stall_warning {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_watching {};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_regcache_drop_region {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regcache_sync {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 status;\n\tconst void *status_ptr_;\n\tu32 type;\n\tconst void *type_ptr_;\n};\n\nstruct trace_event_data_offsets_register_class {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_async {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bool {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_bulk {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 buf;\n\tconst void *buf_ptr_;\n};\n\nstruct trace_event_data_offsets_regmap_reg {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_buf_alloc {};\n\nstruct trace_event_data_offsets_rpc_call_rpcerror {};\n\nstruct trace_event_data_offsets_rpc_clnt_class {};\n\nstruct trace_event_data_offsets_rpc_clnt_clone_err {};\n\nstruct trace_event_data_offsets_rpc_clnt_new {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_clnt_new_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 server;\n\tconst void *server_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_failure {};\n\nstruct trace_event_data_offsets_rpc_reply_event {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_request {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_socket_nospace {};\n\nstruct trace_event_data_offsets_rpc_stats_latency {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_queued {\n\tu32 q_name;\n\tconst void *q_name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_task_running {};\n\nstruct trace_event_data_offsets_rpc_task_status {};\n\nstruct trace_event_data_offsets_rpc_tls_class {\n\tu32 servername;\n\tconst void *servername_ptr_;\n\tu32 progname;\n\tconst void *progname_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_alignment {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_rpc_xdr_overflow {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_lifetime_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_getport {\n\tu32 servername;\n\tconst void *servername_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_register {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcb_setport {};\n\nstruct trace_event_data_offsets_rpcb_unregister {\n\tu32 netid;\n\tconst void *netid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_bad_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_context {\n\tu32 acceptor;\n\tconst void *acceptor_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_createauth {};\n\nstruct trace_event_data_offsets_rpcgss_ctx_class {\n\tu32 principal;\n\tconst void *principal_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_gssapi_event {};\n\nstruct trace_event_data_offsets_rpcgss_import_ctx {};\n\nstruct trace_event_data_offsets_rpcgss_need_reencode {};\n\nstruct trace_event_data_offsets_rpcgss_oid_to_mech {\n\tu32 oid;\n\tconst void *oid_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_svc_accept_upcall {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_authenticate {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_gssapi_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_bad {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_class {};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_low {};\n\nstruct trace_event_data_offsets_rpcgss_svc_unwrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_wrap_failed {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_unwrap_failed {};\n\nstruct trace_event_data_offsets_rpcgss_upcall_msg {\n\tu32 msg;\n\tconst void *msg_ptr_;\n};\n\nstruct trace_event_data_offsets_rpcgss_upcall_result {};\n\nstruct trace_event_data_offsets_rpcgss_update_slack {};\n\nstruct trace_event_data_offsets_rpm_internal {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_return_int {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rpm_status {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\nstruct trace_event_data_offsets_rtas_input {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 inputs;\n\tconst void *inputs_ptr_;\n};\n\nstruct trace_event_data_offsets_rtas_output {\n\tu32 name;\n\tconst void *name_ptr_;\n\tu32 other_outputs;\n\tconst void *other_outputs_ptr_;\n};\n\nstruct trace_event_data_offsets_rtas_parameter_block {};\n\nstruct trace_event_data_offsets_rtc_alarm_irq_enable {};\n\nstruct trace_event_data_offsets_rtc_irq_set_freq {};\n\nstruct trace_event_data_offsets_rtc_irq_set_state {};\n\nstruct trace_event_data_offsets_rtc_offset_class {};\n\nstruct trace_event_data_offsets_rtc_time_alarm_class {};\n\nstruct trace_event_data_offsets_rtc_timer_class {};\n\nstruct trace_event_data_offsets_sched_ext_bypass_lb {};\n\nstruct trace_event_data_offsets_sched_ext_dump {\n\tu32 line;\n\tconst void *line_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_ext_event {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_end {};\n\nstruct trace_event_data_offsets_sched_kthread_work_execute_start {};\n\nstruct trace_event_data_offsets_sched_kthread_work_queue_work {};\n\nstruct trace_event_data_offsets_sched_migrate_task {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_move_numa {};\n\nstruct trace_event_data_offsets_sched_numa_pair_template {};\n\nstruct trace_event_data_offsets_sched_pi_setprio {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_prepare_exec {\n\tu32 interp;\n\tconst void *interp_ptr_;\n\tu32 filename;\n\tconst void *filename_ptr_;\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n\tconst void *filename_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_exit {};\n\nstruct trace_event_data_offsets_sched_process_fork {\n\tu32 parent_comm;\n\tconst void *parent_comm_ptr_;\n\tu32 child_comm;\n\tconst void *child_comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_hang {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_process_wait {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_skip_cpuset_numa {};\n\nstruct trace_event_data_offsets_sched_skip_vma_numa {};\n\nstruct trace_event_data_offsets_sched_stat_runtime {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_stat_template {\n\tu32 comm;\n\tconst void *comm_ptr_;\n};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n\tconst void *cmnd_ptr_;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\nstruct trace_event_data_offsets_selinux_audited {\n\tu32 scontext;\n\tconst void *scontext_ptr_;\n\tu32 tcontext;\n\tconst void *tcontext_ptr_;\n\tu32 tclass;\n\tconst void *tclass_ptr_;\n};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_sk_data_ready {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_smbus_read {};\n\nstruct trace_event_data_offsets_smbus_reply {};\n\nstruct trace_event_data_offsets_smbus_result {};\n\nstruct trace_event_data_offsets_smbus_write {};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_sock_msg_length {};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_softirq {};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_svc_alloc_arg_err {};\n\nstruct trace_event_data_offsets_svc_authenticate {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_deferred_event {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_pool_thread_event {};\n\nstruct trace_event_data_offsets_svc_process {\n\tu32 service;\n\tconst void *service_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_replace_page_err {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_rqst_status {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_stats_latency {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 procedure;\n\tconst void *procedure_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_unregister {\n\tu32 program;\n\tconst void *program_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_svc_xdr_msg_class {};\n\nstruct trace_event_data_offsets_svc_xprt_accept {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_create_err {\n\tu32 program;\n\tconst void *program_ptr_;\n\tu32 protocol;\n\tconst void *protocol_ptr_;\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_dequeue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_enqueue {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svc_xprt_event {\n\tu32 server;\n\tconst void *server_ptr_;\n\tu32 client;\n\tconst void *client_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_accept_class {\n\tu32 service;\n\tconst void *service_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_class {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_lifetime_class {};\n\nstruct trace_event_data_offsets_svcsock_marker {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_recv_short {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_state {\n\tu32 addr;\n\tconst void *addr_ptr_;\n};\n\nstruct trace_event_data_offsets_swiotlb_bounced {\n\tu32 dev_name;\n\tconst void *dev_name_ptr_;\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_prctl_unknown {};\n\nstruct trace_event_data_offsets_task_rename {};\n\nstruct trace_event_data_offsets_tasklet {};\n\nstruct trace_event_data_offsets_tcp_ao_event {};\n\nstruct trace_event_data_offsets_tcp_cong_state_set {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_event_skb {};\n\nstruct trace_event_data_offsets_tcp_hash_event {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\nstruct trace_event_data_offsets_tcp_rcvbuf_grow {};\n\nstruct trace_event_data_offsets_tcp_retransmit_skb {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_send_reset {};\n\nstruct trace_event_data_offsets_tcp_sendmsg_locked {};\n\nstruct trace_event_data_offsets_test_pages_isolated {};\n\nstruct trace_event_data_offsets_tick_stop {};\n\nstruct trace_event_data_offsets_timer_base_idle {};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_tlbia {};\n\nstruct trace_event_data_offsets_tlbie {};\n\nstruct trace_event_data_offsets_tls_contenttype {};\n\nstruct trace_event_data_offsets_tmigr_connect_child_parent {};\n\nstruct trace_event_data_offsets_tmigr_connect_cpu_parent {};\n\nstruct trace_event_data_offsets_tmigr_cpugroup {};\n\nstruct trace_event_data_offsets_tmigr_group_and_cpu {};\n\nstruct trace_event_data_offsets_tmigr_group_set {};\n\nstruct trace_event_data_offsets_tmigr_handle_remote {};\n\nstruct trace_event_data_offsets_tmigr_idle {};\n\nstruct trace_event_data_offsets_tmigr_update_events {};\n\nstruct trace_event_data_offsets_track_foreign_dirty {};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_usb_core_log_usb_device {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_vas_paste_crb {};\n\nstruct trace_event_data_offsets_vas_rx_win_open {};\n\nstruct trace_event_data_offsets_vas_tx_win_open {};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_queue_work {\n\tu32 workqueue;\n\tconst void *workqueue_ptr_;\n};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_folio_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_xchk_block_error_class {};\n\nstruct trace_event_data_offsets_xchk_btree_error {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_btree_op_error {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_class {};\n\nstruct trace_event_data_offsets_xchk_dirpath_changed {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_dirpath_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_dirpath_outcome_class {};\n\nstruct trace_event_data_offsets_xchk_dirtree_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_dirtree_evaluate_class {};\n\nstruct trace_event_data_offsets_xchk_dirtree_live_update {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_fblock_error_class {};\n\nstruct trace_event_data_offsets_xchk_file_op_error {};\n\nstruct trace_event_data_offsets_xchk_fscounters_calc {};\n\nstruct trace_event_data_offsets_xchk_fscounters_within_range {};\n\nstruct trace_event_data_offsets_xchk_fsfreeze_class {};\n\nstruct trace_event_data_offsets_xchk_fsgate_class {};\n\nstruct trace_event_data_offsets_xchk_iallocbt_check_cluster {};\n\nstruct trace_event_data_offsets_xchk_ifork_btree_error {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_ifork_btree_op_error {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_incomplete {};\n\nstruct trace_event_data_offsets_xchk_ino_error_class {};\n\nstruct trace_event_data_offsets_xchk_inode_is_allocated {};\n\nstruct trace_event_data_offsets_xchk_iscan_class {};\n\nstruct trace_event_data_offsets_xchk_iscan_iget {};\n\nstruct trace_event_data_offsets_xchk_iscan_iget_batch {};\n\nstruct trace_event_data_offsets_xchk_iscan_ino_class {};\n\nstruct trace_event_data_offsets_xchk_iscan_retry_wait_class {};\n\nstruct trace_event_data_offsets_xchk_metapath_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_nlinks_check_zero {};\n\nstruct trace_event_data_offsets_xchk_nlinks_collect_dirent {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_nlinks_collect_metafile {};\n\nstruct trace_event_data_offsets_xchk_nlinks_collect_pptr {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_nlinks_diff_class {};\n\nstruct trace_event_data_offsets_xchk_nlinks_live_update {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_nlinks_update_incore {};\n\nstruct trace_event_data_offsets_xchk_op_error {};\n\nstruct trace_event_data_offsets_xchk_pptr_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_refcount_incorrect {};\n\nstruct trace_event_data_offsets_xchk_sbtree_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xchk_vector_class {};\n\nstruct trace_event_data_offsets_xchk_vector_head_class {};\n\nstruct trace_event_data_offsets_xchk_xref_error {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_data_offsets_xfarray_create {};\n\nstruct trace_event_data_offsets_xfarray_foliosort {};\n\nstruct trace_event_data_offsets_xfarray_isort {};\n\nstruct trace_event_data_offsets_xfarray_qsort {};\n\nstruct trace_event_data_offsets_xfarray_sort {};\n\nstruct trace_event_data_offsets_xfarray_sort_scan {};\n\nstruct trace_event_data_offsets_xfarray_sort_stats {};\n\nstruct trace_event_data_offsets_xfbtree_buf_class {};\n\nstruct trace_event_data_offsets_xfbtree_freesp_class {\n\tu32 btname;\n\tconst void *btname_ptr_;\n};\n\nstruct trace_event_data_offsets_xfbtree_init {};\n\nstruct trace_event_data_offsets_xfile_class {};\n\nstruct trace_event_data_offsets_xfile_create {};\n\nstruct trace_event_data_offsets_xfile_destroy {};\n\nstruct trace_event_data_offsets_xfs_ag_class {};\n\nstruct trace_event_data_offsets_xfs_ag_inode_class {};\n\nstruct trace_event_data_offsets_xfs_ag_resv_class {};\n\nstruct trace_event_data_offsets_xfs_ag_resv_init_error {};\n\nstruct trace_event_data_offsets_xfs_agf_class {};\n\nstruct trace_event_data_offsets_xfs_ail_class {};\n\nstruct trace_event_data_offsets_xfs_alloc_class {};\n\nstruct trace_event_data_offsets_xfs_alloc_cur_check {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_attr_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_attr_list_class {};\n\nstruct trace_event_data_offsets_xfs_attr_list_node_descend {};\n\nstruct trace_event_data_offsets_xfs_bmap_class {};\n\nstruct trace_event_data_offsets_xfs_bmap_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_btree_alloc_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_bload_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_bload_level_geometry {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_commit_afakeroot {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_commit_ifakeroot {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_cur_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_btree_error_class {};\n\nstruct trace_event_data_offsets_xfs_btree_free_block {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_buf_class {};\n\nstruct trace_event_data_offsets_xfs_buf_flags_class {};\n\nstruct trace_event_data_offsets_xfs_buf_ioerror {};\n\nstruct trace_event_data_offsets_xfs_buf_item_class {};\n\nstruct trace_event_data_offsets_xfs_bunmap {};\n\nstruct trace_event_data_offsets_xfs_calc_atomic_write_unit_max {};\n\nstruct trace_event_data_offsets_xfs_calc_max_atomic_write_fsblocks {};\n\nstruct trace_event_data_offsets_xfs_calc_max_atomic_write_log_geometry {};\n\nstruct trace_event_data_offsets_xfs_check_new_dalign {};\n\nstruct trace_event_data_offsets_xfs_da_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_das_state_class {};\n\nstruct trace_event_data_offsets_xfs_defer_class {};\n\nstruct trace_event_data_offsets_xfs_defer_error_class {};\n\nstruct trace_event_data_offsets_xfs_defer_pending_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_defer_pending_item_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_dir2_leafn_moveents {};\n\nstruct trace_event_data_offsets_xfs_dir2_space_class {};\n\nstruct trace_event_data_offsets_xfs_discard_class {};\n\nstruct trace_event_data_offsets_xfs_double_io_class {};\n\nstruct trace_event_data_offsets_xfs_dqtrx_class {};\n\nstruct trace_event_data_offsets_xfs_dquot_class {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_delta_nextents {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_delta_nextents_step {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_estimate_class {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_intent_class {};\n\nstruct trace_event_data_offsets_xfs_exchmaps_overhead {};\n\nstruct trace_event_data_offsets_xfs_exchrange_class {};\n\nstruct trace_event_data_offsets_xfs_exchrange_freshness {};\n\nstruct trace_event_data_offsets_xfs_exchrange_inode_class {};\n\nstruct trace_event_data_offsets_xfs_extent_busy_class {};\n\nstruct trace_event_data_offsets_xfs_extent_busy_trim {};\n\nstruct trace_event_data_offsets_xfs_fault_class {};\n\nstruct trace_event_data_offsets_xfs_file_class {};\n\nstruct trace_event_data_offsets_xfs_filestream_class {};\n\nstruct trace_event_data_offsets_xfs_filestream_pick {};\n\nstruct trace_event_data_offsets_xfs_force_shutdown {\n\tu32 fname;\n\tconst void *fname_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_free_extent {};\n\nstruct trace_event_data_offsets_xfs_free_extent_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_freeblocks_resv_class {};\n\nstruct trace_event_data_offsets_xfs_fs_class {};\n\nstruct trace_event_data_offsets_xfs_fs_corrupt_class {};\n\nstruct trace_event_data_offsets_xfs_fsmap_group_key_class {};\n\nstruct trace_event_data_offsets_xfs_fsmap_linear_key_class {};\n\nstruct trace_event_data_offsets_xfs_fsmap_mapping {};\n\nstruct trace_event_data_offsets_xfs_getfsmap_class {};\n\nstruct trace_event_data_offsets_xfs_getparents_class {};\n\nstruct trace_event_data_offsets_xfs_getparents_rec_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_group_class {};\n\nstruct trace_event_data_offsets_xfs_group_corrupt_class {};\n\nstruct trace_event_data_offsets_xfs_group_intents_class {};\n\nstruct trace_event_data_offsets_xfs_healthmon_class {};\n\nstruct trace_event_data_offsets_xfs_healthmon_copybuf {};\n\nstruct trace_event_data_offsets_xfs_healthmon_create {};\n\nstruct trace_event_data_offsets_xfs_healthmon_event_class {};\n\nstruct trace_event_data_offsets_xfs_healthmon_lost_event {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_file_ioerror {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_fs {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_group {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_inode {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_media {};\n\nstruct trace_event_data_offsets_xfs_healthmon_report_shutdown {};\n\nstruct trace_event_data_offsets_xfs_icwalk_class {};\n\nstruct trace_event_data_offsets_xfs_imap_class {};\n\nstruct trace_event_data_offsets_xfs_inode_class {};\n\nstruct trace_event_data_offsets_xfs_inode_corrupt_class {};\n\nstruct trace_event_data_offsets_xfs_inode_error_class {};\n\nstruct trace_event_data_offsets_xfs_inode_irec_class {};\n\nstruct trace_event_data_offsets_xfs_inode_reload_unlinked_bucket {};\n\nstruct trace_event_data_offsets_xfs_inodegc_shrinker_scan {};\n\nstruct trace_event_data_offsets_xfs_inodegc_worker {};\n\nstruct trace_event_data_offsets_xfs_iomap_atomic_write_cow {};\n\nstruct trace_event_data_offsets_xfs_iomap_invalid_class {};\n\nstruct trace_event_data_offsets_xfs_iomap_prealloc_size {};\n\nstruct trace_event_data_offsets_xfs_irec_merge_post {};\n\nstruct trace_event_data_offsets_xfs_irec_merge_pre {};\n\nstruct trace_event_data_offsets_xfs_iref_class {};\n\nstruct trace_event_data_offsets_xfs_itrunc_class {};\n\nstruct trace_event_data_offsets_xfs_iunlink_reload_next {};\n\nstruct trace_event_data_offsets_xfs_iunlink_update_bucket {};\n\nstruct trace_event_data_offsets_xfs_iunlink_update_dinode {};\n\nstruct trace_event_data_offsets_xfs_iwalk_ag_rec {};\n\nstruct trace_event_data_offsets_xfs_lock_class {};\n\nstruct trace_event_data_offsets_xfs_log_assign_tail_lsn {};\n\nstruct trace_event_data_offsets_xfs_log_force {};\n\nstruct trace_event_data_offsets_xfs_log_get_max_trans_res {};\n\nstruct trace_event_data_offsets_xfs_log_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover {};\n\nstruct trace_event_data_offsets_xfs_log_recover_buf_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_icreate_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_ino_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_item_class {};\n\nstruct trace_event_data_offsets_xfs_log_recover_record {};\n\nstruct trace_event_data_offsets_xfs_loggrant_class {};\n\nstruct trace_event_data_offsets_xfs_metadir_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_metadir_update_class {\n\tu32 fname;\n\tconst void *fname_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_metadir_update_error_class {\n\tu32 fname;\n\tconst void *fname_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_metafile_resv_class {};\n\nstruct trace_event_data_offsets_xfs_namespace_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_perag_class {};\n\nstruct trace_event_data_offsets_xfs_pwork_init {};\n\nstruct trace_event_data_offsets_xfs_refcount_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_double_extent_at_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_double_extent_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_extent_at_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_extent_class {};\n\nstruct trace_event_data_offsets_xfs_refcount_lookup {};\n\nstruct trace_event_data_offsets_xfs_refcount_triple_extent_class {};\n\nstruct trace_event_data_offsets_xfs_reflink_remap_blocks {};\n\nstruct trace_event_data_offsets_xfs_rename {\n\tu32 src_name;\n\tconst void *src_name_ptr_;\n\tu32 target_name;\n\tconst void *target_name_ptr_;\n};\n\nstruct trace_event_data_offsets_xfs_rmap_class {};\n\nstruct trace_event_data_offsets_xfs_rmap_convert_state {};\n\nstruct trace_event_data_offsets_xfs_rmap_deferred_class {};\n\nstruct trace_event_data_offsets_xfs_rmapbt_class {};\n\nstruct trace_event_data_offsets_xfs_rtdiscard_class {};\n\nstruct trace_event_data_offsets_xfs_simple_io_class {};\n\nstruct trace_event_data_offsets_xfs_swap_extent_class {};\n\nstruct trace_event_data_offsets_xfs_timestamp_range_class {};\n\nstruct trace_event_data_offsets_xfs_trans_class {};\n\nstruct trace_event_data_offsets_xfs_trans_mod_dquot {};\n\nstruct trace_event_data_offsets_xfs_trans_resv_class {};\n\nstruct trace_event_data_offsets_xfs_verify_media {};\n\nstruct trace_event_data_offsets_xfs_verify_media_end {};\n\nstruct trace_event_data_offsets_xfs_verify_media_error {};\n\nstruct trace_event_data_offsets_xfs_wb_invalid_class {};\n\nstruct trace_event_data_offsets_xlog_iclog_class {};\n\nstruct trace_event_data_offsets_xlog_intent_recovery_failed {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xmbuf_create {};\n\nstruct trace_event_data_offsets_xmbuf_free {};\n\nstruct trace_event_data_offsets_xprt_cong_event {};\n\nstruct trace_event_data_offsets_xprt_ping {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_reserve {};\n\nstruct trace_event_data_offsets_xprt_retransmit {\n\tu32 progname;\n\tconst void *progname_ptr_;\n\tu32 procname;\n\tconst void *procname_ptr_;\n};\n\nstruct trace_event_data_offsets_xprt_transmit {};\n\nstruct trace_event_data_offsets_xprt_writelock_event {};\n\nstruct trace_event_data_offsets_xreap_bmapi_binval_scan {};\n\nstruct trace_event_data_offsets_xreap_ifork_extent {};\n\nstruct trace_event_data_offsets_xrep_abt_found {};\n\nstruct trace_event_data_offsets_xrep_adoption_class {};\n\nstruct trace_event_data_offsets_xrep_bmap_found {};\n\nstruct trace_event_data_offsets_xrep_calc_ag_resblks {};\n\nstruct trace_event_data_offsets_xrep_calc_ag_resblks_btsize {};\n\nstruct trace_event_data_offsets_xrep_cow_free_staging {};\n\nstruct trace_event_data_offsets_xrep_cow_mark_file_range {};\n\nstruct trace_event_data_offsets_xrep_cow_replace_mapping {};\n\nstruct trace_event_data_offsets_xrep_dentry_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xrep_dinode_class {};\n\nstruct trace_event_data_offsets_xrep_dinode_count_rmaps {};\n\nstruct trace_event_data_offsets_xrep_dinode_findmode_dirent {};\n\nstruct trace_event_data_offsets_xrep_dinode_findmode_dirent_inval {};\n\nstruct trace_event_data_offsets_xrep_dir_class {};\n\nstruct trace_event_data_offsets_xrep_dir_recover_dirblock {};\n\nstruct trace_event_data_offsets_xrep_dirent_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xrep_extent_class {};\n\nstruct trace_event_data_offsets_xrep_findroot_block {};\n\nstruct trace_event_data_offsets_xrep_ibt_found {};\n\nstruct trace_event_data_offsets_xrep_ibt_walk_rmap {};\n\nstruct trace_event_data_offsets_xrep_inode_class {};\n\nstruct trace_event_data_offsets_xrep_iunlink_add_to_bucket {};\n\nstruct trace_event_data_offsets_xrep_iunlink_commit_bucket {};\n\nstruct trace_event_data_offsets_xrep_iunlink_relink_next {};\n\nstruct trace_event_data_offsets_xrep_iunlink_relink_prev {};\n\nstruct trace_event_data_offsets_xrep_iunlink_reload_next {};\n\nstruct trace_event_data_offsets_xrep_iunlink_reload_ondisk {};\n\nstruct trace_event_data_offsets_xrep_iunlink_resolve_class {};\n\nstruct trace_event_data_offsets_xrep_iunlink_visit {};\n\nstruct trace_event_data_offsets_xrep_iunlink_walk_ondisk_bucket {};\n\nstruct trace_event_data_offsets_xrep_newbt_extent_class {};\n\nstruct trace_event_data_offsets_xrep_nlinks_set_record {};\n\nstruct trace_event_data_offsets_xrep_parent_salvage_class {};\n\nstruct trace_event_data_offsets_xrep_pptr_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xrep_pptr_salvage_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xrep_pptr_scan_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xrep_reap_find_class {};\n\nstruct trace_event_data_offsets_xrep_reap_limits_class {};\n\nstruct trace_event_data_offsets_xrep_refc_found {};\n\nstruct trace_event_data_offsets_xrep_reset_counters {};\n\nstruct trace_event_data_offsets_xrep_rmap_found {};\n\nstruct trace_event_data_offsets_xrep_rmap_live_update {};\n\nstruct trace_event_data_offsets_xrep_symlink_class {};\n\nstruct trace_event_data_offsets_xrep_symlink_salvage_target {\n\tu32 target;\n\tconst void *target_ptr_;\n};\n\nstruct trace_event_data_offsets_xrep_tempfile_class {};\n\nstruct trace_event_data_offsets_xrep_tempfile_create {};\n\nstruct trace_event_data_offsets_xrep_xattr_class {};\n\nstruct trace_event_data_offsets_xrep_xattr_pptr_scan_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xrep_xattr_recover_leafblock {};\n\nstruct trace_event_data_offsets_xrep_xattr_salvage_class {\n\tu32 name;\n\tconst void *name_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_data_ready {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_socket_event {};\n\nstruct trace_event_data_offsets_xs_socket_event_done {};\n\nstruct trace_event_data_offsets_xs_stream_read_data {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_data_offsets_xs_stream_read_request {\n\tu32 addr;\n\tconst void *addr_ptr_;\n\tu32 port;\n\tconst void *port_ptr_;\n};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst unsigned int is_signed: 1;\n\t\t\tunsigned int needs_test: 1;\n\t\t\tconst int filter_type;\n\t\t\tconst int len;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct eventfs_inode *ei;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\trefcount_t ref;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarmtimer_suspend {\n\tstruct trace_entry ent;\n\ts64 expires;\n\tunsigned char alarm_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alloc_vmap_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int size;\n\tlong unsigned int align;\n\tlong unsigned int vstart;\n\tlong unsigned int vend;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_arm_event {\n\tstruct trace_entry ent;\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n\tu8 affinity;\n\tu32 pei_len;\n\tu32 __data_loc_pei_buf;\n\tu32 ctx_len;\n\tu32 __data_loc_ctx_buf;\n\tu32 oem_len;\n\tu32 __data_loc_oem_buf;\n\tu8 sev;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_bmdma_status {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char host_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_action_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy_qc {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_exec_command_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char feature;\n\tunsigned char hob_nsect;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tlong unsigned int deadline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_link_reset_end_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int class[2];\n\tint rc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_port_eh_begin_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_complete_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char status;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char error;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_issue_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tunsigned char proto;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_hsm_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int protocol;\n\tunsigned int hsm_state;\n\tunsigned char dev_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_sff_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char hsm_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_tf_load {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char proto;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_transfer_data_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int flags;\n\tunsigned int offset;\n\tunsigned int bytes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int wb_setpoint;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bl_ext_tree_prepare_commit {\n\tstruct trace_entry ent;\n\tint ret;\n\tsize_t count;\n\tu64 lwb;\n\tbool not_all_ranges;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_blkdev_zone_mgmt {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t nr_sectors;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_completion {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[10];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tshort unsigned int ioprio;\n\tchar rwbs[10];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[10];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_zwplug {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int zno;\n\tsector_t sector;\n\tunsigned int nr_sectors;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trace_printk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bpf_string;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_trigger_tp {\n\tstruct trace_entry ent;\n\tint nonce;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bpf_xdp_link_attach_failed {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_add {\n\tstruct trace_entry ent;\n\tu8 ndm_flags;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tu16 nlh_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_external_learn_add {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_fdb_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_br_mdb_full {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tint af;\n\tu16 vid;\n\t__u8 src[16];\n\t__u8 grp[16];\n\t__u8 grpmac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_event {\n\tstruct trace_entry ent;\n\tconst struct cache_head *h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cap_capable {\n\tstruct trace_entry ent;\n\tconst struct cred *cred;\n\tstruct user_namespace *target_ns;\n\tconst struct user_namespace *capable_ns;\n\tint cap;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_level;\n\tu64 dst_id;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu32 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_rstat {\n\tstruct trace_entry ent;\n\tint root;\n\tint level;\n\tu64 id;\n\tint cpu;\n\tbool contended;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_busy_retry {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_finish {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tunsigned int align;\n\tint errorno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_alloc_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int request_count;\n\tlong unsigned int available_count;\n\tlong unsigned int total_count;\n\tunsigned int align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cma_release {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int pfn;\n\tconst struct page *page;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_begin {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_contention_end {\n\tstruct trace_entry ent;\n\tvoid *lock_addr;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_context_tracking_user {\n\tstruct trace_entry ent;\n\tint dummy;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_idle_miss {\n\tstruct trace_entry ent;\n\tu32 cpu_id;\n\tu32 state;\n\tbool below;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_function {\n\tstruct trace_entry ent;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_csd_queue_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *func;\n\tvoid *csd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\tu32 ctime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ctime_ns_xchg {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tu32 gen;\n\tu32 old;\n\tu32 new;\n\tu32 cur;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pmd_fault_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tlong unsigned int pgoff;\n\tlong unsigned int max_pgoff;\n\tdev_t dev;\n\tunsigned int flags;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pmd_load_hole_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tstruct folio *zero_folio;\n\tvoid *radix_entry;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_pte_fault_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tvm_flags_t vm_flags;\n\tlong unsigned int address;\n\tlong unsigned int pgoff;\n\tdev_t dev;\n\tunsigned int flags;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_writeback_one {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int pgoff;\n\tlong unsigned int pglen;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dax_writeback_range_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong unsigned int start_index;\n\tlong unsigned int end_index;\n\tdev_t dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_parent;\n\tu32 __data_loc_pm_ops;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_recover_aborted {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tbool health_state;\n\tu64 time_since_last_recover;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_health_reporter_state_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_reporter_name;\n\tu8 new_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwerr {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tint err;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_hwmsg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tbool incoming;\n\tlong unsigned int type;\n\tu32 __data_loc_buf;\n\tsize_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devlink_trap_report {\n\tstruct trace_entry ent;\n\tu32 __data_loc_bus_name;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_driver_name;\n\tu32 __data_loc_trap_name;\n\tu32 __data_loc_trap_group_name;\n\tchar input_dev_name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_devres {\n\tstruct trace_entry ent;\n\tu32 __data_loc_devname;\n\tstruct device *dev;\n\tconst char *op;\n\tvoid *node;\n\tu32 __data_loc_name;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tgfp_t flags;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_alloc_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tgfp_t flags;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_attach_dev {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tstruct dma_buf_attachment *attach;\n\tbool is_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_buf_fd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_exp_name;\n\tsize_t size;\n\tino_t ino;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_fence_unsignaled {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_class {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tvoid *virt_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_free_sgt {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 phys_addr;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tint full_nents;\n\tint full_ents;\n\tbool truncated;\n\tu32 __data_loc_phys_addrs;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_phys_addrs;\n\tint err;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_dma_addrs;\n\tu32 __data_loc_lengths;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_sync_single {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 dma_addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu64 addr;\n\tsize_t size;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_addrs;\n\tenum dma_data_direction dir;\n\tlong unsigned int attrs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dql_stall_detected {\n\tstruct trace_entry ent;\n\tshort unsigned int thrs;\n\tunsigned int len;\n\tlong unsigned int last_reap;\n\tlong unsigned int hist_head;\n\tlong unsigned int now;\n\tlong unsigned int hist[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_e1000e_trace_mac_register {\n\tstruct trace_entry ent;\n\tuint32_t reg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_error_report_template {\n\tstruct trace_entry ent;\n\tenum error_detector error_detector;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_exit_mmap {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tstruct maple_tree *mt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_shrink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_to_scan;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__fallocate_mode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tint mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int flags;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int mflags;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mb_new_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 pa_pstart;\n\t__u64 pa_lstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mballoc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__trim {\n\tstruct trace_entry ent;\n\tint dev_major;\n\tint dev_minor;\n\t__u32 group;\n\tint start;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int copied;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_alloc_da_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int data_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_begin_ordered_truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_collapse_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_release_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint freed_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint reserve_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_update_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint used_blocks;\n\tint reserved_data_blocks;\n\tint quota_claim;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_folios_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t start_pos;\n\tloff_t next_pos;\n\tlong int nr_to_write;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 lblk;\n\t__u32 len;\n\t__u32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 blk;\n\t__u64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_drop_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint drop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tconst char *function;\n\tunsigned int line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_insert_delayed_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tbool lclu_allocated;\n\tbool end_allocated;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tint found;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_remove_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t lblk;\n\tloff_t len;\n\tu64 seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tlong long unsigned int scan_time;\n\tint nr_skipped;\n\tint retried;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_evict_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_fastpath {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\text4_lblk_t i_lblk;\n\tunsigned int i_len;\n\text4_fsblk_t i_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_handle_unwritten_extents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tunsigned int allocated;\n\text4_fsblk_t newblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_load_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tshort unsigned int eh_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_idx {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_leaf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t ee_lblk;\n\text4_fsblk_t ee_pblk;\n\tshort int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_show_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tshort unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fallocate_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int blocks;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_cleanup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint j_fc_off;\n\tint full;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_commit_stop {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nblks;\n\tint reason;\n\tint num_fc;\n\tint num_fc_ineligible;\n\tint nblks_agg;\n\ttid_t tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint tag;\n\tint ino;\n\tint priv1;\n\tint priv2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_replay_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint error;\n\tint off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int fc_ineligible_rc[13];\n\tlong unsigned int fc_commits;\n\tlong unsigned int fc_ineligible_commits;\n\tlong unsigned int fc_numblks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_dentry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fc_track_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t t_tid;\n\tino_t i_ino;\n\ttid_t i_sync_tid;\n\tlong int start;\n\tlong int end;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_forget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tint is_metadata;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tlong unsigned int count;\n\tint flags;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u64 blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu32 agno;\n\tu64 bno;\n\tu64 len;\n\tu64 owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_implied_cluster_alloc_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu64 block;\n\tu64 len;\n\tu64 owner;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_insert_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_invalidate_folio_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tsize_t offset;\n\tsize_t length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_inode {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_reserved {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_lazy_itable_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_load_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mark_inode_dirty {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint needed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_group_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 pa_pstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_inode_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\t__u32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 goal_logical;\n\tint goal_start;\n\t__u32 goal_group;\n\tint goal_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\t__u16 found;\n\t__u16 groups;\n\t__u16 buddy;\n\t__u16 flags;\n\t__u16 tail;\n\t__u8 cr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_prealloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tunsigned int orig_flags;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_move_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t orig_ino;\n\text4_lblk_t orig_lblk;\n\tino_t donor_ino;\n\text4_lblk_t donor_lblk;\n\tunsigned int m_len;\n\tu64 move_len;\n\tint move_type;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_nfs_commit_metadata {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_other_inode_update_time {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t orig_ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_prefetch_bitmaps {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\t__u32 next;\n\t__u32 ios;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_read_block_bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tbool prefetch;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_remove_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\text4_fsblk_t ee_pblk;\n\text4_lblk_t ee_lblk;\n\tshort unsigned int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tint datasync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_update_sb {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\text4_fsblk_t fsblk;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages_result {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tint pages_written;\n\tlong int pages_skipped;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fdb_delete {\n\tstruct trace_entry ent;\n\tu32 __data_loc_br_dev;\n\tu32 __data_loc_dev;\n\tunsigned char addr[6];\n\tu16 vid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ff_layout_commit_error {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib6_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu32 flowlabel;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[16];\n\t__u8 dst[16];\n\tu16 sport;\n\tu16 dport;\n\tu8 proto;\n\tu8 rt_type;\n\tchar name[16];\n\t__u8 gw[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tchar name[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lease *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tlong unsigned int break_time;\n\tlong unsigned int downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock_core *blocker;\n\tfl_owner_t owner;\n\tunsigned int pid;\n\tunsigned int flags;\n\tunsigned char type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fill_mg_cmtime {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\ttime64_t ctime_s;\n\ttime64_t mtime_s;\n\tu32 ctime_ns;\n\tu32 mtime_ns;\n\tu32 gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_fl_getdevinfo {\n\tstruct trace_entry ent;\n\tu32 __data_loc_mds_addr;\n\tunsigned char deviceid[16];\n\tu32 __data_loc_ds_ips;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_flush_foreign {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tunsigned int frn_bdi_id;\n\tunsigned int frn_memcg_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_free_vmap_area_noflush {\n\tstruct trace_entry ent;\n\tlong unsigned int va_start;\n\tlong unsigned int nr_lazy;\n\tlong unsigned int nr_lazy_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t owner;\n\tunsigned int flags;\n\tunsigned char type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_guest_halt_poll_ns {\n\tstruct trace_entry ent;\n\tbool grow;\n\tunsigned int new;\n\tunsigned int old;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_alert_class {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int level;\n\tlong unsigned int description;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_complete {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint status;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_error_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint err;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_event_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_handshake_fd_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tconst void *sk;\n\tint fd;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hash_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int access;\n\tlong unsigned int trap;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hcall_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int opcode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hcall_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int opcode;\n\tlong int retval;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_setup {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugepage_set {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugepage_update {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tlong unsigned int clr;\n\tlong unsigned int set;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs__inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u16 mode;\n\tloff_t size;\n\tunsigned int nlink;\n\tunsigned int seals;\n\tblkcnt_t blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_alloc_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_fallocate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint mode;\n\tloff_t offset;\n\tloff_t len;\n\tloff_t size;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hugetlbfs_setattr {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int d_len;\n\tu32 __data_loc_d_name;\n\tunsigned int ia_valid;\n\tunsigned int ia_mode;\n\tloff_t old_size;\n\tloff_t ia_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_class {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tlong long int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_show_string {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tu32 __data_loc_label;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 nr_msgs;\n\t__s16 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_icmp_send {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint type;\n\tint code;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u16 sport;\n\t__u16 dport;\n\tshort unsigned int ulen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sk_error_report {\n\tstruct trace_entry ent;\n\tint error;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\ntypedef int (*initcall_t)(void);\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_foreign_history {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t cgroup_ino;\n\tunsigned int history;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inode_switch_wbs_queue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t old_cgroup_ino;\n\tino_t new_cgroup_ino;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint res;\n\tunsigned int cflags;\n\tu64 extra1;\n\tu64 extra2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqe_overflow {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tlong long unsigned int user_data;\n\ts32 res;\n\tu32 cflags;\n\tvoid *ocqe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tu8 opcode;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tvoid *link;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_local_work_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint count;\n\tunsigned int loops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tint events;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tu64 user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tstruct io_wq_work *work;\n\tbool hashed;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_req_failed {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tu8 flags;\n\tu8 ioprio;\n\tu64 off;\n\tu64 addr;\n\tu32 len;\n\tu32 op_flags;\n\tu16 buf_index;\n\tu16 personality;\n\tu32 file_index;\n\tu64 pad1;\n\tu64 addr3;\n\tint error;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_short_write {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu64 fpos;\n\tu64 wanted;\n\tu64 got;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_req {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tlong long unsigned int flags;\n\tbool sq_thread;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int user_data;\n\tu8 opcode;\n\tint mask;\n\tu32 __data_loc_op_str;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_work_run {\n\tstruct trace_entry ent;\n\tvoid *tctx;\n\tunsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_add_to_ioend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 pos;\n\tu64 dirty_len;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tint ki_flags;\n\tbool aio;\n\tint error;\n\tssize_t ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_dio_rw_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t isize;\n\tloff_t pos;\n\tsize_t count;\n\tsize_t done_before;\n\tint ki_flags;\n\tunsigned int dio_flags;\n\tbool aio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_iter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t pos;\n\tu64 length;\n\tint status;\n\tunsigned int flags;\n\tconst void *ops;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t size;\n\tloff_t offset;\n\tu64 length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpu {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ipi_send_cpumask {\n\tstruct trace_entry ent;\n\tu32 __data_loc_cpumask;\n\tvoid *callsite;\n\tvoid *callback;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int chp_time;\n\t__u32 forced_to_close;\n\t__u32 written;\n\t__u32 dropped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_end_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\ttid_t transaction;\n\ttid_t head;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_extend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint buffer_credits;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_start_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint interval;\n\tint sync;\n\tint requested_blocks;\n\tint dirtied_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_journal_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_lock_buffer_stall {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int stall_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_run_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tid;\n\tlong unsigned int wait;\n\tlong unsigned int request_delay;\n\tlong unsigned int running;\n\tlong unsigned int locked;\n\tlong unsigned int flushing;\n\tlong unsigned int logging;\n\t__u32 handle_count;\n\t__u32 blocks;\n\t__u32 blocks_logged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_checkpoint_list {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t first_tid;\n\ttid_t tid;\n\ttid_t last_tid;\n\tlong unsigned int nr_freed;\n\ttid_t next_tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_shrunk;\n\tlong unsigned int count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_submit_inode_data {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_update_log_tail {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tail_sequence;\n\ttid_t first_tid;\n\tlong unsigned int block_nr;\n\tlong unsigned int freed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_write_superblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tblk_opf_t write_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tvoid *rx_sk;\n\tshort unsigned int protocol;\n\tenum skb_drop_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmalloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tint node;\n\tbool accounted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_cache_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_advisor {\n\tstruct trace_entry ent;\n\ts64 scan_time;\n\tlong unsigned int pages_to_scan;\n\tunsigned int cpu_percent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_enter_exit_template {\n\tstruct trace_entry ent;\n\tvoid *mm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_merge_one_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_merge_with_ksm_page {\n\tstruct trace_entry ent;\n\tvoid *ksm_page;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_remove_ksm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_remove_rmap_item {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tvoid *rmap_item;\n\tvoid *mm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ksm_scan_template {\n\tstruct trace_entry ent;\n\tint seq;\n\tu32 rmap_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_op {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_read {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ma_write {\n\tstruct trace_entry ent;\n\tconst char *fn;\n\tlong unsigned int min;\n\tlong unsigned int max;\n\tlong unsigned int index;\n\tlong unsigned int last;\n\tlong unsigned int piv;\n\tvoid *val;\n\tvoid *node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tu32 __data_loc_comm;\n\tlong unsigned int total_vm;\n\tlong unsigned int anon_rss;\n\tlong unsigned int file_rss;\n\tlong unsigned int shmem_rss;\n\tuid_t uid;\n\tlong unsigned int pgtables;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mc_event {\n\tstruct trace_entry ent;\n\tunsigned int error_type;\n\tu32 __data_loc_msg;\n\tu32 __data_loc_label;\n\tu16 error_count;\n\tu8 mc_index;\n\ts8 top_layer;\n\ts8 middle_layer;\n\ts8 lower_layer;\n\tlong int address;\n\tu8 grain_bits;\n\tlong int syndrome;\n\tu32 __data_loc_driver_detail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mdio_access {\n\tstruct trace_entry ent;\n\tchar busid[61];\n\tchar read;\n\tu8 addr;\n\tu16 val;\n\tunsigned int regnum;\n\tchar __data[0];\n};\n\nstruct xdp_mem_allocator;\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_flush_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\ts64 stats_updates;\n\tbool force;\n\tbool needs_flush;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_events {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tlong unsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_memcg_rstat_stats {\n\tstruct trace_entry ent;\n\tu64 id;\n\tint item;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pmd {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_migration_pte {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int pte;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_calculate_totalreserve_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int totalreserve_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tint isolated;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page_isolate {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint none_or_zero;\n\tint referenced;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_collapse_huge_page_swapin {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tint swapped_in;\n\tint referenced;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_fault {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tunsigned char order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache_range {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int last_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_collapse_file {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int hpfn;\n\tlong unsigned int index;\n\tlong unsigned int addr;\n\tbool is_shmem;\n\tu32 __data_loc_filename;\n\tint nr;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_scan_file {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tu32 __data_loc_filename;\n\tint present;\n\tint swap;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_khugepaged_scan_pmd {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tint referenced;\n\tint none_or_zero;\n\tint status;\n\tint unmapped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct folio *folio;\n\tlong unsigned int pfn;\n\tenum lru_list lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tlong unsigned int thp_succeeded;\n\tlong unsigned int thp_failed;\n\tlong unsigned int thp_split;\n\tlong unsigned int large_folio_split;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_migrate_pages_start {\n\tstruct trace_entry ent;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tint percpu_refill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tlong unsigned int gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_lowmem_reserve {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tu32 __data_loc_upper_name;\n\tlong int lowmem_reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_setup_per_zone_wmarks {\n\tstruct trace_entry ent;\n\tint node_id;\n\tu32 __data_loc_name;\n\tlong unsigned int watermark_min;\n\tlong unsigned int watermark_low;\n\tlong unsigned int watermark_high;\n\tlong unsigned int watermark_promo;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tlong unsigned int gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_clear_hopeless {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_reclaim_fail {\n\tstruct trace_entry ent;\n\tint nid;\n\tint failures;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_reclaim_pages {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_throttled {\n\tstruct trace_entry ent;\n\tint nid;\n\tint usec_timeout;\n\tint usec_delayed;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_write_folio {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mmap_lock_acquire_returned {\n\tstruct trace_entry ent;\n\tstruct mm_struct *mm;\n\tu64 memcg_id;\n\tbool write;\n\tbool success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tu64 net_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netlink_extack {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cached_open {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_error_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 cbident;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_offload {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 fhandle;\n\tloff_t cb_count;\n\tint cb_how;\n\tint cb_stateid_seq;\n\tu32 cb_stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_seqid_err {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int cachethis;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_clientid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_close {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_commit_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tloff_t offset;\n\tu32 count;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegation_event {\n\tstruct trace_entry ent;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegreturn_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_deviceid_status {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint status;\n\tu32 __data_loc_dstaddr;\n\tunsigned char deviceid[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_flexfiles_io_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int nfs_error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_getattr_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int valid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_idmap_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 id;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_layoutget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 iomode;\n\tu64 offset;\n\tu64 count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lock_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookup_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookupp {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_match_stateid_event {\n\tstruct trace_entry ent;\n\tint s1_seq;\n\tint s2_seq;\n\tu32 s1_hash;\n\tu32 s2_hash;\n\tint s1_type;\n\tint s2_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_open_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint openstateid_seq;\n\tu32 openstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_read_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 olddir;\n\tu32 __data_loc_oldname;\n\tu64 newdir;\n\tu32 __data_loc_newname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_sequence_done {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_slotid;\n\tunsigned int target_highest_slotid;\n\tlong unsigned int status_flags;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_delegation_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_lock {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int cmd;\n\tlong unsigned int type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint lockstateid_seq;\n\tu32 lockstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_setup_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_used_slotid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_lock_reclaim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int state_flags;\n\tlong unsigned int lock_flags;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr_failed {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tu32 __data_loc_section;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_test_stateid_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_trunked_exchange_id {\n\tstruct trace_entry ent;\n\tu32 __data_loc_main_addr;\n\tu32 __data_loc_trunk_addr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_write_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_bad_operation {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tu32 expected;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_access_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tunsigned int mask;\n\tunsigned int permitted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_aop_readahead_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tunsigned int nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tlong unsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_commit_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_direct_req_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t offset;\n\tssize_t count;\n\tssize_t error;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_fh_to_dentry {\n\tstruct trace_entry ent;\n\tint error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_folio_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tint ret;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_read {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_write {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tlong unsigned int stable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_range_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t range_start;\n\tloff_t range_end;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_kiocb_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t offset;\n\tsize_t count;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_local_open_fh {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 fhandle;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu64 fileid;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_assign {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tu32 __data_loc_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_option {\n\tstruct trace_entry ent;\n\tu32 __data_loc_option;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_mount_path {\n\tstruct trace_entry ent;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tconst struct nfs_page *req;\n\tloff_t offset;\n\tunsigned int count;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tunsigned int count;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_pgio_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tloff_t pos;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readdir_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tchar verifier[8];\n\tu64 cookie;\n\tlong unsigned int index;\n\tunsigned int dtsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_short {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 old_dir;\n\tu64 new_dir;\n\tu32 __data_loc_old_name;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 old_dir;\n\tu32 __data_loc_old_name;\n\tu64 new_dir;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_sillyrename_unlink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_update_size_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tloff_t cur_size;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_writeback_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tint error;\n\tlong unsigned int stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_xdr_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tlong unsigned int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nlmclnt_lock_event {\n\tstruct trace_entry ent;\n\tu32 oh;\n\tu32 svid;\n\tu32 fh;\n\tlong unsigned int status;\n\tu64 start;\n\tu64 len;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_non_standard_event {\n\tstruct trace_entry ent;\n\tchar sec_type[16];\n\tchar fru_id[16];\n\tu32 __data_loc_fru_text;\n\tu8 sev;\n\tu32 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_notifier_info {\n\tstruct trace_entry ent;\n\tvoid *cb;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_opal_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int opcode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_opal_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int opcode;\n\tlong unsigned int retval;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_op {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n\tlong unsigned int req_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_order {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tunsigned int order;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_cache_ra_unbounded {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tlong unsigned int index;\n\tlong unsigned int nr_to_read;\n\tlong unsigned int lookahead_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\ts32 inflight;\n\tu32 hold;\n\tu32 release;\n\tu64 cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_hold {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 hold;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_state_release {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tlong unsigned int netmem;\n\tu32 release;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_page_pool_update_nid {\n\tstruct trace_entry ent;\n\tconst struct page_pool *pool;\n\tint pool_nid;\n\tint new_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pci_hp_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tu32 __data_loc_slot;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pcie_link_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_port_name;\n\tunsigned int type;\n\tunsigned int reason;\n\tunsigned int cur_bus_speed;\n\tunsigned int max_bus_speed;\n\tunsigned int width;\n\tunsigned int flit_mode;\n\tunsigned int link_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tsize_t bytes_alloc;\n\tlong unsigned int gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pmap_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_bl_pr_key_err_class {\n\tstruct trace_entry ent;\n\tu64 key;\n\tdev_t dev;\n\tlong unsigned int status;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_ds_connect {\n\tstruct trace_entry ent;\n\tu32 __data_loc_ds_ips;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_layout_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pnfs_update_layout {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu32 fhandle;\n\tloff_t pos;\n\tu64 count;\n\tenum pnfs_iomode iomode;\n\tint layoutstateid_seq;\n\tu32 layoutstateid_hash;\n\tlong int lseg;\n\tenum pnfs_update_layout_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_powernv_throttle {\n\tstruct trace_entry ent;\n\tint chip_id;\n\tu32 __data_loc_reason;\n\tint pmax;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ppc64_interrupt_class {\n\tstruct trace_entry ent;\n\tstruct pt_regs *regs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_purge_vmap_area_lazy {\n\tstruct trace_entry ent;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int npurged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_enqueue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kvfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_nocb_wake {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint cpu;\n\tconst char *reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_segcb_stats {\n\tstruct trace_entry ent;\n\tconst char *ctx;\n\tlong unsigned int gp_seq[4];\n\tlong int seglen[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_sr_normal {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tconst char *srevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_stall_warning {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_watching {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint counter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_drop_region {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int from;\n\tunsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_sync {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_status;\n\tu32 __data_loc_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_register_class {\n\tstruct trace_entry ent;\n\tu32 version;\n\tlong unsigned int family;\n\tshort unsigned int protocol;\n\tshort unsigned int port;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_async {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_block {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bool {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bulk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tu32 __data_loc_buf;\n\tint val_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_reg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_buf_alloc {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tsize_t callsize;\n\tsize_t recvsize;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_call_rpcerror {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint tk_status;\n\tint rpc_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_class {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_clone_err {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tlong unsigned int xprtsec;\n\tlong unsigned int flags;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new_err {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_failure {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_reply_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 __data_loc_progname;\n\tu32 version;\n\tu32 __data_loc_procname;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_request {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tbool async;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_socket_nospace {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int total;\n\tunsigned int remaining;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_stats_latency {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tlong unsigned int backlog;\n\tlong unsigned int rtt;\n\tlong unsigned int execute;\n\tu32 xprt_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_queued {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tlong unsigned int timeout;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tu32 __data_loc_q_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_running {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *action;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_tls_class {\n\tstruct trace_entry ent;\n\tlong unsigned int requested_policy;\n\tu32 version;\n\tu32 __data_loc_servername;\n\tu32 __data_loc_progname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_alignment {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t offset;\n\tunsigned int copied;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_overflow {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t requested;\n\tconst void *end;\n\tconst void *p;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_lifetime_class {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_getport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int program;\n\tunsigned int version;\n\tint protocol;\n\tunsigned int bind_version;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_register {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_setport {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tshort unsigned int port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcb_unregister {\n\tstruct trace_entry ent;\n\tunsigned int program;\n\tunsigned int version;\n\tu32 __data_loc_netid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_bad_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 expected;\n\tu32 received;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_context {\n\tstruct trace_entry ent;\n\tlong unsigned int expiry;\n\tlong unsigned int now;\n\tunsigned int timeout;\n\tu32 window_size;\n\tint len;\n\tu32 __data_loc_acceptor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_createauth {\n\tstruct trace_entry ent;\n\tunsigned int flavor;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_ctx_class {\n\tstruct trace_entry ent;\n\tconst void *cred;\n\tlong unsigned int service;\n\tu32 __data_loc_principal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_gssapi_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 maj_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_import_ctx {\n\tstruct trace_entry ent;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_need_reencode {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seq_xmit;\n\tu32 seqno;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_oid_to_mech {\n\tstruct trace_entry ent;\n\tu32 __data_loc_oid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_accept_upcall {\n\tstruct trace_entry ent;\n\tu32 minor_status;\n\tlong unsigned int major_status;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 seqno;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_gssapi_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 maj_stat;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_bad {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_low {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_unwrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_wrap_failed {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_unwrap_failed {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_result {\n\tstruct trace_entry ent;\n\tu32 uid;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_update_slack {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tconst void *auth;\n\tunsigned int rslack;\n\tunsigned int ralign;\n\tunsigned int verfsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_internal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flags;\n\tint usage_count;\n\tint disable_depth;\n\tint runtime_auto;\n\tint request_pending;\n\tint irq_safe;\n\tint child_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_return_int {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int ip;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\ts32 node_id;\n\ts32 mm_cid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtas_input {\n\tstruct trace_entry ent;\n\t__u32 nargs;\n\tu32 __data_loc_name;\n\tu32 __data_loc_inputs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtas_output {\n\tstruct trace_entry ent;\n\t__u32 nr_other;\n\t__s32 status;\n\tu32 __data_loc_name;\n\tu32 __data_loc_other_outputs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtas_parameter_block {\n\tstruct trace_entry ent;\n\tu32 token;\n\tu32 nargs;\n\tu32 nret;\n\t__u32 params[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_alarm_irq_enable {\n\tstruct trace_entry ent;\n\tunsigned int enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_freq {\n\tstruct trace_entry ent;\n\tint freq;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_state {\n\tstruct trace_entry ent;\n\tint enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_offset_class {\n\tstruct trace_entry ent;\n\tlong int offset;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_time_alarm_class {\n\tstruct trace_entry ent;\n\ttime64_t secs;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_timer_class {\n\tstruct trace_entry ent;\n\tstruct rtc_timer *timer;\n\tktime_t expires;\n\tktime_t period;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_bypass_lb {\n\tstruct trace_entry ent;\n\t__u32 node;\n\t__u32 nr_cpus;\n\t__u32 nr_tasks;\n\t__u32 nr_balanced;\n\t__u32 before_min;\n\t__u32 before_max;\n\t__u32 after_min;\n\t__u32 after_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_dump {\n\tstruct trace_entry ent;\n\tu32 __data_loc_line;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_ext_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\t__s64 delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_work_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *worker;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_move_numa {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_numa_pair_template {\n\tstruct trace_entry ent;\n\tpid_t src_pid;\n\tpid_t src_tgid;\n\tpid_t src_ngid;\n\tint src_cpu;\n\tint src_nid;\n\tpid_t dst_pid;\n\tpid_t dst_tgid;\n\tpid_t dst_ngid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_prepare_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_interp;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exit {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tbool group_dead;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tu32 __data_loc_parent_comm;\n\tpid_t parent_pid;\n\tu32 __data_loc_child_comm;\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_hang {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_cpuset_numa {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tlong unsigned int mem_allowed[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_skip_vma_numa {\n\tstruct trace_entry ent;\n\tlong unsigned int numa_scan_offset;\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tenum numa_vmaskip_reason reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 runtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_comm;\n\tpid_t pid;\n\tu64 delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tint driver_tag;\n\tint scheduler_tag;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_selinux_audited {\n\tstruct trace_entry ent;\n\tu32 requested;\n\tu32 denied;\n\tu32 audited;\n\tint result;\n\tu32 __data_loc_scontext;\n\tu32 __data_loc_tcontext;\n\tu32 __data_loc_tclass;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sk_data_ready {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 family;\n\t__u16 protocol;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 flags;\n\t__u16 addr;\n\t__u8 command;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 read_write;\n\t__u8 command;\n\t__s16 res;\n\t__u32 protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int sysctl_mem[3];\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_msg_length {\n\tstruct trace_entry ent;\n\tvoid *sk;\n\t__u16 family;\n\t__u16 protocol;\n\tint ret;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_alloc_arg_err {\n\tstruct trace_entry ent;\n\tunsigned int requested;\n\tunsigned int allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int svc_status;\n\tlong unsigned int auth_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_deferred_event {\n\tstruct trace_entry ent;\n\tconst void *dr;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_pool_thread_event {\n\tstruct trace_entry ent;\n\tunsigned int pool_id;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_process {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 vers;\n\tu32 proc;\n\tu32 __data_loc_service;\n\tu32 __data_loc_procedure;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_replace_page_err {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tconst void *begin;\n\tconst void *respages;\n\tconst void *nextpage;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_status {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tint status;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_stats_latency {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tunsigned int netns_ino;\n\tu32 xid;\n\tlong unsigned int execute;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_unregister {\n\tstruct trace_entry ent;\n\tu32 version;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_msg_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_accept {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_service;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_create_err {\n\tstruct trace_entry ent;\n\tlong int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_dequeue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tlong unsigned int wakeup;\n\tlong unsigned int qtime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_enqueue {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_server;\n\tu32 __data_loc_client;\n\tlong unsigned int flags;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_accept_class {\n\tstruct trace_entry ent;\n\tlong int status;\n\tu32 __data_loc_service;\n\tunsigned int netns_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_class {\n\tstruct trace_entry ent;\n\tssize_t result;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_lifetime_class {\n\tstruct trace_entry ent;\n\tunsigned int netns_ino;\n\tconst void *svsk;\n\tconst void *sk;\n\tlong unsigned int type;\n\tlong unsigned int family;\n\tlong unsigned int state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_marker {\n\tstruct trace_entry ent;\n\tunsigned int length;\n\tbool last;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_recv_short {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_state {\n\tstruct trace_entry ent;\n\tlong unsigned int socket_state;\n\tlong unsigned int sock_state;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_swiotlb_bounced {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu64 dma_mask;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tbool force;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tu64 clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_prctl_unknown {\n\tstruct trace_entry ent;\n\tint option;\n\tlong unsigned int arg2;\n\tlong unsigned int arg3;\n\tlong unsigned int arg4;\n\tlong unsigned int arg5;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tasklet {\n\tstruct trace_entry ent;\n\tvoid *tasklet;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_ao_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\t__u8 keyid;\n\t__u8 rnext;\n\t__u8 maclen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_cong_state_set {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u8 cong_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_hash_event {\n\tstruct trace_entry ent;\n\t__u64 net_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tint l3index;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\tbool fin;\n\tbool syn;\n\tbool rst;\n\tbool psh;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\t__u64 sock_cookie;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_rcvbuf_grow {\n\tstruct trace_entry ent;\n\tint time;\n\t__u32 rtt_us;\n\t__u32 copied;\n\t__u32 inq;\n\t__u32 space;\n\t__u32 ooo_space;\n\t__u32 rcvbuf;\n\t__u32 rcv_ssthresh;\n\t__u32 window_clamp;\n\t__u32 rcv_wnd;\n\t__u8 scaling_ratio;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tconst void *skaddr;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_send_reset {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\tenum sk_rst_reason reason;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_sendmsg_locked {\n\tstruct trace_entry ent;\n\tconst void *skb_addr;\n\tint skb_len;\n\tint msg_left;\n\tint size_goal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_test_pages_isolated {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int fin_pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_base_idle {\n\tstruct trace_entry ent;\n\tbool is_idle;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int bucket_expiry;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tlbia {\n\tstruct trace_entry ent;\n\tlong unsigned int id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tlbie {\n\tstruct trace_entry ent;\n\tlong unsigned int lpid;\n\tlong unsigned int local;\n\tlong unsigned int rb;\n\tlong unsigned int rs;\n\tlong unsigned int ric;\n\tlong unsigned int prs;\n\tlong unsigned int r;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tls_contenttype {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tunsigned int netns_ino;\n\tlong unsigned int type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_child_parent {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_connect_cpu_parent {\n\tstruct trace_entry ent;\n\tvoid *parent;\n\tunsigned int cpu;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tunsigned int num_children;\n\tu32 groupmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_cpugroup {\n\tstruct trace_entry ent;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_and_cpu {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tvoid *parent;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tu32 childmask;\n\tu8 active;\n\tu8 migrator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_group_set {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tunsigned int numa_node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_handle_remote {\n\tstruct trace_entry ent;\n\tvoid *group;\n\tunsigned int lvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_idle {\n\tstruct trace_entry ent;\n\tu64 nextevt;\n\tu64 wakeup;\n\tvoid *parent;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tmigr_update_events {\n\tstruct trace_entry ent;\n\tvoid *child;\n\tvoid *group;\n\tu64 nextevt;\n\tu64 group_next_expiry;\n\tu64 child_evt_expiry;\n\tunsigned int group_lvl;\n\tunsigned int child_evtcpu;\n\tu8 child_active;\n\tu8 group_active;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_track_foreign_dirty {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tu64 bdi_id;\n\tino_t ino;\n\tunsigned int memcg_id;\n\tino_t cgroup_ino;\n\tino_t page_cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_usb_core_log_usb_device {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum usb_device_speed speed;\n\tenum usb_device_state state;\n\tshort unsigned int bus_mA;\n\tunsigned int authorized;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vas_paste_crb {\n\tstruct trace_entry ent;\n\tstruct task_struct *tsk;\n\tstruct vas_window *win;\n\tint pid;\n\tint vasid;\n\tint winid;\n\tlong unsigned int paste_kaddr;\n\tchar __data[0];\n};\n\nstruct vas_rx_win_attr;\n\nstruct trace_event_raw_vas_rx_win_open {\n\tstruct trace_entry ent;\n\tstruct task_struct *tsk;\n\tint pid;\n\tint cop;\n\tint vasid;\n\tstruct vas_rx_win_attr *rxattr;\n\tint lnotify_lpid;\n\tint lnotify_pid;\n\tint lnotify_tid;\n\tchar __data[0];\n};\n\nstruct vas_tx_win_attr;\n\nstruct trace_event_raw_vas_tx_win_open {\n\tstruct trace_entry ent;\n\tstruct task_struct *tsk;\n\tint pid;\n\tint cop;\n\tint vasid;\n\tstruct vas_tx_win_attr *txattr;\n\tint lpid;\n\tint pidr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tu32 __data_loc_workqueue;\n\tint req_cpu;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_folio_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_block_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_btree_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tu32 __data_loc_name;\n\tint level;\n\txfs_agnumber_t agno;\n\txfs_agblock_t bno;\n\tint ptr;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_btree_op_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tu32 __data_loc_name;\n\tint level;\n\txfs_agnumber_t agno;\n\txfs_agblock_t bno;\n\tint ptr;\n\tint error;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int type;\n\txfs_agnumber_t agno;\n\txfs_ino_t inum;\n\tunsigned int gen;\n\tunsigned int flags;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_dirpath_changed {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int path_nr;\n\tunsigned int step_nr;\n\txfs_ino_t child_ino;\n\txfs_ino_t parent_ino;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_dirpath_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int path_nr;\n\tunsigned int step_nr;\n\txfs_ino_t child_ino;\n\tunsigned int child_gen;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_dirpath_outcome_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int path_nr;\n\tunsigned int nr_steps;\n\tunsigned int outcome;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_dirtree_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int path_nr;\n\txfs_ino_t child_ino;\n\tunsigned int child_gen;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_dirtree_evaluate_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t rootino;\n\tunsigned int nr_paths;\n\tunsigned int bad;\n\tunsigned int suspect;\n\tunsigned int good;\n\tbool needs_adoption;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_dirtree_live_update {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t parent_ino;\n\tint action;\n\txfs_ino_t child_ino;\n\tint delta;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_fblock_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint whichfork;\n\tunsigned int type;\n\txfs_fileoff_t offset;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_file_op_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint whichfork;\n\tunsigned int type;\n\txfs_fileoff_t offset;\n\tint error;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_fscounters_calc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint64_t icount_sb;\n\tuint64_t icount_calculated;\n\tint64_t ifree_sb;\n\tuint64_t ifree_calculated;\n\tint64_t fdblocks_sb;\n\tuint64_t fdblocks_calculated;\n\tuint64_t delalloc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_fscounters_within_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint64_t expected;\n\tint64_t curr_value;\n\tint64_t old_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_fsfreeze_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_fsgate_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int fsgate_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_iallocbt_check_cluster {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t startino;\n\txfs_daddr_t map_daddr;\n\tshort unsigned int map_len;\n\tunsigned int chunk_ino;\n\tunsigned int nr_inodes;\n\tunsigned int cluster_ino;\n\tuint16_t cluster_mask;\n\tuint16_t holemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_ifork_btree_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint whichfork;\n\tunsigned int type;\n\tu32 __data_loc_name;\n\tint level;\n\txfs_agnumber_t agno;\n\txfs_agblock_t bno;\n\tint ptr;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_ifork_btree_op_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint whichfork;\n\tunsigned int type;\n\tu32 __data_loc_name;\n\tint level;\n\tint ptr;\n\txfs_agnumber_t agno;\n\txfs_agblock_t bno;\n\tint error;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_incomplete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_ino_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int type;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_inode_is_allocated {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tlong unsigned int iflags;\n\tumode_t mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_iscan_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t cursor;\n\txfs_ino_t visited;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_iscan_iget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t cursor;\n\txfs_ino_t visited;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_iscan_iget_batch {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t cursor;\n\txfs_ino_t visited;\n\tunsigned int nr;\n\tunsigned int avail;\n\tunsigned int unavail;\n\txfs_ino_t batch_ino;\n\tlong long unsigned int skipmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_iscan_ino_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t startino;\n\txfs_ino_t cursor;\n\txfs_ino_t visited;\n\txfs_ino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_iscan_retry_wait_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t cursor;\n\txfs_ino_t visited;\n\tunsigned int retry_delay;\n\tlong unsigned int remaining;\n\tunsigned int iget_timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_metapath_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t scrub_ino;\n\txfs_ino_t parent_ino;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_nlinks_check_zero {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_nlink_t parents;\n\txfs_nlink_t backrefs;\n\txfs_nlink_t children;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_nlinks_collect_dirent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir;\n\txfs_ino_t ino;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_nlinks_collect_metafile {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_nlinks_collect_pptr {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir;\n\txfs_ino_t ino;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_nlinks_diff_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tuint8_t ftype;\n\txfs_nlink_t nlink;\n\txfs_nlink_t parents;\n\txfs_nlink_t backrefs;\n\txfs_nlink_t children;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_nlinks_live_update {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir;\n\tint action;\n\txfs_ino_t ino;\n\tint delta;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_nlinks_update_incore {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_nlink_t parents;\n\txfs_nlink_t backrefs;\n\txfs_nlink_t children;\n\tint parents_delta;\n\tint backrefs_delta;\n\tint children_delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_op_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t bno;\n\tint error;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_pptr_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\txfs_ino_t far_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_refcount_incorrect {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain domain;\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\txfs_nlink_t refcount;\n\txfs_nlink_t seen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_sbtree_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint type;\n\tu32 __data_loc_name;\n\txfs_agnumber_t agno;\n\txfs_agblock_t bno;\n\tint level;\n\tint nlevels;\n\tint ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_vector_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int vec_nr;\n\tunsigned int vec_type;\n\tunsigned int vec_flags;\n\tint vec_ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_vector_head_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_agnumber_t agno;\n\txfs_ino_t inum;\n\tunsigned int gen;\n\tunsigned int flags;\n\tshort unsigned int rest_us;\n\tshort unsigned int nr_vecs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xchk_xref_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint type;\n\tint error;\n\tvoid *ret_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tunsigned int xdp_pass;\n\tunsigned int xdp_drop;\n\tunsigned int xdp_redirect;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfarray_create {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tuint64_t max_nr;\n\tsize_t obj_size;\n\tint obj_size_log;\n\tlong long unsigned int required_capacity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfarray_foliosort {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong long unsigned int lo;\n\tlong long unsigned int hi;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfarray_isort {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong long unsigned int lo;\n\tlong long unsigned int hi;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfarray_qsort {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong long unsigned int lo;\n\tlong long unsigned int hi;\n\tint stack_depth;\n\tint max_stack_depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfarray_sort {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong long unsigned int nr;\n\tsize_t obj_size;\n\tsize_t bytes;\n\tunsigned int max_stack_depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfarray_sort_scan {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong long unsigned int nr;\n\tsize_t obj_size;\n\tlong long unsigned int idx;\n\tlong long unsigned int folio_pos;\n\tlong unsigned int folio_bytes;\n\tlong long unsigned int first_idx;\n\tlong long unsigned int last_idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfarray_sort_stats {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tunsigned int max_stack_depth;\n\tunsigned int max_stack_used;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfbtree_buf_class {\n\tstruct trace_entry ent;\n\tlong unsigned int xfino;\n\txfs_daddr_t bno;\n\tint nblks;\n\tint hold;\n\tint pincount;\n\tunsigned int lockval;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfbtree_freesp_class {\n\tstruct trace_entry ent;\n\tlong unsigned int xfino;\n\tu32 __data_loc_btname;\n\tint nlevels;\n\txfs_fileoff_t fileoff;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfbtree_init {\n\tstruct trace_entry ent;\n\tconst void *btree_ops;\n\tlong unsigned int xfino;\n\tunsigned int leaf_mxr;\n\tunsigned int leaf_mnr;\n\tunsigned int node_mxr;\n\tunsigned int node_mnr;\n\tlong long unsigned int owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfile_class {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong long unsigned int bytes_used;\n\tloff_t pos;\n\tloff_t size;\n\tlong long unsigned int bytecount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfile_create {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar pathname[256];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfile_destroy {\n\tstruct trace_entry ent;\n\tlong unsigned int ino;\n\tlong long unsigned int bytes;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_inode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint resv;\n\txfs_extlen_t freeblks;\n\txfs_extlen_t flcount;\n\txfs_extlen_t reserved;\n\txfs_extlen_t asked;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ag_resv_init_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint error;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_agf_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint flags;\n\t__u32 length;\n\t__u32 bno_root;\n\t__u32 cnt_root;\n\t__u32 bno_level;\n\t__u32 cnt_level;\n\t__u32 flfirst;\n\t__u32 fllast;\n\t__u32 flcount;\n\t__u32 freeblks;\n\t__u32 longest;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_ail_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tvoid *lip;\n\tuint type;\n\tlong unsigned int flags;\n\txfs_lsn_t old_lsn;\n\txfs_lsn_t new_lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_alloc_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t minlen;\n\txfs_extlen_t maxlen;\n\txfs_extlen_t mod;\n\txfs_extlen_t prod;\n\txfs_extlen_t minleft;\n\txfs_extlen_t total;\n\txfs_extlen_t alignment;\n\txfs_extlen_t minalignslop;\n\txfs_extlen_t len;\n\tchar wasdel;\n\tchar wasfromfl;\n\tint resv;\n\tint datatype;\n\txfs_agnumber_t highest_agno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_alloc_cur_check {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\txfs_agblock_t bno;\n\txfs_extlen_t len;\n\txfs_extlen_t diff;\n\tbool new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_attr_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\tint namelen;\n\tint valuelen;\n\txfs_dahash_t hashval;\n\tunsigned int attr_filter;\n\tuint32_t op_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_attr_list_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 hashval;\n\tu32 blkno;\n\tu32 offset;\n\tvoid *buffer;\n\tint bufsize;\n\tint count;\n\tint firstu;\n\tint dupcnt;\n\tunsigned int attr_filter;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_attr_list_node_descend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 hashval;\n\tu32 blkno;\n\tu32 offset;\n\tvoid *buffer;\n\tint bufsize;\n\tint count;\n\tint firstu;\n\tint dupcnt;\n\tunsigned int attr_filter;\n\tu32 bt_hashval;\n\tu32 bt_before;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_bmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tvoid *leaf;\n\tint pos;\n\txfs_fileoff_t startoff;\n\txfs_fsblock_t startblock;\n\txfs_filblks_t blockcount;\n\txfs_exntst_t state;\n\tint bmap_state;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_bmap_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tlong long unsigned int gbno;\n\tint whichfork;\n\txfs_fileoff_t l_loff;\n\txfs_filblks_t l_len;\n\txfs_exntst_t l_state;\n\tint op;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_alloc_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\tint error;\n\txfs_agblock_t agbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_bload_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tunsigned int level;\n\tlong long unsigned int block_idx;\n\tlong long unsigned int nr_blocks;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tunsigned int nr_records;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_bload_level_geometry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tunsigned int level;\n\tunsigned int nlevels;\n\tuint64_t nr_this_level;\n\tunsigned int nr_per_block;\n\tunsigned int desired_npb;\n\tlong long unsigned int blocks;\n\tlong long unsigned int blocks_with_extra;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_commit_afakeroot {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tunsigned int levels;\n\tunsigned int blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_commit_ifakeroot {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tunsigned int levels;\n\tunsigned int blocks;\n\tint whichfork;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_cur_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tint level;\n\tint nlevels;\n\tint ptr;\n\txfs_daddr_t daddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tint error;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_btree_free_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\txfs_agblock_t agbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_buf_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t bno;\n\tint nblks;\n\tint hold;\n\tint pincount;\n\tunsigned int lockval;\n\tunsigned int flags;\n\tlong unsigned int caller_ip;\n\tconst void *buf_ops;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_buf_flags_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t bno;\n\tunsigned int length;\n\tint hold;\n\tint pincount;\n\tunsigned int lockval;\n\tunsigned int flags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\ntypedef void *xfs_failaddr_t;\n\nstruct trace_event_raw_xfs_buf_ioerror {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t bno;\n\tunsigned int length;\n\tunsigned int flags;\n\tint hold;\n\tint pincount;\n\tunsigned int lockval;\n\tint error;\n\txfs_failaddr_t caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_buf_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t buf_bno;\n\tunsigned int buf_len;\n\tint buf_hold;\n\tint buf_pincount;\n\tint buf_lockval;\n\tunsigned int buf_flags;\n\tunsigned int bli_recur;\n\tint bli_refcount;\n\tunsigned int bli_flags;\n\tlong unsigned int li_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_bunmap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsize_t size;\n\txfs_fileoff_t fileoff;\n\txfs_filblks_t len;\n\tlong unsigned int caller_ip;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_calc_atomic_write_unit_max {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\tunsigned int max_write;\n\tunsigned int max_ioend;\n\tunsigned int max_gsize;\n\tunsigned int awu_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_calc_max_atomic_write_fsblocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int per_intent;\n\tunsigned int step_size;\n\tunsigned int logres;\n\tunsigned int blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_calc_max_atomic_write_log_geometry {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int per_intent;\n\tunsigned int step_size;\n\tunsigned int blockcount;\n\tunsigned int min_logblocks;\n\tunsigned int cur_logblocks;\n\tunsigned int logres;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_check_new_dalign {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint new_dalign;\n\txfs_ino_t sb_rootino;\n\txfs_ino_t calc_rootino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_da_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu32 __data_loc_name;\n\tint namelen;\n\txfs_dahash_t hashval;\n\txfs_ino_t inumber;\n\tuint32_t op_flags;\n\txfs_ino_t owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_das_state_class {\n\tstruct trace_entry ent;\n\tint das;\n\txfs_ino_t ino;\n\tchar __data[0];\n};\n\nstruct xfs_trans;\n\nstruct trace_event_raw_xfs_defer_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tstruct xfs_trans *tp;\n\tchar committed;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_defer_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tstruct xfs_trans *tp;\n\tchar committed;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_defer_pending_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tvoid *intent;\n\tunsigned int flags;\n\tchar committed;\n\tint nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_defer_pending_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tvoid *intent;\n\tvoid *item;\n\tchar committed;\n\tunsigned int flags;\n\tint nr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dir2_leafn_moveents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tuint32_t op_flags;\n\tint src_idx;\n\tint dst_idx;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dir2_space_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tuint32_t op_flags;\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_discard_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_double_io_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t src_ino;\n\tloff_t src_isize;\n\tloff_t src_disize;\n\tloff_t src_offset;\n\tlong long int len;\n\txfs_ino_t dest_ino;\n\tloff_t dest_isize;\n\tloff_t dest_disize;\n\tloff_t dest_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dqtrx_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_dqtype_t type;\n\tunsigned int flags;\n\tu32 dqid;\n\tuint64_t blk_res;\n\tint64_t bcount_delta;\n\tint64_t delbcnt_delta;\n\tuint64_t rtblk_res;\n\tuint64_t rtblk_res_used;\n\tint64_t rtbcount_delta;\n\tint64_t delrtb_delta;\n\tuint64_t ino_res;\n\tuint64_t ino_res_used;\n\tint64_t icount_delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_dquot_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 id;\n\txfs_dqtype_t type;\n\tunsigned int flags;\n\tunsigned int nrefs;\n\tlong long unsigned int res_bcount;\n\tlong long unsigned int res_rtbcount;\n\tlong long unsigned int res_icount;\n\tlong long unsigned int bcount;\n\tlong long unsigned int rtbcount;\n\tlong long unsigned int icount;\n\tlong long unsigned int blk_hardlimit;\n\tlong long unsigned int blk_softlimit;\n\tlong long unsigned int rtb_hardlimit;\n\tlong long unsigned int rtb_softlimit;\n\tlong long unsigned int ino_hardlimit;\n\tlong long unsigned int ino_softlimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_delta_nextents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino1;\n\txfs_ino_t ino2;\n\txfs_extnum_t nexts1;\n\txfs_extnum_t nexts2;\n\tint64_t d_nexts1;\n\tint64_t d_nexts2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_delta_nextents_step {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_fileoff_t loff;\n\txfs_fsblock_t lstart;\n\txfs_filblks_t lcount;\n\txfs_fileoff_t coff;\n\txfs_fsblock_t cstart;\n\txfs_filblks_t ccount;\n\txfs_fileoff_t noff;\n\txfs_fsblock_t nstart;\n\txfs_filblks_t ncount;\n\txfs_fileoff_t roff;\n\txfs_fsblock_t rstart;\n\txfs_filblks_t rcount;\n\tint delta;\n\tunsigned int state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_estimate_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino1;\n\txfs_ino_t ino2;\n\txfs_fileoff_t startoff1;\n\txfs_fileoff_t startoff2;\n\txfs_filblks_t blockcount;\n\tuint64_t flags;\n\txfs_filblks_t ip1_bcount;\n\txfs_filblks_t ip2_bcount;\n\txfs_filblks_t ip1_rtbcount;\n\txfs_filblks_t ip2_rtbcount;\n\tlong long unsigned int resblks;\n\tlong long unsigned int nr_exchanges;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_intent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino1;\n\txfs_ino_t ino2;\n\tuint64_t flags;\n\txfs_fileoff_t startoff1;\n\txfs_fileoff_t startoff2;\n\txfs_filblks_t blockcount;\n\txfs_fsize_t isize1;\n\txfs_fsize_t isize2;\n\txfs_fsize_t new_isize1;\n\txfs_fsize_t new_isize2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchmaps_overhead {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int bmbt_blocks;\n\tlong long unsigned int rmapbt_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchrange_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ip1_ino;\n\tloff_t ip1_isize;\n\tloff_t ip1_disize;\n\txfs_ino_t ip2_ino;\n\tloff_t ip2_isize;\n\tloff_t ip2_disize;\n\tloff_t file1_offset;\n\tloff_t file2_offset;\n\tlong long unsigned int length;\n\tlong long unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchrange_freshness {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ip2_ino;\n\tlong long int ip2_mtime;\n\tlong long int ip2_ctime;\n\tint ip2_mtime_nsec;\n\tint ip2_ctime_nsec;\n\txfs_ino_t file2_ino;\n\tlong long int file2_mtime;\n\tlong long int file2_ctime;\n\tint file2_mtime_nsec;\n\tint file2_ctime_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_exchrange_inode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint whichfile;\n\txfs_ino_t ino;\n\tint format;\n\txfs_extnum_t nex;\n\tint broot_size;\n\tint fork_off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_extent_busy_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_extent_busy_trim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\txfs_agblock_t tbno;\n\txfs_extlen_t tlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fault_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_file_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsize_t size;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_filestream_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_agnumber_t agno;\n\tint streams;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_filestream_pick {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_agnumber_t agno;\n\tint streams;\n\txfs_extlen_t free;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_force_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint ptag;\n\tint flags;\n\tu32 __data_loc_fname;\n\tint line_num;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_free_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tint resv;\n\tint haveleft;\n\tint haveright;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_free_extent_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_freeblocks_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_free_counter ctr;\n\tuint64_t delta;\n\tuint64_t avail;\n\tuint64_t total;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fs_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int mflags;\n\tlong unsigned int opstate;\n\tlong unsigned int sbflags;\n\tvoid *caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fs_corrupt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fsmap_group_key_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fsmap_linear_key_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_fsblock_t bno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_fsmap_mapping {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t len_daddr;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\txfs_daddr_t block;\n\txfs_daddr_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tuint64_t flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_getparents_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tshort unsigned int iflags;\n\tshort unsigned int oflags;\n\tunsigned int bufsize;\n\tunsigned int hashval;\n\tunsigned int blkno;\n\tunsigned int offset;\n\tint initted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_getparents_rec_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int firstu;\n\tshort unsigned int reclen;\n\tunsigned int bufsize;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_group_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tint refcount;\n\tint active_refcount;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_group_corrupt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\tuint32_t index;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_group_intents_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\tuint32_t index;\n\tlong int nr_intents;\n\tvoid *caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int events;\n\tlong long unsigned int lost_prev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_copybuf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsize_t bufsize;\n\tsize_t inpos;\n\tsize_t outpos;\n\tsize_t to_copy;\n\tsize_t iter_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_create {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 flags;\n\tu8 format;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_event_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int mask;\n\tlong long unsigned int ino;\n\tunsigned int gen;\n\tunsigned int group;\n\tlong long unsigned int offset;\n\tlong long unsigned int length;\n\tlong long unsigned int lostcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_lost_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int lost_prev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_file_ioerror {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tlong long unsigned int ino;\n\tunsigned int gen;\n\tlong long int pos;\n\tlong long unsigned int len;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int old_mask;\n\tunsigned int new_mask;\n\tunsigned int fsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_group {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int old_mask;\n\tunsigned int new_mask;\n\tunsigned int grpmask;\n\tunsigned int group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int type;\n\tunsigned int domain;\n\tunsigned int old_mask;\n\tunsigned int new_mask;\n\tunsigned int imask;\n\tlong long unsigned int ino;\n\tunsigned int gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_media {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int error_dev;\n\tuint64_t daddr;\n\tuint64_t bbcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_healthmon_report_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint32_t shutdown_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_icwalk_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 flags;\n\tuint32_t uid;\n\tuint32_t gid;\n\tprid_t prid;\n\t__u64 min_file_size;\n\tlong int scan_limit;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_imap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tloff_t size;\n\tloff_t offset;\n\tsize_t count;\n\tint whichfork;\n\txfs_fileoff_t startoff;\n\txfs_fsblock_t startblock;\n\txfs_filblks_t blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tlong unsigned int iflags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_corrupt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint error;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_irec_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fileoff_t lblk;\n\txfs_extlen_t len;\n\txfs_fsblock_t pblk;\n\tint state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inode_reload_unlinked_bucket {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inodegc_shrinker_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int nr_to_scan;\n\tvoid *caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_inodegc_worker {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int shrinker_hits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iomap_atomic_write_cow {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_off_t offset;\n\tssize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iomap_invalid_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu64 addr;\n\tloff_t pos;\n\tu64 len;\n\tu64 validity_cookie;\n\tu64 inodeseq;\n\tu16 type;\n\tu16 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iomap_prealloc_size {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsblock_t blocks;\n\tint shift;\n\tunsigned int writeio_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_irec_merge_post {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tuint16_t holemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_irec_merge_pre {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tuint16_t holemask;\n\txfs_agino_t nagino;\n\tuint16_t nholemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iref_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint count;\n\tint pincount;\n\tlong unsigned int iflags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_itrunc_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsize_t size;\n\txfs_fsize_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iunlink_reload_next {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\txfs_agino_t prev_agino;\n\txfs_agino_t next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iunlink_update_bucket {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tunsigned int bucket;\n\txfs_agino_t old_ptr;\n\txfs_agino_t new_ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iunlink_update_dinode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\txfs_agino_t old_ptr;\n\txfs_agino_t new_ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_iwalk_ag_rec {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t startino;\n\tuint64_t freemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_lock_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint lock_flags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_assign_tail_lsn {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_lsn_t new_lsn;\n\txfs_lsn_t old_lsn;\n\txfs_lsn_t head_lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_force {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_lsn_t lsn;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_get_max_trans_res {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint logres;\n\tint logcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tvoid *lip;\n\tuint type;\n\tlong unsigned int flags;\n\txfs_lsn_t lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_daddr_t headblk;\n\txfs_daddr_t tailblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_buf_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint64_t blkno;\n\tshort unsigned int len;\n\tshort unsigned int flags;\n\tshort unsigned int size;\n\tunsigned int map_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_icreate_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tunsigned int count;\n\tunsigned int isize;\n\txfs_agblock_t length;\n\tunsigned int gen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_ino_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tshort unsigned int size;\n\tint fields;\n\tshort unsigned int asize;\n\tshort unsigned int dsize;\n\tint64_t blkno;\n\tint len;\n\tint boffset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_item_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int item;\n\txlog_tid_t tid;\n\txfs_lsn_t lsn;\n\tint type;\n\tint pass;\n\tint count;\n\tint total;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_log_recover_record {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_lsn_t lsn;\n\tint len;\n\tint num_logops;\n\tint pass;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_loggrant_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int tic;\n\tchar ocnt;\n\tchar cnt;\n\tint curr_res;\n\tint unit_res;\n\tunsigned int flags;\n\tint reserveq;\n\tint writeq;\n\tuint64_t grant_reserve_bytes;\n\tuint64_t grant_write_bytes;\n\tuint64_t tail_space;\n\tint curr_cycle;\n\tint curr_block;\n\txfs_lsn_t tail_lsn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metadir_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\txfs_ino_t ino;\n\tint ftype;\n\tint namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metadir_update_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\txfs_ino_t ino;\n\tu32 __data_loc_fname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metadir_update_error_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\txfs_ino_t ino;\n\tint error;\n\tu32 __data_loc_fname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_metafile_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int freeblks;\n\tlong long unsigned int reserved;\n\tlong long unsigned int asked;\n\tlong long unsigned int used;\n\tlong long unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_namespace_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dp_ino;\n\tint namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_perag_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tint refcount;\n\tint active_refcount;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_pwork_init {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int nr_threads;\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tint op;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_double_extent_at_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain i1_domain;\n\txfs_agblock_t i1_startblock;\n\txfs_extlen_t i1_blockcount;\n\txfs_nlink_t i1_refcount;\n\tenum xfs_refc_domain i2_domain;\n\txfs_agblock_t i2_startblock;\n\txfs_extlen_t i2_blockcount;\n\txfs_nlink_t i2_refcount;\n\txfs_agblock_t gbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_double_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain i1_domain;\n\txfs_agblock_t i1_startblock;\n\txfs_extlen_t i1_blockcount;\n\txfs_nlink_t i1_refcount;\n\tenum xfs_refc_domain i2_domain;\n\txfs_agblock_t i2_startblock;\n\txfs_extlen_t i2_blockcount;\n\txfs_nlink_t i2_refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_extent_at_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain domain;\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\txfs_nlink_t refcount;\n\txfs_agblock_t gbno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain domain;\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\txfs_nlink_t refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_lookup {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_lookup_t dir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_refcount_triple_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain i1_domain;\n\txfs_agblock_t i1_startblock;\n\txfs_extlen_t i1_blockcount;\n\txfs_nlink_t i1_refcount;\n\tenum xfs_refc_domain i2_domain;\n\txfs_agblock_t i2_startblock;\n\txfs_extlen_t i2_blockcount;\n\txfs_nlink_t i2_refcount;\n\tenum xfs_refc_domain i3_domain;\n\txfs_agblock_t i3_startblock;\n\txfs_extlen_t i3_blockcount;\n\txfs_nlink_t i3_refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_reflink_remap_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t src_ino;\n\txfs_fileoff_t src_lblk;\n\txfs_filblks_t len;\n\txfs_ino_t dest_ino;\n\txfs_fileoff_t dest_lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t src_dp_ino;\n\txfs_ino_t target_dp_ino;\n\tint src_namelen;\n\tint target_namelen;\n\tu32 __data_loc_src_name;\n\tu32 __data_loc_target_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmap_convert_state {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tint state;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmap_deferred_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long unsigned int owner;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\tint whichfork;\n\txfs_fileoff_t l_loff;\n\txfs_filblks_t l_len;\n\txfs_exntst_t l_state;\n\tint op;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rmapbt_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t gbno;\n\txfs_extlen_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_rtdiscard_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_rtblock_t rtbno;\n\txfs_rtblock_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_simple_io_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tloff_t isize;\n\tloff_t disize;\n\tloff_t offset;\n\tsize_t count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_swap_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint which;\n\txfs_ino_t ino;\n\tint format;\n\txfs_extnum_t nex;\n\tint broot_size;\n\tint fork_off;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_timestamp_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong long int min;\n\tlong long int max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_trans_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint32_t tid;\n\tuint32_t flags;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_trans_mod_dquot {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_dqtype_t type;\n\tunsigned int flags;\n\tunsigned int dqid;\n\tunsigned int field;\n\tint64_t delta;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_trans_resv_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint type;\n\tuint logres;\n\tint logcount;\n\tint logflags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_verify_media {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t fdev;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t end_daddr;\n\tunsigned int flags;\n\txfs_daddr_t daddr;\n\tuint64_t bbcount;\n\tunsigned int bufsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_verify_media_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t fdev;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t end_daddr;\n\tint ioerror;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_verify_media_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t fdev;\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t end_daddr;\n\tunsigned int flags;\n\txfs_daddr_t daddr;\n\tuint64_t bbcount;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfs_wb_invalid_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tu64 addr;\n\tloff_t pos;\n\tu64 len;\n\tu16 type;\n\tu16 flags;\n\tu32 wpcseq;\n\tu32 forkseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xlog_iclog_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint32_t state;\n\tint32_t refcount;\n\tuint32_t offset;\n\tuint32_t flags;\n\tlong long unsigned int lsn;\n\tlong unsigned int caller_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xlog_intent_recovery_failed {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 __data_loc_name;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xmbuf_create {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar pathname[256];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xmbuf_free {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ino;\n\tlong long unsigned int bytes;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_cong_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tbool wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_ping {\n\tstruct trace_entry ent;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_reserve {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_retransmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint ntrans;\n\tint version;\n\tlong unsigned int timeout;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_transmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_writelock_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xreap_bmapi_binval_scan {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_filblks_t len;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t scan_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xreap_ifork_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint whichfork;\n\txfs_fileoff_t fileoff;\n\txfs_filblks_t len;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tint state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_abt_found {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_adoption_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir_ino;\n\txfs_ino_t child_ino;\n\tbool moved;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_bmap_found {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint whichfork;\n\txfs_fileoff_t lblk;\n\txfs_filblks_t len;\n\txfs_fsblock_t pblk;\n\tint state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_calc_ag_resblks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t icount;\n\txfs_agblock_t aglen;\n\txfs_agblock_t freelen;\n\txfs_agblock_t usedlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_calc_ag_resblks_btsize {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t bnobt_sz;\n\txfs_agblock_t inobt_sz;\n\txfs_agblock_t rmapbt_sz;\n\txfs_agblock_t refcbt_sz;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_cow_free_staging {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_cow_mark_file_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsblock_t startblock;\n\txfs_fileoff_t startoff;\n\txfs_filblks_t blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_cow_replace_mapping {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsblock_t startblock;\n\txfs_fileoff_t startoff;\n\txfs_filblks_t blockcount;\n\txfs_exntst_t state;\n\txfs_fsblock_t new_startblock;\n\txfs_extlen_t new_blockcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dentry_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tlong unsigned int ino;\n\tbool positive;\n\tlong unsigned int parent_ino;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dinode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tuint16_t mode;\n\tuint8_t version;\n\tuint8_t format;\n\tuint32_t uid;\n\tuint32_t gid;\n\tuint64_t size;\n\tuint64_t nblocks;\n\tuint32_t extsize;\n\tuint32_t nextents;\n\tuint16_t anextents;\n\tuint8_t forkoff;\n\tuint8_t aformat;\n\tuint16_t flags;\n\tuint32_t gen;\n\tuint64_t flags2;\n\tuint32_t cowextsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dinode_count_rmaps {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_rfsblock_t data_blocks;\n\txfs_rfsblock_t rt_blocks;\n\txfs_rfsblock_t attr_blocks;\n\txfs_extnum_t data_extents;\n\txfs_extnum_t rt_extents;\n\txfs_aextnum_t attr_extents;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dinode_findmode_dirent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t parent_ino;\n\tunsigned int ftype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dinode_findmode_dirent_inval {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t parent_ino;\n\tunsigned int ftype;\n\tunsigned int found_ftype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dir_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir_ino;\n\txfs_ino_t parent_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dir_recover_dirblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir_ino;\n\txfs_dablk_t dabno;\n\tuint32_t magic;\n\tuint32_t magic_guess;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_dirent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir_ino;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\txfs_ino_t ino;\n\tuint8_t ftype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_findroot_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\tuint32_t magic;\n\tuint16_t level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_ibt_found {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t startino;\n\tuint16_t holemask;\n\tuint8_t count;\n\tuint8_t freecount;\n\tuint64_t freemask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_ibt_walk_rmap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_inode_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_fsize_t size;\n\txfs_rfsblock_t nblocks;\n\tuint16_t flags;\n\tuint64_t flags2;\n\tuint32_t nextents;\n\tuint8_t format;\n\tuint32_t anextents;\n\tuint8_t aformat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_add_to_bucket {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tunsigned int bucket;\n\txfs_agino_t agino;\n\txfs_agino_t next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_commit_bucket {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tunsigned int bucket;\n\txfs_agino_t old_agino;\n\txfs_agino_t agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_relink_next {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\txfs_agino_t next_agino;\n\txfs_agino_t new_next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_relink_prev {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\txfs_agino_t prev_agino;\n\txfs_agino_t new_prev_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_reload_next {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\txfs_agino_t old_prev_agino;\n\txfs_agino_t prev_agino;\n\txfs_agino_t next_agino;\n\tunsigned int nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_reload_ondisk {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tunsigned int nlink;\n\txfs_agino_t next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_resolve_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tunsigned int bucket;\n\txfs_agino_t prev_agino;\n\txfs_agino_t next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_visit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agino_t agino;\n\tunsigned int bucket;\n\txfs_agino_t bucket_agino;\n\txfs_agino_t prev_agino;\n\txfs_agino_t next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_iunlink_walk_ondisk_bucket {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tunsigned int bucket;\n\txfs_agino_t prev_agino;\n\txfs_agino_t next_agino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_newbt_extent_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tint64_t owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_nlinks_set_record {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_nlink_t parents;\n\txfs_nlink_t backrefs;\n\txfs_nlink_t children;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_parent_salvage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t dir_ino;\n\txfs_ino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_pptr_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_pptr_salvage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_pptr_scan_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_reap_find_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tbool crosslinked;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_reap_limits_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int log_res;\n\tunsigned int per_binval;\n\tunsigned int max_binval;\n\tunsigned int step_size;\n\tunsigned int per_intent;\n\tunsigned int max_deferred;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_refc_found {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\tenum xfs_refc_domain domain;\n\tenum xfs_group_type type;\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\txfs_nlink_t refcount;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_reset_counters {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tuint64_t icount;\n\tuint64_t ifree;\n\tuint64_t fdblocks;\n\tuint64_t frextents;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_rmap_found {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_rmap_live_update {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tenum xfs_group_type type;\n\txfs_agnumber_t agno;\n\tunsigned int op;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_symlink_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_symlink_salvage_target {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int targetlen;\n\tu32 __data_loc_target;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_tempfile_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tint whichfork;\n\txfs_fileoff_t lblk;\n\txfs_filblks_t len;\n\txfs_fsblock_t pblk;\n\tint state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_tempfile_create {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int type;\n\txfs_agnumber_t agno;\n\txfs_ino_t inum;\n\tunsigned int gen;\n\tunsigned int flags;\n\txfs_ino_t temp_inum;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_xattr_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t src_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_xattr_pptr_scan_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_ino_t parent_ino;\n\tunsigned int parent_gen;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_xattr_recover_leafblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\txfs_dablk_t dabno;\n\tuint16_t magic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xrep_xattr_salvage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\txfs_ino_t ino;\n\tunsigned int flags;\n\tunsigned int namelen;\n\tu32 __data_loc_name;\n\tunsigned int valuelen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_data_ready {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event {\n\tstruct trace_entry ent;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event_done {\n\tstruct trace_entry ent;\n\tint error;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_data {\n\tstruct trace_entry ent;\n\tssize_t err;\n\tsize_t total;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tu32 xid;\n\tlong unsigned int copied;\n\tunsigned int reclen;\n\tunsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n\tint flags;\n};\n\nstruct trace_func_repeats {\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n\tlong unsigned int count;\n\tu64 ts_last_call;\n};\n\nstruct trace_imc_data {\n\t__be64 tb1;\n\t__be64 ip;\n\t__be64 val;\n\t__be64 cpmc1;\n\t__be64 cpmc2;\n\t__be64 cpmc3;\n\t__be64 cpmc4;\n\t__be64 tb2;\n};\n\nstruct trace_kprobe {\n\tstruct dyn_event devent;\n\tstruct kretprobe rp;\n\tlong unsigned int *nhit;\n\tconst char *symbol;\n\tstruct trace_probe tp;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n};\n\nstruct trace_min_max_param {\n\tstruct mutex *lock;\n\tu64 *val;\n\tu64 *min;\n\tu64 *max;\n};\n\nstruct trace_mod_entry {\n\tlong unsigned int mod_addr;\n\tchar mod_name[56];\n};\n\nstruct trace_module_delta {\n\tstruct callback_head rcu;\n\tlong int delta[0];\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nunion upper_chunk;\n\nstruct trace_pid_list {\n\tseqcount_raw_spinlock_t seqcount;\n\traw_spinlock_t lock;\n\tstruct irq_work refill_irqwork;\n\tunion upper_chunk *upper[256];\n\tunion upper_chunk *upper_list;\n\tunion lower_chunk *lower_list;\n\tint free_upper_chunks;\n\tint free_lower_chunks;\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nstruct trace_scratch {\n\tunsigned int clock_id;\n\tlong unsigned int text_addr;\n\tlong unsigned int nr_entries;\n\tstruct trace_mod_entry entries[0];\n};\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct eventfs_inode *ei;\n\tint ref_count;\n\tint nr_events;\n};\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tchar *filename;\n\tstruct uprobe *uprobe;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int *nhits;\n\tstruct trace_probe tp;\n};\n\nstruct trace_user_buf {\n\tchar *buf;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_fs_info {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tunsigned int opts;\n};\n\nstruct tracefs_inode {\n\tstruct inode vfs_inode;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tvoid *private;\n};\n\nstruct tracepoint_ext;\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key_false key;\n\tstruct static_call_key *static_call_key;\n\tvoid *static_call_tramp;\n\tvoid *iterator;\n\tvoid *probestub;\n\tstruct tracepoint_func *funcs;\n\tstruct tracepoint_ext *ext;\n};\n\nstruct tracepoint_ext {\n\tint (*regfunc)(void);\n\tvoid (*unregfunc)(void);\n\tunsigned int faultable: 1;\n};\n\nstruct traceprobe_parse_context {\n\tstruct trace_event_call *event;\n\tconst char *funcname;\n\tconst struct btf_type *proto;\n\tconst struct btf_param *params;\n\ts32 nr_params;\n\tstruct btf *btf;\n\tconst struct btf_type *last_type;\n\tu32 last_bitoffs;\n\tu32 last_bitsize;\n\tstruct trace_probe *tp;\n\tunsigned int flags;\n\tint offset;\n};\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u64, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tstruct tracer_flags *default_flags;\n\tint enabled;\n\tbool print_max;\n\tbool allow_instances;\n\tbool use_max_tr;\n\tbool noboot;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct tracers {\n\tstruct list_head list;\n\tstruct tracer *tracer;\n\tstruct tracer_flags *flags;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar *cmd;\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tdepot_stack_handle_t handle;\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n};\n\ntypedef struct tree_desc_s tree_desc;\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct ts_ops;\n\nstruct ts_state;\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[48];\n};\n\nstruct tsconfig_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n\tstruct {\n\t\tu32 tx_type;\n\t\tu32 rx_filter;\n\t\tu32 flags;\n\t} hwtst_config;\n};\n\nstruct tsconfig_req_info {\n\tstruct ethnl_req_info base;\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct kernel_ethtool_ts_info ts_info;\n\tstruct ethtool_ts_stats stats;\n};\n\nstruct tsinfo_req_info {\n\tstruct ethnl_req_info base;\n\tstruct hwtstamp_provider_desc hwprov_desc;\n};\n\nstruct tso_t {\n\tint next_frag_idx;\n\tint size;\n\tvoid *data;\n\tu16 ip_id;\n\tu8 tlen;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct tsq_work {\n\tstruct work_struct work;\n\tstruct list_head head;\n};\n\nstruct tsync_shared_context {\n\tconst struct cred *old_cred;\n\tconst struct cred *new_cred;\n\tbool set_no_new_privs;\n\tatomic_t preparation_error;\n\tatomic_t num_preparing;\n\tstruct completion all_prepared;\n\tstruct completion ready_to_commit;\n\tatomic_t num_unfinished;\n\tstruct completion all_finished;\n};\n\nstruct tsync_work {\n\tstruct callback_head work;\n\tstruct task_struct *task;\n\tstruct tsync_shared_context *shared_ctx;\n};\n\nstruct tsync_works {\n\tstruct tsync_work **works;\n\tsize_t size;\n\tsize_t capacity;\n};\n\nstruct tty_audit_buf {\n\tstruct mutex mutex;\n\tdev_t dev;\n\tbool icanon;\n\tsize_t valid;\n\tu8 *data;\n};\n\nstruct tty_operations;\n\nstruct tty_driver {\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tenum tty_driver_type type;\n\tenum tty_driver_subtype subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct tty_ldisc_ops;\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_ldisc_ops {\n\tchar *name;\n\tint num;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, u8 *, size_t, void **, long unsigned int);\n\tssize_t (*write)(struct tty_struct *, struct file *, const u8 *, size_t);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, bool);\n\tsize_t (*receive_buf2)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_struct *, const u8 *, const u8 *, size_t);\n\tstruct module *owner;\n};\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tssize_t (*write)(struct tty_struct *, const u8 *, size_t);\n\tint (*put_char)(struct tty_struct *, u8);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tunsigned int (*write_room)(struct tty_struct *);\n\tunsigned int (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, const struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tint (*ldisc_ok)(struct tty_struct *, int);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, u8);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct tty_port_client_operations {\n\tsize_t (*receive_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*lookahead_buf)(struct tty_port *, const u8 *, const u8 *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct tty_port_operations {\n\tbool (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, bool);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_struct {\n\tstruct kref kref;\n\tint index;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tstruct tty_port *port;\n\tconst struct tty_operations *ops;\n\tstruct tty_ldisc *ldisc;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tchar name[64];\n\tlong unsigned int flags;\n\tint count;\n\tunsigned int receive_room;\n\tstruct winsize winsize;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tbool stopped;\n\t\tbool tco_stopped;\n\t} flow;\n\tstruct {\n\t\tstruct pid *pgrp;\n\t\tstruct pid *session;\n\t\tspinlock_t lock;\n\t\tunsigned char pktstatus;\n\t\tbool packet;\n\t} ctrl;\n\tbool hw_stopped;\n\tbool closing;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tint write_cnt;\n\tu8 *write_buf;\n\tstruct list_head tty_files;\n\tstruct work_struct SAK_work;\n};\n\nstruct tun_security_struct {\n\tu32 sid;\n};\n\nstruct tuple_flags {\n\tu_int link_space: 4;\n\tu_int has_link: 1;\n\tu_int mfc_fn: 3;\n\tu_int space: 4;\n};\n\nstruct tuple_t {\n\tu_int Attributes;\n\tcisdata_t DesiredTuple;\n\tu_int Flags;\n\tu_int LinkOffset;\n\tu_int CISOffset;\n\tcisdata_t TupleCode;\n\tcisdata_t TupleLink;\n\tcisdata_t TupleOffset;\n\tcisdata_t TupleDataMax;\n\tcisdata_t TupleDataLen;\n\tcisdata_t *TupleData;\n};\n\nstruct type_datum {\n\tu32 value;\n\tu32 bounds;\n\tunsigned char primary;\n\tunsigned char attribute;\n};\n\nstruct type_set {\n\tstruct ebitmap types;\n\tstruct ebitmap negset;\n\tu32 flags;\n};\n\nstruct typec_connector {\n\tvoid (*attach)(struct typec_connector *, struct device *);\n\tvoid (*deattach)(struct typec_connector *, struct device *);\n};\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_tx_dma)(struct uart_8250_port *);\n\tvoid (*prepare_rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan *rxchan;\n\tstruct dma_chan *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n};\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n\tvoid (*setup_timer)(struct uart_8250_port *);\n};\n\ntypedef struct uart_8250_port *class_serial8250_rpm_t;\n\nstruct mctrl_gpios;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tu16 bugs;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tu16 lsr_saved_flags;\n\tu16 lsr_save_mask;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tu32 (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, u32);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *, bool);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *, bool);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*start_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, const struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\ntypedef struct uart_port *class_uart_port_lock_irq_t;\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct ubuf_info_msgzc {\n\tstruct ubuf_info ubuf;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\tstruct mmpin mmp;\n};\n\nstruct ubuf_info_ops {\n\tvoid (*complete)(struct sk_buff *, struct ubuf_info *, bool);\n\tint (*link_skb)(struct sk_buff *, struct ubuf_info *);\n};\n\nstruct ucounts {\n\tstruct hlist_nulls_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tstruct callback_head rcu;\n\trcuref_t count;\n\tatomic_long_t ucount[10];\n\tatomic_long_t rlimit[4];\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct ucs_interval16 {\n\tu16 first;\n\tu16 last;\n};\n\nstruct ucs_interval32 {\n\tu32 first;\n\tu32 last;\n};\n\nstruct ucs_page_desc {\n\tu8 page;\n\tu8 count;\n\tu16 start;\n};\n\nstruct ucs_page_entry {\n\tu8 offset;\n\tu8 fallback;\n};\n\nstruct ucs_recomposition {\n\tu16 base;\n\tu16 mark;\n\tu16 recomposed;\n};\n\nstruct udp_prod_queue;\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tlong unsigned int udp_flags;\n\tint pending;\n\t__u8 encap_type;\n\t__u16 udp_lrpa_hash;\n\tstruct hlist_nulls_node udp_lrpa_node;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*encap_err_rcv)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct udp_prod_queue *udp_prod_queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tint forward_threshold;\n\tbool peeking_with_offset;\n\tstruct hlist_node tunnel_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct numa_drop_counters drop_counters;\n};\n\nstruct udp6_sock {\n\tstruct udp_sock udp;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n\tu16 len;\n\tbool is_linear;\n\tbool csum_unnecessary;\n};\n\nstruct udp_hslot {\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct udp_hslot_main {\n\tstruct udp_hslot hslot;\n\tu32 hash4_cnt;\n\tlong: 64;\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[10];\n};\n\nstruct udp_prod_queue {\n\tstruct llist_head ll_root;\n\tatomic_t rmem_alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot_main *hash2;\n\tstruct udp_hslot *hash4;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n\tu8 hw_priv;\n};\n\nstruct udp_tunnel_nic_table_info {\n\tunsigned int n_entries;\n\tunsigned int tunnel_types;\n};\n\nstruct udp_tunnel_nic_shared;\n\nstruct udp_tunnel_nic_info {\n\tint (*set_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*unset_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tint (*sync_table)(struct net_device *, unsigned int);\n\tstruct udp_tunnel_nic_shared *shared;\n\tunsigned int flags;\n\tstruct udp_tunnel_nic_table_info tables[4];\n};\n\nstruct udp_tunnel_nic_ops {\n\tvoid (*get_port)(struct net_device *, unsigned int, unsigned int, struct udp_tunnel_info *);\n\tvoid (*set_port_priv)(struct net_device *, unsigned int, unsigned int, u8);\n\tvoid (*add_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*del_port)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*reset_ntf)(struct net_device *);\n\tsize_t (*dump_size)(struct net_device *, unsigned int);\n\tint (*dump_write)(struct net_device *, unsigned int, struct sk_buff *);\n\tvoid (*assert_locked)(struct net_device *);\n\tvoid (*lock)(struct net_device *);\n\tvoid (*unlock)(struct net_device *);\n};\n\nstruct udp_tunnel_nic_shared {\n\tstruct udp_tunnel_nic *udp_tunnel_nic_info;\n\tstruct list_head devices;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nstruct uf_node {\n\tstruct uf_node *parent;\n\tunsigned int rank;\n};\n\nstruct umem_info {\n\t__be64 *buf;\n\tu32 size;\n\tu32 max_entries;\n\tu32 idx;\n\tunsigned int nr_ranges;\n\tconst struct range *ranges;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct uncharge_gather {\n\tstruct mem_cgroup *memcg;\n\tlong unsigned int nr_memory;\n\tlong unsigned int pgpgout;\n\tlong unsigned int nr_kmem;\n\tint nid;\n};\n\nstruct uni_pagedict {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\nstruct unipair;\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tstruct sockaddr_un name[0];\n};\n\nstruct unix_domain {\n\tstruct auth_domain h;\n};\n\nstruct unix_edge {\n\tstruct unix_sock *predecessor;\n\tstruct unix_sock *successor;\n\tstruct list_head vertex_entry;\n\tstruct list_head stack_entry;\n};\n\nstruct unix_gid {\n\tstruct cache_head h;\n\tkuid_t uid;\n\tstruct group_info *gi;\n\tstruct callback_head rcu;\n};\n\nstruct unix_peercred {\n\tstruct pid *peer_pid;\n\tconst struct cred *peer_cred;\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 secid;\n\tu32 consumed;\n};\n\nstruct unix_vertex;\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct sock *listener;\n\tstruct unix_vertex *vertex;\n\tspinlock_t lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tint inq_len;\n\tbool recvmsg_inq;\n\tstruct sk_buff *oob_skb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nstruct unix_vertex {\n\tstruct list_head edges;\n\tstruct list_head entry;\n\tstruct list_head scc_entry;\n\tlong unsigned int out_degree;\n\tlong unsigned int index;\n\tlong unsigned int scc_index;\n};\n\nstruct unlink_vma_file_batch {\n\tint count;\n\tstruct vm_area_struct *vmas[8];\n};\n\nstruct unmap_desc {\n\tstruct ma_state *mas;\n\tstruct vm_area_struct *first;\n\tlong unsigned int pg_start;\n\tlong unsigned int pg_end;\n\tlong unsigned int vma_start;\n\tlong unsigned int vma_end;\n\tlong unsigned int tree_end;\n\tlong unsigned int tree_reset;\n\tbool mm_wr_locked;\n};\n\nstruct unwind_stacktrace {\n\tunsigned int nr;\n\tlong unsigned int *entries;\n};\n\nstruct unwind_work;\n\ntypedef void (*unwind_callback_t)(struct unwind_work *, struct unwind_stacktrace *, u64);\n\nstruct unwind_work {\n\tstruct list_head list;\n\tunwind_callback_t func;\n\tint bit;\n};\n\nstruct update_flash_t {\n\tint status;\n};\n\nstruct update_props_workarea {\n\t__be32 phandle;\n\t__be32 state;\n\t__be64 reserved;\n\t__be32 nprops;\n} __attribute__((packed));\n\nunion upper_chunk {\n\tunion upper_chunk *next;\n\tunion lower_chunk *data[256];\n};\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct list_head consumers;\n\tstruct inode *inode;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct work;\n\t};\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n\tint dsize;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunsigned int depth;\n\tstruct return_instance *return_instances;\n\tstruct return_instance *ri_pool;\n\tstruct timer_list ri_timer;\n\tseqcount_t ri_seqcount;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tbool signal_denied;\n\tstruct arch_uprobe *auprobe;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\ntypedef void (*usb_complete_t)(struct urb *);\n\nstruct usb_iso_packet_descriptor {\n\tunsigned int offset;\n\tunsigned int length;\n\tunsigned int actual_length;\n\tint status;\n};\n\nstruct usb_anchor;\n\nstruct urb {\n\tstruct kref kref;\n\tint unlinked;\n\tvoid *hcpriv;\n\tatomic_t use_count;\n\tatomic_t reject;\n\tstruct list_head urb_list;\n\tstruct list_head anchor_list;\n\tstruct usb_anchor *anchor;\n\tstruct usb_device *dev;\n\tstruct usb_host_endpoint *ep;\n\tunsigned int pipe;\n\tunsigned int stream_id;\n\tint status;\n\tunsigned int transfer_flags;\n\tvoid *transfer_buffer;\n\tdma_addr_t transfer_dma;\n\tstruct scatterlist *sg;\n\tstruct sg_table *sgt;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tu32 transfer_buffer_length;\n\tu32 actual_length;\n\tunsigned char *setup_packet;\n\tdma_addr_t setup_dma;\n\tint start_frame;\n\tint number_of_packets;\n\tint interval;\n\tint error_count;\n\tvoid *context;\n\tusb_complete_t complete;\n\tstruct usb_iso_packet_descriptor iso_frame_desc[0];\n};\n\nstruct urb_priv {\n\tstruct ed *ed;\n\tu16 length;\n\tu16 td_cnt;\n\tstruct list_head pending;\n\tstruct td *td[0];\n};\n\ntypedef struct urb_priv urb_priv_t;\n\nstruct usage_priority {\n\t__u32 usage;\n\tbool global;\n\tunsigned int slot_overwrite;\n};\n\nstruct usb2_lpm_parameters {\n\tunsigned int besl;\n\tint timeout;\n};\n\nstruct usb3_lpm_parameters {\n\tunsigned int mel;\n\tunsigned int pel;\n\tunsigned int sel;\n\tint timeout;\n};\n\nstruct usb_anchor {\n\tstruct list_head urb_list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tatomic_t suspend_wakeups;\n\tunsigned int poisoned: 1;\n};\n\nstruct usb_bos_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumDeviceCaps;\n} __attribute__((packed));\n\nstruct mon_bus;\n\nstruct usb_bus {\n\tstruct device *controller;\n\tstruct device *sysdev;\n\tint busnum;\n\tconst char *bus_name;\n\tu8 uses_pio_for_control;\n\tu8 otg_port;\n\tunsigned int is_b_host: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int no_stop_on_short: 1;\n\tunsigned int no_sg_constraint: 1;\n\tunsigned int sg_tablesize;\n\tint devnum_next;\n\tstruct mutex devnum_next_mutex;\n\tlong unsigned int devmap[2];\n\tstruct usb_device *root_hub;\n\tstruct usb_bus *hs_companion;\n\tint bandwidth_allocated;\n\tint bandwidth_int_reqs;\n\tint bandwidth_isoc_reqs;\n\tunsigned int resuming_ports;\n\tstruct mon_bus *mon_bus;\n\tint monitored;\n};\n\nstruct usb_cdc_acm_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n};\n\nstruct usb_cdc_call_mgmt_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n\t__u8 bDataInterface;\n};\n\nstruct usb_cdc_country_functional_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iCountryCodeRelDate;\n\tunion {\n\t\t__le16 wCountryCode0;\n\t\tstruct {\n\t\t\tstruct {} __empty_wCountryCodes;\n\t\t\t__le16 wCountryCodes[0];\n\t\t};\n\t};\n};\n\nstruct usb_cdc_dmm_desc {\n\t__u8 bFunctionLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubtype;\n\t__u16 bcdVersion;\n\t__le16 wMaxCommand;\n} __attribute__((packed));\n\nstruct usb_cdc_ether_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iMACAddress;\n\t__le32 bmEthernetStatistics;\n\t__le16 wMaxSegmentSize;\n\t__le16 wNumberMCFilters;\n\t__u8 bNumberPowerFilters;\n} __attribute__((packed));\n\nstruct usb_cdc_header_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdCDC;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMVersion;\n\t__le16 wMaxControlMessage;\n\t__u8 bNumberFilters;\n\t__u8 bMaxFilterSize;\n\t__le16 wMaxSegmentSize;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_extended_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMExtendedVersion;\n\t__u8 bMaxOutstandingCommandMessages;\n\t__le16 wMTU;\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n\t__u8 bGUID[16];\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_detail_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bGuidDescriptorType;\n\t__u8 bDetailData[0];\n};\n\nstruct usb_cdc_ncm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdNcmVersion;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_network_terminal_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bEntityId;\n\t__u8 iName;\n\t__u8 bChannelIndex;\n\t__u8 bPhysicalInterface;\n};\n\nstruct usb_cdc_obex_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n} __attribute__((packed));\n\nstruct usb_cdc_union_desc;\n\nstruct usb_cdc_parsed_header {\n\tstruct usb_cdc_union_desc *usb_cdc_union_desc;\n\tstruct usb_cdc_header_desc *usb_cdc_header_desc;\n\tstruct usb_cdc_call_mgmt_descriptor *usb_cdc_call_mgmt_descriptor;\n\tstruct usb_cdc_acm_descriptor *usb_cdc_acm_descriptor;\n\tstruct usb_cdc_country_functional_desc *usb_cdc_country_functional_desc;\n\tstruct usb_cdc_network_terminal_desc *usb_cdc_network_terminal_desc;\n\tstruct usb_cdc_ether_desc *usb_cdc_ether_desc;\n\tstruct usb_cdc_dmm_desc *usb_cdc_dmm_desc;\n\tstruct usb_cdc_mdlm_desc *usb_cdc_mdlm_desc;\n\tstruct usb_cdc_mdlm_detail_desc *usb_cdc_mdlm_detail_desc;\n\tstruct usb_cdc_obex_desc *usb_cdc_obex_desc;\n\tstruct usb_cdc_ncm_desc *usb_cdc_ncm_desc;\n\tstruct usb_cdc_mbim_desc *usb_cdc_mbim_desc;\n\tstruct usb_cdc_mbim_extended_desc *usb_cdc_mbim_extended_desc;\n\tbool phonet_magic_present;\n};\n\nstruct usb_cdc_union_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bMasterInterface0;\n\tunion {\n\t\t__u8 bSlaveInterface0;\n\t\tstruct {\n\t\t\tstruct {} __empty_bSlaveInterfaces;\n\t\t\t__u8 bSlaveInterfaces[0];\n\t\t};\n\t};\n};\n\nstruct usb_charger_current {\n\tunsigned int sdp_min;\n\tunsigned int sdp_max;\n\tunsigned int dcp_min;\n\tunsigned int dcp_max;\n\tunsigned int cdp_min;\n\tunsigned int cdp_max;\n\tunsigned int aca_min;\n\tunsigned int aca_max;\n};\n\nstruct usb_class_driver {\n\tchar *name;\n\tchar * (*devnode)(const struct device *, umode_t *);\n\tconst struct file_operations *fops;\n\tint minor_base;\n};\n\nstruct usb_config_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumInterfaces;\n\t__u8 bConfigurationValue;\n\t__u8 iConfiguration;\n\t__u8 bmAttributes;\n\t__u8 bMaxPower;\n} __attribute__((packed));\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nstruct usb_descriptor_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n};\n\nstruct usb_dev_cap_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_dev_state {\n\tstruct list_head list;\n\tstruct usb_device *dev;\n\tstruct file *file;\n\tspinlock_t lock;\n\tstruct list_head async_pending;\n\tstruct list_head async_completed;\n\tstruct list_head memory_list;\n\twait_queue_head_t wait;\n\twait_queue_head_t wait_for_resume;\n\tunsigned int discsignr;\n\tstruct pid *disc_pid;\n\tconst struct cred *cred;\n\tsigval_t disccontext;\n\tlong unsigned int ifclaimed;\n\tu32 disabled_bulk_eps;\n\tlong unsigned int interface_allowed_mask;\n\tint not_yet_resumed;\n\tbool suspend_allowed;\n\tbool privileges_dropped;\n};\n\nstruct usb_endpoint_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bEndpointAddress;\n\t__u8 bmAttributes;\n\t__le16 wMaxPacketSize;\n\t__u8 bInterval;\n\t__u8 bRefresh;\n\t__u8 bSynchAddress;\n} __attribute__((packed));\n\nstruct usb_ss_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bMaxBurst;\n\t__u8 bmAttributes;\n\t__le16 wBytesPerInterval;\n};\n\nstruct usb_ssp_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wReseved;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_eusb2_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wMaxPacketSize;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_host_endpoint {\n\tstruct usb_endpoint_descriptor desc;\n\tstruct usb_ss_ep_comp_descriptor ss_ep_comp;\n\tstruct usb_ssp_isoc_ep_comp_descriptor ssp_isoc_ep_comp;\n\tstruct usb_eusb2_isoc_ep_comp_descriptor eusb2_isoc_ep_comp;\n\tlong: 0;\n\tstruct list_head urb_list;\n\tvoid *hcpriv;\n\tstruct ep_device *ep_dev;\n\tunsigned char *extra;\n\tint extralen;\n\tint enabled;\n\tint streams;\n\tlong: 0;\n} __attribute__((packed));\n\nstruct usb_device_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__le16 idVendor;\n\t__le16 idProduct;\n\t__le16 bcdDevice;\n\t__u8 iManufacturer;\n\t__u8 iProduct;\n\t__u8 iSerialNumber;\n\t__u8 bNumConfigurations;\n};\n\nstruct usb_host_bos;\n\nstruct usb_host_config;\n\nstruct usb_device {\n\tint devnum;\n\tchar devpath[16];\n\tu32 route;\n\tenum usb_device_state state;\n\tenum usb_device_speed speed;\n\tunsigned int rx_lanes;\n\tunsigned int tx_lanes;\n\tenum usb_ssp_rate ssp_rate;\n\tstruct usb_tt *tt;\n\tint ttport;\n\tunsigned int toggle[2];\n\tstruct usb_device *parent;\n\tstruct usb_bus *bus;\n\tstruct usb_host_endpoint ep0;\n\tstruct device dev;\n\tstruct usb_device_descriptor descriptor;\n\tstruct usb_host_bos *bos;\n\tstruct usb_host_config *config;\n\tstruct usb_host_config *actconfig;\n\tstruct usb_host_endpoint *ep_in[16];\n\tstruct usb_host_endpoint *ep_out[16];\n\tchar **rawdescriptors;\n\tshort unsigned int bus_mA;\n\tu8 portnum;\n\tu8 level;\n\tu8 devaddr;\n\tunsigned int can_submit: 1;\n\tunsigned int persist_enabled: 1;\n\tunsigned int reset_in_progress: 1;\n\tunsigned int have_langid: 1;\n\tunsigned int authorized: 1;\n\tunsigned int authenticated: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int lpm_devinit_allow: 1;\n\tunsigned int usb2_hw_lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_besl_capable: 1;\n\tunsigned int usb2_hw_lpm_enabled: 1;\n\tunsigned int usb2_hw_lpm_allowed: 1;\n\tunsigned int usb3_lpm_u1_enabled: 1;\n\tunsigned int usb3_lpm_u2_enabled: 1;\n\tint string_langid;\n\tchar *product;\n\tchar *manufacturer;\n\tchar *serial;\n\tstruct list_head filelist;\n\tint maxchild;\n\tu32 quirks;\n\tatomic_t urbnum;\n\tlong unsigned int active_duration;\n\tlong unsigned int connect_time;\n\tunsigned int do_remote_wakeup: 1;\n\tunsigned int reset_resume: 1;\n\tunsigned int port_is_suspended: 1;\n\tunsigned int offload_at_suspend: 1;\n\tint offload_usage;\n\tenum usb_link_tunnel_mode tunnel_mode;\n\tstruct device_link *usb4_link;\n\tint slot_id;\n\tstruct usb2_lpm_parameters l1_params;\n\tstruct usb3_lpm_parameters u1_params;\n\tstruct usb3_lpm_parameters u2_params;\n\tunsigned int lpm_disable_count;\n\tu16 hub_delay;\n\tunsigned int use_generic_driver: 1;\n};\n\nstruct usb_device_id;\n\nstruct usb_device_driver {\n\tconst char *name;\n\tbool (*match)(struct usb_device *);\n\tint (*probe)(struct usb_device *);\n\tvoid (*disconnect)(struct usb_device *);\n\tint (*suspend)(struct usb_device *, pm_message_t);\n\tint (*resume)(struct usb_device *, pm_message_t);\n\tint (*choose_configuration)(struct usb_device *);\n\tconst struct attribute_group **dev_groups;\n\tstruct device_driver driver;\n\tconst struct usb_device_id *id_table;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int generic_subclass: 1;\n};\n\nstruct usb_device_id {\n\t__u16 match_flags;\n\t__u16 idVendor;\n\t__u16 idProduct;\n\t__u16 bcdDevice_lo;\n\t__u16 bcdDevice_hi;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 bInterfaceNumber;\n\tkernel_ulong_t driver_info;\n};\n\nstruct usb_dynids {\n\tstruct list_head list;\n};\n\nstruct usb_interface;\n\nstruct usb_driver {\n\tconst char *name;\n\tint (*probe)(struct usb_interface *, const struct usb_device_id *);\n\tvoid (*disconnect)(struct usb_interface *);\n\tint (*unlocked_ioctl)(struct usb_interface *, unsigned int, void *);\n\tint (*suspend)(struct usb_interface *, pm_message_t);\n\tint (*resume)(struct usb_interface *);\n\tint (*reset_resume)(struct usb_interface *);\n\tint (*pre_reset)(struct usb_interface *);\n\tint (*post_reset)(struct usb_interface *);\n\tvoid (*shutdown)(struct usb_interface *);\n\tconst struct usb_device_id *id_table;\n\tconst struct attribute_group **dev_groups;\n\tstruct usb_dynids dynids;\n\tstruct device_driver driver;\n\tunsigned int no_dynamic_id: 1;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int disable_hub_initiated_lpm: 1;\n\tunsigned int soft_unbind: 1;\n};\n\nstruct usb_dynid {\n\tstruct list_head node;\n\tstruct usb_device_id id;\n};\n\nstruct usb_ext_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__le32 bmAttributes;\n} __attribute__((packed));\n\nstruct usb_phy;\n\nstruct usb_phy_roothub;\n\nstruct usb_hcd {\n\tstruct usb_bus self;\n\tstruct kref kref;\n\tconst char *product_desc;\n\tint speed;\n\tchar irq_descr[24];\n\tstruct timer_list rh_timer;\n\tstruct urb *status_urb;\n\tstruct work_struct wakeup_work;\n\tstruct work_struct died_work;\n\tconst struct hc_driver *driver;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_phy_roothub *phy_roothub;\n\tlong unsigned int flags;\n\tenum usb_dev_authorize_policy dev_policy;\n\tunsigned int rh_registered: 1;\n\tunsigned int rh_pollable: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int msi_enabled: 1;\n\tunsigned int skip_phy_initialization: 1;\n\tunsigned int uses_new_polling: 1;\n\tunsigned int has_tt: 1;\n\tunsigned int amd_resume_bug: 1;\n\tunsigned int can_do_streams: 1;\n\tunsigned int tpl_support: 1;\n\tunsigned int cant_recv_wakeups: 1;\n\tunsigned int irq;\n\tvoid *regs;\n\tresource_size_t rsrc_start;\n\tresource_size_t rsrc_len;\n\tunsigned int power_budget;\n\tstruct giveback_urb_bh high_prio_bh;\n\tstruct giveback_urb_bh low_prio_bh;\n\tstruct mutex *address0_mutex;\n\tstruct mutex *bandwidth_mutex;\n\tstruct usb_hcd *shared_hcd;\n\tstruct usb_hcd *primary_hcd;\n\tstruct dma_pool *pool[4];\n\tint state;\n\tstruct gen_pool *localmem_pool;\n\tlong unsigned int hcd_priv[0];\n};\n\nstruct usb_ss_cap_descriptor;\n\nstruct usb_ssp_cap_descriptor;\n\nstruct usb_ss_container_id_descriptor;\n\nstruct usb_ptm_cap_descriptor;\n\nstruct usb_host_bos {\n\tstruct usb_bos_descriptor *desc;\n\tstruct usb_ext_cap_descriptor *ext_cap;\n\tstruct usb_ss_cap_descriptor *ss_cap;\n\tstruct usb_ssp_cap_descriptor *ssp_cap;\n\tstruct usb_ss_container_id_descriptor *ss_id;\n\tstruct usb_ptm_cap_descriptor *ptm_cap;\n};\n\nstruct usb_interface_assoc_descriptor;\n\nstruct usb_interface_cache;\n\nstruct usb_host_config {\n\tstruct usb_config_descriptor desc;\n\tchar *string;\n\tstruct usb_interface_assoc_descriptor *intf_assoc[16];\n\tstruct usb_interface *interface[32];\n\tstruct usb_interface_cache *intf_cache[32];\n\tunsigned char *extra;\n\tint extralen;\n};\n\nstruct usb_interface_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bInterfaceNumber;\n\t__u8 bAlternateSetting;\n\t__u8 bNumEndpoints;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 iInterface;\n};\n\nstruct usb_host_interface {\n\tstruct usb_interface_descriptor desc;\n\tint extralen;\n\tunsigned char *extra;\n\tstruct usb_host_endpoint *endpoint;\n\tchar *string;\n};\n\nstruct usb_hub_status {\n\t__le16 wHubStatus;\n\t__le16 wHubChange;\n};\n\nstruct usb_port_status {\n\t__le16 wPortStatus;\n\t__le16 wPortChange;\n\t__le32 dwExtPortStatus;\n};\n\nstruct usb_tt {\n\tstruct usb_device *hub;\n\tint multi;\n\tunsigned int think_time;\n\tvoid *hcpriv;\n\tspinlock_t lock;\n\tstruct list_head clear_list;\n\tstruct work_struct clear_work;\n};\n\nstruct usb_hub_descriptor;\n\nstruct usb_port;\n\nstruct usb_hub {\n\tstruct device *intfdev;\n\tstruct usb_device *hdev;\n\tstruct kref kref;\n\tstruct urb *urb;\n\tu8 (*buffer)[8];\n\tunion {\n\t\tstruct usb_hub_status hub;\n\t\tstruct usb_port_status port;\n\t} *status;\n\tstruct mutex status_mutex;\n\tint error;\n\tint nerrors;\n\tlong unsigned int event_bits[1];\n\tlong unsigned int change_bits[1];\n\tlong unsigned int removed_bits[1];\n\tlong unsigned int wakeup_bits[1];\n\tlong unsigned int power_bits[1];\n\tlong unsigned int child_usage_bits[1];\n\tlong unsigned int warm_reset_bits[1];\n\tstruct usb_hub_descriptor *descriptor;\n\tstruct usb_tt tt;\n\tunsigned int mA_per_port;\n\tunsigned int wakeup_enabled_descendants;\n\tunsigned int limited_power: 1;\n\tunsigned int quiescing: 1;\n\tunsigned int disconnected: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int quirk_disable_autosuspend: 1;\n\tunsigned int quirk_check_port_auto_suspend: 1;\n\tunsigned int has_indicators: 1;\n\tu8 indicator[31];\n\tstruct delayed_work leds;\n\tstruct delayed_work init_work;\n\tstruct delayed_work post_resume_work;\n\tstruct work_struct events;\n\tspinlock_t irq_urb_lock;\n\tstruct timer_list irq_urb_retry;\n\tstruct usb_port **ports;\n\tstruct list_head onboard_devs;\n};\n\nstruct usb_hub_descriptor {\n\t__u8 bDescLength;\n\t__u8 bDescriptorType;\n\t__u8 bNbrPorts;\n\t__le16 wHubCharacteristics;\n\t__u8 bPwrOn2PwrGood;\n\t__u8 bHubContrCurrent;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 DeviceRemovable[4];\n\t\t\t__u8 PortPwrCtrlMask[4];\n\t\t} hs;\n\t\tstruct {\n\t\t\t__u8 bHubHdrDecLat;\n\t\t\t__le16 wHubDelay;\n\t\t\t__le16 DeviceRemovable;\n\t\t} __attribute__((packed)) ss;\n\t} u;\n} __attribute__((packed));\n\nstruct usb_interface {\n\tstruct usb_host_interface *altsetting;\n\tstruct usb_host_interface *cur_altsetting;\n\tunsigned int num_altsetting;\n\tstruct usb_interface_assoc_descriptor *intf_assoc;\n\tint minor;\n\tenum usb_interface_condition condition;\n\tunsigned int sysfs_files_created: 1;\n\tunsigned int ep_devs_created: 1;\n\tunsigned int unregistering: 1;\n\tunsigned int needs_remote_wakeup: 1;\n\tunsigned int needs_altsetting0: 1;\n\tunsigned int needs_binding: 1;\n\tunsigned int resetting_device: 1;\n\tunsigned int authorized: 1;\n\tenum usb_wireless_status wireless_status;\n\tstruct work_struct wireless_status_work;\n\tstruct device dev;\n\tstruct device *usb_dev;\n\tstruct work_struct reset_ws;\n};\n\nstruct usb_interface_assoc_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bFirstInterface;\n\t__u8 bInterfaceCount;\n\t__u8 bFunctionClass;\n\t__u8 bFunctionSubClass;\n\t__u8 bFunctionProtocol;\n\t__u8 iFunction;\n};\n\nstruct usb_interface_cache {\n\tunsigned int num_altsetting;\n\tstruct kref ref;\n\tstruct usb_host_interface altsetting[0];\n};\n\nstruct usb_memory {\n\tstruct list_head memlist;\n\tint vma_use_count;\n\tint urb_use_count;\n\tu32 size;\n\tvoid *mem;\n\tdma_addr_t dma_handle;\n\tlong unsigned int vm_start;\n\tstruct usb_dev_state *ps;\n};\n\nstruct usb_mon_operations {\n\tvoid (*urb_submit)(struct usb_bus *, struct urb *);\n\tvoid (*urb_submit_error)(struct usb_bus *, struct urb *, int);\n\tvoid (*urb_complete)(struct usb_bus *, struct urb *, int);\n};\n\nstruct usb_gadget;\n\nstruct usb_otg {\n\tu8 default_a;\n\tstruct phy___2 *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_bus *host;\n\tstruct usb_gadget *gadget;\n\tenum usb_otg_state state;\n\tint (*set_host)(struct usb_otg *, struct usb_bus *);\n\tint (*set_peripheral)(struct usb_otg *, struct usb_gadget *);\n\tint (*set_vbus)(struct usb_otg *, bool);\n\tint (*start_srp)(struct usb_otg *);\n\tint (*start_hnp)(struct usb_otg *);\n};\n\nstruct usb_otg_caps {\n\tu16 otg_rev;\n\tbool hnp_support;\n\tbool srp_support;\n\tbool adp_support;\n};\n\nstruct extcon_dev;\n\nstruct usb_phy_io_ops;\n\nstruct usb_phy {\n\tstruct device *dev;\n\tconst char *label;\n\tunsigned int flags;\n\tenum usb_phy_type type;\n\tenum usb_phy_events last_event;\n\tstruct usb_otg *otg;\n\tstruct device *io_dev;\n\tstruct usb_phy_io_ops *io_ops;\n\tvoid *io_priv;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *id_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct notifier_block type_nb;\n\tenum usb_charger_type chg_type;\n\tenum usb_charger_state chg_state;\n\tstruct usb_charger_current chg_cur;\n\tstruct work_struct chg_work;\n\tstruct atomic_notifier_head notifier;\n\tu16 port_status;\n\tu16 port_change;\n\tstruct list_head head;\n\tint (*init)(struct usb_phy *);\n\tvoid (*shutdown)(struct usb_phy *);\n\tint (*set_vbus)(struct usb_phy *, int);\n\tint (*set_power)(struct usb_phy *, unsigned int);\n\tint (*set_suspend)(struct usb_phy *, int);\n\tint (*set_wakeup)(struct usb_phy *, bool);\n\tint (*notify_connect)(struct usb_phy *, enum usb_device_speed);\n\tint (*notify_disconnect)(struct usb_phy *, enum usb_device_speed);\n\tenum usb_charger_type (*charger_detect)(struct usb_phy *);\n};\n\nstruct usb_phy_io_ops {\n\tint (*read)(struct usb_phy *, u32);\n\tint (*write)(struct usb_phy *, u32, u32);\n};\n\nstruct usb_phy_roothub {\n\tstruct phy___2 *phy;\n\tstruct list_head list;\n};\n\nstruct usb_port {\n\tstruct usb_device *child;\n\tstruct device dev;\n\tstruct usb_dev_state *port_owner;\n\tstruct usb_port *peer;\n\tstruct typec_connector *connector;\n\tstruct dev_pm_qos_request *req;\n\tenum usb_port_connect_type connect_type;\n\tenum usb_device_state state;\n\tstruct kernfs_node *state_kn;\n\tusb_port_location_t location;\n\tstruct mutex status_lock;\n\tu32 over_current_count;\n\tu8 portnum;\n\tu32 quirks;\n\tunsigned int early_stop: 1;\n\tunsigned int ignore_event: 1;\n\tunsigned int is_superspeed: 1;\n\tunsigned int usb3_lpm_u1_permit: 1;\n\tunsigned int usb3_lpm_u2_permit: 1;\n};\n\nstruct usb_ptm_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_qualifier_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__u8 bNumConfigurations;\n\t__u8 bRESERVED;\n};\n\nstruct usb_set_sel_req {\n\t__u8 u1_sel;\n\t__u8 u1_pel;\n\t__le16 u2_sel;\n\t__le16 u2_pel;\n};\n\nstruct usb_sg_request {\n\tint status;\n\tsize_t bytes;\n\tspinlock_t lock;\n\tstruct usb_device *dev;\n\tint pipe;\n\tint entries;\n\tstruct urb **urbs;\n\tint count;\n\tstruct completion complete;\n};\n\nstruct usb_ss_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bmAttributes;\n\t__le16 wSpeedSupported;\n\t__u8 bFunctionalitySupport;\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n};\n\nstruct usb_ss_container_id_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__u8 ContainerID[16];\n};\n\nstruct usb_ssp_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__le32 bmAttributes;\n\t__le16 wFunctionalitySupport;\n\t__le16 wReserved;\n\tunion {\n\t\t__le32 legacy_padding;\n\t\tstruct {\n\t\t\tstruct {} __empty_bmSublinkSpeedAttr;\n\t\t\t__le32 bmSublinkSpeedAttr[0];\n\t\t};\n\t};\n};\n\nstruct usb_tt_clear {\n\tstruct list_head clear_list;\n\tunsigned int tt;\n\tu16 devinfo;\n\tstruct usb_hcd *hcd;\n\tstruct usb_host_endpoint *ep;\n};\n\nstruct usbdevfs_bulktransfer {\n\tunsigned int ep;\n\tunsigned int len;\n\tunsigned int timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_connectinfo {\n\tunsigned int devnum;\n\tunsigned char slow;\n};\n\nstruct usbdevfs_conninfo_ex {\n\t__u32 size;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 speed;\n\t__u8 num_ports;\n\t__u8 ports[7];\n};\n\nstruct usbdevfs_ctrltransfer {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\t__u32 timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_disconnect_claim {\n\tunsigned int interface;\n\tunsigned int flags;\n\tchar driver[256];\n};\n\nstruct usbdevfs_disconnectsignal {\n\tunsigned int signr;\n\tvoid *context;\n};\n\nstruct usbdevfs_getdriver {\n\tunsigned int interface;\n\tchar driver[256];\n};\n\nstruct usbdevfs_hub_portinfo {\n\tchar nports;\n\tchar port[127];\n};\n\nstruct usbdevfs_ioctl {\n\tint ifno;\n\tint ioctl_code;\n\tvoid *data;\n};\n\nstruct usbdevfs_iso_packet_desc {\n\tunsigned int length;\n\tunsigned int actual_length;\n\tunsigned int status;\n};\n\nstruct usbdevfs_setinterface {\n\tunsigned int interface;\n\tunsigned int altsetting;\n};\n\nstruct usbdevfs_streams {\n\tunsigned int num_streams;\n\tunsigned int num_eps;\n\tunsigned char eps[0];\n};\n\nstruct usbdevfs_urb {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tint status;\n\tunsigned int flags;\n\tvoid *buffer;\n\tint buffer_length;\n\tint actual_length;\n\tint start_frame;\n\tunion {\n\t\tint number_of_packets;\n\t\tunsigned int stream_id;\n\t};\n\tint error_count;\n\tunsigned int signr;\n\tvoid *usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbhid_device {\n\tstruct hid_device *hid;\n\tstruct usb_interface *intf;\n\tint ifnum;\n\tunsigned int bufsize;\n\tstruct urb *urbin;\n\tchar *inbuf;\n\tdma_addr_t inbuf_dma;\n\tstruct urb *urbctrl;\n\tstruct usb_ctrlrequest *cr;\n\tstruct hid_control_fifo ctrl[256];\n\tunsigned char ctrlhead;\n\tunsigned char ctrltail;\n\tchar *ctrlbuf;\n\tdma_addr_t ctrlbuf_dma;\n\tlong unsigned int last_ctrl;\n\tstruct urb *urbout;\n\tstruct hid_output_fifo out[256];\n\tunsigned char outhead;\n\tunsigned char outtail;\n\tchar *outbuf;\n\tdma_addr_t outbuf_dma;\n\tlong unsigned int last_out;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tlong unsigned int iofl;\n\tstruct timer_list io_retry;\n\tlong unsigned int stop_retry;\n\tunsigned int retry_delay;\n\tstruct work_struct reset_work;\n\twait_queue_head_t wait;\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct user_arg_ptr {\n\tunion {\n\t\tconst char * const *native;\n\t} ptr;\n};\n\nstruct user_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap roles;\n\tstruct mls_range range;\n\tstruct mls_level dfltlevel;\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 0;\n\tchar data[0];\n};\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tbool parent_could_setfcap;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tlong int ucount_max[10];\n\tlong int rlimit_max[4];\n\tstruct binfmt_misc *binfmt_misc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct user_regset;\n\ntypedef int user_regset_get2_fn(struct task_struct *, const struct user_regset *, struct membuf);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\nstruct user_regset {\n\tuser_regset_get2_fn *regset_get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n\tconst char *core_note_name;\n};\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tstruct percpu_counter epoll_watches;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n};\n\nstruct userspace_policy {\n\tunsigned int is_managed;\n\tunsigned int setspeed;\n\tstruct mutex mutex;\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\tlong unsigned int f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct ustring_buffer {\n\tchar buffer[1024];\n};\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\nstruct utimbuf {\n\t__kernel_old_time_t actime;\n\t__kernel_old_time_t modtime;\n};\n\nstruct uts_namespace {\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ns_common ns;\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct validate_flash_t {\n\tint status;\n\tvoid *buf;\n\tuint32_t buf_size;\n\tuint32_t result;\n};\n\nstruct value_name_pair {\n\tint value;\n\tconst char *name;\n};\n\nstruct vas_all_caps {\n\tu64 descriptor;\n\tu64 feat_type;\n};\n\nstruct vas_cop_feat_caps {\n\tu64 descriptor;\n\tu8 win_type;\n\tu8 user_mode;\n\tu16 max_lpar_creds;\n\tu16 max_win_creds;\n\tunion {\n\t\tu16 reserved;\n\t\tu16 def_lpar_creds;\n\t};\n\tatomic_t nr_total_credits;\n\tatomic_t nr_used_credits;\n};\n\nstruct vas_caps {\n\tstruct vas_cop_feat_caps caps;\n\tstruct list_head list;\n\tint nr_open_wins_progress;\n\tint nr_close_wins;\n\tint nr_open_windows;\n\tu8 feat;\n};\n\nstruct vas_caps_entry {\n\tstruct kobject kobj;\n\tstruct vas_cop_feat_caps *caps;\n};\n\nstruct vas_instance {\n\tint vas_id;\n\tstruct ida ida;\n\tstruct list_head node;\n\tstruct platform_device *pdev;\n\tu64 hvwc_bar_start;\n\tu64 uwc_bar_start;\n\tu64 paste_base_addr;\n\tu64 paste_win_id_shift;\n\tu64 irq_port;\n\tint virq;\n\tint fault_crbs;\n\tint fault_fifo_size;\n\tint fifo_in_progress;\n\tspinlock_t fault_lock;\n\tvoid *fault_fifo;\n\tstruct pnv_vas_window *fault_win;\n\tstruct mutex mutex;\n\tstruct pnv_vas_window *rxwin[6];\n\tstruct pnv_vas_window *windows[65536];\n\tchar *name;\n\tchar *dbgname;\n\tstruct dentry *dbgdir;\n};\n\nstruct vas_rx_win_attr {\n\tu64 rx_fifo;\n\tint rx_fifo_size;\n\tint wcreds_max;\n\tbool pin_win;\n\tbool rej_no_credit;\n\tbool tx_wcred_mode;\n\tbool rx_wcred_mode;\n\tbool tx_win_ord_mode;\n\tbool rx_win_ord_mode;\n\tbool data_stamp;\n\tbool nx_win;\n\tbool fault_win;\n\tbool user_win;\n\tbool notify_disable;\n\tbool intr_disable;\n\tbool notify_early;\n\tint lnotify_lpid;\n\tint lnotify_pid;\n\tint lnotify_tid;\n\tu32 pswid;\n\tint tc_mode;\n};\n\nstruct vas_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct vas_cop_feat_caps *, char *);\n\tssize_t (*store)(struct vas_cop_feat_caps *, const char *, size_t);\n};\n\nstruct vas_tx_win_attr {\n\tenum vas_cop_type cop;\n\tint wcreds_max;\n\tint lpid;\n\tint pidr;\n\tint pswid;\n\tint rsvd_txbuf_count;\n\tint tc_mode;\n\tbool user_win;\n\tbool pin_win;\n\tbool rej_no_credit;\n\tbool rsvd_txbuf_enable;\n\tbool tx_wcred_mode;\n\tbool rx_wcred_mode;\n\tbool tx_win_ord_mode;\n\tbool rx_win_ord_mode;\n};\n\nstruct vas_tx_win_open_attr {\n\t__u32 version;\n\t__s16 vas_id;\n\t__u16 reserved1;\n\t__u64 flags;\n\t__u64 reserved2[6];\n};\n\nstruct vas_user_win_ops {\n\tstruct vas_window * (*open_win)(int, u64, enum vas_cop_type);\n\tu64 (*paste_addr)(struct vas_window *);\n\tint (*close_win)(struct vas_window *);\n};\n\nstruct vas_winctx {\n\tu64 rx_fifo;\n\tint rx_fifo_size;\n\tint wcreds_max;\n\tint rsvd_txbuf_count;\n\tbool user_win;\n\tbool nx_win;\n\tbool fault_win;\n\tbool rsvd_txbuf_enable;\n\tbool pin_win;\n\tbool rej_no_credit;\n\tbool tx_wcred_mode;\n\tbool rx_wcred_mode;\n\tbool tx_word_mode;\n\tbool rx_word_mode;\n\tbool data_stamp;\n\tbool xtra_write;\n\tbool notify_disable;\n\tbool intr_disable;\n\tbool fifo_disable;\n\tbool notify_early;\n\tbool notify_os_intr_reg;\n\tint lpid;\n\tint pidr;\n\tint lnotify_lpid;\n\tint lnotify_pid;\n\tint lnotify_tid;\n\tu32 pswid;\n\tint rx_win_id;\n\tint fault_win_id;\n\tint tc_mode;\n\tu64 irq_port;\n\tenum vas_dma_type dma_type;\n\tenum vas_notify_scope min_scope;\n\tenum vas_notify_scope max_scope;\n\tenum vas_notify_after_count notify_after_count;\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vc_state {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned char color;\n\tunsigned char Gx_charset[2];\n\tunsigned int charset: 1;\n\tenum vc_intensity intensity;\n\tbool italic;\n\tbool underline;\n\tbool blink;\n\tbool reverse;\n};\n\nstruct vt_mode {\n\t__u8 mode;\n\t__u8 waitv;\n\t__s16 relsig;\n\t__s16 acqsig;\n\t__s16 frsig;\n};\n\nstruct vc_data {\n\tstruct tty_port port;\n\tstruct vc_state state;\n\tstruct vc_state saved_state;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tunsigned int vc_cell_height;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned int vc_bracketed_paste: 1;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tlong unsigned int vc_tab_stop[4];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedict *uni_pagedict;\n\tstruct uni_pagedict **uni_pagedict_loc;\n\tu32 **vc_uni_lines;\n\tu16 *vc_saved_screen;\n\tunsigned int vc_saved_cols;\n\tunsigned int vc_saved_rows;\n};\n\nstruct vc_draw_region {\n\tlong unsigned int from;\n\tlong unsigned int to;\n\tint x;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct vcpu_dispatch_data {\n\tint last_disp_cpu;\n\tint total_disp;\n\tint same_cpu_disp;\n\tint same_chip_disp;\n\tint diff_chip_disp;\n\tint far_chip_disp;\n\tint numa_home_disp;\n\tint numa_remote_disp;\n\tint numa_far_disp;\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct vdso_arch_data {\n\t__u64 tb_ticks_per_sec;\n\t__u32 dcache_block_size;\n\t__u32 icache_block_size;\n\t__u32 dcache_log_block_size;\n\t__u32 icache_log_block_size;\n\t__u32 syscall_map[15];\n\t__u32 compat_syscall_map[15];\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_clock {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n};\n\nstruct vdso_rng_data {\n\tu64 generation;\n\tu8 is_ready;\n};\n\nstruct vdso_time_data {\n\tstruct arch_vdso_time_data arch_data;\n\tstruct vdso_clock clock_data[2];\n\tstruct vdso_clock aux_clock_data[8];\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vec5_fw_feature {\n\tlong unsigned int val;\n\tunsigned int feature;\n};\n\nstruct vers_iter {\n\tsize_t param_size;\n\tstruct dm_target_versions *vers;\n\tstruct dm_target_versions *old_vers;\n\tchar *end;\n\tuint32_t flags;\n};\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tbool is_firmware_default;\n\tunsigned int (*set_decode)(struct pci_dev *, bool);\n};\n\nstruct vhost_task {\n\tbool (*fn)(void *);\n\tvoid (*handle_sigkill)(void *);\n\tvoid *data;\n\tstruct completion exited;\n\tlong unsigned int flags;\n\tstruct task_struct *task;\n\tstruct mutex exit_mutex;\n};\n\nstruct vio_cmo_pool {\n\tsize_t size;\n\tsize_t free;\n};\n\nstruct vio_cmo {\n\tspinlock_t lock;\n\tstruct delayed_work balance_q;\n\tstruct list_head device_list;\n\tsize_t entitled;\n\tstruct vio_cmo_pool reserve;\n\tstruct vio_cmo_pool excess;\n\tsize_t spare;\n\tsize_t min;\n\tsize_t desired;\n\tsize_t curr;\n\tsize_t high;\n};\n\nstruct vio_cmo_dev_entry {\n\tstruct vio_dev *viodev;\n\tstruct list_head list;\n};\n\nstruct vio_dev {\n\tconst char *name;\n\tconst char *type;\n\tuint32_t unit_address;\n\tuint32_t resource_id;\n\tunsigned int irq;\n\tstruct {\n\t\tsize_t desired;\n\t\tsize_t entitled;\n\t\tsize_t allocated;\n\t\tatomic_t allocs_failed;\n\t} cmo;\n\tenum vio_dev_family family;\n\tstruct device dev;\n};\n\nstruct vio_device_id {\n\tchar type[32];\n\tchar compat[32];\n};\n\nstruct vio_driver {\n\tconst char *name;\n\tconst struct vio_device_id *id_table;\n\tint (*probe)(struct vio_dev *, const struct vio_device_id *);\n\tvoid (*remove)(struct vio_dev *);\n\tvoid (*shutdown)(struct vio_dev *);\n\tlong unsigned int (*get_desired_dma)(struct vio_dev *);\n\tconst struct dev_pm_ops *pm;\n\tstruct device_driver driver;\n};\n\nstruct vio_pfo_op {\n\tu64 flags;\n\ts64 in;\n\ts64 inlen;\n\ts64 out;\n\ts64 outlen;\n\tu64 csbcpb;\n\tvoid *done;\n\tlong unsigned int handle;\n\tunsigned int timeout;\n\tlong int hcall_err;\n};\n\nstruct virtio_device_id {\n\t__u32 device;\n\t__u32 vendor;\n};\n\nstruct virtio_config_ops;\n\nstruct vringh_config_ops;\n\nstruct virtio_map_ops;\n\nstruct vduse_vq_group;\n\nunion virtio_map {\n\tstruct device *dma_dev;\n\tstruct vduse_vq_group *group;\n};\n\nstruct virtio_device {\n\tint index;\n\tbool failed;\n\tbool config_core_enabled;\n\tbool config_driver_disabled;\n\tbool config_change_pending;\n\tspinlock_t config_lock;\n\tspinlock_t vqs_list_lock;\n\tstruct device dev;\n\tstruct virtio_device_id id;\n\tconst struct virtio_config_ops *config;\n\tconst struct vringh_config_ops *vringh_config;\n\tconst struct virtio_map_ops *map;\n\tstruct list_head vqs;\n\tunion {\n\t\tu64 features;\n\t\tu64 features_array[2];\n\t};\n\tvoid *priv;\n\tunion virtio_map vmap;\n};\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\t__virtio16 num_buffers;\n};\n\nstruct vlan_priority_tci_mapping;\n\nstruct vlan_pcpu_stats;\n\nstruct vlan_dev_priv {\n\tunsigned int nr_ingress_mappings;\n\tu32 ingress_priority_map[8];\n\tunsigned int nr_egress_mappings;\n\tstruct vlan_priority_tci_mapping *egress_priority_map[16];\n\t__be16 vlan_proto;\n\tu16 vlan_id;\n\tu16 flags;\n\tstruct net_device *real_dev;\n\tnetdevice_tracker dev_tracker;\n\tunsigned char real_dev_addr[6];\n\tstruct proc_dir_entry *dent;\n\tstruct vlan_pcpu_stats *vlan_pcpu_stats;\n\tstruct netpoll *netpoll;\n};\n\nstruct vlan_ethhdr {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char h_dest[6];\n\t\t\tunsigned char h_source[6];\n\t\t} addrs;\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_group {\n\tunsigned int nr_vlan_devs;\n\tstruct hlist_node hlist;\n\tstruct net_device **vlan_devices_arrays[16];\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct vlan_info {\n\tstruct net_device *real_dev;\n\tstruct vlan_group grp;\n\tstruct list_head vid_list;\n\tunsigned int nr_vids;\n\tbool auto_vid0;\n\tstruct callback_head rcu;\n};\n\nstruct vlan_pcpu_stats {\n\tu64_stats_t rx_packets;\n\tu64_stats_t rx_bytes;\n\tu64_stats_t rx_multicast;\n\tu64_stats_t tx_packets;\n\tu64_stats_t tx_bytes;\n\tstruct u64_stats_sync syncp;\n\tu32 rx_errors;\n\tu32 tx_dropped;\n};\n\nstruct vlan_priority_tci_mapping {\n\tu32 priority;\n\tu16 vlan_qos;\n\tstruct vlan_priority_tci_mapping *next;\n};\n\nstruct vlan_type_depth {\n\t__be16 type;\n\tu16 depth;\n};\n\nstruct vlan_vid_info {\n\tstruct list_head list;\n\t__be16 proto;\n\tu16 vid;\n\tint refcount;\n};\n\nstruct vm_area_desc {\n\tconst struct mm_struct * const mm;\n\tstruct file * const file;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tstruct file *vm_file;\n\tvma_flags_t vma_flags;\n\tpgprot_t page_prot;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *private_data;\n\tstruct mmap_action action;\n};\n\nstruct vm_userfaultfd_ctx {};\n\nstruct vma_numab_state;\n\nstruct vm_area_struct {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int vm_start;\n\t\t\tlong unsigned int vm_end;\n\t\t};\n\t\tfreeptr_t vm_freeptr;\n\t};\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tunion {\n\t\tconst vm_flags_t vm_flags;\n\t\tvma_flags_t flags;\n\t};\n\tunsigned int vm_lock_seq;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct mempolicy *vm_policy;\n\tstruct vma_numab_state *numab_state;\n\trefcount_t vm_refcnt;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct vm_area_struct__safe_trusted_or_null {\n\tstruct mm_struct *vm_mm;\n\tstruct file *vm_file;\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[117];\n};\n\nstruct vm_fault {\n\tconst struct {\n\t\tstruct vm_area_struct *vma;\n\t\tgfp_t gfp_mask;\n\t\tlong unsigned int pgoff;\n\t\tlong unsigned int address;\n\t\tlong unsigned int real_address;\n\t};\n\tenum fault_flag flags;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tunion {\n\t\tpte_t orig_pte;\n\t\tpmd_t orig_pmd;\n\t};\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*may_split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tint (*mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int, long unsigned int);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, unsigned int);\n\tvm_fault_t (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n\tint (*set_policy)(struct vm_area_struct *, struct mempolicy *);\n\tstruct mempolicy * (*get_policy)(struct vm_area_struct *, long unsigned int, long unsigned int *);\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n\tvoid (*close)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct vm_struct {\n\tunion {\n\t\tstruct vm_struct *next;\n\t\tstruct llist_node llnode;\n\t};\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int page_order;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n\tlong unsigned int requested_size;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tlong unsigned int start_gap;\n};\n\nstruct vma_exclude_readers_state {\n\tstruct vm_area_struct *vma;\n\tint state;\n\tbool detaching;\n\tbool detached;\n\tbool exclusive;\n};\n\nstruct vma_list {\n\tstruct vm_area_struct *vma;\n\tstruct list_head head;\n\trefcount_t mmap_count;\n};\n\nstruct vma_merge_struct {\n\tstruct mm_struct *mm;\n\tstruct vma_iterator *vmi;\n\tstruct vm_area_struct *prev;\n\tstruct vm_area_struct *middle;\n\tstruct vm_area_struct *next;\n\tstruct vm_area_struct *target;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tlong unsigned int pgoff;\n\tvm_flags_t vm_flags;\n\tstruct file *file;\n\tstruct anon_vma *anon_vma;\n\tstruct mempolicy *policy;\n\tstruct vm_userfaultfd_ctx uffd_ctx;\n\tstruct anon_vma_name *anon_name;\n\tenum vma_merge_state state;\n\tstruct vm_area_struct *copied_from;\n\tbool just_expand: 1;\n\tbool give_up_on_oom: 1;\n\tbool skip_vma_uprobe: 1;\n\tbool __adjust_middle_start: 1;\n\tbool __adjust_next_start: 1;\n\tbool __remove_middle: 1;\n\tbool __remove_next: 1;\n};\n\nstruct vma_numab_state {\n\tlong unsigned int next_scan;\n\tlong unsigned int pids_active_reset;\n\tlong unsigned int pids_active[2];\n\tint start_scan_seq;\n\tint prev_scan_seq;\n};\n\nstruct vma_prepare {\n\tstruct vm_area_struct *vma;\n\tstruct vm_area_struct *adj_next;\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tstruct anon_vma *anon_vma;\n\tstruct vm_area_struct *insert;\n\tstruct vm_area_struct *remove;\n\tstruct vm_area_struct *remove2;\n\tbool skip_vma_uprobe: 1;\n};\n\nstruct vma_remap_struct {\n\tlong unsigned int addr;\n\tlong unsigned int old_len;\n\tlong unsigned int new_len;\n\tconst long unsigned int flags;\n\tlong unsigned int new_addr;\n\tstruct vm_userfaultfd_ctx *uf;\n\tstruct list_head *uf_unmap_early;\n\tstruct list_head *uf_unmap;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int delta;\n\tbool populate_expand;\n\tenum mremap_type remap_type;\n\tbool mmap_locked;\n\tlong unsigned int charged;\n\tbool vmi_needs_invalidate;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t};\n\tlong unsigned int flags;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int used_map[2];\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n\tunsigned int cpu;\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n\tstruct xarray vmap_blocks;\n};\n\nstruct vmap_pool {\n\tstruct list_head head;\n\tlong unsigned int len;\n};\n\nstruct vmap_node {\n\tstruct vmap_pool pool[256];\n\tspinlock_t pool_lock;\n\tbool skip_populate;\n\tstruct rb_list busy;\n\tstruct rb_list lazy;\n\tstruct list_head purge_list;\n\tstruct work_struct purge_work;\n\tlong unsigned int nr_purged;\n};\n\nstruct vmcore_cb {\n\tbool (*pfn_is_ram)(struct vmcore_cb *, long unsigned int);\n\tint (*get_device_ram)(struct vmcore_cb *, struct list_head *);\n\tstruct list_head next;\n};\n\nstruct vmcore_range {\n\tstruct list_head list;\n\tlong long unsigned int paddr;\n\tlong long unsigned int size;\n\tloff_t offset;\n};\n\nstruct vmemmap_backing {\n\tstruct vmemmap_backing *list;\n\tlong unsigned int phys;\n\tlong unsigned int virt_addr;\n};\n\nstruct vmpressure_event {\n\tstruct eventfd_ctx *efd;\n\tenum vmpressure_levels level;\n\tenum vmpressure_modes mode;\n\tstruct list_head node;\n};\n\nstruct vpa_dtl {\n\tstruct dtl_entry *buf;\n\tu64 last_idx;\n};\n\nstruct vpa_pmu_buf {\n\tint nr_pages;\n\tbool snapshot;\n\tu64 *base;\n\tu64 size;\n\tu64 head;\n\tu64 head_size;\n\tint boottb_freq_saved;\n\tu64 threshold;\n\tbool full;\n};\n\nstruct vpa_pmu_ctx {\n\tstruct perf_output_handle handle;\n};\n\nunion vsx_reg {\n\tu8 b[16];\n\tu16 h[8];\n\tu32 w[4];\n\tlong unsigned int d[2];\n\tfloat fp[4];\n\tdouble dp[2];\n\t__vector128 v;\n};\n\nstruct vt_consize {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_vlin;\n\t__u16 v_clin;\n\t__u16 v_vcol;\n\t__u16 v_ccol;\n};\n\nstruct vt_consizecsrpos {\n\t__u16 con_rows;\n\t__u16 con_cols;\n\t__u16 csr_row;\n\t__u16 csr_col;\n};\n\nstruct vt_event {\n\t__u32 event;\n\t__u32 oldev;\n\t__u32 newev;\n\t__u32 pad[4];\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vt_setactivate {\n\t__u32 console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_sizes {\n\t__u16 v_rows;\n\t__u16 v_cols;\n\t__u16 v_scrollsize;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nstruct vt_stat {\n\t__u16 v_active;\n\t__u16 v_signal;\n\t__u16 v_state;\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct wait_bit_key {\n\tlong unsigned int *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\nstruct wait_exceptional_entry_queue {\n\twait_queue_entry_t wait;\n\tstruct exceptional_entry_key key;\n};\n\nstruct wait_page_key {\n\tstruct folio *folio;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n};\n\nstruct walk_stack_ctx {\n\tstruct bpf_prog *prog;\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\nstruct wb_stats {\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_io;\n\tlong unsigned int nr_more_io;\n\tlong unsigned int nr_dirty_time;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_reclaimable;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int wb_thresh;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct weighted_interleave_state {\n\tbool mode_auto;\n\tu8 iw_table[0];\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nstruct word_at_a_time {};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\nstruct work_offq_data {\n\tu32 pool_id;\n\tu32 disable;\n\tu32 flags;\n};\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tu64 current_at;\n\tunsigned int current_color;\n\tint sleeping;\n\twork_func_t last_func;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tchar desc[32];\n\tstruct workqueue_struct *rescue_wq;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tbool cpu_stall;\n\tint nr_running;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct work_struct idle_cull_work;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t __pod_cpumask;\n\tbool affn_strict;\n\tenum wq_affn_scope affn_scope;\n\tbool ordered;\n};\n\nstruct wq_flusher;\n\nstruct wq_device;\n\nstruct wq_node_nr_active;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint max_active;\n\tint min_active;\n\tint saved_max_active;\n\tint saved_min_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[32];\n\tstruct callback_head rcu;\n\tlong: 64;\n\tunsigned int flags;\n\tstruct pool_workqueue **cpu_pwq;\n\tstruct wq_node_nr_active *node_nr_active[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tstruct device dev;\n};\n\nstruct wq_drain_dead_softirq_work {\n\tstruct work_struct work;\n\tstruct worker_pool *pool;\n\tstruct completion done;\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_node_nr_active {\n\tint max;\n\tatomic_t nr;\n\traw_spinlock_t lock;\n\tstruct list_head pending_pwqs;\n};\n\nstruct wq_pod_type {\n\tint nr_pods;\n\tcpumask_var_t *pod_cpus;\n\tint *pod_node;\n\tint *cpu_pod;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\nstruct wrapper {\n\tcmp_func_t cmp;\n\tswap_func_t swap;\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int unpinned_netfs_wb: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tstruct folio_batch fbatch;\n\tlong unsigned int index;\n\tint saved_err;\n\tstruct bdi_writeback *wb;\n\tstruct inode *inode;\n\tint wb_id;\n\tint wb_lcand_id;\n\tint wb_tcand_id;\n\tsize_t wb_bytes;\n\tsize_t wb_lcand_bytes;\n\tsize_t wb_tcand_bytes;\n};\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct wrprotect_file_state {\n\tint cleaned;\n\tlong unsigned int pgoff;\n\tlong unsigned int pfn;\n\tlong unsigned int nr_pages;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n\tunsigned int done_acquire;\n\tstruct ww_class *ww_class;\n\tvoid *contending_lock;\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct x509_certificate {\n\tstruct x509_certificate *next;\n\tstruct x509_certificate *signer;\n\tstruct public_key *pub;\n\tstruct public_key_signature *sig;\n\tu8 sha256[32];\n\tchar *issuer;\n\tchar *subject;\n\tstruct asymmetric_key_id *id;\n\tstruct asymmetric_key_id *skid;\n\ttime64_t valid_from;\n\ttime64_t valid_to;\n\tconst void *tbs;\n\tunsigned int tbs_size;\n\tunsigned int raw_sig_size;\n\tconst void *raw_sig;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_subject;\n\tunsigned int raw_subject_size;\n\tunsigned int raw_skid_size;\n\tconst void *raw_skid;\n\tunsigned int index;\n\tbool seen;\n\tbool verified;\n\tbool self_signed;\n\tbool unsupported_sig;\n\tbool blacklisted;\n};\n\nstruct x509_parse_context {\n\tstruct x509_certificate *cert;\n\tlong unsigned int data;\n\tconst void *key;\n\tsize_t key_size;\n\tconst void *params;\n\tsize_t params_size;\n\tenum OID key_algo;\n\tenum OID last_oid;\n\tenum OID sig_algo;\n\tu8 o_size;\n\tu8 cn_size;\n\tu8 email_size;\n\tu16 o_offset;\n\tu16 cn_offset;\n\tu16 email_offset;\n\tunsigned int raw_akid_size;\n\tconst void *raw_akid;\n\tconst void *akid_raw_issuer;\n\tunsigned int akid_raw_issuer_size;\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[3];\n\t\tlong unsigned int marks[3];\n\t};\n};\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n\tstruct list_lru *xa_lru;\n};\n\nstruct xbitmap32 {\n\tstruct rb_root_cached xb_root;\n};\n\nstruct xagb_bitmap {\n\tstruct xbitmap32 agbitmap;\n};\n\nstruct xagino_bitmap {\n\tstruct xbitmap32 aginobitmap;\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct xattr_args {\n\t__u64 value;\n\t__u32 size;\n\t__u32 flags;\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct mnt_idmap *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\nstruct xattr_name {\n\tchar name[256];\n};\n\nstruct xb1s_ff_report {\n\t__u8 report_id;\n\t__u8 enable;\n\t__u8 magnitude[4];\n\t__u8 duration_10ms;\n\t__u8 start_delay_10ms;\n\t__u8 loop_count;\n};\n\nstruct xb_key {\n\tuint32_t xb_magic;\n\tuint32_t xb_size;\n\tloff_t xb_offset;\n};\n\nstruct xbitmap32_node {\n\tstruct rb_node bn_rbnode;\n\tuint32_t bn_start;\n\tuint32_t bn_last;\n\tuint32_t __bn_subtree_last;\n};\n\nstruct xbitmap64 {\n\tstruct rb_root_cached xb_root;\n};\n\nstruct xbitmap64_node {\n\tstruct rb_node bn_rbnode;\n\tuint64_t bn_start;\n\tuint64_t bn_last;\n\tuint64_t __bn_subtree_last;\n};\n\nstruct xbtree_afakeroot {\n\txfs_agblock_t af_root;\n\tunsigned int af_levels;\n\tunsigned int af_blocks;\n};\n\nstruct xfs_ifork;\n\nstruct xbtree_ifakeroot {\n\tstruct xfs_ifork *if_fork;\n\tint64_t if_blocks;\n\tunsigned int if_levels;\n\tunsigned int if_fork_size;\n};\n\nstruct xcede_latency_record {\n\tu8 hint;\n\t__be64 latency_ticks;\n\tu8 wake_on_irqs;\n} __attribute__((packed));\n\nstruct xcede_latency_payload {\n\tu8 record_size;\n\tstruct xcede_latency_record records[16];\n};\n\nstruct xcede_latency_parameter {\n\t__be16 payload_size;\n\tstruct xcede_latency_payload payload;\n\tu8 null_char;\n};\n\nstruct xfs_perag;\n\nstruct xfs_buf;\n\nstruct xfs_btree_cur;\n\nstruct xchk_ag {\n\tstruct xfs_perag *pag;\n\tstruct xfs_buf *agf_bp;\n\tstruct xfs_buf *agi_bp;\n\tstruct xfs_btree_cur *bno_cur;\n\tstruct xfs_btree_cur *cnt_cur;\n\tstruct xfs_btree_cur *ino_cur;\n\tstruct xfs_btree_cur *fino_cur;\n\tstruct xfs_btree_cur *rmap_cur;\n\tstruct xfs_btree_cur *refc_cur;\n};\n\nstruct xfs_scrub;\n\nstruct xchk_agfl_info {\n\tunsigned int agflcount;\n\tunsigned int nr_entries;\n\txfs_agblock_t *entries;\n\tstruct xfs_buf *agfl_bp;\n\tstruct xfs_scrub *sc;\n};\n\nstruct xfs_alloc_rec_incore {\n\txfs_agblock_t ar_startblock;\n\txfs_extlen_t ar_blockcount;\n};\n\nstruct xchk_alloc {\n\tstruct xfs_alloc_rec_incore prev;\n};\n\nstruct xfs_iext_leaf;\n\nstruct xfs_iext_cursor {\n\tstruct xfs_iext_leaf *leaf;\n\tint pos;\n};\n\nstruct xchk_bmap_check_rmap_info {\n\tstruct xfs_scrub *sc;\n\tint whichfork;\n\tstruct xfs_iext_cursor icur;\n};\n\nstruct xfs_bmbt_irec {\n\txfs_fileoff_t br_startoff;\n\txfs_fsblock_t br_startblock;\n\txfs_filblks_t br_blockcount;\n\txfs_exntst_t br_state;\n};\n\nstruct xchk_bmap_info {\n\tstruct xfs_scrub *sc;\n\tstruct xfs_iext_cursor icur;\n\tstruct xfs_bmbt_irec prev_rec;\n\tbool is_rt;\n\tbool is_shared;\n\tbool was_loaded;\n\tint whichfork;\n};\n\nstruct xchk_btree;\n\nunion xfs_btree_rec;\n\ntypedef int (*xchk_btree_rec_fn)(struct xchk_btree *, const union xfs_btree_rec *);\n\nstruct xfs_bmbt_rec {\n\t__be64 l0;\n\t__be64 l1;\n};\n\ntypedef struct xfs_bmbt_rec xfs_bmbt_rec_t;\n\ntypedef xfs_bmbt_rec_t xfs_bmdr_rec_t;\n\nstruct xfs_alloc_rec {\n\t__be32 ar_startblock;\n\t__be32 ar_blockcount;\n};\n\nstruct xfs_inobt_rec {\n\t__be32 ir_startino;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ir_freecount;\n\t\t} f;\n\t\tstruct {\n\t\t\t__be16 ir_holemask;\n\t\t\t__u8 ir_count;\n\t\t\t__u8 ir_freecount;\n\t\t} sp;\n\t} ir_u;\n\t__be64 ir_free;\n};\n\nstruct xfs_rmap_rec {\n\t__be32 rm_startblock;\n\t__be32 rm_blockcount;\n\t__be64 rm_owner;\n\t__be64 rm_offset;\n};\n\nstruct xfs_refcount_rec {\n\t__be32 rc_startblock;\n\t__be32 rc_blockcount;\n\t__be32 rc_refcount;\n};\n\nunion xfs_btree_rec {\n\tstruct xfs_bmbt_rec bmbt;\n\txfs_bmdr_rec_t bmbr;\n\tstruct xfs_alloc_rec alloc;\n\tstruct xfs_inobt_rec inobt;\n\tstruct xfs_rmap_rec rmap;\n\tstruct xfs_refcount_rec refc;\n};\n\nstruct xfs_bmbt_key {\n\t__be64 br_startoff;\n};\n\ntypedef struct xfs_bmbt_key xfs_bmdr_key_t;\n\ntypedef struct xfs_alloc_rec xfs_alloc_key_t;\n\nstruct xfs_inobt_key {\n\t__be32 ir_startino;\n};\n\nstruct xfs_rmap_key {\n\t__be32 rm_startblock;\n\t__be64 rm_owner;\n\t__be64 rm_offset;\n} __attribute__((packed));\n\nstruct xfs_refcount_key {\n\t__be32 rc_startblock;\n};\n\nunion xfs_btree_key {\n\tstruct xfs_bmbt_key bmbt;\n\txfs_bmdr_key_t bmbr;\n\txfs_alloc_key_t alloc;\n\tstruct xfs_inobt_key inobt;\n\tstruct xfs_rmap_key rmap;\n\tstruct xfs_rmap_key __rmap_bigkey[2];\n\tstruct xfs_refcount_key refc;\n};\n\nstruct xchk_btree_key {\n\tunion xfs_btree_key key;\n\tbool valid;\n};\n\nstruct xfs_owner_info;\n\nstruct xchk_btree {\n\tstruct xfs_scrub *sc;\n\tstruct xfs_btree_cur *cur;\n\txchk_btree_rec_fn scrub_rec;\n\tconst struct xfs_owner_info *oinfo;\n\tvoid *private;\n\tbool lastrec_valid;\n\tunion xfs_btree_rec lastrec;\n\tstruct list_head to_check;\n\tstruct xchk_btree_key lastkey[0];\n};\n\nstruct xfs_da_geometry;\n\nstruct xfs_inode;\n\nstruct xfs_da_args {\n\tstruct xfs_da_geometry *geo;\n\tconst uint8_t *name;\n\tconst uint8_t *new_name;\n\tvoid *value;\n\tvoid *new_value;\n\tstruct xfs_inode *dp;\n\tstruct xfs_trans *trans;\n\txfs_ino_t inumber;\n\txfs_ino_t owner;\n\tint valuelen;\n\tint new_valuelen;\n\tuint8_t filetype;\n\tuint8_t op_flags;\n\tuint8_t attr_filter;\n\tshort int namelen;\n\tshort int new_namelen;\n\txfs_dahash_t hashval;\n\txfs_extlen_t total;\n\tint whichfork;\n\txfs_dablk_t blkno;\n\tint index;\n\txfs_dablk_t rmtblkno;\n\tint rmtblkcnt;\n\tint rmtvaluelen;\n\txfs_dablk_t blkno2;\n\tint index2;\n\txfs_dablk_t rmtblkno2;\n\tint rmtblkcnt2;\n\tint rmtvaluelen2;\n\tenum xfs_dacmp cmpresult;\n};\n\nstruct xfs_da_state;\n\nstruct xchk_da_btree {\n\tstruct xfs_da_args dargs;\n\txfs_dahash_t hashes[5];\n\tint maxrecs[5];\n\tstruct xfs_da_state *state;\n\tstruct xfs_scrub *sc;\n\tvoid *private;\n\txfs_dablk_t lowest;\n\txfs_dablk_t highest;\n\tint tree_level;\n};\n\nstruct xfs_parent_rec {\n\t__be64 p_ino;\n\t__be32 p_gen;\n} __attribute__((packed));\n\nstruct xfs_name {\n\tconst unsigned char *name;\n\tint len;\n\tint type;\n};\n\nstruct xfarray;\n\nstruct xfblob;\n\nstruct xchk_dir {\n\tstruct xfs_scrub *sc;\n\tstruct xfs_parent_rec pptr_rec;\n\tstruct xfs_da_args pptr_args;\n\tstruct xfarray *dir_entries;\n\tstruct xfblob *dir_names;\n\tbool need_revalidate;\n\tstruct xfs_name xname;\n\tuint8_t namebuf[256];\n};\n\nstruct xchk_dirent {\n\txfblob_cookie name_cookie;\n\txfs_ino_t ino;\n\tuint8_t namelen;\n};\n\nstruct xino_bitmap {\n\tstruct xbitmap64 inobitmap;\n};\n\nstruct xchk_dirpath {\n\tstruct list_head list;\n\txfarray_idx_t first_step;\n\txfarray_idx_t second_step;\n\tstruct xino_bitmap seen_inodes;\n\tunsigned int nr_steps;\n\tunsigned int path_nr;\n\tenum xchk_dirpath_outcome outcome;\n};\n\nstruct xchk_dirpath_step {\n\txfblob_cookie name_cookie;\n\tunsigned int name_len;\n\tstruct xfs_parent_rec pptr_rec;\n};\n\nstruct xfs_parent_args {\n\tstruct xfs_parent_rec rec;\n\tstruct xfs_parent_rec new_rec;\n\tstruct xfs_da_args args;\n};\n\nstruct xrep_adoption {\n\tstruct xfs_scrub *sc;\n\tstruct xfs_name *xname;\n\tstruct xfs_parent_args ppargs;\n\tunsigned int orphanage_blkres;\n\tunsigned int child_blkres;\n\tbool bump_child_nlink: 1;\n};\n\nstruct xfs_hook {\n\tstruct notifier_block nb;\n};\n\nstruct xfs_dir_hook {\n\tstruct xfs_hook dirent_hook;\n};\n\nstruct xchk_dirtree {\n\tstruct xfs_scrub *sc;\n\txfs_ino_t root_ino;\n\txfs_ino_t scan_ino;\n\txfs_ino_t parent_ino;\n\tstruct xfs_parent_rec pptr_rec;\n\tstruct xfs_da_args pptr_args;\n\tstruct xfs_name xname;\n\tchar namebuf[256];\n\tstruct xrep_adoption adoption;\n\tstruct xfs_dir_hook dhook;\n\tstruct xfs_parent_args ppargs;\n\tstruct mutex lock;\n\tstruct xfs_name hook_xname;\n\tunsigned char hook_namebuf[256];\n\tstruct xfarray *path_steps;\n\tstruct xfblob *path_names;\n\tstruct list_head path_list;\n\tunsigned int nr_paths;\n\tunsigned int parents_found;\n\tbool stale: 1;\n\tbool aborted: 1;\n};\n\nstruct xchk_dirtree_outcomes {\n\tunsigned int bad;\n\tunsigned int suspect;\n\tunsigned int good;\n\tbool needs_adoption;\n};\n\nstruct xchk_fscounters {\n\tstruct xfs_scrub *sc;\n\tuint64_t icount;\n\tuint64_t ifree;\n\tuint64_t fdblocks;\n\tuint64_t frextents;\n\tuint64_t frextents_delayed;\n\tlong long unsigned int icount_min;\n\tlong long unsigned int icount_max;\n\tbool frozen;\n};\n\nstruct xchk_health_map {\n\tenum xchk_health_group group;\n\tunsigned int sick_mask;\n};\n\nstruct xchk_iallocbt {\n\tlong long unsigned int inodes;\n\txfs_agino_t next_startino;\n\txfs_agino_t next_cluster_ino;\n};\n\nstruct xchk_iscan {\n\tstruct xfs_scrub *sc;\n\tstruct mutex lock;\n\txfs_ino_t scan_start_ino;\n\txfs_ino_t cursor_ino;\n\txfs_ino_t skip_ino;\n\txfs_ino_t __visited_ino;\n\tlong unsigned int __opstate;\n\tlong unsigned int __iget_deadline;\n\tunsigned int iget_timeout;\n\tunsigned int iget_retry_delay;\n\txfs_ino_t __batch_ino;\n\txfs_inofree_t __skipped_inomask;\n\tstruct xfs_inode *__inodes[64];\n};\n\nstruct xchk_meta_ops {\n\tint (*setup)(struct xfs_scrub *);\n\tint (*scrub)(struct xfs_scrub *);\n\tint (*repair)(struct xfs_scrub *);\n\tint (*repair_eval)(struct xfs_scrub *);\n\tbool (*has)(const struct xfs_mount *);\n\tenum xchk_type type;\n};\n\nstruct xfs_dir_update {\n\tstruct xfs_inode *dp;\n\tconst struct xfs_name *name;\n\tstruct xfs_inode *ip;\n\tstruct xfs_parent_args *ppargs;\n};\n\nstruct xchk_metapath {\n\tstruct xfs_scrub *sc;\n\tstruct xfs_name xname;\n\tstruct xfs_dir_update du;\n\tconst char *path;\n\tstruct xfs_inode *dp;\n\tunsigned int dp_ilock_flags;\n\tunsigned int link_resblks;\n\tunsigned int unlink_resblks;\n\tstruct xfs_parent_args link_ppargs;\n\tstruct xfs_parent_args unlink_ppargs;\n\tstruct xfs_da_args pptr_args;\n};\n\nstruct xchk_nlink {\n\txfs_nlink_t parents;\n\txfs_nlink_t backrefs;\n\txfs_nlink_t children;\n\tunsigned int flags;\n};\n\nstruct xchk_nlink_ctrs {\n\tstruct xfs_scrub *sc;\n\tstruct xfarray *nlinks;\n\tstruct mutex lock;\n\tstruct xchk_iscan collect_iscan;\n\tstruct xchk_iscan compare_iscan;\n\tstruct xfs_dir_hook dhook;\n\tstruct xrep_adoption adoption;\n\tstruct xfs_name xname;\n\tchar namebuf[256];\n};\n\nstruct xchk_parent_ctx {\n\tstruct xfs_scrub *sc;\n\txfs_nlink_t nlink;\n};\n\nstruct xchk_pptr {\n\txfblob_cookie name_cookie;\n\tstruct xfs_parent_rec pptr_rec;\n\tuint8_t namelen;\n};\n\nstruct xchk_pptrs {\n\tstruct xfs_scrub *sc;\n\tlong long unsigned int pptrs_found;\n\txfs_ino_t parent_ino;\n\tstruct xfarray *pptr_entries;\n\tstruct xfblob *pptr_names;\n\tstruct xfs_da_args pptr_args;\n\tbool need_revalidate;\n\tstruct xfs_name xname;\n\tchar namebuf[256];\n};\n\nstruct xfs_refcount_irec {\n\txfs_agblock_t rc_startblock;\n\txfs_extlen_t rc_blockcount;\n\txfs_nlink_t rc_refcount;\n\tenum xfs_refc_domain rc_domain;\n};\n\nstruct xchk_refcbt_records {\n\tstruct xfs_refcount_irec prev_rec;\n\txfs_agblock_t next_unshared_agbno;\n\txfs_agblock_t cow_blocks;\n\tenum xfs_refc_domain prev_domain;\n};\n\nstruct xchk_refcnt_check {\n\tstruct xfs_scrub *sc;\n\tstruct list_head fragments;\n\txfs_agblock_t bno;\n\txfs_extlen_t len;\n\txfs_nlink_t refcount;\n\txfs_nlink_t seen;\n};\n\nstruct xfs_rmap_irec {\n\txfs_agblock_t rm_startblock;\n\txfs_extlen_t rm_blockcount;\n\tuint64_t rm_owner;\n\tuint64_t rm_offset;\n\tunsigned int rm_flags;\n};\n\nstruct xchk_refcnt_frag {\n\tstruct list_head list;\n\tstruct xfs_rmap_irec rm;\n};\n\nstruct xchk_relax {\n\tlong unsigned int next_resched;\n\tunsigned int resched_nr;\n\tbool interruptible;\n};\n\nstruct xchk_rmap {\n\tstruct xfs_rmap_irec overlap_rec;\n\tstruct xfs_rmap_irec prev_rec;\n\tstruct xagb_bitmap fs_owned;\n\tstruct xagb_bitmap log_owned;\n\tstruct xagb_bitmap ag_owned;\n\tstruct xagb_bitmap inobt_owned;\n\tstruct xagb_bitmap refcbt_owned;\n\tbool bitmaps_complete;\n};\n\nstruct xchk_rmap_ownedby_info {\n\tconst struct xfs_owner_info *oinfo;\n\txfs_filblks_t *blocks;\n};\n\nstruct xfs_rtgroup;\n\nstruct xchk_rt {\n\tstruct xfs_rtgroup *rtg;\n\tunsigned int rtlock_flags;\n\tstruct xfs_btree_cur *rmap_cur;\n\tstruct xfs_btree_cur *refc_cur;\n};\n\nstruct xchk_scrub_stats {\n\tuint32_t invocations;\n\tuint32_t clean;\n\tuint32_t corrupt;\n\tuint32_t preen;\n\tuint32_t xfail;\n\tuint32_t xcorrupt;\n\tuint32_t incomplete;\n\tuint32_t warning;\n\tuint32_t retries;\n\tuint32_t repair_invocations;\n\tuint32_t repair_success;\n\tuint64_t checktime_us;\n\tuint64_t repairtime_us;\n\tspinlock_t css_lock;\n};\n\nstruct xchk_stats {\n\tstruct dentry *cs_debugfs;\n\tstruct xchk_scrub_stats cs_stats[33];\n};\n\nstruct xchk_stats_run {\n\tu64 scrub_ns;\n\tu64 repair_ns;\n\tunsigned int retries;\n\tbool repair_attempted;\n\tbool repair_succeeded;\n};\n\nstruct xchk_xattr_buf {\n\tlong unsigned int *usedmap;\n\tlong unsigned int *freemap;\n\tunsigned char *name;\n\tvoid *value;\n\tsize_t value_sz;\n};\n\nstruct xdab_bitmap {\n\tstruct xbitmap32 dabitmap;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tu8 cb[24];\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tstruct list_head list_node;\n\tlong: 64;\n};\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_cpumap_stats {\n\tunsigned int redirect;\n\tunsigned int pass;\n\tunsigned int drop;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tstruct bpf_prog *xdp_prog;\n\tunsigned int count;\n\tlocal_lock_t bq_lock;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu32 len;\n\tu32 headroom;\n\tu32 metasize;\n\tenum xdp_mem_type mem_type: 32;\n\tstruct net_device *dev_rx;\n\tu32 frame_sz;\n\tu32 flags;\n};\n\nstruct xdp_frame_bulk {\n\tint count;\n\tnetmem_ref q[16];\n};\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct xdp_metadata_ops {\n\tint (*xmo_rx_timestamp)(const struct xdp_md *, u64 *);\n\tint (*xmo_rx_hash)(const struct xdp_md *, u32 *, enum xdp_rss_hash_type *);\n\tint (*xmo_rx_vlan_tag)(const struct xdp_md *, __be16 *, u16 *);\n};\n\nstruct xdp_page_head {\n\tstruct xdp_buff orig_ctx;\n\tstruct xdp_buff ctx;\n\tunion {\n\t\tstruct {\n\t\t\tstruct {} __empty_frame;\n\t\t\tstruct xdp_frame frame[0];\n\t\t};\n\t\tstruct {\n\t\t\tstruct {} __empty_data;\n\t\t\tu8 data[0];\n\t\t};\n\t};\n};\n\nstruct xsk_queue;\n\nstruct xdp_umem;\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tstruct xsk_buff_pool *pool;\n\tu16 queue_id;\n\tbool zc;\n\tbool sg;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xsk_queue *tx;\n\tstruct list_head tx_list;\n\tu32 tx_budget_spent;\n\tu64 rx_dropped;\n\tu64 rx_queue_full;\n\tstruct sk_buff *skb;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n\tu32 max_tx_budget;\n\tstruct mutex mutex;\n\tstruct xsk_queue *fq_tmp;\n\tstruct xsk_queue *cq_tmp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_test_data {\n\tstruct xdp_buff *orig_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info rxq;\n\tstruct net_device *dev;\n\tstruct page_pool *pp;\n\tstruct xdp_frame **frames;\n\tstruct sk_buff **skbs;\n\tstruct xdp_mem_info mem;\n\tu32 batch_size;\n\tu32 frame_cnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_umem {\n\tvoid *addrs;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunks;\n\tu32 npgs;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tu8 flags;\n\tu8 tx_metadata_len;\n\tbool zc;\n\tstruct page **pgs;\n\tint id;\n\tstruct list_head xsk_dma_list;\n\tstruct work_struct work;\n};\n\nstruct xdr_skb_reader {\n\tstruct sk_buff *skb;\n\tunsigned int offset;\n\tbool need_checksum;\n\tsize_t count;\n\t__wsum csum;\n};\n\nstruct xfile;\n\nstruct xfarray {\n\tstruct xfile *xfile;\n\txfarray_idx_t nr;\n\txfarray_idx_t max_nr;\n\tuint64_t unset_slots;\n\tsize_t obj_size;\n\tint obj_size_log;\n};\n\ntypedef cmp_func_t xfarray_cmp_fn;\n\nstruct xfarray_sortinfo {\n\tstruct xfarray *array;\n\txfarray_cmp_fn cmp_fn;\n\tuint8_t max_stack_depth;\n\tint8_t stack_depth;\n\tuint8_t max_stack_used;\n\tunsigned int flags;\n\tstruct xchk_relax relax;\n\tstruct folio *folio;\n\txfarray_idx_t first_folio_idx;\n\txfarray_idx_t last_folio_idx;\n};\n\nstruct xfblob {\n\tstruct xfile *xfile;\n\tloff_t last_offset;\n};\n\nstruct xfile {\n\tstruct file *file;\n};\n\nstruct xfrm4_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm4_protocol *next;\n\tint priority;\n};\n\nstruct xfrm6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tstruct xfrm6_protocol *next;\n\tint priority;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_dev_offload {\n\tstruct net_device *dev;\n\tnetdevice_tracker dev_tracker;\n\tstruct net_device *real_dev;\n\tlong unsigned int offload_handle;\n\tu8 dir: 2;\n\tu8 type: 2;\n\tu8 flags: 2;\n};\n\nstruct xfrm_dst {\n\tunion {\n\t\tstruct dst_entry dst;\n\t\tstruct rtable rt;\n\t\tstruct rt6_info rt6;\n\t} u;\n\tstruct dst_entry *route;\n\tstruct dst_entry *child;\n\tstruct dst_entry *path;\n\tstruct xfrm_policy *pols[2];\n\tint num_pols;\n\tint num_xfrms;\n\tu32 xfrm_genid;\n\tu32 policy_genid;\n\tu32 route_mtu_cached;\n\tu32 child_mtu_cached;\n\tu32 route_cookie;\n\tu32 path_cookie;\n};\n\nstruct xfrm_dst_lookup_params {\n\tstruct net *net;\n\tdscp_t dscp;\n\tint oif;\n\txfrm_address_t *saddr;\n\txfrm_address_t *daddr;\n\tu32 mark;\n\t__u8 ipproto;\n\tunion flowi_uli uli;\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_flo {\n\tstruct dst_entry *dst_orig;\n\tu8 flags;\n};\n\nstruct xfrm_flow_keys {\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_control control;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t} addrs;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_keyid gre;\n};\n\nstruct xfrm_hash_state_ptrs {\n\tconst struct hlist_head *bydst;\n\tconst struct hlist_head *bysrc;\n\tconst struct hlist_head *byspi;\n\tunsigned int hmask;\n};\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_if_decode_session_result;\n\nstruct xfrm_if_cb {\n\tbool (*decode_session)(struct sk_buff *, short unsigned int, struct xfrm_if_decode_session_result *);\n};\n\nstruct xfrm_if_decode_session_result {\n\tstruct net *net;\n\tu32 if_id;\n};\n\nstruct xfrm_input_afinfo {\n\tu8 family;\n\tbool is_ipip;\n\tint (*callback)(struct sk_buff *, u8, int);\n};\n\nstruct xfrm_kmaddress {\n\txfrm_address_t local;\n\txfrm_address_t remote;\n\tu32 reserved;\n\tu16 family;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_tmpl;\n\nstruct xfrm_selector;\n\nstruct xfrm_migrate;\n\nstruct xfrm_mgr {\n\tstruct list_head list;\n\tint (*notify)(struct xfrm_state *, const struct km_event *);\n\tint (*acquire)(struct xfrm_state *, struct xfrm_tmpl *, struct xfrm_policy *);\n\tstruct xfrm_policy * (*compile_policy)(struct sock *, int, u8 *, int, int *);\n\tint (*new_mapping)(struct xfrm_state *, xfrm_address_t *, __be16);\n\tint (*notify_policy)(struct xfrm_policy *, int, const struct km_event *);\n\tint (*report)(struct net *, u8, struct xfrm_selector *, xfrm_address_t *);\n\tint (*migrate)(const struct xfrm_selector *, u8, u8, const struct xfrm_migrate *, int, const struct xfrm_kmaddress *, const struct xfrm_encap_tmpl *);\n\tbool (*is_alive)(const struct km_event *);\n};\n\nstruct xfrm_migrate {\n\txfrm_address_t old_daddr;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_daddr;\n\txfrm_address_t new_saddr;\n\tu8 proto;\n\tu8 mode;\n\tu16 reserved;\n\tu32 reqid;\n\tu16 old_family;\n\tu16 new_family;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_mode_cbs {\n\tstruct module *owner;\n\tint (*init_state)(struct xfrm_state *);\n\tint (*clone_state)(struct xfrm_state *, struct xfrm_state *);\n\tvoid (*destroy_state)(struct xfrm_state *);\n\tint (*user_init)(struct net *, struct xfrm_state *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*copy_to_user)(struct xfrm_state *, struct sk_buff *);\n\tunsigned int (*sa_len)(const struct xfrm_state *);\n\tu32 (*get_inner_mtu)(struct xfrm_state *, int);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*prepare_output)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_tunnel_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tunion {\n\t\tstruct ip_tunnel *ip4;\n\t\tstruct ip6_tnl *ip6;\n\t} tunnel;\n};\n\nstruct xfrm_mode_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\t__be16 id;\n\t__be16 frag_off;\n\tu8 ihl;\n\tu8 tos;\n\tu8 ttl;\n\tu8 protocol;\n\tu8 optlen;\n\tu8 flow_lbl[3];\n};\n\nstruct xfrm_pol_inexact_key {\n\tpossible_net_t net;\n\tu32 if_id;\n\tu16 family;\n\tu8 dir;\n\tu8 type;\n};\n\nstruct xfrm_pol_inexact_bin {\n\tstruct xfrm_pol_inexact_key k;\n\tstruct rhash_head head;\n\tstruct hlist_head hhead;\n\tseqcount_spinlock_t count;\n\tstruct rb_root root_d;\n\tstruct rb_root root_s;\n\tstruct list_head inexact_bins;\n\tstruct callback_head rcu;\n};\n\nstruct xfrm_pol_inexact_candidates {\n\tstruct hlist_head *res[4];\n};\n\nstruct xfrm_pol_inexact_node {\n\tstruct rb_node node;\n\tunion {\n\t\txfrm_address_t addr;\n\t\tstruct callback_head rcu;\n\t};\n\tu8 prefixlen;\n\tstruct rb_root root;\n\tstruct hlist_head hhead;\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_policy_walk_entry {\n\tstruct list_head all;\n\tu8 dead;\n};\n\nstruct xfrm_policy_queue {\n\tstruct sk_buff_head hold_queue;\n\tstruct timer_list hold_timer;\n\tlong unsigned int timeout;\n};\n\nstruct xfrm_tmpl {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tshort unsigned int encap_family;\n\tu32 reqid;\n\tu8 mode;\n\tu8 share;\n\tu8 optional;\n\tu8 allalgs;\n\tu32 aalgos;\n\tu32 ealgos;\n\tu32 calgos;\n};\n\nstruct xfrm_sec_ctx;\n\nstruct xfrm_policy {\n\tpossible_net_t xp_net;\n\tstruct hlist_node bydst;\n\tstruct hlist_node byidx;\n\tstruct hlist_head state_cache_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tu32 pos;\n\tstruct timer_list timer;\n\tatomic_t genid;\n\tu32 priority;\n\tu32 index;\n\tu32 if_id;\n\tstruct xfrm_mark mark;\n\tstruct xfrm_selector selector;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_policy_walk_entry walk;\n\tstruct xfrm_policy_queue polq;\n\tbool bydst_reinsert;\n\tu8 type;\n\tu8 action;\n\tu8 flags;\n\tu8 xfrm_nr;\n\tu16 family;\n\tstruct xfrm_sec_ctx *security;\n\tstruct xfrm_tmpl xfrm_vec[6];\n\tstruct callback_head rcu;\n\tstruct xfrm_dev_offload xdo;\n};\n\nstruct xfrm_policy_afinfo {\n\tstruct dst_ops *dst_ops;\n\tstruct dst_entry * (*dst_lookup)(const struct xfrm_dst_lookup_params *);\n\tint (*get_saddr)(xfrm_address_t *, const struct xfrm_dst_lookup_params *);\n\tint (*fill_dst)(struct xfrm_dst *, struct net_device *, const struct flowi *);\n\tstruct dst_entry * (*blackhole_route)(struct net *, struct dst_entry *);\n};\n\nstruct xfrm_policy_walk {\n\tstruct xfrm_policy_walk_entry walk;\n\tu8 type;\n\tu32 seq;\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 low;\n\t\t\t__u32 hi;\n\t\t} output;\n\t\tstruct {\n\t\t\t__be32 low;\n\t\t\t__be32 hi;\n\t\t} input;\n\t} seq;\n};\n\nstruct xfrm_spi_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunsigned int daddroff;\n\tunsigned int family;\n\t__be32 seq;\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tunion {\n\t\tstruct hlist_node dev_gclist;\n\t\tstruct hlist_node bysrc;\n\t};\n\tstruct hlist_node byspi;\n\tstruct hlist_node byseq;\n\tstruct hlist_node state_cache;\n\tstruct hlist_node state_cache_input;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tu32 pcpu_num;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint enc_hdr_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\t__be16 new_mapping_sport;\n\tu32 new_mapping;\n\tu32 mapping_maxage;\n\tstruct xfrm_encap_tmpl *encap;\n\tu32 nat_keepalive_interval;\n\ttime64_t nat_keepalive_expiration;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tenum xfrm_replay_mode repl_mode;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_dev_offload xso;\n\tlong int saved_tmo;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n\tu8 dir;\n\tconst struct xfrm_mode_cbs *mode_cbs;\n\tvoid *mode_data;\n};\n\nstruct xfrm_state_afinfo {\n\tu8 family;\n\tu8 proto;\n\tconst struct xfrm_type_offload *type_offload_esp;\n\tconst struct xfrm_type *type_esp;\n\tconst struct xfrm_type *type_ipip;\n\tconst struct xfrm_type *type_ipip6;\n\tconst struct xfrm_type *type_comp;\n\tconst struct xfrm_type *type_ah;\n\tconst struct xfrm_type *type_routing;\n\tconst struct xfrm_type *type_dstopts;\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*transport_finish)(struct sk_buff *, int);\n\tvoid (*local_error)(struct sk_buff *, u32);\n};\n\nstruct xfrm_trans_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tint (*finish)(struct net *, struct sock *, struct sk_buff *);\n\tstruct net *net;\n};\n\nstruct xfrm_trans_tasklet {\n\tstruct work_struct work;\n\tspinlock_t queue_lock;\n\tstruct sk_buff_head queue;\n};\n\nstruct xfrm_translator {\n\tint (*alloc_compat)(struct sk_buff *, const struct nlmsghdr *);\n\tstruct nlmsghdr * (*rcv_msg_compat)(const struct nlmsghdr *, int, const struct nla_policy *, struct netlink_ext_ack *);\n\tint (*xlate_user_policy_sockptr)(u8 **, int);\n\tstruct module *owner;\n};\n\nstruct xfrm_tunnel {\n\tint (*handler)(struct sk_buff *);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm_tunnel *next;\n\tint priority;\n};\n\nstruct xfrm_type {\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *, struct netlink_ext_ack *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n};\n\nstruct xfrm_type_offload {\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nstruct xfrmk_sadinfo {\n\tu32 sadhcnt;\n\tu32 sadhmcnt;\n\tu32 sadcnt;\n};\n\nstruct xfrmk_spdinfo {\n\tu32 incnt;\n\tu32 outcnt;\n\tu32 fwdcnt;\n\tu32 inscnt;\n\tu32 outscnt;\n\tu32 fwdscnt;\n\tu32 spdhcnt;\n\tu32 spdhmcnt;\n};\n\nstruct xfs_acl_entry {\n\t__be32 ae_tag;\n\t__be32 ae_id;\n\t__be16 ae_perm;\n\t__be16 ae_pad;\n};\n\nstruct xfs_acl {\n\t__be32 acl_cnt;\n\tstruct xfs_acl_entry acl_entry[0];\n};\n\nstruct xfs_ag_geometry {\n\tuint32_t ag_number;\n\tuint32_t ag_length;\n\tuint32_t ag_freeblks;\n\tuint32_t ag_icount;\n\tuint32_t ag_ifree;\n\tuint32_t ag_sick;\n\tuint32_t ag_checked;\n\tuint32_t ag_flags;\n\tuint64_t ag_reserved[12];\n};\n\nstruct xfs_ag_resv {\n\txfs_extlen_t ar_orig_reserved;\n\txfs_extlen_t ar_reserved;\n\txfs_extlen_t ar_asked;\n};\n\nstruct xfs_agf {\n\t__be32 agf_magicnum;\n\t__be32 agf_versionnum;\n\t__be32 agf_seqno;\n\t__be32 agf_length;\n\t__be32 agf_bno_root;\n\t__be32 agf_cnt_root;\n\t__be32 agf_rmap_root;\n\t__be32 agf_bno_level;\n\t__be32 agf_cnt_level;\n\t__be32 agf_rmap_level;\n\t__be32 agf_flfirst;\n\t__be32 agf_fllast;\n\t__be32 agf_flcount;\n\t__be32 agf_freeblks;\n\t__be32 agf_longest;\n\t__be32 agf_btreeblks;\n\tuuid_t agf_uuid;\n\t__be32 agf_rmap_blocks;\n\t__be32 agf_refcount_blocks;\n\t__be32 agf_refcount_root;\n\t__be32 agf_refcount_level;\n\t__be64 agf_spare64[14];\n\t__be64 agf_lsn;\n\t__be32 agf_crc;\n\t__be32 agf_spare2;\n};\n\nstruct xfs_agfl {\n\t__be32 agfl_magicnum;\n\t__be32 agfl_seqno;\n\tuuid_t agfl_uuid;\n\t__be64 agfl_lsn;\n\t__be32 agfl_crc;\n} __attribute__((packed));\n\ntypedef void (*aghdr_init_work_f)(struct xfs_mount *, struct xfs_buf *, struct aghdr_init_data *);\n\nstruct xfs_buf_ops;\n\nstruct xfs_aghdr_grow_data {\n\txfs_daddr_t daddr;\n\tsize_t numblks;\n\tconst struct xfs_buf_ops *ops;\n\taghdr_init_work_f work;\n\tconst struct xfs_btree_ops *bc_ops;\n\tbool need_init;\n};\n\nstruct xfs_agi {\n\t__be32 agi_magicnum;\n\t__be32 agi_versionnum;\n\t__be32 agi_seqno;\n\t__be32 agi_length;\n\t__be32 agi_count;\n\t__be32 agi_root;\n\t__be32 agi_level;\n\t__be32 agi_freecount;\n\t__be32 agi_newino;\n\t__be32 agi_dirino;\n\t__be32 agi_unlinked[64];\n\tuuid_t agi_uuid;\n\t__be32 agi_crc;\n\t__be32 agi_pad32;\n\t__be64 agi_lsn;\n\t__be32 agi_free_root;\n\t__be32 agi_free_level;\n\t__be32 agi_iblocks;\n\t__be32 agi_fblocks;\n};\n\nstruct xlog;\n\nstruct xfs_ail {\n\tstruct xlog *ail_log;\n\tstruct task_struct *ail_task;\n\tstruct list_head ail_head;\n\tstruct list_head ail_cursors;\n\tspinlock_t ail_lock;\n\txfs_lsn_t ail_last_pushed_lsn;\n\txfs_lsn_t ail_head_lsn;\n\tint ail_log_flush;\n\tlong unsigned int ail_opstate;\n\tstruct list_head ail_buf_list;\n\twait_queue_head_t ail_empty;\n\txfs_lsn_t ail_target;\n};\n\nstruct xfs_log_item;\n\nstruct xfs_ail_cursor {\n\tstruct list_head list;\n\tstruct xfs_log_item *item;\n};\n\nstruct xfs_owner_info {\n\tuint64_t oi_owner;\n\txfs_fileoff_t oi_offset;\n\tunsigned int oi_flags;\n};\n\nstruct xfs_alloc_arg {\n\tstruct xfs_trans *tp;\n\tstruct xfs_mount *mp;\n\tstruct xfs_buf *agbp;\n\tstruct xfs_perag *pag;\n\txfs_fsblock_t fsbno;\n\txfs_agnumber_t agno;\n\txfs_agblock_t agbno;\n\txfs_extlen_t minlen;\n\txfs_extlen_t maxlen;\n\txfs_extlen_t mod;\n\txfs_extlen_t prod;\n\txfs_extlen_t minleft;\n\txfs_extlen_t total;\n\txfs_extlen_t alignment;\n\txfs_extlen_t minalignslop;\n\txfs_agblock_t min_agbno;\n\txfs_agblock_t max_agbno;\n\txfs_extlen_t len;\n\tint datatype;\n\tchar wasdel;\n\tchar wasfromfl;\n\tbool alloc_minlen_only;\n\tstruct xfs_owner_info oinfo;\n\tenum xfs_ag_resv_type resv;\n};\n\ntypedef struct xfs_alloc_arg xfs_alloc_arg_t;\n\nstruct xfs_defer_pending;\n\nstruct xfs_alloc_autoreap {\n\tstruct xfs_defer_pending *dfp;\n};\n\nstruct xfs_alloc_cur {\n\tstruct xfs_btree_cur *cnt;\n\tstruct xfs_btree_cur *bnolt;\n\tstruct xfs_btree_cur *bnogt;\n\txfs_extlen_t cur_len;\n\txfs_agblock_t rec_bno;\n\txfs_extlen_t rec_len;\n\txfs_agblock_t bno;\n\txfs_extlen_t len;\n\txfs_extlen_t diff;\n\tunsigned int busy_gen;\n\tbool busy;\n};\n\ntypedef int (*xfs_alloc_query_range_fn)(struct xfs_btree_cur *, const struct xfs_alloc_rec_incore *, void *);\n\nstruct xfs_alloc_query_range_info {\n\txfs_alloc_query_range_fn fn;\n\tvoid *priv;\n};\n\ntypedef struct xfs_alloc_rec xfs_alloc_rec_t;\n\nstruct xfs_attr3_icleaf_hdr {\n\tuint32_t forw;\n\tuint32_t back;\n\tuint16_t magic;\n\tuint16_t count;\n\tuint16_t usedbytes;\n\tuint32_t firstused;\n\t__u8 holes;\n\tstruct {\n\t\tuint16_t base;\n\t\tuint16_t size;\n\t} freemap[3];\n};\n\nstruct xfs_da_blkinfo {\n\t__be32 forw;\n\t__be32 back;\n\t__be16 magic;\n\t__be16 pad;\n};\n\nstruct xfs_da3_blkinfo {\n\tstruct xfs_da_blkinfo hdr;\n\t__be32 crc;\n\t__be64 blkno;\n\t__be64 lsn;\n\tuuid_t uuid;\n\t__be64 owner;\n};\n\nstruct xfs_attr_leaf_map {\n\t__be16 base;\n\t__be16 size;\n};\n\nstruct xfs_attr3_leaf_hdr {\n\tstruct xfs_da3_blkinfo info;\n\t__be16 count;\n\t__be16 usedbytes;\n\t__be16 firstused;\n\t__u8 holes;\n\t__u8 pad1;\n\tstruct xfs_attr_leaf_map freemap[3];\n\t__be32 pad2;\n};\n\nstruct xfs_attr_leaf_entry {\n\t__be32 hashval;\n\t__be16 nameidx;\n\t__u8 flags;\n\t__u8 pad2;\n};\n\nstruct xfs_attr3_leafblock {\n\tstruct xfs_attr3_leaf_hdr hdr;\n\tstruct xfs_attr_leaf_entry entries[0];\n};\n\nstruct xfs_attr3_rmt_hdr {\n\t__be32 rm_magic;\n\t__be32 rm_offset;\n\t__be32 rm_bytes;\n\t__be32 rm_crc;\n\tuuid_t rm_uuid;\n\t__be64 rm_owner;\n\t__be64 rm_blkno;\n\t__be64 rm_lsn;\n};\n\nstruct xfs_attri_log_nameval;\n\nstruct xfs_attr_intent {\n\tstruct list_head xattri_list;\n\tstruct xfs_da_state *xattri_da_state;\n\tstruct xfs_da_args *xattri_da_args;\n\tstruct xfs_attri_log_nameval *xattri_nameval;\n\tenum xfs_delattr_state xattri_dela_state;\n\tunsigned int xattri_op_flags;\n\txfs_dablk_t xattri_lblkno;\n\tint xattri_blkcnt;\n\tstruct xfs_bmbt_irec xattri_map;\n};\n\ntypedef struct xfs_attr_leaf_entry xfs_attr_leaf_entry_t;\n\ntypedef struct xfs_da_blkinfo xfs_da_blkinfo_t;\n\ntypedef struct xfs_attr_leaf_map xfs_attr_leaf_map_t;\n\nstruct xfs_attr_leaf_hdr {\n\txfs_da_blkinfo_t info;\n\t__be16 count;\n\t__be16 usedbytes;\n\t__be16 firstused;\n\t__u8 holes;\n\t__u8 pad1;\n\txfs_attr_leaf_map_t freemap[3];\n};\n\ntypedef struct xfs_attr_leaf_hdr xfs_attr_leaf_hdr_t;\n\nstruct xfs_attr_leaf_name_local {\n\t__be16 valuelen;\n\t__u8 namelen;\n\t__u8 nameval[0];\n};\n\ntypedef struct xfs_attr_leaf_name_local xfs_attr_leaf_name_local_t;\n\nstruct xfs_attr_leaf_name_remote {\n\t__be32 valueblk;\n\t__be32 valuelen;\n\t__u8 namelen;\n\t__u8 name[0];\n};\n\ntypedef struct xfs_attr_leaf_name_remote xfs_attr_leaf_name_remote_t;\n\nstruct xfs_attr_leafblock {\n\txfs_attr_leaf_hdr_t hdr;\n\txfs_attr_leaf_entry_t entries[0];\n};\n\ntypedef struct xfs_attr_leafblock xfs_attr_leafblock_t;\n\nstruct xfs_attrlist_cursor_kern {\n\t__u32 hashval;\n\t__u32 blkno;\n\t__u32 offset;\n\t__u16 pad1;\n\t__u8 pad2;\n\t__u8 initted;\n};\n\nstruct xfs_attr_list_context;\n\ntypedef void (*put_listent_func_t)(struct xfs_attr_list_context *, int, unsigned char *, int, void *, int);\n\nstruct xfs_attr_list_context {\n\tstruct xfs_trans *tp;\n\tstruct xfs_inode *dp;\n\tstruct xfs_attrlist_cursor_kern cursor;\n\tvoid *buffer;\n\tint seen_enough;\n\tbool allow_incomplete;\n\tssize_t count;\n\tint dupcnt;\n\tint bufsize;\n\tint firstu;\n\tunsigned int attr_filter;\n\tint resynch;\n\tput_listent_func_t put_listent;\n\tint index;\n};\n\nstruct xfs_attr_multiop {\n\t__u32 am_opcode;\n\t__s32 am_error;\n\tvoid *am_attrname;\n\tvoid *am_attrvalue;\n\t__u32 am_length;\n\t__u32 am_flags;\n};\n\ntypedef struct xfs_attr_multiop xfs_attr_multiop_t;\n\nstruct xfs_attr_sf_entry {\n\t__u8 namelen;\n\t__u8 valuelen;\n\t__u8 flags;\n\t__u8 nameval[0];\n};\n\nstruct xfs_attr_sf_hdr {\n\t__be16 totsize;\n\t__u8 count;\n\t__u8 padding;\n};\n\nstruct xfs_attr_sf_sort {\n\tuint8_t entno;\n\tuint8_t namelen;\n\tuint8_t valuelen;\n\tuint8_t flags;\n\txfs_dahash_t hash;\n\tunsigned char *name;\n\tvoid *value;\n};\n\ntypedef struct xfs_attr_sf_sort xfs_attr_sf_sort_t;\n\nstruct xfs_attrd_log_format {\n\tuint16_t alfd_type;\n\tuint16_t alfd_size;\n\tuint32_t __pad;\n\tuint64_t alfd_alf_id;\n};\n\nstruct xfs_item_ops;\n\nstruct xfs_log_vec;\n\nstruct xfs_log_item {\n\tstruct list_head li_ail;\n\tstruct list_head li_trans;\n\txfs_lsn_t li_lsn;\n\tstruct xlog *li_log;\n\tstruct xfs_ail *li_ailp;\n\tuint li_type;\n\tlong unsigned int li_flags;\n\tstruct xfs_buf *li_buf;\n\tstruct list_head li_bio_list;\n\tconst struct xfs_item_ops *li_ops;\n\tstruct list_head li_cil;\n\tstruct xfs_log_vec *li_lv;\n\tstruct xfs_log_vec *li_lv_shadow;\n\txfs_csn_t li_seq;\n\tuint32_t li_order_id;\n};\n\nstruct xfs_attri_log_item;\n\nstruct xfs_attrd_log_item {\n\tstruct xfs_log_item attrd_item;\n\tstruct xfs_attri_log_item *attrd_attrip;\n\tstruct xfs_attrd_log_format attrd_format;\n};\n\nstruct xfs_attri_log_format {\n\tuint16_t alfi_type;\n\tuint16_t alfi_size;\n\tuint32_t alfi_igen;\n\tuint64_t alfi_id;\n\tuint64_t alfi_ino;\n\tuint32_t alfi_op_flags;\n\tunion {\n\t\tuint32_t alfi_name_len;\n\t\tstruct {\n\t\t\tuint16_t alfi_old_name_len;\n\t\t\tuint16_t alfi_new_name_len;\n\t\t};\n\t};\n\tuint32_t alfi_value_len;\n\tuint32_t alfi_attr_filter;\n};\n\nstruct xfs_attri_log_item {\n\tstruct xfs_log_item attri_item;\n\tatomic_t attri_refcount;\n\tstruct xfs_attri_log_nameval *attri_nameval;\n\tstruct xfs_attri_log_format attri_format;\n};\n\nstruct xfs_attri_log_nameval {\n\tstruct kvec name;\n\tstruct kvec new_name;\n\tstruct kvec value;\n\tstruct kvec new_value;\n\trefcount_t refcount;\n};\n\nstruct xfs_attrlist {\n\t__s32 al_count;\n\t__s32 al_more;\n\t__s32 al_offset[0];\n};\n\nstruct xfs_attrlist_cursor {\n\t__u32 opaque[4];\n};\n\nstruct xfs_attrlist_ent {\n\t__u32 a_valuelen;\n\tchar a_name[0];\n};\n\nstruct xfs_bmalloca {\n\tstruct xfs_trans *tp;\n\tstruct xfs_inode *ip;\n\tstruct xfs_bmbt_irec prev;\n\tstruct xfs_bmbt_irec got;\n\txfs_fileoff_t offset;\n\txfs_extlen_t length;\n\txfs_fsblock_t blkno;\n\tstruct xfs_btree_cur *cur;\n\tstruct xfs_iext_cursor icur;\n\tint nallocs;\n\tint logflags;\n\txfs_extlen_t total;\n\txfs_extlen_t minlen;\n\txfs_extlen_t minleft;\n\tbool eof;\n\tbool wasdel;\n\tbool aeof;\n\tbool conv;\n\tint datatype;\n\tuint32_t flags;\n};\n\nstruct xfs_group;\n\nstruct xfs_bmap_intent {\n\tstruct list_head bi_list;\n\tenum xfs_bmap_intent_type bi_type;\n\tint bi_whichfork;\n\tstruct xfs_inode *bi_owner;\n\tstruct xfs_group *bi_group;\n\tstruct xfs_bmbt_irec bi_bmap;\n};\n\ntypedef int (*xfs_bmap_query_range_fn)(struct xfs_btree_cur *, struct xfs_bmbt_irec *, void *);\n\nstruct xfs_bmap_query_range {\n\txfs_bmap_query_range_fn fn;\n\tvoid *priv;\n};\n\ntypedef struct xfs_bmbt_irec xfs_bmbt_irec_t;\n\ntypedef struct xfs_bmbt_key xfs_bmbt_key_t;\n\nstruct xfs_bmdr_block {\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n};\n\ntypedef struct xfs_bmdr_block xfs_bmdr_block_t;\n\nstruct xfs_bstime {\n\t__kernel_long_t tv_sec;\n\t__s32 tv_nsec;\n};\n\ntypedef struct xfs_bstime xfs_bstime_t;\n\nstruct xfs_bstat {\n\t__u64 bs_ino;\n\t__u16 bs_mode;\n\t__u16 bs_nlink;\n\t__u32 bs_uid;\n\t__u32 bs_gid;\n\t__u32 bs_rdev;\n\t__s32 bs_blksize;\n\t__s64 bs_size;\n\txfs_bstime_t bs_atime;\n\txfs_bstime_t bs_mtime;\n\txfs_bstime_t bs_ctime;\n\tint64_t bs_blocks;\n\t__u32 bs_xflags;\n\t__s32 bs_extsize;\n\t__s32 bs_extents;\n\t__u32 bs_gen;\n\t__u16 bs_projid_lo;\n\t__u16 bs_forkoff;\n\t__u16 bs_projid_hi;\n\tuint16_t bs_sick;\n\tuint16_t bs_checked;\n\tunsigned char bs_pad[2];\n\t__u32 bs_cowextsize;\n\t__u32 bs_dmevmask;\n\t__u16 bs_dmstate;\n\t__u16 bs_aextents;\n};\n\nstruct xfs_ibulk;\n\nstruct xfs_bulkstat;\n\ntypedef int (*bulkstat_one_fmt_pf)(struct xfs_ibulk *, const struct xfs_bulkstat *);\n\nstruct xfs_bstat_chunk {\n\tbulkstat_one_fmt_pf formatter;\n\tstruct xfs_ibulk *breq;\n\tstruct xfs_bulkstat *buf;\n};\n\nstruct xfs_btree_block;\n\ntypedef int (*xfs_btree_bload_get_records_fn)(struct xfs_btree_cur *, unsigned int, struct xfs_btree_block *, unsigned int, void *);\n\ntypedef int (*xfs_btree_bload_claim_block_fn)(struct xfs_btree_cur *, union xfs_btree_ptr *, void *);\n\ntypedef size_t (*xfs_btree_bload_iroot_size_fn)(struct xfs_btree_cur *, unsigned int, unsigned int, void *);\n\nstruct xfs_btree_bload {\n\txfs_btree_bload_get_records_fn get_records;\n\txfs_btree_bload_claim_block_fn claim_block;\n\txfs_btree_bload_iroot_size_fn iroot_size;\n\tuint64_t nr_records;\n\tint leaf_slack;\n\tint node_slack;\n\tuint64_t nr_blocks;\n\tunsigned int btree_height;\n\tuint16_t max_dirty;\n\tuint16_t nr_dirty;\n};\n\nstruct xfs_btree_block_shdr {\n\t__be32 bb_leftsib;\n\t__be32 bb_rightsib;\n\t__be64 bb_blkno;\n\t__be64 bb_lsn;\n\tuuid_t bb_uuid;\n\t__be32 bb_owner;\n\t__le32 bb_crc;\n};\n\nstruct xfs_btree_block_lhdr {\n\t__be64 bb_leftsib;\n\t__be64 bb_rightsib;\n\t__be64 bb_blkno;\n\t__be64 bb_lsn;\n\tuuid_t bb_uuid;\n\t__be64 bb_owner;\n\t__le32 bb_crc;\n\t__be32 bb_pad;\n};\n\nstruct xfs_btree_block {\n\t__be32 bb_magic;\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n\tunion {\n\t\tstruct xfs_btree_block_shdr s;\n\t\tstruct xfs_btree_block_lhdr l;\n\t} bb_u;\n};\n\nstruct xfs_btree_block_change_owner_info {\n\tuint64_t new_owner;\n\tstruct list_head *buffer_list;\n};\n\nstruct xfs_inobt_rec_incore {\n\txfs_agino_t ir_startino;\n\tuint16_t ir_holemask;\n\tuint8_t ir_count;\n\tuint8_t ir_freecount;\n\txfs_inofree_t ir_free;\n};\n\nunion xfs_btree_irec {\n\tstruct xfs_alloc_rec_incore a;\n\tstruct xfs_bmbt_irec b;\n\tstruct xfs_inobt_rec_incore i;\n\tstruct xfs_rmap_irec r;\n\tstruct xfs_refcount_irec rc;\n};\n\nstruct xfs_btree_level {\n\tstruct xfs_buf *bp;\n\tuint16_t ptr;\n\tuint16_t ra;\n};\n\nstruct xfs_btree_cur {\n\tstruct xfs_trans *bc_tp;\n\tstruct xfs_mount *bc_mp;\n\tconst struct xfs_btree_ops *bc_ops;\n\tstruct kmem_cache *bc_cache;\n\tunsigned int bc_flags;\n\tunion xfs_btree_irec bc_rec;\n\tuint8_t bc_nlevels;\n\tuint8_t bc_maxlevels;\n\tstruct xfs_group *bc_group;\n\tunion {\n\t\tstruct {\n\t\t\tstruct xfs_inode *ip;\n\t\t\tshort int forksize;\n\t\t\tchar whichfork;\n\t\t\tstruct xbtree_ifakeroot *ifake;\n\t\t} bc_ino;\n\t\tstruct {\n\t\t\tstruct xfs_buf *agbp;\n\t\t\tstruct xbtree_afakeroot *afake;\n\t\t} bc_ag;\n\t\tstruct {\n\t\t\tstruct xfbtree *xfbtree;\n\t\t} bc_mem;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tint allocated;\n\t\t} bc_bmap;\n\t\tstruct {\n\t\t\tunsigned int nr_ops;\n\t\t\tunsigned int shape_changes;\n\t\t} bc_refc;\n\t};\n\tstruct xfs_btree_level bc_levels[0];\n};\n\nstruct xfs_btree_has_records {\n\tunion xfs_btree_key start_key;\n\tunion xfs_btree_key end_key;\n\tconst union xfs_btree_key *key_mask;\n\tunion xfs_btree_key high_key;\n\tenum xbtree_recpacking outcome;\n};\n\nstruct xfs_btree_ops {\n\tconst char *name;\n\tenum xfs_btree_type type;\n\tunsigned int geom_flags;\n\tsize_t key_len;\n\tsize_t ptr_len;\n\tsize_t rec_len;\n\tunsigned int lru_refs;\n\tunsigned int statoff;\n\tunsigned int sick_mask;\n\tstruct xfs_btree_cur * (*dup_cursor)(struct xfs_btree_cur *);\n\tvoid (*update_cursor)(struct xfs_btree_cur *, struct xfs_btree_cur *);\n\tvoid (*set_root)(struct xfs_btree_cur *, const union xfs_btree_ptr *, int);\n\tint (*alloc_block)(struct xfs_btree_cur *, const union xfs_btree_ptr *, union xfs_btree_ptr *, int *);\n\tint (*free_block)(struct xfs_btree_cur *, struct xfs_buf *);\n\tint (*get_minrecs)(struct xfs_btree_cur *, int);\n\tint (*get_maxrecs)(struct xfs_btree_cur *, int);\n\tint (*get_dmaxrecs)(struct xfs_btree_cur *, int);\n\tvoid (*init_key_from_rec)(union xfs_btree_key *, const union xfs_btree_rec *);\n\tvoid (*init_rec_from_cur)(struct xfs_btree_cur *, union xfs_btree_rec *);\n\tvoid (*init_ptr_from_cur)(struct xfs_btree_cur *, union xfs_btree_ptr *);\n\tvoid (*init_high_key_from_rec)(union xfs_btree_key *, const union xfs_btree_rec *);\n\tint (*cmp_key_with_cur)(struct xfs_btree_cur *, const union xfs_btree_key *);\n\tint (*cmp_two_keys)(struct xfs_btree_cur *, const union xfs_btree_key *, const union xfs_btree_key *, const union xfs_btree_key *);\n\tconst struct xfs_buf_ops *buf_ops;\n\tint (*keys_inorder)(struct xfs_btree_cur *, const union xfs_btree_key *, const union xfs_btree_key *);\n\tint (*recs_inorder)(struct xfs_btree_cur *, const union xfs_btree_rec *, const union xfs_btree_rec *);\n\tenum xbtree_key_contig (*keys_contiguous)(struct xfs_btree_cur *, const union xfs_btree_key *, const union xfs_btree_key *, const union xfs_btree_key *);\n\tstruct xfs_btree_block * (*broot_realloc)(struct xfs_btree_cur *, unsigned int);\n};\n\nstruct xfs_btree_split_args {\n\tstruct xfs_btree_cur *cur;\n\tint level;\n\tunion xfs_btree_ptr *ptrp;\n\tunion xfs_btree_key *key;\n\tstruct xfs_btree_cur **curp;\n\tint *stat;\n\tint result;\n\tbool kswapd;\n\tstruct completion *done;\n\tstruct work_struct work;\n};\n\nstruct xfs_bud_log_format {\n\tuint16_t bud_type;\n\tuint16_t bud_size;\n\tuint32_t __pad;\n\tuint64_t bud_bui_id;\n};\n\nstruct xfs_bui_log_item;\n\nstruct xfs_bud_log_item {\n\tstruct xfs_log_item bud_item;\n\tstruct xfs_bui_log_item *bud_buip;\n\tstruct xfs_bud_log_format bud_format;\n};\n\nstruct xfs_buf_map {\n\txfs_daddr_t bm_bn;\n\tint bm_len;\n\tunsigned int bm_flags;\n};\n\nstruct xfs_buf_log_item;\n\nstruct xfs_buf {\n\tstruct rhash_head b_rhash_head;\n\txfs_daddr_t b_rhash_key;\n\tint b_length;\n\tunsigned int b_hold;\n\tatomic_t b_lru_ref;\n\txfs_buf_flags_t b_flags;\n\tstruct semaphore b_sema;\n\tstruct list_head b_lru;\n\tspinlock_t b_lock;\n\tunsigned int b_state;\n\twait_queue_head_t b_waiters;\n\tstruct list_head b_list;\n\tstruct xfs_perag *b_pag;\n\tstruct xfs_mount *b_mount;\n\tstruct xfs_buftarg *b_target;\n\tvoid *b_addr;\n\tstruct work_struct b_ioend_work;\n\tstruct completion b_iowait;\n\tstruct xfs_buf_log_item *b_log_item;\n\tstruct list_head b_li_list;\n\tstruct xfs_trans *b_transp;\n\tstruct xfs_buf_map *b_maps;\n\tstruct xfs_buf_map __b_map;\n\tint b_map_count;\n\tatomic_t b_pin_count;\n\tint b_error;\n\tvoid (*b_iodone)(struct xfs_buf *);\n\tint b_retries;\n\tlong unsigned int b_first_retry_time;\n\tint b_last_error;\n\tconst struct xfs_buf_ops *b_ops;\n\tstruct callback_head b_rcu;\n};\n\nstruct xfs_buf_cache {\n\tstruct rhashtable bc_hash;\n};\n\nstruct xfs_buf_cancel {\n\txfs_daddr_t bc_blkno;\n\tuint bc_len;\n\tint bc_refcount;\n\tstruct list_head bc_list;\n};\n\nstruct xfs_buf_log_format {\n\tshort unsigned int blf_type;\n\tshort unsigned int blf_size;\n\tshort unsigned int blf_flags;\n\tshort unsigned int blf_len;\n\tint64_t blf_blkno;\n\tunsigned int blf_map_size;\n\tunsigned int blf_data_map[17];\n};\n\nstruct xfs_buf_log_item {\n\tstruct xfs_log_item bli_item;\n\tstruct xfs_buf *bli_buf;\n\tunsigned int bli_flags;\n\tunsigned int bli_recur;\n\tatomic_t bli_refcount;\n\tint bli_format_count;\n\tstruct xfs_buf_log_format *bli_formats;\n\tstruct xfs_buf_log_format __bli_format;\n};\n\nstruct xfs_buf_ops {\n\tchar *name;\n\tunion {\n\t\t__be32 magic[2];\n\t\t__be16 magic16[2];\n\t};\n\tvoid (*verify_read)(struct xfs_buf *);\n\tvoid (*verify_write)(struct xfs_buf *);\n\txfs_failaddr_t (*verify_struct)(struct xfs_buf *);\n};\n\nstruct xfs_buftarg {\n\tdev_t bt_dev;\n\tstruct block_device *bt_bdev;\n\tstruct dax_device *bt_daxdev;\n\tstruct file *bt_file;\n\tu64 bt_dax_part_off;\n\tstruct xfs_mount *bt_mount;\n\tunsigned int bt_meta_sectorsize;\n\tsize_t bt_meta_sectormask;\n\tsize_t bt_logical_sectorsize;\n\tsize_t bt_logical_sectormask;\n\txfs_daddr_t bt_nr_sectors;\n\tstruct shrinker *bt_shrinker;\n\tstruct list_lru bt_lru;\n\tstruct percpu_counter bt_readahead_count;\n\tstruct ratelimit_state bt_ioerror_rl;\n\tunsigned int bt_awu_min;\n\tunsigned int bt_awu_max;\n\tstruct xfs_buf_cache bt_cache[0];\n};\n\nstruct xfs_map_extent {\n\tuint64_t me_owner;\n\tuint64_t me_startblock;\n\tuint64_t me_startoff;\n\tuint32_t me_len;\n\tuint32_t me_flags;\n};\n\nstruct xfs_bui_log_format {\n\tuint16_t bui_type;\n\tuint16_t bui_size;\n\tuint32_t bui_nextents;\n\tuint64_t bui_id;\n\tstruct xfs_map_extent bui_extents[0];\n};\n\nstruct xfs_bui_log_item {\n\tstruct xfs_log_item bui_item;\n\tatomic_t bui_refcount;\n\tatomic_t bui_next_extent;\n\tstruct xfs_bui_log_format bui_format;\n};\n\nstruct xfs_bulk_ireq {\n\tuint64_t ino;\n\tuint32_t flags;\n\tuint32_t icount;\n\tuint32_t ocount;\n\tuint32_t agno;\n\tuint64_t reserved[5];\n};\n\nstruct xfs_bulkstat {\n\tuint64_t bs_ino;\n\tuint64_t bs_size;\n\tuint64_t bs_blocks;\n\tuint64_t bs_xflags;\n\tint64_t bs_atime;\n\tint64_t bs_mtime;\n\tint64_t bs_ctime;\n\tint64_t bs_btime;\n\tuint32_t bs_gen;\n\tuint32_t bs_uid;\n\tuint32_t bs_gid;\n\tuint32_t bs_projectid;\n\tuint32_t bs_atime_nsec;\n\tuint32_t bs_mtime_nsec;\n\tuint32_t bs_ctime_nsec;\n\tuint32_t bs_btime_nsec;\n\tuint32_t bs_blksize;\n\tuint32_t bs_rdev;\n\tuint32_t bs_cowextsize_blks;\n\tuint32_t bs_extsize_blks;\n\tuint32_t bs_nlink;\n\tuint32_t bs_extents;\n\tuint32_t bs_aextents;\n\tuint16_t bs_version;\n\tuint16_t bs_forkoff;\n\tuint16_t bs_sick;\n\tuint16_t bs_checked;\n\tuint16_t bs_mode;\n\tuint16_t bs_pad2;\n\tuint64_t bs_extents64;\n\tuint64_t bs_pad[6];\n};\n\nstruct xfs_bulkstat_req {\n\tstruct xfs_bulk_ireq hdr;\n\tstruct xfs_bulkstat bulkstat[0];\n};\n\nstruct xfs_busy_extents {\n\tstruct list_head extent_list;\n\tstruct work_struct endio_work;\n\tvoid *owner;\n};\n\nstruct xfs_cil_ctx;\n\nstruct xfs_cil {\n\tstruct xlog *xc_log;\n\tlong unsigned int xc_flags;\n\tatomic_t xc_iclog_hdrs;\n\tstruct workqueue_struct *xc_push_wq;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rw_semaphore xc_ctx_lock;\n\tstruct xfs_cil_ctx *xc_ctx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t xc_push_lock;\n\txfs_csn_t xc_push_seq;\n\tbool xc_push_commit_stable;\n\tstruct list_head xc_committing;\n\twait_queue_head_t xc_commit_wait;\n\twait_queue_head_t xc_start_wait;\n\txfs_csn_t xc_current_sequence;\n\twait_queue_head_t xc_push_wait;\n\tvoid *xc_pcp;\n};\n\nstruct xlog_in_core;\n\nstruct xlog_ticket;\n\nstruct xfs_cil_ctx {\n\tstruct xfs_cil *cil;\n\txfs_csn_t sequence;\n\txfs_lsn_t start_lsn;\n\txfs_lsn_t commit_lsn;\n\tstruct xlog_in_core *commit_iclog;\n\tstruct xlog_ticket *ticket;\n\tatomic_t space_used;\n\tstruct xfs_busy_extents busy_extents;\n\tstruct list_head log_items;\n\tstruct list_head lv_chain;\n\tstruct list_head iclog_entry;\n\tstruct list_head committing;\n\tstruct work_struct push_work;\n\tatomic_t order_id;\n\tstruct cpumask cil_pcpmask;\n};\n\nstruct xfs_commit_range {\n\t__s32 file1_fd;\n\t__u32 pad;\n\t__u64 file1_offset;\n\t__u64 file2_offset;\n\t__u64 length;\n\t__u64 flags;\n\t__u64 file2_freshness[6];\n};\n\nstruct xfs_fsid {\n\t__u32 val[2];\n};\n\ntypedef struct xfs_fsid xfs_fsid_t;\n\nstruct xfs_commit_range_fresh {\n\txfs_fsid_t fsid;\n\t__u64 file2_ino;\n\t__s64 file2_mtime;\n\t__s64 file2_ctime;\n\t__s32 file2_mtime_nsec;\n\t__s32 file2_ctime_nsec;\n\t__u32 file2_gen;\n\t__u32 magic;\n};\n\nstruct xfs_cud_log_format {\n\tuint16_t cud_type;\n\tuint16_t cud_size;\n\tuint32_t __pad;\n\tuint64_t cud_cui_id;\n};\n\nstruct xfs_cui_log_item;\n\nstruct xfs_cud_log_item {\n\tstruct xfs_log_item cud_item;\n\tstruct xfs_cui_log_item *cud_cuip;\n\tstruct xfs_cud_log_format cud_format;\n};\n\nstruct xfs_phys_extent {\n\tuint64_t pe_startblock;\n\tuint32_t pe_len;\n\tuint32_t pe_flags;\n};\n\nstruct xfs_cui_log_format {\n\tuint16_t cui_type;\n\tuint16_t cui_size;\n\tuint32_t cui_nextents;\n\tuint64_t cui_id;\n\tstruct xfs_phys_extent cui_extents[0];\n};\n\nstruct xfs_cui_log_item {\n\tstruct xfs_log_item cui_item;\n\tatomic_t cui_refcount;\n\tatomic_t cui_next_extent;\n\tstruct xfs_cui_log_format cui_format;\n};\n\nstruct xfs_da_node_entry;\n\nstruct xfs_da3_icnode_hdr {\n\tuint32_t forw;\n\tuint32_t back;\n\tuint16_t magic;\n\tuint16_t count;\n\tuint16_t level;\n\tstruct xfs_da_node_entry *btree;\n};\n\nstruct xfs_da3_node_hdr {\n\tstruct xfs_da3_blkinfo info;\n\t__be16 __count;\n\t__be16 __level;\n\t__be32 __pad32;\n};\n\nstruct xfs_da_node_entry {\n\t__be32 hashval;\n\t__be32 before;\n};\n\nstruct xfs_da3_intnode {\n\tstruct xfs_da3_node_hdr hdr;\n\tstruct xfs_da_node_entry __btree[0];\n};\n\ntypedef struct xfs_da_args xfs_da_args_t;\n\nstruct xfs_da_geometry {\n\tunsigned int blksize;\n\tunsigned int fsbcount;\n\tuint8_t fsblog;\n\tuint8_t blklog;\n\tunsigned int node_hdr_size;\n\tunsigned int node_ents;\n\tunsigned int magicpct;\n\txfs_dablk_t datablk;\n\tunsigned int leaf_hdr_size;\n\tunsigned int leaf_max_ents;\n\txfs_dablk_t leafblk;\n\tunsigned int free_hdr_size;\n\tunsigned int free_max_bests;\n\txfs_dablk_t freeblk;\n\txfs_extnum_t max_extents;\n\txfs_dir2_data_aoff_t data_first_offset;\n\tsize_t data_entry_offset;\n};\n\nstruct xfs_da_node_hdr {\n\tstruct xfs_da_blkinfo info;\n\t__be16 __count;\n\t__be16 __level;\n};\n\nstruct xfs_da_intnode {\n\tstruct xfs_da_node_hdr hdr;\n\tstruct xfs_da_node_entry __btree[0];\n};\n\ntypedef struct xfs_da_intnode xfs_da_intnode_t;\n\nstruct xfs_da_state_blk {\n\tstruct xfs_buf *bp;\n\txfs_dablk_t blkno;\n\txfs_daddr_t disk_blkno;\n\tint index;\n\txfs_dahash_t hashval;\n\tint magic;\n};\n\ntypedef struct xfs_da_state_blk xfs_da_state_blk_t;\n\nstruct xfs_da_state_path {\n\tint active;\n\txfs_da_state_blk_t blk[5];\n};\n\ntypedef struct xfs_da_state_path xfs_da_state_path_t;\n\nstruct xfs_da_state {\n\txfs_da_args_t *args;\n\tstruct xfs_mount *mp;\n\txfs_da_state_path_t path;\n\txfs_da_state_path_t altpath;\n\tunsigned char inleaf;\n\tunsigned char extravalid;\n\tunsigned char extraafter;\n\txfs_da_state_blk_t extrablk;\n};\n\ntypedef struct xfs_da_state xfs_da_state_t;\n\nstruct xfs_quota_limits {\n\txfs_qcnt_t hard;\n\txfs_qcnt_t soft;\n\ttime64_t time;\n};\n\nstruct xfs_def_quota {\n\tstruct xfs_quota_limits blk;\n\tstruct xfs_quota_limits ino;\n\tstruct xfs_quota_limits rtb;\n};\n\nstruct xfs_defer_resources {\n\tstruct xfs_buf *dr_bp[2];\n\tstruct xfs_inode *dr_ip[5];\n\tshort unsigned int dr_bufs;\n\tshort unsigned int dr_ordered;\n\tshort unsigned int dr_inos;\n};\n\nstruct xfs_defer_capture {\n\tstruct list_head dfc_list;\n\tstruct list_head dfc_dfops;\n\tunsigned int dfc_tpflags;\n\tunsigned int dfc_blkres;\n\tunsigned int dfc_rtxres;\n\tunsigned int dfc_logres;\n\tstruct xfs_defer_resources dfc_held;\n};\n\nstruct xfs_defer_drain {\n\tatomic_t dr_count;\n\tstruct wait_queue_head dr_waiters;\n};\n\nstruct xfs_defer_op_type {\n\tconst char *name;\n\tunsigned int max_items;\n\tstruct xfs_log_item * (*create_intent)(struct xfs_trans *, struct list_head *, unsigned int, bool);\n\tvoid (*abort_intent)(struct xfs_log_item *);\n\tstruct xfs_log_item * (*create_done)(struct xfs_trans *, struct xfs_log_item *, unsigned int);\n\tint (*finish_item)(struct xfs_trans *, struct xfs_log_item *, struct list_head *, struct xfs_btree_cur **);\n\tvoid (*finish_cleanup)(struct xfs_trans *, struct xfs_btree_cur *, int);\n\tvoid (*cancel_item)(struct list_head *);\n\tint (*recover_work)(struct xfs_defer_pending *, struct list_head *);\n\tstruct xfs_log_item * (*relog_intent)(struct xfs_trans *, struct xfs_log_item *, struct xfs_log_item *);\n};\n\nstruct xfs_defer_pending {\n\tstruct list_head dfp_list;\n\tstruct list_head dfp_work;\n\tstruct xfs_log_item *dfp_intent;\n\tstruct xfs_log_item *dfp_done;\n\tconst struct xfs_defer_op_type *dfp_ops;\n\tunsigned int dfp_count;\n\tunsigned int dfp_flags;\n};\n\nstruct xfs_dinode {\n\t__be16 di_magic;\n\t__be16 di_mode;\n\t__u8 di_version;\n\t__u8 di_format;\n\t__be16 di_metatype;\n\t__be32 di_uid;\n\t__be32 di_gid;\n\t__be32 di_nlink;\n\t__be16 di_projid_lo;\n\t__be16 di_projid_hi;\n\tunion {\n\t\t__be64 di_big_nextents;\n\t\t__be64 di_v3_pad;\n\t\tstruct {\n\t\t\t__u8 di_v2_pad[6];\n\t\t\t__be16 di_flushiter;\n\t\t};\n\t};\n\txfs_timestamp_t di_atime;\n\txfs_timestamp_t di_mtime;\n\txfs_timestamp_t di_ctime;\n\t__be64 di_size;\n\t__be64 di_nblocks;\n\t__be32 di_extsize;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 di_nextents;\n\t\t\t__be16 di_anextents;\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\t__be32 di_big_anextents;\n\t\t\t__be16 di_nrext64_pad;\n\t\t} __attribute__((packed));\n\t};\n\t__u8 di_forkoff;\n\t__s8 di_aformat;\n\t__be32 di_dmevmask;\n\t__be16 di_dmstate;\n\t__be16 di_flags;\n\t__be32 di_gen;\n\t__be32 di_next_unlinked;\n\t__le32 di_crc;\n\t__be64 di_changecount;\n\t__be64 di_lsn;\n\t__be64 di_flags2;\n\tunion {\n\t\t__be32 di_cowextsize;\n\t\t__be32 di_used_blocks;\n\t};\n\t__u8 di_pad2[12];\n\txfs_timestamp_t di_crtime;\n\t__be64 di_ino;\n\tuuid_t di_uuid;\n};\n\nstruct xfs_dir2_block_tail {\n\t__be32 count;\n\t__be32 stale;\n};\n\ntypedef struct xfs_dir2_block_tail xfs_dir2_block_tail_t;\n\nstruct xfs_dir2_data_entry {\n\t__be64 inumber;\n\t__u8 namelen;\n\t__u8 name[0];\n};\n\ntypedef struct xfs_dir2_data_entry xfs_dir2_data_entry_t;\n\nstruct xfs_dir2_data_free {\n\t__be16 offset;\n\t__be16 length;\n};\n\ntypedef struct xfs_dir2_data_free xfs_dir2_data_free_t;\n\nstruct xfs_dir2_data_hdr {\n\t__be32 magic;\n\txfs_dir2_data_free_t bestfree[3];\n};\n\ntypedef struct xfs_dir2_data_hdr xfs_dir2_data_hdr_t;\n\nstruct xfs_dir2_data_unused {\n\t__be16 freetag;\n\t__be16 length;\n\t__be16 tag;\n};\n\ntypedef struct xfs_dir2_data_unused xfs_dir2_data_unused_t;\n\nstruct xfs_dir2_free_hdr {\n\t__be32 magic;\n\t__be32 firstdb;\n\t__be32 nvalid;\n\t__be32 nused;\n};\n\ntypedef struct xfs_dir2_free_hdr xfs_dir2_free_hdr_t;\n\nstruct xfs_dir2_free {\n\txfs_dir2_free_hdr_t hdr;\n\t__be16 bests[0];\n};\n\ntypedef struct xfs_dir2_free xfs_dir2_free_t;\n\nstruct xfs_dir2_leaf_hdr {\n\txfs_da_blkinfo_t info;\n\t__be16 count;\n\t__be16 stale;\n};\n\ntypedef struct xfs_dir2_leaf_hdr xfs_dir2_leaf_hdr_t;\n\nstruct xfs_dir2_leaf_entry {\n\t__be32 hashval;\n\t__be32 address;\n};\n\ntypedef struct xfs_dir2_leaf_entry xfs_dir2_leaf_entry_t;\n\nstruct xfs_dir2_leaf {\n\txfs_dir2_leaf_hdr_t hdr;\n\txfs_dir2_leaf_entry_t __ents[0];\n};\n\ntypedef struct xfs_dir2_leaf xfs_dir2_leaf_t;\n\nstruct xfs_dir2_leaf_tail {\n\t__be32 bestcount;\n};\n\ntypedef struct xfs_dir2_leaf_tail xfs_dir2_leaf_tail_t;\n\nstruct xfs_dir2_sf_entry {\n\t__u8 namelen;\n\t__u8 offset[2];\n\t__u8 name[0];\n};\n\ntypedef struct xfs_dir2_sf_entry xfs_dir2_sf_entry_t;\n\nstruct xfs_dir2_sf_hdr {\n\tuint8_t count;\n\tuint8_t i8count;\n\tuint8_t parent[8];\n};\n\ntypedef struct xfs_dir2_sf_hdr xfs_dir2_sf_hdr_t;\n\nstruct xfs_dir3_blk_hdr {\n\t__be32 magic;\n\t__be32 crc;\n\t__be64 blkno;\n\t__be64 lsn;\n\tuuid_t uuid;\n\t__be64 owner;\n};\n\nstruct xfs_dir3_data_hdr {\n\tstruct xfs_dir3_blk_hdr hdr;\n\txfs_dir2_data_free_t best_free[3];\n\t__be32 pad;\n};\n\nstruct xfs_dir3_free_hdr {\n\tstruct xfs_dir3_blk_hdr hdr;\n\t__be32 firstdb;\n\t__be32 nvalid;\n\t__be32 nused;\n\t__be32 pad;\n};\n\nstruct xfs_dir3_free {\n\tstruct xfs_dir3_free_hdr hdr;\n\t__be16 bests[0];\n};\n\nstruct xfs_dir3_icfree_hdr {\n\tuint32_t magic;\n\tuint32_t firstdb;\n\tuint32_t nvalid;\n\tuint32_t nused;\n\t__be16 *bests;\n};\n\nstruct xfs_dir3_icleaf_hdr {\n\tuint32_t forw;\n\tuint32_t back;\n\tuint16_t magic;\n\tuint16_t count;\n\tuint16_t stale;\n\tstruct xfs_dir2_leaf_entry *ents;\n};\n\nstruct xfs_dir3_leaf_hdr {\n\tstruct xfs_da3_blkinfo info;\n\t__be16 count;\n\t__be16 stale;\n\t__be32 pad;\n};\n\nstruct xfs_dir3_leaf {\n\tstruct xfs_dir3_leaf_hdr hdr;\n\tstruct xfs_dir2_leaf_entry __ents[0];\n};\n\nstruct xfs_dir_update_params {\n\tconst struct xfs_inode *dp;\n\tconst struct xfs_inode *ip;\n\tconst struct xfs_name *name;\n\tint delta;\n};\n\nstruct xfs_disk_dquot {\n\t__be16 d_magic;\n\t__u8 d_version;\n\t__u8 d_type;\n\t__be32 d_id;\n\t__be64 d_blk_hardlimit;\n\t__be64 d_blk_softlimit;\n\t__be64 d_ino_hardlimit;\n\t__be64 d_ino_softlimit;\n\t__be64 d_bcount;\n\t__be64 d_icount;\n\t__be32 d_itimer;\n\t__be32 d_btimer;\n\t__be16 d_iwarns;\n\t__be16 d_bwarns;\n\t__be32 d_pad0;\n\t__be64 d_rtb_hardlimit;\n\t__be64 d_rtb_softlimit;\n\t__be64 d_rtbcount;\n\t__be32 d_rtbtimer;\n\t__be16 d_rtbwarns;\n\t__be16 d_pad;\n};\n\nstruct xfs_dq_logformat {\n\tuint16_t qlf_type;\n\tuint16_t qlf_size;\n\txfs_dqid_t qlf_id;\n\tint64_t qlf_blkno;\n\tint32_t qlf_len;\n\tuint32_t qlf_boffset;\n};\n\nstruct xfs_dquot;\n\nstruct xfs_dq_logitem {\n\tstruct xfs_log_item qli_item;\n\tstruct xfs_dquot *qli_dquot;\n\txfs_lsn_t qli_flush_lsn;\n\tspinlock_t qli_lock;\n\tbool qli_dirty;\n};\n\nstruct xfs_dqblk {\n\tstruct xfs_disk_dquot dd_diskdq;\n\tchar dd_fill[4];\n\t__be32 dd_crc;\n\t__be64 dd_lsn;\n\tuuid_t dd_uuid;\n};\n\nstruct xfs_dqtrx {\n\tstruct xfs_dquot *qt_dquot;\n\tuint64_t qt_blk_res;\n\tint64_t qt_bcount_delta;\n\tint64_t qt_delbcnt_delta;\n\tuint64_t qt_rtblk_res;\n\tuint64_t qt_rtblk_res_used;\n\tint64_t qt_rtbcount_delta;\n\tint64_t qt_delrtb_delta;\n\tuint64_t qt_ino_res;\n\tuint64_t qt_ino_res_used;\n\tint64_t qt_icount_delta;\n};\n\nstruct xfs_dquot_res {\n\txfs_qcnt_t reserved;\n\txfs_qcnt_t count;\n\txfs_qcnt_t hardlimit;\n\txfs_qcnt_t softlimit;\n\ttime64_t timer;\n};\n\nstruct xfs_dquot_pre {\n\txfs_qcnt_t q_prealloc_lo_wmark;\n\txfs_qcnt_t q_prealloc_hi_wmark;\n\tint64_t q_low_space[3];\n};\n\nstruct xfs_dquot {\n\tstruct list_head q_lru;\n\tstruct xfs_mount *q_mount;\n\txfs_dqtype_t q_type;\n\tuint16_t q_flags;\n\txfs_dqid_t q_id;\n\tstruct lockref q_lockref;\n\tint q_bufoffset;\n\txfs_daddr_t q_blkno;\n\txfs_fileoff_t q_fileoffset;\n\tstruct xfs_dquot_res q_blk;\n\tstruct xfs_dquot_res q_ino;\n\tstruct xfs_dquot_res q_rtb;\n\tstruct xfs_dq_logitem q_logitem;\n\tstruct xfs_dquot_pre q_blk_prealloc;\n\tstruct xfs_dquot_pre q_rtb_prealloc;\n\tstruct mutex q_qlock;\n\tstruct completion q_flush;\n\tatomic_t q_pincount;\n\tstruct wait_queue_head q_pinwait;\n};\n\nstruct xfs_dquot_acct {\n\tstruct xfs_dqtrx dqs[15];\n};\n\nstruct xfs_dsb {\n\t__be32 sb_magicnum;\n\t__be32 sb_blocksize;\n\t__be64 sb_dblocks;\n\t__be64 sb_rblocks;\n\t__be64 sb_rextents;\n\tuuid_t sb_uuid;\n\t__be64 sb_logstart;\n\t__be64 sb_rootino;\n\t__be64 sb_rbmino;\n\t__be64 sb_rsumino;\n\t__be32 sb_rextsize;\n\t__be32 sb_agblocks;\n\t__be32 sb_agcount;\n\t__be32 sb_rbmblocks;\n\t__be32 sb_logblocks;\n\t__be16 sb_versionnum;\n\t__be16 sb_sectsize;\n\t__be16 sb_inodesize;\n\t__be16 sb_inopblock;\n\tchar sb_fname[12];\n\t__u8 sb_blocklog;\n\t__u8 sb_sectlog;\n\t__u8 sb_inodelog;\n\t__u8 sb_inopblog;\n\t__u8 sb_agblklog;\n\t__u8 sb_rextslog;\n\t__u8 sb_inprogress;\n\t__u8 sb_imax_pct;\n\t__be64 sb_icount;\n\t__be64 sb_ifree;\n\t__be64 sb_fdblocks;\n\t__be64 sb_frextents;\n\t__be64 sb_uquotino;\n\t__be64 sb_gquotino;\n\t__be16 sb_qflags;\n\t__u8 sb_flags;\n\t__u8 sb_shared_vn;\n\t__be32 sb_inoalignmt;\n\t__be32 sb_unit;\n\t__be32 sb_width;\n\t__u8 sb_dirblklog;\n\t__u8 sb_logsectlog;\n\t__be16 sb_logsectsize;\n\t__be32 sb_logsunit;\n\t__be32 sb_features2;\n\t__be32 sb_bad_features2;\n\t__be32 sb_features_compat;\n\t__be32 sb_features_ro_compat;\n\t__be32 sb_features_incompat;\n\t__be32 sb_features_log_incompat;\n\t__le32 sb_crc;\n\t__be32 sb_spino_align;\n\t__be64 sb_pquotino;\n\t__be64 sb_lsn;\n\tuuid_t sb_meta_uuid;\n\t__be64 sb_metadirino;\n\t__be32 sb_rgcount;\n\t__be32 sb_rgextents;\n\t__u8 sb_rgblklog;\n\t__u8 sb_pad[7];\n\t__be64 sb_rtstart;\n\t__be64 sb_rtreserved;\n};\n\nstruct xfs_dsymlink_hdr {\n\t__be32 sl_magic;\n\t__be32 sl_offset;\n\t__be32 sl_bytes;\n\t__be32 sl_crc;\n\tuuid_t sl_uuid;\n\t__be64 sl_owner;\n\t__be64 sl_blkno;\n\t__be64 sl_lsn;\n};\n\nstruct xfs_extent {\n\txfs_fsblock_t ext_start;\n\txfs_extlen_t ext_len;\n};\n\nstruct xfs_efd_log_format {\n\tuint16_t efd_type;\n\tuint16_t efd_size;\n\tuint32_t efd_nextents;\n\tuint64_t efd_efi_id;\n\tstruct xfs_extent efd_extents[0];\n};\n\nstruct xfs_efi_log_item;\n\nstruct xfs_efd_log_item {\n\tstruct xfs_log_item efd_item;\n\tstruct xfs_efi_log_item *efd_efip;\n\tuint efd_next_extent;\n\tstruct xfs_efd_log_format efd_format;\n};\n\nstruct xfs_efi_log_format {\n\tuint16_t efi_type;\n\tuint16_t efi_size;\n\tuint32_t efi_nextents;\n\tuint64_t efi_id;\n\tstruct xfs_extent efi_extents[0];\n};\n\nstruct xfs_extent_32 {\n\tuint64_t ext_start;\n\tuint32_t ext_len;\n} __attribute__((packed));\n\nstruct xfs_efi_log_format_32 {\n\tuint16_t efi_type;\n\tuint16_t efi_size;\n\tuint32_t efi_nextents;\n\tuint64_t efi_id;\n\tstruct xfs_extent_32 efi_extents[0];\n};\n\nstruct xfs_extent_64 {\n\tuint64_t ext_start;\n\tuint32_t ext_len;\n\tuint32_t ext_pad;\n};\n\nstruct xfs_efi_log_format_64 {\n\tuint16_t efi_type;\n\tuint16_t efi_size;\n\tuint32_t efi_nextents;\n\tuint64_t efi_id;\n\tstruct xfs_extent_64 efi_extents[0];\n};\n\nstruct xfs_efi_log_item {\n\tstruct xfs_log_item efi_item;\n\tatomic_t efi_refcount;\n\tatomic_t efi_next_extent;\n\tstruct xfs_efi_log_format efi_format;\n};\n\nstruct xfs_kobj {\n\tstruct kobject kobject;\n\tstruct completion complete;\n};\n\nstruct xfs_error_cfg {\n\tstruct xfs_kobj kobj;\n\tint max_retries;\n\tlong int retry_timeout;\n};\n\nstruct xfs_error_init {\n\tchar *name;\n\tint max_retries;\n\tint retry_timeout;\n};\n\nstruct xfs_error_injection {\n\t__s32 fd;\n\t__s32 errtag;\n};\n\ntypedef struct xfs_error_injection xfs_error_injection_t;\n\nstruct xfs_exchange_range {\n\t__s32 file1_fd;\n\t__u32 pad;\n\t__u64 file1_offset;\n\t__u64 file2_offset;\n\t__u64 length;\n\t__u64 flags;\n};\n\nstruct xfs_exchmaps_adjacent {\n\tstruct xfs_bmbt_irec left1;\n\tstruct xfs_bmbt_irec right1;\n\tstruct xfs_bmbt_irec left2;\n\tstruct xfs_bmbt_irec right2;\n};\n\nstruct xfs_exchmaps_intent {\n\tstruct list_head xmi_list;\n\tstruct xfs_inode *xmi_ip1;\n\tstruct xfs_inode *xmi_ip2;\n\txfs_fileoff_t xmi_startoff1;\n\txfs_fileoff_t xmi_startoff2;\n\txfs_filblks_t xmi_blockcount;\n\txfs_fsize_t xmi_isize1;\n\txfs_fsize_t xmi_isize2;\n\tuint64_t xmi_flags;\n};\n\nstruct xfs_exchmaps_req {\n\tstruct xfs_inode *ip1;\n\tstruct xfs_inode *ip2;\n\txfs_fileoff_t startoff1;\n\txfs_fileoff_t startoff2;\n\txfs_filblks_t blockcount;\n\tuint64_t flags;\n\txfs_filblks_t ip1_bcount;\n\txfs_filblks_t ip2_bcount;\n\txfs_filblks_t ip1_rtbcount;\n\txfs_filblks_t ip2_rtbcount;\n\tlong long unsigned int resblks;\n\tlong long unsigned int nr_exchanges;\n};\n\nstruct xfs_exchrange {\n\tstruct file *file1;\n\tstruct file *file2;\n\tloff_t file1_offset;\n\tloff_t file2_offset;\n\tu64 length;\n\tu64 flags;\n\tu64 file2_ino;\n\tstruct timespec64 file2_mtime;\n\tstruct timespec64 file2_ctime;\n\tu32 file2_gen;\n};\n\nstruct xfs_extent_busy {\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tstruct xfs_group *group;\n\txfs_agblock_t bno;\n\txfs_extlen_t length;\n\tunsigned int flags;\n};\n\nstruct xfs_extent_busy_tree {\n\tspinlock_t eb_lock;\n\tstruct rb_root eb_tree;\n\tunsigned int eb_gen;\n\twait_queue_head_t eb_wait;\n};\n\nstruct xfs_extent_free_item {\n\tstruct list_head xefi_list;\n\tuint64_t xefi_owner;\n\txfs_fsblock_t xefi_startblock;\n\txfs_extlen_t xefi_blockcount;\n\tstruct xfs_group *xefi_group;\n\tunsigned int xefi_flags;\n\tenum xfs_ag_resv_type xefi_agresv;\n};\n\nstruct xfs_fid {\n\t__u16 fid_len;\n\t__u16 fid_pad;\n\t__u32 fid_gen;\n\t__u64 fid_ino;\n};\n\ntypedef struct xfs_fid xfs_fid_t;\n\nstruct xfs_fid64 {\n\tu64 ino;\n\tu32 gen;\n\tu64 parent_ino;\n\tu32 parent_gen;\n} __attribute__((packed));\n\nstruct xfs_find_left_neighbor_info {\n\tstruct xfs_rmap_irec high;\n\tstruct xfs_rmap_irec *irec;\n};\n\nstruct xfs_freecounter {\n\tstruct percpu_counter count;\n\tuint64_t res_total;\n\tuint64_t res_avail;\n\tuint64_t res_saved;\n};\n\nstruct xfs_fs_eofblocks {\n\t__u32 eof_version;\n\t__u32 eof_flags;\n\tuid_t eof_uid;\n\tgid_t eof_gid;\n\tprid_t eof_prid;\n\t__u32 pad32;\n\t__u64 eof_min_file_size;\n\t__u64 pad64[12];\n};\n\nstruct xfs_fsmap {\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\txfs_fileoff_t fmr_offset;\n\txfs_filblks_t fmr_length;\n};\n\nstruct xfs_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct xfs_fsmap fmh_keys[2];\n};\n\nstruct xfs_fsmap_irec {\n\txfs_daddr_t start_daddr;\n\txfs_daddr_t len_daddr;\n\tuint64_t owner;\n\tuint64_t offset;\n\tunsigned int rm_flags;\n\txfs_agblock_t rec_key;\n};\n\nstruct xfs_fsop_handlereq {\n\t__u32 fd;\n\tvoid *path;\n\t__u32 oflags;\n\tvoid *ihandle;\n\t__u32 ihandlen;\n\tvoid *ohandle;\n\t__u32 *ohandlen;\n};\n\nstruct xfs_fsop_attrlist_handlereq {\n\tstruct xfs_fsop_handlereq hreq;\n\tstruct xfs_attrlist_cursor pos;\n\t__u32 flags;\n\t__u32 buflen;\n\tvoid *buffer;\n};\n\nstruct xfs_fsop_attrmulti_handlereq {\n\tstruct xfs_fsop_handlereq hreq;\n\t__u32 opcount;\n\tstruct xfs_attr_multiop *ops;\n};\n\ntypedef struct xfs_fsop_attrmulti_handlereq xfs_fsop_attrmulti_handlereq_t;\n\nstruct xfs_fsop_bulkreq {\n\t__u64 *lastip;\n\t__s32 icount;\n\tvoid *ubuffer;\n\t__s32 *ocount;\n};\n\nstruct xfs_fsop_counts {\n\t__u64 freedata;\n\t__u64 freertx;\n\t__u64 freeino;\n\t__u64 allocino;\n};\n\nstruct xfs_fsop_geom {\n\t__u32 blocksize;\n\t__u32 rtextsize;\n\t__u32 agblocks;\n\t__u32 agcount;\n\t__u32 logblocks;\n\t__u32 sectsize;\n\t__u32 inodesize;\n\t__u32 imaxpct;\n\t__u64 datablocks;\n\t__u64 rtblocks;\n\t__u64 rtextents;\n\t__u64 logstart;\n\tunsigned char uuid[16];\n\t__u32 sunit;\n\t__u32 swidth;\n\t__s32 version;\n\t__u32 flags;\n\t__u32 logsectsize;\n\t__u32 rtsectsize;\n\t__u32 dirblocksize;\n\t__u32 logsunit;\n\tuint32_t sick;\n\tuint32_t checked;\n\t__u32 rgextents;\n\t__u32 rgcount;\n\t__u64 rtstart;\n\t__u64 rtreserved;\n\t__u64 reserved[14];\n};\n\ntypedef struct xfs_fsop_handlereq xfs_fsop_handlereq_t;\n\nstruct xfs_fsop_resblks {\n\t__u64 resblks;\n\t__u64 resblks_avail;\n};\n\nstruct xfs_mru_cache_elem {\n\tstruct list_head list_node;\n\tlong unsigned int key;\n};\n\nstruct xfs_fstrm_item {\n\tstruct xfs_mru_cache_elem mru;\n\tstruct xfs_perag *pag;\n};\n\nstruct xfs_getfsmap_info;\n\nstruct xfs_getfsmap_dev {\n\tu32 dev;\n\tint (*fn)(struct xfs_trans *, const struct xfs_fsmap *, struct xfs_getfsmap_info *);\n\tsector_t nr_sectors;\n};\n\nstruct xfs_getfsmap_info {\n\tstruct xfs_fsmap_head *head;\n\tstruct fsmap *fsmap_recs;\n\tstruct xfs_buf *agf_bp;\n\tstruct xfs_group *group;\n\txfs_daddr_t next_daddr;\n\txfs_daddr_t low_daddr;\n\txfs_daddr_t end_daddr;\n\tu64 missing_owner;\n\tu32 dev;\n\tstruct xfs_rmap_irec low;\n\tstruct xfs_rmap_irec high;\n\tbool last;\n};\n\nstruct xfs_getparents {\n\tstruct xfs_attrlist_cursor gp_cursor;\n\t__u16 gp_iflags;\n\t__u16 gp_oflags;\n\t__u32 gp_bufsize;\n\t__u64 gp_reserved;\n\t__u64 gp_buffer;\n};\n\nstruct xfs_handle {\n\tunion {\n\t\t__s64 align;\n\t\txfs_fsid_t _ha_fsid;\n\t} ha_u;\n\txfs_fid_t ha_fid;\n};\n\nstruct xfs_getparents_by_handle {\n\tstruct xfs_handle gph_handle;\n\tstruct xfs_getparents gph_request;\n};\n\nstruct xfs_getparents_rec;\n\nstruct xfs_getparents_ctx {\n\tstruct xfs_attr_list_context context;\n\tstruct xfs_getparents_by_handle gph;\n\tstruct xfs_inode *ip;\n\tvoid *krecords;\n\tstruct xfs_getparents_rec *lastrec;\n\tunsigned int count;\n};\n\nstruct xfs_getparents_rec {\n\tstruct xfs_handle gpr_parent;\n\t__u32 gpr_reclen;\n\t__u32 gpr_reserved;\n\tchar gpr_name[0];\n};\n\nstruct xfs_globals {\n\tint bload_leaf_slack;\n\tint bload_node_slack;\n\tint log_recovery_delay;\n\tint mount_delay;\n\tbool bug_on_assert;\n\tbool always_cow;\n};\n\nstruct xfs_hooks {\n\tstruct blocking_notifier_head head;\n};\n\nstruct xfs_group {\n\tstruct xfs_mount *xg_mount;\n\tuint32_t xg_gno;\n\tenum xfs_group_type xg_type;\n\tatomic_t xg_ref;\n\tatomic_t xg_active_ref;\n\tuint32_t xg_block_count;\n\tuint32_t xg_min_gbno;\n\tunion {\n\t\tstruct xfs_extent_busy_tree *xg_busy_extents;\n\t\tstruct xfs_group *xg_next_reset;\n\t};\n\tuint16_t xg_checked;\n\tuint16_t xg_sick;\n\tspinlock_t xg_state_lock;\n\tstruct xfs_defer_drain xg_intents_drain;\n\tstruct xfs_hooks xg_rmap_update_hooks;\n};\n\nstruct xfs_group_data_lost {\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n};\n\nstruct xfs_groups {\n\tstruct xarray xa;\n\tuint32_t blocks;\n\tuint8_t blklog;\n\tbool has_daddr_gaps;\n\tuint64_t blkmask;\n\txfs_fsblock_t start_fsb;\n\txfs_extlen_t awu_max;\n};\n\nstruct xfs_growfs_data {\n\t__u64 newblocks;\n\t__u32 imaxpct;\n};\n\nstruct xfs_growfs_log {\n\t__u32 newblocks;\n\t__u32 isint;\n};\n\nstruct xfs_growfs_rt {\n\t__u64 newblocks;\n\t__u32 extsize;\n};\n\ntypedef struct xfs_growfs_rt xfs_growfs_rt_t;\n\ntypedef struct xfs_handle xfs_handle_t;\n\nstruct xfs_health_file_on_monitored_fs {\n\t__s32 fd;\n\t__u32 flags;\n};\n\nstruct xfs_health_monitor {\n\t__u64 flags;\n\t__u8 format;\n\t__u8 pad[23];\n};\n\nstruct xfs_health_monitor_lost {\n\t__u64 count;\n};\n\nstruct xfs_health_monitor_fs {\n\t__u32 mask;\n};\n\nstruct xfs_health_monitor_group {\n\t__u32 mask;\n\t__u32 gno;\n};\n\nstruct xfs_health_monitor_inode {\n\t__u32 mask;\n\t__u32 gen;\n\t__u64 ino;\n};\n\nstruct xfs_health_monitor_shutdown {\n\t__u32 reasons;\n};\n\nstruct xfs_health_monitor_media {\n\t__u64 daddr;\n\t__u64 bbcount;\n};\n\nstruct xfs_health_monitor_filerange {\n\t__u64 pos;\n\t__u64 len;\n\t__u64 ino;\n\t__u32 gen;\n\t__u32 error;\n};\n\nstruct xfs_health_monitor_event {\n\t__u32 domain;\n\t__u32 type;\n\t__u64 time_ns;\n\tunion {\n\t\tstruct xfs_health_monitor_lost lost;\n\t\tstruct xfs_health_monitor_fs fs;\n\t\tstruct xfs_health_monitor_group group;\n\t\tstruct xfs_health_monitor_inode inode;\n\t\tstruct xfs_health_monitor_shutdown shutdown;\n\t\tstruct xfs_health_monitor_media media;\n\t\tstruct xfs_health_monitor_filerange filerange;\n\t} e;\n\t__u64 pad[2];\n};\n\nstruct xfs_healthmon_event;\n\nstruct xfs_healthmon {\n\tuintptr_t mount_cookie;\n\tdev_t dev;\n\trefcount_t ref;\n\tstruct mutex lock;\n\tstruct xfs_healthmon_event *first_event;\n\tstruct xfs_healthmon_event *last_event;\n\tstruct xfs_healthmon_event *unmount_event;\n\tunsigned int events;\n\tbool verbose: 1;\n\tstruct wait_queue_head wait;\n\tchar *buffer;\n\tsize_t bufsize;\n\tsize_t bufhead;\n\tsize_t buftail;\n\tlong long unsigned int lost_prev_event;\n\tlong long unsigned int total_events;\n\tlong long unsigned int total_lost;\n};\n\nstruct xfs_healthmon_event {\n\tstruct xfs_healthmon_event *next;\n\tenum xfs_healthmon_type type;\n\tenum xfs_healthmon_domain domain;\n\tuint64_t time_ns;\n\tunion {\n\t\tstruct {\n\t\t\tuint64_t lostcount;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int fsmask;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int grpmask;\n\t\t\tunsigned int group;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int imask;\n\t\t\tuint32_t gen;\n\t\t\txfs_ino_t ino;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned int flags;\n\t\t};\n\t\tstruct {\n\t\t\txfs_daddr_t daddr;\n\t\t\tuint64_t bbcount;\n\t\t};\n\t\tstruct {\n\t\t\txfs_ino_t fino;\n\t\t\tloff_t fpos;\n\t\t\tuint64_t flen;\n\t\t\tuint32_t fgen;\n\t\t\tint error;\n\t\t};\n\t};\n};\n\nstruct xfs_ialloc_count_inodes {\n\txfs_agino_t count;\n\txfs_agino_t freecount;\n};\n\nstruct xfs_ibulk {\n\tstruct xfs_mount *mp;\n\tstruct mnt_idmap *idmap;\n\tvoid *ubuffer;\n\txfs_ino_t startino;\n\tunsigned int icount;\n\tunsigned int ocount;\n\tunsigned int flags;\n\tunsigned int iwalk_flags;\n};\n\nstruct xfs_icluster {\n\tbool deleted;\n\txfs_ino_t first_ino;\n\tuint64_t alloc;\n};\n\nstruct xfs_icreate_args {\n\tstruct mnt_idmap *idmap;\n\tstruct xfs_inode *pip;\n\tdev_t rdev;\n\tumode_t mode;\n\tuint16_t flags;\n};\n\nstruct xfs_icreate_log {\n\tuint16_t icl_type;\n\tuint16_t icl_size;\n\t__be32 icl_ag;\n\t__be32 icl_agbno;\n\t__be32 icl_count;\n\t__be32 icl_isize;\n\t__be32 icl_length;\n\t__be32 icl_gen;\n};\n\nstruct xfs_icreate_item {\n\tstruct xfs_log_item ic_item;\n\tstruct xfs_icreate_log ic_format;\n};\n\nstruct xfs_icwalk {\n\t__u32 icw_flags;\n\tkuid_t icw_uid;\n\tkgid_t icw_gid;\n\tprid_t icw_prid;\n\t__u64 icw_min_file_size;\n\tlong int icw_scan_limit;\n};\n\nstruct xfs_iext_rec {\n\tuint64_t lo;\n\tuint64_t hi;\n};\n\nstruct xfs_iext_leaf {\n\tstruct xfs_iext_rec recs[15];\n\tstruct xfs_iext_leaf *prev;\n\tstruct xfs_iext_leaf *next;\n};\n\nstruct xfs_iext_node {\n\tuint64_t keys[16];\n\tvoid *ptrs[16];\n};\n\nstruct xfs_ifork {\n\tint64_t if_bytes;\n\tstruct xfs_btree_block *if_broot;\n\tunsigned int if_seq;\n\tint if_height;\n\tvoid *if_data;\n\txfs_extnum_t if_nextents;\n\tshort int if_broot_bytes;\n\tint8_t if_format;\n\tuint8_t if_needextents;\n};\n\nstruct xfs_imap {\n\txfs_daddr_t im_blkno;\n\tshort unsigned int im_len;\n\tshort unsigned int im_boffset;\n};\n\nstruct xfs_ino_geometry {\n\tuint64_t maxicount;\n\tunsigned int inode_cluster_size;\n\tunsigned int inode_cluster_size_raw;\n\tunsigned int inodes_per_cluster;\n\tunsigned int blocks_per_cluster;\n\tunsigned int cluster_align;\n\tunsigned int cluster_align_inodes;\n\tunsigned int inoalign_mask;\n\tunsigned int inobt_mxr[2];\n\tunsigned int inobt_mnr[2];\n\tunsigned int inobt_maxlevels;\n\tunsigned int ialloc_inos;\n\tunsigned int ialloc_blks;\n\tunsigned int ialloc_min_blks;\n\tunsigned int ialloc_align;\n\tunsigned int agino_log;\n\tunsigned int attr_fork_offset;\n\tuint64_t new_diflags2;\n\tunsigned int min_folio_order;\n};\n\ntypedef struct xfs_inobt_rec_incore xfs_inobt_rec_incore_t;\n\nstruct xfs_inode_log_item;\n\nstruct xfs_inode {\n\tstruct xfs_mount *i_mount;\n\tstruct xfs_dquot *i_udquot;\n\tstruct xfs_dquot *i_gdquot;\n\tstruct xfs_dquot *i_pdquot;\n\txfs_ino_t i_ino;\n\tstruct xfs_imap i_imap;\n\tstruct xfs_ifork *i_cowfp;\n\tstruct xfs_ifork i_df;\n\tstruct xfs_ifork i_af;\n\tstruct xfs_inode_log_item *i_itemp;\n\tstruct rw_semaphore i_lock;\n\tatomic_t i_pincount;\n\tstruct llist_node i_gclist;\n\tuint16_t i_checked;\n\tuint16_t i_sick;\n\tspinlock_t i_flags_lock;\n\tlong unsigned int i_flags;\n\tuint64_t i_delayed_blks;\n\txfs_fsize_t i_disk_size;\n\txfs_rfsblock_t i_nblocks;\n\tprid_t i_projid;\n\txfs_extlen_t i_extsize;\n\tunion {\n\t\tuint32_t i_used_blocks;\n\t\txfs_extlen_t i_cowextsize;\n\t\tuint16_t i_flushiter;\n\t};\n\tuint8_t i_forkoff;\n\tenum xfs_metafile_type i_metatype;\n\tuint16_t i_diflags;\n\tuint64_t i_diflags2;\n\tstruct timespec64 i_crtime;\n\txfs_agino_t i_next_unlinked;\n\txfs_agino_t i_prev_unlinked;\n\tstruct inode i_vnode;\n\tspinlock_t i_ioend_lock;\n\tstruct work_struct i_ioend_work;\n\tstruct list_head i_ioend_list;\n};\n\ntypedef struct xfs_inode xfs_inode_t;\n\nstruct xfs_inode_log_format {\n\tuint16_t ilf_type;\n\tuint16_t ilf_size;\n\tuint32_t ilf_fields;\n\tuint16_t ilf_asize;\n\tuint16_t ilf_dsize;\n\tuint32_t ilf_pad;\n\tuint64_t ilf_ino;\n\tunion {\n\t\tuint32_t ilfu_rdev;\n\t\tuint8_t __pad[16];\n\t} ilf_u;\n\tint64_t ilf_blkno;\n\tint32_t ilf_len;\n\tint32_t ilf_boffset;\n};\n\nstruct xfs_inode_log_format_32 {\n\tuint16_t ilf_type;\n\tuint16_t ilf_size;\n\tuint32_t ilf_fields;\n\tuint16_t ilf_asize;\n\tuint16_t ilf_dsize;\n\tuint64_t ilf_ino;\n\tunion {\n\t\tuint32_t ilfu_rdev;\n\t\tuint8_t __pad[16];\n\t} ilf_u;\n\tint64_t ilf_blkno;\n\tint32_t ilf_len;\n\tint32_t ilf_boffset;\n} __attribute__((packed));\n\nstruct xfs_inode_log_item {\n\tstruct xfs_log_item ili_item;\n\tstruct xfs_inode *ili_inode;\n\tshort unsigned int ili_lock_flags;\n\tunsigned int ili_dirty_flags;\n\tspinlock_t ili_lock;\n\tunsigned int ili_last_fields;\n\tunsigned int ili_fields;\n\txfs_lsn_t ili_flush_lsn;\n\txfs_csn_t ili_commit_seq;\n\txfs_csn_t ili_datasync_seq;\n};\n\nstruct xfs_inodegc {\n\tstruct xfs_mount *mp;\n\tstruct llist_head list;\n\tstruct delayed_work work;\n\tint error;\n\tunsigned int items;\n\tunsigned int shrinker_hits;\n\tunsigned int cpu;\n};\n\nstruct xfs_inogrp {\n\t__u64 xi_startino;\n\t__s32 xi_alloccount;\n\t__u64 xi_allocmask;\n};\n\nstruct xfs_inumbers {\n\tuint64_t xi_startino;\n\tuint64_t xi_allocmask;\n\tuint8_t xi_alloccount;\n\tuint8_t xi_version;\n\tuint8_t xi_padding[6];\n};\n\ntypedef int (*inumbers_fmt_pf)(struct xfs_ibulk *, const struct xfs_inumbers *);\n\nstruct xfs_inumbers_chunk {\n\tinumbers_fmt_pf formatter;\n\tstruct xfs_ibulk *breq;\n};\n\nstruct xfs_inumbers_req {\n\tstruct xfs_bulk_ireq hdr;\n\tstruct xfs_inumbers inumbers[0];\n};\n\nstruct xfs_iread_state {\n\tstruct xfs_iext_cursor icur;\n\txfs_extnum_t loaded;\n};\n\nstruct xlog_format_buf;\n\nstruct xfs_item_ops {\n\tunsigned int flags;\n\tvoid (*iop_size)(struct xfs_log_item *, int *, int *);\n\tvoid (*iop_format)(struct xfs_log_item *, struct xlog_format_buf *);\n\tvoid (*iop_pin)(struct xfs_log_item *);\n\tvoid (*iop_unpin)(struct xfs_log_item *, int);\n\tuint64_t (*iop_sort)(struct xfs_log_item *);\n\tint (*iop_precommit)(struct xfs_trans *, struct xfs_log_item *);\n\tvoid (*iop_committing)(struct xfs_log_item *, xfs_csn_t);\n\txfs_lsn_t (*iop_committed)(struct xfs_log_item *, xfs_lsn_t);\n\tuint (*iop_push)(struct xfs_log_item *, struct list_head *);\n\tvoid (*iop_release)(struct xfs_log_item *);\n\tbool (*iop_match)(struct xfs_log_item *, uint64_t);\n\tstruct xfs_log_item * (*iop_intent)(struct xfs_log_item *);\n};\n\nstruct xfs_iunlink_item {\n\tstruct xfs_log_item item;\n\tstruct xfs_inode *ip;\n\tstruct xfs_perag *pag;\n\txfs_agino_t next_agino;\n\txfs_agino_t old_agino;\n};\n\nstruct xfs_pwork_ctl;\n\nstruct xfs_pwork {\n\tstruct work_struct work;\n\tstruct xfs_pwork_ctl *pctl;\n};\n\ntypedef int (*xfs_iwalk_fn)(struct xfs_mount *, struct xfs_trans *, xfs_ino_t, void *);\n\ntypedef int (*xfs_inobt_walk_fn)(struct xfs_mount *, struct xfs_trans *, xfs_agnumber_t, const struct xfs_inobt_rec_incore *, void *);\n\nstruct xfs_iwalk_ag {\n\tstruct xfs_pwork pwork;\n\tstruct xfs_mount *mp;\n\tstruct xfs_trans *tp;\n\tstruct xfs_perag *pag;\n\txfs_ino_t startino;\n\txfs_ino_t lastino;\n\tstruct xfs_inobt_rec_incore *recs;\n\tunsigned int sz_recs;\n\tunsigned int nr_recs;\n\txfs_iwalk_fn iwalk_fn;\n\txfs_inobt_walk_fn inobt_walk_fn;\n\tvoid *data;\n\tunsigned int trim_start: 1;\n\tunsigned int skip_empty: 1;\n\tunsigned int drop_trans: 1;\n};\n\nstruct xfs_legacy_timestamp {\n\t__be32 t_sec;\n\t__be32 t_nsec;\n};\n\nstruct xfs_log_dinode {\n\tuint16_t di_magic;\n\tuint16_t di_mode;\n\tint8_t di_version;\n\tint8_t di_format;\n\tuint16_t di_metatype;\n\tuint32_t di_uid;\n\tuint32_t di_gid;\n\tuint32_t di_nlink;\n\tuint16_t di_projid_lo;\n\tuint16_t di_projid_hi;\n\tunion {\n\t\tuint64_t di_big_nextents;\n\t\tuint64_t di_v3_pad;\n\t\tstruct {\n\t\t\tuint8_t di_v2_pad[6];\n\t\t\tuint16_t di_flushiter;\n\t\t};\n\t};\n\txfs_log_timestamp_t di_atime;\n\txfs_log_timestamp_t di_mtime;\n\txfs_log_timestamp_t di_ctime;\n\txfs_fsize_t di_size;\n\txfs_rfsblock_t di_nblocks;\n\txfs_extlen_t di_extsize;\n\tunion {\n\t\tstruct {\n\t\t\tuint32_t di_nextents;\n\t\t\tuint16_t di_anextents;\n\t\t} __attribute__((packed));\n\t\tstruct {\n\t\t\tuint32_t di_big_anextents;\n\t\t\tuint16_t di_nrext64_pad;\n\t\t} __attribute__((packed));\n\t};\n\tuint8_t di_forkoff;\n\tint8_t di_aformat;\n\tuint32_t di_dmevmask;\n\tuint16_t di_dmstate;\n\tuint16_t di_flags;\n\tuint32_t di_gen;\n\txfs_agino_t di_next_unlinked;\n\tuint32_t di_crc;\n\tuint64_t di_changecount;\n\txfs_lsn_t di_lsn;\n\tuint64_t di_flags2;\n\tunion {\n\t\tuint32_t di_cowextsize;\n\t\tuint32_t di_used_blocks;\n\t};\n\tuint8_t di_pad2[12];\n\txfs_log_timestamp_t di_crtime;\n\txfs_ino_t di_ino;\n\tuuid_t di_uuid;\n};\n\nstruct xfs_log_iovec {\n\tvoid *i_addr;\n\tint i_len;\n\tuint i_type;\n};\n\nstruct xfs_log_legacy_timestamp {\n\tint32_t t_sec;\n\tint32_t t_nsec;\n};\n\nstruct xfs_log_vec {\n\tstruct list_head lv_list;\n\tuint32_t lv_order_id;\n\tint lv_niovecs;\n\tstruct xfs_log_iovec *lv_iovecp;\n\tstruct xfs_log_item *lv_item;\n\tchar *lv_buf;\n\tint lv_bytes;\n\tint lv_buf_used;\n\tint lv_alloc_size;\n};\n\nstruct xfs_metadir_update {\n\tstruct xfs_inode *dp;\n\tconst char *path;\n\tstruct xfs_parent_args *ppargs;\n\tstruct xfs_inode *ip;\n\tstruct xfs_trans *tp;\n\tenum xfs_metafile_type metafile_type;\n\tunsigned int dp_locked: 1;\n\tunsigned int ip_locked: 1;\n};\n\nstruct xfs_sb {\n\tuint32_t sb_magicnum;\n\tuint32_t sb_blocksize;\n\txfs_rfsblock_t sb_dblocks;\n\txfs_rfsblock_t sb_rblocks;\n\txfs_rtbxlen_t sb_rextents;\n\tuuid_t sb_uuid;\n\txfs_fsblock_t sb_logstart;\n\txfs_ino_t sb_rootino;\n\txfs_ino_t sb_rbmino;\n\txfs_ino_t sb_rsumino;\n\txfs_agblock_t sb_rextsize;\n\txfs_agblock_t sb_agblocks;\n\txfs_agnumber_t sb_agcount;\n\txfs_extlen_t sb_rbmblocks;\n\txfs_extlen_t sb_logblocks;\n\tuint16_t sb_versionnum;\n\tuint16_t sb_sectsize;\n\tuint16_t sb_inodesize;\n\tuint16_t sb_inopblock;\n\tchar sb_fname[12];\n\tuint8_t sb_blocklog;\n\tuint8_t sb_sectlog;\n\tuint8_t sb_inodelog;\n\tuint8_t sb_inopblog;\n\tuint8_t sb_agblklog;\n\tuint8_t sb_rextslog;\n\tuint8_t sb_inprogress;\n\tuint8_t sb_imax_pct;\n\tuint64_t sb_icount;\n\tuint64_t sb_ifree;\n\tuint64_t sb_fdblocks;\n\tuint64_t sb_frextents;\n\txfs_ino_t sb_uquotino;\n\txfs_ino_t sb_gquotino;\n\tuint16_t sb_qflags;\n\tuint8_t sb_flags;\n\tuint8_t sb_shared_vn;\n\txfs_extlen_t sb_inoalignmt;\n\tuint32_t sb_unit;\n\tuint32_t sb_width;\n\tuint8_t sb_dirblklog;\n\tuint8_t sb_logsectlog;\n\tuint16_t sb_logsectsize;\n\tuint32_t sb_logsunit;\n\tuint32_t sb_features2;\n\tuint32_t sb_bad_features2;\n\tuint32_t sb_features_compat;\n\tuint32_t sb_features_ro_compat;\n\tuint32_t sb_features_incompat;\n\tuint32_t sb_features_log_incompat;\n\tuint32_t sb_crc;\n\txfs_extlen_t sb_spino_align;\n\txfs_ino_t sb_pquotino;\n\txfs_lsn_t sb_lsn;\n\tuuid_t sb_meta_uuid;\n\txfs_ino_t sb_metadirino;\n\txfs_rgnumber_t sb_rgcount;\n\txfs_rtxlen_t sb_rgextents;\n\tuint8_t sb_rgblklog;\n\tuint8_t sb_pad[7];\n\txfs_rfsblock_t sb_rtstart;\n\txfs_filblks_t sb_rtreserved;\n};\n\nstruct xfs_trans_res {\n\tuint tr_logres;\n\tint tr_logcount;\n\tint tr_logflags;\n};\n\nstruct xfs_trans_resv {\n\tstruct xfs_trans_res tr_write;\n\tstruct xfs_trans_res tr_itruncate;\n\tstruct xfs_trans_res tr_rename;\n\tstruct xfs_trans_res tr_link;\n\tstruct xfs_trans_res tr_remove;\n\tstruct xfs_trans_res tr_symlink;\n\tstruct xfs_trans_res tr_create;\n\tstruct xfs_trans_res tr_create_tmpfile;\n\tstruct xfs_trans_res tr_mkdir;\n\tstruct xfs_trans_res tr_ifree;\n\tstruct xfs_trans_res tr_ichange;\n\tstruct xfs_trans_res tr_growdata;\n\tstruct xfs_trans_res tr_addafork;\n\tstruct xfs_trans_res tr_writeid;\n\tstruct xfs_trans_res tr_attrinval;\n\tstruct xfs_trans_res tr_attrsetm;\n\tstruct xfs_trans_res tr_attrsetrt;\n\tstruct xfs_trans_res tr_attrrm;\n\tstruct xfs_trans_res tr_clearagi;\n\tstruct xfs_trans_res tr_growrtalloc;\n\tstruct xfs_trans_res tr_growrtzero;\n\tstruct xfs_trans_res tr_growrtfree;\n\tstruct xfs_trans_res tr_qm_setqlim;\n\tstruct xfs_trans_res tr_qm_dqalloc;\n\tstruct xfs_trans_res tr_sb;\n\tstruct xfs_trans_res tr_fsyncts;\n\tstruct xfs_trans_res tr_atomic_ioend;\n};\n\nstruct xfsstats;\n\nstruct xstats {\n\tstruct xfsstats *xs_stats;\n\tstruct xfs_kobj xs_kobj;\n};\n\nstruct xfs_quotainfo;\n\nstruct xfs_mru_cache;\n\nstruct xfs_zone_info;\n\nstruct xfs_mount {\n\tstruct xfs_sb m_sb;\n\tstruct super_block *m_super;\n\tstruct xfs_ail *m_ail;\n\tstruct xfs_buf *m_sb_bp;\n\tstruct xfs_buf *m_rtsb_bp;\n\tchar *m_rtname;\n\tchar *m_logname;\n\tstruct xfs_da_geometry *m_dir_geo;\n\tstruct xfs_da_geometry *m_attr_geo;\n\tstruct xlog *m_log;\n\tstruct xfs_inode *m_rootip;\n\tstruct xfs_inode *m_metadirip;\n\tstruct xfs_inode *m_rtdirip;\n\tstruct xfs_quotainfo *m_quotainfo;\n\tstruct xfs_buftarg *m_ddev_targp;\n\tstruct xfs_buftarg *m_logdev_targp;\n\tstruct xfs_buftarg *m_rtdev_targp;\n\tvoid *m_inodegc;\n\tstruct xfs_mru_cache *m_filestream;\n\tstruct workqueue_struct *m_buf_workqueue;\n\tstruct workqueue_struct *m_unwritten_workqueue;\n\tstruct workqueue_struct *m_reclaim_workqueue;\n\tstruct workqueue_struct *m_sync_workqueue;\n\tstruct workqueue_struct *m_blockgc_wq;\n\tstruct workqueue_struct *m_inodegc_wq;\n\tint m_bsize;\n\tuint8_t m_blkbit_log;\n\tuint8_t m_blkbb_log;\n\tuint8_t m_agno_log;\n\tuint8_t m_sectbb_log;\n\tint8_t m_rtxblklog;\n\tuint m_blockmask;\n\tuint m_blockwsize;\n\tunsigned int m_rtx_per_rbmblock;\n\tuint m_alloc_mxr[2];\n\tuint m_alloc_mnr[2];\n\tuint m_bmap_dmxr[2];\n\tuint m_bmap_dmnr[2];\n\tuint m_rmap_mxr[2];\n\tuint m_rmap_mnr[2];\n\tuint m_rtrmap_mxr[2];\n\tuint m_rtrmap_mnr[2];\n\tuint m_refc_mxr[2];\n\tuint m_refc_mnr[2];\n\tuint m_rtrefc_mxr[2];\n\tuint m_rtrefc_mnr[2];\n\tuint m_alloc_maxlevels;\n\tuint m_bm_maxlevels[2];\n\tuint m_rmap_maxlevels;\n\tuint m_rtrmap_maxlevels;\n\tuint m_refc_maxlevels;\n\tuint m_rtrefc_maxlevels;\n\tunsigned int m_agbtree_maxlevels;\n\tunsigned int m_rtbtree_maxlevels;\n\txfs_extlen_t m_ag_prealloc_blocks;\n\tuint m_alloc_set_aside;\n\tuint m_ag_max_usable;\n\tint m_dalign;\n\tint m_swidth;\n\txfs_agnumber_t m_maxagi;\n\tuint m_allocsize_log;\n\tuint m_allocsize_blocks;\n\tint m_logbufs;\n\tint m_logbsize;\n\tunsigned int m_rsumlevels;\n\txfs_filblks_t m_rsumblocks;\n\tint m_fixedfsid[2];\n\tuint m_qflags;\n\tuint64_t m_features;\n\tuint64_t m_low_space[5];\n\tuint64_t m_low_rtexts[5];\n\tuint64_t m_rtxblkmask;\n\tstruct xfs_ino_geometry m_ino_geo;\n\tstruct xfs_trans_resv m_resv;\n\tlong unsigned int m_opstate;\n\tbool m_always_cow;\n\tbool m_fail_unmount;\n\tbool m_finobt_nores;\n\tbool m_update_sb;\n\tunsigned int m_max_open_zones;\n\tunsigned int m_zonegc_low_space;\n\tlong long unsigned int m_awu_max_bytes;\n\tuint8_t m_fs_checked;\n\tuint8_t m_fs_sick;\n\tuint8_t m_rt_checked;\n\tuint8_t m_rt_sick;\n\tlong: 0;\n\tspinlock_t m_sb_lock;\n\tstruct percpu_counter m_icount;\n\tstruct percpu_counter m_ifree;\n\tstruct xfs_freecounter m_free[3];\n\tstruct percpu_counter m_delalloc_blks;\n\tstruct percpu_counter m_delalloc_rtextents;\n\tatomic64_t m_allocbt_blks;\n\tstruct xfs_groups m_groups[2];\n\tstruct delayed_work m_reclaim_work;\n\tstruct xfs_zone_info *m_zone_info;\n\tstruct dentry *m_debugfs;\n\tstruct xfs_kobj m_kobj;\n\tstruct xfs_kobj m_error_kobj;\n\tstruct xfs_kobj m_error_meta_kobj;\n\tstruct xfs_error_cfg m_error_cfg[4];\n\tstruct xstats m_stats;\n\tstruct xchk_stats *m_scrub_stats;\n\tstruct xfs_kobj m_zoned_kobj;\n\txfs_agnumber_t m_agfrotor;\n\tatomic_t m_agirotor;\n\tatomic_t m_rtgrotor;\n\tstruct mutex m_metafile_resv_lock;\n\tuint64_t m_metafile_resv_target;\n\tuint64_t m_metafile_resv_used;\n\tuint64_t m_metafile_resv_avail;\n\tstruct shrinker *m_inodegc_shrinker;\n\tstruct work_struct m_flush_inodes_work;\n\tuint32_t m_generation;\n\tstruct mutex m_growlock;\n\tstruct cpumask m_inodegc_cpumask;\n\tstruct xfs_hooks m_dir_update_hooks;\n\tstruct xfs_healthmon *m_healthmon;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct xfs_mount xfs_mount_t;\n\ntypedef void (*xfs_mru_cache_free_func_t)(void *, struct xfs_mru_cache_elem *);\n\nstruct xfs_mru_cache {\n\tstruct xarray store;\n\tstruct list_head *lists;\n\tstruct list_head reap_list;\n\tspinlock_t lock;\n\tunsigned int grp_count;\n\tunsigned int grp_time;\n\tunsigned int lru_grp;\n\tlong unsigned int time_zero;\n\txfs_mru_cache_free_func_t free_func;\n\tstruct delayed_work work;\n\tunsigned int queued;\n\tvoid *data;\n};\n\nstruct xfs_open_zone {\n\tstruct list_head oz_entry;\n\tatomic_t oz_ref;\n\tspinlock_t oz_alloc_lock;\n\txfs_rgblock_t oz_allocated;\n\txfs_rgblock_t oz_written;\n\tenum rw_hint oz_write_hint;\n\tbool oz_is_gc;\n\tstruct xfs_rtgroup *oz_rtg;\n\tstruct callback_head oz_rcu;\n};\n\nstruct xfs_sysctl_val {\n\tint min;\n\tint val;\n\tint max;\n};\n\ntypedef struct xfs_sysctl_val xfs_sysctl_val_t;\n\nstruct xfs_param {\n\txfs_sysctl_val_t panic_mask;\n\txfs_sysctl_val_t error_level;\n\txfs_sysctl_val_t syncd_timer;\n\txfs_sysctl_val_t stats_clear;\n\txfs_sysctl_val_t inherit_sync;\n\txfs_sysctl_val_t inherit_nodump;\n\txfs_sysctl_val_t inherit_noatim;\n\txfs_sysctl_val_t inherit_nosym;\n\txfs_sysctl_val_t rotorstep;\n\txfs_sysctl_val_t inherit_nodfrg;\n\txfs_sysctl_val_t fstrm_timer;\n\txfs_sysctl_val_t blockgc_timer;\n};\n\ntypedef struct xfs_param xfs_param_t;\n\nstruct xfs_perag {\n\tstruct xfs_group pag_group;\n\tlong unsigned int pag_opstate;\n\tuint8_t pagf_bno_level;\n\tuint8_t pagf_cnt_level;\n\tuint8_t pagf_rmap_level;\n\tuint32_t pagf_flcount;\n\txfs_extlen_t pagf_freeblks;\n\txfs_extlen_t pagf_longest;\n\tuint32_t pagf_btreeblks;\n\txfs_agino_t pagi_freecount;\n\txfs_agino_t pagi_count;\n\txfs_agino_t pagl_pagino;\n\txfs_agino_t pagl_leftrec;\n\txfs_agino_t pagl_rightrec;\n\tuint8_t pagf_refcount_level;\n\tstruct xfs_ag_resv pag_meta_resv;\n\tstruct xfs_ag_resv pag_rmapbt_resv;\n\txfs_agino_t agino_min;\n\txfs_agino_t agino_max;\n\tuint8_t pagf_repair_bno_level;\n\tuint8_t pagf_repair_cnt_level;\n\tuint8_t pagf_repair_refcount_level;\n\tuint8_t pagf_repair_rmap_level;\n\tatomic_t pagf_fstrms;\n\tspinlock_t pag_ici_lock;\n\tstruct xarray pag_ici_root;\n\tint pag_ici_reclaimable;\n\tlong unsigned int pag_ici_reclaim_cursor;\n\tstruct xfs_buf_cache pag_bcache;\n\tstruct delayed_work pag_blockgc_work;\n};\n\ntypedef int (*xfs_pwork_work_fn)(struct xfs_mount *, struct xfs_pwork *);\n\nstruct xfs_pwork_ctl {\n\tstruct workqueue_struct *wq;\n\tstruct xfs_mount *mp;\n\txfs_pwork_work_fn work_fn;\n\tstruct wait_queue_head poll_wait;\n\tatomic_t nr_work;\n\tint error;\n};\n\nstruct xfs_qoff_logformat {\n\tshort unsigned int qf_type;\n\tshort unsigned int qf_size;\n\tunsigned int qf_flags;\n\tchar qf_pad[12];\n};\n\nstruct xfs_quotainfo {\n\tstruct xarray qi_uquota_tree;\n\tstruct xarray qi_gquota_tree;\n\tstruct xarray qi_pquota_tree;\n\tstruct mutex qi_tree_lock;\n\tstruct xfs_inode *qi_uquotaip;\n\tstruct xfs_inode *qi_gquotaip;\n\tstruct xfs_inode *qi_pquotaip;\n\tstruct xfs_inode *qi_dirip;\n\tstruct list_lru qi_lru;\n\tuint64_t qi_dquots;\n\tstruct mutex qi_quotaofflock;\n\txfs_filblks_t qi_dqchunklen;\n\tuint qi_dqperchunk;\n\tstruct xfs_def_quota qi_usr_default;\n\tstruct xfs_def_quota qi_grp_default;\n\tstruct xfs_def_quota qi_prj_default;\n\tstruct shrinker *qi_shrinker;\n\ttime64_t qi_expiry_min;\n\ttime64_t qi_expiry_max;\n\tstruct xfs_hooks qi_mod_ino_dqtrx_hooks;\n\tstruct xfs_hooks qi_apply_dqtrx_hooks;\n};\n\nstruct xfs_refcount_intent {\n\tstruct list_head ri_list;\n\tstruct xfs_group *ri_group;\n\tenum xfs_refcount_intent_type ri_type;\n\txfs_extlen_t ri_blockcount;\n\txfs_fsblock_t ri_startblock;\n\tbool ri_realtime;\n};\n\ntypedef int (*xfs_refcount_query_range_fn)(struct xfs_btree_cur *, const struct xfs_refcount_irec *, void *);\n\nstruct xfs_refcount_query_range_info {\n\txfs_refcount_query_range_fn fn;\n\tvoid *priv;\n};\n\nstruct xfs_refcount_recovery {\n\tstruct list_head rr_list;\n\tstruct xfs_refcount_irec rr_rrec;\n};\n\nstruct xfs_rmap_hook {\n\tstruct xfs_hook rmap_hook;\n};\n\nstruct xfs_rmap_intent {\n\tstruct list_head ri_list;\n\tenum xfs_rmap_intent_type ri_type;\n\tint ri_whichfork;\n\tuint64_t ri_owner;\n\tstruct xfs_bmbt_irec ri_bmap;\n\tstruct xfs_group *ri_group;\n\tbool ri_realtime;\n};\n\nstruct xfs_rmap_matches {\n\tlong long unsigned int matches;\n\tlong long unsigned int non_owner_matches;\n\tlong long unsigned int bad_non_owner_matches;\n};\n\nstruct xfs_rmap_ownercount {\n\tstruct xfs_rmap_irec good;\n\tstruct xfs_rmap_irec low;\n\tstruct xfs_rmap_irec high;\n\tstruct xfs_rmap_matches *results;\n\tbool stop_on_nonmatch;\n};\n\ntypedef int (*xfs_rmap_query_range_fn)(struct xfs_btree_cur *, const struct xfs_rmap_irec *, void *);\n\nstruct xfs_rmap_query_range_info {\n\txfs_rmap_query_range_fn fn;\n\tvoid *priv;\n};\n\nstruct xfs_rmap_update_params {\n\txfs_agblock_t startblock;\n\txfs_extlen_t blockcount;\n\tstruct xfs_owner_info oinfo;\n\tbool unwritten;\n};\n\nstruct xfs_rtbuf_blkinfo {\n\t__be32 rt_magic;\n\t__be32 rt_crc;\n\t__be64 rt_owner;\n\t__be64 rt_blkno;\n\t__be64 rt_lsn;\n\tuuid_t rt_uuid;\n};\n\nstruct xfs_rtgroup {\n\tstruct xfs_group rtg_group;\n\tstruct xfs_inode *rtg_inodes[4];\n\txfs_rtxnum_t rtg_extents;\n\tunion {\n\t\tuint8_t *rtg_rsum_cache;\n\t\tstruct xfs_open_zone *rtg_open_zone;\n\t};\n\tatomic_t rtg_gccount;\n};\n\nstruct xfs_rtgroup_geometry {\n\t__u32 rg_number;\n\t__u32 rg_length;\n\t__u32 rg_sick;\n\t__u32 rg_checked;\n\t__u32 rg_flags;\n\t__u32 rg_reserved[27];\n};\n\nstruct xfs_rtrefcount_root {\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n};\n\nstruct xfs_rtrmap_root {\n\t__be16 bb_level;\n\t__be16 bb_numrecs;\n};\n\nstruct xfs_rud_log_format {\n\tuint16_t rud_type;\n\tuint16_t rud_size;\n\tuint32_t __pad;\n\tuint64_t rud_rui_id;\n};\n\nstruct xfs_rui_log_item;\n\nstruct xfs_rud_log_item {\n\tstruct xfs_log_item rud_item;\n\tstruct xfs_rui_log_item *rud_ruip;\n\tstruct xfs_rud_log_format rud_format;\n};\n\nstruct xfs_rui_log_format {\n\tuint16_t rui_type;\n\tuint16_t rui_size;\n\tuint32_t rui_nextents;\n\tuint64_t rui_id;\n\tstruct xfs_map_extent rui_extents[0];\n};\n\nstruct xfs_rui_log_item {\n\tstruct xfs_log_item rui_item;\n\tatomic_t rui_refcount;\n\tatomic_t rui_next_extent;\n\tstruct xfs_rui_log_format rui_format;\n};\n\ntypedef struct xfs_sb xfs_sb_t;\n\nstruct xfs_scrub_metadata;\n\nstruct xfs_scrub {\n\tstruct xfs_mount *mp;\n\tstruct xfs_scrub_metadata *sm;\n\tconst struct xchk_meta_ops *ops;\n\tstruct xfs_trans *tp;\n\tstruct file *file;\n\tstruct xfs_inode *ip;\n\tvoid *buf;\n\tvoid (*buf_cleanup)(void *);\n\tstruct xfile *xfile;\n\tstruct xfs_buftarg *xmbtp;\n\tuint ilock_flags;\n\tuint orphanage_ilock_flags;\n\tstruct xfs_inode *orphanage;\n\tstruct xfs_inode *tempip;\n\tuint temp_ilock_flags;\n\tunsigned int flags;\n\tunsigned int sick_mask;\n\tunsigned int healthy_mask;\n\tstruct xchk_relax relax;\n\tstruct xchk_ag sa;\n\tstruct xchk_rt sr;\n};\n\nstruct xfs_scrub_metadata {\n\t__u32 sm_type;\n\t__u32 sm_flags;\n\t__u64 sm_ino;\n\t__u32 sm_gen;\n\t__u32 sm_agno;\n\t__u64 sm_reserved[5];\n};\n\nstruct xfs_scrub_subord {\n\tstruct xfs_scrub sc;\n\tstruct xfs_scrub *parent_sc;\n\tunsigned int old_smtype;\n\tunsigned int old_smflags;\n};\n\nstruct xfs_scrub_vec {\n\t__u32 sv_type;\n\t__u32 sv_flags;\n\t__s32 sv_ret;\n\t__u32 sv_reserved;\n};\n\nstruct xfs_scrub_vec_head {\n\t__u64 svh_ino;\n\t__u32 svh_gen;\n\t__u32 svh_agno;\n\t__u32 svh_flags;\n\t__u16 svh_rest_us;\n\t__u16 svh_nr;\n\t__u64 svh_reserved;\n\t__u64 svh_vectors;\n};\n\nstruct xfs_swapext {\n\tint64_t sx_version;\n\tint64_t sx_fdtarget;\n\tint64_t sx_fdtmp;\n\txfs_off_t sx_offset;\n\txfs_off_t sx_length;\n\tchar sx_pad[16];\n\tstruct xfs_bstat sx_stat;\n};\n\ntypedef struct xfs_swapext xfs_swapext_t;\n\nstruct xfs_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, char *);\n\tssize_t (*store)(struct kobject *, const char *, size_t);\n};\n\nstruct xfs_trans {\n\tunsigned int t_log_res;\n\tunsigned int t_log_count;\n\tunsigned int t_blk_res;\n\tunsigned int t_blk_res_used;\n\tunsigned int t_rtx_res;\n\tunsigned int t_rtx_res_used;\n\tunsigned int t_flags;\n\txfs_agnumber_t t_highest_agno;\n\tstruct xlog_ticket *t_ticket;\n\tstruct xfs_mount *t_mountp;\n\tstruct xfs_dquot_acct *t_dqinfo;\n\tint64_t t_icount_delta;\n\tint64_t t_ifree_delta;\n\tint64_t t_fdblocks_delta;\n\tint64_t t_res_fdblocks_delta;\n\tint64_t t_frextents_delta;\n\tint64_t t_res_frextents_delta;\n\tint64_t t_dblocks_delta;\n\tint64_t t_agcount_delta;\n\tint64_t t_imaxpct_delta;\n\tint64_t t_rextsize_delta;\n\tint64_t t_rbmblocks_delta;\n\tint64_t t_rblocks_delta;\n\tint64_t t_rextents_delta;\n\tint64_t t_rextslog_delta;\n\tint64_t t_rgcount_delta;\n\tstruct list_head t_items;\n\tstruct list_head t_busy;\n\tstruct list_head t_dfops;\n\tlong unsigned int t_pflags;\n};\n\ntypedef struct xfs_trans xfs_trans_t;\n\nstruct xfs_trans_header {\n\tuint th_magic;\n\tuint th_type;\n\tint32_t th_tid;\n\tuint th_num_items;\n};\n\nstruct xfs_trim_cur {\n\txfs_agblock_t start;\n\txfs_extlen_t count;\n\txfs_agblock_t end;\n\txfs_extlen_t minlen;\n\tbool by_bno;\n};\n\nstruct xfs_unmount_log_format {\n\tuint16_t magic;\n\tuint16_t pad1;\n\tuint32_t pad2;\n};\n\nstruct xfs_verify_media {\n\t__u32 me_dev;\n\t__u32 me_flags;\n\t__u64 me_start_daddr;\n\t__u64 me_end_daddr;\n\t__u32 me_ioerror;\n\t__u32 me_max_io_size;\n\t__u32 me_rest_us;\n\t__u32 me_pad;\n};\n\nstruct xfs_writepage_ctx {\n\tstruct iomap_writepage_ctx ctx;\n\tunsigned int data_seq;\n\tunsigned int cow_seq;\n};\n\nstruct xfs_xmd_log_format {\n\tuint16_t xmd_type;\n\tuint16_t xmd_size;\n\tuint32_t __pad;\n\tuint64_t xmd_xmi_id;\n};\n\nstruct xfs_xmi_log_item;\n\nstruct xfs_xmd_log_item {\n\tstruct xfs_log_item xmd_item;\n\tstruct xfs_xmi_log_item *xmd_intent_log_item;\n\tstruct xfs_xmd_log_format xmd_format;\n};\n\nstruct xfs_xmi_log_format {\n\tuint16_t xmi_type;\n\tuint16_t xmi_size;\n\tuint32_t __pad;\n\tuint64_t xmi_id;\n\tuint64_t xmi_inode1;\n\tuint64_t xmi_inode2;\n\tuint32_t xmi_igen1;\n\tuint32_t xmi_igen2;\n\tuint64_t xmi_startoff1;\n\tuint64_t xmi_startoff2;\n\tuint64_t xmi_blockcount;\n\tuint64_t xmi_flags;\n\tuint64_t xmi_isize1;\n\tuint64_t xmi_isize2;\n};\n\nstruct xfs_xmi_log_item {\n\tstruct xfs_log_item xmi_item;\n\tatomic_t xmi_refcount;\n\tstruct xfs_xmi_log_format xmi_format;\n};\n\nstruct xfs_zone_alloc_ctx {\n\tstruct xfs_open_zone *open_zone;\n\txfs_filblks_t reserved_blocks;\n};\n\nstruct xfs_zone_info {\n\tspinlock_t zi_reservation_lock;\n\tstruct list_head zi_reclaim_reservations;\n\tspinlock_t zi_open_zones_lock;\n\tstruct list_head zi_open_zones;\n\tunsigned int zi_nr_open_zones;\n\tatomic_t zi_nr_free_zones;\n\twait_queue_head_t zi_zone_wait;\n\tstruct task_struct *zi_gc_thread;\n\tstruct xfs_open_zone *zi_open_gc_zone;\n\tspinlock_t zi_reset_list_lock;\n\tstruct xfs_group *zi_reset_list;\n\tspinlock_t zi_used_buckets_lock;\n\tunsigned int zi_used_bucket_entries[10];\n\tlong unsigned int *zi_used_bucket_bitmap[10];\n};\n\nstruct xfs_zoned_writepage_ctx {\n\tstruct iomap_writepage_ctx ctx;\n\tstruct xfs_open_zone *open_zone;\n};\n\nstruct xfsb_bitmap {\n\tstruct xbitmap64 fsbitmap;\n};\n\nstruct xfsstats {\n\tunion {\n\t\tstruct __xfsstats s;\n\t\tuint32_t a[262];\n\t};\n};\n\nstruct xics_cppr {\n\tunsigned char stack[3];\n\tint index;\n};\n\nstruct xive_cpu {\n\tu32 hw_ipi;\n\tstruct xive_irq_data ipi_data;\n\tint chip_id;\n\tstruct xive_q queue[8];\n\tu8 pending_prio;\n\tu8 cppr;\n};\n\nstruct xive_ipi_alloc_info {\n\tirq_hw_number_t hwirq;\n};\n\nstruct xive_ipi_desc {\n\tunsigned int irq;\n\tchar name[16];\n\tatomic_t started;\n};\n\nstruct xive_irq_bitmap {\n\tlong unsigned int *bitmap;\n\tunsigned int base;\n\tunsigned int count;\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct xive_ops {\n\tint (*populate_irq_data)(u32, struct xive_irq_data *);\n\tint (*configure_irq)(u32, u32, u8, u32);\n\tint (*get_irq_config)(u32, u32 *, u8 *, u32 *);\n\tint (*setup_queue)(unsigned int, struct xive_cpu *, u8);\n\tvoid (*cleanup_queue)(unsigned int, struct xive_cpu *, u8);\n\tvoid (*prepare_cpu)(unsigned int, struct xive_cpu *);\n\tvoid (*setup_cpu)(unsigned int, struct xive_cpu *);\n\tvoid (*teardown_cpu)(unsigned int, struct xive_cpu *);\n\tbool (*match)(struct device_node *);\n\tvoid (*shutdown)(void);\n\tvoid (*update_pending)(struct xive_cpu *);\n\tvoid (*sync_source)(u32);\n\tu64 (*esb_rw)(u32, u32, u64, bool);\n\tint (*get_ipi)(unsigned int, struct xive_cpu *);\n\tvoid (*put_ipi)(unsigned int, struct xive_cpu *);\n\tint (*debug_show)(struct seq_file *, void *);\n\tint (*debug_create)(struct dentry *);\n\tconst char *name;\n};\n\nstruct xlog_grant_head {\n\tspinlock_t lock;\n\tstruct list_head waiters;\n\tatomic64_t grant;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xlog {\n\tstruct xfs_mount *l_mp;\n\tstruct xfs_ail *l_ailp;\n\tstruct xfs_cil *l_cilp;\n\tstruct xfs_buftarg *l_targ;\n\tstruct workqueue_struct *l_ioend_workqueue;\n\tstruct delayed_work l_work;\n\tlong int l_opstate;\n\tuint l_quotaoffs_flag;\n\tstruct list_head *l_buf_cancel_table;\n\tstruct list_head r_dfops;\n\tint l_iclog_hsize;\n\tuint l_sectBBsize;\n\tint l_iclog_size;\n\tint l_iclog_bufs;\n\txfs_daddr_t l_logBBstart;\n\tint l_logsize;\n\tint l_logBBsize;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\twait_queue_head_t l_flush_wait;\n\tint l_covered_state;\n\tstruct xlog_in_core *l_iclog;\n\tspinlock_t l_icloglock;\n\tint l_curr_cycle;\n\tint l_prev_cycle;\n\tint l_curr_block;\n\tint l_prev_block;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t l_tail_lsn;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xlog_grant_head l_reserve_head;\n\tstruct xlog_grant_head l_write_head;\n\tuint64_t l_tail_space;\n\tstruct xfs_kobj l_kobj;\n\txfs_lsn_t l_recovery_lsn;\n\tuint32_t l_iclog_roundoff;\n\tlong: 64;\n};\n\nstruct xlog_cil_pcp {\n\tint32_t space_used;\n\tuint32_t space_reserved;\n\tstruct list_head busy_extents;\n\tstruct list_head log_items;\n};\n\nstruct xlog_op_header {\n\t__be32 oh_tid;\n\t__be32 oh_len;\n\t__u8 oh_clientid;\n\t__u8 oh_flags;\n\t__u16 oh_res2;\n};\n\nstruct xlog_cil_trans_hdr {\n\tstruct xlog_op_header oph[2];\n\tstruct xfs_trans_header thdr;\n\tstruct xfs_log_iovec lhdr[2];\n};\n\nstruct xlog_format_buf {\n\tstruct xfs_log_vec *lv;\n\tunsigned int idx;\n};\n\nstruct xlog_rec_header;\n\nstruct xlog_in_core {\n\twait_queue_head_t ic_force_wait;\n\twait_queue_head_t ic_write_wait;\n\tstruct xlog_in_core *ic_next;\n\tstruct xlog_in_core *ic_prev;\n\tstruct xlog *ic_log;\n\tu32 ic_size;\n\tu32 ic_offset;\n\tenum xlog_iclog_state ic_state;\n\tunsigned int ic_flags;\n\tvoid *ic_datap;\n\tstruct list_head ic_callbacks;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t ic_refcnt;\n\tstruct xlog_rec_header *ic_header;\n\tstruct semaphore ic_sema;\n\tstruct work_struct ic_end_io_work;\n\tstruct bio ic_bio;\n\tstruct bio_vec ic_bvec[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xlog_rec_ext_header {\n\t__be32 xh_cycle;\n\t__be32 xh_cycle_data[64];\n\t__u8 xh_reserved[252];\n};\n\nstruct xlog_rec_header {\n\t__be32 h_magicno;\n\t__be32 h_cycle;\n\t__be32 h_version;\n\t__be32 h_len;\n\t__be64 h_lsn;\n\t__be64 h_tail_lsn;\n\t__le32 h_crc;\n\t__be32 h_prev_block;\n\t__be32 h_num_logops;\n\t__be32 h_cycle_data[64];\n\t__be32 h_fmt;\n\tuuid_t h_fs_uuid;\n\t__be32 h_size;\n\t__u32 h_pad0;\n\t__u8 h_reserved[184];\n\tstruct xlog_rec_ext_header h_ext[0];\n};\n\nstruct xlog_recover {\n\tstruct hlist_node r_list;\n\txlog_tid_t r_log_tid;\n\tstruct xfs_trans_header r_theader;\n\tint r_state;\n\txfs_lsn_t r_lsn;\n\tstruct list_head r_itemq;\n};\n\nstruct xlog_recover_item_ops;\n\nstruct xlog_recover_item {\n\tstruct list_head ri_list;\n\tint ri_cnt;\n\tint ri_total;\n\tstruct kvec *ri_buf;\n\tconst struct xlog_recover_item_ops *ri_ops;\n};\n\nstruct xlog_recover_item_ops {\n\tuint16_t item_type;\n\tenum xlog_recover_reorder (*reorder)(struct xlog_recover_item *);\n\tvoid (*ra_pass2)(struct xlog *, struct xlog_recover_item *);\n\tint (*commit_pass1)(struct xlog *, struct xlog_recover_item *);\n\tint (*commit_pass2)(struct xlog *, struct list_head *, struct xlog_recover_item *, xfs_lsn_t);\n};\n\nstruct xlog_ticket {\n\tstruct list_head t_queue;\n\tstruct task_struct *t_task;\n\txlog_tid_t t_tid;\n\tatomic_t t_ref;\n\tint t_curr_res;\n\tint t_unit_res;\n\tchar t_ocnt;\n\tchar t_cnt;\n\tuint8_t t_flags;\n\tint t_iclog_hdrs;\n};\n\nstruct xlog_write_data {\n\tstruct xlog_ticket *ticket;\n\tstruct xlog_in_core *iclog;\n\tuint32_t bytes_left;\n\tuint32_t record_cnt;\n\tuint32_t data_cnt;\n\tint log_offset;\n};\n\nstruct xoff_bitmap {\n\tstruct xbitmap64 offbitmap;\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tlong unsigned int *bitmap;\n\tstruct page *page;\n\tlong unsigned int vaddr;\n};\n\nstruct xprt_addr {\n\tconst char *addr;\n\tstruct callback_head rcu;\n};\n\nstruct xprt_create;\n\nstruct xprt_class {\n\tstruct list_head list;\n\tint ident;\n\tstruct rpc_xprt * (*setup)(struct xprt_create *);\n\tstruct module *owner;\n\tchar name[32];\n\tconst char *netid[0];\n};\n\nstruct xprt_create {\n\tint ident;\n\tstruct net *net;\n\tstruct sockaddr *srcaddr;\n\tstruct sockaddr *dstaddr;\n\tsize_t addrlen;\n\tconst char *servername;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rpc_xprt_switch *bc_xps;\n\tunsigned int flags;\n\tstruct xprtsec_parms xprtsec;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct xps_map;\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tunsigned int nr_ids;\n\ts16 num_tc;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xreap_state {\n\tstruct xfs_scrub *sc;\n\tunion {\n\t\tstruct {\n\t\t\tconst struct xfs_owner_info *oinfo;\n\t\t\tenum xfs_ag_resv_type resv;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xfs_inode *ip;\n\t\t\tint whichfork;\n\t\t};\n\t};\n\tunsigned int nr_binval;\n\tunsigned int max_binval;\n\tunsigned int nr_deferred;\n\tunsigned int max_deferred;\n};\n\nstruct xrep_newbt {\n\tstruct xfs_scrub *sc;\n\tint (*alloc_vextent)(struct xfs_scrub *, struct xfs_alloc_arg *, xfs_fsblock_t);\n\tstruct list_head resv_list;\n\tunion {\n\t\tstruct xbtree_afakeroot afake;\n\t\tstruct xbtree_ifakeroot ifake;\n\t};\n\tstruct xfs_owner_info oinfo;\n\tstruct xfs_btree_bload bload;\n\txfs_fsblock_t alloc_hint;\n\tenum xfs_ag_resv_type resv;\n};\n\nstruct xrep_abt {\n\tstruct xagb_bitmap not_allocbt_blocks;\n\tstruct xagb_bitmap old_allocbt_blocks;\n\tstruct xrep_newbt new_bnobt;\n\tstruct xrep_newbt new_cntbt;\n\tstruct xfarray *free_records;\n\tstruct xfs_scrub *sc;\n\tuint64_t nr_real_records;\n\txfarray_idx_t array_cur;\n\txfs_agblock_t next_agbno;\n\txfs_agblock_t nr_blocks;\n\txfs_agblock_t longest;\n};\n\nstruct xrep_agf_allocbt {\n\tstruct xfs_scrub *sc;\n\txfs_agblock_t freeblks;\n\txfs_agblock_t longest;\n};\n\nstruct xrep_agfl {\n\tstruct xagb_bitmap crossed;\n\tstruct xagb_bitmap agmetablocks;\n\tstruct xagb_bitmap *freesp;\n\tstruct xfs_btree_cur *rmap_cur;\n\tstruct xfs_scrub *sc;\n};\n\nstruct xrep_agfl_fill {\n\tstruct xagb_bitmap used_extents;\n\tstruct xfs_scrub *sc;\n\t__be32 *agfl_bno;\n\txfs_agblock_t flcount;\n\tunsigned int fl_off;\n};\n\nstruct xrep_find_ag_btree {\n\tuint64_t rmap_owner;\n\tconst struct xfs_buf_ops *buf_ops;\n\tunsigned int maxlevels;\n\txfs_agblock_t root;\n\tunsigned int height;\n};\n\nstruct xrep_agi {\n\tstruct xfs_scrub *sc;\n\tstruct xfs_buf *agi_bp;\n\tstruct xrep_find_ag_btree fab[3];\n\tstruct xfs_agi old_agi;\n\tstruct xagino_bitmap iunlink_bmp;\n\txfs_agino_t iunlink_heads[64];\n\tstruct xfs_inode *lookup_batch[32];\n\tstruct xfarray *iunlink_next;\n\tstruct xfarray *iunlink_prev;\n};\n\nstruct xrep_bmap {\n\tstruct xfsb_bitmap old_bmbt_blocks;\n\tstruct xrep_newbt new_bmapbt;\n\tstruct xfarray *bmap_records;\n\tstruct xfs_scrub *sc;\n\txfs_rfsblock_t nblocks;\n\txfs_rfsblock_t old_bmbt_block_count;\n\txfarray_idx_t array_cur;\n\tuint64_t real_mappings;\n\tint whichfork;\n\tenum reflink_scan_state reflink_scan;\n\tbool allow_unwritten;\n};\n\nstruct xrep_bufscan {\n\txfs_daddr_t daddr;\n\txfs_daddr_t max_sectors;\n\txfs_daddr_t daddr_step;\n\txfs_daddr_t __sector_count;\n};\n\nstruct xrtb_bitmap {\n\tstruct xbitmap64 rtbitmap;\n};\n\nstruct xrep_cow {\n\tstruct xfs_scrub *sc;\n\tstruct xoff_bitmap bad_fileoffs;\n\tunion {\n\t\tstruct xfsb_bitmap old_cowfork_fsblocks;\n\t\tstruct xrtb_bitmap old_cowfork_rtblocks;\n\t};\n\tstruct xfs_bmbt_irec irec;\n\tunsigned int irec_startbno;\n\tunsigned int next_bno;\n};\n\nstruct xrep_cow_extent {\n\txfs_fsblock_t fsbno;\n\txfs_extlen_t len;\n};\n\nstruct xrep_tempexch {\n\tstruct xfs_exchmaps_req req;\n};\n\nstruct xrep_parent_scan_info {\n\tstruct xfs_scrub *sc;\n\tstruct xchk_iscan iscan;\n\tstruct xfs_dir_hook dhook;\n\tstruct mutex lock;\n\txfs_ino_t parent_ino;\n\tbool lookup_parent;\n};\n\nstruct xrep_dir {\n\tstruct xfs_scrub *sc;\n\tstruct xfarray *dir_entries;\n\tstruct xfblob *dir_names;\n\tstruct xrep_tempexch tx;\n\tstruct xfs_da_args args;\n\tstruct xrep_parent_scan_info pscan;\n\tstruct xrep_adoption adoption;\n\tuint64_t subdirs;\n\tunsigned int dirents;\n\tbool needs_adoption;\n\tstruct xfs_name xname;\n\tunsigned char namebuf[256];\n};\n\nstruct xrep_dirent {\n\txfblob_cookie name_cookie;\n\txfs_ino_t ino;\n\tuint8_t namelen;\n\tuint8_t ftype;\n\tuint8_t action;\n};\n\nstruct xrep_findparent_info {\n\tstruct xfs_inode *dp;\n\tstruct xfs_scrub *sc;\n\tstruct xrep_parent_scan_info *parent_scan;\n\txfs_ino_t found_parent;\n\tbool parent_tentative;\n};\n\nstruct xrep_findroot {\n\tstruct xfs_scrub *sc;\n\tstruct xfs_buf *agfl_bp;\n\tstruct xfs_agf *agf;\n\tstruct xrep_find_ag_btree *btree_info;\n};\n\nstruct xrep_ibt {\n\tstruct xfs_inobt_rec_incore rie;\n\tstruct xrep_newbt new_inobt;\n\tstruct xrep_newbt new_finobt;\n\tstruct xagb_bitmap old_iallocbt_blocks;\n\tstruct xfarray *inode_records;\n\tstruct xfs_scrub *sc;\n\tunsigned int icount;\n\tunsigned int iused;\n\tunsigned int finobt_recs;\n\txfarray_idx_t array_cur;\n};\n\nstruct xrep_inode {\n\tstruct xfs_imap imap;\n\tstruct xfs_scrub *sc;\n\txfs_rfsblock_t data_blocks;\n\txfs_rfsblock_t rt_blocks;\n\txfs_rfsblock_t attr_blocks;\n\txfs_extnum_t data_extents;\n\txfs_extnum_t rt_extents;\n\txfs_aextnum_t attr_extents;\n\tunsigned int ino_sick_mask;\n\tbool zap_acls;\n\tstruct xchk_iscan ftype_iscan;\n\tuint8_t alleged_ftype;\n};\n\nstruct xrep_newbt_resv {\n\tstruct list_head list;\n\tstruct xfs_perag *pag;\n\tstruct xfs_alloc_autoreap autoreap;\n\txfs_agblock_t agbno;\n\txfs_extlen_t len;\n\txfs_extlen_t used;\n};\n\nstruct xrep_parent {\n\tstruct xfs_scrub *sc;\n\tstruct xfarray *pptr_recs;\n\tstruct xfblob *pptr_names;\n\tstruct xfarray *xattr_records;\n\tstruct xfblob *xattr_blobs;\n\tunsigned char *xattr_name;\n\tvoid *xattr_value;\n\tunsigned int xattr_value_sz;\n\tstruct xrep_tempexch tx;\n\tstruct xrep_parent_scan_info pscan;\n\tstruct xrep_adoption adoption;\n\tstruct xfs_name xname;\n\tunsigned char namebuf[256];\n\tstruct xfs_da_args pptr_args;\n\tbool saw_pptr_updates;\n\tlong long unsigned int parents;\n};\n\nstruct xrep_parent_xattr {\n\txfblob_cookie name_cookie;\n\txfblob_cookie value_cookie;\n\tint flags;\n\tuint32_t valuelen;\n\tuint16_t namelen;\n};\n\nstruct xrep_pptr {\n\txfblob_cookie name_cookie;\n\tstruct xfs_parent_rec pptr_rec;\n\tuint8_t namelen;\n\tuint8_t action;\n};\n\nstruct xrep_refc {\n\tstruct xfarray *refcount_records;\n\tstruct xrep_newbt new_btree;\n\tstruct xagb_bitmap old_refcountbt_blocks;\n\tstruct xfs_scrub *sc;\n\txfarray_idx_t array_cur;\n\txfs_extlen_t btblocks;\n};\n\nstruct xrep_rmap {\n\tstruct xrep_newbt new_btree;\n\tstruct mutex lock;\n\tstruct xfbtree rmap_btree;\n\tstruct xfs_scrub *sc;\n\tstruct xfs_btree_cur *mcur;\n\tstruct xfs_rmap_hook rhook;\n\tstruct xchk_iscan iscan;\n\tlong long unsigned int nr_records;\n\txfs_agblock_t freesp_btblocks;\n\tunsigned int old_rmapbt_fsbcount;\n};\n\nstruct xrep_rmap_agfl {\n\tstruct xagb_bitmap *bitmap;\n\txfs_agnumber_t agno;\n};\n\nstruct xrep_rmap_find_gaps {\n\tstruct xagb_bitmap rmap_gaps;\n\txfs_agblock_t next_agbno;\n};\n\nstruct xrep_rmap_ifork {\n\tstruct xfs_rmap_irec accum;\n\tstruct xagb_bitmap bmbt_blocks;\n\tstruct xrep_rmap *rr;\n\tint whichfork;\n};\n\nstruct xrep_rmap_inodes {\n\tstruct xrep_rmap *rr;\n\tstruct xagb_bitmap inobt_blocks;\n\tstruct xagb_bitmap ichunk_blocks;\n};\n\nstruct xrep_rmap_stash_run {\n\tstruct xrep_rmap *rr;\n\tuint64_t owner;\n\tunsigned int rmap_flags;\n};\n\nstruct xrep_xattr {\n\tstruct xfs_scrub *sc;\n\tstruct xrep_tempexch tx;\n\tstruct xfarray *xattr_records;\n\tstruct xfblob *xattr_blobs;\n\tlong long unsigned int attrs_found;\n\tbool can_flush;\n\tbool live_update_aborted;\n\tstruct mutex lock;\n\tstruct xfarray *pptr_recs;\n\tstruct xfblob *pptr_names;\n\tstruct xfs_dir_hook dhook;\n\tstruct xfs_da_args pptr_args;\n\tstruct xfs_name xname;\n\tchar namebuf[256];\n};\n\nstruct xrep_xattr_key {\n\txfblob_cookie name_cookie;\n\txfblob_cookie value_cookie;\n\tint flags;\n\tuint32_t valuelen;\n\tuint16_t namelen;\n};\n\nstruct xrep_xattr_pptr {\n\txfblob_cookie name_cookie;\n\tstruct xfs_parent_rec pptr_rec;\n\tuint8_t namelen;\n\tuint8_t action;\n};\n\nstruct xsk_buff_pool {\n\tstruct device *dev;\n\tstruct net_device *netdev;\n\tstruct list_head xsk_tx_list;\n\tspinlock_t xsk_tx_list_lock;\n\trefcount_t users;\n\tstruct xdp_umem *umem;\n\tstruct work_struct work;\n\tspinlock_t rx_lock;\n\tstruct list_head free_list;\n\tstruct list_head xskb_list;\n\tu32 heads_cnt;\n\tu16 queue_id;\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tstruct xdp_desc *tx_descs;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 chunk_shift;\n\tu32 frame_len;\n\tu32 xdp_zc_max_segs;\n\tu8 tx_metadata_len;\n\tu8 cached_need_wakeup;\n\tbool uses_need_wakeup;\n\tbool unaligned;\n\tbool tx_sw_csum;\n\tvoid *addrs;\n\tspinlock_t cq_prod_lock;\n\tstruct xdp_buff_xsk *free_heads[0];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xsk_tx_metadata_ops {\n\tvoid (*tmo_request_timestamp)(void *);\n\tu64 (*tmo_fill_timestamp)(void *);\n\tvoid (*tmo_request_checksum)(u16, u16, void *);\n\tvoid (*tmo_request_launch_time)(u64, void *);\n};\n\nstruct xstats_entry {\n\tchar *desc;\n\tint endpoint;\n};\n\nstruct xstop_reason {\n\tuint32_t xstop_reason;\n\tconst char *unit_failed;\n\tconst char *description;\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n};\n\nstruct xz_dec_bcj {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t\tBCJ_ARM64 = 10,\n\t\tBCJ_RISCV = 11,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\nstruct xz_dec_lzma2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\nstruct zap_details {\n\tstruct folio *single_folio;\n\tbool even_cows;\n\tbool reclaim_pt;\n\tzap_flags_t zap_flags;\n};\n\nstruct zcrx_ctrl_export {\n\t__u32 zcrx_fd;\n\t__u32 __resv1[11];\n};\n\nstruct zcrx_ctrl_flush_rq {\n\t__u64 __resv[6];\n};\n\nstruct zcrx_ctrl {\n\t__u32 zcrx_id;\n\t__u32 op;\n\t__u64 __resv[2];\n\tunion {\n\t\tstruct zcrx_ctrl_export zc_export;\n\t\tstruct zcrx_ctrl_flush_rq zc_flush;\n\t};\n};\n\nstruct zspage;\n\nstruct zpdesc {\n\tlong unsigned int flags;\n\tstruct list_head lru;\n\tlong unsigned int movable_ops;\n\tunion {\n\t\tstruct zpdesc *next;\n\t\tlong unsigned int handle;\n\t};\n\tstruct zspage *zspage;\n\tunsigned int first_obj_offset;\n\tatomic_t _refcount;\n};\n\nstruct zs_pool_stats {\n\tatomic_long_t pages_compacted;\n};\n\nstruct zs_pool {\n\tconst char *name;\n\tstruct size_class *size_class[257];\n\tatomic_long_t pages_allocated;\n\tstruct zs_pool_stats stats;\n\tstruct shrinker *shrinker;\n\tstruct work_struct free_work;\n\trwlock_t lock;\n\tatomic_t compaction_in_progress;\n};\n\nstruct zspage_lock {\n\tspinlock_t lock;\n\tint cnt;\n\tstruct lockdep_map dep_map;\n};\n\nstruct zspage {\n\tstruct {\n\t\tunsigned int huge: 1;\n\t\tunsigned int fullness: 4;\n\t\tunsigned int class: 9;\n\t\tunsigned int magic: 8;\n\t};\n\tunsigned int inuse;\n\tunsigned int freeobj;\n\tstruct zpdesc *first_zpdesc;\n\tstruct list_head list;\n\tstruct zs_pool *pool;\n\tstruct zspage_lock zsl;\n};\n\nstruct zswap_pool;\n\nstruct zswap_entry {\n\tswp_entry_t swpentry;\n\tunsigned int length;\n\tbool referenced;\n\tstruct zswap_pool *pool;\n\tlong unsigned int handle;\n\tstruct obj_cgroup *objcg;\n\tstruct list_head lru;\n};\n\nstruct zswap_pool {\n\tstruct zs_pool *zs_pool;\n\tstruct crypto_acomp_ctx *acomp_ctx;\n\tstruct percpu_ref ref;\n\tstruct list_head list;\n\tstruct work_struct release_work;\n\tstruct hlist_node node;\n\tchar tfm_name[128];\n};\n\ntypedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs *);\n\ntypedef size_t (*HUF_DecompressUsingDTableFn)(void *, size_t, const void *, size_t, const HUF_DTable *);\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\ntypedef void blk_log_action_t(struct trace_iterator *, const char *, bool);\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef unsigned int (*bpf_dispatcher_fn)(const void *, const struct bpf_insn *, unsigned int (*)(const void *, const struct bpf_insn *));\n\ntypedef unsigned int (*bpf_func_t)(const void *, const struct bpf_insn *);\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\ntypedef u32 (*bpf_prog_run_fn)(const struct bpf_prog *, const void *);\n\ntypedef u64 (*bpf_trampoline_enter_t)(struct bpf_prog *, struct bpf_tramp_run_ctx *);\n\ntypedef void (*bpf_trampoline_exit_t)(struct bpf_prog *, u64, struct bpf_tramp_run_ctx *);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_bprm_opts_set)(struct linux_binprm *, u64);\n\ntypedef u64 (*btf_bpf_btf_find_by_name_kind)(char *, int, u32, int);\n\ntypedef u64 (*btf_bpf_cgrp_storage_delete)(struct bpf_map *, struct cgroup *);\n\ntypedef u64 (*btf_bpf_cgrp_storage_get)(struct bpf_map *, struct cgroup *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_copy_from_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_copy_from_user_task)(void *, u32, const void *, struct task_struct *, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_d_path)(const struct path *, char *, u32);\n\ntypedef u64 (*btf_bpf_dynptr_data)(const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_from_mem)(void *, u64, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_dynptr_read)(void *, u64, const struct bpf_dynptr_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_dynptr_write)(const struct bpf_dynptr_kern *, u64, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_find_vma)(struct task_struct *, u64, bpf_callback_t, void *, u64);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_for_each_map_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_get_attach_cookie)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_pe)(struct bpf_perf_event_data_kern *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_trace)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_attach_cookie_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_branch_snapshot)(void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)(void);\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)(void);\n\ntypedef u64 (*btf_bpf_get_current_task)(void);\n\ntypedef u64 (*btf_bpf_get_current_task_btf)(void);\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)(void);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_kprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_func_ip_tracing)(void *);\n\ntypedef u64 (*btf_bpf_get_func_ip_uprobe_multi)(struct pt_regs *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_local_storage)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_netns_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sk_msg)(struct sk_msg *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sockopt)(struct bpf_sockopt_kern *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_get_numa_node_id)(void);\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)(void);\n\ntypedef u64 (*btf_bpf_get_retval)(void);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)(void);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_ptr_cookie)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_pe)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_sleepable)(struct pt_regs *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_pe)(struct bpf_perf_event_data_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_get_task_stack_sleepable)(struct task_struct *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_ima_file_hash)(struct file *, void *, u32);\n\ntypedef u64 (*btf_bpf_ima_inode_hash)(struct inode *, void *, u32);\n\ntypedef u64 (*btf_bpf_inode_storage_delete)(struct bpf_map *, struct inode *);\n\ntypedef u64 (*btf_bpf_inode_storage_get)(struct bpf_map *, struct inode *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_jiffies64)(void);\n\ntypedef u64 (*btf_bpf_kallsyms_lookup_name)(const char *, int, int, u64 *);\n\ntypedef u64 (*btf_bpf_kptr_xchg)(void *, void *);\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_coarse_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_ns)(void);\n\ntypedef u64 (*btf_bpf_ktime_get_tai_ns)(void);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_loop)(u32, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_lookup_percpu_elem)(struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_per_cpu_ptr)(const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_probe_read_compat)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_redirect_neigh)(u32, struct bpf_redir_neigh *, int, u64);\n\ntypedef u64 (*btf_bpf_redirect_peer)(u32, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_reserve_dynptr)(struct bpf_map *, u32, u64, struct bpf_dynptr_kern *);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit_dynptr)(struct bpf_dynptr_kern *, u64);\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_printf_btf)(struct seq_file *, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_set_retval)(int);\n\ntypedef u64 (*btf_bpf_sk_ancestor_cgroup_id)(struct sock *, int);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_cgroup_id)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_lookup_assign)(struct bpf_sk_lookup_kern *, struct sock *, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_delete_tracing)(struct bpf_map *, struct sock *);\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_sk_storage_get_tracing)(struct bpf_map *, struct sock *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_ancestor_cgroup_id)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_cgroup_id)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_check_mtu)(struct sk_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_get_xfrm_state)(struct sk_buff *, u32, struct bpf_xfrm_state *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tstamp)(struct sk_buff *, u64, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_skc_to_mptcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_request_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_tcp_timewait_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_udp6_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skc_to_unix_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_snprintf)(char *, u32, char *, const void *, u32);\n\ntypedef u64 (*btf_bpf_snprintf_btf)(char *, u32, struct btf_ptr *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_create_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_create_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_from_file)(struct file *);\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_load_hdr_opt)(struct bpf_sock_ops_kern *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_reserve_hdr_opt)(struct bpf_sock_ops_kern *, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_store_hdr_opt)(struct bpf_sock_ops_kern *, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_strncmp)(const char *, u32, const char *);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, s64 *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, u64 *);\n\ntypedef u64 (*btf_bpf_sys_bpf)(int, union bpf_attr *, u32);\n\ntypedef u64 (*btf_bpf_sys_close)(u32);\n\ntypedef u64 (*btf_bpf_sysctl_get_current_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_get_name)(struct bpf_sysctl_kern *, char *, size_t, u64);\n\ntypedef u64 (*btf_bpf_sysctl_get_new_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_set_new_value)(struct bpf_sysctl_kern *, const char *, size_t);\n\ntypedef u64 (*btf_bpf_task_pt_regs)(struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_delete)(struct bpf_map *, struct task_struct *);\n\ntypedef u64 (*btf_bpf_task_storage_get)(struct bpf_map *, struct task_struct *, void *, u64, gfp_t);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tc_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv4)(struct iphdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_check_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv4)(struct iphdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_raw_gen_syncookie_ipv6)(struct ipv6hdr *, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_this_cpu_ptr)(const void *);\n\ntypedef u64 (*btf_bpf_timer_cancel)(struct bpf_async_kern *);\n\ntypedef u64 (*btf_bpf_timer_init)(struct bpf_async_kern *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_timer_set_callback)(struct bpf_async_kern *, void *, struct bpf_prog_aux *);\n\ntypedef u64 (*btf_bpf_timer_start)(struct bpf_async_kern *, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_trace_vprintk)(char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_unlocked_sk_getsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_unlocked_sk_setsockopt)(struct sock *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_user_ringbuf_drain)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_user_rnd_u32)(void);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_check_mtu)(struct xdp_buff *, u32, u32 *, s32, u64);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_xdp_get_buff_len)(struct xdp_buff *);\n\ntypedef u64 (*btf_bpf_xdp_load_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_store_bytes)(struct xdp_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_get_func_arg)(void *, u32, u64 *);\n\ntypedef u64 (*btf_get_func_arg_cnt)(void *);\n\ntypedef u64 (*btf_get_func_ret)(void *, u64 *);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_suspend)(void *, ktime_t, int);\n\ntypedef void (*btf_trace_alloc_vmap_area)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_arm_event)(void *, const struct cper_sec_proc_arm *, const u8 *, const u32, const u8 *, const u32, const u8 *, const u32, u8, int);\n\ntypedef void (*btf_trace_ata_bmdma_setup)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_start)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_status)(void *, struct ata_port *, unsigned int);\n\ntypedef void (*btf_trace_ata_bmdma_stop)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_about_to_do)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_done)(void *, struct ata_link *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy)(void *, struct ata_device *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy_qc)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_exec_command)(void *, struct ata_port *, const struct ata_taskfile *, unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_link_softreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_link_softreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_port_freeze)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_port_thaw)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_qc_complete_done)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_failed)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_internal)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_issue)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_prep)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_sff_flush_pio_task)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_sff_hsm_command_complete)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_hsm_state)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_sff_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_sff_port_intr)(void *, struct ata_queued_cmd *, unsigned char);\n\ntypedef void (*btf_trace_ata_slave_hardreset_begin)(void *, struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*btf_trace_ata_slave_hardreset_end)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_slave_postreset)(void *, struct ata_link *, unsigned int *, int);\n\ntypedef void (*btf_trace_ata_std_sched_eh)(void *, struct ata_port *);\n\ntypedef void (*btf_trace_ata_tf_load)(void *, struct ata_port *, const struct ata_taskfile *);\n\ntypedef void (*btf_trace_atapi_pio_transfer_data)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_atapi_send_cdb)(void *, struct ata_queued_cmd *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, struct dirty_throttle_control *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_bl_ext_tree_prepare_commit)(void *, int, size_t, u64, bool);\n\ntypedef void (*btf_trace_bl_pr_key_reg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_reg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_bl_pr_key_unreg)(void *, const struct block_device *, u64);\n\ntypedef void (*btf_trace_bl_pr_key_unreg_err)(void *, const struct block_device *, u64, int);\n\ntypedef void (*btf_trace_blk_zone_append_update_request_bio)(void *, struct request *);\n\ntypedef void (*btf_trace_blk_zone_wplug_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_blkdev_zone_mgmt)(void *, struct bio *, sector_t);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct bio *);\n\ntypedef void (*btf_trace_block_io_done)(void *, struct request *);\n\ntypedef void (*btf_trace_block_io_start)(void *, struct request *);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_error)(void *, struct request *, blk_status_t, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_merge)(void *, struct request *);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request *);\n\ntypedef void (*btf_trace_block_split)(void *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\ntypedef void (*btf_trace_bpf_trace_printk)(void *, const char *);\n\ntypedef void (*btf_trace_bpf_trigger_tp)(void *, int);\n\ntypedef void (*btf_trace_bpf_xdp_link_attach_failed)(void *, const char *);\n\ntypedef void (*btf_trace_br_fdb_add)(void *, struct ndmsg *, struct net_device *, const unsigned char *, u16, u16);\n\ntypedef void (*btf_trace_br_fdb_external_learn_add)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16);\n\ntypedef void (*btf_trace_br_fdb_update)(void *, struct net_bridge *, struct net_bridge_port *, const unsigned char *, u16, long unsigned int);\n\ntypedef void (*btf_trace_br_mdb_full)(void *, const struct net_device *, const struct br_ip *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_cache_entry_expired)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_make_negative)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_no_listener)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_upcall)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_update)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cap_capable)(void *, const struct cred *, struct user_namespace *, const struct user_namespace *, int, int);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rstat_lock_contended)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_locked)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_rstat_unlock)(void *, struct cgroup *, int, bool);\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cma_alloc_busy_retry)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_alloc_finish)(void *, const char *, long unsigned int, const struct page *, long unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_cma_alloc_start)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cma_release)(void *, const char *, long unsigned int, const struct page *, long unsigned int);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_contention_begin)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_contention_end)(void *, void *, int);\n\ntypedef void (*btf_trace_count_memcg_events)(void *, struct mem_cgroup *, int, long unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_idle_miss)(void *, unsigned int, unsigned int, bool);\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_csd_function_entry)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_function_exit)(void *, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_csd_queue_cpu)(void *, const unsigned int, long unsigned int, smp_call_func_t, call_single_data_t *);\n\ntypedef void (*btf_trace_ctime_ns_xchg)(void *, struct inode *, u32, u32, u32);\n\ntypedef void (*btf_trace_ctime_xchg_skip)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_dax_insert_pfn_mkwrite)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_insert_pfn_mkwrite_no_entry)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_load_hole)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_pmd_fault)(void *, struct inode *, struct vm_fault *, long unsigned int, int);\n\ntypedef void (*btf_trace_dax_pmd_fault_done)(void *, struct inode *, struct vm_fault *, long unsigned int, int);\n\ntypedef void (*btf_trace_dax_pmd_load_hole)(void *, struct inode *, struct vm_fault *, struct folio *, void *);\n\ntypedef void (*btf_trace_dax_pmd_load_hole_fallback)(void *, struct inode *, struct vm_fault *, struct folio *, void *);\n\ntypedef void (*btf_trace_dax_pte_fault)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_pte_fault_done)(void *, struct inode *, struct vm_fault *, int);\n\ntypedef void (*btf_trace_dax_writeback_one)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dax_writeback_range)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dax_writeback_range_done)(void *, struct inode *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_device_pm_callback_end)(void *, struct device *, int);\n\ntypedef void (*btf_trace_device_pm_callback_start)(void *, struct device *, const char *, int);\n\ntypedef void (*btf_trace_devlink_health_recover_aborted)(void *, const struct devlink *, const char *, bool, u64);\n\ntypedef void (*btf_trace_devlink_health_report)(void *, const struct devlink *, const char *, const char *);\n\ntypedef void (*btf_trace_devlink_health_reporter_state_update)(void *, const struct devlink *, const char *, bool);\n\ntypedef void (*btf_trace_devlink_hwerr)(void *, const struct devlink *, int, const char *);\n\ntypedef void (*btf_trace_devlink_hwmsg)(void *, const struct devlink *, bool, long unsigned int, const u8 *, size_t);\n\ntypedef void (*btf_trace_devlink_trap_report)(void *, const struct devlink *, struct sk_buff *, const struct devlink_trap_metadata *);\n\ntypedef void (*btf_trace_devres_log)(void *, struct device *, const char *, void *, const char *, size_t);\n\ntypedef void (*btf_trace_disk_zone_wplug_add_bio)(void *, struct request_queue *, unsigned int, sector_t, unsigned int);\n\ntypedef void (*btf_trace_dma_alloc)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_alloc_sgt_err)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, gfp_t, long unsigned int);\n\ntypedef void (*btf_trace_dma_buf_detach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_dynamic_attach)(void *, struct dma_buf *, struct dma_buf_attachment *, bool, struct device *);\n\ntypedef void (*btf_trace_dma_buf_export)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_fd)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_get)(void *, struct dma_buf *, int);\n\ntypedef void (*btf_trace_dma_buf_mmap)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_mmap_internal)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_buf_put)(void *, struct dma_buf *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_free)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_pages)(void *, struct device *, void *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_free_sgt)(void *, struct device *, struct sg_table *, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_map_phys)(void *, struct device *, phys_addr_t, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_map_sg_err)(void *, struct device *, struct scatterlist *, int, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_sync_sg_for_cpu)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_sg_for_device)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_cpu)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_sync_single_for_device)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\ntypedef void (*btf_trace_dma_unmap_phys)(void *, struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_dma_unmap_sg)(void *, struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\ntypedef void (*btf_trace_doorbell_entry)(void *, struct pt_regs *);\n\ntypedef void (*btf_trace_doorbell_exit)(void *, struct pt_regs *);\n\ntypedef void (*btf_trace_dql_stall_detected)(void *, short unsigned int, unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_e1000e_trace_mac_register)(void *, uint32_t);\n\ntypedef void (*btf_trace_error_report_end)(void *, enum error_detector, long unsigned int);\n\ntypedef void (*btf_trace_exit_mmap)(void *, struct mm_struct *);\n\ntypedef void (*btf_trace_ext4_alloc_da_blocks)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_allocate_blocks)(void *, struct ext4_allocation_request *, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_allocate_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_begin_ordered_truncate)(void *, struct inode *, loff_t);\n\ntypedef void (*btf_trace_ext4_collapse_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_da_release_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_reserve_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_da_update_reserve_space)(void *, struct inode *, int, int);\n\ntypedef void (*btf_trace_ext4_da_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_end)(void *, struct inode *, loff_t, loff_t, struct writeback_control *, int);\n\ntypedef void (*btf_trace_ext4_da_write_folios_start)(void *, struct inode *, loff_t, loff_t, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages_extent)(void *, struct inode *, struct ext4_map_blocks *);\n\ntypedef void (*btf_trace_ext4_discard_blocks)(void *, struct super_block *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_discard_preallocations)(void *, struct inode *, unsigned int);\n\ntypedef void (*btf_trace_ext4_drop_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_error)(void *, struct super_block *, const char *, unsigned int);\n\ntypedef void (*btf_trace_ext4_es_cache_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_exit)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_insert_delayed_extent)(void *, struct inode *, struct extent_status *, bool, bool);\n\ntypedef void (*btf_trace_ext4_es_insert_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_exit)(void *, struct inode *, struct extent_status *, int);\n\ntypedef void (*btf_trace_ext4_es_remove_extent)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_shrink)(void *, struct super_block *, int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_count)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_enter)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_exit)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_enter)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_fastpath)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_handle_unwritten_extents)(void *, struct inode *, struct ext4_map_blocks *, int, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_load_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space_done)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, struct partial_cluster *, __le16);\n\ntypedef void (*btf_trace_ext4_ext_rm_idx)(void *, struct inode *, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_rm_leaf)(void *, struct inode *, ext4_lblk_t, struct ext4_extent *, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_show_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t, short unsigned int);\n\ntypedef void (*btf_trace_ext4_fallocate_enter)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_fallocate_exit)(void *, struct inode *, loff_t, unsigned int, int);\n\ntypedef void (*btf_trace_ext4_fc_cleanup)(void *, journal_t *, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_start)(void *, struct super_block *, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_commit_stop)(void *, struct super_block *, int, int, tid_t);\n\ntypedef void (*btf_trace_ext4_fc_replay)(void *, struct super_block *, int, int, int, int);\n\ntypedef void (*btf_trace_ext4_fc_replay_scan)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_fc_stats)(void *, struct super_block *);\n\ntypedef void (*btf_trace_ext4_fc_track_create)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_inode)(void *, handle_t *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_link)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_fc_track_range)(void *, handle_t *, struct inode *, long int, long int, int);\n\ntypedef void (*btf_trace_ext4_fc_track_unlink)(void *, handle_t *, struct inode *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_forget)(void *, struct inode *, int, __u64);\n\ntypedef void (*btf_trace_ext4_free_blocks)(void *, struct inode *, __u64, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_fsmap_high_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_low_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_mapping)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_get_implied_cluster_alloc_exit)(void *, struct super_block *, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_getfsmap_high_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_low_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_mapping)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_insert_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journal_start_inode)(void *, struct inode *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_reserved)(void *, struct super_block *, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_sb)(void *, struct super_block *, int, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_invalidate_folio)(void *, struct folio *, size_t, size_t);\n\ntypedef void (*btf_trace_ext4_journalled_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_lazy_itable_init)(void *, struct super_block *, ext4_group_t);\n\ntypedef void (*btf_trace_ext4_load_inode)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_load_inode_bitmap)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mark_inode_dirty)(void *, struct inode *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_buddy_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_discard_preallocations)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_mb_new_group_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_new_inode_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_group_pa)(void *, struct super_block *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_inode_pa)(void *, struct ext4_prealloc_space *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_mballoc_alloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_discard)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_free)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_prealloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_move_extent_enter)(void *, struct inode *, struct ext4_map_blocks *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_move_extent_exit)(void *, struct inode *, ext4_lblk_t, struct inode *, ext4_lblk_t, unsigned int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_nfs_commit_metadata)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_other_inode_update_time)(void *, struct inode *, ino_t);\n\ntypedef void (*btf_trace_ext4_prefetch_bitmaps)(void *, struct super_block *, ext4_group_t, ext4_group_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_punch_hole)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_read_block_bitmap_load)(void *, struct super_block *, long unsigned int, bool);\n\ntypedef void (*btf_trace_ext4_read_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_release_folio)(void *, struct inode *, struct folio *);\n\ntypedef void (*btf_trace_ext4_remove_blocks)(void *, struct inode *, struct ext4_extent *, ext4_lblk_t, ext4_fsblk_t, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_request_blocks)(void *, struct ext4_allocation_request *);\n\ntypedef void (*btf_trace_ext4_request_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_shutdown)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_sync_file_enter)(void *, struct file *, int);\n\ntypedef void (*btf_trace_ext4_sync_file_exit)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_sync_fs)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_trim_all_free)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_trim_extent)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_truncate_enter)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_truncate_exit)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_unlink_enter)(void *, struct inode *, struct dentry *);\n\ntypedef void (*btf_trace_ext4_unlink_exit)(void *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_update_sb)(void *, struct super_block *, ext4_fsblk_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_begin)(void *, struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_writepages)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_writepages_result)(void *, struct inode *, struct writeback_control *, int, int);\n\ntypedef void (*btf_trace_ext4_zero_range)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_fdb_delete)(void *, struct net_bridge *, struct net_bridge_fdb_entry *);\n\ntypedef void (*btf_trace_ff_layout_commit_error)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_ff_layout_read_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_ff_layout_write_error)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_fib6_table_lookup)(void *, const struct net *, const struct fib6_result *, struct fib6_table *, const struct flowi6 *);\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_fill_mg_cmtime)(void *, struct inode *, struct timespec64 *, struct timespec64 *);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_fl_getdevinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, char *);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_flush_foreign)(void *, struct bdi_writeback *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_folio_wait_writeback)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_free_vmap_area_noflush)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_guest_halt_poll_ns)(void *, bool, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_handshake_cancel)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_busy)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cancel_none)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_cmd_accept)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_accept_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_cmd_done_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_complete)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_destruct)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_notify_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_handshake_submit)(void *, const struct net *, const struct handshake_req *, const struct sock *);\n\ntypedef void (*btf_trace_handshake_submit_err)(void *, const struct net *, const struct handshake_req *, const struct sock *, int);\n\ntypedef void (*btf_trace_hash_fault)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_hcall_entry)(void *, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_hcall_exit)(void *, long unsigned int, long int, long unsigned int *);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_setup)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hugepage_set_pmd)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_hugepage_set_pud)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_hugepage_update_pmd)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_hugepage_update_pud)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_hugetlbfs_alloc_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_hugetlbfs_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_fallocate)(void *, struct inode *, int, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_hugetlbfs_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_hugetlbfs_setattr)(void *, struct inode *, struct dentry *, struct iattr *);\n\ntypedef void (*btf_trace_hwmon_attr_show)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_hwmon_attr_show_string)(void *, int, const char *, const char *);\n\ntypedef void (*btf_trace_hwmon_attr_store)(void *, int, const char *, long long int);\n\ntypedef void (*btf_trace_i2c_read)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_reply)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_result)(void *, const struct i2c_adapter *, int, int);\n\ntypedef void (*btf_trace_i2c_write)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_icmp_send)(void *, const struct sk_buff *, int, int);\n\ntypedef void (*btf_trace_inet_sk_error_report)(void *, const struct sock *);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_inode_foreign_history)(void *, struct inode *, struct writeback_control *, unsigned int);\n\ntypedef void (*btf_trace_inode_set_ctime_to_ts)(void *, struct inode *, struct timespec64 *);\n\ntypedef void (*btf_trace_inode_switch_wbs)(void *, struct inode *, struct bdi_writeback *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_inode_switch_wbs_queue)(void *, struct bdi_writeback *, struct bdi_writeback *, unsigned int);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, struct io_ring_ctx *, void *, struct io_uring_cqe *);\n\ntypedef void (*btf_trace_io_uring_cqe_overflow)(void *, void *, long long unsigned int, s32, u32, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, struct io_kiocb *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_local_work_run)(void *, void *, int, unsigned int);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, struct io_kiocb *, int, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, struct io_kiocb *, bool);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, long int);\n\ntypedef void (*btf_trace_io_uring_req_failed)(void *, const struct io_uring_sqe *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_short_write)(void *, void *, u64, u64, u64);\n\ntypedef void (*btf_trace_io_uring_submit_req)(void *, struct io_kiocb *);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, struct io_kiocb *, int);\n\ntypedef void (*btf_trace_io_uring_task_work_run)(void *, void *, unsigned int);\n\ntypedef void (*btf_trace_iomap_add_to_ioend)(void *, struct inode *, u64, unsigned int, struct iomap *);\n\ntypedef void (*btf_trace_iomap_dio_complete)(void *, struct kiocb *, int, ssize_t);\n\ntypedef void (*btf_trace_iomap_dio_invalidate_fail)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_dio_rw_begin)(void *, struct kiocb *, struct iov_iter *, unsigned int, size_t);\n\ntypedef void (*btf_trace_iomap_dio_rw_queued)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_invalidate_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_iter)(void *, struct iomap_iter *, const void *, long unsigned int);\n\ntypedef void (*btf_trace_iomap_iter_dstmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_iter_srcmap)(void *, struct inode *, struct iomap *);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_release_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_writeback_folio)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_iomap_zero_iter)(void *, struct inode *, loff_t, u64);\n\ntypedef void (*btf_trace_ipi_send_cpu)(void *, const unsigned int, long unsigned int, void *);\n\ntypedef void (*btf_trace_ipi_send_cpumask)(void *, const struct cpumask *, long unsigned int, void *);\n\ntypedef void (*btf_trace_irq_entry)(void *, struct pt_regs *);\n\ntypedef void (*btf_trace_irq_exit)(void *, struct pt_regs *);\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_jbd2_checkpoint)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_checkpoint_stats)(void *, dev_t, tid_t, struct transaction_chp_stats_s *);\n\ntypedef void (*btf_trace_jbd2_commit_flushing)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_locking)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_logging)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_drop_transaction)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_end_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_handle_extend)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int);\n\ntypedef void (*btf_trace_jbd2_handle_restart)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_start)(void *, dev_t, tid_t, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_stats)(void *, dev_t, tid_t, unsigned int, unsigned int, int, int, int, int);\n\ntypedef void (*btf_trace_jbd2_lock_buffer_stall)(void *, dev_t, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_run_stats)(void *, dev_t, tid_t, struct transaction_run_stats_s *);\n\ntypedef void (*btf_trace_jbd2_shrink_checkpoint_list)(void *, journal_t *, tid_t, tid_t, tid_t, long unsigned int, tid_t);\n\ntypedef void (*btf_trace_jbd2_shrink_count)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_enter)(void *, journal_t *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_shrink_scan_exit)(void *, journal_t *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_start_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_submit_inode_data)(void *, struct inode *);\n\ntypedef void (*btf_trace_jbd2_update_log_tail)(void *, journal_t *, tid_t, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_write_superblock)(void *, journal_t *, blk_opf_t);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *, enum skb_drop_reason, struct sock *);\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, struct kmem_cache *, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *, const struct kmem_cache *);\n\ntypedef void (*btf_trace_ksm_advisor)(void *, s64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ksm_enter)(void *, void *);\n\ntypedef void (*btf_trace_ksm_exit)(void *, void *);\n\ntypedef void (*btf_trace_ksm_merge_one_page)(void *, long unsigned int, void *, void *, int);\n\ntypedef void (*btf_trace_ksm_merge_with_ksm_page)(void *, void *, long unsigned int, void *, void *, int);\n\ntypedef void (*btf_trace_ksm_remove_ksm_page)(void *, long unsigned int);\n\ntypedef void (*btf_trace_ksm_remove_rmap_item)(void *, long unsigned int, void *, void *);\n\ntypedef void (*btf_trace_ksm_start_scan)(void *, int, u32);\n\ntypedef void (*btf_trace_ksm_stop_scan)(void *, int, u32);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, dev_t, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_latency)(void *, dev_t, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, dev_t, const char *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lease *, struct file_lease *);\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_ma_op)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_read)(void *, const char *, struct ma_state *);\n\ntypedef void (*btf_trace_ma_write)(void *, const char *, struct ma_state *, long unsigned int, void *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_mark_victim)(void *, struct task_struct *, uid_t);\n\ntypedef void (*btf_trace_mc_event)(void *, const unsigned int, const char *, const char *, const int, const u8, const s8, const s8, const s8, long unsigned int, const u8, long unsigned int, const char *);\n\ntypedef void (*btf_trace_mdio_access)(void *, struct mii_bus *, char, u8, unsigned int, u16, int);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_memcg_flush_stats)(void *, struct mem_cgroup *, s64, bool, bool);\n\ntypedef void (*btf_trace_mm_calculate_totalreserve_pages)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page)(void *, struct mm_struct *, int, int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page_isolate)(void *, struct folio *, int, int, int);\n\ntypedef void (*btf_trace_mm_collapse_huge_page_swapin)(void *, struct mm_struct *, int, int, int);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, struct compact_control *, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, struct compact_control *, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_fast_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_filemap_fault)(void *, struct address_space *, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_get_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_filemap_map_pages)(void *, struct address_space *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_khugepaged_collapse_file)(void *, struct mm_struct *, struct folio *, long unsigned int, long unsigned int, bool, struct file *, int, int);\n\ntypedef void (*btf_trace_mm_khugepaged_scan_file)(void *, struct mm_struct *, struct folio *, struct file *, int, int, int);\n\ntypedef void (*btf_trace_mm_khugepaged_scan_pmd)(void *, struct mm_struct *, struct folio *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct folio *);\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_migrate_pages_start)(void *, enum migrate_mode, int);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_lowmem_reserve)(void *, struct zone *, struct zone *, long int);\n\ntypedef void (*btf_trace_mm_setup_per_zone_wmarks)(void *, struct zone *);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_clear_hopeless)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_reclaim_fail)(void *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_memcg_softlimit_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_vmscan_reclaim_pages)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *);\n\ntypedef void (*btf_trace_mm_vmscan_throttled)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_write_folio)(void *, struct folio *);\n\ntypedef void (*btf_trace_mmap_lock_acquire_returned)(void *, struct mm_struct *, bool, bool);\n\ntypedef void (*btf_trace_mmap_lock_released)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mmap_lock_start_locking)(void *, struct mm_struct *, bool);\n\ntypedef void (*btf_trace_mod_memcg_lruvec_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_mod_memcg_state)(void *, struct mem_cgroup *, int, int);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netlink_extack)(void *, const char *);\n\ntypedef void (*btf_trace_nfs41_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_access)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_bind_conn_to_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_cached_open)(void *, const struct nfs4_state *);\n\ntypedef void (*btf_trace_nfs4_cb_getattr)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_cb_layoutrecall_file)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_offload)(void *, const struct nfs_fh *, const nfs4_stateid *, uint64_t, int, int);\n\ntypedef void (*btf_trace_nfs4_cb_recall)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_seqid_err)(void *, const struct cb_sequenceargs *, __be32);\n\ntypedef void (*btf_trace_nfs4_cb_sequence)(void *, const struct cb_sequenceargs *, const struct cb_sequenceres *, __be32);\n\ntypedef void (*btf_trace_nfs4_close)(void *, const struct nfs4_state *, const struct nfs_closeargs *, const struct nfs_closeres *, int);\n\ntypedef void (*btf_trace_nfs4_close_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_commit)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_create_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn_exit)(void *, const struct nfs4_delegreturnargs *, const struct nfs4_delegreturnres *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_clientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_destroy_session)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_detach_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_deviceid_free)(void *, const struct nfs_client *, const struct nfs4_deviceid *);\n\ntypedef void (*btf_trace_nfs4_exchange_id)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_find_deviceid)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_fsinfo)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_get_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_get_fs_locations)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_get_lock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_getattr)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_getdeviceinfo)(void *, const struct nfs_server *, const struct nfs4_deviceid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutcommit)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layouterror)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutget)(void *, const struct nfs_open_context *, const struct pnfs_layout_range *, const struct pnfs_layout_range *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutreturn_on_close)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_layoutstats)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_lookup)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_lookup_root)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_lookupp)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_map_gid_to_group)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_group_to_gid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_name_to_uid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_uid_to_name)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_match_stateid)(void *, const nfs4_stateid *, const nfs4_stateid *);\n\ntypedef void (*btf_trace_nfs4_mkdir)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_mknod)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_open_expired)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_file)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_reclaim)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_skip)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_commit_ds)(void *, const struct nfs_commit_data *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_pnfs_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_readdir)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_readlink)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_complete)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_reclaim_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_remove)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_rename)(void *, const struct inode *, const struct qstr *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_renew)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_renew_async)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_secinfo)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_sequence)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_sequence_done)(void *, const struct nfs4_session *, const struct nfs4_sequence_res *);\n\ntypedef void (*btf_trace_nfs4_set_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_set_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_set_lock)(void *, const struct file_lock *, const struct nfs4_state *, const nfs4_stateid *, int, int);\n\ntypedef void (*btf_trace_nfs4_setattr)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid_confirm)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setup_sequence)(void *, const struct nfs4_session *, const struct nfs4_sequence_args *);\n\ntypedef void (*btf_trace_nfs4_state_lock_reclaim)(void *, const struct nfs4_state *, const struct nfs4_lock_state *);\n\ntypedef void (*btf_trace_nfs4_state_mgr)(void *, const struct nfs_client *);\n\ntypedef void (*btf_trace_nfs4_state_mgr_failed)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_symlink)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_test_delegation_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_lock_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_test_open_stateid)(void *, const struct nfs4_state *, const struct nfs4_lock_state *, int);\n\ntypedef void (*btf_trace_nfs4_trunked_exchange_id)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_unlock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_filehandle)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_bad_operation)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs4_xdr_status)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs_access_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_access_exit)(void *, const struct inode *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readahead)(void *, const struct inode *, loff_t, unsigned int);\n\ntypedef void (*btf_trace_nfs_aop_readahead_done)(void *, const struct inode *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_aop_readpage)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_aop_readpage_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_async_rename_done)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_atomic_open_enter)(void *, const struct inode *, const struct nfs_open_context *, unsigned int);\n\ntypedef void (*btf_trace_nfs_atomic_open_exit)(void *, const struct inode *, const struct nfs_open_context *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_cb_badprinc)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_cb_no_clp)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_commit_done)(void *, const struct rpc_task *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_commit_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_comp_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_create_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_create_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_delegation_need_return)(void *, const struct nfs_delegation *);\n\ntypedef void (*btf_trace_nfs_direct_commit_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_resched_write)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_complete)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_completion)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_reschedule_io)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_direct_write_schedule_iovec)(void *, const struct nfs_direct_req *);\n\ntypedef void (*btf_trace_nfs_do_writepage)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_fh_to_dentry)(void *, const struct super_block *, const struct nfs_fh *, u64, int);\n\ntypedef void (*btf_trace_nfs_file_read)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_file_write)(void *, const struct kiocb *, const struct iov_iter *);\n\ntypedef void (*btf_trace_nfs_fsync_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_fsync_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_getattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_getattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_initiate_commit)(void *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_initiate_read)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_initiate_write)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_invalidate_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_launder_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_link_enter)(void *, const struct inode *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_link_exit)(void *, const struct inode *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_local_open_fh)(void *, const struct nfs_fh *, fmode_t, int);\n\ntypedef void (*btf_trace_nfs_lookup_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_mkdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mkdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mknod_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mknod_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mount_assign)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_nfs_mount_option)(void *, const struct fs_parameter *);\n\ntypedef void (*btf_trace_nfs_mount_path)(void *, const char *);\n\ntypedef void (*btf_trace_nfs_pgio_error)(void *, const struct nfs_pgio_header *, int, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_cache_fill_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readdir_force_readdirplus)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_readdir_invalidate_cache_range)(void *, const struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_nfs_readdir_lookup)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_readdir_lookup_revalidate_failed)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached)(void *, const struct file *, const __be32 *, u64, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_nfs_readdir_uncached_done)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_readpage_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_readpage_short)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_remove_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_remove_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_rename_enter)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rename_exit)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_rmdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rmdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_set_cache_invalid)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_set_inode_stale)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_sillyrename_unlink)(void *, const struct nfs_unlinkdata *, int);\n\ntypedef void (*btf_trace_nfs_size_grow)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_truncate_folio)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_update)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_size_wcc)(void *, const struct inode *, loff_t);\n\ntypedef void (*btf_trace_nfs_symlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_symlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_try_to_update_request)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_try_to_update_request_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_unlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_unlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_update_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_update_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_begin)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_begin_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_end)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_write_end_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_write_error)(void *, const struct inode *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_writeback_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_writeback_folio)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writeback_folio_reclaim_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_writeback_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_writeback_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_writepage_setup)(void *, const struct nfs_page *);\n\ntypedef void (*btf_trace_nfs_writepages)(void *, const struct inode *, loff_t, size_t);\n\ntypedef void (*btf_trace_nfs_writepages_done)(void *, const struct inode *, loff_t, size_t, int);\n\ntypedef void (*btf_trace_nfs_xdr_bad_filehandle)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nfs_xdr_status)(void *, const struct xdr_stream *, int);\n\ntypedef void (*btf_trace_nlmclnt_grant)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_lock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_test)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_nlmclnt_unlock)(void *, const struct nlm_lock *, const struct sockaddr *, unsigned int, __be32);\n\ntypedef void (*btf_trace_non_standard_event)(void *, const guid_t *, const guid_t *, const char *, const u8, const u8 *, const u32);\n\ntypedef void (*btf_trace_notifier_register)(void *, void *);\n\ntypedef void (*btf_trace_notifier_run)(void *, void *);\n\ntypedef void (*btf_trace_notifier_unregister)(void *, void *);\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_opal_entry)(void *, long unsigned int, long unsigned int *);\n\ntypedef void (*btf_trace_opal_exit)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_async_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_ra_order)(void *, struct inode *, long unsigned int, struct file_ra_state *);\n\ntypedef void (*btf_trace_page_cache_ra_unbounded)(void *, struct inode *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_page_cache_sync_ra)(void *, struct inode *, long unsigned int, struct file_ra_state *, long unsigned int);\n\ntypedef void (*btf_trace_page_pool_release)(void *, const struct page_pool *, s32, u32, u32);\n\ntypedef void (*btf_trace_page_pool_state_hold)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_state_release)(void *, const struct page_pool *, netmem_ref, u32);\n\ntypedef void (*btf_trace_page_pool_update_nid)(void *, const struct page_pool *, int);\n\ntypedef void (*btf_trace_pci_hp_event)(void *, const char *, const char *, const int);\n\ntypedef void (*btf_trace_pcie_link_event)(void *, struct pci_bus *, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pelt_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_pelt_dl_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_hw_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_irq_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_rt_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_pelt_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, long unsigned int, bool, bool, size_t, size_t, void *, int, void *, size_t, gfp_t);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pmap_register)(void *, u32, u32, int, short unsigned int);\n\ntypedef void (*btf_trace_pnfs_ds_connect)(void *, char *, int);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_get_mirror_count)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_read)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_pg_init_write)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_read_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_done)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_mds_fallback_write_pagelist)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *);\n\ntypedef void (*btf_trace_pnfs_update_layout)(void *, struct inode *, loff_t, u64, enum pnfs_iomode, struct pnfs_layout_hdr *, struct pnfs_layout_segment *, enum pnfs_update_layout_reason);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_powernv_throttle)(void *, int, const char *, int);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_purge_vmap_area_lazy)(void *, long unsigned int, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_enqueue)(void *, struct Qdisc *, const struct netdev_queue *, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_invoke_kvfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_nocb_wake)(void *, const char *, int, const char *);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_segcb_stats)(void *, struct rcu_segcblist *, const char *);\n\ntypedef void (*btf_trace_rcu_sr_normal)(void *, const char *, struct callback_head *, const char *);\n\ntypedef void (*btf_trace_rcu_stall_warning)(void *, const char *, const char *);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_watching)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_regcache_drop_region)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regcache_sync)(void *, struct regmap *, const char *, const char *);\n\ntypedef void (*btf_trace_regmap_async_complete_done)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_start)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_io_complete)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_bulk_read)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_bulk_write)(void *, struct regmap *, unsigned int, const void *, int);\n\ntypedef void (*btf_trace_regmap_cache_bypass)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_cache_only)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_hw_read_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_read_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_reg_read)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read_cache)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_write)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_migration_pmd)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_remove_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_rpc__auth_tooweak)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__bad_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__garbage_args)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__proc_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__stale_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__unparsable)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_callhdr)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_verifier)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_buf_alloc)(void *, const struct rpc_task *, int);\n\ntypedef void (*btf_trace_rpc_call_rpcerror)(void *, const struct rpc_task *, int, int);\n\ntypedef void (*btf_trace_rpc_call_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_clnt_clone_err)(void *, const struct rpc_clnt *, int);\n\ntypedef void (*btf_trace_rpc_clnt_free)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_killall)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_new)(void *, const struct rpc_clnt *, const struct rpc_xprt *, const struct rpc_create_args *);\n\ntypedef void (*btf_trace_rpc_clnt_new_err)(void *, const char *, const char *, int);\n\ntypedef void (*btf_trace_rpc_clnt_release)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt_err)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_shutdown)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_connect_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_request)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_retry_refresh_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_socket_close)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_connect)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_error)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_nospace)(void *, const struct rpc_rqst *, const struct sock_xprt *);\n\ntypedef void (*btf_trace_rpc_socket_reset_connection)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_shutdown)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_state_change)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_stats_latency)(void *, const struct rpc_task *, ktime_t, ktime_t, ktime_t);\n\ntypedef void (*btf_trace_rpc_task_begin)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_call_done)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_complete)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_end)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_run_action)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_signalled)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sleep)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_task_sync_sleep)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sync_wake)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_timeout)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_wakeup)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_timeout_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_tls_not_started)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_tls_unavailable)(void *, const struct rpc_clnt *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_rpc_xdr_alignment)(void *, const struct xdr_stream *, size_t, unsigned int);\n\ntypedef void (*btf_trace_rpc_xdr_overflow)(void *, const struct xdr_stream *, size_t);\n\ntypedef void (*btf_trace_rpc_xdr_recvfrom)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_reply_pages)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_sendto)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpcb_bind_version_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_getport)(void *, const struct rpc_clnt *, const struct rpc_task *, unsigned int);\n\ntypedef void (*btf_trace_rpcb_prog_unavail_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_register)(void *, u32, u32, const char *, const char *);\n\ntypedef void (*btf_trace_rpcb_setport)(void *, const struct rpc_task *, int, short unsigned int);\n\ntypedef void (*btf_trace_rpcb_timeout_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unreachable_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unrecognized_err)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcb_unregister)(void *, u32, u32, const char *);\n\ntypedef void (*btf_trace_rpcgss_bad_seqno)(void *, const struct rpc_task *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_context)(void *, u32, long unsigned int, long unsigned int, unsigned int, unsigned int, const u8 *);\n\ntypedef void (*btf_trace_rpcgss_createauth)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rpcgss_ctx_destroy)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_ctx_init)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_get_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_import_ctx)(void *, int);\n\ntypedef void (*btf_trace_rpcgss_need_reencode)(void *, const struct rpc_task *, u32, bool);\n\ntypedef void (*btf_trace_rpcgss_oid_to_mech)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_seqno)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_svc_accept_upcall)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_authenticate)(void *, const struct svc_rqst *, const struct rpc_gss_wire_cred *);\n\ntypedef void (*btf_trace_rpcgss_svc_get_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_mic)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_bad)(void *, const struct svc_rqst *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_large)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_low)(void *, const struct svc_rqst *, u32, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_seqno_seen)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_unwrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap)(void *, const struct svc_rqst *, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_wrap_failed)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_rpcgss_unwrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_unwrap_failed)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_upcall_msg)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_upcall_result)(void *, u32, int);\n\ntypedef void (*btf_trace_rpcgss_update_slack)(void *, const struct rpc_task *, const struct rpc_auth *);\n\ntypedef void (*btf_trace_rpcgss_verify_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_wrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpm_idle)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_resume)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_return_int)(void *, struct device *, long unsigned int, int);\n\ntypedef void (*btf_trace_rpm_status)(void *, struct device *, enum rpm_status);\n\ntypedef void (*btf_trace_rpm_suspend)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_usage)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int);\n\ntypedef void (*btf_trace_rtas_input)(void *, struct rtas_args *, const char *);\n\ntypedef void (*btf_trace_rtas_ll_entry)(void *, struct rtas_args *);\n\ntypedef void (*btf_trace_rtas_ll_exit)(void *, struct rtas_args *);\n\ntypedef void (*btf_trace_rtas_output)(void *, struct rtas_args *, const char *);\n\ntypedef void (*btf_trace_rtc_alarm_irq_enable)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_freq)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_state)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_read_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_read_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_set_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_timer_dequeue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_enqueue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_fired)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sched_compute_energy_tp)(void *, struct task_struct *, int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_sched_cpu_capacity_tp)(void *, struct rq *);\n\ntypedef void (*btf_trace_sched_entry_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_exit_tp)(void *, bool);\n\ntypedef void (*btf_trace_sched_ext_bypass_lb)(void *, __u32, __u32, __u32, __u32, __u32, __u32, __u32, __u32);\n\ntypedef void (*btf_trace_sched_ext_dump)(void *, const char *);\n\ntypedef void (*btf_trace_sched_ext_event)(void *, const char *, __s64);\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_end)(void *, struct kthread_work *, kthread_work_func_t);\n\ntypedef void (*btf_trace_sched_kthread_work_execute_start)(void *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_kthread_work_queue_work)(void *, struct kthread_worker *, struct kthread_work *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_move_numa)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_overutilized_tp)(void *, struct root_domain *, bool);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_prepare_exec)(void *, struct task_struct *, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_hang)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_set_need_resched_tp)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_skip_cpuset_numa)(void *, struct task_struct *, nodemask_t *);\n\ntypedef void (*btf_trace_sched_skip_vma_numa)(void *, struct mm_struct *, struct vm_area_struct *, enum numa_vmaskip_reason);\n\ntypedef void (*btf_trace_sched_stat_blocked)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_iowait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_sleep)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_wait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stick_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_swap_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *, unsigned int);\n\ntypedef void (*btf_trace_sched_update_nr_running_tp)(void *, struct rq *, int);\n\ntypedef void (*btf_trace_sched_util_est_cfs_tp)(void *, struct cfs_rq *);\n\ntypedef void (*btf_trace_sched_util_est_se_tp)(void *, struct sched_entity *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\ntypedef void (*btf_trace_selinux_audited)(void *, struct selinux_audit_data *, char *, char *, const char *);\n\ntypedef void (*btf_trace_set_migration_pmd)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_set_migration_pte)(void *, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sk_data_ready)(void *, const struct sock *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_smbus_read)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int);\n\ntypedef void (*btf_trace_smbus_reply)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *, int);\n\ntypedef void (*btf_trace_smbus_result)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, int);\n\ntypedef void (*btf_trace_smbus_write)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_recv_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_sock_send_length)(void *, struct sock *, int, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_svc_alloc_arg_err)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_svc_authenticate)(void *, const struct svc_rqst *, enum svc_auth_status);\n\ntypedef void (*btf_trace_svc_defer)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_defer_drop)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_queue)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_recv)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_drop)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_noregister)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_pool_thread_noidle)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_running)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_pool_thread_wake)(void *, const struct svc_pool *, pid_t);\n\ntypedef void (*btf_trace_svc_process)(void *, const struct svc_rqst *, const char *);\n\ntypedef void (*btf_trace_svc_register)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_replace_page_err)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_send)(void *, const struct svc_rqst *, int);\n\ntypedef void (*btf_trace_svc_stats_latency)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_tls_not_started)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_start)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_timed_out)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_unavailable)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_tls_upcall)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_unregister)(void *, const char *, const u32, int);\n\ntypedef void (*btf_trace_svc_xdr_recvfrom)(void *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xdr_sendto)(void *, __be32, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xprt_accept)(void *, const struct svc_xprt *, const char *);\n\ntypedef void (*btf_trace_svc_xprt_close)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_create_err)(void *, const char *, const char *, struct sockaddr *, size_t, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_dequeue)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_xprt_detach)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_enqueue)(void *, const struct svc_xprt *, long unsigned int);\n\ntypedef void (*btf_trace_svc_xprt_free)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_no_write_space)(void *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svcsock_accept_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_data_ready)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_free)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_getpeername_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_marker)(void *, const struct svc_xprt *, __be32);\n\ntypedef void (*btf_trace_svcsock_new)(void *, const void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_tcp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_eagain)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_short)(void *, const struct svc_xprt *, u32, u32);\n\ntypedef void (*btf_trace_svcsock_tcp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_state)(void *, const struct svc_xprt *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_udp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_write_space)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_swiotlb_bounced)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_task_prctl_unknown)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef void (*btf_trace_tasklet_entry)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tasklet_exit)(void *, struct tasklet_struct *, void *);\n\ntypedef void (*btf_trace_tcp_ao_handshake_failure)(void *, const struct sock *, const struct sk_buff *, const __u8, const __u8, const __u8);\n\ntypedef void (*btf_trace_tcp_bad_csum)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_cong_state_set)(void *, struct sock *, const u8);\n\ntypedef void (*btf_trace_tcp_cwnd_reduction_tp)(void *, const struct sock *, int, int, int);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_hash_ao_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_bad_header)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_mismatch)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_required)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_hash_md5_unexpected)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcvbuf_grow)(void *, struct sock *, int);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *, const enum sk_rst_reason);\n\ntypedef void (*btf_trace_tcp_sendmsg_locked)(void *, const struct sock *, const struct msghdr *, const struct sk_buff *, int);\n\ntypedef void (*btf_trace_test_pages_isolated)(void *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lease *);\n\ntypedef void (*btf_trace_timer_base_idle)(void *, bool, unsigned int);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_interrupt_entry)(void *, struct pt_regs *);\n\ntypedef void (*btf_trace_timer_interrupt_exit)(void *, struct pt_regs *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_tlbia)(void *, long unsigned int);\n\ntypedef void (*btf_trace_tlbie)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_tls_alert_recv)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_alert_send)(void *, const struct sock *, unsigned char, unsigned char);\n\ntypedef void (*btf_trace_tls_contenttype)(void *, const struct sock *, unsigned char);\n\ntypedef void (*btf_trace_tmigr_connect_child_parent)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_connect_cpu_parent)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_active)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_available)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_cpu_new_timer_idle)(void *, struct tmigr_cpu *, u64);\n\ntypedef void (*btf_trace_tmigr_cpu_unavailable)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_group_set)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_active)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_group_set_cpu_inactive)(void *, struct tmigr_group *, union tmigr_state, u32);\n\ntypedef void (*btf_trace_tmigr_handle_remote)(void *, struct tmigr_group *);\n\ntypedef void (*btf_trace_tmigr_handle_remote_cpu)(void *, struct tmigr_cpu *);\n\ntypedef void (*btf_trace_tmigr_update_events)(void *, struct tmigr_group *, struct tmigr_group *, union tmigr_state, union tmigr_state, u64);\n\ntypedef void (*btf_trace_track_foreign_dirty)(void *, struct folio *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_usb_alloc_dev)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_usb_set_device_state)(void *, struct usb_device *);\n\ntypedef void (*btf_trace_user_enter)(void *, int);\n\ntypedef void (*btf_trace_user_exit)(void *, int);\n\ntypedef void (*btf_trace_vas_paste_crb)(void *, struct task_struct *, struct pnv_vas_window *);\n\ntypedef void (*btf_trace_vas_rx_win_open)(void *, struct task_struct *, int, int, struct vas_rx_win_attr *);\n\ntypedef void (*btf_trace_vas_tx_win_open)(void *, struct task_struct *, int, int, struct vas_tx_win_attr *);\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_dirty_folio)(void *, struct folio *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, long unsigned int, int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_xchk_block_error)(void *, struct xfs_scrub *, xfs_daddr_t, void *);\n\ntypedef void (*btf_trace_xchk_block_preen)(void *, struct xfs_scrub *, xfs_daddr_t, void *);\n\ntypedef void (*btf_trace_xchk_btree_error)(void *, struct xfs_scrub *, struct xfs_btree_cur *, int, void *);\n\ntypedef void (*btf_trace_xchk_btree_key)(void *, struct xfs_scrub *, struct xfs_btree_cur *, int);\n\ntypedef void (*btf_trace_xchk_btree_op_error)(void *, struct xfs_scrub *, struct xfs_btree_cur *, int, int, void *);\n\ntypedef void (*btf_trace_xchk_btree_rec)(void *, struct xfs_scrub *, struct xfs_btree_cur *, int);\n\ntypedef void (*btf_trace_xchk_deadlock_retry)(void *, struct xfs_inode *, struct xfs_scrub_metadata *, int);\n\ntypedef void (*btf_trace_xchk_dir_defer)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_dir_slowpath)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_dir_ultraslowpath)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_dirpath_badgen)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirpath_changed)(void *, struct xfs_scrub *, unsigned int, unsigned int, const struct xfs_inode *, const struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xchk_dirpath_crosses_tree)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirpath_disappeared)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirpath_evaluate_path)(void *, struct xfs_scrub *, long long unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xchk_dirpath_found_next_step)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirpath_nondir_parent)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirpath_set_outcome)(void *, struct xfs_scrub *, long long unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xchk_dirpath_unlinked_parent)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirpath_walk_upwards)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirtree_create_path)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_dirtree_done)(void *, struct xfs_inode *, struct xfs_scrub_metadata *, int);\n\ntypedef void (*btf_trace_xchk_dirtree_evaluate)(void *, const struct xchk_dirtree *, const struct xchk_dirtree_outcomes *);\n\ntypedef void (*btf_trace_xchk_dirtree_live_update)(void *, struct xfs_scrub *, const struct xfs_inode *, int, const struct xfs_inode *, int, const struct xfs_name *);\n\ntypedef void (*btf_trace_xchk_dirtree_start)(void *, struct xfs_inode *, struct xfs_scrub_metadata *, int);\n\ntypedef void (*btf_trace_xchk_done)(void *, struct xfs_inode *, struct xfs_scrub_metadata *, int);\n\ntypedef void (*btf_trace_xchk_fblock_error)(void *, struct xfs_scrub *, int, xfs_fileoff_t, void *);\n\ntypedef void (*btf_trace_xchk_fblock_preen)(void *, struct xfs_scrub *, int, xfs_fileoff_t, void *);\n\ntypedef void (*btf_trace_xchk_fblock_warning)(void *, struct xfs_scrub *, int, xfs_fileoff_t, void *);\n\ntypedef void (*btf_trace_xchk_file_op_error)(void *, struct xfs_scrub *, int, xfs_fileoff_t, int, void *);\n\ntypedef void (*btf_trace_xchk_fs_error)(void *, struct xfs_scrub *, xfs_daddr_t, void *);\n\ntypedef void (*btf_trace_xchk_fscounters_calc)(void *, struct xfs_mount *, uint64_t, uint64_t, uint64_t, uint64_t);\n\ntypedef void (*btf_trace_xchk_fscounters_within_range)(void *, struct xfs_mount *, uint64_t, int64_t, int64_t);\n\ntypedef void (*btf_trace_xchk_fsfreeze)(void *, struct xfs_scrub *, int);\n\ntypedef void (*btf_trace_xchk_fsgates_disable)(void *, struct xfs_scrub *, unsigned int);\n\ntypedef void (*btf_trace_xchk_fsgates_enable)(void *, struct xfs_scrub *, unsigned int);\n\ntypedef void (*btf_trace_xchk_fsthaw)(void *, struct xfs_scrub *, int);\n\ntypedef void (*btf_trace_xchk_iallocbt_check_cluster)(void *, const struct xfs_perag *, xfs_agino_t, xfs_daddr_t, short unsigned int, unsigned int, unsigned int, uint16_t, uint16_t, unsigned int);\n\ntypedef void (*btf_trace_xchk_ifork_btree_error)(void *, struct xfs_scrub *, struct xfs_btree_cur *, int, void *);\n\ntypedef void (*btf_trace_xchk_ifork_btree_op_error)(void *, struct xfs_scrub *, struct xfs_btree_cur *, int, int, void *);\n\ntypedef void (*btf_trace_xchk_incomplete)(void *, struct xfs_scrub *, void *);\n\ntypedef void (*btf_trace_xchk_ino_error)(void *, struct xfs_scrub *, xfs_ino_t, void *);\n\ntypedef void (*btf_trace_xchk_ino_preen)(void *, struct xfs_scrub *, xfs_ino_t, void *);\n\ntypedef void (*btf_trace_xchk_ino_warning)(void *, struct xfs_scrub *, xfs_ino_t, void *);\n\ntypedef void (*btf_trace_xchk_inode_is_allocated)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xchk_iscan_advance_ag)(void *, struct xchk_iscan *);\n\ntypedef void (*btf_trace_xchk_iscan_agi_retry_wait)(void *, struct xchk_iscan *);\n\ntypedef void (*btf_trace_xchk_iscan_iget)(void *, struct xchk_iscan *, int);\n\ntypedef void (*btf_trace_xchk_iscan_iget_batch)(void *, struct xfs_mount *, struct xchk_iscan *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xchk_iscan_iget_retry_wait)(void *, struct xchk_iscan *);\n\ntypedef void (*btf_trace_xchk_iscan_move_cursor)(void *, struct xchk_iscan *);\n\ntypedef void (*btf_trace_xchk_iscan_skip)(void *, struct xchk_iscan *);\n\ntypedef void (*btf_trace_xchk_iscan_start)(void *, struct xchk_iscan *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_iscan_visit)(void *, struct xchk_iscan *);\n\ntypedef void (*btf_trace_xchk_iscan_want_live_update)(void *, struct xchk_iscan *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_metapath_lookup)(void *, struct xfs_scrub *, const char *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_nlinks_check_zero)(void *, struct xfs_mount *, xfs_ino_t, const struct xchk_nlink *);\n\ntypedef void (*btf_trace_xchk_nlinks_collect_dirent)(void *, struct xfs_mount *, struct xfs_inode *, xfs_ino_t, const struct xfs_name *);\n\ntypedef void (*btf_trace_xchk_nlinks_collect_metafile)(void *, struct xfs_mount *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_nlinks_collect_pptr)(void *, struct xfs_mount *, struct xfs_inode *, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xchk_nlinks_compare_inode)(void *, struct xfs_mount *, struct xfs_inode *, const struct xchk_nlink *);\n\ntypedef void (*btf_trace_xchk_nlinks_live_update)(void *, struct xfs_mount *, const struct xfs_inode *, int, xfs_ino_t, int, const char *, unsigned int);\n\ntypedef void (*btf_trace_xchk_nlinks_update_incore)(void *, struct xfs_mount *, xfs_ino_t, const struct xchk_nlink *, int, int, int);\n\ntypedef void (*btf_trace_xchk_op_error)(void *, struct xfs_scrub *, xfs_agnumber_t, xfs_agblock_t, int, void *);\n\ntypedef void (*btf_trace_xchk_parent_defer)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_parent_slowpath)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_parent_ultraslowpath)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xchk_refcount_incorrect)(void *, const struct xfs_perag *, const struct xfs_refcount_irec *, xfs_nlink_t);\n\ntypedef void (*btf_trace_xchk_scrubv_barrier_fail)(void *, struct xfs_mount *, struct xfs_scrub_vec_head *, unsigned int, struct xfs_scrub_vec *);\n\ntypedef void (*btf_trace_xchk_scrubv_item)(void *, struct xfs_mount *, struct xfs_scrub_vec_head *, unsigned int, struct xfs_scrub_vec *);\n\ntypedef void (*btf_trace_xchk_scrubv_outcome)(void *, struct xfs_mount *, struct xfs_scrub_vec_head *, unsigned int, struct xfs_scrub_vec *);\n\ntypedef void (*btf_trace_xchk_scrubv_start)(void *, struct xfs_inode *, struct xfs_scrub_vec_head *);\n\ntypedef void (*btf_trace_xchk_start)(void *, struct xfs_inode *, struct xfs_scrub_metadata *, int);\n\ntypedef void (*btf_trace_xchk_xref_error)(void *, struct xfs_scrub *, int, void *);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int, struct xdp_cpumap_stats *);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, enum bpf_map_type, u32, u32);\n\ntypedef void (*btf_trace_xfarray_create)(void *, struct xfarray *, long long unsigned int);\n\ntypedef void (*btf_trace_xfarray_foliosort)(void *, struct xfarray_sortinfo *, uint64_t, uint64_t);\n\ntypedef void (*btf_trace_xfarray_isort)(void *, struct xfarray_sortinfo *, uint64_t, uint64_t);\n\ntypedef void (*btf_trace_xfarray_qsort)(void *, struct xfarray_sortinfo *, uint64_t, uint64_t);\n\ntypedef void (*btf_trace_xfarray_sort)(void *, struct xfarray_sortinfo *, size_t);\n\ntypedef void (*btf_trace_xfarray_sort_scan)(void *, struct xfarray_sortinfo *, long long unsigned int);\n\ntypedef void (*btf_trace_xfarray_sort_stats)(void *, struct xfarray_sortinfo *, int);\n\ntypedef void (*btf_trace_xfbtree_alloc_block)(void *, struct xfbtree *, struct xfs_btree_cur *, xfs_fileoff_t);\n\ntypedef void (*btf_trace_xfbtree_create_root_buf)(void *, struct xfbtree *, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfbtree_free_block)(void *, struct xfbtree *, struct xfs_btree_cur *, xfs_fileoff_t);\n\ntypedef void (*btf_trace_xfbtree_init)(void *, struct xfs_mount *, struct xfbtree *, const struct xfs_btree_ops *);\n\ntypedef void (*btf_trace_xfbtree_trans_cancel_buf)(void *, struct xfbtree *, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfbtree_trans_commit_buf)(void *, struct xfbtree *, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfile_create)(void *, struct xfile *);\n\ntypedef void (*btf_trace_xfile_destroy)(void *, struct xfile *);\n\ntypedef void (*btf_trace_xfile_discard)(void *, struct xfile *, loff_t, long long unsigned int);\n\ntypedef void (*btf_trace_xfile_get_folio)(void *, struct xfile *, loff_t, long long unsigned int);\n\ntypedef void (*btf_trace_xfile_load)(void *, struct xfile *, loff_t, long long unsigned int);\n\ntypedef void (*btf_trace_xfile_put_folio)(void *, struct xfile *, loff_t, long long unsigned int);\n\ntypedef void (*btf_trace_xfile_seek_data)(void *, struct xfile *, loff_t, long long unsigned int);\n\ntypedef void (*btf_trace_xfile_store)(void *, struct xfile *, loff_t, long long unsigned int);\n\ntypedef void (*btf_trace_xfs_ag_resv_alloc_extent)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_critical)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_free)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_free_extent)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_init)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_ag_resv_init_error)(void *, const struct xfs_perag *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ag_resv_needed)(void *, struct xfs_perag *, enum xfs_ag_resv_type, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_agf)(void *, struct xfs_mount *, struct xfs_agf *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_agfl_free_deferred)(void *, struct xfs_mount *, struct xfs_extent_free_item *);\n\ntypedef void (*btf_trace_xfs_agfl_reset)(void *, struct xfs_mount *, struct xfs_agf *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ail_delete)(void *, struct xfs_log_item *, xfs_lsn_t, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_ail_flushing)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_ail_insert)(void *, struct xfs_log_item *, xfs_lsn_t, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_ail_locked)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_ail_move)(void *, struct xfs_log_item *, xfs_lsn_t, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_ail_pinned)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_ail_push)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_alloc_cur)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_check)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, xfs_extlen_t, bool);\n\ntypedef void (*btf_trace_xfs_alloc_cur_left)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_lookup)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_lookup_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_cur_right)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_exact_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_exact_error)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_exact_notfound)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_alloc_near_busy)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_near_first)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_near_noentry)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_read_agf)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_alloc_size_busy)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_error)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_neither)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_noentry)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_size_nominleft)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_done)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_error)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_freelist)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_small_notenough)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_allfailed)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_badargs)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_exact_bno)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_finish)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_first_ag)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_loopfailed)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_near_bno)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_noagbp)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_nofix)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_skip_deadlock)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_start_ag)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_alloc_vextent_this_ag)(void *, struct xfs_alloc_arg *);\n\ntypedef void (*btf_trace_xfs_attr_defer_add)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add_new)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add_old)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_add_work)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_addname_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_clearflag)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_compact)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_flipflags)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_get)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_list)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_rebalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_remove)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_setflag)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_split_after)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_split_before)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_to_node)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_to_sf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_toosmall)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_leaf_unbalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_list_add)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_full)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_leaf)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_leaf_end)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_node_descend)(void *, struct xfs_attr_list_context *, struct xfs_da_node_entry *);\n\ntypedef void (*btf_trace_xfs_attr_list_notfound)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_sf)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_sf_all)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_list_wrong_blk)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_node_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_node_addname_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_node_get)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_node_list)(void *, struct xfs_attr_list_context *);\n\ntypedef void (*btf_trace_xfs_attr_node_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_rmtval_alloc)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_rmtval_get)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_rmtval_remove_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_set_iter_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_sf_add)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_addname_return)(void *, int, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_attr_sf_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_remove)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_attr_sf_to_leaf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_blockgc_flush_all)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_blockgc_free_space)(void *, struct xfs_mount *, struct xfs_icwalk *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_blockgc_start)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_blockgc_stop)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_blockgc_worker)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_bmap_defer)(void *, struct xfs_bmap_intent *);\n\ntypedef void (*btf_trace_xfs_bmap_deferred)(void *, struct xfs_bmap_intent *);\n\ntypedef void (*btf_trace_xfs_bmap_post_update)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_bmap_pre_update)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_btree_alloc_block)(void *, struct xfs_btree_cur *, union xfs_btree_ptr *, int, int);\n\ntypedef void (*btf_trace_xfs_btree_bload_block)(void *, struct xfs_btree_cur *, unsigned int, uint64_t, uint64_t, union xfs_btree_ptr *, unsigned int);\n\ntypedef void (*btf_trace_xfs_btree_bload_level_geometry)(void *, struct xfs_btree_cur *, unsigned int, uint64_t, unsigned int, unsigned int, uint64_t, uint64_t);\n\ntypedef void (*btf_trace_xfs_btree_commit_afakeroot)(void *, struct xfs_btree_cur *);\n\ntypedef void (*btf_trace_xfs_btree_commit_ifakeroot)(void *, struct xfs_btree_cur *);\n\ntypedef void (*btf_trace_xfs_btree_corrupt)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_btree_free_block)(void *, struct xfs_btree_cur *, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfs_btree_overlapped_query_range)(void *, struct xfs_btree_cur *, int, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfs_btree_updkeys)(void *, struct xfs_btree_cur *, int, struct xfs_buf *);\n\ntypedef void (*btf_trace_xfs_buf_backing_fallback)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_backing_folio)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_backing_kmem)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_backing_vmalloc)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_delwri_queue)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_delwri_queued)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_delwri_split)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_drain_buftarg)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_error_relse)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_find)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_free)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_get)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_get_uncached)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_hold)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_init)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_iodone)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_iodone_async)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_ioerror)(void *, struct xfs_buf *, int, xfs_failaddr_t);\n\ntypedef void (*btf_trace_xfs_buf_iowait)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_iowait_done)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_item_committed)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_format)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_format_stale)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_ordered)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_pin)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_push)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_release)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_relse)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_item_size)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_size_ordered)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_size_stale)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_unpin)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_item_unpin_stale)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_buf_lock)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_lock_done)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_read)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_readahead)(void *, struct xfs_buf *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_rele)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_submit)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_trylock)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_trylock_fail)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_buf_unlock)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_bunmap)(void *, struct xfs_inode *, xfs_fileoff_t, xfs_filblks_t, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_calc_atomic_write_unit_max)(void *, struct xfs_mount *, enum xfs_group_type, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xfs_calc_max_atomic_write_fsblocks)(void *, struct xfs_mount *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xfs_calc_max_atomic_write_log_geometry)(void *, struct xfs_mount *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xfs_check_new_dalign)(void *, struct xfs_mount *, int, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_cil_whiteout_mark)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_cil_whiteout_skip)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_cil_whiteout_unpin)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_collapse_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_create)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_da_fixhashpath)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_grow_inode)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_join)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_link_after)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_link_before)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_add)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_rebalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_remove)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_toosmall)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_node_unbalance)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_path_shift)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_root_join)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_root_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_shrink_inode)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_split)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_swap_lastblock)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_unlink_back)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_da_unlink_forward)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_defer_add_item)(void *, struct xfs_mount *, struct xfs_defer_pending *, void *);\n\ntypedef void (*btf_trace_xfs_defer_cancel)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_cancel_item)(void *, struct xfs_mount *, struct xfs_defer_pending *, void *);\n\ntypedef void (*btf_trace_xfs_defer_cancel_list)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_create_intent)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_finish)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_finish_done)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_finish_error)(void *, struct xfs_trans *, int);\n\ntypedef void (*btf_trace_xfs_defer_finish_item)(void *, struct xfs_mount *, struct xfs_defer_pending *, void *);\n\ntypedef void (*btf_trace_xfs_defer_isolate_paused)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_item_pause)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_item_unpause)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_pending_abort)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_pending_finish)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_relog_intent)(void *, struct xfs_mount *, struct xfs_defer_pending *);\n\ntypedef void (*btf_trace_xfs_defer_trans_abort)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_trans_roll)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_defer_trans_roll_error)(void *, struct xfs_trans *, int);\n\ntypedef void (*btf_trace_xfs_delalloc_enospc)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_destroy_inode)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_dir2_block_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_to_leaf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_block_to_sf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_grow_inode)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_to_block)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leaf_to_node)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_leafn_add)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir2_leafn_moveents)(void *, struct xfs_da_args *, int, int, int);\n\ntypedef void (*btf_trace_xfs_dir2_leafn_remove)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir2_node_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_node_to_leaf)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_addname)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_create)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_lookup)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_removename)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_replace)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_to_block)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_toino4)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_sf_toino8)(void *, struct xfs_da_args *);\n\ntypedef void (*btf_trace_xfs_dir2_shrink_inode)(void *, struct xfs_da_args *, int);\n\ntypedef void (*btf_trace_xfs_dir_fsync)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_discard_busy)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_discard_exclude)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_discard_extent)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_discard_rtextent)(void *, struct xfs_mount *, xfs_rtblock_t, xfs_rtblock_t);\n\ntypedef void (*btf_trace_xfs_discard_rttoosmall)(void *, struct xfs_mount *, xfs_rtblock_t, xfs_rtblock_t);\n\ntypedef void (*btf_trace_xfs_discard_toosmall)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_dqadjust)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqalloc)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqattach_get)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqflush)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqflush_done)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqflush_force)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_dup)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_freeing)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_hit)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqget_miss)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqread)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqread_fail)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqreclaim_busy)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqreclaim_done)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqreclaim_want)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqrele)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqrele_free)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dqtobp_read)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_dquot_dqalloc)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_dquot_dqdetach)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_end_io_direct_write)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_exchmaps_defer)(void *, struct xfs_mount *, const struct xfs_exchmaps_intent *);\n\ntypedef void (*btf_trace_xfs_exchmaps_delta_nextents)(void *, const struct xfs_exchmaps_req *, int64_t, int64_t);\n\ntypedef void (*btf_trace_xfs_exchmaps_delta_nextents_step)(void *, struct xfs_mount *, const struct xfs_bmbt_irec *, const struct xfs_bmbt_irec *, const struct xfs_bmbt_irec *, const struct xfs_bmbt_irec *, int, unsigned int);\n\ntypedef void (*btf_trace_xfs_exchmaps_final_estimate)(void *, const struct xfs_exchmaps_req *);\n\ntypedef void (*btf_trace_xfs_exchmaps_initial_estimate)(void *, const struct xfs_exchmaps_req *);\n\ntypedef void (*btf_trace_xfs_exchmaps_mapping1)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_exchmaps_mapping1_skip)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_exchmaps_mapping2)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_exchmaps_overhead)(void *, struct xfs_mount *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_xfs_exchmaps_recover)(void *, struct xfs_mount *, const struct xfs_exchmaps_intent *);\n\ntypedef void (*btf_trace_xfs_exchmaps_update_inode_size)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_exchrange_after)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_exchrange_before)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_exchrange_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_exchrange_flush)(void *, const struct xfs_exchrange *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_exchrange_freshness)(void *, const struct xfs_exchrange *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_exchrange_mappings)(void *, const struct xfs_exchrange *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_exchrange_prep)(void *, const struct xfs_exchrange *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_extent_busy)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_clear)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_force)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_reuse)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_busy_trim)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_extent_free_defer)(void *, struct xfs_mount *, struct xfs_extent_free_item *);\n\ntypedef void (*btf_trace_xfs_extent_free_deferred)(void *, struct xfs_mount *, struct xfs_extent_free_item *);\n\ntypedef void (*btf_trace_xfs_file_buffered_read)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_buffered_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_dax_read)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_dax_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_direct_read)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_direct_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_file_fsync)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_file_ioctl)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_file_splice_read)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_filestream_free)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_filestream_lookup)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_filestream_pick)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_filestream_scan)(void *, const struct xfs_perag *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_force_shutdown)(void *, struct xfs_mount *, int, int, const char *, int);\n\ntypedef void (*btf_trace_xfs_free_extent)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_extlen_t, enum xfs_ag_resv_type, int, int);\n\ntypedef void (*btf_trace_xfs_free_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_freecounter_enospc)(void *, struct xfs_mount *, enum xfs_free_counter, uint64_t, long unsigned int);\n\ntypedef void (*btf_trace_xfs_freecounter_reserved)(void *, struct xfs_mount *, enum xfs_free_counter, uint64_t, long unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_mark_corrupt)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_mark_healthy)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_mark_sick)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fs_sync_fs)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_fs_unfixed_corruption)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_fsmap_high_group_key)(void *, struct xfs_mount *, u32, xfs_agnumber_t, const struct xfs_rmap_irec *);\n\ntypedef void (*btf_trace_xfs_fsmap_high_linear_key)(void *, struct xfs_mount *, u32, uint64_t);\n\ntypedef void (*btf_trace_xfs_fsmap_low_group_key)(void *, struct xfs_mount *, u32, xfs_agnumber_t, const struct xfs_rmap_irec *);\n\ntypedef void (*btf_trace_xfs_fsmap_low_linear_key)(void *, struct xfs_mount *, u32, uint64_t);\n\ntypedef void (*btf_trace_xfs_fsmap_mapping)(void *, struct xfs_mount *, u32, xfs_agnumber_t, const struct xfs_fsmap_irec *);\n\ntypedef void (*btf_trace_xfs_get_acl)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_getattr)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_getfsmap_high_key)(void *, struct xfs_mount *, struct xfs_fsmap *);\n\ntypedef void (*btf_trace_xfs_getfsmap_low_key)(void *, struct xfs_mount *, struct xfs_fsmap *);\n\ntypedef void (*btf_trace_xfs_getfsmap_mapping)(void *, struct xfs_mount *, struct xfs_fsmap *);\n\ntypedef void (*btf_trace_xfs_getparents_begin)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attrlist_cursor_kern *);\n\ntypedef void (*btf_trace_xfs_getparents_end)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attrlist_cursor_kern *);\n\ntypedef void (*btf_trace_xfs_getparents_expand_lastrec)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attr_list_context *, const struct xfs_getparents_rec *);\n\ntypedef void (*btf_trace_xfs_getparents_put_listent)(void *, struct xfs_inode *, const struct xfs_getparents *, const struct xfs_attr_list_context *, const struct xfs_getparents_rec *);\n\ntypedef void (*btf_trace_xfs_group_get)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_grab)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_grab_next_tag)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_hold)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_intent_hold)(void *, const struct xfs_group *, void *);\n\ntypedef void (*btf_trace_xfs_group_intent_rele)(void *, const struct xfs_group *, void *);\n\ntypedef void (*btf_trace_xfs_group_mark_corrupt)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_group_mark_healthy)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_group_mark_sick)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_group_put)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_rele)(void *, struct xfs_group *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_group_unfixed_corruption)(void *, const struct xfs_group *, unsigned int);\n\ntypedef void (*btf_trace_xfs_group_wait_intents)(void *, const struct xfs_group *, void *);\n\ntypedef void (*btf_trace_xfs_healthmon_copybuf)(void *, const struct xfs_healthmon *, const struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_healthmon_create)(void *, dev_t, u64, u8);\n\ntypedef void (*btf_trace_xfs_healthmon_detach)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_drop)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_format)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_format_overflow)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_insert)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_lost_event)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_merge)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_pop)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_push)(void *, const struct xfs_healthmon *, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_read_finish)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_read_start)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_release)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_file_ioerror)(void *, const struct xfs_healthmon *, const struct fserror_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_fs)(void *, const struct xfs_healthmon *, unsigned int, unsigned int, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_group)(void *, const struct xfs_healthmon *, unsigned int, unsigned int, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_inode)(void *, const struct xfs_healthmon *, unsigned int, unsigned int, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_media)(void *, const struct xfs_healthmon *, enum xfs_device, const struct xfs_healthmon_event *);\n\ntypedef void (*btf_trace_xfs_healthmon_report_shutdown)(void *, const struct xfs_healthmon *, uint32_t);\n\ntypedef void (*btf_trace_xfs_healthmon_report_unmount)(void *, const struct xfs_healthmon *);\n\ntypedef void (*btf_trace_xfs_ialloc_read_agi)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_iext_insert)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_iext_remove)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_iget_hit)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_miss)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_recycle)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_recycle_fail)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iget_skip)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_ilock)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ilock_demote)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ilock_nowait)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inactive_symlink)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_clear_cowblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_clear_eofblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_free_cowblocks_invalid)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_free_eofblocks_invalid)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_inactivating)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_mark_corrupt)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_mark_healthy)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_mark_sick)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_pin)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_push_pinned)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_push_stale)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_reclaiming)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_reload_unlinked_bucket)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_cowblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_eofblocks_tag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_need_inactive)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_set_reclaimable)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_inode_timestamp_range)(void *, struct xfs_mount *, long long int, long long int);\n\ntypedef void (*btf_trace_xfs_inode_unfixed_corruption)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_unpin)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inode_unpin_nowait)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_inodegc_flush)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_push)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_queue)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_shrinker_scan)(void *, struct xfs_mount *, struct shrink_control *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_start)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_stop)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_throttle)(void *, struct xfs_mount *, void *);\n\ntypedef void (*btf_trace_xfs_inodegc_worker)(void *, struct xfs_mount *, unsigned int);\n\ntypedef void (*btf_trace_xfs_insert_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_ioc_free_eofblocks)(void *, struct xfs_mount *, struct xfs_icwalk *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_ioctl_setattr)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iomap_alloc)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_iomap_atomic_write_cow)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_iomap_found)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_iomap_invalid)(void *, struct xfs_inode *, const struct iomap *);\n\ntypedef void (*btf_trace_xfs_iomap_prealloc_size)(void *, struct xfs_inode *, xfs_fsblock_t, int, unsigned int);\n\ntypedef void (*btf_trace_xfs_irec_merge_post)(void *, const struct xfs_perag *, const struct xfs_inobt_rec_incore *);\n\ntypedef void (*btf_trace_xfs_irec_merge_pre)(void *, const struct xfs_perag *, const struct xfs_inobt_rec_incore *, const struct xfs_inobt_rec_incore *);\n\ntypedef void (*btf_trace_xfs_irele)(void *, struct xfs_inode *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_itruncate_extents_end)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_itruncate_extents_start)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_iunlink)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iunlink_reload_next)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iunlink_remove)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_iunlink_update_bucket)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xfs_iunlink_update_dinode)(void *, const struct xfs_iunlink_item *, xfs_agino_t);\n\ntypedef void (*btf_trace_xfs_iunlock)(void *, struct xfs_inode *, unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_iwalk_ag_rec)(void *, const struct xfs_perag *, struct xfs_inobt_rec_incore *);\n\ntypedef void (*btf_trace_xfs_link)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_log_assign_tail_lsn)(void *, struct xlog *, xfs_lsn_t);\n\ntypedef void (*btf_trace_xfs_log_cil_wait)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_force)(void *, struct xfs_mount *, xfs_lsn_t, long unsigned int);\n\ntypedef void (*btf_trace_xfs_log_get_max_trans_res)(void *, struct xfs_mount *, const struct xfs_trans_res *);\n\ntypedef void (*btf_trace_xfs_log_grant_sleep)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_grant_wake)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_grant_wake_up)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_recover)(void *, struct xlog *, xfs_daddr_t, xfs_daddr_t);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_cancel)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_cancel_add)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_cancel_ref_inc)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_dquot_buf)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_inode_buf)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_not_cancel)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_recover)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_reg_buf)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_buf_skip)(void *, struct xlog *, struct xfs_buf_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_icreate_cancel)(void *, struct xlog *, struct xfs_icreate_log *);\n\ntypedef void (*btf_trace_xfs_log_recover_icreate_recover)(void *, struct xlog *, struct xfs_icreate_log *);\n\ntypedef void (*btf_trace_xfs_log_recover_inode_cancel)(void *, struct xlog *, struct xfs_inode_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_inode_recover)(void *, struct xlog *, struct xfs_inode_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_inode_skip)(void *, struct xlog *, struct xfs_inode_log_format *);\n\ntypedef void (*btf_trace_xfs_log_recover_item_add)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_add_cont)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_recover)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_reorder_head)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_item_reorder_tail)(void *, struct xlog *, struct xlog_recover *, struct xlog_recover_item *, int);\n\ntypedef void (*btf_trace_xfs_log_recover_record)(void *, struct xlog *, struct xlog_rec_header *, int);\n\ntypedef void (*btf_trace_xfs_log_regrant)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_regrant_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_reserve)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_reserve_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_regrant)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_regrant_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_regrant_sub)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_ungrant)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_ungrant_exit)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_ticket_ungrant_sub)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_log_umount_write)(void *, struct xlog *, struct xlog_ticket *);\n\ntypedef void (*btf_trace_xfs_lookup)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_map_blocks_alloc)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_map_blocks_found)(void *, struct xfs_inode *, xfs_off_t, ssize_t, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_metadir_cancel)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_commit)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_create)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_link)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_lookup)(void *, struct xfs_inode *, struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xfs_metadir_start_create)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_start_link)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metadir_teardown)(void *, const struct xfs_metadir_update *, int);\n\ntypedef void (*btf_trace_xfs_metadir_try_create)(void *, const struct xfs_metadir_update *);\n\ntypedef void (*btf_trace_xfs_metafile_resv_alloc_space)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_critical)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_free)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_free_space)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_init)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_metafile_resv_init_error)(void *, struct xfs_mount *, xfs_filblks_t);\n\ntypedef void (*btf_trace_xfs_perag_clear_inode_tag)(void *, const struct xfs_perag *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_perag_set_inode_tag)(void *, const struct xfs_perag *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_pwork_init)(void *, struct xfs_mount *, unsigned int, pid_t);\n\ntypedef void (*btf_trace_xfs_quota_expiry_range)(void *, struct xfs_mount *, long long int, long long int);\n\ntypedef void (*btf_trace_xfs_read_agf)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_read_agi)(void *, const struct xfs_perag *);\n\ntypedef void (*btf_trace_xfs_read_extent)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_read_fault)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_readdir)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_readlink)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_reclaim_inodes_count)(void *, const struct xfs_perag *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_adjust_cow_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_adjust_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_cow_decrease)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_cow_increase)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_decrease)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_defer)(void *, struct xfs_mount *, struct xfs_refcount_intent *);\n\ntypedef void (*btf_trace_xfs_refcount_deferred)(void *, struct xfs_mount *, struct xfs_refcount_intent *);\n\ntypedef void (*btf_trace_xfs_refcount_delete)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_delete_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_left_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *, xfs_agblock_t);\n\ntypedef void (*btf_trace_xfs_refcount_find_left_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_right_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *, xfs_agblock_t);\n\ntypedef void (*btf_trace_xfs_refcount_find_right_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_shared)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_find_shared_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_find_shared_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_finish_one_leftover)(void *, struct xfs_mount *, struct xfs_refcount_intent *);\n\ntypedef void (*btf_trace_xfs_refcount_get)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_increase)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xfs_refcount_insert)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_insert_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_lookup)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_lookup_t);\n\ntypedef void (*btf_trace_xfs_refcount_merge_center_extents)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_merge_center_extents_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_merge_left_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_merge_left_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_merge_right_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_merge_right_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_modify_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_modify_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_split_extent)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *, xfs_agblock_t);\n\ntypedef void (*btf_trace_xfs_refcount_split_extent_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_refcount_update)(void *, struct xfs_btree_cur *, struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xfs_refcount_update_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_bounce_dio_write)(void *, struct kiocb *, struct iov_iter *);\n\ntypedef void (*btf_trace_xfs_reflink_cancel_cow)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cancel_cow_range)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_reflink_cancel_cow_range_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_convert_cow)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_found)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_remap_from)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_remap_skip)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_cow_remap_to)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_end_cow)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_reflink_end_cow_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_remap_blocks)(void *, struct xfs_inode *, xfs_fileoff_t, xfs_filblks_t, struct xfs_inode *, xfs_fileoff_t);\n\ntypedef void (*btf_trace_xfs_reflink_remap_blocks_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_remap_extent_dest)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_remap_extent_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_remap_extent_src)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_remap_range)(void *, struct xfs_inode *, xfs_off_t, xfs_off_t, struct xfs_inode *, xfs_off_t);\n\ntypedef void (*btf_trace_xfs_reflink_remap_range_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_set_inode_flag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_reflink_set_inode_flag_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_trim_around_shared)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_reflink_unset_inode_flag)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_reflink_unshare)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_reflink_unshare_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_reflink_update_inode_size)(void *, struct xfs_inode *, xfs_fsize_t);\n\ntypedef void (*btf_trace_xfs_reflink_update_inode_size_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_remove)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_rename)(void *, struct xfs_inode *, struct xfs_inode *, struct xfs_name *, struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_reset_dqcounts)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_convert)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_convert_done)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_convert_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_convert_state)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_defer)(void *, struct xfs_mount *, struct xfs_rmap_intent *);\n\ntypedef void (*btf_trace_xfs_rmap_deferred)(void *, struct xfs_mount *, struct xfs_rmap_intent *);\n\ntypedef void (*btf_trace_xfs_rmap_delete)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_delete_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_left_neighbor_candidate)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_left_neighbor_query)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_left_neighbor_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_find_right_neighbor_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_insert)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_insert_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_lookup_le_range)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_lookup_le_range_candidate)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_lookup_le_range_result)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_map)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_map_done)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_map_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_unmap)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_unmap_done)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, bool, const struct xfs_owner_info *);\n\ntypedef void (*btf_trace_xfs_rmap_unmap_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_update)(void *, struct xfs_btree_cur *, xfs_agblock_t, xfs_extlen_t, uint64_t, uint64_t, unsigned int);\n\ntypedef void (*btf_trace_xfs_rmap_update_error)(void *, struct xfs_btree_cur *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_setattr)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_setfilesize)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_swap_extent_after)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_swap_extent_before)(void *, struct xfs_inode *, int);\n\ntypedef void (*btf_trace_xfs_swap_extent_rmap_error)(void *, struct xfs_inode *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_swap_extent_rmap_remap)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_swap_extent_rmap_remap_piece)(void *, struct xfs_inode *, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xfs_symlink)(void *, struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xfs_trans_add_item)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_alloc)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_apply_dquot_deltas)(void *, struct xfs_dqtrx *);\n\ntypedef void (*btf_trace_xfs_trans_apply_dquot_deltas_after)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_trans_apply_dquot_deltas_before)(void *, struct xfs_dquot *);\n\ntypedef void (*btf_trace_xfs_trans_bdetach)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_bhold)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_bhold_release)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_binval)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_bjoin)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_brelse)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_cancel)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_commit)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_commit_items)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_dup)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_free)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_free_abort)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_free_items)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_get_buf)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_get_buf_recur)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_getsb)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_getsb_recur)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_log_buf)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_mod_dquot)(void *, struct xfs_trans *, struct xfs_dquot *, unsigned int, int64_t);\n\ntypedef void (*btf_trace_xfs_trans_mod_dquot_after)(void *, struct xfs_dqtrx *);\n\ntypedef void (*btf_trace_xfs_trans_mod_dquot_before)(void *, struct xfs_dqtrx *);\n\ntypedef void (*btf_trace_xfs_trans_read_buf)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_read_buf_recur)(void *, struct xfs_buf_log_item *);\n\ntypedef void (*btf_trace_xfs_trans_read_buf_shut)(void *, struct xfs_buf *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_trans_resv_calc)(void *, struct xfs_mount *, unsigned int, struct xfs_trans_res *);\n\ntypedef void (*btf_trace_xfs_trans_resv_calc_minlogsize)(void *, struct xfs_mount *, unsigned int, struct xfs_trans_res *);\n\ntypedef void (*btf_trace_xfs_trans_roll)(void *, struct xfs_trans *, long unsigned int);\n\ntypedef void (*btf_trace_xfs_unwritten_convert)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_update_time)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_verify_media)(void *, const struct xfs_mount *, const struct xfs_verify_media *, dev_t, xfs_daddr_t, uint64_t, const struct folio *);\n\ntypedef void (*btf_trace_xfs_verify_media_end)(void *, const struct xfs_mount *, const struct xfs_verify_media *, dev_t);\n\ntypedef void (*btf_trace_xfs_verify_media_error)(void *, const struct xfs_mount *, const struct xfs_verify_media *, dev_t, xfs_daddr_t, uint64_t, blk_status_t);\n\ntypedef void (*btf_trace_xfs_vm_bmap)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_wb_cow_iomap_invalid)(void *, struct xfs_inode *, const struct iomap *, unsigned int, int);\n\ntypedef void (*btf_trace_xfs_wb_data_iomap_invalid)(void *, struct xfs_inode *, const struct iomap *, unsigned int, int);\n\ntypedef void (*btf_trace_xfs_write_extent)(void *, struct xfs_inode *, struct xfs_iext_cursor *, int, long unsigned int);\n\ntypedef void (*btf_trace_xfs_write_fault)(void *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xfs_zero_eof)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xfs_zero_file_space)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xfs_zoned_map_blocks)(void *, struct xfs_inode *, xfs_off_t, ssize_t);\n\ntypedef void (*btf_trace_xlog_ail_insert_abort)(void *, struct xfs_log_item *);\n\ntypedef void (*btf_trace_xlog_iclog_activate)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_callback)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_callbacks_done)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_callbacks_start)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_clean)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_force)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_force_lsn)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_get_space)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_release)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_switch)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_sync)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_sync_done)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_syncing)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_wait_on)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_iclog_write)(void *, struct xlog_in_core *, long unsigned int);\n\ntypedef void (*btf_trace_xlog_intent_recovery_failed)(void *, struct xfs_mount *, const struct xfs_defer_op_type *, int);\n\ntypedef void (*btf_trace_xmbuf_create)(void *, struct xfs_buftarg *);\n\ntypedef void (*btf_trace_xmbuf_free)(void *, struct xfs_buftarg *);\n\ntypedef void (*btf_trace_xprt_connect)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_create)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_destroy)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_auto)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_done)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_force)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_get_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_lookup_rqst)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_ping)(void *, const struct rpc_xprt *, int);\n\ntypedef void (*btf_trace_xprt_put_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_reserve_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_retransmit)(void *, const struct rpc_rqst *);\n\ntypedef void (*btf_trace_xprt_timer)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_transmit)(void *, const struct rpc_rqst *, int);\n\ntypedef void (*btf_trace_xreap_agcow_limits)(void *, const struct xfs_trans *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xreap_agextent_binval)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xreap_agextent_limits)(void *, const struct xfs_trans *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xreap_agextent_select)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t, bool);\n\ntypedef void (*btf_trace_xreap_bmapi_binval)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xreap_bmapi_binval_scan)(void *, struct xfs_scrub *, const struct xfs_bmbt_irec *, xfs_extlen_t);\n\ntypedef void (*btf_trace_xreap_bmapi_limits)(void *, const struct xfs_trans *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xreap_bmapi_select)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t, bool);\n\ntypedef void (*btf_trace_xreap_dispose_free_extent)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xreap_dispose_unmap_extent)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xreap_ifork_extent)(void *, struct xfs_scrub *, struct xfs_inode *, int, const struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xreap_rgcow_limits)(void *, const struct xfs_trans *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xrep_abt_found)(void *, const struct xfs_perag *, const struct xfs_alloc_rec_incore *);\n\ntypedef void (*btf_trace_xrep_adoption_check_child)(void *, struct xfs_mount *, const struct dentry *);\n\ntypedef void (*btf_trace_xrep_adoption_invalidate_child)(void *, struct xfs_mount *, const struct dentry *);\n\ntypedef void (*btf_trace_xrep_adoption_reparent)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_adoption_trans_roll)(void *, struct xfs_inode *, struct xfs_inode *, bool);\n\ntypedef void (*btf_trace_xrep_agfl_insert)(void *, const struct xfs_group *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xrep_attempt)(void *, struct xfs_inode *, struct xfs_scrub_metadata *, int);\n\ntypedef void (*btf_trace_xrep_bmap_found)(void *, struct xfs_inode *, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xrep_calc_ag_resblks)(void *, const struct xfs_perag *, xfs_agino_t, xfs_agblock_t, xfs_agblock_t, xfs_agblock_t);\n\ntypedef void (*btf_trace_xrep_calc_ag_resblks_btsize)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_agblock_t, xfs_agblock_t, xfs_agblock_t);\n\ntypedef void (*btf_trace_xrep_cow_free_staging)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xrep_cow_mark_file_range)(void *, struct xfs_inode *, xfs_fsblock_t, xfs_fileoff_t, xfs_filblks_t);\n\ntypedef void (*btf_trace_xrep_cow_replace_mapping)(void *, struct xfs_inode *, const struct xfs_bmbt_irec *, xfs_fsblock_t, xfs_extlen_t);\n\ntypedef void (*btf_trace_xrep_dinode_count_rmaps)(void *, struct xfs_scrub *, xfs_rfsblock_t, xfs_rfsblock_t, xfs_rfsblock_t, xfs_extnum_t, xfs_extnum_t, xfs_aextnum_t);\n\ntypedef void (*btf_trace_xrep_dinode_ensure_forkoff)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_extsize_hints)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_findmode_dirent)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int);\n\ntypedef void (*btf_trace_xrep_dinode_findmode_dirent_inval)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xrep_dinode_fixed)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_flags)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_header)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_mode)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_size)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_zap_afork)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_zap_dfork)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_zap_dir)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_zap_forks)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dinode_zap_symlink)(void *, struct xfs_scrub *, struct xfs_dinode *);\n\ntypedef void (*btf_trace_xrep_dir_rebuild_tree)(void *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dir_recover_dirblock)(void *, struct xfs_inode *, xfs_dablk_t, uint32_t, uint32_t);\n\ntypedef void (*btf_trace_xrep_dir_replay_createname)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dir_replay_removename)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dir_reset_fork)(void *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dir_salvage_entry)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dir_salvaged_parent)(void *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dir_stash_createname)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dir_stash_removename)(void *, struct xfs_inode *, const struct xfs_name *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_dirpath_set_outcome)(void *, struct xfs_scrub *, long long unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xrep_dirtree_create_adoption)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xrep_dirtree_decided_fate)(void *, const struct xchk_dirtree *, const struct xchk_dirtree_outcomes *);\n\ntypedef void (*btf_trace_xrep_dirtree_delete_child)(void *, struct xfs_mount *, const struct dentry *);\n\ntypedef void (*btf_trace_xrep_dirtree_delete_path)(void *, struct xfs_scrub *, struct xfs_inode *, unsigned int, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xrep_done)(void *, struct xfs_inode *, struct xfs_scrub_metadata *, int);\n\ntypedef void (*btf_trace_xrep_findparent_dirent)(void *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_findparent_from_dcache)(void *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_findroot_block)(void *, const struct xfs_perag *, xfs_agblock_t, uint32_t, uint16_t);\n\ntypedef void (*btf_trace_xrep_ibt_found)(void *, const struct xfs_perag *, const struct xfs_inobt_rec_incore *);\n\ntypedef void (*btf_trace_xrep_ibt_walk_rmap)(void *, const struct xfs_perag *, const struct xfs_rmap_irec *);\n\ntypedef void (*btf_trace_xrep_inode_blockcounts)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_inode_blockdir_size)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_inode_dir_size)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_inode_fixed)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_inode_flags)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_inode_ids)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_inode_sfdir_size)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_iunlink_add_to_bucket)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_commit_bucket)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_relink_next)(void *, struct xfs_inode *, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_relink_prev)(void *, struct xfs_inode *, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_reload_next)(void *, struct xfs_inode *, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_reload_ondisk)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xrep_iunlink_resolve_nolist)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_resolve_ok)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_resolve_uncached)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_resolve_wronglist)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_iunlink_visit)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, struct xfs_inode *);\n\ntypedef void (*btf_trace_xrep_iunlink_walk_ondisk_bucket)(void *, const struct xfs_perag *, unsigned int, xfs_agino_t, xfs_agino_t);\n\ntypedef void (*btf_trace_xrep_metapath_link)(void *, struct xfs_scrub *, const char *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_metapath_lookup)(void *, struct xfs_scrub *, const char *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_metapath_try_unlink)(void *, struct xfs_scrub *, const char *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_metapath_unlink)(void *, struct xfs_scrub *, const char *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_newbt_alloc_ag_blocks)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_extlen_t, int64_t);\n\ntypedef void (*btf_trace_xrep_newbt_alloc_file_blocks)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_extlen_t, int64_t);\n\ntypedef void (*btf_trace_xrep_newbt_claim_block)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_extlen_t, int64_t);\n\ntypedef void (*btf_trace_xrep_newbt_free_blocks)(void *, const struct xfs_perag *, xfs_agblock_t, xfs_extlen_t, int64_t);\n\ntypedef void (*btf_trace_xrep_nlinks_set_record)(void *, struct xfs_mount *, xfs_ino_t, const struct xchk_nlink *);\n\ntypedef void (*btf_trace_xrep_nlinks_unfixable_inode)(void *, struct xfs_mount *, struct xfs_inode *, const struct xchk_nlink *);\n\ntypedef void (*btf_trace_xrep_nlinks_update_inode)(void *, struct xfs_mount *, struct xfs_inode *, const struct xchk_nlink *);\n\ntypedef void (*btf_trace_xrep_parent_insert_xattr)(void *, struct xfs_inode *, unsigned int, char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xrep_parent_replay_parentadd)(void *, struct xfs_inode *, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xrep_parent_replay_parentremove)(void *, struct xfs_inode *, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xrep_parent_reset_dotdot)(void *, struct xfs_inode *, xfs_ino_t);\n\ntypedef void (*btf_trace_xrep_parent_stash_parentadd)(void *, struct xfs_inode *, const struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xrep_parent_stash_parentremove)(void *, struct xfs_inode *, const struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xrep_parent_stash_xattr)(void *, struct xfs_inode *, unsigned int, char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xrep_refc_found)(void *, const struct xfs_group *, const struct xfs_refcount_irec *);\n\ntypedef void (*btf_trace_xrep_reset_counters)(void *, struct xfs_mount *, struct xchk_fscounters *);\n\ntypedef void (*btf_trace_xrep_rmap_found)(void *, const struct xfs_perag *, const struct xfs_rmap_irec *);\n\ntypedef void (*btf_trace_xrep_rmap_live_update)(void *, const struct xfs_group *, unsigned int, const struct xfs_rmap_update_params *);\n\ntypedef void (*btf_trace_xrep_symlink_rebuild)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xrep_symlink_reset_fork)(void *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xrep_symlink_salvage_target)(void *, struct xfs_inode *, char *, unsigned int);\n\ntypedef void (*btf_trace_xrep_tempfile_copyin)(void *, struct xfs_scrub *, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xrep_tempfile_create)(void *, struct xfs_scrub *);\n\ntypedef void (*btf_trace_xrep_tempfile_prealloc)(void *, struct xfs_scrub *, int, struct xfs_bmbt_irec *);\n\ntypedef void (*btf_trace_xrep_xattr_full_reset)(void *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xrep_xattr_insert_pptr)(void *, struct xfs_inode *, unsigned int, const void *, unsigned int, const void *, unsigned int);\n\ntypedef void (*btf_trace_xrep_xattr_insert_rec)(void *, struct xfs_inode *, unsigned int, char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xrep_xattr_rebuild_tree)(void *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xrep_xattr_recover_leafblock)(void *, struct xfs_inode *, xfs_dablk_t, uint16_t);\n\ntypedef void (*btf_trace_xrep_xattr_replay_parentadd)(void *, struct xfs_inode *, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xrep_xattr_replay_parentremove)(void *, struct xfs_inode *, const struct xfs_name *, const struct xfs_parent_rec *);\n\ntypedef void (*btf_trace_xrep_xattr_reset_fork)(void *, struct xfs_inode *, struct xfs_inode *);\n\ntypedef void (*btf_trace_xrep_xattr_salvage_pptr)(void *, struct xfs_inode *, unsigned int, const void *, unsigned int, const void *, unsigned int);\n\ntypedef void (*btf_trace_xrep_xattr_salvage_rec)(void *, struct xfs_inode *, unsigned int, char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_xrep_xattr_stash_parentadd)(void *, struct xfs_inode *, const struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xrep_xattr_stash_parentremove)(void *, struct xfs_inode *, const struct xfs_inode *, const struct xfs_name *);\n\ntypedef void (*btf_trace_xs_data_ready)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xs_stream_read_data)(void *, struct rpc_xprt *, ssize_t, size_t);\n\ntypedef void (*btf_trace_xs_stream_read_request)(void *, struct sock_xprt *);\n\ntypedef long unsigned int (*callfunc_t)(long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef void (*companion_fn)(struct pci_dev *, struct usb_hcd *, struct pci_dev *, struct usb_hcd *);\n\ntypedef int (*copy_fn_t)(void *, const void *, u32, struct task_struct *);\n\ntypedef void (*crash_shutdown_t)(void);\n\ntypedef void * (*devcon_match_fn_t)(const struct fwnode_handle *, const char *, void *);\n\ntypedef int (*device_iter_t)(struct device *, void *);\n\ntypedef int (*device_match_t)(struct device *, const void *);\n\ntypedef int devlink_chunk_fill_t(void *, u8 *, u32, u64, struct netlink_ext_ack *);\n\ntypedef int devlink_nl_dump_one_func_t(struct sk_buff *, struct devlink *, struct netlink_callback *, int);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\ntypedef int (*dummy_ops_test_ret_fn)(struct bpf_dummy_ops_state *, ...);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\ntypedef void (*eeh_edev_traverse_func)(struct eeh_dev *, void *);\n\ntypedef void * (*eeh_pe_traverse_func)(struct eeh_pe *, void *);\n\ntypedef enum pci_ers_result (*eeh_report_fn)(struct eeh_dev *, struct pci_dev *, struct pci_driver *);\n\ntypedef void (*efi_element_handler_t)(const char *, const void *, size_t);\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const struct ethnl_req_info *);\n\ntypedef void (*exitcall_t)(void);\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\ntypedef void ext4_update_sb_callback(struct ext4_sb_info *, struct ext4_super_block *, const void *);\n\ntypedef int filler_t(struct file *, struct folio *);\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, struct mm_struct *);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\ntypedef void free_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*ftrace_mapper_func)(void *);\n\ntypedef access_mask_t get_access_mask_t(const struct landlock_ruleset * const, const u16);\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\ntypedef bool (*hid_usage_cmp_t)(struct hid_usage *, unsigned int, unsigned int);\n\ntypedef bool (*i8042_filter_t)(unsigned char, unsigned char, struct serio *, void *);\n\ntypedef u32 inet6_ehashfn_t(const struct net *, const struct in6_addr *, const u16, const struct in6_addr *, const __be16);\n\ntypedef u32 inet_ehashfn_t(const struct net *, const __be32, const __u16, const __be32, const __be16);\n\ntypedef initcall_t initcall_entry_t;\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\ntypedef int (*instruction_dump_func)(long unsigned int, long unsigned int);\n\ntypedef int (*ioctl_fn)(struct file *, struct dm_ioctl *, size_t);\n\ntypedef void (*iomap_punch_t)(struct inode *, loff_t, loff_t, struct iomap *);\n\ntypedef size_t (*iov_step_f)(void *, size_t, size_t, void *, void *);\n\ntypedef size_t (*iov_ustep_f)(void *, size_t, size_t, void *, void *);\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *, const struct inet6_skb_parm *);\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef bool (*kunit_resource_match_t)(struct kunit *, struct kunit_resource *, void *);\n\ntypedef int (*list_cmp_func_t)(void *, const struct list_head *, const struct list_head *);\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, void *);\n\ntypedef void (*mapped_f)(struct perf_event *, struct mm_struct *);\n\ntypedef void (*move_fn_t)(struct lruvec *, struct folio *);\n\ntypedef int (*netlink_filter_fn)(struct sock *, struct sk_buff *, void *);\n\ntypedef struct folio *new_folio_t(struct folio *, long unsigned int);\n\ntypedef int (*nlm_host_match_fn_t)(void *, struct nlm_host *);\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\ntypedef int (*objpool_init_obj_cb)(void *, void *);\n\ntypedef void (*online_page_callback_t)(struct page *, unsigned int);\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\ntypedef int (*parse_unknown_fn)(char *, char *, const char *, void *);\n\ntypedef void (*pci_parity_check_fn_t)(struct pci_dev *);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\ntypedef int pcpu_fc_cpu_to_node_fn_t(int);\n\ntypedef void (*perf_irq_t)(struct pt_regs *);\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\ntypedef int perf_snapshot_branch_stack_t(struct perf_branch_entry *, unsigned int);\n\ntypedef int (*platform_irq_probe_t)(struct platform_device *, struct device_node *);\n\ntypedef int (*pm_callback_t)(struct device *);\n\ntypedef struct rt6_info * (*pol_lookup_t)(struct net *, struct fib6_table *, struct flowi6 *, const struct sk_buff *, int);\n\ntypedef int (*pp_nl_fill_cb)(struct sk_buff *, const struct page_pool *, const struct genl_info *);\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\ntypedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\ntypedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\ntypedef int (*reservedmem_of_init_fn)(struct reserved_mem *);\n\ntypedef void (*rethook_handler_t)(struct rethook_node *, void *, long unsigned int, struct pt_regs *);\n\ntypedef bool (*ring_buffer_cond_fn)(void *);\n\ntypedef void (*rpc_action)(struct rpc_task *);\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\ntypedef int (*sendmsg_func)(struct sock *, struct msghdr *);\n\ntypedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);\n\ntypedef int (*set_callee_state_fn)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *, int);\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int);\n\ntypedef void (*swap_r_func_t)(void *, void *, int, const void *);\n\ntypedef long int (*syscall_fn)(const struct pt_regs *);\n\ntypedef int (*task_call_f)(struct task_struct *, void *);\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\ntypedef int (*trace_user_buf_copy)(char *, const char *, size_t, void *);\n\ntypedef struct sk_buff * (*udp_gro_receive_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sock * (*udp_lookup_t)(const struct sk_buff *, __be16, __be16);\n\ntypedef bool (*up_f)(struct tmigr_group *, struct tmigr_group *, struct tmigr_walk *);\n\ntypedef int (*uprobe_write_verify_t)(struct page *, long unsigned int, uprobe_opcode_t *, int, void *);\n\ntypedef void (*visitor128_t)(void *, long unsigned int, u64, u64, size_t);\n\ntypedef void (*visitor32_t)(void *, long unsigned int, u32, size_t);\n\ntypedef void (*visitor64_t)(void *, long unsigned int, u64, size_t);\n\ntypedef void (*visitorl_t)(void *, long unsigned int, long unsigned int, size_t);\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\ntypedef int (*walk_memory_groups_func_t)(struct memory_group *, void *);\n\ntypedef int (*xbitmap32_walk_fn)(uint32_t, uint32_t, void *);\n\ntypedef int (*xbitmap64_walk_fn)(uint64_t, uint64_t, void *);\n\ntypedef int (*xchk_da_btree_rec_fn)(struct xchk_da_btree *, int);\n\ntypedef int (*xchk_dirent_fn)(struct xfs_scrub *, struct xfs_inode *, xfs_dir2_dataptr_t, const struct xfs_name *, xfs_ino_t, void *);\n\ntypedef int (*xchk_xattr_fn)(struct xfs_scrub *, struct xfs_inode *, unsigned int, const unsigned char *, unsigned int, const void *, unsigned int, void *);\n\ntypedef int (*xchk_xattrleaf_fn)(struct xfs_scrub *, void *);\n\ntypedef int (*xfs_agfl_walk_fn)(struct xfs_mount *, xfs_agblock_t, void *);\n\ntypedef int (*xfs_btree_query_range_fn)(struct xfs_btree_cur *, const union xfs_btree_rec *, void *);\n\ntypedef int (*xfs_btree_visit_blocks_fn)(struct xfs_btree_cur *, int, void *);\n\ntypedef struct rpc_xprt * (*xprt_switch_find_xprt_t)(struct rpc_xprt_switch *, const struct rpc_xprt *);\n\ntypedef int (*xrep_tempfile_copyin_fn)(struct xfs_scrub *, struct xfs_buf *, void *);\n\nstruct nf_bridge_frag_data;\n\ntypedef void *acpi_handle;\n\nstruct acpi_device;\n\nstruct bpf_iter;\n\nstruct fscrypt_inode_info;\n\nstruct opal_prd_msg;\n\n\n/* BPF kfuncs */\n#ifndef BPF_NO_KFUNC_PROTOTYPES\nextern void __bpf_trap(void) __weak __ksym;\nextern bool __scx_bpf_dsq_insert_vtime(struct task_struct *p, struct scx_bpf_dsq_insert_vtime_args *args) __weak __ksym;\nextern s32 __scx_bpf_select_cpu_and(struct task_struct *p, const struct cpumask *cpus_allowed, struct scx_bpf_select_cpu_and_args *args) __weak __ksym;\nextern void __attribute__((address_space(1))) *bpf_arena_alloc_pages(void *p__map, void __attribute__((address_space(1))) *addr__ign, u32 page_cnt, int node_id, u64 flags) __weak __ksym;\nextern void bpf_arena_free_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern int bpf_arena_reserve_pages(void *p__map, void __attribute__((address_space(1))) *ptr__ign, u32 page_cnt) __weak __ksym;\nextern __bpf_fastcall void *bpf_cast_to_kern_ctx(void *obj) __weak __ksym;\nextern struct cgroup *bpf_cgroup_acquire(struct cgroup *cgrp) __weak __ksym;\nextern struct cgroup *bpf_cgroup_ancestor(struct cgroup *cgrp, int level) __weak __ksym;\nextern struct cgroup *bpf_cgroup_from_id(u64 cgid) __weak __ksym;\nextern int bpf_cgroup_read_xattr(struct cgroup *cgroup, const char *name__str, struct bpf_dynptr *value_p) __weak __ksym;\nextern void bpf_cgroup_release(struct cgroup *cgrp) __weak __ksym;\nextern int bpf_copy_from_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_copy_from_user_task_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern int bpf_copy_from_user_task_str(void *dst, u32 dst__sz, const void *unsafe_ptr__ign, struct task_struct *tsk, u64 flags) __weak __ksym;\nextern int bpf_copy_from_user_task_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign, struct task_struct *tsk) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_acquire(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_and(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_copy(struct bpf_cpumask *dst, const struct cpumask *src) __weak __ksym;\nextern struct bpf_cpumask *bpf_cpumask_create(void) __weak __ksym;\nextern bool bpf_cpumask_empty(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_equal(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first(const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_first_and(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern u32 bpf_cpumask_first_zero(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_full(const struct cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_intersects(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern void bpf_cpumask_or(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern int bpf_cpumask_populate(struct cpumask *cpumask, void *src, size_t src__sz) __weak __ksym;\nextern void bpf_cpumask_release(struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_setall(struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_subset(const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern bool bpf_cpumask_test_and_clear_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_and_set_cpu(u32 cpu, struct bpf_cpumask *cpumask) __weak __ksym;\nextern bool bpf_cpumask_test_cpu(u32 cpu, const struct cpumask *cpumask) __weak __ksym;\nextern u32 bpf_cpumask_weight(const struct cpumask *cpumask) __weak __ksym;\nextern void bpf_cpumask_xor(struct bpf_cpumask *dst, const struct cpumask *src1, const struct cpumask *src2) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_acquire(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern struct bpf_crypto_ctx *bpf_crypto_ctx_create(const struct bpf_crypto_params *params, u32 params__sz, int *err) __weak __ksym;\nextern void bpf_crypto_ctx_release(struct bpf_crypto_ctx *ctx) __weak __ksym;\nextern int bpf_crypto_decrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_crypto_encrypt(struct bpf_crypto_ctx *ctx, const struct bpf_dynptr *src, const struct bpf_dynptr *dst, const struct bpf_dynptr *siv__nullable) __weak __ksym;\nextern int bpf_dynptr_adjust(const struct bpf_dynptr *p, u64 start, u64 end) __weak __ksym;\nextern int bpf_dynptr_clone(const struct bpf_dynptr *p, struct bpf_dynptr *clone__uninit) __weak __ksym;\nextern int bpf_dynptr_copy(struct bpf_dynptr *dst_ptr, u64 dst_off, struct bpf_dynptr *src_ptr, u64 src_off, u64 size) __weak __ksym;\nextern int bpf_dynptr_file_discard(struct bpf_dynptr *dynptr) __weak __ksym;\nextern int bpf_dynptr_from_file(struct file *file, u32 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb(struct __sk_buff *s, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_skb_meta(struct __sk_buff *skb_, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern int bpf_dynptr_from_xdp(struct xdp_md *x, u64 flags, struct bpf_dynptr *ptr__uninit) __weak __ksym;\nextern bool bpf_dynptr_is_null(const struct bpf_dynptr *p) __weak __ksym;\nextern bool bpf_dynptr_is_rdonly(const struct bpf_dynptr *p) __weak __ksym;\nextern int bpf_dynptr_memset(struct bpf_dynptr *p, u64 offset, u64 size, u8 val) __weak __ksym;\nextern u64 bpf_dynptr_size(const struct bpf_dynptr *p) __weak __ksym;\nextern void *bpf_dynptr_slice(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern void *bpf_dynptr_slice_rdwr(const struct bpf_dynptr *p, u64 offset, void *buffer__nullable, u64 buffer__szk) __weak __ksym;\nextern int bpf_fentry_test1(int a) __weak __ksym;\nextern int bpf_get_dentry_xattr(struct dentry *dentry, const char *name__str, struct bpf_dynptr *value_p) __weak __ksym;\nextern int bpf_get_file_xattr(struct file *file, const char *name__str, struct bpf_dynptr *value_p) __weak __ksym;\nextern struct kmem_cache *bpf_get_kmem_cache(u64 addr) __weak __ksym;\nextern struct mem_cgroup *bpf_get_mem_cgroup(struct cgroup_subsys_state *css) __weak __ksym;\nextern struct mem_cgroup *bpf_get_root_mem_cgroup(void) __weak __ksym;\nextern struct file *bpf_get_task_exe_file(struct task_struct *task) __weak __ksym;\nextern void bpf_iter_bits_destroy(struct bpf_iter_bits *it) __weak __ksym;\nextern int bpf_iter_bits_new(struct bpf_iter_bits *it, const u64 *unsafe_ptr__ign, u32 nr_words) __weak __ksym;\nextern int *bpf_iter_bits_next(struct bpf_iter_bits *it) __weak __ksym;\nextern void bpf_iter_css_destroy(struct bpf_iter_css *it) __weak __ksym;\nextern int bpf_iter_css_new(struct bpf_iter_css *it, struct cgroup_subsys_state *start, unsigned int flags) __weak __ksym;\nextern struct cgroup_subsys_state *bpf_iter_css_next(struct bpf_iter_css *it) __weak __ksym;\nextern void bpf_iter_css_task_destroy(struct bpf_iter_css_task *it) __weak __ksym;\nextern int bpf_iter_css_task_new(struct bpf_iter_css_task *it, struct cgroup_subsys_state *css, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_css_task_next(struct bpf_iter_css_task *it) __weak __ksym;\nextern void bpf_iter_dmabuf_destroy(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern int bpf_iter_dmabuf_new(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern struct dma_buf *bpf_iter_dmabuf_next(struct bpf_iter_dmabuf *it) __weak __ksym;\nextern void bpf_iter_kmem_cache_destroy(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern int bpf_iter_kmem_cache_new(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern struct kmem_cache *bpf_iter_kmem_cache_next(struct bpf_iter_kmem_cache *it) __weak __ksym;\nextern void bpf_iter_num_destroy(struct bpf_iter_num *it) __weak __ksym;\nextern int bpf_iter_num_new(struct bpf_iter_num *it, int start, int end) __weak __ksym;\nextern int *bpf_iter_num_next(struct bpf_iter_num *it) __weak __ksym;\nextern void bpf_iter_scx_dsq_destroy(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern int bpf_iter_scx_dsq_new(struct bpf_iter_scx_dsq *it, u64 dsq_id, u64 flags) __weak __ksym;\nextern struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) __weak __ksym;\nextern void bpf_iter_task_destroy(struct bpf_iter_task *it) __weak __ksym;\nextern int bpf_iter_task_new(struct bpf_iter_task *it, struct task_struct *task__nullable, unsigned int flags) __weak __ksym;\nextern struct task_struct *bpf_iter_task_next(struct bpf_iter_task *it) __weak __ksym;\nextern void bpf_iter_task_vma_destroy(struct bpf_iter_task_vma *it) __weak __ksym;\nextern int bpf_iter_task_vma_new(struct bpf_iter_task_vma *it, struct task_struct *task, u64 addr) __weak __ksym;\nextern struct vm_area_struct *bpf_iter_task_vma_next(struct bpf_iter_task_vma *it) __weak __ksym;\nextern void bpf_key_put(struct bpf_key *bkey) __weak __ksym;\nextern void bpf_kfunc_call_memb_release(struct prog_test_member *p) __weak __ksym;\nextern void bpf_kfunc_call_test_release(struct prog_test_ref_kfunc *p) __weak __ksym;\nextern struct bpf_list_node *bpf_list_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_front(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_back(struct bpf_list_head *head) __weak __ksym;\nextern struct bpf_list_node *bpf_list_pop_front(struct bpf_list_head *head) __weak __ksym;\nextern int bpf_list_push_back_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern int bpf_list_push_front_impl(struct bpf_list_head *head, struct bpf_list_node *node, void *meta__ign, u64 off) __weak __ksym;\nextern void bpf_local_irq_restore(long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_local_irq_save(long unsigned int *flags__irq_flag) __weak __ksym;\nextern struct bpf_key *bpf_lookup_system_key(u64 id) __weak __ksym;\nextern struct bpf_key *bpf_lookup_user_key(s32 serial, u64 flags) __weak __ksym;\nextern s64 bpf_map_sum_elem_count(const struct bpf_map *map) __weak __ksym;\nextern void bpf_mem_cgroup_flush_stats(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_memory_events(struct mem_cgroup *memcg, enum memcg_memory_event event) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_page_state(struct mem_cgroup *memcg, int idx) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_usage(struct mem_cgroup *memcg) __weak __ksym;\nextern long unsigned int bpf_mem_cgroup_vm_events(struct mem_cgroup *memcg, enum vm_event_item event) __weak __ksym;\nextern int bpf_modify_return_test(int a, int *b) __weak __ksym;\nextern int bpf_modify_return_test2(int a, int *b, short int c, int d, void *e, char f, int g) __weak __ksym;\nextern int bpf_modify_return_test_tp(int nonce) __weak __ksym;\nextern void bpf_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern int bpf_path_d_path(const struct path *path, char *buf, size_t buf__sz) __weak __ksym;\nextern void bpf_percpu_obj_drop_impl(void *p__alloc, void *meta__ign) __weak __ksym;\nextern void *bpf_percpu_obj_new_impl(u64 local_type_id__k, void *meta__ign) __weak __ksym;\nextern void bpf_preempt_disable(void) __weak __ksym;\nextern void bpf_preempt_enable(void) __weak __ksym;\nextern int bpf_probe_read_kernel_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_kernel_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern int bpf_probe_read_user_str_dynptr(struct bpf_dynptr *dptr, u64 off, u64 size, const void *unsafe_ptr__ign) __weak __ksym;\nextern void bpf_put_file(struct file *file) __weak __ksym;\nextern void bpf_put_mem_cgroup(struct mem_cgroup *memcg) __weak __ksym;\nextern int bpf_rbtree_add_impl(struct bpf_rb_root *root, struct bpf_rb_node *node, bool (*less)(struct bpf_rb_node *, const struct bpf_rb_node *), void *meta__ign, u64 off) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_first(struct bpf_rb_root *root) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_left(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_remove(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_right(struct bpf_rb_root *root, struct bpf_rb_node *node) __weak __ksym;\nextern struct bpf_rb_node *bpf_rbtree_root(struct bpf_rb_root *root) __weak __ksym;\nextern void bpf_rcu_read_lock(void) __weak __ksym;\nextern void bpf_rcu_read_unlock(void) __weak __ksym;\nextern __bpf_fastcall void *bpf_rdonly_cast(const void *obj__ign, u32 btf_id__k) __weak __ksym;\nextern void *bpf_refcount_acquire_impl(void *p__refcounted_kptr, void *meta__ign) __weak __ksym;\nextern int bpf_remove_dentry_xattr(struct dentry *dentry, const char *name__str) __weak __ksym;\nextern int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __weak __ksym;\nextern void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, long unsigned int *flags__irq_flag) __weak __ksym;\nextern int bpf_send_signal_task(struct task_struct *task, int sig, enum pid_type type, u64 value) __weak __ksym;\nextern __u64 *bpf_session_cookie(void *ctx) __weak __ksym;\nextern bool bpf_session_is_return(void *ctx) __weak __ksym;\nextern int bpf_set_dentry_xattr(struct dentry *dentry, const char *name__str, const struct bpf_dynptr *value_p, int flags) __weak __ksym;\nextern int bpf_sk_assign_tcp_reqsk(struct __sk_buff *s, struct sock *sk, struct bpf_tcp_req_attrs *attrs, int attrs__sz) __weak __ksym;\nextern int bpf_sock_addr_set_sun_path(struct bpf_sock_addr_kern *sa_kern, const u8 *sun_path, u32 sun_path__sz) __weak __ksym;\nextern int bpf_sock_destroy(struct sock_common *sock) __weak __ksym;\nextern int bpf_sock_ops_enable_tx_tstamp(struct bpf_sock_ops_kern *skops, u64 flags) __weak __ksym;\nextern int bpf_strcasecmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcasestr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strchr(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strchrnul(const char *s__ign, char c) __weak __ksym;\nextern int bpf_strcmp(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern int bpf_strcspn(const char *s__ign, const char *reject__ign) __weak __ksym;\nextern int bpf_stream_print_stack(int stream_id) __weak __ksym;\nextern int bpf_stream_vprintk(int stream_id, const char *fmt__str, const void *args, u32 len__sz) __weak __ksym;\nextern int bpf_strlen(const char *s__ign) __weak __ksym;\nextern int bpf_strncasecmp(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strncasestr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strnchr(const char *s__ign, size_t count, char c) __weak __ksym;\nextern int bpf_strnlen(const char *s__ign, size_t count) __weak __ksym;\nextern int bpf_strnstr(const char *s1__ign, const char *s2__ign, size_t len) __weak __ksym;\nextern int bpf_strrchr(const char *s__ign, int c) __weak __ksym;\nextern int bpf_strspn(const char *s__ign, const char *accept__ign) __weak __ksym;\nextern int bpf_strstr(const char *s1__ign, const char *s2__ign) __weak __ksym;\nextern struct task_struct *bpf_task_acquire(struct task_struct *p) __weak __ksym;\nextern struct task_struct *bpf_task_from_pid(s32 pid) __weak __ksym;\nextern struct task_struct *bpf_task_from_vpid(s32 vpid) __weak __ksym;\nextern struct cgroup *bpf_task_get_cgroup1(struct task_struct *task, int hierarchy_id) __weak __ksym;\nextern void bpf_task_release(struct task_struct *p) __weak __ksym;\nextern long int bpf_task_under_cgroup(struct task_struct *task, struct cgroup *ancestor) __weak __ksym;\nextern int bpf_task_work_schedule_resume(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern int bpf_task_work_schedule_signal(struct task_struct *task, struct bpf_task_work *tw, void *map__map, bpf_task_work_callback_t callback) __weak __ksym;\nextern void bpf_throw(u64 cookie) __weak __ksym;\nextern int bpf_timer_cancel_async(struct bpf_timer *timer) __weak __ksym;\nextern int bpf_verify_pkcs7_signature(struct bpf_dynptr *data_p, struct bpf_dynptr *sig_p, struct bpf_key *trusted_keyring) __weak __ksym;\nextern int bpf_wq_init(struct bpf_wq *wq, void *p__map, unsigned int flags) __weak __ksym;\nextern int bpf_wq_set_callback(struct bpf_wq *wq, int (*callback_fn)(void *, int *, void *), unsigned int flags) __weak __ksym;\nextern int bpf_wq_start(struct bpf_wq *wq, unsigned int flags) __weak __ksym;\nextern struct xfrm_state *bpf_xdp_get_xfrm_state(struct xdp_md *ctx, struct bpf_xfrm_state_opts *opts, u32 opts__sz) __weak __ksym;\nextern int bpf_xdp_metadata_rx_hash(const struct xdp_md *ctx, u32 *hash, enum xdp_rss_hash_type *rss_type) __weak __ksym;\nextern int bpf_xdp_metadata_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp) __weak __ksym;\nextern int bpf_xdp_metadata_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto, u16 *vlan_tci) __weak __ksym;\nextern int bpf_xdp_pull_data(struct xdp_md *x, u32 len) __weak __ksym;\nextern void bpf_xdp_xfrm_state_release(struct xfrm_state *x) __weak __ksym;\nextern void crash_kexec(struct pt_regs *regs) __weak __ksym;\nextern void css_rstat_flush(struct cgroup_subsys_state *css) __weak __ksym;\nextern void css_rstat_updated(struct cgroup_subsys_state *css, int cpu) __weak __ksym;\nextern void cubictcp_acked(struct sock *sk, const struct ack_sample *sample) __weak __ksym;\nextern void cubictcp_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern void cubictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) __weak __ksym;\nextern void cubictcp_init(struct sock *sk) __weak __ksym;\nextern u32 cubictcp_recalc_ssthresh(struct sock *sk) __weak __ksym;\nextern void cubictcp_state(struct sock *sk, u8 new_state) __weak __ksym;\nextern struct task_struct *scx_bpf_cpu_curr(s32 cpu) __weak __ksym;\nextern s32 scx_bpf_cpu_node(s32 cpu) __weak __ksym;\nextern struct rq *scx_bpf_cpu_rq(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cap(s32 cpu) __weak __ksym;\nextern u32 scx_bpf_cpuperf_cur(s32 cpu) __weak __ksym;\nextern void scx_bpf_cpuperf_set(s32 cpu, u32 perf) __weak __ksym;\nextern s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) __weak __ksym;\nextern void scx_bpf_destroy_dsq(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dispatch_cancel(void) __weak __ksym;\nextern u32 scx_bpf_dispatch_nr_slots(void) __weak __ksym;\nextern void scx_bpf_dsq_insert(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_insert___v2(struct task_struct *p, u64 dsq_id, u64 slice, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_insert_vtime(struct task_struct *p, u64 dsq_id, u64 slice, u64 vtime, u64 enq_flags) __weak __ksym;\nextern bool scx_bpf_dsq_move(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern void scx_bpf_dsq_move_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __weak __ksym;\nextern void scx_bpf_dsq_move_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __weak __ksym;\nextern bool scx_bpf_dsq_move_to_local(u64 dsq_id) __weak __ksym;\nextern bool scx_bpf_dsq_move_vtime(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __weak __ksym;\nextern s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __weak __ksym;\nextern struct task_struct *scx_bpf_dsq_peek(u64 dsq_id) __weak __ksym;\nextern void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags) __weak __ksym;\nextern void scx_bpf_dump_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_error_bstr(char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __weak __ksym;\nextern void scx_bpf_exit_bstr(s64 exit_code, char *fmt, long long unsigned int *data, u32 data__sz) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_cpumask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_idle_smtmask_node(s32 node) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_online_cpumask(void) __weak __ksym;\nextern const struct cpumask *scx_bpf_get_possible_cpumask(void) __weak __ksym;\nextern void scx_bpf_kick_cpu(s32 cpu, u64 flags) __weak __ksym;\nextern struct rq *scx_bpf_locked_rq(void) __weak __ksym;\nextern u64 scx_bpf_now(void) __weak __ksym;\nextern u32 scx_bpf_nr_cpu_ids(void) __weak __ksym;\nextern u32 scx_bpf_nr_node_ids(void) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_any_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu(const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_pick_idle_cpu_node(const struct cpumask *cpus_allowed, s32 node, u64 flags) __weak __ksym;\nextern void scx_bpf_put_cpumask(const struct cpumask *cpumask) __weak __ksym;\nextern void scx_bpf_put_idle_cpumask(const struct cpumask *idle_mask) __weak __ksym;\nextern u32 scx_bpf_reenqueue_local(void) __weak __ksym;\nextern void scx_bpf_reenqueue_local___v2(void) __weak __ksym;\nextern s32 scx_bpf_select_cpu_and(struct task_struct *p, s32 prev_cpu, u64 wake_flags, const struct cpumask *cpus_allowed, u64 flags) __weak __ksym;\nextern s32 scx_bpf_select_cpu_dfl(struct task_struct *p, s32 prev_cpu, u64 wake_flags, bool *is_idle) __weak __ksym;\nextern bool scx_bpf_sub_dispatch(u64 cgroup_id) __weak __ksym;\nextern struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __weak __ksym;\nextern s32 scx_bpf_task_cpu(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_running(const struct task_struct *p) __weak __ksym;\nextern bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime) __weak __ksym;\nextern bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice) __weak __ksym;\nextern bool scx_bpf_test_and_clear_cpu_idle(s32 cpu) __weak __ksym;\nextern void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked) __weak __ksym;\nextern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked) __weak __ksym;\nextern u32 tcp_reno_ssthresh(struct sock *sk) __weak __ksym;\nextern u32 tcp_reno_undo_cwnd(struct sock *sk) __weak __ksym;\nextern u32 tcp_slow_start(struct tcp_sock *tp, u32 acked) __weak __ksym;\n#endif\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n#pragma clang diagnostic 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fn install_bpf_h<P: AsRef<Path>>(dest: P) -> Result<()>

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fn determine_cflags<P>(clang: &ClangInfo, out_dir: P) -> Result<Vec<String>>
where P: AsRef<Path> + Debug,

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pub fn new() -> Result<Self>

Create a new BpfBuilder struct. Call enable and set methods to configure and build method to compile and generate bindings. See the struct documentation for details.

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pub fn enable_intf(&mut self, input: &str, output: &str) -> &mut Self

Enable generation of header bindings using bindgen. @input is the .h file defining the constants and types to be shared between BPF and Rust components. @output is the .rs file to be generated.

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pub fn enable_skel(&mut self, input: &str, name: &str) -> &mut Self

Enable compilation of BPF code and generation of the skeleton and its Rust bindings. @input is the .bpf.c file containing the BPF source code and @output is the .rs file to be generated.

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fn input_insert_deps(&self, deps: &mut BTreeSet<String>)

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fn bindgen_bpf_intf(&self) -> Result<()>

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pub fn add_source(&mut self, input: &str) -> &mut Self

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fn gen_bpf_skel(&self, deps: &mut BTreeSet<String>) -> Result<()>

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fn add_src_deps(&self, deps: &mut BTreeSet<String>, input: &str) -> Result<()>

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fn gen_cargo_reruns( &self, dependencies: Option<&BTreeSet<String>>, ) -> Result<()>

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pub fn build(&self) -> Result<()>

Build and generate the enabled bindings.

Trait Implementations§

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impl Debug for BpfBuilder

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T> Instrument for T

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fn instrument(self, span: Span) -> Instrumented<Self>

Instruments this type with the provided [Span], returning an Instrumented wrapper. Read more
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fn in_current_span(self) -> Instrumented<Self>

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> IntoEither for T

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fn into_either(self, into_left: bool) -> Either<Self, Self>

Converts self into a Left variant of Either<Self, Self> if into_left is true. Converts self into a Right variant of Either<Self, Self> otherwise. Read more
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fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
where F: FnOnce(&Self) -> bool,

Converts self into a Left variant of Either<Self, Self> if into_left(&self) returns true. Converts self into a Right variant of Either<Self, Self> otherwise. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.
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impl<T> WithSubscriber for T

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fn with_subscriber<S>(self, subscriber: S) -> WithDispatch<Self>
where S: Into<Dispatch>,

Attaches the provided Subscriber to this type, returning a [WithDispatch] wrapper. Read more
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fn with_current_subscriber(self) -> WithDispatch<Self>

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